diff --git a/esp32p4/build.rs b/esp32p4/build.rs new file mode 100644 index 0000000000..d0781acdb6 --- /dev/null +++ b/esp32p4/build.rs @@ -0,0 +1,17 @@ +#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/esp32p4/device.x b/esp32p4/device.x new file mode 100644 index 0000000000..770868f421 --- /dev/null +++ b/esp32p4/device.x @@ -0,0 +1,80 @@ +PROVIDE(LP_WDT = DefaultHandler); +PROVIDE(LP_TIMER0 = DefaultHandler); +PROVIDE(LP_TIMER1 = DefaultHandler); +PROVIDE(PMU0 = DefaultHandler); +PROVIDE(PMU1 = DefaultHandler); +PROVIDE(LP_ANA = DefaultHandler); +PROVIDE(LP_ADC = DefaultHandler); +PROVIDE(LP_GPIO = DefaultHandler); +PROVIDE(LP_I2C0 = DefaultHandler); +PROVIDE(LP_I2S0 = DefaultHandler); +PROVIDE(LP_TOUCH = DefaultHandler); +PROVIDE(LP_TSENS = DefaultHandler); +PROVIDE(LP_UART = DefaultHandler); +PROVIDE(LP_SYS = DefaultHandler); +PROVIDE(LP_HUK = DefaultHandler); +PROVIDE(USB_DEVICE = DefaultHandler); +PROVIDE(DMA = DefaultHandler); +PROVIDE(SPI2 = DefaultHandler); +PROVIDE(SPI3 = DefaultHandler); +PROVIDE(I2S0 = DefaultHandler); +PROVIDE(I2S1 = DefaultHandler); +PROVIDE(I2S2 = DefaultHandler); +PROVIDE(UHCI0 = DefaultHandler); +PROVIDE(UART0 = DefaultHandler); +PROVIDE(PWM0 = DefaultHandler); +PROVIDE(PWM1 = DefaultHandler); +PROVIDE(TWAI0 = DefaultHandler); +PROVIDE(TWAI1 = DefaultHandler); +PROVIDE(TWAI2 = DefaultHandler); +PROVIDE(RMT = DefaultHandler); +PROVIDE(I2C0 = DefaultHandler); +PROVIDE(I2C1 = DefaultHandler); +PROVIDE(TG0_T0 = DefaultHandler); +PROVIDE(TG0_T1 = DefaultHandler); +PROVIDE(TG0_WDT = DefaultHandler); +PROVIDE(TG1_T0 = DefaultHandler); +PROVIDE(TG1_T1 = DefaultHandler); +PROVIDE(TG1_WDT = DefaultHandler); +PROVIDE(LEDC = DefaultHandler); +PROVIDE(SYSTIMER_TARGET0 = DefaultHandler); +PROVIDE(SYSTIMER_TARGET1 = DefaultHandler); +PROVIDE(SYSTIMER_TARGET2 = DefaultHandler); +PROVIDE(RSA = DefaultHandler); +PROVIDE(AES = DefaultHandler); +PROVIDE(SHA = DefaultHandler); +PROVIDE(ECC = DefaultHandler); +PROVIDE(GPIO_INT0 = DefaultHandler); +PROVIDE(GPIO_INT1 = DefaultHandler); +PROVIDE(GPIO_INT2 = DefaultHandler); +PROVIDE(GPIO_INT3 = DefaultHandler); +PROVIDE(GPIO_PAD_COMP = DefaultHandler); +PROVIDE(CACHE = DefaultHandler); +PROVIDE(CSI_BRIDGE = DefaultHandler); +PROVIDE(DSI_BRIDGE = DefaultHandler); +PROVIDE(CSI = DefaultHandler); +PROVIDE(DSI = DefaultHandler); +PROVIDE(JPEG = DefaultHandler); +PROVIDE(PPA = DefaultHandler); +PROVIDE(ISP = DefaultHandler); +PROVIDE(I3C = DefaultHandler); +PROVIDE(I3C_SLV = DefaultHandler); +PROVIDE(HP_SYS = DefaultHandler); +PROVIDE(PCNT = DefaultHandler); +PROVIDE(PAU = DefaultHandler); +PROVIDE(PARLIO_RX = DefaultHandler); +PROVIDE(PARLIO_TX = DefaultHandler); +PROVIDE(H264_DMA2D_OUT_CH0 = DefaultHandler); +PROVIDE(H264_DMA2D_OUT_CH1 = DefaultHandler); +PROVIDE(H264_DMA2D_OUT_CH2 = DefaultHandler); +PROVIDE(H264_DMA2D_OUT_CH3 = DefaultHandler); +PROVIDE(H264_DMA2D_OUT_CH4 = DefaultHandler); +PROVIDE(H264_DMA2D_IN_CH0 = DefaultHandler); +PROVIDE(H264_DMA2D_IN_CH1 = DefaultHandler); +PROVIDE(H264_DMA2D_IN_CH2 = DefaultHandler); +PROVIDE(H264_DMA2D_IN_CH3 = DefaultHandler); +PROVIDE(H264_DMA2D_IN_CH4 = DefaultHandler); +PROVIDE(H264_DMA2D_IN_CH5 = DefaultHandler); +PROVIDE(H264_REG = DefaultHandler); +PROVIDE(ASSIST_DEBUG = DefaultHandler); + diff --git a/esp32p4/src/adc.rs b/esp32p4/src/adc.rs new file mode 100644 index 0000000000..e0c1d77d46 --- /dev/null +++ b/esp32p4/src/adc.rs @@ -0,0 +1,318 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + ctrl: CTRL, + ctrl2: CTRL2, + filter_ctrl1: FILTER_CTRL1, + fsm_wait: FSM_WAIT, + sar1_status: SAR1_STATUS, + sar2_status: SAR2_STATUS, + sar1_patt_tab1: SAR1_PATT_TAB1, + sar1_patt_tab2: SAR1_PATT_TAB2, + sar1_patt_tab3: SAR1_PATT_TAB3, + sar1_patt_tab4: SAR1_PATT_TAB4, + sar2_patt_tab1: SAR2_PATT_TAB1, + sar2_patt_tab2: SAR2_PATT_TAB2, + sar2_patt_tab3: SAR2_PATT_TAB3, + sar2_patt_tab4: SAR2_PATT_TAB4, + arb_ctrl: ARB_CTRL, + filter_ctrl0: FILTER_CTRL0, + sar1_data_status: SAR1_DATA_STATUS, + thres0_ctrl: THRES0_CTRL, + thres1_ctrl: THRES1_CTRL, + thres_ctrl: THRES_CTRL, + int_ena: INT_ENA, + int_raw: INT_RAW, + int_st: INT_ST, + int_clr: INT_CLR, + dma_conf: DMA_CONF, + sar2_data_status: SAR2_DATA_STATUS, + cali: CALI, + rnd_eco_low: RND_ECO_LOW, + rnd_eco_high: RND_ECO_HIGH, + rnd_eco_cs: RND_ECO_CS, + _reserved30: [u8; 0x0384], + ctrl_date: CTRL_DATE, +} +impl RegisterBlock { + #[doc = "0x00 - Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0x04 - Register"] + #[inline(always)] + pub const fn ctrl2(&self) -> &CTRL2 { + &self.ctrl2 + } + #[doc = "0x08 - Register"] + #[inline(always)] + pub const fn filter_ctrl1(&self) -> &FILTER_CTRL1 { + &self.filter_ctrl1 + } + #[doc = "0x0c - Register"] + #[inline(always)] + pub const fn fsm_wait(&self) -> &FSM_WAIT { + &self.fsm_wait + } + #[doc = "0x10 - Register"] + #[inline(always)] + pub const fn sar1_status(&self) -> &SAR1_STATUS { + &self.sar1_status + } + #[doc = "0x14 - Register"] + #[inline(always)] + pub const fn sar2_status(&self) -> &SAR2_STATUS { + &self.sar2_status + } + #[doc = "0x18 - Register"] + #[inline(always)] + pub const fn sar1_patt_tab1(&self) -> &SAR1_PATT_TAB1 { + &self.sar1_patt_tab1 + } + #[doc = "0x1c - Register"] + #[inline(always)] + pub const fn sar1_patt_tab2(&self) -> &SAR1_PATT_TAB2 { + &self.sar1_patt_tab2 + } + #[doc = "0x20 - Register"] + #[inline(always)] + pub const fn sar1_patt_tab3(&self) -> &SAR1_PATT_TAB3 { + &self.sar1_patt_tab3 + } + #[doc = "0x24 - Register"] + #[inline(always)] + pub const fn sar1_patt_tab4(&self) -> &SAR1_PATT_TAB4 { + &self.sar1_patt_tab4 + } + #[doc = "0x28 - Register"] + #[inline(always)] + pub const fn sar2_patt_tab1(&self) -> &SAR2_PATT_TAB1 { + &self.sar2_patt_tab1 + } + #[doc = "0x2c - Register"] + #[inline(always)] + pub const fn sar2_patt_tab2(&self) -> &SAR2_PATT_TAB2 { + &self.sar2_patt_tab2 + } + #[doc = "0x30 - Register"] + #[inline(always)] + pub const fn sar2_patt_tab3(&self) -> &SAR2_PATT_TAB3 { + &self.sar2_patt_tab3 + } + #[doc = "0x34 - Register"] + #[inline(always)] + pub const fn sar2_patt_tab4(&self) -> &SAR2_PATT_TAB4 { + &self.sar2_patt_tab4 + } + #[doc = "0x38 - Register"] + #[inline(always)] + pub const fn arb_ctrl(&self) -> &ARB_CTRL { + &self.arb_ctrl + } + #[doc = "0x3c - Register"] + #[inline(always)] + pub const fn filter_ctrl0(&self) -> &FILTER_CTRL0 { + &self.filter_ctrl0 + } + #[doc = "0x40 - Register"] + #[inline(always)] + pub const fn sar1_data_status(&self) -> &SAR1_DATA_STATUS { + &self.sar1_data_status + } + #[doc = "0x44 - Register"] + #[inline(always)] + pub const fn thres0_ctrl(&self) -> &THRES0_CTRL { + &self.thres0_ctrl + } + #[doc = "0x48 - Register"] + #[inline(always)] + pub const fn thres1_ctrl(&self) -> &THRES1_CTRL { + &self.thres1_ctrl + } + #[doc = "0x4c - Register"] + #[inline(always)] + pub const fn thres_ctrl(&self) -> &THRES_CTRL { + &self.thres_ctrl + } + #[doc = "0x50 - Register"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x54 - Register"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x58 - Register"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x5c - Register"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x60 - Register"] + #[inline(always)] + pub const fn dma_conf(&self) -> &DMA_CONF { + &self.dma_conf + } + #[doc = "0x64 - Register"] + #[inline(always)] + pub const fn sar2_data_status(&self) -> &SAR2_DATA_STATUS { + &self.sar2_data_status + } + #[doc = "0x68 - Register"] + #[inline(always)] + pub const fn cali(&self) -> &CALI { + &self.cali + } + #[doc = "0x6c - Register"] + #[inline(always)] + pub const fn rnd_eco_low(&self) -> &RND_ECO_LOW { + &self.rnd_eco_low + } + #[doc = "0x70 - Register"] + #[inline(always)] + pub const fn rnd_eco_high(&self) -> &RND_ECO_HIGH { + &self.rnd_eco_high + } + #[doc = "0x74 - Register"] + #[inline(always)] + pub const fn rnd_eco_cs(&self) -> &RND_ECO_CS { + &self.rnd_eco_cs + } + #[doc = "0x3fc - Register"] + #[inline(always)] + pub const fn ctrl_date(&self) -> &CTRL_DATE { + &self.ctrl_date + } +} +#[doc = "CTRL (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +pub type CTRL = crate::Reg; +#[doc = "Register"] +pub mod ctrl; +#[doc = "CTRL2 (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2`] module"] +pub type CTRL2 = crate::Reg; +#[doc = "Register"] +pub mod ctrl2; +#[doc = "FILTER_CTRL1 (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_ctrl1`] module"] +pub type FILTER_CTRL1 = crate::Reg; +#[doc = "Register"] +pub mod filter_ctrl1; +#[doc = "FSM_WAIT (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_wait::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsm_wait::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsm_wait`] module"] +pub type FSM_WAIT = crate::Reg; +#[doc = "Register"] +pub mod fsm_wait; +#[doc = "SAR1_STATUS (r) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_status`] module"] +pub type SAR1_STATUS = crate::Reg; +#[doc = "Register"] +pub mod sar1_status; +#[doc = "SAR2_STATUS (r) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_status`] module"] +pub type SAR2_STATUS = crate::Reg; +#[doc = "Register"] +pub mod sar2_status; +#[doc = "SAR1_PATT_TAB1 (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_patt_tab1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar1_patt_tab1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_patt_tab1`] module"] +pub type SAR1_PATT_TAB1 = crate::Reg; +#[doc = "Register"] +pub mod sar1_patt_tab1; +#[doc = "SAR1_PATT_TAB2 (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_patt_tab2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar1_patt_tab2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_patt_tab2`] module"] +pub type SAR1_PATT_TAB2 = crate::Reg; +#[doc = "Register"] +pub mod sar1_patt_tab2; +#[doc = "SAR1_PATT_TAB3 (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_patt_tab3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar1_patt_tab3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_patt_tab3`] module"] +pub type SAR1_PATT_TAB3 = crate::Reg; +#[doc = "Register"] +pub mod sar1_patt_tab3; +#[doc = "SAR1_PATT_TAB4 (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_patt_tab4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar1_patt_tab4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_patt_tab4`] module"] +pub type SAR1_PATT_TAB4 = crate::Reg; +#[doc = "Register"] +pub mod sar1_patt_tab4; +#[doc = "SAR2_PATT_TAB1 (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_patt_tab1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar2_patt_tab1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_patt_tab1`] module"] +pub type SAR2_PATT_TAB1 = crate::Reg; +#[doc = "Register"] +pub mod sar2_patt_tab1; +#[doc = "SAR2_PATT_TAB2 (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_patt_tab2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar2_patt_tab2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_patt_tab2`] module"] +pub type SAR2_PATT_TAB2 = crate::Reg; +#[doc = "Register"] +pub mod sar2_patt_tab2; +#[doc = "SAR2_PATT_TAB3 (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_patt_tab3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar2_patt_tab3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_patt_tab3`] module"] +pub type SAR2_PATT_TAB3 = crate::Reg; +#[doc = "Register"] +pub mod sar2_patt_tab3; +#[doc = "SAR2_PATT_TAB4 (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_patt_tab4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar2_patt_tab4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_patt_tab4`] module"] +pub type SAR2_PATT_TAB4 = crate::Reg; +#[doc = "Register"] +pub mod sar2_patt_tab4; +#[doc = "ARB_CTRL (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arb_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arb_ctrl`] module"] +pub type ARB_CTRL = crate::Reg; +#[doc = "Register"] +pub mod arb_ctrl; +#[doc = "FILTER_CTRL0 (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_ctrl0`] module"] +pub type FILTER_CTRL0 = crate::Reg; +#[doc = "Register"] +pub mod filter_ctrl0; +#[doc = "SAR1_DATA_STATUS (r) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_data_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_data_status`] module"] +pub type SAR1_DATA_STATUS = crate::Reg; +#[doc = "Register"] +pub mod sar1_data_status; +#[doc = "THRES0_CTRL (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thres0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thres0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thres0_ctrl`] module"] +pub type THRES0_CTRL = crate::Reg; +#[doc = "Register"] +pub mod thres0_ctrl; +#[doc = "THRES1_CTRL (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thres1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thres1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thres1_ctrl`] module"] +pub type THRES1_CTRL = crate::Reg; +#[doc = "Register"] +pub mod thres1_ctrl; +#[doc = "THRES_CTRL (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thres_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thres_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thres_ctrl`] module"] +pub type THRES_CTRL = crate::Reg; +#[doc = "Register"] +pub mod thres_ctrl; +#[doc = "INT_ENA (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Register"] +pub mod int_ena; +#[doc = "INT_RAW (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Register"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Register"] +pub mod int_st; +#[doc = "INT_CLR (w) register accessor: Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Register"] +pub mod int_clr; +#[doc = "DMA_CONF (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_conf`] module"] +pub type DMA_CONF = crate::Reg; +#[doc = "Register"] +pub mod dma_conf; +#[doc = "SAR2_DATA_STATUS (r) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_data_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_data_status`] module"] +pub type SAR2_DATA_STATUS = crate::Reg; +#[doc = "Register"] +pub mod sar2_data_status; +#[doc = "CALI (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cali::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cali::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cali`] module"] +pub type CALI = crate::Reg; +#[doc = "Register"] +pub mod cali; +#[doc = "RND_ECO_LOW (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_low`] module"] +pub type RND_ECO_LOW = crate::Reg; +#[doc = "Register"] +pub mod rnd_eco_low; +#[doc = "RND_ECO_HIGH (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_high`] module"] +pub type RND_ECO_HIGH = crate::Reg; +#[doc = "Register"] +pub mod rnd_eco_high; +#[doc = "RND_ECO_CS (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_cs`] module"] +pub type RND_ECO_CS = crate::Reg; +#[doc = "Register"] +pub mod rnd_eco_cs; +#[doc = "CTRL_DATE (rw) register accessor: Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl_date`] module"] +pub type CTRL_DATE = crate::Reg; +#[doc = "Register"] +pub mod ctrl_date; diff --git a/esp32p4/src/adc/arb_ctrl.rs b/esp32p4/src/adc/arb_ctrl.rs new file mode 100644 index 0000000000..0a7f2c9fbc --- /dev/null +++ b/esp32p4/src/adc/arb_ctrl.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ARB_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `ARB_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ARB_APB_FORCE` reader - adc2 arbiter force to enableapb controller"] +pub type ARB_APB_FORCE_R = crate::BitReader; +#[doc = "Field `ARB_APB_FORCE` writer - adc2 arbiter force to enableapb controller"] +pub type ARB_APB_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARB_RTC_FORCE` reader - adc2 arbiter force to enable rtc controller"] +pub type ARB_RTC_FORCE_R = crate::BitReader; +#[doc = "Field `ARB_RTC_FORCE` writer - adc2 arbiter force to enable rtc controller"] +pub type ARB_RTC_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARB_WIFI_FORCE` reader - adc2 arbiter force to enable wifi controller"] +pub type ARB_WIFI_FORCE_R = crate::BitReader; +#[doc = "Field `ARB_WIFI_FORCE` writer - adc2 arbiter force to enable wifi controller"] +pub type ARB_WIFI_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARB_GRANT_FORCE` reader - adc2 arbiter force grant"] +pub type ARB_GRANT_FORCE_R = crate::BitReader; +#[doc = "Field `ARB_GRANT_FORCE` writer - adc2 arbiter force grant"] +pub type ARB_GRANT_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARB_APB_PRIORITY` reader - Set adc2 arbiterapb priority"] +pub type ARB_APB_PRIORITY_R = crate::FieldReader; +#[doc = "Field `ARB_APB_PRIORITY` writer - Set adc2 arbiterapb priority"] +pub type ARB_APB_PRIORITY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ARB_RTC_PRIORITY` reader - Set adc2 arbiter rtc priority"] +pub type ARB_RTC_PRIORITY_R = crate::FieldReader; +#[doc = "Field `ARB_RTC_PRIORITY` writer - Set adc2 arbiter rtc priority"] +pub type ARB_RTC_PRIORITY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ARB_WIFI_PRIORITY` reader - Set adc2 arbiter wifi priority"] +pub type ARB_WIFI_PRIORITY_R = crate::FieldReader; +#[doc = "Field `ARB_WIFI_PRIORITY` writer - Set adc2 arbiter wifi priority"] +pub type ARB_WIFI_PRIORITY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ARB_FIX_PRIORITY` reader - adc2 arbiter uses fixed priority"] +pub type ARB_FIX_PRIORITY_R = crate::BitReader; +#[doc = "Field `ARB_FIX_PRIORITY` writer - adc2 arbiter uses fixed priority"] +pub type ARB_FIX_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - adc2 arbiter force to enableapb controller"] + #[inline(always)] + pub fn arb_apb_force(&self) -> ARB_APB_FORCE_R { + ARB_APB_FORCE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - adc2 arbiter force to enable rtc controller"] + #[inline(always)] + pub fn arb_rtc_force(&self) -> ARB_RTC_FORCE_R { + ARB_RTC_FORCE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - adc2 arbiter force to enable wifi controller"] + #[inline(always)] + pub fn arb_wifi_force(&self) -> ARB_WIFI_FORCE_R { + ARB_WIFI_FORCE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - adc2 arbiter force grant"] + #[inline(always)] + pub fn arb_grant_force(&self) -> ARB_GRANT_FORCE_R { + ARB_GRANT_FORCE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - Set adc2 arbiterapb priority"] + #[inline(always)] + pub fn arb_apb_priority(&self) -> ARB_APB_PRIORITY_R { + ARB_APB_PRIORITY_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Set adc2 arbiter rtc priority"] + #[inline(always)] + pub fn arb_rtc_priority(&self) -> ARB_RTC_PRIORITY_R { + ARB_RTC_PRIORITY_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Set adc2 arbiter wifi priority"] + #[inline(always)] + pub fn arb_wifi_priority(&self) -> ARB_WIFI_PRIORITY_R { + ARB_WIFI_PRIORITY_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 12 - adc2 arbiter uses fixed priority"] + #[inline(always)] + pub fn arb_fix_priority(&self) -> ARB_FIX_PRIORITY_R { + ARB_FIX_PRIORITY_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARB_CTRL") + .field( + "arb_apb_force", + &format_args!("{}", self.arb_apb_force().bit()), + ) + .field( + "arb_rtc_force", + &format_args!("{}", self.arb_rtc_force().bit()), + ) + .field( + "arb_wifi_force", + &format_args!("{}", self.arb_wifi_force().bit()), + ) + .field( + "arb_grant_force", + &format_args!("{}", self.arb_grant_force().bit()), + ) + .field( + "arb_apb_priority", + &format_args!("{}", self.arb_apb_priority().bits()), + ) + .field( + "arb_rtc_priority", + &format_args!("{}", self.arb_rtc_priority().bits()), + ) + .field( + "arb_wifi_priority", + &format_args!("{}", self.arb_wifi_priority().bits()), + ) + .field( + "arb_fix_priority", + &format_args!("{}", self.arb_fix_priority().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 2 - adc2 arbiter force to enableapb controller"] + #[inline(always)] + #[must_use] + pub fn arb_apb_force(&mut self) -> ARB_APB_FORCE_W { + ARB_APB_FORCE_W::new(self, 2) + } + #[doc = "Bit 3 - adc2 arbiter force to enable rtc controller"] + #[inline(always)] + #[must_use] + pub fn arb_rtc_force(&mut self) -> ARB_RTC_FORCE_W { + ARB_RTC_FORCE_W::new(self, 3) + } + #[doc = "Bit 4 - adc2 arbiter force to enable wifi controller"] + #[inline(always)] + #[must_use] + pub fn arb_wifi_force(&mut self) -> ARB_WIFI_FORCE_W { + ARB_WIFI_FORCE_W::new(self, 4) + } + #[doc = "Bit 5 - adc2 arbiter force grant"] + #[inline(always)] + #[must_use] + pub fn arb_grant_force(&mut self) -> ARB_GRANT_FORCE_W { + ARB_GRANT_FORCE_W::new(self, 5) + } + #[doc = "Bits 6:7 - Set adc2 arbiterapb priority"] + #[inline(always)] + #[must_use] + pub fn arb_apb_priority(&mut self) -> ARB_APB_PRIORITY_W { + ARB_APB_PRIORITY_W::new(self, 6) + } + #[doc = "Bits 8:9 - Set adc2 arbiter rtc priority"] + #[inline(always)] + #[must_use] + pub fn arb_rtc_priority(&mut self) -> ARB_RTC_PRIORITY_W { + ARB_RTC_PRIORITY_W::new(self, 8) + } + #[doc = "Bits 10:11 - Set adc2 arbiter wifi priority"] + #[inline(always)] + #[must_use] + pub fn arb_wifi_priority(&mut self) -> ARB_WIFI_PRIORITY_W { + ARB_WIFI_PRIORITY_W::new(self, 10) + } + #[doc = "Bit 12 - adc2 arbiter uses fixed priority"] + #[inline(always)] + #[must_use] + pub fn arb_fix_priority(&mut self) -> ARB_FIX_PRIORITY_W { + ARB_FIX_PRIORITY_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arb_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ARB_CTRL_SPEC; +impl crate::RegisterSpec for ARB_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`arb_ctrl::R`](R) reader structure"] +impl crate::Readable for ARB_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`arb_ctrl::W`](W) writer structure"] +impl crate::Writable for ARB_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ARB_CTRL to value 0x0900"] +impl crate::Resettable for ARB_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0900; +} diff --git a/esp32p4/src/adc/cali.rs b/esp32p4/src/adc/cali.rs new file mode 100644 index 0000000000..b70c3d6e36 --- /dev/null +++ b/esp32p4/src/adc/cali.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CALI` reader"] +pub type R = crate::R; +#[doc = "Register `CALI` writer"] +pub type W = crate::W; +#[doc = "Field `CFG` reader - need_des"] +pub type CFG_R = crate::FieldReader; +#[doc = "Field `CFG` writer - need_des"] +pub type CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - need_des"] + #[inline(always)] + pub fn cfg(&self) -> CFG_R { + CFG_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CALI") + .field("cfg", &format_args!("{}", self.cfg().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - need_des"] + #[inline(always)] + #[must_use] + pub fn cfg(&mut self) -> CFG_W { + CFG_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cali::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cali::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CALI_SPEC; +impl crate::RegisterSpec for CALI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cali::R`](R) reader structure"] +impl crate::Readable for CALI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cali::W`](W) writer structure"] +impl crate::Writable for CALI_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CALI to value 0x8000"] +impl crate::Resettable for CALI_SPEC { + const RESET_VALUE: Self::Ux = 0x8000; +} diff --git a/esp32p4/src/adc/ctrl.rs b/esp32p4/src/adc/ctrl.rs new file mode 100644 index 0000000000..5da1796b65 --- /dev/null +++ b/esp32p4/src/adc/ctrl.rs @@ -0,0 +1,317 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `START_FORCE` reader - need_des"] +pub type START_FORCE_R = crate::BitReader; +#[doc = "Field `START_FORCE` writer - need_des"] +pub type START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `START` reader - need_des"] +pub type START_R = crate::BitReader; +#[doc = "Field `START` writer - need_des"] +pub type START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WORK_MODE` reader - 0: single mode, 1: double mode, 2: alternate mode"] +pub type WORK_MODE_R = crate::FieldReader; +#[doc = "Field `WORK_MODE` writer - 0: single mode, 1: double mode, 2: alternate mode"] +pub type WORK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SAR_SEL` reader - 0: SAR1, 1: SAR2, only work for single SAR mode"] +pub type SAR_SEL_R = crate::BitReader; +#[doc = "Field `SAR_SEL` writer - 0: SAR1, 1: SAR2, only work for single SAR mode"] +pub type SAR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_CLK_GATED` reader - need_des"] +pub type SAR_CLK_GATED_R = crate::BitReader; +#[doc = "Field `SAR_CLK_GATED` writer - need_des"] +pub type SAR_CLK_GATED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_CLK_DIV` reader - SAR clock divider"] +pub type SAR_CLK_DIV_R = crate::FieldReader; +#[doc = "Field `SAR_CLK_DIV` writer - SAR clock divider"] +pub type SAR_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SAR1_PATT_LEN` reader - 0 ~ 15 means length 1 ~ 16"] +pub type SAR1_PATT_LEN_R = crate::FieldReader; +#[doc = "Field `SAR1_PATT_LEN` writer - 0 ~ 15 means length 1 ~ 16"] +pub type SAR1_PATT_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SAR2_PATT_LEN` reader - 0 ~ 15 means length 1 ~ 16"] +pub type SAR2_PATT_LEN_R = crate::FieldReader; +#[doc = "Field `SAR2_PATT_LEN` writer - 0 ~ 15 means length 1 ~ 16"] +pub type SAR2_PATT_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SAR1_PATT_P_CLEAR` reader - clear the pointer of pattern table for DIG ADC1 CTRL"] +pub type SAR1_PATT_P_CLEAR_R = crate::BitReader; +#[doc = "Field `SAR1_PATT_P_CLEAR` writer - clear the pointer of pattern table for DIG ADC1 CTRL"] +pub type SAR1_PATT_P_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR2_PATT_P_CLEAR` reader - clear the pointer of pattern table for DIG ADC2 CTRL"] +pub type SAR2_PATT_P_CLEAR_R = crate::BitReader; +#[doc = "Field `SAR2_PATT_P_CLEAR` writer - clear the pointer of pattern table for DIG ADC2 CTRL"] +pub type SAR2_PATT_P_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA_SAR_SEL` reader - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."] +pub type DATA_SAR_SEL_R = crate::BitReader; +#[doc = "Field `DATA_SAR_SEL` writer - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."] +pub type DATA_SAR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA_TO_I2S` reader - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"] +pub type DATA_TO_I2S_R = crate::BitReader; +#[doc = "Field `DATA_TO_I2S` writer - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"] +pub type DATA_TO_I2S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XPD_SAR1_FORCE` reader - force option to xpd sar1 blocks"] +pub type XPD_SAR1_FORCE_R = crate::FieldReader; +#[doc = "Field `XPD_SAR1_FORCE` writer - force option to xpd sar1 blocks"] +pub type XPD_SAR1_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `XPD_SAR2_FORCE` reader - force option to xpd sar2 blocks"] +pub type XPD_SAR2_FORCE_R = crate::FieldReader; +#[doc = "Field `XPD_SAR2_FORCE` writer - force option to xpd sar2 blocks"] +pub type XPD_SAR2_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `WAIT_ARB_CYCLE` reader - wait arbit signal stable after sar_done"] +pub type WAIT_ARB_CYCLE_R = crate::FieldReader; +#[doc = "Field `WAIT_ARB_CYCLE` writer - wait arbit signal stable after sar_done"] +pub type WAIT_ARB_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn start_force(&self) -> START_FORCE_R { + START_FORCE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - 0: single mode, 1: double mode, 2: alternate mode"] + #[inline(always)] + pub fn work_mode(&self) -> WORK_MODE_R { + WORK_MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - 0: SAR1, 1: SAR2, only work for single SAR mode"] + #[inline(always)] + pub fn sar_sel(&self) -> SAR_SEL_R { + SAR_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + pub fn sar_clk_gated(&self) -> SAR_CLK_GATED_R { + SAR_CLK_GATED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:13 - SAR clock divider"] + #[inline(always)] + pub fn sar_clk_div(&self) -> SAR_CLK_DIV_R { + SAR_CLK_DIV_R::new(((self.bits >> 6) & 0xff) as u8) + } + #[doc = "Bits 14:17 - 0 ~ 15 means length 1 ~ 16"] + #[inline(always)] + pub fn sar1_patt_len(&self) -> SAR1_PATT_LEN_R { + SAR1_PATT_LEN_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bits 18:21 - 0 ~ 15 means length 1 ~ 16"] + #[inline(always)] + pub fn sar2_patt_len(&self) -> SAR2_PATT_LEN_R { + SAR2_PATT_LEN_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 22 - clear the pointer of pattern table for DIG ADC1 CTRL"] + #[inline(always)] + pub fn sar1_patt_p_clear(&self) -> SAR1_PATT_P_CLEAR_R { + SAR1_PATT_P_CLEAR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC2 CTRL"] + #[inline(always)] + pub fn sar2_patt_p_clear(&self) -> SAR2_PATT_P_CLEAR_R { + SAR2_PATT_P_CLEAR_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."] + #[inline(always)] + pub fn data_sar_sel(&self) -> DATA_SAR_SEL_R { + DATA_SAR_SEL_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"] + #[inline(always)] + pub fn data_to_i2s(&self) -> DATA_TO_I2S_R { + DATA_TO_I2S_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 26:27 - force option to xpd sar1 blocks"] + #[inline(always)] + pub fn xpd_sar1_force(&self) -> XPD_SAR1_FORCE_R { + XPD_SAR1_FORCE_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - force option to xpd sar2 blocks"] + #[inline(always)] + pub fn xpd_sar2_force(&self) -> XPD_SAR2_FORCE_R { + XPD_SAR2_FORCE_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - wait arbit signal stable after sar_done"] + #[inline(always)] + pub fn wait_arb_cycle(&self) -> WAIT_ARB_CYCLE_R { + WAIT_ARB_CYCLE_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTRL") + .field("start_force", &format_args!("{}", self.start_force().bit())) + .field("start", &format_args!("{}", self.start().bit())) + .field("work_mode", &format_args!("{}", self.work_mode().bits())) + .field("sar_sel", &format_args!("{}", self.sar_sel().bit())) + .field( + "sar_clk_gated", + &format_args!("{}", self.sar_clk_gated().bit()), + ) + .field( + "sar_clk_div", + &format_args!("{}", self.sar_clk_div().bits()), + ) + .field( + "sar1_patt_len", + &format_args!("{}", self.sar1_patt_len().bits()), + ) + .field( + "sar2_patt_len", + &format_args!("{}", self.sar2_patt_len().bits()), + ) + .field( + "sar1_patt_p_clear", + &format_args!("{}", self.sar1_patt_p_clear().bit()), + ) + .field( + "sar2_patt_p_clear", + &format_args!("{}", self.sar2_patt_p_clear().bit()), + ) + .field( + "data_sar_sel", + &format_args!("{}", self.data_sar_sel().bit()), + ) + .field("data_to_i2s", &format_args!("{}", self.data_to_i2s().bit())) + .field( + "xpd_sar1_force", + &format_args!("{}", self.xpd_sar1_force().bits()), + ) + .field( + "xpd_sar2_force", + &format_args!("{}", self.xpd_sar2_force().bits()), + ) + .field( + "wait_arb_cycle", + &format_args!("{}", self.wait_arb_cycle().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn start_force(&mut self) -> START_FORCE_W { + START_FORCE_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> START_W { + START_W::new(self, 1) + } + #[doc = "Bits 2:3 - 0: single mode, 1: double mode, 2: alternate mode"] + #[inline(always)] + #[must_use] + pub fn work_mode(&mut self) -> WORK_MODE_W { + WORK_MODE_W::new(self, 2) + } + #[doc = "Bit 4 - 0: SAR1, 1: SAR2, only work for single SAR mode"] + #[inline(always)] + #[must_use] + pub fn sar_sel(&mut self) -> SAR_SEL_W { + SAR_SEL_W::new(self, 4) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + #[must_use] + pub fn sar_clk_gated(&mut self) -> SAR_CLK_GATED_W { + SAR_CLK_GATED_W::new(self, 5) + } + #[doc = "Bits 6:13 - SAR clock divider"] + #[inline(always)] + #[must_use] + pub fn sar_clk_div(&mut self) -> SAR_CLK_DIV_W { + SAR_CLK_DIV_W::new(self, 6) + } + #[doc = "Bits 14:17 - 0 ~ 15 means length 1 ~ 16"] + #[inline(always)] + #[must_use] + pub fn sar1_patt_len(&mut self) -> SAR1_PATT_LEN_W { + SAR1_PATT_LEN_W::new(self, 14) + } + #[doc = "Bits 18:21 - 0 ~ 15 means length 1 ~ 16"] + #[inline(always)] + #[must_use] + pub fn sar2_patt_len(&mut self) -> SAR2_PATT_LEN_W { + SAR2_PATT_LEN_W::new(self, 18) + } + #[doc = "Bit 22 - clear the pointer of pattern table for DIG ADC1 CTRL"] + #[inline(always)] + #[must_use] + pub fn sar1_patt_p_clear(&mut self) -> SAR1_PATT_P_CLEAR_W { + SAR1_PATT_P_CLEAR_W::new(self, 22) + } + #[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC2 CTRL"] + #[inline(always)] + #[must_use] + pub fn sar2_patt_p_clear(&mut self) -> SAR2_PATT_P_CLEAR_W { + SAR2_PATT_P_CLEAR_W::new(self, 23) + } + #[doc = "Bit 24 - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."] + #[inline(always)] + #[must_use] + pub fn data_sar_sel(&mut self) -> DATA_SAR_SEL_W { + DATA_SAR_SEL_W::new(self, 24) + } + #[doc = "Bit 25 - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"] + #[inline(always)] + #[must_use] + pub fn data_to_i2s(&mut self) -> DATA_TO_I2S_W { + DATA_TO_I2S_W::new(self, 25) + } + #[doc = "Bits 26:27 - force option to xpd sar1 blocks"] + #[inline(always)] + #[must_use] + pub fn xpd_sar1_force(&mut self) -> XPD_SAR1_FORCE_W { + XPD_SAR1_FORCE_W::new(self, 26) + } + #[doc = "Bits 28:29 - force option to xpd sar2 blocks"] + #[inline(always)] + #[must_use] + pub fn xpd_sar2_force(&mut self) -> XPD_SAR2_FORCE_W { + XPD_SAR2_FORCE_W::new(self, 28) + } + #[doc = "Bits 30:31 - wait arbit signal stable after sar_done"] + #[inline(always)] + #[must_use] + pub fn wait_arb_cycle(&mut self) -> WAIT_ARB_CYCLE_W { + WAIT_ARB_CYCLE_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL to value 0x403f_c120"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x403f_c120; +} diff --git a/esp32p4/src/adc/ctrl2.rs b/esp32p4/src/adc/ctrl2.rs new file mode 100644 index 0000000000..60f00ed318 --- /dev/null +++ b/esp32p4/src/adc/ctrl2.rs @@ -0,0 +1,168 @@ +#[doc = "Register `CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `MEAS_NUM_LIMIT` reader - need_des"] +pub type MEAS_NUM_LIMIT_R = crate::BitReader; +#[doc = "Field `MEAS_NUM_LIMIT` writer - need_des"] +pub type MEAS_NUM_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAX_MEAS_NUM` reader - max conversion number"] +pub type MAX_MEAS_NUM_R = crate::FieldReader; +#[doc = "Field `MAX_MEAS_NUM` writer - max conversion number"] +pub type MAX_MEAS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SAR1_INV` reader - 1: data to DIG ADC1 CTRL is inverted, otherwise not"] +pub type SAR1_INV_R = crate::BitReader; +#[doc = "Field `SAR1_INV` writer - 1: data to DIG ADC1 CTRL is inverted, otherwise not"] +pub type SAR1_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR2_INV` reader - 1: data to DIG ADC2 CTRL is inverted, otherwise not"] +pub type SAR2_INV_R = crate::BitReader; +#[doc = "Field `SAR2_INV` writer - 1: data to DIG ADC2 CTRL is inverted, otherwise not"] +pub type SAR2_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_SEL` reader - 1: select saradc timer 0: i2s_ws trigger"] +pub type TIMER_SEL_R = crate::BitReader; +#[doc = "Field `TIMER_SEL` writer - 1: select saradc timer 0: i2s_ws trigger"] +pub type TIMER_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_TARGET` reader - to set saradc timer target"] +pub type TIMER_TARGET_R = crate::FieldReader; +#[doc = "Field `TIMER_TARGET` writer - to set saradc timer target"] +pub type TIMER_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `TIMER_EN` reader - to enable saradc timer trigger"] +pub type TIMER_EN_R = crate::BitReader; +#[doc = "Field `TIMER_EN` writer - to enable saradc timer trigger"] +pub type TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn meas_num_limit(&self) -> MEAS_NUM_LIMIT_R { + MEAS_NUM_LIMIT_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:8 - max conversion number"] + #[inline(always)] + pub fn max_meas_num(&self) -> MAX_MEAS_NUM_R { + MAX_MEAS_NUM_R::new(((self.bits >> 1) & 0xff) as u8) + } + #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not"] + #[inline(always)] + pub fn sar1_inv(&self) -> SAR1_INV_R { + SAR1_INV_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not"] + #[inline(always)] + pub fn sar2_inv(&self) -> SAR2_INV_R { + SAR2_INV_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"] + #[inline(always)] + pub fn timer_sel(&self) -> TIMER_SEL_R { + TIMER_SEL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:23 - to set saradc timer target"] + #[inline(always)] + pub fn timer_target(&self) -> TIMER_TARGET_R { + TIMER_TARGET_R::new(((self.bits >> 12) & 0x0fff) as u16) + } + #[doc = "Bit 24 - to enable saradc timer trigger"] + #[inline(always)] + pub fn timer_en(&self) -> TIMER_EN_R { + TIMER_EN_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTRL2") + .field( + "meas_num_limit", + &format_args!("{}", self.meas_num_limit().bit()), + ) + .field( + "max_meas_num", + &format_args!("{}", self.max_meas_num().bits()), + ) + .field("sar1_inv", &format_args!("{}", self.sar1_inv().bit())) + .field("sar2_inv", &format_args!("{}", self.sar2_inv().bit())) + .field("timer_sel", &format_args!("{}", self.timer_sel().bit())) + .field( + "timer_target", + &format_args!("{}", self.timer_target().bits()), + ) + .field("timer_en", &format_args!("{}", self.timer_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn meas_num_limit(&mut self) -> MEAS_NUM_LIMIT_W { + MEAS_NUM_LIMIT_W::new(self, 0) + } + #[doc = "Bits 1:8 - max conversion number"] + #[inline(always)] + #[must_use] + pub fn max_meas_num(&mut self) -> MAX_MEAS_NUM_W { + MAX_MEAS_NUM_W::new(self, 1) + } + #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not"] + #[inline(always)] + #[must_use] + pub fn sar1_inv(&mut self) -> SAR1_INV_W { + SAR1_INV_W::new(self, 9) + } + #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not"] + #[inline(always)] + #[must_use] + pub fn sar2_inv(&mut self) -> SAR2_INV_W { + SAR2_INV_W::new(self, 10) + } + #[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"] + #[inline(always)] + #[must_use] + pub fn timer_sel(&mut self) -> TIMER_SEL_W { + TIMER_SEL_W::new(self, 11) + } + #[doc = "Bits 12:23 - to set saradc timer target"] + #[inline(always)] + #[must_use] + pub fn timer_target(&mut self) -> TIMER_TARGET_W { + TIMER_TARGET_W::new(self, 12) + } + #[doc = "Bit 24 - to enable saradc timer trigger"] + #[inline(always)] + #[must_use] + pub fn timer_en(&mut self) -> TIMER_EN_W { + TIMER_EN_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL2_SPEC; +impl crate::RegisterSpec for CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"] +impl crate::Readable for CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"] +impl crate::Writable for CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL2 to value 0xa1fe"] +impl crate::Resettable for CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0xa1fe; +} diff --git a/esp32p4/src/adc/ctrl_date.rs b/esp32p4/src/adc/ctrl_date.rs new file mode 100644 index 0000000000..8b8c33975b --- /dev/null +++ b/esp32p4/src/adc/ctrl_date.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CTRL_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `CTRL_DATE` reader - need_des"] +pub type CTRL_DATE_R = crate::FieldReader; +#[doc = "Field `CTRL_DATE` writer - need_des"] +pub type CTRL_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `CLK_EN` reader - need_des"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - need_des"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn ctrl_date(&self) -> CTRL_DATE_R { + CTRL_DATE_R::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTRL_DATE") + .field("ctrl_date", &format_args!("{}", self.ctrl_date().bits())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn ctrl_date(&mut self) -> CTRL_DATE_W { + CTRL_DATE_W::new(self, 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_DATE_SPEC; +impl crate::RegisterSpec for CTRL_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl_date::R`](R) reader structure"] +impl crate::Readable for CTRL_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl_date::W`](W) writer structure"] +impl crate::Writable for CTRL_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL_DATE to value 0x0221_2260"] +impl crate::Resettable for CTRL_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0221_2260; +} diff --git a/esp32p4/src/adc/dma_conf.rs b/esp32p4/src/adc/dma_conf.rs new file mode 100644 index 0000000000..1a7b2d0be7 --- /dev/null +++ b/esp32p4/src/adc/dma_conf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DMA_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `APB_ADC_EOF_NUM` reader - the dma_in_suc_eof gen when sample cnt = spi_eof_num"] +pub type APB_ADC_EOF_NUM_R = crate::FieldReader; +#[doc = "Field `APB_ADC_EOF_NUM` writer - the dma_in_suc_eof gen when sample cnt = spi_eof_num"] +pub type APB_ADC_EOF_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `APB_ADC_RESET_FSM` reader - reset_apb_adc_state"] +pub type APB_ADC_RESET_FSM_R = crate::BitReader; +#[doc = "Field `APB_ADC_RESET_FSM` writer - reset_apb_adc_state"] +pub type APB_ADC_RESET_FSM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB_ADC_TRANS` reader - enable apb_adc use spi_dma"] +pub type APB_ADC_TRANS_R = crate::BitReader; +#[doc = "Field `APB_ADC_TRANS` writer - enable apb_adc use spi_dma"] +pub type APB_ADC_TRANS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"] + #[inline(always)] + pub fn apb_adc_eof_num(&self) -> APB_ADC_EOF_NUM_R { + APB_ADC_EOF_NUM_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 30 - reset_apb_adc_state"] + #[inline(always)] + pub fn apb_adc_reset_fsm(&self) -> APB_ADC_RESET_FSM_R { + APB_ADC_RESET_FSM_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - enable apb_adc use spi_dma"] + #[inline(always)] + pub fn apb_adc_trans(&self) -> APB_ADC_TRANS_R { + APB_ADC_TRANS_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_CONF") + .field( + "apb_adc_eof_num", + &format_args!("{}", self.apb_adc_eof_num().bits()), + ) + .field( + "apb_adc_reset_fsm", + &format_args!("{}", self.apb_adc_reset_fsm().bit()), + ) + .field( + "apb_adc_trans", + &format_args!("{}", self.apb_adc_trans().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"] + #[inline(always)] + #[must_use] + pub fn apb_adc_eof_num(&mut self) -> APB_ADC_EOF_NUM_W { + APB_ADC_EOF_NUM_W::new(self, 0) + } + #[doc = "Bit 30 - reset_apb_adc_state"] + #[inline(always)] + #[must_use] + pub fn apb_adc_reset_fsm(&mut self) -> APB_ADC_RESET_FSM_W { + APB_ADC_RESET_FSM_W::new(self, 30) + } + #[doc = "Bit 31 - enable apb_adc use spi_dma"] + #[inline(always)] + #[must_use] + pub fn apb_adc_trans(&mut self) -> APB_ADC_TRANS_W { + APB_ADC_TRANS_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_CONF_SPEC; +impl crate::RegisterSpec for DMA_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_conf::R`](R) reader structure"] +impl crate::Readable for DMA_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_conf::W`](W) writer structure"] +impl crate::Writable for DMA_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_CONF to value 0xff"] +impl crate::Resettable for DMA_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0xff; +} diff --git a/esp32p4/src/adc/filter_ctrl0.rs b/esp32p4/src/adc/filter_ctrl0.rs new file mode 100644 index 0000000000..fc217c046e --- /dev/null +++ b/esp32p4/src/adc/filter_ctrl0.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FILTER_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `FILTER_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `FILTER_CHANNEL1` reader - need_des"] +pub type FILTER_CHANNEL1_R = crate::FieldReader; +#[doc = "Field `FILTER_CHANNEL1` writer - need_des"] +pub type FILTER_CHANNEL1_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `FILTER_CHANNEL0` reader - apb_adc1_filter_factor"] +pub type FILTER_CHANNEL0_R = crate::FieldReader; +#[doc = "Field `FILTER_CHANNEL0` writer - apb_adc1_filter_factor"] +pub type FILTER_CHANNEL0_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `FILTER_RESET` reader - enable apb_adc1_filter"] +pub type FILTER_RESET_R = crate::BitReader; +#[doc = "Field `FILTER_RESET` writer - enable apb_adc1_filter"] +pub type FILTER_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 14:18 - need_des"] + #[inline(always)] + pub fn filter_channel1(&self) -> FILTER_CHANNEL1_R { + FILTER_CHANNEL1_R::new(((self.bits >> 14) & 0x1f) as u8) + } + #[doc = "Bits 19:23 - apb_adc1_filter_factor"] + #[inline(always)] + pub fn filter_channel0(&self) -> FILTER_CHANNEL0_R { + FILTER_CHANNEL0_R::new(((self.bits >> 19) & 0x1f) as u8) + } + #[doc = "Bit 31 - enable apb_adc1_filter"] + #[inline(always)] + pub fn filter_reset(&self) -> FILTER_RESET_R { + FILTER_RESET_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FILTER_CTRL0") + .field( + "filter_channel1", + &format_args!("{}", self.filter_channel1().bits()), + ) + .field( + "filter_channel0", + &format_args!("{}", self.filter_channel0().bits()), + ) + .field( + "filter_reset", + &format_args!("{}", self.filter_reset().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 14:18 - need_des"] + #[inline(always)] + #[must_use] + pub fn filter_channel1(&mut self) -> FILTER_CHANNEL1_W { + FILTER_CHANNEL1_W::new(self, 14) + } + #[doc = "Bits 19:23 - apb_adc1_filter_factor"] + #[inline(always)] + #[must_use] + pub fn filter_channel0(&mut self) -> FILTER_CHANNEL0_W { + FILTER_CHANNEL0_W::new(self, 19) + } + #[doc = "Bit 31 - enable apb_adc1_filter"] + #[inline(always)] + #[must_use] + pub fn filter_reset(&mut self) -> FILTER_RESET_W { + FILTER_RESET_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FILTER_CTRL0_SPEC; +impl crate::RegisterSpec for FILTER_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`filter_ctrl0::R`](R) reader structure"] +impl crate::Readable for FILTER_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`filter_ctrl0::W`](W) writer structure"] +impl crate::Writable for FILTER_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FILTER_CTRL0 to value 0x006b_4000"] +impl crate::Resettable for FILTER_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0x006b_4000; +} diff --git a/esp32p4/src/adc/filter_ctrl1.rs b/esp32p4/src/adc/filter_ctrl1.rs new file mode 100644 index 0000000000..d38ace7253 --- /dev/null +++ b/esp32p4/src/adc/filter_ctrl1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `FILTER_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `FILTER_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `FILTER_FACTOR1` reader - need_des"] +pub type FILTER_FACTOR1_R = crate::FieldReader; +#[doc = "Field `FILTER_FACTOR1` writer - need_des"] +pub type FILTER_FACTOR1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `FILTER_FACTOR0` reader - need_des"] +pub type FILTER_FACTOR0_R = crate::FieldReader; +#[doc = "Field `FILTER_FACTOR0` writer - need_des"] +pub type FILTER_FACTOR0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 26:28 - need_des"] + #[inline(always)] + pub fn filter_factor1(&self) -> FILTER_FACTOR1_R { + FILTER_FACTOR1_R::new(((self.bits >> 26) & 7) as u8) + } + #[doc = "Bits 29:31 - need_des"] + #[inline(always)] + pub fn filter_factor0(&self) -> FILTER_FACTOR0_R { + FILTER_FACTOR0_R::new(((self.bits >> 29) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FILTER_CTRL1") + .field( + "filter_factor1", + &format_args!("{}", self.filter_factor1().bits()), + ) + .field( + "filter_factor0", + &format_args!("{}", self.filter_factor0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 26:28 - need_des"] + #[inline(always)] + #[must_use] + pub fn filter_factor1(&mut self) -> FILTER_FACTOR1_W { + FILTER_FACTOR1_W::new(self, 26) + } + #[doc = "Bits 29:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn filter_factor0(&mut self) -> FILTER_FACTOR0_W { + FILTER_FACTOR0_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FILTER_CTRL1_SPEC; +impl crate::RegisterSpec for FILTER_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`filter_ctrl1::R`](R) reader structure"] +impl crate::Readable for FILTER_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`filter_ctrl1::W`](W) writer structure"] +impl crate::Writable for FILTER_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FILTER_CTRL1 to value 0"] +impl crate::Resettable for FILTER_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/fsm_wait.rs b/esp32p4/src/adc/fsm_wait.rs new file mode 100644 index 0000000000..2df2672aee --- /dev/null +++ b/esp32p4/src/adc/fsm_wait.rs @@ -0,0 +1,98 @@ +#[doc = "Register `FSM_WAIT` reader"] +pub type R = crate::R; +#[doc = "Register `FSM_WAIT` writer"] +pub type W = crate::W; +#[doc = "Field `XPD_WAIT` reader - need_des"] +pub type XPD_WAIT_R = crate::FieldReader; +#[doc = "Field `XPD_WAIT` writer - need_des"] +pub type XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RSTB_WAIT` reader - need_des"] +pub type RSTB_WAIT_R = crate::FieldReader; +#[doc = "Field `RSTB_WAIT` writer - need_des"] +pub type RSTB_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `STANDBY_WAIT` reader - need_des"] +pub type STANDBY_WAIT_R = crate::FieldReader; +#[doc = "Field `STANDBY_WAIT` writer - need_des"] +pub type STANDBY_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + pub fn xpd_wait(&self) -> XPD_WAIT_R { + XPD_WAIT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - need_des"] + #[inline(always)] + pub fn rstb_wait(&self) -> RSTB_WAIT_R { + RSTB_WAIT_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + pub fn standby_wait(&self) -> STANDBY_WAIT_R { + STANDBY_WAIT_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FSM_WAIT") + .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits())) + .field("rstb_wait", &format_args!("{}", self.rstb_wait().bits())) + .field( + "standby_wait", + &format_args!("{}", self.standby_wait().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + #[must_use] + pub fn xpd_wait(&mut self) -> XPD_WAIT_W { + XPD_WAIT_W::new(self, 0) + } + #[doc = "Bits 8:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn rstb_wait(&mut self) -> RSTB_WAIT_W { + RSTB_WAIT_W::new(self, 8) + } + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + #[must_use] + pub fn standby_wait(&mut self) -> STANDBY_WAIT_W { + STANDBY_WAIT_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_wait::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsm_wait::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FSM_WAIT_SPEC; +impl crate::RegisterSpec for FSM_WAIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fsm_wait::R`](R) reader structure"] +impl crate::Readable for FSM_WAIT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fsm_wait::W`](W) writer structure"] +impl crate::Writable for FSM_WAIT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FSM_WAIT to value 0x00ff_0808"] +impl crate::Resettable for FSM_WAIT_SPEC { + const RESET_VALUE: Self::Ux = 0x00ff_0808; +} diff --git a/esp32p4/src/adc/int_clr.rs b/esp32p4/src/adc/int_clr.rs new file mode 100644 index 0000000000..68ac0ed259 --- /dev/null +++ b/esp32p4/src/adc/int_clr.rs @@ -0,0 +1,82 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `THRES1_LOW_INT_CLR` writer - need_des"] +pub type THRES1_LOW_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES0_LOW_INT_CLR` writer - need_des"] +pub type THRES0_LOW_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES1_HIGH_INT_CLR` writer - need_des"] +pub type THRES1_HIGH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES0_HIGH_INT_CLR` writer - need_des"] +pub type THRES0_HIGH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB_SARADC2_DONE_INT_CLR` writer - need_des"] +pub type APB_SARADC2_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB_SARADC1_DONE_INT_CLR` writer - need_des"] +pub type APB_SARADC1_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres1_low_int_clr(&mut self) -> THRES1_LOW_INT_CLR_W { + THRES1_LOW_INT_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres0_low_int_clr(&mut self) -> THRES0_LOW_INT_CLR_W { + THRES0_LOW_INT_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres1_high_int_clr(&mut self) -> THRES1_HIGH_INT_CLR_W { + THRES1_HIGH_INT_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres0_high_int_clr(&mut self) -> THRES0_HIGH_INT_CLR_W { + THRES0_HIGH_INT_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn apb_saradc2_done_int_clr(&mut self) -> APB_SARADC2_DONE_INT_CLR_W { + APB_SARADC2_DONE_INT_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn apb_saradc1_done_int_clr(&mut self) -> APB_SARADC1_DONE_INT_CLR_W { + APB_SARADC1_DONE_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/int_ena.rs b/esp32p4/src/adc/int_ena.rs new file mode 100644 index 0000000000..96152b68b6 --- /dev/null +++ b/esp32p4/src/adc/int_ena.rs @@ -0,0 +1,161 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `THRES1_LOW_INT_ENA` reader - need_des"] +pub type THRES1_LOW_INT_ENA_R = crate::BitReader; +#[doc = "Field `THRES1_LOW_INT_ENA` writer - need_des"] +pub type THRES1_LOW_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES0_LOW_INT_ENA` reader - need_des"] +pub type THRES0_LOW_INT_ENA_R = crate::BitReader; +#[doc = "Field `THRES0_LOW_INT_ENA` writer - need_des"] +pub type THRES0_LOW_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES1_HIGH_INT_ENA` reader - need_des"] +pub type THRES1_HIGH_INT_ENA_R = crate::BitReader; +#[doc = "Field `THRES1_HIGH_INT_ENA` writer - need_des"] +pub type THRES1_HIGH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES0_HIGH_INT_ENA` reader - need_des"] +pub type THRES0_HIGH_INT_ENA_R = crate::BitReader; +#[doc = "Field `THRES0_HIGH_INT_ENA` writer - need_des"] +pub type THRES0_HIGH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR2_DONE_INT_ENA` reader - need_des"] +pub type SAR2_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SAR2_DONE_INT_ENA` writer - need_des"] +pub type SAR2_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR1_DONE_INT_ENA` reader - need_des"] +pub type SAR1_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SAR1_DONE_INT_ENA` writer - need_des"] +pub type SAR1_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn thres1_low_int_ena(&self) -> THRES1_LOW_INT_ENA_R { + THRES1_LOW_INT_ENA_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn thres0_low_int_ena(&self) -> THRES0_LOW_INT_ENA_R { + THRES0_LOW_INT_ENA_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn thres1_high_int_ena(&self) -> THRES1_HIGH_INT_ENA_R { + THRES1_HIGH_INT_ENA_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn thres0_high_int_ena(&self) -> THRES0_HIGH_INT_ENA_R { + THRES0_HIGH_INT_ENA_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn sar2_done_int_ena(&self) -> SAR2_DONE_INT_ENA_R { + SAR2_DONE_INT_ENA_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn sar1_done_int_ena(&self) -> SAR1_DONE_INT_ENA_R { + SAR1_DONE_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "thres1_low_int_ena", + &format_args!("{}", self.thres1_low_int_ena().bit()), + ) + .field( + "thres0_low_int_ena", + &format_args!("{}", self.thres0_low_int_ena().bit()), + ) + .field( + "thres1_high_int_ena", + &format_args!("{}", self.thres1_high_int_ena().bit()), + ) + .field( + "thres0_high_int_ena", + &format_args!("{}", self.thres0_high_int_ena().bit()), + ) + .field( + "sar2_done_int_ena", + &format_args!("{}", self.sar2_done_int_ena().bit()), + ) + .field( + "sar1_done_int_ena", + &format_args!("{}", self.sar1_done_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres1_low_int_ena(&mut self) -> THRES1_LOW_INT_ENA_W { + THRES1_LOW_INT_ENA_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres0_low_int_ena(&mut self) -> THRES0_LOW_INT_ENA_W { + THRES0_LOW_INT_ENA_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres1_high_int_ena(&mut self) -> THRES1_HIGH_INT_ENA_W { + THRES1_HIGH_INT_ENA_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres0_high_int_ena(&mut self) -> THRES0_HIGH_INT_ENA_W { + THRES0_HIGH_INT_ENA_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn sar2_done_int_ena(&mut self) -> SAR2_DONE_INT_ENA_W { + SAR2_DONE_INT_ENA_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn sar1_done_int_ena(&mut self) -> SAR1_DONE_INT_ENA_W { + SAR1_DONE_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/int_raw.rs b/esp32p4/src/adc/int_raw.rs new file mode 100644 index 0000000000..0377625c2d --- /dev/null +++ b/esp32p4/src/adc/int_raw.rs @@ -0,0 +1,161 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `THRES1_LOW_INT_RAW` reader - need_des"] +pub type THRES1_LOW_INT_RAW_R = crate::BitReader; +#[doc = "Field `THRES1_LOW_INT_RAW` writer - need_des"] +pub type THRES1_LOW_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES0_LOW_INT_RAW` reader - need_des"] +pub type THRES0_LOW_INT_RAW_R = crate::BitReader; +#[doc = "Field `THRES0_LOW_INT_RAW` writer - need_des"] +pub type THRES0_LOW_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES1_HIGH_INT_RAW` reader - need_des"] +pub type THRES1_HIGH_INT_RAW_R = crate::BitReader; +#[doc = "Field `THRES1_HIGH_INT_RAW` writer - need_des"] +pub type THRES1_HIGH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES0_HIGH_INT_RAW` reader - need_des"] +pub type THRES0_HIGH_INT_RAW_R = crate::BitReader; +#[doc = "Field `THRES0_HIGH_INT_RAW` writer - need_des"] +pub type THRES0_HIGH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR2_DONE_INT_RAW` reader - need_des"] +pub type SAR2_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SAR2_DONE_INT_RAW` writer - need_des"] +pub type SAR2_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR1_DONE_INT_RAW` reader - need_des"] +pub type SAR1_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SAR1_DONE_INT_RAW` writer - need_des"] +pub type SAR1_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn thres1_low_int_raw(&self) -> THRES1_LOW_INT_RAW_R { + THRES1_LOW_INT_RAW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn thres0_low_int_raw(&self) -> THRES0_LOW_INT_RAW_R { + THRES0_LOW_INT_RAW_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn thres1_high_int_raw(&self) -> THRES1_HIGH_INT_RAW_R { + THRES1_HIGH_INT_RAW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn thres0_high_int_raw(&self) -> THRES0_HIGH_INT_RAW_R { + THRES0_HIGH_INT_RAW_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn sar2_done_int_raw(&self) -> SAR2_DONE_INT_RAW_R { + SAR2_DONE_INT_RAW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn sar1_done_int_raw(&self) -> SAR1_DONE_INT_RAW_R { + SAR1_DONE_INT_RAW_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "thres1_low_int_raw", + &format_args!("{}", self.thres1_low_int_raw().bit()), + ) + .field( + "thres0_low_int_raw", + &format_args!("{}", self.thres0_low_int_raw().bit()), + ) + .field( + "thres1_high_int_raw", + &format_args!("{}", self.thres1_high_int_raw().bit()), + ) + .field( + "thres0_high_int_raw", + &format_args!("{}", self.thres0_high_int_raw().bit()), + ) + .field( + "sar2_done_int_raw", + &format_args!("{}", self.sar2_done_int_raw().bit()), + ) + .field( + "sar1_done_int_raw", + &format_args!("{}", self.sar1_done_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres1_low_int_raw(&mut self) -> THRES1_LOW_INT_RAW_W { + THRES1_LOW_INT_RAW_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres0_low_int_raw(&mut self) -> THRES0_LOW_INT_RAW_W { + THRES0_LOW_INT_RAW_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres1_high_int_raw(&mut self) -> THRES1_HIGH_INT_RAW_W { + THRES1_HIGH_INT_RAW_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres0_high_int_raw(&mut self) -> THRES0_HIGH_INT_RAW_W { + THRES0_HIGH_INT_RAW_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn sar2_done_int_raw(&mut self) -> SAR2_DONE_INT_RAW_W { + SAR2_DONE_INT_RAW_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn sar1_done_int_raw(&mut self) -> SAR1_DONE_INT_RAW_W { + SAR1_DONE_INT_RAW_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/int_st.rs b/esp32p4/src/adc/int_st.rs new file mode 100644 index 0000000000..014688d7d2 --- /dev/null +++ b/esp32p4/src/adc/int_st.rs @@ -0,0 +1,94 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `THRES1_LOW_INT_ST` reader - need_des"] +pub type THRES1_LOW_INT_ST_R = crate::BitReader; +#[doc = "Field `THRES0_LOW_INT_ST` reader - need_des"] +pub type THRES0_LOW_INT_ST_R = crate::BitReader; +#[doc = "Field `THRES1_HIGH_INT_ST` reader - need_des"] +pub type THRES1_HIGH_INT_ST_R = crate::BitReader; +#[doc = "Field `THRES0_HIGH_INT_ST` reader - need_des"] +pub type THRES0_HIGH_INT_ST_R = crate::BitReader; +#[doc = "Field `APB_SARADC2_DONE_INT_ST` reader - need_des"] +pub type APB_SARADC2_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `APB_SARADC1_DONE_INT_ST` reader - need_des"] +pub type APB_SARADC1_DONE_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn thres1_low_int_st(&self) -> THRES1_LOW_INT_ST_R { + THRES1_LOW_INT_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn thres0_low_int_st(&self) -> THRES0_LOW_INT_ST_R { + THRES0_LOW_INT_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn thres1_high_int_st(&self) -> THRES1_HIGH_INT_ST_R { + THRES1_HIGH_INT_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn thres0_high_int_st(&self) -> THRES0_HIGH_INT_ST_R { + THRES0_HIGH_INT_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn apb_saradc2_done_int_st(&self) -> APB_SARADC2_DONE_INT_ST_R { + APB_SARADC2_DONE_INT_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn apb_saradc1_done_int_st(&self) -> APB_SARADC1_DONE_INT_ST_R { + APB_SARADC1_DONE_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "thres1_low_int_st", + &format_args!("{}", self.thres1_low_int_st().bit()), + ) + .field( + "thres0_low_int_st", + &format_args!("{}", self.thres0_low_int_st().bit()), + ) + .field( + "thres1_high_int_st", + &format_args!("{}", self.thres1_high_int_st().bit()), + ) + .field( + "thres0_high_int_st", + &format_args!("{}", self.thres0_high_int_st().bit()), + ) + .field( + "apb_saradc2_done_int_st", + &format_args!("{}", self.apb_saradc2_done_int_st().bit()), + ) + .field( + "apb_saradc1_done_int_st", + &format_args!("{}", self.apb_saradc1_done_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/rnd_eco_cs.rs b/esp32p4/src/adc/rnd_eco_cs.rs new file mode 100644 index 0000000000..4e8a2a741c --- /dev/null +++ b/esp32p4/src/adc/rnd_eco_cs.rs @@ -0,0 +1,74 @@ +#[doc = "Register `RND_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `RND_ECO_EN` reader - need_des"] +pub type RND_ECO_EN_R = crate::BitReader; +#[doc = "Field `RND_ECO_EN` writer - need_des"] +pub type RND_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RND_ECO_RESULT` reader - need_des"] +pub type RND_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn rnd_eco_en(&self) -> RND_ECO_EN_R { + RND_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn rnd_eco_result(&self) -> RND_ECO_RESULT_R { + RND_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_CS") + .field("rnd_eco_en", &format_args!("{}", self.rnd_eco_en().bit())) + .field( + "rnd_eco_result", + &format_args!("{}", self.rnd_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn rnd_eco_en(&mut self) -> RND_ECO_EN_W { + RND_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_CS_SPEC; +impl crate::RegisterSpec for RND_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_cs::R`](R) reader structure"] +impl crate::Readable for RND_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_cs::W`](W) writer structure"] +impl crate::Writable for RND_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_CS to value 0"] +impl crate::Resettable for RND_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/rnd_eco_high.rs b/esp32p4/src/adc/rnd_eco_high.rs new file mode 100644 index 0000000000..4f89cde952 --- /dev/null +++ b/esp32p4/src/adc/rnd_eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RND_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `RND_ECO_HIGH` reader - rnd eco high"] +pub type RND_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `RND_ECO_HIGH` writer - rnd eco high"] +pub type RND_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - rnd eco high"] + #[inline(always)] + pub fn rnd_eco_high(&self) -> RND_ECO_HIGH_R { + RND_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_HIGH") + .field( + "rnd_eco_high", + &format_args!("{}", self.rnd_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - rnd eco high"] + #[inline(always)] + #[must_use] + pub fn rnd_eco_high(&mut self) -> RND_ECO_HIGH_W { + RND_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_HIGH_SPEC; +impl crate::RegisterSpec for RND_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_high::R`](R) reader structure"] +impl crate::Readable for RND_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_high::W`](W) writer structure"] +impl crate::Writable for RND_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for RND_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/adc/rnd_eco_low.rs b/esp32p4/src/adc/rnd_eco_low.rs new file mode 100644 index 0000000000..b347e9c500 --- /dev/null +++ b/esp32p4/src/adc/rnd_eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RND_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `RND_ECO_LOW` reader - rnd eco low"] +pub type RND_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `RND_ECO_LOW` writer - rnd eco low"] +pub type RND_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - rnd eco low"] + #[inline(always)] + pub fn rnd_eco_low(&self) -> RND_ECO_LOW_R { + RND_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_LOW") + .field( + "rnd_eco_low", + &format_args!("{}", self.rnd_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - rnd eco low"] + #[inline(always)] + #[must_use] + pub fn rnd_eco_low(&mut self) -> RND_ECO_LOW_W { + RND_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_LOW_SPEC; +impl crate::RegisterSpec for RND_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_low::R`](R) reader structure"] +impl crate::Readable for RND_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_low::W`](W) writer structure"] +impl crate::Writable for RND_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_LOW to value 0"] +impl crate::Resettable for RND_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar1_data_status.rs b/esp32p4/src/adc/sar1_data_status.rs new file mode 100644 index 0000000000..65533620a2 --- /dev/null +++ b/esp32p4/src/adc/sar1_data_status.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SAR1_DATA_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `APB_SARADC1_DATA` reader - need_des"] +pub type APB_SARADC1_DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - need_des"] + #[inline(always)] + pub fn apb_saradc1_data(&self) -> APB_SARADC1_DATA_R { + APB_SARADC1_DATA_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR1_DATA_STATUS") + .field( + "apb_saradc1_data", + &format_args!("{}", self.apb_saradc1_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_data_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR1_DATA_STATUS_SPEC; +impl crate::RegisterSpec for SAR1_DATA_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar1_data_status::R`](R) reader structure"] +impl crate::Readable for SAR1_DATA_STATUS_SPEC {} +#[doc = "`reset()` method sets SAR1_DATA_STATUS to value 0"] +impl crate::Resettable for SAR1_DATA_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar1_patt_tab1.rs b/esp32p4/src/adc/sar1_patt_tab1.rs new file mode 100644 index 0000000000..1192cc78f6 --- /dev/null +++ b/esp32p4/src/adc/sar1_patt_tab1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SAR1_PATT_TAB1` reader"] +pub type R = crate::R; +#[doc = "Register `SAR1_PATT_TAB1` writer"] +pub type W = crate::W; +#[doc = "Field `SAR1_PATT_TAB1` reader - item 0 ~ 3 for pattern table 1 (each item one byte)"] +pub type SAR1_PATT_TAB1_R = crate::FieldReader; +#[doc = "Field `SAR1_PATT_TAB1` writer - item 0 ~ 3 for pattern table 1 (each item one byte)"] +pub type SAR1_PATT_TAB1_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item one byte)"] + #[inline(always)] + pub fn sar1_patt_tab1(&self) -> SAR1_PATT_TAB1_R { + SAR1_PATT_TAB1_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR1_PATT_TAB1") + .field( + "sar1_patt_tab1", + &format_args!("{}", self.sar1_patt_tab1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item one byte)"] + #[inline(always)] + #[must_use] + pub fn sar1_patt_tab1(&mut self) -> SAR1_PATT_TAB1_W { + SAR1_PATT_TAB1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_patt_tab1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar1_patt_tab1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR1_PATT_TAB1_SPEC; +impl crate::RegisterSpec for SAR1_PATT_TAB1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar1_patt_tab1::R`](R) reader structure"] +impl crate::Readable for SAR1_PATT_TAB1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab1::W`](W) writer structure"] +impl crate::Writable for SAR1_PATT_TAB1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAR1_PATT_TAB1 to value 0"] +impl crate::Resettable for SAR1_PATT_TAB1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar1_patt_tab2.rs b/esp32p4/src/adc/sar1_patt_tab2.rs new file mode 100644 index 0000000000..53de981cb7 --- /dev/null +++ b/esp32p4/src/adc/sar1_patt_tab2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SAR1_PATT_TAB2` reader"] +pub type R = crate::R; +#[doc = "Register `SAR1_PATT_TAB2` writer"] +pub type W = crate::W; +#[doc = "Field `SAR1_PATT_TAB2` reader - Item 4 ~ 7 for pattern table 1 (each item one byte)"] +pub type SAR1_PATT_TAB2_R = crate::FieldReader; +#[doc = "Field `SAR1_PATT_TAB2` writer - Item 4 ~ 7 for pattern table 1 (each item one byte)"] +pub type SAR1_PATT_TAB2_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item one byte)"] + #[inline(always)] + pub fn sar1_patt_tab2(&self) -> SAR1_PATT_TAB2_R { + SAR1_PATT_TAB2_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR1_PATT_TAB2") + .field( + "sar1_patt_tab2", + &format_args!("{}", self.sar1_patt_tab2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item one byte)"] + #[inline(always)] + #[must_use] + pub fn sar1_patt_tab2(&mut self) -> SAR1_PATT_TAB2_W { + SAR1_PATT_TAB2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_patt_tab2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar1_patt_tab2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR1_PATT_TAB2_SPEC; +impl crate::RegisterSpec for SAR1_PATT_TAB2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar1_patt_tab2::R`](R) reader structure"] +impl crate::Readable for SAR1_PATT_TAB2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab2::W`](W) writer structure"] +impl crate::Writable for SAR1_PATT_TAB2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAR1_PATT_TAB2 to value 0"] +impl crate::Resettable for SAR1_PATT_TAB2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar1_patt_tab3.rs b/esp32p4/src/adc/sar1_patt_tab3.rs new file mode 100644 index 0000000000..bb34d09844 --- /dev/null +++ b/esp32p4/src/adc/sar1_patt_tab3.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SAR1_PATT_TAB3` reader"] +pub type R = crate::R; +#[doc = "Register `SAR1_PATT_TAB3` writer"] +pub type W = crate::W; +#[doc = "Field `SAR1_PATT_TAB3` reader - Item 8 ~ 11 for pattern table 1 (each item one byte)"] +pub type SAR1_PATT_TAB3_R = crate::FieldReader; +#[doc = "Field `SAR1_PATT_TAB3` writer - Item 8 ~ 11 for pattern table 1 (each item one byte)"] +pub type SAR1_PATT_TAB3_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 1 (each item one byte)"] + #[inline(always)] + pub fn sar1_patt_tab3(&self) -> SAR1_PATT_TAB3_R { + SAR1_PATT_TAB3_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR1_PATT_TAB3") + .field( + "sar1_patt_tab3", + &format_args!("{}", self.sar1_patt_tab3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 1 (each item one byte)"] + #[inline(always)] + #[must_use] + pub fn sar1_patt_tab3(&mut self) -> SAR1_PATT_TAB3_W { + SAR1_PATT_TAB3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_patt_tab3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar1_patt_tab3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR1_PATT_TAB3_SPEC; +impl crate::RegisterSpec for SAR1_PATT_TAB3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar1_patt_tab3::R`](R) reader structure"] +impl crate::Readable for SAR1_PATT_TAB3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab3::W`](W) writer structure"] +impl crate::Writable for SAR1_PATT_TAB3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAR1_PATT_TAB3 to value 0"] +impl crate::Resettable for SAR1_PATT_TAB3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar1_patt_tab4.rs b/esp32p4/src/adc/sar1_patt_tab4.rs new file mode 100644 index 0000000000..c875d7aab6 --- /dev/null +++ b/esp32p4/src/adc/sar1_patt_tab4.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SAR1_PATT_TAB4` reader"] +pub type R = crate::R; +#[doc = "Register `SAR1_PATT_TAB4` writer"] +pub type W = crate::W; +#[doc = "Field `SAR1_PATT_TAB4` reader - Item 12 ~ 15 for pattern table 1 (each item one byte)"] +pub type SAR1_PATT_TAB4_R = crate::FieldReader; +#[doc = "Field `SAR1_PATT_TAB4` writer - Item 12 ~ 15 for pattern table 1 (each item one byte)"] +pub type SAR1_PATT_TAB4_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 1 (each item one byte)"] + #[inline(always)] + pub fn sar1_patt_tab4(&self) -> SAR1_PATT_TAB4_R { + SAR1_PATT_TAB4_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR1_PATT_TAB4") + .field( + "sar1_patt_tab4", + &format_args!("{}", self.sar1_patt_tab4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 1 (each item one byte)"] + #[inline(always)] + #[must_use] + pub fn sar1_patt_tab4(&mut self) -> SAR1_PATT_TAB4_W { + SAR1_PATT_TAB4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_patt_tab4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar1_patt_tab4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR1_PATT_TAB4_SPEC; +impl crate::RegisterSpec for SAR1_PATT_TAB4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar1_patt_tab4::R`](R) reader structure"] +impl crate::Readable for SAR1_PATT_TAB4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab4::W`](W) writer structure"] +impl crate::Writable for SAR1_PATT_TAB4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAR1_PATT_TAB4 to value 0"] +impl crate::Resettable for SAR1_PATT_TAB4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar1_status.rs b/esp32p4/src/adc/sar1_status.rs new file mode 100644 index 0000000000..ed0023538d --- /dev/null +++ b/esp32p4/src/adc/sar1_status.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SAR1_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `SAR1_STATUS` reader - "] +pub type SAR1_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sar1_status(&self) -> SAR1_STATUS_R { + SAR1_STATUS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR1_STATUS") + .field( + "sar1_status", + &format_args!("{}", self.sar1_status().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR1_STATUS_SPEC; +impl crate::RegisterSpec for SAR1_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar1_status::R`](R) reader structure"] +impl crate::Readable for SAR1_STATUS_SPEC {} +#[doc = "`reset()` method sets SAR1_STATUS to value 0"] +impl crate::Resettable for SAR1_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar2_data_status.rs b/esp32p4/src/adc/sar2_data_status.rs new file mode 100644 index 0000000000..5359523645 --- /dev/null +++ b/esp32p4/src/adc/sar2_data_status.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SAR2_DATA_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `APB_SARADC2_DATA` reader - need_des"] +pub type APB_SARADC2_DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - need_des"] + #[inline(always)] + pub fn apb_saradc2_data(&self) -> APB_SARADC2_DATA_R { + APB_SARADC2_DATA_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR2_DATA_STATUS") + .field( + "apb_saradc2_data", + &format_args!("{}", self.apb_saradc2_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_data_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR2_DATA_STATUS_SPEC; +impl crate::RegisterSpec for SAR2_DATA_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar2_data_status::R`](R) reader structure"] +impl crate::Readable for SAR2_DATA_STATUS_SPEC {} +#[doc = "`reset()` method sets SAR2_DATA_STATUS to value 0"] +impl crate::Resettable for SAR2_DATA_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar2_patt_tab1.rs b/esp32p4/src/adc/sar2_patt_tab1.rs new file mode 100644 index 0000000000..5342bc30b5 --- /dev/null +++ b/esp32p4/src/adc/sar2_patt_tab1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SAR2_PATT_TAB1` reader"] +pub type R = crate::R; +#[doc = "Register `SAR2_PATT_TAB1` writer"] +pub type W = crate::W; +#[doc = "Field `SAR2_PATT_TAB1` reader - item 0 ~ 3 for pattern table 2 (each item one byte)"] +pub type SAR2_PATT_TAB1_R = crate::FieldReader; +#[doc = "Field `SAR2_PATT_TAB1` writer - item 0 ~ 3 for pattern table 2 (each item one byte)"] +pub type SAR2_PATT_TAB1_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 2 (each item one byte)"] + #[inline(always)] + pub fn sar2_patt_tab1(&self) -> SAR2_PATT_TAB1_R { + SAR2_PATT_TAB1_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR2_PATT_TAB1") + .field( + "sar2_patt_tab1", + &format_args!("{}", self.sar2_patt_tab1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 2 (each item one byte)"] + #[inline(always)] + #[must_use] + pub fn sar2_patt_tab1(&mut self) -> SAR2_PATT_TAB1_W { + SAR2_PATT_TAB1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_patt_tab1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar2_patt_tab1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR2_PATT_TAB1_SPEC; +impl crate::RegisterSpec for SAR2_PATT_TAB1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar2_patt_tab1::R`](R) reader structure"] +impl crate::Readable for SAR2_PATT_TAB1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sar2_patt_tab1::W`](W) writer structure"] +impl crate::Writable for SAR2_PATT_TAB1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAR2_PATT_TAB1 to value 0"] +impl crate::Resettable for SAR2_PATT_TAB1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar2_patt_tab2.rs b/esp32p4/src/adc/sar2_patt_tab2.rs new file mode 100644 index 0000000000..1861c65c7e --- /dev/null +++ b/esp32p4/src/adc/sar2_patt_tab2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SAR2_PATT_TAB2` reader"] +pub type R = crate::R; +#[doc = "Register `SAR2_PATT_TAB2` writer"] +pub type W = crate::W; +#[doc = "Field `SAR2_PATT_TAB2` reader - Item 4 ~ 7 for pattern table 2 (each item one byte)"] +pub type SAR2_PATT_TAB2_R = crate::FieldReader; +#[doc = "Field `SAR2_PATT_TAB2` writer - Item 4 ~ 7 for pattern table 2 (each item one byte)"] +pub type SAR2_PATT_TAB2_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 2 (each item one byte)"] + #[inline(always)] + pub fn sar2_patt_tab2(&self) -> SAR2_PATT_TAB2_R { + SAR2_PATT_TAB2_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR2_PATT_TAB2") + .field( + "sar2_patt_tab2", + &format_args!("{}", self.sar2_patt_tab2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 2 (each item one byte)"] + #[inline(always)] + #[must_use] + pub fn sar2_patt_tab2(&mut self) -> SAR2_PATT_TAB2_W { + SAR2_PATT_TAB2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_patt_tab2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar2_patt_tab2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR2_PATT_TAB2_SPEC; +impl crate::RegisterSpec for SAR2_PATT_TAB2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar2_patt_tab2::R`](R) reader structure"] +impl crate::Readable for SAR2_PATT_TAB2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sar2_patt_tab2::W`](W) writer structure"] +impl crate::Writable for SAR2_PATT_TAB2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAR2_PATT_TAB2 to value 0"] +impl crate::Resettable for SAR2_PATT_TAB2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar2_patt_tab3.rs b/esp32p4/src/adc/sar2_patt_tab3.rs new file mode 100644 index 0000000000..60d995bae6 --- /dev/null +++ b/esp32p4/src/adc/sar2_patt_tab3.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SAR2_PATT_TAB3` reader"] +pub type R = crate::R; +#[doc = "Register `SAR2_PATT_TAB3` writer"] +pub type W = crate::W; +#[doc = "Field `SAR2_PATT_TAB3` reader - Item 8 ~ 11 for pattern table 2 (each item one byte)"] +pub type SAR2_PATT_TAB3_R = crate::FieldReader; +#[doc = "Field `SAR2_PATT_TAB3` writer - Item 8 ~ 11 for pattern table 2 (each item one byte)"] +pub type SAR2_PATT_TAB3_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 2 (each item one byte)"] + #[inline(always)] + pub fn sar2_patt_tab3(&self) -> SAR2_PATT_TAB3_R { + SAR2_PATT_TAB3_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR2_PATT_TAB3") + .field( + "sar2_patt_tab3", + &format_args!("{}", self.sar2_patt_tab3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 2 (each item one byte)"] + #[inline(always)] + #[must_use] + pub fn sar2_patt_tab3(&mut self) -> SAR2_PATT_TAB3_W { + SAR2_PATT_TAB3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_patt_tab3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar2_patt_tab3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR2_PATT_TAB3_SPEC; +impl crate::RegisterSpec for SAR2_PATT_TAB3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar2_patt_tab3::R`](R) reader structure"] +impl crate::Readable for SAR2_PATT_TAB3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sar2_patt_tab3::W`](W) writer structure"] +impl crate::Writable for SAR2_PATT_TAB3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAR2_PATT_TAB3 to value 0"] +impl crate::Resettable for SAR2_PATT_TAB3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar2_patt_tab4.rs b/esp32p4/src/adc/sar2_patt_tab4.rs new file mode 100644 index 0000000000..e558bd506e --- /dev/null +++ b/esp32p4/src/adc/sar2_patt_tab4.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SAR2_PATT_TAB4` reader"] +pub type R = crate::R; +#[doc = "Register `SAR2_PATT_TAB4` writer"] +pub type W = crate::W; +#[doc = "Field `SAR2_PATT_TAB4` reader - Item 12 ~ 15 for pattern table 2 (each item one byte)"] +pub type SAR2_PATT_TAB4_R = crate::FieldReader; +#[doc = "Field `SAR2_PATT_TAB4` writer - Item 12 ~ 15 for pattern table 2 (each item one byte)"] +pub type SAR2_PATT_TAB4_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 2 (each item one byte)"] + #[inline(always)] + pub fn sar2_patt_tab4(&self) -> SAR2_PATT_TAB4_R { + SAR2_PATT_TAB4_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR2_PATT_TAB4") + .field( + "sar2_patt_tab4", + &format_args!("{}", self.sar2_patt_tab4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 2 (each item one byte)"] + #[inline(always)] + #[must_use] + pub fn sar2_patt_tab4(&mut self) -> SAR2_PATT_TAB4_W { + SAR2_PATT_TAB4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_patt_tab4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar2_patt_tab4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR2_PATT_TAB4_SPEC; +impl crate::RegisterSpec for SAR2_PATT_TAB4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar2_patt_tab4::R`](R) reader structure"] +impl crate::Readable for SAR2_PATT_TAB4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sar2_patt_tab4::W`](W) writer structure"] +impl crate::Writable for SAR2_PATT_TAB4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAR2_PATT_TAB4 to value 0"] +impl crate::Resettable for SAR2_PATT_TAB4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/sar2_status.rs b/esp32p4/src/adc/sar2_status.rs new file mode 100644 index 0000000000..c489607856 --- /dev/null +++ b/esp32p4/src/adc/sar2_status.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SAR2_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `SAR2_STATUS` reader - "] +pub type SAR2_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sar2_status(&self) -> SAR2_STATUS_R { + SAR2_STATUS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR2_STATUS") + .field( + "sar2_status", + &format_args!("{}", self.sar2_status().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR2_STATUS_SPEC; +impl crate::RegisterSpec for SAR2_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar2_status::R`](R) reader structure"] +impl crate::Readable for SAR2_STATUS_SPEC {} +#[doc = "`reset()` method sets SAR2_STATUS to value 0"] +impl crate::Resettable for SAR2_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/adc/thres0_ctrl.rs b/esp32p4/src/adc/thres0_ctrl.rs new file mode 100644 index 0000000000..0c14cff2e4 --- /dev/null +++ b/esp32p4/src/adc/thres0_ctrl.rs @@ -0,0 +1,101 @@ +#[doc = "Register `THRES0_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `THRES0_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `THRES0_CHANNEL` reader - need_des"] +pub type THRES0_CHANNEL_R = crate::FieldReader; +#[doc = "Field `THRES0_CHANNEL` writer - need_des"] +pub type THRES0_CHANNEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `THRES0_HIGH` reader - saradc1's thres0 monitor thres"] +pub type THRES0_HIGH_R = crate::FieldReader; +#[doc = "Field `THRES0_HIGH` writer - saradc1's thres0 monitor thres"] +pub type THRES0_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +#[doc = "Field `THRES0_LOW` reader - saradc1's thres0 monitor thres"] +pub type THRES0_LOW_R = crate::FieldReader; +#[doc = "Field `THRES0_LOW` writer - saradc1's thres0 monitor thres"] +pub type THRES0_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + pub fn thres0_channel(&self) -> THRES0_CHANNEL_R { + THRES0_CHANNEL_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:17 - saradc1's thres0 monitor thres"] + #[inline(always)] + pub fn thres0_high(&self) -> THRES0_HIGH_R { + THRES0_HIGH_R::new(((self.bits >> 5) & 0x1fff) as u16) + } + #[doc = "Bits 18:30 - saradc1's thres0 monitor thres"] + #[inline(always)] + pub fn thres0_low(&self) -> THRES0_LOW_R { + THRES0_LOW_R::new(((self.bits >> 18) & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("THRES0_CTRL") + .field( + "thres0_channel", + &format_args!("{}", self.thres0_channel().bits()), + ) + .field( + "thres0_high", + &format_args!("{}", self.thres0_high().bits()), + ) + .field("thres0_low", &format_args!("{}", self.thres0_low().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres0_channel(&mut self) -> THRES0_CHANNEL_W { + THRES0_CHANNEL_W::new(self, 0) + } + #[doc = "Bits 5:17 - saradc1's thres0 monitor thres"] + #[inline(always)] + #[must_use] + pub fn thres0_high(&mut self) -> THRES0_HIGH_W { + THRES0_HIGH_W::new(self, 5) + } + #[doc = "Bits 18:30 - saradc1's thres0 monitor thres"] + #[inline(always)] + #[must_use] + pub fn thres0_low(&mut self) -> THRES0_LOW_W { + THRES0_LOW_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thres0_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thres0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct THRES0_CTRL_SPEC; +impl crate::RegisterSpec for THRES0_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`thres0_ctrl::R`](R) reader structure"] +impl crate::Readable for THRES0_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`thres0_ctrl::W`](W) writer structure"] +impl crate::Writable for THRES0_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets THRES0_CTRL to value 0x0003_ffed"] +impl crate::Resettable for THRES0_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0003_ffed; +} diff --git a/esp32p4/src/adc/thres1_ctrl.rs b/esp32p4/src/adc/thres1_ctrl.rs new file mode 100644 index 0000000000..27103595b3 --- /dev/null +++ b/esp32p4/src/adc/thres1_ctrl.rs @@ -0,0 +1,101 @@ +#[doc = "Register `THRES1_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `THRES1_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `THRES1_CHANNEL` reader - need_des"] +pub type THRES1_CHANNEL_R = crate::FieldReader; +#[doc = "Field `THRES1_CHANNEL` writer - need_des"] +pub type THRES1_CHANNEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `THRES1_HIGH` reader - saradc1's thres0 monitor thres"] +pub type THRES1_HIGH_R = crate::FieldReader; +#[doc = "Field `THRES1_HIGH` writer - saradc1's thres0 monitor thres"] +pub type THRES1_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +#[doc = "Field `THRES1_LOW` reader - saradc1's thres0 monitor thres"] +pub type THRES1_LOW_R = crate::FieldReader; +#[doc = "Field `THRES1_LOW` writer - saradc1's thres0 monitor thres"] +pub type THRES1_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + pub fn thres1_channel(&self) -> THRES1_CHANNEL_R { + THRES1_CHANNEL_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:17 - saradc1's thres0 monitor thres"] + #[inline(always)] + pub fn thres1_high(&self) -> THRES1_HIGH_R { + THRES1_HIGH_R::new(((self.bits >> 5) & 0x1fff) as u16) + } + #[doc = "Bits 18:30 - saradc1's thres0 monitor thres"] + #[inline(always)] + pub fn thres1_low(&self) -> THRES1_LOW_R { + THRES1_LOW_R::new(((self.bits >> 18) & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("THRES1_CTRL") + .field( + "thres1_channel", + &format_args!("{}", self.thres1_channel().bits()), + ) + .field( + "thres1_high", + &format_args!("{}", self.thres1_high().bits()), + ) + .field("thres1_low", &format_args!("{}", self.thres1_low().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres1_channel(&mut self) -> THRES1_CHANNEL_W { + THRES1_CHANNEL_W::new(self, 0) + } + #[doc = "Bits 5:17 - saradc1's thres0 monitor thres"] + #[inline(always)] + #[must_use] + pub fn thres1_high(&mut self) -> THRES1_HIGH_W { + THRES1_HIGH_W::new(self, 5) + } + #[doc = "Bits 18:30 - saradc1's thres0 monitor thres"] + #[inline(always)] + #[must_use] + pub fn thres1_low(&mut self) -> THRES1_LOW_W { + THRES1_LOW_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thres1_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thres1_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct THRES1_CTRL_SPEC; +impl crate::RegisterSpec for THRES1_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`thres1_ctrl::R`](R) reader structure"] +impl crate::Readable for THRES1_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`thres1_ctrl::W`](W) writer structure"] +impl crate::Writable for THRES1_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets THRES1_CTRL to value 0x0003_ffed"] +impl crate::Resettable for THRES1_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0003_ffed; +} diff --git a/esp32p4/src/adc/thres_ctrl.rs b/esp32p4/src/adc/thres_ctrl.rs new file mode 100644 index 0000000000..15b42ae90c --- /dev/null +++ b/esp32p4/src/adc/thres_ctrl.rs @@ -0,0 +1,130 @@ +#[doc = "Register `THRES_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `THRES_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `THRES_ALL_EN` reader - need_des"] +pub type THRES_ALL_EN_R = crate::BitReader; +#[doc = "Field `THRES_ALL_EN` writer - need_des"] +pub type THRES_ALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES3_EN` reader - need_des"] +pub type THRES3_EN_R = crate::BitReader; +#[doc = "Field `THRES3_EN` writer - need_des"] +pub type THRES3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES2_EN` reader - need_des"] +pub type THRES2_EN_R = crate::BitReader; +#[doc = "Field `THRES2_EN` writer - need_des"] +pub type THRES2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES1_EN` reader - need_des"] +pub type THRES1_EN_R = crate::BitReader; +#[doc = "Field `THRES1_EN` writer - need_des"] +pub type THRES1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES0_EN` reader - need_des"] +pub type THRES0_EN_R = crate::BitReader; +#[doc = "Field `THRES0_EN` writer - need_des"] +pub type THRES0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn thres_all_en(&self) -> THRES_ALL_EN_R { + THRES_ALL_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn thres3_en(&self) -> THRES3_EN_R { + THRES3_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn thres2_en(&self) -> THRES2_EN_R { + THRES2_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn thres1_en(&self) -> THRES1_EN_R { + THRES1_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn thres0_en(&self) -> THRES0_EN_R { + THRES0_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("THRES_CTRL") + .field( + "thres_all_en", + &format_args!("{}", self.thres_all_en().bit()), + ) + .field("thres3_en", &format_args!("{}", self.thres3_en().bit())) + .field("thres2_en", &format_args!("{}", self.thres2_en().bit())) + .field("thres1_en", &format_args!("{}", self.thres1_en().bit())) + .field("thres0_en", &format_args!("{}", self.thres0_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres_all_en(&mut self) -> THRES_ALL_EN_W { + THRES_ALL_EN_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres3_en(&mut self) -> THRES3_EN_W { + THRES3_EN_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres2_en(&mut self) -> THRES2_EN_W { + THRES2_EN_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres1_en(&mut self) -> THRES1_EN_W { + THRES1_EN_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn thres0_en(&mut self) -> THRES0_EN_W { + THRES0_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thres_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thres_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct THRES_CTRL_SPEC; +impl crate::RegisterSpec for THRES_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`thres_ctrl::R`](R) reader structure"] +impl crate::Readable for THRES_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`thres_ctrl::W`](W) writer structure"] +impl crate::Writable for THRES_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets THRES_CTRL to value 0"] +impl crate::Resettable for THRES_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes.rs b/esp32p4/src/aes.rs new file mode 100644 index 0000000000..02bb4fbcf7 --- /dev/null +++ b/esp32p4/src/aes.rs @@ -0,0 +1,357 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + key_0: KEY_0, + key_1: KEY_1, + key_2: KEY_2, + key_3: KEY_3, + key_4: KEY_4, + key_5: KEY_5, + key_6: KEY_6, + key_7: KEY_7, + text_in_0: TEXT_IN_0, + text_in_1: TEXT_IN_1, + text_in_2: TEXT_IN_2, + text_in_3: TEXT_IN_3, + text_out_0: TEXT_OUT_0, + text_out_1: TEXT_OUT_1, + text_out_2: TEXT_OUT_2, + text_out_3: TEXT_OUT_3, + mode: MODE, + endian: ENDIAN, + trigger: TRIGGER, + state: STATE, + iv_mem: [IV_MEM; 16], + h_mem: [H_MEM; 16], + j0_mem: [J0_MEM; 16], + t0_mem: [T0_MEM; 16], + dma_enable: DMA_ENABLE, + block_mode: BLOCK_MODE, + block_num: BLOCK_NUM, + inc_sel: INC_SEL, + aad_block_num: AAD_BLOCK_NUM, + remainder_bit_num: REMAINDER_BIT_NUM, + continue_: CONTINUE, + int_clear: INT_CLEAR, + int_ena: INT_ENA, + date: DATE, + dma_exit: DMA_EXIT, +} +impl RegisterBlock { + #[doc = "0x00 - Key material key_0 configure register"] + #[inline(always)] + pub const fn key_0(&self) -> &KEY_0 { + &self.key_0 + } + #[doc = "0x04 - Key material key_1 configure register"] + #[inline(always)] + pub const fn key_1(&self) -> &KEY_1 { + &self.key_1 + } + #[doc = "0x08 - Key material key_2 configure register"] + #[inline(always)] + pub const fn key_2(&self) -> &KEY_2 { + &self.key_2 + } + #[doc = "0x0c - Key material key_3 configure register"] + #[inline(always)] + pub const fn key_3(&self) -> &KEY_3 { + &self.key_3 + } + #[doc = "0x10 - Key material key_4 configure register"] + #[inline(always)] + pub const fn key_4(&self) -> &KEY_4 { + &self.key_4 + } + #[doc = "0x14 - Key material key_5 configure register"] + #[inline(always)] + pub const fn key_5(&self) -> &KEY_5 { + &self.key_5 + } + #[doc = "0x18 - Key material key_6 configure register"] + #[inline(always)] + pub const fn key_6(&self) -> &KEY_6 { + &self.key_6 + } + #[doc = "0x1c - Key material key_7 configure register"] + #[inline(always)] + pub const fn key_7(&self) -> &KEY_7 { + &self.key_7 + } + #[doc = "0x20 - source text material text_in_0 configure register"] + #[inline(always)] + pub const fn text_in_0(&self) -> &TEXT_IN_0 { + &self.text_in_0 + } + #[doc = "0x24 - source text material text_in_1 configure register"] + #[inline(always)] + pub const fn text_in_1(&self) -> &TEXT_IN_1 { + &self.text_in_1 + } + #[doc = "0x28 - source text material text_in_2 configure register"] + #[inline(always)] + pub const fn text_in_2(&self) -> &TEXT_IN_2 { + &self.text_in_2 + } + #[doc = "0x2c - source text material text_in_3 configure register"] + #[inline(always)] + pub const fn text_in_3(&self) -> &TEXT_IN_3 { + &self.text_in_3 + } + #[doc = "0x30 - result text material text_out_0 configure register"] + #[inline(always)] + pub const fn text_out_0(&self) -> &TEXT_OUT_0 { + &self.text_out_0 + } + #[doc = "0x34 - result text material text_out_1 configure register"] + #[inline(always)] + pub const fn text_out_1(&self) -> &TEXT_OUT_1 { + &self.text_out_1 + } + #[doc = "0x38 - result text material text_out_2 configure register"] + #[inline(always)] + pub const fn text_out_2(&self) -> &TEXT_OUT_2 { + &self.text_out_2 + } + #[doc = "0x3c - result text material text_out_3 configure register"] + #[inline(always)] + pub const fn text_out_3(&self) -> &TEXT_OUT_3 { + &self.text_out_3 + } + #[doc = "0x40 - AES Mode register"] + #[inline(always)] + pub const fn mode(&self) -> &MODE { + &self.mode + } + #[doc = "0x44 - AES Endian configure register"] + #[inline(always)] + pub const fn endian(&self) -> &ENDIAN { + &self.endian + } + #[doc = "0x48 - AES trigger register"] + #[inline(always)] + pub const fn trigger(&self) -> &TRIGGER { + &self.trigger + } + #[doc = "0x4c - AES state register"] + #[inline(always)] + pub const fn state(&self) -> &STATE { + &self.state + } + #[doc = "0x50..0x60 - The memory that stores initialization vector"] + #[inline(always)] + pub const fn iv_mem(&self, n: usize) -> &IV_MEM { + &self.iv_mem[n] + } + #[doc = "0x60..0x70 - The memory that stores GCM hash subkey"] + #[inline(always)] + pub const fn h_mem(&self, n: usize) -> &H_MEM { + &self.h_mem[n] + } + #[doc = "0x70..0x80 - The memory that stores J0"] + #[inline(always)] + pub const fn j0_mem(&self, n: usize) -> &J0_MEM { + &self.j0_mem[n] + } + #[doc = "0x80..0x90 - The memory that stores T0"] + #[inline(always)] + pub const fn t0_mem(&self, n: usize) -> &T0_MEM { + &self.t0_mem[n] + } + #[doc = "0x90 - DMA-AES working mode register"] + #[inline(always)] + pub const fn dma_enable(&self) -> &DMA_ENABLE { + &self.dma_enable + } + #[doc = "0x94 - AES cipher block mode register"] + #[inline(always)] + pub const fn block_mode(&self) -> &BLOCK_MODE { + &self.block_mode + } + #[doc = "0x98 - AES block number register"] + #[inline(always)] + pub const fn block_num(&self) -> &BLOCK_NUM { + &self.block_num + } + #[doc = "0x9c - Standard incrementing function configure register"] + #[inline(always)] + pub const fn inc_sel(&self) -> &INC_SEL { + &self.inc_sel + } + #[doc = "0xa0 - Additional Authential Data block number register"] + #[inline(always)] + pub const fn aad_block_num(&self) -> &AAD_BLOCK_NUM { + &self.aad_block_num + } + #[doc = "0xa4 - AES remainder bit number register"] + #[inline(always)] + pub const fn remainder_bit_num(&self) -> &REMAINDER_BIT_NUM { + &self.remainder_bit_num + } + #[doc = "0xa8 - AES continue register"] + #[inline(always)] + pub const fn continue_(&self) -> &CONTINUE { + &self.continue_ + } + #[doc = "0xac - AES Interrupt clear register"] + #[inline(always)] + pub const fn int_clear(&self) -> &INT_CLEAR { + &self.int_clear + } + #[doc = "0xb0 - AES Interrupt enable register"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0xb4 - AES version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } + #[doc = "0xb8 - AES-DMA exit config"] + #[inline(always)] + pub const fn dma_exit(&self) -> &DMA_EXIT { + &self.dma_exit + } +} +#[doc = "KEY_0 (rw) register accessor: Key material key_0 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key_0`] module"] +pub type KEY_0 = crate::Reg; +#[doc = "Key material key_0 configure register"] +pub mod key_0; +#[doc = "KEY_1 (rw) register accessor: Key material key_1 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key_1`] module"] +pub type KEY_1 = crate::Reg; +#[doc = "Key material key_1 configure register"] +pub mod key_1; +#[doc = "KEY_2 (rw) register accessor: Key material key_2 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key_2`] module"] +pub type KEY_2 = crate::Reg; +#[doc = "Key material key_2 configure register"] +pub mod key_2; +#[doc = "KEY_3 (rw) register accessor: Key material key_3 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key_3`] module"] +pub type KEY_3 = crate::Reg; +#[doc = "Key material key_3 configure register"] +pub mod key_3; +#[doc = "KEY_4 (rw) register accessor: Key material key_4 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key_4`] module"] +pub type KEY_4 = crate::Reg; +#[doc = "Key material key_4 configure register"] +pub mod key_4; +#[doc = "KEY_5 (rw) register accessor: Key material key_5 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key_5`] module"] +pub type KEY_5 = crate::Reg; +#[doc = "Key material key_5 configure register"] +pub mod key_5; +#[doc = "KEY_6 (rw) register accessor: Key material key_6 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key_6`] module"] +pub type KEY_6 = crate::Reg; +#[doc = "Key material key_6 configure register"] +pub mod key_6; +#[doc = "KEY_7 (rw) register accessor: Key material key_7 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key_7`] module"] +pub type KEY_7 = crate::Reg; +#[doc = "Key material key_7 configure register"] +pub mod key_7; +#[doc = "TEXT_IN_0 (rw) register accessor: source text material text_in_0 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_in_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_in_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_in_0`] module"] +pub type TEXT_IN_0 = crate::Reg; +#[doc = "source text material text_in_0 configure register"] +pub mod text_in_0; +#[doc = "TEXT_IN_1 (rw) register accessor: source text material text_in_1 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_in_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_in_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_in_1`] module"] +pub type TEXT_IN_1 = crate::Reg; +#[doc = "source text material text_in_1 configure register"] +pub mod text_in_1; +#[doc = "TEXT_IN_2 (rw) register accessor: source text material text_in_2 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_in_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_in_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_in_2`] module"] +pub type TEXT_IN_2 = crate::Reg; +#[doc = "source text material text_in_2 configure register"] +pub mod text_in_2; +#[doc = "TEXT_IN_3 (rw) register accessor: source text material text_in_3 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_in_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_in_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_in_3`] module"] +pub type TEXT_IN_3 = crate::Reg; +#[doc = "source text material text_in_3 configure register"] +pub mod text_in_3; +#[doc = "TEXT_OUT_0 (rw) register accessor: result text material text_out_0 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_out_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_out_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_out_0`] module"] +pub type TEXT_OUT_0 = crate::Reg; +#[doc = "result text material text_out_0 configure register"] +pub mod text_out_0; +#[doc = "TEXT_OUT_1 (rw) register accessor: result text material text_out_1 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_out_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_out_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_out_1`] module"] +pub type TEXT_OUT_1 = crate::Reg; +#[doc = "result text material text_out_1 configure register"] +pub mod text_out_1; +#[doc = "TEXT_OUT_2 (rw) register accessor: result text material text_out_2 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_out_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_out_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_out_2`] module"] +pub type TEXT_OUT_2 = crate::Reg; +#[doc = "result text material text_out_2 configure register"] +pub mod text_out_2; +#[doc = "TEXT_OUT_3 (rw) register accessor: result text material text_out_3 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_out_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_out_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_out_3`] module"] +pub type TEXT_OUT_3 = crate::Reg; +#[doc = "result text material text_out_3 configure register"] +pub mod text_out_3; +#[doc = "MODE (rw) register accessor: AES Mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`] module"] +pub type MODE = crate::Reg; +#[doc = "AES Mode register"] +pub mod mode; +#[doc = "ENDIAN (rw) register accessor: AES Endian configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endian::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endian::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endian`] module"] +pub type ENDIAN = crate::Reg; +#[doc = "AES Endian configure register"] +pub mod endian; +#[doc = "TRIGGER (w) register accessor: AES trigger register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trigger::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigger`] module"] +pub type TRIGGER = crate::Reg; +#[doc = "AES trigger register"] +pub mod trigger; +#[doc = "STATE (r) register accessor: AES state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] +pub type STATE = crate::Reg; +#[doc = "AES state register"] +pub mod state; +#[doc = "IV_MEM (rw) register accessor: The memory that stores initialization vector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iv_mem`] module"] +pub type IV_MEM = crate::Reg; +#[doc = "The memory that stores initialization vector"] +pub mod iv_mem; +#[doc = "H_MEM (rw) register accessor: The memory that stores GCM hash subkey\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h_mem`] module"] +pub type H_MEM = crate::Reg; +#[doc = "The memory that stores GCM hash subkey"] +pub mod h_mem; +#[doc = "J0_MEM (rw) register accessor: The memory that stores J0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`j0_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`j0_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@j0_mem`] module"] +pub type J0_MEM = crate::Reg; +#[doc = "The memory that stores J0"] +pub mod j0_mem; +#[doc = "T0_MEM (rw) register accessor: The memory that stores T0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0_mem`] module"] +pub type T0_MEM = crate::Reg; +#[doc = "The memory that stores T0"] +pub mod t0_mem; +#[doc = "DMA_ENABLE (rw) register accessor: DMA-AES working mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_enable`] module"] +pub type DMA_ENABLE = crate::Reg; +#[doc = "DMA-AES working mode register"] +pub mod dma_enable; +#[doc = "BLOCK_MODE (rw) register accessor: AES cipher block mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`block_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`block_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@block_mode`] module"] +pub type BLOCK_MODE = crate::Reg; +#[doc = "AES cipher block mode register"] +pub mod block_mode; +#[doc = "BLOCK_NUM (rw) register accessor: AES block number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`block_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`block_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@block_num`] module"] +pub type BLOCK_NUM = crate::Reg; +#[doc = "AES block number register"] +pub mod block_num; +#[doc = "INC_SEL (rw) register accessor: Standard incrementing function configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inc_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inc_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inc_sel`] module"] +pub type INC_SEL = crate::Reg; +#[doc = "Standard incrementing function configure register"] +pub mod inc_sel; +#[doc = "AAD_BLOCK_NUM (rw) register accessor: Additional Authential Data block number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aad_block_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aad_block_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aad_block_num`] module"] +pub type AAD_BLOCK_NUM = crate::Reg; +#[doc = "Additional Authential Data block number register"] +pub mod aad_block_num; +#[doc = "REMAINDER_BIT_NUM (rw) register accessor: AES remainder bit number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`remainder_bit_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`remainder_bit_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remainder_bit_num`] module"] +pub type REMAINDER_BIT_NUM = crate::Reg; +#[doc = "AES remainder bit number register"] +pub mod remainder_bit_num; +#[doc = "CONTINUE (w) register accessor: AES continue register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`continue_::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@continue_`] module"] +pub type CONTINUE = crate::Reg; +#[doc = "AES continue register"] +pub mod continue_; +#[doc = "INT_CLEAR (w) register accessor: AES Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clear::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clear`] module"] +pub type INT_CLEAR = crate::Reg; +#[doc = "AES Interrupt clear register"] +pub mod int_clear; +#[doc = "INT_ENA (rw) register accessor: AES Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "AES Interrupt enable register"] +pub mod int_ena; +#[doc = "DATE (rw) register accessor: AES version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "AES version control register"] +pub mod date; +#[doc = "DMA_EXIT (w) register accessor: AES-DMA exit config\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_exit::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_exit`] module"] +pub type DMA_EXIT = crate::Reg; +#[doc = "AES-DMA exit config"] +pub mod dma_exit; diff --git a/esp32p4/src/aes/aad_block_num.rs b/esp32p4/src/aes/aad_block_num.rs new file mode 100644 index 0000000000..01f3110518 --- /dev/null +++ b/esp32p4/src/aes/aad_block_num.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AAD_BLOCK_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `AAD_BLOCK_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `AAD_BLOCK_NUM` reader - Those bits stores the number of AAD block."] +pub type AAD_BLOCK_NUM_R = crate::FieldReader; +#[doc = "Field `AAD_BLOCK_NUM` writer - Those bits stores the number of AAD block."] +pub type AAD_BLOCK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits stores the number of AAD block."] + #[inline(always)] + pub fn aad_block_num(&self) -> AAD_BLOCK_NUM_R { + AAD_BLOCK_NUM_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AAD_BLOCK_NUM") + .field( + "aad_block_num", + &format_args!("{}", self.aad_block_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits stores the number of AAD block."] + #[inline(always)] + #[must_use] + pub fn aad_block_num(&mut self) -> AAD_BLOCK_NUM_W { + AAD_BLOCK_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Additional Authential Data block number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aad_block_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aad_block_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AAD_BLOCK_NUM_SPEC; +impl crate::RegisterSpec for AAD_BLOCK_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`aad_block_num::R`](R) reader structure"] +impl crate::Readable for AAD_BLOCK_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`aad_block_num::W`](W) writer structure"] +impl crate::Writable for AAD_BLOCK_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AAD_BLOCK_NUM to value 0"] +impl crate::Resettable for AAD_BLOCK_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/block_mode.rs b/esp32p4/src/aes/block_mode.rs new file mode 100644 index 0000000000..4b8003d08d --- /dev/null +++ b/esp32p4/src/aes/block_mode.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BLOCK_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `BLOCK_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `BLOCK_MODE` reader - Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved."] +pub type BLOCK_MODE_R = crate::FieldReader; +#[doc = "Field `BLOCK_MODE` writer - Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved."] +pub type BLOCK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved."] + #[inline(always)] + pub fn block_mode(&self) -> BLOCK_MODE_R { + BLOCK_MODE_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLOCK_MODE") + .field("block_mode", &format_args!("{}", self.block_mode().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved."] + #[inline(always)] + #[must_use] + pub fn block_mode(&mut self) -> BLOCK_MODE_W { + BLOCK_MODE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AES cipher block mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`block_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`block_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLOCK_MODE_SPEC; +impl crate::RegisterSpec for BLOCK_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`block_mode::R`](R) reader structure"] +impl crate::Readable for BLOCK_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`block_mode::W`](W) writer structure"] +impl crate::Writable for BLOCK_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLOCK_MODE to value 0"] +impl crate::Resettable for BLOCK_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/block_num.rs b/esp32p4/src/aes/block_num.rs new file mode 100644 index 0000000000..ec63fb588f --- /dev/null +++ b/esp32p4/src/aes/block_num.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BLOCK_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `BLOCK_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `BLOCK_NUM` reader - Those bits stores the number of Plaintext/ciphertext block."] +pub type BLOCK_NUM_R = crate::FieldReader; +#[doc = "Field `BLOCK_NUM` writer - Those bits stores the number of Plaintext/ciphertext block."] +pub type BLOCK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits stores the number of Plaintext/ciphertext block."] + #[inline(always)] + pub fn block_num(&self) -> BLOCK_NUM_R { + BLOCK_NUM_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLOCK_NUM") + .field("block_num", &format_args!("{}", self.block_num().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits stores the number of Plaintext/ciphertext block."] + #[inline(always)] + #[must_use] + pub fn block_num(&mut self) -> BLOCK_NUM_W { + BLOCK_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AES block number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`block_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`block_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLOCK_NUM_SPEC; +impl crate::RegisterSpec for BLOCK_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`block_num::R`](R) reader structure"] +impl crate::Readable for BLOCK_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`block_num::W`](W) writer structure"] +impl crate::Writable for BLOCK_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLOCK_NUM to value 0"] +impl crate::Resettable for BLOCK_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/continue_.rs b/esp32p4/src/aes/continue_.rs new file mode 100644 index 0000000000..0eabfeddc5 --- /dev/null +++ b/esp32p4/src/aes/continue_.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CONTINUE` writer"] +pub type W = crate::W; +#[doc = "Field `CONTINUE` writer - Set this bit to continue GCM operation."] +pub type CONTINUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to continue GCM operation."] + #[inline(always)] + #[must_use] + pub fn continue_(&mut self) -> CONTINUE_W { + CONTINUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AES continue register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`continue_::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONTINUE_SPEC; +impl crate::RegisterSpec for CONTINUE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`continue_::W`](W) writer structure"] +impl crate::Writable for CONTINUE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONTINUE to value 0"] +impl crate::Resettable for CONTINUE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/date.rs b/esp32p4/src/aes/date.rs new file mode 100644 index 0000000000..bbf2b3d709 --- /dev/null +++ b/esp32p4/src/aes/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - This bits stores the version information of AES."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - This bits stores the version information of AES."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 0:29 - This bits stores the version information of AES."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x3fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:29 - This bits stores the version information of AES."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AES version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x2019_1210"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2019_1210; +} diff --git a/esp32p4/src/aes/dma_enable.rs b/esp32p4/src/aes/dma_enable.rs new file mode 100644 index 0000000000..1f2c0023b5 --- /dev/null +++ b/esp32p4/src/aes/dma_enable.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DMA_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_ENABLE` reader - 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."] +pub type DMA_ENABLE_R = crate::BitReader; +#[doc = "Field `DMA_ENABLE` writer - 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."] +pub type DMA_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."] + #[inline(always)] + pub fn dma_enable(&self) -> DMA_ENABLE_R { + DMA_ENABLE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_ENABLE") + .field("dma_enable", &format_args!("{}", self.dma_enable().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."] + #[inline(always)] + #[must_use] + pub fn dma_enable(&mut self) -> DMA_ENABLE_W { + DMA_ENABLE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DMA-AES working mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_ENABLE_SPEC; +impl crate::RegisterSpec for DMA_ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_enable::R`](R) reader structure"] +impl crate::Readable for DMA_ENABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_enable::W`](W) writer structure"] +impl crate::Writable for DMA_ENABLE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_ENABLE to value 0"] +impl crate::Resettable for DMA_ENABLE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/dma_exit.rs b/esp32p4/src/aes/dma_exit.rs new file mode 100644 index 0000000000..141a4162f8 --- /dev/null +++ b/esp32p4/src/aes/dma_exit.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DMA_EXIT` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_EXIT` writer - Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer."] +pub type DMA_EXIT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer."] + #[inline(always)] + #[must_use] + pub fn dma_exit(&mut self) -> DMA_EXIT_W { + DMA_EXIT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AES-DMA exit config\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_exit::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_EXIT_SPEC; +impl crate::RegisterSpec for DMA_EXIT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`dma_exit::W`](W) writer structure"] +impl crate::Writable for DMA_EXIT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_EXIT to value 0"] +impl crate::Resettable for DMA_EXIT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/endian.rs b/esp32p4/src/aes/endian.rs new file mode 100644 index 0000000000..4473e3cccf --- /dev/null +++ b/esp32p4/src/aes/endian.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ENDIAN` reader"] +pub type R = crate::R; +#[doc = "Register `ENDIAN` writer"] +pub type W = crate::W; +#[doc = "Field `ENDIAN` reader - endian. \\[1:0\\] key endian, \\[3:2\\] text_in endian or in_stream endian, \\[5:4\\] text_out endian or out_stream endian"] +pub type ENDIAN_R = crate::FieldReader; +#[doc = "Field `ENDIAN` writer - endian. \\[1:0\\] key endian, \\[3:2\\] text_in endian or in_stream endian, \\[5:4\\] text_out endian or out_stream endian"] +pub type ENDIAN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - endian. \\[1:0\\] key endian, \\[3:2\\] text_in endian or in_stream endian, \\[5:4\\] text_out endian or out_stream endian"] + #[inline(always)] + pub fn endian(&self) -> ENDIAN_R { + ENDIAN_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENDIAN") + .field("endian", &format_args!("{}", self.endian().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - endian. \\[1:0\\] key endian, \\[3:2\\] text_in endian or in_stream endian, \\[5:4\\] text_out endian or out_stream endian"] + #[inline(always)] + #[must_use] + pub fn endian(&mut self) -> ENDIAN_W { + ENDIAN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AES Endian configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endian::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endian::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENDIAN_SPEC; +impl crate::RegisterSpec for ENDIAN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`endian::R`](R) reader structure"] +impl crate::Readable for ENDIAN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`endian::W`](W) writer structure"] +impl crate::Writable for ENDIAN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENDIAN to value 0"] +impl crate::Resettable for ENDIAN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/h_mem.rs b/esp32p4/src/aes/h_mem.rs new file mode 100644 index 0000000000..4bbdee4a13 --- /dev/null +++ b/esp32p4/src/aes/h_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `H_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `H_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores GCM hash subkey\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H_MEM_SPEC; +impl crate::RegisterSpec for H_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`h_mem::R`](R) reader structure"] +impl crate::Readable for H_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h_mem::W`](W) writer structure"] +impl crate::Writable for H_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H_MEM[%s] to value 0"] +impl crate::Resettable for H_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/inc_sel.rs b/esp32p4/src/aes/inc_sel.rs new file mode 100644 index 0000000000..87e44e4a0b --- /dev/null +++ b/esp32p4/src/aes/inc_sel.rs @@ -0,0 +1,63 @@ +#[doc = "Register `INC_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `INC_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `INC_SEL` reader - This bit decides the standard incrementing function. 0: INC32. 1: INC128."] +pub type INC_SEL_R = crate::BitReader; +#[doc = "Field `INC_SEL` writer - This bit decides the standard incrementing function. 0: INC32. 1: INC128."] +pub type INC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit decides the standard incrementing function. 0: INC32. 1: INC128."] + #[inline(always)] + pub fn inc_sel(&self) -> INC_SEL_R { + INC_SEL_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INC_SEL") + .field("inc_sel", &format_args!("{}", self.inc_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This bit decides the standard incrementing function. 0: INC32. 1: INC128."] + #[inline(always)] + #[must_use] + pub fn inc_sel(&mut self) -> INC_SEL_W { + INC_SEL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Standard incrementing function configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inc_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inc_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INC_SEL_SPEC; +impl crate::RegisterSpec for INC_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inc_sel::R`](R) reader structure"] +impl crate::Readable for INC_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inc_sel::W`](W) writer structure"] +impl crate::Writable for INC_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INC_SEL to value 0"] +impl crate::Resettable for INC_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/int_clear.rs b/esp32p4/src/aes/int_clear.rs new file mode 100644 index 0000000000..d4883d98f6 --- /dev/null +++ b/esp32p4/src/aes/int_clear.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INT_CLEAR` writer"] +pub type W = crate::W; +#[doc = "Field `INT_CLEAR` writer - Set this bit to clear the AES interrupt."] +pub type INT_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the AES interrupt."] + #[inline(always)] + #[must_use] + pub fn int_clear(&mut self) -> INT_CLEAR_W { + INT_CLEAR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AES Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clear::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLEAR_SPEC; +impl crate::RegisterSpec for INT_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clear::W`](W) writer structure"] +impl crate::Writable for INT_CLEAR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLEAR to value 0"] +impl crate::Resettable for INT_CLEAR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/int_ena.rs b/esp32p4/src/aes/int_ena.rs new file mode 100644 index 0000000000..d6223a88a5 --- /dev/null +++ b/esp32p4/src/aes/int_ena.rs @@ -0,0 +1,63 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `INT_ENA` reader - Set this bit to enable interrupt that occurs when DMA-AES calculation is done."] +pub type INT_ENA_R = crate::BitReader; +#[doc = "Field `INT_ENA` writer - Set this bit to enable interrupt that occurs when DMA-AES calculation is done."] +pub type INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable interrupt that occurs when DMA-AES calculation is done."] + #[inline(always)] + pub fn int_ena(&self) -> INT_ENA_R { + INT_ENA_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field("int_ena", &format_args!("{}", self.int_ena().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable interrupt that occurs when DMA-AES calculation is done."] + #[inline(always)] + #[must_use] + pub fn int_ena(&mut self) -> INT_ENA_W { + INT_ENA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AES Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/iv_mem.rs b/esp32p4/src/aes/iv_mem.rs new file mode 100644 index 0000000000..854774b9f1 --- /dev/null +++ b/esp32p4/src/aes/iv_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `IV_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `IV_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores initialization vector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IV_MEM_SPEC; +impl crate::RegisterSpec for IV_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`iv_mem::R`](R) reader structure"] +impl crate::Readable for IV_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`iv_mem::W`](W) writer structure"] +impl crate::Writable for IV_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IV_MEM[%s] to value 0"] +impl crate::Resettable for IV_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/j0_mem.rs b/esp32p4/src/aes/j0_mem.rs new file mode 100644 index 0000000000..a9cc422ce3 --- /dev/null +++ b/esp32p4/src/aes/j0_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `J0_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `J0_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores J0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`j0_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`j0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct J0_MEM_SPEC; +impl crate::RegisterSpec for J0_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`j0_mem::R`](R) reader structure"] +impl crate::Readable for J0_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`j0_mem::W`](W) writer structure"] +impl crate::Writable for J0_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets J0_MEM[%s] to value 0"] +impl crate::Resettable for J0_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/key_0.rs b/esp32p4/src/aes/key_0.rs new file mode 100644 index 0000000000..526d164781 --- /dev/null +++ b/esp32p4/src/aes/key_0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `KEY_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_0` reader - This bits stores key_0 that is a part of key material."] +pub type KEY_0_R = crate::FieldReader; +#[doc = "Field `KEY_0` writer - This bits stores key_0 that is a part of key material."] +pub type KEY_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores key_0 that is a part of key material."] + #[inline(always)] + pub fn key_0(&self) -> KEY_0_R { + KEY_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KEY_0") + .field("key_0", &format_args!("{}", self.key_0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores key_0 that is a part of key material."] + #[inline(always)] + #[must_use] + pub fn key_0(&mut self) -> KEY_0_W { + KEY_0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Key material key_0 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY_0_SPEC; +impl crate::RegisterSpec for KEY_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key_0::R`](R) reader structure"] +impl crate::Readable for KEY_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key_0::W`](W) writer structure"] +impl crate::Writable for KEY_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets KEY_0 to value 0"] +impl crate::Resettable for KEY_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/key_1.rs b/esp32p4/src/aes/key_1.rs new file mode 100644 index 0000000000..ce171bee09 --- /dev/null +++ b/esp32p4/src/aes/key_1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `KEY_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_1` reader - This bits stores key_1 that is a part of key material."] +pub type KEY_1_R = crate::FieldReader; +#[doc = "Field `KEY_1` writer - This bits stores key_1 that is a part of key material."] +pub type KEY_1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores key_1 that is a part of key material."] + #[inline(always)] + pub fn key_1(&self) -> KEY_1_R { + KEY_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KEY_1") + .field("key_1", &format_args!("{}", self.key_1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores key_1 that is a part of key material."] + #[inline(always)] + #[must_use] + pub fn key_1(&mut self) -> KEY_1_W { + KEY_1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Key material key_1 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY_1_SPEC; +impl crate::RegisterSpec for KEY_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key_1::R`](R) reader structure"] +impl crate::Readable for KEY_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key_1::W`](W) writer structure"] +impl crate::Writable for KEY_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets KEY_1 to value 0"] +impl crate::Resettable for KEY_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/key_2.rs b/esp32p4/src/aes/key_2.rs new file mode 100644 index 0000000000..66f99ae1d1 --- /dev/null +++ b/esp32p4/src/aes/key_2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `KEY_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_2` reader - This bits stores key_2 that is a part of key material."] +pub type KEY_2_R = crate::FieldReader; +#[doc = "Field `KEY_2` writer - This bits stores key_2 that is a part of key material."] +pub type KEY_2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores key_2 that is a part of key material."] + #[inline(always)] + pub fn key_2(&self) -> KEY_2_R { + KEY_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KEY_2") + .field("key_2", &format_args!("{}", self.key_2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores key_2 that is a part of key material."] + #[inline(always)] + #[must_use] + pub fn key_2(&mut self) -> KEY_2_W { + KEY_2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Key material key_2 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY_2_SPEC; +impl crate::RegisterSpec for KEY_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key_2::R`](R) reader structure"] +impl crate::Readable for KEY_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key_2::W`](W) writer structure"] +impl crate::Writable for KEY_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets KEY_2 to value 0"] +impl crate::Resettable for KEY_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/key_3.rs b/esp32p4/src/aes/key_3.rs new file mode 100644 index 0000000000..835ab36497 --- /dev/null +++ b/esp32p4/src/aes/key_3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `KEY_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_3` reader - This bits stores key_3 that is a part of key material."] +pub type KEY_3_R = crate::FieldReader; +#[doc = "Field `KEY_3` writer - This bits stores key_3 that is a part of key material."] +pub type KEY_3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores key_3 that is a part of key material."] + #[inline(always)] + pub fn key_3(&self) -> KEY_3_R { + KEY_3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KEY_3") + .field("key_3", &format_args!("{}", self.key_3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores key_3 that is a part of key material."] + #[inline(always)] + #[must_use] + pub fn key_3(&mut self) -> KEY_3_W { + KEY_3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Key material key_3 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY_3_SPEC; +impl crate::RegisterSpec for KEY_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key_3::R`](R) reader structure"] +impl crate::Readable for KEY_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key_3::W`](W) writer structure"] +impl crate::Writable for KEY_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets KEY_3 to value 0"] +impl crate::Resettable for KEY_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/key_4.rs b/esp32p4/src/aes/key_4.rs new file mode 100644 index 0000000000..bf9b7ac3c4 --- /dev/null +++ b/esp32p4/src/aes/key_4.rs @@ -0,0 +1,63 @@ +#[doc = "Register `KEY_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_4` reader - This bits stores key_4 that is a part of key material."] +pub type KEY_4_R = crate::FieldReader; +#[doc = "Field `KEY_4` writer - This bits stores key_4 that is a part of key material."] +pub type KEY_4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores key_4 that is a part of key material."] + #[inline(always)] + pub fn key_4(&self) -> KEY_4_R { + KEY_4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KEY_4") + .field("key_4", &format_args!("{}", self.key_4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores key_4 that is a part of key material."] + #[inline(always)] + #[must_use] + pub fn key_4(&mut self) -> KEY_4_W { + KEY_4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Key material key_4 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY_4_SPEC; +impl crate::RegisterSpec for KEY_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key_4::R`](R) reader structure"] +impl crate::Readable for KEY_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key_4::W`](W) writer structure"] +impl crate::Writable for KEY_4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets KEY_4 to value 0"] +impl crate::Resettable for KEY_4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/key_5.rs b/esp32p4/src/aes/key_5.rs new file mode 100644 index 0000000000..5bebe72920 --- /dev/null +++ b/esp32p4/src/aes/key_5.rs @@ -0,0 +1,63 @@ +#[doc = "Register `KEY_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_5` reader - This bits stores key_5 that is a part of key material."] +pub type KEY_5_R = crate::FieldReader; +#[doc = "Field `KEY_5` writer - This bits stores key_5 that is a part of key material."] +pub type KEY_5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores key_5 that is a part of key material."] + #[inline(always)] + pub fn key_5(&self) -> KEY_5_R { + KEY_5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KEY_5") + .field("key_5", &format_args!("{}", self.key_5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores key_5 that is a part of key material."] + #[inline(always)] + #[must_use] + pub fn key_5(&mut self) -> KEY_5_W { + KEY_5_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Key material key_5 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY_5_SPEC; +impl crate::RegisterSpec for KEY_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key_5::R`](R) reader structure"] +impl crate::Readable for KEY_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key_5::W`](W) writer structure"] +impl crate::Writable for KEY_5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets KEY_5 to value 0"] +impl crate::Resettable for KEY_5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/key_6.rs b/esp32p4/src/aes/key_6.rs new file mode 100644 index 0000000000..1d7d522821 --- /dev/null +++ b/esp32p4/src/aes/key_6.rs @@ -0,0 +1,63 @@ +#[doc = "Register `KEY_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_6` reader - This bits stores key_6 that is a part of key material."] +pub type KEY_6_R = crate::FieldReader; +#[doc = "Field `KEY_6` writer - This bits stores key_6 that is a part of key material."] +pub type KEY_6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores key_6 that is a part of key material."] + #[inline(always)] + pub fn key_6(&self) -> KEY_6_R { + KEY_6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KEY_6") + .field("key_6", &format_args!("{}", self.key_6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores key_6 that is a part of key material."] + #[inline(always)] + #[must_use] + pub fn key_6(&mut self) -> KEY_6_W { + KEY_6_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Key material key_6 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY_6_SPEC; +impl crate::RegisterSpec for KEY_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key_6::R`](R) reader structure"] +impl crate::Readable for KEY_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key_6::W`](W) writer structure"] +impl crate::Writable for KEY_6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets KEY_6 to value 0"] +impl crate::Resettable for KEY_6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/key_7.rs b/esp32p4/src/aes/key_7.rs new file mode 100644 index 0000000000..899cc2d993 --- /dev/null +++ b/esp32p4/src/aes/key_7.rs @@ -0,0 +1,63 @@ +#[doc = "Register `KEY_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_7` reader - This bits stores key_7 that is a part of key material."] +pub type KEY_7_R = crate::FieldReader; +#[doc = "Field `KEY_7` writer - This bits stores key_7 that is a part of key material."] +pub type KEY_7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores key_7 that is a part of key material."] + #[inline(always)] + pub fn key_7(&self) -> KEY_7_R { + KEY_7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KEY_7") + .field("key_7", &format_args!("{}", self.key_7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores key_7 that is a part of key material."] + #[inline(always)] + #[must_use] + pub fn key_7(&mut self) -> KEY_7_W { + KEY_7_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Key material key_7 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`key_7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key_7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY_7_SPEC; +impl crate::RegisterSpec for KEY_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key_7::R`](R) reader structure"] +impl crate::Readable for KEY_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key_7::W`](W) writer structure"] +impl crate::Writable for KEY_7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets KEY_7 to value 0"] +impl crate::Resettable for KEY_7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/mode.rs b/esp32p4/src/aes/mode.rs new file mode 100644 index 0000000000..282263a359 --- /dev/null +++ b/esp32p4/src/aes/mode.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MODE` reader"] +pub type R = crate::R; +#[doc = "Register `MODE` writer"] +pub type W = crate::W; +#[doc = "Field `MODE` reader - This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256."] +pub type MODE_R = crate::FieldReader; +#[doc = "Field `MODE` writer - This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256."] +pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MODE") + .field("mode", &format_args!("{}", self.mode().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AES Mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MODE_SPEC; +impl crate::RegisterSpec for MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mode::R`](R) reader structure"] +impl crate::Readable for MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"] +impl crate::Writable for MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MODE to value 0"] +impl crate::Resettable for MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/remainder_bit_num.rs b/esp32p4/src/aes/remainder_bit_num.rs new file mode 100644 index 0000000000..a1b2df7e3f --- /dev/null +++ b/esp32p4/src/aes/remainder_bit_num.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REMAINDER_BIT_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `REMAINDER_BIT_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `REMAINDER_BIT_NUM` reader - Those bits stores the number of remainder bit."] +pub type REMAINDER_BIT_NUM_R = crate::FieldReader; +#[doc = "Field `REMAINDER_BIT_NUM` writer - Those bits stores the number of remainder bit."] +pub type REMAINDER_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Those bits stores the number of remainder bit."] + #[inline(always)] + pub fn remainder_bit_num(&self) -> REMAINDER_BIT_NUM_R { + REMAINDER_BIT_NUM_R::new((self.bits & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REMAINDER_BIT_NUM") + .field( + "remainder_bit_num", + &format_args!("{}", self.remainder_bit_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Those bits stores the number of remainder bit."] + #[inline(always)] + #[must_use] + pub fn remainder_bit_num(&mut self) -> REMAINDER_BIT_NUM_W { + REMAINDER_BIT_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AES remainder bit number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`remainder_bit_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`remainder_bit_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REMAINDER_BIT_NUM_SPEC; +impl crate::RegisterSpec for REMAINDER_BIT_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`remainder_bit_num::R`](R) reader structure"] +impl crate::Readable for REMAINDER_BIT_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`remainder_bit_num::W`](W) writer structure"] +impl crate::Writable for REMAINDER_BIT_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REMAINDER_BIT_NUM to value 0"] +impl crate::Resettable for REMAINDER_BIT_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/state.rs b/esp32p4/src/aes/state.rs new file mode 100644 index 0000000000..516d73de56 --- /dev/null +++ b/esp32p4/src/aes/state.rs @@ -0,0 +1,36 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +#[doc = "Field `STATE` reader - Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done."] +pub type STATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done."] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATE") + .field("state", &format_args!("{}", self.state().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "AES state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATE_SPEC; +impl crate::RegisterSpec for STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for STATE_SPEC {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for STATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/t0_mem.rs b/esp32p4/src/aes/t0_mem.rs new file mode 100644 index 0000000000..987009c606 --- /dev/null +++ b/esp32p4/src/aes/t0_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `T0_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `T0_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores T0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T0_MEM_SPEC; +impl crate::RegisterSpec for T0_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`t0_mem::R`](R) reader structure"] +impl crate::Readable for T0_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`t0_mem::W`](W) writer structure"] +impl crate::Writable for T0_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets T0_MEM[%s] to value 0"] +impl crate::Resettable for T0_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/text_in_0.rs b/esp32p4/src/aes/text_in_0.rs new file mode 100644 index 0000000000..7a21b4534a --- /dev/null +++ b/esp32p4/src/aes/text_in_0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TEXT_IN_0` reader"] +pub type R = crate::R; +#[doc = "Register `TEXT_IN_0` writer"] +pub type W = crate::W; +#[doc = "Field `TEXT_IN_0` reader - This bits stores text_in_0 that is a part of source text material."] +pub type TEXT_IN_0_R = crate::FieldReader; +#[doc = "Field `TEXT_IN_0` writer - This bits stores text_in_0 that is a part of source text material."] +pub type TEXT_IN_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores text_in_0 that is a part of source text material."] + #[inline(always)] + pub fn text_in_0(&self) -> TEXT_IN_0_R { + TEXT_IN_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TEXT_IN_0") + .field("text_in_0", &format_args!("{}", self.text_in_0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores text_in_0 that is a part of source text material."] + #[inline(always)] + #[must_use] + pub fn text_in_0(&mut self) -> TEXT_IN_0_W { + TEXT_IN_0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "source text material text_in_0 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_in_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_in_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TEXT_IN_0_SPEC; +impl crate::RegisterSpec for TEXT_IN_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`text_in_0::R`](R) reader structure"] +impl crate::Readable for TEXT_IN_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`text_in_0::W`](W) writer structure"] +impl crate::Writable for TEXT_IN_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TEXT_IN_0 to value 0"] +impl crate::Resettable for TEXT_IN_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/text_in_1.rs b/esp32p4/src/aes/text_in_1.rs new file mode 100644 index 0000000000..7618e5672a --- /dev/null +++ b/esp32p4/src/aes/text_in_1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TEXT_IN_1` reader"] +pub type R = crate::R; +#[doc = "Register `TEXT_IN_1` writer"] +pub type W = crate::W; +#[doc = "Field `TEXT_IN_1` reader - This bits stores text_in_1 that is a part of source text material."] +pub type TEXT_IN_1_R = crate::FieldReader; +#[doc = "Field `TEXT_IN_1` writer - This bits stores text_in_1 that is a part of source text material."] +pub type TEXT_IN_1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores text_in_1 that is a part of source text material."] + #[inline(always)] + pub fn text_in_1(&self) -> TEXT_IN_1_R { + TEXT_IN_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TEXT_IN_1") + .field("text_in_1", &format_args!("{}", self.text_in_1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores text_in_1 that is a part of source text material."] + #[inline(always)] + #[must_use] + pub fn text_in_1(&mut self) -> TEXT_IN_1_W { + TEXT_IN_1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "source text material text_in_1 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_in_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_in_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TEXT_IN_1_SPEC; +impl crate::RegisterSpec for TEXT_IN_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`text_in_1::R`](R) reader structure"] +impl crate::Readable for TEXT_IN_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`text_in_1::W`](W) writer structure"] +impl crate::Writable for TEXT_IN_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TEXT_IN_1 to value 0"] +impl crate::Resettable for TEXT_IN_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/text_in_2.rs b/esp32p4/src/aes/text_in_2.rs new file mode 100644 index 0000000000..0b35c6f027 --- /dev/null +++ b/esp32p4/src/aes/text_in_2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TEXT_IN_2` reader"] +pub type R = crate::R; +#[doc = "Register `TEXT_IN_2` writer"] +pub type W = crate::W; +#[doc = "Field `TEXT_IN_2` reader - This bits stores text_in_2 that is a part of source text material."] +pub type TEXT_IN_2_R = crate::FieldReader; +#[doc = "Field `TEXT_IN_2` writer - This bits stores text_in_2 that is a part of source text material."] +pub type TEXT_IN_2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores text_in_2 that is a part of source text material."] + #[inline(always)] + pub fn text_in_2(&self) -> TEXT_IN_2_R { + TEXT_IN_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TEXT_IN_2") + .field("text_in_2", &format_args!("{}", self.text_in_2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores text_in_2 that is a part of source text material."] + #[inline(always)] + #[must_use] + pub fn text_in_2(&mut self) -> TEXT_IN_2_W { + TEXT_IN_2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "source text material text_in_2 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_in_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_in_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TEXT_IN_2_SPEC; +impl crate::RegisterSpec for TEXT_IN_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`text_in_2::R`](R) reader structure"] +impl crate::Readable for TEXT_IN_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`text_in_2::W`](W) writer structure"] +impl crate::Writable for TEXT_IN_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TEXT_IN_2 to value 0"] +impl crate::Resettable for TEXT_IN_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/text_in_3.rs b/esp32p4/src/aes/text_in_3.rs new file mode 100644 index 0000000000..eb3b1ccbdf --- /dev/null +++ b/esp32p4/src/aes/text_in_3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TEXT_IN_3` reader"] +pub type R = crate::R; +#[doc = "Register `TEXT_IN_3` writer"] +pub type W = crate::W; +#[doc = "Field `TEXT_IN_3` reader - This bits stores text_in_3 that is a part of source text material."] +pub type TEXT_IN_3_R = crate::FieldReader; +#[doc = "Field `TEXT_IN_3` writer - This bits stores text_in_3 that is a part of source text material."] +pub type TEXT_IN_3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores text_in_3 that is a part of source text material."] + #[inline(always)] + pub fn text_in_3(&self) -> TEXT_IN_3_R { + TEXT_IN_3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TEXT_IN_3") + .field("text_in_3", &format_args!("{}", self.text_in_3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores text_in_3 that is a part of source text material."] + #[inline(always)] + #[must_use] + pub fn text_in_3(&mut self) -> TEXT_IN_3_W { + TEXT_IN_3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "source text material text_in_3 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_in_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_in_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TEXT_IN_3_SPEC; +impl crate::RegisterSpec for TEXT_IN_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`text_in_3::R`](R) reader structure"] +impl crate::Readable for TEXT_IN_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`text_in_3::W`](W) writer structure"] +impl crate::Writable for TEXT_IN_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TEXT_IN_3 to value 0"] +impl crate::Resettable for TEXT_IN_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/text_out_0.rs b/esp32p4/src/aes/text_out_0.rs new file mode 100644 index 0000000000..d538d618f6 --- /dev/null +++ b/esp32p4/src/aes/text_out_0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TEXT_OUT_0` reader"] +pub type R = crate::R; +#[doc = "Register `TEXT_OUT_0` writer"] +pub type W = crate::W; +#[doc = "Field `TEXT_OUT_0` reader - This bits stores text_out_0 that is a part of result text material."] +pub type TEXT_OUT_0_R = crate::FieldReader; +#[doc = "Field `TEXT_OUT_0` writer - This bits stores text_out_0 that is a part of result text material."] +pub type TEXT_OUT_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores text_out_0 that is a part of result text material."] + #[inline(always)] + pub fn text_out_0(&self) -> TEXT_OUT_0_R { + TEXT_OUT_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TEXT_OUT_0") + .field("text_out_0", &format_args!("{}", self.text_out_0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores text_out_0 that is a part of result text material."] + #[inline(always)] + #[must_use] + pub fn text_out_0(&mut self) -> TEXT_OUT_0_W { + TEXT_OUT_0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "result text material text_out_0 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_out_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_out_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TEXT_OUT_0_SPEC; +impl crate::RegisterSpec for TEXT_OUT_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`text_out_0::R`](R) reader structure"] +impl crate::Readable for TEXT_OUT_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`text_out_0::W`](W) writer structure"] +impl crate::Writable for TEXT_OUT_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TEXT_OUT_0 to value 0"] +impl crate::Resettable for TEXT_OUT_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/text_out_1.rs b/esp32p4/src/aes/text_out_1.rs new file mode 100644 index 0000000000..8898f8f39e --- /dev/null +++ b/esp32p4/src/aes/text_out_1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TEXT_OUT_1` reader"] +pub type R = crate::R; +#[doc = "Register `TEXT_OUT_1` writer"] +pub type W = crate::W; +#[doc = "Field `TEXT_OUT_1` reader - This bits stores text_out_1 that is a part of result text material."] +pub type TEXT_OUT_1_R = crate::FieldReader; +#[doc = "Field `TEXT_OUT_1` writer - This bits stores text_out_1 that is a part of result text material."] +pub type TEXT_OUT_1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores text_out_1 that is a part of result text material."] + #[inline(always)] + pub fn text_out_1(&self) -> TEXT_OUT_1_R { + TEXT_OUT_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TEXT_OUT_1") + .field("text_out_1", &format_args!("{}", self.text_out_1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores text_out_1 that is a part of result text material."] + #[inline(always)] + #[must_use] + pub fn text_out_1(&mut self) -> TEXT_OUT_1_W { + TEXT_OUT_1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "result text material text_out_1 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_out_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_out_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TEXT_OUT_1_SPEC; +impl crate::RegisterSpec for TEXT_OUT_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`text_out_1::R`](R) reader structure"] +impl crate::Readable for TEXT_OUT_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`text_out_1::W`](W) writer structure"] +impl crate::Writable for TEXT_OUT_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TEXT_OUT_1 to value 0"] +impl crate::Resettable for TEXT_OUT_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/text_out_2.rs b/esp32p4/src/aes/text_out_2.rs new file mode 100644 index 0000000000..4bd79eb3ba --- /dev/null +++ b/esp32p4/src/aes/text_out_2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TEXT_OUT_2` reader"] +pub type R = crate::R; +#[doc = "Register `TEXT_OUT_2` writer"] +pub type W = crate::W; +#[doc = "Field `TEXT_OUT_2` reader - This bits stores text_out_2 that is a part of result text material."] +pub type TEXT_OUT_2_R = crate::FieldReader; +#[doc = "Field `TEXT_OUT_2` writer - This bits stores text_out_2 that is a part of result text material."] +pub type TEXT_OUT_2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores text_out_2 that is a part of result text material."] + #[inline(always)] + pub fn text_out_2(&self) -> TEXT_OUT_2_R { + TEXT_OUT_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TEXT_OUT_2") + .field("text_out_2", &format_args!("{}", self.text_out_2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores text_out_2 that is a part of result text material."] + #[inline(always)] + #[must_use] + pub fn text_out_2(&mut self) -> TEXT_OUT_2_W { + TEXT_OUT_2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "result text material text_out_2 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_out_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_out_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TEXT_OUT_2_SPEC; +impl crate::RegisterSpec for TEXT_OUT_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`text_out_2::R`](R) reader structure"] +impl crate::Readable for TEXT_OUT_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`text_out_2::W`](W) writer structure"] +impl crate::Writable for TEXT_OUT_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TEXT_OUT_2 to value 0"] +impl crate::Resettable for TEXT_OUT_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/text_out_3.rs b/esp32p4/src/aes/text_out_3.rs new file mode 100644 index 0000000000..d9934740bd --- /dev/null +++ b/esp32p4/src/aes/text_out_3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TEXT_OUT_3` reader"] +pub type R = crate::R; +#[doc = "Register `TEXT_OUT_3` writer"] +pub type W = crate::W; +#[doc = "Field `TEXT_OUT_3` reader - This bits stores text_out_3 that is a part of result text material."] +pub type TEXT_OUT_3_R = crate::FieldReader; +#[doc = "Field `TEXT_OUT_3` writer - This bits stores text_out_3 that is a part of result text material."] +pub type TEXT_OUT_3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This bits stores text_out_3 that is a part of result text material."] + #[inline(always)] + pub fn text_out_3(&self) -> TEXT_OUT_3_R { + TEXT_OUT_3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TEXT_OUT_3") + .field("text_out_3", &format_args!("{}", self.text_out_3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This bits stores text_out_3 that is a part of result text material."] + #[inline(always)] + #[must_use] + pub fn text_out_3(&mut self) -> TEXT_OUT_3_W { + TEXT_OUT_3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "result text material text_out_3 configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`text_out_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`text_out_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TEXT_OUT_3_SPEC; +impl crate::RegisterSpec for TEXT_OUT_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`text_out_3::R`](R) reader structure"] +impl crate::Readable for TEXT_OUT_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`text_out_3::W`](W) writer structure"] +impl crate::Writable for TEXT_OUT_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TEXT_OUT_3 to value 0"] +impl crate::Resettable for TEXT_OUT_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/aes/trigger.rs b/esp32p4/src/aes/trigger.rs new file mode 100644 index 0000000000..1f48437d41 --- /dev/null +++ b/esp32p4/src/aes/trigger.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRIGGER` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGGER` writer - Set this bit to start AES calculation."] +pub type TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to start AES calculation."] + #[inline(always)] + #[must_use] + pub fn trigger(&mut self) -> TRIGGER_W { + TRIGGER_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AES trigger register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trigger::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRIGGER_SPEC; +impl crate::RegisterSpec for TRIGGER_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`trigger::W`](W) writer structure"] +impl crate::Writable for TRIGGER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TRIGGER to value 0"] +impl crate::Resettable for TRIGGER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug.rs b/esp32p4/src/assist_debug.rs new file mode 100644 index 0000000000..3c098e5fbb --- /dev/null +++ b/esp32p4/src/assist_debug.rs @@ -0,0 +1,682 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + core_0_intr_ena: CORE_0_INTR_ENA, + core_0_intr_raw: CORE_0_INTR_RAW, + core_0_intr_rls: CORE_0_INTR_RLS, + core_0_intr_clr: CORE_0_INTR_CLR, + core_0_area_dram0_0_min: CORE_0_AREA_DRAM0_0_MIN, + core_0_area_dram0_0_max: CORE_0_AREA_DRAM0_0_MAX, + core_0_area_dram0_1_min: CORE_0_AREA_DRAM0_1_MIN, + core_0_area_dram0_1_max: CORE_0_AREA_DRAM0_1_MAX, + core_0_area_pif_0_min: CORE_0_AREA_PIF_0_MIN, + core_0_area_pif_0_max: CORE_0_AREA_PIF_0_MAX, + core_0_area_pif_1_min: CORE_0_AREA_PIF_1_MIN, + core_0_area_pif_1_max: CORE_0_AREA_PIF_1_MAX, + core_0_area_pc: CORE_0_AREA_PC, + core_0_area_sp: CORE_0_AREA_SP, + core_0_sp_min: CORE_0_SP_MIN, + core_0_sp_max: CORE_0_SP_MAX, + core_0_sp_pc: CORE_0_SP_PC, + core_0_rcd_en: CORE_0_RCD_EN, + core_0_rcd_pdebugpc: CORE_0_RCD_PDEBUGPC, + core_0_rcd_pdebugsp: CORE_0_RCD_PDEBUGSP, + core_0_iram0_exception_monitor_0: CORE_0_IRAM0_EXCEPTION_MONITOR_0, + core_0_iram0_exception_monitor_1: CORE_0_IRAM0_EXCEPTION_MONITOR_1, + core_0_dram0_exception_monitor_0: CORE_0_DRAM0_EXCEPTION_MONITOR_0, + core_0_dram0_exception_monitor_1: CORE_0_DRAM0_EXCEPTION_MONITOR_1, + core_0_dram0_exception_monitor_2: CORE_0_DRAM0_EXCEPTION_MONITOR_2, + core_0_dram0_exception_monitor_3: CORE_0_DRAM0_EXCEPTION_MONITOR_3, + core_0_dram0_exception_monitor_4: CORE_0_DRAM0_EXCEPTION_MONITOR_4, + core_0_dram0_exception_monitor_5: CORE_0_DRAM0_EXCEPTION_MONITOR_5, + core_0_lastpc_before_exception: CORE_0_LASTPC_BEFORE_EXCEPTION, + core_0_debug_mode: CORE_0_DEBUG_MODE, + _reserved30: [u8; 0x08], + core_1_intr_ena: CORE_1_INTR_ENA, + core_1_intr_raw: CORE_1_INTR_RAW, + core_1_intr_rls: CORE_1_INTR_RLS, + core_1_intr_clr: CORE_1_INTR_CLR, + core_1_area_dram0_0_min: CORE_1_AREA_DRAM0_0_MIN, + core_1_area_dram0_0_max: CORE_1_AREA_DRAM0_0_MAX, + core_1_area_dram0_1_min: CORE_1_AREA_DRAM0_1_MIN, + core_1_area_dram0_1_max: CORE_1_AREA_DRAM0_1_MAX, + core_1_area_pif_0_min: CORE_1_AREA_PIF_0_MIN, + core_1_area_pif_0_max: CORE_1_AREA_PIF_0_MAX, + core_1_area_pif_1_min: CORE_1_AREA_PIF_1_MIN, + core_1_area_pif_1_max: CORE_1_AREA_PIF_1_MAX, + core_1_area_pc: CORE_1_AREA_PC, + core_1_area_sp: CORE_1_AREA_SP, + core_1_sp_min: CORE_1_SP_MIN, + core_1_sp_max: CORE_1_SP_MAX, + core_1_sp_pc: CORE_1_SP_PC, + core_1_rcd_en: CORE_1_RCD_EN, + core_1_rcd_pdebugpc: CORE_1_RCD_PDEBUGPC, + core_1_rcd_pdebugsp: CORE_1_RCD_PDEBUGSP, + core_1_iram0_exception_monitor_0: CORE_1_IRAM0_EXCEPTION_MONITOR_0, + core_1_iram0_exception_monitor_1: CORE_1_IRAM0_EXCEPTION_MONITOR_1, + core_1_dram0_exception_monitor_0: CORE_1_DRAM0_EXCEPTION_MONITOR_0, + core_1_dram0_exception_monitor_1: CORE_1_DRAM0_EXCEPTION_MONITOR_1, + core_1_dram0_exception_monitor_2: CORE_1_DRAM0_EXCEPTION_MONITOR_2, + core_1_dram0_exception_monitor_3: CORE_1_DRAM0_EXCEPTION_MONITOR_3, + core_1_dram0_exception_monitor_4: CORE_1_DRAM0_EXCEPTION_MONITOR_4, + core_1_dram0_exception_monitor_5: CORE_1_DRAM0_EXCEPTION_MONITOR_5, + core_1_lastpc_before_exception: CORE_1_LASTPC_BEFORE_EXCEPTION, + core_1_debug_mode: CORE_1_DEBUG_MODE, + _reserved60: [u8; 0x08], + core_x_iram0_dram0_exception_monitor_0: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0, + core_x_iram0_dram0_exception_monitor_1: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1, + clock_gate: CLOCK_GATE, + _reserved63: [u8; 0x02f0], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - core0 monitor enable configuration register"] + #[inline(always)] + pub const fn core_0_intr_ena(&self) -> &CORE_0_INTR_ENA { + &self.core_0_intr_ena + } + #[doc = "0x04 - core0 monitor interrupt status register"] + #[inline(always)] + pub const fn core_0_intr_raw(&self) -> &CORE_0_INTR_RAW { + &self.core_0_intr_raw + } + #[doc = "0x08 - core0 monitor interrupt enable register"] + #[inline(always)] + pub const fn core_0_intr_rls(&self) -> &CORE_0_INTR_RLS { + &self.core_0_intr_rls + } + #[doc = "0x0c - core0 monitor interrupt clr register"] + #[inline(always)] + pub const fn core_0_intr_clr(&self) -> &CORE_0_INTR_CLR { + &self.core_0_intr_clr + } + #[doc = "0x10 - core0 dram0 region0 addr configuration register"] + #[inline(always)] + pub const fn core_0_area_dram0_0_min(&self) -> &CORE_0_AREA_DRAM0_0_MIN { + &self.core_0_area_dram0_0_min + } + #[doc = "0x14 - core0 dram0 region0 addr configuration register"] + #[inline(always)] + pub const fn core_0_area_dram0_0_max(&self) -> &CORE_0_AREA_DRAM0_0_MAX { + &self.core_0_area_dram0_0_max + } + #[doc = "0x18 - core0 dram0 region1 addr configuration register"] + #[inline(always)] + pub const fn core_0_area_dram0_1_min(&self) -> &CORE_0_AREA_DRAM0_1_MIN { + &self.core_0_area_dram0_1_min + } + #[doc = "0x1c - core0 dram0 region1 addr configuration register"] + #[inline(always)] + pub const fn core_0_area_dram0_1_max(&self) -> &CORE_0_AREA_DRAM0_1_MAX { + &self.core_0_area_dram0_1_max + } + #[doc = "0x20 - core0 PIF region0 addr configuration register"] + #[inline(always)] + pub const fn core_0_area_pif_0_min(&self) -> &CORE_0_AREA_PIF_0_MIN { + &self.core_0_area_pif_0_min + } + #[doc = "0x24 - core0 PIF region0 addr configuration register"] + #[inline(always)] + pub const fn core_0_area_pif_0_max(&self) -> &CORE_0_AREA_PIF_0_MAX { + &self.core_0_area_pif_0_max + } + #[doc = "0x28 - core0 PIF region1 addr configuration register"] + #[inline(always)] + pub const fn core_0_area_pif_1_min(&self) -> &CORE_0_AREA_PIF_1_MIN { + &self.core_0_area_pif_1_min + } + #[doc = "0x2c - core0 PIF region1 addr configuration register"] + #[inline(always)] + pub const fn core_0_area_pif_1_max(&self) -> &CORE_0_AREA_PIF_1_MAX { + &self.core_0_area_pif_1_max + } + #[doc = "0x30 - core0 area pc status register"] + #[inline(always)] + pub const fn core_0_area_pc(&self) -> &CORE_0_AREA_PC { + &self.core_0_area_pc + } + #[doc = "0x34 - core0 area sp status register"] + #[inline(always)] + pub const fn core_0_area_sp(&self) -> &CORE_0_AREA_SP { + &self.core_0_area_sp + } + #[doc = "0x38 - stack min value"] + #[inline(always)] + pub const fn core_0_sp_min(&self) -> &CORE_0_SP_MIN { + &self.core_0_sp_min + } + #[doc = "0x3c - stack max value"] + #[inline(always)] + pub const fn core_0_sp_max(&self) -> &CORE_0_SP_MAX { + &self.core_0_sp_max + } + #[doc = "0x40 - stack monitor pc status register"] + #[inline(always)] + pub const fn core_0_sp_pc(&self) -> &CORE_0_SP_PC { + &self.core_0_sp_pc + } + #[doc = "0x44 - record enable configuration register"] + #[inline(always)] + pub const fn core_0_rcd_en(&self) -> &CORE_0_RCD_EN { + &self.core_0_rcd_en + } + #[doc = "0x48 - record status regsiter"] + #[inline(always)] + pub const fn core_0_rcd_pdebugpc(&self) -> &CORE_0_RCD_PDEBUGPC { + &self.core_0_rcd_pdebugpc + } + #[doc = "0x4c - record status regsiter"] + #[inline(always)] + pub const fn core_0_rcd_pdebugsp(&self) -> &CORE_0_RCD_PDEBUGSP { + &self.core_0_rcd_pdebugsp + } + #[doc = "0x50 - exception monitor status register0"] + #[inline(always)] + pub const fn core_0_iram0_exception_monitor_0(&self) -> &CORE_0_IRAM0_EXCEPTION_MONITOR_0 { + &self.core_0_iram0_exception_monitor_0 + } + #[doc = "0x54 - exception monitor status register1"] + #[inline(always)] + pub const fn core_0_iram0_exception_monitor_1(&self) -> &CORE_0_IRAM0_EXCEPTION_MONITOR_1 { + &self.core_0_iram0_exception_monitor_1 + } + #[doc = "0x58 - exception monitor status register2"] + #[inline(always)] + pub const fn core_0_dram0_exception_monitor_0(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_0 { + &self.core_0_dram0_exception_monitor_0 + } + #[doc = "0x5c - exception monitor status register3"] + #[inline(always)] + pub const fn core_0_dram0_exception_monitor_1(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_1 { + &self.core_0_dram0_exception_monitor_1 + } + #[doc = "0x60 - exception monitor status register4"] + #[inline(always)] + pub const fn core_0_dram0_exception_monitor_2(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_2 { + &self.core_0_dram0_exception_monitor_2 + } + #[doc = "0x64 - exception monitor status register5"] + #[inline(always)] + pub const fn core_0_dram0_exception_monitor_3(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_3 { + &self.core_0_dram0_exception_monitor_3 + } + #[doc = "0x68 - exception monitor status register6"] + #[inline(always)] + pub const fn core_0_dram0_exception_monitor_4(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_4 { + &self.core_0_dram0_exception_monitor_4 + } + #[doc = "0x6c - exception monitor status register7"] + #[inline(always)] + pub const fn core_0_dram0_exception_monitor_5(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_5 { + &self.core_0_dram0_exception_monitor_5 + } + #[doc = "0x70 - cpu status register"] + #[inline(always)] + pub const fn core_0_lastpc_before_exception(&self) -> &CORE_0_LASTPC_BEFORE_EXCEPTION { + &self.core_0_lastpc_before_exception + } + #[doc = "0x74 - cpu status register"] + #[inline(always)] + pub const fn core_0_debug_mode(&self) -> &CORE_0_DEBUG_MODE { + &self.core_0_debug_mode + } + #[doc = "0x80 - core1 monitor enable configuration register"] + #[inline(always)] + pub const fn core_1_intr_ena(&self) -> &CORE_1_INTR_ENA { + &self.core_1_intr_ena + } + #[doc = "0x84 - core1 monitor interrupt status register"] + #[inline(always)] + pub const fn core_1_intr_raw(&self) -> &CORE_1_INTR_RAW { + &self.core_1_intr_raw + } + #[doc = "0x88 - core1 monitor interrupt enable register"] + #[inline(always)] + pub const fn core_1_intr_rls(&self) -> &CORE_1_INTR_RLS { + &self.core_1_intr_rls + } + #[doc = "0x8c - core1 monitor interrupt clr register"] + #[inline(always)] + pub const fn core_1_intr_clr(&self) -> &CORE_1_INTR_CLR { + &self.core_1_intr_clr + } + #[doc = "0x90 - core1 dram0 region0 addr configuration register"] + #[inline(always)] + pub const fn core_1_area_dram0_0_min(&self) -> &CORE_1_AREA_DRAM0_0_MIN { + &self.core_1_area_dram0_0_min + } + #[doc = "0x94 - core1 dram0 region0 addr configuration register"] + #[inline(always)] + pub const fn core_1_area_dram0_0_max(&self) -> &CORE_1_AREA_DRAM0_0_MAX { + &self.core_1_area_dram0_0_max + } + #[doc = "0x98 - core1 dram0 region1 addr configuration register"] + #[inline(always)] + pub const fn core_1_area_dram0_1_min(&self) -> &CORE_1_AREA_DRAM0_1_MIN { + &self.core_1_area_dram0_1_min + } + #[doc = "0x9c - core1 dram0 region1 addr configuration register"] + #[inline(always)] + pub const fn core_1_area_dram0_1_max(&self) -> &CORE_1_AREA_DRAM0_1_MAX { + &self.core_1_area_dram0_1_max + } + #[doc = "0xa0 - core1 PIF region0 addr configuration register"] + #[inline(always)] + pub const fn core_1_area_pif_0_min(&self) -> &CORE_1_AREA_PIF_0_MIN { + &self.core_1_area_pif_0_min + } + #[doc = "0xa4 - core1 PIF region0 addr configuration register"] + #[inline(always)] + pub const fn core_1_area_pif_0_max(&self) -> &CORE_1_AREA_PIF_0_MAX { + &self.core_1_area_pif_0_max + } + #[doc = "0xa8 - core1 PIF region1 addr configuration register"] + #[inline(always)] + pub const fn core_1_area_pif_1_min(&self) -> &CORE_1_AREA_PIF_1_MIN { + &self.core_1_area_pif_1_min + } + #[doc = "0xac - core1 PIF region1 addr configuration register"] + #[inline(always)] + pub const fn core_1_area_pif_1_max(&self) -> &CORE_1_AREA_PIF_1_MAX { + &self.core_1_area_pif_1_max + } + #[doc = "0xb0 - core1 area pc status register"] + #[inline(always)] + pub const fn core_1_area_pc(&self) -> &CORE_1_AREA_PC { + &self.core_1_area_pc + } + #[doc = "0xb4 - core1 area sp status register"] + #[inline(always)] + pub const fn core_1_area_sp(&self) -> &CORE_1_AREA_SP { + &self.core_1_area_sp + } + #[doc = "0xb8 - stack min value"] + #[inline(always)] + pub const fn core_1_sp_min(&self) -> &CORE_1_SP_MIN { + &self.core_1_sp_min + } + #[doc = "0xbc - stack max value"] + #[inline(always)] + pub const fn core_1_sp_max(&self) -> &CORE_1_SP_MAX { + &self.core_1_sp_max + } + #[doc = "0xc0 - stack monitor pc status register"] + #[inline(always)] + pub const fn core_1_sp_pc(&self) -> &CORE_1_SP_PC { + &self.core_1_sp_pc + } + #[doc = "0xc4 - record enable configuration register"] + #[inline(always)] + pub const fn core_1_rcd_en(&self) -> &CORE_1_RCD_EN { + &self.core_1_rcd_en + } + #[doc = "0xc8 - record status regsiter"] + #[inline(always)] + pub const fn core_1_rcd_pdebugpc(&self) -> &CORE_1_RCD_PDEBUGPC { + &self.core_1_rcd_pdebugpc + } + #[doc = "0xcc - record status regsiter"] + #[inline(always)] + pub const fn core_1_rcd_pdebugsp(&self) -> &CORE_1_RCD_PDEBUGSP { + &self.core_1_rcd_pdebugsp + } + #[doc = "0xd0 - exception monitor status register0"] + #[inline(always)] + pub const fn core_1_iram0_exception_monitor_0(&self) -> &CORE_1_IRAM0_EXCEPTION_MONITOR_0 { + &self.core_1_iram0_exception_monitor_0 + } + #[doc = "0xd4 - exception monitor status register1"] + #[inline(always)] + pub const fn core_1_iram0_exception_monitor_1(&self) -> &CORE_1_IRAM0_EXCEPTION_MONITOR_1 { + &self.core_1_iram0_exception_monitor_1 + } + #[doc = "0xd8 - exception monitor status register2"] + #[inline(always)] + pub const fn core_1_dram0_exception_monitor_0(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_0 { + &self.core_1_dram0_exception_monitor_0 + } + #[doc = "0xdc - exception monitor status register3"] + #[inline(always)] + pub const fn core_1_dram0_exception_monitor_1(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_1 { + &self.core_1_dram0_exception_monitor_1 + } + #[doc = "0xe0 - exception monitor status register4"] + #[inline(always)] + pub const fn core_1_dram0_exception_monitor_2(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_2 { + &self.core_1_dram0_exception_monitor_2 + } + #[doc = "0xe4 - exception monitor status register5"] + #[inline(always)] + pub const fn core_1_dram0_exception_monitor_3(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_3 { + &self.core_1_dram0_exception_monitor_3 + } + #[doc = "0xe8 - exception monitor status register6"] + #[inline(always)] + pub const fn core_1_dram0_exception_monitor_4(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_4 { + &self.core_1_dram0_exception_monitor_4 + } + #[doc = "0xec - exception monitor status register7"] + #[inline(always)] + pub const fn core_1_dram0_exception_monitor_5(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_5 { + &self.core_1_dram0_exception_monitor_5 + } + #[doc = "0xf0 - cpu status register"] + #[inline(always)] + pub const fn core_1_lastpc_before_exception(&self) -> &CORE_1_LASTPC_BEFORE_EXCEPTION { + &self.core_1_lastpc_before_exception + } + #[doc = "0xf4 - cpu status register"] + #[inline(always)] + pub const fn core_1_debug_mode(&self) -> &CORE_1_DEBUG_MODE { + &self.core_1_debug_mode + } + #[doc = "0x100 - exception monitor status register6"] + #[inline(always)] + pub const fn core_x_iram0_dram0_exception_monitor_0( + &self, + ) -> &CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 { + &self.core_x_iram0_dram0_exception_monitor_0 + } + #[doc = "0x104 - exception monitor status register7"] + #[inline(always)] + pub const fn core_x_iram0_dram0_exception_monitor_1( + &self, + ) -> &CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 { + &self.core_x_iram0_dram0_exception_monitor_1 + } + #[doc = "0x108 - clock register"] + #[inline(always)] + pub const fn clock_gate(&self) -> &CLOCK_GATE { + &self.clock_gate + } + #[doc = "0x3fc - version register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "CORE_0_INTR_ENA (rw) register accessor: core0 monitor enable configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_intr_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_intr_ena`] module"] +pub type CORE_0_INTR_ENA = crate::Reg; +#[doc = "core0 monitor enable configuration register"] +pub mod core_0_intr_ena; +#[doc = "CORE_0_INTR_RAW (r) register accessor: core0 monitor interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_intr_raw`] module"] +pub type CORE_0_INTR_RAW = crate::Reg; +#[doc = "core0 monitor interrupt status register"] +pub mod core_0_intr_raw; +#[doc = "CORE_0_INTR_RLS (rw) register accessor: core0 monitor interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_rls::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_intr_rls::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_intr_rls`] module"] +pub type CORE_0_INTR_RLS = crate::Reg; +#[doc = "core0 monitor interrupt enable register"] +pub mod core_0_intr_rls; +#[doc = "CORE_0_INTR_CLR (w) register accessor: core0 monitor interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_intr_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_intr_clr`] module"] +pub type CORE_0_INTR_CLR = crate::Reg; +#[doc = "core0 monitor interrupt clr register"] +pub mod core_0_intr_clr; +#[doc = "CORE_0_AREA_DRAM0_0_MIN (rw) register accessor: core0 dram0 region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_dram0_0_min::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_dram0_0_min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_dram0_0_min`] module"] +pub type CORE_0_AREA_DRAM0_0_MIN = + crate::Reg; +#[doc = "core0 dram0 region0 addr configuration register"] +pub mod core_0_area_dram0_0_min; +#[doc = "CORE_0_AREA_DRAM0_0_MAX (rw) register accessor: core0 dram0 region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_dram0_0_max::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_dram0_0_max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_dram0_0_max`] module"] +pub type CORE_0_AREA_DRAM0_0_MAX = + crate::Reg; +#[doc = "core0 dram0 region0 addr configuration register"] +pub mod core_0_area_dram0_0_max; +#[doc = "CORE_0_AREA_DRAM0_1_MIN (rw) register accessor: core0 dram0 region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_dram0_1_min::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_dram0_1_min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_dram0_1_min`] module"] +pub type CORE_0_AREA_DRAM0_1_MIN = + crate::Reg; +#[doc = "core0 dram0 region1 addr configuration register"] +pub mod core_0_area_dram0_1_min; +#[doc = "CORE_0_AREA_DRAM0_1_MAX (rw) register accessor: core0 dram0 region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_dram0_1_max::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_dram0_1_max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_dram0_1_max`] module"] +pub type CORE_0_AREA_DRAM0_1_MAX = + crate::Reg; +#[doc = "core0 dram0 region1 addr configuration register"] +pub mod core_0_area_dram0_1_max; +#[doc = "CORE_0_AREA_PIF_0_MIN (rw) register accessor: core0 PIF region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pif_0_min::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_pif_0_min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_pif_0_min`] module"] +pub type CORE_0_AREA_PIF_0_MIN = crate::Reg; +#[doc = "core0 PIF region0 addr configuration register"] +pub mod core_0_area_pif_0_min; +#[doc = "CORE_0_AREA_PIF_0_MAX (rw) register accessor: core0 PIF region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pif_0_max::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_pif_0_max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_pif_0_max`] module"] +pub type CORE_0_AREA_PIF_0_MAX = crate::Reg; +#[doc = "core0 PIF region0 addr configuration register"] +pub mod core_0_area_pif_0_max; +#[doc = "CORE_0_AREA_PIF_1_MIN (rw) register accessor: core0 PIF region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pif_1_min::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_pif_1_min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_pif_1_min`] module"] +pub type CORE_0_AREA_PIF_1_MIN = crate::Reg; +#[doc = "core0 PIF region1 addr configuration register"] +pub mod core_0_area_pif_1_min; +#[doc = "CORE_0_AREA_PIF_1_MAX (rw) register accessor: core0 PIF region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pif_1_max::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_pif_1_max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_pif_1_max`] module"] +pub type CORE_0_AREA_PIF_1_MAX = crate::Reg; +#[doc = "core0 PIF region1 addr configuration register"] +pub mod core_0_area_pif_1_max; +#[doc = "CORE_0_AREA_PC (r) register accessor: core0 area pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_pc`] module"] +pub type CORE_0_AREA_PC = crate::Reg; +#[doc = "core0 area pc status register"] +pub mod core_0_area_pc; +#[doc = "CORE_0_AREA_SP (r) register accessor: core0 area sp status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_sp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_sp`] module"] +pub type CORE_0_AREA_SP = crate::Reg; +#[doc = "core0 area sp status register"] +pub mod core_0_area_sp; +#[doc = "CORE_0_SP_MIN (rw) register accessor: stack min value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_min::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_sp_min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_sp_min`] module"] +pub type CORE_0_SP_MIN = crate::Reg; +#[doc = "stack min value"] +pub mod core_0_sp_min; +#[doc = "CORE_0_SP_MAX (rw) register accessor: stack max value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_max::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_sp_max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_sp_max`] module"] +pub type CORE_0_SP_MAX = crate::Reg; +#[doc = "stack max value"] +pub mod core_0_sp_max; +#[doc = "CORE_0_SP_PC (r) register accessor: stack monitor pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_sp_pc`] module"] +pub type CORE_0_SP_PC = crate::Reg; +#[doc = "stack monitor pc status register"] +pub mod core_0_sp_pc; +#[doc = "CORE_0_RCD_EN (rw) register accessor: record enable configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_rcd_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_en`] module"] +pub type CORE_0_RCD_EN = crate::Reg; +#[doc = "record enable configuration register"] +pub mod core_0_rcd_en; +#[doc = "CORE_0_RCD_PDEBUGPC (r) register accessor: record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugpc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_pdebugpc`] module"] +pub type CORE_0_RCD_PDEBUGPC = crate::Reg; +#[doc = "record status regsiter"] +pub mod core_0_rcd_pdebugpc; +#[doc = "CORE_0_RCD_PDEBUGSP (r) register accessor: record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugsp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_pdebugsp`] module"] +pub type CORE_0_RCD_PDEBUGSP = crate::Reg; +#[doc = "record status regsiter"] +pub mod core_0_rcd_pdebugsp; +#[doc = "CORE_0_IRAM0_EXCEPTION_MONITOR_0 (r) register accessor: exception monitor status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_iram0_exception_monitor_0`] module"] +pub type CORE_0_IRAM0_EXCEPTION_MONITOR_0 = + crate::Reg; +#[doc = "exception monitor status register0"] +pub mod core_0_iram0_exception_monitor_0; +#[doc = "CORE_0_IRAM0_EXCEPTION_MONITOR_1 (r) register accessor: exception monitor status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_iram0_exception_monitor_1`] module"] +pub type CORE_0_IRAM0_EXCEPTION_MONITOR_1 = + crate::Reg; +#[doc = "exception monitor status register1"] +pub mod core_0_iram0_exception_monitor_1; +#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_0 (r) register accessor: exception monitor status register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_0`] module"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_0 = + crate::Reg; +#[doc = "exception monitor status register2"] +pub mod core_0_dram0_exception_monitor_0; +#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_1 (r) register accessor: exception monitor status register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_1`] module"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_1 = + crate::Reg; +#[doc = "exception monitor status register3"] +pub mod core_0_dram0_exception_monitor_1; +#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_2 (r) register accessor: exception monitor status register4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_2`] module"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_2 = + crate::Reg; +#[doc = "exception monitor status register4"] +pub mod core_0_dram0_exception_monitor_2; +#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_3 (r) register accessor: exception monitor status register5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_3`] module"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_3 = + crate::Reg; +#[doc = "exception monitor status register5"] +pub mod core_0_dram0_exception_monitor_3; +#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_4 (r) register accessor: exception monitor status register6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_4`] module"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_4 = + crate::Reg; +#[doc = "exception monitor status register6"] +pub mod core_0_dram0_exception_monitor_4; +#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_5 (r) register accessor: exception monitor status register7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_5`] module"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_5 = + crate::Reg; +#[doc = "exception monitor status register7"] +pub mod core_0_dram0_exception_monitor_5; +#[doc = "CORE_0_LASTPC_BEFORE_EXCEPTION (r) register accessor: cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_lastpc_before_exception::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_lastpc_before_exception`] module"] +pub type CORE_0_LASTPC_BEFORE_EXCEPTION = + crate::Reg; +#[doc = "cpu status register"] +pub mod core_0_lastpc_before_exception; +#[doc = "CORE_0_DEBUG_MODE (r) register accessor: cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_debug_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_debug_mode`] module"] +pub type CORE_0_DEBUG_MODE = crate::Reg; +#[doc = "cpu status register"] +pub mod core_0_debug_mode; +#[doc = "CORE_1_INTR_ENA (rw) register accessor: core1 monitor enable configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_intr_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_intr_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_intr_ena`] module"] +pub type CORE_1_INTR_ENA = crate::Reg; +#[doc = "core1 monitor enable configuration register"] +pub mod core_1_intr_ena; +#[doc = "CORE_1_INTR_RAW (r) register accessor: core1 monitor interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_intr_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_intr_raw`] module"] +pub type CORE_1_INTR_RAW = crate::Reg; +#[doc = "core1 monitor interrupt status register"] +pub mod core_1_intr_raw; +#[doc = "CORE_1_INTR_RLS (rw) register accessor: core1 monitor interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_intr_rls::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_intr_rls::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_intr_rls`] module"] +pub type CORE_1_INTR_RLS = crate::Reg; +#[doc = "core1 monitor interrupt enable register"] +pub mod core_1_intr_rls; +#[doc = "CORE_1_INTR_CLR (w) register accessor: core1 monitor interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_intr_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_intr_clr`] module"] +pub type CORE_1_INTR_CLR = crate::Reg; +#[doc = "core1 monitor interrupt clr register"] +pub mod core_1_intr_clr; +#[doc = "CORE_1_AREA_DRAM0_0_MIN (rw) register accessor: core1 dram0 region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_dram0_0_min::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_dram0_0_min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_dram0_0_min`] module"] +pub type CORE_1_AREA_DRAM0_0_MIN = + crate::Reg; +#[doc = "core1 dram0 region0 addr configuration register"] +pub mod core_1_area_dram0_0_min; +#[doc = "CORE_1_AREA_DRAM0_0_MAX (rw) register accessor: core1 dram0 region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_dram0_0_max::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_dram0_0_max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_dram0_0_max`] module"] +pub type CORE_1_AREA_DRAM0_0_MAX = + crate::Reg; +#[doc = "core1 dram0 region0 addr configuration register"] +pub mod core_1_area_dram0_0_max; +#[doc = "CORE_1_AREA_DRAM0_1_MIN (rw) register accessor: core1 dram0 region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_dram0_1_min::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_dram0_1_min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_dram0_1_min`] module"] +pub type CORE_1_AREA_DRAM0_1_MIN = + crate::Reg; +#[doc = "core1 dram0 region1 addr configuration register"] +pub mod core_1_area_dram0_1_min; +#[doc = "CORE_1_AREA_DRAM0_1_MAX (rw) register accessor: core1 dram0 region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_dram0_1_max::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_dram0_1_max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_dram0_1_max`] module"] +pub type CORE_1_AREA_DRAM0_1_MAX = + crate::Reg; +#[doc = "core1 dram0 region1 addr configuration register"] +pub mod core_1_area_dram0_1_max; +#[doc = "CORE_1_AREA_PIF_0_MIN (rw) register accessor: core1 PIF region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pif_0_min::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_pif_0_min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_pif_0_min`] module"] +pub type CORE_1_AREA_PIF_0_MIN = crate::Reg; +#[doc = "core1 PIF region0 addr configuration register"] +pub mod core_1_area_pif_0_min; +#[doc = "CORE_1_AREA_PIF_0_MAX (rw) register accessor: core1 PIF region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pif_0_max::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_pif_0_max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_pif_0_max`] module"] +pub type CORE_1_AREA_PIF_0_MAX = crate::Reg; +#[doc = "core1 PIF region0 addr configuration register"] +pub mod core_1_area_pif_0_max; +#[doc = "CORE_1_AREA_PIF_1_MIN (rw) register accessor: core1 PIF region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pif_1_min::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_pif_1_min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_pif_1_min`] module"] +pub type CORE_1_AREA_PIF_1_MIN = crate::Reg; +#[doc = "core1 PIF region1 addr configuration register"] +pub mod core_1_area_pif_1_min; +#[doc = "CORE_1_AREA_PIF_1_MAX (rw) register accessor: core1 PIF region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pif_1_max::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_pif_1_max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_pif_1_max`] module"] +pub type CORE_1_AREA_PIF_1_MAX = crate::Reg; +#[doc = "core1 PIF region1 addr configuration register"] +pub mod core_1_area_pif_1_max; +#[doc = "CORE_1_AREA_PC (r) register accessor: core1 area pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_pc`] module"] +pub type CORE_1_AREA_PC = crate::Reg; +#[doc = "core1 area pc status register"] +pub mod core_1_area_pc; +#[doc = "CORE_1_AREA_SP (r) register accessor: core1 area sp status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_sp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_sp`] module"] +pub type CORE_1_AREA_SP = crate::Reg; +#[doc = "core1 area sp status register"] +pub mod core_1_area_sp; +#[doc = "CORE_1_SP_MIN (rw) register accessor: stack min value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_sp_min::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_sp_min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_sp_min`] module"] +pub type CORE_1_SP_MIN = crate::Reg; +#[doc = "stack min value"] +pub mod core_1_sp_min; +#[doc = "CORE_1_SP_MAX (rw) register accessor: stack max value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_sp_max::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_sp_max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_sp_max`] module"] +pub type CORE_1_SP_MAX = crate::Reg; +#[doc = "stack max value"] +pub mod core_1_sp_max; +#[doc = "CORE_1_SP_PC (r) register accessor: stack monitor pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_sp_pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_sp_pc`] module"] +pub type CORE_1_SP_PC = crate::Reg; +#[doc = "stack monitor pc status register"] +pub mod core_1_sp_pc; +#[doc = "CORE_1_RCD_EN (rw) register accessor: record enable configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_rcd_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_en`] module"] +pub type CORE_1_RCD_EN = crate::Reg; +#[doc = "record enable configuration register"] +pub mod core_1_rcd_en; +#[doc = "CORE_1_RCD_PDEBUGPC (r) register accessor: record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugpc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_pdebugpc`] module"] +pub type CORE_1_RCD_PDEBUGPC = crate::Reg; +#[doc = "record status regsiter"] +pub mod core_1_rcd_pdebugpc; +#[doc = "CORE_1_RCD_PDEBUGSP (r) register accessor: record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugsp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_pdebugsp`] module"] +pub type CORE_1_RCD_PDEBUGSP = crate::Reg; +#[doc = "record status regsiter"] +pub mod core_1_rcd_pdebugsp; +#[doc = "CORE_1_IRAM0_EXCEPTION_MONITOR_0 (r) register accessor: exception monitor status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_iram0_exception_monitor_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_iram0_exception_monitor_0`] module"] +pub type CORE_1_IRAM0_EXCEPTION_MONITOR_0 = + crate::Reg; +#[doc = "exception monitor status register0"] +pub mod core_1_iram0_exception_monitor_0; +#[doc = "CORE_1_IRAM0_EXCEPTION_MONITOR_1 (r) register accessor: exception monitor status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_iram0_exception_monitor_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_iram0_exception_monitor_1`] module"] +pub type CORE_1_IRAM0_EXCEPTION_MONITOR_1 = + crate::Reg; +#[doc = "exception monitor status register1"] +pub mod core_1_iram0_exception_monitor_1; +#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_0 (r) register accessor: exception monitor status register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_0`] module"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_0 = + crate::Reg; +#[doc = "exception monitor status register2"] +pub mod core_1_dram0_exception_monitor_0; +#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_1 (r) register accessor: exception monitor status register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_1`] module"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_1 = + crate::Reg; +#[doc = "exception monitor status register3"] +pub mod core_1_dram0_exception_monitor_1; +#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_2 (r) register accessor: exception monitor status register4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_2`] module"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_2 = + crate::Reg; +#[doc = "exception monitor status register4"] +pub mod core_1_dram0_exception_monitor_2; +#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_3 (r) register accessor: exception monitor status register5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_3`] module"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_3 = + crate::Reg; +#[doc = "exception monitor status register5"] +pub mod core_1_dram0_exception_monitor_3; +#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_4 (r) register accessor: exception monitor status register6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_4`] module"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_4 = + crate::Reg; +#[doc = "exception monitor status register6"] +pub mod core_1_dram0_exception_monitor_4; +#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_5 (r) register accessor: exception monitor status register7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_5`] module"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_5 = + crate::Reg; +#[doc = "exception monitor status register7"] +pub mod core_1_dram0_exception_monitor_5; +#[doc = "CORE_1_LASTPC_BEFORE_EXCEPTION (r) register accessor: cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_lastpc_before_exception::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_lastpc_before_exception`] module"] +pub type CORE_1_LASTPC_BEFORE_EXCEPTION = + crate::Reg; +#[doc = "cpu status register"] +pub mod core_1_lastpc_before_exception; +#[doc = "CORE_1_DEBUG_MODE (r) register accessor: cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_debug_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_debug_mode`] module"] +pub type CORE_1_DEBUG_MODE = crate::Reg; +#[doc = "cpu status register"] +pub mod core_1_debug_mode; +#[doc = "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 (rw) register accessor: exception monitor status register6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_x_iram0_dram0_exception_monitor_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_x_iram0_dram0_exception_monitor_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_x_iram0_dram0_exception_monitor_0`] module"] +pub type CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 = + crate::Reg; +#[doc = "exception monitor status register6"] +pub mod core_x_iram0_dram0_exception_monitor_0; +#[doc = "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 (rw) register accessor: exception monitor status register7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_x_iram0_dram0_exception_monitor_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_x_iram0_dram0_exception_monitor_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_x_iram0_dram0_exception_monitor_1`] module"] +pub type CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 = + crate::Reg; +#[doc = "exception monitor status register7"] +pub mod core_x_iram0_dram0_exception_monitor_1; +#[doc = "CLOCK_GATE (rw) register accessor: clock register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"] +pub type CLOCK_GATE = crate::Reg; +#[doc = "clock register"] +pub mod clock_gate; +#[doc = "DATE (rw) register accessor: version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "version register"] +pub mod date; diff --git a/esp32p4/src/assist_debug/clock_gate.rs b/esp32p4/src/assist_debug/clock_gate.rs new file mode 100644 index 0000000000..519dbebe1b --- /dev/null +++ b/esp32p4/src/assist_debug/clock_gate.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLOCK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `CLOCK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - Set 1 force on the clock gate"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Set 1 force on the clock gate"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 force on the clock gate"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCK_GATE") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 force on the clock gate"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "clock register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLOCK_GATE_SPEC; +impl crate::RegisterSpec for CLOCK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"] +impl crate::Readable for CLOCK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"] +impl crate::Writable for CLOCK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"] +impl crate::Resettable for CLOCK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/assist_debug/core_0_area_dram0_0_max.rs b/esp32p4/src/assist_debug/core_0_area_dram0_0_max.rs new file mode 100644 index 0000000000..ef9c555b4a --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_area_dram0_0_max.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE_0_AREA_DRAM0_0_MAX` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_AREA_DRAM0_0_MAX` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_AREA_DRAM0_0_MAX` reader - Core0 dram0 region0 end addr"] +pub type CORE_0_AREA_DRAM0_0_MAX_R = crate::FieldReader; +#[doc = "Field `CORE_0_AREA_DRAM0_0_MAX` writer - Core0 dram0 region0 end addr"] +pub type CORE_0_AREA_DRAM0_0_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core0 dram0 region0 end addr"] + #[inline(always)] + pub fn core_0_area_dram0_0_max(&self) -> CORE_0_AREA_DRAM0_0_MAX_R { + CORE_0_AREA_DRAM0_0_MAX_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_AREA_DRAM0_0_MAX") + .field( + "core_0_area_dram0_0_max", + &format_args!("{}", self.core_0_area_dram0_0_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core0 dram0 region0 end addr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_0_max( + &mut self, + ) -> CORE_0_AREA_DRAM0_0_MAX_W { + CORE_0_AREA_DRAM0_0_MAX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core0 dram0 region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_dram0_0_max::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_dram0_0_max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_AREA_DRAM0_0_MAX_SPEC; +impl crate::RegisterSpec for CORE_0_AREA_DRAM0_0_MAX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_area_dram0_0_max::R`](R) reader structure"] +impl crate::Readable for CORE_0_AREA_DRAM0_0_MAX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_area_dram0_0_max::W`](W) writer structure"] +impl crate::Writable for CORE_0_AREA_DRAM0_0_MAX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_AREA_DRAM0_0_MAX to value 0"] +impl crate::Resettable for CORE_0_AREA_DRAM0_0_MAX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_area_dram0_0_min.rs b/esp32p4/src/assist_debug/core_0_area_dram0_0_min.rs new file mode 100644 index 0000000000..7e3bdd9932 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_area_dram0_0_min.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE_0_AREA_DRAM0_0_MIN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_AREA_DRAM0_0_MIN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_AREA_DRAM0_0_MIN` reader - Core0 dram0 region0 start addr"] +pub type CORE_0_AREA_DRAM0_0_MIN_R = crate::FieldReader; +#[doc = "Field `CORE_0_AREA_DRAM0_0_MIN` writer - Core0 dram0 region0 start addr"] +pub type CORE_0_AREA_DRAM0_0_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core0 dram0 region0 start addr"] + #[inline(always)] + pub fn core_0_area_dram0_0_min(&self) -> CORE_0_AREA_DRAM0_0_MIN_R { + CORE_0_AREA_DRAM0_0_MIN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_AREA_DRAM0_0_MIN") + .field( + "core_0_area_dram0_0_min", + &format_args!("{}", self.core_0_area_dram0_0_min().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core0 dram0 region0 start addr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_0_min( + &mut self, + ) -> CORE_0_AREA_DRAM0_0_MIN_W { + CORE_0_AREA_DRAM0_0_MIN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core0 dram0 region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_dram0_0_min::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_dram0_0_min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_AREA_DRAM0_0_MIN_SPEC; +impl crate::RegisterSpec for CORE_0_AREA_DRAM0_0_MIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_area_dram0_0_min::R`](R) reader structure"] +impl crate::Readable for CORE_0_AREA_DRAM0_0_MIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_area_dram0_0_min::W`](W) writer structure"] +impl crate::Writable for CORE_0_AREA_DRAM0_0_MIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_AREA_DRAM0_0_MIN to value 0xffff_ffff"] +impl crate::Resettable for CORE_0_AREA_DRAM0_0_MIN_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/assist_debug/core_0_area_dram0_1_max.rs b/esp32p4/src/assist_debug/core_0_area_dram0_1_max.rs new file mode 100644 index 0000000000..fd7e8348a8 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_area_dram0_1_max.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE_0_AREA_DRAM0_1_MAX` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_AREA_DRAM0_1_MAX` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_AREA_DRAM0_1_MAX` reader - Core0 dram0 region1 end addr"] +pub type CORE_0_AREA_DRAM0_1_MAX_R = crate::FieldReader; +#[doc = "Field `CORE_0_AREA_DRAM0_1_MAX` writer - Core0 dram0 region1 end addr"] +pub type CORE_0_AREA_DRAM0_1_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core0 dram0 region1 end addr"] + #[inline(always)] + pub fn core_0_area_dram0_1_max(&self) -> CORE_0_AREA_DRAM0_1_MAX_R { + CORE_0_AREA_DRAM0_1_MAX_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_AREA_DRAM0_1_MAX") + .field( + "core_0_area_dram0_1_max", + &format_args!("{}", self.core_0_area_dram0_1_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core0 dram0 region1 end addr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_1_max( + &mut self, + ) -> CORE_0_AREA_DRAM0_1_MAX_W { + CORE_0_AREA_DRAM0_1_MAX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core0 dram0 region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_dram0_1_max::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_dram0_1_max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_AREA_DRAM0_1_MAX_SPEC; +impl crate::RegisterSpec for CORE_0_AREA_DRAM0_1_MAX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_area_dram0_1_max::R`](R) reader structure"] +impl crate::Readable for CORE_0_AREA_DRAM0_1_MAX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_area_dram0_1_max::W`](W) writer structure"] +impl crate::Writable for CORE_0_AREA_DRAM0_1_MAX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_AREA_DRAM0_1_MAX to value 0"] +impl crate::Resettable for CORE_0_AREA_DRAM0_1_MAX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_area_dram0_1_min.rs b/esp32p4/src/assist_debug/core_0_area_dram0_1_min.rs new file mode 100644 index 0000000000..5cd5663b5a --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_area_dram0_1_min.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE_0_AREA_DRAM0_1_MIN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_AREA_DRAM0_1_MIN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_AREA_DRAM0_1_MIN` reader - Core0 dram0 region1 start addr"] +pub type CORE_0_AREA_DRAM0_1_MIN_R = crate::FieldReader; +#[doc = "Field `CORE_0_AREA_DRAM0_1_MIN` writer - Core0 dram0 region1 start addr"] +pub type CORE_0_AREA_DRAM0_1_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core0 dram0 region1 start addr"] + #[inline(always)] + pub fn core_0_area_dram0_1_min(&self) -> CORE_0_AREA_DRAM0_1_MIN_R { + CORE_0_AREA_DRAM0_1_MIN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_AREA_DRAM0_1_MIN") + .field( + "core_0_area_dram0_1_min", + &format_args!("{}", self.core_0_area_dram0_1_min().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core0 dram0 region1 start addr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_1_min( + &mut self, + ) -> CORE_0_AREA_DRAM0_1_MIN_W { + CORE_0_AREA_DRAM0_1_MIN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core0 dram0 region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_dram0_1_min::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_dram0_1_min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_AREA_DRAM0_1_MIN_SPEC; +impl crate::RegisterSpec for CORE_0_AREA_DRAM0_1_MIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_area_dram0_1_min::R`](R) reader structure"] +impl crate::Readable for CORE_0_AREA_DRAM0_1_MIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_area_dram0_1_min::W`](W) writer structure"] +impl crate::Writable for CORE_0_AREA_DRAM0_1_MIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_AREA_DRAM0_1_MIN to value 0xffff_ffff"] +impl crate::Resettable for CORE_0_AREA_DRAM0_1_MIN_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/assist_debug/core_0_area_pc.rs b/esp32p4/src/assist_debug/core_0_area_pc.rs new file mode 100644 index 0000000000..5b8dc4d8bc --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_area_pc.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_0_AREA_PC` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_AREA_PC` reader - the stackpointer when first touch region monitor interrupt"] +pub type CORE_0_AREA_PC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - the stackpointer when first touch region monitor interrupt"] + #[inline(always)] + pub fn core_0_area_pc(&self) -> CORE_0_AREA_PC_R { + CORE_0_AREA_PC_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_AREA_PC") + .field( + "core_0_area_pc", + &format_args!("{}", self.core_0_area_pc().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "core0 area pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_AREA_PC_SPEC; +impl crate::RegisterSpec for CORE_0_AREA_PC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_area_pc::R`](R) reader structure"] +impl crate::Readable for CORE_0_AREA_PC_SPEC {} +#[doc = "`reset()` method sets CORE_0_AREA_PC to value 0"] +impl crate::Resettable for CORE_0_AREA_PC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_area_pif_0_max.rs b/esp32p4/src/assist_debug/core_0_area_pif_0_max.rs new file mode 100644 index 0000000000..de5d528150 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_area_pif_0_max.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_0_AREA_PIF_0_MAX` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_AREA_PIF_0_MAX` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_AREA_PIF_0_MAX` reader - Core0 PIF region0 end addr"] +pub type CORE_0_AREA_PIF_0_MAX_R = crate::FieldReader; +#[doc = "Field `CORE_0_AREA_PIF_0_MAX` writer - Core0 PIF region0 end addr"] +pub type CORE_0_AREA_PIF_0_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core0 PIF region0 end addr"] + #[inline(always)] + pub fn core_0_area_pif_0_max(&self) -> CORE_0_AREA_PIF_0_MAX_R { + CORE_0_AREA_PIF_0_MAX_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_AREA_PIF_0_MAX") + .field( + "core_0_area_pif_0_max", + &format_args!("{}", self.core_0_area_pif_0_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core0 PIF region0 end addr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_0_max(&mut self) -> CORE_0_AREA_PIF_0_MAX_W { + CORE_0_AREA_PIF_0_MAX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core0 PIF region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pif_0_max::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_pif_0_max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_AREA_PIF_0_MAX_SPEC; +impl crate::RegisterSpec for CORE_0_AREA_PIF_0_MAX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_area_pif_0_max::R`](R) reader structure"] +impl crate::Readable for CORE_0_AREA_PIF_0_MAX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_area_pif_0_max::W`](W) writer structure"] +impl crate::Writable for CORE_0_AREA_PIF_0_MAX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_AREA_PIF_0_MAX to value 0"] +impl crate::Resettable for CORE_0_AREA_PIF_0_MAX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_area_pif_0_min.rs b/esp32p4/src/assist_debug/core_0_area_pif_0_min.rs new file mode 100644 index 0000000000..f2b88da962 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_area_pif_0_min.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_0_AREA_PIF_0_MIN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_AREA_PIF_0_MIN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_AREA_PIF_0_MIN` reader - Core0 PIF region0 start addr"] +pub type CORE_0_AREA_PIF_0_MIN_R = crate::FieldReader; +#[doc = "Field `CORE_0_AREA_PIF_0_MIN` writer - Core0 PIF region0 start addr"] +pub type CORE_0_AREA_PIF_0_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core0 PIF region0 start addr"] + #[inline(always)] + pub fn core_0_area_pif_0_min(&self) -> CORE_0_AREA_PIF_0_MIN_R { + CORE_0_AREA_PIF_0_MIN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_AREA_PIF_0_MIN") + .field( + "core_0_area_pif_0_min", + &format_args!("{}", self.core_0_area_pif_0_min().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core0 PIF region0 start addr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_0_min(&mut self) -> CORE_0_AREA_PIF_0_MIN_W { + CORE_0_AREA_PIF_0_MIN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core0 PIF region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pif_0_min::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_pif_0_min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_AREA_PIF_0_MIN_SPEC; +impl crate::RegisterSpec for CORE_0_AREA_PIF_0_MIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_area_pif_0_min::R`](R) reader structure"] +impl crate::Readable for CORE_0_AREA_PIF_0_MIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_area_pif_0_min::W`](W) writer structure"] +impl crate::Writable for CORE_0_AREA_PIF_0_MIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_AREA_PIF_0_MIN to value 0xffff_ffff"] +impl crate::Resettable for CORE_0_AREA_PIF_0_MIN_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/assist_debug/core_0_area_pif_1_max.rs b/esp32p4/src/assist_debug/core_0_area_pif_1_max.rs new file mode 100644 index 0000000000..1ecc61dfd0 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_area_pif_1_max.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_0_AREA_PIF_1_MAX` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_AREA_PIF_1_MAX` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_AREA_PIF_1_MAX` reader - Core0 PIF region1 end addr"] +pub type CORE_0_AREA_PIF_1_MAX_R = crate::FieldReader; +#[doc = "Field `CORE_0_AREA_PIF_1_MAX` writer - Core0 PIF region1 end addr"] +pub type CORE_0_AREA_PIF_1_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core0 PIF region1 end addr"] + #[inline(always)] + pub fn core_0_area_pif_1_max(&self) -> CORE_0_AREA_PIF_1_MAX_R { + CORE_0_AREA_PIF_1_MAX_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_AREA_PIF_1_MAX") + .field( + "core_0_area_pif_1_max", + &format_args!("{}", self.core_0_area_pif_1_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core0 PIF region1 end addr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_1_max(&mut self) -> CORE_0_AREA_PIF_1_MAX_W { + CORE_0_AREA_PIF_1_MAX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core0 PIF region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pif_1_max::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_pif_1_max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_AREA_PIF_1_MAX_SPEC; +impl crate::RegisterSpec for CORE_0_AREA_PIF_1_MAX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_area_pif_1_max::R`](R) reader structure"] +impl crate::Readable for CORE_0_AREA_PIF_1_MAX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_area_pif_1_max::W`](W) writer structure"] +impl crate::Writable for CORE_0_AREA_PIF_1_MAX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_AREA_PIF_1_MAX to value 0"] +impl crate::Resettable for CORE_0_AREA_PIF_1_MAX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_area_pif_1_min.rs b/esp32p4/src/assist_debug/core_0_area_pif_1_min.rs new file mode 100644 index 0000000000..1e1b4ddc92 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_area_pif_1_min.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_0_AREA_PIF_1_MIN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_AREA_PIF_1_MIN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_AREA_PIF_1_MIN` reader - Core0 PIF region1 start addr"] +pub type CORE_0_AREA_PIF_1_MIN_R = crate::FieldReader; +#[doc = "Field `CORE_0_AREA_PIF_1_MIN` writer - Core0 PIF region1 start addr"] +pub type CORE_0_AREA_PIF_1_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core0 PIF region1 start addr"] + #[inline(always)] + pub fn core_0_area_pif_1_min(&self) -> CORE_0_AREA_PIF_1_MIN_R { + CORE_0_AREA_PIF_1_MIN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_AREA_PIF_1_MIN") + .field( + "core_0_area_pif_1_min", + &format_args!("{}", self.core_0_area_pif_1_min().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core0 PIF region1 start addr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_1_min(&mut self) -> CORE_0_AREA_PIF_1_MIN_W { + CORE_0_AREA_PIF_1_MIN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core0 PIF region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pif_1_min::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_area_pif_1_min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_AREA_PIF_1_MIN_SPEC; +impl crate::RegisterSpec for CORE_0_AREA_PIF_1_MIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_area_pif_1_min::R`](R) reader structure"] +impl crate::Readable for CORE_0_AREA_PIF_1_MIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_area_pif_1_min::W`](W) writer structure"] +impl crate::Writable for CORE_0_AREA_PIF_1_MIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_AREA_PIF_1_MIN to value 0xffff_ffff"] +impl crate::Resettable for CORE_0_AREA_PIF_1_MIN_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/assist_debug/core_0_area_sp.rs b/esp32p4/src/assist_debug/core_0_area_sp.rs new file mode 100644 index 0000000000..33ab88394b --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_area_sp.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_0_AREA_SP` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_AREA_SP` reader - the PC when first touch region monitor interrupt"] +pub type CORE_0_AREA_SP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - the PC when first touch region monitor interrupt"] + #[inline(always)] + pub fn core_0_area_sp(&self) -> CORE_0_AREA_SP_R { + CORE_0_AREA_SP_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_AREA_SP") + .field( + "core_0_area_sp", + &format_args!("{}", self.core_0_area_sp().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "core0 area sp status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_sp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_AREA_SP_SPEC; +impl crate::RegisterSpec for CORE_0_AREA_SP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_area_sp::R`](R) reader structure"] +impl crate::Readable for CORE_0_AREA_SP_SPEC {} +#[doc = "`reset()` method sets CORE_0_AREA_SP to value 0"] +impl crate::Resettable for CORE_0_AREA_SP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_debug_mode.rs b/esp32p4/src/assist_debug/core_0_debug_mode.rs new file mode 100644 index 0000000000..e2a16fea55 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_debug_mode.rs @@ -0,0 +1,50 @@ +#[doc = "Register `CORE_0_DEBUG_MODE` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_DEBUG_MODE` reader - cpu debug mode status, 1 means cpu enter debug mode."] +pub type CORE_0_DEBUG_MODE_R = crate::BitReader; +#[doc = "Field `CORE_0_DEBUG_MODULE_ACTIVE` reader - cpu debug_module active status"] +pub type CORE_0_DEBUG_MODULE_ACTIVE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - cpu debug mode status, 1 means cpu enter debug mode."] + #[inline(always)] + pub fn core_0_debug_mode(&self) -> CORE_0_DEBUG_MODE_R { + CORE_0_DEBUG_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - cpu debug_module active status"] + #[inline(always)] + pub fn core_0_debug_module_active(&self) -> CORE_0_DEBUG_MODULE_ACTIVE_R { + CORE_0_DEBUG_MODULE_ACTIVE_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_DEBUG_MODE") + .field( + "core_0_debug_mode", + &format_args!("{}", self.core_0_debug_mode().bit()), + ) + .field( + "core_0_debug_module_active", + &format_args!("{}", self.core_0_debug_module_active().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_debug_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_DEBUG_MODE_SPEC; +impl crate::RegisterSpec for CORE_0_DEBUG_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_debug_mode::R`](R) reader structure"] +impl crate::Readable for CORE_0_DEBUG_MODE_SPEC {} +#[doc = "`reset()` method sets CORE_0_DEBUG_MODE to value 0"] +impl crate::Resettable for CORE_0_DEBUG_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_0.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_0.rs new file mode 100644 index 0000000000..738efcffcf --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_0.rs @@ -0,0 +1,50 @@ +#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_0` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_DRAM0_RECORDING_WR_0` reader - reg_core_0_dram0_recording_wr_0"] +pub type CORE_0_DRAM0_RECORDING_WR_0_R = crate::BitReader; +#[doc = "Field `CORE_0_DRAM0_RECORDING_BYTEEN_0` reader - reg_core_0_dram0_recording_byteen_0"] +pub type CORE_0_DRAM0_RECORDING_BYTEEN_0_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - reg_core_0_dram0_recording_wr_0"] + #[inline(always)] + pub fn core_0_dram0_recording_wr_0(&self) -> CORE_0_DRAM0_RECORDING_WR_0_R { + CORE_0_DRAM0_RECORDING_WR_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - reg_core_0_dram0_recording_byteen_0"] + #[inline(always)] + pub fn core_0_dram0_recording_byteen_0(&self) -> CORE_0_DRAM0_RECORDING_BYTEEN_0_R { + CORE_0_DRAM0_RECORDING_BYTEEN_0_R::new(((self.bits >> 1) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_0") + .field( + "core_0_dram0_recording_wr_0", + &format_args!("{}", self.core_0_dram0_recording_wr_0().bit()), + ) + .field( + "core_0_dram0_recording_byteen_0", + &format_args!("{}", self.core_0_dram0_recording_byteen_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC; +impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_0::R`](R) reader structure"] +impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC {} +#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_0 to value 0"] +impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_1.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_1.rs new file mode 100644 index 0000000000..86d5d1613a --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_1` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_DRAM0_RECORDING_ADDR_0` reader - reg_core_0_dram0_recording_addr_0"] +pub type CORE_0_DRAM0_RECORDING_ADDR_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - reg_core_0_dram0_recording_addr_0"] + #[inline(always)] + pub fn core_0_dram0_recording_addr_0(&self) -> CORE_0_DRAM0_RECORDING_ADDR_0_R { + CORE_0_DRAM0_RECORDING_ADDR_0_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_1") + .field( + "core_0_dram0_recording_addr_0", + &format_args!("{}", self.core_0_dram0_recording_addr_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC; +impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_1::R`](R) reader structure"] +impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC {} +#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_1 to value 0"] +impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_2.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_2.rs new file mode 100644 index 0000000000..8a2766d325 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_2` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_DRAM0_RECORDING_PC_0` reader - reg_core_0_dram0_recording_pc_0"] +pub type CORE_0_DRAM0_RECORDING_PC_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - reg_core_0_dram0_recording_pc_0"] + #[inline(always)] + pub fn core_0_dram0_recording_pc_0(&self) -> CORE_0_DRAM0_RECORDING_PC_0_R { + CORE_0_DRAM0_RECORDING_PC_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_2") + .field( + "core_0_dram0_recording_pc_0", + &format_args!("{}", self.core_0_dram0_recording_pc_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC; +impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_2::R`](R) reader structure"] +impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC {} +#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_2 to value 0"] +impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_3.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_3.rs new file mode 100644 index 0000000000..2b4ffd807a --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_3.rs @@ -0,0 +1,50 @@ +#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_3` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_DRAM0_RECORDING_WR_1` reader - reg_core_0_dram0_recording_wr_1"] +pub type CORE_0_DRAM0_RECORDING_WR_1_R = crate::BitReader; +#[doc = "Field `CORE_0_DRAM0_RECORDING_BYTEEN_1` reader - reg_core_0_dram0_recording_byteen_1"] +pub type CORE_0_DRAM0_RECORDING_BYTEEN_1_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - reg_core_0_dram0_recording_wr_1"] + #[inline(always)] + pub fn core_0_dram0_recording_wr_1(&self) -> CORE_0_DRAM0_RECORDING_WR_1_R { + CORE_0_DRAM0_RECORDING_WR_1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - reg_core_0_dram0_recording_byteen_1"] + #[inline(always)] + pub fn core_0_dram0_recording_byteen_1(&self) -> CORE_0_DRAM0_RECORDING_BYTEEN_1_R { + CORE_0_DRAM0_RECORDING_BYTEEN_1_R::new(((self.bits >> 1) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_3") + .field( + "core_0_dram0_recording_wr_1", + &format_args!("{}", self.core_0_dram0_recording_wr_1().bit()), + ) + .field( + "core_0_dram0_recording_byteen_1", + &format_args!("{}", self.core_0_dram0_recording_byteen_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC; +impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_3::R`](R) reader structure"] +impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC {} +#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_3 to value 0"] +impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_4.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_4.rs new file mode 100644 index 0000000000..621dbfd65c --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_4` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_DRAM0_RECORDING_ADDR_1` reader - reg_core_0_dram0_recording_addr_1"] +pub type CORE_0_DRAM0_RECORDING_ADDR_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - reg_core_0_dram0_recording_addr_1"] + #[inline(always)] + pub fn core_0_dram0_recording_addr_1(&self) -> CORE_0_DRAM0_RECORDING_ADDR_1_R { + CORE_0_DRAM0_RECORDING_ADDR_1_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_4") + .field( + "core_0_dram0_recording_addr_1", + &format_args!("{}", self.core_0_dram0_recording_addr_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC; +impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_4::R`](R) reader structure"] +impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC {} +#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_4 to value 0"] +impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_5.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_5.rs new file mode 100644 index 0000000000..a1c63cf288 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_5` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_DRAM0_RECORDING_PC_1` reader - reg_core_0_dram0_recording_pc_1"] +pub type CORE_0_DRAM0_RECORDING_PC_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - reg_core_0_dram0_recording_pc_1"] + #[inline(always)] + pub fn core_0_dram0_recording_pc_1(&self) -> CORE_0_DRAM0_RECORDING_PC_1_R { + CORE_0_DRAM0_RECORDING_PC_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_5") + .field( + "core_0_dram0_recording_pc_1", + &format_args!("{}", self.core_0_dram0_recording_pc_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC; +impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_5::R`](R) reader structure"] +impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC {} +#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_5 to value 0"] +impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_intr_clr.rs b/esp32p4/src/assist_debug/core_0_intr_clr.rs new file mode 100644 index 0000000000..a3352d8324 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_intr_clr.rs @@ -0,0 +1,142 @@ +#[doc = "Register `CORE_0_INTR_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_CLR` writer - Core0 dram0 area0 read monitor interrupt clr"] +pub type CORE_0_AREA_DRAM0_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_CLR` writer - Core0 dram0 area0 write monitor interrupt clr"] +pub type CORE_0_AREA_DRAM0_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_CLR` writer - Core0 dram0 area1 read monitor interrupt clr"] +pub type CORE_0_AREA_DRAM0_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_CLR` writer - Core0 dram0 area1 write monitor interrupt clr"] +pub type CORE_0_AREA_DRAM0_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_0_RD_CLR` writer - Core0 PIF area0 read monitor interrupt clr"] +pub type CORE_0_AREA_PIF_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_0_WR_CLR` writer - Core0 PIF area0 write monitor interrupt clr"] +pub type CORE_0_AREA_PIF_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_1_RD_CLR` writer - Core0 PIF area1 read monitor interrupt clr"] +pub type CORE_0_AREA_PIF_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_1_WR_CLR` writer - Core0 PIF area1 write monitor interrupt clr"] +pub type CORE_0_AREA_PIF_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_SP_SPILL_MIN_CLR` writer - Core0 stackpoint underflow monitor interrupt clr"] +pub type CORE_0_SP_SPILL_MIN_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_SP_SPILL_MAX_CLR` writer - Core0 stackpoint overflow monitor interrupt clr"] +pub type CORE_0_SP_SPILL_MAX_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_CLR` writer - IBUS busy monitor interrupt clr"] +pub type CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_CLR` writer - DBUS busy monitor interrupt clr"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_0_rd_clr( + &mut self, + ) -> CORE_0_AREA_DRAM0_0_RD_CLR_W { + CORE_0_AREA_DRAM0_0_RD_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Core0 dram0 area0 write monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_0_wr_clr( + &mut self, + ) -> CORE_0_AREA_DRAM0_0_WR_CLR_W { + CORE_0_AREA_DRAM0_0_WR_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Core0 dram0 area1 read monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_1_rd_clr( + &mut self, + ) -> CORE_0_AREA_DRAM0_1_RD_CLR_W { + CORE_0_AREA_DRAM0_1_RD_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Core0 dram0 area1 write monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_1_wr_clr( + &mut self, + ) -> CORE_0_AREA_DRAM0_1_WR_CLR_W { + CORE_0_AREA_DRAM0_1_WR_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Core0 PIF area0 read monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_0_rd_clr(&mut self) -> CORE_0_AREA_PIF_0_RD_CLR_W { + CORE_0_AREA_PIF_0_RD_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Core0 PIF area0 write monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_0_wr_clr(&mut self) -> CORE_0_AREA_PIF_0_WR_CLR_W { + CORE_0_AREA_PIF_0_WR_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Core0 PIF area1 read monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_1_rd_clr(&mut self) -> CORE_0_AREA_PIF_1_RD_CLR_W { + CORE_0_AREA_PIF_1_RD_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Core0 PIF area1 write monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_1_wr_clr(&mut self) -> CORE_0_AREA_PIF_1_WR_CLR_W { + CORE_0_AREA_PIF_1_WR_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Core0 stackpoint underflow monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_sp_spill_min_clr(&mut self) -> CORE_0_SP_SPILL_MIN_CLR_W { + CORE_0_SP_SPILL_MIN_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Core0 stackpoint overflow monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_sp_spill_max_clr(&mut self) -> CORE_0_SP_SPILL_MAX_CLR_W { + CORE_0_SP_SPILL_MAX_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - IBUS busy monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_iram0_exception_monitor_clr( + &mut self, + ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W { + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - DBUS busy monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_0_dram0_exception_monitor_clr( + &mut self, + ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W { + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core0 monitor interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_intr_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_INTR_CLR_SPEC; +impl crate::RegisterSpec for CORE_0_INTR_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`core_0_intr_clr::W`](W) writer structure"] +impl crate::Writable for CORE_0_INTR_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_INTR_CLR to value 0"] +impl crate::Resettable for CORE_0_INTR_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_intr_ena.rs b/esp32p4/src/assist_debug/core_0_intr_ena.rs new file mode 100644 index 0000000000..8fc75124cd --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_intr_ena.rs @@ -0,0 +1,287 @@ +#[doc = "Register `CORE_0_INTR_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_INTR_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_ENA` reader - Core0 dram0 area0 read monitor enable"] +pub type CORE_0_AREA_DRAM0_0_RD_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_ENA` writer - Core0 dram0 area0 read monitor enable"] +pub type CORE_0_AREA_DRAM0_0_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_ENA` reader - Core0 dram0 area0 write monitor enable"] +pub type CORE_0_AREA_DRAM0_0_WR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_ENA` writer - Core0 dram0 area0 write monitor enable"] +pub type CORE_0_AREA_DRAM0_0_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_ENA` reader - Core0 dram0 area1 read monitor enable"] +pub type CORE_0_AREA_DRAM0_1_RD_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_ENA` writer - Core0 dram0 area1 read monitor enable"] +pub type CORE_0_AREA_DRAM0_1_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_ENA` reader - Core0 dram0 area1 write monitor enable"] +pub type CORE_0_AREA_DRAM0_1_WR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_ENA` writer - Core0 dram0 area1 write monitor enable"] +pub type CORE_0_AREA_DRAM0_1_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_0_RD_ENA` reader - Core0 PIF area0 read monitor enable"] +pub type CORE_0_AREA_PIF_0_RD_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_0_RD_ENA` writer - Core0 PIF area0 read monitor enable"] +pub type CORE_0_AREA_PIF_0_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_0_WR_ENA` reader - Core0 PIF area0 write monitor enable"] +pub type CORE_0_AREA_PIF_0_WR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_0_WR_ENA` writer - Core0 PIF area0 write monitor enable"] +pub type CORE_0_AREA_PIF_0_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_1_RD_ENA` reader - Core0 PIF area1 read monitor enable"] +pub type CORE_0_AREA_PIF_1_RD_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_1_RD_ENA` writer - Core0 PIF area1 read monitor enable"] +pub type CORE_0_AREA_PIF_1_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_1_WR_ENA` reader - Core0 PIF area1 write monitor enable"] +pub type CORE_0_AREA_PIF_1_WR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_1_WR_ENA` writer - Core0 PIF area1 write monitor enable"] +pub type CORE_0_AREA_PIF_1_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_SP_SPILL_MIN_ENA` reader - Core0 stackpoint underflow monitor enable"] +pub type CORE_0_SP_SPILL_MIN_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_SP_SPILL_MIN_ENA` writer - Core0 stackpoint underflow monitor enable"] +pub type CORE_0_SP_SPILL_MIN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_SP_SPILL_MAX_ENA` reader - Core0 stackpoint overflow monitor enable"] +pub type CORE_0_SP_SPILL_MAX_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_SP_SPILL_MAX_ENA` writer - Core0 stackpoint overflow monitor enable"] +pub type CORE_0_SP_SPILL_MAX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_ENA` reader - IBUS busy monitor enable"] +pub type CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_ENA` writer - IBUS busy monitor enable"] +pub type CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_ENA` reader - DBUS busy monitor enbale"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_ENA` writer - DBUS busy monitor enbale"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Core0 dram0 area0 read monitor enable"] + #[inline(always)] + pub fn core_0_area_dram0_0_rd_ena(&self) -> CORE_0_AREA_DRAM0_0_RD_ENA_R { + CORE_0_AREA_DRAM0_0_RD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Core0 dram0 area0 write monitor enable"] + #[inline(always)] + pub fn core_0_area_dram0_0_wr_ena(&self) -> CORE_0_AREA_DRAM0_0_WR_ENA_R { + CORE_0_AREA_DRAM0_0_WR_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Core0 dram0 area1 read monitor enable"] + #[inline(always)] + pub fn core_0_area_dram0_1_rd_ena(&self) -> CORE_0_AREA_DRAM0_1_RD_ENA_R { + CORE_0_AREA_DRAM0_1_RD_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Core0 dram0 area1 write monitor enable"] + #[inline(always)] + pub fn core_0_area_dram0_1_wr_ena(&self) -> CORE_0_AREA_DRAM0_1_WR_ENA_R { + CORE_0_AREA_DRAM0_1_WR_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Core0 PIF area0 read monitor enable"] + #[inline(always)] + pub fn core_0_area_pif_0_rd_ena(&self) -> CORE_0_AREA_PIF_0_RD_ENA_R { + CORE_0_AREA_PIF_0_RD_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Core0 PIF area0 write monitor enable"] + #[inline(always)] + pub fn core_0_area_pif_0_wr_ena(&self) -> CORE_0_AREA_PIF_0_WR_ENA_R { + CORE_0_AREA_PIF_0_WR_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Core0 PIF area1 read monitor enable"] + #[inline(always)] + pub fn core_0_area_pif_1_rd_ena(&self) -> CORE_0_AREA_PIF_1_RD_ENA_R { + CORE_0_AREA_PIF_1_RD_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Core0 PIF area1 write monitor enable"] + #[inline(always)] + pub fn core_0_area_pif_1_wr_ena(&self) -> CORE_0_AREA_PIF_1_WR_ENA_R { + CORE_0_AREA_PIF_1_WR_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Core0 stackpoint underflow monitor enable"] + #[inline(always)] + pub fn core_0_sp_spill_min_ena(&self) -> CORE_0_SP_SPILL_MIN_ENA_R { + CORE_0_SP_SPILL_MIN_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Core0 stackpoint overflow monitor enable"] + #[inline(always)] + pub fn core_0_sp_spill_max_ena(&self) -> CORE_0_SP_SPILL_MAX_ENA_R { + CORE_0_SP_SPILL_MAX_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - IBUS busy monitor enable"] + #[inline(always)] + pub fn core_0_iram0_exception_monitor_ena(&self) -> CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_R { + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DBUS busy monitor enbale"] + #[inline(always)] + pub fn core_0_dram0_exception_monitor_ena(&self) -> CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_R { + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_INTR_ENA") + .field( + "core_0_area_dram0_0_rd_ena", + &format_args!("{}", self.core_0_area_dram0_0_rd_ena().bit()), + ) + .field( + "core_0_area_dram0_0_wr_ena", + &format_args!("{}", self.core_0_area_dram0_0_wr_ena().bit()), + ) + .field( + "core_0_area_dram0_1_rd_ena", + &format_args!("{}", self.core_0_area_dram0_1_rd_ena().bit()), + ) + .field( + "core_0_area_dram0_1_wr_ena", + &format_args!("{}", self.core_0_area_dram0_1_wr_ena().bit()), + ) + .field( + "core_0_area_pif_0_rd_ena", + &format_args!("{}", self.core_0_area_pif_0_rd_ena().bit()), + ) + .field( + "core_0_area_pif_0_wr_ena", + &format_args!("{}", self.core_0_area_pif_0_wr_ena().bit()), + ) + .field( + "core_0_area_pif_1_rd_ena", + &format_args!("{}", self.core_0_area_pif_1_rd_ena().bit()), + ) + .field( + "core_0_area_pif_1_wr_ena", + &format_args!("{}", self.core_0_area_pif_1_wr_ena().bit()), + ) + .field( + "core_0_sp_spill_min_ena", + &format_args!("{}", self.core_0_sp_spill_min_ena().bit()), + ) + .field( + "core_0_sp_spill_max_ena", + &format_args!("{}", self.core_0_sp_spill_max_ena().bit()), + ) + .field( + "core_0_iram0_exception_monitor_ena", + &format_args!("{}", self.core_0_iram0_exception_monitor_ena().bit()), + ) + .field( + "core_0_dram0_exception_monitor_ena", + &format_args!("{}", self.core_0_dram0_exception_monitor_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Core0 dram0 area0 read monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_0_rd_ena( + &mut self, + ) -> CORE_0_AREA_DRAM0_0_RD_ENA_W { + CORE_0_AREA_DRAM0_0_RD_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Core0 dram0 area0 write monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_0_wr_ena( + &mut self, + ) -> CORE_0_AREA_DRAM0_0_WR_ENA_W { + CORE_0_AREA_DRAM0_0_WR_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Core0 dram0 area1 read monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_1_rd_ena( + &mut self, + ) -> CORE_0_AREA_DRAM0_1_RD_ENA_W { + CORE_0_AREA_DRAM0_1_RD_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Core0 dram0 area1 write monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_1_wr_ena( + &mut self, + ) -> CORE_0_AREA_DRAM0_1_WR_ENA_W { + CORE_0_AREA_DRAM0_1_WR_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Core0 PIF area0 read monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_0_rd_ena(&mut self) -> CORE_0_AREA_PIF_0_RD_ENA_W { + CORE_0_AREA_PIF_0_RD_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - Core0 PIF area0 write monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_0_wr_ena(&mut self) -> CORE_0_AREA_PIF_0_WR_ENA_W { + CORE_0_AREA_PIF_0_WR_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - Core0 PIF area1 read monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_1_rd_ena(&mut self) -> CORE_0_AREA_PIF_1_RD_ENA_W { + CORE_0_AREA_PIF_1_RD_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - Core0 PIF area1 write monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_1_wr_ena(&mut self) -> CORE_0_AREA_PIF_1_WR_ENA_W { + CORE_0_AREA_PIF_1_WR_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - Core0 stackpoint underflow monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_0_sp_spill_min_ena(&mut self) -> CORE_0_SP_SPILL_MIN_ENA_W { + CORE_0_SP_SPILL_MIN_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - Core0 stackpoint overflow monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_0_sp_spill_max_ena(&mut self) -> CORE_0_SP_SPILL_MAX_ENA_W { + CORE_0_SP_SPILL_MAX_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - IBUS busy monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_0_iram0_exception_monitor_ena( + &mut self, + ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W { + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - DBUS busy monitor enbale"] + #[inline(always)] + #[must_use] + pub fn core_0_dram0_exception_monitor_ena( + &mut self, + ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W { + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core0 monitor enable configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_intr_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_INTR_ENA_SPEC; +impl crate::RegisterSpec for CORE_0_INTR_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_intr_ena::R`](R) reader structure"] +impl crate::Readable for CORE_0_INTR_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_intr_ena::W`](W) writer structure"] +impl crate::Writable for CORE_0_INTR_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_INTR_ENA to value 0"] +impl crate::Resettable for CORE_0_INTR_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_intr_raw.rs b/esp32p4/src/assist_debug/core_0_intr_raw.rs new file mode 100644 index 0000000000..1c08590cf3 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_intr_raw.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CORE_0_INTR_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_RAW` reader - Core0 dram0 area0 read monitor interrupt status"] +pub type CORE_0_AREA_DRAM0_0_RD_RAW_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_RAW` reader - Core0 dram0 area0 write monitor interrupt status"] +pub type CORE_0_AREA_DRAM0_0_WR_RAW_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_RAW` reader - Core0 dram0 area1 read monitor interrupt status"] +pub type CORE_0_AREA_DRAM0_1_RD_RAW_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_RAW` reader - Core0 dram0 area1 write monitor interrupt status"] +pub type CORE_0_AREA_DRAM0_1_WR_RAW_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_0_RD_RAW` reader - Core0 PIF area0 read monitor interrupt status"] +pub type CORE_0_AREA_PIF_0_RD_RAW_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_0_WR_RAW` reader - Core0 PIF area0 write monitor interrupt status"] +pub type CORE_0_AREA_PIF_0_WR_RAW_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_1_RD_RAW` reader - Core0 PIF area1 read monitor interrupt status"] +pub type CORE_0_AREA_PIF_1_RD_RAW_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_1_WR_RAW` reader - Core0 PIF area1 write monitor interrupt status"] +pub type CORE_0_AREA_PIF_1_WR_RAW_R = crate::BitReader; +#[doc = "Field `CORE_0_SP_SPILL_MIN_RAW` reader - Core0 stackpoint underflow monitor interrupt status"] +pub type CORE_0_SP_SPILL_MIN_RAW_R = crate::BitReader; +#[doc = "Field `CORE_0_SP_SPILL_MAX_RAW` reader - Core0 stackpoint overflow monitor interrupt status"] +pub type CORE_0_SP_SPILL_MAX_RAW_R = crate::BitReader; +#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_RAW` reader - IBUS busy monitor interrupt status"] +pub type CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_R = crate::BitReader; +#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_RAW` reader - DBUS busy monitor initerrupt status"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt status"] + #[inline(always)] + pub fn core_0_area_dram0_0_rd_raw(&self) -> CORE_0_AREA_DRAM0_0_RD_RAW_R { + CORE_0_AREA_DRAM0_0_RD_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Core0 dram0 area0 write monitor interrupt status"] + #[inline(always)] + pub fn core_0_area_dram0_0_wr_raw(&self) -> CORE_0_AREA_DRAM0_0_WR_RAW_R { + CORE_0_AREA_DRAM0_0_WR_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Core0 dram0 area1 read monitor interrupt status"] + #[inline(always)] + pub fn core_0_area_dram0_1_rd_raw(&self) -> CORE_0_AREA_DRAM0_1_RD_RAW_R { + CORE_0_AREA_DRAM0_1_RD_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Core0 dram0 area1 write monitor interrupt status"] + #[inline(always)] + pub fn core_0_area_dram0_1_wr_raw(&self) -> CORE_0_AREA_DRAM0_1_WR_RAW_R { + CORE_0_AREA_DRAM0_1_WR_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Core0 PIF area0 read monitor interrupt status"] + #[inline(always)] + pub fn core_0_area_pif_0_rd_raw(&self) -> CORE_0_AREA_PIF_0_RD_RAW_R { + CORE_0_AREA_PIF_0_RD_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Core0 PIF area0 write monitor interrupt status"] + #[inline(always)] + pub fn core_0_area_pif_0_wr_raw(&self) -> CORE_0_AREA_PIF_0_WR_RAW_R { + CORE_0_AREA_PIF_0_WR_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Core0 PIF area1 read monitor interrupt status"] + #[inline(always)] + pub fn core_0_area_pif_1_rd_raw(&self) -> CORE_0_AREA_PIF_1_RD_RAW_R { + CORE_0_AREA_PIF_1_RD_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Core0 PIF area1 write monitor interrupt status"] + #[inline(always)] + pub fn core_0_area_pif_1_wr_raw(&self) -> CORE_0_AREA_PIF_1_WR_RAW_R { + CORE_0_AREA_PIF_1_WR_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Core0 stackpoint underflow monitor interrupt status"] + #[inline(always)] + pub fn core_0_sp_spill_min_raw(&self) -> CORE_0_SP_SPILL_MIN_RAW_R { + CORE_0_SP_SPILL_MIN_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Core0 stackpoint overflow monitor interrupt status"] + #[inline(always)] + pub fn core_0_sp_spill_max_raw(&self) -> CORE_0_SP_SPILL_MAX_RAW_R { + CORE_0_SP_SPILL_MAX_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - IBUS busy monitor interrupt status"] + #[inline(always)] + pub fn core_0_iram0_exception_monitor_raw(&self) -> CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_R { + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DBUS busy monitor initerrupt status"] + #[inline(always)] + pub fn core_0_dram0_exception_monitor_raw(&self) -> CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_R { + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_INTR_RAW") + .field( + "core_0_area_dram0_0_rd_raw", + &format_args!("{}", self.core_0_area_dram0_0_rd_raw().bit()), + ) + .field( + "core_0_area_dram0_0_wr_raw", + &format_args!("{}", self.core_0_area_dram0_0_wr_raw().bit()), + ) + .field( + "core_0_area_dram0_1_rd_raw", + &format_args!("{}", self.core_0_area_dram0_1_rd_raw().bit()), + ) + .field( + "core_0_area_dram0_1_wr_raw", + &format_args!("{}", self.core_0_area_dram0_1_wr_raw().bit()), + ) + .field( + "core_0_area_pif_0_rd_raw", + &format_args!("{}", self.core_0_area_pif_0_rd_raw().bit()), + ) + .field( + "core_0_area_pif_0_wr_raw", + &format_args!("{}", self.core_0_area_pif_0_wr_raw().bit()), + ) + .field( + "core_0_area_pif_1_rd_raw", + &format_args!("{}", self.core_0_area_pif_1_rd_raw().bit()), + ) + .field( + "core_0_area_pif_1_wr_raw", + &format_args!("{}", self.core_0_area_pif_1_wr_raw().bit()), + ) + .field( + "core_0_sp_spill_min_raw", + &format_args!("{}", self.core_0_sp_spill_min_raw().bit()), + ) + .field( + "core_0_sp_spill_max_raw", + &format_args!("{}", self.core_0_sp_spill_max_raw().bit()), + ) + .field( + "core_0_iram0_exception_monitor_raw", + &format_args!("{}", self.core_0_iram0_exception_monitor_raw().bit()), + ) + .field( + "core_0_dram0_exception_monitor_raw", + &format_args!("{}", self.core_0_dram0_exception_monitor_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "core0 monitor interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_INTR_RAW_SPEC; +impl crate::RegisterSpec for CORE_0_INTR_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_intr_raw::R`](R) reader structure"] +impl crate::Readable for CORE_0_INTR_RAW_SPEC {} +#[doc = "`reset()` method sets CORE_0_INTR_RAW to value 0"] +impl crate::Resettable for CORE_0_INTR_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_intr_rls.rs b/esp32p4/src/assist_debug/core_0_intr_rls.rs new file mode 100644 index 0000000000..170e41087b --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_intr_rls.rs @@ -0,0 +1,287 @@ +#[doc = "Register `CORE_0_INTR_RLS` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_INTR_RLS` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_RLS` reader - Core0 dram0 area0 read monitor interrupt enable"] +pub type CORE_0_AREA_DRAM0_0_RD_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_RLS` writer - Core0 dram0 area0 read monitor interrupt enable"] +pub type CORE_0_AREA_DRAM0_0_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_RLS` reader - Core0 dram0 area0 write monitor interrupt enable"] +pub type CORE_0_AREA_DRAM0_0_WR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_RLS` writer - Core0 dram0 area0 write monitor interrupt enable"] +pub type CORE_0_AREA_DRAM0_0_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_RLS` reader - Core0 dram0 area1 read monitor interrupt enable"] +pub type CORE_0_AREA_DRAM0_1_RD_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_RLS` writer - Core0 dram0 area1 read monitor interrupt enable"] +pub type CORE_0_AREA_DRAM0_1_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_RLS` reader - Core0 dram0 area1 write monitor interrupt enable"] +pub type CORE_0_AREA_DRAM0_1_WR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_RLS` writer - Core0 dram0 area1 write monitor interrupt enable"] +pub type CORE_0_AREA_DRAM0_1_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_0_RD_RLS` reader - Core0 PIF area0 read monitor interrupt enable"] +pub type CORE_0_AREA_PIF_0_RD_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_0_RD_RLS` writer - Core0 PIF area0 read monitor interrupt enable"] +pub type CORE_0_AREA_PIF_0_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_0_WR_RLS` reader - Core0 PIF area0 write monitor interrupt enable"] +pub type CORE_0_AREA_PIF_0_WR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_0_WR_RLS` writer - Core0 PIF area0 write monitor interrupt enable"] +pub type CORE_0_AREA_PIF_0_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_1_RD_RLS` reader - Core0 PIF area1 read monitor interrupt enable"] +pub type CORE_0_AREA_PIF_1_RD_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_1_RD_RLS` writer - Core0 PIF area1 read monitor interrupt enable"] +pub type CORE_0_AREA_PIF_1_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_AREA_PIF_1_WR_RLS` reader - Core0 PIF area1 write monitor interrupt enable"] +pub type CORE_0_AREA_PIF_1_WR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_AREA_PIF_1_WR_RLS` writer - Core0 PIF area1 write monitor interrupt enable"] +pub type CORE_0_AREA_PIF_1_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_SP_SPILL_MIN_RLS` reader - Core0 stackpoint underflow monitor interrupt enable"] +pub type CORE_0_SP_SPILL_MIN_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_SP_SPILL_MIN_RLS` writer - Core0 stackpoint underflow monitor interrupt enable"] +pub type CORE_0_SP_SPILL_MIN_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_SP_SPILL_MAX_RLS` reader - Core0 stackpoint overflow monitor interrupt enable"] +pub type CORE_0_SP_SPILL_MAX_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_SP_SPILL_MAX_RLS` writer - Core0 stackpoint overflow monitor interrupt enable"] +pub type CORE_0_SP_SPILL_MAX_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_RLS` reader - IBUS busy monitor interrupt enable"] +pub type CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_RLS` writer - IBUS busy monitor interrupt enable"] +pub type CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_RLS` reader - DBUS busy monitor interrupt enbale"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_RLS` writer - DBUS busy monitor interrupt enbale"] +pub type CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt enable"] + #[inline(always)] + pub fn core_0_area_dram0_0_rd_rls(&self) -> CORE_0_AREA_DRAM0_0_RD_RLS_R { + CORE_0_AREA_DRAM0_0_RD_RLS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Core0 dram0 area0 write monitor interrupt enable"] + #[inline(always)] + pub fn core_0_area_dram0_0_wr_rls(&self) -> CORE_0_AREA_DRAM0_0_WR_RLS_R { + CORE_0_AREA_DRAM0_0_WR_RLS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Core0 dram0 area1 read monitor interrupt enable"] + #[inline(always)] + pub fn core_0_area_dram0_1_rd_rls(&self) -> CORE_0_AREA_DRAM0_1_RD_RLS_R { + CORE_0_AREA_DRAM0_1_RD_RLS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Core0 dram0 area1 write monitor interrupt enable"] + #[inline(always)] + pub fn core_0_area_dram0_1_wr_rls(&self) -> CORE_0_AREA_DRAM0_1_WR_RLS_R { + CORE_0_AREA_DRAM0_1_WR_RLS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Core0 PIF area0 read monitor interrupt enable"] + #[inline(always)] + pub fn core_0_area_pif_0_rd_rls(&self) -> CORE_0_AREA_PIF_0_RD_RLS_R { + CORE_0_AREA_PIF_0_RD_RLS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Core0 PIF area0 write monitor interrupt enable"] + #[inline(always)] + pub fn core_0_area_pif_0_wr_rls(&self) -> CORE_0_AREA_PIF_0_WR_RLS_R { + CORE_0_AREA_PIF_0_WR_RLS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Core0 PIF area1 read monitor interrupt enable"] + #[inline(always)] + pub fn core_0_area_pif_1_rd_rls(&self) -> CORE_0_AREA_PIF_1_RD_RLS_R { + CORE_0_AREA_PIF_1_RD_RLS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Core0 PIF area1 write monitor interrupt enable"] + #[inline(always)] + pub fn core_0_area_pif_1_wr_rls(&self) -> CORE_0_AREA_PIF_1_WR_RLS_R { + CORE_0_AREA_PIF_1_WR_RLS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Core0 stackpoint underflow monitor interrupt enable"] + #[inline(always)] + pub fn core_0_sp_spill_min_rls(&self) -> CORE_0_SP_SPILL_MIN_RLS_R { + CORE_0_SP_SPILL_MIN_RLS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Core0 stackpoint overflow monitor interrupt enable"] + #[inline(always)] + pub fn core_0_sp_spill_max_rls(&self) -> CORE_0_SP_SPILL_MAX_RLS_R { + CORE_0_SP_SPILL_MAX_RLS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - IBUS busy monitor interrupt enable"] + #[inline(always)] + pub fn core_0_iram0_exception_monitor_rls(&self) -> CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_R { + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"] + #[inline(always)] + pub fn core_0_dram0_exception_monitor_rls(&self) -> CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_R { + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_INTR_RLS") + .field( + "core_0_area_dram0_0_rd_rls", + &format_args!("{}", self.core_0_area_dram0_0_rd_rls().bit()), + ) + .field( + "core_0_area_dram0_0_wr_rls", + &format_args!("{}", self.core_0_area_dram0_0_wr_rls().bit()), + ) + .field( + "core_0_area_dram0_1_rd_rls", + &format_args!("{}", self.core_0_area_dram0_1_rd_rls().bit()), + ) + .field( + "core_0_area_dram0_1_wr_rls", + &format_args!("{}", self.core_0_area_dram0_1_wr_rls().bit()), + ) + .field( + "core_0_area_pif_0_rd_rls", + &format_args!("{}", self.core_0_area_pif_0_rd_rls().bit()), + ) + .field( + "core_0_area_pif_0_wr_rls", + &format_args!("{}", self.core_0_area_pif_0_wr_rls().bit()), + ) + .field( + "core_0_area_pif_1_rd_rls", + &format_args!("{}", self.core_0_area_pif_1_rd_rls().bit()), + ) + .field( + "core_0_area_pif_1_wr_rls", + &format_args!("{}", self.core_0_area_pif_1_wr_rls().bit()), + ) + .field( + "core_0_sp_spill_min_rls", + &format_args!("{}", self.core_0_sp_spill_min_rls().bit()), + ) + .field( + "core_0_sp_spill_max_rls", + &format_args!("{}", self.core_0_sp_spill_max_rls().bit()), + ) + .field( + "core_0_iram0_exception_monitor_rls", + &format_args!("{}", self.core_0_iram0_exception_monitor_rls().bit()), + ) + .field( + "core_0_dram0_exception_monitor_rls", + &format_args!("{}", self.core_0_dram0_exception_monitor_rls().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_0_rd_rls( + &mut self, + ) -> CORE_0_AREA_DRAM0_0_RD_RLS_W { + CORE_0_AREA_DRAM0_0_RD_RLS_W::new(self, 0) + } + #[doc = "Bit 1 - Core0 dram0 area0 write monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_0_wr_rls( + &mut self, + ) -> CORE_0_AREA_DRAM0_0_WR_RLS_W { + CORE_0_AREA_DRAM0_0_WR_RLS_W::new(self, 1) + } + #[doc = "Bit 2 - Core0 dram0 area1 read monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_1_rd_rls( + &mut self, + ) -> CORE_0_AREA_DRAM0_1_RD_RLS_W { + CORE_0_AREA_DRAM0_1_RD_RLS_W::new(self, 2) + } + #[doc = "Bit 3 - Core0 dram0 area1 write monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_dram0_1_wr_rls( + &mut self, + ) -> CORE_0_AREA_DRAM0_1_WR_RLS_W { + CORE_0_AREA_DRAM0_1_WR_RLS_W::new(self, 3) + } + #[doc = "Bit 4 - Core0 PIF area0 read monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_0_rd_rls(&mut self) -> CORE_0_AREA_PIF_0_RD_RLS_W { + CORE_0_AREA_PIF_0_RD_RLS_W::new(self, 4) + } + #[doc = "Bit 5 - Core0 PIF area0 write monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_0_wr_rls(&mut self) -> CORE_0_AREA_PIF_0_WR_RLS_W { + CORE_0_AREA_PIF_0_WR_RLS_W::new(self, 5) + } + #[doc = "Bit 6 - Core0 PIF area1 read monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_1_rd_rls(&mut self) -> CORE_0_AREA_PIF_1_RD_RLS_W { + CORE_0_AREA_PIF_1_RD_RLS_W::new(self, 6) + } + #[doc = "Bit 7 - Core0 PIF area1 write monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_0_area_pif_1_wr_rls(&mut self) -> CORE_0_AREA_PIF_1_WR_RLS_W { + CORE_0_AREA_PIF_1_WR_RLS_W::new(self, 7) + } + #[doc = "Bit 8 - Core0 stackpoint underflow monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_0_sp_spill_min_rls(&mut self) -> CORE_0_SP_SPILL_MIN_RLS_W { + CORE_0_SP_SPILL_MIN_RLS_W::new(self, 8) + } + #[doc = "Bit 9 - Core0 stackpoint overflow monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_0_sp_spill_max_rls(&mut self) -> CORE_0_SP_SPILL_MAX_RLS_W { + CORE_0_SP_SPILL_MAX_RLS_W::new(self, 9) + } + #[doc = "Bit 10 - IBUS busy monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_0_iram0_exception_monitor_rls( + &mut self, + ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_W { + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_W::new(self, 10) + } + #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"] + #[inline(always)] + #[must_use] + pub fn core_0_dram0_exception_monitor_rls( + &mut self, + ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_W { + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core0 monitor interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_rls::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_intr_rls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_INTR_RLS_SPEC; +impl crate::RegisterSpec for CORE_0_INTR_RLS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_intr_rls::R`](R) reader structure"] +impl crate::Readable for CORE_0_INTR_RLS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_intr_rls::W`](W) writer structure"] +impl crate::Writable for CORE_0_INTR_RLS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_INTR_RLS to value 0"] +impl crate::Resettable for CORE_0_INTR_RLS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_0.rs b/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_0.rs new file mode 100644 index 0000000000..e107393a4e --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_0.rs @@ -0,0 +1,61 @@ +#[doc = "Register `CORE_0_IRAM0_EXCEPTION_MONITOR_0` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_IRAM0_RECORDING_ADDR_0` reader - reg_core_0_iram0_recording_addr_0"] +pub type CORE_0_IRAM0_RECORDING_ADDR_0_R = crate::FieldReader; +#[doc = "Field `CORE_0_IRAM0_RECORDING_WR_0` reader - reg_core_0_iram0_recording_wr_0"] +pub type CORE_0_IRAM0_RECORDING_WR_0_R = crate::BitReader; +#[doc = "Field `CORE_0_IRAM0_RECORDING_LOADSTORE_0` reader - reg_core_0_iram0_recording_loadstore_0"] +pub type CORE_0_IRAM0_RECORDING_LOADSTORE_0_R = crate::BitReader; +impl R { + #[doc = "Bits 0:23 - reg_core_0_iram0_recording_addr_0"] + #[inline(always)] + pub fn core_0_iram0_recording_addr_0(&self) -> CORE_0_IRAM0_RECORDING_ADDR_0_R { + CORE_0_IRAM0_RECORDING_ADDR_0_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bit 24 - reg_core_0_iram0_recording_wr_0"] + #[inline(always)] + pub fn core_0_iram0_recording_wr_0(&self) -> CORE_0_IRAM0_RECORDING_WR_0_R { + CORE_0_IRAM0_RECORDING_WR_0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reg_core_0_iram0_recording_loadstore_0"] + #[inline(always)] + pub fn core_0_iram0_recording_loadstore_0(&self) -> CORE_0_IRAM0_RECORDING_LOADSTORE_0_R { + CORE_0_IRAM0_RECORDING_LOADSTORE_0_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_0") + .field( + "core_0_iram0_recording_addr_0", + &format_args!("{}", self.core_0_iram0_recording_addr_0().bits()), + ) + .field( + "core_0_iram0_recording_wr_0", + &format_args!("{}", self.core_0_iram0_recording_wr_0().bit()), + ) + .field( + "core_0_iram0_recording_loadstore_0", + &format_args!("{}", self.core_0_iram0_recording_loadstore_0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC; +impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_iram0_exception_monitor_0::R`](R) reader structure"] +impl crate::Readable for CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC {} +#[doc = "`reset()` method sets CORE_0_IRAM0_EXCEPTION_MONITOR_0 to value 0"] +impl crate::Resettable for CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_1.rs b/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_1.rs new file mode 100644 index 0000000000..30153f899f --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_1.rs @@ -0,0 +1,61 @@ +#[doc = "Register `CORE_0_IRAM0_EXCEPTION_MONITOR_1` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_IRAM0_RECORDING_ADDR_1` reader - reg_core_0_iram0_recording_addr_1"] +pub type CORE_0_IRAM0_RECORDING_ADDR_1_R = crate::FieldReader; +#[doc = "Field `CORE_0_IRAM0_RECORDING_WR_1` reader - reg_core_0_iram0_recording_wr_1"] +pub type CORE_0_IRAM0_RECORDING_WR_1_R = crate::BitReader; +#[doc = "Field `CORE_0_IRAM0_RECORDING_LOADSTORE_1` reader - reg_core_0_iram0_recording_loadstore_1"] +pub type CORE_0_IRAM0_RECORDING_LOADSTORE_1_R = crate::BitReader; +impl R { + #[doc = "Bits 0:23 - reg_core_0_iram0_recording_addr_1"] + #[inline(always)] + pub fn core_0_iram0_recording_addr_1(&self) -> CORE_0_IRAM0_RECORDING_ADDR_1_R { + CORE_0_IRAM0_RECORDING_ADDR_1_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bit 24 - reg_core_0_iram0_recording_wr_1"] + #[inline(always)] + pub fn core_0_iram0_recording_wr_1(&self) -> CORE_0_IRAM0_RECORDING_WR_1_R { + CORE_0_IRAM0_RECORDING_WR_1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reg_core_0_iram0_recording_loadstore_1"] + #[inline(always)] + pub fn core_0_iram0_recording_loadstore_1(&self) -> CORE_0_IRAM0_RECORDING_LOADSTORE_1_R { + CORE_0_IRAM0_RECORDING_LOADSTORE_1_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_1") + .field( + "core_0_iram0_recording_addr_1", + &format_args!("{}", self.core_0_iram0_recording_addr_1().bits()), + ) + .field( + "core_0_iram0_recording_wr_1", + &format_args!("{}", self.core_0_iram0_recording_wr_1().bit()), + ) + .field( + "core_0_iram0_recording_loadstore_1", + &format_args!("{}", self.core_0_iram0_recording_loadstore_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC; +impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_iram0_exception_monitor_1::R`](R) reader structure"] +impl crate::Readable for CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC {} +#[doc = "`reset()` method sets CORE_0_IRAM0_EXCEPTION_MONITOR_1 to value 0"] +impl crate::Resettable for CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_lastpc_before_exception.rs b/esp32p4/src/assist_debug/core_0_lastpc_before_exception.rs new file mode 100644 index 0000000000..480892c561 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_lastpc_before_exception.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_0_LASTPC_BEFORE_EXCEPTION` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_LASTPC_BEFORE_EXC` reader - cpu's lastpc before exception"] +pub type CORE_0_LASTPC_BEFORE_EXC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - cpu's lastpc before exception"] + #[inline(always)] + pub fn core_0_lastpc_before_exc(&self) -> CORE_0_LASTPC_BEFORE_EXC_R { + CORE_0_LASTPC_BEFORE_EXC_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_LASTPC_BEFORE_EXCEPTION") + .field( + "core_0_lastpc_before_exc", + &format_args!("{}", self.core_0_lastpc_before_exc().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_lastpc_before_exception::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_LASTPC_BEFORE_EXCEPTION_SPEC; +impl crate::RegisterSpec for CORE_0_LASTPC_BEFORE_EXCEPTION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_lastpc_before_exception::R`](R) reader structure"] +impl crate::Readable for CORE_0_LASTPC_BEFORE_EXCEPTION_SPEC {} +#[doc = "`reset()` method sets CORE_0_LASTPC_BEFORE_EXCEPTION to value 0"] +impl crate::Resettable for CORE_0_LASTPC_BEFORE_EXCEPTION_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_rcd_en.rs b/esp32p4/src/assist_debug/core_0_rcd_en.rs new file mode 100644 index 0000000000..7b1071b756 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_rcd_en.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CORE_0_RCD_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_RCD_EN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_RCD_RECORDEN` reader - Set 1 to enable record PC"] +pub type CORE_0_RCD_RECORDEN_R = crate::BitReader; +#[doc = "Field `CORE_0_RCD_RECORDEN` writer - Set 1 to enable record PC"] +pub type CORE_0_RCD_RECORDEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_0_RCD_PDEBUGEN` reader - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC"] +pub type CORE_0_RCD_PDEBUGEN_R = crate::BitReader; +#[doc = "Field `CORE_0_RCD_PDEBUGEN` writer - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC"] +pub type CORE_0_RCD_PDEBUGEN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 to enable record PC"] + #[inline(always)] + pub fn core_0_rcd_recorden(&self) -> CORE_0_RCD_RECORDEN_R { + CORE_0_RCD_RECORDEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC"] + #[inline(always)] + pub fn core_0_rcd_pdebugen(&self) -> CORE_0_RCD_PDEBUGEN_R { + CORE_0_RCD_PDEBUGEN_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_RCD_EN") + .field( + "core_0_rcd_recorden", + &format_args!("{}", self.core_0_rcd_recorden().bit()), + ) + .field( + "core_0_rcd_pdebugen", + &format_args!("{}", self.core_0_rcd_pdebugen().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 to enable record PC"] + #[inline(always)] + #[must_use] + pub fn core_0_rcd_recorden(&mut self) -> CORE_0_RCD_RECORDEN_W { + CORE_0_RCD_RECORDEN_W::new(self, 0) + } + #[doc = "Bit 1 - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC"] + #[inline(always)] + #[must_use] + pub fn core_0_rcd_pdebugen(&mut self) -> CORE_0_RCD_PDEBUGEN_W { + CORE_0_RCD_PDEBUGEN_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "record enable configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_rcd_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_RCD_EN_SPEC; +impl crate::RegisterSpec for CORE_0_RCD_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_rcd_en::R`](R) reader structure"] +impl crate::Readable for CORE_0_RCD_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_rcd_en::W`](W) writer structure"] +impl crate::Writable for CORE_0_RCD_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_RCD_EN to value 0"] +impl crate::Resettable for CORE_0_RCD_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_rcd_pdebugpc.rs b/esp32p4/src/assist_debug/core_0_rcd_pdebugpc.rs new file mode 100644 index 0000000000..1b0d55a958 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_rcd_pdebugpc.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_0_RCD_PDEBUGPC` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_RCD_PDEBUGPC` reader - recorded PC"] +pub type CORE_0_RCD_PDEBUGPC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - recorded PC"] + #[inline(always)] + pub fn core_0_rcd_pdebugpc(&self) -> CORE_0_RCD_PDEBUGPC_R { + CORE_0_RCD_PDEBUGPC_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_RCD_PDEBUGPC") + .field( + "core_0_rcd_pdebugpc", + &format_args!("{}", self.core_0_rcd_pdebugpc().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugpc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_RCD_PDEBUGPC_SPEC; +impl crate::RegisterSpec for CORE_0_RCD_PDEBUGPC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_rcd_pdebugpc::R`](R) reader structure"] +impl crate::Readable for CORE_0_RCD_PDEBUGPC_SPEC {} +#[doc = "`reset()` method sets CORE_0_RCD_PDEBUGPC to value 0"] +impl crate::Resettable for CORE_0_RCD_PDEBUGPC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_rcd_pdebugsp.rs b/esp32p4/src/assist_debug/core_0_rcd_pdebugsp.rs new file mode 100644 index 0000000000..ea2a17566a --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_rcd_pdebugsp.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_0_RCD_PDEBUGSP` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_RCD_PDEBUGSP` reader - recorded sp"] +pub type CORE_0_RCD_PDEBUGSP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - recorded sp"] + #[inline(always)] + pub fn core_0_rcd_pdebugsp(&self) -> CORE_0_RCD_PDEBUGSP_R { + CORE_0_RCD_PDEBUGSP_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_RCD_PDEBUGSP") + .field( + "core_0_rcd_pdebugsp", + &format_args!("{}", self.core_0_rcd_pdebugsp().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugsp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_RCD_PDEBUGSP_SPEC; +impl crate::RegisterSpec for CORE_0_RCD_PDEBUGSP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_rcd_pdebugsp::R`](R) reader structure"] +impl crate::Readable for CORE_0_RCD_PDEBUGSP_SPEC {} +#[doc = "`reset()` method sets CORE_0_RCD_PDEBUGSP to value 0"] +impl crate::Resettable for CORE_0_RCD_PDEBUGSP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_sp_max.rs b/esp32p4/src/assist_debug/core_0_sp_max.rs new file mode 100644 index 0000000000..0b08d46abb --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_sp_max.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_0_SP_MAX` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_SP_MAX` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_SP_MAX` reader - core0 sp pc status register"] +pub type CORE_0_SP_MAX_R = crate::FieldReader; +#[doc = "Field `CORE_0_SP_MAX` writer - core0 sp pc status register"] +pub type CORE_0_SP_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - core0 sp pc status register"] + #[inline(always)] + pub fn core_0_sp_max(&self) -> CORE_0_SP_MAX_R { + CORE_0_SP_MAX_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_SP_MAX") + .field( + "core_0_sp_max", + &format_args!("{}", self.core_0_sp_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - core0 sp pc status register"] + #[inline(always)] + #[must_use] + pub fn core_0_sp_max(&mut self) -> CORE_0_SP_MAX_W { + CORE_0_SP_MAX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "stack max value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_max::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_sp_max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_SP_MAX_SPEC; +impl crate::RegisterSpec for CORE_0_SP_MAX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_sp_max::R`](R) reader structure"] +impl crate::Readable for CORE_0_SP_MAX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_sp_max::W`](W) writer structure"] +impl crate::Writable for CORE_0_SP_MAX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_SP_MAX to value 0xffff_ffff"] +impl crate::Resettable for CORE_0_SP_MAX_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/assist_debug/core_0_sp_min.rs b/esp32p4/src/assist_debug/core_0_sp_min.rs new file mode 100644 index 0000000000..44506068d4 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_sp_min.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_0_SP_MIN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_0_SP_MIN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_0_SP_MIN` reader - core0 sp region configuration regsiter"] +pub type CORE_0_SP_MIN_R = crate::FieldReader; +#[doc = "Field `CORE_0_SP_MIN` writer - core0 sp region configuration regsiter"] +pub type CORE_0_SP_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - core0 sp region configuration regsiter"] + #[inline(always)] + pub fn core_0_sp_min(&self) -> CORE_0_SP_MIN_R { + CORE_0_SP_MIN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_SP_MIN") + .field( + "core_0_sp_min", + &format_args!("{}", self.core_0_sp_min().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - core0 sp region configuration regsiter"] + #[inline(always)] + #[must_use] + pub fn core_0_sp_min(&mut self) -> CORE_0_SP_MIN_W { + CORE_0_SP_MIN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "stack min value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_min::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_0_sp_min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_SP_MIN_SPEC; +impl crate::RegisterSpec for CORE_0_SP_MIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_sp_min::R`](R) reader structure"] +impl crate::Readable for CORE_0_SP_MIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_0_sp_min::W`](W) writer structure"] +impl crate::Writable for CORE_0_SP_MIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_0_SP_MIN to value 0"] +impl crate::Resettable for CORE_0_SP_MIN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_0_sp_pc.rs b/esp32p4/src/assist_debug/core_0_sp_pc.rs new file mode 100644 index 0000000000..ef35585885 --- /dev/null +++ b/esp32p4/src/assist_debug/core_0_sp_pc.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_0_SP_PC` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_0_SP_PC` reader - This regsiter stores the PC when trigger stack monitor."] +pub type CORE_0_SP_PC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This regsiter stores the PC when trigger stack monitor."] + #[inline(always)] + pub fn core_0_sp_pc(&self) -> CORE_0_SP_PC_R { + CORE_0_SP_PC_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_0_SP_PC") + .field( + "core_0_sp_pc", + &format_args!("{}", self.core_0_sp_pc().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "stack monitor pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_0_SP_PC_SPEC; +impl crate::RegisterSpec for CORE_0_SP_PC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_0_sp_pc::R`](R) reader structure"] +impl crate::Readable for CORE_0_SP_PC_SPEC {} +#[doc = "`reset()` method sets CORE_0_SP_PC to value 0"] +impl crate::Resettable for CORE_0_SP_PC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_area_dram0_0_max.rs b/esp32p4/src/assist_debug/core_1_area_dram0_0_max.rs new file mode 100644 index 0000000000..cadd3bff7c --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_area_dram0_0_max.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE_1_AREA_DRAM0_0_MAX` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_AREA_DRAM0_0_MAX` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_AREA_DRAM0_0_MAX` reader - Core1 dram0 region0 end addr"] +pub type CORE_1_AREA_DRAM0_0_MAX_R = crate::FieldReader; +#[doc = "Field `CORE_1_AREA_DRAM0_0_MAX` writer - Core1 dram0 region0 end addr"] +pub type CORE_1_AREA_DRAM0_0_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core1 dram0 region0 end addr"] + #[inline(always)] + pub fn core_1_area_dram0_0_max(&self) -> CORE_1_AREA_DRAM0_0_MAX_R { + CORE_1_AREA_DRAM0_0_MAX_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_AREA_DRAM0_0_MAX") + .field( + "core_1_area_dram0_0_max", + &format_args!("{}", self.core_1_area_dram0_0_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core1 dram0 region0 end addr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_0_max( + &mut self, + ) -> CORE_1_AREA_DRAM0_0_MAX_W { + CORE_1_AREA_DRAM0_0_MAX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core1 dram0 region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_dram0_0_max::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_dram0_0_max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_AREA_DRAM0_0_MAX_SPEC; +impl crate::RegisterSpec for CORE_1_AREA_DRAM0_0_MAX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_area_dram0_0_max::R`](R) reader structure"] +impl crate::Readable for CORE_1_AREA_DRAM0_0_MAX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_area_dram0_0_max::W`](W) writer structure"] +impl crate::Writable for CORE_1_AREA_DRAM0_0_MAX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_AREA_DRAM0_0_MAX to value 0"] +impl crate::Resettable for CORE_1_AREA_DRAM0_0_MAX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_area_dram0_0_min.rs b/esp32p4/src/assist_debug/core_1_area_dram0_0_min.rs new file mode 100644 index 0000000000..58cd5124c2 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_area_dram0_0_min.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE_1_AREA_DRAM0_0_MIN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_AREA_DRAM0_0_MIN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_AREA_DRAM0_0_MIN` reader - Core1 dram0 region0 start addr"] +pub type CORE_1_AREA_DRAM0_0_MIN_R = crate::FieldReader; +#[doc = "Field `CORE_1_AREA_DRAM0_0_MIN` writer - Core1 dram0 region0 start addr"] +pub type CORE_1_AREA_DRAM0_0_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core1 dram0 region0 start addr"] + #[inline(always)] + pub fn core_1_area_dram0_0_min(&self) -> CORE_1_AREA_DRAM0_0_MIN_R { + CORE_1_AREA_DRAM0_0_MIN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_AREA_DRAM0_0_MIN") + .field( + "core_1_area_dram0_0_min", + &format_args!("{}", self.core_1_area_dram0_0_min().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core1 dram0 region0 start addr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_0_min( + &mut self, + ) -> CORE_1_AREA_DRAM0_0_MIN_W { + CORE_1_AREA_DRAM0_0_MIN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core1 dram0 region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_dram0_0_min::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_dram0_0_min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_AREA_DRAM0_0_MIN_SPEC; +impl crate::RegisterSpec for CORE_1_AREA_DRAM0_0_MIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_area_dram0_0_min::R`](R) reader structure"] +impl crate::Readable for CORE_1_AREA_DRAM0_0_MIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_area_dram0_0_min::W`](W) writer structure"] +impl crate::Writable for CORE_1_AREA_DRAM0_0_MIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_AREA_DRAM0_0_MIN to value 0xffff_ffff"] +impl crate::Resettable for CORE_1_AREA_DRAM0_0_MIN_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/assist_debug/core_1_area_dram0_1_max.rs b/esp32p4/src/assist_debug/core_1_area_dram0_1_max.rs new file mode 100644 index 0000000000..aef553c950 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_area_dram0_1_max.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE_1_AREA_DRAM0_1_MAX` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_AREA_DRAM0_1_MAX` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_AREA_DRAM0_1_MAX` reader - Core1 dram0 region1 end addr"] +pub type CORE_1_AREA_DRAM0_1_MAX_R = crate::FieldReader; +#[doc = "Field `CORE_1_AREA_DRAM0_1_MAX` writer - Core1 dram0 region1 end addr"] +pub type CORE_1_AREA_DRAM0_1_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core1 dram0 region1 end addr"] + #[inline(always)] + pub fn core_1_area_dram0_1_max(&self) -> CORE_1_AREA_DRAM0_1_MAX_R { + CORE_1_AREA_DRAM0_1_MAX_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_AREA_DRAM0_1_MAX") + .field( + "core_1_area_dram0_1_max", + &format_args!("{}", self.core_1_area_dram0_1_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core1 dram0 region1 end addr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_1_max( + &mut self, + ) -> CORE_1_AREA_DRAM0_1_MAX_W { + CORE_1_AREA_DRAM0_1_MAX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core1 dram0 region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_dram0_1_max::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_dram0_1_max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_AREA_DRAM0_1_MAX_SPEC; +impl crate::RegisterSpec for CORE_1_AREA_DRAM0_1_MAX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_area_dram0_1_max::R`](R) reader structure"] +impl crate::Readable for CORE_1_AREA_DRAM0_1_MAX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_area_dram0_1_max::W`](W) writer structure"] +impl crate::Writable for CORE_1_AREA_DRAM0_1_MAX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_AREA_DRAM0_1_MAX to value 0"] +impl crate::Resettable for CORE_1_AREA_DRAM0_1_MAX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_area_dram0_1_min.rs b/esp32p4/src/assist_debug/core_1_area_dram0_1_min.rs new file mode 100644 index 0000000000..3bf55633c1 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_area_dram0_1_min.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE_1_AREA_DRAM0_1_MIN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_AREA_DRAM0_1_MIN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_AREA_DRAM0_1_MIN` reader - Core1 dram0 region1 start addr"] +pub type CORE_1_AREA_DRAM0_1_MIN_R = crate::FieldReader; +#[doc = "Field `CORE_1_AREA_DRAM0_1_MIN` writer - Core1 dram0 region1 start addr"] +pub type CORE_1_AREA_DRAM0_1_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core1 dram0 region1 start addr"] + #[inline(always)] + pub fn core_1_area_dram0_1_min(&self) -> CORE_1_AREA_DRAM0_1_MIN_R { + CORE_1_AREA_DRAM0_1_MIN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_AREA_DRAM0_1_MIN") + .field( + "core_1_area_dram0_1_min", + &format_args!("{}", self.core_1_area_dram0_1_min().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core1 dram0 region1 start addr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_1_min( + &mut self, + ) -> CORE_1_AREA_DRAM0_1_MIN_W { + CORE_1_AREA_DRAM0_1_MIN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core1 dram0 region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_dram0_1_min::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_dram0_1_min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_AREA_DRAM0_1_MIN_SPEC; +impl crate::RegisterSpec for CORE_1_AREA_DRAM0_1_MIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_area_dram0_1_min::R`](R) reader structure"] +impl crate::Readable for CORE_1_AREA_DRAM0_1_MIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_area_dram0_1_min::W`](W) writer structure"] +impl crate::Writable for CORE_1_AREA_DRAM0_1_MIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_AREA_DRAM0_1_MIN to value 0xffff_ffff"] +impl crate::Resettable for CORE_1_AREA_DRAM0_1_MIN_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/assist_debug/core_1_area_pc.rs b/esp32p4/src/assist_debug/core_1_area_pc.rs new file mode 100644 index 0000000000..16d923f836 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_area_pc.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_1_AREA_PC` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_AREA_PC` reader - the stackpointer when first touch region monitor interrupt"] +pub type CORE_1_AREA_PC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - the stackpointer when first touch region monitor interrupt"] + #[inline(always)] + pub fn core_1_area_pc(&self) -> CORE_1_AREA_PC_R { + CORE_1_AREA_PC_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_AREA_PC") + .field( + "core_1_area_pc", + &format_args!("{}", self.core_1_area_pc().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "core1 area pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_AREA_PC_SPEC; +impl crate::RegisterSpec for CORE_1_AREA_PC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_area_pc::R`](R) reader structure"] +impl crate::Readable for CORE_1_AREA_PC_SPEC {} +#[doc = "`reset()` method sets CORE_1_AREA_PC to value 0"] +impl crate::Resettable for CORE_1_AREA_PC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_area_pif_0_max.rs b/esp32p4/src/assist_debug/core_1_area_pif_0_max.rs new file mode 100644 index 0000000000..a14a162d88 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_area_pif_0_max.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_1_AREA_PIF_0_MAX` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_AREA_PIF_0_MAX` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_AREA_PIF_0_MAX` reader - Core1 PIF region0 end addr"] +pub type CORE_1_AREA_PIF_0_MAX_R = crate::FieldReader; +#[doc = "Field `CORE_1_AREA_PIF_0_MAX` writer - Core1 PIF region0 end addr"] +pub type CORE_1_AREA_PIF_0_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core1 PIF region0 end addr"] + #[inline(always)] + pub fn core_1_area_pif_0_max(&self) -> CORE_1_AREA_PIF_0_MAX_R { + CORE_1_AREA_PIF_0_MAX_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_AREA_PIF_0_MAX") + .field( + "core_1_area_pif_0_max", + &format_args!("{}", self.core_1_area_pif_0_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core1 PIF region0 end addr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_0_max(&mut self) -> CORE_1_AREA_PIF_0_MAX_W { + CORE_1_AREA_PIF_0_MAX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core1 PIF region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pif_0_max::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_pif_0_max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_AREA_PIF_0_MAX_SPEC; +impl crate::RegisterSpec for CORE_1_AREA_PIF_0_MAX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_area_pif_0_max::R`](R) reader structure"] +impl crate::Readable for CORE_1_AREA_PIF_0_MAX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_area_pif_0_max::W`](W) writer structure"] +impl crate::Writable for CORE_1_AREA_PIF_0_MAX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_AREA_PIF_0_MAX to value 0"] +impl crate::Resettable for CORE_1_AREA_PIF_0_MAX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_area_pif_0_min.rs b/esp32p4/src/assist_debug/core_1_area_pif_0_min.rs new file mode 100644 index 0000000000..c2083c4e25 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_area_pif_0_min.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_1_AREA_PIF_0_MIN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_AREA_PIF_0_MIN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_AREA_PIF_0_MIN` reader - Core1 PIF region0 start addr"] +pub type CORE_1_AREA_PIF_0_MIN_R = crate::FieldReader; +#[doc = "Field `CORE_1_AREA_PIF_0_MIN` writer - Core1 PIF region0 start addr"] +pub type CORE_1_AREA_PIF_0_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core1 PIF region0 start addr"] + #[inline(always)] + pub fn core_1_area_pif_0_min(&self) -> CORE_1_AREA_PIF_0_MIN_R { + CORE_1_AREA_PIF_0_MIN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_AREA_PIF_0_MIN") + .field( + "core_1_area_pif_0_min", + &format_args!("{}", self.core_1_area_pif_0_min().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core1 PIF region0 start addr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_0_min(&mut self) -> CORE_1_AREA_PIF_0_MIN_W { + CORE_1_AREA_PIF_0_MIN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core1 PIF region0 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pif_0_min::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_pif_0_min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_AREA_PIF_0_MIN_SPEC; +impl crate::RegisterSpec for CORE_1_AREA_PIF_0_MIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_area_pif_0_min::R`](R) reader structure"] +impl crate::Readable for CORE_1_AREA_PIF_0_MIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_area_pif_0_min::W`](W) writer structure"] +impl crate::Writable for CORE_1_AREA_PIF_0_MIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_AREA_PIF_0_MIN to value 0xffff_ffff"] +impl crate::Resettable for CORE_1_AREA_PIF_0_MIN_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/assist_debug/core_1_area_pif_1_max.rs b/esp32p4/src/assist_debug/core_1_area_pif_1_max.rs new file mode 100644 index 0000000000..e3faaa5cbe --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_area_pif_1_max.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_1_AREA_PIF_1_MAX` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_AREA_PIF_1_MAX` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_AREA_PIF_1_MAX` reader - Core1 PIF region1 end addr"] +pub type CORE_1_AREA_PIF_1_MAX_R = crate::FieldReader; +#[doc = "Field `CORE_1_AREA_PIF_1_MAX` writer - Core1 PIF region1 end addr"] +pub type CORE_1_AREA_PIF_1_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core1 PIF region1 end addr"] + #[inline(always)] + pub fn core_1_area_pif_1_max(&self) -> CORE_1_AREA_PIF_1_MAX_R { + CORE_1_AREA_PIF_1_MAX_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_AREA_PIF_1_MAX") + .field( + "core_1_area_pif_1_max", + &format_args!("{}", self.core_1_area_pif_1_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core1 PIF region1 end addr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_1_max(&mut self) -> CORE_1_AREA_PIF_1_MAX_W { + CORE_1_AREA_PIF_1_MAX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core1 PIF region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pif_1_max::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_pif_1_max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_AREA_PIF_1_MAX_SPEC; +impl crate::RegisterSpec for CORE_1_AREA_PIF_1_MAX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_area_pif_1_max::R`](R) reader structure"] +impl crate::Readable for CORE_1_AREA_PIF_1_MAX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_area_pif_1_max::W`](W) writer structure"] +impl crate::Writable for CORE_1_AREA_PIF_1_MAX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_AREA_PIF_1_MAX to value 0"] +impl crate::Resettable for CORE_1_AREA_PIF_1_MAX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_area_pif_1_min.rs b/esp32p4/src/assist_debug/core_1_area_pif_1_min.rs new file mode 100644 index 0000000000..94b95b4772 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_area_pif_1_min.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_1_AREA_PIF_1_MIN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_AREA_PIF_1_MIN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_AREA_PIF_1_MIN` reader - Core1 PIF region1 start addr"] +pub type CORE_1_AREA_PIF_1_MIN_R = crate::FieldReader; +#[doc = "Field `CORE_1_AREA_PIF_1_MIN` writer - Core1 PIF region1 start addr"] +pub type CORE_1_AREA_PIF_1_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Core1 PIF region1 start addr"] + #[inline(always)] + pub fn core_1_area_pif_1_min(&self) -> CORE_1_AREA_PIF_1_MIN_R { + CORE_1_AREA_PIF_1_MIN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_AREA_PIF_1_MIN") + .field( + "core_1_area_pif_1_min", + &format_args!("{}", self.core_1_area_pif_1_min().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Core1 PIF region1 start addr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_1_min(&mut self) -> CORE_1_AREA_PIF_1_MIN_W { + CORE_1_AREA_PIF_1_MIN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core1 PIF region1 addr configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pif_1_min::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_area_pif_1_min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_AREA_PIF_1_MIN_SPEC; +impl crate::RegisterSpec for CORE_1_AREA_PIF_1_MIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_area_pif_1_min::R`](R) reader structure"] +impl crate::Readable for CORE_1_AREA_PIF_1_MIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_area_pif_1_min::W`](W) writer structure"] +impl crate::Writable for CORE_1_AREA_PIF_1_MIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_AREA_PIF_1_MIN to value 0xffff_ffff"] +impl crate::Resettable for CORE_1_AREA_PIF_1_MIN_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/assist_debug/core_1_area_sp.rs b/esp32p4/src/assist_debug/core_1_area_sp.rs new file mode 100644 index 0000000000..6ecd58151c --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_area_sp.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_1_AREA_SP` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_AREA_SP` reader - the PC when first touch region monitor interrupt"] +pub type CORE_1_AREA_SP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - the PC when first touch region monitor interrupt"] + #[inline(always)] + pub fn core_1_area_sp(&self) -> CORE_1_AREA_SP_R { + CORE_1_AREA_SP_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_AREA_SP") + .field( + "core_1_area_sp", + &format_args!("{}", self.core_1_area_sp().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "core1 area sp status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_sp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_AREA_SP_SPEC; +impl crate::RegisterSpec for CORE_1_AREA_SP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_area_sp::R`](R) reader structure"] +impl crate::Readable for CORE_1_AREA_SP_SPEC {} +#[doc = "`reset()` method sets CORE_1_AREA_SP to value 0"] +impl crate::Resettable for CORE_1_AREA_SP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_debug_mode.rs b/esp32p4/src/assist_debug/core_1_debug_mode.rs new file mode 100644 index 0000000000..7d00df58f6 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_debug_mode.rs @@ -0,0 +1,50 @@ +#[doc = "Register `CORE_1_DEBUG_MODE` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_DEBUG_MODE` reader - cpu debug mode status, 1 means cpu enter debug mode."] +pub type CORE_1_DEBUG_MODE_R = crate::BitReader; +#[doc = "Field `CORE_1_DEBUG_MODULE_ACTIVE` reader - cpu debug_module active status"] +pub type CORE_1_DEBUG_MODULE_ACTIVE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - cpu debug mode status, 1 means cpu enter debug mode."] + #[inline(always)] + pub fn core_1_debug_mode(&self) -> CORE_1_DEBUG_MODE_R { + CORE_1_DEBUG_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - cpu debug_module active status"] + #[inline(always)] + pub fn core_1_debug_module_active(&self) -> CORE_1_DEBUG_MODULE_ACTIVE_R { + CORE_1_DEBUG_MODULE_ACTIVE_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_DEBUG_MODE") + .field( + "core_1_debug_mode", + &format_args!("{}", self.core_1_debug_mode().bit()), + ) + .field( + "core_1_debug_module_active", + &format_args!("{}", self.core_1_debug_module_active().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_debug_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_DEBUG_MODE_SPEC; +impl crate::RegisterSpec for CORE_1_DEBUG_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_debug_mode::R`](R) reader structure"] +impl crate::Readable for CORE_1_DEBUG_MODE_SPEC {} +#[doc = "`reset()` method sets CORE_1_DEBUG_MODE to value 0"] +impl crate::Resettable for CORE_1_DEBUG_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_0.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_0.rs new file mode 100644 index 0000000000..7964b96d89 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_0.rs @@ -0,0 +1,50 @@ +#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_0` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_DRAM0_RECORDING_WR_0` reader - reg_core_1_dram0_recording_wr_0"] +pub type CORE_1_DRAM0_RECORDING_WR_0_R = crate::BitReader; +#[doc = "Field `CORE_1_DRAM0_RECORDING_BYTEEN_0` reader - reg_core_1_dram0_recording_byteen_0"] +pub type CORE_1_DRAM0_RECORDING_BYTEEN_0_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - reg_core_1_dram0_recording_wr_0"] + #[inline(always)] + pub fn core_1_dram0_recording_wr_0(&self) -> CORE_1_DRAM0_RECORDING_WR_0_R { + CORE_1_DRAM0_RECORDING_WR_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - reg_core_1_dram0_recording_byteen_0"] + #[inline(always)] + pub fn core_1_dram0_recording_byteen_0(&self) -> CORE_1_DRAM0_RECORDING_BYTEEN_0_R { + CORE_1_DRAM0_RECORDING_BYTEEN_0_R::new(((self.bits >> 1) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_0") + .field( + "core_1_dram0_recording_wr_0", + &format_args!("{}", self.core_1_dram0_recording_wr_0().bit()), + ) + .field( + "core_1_dram0_recording_byteen_0", + &format_args!("{}", self.core_1_dram0_recording_byteen_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC; +impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_0::R`](R) reader structure"] +impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC {} +#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_0 to value 0"] +impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_1.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_1.rs new file mode 100644 index 0000000000..3d36da7100 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_1` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_DRAM0_RECORDING_ADDR_0` reader - reg_core_1_dram0_recording_addr_0"] +pub type CORE_1_DRAM0_RECORDING_ADDR_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - reg_core_1_dram0_recording_addr_0"] + #[inline(always)] + pub fn core_1_dram0_recording_addr_0(&self) -> CORE_1_DRAM0_RECORDING_ADDR_0_R { + CORE_1_DRAM0_RECORDING_ADDR_0_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_1") + .field( + "core_1_dram0_recording_addr_0", + &format_args!("{}", self.core_1_dram0_recording_addr_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC; +impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_1::R`](R) reader structure"] +impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC {} +#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_1 to value 0"] +impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_2.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_2.rs new file mode 100644 index 0000000000..680944a32e --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_2` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_DRAM0_RECORDING_PC_0` reader - reg_core_1_dram0_recording_pc_0"] +pub type CORE_1_DRAM0_RECORDING_PC_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - reg_core_1_dram0_recording_pc_0"] + #[inline(always)] + pub fn core_1_dram0_recording_pc_0(&self) -> CORE_1_DRAM0_RECORDING_PC_0_R { + CORE_1_DRAM0_RECORDING_PC_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_2") + .field( + "core_1_dram0_recording_pc_0", + &format_args!("{}", self.core_1_dram0_recording_pc_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC; +impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_2::R`](R) reader structure"] +impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC {} +#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_2 to value 0"] +impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_3.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_3.rs new file mode 100644 index 0000000000..36ac6528a0 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_3.rs @@ -0,0 +1,50 @@ +#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_3` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_DRAM0_RECORDING_WR_1` reader - reg_core_1_dram0_recording_wr_1"] +pub type CORE_1_DRAM0_RECORDING_WR_1_R = crate::BitReader; +#[doc = "Field `CORE_1_DRAM0_RECORDING_BYTEEN_1` reader - reg_core_1_dram0_recording_byteen_1"] +pub type CORE_1_DRAM0_RECORDING_BYTEEN_1_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - reg_core_1_dram0_recording_wr_1"] + #[inline(always)] + pub fn core_1_dram0_recording_wr_1(&self) -> CORE_1_DRAM0_RECORDING_WR_1_R { + CORE_1_DRAM0_RECORDING_WR_1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - reg_core_1_dram0_recording_byteen_1"] + #[inline(always)] + pub fn core_1_dram0_recording_byteen_1(&self) -> CORE_1_DRAM0_RECORDING_BYTEEN_1_R { + CORE_1_DRAM0_RECORDING_BYTEEN_1_R::new(((self.bits >> 1) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_3") + .field( + "core_1_dram0_recording_wr_1", + &format_args!("{}", self.core_1_dram0_recording_wr_1().bit()), + ) + .field( + "core_1_dram0_recording_byteen_1", + &format_args!("{}", self.core_1_dram0_recording_byteen_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC; +impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_3::R`](R) reader structure"] +impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC {} +#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_3 to value 0"] +impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_4.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_4.rs new file mode 100644 index 0000000000..869cf9c22c --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_4` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_DRAM0_RECORDING_ADDR_1` reader - reg_core_1_dram0_recording_addr_1"] +pub type CORE_1_DRAM0_RECORDING_ADDR_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - reg_core_1_dram0_recording_addr_1"] + #[inline(always)] + pub fn core_1_dram0_recording_addr_1(&self) -> CORE_1_DRAM0_RECORDING_ADDR_1_R { + CORE_1_DRAM0_RECORDING_ADDR_1_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_4") + .field( + "core_1_dram0_recording_addr_1", + &format_args!("{}", self.core_1_dram0_recording_addr_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC; +impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_4::R`](R) reader structure"] +impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC {} +#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_4 to value 0"] +impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_5.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_5.rs new file mode 100644 index 0000000000..1ac73232a5 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_5` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_DRAM0_RECORDING_PC_1` reader - reg_core_1_dram0_recording_pc_1"] +pub type CORE_1_DRAM0_RECORDING_PC_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - reg_core_1_dram0_recording_pc_1"] + #[inline(always)] + pub fn core_1_dram0_recording_pc_1(&self) -> CORE_1_DRAM0_RECORDING_PC_1_R { + CORE_1_DRAM0_RECORDING_PC_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_5") + .field( + "core_1_dram0_recording_pc_1", + &format_args!("{}", self.core_1_dram0_recording_pc_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC; +impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_5::R`](R) reader structure"] +impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC {} +#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_5 to value 0"] +impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_intr_clr.rs b/esp32p4/src/assist_debug/core_1_intr_clr.rs new file mode 100644 index 0000000000..4c4df2d13b --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_intr_clr.rs @@ -0,0 +1,142 @@ +#[doc = "Register `CORE_1_INTR_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_CLR` writer - Core1 dram0 area0 read monitor interrupt clr"] +pub type CORE_1_AREA_DRAM0_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_CLR` writer - Core1 dram0 area0 write monitor interrupt clr"] +pub type CORE_1_AREA_DRAM0_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_CLR` writer - Core1 dram0 area1 read monitor interrupt clr"] +pub type CORE_1_AREA_DRAM0_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_CLR` writer - Core1 dram0 area1 write monitor interrupt clr"] +pub type CORE_1_AREA_DRAM0_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_0_RD_CLR` writer - Core1 PIF area0 read monitor interrupt clr"] +pub type CORE_1_AREA_PIF_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_0_WR_CLR` writer - Core1 PIF area0 write monitor interrupt clr"] +pub type CORE_1_AREA_PIF_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_1_RD_CLR` writer - Core1 PIF area1 read monitor interrupt clr"] +pub type CORE_1_AREA_PIF_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_1_WR_CLR` writer - Core1 PIF area1 write monitor interrupt clr"] +pub type CORE_1_AREA_PIF_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_SP_SPILL_MIN_CLR` writer - Core1 stackpoint underflow monitor interrupt clr"] +pub type CORE_1_SP_SPILL_MIN_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_SP_SPILL_MAX_CLR` writer - Core1 stackpoint overflow monitor interrupt clr"] +pub type CORE_1_SP_SPILL_MAX_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_CLR` writer - IBUS busy monitor interrupt clr"] +pub type CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_CLR` writer - DBUS busy monitor interrupt clr"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_0_rd_clr( + &mut self, + ) -> CORE_1_AREA_DRAM0_0_RD_CLR_W { + CORE_1_AREA_DRAM0_0_RD_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_0_wr_clr( + &mut self, + ) -> CORE_1_AREA_DRAM0_0_WR_CLR_W { + CORE_1_AREA_DRAM0_0_WR_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_1_rd_clr( + &mut self, + ) -> CORE_1_AREA_DRAM0_1_RD_CLR_W { + CORE_1_AREA_DRAM0_1_RD_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_1_wr_clr( + &mut self, + ) -> CORE_1_AREA_DRAM0_1_WR_CLR_W { + CORE_1_AREA_DRAM0_1_WR_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_0_rd_clr(&mut self) -> CORE_1_AREA_PIF_0_RD_CLR_W { + CORE_1_AREA_PIF_0_RD_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_0_wr_clr(&mut self) -> CORE_1_AREA_PIF_0_WR_CLR_W { + CORE_1_AREA_PIF_0_WR_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_1_rd_clr(&mut self) -> CORE_1_AREA_PIF_1_RD_CLR_W { + CORE_1_AREA_PIF_1_RD_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_1_wr_clr(&mut self) -> CORE_1_AREA_PIF_1_WR_CLR_W { + CORE_1_AREA_PIF_1_WR_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Core1 stackpoint underflow monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_sp_spill_min_clr(&mut self) -> CORE_1_SP_SPILL_MIN_CLR_W { + CORE_1_SP_SPILL_MIN_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Core1 stackpoint overflow monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_sp_spill_max_clr(&mut self) -> CORE_1_SP_SPILL_MAX_CLR_W { + CORE_1_SP_SPILL_MAX_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - IBUS busy monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_iram0_exception_monitor_clr( + &mut self, + ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_W { + CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - DBUS busy monitor interrupt clr"] + #[inline(always)] + #[must_use] + pub fn core_1_dram0_exception_monitor_clr( + &mut self, + ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_W { + CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core1 monitor interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_intr_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_INTR_CLR_SPEC; +impl crate::RegisterSpec for CORE_1_INTR_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`core_1_intr_clr::W`](W) writer structure"] +impl crate::Writable for CORE_1_INTR_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_INTR_CLR to value 0"] +impl crate::Resettable for CORE_1_INTR_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_intr_ena.rs b/esp32p4/src/assist_debug/core_1_intr_ena.rs new file mode 100644 index 0000000000..312144ba35 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_intr_ena.rs @@ -0,0 +1,287 @@ +#[doc = "Register `CORE_1_INTR_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_INTR_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_ENA` reader - Core1 dram0 area0 read monitor enable"] +pub type CORE_1_AREA_DRAM0_0_RD_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_ENA` writer - Core1 dram0 area0 read monitor enable"] +pub type CORE_1_AREA_DRAM0_0_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_ENA` reader - Core1 dram0 area0 write monitor enable"] +pub type CORE_1_AREA_DRAM0_0_WR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_ENA` writer - Core1 dram0 area0 write monitor enable"] +pub type CORE_1_AREA_DRAM0_0_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_ENA` reader - Core1 dram0 area1 read monitor enable"] +pub type CORE_1_AREA_DRAM0_1_RD_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_ENA` writer - Core1 dram0 area1 read monitor enable"] +pub type CORE_1_AREA_DRAM0_1_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_ENA` reader - Core1 dram0 area1 write monitor enable"] +pub type CORE_1_AREA_DRAM0_1_WR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_ENA` writer - Core1 dram0 area1 write monitor enable"] +pub type CORE_1_AREA_DRAM0_1_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_0_RD_ENA` reader - Core1 PIF area0 read monitor enable"] +pub type CORE_1_AREA_PIF_0_RD_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_0_RD_ENA` writer - Core1 PIF area0 read monitor enable"] +pub type CORE_1_AREA_PIF_0_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_0_WR_ENA` reader - Core1 PIF area0 write monitor enable"] +pub type CORE_1_AREA_PIF_0_WR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_0_WR_ENA` writer - Core1 PIF area0 write monitor enable"] +pub type CORE_1_AREA_PIF_0_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_1_RD_ENA` reader - Core1 PIF area1 read monitor enable"] +pub type CORE_1_AREA_PIF_1_RD_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_1_RD_ENA` writer - Core1 PIF area1 read monitor enable"] +pub type CORE_1_AREA_PIF_1_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_1_WR_ENA` reader - Core1 PIF area1 write monitor enable"] +pub type CORE_1_AREA_PIF_1_WR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_1_WR_ENA` writer - Core1 PIF area1 write monitor enable"] +pub type CORE_1_AREA_PIF_1_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_SP_SPILL_MIN_ENA` reader - Core1 stackpoint underflow monitor enable"] +pub type CORE_1_SP_SPILL_MIN_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_SP_SPILL_MIN_ENA` writer - Core1 stackpoint underflow monitor enable"] +pub type CORE_1_SP_SPILL_MIN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_SP_SPILL_MAX_ENA` reader - Core1 stackpoint overflow monitor enable"] +pub type CORE_1_SP_SPILL_MAX_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_SP_SPILL_MAX_ENA` writer - Core1 stackpoint overflow monitor enable"] +pub type CORE_1_SP_SPILL_MAX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_ENA` reader - IBUS busy monitor enable"] +pub type CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_ENA` writer - IBUS busy monitor enable"] +pub type CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_ENA` reader - DBUS busy monitor enbale"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_R = crate::BitReader; +#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_ENA` writer - DBUS busy monitor enbale"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Core1 dram0 area0 read monitor enable"] + #[inline(always)] + pub fn core_1_area_dram0_0_rd_ena(&self) -> CORE_1_AREA_DRAM0_0_RD_ENA_R { + CORE_1_AREA_DRAM0_0_RD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Core1 dram0 area0 write monitor enable"] + #[inline(always)] + pub fn core_1_area_dram0_0_wr_ena(&self) -> CORE_1_AREA_DRAM0_0_WR_ENA_R { + CORE_1_AREA_DRAM0_0_WR_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Core1 dram0 area1 read monitor enable"] + #[inline(always)] + pub fn core_1_area_dram0_1_rd_ena(&self) -> CORE_1_AREA_DRAM0_1_RD_ENA_R { + CORE_1_AREA_DRAM0_1_RD_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Core1 dram0 area1 write monitor enable"] + #[inline(always)] + pub fn core_1_area_dram0_1_wr_ena(&self) -> CORE_1_AREA_DRAM0_1_WR_ENA_R { + CORE_1_AREA_DRAM0_1_WR_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Core1 PIF area0 read monitor enable"] + #[inline(always)] + pub fn core_1_area_pif_0_rd_ena(&self) -> CORE_1_AREA_PIF_0_RD_ENA_R { + CORE_1_AREA_PIF_0_RD_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Core1 PIF area0 write monitor enable"] + #[inline(always)] + pub fn core_1_area_pif_0_wr_ena(&self) -> CORE_1_AREA_PIF_0_WR_ENA_R { + CORE_1_AREA_PIF_0_WR_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Core1 PIF area1 read monitor enable"] + #[inline(always)] + pub fn core_1_area_pif_1_rd_ena(&self) -> CORE_1_AREA_PIF_1_RD_ENA_R { + CORE_1_AREA_PIF_1_RD_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Core1 PIF area1 write monitor enable"] + #[inline(always)] + pub fn core_1_area_pif_1_wr_ena(&self) -> CORE_1_AREA_PIF_1_WR_ENA_R { + CORE_1_AREA_PIF_1_WR_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Core1 stackpoint underflow monitor enable"] + #[inline(always)] + pub fn core_1_sp_spill_min_ena(&self) -> CORE_1_SP_SPILL_MIN_ENA_R { + CORE_1_SP_SPILL_MIN_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Core1 stackpoint overflow monitor enable"] + #[inline(always)] + pub fn core_1_sp_spill_max_ena(&self) -> CORE_1_SP_SPILL_MAX_ENA_R { + CORE_1_SP_SPILL_MAX_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - IBUS busy monitor enable"] + #[inline(always)] + pub fn core_1_iram0_exception_monitor_ena(&self) -> CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_R { + CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DBUS busy monitor enbale"] + #[inline(always)] + pub fn core_1_dram0_exception_monitor_ena(&self) -> CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_R { + CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_INTR_ENA") + .field( + "core_1_area_dram0_0_rd_ena", + &format_args!("{}", self.core_1_area_dram0_0_rd_ena().bit()), + ) + .field( + "core_1_area_dram0_0_wr_ena", + &format_args!("{}", self.core_1_area_dram0_0_wr_ena().bit()), + ) + .field( + "core_1_area_dram0_1_rd_ena", + &format_args!("{}", self.core_1_area_dram0_1_rd_ena().bit()), + ) + .field( + "core_1_area_dram0_1_wr_ena", + &format_args!("{}", self.core_1_area_dram0_1_wr_ena().bit()), + ) + .field( + "core_1_area_pif_0_rd_ena", + &format_args!("{}", self.core_1_area_pif_0_rd_ena().bit()), + ) + .field( + "core_1_area_pif_0_wr_ena", + &format_args!("{}", self.core_1_area_pif_0_wr_ena().bit()), + ) + .field( + "core_1_area_pif_1_rd_ena", + &format_args!("{}", self.core_1_area_pif_1_rd_ena().bit()), + ) + .field( + "core_1_area_pif_1_wr_ena", + &format_args!("{}", self.core_1_area_pif_1_wr_ena().bit()), + ) + .field( + "core_1_sp_spill_min_ena", + &format_args!("{}", self.core_1_sp_spill_min_ena().bit()), + ) + .field( + "core_1_sp_spill_max_ena", + &format_args!("{}", self.core_1_sp_spill_max_ena().bit()), + ) + .field( + "core_1_iram0_exception_monitor_ena", + &format_args!("{}", self.core_1_iram0_exception_monitor_ena().bit()), + ) + .field( + "core_1_dram0_exception_monitor_ena", + &format_args!("{}", self.core_1_dram0_exception_monitor_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Core1 dram0 area0 read monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_0_rd_ena( + &mut self, + ) -> CORE_1_AREA_DRAM0_0_RD_ENA_W { + CORE_1_AREA_DRAM0_0_RD_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Core1 dram0 area0 write monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_0_wr_ena( + &mut self, + ) -> CORE_1_AREA_DRAM0_0_WR_ENA_W { + CORE_1_AREA_DRAM0_0_WR_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Core1 dram0 area1 read monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_1_rd_ena( + &mut self, + ) -> CORE_1_AREA_DRAM0_1_RD_ENA_W { + CORE_1_AREA_DRAM0_1_RD_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Core1 dram0 area1 write monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_1_wr_ena( + &mut self, + ) -> CORE_1_AREA_DRAM0_1_WR_ENA_W { + CORE_1_AREA_DRAM0_1_WR_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Core1 PIF area0 read monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_0_rd_ena(&mut self) -> CORE_1_AREA_PIF_0_RD_ENA_W { + CORE_1_AREA_PIF_0_RD_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - Core1 PIF area0 write monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_0_wr_ena(&mut self) -> CORE_1_AREA_PIF_0_WR_ENA_W { + CORE_1_AREA_PIF_0_WR_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - Core1 PIF area1 read monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_1_rd_ena(&mut self) -> CORE_1_AREA_PIF_1_RD_ENA_W { + CORE_1_AREA_PIF_1_RD_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - Core1 PIF area1 write monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_1_wr_ena(&mut self) -> CORE_1_AREA_PIF_1_WR_ENA_W { + CORE_1_AREA_PIF_1_WR_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - Core1 stackpoint underflow monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_1_sp_spill_min_ena(&mut self) -> CORE_1_SP_SPILL_MIN_ENA_W { + CORE_1_SP_SPILL_MIN_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - Core1 stackpoint overflow monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_1_sp_spill_max_ena(&mut self) -> CORE_1_SP_SPILL_MAX_ENA_W { + CORE_1_SP_SPILL_MAX_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - IBUS busy monitor enable"] + #[inline(always)] + #[must_use] + pub fn core_1_iram0_exception_monitor_ena( + &mut self, + ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_W { + CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - DBUS busy monitor enbale"] + #[inline(always)] + #[must_use] + pub fn core_1_dram0_exception_monitor_ena( + &mut self, + ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_W { + CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core1 monitor enable configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_intr_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_intr_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_INTR_ENA_SPEC; +impl crate::RegisterSpec for CORE_1_INTR_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_intr_ena::R`](R) reader structure"] +impl crate::Readable for CORE_1_INTR_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_intr_ena::W`](W) writer structure"] +impl crate::Writable for CORE_1_INTR_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_INTR_ENA to value 0"] +impl crate::Resettable for CORE_1_INTR_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_intr_raw.rs b/esp32p4/src/assist_debug/core_1_intr_raw.rs new file mode 100644 index 0000000000..1e62b45db2 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_intr_raw.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CORE_1_INTR_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_RAW` reader - Core1 dram0 area0 read monitor interrupt status"] +pub type CORE_1_AREA_DRAM0_0_RD_RAW_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_RAW` reader - Core1 dram0 area0 write monitor interrupt status"] +pub type CORE_1_AREA_DRAM0_0_WR_RAW_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_RAW` reader - Core1 dram0 area1 read monitor interrupt status"] +pub type CORE_1_AREA_DRAM0_1_RD_RAW_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_RAW` reader - Core1 dram0 area1 write monitor interrupt status"] +pub type CORE_1_AREA_DRAM0_1_WR_RAW_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_0_RD_RAW` reader - Core1 PIF area0 read monitor interrupt status"] +pub type CORE_1_AREA_PIF_0_RD_RAW_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_0_WR_RAW` reader - Core1 PIF area0 write monitor interrupt status"] +pub type CORE_1_AREA_PIF_0_WR_RAW_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_1_RD_RAW` reader - Core1 PIF area1 read monitor interrupt status"] +pub type CORE_1_AREA_PIF_1_RD_RAW_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_1_WR_RAW` reader - Core1 PIF area1 write monitor interrupt status"] +pub type CORE_1_AREA_PIF_1_WR_RAW_R = crate::BitReader; +#[doc = "Field `CORE_1_SP_SPILL_MIN_RAW` reader - Core1 stackpoint underflow monitor interrupt status"] +pub type CORE_1_SP_SPILL_MIN_RAW_R = crate::BitReader; +#[doc = "Field `CORE_1_SP_SPILL_MAX_RAW` reader - Core1 stackpoint overflow monitor interrupt status"] +pub type CORE_1_SP_SPILL_MAX_RAW_R = crate::BitReader; +#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_RAW` reader - IBUS busy monitor interrupt status"] +pub type CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_R = crate::BitReader; +#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_RAW` reader - DBUS busy monitor initerrupt status"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt status"] + #[inline(always)] + pub fn core_1_area_dram0_0_rd_raw(&self) -> CORE_1_AREA_DRAM0_0_RD_RAW_R { + CORE_1_AREA_DRAM0_0_RD_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt status"] + #[inline(always)] + pub fn core_1_area_dram0_0_wr_raw(&self) -> CORE_1_AREA_DRAM0_0_WR_RAW_R { + CORE_1_AREA_DRAM0_0_WR_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt status"] + #[inline(always)] + pub fn core_1_area_dram0_1_rd_raw(&self) -> CORE_1_AREA_DRAM0_1_RD_RAW_R { + CORE_1_AREA_DRAM0_1_RD_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt status"] + #[inline(always)] + pub fn core_1_area_dram0_1_wr_raw(&self) -> CORE_1_AREA_DRAM0_1_WR_RAW_R { + CORE_1_AREA_DRAM0_1_WR_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt status"] + #[inline(always)] + pub fn core_1_area_pif_0_rd_raw(&self) -> CORE_1_AREA_PIF_0_RD_RAW_R { + CORE_1_AREA_PIF_0_RD_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt status"] + #[inline(always)] + pub fn core_1_area_pif_0_wr_raw(&self) -> CORE_1_AREA_PIF_0_WR_RAW_R { + CORE_1_AREA_PIF_0_WR_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt status"] + #[inline(always)] + pub fn core_1_area_pif_1_rd_raw(&self) -> CORE_1_AREA_PIF_1_RD_RAW_R { + CORE_1_AREA_PIF_1_RD_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt status"] + #[inline(always)] + pub fn core_1_area_pif_1_wr_raw(&self) -> CORE_1_AREA_PIF_1_WR_RAW_R { + CORE_1_AREA_PIF_1_WR_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Core1 stackpoint underflow monitor interrupt status"] + #[inline(always)] + pub fn core_1_sp_spill_min_raw(&self) -> CORE_1_SP_SPILL_MIN_RAW_R { + CORE_1_SP_SPILL_MIN_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Core1 stackpoint overflow monitor interrupt status"] + #[inline(always)] + pub fn core_1_sp_spill_max_raw(&self) -> CORE_1_SP_SPILL_MAX_RAW_R { + CORE_1_SP_SPILL_MAX_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - IBUS busy monitor interrupt status"] + #[inline(always)] + pub fn core_1_iram0_exception_monitor_raw(&self) -> CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_R { + CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DBUS busy monitor initerrupt status"] + #[inline(always)] + pub fn core_1_dram0_exception_monitor_raw(&self) -> CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_R { + CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_INTR_RAW") + .field( + "core_1_area_dram0_0_rd_raw", + &format_args!("{}", self.core_1_area_dram0_0_rd_raw().bit()), + ) + .field( + "core_1_area_dram0_0_wr_raw", + &format_args!("{}", self.core_1_area_dram0_0_wr_raw().bit()), + ) + .field( + "core_1_area_dram0_1_rd_raw", + &format_args!("{}", self.core_1_area_dram0_1_rd_raw().bit()), + ) + .field( + "core_1_area_dram0_1_wr_raw", + &format_args!("{}", self.core_1_area_dram0_1_wr_raw().bit()), + ) + .field( + "core_1_area_pif_0_rd_raw", + &format_args!("{}", self.core_1_area_pif_0_rd_raw().bit()), + ) + .field( + "core_1_area_pif_0_wr_raw", + &format_args!("{}", self.core_1_area_pif_0_wr_raw().bit()), + ) + .field( + "core_1_area_pif_1_rd_raw", + &format_args!("{}", self.core_1_area_pif_1_rd_raw().bit()), + ) + .field( + "core_1_area_pif_1_wr_raw", + &format_args!("{}", self.core_1_area_pif_1_wr_raw().bit()), + ) + .field( + "core_1_sp_spill_min_raw", + &format_args!("{}", self.core_1_sp_spill_min_raw().bit()), + ) + .field( + "core_1_sp_spill_max_raw", + &format_args!("{}", self.core_1_sp_spill_max_raw().bit()), + ) + .field( + "core_1_iram0_exception_monitor_raw", + &format_args!("{}", self.core_1_iram0_exception_monitor_raw().bit()), + ) + .field( + "core_1_dram0_exception_monitor_raw", + &format_args!("{}", self.core_1_dram0_exception_monitor_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "core1 monitor interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_intr_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_INTR_RAW_SPEC; +impl crate::RegisterSpec for CORE_1_INTR_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_intr_raw::R`](R) reader structure"] +impl crate::Readable for CORE_1_INTR_RAW_SPEC {} +#[doc = "`reset()` method sets CORE_1_INTR_RAW to value 0"] +impl crate::Resettable for CORE_1_INTR_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_intr_rls.rs b/esp32p4/src/assist_debug/core_1_intr_rls.rs new file mode 100644 index 0000000000..e9394b46e3 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_intr_rls.rs @@ -0,0 +1,287 @@ +#[doc = "Register `CORE_1_INTR_RLS` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_INTR_RLS` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_RLS` reader - Core1 dram0 area0 read monitor interrupt enable"] +pub type CORE_1_AREA_DRAM0_0_RD_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_RLS` writer - Core1 dram0 area0 read monitor interrupt enable"] +pub type CORE_1_AREA_DRAM0_0_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_RLS` reader - Core1 dram0 area0 write monitor interrupt enable"] +pub type CORE_1_AREA_DRAM0_0_WR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_RLS` writer - Core1 dram0 area0 write monitor interrupt enable"] +pub type CORE_1_AREA_DRAM0_0_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_RLS` reader - Core1 dram0 area1 read monitor interrupt enable"] +pub type CORE_1_AREA_DRAM0_1_RD_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_RLS` writer - Core1 dram0 area1 read monitor interrupt enable"] +pub type CORE_1_AREA_DRAM0_1_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_RLS` reader - Core1 dram0 area1 write monitor interrupt enable"] +pub type CORE_1_AREA_DRAM0_1_WR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_RLS` writer - Core1 dram0 area1 write monitor interrupt enable"] +pub type CORE_1_AREA_DRAM0_1_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_0_RD_RLS` reader - Core1 PIF area0 read monitor interrupt enable"] +pub type CORE_1_AREA_PIF_0_RD_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_0_RD_RLS` writer - Core1 PIF area0 read monitor interrupt enable"] +pub type CORE_1_AREA_PIF_0_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_0_WR_RLS` reader - Core1 PIF area0 write monitor interrupt enable"] +pub type CORE_1_AREA_PIF_0_WR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_0_WR_RLS` writer - Core1 PIF area0 write monitor interrupt enable"] +pub type CORE_1_AREA_PIF_0_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_1_RD_RLS` reader - Core1 PIF area1 read monitor interrupt enable"] +pub type CORE_1_AREA_PIF_1_RD_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_1_RD_RLS` writer - Core1 PIF area1 read monitor interrupt enable"] +pub type CORE_1_AREA_PIF_1_RD_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_AREA_PIF_1_WR_RLS` reader - Core1 PIF area1 write monitor interrupt enable"] +pub type CORE_1_AREA_PIF_1_WR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_AREA_PIF_1_WR_RLS` writer - Core1 PIF area1 write monitor interrupt enable"] +pub type CORE_1_AREA_PIF_1_WR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_SP_SPILL_MIN_RLS` reader - Core1 stackpoint underflow monitor interrupt enable"] +pub type CORE_1_SP_SPILL_MIN_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_SP_SPILL_MIN_RLS` writer - Core1 stackpoint underflow monitor interrupt enable"] +pub type CORE_1_SP_SPILL_MIN_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_SP_SPILL_MAX_RLS` reader - Core1 stackpoint overflow monitor interrupt enable"] +pub type CORE_1_SP_SPILL_MAX_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_SP_SPILL_MAX_RLS` writer - Core1 stackpoint overflow monitor interrupt enable"] +pub type CORE_1_SP_SPILL_MAX_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_RLS` reader - IBUS busy monitor interrupt enable"] +pub type CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_RLS` writer - IBUS busy monitor interrupt enable"] +pub type CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_RLS` reader - DBUS busy monitor interrupt enbale"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_R = crate::BitReader; +#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_RLS` writer - DBUS busy monitor interrupt enbale"] +pub type CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt enable"] + #[inline(always)] + pub fn core_1_area_dram0_0_rd_rls(&self) -> CORE_1_AREA_DRAM0_0_RD_RLS_R { + CORE_1_AREA_DRAM0_0_RD_RLS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt enable"] + #[inline(always)] + pub fn core_1_area_dram0_0_wr_rls(&self) -> CORE_1_AREA_DRAM0_0_WR_RLS_R { + CORE_1_AREA_DRAM0_0_WR_RLS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt enable"] + #[inline(always)] + pub fn core_1_area_dram0_1_rd_rls(&self) -> CORE_1_AREA_DRAM0_1_RD_RLS_R { + CORE_1_AREA_DRAM0_1_RD_RLS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt enable"] + #[inline(always)] + pub fn core_1_area_dram0_1_wr_rls(&self) -> CORE_1_AREA_DRAM0_1_WR_RLS_R { + CORE_1_AREA_DRAM0_1_WR_RLS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt enable"] + #[inline(always)] + pub fn core_1_area_pif_0_rd_rls(&self) -> CORE_1_AREA_PIF_0_RD_RLS_R { + CORE_1_AREA_PIF_0_RD_RLS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt enable"] + #[inline(always)] + pub fn core_1_area_pif_0_wr_rls(&self) -> CORE_1_AREA_PIF_0_WR_RLS_R { + CORE_1_AREA_PIF_0_WR_RLS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt enable"] + #[inline(always)] + pub fn core_1_area_pif_1_rd_rls(&self) -> CORE_1_AREA_PIF_1_RD_RLS_R { + CORE_1_AREA_PIF_1_RD_RLS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt enable"] + #[inline(always)] + pub fn core_1_area_pif_1_wr_rls(&self) -> CORE_1_AREA_PIF_1_WR_RLS_R { + CORE_1_AREA_PIF_1_WR_RLS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Core1 stackpoint underflow monitor interrupt enable"] + #[inline(always)] + pub fn core_1_sp_spill_min_rls(&self) -> CORE_1_SP_SPILL_MIN_RLS_R { + CORE_1_SP_SPILL_MIN_RLS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Core1 stackpoint overflow monitor interrupt enable"] + #[inline(always)] + pub fn core_1_sp_spill_max_rls(&self) -> CORE_1_SP_SPILL_MAX_RLS_R { + CORE_1_SP_SPILL_MAX_RLS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - IBUS busy monitor interrupt enable"] + #[inline(always)] + pub fn core_1_iram0_exception_monitor_rls(&self) -> CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_R { + CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"] + #[inline(always)] + pub fn core_1_dram0_exception_monitor_rls(&self) -> CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_R { + CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_INTR_RLS") + .field( + "core_1_area_dram0_0_rd_rls", + &format_args!("{}", self.core_1_area_dram0_0_rd_rls().bit()), + ) + .field( + "core_1_area_dram0_0_wr_rls", + &format_args!("{}", self.core_1_area_dram0_0_wr_rls().bit()), + ) + .field( + "core_1_area_dram0_1_rd_rls", + &format_args!("{}", self.core_1_area_dram0_1_rd_rls().bit()), + ) + .field( + "core_1_area_dram0_1_wr_rls", + &format_args!("{}", self.core_1_area_dram0_1_wr_rls().bit()), + ) + .field( + "core_1_area_pif_0_rd_rls", + &format_args!("{}", self.core_1_area_pif_0_rd_rls().bit()), + ) + .field( + "core_1_area_pif_0_wr_rls", + &format_args!("{}", self.core_1_area_pif_0_wr_rls().bit()), + ) + .field( + "core_1_area_pif_1_rd_rls", + &format_args!("{}", self.core_1_area_pif_1_rd_rls().bit()), + ) + .field( + "core_1_area_pif_1_wr_rls", + &format_args!("{}", self.core_1_area_pif_1_wr_rls().bit()), + ) + .field( + "core_1_sp_spill_min_rls", + &format_args!("{}", self.core_1_sp_spill_min_rls().bit()), + ) + .field( + "core_1_sp_spill_max_rls", + &format_args!("{}", self.core_1_sp_spill_max_rls().bit()), + ) + .field( + "core_1_iram0_exception_monitor_rls", + &format_args!("{}", self.core_1_iram0_exception_monitor_rls().bit()), + ) + .field( + "core_1_dram0_exception_monitor_rls", + &format_args!("{}", self.core_1_dram0_exception_monitor_rls().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_0_rd_rls( + &mut self, + ) -> CORE_1_AREA_DRAM0_0_RD_RLS_W { + CORE_1_AREA_DRAM0_0_RD_RLS_W::new(self, 0) + } + #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_0_wr_rls( + &mut self, + ) -> CORE_1_AREA_DRAM0_0_WR_RLS_W { + CORE_1_AREA_DRAM0_0_WR_RLS_W::new(self, 1) + } + #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_1_rd_rls( + &mut self, + ) -> CORE_1_AREA_DRAM0_1_RD_RLS_W { + CORE_1_AREA_DRAM0_1_RD_RLS_W::new(self, 2) + } + #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_dram0_1_wr_rls( + &mut self, + ) -> CORE_1_AREA_DRAM0_1_WR_RLS_W { + CORE_1_AREA_DRAM0_1_WR_RLS_W::new(self, 3) + } + #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_0_rd_rls(&mut self) -> CORE_1_AREA_PIF_0_RD_RLS_W { + CORE_1_AREA_PIF_0_RD_RLS_W::new(self, 4) + } + #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_0_wr_rls(&mut self) -> CORE_1_AREA_PIF_0_WR_RLS_W { + CORE_1_AREA_PIF_0_WR_RLS_W::new(self, 5) + } + #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_1_rd_rls(&mut self) -> CORE_1_AREA_PIF_1_RD_RLS_W { + CORE_1_AREA_PIF_1_RD_RLS_W::new(self, 6) + } + #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_1_area_pif_1_wr_rls(&mut self) -> CORE_1_AREA_PIF_1_WR_RLS_W { + CORE_1_AREA_PIF_1_WR_RLS_W::new(self, 7) + } + #[doc = "Bit 8 - Core1 stackpoint underflow monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_1_sp_spill_min_rls(&mut self) -> CORE_1_SP_SPILL_MIN_RLS_W { + CORE_1_SP_SPILL_MIN_RLS_W::new(self, 8) + } + #[doc = "Bit 9 - Core1 stackpoint overflow monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_1_sp_spill_max_rls(&mut self) -> CORE_1_SP_SPILL_MAX_RLS_W { + CORE_1_SP_SPILL_MAX_RLS_W::new(self, 9) + } + #[doc = "Bit 10 - IBUS busy monitor interrupt enable"] + #[inline(always)] + #[must_use] + pub fn core_1_iram0_exception_monitor_rls( + &mut self, + ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_W { + CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_W::new(self, 10) + } + #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"] + #[inline(always)] + #[must_use] + pub fn core_1_dram0_exception_monitor_rls( + &mut self, + ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_W { + CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "core1 monitor interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_intr_rls::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_intr_rls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_INTR_RLS_SPEC; +impl crate::RegisterSpec for CORE_1_INTR_RLS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_intr_rls::R`](R) reader structure"] +impl crate::Readable for CORE_1_INTR_RLS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_intr_rls::W`](W) writer structure"] +impl crate::Writable for CORE_1_INTR_RLS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_INTR_RLS to value 0"] +impl crate::Resettable for CORE_1_INTR_RLS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_0.rs b/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_0.rs new file mode 100644 index 0000000000..0bf0724856 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_0.rs @@ -0,0 +1,61 @@ +#[doc = "Register `CORE_1_IRAM0_EXCEPTION_MONITOR_0` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_IRAM0_RECORDING_ADDR_0` reader - reg_core_1_iram0_recording_addr_0"] +pub type CORE_1_IRAM0_RECORDING_ADDR_0_R = crate::FieldReader; +#[doc = "Field `CORE_1_IRAM0_RECORDING_WR_0` reader - reg_core_1_iram0_recording_wr_0"] +pub type CORE_1_IRAM0_RECORDING_WR_0_R = crate::BitReader; +#[doc = "Field `CORE_1_IRAM0_RECORDING_LOADSTORE_0` reader - reg_core_1_iram0_recording_loadstore_0"] +pub type CORE_1_IRAM0_RECORDING_LOADSTORE_0_R = crate::BitReader; +impl R { + #[doc = "Bits 0:23 - reg_core_1_iram0_recording_addr_0"] + #[inline(always)] + pub fn core_1_iram0_recording_addr_0(&self) -> CORE_1_IRAM0_RECORDING_ADDR_0_R { + CORE_1_IRAM0_RECORDING_ADDR_0_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bit 24 - reg_core_1_iram0_recording_wr_0"] + #[inline(always)] + pub fn core_1_iram0_recording_wr_0(&self) -> CORE_1_IRAM0_RECORDING_WR_0_R { + CORE_1_IRAM0_RECORDING_WR_0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reg_core_1_iram0_recording_loadstore_0"] + #[inline(always)] + pub fn core_1_iram0_recording_loadstore_0(&self) -> CORE_1_IRAM0_RECORDING_LOADSTORE_0_R { + CORE_1_IRAM0_RECORDING_LOADSTORE_0_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_IRAM0_EXCEPTION_MONITOR_0") + .field( + "core_1_iram0_recording_addr_0", + &format_args!("{}", self.core_1_iram0_recording_addr_0().bits()), + ) + .field( + "core_1_iram0_recording_wr_0", + &format_args!("{}", self.core_1_iram0_recording_wr_0().bit()), + ) + .field( + "core_1_iram0_recording_loadstore_0", + &format_args!("{}", self.core_1_iram0_recording_loadstore_0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_iram0_exception_monitor_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC; +impl crate::RegisterSpec for CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_iram0_exception_monitor_0::R`](R) reader structure"] +impl crate::Readable for CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC {} +#[doc = "`reset()` method sets CORE_1_IRAM0_EXCEPTION_MONITOR_0 to value 0"] +impl crate::Resettable for CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_1.rs b/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_1.rs new file mode 100644 index 0000000000..1d5706a9f7 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_1.rs @@ -0,0 +1,61 @@ +#[doc = "Register `CORE_1_IRAM0_EXCEPTION_MONITOR_1` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_IRAM0_RECORDING_ADDR_1` reader - reg_core_1_iram0_recording_addr_1"] +pub type CORE_1_IRAM0_RECORDING_ADDR_1_R = crate::FieldReader; +#[doc = "Field `CORE_1_IRAM0_RECORDING_WR_1` reader - reg_core_1_iram0_recording_wr_1"] +pub type CORE_1_IRAM0_RECORDING_WR_1_R = crate::BitReader; +#[doc = "Field `CORE_1_IRAM0_RECORDING_LOADSTORE_1` reader - reg_core_1_iram0_recording_loadstore_1"] +pub type CORE_1_IRAM0_RECORDING_LOADSTORE_1_R = crate::BitReader; +impl R { + #[doc = "Bits 0:23 - reg_core_1_iram0_recording_addr_1"] + #[inline(always)] + pub fn core_1_iram0_recording_addr_1(&self) -> CORE_1_IRAM0_RECORDING_ADDR_1_R { + CORE_1_IRAM0_RECORDING_ADDR_1_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bit 24 - reg_core_1_iram0_recording_wr_1"] + #[inline(always)] + pub fn core_1_iram0_recording_wr_1(&self) -> CORE_1_IRAM0_RECORDING_WR_1_R { + CORE_1_IRAM0_RECORDING_WR_1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reg_core_1_iram0_recording_loadstore_1"] + #[inline(always)] + pub fn core_1_iram0_recording_loadstore_1(&self) -> CORE_1_IRAM0_RECORDING_LOADSTORE_1_R { + CORE_1_IRAM0_RECORDING_LOADSTORE_1_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_IRAM0_EXCEPTION_MONITOR_1") + .field( + "core_1_iram0_recording_addr_1", + &format_args!("{}", self.core_1_iram0_recording_addr_1().bits()), + ) + .field( + "core_1_iram0_recording_wr_1", + &format_args!("{}", self.core_1_iram0_recording_wr_1().bit()), + ) + .field( + "core_1_iram0_recording_loadstore_1", + &format_args!("{}", self.core_1_iram0_recording_loadstore_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exception monitor status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_iram0_exception_monitor_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC; +impl crate::RegisterSpec for CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_iram0_exception_monitor_1::R`](R) reader structure"] +impl crate::Readable for CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC {} +#[doc = "`reset()` method sets CORE_1_IRAM0_EXCEPTION_MONITOR_1 to value 0"] +impl crate::Resettable for CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_lastpc_before_exception.rs b/esp32p4/src/assist_debug/core_1_lastpc_before_exception.rs new file mode 100644 index 0000000000..8c0480f673 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_lastpc_before_exception.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_1_LASTPC_BEFORE_EXCEPTION` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_LASTPC_BEFORE_EXC` reader - cpu's lastpc before exception"] +pub type CORE_1_LASTPC_BEFORE_EXC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - cpu's lastpc before exception"] + #[inline(always)] + pub fn core_1_lastpc_before_exc(&self) -> CORE_1_LASTPC_BEFORE_EXC_R { + CORE_1_LASTPC_BEFORE_EXC_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_LASTPC_BEFORE_EXCEPTION") + .field( + "core_1_lastpc_before_exc", + &format_args!("{}", self.core_1_lastpc_before_exc().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_lastpc_before_exception::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_LASTPC_BEFORE_EXCEPTION_SPEC; +impl crate::RegisterSpec for CORE_1_LASTPC_BEFORE_EXCEPTION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_lastpc_before_exception::R`](R) reader structure"] +impl crate::Readable for CORE_1_LASTPC_BEFORE_EXCEPTION_SPEC {} +#[doc = "`reset()` method sets CORE_1_LASTPC_BEFORE_EXCEPTION to value 0"] +impl crate::Resettable for CORE_1_LASTPC_BEFORE_EXCEPTION_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_rcd_en.rs b/esp32p4/src/assist_debug/core_1_rcd_en.rs new file mode 100644 index 0000000000..1fb8bf70b6 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_rcd_en.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CORE_1_RCD_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_RCD_EN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_RCD_RECORDEN` reader - Set 1 to enable record PC"] +pub type CORE_1_RCD_RECORDEN_R = crate::BitReader; +#[doc = "Field `CORE_1_RCD_RECORDEN` writer - Set 1 to enable record PC"] +pub type CORE_1_RCD_RECORDEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE_1_RCD_PDEBUGEN` reader - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC"] +pub type CORE_1_RCD_PDEBUGEN_R = crate::BitReader; +#[doc = "Field `CORE_1_RCD_PDEBUGEN` writer - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC"] +pub type CORE_1_RCD_PDEBUGEN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 to enable record PC"] + #[inline(always)] + pub fn core_1_rcd_recorden(&self) -> CORE_1_RCD_RECORDEN_R { + CORE_1_RCD_RECORDEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC"] + #[inline(always)] + pub fn core_1_rcd_pdebugen(&self) -> CORE_1_RCD_PDEBUGEN_R { + CORE_1_RCD_PDEBUGEN_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_RCD_EN") + .field( + "core_1_rcd_recorden", + &format_args!("{}", self.core_1_rcd_recorden().bit()), + ) + .field( + "core_1_rcd_pdebugen", + &format_args!("{}", self.core_1_rcd_pdebugen().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 to enable record PC"] + #[inline(always)] + #[must_use] + pub fn core_1_rcd_recorden(&mut self) -> CORE_1_RCD_RECORDEN_W { + CORE_1_RCD_RECORDEN_W::new(self, 0) + } + #[doc = "Bit 1 - Set 1 to enable cpu pdebug function, must set this bit can get cpu PC"] + #[inline(always)] + #[must_use] + pub fn core_1_rcd_pdebugen(&mut self) -> CORE_1_RCD_PDEBUGEN_W { + CORE_1_RCD_PDEBUGEN_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "record enable configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_rcd_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_RCD_EN_SPEC; +impl crate::RegisterSpec for CORE_1_RCD_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_rcd_en::R`](R) reader structure"] +impl crate::Readable for CORE_1_RCD_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_rcd_en::W`](W) writer structure"] +impl crate::Writable for CORE_1_RCD_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_RCD_EN to value 0"] +impl crate::Resettable for CORE_1_RCD_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_rcd_pdebugpc.rs b/esp32p4/src/assist_debug/core_1_rcd_pdebugpc.rs new file mode 100644 index 0000000000..d254065701 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_rcd_pdebugpc.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_1_RCD_PDEBUGPC` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_RCD_PDEBUGPC` reader - recorded PC"] +pub type CORE_1_RCD_PDEBUGPC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - recorded PC"] + #[inline(always)] + pub fn core_1_rcd_pdebugpc(&self) -> CORE_1_RCD_PDEBUGPC_R { + CORE_1_RCD_PDEBUGPC_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_RCD_PDEBUGPC") + .field( + "core_1_rcd_pdebugpc", + &format_args!("{}", self.core_1_rcd_pdebugpc().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugpc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_RCD_PDEBUGPC_SPEC; +impl crate::RegisterSpec for CORE_1_RCD_PDEBUGPC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_rcd_pdebugpc::R`](R) reader structure"] +impl crate::Readable for CORE_1_RCD_PDEBUGPC_SPEC {} +#[doc = "`reset()` method sets CORE_1_RCD_PDEBUGPC to value 0"] +impl crate::Resettable for CORE_1_RCD_PDEBUGPC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_rcd_pdebugsp.rs b/esp32p4/src/assist_debug/core_1_rcd_pdebugsp.rs new file mode 100644 index 0000000000..c87a7a52f2 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_rcd_pdebugsp.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_1_RCD_PDEBUGSP` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_RCD_PDEBUGSP` reader - recorded sp"] +pub type CORE_1_RCD_PDEBUGSP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - recorded sp"] + #[inline(always)] + pub fn core_1_rcd_pdebugsp(&self) -> CORE_1_RCD_PDEBUGSP_R { + CORE_1_RCD_PDEBUGSP_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_RCD_PDEBUGSP") + .field( + "core_1_rcd_pdebugsp", + &format_args!("{}", self.core_1_rcd_pdebugsp().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugsp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_RCD_PDEBUGSP_SPEC; +impl crate::RegisterSpec for CORE_1_RCD_PDEBUGSP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_rcd_pdebugsp::R`](R) reader structure"] +impl crate::Readable for CORE_1_RCD_PDEBUGSP_SPEC {} +#[doc = "`reset()` method sets CORE_1_RCD_PDEBUGSP to value 0"] +impl crate::Resettable for CORE_1_RCD_PDEBUGSP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_sp_max.rs b/esp32p4/src/assist_debug/core_1_sp_max.rs new file mode 100644 index 0000000000..31fbe12f67 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_sp_max.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_1_SP_MAX` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_SP_MAX` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_SP_MAX` reader - core1 sp pc status register"] +pub type CORE_1_SP_MAX_R = crate::FieldReader; +#[doc = "Field `CORE_1_SP_MAX` writer - core1 sp pc status register"] +pub type CORE_1_SP_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - core1 sp pc status register"] + #[inline(always)] + pub fn core_1_sp_max(&self) -> CORE_1_SP_MAX_R { + CORE_1_SP_MAX_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_SP_MAX") + .field( + "core_1_sp_max", + &format_args!("{}", self.core_1_sp_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - core1 sp pc status register"] + #[inline(always)] + #[must_use] + pub fn core_1_sp_max(&mut self) -> CORE_1_SP_MAX_W { + CORE_1_SP_MAX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "stack max value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_sp_max::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_sp_max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_SP_MAX_SPEC; +impl crate::RegisterSpec for CORE_1_SP_MAX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_sp_max::R`](R) reader structure"] +impl crate::Readable for CORE_1_SP_MAX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_sp_max::W`](W) writer structure"] +impl crate::Writable for CORE_1_SP_MAX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_SP_MAX to value 0xffff_ffff"] +impl crate::Resettable for CORE_1_SP_MAX_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/assist_debug/core_1_sp_min.rs b/esp32p4/src/assist_debug/core_1_sp_min.rs new file mode 100644 index 0000000000..0582bd2a2f --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_sp_min.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CORE_1_SP_MIN` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_1_SP_MIN` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_1_SP_MIN` reader - core1 sp region configuration regsiter"] +pub type CORE_1_SP_MIN_R = crate::FieldReader; +#[doc = "Field `CORE_1_SP_MIN` writer - core1 sp region configuration regsiter"] +pub type CORE_1_SP_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - core1 sp region configuration regsiter"] + #[inline(always)] + pub fn core_1_sp_min(&self) -> CORE_1_SP_MIN_R { + CORE_1_SP_MIN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_SP_MIN") + .field( + "core_1_sp_min", + &format_args!("{}", self.core_1_sp_min().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - core1 sp region configuration regsiter"] + #[inline(always)] + #[must_use] + pub fn core_1_sp_min(&mut self) -> CORE_1_SP_MIN_W { + CORE_1_SP_MIN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "stack min value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_sp_min::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_sp_min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_SP_MIN_SPEC; +impl crate::RegisterSpec for CORE_1_SP_MIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_sp_min::R`](R) reader structure"] +impl crate::Readable for CORE_1_SP_MIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_1_sp_min::W`](W) writer structure"] +impl crate::Writable for CORE_1_SP_MIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_1_SP_MIN to value 0"] +impl crate::Resettable for CORE_1_SP_MIN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_1_sp_pc.rs b/esp32p4/src/assist_debug/core_1_sp_pc.rs new file mode 100644 index 0000000000..19a2e55e62 --- /dev/null +++ b/esp32p4/src/assist_debug/core_1_sp_pc.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CORE_1_SP_PC` reader"] +pub type R = crate::R; +#[doc = "Field `CORE_1_SP_PC` reader - This regsiter stores the PC when trigger stack monitor."] +pub type CORE_1_SP_PC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This regsiter stores the PC when trigger stack monitor."] + #[inline(always)] + pub fn core_1_sp_pc(&self) -> CORE_1_SP_PC_R { + CORE_1_SP_PC_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_1_SP_PC") + .field( + "core_1_sp_pc", + &format_args!("{}", self.core_1_sp_pc().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "stack monitor pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_sp_pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_1_SP_PC_SPEC; +impl crate::RegisterSpec for CORE_1_SP_PC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_1_sp_pc::R`](R) reader structure"] +impl crate::Readable for CORE_1_SP_PC_SPEC {} +#[doc = "`reset()` method sets CORE_1_SP_PC to value 0"] +impl crate::Resettable for CORE_1_SP_PC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs b/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs new file mode 100644 index 0000000000..0ac075db55 --- /dev/null +++ b/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0` reader - reg_core_x_iram0_dram0_limit_cycle_0"] +pub type CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_R = crate::FieldReader; +#[doc = "Field `CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0` writer - reg_core_x_iram0_dram0_limit_cycle_0"] +pub type CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_0"] + #[inline(always)] + pub fn core_x_iram0_dram0_limit_cycle_0(&self) -> CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_R { + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0") + .field( + "core_x_iram0_dram0_limit_cycle_0", + &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_0"] + #[inline(always)] + #[must_use] + pub fn core_x_iram0_dram0_limit_cycle_0( + &mut self, + ) -> CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_W { + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "exception monitor status register6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_x_iram0_dram0_exception_monitor_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_x_iram0_dram0_exception_monitor_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC; +impl crate::RegisterSpec for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_x_iram0_dram0_exception_monitor_0::R`](R) reader structure"] +impl crate::Readable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_x_iram0_dram0_exception_monitor_0::W`](W) writer structure"] +impl crate::Writable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 to value 0"] +impl crate::Resettable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs b/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs new file mode 100644 index 0000000000..2d8ef443b3 --- /dev/null +++ b/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1` reader - reg_core_x_iram0_dram0_limit_cycle_1"] +pub type CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_R = crate::FieldReader; +#[doc = "Field `CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1` writer - reg_core_x_iram0_dram0_limit_cycle_1"] +pub type CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_1"] + #[inline(always)] + pub fn core_x_iram0_dram0_limit_cycle_1(&self) -> CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_R { + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1") + .field( + "core_x_iram0_dram0_limit_cycle_1", + &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_1"] + #[inline(always)] + #[must_use] + pub fn core_x_iram0_dram0_limit_cycle_1( + &mut self, + ) -> CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_W { + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "exception monitor status register7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_x_iram0_dram0_exception_monitor_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_x_iram0_dram0_exception_monitor_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC; +impl crate::RegisterSpec for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_x_iram0_dram0_exception_monitor_1::R`](R) reader structure"] +impl crate::Readable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_x_iram0_dram0_exception_monitor_1::W`](W) writer structure"] +impl crate::Writable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 to value 0"] +impl crate::Resettable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/assist_debug/date.rs b/esp32p4/src/assist_debug/date.rs new file mode 100644 index 0000000000..8d53d3a774 --- /dev/null +++ b/esp32p4/src/assist_debug/date.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `ASSIST_DEBUG_DATE` reader - version register"] +pub type ASSIST_DEBUG_DATE_R = crate::FieldReader; +#[doc = "Field `ASSIST_DEBUG_DATE` writer - version register"] +pub type ASSIST_DEBUG_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - version register"] + #[inline(always)] + pub fn assist_debug_date(&self) -> ASSIST_DEBUG_DATE_R { + ASSIST_DEBUG_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field( + "assist_debug_date", + &format_args!("{}", self.assist_debug_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - version register"] + #[inline(always)] + #[must_use] + pub fn assist_debug_date(&mut self) -> ASSIST_DEBUG_DATE_W { + ASSIST_DEBUG_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0210_9130"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0210_9130; +} diff --git a/esp32p4/src/axi_dma.rs b/esp32p4/src/axi_dma.rs new file mode 100644 index 0000000000..3d2413aa0a --- /dev/null +++ b/esp32p4/src/axi_dma.rs @@ -0,0 +1,1193 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + in_int_raw_ch: (), + _reserved1: [u8; 0x04], + in_int_st_ch: (), + _reserved2: [u8; 0x04], + in_int_ena_ch: (), + _reserved3: [u8; 0x04], + in_int_clr_ch: (), + _reserved4: [u8; 0x04], + in_conf0_ch: (), + _reserved5: [u8; 0x04], + in_conf1_ch: (), + _reserved6: [u8; 0x04], + infifo_status_ch: (), + _reserved7: [u8; 0x04], + in_pop_ch: (), + _reserved8: [u8; 0x04], + in_link1_ch: (), + _reserved9: [u8; 0x04], + in_link2_ch: (), + _reserved10: [u8; 0x04], + in_state_ch: (), + _reserved11: [u8; 0x04], + in_suc_eof_des_addr_ch: (), + _reserved12: [u8; 0x04], + in_err_eof_des_addr_ch: (), + _reserved13: [u8; 0x04], + in_dscr_ch: (), + _reserved14: [u8; 0x04], + in_dscr_bf0_ch: (), + _reserved15: [u8; 0x04], + in_dscr_bf1_ch: (), + _reserved16: [u8; 0x04], + in_pri_ch: (), + _reserved17: [u8; 0x04], + in_peri_sel_ch: (), + _reserved18: [u8; 0x04], + in_crc_init_data_ch: (), + _reserved19: [u8; 0x04], + rx_crc_width_ch: (), + _reserved20: [u8; 0x04], + in_crc_clear_ch: (), + _reserved21: [u8; 0x04], + in_crc_final_result_ch: (), + _reserved22: [u8; 0x04], + rx_crc_en_wr_data_ch: (), + _reserved23: [u8; 0x04], + rx_crc_en_addr_ch: (), + _reserved24: [u8; 0x04], + rx_crc_data_en_wr_data_ch: (), + _reserved25: [u8; 0x04], + rx_crc_data_en_addr_ch: (), + _reserved26: [u8; 0xd4], + out_int_raw_ch: (), + _reserved27: [u8; 0x04], + out_int_st_ch: (), + _reserved28: [u8; 0x04], + out_int_ena_ch: (), + _reserved29: [u8; 0x04], + out_int_clr_ch: (), + _reserved30: [u8; 0x04], + out_conf0_ch0: OUT_CONF0_CH0, + out_conf1_ch: (), + _reserved32: [u8; 0x04], + outfifo_status_ch: (), + _reserved33: [u8; 0x04], + out_push_ch: (), + _reserved34: [u8; 0x04], + out_link1_ch: (), + _reserved35: [u8; 0x04], + out_link2_ch: (), + _reserved36: [u8; 0x04], + out_state_ch: (), + _reserved37: [u8; 0x04], + out_eof_des_addr_ch: (), + _reserved38: [u8; 0x04], + out_eof_bfr_des_addr_ch: (), + _reserved39: [u8; 0x04], + out_dscr_ch: (), + _reserved40: [u8; 0x04], + out_dscr_bf0_ch: (), + _reserved41: [u8; 0x04], + out_dscr_bf1_ch: (), + _reserved42: [u8; 0x04], + out_pri_ch: (), + _reserved43: [u8; 0x04], + out_peri_sel_ch: (), + _reserved44: [u8; 0x04], + out_crc_init_data_ch: (), + _reserved45: [u8; 0x04], + tx_crc_width_ch: (), + _reserved46: [u8; 0x04], + out_crc_clear_ch: (), + _reserved47: [u8; 0x04], + out_crc_final_result_ch: (), + _reserved48: [u8; 0x04], + tx_crc_en_wr_data_ch: (), + _reserved49: [u8; 0x04], + tx_crc_en_addr_ch: (), + _reserved50: [u8; 0x04], + tx_crc_data_en_wr_data_ch: (), + _reserved51: [u8; 0x04], + tx_crc_data_en_addr_ch: (), + _reserved52: [u8; 0x14], + out_conf0_ch1: OUT_CONF0_CH1, + _reserved53: [u8; 0x64], + out_conf0_ch2: OUT_CONF0_CH2, + _reserved54: [u8; 0x54], + arb_timeout: ARB_TIMEOUT, + weight_en: WEIGHT_EN, + in_mem_conf: IN_MEM_CONF, + intr_mem_start_addr: INTR_MEM_START_ADDR, + intr_mem_end_addr: INTR_MEM_END_ADDR, + extr_mem_start_addr: EXTR_MEM_START_ADDR, + extr_mem_end_addr: EXTR_MEM_END_ADDR, + in_reset_avail_ch: [IN_RESET_AVAIL_CH; 3], + out_reset_avail_ch: [OUT_RESET_AVAIL_CH; 3], + _reserved63: [u8; 0x04], + misc_conf: MISC_CONF, + rdn_result: RDN_RESULT, + rdn_eco_high: RDN_ECO_HIGH, + rdn_eco_low: RDN_ECO_LOW, + wresp_cnt: WRESP_CNT, + rresp_cnt: RRESP_CNT, + infifo_status1_ch: [INFIFO_STATUS1_CH; 3], + outfifo_status1_ch: [OUTFIFO_STATUS1_CH; 3], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00..0x0c - Raw status interrupt of channel 0"] + #[inline(always)] + pub const fn in_int_raw_ch(&self, n: usize) -> &IN_INT_RAW_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(0) + .add(104 * n) + .cast() + } + } + #[doc = "0x04..0x10 - Masked interrupt of channel 0"] + #[inline(always)] + pub const fn in_int_st_ch(&self, n: usize) -> &IN_INT_ST_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(4) + .add(104 * n) + .cast() + } + } + #[doc = "0x08..0x14 - Interrupt enable bits of channel 0"] + #[inline(always)] + pub const fn in_int_ena_ch(&self, n: usize) -> &IN_INT_ENA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(8) + .add(104 * n) + .cast() + } + } + #[doc = "0x0c..0x18 - Interrupt clear bits of channel 0"] + #[inline(always)] + pub const fn in_int_clr_ch(&self, n: usize) -> &IN_INT_CLR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(12) + .add(104 * n) + .cast() + } + } + #[doc = "0x10..0x1c - Configure 0 register of Rx channel 0"] + #[inline(always)] + pub const fn in_conf0_ch(&self, n: usize) -> &IN_CONF0_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(16) + .add(104 * n) + .cast() + } + } + #[doc = "0x14..0x20 - Configure 1 register of Rx channel 0"] + #[inline(always)] + pub const fn in_conf1_ch(&self, n: usize) -> &IN_CONF1_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(20) + .add(104 * n) + .cast() + } + } + #[doc = "0x18..0x24 - Receive FIFO status of Rx channel 0"] + #[inline(always)] + pub const fn infifo_status_ch(&self, n: usize) -> &INFIFO_STATUS_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(24) + .add(104 * n) + .cast() + } + } + #[doc = "0x1c..0x28 - Pop control register of Rx channel 0"] + #[inline(always)] + pub const fn in_pop_ch(&self, n: usize) -> &IN_POP_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(28) + .add(104 * n) + .cast() + } + } + #[doc = "0x20..0x2c - Link descriptor configure and control register of Rx channel 0"] + #[inline(always)] + pub const fn in_link1_ch(&self, n: usize) -> &IN_LINK1_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(32) + .add(104 * n) + .cast() + } + } + #[doc = "0x24..0x30 - Link descriptor configure and control register of Rx channel 0"] + #[inline(always)] + pub const fn in_link2_ch(&self, n: usize) -> &IN_LINK2_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(36) + .add(104 * n) + .cast() + } + } + #[doc = "0x28..0x34 - Receive status of Rx channel 0"] + #[inline(always)] + pub const fn in_state_ch(&self, n: usize) -> &IN_STATE_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(40) + .add(104 * n) + .cast() + } + } + #[doc = "0x2c..0x38 - Inlink descriptor address when EOF occurs of Rx channel 0"] + #[inline(always)] + pub const fn in_suc_eof_des_addr_ch(&self, n: usize) -> &IN_SUC_EOF_DES_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(44) + .add(104 * n) + .cast() + } + } + #[doc = "0x30..0x3c - Inlink descriptor address when errors occur of Rx channel 0"] + #[inline(always)] + pub const fn in_err_eof_des_addr_ch(&self, n: usize) -> &IN_ERR_EOF_DES_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(48) + .add(104 * n) + .cast() + } + } + #[doc = "0x34..0x40 - Current inlink descriptor address of Rx channel 0"] + #[inline(always)] + pub const fn in_dscr_ch(&self, n: usize) -> &IN_DSCR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(52) + .add(104 * n) + .cast() + } + } + #[doc = "0x38..0x44 - The last inlink descriptor address of Rx channel 0"] + #[inline(always)] + pub const fn in_dscr_bf0_ch(&self, n: usize) -> &IN_DSCR_BF0_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(56) + .add(104 * n) + .cast() + } + } + #[doc = "0x3c..0x48 - The second-to-last inlink descriptor address of Rx channel 0"] + #[inline(always)] + pub const fn in_dscr_bf1_ch(&self, n: usize) -> &IN_DSCR_BF1_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(60) + .add(104 * n) + .cast() + } + } + #[doc = "0x40..0x4c - Priority register of Rx channel 0"] + #[inline(always)] + pub const fn in_pri_ch(&self, n: usize) -> &IN_PRI_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(64) + .add(104 * n) + .cast() + } + } + #[doc = "0x44..0x50 - Peripheral selection of Rx channel 0"] + #[inline(always)] + pub const fn in_peri_sel_ch(&self, n: usize) -> &IN_PERI_SEL_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(68) + .add(104 * n) + .cast() + } + } + #[doc = "0x48..0x54 - This register is used to config ch0 crc initial data(max 32 bit)"] + #[inline(always)] + pub const fn in_crc_init_data_ch(&self, n: usize) -> &IN_CRC_INIT_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(72) + .add(104 * n) + .cast() + } + } + #[doc = "0x4c..0x58 - This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32"] + #[inline(always)] + pub const fn rx_crc_width_ch(&self, n: usize) -> &RX_CRC_WIDTH_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(76) + .add(104 * n) + .cast() + } + } + #[doc = "0x50..0x5c - This register is used to clear ch0 crc result"] + #[inline(always)] + pub const fn in_crc_clear_ch(&self, n: usize) -> &IN_CRC_CLEAR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(80) + .add(104 * n) + .cast() + } + } + #[doc = "0x54..0x60 - This register is used to store ch0 crc result"] + #[inline(always)] + pub const fn in_crc_final_result_ch(&self, n: usize) -> &IN_CRC_FINAL_RESULT_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(84) + .add(104 * n) + .cast() + } + } + #[doc = "0x58..0x64 - This resister is used to config ch0 crc en for every bit"] + #[inline(always)] + pub const fn rx_crc_en_wr_data_ch(&self, n: usize) -> &RX_CRC_EN_WR_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(88) + .add(104 * n) + .cast() + } + } + #[doc = "0x5c..0x68 - This register is used to config ch0 crc en addr"] + #[inline(always)] + pub const fn rx_crc_en_addr_ch(&self, n: usize) -> &RX_CRC_EN_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(92) + .add(104 * n) + .cast() + } + } + #[doc = "0x60..0x6c - This register is used to config crc data_8bit en"] + #[inline(always)] + pub const fn rx_crc_data_en_wr_data_ch(&self, n: usize) -> &RX_CRC_DATA_EN_WR_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(96) + .add(104 * n) + .cast() + } + } + #[doc = "0x64..0x70 - This register is used to config addr of crc data_8bit en"] + #[inline(always)] + pub const fn rx_crc_data_en_addr_ch(&self, n: usize) -> &RX_CRC_DATA_EN_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(100) + .add(104 * n) + .cast() + } + } + #[doc = "0x138..0x144 - Raw status interrupt of channel0"] + #[inline(always)] + pub const fn out_int_raw_ch(&self, n: usize) -> &OUT_INT_RAW_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(312) + .add(104 * n) + .cast() + } + } + #[doc = "0x13c..0x148 - Masked interrupt of channel0"] + #[inline(always)] + pub const fn out_int_st_ch(&self, n: usize) -> &OUT_INT_ST_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(316) + .add(104 * n) + .cast() + } + } + #[doc = "0x140..0x14c - Interrupt enable bits of channel0"] + #[inline(always)] + pub const fn out_int_ena_ch(&self, n: usize) -> &OUT_INT_ENA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(320) + .add(104 * n) + .cast() + } + } + #[doc = "0x144..0x150 - Interrupt clear bits of channel0"] + #[inline(always)] + pub const fn out_int_clr_ch(&self, n: usize) -> &OUT_INT_CLR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(324) + .add(104 * n) + .cast() + } + } + #[doc = "0x148 - Configure 0 register of Tx channel0"] + #[inline(always)] + pub const fn out_conf0_ch0(&self) -> &OUT_CONF0_CH0 { + &self.out_conf0_ch0 + } + #[doc = "0x14c..0x158 - Configure 1 register of Tx channel0"] + #[inline(always)] + pub const fn out_conf1_ch(&self, n: usize) -> &OUT_CONF1_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(332) + .add(104 * n) + .cast() + } + } + #[doc = "0x150..0x15c - Transmit FIFO status of Tx channel0"] + #[inline(always)] + pub const fn outfifo_status_ch(&self, n: usize) -> &OUTFIFO_STATUS_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(336) + .add(104 * n) + .cast() + } + } + #[doc = "0x154..0x160 - Push control register of Tx channel0"] + #[inline(always)] + pub const fn out_push_ch(&self, n: usize) -> &OUT_PUSH_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(340) + .add(104 * n) + .cast() + } + } + #[doc = "0x158..0x164 - Link descriptor configure and control register of Tx channel0"] + #[inline(always)] + pub const fn out_link1_ch(&self, n: usize) -> &OUT_LINK1_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(344) + .add(104 * n) + .cast() + } + } + #[doc = "0x15c..0x168 - Link descriptor configure and control register of Tx channel0"] + #[inline(always)] + pub const fn out_link2_ch(&self, n: usize) -> &OUT_LINK2_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(348) + .add(104 * n) + .cast() + } + } + #[doc = "0x160..0x16c - Transmit status of Tx channel0"] + #[inline(always)] + pub const fn out_state_ch(&self, n: usize) -> &OUT_STATE_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(352) + .add(104 * n) + .cast() + } + } + #[doc = "0x164..0x170 - Outlink descriptor address when EOF occurs of Tx channel0"] + #[inline(always)] + pub const fn out_eof_des_addr_ch(&self, n: usize) -> &OUT_EOF_DES_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(356) + .add(104 * n) + .cast() + } + } + #[doc = "0x168..0x174 - The last outlink descriptor address when EOF occurs of Tx channel0"] + #[inline(always)] + pub const fn out_eof_bfr_des_addr_ch(&self, n: usize) -> &OUT_EOF_BFR_DES_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(360) + .add(104 * n) + .cast() + } + } + #[doc = "0x16c..0x178 - Current outlink descriptor address of Tx channel0"] + #[inline(always)] + pub const fn out_dscr_ch(&self, n: usize) -> &OUT_DSCR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(364) + .add(104 * n) + .cast() + } + } + #[doc = "0x170..0x17c - The last outlink descriptor address of Tx channel0"] + #[inline(always)] + pub const fn out_dscr_bf0_ch(&self, n: usize) -> &OUT_DSCR_BF0_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(368) + .add(104 * n) + .cast() + } + } + #[doc = "0x174..0x180 - The second-to-last outlink descriptor address of Tx channel0"] + #[inline(always)] + pub const fn out_dscr_bf1_ch(&self, n: usize) -> &OUT_DSCR_BF1_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(372) + .add(104 * n) + .cast() + } + } + #[doc = "0x178..0x184 - Priority register of Tx channel0."] + #[inline(always)] + pub const fn out_pri_ch(&self, n: usize) -> &OUT_PRI_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(376) + .add(104 * n) + .cast() + } + } + #[doc = "0x17c..0x188 - Peripheral selection of Tx channel0"] + #[inline(always)] + pub const fn out_peri_sel_ch(&self, n: usize) -> &OUT_PERI_SEL_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(380) + .add(104 * n) + .cast() + } + } + #[doc = "0x180..0x18c - This register is used to config ch0 crc initial data(max 32 bit)"] + #[inline(always)] + pub const fn out_crc_init_data_ch(&self, n: usize) -> &OUT_CRC_INIT_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(384) + .add(104 * n) + .cast() + } + } + #[doc = "0x184..0x190 - This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32"] + #[inline(always)] + pub const fn tx_crc_width_ch(&self, n: usize) -> &TX_CRC_WIDTH_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(388) + .add(104 * n) + .cast() + } + } + #[doc = "0x188..0x194 - This register is used to clear ch0 crc result"] + #[inline(always)] + pub const fn out_crc_clear_ch(&self, n: usize) -> &OUT_CRC_CLEAR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(392) + .add(104 * n) + .cast() + } + } + #[doc = "0x18c..0x198 - This register is used to store ch0 crc result"] + #[inline(always)] + pub const fn out_crc_final_result_ch(&self, n: usize) -> &OUT_CRC_FINAL_RESULT_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(396) + .add(104 * n) + .cast() + } + } + #[doc = "0x190..0x19c - This resister is used to config ch0 crc en for every bit"] + #[inline(always)] + pub const fn tx_crc_en_wr_data_ch(&self, n: usize) -> &TX_CRC_EN_WR_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(400) + .add(104 * n) + .cast() + } + } + #[doc = "0x194..0x1a0 - This register is used to config ch0 crc en addr"] + #[inline(always)] + pub const fn tx_crc_en_addr_ch(&self, n: usize) -> &TX_CRC_EN_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(404) + .add(104 * n) + .cast() + } + } + #[doc = "0x198..0x1a4 - This register is used to config crc data_8bit en"] + #[inline(always)] + pub const fn tx_crc_data_en_wr_data_ch(&self, n: usize) -> &TX_CRC_DATA_EN_WR_DATA_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(408) + .add(104 * n) + .cast() + } + } + #[doc = "0x19c..0x1a8 - This register is used to config addr of crc data_8bit en"] + #[inline(always)] + pub const fn tx_crc_data_en_addr_ch(&self, n: usize) -> &TX_CRC_DATA_EN_ADDR_CH { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(412) + .add(104 * n) + .cast() + } + } + #[doc = "0x1b0 - Configure 0 register of Tx channel1"] + #[inline(always)] + pub const fn out_conf0_ch1(&self) -> &OUT_CONF0_CH1 { + &self.out_conf0_ch1 + } + #[doc = "0x218 - Configure 0 register of Tx channel2"] + #[inline(always)] + pub const fn out_conf0_ch2(&self) -> &OUT_CONF0_CH2 { + &self.out_conf0_ch2 + } + #[doc = "0x270 - This retister is used to config arbiter time slice"] + #[inline(always)] + pub const fn arb_timeout(&self) -> &ARB_TIMEOUT { + &self.arb_timeout + } + #[doc = "0x274 - This register is used to config arbiter weight function to on or off"] + #[inline(always)] + pub const fn weight_en(&self) -> &WEIGHT_EN { + &self.weight_en + } + #[doc = "0x278 - Mem power configure register of Rx channel"] + #[inline(always)] + pub const fn in_mem_conf(&self) -> &IN_MEM_CONF { + &self.in_mem_conf + } + #[doc = "0x27c - The start address of accessible address space."] + #[inline(always)] + pub const fn intr_mem_start_addr(&self) -> &INTR_MEM_START_ADDR { + &self.intr_mem_start_addr + } + #[doc = "0x280 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + pub const fn intr_mem_end_addr(&self) -> &INTR_MEM_END_ADDR { + &self.intr_mem_end_addr + } + #[doc = "0x284 - The start address of accessible address space."] + #[inline(always)] + pub const fn extr_mem_start_addr(&self) -> &EXTR_MEM_START_ADDR { + &self.extr_mem_start_addr + } + #[doc = "0x288 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + pub const fn extr_mem_end_addr(&self) -> &EXTR_MEM_END_ADDR { + &self.extr_mem_end_addr + } + #[doc = "0x28c..0x298 - The rx channel 0 reset valid_flag register."] + #[inline(always)] + pub const fn in_reset_avail_ch(&self, n: usize) -> &IN_RESET_AVAIL_CH { + &self.in_reset_avail_ch[n] + } + #[doc = "0x298..0x2a4 - The tx channel 0 reset valid_flag register."] + #[inline(always)] + pub const fn out_reset_avail_ch(&self, n: usize) -> &OUT_RESET_AVAIL_CH { + &self.out_reset_avail_ch[n] + } + #[doc = "0x2a8 - MISC register"] + #[inline(always)] + pub const fn misc_conf(&self) -> &MISC_CONF { + &self.misc_conf + } + #[doc = "0x2ac - reserved"] + #[inline(always)] + pub const fn rdn_result(&self) -> &RDN_RESULT { + &self.rdn_result + } + #[doc = "0x2b0 - reserved"] + #[inline(always)] + pub const fn rdn_eco_high(&self) -> &RDN_ECO_HIGH { + &self.rdn_eco_high + } + #[doc = "0x2b4 - reserved"] + #[inline(always)] + pub const fn rdn_eco_low(&self) -> &RDN_ECO_LOW { + &self.rdn_eco_low + } + #[doc = "0x2b8 - AXI wr responce cnt register."] + #[inline(always)] + pub const fn wresp_cnt(&self) -> &WRESP_CNT { + &self.wresp_cnt + } + #[doc = "0x2bc - AXI wr responce cnt register."] + #[inline(always)] + pub const fn rresp_cnt(&self) -> &RRESP_CNT { + &self.rresp_cnt + } + #[doc = "0x2c0..0x2cc - Receive FIFO status of Rx channel 0"] + #[inline(always)] + pub const fn infifo_status1_ch(&self, n: usize) -> &INFIFO_STATUS1_CH { + &self.infifo_status1_ch[n] + } + #[doc = "0x2cc..0x2d8 - Receive FIFO status of Tx channel 0"] + #[inline(always)] + pub const fn outfifo_status1_ch(&self, n: usize) -> &OUTFIFO_STATUS1_CH { + &self.outfifo_status1_ch[n] + } + #[doc = "0x2d8 - Version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "IN_INT_RAW_CH (rw) register accessor: Raw status interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_raw_ch`] module"] +pub type IN_INT_RAW_CH = crate::Reg; +#[doc = "Raw status interrupt of channel 0"] +pub mod in_int_raw_ch; +#[doc = "IN_INT_ST_CH (r) register accessor: Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_st_ch`] module"] +pub type IN_INT_ST_CH = crate::Reg; +#[doc = "Masked interrupt of channel 0"] +pub mod in_int_st_ch; +#[doc = "IN_INT_ENA_CH (rw) register accessor: Interrupt enable bits of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_ena_ch`] module"] +pub type IN_INT_ENA_CH = crate::Reg; +#[doc = "Interrupt enable bits of channel 0"] +pub mod in_int_ena_ch; +#[doc = "IN_INT_CLR_CH (w) register accessor: Interrupt clear bits of channel 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_clr_ch`] module"] +pub type IN_INT_CLR_CH = crate::Reg; +#[doc = "Interrupt clear bits of channel 0"] +pub mod in_int_clr_ch; +#[doc = "IN_CONF0_CH (rw) register accessor: Configure 0 register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf0_ch`] module"] +pub type IN_CONF0_CH = crate::Reg; +#[doc = "Configure 0 register of Rx channel 0"] +pub mod in_conf0_ch; +#[doc = "IN_CONF1_CH (rw) register accessor: Configure 1 register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf1_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf1_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf1_ch`] module"] +pub type IN_CONF1_CH = crate::Reg; +#[doc = "Configure 1 register of Rx channel 0"] +pub mod in_conf1_ch; +#[doc = "INFIFO_STATUS_CH (r) register accessor: Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@infifo_status_ch`] module"] +pub type INFIFO_STATUS_CH = crate::Reg; +#[doc = "Receive FIFO status of Rx channel 0"] +pub mod infifo_status_ch; +#[doc = "IN_POP_CH (rw) register accessor: Pop control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_ch`] module"] +pub type IN_POP_CH = crate::Reg; +#[doc = "Pop control register of Rx channel 0"] +pub mod in_pop_ch; +#[doc = "IN_LINK1_CH (rw) register accessor: Link descriptor configure and control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link1_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link1_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link1_ch`] module"] +pub type IN_LINK1_CH = crate::Reg; +#[doc = "Link descriptor configure and control register of Rx channel 0"] +pub mod in_link1_ch; +#[doc = "IN_LINK2_CH (rw) register accessor: Link descriptor configure and control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link2_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link2_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link2_ch`] module"] +pub type IN_LINK2_CH = crate::Reg; +#[doc = "Link descriptor configure and control register of Rx channel 0"] +pub mod in_link2_ch; +#[doc = "IN_STATE_CH (r) register accessor: Receive status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_state_ch`] module"] +pub type IN_STATE_CH = crate::Reg; +#[doc = "Receive status of Rx channel 0"] +pub mod in_state_ch; +#[doc = "IN_SUC_EOF_DES_ADDR_CH (r) register accessor: Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_suc_eof_des_addr_ch`] module"] +pub type IN_SUC_EOF_DES_ADDR_CH = crate::Reg; +#[doc = "Inlink descriptor address when EOF occurs of Rx channel 0"] +pub mod in_suc_eof_des_addr_ch; +#[doc = "IN_ERR_EOF_DES_ADDR_CH (r) register accessor: Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_err_eof_des_addr_ch`] module"] +pub type IN_ERR_EOF_DES_ADDR_CH = crate::Reg; +#[doc = "Inlink descriptor address when errors occur of Rx channel 0"] +pub mod in_err_eof_des_addr_ch; +#[doc = "IN_DSCR_CH (r) register accessor: Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_ch`] module"] +pub type IN_DSCR_CH = crate::Reg; +#[doc = "Current inlink descriptor address of Rx channel 0"] +pub mod in_dscr_ch; +#[doc = "IN_DSCR_BF0_CH (r) register accessor: The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf0_ch`] module"] +pub type IN_DSCR_BF0_CH = crate::Reg; +#[doc = "The last inlink descriptor address of Rx channel 0"] +pub mod in_dscr_bf0_ch; +#[doc = "IN_DSCR_BF1_CH (r) register accessor: The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf1_ch`] module"] +pub type IN_DSCR_BF1_CH = crate::Reg; +#[doc = "The second-to-last inlink descriptor address of Rx channel 0"] +pub mod in_dscr_bf1_ch; +#[doc = "IN_PRI_CH (rw) register accessor: Priority register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pri_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pri_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pri_ch`] module"] +pub type IN_PRI_CH = crate::Reg; +#[doc = "Priority register of Rx channel 0"] +pub mod in_pri_ch; +#[doc = "IN_PERI_SEL_CH (rw) register accessor: Peripheral selection of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_peri_sel_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_peri_sel_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_peri_sel_ch`] module"] +pub type IN_PERI_SEL_CH = crate::Reg; +#[doc = "Peripheral selection of Rx channel 0"] +pub mod in_peri_sel_ch; +#[doc = "IN_CRC_INIT_DATA_CH (rw) register accessor: This register is used to config ch0 crc initial data(max 32 bit)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_init_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_crc_init_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_crc_init_data_ch`] module"] +pub type IN_CRC_INIT_DATA_CH = crate::Reg; +#[doc = "This register is used to config ch0 crc initial data(max 32 bit)"] +pub mod in_crc_init_data_ch; +#[doc = "RX_CRC_WIDTH_CH (rw) register accessor: This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_width_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_width_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_crc_width_ch`] module"] +pub type RX_CRC_WIDTH_CH = crate::Reg; +#[doc = "This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32"] +pub mod rx_crc_width_ch; +#[doc = "IN_CRC_CLEAR_CH (rw) register accessor: This register is used to clear ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_clear_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_crc_clear_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_crc_clear_ch`] module"] +pub type IN_CRC_CLEAR_CH = crate::Reg; +#[doc = "This register is used to clear ch0 crc result"] +pub mod in_crc_clear_ch; +#[doc = "IN_CRC_FINAL_RESULT_CH (r) register accessor: This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_final_result_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_crc_final_result_ch`] module"] +pub type IN_CRC_FINAL_RESULT_CH = crate::Reg; +#[doc = "This register is used to store ch0 crc result"] +pub mod in_crc_final_result_ch; +#[doc = "RX_CRC_EN_WR_DATA_CH (rw) register accessor: This resister is used to config ch0 crc en for every bit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_en_wr_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_en_wr_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_crc_en_wr_data_ch`] module"] +pub type RX_CRC_EN_WR_DATA_CH = crate::Reg; +#[doc = "This resister is used to config ch0 crc en for every bit"] +pub mod rx_crc_en_wr_data_ch; +#[doc = "RX_CRC_EN_ADDR_CH (rw) register accessor: This register is used to config ch0 crc en addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_en_addr_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_en_addr_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_crc_en_addr_ch`] module"] +pub type RX_CRC_EN_ADDR_CH = crate::Reg; +#[doc = "This register is used to config ch0 crc en addr"] +pub mod rx_crc_en_addr_ch; +#[doc = "RX_CRC_DATA_EN_WR_DATA_CH (rw) register accessor: This register is used to config crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_data_en_wr_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_data_en_wr_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_crc_data_en_wr_data_ch`] module"] +pub type RX_CRC_DATA_EN_WR_DATA_CH = + crate::Reg; +#[doc = "This register is used to config crc data_8bit en"] +pub mod rx_crc_data_en_wr_data_ch; +#[doc = "RX_CRC_DATA_EN_ADDR_CH (rw) register accessor: This register is used to config addr of crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_data_en_addr_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_data_en_addr_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_crc_data_en_addr_ch`] module"] +pub type RX_CRC_DATA_EN_ADDR_CH = crate::Reg; +#[doc = "This register is used to config addr of crc data_8bit en"] +pub mod rx_crc_data_en_addr_ch; +#[doc = "OUT_INT_RAW_CH (rw) register accessor: Raw status interrupt of channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_raw_ch`] module"] +pub type OUT_INT_RAW_CH = crate::Reg; +#[doc = "Raw status interrupt of channel0"] +pub mod out_int_raw_ch; +#[doc = "OUT_INT_ST_CH (r) register accessor: Masked interrupt of channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_st_ch`] module"] +pub type OUT_INT_ST_CH = crate::Reg; +#[doc = "Masked interrupt of channel0"] +pub mod out_int_st_ch; +#[doc = "OUT_INT_ENA_CH (rw) register accessor: Interrupt enable bits of channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_ena_ch`] module"] +pub type OUT_INT_ENA_CH = crate::Reg; +#[doc = "Interrupt enable bits of channel0"] +pub mod out_int_ena_ch; +#[doc = "OUT_INT_CLR_CH (w) register accessor: Interrupt clear bits of channel0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_clr_ch`] module"] +pub type OUT_INT_CLR_CH = crate::Reg; +#[doc = "Interrupt clear bits of channel0"] +pub mod out_int_clr_ch; +#[doc = "OUT_CONF0_CH0 (rw) register accessor: Configure 0 register of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0_ch0`] module"] +pub type OUT_CONF0_CH0 = crate::Reg; +#[doc = "Configure 0 register of Tx channel0"] +pub mod out_conf0_ch0; +#[doc = "OUT_CONF1_CH (rw) register accessor: Configure 1 register of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf1_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf1_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf1_ch`] module"] +pub type OUT_CONF1_CH = crate::Reg; +#[doc = "Configure 1 register of Tx channel0"] +pub mod out_conf1_ch; +#[doc = "OUTFIFO_STATUS_CH (r) register accessor: Transmit FIFO status of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outfifo_status_ch`] module"] +pub type OUTFIFO_STATUS_CH = crate::Reg; +#[doc = "Transmit FIFO status of Tx channel0"] +pub mod outfifo_status_ch; +#[doc = "OUT_PUSH_CH (rw) register accessor: Push control register of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_ch`] module"] +pub type OUT_PUSH_CH = crate::Reg; +#[doc = "Push control register of Tx channel0"] +pub mod out_push_ch; +#[doc = "OUT_LINK1_CH (rw) register accessor: Link descriptor configure and control register of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link1_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link1_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link1_ch`] module"] +pub type OUT_LINK1_CH = crate::Reg; +#[doc = "Link descriptor configure and control register of Tx channel0"] +pub mod out_link1_ch; +#[doc = "OUT_LINK2_CH (rw) register accessor: Link descriptor configure and control register of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link2_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link2_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link2_ch`] module"] +pub type OUT_LINK2_CH = crate::Reg; +#[doc = "Link descriptor configure and control register of Tx channel0"] +pub mod out_link2_ch; +#[doc = "OUT_STATE_CH (r) register accessor: Transmit status of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_state_ch`] module"] +pub type OUT_STATE_CH = crate::Reg; +#[doc = "Transmit status of Tx channel0"] +pub mod out_state_ch; +#[doc = "OUT_EOF_DES_ADDR_CH (r) register accessor: Outlink descriptor address when EOF occurs of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr_ch`] module"] +pub type OUT_EOF_DES_ADDR_CH = crate::Reg; +#[doc = "Outlink descriptor address when EOF occurs of Tx channel0"] +pub mod out_eof_des_addr_ch; +#[doc = "OUT_EOF_BFR_DES_ADDR_CH (r) register accessor: The last outlink descriptor address when EOF occurs of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_bfr_des_addr_ch`] module"] +pub type OUT_EOF_BFR_DES_ADDR_CH = + crate::Reg; +#[doc = "The last outlink descriptor address when EOF occurs of Tx channel0"] +pub mod out_eof_bfr_des_addr_ch; +#[doc = "OUT_DSCR_CH (r) register accessor: Current outlink descriptor address of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_ch`] module"] +pub type OUT_DSCR_CH = crate::Reg; +#[doc = "Current outlink descriptor address of Tx channel0"] +pub mod out_dscr_ch; +#[doc = "OUT_DSCR_BF0_CH (r) register accessor: The last outlink descriptor address of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf0_ch`] module"] +pub type OUT_DSCR_BF0_CH = crate::Reg; +#[doc = "The last outlink descriptor address of Tx channel0"] +pub mod out_dscr_bf0_ch; +#[doc = "OUT_DSCR_BF1_CH (r) register accessor: The second-to-last outlink descriptor address of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf1_ch`] module"] +pub type OUT_DSCR_BF1_CH = crate::Reg; +#[doc = "The second-to-last outlink descriptor address of Tx channel0"] +pub mod out_dscr_bf1_ch; +#[doc = "OUT_PRI_CH (rw) register accessor: Priority register of Tx channel0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_pri_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_pri_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_pri_ch`] module"] +pub type OUT_PRI_CH = crate::Reg; +#[doc = "Priority register of Tx channel0."] +pub mod out_pri_ch; +#[doc = "OUT_PERI_SEL_CH (rw) register accessor: Peripheral selection of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_peri_sel_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_peri_sel_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_peri_sel_ch`] module"] +pub type OUT_PERI_SEL_CH = crate::Reg; +#[doc = "Peripheral selection of Tx channel0"] +pub mod out_peri_sel_ch; +#[doc = "OUT_CRC_INIT_DATA_CH (rw) register accessor: This register is used to config ch0 crc initial data(max 32 bit)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_init_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_crc_init_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_crc_init_data_ch`] module"] +pub type OUT_CRC_INIT_DATA_CH = crate::Reg; +#[doc = "This register is used to config ch0 crc initial data(max 32 bit)"] +pub mod out_crc_init_data_ch; +#[doc = "TX_CRC_WIDTH_CH (rw) register accessor: This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_width_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_width_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc_width_ch`] module"] +pub type TX_CRC_WIDTH_CH = crate::Reg; +#[doc = "This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32"] +pub mod tx_crc_width_ch; +#[doc = "OUT_CRC_CLEAR_CH (rw) register accessor: This register is used to clear ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_clear_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_crc_clear_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_crc_clear_ch`] module"] +pub type OUT_CRC_CLEAR_CH = crate::Reg; +#[doc = "This register is used to clear ch0 crc result"] +pub mod out_crc_clear_ch; +#[doc = "OUT_CRC_FINAL_RESULT_CH (r) register accessor: This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_final_result_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_crc_final_result_ch`] module"] +pub type OUT_CRC_FINAL_RESULT_CH = + crate::Reg; +#[doc = "This register is used to store ch0 crc result"] +pub mod out_crc_final_result_ch; +#[doc = "TX_CRC_EN_WR_DATA_CH (rw) register accessor: This resister is used to config ch0 crc en for every bit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_en_wr_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_en_wr_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc_en_wr_data_ch`] module"] +pub type TX_CRC_EN_WR_DATA_CH = crate::Reg; +#[doc = "This resister is used to config ch0 crc en for every bit"] +pub mod tx_crc_en_wr_data_ch; +#[doc = "TX_CRC_EN_ADDR_CH (rw) register accessor: This register is used to config ch0 crc en addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_en_addr_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_en_addr_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc_en_addr_ch`] module"] +pub type TX_CRC_EN_ADDR_CH = crate::Reg; +#[doc = "This register is used to config ch0 crc en addr"] +pub mod tx_crc_en_addr_ch; +#[doc = "TX_CRC_DATA_EN_WR_DATA_CH (rw) register accessor: This register is used to config crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_data_en_wr_data_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_data_en_wr_data_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc_data_en_wr_data_ch`] module"] +pub type TX_CRC_DATA_EN_WR_DATA_CH = + crate::Reg; +#[doc = "This register is used to config crc data_8bit en"] +pub mod tx_crc_data_en_wr_data_ch; +#[doc = "TX_CRC_DATA_EN_ADDR_CH (rw) register accessor: This register is used to config addr of crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_data_en_addr_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_data_en_addr_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc_data_en_addr_ch`] module"] +pub type TX_CRC_DATA_EN_ADDR_CH = crate::Reg; +#[doc = "This register is used to config addr of crc data_8bit en"] +pub mod tx_crc_data_en_addr_ch; +#[doc = "OUT_CONF0_CH1 (rw) register accessor: Configure 0 register of Tx channel1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0_ch1`] module"] +pub type OUT_CONF0_CH1 = crate::Reg; +#[doc = "Configure 0 register of Tx channel1"] +pub mod out_conf0_ch1; +#[doc = "OUT_CONF0_CH2 (rw) register accessor: Configure 0 register of Tx channel2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0_ch2`] module"] +pub type OUT_CONF0_CH2 = crate::Reg; +#[doc = "Configure 0 register of Tx channel2"] +pub mod out_conf0_ch2; +#[doc = "ARB_TIMEOUT (rw) register accessor: This retister is used to config arbiter time slice\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arb_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arb_timeout`] module"] +pub type ARB_TIMEOUT = crate::Reg; +#[doc = "This retister is used to config arbiter time slice"] +pub mod arb_timeout; +#[doc = "WEIGHT_EN (rw) register accessor: This register is used to config arbiter weight function to on or off\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`weight_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`weight_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@weight_en`] module"] +pub type WEIGHT_EN = crate::Reg; +#[doc = "This register is used to config arbiter weight function to on or off"] +pub mod weight_en; +#[doc = "IN_MEM_CONF (rw) register accessor: Mem power configure register of Rx channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_mem_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_mem_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_mem_conf`] module"] +pub type IN_MEM_CONF = crate::Reg; +#[doc = "Mem power configure register of Rx channel"] +pub mod in_mem_conf; +#[doc = "INTR_MEM_START_ADDR (rw) register accessor: The start address of accessible address space.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mem_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mem_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mem_start_addr`] module"] +pub type INTR_MEM_START_ADDR = crate::Reg; +#[doc = "The start address of accessible address space."] +pub mod intr_mem_start_addr; +#[doc = "INTR_MEM_END_ADDR (rw) register accessor: The end address of accessible address space. The access address beyond this range would lead to descriptor error.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mem_end_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mem_end_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_mem_end_addr`] module"] +pub type INTR_MEM_END_ADDR = crate::Reg; +#[doc = "The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub mod intr_mem_end_addr; +#[doc = "EXTR_MEM_START_ADDR (rw) register accessor: The start address of accessible address space.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extr_mem_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extr_mem_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extr_mem_start_addr`] module"] +pub type EXTR_MEM_START_ADDR = crate::Reg; +#[doc = "The start address of accessible address space."] +pub mod extr_mem_start_addr; +#[doc = "EXTR_MEM_END_ADDR (rw) register accessor: The end address of accessible address space. The access address beyond this range would lead to descriptor error.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extr_mem_end_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extr_mem_end_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extr_mem_end_addr`] module"] +pub type EXTR_MEM_END_ADDR = crate::Reg; +#[doc = "The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub mod extr_mem_end_addr; +#[doc = "IN_RESET_AVAIL_CH (r) register accessor: The rx channel 0 reset valid_flag register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_reset_avail_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_reset_avail_ch`] module"] +pub type IN_RESET_AVAIL_CH = crate::Reg; +#[doc = "The rx channel 0 reset valid_flag register."] +pub mod in_reset_avail_ch; +#[doc = "OUT_RESET_AVAIL_CH (r) register accessor: The tx channel 0 reset valid_flag register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_reset_avail_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_reset_avail_ch`] module"] +pub type OUT_RESET_AVAIL_CH = crate::Reg; +#[doc = "The tx channel 0 reset valid_flag register."] +pub mod out_reset_avail_ch; +#[doc = "MISC_CONF (rw) register accessor: MISC register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`misc_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`misc_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc_conf`] module"] +pub type MISC_CONF = crate::Reg; +#[doc = "MISC register"] +pub mod misc_conf; +#[doc = "RDN_RESULT (rw) register accessor: reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_result::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_result::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_result`] module"] +pub type RDN_RESULT = crate::Reg; +#[doc = "reserved"] +pub mod rdn_result; +#[doc = "RDN_ECO_HIGH (rw) register accessor: reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_high`] module"] +pub type RDN_ECO_HIGH = crate::Reg; +#[doc = "reserved"] +pub mod rdn_eco_high; +#[doc = "RDN_ECO_LOW (rw) register accessor: reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_low`] module"] +pub type RDN_ECO_LOW = crate::Reg; +#[doc = "reserved"] +pub mod rdn_eco_low; +#[doc = "WRESP_CNT (r) register accessor: AXI wr responce cnt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wresp_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wresp_cnt`] module"] +pub type WRESP_CNT = crate::Reg; +#[doc = "AXI wr responce cnt register."] +pub mod wresp_cnt; +#[doc = "RRESP_CNT (r) register accessor: AXI wr responce cnt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rresp_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rresp_cnt`] module"] +pub type RRESP_CNT = crate::Reg; +#[doc = "AXI wr responce cnt register."] +pub mod rresp_cnt; +#[doc = "INFIFO_STATUS1_CH (r) register accessor: Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status1_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@infifo_status1_ch`] module"] +pub type INFIFO_STATUS1_CH = crate::Reg; +#[doc = "Receive FIFO status of Rx channel 0"] +pub mod infifo_status1_ch; +#[doc = "OUTFIFO_STATUS1_CH (r) register accessor: Receive FIFO status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status1_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outfifo_status1_ch`] module"] +pub type OUTFIFO_STATUS1_CH = crate::Reg; +#[doc = "Receive FIFO status of Tx channel 0"] +pub mod outfifo_status1_ch; +#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version control register"] +pub mod date; diff --git a/esp32p4/src/axi_dma/arb_timeout.rs b/esp32p4/src/axi_dma/arb_timeout.rs new file mode 100644 index 0000000000..2b8c5cff54 --- /dev/null +++ b/esp32p4/src/axi_dma/arb_timeout.rs @@ -0,0 +1,79 @@ +#[doc = "Register `ARB_TIMEOUT` reader"] +pub type R = crate::R; +#[doc = "Register `ARB_TIMEOUT` writer"] +pub type W = crate::W; +#[doc = "Field `TX` reader - This register is used to config tx arbiter time out value"] +pub type TX_R = crate::FieldReader; +#[doc = "Field `TX` writer - This register is used to config tx arbiter time out value"] +pub type TX_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `RX` reader - This register is used to config rx arbiter time out value"] +pub type RX_R = crate::FieldReader; +#[doc = "Field `RX` writer - This register is used to config rx arbiter time out value"] +pub type RX_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to config tx arbiter time out value"] + #[inline(always)] + pub fn tx(&self) -> TX_R { + TX_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - This register is used to config rx arbiter time out value"] + #[inline(always)] + pub fn rx(&self) -> RX_R { + RX_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARB_TIMEOUT") + .field("tx", &format_args!("{}", self.tx().bits())) + .field("rx", &format_args!("{}", self.rx().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to config tx arbiter time out value"] + #[inline(always)] + #[must_use] + pub fn tx(&mut self) -> TX_W { + TX_W::new(self, 0) + } + #[doc = "Bits 16:31 - This register is used to config rx arbiter time out value"] + #[inline(always)] + #[must_use] + pub fn rx(&mut self) -> RX_W { + RX_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This retister is used to config arbiter time slice\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_timeout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`arb_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ARB_TIMEOUT_SPEC; +impl crate::RegisterSpec for ARB_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`arb_timeout::R`](R) reader structure"] +impl crate::Readable for ARB_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`arb_timeout::W`](W) writer structure"] +impl crate::Writable for ARB_TIMEOUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ARB_TIMEOUT to value 0"] +impl crate::Resettable for ARB_TIMEOUT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/date.rs b/esp32p4/src/axi_dma/date.rs new file mode 100644 index 0000000000..f49507d763 --- /dev/null +++ b/esp32p4/src/axi_dma/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - register version."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - register version."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - register version."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - register version."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_3140"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_3140; +} diff --git a/esp32p4/src/axi_dma/extr_mem_end_addr.rs b/esp32p4/src/axi_dma/extr_mem_end_addr.rs new file mode 100644 index 0000000000..e2d35b3332 --- /dev/null +++ b/esp32p4/src/axi_dma/extr_mem_end_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `EXTR_MEM_END_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `EXTR_MEM_END_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_EXTR_MEM_END_ADDR` reader - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_EXTR_MEM_END_ADDR_R = crate::FieldReader; +#[doc = "Field `ACCESS_EXTR_MEM_END_ADDR` writer - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_EXTR_MEM_END_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + pub fn access_extr_mem_end_addr(&self) -> ACCESS_EXTR_MEM_END_ADDR_R { + ACCESS_EXTR_MEM_END_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXTR_MEM_END_ADDR") + .field( + "access_extr_mem_end_addr", + &format_args!("{}", self.access_extr_mem_end_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + #[must_use] + pub fn access_extr_mem_end_addr( + &mut self, + ) -> ACCESS_EXTR_MEM_END_ADDR_W { + ACCESS_EXTR_MEM_END_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The end address of accessible address space. The access address beyond this range would lead to descriptor error.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extr_mem_end_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extr_mem_end_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXTR_MEM_END_ADDR_SPEC; +impl crate::RegisterSpec for EXTR_MEM_END_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`extr_mem_end_addr::R`](R) reader structure"] +impl crate::Readable for EXTR_MEM_END_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`extr_mem_end_addr::W`](W) writer structure"] +impl crate::Writable for EXTR_MEM_END_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXTR_MEM_END_ADDR to value 0x8fff_ffff"] +impl crate::Resettable for EXTR_MEM_END_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0x8fff_ffff; +} diff --git a/esp32p4/src/axi_dma/extr_mem_start_addr.rs b/esp32p4/src/axi_dma/extr_mem_start_addr.rs new file mode 100644 index 0000000000..17e6d85429 --- /dev/null +++ b/esp32p4/src/axi_dma/extr_mem_start_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `EXTR_MEM_START_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `EXTR_MEM_START_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_EXTR_MEM_START_ADDR` reader - The start address of accessible address space."] +pub type ACCESS_EXTR_MEM_START_ADDR_R = crate::FieldReader; +#[doc = "Field `ACCESS_EXTR_MEM_START_ADDR` writer - The start address of accessible address space."] +pub type ACCESS_EXTR_MEM_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + pub fn access_extr_mem_start_addr(&self) -> ACCESS_EXTR_MEM_START_ADDR_R { + ACCESS_EXTR_MEM_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXTR_MEM_START_ADDR") + .field( + "access_extr_mem_start_addr", + &format_args!("{}", self.access_extr_mem_start_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + #[must_use] + pub fn access_extr_mem_start_addr( + &mut self, + ) -> ACCESS_EXTR_MEM_START_ADDR_W { + ACCESS_EXTR_MEM_START_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The start address of accessible address space.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extr_mem_start_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`extr_mem_start_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXTR_MEM_START_ADDR_SPEC; +impl crate::RegisterSpec for EXTR_MEM_START_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`extr_mem_start_addr::R`](R) reader structure"] +impl crate::Readable for EXTR_MEM_START_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`extr_mem_start_addr::W`](W) writer structure"] +impl crate::Writable for EXTR_MEM_START_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXTR_MEM_START_ADDR to value 0x3010_0000"] +impl crate::Resettable for EXTR_MEM_START_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0x3010_0000; +} diff --git a/esp32p4/src/axi_dma/in_conf0_ch.rs b/esp32p4/src/axi_dma/in_conf0_ch.rs new file mode 100644 index 0000000000..5ce5496c48 --- /dev/null +++ b/esp32p4/src/axi_dma/in_conf0_ch.rs @@ -0,0 +1,196 @@ +#[doc = "Register `IN_CONF0_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF0_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_RST_CH` reader - This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_CH_R = crate::BitReader; +#[doc = "Field `IN_RST_CH` writer - This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer."] +pub type IN_RST_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_LOOP_TEST_CH` reader - reserved"] +pub type IN_LOOP_TEST_CH_R = crate::BitReader; +#[doc = "Field `IN_LOOP_TEST_CH` writer - reserved"] +pub type IN_LOOP_TEST_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_TRANS_EN_CH` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via AXI_DMA."] +pub type MEM_TRANS_EN_CH_R = crate::BitReader; +#[doc = "Field `MEM_TRANS_EN_CH` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via AXI_DMA."] +pub type MEM_TRANS_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ETM_EN_CH` reader - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."] +pub type IN_ETM_EN_CH_R = crate::BitReader; +#[doc = "Field `IN_ETM_EN_CH` writer - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."] +pub type IN_ETM_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_BURST_SIZE_SEL_CH` reader - 3'b000-3'b100:burst length 8byte~128byte"] +pub type IN_BURST_SIZE_SEL_CH_R = crate::FieldReader; +#[doc = "Field `IN_BURST_SIZE_SEL_CH` writer - 3'b000-3'b100:burst length 8byte~128byte"] +pub type IN_BURST_SIZE_SEL_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IN_CMD_DISABLE_CH` reader - 1:mean disable cmd of this ch0"] +pub type IN_CMD_DISABLE_CH_R = crate::BitReader; +#[doc = "Field `IN_CMD_DISABLE_CH` writer - 1:mean disable cmd of this ch0"] +pub type IN_CMD_DISABLE_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ECC_AEC_EN_CH` reader - 1: mean access ecc or aes domain,0: mean not"] +pub type IN_ECC_AEC_EN_CH_R = crate::BitReader; +#[doc = "Field `IN_ECC_AEC_EN_CH` writer - 1: mean access ecc or aes domain,0: mean not"] +pub type IN_ECC_AEC_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INDSCR_BURST_EN_CH` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_CH_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN_CH` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] +pub type INDSCR_BURST_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer."] + #[inline(always)] + pub fn in_rst_ch(&self) -> IN_RST_CH_R { + IN_RST_CH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + pub fn in_loop_test_ch(&self) -> IN_LOOP_TEST_CH_R { + IN_LOOP_TEST_CH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit 1 to enable automatic transmitting data from memory to memory via AXI_DMA."] + #[inline(always)] + pub fn mem_trans_en_ch(&self) -> MEM_TRANS_EN_CH_R { + MEM_TRANS_EN_CH_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."] + #[inline(always)] + pub fn in_etm_en_ch(&self) -> IN_ETM_EN_CH_R { + IN_ETM_EN_CH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - 3'b000-3'b100:burst length 8byte~128byte"] + #[inline(always)] + pub fn in_burst_size_sel_ch(&self) -> IN_BURST_SIZE_SEL_CH_R { + IN_BURST_SIZE_SEL_CH_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - 1:mean disable cmd of this ch0"] + #[inline(always)] + pub fn in_cmd_disable_ch(&self) -> IN_CMD_DISABLE_CH_R { + IN_CMD_DISABLE_CH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - 1: mean access ecc or aes domain,0: mean not"] + #[inline(always)] + pub fn in_ecc_aec_en_ch(&self) -> IN_ECC_AEC_EN_CH_R { + IN_ECC_AEC_EN_CH_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn indscr_burst_en_ch(&self) -> INDSCR_BURST_EN_CH_R { + INDSCR_BURST_EN_CH_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF0_CH") + .field("in_rst_ch", &format_args!("{}", self.in_rst_ch().bit())) + .field( + "in_loop_test_ch", + &format_args!("{}", self.in_loop_test_ch().bit()), + ) + .field( + "mem_trans_en_ch", + &format_args!("{}", self.mem_trans_en_ch().bit()), + ) + .field( + "in_etm_en_ch", + &format_args!("{}", self.in_etm_en_ch().bit()), + ) + .field( + "in_burst_size_sel_ch", + &format_args!("{}", self.in_burst_size_sel_ch().bits()), + ) + .field( + "in_cmd_disable_ch", + &format_args!("{}", self.in_cmd_disable_ch().bit()), + ) + .field( + "in_ecc_aec_en_ch", + &format_args!("{}", self.in_ecc_aec_en_ch().bit()), + ) + .field( + "indscr_burst_en_ch", + &format_args!("{}", self.indscr_burst_en_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer."] + #[inline(always)] + #[must_use] + pub fn in_rst_ch(&mut self) -> IN_RST_CH_W { + IN_RST_CH_W::new(self, 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + #[must_use] + pub fn in_loop_test_ch(&mut self) -> IN_LOOP_TEST_CH_W { + IN_LOOP_TEST_CH_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit 1 to enable automatic transmitting data from memory to memory via AXI_DMA."] + #[inline(always)] + #[must_use] + pub fn mem_trans_en_ch(&mut self) -> MEM_TRANS_EN_CH_W { + MEM_TRANS_EN_CH_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task."] + #[inline(always)] + #[must_use] + pub fn in_etm_en_ch(&mut self) -> IN_ETM_EN_CH_W { + IN_ETM_EN_CH_W::new(self, 3) + } + #[doc = "Bits 4:6 - 3'b000-3'b100:burst length 8byte~128byte"] + #[inline(always)] + #[must_use] + pub fn in_burst_size_sel_ch(&mut self) -> IN_BURST_SIZE_SEL_CH_W { + IN_BURST_SIZE_SEL_CH_W::new(self, 4) + } + #[doc = "Bit 7 - 1:mean disable cmd of this ch0"] + #[inline(always)] + #[must_use] + pub fn in_cmd_disable_ch(&mut self) -> IN_CMD_DISABLE_CH_W { + IN_CMD_DISABLE_CH_W::new(self, 7) + } + #[doc = "Bit 8 - 1: mean access ecc or aes domain,0: mean not"] + #[inline(always)] + #[must_use] + pub fn in_ecc_aec_en_ch(&mut self) -> IN_ECC_AEC_EN_CH_W { + IN_ECC_AEC_EN_CH_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn indscr_burst_en_ch(&mut self) -> INDSCR_BURST_EN_CH_W { + INDSCR_BURST_EN_CH_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure 0 register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF0_CH_SPEC; +impl crate::RegisterSpec for IN_CONF0_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf0_ch::R`](R) reader structure"] +impl crate::Readable for IN_CONF0_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf0_ch::W`](W) writer structure"] +impl crate::Writable for IN_CONF0_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF0_CH%s to value 0"] +impl crate::Resettable for IN_CONF0_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_conf1_ch.rs b/esp32p4/src/axi_dma/in_conf1_ch.rs new file mode 100644 index 0000000000..b8ad457fd6 --- /dev/null +++ b/esp32p4/src/axi_dma/in_conf1_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_CONF1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF1_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_CHECK_OWNER_CH` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER_CH` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn in_check_owner_ch(&self) -> IN_CHECK_OWNER_CH_R { + IN_CHECK_OWNER_CH_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF1_CH") + .field( + "in_check_owner_ch", + &format_args!("{}", self.in_check_owner_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn in_check_owner_ch(&mut self) -> IN_CHECK_OWNER_CH_W { + IN_CHECK_OWNER_CH_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure 1 register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf1_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf1_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF1_CH_SPEC; +impl crate::RegisterSpec for IN_CONF1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf1_ch::R`](R) reader structure"] +impl crate::Readable for IN_CONF1_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf1_ch::W`](W) writer structure"] +impl crate::Writable for IN_CONF1_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF1_CH%s to value 0"] +impl crate::Resettable for IN_CONF1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_crc_clear_ch.rs b/esp32p4/src/axi_dma/in_crc_clear_ch.rs new file mode 100644 index 0000000000..b1495d4987 --- /dev/null +++ b/esp32p4/src/axi_dma/in_crc_clear_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_CRC_CLEAR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CRC_CLEAR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_CRC_CLEAR_CH` reader - This register is used to clear ch0 of rx crc result"] +pub type IN_CRC_CLEAR_CH_R = crate::BitReader; +#[doc = "Field `IN_CRC_CLEAR_CH` writer - This register is used to clear ch0 of rx crc result"] +pub type IN_CRC_CLEAR_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This register is used to clear ch0 of rx crc result"] + #[inline(always)] + pub fn in_crc_clear_ch(&self) -> IN_CRC_CLEAR_CH_R { + IN_CRC_CLEAR_CH_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CRC_CLEAR_CH") + .field( + "in_crc_clear_ch", + &format_args!("{}", self.in_crc_clear_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This register is used to clear ch0 of rx crc result"] + #[inline(always)] + #[must_use] + pub fn in_crc_clear_ch(&mut self) -> IN_CRC_CLEAR_CH_W { + IN_CRC_CLEAR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to clear ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_clear_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_crc_clear_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CRC_CLEAR_CH_SPEC; +impl crate::RegisterSpec for IN_CRC_CLEAR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_crc_clear_ch::R`](R) reader structure"] +impl crate::Readable for IN_CRC_CLEAR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_crc_clear_ch::W`](W) writer structure"] +impl crate::Writable for IN_CRC_CLEAR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CRC_CLEAR_CH%s to value 0"] +impl crate::Resettable for IN_CRC_CLEAR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_crc_final_result_ch.rs b/esp32p4/src/axi_dma/in_crc_final_result_ch.rs new file mode 100644 index 0000000000..0c882874f2 --- /dev/null +++ b/esp32p4/src/axi_dma/in_crc_final_result_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_CRC_FINAL_RESULT_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CRC_FINAL_RESULT_CH` reader - This register is used to store result ch0 of rx"] +pub type IN_CRC_FINAL_RESULT_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register is used to store result ch0 of rx"] + #[inline(always)] + pub fn in_crc_final_result_ch(&self) -> IN_CRC_FINAL_RESULT_CH_R { + IN_CRC_FINAL_RESULT_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CRC_FINAL_RESULT_CH") + .field( + "in_crc_final_result_ch", + &format_args!("{}", self.in_crc_final_result_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_final_result_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CRC_FINAL_RESULT_CH_SPEC; +impl crate::RegisterSpec for IN_CRC_FINAL_RESULT_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_crc_final_result_ch::R`](R) reader structure"] +impl crate::Readable for IN_CRC_FINAL_RESULT_CH_SPEC {} +#[doc = "`reset()` method sets IN_CRC_FINAL_RESULT_CH%s to value 0"] +impl crate::Resettable for IN_CRC_FINAL_RESULT_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_crc_init_data_ch.rs b/esp32p4/src/axi_dma/in_crc_init_data_ch.rs new file mode 100644 index 0000000000..4d9e32f0a0 --- /dev/null +++ b/esp32p4/src/axi_dma/in_crc_init_data_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_CRC_INIT_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CRC_INIT_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_CRC_INIT_DATA_CH` reader - This register is used to config ch0 of rx crc initial value"] +pub type IN_CRC_INIT_DATA_CH_R = crate::FieldReader; +#[doc = "Field `IN_CRC_INIT_DATA_CH` writer - This register is used to config ch0 of rx crc initial value"] +pub type IN_CRC_INIT_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is used to config ch0 of rx crc initial value"] + #[inline(always)] + pub fn in_crc_init_data_ch(&self) -> IN_CRC_INIT_DATA_CH_R { + IN_CRC_INIT_DATA_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CRC_INIT_DATA_CH") + .field( + "in_crc_init_data_ch", + &format_args!("{}", self.in_crc_init_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register is used to config ch0 of rx crc initial value"] + #[inline(always)] + #[must_use] + pub fn in_crc_init_data_ch(&mut self) -> IN_CRC_INIT_DATA_CH_W { + IN_CRC_INIT_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config ch0 crc initial data(max 32 bit)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_init_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_crc_init_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CRC_INIT_DATA_CH_SPEC; +impl crate::RegisterSpec for IN_CRC_INIT_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_crc_init_data_ch::R`](R) reader structure"] +impl crate::Readable for IN_CRC_INIT_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_crc_init_data_ch::W`](W) writer structure"] +impl crate::Writable for IN_CRC_INIT_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CRC_INIT_DATA_CH%s to value 0xffff_ffff"] +impl crate::Resettable for IN_CRC_INIT_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/axi_dma/in_dscr_bf0_ch.rs b/esp32p4/src/axi_dma/in_dscr_bf0_ch.rs new file mode 100644 index 0000000000..b860c84a76 --- /dev/null +++ b/esp32p4/src/axi_dma/in_dscr_bf0_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF0_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF0_CH` reader - The address of the last inlink descriptor x-1."] +pub type INLINK_DSCR_BF0_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last inlink descriptor x-1."] + #[inline(always)] + pub fn inlink_dscr_bf0_ch(&self) -> INLINK_DSCR_BF0_CH_R { + INLINK_DSCR_BF0_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF0_CH") + .field( + "inlink_dscr_bf0_ch", + &format_args!("{}", self.inlink_dscr_bf0_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF0_CH_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF0_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf0_ch::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF0_CH_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF0_CH%s to value 0"] +impl crate::Resettable for IN_DSCR_BF0_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_dscr_bf1_ch.rs b/esp32p4/src/axi_dma/in_dscr_bf1_ch.rs new file mode 100644 index 0000000000..1db9eea30b --- /dev/null +++ b/esp32p4/src/axi_dma/in_dscr_bf1_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF1_CH` reader - The address of the second-to-last inlink descriptor x-2."] +pub type INLINK_DSCR_BF1_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."] + #[inline(always)] + pub fn inlink_dscr_bf1_ch(&self) -> INLINK_DSCR_BF1_CH_R { + INLINK_DSCR_BF1_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF1_CH") + .field( + "inlink_dscr_bf1_ch", + &format_args!("{}", self.inlink_dscr_bf1_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF1_CH_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf1_ch::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF1_CH_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF1_CH%s to value 0"] +impl crate::Resettable for IN_DSCR_BF1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_dscr_ch.rs b/esp32p4/src/axi_dma/in_dscr_ch.rs new file mode 100644 index 0000000000..1759668e9f --- /dev/null +++ b/esp32p4/src/axi_dma/in_dscr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_CH` reader - The address of the current inlink descriptor x."] +pub type INLINK_DSCR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the current inlink descriptor x."] + #[inline(always)] + pub fn inlink_dscr_ch(&self) -> INLINK_DSCR_CH_R { + INLINK_DSCR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_CH") + .field( + "inlink_dscr_ch", + &format_args!("{}", self.inlink_dscr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_CH_SPEC; +impl crate::RegisterSpec for IN_DSCR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_ch::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_CH_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_CH%s to value 0"] +impl crate::Resettable for IN_DSCR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_err_eof_des_addr_ch.rs b/esp32p4/src/axi_dma/in_err_eof_des_addr_ch.rs new file mode 100644 index 0000000000..aa9a2761b7 --- /dev/null +++ b/esp32p4/src/axi_dma/in_err_eof_des_addr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_ERR_EOF_DES_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] +pub type IN_ERR_EOF_DES_ADDR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."] + #[inline(always)] + pub fn in_err_eof_des_addr_ch(&self) -> IN_ERR_EOF_DES_ADDR_CH_R { + IN_ERR_EOF_DES_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ERR_EOF_DES_ADDR_CH") + .field( + "in_err_eof_des_addr_ch", + &format_args!("{}", self.in_err_eof_des_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ERR_EOF_DES_ADDR_CH_SPEC; +impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_err_eof_des_addr_ch::R`](R) reader structure"] +impl crate::Readable for IN_ERR_EOF_DES_ADDR_CH_SPEC {} +#[doc = "`reset()` method sets IN_ERR_EOF_DES_ADDR_CH%s to value 0"] +impl crate::Resettable for IN_ERR_EOF_DES_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_int_clr_ch.rs b/esp32p4/src/axi_dma/in_int_clr_ch.rs new file mode 100644 index 0000000000..ed01d64dff --- /dev/null +++ b/esp32p4/src/axi_dma/in_int_clr_ch.rs @@ -0,0 +1,122 @@ +#[doc = "Register `IN_INT_CLR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH_INT_CLR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L1_OVF_CH_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_L1_OVF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L1_UDF_CH_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_L1_UDF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L2_OVF_CH_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_L2_OVF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L2_UDF_CH_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_L2_UDF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L3_OVF_CH_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt."] +pub type INFIFO_L3_OVF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L3_UDF_CH_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt."] +pub type INFIFO_L3_UDF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch_int_clr(&mut self) -> IN_DONE_CH_INT_CLR_W { + IN_DONE_CH_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch_int_clr(&mut self) -> IN_SUC_EOF_CH_INT_CLR_W { + IN_SUC_EOF_CH_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch_int_clr(&mut self) -> IN_ERR_EOF_CH_INT_CLR_W { + IN_ERR_EOF_CH_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch_int_clr(&mut self) -> IN_DSCR_ERR_CH_INT_CLR_W { + IN_DSCR_ERR_CH_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch_int_clr(&mut self) -> IN_DSCR_EMPTY_CH_INT_CLR_W { + IN_DSCR_EMPTY_CH_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l1_ovf_ch_int_clr(&mut self) -> INFIFO_L1_OVF_CH_INT_CLR_W { + INFIFO_L1_OVF_CH_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l1_udf_ch_int_clr(&mut self) -> INFIFO_L1_UDF_CH_INT_CLR_W { + INFIFO_L1_UDF_CH_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l2_ovf_ch_int_clr(&mut self) -> INFIFO_L2_OVF_CH_INT_CLR_W { + INFIFO_L2_OVF_CH_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l2_udf_ch_int_clr(&mut self) -> INFIFO_L2_UDF_CH_INT_CLR_W { + INFIFO_L2_UDF_CH_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l3_ovf_ch_int_clr(&mut self) -> INFIFO_L3_OVF_CH_INT_CLR_W { + INFIFO_L3_OVF_CH_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l3_udf_ch_int_clr(&mut self) -> INFIFO_L3_UDF_CH_INT_CLR_W { + INFIFO_L3_UDF_CH_INT_CLR_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear bits of channel 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_CLR_CH_SPEC; +impl crate::RegisterSpec for IN_INT_CLR_CH_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`in_int_clr_ch::W`](W) writer structure"] +impl crate::Writable for IN_INT_CLR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_CLR_CH%s to value 0"] +impl crate::Resettable for IN_INT_CLR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_int_ena_ch.rs b/esp32p4/src/axi_dma/in_int_ena_ch.rs new file mode 100644 index 0000000000..e7d759ccee --- /dev/null +++ b/esp32p4/src/axi_dma/in_int_ena_ch.rs @@ -0,0 +1,256 @@ +#[doc = "Register `IN_INT_ENA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_ENA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L1_OVF_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_L1_OVF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_L1_OVF_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_L1_OVF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L1_UDF_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_L1_UDF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_L1_UDF_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_L1_UDF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L2_OVF_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_L2_OVF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_L2_OVF_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_L2_OVF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L2_UDF_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_L2_UDF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_L2_UDF_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_L2_UDF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L3_OVF_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."] +pub type INFIFO_L3_OVF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_L3_OVF_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."] +pub type INFIFO_L3_OVF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L3_UDF_CH_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."] +pub type INFIFO_L3_UDF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_L3_UDF_CH_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."] +pub type INFIFO_L3_UDF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch_int_ena(&self) -> IN_DONE_CH_INT_ENA_R { + IN_DONE_CH_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch_int_ena(&self) -> IN_SUC_EOF_CH_INT_ENA_R { + IN_SUC_EOF_CH_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch_int_ena(&self) -> IN_ERR_EOF_CH_INT_ENA_R { + IN_ERR_EOF_CH_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch_int_ena(&self) -> IN_DSCR_ERR_CH_INT_ENA_R { + IN_DSCR_ERR_CH_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch_int_ena(&self) -> IN_DSCR_EMPTY_CH_INT_ENA_R { + IN_DSCR_EMPTY_CH_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_l1_ovf_ch_int_ena(&self) -> INFIFO_L1_OVF_CH_INT_ENA_R { + INFIFO_L1_OVF_CH_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_l1_udf_ch_int_ena(&self) -> INFIFO_L1_UDF_CH_INT_ENA_R { + INFIFO_L1_UDF_CH_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_l2_ovf_ch_int_ena(&self) -> INFIFO_L2_OVF_CH_INT_ENA_R { + INFIFO_L2_OVF_CH_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_l2_udf_ch_int_ena(&self) -> INFIFO_L2_UDF_CH_INT_ENA_R { + INFIFO_L2_UDF_CH_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_l3_ovf_ch_int_ena(&self) -> INFIFO_L3_OVF_CH_INT_ENA_R { + INFIFO_L3_OVF_CH_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_l3_udf_ch_int_ena(&self) -> INFIFO_L3_UDF_CH_INT_ENA_R { + INFIFO_L3_UDF_CH_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ENA_CH") + .field( + "in_done_ch_int_ena", + &format_args!("{}", self.in_done_ch_int_ena().bit()), + ) + .field( + "in_suc_eof_ch_int_ena", + &format_args!("{}", self.in_suc_eof_ch_int_ena().bit()), + ) + .field( + "in_err_eof_ch_int_ena", + &format_args!("{}", self.in_err_eof_ch_int_ena().bit()), + ) + .field( + "in_dscr_err_ch_int_ena", + &format_args!("{}", self.in_dscr_err_ch_int_ena().bit()), + ) + .field( + "in_dscr_empty_ch_int_ena", + &format_args!("{}", self.in_dscr_empty_ch_int_ena().bit()), + ) + .field( + "infifo_l1_ovf_ch_int_ena", + &format_args!("{}", self.infifo_l1_ovf_ch_int_ena().bit()), + ) + .field( + "infifo_l1_udf_ch_int_ena", + &format_args!("{}", self.infifo_l1_udf_ch_int_ena().bit()), + ) + .field( + "infifo_l2_ovf_ch_int_ena", + &format_args!("{}", self.infifo_l2_ovf_ch_int_ena().bit()), + ) + .field( + "infifo_l2_udf_ch_int_ena", + &format_args!("{}", self.infifo_l2_udf_ch_int_ena().bit()), + ) + .field( + "infifo_l3_ovf_ch_int_ena", + &format_args!("{}", self.infifo_l3_ovf_ch_int_ena().bit()), + ) + .field( + "infifo_l3_udf_ch_int_ena", + &format_args!("{}", self.infifo_l3_udf_ch_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch_int_ena(&mut self) -> IN_DONE_CH_INT_ENA_W { + IN_DONE_CH_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch_int_ena(&mut self) -> IN_SUC_EOF_CH_INT_ENA_W { + IN_SUC_EOF_CH_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch_int_ena(&mut self) -> IN_ERR_EOF_CH_INT_ENA_W { + IN_ERR_EOF_CH_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch_int_ena(&mut self) -> IN_DSCR_ERR_CH_INT_ENA_W { + IN_DSCR_ERR_CH_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch_int_ena(&mut self) -> IN_DSCR_EMPTY_CH_INT_ENA_W { + IN_DSCR_EMPTY_CH_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l1_ovf_ch_int_ena(&mut self) -> INFIFO_L1_OVF_CH_INT_ENA_W { + INFIFO_L1_OVF_CH_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l1_udf_ch_int_ena(&mut self) -> INFIFO_L1_UDF_CH_INT_ENA_W { + INFIFO_L1_UDF_CH_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l2_ovf_ch_int_ena(&mut self) -> INFIFO_L2_OVF_CH_INT_ENA_W { + INFIFO_L2_OVF_CH_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l2_udf_ch_int_ena(&mut self) -> INFIFO_L2_UDF_CH_INT_ENA_W { + INFIFO_L2_UDF_CH_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l3_ovf_ch_int_ena(&mut self) -> INFIFO_L3_OVF_CH_INT_ENA_W { + INFIFO_L3_OVF_CH_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_l3_udf_ch_int_ena(&mut self) -> INFIFO_L3_UDF_CH_INT_ENA_W { + INFIFO_L3_UDF_CH_INT_ENA_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable bits of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ENA_CH_SPEC; +impl crate::RegisterSpec for IN_INT_ENA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_ena_ch::R`](R) reader structure"] +impl crate::Readable for IN_INT_ENA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_ena_ch::W`](W) writer structure"] +impl crate::Writable for IN_INT_ENA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_ENA_CH%s to value 0"] +impl crate::Resettable for IN_INT_ENA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_int_raw_ch.rs b/esp32p4/src/axi_dma/in_int_raw_ch.rs new file mode 100644 index 0000000000..a0b1b4aa04 --- /dev/null +++ b/esp32p4/src/axi_dma/in_int_raw_ch.rs @@ -0,0 +1,256 @@ +#[doc = "Register `IN_INT_RAW_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_RAW_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] +pub type IN_DONE_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] +pub type IN_DONE_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] +pub type IN_SUC_EOF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] +pub type IN_SUC_EOF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."] +pub type IN_ERR_EOF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH_INT_RAW` writer - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."] +pub type IN_ERR_EOF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."] +pub type IN_DSCR_ERR_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH_INT_RAW` writer - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."] +pub type IN_DSCR_ERR_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_RAW` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."] +pub type IN_DSCR_EMPTY_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_RAW` writer - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."] +pub type IN_DSCR_EMPTY_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L1_OVF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] +pub type INFIFO_L1_OVF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_L1_OVF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] +pub type INFIFO_L1_OVF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L1_UDF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] +pub type INFIFO_L1_UDF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_L1_UDF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] +pub type INFIFO_L1_UDF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L2_OVF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] +pub type INFIFO_L2_OVF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_L2_OVF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] +pub type INFIFO_L2_OVF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L2_UDF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] +pub type INFIFO_L2_UDF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_L2_UDF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] +pub type INFIFO_L2_UDF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L3_OVF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] +pub type INFIFO_L3_OVF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_L3_OVF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] +pub type INFIFO_L3_OVF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_L3_UDF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] +pub type INFIFO_L3_UDF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_L3_UDF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] +pub type INFIFO_L3_UDF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] + #[inline(always)] + pub fn in_done_ch_int_raw(&self) -> IN_DONE_CH_INT_RAW_R { + IN_DONE_CH_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] + #[inline(always)] + pub fn in_suc_eof_ch_int_raw(&self) -> IN_SUC_EOF_CH_INT_RAW_R { + IN_SUC_EOF_CH_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."] + #[inline(always)] + pub fn in_err_eof_ch_int_raw(&self) -> IN_ERR_EOF_CH_INT_RAW_R { + IN_ERR_EOF_CH_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."] + #[inline(always)] + pub fn in_dscr_err_ch_int_raw(&self) -> IN_DSCR_ERR_CH_INT_RAW_R { + IN_DSCR_ERR_CH_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."] + #[inline(always)] + pub fn in_dscr_empty_ch_int_raw(&self) -> IN_DSCR_EMPTY_CH_INT_RAW_R { + IN_DSCR_EMPTY_CH_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] + #[inline(always)] + pub fn infifo_l1_ovf_ch_int_raw(&self) -> INFIFO_L1_OVF_CH_INT_RAW_R { + INFIFO_L1_OVF_CH_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] + #[inline(always)] + pub fn infifo_l1_udf_ch_int_raw(&self) -> INFIFO_L1_UDF_CH_INT_RAW_R { + INFIFO_L1_UDF_CH_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] + #[inline(always)] + pub fn infifo_l2_ovf_ch_int_raw(&self) -> INFIFO_L2_OVF_CH_INT_RAW_R { + INFIFO_L2_OVF_CH_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] + #[inline(always)] + pub fn infifo_l2_udf_ch_int_raw(&self) -> INFIFO_L2_UDF_CH_INT_RAW_R { + INFIFO_L2_UDF_CH_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] + #[inline(always)] + pub fn infifo_l3_ovf_ch_int_raw(&self) -> INFIFO_L3_OVF_CH_INT_RAW_R { + INFIFO_L3_OVF_CH_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] + #[inline(always)] + pub fn infifo_l3_udf_ch_int_raw(&self) -> INFIFO_L3_UDF_CH_INT_RAW_R { + INFIFO_L3_UDF_CH_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_RAW_CH") + .field( + "in_done_ch_int_raw", + &format_args!("{}", self.in_done_ch_int_raw().bit()), + ) + .field( + "in_suc_eof_ch_int_raw", + &format_args!("{}", self.in_suc_eof_ch_int_raw().bit()), + ) + .field( + "in_err_eof_ch_int_raw", + &format_args!("{}", self.in_err_eof_ch_int_raw().bit()), + ) + .field( + "in_dscr_err_ch_int_raw", + &format_args!("{}", self.in_dscr_err_ch_int_raw().bit()), + ) + .field( + "in_dscr_empty_ch_int_raw", + &format_args!("{}", self.in_dscr_empty_ch_int_raw().bit()), + ) + .field( + "infifo_l1_ovf_ch_int_raw", + &format_args!("{}", self.infifo_l1_ovf_ch_int_raw().bit()), + ) + .field( + "infifo_l1_udf_ch_int_raw", + &format_args!("{}", self.infifo_l1_udf_ch_int_raw().bit()), + ) + .field( + "infifo_l2_ovf_ch_int_raw", + &format_args!("{}", self.infifo_l2_ovf_ch_int_raw().bit()), + ) + .field( + "infifo_l2_udf_ch_int_raw", + &format_args!("{}", self.infifo_l2_udf_ch_int_raw().bit()), + ) + .field( + "infifo_l3_ovf_ch_int_raw", + &format_args!("{}", self.infifo_l3_ovf_ch_int_raw().bit()), + ) + .field( + "infifo_l3_udf_ch_int_raw", + &format_args!("{}", self.infifo_l3_udf_ch_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."] + #[inline(always)] + #[must_use] + pub fn in_done_ch_int_raw(&mut self) -> IN_DONE_CH_INT_RAW_W { + IN_DONE_CH_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch_int_raw(&mut self) -> IN_SUC_EOF_CH_INT_RAW_W { + IN_SUC_EOF_CH_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch_int_raw(&mut self) -> IN_ERR_EOF_CH_INT_RAW_W { + IN_ERR_EOF_CH_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch_int_raw(&mut self) -> IN_DSCR_ERR_CH_INT_RAW_W { + IN_DSCR_ERR_CH_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch_int_raw(&mut self) -> IN_DSCR_EMPTY_CH_INT_RAW_W { + IN_DSCR_EMPTY_CH_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_l1_ovf_ch_int_raw(&mut self) -> INFIFO_L1_OVF_CH_INT_RAW_W { + INFIFO_L1_OVF_CH_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_l1_udf_ch_int_raw(&mut self) -> INFIFO_L1_UDF_CH_INT_RAW_W { + INFIFO_L1_UDF_CH_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_l2_ovf_ch_int_raw(&mut self) -> INFIFO_L2_OVF_CH_INT_RAW_W { + INFIFO_L2_OVF_CH_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_l2_udf_ch_int_raw(&mut self) -> INFIFO_L2_UDF_CH_INT_RAW_W { + INFIFO_L2_UDF_CH_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_l3_ovf_ch_int_raw(&mut self) -> INFIFO_L3_OVF_CH_INT_RAW_W { + INFIFO_L3_OVF_CH_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_l3_udf_ch_int_raw(&mut self) -> INFIFO_L3_UDF_CH_INT_RAW_W { + INFIFO_L3_UDF_CH_INT_RAW_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Raw status interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_RAW_CH_SPEC; +impl crate::RegisterSpec for IN_INT_RAW_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_raw_ch::R`](R) reader structure"] +impl crate::Readable for IN_INT_RAW_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_raw_ch::W`](W) writer structure"] +impl crate::Writable for IN_INT_RAW_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_RAW_CH%s to value 0"] +impl crate::Resettable for IN_INT_RAW_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_int_st_ch.rs b/esp32p4/src/axi_dma/in_int_st_ch.rs new file mode 100644 index 0000000000..5e519af757 --- /dev/null +++ b/esp32p4/src/axi_dma/in_int_st_ch.rs @@ -0,0 +1,149 @@ +#[doc = "Register `IN_INT_ST_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE_CH_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_L1_OVF_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_L1_OVF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_L1_UDF_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_L1_UDF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_L3_OVF_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt."] +pub type INFIFO_L3_OVF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_L3_UDF_CH_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt."] +pub type INFIFO_L3_UDF_CH_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch_int_st(&self) -> IN_DONE_CH_INT_ST_R { + IN_DONE_CH_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch_int_st(&self) -> IN_SUC_EOF_CH_INT_ST_R { + IN_SUC_EOF_CH_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch_int_st(&self) -> IN_ERR_EOF_CH_INT_ST_R { + IN_ERR_EOF_CH_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch_int_st(&self) -> IN_DSCR_ERR_CH_INT_ST_R { + IN_DSCR_ERR_CH_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch_int_st(&self) -> IN_DSCR_EMPTY_CH_INT_ST_R { + IN_DSCR_EMPTY_CH_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_ch_int_st(&self) -> INFIFO_OVF_CH_INT_ST_R { + INFIFO_OVF_CH_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_ch_int_st(&self) -> INFIFO_UDF_CH_INT_ST_R { + INFIFO_UDF_CH_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_l1_ovf_ch_int_st(&self) -> INFIFO_L1_OVF_CH_INT_ST_R { + INFIFO_L1_OVF_CH_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_l1_udf_ch_int_st(&self) -> INFIFO_L1_UDF_CH_INT_ST_R { + INFIFO_L1_UDF_CH_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_l3_ovf_ch_int_st(&self) -> INFIFO_L3_OVF_CH_INT_ST_R { + INFIFO_L3_OVF_CH_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_l3_udf_ch_int_st(&self) -> INFIFO_L3_UDF_CH_INT_ST_R { + INFIFO_L3_UDF_CH_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ST_CH") + .field( + "in_done_ch_int_st", + &format_args!("{}", self.in_done_ch_int_st().bit()), + ) + .field( + "in_suc_eof_ch_int_st", + &format_args!("{}", self.in_suc_eof_ch_int_st().bit()), + ) + .field( + "in_err_eof_ch_int_st", + &format_args!("{}", self.in_err_eof_ch_int_st().bit()), + ) + .field( + "in_dscr_err_ch_int_st", + &format_args!("{}", self.in_dscr_err_ch_int_st().bit()), + ) + .field( + "in_dscr_empty_ch_int_st", + &format_args!("{}", self.in_dscr_empty_ch_int_st().bit()), + ) + .field( + "infifo_ovf_ch_int_st", + &format_args!("{}", self.infifo_ovf_ch_int_st().bit()), + ) + .field( + "infifo_udf_ch_int_st", + &format_args!("{}", self.infifo_udf_ch_int_st().bit()), + ) + .field( + "infifo_l1_ovf_ch_int_st", + &format_args!("{}", self.infifo_l1_ovf_ch_int_st().bit()), + ) + .field( + "infifo_l1_udf_ch_int_st", + &format_args!("{}", self.infifo_l1_udf_ch_int_st().bit()), + ) + .field( + "infifo_l3_ovf_ch_int_st", + &format_args!("{}", self.infifo_l3_ovf_ch_int_st().bit()), + ) + .field( + "infifo_l3_udf_ch_int_st", + &format_args!("{}", self.infifo_l3_udf_ch_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ST_CH_SPEC; +impl crate::RegisterSpec for IN_INT_ST_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_st_ch::R`](R) reader structure"] +impl crate::Readable for IN_INT_ST_CH_SPEC {} +#[doc = "`reset()` method sets IN_INT_ST_CH%s to value 0"] +impl crate::Resettable for IN_INT_ST_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_link1_ch.rs b/esp32p4/src/axi_dma/in_link1_ch.rs new file mode 100644 index 0000000000..cfe74a383d --- /dev/null +++ b/esp32p4/src/axi_dma/in_link1_ch.rs @@ -0,0 +1,101 @@ +#[doc = "Register `IN_LINK1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK1_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_AUTO_RET_CH` reader - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET_CH` writer - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_STOP_CH` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_START_CH` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_RESTART_CH` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_PARK_CH` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_CH_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data."] + #[inline(always)] + pub fn inlink_auto_ret_ch(&self) -> INLINK_AUTO_RET_CH_R { + INLINK_AUTO_RET_CH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] + #[inline(always)] + pub fn inlink_park_ch(&self) -> INLINK_PARK_CH_R { + INLINK_PARK_CH_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK1_CH") + .field( + "inlink_auto_ret_ch", + &format_args!("{}", self.inlink_auto_ret_ch().bit()), + ) + .field( + "inlink_park_ch", + &format_args!("{}", self.inlink_park_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data."] + #[inline(always)] + #[must_use] + pub fn inlink_auto_ret_ch(&mut self) -> INLINK_AUTO_RET_CH_W { + INLINK_AUTO_RET_CH_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_stop_ch(&mut self) -> INLINK_STOP_CH_W { + INLINK_STOP_CH_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_start_ch(&mut self) -> INLINK_START_CH_W { + INLINK_START_CH_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + #[must_use] + pub fn inlink_restart_ch(&mut self) -> INLINK_RESTART_CH_W { + INLINK_RESTART_CH_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link descriptor configure and control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link1_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link1_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK1_CH_SPEC; +impl crate::RegisterSpec for IN_LINK1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link1_ch::R`](R) reader structure"] +impl crate::Readable for IN_LINK1_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link1_ch::W`](W) writer structure"] +impl crate::Writable for IN_LINK1_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK1_CH%s to value 0x11"] +impl crate::Resettable for IN_LINK1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x11; +} diff --git a/esp32p4/src/axi_dma/in_link2_ch.rs b/esp32p4/src/axi_dma/in_link2_ch.rs new file mode 100644 index 0000000000..00bac5d821 --- /dev/null +++ b/esp32p4/src/axi_dma/in_link2_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_LINK2_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK2_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_ADDR_CH` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR_CH` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."] +pub type INLINK_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the 20 least significant bits of the first inlink descriptor's address."] + #[inline(always)] + pub fn inlink_addr_ch(&self) -> INLINK_ADDR_CH_R { + INLINK_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK2_CH") + .field( + "inlink_addr_ch", + &format_args!("{}", self.inlink_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the 20 least significant bits of the first inlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn inlink_addr_ch(&mut self) -> INLINK_ADDR_CH_W { + INLINK_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link descriptor configure and control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link2_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link2_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK2_CH_SPEC; +impl crate::RegisterSpec for IN_LINK2_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link2_ch::R`](R) reader structure"] +impl crate::Readable for IN_LINK2_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link2_ch::W`](W) writer structure"] +impl crate::Writable for IN_LINK2_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK2_CH%s to value 0"] +impl crate::Resettable for IN_LINK2_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_mem_conf.rs b/esp32p4/src/axi_dma/in_mem_conf.rs new file mode 100644 index 0000000000..fef89075f8 --- /dev/null +++ b/esp32p4/src/axi_dma/in_mem_conf.rs @@ -0,0 +1,161 @@ +#[doc = "Register `IN_MEM_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `IN_MEM_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `IN_MEM_CLK_FORCE_EN` reader - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."] +pub type IN_MEM_CLK_FORCE_EN_R = crate::BitReader; +#[doc = "Field `IN_MEM_CLK_FORCE_EN` writer - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."] +pub type IN_MEM_CLK_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_MEM_FORCE_PU` reader - Force power up ram"] +pub type IN_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `IN_MEM_FORCE_PU` writer - Force power up ram"] +pub type IN_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_MEM_FORCE_PD` reader - Force power down ram"] +pub type IN_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `IN_MEM_FORCE_PD` writer - Force power down ram"] +pub type IN_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_MEM_CLK_FORCE_EN` reader - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."] +pub type OUT_MEM_CLK_FORCE_EN_R = crate::BitReader; +#[doc = "Field `OUT_MEM_CLK_FORCE_EN` writer - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."] +pub type OUT_MEM_CLK_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_MEM_FORCE_PU` reader - Force power up ram"] +pub type OUT_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `OUT_MEM_FORCE_PU` writer - Force power up ram"] +pub type OUT_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_MEM_FORCE_PD` reader - Force power down ram"] +pub type OUT_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `OUT_MEM_FORCE_PD` writer - Force power down ram"] +pub type OUT_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."] + #[inline(always)] + pub fn in_mem_clk_force_en(&self) -> IN_MEM_CLK_FORCE_EN_R { + IN_MEM_CLK_FORCE_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Force power up ram"] + #[inline(always)] + pub fn in_mem_force_pu(&self) -> IN_MEM_FORCE_PU_R { + IN_MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Force power down ram"] + #[inline(always)] + pub fn in_mem_force_pd(&self) -> IN_MEM_FORCE_PD_R { + IN_MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."] + #[inline(always)] + pub fn out_mem_clk_force_en(&self) -> OUT_MEM_CLK_FORCE_EN_R { + OUT_MEM_CLK_FORCE_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Force power up ram"] + #[inline(always)] + pub fn out_mem_force_pu(&self) -> OUT_MEM_FORCE_PU_R { + OUT_MEM_FORCE_PU_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Force power down ram"] + #[inline(always)] + pub fn out_mem_force_pd(&self) -> OUT_MEM_FORCE_PD_R { + OUT_MEM_FORCE_PD_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_MEM_CONF") + .field( + "in_mem_clk_force_en", + &format_args!("{}", self.in_mem_clk_force_en().bit()), + ) + .field( + "in_mem_force_pu", + &format_args!("{}", self.in_mem_force_pu().bit()), + ) + .field( + "in_mem_force_pd", + &format_args!("{}", self.in_mem_force_pd().bit()), + ) + .field( + "out_mem_clk_force_en", + &format_args!("{}", self.out_mem_clk_force_en().bit()), + ) + .field( + "out_mem_force_pu", + &format_args!("{}", self.out_mem_force_pu().bit()), + ) + .field( + "out_mem_force_pd", + &format_args!("{}", self.out_mem_force_pd().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."] + #[inline(always)] + #[must_use] + pub fn in_mem_clk_force_en(&mut self) -> IN_MEM_CLK_FORCE_EN_W { + IN_MEM_CLK_FORCE_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Force power up ram"] + #[inline(always)] + #[must_use] + pub fn in_mem_force_pu(&mut self) -> IN_MEM_FORCE_PU_W { + IN_MEM_FORCE_PU_W::new(self, 1) + } + #[doc = "Bit 2 - Force power down ram"] + #[inline(always)] + #[must_use] + pub fn in_mem_force_pd(&mut self) -> IN_MEM_FORCE_PD_W { + IN_MEM_FORCE_PD_W::new(self, 2) + } + #[doc = "Bit 3 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."] + #[inline(always)] + #[must_use] + pub fn out_mem_clk_force_en(&mut self) -> OUT_MEM_CLK_FORCE_EN_W { + OUT_MEM_CLK_FORCE_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Force power up ram"] + #[inline(always)] + #[must_use] + pub fn out_mem_force_pu(&mut self) -> OUT_MEM_FORCE_PU_W { + OUT_MEM_FORCE_PU_W::new(self, 4) + } + #[doc = "Bit 5 - Force power down ram"] + #[inline(always)] + #[must_use] + pub fn out_mem_force_pd(&mut self) -> OUT_MEM_FORCE_PD_W { + OUT_MEM_FORCE_PD_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Mem power configure register of Rx channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_mem_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_mem_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_MEM_CONF_SPEC; +impl crate::RegisterSpec for IN_MEM_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_mem_conf::R`](R) reader structure"] +impl crate::Readable for IN_MEM_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_mem_conf::W`](W) writer structure"] +impl crate::Writable for IN_MEM_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_MEM_CONF to value 0"] +impl crate::Resettable for IN_MEM_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_peri_sel_ch.rs b/esp32p4/src/axi_dma/in_peri_sel_ch.rs new file mode 100644 index 0000000000..74e86e6a5a --- /dev/null +++ b/esp32p4/src/axi_dma/in_peri_sel_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_PERI_SEL_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_PERI_SEL_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `PERI_IN_SEL_CH` reader - This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy"] +pub type PERI_IN_SEL_CH_R = crate::FieldReader; +#[doc = "Field `PERI_IN_SEL_CH` writer - This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy"] +pub type PERI_IN_SEL_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy"] + #[inline(always)] + pub fn peri_in_sel_ch(&self) -> PERI_IN_SEL_CH_R { + PERI_IN_SEL_CH_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_PERI_SEL_CH") + .field( + "peri_in_sel_ch", + &format_args!("{}", self.peri_in_sel_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy"] + #[inline(always)] + #[must_use] + pub fn peri_in_sel_ch(&mut self) -> PERI_IN_SEL_CH_W { + PERI_IN_SEL_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Peripheral selection of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_peri_sel_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_peri_sel_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_PERI_SEL_CH_SPEC; +impl crate::RegisterSpec for IN_PERI_SEL_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_peri_sel_ch::R`](R) reader structure"] +impl crate::Readable for IN_PERI_SEL_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_peri_sel_ch::W`](W) writer structure"] +impl crate::Writable for IN_PERI_SEL_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_PERI_SEL_CH%s to value 0x3f"] +impl crate::Resettable for IN_PERI_SEL_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/axi_dma/in_pop_ch.rs b/esp32p4/src/axi_dma/in_pop_ch.rs new file mode 100644 index 0000000000..b68c85938b --- /dev/null +++ b/esp32p4/src/axi_dma/in_pop_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_POP_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_POP_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `INFIFO_RDATA_CH` reader - This register stores the data popping from AXI_DMA FIFO."] +pub type INFIFO_RDATA_CH_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP_CH` writer - Set this bit to pop data from AXI_DMA FIFO."] +pub type INFIFO_POP_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:11 - This register stores the data popping from AXI_DMA FIFO."] + #[inline(always)] + pub fn infifo_rdata_ch(&self) -> INFIFO_RDATA_CH_R { + INFIFO_RDATA_CH_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_CH") + .field( + "infifo_rdata_ch", + &format_args!("{}", self.infifo_rdata_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 12 - Set this bit to pop data from AXI_DMA FIFO."] + #[inline(always)] + #[must_use] + pub fn infifo_pop_ch(&mut self) -> INFIFO_POP_CH_W { + INFIFO_POP_CH_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Pop control register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_CH_SPEC; +impl crate::RegisterSpec for IN_POP_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_ch::R`](R) reader structure"] +impl crate::Readable for IN_POP_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_pop_ch::W`](W) writer structure"] +impl crate::Writable for IN_POP_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_POP_CH%s to value 0x0800"] +impl crate::Resettable for IN_POP_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/axi_dma/in_pri_ch.rs b/esp32p4/src/axi_dma/in_pri_ch.rs new file mode 100644 index 0000000000..9a76ecd631 --- /dev/null +++ b/esp32p4/src/axi_dma/in_pri_ch.rs @@ -0,0 +1,101 @@ +#[doc = "Register `IN_PRI_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `IN_PRI_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_PRI_CH` reader - The priority of Rx channel 0. The larger of the value the higher of the priority."] +pub type RX_PRI_CH_R = crate::FieldReader; +#[doc = "Field `RX_PRI_CH` writer - The priority of Rx channel 0. The larger of the value the higher of the priority."] +pub type RX_PRI_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RX_CH_ARB_WEIGH_CH` reader - The weight of Rx channel 0"] +pub type RX_CH_ARB_WEIGH_CH_R = crate::FieldReader; +#[doc = "Field `RX_CH_ARB_WEIGH_CH` writer - The weight of Rx channel 0"] +pub type RX_CH_ARB_WEIGH_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RX_ARB_WEIGH_OPT_DIR_CH` reader - 0: mean not optimazation weight function ,1: mean optimazation"] +pub type RX_ARB_WEIGH_OPT_DIR_CH_R = crate::BitReader; +#[doc = "Field `RX_ARB_WEIGH_OPT_DIR_CH` writer - 0: mean not optimazation weight function ,1: mean optimazation"] +pub type RX_ARB_WEIGH_OPT_DIR_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value the higher of the priority."] + #[inline(always)] + pub fn rx_pri_ch(&self) -> RX_PRI_CH_R { + RX_PRI_CH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - The weight of Rx channel 0"] + #[inline(always)] + pub fn rx_ch_arb_weigh_ch(&self) -> RX_CH_ARB_WEIGH_CH_R { + RX_CH_ARB_WEIGH_CH_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8 - 0: mean not optimazation weight function ,1: mean optimazation"] + #[inline(always)] + pub fn rx_arb_weigh_opt_dir_ch(&self) -> RX_ARB_WEIGH_OPT_DIR_CH_R { + RX_ARB_WEIGH_OPT_DIR_CH_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_PRI_CH") + .field("rx_pri_ch", &format_args!("{}", self.rx_pri_ch().bits())) + .field( + "rx_ch_arb_weigh_ch", + &format_args!("{}", self.rx_ch_arb_weigh_ch().bits()), + ) + .field( + "rx_arb_weigh_opt_dir_ch", + &format_args!("{}", self.rx_arb_weigh_opt_dir_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value the higher of the priority."] + #[inline(always)] + #[must_use] + pub fn rx_pri_ch(&mut self) -> RX_PRI_CH_W { + RX_PRI_CH_W::new(self, 0) + } + #[doc = "Bits 4:7 - The weight of Rx channel 0"] + #[inline(always)] + #[must_use] + pub fn rx_ch_arb_weigh_ch(&mut self) -> RX_CH_ARB_WEIGH_CH_W { + RX_CH_ARB_WEIGH_CH_W::new(self, 4) + } + #[doc = "Bit 8 - 0: mean not optimazation weight function ,1: mean optimazation"] + #[inline(always)] + #[must_use] + pub fn rx_arb_weigh_opt_dir_ch(&mut self) -> RX_ARB_WEIGH_OPT_DIR_CH_W { + RX_ARB_WEIGH_OPT_DIR_CH_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Priority register of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pri_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pri_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_PRI_CH_SPEC; +impl crate::RegisterSpec for IN_PRI_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pri_ch::R`](R) reader structure"] +impl crate::Readable for IN_PRI_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_pri_ch::W`](W) writer structure"] +impl crate::Writable for IN_PRI_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_PRI_CH%s to value 0"] +impl crate::Resettable for IN_PRI_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_reset_avail_ch.rs b/esp32p4/src/axi_dma/in_reset_avail_ch.rs new file mode 100644 index 0000000000..dcc6e25146 --- /dev/null +++ b/esp32p4/src/axi_dma/in_reset_avail_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_RESET_AVAIL_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `IN_RESET_AVAIL_CH` reader - rx chan0 reset valid reg."] +pub type IN_RESET_AVAIL_CH_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - rx chan0 reset valid reg."] + #[inline(always)] + pub fn in_reset_avail_ch(&self) -> IN_RESET_AVAIL_CH_R { + IN_RESET_AVAIL_CH_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_RESET_AVAIL_CH") + .field( + "in_reset_avail_ch", + &format_args!("{}", self.in_reset_avail_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The rx channel 0 reset valid_flag register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_reset_avail_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_RESET_AVAIL_CH_SPEC; +impl crate::RegisterSpec for IN_RESET_AVAIL_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_reset_avail_ch::R`](R) reader structure"] +impl crate::Readable for IN_RESET_AVAIL_CH_SPEC {} +#[doc = "`reset()` method sets IN_RESET_AVAIL_CH%s to value 0x01"] +impl crate::Resettable for IN_RESET_AVAIL_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/axi_dma/in_state_ch.rs b/esp32p4/src/axi_dma/in_state_ch.rs new file mode 100644 index 0000000000..88cde19415 --- /dev/null +++ b/esp32p4/src/axi_dma/in_state_ch.rs @@ -0,0 +1,61 @@ +#[doc = "Register `IN_STATE_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_ADDR_CH` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE_CH` reader - reserved"] +pub type IN_DSCR_STATE_CH_R = crate::FieldReader; +#[doc = "Field `IN_STATE_CH` reader - reserved"] +pub type IN_STATE_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] + #[inline(always)] + pub fn inlink_dscr_addr_ch(&self) -> INLINK_DSCR_ADDR_CH_R { + INLINK_DSCR_ADDR_CH_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - reserved"] + #[inline(always)] + pub fn in_dscr_state_ch(&self) -> IN_DSCR_STATE_CH_R { + IN_DSCR_STATE_CH_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - reserved"] + #[inline(always)] + pub fn in_state_ch(&self) -> IN_STATE_CH_R { + IN_STATE_CH_R::new(((self.bits >> 20) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_STATE_CH") + .field( + "inlink_dscr_addr_ch", + &format_args!("{}", self.inlink_dscr_addr_ch().bits()), + ) + .field( + "in_dscr_state_ch", + &format_args!("{}", self.in_dscr_state_ch().bits()), + ) + .field( + "in_state_ch", + &format_args!("{}", self.in_state_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Receive status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_STATE_CH_SPEC; +impl crate::RegisterSpec for IN_STATE_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_state_ch::R`](R) reader structure"] +impl crate::Readable for IN_STATE_CH_SPEC {} +#[doc = "`reset()` method sets IN_STATE_CH%s to value 0"] +impl crate::Resettable for IN_STATE_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/in_suc_eof_des_addr_ch.rs b/esp32p4/src/axi_dma/in_suc_eof_des_addr_ch.rs new file mode 100644 index 0000000000..3405d46814 --- /dev/null +++ b/esp32p4/src/axi_dma/in_suc_eof_des_addr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_SUC_EOF_DES_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn in_suc_eof_des_addr_ch(&self) -> IN_SUC_EOF_DES_ADDR_CH_R { + IN_SUC_EOF_DES_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_SUC_EOF_DES_ADDR_CH") + .field( + "in_suc_eof_des_addr_ch", + &format_args!("{}", self.in_suc_eof_des_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_SUC_EOF_DES_ADDR_CH_SPEC; +impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_suc_eof_des_addr_ch::R`](R) reader structure"] +impl crate::Readable for IN_SUC_EOF_DES_ADDR_CH_SPEC {} +#[doc = "`reset()` method sets IN_SUC_EOF_DES_ADDR_CH%s to value 0"] +impl crate::Resettable for IN_SUC_EOF_DES_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/infifo_status1_ch.rs b/esp32p4/src/axi_dma/infifo_status1_ch.rs new file mode 100644 index 0000000000..7263641a6e --- /dev/null +++ b/esp32p4/src/axi_dma/infifo_status1_ch.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INFIFO_STATUS1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `L1INFIFO_CNT_CH` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] +pub type L1INFIFO_CNT_CH_R = crate::FieldReader; +#[doc = "Field `L2INFIFO_CNT_CH` reader - The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0."] +pub type L2INFIFO_CNT_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:5 - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."] + #[inline(always)] + pub fn l1infifo_cnt_ch(&self) -> L1INFIFO_CNT_CH_R { + L1INFIFO_CNT_CH_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:9 - The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0."] + #[inline(always)] + pub fn l2infifo_cnt_ch(&self) -> L2INFIFO_CNT_CH_R { + L2INFIFO_CNT_CH_R::new(((self.bits >> 6) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INFIFO_STATUS1_CH") + .field( + "l1infifo_cnt_ch", + &format_args!("{}", self.l1infifo_cnt_ch().bits()), + ) + .field( + "l2infifo_cnt_ch", + &format_args!("{}", self.l2infifo_cnt_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status1_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFIFO_STATUS1_CH_SPEC; +impl crate::RegisterSpec for INFIFO_STATUS1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`infifo_status1_ch::R`](R) reader structure"] +impl crate::Readable for INFIFO_STATUS1_CH_SPEC {} +#[doc = "`reset()` method sets INFIFO_STATUS1_CH%s to value 0"] +impl crate::Resettable for INFIFO_STATUS1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/infifo_status_ch.rs b/esp32p4/src/axi_dma/infifo_status_ch.rs new file mode 100644 index 0000000000..367b068d3f --- /dev/null +++ b/esp32p4/src/axi_dma/infifo_status_ch.rs @@ -0,0 +1,270 @@ +#[doc = "Register `INFIFO_STATUS_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `INFIFO_L3_FULL_CH` reader - L3 Rx FIFO full signal for Rx channel 0."] +pub type INFIFO_L3_FULL_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_L3_EMPTY_CH` reader - L3 Rx FIFO empty signal for Rx channel 0."] +pub type INFIFO_L3_EMPTY_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_L3_CNT_CH` reader - The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0."] +pub type INFIFO_L3_CNT_CH_R = crate::FieldReader; +#[doc = "Field `INFIFO_L3_UDF_CH` reader - L3 Rx FIFO under flow signal for Rx channel 0."] +pub type INFIFO_L3_UDF_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_L3_OVF_CH` reader - L3 Rx FIFO over flow signal for Rx channel 0."] +pub type INFIFO_L3_OVF_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_L1_FULL_CH` reader - L1 Rx FIFO full signal for Rx channel 0."] +pub type INFIFO_L1_FULL_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_L1_EMPTY_CH` reader - L1 Rx FIFO empty signal for Rx channel 0."] +pub type INFIFO_L1_EMPTY_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_L1_UDF_CH` reader - L1 Rx FIFO under flow signal for Rx channel 0."] +pub type INFIFO_L1_UDF_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_L1_OVF_CH` reader - L1 Rx FIFO over flow signal for Rx channel 0."] +pub type INFIFO_L1_OVF_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_L2_FULL_CH` reader - L2 Rx RAM full signal for Rx channel 0."] +pub type INFIFO_L2_FULL_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_L2_EMPTY_CH` reader - L2 Rx RAM empty signal for Rx channel 0."] +pub type INFIFO_L2_EMPTY_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_L2_UDF_CH` reader - L2 Rx FIFO under flow signal for Rx channel 0."] +pub type INFIFO_L2_UDF_CH_R = crate::BitReader; +#[doc = "Field `INFIFO_L2_OVF_CH` reader - L2 Rx FIFO over flow signal for Rx channel 0."] +pub type INFIFO_L2_OVF_CH_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_1B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_1B_CH_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_2B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_2B_CH_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_3B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_3B_CH_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_4B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_4B_CH_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_5B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_5B_CH_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_6B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_6B_CH_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_7B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_7B_CH_R = crate::BitReader; +#[doc = "Field `IN_REMAIN_UNDER_8B_CH` reader - reserved"] +pub type IN_REMAIN_UNDER_8B_CH_R = crate::BitReader; +#[doc = "Field `IN_BUF_HUNGRY_CH` reader - reserved"] +pub type IN_BUF_HUNGRY_CH_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - L3 Rx FIFO full signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l3_full_ch(&self) -> INFIFO_L3_FULL_CH_R { + INFIFO_L3_FULL_CH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - L3 Rx FIFO empty signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l3_empty_ch(&self) -> INFIFO_L3_EMPTY_CH_R { + INFIFO_L3_EMPTY_CH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0."] + #[inline(always)] + pub fn infifo_l3_cnt_ch(&self) -> INFIFO_L3_CNT_CH_R { + INFIFO_L3_CNT_CH_R::new(((self.bits >> 2) & 0x3f) as u8) + } + #[doc = "Bit 8 - L3 Rx FIFO under flow signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l3_udf_ch(&self) -> INFIFO_L3_UDF_CH_R { + INFIFO_L3_UDF_CH_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - L3 Rx FIFO over flow signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l3_ovf_ch(&self) -> INFIFO_L3_OVF_CH_R { + INFIFO_L3_OVF_CH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - L1 Rx FIFO full signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l1_full_ch(&self) -> INFIFO_L1_FULL_CH_R { + INFIFO_L1_FULL_CH_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - L1 Rx FIFO empty signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l1_empty_ch(&self) -> INFIFO_L1_EMPTY_CH_R { + INFIFO_L1_EMPTY_CH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - L1 Rx FIFO under flow signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l1_udf_ch(&self) -> INFIFO_L1_UDF_CH_R { + INFIFO_L1_UDF_CH_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - L1 Rx FIFO over flow signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l1_ovf_ch(&self) -> INFIFO_L1_OVF_CH_R { + INFIFO_L1_OVF_CH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - L2 Rx RAM full signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l2_full_ch(&self) -> INFIFO_L2_FULL_CH_R { + INFIFO_L2_FULL_CH_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - L2 Rx RAM empty signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l2_empty_ch(&self) -> INFIFO_L2_EMPTY_CH_R { + INFIFO_L2_EMPTY_CH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - L2 Rx FIFO under flow signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l2_udf_ch(&self) -> INFIFO_L2_UDF_CH_R { + INFIFO_L2_UDF_CH_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - L2 Rx FIFO over flow signal for Rx channel 0."] + #[inline(always)] + pub fn infifo_l2_ovf_ch(&self) -> INFIFO_L2_OVF_CH_R { + INFIFO_L2_OVF_CH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 23 - reserved"] + #[inline(always)] + pub fn in_remain_under_1b_ch(&self) -> IN_REMAIN_UNDER_1B_CH_R { + IN_REMAIN_UNDER_1B_CH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - reserved"] + #[inline(always)] + pub fn in_remain_under_2b_ch(&self) -> IN_REMAIN_UNDER_2B_CH_R { + IN_REMAIN_UNDER_2B_CH_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reserved"] + #[inline(always)] + pub fn in_remain_under_3b_ch(&self) -> IN_REMAIN_UNDER_3B_CH_R { + IN_REMAIN_UNDER_3B_CH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - reserved"] + #[inline(always)] + pub fn in_remain_under_4b_ch(&self) -> IN_REMAIN_UNDER_4B_CH_R { + IN_REMAIN_UNDER_4B_CH_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - reserved"] + #[inline(always)] + pub fn in_remain_under_5b_ch(&self) -> IN_REMAIN_UNDER_5B_CH_R { + IN_REMAIN_UNDER_5B_CH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - reserved"] + #[inline(always)] + pub fn in_remain_under_6b_ch(&self) -> IN_REMAIN_UNDER_6B_CH_R { + IN_REMAIN_UNDER_6B_CH_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - reserved"] + #[inline(always)] + pub fn in_remain_under_7b_ch(&self) -> IN_REMAIN_UNDER_7B_CH_R { + IN_REMAIN_UNDER_7B_CH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - reserved"] + #[inline(always)] + pub fn in_remain_under_8b_ch(&self) -> IN_REMAIN_UNDER_8B_CH_R { + IN_REMAIN_UNDER_8B_CH_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - reserved"] + #[inline(always)] + pub fn in_buf_hungry_ch(&self) -> IN_BUF_HUNGRY_CH_R { + IN_BUF_HUNGRY_CH_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INFIFO_STATUS_CH") + .field( + "infifo_l3_full_ch", + &format_args!("{}", self.infifo_l3_full_ch().bit()), + ) + .field( + "infifo_l3_empty_ch", + &format_args!("{}", self.infifo_l3_empty_ch().bit()), + ) + .field( + "infifo_l3_cnt_ch", + &format_args!("{}", self.infifo_l3_cnt_ch().bits()), + ) + .field( + "infifo_l3_udf_ch", + &format_args!("{}", self.infifo_l3_udf_ch().bit()), + ) + .field( + "infifo_l3_ovf_ch", + &format_args!("{}", self.infifo_l3_ovf_ch().bit()), + ) + .field( + "infifo_l1_full_ch", + &format_args!("{}", self.infifo_l1_full_ch().bit()), + ) + .field( + "infifo_l1_empty_ch", + &format_args!("{}", self.infifo_l1_empty_ch().bit()), + ) + .field( + "infifo_l1_udf_ch", + &format_args!("{}", self.infifo_l1_udf_ch().bit()), + ) + .field( + "infifo_l1_ovf_ch", + &format_args!("{}", self.infifo_l1_ovf_ch().bit()), + ) + .field( + "infifo_l2_full_ch", + &format_args!("{}", self.infifo_l2_full_ch().bit()), + ) + .field( + "infifo_l2_empty_ch", + &format_args!("{}", self.infifo_l2_empty_ch().bit()), + ) + .field( + "infifo_l2_udf_ch", + &format_args!("{}", self.infifo_l2_udf_ch().bit()), + ) + .field( + "infifo_l2_ovf_ch", + &format_args!("{}", self.infifo_l2_ovf_ch().bit()), + ) + .field( + "in_remain_under_1b_ch", + &format_args!("{}", self.in_remain_under_1b_ch().bit()), + ) + .field( + "in_remain_under_2b_ch", + &format_args!("{}", self.in_remain_under_2b_ch().bit()), + ) + .field( + "in_remain_under_3b_ch", + &format_args!("{}", self.in_remain_under_3b_ch().bit()), + ) + .field( + "in_remain_under_4b_ch", + &format_args!("{}", self.in_remain_under_4b_ch().bit()), + ) + .field( + "in_remain_under_5b_ch", + &format_args!("{}", self.in_remain_under_5b_ch().bit()), + ) + .field( + "in_remain_under_6b_ch", + &format_args!("{}", self.in_remain_under_6b_ch().bit()), + ) + .field( + "in_remain_under_7b_ch", + &format_args!("{}", self.in_remain_under_7b_ch().bit()), + ) + .field( + "in_remain_under_8b_ch", + &format_args!("{}", self.in_remain_under_8b_ch().bit()), + ) + .field( + "in_buf_hungry_ch", + &format_args!("{}", self.in_buf_hungry_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFIFO_STATUS_CH_SPEC; +impl crate::RegisterSpec for INFIFO_STATUS_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`infifo_status_ch::R`](R) reader structure"] +impl crate::Readable for INFIFO_STATUS_CH_SPEC {} +#[doc = "`reset()` method sets INFIFO_STATUS_CH%s to value 0x8803"] +impl crate::Resettable for INFIFO_STATUS_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x8803; +} diff --git a/esp32p4/src/axi_dma/intr_mem_end_addr.rs b/esp32p4/src/axi_dma/intr_mem_end_addr.rs new file mode 100644 index 0000000000..4636ab83cd --- /dev/null +++ b/esp32p4/src/axi_dma/intr_mem_end_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `INTR_MEM_END_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR_MEM_END_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_INTR_MEM_END_ADDR` reader - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_INTR_MEM_END_ADDR_R = crate::FieldReader; +#[doc = "Field `ACCESS_INTR_MEM_END_ADDR` writer - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_INTR_MEM_END_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + pub fn access_intr_mem_end_addr(&self) -> ACCESS_INTR_MEM_END_ADDR_R { + ACCESS_INTR_MEM_END_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_MEM_END_ADDR") + .field( + "access_intr_mem_end_addr", + &format_args!("{}", self.access_intr_mem_end_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + #[must_use] + pub fn access_intr_mem_end_addr( + &mut self, + ) -> ACCESS_INTR_MEM_END_ADDR_W { + ACCESS_INTR_MEM_END_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The end address of accessible address space. The access address beyond this range would lead to descriptor error.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mem_end_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mem_end_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_MEM_END_ADDR_SPEC; +impl crate::RegisterSpec for INTR_MEM_END_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_mem_end_addr::R`](R) reader structure"] +impl crate::Readable for INTR_MEM_END_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr_mem_end_addr::W`](W) writer structure"] +impl crate::Writable for INTR_MEM_END_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTR_MEM_END_ADDR to value 0x8fff_ffff"] +impl crate::Resettable for INTR_MEM_END_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0x8fff_ffff; +} diff --git a/esp32p4/src/axi_dma/intr_mem_start_addr.rs b/esp32p4/src/axi_dma/intr_mem_start_addr.rs new file mode 100644 index 0000000000..fb0a4c548d --- /dev/null +++ b/esp32p4/src/axi_dma/intr_mem_start_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `INTR_MEM_START_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR_MEM_START_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_INTR_MEM_START_ADDR` reader - The start address of accessible address space."] +pub type ACCESS_INTR_MEM_START_ADDR_R = crate::FieldReader; +#[doc = "Field `ACCESS_INTR_MEM_START_ADDR` writer - The start address of accessible address space."] +pub type ACCESS_INTR_MEM_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + pub fn access_intr_mem_start_addr(&self) -> ACCESS_INTR_MEM_START_ADDR_R { + ACCESS_INTR_MEM_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_MEM_START_ADDR") + .field( + "access_intr_mem_start_addr", + &format_args!("{}", self.access_intr_mem_start_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + #[must_use] + pub fn access_intr_mem_start_addr( + &mut self, + ) -> ACCESS_INTR_MEM_START_ADDR_W { + ACCESS_INTR_MEM_START_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The start address of accessible address space.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_mem_start_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_mem_start_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_MEM_START_ADDR_SPEC; +impl crate::RegisterSpec for INTR_MEM_START_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_mem_start_addr::R`](R) reader structure"] +impl crate::Readable for INTR_MEM_START_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr_mem_start_addr::W`](W) writer structure"] +impl crate::Writable for INTR_MEM_START_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTR_MEM_START_ADDR to value 0x3010_0000"] +impl crate::Resettable for INTR_MEM_START_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0x3010_0000; +} diff --git a/esp32p4/src/axi_dma/misc_conf.rs b/esp32p4/src/axi_dma/misc_conf.rs new file mode 100644 index 0000000000..53562daa4a --- /dev/null +++ b/esp32p4/src/axi_dma/misc_conf.rs @@ -0,0 +1,117 @@ +#[doc = "Register `MISC_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `MISC_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `AXIM_RST_WR_INTER` reader - Set this bit then clear this bit to reset the internal axi_wr FSM."] +pub type AXIM_RST_WR_INTER_R = crate::BitReader; +#[doc = "Field `AXIM_RST_WR_INTER` writer - Set this bit then clear this bit to reset the internal axi_wr FSM."] +pub type AXIM_RST_WR_INTER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AXIM_RST_RD_INTER` reader - Set this bit then clear this bit to reset the internal axi_rd FSM."] +pub type AXIM_RST_RD_INTER_R = crate::BitReader; +#[doc = "Field `AXIM_RST_RD_INTER` writer - Set this bit then clear this bit to reset the internal axi_rd FSM."] +pub type AXIM_RST_RD_INTER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARB_PRI_DIS` reader - Set this bit to disable priority arbitration function."] +pub type ARB_PRI_DIS_R = crate::BitReader; +#[doc = "Field `ARB_PRI_DIS` writer - Set this bit to disable priority arbitration function."] +pub type ARB_PRI_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit then clear this bit to reset the internal axi_wr FSM."] + #[inline(always)] + pub fn axim_rst_wr_inter(&self) -> AXIM_RST_WR_INTER_R { + AXIM_RST_WR_INTER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit then clear this bit to reset the internal axi_rd FSM."] + #[inline(always)] + pub fn axim_rst_rd_inter(&self) -> AXIM_RST_RD_INTER_R { + AXIM_RST_RD_INTER_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to disable priority arbitration function."] + #[inline(always)] + pub fn arb_pri_dis(&self) -> ARB_PRI_DIS_R { + ARB_PRI_DIS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MISC_CONF") + .field( + "axim_rst_wr_inter", + &format_args!("{}", self.axim_rst_wr_inter().bit()), + ) + .field( + "axim_rst_rd_inter", + &format_args!("{}", self.axim_rst_rd_inter().bit()), + ) + .field("arb_pri_dis", &format_args!("{}", self.arb_pri_dis().bit())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit then clear this bit to reset the internal axi_wr FSM."] + #[inline(always)] + #[must_use] + pub fn axim_rst_wr_inter(&mut self) -> AXIM_RST_WR_INTER_W { + AXIM_RST_WR_INTER_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit then clear this bit to reset the internal axi_rd FSM."] + #[inline(always)] + #[must_use] + pub fn axim_rst_rd_inter(&mut self) -> AXIM_RST_RD_INTER_W { + AXIM_RST_RD_INTER_W::new(self, 1) + } + #[doc = "Bit 3 - Set this bit to disable priority arbitration function."] + #[inline(always)] + #[must_use] + pub fn arb_pri_dis(&mut self) -> ARB_PRI_DIS_W { + ARB_PRI_DIS_W::new(self, 3) + } + #[doc = "Bit 4 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MISC register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`misc_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`misc_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MISC_CONF_SPEC; +impl crate::RegisterSpec for MISC_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`misc_conf::R`](R) reader structure"] +impl crate::Readable for MISC_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`misc_conf::W`](W) writer structure"] +impl crate::Writable for MISC_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MISC_CONF to value 0"] +impl crate::Resettable for MISC_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_conf0_ch0.rs b/esp32p4/src/axi_dma/out_conf0_ch0.rs new file mode 100644 index 0000000000..f2af0d821a --- /dev/null +++ b/esp32p4/src/axi_dma/out_conf0_ch0.rs @@ -0,0 +1,215 @@ +#[doc = "Register `OUT_CONF0_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF0_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_RST_CH0` reader - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_CH0_R = crate::BitReader; +#[doc = "Field `OUT_RST_CH0` writer - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_LOOP_TEST_CH0` reader - reserved"] +pub type OUT_LOOP_TEST_CH0_R = crate::BitReader; +#[doc = "Field `OUT_LOOP_TEST_CH0` writer - reserved"] +pub type OUT_LOOP_TEST_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_AUTO_WRBACK_CH0` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_CH0_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK_CH0` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_MODE_CH0` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] +pub type OUT_EOF_MODE_CH0_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE_CH0` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] +pub type OUT_EOF_MODE_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ETM_EN_CH0` reader - Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task."] +pub type OUT_ETM_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUT_ETM_EN_CH0` writer - Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task."] +pub type OUT_ETM_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_BURST_SIZE_SEL_CH0` reader - 3'b000-3'b100:burst length 8byte~128byte"] +pub type OUT_BURST_SIZE_SEL_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_BURST_SIZE_SEL_CH0` writer - 3'b000-3'b100:burst length 8byte~128byte"] +pub type OUT_BURST_SIZE_SEL_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OUT_CMD_DISABLE_CH0` reader - 1:mean disable cmd of this ch0"] +pub type OUT_CMD_DISABLE_CH0_R = crate::BitReader; +#[doc = "Field `OUT_CMD_DISABLE_CH0` writer - 1:mean disable cmd of this ch0"] +pub type OUT_CMD_DISABLE_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ECC_AEC_EN_CH0` reader - 1: mean access ecc or aes domain,0: mean not"] +pub type OUT_ECC_AEC_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUT_ECC_AEC_EN_CH0` writer - 1: mean access ecc or aes domain,0: mean not"] +pub type OUT_ECC_AEC_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTDSCR_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."] + #[inline(always)] + pub fn out_rst_ch0(&self) -> OUT_RST_CH0_R { + OUT_RST_CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + pub fn out_loop_test_ch0(&self) -> OUT_LOOP_TEST_CH0_R { + OUT_LOOP_TEST_CH0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] + #[inline(always)] + pub fn out_auto_wrback_ch0(&self) -> OUT_AUTO_WRBACK_CH0_R { + OUT_AUTO_WRBACK_CH0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] + #[inline(always)] + pub fn out_eof_mode_ch0(&self) -> OUT_EOF_MODE_CH0_R { + OUT_EOF_MODE_CH0_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task."] + #[inline(always)] + pub fn out_etm_en_ch0(&self) -> OUT_ETM_EN_CH0_R { + OUT_ETM_EN_CH0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - 3'b000-3'b100:burst length 8byte~128byte"] + #[inline(always)] + pub fn out_burst_size_sel_ch0(&self) -> OUT_BURST_SIZE_SEL_CH0_R { + OUT_BURST_SIZE_SEL_CH0_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 8 - 1:mean disable cmd of this ch0"] + #[inline(always)] + pub fn out_cmd_disable_ch0(&self) -> OUT_CMD_DISABLE_CH0_R { + OUT_CMD_DISABLE_CH0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: mean access ecc or aes domain,0: mean not"] + #[inline(always)] + pub fn out_ecc_aec_en_ch0(&self) -> OUT_ECC_AEC_EN_CH0_R { + OUT_ECC_AEC_EN_CH0_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn outdscr_burst_en_ch0(&self) -> OUTDSCR_BURST_EN_CH0_R { + OUTDSCR_BURST_EN_CH0_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF0_CH0") + .field("out_rst_ch0", &format_args!("{}", self.out_rst_ch0().bit())) + .field( + "out_loop_test_ch0", + &format_args!("{}", self.out_loop_test_ch0().bit()), + ) + .field( + "out_auto_wrback_ch0", + &format_args!("{}", self.out_auto_wrback_ch0().bit()), + ) + .field( + "out_eof_mode_ch0", + &format_args!("{}", self.out_eof_mode_ch0().bit()), + ) + .field( + "out_etm_en_ch0", + &format_args!("{}", self.out_etm_en_ch0().bit()), + ) + .field( + "out_burst_size_sel_ch0", + &format_args!("{}", self.out_burst_size_sel_ch0().bits()), + ) + .field( + "out_cmd_disable_ch0", + &format_args!("{}", self.out_cmd_disable_ch0().bit()), + ) + .field( + "out_ecc_aec_en_ch0", + &format_args!("{}", self.out_ecc_aec_en_ch0().bit()), + ) + .field( + "outdscr_burst_en_ch0", + &format_args!("{}", self.outdscr_burst_en_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."] + #[inline(always)] + #[must_use] + pub fn out_rst_ch0(&mut self) -> OUT_RST_CH0_W { + OUT_RST_CH0_W::new(self, 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + #[must_use] + pub fn out_loop_test_ch0(&mut self) -> OUT_LOOP_TEST_CH0_W { + OUT_LOOP_TEST_CH0_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] + #[inline(always)] + #[must_use] + pub fn out_auto_wrback_ch0(&mut self) -> OUT_AUTO_WRBACK_CH0_W { + OUT_AUTO_WRBACK_CH0_W::new(self, 2) + } + #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] + #[inline(always)] + #[must_use] + pub fn out_eof_mode_ch0(&mut self) -> OUT_EOF_MODE_CH0_W { + OUT_EOF_MODE_CH0_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task."] + #[inline(always)] + #[must_use] + pub fn out_etm_en_ch0(&mut self) -> OUT_ETM_EN_CH0_W { + OUT_ETM_EN_CH0_W::new(self, 4) + } + #[doc = "Bits 5:7 - 3'b000-3'b100:burst length 8byte~128byte"] + #[inline(always)] + #[must_use] + pub fn out_burst_size_sel_ch0(&mut self) -> OUT_BURST_SIZE_SEL_CH0_W { + OUT_BURST_SIZE_SEL_CH0_W::new(self, 5) + } + #[doc = "Bit 8 - 1:mean disable cmd of this ch0"] + #[inline(always)] + #[must_use] + pub fn out_cmd_disable_ch0(&mut self) -> OUT_CMD_DISABLE_CH0_W { + OUT_CMD_DISABLE_CH0_W::new(self, 8) + } + #[doc = "Bit 9 - 1: mean access ecc or aes domain,0: mean not"] + #[inline(always)] + #[must_use] + pub fn out_ecc_aec_en_ch0(&mut self) -> OUT_ECC_AEC_EN_CH0_W { + OUT_ECC_AEC_EN_CH0_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn outdscr_burst_en_ch0(&mut self) -> OUTDSCR_BURST_EN_CH0_W { + OUTDSCR_BURST_EN_CH0_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure 0 register of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF0_CH0_SPEC; +impl crate::RegisterSpec for OUT_CONF0_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf0_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_CONF0_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf0_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_CONF0_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF0_CH0 to value 0x08"] +impl crate::Resettable for OUT_CONF0_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/axi_dma/out_conf0_ch1.rs b/esp32p4/src/axi_dma/out_conf0_ch1.rs new file mode 100644 index 0000000000..d8710cfdca --- /dev/null +++ b/esp32p4/src/axi_dma/out_conf0_ch1.rs @@ -0,0 +1,215 @@ +#[doc = "Register `OUT_CONF0_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF0_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_RST_CH1` reader - This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_CH1_R = crate::BitReader; +#[doc = "Field `OUT_RST_CH1` writer - This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_LOOP_TEST_CH1` reader - reserved"] +pub type OUT_LOOP_TEST_CH1_R = crate::BitReader; +#[doc = "Field `OUT_LOOP_TEST_CH1` writer - reserved"] +pub type OUT_LOOP_TEST_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_AUTO_WRBACK_CH1` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_CH1_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK_CH1` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_MODE_CH1` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] +pub type OUT_EOF_MODE_CH1_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE_CH1` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] +pub type OUT_EOF_MODE_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ETM_EN_CH1` reader - Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm task."] +pub type OUT_ETM_EN_CH1_R = crate::BitReader; +#[doc = "Field `OUT_ETM_EN_CH1` writer - Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm task."] +pub type OUT_ETM_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_BURST_SIZE_SEL_CH1` reader - 3'b000-3'b100:burst length 8byte~128byte"] +pub type OUT_BURST_SIZE_SEL_CH1_R = crate::FieldReader; +#[doc = "Field `OUT_BURST_SIZE_SEL_CH1` writer - 3'b000-3'b100:burst length 8byte~128byte"] +pub type OUT_BURST_SIZE_SEL_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OUT_CMD_DISABLE_CH1` reader - 1:mean disable cmd of this ch1"] +pub type OUT_CMD_DISABLE_CH1_R = crate::BitReader; +#[doc = "Field `OUT_CMD_DISABLE_CH1` writer - 1:mean disable cmd of this ch1"] +pub type OUT_CMD_DISABLE_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ECC_AEC_EN_CH1` reader - 1: mean access ecc or aes domain,0: mean not"] +pub type OUT_ECC_AEC_EN_CH1_R = crate::BitReader; +#[doc = "Field `OUT_ECC_AEC_EN_CH1` writer - 1: mean access ecc or aes domain,0: mean not"] +pub type OUT_ECC_AEC_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTDSCR_BURST_EN_CH1` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH1_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN_CH1` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer."] + #[inline(always)] + pub fn out_rst_ch1(&self) -> OUT_RST_CH1_R { + OUT_RST_CH1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + pub fn out_loop_test_ch1(&self) -> OUT_LOOP_TEST_CH1_R { + OUT_LOOP_TEST_CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] + #[inline(always)] + pub fn out_auto_wrback_ch1(&self) -> OUT_AUTO_WRBACK_CH1_R { + OUT_AUTO_WRBACK_CH1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] + #[inline(always)] + pub fn out_eof_mode_ch1(&self) -> OUT_EOF_MODE_CH1_R { + OUT_EOF_MODE_CH1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm task."] + #[inline(always)] + pub fn out_etm_en_ch1(&self) -> OUT_ETM_EN_CH1_R { + OUT_ETM_EN_CH1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - 3'b000-3'b100:burst length 8byte~128byte"] + #[inline(always)] + pub fn out_burst_size_sel_ch1(&self) -> OUT_BURST_SIZE_SEL_CH1_R { + OUT_BURST_SIZE_SEL_CH1_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 8 - 1:mean disable cmd of this ch1"] + #[inline(always)] + pub fn out_cmd_disable_ch1(&self) -> OUT_CMD_DISABLE_CH1_R { + OUT_CMD_DISABLE_CH1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: mean access ecc or aes domain,0: mean not"] + #[inline(always)] + pub fn out_ecc_aec_en_ch1(&self) -> OUT_ECC_AEC_EN_CH1_R { + OUT_ECC_AEC_EN_CH1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn outdscr_burst_en_ch1(&self) -> OUTDSCR_BURST_EN_CH1_R { + OUTDSCR_BURST_EN_CH1_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF0_CH1") + .field("out_rst_ch1", &format_args!("{}", self.out_rst_ch1().bit())) + .field( + "out_loop_test_ch1", + &format_args!("{}", self.out_loop_test_ch1().bit()), + ) + .field( + "out_auto_wrback_ch1", + &format_args!("{}", self.out_auto_wrback_ch1().bit()), + ) + .field( + "out_eof_mode_ch1", + &format_args!("{}", self.out_eof_mode_ch1().bit()), + ) + .field( + "out_etm_en_ch1", + &format_args!("{}", self.out_etm_en_ch1().bit()), + ) + .field( + "out_burst_size_sel_ch1", + &format_args!("{}", self.out_burst_size_sel_ch1().bits()), + ) + .field( + "out_cmd_disable_ch1", + &format_args!("{}", self.out_cmd_disable_ch1().bit()), + ) + .field( + "out_ecc_aec_en_ch1", + &format_args!("{}", self.out_ecc_aec_en_ch1().bit()), + ) + .field( + "outdscr_burst_en_ch1", + &format_args!("{}", self.outdscr_burst_en_ch1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer."] + #[inline(always)] + #[must_use] + pub fn out_rst_ch1(&mut self) -> OUT_RST_CH1_W { + OUT_RST_CH1_W::new(self, 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + #[must_use] + pub fn out_loop_test_ch1(&mut self) -> OUT_LOOP_TEST_CH1_W { + OUT_LOOP_TEST_CH1_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] + #[inline(always)] + #[must_use] + pub fn out_auto_wrback_ch1(&mut self) -> OUT_AUTO_WRBACK_CH1_W { + OUT_AUTO_WRBACK_CH1_W::new(self, 2) + } + #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] + #[inline(always)] + #[must_use] + pub fn out_eof_mode_ch1(&mut self) -> OUT_EOF_MODE_CH1_W { + OUT_EOF_MODE_CH1_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm task."] + #[inline(always)] + #[must_use] + pub fn out_etm_en_ch1(&mut self) -> OUT_ETM_EN_CH1_W { + OUT_ETM_EN_CH1_W::new(self, 4) + } + #[doc = "Bits 5:7 - 3'b000-3'b100:burst length 8byte~128byte"] + #[inline(always)] + #[must_use] + pub fn out_burst_size_sel_ch1(&mut self) -> OUT_BURST_SIZE_SEL_CH1_W { + OUT_BURST_SIZE_SEL_CH1_W::new(self, 5) + } + #[doc = "Bit 8 - 1:mean disable cmd of this ch1"] + #[inline(always)] + #[must_use] + pub fn out_cmd_disable_ch1(&mut self) -> OUT_CMD_DISABLE_CH1_W { + OUT_CMD_DISABLE_CH1_W::new(self, 8) + } + #[doc = "Bit 9 - 1: mean access ecc or aes domain,0: mean not"] + #[inline(always)] + #[must_use] + pub fn out_ecc_aec_en_ch1(&mut self) -> OUT_ECC_AEC_EN_CH1_W { + OUT_ECC_AEC_EN_CH1_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn outdscr_burst_en_ch1(&mut self) -> OUTDSCR_BURST_EN_CH1_W { + OUTDSCR_BURST_EN_CH1_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure 0 register of Tx channel1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF0_CH1_SPEC; +impl crate::RegisterSpec for OUT_CONF0_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf0_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_CONF0_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf0_ch1::W`](W) writer structure"] +impl crate::Writable for OUT_CONF0_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF0_CH1 to value 0x08"] +impl crate::Resettable for OUT_CONF0_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/axi_dma/out_conf0_ch2.rs b/esp32p4/src/axi_dma/out_conf0_ch2.rs new file mode 100644 index 0000000000..e1f6c63da8 --- /dev/null +++ b/esp32p4/src/axi_dma/out_conf0_ch2.rs @@ -0,0 +1,215 @@ +#[doc = "Register `OUT_CONF0_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF0_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_RST_CH2` reader - This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_CH2_R = crate::BitReader; +#[doc = "Field `OUT_RST_CH2` writer - This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_LOOP_TEST_CH2` reader - reserved"] +pub type OUT_LOOP_TEST_CH2_R = crate::BitReader; +#[doc = "Field `OUT_LOOP_TEST_CH2` writer - reserved"] +pub type OUT_LOOP_TEST_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_AUTO_WRBACK_CH2` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_CH2_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK_CH2` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] +pub type OUT_AUTO_WRBACK_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_MODE_CH2` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] +pub type OUT_EOF_MODE_CH2_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE_CH2` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] +pub type OUT_EOF_MODE_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ETM_EN_CH2` reader - Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm task."] +pub type OUT_ETM_EN_CH2_R = crate::BitReader; +#[doc = "Field `OUT_ETM_EN_CH2` writer - Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm task."] +pub type OUT_ETM_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_BURST_SIZE_SEL_CH2` reader - 3'b000-3'b100:burst length 8byte~128byte"] +pub type OUT_BURST_SIZE_SEL_CH2_R = crate::FieldReader; +#[doc = "Field `OUT_BURST_SIZE_SEL_CH2` writer - 3'b000-3'b100:burst length 8byte~128byte"] +pub type OUT_BURST_SIZE_SEL_CH2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OUT_CMD_DISABLE_CH2` reader - 1:mean disable cmd of this ch2"] +pub type OUT_CMD_DISABLE_CH2_R = crate::BitReader; +#[doc = "Field `OUT_CMD_DISABLE_CH2` writer - 1:mean disable cmd of this ch2"] +pub type OUT_CMD_DISABLE_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ECC_AEC_EN_CH2` reader - 1: mean access ecc or aes domain,0: mean not"] +pub type OUT_ECC_AEC_EN_CH2_R = crate::BitReader; +#[doc = "Field `OUT_ECC_AEC_EN_CH2` writer - 1: mean access ecc or aes domain,0: mean not"] +pub type OUT_ECC_AEC_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTDSCR_BURST_EN_CH2` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH2_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN_CH2` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer."] + #[inline(always)] + pub fn out_rst_ch2(&self) -> OUT_RST_CH2_R { + OUT_RST_CH2_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + pub fn out_loop_test_ch2(&self) -> OUT_LOOP_TEST_CH2_R { + OUT_LOOP_TEST_CH2_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] + #[inline(always)] + pub fn out_auto_wrback_ch2(&self) -> OUT_AUTO_WRBACK_CH2_R { + OUT_AUTO_WRBACK_CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] + #[inline(always)] + pub fn out_eof_mode_ch2(&self) -> OUT_EOF_MODE_CH2_R { + OUT_EOF_MODE_CH2_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm task."] + #[inline(always)] + pub fn out_etm_en_ch2(&self) -> OUT_ETM_EN_CH2_R { + OUT_ETM_EN_CH2_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - 3'b000-3'b100:burst length 8byte~128byte"] + #[inline(always)] + pub fn out_burst_size_sel_ch2(&self) -> OUT_BURST_SIZE_SEL_CH2_R { + OUT_BURST_SIZE_SEL_CH2_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 8 - 1:mean disable cmd of this ch2"] + #[inline(always)] + pub fn out_cmd_disable_ch2(&self) -> OUT_CMD_DISABLE_CH2_R { + OUT_CMD_DISABLE_CH2_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: mean access ecc or aes domain,0: mean not"] + #[inline(always)] + pub fn out_ecc_aec_en_ch2(&self) -> OUT_ECC_AEC_EN_CH2_R { + OUT_ECC_AEC_EN_CH2_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn outdscr_burst_en_ch2(&self) -> OUTDSCR_BURST_EN_CH2_R { + OUTDSCR_BURST_EN_CH2_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF0_CH2") + .field("out_rst_ch2", &format_args!("{}", self.out_rst_ch2().bit())) + .field( + "out_loop_test_ch2", + &format_args!("{}", self.out_loop_test_ch2().bit()), + ) + .field( + "out_auto_wrback_ch2", + &format_args!("{}", self.out_auto_wrback_ch2().bit()), + ) + .field( + "out_eof_mode_ch2", + &format_args!("{}", self.out_eof_mode_ch2().bit()), + ) + .field( + "out_etm_en_ch2", + &format_args!("{}", self.out_etm_en_ch2().bit()), + ) + .field( + "out_burst_size_sel_ch2", + &format_args!("{}", self.out_burst_size_sel_ch2().bits()), + ) + .field( + "out_cmd_disable_ch2", + &format_args!("{}", self.out_cmd_disable_ch2().bit()), + ) + .field( + "out_ecc_aec_en_ch2", + &format_args!("{}", self.out_ecc_aec_en_ch2().bit()), + ) + .field( + "outdscr_burst_en_ch2", + &format_args!("{}", self.outdscr_burst_en_ch2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer."] + #[inline(always)] + #[must_use] + pub fn out_rst_ch2(&mut self) -> OUT_RST_CH2_W { + OUT_RST_CH2_W::new(self, 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + #[must_use] + pub fn out_loop_test_ch2(&mut self) -> OUT_LOOP_TEST_CH2_W { + OUT_LOOP_TEST_CH2_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."] + #[inline(always)] + #[must_use] + pub fn out_auto_wrback_ch2(&mut self) -> OUT_AUTO_WRBACK_CH2_W { + OUT_AUTO_WRBACK_CH2_W::new(self, 2) + } + #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is generated when data need to transmit has been popped from FIFO in AXI_DMA"] + #[inline(always)] + #[must_use] + pub fn out_eof_mode_ch2(&mut self) -> OUT_EOF_MODE_CH2_W { + OUT_EOF_MODE_CH2_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm task."] + #[inline(always)] + #[must_use] + pub fn out_etm_en_ch2(&mut self) -> OUT_ETM_EN_CH2_W { + OUT_ETM_EN_CH2_W::new(self, 4) + } + #[doc = "Bits 5:7 - 3'b000-3'b100:burst length 8byte~128byte"] + #[inline(always)] + #[must_use] + pub fn out_burst_size_sel_ch2(&mut self) -> OUT_BURST_SIZE_SEL_CH2_W { + OUT_BURST_SIZE_SEL_CH2_W::new(self, 5) + } + #[doc = "Bit 8 - 1:mean disable cmd of this ch2"] + #[inline(always)] + #[must_use] + pub fn out_cmd_disable_ch2(&mut self) -> OUT_CMD_DISABLE_CH2_W { + OUT_CMD_DISABLE_CH2_W::new(self, 8) + } + #[doc = "Bit 9 - 1: mean access ecc or aes domain,0: mean not"] + #[inline(always)] + #[must_use] + pub fn out_ecc_aec_en_ch2(&mut self) -> OUT_ECC_AEC_EN_CH2_W { + OUT_ECC_AEC_EN_CH2_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn outdscr_burst_en_ch2(&mut self) -> OUTDSCR_BURST_EN_CH2_W { + OUTDSCR_BURST_EN_CH2_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure 0 register of Tx channel2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF0_CH2_SPEC; +impl crate::RegisterSpec for OUT_CONF0_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf0_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_CONF0_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf0_ch2::W`](W) writer structure"] +impl crate::Writable for OUT_CONF0_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF0_CH2 to value 0x08"] +impl crate::Resettable for OUT_CONF0_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/axi_dma/out_conf1_ch.rs b/esp32p4/src/axi_dma/out_conf1_ch.rs new file mode 100644 index 0000000000..0cebb25e47 --- /dev/null +++ b/esp32p4/src/axi_dma/out_conf1_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_CONF1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF1_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_CHECK_OWNER_CH` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER_CH` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn out_check_owner_ch(&self) -> OUT_CHECK_OWNER_CH_R { + OUT_CHECK_OWNER_CH_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF1_CH") + .field( + "out_check_owner_ch", + &format_args!("{}", self.out_check_owner_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn out_check_owner_ch(&mut self) -> OUT_CHECK_OWNER_CH_W { + OUT_CHECK_OWNER_CH_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure 1 register of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf1_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf1_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF1_CH_SPEC; +impl crate::RegisterSpec for OUT_CONF1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf1_ch::R`](R) reader structure"] +impl crate::Readable for OUT_CONF1_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf1_ch::W`](W) writer structure"] +impl crate::Writable for OUT_CONF1_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF1_CH%s to value 0"] +impl crate::Resettable for OUT_CONF1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_crc_clear_ch.rs b/esp32p4/src/axi_dma/out_crc_clear_ch.rs new file mode 100644 index 0000000000..b4120a9aea --- /dev/null +++ b/esp32p4/src/axi_dma/out_crc_clear_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_CRC_CLEAR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CRC_CLEAR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_CRC_CLEAR_CH` reader - This register is used to clear ch0 of tx crc result"] +pub type OUT_CRC_CLEAR_CH_R = crate::BitReader; +#[doc = "Field `OUT_CRC_CLEAR_CH` writer - This register is used to clear ch0 of tx crc result"] +pub type OUT_CRC_CLEAR_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This register is used to clear ch0 of tx crc result"] + #[inline(always)] + pub fn out_crc_clear_ch(&self) -> OUT_CRC_CLEAR_CH_R { + OUT_CRC_CLEAR_CH_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CRC_CLEAR_CH") + .field( + "out_crc_clear_ch", + &format_args!("{}", self.out_crc_clear_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This register is used to clear ch0 of tx crc result"] + #[inline(always)] + #[must_use] + pub fn out_crc_clear_ch(&mut self) -> OUT_CRC_CLEAR_CH_W { + OUT_CRC_CLEAR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to clear ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_clear_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_crc_clear_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CRC_CLEAR_CH_SPEC; +impl crate::RegisterSpec for OUT_CRC_CLEAR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_crc_clear_ch::R`](R) reader structure"] +impl crate::Readable for OUT_CRC_CLEAR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_crc_clear_ch::W`](W) writer structure"] +impl crate::Writable for OUT_CRC_CLEAR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CRC_CLEAR_CH%s to value 0"] +impl crate::Resettable for OUT_CRC_CLEAR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_crc_final_result_ch.rs b/esp32p4/src/axi_dma/out_crc_final_result_ch.rs new file mode 100644 index 0000000000..6587c37565 --- /dev/null +++ b/esp32p4/src/axi_dma/out_crc_final_result_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_CRC_FINAL_RESULT_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CRC_FINAL_RESULT_CH` reader - This register is used to store result ch0 of tx"] +pub type OUT_CRC_FINAL_RESULT_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register is used to store result ch0 of tx"] + #[inline(always)] + pub fn out_crc_final_result_ch(&self) -> OUT_CRC_FINAL_RESULT_CH_R { + OUT_CRC_FINAL_RESULT_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CRC_FINAL_RESULT_CH") + .field( + "out_crc_final_result_ch", + &format_args!("{}", self.out_crc_final_result_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_final_result_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CRC_FINAL_RESULT_CH_SPEC; +impl crate::RegisterSpec for OUT_CRC_FINAL_RESULT_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_crc_final_result_ch::R`](R) reader structure"] +impl crate::Readable for OUT_CRC_FINAL_RESULT_CH_SPEC {} +#[doc = "`reset()` method sets OUT_CRC_FINAL_RESULT_CH%s to value 0"] +impl crate::Resettable for OUT_CRC_FINAL_RESULT_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_crc_init_data_ch.rs b/esp32p4/src/axi_dma/out_crc_init_data_ch.rs new file mode 100644 index 0000000000..780dd55dd3 --- /dev/null +++ b/esp32p4/src/axi_dma/out_crc_init_data_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_CRC_INIT_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CRC_INIT_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_CRC_INIT_DATA_CH` reader - This register is used to config ch0 of tx crc initial value"] +pub type OUT_CRC_INIT_DATA_CH_R = crate::FieldReader; +#[doc = "Field `OUT_CRC_INIT_DATA_CH` writer - This register is used to config ch0 of tx crc initial value"] +pub type OUT_CRC_INIT_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is used to config ch0 of tx crc initial value"] + #[inline(always)] + pub fn out_crc_init_data_ch(&self) -> OUT_CRC_INIT_DATA_CH_R { + OUT_CRC_INIT_DATA_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CRC_INIT_DATA_CH") + .field( + "out_crc_init_data_ch", + &format_args!("{}", self.out_crc_init_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register is used to config ch0 of tx crc initial value"] + #[inline(always)] + #[must_use] + pub fn out_crc_init_data_ch(&mut self) -> OUT_CRC_INIT_DATA_CH_W { + OUT_CRC_INIT_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config ch0 crc initial data(max 32 bit)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_init_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_crc_init_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CRC_INIT_DATA_CH_SPEC; +impl crate::RegisterSpec for OUT_CRC_INIT_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_crc_init_data_ch::R`](R) reader structure"] +impl crate::Readable for OUT_CRC_INIT_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_crc_init_data_ch::W`](W) writer structure"] +impl crate::Writable for OUT_CRC_INIT_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CRC_INIT_DATA_CH%s to value 0xffff_ffff"] +impl crate::Resettable for OUT_CRC_INIT_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/axi_dma/out_dscr_bf0_ch.rs b/esp32p4/src/axi_dma/out_dscr_bf0_ch.rs new file mode 100644 index 0000000000..fcff80d389 --- /dev/null +++ b/esp32p4/src/axi_dma/out_dscr_bf0_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF0_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF0_CH` reader - The address of the last outlink descriptor y-1."] +pub type OUTLINK_DSCR_BF0_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last outlink descriptor y-1."] + #[inline(always)] + pub fn outlink_dscr_bf0_ch(&self) -> OUTLINK_DSCR_BF0_CH_R { + OUTLINK_DSCR_BF0_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF0_CH") + .field( + "outlink_dscr_bf0_ch", + &format_args!("{}", self.outlink_dscr_bf0_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The last outlink descriptor address of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF0_CH_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF0_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf0_ch::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF0_CH_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF0_CH%s to value 0"] +impl crate::Resettable for OUT_DSCR_BF0_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_dscr_bf1_ch.rs b/esp32p4/src/axi_dma/out_dscr_bf1_ch.rs new file mode 100644 index 0000000000..abf37398f8 --- /dev/null +++ b/esp32p4/src/axi_dma/out_dscr_bf1_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF1_CH` reader - The address of the second-to-last outlink descriptor x-2."] +pub type OUTLINK_DSCR_BF1_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last outlink descriptor x-2."] + #[inline(always)] + pub fn outlink_dscr_bf1_ch(&self) -> OUTLINK_DSCR_BF1_CH_R { + OUTLINK_DSCR_BF1_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF1_CH") + .field( + "outlink_dscr_bf1_ch", + &format_args!("{}", self.outlink_dscr_bf1_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The second-to-last outlink descriptor address of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF1_CH_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf1_ch::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF1_CH_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF1_CH%s to value 0"] +impl crate::Resettable for OUT_DSCR_BF1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_dscr_ch.rs b/esp32p4/src/axi_dma/out_dscr_ch.rs new file mode 100644 index 0000000000..7dac03403d --- /dev/null +++ b/esp32p4/src/axi_dma/out_dscr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_CH` reader - The address of the current outlink descriptor y."] +pub type OUTLINK_DSCR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the current outlink descriptor y."] + #[inline(always)] + pub fn outlink_dscr_ch(&self) -> OUTLINK_DSCR_CH_R { + OUTLINK_DSCR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_CH") + .field( + "outlink_dscr_ch", + &format_args!("{}", self.outlink_dscr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Current outlink descriptor address of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_CH_SPEC; +impl crate::RegisterSpec for OUT_DSCR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_ch::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_CH_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_CH%s to value 0"] +impl crate::Resettable for OUT_DSCR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_eof_bfr_des_addr_ch.rs b/esp32p4/src/axi_dma/out_eof_bfr_des_addr_ch.rs new file mode 100644 index 0000000000..a47b5559ce --- /dev/null +++ b/esp32p4/src/axi_dma/out_eof_bfr_des_addr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_EOF_BFR_DES_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_BFR_DES_ADDR_CH` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."] +pub type OUT_EOF_BFR_DES_ADDR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor before the last outlink descriptor."] + #[inline(always)] + pub fn out_eof_bfr_des_addr_ch(&self) -> OUT_EOF_BFR_DES_ADDR_CH_R { + OUT_EOF_BFR_DES_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_BFR_DES_ADDR_CH") + .field( + "out_eof_bfr_des_addr_ch", + &format_args!("{}", self.out_eof_bfr_des_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The last outlink descriptor address when EOF occurs of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_BFR_DES_ADDR_CH_SPEC; +impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_bfr_des_addr_ch::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_BFR_DES_ADDR_CH_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_BFR_DES_ADDR_CH%s to value 0"] +impl crate::Resettable for OUT_EOF_BFR_DES_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_eof_des_addr_ch.rs b/esp32p4/src/axi_dma/out_eof_des_addr_ch.rs new file mode 100644 index 0000000000..599788a359 --- /dev/null +++ b/esp32p4/src/axi_dma/out_eof_des_addr_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_EOF_DES_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_DES_ADDR_CH` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn out_eof_des_addr_ch(&self) -> OUT_EOF_DES_ADDR_CH_R { + OUT_EOF_DES_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_DES_ADDR_CH") + .field( + "out_eof_des_addr_ch", + &format_args!("{}", self.out_eof_des_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Outlink descriptor address when EOF occurs of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_DES_ADDR_CH_SPEC; +impl crate::RegisterSpec for OUT_EOF_DES_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_des_addr_ch::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_DES_ADDR_CH_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_DES_ADDR_CH%s to value 0"] +impl crate::Resettable for OUT_EOF_DES_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_int_clr_ch.rs b/esp32p4/src/axi_dma/out_int_clr_ch.rs new file mode 100644 index 0000000000..60d9ad995b --- /dev/null +++ b/esp32p4/src/axi_dma/out_int_clr_ch.rs @@ -0,0 +1,126 @@ +#[doc = "Register `OUT_INT_CLR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L1_OVF_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_L1_OVF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L1_UDF_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_L1_UDF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L2_OVF_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_L2_OVF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L2_UDF_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_L2_UDF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L3_OVF_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."] +pub type OUTFIFO_L3_OVF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L3_UDF_CH_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."] +pub type OUTFIFO_L3_UDF_CH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch_int_clr(&mut self) -> OUT_DONE_CH_INT_CLR_W { + OUT_DONE_CH_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch_int_clr(&mut self) -> OUT_EOF_CH_INT_CLR_W { + OUT_EOF_CH_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch_int_clr(&mut self) -> OUT_DSCR_ERR_CH_INT_CLR_W { + OUT_DSCR_ERR_CH_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch_int_clr(&mut self) -> OUT_TOTAL_EOF_CH_INT_CLR_W { + OUT_TOTAL_EOF_CH_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l1_ovf_ch_int_clr( + &mut self, + ) -> OUTFIFO_L1_OVF_CH_INT_CLR_W { + OUTFIFO_L1_OVF_CH_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l1_udf_ch_int_clr( + &mut self, + ) -> OUTFIFO_L1_UDF_CH_INT_CLR_W { + OUTFIFO_L1_UDF_CH_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l2_ovf_ch_int_clr( + &mut self, + ) -> OUTFIFO_L2_OVF_CH_INT_CLR_W { + OUTFIFO_L2_OVF_CH_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l2_udf_ch_int_clr( + &mut self, + ) -> OUTFIFO_L2_UDF_CH_INT_CLR_W { + OUTFIFO_L2_UDF_CH_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l3_ovf_ch_int_clr( + &mut self, + ) -> OUTFIFO_L3_OVF_CH_INT_CLR_W { + OUTFIFO_L3_OVF_CH_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l3_udf_ch_int_clr( + &mut self, + ) -> OUTFIFO_L3_UDF_CH_INT_CLR_W { + OUTFIFO_L3_UDF_CH_INT_CLR_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear bits of channel0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_CLR_CH_SPEC; +impl crate::RegisterSpec for OUT_INT_CLR_CH_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out_int_clr_ch::W`](W) writer structure"] +impl crate::Writable for OUT_INT_CLR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_CLR_CH%s to value 0"] +impl crate::Resettable for OUT_INT_CLR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_int_ena_ch.rs b/esp32p4/src/axi_dma/out_int_ena_ch.rs new file mode 100644 index 0000000000..f02085be6f --- /dev/null +++ b/esp32p4/src/axi_dma/out_int_ena_ch.rs @@ -0,0 +1,249 @@ +#[doc = "Register `OUT_INT_ENA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_ENA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L1_OVF_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_L1_OVF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L1_OVF_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_L1_OVF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L1_UDF_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_L1_UDF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L1_UDF_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_L1_UDF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L2_OVF_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_L2_OVF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L2_OVF_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_L2_OVF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L2_UDF_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_L2_UDF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L2_UDF_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_L2_UDF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L3_OVF_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] +pub type OUTFIFO_L3_OVF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L3_OVF_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] +pub type OUTFIFO_L3_OVF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L3_UDF_CH_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] +pub type OUTFIFO_L3_UDF_CH_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L3_UDF_CH_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] +pub type OUTFIFO_L3_UDF_CH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch_int_ena(&self) -> OUT_DONE_CH_INT_ENA_R { + OUT_DONE_CH_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch_int_ena(&self) -> OUT_EOF_CH_INT_ENA_R { + OUT_EOF_CH_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch_int_ena(&self) -> OUT_DSCR_ERR_CH_INT_ENA_R { + OUT_DSCR_ERR_CH_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch_int_ena(&self) -> OUT_TOTAL_EOF_CH_INT_ENA_R { + OUT_TOTAL_EOF_CH_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_l1_ovf_ch_int_ena(&self) -> OUTFIFO_L1_OVF_CH_INT_ENA_R { + OUTFIFO_L1_OVF_CH_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_l1_udf_ch_int_ena(&self) -> OUTFIFO_L1_UDF_CH_INT_ENA_R { + OUTFIFO_L1_UDF_CH_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_l2_ovf_ch_int_ena(&self) -> OUTFIFO_L2_OVF_CH_INT_ENA_R { + OUTFIFO_L2_OVF_CH_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_l2_udf_ch_int_ena(&self) -> OUTFIFO_L2_UDF_CH_INT_ENA_R { + OUTFIFO_L2_UDF_CH_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_l3_ovf_ch_int_ena(&self) -> OUTFIFO_L3_OVF_CH_INT_ENA_R { + OUTFIFO_L3_OVF_CH_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_l3_udf_ch_int_ena(&self) -> OUTFIFO_L3_UDF_CH_INT_ENA_R { + OUTFIFO_L3_UDF_CH_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ENA_CH") + .field( + "out_done_ch_int_ena", + &format_args!("{}", self.out_done_ch_int_ena().bit()), + ) + .field( + "out_eof_ch_int_ena", + &format_args!("{}", self.out_eof_ch_int_ena().bit()), + ) + .field( + "out_dscr_err_ch_int_ena", + &format_args!("{}", self.out_dscr_err_ch_int_ena().bit()), + ) + .field( + "out_total_eof_ch_int_ena", + &format_args!("{}", self.out_total_eof_ch_int_ena().bit()), + ) + .field( + "outfifo_l1_ovf_ch_int_ena", + &format_args!("{}", self.outfifo_l1_ovf_ch_int_ena().bit()), + ) + .field( + "outfifo_l1_udf_ch_int_ena", + &format_args!("{}", self.outfifo_l1_udf_ch_int_ena().bit()), + ) + .field( + "outfifo_l2_ovf_ch_int_ena", + &format_args!("{}", self.outfifo_l2_ovf_ch_int_ena().bit()), + ) + .field( + "outfifo_l2_udf_ch_int_ena", + &format_args!("{}", self.outfifo_l2_udf_ch_int_ena().bit()), + ) + .field( + "outfifo_l3_ovf_ch_int_ena", + &format_args!("{}", self.outfifo_l3_ovf_ch_int_ena().bit()), + ) + .field( + "outfifo_l3_udf_ch_int_ena", + &format_args!("{}", self.outfifo_l3_udf_ch_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch_int_ena(&mut self) -> OUT_DONE_CH_INT_ENA_W { + OUT_DONE_CH_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch_int_ena(&mut self) -> OUT_EOF_CH_INT_ENA_W { + OUT_EOF_CH_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch_int_ena(&mut self) -> OUT_DSCR_ERR_CH_INT_ENA_W { + OUT_DSCR_ERR_CH_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch_int_ena(&mut self) -> OUT_TOTAL_EOF_CH_INT_ENA_W { + OUT_TOTAL_EOF_CH_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l1_ovf_ch_int_ena( + &mut self, + ) -> OUTFIFO_L1_OVF_CH_INT_ENA_W { + OUTFIFO_L1_OVF_CH_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l1_udf_ch_int_ena( + &mut self, + ) -> OUTFIFO_L1_UDF_CH_INT_ENA_W { + OUTFIFO_L1_UDF_CH_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l2_ovf_ch_int_ena( + &mut self, + ) -> OUTFIFO_L2_OVF_CH_INT_ENA_W { + OUTFIFO_L2_OVF_CH_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l2_udf_ch_int_ena( + &mut self, + ) -> OUTFIFO_L2_UDF_CH_INT_ENA_W { + OUTFIFO_L2_UDF_CH_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l3_ovf_ch_int_ena( + &mut self, + ) -> OUTFIFO_L3_OVF_CH_INT_ENA_W { + OUTFIFO_L3_OVF_CH_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_l3_udf_ch_int_ena( + &mut self, + ) -> OUTFIFO_L3_UDF_CH_INT_ENA_W { + OUTFIFO_L3_UDF_CH_INT_ENA_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable bits of channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ENA_CH_SPEC; +impl crate::RegisterSpec for OUT_INT_ENA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_ena_ch::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ENA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_ena_ch::W`](W) writer structure"] +impl crate::Writable for OUT_INT_ENA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_ENA_CH%s to value 0"] +impl crate::Resettable for OUT_INT_ENA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_int_raw_ch.rs b/esp32p4/src/axi_dma/out_int_raw_ch.rs new file mode 100644 index 0000000000..5da36fc7de --- /dev/null +++ b/esp32p4/src/axi_dma/out_int_raw_ch.rs @@ -0,0 +1,249 @@ +#[doc = "Register `OUT_INT_RAW_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_RAW_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0."] +pub type OUT_DONE_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0."] +pub type OUT_DONE_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel0."] +pub type OUT_EOF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel0."] +pub type OUT_EOF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel0."] +pub type OUT_DSCR_ERR_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_RAW` writer - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel0."] +pub type OUT_DSCR_ERR_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel0."] +pub type OUT_TOTAL_EOF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_RAW` writer - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel0."] +pub type OUT_TOTAL_EOF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L1_OVF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] +pub type OUTFIFO_L1_OVF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L1_OVF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] +pub type OUTFIFO_L1_OVF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L1_UDF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] +pub type OUTFIFO_L1_UDF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L1_UDF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] +pub type OUTFIFO_L1_UDF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L2_OVF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] +pub type OUTFIFO_L2_OVF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L2_OVF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] +pub type OUTFIFO_L2_OVF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L2_UDF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] +pub type OUTFIFO_L2_UDF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L2_UDF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] +pub type OUTFIFO_L2_UDF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L3_OVF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] +pub type OUTFIFO_L3_OVF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L3_OVF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] +pub type OUTFIFO_L3_OVF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_L3_UDF_CH_INT_RAW` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] +pub type OUTFIFO_L3_UDF_CH_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L3_UDF_CH_INT_RAW` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] +pub type OUTFIFO_L3_UDF_CH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0."] + #[inline(always)] + pub fn out_done_ch_int_raw(&self) -> OUT_DONE_CH_INT_RAW_R { + OUT_DONE_CH_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel0."] + #[inline(always)] + pub fn out_eof_ch_int_raw(&self) -> OUT_EOF_CH_INT_RAW_R { + OUT_EOF_CH_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel0."] + #[inline(always)] + pub fn out_dscr_err_ch_int_raw(&self) -> OUT_DSCR_ERR_CH_INT_RAW_R { + OUT_DSCR_ERR_CH_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel0."] + #[inline(always)] + pub fn out_total_eof_ch_int_raw(&self) -> OUT_TOTAL_EOF_CH_INT_RAW_R { + OUT_TOTAL_EOF_CH_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] + #[inline(always)] + pub fn outfifo_l1_ovf_ch_int_raw(&self) -> OUTFIFO_L1_OVF_CH_INT_RAW_R { + OUTFIFO_L1_OVF_CH_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] + #[inline(always)] + pub fn outfifo_l1_udf_ch_int_raw(&self) -> OUTFIFO_L1_UDF_CH_INT_RAW_R { + OUTFIFO_L1_UDF_CH_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] + #[inline(always)] + pub fn outfifo_l2_ovf_ch_int_raw(&self) -> OUTFIFO_L2_OVF_CH_INT_RAW_R { + OUTFIFO_L2_OVF_CH_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] + #[inline(always)] + pub fn outfifo_l2_udf_ch_int_raw(&self) -> OUTFIFO_L2_UDF_CH_INT_RAW_R { + OUTFIFO_L2_UDF_CH_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] + #[inline(always)] + pub fn outfifo_l3_ovf_ch_int_raw(&self) -> OUTFIFO_L3_OVF_CH_INT_RAW_R { + OUTFIFO_L3_OVF_CH_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] + #[inline(always)] + pub fn outfifo_l3_udf_ch_int_raw(&self) -> OUTFIFO_L3_UDF_CH_INT_RAW_R { + OUTFIFO_L3_UDF_CH_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_RAW_CH") + .field( + "out_done_ch_int_raw", + &format_args!("{}", self.out_done_ch_int_raw().bit()), + ) + .field( + "out_eof_ch_int_raw", + &format_args!("{}", self.out_eof_ch_int_raw().bit()), + ) + .field( + "out_dscr_err_ch_int_raw", + &format_args!("{}", self.out_dscr_err_ch_int_raw().bit()), + ) + .field( + "out_total_eof_ch_int_raw", + &format_args!("{}", self.out_total_eof_ch_int_raw().bit()), + ) + .field( + "outfifo_l1_ovf_ch_int_raw", + &format_args!("{}", self.outfifo_l1_ovf_ch_int_raw().bit()), + ) + .field( + "outfifo_l1_udf_ch_int_raw", + &format_args!("{}", self.outfifo_l1_udf_ch_int_raw().bit()), + ) + .field( + "outfifo_l2_ovf_ch_int_raw", + &format_args!("{}", self.outfifo_l2_ovf_ch_int_raw().bit()), + ) + .field( + "outfifo_l2_udf_ch_int_raw", + &format_args!("{}", self.outfifo_l2_udf_ch_int_raw().bit()), + ) + .field( + "outfifo_l3_ovf_ch_int_raw", + &format_args!("{}", self.outfifo_l3_ovf_ch_int_raw().bit()), + ) + .field( + "outfifo_l3_udf_ch_int_raw", + &format_args!("{}", self.outfifo_l3_udf_ch_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0."] + #[inline(always)] + #[must_use] + pub fn out_done_ch_int_raw(&mut self) -> OUT_DONE_CH_INT_RAW_W { + OUT_DONE_CH_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel0."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch_int_raw(&mut self) -> OUT_EOF_CH_INT_RAW_W { + OUT_EOF_CH_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel0."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch_int_raw(&mut self) -> OUT_DSCR_ERR_CH_INT_RAW_W { + OUT_DSCR_ERR_CH_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel0."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch_int_raw(&mut self) -> OUT_TOTAL_EOF_CH_INT_RAW_W { + OUT_TOTAL_EOF_CH_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_l1_ovf_ch_int_raw( + &mut self, + ) -> OUTFIFO_L1_OVF_CH_INT_RAW_W { + OUTFIFO_L1_OVF_CH_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_l1_udf_ch_int_raw( + &mut self, + ) -> OUTFIFO_L1_UDF_CH_INT_RAW_W { + OUTFIFO_L1_UDF_CH_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_l2_ovf_ch_int_raw( + &mut self, + ) -> OUTFIFO_L2_OVF_CH_INT_RAW_W { + OUTFIFO_L2_OVF_CH_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_l2_udf_ch_int_raw( + &mut self, + ) -> OUTFIFO_L2_UDF_CH_INT_RAW_W { + OUTFIFO_L2_UDF_CH_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_l3_ovf_ch_int_raw( + &mut self, + ) -> OUTFIFO_L3_OVF_CH_INT_RAW_W { + OUTFIFO_L3_OVF_CH_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_l3_udf_ch_int_raw( + &mut self, + ) -> OUTFIFO_L3_UDF_CH_INT_RAW_W { + OUTFIFO_L3_UDF_CH_INT_RAW_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Raw status interrupt of channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_RAW_CH_SPEC; +impl crate::RegisterSpec for OUT_INT_RAW_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_raw_ch::R`](R) reader structure"] +impl crate::Readable for OUT_INT_RAW_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_raw_ch::W`](W) writer structure"] +impl crate::Writable for OUT_INT_RAW_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_RAW_CH%s to value 0"] +impl crate::Resettable for OUT_INT_RAW_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_int_st_ch.rs b/esp32p4/src/axi_dma/out_int_st_ch.rs new file mode 100644 index 0000000000..01e4657eb7 --- /dev/null +++ b/esp32p4/src/axi_dma/out_int_st_ch.rs @@ -0,0 +1,138 @@ +#[doc = "Register `OUT_INT_ST_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_DONE_CH_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L1_OVF_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_L1_OVF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L1_UDF_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_L1_UDF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L3_OVF_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] +pub type OUTFIFO_L3_OVF_CH_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L3_UDF_CH_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] +pub type OUTFIFO_L3_UDF_CH_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch_int_st(&self) -> OUT_DONE_CH_INT_ST_R { + OUT_DONE_CH_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch_int_st(&self) -> OUT_EOF_CH_INT_ST_R { + OUT_EOF_CH_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch_int_st(&self) -> OUT_DSCR_ERR_CH_INT_ST_R { + OUT_DSCR_ERR_CH_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch_int_st(&self) -> OUT_TOTAL_EOF_CH_INT_ST_R { + OUT_TOTAL_EOF_CH_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_ch_int_st(&self) -> OUTFIFO_OVF_CH_INT_ST_R { + OUTFIFO_OVF_CH_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_ch_int_st(&self) -> OUTFIFO_UDF_CH_INT_ST_R { + OUTFIFO_UDF_CH_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_l1_ovf_ch_int_st(&self) -> OUTFIFO_L1_OVF_CH_INT_ST_R { + OUTFIFO_L1_OVF_CH_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_l1_udf_ch_int_st(&self) -> OUTFIFO_L1_UDF_CH_INT_ST_R { + OUTFIFO_L1_UDF_CH_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_l3_ovf_ch_int_st(&self) -> OUTFIFO_L3_OVF_CH_INT_ST_R { + OUTFIFO_L3_OVF_CH_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_l3_udf_ch_int_st(&self) -> OUTFIFO_L3_UDF_CH_INT_ST_R { + OUTFIFO_L3_UDF_CH_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ST_CH") + .field( + "out_done_ch_int_st", + &format_args!("{}", self.out_done_ch_int_st().bit()), + ) + .field( + "out_eof_ch_int_st", + &format_args!("{}", self.out_eof_ch_int_st().bit()), + ) + .field( + "out_dscr_err_ch_int_st", + &format_args!("{}", self.out_dscr_err_ch_int_st().bit()), + ) + .field( + "out_total_eof_ch_int_st", + &format_args!("{}", self.out_total_eof_ch_int_st().bit()), + ) + .field( + "outfifo_ovf_ch_int_st", + &format_args!("{}", self.outfifo_ovf_ch_int_st().bit()), + ) + .field( + "outfifo_udf_ch_int_st", + &format_args!("{}", self.outfifo_udf_ch_int_st().bit()), + ) + .field( + "outfifo_l1_ovf_ch_int_st", + &format_args!("{}", self.outfifo_l1_ovf_ch_int_st().bit()), + ) + .field( + "outfifo_l1_udf_ch_int_st", + &format_args!("{}", self.outfifo_l1_udf_ch_int_st().bit()), + ) + .field( + "outfifo_l3_ovf_ch_int_st", + &format_args!("{}", self.outfifo_l3_ovf_ch_int_st().bit()), + ) + .field( + "outfifo_l3_udf_ch_int_st", + &format_args!("{}", self.outfifo_l3_udf_ch_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Masked interrupt of channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ST_CH_SPEC; +impl crate::RegisterSpec for OUT_INT_ST_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_st_ch::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ST_CH_SPEC {} +#[doc = "`reset()` method sets OUT_INT_ST_CH%s to value 0"] +impl crate::Resettable for OUT_INT_ST_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_link1_ch.rs b/esp32p4/src/axi_dma/out_link1_ch.rs new file mode 100644 index 0000000000..706e16f612 --- /dev/null +++ b/esp32p4/src/axi_dma/out_link1_ch.rs @@ -0,0 +1,82 @@ +#[doc = "Register `OUT_LINK1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK1_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_STOP_CH` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_START_CH` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_RESTART_CH` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_PARK_CH` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_CH_R = crate::BitReader; +impl R { + #[doc = "Bit 3 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] + #[inline(always)] + pub fn outlink_park_ch(&self) -> OUTLINK_PARK_CH_R { + OUTLINK_PARK_CH_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK1_CH") + .field( + "outlink_park_ch", + &format_args!("{}", self.outlink_park_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_stop_ch(&mut self) -> OUTLINK_STOP_CH_W { + OUTLINK_STOP_CH_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_start_ch(&mut self) -> OUTLINK_START_CH_W { + OUTLINK_START_CH_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + #[must_use] + pub fn outlink_restart_ch(&mut self) -> OUTLINK_RESTART_CH_W { + OUTLINK_RESTART_CH_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link descriptor configure and control register of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link1_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link1_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK1_CH_SPEC; +impl crate::RegisterSpec for OUT_LINK1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link1_ch::R`](R) reader structure"] +impl crate::Readable for OUT_LINK1_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link1_ch::W`](W) writer structure"] +impl crate::Writable for OUT_LINK1_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK1_CH%s to value 0x08"] +impl crate::Resettable for OUT_LINK1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/axi_dma/out_link2_ch.rs b/esp32p4/src/axi_dma/out_link2_ch.rs new file mode 100644 index 0000000000..abdfd122d3 --- /dev/null +++ b/esp32p4/src/axi_dma/out_link2_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_LINK2_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK2_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_ADDR_CH` reader - This register stores the 32 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR_CH` writer - This register stores the 32 least significant bits of the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the 32 least significant bits of the first outlink descriptor's address."] + #[inline(always)] + pub fn outlink_addr_ch(&self) -> OUTLINK_ADDR_CH_R { + OUTLINK_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK2_CH") + .field( + "outlink_addr_ch", + &format_args!("{}", self.outlink_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the 32 least significant bits of the first outlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn outlink_addr_ch(&mut self) -> OUTLINK_ADDR_CH_W { + OUTLINK_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link descriptor configure and control register of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link2_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link2_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK2_CH_SPEC; +impl crate::RegisterSpec for OUT_LINK2_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link2_ch::R`](R) reader structure"] +impl crate::Readable for OUT_LINK2_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link2_ch::W`](W) writer structure"] +impl crate::Writable for OUT_LINK2_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK2_CH%s to value 0"] +impl crate::Resettable for OUT_LINK2_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_peri_sel_ch.rs b/esp32p4/src/axi_dma/out_peri_sel_ch.rs new file mode 100644 index 0000000000..796c932da5 --- /dev/null +++ b/esp32p4/src/axi_dma/out_peri_sel_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_PERI_SEL_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_PERI_SEL_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `PERI_OUT_SEL_CH` reader - This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy"] +pub type PERI_OUT_SEL_CH_R = crate::FieldReader; +#[doc = "Field `PERI_OUT_SEL_CH` writer - This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy"] +pub type PERI_OUT_SEL_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy"] + #[inline(always)] + pub fn peri_out_sel_ch(&self) -> PERI_OUT_SEL_CH_R { + PERI_OUT_SEL_CH_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PERI_SEL_CH") + .field( + "peri_out_sel_ch", + &format_args!("{}", self.peri_out_sel_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy"] + #[inline(always)] + #[must_use] + pub fn peri_out_sel_ch(&mut self) -> PERI_OUT_SEL_CH_W { + PERI_OUT_SEL_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Peripheral selection of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_peri_sel_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_peri_sel_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PERI_SEL_CH_SPEC; +impl crate::RegisterSpec for OUT_PERI_SEL_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_peri_sel_ch::R`](R) reader structure"] +impl crate::Readable for OUT_PERI_SEL_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_peri_sel_ch::W`](W) writer structure"] +impl crate::Writable for OUT_PERI_SEL_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_PERI_SEL_CH%s to value 0x3f"] +impl crate::Resettable for OUT_PERI_SEL_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/axi_dma/out_pri_ch.rs b/esp32p4/src/axi_dma/out_pri_ch.rs new file mode 100644 index 0000000000..4d005529b8 --- /dev/null +++ b/esp32p4/src/axi_dma/out_pri_ch.rs @@ -0,0 +1,101 @@ +#[doc = "Register `OUT_PRI_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_PRI_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_PRI_CH` reader - The priority of Tx channel0. The larger of the value the higher of the priority."] +pub type TX_PRI_CH_R = crate::FieldReader; +#[doc = "Field `TX_PRI_CH` writer - The priority of Tx channel0. The larger of the value the higher of the priority."] +pub type TX_PRI_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TX_CH_ARB_WEIGH_CH` reader - The weight of Tx channel0"] +pub type TX_CH_ARB_WEIGH_CH_R = crate::FieldReader; +#[doc = "Field `TX_CH_ARB_WEIGH_CH` writer - The weight of Tx channel0"] +pub type TX_CH_ARB_WEIGH_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TX_ARB_WEIGH_OPT_DIR_CH` reader - 0: mean not optimazation weight function ,1: mean optimazation"] +pub type TX_ARB_WEIGH_OPT_DIR_CH_R = crate::BitReader; +#[doc = "Field `TX_ARB_WEIGH_OPT_DIR_CH` writer - 0: mean not optimazation weight function ,1: mean optimazation"] +pub type TX_ARB_WEIGH_OPT_DIR_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - The priority of Tx channel0. The larger of the value the higher of the priority."] + #[inline(always)] + pub fn tx_pri_ch(&self) -> TX_PRI_CH_R { + TX_PRI_CH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - The weight of Tx channel0"] + #[inline(always)] + pub fn tx_ch_arb_weigh_ch(&self) -> TX_CH_ARB_WEIGH_CH_R { + TX_CH_ARB_WEIGH_CH_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8 - 0: mean not optimazation weight function ,1: mean optimazation"] + #[inline(always)] + pub fn tx_arb_weigh_opt_dir_ch(&self) -> TX_ARB_WEIGH_OPT_DIR_CH_R { + TX_ARB_WEIGH_OPT_DIR_CH_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PRI_CH") + .field("tx_pri_ch", &format_args!("{}", self.tx_pri_ch().bits())) + .field( + "tx_ch_arb_weigh_ch", + &format_args!("{}", self.tx_ch_arb_weigh_ch().bits()), + ) + .field( + "tx_arb_weigh_opt_dir_ch", + &format_args!("{}", self.tx_arb_weigh_opt_dir_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - The priority of Tx channel0. The larger of the value the higher of the priority."] + #[inline(always)] + #[must_use] + pub fn tx_pri_ch(&mut self) -> TX_PRI_CH_W { + TX_PRI_CH_W::new(self, 0) + } + #[doc = "Bits 4:7 - The weight of Tx channel0"] + #[inline(always)] + #[must_use] + pub fn tx_ch_arb_weigh_ch(&mut self) -> TX_CH_ARB_WEIGH_CH_W { + TX_CH_ARB_WEIGH_CH_W::new(self, 4) + } + #[doc = "Bit 8 - 0: mean not optimazation weight function ,1: mean optimazation"] + #[inline(always)] + #[must_use] + pub fn tx_arb_weigh_opt_dir_ch(&mut self) -> TX_ARB_WEIGH_OPT_DIR_CH_W { + TX_ARB_WEIGH_OPT_DIR_CH_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Priority register of Tx channel0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_pri_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_pri_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PRI_CH_SPEC; +impl crate::RegisterSpec for OUT_PRI_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_pri_ch::R`](R) reader structure"] +impl crate::Readable for OUT_PRI_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_pri_ch::W`](W) writer structure"] +impl crate::Writable for OUT_PRI_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_PRI_CH%s to value 0"] +impl crate::Resettable for OUT_PRI_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_push_ch.rs b/esp32p4/src/axi_dma/out_push_ch.rs new file mode 100644 index 0000000000..1588890f6a --- /dev/null +++ b/esp32p4/src/axi_dma/out_push_ch.rs @@ -0,0 +1,74 @@ +#[doc = "Register `OUT_PUSH_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_PUSH_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `OUTFIFO_WDATA_CH` reader - This register stores the data that need to be pushed into AXI_DMA FIFO."] +pub type OUTFIFO_WDATA_CH_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA_CH` writer - This register stores the data that need to be pushed into AXI_DMA FIFO."] +pub type OUTFIFO_WDATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `OUTFIFO_PUSH_CH` writer - Set this bit to push data into AXI_DMA FIFO."] +pub type OUTFIFO_PUSH_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:8 - This register stores the data that need to be pushed into AXI_DMA FIFO."] + #[inline(always)] + pub fn outfifo_wdata_ch(&self) -> OUTFIFO_WDATA_CH_R { + OUTFIFO_WDATA_CH_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_CH") + .field( + "outfifo_wdata_ch", + &format_args!("{}", self.outfifo_wdata_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - This register stores the data that need to be pushed into AXI_DMA FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_wdata_ch(&mut self) -> OUTFIFO_WDATA_CH_W { + OUTFIFO_WDATA_CH_W::new(self, 0) + } + #[doc = "Bit 9 - Set this bit to push data into AXI_DMA FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_push_ch(&mut self) -> OUTFIFO_PUSH_CH_W { + OUTFIFO_PUSH_CH_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Push control register of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_CH_SPEC; +impl crate::RegisterSpec for OUT_PUSH_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_ch::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_push_ch::W`](W) writer structure"] +impl crate::Writable for OUT_PUSH_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_PUSH_CH%s to value 0"] +impl crate::Resettable for OUT_PUSH_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/out_reset_avail_ch.rs b/esp32p4/src/axi_dma/out_reset_avail_ch.rs new file mode 100644 index 0000000000..f37e0b6c80 --- /dev/null +++ b/esp32p4/src/axi_dma/out_reset_avail_ch.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_RESET_AVAIL_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_RESET_AVAIL_CH` reader - tx chan0 reset valid reg."] +pub type OUT_RESET_AVAIL_CH_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - tx chan0 reset valid reg."] + #[inline(always)] + pub fn out_reset_avail_ch(&self) -> OUT_RESET_AVAIL_CH_R { + OUT_RESET_AVAIL_CH_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_RESET_AVAIL_CH") + .field( + "out_reset_avail_ch", + &format_args!("{}", self.out_reset_avail_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The tx channel 0 reset valid_flag register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_reset_avail_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_RESET_AVAIL_CH_SPEC; +impl crate::RegisterSpec for OUT_RESET_AVAIL_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_reset_avail_ch::R`](R) reader structure"] +impl crate::Readable for OUT_RESET_AVAIL_CH_SPEC {} +#[doc = "`reset()` method sets OUT_RESET_AVAIL_CH%s to value 0x01"] +impl crate::Resettable for OUT_RESET_AVAIL_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/axi_dma/out_state_ch.rs b/esp32p4/src/axi_dma/out_state_ch.rs new file mode 100644 index 0000000000..ae163b136c --- /dev/null +++ b/esp32p4/src/axi_dma/out_state_ch.rs @@ -0,0 +1,61 @@ +#[doc = "Register `OUT_STATE_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_ADDR_CH` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE_CH` reader - reserved"] +pub type OUT_DSCR_STATE_CH_R = crate::FieldReader; +#[doc = "Field `OUT_STATE_CH` reader - reserved"] +pub type OUT_STATE_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] + #[inline(always)] + pub fn outlink_dscr_addr_ch(&self) -> OUTLINK_DSCR_ADDR_CH_R { + OUTLINK_DSCR_ADDR_CH_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - reserved"] + #[inline(always)] + pub fn out_dscr_state_ch(&self) -> OUT_DSCR_STATE_CH_R { + OUT_DSCR_STATE_CH_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - reserved"] + #[inline(always)] + pub fn out_state_ch(&self) -> OUT_STATE_CH_R { + OUT_STATE_CH_R::new(((self.bits >> 20) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_STATE_CH") + .field( + "outlink_dscr_addr_ch", + &format_args!("{}", self.outlink_dscr_addr_ch().bits()), + ) + .field( + "out_dscr_state_ch", + &format_args!("{}", self.out_dscr_state_ch().bits()), + ) + .field( + "out_state_ch", + &format_args!("{}", self.out_state_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Transmit status of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_STATE_CH_SPEC; +impl crate::RegisterSpec for OUT_STATE_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_state_ch::R`](R) reader structure"] +impl crate::Readable for OUT_STATE_CH_SPEC {} +#[doc = "`reset()` method sets OUT_STATE_CH%s to value 0"] +impl crate::Resettable for OUT_STATE_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/outfifo_status1_ch.rs b/esp32p4/src/axi_dma/outfifo_status1_ch.rs new file mode 100644 index 0000000000..2a9e799724 --- /dev/null +++ b/esp32p4/src/axi_dma/outfifo_status1_ch.rs @@ -0,0 +1,50 @@ +#[doc = "Register `OUTFIFO_STATUS1_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `L1OUTFIFO_CNT_CH` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] +pub type L1OUTFIFO_CNT_CH_R = crate::FieldReader; +#[doc = "Field `L2OUTFIFO_CNT_CH` reader - The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0."] +pub type L2OUTFIFO_CNT_CH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:5 - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."] + #[inline(always)] + pub fn l1outfifo_cnt_ch(&self) -> L1OUTFIFO_CNT_CH_R { + L1OUTFIFO_CNT_CH_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:9 - The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0."] + #[inline(always)] + pub fn l2outfifo_cnt_ch(&self) -> L2OUTFIFO_CNT_CH_R { + L2OUTFIFO_CNT_CH_R::new(((self.bits >> 6) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUTFIFO_STATUS1_CH") + .field( + "l1outfifo_cnt_ch", + &format_args!("{}", self.l1outfifo_cnt_ch().bits()), + ) + .field( + "l2outfifo_cnt_ch", + &format_args!("{}", self.l2outfifo_cnt_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Receive FIFO status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status1_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUTFIFO_STATUS1_CH_SPEC; +impl crate::RegisterSpec for OUTFIFO_STATUS1_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`outfifo_status1_ch::R`](R) reader structure"] +impl crate::Readable for OUTFIFO_STATUS1_CH_SPEC {} +#[doc = "`reset()` method sets OUTFIFO_STATUS1_CH%s to value 0"] +impl crate::Resettable for OUTFIFO_STATUS1_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/outfifo_status_ch.rs b/esp32p4/src/axi_dma/outfifo_status_ch.rs new file mode 100644 index 0000000000..184bae0f1b --- /dev/null +++ b/esp32p4/src/axi_dma/outfifo_status_ch.rs @@ -0,0 +1,259 @@ +#[doc = "Register `OUTFIFO_STATUS_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `OUTFIFO_L3_FULL_CH` reader - L3 Tx FIFO full signal for Tx channel0."] +pub type OUTFIFO_L3_FULL_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L3_EMPTY_CH` reader - L3 Tx FIFO empty signal for Tx channel0."] +pub type OUTFIFO_L3_EMPTY_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L3_CNT_CH` reader - The register stores the byte number of the data in L3 Tx FIFO for Tx channel0."] +pub type OUTFIFO_L3_CNT_CH_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_L3_UDF_CH` reader - L3 Tx FIFO under flow signal for Tx channel0."] +pub type OUTFIFO_L3_UDF_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L3_OVF_CH` reader - L3 Tx FIFO over flow signal for Tx channel0."] +pub type OUTFIFO_L3_OVF_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L1_FULL_CH` reader - L1 Tx FIFO full signal for Tx channel0."] +pub type OUTFIFO_L1_FULL_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L1_EMPTY_CH` reader - L1 Tx FIFO empty signal for Tx channel0."] +pub type OUTFIFO_L1_EMPTY_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L1_UDF_CH` reader - L1 Tx FIFO under flow signal for Tx channel0."] +pub type OUTFIFO_L1_UDF_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L1_OVF_CH` reader - L1 Tx FIFO over flow signal for Tx channel0."] +pub type OUTFIFO_L1_OVF_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L2_FULL_CH` reader - L2 Tx RAM full signal for Tx channel0."] +pub type OUTFIFO_L2_FULL_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L2_EMPTY_CH` reader - L2 Tx RAM empty signal for Tx channel0."] +pub type OUTFIFO_L2_EMPTY_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L2_UDF_CH` reader - L2 Tx FIFO under flow signal for Tx channel0."] +pub type OUTFIFO_L2_UDF_CH_R = crate::BitReader; +#[doc = "Field `OUTFIFO_L2_OVF_CH` reader - L2 Tx FIFO over flow signal for Tx channel0."] +pub type OUTFIFO_L2_OVF_CH_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_1B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_1B_CH_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_2B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_2B_CH_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_3B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_3B_CH_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_4B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_4B_CH_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_5B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_5B_CH_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_6B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_6B_CH_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_7B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_7B_CH_R = crate::BitReader; +#[doc = "Field `OUT_REMAIN_UNDER_8B_CH` reader - reserved"] +pub type OUT_REMAIN_UNDER_8B_CH_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - L3 Tx FIFO full signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l3_full_ch(&self) -> OUTFIFO_L3_FULL_CH_R { + OUTFIFO_L3_FULL_CH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - L3 Tx FIFO empty signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l3_empty_ch(&self) -> OUTFIFO_L3_EMPTY_CH_R { + OUTFIFO_L3_EMPTY_CH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - The register stores the byte number of the data in L3 Tx FIFO for Tx channel0."] + #[inline(always)] + pub fn outfifo_l3_cnt_ch(&self) -> OUTFIFO_L3_CNT_CH_R { + OUTFIFO_L3_CNT_CH_R::new(((self.bits >> 2) & 0x3f) as u8) + } + #[doc = "Bit 8 - L3 Tx FIFO under flow signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l3_udf_ch(&self) -> OUTFIFO_L3_UDF_CH_R { + OUTFIFO_L3_UDF_CH_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - L3 Tx FIFO over flow signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l3_ovf_ch(&self) -> OUTFIFO_L3_OVF_CH_R { + OUTFIFO_L3_OVF_CH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - L1 Tx FIFO full signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l1_full_ch(&self) -> OUTFIFO_L1_FULL_CH_R { + OUTFIFO_L1_FULL_CH_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - L1 Tx FIFO empty signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l1_empty_ch(&self) -> OUTFIFO_L1_EMPTY_CH_R { + OUTFIFO_L1_EMPTY_CH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - L1 Tx FIFO under flow signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l1_udf_ch(&self) -> OUTFIFO_L1_UDF_CH_R { + OUTFIFO_L1_UDF_CH_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - L1 Tx FIFO over flow signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l1_ovf_ch(&self) -> OUTFIFO_L1_OVF_CH_R { + OUTFIFO_L1_OVF_CH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - L2 Tx RAM full signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l2_full_ch(&self) -> OUTFIFO_L2_FULL_CH_R { + OUTFIFO_L2_FULL_CH_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - L2 Tx RAM empty signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l2_empty_ch(&self) -> OUTFIFO_L2_EMPTY_CH_R { + OUTFIFO_L2_EMPTY_CH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - L2 Tx FIFO under flow signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l2_udf_ch(&self) -> OUTFIFO_L2_UDF_CH_R { + OUTFIFO_L2_UDF_CH_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - L2 Tx FIFO over flow signal for Tx channel0."] + #[inline(always)] + pub fn outfifo_l2_ovf_ch(&self) -> OUTFIFO_L2_OVF_CH_R { + OUTFIFO_L2_OVF_CH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 23 - reserved"] + #[inline(always)] + pub fn out_remain_under_1b_ch(&self) -> OUT_REMAIN_UNDER_1B_CH_R { + OUT_REMAIN_UNDER_1B_CH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - reserved"] + #[inline(always)] + pub fn out_remain_under_2b_ch(&self) -> OUT_REMAIN_UNDER_2B_CH_R { + OUT_REMAIN_UNDER_2B_CH_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reserved"] + #[inline(always)] + pub fn out_remain_under_3b_ch(&self) -> OUT_REMAIN_UNDER_3B_CH_R { + OUT_REMAIN_UNDER_3B_CH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - reserved"] + #[inline(always)] + pub fn out_remain_under_4b_ch(&self) -> OUT_REMAIN_UNDER_4B_CH_R { + OUT_REMAIN_UNDER_4B_CH_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - reserved"] + #[inline(always)] + pub fn out_remain_under_5b_ch(&self) -> OUT_REMAIN_UNDER_5B_CH_R { + OUT_REMAIN_UNDER_5B_CH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - reserved"] + #[inline(always)] + pub fn out_remain_under_6b_ch(&self) -> OUT_REMAIN_UNDER_6B_CH_R { + OUT_REMAIN_UNDER_6B_CH_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - reserved"] + #[inline(always)] + pub fn out_remain_under_7b_ch(&self) -> OUT_REMAIN_UNDER_7B_CH_R { + OUT_REMAIN_UNDER_7B_CH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - reserved"] + #[inline(always)] + pub fn out_remain_under_8b_ch(&self) -> OUT_REMAIN_UNDER_8B_CH_R { + OUT_REMAIN_UNDER_8B_CH_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUTFIFO_STATUS_CH") + .field( + "outfifo_l3_full_ch", + &format_args!("{}", self.outfifo_l3_full_ch().bit()), + ) + .field( + "outfifo_l3_empty_ch", + &format_args!("{}", self.outfifo_l3_empty_ch().bit()), + ) + .field( + "outfifo_l3_cnt_ch", + &format_args!("{}", self.outfifo_l3_cnt_ch().bits()), + ) + .field( + "outfifo_l3_udf_ch", + &format_args!("{}", self.outfifo_l3_udf_ch().bit()), + ) + .field( + "outfifo_l3_ovf_ch", + &format_args!("{}", self.outfifo_l3_ovf_ch().bit()), + ) + .field( + "outfifo_l1_full_ch", + &format_args!("{}", self.outfifo_l1_full_ch().bit()), + ) + .field( + "outfifo_l1_empty_ch", + &format_args!("{}", self.outfifo_l1_empty_ch().bit()), + ) + .field( + "outfifo_l1_udf_ch", + &format_args!("{}", self.outfifo_l1_udf_ch().bit()), + ) + .field( + "outfifo_l1_ovf_ch", + &format_args!("{}", self.outfifo_l1_ovf_ch().bit()), + ) + .field( + "outfifo_l2_full_ch", + &format_args!("{}", self.outfifo_l2_full_ch().bit()), + ) + .field( + "outfifo_l2_empty_ch", + &format_args!("{}", self.outfifo_l2_empty_ch().bit()), + ) + .field( + "outfifo_l2_udf_ch", + &format_args!("{}", self.outfifo_l2_udf_ch().bit()), + ) + .field( + "outfifo_l2_ovf_ch", + &format_args!("{}", self.outfifo_l2_ovf_ch().bit()), + ) + .field( + "out_remain_under_1b_ch", + &format_args!("{}", self.out_remain_under_1b_ch().bit()), + ) + .field( + "out_remain_under_2b_ch", + &format_args!("{}", self.out_remain_under_2b_ch().bit()), + ) + .field( + "out_remain_under_3b_ch", + &format_args!("{}", self.out_remain_under_3b_ch().bit()), + ) + .field( + "out_remain_under_4b_ch", + &format_args!("{}", self.out_remain_under_4b_ch().bit()), + ) + .field( + "out_remain_under_5b_ch", + &format_args!("{}", self.out_remain_under_5b_ch().bit()), + ) + .field( + "out_remain_under_6b_ch", + &format_args!("{}", self.out_remain_under_6b_ch().bit()), + ) + .field( + "out_remain_under_7b_ch", + &format_args!("{}", self.out_remain_under_7b_ch().bit()), + ) + .field( + "out_remain_under_8b_ch", + &format_args!("{}", self.out_remain_under_8b_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Transmit FIFO status of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUTFIFO_STATUS_CH_SPEC; +impl crate::RegisterSpec for OUTFIFO_STATUS_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`outfifo_status_ch::R`](R) reader structure"] +impl crate::Readable for OUTFIFO_STATUS_CH_SPEC {} +#[doc = "`reset()` method sets OUTFIFO_STATUS_CH%s to value 0x7f80_8802"] +impl crate::Resettable for OUTFIFO_STATUS_CH_SPEC { + const RESET_VALUE: Self::Ux = 0x7f80_8802; +} diff --git a/esp32p4/src/axi_dma/rdn_eco_high.rs b/esp32p4/src/axi_dma/rdn_eco_high.rs new file mode 100644 index 0000000000..9e994cdb25 --- /dev/null +++ b/esp32p4/src/axi_dma/rdn_eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RDN_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_HIGH` reader - The start address of accessible address space."] +pub type RDN_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_HIGH` writer - The start address of accessible address space."] +pub type RDN_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + pub fn rdn_eco_high(&self) -> RDN_ECO_HIGH_R { + RDN_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_HIGH") + .field( + "rdn_eco_high", + &format_args!("{}", self.rdn_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + #[must_use] + pub fn rdn_eco_high(&mut self) -> RDN_ECO_HIGH_W { + RDN_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_HIGH_SPEC; +impl crate::RegisterSpec for RDN_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_high::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_high::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for RDN_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/axi_dma/rdn_eco_low.rs b/esp32p4/src/axi_dma/rdn_eco_low.rs new file mode 100644 index 0000000000..51efef1e0a --- /dev/null +++ b/esp32p4/src/axi_dma/rdn_eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RDN_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_LOW` reader - The start address of accessible address space."] +pub type RDN_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_LOW` writer - The start address of accessible address space."] +pub type RDN_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + pub fn rdn_eco_low(&self) -> RDN_ECO_LOW_R { + RDN_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_LOW") + .field( + "rdn_eco_low", + &format_args!("{}", self.rdn_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + #[must_use] + pub fn rdn_eco_low(&mut self) -> RDN_ECO_LOW_W { + RDN_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_LOW_SPEC; +impl crate::RegisterSpec for RDN_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_low::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_low::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_LOW to value 0"] +impl crate::Resettable for RDN_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/rdn_result.rs b/esp32p4/src/axi_dma/rdn_result.rs new file mode 100644 index 0000000000..bd9583d011 --- /dev/null +++ b/esp32p4/src/axi_dma/rdn_result.rs @@ -0,0 +1,71 @@ +#[doc = "Register `RDN_RESULT` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_RESULT` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ENA` reader - reserved"] +pub type RDN_ENA_R = crate::BitReader; +#[doc = "Field `RDN_ENA` writer - reserved"] +pub type RDN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RDN_RESULT` reader - reserved"] +pub type RDN_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - reserved"] + #[inline(always)] + pub fn rdn_ena(&self) -> RDN_ENA_R { + RDN_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - reserved"] + #[inline(always)] + pub fn rdn_result(&self) -> RDN_RESULT_R { + RDN_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_RESULT") + .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit())) + .field("rdn_result", &format_args!("{}", self.rdn_result().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - reserved"] + #[inline(always)] + #[must_use] + pub fn rdn_ena(&mut self) -> RDN_ENA_W { + RDN_ENA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_result::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_result::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_RESULT_SPEC; +impl crate::RegisterSpec for RDN_RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_result::R`](R) reader structure"] +impl crate::Readable for RDN_RESULT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_result::W`](W) writer structure"] +impl crate::Writable for RDN_RESULT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_RESULT to value 0"] +impl crate::Resettable for RDN_RESULT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/rresp_cnt.rs b/esp32p4/src/axi_dma/rresp_cnt.rs new file mode 100644 index 0000000000..04b652fa1d --- /dev/null +++ b/esp32p4/src/axi_dma/rresp_cnt.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RRESP_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `RRESP_CNT` reader - axi rd responce cnt reg."] +pub type RRESP_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - axi rd responce cnt reg."] + #[inline(always)] + pub fn rresp_cnt(&self) -> RRESP_CNT_R { + RRESP_CNT_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RRESP_CNT") + .field("rresp_cnt", &format_args!("{}", self.rresp_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "AXI wr responce cnt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rresp_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RRESP_CNT_SPEC; +impl crate::RegisterSpec for RRESP_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rresp_cnt::R`](R) reader structure"] +impl crate::Readable for RRESP_CNT_SPEC {} +#[doc = "`reset()` method sets RRESP_CNT to value 0"] +impl crate::Resettable for RRESP_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/rx_crc_data_en_addr_ch.rs b/esp32p4/src/axi_dma/rx_crc_data_en_addr_ch.rs new file mode 100644 index 0000000000..fbd6131eee --- /dev/null +++ b/esp32p4/src/axi_dma/rx_crc_data_en_addr_ch.rs @@ -0,0 +1,68 @@ +#[doc = "Register `RX_CRC_DATA_EN_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CRC_DATA_EN_ADDR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CRC_DATA_EN_ADDR_CH` reader - reserved"] +pub type RX_CRC_DATA_EN_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `RX_CRC_DATA_EN_ADDR_CH` writer - reserved"] +pub type RX_CRC_DATA_EN_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + pub fn rx_crc_data_en_addr_ch(&self) -> RX_CRC_DATA_EN_ADDR_CH_R { + RX_CRC_DATA_EN_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CRC_DATA_EN_ADDR_CH") + .field( + "rx_crc_data_en_addr_ch", + &format_args!("{}", self.rx_crc_data_en_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_crc_data_en_addr_ch( + &mut self, + ) -> RX_CRC_DATA_EN_ADDR_CH_W { + RX_CRC_DATA_EN_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config addr of crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_data_en_addr_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_data_en_addr_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CRC_DATA_EN_ADDR_CH_SPEC; +impl crate::RegisterSpec for RX_CRC_DATA_EN_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_crc_data_en_addr_ch::R`](R) reader structure"] +impl crate::Readable for RX_CRC_DATA_EN_ADDR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_crc_data_en_addr_ch::W`](W) writer structure"] +impl crate::Writable for RX_CRC_DATA_EN_ADDR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CRC_DATA_EN_ADDR_CH%s to value 0"] +impl crate::Resettable for RX_CRC_DATA_EN_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/rx_crc_data_en_wr_data_ch.rs b/esp32p4/src/axi_dma/rx_crc_data_en_wr_data_ch.rs new file mode 100644 index 0000000000..1fcc9a273c --- /dev/null +++ b/esp32p4/src/axi_dma/rx_crc_data_en_wr_data_ch.rs @@ -0,0 +1,68 @@ +#[doc = "Register `RX_CRC_DATA_EN_WR_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CRC_DATA_EN_WR_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CRC_DATA_EN_WR_DATA_CH` reader - reserved"] +pub type RX_CRC_DATA_EN_WR_DATA_CH_R = crate::FieldReader; +#[doc = "Field `RX_CRC_DATA_EN_WR_DATA_CH` writer - reserved"] +pub type RX_CRC_DATA_EN_WR_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - reserved"] + #[inline(always)] + pub fn rx_crc_data_en_wr_data_ch(&self) -> RX_CRC_DATA_EN_WR_DATA_CH_R { + RX_CRC_DATA_EN_WR_DATA_CH_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CRC_DATA_EN_WR_DATA_CH") + .field( + "rx_crc_data_en_wr_data_ch", + &format_args!("{}", self.rx_crc_data_en_wr_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_crc_data_en_wr_data_ch( + &mut self, + ) -> RX_CRC_DATA_EN_WR_DATA_CH_W { + RX_CRC_DATA_EN_WR_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_data_en_wr_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_data_en_wr_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CRC_DATA_EN_WR_DATA_CH_SPEC; +impl crate::RegisterSpec for RX_CRC_DATA_EN_WR_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_crc_data_en_wr_data_ch::R`](R) reader structure"] +impl crate::Readable for RX_CRC_DATA_EN_WR_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_crc_data_en_wr_data_ch::W`](W) writer structure"] +impl crate::Writable for RX_CRC_DATA_EN_WR_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CRC_DATA_EN_WR_DATA_CH%s to value 0"] +impl crate::Resettable for RX_CRC_DATA_EN_WR_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/rx_crc_en_addr_ch.rs b/esp32p4/src/axi_dma/rx_crc_en_addr_ch.rs new file mode 100644 index 0000000000..d37b045934 --- /dev/null +++ b/esp32p4/src/axi_dma/rx_crc_en_addr_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RX_CRC_EN_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CRC_EN_ADDR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CRC_EN_ADDR_CH` reader - reserved"] +pub type RX_CRC_EN_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `RX_CRC_EN_ADDR_CH` writer - reserved"] +pub type RX_CRC_EN_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + pub fn rx_crc_en_addr_ch(&self) -> RX_CRC_EN_ADDR_CH_R { + RX_CRC_EN_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CRC_EN_ADDR_CH") + .field( + "rx_crc_en_addr_ch", + &format_args!("{}", self.rx_crc_en_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_crc_en_addr_ch(&mut self) -> RX_CRC_EN_ADDR_CH_W { + RX_CRC_EN_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config ch0 crc en addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_en_addr_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_en_addr_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CRC_EN_ADDR_CH_SPEC; +impl crate::RegisterSpec for RX_CRC_EN_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_crc_en_addr_ch::R`](R) reader structure"] +impl crate::Readable for RX_CRC_EN_ADDR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_crc_en_addr_ch::W`](W) writer structure"] +impl crate::Writable for RX_CRC_EN_ADDR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CRC_EN_ADDR_CH%s to value 0"] +impl crate::Resettable for RX_CRC_EN_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/rx_crc_en_wr_data_ch.rs b/esp32p4/src/axi_dma/rx_crc_en_wr_data_ch.rs new file mode 100644 index 0000000000..cba96b2e45 --- /dev/null +++ b/esp32p4/src/axi_dma/rx_crc_en_wr_data_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RX_CRC_EN_WR_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CRC_EN_WR_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CRC_EN_WR_DATA_CH` reader - This register is used to enable rx ch0 crc 32bit on/off"] +pub type RX_CRC_EN_WR_DATA_CH_R = crate::FieldReader; +#[doc = "Field `RX_CRC_EN_WR_DATA_CH` writer - This register is used to enable rx ch0 crc 32bit on/off"] +pub type RX_CRC_EN_WR_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is used to enable rx ch0 crc 32bit on/off"] + #[inline(always)] + pub fn rx_crc_en_wr_data_ch(&self) -> RX_CRC_EN_WR_DATA_CH_R { + RX_CRC_EN_WR_DATA_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CRC_EN_WR_DATA_CH") + .field( + "rx_crc_en_wr_data_ch", + &format_args!("{}", self.rx_crc_en_wr_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register is used to enable rx ch0 crc 32bit on/off"] + #[inline(always)] + #[must_use] + pub fn rx_crc_en_wr_data_ch(&mut self) -> RX_CRC_EN_WR_DATA_CH_W { + RX_CRC_EN_WR_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This resister is used to config ch0 crc en for every bit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_en_wr_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_en_wr_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CRC_EN_WR_DATA_CH_SPEC; +impl crate::RegisterSpec for RX_CRC_EN_WR_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_crc_en_wr_data_ch::R`](R) reader structure"] +impl crate::Readable for RX_CRC_EN_WR_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_crc_en_wr_data_ch::W`](W) writer structure"] +impl crate::Writable for RX_CRC_EN_WR_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CRC_EN_WR_DATA_CH%s to value 0"] +impl crate::Resettable for RX_CRC_EN_WR_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/rx_crc_width_ch.rs b/esp32p4/src/axi_dma/rx_crc_width_ch.rs new file mode 100644 index 0000000000..bae11f4183 --- /dev/null +++ b/esp32p4/src/axi_dma/rx_crc_width_ch.rs @@ -0,0 +1,85 @@ +#[doc = "Register `RX_CRC_WIDTH_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CRC_WIDTH_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CRC_WIDTH_CH` reader - reserved"] +pub type RX_CRC_WIDTH_CH_R = crate::FieldReader; +#[doc = "Field `RX_CRC_WIDTH_CH` writer - reserved"] +pub type RX_CRC_WIDTH_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_CRC_LAUTCH_FLGA_CH` reader - reserved"] +pub type RX_CRC_LAUTCH_FLGA_CH_R = crate::BitReader; +#[doc = "Field `RX_CRC_LAUTCH_FLGA_CH` writer - reserved"] +pub type RX_CRC_LAUTCH_FLGA_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - reserved"] + #[inline(always)] + pub fn rx_crc_width_ch(&self) -> RX_CRC_WIDTH_CH_R { + RX_CRC_WIDTH_CH_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - reserved"] + #[inline(always)] + pub fn rx_crc_lautch_flga_ch(&self) -> RX_CRC_LAUTCH_FLGA_CH_R { + RX_CRC_LAUTCH_FLGA_CH_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CRC_WIDTH_CH") + .field( + "rx_crc_width_ch", + &format_args!("{}", self.rx_crc_width_ch().bits()), + ) + .field( + "rx_crc_lautch_flga_ch", + &format_args!("{}", self.rx_crc_lautch_flga_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_crc_width_ch(&mut self) -> RX_CRC_WIDTH_CH_W { + RX_CRC_WIDTH_CH_W::new(self, 0) + } + #[doc = "Bit 2 - reserved"] + #[inline(always)] + #[must_use] + pub fn rx_crc_lautch_flga_ch(&mut self) -> RX_CRC_LAUTCH_FLGA_CH_W { + RX_CRC_LAUTCH_FLGA_CH_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_crc_width_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_crc_width_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CRC_WIDTH_CH_SPEC; +impl crate::RegisterSpec for RX_CRC_WIDTH_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_crc_width_ch::R`](R) reader structure"] +impl crate::Readable for RX_CRC_WIDTH_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_crc_width_ch::W`](W) writer structure"] +impl crate::Writable for RX_CRC_WIDTH_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CRC_WIDTH_CH%s to value 0"] +impl crate::Resettable for RX_CRC_WIDTH_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/tx_crc_data_en_addr_ch.rs b/esp32p4/src/axi_dma/tx_crc_data_en_addr_ch.rs new file mode 100644 index 0000000000..0393763613 --- /dev/null +++ b/esp32p4/src/axi_dma/tx_crc_data_en_addr_ch.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TX_CRC_DATA_EN_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CRC_DATA_EN_ADDR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CRC_DATA_EN_ADDR_CH` reader - reserved"] +pub type TX_CRC_DATA_EN_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `TX_CRC_DATA_EN_ADDR_CH` writer - reserved"] +pub type TX_CRC_DATA_EN_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + pub fn tx_crc_data_en_addr_ch(&self) -> TX_CRC_DATA_EN_ADDR_CH_R { + TX_CRC_DATA_EN_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CRC_DATA_EN_ADDR_CH") + .field( + "tx_crc_data_en_addr_ch", + &format_args!("{}", self.tx_crc_data_en_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_crc_data_en_addr_ch( + &mut self, + ) -> TX_CRC_DATA_EN_ADDR_CH_W { + TX_CRC_DATA_EN_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config addr of crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_data_en_addr_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_data_en_addr_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CRC_DATA_EN_ADDR_CH_SPEC; +impl crate::RegisterSpec for TX_CRC_DATA_EN_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_crc_data_en_addr_ch::R`](R) reader structure"] +impl crate::Readable for TX_CRC_DATA_EN_ADDR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_crc_data_en_addr_ch::W`](W) writer structure"] +impl crate::Writable for TX_CRC_DATA_EN_ADDR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CRC_DATA_EN_ADDR_CH%s to value 0"] +impl crate::Resettable for TX_CRC_DATA_EN_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/tx_crc_data_en_wr_data_ch.rs b/esp32p4/src/axi_dma/tx_crc_data_en_wr_data_ch.rs new file mode 100644 index 0000000000..d0efb60237 --- /dev/null +++ b/esp32p4/src/axi_dma/tx_crc_data_en_wr_data_ch.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TX_CRC_DATA_EN_WR_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CRC_DATA_EN_WR_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CRC_DATA_EN_WR_DATA_CH` reader - reserved"] +pub type TX_CRC_DATA_EN_WR_DATA_CH_R = crate::FieldReader; +#[doc = "Field `TX_CRC_DATA_EN_WR_DATA_CH` writer - reserved"] +pub type TX_CRC_DATA_EN_WR_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - reserved"] + #[inline(always)] + pub fn tx_crc_data_en_wr_data_ch(&self) -> TX_CRC_DATA_EN_WR_DATA_CH_R { + TX_CRC_DATA_EN_WR_DATA_CH_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CRC_DATA_EN_WR_DATA_CH") + .field( + "tx_crc_data_en_wr_data_ch", + &format_args!("{}", self.tx_crc_data_en_wr_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_crc_data_en_wr_data_ch( + &mut self, + ) -> TX_CRC_DATA_EN_WR_DATA_CH_W { + TX_CRC_DATA_EN_WR_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config crc data_8bit en\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_data_en_wr_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_data_en_wr_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CRC_DATA_EN_WR_DATA_CH_SPEC; +impl crate::RegisterSpec for TX_CRC_DATA_EN_WR_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_crc_data_en_wr_data_ch::R`](R) reader structure"] +impl crate::Readable for TX_CRC_DATA_EN_WR_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_crc_data_en_wr_data_ch::W`](W) writer structure"] +impl crate::Writable for TX_CRC_DATA_EN_WR_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CRC_DATA_EN_WR_DATA_CH%s to value 0"] +impl crate::Resettable for TX_CRC_DATA_EN_WR_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/tx_crc_en_addr_ch.rs b/esp32p4/src/axi_dma/tx_crc_en_addr_ch.rs new file mode 100644 index 0000000000..8323392846 --- /dev/null +++ b/esp32p4/src/axi_dma/tx_crc_en_addr_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TX_CRC_EN_ADDR_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CRC_EN_ADDR_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CRC_EN_ADDR_CH` reader - reserved"] +pub type TX_CRC_EN_ADDR_CH_R = crate::FieldReader; +#[doc = "Field `TX_CRC_EN_ADDR_CH` writer - reserved"] +pub type TX_CRC_EN_ADDR_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + pub fn tx_crc_en_addr_ch(&self) -> TX_CRC_EN_ADDR_CH_R { + TX_CRC_EN_ADDR_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CRC_EN_ADDR_CH") + .field( + "tx_crc_en_addr_ch", + &format_args!("{}", self.tx_crc_en_addr_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_crc_en_addr_ch(&mut self) -> TX_CRC_EN_ADDR_CH_W { + TX_CRC_EN_ADDR_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config ch0 crc en addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_en_addr_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_en_addr_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CRC_EN_ADDR_CH_SPEC; +impl crate::RegisterSpec for TX_CRC_EN_ADDR_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_crc_en_addr_ch::R`](R) reader structure"] +impl crate::Readable for TX_CRC_EN_ADDR_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_crc_en_addr_ch::W`](W) writer structure"] +impl crate::Writable for TX_CRC_EN_ADDR_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CRC_EN_ADDR_CH%s to value 0"] +impl crate::Resettable for TX_CRC_EN_ADDR_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/tx_crc_en_wr_data_ch.rs b/esp32p4/src/axi_dma/tx_crc_en_wr_data_ch.rs new file mode 100644 index 0000000000..d6a469072f --- /dev/null +++ b/esp32p4/src/axi_dma/tx_crc_en_wr_data_ch.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TX_CRC_EN_WR_DATA_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CRC_EN_WR_DATA_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CRC_EN_WR_DATA_CH` reader - This register is used to enable tx ch0 crc 32bit on/off"] +pub type TX_CRC_EN_WR_DATA_CH_R = crate::FieldReader; +#[doc = "Field `TX_CRC_EN_WR_DATA_CH` writer - This register is used to enable tx ch0 crc 32bit on/off"] +pub type TX_CRC_EN_WR_DATA_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is used to enable tx ch0 crc 32bit on/off"] + #[inline(always)] + pub fn tx_crc_en_wr_data_ch(&self) -> TX_CRC_EN_WR_DATA_CH_R { + TX_CRC_EN_WR_DATA_CH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CRC_EN_WR_DATA_CH") + .field( + "tx_crc_en_wr_data_ch", + &format_args!("{}", self.tx_crc_en_wr_data_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register is used to enable tx ch0 crc 32bit on/off"] + #[inline(always)] + #[must_use] + pub fn tx_crc_en_wr_data_ch(&mut self) -> TX_CRC_EN_WR_DATA_CH_W { + TX_CRC_EN_WR_DATA_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This resister is used to config ch0 crc en for every bit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_en_wr_data_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_en_wr_data_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CRC_EN_WR_DATA_CH_SPEC; +impl crate::RegisterSpec for TX_CRC_EN_WR_DATA_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_crc_en_wr_data_ch::R`](R) reader structure"] +impl crate::Readable for TX_CRC_EN_WR_DATA_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_crc_en_wr_data_ch::W`](W) writer structure"] +impl crate::Writable for TX_CRC_EN_WR_DATA_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CRC_EN_WR_DATA_CH%s to value 0"] +impl crate::Resettable for TX_CRC_EN_WR_DATA_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/tx_crc_width_ch.rs b/esp32p4/src/axi_dma/tx_crc_width_ch.rs new file mode 100644 index 0000000000..7b1efff15d --- /dev/null +++ b/esp32p4/src/axi_dma/tx_crc_width_ch.rs @@ -0,0 +1,85 @@ +#[doc = "Register `TX_CRC_WIDTH_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CRC_WIDTH_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CRC_WIDTH_CH` reader - reserved"] +pub type TX_CRC_WIDTH_CH_R = crate::FieldReader; +#[doc = "Field `TX_CRC_WIDTH_CH` writer - reserved"] +pub type TX_CRC_WIDTH_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_CRC_LAUTCH_FLGA_CH` reader - reserved"] +pub type TX_CRC_LAUTCH_FLGA_CH_R = crate::BitReader; +#[doc = "Field `TX_CRC_LAUTCH_FLGA_CH` writer - reserved"] +pub type TX_CRC_LAUTCH_FLGA_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - reserved"] + #[inline(always)] + pub fn tx_crc_width_ch(&self) -> TX_CRC_WIDTH_CH_R { + TX_CRC_WIDTH_CH_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - reserved"] + #[inline(always)] + pub fn tx_crc_lautch_flga_ch(&self) -> TX_CRC_LAUTCH_FLGA_CH_R { + TX_CRC_LAUTCH_FLGA_CH_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CRC_WIDTH_CH") + .field( + "tx_crc_width_ch", + &format_args!("{}", self.tx_crc_width_ch().bits()), + ) + .field( + "tx_crc_lautch_flga_ch", + &format_args!("{}", self.tx_crc_lautch_flga_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_crc_width_ch(&mut self) -> TX_CRC_WIDTH_CH_W { + TX_CRC_WIDTH_CH_W::new(self, 0) + } + #[doc = "Bit 2 - reserved"] + #[inline(always)] + #[must_use] + pub fn tx_crc_lautch_flga_ch(&mut self) -> TX_CRC_LAUTCH_FLGA_CH_W { + TX_CRC_LAUTCH_FLGA_CH_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc_width_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_crc_width_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CRC_WIDTH_CH_SPEC; +impl crate::RegisterSpec for TX_CRC_WIDTH_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_crc_width_ch::R`](R) reader structure"] +impl crate::Readable for TX_CRC_WIDTH_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_crc_width_ch::W`](W) writer structure"] +impl crate::Writable for TX_CRC_WIDTH_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CRC_WIDTH_CH%s to value 0"] +impl crate::Resettable for TX_CRC_WIDTH_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/weight_en.rs b/esp32p4/src/axi_dma/weight_en.rs new file mode 100644 index 0000000000..6f0de21ffc --- /dev/null +++ b/esp32p4/src/axi_dma/weight_en.rs @@ -0,0 +1,79 @@ +#[doc = "Register `WEIGHT_EN` reader"] +pub type R = crate::R; +#[doc = "Register `WEIGHT_EN` writer"] +pub type W = crate::W; +#[doc = "Field `TX` reader - This register is used to config tx arbiter weight function off/on"] +pub type TX_R = crate::BitReader; +#[doc = "Field `TX` writer - This register is used to config tx arbiter weight function off/on"] +pub type TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX` reader - This register is used to config rx arbiter weight function off/on"] +pub type RX_R = crate::BitReader; +#[doc = "Field `RX` writer - This register is used to config rx arbiter weight function off/on"] +pub type RX_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This register is used to config tx arbiter weight function off/on"] + #[inline(always)] + pub fn tx(&self) -> TX_R { + TX_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This register is used to config rx arbiter weight function off/on"] + #[inline(always)] + pub fn rx(&self) -> RX_R { + RX_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WEIGHT_EN") + .field("tx", &format_args!("{}", self.tx().bit())) + .field("rx", &format_args!("{}", self.rx().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This register is used to config tx arbiter weight function off/on"] + #[inline(always)] + #[must_use] + pub fn tx(&mut self) -> TX_W { + TX_W::new(self, 0) + } + #[doc = "Bit 1 - This register is used to config rx arbiter weight function off/on"] + #[inline(always)] + #[must_use] + pub fn rx(&mut self) -> RX_W { + RX_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "This register is used to config arbiter weight function to on or off\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`weight_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`weight_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WEIGHT_EN_SPEC; +impl crate::RegisterSpec for WEIGHT_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`weight_en::R`](R) reader structure"] +impl crate::Readable for WEIGHT_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`weight_en::W`](W) writer structure"] +impl crate::Writable for WEIGHT_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WEIGHT_EN to value 0"] +impl crate::Resettable for WEIGHT_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_dma/wresp_cnt.rs b/esp32p4/src/axi_dma/wresp_cnt.rs new file mode 100644 index 0000000000..bd9e9f652e --- /dev/null +++ b/esp32p4/src/axi_dma/wresp_cnt.rs @@ -0,0 +1,36 @@ +#[doc = "Register `WRESP_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `WRESP_CNT` reader - axi wr responce cnt reg."] +pub type WRESP_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - axi wr responce cnt reg."] + #[inline(always)] + pub fn wresp_cnt(&self) -> WRESP_CNT_R { + WRESP_CNT_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WRESP_CNT") + .field("wresp_cnt", &format_args!("{}", self.wresp_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "AXI wr responce cnt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wresp_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WRESP_CNT_SPEC; +impl crate::RegisterSpec for WRESP_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wresp_cnt::R`](R) reader structure"] +impl crate::Readable for WRESP_CNT_SPEC {} +#[doc = "`reset()` method sets WRESP_CNT to value 0"] +impl crate::Resettable for WRESP_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_icm.rs b/esp32p4/src/axi_icm.rs new file mode 100644 index 0000000000..dda206ee1c --- /dev/null +++ b/esp32p4/src/axi_icm.rs @@ -0,0 +1,47 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + verid_fileds: VERID_FILEDS, + hw_cfg: HW_CFG, + cmd: CMD, + data: DATA, +} +impl RegisterBlock { + #[doc = "0x00 - NA"] + #[inline(always)] + pub const fn verid_fileds(&self) -> &VERID_FILEDS { + &self.verid_fileds + } + #[doc = "0x04 - NA"] + #[inline(always)] + pub const fn hw_cfg(&self) -> &HW_CFG { + &self.hw_cfg + } + #[doc = "0x08 - NA"] + #[inline(always)] + pub const fn cmd(&self) -> &CMD { + &self.cmd + } + #[doc = "0x0c - NA"] + #[inline(always)] + pub const fn data(&self) -> &DATA { + &self.data + } +} +#[doc = "VERID_FILEDS (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`verid_fileds::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid_fileds`] module"] +pub type VERID_FILEDS = crate::Reg; +#[doc = "NA"] +pub mod verid_fileds; +#[doc = "HW_CFG (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_cfg::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_cfg`] module"] +pub type HW_CFG = crate::Reg; +#[doc = "NA"] +pub mod hw_cfg; +#[doc = "CMD (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"] +pub type CMD = crate::Reg; +#[doc = "NA"] +pub mod cmd; +#[doc = "DATA (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +pub type DATA = crate::Reg; +#[doc = "NA"] +pub mod data; diff --git a/esp32p4/src/axi_icm/cmd.rs b/esp32p4/src/axi_icm/cmd.rs new file mode 100644 index 0000000000..7b82b2a54b --- /dev/null +++ b/esp32p4/src/axi_icm/cmd.rs @@ -0,0 +1,172 @@ +#[doc = "Register `CMD` reader"] +pub type R = crate::R; +#[doc = "Register `CMD` writer"] +pub type W = crate::W; +#[doc = "Field `ICM_REG_AXI_CMD` reader - NA"] +pub type ICM_REG_AXI_CMD_R = crate::FieldReader; +#[doc = "Field `ICM_REG_AXI_CMD` writer - NA"] +pub type ICM_REG_AXI_CMD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ICM_REG_RD_WR_CHAN` reader - NA"] +pub type ICM_REG_RD_WR_CHAN_R = crate::BitReader; +#[doc = "Field `ICM_REG_RD_WR_CHAN` writer - NA"] +pub type ICM_REG_RD_WR_CHAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ICM_REG_AXI_MASTER_PORT` reader - NA"] +pub type ICM_REG_AXI_MASTER_PORT_R = crate::FieldReader; +#[doc = "Field `ICM_REG_AXI_MASTER_PORT` writer - NA"] +pub type ICM_REG_AXI_MASTER_PORT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ICM_REG_AXI_ERR_BIT` reader - NA"] +pub type ICM_REG_AXI_ERR_BIT_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_SOFT_RESET_BIT` reader - NA"] +pub type ICM_REG_AXI_SOFT_RESET_BIT_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_SOFT_RESET_BIT` writer - NA"] +pub type ICM_REG_AXI_SOFT_RESET_BIT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ICM_REG_AXI_RD_WR_CMD` reader - NA"] +pub type ICM_REG_AXI_RD_WR_CMD_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_RD_WR_CMD` writer - NA"] +pub type ICM_REG_AXI_RD_WR_CMD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ICM_REG_AXI_CMD_EN` reader - NA"] +pub type ICM_REG_AXI_CMD_EN_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_CMD_EN` writer - NA"] +pub type ICM_REG_AXI_CMD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + pub fn icm_reg_axi_cmd(&self) -> ICM_REG_AXI_CMD_R { + ICM_REG_AXI_CMD_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn icm_reg_rd_wr_chan(&self) -> ICM_REG_RD_WR_CHAN_R { + ICM_REG_RD_WR_CHAN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - NA"] + #[inline(always)] + pub fn icm_reg_axi_master_port(&self) -> ICM_REG_AXI_MASTER_PORT_R { + ICM_REG_AXI_MASTER_PORT_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn icm_reg_axi_err_bit(&self) -> ICM_REG_AXI_ERR_BIT_R { + ICM_REG_AXI_ERR_BIT_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn icm_reg_axi_soft_reset_bit(&self) -> ICM_REG_AXI_SOFT_RESET_BIT_R { + ICM_REG_AXI_SOFT_RESET_BIT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn icm_reg_axi_rd_wr_cmd(&self) -> ICM_REG_AXI_RD_WR_CMD_R { + ICM_REG_AXI_RD_WR_CMD_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn icm_reg_axi_cmd_en(&self) -> ICM_REG_AXI_CMD_EN_R { + ICM_REG_AXI_CMD_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CMD") + .field( + "icm_reg_axi_cmd", + &format_args!("{}", self.icm_reg_axi_cmd().bits()), + ) + .field( + "icm_reg_rd_wr_chan", + &format_args!("{}", self.icm_reg_rd_wr_chan().bit()), + ) + .field( + "icm_reg_axi_master_port", + &format_args!("{}", self.icm_reg_axi_master_port().bits()), + ) + .field( + "icm_reg_axi_err_bit", + &format_args!("{}", self.icm_reg_axi_err_bit().bit()), + ) + .field( + "icm_reg_axi_soft_reset_bit", + &format_args!("{}", self.icm_reg_axi_soft_reset_bit().bit()), + ) + .field( + "icm_reg_axi_rd_wr_cmd", + &format_args!("{}", self.icm_reg_axi_rd_wr_cmd().bit()), + ) + .field( + "icm_reg_axi_cmd_en", + &format_args!("{}", self.icm_reg_axi_cmd_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + #[must_use] + pub fn icm_reg_axi_cmd(&mut self) -> ICM_REG_AXI_CMD_W { + ICM_REG_AXI_CMD_W::new(self, 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn icm_reg_rd_wr_chan(&mut self) -> ICM_REG_RD_WR_CHAN_W { + ICM_REG_RD_WR_CHAN_W::new(self, 7) + } + #[doc = "Bits 8:11 - NA"] + #[inline(always)] + #[must_use] + pub fn icm_reg_axi_master_port(&mut self) -> ICM_REG_AXI_MASTER_PORT_W { + ICM_REG_AXI_MASTER_PORT_W::new(self, 8) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn icm_reg_axi_soft_reset_bit(&mut self) -> ICM_REG_AXI_SOFT_RESET_BIT_W { + ICM_REG_AXI_SOFT_RESET_BIT_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn icm_reg_axi_rd_wr_cmd(&mut self) -> ICM_REG_AXI_RD_WR_CMD_W { + ICM_REG_AXI_RD_WR_CMD_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn icm_reg_axi_cmd_en(&mut self) -> ICM_REG_AXI_CMD_EN_W { + ICM_REG_AXI_CMD_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CMD_SPEC; +impl crate::RegisterSpec for CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmd::R`](R) reader structure"] +impl crate::Readable for CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"] +impl crate::Writable for CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMD to value 0"] +impl crate::Resettable for CMD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_icm/data.rs b/esp32p4/src/axi_icm/data.rs new file mode 100644 index 0000000000..c7348d2d84 --- /dev/null +++ b/esp32p4/src/axi_icm/data.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[doc = "Field `ICM_REG_DATA` reader - NA"] +pub type ICM_REG_DATA_R = crate::FieldReader; +#[doc = "Field `ICM_REG_DATA` writer - NA"] +pub type ICM_REG_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn icm_reg_data(&self) -> ICM_REG_DATA_R { + ICM_REG_DATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA") + .field( + "icm_reg_data", + &format_args!("{}", self.icm_reg_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn icm_reg_data(&mut self) -> ICM_REG_DATA_W { + ICM_REG_DATA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DATA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/axi_icm/hw_cfg.rs b/esp32p4/src/axi_icm/hw_cfg.rs new file mode 100644 index 0000000000..0d91202ee1 --- /dev/null +++ b/esp32p4/src/axi_icm/hw_cfg.rs @@ -0,0 +1,149 @@ +#[doc = "Register `HW_CFG` reader"] +pub type R = crate::R; +#[doc = "Field `ICM_REG_AXI_HWCFG_QOS_SUPPORT` reader - NA"] +pub type ICM_REG_AXI_HWCFG_QOS_SUPPORT_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_HWCFG_APB3_SUPPORT` reader - NA"] +pub type ICM_REG_AXI_HWCFG_APB3_SUPPORT_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_HWCFG_AXI4_SUPPORT` reader - NA"] +pub type ICM_REG_AXI_HWCFG_AXI4_SUPPORT_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_HWCFG_LOCK_EN` reader - NA"] +pub type ICM_REG_AXI_HWCFG_LOCK_EN_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_HWCFG_TRUST_ZONE_EN` reader - NA"] +pub type ICM_REG_AXI_HWCFG_TRUST_ZONE_EN_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_HWCFG_DECODER_TYPE` reader - NA"] +pub type ICM_REG_AXI_HWCFG_DECODER_TYPE_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_HWCFG_REMAP_EN` reader - NA"] +pub type ICM_REG_AXI_HWCFG_REMAP_EN_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN` reader - NA"] +pub type ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN` reader - NA"] +pub type ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN_R = crate::BitReader; +#[doc = "Field `ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS` reader - NA"] +pub type ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS_R = crate::FieldReader; +#[doc = "Field `ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES` reader - NA"] +pub type ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn icm_reg_axi_hwcfg_qos_support(&self) -> ICM_REG_AXI_HWCFG_QOS_SUPPORT_R { + ICM_REG_AXI_HWCFG_QOS_SUPPORT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn icm_reg_axi_hwcfg_apb3_support(&self) -> ICM_REG_AXI_HWCFG_APB3_SUPPORT_R { + ICM_REG_AXI_HWCFG_APB3_SUPPORT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn icm_reg_axi_hwcfg_axi4_support(&self) -> ICM_REG_AXI_HWCFG_AXI4_SUPPORT_R { + ICM_REG_AXI_HWCFG_AXI4_SUPPORT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn icm_reg_axi_hwcfg_lock_en(&self) -> ICM_REG_AXI_HWCFG_LOCK_EN_R { + ICM_REG_AXI_HWCFG_LOCK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn icm_reg_axi_hwcfg_trust_zone_en(&self) -> ICM_REG_AXI_HWCFG_TRUST_ZONE_EN_R { + ICM_REG_AXI_HWCFG_TRUST_ZONE_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn icm_reg_axi_hwcfg_decoder_type(&self) -> ICM_REG_AXI_HWCFG_DECODER_TYPE_R { + ICM_REG_AXI_HWCFG_DECODER_TYPE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn icm_reg_axi_hwcfg_remap_en(&self) -> ICM_REG_AXI_HWCFG_REMAP_EN_R { + ICM_REG_AXI_HWCFG_REMAP_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn icm_reg_axi_hwcfg_bi_dir_cmd_en(&self) -> ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN_R { + ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn icm_reg_axi_hwcfg_low_power_inf_en(&self) -> ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN_R { + ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 12:16 - NA"] + #[inline(always)] + pub fn icm_reg_axi_hwcfg_axi_num_masters(&self) -> ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS_R { + ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 20:24 - NA"] + #[inline(always)] + pub fn icm_reg_axi_hwcfg_axi_num_slaves(&self) -> ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES_R { + ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES_R::new(((self.bits >> 20) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HW_CFG") + .field( + "icm_reg_axi_hwcfg_qos_support", + &format_args!("{}", self.icm_reg_axi_hwcfg_qos_support().bit()), + ) + .field( + "icm_reg_axi_hwcfg_apb3_support", + &format_args!("{}", self.icm_reg_axi_hwcfg_apb3_support().bit()), + ) + .field( + "icm_reg_axi_hwcfg_axi4_support", + &format_args!("{}", self.icm_reg_axi_hwcfg_axi4_support().bit()), + ) + .field( + "icm_reg_axi_hwcfg_lock_en", + &format_args!("{}", self.icm_reg_axi_hwcfg_lock_en().bit()), + ) + .field( + "icm_reg_axi_hwcfg_trust_zone_en", + &format_args!("{}", self.icm_reg_axi_hwcfg_trust_zone_en().bit()), + ) + .field( + "icm_reg_axi_hwcfg_decoder_type", + &format_args!("{}", self.icm_reg_axi_hwcfg_decoder_type().bit()), + ) + .field( + "icm_reg_axi_hwcfg_remap_en", + &format_args!("{}", self.icm_reg_axi_hwcfg_remap_en().bit()), + ) + .field( + "icm_reg_axi_hwcfg_bi_dir_cmd_en", + &format_args!("{}", self.icm_reg_axi_hwcfg_bi_dir_cmd_en().bit()), + ) + .field( + "icm_reg_axi_hwcfg_low_power_inf_en", + &format_args!("{}", self.icm_reg_axi_hwcfg_low_power_inf_en().bit()), + ) + .field( + "icm_reg_axi_hwcfg_axi_num_masters", + &format_args!("{}", self.icm_reg_axi_hwcfg_axi_num_masters().bits()), + ) + .field( + "icm_reg_axi_hwcfg_axi_num_slaves", + &format_args!("{}", self.icm_reg_axi_hwcfg_axi_num_slaves().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_cfg::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HW_CFG_SPEC; +impl crate::RegisterSpec for HW_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hw_cfg::R`](R) reader structure"] +impl crate::Readable for HW_CFG_SPEC {} +#[doc = "`reset()` method sets HW_CFG to value 0x0070_d151"] +impl crate::Resettable for HW_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0070_d151; +} diff --git a/esp32p4/src/axi_icm/verid_fileds.rs b/esp32p4/src/axi_icm/verid_fileds.rs new file mode 100644 index 0000000000..87459cf55f --- /dev/null +++ b/esp32p4/src/axi_icm/verid_fileds.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VERID_FILEDS` reader"] +pub type R = crate::R; +#[doc = "Field `ICM_REG_VERID` reader - NA"] +pub type ICM_REG_VERID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn icm_reg_verid(&self) -> ICM_REG_VERID_R { + ICM_REG_VERID_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VERID_FILEDS") + .field( + "icm_reg_verid", + &format_args!("{}", self.icm_reg_verid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`verid_fileds::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VERID_FILEDS_SPEC; +impl crate::RegisterSpec for VERID_FILEDS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid_fileds::R`](R) reader structure"] +impl crate::Readable for VERID_FILEDS_SPEC {} +#[doc = "`reset()` method sets VERID_FILEDS to value 0x3430_342a"] +impl crate::Resettable for VERID_FILEDS_SPEC { + const RESET_VALUE: Self::Ux = 0x3430_342a; +} diff --git a/esp32p4/src/bitscrambler.rs b/esp32p4/src/bitscrambler.rs new file mode 100644 index 0000000000..b77be5ef0f --- /dev/null +++ b/esp32p4/src/bitscrambler.rs @@ -0,0 +1,168 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + tx_inst_cfg0: TX_INST_CFG0, + tx_inst_cfg1: TX_INST_CFG1, + rx_inst_cfg0: RX_INST_CFG0, + rx_inst_cfg1: RX_INST_CFG1, + tx_lut_cfg0: TX_LUT_CFG0, + tx_lut_cfg1: TX_LUT_CFG1, + rx_lut_cfg0: RX_LUT_CFG0, + rx_lut_cfg1: RX_LUT_CFG1, + tx_tailing_bits: TX_TAILING_BITS, + rx_tailing_bits: RX_TAILING_BITS, + tx_ctrl: TX_CTRL, + rx_ctrl: RX_CTRL, + tx_state: TX_STATE, + rx_state: RX_STATE, + _reserved14: [u8; 0xc0], + sys: SYS, + version: VERSION, +} +impl RegisterBlock { + #[doc = "0x00 - Control and configuration registers"] + #[inline(always)] + pub const fn tx_inst_cfg0(&self) -> &TX_INST_CFG0 { + &self.tx_inst_cfg0 + } + #[doc = "0x04 - Control and configuration registers"] + #[inline(always)] + pub const fn tx_inst_cfg1(&self) -> &TX_INST_CFG1 { + &self.tx_inst_cfg1 + } + #[doc = "0x08 - Control and configuration registers"] + #[inline(always)] + pub const fn rx_inst_cfg0(&self) -> &RX_INST_CFG0 { + &self.rx_inst_cfg0 + } + #[doc = "0x0c - Control and configuration registers"] + #[inline(always)] + pub const fn rx_inst_cfg1(&self) -> &RX_INST_CFG1 { + &self.rx_inst_cfg1 + } + #[doc = "0x10 - Control and configuration registers"] + #[inline(always)] + pub const fn tx_lut_cfg0(&self) -> &TX_LUT_CFG0 { + &self.tx_lut_cfg0 + } + #[doc = "0x14 - Control and configuration registers"] + #[inline(always)] + pub const fn tx_lut_cfg1(&self) -> &TX_LUT_CFG1 { + &self.tx_lut_cfg1 + } + #[doc = "0x18 - Control and configuration registers"] + #[inline(always)] + pub const fn rx_lut_cfg0(&self) -> &RX_LUT_CFG0 { + &self.rx_lut_cfg0 + } + #[doc = "0x1c - Control and configuration registers"] + #[inline(always)] + pub const fn rx_lut_cfg1(&self) -> &RX_LUT_CFG1 { + &self.rx_lut_cfg1 + } + #[doc = "0x20 - Control and configuration registers"] + #[inline(always)] + pub const fn tx_tailing_bits(&self) -> &TX_TAILING_BITS { + &self.tx_tailing_bits + } + #[doc = "0x24 - Control and configuration registers"] + #[inline(always)] + pub const fn rx_tailing_bits(&self) -> &RX_TAILING_BITS { + &self.rx_tailing_bits + } + #[doc = "0x28 - Control and configuration registers"] + #[inline(always)] + pub const fn tx_ctrl(&self) -> &TX_CTRL { + &self.tx_ctrl + } + #[doc = "0x2c - Control and configuration registers"] + #[inline(always)] + pub const fn rx_ctrl(&self) -> &RX_CTRL { + &self.rx_ctrl + } + #[doc = "0x30 - Status registers"] + #[inline(always)] + pub const fn tx_state(&self) -> &TX_STATE { + &self.tx_state + } + #[doc = "0x34 - Status registers"] + #[inline(always)] + pub const fn rx_state(&self) -> &RX_STATE { + &self.rx_state + } + #[doc = "0xf8 - Control and configuration registers"] + #[inline(always)] + pub const fn sys(&self) -> &SYS { + &self.sys + } + #[doc = "0xfc - Control and configuration registers"] + #[inline(always)] + pub const fn version(&self) -> &VERSION { + &self.version + } +} +#[doc = "TX_INST_CFG0 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_inst_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_inst_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_inst_cfg0`] module"] +pub type TX_INST_CFG0 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod tx_inst_cfg0; +#[doc = "TX_INST_CFG1 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_inst_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_inst_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_inst_cfg1`] module"] +pub type TX_INST_CFG1 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod tx_inst_cfg1; +#[doc = "RX_INST_CFG0 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_inst_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_inst_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_inst_cfg0`] module"] +pub type RX_INST_CFG0 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod rx_inst_cfg0; +#[doc = "RX_INST_CFG1 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_inst_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_inst_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_inst_cfg1`] module"] +pub type RX_INST_CFG1 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod rx_inst_cfg1; +#[doc = "TX_LUT_CFG0 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_lut_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_lut_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_lut_cfg0`] module"] +pub type TX_LUT_CFG0 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod tx_lut_cfg0; +#[doc = "TX_LUT_CFG1 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_lut_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_lut_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_lut_cfg1`] module"] +pub type TX_LUT_CFG1 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod tx_lut_cfg1; +#[doc = "RX_LUT_CFG0 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_lut_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_lut_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_lut_cfg0`] module"] +pub type RX_LUT_CFG0 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod rx_lut_cfg0; +#[doc = "RX_LUT_CFG1 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_lut_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_lut_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_lut_cfg1`] module"] +pub type RX_LUT_CFG1 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod rx_lut_cfg1; +#[doc = "TX_TAILING_BITS (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tailing_bits::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tailing_bits::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tailing_bits`] module"] +pub type TX_TAILING_BITS = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod tx_tailing_bits; +#[doc = "RX_TAILING_BITS (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tailing_bits::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tailing_bits::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tailing_bits`] module"] +pub type RX_TAILING_BITS = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod rx_tailing_bits; +#[doc = "TX_CTRL (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_ctrl`] module"] +pub type TX_CTRL = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod tx_ctrl; +#[doc = "RX_CTRL (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_ctrl`] module"] +pub type RX_CTRL = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod rx_ctrl; +#[doc = "TX_STATE (rw) register accessor: Status registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_state::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_state`] module"] +pub type TX_STATE = crate::Reg; +#[doc = "Status registers"] +pub mod tx_state; +#[doc = "RX_STATE (rw) register accessor: Status registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_state::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_state`] module"] +pub type RX_STATE = crate::Reg; +#[doc = "Status registers"] +pub mod rx_state; +#[doc = "SYS (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys`] module"] +pub type SYS = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod sys; +#[doc = "VERSION (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"] +pub type VERSION = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod version; diff --git a/esp32p4/src/bitscrambler/rx_ctrl.rs b/esp32p4/src/bitscrambler/rx_ctrl.rs new file mode 100644 index 0000000000..4d5adde6eb --- /dev/null +++ b/esp32p4/src/bitscrambler/rx_ctrl.rs @@ -0,0 +1,192 @@ +#[doc = "Register `RX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `RX_ENA` reader - write this bit to enable the bitscrambler rx"] +pub type RX_ENA_R = crate::BitReader; +#[doc = "Field `RX_ENA` writer - write this bit to enable the bitscrambler rx"] +pub type RX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PAUSE` reader - write this bit to pause the bitscrambler rx core"] +pub type RX_PAUSE_R = crate::BitReader; +#[doc = "Field `RX_PAUSE` writer - write this bit to pause the bitscrambler rx core"] +pub type RX_PAUSE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_HALT` reader - write this bit to halt the bitscrambler rx core"] +pub type RX_HALT_R = crate::BitReader; +#[doc = "Field `RX_HALT` writer - write this bit to halt the bitscrambler rx core"] +pub type RX_HALT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_EOF_MODE` reader - write this bit to ser the bitscrambler rx core EOF signal generating mode which is combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral buffer, 0 counter by write dma fifo"] +pub type RX_EOF_MODE_R = crate::BitReader; +#[doc = "Field `RX_EOF_MODE` writer - write this bit to ser the bitscrambler rx core EOF signal generating mode which is combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral buffer, 0 counter by write dma fifo"] +pub type RX_EOF_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_COND_MODE` reader - write this bit to specify the LOOP instruction condition mode of bitscrambler rx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition"] +pub type RX_COND_MODE_R = crate::BitReader; +#[doc = "Field `RX_COND_MODE` writer - write this bit to specify the LOOP instruction condition mode of bitscrambler rx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition"] +pub type RX_COND_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FETCH_MODE` reader - write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions"] +pub type RX_FETCH_MODE_R = crate::BitReader; +#[doc = "Field `RX_FETCH_MODE` writer - write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions"] +pub type RX_FETCH_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_HALT_MODE` reader - write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: wait write data back done, , 1: ignore write data back"] +pub type RX_HALT_MODE_R = crate::BitReader; +#[doc = "Field `RX_HALT_MODE` writer - write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: wait write data back done, , 1: ignore write data back"] +pub type RX_HALT_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_RD_DUMMY` reader - write this bit to set the bitscrambler rx core read data mode when EOF received.0: wait read data, 1: ignore read data"] +pub type RX_RD_DUMMY_R = crate::BitReader; +#[doc = "Field `RX_RD_DUMMY` writer - write this bit to set the bitscrambler rx core read data mode when EOF received.0: wait read data, 1: ignore read data"] +pub type RX_RD_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFO_RST` writer - write this bit to reset the bitscrambler rx fifo"] +pub type RX_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - write this bit to enable the bitscrambler rx"] + #[inline(always)] + pub fn rx_ena(&self) -> RX_ENA_R { + RX_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - write this bit to pause the bitscrambler rx core"] + #[inline(always)] + pub fn rx_pause(&self) -> RX_PAUSE_R { + RX_PAUSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - write this bit to halt the bitscrambler rx core"] + #[inline(always)] + pub fn rx_halt(&self) -> RX_HALT_R { + RX_HALT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - write this bit to ser the bitscrambler rx core EOF signal generating mode which is combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral buffer, 0 counter by write dma fifo"] + #[inline(always)] + pub fn rx_eof_mode(&self) -> RX_EOF_MODE_R { + RX_EOF_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - write this bit to specify the LOOP instruction condition mode of bitscrambler rx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition"] + #[inline(always)] + pub fn rx_cond_mode(&self) -> RX_COND_MODE_R { + RX_COND_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions"] + #[inline(always)] + pub fn rx_fetch_mode(&self) -> RX_FETCH_MODE_R { + RX_FETCH_MODE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: wait write data back done, , 1: ignore write data back"] + #[inline(always)] + pub fn rx_halt_mode(&self) -> RX_HALT_MODE_R { + RX_HALT_MODE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - write this bit to set the bitscrambler rx core read data mode when EOF received.0: wait read data, 1: ignore read data"] + #[inline(always)] + pub fn rx_rd_dummy(&self) -> RX_RD_DUMMY_R { + RX_RD_DUMMY_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CTRL") + .field("rx_ena", &format_args!("{}", self.rx_ena().bit())) + .field("rx_pause", &format_args!("{}", self.rx_pause().bit())) + .field("rx_halt", &format_args!("{}", self.rx_halt().bit())) + .field("rx_eof_mode", &format_args!("{}", self.rx_eof_mode().bit())) + .field( + "rx_cond_mode", + &format_args!("{}", self.rx_cond_mode().bit()), + ) + .field( + "rx_fetch_mode", + &format_args!("{}", self.rx_fetch_mode().bit()), + ) + .field( + "rx_halt_mode", + &format_args!("{}", self.rx_halt_mode().bit()), + ) + .field("rx_rd_dummy", &format_args!("{}", self.rx_rd_dummy().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - write this bit to enable the bitscrambler rx"] + #[inline(always)] + #[must_use] + pub fn rx_ena(&mut self) -> RX_ENA_W { + RX_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - write this bit to pause the bitscrambler rx core"] + #[inline(always)] + #[must_use] + pub fn rx_pause(&mut self) -> RX_PAUSE_W { + RX_PAUSE_W::new(self, 1) + } + #[doc = "Bit 2 - write this bit to halt the bitscrambler rx core"] + #[inline(always)] + #[must_use] + pub fn rx_halt(&mut self) -> RX_HALT_W { + RX_HALT_W::new(self, 2) + } + #[doc = "Bit 3 - write this bit to ser the bitscrambler rx core EOF signal generating mode which is combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral buffer, 0 counter by write dma fifo"] + #[inline(always)] + #[must_use] + pub fn rx_eof_mode(&mut self) -> RX_EOF_MODE_W { + RX_EOF_MODE_W::new(self, 3) + } + #[doc = "Bit 4 - write this bit to specify the LOOP instruction condition mode of bitscrambler rx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition"] + #[inline(always)] + #[must_use] + pub fn rx_cond_mode(&mut self) -> RX_COND_MODE_W { + RX_COND_MODE_W::new(self, 4) + } + #[doc = "Bit 5 - write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions"] + #[inline(always)] + #[must_use] + pub fn rx_fetch_mode(&mut self) -> RX_FETCH_MODE_W { + RX_FETCH_MODE_W::new(self, 5) + } + #[doc = "Bit 6 - write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: wait write data back done, , 1: ignore write data back"] + #[inline(always)] + #[must_use] + pub fn rx_halt_mode(&mut self) -> RX_HALT_MODE_W { + RX_HALT_MODE_W::new(self, 6) + } + #[doc = "Bit 7 - write this bit to set the bitscrambler rx core read data mode when EOF received.0: wait read data, 1: ignore read data"] + #[inline(always)] + #[must_use] + pub fn rx_rd_dummy(&mut self) -> RX_RD_DUMMY_W { + RX_RD_DUMMY_W::new(self, 7) + } + #[doc = "Bit 8 - write this bit to reset the bitscrambler rx fifo"] + #[inline(always)] + #[must_use] + pub fn rx_fifo_rst(&mut self) -> RX_FIFO_RST_W { + RX_FIFO_RST_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CTRL_SPEC; +impl crate::RegisterSpec for RX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_ctrl::R`](R) reader structure"] +impl crate::Readable for RX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_ctrl::W`](W) writer structure"] +impl crate::Writable for RX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CTRL to value 0x04"] +impl crate::Resettable for RX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/bitscrambler/rx_inst_cfg0.rs b/esp32p4/src/bitscrambler/rx_inst_cfg0.rs new file mode 100644 index 0000000000..5ab5fe41a0 --- /dev/null +++ b/esp32p4/src/bitscrambler/rx_inst_cfg0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `RX_INST_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `RX_INST_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `RX_INST_IDX` reader - write this bits to specify the one of 8 instruction"] +pub type RX_INST_IDX_R = crate::FieldReader; +#[doc = "Field `RX_INST_IDX` writer - write this bits to specify the one of 8 instruction"] +pub type RX_INST_IDX_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `RX_INST_POS` reader - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits"] +pub type RX_INST_POS_R = crate::FieldReader; +#[doc = "Field `RX_INST_POS` writer - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits"] +pub type RX_INST_POS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:2 - write this bits to specify the one of 8 instruction"] + #[inline(always)] + pub fn rx_inst_idx(&self) -> RX_INST_IDX_R { + RX_INST_IDX_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:6 - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits"] + #[inline(always)] + pub fn rx_inst_pos(&self) -> RX_INST_POS_R { + RX_INST_POS_R::new(((self.bits >> 3) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_INST_CFG0") + .field( + "rx_inst_idx", + &format_args!("{}", self.rx_inst_idx().bits()), + ) + .field( + "rx_inst_pos", + &format_args!("{}", self.rx_inst_pos().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - write this bits to specify the one of 8 instruction"] + #[inline(always)] + #[must_use] + pub fn rx_inst_idx(&mut self) -> RX_INST_IDX_W { + RX_INST_IDX_W::new(self, 0) + } + #[doc = "Bits 3:6 - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits"] + #[inline(always)] + #[must_use] + pub fn rx_inst_pos(&mut self) -> RX_INST_POS_W { + RX_INST_POS_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_inst_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_inst_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_INST_CFG0_SPEC; +impl crate::RegisterSpec for RX_INST_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_inst_cfg0::R`](R) reader structure"] +impl crate::Readable for RX_INST_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_inst_cfg0::W`](W) writer structure"] +impl crate::Writable for RX_INST_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_INST_CFG0 to value 0"] +impl crate::Resettable for RX_INST_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/bitscrambler/rx_inst_cfg1.rs b/esp32p4/src/bitscrambler/rx_inst_cfg1.rs new file mode 100644 index 0000000000..b32506db34 --- /dev/null +++ b/esp32p4/src/bitscrambler/rx_inst_cfg1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RX_INST_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `RX_INST_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `RX_INST` reader - write this bits to update instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG"] +pub type RX_INST_R = crate::FieldReader; +#[doc = "Field `RX_INST` writer - write this bits to update instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG"] +pub type RX_INST_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - write this bits to update instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG"] + #[inline(always)] + pub fn rx_inst(&self) -> RX_INST_R { + RX_INST_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_INST_CFG1") + .field("rx_inst", &format_args!("{}", self.rx_inst().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - write this bits to update instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG"] + #[inline(always)] + #[must_use] + pub fn rx_inst(&mut self) -> RX_INST_W { + RX_INST_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_inst_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_inst_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_INST_CFG1_SPEC; +impl crate::RegisterSpec for RX_INST_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_inst_cfg1::R`](R) reader structure"] +impl crate::Readable for RX_INST_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_inst_cfg1::W`](W) writer structure"] +impl crate::Writable for RX_INST_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_INST_CFG1 to value 0x0c"] +impl crate::Resettable for RX_INST_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0x0c; +} diff --git a/esp32p4/src/bitscrambler/rx_lut_cfg0.rs b/esp32p4/src/bitscrambler/rx_lut_cfg0.rs new file mode 100644 index 0000000000..6111b886ac --- /dev/null +++ b/esp32p4/src/bitscrambler/rx_lut_cfg0.rs @@ -0,0 +1,82 @@ +#[doc = "Register `RX_LUT_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `RX_LUT_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `RX_LUT_IDX` reader - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_rx_lut_mode"] +pub type RX_LUT_IDX_R = crate::FieldReader; +#[doc = "Field `RX_LUT_IDX` writer - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_rx_lut_mode"] +pub type RX_LUT_IDX_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `RX_LUT_MODE` reader - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes"] +pub type RX_LUT_MODE_R = crate::FieldReader; +#[doc = "Field `RX_LUT_MODE` writer - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes"] +pub type RX_LUT_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:10 - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_rx_lut_mode"] + #[inline(always)] + pub fn rx_lut_idx(&self) -> RX_LUT_IDX_R { + RX_LUT_IDX_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 11:12 - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes"] + #[inline(always)] + pub fn rx_lut_mode(&self) -> RX_LUT_MODE_R { + RX_LUT_MODE_R::new(((self.bits >> 11) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_LUT_CFG0") + .field("rx_lut_idx", &format_args!("{}", self.rx_lut_idx().bits())) + .field( + "rx_lut_mode", + &format_args!("{}", self.rx_lut_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:10 - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_rx_lut_mode"] + #[inline(always)] + #[must_use] + pub fn rx_lut_idx(&mut self) -> RX_LUT_IDX_W { + RX_LUT_IDX_W::new(self, 0) + } + #[doc = "Bits 11:12 - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes"] + #[inline(always)] + #[must_use] + pub fn rx_lut_mode(&mut self) -> RX_LUT_MODE_W { + RX_LUT_MODE_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_lut_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_lut_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_LUT_CFG0_SPEC; +impl crate::RegisterSpec for RX_LUT_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_lut_cfg0::R`](R) reader structure"] +impl crate::Readable for RX_LUT_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_lut_cfg0::W`](W) writer structure"] +impl crate::Writable for RX_LUT_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_LUT_CFG0 to value 0"] +impl crate::Resettable for RX_LUT_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/bitscrambler/rx_lut_cfg1.rs b/esp32p4/src/bitscrambler/rx_lut_cfg1.rs new file mode 100644 index 0000000000..44bba6ffe4 --- /dev/null +++ b/esp32p4/src/bitscrambler/rx_lut_cfg1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RX_LUT_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `RX_LUT_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `RX_LUT` reader - write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG"] +pub type RX_LUT_R = crate::FieldReader; +#[doc = "Field `RX_LUT` writer - write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG"] +pub type RX_LUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG"] + #[inline(always)] + pub fn rx_lut(&self) -> RX_LUT_R { + RX_LUT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_LUT_CFG1") + .field("rx_lut", &format_args!("{}", self.rx_lut().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG"] + #[inline(always)] + #[must_use] + pub fn rx_lut(&mut self) -> RX_LUT_W { + RX_LUT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_lut_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_lut_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_LUT_CFG1_SPEC; +impl crate::RegisterSpec for RX_LUT_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_lut_cfg1::R`](R) reader structure"] +impl crate::Readable for RX_LUT_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_lut_cfg1::W`](W) writer structure"] +impl crate::Writable for RX_LUT_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_LUT_CFG1 to value 0x1c"] +impl crate::Resettable for RX_LUT_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0x1c; +} diff --git a/esp32p4/src/bitscrambler/rx_state.rs b/esp32p4/src/bitscrambler/rx_state.rs new file mode 100644 index 0000000000..052c762406 --- /dev/null +++ b/esp32p4/src/bitscrambler/rx_state.rs @@ -0,0 +1,120 @@ +#[doc = "Register `RX_STATE` reader"] +pub type R = crate::R; +#[doc = "Register `RX_STATE` writer"] +pub type W = crate::W; +#[doc = "Field `RX_IN_IDLE` reader - represents the bitscrambler rx core in halt mode"] +pub type RX_IN_IDLE_R = crate::BitReader; +#[doc = "Field `RX_IN_RUN` reader - represents the bitscrambler rx core in run mode"] +pub type RX_IN_RUN_R = crate::BitReader; +#[doc = "Field `RX_IN_WAIT` reader - represents the bitscrambler rx core in wait mode to wait write back done"] +pub type RX_IN_WAIT_R = crate::BitReader; +#[doc = "Field `RX_IN_PAUSE` reader - represents the bitscrambler rx core in pause mode"] +pub type RX_IN_PAUSE_R = crate::BitReader; +#[doc = "Field `RX_FIFO_FULL` reader - represents the bitscrambler rx fifo in full state"] +pub type RX_FIFO_FULL_R = crate::BitReader; +#[doc = "Field `RX_EOF_GET_CNT` reader - represents the bytes numbers of bitscrambler rx core when get EOF"] +pub type RX_EOF_GET_CNT_R = crate::FieldReader; +#[doc = "Field `RX_EOF_OVERLOAD` reader - represents the some EOFs will be lost for bitscrambler rx core"] +pub type RX_EOF_OVERLOAD_R = crate::BitReader; +#[doc = "Field `RX_EOF_TRACE_CLR` writer - write this bit to clear reg_bitscrambler_rx_eof_overload and reg_bitscrambler_rx_eof_get_cnt registers"] +pub type RX_EOF_TRACE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - represents the bitscrambler rx core in halt mode"] + #[inline(always)] + pub fn rx_in_idle(&self) -> RX_IN_IDLE_R { + RX_IN_IDLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - represents the bitscrambler rx core in run mode"] + #[inline(always)] + pub fn rx_in_run(&self) -> RX_IN_RUN_R { + RX_IN_RUN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - represents the bitscrambler rx core in wait mode to wait write back done"] + #[inline(always)] + pub fn rx_in_wait(&self) -> RX_IN_WAIT_R { + RX_IN_WAIT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - represents the bitscrambler rx core in pause mode"] + #[inline(always)] + pub fn rx_in_pause(&self) -> RX_IN_PAUSE_R { + RX_IN_PAUSE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - represents the bitscrambler rx fifo in full state"] + #[inline(always)] + pub fn rx_fifo_full(&self) -> RX_FIFO_FULL_R { + RX_FIFO_FULL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 16:29 - represents the bytes numbers of bitscrambler rx core when get EOF"] + #[inline(always)] + pub fn rx_eof_get_cnt(&self) -> RX_EOF_GET_CNT_R { + RX_EOF_GET_CNT_R::new(((self.bits >> 16) & 0x3fff) as u16) + } + #[doc = "Bit 30 - represents the some EOFs will be lost for bitscrambler rx core"] + #[inline(always)] + pub fn rx_eof_overload(&self) -> RX_EOF_OVERLOAD_R { + RX_EOF_OVERLOAD_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_STATE") + .field("rx_in_idle", &format_args!("{}", self.rx_in_idle().bit())) + .field("rx_in_run", &format_args!("{}", self.rx_in_run().bit())) + .field("rx_in_wait", &format_args!("{}", self.rx_in_wait().bit())) + .field("rx_in_pause", &format_args!("{}", self.rx_in_pause().bit())) + .field( + "rx_fifo_full", + &format_args!("{}", self.rx_fifo_full().bit()), + ) + .field( + "rx_eof_get_cnt", + &format_args!("{}", self.rx_eof_get_cnt().bits()), + ) + .field( + "rx_eof_overload", + &format_args!("{}", self.rx_eof_overload().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - write this bit to clear reg_bitscrambler_rx_eof_overload and reg_bitscrambler_rx_eof_get_cnt registers"] + #[inline(always)] + #[must_use] + pub fn rx_eof_trace_clr(&mut self) -> RX_EOF_TRACE_CLR_W { + RX_EOF_TRACE_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Status registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_state::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_state::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_STATE_SPEC; +impl crate::RegisterSpec for RX_STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_state::R`](R) reader structure"] +impl crate::Readable for RX_STATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_state::W`](W) writer structure"] +impl crate::Writable for RX_STATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_STATE to value 0x01"] +impl crate::Resettable for RX_STATE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/bitscrambler/rx_tailing_bits.rs b/esp32p4/src/bitscrambler/rx_tailing_bits.rs new file mode 100644 index 0000000000..30f34a42a6 --- /dev/null +++ b/esp32p4/src/bitscrambler/rx_tailing_bits.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RX_TAILING_BITS` reader"] +pub type R = crate::R; +#[doc = "Register `RX_TAILING_BITS` writer"] +pub type W = crate::W; +#[doc = "Field `RX_TAILING_BITS` reader - write this bits to specify the extra data bit length after getting EOF"] +pub type RX_TAILING_BITS_R = crate::FieldReader; +#[doc = "Field `RX_TAILING_BITS` writer - write this bits to specify the extra data bit length after getting EOF"] +pub type RX_TAILING_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - write this bits to specify the extra data bit length after getting EOF"] + #[inline(always)] + pub fn rx_tailing_bits(&self) -> RX_TAILING_BITS_R { + RX_TAILING_BITS_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_TAILING_BITS") + .field( + "rx_tailing_bits", + &format_args!("{}", self.rx_tailing_bits().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - write this bits to specify the extra data bit length after getting EOF"] + #[inline(always)] + #[must_use] + pub fn rx_tailing_bits(&mut self) -> RX_TAILING_BITS_W { + RX_TAILING_BITS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tailing_bits::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tailing_bits::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_TAILING_BITS_SPEC; +impl crate::RegisterSpec for RX_TAILING_BITS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_tailing_bits::R`](R) reader structure"] +impl crate::Readable for RX_TAILING_BITS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_tailing_bits::W`](W) writer structure"] +impl crate::Writable for RX_TAILING_BITS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_TAILING_BITS to value 0"] +impl crate::Resettable for RX_TAILING_BITS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/bitscrambler/sys.rs b/esp32p4/src/bitscrambler/sys.rs new file mode 100644 index 0000000000..c7851ac6ae --- /dev/null +++ b/esp32p4/src/bitscrambler/sys.rs @@ -0,0 +1,79 @@ +#[doc = "Register `SYS` reader"] +pub type R = crate::R; +#[doc = "Register `SYS` writer"] +pub type W = crate::W; +#[doc = "Field `LOOP_MODE` reader - write this bit to set the bitscrambler tx loop back to DMA rx"] +pub type LOOP_MODE_R = crate::BitReader; +#[doc = "Field `LOOP_MODE` writer - write this bit to set the bitscrambler tx loop back to DMA rx"] +pub type LOOP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - Reserved"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Reserved"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - write this bit to set the bitscrambler tx loop back to DMA rx"] + #[inline(always)] + pub fn loop_mode(&self) -> LOOP_MODE_R { + LOOP_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYS") + .field("loop_mode", &format_args!("{}", self.loop_mode().bit())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - write this bit to set the bitscrambler tx loop back to DMA rx"] + #[inline(always)] + #[must_use] + pub fn loop_mode(&mut self) -> LOOP_MODE_W { + LOOP_MODE_W::new(self, 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYS_SPEC; +impl crate::RegisterSpec for SYS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sys::R`](R) reader structure"] +impl crate::Readable for SYS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sys::W`](W) writer structure"] +impl crate::Writable for SYS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYS to value 0"] +impl crate::Resettable for SYS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/bitscrambler/tx_ctrl.rs b/esp32p4/src/bitscrambler/tx_ctrl.rs new file mode 100644 index 0000000000..9603e39764 --- /dev/null +++ b/esp32p4/src/bitscrambler/tx_ctrl.rs @@ -0,0 +1,192 @@ +#[doc = "Register `TX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `TX_ENA` reader - write this bit to enable the bitscrambler tx"] +pub type TX_ENA_R = crate::BitReader; +#[doc = "Field `TX_ENA` writer - write this bit to enable the bitscrambler tx"] +pub type TX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_PAUSE` reader - write this bit to pause the bitscrambler tx core"] +pub type TX_PAUSE_R = crate::BitReader; +#[doc = "Field `TX_PAUSE` writer - write this bit to pause the bitscrambler tx core"] +pub type TX_PAUSE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_HALT` reader - write this bit to halt the bitscrambler tx core"] +pub type TX_HALT_R = crate::BitReader; +#[doc = "Field `TX_HALT` writer - write this bit to halt the bitscrambler tx core"] +pub type TX_HALT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_EOF_MODE` reader - write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer"] +pub type TX_EOF_MODE_R = crate::BitReader; +#[doc = "Field `TX_EOF_MODE` writer - write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer"] +pub type TX_EOF_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_COND_MODE` reader - write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition"] +pub type TX_COND_MODE_R = crate::BitReader; +#[doc = "Field `TX_COND_MODE` writer - write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition"] +pub type TX_COND_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_FETCH_MODE` reader - write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions"] +pub type TX_FETCH_MODE_R = crate::BitReader; +#[doc = "Field `TX_FETCH_MODE` writer - write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions"] +pub type TX_FETCH_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_HALT_MODE` reader - write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back"] +pub type TX_HALT_MODE_R = crate::BitReader; +#[doc = "Field `TX_HALT_MODE` writer - write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back"] +pub type TX_HALT_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_RD_DUMMY` reader - write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data"] +pub type TX_RD_DUMMY_R = crate::BitReader; +#[doc = "Field `TX_RD_DUMMY` writer - write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data"] +pub type TX_RD_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_FIFO_RST` writer - write this bit to reset the bitscrambler tx fifo"] +pub type TX_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - write this bit to enable the bitscrambler tx"] + #[inline(always)] + pub fn tx_ena(&self) -> TX_ENA_R { + TX_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - write this bit to pause the bitscrambler tx core"] + #[inline(always)] + pub fn tx_pause(&self) -> TX_PAUSE_R { + TX_PAUSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - write this bit to halt the bitscrambler tx core"] + #[inline(always)] + pub fn tx_halt(&self) -> TX_HALT_R { + TX_HALT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer"] + #[inline(always)] + pub fn tx_eof_mode(&self) -> TX_EOF_MODE_R { + TX_EOF_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition"] + #[inline(always)] + pub fn tx_cond_mode(&self) -> TX_COND_MODE_R { + TX_COND_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions"] + #[inline(always)] + pub fn tx_fetch_mode(&self) -> TX_FETCH_MODE_R { + TX_FETCH_MODE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back"] + #[inline(always)] + pub fn tx_halt_mode(&self) -> TX_HALT_MODE_R { + TX_HALT_MODE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data"] + #[inline(always)] + pub fn tx_rd_dummy(&self) -> TX_RD_DUMMY_R { + TX_RD_DUMMY_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CTRL") + .field("tx_ena", &format_args!("{}", self.tx_ena().bit())) + .field("tx_pause", &format_args!("{}", self.tx_pause().bit())) + .field("tx_halt", &format_args!("{}", self.tx_halt().bit())) + .field("tx_eof_mode", &format_args!("{}", self.tx_eof_mode().bit())) + .field( + "tx_cond_mode", + &format_args!("{}", self.tx_cond_mode().bit()), + ) + .field( + "tx_fetch_mode", + &format_args!("{}", self.tx_fetch_mode().bit()), + ) + .field( + "tx_halt_mode", + &format_args!("{}", self.tx_halt_mode().bit()), + ) + .field("tx_rd_dummy", &format_args!("{}", self.tx_rd_dummy().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - write this bit to enable the bitscrambler tx"] + #[inline(always)] + #[must_use] + pub fn tx_ena(&mut self) -> TX_ENA_W { + TX_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - write this bit to pause the bitscrambler tx core"] + #[inline(always)] + #[must_use] + pub fn tx_pause(&mut self) -> TX_PAUSE_W { + TX_PAUSE_W::new(self, 1) + } + #[doc = "Bit 2 - write this bit to halt the bitscrambler tx core"] + #[inline(always)] + #[must_use] + pub fn tx_halt(&mut self) -> TX_HALT_W { + TX_HALT_W::new(self, 2) + } + #[doc = "Bit 3 - write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer"] + #[inline(always)] + #[must_use] + pub fn tx_eof_mode(&mut self) -> TX_EOF_MODE_W { + TX_EOF_MODE_W::new(self, 3) + } + #[doc = "Bit 4 - write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition"] + #[inline(always)] + #[must_use] + pub fn tx_cond_mode(&mut self) -> TX_COND_MODE_W { + TX_COND_MODE_W::new(self, 4) + } + #[doc = "Bit 5 - write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions"] + #[inline(always)] + #[must_use] + pub fn tx_fetch_mode(&mut self) -> TX_FETCH_MODE_W { + TX_FETCH_MODE_W::new(self, 5) + } + #[doc = "Bit 6 - write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back"] + #[inline(always)] + #[must_use] + pub fn tx_halt_mode(&mut self) -> TX_HALT_MODE_W { + TX_HALT_MODE_W::new(self, 6) + } + #[doc = "Bit 7 - write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data"] + #[inline(always)] + #[must_use] + pub fn tx_rd_dummy(&mut self) -> TX_RD_DUMMY_W { + TX_RD_DUMMY_W::new(self, 7) + } + #[doc = "Bit 8 - write this bit to reset the bitscrambler tx fifo"] + #[inline(always)] + #[must_use] + pub fn tx_fifo_rst(&mut self) -> TX_FIFO_RST_W { + TX_FIFO_RST_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CTRL_SPEC; +impl crate::RegisterSpec for TX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_ctrl::R`](R) reader structure"] +impl crate::Readable for TX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_ctrl::W`](W) writer structure"] +impl crate::Writable for TX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CTRL to value 0x04"] +impl crate::Resettable for TX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/bitscrambler/tx_inst_cfg0.rs b/esp32p4/src/bitscrambler/tx_inst_cfg0.rs new file mode 100644 index 0000000000..fa9b9c9ce2 --- /dev/null +++ b/esp32p4/src/bitscrambler/tx_inst_cfg0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `TX_INST_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `TX_INST_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `TX_INST_IDX` reader - write this bits to specify the one of 8 instruction"] +pub type TX_INST_IDX_R = crate::FieldReader; +#[doc = "Field `TX_INST_IDX` writer - write this bits to specify the one of 8 instruction"] +pub type TX_INST_IDX_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `TX_INST_POS` reader - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits"] +pub type TX_INST_POS_R = crate::FieldReader; +#[doc = "Field `TX_INST_POS` writer - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits"] +pub type TX_INST_POS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:2 - write this bits to specify the one of 8 instruction"] + #[inline(always)] + pub fn tx_inst_idx(&self) -> TX_INST_IDX_R { + TX_INST_IDX_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:6 - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits"] + #[inline(always)] + pub fn tx_inst_pos(&self) -> TX_INST_POS_R { + TX_INST_POS_R::new(((self.bits >> 3) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_INST_CFG0") + .field( + "tx_inst_idx", + &format_args!("{}", self.tx_inst_idx().bits()), + ) + .field( + "tx_inst_pos", + &format_args!("{}", self.tx_inst_pos().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - write this bits to specify the one of 8 instruction"] + #[inline(always)] + #[must_use] + pub fn tx_inst_idx(&mut self) -> TX_INST_IDX_W { + TX_INST_IDX_W::new(self, 0) + } + #[doc = "Bits 3:6 - write this bits to specify the bit position of 257 bit instruction which in units of 32 bits"] + #[inline(always)] + #[must_use] + pub fn tx_inst_pos(&mut self) -> TX_INST_POS_W { + TX_INST_POS_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_inst_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_inst_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_INST_CFG0_SPEC; +impl crate::RegisterSpec for TX_INST_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_inst_cfg0::R`](R) reader structure"] +impl crate::Readable for TX_INST_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_inst_cfg0::W`](W) writer structure"] +impl crate::Writable for TX_INST_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_INST_CFG0 to value 0"] +impl crate::Resettable for TX_INST_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/bitscrambler/tx_inst_cfg1.rs b/esp32p4/src/bitscrambler/tx_inst_cfg1.rs new file mode 100644 index 0000000000..acac6e6982 --- /dev/null +++ b/esp32p4/src/bitscrambler/tx_inst_cfg1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TX_INST_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `TX_INST_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `TX_INST` reader - write this bits to update instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG"] +pub type TX_INST_R = crate::FieldReader; +#[doc = "Field `TX_INST` writer - write this bits to update instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG"] +pub type TX_INST_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - write this bits to update instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG"] + #[inline(always)] + pub fn tx_inst(&self) -> TX_INST_R { + TX_INST_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_INST_CFG1") + .field("tx_inst", &format_args!("{}", self.tx_inst().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - write this bits to update instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG"] + #[inline(always)] + #[must_use] + pub fn tx_inst(&mut self) -> TX_INST_W { + TX_INST_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_inst_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_inst_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_INST_CFG1_SPEC; +impl crate::RegisterSpec for TX_INST_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_inst_cfg1::R`](R) reader structure"] +impl crate::Readable for TX_INST_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_inst_cfg1::W`](W) writer structure"] +impl crate::Writable for TX_INST_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_INST_CFG1 to value 0x04"] +impl crate::Resettable for TX_INST_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/bitscrambler/tx_lut_cfg0.rs b/esp32p4/src/bitscrambler/tx_lut_cfg0.rs new file mode 100644 index 0000000000..e6877768d7 --- /dev/null +++ b/esp32p4/src/bitscrambler/tx_lut_cfg0.rs @@ -0,0 +1,82 @@ +#[doc = "Register `TX_LUT_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `TX_LUT_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `TX_LUT_IDX` reader - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_tx_lut_mode"] +pub type TX_LUT_IDX_R = crate::FieldReader; +#[doc = "Field `TX_LUT_IDX` writer - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_tx_lut_mode"] +pub type TX_LUT_IDX_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `TX_LUT_MODE` reader - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes"] +pub type TX_LUT_MODE_R = crate::FieldReader; +#[doc = "Field `TX_LUT_MODE` writer - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes"] +pub type TX_LUT_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:10 - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_tx_lut_mode"] + #[inline(always)] + pub fn tx_lut_idx(&self) -> TX_LUT_IDX_R { + TX_LUT_IDX_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 11:12 - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes"] + #[inline(always)] + pub fn tx_lut_mode(&self) -> TX_LUT_MODE_R { + TX_LUT_MODE_R::new(((self.bits >> 11) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_LUT_CFG0") + .field("tx_lut_idx", &format_args!("{}", self.tx_lut_idx().bits())) + .field( + "tx_lut_mode", + &format_args!("{}", self.tx_lut_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:10 - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_tx_lut_mode"] + #[inline(always)] + #[must_use] + pub fn tx_lut_idx(&mut self) -> TX_LUT_IDX_W { + TX_LUT_IDX_W::new(self, 0) + } + #[doc = "Bits 11:12 - write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes"] + #[inline(always)] + #[must_use] + pub fn tx_lut_mode(&mut self) -> TX_LUT_MODE_W { + TX_LUT_MODE_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_lut_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_lut_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_LUT_CFG0_SPEC; +impl crate::RegisterSpec for TX_LUT_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_lut_cfg0::R`](R) reader structure"] +impl crate::Readable for TX_LUT_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_lut_cfg0::W`](W) writer structure"] +impl crate::Writable for TX_LUT_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_LUT_CFG0 to value 0"] +impl crate::Resettable for TX_LUT_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/bitscrambler/tx_lut_cfg1.rs b/esp32p4/src/bitscrambler/tx_lut_cfg1.rs new file mode 100644 index 0000000000..2be16ac525 --- /dev/null +++ b/esp32p4/src/bitscrambler/tx_lut_cfg1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TX_LUT_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `TX_LUT_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `TX_LUT` reader - write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG"] +pub type TX_LUT_R = crate::FieldReader; +#[doc = "Field `TX_LUT` writer - write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG"] +pub type TX_LUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG"] + #[inline(always)] + pub fn tx_lut(&self) -> TX_LUT_R { + TX_LUT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_LUT_CFG1") + .field("tx_lut", &format_args!("{}", self.tx_lut().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG"] + #[inline(always)] + #[must_use] + pub fn tx_lut(&mut self) -> TX_LUT_W { + TX_LUT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_lut_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_lut_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_LUT_CFG1_SPEC; +impl crate::RegisterSpec for TX_LUT_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_lut_cfg1::R`](R) reader structure"] +impl crate::Readable for TX_LUT_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_lut_cfg1::W`](W) writer structure"] +impl crate::Writable for TX_LUT_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_LUT_CFG1 to value 0x14"] +impl crate::Resettable for TX_LUT_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0x14; +} diff --git a/esp32p4/src/bitscrambler/tx_state.rs b/esp32p4/src/bitscrambler/tx_state.rs new file mode 100644 index 0000000000..0b14cbdb5d --- /dev/null +++ b/esp32p4/src/bitscrambler/tx_state.rs @@ -0,0 +1,120 @@ +#[doc = "Register `TX_STATE` reader"] +pub type R = crate::R; +#[doc = "Register `TX_STATE` writer"] +pub type W = crate::W; +#[doc = "Field `TX_IN_IDLE` reader - represents the bitscrambler tx core in halt mode"] +pub type TX_IN_IDLE_R = crate::BitReader; +#[doc = "Field `TX_IN_RUN` reader - represents the bitscrambler tx core in run mode"] +pub type TX_IN_RUN_R = crate::BitReader; +#[doc = "Field `TX_IN_WAIT` reader - represents the bitscrambler tx core in wait mode to wait write back done"] +pub type TX_IN_WAIT_R = crate::BitReader; +#[doc = "Field `TX_IN_PAUSE` reader - represents the bitscrambler tx core in pause mode"] +pub type TX_IN_PAUSE_R = crate::BitReader; +#[doc = "Field `TX_FIFO_EMPTY` reader - represents the bitscrambler tx fifo in empty state"] +pub type TX_FIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `TX_EOF_GET_CNT` reader - represents the bytes numbers of bitscrambler tx core when get EOF"] +pub type TX_EOF_GET_CNT_R = crate::FieldReader; +#[doc = "Field `TX_EOF_OVERLOAD` reader - represents the some EOFs will be lost for bitscrambler tx core"] +pub type TX_EOF_OVERLOAD_R = crate::BitReader; +#[doc = "Field `TX_EOF_TRACE_CLR` writer - write this bit to clear reg_bitscrambler_tx_eof_overload and reg_bitscrambler_tx_eof_get_cnt registers"] +pub type TX_EOF_TRACE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - represents the bitscrambler tx core in halt mode"] + #[inline(always)] + pub fn tx_in_idle(&self) -> TX_IN_IDLE_R { + TX_IN_IDLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - represents the bitscrambler tx core in run mode"] + #[inline(always)] + pub fn tx_in_run(&self) -> TX_IN_RUN_R { + TX_IN_RUN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - represents the bitscrambler tx core in wait mode to wait write back done"] + #[inline(always)] + pub fn tx_in_wait(&self) -> TX_IN_WAIT_R { + TX_IN_WAIT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - represents the bitscrambler tx core in pause mode"] + #[inline(always)] + pub fn tx_in_pause(&self) -> TX_IN_PAUSE_R { + TX_IN_PAUSE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - represents the bitscrambler tx fifo in empty state"] + #[inline(always)] + pub fn tx_fifo_empty(&self) -> TX_FIFO_EMPTY_R { + TX_FIFO_EMPTY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 16:29 - represents the bytes numbers of bitscrambler tx core when get EOF"] + #[inline(always)] + pub fn tx_eof_get_cnt(&self) -> TX_EOF_GET_CNT_R { + TX_EOF_GET_CNT_R::new(((self.bits >> 16) & 0x3fff) as u16) + } + #[doc = "Bit 30 - represents the some EOFs will be lost for bitscrambler tx core"] + #[inline(always)] + pub fn tx_eof_overload(&self) -> TX_EOF_OVERLOAD_R { + TX_EOF_OVERLOAD_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_STATE") + .field("tx_in_idle", &format_args!("{}", self.tx_in_idle().bit())) + .field("tx_in_run", &format_args!("{}", self.tx_in_run().bit())) + .field("tx_in_wait", &format_args!("{}", self.tx_in_wait().bit())) + .field("tx_in_pause", &format_args!("{}", self.tx_in_pause().bit())) + .field( + "tx_fifo_empty", + &format_args!("{}", self.tx_fifo_empty().bit()), + ) + .field( + "tx_eof_get_cnt", + &format_args!("{}", self.tx_eof_get_cnt().bits()), + ) + .field( + "tx_eof_overload", + &format_args!("{}", self.tx_eof_overload().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - write this bit to clear reg_bitscrambler_tx_eof_overload and reg_bitscrambler_tx_eof_get_cnt registers"] + #[inline(always)] + #[must_use] + pub fn tx_eof_trace_clr(&mut self) -> TX_EOF_TRACE_CLR_W { + TX_EOF_TRACE_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Status registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_state::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_state::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_STATE_SPEC; +impl crate::RegisterSpec for TX_STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_state::R`](R) reader structure"] +impl crate::Readable for TX_STATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_state::W`](W) writer structure"] +impl crate::Writable for TX_STATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_STATE to value 0x01"] +impl crate::Resettable for TX_STATE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/bitscrambler/tx_tailing_bits.rs b/esp32p4/src/bitscrambler/tx_tailing_bits.rs new file mode 100644 index 0000000000..c71d4d6dae --- /dev/null +++ b/esp32p4/src/bitscrambler/tx_tailing_bits.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TX_TAILING_BITS` reader"] +pub type R = crate::R; +#[doc = "Register `TX_TAILING_BITS` writer"] +pub type W = crate::W; +#[doc = "Field `TX_TAILING_BITS` reader - write this bits to specify the extra data bit length after getting EOF"] +pub type TX_TAILING_BITS_R = crate::FieldReader; +#[doc = "Field `TX_TAILING_BITS` writer - write this bits to specify the extra data bit length after getting EOF"] +pub type TX_TAILING_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - write this bits to specify the extra data bit length after getting EOF"] + #[inline(always)] + pub fn tx_tailing_bits(&self) -> TX_TAILING_BITS_R { + TX_TAILING_BITS_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_TAILING_BITS") + .field( + "tx_tailing_bits", + &format_args!("{}", self.tx_tailing_bits().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - write this bits to specify the extra data bit length after getting EOF"] + #[inline(always)] + #[must_use] + pub fn tx_tailing_bits(&mut self) -> TX_TAILING_BITS_W { + TX_TAILING_BITS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tailing_bits::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tailing_bits::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_TAILING_BITS_SPEC; +impl crate::RegisterSpec for TX_TAILING_BITS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_tailing_bits::R`](R) reader structure"] +impl crate::Readable for TX_TAILING_BITS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_tailing_bits::W`](W) writer structure"] +impl crate::Writable for TX_TAILING_BITS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_TAILING_BITS to value 0"] +impl crate::Resettable for TX_TAILING_BITS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/bitscrambler/version.rs b/esp32p4/src/bitscrambler/version.rs new file mode 100644 index 0000000000..db9fb02e45 --- /dev/null +++ b/esp32p4/src/bitscrambler/version.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VERSION` reader"] +pub type R = crate::R; +#[doc = "Register `VERSION` writer"] +pub type W = crate::W; +#[doc = "Field `BITSCRAMBLER_VER` reader - Reserved"] +pub type BITSCRAMBLER_VER_R = crate::FieldReader; +#[doc = "Field `BITSCRAMBLER_VER` writer - Reserved"] +pub type BITSCRAMBLER_VER_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Reserved"] + #[inline(always)] + pub fn bitscrambler_ver(&self) -> BITSCRAMBLER_VER_R { + BITSCRAMBLER_VER_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VERSION") + .field( + "bitscrambler_ver", + &format_args!("{}", self.bitscrambler_ver().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn bitscrambler_ver(&mut self) -> BITSCRAMBLER_VER_W { + BITSCRAMBLER_VER_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VERSION_SPEC; +impl crate::RegisterSpec for VERSION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`version::R`](R) reader structure"] +impl crate::Readable for VERSION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"] +impl crate::Writable for VERSION_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VERSION to value 0x0230_3240"] +impl crate::Resettable for VERSION_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_3240; +} diff --git a/esp32p4/src/cache.rs b/esp32p4/src/cache.rs new file mode 100644 index 0000000000..3d8199d1d4 --- /dev/null +++ b/esp32p4/src/cache.rs @@ -0,0 +1,2699 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + l1_icache_ctrl: L1_ICACHE_CTRL, + l1_dcache_ctrl: L1_DCACHE_CTRL, + l1_bypass_cache_conf: L1_BYPASS_CACHE_CONF, + l1_cache_atomic_conf: L1_CACHE_ATOMIC_CONF, + l1_icache_cachesize_conf: L1_ICACHE_CACHESIZE_CONF, + l1_icache_blocksize_conf: L1_ICACHE_BLOCKSIZE_CONF, + l1_dcache_cachesize_conf: L1_DCACHE_CACHESIZE_CONF, + l1_dcache_blocksize_conf: L1_DCACHE_BLOCKSIZE_CONF, + l1_cache_wrap_around_ctrl: L1_CACHE_WRAP_AROUND_CTRL, + l1_cache_tag_mem_power_ctrl: L1_CACHE_TAG_MEM_POWER_CTRL, + l1_cache_data_mem_power_ctrl: L1_CACHE_DATA_MEM_POWER_CTRL, + l1_cache_freeze_ctrl: L1_CACHE_FREEZE_CTRL, + l1_cache_data_mem_acs_conf: L1_CACHE_DATA_MEM_ACS_CONF, + l1_cache_tag_mem_acs_conf: L1_CACHE_TAG_MEM_ACS_CONF, + l1_icache0_prelock_conf: L1_ICACHE0_PRELOCK_CONF, + l1_icache0_prelock_sct0_addr: L1_ICACHE0_PRELOCK_SCT0_ADDR, + l1_icache0_prelock_sct1_addr: L1_ICACHE0_PRELOCK_SCT1_ADDR, + l1_icache0_prelock_sct_size: L1_ICACHE0_PRELOCK_SCT_SIZE, + l1_icache1_prelock_conf: L1_ICACHE1_PRELOCK_CONF, + l1_icache1_prelock_sct0_addr: L1_ICACHE1_PRELOCK_SCT0_ADDR, + l1_icache1_prelock_sct1_addr: L1_ICACHE1_PRELOCK_SCT1_ADDR, + l1_icache1_prelock_sct_size: L1_ICACHE1_PRELOCK_SCT_SIZE, + l1_icache2_prelock_conf: L1_ICACHE2_PRELOCK_CONF, + l1_icache2_prelock_sct0_addr: L1_ICACHE2_PRELOCK_SCT0_ADDR, + l1_icache2_prelock_sct1_addr: L1_ICACHE2_PRELOCK_SCT1_ADDR, + l1_icache2_prelock_sct_size: L1_ICACHE2_PRELOCK_SCT_SIZE, + l1_icache3_prelock_conf: L1_ICACHE3_PRELOCK_CONF, + l1_icache3_prelock_sct0_addr: L1_ICACHE3_PRELOCK_SCT0_ADDR, + l1_icache3_prelock_sct1_addr: L1_ICACHE3_PRELOCK_SCT1_ADDR, + l1_icache3_prelock_sct_size: L1_ICACHE3_PRELOCK_SCT_SIZE, + l1_dcache_prelock_conf: L1_DCACHE_PRELOCK_CONF, + l1_dcache_prelock_sct0_addr: L1_DCACHE_PRELOCK_SCT0_ADDR, + l1_dcache_prelock_sct1_addr: L1_DCACHE_PRELOCK_SCT1_ADDR, + l1_dcache_prelock_sct_size: L1_DCACHE_PRELOCK_SCT_SIZE, + lock_ctrl: LOCK_CTRL, + lock_map: LOCK_MAP, + lock_addr: LOCK_ADDR, + lock_size: LOCK_SIZE, + sync_ctrl: SYNC_CTRL, + sync_map: SYNC_MAP, + sync_addr: SYNC_ADDR, + sync_size: SYNC_SIZE, + l1_icache0_preload_ctrl: L1_ICACHE0_PRELOAD_CTRL, + l1_icache0_preload_addr: L1_ICACHE0_PRELOAD_ADDR, + l1_icache0_preload_size: L1_ICACHE0_PRELOAD_SIZE, + l1_icache1_preload_ctrl: L1_ICACHE1_PRELOAD_CTRL, + l1_icache1_preload_addr: L1_ICACHE1_PRELOAD_ADDR, + l1_icache1_preload_size: L1_ICACHE1_PRELOAD_SIZE, + l1_icache2_preload_ctrl: L1_ICACHE2_PRELOAD_CTRL, + l1_icache2_preload_addr: L1_ICACHE2_PRELOAD_ADDR, + l1_icache2_preload_size: L1_ICACHE2_PRELOAD_SIZE, + l1_icache3_preload_ctrl: L1_ICACHE3_PRELOAD_CTRL, + l1_icache3_preload_addr: L1_ICACHE3_PRELOAD_ADDR, + l1_icache3_preload_size: L1_ICACHE3_PRELOAD_SIZE, + l1_dcache_preload_ctrl: L1_DCACHE_PRELOAD_CTRL, + l1_dcache_preload_addr: L1_DCACHE_PRELOAD_ADDR, + l1_dcache_preload_size: L1_DCACHE_PRELOAD_SIZE, + l1_icache0_autoload_ctrl: L1_ICACHE0_AUTOLOAD_CTRL, + l1_icache0_autoload_sct0_addr: L1_ICACHE0_AUTOLOAD_SCT0_ADDR, + l1_icache0_autoload_sct0_size: L1_ICACHE0_AUTOLOAD_SCT0_SIZE, + l1_icache0_autoload_sct1_addr: L1_ICACHE0_AUTOLOAD_SCT1_ADDR, + l1_icache0_autoload_sct1_size: L1_ICACHE0_AUTOLOAD_SCT1_SIZE, + l1_icache1_autoload_ctrl: L1_ICACHE1_AUTOLOAD_CTRL, + l1_icache1_autoload_sct0_addr: L1_ICACHE1_AUTOLOAD_SCT0_ADDR, + l1_icache1_autoload_sct0_size: L1_ICACHE1_AUTOLOAD_SCT0_SIZE, + l1_icache1_autoload_sct1_addr: L1_ICACHE1_AUTOLOAD_SCT1_ADDR, + l1_icache1_autoload_sct1_size: L1_ICACHE1_AUTOLOAD_SCT1_SIZE, + l1_icache2_autoload_ctrl: L1_ICACHE2_AUTOLOAD_CTRL, + l1_icache2_autoload_sct0_addr: L1_ICACHE2_AUTOLOAD_SCT0_ADDR, + l1_icache2_autoload_sct0_size: L1_ICACHE2_AUTOLOAD_SCT0_SIZE, + l1_icache2_autoload_sct1_addr: L1_ICACHE2_AUTOLOAD_SCT1_ADDR, + l1_icache2_autoload_sct1_size: L1_ICACHE2_AUTOLOAD_SCT1_SIZE, + l1_icache3_autoload_ctrl: L1_ICACHE3_AUTOLOAD_CTRL, + l1_icache3_autoload_sct0_addr: L1_ICACHE3_AUTOLOAD_SCT0_ADDR, + l1_icache3_autoload_sct0_size: L1_ICACHE3_AUTOLOAD_SCT0_SIZE, + l1_icache3_autoload_sct1_addr: L1_ICACHE3_AUTOLOAD_SCT1_ADDR, + l1_icache3_autoload_sct1_size: L1_ICACHE3_AUTOLOAD_SCT1_SIZE, + l1_dcache_autoload_ctrl: L1_DCACHE_AUTOLOAD_CTRL, + l1_dcache_autoload_sct0_addr: L1_DCACHE_AUTOLOAD_SCT0_ADDR, + l1_dcache_autoload_sct0_size: L1_DCACHE_AUTOLOAD_SCT0_SIZE, + l1_dcache_autoload_sct1_addr: L1_DCACHE_AUTOLOAD_SCT1_ADDR, + l1_dcache_autoload_sct1_size: L1_DCACHE_AUTOLOAD_SCT1_SIZE, + l1_dcache_autoload_sct2_addr: L1_DCACHE_AUTOLOAD_SCT2_ADDR, + l1_dcache_autoload_sct2_size: L1_DCACHE_AUTOLOAD_SCT2_SIZE, + l1_dcache_autoload_sct3_addr: L1_DCACHE_AUTOLOAD_SCT3_ADDR, + l1_dcache_autoload_sct3_size: L1_DCACHE_AUTOLOAD_SCT3_SIZE, + l1_cache_acs_cnt_int_ena: L1_CACHE_ACS_CNT_INT_ENA, + l1_cache_acs_cnt_int_clr: L1_CACHE_ACS_CNT_INT_CLR, + l1_cache_acs_cnt_int_raw: L1_CACHE_ACS_CNT_INT_RAW, + l1_cache_acs_cnt_int_st: L1_CACHE_ACS_CNT_INT_ST, + l1_cache_acs_fail_ctrl: L1_CACHE_ACS_FAIL_CTRL, + l1_cache_acs_fail_int_ena: L1_CACHE_ACS_FAIL_INT_ENA, + l1_cache_acs_fail_int_clr: L1_CACHE_ACS_FAIL_INT_CLR, + l1_cache_acs_fail_int_raw: L1_CACHE_ACS_FAIL_INT_RAW, + l1_cache_acs_fail_int_st: L1_CACHE_ACS_FAIL_INT_ST, + l1_cache_acs_cnt_ctrl: L1_CACHE_ACS_CNT_CTRL, + l1_ibus0_acs_hit_cnt: L1_IBUS0_ACS_HIT_CNT, + l1_ibus0_acs_miss_cnt: L1_IBUS0_ACS_MISS_CNT, + l1_ibus0_acs_conflict_cnt: L1_IBUS0_ACS_CONFLICT_CNT, + l1_ibus0_acs_nxtlvl_rd_cnt: L1_IBUS0_ACS_NXTLVL_RD_CNT, + l1_ibus1_acs_hit_cnt: L1_IBUS1_ACS_HIT_CNT, + l1_ibus1_acs_miss_cnt: L1_IBUS1_ACS_MISS_CNT, + l1_ibus1_acs_conflict_cnt: L1_IBUS1_ACS_CONFLICT_CNT, + l1_ibus1_acs_nxtlvl_rd_cnt: L1_IBUS1_ACS_NXTLVL_RD_CNT, + l1_ibus2_acs_hit_cnt: L1_IBUS2_ACS_HIT_CNT, + l1_ibus2_acs_miss_cnt: L1_IBUS2_ACS_MISS_CNT, + l1_ibus2_acs_conflict_cnt: L1_IBUS2_ACS_CONFLICT_CNT, + l1_ibus2_acs_nxtlvl_rd_cnt: L1_IBUS2_ACS_NXTLVL_RD_CNT, + l1_ibus3_acs_hit_cnt: L1_IBUS3_ACS_HIT_CNT, + l1_ibus3_acs_miss_cnt: L1_IBUS3_ACS_MISS_CNT, + l1_ibus3_acs_conflict_cnt: L1_IBUS3_ACS_CONFLICT_CNT, + l1_ibus3_acs_nxtlvl_rd_cnt: L1_IBUS3_ACS_NXTLVL_RD_CNT, + l1_dbus0_acs_hit_cnt: L1_DBUS0_ACS_HIT_CNT, + l1_dbus0_acs_miss_cnt: L1_DBUS0_ACS_MISS_CNT, + l1_dbus0_acs_conflict_cnt: L1_DBUS0_ACS_CONFLICT_CNT, + l1_dbus0_acs_nxtlvl_rd_cnt: L1_DBUS0_ACS_NXTLVL_RD_CNT, + l1_dbus0_acs_nxtlvl_wr_cnt: L1_DBUS0_ACS_NXTLVL_WR_CNT, + l1_dbus1_acs_hit_cnt: L1_DBUS1_ACS_HIT_CNT, + l1_dbus1_acs_miss_cnt: L1_DBUS1_ACS_MISS_CNT, + l1_dbus1_acs_conflict_cnt: L1_DBUS1_ACS_CONFLICT_CNT, + l1_dbus1_acs_nxtlvl_rd_cnt: L1_DBUS1_ACS_NXTLVL_RD_CNT, + l1_dbus1_acs_nxtlvl_wr_cnt: L1_DBUS1_ACS_NXTLVL_WR_CNT, + l1_dbus2_acs_hit_cnt: L1_DBUS2_ACS_HIT_CNT, + l1_dbus2_acs_miss_cnt: L1_DBUS2_ACS_MISS_CNT, + l1_dbus2_acs_conflict_cnt: L1_DBUS2_ACS_CONFLICT_CNT, + l1_dbus2_acs_nxtlvl_rd_cnt: L1_DBUS2_ACS_NXTLVL_RD_CNT, + l1_dbus2_acs_nxtlvl_wr_cnt: L1_DBUS2_ACS_NXTLVL_WR_CNT, + l1_dbus3_acs_hit_cnt: L1_DBUS3_ACS_HIT_CNT, + l1_dbus3_acs_miss_cnt: L1_DBUS3_ACS_MISS_CNT, + l1_dbus3_acs_conflict_cnt: L1_DBUS3_ACS_CONFLICT_CNT, + l1_dbus3_acs_nxtlvl_rd_cnt: L1_DBUS3_ACS_NXTLVL_RD_CNT, + l1_dbus3_acs_nxtlvl_wr_cnt: L1_DBUS3_ACS_NXTLVL_WR_CNT, + l1_icache0_acs_fail_id_attr: L1_ICACHE0_ACS_FAIL_ID_ATTR, + l1_icache0_acs_fail_addr: L1_ICACHE0_ACS_FAIL_ADDR, + l1_icache1_acs_fail_id_attr: L1_ICACHE1_ACS_FAIL_ID_ATTR, + l1_icache1_acs_fail_addr: L1_ICACHE1_ACS_FAIL_ADDR, + l1_icache2_acs_fail_id_attr: L1_ICACHE2_ACS_FAIL_ID_ATTR, + l1_icache2_acs_fail_addr: L1_ICACHE2_ACS_FAIL_ADDR, + l1_icache3_acs_fail_id_attr: L1_ICACHE3_ACS_FAIL_ID_ATTR, + l1_icache3_acs_fail_addr: L1_ICACHE3_ACS_FAIL_ADDR, + l1_dcache_acs_fail_id_attr: L1_DCACHE_ACS_FAIL_ID_ATTR, + l1_dcache_acs_fail_addr: L1_DCACHE_ACS_FAIL_ADDR, + sync_l1_cache_preload_int_ena: SYNC_L1_CACHE_PRELOAD_INT_ENA, + sync_l1_cache_preload_int_clr: SYNC_L1_CACHE_PRELOAD_INT_CLR, + sync_l1_cache_preload_int_raw: SYNC_L1_CACHE_PRELOAD_INT_RAW, + sync_l1_cache_preload_int_st: SYNC_L1_CACHE_PRELOAD_INT_ST, + sync_l1_cache_preload_exception: SYNC_L1_CACHE_PRELOAD_EXCEPTION, + l1_cache_sync_rst_ctrl: L1_CACHE_SYNC_RST_CTRL, + l1_cache_preload_rst_ctrl: L1_CACHE_PRELOAD_RST_CTRL, + l1_cache_autoload_buf_clr_ctrl: L1_CACHE_AUTOLOAD_BUF_CLR_CTRL, + l1_unallocate_buffer_clear: L1_UNALLOCATE_BUFFER_CLEAR, + l1_cache_object_ctrl: L1_CACHE_OBJECT_CTRL, + l1_cache_way_object: L1_CACHE_WAY_OBJECT, + l1_cache_vaddr: L1_CACHE_VADDR, + l1_cache_debug_bus: L1_CACHE_DEBUG_BUS, + level_split0: LEVEL_SPLIT0, + l2_cache_ctrl: L2_CACHE_CTRL, + l2_bypass_cache_conf: L2_BYPASS_CACHE_CONF, + l2_cache_cachesize_conf: L2_CACHE_CACHESIZE_CONF, + l2_cache_blocksize_conf: L2_CACHE_BLOCKSIZE_CONF, + l2_cache_wrap_around_ctrl: L2_CACHE_WRAP_AROUND_CTRL, + l2_cache_tag_mem_power_ctrl: L2_CACHE_TAG_MEM_POWER_CTRL, + l2_cache_data_mem_power_ctrl: L2_CACHE_DATA_MEM_POWER_CTRL, + l2_cache_freeze_ctrl: L2_CACHE_FREEZE_CTRL, + l2_cache_data_mem_acs_conf: L2_CACHE_DATA_MEM_ACS_CONF, + l2_cache_tag_mem_acs_conf: L2_CACHE_TAG_MEM_ACS_CONF, + l2_cache_prelock_conf: L2_CACHE_PRELOCK_CONF, + l2_cache_prelock_sct0_addr: L2_CACHE_PRELOCK_SCT0_ADDR, + l2_cache_prelock_sct1_addr: L2_CACHE_PRELOCK_SCT1_ADDR, + l2_cache_prelock_sct_size: L2_CACHE_PRELOCK_SCT_SIZE, + l2_cache_preload_ctrl: L2_CACHE_PRELOAD_CTRL, + l2_cache_preload_addr: L2_CACHE_PRELOAD_ADDR, + l2_cache_preload_size: L2_CACHE_PRELOAD_SIZE, + l2_cache_autoload_ctrl: L2_CACHE_AUTOLOAD_CTRL, + l2_cache_autoload_sct0_addr: L2_CACHE_AUTOLOAD_SCT0_ADDR, + l2_cache_autoload_sct0_size: L2_CACHE_AUTOLOAD_SCT0_SIZE, + l2_cache_autoload_sct1_addr: L2_CACHE_AUTOLOAD_SCT1_ADDR, + l2_cache_autoload_sct1_size: L2_CACHE_AUTOLOAD_SCT1_SIZE, + l2_cache_autoload_sct2_addr: L2_CACHE_AUTOLOAD_SCT2_ADDR, + l2_cache_autoload_sct2_size: L2_CACHE_AUTOLOAD_SCT2_SIZE, + l2_cache_autoload_sct3_addr: L2_CACHE_AUTOLOAD_SCT3_ADDR, + l2_cache_autoload_sct3_size: L2_CACHE_AUTOLOAD_SCT3_SIZE, + l2_cache_acs_cnt_int_ena: L2_CACHE_ACS_CNT_INT_ENA, + l2_cache_acs_cnt_int_clr: L2_CACHE_ACS_CNT_INT_CLR, + l2_cache_acs_cnt_int_raw: L2_CACHE_ACS_CNT_INT_RAW, + l2_cache_acs_cnt_int_st: L2_CACHE_ACS_CNT_INT_ST, + l2_cache_acs_fail_ctrl: L2_CACHE_ACS_FAIL_CTRL, + l2_cache_acs_fail_int_ena: L2_CACHE_ACS_FAIL_INT_ENA, + l2_cache_acs_fail_int_clr: L2_CACHE_ACS_FAIL_INT_CLR, + l2_cache_acs_fail_int_raw: L2_CACHE_ACS_FAIL_INT_RAW, + l2_cache_acs_fail_int_st: L2_CACHE_ACS_FAIL_INT_ST, + l2_cache_acs_cnt_ctrl: L2_CACHE_ACS_CNT_CTRL, + l2_ibus0_acs_hit_cnt: L2_IBUS0_ACS_HIT_CNT, + l2_ibus0_acs_miss_cnt: L2_IBUS0_ACS_MISS_CNT, + l2_ibus0_acs_conflict_cnt: L2_IBUS0_ACS_CONFLICT_CNT, + l2_ibus0_acs_nxtlvl_rd_cnt: L2_IBUS0_ACS_NXTLVL_RD_CNT, + l2_ibus1_acs_hit_cnt: L2_IBUS1_ACS_HIT_CNT, + l2_ibus1_acs_miss_cnt: L2_IBUS1_ACS_MISS_CNT, + l2_ibus1_acs_conflict_cnt: L2_IBUS1_ACS_CONFLICT_CNT, + l2_ibus1_acs_nxtlvl_rd_cnt: L2_IBUS1_ACS_NXTLVL_RD_CNT, + l2_ibus2_acs_hit_cnt: L2_IBUS2_ACS_HIT_CNT, + l2_ibus2_acs_miss_cnt: L2_IBUS2_ACS_MISS_CNT, + l2_ibus2_acs_conflict_cnt: L2_IBUS2_ACS_CONFLICT_CNT, + l2_ibus2_acs_nxtlvl_rd_cnt: L2_IBUS2_ACS_NXTLVL_RD_CNT, + l2_ibus3_acs_hit_cnt: L2_IBUS3_ACS_HIT_CNT, + l2_ibus3_acs_miss_cnt: L2_IBUS3_ACS_MISS_CNT, + l2_ibus3_acs_conflict_cnt: L2_IBUS3_ACS_CONFLICT_CNT, + l2_ibus3_acs_nxtlvl_rd_cnt: L2_IBUS3_ACS_NXTLVL_RD_CNT, + l2_dbus0_acs_hit_cnt: L2_DBUS0_ACS_HIT_CNT, + l2_dbus0_acs_miss_cnt: L2_DBUS0_ACS_MISS_CNT, + l2_dbus0_acs_conflict_cnt: L2_DBUS0_ACS_CONFLICT_CNT, + l2_dbus0_acs_nxtlvl_rd_cnt: L2_DBUS0_ACS_NXTLVL_RD_CNT, + l2_dbus0_acs_nxtlvl_wr_cnt: L2_DBUS0_ACS_NXTLVL_WR_CNT, + l2_dbus1_acs_hit_cnt: L2_DBUS1_ACS_HIT_CNT, + l2_dbus1_acs_miss_cnt: L2_DBUS1_ACS_MISS_CNT, + l2_dbus1_acs_conflict_cnt: L2_DBUS1_ACS_CONFLICT_CNT, + l2_dbus1_acs_nxtlvl_rd_cnt: L2_DBUS1_ACS_NXTLVL_RD_CNT, + l2_dbus1_acs_nxtlvl_wr_cnt: L2_DBUS1_ACS_NXTLVL_WR_CNT, + l2_dbus2_acs_hit_cnt: L2_DBUS2_ACS_HIT_CNT, + l2_dbus2_acs_miss_cnt: L2_DBUS2_ACS_MISS_CNT, + l2_dbus2_acs_conflict_cnt: L2_DBUS2_ACS_CONFLICT_CNT, + l2_dbus2_acs_nxtlvl_rd_cnt: L2_DBUS2_ACS_NXTLVL_RD_CNT, + l2_dbus2_acs_nxtlvl_wr_cnt: L2_DBUS2_ACS_NXTLVL_WR_CNT, + l2_dbus3_acs_hit_cnt: L2_DBUS3_ACS_HIT_CNT, + l2_dbus3_acs_miss_cnt: L2_DBUS3_ACS_MISS_CNT, + l2_dbus3_acs_conflict_cnt: L2_DBUS3_ACS_CONFLICT_CNT, + l2_dbus3_acs_nxtlvl_rd_cnt: L2_DBUS3_ACS_NXTLVL_RD_CNT, + l2_dbus3_acs_nxtlvl_wr_cnt: L2_DBUS3_ACS_NXTLVL_WR_CNT, + l2_cache_acs_fail_id_attr: L2_CACHE_ACS_FAIL_ID_ATTR, + l2_cache_acs_fail_addr: L2_CACHE_ACS_FAIL_ADDR, + l2_cache_sync_preload_int_ena: L2_CACHE_SYNC_PRELOAD_INT_ENA, + l2_cache_sync_preload_int_clr: L2_CACHE_SYNC_PRELOAD_INT_CLR, + l2_cache_sync_preload_int_raw: L2_CACHE_SYNC_PRELOAD_INT_RAW, + l2_cache_sync_preload_int_st: L2_CACHE_SYNC_PRELOAD_INT_ST, + l2_cache_sync_preload_exception: L2_CACHE_SYNC_PRELOAD_EXCEPTION, + l2_cache_sync_rst_ctrl: L2_CACHE_SYNC_RST_CTRL, + l2_cache_preload_rst_ctrl: L2_CACHE_PRELOAD_RST_CTRL, + l2_cache_autoload_buf_clr_ctrl: L2_CACHE_AUTOLOAD_BUF_CLR_CTRL, + l2_unallocate_buffer_clear: L2_UNALLOCATE_BUFFER_CLEAR, + l2_cache_access_attr_ctrl: L2_CACHE_ACCESS_ATTR_CTRL, + l2_cache_object_ctrl: L2_CACHE_OBJECT_CTRL, + l2_cache_way_object: L2_CACHE_WAY_OBJECT, + l2_cache_vaddr: L2_CACHE_VADDR, + l2_cache_debug_bus: L2_CACHE_DEBUG_BUS, + level_split1: LEVEL_SPLIT1, + clock_gate: CLOCK_GATE, + redundancy_sig0: REDUNDANCY_SIG0, + redundancy_sig1: REDUNDANCY_SIG1, + redundancy_sig2: REDUNDANCY_SIG2, + redundancy_sig3: REDUNDANCY_SIG3, + redundancy_sig4: REDUNDANCY_SIG4, + _reserved251: [u8; 0x10], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - L1 instruction Cache(L1-ICache) control register"] + #[inline(always)] + pub const fn l1_icache_ctrl(&self) -> &L1_ICACHE_CTRL { + &self.l1_icache_ctrl + } + #[doc = "0x04 - L1 data Cache(L1-DCache) control register"] + #[inline(always)] + pub const fn l1_dcache_ctrl(&self) -> &L1_DCACHE_CTRL { + &self.l1_dcache_ctrl + } + #[doc = "0x08 - Bypass Cache configure register"] + #[inline(always)] + pub const fn l1_bypass_cache_conf(&self) -> &L1_BYPASS_CACHE_CONF { + &self.l1_bypass_cache_conf + } + #[doc = "0x0c - L1 Cache atomic feature configure register"] + #[inline(always)] + pub const fn l1_cache_atomic_conf(&self) -> &L1_CACHE_ATOMIC_CONF { + &self.l1_cache_atomic_conf + } + #[doc = "0x10 - L1 instruction Cache CacheSize mode configure register"] + #[inline(always)] + pub const fn l1_icache_cachesize_conf(&self) -> &L1_ICACHE_CACHESIZE_CONF { + &self.l1_icache_cachesize_conf + } + #[doc = "0x14 - L1 instruction Cache BlockSize mode configure register"] + #[inline(always)] + pub const fn l1_icache_blocksize_conf(&self) -> &L1_ICACHE_BLOCKSIZE_CONF { + &self.l1_icache_blocksize_conf + } + #[doc = "0x18 - L1 data Cache CacheSize mode configure register"] + #[inline(always)] + pub const fn l1_dcache_cachesize_conf(&self) -> &L1_DCACHE_CACHESIZE_CONF { + &self.l1_dcache_cachesize_conf + } + #[doc = "0x1c - L1 data Cache BlockSize mode configure register"] + #[inline(always)] + pub const fn l1_dcache_blocksize_conf(&self) -> &L1_DCACHE_BLOCKSIZE_CONF { + &self.l1_dcache_blocksize_conf + } + #[doc = "0x20 - Cache wrap around control register"] + #[inline(always)] + pub const fn l1_cache_wrap_around_ctrl(&self) -> &L1_CACHE_WRAP_AROUND_CTRL { + &self.l1_cache_wrap_around_ctrl + } + #[doc = "0x24 - Cache tag memory power control register"] + #[inline(always)] + pub const fn l1_cache_tag_mem_power_ctrl(&self) -> &L1_CACHE_TAG_MEM_POWER_CTRL { + &self.l1_cache_tag_mem_power_ctrl + } + #[doc = "0x28 - Cache data memory power control register"] + #[inline(always)] + pub const fn l1_cache_data_mem_power_ctrl(&self) -> &L1_CACHE_DATA_MEM_POWER_CTRL { + &self.l1_cache_data_mem_power_ctrl + } + #[doc = "0x2c - Cache Freeze control register"] + #[inline(always)] + pub const fn l1_cache_freeze_ctrl(&self) -> &L1_CACHE_FREEZE_CTRL { + &self.l1_cache_freeze_ctrl + } + #[doc = "0x30 - Cache data memory access configure register"] + #[inline(always)] + pub const fn l1_cache_data_mem_acs_conf(&self) -> &L1_CACHE_DATA_MEM_ACS_CONF { + &self.l1_cache_data_mem_acs_conf + } + #[doc = "0x34 - Cache tag memory access configure register"] + #[inline(always)] + pub const fn l1_cache_tag_mem_acs_conf(&self) -> &L1_CACHE_TAG_MEM_ACS_CONF { + &self.l1_cache_tag_mem_acs_conf + } + #[doc = "0x38 - L1 instruction Cache 0 prelock configure register"] + #[inline(always)] + pub const fn l1_icache0_prelock_conf(&self) -> &L1_ICACHE0_PRELOCK_CONF { + &self.l1_icache0_prelock_conf + } + #[doc = "0x3c - L1 instruction Cache 0 prelock section0 address configure register"] + #[inline(always)] + pub const fn l1_icache0_prelock_sct0_addr(&self) -> &L1_ICACHE0_PRELOCK_SCT0_ADDR { + &self.l1_icache0_prelock_sct0_addr + } + #[doc = "0x40 - L1 instruction Cache 0 prelock section1 address configure register"] + #[inline(always)] + pub const fn l1_icache0_prelock_sct1_addr(&self) -> &L1_ICACHE0_PRELOCK_SCT1_ADDR { + &self.l1_icache0_prelock_sct1_addr + } + #[doc = "0x44 - L1 instruction Cache 0 prelock section size configure register"] + #[inline(always)] + pub const fn l1_icache0_prelock_sct_size(&self) -> &L1_ICACHE0_PRELOCK_SCT_SIZE { + &self.l1_icache0_prelock_sct_size + } + #[doc = "0x48 - L1 instruction Cache 1 prelock configure register"] + #[inline(always)] + pub const fn l1_icache1_prelock_conf(&self) -> &L1_ICACHE1_PRELOCK_CONF { + &self.l1_icache1_prelock_conf + } + #[doc = "0x4c - L1 instruction Cache 1 prelock section0 address configure register"] + #[inline(always)] + pub const fn l1_icache1_prelock_sct0_addr(&self) -> &L1_ICACHE1_PRELOCK_SCT0_ADDR { + &self.l1_icache1_prelock_sct0_addr + } + #[doc = "0x50 - L1 instruction Cache 1 prelock section1 address configure register"] + #[inline(always)] + pub const fn l1_icache1_prelock_sct1_addr(&self) -> &L1_ICACHE1_PRELOCK_SCT1_ADDR { + &self.l1_icache1_prelock_sct1_addr + } + #[doc = "0x54 - L1 instruction Cache 1 prelock section size configure register"] + #[inline(always)] + pub const fn l1_icache1_prelock_sct_size(&self) -> &L1_ICACHE1_PRELOCK_SCT_SIZE { + &self.l1_icache1_prelock_sct_size + } + #[doc = "0x58 - L1 instruction Cache 2 prelock configure register"] + #[inline(always)] + pub const fn l1_icache2_prelock_conf(&self) -> &L1_ICACHE2_PRELOCK_CONF { + &self.l1_icache2_prelock_conf + } + #[doc = "0x5c - L1 instruction Cache 2 prelock section0 address configure register"] + #[inline(always)] + pub const fn l1_icache2_prelock_sct0_addr(&self) -> &L1_ICACHE2_PRELOCK_SCT0_ADDR { + &self.l1_icache2_prelock_sct0_addr + } + #[doc = "0x60 - L1 instruction Cache 2 prelock section1 address configure register"] + #[inline(always)] + pub const fn l1_icache2_prelock_sct1_addr(&self) -> &L1_ICACHE2_PRELOCK_SCT1_ADDR { + &self.l1_icache2_prelock_sct1_addr + } + #[doc = "0x64 - L1 instruction Cache 2 prelock section size configure register"] + #[inline(always)] + pub const fn l1_icache2_prelock_sct_size(&self) -> &L1_ICACHE2_PRELOCK_SCT_SIZE { + &self.l1_icache2_prelock_sct_size + } + #[doc = "0x68 - L1 instruction Cache 3 prelock configure register"] + #[inline(always)] + pub const fn l1_icache3_prelock_conf(&self) -> &L1_ICACHE3_PRELOCK_CONF { + &self.l1_icache3_prelock_conf + } + #[doc = "0x6c - L1 instruction Cache 3 prelock section0 address configure register"] + #[inline(always)] + pub const fn l1_icache3_prelock_sct0_addr(&self) -> &L1_ICACHE3_PRELOCK_SCT0_ADDR { + &self.l1_icache3_prelock_sct0_addr + } + #[doc = "0x70 - L1 instruction Cache 3 prelock section1 address configure register"] + #[inline(always)] + pub const fn l1_icache3_prelock_sct1_addr(&self) -> &L1_ICACHE3_PRELOCK_SCT1_ADDR { + &self.l1_icache3_prelock_sct1_addr + } + #[doc = "0x74 - L1 instruction Cache 3 prelock section size configure register"] + #[inline(always)] + pub const fn l1_icache3_prelock_sct_size(&self) -> &L1_ICACHE3_PRELOCK_SCT_SIZE { + &self.l1_icache3_prelock_sct_size + } + #[doc = "0x78 - L1 data Cache prelock configure register"] + #[inline(always)] + pub const fn l1_dcache_prelock_conf(&self) -> &L1_DCACHE_PRELOCK_CONF { + &self.l1_dcache_prelock_conf + } + #[doc = "0x7c - L1 data Cache prelock section0 address configure register"] + #[inline(always)] + pub const fn l1_dcache_prelock_sct0_addr(&self) -> &L1_DCACHE_PRELOCK_SCT0_ADDR { + &self.l1_dcache_prelock_sct0_addr + } + #[doc = "0x80 - L1 data Cache prelock section1 address configure register"] + #[inline(always)] + pub const fn l1_dcache_prelock_sct1_addr(&self) -> &L1_DCACHE_PRELOCK_SCT1_ADDR { + &self.l1_dcache_prelock_sct1_addr + } + #[doc = "0x84 - L1 data Cache prelock section size configure register"] + #[inline(always)] + pub const fn l1_dcache_prelock_sct_size(&self) -> &L1_DCACHE_PRELOCK_SCT_SIZE { + &self.l1_dcache_prelock_sct_size + } + #[doc = "0x88 - Lock-class (manual lock) operation control register"] + #[inline(always)] + pub const fn lock_ctrl(&self) -> &LOCK_CTRL { + &self.lock_ctrl + } + #[doc = "0x8c - Lock (manual lock) map configure register"] + #[inline(always)] + pub const fn lock_map(&self) -> &LOCK_MAP { + &self.lock_map + } + #[doc = "0x90 - Lock (manual lock) address configure register"] + #[inline(always)] + pub const fn lock_addr(&self) -> &LOCK_ADDR { + &self.lock_addr + } + #[doc = "0x94 - Lock (manual lock) size configure register"] + #[inline(always)] + pub const fn lock_size(&self) -> &LOCK_SIZE { + &self.lock_size + } + #[doc = "0x98 - Sync-class operation control register"] + #[inline(always)] + pub const fn sync_ctrl(&self) -> &SYNC_CTRL { + &self.sync_ctrl + } + #[doc = "0x9c - Sync map configure register"] + #[inline(always)] + pub const fn sync_map(&self) -> &SYNC_MAP { + &self.sync_map + } + #[doc = "0xa0 - Sync address configure register"] + #[inline(always)] + pub const fn sync_addr(&self) -> &SYNC_ADDR { + &self.sync_addr + } + #[doc = "0xa4 - Sync size configure register"] + #[inline(always)] + pub const fn sync_size(&self) -> &SYNC_SIZE { + &self.sync_size + } + #[doc = "0xa8 - L1 instruction Cache 0 preload-operation control register"] + #[inline(always)] + pub const fn l1_icache0_preload_ctrl(&self) -> &L1_ICACHE0_PRELOAD_CTRL { + &self.l1_icache0_preload_ctrl + } + #[doc = "0xac - L1 instruction Cache 0 preload address configure register"] + #[inline(always)] + pub const fn l1_icache0_preload_addr(&self) -> &L1_ICACHE0_PRELOAD_ADDR { + &self.l1_icache0_preload_addr + } + #[doc = "0xb0 - L1 instruction Cache 0 preload size configure register"] + #[inline(always)] + pub const fn l1_icache0_preload_size(&self) -> &L1_ICACHE0_PRELOAD_SIZE { + &self.l1_icache0_preload_size + } + #[doc = "0xb4 - L1 instruction Cache 1 preload-operation control register"] + #[inline(always)] + pub const fn l1_icache1_preload_ctrl(&self) -> &L1_ICACHE1_PRELOAD_CTRL { + &self.l1_icache1_preload_ctrl + } + #[doc = "0xb8 - L1 instruction Cache 1 preload address configure register"] + #[inline(always)] + pub const fn l1_icache1_preload_addr(&self) -> &L1_ICACHE1_PRELOAD_ADDR { + &self.l1_icache1_preload_addr + } + #[doc = "0xbc - L1 instruction Cache 1 preload size configure register"] + #[inline(always)] + pub const fn l1_icache1_preload_size(&self) -> &L1_ICACHE1_PRELOAD_SIZE { + &self.l1_icache1_preload_size + } + #[doc = "0xc0 - L1 instruction Cache 2 preload-operation control register"] + #[inline(always)] + pub const fn l1_icache2_preload_ctrl(&self) -> &L1_ICACHE2_PRELOAD_CTRL { + &self.l1_icache2_preload_ctrl + } + #[doc = "0xc4 - L1 instruction Cache 2 preload address configure register"] + #[inline(always)] + pub const fn l1_icache2_preload_addr(&self) -> &L1_ICACHE2_PRELOAD_ADDR { + &self.l1_icache2_preload_addr + } + #[doc = "0xc8 - L1 instruction Cache 2 preload size configure register"] + #[inline(always)] + pub const fn l1_icache2_preload_size(&self) -> &L1_ICACHE2_PRELOAD_SIZE { + &self.l1_icache2_preload_size + } + #[doc = "0xcc - L1 instruction Cache 3 preload-operation control register"] + #[inline(always)] + pub const fn l1_icache3_preload_ctrl(&self) -> &L1_ICACHE3_PRELOAD_CTRL { + &self.l1_icache3_preload_ctrl + } + #[doc = "0xd0 - L1 instruction Cache 3 preload address configure register"] + #[inline(always)] + pub const fn l1_icache3_preload_addr(&self) -> &L1_ICACHE3_PRELOAD_ADDR { + &self.l1_icache3_preload_addr + } + #[doc = "0xd4 - L1 instruction Cache 3 preload size configure register"] + #[inline(always)] + pub const fn l1_icache3_preload_size(&self) -> &L1_ICACHE3_PRELOAD_SIZE { + &self.l1_icache3_preload_size + } + #[doc = "0xd8 - L1 data Cache preload-operation control register"] + #[inline(always)] + pub const fn l1_dcache_preload_ctrl(&self) -> &L1_DCACHE_PRELOAD_CTRL { + &self.l1_dcache_preload_ctrl + } + #[doc = "0xdc - L1 data Cache preload address configure register"] + #[inline(always)] + pub const fn l1_dcache_preload_addr(&self) -> &L1_DCACHE_PRELOAD_ADDR { + &self.l1_dcache_preload_addr + } + #[doc = "0xe0 - L1 data Cache preload size configure register"] + #[inline(always)] + pub const fn l1_dcache_preload_size(&self) -> &L1_DCACHE_PRELOAD_SIZE { + &self.l1_dcache_preload_size + } + #[doc = "0xe4 - L1 instruction Cache 0 autoload-operation control register"] + #[inline(always)] + pub const fn l1_icache0_autoload_ctrl(&self) -> &L1_ICACHE0_AUTOLOAD_CTRL { + &self.l1_icache0_autoload_ctrl + } + #[doc = "0xe8 - L1 instruction Cache 0 autoload section 0 address configure register"] + #[inline(always)] + pub const fn l1_icache0_autoload_sct0_addr(&self) -> &L1_ICACHE0_AUTOLOAD_SCT0_ADDR { + &self.l1_icache0_autoload_sct0_addr + } + #[doc = "0xec - L1 instruction Cache 0 autoload section 0 size configure register"] + #[inline(always)] + pub const fn l1_icache0_autoload_sct0_size(&self) -> &L1_ICACHE0_AUTOLOAD_SCT0_SIZE { + &self.l1_icache0_autoload_sct0_size + } + #[doc = "0xf0 - L1 instruction Cache 0 autoload section 1 address configure register"] + #[inline(always)] + pub const fn l1_icache0_autoload_sct1_addr(&self) -> &L1_ICACHE0_AUTOLOAD_SCT1_ADDR { + &self.l1_icache0_autoload_sct1_addr + } + #[doc = "0xf4 - L1 instruction Cache 0 autoload section 1 size configure register"] + #[inline(always)] + pub const fn l1_icache0_autoload_sct1_size(&self) -> &L1_ICACHE0_AUTOLOAD_SCT1_SIZE { + &self.l1_icache0_autoload_sct1_size + } + #[doc = "0xf8 - L1 instruction Cache 1 autoload-operation control register"] + #[inline(always)] + pub const fn l1_icache1_autoload_ctrl(&self) -> &L1_ICACHE1_AUTOLOAD_CTRL { + &self.l1_icache1_autoload_ctrl + } + #[doc = "0xfc - L1 instruction Cache 1 autoload section 0 address configure register"] + #[inline(always)] + pub const fn l1_icache1_autoload_sct0_addr(&self) -> &L1_ICACHE1_AUTOLOAD_SCT0_ADDR { + &self.l1_icache1_autoload_sct0_addr + } + #[doc = "0x100 - L1 instruction Cache 1 autoload section 0 size configure register"] + #[inline(always)] + pub const fn l1_icache1_autoload_sct0_size(&self) -> &L1_ICACHE1_AUTOLOAD_SCT0_SIZE { + &self.l1_icache1_autoload_sct0_size + } + #[doc = "0x104 - L1 instruction Cache 1 autoload section 1 address configure register"] + #[inline(always)] + pub const fn l1_icache1_autoload_sct1_addr(&self) -> &L1_ICACHE1_AUTOLOAD_SCT1_ADDR { + &self.l1_icache1_autoload_sct1_addr + } + #[doc = "0x108 - L1 instruction Cache 1 autoload section 1 size configure register"] + #[inline(always)] + pub const fn l1_icache1_autoload_sct1_size(&self) -> &L1_ICACHE1_AUTOLOAD_SCT1_SIZE { + &self.l1_icache1_autoload_sct1_size + } + #[doc = "0x10c - L1 instruction Cache 2 autoload-operation control register"] + #[inline(always)] + pub const fn l1_icache2_autoload_ctrl(&self) -> &L1_ICACHE2_AUTOLOAD_CTRL { + &self.l1_icache2_autoload_ctrl + } + #[doc = "0x110 - L1 instruction Cache 2 autoload section 0 address configure register"] + #[inline(always)] + pub const fn l1_icache2_autoload_sct0_addr(&self) -> &L1_ICACHE2_AUTOLOAD_SCT0_ADDR { + &self.l1_icache2_autoload_sct0_addr + } + #[doc = "0x114 - L1 instruction Cache 2 autoload section 0 size configure register"] + #[inline(always)] + pub const fn l1_icache2_autoload_sct0_size(&self) -> &L1_ICACHE2_AUTOLOAD_SCT0_SIZE { + &self.l1_icache2_autoload_sct0_size + } + #[doc = "0x118 - L1 instruction Cache 2 autoload section 1 address configure register"] + #[inline(always)] + pub const fn l1_icache2_autoload_sct1_addr(&self) -> &L1_ICACHE2_AUTOLOAD_SCT1_ADDR { + &self.l1_icache2_autoload_sct1_addr + } + #[doc = "0x11c - L1 instruction Cache 2 autoload section 1 size configure register"] + #[inline(always)] + pub const fn l1_icache2_autoload_sct1_size(&self) -> &L1_ICACHE2_AUTOLOAD_SCT1_SIZE { + &self.l1_icache2_autoload_sct1_size + } + #[doc = "0x120 - L1 instruction Cache 3 autoload-operation control register"] + #[inline(always)] + pub const fn l1_icache3_autoload_ctrl(&self) -> &L1_ICACHE3_AUTOLOAD_CTRL { + &self.l1_icache3_autoload_ctrl + } + #[doc = "0x124 - L1 instruction Cache 3 autoload section 0 address configure register"] + #[inline(always)] + pub const fn l1_icache3_autoload_sct0_addr(&self) -> &L1_ICACHE3_AUTOLOAD_SCT0_ADDR { + &self.l1_icache3_autoload_sct0_addr + } + #[doc = "0x128 - L1 instruction Cache 3 autoload section 0 size configure register"] + #[inline(always)] + pub const fn l1_icache3_autoload_sct0_size(&self) -> &L1_ICACHE3_AUTOLOAD_SCT0_SIZE { + &self.l1_icache3_autoload_sct0_size + } + #[doc = "0x12c - L1 instruction Cache 3 autoload section 1 address configure register"] + #[inline(always)] + pub const fn l1_icache3_autoload_sct1_addr(&self) -> &L1_ICACHE3_AUTOLOAD_SCT1_ADDR { + &self.l1_icache3_autoload_sct1_addr + } + #[doc = "0x130 - L1 instruction Cache 3 autoload section 1 size configure register"] + #[inline(always)] + pub const fn l1_icache3_autoload_sct1_size(&self) -> &L1_ICACHE3_AUTOLOAD_SCT1_SIZE { + &self.l1_icache3_autoload_sct1_size + } + #[doc = "0x134 - L1 data Cache autoload-operation control register"] + #[inline(always)] + pub const fn l1_dcache_autoload_ctrl(&self) -> &L1_DCACHE_AUTOLOAD_CTRL { + &self.l1_dcache_autoload_ctrl + } + #[doc = "0x138 - L1 data Cache autoload section 0 address configure register"] + #[inline(always)] + pub const fn l1_dcache_autoload_sct0_addr(&self) -> &L1_DCACHE_AUTOLOAD_SCT0_ADDR { + &self.l1_dcache_autoload_sct0_addr + } + #[doc = "0x13c - L1 data Cache autoload section 0 size configure register"] + #[inline(always)] + pub const fn l1_dcache_autoload_sct0_size(&self) -> &L1_DCACHE_AUTOLOAD_SCT0_SIZE { + &self.l1_dcache_autoload_sct0_size + } + #[doc = "0x140 - L1 data Cache autoload section 1 address configure register"] + #[inline(always)] + pub const fn l1_dcache_autoload_sct1_addr(&self) -> &L1_DCACHE_AUTOLOAD_SCT1_ADDR { + &self.l1_dcache_autoload_sct1_addr + } + #[doc = "0x144 - L1 data Cache autoload section 1 size configure register"] + #[inline(always)] + pub const fn l1_dcache_autoload_sct1_size(&self) -> &L1_DCACHE_AUTOLOAD_SCT1_SIZE { + &self.l1_dcache_autoload_sct1_size + } + #[doc = "0x148 - L1 data Cache autoload section 2 address configure register"] + #[inline(always)] + pub const fn l1_dcache_autoload_sct2_addr(&self) -> &L1_DCACHE_AUTOLOAD_SCT2_ADDR { + &self.l1_dcache_autoload_sct2_addr + } + #[doc = "0x14c - L1 data Cache autoload section 2 size configure register"] + #[inline(always)] + pub const fn l1_dcache_autoload_sct2_size(&self) -> &L1_DCACHE_AUTOLOAD_SCT2_SIZE { + &self.l1_dcache_autoload_sct2_size + } + #[doc = "0x150 - L1 data Cache autoload section 1 address configure register"] + #[inline(always)] + pub const fn l1_dcache_autoload_sct3_addr(&self) -> &L1_DCACHE_AUTOLOAD_SCT3_ADDR { + &self.l1_dcache_autoload_sct3_addr + } + #[doc = "0x154 - L1 data Cache autoload section 1 size configure register"] + #[inline(always)] + pub const fn l1_dcache_autoload_sct3_size(&self) -> &L1_DCACHE_AUTOLOAD_SCT3_SIZE { + &self.l1_dcache_autoload_sct3_size + } + #[doc = "0x158 - Cache Access Counter Interrupt enable register"] + #[inline(always)] + pub const fn l1_cache_acs_cnt_int_ena(&self) -> &L1_CACHE_ACS_CNT_INT_ENA { + &self.l1_cache_acs_cnt_int_ena + } + #[doc = "0x15c - Cache Access Counter Interrupt clear register"] + #[inline(always)] + pub const fn l1_cache_acs_cnt_int_clr(&self) -> &L1_CACHE_ACS_CNT_INT_CLR { + &self.l1_cache_acs_cnt_int_clr + } + #[doc = "0x160 - Cache Access Counter Interrupt raw register"] + #[inline(always)] + pub const fn l1_cache_acs_cnt_int_raw(&self) -> &L1_CACHE_ACS_CNT_INT_RAW { + &self.l1_cache_acs_cnt_int_raw + } + #[doc = "0x164 - Cache Access Counter Interrupt status register"] + #[inline(always)] + pub const fn l1_cache_acs_cnt_int_st(&self) -> &L1_CACHE_ACS_CNT_INT_ST { + &self.l1_cache_acs_cnt_int_st + } + #[doc = "0x168 - Cache Access Fail Configuration register"] + #[inline(always)] + pub const fn l1_cache_acs_fail_ctrl(&self) -> &L1_CACHE_ACS_FAIL_CTRL { + &self.l1_cache_acs_fail_ctrl + } + #[doc = "0x16c - Cache Access Fail Interrupt enable register"] + #[inline(always)] + pub const fn l1_cache_acs_fail_int_ena(&self) -> &L1_CACHE_ACS_FAIL_INT_ENA { + &self.l1_cache_acs_fail_int_ena + } + #[doc = "0x170 - L1-Cache Access Fail Interrupt clear register"] + #[inline(always)] + pub const fn l1_cache_acs_fail_int_clr(&self) -> &L1_CACHE_ACS_FAIL_INT_CLR { + &self.l1_cache_acs_fail_int_clr + } + #[doc = "0x174 - Cache Access Fail Interrupt raw register"] + #[inline(always)] + pub const fn l1_cache_acs_fail_int_raw(&self) -> &L1_CACHE_ACS_FAIL_INT_RAW { + &self.l1_cache_acs_fail_int_raw + } + #[doc = "0x178 - Cache Access Fail Interrupt status register"] + #[inline(always)] + pub const fn l1_cache_acs_fail_int_st(&self) -> &L1_CACHE_ACS_FAIL_INT_ST { + &self.l1_cache_acs_fail_int_st + } + #[doc = "0x17c - Cache Access Counter enable and clear register"] + #[inline(always)] + pub const fn l1_cache_acs_cnt_ctrl(&self) -> &L1_CACHE_ACS_CNT_CTRL { + &self.l1_cache_acs_cnt_ctrl + } + #[doc = "0x180 - L1-ICache bus0 Hit-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus0_acs_hit_cnt(&self) -> &L1_IBUS0_ACS_HIT_CNT { + &self.l1_ibus0_acs_hit_cnt + } + #[doc = "0x184 - L1-ICache bus0 Miss-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus0_acs_miss_cnt(&self) -> &L1_IBUS0_ACS_MISS_CNT { + &self.l1_ibus0_acs_miss_cnt + } + #[doc = "0x188 - L1-ICache bus0 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus0_acs_conflict_cnt(&self) -> &L1_IBUS0_ACS_CONFLICT_CNT { + &self.l1_ibus0_acs_conflict_cnt + } + #[doc = "0x18c - L1-ICache bus0 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus0_acs_nxtlvl_rd_cnt(&self) -> &L1_IBUS0_ACS_NXTLVL_RD_CNT { + &self.l1_ibus0_acs_nxtlvl_rd_cnt + } + #[doc = "0x190 - L1-ICache bus1 Hit-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus1_acs_hit_cnt(&self) -> &L1_IBUS1_ACS_HIT_CNT { + &self.l1_ibus1_acs_hit_cnt + } + #[doc = "0x194 - L1-ICache bus1 Miss-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus1_acs_miss_cnt(&self) -> &L1_IBUS1_ACS_MISS_CNT { + &self.l1_ibus1_acs_miss_cnt + } + #[doc = "0x198 - L1-ICache bus1 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus1_acs_conflict_cnt(&self) -> &L1_IBUS1_ACS_CONFLICT_CNT { + &self.l1_ibus1_acs_conflict_cnt + } + #[doc = "0x19c - L1-ICache bus1 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus1_acs_nxtlvl_rd_cnt(&self) -> &L1_IBUS1_ACS_NXTLVL_RD_CNT { + &self.l1_ibus1_acs_nxtlvl_rd_cnt + } + #[doc = "0x1a0 - L1-ICache bus2 Hit-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus2_acs_hit_cnt(&self) -> &L1_IBUS2_ACS_HIT_CNT { + &self.l1_ibus2_acs_hit_cnt + } + #[doc = "0x1a4 - L1-ICache bus2 Miss-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus2_acs_miss_cnt(&self) -> &L1_IBUS2_ACS_MISS_CNT { + &self.l1_ibus2_acs_miss_cnt + } + #[doc = "0x1a8 - L1-ICache bus2 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus2_acs_conflict_cnt(&self) -> &L1_IBUS2_ACS_CONFLICT_CNT { + &self.l1_ibus2_acs_conflict_cnt + } + #[doc = "0x1ac - L1-ICache bus2 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus2_acs_nxtlvl_rd_cnt(&self) -> &L1_IBUS2_ACS_NXTLVL_RD_CNT { + &self.l1_ibus2_acs_nxtlvl_rd_cnt + } + #[doc = "0x1b0 - L1-ICache bus3 Hit-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus3_acs_hit_cnt(&self) -> &L1_IBUS3_ACS_HIT_CNT { + &self.l1_ibus3_acs_hit_cnt + } + #[doc = "0x1b4 - L1-ICache bus3 Miss-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus3_acs_miss_cnt(&self) -> &L1_IBUS3_ACS_MISS_CNT { + &self.l1_ibus3_acs_miss_cnt + } + #[doc = "0x1b8 - L1-ICache bus3 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus3_acs_conflict_cnt(&self) -> &L1_IBUS3_ACS_CONFLICT_CNT { + &self.l1_ibus3_acs_conflict_cnt + } + #[doc = "0x1bc - L1-ICache bus3 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l1_ibus3_acs_nxtlvl_rd_cnt(&self) -> &L1_IBUS3_ACS_NXTLVL_RD_CNT { + &self.l1_ibus3_acs_nxtlvl_rd_cnt + } + #[doc = "0x1c0 - L1-DCache bus0 Hit-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus0_acs_hit_cnt(&self) -> &L1_DBUS0_ACS_HIT_CNT { + &self.l1_dbus0_acs_hit_cnt + } + #[doc = "0x1c4 - L1-DCache bus0 Miss-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus0_acs_miss_cnt(&self) -> &L1_DBUS0_ACS_MISS_CNT { + &self.l1_dbus0_acs_miss_cnt + } + #[doc = "0x1c8 - L1-DCache bus0 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus0_acs_conflict_cnt(&self) -> &L1_DBUS0_ACS_CONFLICT_CNT { + &self.l1_dbus0_acs_conflict_cnt + } + #[doc = "0x1cc - L1-DCache bus0 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus0_acs_nxtlvl_rd_cnt(&self) -> &L1_DBUS0_ACS_NXTLVL_RD_CNT { + &self.l1_dbus0_acs_nxtlvl_rd_cnt + } + #[doc = "0x1d0 - L1-DCache bus0 WB-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus0_acs_nxtlvl_wr_cnt(&self) -> &L1_DBUS0_ACS_NXTLVL_WR_CNT { + &self.l1_dbus0_acs_nxtlvl_wr_cnt + } + #[doc = "0x1d4 - L1-DCache bus1 Hit-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus1_acs_hit_cnt(&self) -> &L1_DBUS1_ACS_HIT_CNT { + &self.l1_dbus1_acs_hit_cnt + } + #[doc = "0x1d8 - L1-DCache bus1 Miss-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus1_acs_miss_cnt(&self) -> &L1_DBUS1_ACS_MISS_CNT { + &self.l1_dbus1_acs_miss_cnt + } + #[doc = "0x1dc - L1-DCache bus1 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus1_acs_conflict_cnt(&self) -> &L1_DBUS1_ACS_CONFLICT_CNT { + &self.l1_dbus1_acs_conflict_cnt + } + #[doc = "0x1e0 - L1-DCache bus1 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus1_acs_nxtlvl_rd_cnt(&self) -> &L1_DBUS1_ACS_NXTLVL_RD_CNT { + &self.l1_dbus1_acs_nxtlvl_rd_cnt + } + #[doc = "0x1e4 - L1-DCache bus1 WB-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus1_acs_nxtlvl_wr_cnt(&self) -> &L1_DBUS1_ACS_NXTLVL_WR_CNT { + &self.l1_dbus1_acs_nxtlvl_wr_cnt + } + #[doc = "0x1e8 - L1-DCache bus2 Hit-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus2_acs_hit_cnt(&self) -> &L1_DBUS2_ACS_HIT_CNT { + &self.l1_dbus2_acs_hit_cnt + } + #[doc = "0x1ec - L1-DCache bus2 Miss-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus2_acs_miss_cnt(&self) -> &L1_DBUS2_ACS_MISS_CNT { + &self.l1_dbus2_acs_miss_cnt + } + #[doc = "0x1f0 - L1-DCache bus2 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus2_acs_conflict_cnt(&self) -> &L1_DBUS2_ACS_CONFLICT_CNT { + &self.l1_dbus2_acs_conflict_cnt + } + #[doc = "0x1f4 - L1-DCache bus2 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus2_acs_nxtlvl_rd_cnt(&self) -> &L1_DBUS2_ACS_NXTLVL_RD_CNT { + &self.l1_dbus2_acs_nxtlvl_rd_cnt + } + #[doc = "0x1f8 - L1-DCache bus2 WB-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus2_acs_nxtlvl_wr_cnt(&self) -> &L1_DBUS2_ACS_NXTLVL_WR_CNT { + &self.l1_dbus2_acs_nxtlvl_wr_cnt + } + #[doc = "0x1fc - L1-DCache bus3 Hit-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus3_acs_hit_cnt(&self) -> &L1_DBUS3_ACS_HIT_CNT { + &self.l1_dbus3_acs_hit_cnt + } + #[doc = "0x200 - L1-DCache bus3 Miss-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus3_acs_miss_cnt(&self) -> &L1_DBUS3_ACS_MISS_CNT { + &self.l1_dbus3_acs_miss_cnt + } + #[doc = "0x204 - L1-DCache bus3 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus3_acs_conflict_cnt(&self) -> &L1_DBUS3_ACS_CONFLICT_CNT { + &self.l1_dbus3_acs_conflict_cnt + } + #[doc = "0x208 - L1-DCache bus3 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus3_acs_nxtlvl_rd_cnt(&self) -> &L1_DBUS3_ACS_NXTLVL_RD_CNT { + &self.l1_dbus3_acs_nxtlvl_rd_cnt + } + #[doc = "0x20c - L1-DCache bus3 WB-Access Counter register"] + #[inline(always)] + pub const fn l1_dbus3_acs_nxtlvl_wr_cnt(&self) -> &L1_DBUS3_ACS_NXTLVL_WR_CNT { + &self.l1_dbus3_acs_nxtlvl_wr_cnt + } + #[doc = "0x210 - L1-ICache0 Access Fail ID/attribution information register"] + #[inline(always)] + pub const fn l1_icache0_acs_fail_id_attr(&self) -> &L1_ICACHE0_ACS_FAIL_ID_ATTR { + &self.l1_icache0_acs_fail_id_attr + } + #[doc = "0x214 - L1-ICache0 Access Fail Address information register"] + #[inline(always)] + pub const fn l1_icache0_acs_fail_addr(&self) -> &L1_ICACHE0_ACS_FAIL_ADDR { + &self.l1_icache0_acs_fail_addr + } + #[doc = "0x218 - L1-ICache0 Access Fail ID/attribution information register"] + #[inline(always)] + pub const fn l1_icache1_acs_fail_id_attr(&self) -> &L1_ICACHE1_ACS_FAIL_ID_ATTR { + &self.l1_icache1_acs_fail_id_attr + } + #[doc = "0x21c - L1-ICache0 Access Fail Address information register"] + #[inline(always)] + pub const fn l1_icache1_acs_fail_addr(&self) -> &L1_ICACHE1_ACS_FAIL_ADDR { + &self.l1_icache1_acs_fail_addr + } + #[doc = "0x220 - L1-ICache0 Access Fail ID/attribution information register"] + #[inline(always)] + pub const fn l1_icache2_acs_fail_id_attr(&self) -> &L1_ICACHE2_ACS_FAIL_ID_ATTR { + &self.l1_icache2_acs_fail_id_attr + } + #[doc = "0x224 - L1-ICache0 Access Fail Address information register"] + #[inline(always)] + pub const fn l1_icache2_acs_fail_addr(&self) -> &L1_ICACHE2_ACS_FAIL_ADDR { + &self.l1_icache2_acs_fail_addr + } + #[doc = "0x228 - L1-ICache0 Access Fail ID/attribution information register"] + #[inline(always)] + pub const fn l1_icache3_acs_fail_id_attr(&self) -> &L1_ICACHE3_ACS_FAIL_ID_ATTR { + &self.l1_icache3_acs_fail_id_attr + } + #[doc = "0x22c - L1-ICache0 Access Fail Address information register"] + #[inline(always)] + pub const fn l1_icache3_acs_fail_addr(&self) -> &L1_ICACHE3_ACS_FAIL_ADDR { + &self.l1_icache3_acs_fail_addr + } + #[doc = "0x230 - L1-DCache Access Fail ID/attribution information register"] + #[inline(always)] + pub const fn l1_dcache_acs_fail_id_attr(&self) -> &L1_DCACHE_ACS_FAIL_ID_ATTR { + &self.l1_dcache_acs_fail_id_attr + } + #[doc = "0x234 - L1-DCache Access Fail Address information register"] + #[inline(always)] + pub const fn l1_dcache_acs_fail_addr(&self) -> &L1_DCACHE_ACS_FAIL_ADDR { + &self.l1_dcache_acs_fail_addr + } + #[doc = "0x238 - L1-Cache Access Fail Interrupt enable register"] + #[inline(always)] + pub const fn sync_l1_cache_preload_int_ena(&self) -> &SYNC_L1_CACHE_PRELOAD_INT_ENA { + &self.sync_l1_cache_preload_int_ena + } + #[doc = "0x23c - Sync Preload operation Interrupt clear register"] + #[inline(always)] + pub const fn sync_l1_cache_preload_int_clr(&self) -> &SYNC_L1_CACHE_PRELOAD_INT_CLR { + &self.sync_l1_cache_preload_int_clr + } + #[doc = "0x240 - Sync Preload operation Interrupt raw register"] + #[inline(always)] + pub const fn sync_l1_cache_preload_int_raw(&self) -> &SYNC_L1_CACHE_PRELOAD_INT_RAW { + &self.sync_l1_cache_preload_int_raw + } + #[doc = "0x244 - L1-Cache Access Fail Interrupt status register"] + #[inline(always)] + pub const fn sync_l1_cache_preload_int_st(&self) -> &SYNC_L1_CACHE_PRELOAD_INT_ST { + &self.sync_l1_cache_preload_int_st + } + #[doc = "0x248 - Cache Sync/Preload Operation exception register"] + #[inline(always)] + pub const fn sync_l1_cache_preload_exception(&self) -> &SYNC_L1_CACHE_PRELOAD_EXCEPTION { + &self.sync_l1_cache_preload_exception + } + #[doc = "0x24c - Cache Sync Reset control register"] + #[inline(always)] + pub const fn l1_cache_sync_rst_ctrl(&self) -> &L1_CACHE_SYNC_RST_CTRL { + &self.l1_cache_sync_rst_ctrl + } + #[doc = "0x250 - Cache Preload Reset control register"] + #[inline(always)] + pub const fn l1_cache_preload_rst_ctrl(&self) -> &L1_CACHE_PRELOAD_RST_CTRL { + &self.l1_cache_preload_rst_ctrl + } + #[doc = "0x254 - Cache Autoload buffer clear control register"] + #[inline(always)] + pub const fn l1_cache_autoload_buf_clr_ctrl(&self) -> &L1_CACHE_AUTOLOAD_BUF_CLR_CTRL { + &self.l1_cache_autoload_buf_clr_ctrl + } + #[doc = "0x258 - Unallocate request buffer clear registers"] + #[inline(always)] + pub const fn l1_unallocate_buffer_clear(&self) -> &L1_UNALLOCATE_BUFFER_CLEAR { + &self.l1_unallocate_buffer_clear + } + #[doc = "0x25c - Cache Tag and Data memory Object control register"] + #[inline(always)] + pub const fn l1_cache_object_ctrl(&self) -> &L1_CACHE_OBJECT_CTRL { + &self.l1_cache_object_ctrl + } + #[doc = "0x260 - Cache Tag and Data memory way register"] + #[inline(always)] + pub const fn l1_cache_way_object(&self) -> &L1_CACHE_WAY_OBJECT { + &self.l1_cache_way_object + } + #[doc = "0x264 - Cache Vaddr register"] + #[inline(always)] + pub const fn l1_cache_vaddr(&self) -> &L1_CACHE_VADDR { + &self.l1_cache_vaddr + } + #[doc = "0x268 - Cache Tag/data memory content register"] + #[inline(always)] + pub const fn l1_cache_debug_bus(&self) -> &L1_CACHE_DEBUG_BUS { + &self.l1_cache_debug_bus + } + #[doc = "0x26c - USED TO SPLIT L1 CACHE AND L2 CACHE"] + #[inline(always)] + pub const fn level_split0(&self) -> &LEVEL_SPLIT0 { + &self.level_split0 + } + #[doc = "0x270 - L2 Cache(L2-Cache) control register"] + #[inline(always)] + pub const fn l2_cache_ctrl(&self) -> &L2_CACHE_CTRL { + &self.l2_cache_ctrl + } + #[doc = "0x274 - Bypass Cache configure register"] + #[inline(always)] + pub const fn l2_bypass_cache_conf(&self) -> &L2_BYPASS_CACHE_CONF { + &self.l2_bypass_cache_conf + } + #[doc = "0x278 - L2 Cache CacheSize mode configure register"] + #[inline(always)] + pub const fn l2_cache_cachesize_conf(&self) -> &L2_CACHE_CACHESIZE_CONF { + &self.l2_cache_cachesize_conf + } + #[doc = "0x27c - L2 Cache BlockSize mode configure register"] + #[inline(always)] + pub const fn l2_cache_blocksize_conf(&self) -> &L2_CACHE_BLOCKSIZE_CONF { + &self.l2_cache_blocksize_conf + } + #[doc = "0x280 - Cache wrap around control register"] + #[inline(always)] + pub const fn l2_cache_wrap_around_ctrl(&self) -> &L2_CACHE_WRAP_AROUND_CTRL { + &self.l2_cache_wrap_around_ctrl + } + #[doc = "0x284 - Cache tag memory power control register"] + #[inline(always)] + pub const fn l2_cache_tag_mem_power_ctrl(&self) -> &L2_CACHE_TAG_MEM_POWER_CTRL { + &self.l2_cache_tag_mem_power_ctrl + } + #[doc = "0x288 - Cache data memory power control register"] + #[inline(always)] + pub const fn l2_cache_data_mem_power_ctrl(&self) -> &L2_CACHE_DATA_MEM_POWER_CTRL { + &self.l2_cache_data_mem_power_ctrl + } + #[doc = "0x28c - Cache Freeze control register"] + #[inline(always)] + pub const fn l2_cache_freeze_ctrl(&self) -> &L2_CACHE_FREEZE_CTRL { + &self.l2_cache_freeze_ctrl + } + #[doc = "0x290 - Cache data memory access configure register"] + #[inline(always)] + pub const fn l2_cache_data_mem_acs_conf(&self) -> &L2_CACHE_DATA_MEM_ACS_CONF { + &self.l2_cache_data_mem_acs_conf + } + #[doc = "0x294 - Cache tag memory access configure register"] + #[inline(always)] + pub const fn l2_cache_tag_mem_acs_conf(&self) -> &L2_CACHE_TAG_MEM_ACS_CONF { + &self.l2_cache_tag_mem_acs_conf + } + #[doc = "0x298 - L2 Cache prelock configure register"] + #[inline(always)] + pub const fn l2_cache_prelock_conf(&self) -> &L2_CACHE_PRELOCK_CONF { + &self.l2_cache_prelock_conf + } + #[doc = "0x29c - L2 Cache prelock section0 address configure register"] + #[inline(always)] + pub const fn l2_cache_prelock_sct0_addr(&self) -> &L2_CACHE_PRELOCK_SCT0_ADDR { + &self.l2_cache_prelock_sct0_addr + } + #[doc = "0x2a0 - L2 Cache prelock section1 address configure register"] + #[inline(always)] + pub const fn l2_cache_prelock_sct1_addr(&self) -> &L2_CACHE_PRELOCK_SCT1_ADDR { + &self.l2_cache_prelock_sct1_addr + } + #[doc = "0x2a4 - L2 Cache prelock section size configure register"] + #[inline(always)] + pub const fn l2_cache_prelock_sct_size(&self) -> &L2_CACHE_PRELOCK_SCT_SIZE { + &self.l2_cache_prelock_sct_size + } + #[doc = "0x2a8 - L2 Cache preload-operation control register"] + #[inline(always)] + pub const fn l2_cache_preload_ctrl(&self) -> &L2_CACHE_PRELOAD_CTRL { + &self.l2_cache_preload_ctrl + } + #[doc = "0x2ac - L2 Cache preload address configure register"] + #[inline(always)] + pub const fn l2_cache_preload_addr(&self) -> &L2_CACHE_PRELOAD_ADDR { + &self.l2_cache_preload_addr + } + #[doc = "0x2b0 - L2 Cache preload size configure register"] + #[inline(always)] + pub const fn l2_cache_preload_size(&self) -> &L2_CACHE_PRELOAD_SIZE { + &self.l2_cache_preload_size + } + #[doc = "0x2b4 - L2 Cache autoload-operation control register"] + #[inline(always)] + pub const fn l2_cache_autoload_ctrl(&self) -> &L2_CACHE_AUTOLOAD_CTRL { + &self.l2_cache_autoload_ctrl + } + #[doc = "0x2b8 - L2 Cache autoload section 0 address configure register"] + #[inline(always)] + pub const fn l2_cache_autoload_sct0_addr(&self) -> &L2_CACHE_AUTOLOAD_SCT0_ADDR { + &self.l2_cache_autoload_sct0_addr + } + #[doc = "0x2bc - L2 Cache autoload section 0 size configure register"] + #[inline(always)] + pub const fn l2_cache_autoload_sct0_size(&self) -> &L2_CACHE_AUTOLOAD_SCT0_SIZE { + &self.l2_cache_autoload_sct0_size + } + #[doc = "0x2c0 - L2 Cache autoload section 1 address configure register"] + #[inline(always)] + pub const fn l2_cache_autoload_sct1_addr(&self) -> &L2_CACHE_AUTOLOAD_SCT1_ADDR { + &self.l2_cache_autoload_sct1_addr + } + #[doc = "0x2c4 - L2 Cache autoload section 1 size configure register"] + #[inline(always)] + pub const fn l2_cache_autoload_sct1_size(&self) -> &L2_CACHE_AUTOLOAD_SCT1_SIZE { + &self.l2_cache_autoload_sct1_size + } + #[doc = "0x2c8 - L2 Cache autoload section 2 address configure register"] + #[inline(always)] + pub const fn l2_cache_autoload_sct2_addr(&self) -> &L2_CACHE_AUTOLOAD_SCT2_ADDR { + &self.l2_cache_autoload_sct2_addr + } + #[doc = "0x2cc - L2 Cache autoload section 2 size configure register"] + #[inline(always)] + pub const fn l2_cache_autoload_sct2_size(&self) -> &L2_CACHE_AUTOLOAD_SCT2_SIZE { + &self.l2_cache_autoload_sct2_size + } + #[doc = "0x2d0 - L2 Cache autoload section 3 address configure register"] + #[inline(always)] + pub const fn l2_cache_autoload_sct3_addr(&self) -> &L2_CACHE_AUTOLOAD_SCT3_ADDR { + &self.l2_cache_autoload_sct3_addr + } + #[doc = "0x2d4 - L2 Cache autoload section 3 size configure register"] + #[inline(always)] + pub const fn l2_cache_autoload_sct3_size(&self) -> &L2_CACHE_AUTOLOAD_SCT3_SIZE { + &self.l2_cache_autoload_sct3_size + } + #[doc = "0x2d8 - Cache Access Counter Interrupt enable register"] + #[inline(always)] + pub const fn l2_cache_acs_cnt_int_ena(&self) -> &L2_CACHE_ACS_CNT_INT_ENA { + &self.l2_cache_acs_cnt_int_ena + } + #[doc = "0x2dc - Cache Access Counter Interrupt clear register"] + #[inline(always)] + pub const fn l2_cache_acs_cnt_int_clr(&self) -> &L2_CACHE_ACS_CNT_INT_CLR { + &self.l2_cache_acs_cnt_int_clr + } + #[doc = "0x2e0 - Cache Access Counter Interrupt raw register"] + #[inline(always)] + pub const fn l2_cache_acs_cnt_int_raw(&self) -> &L2_CACHE_ACS_CNT_INT_RAW { + &self.l2_cache_acs_cnt_int_raw + } + #[doc = "0x2e4 - Cache Access Counter Interrupt status register"] + #[inline(always)] + pub const fn l2_cache_acs_cnt_int_st(&self) -> &L2_CACHE_ACS_CNT_INT_ST { + &self.l2_cache_acs_cnt_int_st + } + #[doc = "0x2e8 - Cache Access Fail Configuration register"] + #[inline(always)] + pub const fn l2_cache_acs_fail_ctrl(&self) -> &L2_CACHE_ACS_FAIL_CTRL { + &self.l2_cache_acs_fail_ctrl + } + #[doc = "0x2ec - Cache Access Fail Interrupt enable register"] + #[inline(always)] + pub const fn l2_cache_acs_fail_int_ena(&self) -> &L2_CACHE_ACS_FAIL_INT_ENA { + &self.l2_cache_acs_fail_int_ena + } + #[doc = "0x2f0 - L1-Cache Access Fail Interrupt clear register"] + #[inline(always)] + pub const fn l2_cache_acs_fail_int_clr(&self) -> &L2_CACHE_ACS_FAIL_INT_CLR { + &self.l2_cache_acs_fail_int_clr + } + #[doc = "0x2f4 - Cache Access Fail Interrupt raw register"] + #[inline(always)] + pub const fn l2_cache_acs_fail_int_raw(&self) -> &L2_CACHE_ACS_FAIL_INT_RAW { + &self.l2_cache_acs_fail_int_raw + } + #[doc = "0x2f8 - Cache Access Fail Interrupt status register"] + #[inline(always)] + pub const fn l2_cache_acs_fail_int_st(&self) -> &L2_CACHE_ACS_FAIL_INT_ST { + &self.l2_cache_acs_fail_int_st + } + #[doc = "0x2fc - Cache Access Counter enable and clear register"] + #[inline(always)] + pub const fn l2_cache_acs_cnt_ctrl(&self) -> &L2_CACHE_ACS_CNT_CTRL { + &self.l2_cache_acs_cnt_ctrl + } + #[doc = "0x300 - L2-Cache bus0 Hit-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus0_acs_hit_cnt(&self) -> &L2_IBUS0_ACS_HIT_CNT { + &self.l2_ibus0_acs_hit_cnt + } + #[doc = "0x304 - L2-Cache bus0 Miss-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus0_acs_miss_cnt(&self) -> &L2_IBUS0_ACS_MISS_CNT { + &self.l2_ibus0_acs_miss_cnt + } + #[doc = "0x308 - L2-Cache bus0 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus0_acs_conflict_cnt(&self) -> &L2_IBUS0_ACS_CONFLICT_CNT { + &self.l2_ibus0_acs_conflict_cnt + } + #[doc = "0x30c - L2-Cache bus0 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus0_acs_nxtlvl_rd_cnt(&self) -> &L2_IBUS0_ACS_NXTLVL_RD_CNT { + &self.l2_ibus0_acs_nxtlvl_rd_cnt + } + #[doc = "0x310 - L2-Cache bus1 Hit-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus1_acs_hit_cnt(&self) -> &L2_IBUS1_ACS_HIT_CNT { + &self.l2_ibus1_acs_hit_cnt + } + #[doc = "0x314 - L2-Cache bus1 Miss-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus1_acs_miss_cnt(&self) -> &L2_IBUS1_ACS_MISS_CNT { + &self.l2_ibus1_acs_miss_cnt + } + #[doc = "0x318 - L2-Cache bus1 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus1_acs_conflict_cnt(&self) -> &L2_IBUS1_ACS_CONFLICT_CNT { + &self.l2_ibus1_acs_conflict_cnt + } + #[doc = "0x31c - L2-Cache bus1 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus1_acs_nxtlvl_rd_cnt(&self) -> &L2_IBUS1_ACS_NXTLVL_RD_CNT { + &self.l2_ibus1_acs_nxtlvl_rd_cnt + } + #[doc = "0x320 - L2-Cache bus2 Hit-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus2_acs_hit_cnt(&self) -> &L2_IBUS2_ACS_HIT_CNT { + &self.l2_ibus2_acs_hit_cnt + } + #[doc = "0x324 - L2-Cache bus2 Miss-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus2_acs_miss_cnt(&self) -> &L2_IBUS2_ACS_MISS_CNT { + &self.l2_ibus2_acs_miss_cnt + } + #[doc = "0x328 - L2-Cache bus2 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus2_acs_conflict_cnt(&self) -> &L2_IBUS2_ACS_CONFLICT_CNT { + &self.l2_ibus2_acs_conflict_cnt + } + #[doc = "0x32c - L2-Cache bus2 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus2_acs_nxtlvl_rd_cnt(&self) -> &L2_IBUS2_ACS_NXTLVL_RD_CNT { + &self.l2_ibus2_acs_nxtlvl_rd_cnt + } + #[doc = "0x330 - L2-Cache bus3 Hit-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus3_acs_hit_cnt(&self) -> &L2_IBUS3_ACS_HIT_CNT { + &self.l2_ibus3_acs_hit_cnt + } + #[doc = "0x334 - L2-Cache bus3 Miss-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus3_acs_miss_cnt(&self) -> &L2_IBUS3_ACS_MISS_CNT { + &self.l2_ibus3_acs_miss_cnt + } + #[doc = "0x338 - L2-Cache bus3 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus3_acs_conflict_cnt(&self) -> &L2_IBUS3_ACS_CONFLICT_CNT { + &self.l2_ibus3_acs_conflict_cnt + } + #[doc = "0x33c - L2-Cache bus3 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l2_ibus3_acs_nxtlvl_rd_cnt(&self) -> &L2_IBUS3_ACS_NXTLVL_RD_CNT { + &self.l2_ibus3_acs_nxtlvl_rd_cnt + } + #[doc = "0x340 - L2-Cache bus0 Hit-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus0_acs_hit_cnt(&self) -> &L2_DBUS0_ACS_HIT_CNT { + &self.l2_dbus0_acs_hit_cnt + } + #[doc = "0x344 - L2-Cache bus0 Miss-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus0_acs_miss_cnt(&self) -> &L2_DBUS0_ACS_MISS_CNT { + &self.l2_dbus0_acs_miss_cnt + } + #[doc = "0x348 - L2-Cache bus0 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus0_acs_conflict_cnt(&self) -> &L2_DBUS0_ACS_CONFLICT_CNT { + &self.l2_dbus0_acs_conflict_cnt + } + #[doc = "0x34c - L2-Cache bus0 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus0_acs_nxtlvl_rd_cnt(&self) -> &L2_DBUS0_ACS_NXTLVL_RD_CNT { + &self.l2_dbus0_acs_nxtlvl_rd_cnt + } + #[doc = "0x350 - L2-Cache bus0 WB-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus0_acs_nxtlvl_wr_cnt(&self) -> &L2_DBUS0_ACS_NXTLVL_WR_CNT { + &self.l2_dbus0_acs_nxtlvl_wr_cnt + } + #[doc = "0x354 - L2-Cache bus1 Hit-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus1_acs_hit_cnt(&self) -> &L2_DBUS1_ACS_HIT_CNT { + &self.l2_dbus1_acs_hit_cnt + } + #[doc = "0x358 - L2-Cache bus1 Miss-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus1_acs_miss_cnt(&self) -> &L2_DBUS1_ACS_MISS_CNT { + &self.l2_dbus1_acs_miss_cnt + } + #[doc = "0x35c - L2-Cache bus1 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus1_acs_conflict_cnt(&self) -> &L2_DBUS1_ACS_CONFLICT_CNT { + &self.l2_dbus1_acs_conflict_cnt + } + #[doc = "0x360 - L2-Cache bus1 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus1_acs_nxtlvl_rd_cnt(&self) -> &L2_DBUS1_ACS_NXTLVL_RD_CNT { + &self.l2_dbus1_acs_nxtlvl_rd_cnt + } + #[doc = "0x364 - L2-Cache bus1 WB-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus1_acs_nxtlvl_wr_cnt(&self) -> &L2_DBUS1_ACS_NXTLVL_WR_CNT { + &self.l2_dbus1_acs_nxtlvl_wr_cnt + } + #[doc = "0x368 - L2-Cache bus2 Hit-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus2_acs_hit_cnt(&self) -> &L2_DBUS2_ACS_HIT_CNT { + &self.l2_dbus2_acs_hit_cnt + } + #[doc = "0x36c - L2-Cache bus2 Miss-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus2_acs_miss_cnt(&self) -> &L2_DBUS2_ACS_MISS_CNT { + &self.l2_dbus2_acs_miss_cnt + } + #[doc = "0x370 - L2-Cache bus2 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus2_acs_conflict_cnt(&self) -> &L2_DBUS2_ACS_CONFLICT_CNT { + &self.l2_dbus2_acs_conflict_cnt + } + #[doc = "0x374 - L2-Cache bus2 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus2_acs_nxtlvl_rd_cnt(&self) -> &L2_DBUS2_ACS_NXTLVL_RD_CNT { + &self.l2_dbus2_acs_nxtlvl_rd_cnt + } + #[doc = "0x378 - L2-Cache bus2 WB-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus2_acs_nxtlvl_wr_cnt(&self) -> &L2_DBUS2_ACS_NXTLVL_WR_CNT { + &self.l2_dbus2_acs_nxtlvl_wr_cnt + } + #[doc = "0x37c - L2-Cache bus3 Hit-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus3_acs_hit_cnt(&self) -> &L2_DBUS3_ACS_HIT_CNT { + &self.l2_dbus3_acs_hit_cnt + } + #[doc = "0x380 - L2-Cache bus3 Miss-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus3_acs_miss_cnt(&self) -> &L2_DBUS3_ACS_MISS_CNT { + &self.l2_dbus3_acs_miss_cnt + } + #[doc = "0x384 - L2-Cache bus3 Conflict-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus3_acs_conflict_cnt(&self) -> &L2_DBUS3_ACS_CONFLICT_CNT { + &self.l2_dbus3_acs_conflict_cnt + } + #[doc = "0x388 - L2-Cache bus3 Next-Level-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus3_acs_nxtlvl_rd_cnt(&self) -> &L2_DBUS3_ACS_NXTLVL_RD_CNT { + &self.l2_dbus3_acs_nxtlvl_rd_cnt + } + #[doc = "0x38c - L2-Cache bus3 WB-Access Counter register"] + #[inline(always)] + pub const fn l2_dbus3_acs_nxtlvl_wr_cnt(&self) -> &L2_DBUS3_ACS_NXTLVL_WR_CNT { + &self.l2_dbus3_acs_nxtlvl_wr_cnt + } + #[doc = "0x390 - L2-Cache Access Fail ID/attribution information register"] + #[inline(always)] + pub const fn l2_cache_acs_fail_id_attr(&self) -> &L2_CACHE_ACS_FAIL_ID_ATTR { + &self.l2_cache_acs_fail_id_attr + } + #[doc = "0x394 - L2-Cache Access Fail Address information register"] + #[inline(always)] + pub const fn l2_cache_acs_fail_addr(&self) -> &L2_CACHE_ACS_FAIL_ADDR { + &self.l2_cache_acs_fail_addr + } + #[doc = "0x398 - L1-Cache Access Fail Interrupt enable register"] + #[inline(always)] + pub const fn l2_cache_sync_preload_int_ena(&self) -> &L2_CACHE_SYNC_PRELOAD_INT_ENA { + &self.l2_cache_sync_preload_int_ena + } + #[doc = "0x39c - Sync Preload operation Interrupt clear register"] + #[inline(always)] + pub const fn l2_cache_sync_preload_int_clr(&self) -> &L2_CACHE_SYNC_PRELOAD_INT_CLR { + &self.l2_cache_sync_preload_int_clr + } + #[doc = "0x3a0 - Sync Preload operation Interrupt raw register"] + #[inline(always)] + pub const fn l2_cache_sync_preload_int_raw(&self) -> &L2_CACHE_SYNC_PRELOAD_INT_RAW { + &self.l2_cache_sync_preload_int_raw + } + #[doc = "0x3a4 - L1-Cache Access Fail Interrupt status register"] + #[inline(always)] + pub const fn l2_cache_sync_preload_int_st(&self) -> &L2_CACHE_SYNC_PRELOAD_INT_ST { + &self.l2_cache_sync_preload_int_st + } + #[doc = "0x3a8 - Cache Sync/Preload Operation exception register"] + #[inline(always)] + pub const fn l2_cache_sync_preload_exception(&self) -> &L2_CACHE_SYNC_PRELOAD_EXCEPTION { + &self.l2_cache_sync_preload_exception + } + #[doc = "0x3ac - Cache Sync Reset control register"] + #[inline(always)] + pub const fn l2_cache_sync_rst_ctrl(&self) -> &L2_CACHE_SYNC_RST_CTRL { + &self.l2_cache_sync_rst_ctrl + } + #[doc = "0x3b0 - Cache Preload Reset control register"] + #[inline(always)] + pub const fn l2_cache_preload_rst_ctrl(&self) -> &L2_CACHE_PRELOAD_RST_CTRL { + &self.l2_cache_preload_rst_ctrl + } + #[doc = "0x3b4 - Cache Autoload buffer clear control register"] + #[inline(always)] + pub const fn l2_cache_autoload_buf_clr_ctrl(&self) -> &L2_CACHE_AUTOLOAD_BUF_CLR_CTRL { + &self.l2_cache_autoload_buf_clr_ctrl + } + #[doc = "0x3b8 - Unallocate request buffer clear registers"] + #[inline(always)] + pub const fn l2_unallocate_buffer_clear(&self) -> &L2_UNALLOCATE_BUFFER_CLEAR { + &self.l2_unallocate_buffer_clear + } + #[doc = "0x3bc - L2 cache access attribute control register"] + #[inline(always)] + pub const fn l2_cache_access_attr_ctrl(&self) -> &L2_CACHE_ACCESS_ATTR_CTRL { + &self.l2_cache_access_attr_ctrl + } + #[doc = "0x3c0 - Cache Tag and Data memory Object control register"] + #[inline(always)] + pub const fn l2_cache_object_ctrl(&self) -> &L2_CACHE_OBJECT_CTRL { + &self.l2_cache_object_ctrl + } + #[doc = "0x3c4 - Cache Tag and Data memory way register"] + #[inline(always)] + pub const fn l2_cache_way_object(&self) -> &L2_CACHE_WAY_OBJECT { + &self.l2_cache_way_object + } + #[doc = "0x3c8 - Cache Vaddr register"] + #[inline(always)] + pub const fn l2_cache_vaddr(&self) -> &L2_CACHE_VADDR { + &self.l2_cache_vaddr + } + #[doc = "0x3cc - Cache Tag/data memory content register"] + #[inline(always)] + pub const fn l2_cache_debug_bus(&self) -> &L2_CACHE_DEBUG_BUS { + &self.l2_cache_debug_bus + } + #[doc = "0x3d0 - USED TO SPLIT L1 CACHE AND L2 CACHE"] + #[inline(always)] + pub const fn level_split1(&self) -> &LEVEL_SPLIT1 { + &self.level_split1 + } + #[doc = "0x3d4 - Clock gate control register"] + #[inline(always)] + pub const fn clock_gate(&self) -> &CLOCK_GATE { + &self.clock_gate + } + #[doc = "0x3d8 - Cache redundancy signal 0 register"] + #[inline(always)] + pub const fn redundancy_sig0(&self) -> &REDUNDANCY_SIG0 { + &self.redundancy_sig0 + } + #[doc = "0x3dc - Cache redundancy signal 1 register"] + #[inline(always)] + pub const fn redundancy_sig1(&self) -> &REDUNDANCY_SIG1 { + &self.redundancy_sig1 + } + #[doc = "0x3e0 - Cache redundancy signal 2 register"] + #[inline(always)] + pub const fn redundancy_sig2(&self) -> &REDUNDANCY_SIG2 { + &self.redundancy_sig2 + } + #[doc = "0x3e4 - Cache redundancy signal 3 register"] + #[inline(always)] + pub const fn redundancy_sig3(&self) -> &REDUNDANCY_SIG3 { + &self.redundancy_sig3 + } + #[doc = "0x3e8 - Cache redundancy signal 0 register"] + #[inline(always)] + pub const fn redundancy_sig4(&self) -> &REDUNDANCY_SIG4 { + &self.redundancy_sig4 + } + #[doc = "0x3fc - Version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "L1_ICACHE_CTRL (rw) register accessor: L1 instruction Cache(L1-ICache) control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache_ctrl`] module"] +pub type L1_ICACHE_CTRL = crate::Reg; +#[doc = "L1 instruction Cache(L1-ICache) control register"] +pub mod l1_icache_ctrl; +#[doc = "L1_DCACHE_CTRL (rw) register accessor: L1 data Cache(L1-DCache) control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_ctrl`] module"] +pub type L1_DCACHE_CTRL = crate::Reg; +#[doc = "L1 data Cache(L1-DCache) control register"] +pub mod l1_dcache_ctrl; +#[doc = "L1_BYPASS_CACHE_CONF (rw) register accessor: Bypass Cache configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bypass_cache_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_bypass_cache_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_bypass_cache_conf`] module"] +pub type L1_BYPASS_CACHE_CONF = crate::Reg; +#[doc = "Bypass Cache configure register"] +pub mod l1_bypass_cache_conf; +#[doc = "L1_CACHE_ATOMIC_CONF (rw) register accessor: L1 Cache atomic feature configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_atomic_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_atomic_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_atomic_conf`] module"] +pub type L1_CACHE_ATOMIC_CONF = crate::Reg; +#[doc = "L1 Cache atomic feature configure register"] +pub mod l1_cache_atomic_conf; +#[doc = "L1_ICACHE_CACHESIZE_CONF (r) register accessor: L1 instruction Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_cachesize_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache_cachesize_conf`] module"] +pub type L1_ICACHE_CACHESIZE_CONF = + crate::Reg; +#[doc = "L1 instruction Cache CacheSize mode configure register"] +pub mod l1_icache_cachesize_conf; +#[doc = "L1_ICACHE_BLOCKSIZE_CONF (r) register accessor: L1 instruction Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_blocksize_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache_blocksize_conf`] module"] +pub type L1_ICACHE_BLOCKSIZE_CONF = + crate::Reg; +#[doc = "L1 instruction Cache BlockSize mode configure register"] +pub mod l1_icache_blocksize_conf; +#[doc = "L1_DCACHE_CACHESIZE_CONF (r) register accessor: L1 data Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_cachesize_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_cachesize_conf`] module"] +pub type L1_DCACHE_CACHESIZE_CONF = + crate::Reg; +#[doc = "L1 data Cache CacheSize mode configure register"] +pub mod l1_dcache_cachesize_conf; +#[doc = "L1_DCACHE_BLOCKSIZE_CONF (r) register accessor: L1 data Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_blocksize_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_blocksize_conf`] module"] +pub type L1_DCACHE_BLOCKSIZE_CONF = + crate::Reg; +#[doc = "L1 data Cache BlockSize mode configure register"] +pub mod l1_dcache_blocksize_conf; +#[doc = "L1_CACHE_WRAP_AROUND_CTRL (rw) register accessor: Cache wrap around control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_wrap_around_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_wrap_around_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_wrap_around_ctrl`] module"] +pub type L1_CACHE_WRAP_AROUND_CTRL = + crate::Reg; +#[doc = "Cache wrap around control register"] +pub mod l1_cache_wrap_around_ctrl; +#[doc = "L1_CACHE_TAG_MEM_POWER_CTRL (rw) register accessor: Cache tag memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_tag_mem_power_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_tag_mem_power_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_tag_mem_power_ctrl`] module"] +pub type L1_CACHE_TAG_MEM_POWER_CTRL = + crate::Reg; +#[doc = "Cache tag memory power control register"] +pub mod l1_cache_tag_mem_power_ctrl; +#[doc = "L1_CACHE_DATA_MEM_POWER_CTRL (rw) register accessor: Cache data memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_data_mem_power_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_data_mem_power_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_data_mem_power_ctrl`] module"] +pub type L1_CACHE_DATA_MEM_POWER_CTRL = + crate::Reg; +#[doc = "Cache data memory power control register"] +pub mod l1_cache_data_mem_power_ctrl; +#[doc = "L1_CACHE_FREEZE_CTRL (rw) register accessor: Cache Freeze control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_freeze_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_freeze_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_freeze_ctrl`] module"] +pub type L1_CACHE_FREEZE_CTRL = crate::Reg; +#[doc = "Cache Freeze control register"] +pub mod l1_cache_freeze_ctrl; +#[doc = "L1_CACHE_DATA_MEM_ACS_CONF (rw) register accessor: Cache data memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_data_mem_acs_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_data_mem_acs_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_data_mem_acs_conf`] module"] +pub type L1_CACHE_DATA_MEM_ACS_CONF = + crate::Reg; +#[doc = "Cache data memory access configure register"] +pub mod l1_cache_data_mem_acs_conf; +#[doc = "L1_CACHE_TAG_MEM_ACS_CONF (rw) register accessor: Cache tag memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_tag_mem_acs_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_tag_mem_acs_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_tag_mem_acs_conf`] module"] +pub type L1_CACHE_TAG_MEM_ACS_CONF = + crate::Reg; +#[doc = "Cache tag memory access configure register"] +pub mod l1_cache_tag_mem_acs_conf; +#[doc = "L1_ICACHE0_PRELOCK_CONF (rw) register accessor: L1 instruction Cache 0 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_prelock_conf`] module"] +pub type L1_ICACHE0_PRELOCK_CONF = + crate::Reg; +#[doc = "L1 instruction Cache 0 prelock configure register"] +pub mod l1_icache0_prelock_conf; +#[doc = "L1_ICACHE0_PRELOCK_SCT0_ADDR (rw) register accessor: L1 instruction Cache 0 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_prelock_sct0_addr`] module"] +pub type L1_ICACHE0_PRELOCK_SCT0_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 0 prelock section0 address configure register"] +pub mod l1_icache0_prelock_sct0_addr; +#[doc = "L1_ICACHE0_PRELOCK_SCT1_ADDR (rw) register accessor: L1 instruction Cache 0 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_prelock_sct1_addr`] module"] +pub type L1_ICACHE0_PRELOCK_SCT1_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 0 prelock section1 address configure register"] +pub mod l1_icache0_prelock_sct1_addr; +#[doc = "L1_ICACHE0_PRELOCK_SCT_SIZE (rw) register accessor: L1 instruction Cache 0 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_sct_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_prelock_sct_size`] module"] +pub type L1_ICACHE0_PRELOCK_SCT_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 0 prelock section size configure register"] +pub mod l1_icache0_prelock_sct_size; +#[doc = "L1_ICACHE1_PRELOCK_CONF (rw) register accessor: L1 instruction Cache 1 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_prelock_conf`] module"] +pub type L1_ICACHE1_PRELOCK_CONF = + crate::Reg; +#[doc = "L1 instruction Cache 1 prelock configure register"] +pub mod l1_icache1_prelock_conf; +#[doc = "L1_ICACHE1_PRELOCK_SCT0_ADDR (rw) register accessor: L1 instruction Cache 1 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_prelock_sct0_addr`] module"] +pub type L1_ICACHE1_PRELOCK_SCT0_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 1 prelock section0 address configure register"] +pub mod l1_icache1_prelock_sct0_addr; +#[doc = "L1_ICACHE1_PRELOCK_SCT1_ADDR (rw) register accessor: L1 instruction Cache 1 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_prelock_sct1_addr`] module"] +pub type L1_ICACHE1_PRELOCK_SCT1_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 1 prelock section1 address configure register"] +pub mod l1_icache1_prelock_sct1_addr; +#[doc = "L1_ICACHE1_PRELOCK_SCT_SIZE (rw) register accessor: L1 instruction Cache 1 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_sct_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_prelock_sct_size`] module"] +pub type L1_ICACHE1_PRELOCK_SCT_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 1 prelock section size configure register"] +pub mod l1_icache1_prelock_sct_size; +#[doc = "L1_ICACHE2_PRELOCK_CONF (r) register accessor: L1 instruction Cache 2 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_prelock_conf`] module"] +pub type L1_ICACHE2_PRELOCK_CONF = + crate::Reg; +#[doc = "L1 instruction Cache 2 prelock configure register"] +pub mod l1_icache2_prelock_conf; +#[doc = "L1_ICACHE2_PRELOCK_SCT0_ADDR (r) register accessor: L1 instruction Cache 2 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct0_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_prelock_sct0_addr`] module"] +pub type L1_ICACHE2_PRELOCK_SCT0_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 2 prelock section0 address configure register"] +pub mod l1_icache2_prelock_sct0_addr; +#[doc = "L1_ICACHE2_PRELOCK_SCT1_ADDR (r) register accessor: L1 instruction Cache 2 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct1_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_prelock_sct1_addr`] module"] +pub type L1_ICACHE2_PRELOCK_SCT1_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 2 prelock section1 address configure register"] +pub mod l1_icache2_prelock_sct1_addr; +#[doc = "L1_ICACHE2_PRELOCK_SCT_SIZE (r) register accessor: L1 instruction Cache 2 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_prelock_sct_size`] module"] +pub type L1_ICACHE2_PRELOCK_SCT_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 2 prelock section size configure register"] +pub mod l1_icache2_prelock_sct_size; +#[doc = "L1_ICACHE3_PRELOCK_CONF (r) register accessor: L1 instruction Cache 3 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_conf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_prelock_conf`] module"] +pub type L1_ICACHE3_PRELOCK_CONF = + crate::Reg; +#[doc = "L1 instruction Cache 3 prelock configure register"] +pub mod l1_icache3_prelock_conf; +#[doc = "L1_ICACHE3_PRELOCK_SCT0_ADDR (r) register accessor: L1 instruction Cache 3 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct0_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_prelock_sct0_addr`] module"] +pub type L1_ICACHE3_PRELOCK_SCT0_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 3 prelock section0 address configure register"] +pub mod l1_icache3_prelock_sct0_addr; +#[doc = "L1_ICACHE3_PRELOCK_SCT1_ADDR (r) register accessor: L1 instruction Cache 3 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct1_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_prelock_sct1_addr`] module"] +pub type L1_ICACHE3_PRELOCK_SCT1_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 3 prelock section1 address configure register"] +pub mod l1_icache3_prelock_sct1_addr; +#[doc = "L1_ICACHE3_PRELOCK_SCT_SIZE (r) register accessor: L1 instruction Cache 3 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_prelock_sct_size`] module"] +pub type L1_ICACHE3_PRELOCK_SCT_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 3 prelock section size configure register"] +pub mod l1_icache3_prelock_sct_size; +#[doc = "L1_DCACHE_PRELOCK_CONF (rw) register accessor: L1 data Cache prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_prelock_conf`] module"] +pub type L1_DCACHE_PRELOCK_CONF = crate::Reg; +#[doc = "L1 data Cache prelock configure register"] +pub mod l1_dcache_prelock_conf; +#[doc = "L1_DCACHE_PRELOCK_SCT0_ADDR (rw) register accessor: L1 data Cache prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_prelock_sct0_addr`] module"] +pub type L1_DCACHE_PRELOCK_SCT0_ADDR = + crate::Reg; +#[doc = "L1 data Cache prelock section0 address configure register"] +pub mod l1_dcache_prelock_sct0_addr; +#[doc = "L1_DCACHE_PRELOCK_SCT1_ADDR (rw) register accessor: L1 data Cache prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_prelock_sct1_addr`] module"] +pub type L1_DCACHE_PRELOCK_SCT1_ADDR = + crate::Reg; +#[doc = "L1 data Cache prelock section1 address configure register"] +pub mod l1_dcache_prelock_sct1_addr; +#[doc = "L1_DCACHE_PRELOCK_SCT_SIZE (rw) register accessor: L1 data Cache prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_sct_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_sct_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_prelock_sct_size`] module"] +pub type L1_DCACHE_PRELOCK_SCT_SIZE = + crate::Reg; +#[doc = "L1 data Cache prelock section size configure register"] +pub mod l1_dcache_prelock_sct_size; +#[doc = "LOCK_CTRL (rw) register accessor: Lock-class (manual lock) operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock_ctrl`] module"] +pub type LOCK_CTRL = crate::Reg; +#[doc = "Lock-class (manual lock) operation control register"] +pub mod lock_ctrl; +#[doc = "LOCK_MAP (rw) register accessor: Lock (manual lock) map configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock_map`] module"] +pub type LOCK_MAP = crate::Reg; +#[doc = "Lock (manual lock) map configure register"] +pub mod lock_map; +#[doc = "LOCK_ADDR (rw) register accessor: Lock (manual lock) address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock_addr`] module"] +pub type LOCK_ADDR = crate::Reg; +#[doc = "Lock (manual lock) address configure register"] +pub mod lock_addr; +#[doc = "LOCK_SIZE (rw) register accessor: Lock (manual lock) size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock_size`] module"] +pub type LOCK_SIZE = crate::Reg; +#[doc = "Lock (manual lock) size configure register"] +pub mod lock_size; +#[doc = "SYNC_CTRL (rw) register accessor: Sync-class operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_ctrl`] module"] +pub type SYNC_CTRL = crate::Reg; +#[doc = "Sync-class operation control register"] +pub mod sync_ctrl; +#[doc = "SYNC_MAP (rw) register accessor: Sync map configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_map`] module"] +pub type SYNC_MAP = crate::Reg; +#[doc = "Sync map configure register"] +pub mod sync_map; +#[doc = "SYNC_ADDR (rw) register accessor: Sync address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_addr`] module"] +pub type SYNC_ADDR = crate::Reg; +#[doc = "Sync address configure register"] +pub mod sync_addr; +#[doc = "SYNC_SIZE (rw) register accessor: Sync size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_size`] module"] +pub type SYNC_SIZE = crate::Reg; +#[doc = "Sync size configure register"] +pub mod sync_size; +#[doc = "L1_ICACHE0_PRELOAD_CTRL (rw) register accessor: L1 instruction Cache 0 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_preload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_preload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_preload_ctrl`] module"] +pub type L1_ICACHE0_PRELOAD_CTRL = + crate::Reg; +#[doc = "L1 instruction Cache 0 preload-operation control register"] +pub mod l1_icache0_preload_ctrl; +#[doc = "L1_ICACHE0_PRELOAD_ADDR (rw) register accessor: L1 instruction Cache 0 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_preload_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_preload_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_preload_addr`] module"] +pub type L1_ICACHE0_PRELOAD_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 0 preload address configure register"] +pub mod l1_icache0_preload_addr; +#[doc = "L1_ICACHE0_PRELOAD_SIZE (rw) register accessor: L1 instruction Cache 0 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_preload_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_preload_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_preload_size`] module"] +pub type L1_ICACHE0_PRELOAD_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 0 preload size configure register"] +pub mod l1_icache0_preload_size; +#[doc = "L1_ICACHE1_PRELOAD_CTRL (rw) register accessor: L1 instruction Cache 1 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_preload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_preload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_preload_ctrl`] module"] +pub type L1_ICACHE1_PRELOAD_CTRL = + crate::Reg; +#[doc = "L1 instruction Cache 1 preload-operation control register"] +pub mod l1_icache1_preload_ctrl; +#[doc = "L1_ICACHE1_PRELOAD_ADDR (rw) register accessor: L1 instruction Cache 1 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_preload_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_preload_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_preload_addr`] module"] +pub type L1_ICACHE1_PRELOAD_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 1 preload address configure register"] +pub mod l1_icache1_preload_addr; +#[doc = "L1_ICACHE1_PRELOAD_SIZE (rw) register accessor: L1 instruction Cache 1 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_preload_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_preload_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_preload_size`] module"] +pub type L1_ICACHE1_PRELOAD_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 1 preload size configure register"] +pub mod l1_icache1_preload_size; +#[doc = "L1_ICACHE2_PRELOAD_CTRL (r) register accessor: L1 instruction Cache 2 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_ctrl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_preload_ctrl`] module"] +pub type L1_ICACHE2_PRELOAD_CTRL = + crate::Reg; +#[doc = "L1 instruction Cache 2 preload-operation control register"] +pub mod l1_icache2_preload_ctrl; +#[doc = "L1_ICACHE2_PRELOAD_ADDR (r) register accessor: L1 instruction Cache 2 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_preload_addr`] module"] +pub type L1_ICACHE2_PRELOAD_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 2 preload address configure register"] +pub mod l1_icache2_preload_addr; +#[doc = "L1_ICACHE2_PRELOAD_SIZE (r) register accessor: L1 instruction Cache 2 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_preload_size`] module"] +pub type L1_ICACHE2_PRELOAD_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 2 preload size configure register"] +pub mod l1_icache2_preload_size; +#[doc = "L1_ICACHE3_PRELOAD_CTRL (r) register accessor: L1 instruction Cache 3 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_ctrl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_preload_ctrl`] module"] +pub type L1_ICACHE3_PRELOAD_CTRL = + crate::Reg; +#[doc = "L1 instruction Cache 3 preload-operation control register"] +pub mod l1_icache3_preload_ctrl; +#[doc = "L1_ICACHE3_PRELOAD_ADDR (r) register accessor: L1 instruction Cache 3 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_preload_addr`] module"] +pub type L1_ICACHE3_PRELOAD_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 3 preload address configure register"] +pub mod l1_icache3_preload_addr; +#[doc = "L1_ICACHE3_PRELOAD_SIZE (r) register accessor: L1 instruction Cache 3 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_preload_size`] module"] +pub type L1_ICACHE3_PRELOAD_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 3 preload size configure register"] +pub mod l1_icache3_preload_size; +#[doc = "L1_DCACHE_PRELOAD_CTRL (rw) register accessor: L1 data Cache preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_preload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_preload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_preload_ctrl`] module"] +pub type L1_DCACHE_PRELOAD_CTRL = crate::Reg; +#[doc = "L1 data Cache preload-operation control register"] +pub mod l1_dcache_preload_ctrl; +#[doc = "L1_DCACHE_PRELOAD_ADDR (rw) register accessor: L1 data Cache preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_preload_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_preload_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_preload_addr`] module"] +pub type L1_DCACHE_PRELOAD_ADDR = crate::Reg; +#[doc = "L1 data Cache preload address configure register"] +pub mod l1_dcache_preload_addr; +#[doc = "L1_DCACHE_PRELOAD_SIZE (rw) register accessor: L1 data Cache preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_preload_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_preload_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_preload_size`] module"] +pub type L1_DCACHE_PRELOAD_SIZE = crate::Reg; +#[doc = "L1 data Cache preload size configure register"] +pub mod l1_dcache_preload_size; +#[doc = "L1_ICACHE0_AUTOLOAD_CTRL (rw) register accessor: L1 instruction Cache 0 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_autoload_ctrl`] module"] +pub type L1_ICACHE0_AUTOLOAD_CTRL = + crate::Reg; +#[doc = "L1 instruction Cache 0 autoload-operation control register"] +pub mod l1_icache0_autoload_ctrl; +#[doc = "L1_ICACHE0_AUTOLOAD_SCT0_ADDR (rw) register accessor: L1 instruction Cache 0 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_autoload_sct0_addr`] module"] +pub type L1_ICACHE0_AUTOLOAD_SCT0_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 0 autoload section 0 address configure register"] +pub mod l1_icache0_autoload_sct0_addr; +#[doc = "L1_ICACHE0_AUTOLOAD_SCT0_SIZE (rw) register accessor: L1 instruction Cache 0 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct0_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct0_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_autoload_sct0_size`] module"] +pub type L1_ICACHE0_AUTOLOAD_SCT0_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 0 autoload section 0 size configure register"] +pub mod l1_icache0_autoload_sct0_size; +#[doc = "L1_ICACHE0_AUTOLOAD_SCT1_ADDR (rw) register accessor: L1 instruction Cache 0 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_autoload_sct1_addr`] module"] +pub type L1_ICACHE0_AUTOLOAD_SCT1_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 0 autoload section 1 address configure register"] +pub mod l1_icache0_autoload_sct1_addr; +#[doc = "L1_ICACHE0_AUTOLOAD_SCT1_SIZE (rw) register accessor: L1 instruction Cache 0 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct1_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct1_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_autoload_sct1_size`] module"] +pub type L1_ICACHE0_AUTOLOAD_SCT1_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 0 autoload section 1 size configure register"] +pub mod l1_icache0_autoload_sct1_size; +#[doc = "L1_ICACHE1_AUTOLOAD_CTRL (rw) register accessor: L1 instruction Cache 1 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_autoload_ctrl`] module"] +pub type L1_ICACHE1_AUTOLOAD_CTRL = + crate::Reg; +#[doc = "L1 instruction Cache 1 autoload-operation control register"] +pub mod l1_icache1_autoload_ctrl; +#[doc = "L1_ICACHE1_AUTOLOAD_SCT0_ADDR (rw) register accessor: L1 instruction Cache 1 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_autoload_sct0_addr`] module"] +pub type L1_ICACHE1_AUTOLOAD_SCT0_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 1 autoload section 0 address configure register"] +pub mod l1_icache1_autoload_sct0_addr; +#[doc = "L1_ICACHE1_AUTOLOAD_SCT0_SIZE (rw) register accessor: L1 instruction Cache 1 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct0_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct0_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_autoload_sct0_size`] module"] +pub type L1_ICACHE1_AUTOLOAD_SCT0_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 1 autoload section 0 size configure register"] +pub mod l1_icache1_autoload_sct0_size; +#[doc = "L1_ICACHE1_AUTOLOAD_SCT1_ADDR (rw) register accessor: L1 instruction Cache 1 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_autoload_sct1_addr`] module"] +pub type L1_ICACHE1_AUTOLOAD_SCT1_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 1 autoload section 1 address configure register"] +pub mod l1_icache1_autoload_sct1_addr; +#[doc = "L1_ICACHE1_AUTOLOAD_SCT1_SIZE (rw) register accessor: L1 instruction Cache 1 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct1_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct1_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_autoload_sct1_size`] module"] +pub type L1_ICACHE1_AUTOLOAD_SCT1_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 1 autoload section 1 size configure register"] +pub mod l1_icache1_autoload_sct1_size; +#[doc = "L1_ICACHE2_AUTOLOAD_CTRL (r) register accessor: L1 instruction Cache 2 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_ctrl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_autoload_ctrl`] module"] +pub type L1_ICACHE2_AUTOLOAD_CTRL = + crate::Reg; +#[doc = "L1 instruction Cache 2 autoload-operation control register"] +pub mod l1_icache2_autoload_ctrl; +#[doc = "L1_ICACHE2_AUTOLOAD_SCT0_ADDR (r) register accessor: L1 instruction Cache 2 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct0_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_autoload_sct0_addr`] module"] +pub type L1_ICACHE2_AUTOLOAD_SCT0_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 2 autoload section 0 address configure register"] +pub mod l1_icache2_autoload_sct0_addr; +#[doc = "L1_ICACHE2_AUTOLOAD_SCT0_SIZE (r) register accessor: L1 instruction Cache 2 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct0_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_autoload_sct0_size`] module"] +pub type L1_ICACHE2_AUTOLOAD_SCT0_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 2 autoload section 0 size configure register"] +pub mod l1_icache2_autoload_sct0_size; +#[doc = "L1_ICACHE2_AUTOLOAD_SCT1_ADDR (r) register accessor: L1 instruction Cache 2 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct1_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_autoload_sct1_addr`] module"] +pub type L1_ICACHE2_AUTOLOAD_SCT1_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 2 autoload section 1 address configure register"] +pub mod l1_icache2_autoload_sct1_addr; +#[doc = "L1_ICACHE2_AUTOLOAD_SCT1_SIZE (r) register accessor: L1 instruction Cache 2 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct1_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_autoload_sct1_size`] module"] +pub type L1_ICACHE2_AUTOLOAD_SCT1_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 2 autoload section 1 size configure register"] +pub mod l1_icache2_autoload_sct1_size; +#[doc = "L1_ICACHE3_AUTOLOAD_CTRL (r) register accessor: L1 instruction Cache 3 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_ctrl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_autoload_ctrl`] module"] +pub type L1_ICACHE3_AUTOLOAD_CTRL = + crate::Reg; +#[doc = "L1 instruction Cache 3 autoload-operation control register"] +pub mod l1_icache3_autoload_ctrl; +#[doc = "L1_ICACHE3_AUTOLOAD_SCT0_ADDR (r) register accessor: L1 instruction Cache 3 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct0_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_autoload_sct0_addr`] module"] +pub type L1_ICACHE3_AUTOLOAD_SCT0_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 3 autoload section 0 address configure register"] +pub mod l1_icache3_autoload_sct0_addr; +#[doc = "L1_ICACHE3_AUTOLOAD_SCT0_SIZE (r) register accessor: L1 instruction Cache 3 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct0_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_autoload_sct0_size`] module"] +pub type L1_ICACHE3_AUTOLOAD_SCT0_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 3 autoload section 0 size configure register"] +pub mod l1_icache3_autoload_sct0_size; +#[doc = "L1_ICACHE3_AUTOLOAD_SCT1_ADDR (r) register accessor: L1 instruction Cache 3 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct1_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_autoload_sct1_addr`] module"] +pub type L1_ICACHE3_AUTOLOAD_SCT1_ADDR = + crate::Reg; +#[doc = "L1 instruction Cache 3 autoload section 1 address configure register"] +pub mod l1_icache3_autoload_sct1_addr; +#[doc = "L1_ICACHE3_AUTOLOAD_SCT1_SIZE (r) register accessor: L1 instruction Cache 3 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct1_size::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_autoload_sct1_size`] module"] +pub type L1_ICACHE3_AUTOLOAD_SCT1_SIZE = + crate::Reg; +#[doc = "L1 instruction Cache 3 autoload section 1 size configure register"] +pub mod l1_icache3_autoload_sct1_size; +#[doc = "L1_DCACHE_AUTOLOAD_CTRL (rw) register accessor: L1 data Cache autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_ctrl`] module"] +pub type L1_DCACHE_AUTOLOAD_CTRL = + crate::Reg; +#[doc = "L1 data Cache autoload-operation control register"] +pub mod l1_dcache_autoload_ctrl; +#[doc = "L1_DCACHE_AUTOLOAD_SCT0_ADDR (rw) register accessor: L1 data Cache autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct0_addr`] module"] +pub type L1_DCACHE_AUTOLOAD_SCT0_ADDR = + crate::Reg; +#[doc = "L1 data Cache autoload section 0 address configure register"] +pub mod l1_dcache_autoload_sct0_addr; +#[doc = "L1_DCACHE_AUTOLOAD_SCT0_SIZE (rw) register accessor: L1 data Cache autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct0_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct0_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct0_size`] module"] +pub type L1_DCACHE_AUTOLOAD_SCT0_SIZE = + crate::Reg; +#[doc = "L1 data Cache autoload section 0 size configure register"] +pub mod l1_dcache_autoload_sct0_size; +#[doc = "L1_DCACHE_AUTOLOAD_SCT1_ADDR (rw) register accessor: L1 data Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct1_addr`] module"] +pub type L1_DCACHE_AUTOLOAD_SCT1_ADDR = + crate::Reg; +#[doc = "L1 data Cache autoload section 1 address configure register"] +pub mod l1_dcache_autoload_sct1_addr; +#[doc = "L1_DCACHE_AUTOLOAD_SCT1_SIZE (rw) register accessor: L1 data Cache autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct1_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct1_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct1_size`] module"] +pub type L1_DCACHE_AUTOLOAD_SCT1_SIZE = + crate::Reg; +#[doc = "L1 data Cache autoload section 1 size configure register"] +pub mod l1_dcache_autoload_sct1_size; +#[doc = "L1_DCACHE_AUTOLOAD_SCT2_ADDR (rw) register accessor: L1 data Cache autoload section 2 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct2_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct2_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct2_addr`] module"] +pub type L1_DCACHE_AUTOLOAD_SCT2_ADDR = + crate::Reg; +#[doc = "L1 data Cache autoload section 2 address configure register"] +pub mod l1_dcache_autoload_sct2_addr; +#[doc = "L1_DCACHE_AUTOLOAD_SCT2_SIZE (rw) register accessor: L1 data Cache autoload section 2 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct2_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct2_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct2_size`] module"] +pub type L1_DCACHE_AUTOLOAD_SCT2_SIZE = + crate::Reg; +#[doc = "L1 data Cache autoload section 2 size configure register"] +pub mod l1_dcache_autoload_sct2_size; +#[doc = "L1_DCACHE_AUTOLOAD_SCT3_ADDR (rw) register accessor: L1 data Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct3_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct3_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct3_addr`] module"] +pub type L1_DCACHE_AUTOLOAD_SCT3_ADDR = + crate::Reg; +#[doc = "L1 data Cache autoload section 1 address configure register"] +pub mod l1_dcache_autoload_sct3_addr; +#[doc = "L1_DCACHE_AUTOLOAD_SCT3_SIZE (rw) register accessor: L1 data Cache autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct3_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct3_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_autoload_sct3_size`] module"] +pub type L1_DCACHE_AUTOLOAD_SCT3_SIZE = + crate::Reg; +#[doc = "L1 data Cache autoload section 1 size configure register"] +pub mod l1_dcache_autoload_sct3_size; +#[doc = "L1_CACHE_ACS_CNT_INT_ENA (rw) register accessor: Cache Access Counter Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_cnt_int_ena`] module"] +pub type L1_CACHE_ACS_CNT_INT_ENA = + crate::Reg; +#[doc = "Cache Access Counter Interrupt enable register"] +pub mod l1_cache_acs_cnt_int_ena; +#[doc = "L1_CACHE_ACS_CNT_INT_CLR (rw) register accessor: Cache Access Counter Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_int_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_cnt_int_clr`] module"] +pub type L1_CACHE_ACS_CNT_INT_CLR = + crate::Reg; +#[doc = "Cache Access Counter Interrupt clear register"] +pub mod l1_cache_acs_cnt_int_clr; +#[doc = "L1_CACHE_ACS_CNT_INT_RAW (rw) register accessor: Cache Access Counter Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_cnt_int_raw`] module"] +pub type L1_CACHE_ACS_CNT_INT_RAW = + crate::Reg; +#[doc = "Cache Access Counter Interrupt raw register"] +pub mod l1_cache_acs_cnt_int_raw; +#[doc = "L1_CACHE_ACS_CNT_INT_ST (r) register accessor: Cache Access Counter Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_cnt_int_st`] module"] +pub type L1_CACHE_ACS_CNT_INT_ST = + crate::Reg; +#[doc = "Cache Access Counter Interrupt status register"] +pub mod l1_cache_acs_cnt_int_st; +#[doc = "L1_CACHE_ACS_FAIL_CTRL (rw) register accessor: Cache Access Fail Configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_fail_ctrl`] module"] +pub type L1_CACHE_ACS_FAIL_CTRL = crate::Reg; +#[doc = "Cache Access Fail Configuration register"] +pub mod l1_cache_acs_fail_ctrl; +#[doc = "L1_CACHE_ACS_FAIL_INT_ENA (rw) register accessor: Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_fail_int_ena`] module"] +pub type L1_CACHE_ACS_FAIL_INT_ENA = + crate::Reg; +#[doc = "Cache Access Fail Interrupt enable register"] +pub mod l1_cache_acs_fail_int_ena; +#[doc = "L1_CACHE_ACS_FAIL_INT_CLR (rw) register accessor: L1-Cache Access Fail Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_fail_int_clr`] module"] +pub type L1_CACHE_ACS_FAIL_INT_CLR = + crate::Reg; +#[doc = "L1-Cache Access Fail Interrupt clear register"] +pub mod l1_cache_acs_fail_int_clr; +#[doc = "L1_CACHE_ACS_FAIL_INT_RAW (rw) register accessor: Cache Access Fail Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_fail_int_raw`] module"] +pub type L1_CACHE_ACS_FAIL_INT_RAW = + crate::Reg; +#[doc = "Cache Access Fail Interrupt raw register"] +pub mod l1_cache_acs_fail_int_raw; +#[doc = "L1_CACHE_ACS_FAIL_INT_ST (r) register accessor: Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_fail_int_st`] module"] +pub type L1_CACHE_ACS_FAIL_INT_ST = + crate::Reg; +#[doc = "Cache Access Fail Interrupt status register"] +pub mod l1_cache_acs_fail_int_st; +#[doc = "L1_CACHE_ACS_CNT_CTRL (rw) register accessor: Cache Access Counter enable and clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_acs_cnt_ctrl`] module"] +pub type L1_CACHE_ACS_CNT_CTRL = crate::Reg; +#[doc = "Cache Access Counter enable and clear register"] +pub mod l1_cache_acs_cnt_ctrl; +#[doc = "L1_IBUS0_ACS_HIT_CNT (r) register accessor: L1-ICache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus0_acs_hit_cnt`] module"] +pub type L1_IBUS0_ACS_HIT_CNT = crate::Reg; +#[doc = "L1-ICache bus0 Hit-Access Counter register"] +pub mod l1_ibus0_acs_hit_cnt; +#[doc = "L1_IBUS0_ACS_MISS_CNT (r) register accessor: L1-ICache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus0_acs_miss_cnt`] module"] +pub type L1_IBUS0_ACS_MISS_CNT = crate::Reg; +#[doc = "L1-ICache bus0 Miss-Access Counter register"] +pub mod l1_ibus0_acs_miss_cnt; +#[doc = "L1_IBUS0_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus0_acs_conflict_cnt`] module"] +pub type L1_IBUS0_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L1-ICache bus0 Conflict-Access Counter register"] +pub mod l1_ibus0_acs_conflict_cnt; +#[doc = "L1_IBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus0_acs_nxtlvl_rd_cnt`] module"] +pub type L1_IBUS0_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L1-ICache bus0 Next-Level-Access Counter register"] +pub mod l1_ibus0_acs_nxtlvl_rd_cnt; +#[doc = "L1_IBUS1_ACS_HIT_CNT (r) register accessor: L1-ICache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus1_acs_hit_cnt`] module"] +pub type L1_IBUS1_ACS_HIT_CNT = crate::Reg; +#[doc = "L1-ICache bus1 Hit-Access Counter register"] +pub mod l1_ibus1_acs_hit_cnt; +#[doc = "L1_IBUS1_ACS_MISS_CNT (r) register accessor: L1-ICache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus1_acs_miss_cnt`] module"] +pub type L1_IBUS1_ACS_MISS_CNT = crate::Reg; +#[doc = "L1-ICache bus1 Miss-Access Counter register"] +pub mod l1_ibus1_acs_miss_cnt; +#[doc = "L1_IBUS1_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus1_acs_conflict_cnt`] module"] +pub type L1_IBUS1_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L1-ICache bus1 Conflict-Access Counter register"] +pub mod l1_ibus1_acs_conflict_cnt; +#[doc = "L1_IBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus1_acs_nxtlvl_rd_cnt`] module"] +pub type L1_IBUS1_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L1-ICache bus1 Next-Level-Access Counter register"] +pub mod l1_ibus1_acs_nxtlvl_rd_cnt; +#[doc = "L1_IBUS2_ACS_HIT_CNT (r) register accessor: L1-ICache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus2_acs_hit_cnt`] module"] +pub type L1_IBUS2_ACS_HIT_CNT = crate::Reg; +#[doc = "L1-ICache bus2 Hit-Access Counter register"] +pub mod l1_ibus2_acs_hit_cnt; +#[doc = "L1_IBUS2_ACS_MISS_CNT (r) register accessor: L1-ICache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus2_acs_miss_cnt`] module"] +pub type L1_IBUS2_ACS_MISS_CNT = crate::Reg; +#[doc = "L1-ICache bus2 Miss-Access Counter register"] +pub mod l1_ibus2_acs_miss_cnt; +#[doc = "L1_IBUS2_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus2_acs_conflict_cnt`] module"] +pub type L1_IBUS2_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L1-ICache bus2 Conflict-Access Counter register"] +pub mod l1_ibus2_acs_conflict_cnt; +#[doc = "L1_IBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus2_acs_nxtlvl_rd_cnt`] module"] +pub type L1_IBUS2_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L1-ICache bus2 Next-Level-Access Counter register"] +pub mod l1_ibus2_acs_nxtlvl_rd_cnt; +#[doc = "L1_IBUS3_ACS_HIT_CNT (r) register accessor: L1-ICache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus3_acs_hit_cnt`] module"] +pub type L1_IBUS3_ACS_HIT_CNT = crate::Reg; +#[doc = "L1-ICache bus3 Hit-Access Counter register"] +pub mod l1_ibus3_acs_hit_cnt; +#[doc = "L1_IBUS3_ACS_MISS_CNT (r) register accessor: L1-ICache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus3_acs_miss_cnt`] module"] +pub type L1_IBUS3_ACS_MISS_CNT = crate::Reg; +#[doc = "L1-ICache bus3 Miss-Access Counter register"] +pub mod l1_ibus3_acs_miss_cnt; +#[doc = "L1_IBUS3_ACS_CONFLICT_CNT (r) register accessor: L1-ICache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus3_acs_conflict_cnt`] module"] +pub type L1_IBUS3_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L1-ICache bus3 Conflict-Access Counter register"] +pub mod l1_ibus3_acs_conflict_cnt; +#[doc = "L1_IBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L1-ICache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_ibus3_acs_nxtlvl_rd_cnt`] module"] +pub type L1_IBUS3_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L1-ICache bus3 Next-Level-Access Counter register"] +pub mod l1_ibus3_acs_nxtlvl_rd_cnt; +#[doc = "L1_DBUS0_ACS_HIT_CNT (r) register accessor: L1-DCache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus0_acs_hit_cnt`] module"] +pub type L1_DBUS0_ACS_HIT_CNT = crate::Reg; +#[doc = "L1-DCache bus0 Hit-Access Counter register"] +pub mod l1_dbus0_acs_hit_cnt; +#[doc = "L1_DBUS0_ACS_MISS_CNT (r) register accessor: L1-DCache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus0_acs_miss_cnt`] module"] +pub type L1_DBUS0_ACS_MISS_CNT = crate::Reg; +#[doc = "L1-DCache bus0 Miss-Access Counter register"] +pub mod l1_dbus0_acs_miss_cnt; +#[doc = "L1_DBUS0_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus0_acs_conflict_cnt`] module"] +pub type L1_DBUS0_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L1-DCache bus0 Conflict-Access Counter register"] +pub mod l1_dbus0_acs_conflict_cnt; +#[doc = "L1_DBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus0_acs_nxtlvl_rd_cnt`] module"] +pub type L1_DBUS0_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L1-DCache bus0 Next-Level-Access Counter register"] +pub mod l1_dbus0_acs_nxtlvl_rd_cnt; +#[doc = "L1_DBUS0_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus0 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus0_acs_nxtlvl_wr_cnt`] module"] +pub type L1_DBUS0_ACS_NXTLVL_WR_CNT = + crate::Reg; +#[doc = "L1-DCache bus0 WB-Access Counter register"] +pub mod l1_dbus0_acs_nxtlvl_wr_cnt; +#[doc = "L1_DBUS1_ACS_HIT_CNT (r) register accessor: L1-DCache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus1_acs_hit_cnt`] module"] +pub type L1_DBUS1_ACS_HIT_CNT = crate::Reg; +#[doc = "L1-DCache bus1 Hit-Access Counter register"] +pub mod l1_dbus1_acs_hit_cnt; +#[doc = "L1_DBUS1_ACS_MISS_CNT (r) register accessor: L1-DCache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus1_acs_miss_cnt`] module"] +pub type L1_DBUS1_ACS_MISS_CNT = crate::Reg; +#[doc = "L1-DCache bus1 Miss-Access Counter register"] +pub mod l1_dbus1_acs_miss_cnt; +#[doc = "L1_DBUS1_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus1_acs_conflict_cnt`] module"] +pub type L1_DBUS1_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L1-DCache bus1 Conflict-Access Counter register"] +pub mod l1_dbus1_acs_conflict_cnt; +#[doc = "L1_DBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus1_acs_nxtlvl_rd_cnt`] module"] +pub type L1_DBUS1_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L1-DCache bus1 Next-Level-Access Counter register"] +pub mod l1_dbus1_acs_nxtlvl_rd_cnt; +#[doc = "L1_DBUS1_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus1 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus1_acs_nxtlvl_wr_cnt`] module"] +pub type L1_DBUS1_ACS_NXTLVL_WR_CNT = + crate::Reg; +#[doc = "L1-DCache bus1 WB-Access Counter register"] +pub mod l1_dbus1_acs_nxtlvl_wr_cnt; +#[doc = "L1_DBUS2_ACS_HIT_CNT (r) register accessor: L1-DCache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus2_acs_hit_cnt`] module"] +pub type L1_DBUS2_ACS_HIT_CNT = crate::Reg; +#[doc = "L1-DCache bus2 Hit-Access Counter register"] +pub mod l1_dbus2_acs_hit_cnt; +#[doc = "L1_DBUS2_ACS_MISS_CNT (r) register accessor: L1-DCache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus2_acs_miss_cnt`] module"] +pub type L1_DBUS2_ACS_MISS_CNT = crate::Reg; +#[doc = "L1-DCache bus2 Miss-Access Counter register"] +pub mod l1_dbus2_acs_miss_cnt; +#[doc = "L1_DBUS2_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus2_acs_conflict_cnt`] module"] +pub type L1_DBUS2_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L1-DCache bus2 Conflict-Access Counter register"] +pub mod l1_dbus2_acs_conflict_cnt; +#[doc = "L1_DBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus2_acs_nxtlvl_rd_cnt`] module"] +pub type L1_DBUS2_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L1-DCache bus2 Next-Level-Access Counter register"] +pub mod l1_dbus2_acs_nxtlvl_rd_cnt; +#[doc = "L1_DBUS2_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus2 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus2_acs_nxtlvl_wr_cnt`] module"] +pub type L1_DBUS2_ACS_NXTLVL_WR_CNT = + crate::Reg; +#[doc = "L1-DCache bus2 WB-Access Counter register"] +pub mod l1_dbus2_acs_nxtlvl_wr_cnt; +#[doc = "L1_DBUS3_ACS_HIT_CNT (r) register accessor: L1-DCache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus3_acs_hit_cnt`] module"] +pub type L1_DBUS3_ACS_HIT_CNT = crate::Reg; +#[doc = "L1-DCache bus3 Hit-Access Counter register"] +pub mod l1_dbus3_acs_hit_cnt; +#[doc = "L1_DBUS3_ACS_MISS_CNT (r) register accessor: L1-DCache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus3_acs_miss_cnt`] module"] +pub type L1_DBUS3_ACS_MISS_CNT = crate::Reg; +#[doc = "L1-DCache bus3 Miss-Access Counter register"] +pub mod l1_dbus3_acs_miss_cnt; +#[doc = "L1_DBUS3_ACS_CONFLICT_CNT (r) register accessor: L1-DCache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus3_acs_conflict_cnt`] module"] +pub type L1_DBUS3_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L1-DCache bus3 Conflict-Access Counter register"] +pub mod l1_dbus3_acs_conflict_cnt; +#[doc = "L1_DBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L1-DCache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus3_acs_nxtlvl_rd_cnt`] module"] +pub type L1_DBUS3_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L1-DCache bus3 Next-Level-Access Counter register"] +pub mod l1_dbus3_acs_nxtlvl_rd_cnt; +#[doc = "L1_DBUS3_ACS_NXTLVL_WR_CNT (r) register accessor: L1-DCache bus3 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dbus3_acs_nxtlvl_wr_cnt`] module"] +pub type L1_DBUS3_ACS_NXTLVL_WR_CNT = + crate::Reg; +#[doc = "L1-DCache bus3 WB-Access Counter register"] +pub mod l1_dbus3_acs_nxtlvl_wr_cnt; +#[doc = "L1_ICACHE0_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_acs_fail_id_attr`] module"] +pub type L1_ICACHE0_ACS_FAIL_ID_ATTR = + crate::Reg; +#[doc = "L1-ICache0 Access Fail ID/attribution information register"] +pub mod l1_icache0_acs_fail_id_attr; +#[doc = "L1_ICACHE0_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache0_acs_fail_addr`] module"] +pub type L1_ICACHE0_ACS_FAIL_ADDR = + crate::Reg; +#[doc = "L1-ICache0 Access Fail Address information register"] +pub mod l1_icache0_acs_fail_addr; +#[doc = "L1_ICACHE1_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_acs_fail_id_attr`] module"] +pub type L1_ICACHE1_ACS_FAIL_ID_ATTR = + crate::Reg; +#[doc = "L1-ICache0 Access Fail ID/attribution information register"] +pub mod l1_icache1_acs_fail_id_attr; +#[doc = "L1_ICACHE1_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache1_acs_fail_addr`] module"] +pub type L1_ICACHE1_ACS_FAIL_ADDR = + crate::Reg; +#[doc = "L1-ICache0 Access Fail Address information register"] +pub mod l1_icache1_acs_fail_addr; +#[doc = "L1_ICACHE2_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_acs_fail_id_attr`] module"] +pub type L1_ICACHE2_ACS_FAIL_ID_ATTR = + crate::Reg; +#[doc = "L1-ICache0 Access Fail ID/attribution information register"] +pub mod l1_icache2_acs_fail_id_attr; +#[doc = "L1_ICACHE2_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache2_acs_fail_addr`] module"] +pub type L1_ICACHE2_ACS_FAIL_ADDR = + crate::Reg; +#[doc = "L1-ICache0 Access Fail Address information register"] +pub mod l1_icache2_acs_fail_addr; +#[doc = "L1_ICACHE3_ACS_FAIL_ID_ATTR (r) register accessor: L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_acs_fail_id_attr`] module"] +pub type L1_ICACHE3_ACS_FAIL_ID_ATTR = + crate::Reg; +#[doc = "L1-ICache0 Access Fail ID/attribution information register"] +pub mod l1_icache3_acs_fail_id_attr; +#[doc = "L1_ICACHE3_ACS_FAIL_ADDR (r) register accessor: L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_icache3_acs_fail_addr`] module"] +pub type L1_ICACHE3_ACS_FAIL_ADDR = + crate::Reg; +#[doc = "L1-ICache0 Access Fail Address information register"] +pub mod l1_icache3_acs_fail_addr; +#[doc = "L1_DCACHE_ACS_FAIL_ID_ATTR (r) register accessor: L1-DCache Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_acs_fail_id_attr`] module"] +pub type L1_DCACHE_ACS_FAIL_ID_ATTR = + crate::Reg; +#[doc = "L1-DCache Access Fail ID/attribution information register"] +pub mod l1_dcache_acs_fail_id_attr; +#[doc = "L1_DCACHE_ACS_FAIL_ADDR (r) register accessor: L1-DCache Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_dcache_acs_fail_addr`] module"] +pub type L1_DCACHE_ACS_FAIL_ADDR = + crate::Reg; +#[doc = "L1-DCache Access Fail Address information register"] +pub mod l1_dcache_acs_fail_addr; +#[doc = "SYNC_L1_CACHE_PRELOAD_INT_ENA (rw) register accessor: L1-Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_l1_cache_preload_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_l1_cache_preload_int_ena`] module"] +pub type SYNC_L1_CACHE_PRELOAD_INT_ENA = + crate::Reg; +#[doc = "L1-Cache Access Fail Interrupt enable register"] +pub mod sync_l1_cache_preload_int_ena; +#[doc = "SYNC_L1_CACHE_PRELOAD_INT_CLR (rw) register accessor: Sync Preload operation Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_l1_cache_preload_int_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_l1_cache_preload_int_clr`] module"] +pub type SYNC_L1_CACHE_PRELOAD_INT_CLR = + crate::Reg; +#[doc = "Sync Preload operation Interrupt clear register"] +pub mod sync_l1_cache_preload_int_clr; +#[doc = "SYNC_L1_CACHE_PRELOAD_INT_RAW (rw) register accessor: Sync Preload operation Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_l1_cache_preload_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_l1_cache_preload_int_raw`] module"] +pub type SYNC_L1_CACHE_PRELOAD_INT_RAW = + crate::Reg; +#[doc = "Sync Preload operation Interrupt raw register"] +pub mod sync_l1_cache_preload_int_raw; +#[doc = "SYNC_L1_CACHE_PRELOAD_INT_ST (r) register accessor: L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_l1_cache_preload_int_st`] module"] +pub type SYNC_L1_CACHE_PRELOAD_INT_ST = + crate::Reg; +#[doc = "L1-Cache Access Fail Interrupt status register"] +pub mod sync_l1_cache_preload_int_st; +#[doc = "SYNC_L1_CACHE_PRELOAD_EXCEPTION (r) register accessor: Cache Sync/Preload Operation exception register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_exception::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_l1_cache_preload_exception`] module"] +pub type SYNC_L1_CACHE_PRELOAD_EXCEPTION = + crate::Reg; +#[doc = "Cache Sync/Preload Operation exception register"] +pub mod sync_l1_cache_preload_exception; +#[doc = "L1_CACHE_SYNC_RST_CTRL (rw) register accessor: Cache Sync Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_sync_rst_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_sync_rst_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_sync_rst_ctrl`] module"] +pub type L1_CACHE_SYNC_RST_CTRL = crate::Reg; +#[doc = "Cache Sync Reset control register"] +pub mod l1_cache_sync_rst_ctrl; +#[doc = "L1_CACHE_PRELOAD_RST_CTRL (rw) register accessor: Cache Preload Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_preload_rst_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_preload_rst_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_preload_rst_ctrl`] module"] +pub type L1_CACHE_PRELOAD_RST_CTRL = + crate::Reg; +#[doc = "Cache Preload Reset control register"] +pub mod l1_cache_preload_rst_ctrl; +#[doc = "L1_CACHE_AUTOLOAD_BUF_CLR_CTRL (rw) register accessor: Cache Autoload buffer clear control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_autoload_buf_clr_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_autoload_buf_clr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_autoload_buf_clr_ctrl`] module"] +pub type L1_CACHE_AUTOLOAD_BUF_CLR_CTRL = + crate::Reg; +#[doc = "Cache Autoload buffer clear control register"] +pub mod l1_cache_autoload_buf_clr_ctrl; +#[doc = "L1_UNALLOCATE_BUFFER_CLEAR (rw) register accessor: Unallocate request buffer clear registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_unallocate_buffer_clear::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_unallocate_buffer_clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_unallocate_buffer_clear`] module"] +pub type L1_UNALLOCATE_BUFFER_CLEAR = + crate::Reg; +#[doc = "Unallocate request buffer clear registers"] +pub mod l1_unallocate_buffer_clear; +#[doc = "L1_CACHE_OBJECT_CTRL (rw) register accessor: Cache Tag and Data memory Object control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_object_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_object_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_object_ctrl`] module"] +pub type L1_CACHE_OBJECT_CTRL = crate::Reg; +#[doc = "Cache Tag and Data memory Object control register"] +pub mod l1_cache_object_ctrl; +#[doc = "L1_CACHE_WAY_OBJECT (rw) register accessor: Cache Tag and Data memory way register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_way_object::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_way_object::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_way_object`] module"] +pub type L1_CACHE_WAY_OBJECT = crate::Reg; +#[doc = "Cache Tag and Data memory way register"] +pub mod l1_cache_way_object; +#[doc = "L1_CACHE_VADDR (rw) register accessor: Cache Vaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_vaddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_vaddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_vaddr`] module"] +pub type L1_CACHE_VADDR = crate::Reg; +#[doc = "Cache Vaddr register"] +pub mod l1_cache_vaddr; +#[doc = "L1_CACHE_DEBUG_BUS (rw) register accessor: Cache Tag/data memory content register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_debug_bus::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_debug_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l1_cache_debug_bus`] module"] +pub type L1_CACHE_DEBUG_BUS = crate::Reg; +#[doc = "Cache Tag/data memory content register"] +pub mod l1_cache_debug_bus; +#[doc = "LEVEL_SPLIT0 (r) register accessor: USED TO SPLIT L1 CACHE AND L2 CACHE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`level_split0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@level_split0`] module"] +pub type LEVEL_SPLIT0 = crate::Reg; +#[doc = "USED TO SPLIT L1 CACHE AND L2 CACHE"] +pub mod level_split0; +#[doc = "L2_CACHE_CTRL (rw) register accessor: L2 Cache(L2-Cache) control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_ctrl`] module"] +pub type L2_CACHE_CTRL = crate::Reg; +#[doc = "L2 Cache(L2-Cache) control register"] +pub mod l2_cache_ctrl; +#[doc = "L2_BYPASS_CACHE_CONF (rw) register accessor: Bypass Cache configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_bypass_cache_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_bypass_cache_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_bypass_cache_conf`] module"] +pub type L2_BYPASS_CACHE_CONF = crate::Reg; +#[doc = "Bypass Cache configure register"] +pub mod l2_bypass_cache_conf; +#[doc = "L2_CACHE_CACHESIZE_CONF (rw) register accessor: L2 Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_cachesize_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_cachesize_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_cachesize_conf`] module"] +pub type L2_CACHE_CACHESIZE_CONF = + crate::Reg; +#[doc = "L2 Cache CacheSize mode configure register"] +pub mod l2_cache_cachesize_conf; +#[doc = "L2_CACHE_BLOCKSIZE_CONF (rw) register accessor: L2 Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_blocksize_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_blocksize_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_blocksize_conf`] module"] +pub type L2_CACHE_BLOCKSIZE_CONF = + crate::Reg; +#[doc = "L2 Cache BlockSize mode configure register"] +pub mod l2_cache_blocksize_conf; +#[doc = "L2_CACHE_WRAP_AROUND_CTRL (rw) register accessor: Cache wrap around control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_wrap_around_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_wrap_around_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_wrap_around_ctrl`] module"] +pub type L2_CACHE_WRAP_AROUND_CTRL = + crate::Reg; +#[doc = "Cache wrap around control register"] +pub mod l2_cache_wrap_around_ctrl; +#[doc = "L2_CACHE_TAG_MEM_POWER_CTRL (rw) register accessor: Cache tag memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_tag_mem_power_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_tag_mem_power_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_tag_mem_power_ctrl`] module"] +pub type L2_CACHE_TAG_MEM_POWER_CTRL = + crate::Reg; +#[doc = "Cache tag memory power control register"] +pub mod l2_cache_tag_mem_power_ctrl; +#[doc = "L2_CACHE_DATA_MEM_POWER_CTRL (rw) register accessor: Cache data memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_data_mem_power_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_data_mem_power_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_data_mem_power_ctrl`] module"] +pub type L2_CACHE_DATA_MEM_POWER_CTRL = + crate::Reg; +#[doc = "Cache data memory power control register"] +pub mod l2_cache_data_mem_power_ctrl; +#[doc = "L2_CACHE_FREEZE_CTRL (rw) register accessor: Cache Freeze control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_freeze_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_freeze_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_freeze_ctrl`] module"] +pub type L2_CACHE_FREEZE_CTRL = crate::Reg; +#[doc = "Cache Freeze control register"] +pub mod l2_cache_freeze_ctrl; +#[doc = "L2_CACHE_DATA_MEM_ACS_CONF (rw) register accessor: Cache data memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_data_mem_acs_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_data_mem_acs_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_data_mem_acs_conf`] module"] +pub type L2_CACHE_DATA_MEM_ACS_CONF = + crate::Reg; +#[doc = "Cache data memory access configure register"] +pub mod l2_cache_data_mem_acs_conf; +#[doc = "L2_CACHE_TAG_MEM_ACS_CONF (rw) register accessor: Cache tag memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_tag_mem_acs_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_tag_mem_acs_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_tag_mem_acs_conf`] module"] +pub type L2_CACHE_TAG_MEM_ACS_CONF = + crate::Reg; +#[doc = "Cache tag memory access configure register"] +pub mod l2_cache_tag_mem_acs_conf; +#[doc = "L2_CACHE_PRELOCK_CONF (rw) register accessor: L2 Cache prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_prelock_conf`] module"] +pub type L2_CACHE_PRELOCK_CONF = crate::Reg; +#[doc = "L2 Cache prelock configure register"] +pub mod l2_cache_prelock_conf; +#[doc = "L2_CACHE_PRELOCK_SCT0_ADDR (rw) register accessor: L2 Cache prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_prelock_sct0_addr`] module"] +pub type L2_CACHE_PRELOCK_SCT0_ADDR = + crate::Reg; +#[doc = "L2 Cache prelock section0 address configure register"] +pub mod l2_cache_prelock_sct0_addr; +#[doc = "L2_CACHE_PRELOCK_SCT1_ADDR (rw) register accessor: L2 Cache prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_prelock_sct1_addr`] module"] +pub type L2_CACHE_PRELOCK_SCT1_ADDR = + crate::Reg; +#[doc = "L2 Cache prelock section1 address configure register"] +pub mod l2_cache_prelock_sct1_addr; +#[doc = "L2_CACHE_PRELOCK_SCT_SIZE (rw) register accessor: L2 Cache prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_sct_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_prelock_sct_size`] module"] +pub type L2_CACHE_PRELOCK_SCT_SIZE = + crate::Reg; +#[doc = "L2 Cache prelock section size configure register"] +pub mod l2_cache_prelock_sct_size; +#[doc = "L2_CACHE_PRELOAD_CTRL (rw) register accessor: L2 Cache preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_preload_ctrl`] module"] +pub type L2_CACHE_PRELOAD_CTRL = crate::Reg; +#[doc = "L2 Cache preload-operation control register"] +pub mod l2_cache_preload_ctrl; +#[doc = "L2_CACHE_PRELOAD_ADDR (rw) register accessor: L2 Cache preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_preload_addr`] module"] +pub type L2_CACHE_PRELOAD_ADDR = crate::Reg; +#[doc = "L2 Cache preload address configure register"] +pub mod l2_cache_preload_addr; +#[doc = "L2_CACHE_PRELOAD_SIZE (rw) register accessor: L2 Cache preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_preload_size`] module"] +pub type L2_CACHE_PRELOAD_SIZE = crate::Reg; +#[doc = "L2 Cache preload size configure register"] +pub mod l2_cache_preload_size; +#[doc = "L2_CACHE_AUTOLOAD_CTRL (rw) register accessor: L2 Cache autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_ctrl`] module"] +pub type L2_CACHE_AUTOLOAD_CTRL = crate::Reg; +#[doc = "L2 Cache autoload-operation control register"] +pub mod l2_cache_autoload_ctrl; +#[doc = "L2_CACHE_AUTOLOAD_SCT0_ADDR (rw) register accessor: L2 Cache autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct0_addr`] module"] +pub type L2_CACHE_AUTOLOAD_SCT0_ADDR = + crate::Reg; +#[doc = "L2 Cache autoload section 0 address configure register"] +pub mod l2_cache_autoload_sct0_addr; +#[doc = "L2_CACHE_AUTOLOAD_SCT0_SIZE (rw) register accessor: L2 Cache autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct0_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct0_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct0_size`] module"] +pub type L2_CACHE_AUTOLOAD_SCT0_SIZE = + crate::Reg; +#[doc = "L2 Cache autoload section 0 size configure register"] +pub mod l2_cache_autoload_sct0_size; +#[doc = "L2_CACHE_AUTOLOAD_SCT1_ADDR (rw) register accessor: L2 Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct1_addr`] module"] +pub type L2_CACHE_AUTOLOAD_SCT1_ADDR = + crate::Reg; +#[doc = "L2 Cache autoload section 1 address configure register"] +pub mod l2_cache_autoload_sct1_addr; +#[doc = "L2_CACHE_AUTOLOAD_SCT1_SIZE (rw) register accessor: L2 Cache autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct1_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct1_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct1_size`] module"] +pub type L2_CACHE_AUTOLOAD_SCT1_SIZE = + crate::Reg; +#[doc = "L2 Cache autoload section 1 size configure register"] +pub mod l2_cache_autoload_sct1_size; +#[doc = "L2_CACHE_AUTOLOAD_SCT2_ADDR (rw) register accessor: L2 Cache autoload section 2 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct2_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct2_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct2_addr`] module"] +pub type L2_CACHE_AUTOLOAD_SCT2_ADDR = + crate::Reg; +#[doc = "L2 Cache autoload section 2 address configure register"] +pub mod l2_cache_autoload_sct2_addr; +#[doc = "L2_CACHE_AUTOLOAD_SCT2_SIZE (rw) register accessor: L2 Cache autoload section 2 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct2_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct2_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct2_size`] module"] +pub type L2_CACHE_AUTOLOAD_SCT2_SIZE = + crate::Reg; +#[doc = "L2 Cache autoload section 2 size configure register"] +pub mod l2_cache_autoload_sct2_size; +#[doc = "L2_CACHE_AUTOLOAD_SCT3_ADDR (rw) register accessor: L2 Cache autoload section 3 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct3_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct3_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct3_addr`] module"] +pub type L2_CACHE_AUTOLOAD_SCT3_ADDR = + crate::Reg; +#[doc = "L2 Cache autoload section 3 address configure register"] +pub mod l2_cache_autoload_sct3_addr; +#[doc = "L2_CACHE_AUTOLOAD_SCT3_SIZE (rw) register accessor: L2 Cache autoload section 3 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct3_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct3_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_sct3_size`] module"] +pub type L2_CACHE_AUTOLOAD_SCT3_SIZE = + crate::Reg; +#[doc = "L2 Cache autoload section 3 size configure register"] +pub mod l2_cache_autoload_sct3_size; +#[doc = "L2_CACHE_ACS_CNT_INT_ENA (rw) register accessor: Cache Access Counter Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_cnt_int_ena`] module"] +pub type L2_CACHE_ACS_CNT_INT_ENA = + crate::Reg; +#[doc = "Cache Access Counter Interrupt enable register"] +pub mod l2_cache_acs_cnt_int_ena; +#[doc = "L2_CACHE_ACS_CNT_INT_CLR (rw) register accessor: Cache Access Counter Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_int_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_cnt_int_clr`] module"] +pub type L2_CACHE_ACS_CNT_INT_CLR = + crate::Reg; +#[doc = "Cache Access Counter Interrupt clear register"] +pub mod l2_cache_acs_cnt_int_clr; +#[doc = "L2_CACHE_ACS_CNT_INT_RAW (rw) register accessor: Cache Access Counter Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_cnt_int_raw`] module"] +pub type L2_CACHE_ACS_CNT_INT_RAW = + crate::Reg; +#[doc = "Cache Access Counter Interrupt raw register"] +pub mod l2_cache_acs_cnt_int_raw; +#[doc = "L2_CACHE_ACS_CNT_INT_ST (r) register accessor: Cache Access Counter Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_cnt_int_st`] module"] +pub type L2_CACHE_ACS_CNT_INT_ST = + crate::Reg; +#[doc = "Cache Access Counter Interrupt status register"] +pub mod l2_cache_acs_cnt_int_st; +#[doc = "L2_CACHE_ACS_FAIL_CTRL (rw) register accessor: Cache Access Fail Configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_ctrl`] module"] +pub type L2_CACHE_ACS_FAIL_CTRL = crate::Reg; +#[doc = "Cache Access Fail Configuration register"] +pub mod l2_cache_acs_fail_ctrl; +#[doc = "L2_CACHE_ACS_FAIL_INT_ENA (rw) register accessor: Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_int_ena`] module"] +pub type L2_CACHE_ACS_FAIL_INT_ENA = + crate::Reg; +#[doc = "Cache Access Fail Interrupt enable register"] +pub mod l2_cache_acs_fail_int_ena; +#[doc = "L2_CACHE_ACS_FAIL_INT_CLR (w) register accessor: L1-Cache Access Fail Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_int_clr`] module"] +pub type L2_CACHE_ACS_FAIL_INT_CLR = + crate::Reg; +#[doc = "L1-Cache Access Fail Interrupt clear register"] +pub mod l2_cache_acs_fail_int_clr; +#[doc = "L2_CACHE_ACS_FAIL_INT_RAW (rw) register accessor: Cache Access Fail Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_int_raw`] module"] +pub type L2_CACHE_ACS_FAIL_INT_RAW = + crate::Reg; +#[doc = "Cache Access Fail Interrupt raw register"] +pub mod l2_cache_acs_fail_int_raw; +#[doc = "L2_CACHE_ACS_FAIL_INT_ST (r) register accessor: Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_int_st`] module"] +pub type L2_CACHE_ACS_FAIL_INT_ST = + crate::Reg; +#[doc = "Cache Access Fail Interrupt status register"] +pub mod l2_cache_acs_fail_int_st; +#[doc = "L2_CACHE_ACS_CNT_CTRL (rw) register accessor: Cache Access Counter enable and clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_cnt_ctrl`] module"] +pub type L2_CACHE_ACS_CNT_CTRL = crate::Reg; +#[doc = "Cache Access Counter enable and clear register"] +pub mod l2_cache_acs_cnt_ctrl; +#[doc = "L2_IBUS0_ACS_HIT_CNT (r) register accessor: L2-Cache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus0_acs_hit_cnt`] module"] +pub type L2_IBUS0_ACS_HIT_CNT = crate::Reg; +#[doc = "L2-Cache bus0 Hit-Access Counter register"] +pub mod l2_ibus0_acs_hit_cnt; +#[doc = "L2_IBUS0_ACS_MISS_CNT (r) register accessor: L2-Cache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus0_acs_miss_cnt`] module"] +pub type L2_IBUS0_ACS_MISS_CNT = crate::Reg; +#[doc = "L2-Cache bus0 Miss-Access Counter register"] +pub mod l2_ibus0_acs_miss_cnt; +#[doc = "L2_IBUS0_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus0_acs_conflict_cnt`] module"] +pub type L2_IBUS0_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L2-Cache bus0 Conflict-Access Counter register"] +pub mod l2_ibus0_acs_conflict_cnt; +#[doc = "L2_IBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus0_acs_nxtlvl_rd_cnt`] module"] +pub type L2_IBUS0_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L2-Cache bus0 Next-Level-Access Counter register"] +pub mod l2_ibus0_acs_nxtlvl_rd_cnt; +#[doc = "L2_IBUS1_ACS_HIT_CNT (r) register accessor: L2-Cache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus1_acs_hit_cnt`] module"] +pub type L2_IBUS1_ACS_HIT_CNT = crate::Reg; +#[doc = "L2-Cache bus1 Hit-Access Counter register"] +pub mod l2_ibus1_acs_hit_cnt; +#[doc = "L2_IBUS1_ACS_MISS_CNT (r) register accessor: L2-Cache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus1_acs_miss_cnt`] module"] +pub type L2_IBUS1_ACS_MISS_CNT = crate::Reg; +#[doc = "L2-Cache bus1 Miss-Access Counter register"] +pub mod l2_ibus1_acs_miss_cnt; +#[doc = "L2_IBUS1_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus1_acs_conflict_cnt`] module"] +pub type L2_IBUS1_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L2-Cache bus1 Conflict-Access Counter register"] +pub mod l2_ibus1_acs_conflict_cnt; +#[doc = "L2_IBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus1_acs_nxtlvl_rd_cnt`] module"] +pub type L2_IBUS1_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L2-Cache bus1 Next-Level-Access Counter register"] +pub mod l2_ibus1_acs_nxtlvl_rd_cnt; +#[doc = "L2_IBUS2_ACS_HIT_CNT (r) register accessor: L2-Cache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus2_acs_hit_cnt`] module"] +pub type L2_IBUS2_ACS_HIT_CNT = crate::Reg; +#[doc = "L2-Cache bus2 Hit-Access Counter register"] +pub mod l2_ibus2_acs_hit_cnt; +#[doc = "L2_IBUS2_ACS_MISS_CNT (r) register accessor: L2-Cache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus2_acs_miss_cnt`] module"] +pub type L2_IBUS2_ACS_MISS_CNT = crate::Reg; +#[doc = "L2-Cache bus2 Miss-Access Counter register"] +pub mod l2_ibus2_acs_miss_cnt; +#[doc = "L2_IBUS2_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus2_acs_conflict_cnt`] module"] +pub type L2_IBUS2_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L2-Cache bus2 Conflict-Access Counter register"] +pub mod l2_ibus2_acs_conflict_cnt; +#[doc = "L2_IBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus2_acs_nxtlvl_rd_cnt`] module"] +pub type L2_IBUS2_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L2-Cache bus2 Next-Level-Access Counter register"] +pub mod l2_ibus2_acs_nxtlvl_rd_cnt; +#[doc = "L2_IBUS3_ACS_HIT_CNT (r) register accessor: L2-Cache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus3_acs_hit_cnt`] module"] +pub type L2_IBUS3_ACS_HIT_CNT = crate::Reg; +#[doc = "L2-Cache bus3 Hit-Access Counter register"] +pub mod l2_ibus3_acs_hit_cnt; +#[doc = "L2_IBUS3_ACS_MISS_CNT (r) register accessor: L2-Cache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus3_acs_miss_cnt`] module"] +pub type L2_IBUS3_ACS_MISS_CNT = crate::Reg; +#[doc = "L2-Cache bus3 Miss-Access Counter register"] +pub mod l2_ibus3_acs_miss_cnt; +#[doc = "L2_IBUS3_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus3_acs_conflict_cnt`] module"] +pub type L2_IBUS3_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L2-Cache bus3 Conflict-Access Counter register"] +pub mod l2_ibus3_acs_conflict_cnt; +#[doc = "L2_IBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_ibus3_acs_nxtlvl_rd_cnt`] module"] +pub type L2_IBUS3_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L2-Cache bus3 Next-Level-Access Counter register"] +pub mod l2_ibus3_acs_nxtlvl_rd_cnt; +#[doc = "L2_DBUS0_ACS_HIT_CNT (r) register accessor: L2-Cache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus0_acs_hit_cnt`] module"] +pub type L2_DBUS0_ACS_HIT_CNT = crate::Reg; +#[doc = "L2-Cache bus0 Hit-Access Counter register"] +pub mod l2_dbus0_acs_hit_cnt; +#[doc = "L2_DBUS0_ACS_MISS_CNT (r) register accessor: L2-Cache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus0_acs_miss_cnt`] module"] +pub type L2_DBUS0_ACS_MISS_CNT = crate::Reg; +#[doc = "L2-Cache bus0 Miss-Access Counter register"] +pub mod l2_dbus0_acs_miss_cnt; +#[doc = "L2_DBUS0_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus0_acs_conflict_cnt`] module"] +pub type L2_DBUS0_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L2-Cache bus0 Conflict-Access Counter register"] +pub mod l2_dbus0_acs_conflict_cnt; +#[doc = "L2_DBUS0_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus0_acs_nxtlvl_rd_cnt`] module"] +pub type L2_DBUS0_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L2-Cache bus0 Next-Level-Access Counter register"] +pub mod l2_dbus0_acs_nxtlvl_rd_cnt; +#[doc = "L2_DBUS0_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus0 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus0_acs_nxtlvl_wr_cnt`] module"] +pub type L2_DBUS0_ACS_NXTLVL_WR_CNT = + crate::Reg; +#[doc = "L2-Cache bus0 WB-Access Counter register"] +pub mod l2_dbus0_acs_nxtlvl_wr_cnt; +#[doc = "L2_DBUS1_ACS_HIT_CNT (r) register accessor: L2-Cache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus1_acs_hit_cnt`] module"] +pub type L2_DBUS1_ACS_HIT_CNT = crate::Reg; +#[doc = "L2-Cache bus1 Hit-Access Counter register"] +pub mod l2_dbus1_acs_hit_cnt; +#[doc = "L2_DBUS1_ACS_MISS_CNT (r) register accessor: L2-Cache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus1_acs_miss_cnt`] module"] +pub type L2_DBUS1_ACS_MISS_CNT = crate::Reg; +#[doc = "L2-Cache bus1 Miss-Access Counter register"] +pub mod l2_dbus1_acs_miss_cnt; +#[doc = "L2_DBUS1_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus1_acs_conflict_cnt`] module"] +pub type L2_DBUS1_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L2-Cache bus1 Conflict-Access Counter register"] +pub mod l2_dbus1_acs_conflict_cnt; +#[doc = "L2_DBUS1_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus1_acs_nxtlvl_rd_cnt`] module"] +pub type L2_DBUS1_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L2-Cache bus1 Next-Level-Access Counter register"] +pub mod l2_dbus1_acs_nxtlvl_rd_cnt; +#[doc = "L2_DBUS1_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus1 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus1_acs_nxtlvl_wr_cnt`] module"] +pub type L2_DBUS1_ACS_NXTLVL_WR_CNT = + crate::Reg; +#[doc = "L2-Cache bus1 WB-Access Counter register"] +pub mod l2_dbus1_acs_nxtlvl_wr_cnt; +#[doc = "L2_DBUS2_ACS_HIT_CNT (r) register accessor: L2-Cache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus2_acs_hit_cnt`] module"] +pub type L2_DBUS2_ACS_HIT_CNT = crate::Reg; +#[doc = "L2-Cache bus2 Hit-Access Counter register"] +pub mod l2_dbus2_acs_hit_cnt; +#[doc = "L2_DBUS2_ACS_MISS_CNT (r) register accessor: L2-Cache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus2_acs_miss_cnt`] module"] +pub type L2_DBUS2_ACS_MISS_CNT = crate::Reg; +#[doc = "L2-Cache bus2 Miss-Access Counter register"] +pub mod l2_dbus2_acs_miss_cnt; +#[doc = "L2_DBUS2_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus2_acs_conflict_cnt`] module"] +pub type L2_DBUS2_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L2-Cache bus2 Conflict-Access Counter register"] +pub mod l2_dbus2_acs_conflict_cnt; +#[doc = "L2_DBUS2_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus2_acs_nxtlvl_rd_cnt`] module"] +pub type L2_DBUS2_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L2-Cache bus2 Next-Level-Access Counter register"] +pub mod l2_dbus2_acs_nxtlvl_rd_cnt; +#[doc = "L2_DBUS2_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus2 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus2_acs_nxtlvl_wr_cnt`] module"] +pub type L2_DBUS2_ACS_NXTLVL_WR_CNT = + crate::Reg; +#[doc = "L2-Cache bus2 WB-Access Counter register"] +pub mod l2_dbus2_acs_nxtlvl_wr_cnt; +#[doc = "L2_DBUS3_ACS_HIT_CNT (r) register accessor: L2-Cache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_hit_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus3_acs_hit_cnt`] module"] +pub type L2_DBUS3_ACS_HIT_CNT = crate::Reg; +#[doc = "L2-Cache bus3 Hit-Access Counter register"] +pub mod l2_dbus3_acs_hit_cnt; +#[doc = "L2_DBUS3_ACS_MISS_CNT (r) register accessor: L2-Cache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_miss_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus3_acs_miss_cnt`] module"] +pub type L2_DBUS3_ACS_MISS_CNT = crate::Reg; +#[doc = "L2-Cache bus3 Miss-Access Counter register"] +pub mod l2_dbus3_acs_miss_cnt; +#[doc = "L2_DBUS3_ACS_CONFLICT_CNT (r) register accessor: L2-Cache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_conflict_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus3_acs_conflict_cnt`] module"] +pub type L2_DBUS3_ACS_CONFLICT_CNT = + crate::Reg; +#[doc = "L2-Cache bus3 Conflict-Access Counter register"] +pub mod l2_dbus3_acs_conflict_cnt; +#[doc = "L2_DBUS3_ACS_NXTLVL_RD_CNT (r) register accessor: L2-Cache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_nxtlvl_rd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus3_acs_nxtlvl_rd_cnt`] module"] +pub type L2_DBUS3_ACS_NXTLVL_RD_CNT = + crate::Reg; +#[doc = "L2-Cache bus3 Next-Level-Access Counter register"] +pub mod l2_dbus3_acs_nxtlvl_rd_cnt; +#[doc = "L2_DBUS3_ACS_NXTLVL_WR_CNT (r) register accessor: L2-Cache bus3 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_nxtlvl_wr_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_dbus3_acs_nxtlvl_wr_cnt`] module"] +pub type L2_DBUS3_ACS_NXTLVL_WR_CNT = + crate::Reg; +#[doc = "L2-Cache bus3 WB-Access Counter register"] +pub mod l2_dbus3_acs_nxtlvl_wr_cnt; +#[doc = "L2_CACHE_ACS_FAIL_ID_ATTR (r) register accessor: L2-Cache Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_id_attr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_id_attr`] module"] +pub type L2_CACHE_ACS_FAIL_ID_ATTR = + crate::Reg; +#[doc = "L2-Cache Access Fail ID/attribution information register"] +pub mod l2_cache_acs_fail_id_attr; +#[doc = "L2_CACHE_ACS_FAIL_ADDR (r) register accessor: L2-Cache Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_acs_fail_addr`] module"] +pub type L2_CACHE_ACS_FAIL_ADDR = crate::Reg; +#[doc = "L2-Cache Access Fail Address information register"] +pub mod l2_cache_acs_fail_addr; +#[doc = "L2_CACHE_SYNC_PRELOAD_INT_ENA (rw) register accessor: L1-Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_preload_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_preload_int_ena`] module"] +pub type L2_CACHE_SYNC_PRELOAD_INT_ENA = + crate::Reg; +#[doc = "L1-Cache Access Fail Interrupt enable register"] +pub mod l2_cache_sync_preload_int_ena; +#[doc = "L2_CACHE_SYNC_PRELOAD_INT_CLR (w) register accessor: Sync Preload operation Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_preload_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_preload_int_clr`] module"] +pub type L2_CACHE_SYNC_PRELOAD_INT_CLR = + crate::Reg; +#[doc = "Sync Preload operation Interrupt clear register"] +pub mod l2_cache_sync_preload_int_clr; +#[doc = "L2_CACHE_SYNC_PRELOAD_INT_RAW (rw) register accessor: Sync Preload operation Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_preload_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_preload_int_raw`] module"] +pub type L2_CACHE_SYNC_PRELOAD_INT_RAW = + crate::Reg; +#[doc = "Sync Preload operation Interrupt raw register"] +pub mod l2_cache_sync_preload_int_raw; +#[doc = "L2_CACHE_SYNC_PRELOAD_INT_ST (r) register accessor: L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_preload_int_st`] module"] +pub type L2_CACHE_SYNC_PRELOAD_INT_ST = + crate::Reg; +#[doc = "L1-Cache Access Fail Interrupt status register"] +pub mod l2_cache_sync_preload_int_st; +#[doc = "L2_CACHE_SYNC_PRELOAD_EXCEPTION (r) register accessor: Cache Sync/Preload Operation exception register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_exception::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_preload_exception`] module"] +pub type L2_CACHE_SYNC_PRELOAD_EXCEPTION = + crate::Reg; +#[doc = "Cache Sync/Preload Operation exception register"] +pub mod l2_cache_sync_preload_exception; +#[doc = "L2_CACHE_SYNC_RST_CTRL (rw) register accessor: Cache Sync Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_rst_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_rst_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_sync_rst_ctrl`] module"] +pub type L2_CACHE_SYNC_RST_CTRL = crate::Reg; +#[doc = "Cache Sync Reset control register"] +pub mod l2_cache_sync_rst_ctrl; +#[doc = "L2_CACHE_PRELOAD_RST_CTRL (rw) register accessor: Cache Preload Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_rst_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_rst_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_preload_rst_ctrl`] module"] +pub type L2_CACHE_PRELOAD_RST_CTRL = + crate::Reg; +#[doc = "Cache Preload Reset control register"] +pub mod l2_cache_preload_rst_ctrl; +#[doc = "L2_CACHE_AUTOLOAD_BUF_CLR_CTRL (rw) register accessor: Cache Autoload buffer clear control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_buf_clr_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_buf_clr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_autoload_buf_clr_ctrl`] module"] +pub type L2_CACHE_AUTOLOAD_BUF_CLR_CTRL = + crate::Reg; +#[doc = "Cache Autoload buffer clear control register"] +pub mod l2_cache_autoload_buf_clr_ctrl; +#[doc = "L2_UNALLOCATE_BUFFER_CLEAR (rw) register accessor: Unallocate request buffer clear registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_unallocate_buffer_clear::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_unallocate_buffer_clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_unallocate_buffer_clear`] module"] +pub type L2_UNALLOCATE_BUFFER_CLEAR = + crate::Reg; +#[doc = "Unallocate request buffer clear registers"] +pub mod l2_unallocate_buffer_clear; +#[doc = "L2_CACHE_ACCESS_ATTR_CTRL (rw) register accessor: L2 cache access attribute control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_access_attr_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_access_attr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_access_attr_ctrl`] module"] +pub type L2_CACHE_ACCESS_ATTR_CTRL = + crate::Reg; +#[doc = "L2 cache access attribute control register"] +pub mod l2_cache_access_attr_ctrl; +#[doc = "L2_CACHE_OBJECT_CTRL (rw) register accessor: Cache Tag and Data memory Object control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_object_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_object_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_object_ctrl`] module"] +pub type L2_CACHE_OBJECT_CTRL = crate::Reg; +#[doc = "Cache Tag and Data memory Object control register"] +pub mod l2_cache_object_ctrl; +#[doc = "L2_CACHE_WAY_OBJECT (rw) register accessor: Cache Tag and Data memory way register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_way_object::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_way_object::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_way_object`] module"] +pub type L2_CACHE_WAY_OBJECT = crate::Reg; +#[doc = "Cache Tag and Data memory way register"] +pub mod l2_cache_way_object; +#[doc = "L2_CACHE_VADDR (rw) register accessor: Cache Vaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_vaddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_vaddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_vaddr`] module"] +pub type L2_CACHE_VADDR = crate::Reg; +#[doc = "Cache Vaddr register"] +pub mod l2_cache_vaddr; +#[doc = "L2_CACHE_DEBUG_BUS (rw) register accessor: Cache Tag/data memory content register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_debug_bus::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_debug_bus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@l2_cache_debug_bus`] module"] +pub type L2_CACHE_DEBUG_BUS = crate::Reg; +#[doc = "Cache Tag/data memory content register"] +pub mod l2_cache_debug_bus; +#[doc = "LEVEL_SPLIT1 (r) register accessor: USED TO SPLIT L1 CACHE AND L2 CACHE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`level_split1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@level_split1`] module"] +pub type LEVEL_SPLIT1 = crate::Reg; +#[doc = "USED TO SPLIT L1 CACHE AND L2 CACHE"] +pub mod level_split1; +#[doc = "CLOCK_GATE (rw) register accessor: Clock gate control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"] +pub type CLOCK_GATE = crate::Reg; +#[doc = "Clock gate control register"] +pub mod clock_gate; +#[doc = "REDUNDANCY_SIG0 (rw) register accessor: Cache redundancy signal 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redundancy_sig0`] module"] +pub type REDUNDANCY_SIG0 = crate::Reg; +#[doc = "Cache redundancy signal 0 register"] +pub mod redundancy_sig0; +#[doc = "REDUNDANCY_SIG1 (rw) register accessor: Cache redundancy signal 1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redundancy_sig1`] module"] +pub type REDUNDANCY_SIG1 = crate::Reg; +#[doc = "Cache redundancy signal 1 register"] +pub mod redundancy_sig1; +#[doc = "REDUNDANCY_SIG2 (rw) register accessor: Cache redundancy signal 2 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redundancy_sig2`] module"] +pub type REDUNDANCY_SIG2 = crate::Reg; +#[doc = "Cache redundancy signal 2 register"] +pub mod redundancy_sig2; +#[doc = "REDUNDANCY_SIG3 (rw) register accessor: Cache redundancy signal 3 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redundancy_sig3`] module"] +pub type REDUNDANCY_SIG3 = crate::Reg; +#[doc = "Cache redundancy signal 3 register"] +pub mod redundancy_sig3; +#[doc = "REDUNDANCY_SIG4 (r) register accessor: Cache redundancy signal 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redundancy_sig4`] module"] +pub type REDUNDANCY_SIG4 = crate::Reg; +#[doc = "Cache redundancy signal 0 register"] +pub mod redundancy_sig4; +#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version control register"] +pub mod date; diff --git a/esp32p4/src/cache/clock_gate.rs b/esp32p4/src/cache/clock_gate.rs new file mode 100644 index 0000000000..10334899eb --- /dev/null +++ b/esp32p4/src/cache/clock_gate.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLOCK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `CLOCK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - The bit is used to enable clock gate when access all registers in this module."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - The bit is used to enable clock gate when access all registers in this module."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to enable clock gate when access all registers in this module."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCK_GATE") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable clock gate when access all registers in this module."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock gate control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLOCK_GATE_SPEC; +impl crate::RegisterSpec for CLOCK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"] +impl crate::Readable for CLOCK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"] +impl crate::Writable for CLOCK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"] +impl crate::Resettable for CLOCK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/cache/date.rs b/esp32p4/src/cache/date.rs new file mode 100644 index 0000000000..4d7470b3ab --- /dev/null +++ b/esp32p4/src/cache/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - version control register. Note that this default value stored is the latest date when the hardware logic was updated."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - version control register. Note that this default value stored is the latest date when the hardware logic was updated."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - version control register. Note that this default value stored is the latest date when the hardware logic was updated."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - version control register. Note that this default value stored is the latest date when the hardware logic was updated."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_4130"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_4130; +} diff --git a/esp32p4/src/cache/l1_bypass_cache_conf.rs b/esp32p4/src/cache/l1_bypass_cache_conf.rs new file mode 100644 index 0000000000..03eb719599 --- /dev/null +++ b/esp32p4/src/cache/l1_bypass_cache_conf.rs @@ -0,0 +1,126 @@ +#[doc = "Register `L1_BYPASS_CACHE_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L1_BYPASS_CACHE_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `BYPASS_L1_ICACHE0_EN` reader - The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass."] +pub type BYPASS_L1_ICACHE0_EN_R = crate::BitReader; +#[doc = "Field `BYPASS_L1_ICACHE0_EN` writer - The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass."] +pub type BYPASS_L1_ICACHE0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BYPASS_L1_ICACHE1_EN` reader - The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass."] +pub type BYPASS_L1_ICACHE1_EN_R = crate::BitReader; +#[doc = "Field `BYPASS_L1_ICACHE1_EN` writer - The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass."] +pub type BYPASS_L1_ICACHE1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BYPASS_L1_ICACHE2_EN` reader - Reserved"] +pub type BYPASS_L1_ICACHE2_EN_R = crate::BitReader; +#[doc = "Field `BYPASS_L1_ICACHE3_EN` reader - Reserved"] +pub type BYPASS_L1_ICACHE3_EN_R = crate::BitReader; +#[doc = "Field `BYPASS_L1_DCACHE_EN` reader - The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass."] +pub type BYPASS_L1_DCACHE_EN_R = crate::BitReader; +#[doc = "Field `BYPASS_L1_DCACHE_EN` writer - The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass."] +pub type BYPASS_L1_DCACHE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass."] + #[inline(always)] + pub fn bypass_l1_icache0_en(&self) -> BYPASS_L1_ICACHE0_EN_R { + BYPASS_L1_ICACHE0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass."] + #[inline(always)] + pub fn bypass_l1_icache1_en(&self) -> BYPASS_L1_ICACHE1_EN_R { + BYPASS_L1_ICACHE1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn bypass_l1_icache2_en(&self) -> BYPASS_L1_ICACHE2_EN_R { + BYPASS_L1_ICACHE2_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn bypass_l1_icache3_en(&self) -> BYPASS_L1_ICACHE3_EN_R { + BYPASS_L1_ICACHE3_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass."] + #[inline(always)] + pub fn bypass_l1_dcache_en(&self) -> BYPASS_L1_DCACHE_EN_R { + BYPASS_L1_DCACHE_EN_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_BYPASS_CACHE_CONF") + .field( + "bypass_l1_icache0_en", + &format_args!("{}", self.bypass_l1_icache0_en().bit()), + ) + .field( + "bypass_l1_icache1_en", + &format_args!("{}", self.bypass_l1_icache1_en().bit()), + ) + .field( + "bypass_l1_icache2_en", + &format_args!("{}", self.bypass_l1_icache2_en().bit()), + ) + .field( + "bypass_l1_icache3_en", + &format_args!("{}", self.bypass_l1_icache3_en().bit()), + ) + .field( + "bypass_l1_dcache_en", + &format_args!("{}", self.bypass_l1_dcache_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass."] + #[inline(always)] + #[must_use] + pub fn bypass_l1_icache0_en(&mut self) -> BYPASS_L1_ICACHE0_EN_W { + BYPASS_L1_ICACHE0_EN_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass."] + #[inline(always)] + #[must_use] + pub fn bypass_l1_icache1_en(&mut self) -> BYPASS_L1_ICACHE1_EN_W { + BYPASS_L1_ICACHE1_EN_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass."] + #[inline(always)] + #[must_use] + pub fn bypass_l1_dcache_en(&mut self) -> BYPASS_L1_DCACHE_EN_W { + BYPASS_L1_DCACHE_EN_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Bypass Cache configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bypass_cache_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_bypass_cache_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_BYPASS_CACHE_CONF_SPEC; +impl crate::RegisterSpec for L1_BYPASS_CACHE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_bypass_cache_conf::R`](R) reader structure"] +impl crate::Readable for L1_BYPASS_CACHE_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_bypass_cache_conf::W`](W) writer structure"] +impl crate::Writable for L1_BYPASS_CACHE_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_BYPASS_CACHE_CONF to value 0"] +impl crate::Resettable for L1_BYPASS_CACHE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_acs_cnt_ctrl.rs b/esp32p4/src/cache/l1_cache_acs_cnt_ctrl.rs new file mode 100644 index 0000000000..79b0fe1243 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_acs_cnt_ctrl.rs @@ -0,0 +1,243 @@ +#[doc = "Register `L1_CACHE_ACS_CNT_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_ACS_CNT_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_IBUS0_CNT_ENA` reader - The bit is used to enable ibus0 counter in L1-ICache0."] +pub type L1_IBUS0_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L1_IBUS0_CNT_ENA` writer - The bit is used to enable ibus0 counter in L1-ICache0."] +pub type L1_IBUS0_CNT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_IBUS1_CNT_ENA` reader - The bit is used to enable ibus1 counter in L1-ICache1."] +pub type L1_IBUS1_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L1_IBUS1_CNT_ENA` writer - The bit is used to enable ibus1 counter in L1-ICache1."] +pub type L1_IBUS1_CNT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_IBUS2_CNT_ENA` reader - Reserved"] +pub type L1_IBUS2_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L1_IBUS3_CNT_ENA` reader - Reserved"] +pub type L1_IBUS3_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DBUS0_CNT_ENA` reader - The bit is used to enable dbus0 counter in L1-DCache."] +pub type L1_DBUS0_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DBUS0_CNT_ENA` writer - The bit is used to enable dbus0 counter in L1-DCache."] +pub type L1_DBUS0_CNT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS1_CNT_ENA` reader - The bit is used to enable dbus1 counter in L1-DCache."] +pub type L1_DBUS1_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DBUS1_CNT_ENA` writer - The bit is used to enable dbus1 counter in L1-DCache."] +pub type L1_DBUS1_CNT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS2_CNT_ENA` reader - Reserved"] +pub type L1_DBUS2_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DBUS3_CNT_ENA` reader - Reserved"] +pub type L1_DBUS3_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L1_IBUS0_CNT_CLR` writer - The bit is used to clear ibus0 counter in L1-ICache0."] +pub type L1_IBUS0_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_IBUS1_CNT_CLR` writer - The bit is used to clear ibus1 counter in L1-ICache1."] +pub type L1_IBUS1_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_IBUS2_CNT_CLR` reader - Reserved"] +pub type L1_IBUS2_CNT_CLR_R = crate::BitReader; +#[doc = "Field `L1_IBUS3_CNT_CLR` reader - Reserved"] +pub type L1_IBUS3_CNT_CLR_R = crate::BitReader; +#[doc = "Field `L1_DBUS0_CNT_CLR` writer - The bit is used to clear dbus0 counter in L1-DCache."] +pub type L1_DBUS0_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS1_CNT_CLR` writer - The bit is used to clear dbus1 counter in L1-DCache."] +pub type L1_DBUS1_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS2_CNT_CLR` reader - Reserved"] +pub type L1_DBUS2_CNT_CLR_R = crate::BitReader; +#[doc = "Field `L1_DBUS3_CNT_CLR` reader - Reserved"] +pub type L1_DBUS3_CNT_CLR_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The bit is used to enable ibus0 counter in L1-ICache0."] + #[inline(always)] + pub fn l1_ibus0_cnt_ena(&self) -> L1_IBUS0_CNT_ENA_R { + L1_IBUS0_CNT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable ibus1 counter in L1-ICache1."] + #[inline(always)] + pub fn l1_ibus1_cnt_ena(&self) -> L1_IBUS1_CNT_ENA_R { + L1_IBUS1_CNT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_ibus2_cnt_ena(&self) -> L1_IBUS2_CNT_ENA_R { + L1_IBUS2_CNT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_ibus3_cnt_ena(&self) -> L1_IBUS3_CNT_ENA_R { + L1_IBUS3_CNT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to enable dbus0 counter in L1-DCache."] + #[inline(always)] + pub fn l1_dbus0_cnt_ena(&self) -> L1_DBUS0_CNT_ENA_R { + L1_DBUS0_CNT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The bit is used to enable dbus1 counter in L1-DCache."] + #[inline(always)] + pub fn l1_dbus1_cnt_ena(&self) -> L1_DBUS1_CNT_ENA_R { + L1_DBUS1_CNT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn l1_dbus2_cnt_ena(&self) -> L1_DBUS2_CNT_ENA_R { + L1_DBUS2_CNT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn l1_dbus3_cnt_ena(&self) -> L1_DBUS3_CNT_ENA_R { + L1_DBUS3_CNT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn l1_ibus2_cnt_clr(&self) -> L1_IBUS2_CNT_CLR_R { + L1_IBUS2_CNT_CLR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn l1_ibus3_cnt_clr(&self) -> L1_IBUS3_CNT_CLR_R { + L1_IBUS3_CNT_CLR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn l1_dbus2_cnt_clr(&self) -> L1_DBUS2_CNT_CLR_R { + L1_DBUS2_CNT_CLR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + pub fn l1_dbus3_cnt_clr(&self) -> L1_DBUS3_CNT_CLR_R { + L1_DBUS3_CNT_CLR_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_ACS_CNT_CTRL") + .field( + "l1_ibus0_cnt_ena", + &format_args!("{}", self.l1_ibus0_cnt_ena().bit()), + ) + .field( + "l1_ibus1_cnt_ena", + &format_args!("{}", self.l1_ibus1_cnt_ena().bit()), + ) + .field( + "l1_ibus2_cnt_ena", + &format_args!("{}", self.l1_ibus2_cnt_ena().bit()), + ) + .field( + "l1_ibus3_cnt_ena", + &format_args!("{}", self.l1_ibus3_cnt_ena().bit()), + ) + .field( + "l1_dbus0_cnt_ena", + &format_args!("{}", self.l1_dbus0_cnt_ena().bit()), + ) + .field( + "l1_dbus1_cnt_ena", + &format_args!("{}", self.l1_dbus1_cnt_ena().bit()), + ) + .field( + "l1_dbus2_cnt_ena", + &format_args!("{}", self.l1_dbus2_cnt_ena().bit()), + ) + .field( + "l1_dbus3_cnt_ena", + &format_args!("{}", self.l1_dbus3_cnt_ena().bit()), + ) + .field( + "l1_ibus2_cnt_clr", + &format_args!("{}", self.l1_ibus2_cnt_clr().bit()), + ) + .field( + "l1_ibus3_cnt_clr", + &format_args!("{}", self.l1_ibus3_cnt_clr().bit()), + ) + .field( + "l1_dbus2_cnt_clr", + &format_args!("{}", self.l1_dbus2_cnt_clr().bit()), + ) + .field( + "l1_dbus3_cnt_clr", + &format_args!("{}", self.l1_dbus3_cnt_clr().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable ibus0 counter in L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_ibus0_cnt_ena(&mut self) -> L1_IBUS0_CNT_ENA_W { + L1_IBUS0_CNT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable ibus1 counter in L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_ibus1_cnt_ena(&mut self) -> L1_IBUS1_CNT_ENA_W { + L1_IBUS1_CNT_ENA_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to enable dbus0 counter in L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus0_cnt_ena(&mut self) -> L1_DBUS0_CNT_ENA_W { + L1_DBUS0_CNT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The bit is used to enable dbus1 counter in L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus1_cnt_ena(&mut self) -> L1_DBUS1_CNT_ENA_W { + L1_DBUS1_CNT_ENA_W::new(self, 5) + } + #[doc = "Bit 16 - The bit is used to clear ibus0 counter in L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_ibus0_cnt_clr(&mut self) -> L1_IBUS0_CNT_CLR_W { + L1_IBUS0_CNT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - The bit is used to clear ibus1 counter in L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_ibus1_cnt_clr(&mut self) -> L1_IBUS1_CNT_CLR_W { + L1_IBUS1_CNT_CLR_W::new(self, 17) + } + #[doc = "Bit 20 - The bit is used to clear dbus0 counter in L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus0_cnt_clr(&mut self) -> L1_DBUS0_CNT_CLR_W { + L1_DBUS0_CNT_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - The bit is used to clear dbus1 counter in L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus1_cnt_clr(&mut self) -> L1_DBUS1_CNT_CLR_W { + L1_DBUS1_CNT_CLR_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Counter enable and clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_ACS_CNT_CTRL_SPEC; +impl crate::RegisterSpec for L1_CACHE_ACS_CNT_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_acs_cnt_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_ACS_CNT_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_cnt_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_ACS_CNT_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_ACS_CNT_CTRL to value 0"] +impl crate::Resettable for L1_CACHE_ACS_CNT_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_acs_cnt_int_clr.rs b/esp32p4/src/cache/l1_cache_acs_cnt_int_clr.rs new file mode 100644 index 0000000000..ceeb6055d4 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_acs_cnt_int_clr.rs @@ -0,0 +1,131 @@ +#[doc = "Register `L1_CACHE_ACS_CNT_INT_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_ACS_CNT_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_IBUS0_OVF_INT_CLR` writer - The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0."] +pub type L1_IBUS0_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_IBUS1_OVF_INT_CLR` writer - The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1."] +pub type L1_IBUS1_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_IBUS2_OVF_INT_CLR` reader - Reserved"] +pub type L1_IBUS2_OVF_INT_CLR_R = crate::BitReader; +#[doc = "Field `L1_IBUS3_OVF_INT_CLR` reader - Reserved"] +pub type L1_IBUS3_OVF_INT_CLR_R = crate::BitReader; +#[doc = "Field `L1_DBUS0_OVF_INT_CLR` writer - The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache."] +pub type L1_DBUS0_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS1_OVF_INT_CLR` writer - The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache."] +pub type L1_DBUS1_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS2_OVF_INT_CLR` reader - Reserved"] +pub type L1_DBUS2_OVF_INT_CLR_R = crate::BitReader; +#[doc = "Field `L1_DBUS3_OVF_INT_CLR` reader - Reserved"] +pub type L1_DBUS3_OVF_INT_CLR_R = crate::BitReader; +impl R { + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_ibus2_ovf_int_clr(&self) -> L1_IBUS2_OVF_INT_CLR_R { + L1_IBUS2_OVF_INT_CLR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_ibus3_ovf_int_clr(&self) -> L1_IBUS3_OVF_INT_CLR_R { + L1_IBUS3_OVF_INT_CLR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn l1_dbus2_ovf_int_clr(&self) -> L1_DBUS2_OVF_INT_CLR_R { + L1_DBUS2_OVF_INT_CLR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn l1_dbus3_ovf_int_clr(&self) -> L1_DBUS3_OVF_INT_CLR_R { + L1_DBUS3_OVF_INT_CLR_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_ACS_CNT_INT_CLR") + .field( + "l1_ibus2_ovf_int_clr", + &format_args!("{}", self.l1_ibus2_ovf_int_clr().bit()), + ) + .field( + "l1_ibus3_ovf_int_clr", + &format_args!("{}", self.l1_ibus3_ovf_int_clr().bit()), + ) + .field( + "l1_dbus2_ovf_int_clr", + &format_args!("{}", self.l1_dbus2_ovf_int_clr().bit()), + ) + .field( + "l1_dbus3_ovf_int_clr", + &format_args!("{}", self.l1_dbus3_ovf_int_clr().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_ibus0_ovf_int_clr( + &mut self, + ) -> L1_IBUS0_OVF_INT_CLR_W { + L1_IBUS0_OVF_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_ibus1_ovf_int_clr( + &mut self, + ) -> L1_IBUS1_OVF_INT_CLR_W { + L1_IBUS1_OVF_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus0_ovf_int_clr( + &mut self, + ) -> L1_DBUS0_OVF_INT_CLR_W { + L1_DBUS0_OVF_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus1_ovf_int_clr( + &mut self, + ) -> L1_DBUS1_OVF_INT_CLR_W { + L1_DBUS1_OVF_INT_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Counter Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_int_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_ACS_CNT_INT_CLR_SPEC; +impl crate::RegisterSpec for L1_CACHE_ACS_CNT_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_acs_cnt_int_clr::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_ACS_CNT_INT_CLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_cnt_int_clr::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_ACS_CNT_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_ACS_CNT_INT_CLR to value 0"] +impl crate::Resettable for L1_CACHE_ACS_CNT_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_acs_cnt_int_ena.rs b/esp32p4/src/cache/l1_cache_acs_cnt_int_ena.rs new file mode 100644 index 0000000000..78390c8d03 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_acs_cnt_int_ena.rs @@ -0,0 +1,175 @@ +#[doc = "Register `L1_CACHE_ACS_CNT_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_ACS_CNT_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `L1_IBUS0_OVF_INT_ENA` reader - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."] +pub type L1_IBUS0_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_IBUS0_OVF_INT_ENA` writer - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."] +pub type L1_IBUS0_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_IBUS1_OVF_INT_ENA` reader - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1."] +pub type L1_IBUS1_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_IBUS1_OVF_INT_ENA` writer - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1."] +pub type L1_IBUS1_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_IBUS2_OVF_INT_ENA` reader - Reserved"] +pub type L1_IBUS2_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_IBUS3_OVF_INT_ENA` reader - Reserved"] +pub type L1_IBUS3_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DBUS0_OVF_INT_ENA` reader - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache."] +pub type L1_DBUS0_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DBUS0_OVF_INT_ENA` writer - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache."] +pub type L1_DBUS0_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS1_OVF_INT_ENA` reader - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache."] +pub type L1_DBUS1_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DBUS1_OVF_INT_ENA` writer - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache."] +pub type L1_DBUS1_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS2_OVF_INT_ENA` reader - Reserved"] +pub type L1_DBUS2_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DBUS3_OVF_INT_ENA` reader - Reserved"] +pub type L1_DBUS3_OVF_INT_ENA_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."] + #[inline(always)] + pub fn l1_ibus0_ovf_int_ena(&self) -> L1_IBUS0_OVF_INT_ENA_R { + L1_IBUS0_OVF_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1."] + #[inline(always)] + pub fn l1_ibus1_ovf_int_ena(&self) -> L1_IBUS1_OVF_INT_ENA_R { + L1_IBUS1_OVF_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_ibus2_ovf_int_ena(&self) -> L1_IBUS2_OVF_INT_ENA_R { + L1_IBUS2_OVF_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_ibus3_ovf_int_ena(&self) -> L1_IBUS3_OVF_INT_ENA_R { + L1_IBUS3_OVF_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus0_ovf_int_ena(&self) -> L1_DBUS0_OVF_INT_ENA_R { + L1_DBUS0_OVF_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus1_ovf_int_ena(&self) -> L1_DBUS1_OVF_INT_ENA_R { + L1_DBUS1_OVF_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn l1_dbus2_ovf_int_ena(&self) -> L1_DBUS2_OVF_INT_ENA_R { + L1_DBUS2_OVF_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn l1_dbus3_ovf_int_ena(&self) -> L1_DBUS3_OVF_INT_ENA_R { + L1_DBUS3_OVF_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_ACS_CNT_INT_ENA") + .field( + "l1_ibus0_ovf_int_ena", + &format_args!("{}", self.l1_ibus0_ovf_int_ena().bit()), + ) + .field( + "l1_ibus1_ovf_int_ena", + &format_args!("{}", self.l1_ibus1_ovf_int_ena().bit()), + ) + .field( + "l1_ibus2_ovf_int_ena", + &format_args!("{}", self.l1_ibus2_ovf_int_ena().bit()), + ) + .field( + "l1_ibus3_ovf_int_ena", + &format_args!("{}", self.l1_ibus3_ovf_int_ena().bit()), + ) + .field( + "l1_dbus0_ovf_int_ena", + &format_args!("{}", self.l1_dbus0_ovf_int_ena().bit()), + ) + .field( + "l1_dbus1_ovf_int_ena", + &format_args!("{}", self.l1_dbus1_ovf_int_ena().bit()), + ) + .field( + "l1_dbus2_ovf_int_ena", + &format_args!("{}", self.l1_dbus2_ovf_int_ena().bit()), + ) + .field( + "l1_dbus3_ovf_int_ena", + &format_args!("{}", self.l1_dbus3_ovf_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_ibus0_ovf_int_ena( + &mut self, + ) -> L1_IBUS0_OVF_INT_ENA_W { + L1_IBUS0_OVF_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_ibus1_ovf_int_ena( + &mut self, + ) -> L1_IBUS1_OVF_INT_ENA_W { + L1_IBUS1_OVF_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus0_ovf_int_ena( + &mut self, + ) -> L1_DBUS0_OVF_INT_ENA_W { + L1_DBUS0_OVF_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus1_ovf_int_ena( + &mut self, + ) -> L1_DBUS1_OVF_INT_ENA_W { + L1_DBUS1_OVF_INT_ENA_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Counter Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_ACS_CNT_INT_ENA_SPEC; +impl crate::RegisterSpec for L1_CACHE_ACS_CNT_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_acs_cnt_int_ena::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_ACS_CNT_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_cnt_int_ena::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_ACS_CNT_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_ACS_CNT_INT_ENA to value 0"] +impl crate::Resettable for L1_CACHE_ACS_CNT_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_acs_cnt_int_raw.rs b/esp32p4/src/cache/l1_cache_acs_cnt_int_raw.rs new file mode 100644 index 0000000000..79e14a8ac6 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_acs_cnt_int_raw.rs @@ -0,0 +1,215 @@ +#[doc = "Register `L1_CACHE_ACS_CNT_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_ACS_CNT_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `L1_IBUS0_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."] +pub type L1_IBUS0_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_IBUS0_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."] +pub type L1_IBUS0_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_IBUS1_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1."] +pub type L1_IBUS1_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_IBUS1_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1."] +pub type L1_IBUS1_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_IBUS2_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2."] +pub type L1_IBUS2_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_IBUS2_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2."] +pub type L1_IBUS2_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_IBUS3_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3."] +pub type L1_IBUS3_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_IBUS3_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3."] +pub type L1_IBUS3_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS0_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache."] +pub type L1_DBUS0_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_DBUS0_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache."] +pub type L1_DBUS0_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS1_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache."] +pub type L1_DBUS1_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_DBUS1_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache."] +pub type L1_DBUS1_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS2_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache."] +pub type L1_DBUS2_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_DBUS2_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache."] +pub type L1_DBUS2_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DBUS3_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache."] +pub type L1_DBUS3_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_DBUS3_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache."] +pub type L1_DBUS3_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."] + #[inline(always)] + pub fn l1_ibus0_ovf_int_raw(&self) -> L1_IBUS0_OVF_INT_RAW_R { + L1_IBUS0_OVF_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1."] + #[inline(always)] + pub fn l1_ibus1_ovf_int_raw(&self) -> L1_IBUS1_OVF_INT_RAW_R { + L1_IBUS1_OVF_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2."] + #[inline(always)] + pub fn l1_ibus2_ovf_int_raw(&self) -> L1_IBUS2_OVF_INT_RAW_R { + L1_IBUS2_OVF_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3."] + #[inline(always)] + pub fn l1_ibus3_ovf_int_raw(&self) -> L1_IBUS3_OVF_INT_RAW_R { + L1_IBUS3_OVF_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus0_ovf_int_raw(&self) -> L1_DBUS0_OVF_INT_RAW_R { + L1_DBUS0_OVF_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus1_ovf_int_raw(&self) -> L1_DBUS1_OVF_INT_RAW_R { + L1_DBUS1_OVF_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus2_ovf_int_raw(&self) -> L1_DBUS2_OVF_INT_RAW_R { + L1_DBUS2_OVF_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus3_ovf_int_raw(&self) -> L1_DBUS3_OVF_INT_RAW_R { + L1_DBUS3_OVF_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_ACS_CNT_INT_RAW") + .field( + "l1_ibus0_ovf_int_raw", + &format_args!("{}", self.l1_ibus0_ovf_int_raw().bit()), + ) + .field( + "l1_ibus1_ovf_int_raw", + &format_args!("{}", self.l1_ibus1_ovf_int_raw().bit()), + ) + .field( + "l1_ibus2_ovf_int_raw", + &format_args!("{}", self.l1_ibus2_ovf_int_raw().bit()), + ) + .field( + "l1_ibus3_ovf_int_raw", + &format_args!("{}", self.l1_ibus3_ovf_int_raw().bit()), + ) + .field( + "l1_dbus0_ovf_int_raw", + &format_args!("{}", self.l1_dbus0_ovf_int_raw().bit()), + ) + .field( + "l1_dbus1_ovf_int_raw", + &format_args!("{}", self.l1_dbus1_ovf_int_raw().bit()), + ) + .field( + "l1_dbus2_ovf_int_raw", + &format_args!("{}", self.l1_dbus2_ovf_int_raw().bit()), + ) + .field( + "l1_dbus3_ovf_int_raw", + &format_args!("{}", self.l1_dbus3_ovf_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_ibus0_ovf_int_raw( + &mut self, + ) -> L1_IBUS0_OVF_INT_RAW_W { + L1_IBUS0_OVF_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_ibus1_ovf_int_raw( + &mut self, + ) -> L1_IBUS1_OVF_INT_RAW_W { + L1_IBUS1_OVF_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2."] + #[inline(always)] + #[must_use] + pub fn l1_ibus2_ovf_int_raw( + &mut self, + ) -> L1_IBUS2_OVF_INT_RAW_W { + L1_IBUS2_OVF_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3."] + #[inline(always)] + #[must_use] + pub fn l1_ibus3_ovf_int_raw( + &mut self, + ) -> L1_IBUS3_OVF_INT_RAW_W { + L1_IBUS3_OVF_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus0_ovf_int_raw( + &mut self, + ) -> L1_DBUS0_OVF_INT_RAW_W { + L1_DBUS0_OVF_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus1_ovf_int_raw( + &mut self, + ) -> L1_DBUS1_OVF_INT_RAW_W { + L1_DBUS1_OVF_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus2_ovf_int_raw( + &mut self, + ) -> L1_DBUS2_OVF_INT_RAW_W { + L1_DBUS2_OVF_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dbus3_ovf_int_raw( + &mut self, + ) -> L1_DBUS3_OVF_INT_RAW_W { + L1_DBUS3_OVF_INT_RAW_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Counter Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_ACS_CNT_INT_RAW_SPEC; +impl crate::RegisterSpec for L1_CACHE_ACS_CNT_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_acs_cnt_int_raw::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_ACS_CNT_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_cnt_int_raw::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_ACS_CNT_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_ACS_CNT_INT_RAW to value 0"] +impl crate::Resettable for L1_CACHE_ACS_CNT_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_acs_cnt_int_st.rs b/esp32p4/src/cache/l1_cache_acs_cnt_int_st.rs new file mode 100644 index 0000000000..0b66a5f3c6 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_acs_cnt_int_st.rs @@ -0,0 +1,116 @@ +#[doc = "Register `L1_CACHE_ACS_CNT_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS0_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."] +pub type L1_IBUS0_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_IBUS1_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1."] +pub type L1_IBUS1_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_IBUS2_OVF_INT_ST` reader - Reserved"] +pub type L1_IBUS2_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_IBUS3_OVF_INT_ST` reader - Reserved"] +pub type L1_IBUS3_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_DBUS0_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache."] +pub type L1_DBUS0_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_DBUS1_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache."] +pub type L1_DBUS1_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_DBUS2_OVF_INT_ST` reader - Reserved"] +pub type L1_DBUS2_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_DBUS3_OVF_INT_ST` reader - Reserved"] +pub type L1_DBUS3_OVF_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."] + #[inline(always)] + pub fn l1_ibus0_ovf_int_st(&self) -> L1_IBUS0_OVF_INT_ST_R { + L1_IBUS0_OVF_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1."] + #[inline(always)] + pub fn l1_ibus1_ovf_int_st(&self) -> L1_IBUS1_OVF_INT_ST_R { + L1_IBUS1_OVF_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_ibus2_ovf_int_st(&self) -> L1_IBUS2_OVF_INT_ST_R { + L1_IBUS2_OVF_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_ibus3_ovf_int_st(&self) -> L1_IBUS3_OVF_INT_ST_R { + L1_IBUS3_OVF_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus0_ovf_int_st(&self) -> L1_DBUS0_OVF_INT_ST_R { + L1_DBUS0_OVF_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus1_ovf_int_st(&self) -> L1_DBUS1_OVF_INT_ST_R { + L1_DBUS1_OVF_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn l1_dbus2_ovf_int_st(&self) -> L1_DBUS2_OVF_INT_ST_R { + L1_DBUS2_OVF_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn l1_dbus3_ovf_int_st(&self) -> L1_DBUS3_OVF_INT_ST_R { + L1_DBUS3_OVF_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_ACS_CNT_INT_ST") + .field( + "l1_ibus0_ovf_int_st", + &format_args!("{}", self.l1_ibus0_ovf_int_st().bit()), + ) + .field( + "l1_ibus1_ovf_int_st", + &format_args!("{}", self.l1_ibus1_ovf_int_st().bit()), + ) + .field( + "l1_ibus2_ovf_int_st", + &format_args!("{}", self.l1_ibus2_ovf_int_st().bit()), + ) + .field( + "l1_ibus3_ovf_int_st", + &format_args!("{}", self.l1_ibus3_ovf_int_st().bit()), + ) + .field( + "l1_dbus0_ovf_int_st", + &format_args!("{}", self.l1_dbus0_ovf_int_st().bit()), + ) + .field( + "l1_dbus1_ovf_int_st", + &format_args!("{}", self.l1_dbus1_ovf_int_st().bit()), + ) + .field( + "l1_dbus2_ovf_int_st", + &format_args!("{}", self.l1_dbus2_ovf_int_st().bit()), + ) + .field( + "l1_dbus3_ovf_int_st", + &format_args!("{}", self.l1_dbus3_ovf_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Cache Access Counter Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_ACS_CNT_INT_ST_SPEC; +impl crate::RegisterSpec for L1_CACHE_ACS_CNT_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_acs_cnt_int_st::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_ACS_CNT_INT_ST_SPEC {} +#[doc = "`reset()` method sets L1_CACHE_ACS_CNT_INT_ST to value 0"] +impl crate::Resettable for L1_CACHE_ACS_CNT_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_acs_fail_ctrl.rs b/esp32p4/src/cache/l1_cache_acs_fail_ctrl.rs new file mode 100644 index 0000000000..761549165c --- /dev/null +++ b/esp32p4/src/cache/l1_cache_acs_fail_ctrl.rs @@ -0,0 +1,152 @@ +#[doc = "Register `L1_CACHE_ACS_FAIL_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_ACS_FAIL_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_ACS_FAIL_CHECK_MODE` reader - The bit is used to configure l1 icache0 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L1_ICACHE0_ACS_FAIL_CHECK_MODE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_ACS_FAIL_CHECK_MODE` writer - The bit is used to configure l1 icache0 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L1_ICACHE0_ACS_FAIL_CHECK_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_ACS_FAIL_CHECK_MODE` reader - The bit is used to configure l1 icache1 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L1_ICACHE1_ACS_FAIL_CHECK_MODE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_ACS_FAIL_CHECK_MODE` writer - The bit is used to configure l1 icache1 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L1_ICACHE1_ACS_FAIL_CHECK_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_ACS_FAIL_CHECK_MODE` reader - The bit is used to configure l1 icache2 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L1_ICACHE2_ACS_FAIL_CHECK_MODE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_ACS_FAIL_CHECK_MODE` writer - The bit is used to configure l1 icache2 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L1_ICACHE2_ACS_FAIL_CHECK_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE3_ACS_FAIL_CHECK_MODE` reader - The bit is used to configure l1 icache3 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L1_ICACHE3_ACS_FAIL_CHECK_MODE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_ACS_FAIL_CHECK_MODE` writer - The bit is used to configure l1 icache3 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L1_ICACHE3_ACS_FAIL_CHECK_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_ACS_FAIL_CHECK_MODE` reader - The bit is used to configure l1 dcache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L1_DCACHE_ACS_FAIL_CHECK_MODE_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_ACS_FAIL_CHECK_MODE` writer - The bit is used to configure l1 dcache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L1_DCACHE_ACS_FAIL_CHECK_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to configure l1 icache0 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + pub fn l1_icache0_acs_fail_check_mode(&self) -> L1_ICACHE0_ACS_FAIL_CHECK_MODE_R { + L1_ICACHE0_ACS_FAIL_CHECK_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to configure l1 icache1 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + pub fn l1_icache1_acs_fail_check_mode(&self) -> L1_ICACHE1_ACS_FAIL_CHECK_MODE_R { + L1_ICACHE1_ACS_FAIL_CHECK_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure l1 icache2 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + pub fn l1_icache2_acs_fail_check_mode(&self) -> L1_ICACHE2_ACS_FAIL_CHECK_MODE_R { + L1_ICACHE2_ACS_FAIL_CHECK_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The bit is used to configure l1 icache3 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + pub fn l1_icache3_acs_fail_check_mode(&self) -> L1_ICACHE3_ACS_FAIL_CHECK_MODE_R { + L1_ICACHE3_ACS_FAIL_CHECK_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to configure l1 dcache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + pub fn l1_dcache_acs_fail_check_mode(&self) -> L1_DCACHE_ACS_FAIL_CHECK_MODE_R { + L1_DCACHE_ACS_FAIL_CHECK_MODE_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_ACS_FAIL_CTRL") + .field( + "l1_icache0_acs_fail_check_mode", + &format_args!("{}", self.l1_icache0_acs_fail_check_mode().bit()), + ) + .field( + "l1_icache1_acs_fail_check_mode", + &format_args!("{}", self.l1_icache1_acs_fail_check_mode().bit()), + ) + .field( + "l1_icache2_acs_fail_check_mode", + &format_args!("{}", self.l1_icache2_acs_fail_check_mode().bit()), + ) + .field( + "l1_icache3_acs_fail_check_mode", + &format_args!("{}", self.l1_icache3_acs_fail_check_mode().bit()), + ) + .field( + "l1_dcache_acs_fail_check_mode", + &format_args!("{}", self.l1_dcache_acs_fail_check_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to configure l1 icache0 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + #[must_use] + pub fn l1_icache0_acs_fail_check_mode( + &mut self, + ) -> L1_ICACHE0_ACS_FAIL_CHECK_MODE_W { + L1_ICACHE0_ACS_FAIL_CHECK_MODE_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to configure l1 icache1 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + #[must_use] + pub fn l1_icache1_acs_fail_check_mode( + &mut self, + ) -> L1_ICACHE1_ACS_FAIL_CHECK_MODE_W { + L1_ICACHE1_ACS_FAIL_CHECK_MODE_W::new(self, 1) + } + #[doc = "Bit 2 - The bit is used to configure l1 icache2 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + #[must_use] + pub fn l1_icache2_acs_fail_check_mode( + &mut self, + ) -> L1_ICACHE2_ACS_FAIL_CHECK_MODE_W { + L1_ICACHE2_ACS_FAIL_CHECK_MODE_W::new(self, 2) + } + #[doc = "Bit 3 - The bit is used to configure l1 icache3 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + #[must_use] + pub fn l1_icache3_acs_fail_check_mode( + &mut self, + ) -> L1_ICACHE3_ACS_FAIL_CHECK_MODE_W { + L1_ICACHE3_ACS_FAIL_CHECK_MODE_W::new(self, 3) + } + #[doc = "Bit 4 - The bit is used to configure l1 dcache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_acs_fail_check_mode( + &mut self, + ) -> L1_DCACHE_ACS_FAIL_CHECK_MODE_W { + L1_DCACHE_ACS_FAIL_CHECK_MODE_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Fail Configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_ACS_FAIL_CTRL_SPEC; +impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_acs_fail_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_ACS_FAIL_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_fail_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_ACS_FAIL_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_ACS_FAIL_CTRL to value 0"] +impl crate::Resettable for L1_CACHE_ACS_FAIL_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_acs_fail_int_clr.rs b/esp32p4/src/cache/l1_cache_acs_fail_int_clr.rs new file mode 100644 index 0000000000..818b34ab46 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_acs_fail_int_clr.rs @@ -0,0 +1,99 @@ +#[doc = "Register `L1_CACHE_ACS_FAIL_INT_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_ACS_FAIL_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_FAIL_INT_CLR` writer - The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."] +pub type L1_ICACHE0_FAIL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_FAIL_INT_CLR` writer - The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1."] +pub type L1_ICACHE1_FAIL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_FAIL_INT_CLR` reader - Reserved"] +pub type L1_ICACHE2_FAIL_INT_CLR_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_FAIL_INT_CLR` reader - Reserved"] +pub type L1_ICACHE3_FAIL_INT_CLR_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_FAIL_INT_CLR` writer - The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."] +pub type L1_DCACHE_FAIL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_fail_int_clr(&self) -> L1_ICACHE2_FAIL_INT_CLR_R { + L1_ICACHE2_FAIL_INT_CLR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_fail_int_clr(&self) -> L1_ICACHE3_FAIL_INT_CLR_R { + L1_ICACHE3_FAIL_INT_CLR_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_ACS_FAIL_INT_CLR") + .field( + "l1_icache2_fail_int_clr", + &format_args!("{}", self.l1_icache2_fail_int_clr().bit()), + ) + .field( + "l1_icache3_fail_int_clr", + &format_args!("{}", self.l1_icache3_fail_int_clr().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_fail_int_clr( + &mut self, + ) -> L1_ICACHE0_FAIL_INT_CLR_W { + L1_ICACHE0_FAIL_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_fail_int_clr( + &mut self, + ) -> L1_ICACHE1_FAIL_INT_CLR_W { + L1_ICACHE1_FAIL_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_fail_int_clr( + &mut self, + ) -> L1_DCACHE_FAIL_INT_CLR_W { + L1_DCACHE_FAIL_INT_CLR_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1-Cache Access Fail Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_ACS_FAIL_INT_CLR_SPEC; +impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_acs_fail_int_clr::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_ACS_FAIL_INT_CLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_fail_int_clr::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_ACS_FAIL_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_ACS_FAIL_INT_CLR to value 0"] +impl crate::Resettable for L1_CACHE_ACS_FAIL_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_acs_fail_int_ena.rs b/esp32p4/src/cache/l1_cache_acs_fail_int_ena.rs new file mode 100644 index 0000000000..51874079c2 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_acs_fail_int_ena.rs @@ -0,0 +1,132 @@ +#[doc = "Register `L1_CACHE_ACS_FAIL_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_ACS_FAIL_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_FAIL_INT_ENA` reader - The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."] +pub type L1_ICACHE0_FAIL_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_FAIL_INT_ENA` writer - The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."] +pub type L1_ICACHE0_FAIL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_FAIL_INT_ENA` reader - The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1."] +pub type L1_ICACHE1_FAIL_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_FAIL_INT_ENA` writer - The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1."] +pub type L1_ICACHE1_FAIL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_FAIL_INT_ENA` reader - Reserved"] +pub type L1_ICACHE2_FAIL_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_FAIL_INT_ENA` reader - Reserved"] +pub type L1_ICACHE3_FAIL_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_FAIL_INT_ENA` reader - The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."] +pub type L1_DCACHE_FAIL_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_FAIL_INT_ENA` writer - The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."] +pub type L1_DCACHE_FAIL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."] + #[inline(always)] + pub fn l1_icache0_fail_int_ena(&self) -> L1_ICACHE0_FAIL_INT_ENA_R { + L1_ICACHE0_FAIL_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1."] + #[inline(always)] + pub fn l1_icache1_fail_int_ena(&self) -> L1_ICACHE1_FAIL_INT_ENA_R { + L1_ICACHE1_FAIL_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_fail_int_ena(&self) -> L1_ICACHE2_FAIL_INT_ENA_R { + L1_ICACHE2_FAIL_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_fail_int_ena(&self) -> L1_ICACHE3_FAIL_INT_ENA_R { + L1_ICACHE3_FAIL_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."] + #[inline(always)] + pub fn l1_dcache_fail_int_ena(&self) -> L1_DCACHE_FAIL_INT_ENA_R { + L1_DCACHE_FAIL_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_ACS_FAIL_INT_ENA") + .field( + "l1_icache0_fail_int_ena", + &format_args!("{}", self.l1_icache0_fail_int_ena().bit()), + ) + .field( + "l1_icache1_fail_int_ena", + &format_args!("{}", self.l1_icache1_fail_int_ena().bit()), + ) + .field( + "l1_icache2_fail_int_ena", + &format_args!("{}", self.l1_icache2_fail_int_ena().bit()), + ) + .field( + "l1_icache3_fail_int_ena", + &format_args!("{}", self.l1_icache3_fail_int_ena().bit()), + ) + .field( + "l1_dcache_fail_int_ena", + &format_args!("{}", self.l1_dcache_fail_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_fail_int_ena( + &mut self, + ) -> L1_ICACHE0_FAIL_INT_ENA_W { + L1_ICACHE0_FAIL_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_fail_int_ena( + &mut self, + ) -> L1_ICACHE1_FAIL_INT_ENA_W { + L1_ICACHE1_FAIL_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_fail_int_ena( + &mut self, + ) -> L1_DCACHE_FAIL_INT_ENA_W { + L1_DCACHE_FAIL_INT_ENA_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_ACS_FAIL_INT_ENA_SPEC; +impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_acs_fail_int_ena::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_ACS_FAIL_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_fail_int_ena::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_ACS_FAIL_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_ACS_FAIL_INT_ENA to value 0"] +impl crate::Resettable for L1_CACHE_ACS_FAIL_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_acs_fail_int_raw.rs b/esp32p4/src/cache/l1_cache_acs_fail_int_raw.rs new file mode 100644 index 0000000000..2a9a895bff --- /dev/null +++ b/esp32p4/src/cache/l1_cache_acs_fail_int_raw.rs @@ -0,0 +1,152 @@ +#[doc = "Register `L1_CACHE_ACS_FAIL_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_ACS_FAIL_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_FAIL_INT_RAW` reader - The raw bit of the interrupt of access fail that occurs in L1-ICache0."] +pub type L1_ICACHE0_FAIL_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_FAIL_INT_RAW` writer - The raw bit of the interrupt of access fail that occurs in L1-ICache0."] +pub type L1_ICACHE0_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_FAIL_INT_RAW` reader - The raw bit of the interrupt of access fail that occurs in L1-ICache1."] +pub type L1_ICACHE1_FAIL_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_FAIL_INT_RAW` writer - The raw bit of the interrupt of access fail that occurs in L1-ICache1."] +pub type L1_ICACHE1_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_FAIL_INT_RAW` reader - The raw bit of the interrupt of access fail that occurs in L1-ICache2."] +pub type L1_ICACHE2_FAIL_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_FAIL_INT_RAW` writer - The raw bit of the interrupt of access fail that occurs in L1-ICache2."] +pub type L1_ICACHE2_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE3_FAIL_INT_RAW` reader - The raw bit of the interrupt of access fail that occurs in L1-ICache3."] +pub type L1_ICACHE3_FAIL_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_FAIL_INT_RAW` writer - The raw bit of the interrupt of access fail that occurs in L1-ICache3."] +pub type L1_ICACHE3_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_FAIL_INT_RAW` reader - The raw bit of the interrupt of access fail that occurs in L1-DCache."] +pub type L1_DCACHE_FAIL_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_FAIL_INT_RAW` writer - The raw bit of the interrupt of access fail that occurs in L1-DCache."] +pub type L1_DCACHE_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw bit of the interrupt of access fail that occurs in L1-ICache0."] + #[inline(always)] + pub fn l1_icache0_fail_int_raw(&self) -> L1_ICACHE0_FAIL_INT_RAW_R { + L1_ICACHE0_FAIL_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw bit of the interrupt of access fail that occurs in L1-ICache1."] + #[inline(always)] + pub fn l1_icache1_fail_int_raw(&self) -> L1_ICACHE1_FAIL_INT_RAW_R { + L1_ICACHE1_FAIL_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw bit of the interrupt of access fail that occurs in L1-ICache2."] + #[inline(always)] + pub fn l1_icache2_fail_int_raw(&self) -> L1_ICACHE2_FAIL_INT_RAW_R { + L1_ICACHE2_FAIL_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw bit of the interrupt of access fail that occurs in L1-ICache3."] + #[inline(always)] + pub fn l1_icache3_fail_int_raw(&self) -> L1_ICACHE3_FAIL_INT_RAW_R { + L1_ICACHE3_FAIL_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw bit of the interrupt of access fail that occurs in L1-DCache."] + #[inline(always)] + pub fn l1_dcache_fail_int_raw(&self) -> L1_DCACHE_FAIL_INT_RAW_R { + L1_DCACHE_FAIL_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_ACS_FAIL_INT_RAW") + .field( + "l1_icache0_fail_int_raw", + &format_args!("{}", self.l1_icache0_fail_int_raw().bit()), + ) + .field( + "l1_icache1_fail_int_raw", + &format_args!("{}", self.l1_icache1_fail_int_raw().bit()), + ) + .field( + "l1_icache2_fail_int_raw", + &format_args!("{}", self.l1_icache2_fail_int_raw().bit()), + ) + .field( + "l1_icache3_fail_int_raw", + &format_args!("{}", self.l1_icache3_fail_int_raw().bit()), + ) + .field( + "l1_dcache_fail_int_raw", + &format_args!("{}", self.l1_dcache_fail_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw bit of the interrupt of access fail that occurs in L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_fail_int_raw( + &mut self, + ) -> L1_ICACHE0_FAIL_INT_RAW_W { + L1_ICACHE0_FAIL_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw bit of the interrupt of access fail that occurs in L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_fail_int_raw( + &mut self, + ) -> L1_ICACHE1_FAIL_INT_RAW_W { + L1_ICACHE1_FAIL_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw bit of the interrupt of access fail that occurs in L1-ICache2."] + #[inline(always)] + #[must_use] + pub fn l1_icache2_fail_int_raw( + &mut self, + ) -> L1_ICACHE2_FAIL_INT_RAW_W { + L1_ICACHE2_FAIL_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw bit of the interrupt of access fail that occurs in L1-ICache3."] + #[inline(always)] + #[must_use] + pub fn l1_icache3_fail_int_raw( + &mut self, + ) -> L1_ICACHE3_FAIL_INT_RAW_W { + L1_ICACHE3_FAIL_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw bit of the interrupt of access fail that occurs in L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_fail_int_raw( + &mut self, + ) -> L1_DCACHE_FAIL_INT_RAW_W { + L1_DCACHE_FAIL_INT_RAW_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Fail Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_ACS_FAIL_INT_RAW_SPEC; +impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_acs_fail_int_raw::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_ACS_FAIL_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_fail_int_raw::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_ACS_FAIL_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_ACS_FAIL_INT_RAW to value 0"] +impl crate::Resettable for L1_CACHE_ACS_FAIL_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_acs_fail_int_st.rs b/esp32p4/src/cache/l1_cache_acs_fail_int_st.rs new file mode 100644 index 0000000000..c1db8ad0e0 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_acs_fail_int_st.rs @@ -0,0 +1,83 @@ +#[doc = "Register `L1_CACHE_ACS_FAIL_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE0_FAIL_INT_ST` reader - The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache."] +pub type L1_ICACHE0_FAIL_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_FAIL_INT_ST` reader - The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache."] +pub type L1_ICACHE1_FAIL_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_FAIL_INT_ST` reader - Reserved"] +pub type L1_ICACHE2_FAIL_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_FAIL_INT_ST` reader - Reserved"] +pub type L1_ICACHE3_FAIL_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_FAIL_INT_ST` reader - The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."] +pub type L1_DCACHE_FAIL_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache0_fail_int_st(&self) -> L1_ICACHE0_FAIL_INT_ST_R { + L1_ICACHE0_FAIL_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache1_fail_int_st(&self) -> L1_ICACHE1_FAIL_INT_ST_R { + L1_ICACHE1_FAIL_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_fail_int_st(&self) -> L1_ICACHE2_FAIL_INT_ST_R { + L1_ICACHE2_FAIL_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_fail_int_st(&self) -> L1_ICACHE3_FAIL_INT_ST_R { + L1_ICACHE3_FAIL_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."] + #[inline(always)] + pub fn l1_dcache_fail_int_st(&self) -> L1_DCACHE_FAIL_INT_ST_R { + L1_DCACHE_FAIL_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_ACS_FAIL_INT_ST") + .field( + "l1_icache0_fail_int_st", + &format_args!("{}", self.l1_icache0_fail_int_st().bit()), + ) + .field( + "l1_icache1_fail_int_st", + &format_args!("{}", self.l1_icache1_fail_int_st().bit()), + ) + .field( + "l1_icache2_fail_int_st", + &format_args!("{}", self.l1_icache2_fail_int_st().bit()), + ) + .field( + "l1_icache3_fail_int_st", + &format_args!("{}", self.l1_icache3_fail_int_st().bit()), + ) + .field( + "l1_dcache_fail_int_st", + &format_args!("{}", self.l1_dcache_fail_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_ACS_FAIL_INT_ST_SPEC; +impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_acs_fail_int_st::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_ACS_FAIL_INT_ST_SPEC {} +#[doc = "`reset()` method sets L1_CACHE_ACS_FAIL_INT_ST to value 0"] +impl crate::Resettable for L1_CACHE_ACS_FAIL_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_atomic_conf.rs b/esp32p4/src/cache/l1_cache_atomic_conf.rs new file mode 100644 index 0000000000..dace0f729a --- /dev/null +++ b/esp32p4/src/cache/l1_cache_atomic_conf.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L1_CACHE_ATOMIC_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_ATOMIC_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_ATOMIC_EN` reader - The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable."] +pub type L1_DCACHE_ATOMIC_EN_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_ATOMIC_EN` writer - The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable."] +pub type L1_DCACHE_ATOMIC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable."] + #[inline(always)] + pub fn l1_dcache_atomic_en(&self) -> L1_DCACHE_ATOMIC_EN_R { + L1_DCACHE_ATOMIC_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_ATOMIC_CONF") + .field( + "l1_dcache_atomic_en", + &format_args!("{}", self.l1_dcache_atomic_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_atomic_en(&mut self) -> L1_DCACHE_ATOMIC_EN_W { + L1_DCACHE_ATOMIC_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 Cache atomic feature configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_atomic_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_atomic_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_ATOMIC_CONF_SPEC; +impl crate::RegisterSpec for L1_CACHE_ATOMIC_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_atomic_conf::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_ATOMIC_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_atomic_conf::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_ATOMIC_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_ATOMIC_CONF to value 0x01"] +impl crate::Resettable for L1_CACHE_ATOMIC_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/cache/l1_cache_autoload_buf_clr_ctrl.rs b/esp32p4/src/cache/l1_cache_autoload_buf_clr_ctrl.rs new file mode 100644 index 0000000000..4106bf5201 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_autoload_buf_clr_ctrl.rs @@ -0,0 +1,132 @@ +#[doc = "Register `L1_CACHE_AUTOLOAD_BUF_CLR_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_AUTOLOAD_BUF_CLR_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_ALD_BUF_CLR` reader - set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0."] +pub type L1_ICACHE0_ALD_BUF_CLR_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_ALD_BUF_CLR` writer - set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0."] +pub type L1_ICACHE0_ALD_BUF_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_ALD_BUF_CLR` reader - set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1."] +pub type L1_ICACHE1_ALD_BUF_CLR_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_ALD_BUF_CLR` writer - set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1."] +pub type L1_ICACHE1_ALD_BUF_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_ALD_BUF_CLR` reader - Reserved"] +pub type L1_ICACHE2_ALD_BUF_CLR_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_ALD_BUF_CLR` reader - Reserved"] +pub type L1_ICACHE3_ALD_BUF_CLR_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_ALD_BUF_CLR` reader - set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, autoload will not work in L1-DCache. This bit should not be active when autoload works in L1-DCache."] +pub type L1_DCACHE_ALD_BUF_CLR_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_ALD_BUF_CLR` writer - set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, autoload will not work in L1-DCache. This bit should not be active when autoload works in L1-DCache."] +pub type L1_DCACHE_ALD_BUF_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0."] + #[inline(always)] + pub fn l1_icache0_ald_buf_clr(&self) -> L1_ICACHE0_ALD_BUF_CLR_R { + L1_ICACHE0_ALD_BUF_CLR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1."] + #[inline(always)] + pub fn l1_icache1_ald_buf_clr(&self) -> L1_ICACHE1_ALD_BUF_CLR_R { + L1_ICACHE1_ALD_BUF_CLR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_ald_buf_clr(&self) -> L1_ICACHE2_ALD_BUF_CLR_R { + L1_ICACHE2_ALD_BUF_CLR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_ald_buf_clr(&self) -> L1_ICACHE3_ALD_BUF_CLR_R { + L1_ICACHE3_ALD_BUF_CLR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, autoload will not work in L1-DCache. This bit should not be active when autoload works in L1-DCache."] + #[inline(always)] + pub fn l1_dcache_ald_buf_clr(&self) -> L1_DCACHE_ALD_BUF_CLR_R { + L1_DCACHE_ALD_BUF_CLR_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_AUTOLOAD_BUF_CLR_CTRL") + .field( + "l1_icache0_ald_buf_clr", + &format_args!("{}", self.l1_icache0_ald_buf_clr().bit()), + ) + .field( + "l1_icache1_ald_buf_clr", + &format_args!("{}", self.l1_icache1_ald_buf_clr().bit()), + ) + .field( + "l1_icache2_ald_buf_clr", + &format_args!("{}", self.l1_icache2_ald_buf_clr().bit()), + ) + .field( + "l1_icache3_ald_buf_clr", + &format_args!("{}", self.l1_icache3_ald_buf_clr().bit()), + ) + .field( + "l1_dcache_ald_buf_clr", + &format_args!("{}", self.l1_dcache_ald_buf_clr().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_ald_buf_clr( + &mut self, + ) -> L1_ICACHE0_ALD_BUF_CLR_W { + L1_ICACHE0_ALD_BUF_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_ald_buf_clr( + &mut self, + ) -> L1_ICACHE1_ALD_BUF_CLR_W { + L1_ICACHE1_ALD_BUF_CLR_W::new(self, 1) + } + #[doc = "Bit 4 - set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, autoload will not work in L1-DCache. This bit should not be active when autoload works in L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_ald_buf_clr( + &mut self, + ) -> L1_DCACHE_ALD_BUF_CLR_W { + L1_DCACHE_ALD_BUF_CLR_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Autoload buffer clear control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_autoload_buf_clr_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_autoload_buf_clr_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC; +impl crate::RegisterSpec for L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_autoload_buf_clr_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_autoload_buf_clr_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_AUTOLOAD_BUF_CLR_CTRL to value 0"] +impl crate::Resettable for L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_data_mem_acs_conf.rs b/esp32p4/src/cache/l1_cache_data_mem_acs_conf.rs new file mode 100644 index 0000000000..49dcec4cdc --- /dev/null +++ b/esp32p4/src/cache/l1_cache_data_mem_acs_conf.rs @@ -0,0 +1,217 @@ +#[doc = "Register `L1_CACHE_DATA_MEM_ACS_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_DATA_MEM_ACS_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_DATA_MEM_RD_EN` reader - The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE0_DATA_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_DATA_MEM_RD_EN` writer - The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE0_DATA_MEM_RD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_DATA_MEM_WR_EN` reader - The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE0_DATA_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_DATA_MEM_WR_EN` writer - The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE0_DATA_MEM_WR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_DATA_MEM_RD_EN` reader - The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE1_DATA_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_DATA_MEM_RD_EN` writer - The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE1_DATA_MEM_RD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_DATA_MEM_WR_EN` reader - The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE1_DATA_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_DATA_MEM_WR_EN` writer - The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE1_DATA_MEM_WR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_DATA_MEM_RD_EN` reader - Reserved"] +pub type L1_ICACHE2_DATA_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_DATA_MEM_WR_EN` reader - Reserved"] +pub type L1_ICACHE2_DATA_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_DATA_MEM_RD_EN` reader - Reserved"] +pub type L1_ICACHE3_DATA_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_DATA_MEM_WR_EN` reader - Reserved"] +pub type L1_ICACHE3_DATA_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_DATA_MEM_RD_EN` reader - The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1: enable."] +pub type L1_DCACHE_DATA_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_DATA_MEM_RD_EN` writer - The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1: enable."] +pub type L1_DCACHE_DATA_MEM_RD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_DATA_MEM_WR_EN` reader - The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1: enable."] +pub type L1_DCACHE_DATA_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_DATA_MEM_WR_EN` writer - The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1: enable."] +pub type L1_DCACHE_DATA_MEM_WR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_icache0_data_mem_rd_en(&self) -> L1_ICACHE0_DATA_MEM_RD_EN_R { + L1_ICACHE0_DATA_MEM_RD_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_icache0_data_mem_wr_en(&self) -> L1_ICACHE0_DATA_MEM_WR_EN_R { + L1_ICACHE0_DATA_MEM_WR_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_icache1_data_mem_rd_en(&self) -> L1_ICACHE1_DATA_MEM_RD_EN_R { + L1_ICACHE1_DATA_MEM_RD_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_icache1_data_mem_wr_en(&self) -> L1_ICACHE1_DATA_MEM_WR_EN_R { + L1_ICACHE1_DATA_MEM_WR_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn l1_icache2_data_mem_rd_en(&self) -> L1_ICACHE2_DATA_MEM_RD_EN_R { + L1_ICACHE2_DATA_MEM_RD_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn l1_icache2_data_mem_wr_en(&self) -> L1_ICACHE2_DATA_MEM_WR_EN_R { + L1_ICACHE2_DATA_MEM_WR_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn l1_icache3_data_mem_rd_en(&self) -> L1_ICACHE3_DATA_MEM_RD_EN_R { + L1_ICACHE3_DATA_MEM_RD_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn l1_icache3_data_mem_wr_en(&self) -> L1_ICACHE3_DATA_MEM_WR_EN_R { + L1_ICACHE3_DATA_MEM_WR_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 16 - The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_dcache_data_mem_rd_en(&self) -> L1_DCACHE_DATA_MEM_RD_EN_R { + L1_DCACHE_DATA_MEM_RD_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_dcache_data_mem_wr_en(&self) -> L1_DCACHE_DATA_MEM_WR_EN_R { + L1_DCACHE_DATA_MEM_WR_EN_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_DATA_MEM_ACS_CONF") + .field( + "l1_icache0_data_mem_rd_en", + &format_args!("{}", self.l1_icache0_data_mem_rd_en().bit()), + ) + .field( + "l1_icache0_data_mem_wr_en", + &format_args!("{}", self.l1_icache0_data_mem_wr_en().bit()), + ) + .field( + "l1_icache1_data_mem_rd_en", + &format_args!("{}", self.l1_icache1_data_mem_rd_en().bit()), + ) + .field( + "l1_icache1_data_mem_wr_en", + &format_args!("{}", self.l1_icache1_data_mem_wr_en().bit()), + ) + .field( + "l1_icache2_data_mem_rd_en", + &format_args!("{}", self.l1_icache2_data_mem_rd_en().bit()), + ) + .field( + "l1_icache2_data_mem_wr_en", + &format_args!("{}", self.l1_icache2_data_mem_wr_en().bit()), + ) + .field( + "l1_icache3_data_mem_rd_en", + &format_args!("{}", self.l1_icache3_data_mem_rd_en().bit()), + ) + .field( + "l1_icache3_data_mem_wr_en", + &format_args!("{}", self.l1_icache3_data_mem_wr_en().bit()), + ) + .field( + "l1_dcache_data_mem_rd_en", + &format_args!("{}", self.l1_dcache_data_mem_rd_en().bit()), + ) + .field( + "l1_dcache_data_mem_wr_en", + &format_args!("{}", self.l1_dcache_data_mem_wr_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_data_mem_rd_en( + &mut self, + ) -> L1_ICACHE0_DATA_MEM_RD_EN_W { + L1_ICACHE0_DATA_MEM_RD_EN_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_data_mem_wr_en( + &mut self, + ) -> L1_ICACHE0_DATA_MEM_WR_EN_W { + L1_ICACHE0_DATA_MEM_WR_EN_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_data_mem_rd_en( + &mut self, + ) -> L1_ICACHE1_DATA_MEM_RD_EN_W { + L1_ICACHE1_DATA_MEM_RD_EN_W::new(self, 4) + } + #[doc = "Bit 5 - The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_data_mem_wr_en( + &mut self, + ) -> L1_ICACHE1_DATA_MEM_WR_EN_W { + L1_ICACHE1_DATA_MEM_WR_EN_W::new(self, 5) + } + #[doc = "Bit 16 - The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_data_mem_rd_en( + &mut self, + ) -> L1_DCACHE_DATA_MEM_RD_EN_W { + L1_DCACHE_DATA_MEM_RD_EN_W::new(self, 16) + } + #[doc = "Bit 17 - The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_data_mem_wr_en( + &mut self, + ) -> L1_DCACHE_DATA_MEM_WR_EN_W { + L1_DCACHE_DATA_MEM_WR_EN_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache data memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_data_mem_acs_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_data_mem_acs_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_DATA_MEM_ACS_CONF_SPEC; +impl crate::RegisterSpec for L1_CACHE_DATA_MEM_ACS_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_data_mem_acs_conf::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_DATA_MEM_ACS_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_data_mem_acs_conf::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_DATA_MEM_ACS_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_DATA_MEM_ACS_CONF to value 0x0003_3333"] +impl crate::Resettable for L1_CACHE_DATA_MEM_ACS_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0003_3333; +} diff --git a/esp32p4/src/cache/l1_cache_data_mem_power_ctrl.rs b/esp32p4/src/cache/l1_cache_data_mem_power_ctrl.rs new file mode 100644 index 0000000000..7595c4b8a2 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_data_mem_power_ctrl.rs @@ -0,0 +1,302 @@ +#[doc = "Register `L1_CACHE_DATA_MEM_POWER_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_DATA_MEM_POWER_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_DATA_MEM_FORCE_ON` reader - The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating."] +pub type L1_ICACHE0_DATA_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_DATA_MEM_FORCE_ON` writer - The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating."] +pub type L1_ICACHE0_DATA_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_DATA_MEM_FORCE_PD` reader - The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_ICACHE0_DATA_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_DATA_MEM_FORCE_PD` writer - The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_ICACHE0_DATA_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_DATA_MEM_FORCE_PU` reader - The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_ICACHE0_DATA_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_DATA_MEM_FORCE_PU` writer - The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_ICACHE0_DATA_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_DATA_MEM_FORCE_ON` reader - The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating."] +pub type L1_ICACHE1_DATA_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_DATA_MEM_FORCE_ON` writer - The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating."] +pub type L1_ICACHE1_DATA_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_DATA_MEM_FORCE_PD` reader - The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_ICACHE1_DATA_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_DATA_MEM_FORCE_PD` writer - The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_ICACHE1_DATA_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_DATA_MEM_FORCE_PU` reader - The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_ICACHE1_DATA_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_DATA_MEM_FORCE_PU` writer - The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_ICACHE1_DATA_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_DATA_MEM_FORCE_ON` reader - Reserved"] +pub type L1_ICACHE2_DATA_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_DATA_MEM_FORCE_PD` reader - Reserved"] +pub type L1_ICACHE2_DATA_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_DATA_MEM_FORCE_PU` reader - Reserved"] +pub type L1_ICACHE2_DATA_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_DATA_MEM_FORCE_ON` reader - Reserved"] +pub type L1_ICACHE3_DATA_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_DATA_MEM_FORCE_PD` reader - Reserved"] +pub type L1_ICACHE3_DATA_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_DATA_MEM_FORCE_PU` reader - Reserved"] +pub type L1_ICACHE3_DATA_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_DATA_MEM_FORCE_ON` reader - The bit is used to close clock gating of L1-DCache data memory. 1: close gating, 0: open clock gating."] +pub type L1_DCACHE_DATA_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_DATA_MEM_FORCE_ON` writer - The bit is used to close clock gating of L1-DCache data memory. 1: close gating, 0: open clock gating."] +pub type L1_DCACHE_DATA_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_DATA_MEM_FORCE_PD` reader - The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_DCACHE_DATA_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_DATA_MEM_FORCE_PD` writer - The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_DCACHE_DATA_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_DATA_MEM_FORCE_PU` reader - The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_DCACHE_DATA_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_DATA_MEM_FORCE_PU` writer - The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_DCACHE_DATA_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + pub fn l1_icache0_data_mem_force_on(&self) -> L1_ICACHE0_DATA_MEM_FORCE_ON_R { + L1_ICACHE0_DATA_MEM_FORCE_ON_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + pub fn l1_icache0_data_mem_force_pd(&self) -> L1_ICACHE0_DATA_MEM_FORCE_PD_R { + L1_ICACHE0_DATA_MEM_FORCE_PD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + pub fn l1_icache0_data_mem_force_pu(&self) -> L1_ICACHE0_DATA_MEM_FORCE_PU_R { + L1_ICACHE0_DATA_MEM_FORCE_PU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + pub fn l1_icache1_data_mem_force_on(&self) -> L1_ICACHE1_DATA_MEM_FORCE_ON_R { + L1_ICACHE1_DATA_MEM_FORCE_ON_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + pub fn l1_icache1_data_mem_force_pd(&self) -> L1_ICACHE1_DATA_MEM_FORCE_PD_R { + L1_ICACHE1_DATA_MEM_FORCE_PD_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + pub fn l1_icache1_data_mem_force_pu(&self) -> L1_ICACHE1_DATA_MEM_FORCE_PU_R { + L1_ICACHE1_DATA_MEM_FORCE_PU_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn l1_icache2_data_mem_force_on(&self) -> L1_ICACHE2_DATA_MEM_FORCE_ON_R { + L1_ICACHE2_DATA_MEM_FORCE_ON_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn l1_icache2_data_mem_force_pd(&self) -> L1_ICACHE2_DATA_MEM_FORCE_PD_R { + L1_ICACHE2_DATA_MEM_FORCE_PD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn l1_icache2_data_mem_force_pu(&self) -> L1_ICACHE2_DATA_MEM_FORCE_PU_R { + L1_ICACHE2_DATA_MEM_FORCE_PU_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn l1_icache3_data_mem_force_on(&self) -> L1_ICACHE3_DATA_MEM_FORCE_ON_R { + L1_ICACHE3_DATA_MEM_FORCE_ON_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn l1_icache3_data_mem_force_pd(&self) -> L1_ICACHE3_DATA_MEM_FORCE_PD_R { + L1_ICACHE3_DATA_MEM_FORCE_PD_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn l1_icache3_data_mem_force_pu(&self) -> L1_ICACHE3_DATA_MEM_FORCE_PU_R { + L1_ICACHE3_DATA_MEM_FORCE_PU_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - The bit is used to close clock gating of L1-DCache data memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + pub fn l1_dcache_data_mem_force_on(&self) -> L1_DCACHE_DATA_MEM_FORCE_ON_R { + L1_DCACHE_DATA_MEM_FORCE_ON_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + pub fn l1_dcache_data_mem_force_pd(&self) -> L1_DCACHE_DATA_MEM_FORCE_PD_R { + L1_DCACHE_DATA_MEM_FORCE_PD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + pub fn l1_dcache_data_mem_force_pu(&self) -> L1_DCACHE_DATA_MEM_FORCE_PU_R { + L1_DCACHE_DATA_MEM_FORCE_PU_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_DATA_MEM_POWER_CTRL") + .field( + "l1_icache0_data_mem_force_on", + &format_args!("{}", self.l1_icache0_data_mem_force_on().bit()), + ) + .field( + "l1_icache0_data_mem_force_pd", + &format_args!("{}", self.l1_icache0_data_mem_force_pd().bit()), + ) + .field( + "l1_icache0_data_mem_force_pu", + &format_args!("{}", self.l1_icache0_data_mem_force_pu().bit()), + ) + .field( + "l1_icache1_data_mem_force_on", + &format_args!("{}", self.l1_icache1_data_mem_force_on().bit()), + ) + .field( + "l1_icache1_data_mem_force_pd", + &format_args!("{}", self.l1_icache1_data_mem_force_pd().bit()), + ) + .field( + "l1_icache1_data_mem_force_pu", + &format_args!("{}", self.l1_icache1_data_mem_force_pu().bit()), + ) + .field( + "l1_icache2_data_mem_force_on", + &format_args!("{}", self.l1_icache2_data_mem_force_on().bit()), + ) + .field( + "l1_icache2_data_mem_force_pd", + &format_args!("{}", self.l1_icache2_data_mem_force_pd().bit()), + ) + .field( + "l1_icache2_data_mem_force_pu", + &format_args!("{}", self.l1_icache2_data_mem_force_pu().bit()), + ) + .field( + "l1_icache3_data_mem_force_on", + &format_args!("{}", self.l1_icache3_data_mem_force_on().bit()), + ) + .field( + "l1_icache3_data_mem_force_pd", + &format_args!("{}", self.l1_icache3_data_mem_force_pd().bit()), + ) + .field( + "l1_icache3_data_mem_force_pu", + &format_args!("{}", self.l1_icache3_data_mem_force_pu().bit()), + ) + .field( + "l1_dcache_data_mem_force_on", + &format_args!("{}", self.l1_dcache_data_mem_force_on().bit()), + ) + .field( + "l1_dcache_data_mem_force_pd", + &format_args!("{}", self.l1_dcache_data_mem_force_pd().bit()), + ) + .field( + "l1_dcache_data_mem_force_pu", + &format_args!("{}", self.l1_dcache_data_mem_force_pu().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_data_mem_force_on( + &mut self, + ) -> L1_ICACHE0_DATA_MEM_FORCE_ON_W { + L1_ICACHE0_DATA_MEM_FORCE_ON_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + #[must_use] + pub fn l1_icache0_data_mem_force_pd( + &mut self, + ) -> L1_ICACHE0_DATA_MEM_FORCE_PD_W { + L1_ICACHE0_DATA_MEM_FORCE_PD_W::new(self, 1) + } + #[doc = "Bit 2 - The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + #[must_use] + pub fn l1_icache0_data_mem_force_pu( + &mut self, + ) -> L1_ICACHE0_DATA_MEM_FORCE_PU_W { + L1_ICACHE0_DATA_MEM_FORCE_PU_W::new(self, 2) + } + #[doc = "Bit 4 - The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_data_mem_force_on( + &mut self, + ) -> L1_ICACHE1_DATA_MEM_FORCE_ON_W { + L1_ICACHE1_DATA_MEM_FORCE_ON_W::new(self, 4) + } + #[doc = "Bit 5 - The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + #[must_use] + pub fn l1_icache1_data_mem_force_pd( + &mut self, + ) -> L1_ICACHE1_DATA_MEM_FORCE_PD_W { + L1_ICACHE1_DATA_MEM_FORCE_PD_W::new(self, 5) + } + #[doc = "Bit 6 - The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + #[must_use] + pub fn l1_icache1_data_mem_force_pu( + &mut self, + ) -> L1_ICACHE1_DATA_MEM_FORCE_PU_W { + L1_ICACHE1_DATA_MEM_FORCE_PU_W::new(self, 6) + } + #[doc = "Bit 16 - The bit is used to close clock gating of L1-DCache data memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_data_mem_force_on( + &mut self, + ) -> L1_DCACHE_DATA_MEM_FORCE_ON_W { + L1_DCACHE_DATA_MEM_FORCE_ON_W::new(self, 16) + } + #[doc = "Bit 17 - The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_data_mem_force_pd( + &mut self, + ) -> L1_DCACHE_DATA_MEM_FORCE_PD_W { + L1_DCACHE_DATA_MEM_FORCE_PD_W::new(self, 17) + } + #[doc = "Bit 18 - The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_data_mem_force_pu( + &mut self, + ) -> L1_DCACHE_DATA_MEM_FORCE_PU_W { + L1_DCACHE_DATA_MEM_FORCE_PU_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache data memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_data_mem_power_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_data_mem_power_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_DATA_MEM_POWER_CTRL_SPEC; +impl crate::RegisterSpec for L1_CACHE_DATA_MEM_POWER_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_data_mem_power_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_DATA_MEM_POWER_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_data_mem_power_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_DATA_MEM_POWER_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_DATA_MEM_POWER_CTRL to value 0x0005_5555"] +impl crate::Resettable for L1_CACHE_DATA_MEM_POWER_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0005_5555; +} diff --git a/esp32p4/src/cache/l1_cache_debug_bus.rs b/esp32p4/src/cache/l1_cache_debug_bus.rs new file mode 100644 index 0000000000..5dc2bc58c1 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_debug_bus.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L1_CACHE_DEBUG_BUS` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_DEBUG_BUS` writer"] +pub type W = crate::W; +#[doc = "Field `L1_CACHE_DEBUG_BUS` reader - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."] +pub type L1_CACHE_DEBUG_BUS_R = crate::FieldReader; +#[doc = "Field `L1_CACHE_DEBUG_BUS` writer - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."] +pub type L1_CACHE_DEBUG_BUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."] + #[inline(always)] + pub fn l1_cache_debug_bus(&self) -> L1_CACHE_DEBUG_BUS_R { + L1_CACHE_DEBUG_BUS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_DEBUG_BUS") + .field( + "l1_cache_debug_bus", + &format_args!("{}", self.l1_cache_debug_bus().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."] + #[inline(always)] + #[must_use] + pub fn l1_cache_debug_bus(&mut self) -> L1_CACHE_DEBUG_BUS_W { + L1_CACHE_DEBUG_BUS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Tag/data memory content register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_debug_bus::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_debug_bus::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_DEBUG_BUS_SPEC; +impl crate::RegisterSpec for L1_CACHE_DEBUG_BUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_debug_bus::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_DEBUG_BUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_debug_bus::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_DEBUG_BUS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_DEBUG_BUS to value 0x0268"] +impl crate::Resettable for L1_CACHE_DEBUG_BUS_SPEC { + const RESET_VALUE: Self::Ux = 0x0268; +} diff --git a/esp32p4/src/cache/l1_cache_freeze_ctrl.rs b/esp32p4/src/cache/l1_cache_freeze_ctrl.rs new file mode 100644 index 0000000000..2b5a3a09f2 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_freeze_ctrl.rs @@ -0,0 +1,264 @@ +#[doc = "Register `L1_CACHE_FREEZE_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_FREEZE_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_FREEZE_EN` reader - The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software."] +pub type L1_ICACHE0_FREEZE_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_FREEZE_EN` writer - The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software."] +pub type L1_ICACHE0_FREEZE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_FREEZE_MODE` reader - The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck."] +pub type L1_ICACHE0_FREEZE_MODE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_FREEZE_MODE` writer - The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck."] +pub type L1_ICACHE0_FREEZE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_FREEZE_DONE` reader - The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished."] +pub type L1_ICACHE0_FREEZE_DONE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_FREEZE_EN` reader - The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software."] +pub type L1_ICACHE1_FREEZE_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_FREEZE_EN` writer - The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software."] +pub type L1_ICACHE1_FREEZE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_FREEZE_MODE` reader - The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck."] +pub type L1_ICACHE1_FREEZE_MODE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_FREEZE_MODE` writer - The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck."] +pub type L1_ICACHE1_FREEZE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_FREEZE_DONE` reader - The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished."] +pub type L1_ICACHE1_FREEZE_DONE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_FREEZE_EN` reader - Reserved"] +pub type L1_ICACHE2_FREEZE_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_FREEZE_MODE` reader - Reserved"] +pub type L1_ICACHE2_FREEZE_MODE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_FREEZE_DONE` reader - Reserved"] +pub type L1_ICACHE2_FREEZE_DONE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_FREEZE_EN` reader - Reserved"] +pub type L1_ICACHE3_FREEZE_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_FREEZE_MODE` reader - Reserved"] +pub type L1_ICACHE3_FREEZE_MODE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_FREEZE_DONE` reader - Reserved"] +pub type L1_ICACHE3_FREEZE_DONE_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_FREEZE_EN` reader - The bit is used to enable freeze operation on L1-DCache. It can be cleared by software."] +pub type L1_DCACHE_FREEZE_EN_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_FREEZE_EN` writer - The bit is used to enable freeze operation on L1-DCache. It can be cleared by software."] +pub type L1_DCACHE_FREEZE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_FREEZE_MODE` reader - The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access will not stuck. 1: a miss-access will stuck."] +pub type L1_DCACHE_FREEZE_MODE_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_FREEZE_MODE` writer - The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access will not stuck. 1: a miss-access will stuck."] +pub type L1_DCACHE_FREEZE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_FREEZE_DONE` reader - The bit is used to indicate whether freeze operation on L1-DCache is finished or not. 0: not finished. 1: finished."] +pub type L1_DCACHE_FREEZE_DONE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software."] + #[inline(always)] + pub fn l1_icache0_freeze_en(&self) -> L1_ICACHE0_FREEZE_EN_R { + L1_ICACHE0_FREEZE_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck."] + #[inline(always)] + pub fn l1_icache0_freeze_mode(&self) -> L1_ICACHE0_FREEZE_MODE_R { + L1_ICACHE0_FREEZE_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_icache0_freeze_done(&self) -> L1_ICACHE0_FREEZE_DONE_R { + L1_ICACHE0_FREEZE_DONE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software."] + #[inline(always)] + pub fn l1_icache1_freeze_en(&self) -> L1_ICACHE1_FREEZE_EN_R { + L1_ICACHE1_FREEZE_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck."] + #[inline(always)] + pub fn l1_icache1_freeze_mode(&self) -> L1_ICACHE1_FREEZE_MODE_R { + L1_ICACHE1_FREEZE_MODE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_icache1_freeze_done(&self) -> L1_ICACHE1_FREEZE_DONE_R { + L1_ICACHE1_FREEZE_DONE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn l1_icache2_freeze_en(&self) -> L1_ICACHE2_FREEZE_EN_R { + L1_ICACHE2_FREEZE_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn l1_icache2_freeze_mode(&self) -> L1_ICACHE2_FREEZE_MODE_R { + L1_ICACHE2_FREEZE_MODE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn l1_icache2_freeze_done(&self) -> L1_ICACHE2_FREEZE_DONE_R { + L1_ICACHE2_FREEZE_DONE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn l1_icache3_freeze_en(&self) -> L1_ICACHE3_FREEZE_EN_R { + L1_ICACHE3_FREEZE_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn l1_icache3_freeze_mode(&self) -> L1_ICACHE3_FREEZE_MODE_R { + L1_ICACHE3_FREEZE_MODE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn l1_icache3_freeze_done(&self) -> L1_ICACHE3_FREEZE_DONE_R { + L1_ICACHE3_FREEZE_DONE_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - The bit is used to enable freeze operation on L1-DCache. It can be cleared by software."] + #[inline(always)] + pub fn l1_dcache_freeze_en(&self) -> L1_DCACHE_FREEZE_EN_R { + L1_DCACHE_FREEZE_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access will not stuck. 1: a miss-access will stuck."] + #[inline(always)] + pub fn l1_dcache_freeze_mode(&self) -> L1_DCACHE_FREEZE_MODE_R { + L1_DCACHE_FREEZE_MODE_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The bit is used to indicate whether freeze operation on L1-DCache is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_dcache_freeze_done(&self) -> L1_DCACHE_FREEZE_DONE_R { + L1_DCACHE_FREEZE_DONE_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_FREEZE_CTRL") + .field( + "l1_icache0_freeze_en", + &format_args!("{}", self.l1_icache0_freeze_en().bit()), + ) + .field( + "l1_icache0_freeze_mode", + &format_args!("{}", self.l1_icache0_freeze_mode().bit()), + ) + .field( + "l1_icache0_freeze_done", + &format_args!("{}", self.l1_icache0_freeze_done().bit()), + ) + .field( + "l1_icache1_freeze_en", + &format_args!("{}", self.l1_icache1_freeze_en().bit()), + ) + .field( + "l1_icache1_freeze_mode", + &format_args!("{}", self.l1_icache1_freeze_mode().bit()), + ) + .field( + "l1_icache1_freeze_done", + &format_args!("{}", self.l1_icache1_freeze_done().bit()), + ) + .field( + "l1_icache2_freeze_en", + &format_args!("{}", self.l1_icache2_freeze_en().bit()), + ) + .field( + "l1_icache2_freeze_mode", + &format_args!("{}", self.l1_icache2_freeze_mode().bit()), + ) + .field( + "l1_icache2_freeze_done", + &format_args!("{}", self.l1_icache2_freeze_done().bit()), + ) + .field( + "l1_icache3_freeze_en", + &format_args!("{}", self.l1_icache3_freeze_en().bit()), + ) + .field( + "l1_icache3_freeze_mode", + &format_args!("{}", self.l1_icache3_freeze_mode().bit()), + ) + .field( + "l1_icache3_freeze_done", + &format_args!("{}", self.l1_icache3_freeze_done().bit()), + ) + .field( + "l1_dcache_freeze_en", + &format_args!("{}", self.l1_dcache_freeze_en().bit()), + ) + .field( + "l1_dcache_freeze_mode", + &format_args!("{}", self.l1_dcache_freeze_mode().bit()), + ) + .field( + "l1_dcache_freeze_done", + &format_args!("{}", self.l1_dcache_freeze_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_freeze_en(&mut self) -> L1_ICACHE0_FREEZE_EN_W { + L1_ICACHE0_FREEZE_EN_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_freeze_mode( + &mut self, + ) -> L1_ICACHE0_FREEZE_MODE_W { + L1_ICACHE0_FREEZE_MODE_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_freeze_en(&mut self) -> L1_ICACHE1_FREEZE_EN_W { + L1_ICACHE1_FREEZE_EN_W::new(self, 4) + } + #[doc = "Bit 5 - The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_freeze_mode( + &mut self, + ) -> L1_ICACHE1_FREEZE_MODE_W { + L1_ICACHE1_FREEZE_MODE_W::new(self, 5) + } + #[doc = "Bit 16 - The bit is used to enable freeze operation on L1-DCache. It can be cleared by software."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_freeze_en(&mut self) -> L1_DCACHE_FREEZE_EN_W { + L1_DCACHE_FREEZE_EN_W::new(self, 16) + } + #[doc = "Bit 17 - The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access will not stuck. 1: a miss-access will stuck."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_freeze_mode(&mut self) -> L1_DCACHE_FREEZE_MODE_W { + L1_DCACHE_FREEZE_MODE_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Freeze control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_freeze_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_freeze_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_FREEZE_CTRL_SPEC; +impl crate::RegisterSpec for L1_CACHE_FREEZE_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_freeze_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_FREEZE_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_freeze_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_FREEZE_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_FREEZE_CTRL to value 0"] +impl crate::Resettable for L1_CACHE_FREEZE_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_object_ctrl.rs b/esp32p4/src/cache/l1_cache_object_ctrl.rs new file mode 100644 index 0000000000..edba89d476 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_object_ctrl.rs @@ -0,0 +1,205 @@ +#[doc = "Register `L1_CACHE_OBJECT_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_OBJECT_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_TAG_OBJECT` reader - Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_ICACHE0_TAG_OBJECT_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_TAG_OBJECT` writer - Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_ICACHE0_TAG_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_TAG_OBJECT` reader - Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_ICACHE1_TAG_OBJECT_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_TAG_OBJECT` writer - Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_ICACHE1_TAG_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_TAG_OBJECT` reader - Reserved"] +pub type L1_ICACHE2_TAG_OBJECT_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_TAG_OBJECT` reader - Reserved"] +pub type L1_ICACHE3_TAG_OBJECT_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_TAG_OBJECT` reader - Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_DCACHE_TAG_OBJECT_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_TAG_OBJECT` writer - Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_DCACHE_TAG_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_MEM_OBJECT` reader - Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_ICACHE0_MEM_OBJECT_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_MEM_OBJECT` writer - Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_ICACHE0_MEM_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_MEM_OBJECT` reader - Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_ICACHE1_MEM_OBJECT_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_MEM_OBJECT` writer - Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_ICACHE1_MEM_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_MEM_OBJECT` reader - Reserved"] +pub type L1_ICACHE2_MEM_OBJECT_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_MEM_OBJECT` reader - Reserved"] +pub type L1_ICACHE3_MEM_OBJECT_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_MEM_OBJECT` reader - Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_DCACHE_MEM_OBJECT_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_MEM_OBJECT` writer - Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register."] +pub type L1_DCACHE_MEM_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + pub fn l1_icache0_tag_object(&self) -> L1_ICACHE0_TAG_OBJECT_R { + L1_ICACHE0_TAG_OBJECT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + pub fn l1_icache1_tag_object(&self) -> L1_ICACHE1_TAG_OBJECT_R { + L1_ICACHE1_TAG_OBJECT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_tag_object(&self) -> L1_ICACHE2_TAG_OBJECT_R { + L1_ICACHE2_TAG_OBJECT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_tag_object(&self) -> L1_ICACHE3_TAG_OBJECT_R { + L1_ICACHE3_TAG_OBJECT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + pub fn l1_dcache_tag_object(&self) -> L1_DCACHE_TAG_OBJECT_R { + L1_DCACHE_TAG_OBJECT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + pub fn l1_icache0_mem_object(&self) -> L1_ICACHE0_MEM_OBJECT_R { + L1_ICACHE0_MEM_OBJECT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + pub fn l1_icache1_mem_object(&self) -> L1_ICACHE1_MEM_OBJECT_R { + L1_ICACHE1_MEM_OBJECT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn l1_icache2_mem_object(&self) -> L1_ICACHE2_MEM_OBJECT_R { + L1_ICACHE2_MEM_OBJECT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn l1_icache3_mem_object(&self) -> L1_ICACHE3_MEM_OBJECT_R { + L1_ICACHE3_MEM_OBJECT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + pub fn l1_dcache_mem_object(&self) -> L1_DCACHE_MEM_OBJECT_R { + L1_DCACHE_MEM_OBJECT_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_OBJECT_CTRL") + .field( + "l1_icache0_tag_object", + &format_args!("{}", self.l1_icache0_tag_object().bit()), + ) + .field( + "l1_icache1_tag_object", + &format_args!("{}", self.l1_icache1_tag_object().bit()), + ) + .field( + "l1_icache2_tag_object", + &format_args!("{}", self.l1_icache2_tag_object().bit()), + ) + .field( + "l1_icache3_tag_object", + &format_args!("{}", self.l1_icache3_tag_object().bit()), + ) + .field( + "l1_dcache_tag_object", + &format_args!("{}", self.l1_dcache_tag_object().bit()), + ) + .field( + "l1_icache0_mem_object", + &format_args!("{}", self.l1_icache0_mem_object().bit()), + ) + .field( + "l1_icache1_mem_object", + &format_args!("{}", self.l1_icache1_mem_object().bit()), + ) + .field( + "l1_icache2_mem_object", + &format_args!("{}", self.l1_icache2_mem_object().bit()), + ) + .field( + "l1_icache3_mem_object", + &format_args!("{}", self.l1_icache3_mem_object().bit()), + ) + .field( + "l1_dcache_mem_object", + &format_args!("{}", self.l1_dcache_mem_object().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_tag_object(&mut self) -> L1_ICACHE0_TAG_OBJECT_W { + L1_ICACHE0_TAG_OBJECT_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_tag_object(&mut self) -> L1_ICACHE1_TAG_OBJECT_W { + L1_ICACHE1_TAG_OBJECT_W::new(self, 1) + } + #[doc = "Bit 4 - Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_tag_object(&mut self) -> L1_DCACHE_TAG_OBJECT_W { + L1_DCACHE_TAG_OBJECT_W::new(self, 4) + } + #[doc = "Bit 6 - Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_mem_object(&mut self) -> L1_ICACHE0_MEM_OBJECT_W { + L1_ICACHE0_MEM_OBJECT_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_mem_object(&mut self) -> L1_ICACHE1_MEM_OBJECT_W { + L1_ICACHE1_MEM_OBJECT_W::new(self, 7) + } + #[doc = "Bit 10 - Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_mem_object(&mut self) -> L1_DCACHE_MEM_OBJECT_W { + L1_DCACHE_MEM_OBJECT_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Tag and Data memory Object control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_object_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_object_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_OBJECT_CTRL_SPEC; +impl crate::RegisterSpec for L1_CACHE_OBJECT_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_object_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_OBJECT_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_object_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_OBJECT_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_OBJECT_CTRL to value 0"] +impl crate::Resettable for L1_CACHE_OBJECT_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_preload_rst_ctrl.rs b/esp32p4/src/cache/l1_cache_preload_rst_ctrl.rs new file mode 100644 index 0000000000..3ff69a2929 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_preload_rst_ctrl.rs @@ -0,0 +1,126 @@ +#[doc = "Register `L1_CACHE_PRELOAD_RST_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_PRELOAD_RST_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_PLD_RST` reader - set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] +pub type L1_ICACHE0_PLD_RST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_PLD_RST` writer - set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] +pub type L1_ICACHE0_PLD_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_PLD_RST` reader - set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] +pub type L1_ICACHE1_PLD_RST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PLD_RST` writer - set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] +pub type L1_ICACHE1_PLD_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_PLD_RST` reader - Reserved"] +pub type L1_ICACHE2_PLD_RST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PLD_RST` reader - Reserved"] +pub type L1_ICACHE3_PLD_RST_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_RST` reader - set this bit to reset preload-logic inside L1-DCache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] +pub type L1_DCACHE_PLD_RST_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_RST` writer - set this bit to reset preload-logic inside L1-DCache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] +pub type L1_DCACHE_PLD_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] + #[inline(always)] + pub fn l1_icache0_pld_rst(&self) -> L1_ICACHE0_PLD_RST_R { + L1_ICACHE0_PLD_RST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] + #[inline(always)] + pub fn l1_icache1_pld_rst(&self) -> L1_ICACHE1_PLD_RST_R { + L1_ICACHE1_PLD_RST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_pld_rst(&self) -> L1_ICACHE2_PLD_RST_R { + L1_ICACHE2_PLD_RST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_pld_rst(&self) -> L1_ICACHE3_PLD_RST_R { + L1_ICACHE3_PLD_RST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - set this bit to reset preload-logic inside L1-DCache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] + #[inline(always)] + pub fn l1_dcache_pld_rst(&self) -> L1_DCACHE_PLD_RST_R { + L1_DCACHE_PLD_RST_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_PRELOAD_RST_CTRL") + .field( + "l1_icache0_pld_rst", + &format_args!("{}", self.l1_icache0_pld_rst().bit()), + ) + .field( + "l1_icache1_pld_rst", + &format_args!("{}", self.l1_icache1_pld_rst().bit()), + ) + .field( + "l1_icache2_pld_rst", + &format_args!("{}", self.l1_icache2_pld_rst().bit()), + ) + .field( + "l1_icache3_pld_rst", + &format_args!("{}", self.l1_icache3_pld_rst().bit()), + ) + .field( + "l1_dcache_pld_rst", + &format_args!("{}", self.l1_dcache_pld_rst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_pld_rst(&mut self) -> L1_ICACHE0_PLD_RST_W { + L1_ICACHE0_PLD_RST_W::new(self, 0) + } + #[doc = "Bit 1 - set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_pld_rst(&mut self) -> L1_ICACHE1_PLD_RST_W { + L1_ICACHE1_PLD_RST_W::new(self, 1) + } + #[doc = "Bit 4 - set this bit to reset preload-logic inside L1-DCache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_pld_rst(&mut self) -> L1_DCACHE_PLD_RST_W { + L1_DCACHE_PLD_RST_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Preload Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_preload_rst_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_preload_rst_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_PRELOAD_RST_CTRL_SPEC; +impl crate::RegisterSpec for L1_CACHE_PRELOAD_RST_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_preload_rst_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_PRELOAD_RST_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_preload_rst_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_PRELOAD_RST_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_PRELOAD_RST_CTRL to value 0"] +impl crate::Resettable for L1_CACHE_PRELOAD_RST_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_sync_rst_ctrl.rs b/esp32p4/src/cache/l1_cache_sync_rst_ctrl.rs new file mode 100644 index 0000000000..4627ff02fe --- /dev/null +++ b/esp32p4/src/cache/l1_cache_sync_rst_ctrl.rs @@ -0,0 +1,126 @@ +#[doc = "Register `L1_CACHE_SYNC_RST_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_SYNC_RST_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_SYNC_RST` reader - set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] +pub type L1_ICACHE0_SYNC_RST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_SYNC_RST` writer - set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] +pub type L1_ICACHE0_SYNC_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_SYNC_RST` reader - set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] +pub type L1_ICACHE1_SYNC_RST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_SYNC_RST` writer - set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] +pub type L1_ICACHE1_SYNC_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_SYNC_RST` reader - Reserved"] +pub type L1_ICACHE2_SYNC_RST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_SYNC_RST` reader - Reserved"] +pub type L1_ICACHE3_SYNC_RST_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_SYNC_RST` reader - set this bit to reset sync-logic inside L1-DCache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] +pub type L1_DCACHE_SYNC_RST_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_SYNC_RST` writer - set this bit to reset sync-logic inside L1-DCache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] +pub type L1_DCACHE_SYNC_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] + #[inline(always)] + pub fn l1_icache0_sync_rst(&self) -> L1_ICACHE0_SYNC_RST_R { + L1_ICACHE0_SYNC_RST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] + #[inline(always)] + pub fn l1_icache1_sync_rst(&self) -> L1_ICACHE1_SYNC_RST_R { + L1_ICACHE1_SYNC_RST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_sync_rst(&self) -> L1_ICACHE2_SYNC_RST_R { + L1_ICACHE2_SYNC_RST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_sync_rst(&self) -> L1_ICACHE3_SYNC_RST_R { + L1_ICACHE3_SYNC_RST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - set this bit to reset sync-logic inside L1-DCache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] + #[inline(always)] + pub fn l1_dcache_sync_rst(&self) -> L1_DCACHE_SYNC_RST_R { + L1_DCACHE_SYNC_RST_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_SYNC_RST_CTRL") + .field( + "l1_icache0_sync_rst", + &format_args!("{}", self.l1_icache0_sync_rst().bit()), + ) + .field( + "l1_icache1_sync_rst", + &format_args!("{}", self.l1_icache1_sync_rst().bit()), + ) + .field( + "l1_icache2_sync_rst", + &format_args!("{}", self.l1_icache2_sync_rst().bit()), + ) + .field( + "l1_icache3_sync_rst", + &format_args!("{}", self.l1_icache3_sync_rst().bit()), + ) + .field( + "l1_dcache_sync_rst", + &format_args!("{}", self.l1_dcache_sync_rst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_sync_rst(&mut self) -> L1_ICACHE0_SYNC_RST_W { + L1_ICACHE0_SYNC_RST_W::new(self, 0) + } + #[doc = "Bit 1 - set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_sync_rst(&mut self) -> L1_ICACHE1_SYNC_RST_W { + L1_ICACHE1_SYNC_RST_W::new(self, 1) + } + #[doc = "Bit 4 - set this bit to reset sync-logic inside L1-DCache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_sync_rst(&mut self) -> L1_DCACHE_SYNC_RST_W { + L1_DCACHE_SYNC_RST_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Sync Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_sync_rst_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_sync_rst_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_SYNC_RST_CTRL_SPEC; +impl crate::RegisterSpec for L1_CACHE_SYNC_RST_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_sync_rst_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_SYNC_RST_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_sync_rst_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_SYNC_RST_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_SYNC_RST_CTRL to value 0"] +impl crate::Resettable for L1_CACHE_SYNC_RST_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_tag_mem_acs_conf.rs b/esp32p4/src/cache/l1_cache_tag_mem_acs_conf.rs new file mode 100644 index 0000000000..5ef937fb82 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_tag_mem_acs_conf.rs @@ -0,0 +1,217 @@ +#[doc = "Register `L1_CACHE_TAG_MEM_ACS_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_TAG_MEM_ACS_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_TAG_MEM_RD_EN` reader - The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE0_TAG_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_TAG_MEM_RD_EN` writer - The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE0_TAG_MEM_RD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_TAG_MEM_WR_EN` reader - The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE0_TAG_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_TAG_MEM_WR_EN` writer - The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE0_TAG_MEM_WR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_TAG_MEM_RD_EN` reader - The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE1_TAG_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_TAG_MEM_RD_EN` writer - The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE1_TAG_MEM_RD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_TAG_MEM_WR_EN` reader - The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE1_TAG_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_TAG_MEM_WR_EN` writer - The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable."] +pub type L1_ICACHE1_TAG_MEM_WR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_TAG_MEM_RD_EN` reader - Reserved"] +pub type L1_ICACHE2_TAG_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_TAG_MEM_WR_EN` reader - Reserved"] +pub type L1_ICACHE2_TAG_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_TAG_MEM_RD_EN` reader - Reserved"] +pub type L1_ICACHE3_TAG_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_TAG_MEM_WR_EN` reader - Reserved"] +pub type L1_ICACHE3_TAG_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_TAG_MEM_RD_EN` reader - The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1: enable."] +pub type L1_DCACHE_TAG_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_TAG_MEM_RD_EN` writer - The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1: enable."] +pub type L1_DCACHE_TAG_MEM_RD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_TAG_MEM_WR_EN` reader - The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1: enable."] +pub type L1_DCACHE_TAG_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_TAG_MEM_WR_EN` writer - The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1: enable."] +pub type L1_DCACHE_TAG_MEM_WR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_icache0_tag_mem_rd_en(&self) -> L1_ICACHE0_TAG_MEM_RD_EN_R { + L1_ICACHE0_TAG_MEM_RD_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_icache0_tag_mem_wr_en(&self) -> L1_ICACHE0_TAG_MEM_WR_EN_R { + L1_ICACHE0_TAG_MEM_WR_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_icache1_tag_mem_rd_en(&self) -> L1_ICACHE1_TAG_MEM_RD_EN_R { + L1_ICACHE1_TAG_MEM_RD_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_icache1_tag_mem_wr_en(&self) -> L1_ICACHE1_TAG_MEM_WR_EN_R { + L1_ICACHE1_TAG_MEM_WR_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn l1_icache2_tag_mem_rd_en(&self) -> L1_ICACHE2_TAG_MEM_RD_EN_R { + L1_ICACHE2_TAG_MEM_RD_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn l1_icache2_tag_mem_wr_en(&self) -> L1_ICACHE2_TAG_MEM_WR_EN_R { + L1_ICACHE2_TAG_MEM_WR_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn l1_icache3_tag_mem_rd_en(&self) -> L1_ICACHE3_TAG_MEM_RD_EN_R { + L1_ICACHE3_TAG_MEM_RD_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn l1_icache3_tag_mem_wr_en(&self) -> L1_ICACHE3_TAG_MEM_WR_EN_R { + L1_ICACHE3_TAG_MEM_WR_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 16 - The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_dcache_tag_mem_rd_en(&self) -> L1_DCACHE_TAG_MEM_RD_EN_R { + L1_DCACHE_TAG_MEM_RD_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l1_dcache_tag_mem_wr_en(&self) -> L1_DCACHE_TAG_MEM_WR_EN_R { + L1_DCACHE_TAG_MEM_WR_EN_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_TAG_MEM_ACS_CONF") + .field( + "l1_icache0_tag_mem_rd_en", + &format_args!("{}", self.l1_icache0_tag_mem_rd_en().bit()), + ) + .field( + "l1_icache0_tag_mem_wr_en", + &format_args!("{}", self.l1_icache0_tag_mem_wr_en().bit()), + ) + .field( + "l1_icache1_tag_mem_rd_en", + &format_args!("{}", self.l1_icache1_tag_mem_rd_en().bit()), + ) + .field( + "l1_icache1_tag_mem_wr_en", + &format_args!("{}", self.l1_icache1_tag_mem_wr_en().bit()), + ) + .field( + "l1_icache2_tag_mem_rd_en", + &format_args!("{}", self.l1_icache2_tag_mem_rd_en().bit()), + ) + .field( + "l1_icache2_tag_mem_wr_en", + &format_args!("{}", self.l1_icache2_tag_mem_wr_en().bit()), + ) + .field( + "l1_icache3_tag_mem_rd_en", + &format_args!("{}", self.l1_icache3_tag_mem_rd_en().bit()), + ) + .field( + "l1_icache3_tag_mem_wr_en", + &format_args!("{}", self.l1_icache3_tag_mem_wr_en().bit()), + ) + .field( + "l1_dcache_tag_mem_rd_en", + &format_args!("{}", self.l1_dcache_tag_mem_rd_en().bit()), + ) + .field( + "l1_dcache_tag_mem_wr_en", + &format_args!("{}", self.l1_dcache_tag_mem_wr_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_tag_mem_rd_en( + &mut self, + ) -> L1_ICACHE0_TAG_MEM_RD_EN_W { + L1_ICACHE0_TAG_MEM_RD_EN_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_tag_mem_wr_en( + &mut self, + ) -> L1_ICACHE0_TAG_MEM_WR_EN_W { + L1_ICACHE0_TAG_MEM_WR_EN_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_tag_mem_rd_en( + &mut self, + ) -> L1_ICACHE1_TAG_MEM_RD_EN_W { + L1_ICACHE1_TAG_MEM_RD_EN_W::new(self, 4) + } + #[doc = "Bit 5 - The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_tag_mem_wr_en( + &mut self, + ) -> L1_ICACHE1_TAG_MEM_WR_EN_W { + L1_ICACHE1_TAG_MEM_WR_EN_W::new(self, 5) + } + #[doc = "Bit 16 - The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_tag_mem_rd_en( + &mut self, + ) -> L1_DCACHE_TAG_MEM_RD_EN_W { + L1_DCACHE_TAG_MEM_RD_EN_W::new(self, 16) + } + #[doc = "Bit 17 - The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_tag_mem_wr_en( + &mut self, + ) -> L1_DCACHE_TAG_MEM_WR_EN_W { + L1_DCACHE_TAG_MEM_WR_EN_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache tag memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_tag_mem_acs_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_tag_mem_acs_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_TAG_MEM_ACS_CONF_SPEC; +impl crate::RegisterSpec for L1_CACHE_TAG_MEM_ACS_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_tag_mem_acs_conf::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_TAG_MEM_ACS_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_tag_mem_acs_conf::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_TAG_MEM_ACS_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_TAG_MEM_ACS_CONF to value 0x0003_3333"] +impl crate::Resettable for L1_CACHE_TAG_MEM_ACS_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0003_3333; +} diff --git a/esp32p4/src/cache/l1_cache_tag_mem_power_ctrl.rs b/esp32p4/src/cache/l1_cache_tag_mem_power_ctrl.rs new file mode 100644 index 0000000000..154252e8ee --- /dev/null +++ b/esp32p4/src/cache/l1_cache_tag_mem_power_ctrl.rs @@ -0,0 +1,302 @@ +#[doc = "Register `L1_CACHE_TAG_MEM_POWER_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_TAG_MEM_POWER_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_TAG_MEM_FORCE_ON` reader - The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating."] +pub type L1_ICACHE0_TAG_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_TAG_MEM_FORCE_ON` writer - The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating."] +pub type L1_ICACHE0_TAG_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_TAG_MEM_FORCE_PD` reader - The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_ICACHE0_TAG_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_TAG_MEM_FORCE_PD` writer - The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_ICACHE0_TAG_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_TAG_MEM_FORCE_PU` reader - The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_ICACHE0_TAG_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_TAG_MEM_FORCE_PU` writer - The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_ICACHE0_TAG_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_TAG_MEM_FORCE_ON` reader - The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating."] +pub type L1_ICACHE1_TAG_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_TAG_MEM_FORCE_ON` writer - The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating."] +pub type L1_ICACHE1_TAG_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_TAG_MEM_FORCE_PD` reader - The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_ICACHE1_TAG_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_TAG_MEM_FORCE_PD` writer - The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_ICACHE1_TAG_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_TAG_MEM_FORCE_PU` reader - The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_ICACHE1_TAG_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_TAG_MEM_FORCE_PU` writer - The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_ICACHE1_TAG_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_TAG_MEM_FORCE_ON` reader - Reserved"] +pub type L1_ICACHE2_TAG_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_TAG_MEM_FORCE_PD` reader - Reserved"] +pub type L1_ICACHE2_TAG_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_TAG_MEM_FORCE_PU` reader - Reserved"] +pub type L1_ICACHE2_TAG_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_TAG_MEM_FORCE_ON` reader - Reserved"] +pub type L1_ICACHE3_TAG_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_TAG_MEM_FORCE_PD` reader - Reserved"] +pub type L1_ICACHE3_TAG_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_TAG_MEM_FORCE_PU` reader - Reserved"] +pub type L1_ICACHE3_TAG_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_TAG_MEM_FORCE_ON` reader - The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, 0: open clock gating."] +pub type L1_DCACHE_TAG_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_TAG_MEM_FORCE_ON` writer - The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, 0: open clock gating."] +pub type L1_DCACHE_TAG_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_TAG_MEM_FORCE_PD` reader - The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_DCACHE_TAG_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_TAG_MEM_FORCE_PD` writer - The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power down"] +pub type L1_DCACHE_TAG_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_TAG_MEM_FORCE_PU` reader - The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_DCACHE_TAG_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_TAG_MEM_FORCE_PU` writer - The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up"] +pub type L1_DCACHE_TAG_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + pub fn l1_icache0_tag_mem_force_on(&self) -> L1_ICACHE0_TAG_MEM_FORCE_ON_R { + L1_ICACHE0_TAG_MEM_FORCE_ON_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + pub fn l1_icache0_tag_mem_force_pd(&self) -> L1_ICACHE0_TAG_MEM_FORCE_PD_R { + L1_ICACHE0_TAG_MEM_FORCE_PD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + pub fn l1_icache0_tag_mem_force_pu(&self) -> L1_ICACHE0_TAG_MEM_FORCE_PU_R { + L1_ICACHE0_TAG_MEM_FORCE_PU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + pub fn l1_icache1_tag_mem_force_on(&self) -> L1_ICACHE1_TAG_MEM_FORCE_ON_R { + L1_ICACHE1_TAG_MEM_FORCE_ON_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + pub fn l1_icache1_tag_mem_force_pd(&self) -> L1_ICACHE1_TAG_MEM_FORCE_PD_R { + L1_ICACHE1_TAG_MEM_FORCE_PD_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + pub fn l1_icache1_tag_mem_force_pu(&self) -> L1_ICACHE1_TAG_MEM_FORCE_PU_R { + L1_ICACHE1_TAG_MEM_FORCE_PU_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn l1_icache2_tag_mem_force_on(&self) -> L1_ICACHE2_TAG_MEM_FORCE_ON_R { + L1_ICACHE2_TAG_MEM_FORCE_ON_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn l1_icache2_tag_mem_force_pd(&self) -> L1_ICACHE2_TAG_MEM_FORCE_PD_R { + L1_ICACHE2_TAG_MEM_FORCE_PD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn l1_icache2_tag_mem_force_pu(&self) -> L1_ICACHE2_TAG_MEM_FORCE_PU_R { + L1_ICACHE2_TAG_MEM_FORCE_PU_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn l1_icache3_tag_mem_force_on(&self) -> L1_ICACHE3_TAG_MEM_FORCE_ON_R { + L1_ICACHE3_TAG_MEM_FORCE_ON_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn l1_icache3_tag_mem_force_pd(&self) -> L1_ICACHE3_TAG_MEM_FORCE_PD_R { + L1_ICACHE3_TAG_MEM_FORCE_PD_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn l1_icache3_tag_mem_force_pu(&self) -> L1_ICACHE3_TAG_MEM_FORCE_PU_R { + L1_ICACHE3_TAG_MEM_FORCE_PU_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + pub fn l1_dcache_tag_mem_force_on(&self) -> L1_DCACHE_TAG_MEM_FORCE_ON_R { + L1_DCACHE_TAG_MEM_FORCE_ON_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + pub fn l1_dcache_tag_mem_force_pd(&self) -> L1_DCACHE_TAG_MEM_FORCE_PD_R { + L1_DCACHE_TAG_MEM_FORCE_PD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + pub fn l1_dcache_tag_mem_force_pu(&self) -> L1_DCACHE_TAG_MEM_FORCE_PU_R { + L1_DCACHE_TAG_MEM_FORCE_PU_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_TAG_MEM_POWER_CTRL") + .field( + "l1_icache0_tag_mem_force_on", + &format_args!("{}", self.l1_icache0_tag_mem_force_on().bit()), + ) + .field( + "l1_icache0_tag_mem_force_pd", + &format_args!("{}", self.l1_icache0_tag_mem_force_pd().bit()), + ) + .field( + "l1_icache0_tag_mem_force_pu", + &format_args!("{}", self.l1_icache0_tag_mem_force_pu().bit()), + ) + .field( + "l1_icache1_tag_mem_force_on", + &format_args!("{}", self.l1_icache1_tag_mem_force_on().bit()), + ) + .field( + "l1_icache1_tag_mem_force_pd", + &format_args!("{}", self.l1_icache1_tag_mem_force_pd().bit()), + ) + .field( + "l1_icache1_tag_mem_force_pu", + &format_args!("{}", self.l1_icache1_tag_mem_force_pu().bit()), + ) + .field( + "l1_icache2_tag_mem_force_on", + &format_args!("{}", self.l1_icache2_tag_mem_force_on().bit()), + ) + .field( + "l1_icache2_tag_mem_force_pd", + &format_args!("{}", self.l1_icache2_tag_mem_force_pd().bit()), + ) + .field( + "l1_icache2_tag_mem_force_pu", + &format_args!("{}", self.l1_icache2_tag_mem_force_pu().bit()), + ) + .field( + "l1_icache3_tag_mem_force_on", + &format_args!("{}", self.l1_icache3_tag_mem_force_on().bit()), + ) + .field( + "l1_icache3_tag_mem_force_pd", + &format_args!("{}", self.l1_icache3_tag_mem_force_pd().bit()), + ) + .field( + "l1_icache3_tag_mem_force_pu", + &format_args!("{}", self.l1_icache3_tag_mem_force_pu().bit()), + ) + .field( + "l1_dcache_tag_mem_force_on", + &format_args!("{}", self.l1_dcache_tag_mem_force_on().bit()), + ) + .field( + "l1_dcache_tag_mem_force_pd", + &format_args!("{}", self.l1_dcache_tag_mem_force_pd().bit()), + ) + .field( + "l1_dcache_tag_mem_force_pu", + &format_args!("{}", self.l1_dcache_tag_mem_force_pu().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_tag_mem_force_on( + &mut self, + ) -> L1_ICACHE0_TAG_MEM_FORCE_ON_W { + L1_ICACHE0_TAG_MEM_FORCE_ON_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + #[must_use] + pub fn l1_icache0_tag_mem_force_pd( + &mut self, + ) -> L1_ICACHE0_TAG_MEM_FORCE_PD_W { + L1_ICACHE0_TAG_MEM_FORCE_PD_W::new(self, 1) + } + #[doc = "Bit 2 - The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + #[must_use] + pub fn l1_icache0_tag_mem_force_pu( + &mut self, + ) -> L1_ICACHE0_TAG_MEM_FORCE_PU_W { + L1_ICACHE0_TAG_MEM_FORCE_PU_W::new(self, 2) + } + #[doc = "Bit 4 - The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_tag_mem_force_on( + &mut self, + ) -> L1_ICACHE1_TAG_MEM_FORCE_ON_W { + L1_ICACHE1_TAG_MEM_FORCE_ON_W::new(self, 4) + } + #[doc = "Bit 5 - The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + #[must_use] + pub fn l1_icache1_tag_mem_force_pd( + &mut self, + ) -> L1_ICACHE1_TAG_MEM_FORCE_PD_W { + L1_ICACHE1_TAG_MEM_FORCE_PD_W::new(self, 5) + } + #[doc = "Bit 6 - The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + #[must_use] + pub fn l1_icache1_tag_mem_force_pu( + &mut self, + ) -> L1_ICACHE1_TAG_MEM_FORCE_PU_W { + L1_ICACHE1_TAG_MEM_FORCE_PU_W::new(self, 6) + } + #[doc = "Bit 16 - The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_tag_mem_force_on( + &mut self, + ) -> L1_DCACHE_TAG_MEM_FORCE_ON_W { + L1_DCACHE_TAG_MEM_FORCE_ON_W::new(self, 16) + } + #[doc = "Bit 17 - The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_tag_mem_force_pd( + &mut self, + ) -> L1_DCACHE_TAG_MEM_FORCE_PD_W { + L1_DCACHE_TAG_MEM_FORCE_PD_W::new(self, 17) + } + #[doc = "Bit 18 - The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_tag_mem_force_pu( + &mut self, + ) -> L1_DCACHE_TAG_MEM_FORCE_PU_W { + L1_DCACHE_TAG_MEM_FORCE_PU_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache tag memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_tag_mem_power_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_tag_mem_power_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_TAG_MEM_POWER_CTRL_SPEC; +impl crate::RegisterSpec for L1_CACHE_TAG_MEM_POWER_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_tag_mem_power_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_TAG_MEM_POWER_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_tag_mem_power_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_TAG_MEM_POWER_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_TAG_MEM_POWER_CTRL to value 0x0005_5555"] +impl crate::Resettable for L1_CACHE_TAG_MEM_POWER_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0005_5555; +} diff --git a/esp32p4/src/cache/l1_cache_vaddr.rs b/esp32p4/src/cache/l1_cache_vaddr.rs new file mode 100644 index 0000000000..0425383d90 --- /dev/null +++ b/esp32p4/src/cache/l1_cache_vaddr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L1_CACHE_VADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_VADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_CACHE_VADDR` reader - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."] +pub type L1_CACHE_VADDR_R = crate::FieldReader; +#[doc = "Field `L1_CACHE_VADDR` writer - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."] +pub type L1_CACHE_VADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."] + #[inline(always)] + pub fn l1_cache_vaddr(&self) -> L1_CACHE_VADDR_R { + L1_CACHE_VADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_VADDR") + .field( + "l1_cache_vaddr", + &format_args!("{}", self.l1_cache_vaddr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."] + #[inline(always)] + #[must_use] + pub fn l1_cache_vaddr(&mut self) -> L1_CACHE_VADDR_W { + L1_CACHE_VADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Vaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_vaddr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_vaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_VADDR_SPEC; +impl crate::RegisterSpec for L1_CACHE_VADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_vaddr::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_VADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_vaddr::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_VADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_VADDR to value 0x4000_0000"] +impl crate::Resettable for L1_CACHE_VADDR_SPEC { + const RESET_VALUE: Self::Ux = 0x4000_0000; +} diff --git a/esp32p4/src/cache/l1_cache_way_object.rs b/esp32p4/src/cache/l1_cache_way_object.rs new file mode 100644 index 0000000000..8af91e910a --- /dev/null +++ b/esp32p4/src/cache/l1_cache_way_object.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L1_CACHE_WAY_OBJECT` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_WAY_OBJECT` writer"] +pub type W = crate::W; +#[doc = "Field `L1_CACHE_WAY_OBJECT` reader - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."] +pub type L1_CACHE_WAY_OBJECT_R = crate::FieldReader; +#[doc = "Field `L1_CACHE_WAY_OBJECT` writer - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."] +pub type L1_CACHE_WAY_OBJECT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."] + #[inline(always)] + pub fn l1_cache_way_object(&self) -> L1_CACHE_WAY_OBJECT_R { + L1_CACHE_WAY_OBJECT_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_WAY_OBJECT") + .field( + "l1_cache_way_object", + &format_args!("{}", self.l1_cache_way_object().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."] + #[inline(always)] + #[must_use] + pub fn l1_cache_way_object(&mut self) -> L1_CACHE_WAY_OBJECT_W { + L1_CACHE_WAY_OBJECT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Tag and Data memory way register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_way_object::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_way_object::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_WAY_OBJECT_SPEC; +impl crate::RegisterSpec for L1_CACHE_WAY_OBJECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_way_object::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_WAY_OBJECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_way_object::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_WAY_OBJECT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_WAY_OBJECT to value 0"] +impl crate::Resettable for L1_CACHE_WAY_OBJECT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_cache_wrap_around_ctrl.rs b/esp32p4/src/cache/l1_cache_wrap_around_ctrl.rs new file mode 100644 index 0000000000..eb9708c61c --- /dev/null +++ b/esp32p4/src/cache/l1_cache_wrap_around_ctrl.rs @@ -0,0 +1,126 @@ +#[doc = "Register `L1_CACHE_WRAP_AROUND_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_CACHE_WRAP_AROUND_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_WRAP` reader - Set this bit as 1 to enable L1-ICache0 wrap around mode."] +pub type L1_ICACHE0_WRAP_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_WRAP` writer - Set this bit as 1 to enable L1-ICache0 wrap around mode."] +pub type L1_ICACHE0_WRAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_WRAP` reader - Set this bit as 1 to enable L1-ICache1 wrap around mode."] +pub type L1_ICACHE1_WRAP_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_WRAP` writer - Set this bit as 1 to enable L1-ICache1 wrap around mode."] +pub type L1_ICACHE1_WRAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_WRAP` reader - Reserved"] +pub type L1_ICACHE2_WRAP_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_WRAP` reader - Reserved"] +pub type L1_ICACHE3_WRAP_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_WRAP` reader - Set this bit as 1 to enable L1-DCache wrap around mode."] +pub type L1_DCACHE_WRAP_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_WRAP` writer - Set this bit as 1 to enable L1-DCache wrap around mode."] +pub type L1_DCACHE_WRAP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit as 1 to enable L1-ICache0 wrap around mode."] + #[inline(always)] + pub fn l1_icache0_wrap(&self) -> L1_ICACHE0_WRAP_R { + L1_ICACHE0_WRAP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit as 1 to enable L1-ICache1 wrap around mode."] + #[inline(always)] + pub fn l1_icache1_wrap(&self) -> L1_ICACHE1_WRAP_R { + L1_ICACHE1_WRAP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_wrap(&self) -> L1_ICACHE2_WRAP_R { + L1_ICACHE2_WRAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_wrap(&self) -> L1_ICACHE3_WRAP_R { + L1_ICACHE3_WRAP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit as 1 to enable L1-DCache wrap around mode."] + #[inline(always)] + pub fn l1_dcache_wrap(&self) -> L1_DCACHE_WRAP_R { + L1_DCACHE_WRAP_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_CACHE_WRAP_AROUND_CTRL") + .field( + "l1_icache0_wrap", + &format_args!("{}", self.l1_icache0_wrap().bit()), + ) + .field( + "l1_icache1_wrap", + &format_args!("{}", self.l1_icache1_wrap().bit()), + ) + .field( + "l1_icache2_wrap", + &format_args!("{}", self.l1_icache2_wrap().bit()), + ) + .field( + "l1_icache3_wrap", + &format_args!("{}", self.l1_icache3_wrap().bit()), + ) + .field( + "l1_dcache_wrap", + &format_args!("{}", self.l1_dcache_wrap().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit as 1 to enable L1-ICache0 wrap around mode."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_wrap(&mut self) -> L1_ICACHE0_WRAP_W { + L1_ICACHE0_WRAP_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit as 1 to enable L1-ICache1 wrap around mode."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_wrap(&mut self) -> L1_ICACHE1_WRAP_W { + L1_ICACHE1_WRAP_W::new(self, 1) + } + #[doc = "Bit 4 - Set this bit as 1 to enable L1-DCache wrap around mode."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_wrap(&mut self) -> L1_DCACHE_WRAP_W { + L1_DCACHE_WRAP_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache wrap around control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_wrap_around_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_cache_wrap_around_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_CACHE_WRAP_AROUND_CTRL_SPEC; +impl crate::RegisterSpec for L1_CACHE_WRAP_AROUND_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_cache_wrap_around_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_CACHE_WRAP_AROUND_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_cache_wrap_around_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_CACHE_WRAP_AROUND_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_CACHE_WRAP_AROUND_CTRL to value 0"] +impl crate::Resettable for L1_CACHE_WRAP_AROUND_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus0_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_dbus0_acs_conflict_cnt.rs new file mode 100644 index 0000000000..bd806f1e41 --- /dev/null +++ b/esp32p4/src/cache/l1_dbus0_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS0_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS0_CONFLICT_CNT` reader - The register records the number of access-conflicts when bus0 accesses L1-DCache."] +pub type L1_DBUS0_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when bus0 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus0_conflict_cnt(&self) -> L1_DBUS0_CONFLICT_CNT_R { + L1_DBUS0_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS0_ACS_CONFLICT_CNT") + .field( + "l1_dbus0_conflict_cnt", + &format_args!("{}", self.l1_dbus0_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS0_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS0_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus0_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS0_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS0_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L1_DBUS0_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus0_acs_hit_cnt.rs b/esp32p4/src/cache/l1_dbus0_acs_hit_cnt.rs new file mode 100644 index 0000000000..887286f0b3 --- /dev/null +++ b/esp32p4/src/cache/l1_dbus0_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS0_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS0_HIT_CNT` reader - The register records the number of hits when bus0 accesses L1-DCache."] +pub type L1_DBUS0_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when bus0 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus0_hit_cnt(&self) -> L1_DBUS0_HIT_CNT_R { + L1_DBUS0_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS0_ACS_HIT_CNT") + .field( + "l1_dbus0_hit_cnt", + &format_args!("{}", self.l1_dbus0_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS0_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS0_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus0_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS0_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS0_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L1_DBUS0_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus0_acs_miss_cnt.rs b/esp32p4/src/cache/l1_dbus0_acs_miss_cnt.rs new file mode 100644 index 0000000000..36dfcd51bf --- /dev/null +++ b/esp32p4/src/cache/l1_dbus0_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS0_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS0_MISS_CNT` reader - The register records the number of missing when bus0 accesses L1-DCache."] +pub type L1_DBUS0_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when bus0 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus0_miss_cnt(&self) -> L1_DBUS0_MISS_CNT_R { + L1_DBUS0_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS0_ACS_MISS_CNT") + .field( + "l1_dbus0_miss_cnt", + &format_args!("{}", self.l1_dbus0_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS0_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS0_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus0_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS0_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS0_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L1_DBUS0_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..2f7119a70c --- /dev/null +++ b/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS0_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS0_NXTLVL_RD_CNT` reader - The register records the number of times that L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache."] +pub type L1_DBUS0_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache."] + #[inline(always)] + pub fn l1_dbus0_nxtlvl_rd_cnt(&self) -> L1_DBUS0_NXTLVL_RD_CNT_R { + L1_DBUS0_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS0_ACS_NXTLVL_RD_CNT") + .field( + "l1_dbus0_nxtlvl_rd_cnt", + &format_args!("{}", self.l1_dbus0_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS0_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS0_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus0_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS0_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS0_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L1_DBUS0_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_wr_cnt.rs new file mode 100644 index 0000000000..c2f2d92eae --- /dev/null +++ b/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_wr_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS0_ACS_NXTLVL_WR_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS0_NXTLVL_WR_CNT` reader - The register records the number of write back when bus0 accesses L1-DCache."] +pub type L1_DBUS0_NXTLVL_WR_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of write back when bus0 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus0_nxtlvl_wr_cnt(&self) -> L1_DBUS0_NXTLVL_WR_CNT_R { + L1_DBUS0_NXTLVL_WR_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS0_ACS_NXTLVL_WR_CNT") + .field( + "l1_dbus0_nxtlvl_wr_cnt", + &format_args!("{}", self.l1_dbus0_nxtlvl_wr_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus0 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_nxtlvl_wr_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS0_ACS_NXTLVL_WR_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS0_ACS_NXTLVL_WR_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus0_acs_nxtlvl_wr_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS0_ACS_NXTLVL_WR_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS0_ACS_NXTLVL_WR_CNT to value 0"] +impl crate::Resettable for L1_DBUS0_ACS_NXTLVL_WR_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus1_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_dbus1_acs_conflict_cnt.rs new file mode 100644 index 0000000000..f5edae3d57 --- /dev/null +++ b/esp32p4/src/cache/l1_dbus1_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS1_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS1_CONFLICT_CNT` reader - The register records the number of access-conflicts when bus1 accesses L1-DCache."] +pub type L1_DBUS1_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when bus1 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus1_conflict_cnt(&self) -> L1_DBUS1_CONFLICT_CNT_R { + L1_DBUS1_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS1_ACS_CONFLICT_CNT") + .field( + "l1_dbus1_conflict_cnt", + &format_args!("{}", self.l1_dbus1_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS1_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS1_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus1_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS1_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS1_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L1_DBUS1_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus1_acs_hit_cnt.rs b/esp32p4/src/cache/l1_dbus1_acs_hit_cnt.rs new file mode 100644 index 0000000000..6023f4d11d --- /dev/null +++ b/esp32p4/src/cache/l1_dbus1_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS1_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS1_HIT_CNT` reader - The register records the number of hits when bus1 accesses L1-DCache."] +pub type L1_DBUS1_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when bus1 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus1_hit_cnt(&self) -> L1_DBUS1_HIT_CNT_R { + L1_DBUS1_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS1_ACS_HIT_CNT") + .field( + "l1_dbus1_hit_cnt", + &format_args!("{}", self.l1_dbus1_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS1_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS1_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus1_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS1_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS1_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L1_DBUS1_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus1_acs_miss_cnt.rs b/esp32p4/src/cache/l1_dbus1_acs_miss_cnt.rs new file mode 100644 index 0000000000..c0b82fb984 --- /dev/null +++ b/esp32p4/src/cache/l1_dbus1_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS1_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS1_MISS_CNT` reader - The register records the number of missing when bus1 accesses L1-DCache."] +pub type L1_DBUS1_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when bus1 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus1_miss_cnt(&self) -> L1_DBUS1_MISS_CNT_R { + L1_DBUS1_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS1_ACS_MISS_CNT") + .field( + "l1_dbus1_miss_cnt", + &format_args!("{}", self.l1_dbus1_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS1_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS1_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus1_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS1_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS1_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L1_DBUS1_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..1f5d58c8ad --- /dev/null +++ b/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS1_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS1_NXTLVL_RD_CNT` reader - The register records the number of times that L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache."] +pub type L1_DBUS1_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache."] + #[inline(always)] + pub fn l1_dbus1_nxtlvl_rd_cnt(&self) -> L1_DBUS1_NXTLVL_RD_CNT_R { + L1_DBUS1_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS1_ACS_NXTLVL_RD_CNT") + .field( + "l1_dbus1_nxtlvl_rd_cnt", + &format_args!("{}", self.l1_dbus1_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS1_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS1_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus1_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS1_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS1_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L1_DBUS1_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_wr_cnt.rs new file mode 100644 index 0000000000..386ba2902f --- /dev/null +++ b/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_wr_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS1_ACS_NXTLVL_WR_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS1_NXTLVL_WR_CNT` reader - The register records the number of write back when bus1 accesses L1-DCache."] +pub type L1_DBUS1_NXTLVL_WR_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of write back when bus1 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus1_nxtlvl_wr_cnt(&self) -> L1_DBUS1_NXTLVL_WR_CNT_R { + L1_DBUS1_NXTLVL_WR_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS1_ACS_NXTLVL_WR_CNT") + .field( + "l1_dbus1_nxtlvl_wr_cnt", + &format_args!("{}", self.l1_dbus1_nxtlvl_wr_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus1 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_nxtlvl_wr_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS1_ACS_NXTLVL_WR_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS1_ACS_NXTLVL_WR_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus1_acs_nxtlvl_wr_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS1_ACS_NXTLVL_WR_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS1_ACS_NXTLVL_WR_CNT to value 0"] +impl crate::Resettable for L1_DBUS1_ACS_NXTLVL_WR_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus2_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_dbus2_acs_conflict_cnt.rs new file mode 100644 index 0000000000..ad2e96319a --- /dev/null +++ b/esp32p4/src/cache/l1_dbus2_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS2_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS2_CONFLICT_CNT` reader - The register records the number of access-conflicts when bus2 accesses L1-DCache."] +pub type L1_DBUS2_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when bus2 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus2_conflict_cnt(&self) -> L1_DBUS2_CONFLICT_CNT_R { + L1_DBUS2_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS2_ACS_CONFLICT_CNT") + .field( + "l1_dbus2_conflict_cnt", + &format_args!("{}", self.l1_dbus2_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS2_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS2_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus2_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS2_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS2_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L1_DBUS2_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus2_acs_hit_cnt.rs b/esp32p4/src/cache/l1_dbus2_acs_hit_cnt.rs new file mode 100644 index 0000000000..b27e440f5a --- /dev/null +++ b/esp32p4/src/cache/l1_dbus2_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS2_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS2_HIT_CNT` reader - The register records the number of hits when bus2 accesses L1-DCache."] +pub type L1_DBUS2_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when bus2 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus2_hit_cnt(&self) -> L1_DBUS2_HIT_CNT_R { + L1_DBUS2_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS2_ACS_HIT_CNT") + .field( + "l1_dbus2_hit_cnt", + &format_args!("{}", self.l1_dbus2_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS2_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS2_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus2_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS2_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS2_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L1_DBUS2_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus2_acs_miss_cnt.rs b/esp32p4/src/cache/l1_dbus2_acs_miss_cnt.rs new file mode 100644 index 0000000000..6967253f15 --- /dev/null +++ b/esp32p4/src/cache/l1_dbus2_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS2_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS2_MISS_CNT` reader - The register records the number of missing when bus2 accesses L1-DCache."] +pub type L1_DBUS2_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when bus2 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus2_miss_cnt(&self) -> L1_DBUS2_MISS_CNT_R { + L1_DBUS2_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS2_ACS_MISS_CNT") + .field( + "l1_dbus2_miss_cnt", + &format_args!("{}", self.l1_dbus2_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS2_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS2_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus2_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS2_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS2_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L1_DBUS2_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..ccd5e7dd8a --- /dev/null +++ b/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS2_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS2_NXTLVL_RD_CNT` reader - The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."] +pub type L1_DBUS2_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."] + #[inline(always)] + pub fn l1_dbus2_nxtlvl_rd_cnt(&self) -> L1_DBUS2_NXTLVL_RD_CNT_R { + L1_DBUS2_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS2_ACS_NXTLVL_RD_CNT") + .field( + "l1_dbus2_nxtlvl_rd_cnt", + &format_args!("{}", self.l1_dbus2_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS2_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS2_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus2_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS2_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS2_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L1_DBUS2_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_wr_cnt.rs new file mode 100644 index 0000000000..5c1978fb6f --- /dev/null +++ b/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_wr_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS2_ACS_NXTLVL_WR_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS2_NXTLVL_WR_CNT` reader - The register records the number of write back when bus2 accesses L1-DCache."] +pub type L1_DBUS2_NXTLVL_WR_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of write back when bus2 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus2_nxtlvl_wr_cnt(&self) -> L1_DBUS2_NXTLVL_WR_CNT_R { + L1_DBUS2_NXTLVL_WR_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS2_ACS_NXTLVL_WR_CNT") + .field( + "l1_dbus2_nxtlvl_wr_cnt", + &format_args!("{}", self.l1_dbus2_nxtlvl_wr_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus2 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_nxtlvl_wr_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS2_ACS_NXTLVL_WR_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS2_ACS_NXTLVL_WR_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus2_acs_nxtlvl_wr_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS2_ACS_NXTLVL_WR_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS2_ACS_NXTLVL_WR_CNT to value 0"] +impl crate::Resettable for L1_DBUS2_ACS_NXTLVL_WR_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus3_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_dbus3_acs_conflict_cnt.rs new file mode 100644 index 0000000000..bf08c1f91d --- /dev/null +++ b/esp32p4/src/cache/l1_dbus3_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS3_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS3_CONFLICT_CNT` reader - The register records the number of access-conflicts when bus3 accesses L1-DCache."] +pub type L1_DBUS3_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when bus3 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus3_conflict_cnt(&self) -> L1_DBUS3_CONFLICT_CNT_R { + L1_DBUS3_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS3_ACS_CONFLICT_CNT") + .field( + "l1_dbus3_conflict_cnt", + &format_args!("{}", self.l1_dbus3_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS3_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS3_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus3_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS3_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS3_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L1_DBUS3_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus3_acs_hit_cnt.rs b/esp32p4/src/cache/l1_dbus3_acs_hit_cnt.rs new file mode 100644 index 0000000000..2fb67a7c61 --- /dev/null +++ b/esp32p4/src/cache/l1_dbus3_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS3_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS3_HIT_CNT` reader - The register records the number of hits when bus3 accesses L1-DCache."] +pub type L1_DBUS3_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when bus3 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus3_hit_cnt(&self) -> L1_DBUS3_HIT_CNT_R { + L1_DBUS3_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS3_ACS_HIT_CNT") + .field( + "l1_dbus3_hit_cnt", + &format_args!("{}", self.l1_dbus3_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS3_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS3_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus3_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS3_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS3_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L1_DBUS3_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus3_acs_miss_cnt.rs b/esp32p4/src/cache/l1_dbus3_acs_miss_cnt.rs new file mode 100644 index 0000000000..c648d1362b --- /dev/null +++ b/esp32p4/src/cache/l1_dbus3_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS3_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS3_MISS_CNT` reader - The register records the number of missing when bus3 accesses L1-DCache."] +pub type L1_DBUS3_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when bus3 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus3_miss_cnt(&self) -> L1_DBUS3_MISS_CNT_R { + L1_DBUS3_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS3_ACS_MISS_CNT") + .field( + "l1_dbus3_miss_cnt", + &format_args!("{}", self.l1_dbus3_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS3_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS3_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus3_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS3_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS3_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L1_DBUS3_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..75f37ae722 --- /dev/null +++ b/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS3_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS3_NXTLVL_RD_CNT` reader - The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache."] +pub type L1_DBUS3_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache."] + #[inline(always)] + pub fn l1_dbus3_nxtlvl_rd_cnt(&self) -> L1_DBUS3_NXTLVL_RD_CNT_R { + L1_DBUS3_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS3_ACS_NXTLVL_RD_CNT") + .field( + "l1_dbus3_nxtlvl_rd_cnt", + &format_args!("{}", self.l1_dbus3_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS3_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS3_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus3_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS3_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS3_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L1_DBUS3_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_wr_cnt.rs new file mode 100644 index 0000000000..10fe3cefbf --- /dev/null +++ b/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_wr_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DBUS3_ACS_NXTLVL_WR_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DBUS3_NXTLVL_WR_CNT` reader - The register records the number of write back when bus0 accesses L1-DCache."] +pub type L1_DBUS3_NXTLVL_WR_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of write back when bus0 accesses L1-DCache."] + #[inline(always)] + pub fn l1_dbus3_nxtlvl_wr_cnt(&self) -> L1_DBUS3_NXTLVL_WR_CNT_R { + L1_DBUS3_NXTLVL_WR_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DBUS3_ACS_NXTLVL_WR_CNT") + .field( + "l1_dbus3_nxtlvl_wr_cnt", + &format_args!("{}", self.l1_dbus3_nxtlvl_wr_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache bus3 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_nxtlvl_wr_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DBUS3_ACS_NXTLVL_WR_CNT_SPEC; +impl crate::RegisterSpec for L1_DBUS3_ACS_NXTLVL_WR_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dbus3_acs_nxtlvl_wr_cnt::R`](R) reader structure"] +impl crate::Readable for L1_DBUS3_ACS_NXTLVL_WR_CNT_SPEC {} +#[doc = "`reset()` method sets L1_DBUS3_ACS_NXTLVL_WR_CNT to value 0"] +impl crate::Resettable for L1_DBUS3_ACS_NXTLVL_WR_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_acs_fail_addr.rs b/esp32p4/src/cache/l1_dcache_acs_fail_addr.rs new file mode 100644 index 0000000000..d7c7d99c81 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_acs_fail_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_DCACHE_ACS_FAIL_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DCACHE_FAIL_ADDR` reader - The register records the address of fail-access when cache accesses L1-DCache."] +pub type L1_DCACHE_FAIL_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the address of fail-access when cache accesses L1-DCache."] + #[inline(always)] + pub fn l1_dcache_fail_addr(&self) -> L1_DCACHE_FAIL_ADDR_R { + L1_DCACHE_FAIL_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_ACS_FAIL_ADDR") + .field( + "l1_dcache_fail_addr", + &format_args!("{}", self.l1_dcache_fail_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_acs_fail_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_ACS_FAIL_ADDR_SPEC; +impl crate::RegisterSpec for L1_DCACHE_ACS_FAIL_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_acs_fail_addr::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_ACS_FAIL_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_DCACHE_ACS_FAIL_ADDR to value 0"] +impl crate::Resettable for L1_DCACHE_ACS_FAIL_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_acs_fail_id_attr.rs b/esp32p4/src/cache/l1_dcache_acs_fail_id_attr.rs new file mode 100644 index 0000000000..04bca18e96 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_acs_fail_id_attr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `L1_DCACHE_ACS_FAIL_ID_ATTR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DCACHE_FAIL_ID` reader - The register records the ID of fail-access when cache accesses L1-DCache."] +pub type L1_DCACHE_FAIL_ID_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_FAIL_ATTR` reader - The register records the attribution of fail-access when cache accesses L1-DCache."] +pub type L1_DCACHE_FAIL_ATTR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - The register records the ID of fail-access when cache accesses L1-DCache."] + #[inline(always)] + pub fn l1_dcache_fail_id(&self) -> L1_DCACHE_FAIL_ID_R { + L1_DCACHE_FAIL_ID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - The register records the attribution of fail-access when cache accesses L1-DCache."] + #[inline(always)] + pub fn l1_dcache_fail_attr(&self) -> L1_DCACHE_FAIL_ATTR_R { + L1_DCACHE_FAIL_ATTR_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_ACS_FAIL_ID_ATTR") + .field( + "l1_dcache_fail_id", + &format_args!("{}", self.l1_dcache_fail_id().bits()), + ) + .field( + "l1_dcache_fail_attr", + &format_args!("{}", self.l1_dcache_fail_attr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-DCache Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_acs_fail_id_attr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_ACS_FAIL_ID_ATTR_SPEC; +impl crate::RegisterSpec for L1_DCACHE_ACS_FAIL_ID_ATTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_acs_fail_id_attr::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_ACS_FAIL_ID_ATTR_SPEC {} +#[doc = "`reset()` method sets L1_DCACHE_ACS_FAIL_ID_ATTR to value 0"] +impl crate::Resettable for L1_DCACHE_ACS_FAIL_ID_ATTR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_autoload_ctrl.rs b/esp32p4/src/cache/l1_dcache_autoload_ctrl.rs new file mode 100644 index 0000000000..1ba13001b9 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_autoload_ctrl.rs @@ -0,0 +1,226 @@ +#[doc = "Register `L1_DCACHE_AUTOLOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_AUTOLOAD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_AUTOLOAD_ENA` reader - The bit is used to enable and disable autoload operation on L1-DCache. 1: enable, 0: disable."] +pub type L1_DCACHE_AUTOLOAD_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_ENA` writer - The bit is used to enable and disable autoload operation on L1-DCache. 1: enable, 0: disable."] +pub type L1_DCACHE_AUTOLOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_AUTOLOAD_DONE` reader - The bit is used to indicate whether autoload operation on L1-DCache is finished or not. 0: not finished. 1: finished."] +pub type L1_DCACHE_AUTOLOAD_DONE_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_ORDER` reader - The bit is used to configure the direction of autoload operation on L1-DCache. 0: ascending. 1: descending."] +pub type L1_DCACHE_AUTOLOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_ORDER` writer - The bit is used to configure the direction of autoload operation on L1-DCache. 0: ascending. 1: descending."] +pub type L1_DCACHE_AUTOLOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_AUTOLOAD_TRIGGER_MODE` reader - The field is used to configure trigger mode of autoload operation on L1-DCache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] +pub type L1_DCACHE_AUTOLOAD_TRIGGER_MODE_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_TRIGGER_MODE` writer - The field is used to configure trigger mode of autoload operation on L1-DCache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] +pub type L1_DCACHE_AUTOLOAD_TRIGGER_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT0_ENA` reader - The bit is used to enable the first section for autoload operation on L1-DCache."] +pub type L1_DCACHE_AUTOLOAD_SCT0_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT0_ENA` writer - The bit is used to enable the first section for autoload operation on L1-DCache."] +pub type L1_DCACHE_AUTOLOAD_SCT0_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT1_ENA` reader - The bit is used to enable the second section for autoload operation on L1-DCache."] +pub type L1_DCACHE_AUTOLOAD_SCT1_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT1_ENA` writer - The bit is used to enable the second section for autoload operation on L1-DCache."] +pub type L1_DCACHE_AUTOLOAD_SCT1_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT2_ENA` reader - The bit is used to enable the third section for autoload operation on L1-DCache."] +pub type L1_DCACHE_AUTOLOAD_SCT2_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT2_ENA` writer - The bit is used to enable the third section for autoload operation on L1-DCache."] +pub type L1_DCACHE_AUTOLOAD_SCT2_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT3_ENA` reader - The bit is used to enable the fourth section for autoload operation on L1-DCache."] +pub type L1_DCACHE_AUTOLOAD_SCT3_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT3_ENA` writer - The bit is used to enable the fourth section for autoload operation on L1-DCache."] +pub type L1_DCACHE_AUTOLOAD_SCT3_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_AUTOLOAD_RGID` reader - The bit is used to set the gid of l1 dcache autoload."] +pub type L1_DCACHE_AUTOLOAD_RGID_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_RGID` writer - The bit is used to set the gid of l1 dcache autoload."] +pub type L1_DCACHE_AUTOLOAD_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-DCache. 1: enable, 0: disable."] + #[inline(always)] + pub fn l1_dcache_autoload_ena(&self) -> L1_DCACHE_AUTOLOAD_ENA_R { + L1_DCACHE_AUTOLOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether autoload operation on L1-DCache is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_dcache_autoload_done(&self) -> L1_DCACHE_AUTOLOAD_DONE_R { + L1_DCACHE_AUTOLOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of autoload operation on L1-DCache. 0: ascending. 1: descending."] + #[inline(always)] + pub fn l1_dcache_autoload_order(&self) -> L1_DCACHE_AUTOLOAD_ORDER_R { + L1_DCACHE_AUTOLOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - The field is used to configure trigger mode of autoload operation on L1-DCache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] + #[inline(always)] + pub fn l1_dcache_autoload_trigger_mode(&self) -> L1_DCACHE_AUTOLOAD_TRIGGER_MODE_R { + L1_DCACHE_AUTOLOAD_TRIGGER_MODE_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 8 - The bit is used to enable the first section for autoload operation on L1-DCache."] + #[inline(always)] + pub fn l1_dcache_autoload_sct0_ena(&self) -> L1_DCACHE_AUTOLOAD_SCT0_ENA_R { + L1_DCACHE_AUTOLOAD_SCT0_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The bit is used to enable the second section for autoload operation on L1-DCache."] + #[inline(always)] + pub fn l1_dcache_autoload_sct1_ena(&self) -> L1_DCACHE_AUTOLOAD_SCT1_ENA_R { + L1_DCACHE_AUTOLOAD_SCT1_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The bit is used to enable the third section for autoload operation on L1-DCache."] + #[inline(always)] + pub fn l1_dcache_autoload_sct2_ena(&self) -> L1_DCACHE_AUTOLOAD_SCT2_ENA_R { + L1_DCACHE_AUTOLOAD_SCT2_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The bit is used to enable the fourth section for autoload operation on L1-DCache."] + #[inline(always)] + pub fn l1_dcache_autoload_sct3_ena(&self) -> L1_DCACHE_AUTOLOAD_SCT3_ENA_R { + L1_DCACHE_AUTOLOAD_SCT3_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:15 - The bit is used to set the gid of l1 dcache autoload."] + #[inline(always)] + pub fn l1_dcache_autoload_rgid(&self) -> L1_DCACHE_AUTOLOAD_RGID_R { + L1_DCACHE_AUTOLOAD_RGID_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_AUTOLOAD_CTRL") + .field( + "l1_dcache_autoload_ena", + &format_args!("{}", self.l1_dcache_autoload_ena().bit()), + ) + .field( + "l1_dcache_autoload_done", + &format_args!("{}", self.l1_dcache_autoload_done().bit()), + ) + .field( + "l1_dcache_autoload_order", + &format_args!("{}", self.l1_dcache_autoload_order().bit()), + ) + .field( + "l1_dcache_autoload_trigger_mode", + &format_args!("{}", self.l1_dcache_autoload_trigger_mode().bits()), + ) + .field( + "l1_dcache_autoload_sct0_ena", + &format_args!("{}", self.l1_dcache_autoload_sct0_ena().bit()), + ) + .field( + "l1_dcache_autoload_sct1_ena", + &format_args!("{}", self.l1_dcache_autoload_sct1_ena().bit()), + ) + .field( + "l1_dcache_autoload_sct2_ena", + &format_args!("{}", self.l1_dcache_autoload_sct2_ena().bit()), + ) + .field( + "l1_dcache_autoload_sct3_ena", + &format_args!("{}", self.l1_dcache_autoload_sct3_ena().bit()), + ) + .field( + "l1_dcache_autoload_rgid", + &format_args!("{}", self.l1_dcache_autoload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-DCache. 1: enable, 0: disable."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_ena( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_ENA_W { + L1_DCACHE_AUTOLOAD_ENA_W::new(self, 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of autoload operation on L1-DCache. 0: ascending. 1: descending."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_order( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_ORDER_W { + L1_DCACHE_AUTOLOAD_ORDER_W::new(self, 2) + } + #[doc = "Bits 3:4 - The field is used to configure trigger mode of autoload operation on L1-DCache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_trigger_mode( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_TRIGGER_MODE_W { + L1_DCACHE_AUTOLOAD_TRIGGER_MODE_W::new(self, 3) + } + #[doc = "Bit 8 - The bit is used to enable the first section for autoload operation on L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct0_ena( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT0_ENA_W { + L1_DCACHE_AUTOLOAD_SCT0_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The bit is used to enable the second section for autoload operation on L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct1_ena( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT1_ENA_W { + L1_DCACHE_AUTOLOAD_SCT1_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - The bit is used to enable the third section for autoload operation on L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct2_ena( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT2_ENA_W { + L1_DCACHE_AUTOLOAD_SCT2_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - The bit is used to enable the fourth section for autoload operation on L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct3_ena( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT3_ENA_W { + L1_DCACHE_AUTOLOAD_SCT3_ENA_W::new(self, 11) + } + #[doc = "Bits 12:15 - The bit is used to set the gid of l1 dcache autoload."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_rgid( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_RGID_W { + L1_DCACHE_AUTOLOAD_RGID_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_AUTOLOAD_CTRL_SPEC; +impl crate::RegisterSpec for L1_DCACHE_AUTOLOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_autoload_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_AUTOLOAD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_autoload_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_AUTOLOAD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_AUTOLOAD_CTRL to value 0x02"] +impl crate::Resettable for L1_DCACHE_AUTOLOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct0_addr.rs b/esp32p4/src/cache/l1_dcache_autoload_sct0_addr.rs new file mode 100644 index 0000000000..4c6ec3bdb4 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_autoload_sct0_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT0_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT0_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT0_ADDR` writer - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l1_dcache_autoload_sct0_addr(&self) -> L1_DCACHE_AUTOLOAD_SCT0_ADDR_R { + L1_DCACHE_AUTOLOAD_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_AUTOLOAD_SCT0_ADDR") + .field( + "l1_dcache_autoload_sct0_addr", + &format_args!("{}", self.l1_dcache_autoload_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct0_addr( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT0_ADDR_W { + L1_DCACHE_AUTOLOAD_SCT0_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct0_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct0_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_AUTOLOAD_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L1_DCACHE_AUTOLOAD_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_autoload_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_AUTOLOAD_SCT0_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_autoload_sct0_addr::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_AUTOLOAD_SCT0_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_AUTOLOAD_SCT0_ADDR to value 0"] +impl crate::Resettable for L1_DCACHE_AUTOLOAD_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct0_size.rs b/esp32p4/src/cache/l1_dcache_autoload_sct0_size.rs new file mode 100644 index 0000000000..43c39c6bf7 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_autoload_sct0_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT0_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT0_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT0_SIZE` reader - Those bits are used to configure the size of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT0_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT0_SIZE` writer - Those bits are used to configure the size of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l1_dcache_autoload_sct0_size(&self) -> L1_DCACHE_AUTOLOAD_SCT0_SIZE_R { + L1_DCACHE_AUTOLOAD_SCT0_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_AUTOLOAD_SCT0_SIZE") + .field( + "l1_dcache_autoload_sct0_size", + &format_args!("{}", self.l1_dcache_autoload_sct0_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct0_size( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT0_SIZE_W { + L1_DCACHE_AUTOLOAD_SCT0_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct0_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct0_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_AUTOLOAD_SCT0_SIZE_SPEC; +impl crate::RegisterSpec for L1_DCACHE_AUTOLOAD_SCT0_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_autoload_sct0_size::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_AUTOLOAD_SCT0_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_autoload_sct0_size::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_AUTOLOAD_SCT0_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_AUTOLOAD_SCT0_SIZE to value 0"] +impl crate::Resettable for L1_DCACHE_AUTOLOAD_SCT0_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct1_addr.rs b/esp32p4/src/cache/l1_dcache_autoload_sct1_addr.rs new file mode 100644 index 0000000000..e7f845b894 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_autoload_sct1_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT1_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT1_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT1_ADDR` writer - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + pub fn l1_dcache_autoload_sct1_addr(&self) -> L1_DCACHE_AUTOLOAD_SCT1_ADDR_R { + L1_DCACHE_AUTOLOAD_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_AUTOLOAD_SCT1_ADDR") + .field( + "l1_dcache_autoload_sct1_addr", + &format_args!("{}", self.l1_dcache_autoload_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct1_addr( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT1_ADDR_W { + L1_DCACHE_AUTOLOAD_SCT1_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct1_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct1_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_AUTOLOAD_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L1_DCACHE_AUTOLOAD_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_autoload_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_AUTOLOAD_SCT1_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_autoload_sct1_addr::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_AUTOLOAD_SCT1_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_AUTOLOAD_SCT1_ADDR to value 0"] +impl crate::Resettable for L1_DCACHE_AUTOLOAD_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct1_size.rs b/esp32p4/src/cache/l1_dcache_autoload_sct1_size.rs new file mode 100644 index 0000000000..d8c1c7e9f2 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_autoload_sct1_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT1_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT1_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT1_SIZE` reader - Those bits are used to configure the size of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT1_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT1_SIZE` writer - Those bits are used to configure the size of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + pub fn l1_dcache_autoload_sct1_size(&self) -> L1_DCACHE_AUTOLOAD_SCT1_SIZE_R { + L1_DCACHE_AUTOLOAD_SCT1_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_AUTOLOAD_SCT1_SIZE") + .field( + "l1_dcache_autoload_sct1_size", + &format_args!("{}", self.l1_dcache_autoload_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct1_size( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT1_SIZE_W { + L1_DCACHE_AUTOLOAD_SCT1_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct1_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct1_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_AUTOLOAD_SCT1_SIZE_SPEC; +impl crate::RegisterSpec for L1_DCACHE_AUTOLOAD_SCT1_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_autoload_sct1_size::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_AUTOLOAD_SCT1_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_autoload_sct1_size::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_AUTOLOAD_SCT1_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_AUTOLOAD_SCT1_SIZE to value 0"] +impl crate::Resettable for L1_DCACHE_AUTOLOAD_SCT1_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct2_addr.rs b/esp32p4/src/cache/l1_dcache_autoload_sct2_addr.rs new file mode 100644 index 0000000000..392b4c4b58 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_autoload_sct2_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT2_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT2_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT2_ADDR` reader - Those bits are used to configure the start virtual address of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT2_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT2_ADDR` writer - Those bits are used to configure the start virtual address of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT2_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA."] + #[inline(always)] + pub fn l1_dcache_autoload_sct2_addr(&self) -> L1_DCACHE_AUTOLOAD_SCT2_ADDR_R { + L1_DCACHE_AUTOLOAD_SCT2_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_AUTOLOAD_SCT2_ADDR") + .field( + "l1_dcache_autoload_sct2_addr", + &format_args!("{}", self.l1_dcache_autoload_sct2_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct2_addr( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT2_ADDR_W { + L1_DCACHE_AUTOLOAD_SCT2_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache autoload section 2 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct2_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct2_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_AUTOLOAD_SCT2_ADDR_SPEC; +impl crate::RegisterSpec for L1_DCACHE_AUTOLOAD_SCT2_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_autoload_sct2_addr::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_AUTOLOAD_SCT2_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_autoload_sct2_addr::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_AUTOLOAD_SCT2_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_AUTOLOAD_SCT2_ADDR to value 0"] +impl crate::Resettable for L1_DCACHE_AUTOLOAD_SCT2_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct2_size.rs b/esp32p4/src/cache/l1_dcache_autoload_sct2_size.rs new file mode 100644 index 0000000000..3b1d01d4d2 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_autoload_sct2_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT2_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT2_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT2_SIZE` reader - Those bits are used to configure the size of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT2_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT2_SIZE` writer - Those bits are used to configure the size of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT2_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA."] + #[inline(always)] + pub fn l1_dcache_autoload_sct2_size(&self) -> L1_DCACHE_AUTOLOAD_SCT2_SIZE_R { + L1_DCACHE_AUTOLOAD_SCT2_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_AUTOLOAD_SCT2_SIZE") + .field( + "l1_dcache_autoload_sct2_size", + &format_args!("{}", self.l1_dcache_autoload_sct2_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct2_size( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT2_SIZE_W { + L1_DCACHE_AUTOLOAD_SCT2_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache autoload section 2 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct2_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct2_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_AUTOLOAD_SCT2_SIZE_SPEC; +impl crate::RegisterSpec for L1_DCACHE_AUTOLOAD_SCT2_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_autoload_sct2_size::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_AUTOLOAD_SCT2_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_autoload_sct2_size::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_AUTOLOAD_SCT2_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_AUTOLOAD_SCT2_SIZE to value 0"] +impl crate::Resettable for L1_DCACHE_AUTOLOAD_SCT2_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct3_addr.rs b/esp32p4/src/cache/l1_dcache_autoload_sct3_addr.rs new file mode 100644 index 0000000000..f8a6d9d689 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_autoload_sct3_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT3_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT3_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT3_ADDR` reader - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT3_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT3_ADDR` writer - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT3_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA."] + #[inline(always)] + pub fn l1_dcache_autoload_sct3_addr(&self) -> L1_DCACHE_AUTOLOAD_SCT3_ADDR_R { + L1_DCACHE_AUTOLOAD_SCT3_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_AUTOLOAD_SCT3_ADDR") + .field( + "l1_dcache_autoload_sct3_addr", + &format_args!("{}", self.l1_dcache_autoload_sct3_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct3_addr( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT3_ADDR_W { + L1_DCACHE_AUTOLOAD_SCT3_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct3_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct3_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC; +impl crate::RegisterSpec for L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_autoload_sct3_addr::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_autoload_sct3_addr::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_AUTOLOAD_SCT3_ADDR to value 0"] +impl crate::Resettable for L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct3_size.rs b/esp32p4/src/cache/l1_dcache_autoload_sct3_size.rs new file mode 100644 index 0000000000..59c19ab2f9 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_autoload_sct3_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT3_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_AUTOLOAD_SCT3_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT3_SIZE` reader - Those bits are used to configure the size of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT3_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_AUTOLOAD_SCT3_SIZE` writer - Those bits are used to configure the size of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA."] +pub type L1_DCACHE_AUTOLOAD_SCT3_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA."] + #[inline(always)] + pub fn l1_dcache_autoload_sct3_size(&self) -> L1_DCACHE_AUTOLOAD_SCT3_SIZE_R { + L1_DCACHE_AUTOLOAD_SCT3_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_AUTOLOAD_SCT3_SIZE") + .field( + "l1_dcache_autoload_sct3_size", + &format_args!("{}", self.l1_dcache_autoload_sct3_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_autoload_sct3_size( + &mut self, + ) -> L1_DCACHE_AUTOLOAD_SCT3_SIZE_W { + L1_DCACHE_AUTOLOAD_SCT3_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_autoload_sct3_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_autoload_sct3_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_AUTOLOAD_SCT3_SIZE_SPEC; +impl crate::RegisterSpec for L1_DCACHE_AUTOLOAD_SCT3_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_autoload_sct3_size::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_AUTOLOAD_SCT3_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_autoload_sct3_size::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_AUTOLOAD_SCT3_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_AUTOLOAD_SCT3_SIZE to value 0"] +impl crate::Resettable for L1_DCACHE_AUTOLOAD_SCT3_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_blocksize_conf.rs b/esp32p4/src/cache/l1_dcache_blocksize_conf.rs new file mode 100644 index 0000000000..90f7d6eff1 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_blocksize_conf.rs @@ -0,0 +1,94 @@ +#[doc = "Register `L1_DCACHE_BLOCKSIZE_CONF` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DCACHE_BLOCKSIZE_8` reader - The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_BLOCKSIZE_8_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_BLOCKSIZE_16` reader - The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_BLOCKSIZE_16_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_BLOCKSIZE_32` reader - The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_BLOCKSIZE_32_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_BLOCKSIZE_64` reader - The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_BLOCKSIZE_64_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_BLOCKSIZE_128` reader - The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_BLOCKSIZE_128_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_BLOCKSIZE_256` reader - The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_BLOCKSIZE_256_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_blocksize_8(&self) -> L1_DCACHE_BLOCKSIZE_8_R { + L1_DCACHE_BLOCKSIZE_8_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_blocksize_16(&self) -> L1_DCACHE_BLOCKSIZE_16_R { + L1_DCACHE_BLOCKSIZE_16_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_blocksize_32(&self) -> L1_DCACHE_BLOCKSIZE_32_R { + L1_DCACHE_BLOCKSIZE_32_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_blocksize_64(&self) -> L1_DCACHE_BLOCKSIZE_64_R { + L1_DCACHE_BLOCKSIZE_64_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_blocksize_128(&self) -> L1_DCACHE_BLOCKSIZE_128_R { + L1_DCACHE_BLOCKSIZE_128_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_blocksize_256(&self) -> L1_DCACHE_BLOCKSIZE_256_R { + L1_DCACHE_BLOCKSIZE_256_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_BLOCKSIZE_CONF") + .field( + "l1_dcache_blocksize_8", + &format_args!("{}", self.l1_dcache_blocksize_8().bit()), + ) + .field( + "l1_dcache_blocksize_16", + &format_args!("{}", self.l1_dcache_blocksize_16().bit()), + ) + .field( + "l1_dcache_blocksize_32", + &format_args!("{}", self.l1_dcache_blocksize_32().bit()), + ) + .field( + "l1_dcache_blocksize_64", + &format_args!("{}", self.l1_dcache_blocksize_64().bit()), + ) + .field( + "l1_dcache_blocksize_128", + &format_args!("{}", self.l1_dcache_blocksize_128().bit()), + ) + .field( + "l1_dcache_blocksize_256", + &format_args!("{}", self.l1_dcache_blocksize_256().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 data Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_blocksize_conf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_BLOCKSIZE_CONF_SPEC; +impl crate::RegisterSpec for L1_DCACHE_BLOCKSIZE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_blocksize_conf::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_BLOCKSIZE_CONF_SPEC {} +#[doc = "`reset()` method sets L1_DCACHE_BLOCKSIZE_CONF to value 0x08"] +impl crate::Resettable for L1_DCACHE_BLOCKSIZE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/cache/l1_dcache_cachesize_conf.rs b/esp32p4/src/cache/l1_dcache_cachesize_conf.rs new file mode 100644 index 0000000000..bf41423c2e --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_cachesize_conf.rs @@ -0,0 +1,171 @@ +#[doc = "Register `L1_DCACHE_CACHESIZE_CONF` reader"] +pub type R = crate::R; +#[doc = "Field `L1_DCACHE_CACHESIZE_256` reader - The field is used to configure cachesize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_256_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_512` reader - The field is used to configure cachesize of L1-DCache as 512 bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_512_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_1K` reader - The field is used to configure cachesize of L1-DCache as 1k bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_1K_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_2K` reader - The field is used to configure cachesize of L1-DCache as 2k bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_2K_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_4K` reader - The field is used to configure cachesize of L1-DCache as 4k bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_4K_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_8K` reader - The field is used to configure cachesize of L1-DCache as 8k bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_8K_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_16K` reader - The field is used to configure cachesize of L1-DCache as 16k bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_16K_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_32K` reader - The field is used to configure cachesize of L1-DCache as 32k bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_32K_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_64K` reader - The field is used to configure cachesize of L1-DCache as 64k bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_64K_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_128K` reader - The field is used to configure cachesize of L1-DCache as 128k bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_128K_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_256K` reader - The field is used to configure cachesize of L1-DCache as 256k bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_256K_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_512K` reader - The field is used to configure cachesize of L1-DCache as 512k bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_512K_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_CACHESIZE_1024K` reader - The field is used to configure cachesize of L1-DCache as 1024k bytes. This field and all other fields within this register is onehot."] +pub type L1_DCACHE_CACHESIZE_1024K_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The field is used to configure cachesize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_256(&self) -> L1_DCACHE_CACHESIZE_256_R { + L1_DCACHE_CACHESIZE_256_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The field is used to configure cachesize of L1-DCache as 512 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_512(&self) -> L1_DCACHE_CACHESIZE_512_R { + L1_DCACHE_CACHESIZE_512_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The field is used to configure cachesize of L1-DCache as 1k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_1k(&self) -> L1_DCACHE_CACHESIZE_1K_R { + L1_DCACHE_CACHESIZE_1K_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The field is used to configure cachesize of L1-DCache as 2k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_2k(&self) -> L1_DCACHE_CACHESIZE_2K_R { + L1_DCACHE_CACHESIZE_2K_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The field is used to configure cachesize of L1-DCache as 4k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_4k(&self) -> L1_DCACHE_CACHESIZE_4K_R { + L1_DCACHE_CACHESIZE_4K_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The field is used to configure cachesize of L1-DCache as 8k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_8k(&self) -> L1_DCACHE_CACHESIZE_8K_R { + L1_DCACHE_CACHESIZE_8K_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The field is used to configure cachesize of L1-DCache as 16k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_16k(&self) -> L1_DCACHE_CACHESIZE_16K_R { + L1_DCACHE_CACHESIZE_16K_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The field is used to configure cachesize of L1-DCache as 32k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_32k(&self) -> L1_DCACHE_CACHESIZE_32K_R { + L1_DCACHE_CACHESIZE_32K_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The field is used to configure cachesize of L1-DCache as 64k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_64k(&self) -> L1_DCACHE_CACHESIZE_64K_R { + L1_DCACHE_CACHESIZE_64K_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The field is used to configure cachesize of L1-DCache as 128k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_128k(&self) -> L1_DCACHE_CACHESIZE_128K_R { + L1_DCACHE_CACHESIZE_128K_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The field is used to configure cachesize of L1-DCache as 256k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_256k(&self) -> L1_DCACHE_CACHESIZE_256K_R { + L1_DCACHE_CACHESIZE_256K_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The field is used to configure cachesize of L1-DCache as 512k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_512k(&self) -> L1_DCACHE_CACHESIZE_512K_R { + L1_DCACHE_CACHESIZE_512K_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The field is used to configure cachesize of L1-DCache as 1024k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_dcache_cachesize_1024k(&self) -> L1_DCACHE_CACHESIZE_1024K_R { + L1_DCACHE_CACHESIZE_1024K_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_CACHESIZE_CONF") + .field( + "l1_dcache_cachesize_256", + &format_args!("{}", self.l1_dcache_cachesize_256().bit()), + ) + .field( + "l1_dcache_cachesize_512", + &format_args!("{}", self.l1_dcache_cachesize_512().bit()), + ) + .field( + "l1_dcache_cachesize_1k", + &format_args!("{}", self.l1_dcache_cachesize_1k().bit()), + ) + .field( + "l1_dcache_cachesize_2k", + &format_args!("{}", self.l1_dcache_cachesize_2k().bit()), + ) + .field( + "l1_dcache_cachesize_4k", + &format_args!("{}", self.l1_dcache_cachesize_4k().bit()), + ) + .field( + "l1_dcache_cachesize_8k", + &format_args!("{}", self.l1_dcache_cachesize_8k().bit()), + ) + .field( + "l1_dcache_cachesize_16k", + &format_args!("{}", self.l1_dcache_cachesize_16k().bit()), + ) + .field( + "l1_dcache_cachesize_32k", + &format_args!("{}", self.l1_dcache_cachesize_32k().bit()), + ) + .field( + "l1_dcache_cachesize_64k", + &format_args!("{}", self.l1_dcache_cachesize_64k().bit()), + ) + .field( + "l1_dcache_cachesize_128k", + &format_args!("{}", self.l1_dcache_cachesize_128k().bit()), + ) + .field( + "l1_dcache_cachesize_256k", + &format_args!("{}", self.l1_dcache_cachesize_256k().bit()), + ) + .field( + "l1_dcache_cachesize_512k", + &format_args!("{}", self.l1_dcache_cachesize_512k().bit()), + ) + .field( + "l1_dcache_cachesize_1024k", + &format_args!("{}", self.l1_dcache_cachesize_1024k().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 data Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_cachesize_conf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_CACHESIZE_CONF_SPEC; +impl crate::RegisterSpec for L1_DCACHE_CACHESIZE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_cachesize_conf::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_CACHESIZE_CONF_SPEC {} +#[doc = "`reset()` method sets L1_DCACHE_CACHESIZE_CONF to value 0x0100"] +impl crate::Resettable for L1_DCACHE_CACHESIZE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/cache/l1_dcache_ctrl.rs b/esp32p4/src/cache/l1_dcache_ctrl.rs new file mode 100644 index 0000000000..53d5321c0b --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_ctrl.rs @@ -0,0 +1,145 @@ +#[doc = "Register `L1_DCACHE_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_SHUT_DBUS0` reader - The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable"] +pub type L1_DCACHE_SHUT_DBUS0_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_SHUT_DBUS0` writer - The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable"] +pub type L1_DCACHE_SHUT_DBUS0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_SHUT_DBUS1` reader - The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable"] +pub type L1_DCACHE_SHUT_DBUS1_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_SHUT_DBUS1` writer - The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable"] +pub type L1_DCACHE_SHUT_DBUS1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_SHUT_DBUS2` reader - Reserved"] +pub type L1_DCACHE_SHUT_DBUS2_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_SHUT_DBUS3` reader - Reserved"] +pub type L1_DCACHE_SHUT_DBUS3_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_SHUT_DMA` reader - The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable"] +pub type L1_DCACHE_SHUT_DMA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_SHUT_DMA` writer - The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable"] +pub type L1_DCACHE_SHUT_DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_UNDEF_OP` reader - Reserved"] +pub type L1_DCACHE_UNDEF_OP_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_UNDEF_OP` writer - Reserved"] +pub type L1_DCACHE_UNDEF_OP_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable"] + #[inline(always)] + pub fn l1_dcache_shut_dbus0(&self) -> L1_DCACHE_SHUT_DBUS0_R { + L1_DCACHE_SHUT_DBUS0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable"] + #[inline(always)] + pub fn l1_dcache_shut_dbus1(&self) -> L1_DCACHE_SHUT_DBUS1_R { + L1_DCACHE_SHUT_DBUS1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_dcache_shut_dbus2(&self) -> L1_DCACHE_SHUT_DBUS2_R { + L1_DCACHE_SHUT_DBUS2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_dcache_shut_dbus3(&self) -> L1_DCACHE_SHUT_DBUS3_R { + L1_DCACHE_SHUT_DBUS3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable"] + #[inline(always)] + pub fn l1_dcache_shut_dma(&self) -> L1_DCACHE_SHUT_DMA_R { + L1_DCACHE_SHUT_DMA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn l1_dcache_undef_op(&self) -> L1_DCACHE_UNDEF_OP_R { + L1_DCACHE_UNDEF_OP_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_CTRL") + .field( + "l1_dcache_shut_dbus0", + &format_args!("{}", self.l1_dcache_shut_dbus0().bit()), + ) + .field( + "l1_dcache_shut_dbus1", + &format_args!("{}", self.l1_dcache_shut_dbus1().bit()), + ) + .field( + "l1_dcache_shut_dbus2", + &format_args!("{}", self.l1_dcache_shut_dbus2().bit()), + ) + .field( + "l1_dcache_shut_dbus3", + &format_args!("{}", self.l1_dcache_shut_dbus3().bit()), + ) + .field( + "l1_dcache_shut_dma", + &format_args!("{}", self.l1_dcache_shut_dma().bit()), + ) + .field( + "l1_dcache_undef_op", + &format_args!("{}", self.l1_dcache_undef_op().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_shut_dbus0(&mut self) -> L1_DCACHE_SHUT_DBUS0_W { + L1_DCACHE_SHUT_DBUS0_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_shut_dbus1(&mut self) -> L1_DCACHE_SHUT_DBUS1_W { + L1_DCACHE_SHUT_DBUS1_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_shut_dma(&mut self) -> L1_DCACHE_SHUT_DMA_W { + L1_DCACHE_SHUT_DMA_W::new(self, 4) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_undef_op(&mut self) -> L1_DCACHE_UNDEF_OP_W { + L1_DCACHE_UNDEF_OP_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache(L1-DCache) control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_CTRL_SPEC; +impl crate::RegisterSpec for L1_DCACHE_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_CTRL to value 0"] +impl crate::Resettable for L1_DCACHE_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_preload_addr.rs b/esp32p4/src/cache/l1_dcache_preload_addr.rs new file mode 100644 index 0000000000..5f56938275 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_preload_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_PRELOAD_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_PRELOAD_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_PRELOAD_ADDR` reader - Those bits are used to configure the start virtual address of preload on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG"] +pub type L1_DCACHE_PRELOAD_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_PRELOAD_ADDR` writer - Those bits are used to configure the start virtual address of preload on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG"] +pub type L1_DCACHE_PRELOAD_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG"] + #[inline(always)] + pub fn l1_dcache_preload_addr(&self) -> L1_DCACHE_PRELOAD_ADDR_R { + L1_DCACHE_PRELOAD_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_PRELOAD_ADDR") + .field( + "l1_dcache_preload_addr", + &format_args!("{}", self.l1_dcache_preload_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_preload_addr( + &mut self, + ) -> L1_DCACHE_PRELOAD_ADDR_W { + L1_DCACHE_PRELOAD_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_preload_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_preload_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_PRELOAD_ADDR_SPEC; +impl crate::RegisterSpec for L1_DCACHE_PRELOAD_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_preload_addr::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_PRELOAD_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_preload_addr::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_PRELOAD_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_PRELOAD_ADDR to value 0"] +impl crate::Resettable for L1_DCACHE_PRELOAD_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_preload_ctrl.rs b/esp32p4/src/cache/l1_dcache_preload_ctrl.rs new file mode 100644 index 0000000000..17c8137a83 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_preload_ctrl.rs @@ -0,0 +1,121 @@ +#[doc = "Register `L1_DCACHE_PRELOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_PRELOAD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_PRELOAD_ENA` reader - The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done."] +pub type L1_DCACHE_PRELOAD_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PRELOAD_ENA` writer - The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done."] +pub type L1_DCACHE_PRELOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_PRELOAD_DONE` reader - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] +pub type L1_DCACHE_PRELOAD_DONE_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PRELOAD_ORDER` reader - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] +pub type L1_DCACHE_PRELOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PRELOAD_ORDER` writer - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] +pub type L1_DCACHE_PRELOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_PRELOAD_RGID` reader - The bit is used to set the gid of l1 dcache preload."] +pub type L1_DCACHE_PRELOAD_RGID_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_PRELOAD_RGID` writer - The bit is used to set the gid of l1 dcache preload."] +pub type L1_DCACHE_PRELOAD_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done."] + #[inline(always)] + pub fn l1_dcache_preload_ena(&self) -> L1_DCACHE_PRELOAD_ENA_R { + L1_DCACHE_PRELOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_dcache_preload_done(&self) -> L1_DCACHE_PRELOAD_DONE_R { + L1_DCACHE_PRELOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] + #[inline(always)] + pub fn l1_dcache_preload_order(&self) -> L1_DCACHE_PRELOAD_ORDER_R { + L1_DCACHE_PRELOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of l1 dcache preload."] + #[inline(always)] + pub fn l1_dcache_preload_rgid(&self) -> L1_DCACHE_PRELOAD_RGID_R { + L1_DCACHE_PRELOAD_RGID_R::new(((self.bits >> 3) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_PRELOAD_CTRL") + .field( + "l1_dcache_preload_ena", + &format_args!("{}", self.l1_dcache_preload_ena().bit()), + ) + .field( + "l1_dcache_preload_done", + &format_args!("{}", self.l1_dcache_preload_done().bit()), + ) + .field( + "l1_dcache_preload_order", + &format_args!("{}", self.l1_dcache_preload_order().bit()), + ) + .field( + "l1_dcache_preload_rgid", + &format_args!("{}", self.l1_dcache_preload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_preload_ena( + &mut self, + ) -> L1_DCACHE_PRELOAD_ENA_W { + L1_DCACHE_PRELOAD_ENA_W::new(self, 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_preload_order( + &mut self, + ) -> L1_DCACHE_PRELOAD_ORDER_W { + L1_DCACHE_PRELOAD_ORDER_W::new(self, 2) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of l1 dcache preload."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_preload_rgid( + &mut self, + ) -> L1_DCACHE_PRELOAD_RGID_W { + L1_DCACHE_PRELOAD_RGID_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_preload_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_preload_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_PRELOAD_CTRL_SPEC; +impl crate::RegisterSpec for L1_DCACHE_PRELOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_preload_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_PRELOAD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_preload_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_PRELOAD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_PRELOAD_CTRL to value 0x02"] +impl crate::Resettable for L1_DCACHE_PRELOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l1_dcache_preload_size.rs b/esp32p4/src/cache/l1_dcache_preload_size.rs new file mode 100644 index 0000000000..5681053478 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_preload_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_PRELOAD_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_PRELOAD_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_PRELOAD_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG"] +pub type L1_DCACHE_PRELOAD_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_PRELOAD_SIZE` writer - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG"] +pub type L1_DCACHE_PRELOAD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG"] + #[inline(always)] + pub fn l1_dcache_preload_size(&self) -> L1_DCACHE_PRELOAD_SIZE_R { + L1_DCACHE_PRELOAD_SIZE_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_PRELOAD_SIZE") + .field( + "l1_dcache_preload_size", + &format_args!("{}", self.l1_dcache_preload_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_preload_size( + &mut self, + ) -> L1_DCACHE_PRELOAD_SIZE_W { + L1_DCACHE_PRELOAD_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_preload_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_preload_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_PRELOAD_SIZE_SPEC; +impl crate::RegisterSpec for L1_DCACHE_PRELOAD_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_preload_size::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_PRELOAD_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_preload_size::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_PRELOAD_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_PRELOAD_SIZE to value 0"] +impl crate::Resettable for L1_DCACHE_PRELOAD_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_prelock_conf.rs b/esp32p4/src/cache/l1_dcache_prelock_conf.rs new file mode 100644 index 0000000000..c52bd892d3 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_prelock_conf.rs @@ -0,0 +1,110 @@ +#[doc = "Register `L1_DCACHE_PRELOCK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_PRELOCK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT0_EN` reader - The bit is used to enable the first section of prelock function on L1-DCache."] +pub type L1_DCACHE_PRELOCK_SCT0_EN_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT0_EN` writer - The bit is used to enable the first section of prelock function on L1-DCache."] +pub type L1_DCACHE_PRELOCK_SCT0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT1_EN` reader - The bit is used to enable the second section of prelock function on L1-DCache."] +pub type L1_DCACHE_PRELOCK_SCT1_EN_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT1_EN` writer - The bit is used to enable the second section of prelock function on L1-DCache."] +pub type L1_DCACHE_PRELOCK_SCT1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_PRELOCK_RGID` reader - The bit is used to set the gid of l1 dcache prelock."] +pub type L1_DCACHE_PRELOCK_RGID_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_PRELOCK_RGID` writer - The bit is used to set the gid of l1 dcache prelock."] +pub type L1_DCACHE_PRELOCK_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-DCache."] + #[inline(always)] + pub fn l1_dcache_prelock_sct0_en(&self) -> L1_DCACHE_PRELOCK_SCT0_EN_R { + L1_DCACHE_PRELOCK_SCT0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable the second section of prelock function on L1-DCache."] + #[inline(always)] + pub fn l1_dcache_prelock_sct1_en(&self) -> L1_DCACHE_PRELOCK_SCT1_EN_R { + L1_DCACHE_PRELOCK_SCT1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The bit is used to set the gid of l1 dcache prelock."] + #[inline(always)] + pub fn l1_dcache_prelock_rgid(&self) -> L1_DCACHE_PRELOCK_RGID_R { + L1_DCACHE_PRELOCK_RGID_R::new(((self.bits >> 2) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_PRELOCK_CONF") + .field( + "l1_dcache_prelock_sct0_en", + &format_args!("{}", self.l1_dcache_prelock_sct0_en().bit()), + ) + .field( + "l1_dcache_prelock_sct1_en", + &format_args!("{}", self.l1_dcache_prelock_sct1_en().bit()), + ) + .field( + "l1_dcache_prelock_rgid", + &format_args!("{}", self.l1_dcache_prelock_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_prelock_sct0_en( + &mut self, + ) -> L1_DCACHE_PRELOCK_SCT0_EN_W { + L1_DCACHE_PRELOCK_SCT0_EN_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable the second section of prelock function on L1-DCache."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_prelock_sct1_en( + &mut self, + ) -> L1_DCACHE_PRELOCK_SCT1_EN_W { + L1_DCACHE_PRELOCK_SCT1_EN_W::new(self, 1) + } + #[doc = "Bits 2:5 - The bit is used to set the gid of l1 dcache prelock."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_prelock_rgid( + &mut self, + ) -> L1_DCACHE_PRELOCK_RGID_W { + L1_DCACHE_PRELOCK_RGID_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_PRELOCK_CONF_SPEC; +impl crate::RegisterSpec for L1_DCACHE_PRELOCK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_prelock_conf::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_PRELOCK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_prelock_conf::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_PRELOCK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_PRELOCK_CONF to value 0"] +impl crate::Resettable for L1_DCACHE_PRELOCK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_prelock_sct0_addr.rs b/esp32p4/src/cache/l1_dcache_prelock_sct0_addr.rs new file mode 100644 index 0000000000..19125a2d0e --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_prelock_sct0_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_PRELOCK_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_PRELOCK_SCT0_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG"] +pub type L1_DCACHE_PRELOCK_SCT0_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT0_ADDR` writer - Those bits are used to configure the start virtual address of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG"] +pub type L1_DCACHE_PRELOCK_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG"] + #[inline(always)] + pub fn l1_dcache_prelock_sct0_addr(&self) -> L1_DCACHE_PRELOCK_SCT0_ADDR_R { + L1_DCACHE_PRELOCK_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_PRELOCK_SCT0_ADDR") + .field( + "l1_dcache_prelock_sct0_addr", + &format_args!("{}", self.l1_dcache_prelock_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_prelock_sct0_addr( + &mut self, + ) -> L1_DCACHE_PRELOCK_SCT0_ADDR_W { + L1_DCACHE_PRELOCK_SCT0_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_sct0_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_sct0_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_PRELOCK_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L1_DCACHE_PRELOCK_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_prelock_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_PRELOCK_SCT0_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_prelock_sct0_addr::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_PRELOCK_SCT0_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_PRELOCK_SCT0_ADDR to value 0"] +impl crate::Resettable for L1_DCACHE_PRELOCK_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_prelock_sct1_addr.rs b/esp32p4/src/cache/l1_dcache_prelock_sct1_addr.rs new file mode 100644 index 0000000000..86a9400cf8 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_prelock_sct1_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_DCACHE_PRELOCK_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_PRELOCK_SCT1_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG"] +pub type L1_DCACHE_PRELOCK_SCT1_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT1_ADDR` writer - Those bits are used to configure the start virtual address of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG"] +pub type L1_DCACHE_PRELOCK_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG"] + #[inline(always)] + pub fn l1_dcache_prelock_sct1_addr(&self) -> L1_DCACHE_PRELOCK_SCT1_ADDR_R { + L1_DCACHE_PRELOCK_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_PRELOCK_SCT1_ADDR") + .field( + "l1_dcache_prelock_sct1_addr", + &format_args!("{}", self.l1_dcache_prelock_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_prelock_sct1_addr( + &mut self, + ) -> L1_DCACHE_PRELOCK_SCT1_ADDR_W { + L1_DCACHE_PRELOCK_SCT1_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_sct1_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_sct1_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_PRELOCK_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L1_DCACHE_PRELOCK_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_prelock_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_PRELOCK_SCT1_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_prelock_sct1_addr::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_PRELOCK_SCT1_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_PRELOCK_SCT1_ADDR to value 0"] +impl crate::Resettable for L1_DCACHE_PRELOCK_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_dcache_prelock_sct_size.rs b/esp32p4/src/cache/l1_dcache_prelock_sct_size.rs new file mode 100644 index 0000000000..1c599bc348 --- /dev/null +++ b/esp32p4/src/cache/l1_dcache_prelock_sct_size.rs @@ -0,0 +1,89 @@ +#[doc = "Register `L1_DCACHE_PRELOCK_SCT_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_DCACHE_PRELOCK_SCT_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT0_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG"] +pub type L1_DCACHE_PRELOCK_SCT0_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT0_SIZE` writer - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG"] +pub type L1_DCACHE_PRELOCK_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT1_SIZE` reader - Those bits are used to configure the size of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG"] +pub type L1_DCACHE_PRELOCK_SCT1_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_PRELOCK_SCT1_SIZE` writer - Those bits are used to configure the size of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG"] +pub type L1_DCACHE_PRELOCK_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG"] + #[inline(always)] + pub fn l1_dcache_prelock_sct0_size(&self) -> L1_DCACHE_PRELOCK_SCT0_SIZE_R { + L1_DCACHE_PRELOCK_SCT0_SIZE_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - Those bits are used to configure the size of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG"] + #[inline(always)] + pub fn l1_dcache_prelock_sct1_size(&self) -> L1_DCACHE_PRELOCK_SCT1_SIZE_R { + L1_DCACHE_PRELOCK_SCT1_SIZE_R::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_DCACHE_PRELOCK_SCT_SIZE") + .field( + "l1_dcache_prelock_sct0_size", + &format_args!("{}", self.l1_dcache_prelock_sct0_size().bits()), + ) + .field( + "l1_dcache_prelock_sct1_size", + &format_args!("{}", self.l1_dcache_prelock_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_prelock_sct0_size( + &mut self, + ) -> L1_DCACHE_PRELOCK_SCT0_SIZE_W { + L1_DCACHE_PRELOCK_SCT0_SIZE_W::new(self, 0) + } + #[doc = "Bits 16:29 - Those bits are used to configure the size of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l1_dcache_prelock_sct1_size( + &mut self, + ) -> L1_DCACHE_PRELOCK_SCT1_SIZE_W { + L1_DCACHE_PRELOCK_SCT1_SIZE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 data Cache prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_prelock_sct_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_dcache_prelock_sct_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_DCACHE_PRELOCK_SCT_SIZE_SPEC; +impl crate::RegisterSpec for L1_DCACHE_PRELOCK_SCT_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_dcache_prelock_sct_size::R`](R) reader structure"] +impl crate::Readable for L1_DCACHE_PRELOCK_SCT_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_dcache_prelock_sct_size::W`](W) writer structure"] +impl crate::Writable for L1_DCACHE_PRELOCK_SCT_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_DCACHE_PRELOCK_SCT_SIZE to value 0x3fff_3fff"] +impl crate::Resettable for L1_DCACHE_PRELOCK_SCT_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0x3fff_3fff; +} diff --git a/esp32p4/src/cache/l1_ibus0_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_ibus0_acs_conflict_cnt.rs new file mode 100644 index 0000000000..f78b860e5a --- /dev/null +++ b/esp32p4/src/cache/l1_ibus0_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS0_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS0_CONFLICT_CNT` reader - The register records the number of access-conflicts when bus0 accesses L1-ICache0."] +pub type L1_IBUS0_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when bus0 accesses L1-ICache0."] + #[inline(always)] + pub fn l1_ibus0_conflict_cnt(&self) -> L1_IBUS0_CONFLICT_CNT_R { + L1_IBUS0_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS0_ACS_CONFLICT_CNT") + .field( + "l1_ibus0_conflict_cnt", + &format_args!("{}", self.l1_ibus0_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS0_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS0_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus0_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS0_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS0_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L1_IBUS0_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus0_acs_hit_cnt.rs b/esp32p4/src/cache/l1_ibus0_acs_hit_cnt.rs new file mode 100644 index 0000000000..0f10f7952e --- /dev/null +++ b/esp32p4/src/cache/l1_ibus0_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS0_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS0_HIT_CNT` reader - The register records the number of hits when bus0 accesses L1-ICache0."] +pub type L1_IBUS0_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when bus0 accesses L1-ICache0."] + #[inline(always)] + pub fn l1_ibus0_hit_cnt(&self) -> L1_IBUS0_HIT_CNT_R { + L1_IBUS0_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS0_ACS_HIT_CNT") + .field( + "l1_ibus0_hit_cnt", + &format_args!("{}", self.l1_ibus0_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS0_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS0_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus0_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS0_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS0_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L1_IBUS0_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus0_acs_miss_cnt.rs b/esp32p4/src/cache/l1_ibus0_acs_miss_cnt.rs new file mode 100644 index 0000000000..27b5499d8c --- /dev/null +++ b/esp32p4/src/cache/l1_ibus0_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS0_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS0_MISS_CNT` reader - The register records the number of missing when bus0 accesses L1-ICache0."] +pub type L1_IBUS0_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when bus0 accesses L1-ICache0."] + #[inline(always)] + pub fn l1_ibus0_miss_cnt(&self) -> L1_IBUS0_MISS_CNT_R { + L1_IBUS0_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS0_ACS_MISS_CNT") + .field( + "l1_ibus0_miss_cnt", + &format_args!("{}", self.l1_ibus0_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS0_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS0_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus0_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS0_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS0_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L1_IBUS0_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus0_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_ibus0_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..8ee0f19e7e --- /dev/null +++ b/esp32p4/src/cache/l1_ibus0_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS0_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS0_NXTLVL_RD_CNT` reader - The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0."] +pub type L1_IBUS0_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0."] + #[inline(always)] + pub fn l1_ibus0_nxtlvl_rd_cnt(&self) -> L1_IBUS0_NXTLVL_RD_CNT_R { + L1_IBUS0_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS0_ACS_NXTLVL_RD_CNT") + .field( + "l1_ibus0_nxtlvl_rd_cnt", + &format_args!("{}", self.l1_ibus0_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS0_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS0_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus0_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS0_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS0_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L1_IBUS0_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus1_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_ibus1_acs_conflict_cnt.rs new file mode 100644 index 0000000000..946f66a485 --- /dev/null +++ b/esp32p4/src/cache/l1_ibus1_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS1_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS1_CONFLICT_CNT` reader - The register records the number of access-conflicts when bus1 accesses L1-ICache1."] +pub type L1_IBUS1_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when bus1 accesses L1-ICache1."] + #[inline(always)] + pub fn l1_ibus1_conflict_cnt(&self) -> L1_IBUS1_CONFLICT_CNT_R { + L1_IBUS1_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS1_ACS_CONFLICT_CNT") + .field( + "l1_ibus1_conflict_cnt", + &format_args!("{}", self.l1_ibus1_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS1_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS1_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus1_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS1_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS1_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L1_IBUS1_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus1_acs_hit_cnt.rs b/esp32p4/src/cache/l1_ibus1_acs_hit_cnt.rs new file mode 100644 index 0000000000..616ce5fe80 --- /dev/null +++ b/esp32p4/src/cache/l1_ibus1_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS1_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS1_HIT_CNT` reader - The register records the number of hits when bus1 accesses L1-ICache1."] +pub type L1_IBUS1_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when bus1 accesses L1-ICache1."] + #[inline(always)] + pub fn l1_ibus1_hit_cnt(&self) -> L1_IBUS1_HIT_CNT_R { + L1_IBUS1_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS1_ACS_HIT_CNT") + .field( + "l1_ibus1_hit_cnt", + &format_args!("{}", self.l1_ibus1_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS1_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS1_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus1_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS1_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS1_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L1_IBUS1_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus1_acs_miss_cnt.rs b/esp32p4/src/cache/l1_ibus1_acs_miss_cnt.rs new file mode 100644 index 0000000000..bd7805059e --- /dev/null +++ b/esp32p4/src/cache/l1_ibus1_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS1_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS1_MISS_CNT` reader - The register records the number of missing when bus1 accesses L1-ICache1."] +pub type L1_IBUS1_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when bus1 accesses L1-ICache1."] + #[inline(always)] + pub fn l1_ibus1_miss_cnt(&self) -> L1_IBUS1_MISS_CNT_R { + L1_IBUS1_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS1_ACS_MISS_CNT") + .field( + "l1_ibus1_miss_cnt", + &format_args!("{}", self.l1_ibus1_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS1_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS1_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus1_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS1_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS1_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L1_IBUS1_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus1_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_ibus1_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..2361f84fc6 --- /dev/null +++ b/esp32p4/src/cache/l1_ibus1_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS1_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS1_NXTLVL_RD_CNT` reader - The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1."] +pub type L1_IBUS1_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1."] + #[inline(always)] + pub fn l1_ibus1_nxtlvl_rd_cnt(&self) -> L1_IBUS1_NXTLVL_RD_CNT_R { + L1_IBUS1_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS1_ACS_NXTLVL_RD_CNT") + .field( + "l1_ibus1_nxtlvl_rd_cnt", + &format_args!("{}", self.l1_ibus1_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS1_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS1_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus1_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS1_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS1_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L1_IBUS1_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus2_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_ibus2_acs_conflict_cnt.rs new file mode 100644 index 0000000000..18a1e72fe8 --- /dev/null +++ b/esp32p4/src/cache/l1_ibus2_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS2_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS2_CONFLICT_CNT` reader - The register records the number of access-conflicts when bus2 accesses L1-ICache2."] +pub type L1_IBUS2_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when bus2 accesses L1-ICache2."] + #[inline(always)] + pub fn l1_ibus2_conflict_cnt(&self) -> L1_IBUS2_CONFLICT_CNT_R { + L1_IBUS2_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS2_ACS_CONFLICT_CNT") + .field( + "l1_ibus2_conflict_cnt", + &format_args!("{}", self.l1_ibus2_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS2_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS2_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus2_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS2_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS2_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L1_IBUS2_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus2_acs_hit_cnt.rs b/esp32p4/src/cache/l1_ibus2_acs_hit_cnt.rs new file mode 100644 index 0000000000..18f8c59ad4 --- /dev/null +++ b/esp32p4/src/cache/l1_ibus2_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS2_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS2_HIT_CNT` reader - The register records the number of hits when bus2 accesses L1-ICache2."] +pub type L1_IBUS2_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when bus2 accesses L1-ICache2."] + #[inline(always)] + pub fn l1_ibus2_hit_cnt(&self) -> L1_IBUS2_HIT_CNT_R { + L1_IBUS2_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS2_ACS_HIT_CNT") + .field( + "l1_ibus2_hit_cnt", + &format_args!("{}", self.l1_ibus2_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS2_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS2_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus2_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS2_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS2_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L1_IBUS2_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus2_acs_miss_cnt.rs b/esp32p4/src/cache/l1_ibus2_acs_miss_cnt.rs new file mode 100644 index 0000000000..e7a918fc52 --- /dev/null +++ b/esp32p4/src/cache/l1_ibus2_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS2_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS2_MISS_CNT` reader - The register records the number of missing when bus2 accesses L1-ICache2."] +pub type L1_IBUS2_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when bus2 accesses L1-ICache2."] + #[inline(always)] + pub fn l1_ibus2_miss_cnt(&self) -> L1_IBUS2_MISS_CNT_R { + L1_IBUS2_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS2_ACS_MISS_CNT") + .field( + "l1_ibus2_miss_cnt", + &format_args!("{}", self.l1_ibus2_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS2_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS2_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus2_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS2_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS2_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L1_IBUS2_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus2_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_ibus2_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..bda174c843 --- /dev/null +++ b/esp32p4/src/cache/l1_ibus2_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS2_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS2_NXTLVL_RD_CNT` reader - The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2."] +pub type L1_IBUS2_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2."] + #[inline(always)] + pub fn l1_ibus2_nxtlvl_rd_cnt(&self) -> L1_IBUS2_NXTLVL_RD_CNT_R { + L1_IBUS2_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS2_ACS_NXTLVL_RD_CNT") + .field( + "l1_ibus2_nxtlvl_rd_cnt", + &format_args!("{}", self.l1_ibus2_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS2_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS2_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus2_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS2_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS2_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L1_IBUS2_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus3_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_ibus3_acs_conflict_cnt.rs new file mode 100644 index 0000000000..9820536e3e --- /dev/null +++ b/esp32p4/src/cache/l1_ibus3_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS3_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS3_CONFLICT_CNT` reader - The register records the number of access-conflicts when bus3 accesses L1-ICache3."] +pub type L1_IBUS3_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when bus3 accesses L1-ICache3."] + #[inline(always)] + pub fn l1_ibus3_conflict_cnt(&self) -> L1_IBUS3_CONFLICT_CNT_R { + L1_IBUS3_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS3_ACS_CONFLICT_CNT") + .field( + "l1_ibus3_conflict_cnt", + &format_args!("{}", self.l1_ibus3_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS3_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS3_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus3_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS3_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS3_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L1_IBUS3_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus3_acs_hit_cnt.rs b/esp32p4/src/cache/l1_ibus3_acs_hit_cnt.rs new file mode 100644 index 0000000000..469383d709 --- /dev/null +++ b/esp32p4/src/cache/l1_ibus3_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS3_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS3_HIT_CNT` reader - The register records the number of hits when bus3 accesses L1-ICache3."] +pub type L1_IBUS3_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when bus3 accesses L1-ICache3."] + #[inline(always)] + pub fn l1_ibus3_hit_cnt(&self) -> L1_IBUS3_HIT_CNT_R { + L1_IBUS3_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS3_ACS_HIT_CNT") + .field( + "l1_ibus3_hit_cnt", + &format_args!("{}", self.l1_ibus3_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS3_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS3_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus3_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS3_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS3_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L1_IBUS3_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus3_acs_miss_cnt.rs b/esp32p4/src/cache/l1_ibus3_acs_miss_cnt.rs new file mode 100644 index 0000000000..c9d546368e --- /dev/null +++ b/esp32p4/src/cache/l1_ibus3_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS3_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS3_MISS_CNT` reader - The register records the number of missing when bus3 accesses L1-ICache3."] +pub type L1_IBUS3_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when bus3 accesses L1-ICache3."] + #[inline(always)] + pub fn l1_ibus3_miss_cnt(&self) -> L1_IBUS3_MISS_CNT_R { + L1_IBUS3_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS3_ACS_MISS_CNT") + .field( + "l1_ibus3_miss_cnt", + &format_args!("{}", self.l1_ibus3_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS3_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS3_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus3_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS3_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS3_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L1_IBUS3_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_ibus3_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_ibus3_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..884c279b2c --- /dev/null +++ b/esp32p4/src/cache/l1_ibus3_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_IBUS3_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L1_IBUS3_NXTLVL_RD_CNT` reader - The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3."] +pub type L1_IBUS3_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3."] + #[inline(always)] + pub fn l1_ibus3_nxtlvl_rd_cnt(&self) -> L1_IBUS3_NXTLVL_RD_CNT_R { + L1_IBUS3_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_IBUS3_ACS_NXTLVL_RD_CNT") + .field( + "l1_ibus3_nxtlvl_rd_cnt", + &format_args!("{}", self.l1_ibus3_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_IBUS3_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L1_IBUS3_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_ibus3_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L1_IBUS3_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L1_IBUS3_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L1_IBUS3_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_acs_fail_addr.rs b/esp32p4/src/cache/l1_icache0_acs_fail_addr.rs new file mode 100644 index 0000000000..7abf1e3d95 --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_acs_fail_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE0_ACS_FAIL_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE0_FAIL_ADDR` reader - The register records the address of fail-access when cache0 accesses L1-ICache."] +pub type L1_ICACHE0_FAIL_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the address of fail-access when cache0 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache0_fail_addr(&self) -> L1_ICACHE0_FAIL_ADDR_R { + L1_ICACHE0_FAIL_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_ACS_FAIL_ADDR") + .field( + "l1_icache0_fail_addr", + &format_args!("{}", self.l1_icache0_fail_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_acs_fail_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_ACS_FAIL_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_ACS_FAIL_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_acs_fail_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_ACS_FAIL_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE0_ACS_FAIL_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE0_ACS_FAIL_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_acs_fail_id_attr.rs b/esp32p4/src/cache/l1_icache0_acs_fail_id_attr.rs new file mode 100644 index 0000000000..ef42b7268a --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_acs_fail_id_attr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `L1_ICACHE0_ACS_FAIL_ID_ATTR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE0_FAIL_ID` reader - The register records the ID of fail-access when cache0 accesses L1-ICache."] +pub type L1_ICACHE0_FAIL_ID_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_FAIL_ATTR` reader - The register records the attribution of fail-access when cache0 accesses L1-ICache."] +pub type L1_ICACHE0_FAIL_ATTR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - The register records the ID of fail-access when cache0 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache0_fail_id(&self) -> L1_ICACHE0_FAIL_ID_R { + L1_ICACHE0_FAIL_ID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - The register records the attribution of fail-access when cache0 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache0_fail_attr(&self) -> L1_ICACHE0_FAIL_ATTR_R { + L1_ICACHE0_FAIL_ATTR_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_ACS_FAIL_ID_ATTR") + .field( + "l1_icache0_fail_id", + &format_args!("{}", self.l1_icache0_fail_id().bits()), + ) + .field( + "l1_icache0_fail_attr", + &format_args!("{}", self.l1_icache0_fail_attr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_acs_fail_id_attr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_acs_fail_id_attr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE0_ACS_FAIL_ID_ATTR to value 0"] +impl crate::Resettable for L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_autoload_ctrl.rs b/esp32p4/src/cache/l1_icache0_autoload_ctrl.rs new file mode 100644 index 0000000000..1c27fcb8dd --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_autoload_ctrl.rs @@ -0,0 +1,184 @@ +#[doc = "Register `L1_ICACHE0_AUTOLOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_AUTOLOAD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_ENA` reader - The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable."] +pub type L1_ICACHE0_AUTOLOAD_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_ENA` writer - The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable."] +pub type L1_ICACHE0_AUTOLOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_DONE` reader - The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished."] +pub type L1_ICACHE0_AUTOLOAD_DONE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_ORDER` reader - The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending."] +pub type L1_ICACHE0_AUTOLOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_ORDER` writer - The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending."] +pub type L1_ICACHE0_AUTOLOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_TRIGGER_MODE` reader - The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] +pub type L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_TRIGGER_MODE` writer - The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] +pub type L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT0_ENA` reader - The bit is used to enable the first section for autoload operation on L1-ICache0."] +pub type L1_ICACHE0_AUTOLOAD_SCT0_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT0_ENA` writer - The bit is used to enable the first section for autoload operation on L1-ICache0."] +pub type L1_ICACHE0_AUTOLOAD_SCT0_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT1_ENA` reader - The bit is used to enable the second section for autoload operation on L1-ICache0."] +pub type L1_ICACHE0_AUTOLOAD_SCT1_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT1_ENA` writer - The bit is used to enable the second section for autoload operation on L1-ICache0."] +pub type L1_ICACHE0_AUTOLOAD_SCT1_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_RGID` reader - The bit is used to set the gid of l1 icache0 autoload."] +pub type L1_ICACHE0_AUTOLOAD_RGID_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_RGID` writer - The bit is used to set the gid of l1 icache0 autoload."] +pub type L1_ICACHE0_AUTOLOAD_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable."] + #[inline(always)] + pub fn l1_icache0_autoload_ena(&self) -> L1_ICACHE0_AUTOLOAD_ENA_R { + L1_ICACHE0_AUTOLOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_icache0_autoload_done(&self) -> L1_ICACHE0_AUTOLOAD_DONE_R { + L1_ICACHE0_AUTOLOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending."] + #[inline(always)] + pub fn l1_icache0_autoload_order(&self) -> L1_ICACHE0_AUTOLOAD_ORDER_R { + L1_ICACHE0_AUTOLOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] + #[inline(always)] + pub fn l1_icache0_autoload_trigger_mode(&self) -> L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_R { + L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 8 - The bit is used to enable the first section for autoload operation on L1-ICache0."] + #[inline(always)] + pub fn l1_icache0_autoload_sct0_ena(&self) -> L1_ICACHE0_AUTOLOAD_SCT0_ENA_R { + L1_ICACHE0_AUTOLOAD_SCT0_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The bit is used to enable the second section for autoload operation on L1-ICache0."] + #[inline(always)] + pub fn l1_icache0_autoload_sct1_ena(&self) -> L1_ICACHE0_AUTOLOAD_SCT1_ENA_R { + L1_ICACHE0_AUTOLOAD_SCT1_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:13 - The bit is used to set the gid of l1 icache0 autoload."] + #[inline(always)] + pub fn l1_icache0_autoload_rgid(&self) -> L1_ICACHE0_AUTOLOAD_RGID_R { + L1_ICACHE0_AUTOLOAD_RGID_R::new(((self.bits >> 10) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_AUTOLOAD_CTRL") + .field( + "l1_icache0_autoload_ena", + &format_args!("{}", self.l1_icache0_autoload_ena().bit()), + ) + .field( + "l1_icache0_autoload_done", + &format_args!("{}", self.l1_icache0_autoload_done().bit()), + ) + .field( + "l1_icache0_autoload_order", + &format_args!("{}", self.l1_icache0_autoload_order().bit()), + ) + .field( + "l1_icache0_autoload_trigger_mode", + &format_args!("{}", self.l1_icache0_autoload_trigger_mode().bits()), + ) + .field( + "l1_icache0_autoload_sct0_ena", + &format_args!("{}", self.l1_icache0_autoload_sct0_ena().bit()), + ) + .field( + "l1_icache0_autoload_sct1_ena", + &format_args!("{}", self.l1_icache0_autoload_sct1_ena().bit()), + ) + .field( + "l1_icache0_autoload_rgid", + &format_args!("{}", self.l1_icache0_autoload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_autoload_ena( + &mut self, + ) -> L1_ICACHE0_AUTOLOAD_ENA_W { + L1_ICACHE0_AUTOLOAD_ENA_W::new(self, 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_autoload_order( + &mut self, + ) -> L1_ICACHE0_AUTOLOAD_ORDER_W { + L1_ICACHE0_AUTOLOAD_ORDER_W::new(self, 2) + } + #[doc = "Bits 3:4 - The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_autoload_trigger_mode( + &mut self, + ) -> L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_W { + L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_W::new(self, 3) + } + #[doc = "Bit 8 - The bit is used to enable the first section for autoload operation on L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_autoload_sct0_ena( + &mut self, + ) -> L1_ICACHE0_AUTOLOAD_SCT0_ENA_W { + L1_ICACHE0_AUTOLOAD_SCT0_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The bit is used to enable the second section for autoload operation on L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_autoload_sct1_ena( + &mut self, + ) -> L1_ICACHE0_AUTOLOAD_SCT1_ENA_W { + L1_ICACHE0_AUTOLOAD_SCT1_ENA_W::new(self, 9) + } + #[doc = "Bits 10:13 - The bit is used to set the gid of l1 icache0 autoload."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_autoload_rgid( + &mut self, + ) -> L1_ICACHE0_AUTOLOAD_RGID_W { + L1_ICACHE0_AUTOLOAD_RGID_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_AUTOLOAD_CTRL_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_AUTOLOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_autoload_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_AUTOLOAD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_autoload_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_AUTOLOAD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_AUTOLOAD_CTRL to value 0x02"] +impl crate::Resettable for L1_ICACHE0_AUTOLOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l1_icache0_autoload_sct0_addr.rs b/esp32p4/src/cache/l1_icache0_autoload_sct0_addr.rs new file mode 100644 index 0000000000..1943da4bad --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_autoload_sct0_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE0_AUTOLOAD_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_AUTOLOAD_SCT0_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE0_AUTOLOAD_SCT0_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT0_ADDR` writer - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE0_AUTOLOAD_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l1_icache0_autoload_sct0_addr(&self) -> L1_ICACHE0_AUTOLOAD_SCT0_ADDR_R { + L1_ICACHE0_AUTOLOAD_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT0_ADDR") + .field( + "l1_icache0_autoload_sct0_addr", + &format_args!("{}", self.l1_icache0_autoload_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_autoload_sct0_addr( + &mut self, + ) -> L1_ICACHE0_AUTOLOAD_SCT0_ADDR_W { + L1_ICACHE0_AUTOLOAD_SCT0_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct0_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct0_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_autoload_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_autoload_sct0_addr::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_AUTOLOAD_SCT0_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_autoload_sct0_size.rs b/esp32p4/src/cache/l1_icache0_autoload_sct0_size.rs new file mode 100644 index 0000000000..c8b4ed4da5 --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_autoload_sct0_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE0_AUTOLOAD_SCT0_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_AUTOLOAD_SCT0_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT0_SIZE` reader - Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE0_AUTOLOAD_SCT0_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT0_SIZE` writer - Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE0_AUTOLOAD_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l1_icache0_autoload_sct0_size(&self) -> L1_ICACHE0_AUTOLOAD_SCT0_SIZE_R { + L1_ICACHE0_AUTOLOAD_SCT0_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT0_SIZE") + .field( + "l1_icache0_autoload_sct0_size", + &format_args!("{}", self.l1_icache0_autoload_sct0_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_autoload_sct0_size( + &mut self, + ) -> L1_ICACHE0_AUTOLOAD_SCT0_SIZE_W { + L1_ICACHE0_AUTOLOAD_SCT0_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct0_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct0_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_autoload_sct0_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_autoload_sct0_size::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_AUTOLOAD_SCT0_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_autoload_sct1_addr.rs b/esp32p4/src/cache/l1_icache0_autoload_sct1_addr.rs new file mode 100644 index 0000000000..6d537df8f0 --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_autoload_sct1_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE0_AUTOLOAD_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_AUTOLOAD_SCT1_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_ICACHE0_AUTOLOAD_SCT1_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT1_ADDR` writer - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_ICACHE0_AUTOLOAD_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + pub fn l1_icache0_autoload_sct1_addr(&self) -> L1_ICACHE0_AUTOLOAD_SCT1_ADDR_R { + L1_ICACHE0_AUTOLOAD_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT1_ADDR") + .field( + "l1_icache0_autoload_sct1_addr", + &format_args!("{}", self.l1_icache0_autoload_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_autoload_sct1_addr( + &mut self, + ) -> L1_ICACHE0_AUTOLOAD_SCT1_ADDR_W { + L1_ICACHE0_AUTOLOAD_SCT1_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct1_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct1_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_autoload_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_autoload_sct1_addr::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_AUTOLOAD_SCT1_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_autoload_sct1_size.rs b/esp32p4/src/cache/l1_icache0_autoload_sct1_size.rs new file mode 100644 index 0000000000..219a14b4a6 --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_autoload_sct1_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE0_AUTOLOAD_SCT1_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_AUTOLOAD_SCT1_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT1_SIZE` reader - Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_ICACHE0_AUTOLOAD_SCT1_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT1_SIZE` writer - Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_ICACHE0_AUTOLOAD_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + pub fn l1_icache0_autoload_sct1_size(&self) -> L1_ICACHE0_AUTOLOAD_SCT1_SIZE_R { + L1_ICACHE0_AUTOLOAD_SCT1_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT1_SIZE") + .field( + "l1_icache0_autoload_sct1_size", + &format_args!("{}", self.l1_icache0_autoload_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_autoload_sct1_size( + &mut self, + ) -> L1_ICACHE0_AUTOLOAD_SCT1_SIZE_W { + L1_ICACHE0_AUTOLOAD_SCT1_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct1_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_autoload_sct1_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_autoload_sct1_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_autoload_sct1_size::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_AUTOLOAD_SCT1_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_preload_addr.rs b/esp32p4/src/cache/l1_icache0_preload_addr.rs new file mode 100644 index 0000000000..a294b87d11 --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_preload_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE0_PRELOAD_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_PRELOAD_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_PRELOAD_ADDR` reader - Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG"] +pub type L1_ICACHE0_PRELOAD_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_PRELOAD_ADDR` writer - Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG"] +pub type L1_ICACHE0_PRELOAD_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG"] + #[inline(always)] + pub fn l1_icache0_preload_addr(&self) -> L1_ICACHE0_PRELOAD_ADDR_R { + L1_ICACHE0_PRELOAD_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_PRELOAD_ADDR") + .field( + "l1_icache0_preload_addr", + &format_args!("{}", self.l1_icache0_preload_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache0_preload_addr( + &mut self, + ) -> L1_ICACHE0_PRELOAD_ADDR_W { + L1_ICACHE0_PRELOAD_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_preload_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_preload_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_PRELOAD_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_PRELOAD_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_preload_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_PRELOAD_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_preload_addr::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_PRELOAD_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_PRELOAD_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE0_PRELOAD_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_preload_ctrl.rs b/esp32p4/src/cache/l1_icache0_preload_ctrl.rs new file mode 100644 index 0000000000..30f61161d2 --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_preload_ctrl.rs @@ -0,0 +1,121 @@ +#[doc = "Register `L1_ICACHE0_PRELOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_PRELOAD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_PRELOAD_ENA` reader - The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done."] +pub type L1_ICACHE0_PRELOAD_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_PRELOAD_ENA` writer - The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done."] +pub type L1_ICACHE0_PRELOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_PRELOAD_DONE` reader - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] +pub type L1_ICACHE0_PRELOAD_DONE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_PRELOAD_ORDER` reader - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] +pub type L1_ICACHE0_PRELOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_PRELOAD_ORDER` writer - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] +pub type L1_ICACHE0_PRELOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_PRELOAD_RGID` reader - The bit is used to set the gid of l1 icache0 preload."] +pub type L1_ICACHE0_PRELOAD_RGID_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_PRELOAD_RGID` writer - The bit is used to set the gid of l1 icache0 preload."] +pub type L1_ICACHE0_PRELOAD_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done."] + #[inline(always)] + pub fn l1_icache0_preload_ena(&self) -> L1_ICACHE0_PRELOAD_ENA_R { + L1_ICACHE0_PRELOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_icache0_preload_done(&self) -> L1_ICACHE0_PRELOAD_DONE_R { + L1_ICACHE0_PRELOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] + #[inline(always)] + pub fn l1_icache0_preload_order(&self) -> L1_ICACHE0_PRELOAD_ORDER_R { + L1_ICACHE0_PRELOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of l1 icache0 preload."] + #[inline(always)] + pub fn l1_icache0_preload_rgid(&self) -> L1_ICACHE0_PRELOAD_RGID_R { + L1_ICACHE0_PRELOAD_RGID_R::new(((self.bits >> 3) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_PRELOAD_CTRL") + .field( + "l1_icache0_preload_ena", + &format_args!("{}", self.l1_icache0_preload_ena().bit()), + ) + .field( + "l1_icache0_preload_done", + &format_args!("{}", self.l1_icache0_preload_done().bit()), + ) + .field( + "l1_icache0_preload_order", + &format_args!("{}", self.l1_icache0_preload_order().bit()), + ) + .field( + "l1_icache0_preload_rgid", + &format_args!("{}", self.l1_icache0_preload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_preload_ena( + &mut self, + ) -> L1_ICACHE0_PRELOAD_ENA_W { + L1_ICACHE0_PRELOAD_ENA_W::new(self, 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_preload_order( + &mut self, + ) -> L1_ICACHE0_PRELOAD_ORDER_W { + L1_ICACHE0_PRELOAD_ORDER_W::new(self, 2) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of l1 icache0 preload."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_preload_rgid( + &mut self, + ) -> L1_ICACHE0_PRELOAD_RGID_W { + L1_ICACHE0_PRELOAD_RGID_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_preload_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_preload_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_PRELOAD_CTRL_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_PRELOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_preload_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_PRELOAD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_preload_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_PRELOAD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_PRELOAD_CTRL to value 0x02"] +impl crate::Resettable for L1_ICACHE0_PRELOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l1_icache0_preload_size.rs b/esp32p4/src/cache/l1_icache0_preload_size.rs new file mode 100644 index 0000000000..d4c67ec2dd --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_preload_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE0_PRELOAD_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_PRELOAD_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_PRELOAD_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG"] +pub type L1_ICACHE0_PRELOAD_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_PRELOAD_SIZE` writer - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG"] +pub type L1_ICACHE0_PRELOAD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG"] + #[inline(always)] + pub fn l1_icache0_preload_size(&self) -> L1_ICACHE0_PRELOAD_SIZE_R { + L1_ICACHE0_PRELOAD_SIZE_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_PRELOAD_SIZE") + .field( + "l1_icache0_preload_size", + &format_args!("{}", self.l1_icache0_preload_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache0_preload_size( + &mut self, + ) -> L1_ICACHE0_PRELOAD_SIZE_W { + L1_ICACHE0_PRELOAD_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_preload_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_preload_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_PRELOAD_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_PRELOAD_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_preload_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_PRELOAD_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_preload_size::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_PRELOAD_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_PRELOAD_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE0_PRELOAD_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_prelock_conf.rs b/esp32p4/src/cache/l1_icache0_prelock_conf.rs new file mode 100644 index 0000000000..1251b425ac --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_prelock_conf.rs @@ -0,0 +1,110 @@ +#[doc = "Register `L1_ICACHE0_PRELOCK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_PRELOCK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT0_EN` reader - The bit is used to enable the first section of prelock function on L1-ICache0."] +pub type L1_ICACHE0_PRELOCK_SCT0_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT0_EN` writer - The bit is used to enable the first section of prelock function on L1-ICache0."] +pub type L1_ICACHE0_PRELOCK_SCT0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT1_EN` reader - The bit is used to enable the second section of prelock function on L1-ICache0."] +pub type L1_ICACHE0_PRELOCK_SCT1_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT1_EN` writer - The bit is used to enable the second section of prelock function on L1-ICache0."] +pub type L1_ICACHE0_PRELOCK_SCT1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_PRELOCK_RGID` reader - The bit is used to set the gid of l1 icache0 prelock."] +pub type L1_ICACHE0_PRELOCK_RGID_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_PRELOCK_RGID` writer - The bit is used to set the gid of l1 icache0 prelock."] +pub type L1_ICACHE0_PRELOCK_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-ICache0."] + #[inline(always)] + pub fn l1_icache0_prelock_sct0_en(&self) -> L1_ICACHE0_PRELOCK_SCT0_EN_R { + L1_ICACHE0_PRELOCK_SCT0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable the second section of prelock function on L1-ICache0."] + #[inline(always)] + pub fn l1_icache0_prelock_sct1_en(&self) -> L1_ICACHE0_PRELOCK_SCT1_EN_R { + L1_ICACHE0_PRELOCK_SCT1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The bit is used to set the gid of l1 icache0 prelock."] + #[inline(always)] + pub fn l1_icache0_prelock_rgid(&self) -> L1_ICACHE0_PRELOCK_RGID_R { + L1_ICACHE0_PRELOCK_RGID_R::new(((self.bits >> 2) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_PRELOCK_CONF") + .field( + "l1_icache0_prelock_sct0_en", + &format_args!("{}", self.l1_icache0_prelock_sct0_en().bit()), + ) + .field( + "l1_icache0_prelock_sct1_en", + &format_args!("{}", self.l1_icache0_prelock_sct1_en().bit()), + ) + .field( + "l1_icache0_prelock_rgid", + &format_args!("{}", self.l1_icache0_prelock_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_prelock_sct0_en( + &mut self, + ) -> L1_ICACHE0_PRELOCK_SCT0_EN_W { + L1_ICACHE0_PRELOCK_SCT0_EN_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable the second section of prelock function on L1-ICache0."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_prelock_sct1_en( + &mut self, + ) -> L1_ICACHE0_PRELOCK_SCT1_EN_W { + L1_ICACHE0_PRELOCK_SCT1_EN_W::new(self, 1) + } + #[doc = "Bits 2:5 - The bit is used to set the gid of l1 icache0 prelock."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_prelock_rgid( + &mut self, + ) -> L1_ICACHE0_PRELOCK_RGID_W { + L1_ICACHE0_PRELOCK_RGID_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_PRELOCK_CONF_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_PRELOCK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_prelock_conf::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_PRELOCK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_prelock_conf::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_PRELOCK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_PRELOCK_CONF to value 0"] +impl crate::Resettable for L1_ICACHE0_PRELOCK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_prelock_sct0_addr.rs b/esp32p4/src/cache/l1_icache0_prelock_sct0_addr.rs new file mode 100644 index 0000000000..e8172f9817 --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_prelock_sct0_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE0_PRELOCK_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_PRELOCK_SCT0_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG"] +pub type L1_ICACHE0_PRELOCK_SCT0_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT0_ADDR` writer - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG"] +pub type L1_ICACHE0_PRELOCK_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG"] + #[inline(always)] + pub fn l1_icache0_prelock_sct0_addr(&self) -> L1_ICACHE0_PRELOCK_SCT0_ADDR_R { + L1_ICACHE0_PRELOCK_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_PRELOCK_SCT0_ADDR") + .field( + "l1_icache0_prelock_sct0_addr", + &format_args!("{}", self.l1_icache0_prelock_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache0_prelock_sct0_addr( + &mut self, + ) -> L1_ICACHE0_PRELOCK_SCT0_ADDR_W { + L1_ICACHE0_PRELOCK_SCT0_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct0_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_sct0_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_prelock_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_prelock_sct0_addr::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_PRELOCK_SCT0_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_prelock_sct1_addr.rs b/esp32p4/src/cache/l1_icache0_prelock_sct1_addr.rs new file mode 100644 index 0000000000..1c82369876 --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_prelock_sct1_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE0_PRELOCK_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_PRELOCK_SCT1_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG"] +pub type L1_ICACHE0_PRELOCK_SCT1_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT1_ADDR` writer - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG"] +pub type L1_ICACHE0_PRELOCK_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG"] + #[inline(always)] + pub fn l1_icache0_prelock_sct1_addr(&self) -> L1_ICACHE0_PRELOCK_SCT1_ADDR_R { + L1_ICACHE0_PRELOCK_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_PRELOCK_SCT1_ADDR") + .field( + "l1_icache0_prelock_sct1_addr", + &format_args!("{}", self.l1_icache0_prelock_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache0_prelock_sct1_addr( + &mut self, + ) -> L1_ICACHE0_PRELOCK_SCT1_ADDR_W { + L1_ICACHE0_PRELOCK_SCT1_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct1_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_sct1_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_prelock_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_prelock_sct1_addr::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_PRELOCK_SCT1_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache0_prelock_sct_size.rs b/esp32p4/src/cache/l1_icache0_prelock_sct_size.rs new file mode 100644 index 0000000000..8a36518833 --- /dev/null +++ b/esp32p4/src/cache/l1_icache0_prelock_sct_size.rs @@ -0,0 +1,89 @@ +#[doc = "Register `L1_ICACHE0_PRELOCK_SCT_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE0_PRELOCK_SCT_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT0_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG"] +pub type L1_ICACHE0_PRELOCK_SCT0_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT0_SIZE` writer - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG"] +pub type L1_ICACHE0_PRELOCK_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT1_SIZE` reader - Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG"] +pub type L1_ICACHE0_PRELOCK_SCT1_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE0_PRELOCK_SCT1_SIZE` writer - Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG"] +pub type L1_ICACHE0_PRELOCK_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG"] + #[inline(always)] + pub fn l1_icache0_prelock_sct0_size(&self) -> L1_ICACHE0_PRELOCK_SCT0_SIZE_R { + L1_ICACHE0_PRELOCK_SCT0_SIZE_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG"] + #[inline(always)] + pub fn l1_icache0_prelock_sct1_size(&self) -> L1_ICACHE0_PRELOCK_SCT1_SIZE_R { + L1_ICACHE0_PRELOCK_SCT1_SIZE_R::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE0_PRELOCK_SCT_SIZE") + .field( + "l1_icache0_prelock_sct0_size", + &format_args!("{}", self.l1_icache0_prelock_sct0_size().bits()), + ) + .field( + "l1_icache0_prelock_sct1_size", + &format_args!("{}", self.l1_icache0_prelock_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache0_prelock_sct0_size( + &mut self, + ) -> L1_ICACHE0_PRELOCK_SCT0_SIZE_W { + L1_ICACHE0_PRELOCK_SCT0_SIZE_W::new(self, 0) + } + #[doc = "Bits 16:29 - Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache0_prelock_sct1_size( + &mut self, + ) -> L1_ICACHE0_PRELOCK_SCT1_SIZE_W { + L1_ICACHE0_PRELOCK_SCT1_SIZE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 0 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache0_prelock_sct_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache0_prelock_sct_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache0_prelock_sct_size::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE0_PRELOCK_SCT_SIZE to value 0x3fff_3fff"] +impl crate::Resettable for L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0x3fff_3fff; +} diff --git a/esp32p4/src/cache/l1_icache1_acs_fail_addr.rs b/esp32p4/src/cache/l1_icache1_acs_fail_addr.rs new file mode 100644 index 0000000000..5484b49b72 --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_acs_fail_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE1_ACS_FAIL_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE1_FAIL_ADDR` reader - The register records the address of fail-access when cache1 accesses L1-ICache."] +pub type L1_ICACHE1_FAIL_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the address of fail-access when cache1 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache1_fail_addr(&self) -> L1_ICACHE1_FAIL_ADDR_R { + L1_ICACHE1_FAIL_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_ACS_FAIL_ADDR") + .field( + "l1_icache1_fail_addr", + &format_args!("{}", self.l1_icache1_fail_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_acs_fail_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_ACS_FAIL_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_ACS_FAIL_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_acs_fail_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_ACS_FAIL_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE1_ACS_FAIL_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE1_ACS_FAIL_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache1_acs_fail_id_attr.rs b/esp32p4/src/cache/l1_icache1_acs_fail_id_attr.rs new file mode 100644 index 0000000000..e34a74cdd5 --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_acs_fail_id_attr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `L1_ICACHE1_ACS_FAIL_ID_ATTR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE1_FAIL_ID` reader - The register records the ID of fail-access when cache1 accesses L1-ICache."] +pub type L1_ICACHE1_FAIL_ID_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_FAIL_ATTR` reader - The register records the attribution of fail-access when cache1 accesses L1-ICache."] +pub type L1_ICACHE1_FAIL_ATTR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - The register records the ID of fail-access when cache1 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache1_fail_id(&self) -> L1_ICACHE1_FAIL_ID_R { + L1_ICACHE1_FAIL_ID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - The register records the attribution of fail-access when cache1 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache1_fail_attr(&self) -> L1_ICACHE1_FAIL_ATTR_R { + L1_ICACHE1_FAIL_ATTR_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_ACS_FAIL_ID_ATTR") + .field( + "l1_icache1_fail_id", + &format_args!("{}", self.l1_icache1_fail_id().bits()), + ) + .field( + "l1_icache1_fail_attr", + &format_args!("{}", self.l1_icache1_fail_attr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_acs_fail_id_attr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_acs_fail_id_attr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE1_ACS_FAIL_ID_ATTR to value 0"] +impl crate::Resettable for L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache1_autoload_ctrl.rs b/esp32p4/src/cache/l1_icache1_autoload_ctrl.rs new file mode 100644 index 0000000000..6bde8b0e2b --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_autoload_ctrl.rs @@ -0,0 +1,184 @@ +#[doc = "Register `L1_ICACHE1_AUTOLOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_AUTOLOAD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_ENA` reader - The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable."] +pub type L1_ICACHE1_AUTOLOAD_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_ENA` writer - The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable."] +pub type L1_ICACHE1_AUTOLOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_DONE` reader - The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished."] +pub type L1_ICACHE1_AUTOLOAD_DONE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_ORDER` reader - The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending."] +pub type L1_ICACHE1_AUTOLOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_ORDER` writer - The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending."] +pub type L1_ICACHE1_AUTOLOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_TRIGGER_MODE` reader - The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] +pub type L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_TRIGGER_MODE` writer - The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] +pub type L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT0_ENA` reader - The bit is used to enable the first section for autoload operation on L1-ICache1."] +pub type L1_ICACHE1_AUTOLOAD_SCT0_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT0_ENA` writer - The bit is used to enable the first section for autoload operation on L1-ICache1."] +pub type L1_ICACHE1_AUTOLOAD_SCT0_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT1_ENA` reader - The bit is used to enable the second section for autoload operation on L1-ICache1."] +pub type L1_ICACHE1_AUTOLOAD_SCT1_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT1_ENA` writer - The bit is used to enable the second section for autoload operation on L1-ICache1."] +pub type L1_ICACHE1_AUTOLOAD_SCT1_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_RGID` reader - The bit is used to set the gid of l1 icache1 autoload."] +pub type L1_ICACHE1_AUTOLOAD_RGID_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_RGID` writer - The bit is used to set the gid of l1 icache1 autoload."] +pub type L1_ICACHE1_AUTOLOAD_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable."] + #[inline(always)] + pub fn l1_icache1_autoload_ena(&self) -> L1_ICACHE1_AUTOLOAD_ENA_R { + L1_ICACHE1_AUTOLOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_icache1_autoload_done(&self) -> L1_ICACHE1_AUTOLOAD_DONE_R { + L1_ICACHE1_AUTOLOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending."] + #[inline(always)] + pub fn l1_icache1_autoload_order(&self) -> L1_ICACHE1_AUTOLOAD_ORDER_R { + L1_ICACHE1_AUTOLOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] + #[inline(always)] + pub fn l1_icache1_autoload_trigger_mode(&self) -> L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_R { + L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 8 - The bit is used to enable the first section for autoload operation on L1-ICache1."] + #[inline(always)] + pub fn l1_icache1_autoload_sct0_ena(&self) -> L1_ICACHE1_AUTOLOAD_SCT0_ENA_R { + L1_ICACHE1_AUTOLOAD_SCT0_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The bit is used to enable the second section for autoload operation on L1-ICache1."] + #[inline(always)] + pub fn l1_icache1_autoload_sct1_ena(&self) -> L1_ICACHE1_AUTOLOAD_SCT1_ENA_R { + L1_ICACHE1_AUTOLOAD_SCT1_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:13 - The bit is used to set the gid of l1 icache1 autoload."] + #[inline(always)] + pub fn l1_icache1_autoload_rgid(&self) -> L1_ICACHE1_AUTOLOAD_RGID_R { + L1_ICACHE1_AUTOLOAD_RGID_R::new(((self.bits >> 10) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_AUTOLOAD_CTRL") + .field( + "l1_icache1_autoload_ena", + &format_args!("{}", self.l1_icache1_autoload_ena().bit()), + ) + .field( + "l1_icache1_autoload_done", + &format_args!("{}", self.l1_icache1_autoload_done().bit()), + ) + .field( + "l1_icache1_autoload_order", + &format_args!("{}", self.l1_icache1_autoload_order().bit()), + ) + .field( + "l1_icache1_autoload_trigger_mode", + &format_args!("{}", self.l1_icache1_autoload_trigger_mode().bits()), + ) + .field( + "l1_icache1_autoload_sct0_ena", + &format_args!("{}", self.l1_icache1_autoload_sct0_ena().bit()), + ) + .field( + "l1_icache1_autoload_sct1_ena", + &format_args!("{}", self.l1_icache1_autoload_sct1_ena().bit()), + ) + .field( + "l1_icache1_autoload_rgid", + &format_args!("{}", self.l1_icache1_autoload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_autoload_ena( + &mut self, + ) -> L1_ICACHE1_AUTOLOAD_ENA_W { + L1_ICACHE1_AUTOLOAD_ENA_W::new(self, 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_autoload_order( + &mut self, + ) -> L1_ICACHE1_AUTOLOAD_ORDER_W { + L1_ICACHE1_AUTOLOAD_ORDER_W::new(self, 2) + } + #[doc = "Bits 3:4 - The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_autoload_trigger_mode( + &mut self, + ) -> L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_W { + L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_W::new(self, 3) + } + #[doc = "Bit 8 - The bit is used to enable the first section for autoload operation on L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_autoload_sct0_ena( + &mut self, + ) -> L1_ICACHE1_AUTOLOAD_SCT0_ENA_W { + L1_ICACHE1_AUTOLOAD_SCT0_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The bit is used to enable the second section for autoload operation on L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_autoload_sct1_ena( + &mut self, + ) -> L1_ICACHE1_AUTOLOAD_SCT1_ENA_W { + L1_ICACHE1_AUTOLOAD_SCT1_ENA_W::new(self, 9) + } + #[doc = "Bits 10:13 - The bit is used to set the gid of l1 icache1 autoload."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_autoload_rgid( + &mut self, + ) -> L1_ICACHE1_AUTOLOAD_RGID_W { + L1_ICACHE1_AUTOLOAD_RGID_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_AUTOLOAD_CTRL_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_AUTOLOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_autoload_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_AUTOLOAD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_autoload_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_AUTOLOAD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_AUTOLOAD_CTRL to value 0x02"] +impl crate::Resettable for L1_ICACHE1_AUTOLOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l1_icache1_autoload_sct0_addr.rs b/esp32p4/src/cache/l1_icache1_autoload_sct0_addr.rs new file mode 100644 index 0000000000..ab6aef30a8 --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_autoload_sct0_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE1_AUTOLOAD_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_AUTOLOAD_SCT0_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE1_AUTOLOAD_SCT0_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT0_ADDR` writer - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE1_AUTOLOAD_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l1_icache1_autoload_sct0_addr(&self) -> L1_ICACHE1_AUTOLOAD_SCT0_ADDR_R { + L1_ICACHE1_AUTOLOAD_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT0_ADDR") + .field( + "l1_icache1_autoload_sct0_addr", + &format_args!("{}", self.l1_icache1_autoload_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_autoload_sct0_addr( + &mut self, + ) -> L1_ICACHE1_AUTOLOAD_SCT0_ADDR_W { + L1_ICACHE1_AUTOLOAD_SCT0_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct0_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct0_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_autoload_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_autoload_sct0_addr::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_AUTOLOAD_SCT0_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache1_autoload_sct0_size.rs b/esp32p4/src/cache/l1_icache1_autoload_sct0_size.rs new file mode 100644 index 0000000000..f1a576c128 --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_autoload_sct0_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE1_AUTOLOAD_SCT0_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_AUTOLOAD_SCT0_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT0_SIZE` reader - Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE1_AUTOLOAD_SCT0_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT0_SIZE` writer - Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE1_AUTOLOAD_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l1_icache1_autoload_sct0_size(&self) -> L1_ICACHE1_AUTOLOAD_SCT0_SIZE_R { + L1_ICACHE1_AUTOLOAD_SCT0_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT0_SIZE") + .field( + "l1_icache1_autoload_sct0_size", + &format_args!("{}", self.l1_icache1_autoload_sct0_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_autoload_sct0_size( + &mut self, + ) -> L1_ICACHE1_AUTOLOAD_SCT0_SIZE_W { + L1_ICACHE1_AUTOLOAD_SCT0_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct0_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct0_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_autoload_sct0_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_autoload_sct0_size::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_AUTOLOAD_SCT0_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache1_autoload_sct1_addr.rs b/esp32p4/src/cache/l1_icache1_autoload_sct1_addr.rs new file mode 100644 index 0000000000..3224875df5 --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_autoload_sct1_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE1_AUTOLOAD_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_AUTOLOAD_SCT1_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_ICACHE1_AUTOLOAD_SCT1_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT1_ADDR` writer - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_ICACHE1_AUTOLOAD_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + pub fn l1_icache1_autoload_sct1_addr(&self) -> L1_ICACHE1_AUTOLOAD_SCT1_ADDR_R { + L1_ICACHE1_AUTOLOAD_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT1_ADDR") + .field( + "l1_icache1_autoload_sct1_addr", + &format_args!("{}", self.l1_icache1_autoload_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_autoload_sct1_addr( + &mut self, + ) -> L1_ICACHE1_AUTOLOAD_SCT1_ADDR_W { + L1_ICACHE1_AUTOLOAD_SCT1_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct1_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct1_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_autoload_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_autoload_sct1_addr::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_AUTOLOAD_SCT1_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache1_autoload_sct1_size.rs b/esp32p4/src/cache/l1_icache1_autoload_sct1_size.rs new file mode 100644 index 0000000000..d5c1503275 --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_autoload_sct1_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE1_AUTOLOAD_SCT1_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_AUTOLOAD_SCT1_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT1_SIZE` reader - Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_ICACHE1_AUTOLOAD_SCT1_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_AUTOLOAD_SCT1_SIZE` writer - Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_ICACHE1_AUTOLOAD_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + pub fn l1_icache1_autoload_sct1_size(&self) -> L1_ICACHE1_AUTOLOAD_SCT1_SIZE_R { + L1_ICACHE1_AUTOLOAD_SCT1_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT1_SIZE") + .field( + "l1_icache1_autoload_sct1_size", + &format_args!("{}", self.l1_icache1_autoload_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_autoload_sct1_size( + &mut self, + ) -> L1_ICACHE1_AUTOLOAD_SCT1_SIZE_W { + L1_ICACHE1_AUTOLOAD_SCT1_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct1_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_autoload_sct1_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_autoload_sct1_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_autoload_sct1_size::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_AUTOLOAD_SCT1_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache1_preload_addr.rs b/esp32p4/src/cache/l1_icache1_preload_addr.rs new file mode 100644 index 0000000000..9c410256f2 --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_preload_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE1_PRELOAD_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_PRELOAD_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_PRELOAD_ADDR` reader - Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG"] +pub type L1_ICACHE1_PRELOAD_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_PRELOAD_ADDR` writer - Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG"] +pub type L1_ICACHE1_PRELOAD_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG"] + #[inline(always)] + pub fn l1_icache1_preload_addr(&self) -> L1_ICACHE1_PRELOAD_ADDR_R { + L1_ICACHE1_PRELOAD_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_PRELOAD_ADDR") + .field( + "l1_icache1_preload_addr", + &format_args!("{}", self.l1_icache1_preload_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache1_preload_addr( + &mut self, + ) -> L1_ICACHE1_PRELOAD_ADDR_W { + L1_ICACHE1_PRELOAD_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_preload_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_preload_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_PRELOAD_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_PRELOAD_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_preload_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_PRELOAD_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_preload_addr::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_PRELOAD_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_PRELOAD_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE1_PRELOAD_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache1_preload_ctrl.rs b/esp32p4/src/cache/l1_icache1_preload_ctrl.rs new file mode 100644 index 0000000000..8a88e69ec0 --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_preload_ctrl.rs @@ -0,0 +1,121 @@ +#[doc = "Register `L1_ICACHE1_PRELOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_PRELOAD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_PRELOAD_ENA` reader - The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done."] +pub type L1_ICACHE1_PRELOAD_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PRELOAD_ENA` writer - The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done."] +pub type L1_ICACHE1_PRELOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_PRELOAD_DONE` reader - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] +pub type L1_ICACHE1_PRELOAD_DONE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PRELOAD_ORDER` reader - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] +pub type L1_ICACHE1_PRELOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PRELOAD_ORDER` writer - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] +pub type L1_ICACHE1_PRELOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_PRELOAD_RGID` reader - The bit is used to set the gid of l1 icache1 preload."] +pub type L1_ICACHE1_PRELOAD_RGID_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_PRELOAD_RGID` writer - The bit is used to set the gid of l1 icache1 preload."] +pub type L1_ICACHE1_PRELOAD_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done."] + #[inline(always)] + pub fn l1_icache1_preload_ena(&self) -> L1_ICACHE1_PRELOAD_ENA_R { + L1_ICACHE1_PRELOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_icache1_preload_done(&self) -> L1_ICACHE1_PRELOAD_DONE_R { + L1_ICACHE1_PRELOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] + #[inline(always)] + pub fn l1_icache1_preload_order(&self) -> L1_ICACHE1_PRELOAD_ORDER_R { + L1_ICACHE1_PRELOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of l1 icache1 preload."] + #[inline(always)] + pub fn l1_icache1_preload_rgid(&self) -> L1_ICACHE1_PRELOAD_RGID_R { + L1_ICACHE1_PRELOAD_RGID_R::new(((self.bits >> 3) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_PRELOAD_CTRL") + .field( + "l1_icache1_preload_ena", + &format_args!("{}", self.l1_icache1_preload_ena().bit()), + ) + .field( + "l1_icache1_preload_done", + &format_args!("{}", self.l1_icache1_preload_done().bit()), + ) + .field( + "l1_icache1_preload_order", + &format_args!("{}", self.l1_icache1_preload_order().bit()), + ) + .field( + "l1_icache1_preload_rgid", + &format_args!("{}", self.l1_icache1_preload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_preload_ena( + &mut self, + ) -> L1_ICACHE1_PRELOAD_ENA_W { + L1_ICACHE1_PRELOAD_ENA_W::new(self, 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_preload_order( + &mut self, + ) -> L1_ICACHE1_PRELOAD_ORDER_W { + L1_ICACHE1_PRELOAD_ORDER_W::new(self, 2) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of l1 icache1 preload."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_preload_rgid( + &mut self, + ) -> L1_ICACHE1_PRELOAD_RGID_W { + L1_ICACHE1_PRELOAD_RGID_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_preload_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_preload_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_PRELOAD_CTRL_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_PRELOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_preload_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_PRELOAD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_preload_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_PRELOAD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_PRELOAD_CTRL to value 0x02"] +impl crate::Resettable for L1_ICACHE1_PRELOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l1_icache1_preload_size.rs b/esp32p4/src/cache/l1_icache1_preload_size.rs new file mode 100644 index 0000000000..8fa0de287f --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_preload_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE1_PRELOAD_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_PRELOAD_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_PRELOAD_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG"] +pub type L1_ICACHE1_PRELOAD_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_PRELOAD_SIZE` writer - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG"] +pub type L1_ICACHE1_PRELOAD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG"] + #[inline(always)] + pub fn l1_icache1_preload_size(&self) -> L1_ICACHE1_PRELOAD_SIZE_R { + L1_ICACHE1_PRELOAD_SIZE_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_PRELOAD_SIZE") + .field( + "l1_icache1_preload_size", + &format_args!("{}", self.l1_icache1_preload_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache1_preload_size( + &mut self, + ) -> L1_ICACHE1_PRELOAD_SIZE_W { + L1_ICACHE1_PRELOAD_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_preload_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_preload_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_PRELOAD_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_PRELOAD_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_preload_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_PRELOAD_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_preload_size::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_PRELOAD_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_PRELOAD_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE1_PRELOAD_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache1_prelock_conf.rs b/esp32p4/src/cache/l1_icache1_prelock_conf.rs new file mode 100644 index 0000000000..2500ba2a0b --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_prelock_conf.rs @@ -0,0 +1,110 @@ +#[doc = "Register `L1_ICACHE1_PRELOCK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_PRELOCK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT0_EN` reader - The bit is used to enable the first section of prelock function on L1-ICache1."] +pub type L1_ICACHE1_PRELOCK_SCT0_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT0_EN` writer - The bit is used to enable the first section of prelock function on L1-ICache1."] +pub type L1_ICACHE1_PRELOCK_SCT0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT1_EN` reader - The bit is used to enable the second section of prelock function on L1-ICache1."] +pub type L1_ICACHE1_PRELOCK_SCT1_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT1_EN` writer - The bit is used to enable the second section of prelock function on L1-ICache1."] +pub type L1_ICACHE1_PRELOCK_SCT1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_PRELOCK_RGID` reader - The bit is used to set the gid of l1 icache1 prelock."] +pub type L1_ICACHE1_PRELOCK_RGID_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_PRELOCK_RGID` writer - The bit is used to set the gid of l1 icache1 prelock."] +pub type L1_ICACHE1_PRELOCK_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-ICache1."] + #[inline(always)] + pub fn l1_icache1_prelock_sct0_en(&self) -> L1_ICACHE1_PRELOCK_SCT0_EN_R { + L1_ICACHE1_PRELOCK_SCT0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable the second section of prelock function on L1-ICache1."] + #[inline(always)] + pub fn l1_icache1_prelock_sct1_en(&self) -> L1_ICACHE1_PRELOCK_SCT1_EN_R { + L1_ICACHE1_PRELOCK_SCT1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The bit is used to set the gid of l1 icache1 prelock."] + #[inline(always)] + pub fn l1_icache1_prelock_rgid(&self) -> L1_ICACHE1_PRELOCK_RGID_R { + L1_ICACHE1_PRELOCK_RGID_R::new(((self.bits >> 2) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_PRELOCK_CONF") + .field( + "l1_icache1_prelock_sct0_en", + &format_args!("{}", self.l1_icache1_prelock_sct0_en().bit()), + ) + .field( + "l1_icache1_prelock_sct1_en", + &format_args!("{}", self.l1_icache1_prelock_sct1_en().bit()), + ) + .field( + "l1_icache1_prelock_rgid", + &format_args!("{}", self.l1_icache1_prelock_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_prelock_sct0_en( + &mut self, + ) -> L1_ICACHE1_PRELOCK_SCT0_EN_W { + L1_ICACHE1_PRELOCK_SCT0_EN_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable the second section of prelock function on L1-ICache1."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_prelock_sct1_en( + &mut self, + ) -> L1_ICACHE1_PRELOCK_SCT1_EN_W { + L1_ICACHE1_PRELOCK_SCT1_EN_W::new(self, 1) + } + #[doc = "Bits 2:5 - The bit is used to set the gid of l1 icache1 prelock."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_prelock_rgid( + &mut self, + ) -> L1_ICACHE1_PRELOCK_RGID_W { + L1_ICACHE1_PRELOCK_RGID_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_PRELOCK_CONF_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_PRELOCK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_prelock_conf::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_PRELOCK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_prelock_conf::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_PRELOCK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_PRELOCK_CONF to value 0"] +impl crate::Resettable for L1_ICACHE1_PRELOCK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache1_prelock_sct0_addr.rs b/esp32p4/src/cache/l1_icache1_prelock_sct0_addr.rs new file mode 100644 index 0000000000..71a64831f3 --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_prelock_sct0_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE1_PRELOCK_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_PRELOCK_SCT0_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG"] +pub type L1_ICACHE1_PRELOCK_SCT0_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT0_ADDR` writer - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG"] +pub type L1_ICACHE1_PRELOCK_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG"] + #[inline(always)] + pub fn l1_icache1_prelock_sct0_addr(&self) -> L1_ICACHE1_PRELOCK_SCT0_ADDR_R { + L1_ICACHE1_PRELOCK_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_PRELOCK_SCT0_ADDR") + .field( + "l1_icache1_prelock_sct0_addr", + &format_args!("{}", self.l1_icache1_prelock_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache1_prelock_sct0_addr( + &mut self, + ) -> L1_ICACHE1_PRELOCK_SCT0_ADDR_W { + L1_ICACHE1_PRELOCK_SCT0_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct0_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_sct0_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_prelock_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_prelock_sct0_addr::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_PRELOCK_SCT0_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache1_prelock_sct1_addr.rs b/esp32p4/src/cache/l1_icache1_prelock_sct1_addr.rs new file mode 100644 index 0000000000..8757f49867 --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_prelock_sct1_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L1_ICACHE1_PRELOCK_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_PRELOCK_SCT1_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG"] +pub type L1_ICACHE1_PRELOCK_SCT1_ADDR_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT1_ADDR` writer - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG"] +pub type L1_ICACHE1_PRELOCK_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG"] + #[inline(always)] + pub fn l1_icache1_prelock_sct1_addr(&self) -> L1_ICACHE1_PRELOCK_SCT1_ADDR_R { + L1_ICACHE1_PRELOCK_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_PRELOCK_SCT1_ADDR") + .field( + "l1_icache1_prelock_sct1_addr", + &format_args!("{}", self.l1_icache1_prelock_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache1_prelock_sct1_addr( + &mut self, + ) -> L1_ICACHE1_PRELOCK_SCT1_ADDR_W { + L1_ICACHE1_PRELOCK_SCT1_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct1_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_sct1_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_prelock_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_prelock_sct1_addr::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_PRELOCK_SCT1_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache1_prelock_sct_size.rs b/esp32p4/src/cache/l1_icache1_prelock_sct_size.rs new file mode 100644 index 0000000000..d0f55e5b40 --- /dev/null +++ b/esp32p4/src/cache/l1_icache1_prelock_sct_size.rs @@ -0,0 +1,89 @@ +#[doc = "Register `L1_ICACHE1_PRELOCK_SCT_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE1_PRELOCK_SCT_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT0_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG"] +pub type L1_ICACHE1_PRELOCK_SCT0_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT0_SIZE` writer - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG"] +pub type L1_ICACHE1_PRELOCK_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT1_SIZE` reader - Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG"] +pub type L1_ICACHE1_PRELOCK_SCT1_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_PRELOCK_SCT1_SIZE` writer - Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG"] +pub type L1_ICACHE1_PRELOCK_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG"] + #[inline(always)] + pub fn l1_icache1_prelock_sct0_size(&self) -> L1_ICACHE1_PRELOCK_SCT0_SIZE_R { + L1_ICACHE1_PRELOCK_SCT0_SIZE_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG"] + #[inline(always)] + pub fn l1_icache1_prelock_sct1_size(&self) -> L1_ICACHE1_PRELOCK_SCT1_SIZE_R { + L1_ICACHE1_PRELOCK_SCT1_SIZE_R::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE1_PRELOCK_SCT_SIZE") + .field( + "l1_icache1_prelock_sct0_size", + &format_args!("{}", self.l1_icache1_prelock_sct0_size().bits()), + ) + .field( + "l1_icache1_prelock_sct1_size", + &format_args!("{}", self.l1_icache1_prelock_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache1_prelock_sct0_size( + &mut self, + ) -> L1_ICACHE1_PRELOCK_SCT0_SIZE_W { + L1_ICACHE1_PRELOCK_SCT0_SIZE_W::new(self, 0) + } + #[doc = "Bits 16:29 - Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l1_icache1_prelock_sct1_size( + &mut self, + ) -> L1_ICACHE1_PRELOCK_SCT1_SIZE_W { + L1_ICACHE1_PRELOCK_SCT1_SIZE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache 1 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache1_prelock_sct_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache1_prelock_sct_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache1_prelock_sct_size::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE1_PRELOCK_SCT_SIZE to value 0x3fff_3fff"] +impl crate::Resettable for L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0x3fff_3fff; +} diff --git a/esp32p4/src/cache/l1_icache2_acs_fail_addr.rs b/esp32p4/src/cache/l1_icache2_acs_fail_addr.rs new file mode 100644 index 0000000000..0c4bc336bf --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_acs_fail_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE2_ACS_FAIL_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_FAIL_ADDR` reader - The register records the address of fail-access when cache2 accesses L1-ICache."] +pub type L1_ICACHE2_FAIL_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the address of fail-access when cache2 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache2_fail_addr(&self) -> L1_ICACHE2_FAIL_ADDR_R { + L1_ICACHE2_FAIL_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_ACS_FAIL_ADDR") + .field( + "l1_icache2_fail_addr", + &format_args!("{}", self.l1_icache2_fail_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_acs_fail_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_ACS_FAIL_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_ACS_FAIL_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_acs_fail_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_ACS_FAIL_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_ACS_FAIL_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE2_ACS_FAIL_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache2_acs_fail_id_attr.rs b/esp32p4/src/cache/l1_icache2_acs_fail_id_attr.rs new file mode 100644 index 0000000000..a0f7d1277b --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_acs_fail_id_attr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `L1_ICACHE2_ACS_FAIL_ID_ATTR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_FAIL_ID` reader - The register records the ID of fail-access when cache2 accesses L1-ICache."] +pub type L1_ICACHE2_FAIL_ID_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE2_FAIL_ATTR` reader - The register records the attribution of fail-access when cache2 accesses L1-ICache."] +pub type L1_ICACHE2_FAIL_ATTR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - The register records the ID of fail-access when cache2 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache2_fail_id(&self) -> L1_ICACHE2_FAIL_ID_R { + L1_ICACHE2_FAIL_ID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - The register records the attribution of fail-access when cache2 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache2_fail_attr(&self) -> L1_ICACHE2_FAIL_ATTR_R { + L1_ICACHE2_FAIL_ATTR_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_ACS_FAIL_ID_ATTR") + .field( + "l1_icache2_fail_id", + &format_args!("{}", self.l1_icache2_fail_id().bits()), + ) + .field( + "l1_icache2_fail_attr", + &format_args!("{}", self.l1_icache2_fail_attr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_acs_fail_id_attr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_acs_fail_id_attr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_ACS_FAIL_ID_ATTR to value 0"] +impl crate::Resettable for L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache2_autoload_ctrl.rs b/esp32p4/src/cache/l1_icache2_autoload_ctrl.rs new file mode 100644 index 0000000000..b8a44e73dd --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_autoload_ctrl.rs @@ -0,0 +1,105 @@ +#[doc = "Register `L1_ICACHE2_AUTOLOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_AUTOLOAD_ENA` reader - The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, 0: disable."] +pub type L1_ICACHE2_AUTOLOAD_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_AUTOLOAD_DONE` reader - The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished."] +pub type L1_ICACHE2_AUTOLOAD_DONE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_AUTOLOAD_ORDER` reader - The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending."] +pub type L1_ICACHE2_AUTOLOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_AUTOLOAD_TRIGGER_MODE` reader - The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] +pub type L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE2_AUTOLOAD_SCT0_ENA` reader - The bit is used to enable the first section for autoload operation on L1-ICache2."] +pub type L1_ICACHE2_AUTOLOAD_SCT0_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_AUTOLOAD_SCT1_ENA` reader - The bit is used to enable the second section for autoload operation on L1-ICache2."] +pub type L1_ICACHE2_AUTOLOAD_SCT1_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_AUTOLOAD_RGID` reader - The bit is used to set the gid of l1 icache2 autoload."] +pub type L1_ICACHE2_AUTOLOAD_RGID_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, 0: disable."] + #[inline(always)] + pub fn l1_icache2_autoload_ena(&self) -> L1_ICACHE2_AUTOLOAD_ENA_R { + L1_ICACHE2_AUTOLOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_icache2_autoload_done(&self) -> L1_ICACHE2_AUTOLOAD_DONE_R { + L1_ICACHE2_AUTOLOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending."] + #[inline(always)] + pub fn l1_icache2_autoload_order(&self) -> L1_ICACHE2_AUTOLOAD_ORDER_R { + L1_ICACHE2_AUTOLOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] + #[inline(always)] + pub fn l1_icache2_autoload_trigger_mode(&self) -> L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_R { + L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 8 - The bit is used to enable the first section for autoload operation on L1-ICache2."] + #[inline(always)] + pub fn l1_icache2_autoload_sct0_ena(&self) -> L1_ICACHE2_AUTOLOAD_SCT0_ENA_R { + L1_ICACHE2_AUTOLOAD_SCT0_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The bit is used to enable the second section for autoload operation on L1-ICache2."] + #[inline(always)] + pub fn l1_icache2_autoload_sct1_ena(&self) -> L1_ICACHE2_AUTOLOAD_SCT1_ENA_R { + L1_ICACHE2_AUTOLOAD_SCT1_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:13 - The bit is used to set the gid of l1 icache2 autoload."] + #[inline(always)] + pub fn l1_icache2_autoload_rgid(&self) -> L1_ICACHE2_AUTOLOAD_RGID_R { + L1_ICACHE2_AUTOLOAD_RGID_R::new(((self.bits >> 10) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_AUTOLOAD_CTRL") + .field( + "l1_icache2_autoload_ena", + &format_args!("{}", self.l1_icache2_autoload_ena().bit()), + ) + .field( + "l1_icache2_autoload_done", + &format_args!("{}", self.l1_icache2_autoload_done().bit()), + ) + .field( + "l1_icache2_autoload_order", + &format_args!("{}", self.l1_icache2_autoload_order().bit()), + ) + .field( + "l1_icache2_autoload_trigger_mode", + &format_args!("{}", self.l1_icache2_autoload_trigger_mode().bits()), + ) + .field( + "l1_icache2_autoload_sct0_ena", + &format_args!("{}", self.l1_icache2_autoload_sct0_ena().bit()), + ) + .field( + "l1_icache2_autoload_sct1_ena", + &format_args!("{}", self.l1_icache2_autoload_sct1_ena().bit()), + ) + .field( + "l1_icache2_autoload_rgid", + &format_args!("{}", self.l1_icache2_autoload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_ctrl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_AUTOLOAD_CTRL_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_autoload_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_AUTOLOAD_CTRL_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_AUTOLOAD_CTRL to value 0x02"] +impl crate::Resettable for L1_ICACHE2_AUTOLOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l1_icache2_autoload_sct0_addr.rs b/esp32p4/src/cache/l1_icache2_autoload_sct0_addr.rs new file mode 100644 index 0000000000..e1172cec51 --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_autoload_sct0_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE2_AUTOLOAD_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_AUTOLOAD_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE2_AUTOLOAD_SCT0_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l1_icache2_autoload_sct0_addr(&self) -> L1_ICACHE2_AUTOLOAD_SCT0_ADDR_R { + L1_ICACHE2_AUTOLOAD_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT0_ADDR") + .field( + "l1_icache2_autoload_sct0_addr", + &format_args!("{}", self.l1_icache2_autoload_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct0_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_autoload_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_AUTOLOAD_SCT0_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache2_autoload_sct0_size.rs b/esp32p4/src/cache/l1_icache2_autoload_sct0_size.rs new file mode 100644 index 0000000000..9fb284d3b0 --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_autoload_sct0_size.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE2_AUTOLOAD_SCT0_SIZE` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_AUTOLOAD_SCT0_SIZE` reader - Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE2_AUTOLOAD_SCT0_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l1_icache2_autoload_sct0_size(&self) -> L1_ICACHE2_AUTOLOAD_SCT0_SIZE_R { + L1_ICACHE2_AUTOLOAD_SCT0_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT0_SIZE") + .field( + "l1_icache2_autoload_sct0_size", + &format_args!("{}", self.l1_icache2_autoload_sct0_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct0_size::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_autoload_sct0_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_AUTOLOAD_SCT0_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache2_autoload_sct1_addr.rs b/esp32p4/src/cache/l1_icache2_autoload_sct1_addr.rs new file mode 100644 index 0000000000..176436cdce --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_autoload_sct1_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE2_AUTOLOAD_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_AUTOLOAD_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_ICACHE2_AUTOLOAD_SCT1_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + pub fn l1_icache2_autoload_sct1_addr(&self) -> L1_ICACHE2_AUTOLOAD_SCT1_ADDR_R { + L1_ICACHE2_AUTOLOAD_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT1_ADDR") + .field( + "l1_icache2_autoload_sct1_addr", + &format_args!("{}", self.l1_icache2_autoload_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct1_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_autoload_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_AUTOLOAD_SCT1_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache2_autoload_sct1_size.rs b/esp32p4/src/cache/l1_icache2_autoload_sct1_size.rs new file mode 100644 index 0000000000..d3dc8d39f9 --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_autoload_sct1_size.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE2_AUTOLOAD_SCT1_SIZE` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_AUTOLOAD_SCT1_SIZE` reader - Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_ICACHE2_AUTOLOAD_SCT1_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + pub fn l1_icache2_autoload_sct1_size(&self) -> L1_ICACHE2_AUTOLOAD_SCT1_SIZE_R { + L1_ICACHE2_AUTOLOAD_SCT1_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT1_SIZE") + .field( + "l1_icache2_autoload_sct1_size", + &format_args!("{}", self.l1_icache2_autoload_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct1_size::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_autoload_sct1_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_AUTOLOAD_SCT1_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache2_preload_addr.rs b/esp32p4/src/cache/l1_icache2_preload_addr.rs new file mode 100644 index 0000000000..008484ca3e --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_preload_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE2_PRELOAD_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_PRELOAD_ADDR` reader - Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG"] +pub type L1_ICACHE2_PRELOAD_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG"] + #[inline(always)] + pub fn l1_icache2_preload_addr(&self) -> L1_ICACHE2_PRELOAD_ADDR_R { + L1_ICACHE2_PRELOAD_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_PRELOAD_ADDR") + .field( + "l1_icache2_preload_addr", + &format_args!("{}", self.l1_icache2_preload_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_PRELOAD_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_PRELOAD_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_preload_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_PRELOAD_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_PRELOAD_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE2_PRELOAD_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache2_preload_ctrl.rs b/esp32p4/src/cache/l1_icache2_preload_ctrl.rs new file mode 100644 index 0000000000..ad3b2fed9e --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_preload_ctrl.rs @@ -0,0 +1,72 @@ +#[doc = "Register `L1_ICACHE2_PRELOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_PRELOAD_ENA` reader - The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done."] +pub type L1_ICACHE2_PRELOAD_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_PRELOAD_DONE` reader - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] +pub type L1_ICACHE2_PRELOAD_DONE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_PRELOAD_ORDER` reader - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] +pub type L1_ICACHE2_PRELOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_PRELOAD_RGID` reader - The bit is used to set the gid of l1 icache2 preload."] +pub type L1_ICACHE2_PRELOAD_RGID_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done."] + #[inline(always)] + pub fn l1_icache2_preload_ena(&self) -> L1_ICACHE2_PRELOAD_ENA_R { + L1_ICACHE2_PRELOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_icache2_preload_done(&self) -> L1_ICACHE2_PRELOAD_DONE_R { + L1_ICACHE2_PRELOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] + #[inline(always)] + pub fn l1_icache2_preload_order(&self) -> L1_ICACHE2_PRELOAD_ORDER_R { + L1_ICACHE2_PRELOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of l1 icache2 preload."] + #[inline(always)] + pub fn l1_icache2_preload_rgid(&self) -> L1_ICACHE2_PRELOAD_RGID_R { + L1_ICACHE2_PRELOAD_RGID_R::new(((self.bits >> 3) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_PRELOAD_CTRL") + .field( + "l1_icache2_preload_ena", + &format_args!("{}", self.l1_icache2_preload_ena().bit()), + ) + .field( + "l1_icache2_preload_done", + &format_args!("{}", self.l1_icache2_preload_done().bit()), + ) + .field( + "l1_icache2_preload_order", + &format_args!("{}", self.l1_icache2_preload_order().bit()), + ) + .field( + "l1_icache2_preload_rgid", + &format_args!("{}", self.l1_icache2_preload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_ctrl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_PRELOAD_CTRL_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_PRELOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_preload_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_PRELOAD_CTRL_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_PRELOAD_CTRL to value 0x02"] +impl crate::Resettable for L1_ICACHE2_PRELOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l1_icache2_preload_size.rs b/esp32p4/src/cache/l1_icache2_preload_size.rs new file mode 100644 index 0000000000..4f7273c742 --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_preload_size.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE2_PRELOAD_SIZE` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_PRELOAD_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG"] +pub type L1_ICACHE2_PRELOAD_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG"] + #[inline(always)] + pub fn l1_icache2_preload_size(&self) -> L1_ICACHE2_PRELOAD_SIZE_R { + L1_ICACHE2_PRELOAD_SIZE_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_PRELOAD_SIZE") + .field( + "l1_icache2_preload_size", + &format_args!("{}", self.l1_icache2_preload_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_size::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_PRELOAD_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_PRELOAD_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_preload_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_PRELOAD_SIZE_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_PRELOAD_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE2_PRELOAD_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache2_prelock_conf.rs b/esp32p4/src/cache/l1_icache2_prelock_conf.rs new file mode 100644 index 0000000000..a142f2de4f --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_prelock_conf.rs @@ -0,0 +1,61 @@ +#[doc = "Register `L1_ICACHE2_PRELOCK_CONF` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_PRELOCK_SCT0_EN` reader - The bit is used to enable the first section of prelock function on L1-ICache2."] +pub type L1_ICACHE2_PRELOCK_SCT0_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_PRELOCK_SCT1_EN` reader - The bit is used to enable the second section of prelock function on L1-ICache2."] +pub type L1_ICACHE2_PRELOCK_SCT1_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_PRELOCK_RGID` reader - The bit is used to set the gid of l1 icache2 prelock."] +pub type L1_ICACHE2_PRELOCK_RGID_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-ICache2."] + #[inline(always)] + pub fn l1_icache2_prelock_sct0_en(&self) -> L1_ICACHE2_PRELOCK_SCT0_EN_R { + L1_ICACHE2_PRELOCK_SCT0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable the second section of prelock function on L1-ICache2."] + #[inline(always)] + pub fn l1_icache2_prelock_sct1_en(&self) -> L1_ICACHE2_PRELOCK_SCT1_EN_R { + L1_ICACHE2_PRELOCK_SCT1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The bit is used to set the gid of l1 icache2 prelock."] + #[inline(always)] + pub fn l1_icache2_prelock_rgid(&self) -> L1_ICACHE2_PRELOCK_RGID_R { + L1_ICACHE2_PRELOCK_RGID_R::new(((self.bits >> 2) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_PRELOCK_CONF") + .field( + "l1_icache2_prelock_sct0_en", + &format_args!("{}", self.l1_icache2_prelock_sct0_en().bit()), + ) + .field( + "l1_icache2_prelock_sct1_en", + &format_args!("{}", self.l1_icache2_prelock_sct1_en().bit()), + ) + .field( + "l1_icache2_prelock_rgid", + &format_args!("{}", self.l1_icache2_prelock_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_conf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_PRELOCK_CONF_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_prelock_conf::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_PRELOCK_CONF_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_PRELOCK_CONF to value 0"] +impl crate::Resettable for L1_ICACHE2_PRELOCK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache2_prelock_sct0_addr.rs b/esp32p4/src/cache/l1_icache2_prelock_sct0_addr.rs new file mode 100644 index 0000000000..1803b04c7a --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_prelock_sct0_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE2_PRELOCK_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_PRELOCK_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG"] +pub type L1_ICACHE2_PRELOCK_SCT0_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG"] + #[inline(always)] + pub fn l1_icache2_prelock_sct0_addr(&self) -> L1_ICACHE2_PRELOCK_SCT0_ADDR_R { + L1_ICACHE2_PRELOCK_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_PRELOCK_SCT0_ADDR") + .field( + "l1_icache2_prelock_sct0_addr", + &format_args!("{}", self.l1_icache2_prelock_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct0_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_prelock_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_PRELOCK_SCT0_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache2_prelock_sct1_addr.rs b/esp32p4/src/cache/l1_icache2_prelock_sct1_addr.rs new file mode 100644 index 0000000000..82b84a7c48 --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_prelock_sct1_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE2_PRELOCK_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_PRELOCK_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG"] +pub type L1_ICACHE2_PRELOCK_SCT1_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG"] + #[inline(always)] + pub fn l1_icache2_prelock_sct1_addr(&self) -> L1_ICACHE2_PRELOCK_SCT1_ADDR_R { + L1_ICACHE2_PRELOCK_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_PRELOCK_SCT1_ADDR") + .field( + "l1_icache2_prelock_sct1_addr", + &format_args!("{}", self.l1_icache2_prelock_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct1_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_prelock_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_PRELOCK_SCT1_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache2_prelock_sct_size.rs b/esp32p4/src/cache/l1_icache2_prelock_sct_size.rs new file mode 100644 index 0000000000..28fca600b6 --- /dev/null +++ b/esp32p4/src/cache/l1_icache2_prelock_sct_size.rs @@ -0,0 +1,50 @@ +#[doc = "Register `L1_ICACHE2_PRELOCK_SCT_SIZE` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE2_PRELOCK_SCT0_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG"] +pub type L1_ICACHE2_PRELOCK_SCT0_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE2_PRELOCK_SCT1_SIZE` reader - Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG"] +pub type L1_ICACHE2_PRELOCK_SCT1_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG"] + #[inline(always)] + pub fn l1_icache2_prelock_sct0_size(&self) -> L1_ICACHE2_PRELOCK_SCT0_SIZE_R { + L1_ICACHE2_PRELOCK_SCT0_SIZE_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG"] + #[inline(always)] + pub fn l1_icache2_prelock_sct1_size(&self) -> L1_ICACHE2_PRELOCK_SCT1_SIZE_R { + L1_ICACHE2_PRELOCK_SCT1_SIZE_R::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE2_PRELOCK_SCT_SIZE") + .field( + "l1_icache2_prelock_sct0_size", + &format_args!("{}", self.l1_icache2_prelock_sct0_size().bits()), + ) + .field( + "l1_icache2_prelock_sct1_size", + &format_args!("{}", self.l1_icache2_prelock_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 2 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct_size::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache2_prelock_sct_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE2_PRELOCK_SCT_SIZE to value 0x3fff_3fff"] +impl crate::Resettable for L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0x3fff_3fff; +} diff --git a/esp32p4/src/cache/l1_icache3_acs_fail_addr.rs b/esp32p4/src/cache/l1_icache3_acs_fail_addr.rs new file mode 100644 index 0000000000..f4be3dc797 --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_acs_fail_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE3_ACS_FAIL_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_FAIL_ADDR` reader - The register records the address of fail-access when cache3 accesses L1-ICache."] +pub type L1_ICACHE3_FAIL_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the address of fail-access when cache3 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache3_fail_addr(&self) -> L1_ICACHE3_FAIL_ADDR_R { + L1_ICACHE3_FAIL_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_ACS_FAIL_ADDR") + .field( + "l1_icache3_fail_addr", + &format_args!("{}", self.l1_icache3_fail_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_acs_fail_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_ACS_FAIL_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_ACS_FAIL_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_acs_fail_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_ACS_FAIL_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_ACS_FAIL_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE3_ACS_FAIL_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache3_acs_fail_id_attr.rs b/esp32p4/src/cache/l1_icache3_acs_fail_id_attr.rs new file mode 100644 index 0000000000..02566bbe43 --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_acs_fail_id_attr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `L1_ICACHE3_ACS_FAIL_ID_ATTR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_FAIL_ID` reader - The register records the ID of fail-access when cache3 accesses L1-ICache."] +pub type L1_ICACHE3_FAIL_ID_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE3_FAIL_ATTR` reader - The register records the attribution of fail-access when cache3 accesses L1-ICache."] +pub type L1_ICACHE3_FAIL_ATTR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - The register records the ID of fail-access when cache3 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache3_fail_id(&self) -> L1_ICACHE3_FAIL_ID_R { + L1_ICACHE3_FAIL_ID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - The register records the attribution of fail-access when cache3 accesses L1-ICache."] + #[inline(always)] + pub fn l1_icache3_fail_attr(&self) -> L1_ICACHE3_FAIL_ATTR_R { + L1_ICACHE3_FAIL_ATTR_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_ACS_FAIL_ID_ATTR") + .field( + "l1_icache3_fail_id", + &format_args!("{}", self.l1_icache3_fail_id().bits()), + ) + .field( + "l1_icache3_fail_attr", + &format_args!("{}", self.l1_icache3_fail_attr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_acs_fail_id_attr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_acs_fail_id_attr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_ACS_FAIL_ID_ATTR to value 0"] +impl crate::Resettable for L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache3_autoload_ctrl.rs b/esp32p4/src/cache/l1_icache3_autoload_ctrl.rs new file mode 100644 index 0000000000..47151272e5 --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_autoload_ctrl.rs @@ -0,0 +1,105 @@ +#[doc = "Register `L1_ICACHE3_AUTOLOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_AUTOLOAD_ENA` reader - The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, 0: disable."] +pub type L1_ICACHE3_AUTOLOAD_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_AUTOLOAD_DONE` reader - The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished."] +pub type L1_ICACHE3_AUTOLOAD_DONE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_AUTOLOAD_ORDER` reader - The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending."] +pub type L1_ICACHE3_AUTOLOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_AUTOLOAD_TRIGGER_MODE` reader - The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] +pub type L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE3_AUTOLOAD_SCT0_ENA` reader - The bit is used to enable the first section for autoload operation on L1-ICache3."] +pub type L1_ICACHE3_AUTOLOAD_SCT0_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_AUTOLOAD_SCT1_ENA` reader - The bit is used to enable the second section for autoload operation on L1-ICache3."] +pub type L1_ICACHE3_AUTOLOAD_SCT1_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_AUTOLOAD_RGID` reader - The bit is used to set the gid of l1 icache3 autoload."] +pub type L1_ICACHE3_AUTOLOAD_RGID_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, 0: disable."] + #[inline(always)] + pub fn l1_icache3_autoload_ena(&self) -> L1_ICACHE3_AUTOLOAD_ENA_R { + L1_ICACHE3_AUTOLOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_icache3_autoload_done(&self) -> L1_ICACHE3_AUTOLOAD_DONE_R { + L1_ICACHE3_AUTOLOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending."] + #[inline(always)] + pub fn l1_icache3_autoload_order(&self) -> L1_ICACHE3_AUTOLOAD_ORDER_R { + L1_ICACHE3_AUTOLOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] + #[inline(always)] + pub fn l1_icache3_autoload_trigger_mode(&self) -> L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_R { + L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 8 - The bit is used to enable the first section for autoload operation on L1-ICache3."] + #[inline(always)] + pub fn l1_icache3_autoload_sct0_ena(&self) -> L1_ICACHE3_AUTOLOAD_SCT0_ENA_R { + L1_ICACHE3_AUTOLOAD_SCT0_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The bit is used to enable the second section for autoload operation on L1-ICache3."] + #[inline(always)] + pub fn l1_icache3_autoload_sct1_ena(&self) -> L1_ICACHE3_AUTOLOAD_SCT1_ENA_R { + L1_ICACHE3_AUTOLOAD_SCT1_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:13 - The bit is used to set the gid of l1 icache3 autoload."] + #[inline(always)] + pub fn l1_icache3_autoload_rgid(&self) -> L1_ICACHE3_AUTOLOAD_RGID_R { + L1_ICACHE3_AUTOLOAD_RGID_R::new(((self.bits >> 10) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_AUTOLOAD_CTRL") + .field( + "l1_icache3_autoload_ena", + &format_args!("{}", self.l1_icache3_autoload_ena().bit()), + ) + .field( + "l1_icache3_autoload_done", + &format_args!("{}", self.l1_icache3_autoload_done().bit()), + ) + .field( + "l1_icache3_autoload_order", + &format_args!("{}", self.l1_icache3_autoload_order().bit()), + ) + .field( + "l1_icache3_autoload_trigger_mode", + &format_args!("{}", self.l1_icache3_autoload_trigger_mode().bits()), + ) + .field( + "l1_icache3_autoload_sct0_ena", + &format_args!("{}", self.l1_icache3_autoload_sct0_ena().bit()), + ) + .field( + "l1_icache3_autoload_sct1_ena", + &format_args!("{}", self.l1_icache3_autoload_sct1_ena().bit()), + ) + .field( + "l1_icache3_autoload_rgid", + &format_args!("{}", self.l1_icache3_autoload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_ctrl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_AUTOLOAD_CTRL_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_autoload_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_AUTOLOAD_CTRL_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_AUTOLOAD_CTRL to value 0x02"] +impl crate::Resettable for L1_ICACHE3_AUTOLOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l1_icache3_autoload_sct0_addr.rs b/esp32p4/src/cache/l1_icache3_autoload_sct0_addr.rs new file mode 100644 index 0000000000..275513f63b --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_autoload_sct0_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE3_AUTOLOAD_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_AUTOLOAD_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE3_AUTOLOAD_SCT0_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l1_icache3_autoload_sct0_addr(&self) -> L1_ICACHE3_AUTOLOAD_SCT0_ADDR_R { + L1_ICACHE3_AUTOLOAD_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT0_ADDR") + .field( + "l1_icache3_autoload_sct0_addr", + &format_args!("{}", self.l1_icache3_autoload_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct0_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_autoload_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_AUTOLOAD_SCT0_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache3_autoload_sct0_size.rs b/esp32p4/src/cache/l1_icache3_autoload_sct0_size.rs new file mode 100644 index 0000000000..92ce5a922e --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_autoload_sct0_size.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE3_AUTOLOAD_SCT0_SIZE` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_AUTOLOAD_SCT0_SIZE` reader - Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] +pub type L1_ICACHE3_AUTOLOAD_SCT0_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l1_icache3_autoload_sct0_size(&self) -> L1_ICACHE3_AUTOLOAD_SCT0_SIZE_R { + L1_ICACHE3_AUTOLOAD_SCT0_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT0_SIZE") + .field( + "l1_icache3_autoload_sct0_size", + &format_args!("{}", self.l1_icache3_autoload_sct0_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct0_size::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_autoload_sct0_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_AUTOLOAD_SCT0_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache3_autoload_sct1_addr.rs b/esp32p4/src/cache/l1_icache3_autoload_sct1_addr.rs new file mode 100644 index 0000000000..759083b415 --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_autoload_sct1_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE3_AUTOLOAD_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_AUTOLOAD_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] +pub type L1_ICACHE3_AUTOLOAD_SCT1_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + pub fn l1_icache3_autoload_sct1_addr(&self) -> L1_ICACHE3_AUTOLOAD_SCT1_ADDR_R { + L1_ICACHE3_AUTOLOAD_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT1_ADDR") + .field( + "l1_icache3_autoload_sct1_addr", + &format_args!("{}", self.l1_icache3_autoload_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct1_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_autoload_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_AUTOLOAD_SCT1_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache3_autoload_sct1_size.rs b/esp32p4/src/cache/l1_icache3_autoload_sct1_size.rs new file mode 100644 index 0000000000..24f3ba612f --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_autoload_sct1_size.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE3_AUTOLOAD_SCT1_SIZE` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_AUTOLOAD_SCT1_SIZE` reader - Reserved"] +pub type L1_ICACHE3_AUTOLOAD_SCT1_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:27 - Reserved"] + #[inline(always)] + pub fn l1_icache3_autoload_sct1_size(&self) -> L1_ICACHE3_AUTOLOAD_SCT1_SIZE_R { + L1_ICACHE3_AUTOLOAD_SCT1_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT1_SIZE") + .field( + "l1_icache3_autoload_sct1_size", + &format_args!("{}", self.l1_icache3_autoload_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct1_size::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_autoload_sct1_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_AUTOLOAD_SCT1_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache3_preload_addr.rs b/esp32p4/src/cache/l1_icache3_preload_addr.rs new file mode 100644 index 0000000000..4c45e90f8b --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_preload_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE3_PRELOAD_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_PRELOAD_ADDR` reader - Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG"] +pub type L1_ICACHE3_PRELOAD_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG"] + #[inline(always)] + pub fn l1_icache3_preload_addr(&self) -> L1_ICACHE3_PRELOAD_ADDR_R { + L1_ICACHE3_PRELOAD_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_PRELOAD_ADDR") + .field( + "l1_icache3_preload_addr", + &format_args!("{}", self.l1_icache3_preload_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_PRELOAD_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_PRELOAD_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_preload_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_PRELOAD_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_PRELOAD_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE3_PRELOAD_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache3_preload_ctrl.rs b/esp32p4/src/cache/l1_icache3_preload_ctrl.rs new file mode 100644 index 0000000000..0cae8d45a5 --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_preload_ctrl.rs @@ -0,0 +1,72 @@ +#[doc = "Register `L1_ICACHE3_PRELOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_PRELOAD_ENA` reader - The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done."] +pub type L1_ICACHE3_PRELOAD_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PRELOAD_DONE` reader - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] +pub type L1_ICACHE3_PRELOAD_DONE_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PRELOAD_ORDER` reader - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] +pub type L1_ICACHE3_PRELOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PRELOAD_RGID` reader - The bit is used to set the gid of l1 icache3 preload."] +pub type L1_ICACHE3_PRELOAD_RGID_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done."] + #[inline(always)] + pub fn l1_icache3_preload_ena(&self) -> L1_ICACHE3_PRELOAD_ENA_R { + L1_ICACHE3_PRELOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l1_icache3_preload_done(&self) -> L1_ICACHE3_PRELOAD_DONE_R { + L1_ICACHE3_PRELOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] + #[inline(always)] + pub fn l1_icache3_preload_order(&self) -> L1_ICACHE3_PRELOAD_ORDER_R { + L1_ICACHE3_PRELOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of l1 icache3 preload."] + #[inline(always)] + pub fn l1_icache3_preload_rgid(&self) -> L1_ICACHE3_PRELOAD_RGID_R { + L1_ICACHE3_PRELOAD_RGID_R::new(((self.bits >> 3) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_PRELOAD_CTRL") + .field( + "l1_icache3_preload_ena", + &format_args!("{}", self.l1_icache3_preload_ena().bit()), + ) + .field( + "l1_icache3_preload_done", + &format_args!("{}", self.l1_icache3_preload_done().bit()), + ) + .field( + "l1_icache3_preload_order", + &format_args!("{}", self.l1_icache3_preload_order().bit()), + ) + .field( + "l1_icache3_preload_rgid", + &format_args!("{}", self.l1_icache3_preload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_ctrl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_PRELOAD_CTRL_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_PRELOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_preload_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_PRELOAD_CTRL_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_PRELOAD_CTRL to value 0x02"] +impl crate::Resettable for L1_ICACHE3_PRELOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l1_icache3_preload_size.rs b/esp32p4/src/cache/l1_icache3_preload_size.rs new file mode 100644 index 0000000000..698daca1dc --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_preload_size.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE3_PRELOAD_SIZE` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_PRELOAD_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG"] +pub type L1_ICACHE3_PRELOAD_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG"] + #[inline(always)] + pub fn l1_icache3_preload_size(&self) -> L1_ICACHE3_PRELOAD_SIZE_R { + L1_ICACHE3_PRELOAD_SIZE_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_PRELOAD_SIZE") + .field( + "l1_icache3_preload_size", + &format_args!("{}", self.l1_icache3_preload_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_size::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_PRELOAD_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_PRELOAD_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_preload_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_PRELOAD_SIZE_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_PRELOAD_SIZE to value 0"] +impl crate::Resettable for L1_ICACHE3_PRELOAD_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache3_prelock_conf.rs b/esp32p4/src/cache/l1_icache3_prelock_conf.rs new file mode 100644 index 0000000000..2d6890ce36 --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_prelock_conf.rs @@ -0,0 +1,61 @@ +#[doc = "Register `L1_ICACHE3_PRELOCK_CONF` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_PRELOCK_SCT0_EN` reader - The bit is used to enable the first section of prelock function on L1-ICache3."] +pub type L1_ICACHE3_PRELOCK_SCT0_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PRELOCK_SCT1_EN` reader - The bit is used to enable the second section of prelock function on L1-ICache3."] +pub type L1_ICACHE3_PRELOCK_SCT1_EN_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PRELOCK_RGID` reader - The bit is used to set the gid of l1 icache3 prelock."] +pub type L1_ICACHE3_PRELOCK_RGID_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-ICache3."] + #[inline(always)] + pub fn l1_icache3_prelock_sct0_en(&self) -> L1_ICACHE3_PRELOCK_SCT0_EN_R { + L1_ICACHE3_PRELOCK_SCT0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable the second section of prelock function on L1-ICache3."] + #[inline(always)] + pub fn l1_icache3_prelock_sct1_en(&self) -> L1_ICACHE3_PRELOCK_SCT1_EN_R { + L1_ICACHE3_PRELOCK_SCT1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The bit is used to set the gid of l1 icache3 prelock."] + #[inline(always)] + pub fn l1_icache3_prelock_rgid(&self) -> L1_ICACHE3_PRELOCK_RGID_R { + L1_ICACHE3_PRELOCK_RGID_R::new(((self.bits >> 2) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_PRELOCK_CONF") + .field( + "l1_icache3_prelock_sct0_en", + &format_args!("{}", self.l1_icache3_prelock_sct0_en().bit()), + ) + .field( + "l1_icache3_prelock_sct1_en", + &format_args!("{}", self.l1_icache3_prelock_sct1_en().bit()), + ) + .field( + "l1_icache3_prelock_rgid", + &format_args!("{}", self.l1_icache3_prelock_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_conf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_PRELOCK_CONF_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_prelock_conf::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_PRELOCK_CONF_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_PRELOCK_CONF to value 0"] +impl crate::Resettable for L1_ICACHE3_PRELOCK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache3_prelock_sct0_addr.rs b/esp32p4/src/cache/l1_icache3_prelock_sct0_addr.rs new file mode 100644 index 0000000000..de8c945122 --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_prelock_sct0_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE3_PRELOCK_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_PRELOCK_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG"] +pub type L1_ICACHE3_PRELOCK_SCT0_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG"] + #[inline(always)] + pub fn l1_icache3_prelock_sct0_addr(&self) -> L1_ICACHE3_PRELOCK_SCT0_ADDR_R { + L1_ICACHE3_PRELOCK_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_PRELOCK_SCT0_ADDR") + .field( + "l1_icache3_prelock_sct0_addr", + &format_args!("{}", self.l1_icache3_prelock_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct0_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_prelock_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_PRELOCK_SCT0_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache3_prelock_sct1_addr.rs b/esp32p4/src/cache/l1_icache3_prelock_sct1_addr.rs new file mode 100644 index 0000000000..b22a0dd9c2 --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_prelock_sct1_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L1_ICACHE3_PRELOCK_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_PRELOCK_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG"] +pub type L1_ICACHE3_PRELOCK_SCT1_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG"] + #[inline(always)] + pub fn l1_icache3_prelock_sct1_addr(&self) -> L1_ICACHE3_PRELOCK_SCT1_ADDR_R { + L1_ICACHE3_PRELOCK_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_PRELOCK_SCT1_ADDR") + .field( + "l1_icache3_prelock_sct1_addr", + &format_args!("{}", self.l1_icache3_prelock_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct1_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_prelock_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_PRELOCK_SCT1_ADDR to value 0"] +impl crate::Resettable for L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_icache3_prelock_sct_size.rs b/esp32p4/src/cache/l1_icache3_prelock_sct_size.rs new file mode 100644 index 0000000000..63b7e5f1da --- /dev/null +++ b/esp32p4/src/cache/l1_icache3_prelock_sct_size.rs @@ -0,0 +1,50 @@ +#[doc = "Register `L1_ICACHE3_PRELOCK_SCT_SIZE` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE3_PRELOCK_SCT0_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG"] +pub type L1_ICACHE3_PRELOCK_SCT0_SIZE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE3_PRELOCK_SCT1_SIZE` reader - Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG"] +pub type L1_ICACHE3_PRELOCK_SCT1_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG"] + #[inline(always)] + pub fn l1_icache3_prelock_sct0_size(&self) -> L1_ICACHE3_PRELOCK_SCT0_SIZE_R { + L1_ICACHE3_PRELOCK_SCT0_SIZE_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG"] + #[inline(always)] + pub fn l1_icache3_prelock_sct1_size(&self) -> L1_ICACHE3_PRELOCK_SCT1_SIZE_R { + L1_ICACHE3_PRELOCK_SCT1_SIZE_R::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE3_PRELOCK_SCT_SIZE") + .field( + "l1_icache3_prelock_sct0_size", + &format_args!("{}", self.l1_icache3_prelock_sct0_size().bits()), + ) + .field( + "l1_icache3_prelock_sct1_size", + &format_args!("{}", self.l1_icache3_prelock_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache 3 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct_size::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC; +impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache3_prelock_sct_size::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE3_PRELOCK_SCT_SIZE to value 0x3fff_3fff"] +impl crate::Resettable for L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0x3fff_3fff; +} diff --git a/esp32p4/src/cache/l1_icache_blocksize_conf.rs b/esp32p4/src/cache/l1_icache_blocksize_conf.rs new file mode 100644 index 0000000000..0deaeea066 --- /dev/null +++ b/esp32p4/src/cache/l1_icache_blocksize_conf.rs @@ -0,0 +1,94 @@ +#[doc = "Register `L1_ICACHE_BLOCKSIZE_CONF` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE_BLOCKSIZE_8` reader - The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_BLOCKSIZE_8_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_BLOCKSIZE_16` reader - The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_BLOCKSIZE_16_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_BLOCKSIZE_32` reader - The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_BLOCKSIZE_32_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_BLOCKSIZE_64` reader - The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_BLOCKSIZE_64_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_BLOCKSIZE_128` reader - The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_BLOCKSIZE_128_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_BLOCKSIZE_256` reader - The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_BLOCKSIZE_256_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_blocksize_8(&self) -> L1_ICACHE_BLOCKSIZE_8_R { + L1_ICACHE_BLOCKSIZE_8_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_blocksize_16(&self) -> L1_ICACHE_BLOCKSIZE_16_R { + L1_ICACHE_BLOCKSIZE_16_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_blocksize_32(&self) -> L1_ICACHE_BLOCKSIZE_32_R { + L1_ICACHE_BLOCKSIZE_32_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_blocksize_64(&self) -> L1_ICACHE_BLOCKSIZE_64_R { + L1_ICACHE_BLOCKSIZE_64_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_blocksize_128(&self) -> L1_ICACHE_BLOCKSIZE_128_R { + L1_ICACHE_BLOCKSIZE_128_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_blocksize_256(&self) -> L1_ICACHE_BLOCKSIZE_256_R { + L1_ICACHE_BLOCKSIZE_256_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE_BLOCKSIZE_CONF") + .field( + "l1_icache_blocksize_8", + &format_args!("{}", self.l1_icache_blocksize_8().bit()), + ) + .field( + "l1_icache_blocksize_16", + &format_args!("{}", self.l1_icache_blocksize_16().bit()), + ) + .field( + "l1_icache_blocksize_32", + &format_args!("{}", self.l1_icache_blocksize_32().bit()), + ) + .field( + "l1_icache_blocksize_64", + &format_args!("{}", self.l1_icache_blocksize_64().bit()), + ) + .field( + "l1_icache_blocksize_128", + &format_args!("{}", self.l1_icache_blocksize_128().bit()), + ) + .field( + "l1_icache_blocksize_256", + &format_args!("{}", self.l1_icache_blocksize_256().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_blocksize_conf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE_BLOCKSIZE_CONF_SPEC; +impl crate::RegisterSpec for L1_ICACHE_BLOCKSIZE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache_blocksize_conf::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE_BLOCKSIZE_CONF_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE_BLOCKSIZE_CONF to value 0x08"] +impl crate::Resettable for L1_ICACHE_BLOCKSIZE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/cache/l1_icache_cachesize_conf.rs b/esp32p4/src/cache/l1_icache_cachesize_conf.rs new file mode 100644 index 0000000000..3051448f92 --- /dev/null +++ b/esp32p4/src/cache/l1_icache_cachesize_conf.rs @@ -0,0 +1,171 @@ +#[doc = "Register `L1_ICACHE_CACHESIZE_CONF` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE_CACHESIZE_256` reader - The field is used to configure cachesize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_256_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_512` reader - The field is used to configure cachesize of L1-ICache as 512 bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_512_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_1K` reader - The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_1K_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_2K` reader - The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_2K_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_4K` reader - The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_4K_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_8K` reader - The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_8K_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_16K` reader - The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_16K_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_32K` reader - The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_32K_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_64K` reader - The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_64K_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_128K` reader - The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_128K_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_256K` reader - The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_256K_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_512K` reader - The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_512K_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_CACHESIZE_1024K` reader - The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot."] +pub type L1_ICACHE_CACHESIZE_1024K_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The field is used to configure cachesize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_256(&self) -> L1_ICACHE_CACHESIZE_256_R { + L1_ICACHE_CACHESIZE_256_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The field is used to configure cachesize of L1-ICache as 512 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_512(&self) -> L1_ICACHE_CACHESIZE_512_R { + L1_ICACHE_CACHESIZE_512_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_1k(&self) -> L1_ICACHE_CACHESIZE_1K_R { + L1_ICACHE_CACHESIZE_1K_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_2k(&self) -> L1_ICACHE_CACHESIZE_2K_R { + L1_ICACHE_CACHESIZE_2K_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_4k(&self) -> L1_ICACHE_CACHESIZE_4K_R { + L1_ICACHE_CACHESIZE_4K_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_8k(&self) -> L1_ICACHE_CACHESIZE_8K_R { + L1_ICACHE_CACHESIZE_8K_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_16k(&self) -> L1_ICACHE_CACHESIZE_16K_R { + L1_ICACHE_CACHESIZE_16K_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_32k(&self) -> L1_ICACHE_CACHESIZE_32K_R { + L1_ICACHE_CACHESIZE_32K_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_64k(&self) -> L1_ICACHE_CACHESIZE_64K_R { + L1_ICACHE_CACHESIZE_64K_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_128k(&self) -> L1_ICACHE_CACHESIZE_128K_R { + L1_ICACHE_CACHESIZE_128K_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_256k(&self) -> L1_ICACHE_CACHESIZE_256K_R { + L1_ICACHE_CACHESIZE_256K_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_512k(&self) -> L1_ICACHE_CACHESIZE_512K_R { + L1_ICACHE_CACHESIZE_512K_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l1_icache_cachesize_1024k(&self) -> L1_ICACHE_CACHESIZE_1024K_R { + L1_ICACHE_CACHESIZE_1024K_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE_CACHESIZE_CONF") + .field( + "l1_icache_cachesize_256", + &format_args!("{}", self.l1_icache_cachesize_256().bit()), + ) + .field( + "l1_icache_cachesize_512", + &format_args!("{}", self.l1_icache_cachesize_512().bit()), + ) + .field( + "l1_icache_cachesize_1k", + &format_args!("{}", self.l1_icache_cachesize_1k().bit()), + ) + .field( + "l1_icache_cachesize_2k", + &format_args!("{}", self.l1_icache_cachesize_2k().bit()), + ) + .field( + "l1_icache_cachesize_4k", + &format_args!("{}", self.l1_icache_cachesize_4k().bit()), + ) + .field( + "l1_icache_cachesize_8k", + &format_args!("{}", self.l1_icache_cachesize_8k().bit()), + ) + .field( + "l1_icache_cachesize_16k", + &format_args!("{}", self.l1_icache_cachesize_16k().bit()), + ) + .field( + "l1_icache_cachesize_32k", + &format_args!("{}", self.l1_icache_cachesize_32k().bit()), + ) + .field( + "l1_icache_cachesize_64k", + &format_args!("{}", self.l1_icache_cachesize_64k().bit()), + ) + .field( + "l1_icache_cachesize_128k", + &format_args!("{}", self.l1_icache_cachesize_128k().bit()), + ) + .field( + "l1_icache_cachesize_256k", + &format_args!("{}", self.l1_icache_cachesize_256k().bit()), + ) + .field( + "l1_icache_cachesize_512k", + &format_args!("{}", self.l1_icache_cachesize_512k().bit()), + ) + .field( + "l1_icache_cachesize_1024k", + &format_args!("{}", self.l1_icache_cachesize_1024k().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1 instruction Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_cachesize_conf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE_CACHESIZE_CONF_SPEC; +impl crate::RegisterSpec for L1_ICACHE_CACHESIZE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache_cachesize_conf::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE_CACHESIZE_CONF_SPEC {} +#[doc = "`reset()` method sets L1_ICACHE_CACHESIZE_CONF to value 0x40"] +impl crate::Resettable for L1_ICACHE_CACHESIZE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x40; +} diff --git a/esp32p4/src/cache/l1_icache_ctrl.rs b/esp32p4/src/cache/l1_icache_ctrl.rs new file mode 100644 index 0000000000..cf4a8fc3df --- /dev/null +++ b/esp32p4/src/cache/l1_icache_ctrl.rs @@ -0,0 +1,126 @@ +#[doc = "Register `L1_ICACHE_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L1_ICACHE_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE_SHUT_IBUS0` reader - The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable"] +pub type L1_ICACHE_SHUT_IBUS0_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_SHUT_IBUS0` writer - The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable"] +pub type L1_ICACHE_SHUT_IBUS0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE_SHUT_IBUS1` reader - The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable"] +pub type L1_ICACHE_SHUT_IBUS1_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_SHUT_IBUS1` writer - The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable"] +pub type L1_ICACHE_SHUT_IBUS1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE_SHUT_IBUS2` reader - Reserved"] +pub type L1_ICACHE_SHUT_IBUS2_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_SHUT_IBUS3` reader - Reserved"] +pub type L1_ICACHE_SHUT_IBUS3_R = crate::BitReader; +#[doc = "Field `L1_ICACHE_UNDEF_OP` reader - Reserved"] +pub type L1_ICACHE_UNDEF_OP_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE_UNDEF_OP` writer - Reserved"] +pub type L1_ICACHE_UNDEF_OP_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable"] + #[inline(always)] + pub fn l1_icache_shut_ibus0(&self) -> L1_ICACHE_SHUT_IBUS0_R { + L1_ICACHE_SHUT_IBUS0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable"] + #[inline(always)] + pub fn l1_icache_shut_ibus1(&self) -> L1_ICACHE_SHUT_IBUS1_R { + L1_ICACHE_SHUT_IBUS1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache_shut_ibus2(&self) -> L1_ICACHE_SHUT_IBUS2_R { + L1_ICACHE_SHUT_IBUS2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache_shut_ibus3(&self) -> L1_ICACHE_SHUT_IBUS3_R { + L1_ICACHE_SHUT_IBUS3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn l1_icache_undef_op(&self) -> L1_ICACHE_UNDEF_OP_R { + L1_ICACHE_UNDEF_OP_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_ICACHE_CTRL") + .field( + "l1_icache_shut_ibus0", + &format_args!("{}", self.l1_icache_shut_ibus0().bit()), + ) + .field( + "l1_icache_shut_ibus1", + &format_args!("{}", self.l1_icache_shut_ibus1().bit()), + ) + .field( + "l1_icache_shut_ibus2", + &format_args!("{}", self.l1_icache_shut_ibus2().bit()), + ) + .field( + "l1_icache_shut_ibus3", + &format_args!("{}", self.l1_icache_shut_ibus3().bit()), + ) + .field( + "l1_icache_undef_op", + &format_args!("{}", self.l1_icache_undef_op().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable"] + #[inline(always)] + #[must_use] + pub fn l1_icache_shut_ibus0(&mut self) -> L1_ICACHE_SHUT_IBUS0_W { + L1_ICACHE_SHUT_IBUS0_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable"] + #[inline(always)] + #[must_use] + pub fn l1_icache_shut_ibus1(&mut self) -> L1_ICACHE_SHUT_IBUS1_W { + L1_ICACHE_SHUT_IBUS1_W::new(self, 1) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn l1_icache_undef_op(&mut self) -> L1_ICACHE_UNDEF_OP_W { + L1_ICACHE_UNDEF_OP_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1 instruction Cache(L1-ICache) control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_icache_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_ICACHE_CTRL_SPEC; +impl crate::RegisterSpec for L1_ICACHE_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_icache_ctrl::R`](R) reader structure"] +impl crate::Readable for L1_ICACHE_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_icache_ctrl::W`](W) writer structure"] +impl crate::Writable for L1_ICACHE_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_ICACHE_CTRL to value 0"] +impl crate::Resettable for L1_ICACHE_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l1_unallocate_buffer_clear.rs b/esp32p4/src/cache/l1_unallocate_buffer_clear.rs new file mode 100644 index 0000000000..76213aef97 --- /dev/null +++ b/esp32p4/src/cache/l1_unallocate_buffer_clear.rs @@ -0,0 +1,132 @@ +#[doc = "Register `L1_UNALLOCATE_BUFFER_CLEAR` reader"] +pub type R = crate::R; +#[doc = "Register `L1_UNALLOCATE_BUFFER_CLEAR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_UNALLOC_CLR` reader - The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed."] +pub type L1_ICACHE0_UNALLOC_CLR_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_UNALLOC_CLR` writer - The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed."] +pub type L1_ICACHE0_UNALLOC_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_UNALLOC_CLR` reader - The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed."] +pub type L1_ICACHE1_UNALLOC_CLR_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_UNALLOC_CLR` writer - The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed."] +pub type L1_ICACHE1_UNALLOC_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_UNALLOC_CLR` reader - Reserved"] +pub type L1_ICACHE2_UNALLOC_CLR_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_UNALLOC_CLR` reader - Reserved"] +pub type L1_ICACHE3_UNALLOC_CLR_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_UNALLOC_CLR` reader - The bit is used to clear the unallocate request buffer of l1 dcache where the unallocate request is responsed but not completed."] +pub type L1_DCACHE_UNALLOC_CLR_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_UNALLOC_CLR` writer - The bit is used to clear the unallocate request buffer of l1 dcache where the unallocate request is responsed but not completed."] +pub type L1_DCACHE_UNALLOC_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed."] + #[inline(always)] + pub fn l1_icache0_unalloc_clr(&self) -> L1_ICACHE0_UNALLOC_CLR_R { + L1_ICACHE0_UNALLOC_CLR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed."] + #[inline(always)] + pub fn l1_icache1_unalloc_clr(&self) -> L1_ICACHE1_UNALLOC_CLR_R { + L1_ICACHE1_UNALLOC_CLR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_unalloc_clr(&self) -> L1_ICACHE2_UNALLOC_CLR_R { + L1_ICACHE2_UNALLOC_CLR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_unalloc_clr(&self) -> L1_ICACHE3_UNALLOC_CLR_R { + L1_ICACHE3_UNALLOC_CLR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to clear the unallocate request buffer of l1 dcache where the unallocate request is responsed but not completed."] + #[inline(always)] + pub fn l1_dcache_unalloc_clr(&self) -> L1_DCACHE_UNALLOC_CLR_R { + L1_DCACHE_UNALLOC_CLR_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L1_UNALLOCATE_BUFFER_CLEAR") + .field( + "l1_icache0_unalloc_clr", + &format_args!("{}", self.l1_icache0_unalloc_clr().bit()), + ) + .field( + "l1_icache1_unalloc_clr", + &format_args!("{}", self.l1_icache1_unalloc_clr().bit()), + ) + .field( + "l1_icache2_unalloc_clr", + &format_args!("{}", self.l1_icache2_unalloc_clr().bit()), + ) + .field( + "l1_icache3_unalloc_clr", + &format_args!("{}", self.l1_icache3_unalloc_clr().bit()), + ) + .field( + "l1_dcache_unalloc_clr", + &format_args!("{}", self.l1_dcache_unalloc_clr().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_unalloc_clr( + &mut self, + ) -> L1_ICACHE0_UNALLOC_CLR_W { + L1_ICACHE0_UNALLOC_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_unalloc_clr( + &mut self, + ) -> L1_ICACHE1_UNALLOC_CLR_W { + L1_ICACHE1_UNALLOC_CLR_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to clear the unallocate request buffer of l1 dcache where the unallocate request is responsed but not completed."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_unalloc_clr( + &mut self, + ) -> L1_DCACHE_UNALLOC_CLR_W { + L1_DCACHE_UNALLOC_CLR_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Unallocate request buffer clear registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_unallocate_buffer_clear::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l1_unallocate_buffer_clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L1_UNALLOCATE_BUFFER_CLEAR_SPEC; +impl crate::RegisterSpec for L1_UNALLOCATE_BUFFER_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l1_unallocate_buffer_clear::R`](R) reader structure"] +impl crate::Readable for L1_UNALLOCATE_BUFFER_CLEAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l1_unallocate_buffer_clear::W`](W) writer structure"] +impl crate::Writable for L1_UNALLOCATE_BUFFER_CLEAR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L1_UNALLOCATE_BUFFER_CLEAR to value 0"] +impl crate::Resettable for L1_UNALLOCATE_BUFFER_CLEAR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_bypass_cache_conf.rs b/esp32p4/src/cache/l2_bypass_cache_conf.rs new file mode 100644 index 0000000000..17092f0847 --- /dev/null +++ b/esp32p4/src/cache/l2_bypass_cache_conf.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L2_BYPASS_CACHE_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L2_BYPASS_CACHE_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `BYPASS_L2_CACHE_EN` reader - The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass."] +pub type BYPASS_L2_CACHE_EN_R = crate::BitReader; +#[doc = "Field `BYPASS_L2_CACHE_EN` writer - The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass."] +pub type BYPASS_L2_CACHE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass."] + #[inline(always)] + pub fn bypass_l2_cache_en(&self) -> BYPASS_L2_CACHE_EN_R { + BYPASS_L2_CACHE_EN_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_BYPASS_CACHE_CONF") + .field( + "bypass_l2_cache_en", + &format_args!("{}", self.bypass_l2_cache_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass."] + #[inline(always)] + #[must_use] + pub fn bypass_l2_cache_en(&mut self) -> BYPASS_L2_CACHE_EN_W { + BYPASS_L2_CACHE_EN_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Bypass Cache configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_bypass_cache_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_bypass_cache_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_BYPASS_CACHE_CONF_SPEC; +impl crate::RegisterSpec for L2_BYPASS_CACHE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_bypass_cache_conf::R`](R) reader structure"] +impl crate::Readable for L2_BYPASS_CACHE_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_bypass_cache_conf::W`](W) writer structure"] +impl crate::Writable for L2_BYPASS_CACHE_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_BYPASS_CACHE_CONF to value 0"] +impl crate::Resettable for L2_BYPASS_CACHE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_access_attr_ctrl.rs b/esp32p4/src/cache/l2_cache_access_attr_ctrl.rs new file mode 100644 index 0000000000..2867a334a1 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_access_attr_ctrl.rs @@ -0,0 +1,131 @@ +#[doc = "Register `L2_CACHE_ACCESS_ATTR_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_ACCESS_ATTR_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_ACCESS_FORCE_CC` reader - Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable."] +pub type L2_CACHE_ACCESS_FORCE_CC_R = crate::BitReader; +#[doc = "Field `L2_CACHE_ACCESS_FORCE_CC` writer - Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable."] +pub type L2_CACHE_ACCESS_FORCE_CC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_ACCESS_FORCE_WB` reader - Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through."] +pub type L2_CACHE_ACCESS_FORCE_WB_R = crate::BitReader; +#[doc = "Field `L2_CACHE_ACCESS_FORCE_WB` writer - Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through."] +pub type L2_CACHE_ACCESS_FORCE_WB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_ACCESS_FORCE_WMA` reader - Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate."] +pub type L2_CACHE_ACCESS_FORCE_WMA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_ACCESS_FORCE_WMA` writer - Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate."] +pub type L2_CACHE_ACCESS_FORCE_WMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_ACCESS_FORCE_RMA` reader - Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate."] +pub type L2_CACHE_ACCESS_FORCE_RMA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_ACCESS_FORCE_RMA` writer - Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate."] +pub type L2_CACHE_ACCESS_FORCE_RMA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable."] + #[inline(always)] + pub fn l2_cache_access_force_cc(&self) -> L2_CACHE_ACCESS_FORCE_CC_R { + L2_CACHE_ACCESS_FORCE_CC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through."] + #[inline(always)] + pub fn l2_cache_access_force_wb(&self) -> L2_CACHE_ACCESS_FORCE_WB_R { + L2_CACHE_ACCESS_FORCE_WB_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate."] + #[inline(always)] + pub fn l2_cache_access_force_wma(&self) -> L2_CACHE_ACCESS_FORCE_WMA_R { + L2_CACHE_ACCESS_FORCE_WMA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate."] + #[inline(always)] + pub fn l2_cache_access_force_rma(&self) -> L2_CACHE_ACCESS_FORCE_RMA_R { + L2_CACHE_ACCESS_FORCE_RMA_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACCESS_ATTR_CTRL") + .field( + "l2_cache_access_force_cc", + &format_args!("{}", self.l2_cache_access_force_cc().bit()), + ) + .field( + "l2_cache_access_force_wb", + &format_args!("{}", self.l2_cache_access_force_wb().bit()), + ) + .field( + "l2_cache_access_force_wma", + &format_args!("{}", self.l2_cache_access_force_wma().bit()), + ) + .field( + "l2_cache_access_force_rma", + &format_args!("{}", self.l2_cache_access_force_rma().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable."] + #[inline(always)] + #[must_use] + pub fn l2_cache_access_force_cc( + &mut self, + ) -> L2_CACHE_ACCESS_FORCE_CC_W { + L2_CACHE_ACCESS_FORCE_CC_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through."] + #[inline(always)] + #[must_use] + pub fn l2_cache_access_force_wb( + &mut self, + ) -> L2_CACHE_ACCESS_FORCE_WB_W { + L2_CACHE_ACCESS_FORCE_WB_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate."] + #[inline(always)] + #[must_use] + pub fn l2_cache_access_force_wma( + &mut self, + ) -> L2_CACHE_ACCESS_FORCE_WMA_W { + L2_CACHE_ACCESS_FORCE_WMA_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate."] + #[inline(always)] + #[must_use] + pub fn l2_cache_access_force_rma( + &mut self, + ) -> L2_CACHE_ACCESS_FORCE_RMA_W { + L2_CACHE_ACCESS_FORCE_RMA_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 cache access attribute control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_access_attr_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_access_attr_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACCESS_ATTR_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACCESS_ATTR_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_access_attr_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACCESS_ATTR_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_access_attr_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_ACCESS_ATTR_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_ACCESS_ATTR_CTRL to value 0x0f"] +impl crate::Resettable for L2_CACHE_ACCESS_ATTR_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/cache/l2_cache_acs_cnt_ctrl.rs b/esp32p4/src/cache/l2_cache_acs_cnt_ctrl.rs new file mode 100644 index 0000000000..6435e33a99 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_cnt_ctrl.rs @@ -0,0 +1,243 @@ +#[doc = "Register `L2_CACHE_ACS_CNT_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_ACS_CNT_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_IBUS0_CNT_ENA` reader - The bit is used to enable ibus0 counter in L2-Cache."] +pub type L2_IBUS0_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L2_IBUS0_CNT_ENA` writer - The bit is used to enable ibus0 counter in L2-Cache."] +pub type L2_IBUS0_CNT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_IBUS1_CNT_ENA` reader - The bit is used to enable ibus1 counter in L2-Cache."] +pub type L2_IBUS1_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L2_IBUS1_CNT_ENA` writer - The bit is used to enable ibus1 counter in L2-Cache."] +pub type L2_IBUS1_CNT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_IBUS2_CNT_ENA` reader - Reserved"] +pub type L2_IBUS2_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L2_IBUS3_CNT_ENA` reader - Reserved"] +pub type L2_IBUS3_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L2_DBUS0_CNT_ENA` reader - The bit is used to enable dbus0 counter in L2-Cache."] +pub type L2_DBUS0_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L2_DBUS0_CNT_ENA` writer - The bit is used to enable dbus0 counter in L2-Cache."] +pub type L2_DBUS0_CNT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS1_CNT_ENA` reader - The bit is used to enable dbus1 counter in L2-Cache."] +pub type L2_DBUS1_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L2_DBUS1_CNT_ENA` writer - The bit is used to enable dbus1 counter in L2-Cache."] +pub type L2_DBUS1_CNT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS2_CNT_ENA` reader - Reserved"] +pub type L2_DBUS2_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L2_DBUS3_CNT_ENA` reader - Reserved"] +pub type L2_DBUS3_CNT_ENA_R = crate::BitReader; +#[doc = "Field `L2_IBUS0_CNT_CLR` writer - The bit is used to clear ibus0 counter in L2-Cache."] +pub type L2_IBUS0_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_IBUS1_CNT_CLR` writer - The bit is used to clear ibus1 counter in L2-Cache."] +pub type L2_IBUS1_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_IBUS2_CNT_CLR` reader - Reserved"] +pub type L2_IBUS2_CNT_CLR_R = crate::BitReader; +#[doc = "Field `L2_IBUS3_CNT_CLR` reader - Reserved"] +pub type L2_IBUS3_CNT_CLR_R = crate::BitReader; +#[doc = "Field `L2_DBUS0_CNT_CLR` writer - The bit is used to clear dbus0 counter in L2-Cache."] +pub type L2_DBUS0_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS1_CNT_CLR` writer - The bit is used to clear dbus1 counter in L2-Cache."] +pub type L2_DBUS1_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS2_CNT_CLR` reader - Reserved"] +pub type L2_DBUS2_CNT_CLR_R = crate::BitReader; +#[doc = "Field `L2_DBUS3_CNT_CLR` reader - Reserved"] +pub type L2_DBUS3_CNT_CLR_R = crate::BitReader; +impl R { + #[doc = "Bit 8 - The bit is used to enable ibus0 counter in L2-Cache."] + #[inline(always)] + pub fn l2_ibus0_cnt_ena(&self) -> L2_IBUS0_CNT_ENA_R { + L2_IBUS0_CNT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The bit is used to enable ibus1 counter in L2-Cache."] + #[inline(always)] + pub fn l2_ibus1_cnt_ena(&self) -> L2_IBUS1_CNT_ENA_R { + L2_IBUS1_CNT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn l2_ibus2_cnt_ena(&self) -> L2_IBUS2_CNT_ENA_R { + L2_IBUS2_CNT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn l2_ibus3_cnt_ena(&self) -> L2_IBUS3_CNT_ENA_R { + L2_IBUS3_CNT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The bit is used to enable dbus0 counter in L2-Cache."] + #[inline(always)] + pub fn l2_dbus0_cnt_ena(&self) -> L2_DBUS0_CNT_ENA_R { + L2_DBUS0_CNT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The bit is used to enable dbus1 counter in L2-Cache."] + #[inline(always)] + pub fn l2_dbus1_cnt_ena(&self) -> L2_DBUS1_CNT_ENA_R { + L2_DBUS1_CNT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn l2_dbus2_cnt_ena(&self) -> L2_DBUS2_CNT_ENA_R { + L2_DBUS2_CNT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn l2_dbus3_cnt_ena(&self) -> L2_DBUS3_CNT_ENA_R { + L2_DBUS3_CNT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn l2_ibus2_cnt_clr(&self) -> L2_IBUS2_CNT_CLR_R { + L2_IBUS2_CNT_CLR_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn l2_ibus3_cnt_clr(&self) -> L2_IBUS3_CNT_CLR_R { + L2_IBUS3_CNT_CLR_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + pub fn l2_dbus2_cnt_clr(&self) -> L2_DBUS2_CNT_CLR_R { + L2_DBUS2_CNT_CLR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn l2_dbus3_cnt_clr(&self) -> L2_DBUS3_CNT_CLR_R { + L2_DBUS3_CNT_CLR_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACS_CNT_CTRL") + .field( + "l2_ibus0_cnt_ena", + &format_args!("{}", self.l2_ibus0_cnt_ena().bit()), + ) + .field( + "l2_ibus1_cnt_ena", + &format_args!("{}", self.l2_ibus1_cnt_ena().bit()), + ) + .field( + "l2_ibus2_cnt_ena", + &format_args!("{}", self.l2_ibus2_cnt_ena().bit()), + ) + .field( + "l2_ibus3_cnt_ena", + &format_args!("{}", self.l2_ibus3_cnt_ena().bit()), + ) + .field( + "l2_dbus0_cnt_ena", + &format_args!("{}", self.l2_dbus0_cnt_ena().bit()), + ) + .field( + "l2_dbus1_cnt_ena", + &format_args!("{}", self.l2_dbus1_cnt_ena().bit()), + ) + .field( + "l2_dbus2_cnt_ena", + &format_args!("{}", self.l2_dbus2_cnt_ena().bit()), + ) + .field( + "l2_dbus3_cnt_ena", + &format_args!("{}", self.l2_dbus3_cnt_ena().bit()), + ) + .field( + "l2_ibus2_cnt_clr", + &format_args!("{}", self.l2_ibus2_cnt_clr().bit()), + ) + .field( + "l2_ibus3_cnt_clr", + &format_args!("{}", self.l2_ibus3_cnt_clr().bit()), + ) + .field( + "l2_dbus2_cnt_clr", + &format_args!("{}", self.l2_dbus2_cnt_clr().bit()), + ) + .field( + "l2_dbus3_cnt_clr", + &format_args!("{}", self.l2_dbus3_cnt_clr().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 8 - The bit is used to enable ibus0 counter in L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_ibus0_cnt_ena(&mut self) -> L2_IBUS0_CNT_ENA_W { + L2_IBUS0_CNT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The bit is used to enable ibus1 counter in L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_ibus1_cnt_ena(&mut self) -> L2_IBUS1_CNT_ENA_W { + L2_IBUS1_CNT_ENA_W::new(self, 9) + } + #[doc = "Bit 12 - The bit is used to enable dbus0 counter in L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus0_cnt_ena(&mut self) -> L2_DBUS0_CNT_ENA_W { + L2_DBUS0_CNT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - The bit is used to enable dbus1 counter in L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus1_cnt_ena(&mut self) -> L2_DBUS1_CNT_ENA_W { + L2_DBUS1_CNT_ENA_W::new(self, 13) + } + #[doc = "Bit 24 - The bit is used to clear ibus0 counter in L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_ibus0_cnt_clr(&mut self) -> L2_IBUS0_CNT_CLR_W { + L2_IBUS0_CNT_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - The bit is used to clear ibus1 counter in L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_ibus1_cnt_clr(&mut self) -> L2_IBUS1_CNT_CLR_W { + L2_IBUS1_CNT_CLR_W::new(self, 25) + } + #[doc = "Bit 28 - The bit is used to clear dbus0 counter in L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus0_cnt_clr(&mut self) -> L2_DBUS0_CNT_CLR_W { + L2_DBUS0_CNT_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - The bit is used to clear dbus1 counter in L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus1_cnt_clr(&mut self) -> L2_DBUS1_CNT_CLR_W { + L2_DBUS1_CNT_CLR_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Counter enable and clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_CNT_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_CNT_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_acs_cnt_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACS_CNT_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_acs_cnt_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_ACS_CNT_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_ACS_CNT_CTRL to value 0"] +impl crate::Resettable for L2_CACHE_ACS_CNT_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_acs_cnt_int_clr.rs b/esp32p4/src/cache/l2_cache_acs_cnt_int_clr.rs new file mode 100644 index 0000000000..58446ec431 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_cnt_int_clr.rs @@ -0,0 +1,131 @@ +#[doc = "Register `L2_CACHE_ACS_CNT_INT_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_ACS_CNT_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_IBUS0_OVF_INT_CLR` writer - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache."] +pub type L2_IBUS0_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_IBUS1_OVF_INT_CLR` writer - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache."] +pub type L2_IBUS1_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_IBUS2_OVF_INT_CLR` reader - Reserved"] +pub type L2_IBUS2_OVF_INT_CLR_R = crate::BitReader; +#[doc = "Field `L2_IBUS3_OVF_INT_CLR` reader - Reserved"] +pub type L2_IBUS3_OVF_INT_CLR_R = crate::BitReader; +#[doc = "Field `L2_DBUS0_OVF_INT_CLR` writer - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache."] +pub type L2_DBUS0_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS1_OVF_INT_CLR` writer - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache."] +pub type L2_DBUS1_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS2_OVF_INT_CLR` reader - Reserved"] +pub type L2_DBUS2_OVF_INT_CLR_R = crate::BitReader; +#[doc = "Field `L2_DBUS3_OVF_INT_CLR` reader - Reserved"] +pub type L2_DBUS3_OVF_INT_CLR_R = crate::BitReader; +impl R { + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn l2_ibus2_ovf_int_clr(&self) -> L2_IBUS2_OVF_INT_CLR_R { + L2_IBUS2_OVF_INT_CLR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn l2_ibus3_ovf_int_clr(&self) -> L2_IBUS3_OVF_INT_CLR_R { + L2_IBUS3_OVF_INT_CLR_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn l2_dbus2_ovf_int_clr(&self) -> L2_DBUS2_OVF_INT_CLR_R { + L2_DBUS2_OVF_INT_CLR_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn l2_dbus3_ovf_int_clr(&self) -> L2_DBUS3_OVF_INT_CLR_R { + L2_DBUS3_OVF_INT_CLR_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACS_CNT_INT_CLR") + .field( + "l2_ibus2_ovf_int_clr", + &format_args!("{}", self.l2_ibus2_ovf_int_clr().bit()), + ) + .field( + "l2_ibus3_ovf_int_clr", + &format_args!("{}", self.l2_ibus3_ovf_int_clr().bit()), + ) + .field( + "l2_dbus2_ovf_int_clr", + &format_args!("{}", self.l2_dbus2_ovf_int_clr().bit()), + ) + .field( + "l2_dbus3_ovf_int_clr", + &format_args!("{}", self.l2_dbus3_ovf_int_clr().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 8 - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_ibus0_ovf_int_clr( + &mut self, + ) -> L2_IBUS0_OVF_INT_CLR_W { + L2_IBUS0_OVF_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_ibus1_ovf_int_clr( + &mut self, + ) -> L2_IBUS1_OVF_INT_CLR_W { + L2_IBUS1_OVF_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 12 - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus0_ovf_int_clr( + &mut self, + ) -> L2_DBUS0_OVF_INT_CLR_W { + L2_DBUS0_OVF_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus1_ovf_int_clr( + &mut self, + ) -> L2_DBUS1_OVF_INT_CLR_W { + L2_DBUS1_OVF_INT_CLR_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Counter Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_int_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_CNT_INT_CLR_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_CNT_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_acs_cnt_int_clr::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACS_CNT_INT_CLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_acs_cnt_int_clr::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_ACS_CNT_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_ACS_CNT_INT_CLR to value 0"] +impl crate::Resettable for L2_CACHE_ACS_CNT_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_acs_cnt_int_ena.rs b/esp32p4/src/cache/l2_cache_acs_cnt_int_ena.rs new file mode 100644 index 0000000000..20004aaee9 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_cnt_int_ena.rs @@ -0,0 +1,175 @@ +#[doc = "Register `L2_CACHE_ACS_CNT_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_ACS_CNT_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `L2_IBUS0_OVF_INT_ENA` reader - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] +pub type L2_IBUS0_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L2_IBUS0_OVF_INT_ENA` writer - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] +pub type L2_IBUS0_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_IBUS1_OVF_INT_ENA` reader - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] +pub type L2_IBUS1_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L2_IBUS1_OVF_INT_ENA` writer - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] +pub type L2_IBUS1_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_IBUS2_OVF_INT_ENA` reader - Reserved"] +pub type L2_IBUS2_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L2_IBUS3_OVF_INT_ENA` reader - Reserved"] +pub type L2_IBUS3_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L2_DBUS0_OVF_INT_ENA` reader - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] +pub type L2_DBUS0_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L2_DBUS0_OVF_INT_ENA` writer - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] +pub type L2_DBUS0_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS1_OVF_INT_ENA` reader - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] +pub type L2_DBUS1_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L2_DBUS1_OVF_INT_ENA` writer - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] +pub type L2_DBUS1_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS2_OVF_INT_ENA` reader - Reserved"] +pub type L2_DBUS2_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `L2_DBUS3_OVF_INT_ENA` reader - Reserved"] +pub type L2_DBUS3_OVF_INT_ENA_R = crate::BitReader; +impl R { + #[doc = "Bit 8 - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] + #[inline(always)] + pub fn l2_ibus0_ovf_int_ena(&self) -> L2_IBUS0_OVF_INT_ENA_R { + L2_IBUS0_OVF_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] + #[inline(always)] + pub fn l2_ibus1_ovf_int_ena(&self) -> L2_IBUS1_OVF_INT_ENA_R { + L2_IBUS1_OVF_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn l2_ibus2_ovf_int_ena(&self) -> L2_IBUS2_OVF_INT_ENA_R { + L2_IBUS2_OVF_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn l2_ibus3_ovf_int_ena(&self) -> L2_IBUS3_OVF_INT_ENA_R { + L2_IBUS3_OVF_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] + #[inline(always)] + pub fn l2_dbus0_ovf_int_ena(&self) -> L2_DBUS0_OVF_INT_ENA_R { + L2_DBUS0_OVF_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] + #[inline(always)] + pub fn l2_dbus1_ovf_int_ena(&self) -> L2_DBUS1_OVF_INT_ENA_R { + L2_DBUS1_OVF_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn l2_dbus2_ovf_int_ena(&self) -> L2_DBUS2_OVF_INT_ENA_R { + L2_DBUS2_OVF_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn l2_dbus3_ovf_int_ena(&self) -> L2_DBUS3_OVF_INT_ENA_R { + L2_DBUS3_OVF_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACS_CNT_INT_ENA") + .field( + "l2_ibus0_ovf_int_ena", + &format_args!("{}", self.l2_ibus0_ovf_int_ena().bit()), + ) + .field( + "l2_ibus1_ovf_int_ena", + &format_args!("{}", self.l2_ibus1_ovf_int_ena().bit()), + ) + .field( + "l2_ibus2_ovf_int_ena", + &format_args!("{}", self.l2_ibus2_ovf_int_ena().bit()), + ) + .field( + "l2_ibus3_ovf_int_ena", + &format_args!("{}", self.l2_ibus3_ovf_int_ena().bit()), + ) + .field( + "l2_dbus0_ovf_int_ena", + &format_args!("{}", self.l2_dbus0_ovf_int_ena().bit()), + ) + .field( + "l2_dbus1_ovf_int_ena", + &format_args!("{}", self.l2_dbus1_ovf_int_ena().bit()), + ) + .field( + "l2_dbus2_ovf_int_ena", + &format_args!("{}", self.l2_dbus2_ovf_int_ena().bit()), + ) + .field( + "l2_dbus3_ovf_int_ena", + &format_args!("{}", self.l2_dbus3_ovf_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 8 - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_ibus0_ovf_int_ena( + &mut self, + ) -> L2_IBUS0_OVF_INT_ENA_W { + L2_IBUS0_OVF_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_ibus1_ovf_int_ena( + &mut self, + ) -> L2_IBUS1_OVF_INT_ENA_W { + L2_IBUS1_OVF_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 12 - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus0_ovf_int_ena( + &mut self, + ) -> L2_DBUS0_OVF_INT_ENA_W { + L2_DBUS0_OVF_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus1_ovf_int_ena( + &mut self, + ) -> L2_DBUS1_OVF_INT_ENA_W { + L2_DBUS1_OVF_INT_ENA_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Counter Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_CNT_INT_ENA_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_CNT_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_acs_cnt_int_ena::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACS_CNT_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_acs_cnt_int_ena::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_ACS_CNT_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_ACS_CNT_INT_ENA to value 0"] +impl crate::Resettable for L2_CACHE_ACS_CNT_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_acs_cnt_int_raw.rs b/esp32p4/src/cache/l2_cache_acs_cnt_int_raw.rs new file mode 100644 index 0000000000..23a5e8bf7a --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_cnt_int_raw.rs @@ -0,0 +1,215 @@ +#[doc = "Register `L2_CACHE_ACS_CNT_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_ACS_CNT_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `L2_IBUS0_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0."] +pub type L2_IBUS0_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L2_IBUS0_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0."] +pub type L2_IBUS0_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_IBUS1_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1."] +pub type L2_IBUS1_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L2_IBUS1_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1."] +pub type L2_IBUS1_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_IBUS2_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2."] +pub type L2_IBUS2_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L2_IBUS2_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2."] +pub type L2_IBUS2_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_IBUS3_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3."] +pub type L2_IBUS3_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L2_IBUS3_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3."] +pub type L2_IBUS3_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS0_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache."] +pub type L2_DBUS0_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L2_DBUS0_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache."] +pub type L2_DBUS0_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS1_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache."] +pub type L2_DBUS1_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L2_DBUS1_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache."] +pub type L2_DBUS1_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS2_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache."] +pub type L2_DBUS2_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L2_DBUS2_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache."] +pub type L2_DBUS2_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_DBUS3_OVF_INT_RAW` reader - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache."] +pub type L2_DBUS3_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `L2_DBUS3_OVF_INT_RAW` writer - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache."] +pub type L2_DBUS3_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 8 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0."] + #[inline(always)] + pub fn l2_ibus0_ovf_int_raw(&self) -> L2_IBUS0_OVF_INT_RAW_R { + L2_IBUS0_OVF_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1."] + #[inline(always)] + pub fn l2_ibus1_ovf_int_raw(&self) -> L2_IBUS1_OVF_INT_RAW_R { + L2_IBUS1_OVF_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2."] + #[inline(always)] + pub fn l2_ibus2_ovf_int_raw(&self) -> L2_IBUS2_OVF_INT_RAW_R { + L2_IBUS2_OVF_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3."] + #[inline(always)] + pub fn l2_ibus3_ovf_int_raw(&self) -> L2_IBUS3_OVF_INT_RAW_R { + L2_IBUS3_OVF_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache."] + #[inline(always)] + pub fn l2_dbus0_ovf_int_raw(&self) -> L2_DBUS0_OVF_INT_RAW_R { + L2_DBUS0_OVF_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache."] + #[inline(always)] + pub fn l2_dbus1_ovf_int_raw(&self) -> L2_DBUS1_OVF_INT_RAW_R { + L2_DBUS1_OVF_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache."] + #[inline(always)] + pub fn l2_dbus2_ovf_int_raw(&self) -> L2_DBUS2_OVF_INT_RAW_R { + L2_DBUS2_OVF_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache."] + #[inline(always)] + pub fn l2_dbus3_ovf_int_raw(&self) -> L2_DBUS3_OVF_INT_RAW_R { + L2_DBUS3_OVF_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACS_CNT_INT_RAW") + .field( + "l2_ibus0_ovf_int_raw", + &format_args!("{}", self.l2_ibus0_ovf_int_raw().bit()), + ) + .field( + "l2_ibus1_ovf_int_raw", + &format_args!("{}", self.l2_ibus1_ovf_int_raw().bit()), + ) + .field( + "l2_ibus2_ovf_int_raw", + &format_args!("{}", self.l2_ibus2_ovf_int_raw().bit()), + ) + .field( + "l2_ibus3_ovf_int_raw", + &format_args!("{}", self.l2_ibus3_ovf_int_raw().bit()), + ) + .field( + "l2_dbus0_ovf_int_raw", + &format_args!("{}", self.l2_dbus0_ovf_int_raw().bit()), + ) + .field( + "l2_dbus1_ovf_int_raw", + &format_args!("{}", self.l2_dbus1_ovf_int_raw().bit()), + ) + .field( + "l2_dbus2_ovf_int_raw", + &format_args!("{}", self.l2_dbus2_ovf_int_raw().bit()), + ) + .field( + "l2_dbus3_ovf_int_raw", + &format_args!("{}", self.l2_dbus3_ovf_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 8 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0."] + #[inline(always)] + #[must_use] + pub fn l2_ibus0_ovf_int_raw( + &mut self, + ) -> L2_IBUS0_OVF_INT_RAW_W { + L2_IBUS0_OVF_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1."] + #[inline(always)] + #[must_use] + pub fn l2_ibus1_ovf_int_raw( + &mut self, + ) -> L2_IBUS1_OVF_INT_RAW_W { + L2_IBUS1_OVF_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2."] + #[inline(always)] + #[must_use] + pub fn l2_ibus2_ovf_int_raw( + &mut self, + ) -> L2_IBUS2_OVF_INT_RAW_W { + L2_IBUS2_OVF_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3."] + #[inline(always)] + #[must_use] + pub fn l2_ibus3_ovf_int_raw( + &mut self, + ) -> L2_IBUS3_OVF_INT_RAW_W { + L2_IBUS3_OVF_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 12 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus0_ovf_int_raw( + &mut self, + ) -> L2_DBUS0_OVF_INT_RAW_W { + L2_DBUS0_OVF_INT_RAW_W::new(self, 12) + } + #[doc = "Bit 13 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus1_ovf_int_raw( + &mut self, + ) -> L2_DBUS1_OVF_INT_RAW_W { + L2_DBUS1_OVF_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 14 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus2_ovf_int_raw( + &mut self, + ) -> L2_DBUS2_OVF_INT_RAW_W { + L2_DBUS2_OVF_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache."] + #[inline(always)] + #[must_use] + pub fn l2_dbus3_ovf_int_raw( + &mut self, + ) -> L2_DBUS3_OVF_INT_RAW_W { + L2_DBUS3_OVF_INT_RAW_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Counter Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_cnt_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_CNT_INT_RAW_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_CNT_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_acs_cnt_int_raw::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACS_CNT_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_acs_cnt_int_raw::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_ACS_CNT_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_ACS_CNT_INT_RAW to value 0"] +impl crate::Resettable for L2_CACHE_ACS_CNT_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_acs_cnt_int_st.rs b/esp32p4/src/cache/l2_cache_acs_cnt_int_st.rs new file mode 100644 index 0000000000..ed3167e95e --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_cnt_int_st.rs @@ -0,0 +1,116 @@ +#[doc = "Register `L2_CACHE_ACS_CNT_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS0_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] +pub type L2_IBUS0_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L2_IBUS1_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] +pub type L2_IBUS1_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L2_IBUS2_OVF_INT_ST` reader - Reserved"] +pub type L2_IBUS2_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L2_IBUS3_OVF_INT_ST` reader - Reserved"] +pub type L2_IBUS3_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L2_DBUS0_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] +pub type L2_DBUS0_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L2_DBUS1_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] +pub type L2_DBUS1_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L2_DBUS2_OVF_INT_ST` reader - Reserved"] +pub type L2_DBUS2_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `L2_DBUS3_OVF_INT_ST` reader - Reserved"] +pub type L2_DBUS3_OVF_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 8 - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] + #[inline(always)] + pub fn l2_ibus0_ovf_int_st(&self) -> L2_IBUS0_OVF_INT_ST_R { + L2_IBUS0_OVF_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] + #[inline(always)] + pub fn l2_ibus1_ovf_int_st(&self) -> L2_IBUS1_OVF_INT_ST_R { + L2_IBUS1_OVF_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn l2_ibus2_ovf_int_st(&self) -> L2_IBUS2_OVF_INT_ST_R { + L2_IBUS2_OVF_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn l2_ibus3_ovf_int_st(&self) -> L2_IBUS3_OVF_INT_ST_R { + L2_IBUS3_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."] + #[inline(always)] + pub fn l2_dbus0_ovf_int_st(&self) -> L2_DBUS0_OVF_INT_ST_R { + L2_DBUS0_OVF_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."] + #[inline(always)] + pub fn l2_dbus1_ovf_int_st(&self) -> L2_DBUS1_OVF_INT_ST_R { + L2_DBUS1_OVF_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn l2_dbus2_ovf_int_st(&self) -> L2_DBUS2_OVF_INT_ST_R { + L2_DBUS2_OVF_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn l2_dbus3_ovf_int_st(&self) -> L2_DBUS3_OVF_INT_ST_R { + L2_DBUS3_OVF_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACS_CNT_INT_ST") + .field( + "l2_ibus0_ovf_int_st", + &format_args!("{}", self.l2_ibus0_ovf_int_st().bit()), + ) + .field( + "l2_ibus1_ovf_int_st", + &format_args!("{}", self.l2_ibus1_ovf_int_st().bit()), + ) + .field( + "l2_ibus2_ovf_int_st", + &format_args!("{}", self.l2_ibus2_ovf_int_st().bit()), + ) + .field( + "l2_ibus3_ovf_int_st", + &format_args!("{}", self.l2_ibus3_ovf_int_st().bit()), + ) + .field( + "l2_dbus0_ovf_int_st", + &format_args!("{}", self.l2_dbus0_ovf_int_st().bit()), + ) + .field( + "l2_dbus1_ovf_int_st", + &format_args!("{}", self.l2_dbus1_ovf_int_st().bit()), + ) + .field( + "l2_dbus2_ovf_int_st", + &format_args!("{}", self.l2_dbus2_ovf_int_st().bit()), + ) + .field( + "l2_dbus3_ovf_int_st", + &format_args!("{}", self.l2_dbus3_ovf_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Cache Access Counter Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_CNT_INT_ST_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_CNT_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_acs_cnt_int_st::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACS_CNT_INT_ST_SPEC {} +#[doc = "`reset()` method sets L2_CACHE_ACS_CNT_INT_ST to value 0"] +impl crate::Resettable for L2_CACHE_ACS_CNT_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_acs_fail_addr.rs b/esp32p4/src/cache/l2_cache_acs_fail_addr.rs new file mode 100644 index 0000000000..48c2d9ccaf --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_fail_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_CACHE_ACS_FAIL_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `L2_CACHE_FAIL_ADDR` reader - The register records the address of fail-access when L1-Cache accesses L2-Cache."] +pub type L2_CACHE_FAIL_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the address of fail-access when L1-Cache accesses L2-Cache."] + #[inline(always)] + pub fn l2_cache_fail_addr(&self) -> L2_CACHE_FAIL_ADDR_R { + L2_CACHE_FAIL_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACS_FAIL_ADDR") + .field( + "l2_cache_fail_addr", + &format_args!("{}", self.l2_cache_fail_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_FAIL_ADDR_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_acs_fail_addr::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACS_FAIL_ADDR_SPEC {} +#[doc = "`reset()` method sets L2_CACHE_ACS_FAIL_ADDR to value 0"] +impl crate::Resettable for L2_CACHE_ACS_FAIL_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_acs_fail_ctrl.rs b/esp32p4/src/cache/l2_cache_acs_fail_ctrl.rs new file mode 100644 index 0000000000..21f7bf225d --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_fail_ctrl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_ACS_FAIL_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_ACS_FAIL_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_ACS_FAIL_CHECK_MODE` reader - The bit is used to configure l2 cache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L2_CACHE_ACS_FAIL_CHECK_MODE_R = crate::BitReader; +#[doc = "Field `L2_CACHE_ACS_FAIL_CHECK_MODE` writer - The bit is used to configure l2 cache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] +pub type L2_CACHE_ACS_FAIL_CHECK_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to configure l2 cache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + pub fn l2_cache_acs_fail_check_mode(&self) -> L2_CACHE_ACS_FAIL_CHECK_MODE_R { + L2_CACHE_ACS_FAIL_CHECK_MODE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACS_FAIL_CTRL") + .field( + "l2_cache_acs_fail_check_mode", + &format_args!("{}", self.l2_cache_acs_fail_check_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to configure l2 cache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"] + #[inline(always)] + #[must_use] + pub fn l2_cache_acs_fail_check_mode( + &mut self, + ) -> L2_CACHE_ACS_FAIL_CHECK_MODE_W { + L2_CACHE_ACS_FAIL_CHECK_MODE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Fail Configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_FAIL_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_acs_fail_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACS_FAIL_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_acs_fail_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_ACS_FAIL_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_ACS_FAIL_CTRL to value 0"] +impl crate::Resettable for L2_CACHE_ACS_FAIL_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_acs_fail_id_attr.rs b/esp32p4/src/cache/l2_cache_acs_fail_id_attr.rs new file mode 100644 index 0000000000..1b42f7dd97 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_fail_id_attr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `L2_CACHE_ACS_FAIL_ID_ATTR` reader"] +pub type R = crate::R; +#[doc = "Field `L2_CACHE_FAIL_ID` reader - The register records the ID of fail-access when L1-Cache accesses L2-Cache."] +pub type L2_CACHE_FAIL_ID_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_FAIL_ATTR` reader - The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache."] +pub type L2_CACHE_FAIL_ATTR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - The register records the ID of fail-access when L1-Cache accesses L2-Cache."] + #[inline(always)] + pub fn l2_cache_fail_id(&self) -> L2_CACHE_FAIL_ID_R { + L2_CACHE_FAIL_ID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache."] + #[inline(always)] + pub fn l2_cache_fail_attr(&self) -> L2_CACHE_FAIL_ATTR_R { + L2_CACHE_FAIL_ATTR_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACS_FAIL_ID_ATTR") + .field( + "l2_cache_fail_id", + &format_args!("{}", self.l2_cache_fail_id().bits()), + ) + .field( + "l2_cache_fail_attr", + &format_args!("{}", self.l2_cache_fail_attr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_id_attr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_FAIL_ID_ATTR_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_ID_ATTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_acs_fail_id_attr::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACS_FAIL_ID_ATTR_SPEC {} +#[doc = "`reset()` method sets L2_CACHE_ACS_FAIL_ID_ATTR to value 0"] +impl crate::Resettable for L2_CACHE_ACS_FAIL_ID_ATTR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_acs_fail_int_clr.rs b/esp32p4/src/cache/l2_cache_acs_fail_int_clr.rs new file mode 100644 index 0000000000..3ec2e77e06 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_fail_int_clr.rs @@ -0,0 +1,44 @@ +#[doc = "Register `L2_CACHE_ACS_FAIL_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_FAIL_INT_CLR` writer - The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache."] +pub type L2_CACHE_FAIL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 5 - The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_cache_fail_int_clr( + &mut self, + ) -> L2_CACHE_FAIL_INT_CLR_W { + L2_CACHE_FAIL_INT_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1-Cache Access Fail Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_FAIL_INT_CLR_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`l2_cache_acs_fail_int_clr::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_ACS_FAIL_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_ACS_FAIL_INT_CLR to value 0"] +impl crate::Resettable for L2_CACHE_ACS_FAIL_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_acs_fail_int_ena.rs b/esp32p4/src/cache/l2_cache_acs_fail_int_ena.rs new file mode 100644 index 0000000000..2f6a0a62c7 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_fail_int_ena.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_ACS_FAIL_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_ACS_FAIL_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_FAIL_INT_ENA` reader - The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache."] +pub type L2_CACHE_FAIL_INT_ENA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_FAIL_INT_ENA` writer - The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache."] +pub type L2_CACHE_FAIL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache."] + #[inline(always)] + pub fn l2_cache_fail_int_ena(&self) -> L2_CACHE_FAIL_INT_ENA_R { + L2_CACHE_FAIL_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACS_FAIL_INT_ENA") + .field( + "l2_cache_fail_int_ena", + &format_args!("{}", self.l2_cache_fail_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_cache_fail_int_ena( + &mut self, + ) -> L2_CACHE_FAIL_INT_ENA_W { + L2_CACHE_FAIL_INT_ENA_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_FAIL_INT_ENA_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_acs_fail_int_ena::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACS_FAIL_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_acs_fail_int_ena::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_ACS_FAIL_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_ACS_FAIL_INT_ENA to value 0"] +impl crate::Resettable for L2_CACHE_ACS_FAIL_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_acs_fail_int_raw.rs b/esp32p4/src/cache/l2_cache_acs_fail_int_raw.rs new file mode 100644 index 0000000000..f54f2d9fc2 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_fail_int_raw.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_ACS_FAIL_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_ACS_FAIL_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_FAIL_INT_RAW` reader - The raw bit of the interrupt of access fail that occurs in L2-Cache."] +pub type L2_CACHE_FAIL_INT_RAW_R = crate::BitReader; +#[doc = "Field `L2_CACHE_FAIL_INT_RAW` writer - The raw bit of the interrupt of access fail that occurs in L2-Cache."] +pub type L2_CACHE_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - The raw bit of the interrupt of access fail that occurs in L2-Cache."] + #[inline(always)] + pub fn l2_cache_fail_int_raw(&self) -> L2_CACHE_FAIL_INT_RAW_R { + L2_CACHE_FAIL_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACS_FAIL_INT_RAW") + .field( + "l2_cache_fail_int_raw", + &format_args!("{}", self.l2_cache_fail_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - The raw bit of the interrupt of access fail that occurs in L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_cache_fail_int_raw( + &mut self, + ) -> L2_CACHE_FAIL_INT_RAW_W { + L2_CACHE_FAIL_INT_RAW_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Access Fail Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_acs_fail_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_FAIL_INT_RAW_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_acs_fail_int_raw::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACS_FAIL_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_acs_fail_int_raw::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_ACS_FAIL_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_ACS_FAIL_INT_RAW to value 0"] +impl crate::Resettable for L2_CACHE_ACS_FAIL_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_acs_fail_int_st.rs b/esp32p4/src/cache/l2_cache_acs_fail_int_st.rs new file mode 100644 index 0000000000..dc12582969 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_acs_fail_int_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_CACHE_ACS_FAIL_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `L2_CACHE_FAIL_INT_ST` reader - The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache."] +pub type L2_CACHE_FAIL_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 5 - The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache."] + #[inline(always)] + pub fn l2_cache_fail_int_st(&self) -> L2_CACHE_FAIL_INT_ST_R { + L2_CACHE_FAIL_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_ACS_FAIL_INT_ST") + .field( + "l2_cache_fail_int_st", + &format_args!("{}", self.l2_cache_fail_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_ACS_FAIL_INT_ST_SPEC; +impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_acs_fail_int_st::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_ACS_FAIL_INT_ST_SPEC {} +#[doc = "`reset()` method sets L2_CACHE_ACS_FAIL_INT_ST to value 0"] +impl crate::Resettable for L2_CACHE_ACS_FAIL_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_autoload_buf_clr_ctrl.rs b/esp32p4/src/cache/l2_cache_autoload_buf_clr_ctrl.rs new file mode 100644 index 0000000000..a36d4a114c --- /dev/null +++ b/esp32p4/src/cache/l2_cache_autoload_buf_clr_ctrl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_AUTOLOAD_BUF_CLR_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_AUTOLOAD_BUF_CLR_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_ALD_BUF_CLR` reader - set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache."] +pub type L2_CACHE_ALD_BUF_CLR_R = crate::BitReader; +#[doc = "Field `L2_CACHE_ALD_BUF_CLR` writer - set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache."] +pub type L2_CACHE_ALD_BUF_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache."] + #[inline(always)] + pub fn l2_cache_ald_buf_clr(&self) -> L2_CACHE_ALD_BUF_CLR_R { + L2_CACHE_ALD_BUF_CLR_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_AUTOLOAD_BUF_CLR_CTRL") + .field( + "l2_cache_ald_buf_clr", + &format_args!("{}", self.l2_cache_ald_buf_clr().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_cache_ald_buf_clr( + &mut self, + ) -> L2_CACHE_ALD_BUF_CLR_W { + L2_CACHE_ALD_BUF_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Autoload buffer clear control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_buf_clr_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_buf_clr_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_autoload_buf_clr_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_autoload_buf_clr_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_AUTOLOAD_BUF_CLR_CTRL to value 0"] +impl crate::Resettable for L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_autoload_ctrl.rs b/esp32p4/src/cache/l2_cache_autoload_ctrl.rs new file mode 100644 index 0000000000..431b02db5a --- /dev/null +++ b/esp32p4/src/cache/l2_cache_autoload_ctrl.rs @@ -0,0 +1,226 @@ +#[doc = "Register `L2_CACHE_AUTOLOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_AUTOLOAD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_AUTOLOAD_ENA` reader - The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable."] +pub type L2_CACHE_AUTOLOAD_ENA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_ENA` writer - The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable."] +pub type L2_CACHE_AUTOLOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_AUTOLOAD_DONE` reader - The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished."] +pub type L2_CACHE_AUTOLOAD_DONE_R = crate::BitReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_ORDER` reader - The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending."] +pub type L2_CACHE_AUTOLOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_ORDER` writer - The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending."] +pub type L2_CACHE_AUTOLOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_AUTOLOAD_TRIGGER_MODE` reader - The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] +pub type L2_CACHE_AUTOLOAD_TRIGGER_MODE_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_TRIGGER_MODE` writer - The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] +pub type L2_CACHE_AUTOLOAD_TRIGGER_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT0_ENA` reader - The bit is used to enable the first section for autoload operation on L2-Cache."] +pub type L2_CACHE_AUTOLOAD_SCT0_ENA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT0_ENA` writer - The bit is used to enable the first section for autoload operation on L2-Cache."] +pub type L2_CACHE_AUTOLOAD_SCT0_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT1_ENA` reader - The bit is used to enable the second section for autoload operation on L2-Cache."] +pub type L2_CACHE_AUTOLOAD_SCT1_ENA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT1_ENA` writer - The bit is used to enable the second section for autoload operation on L2-Cache."] +pub type L2_CACHE_AUTOLOAD_SCT1_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT2_ENA` reader - The bit is used to enable the third section for autoload operation on L2-Cache."] +pub type L2_CACHE_AUTOLOAD_SCT2_ENA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT2_ENA` writer - The bit is used to enable the third section for autoload operation on L2-Cache."] +pub type L2_CACHE_AUTOLOAD_SCT2_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT3_ENA` reader - The bit is used to enable the fourth section for autoload operation on L2-Cache."] +pub type L2_CACHE_AUTOLOAD_SCT3_ENA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT3_ENA` writer - The bit is used to enable the fourth section for autoload operation on L2-Cache."] +pub type L2_CACHE_AUTOLOAD_SCT3_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_AUTOLOAD_RGID` reader - The bit is used to set the gid of l2 cache autoload."] +pub type L2_CACHE_AUTOLOAD_RGID_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_RGID` writer - The bit is used to set the gid of l2 cache autoload."] +pub type L2_CACHE_AUTOLOAD_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable."] + #[inline(always)] + pub fn l2_cache_autoload_ena(&self) -> L2_CACHE_AUTOLOAD_ENA_R { + L2_CACHE_AUTOLOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l2_cache_autoload_done(&self) -> L2_CACHE_AUTOLOAD_DONE_R { + L2_CACHE_AUTOLOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending."] + #[inline(always)] + pub fn l2_cache_autoload_order(&self) -> L2_CACHE_AUTOLOAD_ORDER_R { + L2_CACHE_AUTOLOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] + #[inline(always)] + pub fn l2_cache_autoload_trigger_mode(&self) -> L2_CACHE_AUTOLOAD_TRIGGER_MODE_R { + L2_CACHE_AUTOLOAD_TRIGGER_MODE_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 8 - The bit is used to enable the first section for autoload operation on L2-Cache."] + #[inline(always)] + pub fn l2_cache_autoload_sct0_ena(&self) -> L2_CACHE_AUTOLOAD_SCT0_ENA_R { + L2_CACHE_AUTOLOAD_SCT0_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The bit is used to enable the second section for autoload operation on L2-Cache."] + #[inline(always)] + pub fn l2_cache_autoload_sct1_ena(&self) -> L2_CACHE_AUTOLOAD_SCT1_ENA_R { + L2_CACHE_AUTOLOAD_SCT1_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The bit is used to enable the third section for autoload operation on L2-Cache."] + #[inline(always)] + pub fn l2_cache_autoload_sct2_ena(&self) -> L2_CACHE_AUTOLOAD_SCT2_ENA_R { + L2_CACHE_AUTOLOAD_SCT2_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The bit is used to enable the fourth section for autoload operation on L2-Cache."] + #[inline(always)] + pub fn l2_cache_autoload_sct3_ena(&self) -> L2_CACHE_AUTOLOAD_SCT3_ENA_R { + L2_CACHE_AUTOLOAD_SCT3_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:15 - The bit is used to set the gid of l2 cache autoload."] + #[inline(always)] + pub fn l2_cache_autoload_rgid(&self) -> L2_CACHE_AUTOLOAD_RGID_R { + L2_CACHE_AUTOLOAD_RGID_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_AUTOLOAD_CTRL") + .field( + "l2_cache_autoload_ena", + &format_args!("{}", self.l2_cache_autoload_ena().bit()), + ) + .field( + "l2_cache_autoload_done", + &format_args!("{}", self.l2_cache_autoload_done().bit()), + ) + .field( + "l2_cache_autoload_order", + &format_args!("{}", self.l2_cache_autoload_order().bit()), + ) + .field( + "l2_cache_autoload_trigger_mode", + &format_args!("{}", self.l2_cache_autoload_trigger_mode().bits()), + ) + .field( + "l2_cache_autoload_sct0_ena", + &format_args!("{}", self.l2_cache_autoload_sct0_ena().bit()), + ) + .field( + "l2_cache_autoload_sct1_ena", + &format_args!("{}", self.l2_cache_autoload_sct1_ena().bit()), + ) + .field( + "l2_cache_autoload_sct2_ena", + &format_args!("{}", self.l2_cache_autoload_sct2_ena().bit()), + ) + .field( + "l2_cache_autoload_sct3_ena", + &format_args!("{}", self.l2_cache_autoload_sct3_ena().bit()), + ) + .field( + "l2_cache_autoload_rgid", + &format_args!("{}", self.l2_cache_autoload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_ena( + &mut self, + ) -> L2_CACHE_AUTOLOAD_ENA_W { + L2_CACHE_AUTOLOAD_ENA_W::new(self, 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_order( + &mut self, + ) -> L2_CACHE_AUTOLOAD_ORDER_W { + L2_CACHE_AUTOLOAD_ORDER_W::new(self, 2) + } + #[doc = "Bits 3:4 - The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_trigger_mode( + &mut self, + ) -> L2_CACHE_AUTOLOAD_TRIGGER_MODE_W { + L2_CACHE_AUTOLOAD_TRIGGER_MODE_W::new(self, 3) + } + #[doc = "Bit 8 - The bit is used to enable the first section for autoload operation on L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct0_ena( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT0_ENA_W { + L2_CACHE_AUTOLOAD_SCT0_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The bit is used to enable the second section for autoload operation on L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct1_ena( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT1_ENA_W { + L2_CACHE_AUTOLOAD_SCT1_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - The bit is used to enable the third section for autoload operation on L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct2_ena( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT2_ENA_W { + L2_CACHE_AUTOLOAD_SCT2_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - The bit is used to enable the fourth section for autoload operation on L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct3_ena( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT3_ENA_W { + L2_CACHE_AUTOLOAD_SCT3_ENA_W::new(self, 11) + } + #[doc = "Bits 12:15 - The bit is used to set the gid of l2 cache autoload."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_rgid( + &mut self, + ) -> L2_CACHE_AUTOLOAD_RGID_W { + L2_CACHE_AUTOLOAD_RGID_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_AUTOLOAD_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_autoload_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_AUTOLOAD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_autoload_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_AUTOLOAD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_AUTOLOAD_CTRL to value 0x02"] +impl crate::Resettable for L2_CACHE_AUTOLOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l2_cache_autoload_sct0_addr.rs b/esp32p4/src/cache/l2_cache_autoload_sct0_addr.rs new file mode 100644 index 0000000000..e2bbeafce9 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_autoload_sct0_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT0_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT0_ADDR_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT0_ADDR` writer - Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l2_cache_autoload_sct0_addr(&self) -> L2_CACHE_AUTOLOAD_SCT0_ADDR_R { + L2_CACHE_AUTOLOAD_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_AUTOLOAD_SCT0_ADDR") + .field( + "l2_cache_autoload_sct0_addr", + &format_args!("{}", self.l2_cache_autoload_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct0_addr( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT0_ADDR_W { + L2_CACHE_AUTOLOAD_SCT0_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct0_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct0_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_autoload_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_autoload_sct0_addr::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_AUTOLOAD_SCT0_ADDR to value 0"] +impl crate::Resettable for L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_autoload_sct0_size.rs b/esp32p4/src/cache/l2_cache_autoload_sct0_size.rs new file mode 100644 index 0000000000..1c1ec3012c --- /dev/null +++ b/esp32p4/src/cache/l2_cache_autoload_sct0_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT0_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT0_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT0_SIZE` reader - Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT0_SIZE_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT0_SIZE` writer - Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + pub fn l2_cache_autoload_sct0_size(&self) -> L2_CACHE_AUTOLOAD_SCT0_SIZE_R { + L2_CACHE_AUTOLOAD_SCT0_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_AUTOLOAD_SCT0_SIZE") + .field( + "l2_cache_autoload_sct0_size", + &format_args!("{}", self.l2_cache_autoload_sct0_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct0_size( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT0_SIZE_W { + L2_CACHE_AUTOLOAD_SCT0_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct0_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct0_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC; +impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_autoload_sct0_size::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_autoload_sct0_size::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_AUTOLOAD_SCT0_SIZE to value 0"] +impl crate::Resettable for L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_autoload_sct1_addr.rs b/esp32p4/src/cache/l2_cache_autoload_sct1_addr.rs new file mode 100644 index 0000000000..eb4742b41e --- /dev/null +++ b/esp32p4/src/cache/l2_cache_autoload_sct1_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT1_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT1_ADDR_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT1_ADDR` writer - Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + pub fn l2_cache_autoload_sct1_addr(&self) -> L2_CACHE_AUTOLOAD_SCT1_ADDR_R { + L2_CACHE_AUTOLOAD_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_AUTOLOAD_SCT1_ADDR") + .field( + "l2_cache_autoload_sct1_addr", + &format_args!("{}", self.l2_cache_autoload_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct1_addr( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT1_ADDR_W { + L2_CACHE_AUTOLOAD_SCT1_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct1_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct1_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_autoload_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_autoload_sct1_addr::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_AUTOLOAD_SCT1_ADDR to value 0"] +impl crate::Resettable for L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_autoload_sct1_size.rs b/esp32p4/src/cache/l2_cache_autoload_sct1_size.rs new file mode 100644 index 0000000000..3ff7f5bc85 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_autoload_sct1_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT1_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT1_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT1_SIZE` reader - Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT1_SIZE_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT1_SIZE` writer - Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + pub fn l2_cache_autoload_sct1_size(&self) -> L2_CACHE_AUTOLOAD_SCT1_SIZE_R { + L2_CACHE_AUTOLOAD_SCT1_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_AUTOLOAD_SCT1_SIZE") + .field( + "l2_cache_autoload_sct1_size", + &format_args!("{}", self.l2_cache_autoload_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct1_size( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT1_SIZE_W { + L2_CACHE_AUTOLOAD_SCT1_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct1_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct1_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC; +impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_autoload_sct1_size::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_autoload_sct1_size::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_AUTOLOAD_SCT1_SIZE to value 0"] +impl crate::Resettable for L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_autoload_sct2_addr.rs b/esp32p4/src/cache/l2_cache_autoload_sct2_addr.rs new file mode 100644 index 0000000000..1258730885 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_autoload_sct2_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT2_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT2_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT2_ADDR` reader - Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT2_ADDR_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT2_ADDR` writer - Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT2_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA."] + #[inline(always)] + pub fn l2_cache_autoload_sct2_addr(&self) -> L2_CACHE_AUTOLOAD_SCT2_ADDR_R { + L2_CACHE_AUTOLOAD_SCT2_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_AUTOLOAD_SCT2_ADDR") + .field( + "l2_cache_autoload_sct2_addr", + &format_args!("{}", self.l2_cache_autoload_sct2_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct2_addr( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT2_ADDR_W { + L2_CACHE_AUTOLOAD_SCT2_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache autoload section 2 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct2_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct2_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC; +impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_autoload_sct2_addr::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_autoload_sct2_addr::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_AUTOLOAD_SCT2_ADDR to value 0"] +impl crate::Resettable for L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_autoload_sct2_size.rs b/esp32p4/src/cache/l2_cache_autoload_sct2_size.rs new file mode 100644 index 0000000000..54f76bd175 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_autoload_sct2_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT2_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT2_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT2_SIZE` reader - Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT2_SIZE_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT2_SIZE` writer - Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT2_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA."] + #[inline(always)] + pub fn l2_cache_autoload_sct2_size(&self) -> L2_CACHE_AUTOLOAD_SCT2_SIZE_R { + L2_CACHE_AUTOLOAD_SCT2_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_AUTOLOAD_SCT2_SIZE") + .field( + "l2_cache_autoload_sct2_size", + &format_args!("{}", self.l2_cache_autoload_sct2_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct2_size( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT2_SIZE_W { + L2_CACHE_AUTOLOAD_SCT2_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache autoload section 2 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct2_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct2_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC; +impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_autoload_sct2_size::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_autoload_sct2_size::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_AUTOLOAD_SCT2_SIZE to value 0"] +impl crate::Resettable for L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_autoload_sct3_addr.rs b/esp32p4/src/cache/l2_cache_autoload_sct3_addr.rs new file mode 100644 index 0000000000..51e5522b21 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_autoload_sct3_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT3_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT3_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT3_ADDR` reader - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT3_ADDR_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT3_ADDR` writer - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT3_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA."] + #[inline(always)] + pub fn l2_cache_autoload_sct3_addr(&self) -> L2_CACHE_AUTOLOAD_SCT3_ADDR_R { + L2_CACHE_AUTOLOAD_SCT3_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_AUTOLOAD_SCT3_ADDR") + .field( + "l2_cache_autoload_sct3_addr", + &format_args!("{}", self.l2_cache_autoload_sct3_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct3_addr( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT3_ADDR_W { + L2_CACHE_AUTOLOAD_SCT3_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache autoload section 3 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct3_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct3_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC; +impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_autoload_sct3_addr::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_autoload_sct3_addr::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_AUTOLOAD_SCT3_ADDR to value 0"] +impl crate::Resettable for L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_autoload_sct3_size.rs b/esp32p4/src/cache/l2_cache_autoload_sct3_size.rs new file mode 100644 index 0000000000..bccee584c6 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_autoload_sct3_size.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT3_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_AUTOLOAD_SCT3_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT3_SIZE` reader - Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT3_SIZE_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_AUTOLOAD_SCT3_SIZE` writer - Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA."] +pub type L2_CACHE_AUTOLOAD_SCT3_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA."] + #[inline(always)] + pub fn l2_cache_autoload_sct3_size(&self) -> L2_CACHE_AUTOLOAD_SCT3_SIZE_R { + L2_CACHE_AUTOLOAD_SCT3_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_AUTOLOAD_SCT3_SIZE") + .field( + "l2_cache_autoload_sct3_size", + &format_args!("{}", self.l2_cache_autoload_sct3_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA."] + #[inline(always)] + #[must_use] + pub fn l2_cache_autoload_sct3_size( + &mut self, + ) -> L2_CACHE_AUTOLOAD_SCT3_SIZE_W { + L2_CACHE_AUTOLOAD_SCT3_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache autoload section 3 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct3_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_autoload_sct3_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC; +impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_autoload_sct3_size::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_autoload_sct3_size::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_AUTOLOAD_SCT3_SIZE to value 0"] +impl crate::Resettable for L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_blocksize_conf.rs b/esp32p4/src/cache/l2_cache_blocksize_conf.rs new file mode 100644 index 0000000000..9b86897f6e --- /dev/null +++ b/esp32p4/src/cache/l2_cache_blocksize_conf.rs @@ -0,0 +1,133 @@ +#[doc = "Register `L2_CACHE_BLOCKSIZE_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_BLOCKSIZE_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_BLOCKSIZE_8` reader - The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_BLOCKSIZE_8_R = crate::BitReader; +#[doc = "Field `L2_CACHE_BLOCKSIZE_16` reader - The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_BLOCKSIZE_16_R = crate::BitReader; +#[doc = "Field `L2_CACHE_BLOCKSIZE_32` reader - The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_BLOCKSIZE_32_R = crate::BitReader; +#[doc = "Field `L2_CACHE_BLOCKSIZE_64` reader - The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_BLOCKSIZE_64_R = crate::BitReader; +#[doc = "Field `L2_CACHE_BLOCKSIZE_64` writer - The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_BLOCKSIZE_64_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_BLOCKSIZE_128` reader - The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_BLOCKSIZE_128_R = crate::BitReader; +#[doc = "Field `L2_CACHE_BLOCKSIZE_128` writer - The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_BLOCKSIZE_128_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_BLOCKSIZE_256` reader - The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_BLOCKSIZE_256_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_blocksize_8(&self) -> L2_CACHE_BLOCKSIZE_8_R { + L2_CACHE_BLOCKSIZE_8_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_blocksize_16(&self) -> L2_CACHE_BLOCKSIZE_16_R { + L2_CACHE_BLOCKSIZE_16_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_blocksize_32(&self) -> L2_CACHE_BLOCKSIZE_32_R { + L2_CACHE_BLOCKSIZE_32_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_blocksize_64(&self) -> L2_CACHE_BLOCKSIZE_64_R { + L2_CACHE_BLOCKSIZE_64_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_blocksize_128(&self) -> L2_CACHE_BLOCKSIZE_128_R { + L2_CACHE_BLOCKSIZE_128_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_blocksize_256(&self) -> L2_CACHE_BLOCKSIZE_256_R { + L2_CACHE_BLOCKSIZE_256_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_BLOCKSIZE_CONF") + .field( + "l2_cache_blocksize_8", + &format_args!("{}", self.l2_cache_blocksize_8().bit()), + ) + .field( + "l2_cache_blocksize_16", + &format_args!("{}", self.l2_cache_blocksize_16().bit()), + ) + .field( + "l2_cache_blocksize_32", + &format_args!("{}", self.l2_cache_blocksize_32().bit()), + ) + .field( + "l2_cache_blocksize_64", + &format_args!("{}", self.l2_cache_blocksize_64().bit()), + ) + .field( + "l2_cache_blocksize_128", + &format_args!("{}", self.l2_cache_blocksize_128().bit()), + ) + .field( + "l2_cache_blocksize_256", + &format_args!("{}", self.l2_cache_blocksize_256().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 3 - The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + #[must_use] + pub fn l2_cache_blocksize_64( + &mut self, + ) -> L2_CACHE_BLOCKSIZE_64_W { + L2_CACHE_BLOCKSIZE_64_W::new(self, 3) + } + #[doc = "Bit 4 - The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + #[must_use] + pub fn l2_cache_blocksize_128( + &mut self, + ) -> L2_CACHE_BLOCKSIZE_128_W { + L2_CACHE_BLOCKSIZE_128_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_blocksize_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_blocksize_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_BLOCKSIZE_CONF_SPEC; +impl crate::RegisterSpec for L2_CACHE_BLOCKSIZE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_blocksize_conf::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_BLOCKSIZE_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_blocksize_conf::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_BLOCKSIZE_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_BLOCKSIZE_CONF to value 0x08"] +impl crate::Resettable for L2_CACHE_BLOCKSIZE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/cache/l2_cache_cachesize_conf.rs b/esp32p4/src/cache/l2_cache_cachesize_conf.rs new file mode 100644 index 0000000000..08856c485a --- /dev/null +++ b/esp32p4/src/cache/l2_cache_cachesize_conf.rs @@ -0,0 +1,220 @@ +#[doc = "Register `L2_CACHE_CACHESIZE_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_CACHESIZE_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_CACHESIZE_256` reader - The field is used to configure cachesize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_256_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_512` reader - The field is used to configure cachesize of L2-Cache as 512 bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_512_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_1K` reader - The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_1K_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_2K` reader - The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_2K_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_4K` reader - The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_4K_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_8K` reader - The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_8K_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_16K` reader - The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_16K_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_32K` reader - The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_32K_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_64K` reader - The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_64K_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_128K` reader - The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_128K_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_128K` writer - The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_128K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_CACHESIZE_256K` reader - The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_256K_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_256K` writer - The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_256K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_CACHESIZE_512K` reader - The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_512K_R = crate::BitReader; +#[doc = "Field `L2_CACHE_CACHESIZE_512K` writer - The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_512K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_CACHESIZE_1024K` reader - The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot."] +pub type L2_CACHE_CACHESIZE_1024K_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The field is used to configure cachesize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_256(&self) -> L2_CACHE_CACHESIZE_256_R { + L2_CACHE_CACHESIZE_256_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The field is used to configure cachesize of L2-Cache as 512 bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_512(&self) -> L2_CACHE_CACHESIZE_512_R { + L2_CACHE_CACHESIZE_512_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_1k(&self) -> L2_CACHE_CACHESIZE_1K_R { + L2_CACHE_CACHESIZE_1K_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_2k(&self) -> L2_CACHE_CACHESIZE_2K_R { + L2_CACHE_CACHESIZE_2K_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_4k(&self) -> L2_CACHE_CACHESIZE_4K_R { + L2_CACHE_CACHESIZE_4K_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_8k(&self) -> L2_CACHE_CACHESIZE_8K_R { + L2_CACHE_CACHESIZE_8K_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_16k(&self) -> L2_CACHE_CACHESIZE_16K_R { + L2_CACHE_CACHESIZE_16K_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_32k(&self) -> L2_CACHE_CACHESIZE_32K_R { + L2_CACHE_CACHESIZE_32K_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_64k(&self) -> L2_CACHE_CACHESIZE_64K_R { + L2_CACHE_CACHESIZE_64K_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_128k(&self) -> L2_CACHE_CACHESIZE_128K_R { + L2_CACHE_CACHESIZE_128K_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_256k(&self) -> L2_CACHE_CACHESIZE_256K_R { + L2_CACHE_CACHESIZE_256K_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_512k(&self) -> L2_CACHE_CACHESIZE_512K_R { + L2_CACHE_CACHESIZE_512K_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + pub fn l2_cache_cachesize_1024k(&self) -> L2_CACHE_CACHESIZE_1024K_R { + L2_CACHE_CACHESIZE_1024K_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_CACHESIZE_CONF") + .field( + "l2_cache_cachesize_256", + &format_args!("{}", self.l2_cache_cachesize_256().bit()), + ) + .field( + "l2_cache_cachesize_512", + &format_args!("{}", self.l2_cache_cachesize_512().bit()), + ) + .field( + "l2_cache_cachesize_1k", + &format_args!("{}", self.l2_cache_cachesize_1k().bit()), + ) + .field( + "l2_cache_cachesize_2k", + &format_args!("{}", self.l2_cache_cachesize_2k().bit()), + ) + .field( + "l2_cache_cachesize_4k", + &format_args!("{}", self.l2_cache_cachesize_4k().bit()), + ) + .field( + "l2_cache_cachesize_8k", + &format_args!("{}", self.l2_cache_cachesize_8k().bit()), + ) + .field( + "l2_cache_cachesize_16k", + &format_args!("{}", self.l2_cache_cachesize_16k().bit()), + ) + .field( + "l2_cache_cachesize_32k", + &format_args!("{}", self.l2_cache_cachesize_32k().bit()), + ) + .field( + "l2_cache_cachesize_64k", + &format_args!("{}", self.l2_cache_cachesize_64k().bit()), + ) + .field( + "l2_cache_cachesize_128k", + &format_args!("{}", self.l2_cache_cachesize_128k().bit()), + ) + .field( + "l2_cache_cachesize_256k", + &format_args!("{}", self.l2_cache_cachesize_256k().bit()), + ) + .field( + "l2_cache_cachesize_512k", + &format_args!("{}", self.l2_cache_cachesize_512k().bit()), + ) + .field( + "l2_cache_cachesize_1024k", + &format_args!("{}", self.l2_cache_cachesize_1024k().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 9 - The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + #[must_use] + pub fn l2_cache_cachesize_128k( + &mut self, + ) -> L2_CACHE_CACHESIZE_128K_W { + L2_CACHE_CACHESIZE_128K_W::new(self, 9) + } + #[doc = "Bit 10 - The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + #[must_use] + pub fn l2_cache_cachesize_256k( + &mut self, + ) -> L2_CACHE_CACHESIZE_256K_W { + L2_CACHE_CACHESIZE_256K_W::new(self, 10) + } + #[doc = "Bit 11 - The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot."] + #[inline(always)] + #[must_use] + pub fn l2_cache_cachesize_512k( + &mut self, + ) -> L2_CACHE_CACHESIZE_512K_W { + L2_CACHE_CACHESIZE_512K_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_cachesize_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_cachesize_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_CACHESIZE_CONF_SPEC; +impl crate::RegisterSpec for L2_CACHE_CACHESIZE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_cachesize_conf::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_CACHESIZE_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_cachesize_conf::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_CACHESIZE_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_CACHESIZE_CONF to value 0x0400"] +impl crate::Resettable for L2_CACHE_CACHESIZE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0400; +} diff --git a/esp32p4/src/cache/l2_cache_ctrl.rs b/esp32p4/src/cache/l2_cache_ctrl.rs new file mode 100644 index 0000000000..bc927f29c0 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `L2_CACHE_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_SHUT_DMA` reader - The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable"] +pub type L2_CACHE_SHUT_DMA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_SHUT_DMA` writer - The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable"] +pub type L2_CACHE_SHUT_DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_UNDEF_OP` reader - Reserved"] +pub type L2_CACHE_UNDEF_OP_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_UNDEF_OP` writer - Reserved"] +pub type L2_CACHE_UNDEF_OP_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 4 - The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable"] + #[inline(always)] + pub fn l2_cache_shut_dma(&self) -> L2_CACHE_SHUT_DMA_R { + L2_CACHE_SHUT_DMA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn l2_cache_undef_op(&self) -> L2_CACHE_UNDEF_OP_R { + L2_CACHE_UNDEF_OP_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_CTRL") + .field( + "l2_cache_shut_dma", + &format_args!("{}", self.l2_cache_shut_dma().bit()), + ) + .field( + "l2_cache_undef_op", + &format_args!("{}", self.l2_cache_undef_op().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 4 - The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable"] + #[inline(always)] + #[must_use] + pub fn l2_cache_shut_dma(&mut self) -> L2_CACHE_SHUT_DMA_W { + L2_CACHE_SHUT_DMA_W::new(self, 4) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn l2_cache_undef_op(&mut self) -> L2_CACHE_UNDEF_OP_W { + L2_CACHE_UNDEF_OP_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache(L2-Cache) control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_CTRL to value 0x10"] +impl crate::Resettable for L2_CACHE_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/esp32p4/src/cache/l2_cache_data_mem_acs_conf.rs b/esp32p4/src/cache/l2_cache_data_mem_acs_conf.rs new file mode 100644 index 0000000000..564094392f --- /dev/null +++ b/esp32p4/src/cache/l2_cache_data_mem_acs_conf.rs @@ -0,0 +1,89 @@ +#[doc = "Register `L2_CACHE_DATA_MEM_ACS_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_DATA_MEM_ACS_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_DATA_MEM_RD_EN` reader - The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable."] +pub type L2_CACHE_DATA_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L2_CACHE_DATA_MEM_RD_EN` writer - The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable."] +pub type L2_CACHE_DATA_MEM_RD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_DATA_MEM_WR_EN` reader - The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable."] +pub type L2_CACHE_DATA_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L2_CACHE_DATA_MEM_WR_EN` writer - The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable."] +pub type L2_CACHE_DATA_MEM_WR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 20 - The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l2_cache_data_mem_rd_en(&self) -> L2_CACHE_DATA_MEM_RD_EN_R { + L2_CACHE_DATA_MEM_RD_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l2_cache_data_mem_wr_en(&self) -> L2_CACHE_DATA_MEM_WR_EN_R { + L2_CACHE_DATA_MEM_WR_EN_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_DATA_MEM_ACS_CONF") + .field( + "l2_cache_data_mem_rd_en", + &format_args!("{}", self.l2_cache_data_mem_rd_en().bit()), + ) + .field( + "l2_cache_data_mem_wr_en", + &format_args!("{}", self.l2_cache_data_mem_wr_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l2_cache_data_mem_rd_en( + &mut self, + ) -> L2_CACHE_DATA_MEM_RD_EN_W { + L2_CACHE_DATA_MEM_RD_EN_W::new(self, 20) + } + #[doc = "Bit 21 - The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l2_cache_data_mem_wr_en( + &mut self, + ) -> L2_CACHE_DATA_MEM_WR_EN_W { + L2_CACHE_DATA_MEM_WR_EN_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache data memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_data_mem_acs_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_data_mem_acs_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_DATA_MEM_ACS_CONF_SPEC; +impl crate::RegisterSpec for L2_CACHE_DATA_MEM_ACS_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_data_mem_acs_conf::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_DATA_MEM_ACS_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_data_mem_acs_conf::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_DATA_MEM_ACS_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_DATA_MEM_ACS_CONF to value 0x0030_0000"] +impl crate::Resettable for L2_CACHE_DATA_MEM_ACS_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0030_0000; +} diff --git a/esp32p4/src/cache/l2_cache_data_mem_power_ctrl.rs b/esp32p4/src/cache/l2_cache_data_mem_power_ctrl.rs new file mode 100644 index 0000000000..d0d8c1662d --- /dev/null +++ b/esp32p4/src/cache/l2_cache_data_mem_power_ctrl.rs @@ -0,0 +1,110 @@ +#[doc = "Register `L2_CACHE_DATA_MEM_POWER_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_DATA_MEM_POWER_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_ON` reader - The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating."] +pub type L2_CACHE_DATA_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_ON` writer - The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating."] +pub type L2_CACHE_DATA_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_PD` reader - The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down"] +pub type L2_CACHE_DATA_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_PD` writer - The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down"] +pub type L2_CACHE_DATA_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_PU` reader - The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up"] +pub type L2_CACHE_DATA_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L2_CACHE_DATA_MEM_FORCE_PU` writer - The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up"] +pub type L2_CACHE_DATA_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 20 - The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + pub fn l2_cache_data_mem_force_on(&self) -> L2_CACHE_DATA_MEM_FORCE_ON_R { + L2_CACHE_DATA_MEM_FORCE_ON_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + pub fn l2_cache_data_mem_force_pd(&self) -> L2_CACHE_DATA_MEM_FORCE_PD_R { + L2_CACHE_DATA_MEM_FORCE_PD_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + pub fn l2_cache_data_mem_force_pu(&self) -> L2_CACHE_DATA_MEM_FORCE_PU_R { + L2_CACHE_DATA_MEM_FORCE_PU_R::new(((self.bits >> 22) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_DATA_MEM_POWER_CTRL") + .field( + "l2_cache_data_mem_force_on", + &format_args!("{}", self.l2_cache_data_mem_force_on().bit()), + ) + .field( + "l2_cache_data_mem_force_pd", + &format_args!("{}", self.l2_cache_data_mem_force_pd().bit()), + ) + .field( + "l2_cache_data_mem_force_pu", + &format_args!("{}", self.l2_cache_data_mem_force_pu().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + #[must_use] + pub fn l2_cache_data_mem_force_on( + &mut self, + ) -> L2_CACHE_DATA_MEM_FORCE_ON_W { + L2_CACHE_DATA_MEM_FORCE_ON_W::new(self, 20) + } + #[doc = "Bit 21 - The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + #[must_use] + pub fn l2_cache_data_mem_force_pd( + &mut self, + ) -> L2_CACHE_DATA_MEM_FORCE_PD_W { + L2_CACHE_DATA_MEM_FORCE_PD_W::new(self, 21) + } + #[doc = "Bit 22 - The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + #[must_use] + pub fn l2_cache_data_mem_force_pu( + &mut self, + ) -> L2_CACHE_DATA_MEM_FORCE_PU_W { + L2_CACHE_DATA_MEM_FORCE_PU_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache data memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_data_mem_power_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_data_mem_power_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_DATA_MEM_POWER_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_DATA_MEM_POWER_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_data_mem_power_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_DATA_MEM_POWER_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_data_mem_power_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_DATA_MEM_POWER_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_DATA_MEM_POWER_CTRL to value 0x0050_0000"] +impl crate::Resettable for L2_CACHE_DATA_MEM_POWER_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0050_0000; +} diff --git a/esp32p4/src/cache/l2_cache_debug_bus.rs b/esp32p4/src/cache/l2_cache_debug_bus.rs new file mode 100644 index 0000000000..8f08bb62cc --- /dev/null +++ b/esp32p4/src/cache/l2_cache_debug_bus.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L2_CACHE_DEBUG_BUS` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_DEBUG_BUS` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_DEBUG_BUS` reader - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."] +pub type L2_CACHE_DEBUG_BUS_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_DEBUG_BUS` writer - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."] +pub type L2_CACHE_DEBUG_BUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."] + #[inline(always)] + pub fn l2_cache_debug_bus(&self) -> L2_CACHE_DEBUG_BUS_R { + L2_CACHE_DEBUG_BUS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_DEBUG_BUS") + .field( + "l2_cache_debug_bus", + &format_args!("{}", self.l2_cache_debug_bus().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."] + #[inline(always)] + #[must_use] + pub fn l2_cache_debug_bus(&mut self) -> L2_CACHE_DEBUG_BUS_W { + L2_CACHE_DEBUG_BUS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Tag/data memory content register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_debug_bus::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_debug_bus::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_DEBUG_BUS_SPEC; +impl crate::RegisterSpec for L2_CACHE_DEBUG_BUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_debug_bus::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_DEBUG_BUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_debug_bus::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_DEBUG_BUS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_DEBUG_BUS to value 0x03cc"] +impl crate::Resettable for L2_CACHE_DEBUG_BUS_SPEC { + const RESET_VALUE: Self::Ux = 0x03cc; +} diff --git a/esp32p4/src/cache/l2_cache_freeze_ctrl.rs b/esp32p4/src/cache/l2_cache_freeze_ctrl.rs new file mode 100644 index 0000000000..e7e9d22185 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_freeze_ctrl.rs @@ -0,0 +1,96 @@ +#[doc = "Register `L2_CACHE_FREEZE_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_FREEZE_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_FREEZE_EN` reader - The bit is used to enable freeze operation on L2-Cache. It can be cleared by software."] +pub type L2_CACHE_FREEZE_EN_R = crate::BitReader; +#[doc = "Field `L2_CACHE_FREEZE_EN` writer - The bit is used to enable freeze operation on L2-Cache. It can be cleared by software."] +pub type L2_CACHE_FREEZE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_FREEZE_MODE` reader - The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck."] +pub type L2_CACHE_FREEZE_MODE_R = crate::BitReader; +#[doc = "Field `L2_CACHE_FREEZE_MODE` writer - The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck."] +pub type L2_CACHE_FREEZE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_FREEZE_DONE` reader - The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished."] +pub type L2_CACHE_FREEZE_DONE_R = crate::BitReader; +impl R { + #[doc = "Bit 20 - The bit is used to enable freeze operation on L2-Cache. It can be cleared by software."] + #[inline(always)] + pub fn l2_cache_freeze_en(&self) -> L2_CACHE_FREEZE_EN_R { + L2_CACHE_FREEZE_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck."] + #[inline(always)] + pub fn l2_cache_freeze_mode(&self) -> L2_CACHE_FREEZE_MODE_R { + L2_CACHE_FREEZE_MODE_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l2_cache_freeze_done(&self) -> L2_CACHE_FREEZE_DONE_R { + L2_CACHE_FREEZE_DONE_R::new(((self.bits >> 22) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_FREEZE_CTRL") + .field( + "l2_cache_freeze_en", + &format_args!("{}", self.l2_cache_freeze_en().bit()), + ) + .field( + "l2_cache_freeze_mode", + &format_args!("{}", self.l2_cache_freeze_mode().bit()), + ) + .field( + "l2_cache_freeze_done", + &format_args!("{}", self.l2_cache_freeze_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - The bit is used to enable freeze operation on L2-Cache. It can be cleared by software."] + #[inline(always)] + #[must_use] + pub fn l2_cache_freeze_en(&mut self) -> L2_CACHE_FREEZE_EN_W { + L2_CACHE_FREEZE_EN_W::new(self, 20) + } + #[doc = "Bit 21 - The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck."] + #[inline(always)] + #[must_use] + pub fn l2_cache_freeze_mode(&mut self) -> L2_CACHE_FREEZE_MODE_W { + L2_CACHE_FREEZE_MODE_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Freeze control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_freeze_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_freeze_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_FREEZE_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_FREEZE_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_freeze_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_FREEZE_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_freeze_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_FREEZE_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_FREEZE_CTRL to value 0"] +impl crate::Resettable for L2_CACHE_FREEZE_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_object_ctrl.rs b/esp32p4/src/cache/l2_cache_object_ctrl.rs new file mode 100644 index 0000000000..b644ebbe7d --- /dev/null +++ b/esp32p4/src/cache/l2_cache_object_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `L2_CACHE_OBJECT_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_OBJECT_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_TAG_OBJECT` reader - Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register."] +pub type L2_CACHE_TAG_OBJECT_R = crate::BitReader; +#[doc = "Field `L2_CACHE_TAG_OBJECT` writer - Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register."] +pub type L2_CACHE_TAG_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_MEM_OBJECT` reader - Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register."] +pub type L2_CACHE_MEM_OBJECT_R = crate::BitReader; +#[doc = "Field `L2_CACHE_MEM_OBJECT` writer - Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register."] +pub type L2_CACHE_MEM_OBJECT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + pub fn l2_cache_tag_object(&self) -> L2_CACHE_TAG_OBJECT_R { + L2_CACHE_TAG_OBJECT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 11 - Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + pub fn l2_cache_mem_object(&self) -> L2_CACHE_MEM_OBJECT_R { + L2_CACHE_MEM_OBJECT_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_OBJECT_CTRL") + .field( + "l2_cache_tag_object", + &format_args!("{}", self.l2_cache_tag_object().bit()), + ) + .field( + "l2_cache_mem_object", + &format_args!("{}", self.l2_cache_mem_object().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + #[must_use] + pub fn l2_cache_tag_object(&mut self) -> L2_CACHE_TAG_OBJECT_W { + L2_CACHE_TAG_OBJECT_W::new(self, 5) + } + #[doc = "Bit 11 - Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register."] + #[inline(always)] + #[must_use] + pub fn l2_cache_mem_object(&mut self) -> L2_CACHE_MEM_OBJECT_W { + L2_CACHE_MEM_OBJECT_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Tag and Data memory Object control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_object_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_object_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_OBJECT_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_OBJECT_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_object_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_OBJECT_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_object_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_OBJECT_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_OBJECT_CTRL to value 0"] +impl crate::Resettable for L2_CACHE_OBJECT_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_preload_addr.rs b/esp32p4/src/cache/l2_cache_preload_addr.rs new file mode 100644 index 0000000000..b372e1ba60 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_preload_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L2_CACHE_PRELOAD_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_PRELOAD_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_PRELOAD_ADDR` reader - Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG"] +pub type L2_CACHE_PRELOAD_ADDR_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_PRELOAD_ADDR` writer - Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG"] +pub type L2_CACHE_PRELOAD_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG"] + #[inline(always)] + pub fn l2_cache_preload_addr(&self) -> L2_CACHE_PRELOAD_ADDR_R { + L2_CACHE_PRELOAD_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_PRELOAD_ADDR") + .field( + "l2_cache_preload_addr", + &format_args!("{}", self.l2_cache_preload_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l2_cache_preload_addr(&mut self) -> L2_CACHE_PRELOAD_ADDR_W { + L2_CACHE_PRELOAD_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_PRELOAD_ADDR_SPEC; +impl crate::RegisterSpec for L2_CACHE_PRELOAD_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_preload_addr::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_PRELOAD_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_preload_addr::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_PRELOAD_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_PRELOAD_ADDR to value 0"] +impl crate::Resettable for L2_CACHE_PRELOAD_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_preload_ctrl.rs b/esp32p4/src/cache/l2_cache_preload_ctrl.rs new file mode 100644 index 0000000000..c143367548 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_preload_ctrl.rs @@ -0,0 +1,117 @@ +#[doc = "Register `L2_CACHE_PRELOAD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_PRELOAD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_PRELOAD_ENA` reader - The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done."] +pub type L2_CACHE_PRELOAD_ENA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_PRELOAD_ENA` writer - The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done."] +pub type L2_CACHE_PRELOAD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_PRELOAD_DONE` reader - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] +pub type L2_CACHE_PRELOAD_DONE_R = crate::BitReader; +#[doc = "Field `L2_CACHE_PRELOAD_ORDER` reader - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] +pub type L2_CACHE_PRELOAD_ORDER_R = crate::BitReader; +#[doc = "Field `L2_CACHE_PRELOAD_ORDER` writer - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] +pub type L2_CACHE_PRELOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_PRELOAD_RGID` reader - The bit is used to set the gid of l2 cache preload."] +pub type L2_CACHE_PRELOAD_RGID_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_PRELOAD_RGID` writer - The bit is used to set the gid of l2 cache preload."] +pub type L2_CACHE_PRELOAD_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done."] + #[inline(always)] + pub fn l2_cache_preload_ena(&self) -> L2_CACHE_PRELOAD_ENA_R { + L2_CACHE_PRELOAD_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn l2_cache_preload_done(&self) -> L2_CACHE_PRELOAD_DONE_R { + L2_CACHE_PRELOAD_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] + #[inline(always)] + pub fn l2_cache_preload_order(&self) -> L2_CACHE_PRELOAD_ORDER_R { + L2_CACHE_PRELOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of l2 cache preload."] + #[inline(always)] + pub fn l2_cache_preload_rgid(&self) -> L2_CACHE_PRELOAD_RGID_R { + L2_CACHE_PRELOAD_RGID_R::new(((self.bits >> 3) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_PRELOAD_CTRL") + .field( + "l2_cache_preload_ena", + &format_args!("{}", self.l2_cache_preload_ena().bit()), + ) + .field( + "l2_cache_preload_done", + &format_args!("{}", self.l2_cache_preload_done().bit()), + ) + .field( + "l2_cache_preload_order", + &format_args!("{}", self.l2_cache_preload_order().bit()), + ) + .field( + "l2_cache_preload_rgid", + &format_args!("{}", self.l2_cache_preload_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done."] + #[inline(always)] + #[must_use] + pub fn l2_cache_preload_ena(&mut self) -> L2_CACHE_PRELOAD_ENA_W { + L2_CACHE_PRELOAD_ENA_W::new(self, 0) + } + #[doc = "Bit 2 - The bit is used to configure the direction of preload operation. 0: ascending, 1: descending."] + #[inline(always)] + #[must_use] + pub fn l2_cache_preload_order( + &mut self, + ) -> L2_CACHE_PRELOAD_ORDER_W { + L2_CACHE_PRELOAD_ORDER_W::new(self, 2) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of l2 cache preload."] + #[inline(always)] + #[must_use] + pub fn l2_cache_preload_rgid(&mut self) -> L2_CACHE_PRELOAD_RGID_W { + L2_CACHE_PRELOAD_RGID_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_PRELOAD_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_PRELOAD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_preload_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_PRELOAD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_preload_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_PRELOAD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_PRELOAD_CTRL to value 0x02"] +impl crate::Resettable for L2_CACHE_PRELOAD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/cache/l2_cache_preload_rst_ctrl.rs b/esp32p4/src/cache/l2_cache_preload_rst_ctrl.rs new file mode 100644 index 0000000000..c80696eb80 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_preload_rst_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L2_CACHE_PRELOAD_RST_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_PRELOAD_RST_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_PLD_RST` reader - set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] +pub type L2_CACHE_PLD_RST_R = crate::BitReader; +#[doc = "Field `L2_CACHE_PLD_RST` writer - set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] +pub type L2_CACHE_PLD_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] + #[inline(always)] + pub fn l2_cache_pld_rst(&self) -> L2_CACHE_PLD_RST_R { + L2_CACHE_PLD_RST_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_PRELOAD_RST_CTRL") + .field( + "l2_cache_pld_rst", + &format_args!("{}", self.l2_cache_pld_rst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."] + #[inline(always)] + #[must_use] + pub fn l2_cache_pld_rst(&mut self) -> L2_CACHE_PLD_RST_W { + L2_CACHE_PLD_RST_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Preload Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_rst_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_rst_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_PRELOAD_RST_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_PRELOAD_RST_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_preload_rst_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_PRELOAD_RST_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_preload_rst_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_PRELOAD_RST_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_PRELOAD_RST_CTRL to value 0"] +impl crate::Resettable for L2_CACHE_PRELOAD_RST_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_preload_size.rs b/esp32p4/src/cache/l2_cache_preload_size.rs new file mode 100644 index 0000000000..4d1938aee0 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_preload_size.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L2_CACHE_PRELOAD_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_PRELOAD_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_PRELOAD_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG"] +pub type L2_CACHE_PRELOAD_SIZE_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_PRELOAD_SIZE` writer - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG"] +pub type L2_CACHE_PRELOAD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG"] + #[inline(always)] + pub fn l2_cache_preload_size(&self) -> L2_CACHE_PRELOAD_SIZE_R { + L2_CACHE_PRELOAD_SIZE_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_PRELOAD_SIZE") + .field( + "l2_cache_preload_size", + &format_args!("{}", self.l2_cache_preload_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l2_cache_preload_size(&mut self) -> L2_CACHE_PRELOAD_SIZE_W { + L2_CACHE_PRELOAD_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_preload_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_PRELOAD_SIZE_SPEC; +impl crate::RegisterSpec for L2_CACHE_PRELOAD_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_preload_size::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_PRELOAD_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_preload_size::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_PRELOAD_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_PRELOAD_SIZE to value 0"] +impl crate::Resettable for L2_CACHE_PRELOAD_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_prelock_conf.rs b/esp32p4/src/cache/l2_cache_prelock_conf.rs new file mode 100644 index 0000000000..7fb35aabb5 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_prelock_conf.rs @@ -0,0 +1,108 @@ +#[doc = "Register `L2_CACHE_PRELOCK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_PRELOCK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_PRELOCK_SCT0_EN` reader - The bit is used to enable the first section of prelock function on L2-Cache."] +pub type L2_CACHE_PRELOCK_SCT0_EN_R = crate::BitReader; +#[doc = "Field `L2_CACHE_PRELOCK_SCT0_EN` writer - The bit is used to enable the first section of prelock function on L2-Cache."] +pub type L2_CACHE_PRELOCK_SCT0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_PRELOCK_SCT1_EN` reader - The bit is used to enable the second section of prelock function on L2-Cache."] +pub type L2_CACHE_PRELOCK_SCT1_EN_R = crate::BitReader; +#[doc = "Field `L2_CACHE_PRELOCK_SCT1_EN` writer - The bit is used to enable the second section of prelock function on L2-Cache."] +pub type L2_CACHE_PRELOCK_SCT1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_PRELOCK_RGID` reader - The bit is used to set the gid of l2 cache prelock."] +pub type L2_CACHE_PRELOCK_RGID_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_PRELOCK_RGID` writer - The bit is used to set the gid of l2 cache prelock."] +pub type L2_CACHE_PRELOCK_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L2-Cache."] + #[inline(always)] + pub fn l2_cache_prelock_sct0_en(&self) -> L2_CACHE_PRELOCK_SCT0_EN_R { + L2_CACHE_PRELOCK_SCT0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable the second section of prelock function on L2-Cache."] + #[inline(always)] + pub fn l2_cache_prelock_sct1_en(&self) -> L2_CACHE_PRELOCK_SCT1_EN_R { + L2_CACHE_PRELOCK_SCT1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The bit is used to set the gid of l2 cache prelock."] + #[inline(always)] + pub fn l2_cache_prelock_rgid(&self) -> L2_CACHE_PRELOCK_RGID_R { + L2_CACHE_PRELOCK_RGID_R::new(((self.bits >> 2) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_PRELOCK_CONF") + .field( + "l2_cache_prelock_sct0_en", + &format_args!("{}", self.l2_cache_prelock_sct0_en().bit()), + ) + .field( + "l2_cache_prelock_sct1_en", + &format_args!("{}", self.l2_cache_prelock_sct1_en().bit()), + ) + .field( + "l2_cache_prelock_rgid", + &format_args!("{}", self.l2_cache_prelock_rgid().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_cache_prelock_sct0_en( + &mut self, + ) -> L2_CACHE_PRELOCK_SCT0_EN_W { + L2_CACHE_PRELOCK_SCT0_EN_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable the second section of prelock function on L2-Cache."] + #[inline(always)] + #[must_use] + pub fn l2_cache_prelock_sct1_en( + &mut self, + ) -> L2_CACHE_PRELOCK_SCT1_EN_W { + L2_CACHE_PRELOCK_SCT1_EN_W::new(self, 1) + } + #[doc = "Bits 2:5 - The bit is used to set the gid of l2 cache prelock."] + #[inline(always)] + #[must_use] + pub fn l2_cache_prelock_rgid(&mut self) -> L2_CACHE_PRELOCK_RGID_W { + L2_CACHE_PRELOCK_RGID_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_PRELOCK_CONF_SPEC; +impl crate::RegisterSpec for L2_CACHE_PRELOCK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_prelock_conf::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_PRELOCK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_prelock_conf::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_PRELOCK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_PRELOCK_CONF to value 0"] +impl crate::Resettable for L2_CACHE_PRELOCK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_prelock_sct0_addr.rs b/esp32p4/src/cache/l2_cache_prelock_sct0_addr.rs new file mode 100644 index 0000000000..f637828627 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_prelock_sct0_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_PRELOCK_SCT0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_PRELOCK_SCT0_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_PRELOCK_SCT0_ADDR` reader - Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG"] +pub type L2_CACHE_PRELOCK_SCT0_ADDR_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_PRELOCK_SCT0_ADDR` writer - Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG"] +pub type L2_CACHE_PRELOCK_SCT0_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG"] + #[inline(always)] + pub fn l2_cache_prelock_sct0_addr(&self) -> L2_CACHE_PRELOCK_SCT0_ADDR_R { + L2_CACHE_PRELOCK_SCT0_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_PRELOCK_SCT0_ADDR") + .field( + "l2_cache_prelock_sct0_addr", + &format_args!("{}", self.l2_cache_prelock_sct0_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l2_cache_prelock_sct0_addr( + &mut self, + ) -> L2_CACHE_PRELOCK_SCT0_ADDR_W { + L2_CACHE_PRELOCK_SCT0_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct0_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_sct0_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_PRELOCK_SCT0_ADDR_SPEC; +impl crate::RegisterSpec for L2_CACHE_PRELOCK_SCT0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_prelock_sct0_addr::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_PRELOCK_SCT0_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_prelock_sct0_addr::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_PRELOCK_SCT0_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_PRELOCK_SCT0_ADDR to value 0"] +impl crate::Resettable for L2_CACHE_PRELOCK_SCT0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_prelock_sct1_addr.rs b/esp32p4/src/cache/l2_cache_prelock_sct1_addr.rs new file mode 100644 index 0000000000..b46e6a29d2 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_prelock_sct1_addr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_CACHE_PRELOCK_SCT1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_PRELOCK_SCT1_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_PRELOCK_SCT1_ADDR` reader - Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG"] +pub type L2_CACHE_PRELOCK_SCT1_ADDR_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_PRELOCK_SCT1_ADDR` writer - Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG"] +pub type L2_CACHE_PRELOCK_SCT1_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG"] + #[inline(always)] + pub fn l2_cache_prelock_sct1_addr(&self) -> L2_CACHE_PRELOCK_SCT1_ADDR_R { + L2_CACHE_PRELOCK_SCT1_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_PRELOCK_SCT1_ADDR") + .field( + "l2_cache_prelock_sct1_addr", + &format_args!("{}", self.l2_cache_prelock_sct1_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn l2_cache_prelock_sct1_addr( + &mut self, + ) -> L2_CACHE_PRELOCK_SCT1_ADDR_W { + L2_CACHE_PRELOCK_SCT1_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct1_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_sct1_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_PRELOCK_SCT1_ADDR_SPEC; +impl crate::RegisterSpec for L2_CACHE_PRELOCK_SCT1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_prelock_sct1_addr::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_PRELOCK_SCT1_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_prelock_sct1_addr::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_PRELOCK_SCT1_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_PRELOCK_SCT1_ADDR to value 0"] +impl crate::Resettable for L2_CACHE_PRELOCK_SCT1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_prelock_sct_size.rs b/esp32p4/src/cache/l2_cache_prelock_sct_size.rs new file mode 100644 index 0000000000..b89dfb1d60 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_prelock_sct_size.rs @@ -0,0 +1,89 @@ +#[doc = "Register `L2_CACHE_PRELOCK_SCT_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_PRELOCK_SCT_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_PRELOCK_SCT0_SIZE` reader - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG"] +pub type L2_CACHE_PRELOCK_SCT0_SIZE_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_PRELOCK_SCT0_SIZE` writer - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG"] +pub type L2_CACHE_PRELOCK_SCT0_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `L2_CACHE_PRELOCK_SCT1_SIZE` reader - Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG"] +pub type L2_CACHE_PRELOCK_SCT1_SIZE_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_PRELOCK_SCT1_SIZE` writer - Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG"] +pub type L2_CACHE_PRELOCK_SCT1_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG"] + #[inline(always)] + pub fn l2_cache_prelock_sct0_size(&self) -> L2_CACHE_PRELOCK_SCT0_SIZE_R { + L2_CACHE_PRELOCK_SCT0_SIZE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG"] + #[inline(always)] + pub fn l2_cache_prelock_sct1_size(&self) -> L2_CACHE_PRELOCK_SCT1_SIZE_R { + L2_CACHE_PRELOCK_SCT1_SIZE_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_PRELOCK_SCT_SIZE") + .field( + "l2_cache_prelock_sct0_size", + &format_args!("{}", self.l2_cache_prelock_sct0_size().bits()), + ) + .field( + "l2_cache_prelock_sct1_size", + &format_args!("{}", self.l2_cache_prelock_sct1_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l2_cache_prelock_sct0_size( + &mut self, + ) -> L2_CACHE_PRELOCK_SCT0_SIZE_W { + L2_CACHE_PRELOCK_SCT0_SIZE_W::new(self, 0) + } + #[doc = "Bits 16:31 - Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn l2_cache_prelock_sct1_size( + &mut self, + ) -> L2_CACHE_PRELOCK_SCT1_SIZE_W { + L2_CACHE_PRELOCK_SCT1_SIZE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L2 Cache prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_prelock_sct_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_PRELOCK_SCT_SIZE_SPEC; +impl crate::RegisterSpec for L2_CACHE_PRELOCK_SCT_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_prelock_sct_size::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_PRELOCK_SCT_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_prelock_sct_size::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_PRELOCK_SCT_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_PRELOCK_SCT_SIZE to value 0xffff_ffff"] +impl crate::Resettable for L2_CACHE_PRELOCK_SCT_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/cache/l2_cache_sync_preload_exception.rs b/esp32p4/src/cache/l2_cache_sync_preload_exception.rs new file mode 100644 index 0000000000..ab4a05fcc1 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_sync_preload_exception.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_CACHE_SYNC_PRELOAD_EXCEPTION` reader"] +pub type R = crate::R; +#[doc = "Field `L2_CACHE_PLD_ERR_CODE` reader - The value 2 is Only available which means preload size is error in L2-Cache."] +pub type L2_CACHE_PLD_ERR_CODE_R = crate::FieldReader; +impl R { + #[doc = "Bits 10:11 - The value 2 is Only available which means preload size is error in L2-Cache."] + #[inline(always)] + pub fn l2_cache_pld_err_code(&self) -> L2_CACHE_PLD_ERR_CODE_R { + L2_CACHE_PLD_ERR_CODE_R::new(((self.bits >> 10) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_SYNC_PRELOAD_EXCEPTION") + .field( + "l2_cache_pld_err_code", + &format_args!("{}", self.l2_cache_pld_err_code().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Cache Sync/Preload Operation exception register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_exception::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC; +impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_sync_preload_exception::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC {} +#[doc = "`reset()` method sets L2_CACHE_SYNC_PRELOAD_EXCEPTION to value 0"] +impl crate::Resettable for L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_sync_preload_int_clr.rs b/esp32p4/src/cache/l2_cache_sync_preload_int_clr.rs new file mode 100644 index 0000000000..710e2c453d --- /dev/null +++ b/esp32p4/src/cache/l2_cache_sync_preload_int_clr.rs @@ -0,0 +1,54 @@ +#[doc = "Register `L2_CACHE_SYNC_PRELOAD_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_PLD_DONE_INT_CLR` writer - The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done."] +pub type L2_CACHE_PLD_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_PLD_ERR_INT_CLR` writer - The bit is used to clear interrupt of L2-Cache preload-operation error."] +pub type L2_CACHE_PLD_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 5 - The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done."] + #[inline(always)] + #[must_use] + pub fn l2_cache_pld_done_int_clr( + &mut self, + ) -> L2_CACHE_PLD_DONE_INT_CLR_W { + L2_CACHE_PLD_DONE_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 12 - The bit is used to clear interrupt of L2-Cache preload-operation error."] + #[inline(always)] + #[must_use] + pub fn l2_cache_pld_err_int_clr( + &mut self, + ) -> L2_CACHE_PLD_ERR_INT_CLR_W { + L2_CACHE_PLD_ERR_INT_CLR_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Sync Preload operation Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_preload_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_SYNC_PRELOAD_INT_CLR_SPEC; +impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`l2_cache_sync_preload_int_clr::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_SYNC_PRELOAD_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_SYNC_PRELOAD_INT_CLR to value 0"] +impl crate::Resettable for L2_CACHE_SYNC_PRELOAD_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_sync_preload_int_ena.rs b/esp32p4/src/cache/l2_cache_sync_preload_int_ena.rs new file mode 100644 index 0000000000..7d74f93d49 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_sync_preload_int_ena.rs @@ -0,0 +1,89 @@ +#[doc = "Register `L2_CACHE_SYNC_PRELOAD_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_SYNC_PRELOAD_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_PLD_DONE_INT_ENA` reader - The bit is used to enable interrupt of L2-Cache preload-operation done."] +pub type L2_CACHE_PLD_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_PLD_DONE_INT_ENA` writer - The bit is used to enable interrupt of L2-Cache preload-operation done."] +pub type L2_CACHE_PLD_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_PLD_ERR_INT_ENA` reader - The bit is used to enable interrupt of L2-Cache preload-operation error."] +pub type L2_CACHE_PLD_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `L2_CACHE_PLD_ERR_INT_ENA` writer - The bit is used to enable interrupt of L2-Cache preload-operation error."] +pub type L2_CACHE_PLD_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - The bit is used to enable interrupt of L2-Cache preload-operation done."] + #[inline(always)] + pub fn l2_cache_pld_done_int_ena(&self) -> L2_CACHE_PLD_DONE_INT_ENA_R { + L2_CACHE_PLD_DONE_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 12 - The bit is used to enable interrupt of L2-Cache preload-operation error."] + #[inline(always)] + pub fn l2_cache_pld_err_int_ena(&self) -> L2_CACHE_PLD_ERR_INT_ENA_R { + L2_CACHE_PLD_ERR_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_ENA") + .field( + "l2_cache_pld_done_int_ena", + &format_args!("{}", self.l2_cache_pld_done_int_ena().bit()), + ) + .field( + "l2_cache_pld_err_int_ena", + &format_args!("{}", self.l2_cache_pld_err_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - The bit is used to enable interrupt of L2-Cache preload-operation done."] + #[inline(always)] + #[must_use] + pub fn l2_cache_pld_done_int_ena( + &mut self, + ) -> L2_CACHE_PLD_DONE_INT_ENA_W { + L2_CACHE_PLD_DONE_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 12 - The bit is used to enable interrupt of L2-Cache preload-operation error."] + #[inline(always)] + #[must_use] + pub fn l2_cache_pld_err_int_ena( + &mut self, + ) -> L2_CACHE_PLD_ERR_INT_ENA_W { + L2_CACHE_PLD_ERR_INT_ENA_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1-Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_preload_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC; +impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_sync_preload_int_ena::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_sync_preload_int_ena::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_SYNC_PRELOAD_INT_ENA to value 0"] +impl crate::Resettable for L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_sync_preload_int_raw.rs b/esp32p4/src/cache/l2_cache_sync_preload_int_raw.rs new file mode 100644 index 0000000000..6d5a95c548 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_sync_preload_int_raw.rs @@ -0,0 +1,89 @@ +#[doc = "Register `L2_CACHE_SYNC_PRELOAD_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_SYNC_PRELOAD_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_PLD_DONE_INT_RAW` reader - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done."] +pub type L2_CACHE_PLD_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `L2_CACHE_PLD_DONE_INT_RAW` writer - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done."] +pub type L2_CACHE_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_PLD_ERR_INT_RAW` reader - The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs."] +pub type L2_CACHE_PLD_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `L2_CACHE_PLD_ERR_INT_RAW` writer - The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs."] +pub type L2_CACHE_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done."] + #[inline(always)] + pub fn l2_cache_pld_done_int_raw(&self) -> L2_CACHE_PLD_DONE_INT_RAW_R { + L2_CACHE_PLD_DONE_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 12 - The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs."] + #[inline(always)] + pub fn l2_cache_pld_err_int_raw(&self) -> L2_CACHE_PLD_ERR_INT_RAW_R { + L2_CACHE_PLD_ERR_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_RAW") + .field( + "l2_cache_pld_done_int_raw", + &format_args!("{}", self.l2_cache_pld_done_int_raw().bit()), + ) + .field( + "l2_cache_pld_err_int_raw", + &format_args!("{}", self.l2_cache_pld_err_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done."] + #[inline(always)] + #[must_use] + pub fn l2_cache_pld_done_int_raw( + &mut self, + ) -> L2_CACHE_PLD_DONE_INT_RAW_W { + L2_CACHE_PLD_DONE_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 12 - The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs."] + #[inline(always)] + #[must_use] + pub fn l2_cache_pld_err_int_raw( + &mut self, + ) -> L2_CACHE_PLD_ERR_INT_RAW_W { + L2_CACHE_PLD_ERR_INT_RAW_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Sync Preload operation Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_preload_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC; +impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_sync_preload_int_raw::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_sync_preload_int_raw::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_SYNC_PRELOAD_INT_RAW to value 0"] +impl crate::Resettable for L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_sync_preload_int_st.rs b/esp32p4/src/cache/l2_cache_sync_preload_int_st.rs new file mode 100644 index 0000000000..212043fd26 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_sync_preload_int_st.rs @@ -0,0 +1,50 @@ +#[doc = "Register `L2_CACHE_SYNC_PRELOAD_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `L2_CACHE_PLD_DONE_INT_ST` reader - The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done."] +pub type L2_CACHE_PLD_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `L2_CACHE_PLD_ERR_INT_ST` reader - The bit indicates the status of the interrupt of L2-Cache preload-operation error."] +pub type L2_CACHE_PLD_ERR_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 5 - The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done."] + #[inline(always)] + pub fn l2_cache_pld_done_int_st(&self) -> L2_CACHE_PLD_DONE_INT_ST_R { + L2_CACHE_PLD_DONE_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 12 - The bit indicates the status of the interrupt of L2-Cache preload-operation error."] + #[inline(always)] + pub fn l2_cache_pld_err_int_st(&self) -> L2_CACHE_PLD_ERR_INT_ST_R { + L2_CACHE_PLD_ERR_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_ST") + .field( + "l2_cache_pld_done_int_st", + &format_args!("{}", self.l2_cache_pld_done_int_st().bit()), + ) + .field( + "l2_cache_pld_err_int_st", + &format_args!("{}", self.l2_cache_pld_err_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC; +impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_sync_preload_int_st::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC {} +#[doc = "`reset()` method sets L2_CACHE_SYNC_PRELOAD_INT_ST to value 0"] +impl crate::Resettable for L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_sync_rst_ctrl.rs b/esp32p4/src/cache/l2_cache_sync_rst_ctrl.rs new file mode 100644 index 0000000000..86997b2c00 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_sync_rst_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L2_CACHE_SYNC_RST_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_SYNC_RST_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_SYNC_RST` reader - set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] +pub type L2_CACHE_SYNC_RST_R = crate::BitReader; +#[doc = "Field `L2_CACHE_SYNC_RST` writer - set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] +pub type L2_CACHE_SYNC_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] + #[inline(always)] + pub fn l2_cache_sync_rst(&self) -> L2_CACHE_SYNC_RST_R { + L2_CACHE_SYNC_RST_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_SYNC_RST_CTRL") + .field( + "l2_cache_sync_rst", + &format_args!("{}", self.l2_cache_sync_rst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."] + #[inline(always)] + #[must_use] + pub fn l2_cache_sync_rst(&mut self) -> L2_CACHE_SYNC_RST_W { + L2_CACHE_SYNC_RST_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Sync Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_rst_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_sync_rst_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_SYNC_RST_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_SYNC_RST_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_sync_rst_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_SYNC_RST_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_sync_rst_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_SYNC_RST_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_SYNC_RST_CTRL to value 0"] +impl crate::Resettable for L2_CACHE_SYNC_RST_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_tag_mem_acs_conf.rs b/esp32p4/src/cache/l2_cache_tag_mem_acs_conf.rs new file mode 100644 index 0000000000..b9035a9922 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_tag_mem_acs_conf.rs @@ -0,0 +1,89 @@ +#[doc = "Register `L2_CACHE_TAG_MEM_ACS_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_TAG_MEM_ACS_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_TAG_MEM_RD_EN` reader - The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable."] +pub type L2_CACHE_TAG_MEM_RD_EN_R = crate::BitReader; +#[doc = "Field `L2_CACHE_TAG_MEM_RD_EN` writer - The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable."] +pub type L2_CACHE_TAG_MEM_RD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_TAG_MEM_WR_EN` reader - The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable."] +pub type L2_CACHE_TAG_MEM_WR_EN_R = crate::BitReader; +#[doc = "Field `L2_CACHE_TAG_MEM_WR_EN` writer - The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable."] +pub type L2_CACHE_TAG_MEM_WR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 20 - The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l2_cache_tag_mem_rd_en(&self) -> L2_CACHE_TAG_MEM_RD_EN_R { + L2_CACHE_TAG_MEM_RD_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + pub fn l2_cache_tag_mem_wr_en(&self) -> L2_CACHE_TAG_MEM_WR_EN_R { + L2_CACHE_TAG_MEM_WR_EN_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_TAG_MEM_ACS_CONF") + .field( + "l2_cache_tag_mem_rd_en", + &format_args!("{}", self.l2_cache_tag_mem_rd_en().bit()), + ) + .field( + "l2_cache_tag_mem_wr_en", + &format_args!("{}", self.l2_cache_tag_mem_wr_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l2_cache_tag_mem_rd_en( + &mut self, + ) -> L2_CACHE_TAG_MEM_RD_EN_W { + L2_CACHE_TAG_MEM_RD_EN_W::new(self, 20) + } + #[doc = "Bit 21 - The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable."] + #[inline(always)] + #[must_use] + pub fn l2_cache_tag_mem_wr_en( + &mut self, + ) -> L2_CACHE_TAG_MEM_WR_EN_W { + L2_CACHE_TAG_MEM_WR_EN_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache tag memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_tag_mem_acs_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_tag_mem_acs_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_TAG_MEM_ACS_CONF_SPEC; +impl crate::RegisterSpec for L2_CACHE_TAG_MEM_ACS_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_tag_mem_acs_conf::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_TAG_MEM_ACS_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_tag_mem_acs_conf::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_TAG_MEM_ACS_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_TAG_MEM_ACS_CONF to value 0x0030_0000"] +impl crate::Resettable for L2_CACHE_TAG_MEM_ACS_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0030_0000; +} diff --git a/esp32p4/src/cache/l2_cache_tag_mem_power_ctrl.rs b/esp32p4/src/cache/l2_cache_tag_mem_power_ctrl.rs new file mode 100644 index 0000000000..a762ec9768 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_tag_mem_power_ctrl.rs @@ -0,0 +1,110 @@ +#[doc = "Register `L2_CACHE_TAG_MEM_POWER_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_TAG_MEM_POWER_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_TAG_MEM_FORCE_ON` reader - The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating."] +pub type L2_CACHE_TAG_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `L2_CACHE_TAG_MEM_FORCE_ON` writer - The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating."] +pub type L2_CACHE_TAG_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_TAG_MEM_FORCE_PD` reader - The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down"] +pub type L2_CACHE_TAG_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `L2_CACHE_TAG_MEM_FORCE_PD` writer - The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down"] +pub type L2_CACHE_TAG_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L2_CACHE_TAG_MEM_FORCE_PU` reader - The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up"] +pub type L2_CACHE_TAG_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `L2_CACHE_TAG_MEM_FORCE_PU` writer - The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up"] +pub type L2_CACHE_TAG_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 20 - The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + pub fn l2_cache_tag_mem_force_on(&self) -> L2_CACHE_TAG_MEM_FORCE_ON_R { + L2_CACHE_TAG_MEM_FORCE_ON_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + pub fn l2_cache_tag_mem_force_pd(&self) -> L2_CACHE_TAG_MEM_FORCE_PD_R { + L2_CACHE_TAG_MEM_FORCE_PD_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + pub fn l2_cache_tag_mem_force_pu(&self) -> L2_CACHE_TAG_MEM_FORCE_PU_R { + L2_CACHE_TAG_MEM_FORCE_PU_R::new(((self.bits >> 22) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_TAG_MEM_POWER_CTRL") + .field( + "l2_cache_tag_mem_force_on", + &format_args!("{}", self.l2_cache_tag_mem_force_on().bit()), + ) + .field( + "l2_cache_tag_mem_force_pd", + &format_args!("{}", self.l2_cache_tag_mem_force_pd().bit()), + ) + .field( + "l2_cache_tag_mem_force_pu", + &format_args!("{}", self.l2_cache_tag_mem_force_pu().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating."] + #[inline(always)] + #[must_use] + pub fn l2_cache_tag_mem_force_on( + &mut self, + ) -> L2_CACHE_TAG_MEM_FORCE_ON_W { + L2_CACHE_TAG_MEM_FORCE_ON_W::new(self, 20) + } + #[doc = "Bit 21 - The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down"] + #[inline(always)] + #[must_use] + pub fn l2_cache_tag_mem_force_pd( + &mut self, + ) -> L2_CACHE_TAG_MEM_FORCE_PD_W { + L2_CACHE_TAG_MEM_FORCE_PD_W::new(self, 21) + } + #[doc = "Bit 22 - The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up"] + #[inline(always)] + #[must_use] + pub fn l2_cache_tag_mem_force_pu( + &mut self, + ) -> L2_CACHE_TAG_MEM_FORCE_PU_W { + L2_CACHE_TAG_MEM_FORCE_PU_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache tag memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_tag_mem_power_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_tag_mem_power_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_TAG_MEM_POWER_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_TAG_MEM_POWER_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_tag_mem_power_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_TAG_MEM_POWER_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_tag_mem_power_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_TAG_MEM_POWER_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_TAG_MEM_POWER_CTRL to value 0x0050_0000"] +impl crate::Resettable for L2_CACHE_TAG_MEM_POWER_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0050_0000; +} diff --git a/esp32p4/src/cache/l2_cache_vaddr.rs b/esp32p4/src/cache/l2_cache_vaddr.rs new file mode 100644 index 0000000000..e688bb2c81 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_vaddr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L2_CACHE_VADDR` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_VADDR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_VADDR` reader - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."] +pub type L2_CACHE_VADDR_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_VADDR` writer - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."] +pub type L2_CACHE_VADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."] + #[inline(always)] + pub fn l2_cache_vaddr(&self) -> L2_CACHE_VADDR_R { + L2_CACHE_VADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_VADDR") + .field( + "l2_cache_vaddr", + &format_args!("{}", self.l2_cache_vaddr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."] + #[inline(always)] + #[must_use] + pub fn l2_cache_vaddr(&mut self) -> L2_CACHE_VADDR_W { + L2_CACHE_VADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Vaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_vaddr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_vaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_VADDR_SPEC; +impl crate::RegisterSpec for L2_CACHE_VADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_vaddr::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_VADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_vaddr::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_VADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_VADDR to value 0x4000_0000"] +impl crate::Resettable for L2_CACHE_VADDR_SPEC { + const RESET_VALUE: Self::Ux = 0x4000_0000; +} diff --git a/esp32p4/src/cache/l2_cache_way_object.rs b/esp32p4/src/cache/l2_cache_way_object.rs new file mode 100644 index 0000000000..d2b6d9f802 --- /dev/null +++ b/esp32p4/src/cache/l2_cache_way_object.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L2_CACHE_WAY_OBJECT` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_WAY_OBJECT` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_WAY_OBJECT` reader - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."] +pub type L2_CACHE_WAY_OBJECT_R = crate::FieldReader; +#[doc = "Field `L2_CACHE_WAY_OBJECT` writer - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."] +pub type L2_CACHE_WAY_OBJECT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."] + #[inline(always)] + pub fn l2_cache_way_object(&self) -> L2_CACHE_WAY_OBJECT_R { + L2_CACHE_WAY_OBJECT_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_WAY_OBJECT") + .field( + "l2_cache_way_object", + &format_args!("{}", self.l2_cache_way_object().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."] + #[inline(always)] + #[must_use] + pub fn l2_cache_way_object(&mut self) -> L2_CACHE_WAY_OBJECT_W { + L2_CACHE_WAY_OBJECT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache Tag and Data memory way register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_way_object::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_way_object::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_WAY_OBJECT_SPEC; +impl crate::RegisterSpec for L2_CACHE_WAY_OBJECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_way_object::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_WAY_OBJECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_way_object::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_WAY_OBJECT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_WAY_OBJECT to value 0"] +impl crate::Resettable for L2_CACHE_WAY_OBJECT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_cache_wrap_around_ctrl.rs b/esp32p4/src/cache/l2_cache_wrap_around_ctrl.rs new file mode 100644 index 0000000000..1f192ff51e --- /dev/null +++ b/esp32p4/src/cache/l2_cache_wrap_around_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `L2_CACHE_WRAP_AROUND_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `L2_CACHE_WRAP_AROUND_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_WRAP` reader - Set this bit as 1 to enable L2-Cache wrap around mode."] +pub type L2_CACHE_WRAP_R = crate::BitReader; +#[doc = "Field `L2_CACHE_WRAP` writer - Set this bit as 1 to enable L2-Cache wrap around mode."] +pub type L2_CACHE_WRAP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - Set this bit as 1 to enable L2-Cache wrap around mode."] + #[inline(always)] + pub fn l2_cache_wrap(&self) -> L2_CACHE_WRAP_R { + L2_CACHE_WRAP_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_CACHE_WRAP_AROUND_CTRL") + .field( + "l2_cache_wrap", + &format_args!("{}", self.l2_cache_wrap().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - Set this bit as 1 to enable L2-Cache wrap around mode."] + #[inline(always)] + #[must_use] + pub fn l2_cache_wrap(&mut self) -> L2_CACHE_WRAP_W { + L2_CACHE_WRAP_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache wrap around control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_wrap_around_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_cache_wrap_around_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_CACHE_WRAP_AROUND_CTRL_SPEC; +impl crate::RegisterSpec for L2_CACHE_WRAP_AROUND_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_cache_wrap_around_ctrl::R`](R) reader structure"] +impl crate::Readable for L2_CACHE_WRAP_AROUND_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_cache_wrap_around_ctrl::W`](W) writer structure"] +impl crate::Writable for L2_CACHE_WRAP_AROUND_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_CACHE_WRAP_AROUND_CTRL to value 0"] +impl crate::Resettable for L2_CACHE_WRAP_AROUND_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus0_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_dbus0_acs_conflict_cnt.rs new file mode 100644 index 0000000000..77fa92ae17 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus0_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS0_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS0_CONFLICT_CNT` reader - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache."] +pub type L2_DBUS0_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus0_conflict_cnt(&self) -> L2_DBUS0_CONFLICT_CNT_R { + L2_DBUS0_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS0_ACS_CONFLICT_CNT") + .field( + "l2_dbus0_conflict_cnt", + &format_args!("{}", self.l2_dbus0_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS0_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS0_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus0_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS0_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS0_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L2_DBUS0_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus0_acs_hit_cnt.rs b/esp32p4/src/cache/l2_dbus0_acs_hit_cnt.rs new file mode 100644 index 0000000000..89e4d55e1b --- /dev/null +++ b/esp32p4/src/cache/l2_dbus0_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS0_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS0_HIT_CNT` reader - The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache."] +pub type L2_DBUS0_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus0_hit_cnt(&self) -> L2_DBUS0_HIT_CNT_R { + L2_DBUS0_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS0_ACS_HIT_CNT") + .field( + "l2_dbus0_hit_cnt", + &format_args!("{}", self.l2_dbus0_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS0_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS0_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus0_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS0_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS0_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L2_DBUS0_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus0_acs_miss_cnt.rs b/esp32p4/src/cache/l2_dbus0_acs_miss_cnt.rs new file mode 100644 index 0000000000..2e04a6889d --- /dev/null +++ b/esp32p4/src/cache/l2_dbus0_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS0_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS0_MISS_CNT` reader - The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache."] +pub type L2_DBUS0_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus0_miss_cnt(&self) -> L2_DBUS0_MISS_CNT_R { + L2_DBUS0_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS0_ACS_MISS_CNT") + .field( + "l2_dbus0_miss_cnt", + &format_args!("{}", self.l2_dbus0_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS0_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS0_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus0_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS0_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS0_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L2_DBUS0_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..c508e71d0f --- /dev/null +++ b/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS0_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS0_NXTLVL_RD_CNT` reader - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache."] +pub type L2_DBUS0_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus0_nxtlvl_rd_cnt(&self) -> L2_DBUS0_NXTLVL_RD_CNT_R { + L2_DBUS0_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS0_ACS_NXTLVL_RD_CNT") + .field( + "l2_dbus0_nxtlvl_rd_cnt", + &format_args!("{}", self.l2_dbus0_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS0_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS0_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus0_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS0_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS0_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L2_DBUS0_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_wr_cnt.rs new file mode 100644 index 0000000000..b3d6010f93 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_wr_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS0_ACS_NXTLVL_WR_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS0_NXTLVL_WR_CNT` reader - The register records the number of write back when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache."] +pub type L2_DBUS0_NXTLVL_WR_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of write back when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus0_nxtlvl_wr_cnt(&self) -> L2_DBUS0_NXTLVL_WR_CNT_R { + L2_DBUS0_NXTLVL_WR_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS0_ACS_NXTLVL_WR_CNT") + .field( + "l2_dbus0_nxtlvl_wr_cnt", + &format_args!("{}", self.l2_dbus0_nxtlvl_wr_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus0 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_nxtlvl_wr_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS0_ACS_NXTLVL_WR_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS0_ACS_NXTLVL_WR_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus0_acs_nxtlvl_wr_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS0_ACS_NXTLVL_WR_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS0_ACS_NXTLVL_WR_CNT to value 0"] +impl crate::Resettable for L2_DBUS0_ACS_NXTLVL_WR_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus1_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_dbus1_acs_conflict_cnt.rs new file mode 100644 index 0000000000..139db0fd7a --- /dev/null +++ b/esp32p4/src/cache/l2_dbus1_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS1_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS1_CONFLICT_CNT` reader - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache."] +pub type L2_DBUS1_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus1_conflict_cnt(&self) -> L2_DBUS1_CONFLICT_CNT_R { + L2_DBUS1_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS1_ACS_CONFLICT_CNT") + .field( + "l2_dbus1_conflict_cnt", + &format_args!("{}", self.l2_dbus1_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS1_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS1_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus1_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS1_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS1_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L2_DBUS1_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus1_acs_hit_cnt.rs b/esp32p4/src/cache/l2_dbus1_acs_hit_cnt.rs new file mode 100644 index 0000000000..28281daf77 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus1_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS1_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS1_HIT_CNT` reader - The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache."] +pub type L2_DBUS1_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus1_hit_cnt(&self) -> L2_DBUS1_HIT_CNT_R { + L2_DBUS1_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS1_ACS_HIT_CNT") + .field( + "l2_dbus1_hit_cnt", + &format_args!("{}", self.l2_dbus1_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS1_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS1_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus1_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS1_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS1_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L2_DBUS1_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus1_acs_miss_cnt.rs b/esp32p4/src/cache/l2_dbus1_acs_miss_cnt.rs new file mode 100644 index 0000000000..fc3f49f762 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus1_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS1_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS1_MISS_CNT` reader - The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache."] +pub type L2_DBUS1_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus1_miss_cnt(&self) -> L2_DBUS1_MISS_CNT_R { + L2_DBUS1_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS1_ACS_MISS_CNT") + .field( + "l2_dbus1_miss_cnt", + &format_args!("{}", self.l2_dbus1_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS1_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS1_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus1_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS1_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS1_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L2_DBUS1_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..090706cda1 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS1_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS1_NXTLVL_RD_CNT` reader - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache."] +pub type L2_DBUS1_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus1_nxtlvl_rd_cnt(&self) -> L2_DBUS1_NXTLVL_RD_CNT_R { + L2_DBUS1_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS1_ACS_NXTLVL_RD_CNT") + .field( + "l2_dbus1_nxtlvl_rd_cnt", + &format_args!("{}", self.l2_dbus1_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS1_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS1_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus1_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS1_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS1_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L2_DBUS1_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_wr_cnt.rs new file mode 100644 index 0000000000..8a3e6e42e9 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_wr_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS1_ACS_NXTLVL_WR_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS1_NXTLVL_WR_CNT` reader - The register records the number of write back when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache."] +pub type L2_DBUS1_NXTLVL_WR_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of write back when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus1_nxtlvl_wr_cnt(&self) -> L2_DBUS1_NXTLVL_WR_CNT_R { + L2_DBUS1_NXTLVL_WR_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS1_ACS_NXTLVL_WR_CNT") + .field( + "l2_dbus1_nxtlvl_wr_cnt", + &format_args!("{}", self.l2_dbus1_nxtlvl_wr_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus1 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_nxtlvl_wr_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS1_ACS_NXTLVL_WR_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS1_ACS_NXTLVL_WR_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus1_acs_nxtlvl_wr_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS1_ACS_NXTLVL_WR_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS1_ACS_NXTLVL_WR_CNT to value 0"] +impl crate::Resettable for L2_DBUS1_ACS_NXTLVL_WR_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus2_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_dbus2_acs_conflict_cnt.rs new file mode 100644 index 0000000000..5dd27ea3fa --- /dev/null +++ b/esp32p4/src/cache/l2_dbus2_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS2_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS2_CONFLICT_CNT` reader - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."] +pub type L2_DBUS2_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus2_conflict_cnt(&self) -> L2_DBUS2_CONFLICT_CNT_R { + L2_DBUS2_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS2_ACS_CONFLICT_CNT") + .field( + "l2_dbus2_conflict_cnt", + &format_args!("{}", self.l2_dbus2_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS2_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS2_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus2_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS2_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS2_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L2_DBUS2_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus2_acs_hit_cnt.rs b/esp32p4/src/cache/l2_dbus2_acs_hit_cnt.rs new file mode 100644 index 0000000000..b099ef58ad --- /dev/null +++ b/esp32p4/src/cache/l2_dbus2_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS2_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS2_HIT_CNT` reader - The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."] +pub type L2_DBUS2_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus2_hit_cnt(&self) -> L2_DBUS2_HIT_CNT_R { + L2_DBUS2_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS2_ACS_HIT_CNT") + .field( + "l2_dbus2_hit_cnt", + &format_args!("{}", self.l2_dbus2_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS2_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS2_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus2_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS2_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS2_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L2_DBUS2_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus2_acs_miss_cnt.rs b/esp32p4/src/cache/l2_dbus2_acs_miss_cnt.rs new file mode 100644 index 0000000000..a2b6a473f3 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus2_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS2_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS2_MISS_CNT` reader - The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."] +pub type L2_DBUS2_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus2_miss_cnt(&self) -> L2_DBUS2_MISS_CNT_R { + L2_DBUS2_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS2_ACS_MISS_CNT") + .field( + "l2_dbus2_miss_cnt", + &format_args!("{}", self.l2_dbus2_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS2_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS2_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus2_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS2_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS2_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L2_DBUS2_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..a754083102 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS2_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS2_NXTLVL_RD_CNT` reader - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache."] +pub type L2_DBUS2_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus2_nxtlvl_rd_cnt(&self) -> L2_DBUS2_NXTLVL_RD_CNT_R { + L2_DBUS2_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS2_ACS_NXTLVL_RD_CNT") + .field( + "l2_dbus2_nxtlvl_rd_cnt", + &format_args!("{}", self.l2_dbus2_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS2_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS2_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus2_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS2_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS2_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L2_DBUS2_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_wr_cnt.rs new file mode 100644 index 0000000000..f4155c6f74 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_wr_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS2_ACS_NXTLVL_WR_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS2_NXTLVL_WR_CNT` reader - The register records the number of write back when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."] +pub type L2_DBUS2_NXTLVL_WR_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of write back when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus2_nxtlvl_wr_cnt(&self) -> L2_DBUS2_NXTLVL_WR_CNT_R { + L2_DBUS2_NXTLVL_WR_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS2_ACS_NXTLVL_WR_CNT") + .field( + "l2_dbus2_nxtlvl_wr_cnt", + &format_args!("{}", self.l2_dbus2_nxtlvl_wr_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus2 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_nxtlvl_wr_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS2_ACS_NXTLVL_WR_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS2_ACS_NXTLVL_WR_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus2_acs_nxtlvl_wr_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS2_ACS_NXTLVL_WR_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS2_ACS_NXTLVL_WR_CNT to value 0"] +impl crate::Resettable for L2_DBUS2_ACS_NXTLVL_WR_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus3_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_dbus3_acs_conflict_cnt.rs new file mode 100644 index 0000000000..33b1e35b0e --- /dev/null +++ b/esp32p4/src/cache/l2_dbus3_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS3_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS3_CONFLICT_CNT` reader - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache."] +pub type L2_DBUS3_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus3_conflict_cnt(&self) -> L2_DBUS3_CONFLICT_CNT_R { + L2_DBUS3_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS3_ACS_CONFLICT_CNT") + .field( + "l2_dbus3_conflict_cnt", + &format_args!("{}", self.l2_dbus3_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS3_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS3_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus3_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS3_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS3_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L2_DBUS3_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus3_acs_hit_cnt.rs b/esp32p4/src/cache/l2_dbus3_acs_hit_cnt.rs new file mode 100644 index 0000000000..a79ad20cd9 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus3_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS3_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS3_HIT_CNT` reader - The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache."] +pub type L2_DBUS3_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus3_hit_cnt(&self) -> L2_DBUS3_HIT_CNT_R { + L2_DBUS3_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS3_ACS_HIT_CNT") + .field( + "l2_dbus3_hit_cnt", + &format_args!("{}", self.l2_dbus3_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS3_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS3_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus3_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS3_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS3_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L2_DBUS3_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus3_acs_miss_cnt.rs b/esp32p4/src/cache/l2_dbus3_acs_miss_cnt.rs new file mode 100644 index 0000000000..6359191223 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus3_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS3_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS3_MISS_CNT` reader - The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache."] +pub type L2_DBUS3_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus3_miss_cnt(&self) -> L2_DBUS3_MISS_CNT_R { + L2_DBUS3_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS3_ACS_MISS_CNT") + .field( + "l2_dbus3_miss_cnt", + &format_args!("{}", self.l2_dbus3_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS3_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS3_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus3_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS3_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS3_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L2_DBUS3_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..13d6c67e94 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS3_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS3_NXTLVL_RD_CNT` reader - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache."] +pub type L2_DBUS3_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus3_nxtlvl_rd_cnt(&self) -> L2_DBUS3_NXTLVL_RD_CNT_R { + L2_DBUS3_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS3_ACS_NXTLVL_RD_CNT") + .field( + "l2_dbus3_nxtlvl_rd_cnt", + &format_args!("{}", self.l2_dbus3_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS3_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS3_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus3_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS3_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS3_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L2_DBUS3_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_wr_cnt.rs new file mode 100644 index 0000000000..f415c33714 --- /dev/null +++ b/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_wr_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_DBUS3_ACS_NXTLVL_WR_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_DBUS3_NXTLVL_WR_CNT` reader - The register records the number of write back when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache."] +pub type L2_DBUS3_NXTLVL_WR_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of write back when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache."] + #[inline(always)] + pub fn l2_dbus3_nxtlvl_wr_cnt(&self) -> L2_DBUS3_NXTLVL_WR_CNT_R { + L2_DBUS3_NXTLVL_WR_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_DBUS3_ACS_NXTLVL_WR_CNT") + .field( + "l2_dbus3_nxtlvl_wr_cnt", + &format_args!("{}", self.l2_dbus3_nxtlvl_wr_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus3 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_nxtlvl_wr_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_DBUS3_ACS_NXTLVL_WR_CNT_SPEC; +impl crate::RegisterSpec for L2_DBUS3_ACS_NXTLVL_WR_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_dbus3_acs_nxtlvl_wr_cnt::R`](R) reader structure"] +impl crate::Readable for L2_DBUS3_ACS_NXTLVL_WR_CNT_SPEC {} +#[doc = "`reset()` method sets L2_DBUS3_ACS_NXTLVL_WR_CNT to value 0"] +impl crate::Resettable for L2_DBUS3_ACS_NXTLVL_WR_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus0_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_ibus0_acs_conflict_cnt.rs new file mode 100644 index 0000000000..b99e0d64ae --- /dev/null +++ b/esp32p4/src/cache/l2_ibus0_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS0_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS0_CONFLICT_CNT` reader - The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0."] +pub type L2_IBUS0_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0."] + #[inline(always)] + pub fn l2_ibus0_conflict_cnt(&self) -> L2_IBUS0_CONFLICT_CNT_R { + L2_IBUS0_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS0_ACS_CONFLICT_CNT") + .field( + "l2_ibus0_conflict_cnt", + &format_args!("{}", self.l2_ibus0_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS0_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS0_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus0_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS0_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS0_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L2_IBUS0_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus0_acs_hit_cnt.rs b/esp32p4/src/cache/l2_ibus0_acs_hit_cnt.rs new file mode 100644 index 0000000000..128a94c3e9 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus0_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS0_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS0_HIT_CNT` reader - The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0."] +pub type L2_IBUS0_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0."] + #[inline(always)] + pub fn l2_ibus0_hit_cnt(&self) -> L2_IBUS0_HIT_CNT_R { + L2_IBUS0_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS0_ACS_HIT_CNT") + .field( + "l2_ibus0_hit_cnt", + &format_args!("{}", self.l2_ibus0_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS0_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS0_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus0_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS0_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS0_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L2_IBUS0_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus0_acs_miss_cnt.rs b/esp32p4/src/cache/l2_ibus0_acs_miss_cnt.rs new file mode 100644 index 0000000000..e9a0b7bf61 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus0_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS0_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS0_MISS_CNT` reader - The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0."] +pub type L2_IBUS0_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0."] + #[inline(always)] + pub fn l2_ibus0_miss_cnt(&self) -> L2_IBUS0_MISS_CNT_R { + L2_IBUS0_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS0_ACS_MISS_CNT") + .field( + "l2_ibus0_miss_cnt", + &format_args!("{}", self.l2_ibus0_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS0_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS0_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus0_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS0_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS0_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L2_IBUS0_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus0_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_ibus0_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..cf6cd996da --- /dev/null +++ b/esp32p4/src/cache/l2_ibus0_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS0_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS0_NXTLVL_RD_CNT` reader - The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0."] +pub type L2_IBUS0_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0."] + #[inline(always)] + pub fn l2_ibus0_nxtlvl_rd_cnt(&self) -> L2_IBUS0_NXTLVL_RD_CNT_R { + L2_IBUS0_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS0_ACS_NXTLVL_RD_CNT") + .field( + "l2_ibus0_nxtlvl_rd_cnt", + &format_args!("{}", self.l2_ibus0_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS0_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS0_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus0_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS0_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS0_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L2_IBUS0_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus1_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_ibus1_acs_conflict_cnt.rs new file mode 100644 index 0000000000..7e5607c6a6 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus1_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS1_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS1_CONFLICT_CNT` reader - The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1."] +pub type L2_IBUS1_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1."] + #[inline(always)] + pub fn l2_ibus1_conflict_cnt(&self) -> L2_IBUS1_CONFLICT_CNT_R { + L2_IBUS1_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS1_ACS_CONFLICT_CNT") + .field( + "l2_ibus1_conflict_cnt", + &format_args!("{}", self.l2_ibus1_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS1_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS1_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus1_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS1_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS1_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L2_IBUS1_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus1_acs_hit_cnt.rs b/esp32p4/src/cache/l2_ibus1_acs_hit_cnt.rs new file mode 100644 index 0000000000..fec50a8d77 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus1_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS1_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS1_HIT_CNT` reader - The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1."] +pub type L2_IBUS1_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1."] + #[inline(always)] + pub fn l2_ibus1_hit_cnt(&self) -> L2_IBUS1_HIT_CNT_R { + L2_IBUS1_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS1_ACS_HIT_CNT") + .field( + "l2_ibus1_hit_cnt", + &format_args!("{}", self.l2_ibus1_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS1_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS1_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus1_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS1_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS1_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L2_IBUS1_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus1_acs_miss_cnt.rs b/esp32p4/src/cache/l2_ibus1_acs_miss_cnt.rs new file mode 100644 index 0000000000..3ced3b8c54 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus1_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS1_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS1_MISS_CNT` reader - The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1."] +pub type L2_IBUS1_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1."] + #[inline(always)] + pub fn l2_ibus1_miss_cnt(&self) -> L2_IBUS1_MISS_CNT_R { + L2_IBUS1_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS1_ACS_MISS_CNT") + .field( + "l2_ibus1_miss_cnt", + &format_args!("{}", self.l2_ibus1_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS1_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS1_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus1_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS1_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS1_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L2_IBUS1_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus1_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_ibus1_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..afd89d1938 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus1_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS1_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS1_NXTLVL_RD_CNT` reader - The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1."] +pub type L2_IBUS1_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1."] + #[inline(always)] + pub fn l2_ibus1_nxtlvl_rd_cnt(&self) -> L2_IBUS1_NXTLVL_RD_CNT_R { + L2_IBUS1_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS1_ACS_NXTLVL_RD_CNT") + .field( + "l2_ibus1_nxtlvl_rd_cnt", + &format_args!("{}", self.l2_ibus1_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS1_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS1_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus1_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS1_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS1_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L2_IBUS1_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus2_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_ibus2_acs_conflict_cnt.rs new file mode 100644 index 0000000000..94cb867822 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus2_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS2_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS2_CONFLICT_CNT` reader - The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2."] +pub type L2_IBUS2_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2."] + #[inline(always)] + pub fn l2_ibus2_conflict_cnt(&self) -> L2_IBUS2_CONFLICT_CNT_R { + L2_IBUS2_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS2_ACS_CONFLICT_CNT") + .field( + "l2_ibus2_conflict_cnt", + &format_args!("{}", self.l2_ibus2_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS2_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS2_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus2_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS2_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS2_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L2_IBUS2_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus2_acs_hit_cnt.rs b/esp32p4/src/cache/l2_ibus2_acs_hit_cnt.rs new file mode 100644 index 0000000000..583e67fb19 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus2_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS2_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS2_HIT_CNT` reader - The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2."] +pub type L2_IBUS2_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2."] + #[inline(always)] + pub fn l2_ibus2_hit_cnt(&self) -> L2_IBUS2_HIT_CNT_R { + L2_IBUS2_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS2_ACS_HIT_CNT") + .field( + "l2_ibus2_hit_cnt", + &format_args!("{}", self.l2_ibus2_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS2_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS2_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus2_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS2_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS2_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L2_IBUS2_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus2_acs_miss_cnt.rs b/esp32p4/src/cache/l2_ibus2_acs_miss_cnt.rs new file mode 100644 index 0000000000..cd099cc0db --- /dev/null +++ b/esp32p4/src/cache/l2_ibus2_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS2_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS2_MISS_CNT` reader - The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2."] +pub type L2_IBUS2_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2."] + #[inline(always)] + pub fn l2_ibus2_miss_cnt(&self) -> L2_IBUS2_MISS_CNT_R { + L2_IBUS2_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS2_ACS_MISS_CNT") + .field( + "l2_ibus2_miss_cnt", + &format_args!("{}", self.l2_ibus2_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS2_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS2_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus2_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS2_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS2_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L2_IBUS2_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus2_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_ibus2_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..ef29c7d3a4 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus2_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS2_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS2_NXTLVL_RD_CNT` reader - The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2."] +pub type L2_IBUS2_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2."] + #[inline(always)] + pub fn l2_ibus2_nxtlvl_rd_cnt(&self) -> L2_IBUS2_NXTLVL_RD_CNT_R { + L2_IBUS2_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS2_ACS_NXTLVL_RD_CNT") + .field( + "l2_ibus2_nxtlvl_rd_cnt", + &format_args!("{}", self.l2_ibus2_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS2_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS2_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus2_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS2_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS2_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L2_IBUS2_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus3_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_ibus3_acs_conflict_cnt.rs new file mode 100644 index 0000000000..cb920705f2 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus3_acs_conflict_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS3_ACS_CONFLICT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS3_CONFLICT_CNT` reader - The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3."] +pub type L2_IBUS3_CONFLICT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3."] + #[inline(always)] + pub fn l2_ibus3_conflict_cnt(&self) -> L2_IBUS3_CONFLICT_CNT_R { + L2_IBUS3_CONFLICT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS3_ACS_CONFLICT_CNT") + .field( + "l2_ibus3_conflict_cnt", + &format_args!("{}", self.l2_ibus3_conflict_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_conflict_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS3_ACS_CONFLICT_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS3_ACS_CONFLICT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus3_acs_conflict_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS3_ACS_CONFLICT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS3_ACS_CONFLICT_CNT to value 0"] +impl crate::Resettable for L2_IBUS3_ACS_CONFLICT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus3_acs_hit_cnt.rs b/esp32p4/src/cache/l2_ibus3_acs_hit_cnt.rs new file mode 100644 index 0000000000..b25e2ddd26 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus3_acs_hit_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS3_ACS_HIT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS3_HIT_CNT` reader - The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3."] +pub type L2_IBUS3_HIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3."] + #[inline(always)] + pub fn l2_ibus3_hit_cnt(&self) -> L2_IBUS3_HIT_CNT_R { + L2_IBUS3_HIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS3_ACS_HIT_CNT") + .field( + "l2_ibus3_hit_cnt", + &format_args!("{}", self.l2_ibus3_hit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_hit_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS3_ACS_HIT_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS3_ACS_HIT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus3_acs_hit_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS3_ACS_HIT_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS3_ACS_HIT_CNT to value 0"] +impl crate::Resettable for L2_IBUS3_ACS_HIT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus3_acs_miss_cnt.rs b/esp32p4/src/cache/l2_ibus3_acs_miss_cnt.rs new file mode 100644 index 0000000000..ecf7eb2d49 --- /dev/null +++ b/esp32p4/src/cache/l2_ibus3_acs_miss_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS3_ACS_MISS_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS3_MISS_CNT` reader - The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3."] +pub type L2_IBUS3_MISS_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3."] + #[inline(always)] + pub fn l2_ibus3_miss_cnt(&self) -> L2_IBUS3_MISS_CNT_R { + L2_IBUS3_MISS_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS3_ACS_MISS_CNT") + .field( + "l2_ibus3_miss_cnt", + &format_args!("{}", self.l2_ibus3_miss_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS3_ACS_MISS_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS3_ACS_MISS_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus3_acs_miss_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS3_ACS_MISS_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS3_ACS_MISS_CNT to value 0"] +impl crate::Resettable for L2_IBUS3_ACS_MISS_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_ibus3_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_ibus3_acs_nxtlvl_rd_cnt.rs new file mode 100644 index 0000000000..8ff96e2b0c --- /dev/null +++ b/esp32p4/src/cache/l2_ibus3_acs_nxtlvl_rd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `L2_IBUS3_ACS_NXTLVL_RD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `L2_IBUS3_NXTLVL_RD_CNT` reader - The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3."] +pub type L2_IBUS3_NXTLVL_RD_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3."] + #[inline(always)] + pub fn l2_ibus3_nxtlvl_rd_cnt(&self) -> L2_IBUS3_NXTLVL_RD_CNT_R { + L2_IBUS3_NXTLVL_RD_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_IBUS3_ACS_NXTLVL_RD_CNT") + .field( + "l2_ibus3_nxtlvl_rd_cnt", + &format_args!("{}", self.l2_ibus3_nxtlvl_rd_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L2-Cache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_nxtlvl_rd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_IBUS3_ACS_NXTLVL_RD_CNT_SPEC; +impl crate::RegisterSpec for L2_IBUS3_ACS_NXTLVL_RD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_ibus3_acs_nxtlvl_rd_cnt::R`](R) reader structure"] +impl crate::Readable for L2_IBUS3_ACS_NXTLVL_RD_CNT_SPEC {} +#[doc = "`reset()` method sets L2_IBUS3_ACS_NXTLVL_RD_CNT to value 0"] +impl crate::Resettable for L2_IBUS3_ACS_NXTLVL_RD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/l2_unallocate_buffer_clear.rs b/esp32p4/src/cache/l2_unallocate_buffer_clear.rs new file mode 100644 index 0000000000..4fef51c05d --- /dev/null +++ b/esp32p4/src/cache/l2_unallocate_buffer_clear.rs @@ -0,0 +1,68 @@ +#[doc = "Register `L2_UNALLOCATE_BUFFER_CLEAR` reader"] +pub type R = crate::R; +#[doc = "Register `L2_UNALLOCATE_BUFFER_CLEAR` writer"] +pub type W = crate::W; +#[doc = "Field `L2_CACHE_UNALLOC_CLR` reader - The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed."] +pub type L2_CACHE_UNALLOC_CLR_R = crate::BitReader; +#[doc = "Field `L2_CACHE_UNALLOC_CLR` writer - The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed."] +pub type L2_CACHE_UNALLOC_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed."] + #[inline(always)] + pub fn l2_cache_unalloc_clr(&self) -> L2_CACHE_UNALLOC_CLR_R { + L2_CACHE_UNALLOC_CLR_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("L2_UNALLOCATE_BUFFER_CLEAR") + .field( + "l2_cache_unalloc_clr", + &format_args!("{}", self.l2_cache_unalloc_clr().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed."] + #[inline(always)] + #[must_use] + pub fn l2_cache_unalloc_clr( + &mut self, + ) -> L2_CACHE_UNALLOC_CLR_W { + L2_CACHE_UNALLOC_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Unallocate request buffer clear registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_unallocate_buffer_clear::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`l2_unallocate_buffer_clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct L2_UNALLOCATE_BUFFER_CLEAR_SPEC; +impl crate::RegisterSpec for L2_UNALLOCATE_BUFFER_CLEAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`l2_unallocate_buffer_clear::R`](R) reader structure"] +impl crate::Readable for L2_UNALLOCATE_BUFFER_CLEAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`l2_unallocate_buffer_clear::W`](W) writer structure"] +impl crate::Writable for L2_UNALLOCATE_BUFFER_CLEAR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets L2_UNALLOCATE_BUFFER_CLEAR to value 0"] +impl crate::Resettable for L2_UNALLOCATE_BUFFER_CLEAR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/level_split0.rs b/esp32p4/src/cache/level_split0.rs new file mode 100644 index 0000000000..bdfc9ce7d5 --- /dev/null +++ b/esp32p4/src/cache/level_split0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `LEVEL_SPLIT0` reader"] +pub type R = crate::R; +#[doc = "Field `LEVEL_SPLIT0` reader - Reserved"] +pub type LEVEL_SPLIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Reserved"] + #[inline(always)] + pub fn level_split0(&self) -> LEVEL_SPLIT0_R { + LEVEL_SPLIT0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LEVEL_SPLIT0") + .field( + "level_split0", + &format_args!("{}", self.level_split0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "USED TO SPLIT L1 CACHE AND L2 CACHE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`level_split0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LEVEL_SPLIT0_SPEC; +impl crate::RegisterSpec for LEVEL_SPLIT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`level_split0::R`](R) reader structure"] +impl crate::Readable for LEVEL_SPLIT0_SPEC {} +#[doc = "`reset()` method sets LEVEL_SPLIT0 to value 0x026c"] +impl crate::Resettable for LEVEL_SPLIT0_SPEC { + const RESET_VALUE: Self::Ux = 0x026c; +} diff --git a/esp32p4/src/cache/level_split1.rs b/esp32p4/src/cache/level_split1.rs new file mode 100644 index 0000000000..64f8398293 --- /dev/null +++ b/esp32p4/src/cache/level_split1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `LEVEL_SPLIT1` reader"] +pub type R = crate::R; +#[doc = "Field `LEVEL_SPLIT1` reader - Reserved"] +pub type LEVEL_SPLIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Reserved"] + #[inline(always)] + pub fn level_split1(&self) -> LEVEL_SPLIT1_R { + LEVEL_SPLIT1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LEVEL_SPLIT1") + .field( + "level_split1", + &format_args!("{}", self.level_split1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "USED TO SPLIT L1 CACHE AND L2 CACHE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`level_split1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LEVEL_SPLIT1_SPEC; +impl crate::RegisterSpec for LEVEL_SPLIT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`level_split1::R`](R) reader structure"] +impl crate::Readable for LEVEL_SPLIT1_SPEC {} +#[doc = "`reset()` method sets LEVEL_SPLIT1 to value 0x03d0"] +impl crate::Resettable for LEVEL_SPLIT1_SPEC { + const RESET_VALUE: Self::Ux = 0x03d0; +} diff --git a/esp32p4/src/cache/lock_addr.rs b/esp32p4/src/cache/lock_addr.rs new file mode 100644 index 0000000000..4861484ffe --- /dev/null +++ b/esp32p4/src/cache/lock_addr.rs @@ -0,0 +1,63 @@ +#[doc = "Register `LOCK_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `LOCK_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `LOCK_ADDR` reader - Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG"] +pub type LOCK_ADDR_R = crate::FieldReader; +#[doc = "Field `LOCK_ADDR` writer - Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG"] +pub type LOCK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG"] + #[inline(always)] + pub fn lock_addr(&self) -> LOCK_ADDR_R { + LOCK_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LOCK_ADDR") + .field("lock_addr", &format_args!("{}", self.lock_addr().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn lock_addr(&mut self) -> LOCK_ADDR_W { + LOCK_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Lock (manual lock) address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LOCK_ADDR_SPEC; +impl crate::RegisterSpec for LOCK_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lock_addr::R`](R) reader structure"] +impl crate::Readable for LOCK_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lock_addr::W`](W) writer structure"] +impl crate::Writable for LOCK_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LOCK_ADDR to value 0"] +impl crate::Resettable for LOCK_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/lock_ctrl.rs b/esp32p4/src/cache/lock_ctrl.rs new file mode 100644 index 0000000000..4660bb0bfc --- /dev/null +++ b/esp32p4/src/cache/lock_ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `LOCK_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LOCK_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LOCK_ENA` reader - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) lock operation can be applied on LL1-ICache, L1-DCache and L2-Cache."] +pub type LOCK_ENA_R = crate::BitReader; +#[doc = "Field `LOCK_ENA` writer - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) lock operation can be applied on LL1-ICache, L1-DCache and L2-Cache."] +pub type LOCK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UNLOCK_ENA` reader - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. Note that (1) this bit and lock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock operation can be applied on L1-ICache, L1-DCache and L2-Cache."] +pub type UNLOCK_ENA_R = crate::BitReader; +#[doc = "Field `UNLOCK_ENA` writer - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. Note that (1) this bit and lock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock operation can be applied on L1-ICache, L1-DCache and L2-Cache."] +pub type UNLOCK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK_DONE` reader - The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished."] +pub type LOCK_DONE_R = crate::BitReader; +#[doc = "Field `LOCK_RGID` reader - The bit is used to set the gid of cache lock/unlock."] +pub type LOCK_RGID_R = crate::FieldReader; +#[doc = "Field `LOCK_RGID` writer - The bit is used to set the gid of cache lock/unlock."] +pub type LOCK_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) lock operation can be applied on LL1-ICache, L1-DCache and L2-Cache."] + #[inline(always)] + pub fn lock_ena(&self) -> LOCK_ENA_R { + LOCK_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. Note that (1) this bit and lock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock operation can be applied on L1-ICache, L1-DCache and L2-Cache."] + #[inline(always)] + pub fn unlock_ena(&self) -> UNLOCK_ENA_R { + UNLOCK_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn lock_done(&self) -> LOCK_DONE_R { + LOCK_DONE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of cache lock/unlock."] + #[inline(always)] + pub fn lock_rgid(&self) -> LOCK_RGID_R { + LOCK_RGID_R::new(((self.bits >> 3) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LOCK_CTRL") + .field("lock_ena", &format_args!("{}", self.lock_ena().bit())) + .field("unlock_ena", &format_args!("{}", self.unlock_ena().bit())) + .field("lock_done", &format_args!("{}", self.lock_done().bit())) + .field("lock_rgid", &format_args!("{}", self.lock_rgid().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) lock operation can be applied on LL1-ICache, L1-DCache and L2-Cache."] + #[inline(always)] + #[must_use] + pub fn lock_ena(&mut self) -> LOCK_ENA_W { + LOCK_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. Note that (1) this bit and lock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock operation can be applied on L1-ICache, L1-DCache and L2-Cache."] + #[inline(always)] + #[must_use] + pub fn unlock_ena(&mut self) -> UNLOCK_ENA_W { + UNLOCK_ENA_W::new(self, 1) + } + #[doc = "Bits 3:6 - The bit is used to set the gid of cache lock/unlock."] + #[inline(always)] + #[must_use] + pub fn lock_rgid(&mut self) -> LOCK_RGID_W { + LOCK_RGID_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Lock-class (manual lock) operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LOCK_CTRL_SPEC; +impl crate::RegisterSpec for LOCK_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lock_ctrl::R`](R) reader structure"] +impl crate::Readable for LOCK_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lock_ctrl::W`](W) writer structure"] +impl crate::Writable for LOCK_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LOCK_CTRL to value 0x04"] +impl crate::Resettable for LOCK_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/cache/lock_map.rs b/esp32p4/src/cache/lock_map.rs new file mode 100644 index 0000000000..8bde9cb337 --- /dev/null +++ b/esp32p4/src/cache/lock_map.rs @@ -0,0 +1,63 @@ +#[doc = "Register `LOCK_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LOCK_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `LOCK_MAP` reader - Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. \\[0\\]: L1-ICache0, \\[1\\]: L1-ICache1, \\[2\\]: L1-ICache2, \\[3\\]: L1-ICache3, \\[4\\]: L1-DCache, \\[5\\]: L2-Cache."] +pub type LOCK_MAP_R = crate::FieldReader; +#[doc = "Field `LOCK_MAP` writer - Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. \\[0\\]: L1-ICache0, \\[1\\]: L1-ICache1, \\[2\\]: L1-ICache2, \\[3\\]: L1-ICache3, \\[4\\]: L1-DCache, \\[5\\]: L2-Cache."] +pub type LOCK_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. \\[0\\]: L1-ICache0, \\[1\\]: L1-ICache1, \\[2\\]: L1-ICache2, \\[3\\]: L1-ICache3, \\[4\\]: L1-DCache, \\[5\\]: L2-Cache."] + #[inline(always)] + pub fn lock_map(&self) -> LOCK_MAP_R { + LOCK_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LOCK_MAP") + .field("lock_map", &format_args!("{}", self.lock_map().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. \\[0\\]: L1-ICache0, \\[1\\]: L1-ICache1, \\[2\\]: L1-ICache2, \\[3\\]: L1-ICache3, \\[4\\]: L1-DCache, \\[5\\]: L2-Cache."] + #[inline(always)] + #[must_use] + pub fn lock_map(&mut self) -> LOCK_MAP_W { + LOCK_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Lock (manual lock) map configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LOCK_MAP_SPEC; +impl crate::RegisterSpec for LOCK_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lock_map::R`](R) reader structure"] +impl crate::Readable for LOCK_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lock_map::W`](W) writer structure"] +impl crate::Writable for LOCK_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LOCK_MAP to value 0"] +impl crate::Resettable for LOCK_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/lock_size.rs b/esp32p4/src/cache/lock_size.rs new file mode 100644 index 0000000000..9e5465b14e --- /dev/null +++ b/esp32p4/src/cache/lock_size.rs @@ -0,0 +1,63 @@ +#[doc = "Register `LOCK_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `LOCK_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `LOCK_SIZE` reader - Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG"] +pub type LOCK_SIZE_R = crate::FieldReader; +#[doc = "Field `LOCK_SIZE` writer - Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG"] +pub type LOCK_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG"] + #[inline(always)] + pub fn lock_size(&self) -> LOCK_SIZE_R { + LOCK_SIZE_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LOCK_SIZE") + .field("lock_size", &format_args!("{}", self.lock_size().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn lock_size(&mut self) -> LOCK_SIZE_W { + LOCK_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Lock (manual lock) size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LOCK_SIZE_SPEC; +impl crate::RegisterSpec for LOCK_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lock_size::R`](R) reader structure"] +impl crate::Readable for LOCK_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lock_size::W`](W) writer structure"] +impl crate::Writable for LOCK_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LOCK_SIZE to value 0"] +impl crate::Resettable for LOCK_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/redundancy_sig0.rs b/esp32p4/src/cache/redundancy_sig0.rs new file mode 100644 index 0000000000..8139d7fa63 --- /dev/null +++ b/esp32p4/src/cache/redundancy_sig0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `REDUNDANCY_SIG0` reader"] +pub type R = crate::R; +#[doc = "Register `REDUNDANCY_SIG0` writer"] +pub type W = crate::W; +#[doc = "Field `REDCY_SIG0` reader - Those bits are prepared for ECO."] +pub type REDCY_SIG0_R = crate::FieldReader; +#[doc = "Field `REDCY_SIG0` writer - Those bits are prepared for ECO."] +pub type REDCY_SIG0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are prepared for ECO."] + #[inline(always)] + pub fn redcy_sig0(&self) -> REDCY_SIG0_R { + REDCY_SIG0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REDUNDANCY_SIG0") + .field("redcy_sig0", &format_args!("{}", self.redcy_sig0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are prepared for ECO."] + #[inline(always)] + #[must_use] + pub fn redcy_sig0(&mut self) -> REDCY_SIG0_W { + REDCY_SIG0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache redundancy signal 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REDUNDANCY_SIG0_SPEC; +impl crate::RegisterSpec for REDUNDANCY_SIG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`redundancy_sig0::R`](R) reader structure"] +impl crate::Readable for REDUNDANCY_SIG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`redundancy_sig0::W`](W) writer structure"] +impl crate::Writable for REDUNDANCY_SIG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REDUNDANCY_SIG0 to value 0"] +impl crate::Resettable for REDUNDANCY_SIG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/redundancy_sig1.rs b/esp32p4/src/cache/redundancy_sig1.rs new file mode 100644 index 0000000000..c5441788e3 --- /dev/null +++ b/esp32p4/src/cache/redundancy_sig1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `REDUNDANCY_SIG1` reader"] +pub type R = crate::R; +#[doc = "Register `REDUNDANCY_SIG1` writer"] +pub type W = crate::W; +#[doc = "Field `REDCY_SIG1` reader - Those bits are prepared for ECO."] +pub type REDCY_SIG1_R = crate::FieldReader; +#[doc = "Field `REDCY_SIG1` writer - Those bits are prepared for ECO."] +pub type REDCY_SIG1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are prepared for ECO."] + #[inline(always)] + pub fn redcy_sig1(&self) -> REDCY_SIG1_R { + REDCY_SIG1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REDUNDANCY_SIG1") + .field("redcy_sig1", &format_args!("{}", self.redcy_sig1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are prepared for ECO."] + #[inline(always)] + #[must_use] + pub fn redcy_sig1(&mut self) -> REDCY_SIG1_W { + REDCY_SIG1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache redundancy signal 1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REDUNDANCY_SIG1_SPEC; +impl crate::RegisterSpec for REDUNDANCY_SIG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`redundancy_sig1::R`](R) reader structure"] +impl crate::Readable for REDUNDANCY_SIG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`redundancy_sig1::W`](W) writer structure"] +impl crate::Writable for REDUNDANCY_SIG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REDUNDANCY_SIG1 to value 0"] +impl crate::Resettable for REDUNDANCY_SIG1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/redundancy_sig2.rs b/esp32p4/src/cache/redundancy_sig2.rs new file mode 100644 index 0000000000..7cde23818e --- /dev/null +++ b/esp32p4/src/cache/redundancy_sig2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `REDUNDANCY_SIG2` reader"] +pub type R = crate::R; +#[doc = "Register `REDUNDANCY_SIG2` writer"] +pub type W = crate::W; +#[doc = "Field `REDCY_SIG2` reader - Those bits are prepared for ECO."] +pub type REDCY_SIG2_R = crate::FieldReader; +#[doc = "Field `REDCY_SIG2` writer - Those bits are prepared for ECO."] +pub type REDCY_SIG2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are prepared for ECO."] + #[inline(always)] + pub fn redcy_sig2(&self) -> REDCY_SIG2_R { + REDCY_SIG2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REDUNDANCY_SIG2") + .field("redcy_sig2", &format_args!("{}", self.redcy_sig2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are prepared for ECO."] + #[inline(always)] + #[must_use] + pub fn redcy_sig2(&mut self) -> REDCY_SIG2_W { + REDCY_SIG2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache redundancy signal 2 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REDUNDANCY_SIG2_SPEC; +impl crate::RegisterSpec for REDUNDANCY_SIG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`redundancy_sig2::R`](R) reader structure"] +impl crate::Readable for REDUNDANCY_SIG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`redundancy_sig2::W`](W) writer structure"] +impl crate::Writable for REDUNDANCY_SIG2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REDUNDANCY_SIG2 to value 0"] +impl crate::Resettable for REDUNDANCY_SIG2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/redundancy_sig3.rs b/esp32p4/src/cache/redundancy_sig3.rs new file mode 100644 index 0000000000..68b543e05f --- /dev/null +++ b/esp32p4/src/cache/redundancy_sig3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `REDUNDANCY_SIG3` reader"] +pub type R = crate::R; +#[doc = "Register `REDUNDANCY_SIG3` writer"] +pub type W = crate::W; +#[doc = "Field `REDCY_SIG3` reader - Those bits are prepared for ECO."] +pub type REDCY_SIG3_R = crate::FieldReader; +#[doc = "Field `REDCY_SIG3` writer - Those bits are prepared for ECO."] +pub type REDCY_SIG3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are prepared for ECO."] + #[inline(always)] + pub fn redcy_sig3(&self) -> REDCY_SIG3_R { + REDCY_SIG3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REDUNDANCY_SIG3") + .field("redcy_sig3", &format_args!("{}", self.redcy_sig3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are prepared for ECO."] + #[inline(always)] + #[must_use] + pub fn redcy_sig3(&mut self) -> REDCY_SIG3_W { + REDCY_SIG3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Cache redundancy signal 3 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`redundancy_sig3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REDUNDANCY_SIG3_SPEC; +impl crate::RegisterSpec for REDUNDANCY_SIG3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`redundancy_sig3::R`](R) reader structure"] +impl crate::Readable for REDUNDANCY_SIG3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`redundancy_sig3::W`](W) writer structure"] +impl crate::Writable for REDUNDANCY_SIG3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REDUNDANCY_SIG3 to value 0"] +impl crate::Resettable for REDUNDANCY_SIG3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/redundancy_sig4.rs b/esp32p4/src/cache/redundancy_sig4.rs new file mode 100644 index 0000000000..b1ec160e4d --- /dev/null +++ b/esp32p4/src/cache/redundancy_sig4.rs @@ -0,0 +1,36 @@ +#[doc = "Register `REDUNDANCY_SIG4` reader"] +pub type R = crate::R; +#[doc = "Field `REDCY_SIG4` reader - Those bits are prepared for ECO."] +pub type REDCY_SIG4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Those bits are prepared for ECO."] + #[inline(always)] + pub fn redcy_sig4(&self) -> REDCY_SIG4_R { + REDCY_SIG4_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REDUNDANCY_SIG4") + .field("redcy_sig4", &format_args!("{}", self.redcy_sig4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Cache redundancy signal 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REDUNDANCY_SIG4_SPEC; +impl crate::RegisterSpec for REDUNDANCY_SIG4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`redundancy_sig4::R`](R) reader structure"] +impl crate::Readable for REDUNDANCY_SIG4_SPEC {} +#[doc = "`reset()` method sets REDUNDANCY_SIG4 to value 0"] +impl crate::Resettable for REDUNDANCY_SIG4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/sync_addr.rs b/esp32p4/src/cache/sync_addr.rs new file mode 100644 index 0000000000..8725058e33 --- /dev/null +++ b/esp32p4/src/cache/sync_addr.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SYNC_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SYNC_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `SYNC_ADDR` reader - Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG"] +pub type SYNC_ADDR_R = crate::FieldReader; +#[doc = "Field `SYNC_ADDR` writer - Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG"] +pub type SYNC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG"] + #[inline(always)] + pub fn sync_addr(&self) -> SYNC_ADDR_R { + SYNC_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYNC_ADDR") + .field("sync_addr", &format_args!("{}", self.sync_addr().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG"] + #[inline(always)] + #[must_use] + pub fn sync_addr(&mut self) -> SYNC_ADDR_W { + SYNC_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Sync address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYNC_ADDR_SPEC; +impl crate::RegisterSpec for SYNC_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sync_addr::R`](R) reader structure"] +impl crate::Readable for SYNC_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sync_addr::W`](W) writer structure"] +impl crate::Writable for SYNC_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYNC_ADDR to value 0"] +impl crate::Resettable for SYNC_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/sync_ctrl.rs b/esp32p4/src/cache/sync_ctrl.rs new file mode 100644 index 0000000000..5df6ae7e97 --- /dev/null +++ b/esp32p4/src/cache/sync_ctrl.rs @@ -0,0 +1,144 @@ +#[doc = "Register `SYNC_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SYNC_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `INVALIDATE_ENA` reader - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] +pub type INVALIDATE_ENA_R = crate::BitReader; +#[doc = "Field `INVALIDATE_ENA` writer - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] +pub type INVALIDATE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAN_ENA` reader - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] +pub type CLEAN_ENA_R = crate::BitReader; +#[doc = "Field `CLEAN_ENA` writer - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] +pub type CLEAN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WRITEBACK_ENA` reader - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] +pub type WRITEBACK_ENA_R = crate::BitReader; +#[doc = "Field `WRITEBACK_ENA` writer - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] +pub type WRITEBACK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WRITEBACK_INVALIDATE_ENA` reader - The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] +pub type WRITEBACK_INVALIDATE_ENA_R = crate::BitReader; +#[doc = "Field `WRITEBACK_INVALIDATE_ENA` writer - The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] +pub type WRITEBACK_INVALIDATE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYNC_DONE` reader - The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished."] +pub type SYNC_DONE_R = crate::BitReader; +#[doc = "Field `SYNC_RGID` reader - The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate)"] +pub type SYNC_RGID_R = crate::FieldReader; +#[doc = "Field `SYNC_RGID` writer - The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate)"] +pub type SYNC_RGID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] + #[inline(always)] + pub fn invalidate_ena(&self) -> INVALIDATE_ENA_R { + INVALIDATE_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] + #[inline(always)] + pub fn clean_ena(&self) -> CLEAN_ENA_R { + CLEAN_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] + #[inline(always)] + pub fn writeback_ena(&self) -> WRITEBACK_ENA_R { + WRITEBACK_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] + #[inline(always)] + pub fn writeback_invalidate_ena(&self) -> WRITEBACK_INVALIDATE_ENA_R { + WRITEBACK_INVALIDATE_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished."] + #[inline(always)] + pub fn sync_done(&self) -> SYNC_DONE_R { + SYNC_DONE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:8 - The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate)"] + #[inline(always)] + pub fn sync_rgid(&self) -> SYNC_RGID_R { + SYNC_RGID_R::new(((self.bits >> 5) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYNC_CTRL") + .field( + "invalidate_ena", + &format_args!("{}", self.invalidate_ena().bit()), + ) + .field("clean_ena", &format_args!("{}", self.clean_ena().bit())) + .field( + "writeback_ena", + &format_args!("{}", self.writeback_ena().bit()), + ) + .field( + "writeback_invalidate_ena", + &format_args!("{}", self.writeback_invalidate_ena().bit()), + ) + .field("sync_done", &format_args!("{}", self.sync_done().bit())) + .field("sync_rgid", &format_args!("{}", self.sync_rgid().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] + #[inline(always)] + #[must_use] + pub fn invalidate_ena(&mut self) -> INVALIDATE_ENA_W { + INVALIDATE_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] + #[inline(always)] + #[must_use] + pub fn clean_ena(&mut self) -> CLEAN_ENA_W { + CLEAN_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] + #[inline(always)] + #[must_use] + pub fn writeback_ena(&mut self) -> WRITEBACK_ENA_W { + WRITEBACK_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."] + #[inline(always)] + #[must_use] + pub fn writeback_invalidate_ena(&mut self) -> WRITEBACK_INVALIDATE_ENA_W { + WRITEBACK_INVALIDATE_ENA_W::new(self, 3) + } + #[doc = "Bits 5:8 - The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate)"] + #[inline(always)] + #[must_use] + pub fn sync_rgid(&mut self) -> SYNC_RGID_W { + SYNC_RGID_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Sync-class operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYNC_CTRL_SPEC; +impl crate::RegisterSpec for SYNC_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sync_ctrl::R`](R) reader structure"] +impl crate::Readable for SYNC_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sync_ctrl::W`](W) writer structure"] +impl crate::Writable for SYNC_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYNC_CTRL to value 0x01"] +impl crate::Resettable for SYNC_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/cache/sync_l1_cache_preload_exception.rs b/esp32p4/src/cache/sync_l1_cache_preload_exception.rs new file mode 100644 index 0000000000..0be5e0a991 --- /dev/null +++ b/esp32p4/src/cache/sync_l1_cache_preload_exception.rs @@ -0,0 +1,94 @@ +#[doc = "Register `SYNC_L1_CACHE_PRELOAD_EXCEPTION` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE0_PLD_ERR_CODE` reader - The value 2 is Only available which means preload size is error in L1-ICache0."] +pub type L1_ICACHE0_PLD_ERR_CODE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE1_PLD_ERR_CODE` reader - The value 2 is Only available which means preload size is error in L1-ICache1."] +pub type L1_ICACHE1_PLD_ERR_CODE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE2_PLD_ERR_CODE` reader - Reserved"] +pub type L1_ICACHE2_PLD_ERR_CODE_R = crate::FieldReader; +#[doc = "Field `L1_ICACHE3_PLD_ERR_CODE` reader - Reserved"] +pub type L1_ICACHE3_PLD_ERR_CODE_R = crate::FieldReader; +#[doc = "Field `L1_DCACHE_PLD_ERR_CODE` reader - The value 2 is Only available which means preload size is error in L1-DCache."] +pub type L1_DCACHE_PLD_ERR_CODE_R = crate::FieldReader; +#[doc = "Field `SYNC_ERR_CODE` reader - The values 0-2 are available which means sync map, command conflict and size are error in Cache System."] +pub type SYNC_ERR_CODE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - The value 2 is Only available which means preload size is error in L1-ICache0."] + #[inline(always)] + pub fn l1_icache0_pld_err_code(&self) -> L1_ICACHE0_PLD_ERR_CODE_R { + L1_ICACHE0_PLD_ERR_CODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - The value 2 is Only available which means preload size is error in L1-ICache1."] + #[inline(always)] + pub fn l1_icache1_pld_err_code(&self) -> L1_ICACHE1_PLD_ERR_CODE_R { + L1_ICACHE1_PLD_ERR_CODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Reserved"] + #[inline(always)] + pub fn l1_icache2_pld_err_code(&self) -> L1_ICACHE2_PLD_ERR_CODE_R { + L1_ICACHE2_PLD_ERR_CODE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Reserved"] + #[inline(always)] + pub fn l1_icache3_pld_err_code(&self) -> L1_ICACHE3_PLD_ERR_CODE_R { + L1_ICACHE3_PLD_ERR_CODE_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - The value 2 is Only available which means preload size is error in L1-DCache."] + #[inline(always)] + pub fn l1_dcache_pld_err_code(&self) -> L1_DCACHE_PLD_ERR_CODE_R { + L1_DCACHE_PLD_ERR_CODE_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 12:13 - The values 0-2 are available which means sync map, command conflict and size are error in Cache System."] + #[inline(always)] + pub fn sync_err_code(&self) -> SYNC_ERR_CODE_R { + SYNC_ERR_CODE_R::new(((self.bits >> 12) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYNC_L1_CACHE_PRELOAD_EXCEPTION") + .field( + "l1_icache0_pld_err_code", + &format_args!("{}", self.l1_icache0_pld_err_code().bits()), + ) + .field( + "l1_icache1_pld_err_code", + &format_args!("{}", self.l1_icache1_pld_err_code().bits()), + ) + .field( + "l1_icache2_pld_err_code", + &format_args!("{}", self.l1_icache2_pld_err_code().bits()), + ) + .field( + "l1_icache3_pld_err_code", + &format_args!("{}", self.l1_icache3_pld_err_code().bits()), + ) + .field( + "l1_dcache_pld_err_code", + &format_args!("{}", self.l1_dcache_pld_err_code().bits()), + ) + .field( + "sync_err_code", + &format_args!("{}", self.sync_err_code().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Cache Sync/Preload Operation exception register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_exception::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYNC_L1_CACHE_PRELOAD_EXCEPTION_SPEC; +impl crate::RegisterSpec for SYNC_L1_CACHE_PRELOAD_EXCEPTION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sync_l1_cache_preload_exception::R`](R) reader structure"] +impl crate::Readable for SYNC_L1_CACHE_PRELOAD_EXCEPTION_SPEC {} +#[doc = "`reset()` method sets SYNC_L1_CACHE_PRELOAD_EXCEPTION to value 0"] +impl crate::Resettable for SYNC_L1_CACHE_PRELOAD_EXCEPTION_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/sync_l1_cache_preload_int_clr.rs b/esp32p4/src/cache/sync_l1_cache_preload_int_clr.rs new file mode 100644 index 0000000000..1c8d0d290e --- /dev/null +++ b/esp32p4/src/cache/sync_l1_cache_preload_int_clr.rs @@ -0,0 +1,167 @@ +#[doc = "Register `SYNC_L1_CACHE_PRELOAD_INT_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `SYNC_L1_CACHE_PRELOAD_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_PLD_DONE_INT_CLR` writer - The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done."] +pub type L1_ICACHE0_PLD_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_PLD_DONE_INT_CLR` writer - The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done."] +pub type L1_ICACHE1_PLD_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_PLD_DONE_INT_CLR` reader - Reserved"] +pub type L1_ICACHE2_PLD_DONE_INT_CLR_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PLD_DONE_INT_CLR` reader - Reserved"] +pub type L1_ICACHE3_PLD_DONE_INT_CLR_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_DONE_INT_CLR` writer - The bit is used to clear interrupt that occurs only when L1-DCache preload-operation is done."] +pub type L1_DCACHE_PLD_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYNC_DONE_INT_CLR` writer - The bit is used to clear interrupt that occurs only when Cache sync-operation is done."] +pub type SYNC_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_PLD_ERR_INT_CLR` writer - The bit is used to clear interrupt of L1-ICache0 preload-operation error."] +pub type L1_ICACHE0_PLD_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_PLD_ERR_INT_CLR` writer - The bit is used to clear interrupt of L1-ICache1 preload-operation error."] +pub type L1_ICACHE1_PLD_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_PLD_ERR_INT_CLR` reader - Reserved"] +pub type L1_ICACHE2_PLD_ERR_INT_CLR_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PLD_ERR_INT_CLR` reader - Reserved"] +pub type L1_ICACHE3_PLD_ERR_INT_CLR_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_ERR_INT_CLR` writer - The bit is used to clear interrupt of L1-DCache preload-operation error."] +pub type L1_DCACHE_PLD_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYNC_ERR_INT_CLR` writer - The bit is used to clear interrupt of Cache sync-operation error."] +pub type SYNC_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_pld_done_int_clr(&self) -> L1_ICACHE2_PLD_DONE_INT_CLR_R { + L1_ICACHE2_PLD_DONE_INT_CLR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_pld_done_int_clr(&self) -> L1_ICACHE3_PLD_DONE_INT_CLR_R { + L1_ICACHE3_PLD_DONE_INT_CLR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn l1_icache2_pld_err_int_clr(&self) -> L1_ICACHE2_PLD_ERR_INT_CLR_R { + L1_ICACHE2_PLD_ERR_INT_CLR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn l1_icache3_pld_err_int_clr(&self) -> L1_ICACHE3_PLD_ERR_INT_CLR_R { + L1_ICACHE3_PLD_ERR_INT_CLR_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYNC_L1_CACHE_PRELOAD_INT_CLR") + .field( + "l1_icache2_pld_done_int_clr", + &format_args!("{}", self.l1_icache2_pld_done_int_clr().bit()), + ) + .field( + "l1_icache3_pld_done_int_clr", + &format_args!("{}", self.l1_icache3_pld_done_int_clr().bit()), + ) + .field( + "l1_icache2_pld_err_int_clr", + &format_args!("{}", self.l1_icache2_pld_err_int_clr().bit()), + ) + .field( + "l1_icache3_pld_err_int_clr", + &format_args!("{}", self.l1_icache3_pld_err_int_clr().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_pld_done_int_clr( + &mut self, + ) -> L1_ICACHE0_PLD_DONE_INT_CLR_W { + L1_ICACHE0_PLD_DONE_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_pld_done_int_clr( + &mut self, + ) -> L1_ICACHE1_PLD_DONE_INT_CLR_W { + L1_ICACHE1_PLD_DONE_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to clear interrupt that occurs only when L1-DCache preload-operation is done."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_pld_done_int_clr( + &mut self, + ) -> L1_DCACHE_PLD_DONE_INT_CLR_W { + L1_DCACHE_PLD_DONE_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 6 - The bit is used to clear interrupt that occurs only when Cache sync-operation is done."] + #[inline(always)] + #[must_use] + pub fn sync_done_int_clr(&mut self) -> SYNC_DONE_INT_CLR_W { + SYNC_DONE_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - The bit is used to clear interrupt of L1-ICache0 preload-operation error."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_pld_err_int_clr( + &mut self, + ) -> L1_ICACHE0_PLD_ERR_INT_CLR_W { + L1_ICACHE0_PLD_ERR_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - The bit is used to clear interrupt of L1-ICache1 preload-operation error."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_pld_err_int_clr( + &mut self, + ) -> L1_ICACHE1_PLD_ERR_INT_CLR_W { + L1_ICACHE1_PLD_ERR_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 11 - The bit is used to clear interrupt of L1-DCache preload-operation error."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_pld_err_int_clr( + &mut self, + ) -> L1_DCACHE_PLD_ERR_INT_CLR_W { + L1_DCACHE_PLD_ERR_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 13 - The bit is used to clear interrupt of Cache sync-operation error."] + #[inline(always)] + #[must_use] + pub fn sync_err_int_clr(&mut self) -> SYNC_ERR_INT_CLR_W { + SYNC_ERR_INT_CLR_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Sync Preload operation Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_l1_cache_preload_int_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYNC_L1_CACHE_PRELOAD_INT_CLR_SPEC; +impl crate::RegisterSpec for SYNC_L1_CACHE_PRELOAD_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sync_l1_cache_preload_int_clr::R`](R) reader structure"] +impl crate::Readable for SYNC_L1_CACHE_PRELOAD_INT_CLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sync_l1_cache_preload_int_clr::W`](W) writer structure"] +impl crate::Writable for SYNC_L1_CACHE_PRELOAD_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYNC_L1_CACHE_PRELOAD_INT_CLR to value 0"] +impl crate::Resettable for SYNC_L1_CACHE_PRELOAD_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/sync_l1_cache_preload_int_ena.rs b/esp32p4/src/cache/sync_l1_cache_preload_int_ena.rs new file mode 100644 index 0000000000..8a34229e75 --- /dev/null +++ b/esp32p4/src/cache/sync_l1_cache_preload_int_ena.rs @@ -0,0 +1,255 @@ +#[doc = "Register `SYNC_L1_CACHE_PRELOAD_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `SYNC_L1_CACHE_PRELOAD_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_PLD_DONE_INT_ENA` reader - The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs."] +pub type L1_ICACHE0_PLD_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_PLD_DONE_INT_ENA` writer - The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs."] +pub type L1_ICACHE0_PLD_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_PLD_DONE_INT_ENA` reader - The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs."] +pub type L1_ICACHE1_PLD_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PLD_DONE_INT_ENA` writer - The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs."] +pub type L1_ICACHE1_PLD_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_PLD_DONE_INT_ENA` reader - Reserved"] +pub type L1_ICACHE2_PLD_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PLD_DONE_INT_ENA` reader - Reserved"] +pub type L1_ICACHE3_PLD_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_DONE_INT_ENA` reader - The bit is used to enable interrupt of L1-DCache preload-operation. If preload operation is done, interrupt occurs."] +pub type L1_DCACHE_PLD_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_DONE_INT_ENA` writer - The bit is used to enable interrupt of L1-DCache preload-operation. If preload operation is done, interrupt occurs."] +pub type L1_DCACHE_PLD_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYNC_DONE_INT_ENA` reader - The bit is used to enable interrupt of Cache sync-operation done."] +pub type SYNC_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SYNC_DONE_INT_ENA` writer - The bit is used to enable interrupt of Cache sync-operation done."] +pub type SYNC_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_PLD_ERR_INT_ENA` reader - The bit is used to enable interrupt of L1-ICache0 preload-operation error."] +pub type L1_ICACHE0_PLD_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_PLD_ERR_INT_ENA` writer - The bit is used to enable interrupt of L1-ICache0 preload-operation error."] +pub type L1_ICACHE0_PLD_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_PLD_ERR_INT_ENA` reader - The bit is used to enable interrupt of L1-ICache1 preload-operation error."] +pub type L1_ICACHE1_PLD_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PLD_ERR_INT_ENA` writer - The bit is used to enable interrupt of L1-ICache1 preload-operation error."] +pub type L1_ICACHE1_PLD_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_PLD_ERR_INT_ENA` reader - Reserved"] +pub type L1_ICACHE2_PLD_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PLD_ERR_INT_ENA` reader - Reserved"] +pub type L1_ICACHE3_PLD_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_ERR_INT_ENA` reader - The bit is used to enable interrupt of L1-DCache preload-operation error."] +pub type L1_DCACHE_PLD_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_ERR_INT_ENA` writer - The bit is used to enable interrupt of L1-DCache preload-operation error."] +pub type L1_DCACHE_PLD_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYNC_ERR_INT_ENA` reader - The bit is used to enable interrupt of Cache sync-operation error."] +pub type SYNC_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SYNC_ERR_INT_ENA` writer - The bit is used to enable interrupt of Cache sync-operation error."] +pub type SYNC_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs."] + #[inline(always)] + pub fn l1_icache0_pld_done_int_ena(&self) -> L1_ICACHE0_PLD_DONE_INT_ENA_R { + L1_ICACHE0_PLD_DONE_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs."] + #[inline(always)] + pub fn l1_icache1_pld_done_int_ena(&self) -> L1_ICACHE1_PLD_DONE_INT_ENA_R { + L1_ICACHE1_PLD_DONE_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_pld_done_int_ena(&self) -> L1_ICACHE2_PLD_DONE_INT_ENA_R { + L1_ICACHE2_PLD_DONE_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_pld_done_int_ena(&self) -> L1_ICACHE3_PLD_DONE_INT_ENA_R { + L1_ICACHE3_PLD_DONE_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit is used to enable interrupt of L1-DCache preload-operation. If preload operation is done, interrupt occurs."] + #[inline(always)] + pub fn l1_dcache_pld_done_int_ena(&self) -> L1_DCACHE_PLD_DONE_INT_ENA_R { + L1_DCACHE_PLD_DONE_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - The bit is used to enable interrupt of Cache sync-operation done."] + #[inline(always)] + pub fn sync_done_int_ena(&self) -> SYNC_DONE_INT_ENA_R { + SYNC_DONE_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The bit is used to enable interrupt of L1-ICache0 preload-operation error."] + #[inline(always)] + pub fn l1_icache0_pld_err_int_ena(&self) -> L1_ICACHE0_PLD_ERR_INT_ENA_R { + L1_ICACHE0_PLD_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The bit is used to enable interrupt of L1-ICache1 preload-operation error."] + #[inline(always)] + pub fn l1_icache1_pld_err_int_ena(&self) -> L1_ICACHE1_PLD_ERR_INT_ENA_R { + L1_ICACHE1_PLD_ERR_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn l1_icache2_pld_err_int_ena(&self) -> L1_ICACHE2_PLD_ERR_INT_ENA_R { + L1_ICACHE2_PLD_ERR_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn l1_icache3_pld_err_int_ena(&self) -> L1_ICACHE3_PLD_ERR_INT_ENA_R { + L1_ICACHE3_PLD_ERR_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The bit is used to enable interrupt of L1-DCache preload-operation error."] + #[inline(always)] + pub fn l1_dcache_pld_err_int_ena(&self) -> L1_DCACHE_PLD_ERR_INT_ENA_R { + L1_DCACHE_PLD_ERR_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - The bit is used to enable interrupt of Cache sync-operation error."] + #[inline(always)] + pub fn sync_err_int_ena(&self) -> SYNC_ERR_INT_ENA_R { + SYNC_ERR_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYNC_L1_CACHE_PRELOAD_INT_ENA") + .field( + "l1_icache0_pld_done_int_ena", + &format_args!("{}", self.l1_icache0_pld_done_int_ena().bit()), + ) + .field( + "l1_icache1_pld_done_int_ena", + &format_args!("{}", self.l1_icache1_pld_done_int_ena().bit()), + ) + .field( + "l1_icache2_pld_done_int_ena", + &format_args!("{}", self.l1_icache2_pld_done_int_ena().bit()), + ) + .field( + "l1_icache3_pld_done_int_ena", + &format_args!("{}", self.l1_icache3_pld_done_int_ena().bit()), + ) + .field( + "l1_dcache_pld_done_int_ena", + &format_args!("{}", self.l1_dcache_pld_done_int_ena().bit()), + ) + .field( + "sync_done_int_ena", + &format_args!("{}", self.sync_done_int_ena().bit()), + ) + .field( + "l1_icache0_pld_err_int_ena", + &format_args!("{}", self.l1_icache0_pld_err_int_ena().bit()), + ) + .field( + "l1_icache1_pld_err_int_ena", + &format_args!("{}", self.l1_icache1_pld_err_int_ena().bit()), + ) + .field( + "l1_icache2_pld_err_int_ena", + &format_args!("{}", self.l1_icache2_pld_err_int_ena().bit()), + ) + .field( + "l1_icache3_pld_err_int_ena", + &format_args!("{}", self.l1_icache3_pld_err_int_ena().bit()), + ) + .field( + "l1_dcache_pld_err_int_ena", + &format_args!("{}", self.l1_dcache_pld_err_int_ena().bit()), + ) + .field( + "sync_err_int_ena", + &format_args!("{}", self.sync_err_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_pld_done_int_ena( + &mut self, + ) -> L1_ICACHE0_PLD_DONE_INT_ENA_W { + L1_ICACHE0_PLD_DONE_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_pld_done_int_ena( + &mut self, + ) -> L1_ICACHE1_PLD_DONE_INT_ENA_W { + L1_ICACHE1_PLD_DONE_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 4 - The bit is used to enable interrupt of L1-DCache preload-operation. If preload operation is done, interrupt occurs."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_pld_done_int_ena( + &mut self, + ) -> L1_DCACHE_PLD_DONE_INT_ENA_W { + L1_DCACHE_PLD_DONE_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 6 - The bit is used to enable interrupt of Cache sync-operation done."] + #[inline(always)] + #[must_use] + pub fn sync_done_int_ena(&mut self) -> SYNC_DONE_INT_ENA_W { + SYNC_DONE_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The bit is used to enable interrupt of L1-ICache0 preload-operation error."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_pld_err_int_ena( + &mut self, + ) -> L1_ICACHE0_PLD_ERR_INT_ENA_W { + L1_ICACHE0_PLD_ERR_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The bit is used to enable interrupt of L1-ICache1 preload-operation error."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_pld_err_int_ena( + &mut self, + ) -> L1_ICACHE1_PLD_ERR_INT_ENA_W { + L1_ICACHE1_PLD_ERR_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 11 - The bit is used to enable interrupt of L1-DCache preload-operation error."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_pld_err_int_ena( + &mut self, + ) -> L1_DCACHE_PLD_ERR_INT_ENA_W { + L1_DCACHE_PLD_ERR_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 13 - The bit is used to enable interrupt of Cache sync-operation error."] + #[inline(always)] + #[must_use] + pub fn sync_err_int_ena(&mut self) -> SYNC_ERR_INT_ENA_W { + SYNC_ERR_INT_ENA_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "L1-Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_l1_cache_preload_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYNC_L1_CACHE_PRELOAD_INT_ENA_SPEC; +impl crate::RegisterSpec for SYNC_L1_CACHE_PRELOAD_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sync_l1_cache_preload_int_ena::R`](R) reader structure"] +impl crate::Readable for SYNC_L1_CACHE_PRELOAD_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sync_l1_cache_preload_int_ena::W`](W) writer structure"] +impl crate::Writable for SYNC_L1_CACHE_PRELOAD_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYNC_L1_CACHE_PRELOAD_INT_ENA to value 0"] +impl crate::Resettable for SYNC_L1_CACHE_PRELOAD_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/sync_l1_cache_preload_int_raw.rs b/esp32p4/src/cache/sync_l1_cache_preload_int_raw.rs new file mode 100644 index 0000000000..6dce48fb1b --- /dev/null +++ b/esp32p4/src/cache/sync_l1_cache_preload_int_raw.rs @@ -0,0 +1,295 @@ +#[doc = "Register `SYNC_L1_CACHE_PRELOAD_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `SYNC_L1_CACHE_PRELOAD_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `L1_ICACHE0_PLD_DONE_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done."] +pub type L1_ICACHE0_PLD_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_PLD_DONE_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done."] +pub type L1_ICACHE0_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_PLD_DONE_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done."] +pub type L1_ICACHE1_PLD_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PLD_DONE_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done."] +pub type L1_ICACHE1_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_PLD_DONE_INT_RAW` reader - Reserved"] +pub type L1_ICACHE2_PLD_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_PLD_DONE_INT_RAW` writer - Reserved"] +pub type L1_ICACHE2_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE3_PLD_DONE_INT_RAW` reader - Reserved"] +pub type L1_ICACHE3_PLD_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PLD_DONE_INT_RAW` writer - Reserved"] +pub type L1_ICACHE3_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_PLD_DONE_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done."] +pub type L1_DCACHE_PLD_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_DONE_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done."] +pub type L1_DCACHE_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYNC_DONE_INT_RAW` reader - The raw bit of the interrupt that occurs only when Cache sync-operation is done."] +pub type SYNC_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SYNC_DONE_INT_RAW` writer - The raw bit of the interrupt that occurs only when Cache sync-operation is done."] +pub type SYNC_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE0_PLD_ERR_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs."] +pub type L1_ICACHE0_PLD_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_PLD_ERR_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs."] +pub type L1_ICACHE0_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE1_PLD_ERR_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs."] +pub type L1_ICACHE1_PLD_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PLD_ERR_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs."] +pub type L1_ICACHE1_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE2_PLD_ERR_INT_RAW` reader - Reserved"] +pub type L1_ICACHE2_PLD_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_PLD_ERR_INT_RAW` writer - Reserved"] +pub type L1_ICACHE2_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_ICACHE3_PLD_ERR_INT_RAW` reader - Reserved"] +pub type L1_ICACHE3_PLD_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PLD_ERR_INT_RAW` writer - Reserved"] +pub type L1_ICACHE3_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `L1_DCACHE_PLD_ERR_INT_RAW` reader - The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs."] +pub type L1_DCACHE_PLD_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_ERR_INT_RAW` writer - The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs."] +pub type L1_DCACHE_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYNC_ERR_INT_RAW` reader - The raw bit of the interrupt that occurs only when Cache sync-operation error occurs."] +pub type SYNC_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SYNC_ERR_INT_RAW` writer - The raw bit of the interrupt that occurs only when Cache sync-operation error occurs."] +pub type SYNC_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done."] + #[inline(always)] + pub fn l1_icache0_pld_done_int_raw(&self) -> L1_ICACHE0_PLD_DONE_INT_RAW_R { + L1_ICACHE0_PLD_DONE_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done."] + #[inline(always)] + pub fn l1_icache1_pld_done_int_raw(&self) -> L1_ICACHE1_PLD_DONE_INT_RAW_R { + L1_ICACHE1_PLD_DONE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_pld_done_int_raw(&self) -> L1_ICACHE2_PLD_DONE_INT_RAW_R { + L1_ICACHE2_PLD_DONE_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_pld_done_int_raw(&self) -> L1_ICACHE3_PLD_DONE_INT_RAW_R { + L1_ICACHE3_PLD_DONE_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done."] + #[inline(always)] + pub fn l1_dcache_pld_done_int_raw(&self) -> L1_DCACHE_PLD_DONE_INT_RAW_R { + L1_DCACHE_PLD_DONE_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - The raw bit of the interrupt that occurs only when Cache sync-operation is done."] + #[inline(always)] + pub fn sync_done_int_raw(&self) -> SYNC_DONE_INT_RAW_R { + SYNC_DONE_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs."] + #[inline(always)] + pub fn l1_icache0_pld_err_int_raw(&self) -> L1_ICACHE0_PLD_ERR_INT_RAW_R { + L1_ICACHE0_PLD_ERR_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs."] + #[inline(always)] + pub fn l1_icache1_pld_err_int_raw(&self) -> L1_ICACHE1_PLD_ERR_INT_RAW_R { + L1_ICACHE1_PLD_ERR_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn l1_icache2_pld_err_int_raw(&self) -> L1_ICACHE2_PLD_ERR_INT_RAW_R { + L1_ICACHE2_PLD_ERR_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn l1_icache3_pld_err_int_raw(&self) -> L1_ICACHE3_PLD_ERR_INT_RAW_R { + L1_ICACHE3_PLD_ERR_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs."] + #[inline(always)] + pub fn l1_dcache_pld_err_int_raw(&self) -> L1_DCACHE_PLD_ERR_INT_RAW_R { + L1_DCACHE_PLD_ERR_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - The raw bit of the interrupt that occurs only when Cache sync-operation error occurs."] + #[inline(always)] + pub fn sync_err_int_raw(&self) -> SYNC_ERR_INT_RAW_R { + SYNC_ERR_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYNC_L1_CACHE_PRELOAD_INT_RAW") + .field( + "l1_icache0_pld_done_int_raw", + &format_args!("{}", self.l1_icache0_pld_done_int_raw().bit()), + ) + .field( + "l1_icache1_pld_done_int_raw", + &format_args!("{}", self.l1_icache1_pld_done_int_raw().bit()), + ) + .field( + "l1_icache2_pld_done_int_raw", + &format_args!("{}", self.l1_icache2_pld_done_int_raw().bit()), + ) + .field( + "l1_icache3_pld_done_int_raw", + &format_args!("{}", self.l1_icache3_pld_done_int_raw().bit()), + ) + .field( + "l1_dcache_pld_done_int_raw", + &format_args!("{}", self.l1_dcache_pld_done_int_raw().bit()), + ) + .field( + "sync_done_int_raw", + &format_args!("{}", self.sync_done_int_raw().bit()), + ) + .field( + "l1_icache0_pld_err_int_raw", + &format_args!("{}", self.l1_icache0_pld_err_int_raw().bit()), + ) + .field( + "l1_icache1_pld_err_int_raw", + &format_args!("{}", self.l1_icache1_pld_err_int_raw().bit()), + ) + .field( + "l1_icache2_pld_err_int_raw", + &format_args!("{}", self.l1_icache2_pld_err_int_raw().bit()), + ) + .field( + "l1_icache3_pld_err_int_raw", + &format_args!("{}", self.l1_icache3_pld_err_int_raw().bit()), + ) + .field( + "l1_dcache_pld_err_int_raw", + &format_args!("{}", self.l1_dcache_pld_err_int_raw().bit()), + ) + .field( + "sync_err_int_raw", + &format_args!("{}", self.sync_err_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_pld_done_int_raw( + &mut self, + ) -> L1_ICACHE0_PLD_DONE_INT_RAW_W { + L1_ICACHE0_PLD_DONE_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_pld_done_int_raw( + &mut self, + ) -> L1_ICACHE1_PLD_DONE_INT_RAW_W { + L1_ICACHE1_PLD_DONE_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn l1_icache2_pld_done_int_raw( + &mut self, + ) -> L1_ICACHE2_PLD_DONE_INT_RAW_W { + L1_ICACHE2_PLD_DONE_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn l1_icache3_pld_done_int_raw( + &mut self, + ) -> L1_ICACHE3_PLD_DONE_INT_RAW_W { + L1_ICACHE3_PLD_DONE_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_pld_done_int_raw( + &mut self, + ) -> L1_DCACHE_PLD_DONE_INT_RAW_W { + L1_DCACHE_PLD_DONE_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 6 - The raw bit of the interrupt that occurs only when Cache sync-operation is done."] + #[inline(always)] + #[must_use] + pub fn sync_done_int_raw(&mut self) -> SYNC_DONE_INT_RAW_W { + SYNC_DONE_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs."] + #[inline(always)] + #[must_use] + pub fn l1_icache0_pld_err_int_raw( + &mut self, + ) -> L1_ICACHE0_PLD_ERR_INT_RAW_W { + L1_ICACHE0_PLD_ERR_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs."] + #[inline(always)] + #[must_use] + pub fn l1_icache1_pld_err_int_raw( + &mut self, + ) -> L1_ICACHE1_PLD_ERR_INT_RAW_W { + L1_ICACHE1_PLD_ERR_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn l1_icache2_pld_err_int_raw( + &mut self, + ) -> L1_ICACHE2_PLD_ERR_INT_RAW_W { + L1_ICACHE2_PLD_ERR_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn l1_icache3_pld_err_int_raw( + &mut self, + ) -> L1_ICACHE3_PLD_ERR_INT_RAW_W { + L1_ICACHE3_PLD_ERR_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs."] + #[inline(always)] + #[must_use] + pub fn l1_dcache_pld_err_int_raw( + &mut self, + ) -> L1_DCACHE_PLD_ERR_INT_RAW_W { + L1_DCACHE_PLD_ERR_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 13 - The raw bit of the interrupt that occurs only when Cache sync-operation error occurs."] + #[inline(always)] + #[must_use] + pub fn sync_err_int_raw(&mut self) -> SYNC_ERR_INT_RAW_W { + SYNC_ERR_INT_RAW_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Sync Preload operation Interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_l1_cache_preload_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC; +impl crate::RegisterSpec for SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sync_l1_cache_preload_int_raw::R`](R) reader structure"] +impl crate::Readable for SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sync_l1_cache_preload_int_raw::W`](W) writer structure"] +impl crate::Writable for SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYNC_L1_CACHE_PRELOAD_INT_RAW to value 0"] +impl crate::Resettable for SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/sync_l1_cache_preload_int_st.rs b/esp32p4/src/cache/sync_l1_cache_preload_int_st.rs new file mode 100644 index 0000000000..1f59690fde --- /dev/null +++ b/esp32p4/src/cache/sync_l1_cache_preload_int_st.rs @@ -0,0 +1,160 @@ +#[doc = "Register `SYNC_L1_CACHE_PRELOAD_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `L1_ICACHE0_PLD_DONE_INT_ST` reader - The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done."] +pub type L1_ICACHE0_PLD_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PLD_DONE_INT_ST` reader - The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done."] +pub type L1_ICACHE1_PLD_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_PLD_DONE_INT_ST` reader - Reserved"] +pub type L1_ICACHE2_PLD_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PLD_DONE_INT_ST` reader - Reserved"] +pub type L1_ICACHE3_PLD_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_DONE_INT_ST` reader - The bit indicates the status of the interrupt that occurs only when L1-DCache preload-operation is done."] +pub type L1_DCACHE_PLD_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SYNC_DONE_INT_ST` reader - The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done."] +pub type SYNC_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE0_PLD_ERR_INT_ST` reader - The bit indicates the status of the interrupt of L1-ICache0 preload-operation error."] +pub type L1_ICACHE0_PLD_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE1_PLD_ERR_INT_ST` reader - The bit indicates the status of the interrupt of L1-ICache1 preload-operation error."] +pub type L1_ICACHE1_PLD_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE2_PLD_ERR_INT_ST` reader - Reserved"] +pub type L1_ICACHE2_PLD_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_ICACHE3_PLD_ERR_INT_ST` reader - Reserved"] +pub type L1_ICACHE3_PLD_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `L1_DCACHE_PLD_ERR_INT_ST` reader - The bit indicates the status of the interrupt of L1-DCache preload-operation error."] +pub type L1_DCACHE_PLD_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SYNC_ERR_INT_ST` reader - The bit indicates the status of the interrupt of Cache sync-operation error."] +pub type SYNC_ERR_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done."] + #[inline(always)] + pub fn l1_icache0_pld_done_int_st(&self) -> L1_ICACHE0_PLD_DONE_INT_ST_R { + L1_ICACHE0_PLD_DONE_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done."] + #[inline(always)] + pub fn l1_icache1_pld_done_int_st(&self) -> L1_ICACHE1_PLD_DONE_INT_ST_R { + L1_ICACHE1_PLD_DONE_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn l1_icache2_pld_done_int_st(&self) -> L1_ICACHE2_PLD_DONE_INT_ST_R { + L1_ICACHE2_PLD_DONE_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn l1_icache3_pld_done_int_st(&self) -> L1_ICACHE3_PLD_DONE_INT_ST_R { + L1_ICACHE3_PLD_DONE_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The bit indicates the status of the interrupt that occurs only when L1-DCache preload-operation is done."] + #[inline(always)] + pub fn l1_dcache_pld_done_int_st(&self) -> L1_DCACHE_PLD_DONE_INT_ST_R { + L1_DCACHE_PLD_DONE_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done."] + #[inline(always)] + pub fn sync_done_int_st(&self) -> SYNC_DONE_INT_ST_R { + SYNC_DONE_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The bit indicates the status of the interrupt of L1-ICache0 preload-operation error."] + #[inline(always)] + pub fn l1_icache0_pld_err_int_st(&self) -> L1_ICACHE0_PLD_ERR_INT_ST_R { + L1_ICACHE0_PLD_ERR_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The bit indicates the status of the interrupt of L1-ICache1 preload-operation error."] + #[inline(always)] + pub fn l1_icache1_pld_err_int_st(&self) -> L1_ICACHE1_PLD_ERR_INT_ST_R { + L1_ICACHE1_PLD_ERR_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn l1_icache2_pld_err_int_st(&self) -> L1_ICACHE2_PLD_ERR_INT_ST_R { + L1_ICACHE2_PLD_ERR_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn l1_icache3_pld_err_int_st(&self) -> L1_ICACHE3_PLD_ERR_INT_ST_R { + L1_ICACHE3_PLD_ERR_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The bit indicates the status of the interrupt of L1-DCache preload-operation error."] + #[inline(always)] + pub fn l1_dcache_pld_err_int_st(&self) -> L1_DCACHE_PLD_ERR_INT_ST_R { + L1_DCACHE_PLD_ERR_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - The bit indicates the status of the interrupt of Cache sync-operation error."] + #[inline(always)] + pub fn sync_err_int_st(&self) -> SYNC_ERR_INT_ST_R { + SYNC_ERR_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYNC_L1_CACHE_PRELOAD_INT_ST") + .field( + "l1_icache0_pld_done_int_st", + &format_args!("{}", self.l1_icache0_pld_done_int_st().bit()), + ) + .field( + "l1_icache1_pld_done_int_st", + &format_args!("{}", self.l1_icache1_pld_done_int_st().bit()), + ) + .field( + "l1_icache2_pld_done_int_st", + &format_args!("{}", self.l1_icache2_pld_done_int_st().bit()), + ) + .field( + "l1_icache3_pld_done_int_st", + &format_args!("{}", self.l1_icache3_pld_done_int_st().bit()), + ) + .field( + "l1_dcache_pld_done_int_st", + &format_args!("{}", self.l1_dcache_pld_done_int_st().bit()), + ) + .field( + "sync_done_int_st", + &format_args!("{}", self.sync_done_int_st().bit()), + ) + .field( + "l1_icache0_pld_err_int_st", + &format_args!("{}", self.l1_icache0_pld_err_int_st().bit()), + ) + .field( + "l1_icache1_pld_err_int_st", + &format_args!("{}", self.l1_icache1_pld_err_int_st().bit()), + ) + .field( + "l1_icache2_pld_err_int_st", + &format_args!("{}", self.l1_icache2_pld_err_int_st().bit()), + ) + .field( + "l1_icache3_pld_err_int_st", + &format_args!("{}", self.l1_icache3_pld_err_int_st().bit()), + ) + .field( + "l1_dcache_pld_err_int_st", + &format_args!("{}", self.l1_dcache_pld_err_int_st().bit()), + ) + .field( + "sync_err_int_st", + &format_args!("{}", self.sync_err_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC; +impl crate::RegisterSpec for SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sync_l1_cache_preload_int_st::R`](R) reader structure"] +impl crate::Readable for SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC {} +#[doc = "`reset()` method sets SYNC_L1_CACHE_PRELOAD_INT_ST to value 0"] +impl crate::Resettable for SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/cache/sync_map.rs b/esp32p4/src/cache/sync_map.rs new file mode 100644 index 0000000000..a80a81e408 --- /dev/null +++ b/esp32p4/src/cache/sync_map.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SYNC_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SYNC_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `SYNC_MAP` reader - Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. \\[0\\]: L1-ICache0, \\[1\\]: L1-ICache1, \\[2\\]: L1-ICache2, \\[3\\]: L1-ICache3, \\[4\\]: L1-DCache, \\[5\\]: L2-Cache."] +pub type SYNC_MAP_R = crate::FieldReader; +#[doc = "Field `SYNC_MAP` writer - Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. \\[0\\]: L1-ICache0, \\[1\\]: L1-ICache1, \\[2\\]: L1-ICache2, \\[3\\]: L1-ICache3, \\[4\\]: L1-DCache, \\[5\\]: L2-Cache."] +pub type SYNC_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. \\[0\\]: L1-ICache0, \\[1\\]: L1-ICache1, \\[2\\]: L1-ICache2, \\[3\\]: L1-ICache3, \\[4\\]: L1-DCache, \\[5\\]: L2-Cache."] + #[inline(always)] + pub fn sync_map(&self) -> SYNC_MAP_R { + SYNC_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYNC_MAP") + .field("sync_map", &format_args!("{}", self.sync_map().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. \\[0\\]: L1-ICache0, \\[1\\]: L1-ICache1, \\[2\\]: L1-ICache2, \\[3\\]: L1-ICache3, \\[4\\]: L1-DCache, \\[5\\]: L2-Cache."] + #[inline(always)] + #[must_use] + pub fn sync_map(&mut self) -> SYNC_MAP_W { + SYNC_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Sync map configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYNC_MAP_SPEC; +impl crate::RegisterSpec for SYNC_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sync_map::R`](R) reader structure"] +impl crate::Readable for SYNC_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sync_map::W`](W) writer structure"] +impl crate::Writable for SYNC_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYNC_MAP to value 0x1f"] +impl crate::Resettable for SYNC_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0x1f; +} diff --git a/esp32p4/src/cache/sync_size.rs b/esp32p4/src/cache/sync_size.rs new file mode 100644 index 0000000000..6e8f8fd7cb --- /dev/null +++ b/esp32p4/src/cache/sync_size.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SYNC_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `SYNC_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `SYNC_SIZE` reader - Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG"] +pub type SYNC_SIZE_R = crate::FieldReader; +#[doc = "Field `SYNC_SIZE` writer - Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG"] +pub type SYNC_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG"] + #[inline(always)] + pub fn sync_size(&self) -> SYNC_SIZE_R { + SYNC_SIZE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYNC_SIZE") + .field("sync_size", &format_args!("{}", self.sync_size().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG"] + #[inline(always)] + #[must_use] + pub fn sync_size(&mut self) -> SYNC_SIZE_W { + SYNC_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Sync size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYNC_SIZE_SPEC; +impl crate::RegisterSpec for SYNC_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sync_size::R`](R) reader structure"] +impl crate::Readable for SYNC_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sync_size::W`](W) writer structure"] +impl crate::Writable for SYNC_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYNC_SIZE to value 0"] +impl crate::Resettable for SYNC_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma.rs b/esp32p4/src/dma.rs new file mode 100644 index 0000000000..a78d264d0f --- /dev/null +++ b/esp32p4/src/dma.rs @@ -0,0 +1,1465 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + id0: ID0, + _reserved1: [u8; 0x04], + compver0: COMPVER0, + _reserved2: [u8; 0x04], + cfg0: CFG0, + _reserved3: [u8; 0x04], + chen0: CHEN0, + chen1: CHEN1, + _reserved5: [u8; 0x10], + intstatus0: INTSTATUS0, + _reserved6: [u8; 0x04], + commonreg_intclear0: COMMONREG_INTCLEAR0, + _reserved7: [u8; 0x04], + commonreg_intstatus_enable0: COMMONREG_INTSTATUS_ENABLE0, + _reserved8: [u8; 0x04], + commonreg_intsignal_enable0: COMMONREG_INTSIGNAL_ENABLE0, + _reserved9: [u8; 0x04], + commonreg_intstatus0: COMMONREG_INTSTATUS0, + _reserved10: [u8; 0x04], + reset0: RESET0, + _reserved11: [u8; 0x04], + lowpower_cfg0: LOWPOWER_CFG0, + lowpower_cfg1: LOWPOWER_CFG1, + _reserved13: [u8; 0x98], + ch1_sar0: CH1_SAR0, + ch1_sar1: CH1_SAR1, + ch1_dar0: CH1_DAR0, + ch1_dar1: CH1_DAR1, + ch1_block_ts0: CH1_BLOCK_TS0, + _reserved18: [u8; 0x04], + ch1_ctl0: CH1_CTL0, + ch1_ctl1: CH1_CTL1, + ch1_cfg0: CH1_CFG0, + ch1_cfg1: CH1_CFG1, + ch1_llp0: CH1_LLP0, + ch1_llp1: CH1_LLP1, + ch1_status0: CH1_STATUS0, + ch1_status1: CH1_STATUS1, + ch1_swhssrc0: CH1_SWHSSRC0, + _reserved27: [u8; 0x04], + ch1_swhsdst0: CH1_SWHSDST0, + _reserved28: [u8; 0x04], + ch1_blk_tfr_resumereq0: CH1_BLK_TFR_RESUMEREQ0, + _reserved29: [u8; 0x04], + ch1_axi_id0: CH1_AXI_ID0, + _reserved30: [u8; 0x04], + ch1_axi_qos0: CH1_AXI_QOS0, + _reserved31: [u8; 0x04], + ch1_sstat0: CH1_SSTAT0, + _reserved32: [u8; 0x04], + ch1_dstat0: CH1_DSTAT0, + _reserved33: [u8; 0x04], + ch1_sstatar0: CH1_SSTATAR0, + ch1_sstatar1: CH1_SSTATAR1, + ch1_dstatar0: CH1_DSTATAR0, + ch1_dstatar1: CH1_DSTATAR1, + ch1_intstatus_enable0: CH1_INTSTATUS_ENABLE0, + ch1_intstatus_enable1: CH1_INTSTATUS_ENABLE1, + ch1_intstatus0: CH1_INTSTATUS0, + ch1_intstatus1: CH1_INTSTATUS1, + ch1_intsignal_enable0: CH1_INTSIGNAL_ENABLE0, + ch1_intsignal_enable1: CH1_INTSIGNAL_ENABLE1, + ch1_intclear0: CH1_INTCLEAR0, + ch1_intclear1: CH1_INTCLEAR1, + _reserved45: [u8; 0x60], + ch2_sar0: CH2_SAR0, + ch2_sar1: CH2_SAR1, + ch2_dar0: CH2_DAR0, + ch2_dar1: CH2_DAR1, + ch2_block_ts0: CH2_BLOCK_TS0, + _reserved50: [u8; 0x04], + ch2_ctl0: CH2_CTL0, + ch2_ctl1: CH2_CTL1, + ch2_cfg0: CH2_CFG0, + ch2_cfg1: CH2_CFG1, + ch2_llp0: CH2_LLP0, + ch2_llp1: CH2_LLP1, + ch2_status0: CH2_STATUS0, + ch2_status1: CH2_STATUS1, + ch2_swhssrc0: CH2_SWHSSRC0, + _reserved59: [u8; 0x04], + ch2_swhsdst0: CH2_SWHSDST0, + _reserved60: [u8; 0x04], + ch2_blk_tfr_resumereq0: CH2_BLK_TFR_RESUMEREQ0, + _reserved61: [u8; 0x04], + ch2_axi_id0: CH2_AXI_ID0, + _reserved62: [u8; 0x04], + ch2_axi_qos0: CH2_AXI_QOS0, + _reserved63: [u8; 0x04], + ch2_sstat0: CH2_SSTAT0, + _reserved64: [u8; 0x04], + ch2_dstat0: CH2_DSTAT0, + _reserved65: [u8; 0x04], + ch2_sstatar0: CH2_SSTATAR0, + ch2_sstatar1: CH2_SSTATAR1, + ch2_dstatar0: CH2_DSTATAR0, + ch2_dstatar1: CH2_DSTATAR1, + ch2_intstatus_enable0: CH2_INTSTATUS_ENABLE0, + ch2_intstatus_enable1: CH2_INTSTATUS_ENABLE1, + ch2_intstatus0: CH2_INTSTATUS0, + ch2_intstatus1: CH2_INTSTATUS1, + ch2_intsignal_enable0: CH2_INTSIGNAL_ENABLE0, + ch2_intsignal_enable1: CH2_INTSIGNAL_ENABLE1, + ch2_intclear0: CH2_INTCLEAR0, + ch2_intclear1: CH2_INTCLEAR1, + _reserved77: [u8; 0x60], + ch3_sar0: CH3_SAR0, + ch3_sar1: CH3_SAR1, + ch3_dar0: CH3_DAR0, + ch3_dar1: CH3_DAR1, + ch3_block_ts0: CH3_BLOCK_TS0, + _reserved82: [u8; 0x04], + ch3_ctl0: CH3_CTL0, + ch3_ctl1: CH3_CTL1, + ch3_cfg0: CH3_CFG0, + ch3_cfg1: CH3_CFG1, + ch3_llp0: CH3_LLP0, + ch3_llp1: CH3_LLP1, + ch3_status0: CH3_STATUS0, + ch3_status1: CH3_STATUS1, + ch3_swhssrc0: CH3_SWHSSRC0, + _reserved91: [u8; 0x04], + ch3_swhsdst0: CH3_SWHSDST0, + _reserved92: [u8; 0x04], + ch3_blk_tfr_resumereq0: CH3_BLK_TFR_RESUMEREQ0, + _reserved93: [u8; 0x04], + ch3_axi_id0: CH3_AXI_ID0, + _reserved94: [u8; 0x04], + ch3_axi_qos0: CH3_AXI_QOS0, + _reserved95: [u8; 0x04], + ch3_sstat0: CH3_SSTAT0, + _reserved96: [u8; 0x04], + ch3_dstat0: CH3_DSTAT0, + _reserved97: [u8; 0x04], + ch3_sstatar0: CH3_SSTATAR0, + ch3_sstatar1: CH3_SSTATAR1, + ch3_dstatar0: CH3_DSTATAR0, + ch3_dstatar1: CH3_DSTATAR1, + ch3_intstatus_enable0: CH3_INTSTATUS_ENABLE0, + ch3_intstatus_enable1: CH3_INTSTATUS_ENABLE1, + ch3_intstatus0: CH3_INTSTATUS0, + ch3_intstatus1: CH3_INTSTATUS1, + ch3_intsignal_enable0: CH3_INTSIGNAL_ENABLE0, + ch3_intsignal_enable1: CH3_INTSIGNAL_ENABLE1, + ch3_intclear0: CH3_INTCLEAR0, + ch3_intclear1: CH3_INTCLEAR1, + _reserved109: [u8; 0x60], + ch4_sar0: CH4_SAR0, + ch4_sar1: CH4_SAR1, + ch4_dar0: CH4_DAR0, + ch4_dar1: CH4_DAR1, + ch4_block_ts0: CH4_BLOCK_TS0, + _reserved114: [u8; 0x04], + ch4_ctl0: CH4_CTL0, + ch4_ctl1: CH4_CTL1, + ch4_cfg0: CH4_CFG0, + ch4_cfg1: CH4_CFG1, + ch4_llp0: CH4_LLP0, + ch4_llp1: CH4_LLP1, + ch4_status0: CH4_STATUS0, + ch4_status1: CH4_STATUS1, + ch4_swhssrc0: CH4_SWHSSRC0, + _reserved123: [u8; 0x04], + ch4_swhsdst0: CH4_SWHSDST0, + _reserved124: [u8; 0x04], + ch4_blk_tfr_resumereq0: CH4_BLK_TFR_RESUMEREQ0, + _reserved125: [u8; 0x04], + ch4_axi_id0: CH4_AXI_ID0, + _reserved126: [u8; 0x04], + ch4_axi_qos0: CH4_AXI_QOS0, + _reserved127: [u8; 0x04], + ch4_sstat0: CH4_SSTAT0, + _reserved128: [u8; 0x04], + ch4_dstat0: CH4_DSTAT0, + _reserved129: [u8; 0x04], + ch4_sstatar0: CH4_SSTATAR0, + ch4_sstatar1: CH4_SSTATAR1, + ch4_dstatar0: CH4_DSTATAR0, + ch4_dstatar1: CH4_DSTATAR1, + ch4_intstatus_enable0: CH4_INTSTATUS_ENABLE0, + ch4_intstatus_enable1: CH4_INTSTATUS_ENABLE1, + ch4_intstatus0: CH4_INTSTATUS0, + ch4_intstatus1: CH4_INTSTATUS1, + ch4_intsignal_enable0: CH4_INTSIGNAL_ENABLE0, + ch4_intsignal_enable1: CH4_INTSIGNAL_ENABLE1, + ch4_intclear0: CH4_INTCLEAR0, + ch4_intclear1: CH4_INTCLEAR1, +} +impl RegisterBlock { + #[doc = "0x00 - NA"] + #[inline(always)] + pub const fn id0(&self) -> &ID0 { + &self.id0 + } + #[doc = "0x08 - NA"] + #[inline(always)] + pub const fn compver0(&self) -> &COMPVER0 { + &self.compver0 + } + #[doc = "0x10 - NA"] + #[inline(always)] + pub const fn cfg0(&self) -> &CFG0 { + &self.cfg0 + } + #[doc = "0x18 - NA"] + #[inline(always)] + pub const fn chen0(&self) -> &CHEN0 { + &self.chen0 + } + #[doc = "0x1c - NA"] + #[inline(always)] + pub const fn chen1(&self) -> &CHEN1 { + &self.chen1 + } + #[doc = "0x30 - NA"] + #[inline(always)] + pub const fn intstatus0(&self) -> &INTSTATUS0 { + &self.intstatus0 + } + #[doc = "0x38 - NA"] + #[inline(always)] + pub const fn commonreg_intclear0(&self) -> &COMMONREG_INTCLEAR0 { + &self.commonreg_intclear0 + } + #[doc = "0x40 - NA"] + #[inline(always)] + pub const fn commonreg_intstatus_enable0(&self) -> &COMMONREG_INTSTATUS_ENABLE0 { + &self.commonreg_intstatus_enable0 + } + #[doc = "0x48 - NA"] + #[inline(always)] + pub const fn commonreg_intsignal_enable0(&self) -> &COMMONREG_INTSIGNAL_ENABLE0 { + &self.commonreg_intsignal_enable0 + } + #[doc = "0x50 - NA"] + #[inline(always)] + pub const fn commonreg_intstatus0(&self) -> &COMMONREG_INTSTATUS0 { + &self.commonreg_intstatus0 + } + #[doc = "0x58 - NA"] + #[inline(always)] + pub const fn reset0(&self) -> &RESET0 { + &self.reset0 + } + #[doc = "0x60 - NA"] + #[inline(always)] + pub const fn lowpower_cfg0(&self) -> &LOWPOWER_CFG0 { + &self.lowpower_cfg0 + } + #[doc = "0x64 - NA"] + #[inline(always)] + pub const fn lowpower_cfg1(&self) -> &LOWPOWER_CFG1 { + &self.lowpower_cfg1 + } + #[doc = "0x100 - NA"] + #[inline(always)] + pub const fn ch1_sar0(&self) -> &CH1_SAR0 { + &self.ch1_sar0 + } + #[doc = "0x104 - NA"] + #[inline(always)] + pub const fn ch1_sar1(&self) -> &CH1_SAR1 { + &self.ch1_sar1 + } + #[doc = "0x108 - NA"] + #[inline(always)] + pub const fn ch1_dar0(&self) -> &CH1_DAR0 { + &self.ch1_dar0 + } + #[doc = "0x10c - NA"] + #[inline(always)] + pub const fn ch1_dar1(&self) -> &CH1_DAR1 { + &self.ch1_dar1 + } + #[doc = "0x110 - NA"] + #[inline(always)] + pub const fn ch1_block_ts0(&self) -> &CH1_BLOCK_TS0 { + &self.ch1_block_ts0 + } + #[doc = "0x118 - NA"] + #[inline(always)] + pub const fn ch1_ctl0(&self) -> &CH1_CTL0 { + &self.ch1_ctl0 + } + #[doc = "0x11c - NA"] + #[inline(always)] + pub const fn ch1_ctl1(&self) -> &CH1_CTL1 { + &self.ch1_ctl1 + } + #[doc = "0x120 - NA"] + #[inline(always)] + pub const fn ch1_cfg0(&self) -> &CH1_CFG0 { + &self.ch1_cfg0 + } + #[doc = "0x124 - NA"] + #[inline(always)] + pub const fn ch1_cfg1(&self) -> &CH1_CFG1 { + &self.ch1_cfg1 + } + #[doc = "0x128 - NA"] + #[inline(always)] + pub const fn ch1_llp0(&self) -> &CH1_LLP0 { + &self.ch1_llp0 + } + #[doc = "0x12c - NA"] + #[inline(always)] + pub const fn ch1_llp1(&self) -> &CH1_LLP1 { + &self.ch1_llp1 + } + #[doc = "0x130 - NA"] + #[inline(always)] + pub const fn ch1_status0(&self) -> &CH1_STATUS0 { + &self.ch1_status0 + } + #[doc = "0x134 - NA"] + #[inline(always)] + pub const fn ch1_status1(&self) -> &CH1_STATUS1 { + &self.ch1_status1 + } + #[doc = "0x138 - NA"] + #[inline(always)] + pub const fn ch1_swhssrc0(&self) -> &CH1_SWHSSRC0 { + &self.ch1_swhssrc0 + } + #[doc = "0x140 - NA"] + #[inline(always)] + pub const fn ch1_swhsdst0(&self) -> &CH1_SWHSDST0 { + &self.ch1_swhsdst0 + } + #[doc = "0x148 - NA"] + #[inline(always)] + pub const fn ch1_blk_tfr_resumereq0(&self) -> &CH1_BLK_TFR_RESUMEREQ0 { + &self.ch1_blk_tfr_resumereq0 + } + #[doc = "0x150 - NA"] + #[inline(always)] + pub const fn ch1_axi_id0(&self) -> &CH1_AXI_ID0 { + &self.ch1_axi_id0 + } + #[doc = "0x158 - NA"] + #[inline(always)] + pub const fn ch1_axi_qos0(&self) -> &CH1_AXI_QOS0 { + &self.ch1_axi_qos0 + } + #[doc = "0x160 - NA"] + #[inline(always)] + pub const fn ch1_sstat0(&self) -> &CH1_SSTAT0 { + &self.ch1_sstat0 + } + #[doc = "0x168 - NA"] + #[inline(always)] + pub const fn ch1_dstat0(&self) -> &CH1_DSTAT0 { + &self.ch1_dstat0 + } + #[doc = "0x170 - NA"] + #[inline(always)] + pub const fn ch1_sstatar0(&self) -> &CH1_SSTATAR0 { + &self.ch1_sstatar0 + } + #[doc = "0x174 - NA"] + #[inline(always)] + pub const fn ch1_sstatar1(&self) -> &CH1_SSTATAR1 { + &self.ch1_sstatar1 + } + #[doc = "0x178 - NA"] + #[inline(always)] + pub const fn ch1_dstatar0(&self) -> &CH1_DSTATAR0 { + &self.ch1_dstatar0 + } + #[doc = "0x17c - NA"] + #[inline(always)] + pub const fn ch1_dstatar1(&self) -> &CH1_DSTATAR1 { + &self.ch1_dstatar1 + } + #[doc = "0x180 - NA"] + #[inline(always)] + pub const fn ch1_intstatus_enable0(&self) -> &CH1_INTSTATUS_ENABLE0 { + &self.ch1_intstatus_enable0 + } + #[doc = "0x184 - NA"] + #[inline(always)] + pub const fn ch1_intstatus_enable1(&self) -> &CH1_INTSTATUS_ENABLE1 { + &self.ch1_intstatus_enable1 + } + #[doc = "0x188 - NA"] + #[inline(always)] + pub const fn ch1_intstatus0(&self) -> &CH1_INTSTATUS0 { + &self.ch1_intstatus0 + } + #[doc = "0x18c - NA"] + #[inline(always)] + pub const fn ch1_intstatus1(&self) -> &CH1_INTSTATUS1 { + &self.ch1_intstatus1 + } + #[doc = "0x190 - NA"] + #[inline(always)] + pub const fn ch1_intsignal_enable0(&self) -> &CH1_INTSIGNAL_ENABLE0 { + &self.ch1_intsignal_enable0 + } + #[doc = "0x194 - NA"] + #[inline(always)] + pub const fn ch1_intsignal_enable1(&self) -> &CH1_INTSIGNAL_ENABLE1 { + &self.ch1_intsignal_enable1 + } + #[doc = "0x198 - NA"] + #[inline(always)] + pub const fn ch1_intclear0(&self) -> &CH1_INTCLEAR0 { + &self.ch1_intclear0 + } + #[doc = "0x19c - NA"] + #[inline(always)] + pub const fn ch1_intclear1(&self) -> &CH1_INTCLEAR1 { + &self.ch1_intclear1 + } + #[doc = "0x200 - NA"] + #[inline(always)] + pub const fn ch2_sar0(&self) -> &CH2_SAR0 { + &self.ch2_sar0 + } + #[doc = "0x204 - NA"] + #[inline(always)] + pub const fn ch2_sar1(&self) -> &CH2_SAR1 { + &self.ch2_sar1 + } + #[doc = "0x208 - NA"] + #[inline(always)] + pub const fn ch2_dar0(&self) -> &CH2_DAR0 { + &self.ch2_dar0 + } + #[doc = "0x20c - NA"] + #[inline(always)] + pub const fn ch2_dar1(&self) -> &CH2_DAR1 { + &self.ch2_dar1 + } + #[doc = "0x210 - NA"] + #[inline(always)] + pub const fn ch2_block_ts0(&self) -> &CH2_BLOCK_TS0 { + &self.ch2_block_ts0 + } + #[doc = "0x218 - NA"] + #[inline(always)] + pub const fn ch2_ctl0(&self) -> &CH2_CTL0 { + &self.ch2_ctl0 + } + #[doc = "0x21c - NA"] + #[inline(always)] + pub const fn ch2_ctl1(&self) -> &CH2_CTL1 { + &self.ch2_ctl1 + } + #[doc = "0x220 - NA"] + #[inline(always)] + pub const fn ch2_cfg0(&self) -> &CH2_CFG0 { + &self.ch2_cfg0 + } + #[doc = "0x224 - NA"] + #[inline(always)] + pub const fn ch2_cfg1(&self) -> &CH2_CFG1 { + &self.ch2_cfg1 + } + #[doc = "0x228 - NA"] + #[inline(always)] + pub const fn ch2_llp0(&self) -> &CH2_LLP0 { + &self.ch2_llp0 + } + #[doc = "0x22c - NA"] + #[inline(always)] + pub const fn ch2_llp1(&self) -> &CH2_LLP1 { + &self.ch2_llp1 + } + #[doc = "0x230 - NA"] + #[inline(always)] + pub const fn ch2_status0(&self) -> &CH2_STATUS0 { + &self.ch2_status0 + } + #[doc = "0x234 - NA"] + #[inline(always)] + pub const fn ch2_status1(&self) -> &CH2_STATUS1 { + &self.ch2_status1 + } + #[doc = "0x238 - NA"] + #[inline(always)] + pub const fn ch2_swhssrc0(&self) -> &CH2_SWHSSRC0 { + &self.ch2_swhssrc0 + } + #[doc = "0x240 - NA"] + #[inline(always)] + pub const fn ch2_swhsdst0(&self) -> &CH2_SWHSDST0 { + &self.ch2_swhsdst0 + } + #[doc = "0x248 - NA"] + #[inline(always)] + pub const fn ch2_blk_tfr_resumereq0(&self) -> &CH2_BLK_TFR_RESUMEREQ0 { + &self.ch2_blk_tfr_resumereq0 + } + #[doc = "0x250 - NA"] + #[inline(always)] + pub const fn ch2_axi_id0(&self) -> &CH2_AXI_ID0 { + &self.ch2_axi_id0 + } + #[doc = "0x258 - NA"] + #[inline(always)] + pub const fn ch2_axi_qos0(&self) -> &CH2_AXI_QOS0 { + &self.ch2_axi_qos0 + } + #[doc = "0x260 - NA"] + #[inline(always)] + pub const fn ch2_sstat0(&self) -> &CH2_SSTAT0 { + &self.ch2_sstat0 + } + #[doc = "0x268 - NA"] + #[inline(always)] + pub const fn ch2_dstat0(&self) -> &CH2_DSTAT0 { + &self.ch2_dstat0 + } + #[doc = "0x270 - NA"] + #[inline(always)] + pub const fn ch2_sstatar0(&self) -> &CH2_SSTATAR0 { + &self.ch2_sstatar0 + } + #[doc = "0x274 - NA"] + #[inline(always)] + pub const fn ch2_sstatar1(&self) -> &CH2_SSTATAR1 { + &self.ch2_sstatar1 + } + #[doc = "0x278 - NA"] + #[inline(always)] + pub const fn ch2_dstatar0(&self) -> &CH2_DSTATAR0 { + &self.ch2_dstatar0 + } + #[doc = "0x27c - NA"] + #[inline(always)] + pub const fn ch2_dstatar1(&self) -> &CH2_DSTATAR1 { + &self.ch2_dstatar1 + } + #[doc = "0x280 - NA"] + #[inline(always)] + pub const fn ch2_intstatus_enable0(&self) -> &CH2_INTSTATUS_ENABLE0 { + &self.ch2_intstatus_enable0 + } + #[doc = "0x284 - NA"] + #[inline(always)] + pub const fn ch2_intstatus_enable1(&self) -> &CH2_INTSTATUS_ENABLE1 { + &self.ch2_intstatus_enable1 + } + #[doc = "0x288 - NA"] + #[inline(always)] + pub const fn ch2_intstatus0(&self) -> &CH2_INTSTATUS0 { + &self.ch2_intstatus0 + } + #[doc = "0x28c - NA"] + #[inline(always)] + pub const fn ch2_intstatus1(&self) -> &CH2_INTSTATUS1 { + &self.ch2_intstatus1 + } + #[doc = "0x290 - NA"] + #[inline(always)] + pub const fn ch2_intsignal_enable0(&self) -> &CH2_INTSIGNAL_ENABLE0 { + &self.ch2_intsignal_enable0 + } + #[doc = "0x294 - NA"] + #[inline(always)] + pub const fn ch2_intsignal_enable1(&self) -> &CH2_INTSIGNAL_ENABLE1 { + &self.ch2_intsignal_enable1 + } + #[doc = "0x298 - NA"] + #[inline(always)] + pub const fn ch2_intclear0(&self) -> &CH2_INTCLEAR0 { + &self.ch2_intclear0 + } + #[doc = "0x29c - NA"] + #[inline(always)] + pub const fn ch2_intclear1(&self) -> &CH2_INTCLEAR1 { + &self.ch2_intclear1 + } + #[doc = "0x300 - NA"] + #[inline(always)] + pub const fn ch3_sar0(&self) -> &CH3_SAR0 { + &self.ch3_sar0 + } + #[doc = "0x304 - NA"] + #[inline(always)] + pub const fn ch3_sar1(&self) -> &CH3_SAR1 { + &self.ch3_sar1 + } + #[doc = "0x308 - NA"] + #[inline(always)] + pub const fn ch3_dar0(&self) -> &CH3_DAR0 { + &self.ch3_dar0 + } + #[doc = "0x30c - NA"] + #[inline(always)] + pub const fn ch3_dar1(&self) -> &CH3_DAR1 { + &self.ch3_dar1 + } + #[doc = "0x310 - NA"] + #[inline(always)] + pub const fn ch3_block_ts0(&self) -> &CH3_BLOCK_TS0 { + &self.ch3_block_ts0 + } + #[doc = "0x318 - NA"] + #[inline(always)] + pub const fn ch3_ctl0(&self) -> &CH3_CTL0 { + &self.ch3_ctl0 + } + #[doc = "0x31c - NA"] + #[inline(always)] + pub const fn ch3_ctl1(&self) -> &CH3_CTL1 { + &self.ch3_ctl1 + } + #[doc = "0x320 - NA"] + #[inline(always)] + pub const fn ch3_cfg0(&self) -> &CH3_CFG0 { + &self.ch3_cfg0 + } + #[doc = "0x324 - NA"] + #[inline(always)] + pub const fn ch3_cfg1(&self) -> &CH3_CFG1 { + &self.ch3_cfg1 + } + #[doc = "0x328 - NA"] + #[inline(always)] + pub const fn ch3_llp0(&self) -> &CH3_LLP0 { + &self.ch3_llp0 + } + #[doc = "0x32c - NA"] + #[inline(always)] + pub const fn ch3_llp1(&self) -> &CH3_LLP1 { + &self.ch3_llp1 + } + #[doc = "0x330 - NA"] + #[inline(always)] + pub const fn ch3_status0(&self) -> &CH3_STATUS0 { + &self.ch3_status0 + } + #[doc = "0x334 - NA"] + #[inline(always)] + pub const fn ch3_status1(&self) -> &CH3_STATUS1 { + &self.ch3_status1 + } + #[doc = "0x338 - NA"] + #[inline(always)] + pub const fn ch3_swhssrc0(&self) -> &CH3_SWHSSRC0 { + &self.ch3_swhssrc0 + } + #[doc = "0x340 - NA"] + #[inline(always)] + pub const fn ch3_swhsdst0(&self) -> &CH3_SWHSDST0 { + &self.ch3_swhsdst0 + } + #[doc = "0x348 - NA"] + #[inline(always)] + pub const fn ch3_blk_tfr_resumereq0(&self) -> &CH3_BLK_TFR_RESUMEREQ0 { + &self.ch3_blk_tfr_resumereq0 + } + #[doc = "0x350 - NA"] + #[inline(always)] + pub const fn ch3_axi_id0(&self) -> &CH3_AXI_ID0 { + &self.ch3_axi_id0 + } + #[doc = "0x358 - NA"] + #[inline(always)] + pub const fn ch3_axi_qos0(&self) -> &CH3_AXI_QOS0 { + &self.ch3_axi_qos0 + } + #[doc = "0x360 - NA"] + #[inline(always)] + pub const fn ch3_sstat0(&self) -> &CH3_SSTAT0 { + &self.ch3_sstat0 + } + #[doc = "0x368 - NA"] + #[inline(always)] + pub const fn ch3_dstat0(&self) -> &CH3_DSTAT0 { + &self.ch3_dstat0 + } + #[doc = "0x370 - NA"] + #[inline(always)] + pub const fn ch3_sstatar0(&self) -> &CH3_SSTATAR0 { + &self.ch3_sstatar0 + } + #[doc = "0x374 - NA"] + #[inline(always)] + pub const fn ch3_sstatar1(&self) -> &CH3_SSTATAR1 { + &self.ch3_sstatar1 + } + #[doc = "0x378 - NA"] + #[inline(always)] + pub const fn ch3_dstatar0(&self) -> &CH3_DSTATAR0 { + &self.ch3_dstatar0 + } + #[doc = "0x37c - NA"] + #[inline(always)] + pub const fn ch3_dstatar1(&self) -> &CH3_DSTATAR1 { + &self.ch3_dstatar1 + } + #[doc = "0x380 - NA"] + #[inline(always)] + pub const fn ch3_intstatus_enable0(&self) -> &CH3_INTSTATUS_ENABLE0 { + &self.ch3_intstatus_enable0 + } + #[doc = "0x384 - NA"] + #[inline(always)] + pub const fn ch3_intstatus_enable1(&self) -> &CH3_INTSTATUS_ENABLE1 { + &self.ch3_intstatus_enable1 + } + #[doc = "0x388 - NA"] + #[inline(always)] + pub const fn ch3_intstatus0(&self) -> &CH3_INTSTATUS0 { + &self.ch3_intstatus0 + } + #[doc = "0x38c - NA"] + #[inline(always)] + pub const fn ch3_intstatus1(&self) -> &CH3_INTSTATUS1 { + &self.ch3_intstatus1 + } + #[doc = "0x390 - NA"] + #[inline(always)] + pub const fn ch3_intsignal_enable0(&self) -> &CH3_INTSIGNAL_ENABLE0 { + &self.ch3_intsignal_enable0 + } + #[doc = "0x394 - NA"] + #[inline(always)] + pub const fn ch3_intsignal_enable1(&self) -> &CH3_INTSIGNAL_ENABLE1 { + &self.ch3_intsignal_enable1 + } + #[doc = "0x398 - NA"] + #[inline(always)] + pub const fn ch3_intclear0(&self) -> &CH3_INTCLEAR0 { + &self.ch3_intclear0 + } + #[doc = "0x39c - NA"] + #[inline(always)] + pub const fn ch3_intclear1(&self) -> &CH3_INTCLEAR1 { + &self.ch3_intclear1 + } + #[doc = "0x400 - NA"] + #[inline(always)] + pub const fn ch4_sar0(&self) -> &CH4_SAR0 { + &self.ch4_sar0 + } + #[doc = "0x404 - NA"] + #[inline(always)] + pub const fn ch4_sar1(&self) -> &CH4_SAR1 { + &self.ch4_sar1 + } + #[doc = "0x408 - NA"] + #[inline(always)] + pub const fn ch4_dar0(&self) -> &CH4_DAR0 { + &self.ch4_dar0 + } + #[doc = "0x40c - NA"] + #[inline(always)] + pub const fn ch4_dar1(&self) -> &CH4_DAR1 { + &self.ch4_dar1 + } + #[doc = "0x410 - NA"] + #[inline(always)] + pub const fn ch4_block_ts0(&self) -> &CH4_BLOCK_TS0 { + &self.ch4_block_ts0 + } + #[doc = "0x418 - NA"] + #[inline(always)] + pub const fn ch4_ctl0(&self) -> &CH4_CTL0 { + &self.ch4_ctl0 + } + #[doc = "0x41c - NA"] + #[inline(always)] + pub const fn ch4_ctl1(&self) -> &CH4_CTL1 { + &self.ch4_ctl1 + } + #[doc = "0x420 - NA"] + #[inline(always)] + pub const fn ch4_cfg0(&self) -> &CH4_CFG0 { + &self.ch4_cfg0 + } + #[doc = "0x424 - NA"] + #[inline(always)] + pub const fn ch4_cfg1(&self) -> &CH4_CFG1 { + &self.ch4_cfg1 + } + #[doc = "0x428 - NA"] + #[inline(always)] + pub const fn ch4_llp0(&self) -> &CH4_LLP0 { + &self.ch4_llp0 + } + #[doc = "0x42c - NA"] + #[inline(always)] + pub const fn ch4_llp1(&self) -> &CH4_LLP1 { + &self.ch4_llp1 + } + #[doc = "0x430 - NA"] + #[inline(always)] + pub const fn ch4_status0(&self) -> &CH4_STATUS0 { + &self.ch4_status0 + } + #[doc = "0x434 - NA"] + #[inline(always)] + pub const fn ch4_status1(&self) -> &CH4_STATUS1 { + &self.ch4_status1 + } + #[doc = "0x438 - NA"] + #[inline(always)] + pub const fn ch4_swhssrc0(&self) -> &CH4_SWHSSRC0 { + &self.ch4_swhssrc0 + } + #[doc = "0x440 - NA"] + #[inline(always)] + pub const fn ch4_swhsdst0(&self) -> &CH4_SWHSDST0 { + &self.ch4_swhsdst0 + } + #[doc = "0x448 - NA"] + #[inline(always)] + pub const fn ch4_blk_tfr_resumereq0(&self) -> &CH4_BLK_TFR_RESUMEREQ0 { + &self.ch4_blk_tfr_resumereq0 + } + #[doc = "0x450 - NA"] + #[inline(always)] + pub const fn ch4_axi_id0(&self) -> &CH4_AXI_ID0 { + &self.ch4_axi_id0 + } + #[doc = "0x458 - NA"] + #[inline(always)] + pub const fn ch4_axi_qos0(&self) -> &CH4_AXI_QOS0 { + &self.ch4_axi_qos0 + } + #[doc = "0x460 - NA"] + #[inline(always)] + pub const fn ch4_sstat0(&self) -> &CH4_SSTAT0 { + &self.ch4_sstat0 + } + #[doc = "0x468 - NA"] + #[inline(always)] + pub const fn ch4_dstat0(&self) -> &CH4_DSTAT0 { + &self.ch4_dstat0 + } + #[doc = "0x470 - NA"] + #[inline(always)] + pub const fn ch4_sstatar0(&self) -> &CH4_SSTATAR0 { + &self.ch4_sstatar0 + } + #[doc = "0x474 - NA"] + #[inline(always)] + pub const fn ch4_sstatar1(&self) -> &CH4_SSTATAR1 { + &self.ch4_sstatar1 + } + #[doc = "0x478 - NA"] + #[inline(always)] + pub const fn ch4_dstatar0(&self) -> &CH4_DSTATAR0 { + &self.ch4_dstatar0 + } + #[doc = "0x47c - NA"] + #[inline(always)] + pub const fn ch4_dstatar1(&self) -> &CH4_DSTATAR1 { + &self.ch4_dstatar1 + } + #[doc = "0x480 - NA"] + #[inline(always)] + pub const fn ch4_intstatus_enable0(&self) -> &CH4_INTSTATUS_ENABLE0 { + &self.ch4_intstatus_enable0 + } + #[doc = "0x484 - NA"] + #[inline(always)] + pub const fn ch4_intstatus_enable1(&self) -> &CH4_INTSTATUS_ENABLE1 { + &self.ch4_intstatus_enable1 + } + #[doc = "0x488 - NA"] + #[inline(always)] + pub const fn ch4_intstatus0(&self) -> &CH4_INTSTATUS0 { + &self.ch4_intstatus0 + } + #[doc = "0x48c - NA"] + #[inline(always)] + pub const fn ch4_intstatus1(&self) -> &CH4_INTSTATUS1 { + &self.ch4_intstatus1 + } + #[doc = "0x490 - NA"] + #[inline(always)] + pub const fn ch4_intsignal_enable0(&self) -> &CH4_INTSIGNAL_ENABLE0 { + &self.ch4_intsignal_enable0 + } + #[doc = "0x494 - NA"] + #[inline(always)] + pub const fn ch4_intsignal_enable1(&self) -> &CH4_INTSIGNAL_ENABLE1 { + &self.ch4_intsignal_enable1 + } + #[doc = "0x498 - NA"] + #[inline(always)] + pub const fn ch4_intclear0(&self) -> &CH4_INTCLEAR0 { + &self.ch4_intclear0 + } + #[doc = "0x49c - NA"] + #[inline(always)] + pub const fn ch4_intclear1(&self) -> &CH4_INTCLEAR1 { + &self.ch4_intclear1 + } +} +#[doc = "ID0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0`] module"] +pub type ID0 = crate::Reg; +#[doc = "NA"] +pub mod id0; +#[doc = "COMPVER0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`compver0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@compver0`] module"] +pub type COMPVER0 = crate::Reg; +#[doc = "NA"] +pub mod compver0; +#[doc = "CFG0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg0`] module"] +pub type CFG0 = crate::Reg; +#[doc = "NA"] +pub mod cfg0; +#[doc = "CHEN0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chen0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chen0`] module"] +pub type CHEN0 = crate::Reg; +#[doc = "NA"] +pub mod chen0; +#[doc = "CHEN1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chen1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chen1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chen1`] module"] +pub type CHEN1 = crate::Reg; +#[doc = "NA"] +pub mod chen1; +#[doc = "INTSTATUS0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intstatus0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intstatus0`] module"] +pub type INTSTATUS0 = crate::Reg; +#[doc = "NA"] +pub mod intstatus0; +#[doc = "COMMONREG_INTCLEAR0 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`commonreg_intclear0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@commonreg_intclear0`] module"] +pub type COMMONREG_INTCLEAR0 = crate::Reg; +#[doc = "NA"] +pub mod commonreg_intclear0; +#[doc = "COMMONREG_INTSTATUS_ENABLE0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`commonreg_intstatus_enable0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`commonreg_intstatus_enable0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@commonreg_intstatus_enable0`] module"] +pub type COMMONREG_INTSTATUS_ENABLE0 = + crate::Reg; +#[doc = "NA"] +pub mod commonreg_intstatus_enable0; +#[doc = "COMMONREG_INTSIGNAL_ENABLE0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`commonreg_intsignal_enable0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`commonreg_intsignal_enable0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@commonreg_intsignal_enable0`] module"] +pub type COMMONREG_INTSIGNAL_ENABLE0 = + crate::Reg; +#[doc = "NA"] +pub mod commonreg_intsignal_enable0; +#[doc = "COMMONREG_INTSTATUS0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`commonreg_intstatus0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@commonreg_intstatus0`] module"] +pub type COMMONREG_INTSTATUS0 = crate::Reg; +#[doc = "NA"] +pub mod commonreg_intstatus0; +#[doc = "RESET0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset0`] module"] +pub type RESET0 = crate::Reg; +#[doc = "NA"] +pub mod reset0; +#[doc = "LOWPOWER_CFG0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpower_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lowpower_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lowpower_cfg0`] module"] +pub type LOWPOWER_CFG0 = crate::Reg; +#[doc = "NA"] +pub mod lowpower_cfg0; +#[doc = "LOWPOWER_CFG1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpower_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lowpower_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lowpower_cfg1`] module"] +pub type LOWPOWER_CFG1 = crate::Reg; +#[doc = "NA"] +pub mod lowpower_cfg1; +#[doc = "CH1_SAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_sar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_sar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_sar0`] module"] +pub type CH1_SAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_sar0; +#[doc = "CH1_SAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_sar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_sar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_sar1`] module"] +pub type CH1_SAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_sar1; +#[doc = "CH1_DAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_dar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_dar0`] module"] +pub type CH1_DAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_dar0; +#[doc = "CH1_DAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_dar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_dar1`] module"] +pub type CH1_DAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_dar1; +#[doc = "CH1_BLOCK_TS0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_block_ts0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_block_ts0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_block_ts0`] module"] +pub type CH1_BLOCK_TS0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_block_ts0; +#[doc = "CH1_CTL0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_ctl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_ctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_ctl0`] module"] +pub type CH1_CTL0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_ctl0; +#[doc = "CH1_CTL1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_ctl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_ctl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_ctl1`] module"] +pub type CH1_CTL1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_ctl1; +#[doc = "CH1_CFG0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_cfg0`] module"] +pub type CH1_CFG0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_cfg0; +#[doc = "CH1_CFG1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_cfg1`] module"] +pub type CH1_CFG1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_cfg1; +#[doc = "CH1_LLP0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_llp0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_llp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_llp0`] module"] +pub type CH1_LLP0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_llp0; +#[doc = "CH1_LLP1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_llp1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_llp1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_llp1`] module"] +pub type CH1_LLP1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_llp1; +#[doc = "CH1_STATUS0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_status0`] module"] +pub type CH1_STATUS0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_status0; +#[doc = "CH1_STATUS1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_status1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_status1`] module"] +pub type CH1_STATUS1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_status1; +#[doc = "CH1_SWHSSRC0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_swhssrc0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_swhssrc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_swhssrc0`] module"] +pub type CH1_SWHSSRC0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_swhssrc0; +#[doc = "CH1_SWHSDST0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_swhsdst0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_swhsdst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_swhsdst0`] module"] +pub type CH1_SWHSDST0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_swhsdst0; +#[doc = "CH1_BLK_TFR_RESUMEREQ0 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_blk_tfr_resumereq0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_blk_tfr_resumereq0`] module"] +pub type CH1_BLK_TFR_RESUMEREQ0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_blk_tfr_resumereq0; +#[doc = "CH1_AXI_ID0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_axi_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_axi_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_axi_id0`] module"] +pub type CH1_AXI_ID0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_axi_id0; +#[doc = "CH1_AXI_QOS0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_axi_qos0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_axi_qos0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_axi_qos0`] module"] +pub type CH1_AXI_QOS0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_axi_qos0; +#[doc = "CH1_SSTAT0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_sstat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_sstat0`] module"] +pub type CH1_SSTAT0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_sstat0; +#[doc = "CH1_DSTAT0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_dstat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_dstat0`] module"] +pub type CH1_DSTAT0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_dstat0; +#[doc = "CH1_SSTATAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_sstatar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_sstatar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_sstatar0`] module"] +pub type CH1_SSTATAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_sstatar0; +#[doc = "CH1_SSTATAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_sstatar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_sstatar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_sstatar1`] module"] +pub type CH1_SSTATAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_sstatar1; +#[doc = "CH1_DSTATAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_dstatar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dstatar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_dstatar0`] module"] +pub type CH1_DSTATAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_dstatar0; +#[doc = "CH1_DSTATAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_dstatar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dstatar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_dstatar1`] module"] +pub type CH1_DSTATAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_dstatar1; +#[doc = "CH1_INTSTATUS_ENABLE0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intstatus_enable0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_intstatus_enable0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_intstatus_enable0`] module"] +pub type CH1_INTSTATUS_ENABLE0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_intstatus_enable0; +#[doc = "CH1_INTSTATUS_ENABLE1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intstatus_enable1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_intstatus_enable1`] module"] +pub type CH1_INTSTATUS_ENABLE1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_intstatus_enable1; +#[doc = "CH1_INTSTATUS0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intstatus0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_intstatus0`] module"] +pub type CH1_INTSTATUS0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_intstatus0; +#[doc = "CH1_INTSTATUS1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intstatus1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_intstatus1`] module"] +pub type CH1_INTSTATUS1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_intstatus1; +#[doc = "CH1_INTSIGNAL_ENABLE0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intsignal_enable0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_intsignal_enable0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_intsignal_enable0`] module"] +pub type CH1_INTSIGNAL_ENABLE0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_intsignal_enable0; +#[doc = "CH1_INTSIGNAL_ENABLE1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intsignal_enable1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_intsignal_enable1`] module"] +pub type CH1_INTSIGNAL_ENABLE1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_intsignal_enable1; +#[doc = "CH1_INTCLEAR0 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_intclear0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_intclear0`] module"] +pub type CH1_INTCLEAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch1_intclear0; +#[doc = "CH1_INTCLEAR1 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_intclear1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_intclear1`] module"] +pub type CH1_INTCLEAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch1_intclear1; +#[doc = "CH2_SAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_sar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_sar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_sar0`] module"] +pub type CH2_SAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_sar0; +#[doc = "CH2_SAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_sar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_sar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_sar1`] module"] +pub type CH2_SAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_sar1; +#[doc = "CH2_DAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_dar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_dar0`] module"] +pub type CH2_DAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_dar0; +#[doc = "CH2_DAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_dar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_dar1`] module"] +pub type CH2_DAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_dar1; +#[doc = "CH2_BLOCK_TS0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_block_ts0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_block_ts0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_block_ts0`] module"] +pub type CH2_BLOCK_TS0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_block_ts0; +#[doc = "CH2_CTL0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_ctl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_ctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_ctl0`] module"] +pub type CH2_CTL0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_ctl0; +#[doc = "CH2_CTL1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_ctl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_ctl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_ctl1`] module"] +pub type CH2_CTL1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_ctl1; +#[doc = "CH2_CFG0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_cfg0`] module"] +pub type CH2_CFG0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_cfg0; +#[doc = "CH2_CFG1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_cfg1`] module"] +pub type CH2_CFG1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_cfg1; +#[doc = "CH2_LLP0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_llp0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_llp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_llp0`] module"] +pub type CH2_LLP0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_llp0; +#[doc = "CH2_LLP1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_llp1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_llp1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_llp1`] module"] +pub type CH2_LLP1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_llp1; +#[doc = "CH2_STATUS0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_status0`] module"] +pub type CH2_STATUS0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_status0; +#[doc = "CH2_STATUS1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_status1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_status1`] module"] +pub type CH2_STATUS1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_status1; +#[doc = "CH2_SWHSSRC0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_swhssrc0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_swhssrc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_swhssrc0`] module"] +pub type CH2_SWHSSRC0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_swhssrc0; +#[doc = "CH2_SWHSDST0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_swhsdst0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_swhsdst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_swhsdst0`] module"] +pub type CH2_SWHSDST0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_swhsdst0; +#[doc = "CH2_BLK_TFR_RESUMEREQ0 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_blk_tfr_resumereq0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_blk_tfr_resumereq0`] module"] +pub type CH2_BLK_TFR_RESUMEREQ0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_blk_tfr_resumereq0; +#[doc = "CH2_AXI_ID0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_axi_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_axi_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_axi_id0`] module"] +pub type CH2_AXI_ID0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_axi_id0; +#[doc = "CH2_AXI_QOS0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_axi_qos0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_axi_qos0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_axi_qos0`] module"] +pub type CH2_AXI_QOS0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_axi_qos0; +#[doc = "CH2_SSTAT0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_sstat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_sstat0`] module"] +pub type CH2_SSTAT0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_sstat0; +#[doc = "CH2_DSTAT0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_dstat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_dstat0`] module"] +pub type CH2_DSTAT0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_dstat0; +#[doc = "CH2_SSTATAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_sstatar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_sstatar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_sstatar0`] module"] +pub type CH2_SSTATAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_sstatar0; +#[doc = "CH2_SSTATAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_sstatar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_sstatar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_sstatar1`] module"] +pub type CH2_SSTATAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_sstatar1; +#[doc = "CH2_DSTATAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_dstatar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dstatar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_dstatar0`] module"] +pub type CH2_DSTATAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_dstatar0; +#[doc = "CH2_DSTATAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_dstatar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dstatar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_dstatar1`] module"] +pub type CH2_DSTATAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_dstatar1; +#[doc = "CH2_INTSTATUS_ENABLE0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intstatus_enable0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_intstatus_enable0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_intstatus_enable0`] module"] +pub type CH2_INTSTATUS_ENABLE0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_intstatus_enable0; +#[doc = "CH2_INTSTATUS_ENABLE1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intstatus_enable1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_intstatus_enable1`] module"] +pub type CH2_INTSTATUS_ENABLE1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_intstatus_enable1; +#[doc = "CH2_INTSTATUS0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intstatus0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_intstatus0`] module"] +pub type CH2_INTSTATUS0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_intstatus0; +#[doc = "CH2_INTSTATUS1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intstatus1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_intstatus1`] module"] +pub type CH2_INTSTATUS1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_intstatus1; +#[doc = "CH2_INTSIGNAL_ENABLE0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intsignal_enable0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_intsignal_enable0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_intsignal_enable0`] module"] +pub type CH2_INTSIGNAL_ENABLE0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_intsignal_enable0; +#[doc = "CH2_INTSIGNAL_ENABLE1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intsignal_enable1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_intsignal_enable1`] module"] +pub type CH2_INTSIGNAL_ENABLE1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_intsignal_enable1; +#[doc = "CH2_INTCLEAR0 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_intclear0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_intclear0`] module"] +pub type CH2_INTCLEAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch2_intclear0; +#[doc = "CH2_INTCLEAR1 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_intclear1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_intclear1`] module"] +pub type CH2_INTCLEAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch2_intclear1; +#[doc = "CH3_SAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_sar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_sar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_sar0`] module"] +pub type CH3_SAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_sar0; +#[doc = "CH3_SAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_sar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_sar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_sar1`] module"] +pub type CH3_SAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_sar1; +#[doc = "CH3_DAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_dar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_dar0`] module"] +pub type CH3_DAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_dar0; +#[doc = "CH3_DAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_dar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_dar1`] module"] +pub type CH3_DAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_dar1; +#[doc = "CH3_BLOCK_TS0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_block_ts0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_block_ts0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_block_ts0`] module"] +pub type CH3_BLOCK_TS0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_block_ts0; +#[doc = "CH3_CTL0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_ctl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_ctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_ctl0`] module"] +pub type CH3_CTL0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_ctl0; +#[doc = "CH3_CTL1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_ctl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_ctl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_ctl1`] module"] +pub type CH3_CTL1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_ctl1; +#[doc = "CH3_CFG0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_cfg0`] module"] +pub type CH3_CFG0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_cfg0; +#[doc = "CH3_CFG1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_cfg1`] module"] +pub type CH3_CFG1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_cfg1; +#[doc = "CH3_LLP0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_llp0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_llp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_llp0`] module"] +pub type CH3_LLP0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_llp0; +#[doc = "CH3_LLP1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_llp1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_llp1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_llp1`] module"] +pub type CH3_LLP1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_llp1; +#[doc = "CH3_STATUS0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_status0`] module"] +pub type CH3_STATUS0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_status0; +#[doc = "CH3_STATUS1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_status1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_status1`] module"] +pub type CH3_STATUS1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_status1; +#[doc = "CH3_SWHSSRC0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_swhssrc0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_swhssrc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_swhssrc0`] module"] +pub type CH3_SWHSSRC0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_swhssrc0; +#[doc = "CH3_SWHSDST0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_swhsdst0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_swhsdst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_swhsdst0`] module"] +pub type CH3_SWHSDST0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_swhsdst0; +#[doc = "CH3_BLK_TFR_RESUMEREQ0 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_blk_tfr_resumereq0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_blk_tfr_resumereq0`] module"] +pub type CH3_BLK_TFR_RESUMEREQ0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_blk_tfr_resumereq0; +#[doc = "CH3_AXI_ID0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_axi_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_axi_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_axi_id0`] module"] +pub type CH3_AXI_ID0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_axi_id0; +#[doc = "CH3_AXI_QOS0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_axi_qos0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_axi_qos0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_axi_qos0`] module"] +pub type CH3_AXI_QOS0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_axi_qos0; +#[doc = "CH3_SSTAT0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_sstat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_sstat0`] module"] +pub type CH3_SSTAT0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_sstat0; +#[doc = "CH3_DSTAT0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_dstat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_dstat0`] module"] +pub type CH3_DSTAT0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_dstat0; +#[doc = "CH3_SSTATAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_sstatar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_sstatar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_sstatar0`] module"] +pub type CH3_SSTATAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_sstatar0; +#[doc = "CH3_SSTATAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_sstatar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_sstatar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_sstatar1`] module"] +pub type CH3_SSTATAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_sstatar1; +#[doc = "CH3_DSTATAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_dstatar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dstatar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_dstatar0`] module"] +pub type CH3_DSTATAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_dstatar0; +#[doc = "CH3_DSTATAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_dstatar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dstatar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_dstatar1`] module"] +pub type CH3_DSTATAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_dstatar1; +#[doc = "CH3_INTSTATUS_ENABLE0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intstatus_enable0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_intstatus_enable0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_intstatus_enable0`] module"] +pub type CH3_INTSTATUS_ENABLE0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_intstatus_enable0; +#[doc = "CH3_INTSTATUS_ENABLE1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intstatus_enable1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_intstatus_enable1`] module"] +pub type CH3_INTSTATUS_ENABLE1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_intstatus_enable1; +#[doc = "CH3_INTSTATUS0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intstatus0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_intstatus0`] module"] +pub type CH3_INTSTATUS0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_intstatus0; +#[doc = "CH3_INTSTATUS1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intstatus1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_intstatus1`] module"] +pub type CH3_INTSTATUS1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_intstatus1; +#[doc = "CH3_INTSIGNAL_ENABLE0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intsignal_enable0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_intsignal_enable0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_intsignal_enable0`] module"] +pub type CH3_INTSIGNAL_ENABLE0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_intsignal_enable0; +#[doc = "CH3_INTSIGNAL_ENABLE1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intsignal_enable1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_intsignal_enable1`] module"] +pub type CH3_INTSIGNAL_ENABLE1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_intsignal_enable1; +#[doc = "CH3_INTCLEAR0 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_intclear0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_intclear0`] module"] +pub type CH3_INTCLEAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch3_intclear0; +#[doc = "CH3_INTCLEAR1 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_intclear1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_intclear1`] module"] +pub type CH3_INTCLEAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch3_intclear1; +#[doc = "CH4_SAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_sar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_sar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_sar0`] module"] +pub type CH4_SAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_sar0; +#[doc = "CH4_SAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_sar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_sar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_sar1`] module"] +pub type CH4_SAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_sar1; +#[doc = "CH4_DAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_dar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_dar0`] module"] +pub type CH4_DAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_dar0; +#[doc = "CH4_DAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_dar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_dar1`] module"] +pub type CH4_DAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_dar1; +#[doc = "CH4_BLOCK_TS0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_block_ts0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_block_ts0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_block_ts0`] module"] +pub type CH4_BLOCK_TS0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_block_ts0; +#[doc = "CH4_CTL0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_ctl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_ctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_ctl0`] module"] +pub type CH4_CTL0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_ctl0; +#[doc = "CH4_CTL1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_ctl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_ctl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_ctl1`] module"] +pub type CH4_CTL1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_ctl1; +#[doc = "CH4_CFG0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_cfg0`] module"] +pub type CH4_CFG0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_cfg0; +#[doc = "CH4_CFG1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_cfg1`] module"] +pub type CH4_CFG1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_cfg1; +#[doc = "CH4_LLP0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_llp0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_llp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_llp0`] module"] +pub type CH4_LLP0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_llp0; +#[doc = "CH4_LLP1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_llp1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_llp1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_llp1`] module"] +pub type CH4_LLP1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_llp1; +#[doc = "CH4_STATUS0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_status0`] module"] +pub type CH4_STATUS0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_status0; +#[doc = "CH4_STATUS1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_status1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_status1`] module"] +pub type CH4_STATUS1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_status1; +#[doc = "CH4_SWHSSRC0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_swhssrc0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_swhssrc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_swhssrc0`] module"] +pub type CH4_SWHSSRC0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_swhssrc0; +#[doc = "CH4_SWHSDST0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_swhsdst0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_swhsdst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_swhsdst0`] module"] +pub type CH4_SWHSDST0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_swhsdst0; +#[doc = "CH4_BLK_TFR_RESUMEREQ0 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_blk_tfr_resumereq0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_blk_tfr_resumereq0`] module"] +pub type CH4_BLK_TFR_RESUMEREQ0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_blk_tfr_resumereq0; +#[doc = "CH4_AXI_ID0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_axi_id0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_axi_id0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_axi_id0`] module"] +pub type CH4_AXI_ID0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_axi_id0; +#[doc = "CH4_AXI_QOS0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_axi_qos0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_axi_qos0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_axi_qos0`] module"] +pub type CH4_AXI_QOS0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_axi_qos0; +#[doc = "CH4_SSTAT0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_sstat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_sstat0`] module"] +pub type CH4_SSTAT0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_sstat0; +#[doc = "CH4_DSTAT0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_dstat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_dstat0`] module"] +pub type CH4_DSTAT0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_dstat0; +#[doc = "CH4_SSTATAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_sstatar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_sstatar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_sstatar0`] module"] +pub type CH4_SSTATAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_sstatar0; +#[doc = "CH4_SSTATAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_sstatar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_sstatar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_sstatar1`] module"] +pub type CH4_SSTATAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_sstatar1; +#[doc = "CH4_DSTATAR0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_dstatar0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dstatar0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_dstatar0`] module"] +pub type CH4_DSTATAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_dstatar0; +#[doc = "CH4_DSTATAR1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_dstatar1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dstatar1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_dstatar1`] module"] +pub type CH4_DSTATAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_dstatar1; +#[doc = "CH4_INTSTATUS_ENABLE0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intstatus_enable0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_intstatus_enable0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_intstatus_enable0`] module"] +pub type CH4_INTSTATUS_ENABLE0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_intstatus_enable0; +#[doc = "CH4_INTSTATUS_ENABLE1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intstatus_enable1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_intstatus_enable1`] module"] +pub type CH4_INTSTATUS_ENABLE1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_intstatus_enable1; +#[doc = "CH4_INTSTATUS0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intstatus0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_intstatus0`] module"] +pub type CH4_INTSTATUS0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_intstatus0; +#[doc = "CH4_INTSTATUS1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intstatus1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_intstatus1`] module"] +pub type CH4_INTSTATUS1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_intstatus1; +#[doc = "CH4_INTSIGNAL_ENABLE0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intsignal_enable0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_intsignal_enable0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_intsignal_enable0`] module"] +pub type CH4_INTSIGNAL_ENABLE0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_intsignal_enable0; +#[doc = "CH4_INTSIGNAL_ENABLE1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intsignal_enable1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_intsignal_enable1`] module"] +pub type CH4_INTSIGNAL_ENABLE1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_intsignal_enable1; +#[doc = "CH4_INTCLEAR0 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_intclear0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_intclear0`] module"] +pub type CH4_INTCLEAR0 = crate::Reg; +#[doc = "NA"] +pub mod ch4_intclear0; +#[doc = "CH4_INTCLEAR1 (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_intclear1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_intclear1`] module"] +pub type CH4_INTCLEAR1 = crate::Reg; +#[doc = "NA"] +pub mod ch4_intclear1; diff --git a/esp32p4/src/dma/cfg0.rs b/esp32p4/src/dma/cfg0.rs new file mode 100644 index 0000000000..e196bcaa4c --- /dev/null +++ b/esp32p4/src/dma/cfg0.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `DMAC_EN` reader - NA"] +pub type DMAC_EN_R = crate::BitReader; +#[doc = "Field `DMAC_EN` writer - NA"] +pub type DMAC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INT_EN` reader - NA"] +pub type INT_EN_R = crate::BitReader; +#[doc = "Field `INT_EN` writer - NA"] +pub type INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn dmac_en(&self) -> DMAC_EN_R { + DMAC_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn int_en(&self) -> INT_EN_R { + INT_EN_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CFG0") + .field("dmac_en", &format_args!("{}", self.dmac_en().bit())) + .field("int_en", &format_args!("{}", self.int_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn dmac_en(&mut self) -> DMAC_EN_W { + DMAC_EN_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn int_en(&mut self) -> INT_EN_W { + INT_EN_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CFG0_SPEC; +impl crate::RegisterSpec for CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cfg0::R`](R) reader structure"] +impl crate::Readable for CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cfg0::W`](W) writer structure"] +impl crate::Writable for CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CFG0 to value 0"] +impl crate::Resettable for CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_axi_id0.rs b/esp32p4/src/dma/ch1_axi_id0.rs new file mode 100644 index 0000000000..89d92d5a5a --- /dev/null +++ b/esp32p4/src/dma/ch1_axi_id0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CH1_AXI_ID0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_AXI_ID0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_AXI_READ_ID_SUFFIX` reader - NA"] +pub type CH1_AXI_READ_ID_SUFFIX_R = crate::BitReader; +#[doc = "Field `CH1_AXI_READ_ID_SUFFIX` writer - NA"] +pub type CH1_AXI_READ_ID_SUFFIX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_AXI_WRITE_ID_SUFFIX` reader - NA"] +pub type CH1_AXI_WRITE_ID_SUFFIX_R = crate::BitReader; +#[doc = "Field `CH1_AXI_WRITE_ID_SUFFIX` writer - NA"] +pub type CH1_AXI_WRITE_ID_SUFFIX_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_axi_read_id_suffix(&self) -> CH1_AXI_READ_ID_SUFFIX_R { + CH1_AXI_READ_ID_SUFFIX_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch1_axi_write_id_suffix(&self) -> CH1_AXI_WRITE_ID_SUFFIX_R { + CH1_AXI_WRITE_ID_SUFFIX_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_AXI_ID0") + .field( + "ch1_axi_read_id_suffix", + &format_args!("{}", self.ch1_axi_read_id_suffix().bit()), + ) + .field( + "ch1_axi_write_id_suffix", + &format_args!("{}", self.ch1_axi_write_id_suffix().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_axi_read_id_suffix(&mut self) -> CH1_AXI_READ_ID_SUFFIX_W { + CH1_AXI_READ_ID_SUFFIX_W::new(self, 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_axi_write_id_suffix(&mut self) -> CH1_AXI_WRITE_ID_SUFFIX_W { + CH1_AXI_WRITE_ID_SUFFIX_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_axi_id0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_axi_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_AXI_ID0_SPEC; +impl crate::RegisterSpec for CH1_AXI_ID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_axi_id0::R`](R) reader structure"] +impl crate::Readable for CH1_AXI_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_axi_id0::W`](W) writer structure"] +impl crate::Writable for CH1_AXI_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_AXI_ID0 to value 0"] +impl crate::Resettable for CH1_AXI_ID0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_axi_qos0.rs b/esp32p4/src/dma/ch1_axi_qos0.rs new file mode 100644 index 0000000000..4e3e11805a --- /dev/null +++ b/esp32p4/src/dma/ch1_axi_qos0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CH1_AXI_QOS0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_AXI_QOS0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_AXI_AWQOS` reader - NA"] +pub type CH1_AXI_AWQOS_R = crate::FieldReader; +#[doc = "Field `CH1_AXI_AWQOS` writer - NA"] +pub type CH1_AXI_AWQOS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH1_AXI_ARQOS` reader - NA"] +pub type CH1_AXI_ARQOS_R = crate::FieldReader; +#[doc = "Field `CH1_AXI_ARQOS` writer - NA"] +pub type CH1_AXI_ARQOS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + pub fn ch1_axi_awqos(&self) -> CH1_AXI_AWQOS_R { + CH1_AXI_AWQOS_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - NA"] + #[inline(always)] + pub fn ch1_axi_arqos(&self) -> CH1_AXI_ARQOS_R { + CH1_AXI_ARQOS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_AXI_QOS0") + .field( + "ch1_axi_awqos", + &format_args!("{}", self.ch1_axi_awqos().bits()), + ) + .field( + "ch1_axi_arqos", + &format_args!("{}", self.ch1_axi_arqos().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_axi_awqos(&mut self) -> CH1_AXI_AWQOS_W { + CH1_AXI_AWQOS_W::new(self, 0) + } + #[doc = "Bits 4:7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_axi_arqos(&mut self) -> CH1_AXI_ARQOS_W { + CH1_AXI_ARQOS_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_axi_qos0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_axi_qos0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_AXI_QOS0_SPEC; +impl crate::RegisterSpec for CH1_AXI_QOS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_axi_qos0::R`](R) reader structure"] +impl crate::Readable for CH1_AXI_QOS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_axi_qos0::W`](W) writer structure"] +impl crate::Writable for CH1_AXI_QOS0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_AXI_QOS0 to value 0"] +impl crate::Resettable for CH1_AXI_QOS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_blk_tfr_resumereq0.rs b/esp32p4/src/dma/ch1_blk_tfr_resumereq0.rs new file mode 100644 index 0000000000..8e94676341 --- /dev/null +++ b/esp32p4/src/dma/ch1_blk_tfr_resumereq0.rs @@ -0,0 +1,44 @@ +#[doc = "Register `CH1_BLK_TFR_RESUMEREQ0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_BLK_TFR_RESUMEREQ` writer - NA"] +pub type CH1_BLK_TFR_RESUMEREQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_blk_tfr_resumereq( + &mut self, + ) -> CH1_BLK_TFR_RESUMEREQ_W { + CH1_BLK_TFR_RESUMEREQ_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_blk_tfr_resumereq0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_BLK_TFR_RESUMEREQ0_SPEC; +impl crate::RegisterSpec for CH1_BLK_TFR_RESUMEREQ0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch1_blk_tfr_resumereq0::W`](W) writer structure"] +impl crate::Writable for CH1_BLK_TFR_RESUMEREQ0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_BLK_TFR_RESUMEREQ0 to value 0"] +impl crate::Resettable for CH1_BLK_TFR_RESUMEREQ0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_block_ts0.rs b/esp32p4/src/dma/ch1_block_ts0.rs new file mode 100644 index 0000000000..b7ba5262fd --- /dev/null +++ b/esp32p4/src/dma/ch1_block_ts0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH1_BLOCK_TS0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_BLOCK_TS0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_BLOCK_TS` reader - NA"] +pub type CH1_BLOCK_TS_R = crate::FieldReader; +#[doc = "Field `CH1_BLOCK_TS` writer - NA"] +pub type CH1_BLOCK_TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + pub fn ch1_block_ts(&self) -> CH1_BLOCK_TS_R { + CH1_BLOCK_TS_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_BLOCK_TS0") + .field( + "ch1_block_ts", + &format_args!("{}", self.ch1_block_ts().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_block_ts(&mut self) -> CH1_BLOCK_TS_W { + CH1_BLOCK_TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_block_ts0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_block_ts0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_BLOCK_TS0_SPEC; +impl crate::RegisterSpec for CH1_BLOCK_TS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_block_ts0::R`](R) reader structure"] +impl crate::Readable for CH1_BLOCK_TS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_block_ts0::W`](W) writer structure"] +impl crate::Writable for CH1_BLOCK_TS0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_BLOCK_TS0 to value 0"] +impl crate::Resettable for CH1_BLOCK_TS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_cfg0.rs b/esp32p4/src/dma/ch1_cfg0.rs new file mode 100644 index 0000000000..0da197d11e --- /dev/null +++ b/esp32p4/src/dma/ch1_cfg0.rs @@ -0,0 +1,101 @@ +#[doc = "Register `CH1_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_SRC_MULTBLK_TYPE` reader - NA"] +pub type CH1_SRC_MULTBLK_TYPE_R = crate::FieldReader; +#[doc = "Field `CH1_SRC_MULTBLK_TYPE` writer - NA"] +pub type CH1_SRC_MULTBLK_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH1_DST_MULTBLK_TYPE` reader - NA"] +pub type CH1_DST_MULTBLK_TYPE_R = crate::FieldReader; +#[doc = "Field `CH1_DST_MULTBLK_TYPE` writer - NA"] +pub type CH1_DST_MULTBLK_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH1_RD_UID` reader - NA"] +pub type CH1_RD_UID_R = crate::FieldReader; +#[doc = "Field `CH1_WR_UID` reader - NA"] +pub type CH1_WR_UID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn ch1_src_multblk_type(&self) -> CH1_SRC_MULTBLK_TYPE_R { + CH1_SRC_MULTBLK_TYPE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - NA"] + #[inline(always)] + pub fn ch1_dst_multblk_type(&self) -> CH1_DST_MULTBLK_TYPE_R { + CH1_DST_MULTBLK_TYPE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + pub fn ch1_rd_uid(&self) -> CH1_RD_UID_R { + CH1_RD_UID_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bits 25:28 - NA"] + #[inline(always)] + pub fn ch1_wr_uid(&self) -> CH1_WR_UID_R { + CH1_WR_UID_R::new(((self.bits >> 25) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_CFG0") + .field( + "ch1_src_multblk_type", + &format_args!("{}", self.ch1_src_multblk_type().bits()), + ) + .field( + "ch1_dst_multblk_type", + &format_args!("{}", self.ch1_dst_multblk_type().bits()), + ) + .field("ch1_rd_uid", &format_args!("{}", self.ch1_rd_uid().bits())) + .field("ch1_wr_uid", &format_args!("{}", self.ch1_wr_uid().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_src_multblk_type(&mut self) -> CH1_SRC_MULTBLK_TYPE_W { + CH1_SRC_MULTBLK_TYPE_W::new(self, 0) + } + #[doc = "Bits 2:3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dst_multblk_type(&mut self) -> CH1_DST_MULTBLK_TYPE_W { + CH1_DST_MULTBLK_TYPE_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_CFG0_SPEC; +impl crate::RegisterSpec for CH1_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_cfg0::R`](R) reader structure"] +impl crate::Readable for CH1_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_cfg0::W`](W) writer structure"] +impl crate::Writable for CH1_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_CFG0 to value 0"] +impl crate::Resettable for CH1_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_cfg1.rs b/esp32p4/src/dma/ch1_cfg1.rs new file mode 100644 index 0000000000..e586ff1e8b --- /dev/null +++ b/esp32p4/src/dma/ch1_cfg1.rs @@ -0,0 +1,237 @@ +#[doc = "Register `CH1_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_TT_FC` reader - NA"] +pub type CH1_TT_FC_R = crate::FieldReader; +#[doc = "Field `CH1_TT_FC` writer - NA"] +pub type CH1_TT_FC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH1_HS_SEL_SRC` reader - NA"] +pub type CH1_HS_SEL_SRC_R = crate::BitReader; +#[doc = "Field `CH1_HS_SEL_SRC` writer - NA"] +pub type CH1_HS_SEL_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_HS_SEL_DST` reader - NA"] +pub type CH1_HS_SEL_DST_R = crate::BitReader; +#[doc = "Field `CH1_HS_SEL_DST` writer - NA"] +pub type CH1_HS_SEL_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SRC_HWHS_POL` reader - NA"] +pub type CH1_SRC_HWHS_POL_R = crate::BitReader; +#[doc = "Field `CH1_DST_HWHS_POL` reader - NA"] +pub type CH1_DST_HWHS_POL_R = crate::BitReader; +#[doc = "Field `CH1_SRC_PER` reader - NA"] +pub type CH1_SRC_PER_R = crate::FieldReader; +#[doc = "Field `CH1_SRC_PER` writer - NA"] +pub type CH1_SRC_PER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH1_DST_PER` reader - NA"] +pub type CH1_DST_PER_R = crate::FieldReader; +#[doc = "Field `CH1_DST_PER` writer - NA"] +pub type CH1_DST_PER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH1_CH_PRIOR` reader - NA"] +pub type CH1_CH_PRIOR_R = crate::FieldReader; +#[doc = "Field `CH1_CH_PRIOR` writer - NA"] +pub type CH1_CH_PRIOR_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH1_LOCK_CH` reader - NA"] +pub type CH1_LOCK_CH_R = crate::BitReader; +#[doc = "Field `CH1_LOCK_CH_L` reader - NA"] +pub type CH1_LOCK_CH_L_R = crate::FieldReader; +#[doc = "Field `CH1_SRC_OSR_LMT` reader - NA"] +pub type CH1_SRC_OSR_LMT_R = crate::FieldReader; +#[doc = "Field `CH1_SRC_OSR_LMT` writer - NA"] +pub type CH1_SRC_OSR_LMT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH1_DST_OSR_LMT` reader - NA"] +pub type CH1_DST_OSR_LMT_R = crate::FieldReader; +#[doc = "Field `CH1_DST_OSR_LMT` writer - NA"] +pub type CH1_DST_OSR_LMT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + pub fn ch1_tt_fc(&self) -> CH1_TT_FC_R { + CH1_TT_FC_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch1_hs_sel_src(&self) -> CH1_HS_SEL_SRC_R { + CH1_HS_SEL_SRC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch1_hs_sel_dst(&self) -> CH1_HS_SEL_DST_R { + CH1_HS_SEL_DST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch1_src_hwhs_pol(&self) -> CH1_SRC_HWHS_POL_R { + CH1_SRC_HWHS_POL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch1_dst_hwhs_pol(&self) -> CH1_DST_HWHS_POL_R { + CH1_DST_HWHS_POL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:8 - NA"] + #[inline(always)] + pub fn ch1_src_per(&self) -> CH1_SRC_PER_R { + CH1_SRC_PER_R::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 12:13 - NA"] + #[inline(always)] + pub fn ch1_dst_per(&self) -> CH1_DST_PER_R { + CH1_DST_PER_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 17:19 - NA"] + #[inline(always)] + pub fn ch1_ch_prior(&self) -> CH1_CH_PRIOR_R { + CH1_CH_PRIOR_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch1_lock_ch(&self) -> CH1_LOCK_CH_R { + CH1_LOCK_CH_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:22 - NA"] + #[inline(always)] + pub fn ch1_lock_ch_l(&self) -> CH1_LOCK_CH_L_R { + CH1_LOCK_CH_L_R::new(((self.bits >> 21) & 3) as u8) + } + #[doc = "Bits 23:26 - NA"] + #[inline(always)] + pub fn ch1_src_osr_lmt(&self) -> CH1_SRC_OSR_LMT_R { + CH1_SRC_OSR_LMT_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bits 27:30 - NA"] + #[inline(always)] + pub fn ch1_dst_osr_lmt(&self) -> CH1_DST_OSR_LMT_R { + CH1_DST_OSR_LMT_R::new(((self.bits >> 27) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_CFG1") + .field("ch1_tt_fc", &format_args!("{}", self.ch1_tt_fc().bits())) + .field( + "ch1_hs_sel_src", + &format_args!("{}", self.ch1_hs_sel_src().bit()), + ) + .field( + "ch1_hs_sel_dst", + &format_args!("{}", self.ch1_hs_sel_dst().bit()), + ) + .field( + "ch1_src_hwhs_pol", + &format_args!("{}", self.ch1_src_hwhs_pol().bit()), + ) + .field( + "ch1_dst_hwhs_pol", + &format_args!("{}", self.ch1_dst_hwhs_pol().bit()), + ) + .field( + "ch1_src_per", + &format_args!("{}", self.ch1_src_per().bits()), + ) + .field( + "ch1_dst_per", + &format_args!("{}", self.ch1_dst_per().bits()), + ) + .field( + "ch1_ch_prior", + &format_args!("{}", self.ch1_ch_prior().bits()), + ) + .field("ch1_lock_ch", &format_args!("{}", self.ch1_lock_ch().bit())) + .field( + "ch1_lock_ch_l", + &format_args!("{}", self.ch1_lock_ch_l().bits()), + ) + .field( + "ch1_src_osr_lmt", + &format_args!("{}", self.ch1_src_osr_lmt().bits()), + ) + .field( + "ch1_dst_osr_lmt", + &format_args!("{}", self.ch1_dst_osr_lmt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_tt_fc(&mut self) -> CH1_TT_FC_W { + CH1_TT_FC_W::new(self, 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_hs_sel_src(&mut self) -> CH1_HS_SEL_SRC_W { + CH1_HS_SEL_SRC_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_hs_sel_dst(&mut self) -> CH1_HS_SEL_DST_W { + CH1_HS_SEL_DST_W::new(self, 4) + } + #[doc = "Bits 7:8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_src_per(&mut self) -> CH1_SRC_PER_W { + CH1_SRC_PER_W::new(self, 7) + } + #[doc = "Bits 12:13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dst_per(&mut self) -> CH1_DST_PER_W { + CH1_DST_PER_W::new(self, 12) + } + #[doc = "Bits 17:19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_ch_prior(&mut self) -> CH1_CH_PRIOR_W { + CH1_CH_PRIOR_W::new(self, 17) + } + #[doc = "Bits 23:26 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_src_osr_lmt(&mut self) -> CH1_SRC_OSR_LMT_W { + CH1_SRC_OSR_LMT_W::new(self, 23) + } + #[doc = "Bits 27:30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dst_osr_lmt(&mut self) -> CH1_DST_OSR_LMT_W { + CH1_DST_OSR_LMT_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_CFG1_SPEC; +impl crate::RegisterSpec for CH1_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_cfg1::R`](R) reader structure"] +impl crate::Readable for CH1_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_cfg1::W`](W) writer structure"] +impl crate::Writable for CH1_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_CFG1 to value 0x0006_001b"] +impl crate::Resettable for CH1_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0x0006_001b; +} diff --git a/esp32p4/src/dma/ch1_ctl0.rs b/esp32p4/src/dma/ch1_ctl0.rs new file mode 100644 index 0000000000..521ec71e69 --- /dev/null +++ b/esp32p4/src/dma/ch1_ctl0.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CH1_CTL0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_CTL0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_SMS` reader - NA"] +pub type CH1_SMS_R = crate::BitReader; +#[doc = "Field `CH1_SMS` writer - NA"] +pub type CH1_SMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_DMS` reader - NA"] +pub type CH1_DMS_R = crate::BitReader; +#[doc = "Field `CH1_DMS` writer - NA"] +pub type CH1_DMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SINC` reader - NA"] +pub type CH1_SINC_R = crate::BitReader; +#[doc = "Field `CH1_SINC` writer - NA"] +pub type CH1_SINC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_DINC` reader - NA"] +pub type CH1_DINC_R = crate::BitReader; +#[doc = "Field `CH1_DINC` writer - NA"] +pub type CH1_DINC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SRC_TR_WIDTH` reader - NA"] +pub type CH1_SRC_TR_WIDTH_R = crate::FieldReader; +#[doc = "Field `CH1_SRC_TR_WIDTH` writer - NA"] +pub type CH1_SRC_TR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH1_DST_TR_WIDTH` reader - NA"] +pub type CH1_DST_TR_WIDTH_R = crate::FieldReader; +#[doc = "Field `CH1_DST_TR_WIDTH` writer - NA"] +pub type CH1_DST_TR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH1_SRC_MSIZE` reader - NA"] +pub type CH1_SRC_MSIZE_R = crate::FieldReader; +#[doc = "Field `CH1_SRC_MSIZE` writer - NA"] +pub type CH1_SRC_MSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH1_DST_MSIZE` reader - NA"] +pub type CH1_DST_MSIZE_R = crate::FieldReader; +#[doc = "Field `CH1_DST_MSIZE` writer - NA"] +pub type CH1_DST_MSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH1_AR_CACHE` reader - NA"] +pub type CH1_AR_CACHE_R = crate::FieldReader; +#[doc = "Field `CH1_AR_CACHE` writer - NA"] +pub type CH1_AR_CACHE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH1_AW_CACHE` reader - NA"] +pub type CH1_AW_CACHE_R = crate::FieldReader; +#[doc = "Field `CH1_AW_CACHE` writer - NA"] +pub type CH1_AW_CACHE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH1_NONPOSTED_LASTWRITE_EN` reader - NA"] +pub type CH1_NONPOSTED_LASTWRITE_EN_R = crate::BitReader; +#[doc = "Field `CH1_NONPOSTED_LASTWRITE_EN` writer - NA"] +pub type CH1_NONPOSTED_LASTWRITE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_sms(&self) -> CH1_SMS_R { + CH1_SMS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch1_dms(&self) -> CH1_DMS_R { + CH1_DMS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch1_sinc(&self) -> CH1_SINC_R { + CH1_SINC_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch1_dinc(&self) -> CH1_DINC_R { + CH1_DINC_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - NA"] + #[inline(always)] + pub fn ch1_src_tr_width(&self) -> CH1_SRC_TR_WIDTH_R { + CH1_SRC_TR_WIDTH_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 11:13 - NA"] + #[inline(always)] + pub fn ch1_dst_tr_width(&self) -> CH1_DST_TR_WIDTH_R { + CH1_DST_TR_WIDTH_R::new(((self.bits >> 11) & 7) as u8) + } + #[doc = "Bits 14:17 - NA"] + #[inline(always)] + pub fn ch1_src_msize(&self) -> CH1_SRC_MSIZE_R { + CH1_SRC_MSIZE_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + pub fn ch1_dst_msize(&self) -> CH1_DST_MSIZE_R { + CH1_DST_MSIZE_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bits 22:25 - NA"] + #[inline(always)] + pub fn ch1_ar_cache(&self) -> CH1_AR_CACHE_R { + CH1_AR_CACHE_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:29 - NA"] + #[inline(always)] + pub fn ch1_aw_cache(&self) -> CH1_AW_CACHE_R { + CH1_AW_CACHE_R::new(((self.bits >> 26) & 0x0f) as u8) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch1_nonposted_lastwrite_en(&self) -> CH1_NONPOSTED_LASTWRITE_EN_R { + CH1_NONPOSTED_LASTWRITE_EN_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_CTL0") + .field("ch1_sms", &format_args!("{}", self.ch1_sms().bit())) + .field("ch1_dms", &format_args!("{}", self.ch1_dms().bit())) + .field("ch1_sinc", &format_args!("{}", self.ch1_sinc().bit())) + .field("ch1_dinc", &format_args!("{}", self.ch1_dinc().bit())) + .field( + "ch1_src_tr_width", + &format_args!("{}", self.ch1_src_tr_width().bits()), + ) + .field( + "ch1_dst_tr_width", + &format_args!("{}", self.ch1_dst_tr_width().bits()), + ) + .field( + "ch1_src_msize", + &format_args!("{}", self.ch1_src_msize().bits()), + ) + .field( + "ch1_dst_msize", + &format_args!("{}", self.ch1_dst_msize().bits()), + ) + .field( + "ch1_ar_cache", + &format_args!("{}", self.ch1_ar_cache().bits()), + ) + .field( + "ch1_aw_cache", + &format_args!("{}", self.ch1_aw_cache().bits()), + ) + .field( + "ch1_nonposted_lastwrite_en", + &format_args!("{}", self.ch1_nonposted_lastwrite_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_sms(&mut self) -> CH1_SMS_W { + CH1_SMS_W::new(self, 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dms(&mut self) -> CH1_DMS_W { + CH1_DMS_W::new(self, 2) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_sinc(&mut self) -> CH1_SINC_W { + CH1_SINC_W::new(self, 4) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dinc(&mut self) -> CH1_DINC_W { + CH1_DINC_W::new(self, 6) + } + #[doc = "Bits 8:10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_src_tr_width(&mut self) -> CH1_SRC_TR_WIDTH_W { + CH1_SRC_TR_WIDTH_W::new(self, 8) + } + #[doc = "Bits 11:13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dst_tr_width(&mut self) -> CH1_DST_TR_WIDTH_W { + CH1_DST_TR_WIDTH_W::new(self, 11) + } + #[doc = "Bits 14:17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_src_msize(&mut self) -> CH1_SRC_MSIZE_W { + CH1_SRC_MSIZE_W::new(self, 14) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dst_msize(&mut self) -> CH1_DST_MSIZE_W { + CH1_DST_MSIZE_W::new(self, 18) + } + #[doc = "Bits 22:25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_ar_cache(&mut self) -> CH1_AR_CACHE_W { + CH1_AR_CACHE_W::new(self, 22) + } + #[doc = "Bits 26:29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_aw_cache(&mut self) -> CH1_AW_CACHE_W { + CH1_AW_CACHE_W::new(self, 26) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_nonposted_lastwrite_en(&mut self) -> CH1_NONPOSTED_LASTWRITE_EN_W { + CH1_NONPOSTED_LASTWRITE_EN_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_CTL0_SPEC; +impl crate::RegisterSpec for CH1_CTL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_ctl0::R`](R) reader structure"] +impl crate::Readable for CH1_CTL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_ctl0::W`](W) writer structure"] +impl crate::Writable for CH1_CTL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_CTL0 to value 0x1200"] +impl crate::Resettable for CH1_CTL0_SPEC { + const RESET_VALUE: Self::Ux = 0x1200; +} diff --git a/esp32p4/src/dma/ch1_ctl1.rs b/esp32p4/src/dma/ch1_ctl1.rs new file mode 100644 index 0000000000..0007bb421a --- /dev/null +++ b/esp32p4/src/dma/ch1_ctl1.rs @@ -0,0 +1,250 @@ +#[doc = "Register `CH1_CTL1` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_CTL1` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_AR_PROT` reader - NA"] +pub type CH1_AR_PROT_R = crate::FieldReader; +#[doc = "Field `CH1_AR_PROT` writer - NA"] +pub type CH1_AR_PROT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH1_AW_PROT` reader - NA"] +pub type CH1_AW_PROT_R = crate::FieldReader; +#[doc = "Field `CH1_AW_PROT` writer - NA"] +pub type CH1_AW_PROT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH1_ARLEN_EN` reader - NA"] +pub type CH1_ARLEN_EN_R = crate::BitReader; +#[doc = "Field `CH1_ARLEN_EN` writer - NA"] +pub type CH1_ARLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ARLEN` reader - NA"] +pub type CH1_ARLEN_R = crate::FieldReader; +#[doc = "Field `CH1_ARLEN` writer - NA"] +pub type CH1_ARLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CH1_AWLEN_EN` reader - NA"] +pub type CH1_AWLEN_EN_R = crate::BitReader; +#[doc = "Field `CH1_AWLEN_EN` writer - NA"] +pub type CH1_AWLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_AWLEN` reader - NA"] +pub type CH1_AWLEN_R = crate::FieldReader; +#[doc = "Field `CH1_AWLEN` writer - NA"] +pub type CH1_AWLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CH1_SRC_STAT_EN` reader - NA"] +pub type CH1_SRC_STAT_EN_R = crate::BitReader; +#[doc = "Field `CH1_SRC_STAT_EN` writer - NA"] +pub type CH1_SRC_STAT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_DST_STAT_EN` reader - NA"] +pub type CH1_DST_STAT_EN_R = crate::BitReader; +#[doc = "Field `CH1_DST_STAT_EN` writer - NA"] +pub type CH1_DST_STAT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_IOC_BLKTFR` reader - NA"] +pub type CH1_IOC_BLKTFR_R = crate::BitReader; +#[doc = "Field `CH1_IOC_BLKTFR` writer - NA"] +pub type CH1_IOC_BLKTFR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SHADOWREG_OR_LLI_LAST` reader - NA"] +pub type CH1_SHADOWREG_OR_LLI_LAST_R = crate::BitReader; +#[doc = "Field `CH1_SHADOWREG_OR_LLI_LAST` writer - NA"] +pub type CH1_SHADOWREG_OR_LLI_LAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SHADOWREG_OR_LLI_VALID` reader - NA"] +pub type CH1_SHADOWREG_OR_LLI_VALID_R = crate::BitReader; +#[doc = "Field `CH1_SHADOWREG_OR_LLI_VALID` writer - NA"] +pub type CH1_SHADOWREG_OR_LLI_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + pub fn ch1_ar_prot(&self) -> CH1_AR_PROT_R { + CH1_AR_PROT_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - NA"] + #[inline(always)] + pub fn ch1_aw_prot(&self) -> CH1_AW_PROT_R { + CH1_AW_PROT_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch1_arlen_en(&self) -> CH1_ARLEN_EN_R { + CH1_ARLEN_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:14 - NA"] + #[inline(always)] + pub fn ch1_arlen(&self) -> CH1_ARLEN_R { + CH1_ARLEN_R::new(((self.bits >> 7) & 0xff) as u8) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn ch1_awlen_en(&self) -> CH1_AWLEN_EN_R { + CH1_AWLEN_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn ch1_awlen(&self) -> CH1_AWLEN_R { + CH1_AWLEN_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + pub fn ch1_src_stat_en(&self) -> CH1_SRC_STAT_EN_R { + CH1_SRC_STAT_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch1_dst_stat_en(&self) -> CH1_DST_STAT_EN_R { + CH1_DST_STAT_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - NA"] + #[inline(always)] + pub fn ch1_ioc_blktfr(&self) -> CH1_IOC_BLKTFR_R { + CH1_IOC_BLKTFR_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch1_shadowreg_or_lli_last(&self) -> CH1_SHADOWREG_OR_LLI_LAST_R { + CH1_SHADOWREG_OR_LLI_LAST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch1_shadowreg_or_lli_valid(&self) -> CH1_SHADOWREG_OR_LLI_VALID_R { + CH1_SHADOWREG_OR_LLI_VALID_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_CTL1") + .field( + "ch1_ar_prot", + &format_args!("{}", self.ch1_ar_prot().bits()), + ) + .field( + "ch1_aw_prot", + &format_args!("{}", self.ch1_aw_prot().bits()), + ) + .field( + "ch1_arlen_en", + &format_args!("{}", self.ch1_arlen_en().bit()), + ) + .field("ch1_arlen", &format_args!("{}", self.ch1_arlen().bits())) + .field( + "ch1_awlen_en", + &format_args!("{}", self.ch1_awlen_en().bit()), + ) + .field("ch1_awlen", &format_args!("{}", self.ch1_awlen().bits())) + .field( + "ch1_src_stat_en", + &format_args!("{}", self.ch1_src_stat_en().bit()), + ) + .field( + "ch1_dst_stat_en", + &format_args!("{}", self.ch1_dst_stat_en().bit()), + ) + .field( + "ch1_ioc_blktfr", + &format_args!("{}", self.ch1_ioc_blktfr().bit()), + ) + .field( + "ch1_shadowreg_or_lli_last", + &format_args!("{}", self.ch1_shadowreg_or_lli_last().bit()), + ) + .field( + "ch1_shadowreg_or_lli_valid", + &format_args!("{}", self.ch1_shadowreg_or_lli_valid().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_ar_prot(&mut self) -> CH1_AR_PROT_W { + CH1_AR_PROT_W::new(self, 0) + } + #[doc = "Bits 3:5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_aw_prot(&mut self) -> CH1_AW_PROT_W { + CH1_AW_PROT_W::new(self, 3) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_arlen_en(&mut self) -> CH1_ARLEN_EN_W { + CH1_ARLEN_EN_W::new(self, 6) + } + #[doc = "Bits 7:14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_arlen(&mut self) -> CH1_ARLEN_W { + CH1_ARLEN_W::new(self, 7) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_awlen_en(&mut self) -> CH1_AWLEN_EN_W { + CH1_AWLEN_EN_W::new(self, 15) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_awlen(&mut self) -> CH1_AWLEN_W { + CH1_AWLEN_W::new(self, 16) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_src_stat_en(&mut self) -> CH1_SRC_STAT_EN_W { + CH1_SRC_STAT_EN_W::new(self, 24) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dst_stat_en(&mut self) -> CH1_DST_STAT_EN_W { + CH1_DST_STAT_EN_W::new(self, 25) + } + #[doc = "Bit 26 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_ioc_blktfr(&mut self) -> CH1_IOC_BLKTFR_W { + CH1_IOC_BLKTFR_W::new(self, 26) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_shadowreg_or_lli_last(&mut self) -> CH1_SHADOWREG_OR_LLI_LAST_W { + CH1_SHADOWREG_OR_LLI_LAST_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_shadowreg_or_lli_valid(&mut self) -> CH1_SHADOWREG_OR_LLI_VALID_W { + CH1_SHADOWREG_OR_LLI_VALID_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_ctl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_CTL1_SPEC; +impl crate::RegisterSpec for CH1_CTL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_ctl1::R`](R) reader structure"] +impl crate::Readable for CH1_CTL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_ctl1::W`](W) writer structure"] +impl crate::Writable for CH1_CTL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_CTL1 to value 0"] +impl crate::Resettable for CH1_CTL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_dar0.rs b/esp32p4/src/dma/ch1_dar0.rs new file mode 100644 index 0000000000..ea9110fdb8 --- /dev/null +++ b/esp32p4/src/dma/ch1_dar0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH1_DAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_DAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_DAR0` reader - NA"] +pub type CH1_DAR0_R = crate::FieldReader; +#[doc = "Field `CH1_DAR0` writer - NA"] +pub type CH1_DAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch1_dar0(&self) -> CH1_DAR0_R { + CH1_DAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_DAR0") + .field("ch1_dar0", &format_args!("{}", self.ch1_dar0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dar0(&mut self) -> CH1_DAR0_W { + CH1_DAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_dar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_DAR0_SPEC; +impl crate::RegisterSpec for CH1_DAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_dar0::R`](R) reader structure"] +impl crate::Readable for CH1_DAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_dar0::W`](W) writer structure"] +impl crate::Writable for CH1_DAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_DAR0 to value 0"] +impl crate::Resettable for CH1_DAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_dar1.rs b/esp32p4/src/dma/ch1_dar1.rs new file mode 100644 index 0000000000..880344d902 --- /dev/null +++ b/esp32p4/src/dma/ch1_dar1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH1_DAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_DAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_DAR1` reader - NA"] +pub type CH1_DAR1_R = crate::FieldReader; +#[doc = "Field `CH1_DAR1` writer - NA"] +pub type CH1_DAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch1_dar1(&self) -> CH1_DAR1_R { + CH1_DAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_DAR1") + .field("ch1_dar1", &format_args!("{}", self.ch1_dar1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dar1(&mut self) -> CH1_DAR1_W { + CH1_DAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_dar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_DAR1_SPEC; +impl crate::RegisterSpec for CH1_DAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_dar1::R`](R) reader structure"] +impl crate::Readable for CH1_DAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_dar1::W`](W) writer structure"] +impl crate::Writable for CH1_DAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_DAR1 to value 0"] +impl crate::Resettable for CH1_DAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_dstat0.rs b/esp32p4/src/dma/ch1_dstat0.rs new file mode 100644 index 0000000000..0b31d0af49 --- /dev/null +++ b/esp32p4/src/dma/ch1_dstat0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `CH1_DSTAT0` reader"] +pub type R = crate::R; +#[doc = "Field `CH1_DSTAT` reader - NA"] +pub type CH1_DSTAT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch1_dstat(&self) -> CH1_DSTAT_R { + CH1_DSTAT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_DSTAT0") + .field("ch1_dstat", &format_args!("{}", self.ch1_dstat().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_dstat0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_DSTAT0_SPEC; +impl crate::RegisterSpec for CH1_DSTAT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_dstat0::R`](R) reader structure"] +impl crate::Readable for CH1_DSTAT0_SPEC {} +#[doc = "`reset()` method sets CH1_DSTAT0 to value 0"] +impl crate::Resettable for CH1_DSTAT0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_dstatar0.rs b/esp32p4/src/dma/ch1_dstatar0.rs new file mode 100644 index 0000000000..39a7de9110 --- /dev/null +++ b/esp32p4/src/dma/ch1_dstatar0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH1_DSTATAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_DSTATAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_DSTATAR0` reader - NA"] +pub type CH1_DSTATAR0_R = crate::FieldReader; +#[doc = "Field `CH1_DSTATAR0` writer - NA"] +pub type CH1_DSTATAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch1_dstatar0(&self) -> CH1_DSTATAR0_R { + CH1_DSTATAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_DSTATAR0") + .field( + "ch1_dstatar0", + &format_args!("{}", self.ch1_dstatar0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dstatar0(&mut self) -> CH1_DSTATAR0_W { + CH1_DSTATAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_dstatar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dstatar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_DSTATAR0_SPEC; +impl crate::RegisterSpec for CH1_DSTATAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_dstatar0::R`](R) reader structure"] +impl crate::Readable for CH1_DSTATAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_dstatar0::W`](W) writer structure"] +impl crate::Writable for CH1_DSTATAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_DSTATAR0 to value 0"] +impl crate::Resettable for CH1_DSTATAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_dstatar1.rs b/esp32p4/src/dma/ch1_dstatar1.rs new file mode 100644 index 0000000000..a9e7facb55 --- /dev/null +++ b/esp32p4/src/dma/ch1_dstatar1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH1_DSTATAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_DSTATAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_DSTATAR1` reader - NA"] +pub type CH1_DSTATAR1_R = crate::FieldReader; +#[doc = "Field `CH1_DSTATAR1` writer - NA"] +pub type CH1_DSTATAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch1_dstatar1(&self) -> CH1_DSTATAR1_R { + CH1_DSTATAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_DSTATAR1") + .field( + "ch1_dstatar1", + &format_args!("{}", self.ch1_dstatar1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_dstatar1(&mut self) -> CH1_DSTATAR1_W { + CH1_DSTATAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_dstatar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_dstatar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_DSTATAR1_SPEC; +impl crate::RegisterSpec for CH1_DSTATAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_dstatar1::R`](R) reader structure"] +impl crate::Readable for CH1_DSTATAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_dstatar1::W`](W) writer structure"] +impl crate::Writable for CH1_DSTATAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_DSTATAR1 to value 0"] +impl crate::Resettable for CH1_DSTATAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_intclear0.rs b/esp32p4/src/dma/ch1_intclear0.rs new file mode 100644 index 0000000000..8f78a1b5ca --- /dev/null +++ b/esp32p4/src/dma/ch1_intclear0.rs @@ -0,0 +1,294 @@ +#[doc = "Register `CH1_INTCLEAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT` writer - NA"] +pub type CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_DMA_TFR_DONE_INTSTAT` writer - NA"] +pub type CH1_CLEAR_DMA_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SRC_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_DST_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH1_CLEAR_DST_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SRC_DEC_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SRC_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_DST_DEC_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_DST_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SRC_SLV_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SRC_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_DST_SLV_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_DST_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT` writer - NA"] +pub type CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT` writer - NA"] +pub type CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_CH_SUSPENDED_INTSTAT` writer - NA"] +pub type CH1_CLEAR_CH_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_CH_DISABLED_INTSTAT` writer - NA"] +pub type CH1_CLEAR_CH_DISABLED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_CH_ABORTED_INTSTAT` writer - NA"] +pub type CH1_CLEAR_CH_ABORTED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_block_tfr_done_intstat( + &mut self, + ) -> CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_W { + CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_dma_tfr_done_intstat( + &mut self, + ) -> CH1_CLEAR_DMA_TFR_DONE_INTSTAT_W { + CH1_CLEAR_DMA_TFR_DONE_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_src_transcomp_intstat( + &mut self, + ) -> CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_W { + CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_dst_transcomp_intstat( + &mut self, + ) -> CH1_CLEAR_DST_TRANSCOMP_INTSTAT_W { + CH1_CLEAR_DST_TRANSCOMP_INTSTAT_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_src_dec_err_intstat( + &mut self, + ) -> CH1_CLEAR_SRC_DEC_ERR_INTSTAT_W { + CH1_CLEAR_SRC_DEC_ERR_INTSTAT_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_dst_dec_err_intstat( + &mut self, + ) -> CH1_CLEAR_DST_DEC_ERR_INTSTAT_W { + CH1_CLEAR_DST_DEC_ERR_INTSTAT_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_src_slv_err_intstat( + &mut self, + ) -> CH1_CLEAR_SRC_SLV_ERR_INTSTAT_W { + CH1_CLEAR_SRC_SLV_ERR_INTSTAT_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_dst_slv_err_intstat( + &mut self, + ) -> CH1_CLEAR_DST_SLV_ERR_INTSTAT_W { + CH1_CLEAR_DST_SLV_ERR_INTSTAT_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_lli_rd_dec_err_intstat( + &mut self, + ) -> CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W { + CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_lli_wr_dec_err_intstat( + &mut self, + ) -> CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W { + CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_lli_rd_slv_err_intstat( + &mut self, + ) -> CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W { + CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_lli_wr_slv_err_intstat( + &mut self, + ) -> CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W { + CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_shadowreg_or_lli_invalid_err_intstat( + &mut self, + ) -> CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W { + CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_slvif_multiblktype_err_intstat( + &mut self, + ) -> CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W { + CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_slvif_dec_err_intstat( + &mut self, + ) -> CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_W { + CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_slvif_wr2ro_err_intstat( + &mut self, + ) -> CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W { + CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_slvif_rd2rwo_err_intstat( + &mut self, + ) -> CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W { + CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_slvif_wronchen_err_intstat( + &mut self, + ) -> CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W { + CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_slvif_shadowreg_wron_valid_err_intstat( + &mut self, + ) -> CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W { + CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_slvif_wronhold_err_intstat( + &mut self, + ) -> CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W { + CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W::new(self, 21) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_slvif_wrparity_err_intstat( + &mut self, + ) -> CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W { + CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W::new(self, 25) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_ch_lock_cleared_intstat( + &mut self, + ) -> CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_W { + CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_ch_src_suspended_intstat( + &mut self, + ) -> CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W { + CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_ch_suspended_intstat( + &mut self, + ) -> CH1_CLEAR_CH_SUSPENDED_INTSTAT_W { + CH1_CLEAR_CH_SUSPENDED_INTSTAT_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_ch_disabled_intstat( + &mut self, + ) -> CH1_CLEAR_CH_DISABLED_INTSTAT_W { + CH1_CLEAR_CH_DISABLED_INTSTAT_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_ch_aborted_intstat( + &mut self, + ) -> CH1_CLEAR_CH_ABORTED_INTSTAT_W { + CH1_CLEAR_CH_ABORTED_INTSTAT_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_intclear0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_INTCLEAR0_SPEC; +impl crate::RegisterSpec for CH1_INTCLEAR0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch1_intclear0::W`](W) writer structure"] +impl crate::Writable for CH1_INTCLEAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_INTCLEAR0 to value 0"] +impl crate::Resettable for CH1_INTCLEAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_intclear1.rs b/esp32p4/src/dma/ch1_intclear1.rs new file mode 100644 index 0000000000..c8b16cbdbb --- /dev/null +++ b/esp32p4/src/dma/ch1_intclear1.rs @@ -0,0 +1,74 @@ +#[doc = "Register `CH1_INTCLEAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` writer - NA"] +pub type CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_ecc_prot_chmem_correrr_intstat( + &mut self, + ) -> CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W { + CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_ecc_prot_chmem_uncorrerr_intstat( + &mut self, + ) -> CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W { + CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_ecc_prot_uidmem_correrr_intstat( + &mut self, + ) -> CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W { + CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_clear_ecc_prot_uidmem_uncorrerr_intstat( + &mut self, + ) -> CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W { + CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_intclear1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_INTCLEAR1_SPEC; +impl crate::RegisterSpec for CH1_INTCLEAR1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch1_intclear1::W`](W) writer structure"] +impl crate::Writable for CH1_INTCLEAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_INTCLEAR1 to value 0"] +impl crate::Resettable for CH1_INTCLEAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_intsignal_enable0.rs b/esp32p4/src/dma/ch1_intsignal_enable0.rs new file mode 100644 index 0000000000..e4ad1ac90c --- /dev/null +++ b/esp32p4/src/dma/ch1_intsignal_enable0.rs @@ -0,0 +1,606 @@ +#[doc = "Register `CH1_INTSIGNAL_ENABLE0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_INTSIGNAL_ENABLE0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_DST_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_DST_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_DST_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_DST_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_CH_SUSPENDED_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_SUSPENDED_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_CH_DISABLED_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_CH_DISABLED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_DISABLED_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_CH_DISABLED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_CH_ABORTED_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_CH_ABORTED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_ABORTED_INTSIGNAL` writer - NA"] +pub type CH1_ENABLE_CH_ABORTED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_enable_block_tfr_done_intsignal(&self) -> CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R { + CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch1_enable_dma_tfr_done_intsignal(&self) -> CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_R { + CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch1_enable_src_transcomp_intsignal(&self) -> CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R { + CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch1_enable_dst_transcomp_intsignal(&self) -> CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_R { + CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch1_enable_src_dec_err_intsignal(&self) -> CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_R { + CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch1_enable_dst_dec_err_intsignal(&self) -> CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_R { + CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch1_enable_src_slv_err_intsignal(&self) -> CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_R { + CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch1_enable_dst_slv_err_intsignal(&self) -> CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_R { + CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch1_enable_lli_rd_dec_err_intsignal(&self) -> CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R { + CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch1_enable_lli_wr_dec_err_intsignal(&self) -> CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R { + CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch1_enable_lli_rd_slv_err_intsignal(&self) -> CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R { + CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch1_enable_lli_wr_slv_err_intsignal(&self) -> CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R { + CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch1_enable_shadowreg_or_lli_invalid_err_intsignal( + &self, + ) -> CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R { + CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_multiblktype_err_intsignal( + &self, + ) -> CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R { + CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_dec_err_intsignal(&self) -> CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R { + CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_wr2ro_err_intsignal(&self) -> CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R { + CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_rd2rwo_err_intsignal(&self) -> CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R { + CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_wronchen_err_intsignal( + &self, + ) -> CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R { + CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_shadowreg_wron_valid_err_intsignal( + &self, + ) -> CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R { + CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_wronhold_err_intsignal( + &self, + ) -> CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R { + CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_wrparity_err_intsignal( + &self, + ) -> CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R { + CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch1_enable_ch_lock_cleared_intsignal(&self) -> CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R { + CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch1_enable_ch_src_suspended_intsignal(&self) -> CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R { + CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch1_enable_ch_suspended_intsignal(&self) -> CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_R { + CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch1_enable_ch_disabled_intsignal(&self) -> CH1_ENABLE_CH_DISABLED_INTSIGNAL_R { + CH1_ENABLE_CH_DISABLED_INTSIGNAL_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch1_enable_ch_aborted_intsignal(&self) -> CH1_ENABLE_CH_ABORTED_INTSIGNAL_R { + CH1_ENABLE_CH_ABORTED_INTSIGNAL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_INTSIGNAL_ENABLE0") + .field( + "ch1_enable_block_tfr_done_intsignal", + &format_args!("{}", self.ch1_enable_block_tfr_done_intsignal().bit()), + ) + .field( + "ch1_enable_dma_tfr_done_intsignal", + &format_args!("{}", self.ch1_enable_dma_tfr_done_intsignal().bit()), + ) + .field( + "ch1_enable_src_transcomp_intsignal", + &format_args!("{}", self.ch1_enable_src_transcomp_intsignal().bit()), + ) + .field( + "ch1_enable_dst_transcomp_intsignal", + &format_args!("{}", self.ch1_enable_dst_transcomp_intsignal().bit()), + ) + .field( + "ch1_enable_src_dec_err_intsignal", + &format_args!("{}", self.ch1_enable_src_dec_err_intsignal().bit()), + ) + .field( + "ch1_enable_dst_dec_err_intsignal", + &format_args!("{}", self.ch1_enable_dst_dec_err_intsignal().bit()), + ) + .field( + "ch1_enable_src_slv_err_intsignal", + &format_args!("{}", self.ch1_enable_src_slv_err_intsignal().bit()), + ) + .field( + "ch1_enable_dst_slv_err_intsignal", + &format_args!("{}", self.ch1_enable_dst_slv_err_intsignal().bit()), + ) + .field( + "ch1_enable_lli_rd_dec_err_intsignal", + &format_args!("{}", self.ch1_enable_lli_rd_dec_err_intsignal().bit()), + ) + .field( + "ch1_enable_lli_wr_dec_err_intsignal", + &format_args!("{}", self.ch1_enable_lli_wr_dec_err_intsignal().bit()), + ) + .field( + "ch1_enable_lli_rd_slv_err_intsignal", + &format_args!("{}", self.ch1_enable_lli_rd_slv_err_intsignal().bit()), + ) + .field( + "ch1_enable_lli_wr_slv_err_intsignal", + &format_args!("{}", self.ch1_enable_lli_wr_slv_err_intsignal().bit()), + ) + .field( + "ch1_enable_shadowreg_or_lli_invalid_err_intsignal", + &format_args!( + "{}", + self.ch1_enable_shadowreg_or_lli_invalid_err_intsignal() + .bit() + ), + ) + .field( + "ch1_enable_slvif_multiblktype_err_intsignal", + &format_args!( + "{}", + self.ch1_enable_slvif_multiblktype_err_intsignal().bit() + ), + ) + .field( + "ch1_enable_slvif_dec_err_intsignal", + &format_args!("{}", self.ch1_enable_slvif_dec_err_intsignal().bit()), + ) + .field( + "ch1_enable_slvif_wr2ro_err_intsignal", + &format_args!("{}", self.ch1_enable_slvif_wr2ro_err_intsignal().bit()), + ) + .field( + "ch1_enable_slvif_rd2rwo_err_intsignal", + &format_args!("{}", self.ch1_enable_slvif_rd2rwo_err_intsignal().bit()), + ) + .field( + "ch1_enable_slvif_wronchen_err_intsignal", + &format_args!("{}", self.ch1_enable_slvif_wronchen_err_intsignal().bit()), + ) + .field( + "ch1_enable_slvif_shadowreg_wron_valid_err_intsignal", + &format_args!( + "{}", + self.ch1_enable_slvif_shadowreg_wron_valid_err_intsignal() + .bit() + ), + ) + .field( + "ch1_enable_slvif_wronhold_err_intsignal", + &format_args!("{}", self.ch1_enable_slvif_wronhold_err_intsignal().bit()), + ) + .field( + "ch1_enable_slvif_wrparity_err_intsignal", + &format_args!("{}", self.ch1_enable_slvif_wrparity_err_intsignal().bit()), + ) + .field( + "ch1_enable_ch_lock_cleared_intsignal", + &format_args!("{}", self.ch1_enable_ch_lock_cleared_intsignal().bit()), + ) + .field( + "ch1_enable_ch_src_suspended_intsignal", + &format_args!("{}", self.ch1_enable_ch_src_suspended_intsignal().bit()), + ) + .field( + "ch1_enable_ch_suspended_intsignal", + &format_args!("{}", self.ch1_enable_ch_suspended_intsignal().bit()), + ) + .field( + "ch1_enable_ch_disabled_intsignal", + &format_args!("{}", self.ch1_enable_ch_disabled_intsignal().bit()), + ) + .field( + "ch1_enable_ch_aborted_intsignal", + &format_args!("{}", self.ch1_enable_ch_aborted_intsignal().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_block_tfr_done_intsignal( + &mut self, + ) -> CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W { + CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_dma_tfr_done_intsignal( + &mut self, + ) -> CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_W { + CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_src_transcomp_intsignal( + &mut self, + ) -> CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W { + CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_dst_transcomp_intsignal( + &mut self, + ) -> CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_W { + CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_src_dec_err_intsignal( + &mut self, + ) -> CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_W { + CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_dst_dec_err_intsignal( + &mut self, + ) -> CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_W { + CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_src_slv_err_intsignal( + &mut self, + ) -> CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_W { + CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_dst_slv_err_intsignal( + &mut self, + ) -> CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_W { + CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_lli_rd_dec_err_intsignal( + &mut self, + ) -> CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W { + CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_lli_wr_dec_err_intsignal( + &mut self, + ) -> CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W { + CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_lli_rd_slv_err_intsignal( + &mut self, + ) -> CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W { + CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_lli_wr_slv_err_intsignal( + &mut self, + ) -> CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W { + CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_shadowreg_or_lli_invalid_err_intsignal( + &mut self, + ) -> CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W { + CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_multiblktype_err_intsignal( + &mut self, + ) -> CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W { + CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_dec_err_intsignal( + &mut self, + ) -> CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W { + CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_wr2ro_err_intsignal( + &mut self, + ) -> CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W { + CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_rd2rwo_err_intsignal( + &mut self, + ) -> CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W { + CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_wronchen_err_intsignal( + &mut self, + ) -> CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W { + CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_shadowreg_wron_valid_err_intsignal( + &mut self, + ) -> CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W { + CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_wronhold_err_intsignal( + &mut self, + ) -> CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W { + CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W::new(self, 21) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_ch_lock_cleared_intsignal( + &mut self, + ) -> CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W { + CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_ch_src_suspended_intsignal( + &mut self, + ) -> CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W { + CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_ch_suspended_intsignal( + &mut self, + ) -> CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_W { + CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_ch_disabled_intsignal( + &mut self, + ) -> CH1_ENABLE_CH_DISABLED_INTSIGNAL_W { + CH1_ENABLE_CH_DISABLED_INTSIGNAL_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_ch_aborted_intsignal( + &mut self, + ) -> CH1_ENABLE_CH_ABORTED_INTSIGNAL_W { + CH1_ENABLE_CH_ABORTED_INTSIGNAL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intsignal_enable0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_intsignal_enable0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_INTSIGNAL_ENABLE0_SPEC; +impl crate::RegisterSpec for CH1_INTSIGNAL_ENABLE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_intsignal_enable0::R`](R) reader structure"] +impl crate::Readable for CH1_INTSIGNAL_ENABLE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_intsignal_enable0::W`](W) writer structure"] +impl crate::Writable for CH1_INTSIGNAL_ENABLE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_INTSIGNAL_ENABLE0 to value 0xfa3f_7ffb"] +impl crate::Resettable for CH1_INTSIGNAL_ENABLE0_SPEC { + const RESET_VALUE: Self::Ux = 0xfa3f_7ffb; +} diff --git a/esp32p4/src/dma/ch1_intsignal_enable1.rs b/esp32p4/src/dma/ch1_intsignal_enable1.rs new file mode 100644 index 0000000000..5f25dd02b8 --- /dev/null +++ b/esp32p4/src/dma/ch1_intsignal_enable1.rs @@ -0,0 +1,92 @@ +#[doc = "Register `CH1_INTSIGNAL_ENABLE1` reader"] +pub type R = crate::R; +#[doc = "Field `CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL` reader - NA"] +pub type CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_enable_ecc_prot_chmem_correrr_intsignal( + &self, + ) -> CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R { + CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch1_enable_ecc_prot_chmem_uncorrerr_intsignal( + &self, + ) -> CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R { + CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch1_enable_ecc_prot_uidmem_correrr_intsignal( + &self, + ) -> CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R { + CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal( + &self, + ) -> CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R { + CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_INTSIGNAL_ENABLE1") + .field( + "ch1_enable_ecc_prot_chmem_correrr_intsignal", + &format_args!( + "{}", + self.ch1_enable_ecc_prot_chmem_correrr_intsignal().bit() + ), + ) + .field( + "ch1_enable_ecc_prot_chmem_uncorrerr_intsignal", + &format_args!( + "{}", + self.ch1_enable_ecc_prot_chmem_uncorrerr_intsignal().bit() + ), + ) + .field( + "ch1_enable_ecc_prot_uidmem_correrr_intsignal", + &format_args!( + "{}", + self.ch1_enable_ecc_prot_uidmem_correrr_intsignal().bit() + ), + ) + .field( + "ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal", + &format_args!( + "{}", + self.ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal().bit() + ), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intsignal_enable1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_INTSIGNAL_ENABLE1_SPEC; +impl crate::RegisterSpec for CH1_INTSIGNAL_ENABLE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_intsignal_enable1::R`](R) reader structure"] +impl crate::Readable for CH1_INTSIGNAL_ENABLE1_SPEC {} +#[doc = "`reset()` method sets CH1_INTSIGNAL_ENABLE1 to value 0x0f"] +impl crate::Resettable for CH1_INTSIGNAL_ENABLE1_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/dma/ch1_intstatus0.rs b/esp32p4/src/dma/ch1_intstatus0.rs new file mode 100644 index 0000000000..f74201e423 --- /dev/null +++ b/esp32p4/src/dma/ch1_intstatus0.rs @@ -0,0 +1,321 @@ +#[doc = "Register `CH1_INTSTATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `CH1_BLOCK_TFR_DONE_INTSTAT` reader - NA"] +pub type CH1_BLOCK_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_DMA_TFR_DONE_INTSTAT` reader - NA"] +pub type CH1_DMA_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SRC_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH1_SRC_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_DST_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH1_DST_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SRC_DEC_ERR_INTSTAT` reader - NA"] +pub type CH1_SRC_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_DST_DEC_ERR_INTSTAT` reader - NA"] +pub type CH1_DST_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SRC_SLV_ERR_INTSTAT` reader - NA"] +pub type CH1_SRC_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_DST_SLV_ERR_INTSTAT` reader - NA"] +pub type CH1_DST_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_LLI_RD_DEC_ERR_INTSTAT` reader - NA"] +pub type CH1_LLI_RD_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_LLI_WR_DEC_ERR_INTSTAT` reader - NA"] +pub type CH1_LLI_WR_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_LLI_RD_SLV_ERR_INTSTAT` reader - NA"] +pub type CH1_LLI_RD_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_LLI_WR_SLV_ERR_INTSTAT` reader - NA"] +pub type CH1_LLI_WR_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` reader - NA"] +pub type CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` reader - NA"] +pub type CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SLVIF_DEC_ERR_INTSTAT` reader - NA"] +pub type CH1_SLVIF_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SLVIF_WR2RO_ERR_INTSTAT` reader - NA"] +pub type CH1_SLVIF_WR2RO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SLVIF_RD2RWO_ERR_INTSTAT` reader - NA"] +pub type CH1_SLVIF_RD2RWO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SLVIF_WRONCHEN_ERR_INTSTAT` reader - NA"] +pub type CH1_SLVIF_WRONCHEN_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` reader - NA"] +pub type CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SLVIF_WRONHOLD_ERR_INTSTAT` reader - NA"] +pub type CH1_SLVIF_WRONHOLD_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_SLVIF_WRPARITY_ERR_INTSTAT` reader - NA"] +pub type CH1_SLVIF_WRPARITY_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_CH_LOCK_CLEARED_INTSTAT` reader - NA"] +pub type CH1_CH_LOCK_CLEARED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_CH_SRC_SUSPENDED_INTSTAT` reader - NA"] +pub type CH1_CH_SRC_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_CH_SUSPENDED_INTSTAT` reader - NA"] +pub type CH1_CH_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_CH_DISABLED_INTSTAT` reader - NA"] +pub type CH1_CH_DISABLED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_CH_ABORTED_INTSTAT` reader - NA"] +pub type CH1_CH_ABORTED_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_block_tfr_done_intstat(&self) -> CH1_BLOCK_TFR_DONE_INTSTAT_R { + CH1_BLOCK_TFR_DONE_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch1_dma_tfr_done_intstat(&self) -> CH1_DMA_TFR_DONE_INTSTAT_R { + CH1_DMA_TFR_DONE_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch1_src_transcomp_intstat(&self) -> CH1_SRC_TRANSCOMP_INTSTAT_R { + CH1_SRC_TRANSCOMP_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch1_dst_transcomp_intstat(&self) -> CH1_DST_TRANSCOMP_INTSTAT_R { + CH1_DST_TRANSCOMP_INTSTAT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch1_src_dec_err_intstat(&self) -> CH1_SRC_DEC_ERR_INTSTAT_R { + CH1_SRC_DEC_ERR_INTSTAT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch1_dst_dec_err_intstat(&self) -> CH1_DST_DEC_ERR_INTSTAT_R { + CH1_DST_DEC_ERR_INTSTAT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch1_src_slv_err_intstat(&self) -> CH1_SRC_SLV_ERR_INTSTAT_R { + CH1_SRC_SLV_ERR_INTSTAT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch1_dst_slv_err_intstat(&self) -> CH1_DST_SLV_ERR_INTSTAT_R { + CH1_DST_SLV_ERR_INTSTAT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch1_lli_rd_dec_err_intstat(&self) -> CH1_LLI_RD_DEC_ERR_INTSTAT_R { + CH1_LLI_RD_DEC_ERR_INTSTAT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch1_lli_wr_dec_err_intstat(&self) -> CH1_LLI_WR_DEC_ERR_INTSTAT_R { + CH1_LLI_WR_DEC_ERR_INTSTAT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch1_lli_rd_slv_err_intstat(&self) -> CH1_LLI_RD_SLV_ERR_INTSTAT_R { + CH1_LLI_RD_SLV_ERR_INTSTAT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch1_lli_wr_slv_err_intstat(&self) -> CH1_LLI_WR_SLV_ERR_INTSTAT_R { + CH1_LLI_WR_SLV_ERR_INTSTAT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch1_shadowreg_or_lli_invalid_err_intstat( + &self, + ) -> CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R { + CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch1_slvif_multiblktype_err_intstat(&self) -> CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R { + CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch1_slvif_dec_err_intstat(&self) -> CH1_SLVIF_DEC_ERR_INTSTAT_R { + CH1_SLVIF_DEC_ERR_INTSTAT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch1_slvif_wr2ro_err_intstat(&self) -> CH1_SLVIF_WR2RO_ERR_INTSTAT_R { + CH1_SLVIF_WR2RO_ERR_INTSTAT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch1_slvif_rd2rwo_err_intstat(&self) -> CH1_SLVIF_RD2RWO_ERR_INTSTAT_R { + CH1_SLVIF_RD2RWO_ERR_INTSTAT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch1_slvif_wronchen_err_intstat(&self) -> CH1_SLVIF_WRONCHEN_ERR_INTSTAT_R { + CH1_SLVIF_WRONCHEN_ERR_INTSTAT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch1_slvif_shadowreg_wron_valid_err_intstat( + &self, + ) -> CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R { + CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch1_slvif_wronhold_err_intstat(&self) -> CH1_SLVIF_WRONHOLD_ERR_INTSTAT_R { + CH1_SLVIF_WRONHOLD_ERR_INTSTAT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch1_slvif_wrparity_err_intstat(&self) -> CH1_SLVIF_WRPARITY_ERR_INTSTAT_R { + CH1_SLVIF_WRPARITY_ERR_INTSTAT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch1_ch_lock_cleared_intstat(&self) -> CH1_CH_LOCK_CLEARED_INTSTAT_R { + CH1_CH_LOCK_CLEARED_INTSTAT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch1_ch_src_suspended_intstat(&self) -> CH1_CH_SRC_SUSPENDED_INTSTAT_R { + CH1_CH_SRC_SUSPENDED_INTSTAT_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch1_ch_suspended_intstat(&self) -> CH1_CH_SUSPENDED_INTSTAT_R { + CH1_CH_SUSPENDED_INTSTAT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch1_ch_disabled_intstat(&self) -> CH1_CH_DISABLED_INTSTAT_R { + CH1_CH_DISABLED_INTSTAT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch1_ch_aborted_intstat(&self) -> CH1_CH_ABORTED_INTSTAT_R { + CH1_CH_ABORTED_INTSTAT_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_INTSTATUS0") + .field( + "ch1_block_tfr_done_intstat", + &format_args!("{}", self.ch1_block_tfr_done_intstat().bit()), + ) + .field( + "ch1_dma_tfr_done_intstat", + &format_args!("{}", self.ch1_dma_tfr_done_intstat().bit()), + ) + .field( + "ch1_src_transcomp_intstat", + &format_args!("{}", self.ch1_src_transcomp_intstat().bit()), + ) + .field( + "ch1_dst_transcomp_intstat", + &format_args!("{}", self.ch1_dst_transcomp_intstat().bit()), + ) + .field( + "ch1_src_dec_err_intstat", + &format_args!("{}", self.ch1_src_dec_err_intstat().bit()), + ) + .field( + "ch1_dst_dec_err_intstat", + &format_args!("{}", self.ch1_dst_dec_err_intstat().bit()), + ) + .field( + "ch1_src_slv_err_intstat", + &format_args!("{}", self.ch1_src_slv_err_intstat().bit()), + ) + .field( + "ch1_dst_slv_err_intstat", + &format_args!("{}", self.ch1_dst_slv_err_intstat().bit()), + ) + .field( + "ch1_lli_rd_dec_err_intstat", + &format_args!("{}", self.ch1_lli_rd_dec_err_intstat().bit()), + ) + .field( + "ch1_lli_wr_dec_err_intstat", + &format_args!("{}", self.ch1_lli_wr_dec_err_intstat().bit()), + ) + .field( + "ch1_lli_rd_slv_err_intstat", + &format_args!("{}", self.ch1_lli_rd_slv_err_intstat().bit()), + ) + .field( + "ch1_lli_wr_slv_err_intstat", + &format_args!("{}", self.ch1_lli_wr_slv_err_intstat().bit()), + ) + .field( + "ch1_shadowreg_or_lli_invalid_err_intstat", + &format_args!("{}", self.ch1_shadowreg_or_lli_invalid_err_intstat().bit()), + ) + .field( + "ch1_slvif_multiblktype_err_intstat", + &format_args!("{}", self.ch1_slvif_multiblktype_err_intstat().bit()), + ) + .field( + "ch1_slvif_dec_err_intstat", + &format_args!("{}", self.ch1_slvif_dec_err_intstat().bit()), + ) + .field( + "ch1_slvif_wr2ro_err_intstat", + &format_args!("{}", self.ch1_slvif_wr2ro_err_intstat().bit()), + ) + .field( + "ch1_slvif_rd2rwo_err_intstat", + &format_args!("{}", self.ch1_slvif_rd2rwo_err_intstat().bit()), + ) + .field( + "ch1_slvif_wronchen_err_intstat", + &format_args!("{}", self.ch1_slvif_wronchen_err_intstat().bit()), + ) + .field( + "ch1_slvif_shadowreg_wron_valid_err_intstat", + &format_args!( + "{}", + self.ch1_slvif_shadowreg_wron_valid_err_intstat().bit() + ), + ) + .field( + "ch1_slvif_wronhold_err_intstat", + &format_args!("{}", self.ch1_slvif_wronhold_err_intstat().bit()), + ) + .field( + "ch1_slvif_wrparity_err_intstat", + &format_args!("{}", self.ch1_slvif_wrparity_err_intstat().bit()), + ) + .field( + "ch1_ch_lock_cleared_intstat", + &format_args!("{}", self.ch1_ch_lock_cleared_intstat().bit()), + ) + .field( + "ch1_ch_src_suspended_intstat", + &format_args!("{}", self.ch1_ch_src_suspended_intstat().bit()), + ) + .field( + "ch1_ch_suspended_intstat", + &format_args!("{}", self.ch1_ch_suspended_intstat().bit()), + ) + .field( + "ch1_ch_disabled_intstat", + &format_args!("{}", self.ch1_ch_disabled_intstat().bit()), + ) + .field( + "ch1_ch_aborted_intstat", + &format_args!("{}", self.ch1_ch_aborted_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intstatus0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_INTSTATUS0_SPEC; +impl crate::RegisterSpec for CH1_INTSTATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_intstatus0::R`](R) reader structure"] +impl crate::Readable for CH1_INTSTATUS0_SPEC {} +#[doc = "`reset()` method sets CH1_INTSTATUS0 to value 0"] +impl crate::Resettable for CH1_INTSTATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_intstatus1.rs b/esp32p4/src/dma/ch1_intstatus1.rs new file mode 100644 index 0000000000..7e52f6a28c --- /dev/null +++ b/esp32p4/src/dma/ch1_intstatus1.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CH1_INTSTATUS1` reader"] +pub type R = crate::R; +#[doc = "Field `CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_ecc_prot_chmem_correrr_intstat(&self) -> CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_R { + CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch1_ecc_prot_chmem_uncorrerr_intstat(&self) -> CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R { + CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch1_ecc_prot_uidmem_correrr_intstat(&self) -> CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R { + CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch1_ecc_prot_uidmem_uncorrerr_intstat(&self) -> CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R { + CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_INTSTATUS1") + .field( + "ch1_ecc_prot_chmem_correrr_intstat", + &format_args!("{}", self.ch1_ecc_prot_chmem_correrr_intstat().bit()), + ) + .field( + "ch1_ecc_prot_chmem_uncorrerr_intstat", + &format_args!("{}", self.ch1_ecc_prot_chmem_uncorrerr_intstat().bit()), + ) + .field( + "ch1_ecc_prot_uidmem_correrr_intstat", + &format_args!("{}", self.ch1_ecc_prot_uidmem_correrr_intstat().bit()), + ) + .field( + "ch1_ecc_prot_uidmem_uncorrerr_intstat", + &format_args!("{}", self.ch1_ecc_prot_uidmem_uncorrerr_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intstatus1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_INTSTATUS1_SPEC; +impl crate::RegisterSpec for CH1_INTSTATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_intstatus1::R`](R) reader structure"] +impl crate::Readable for CH1_INTSTATUS1_SPEC {} +#[doc = "`reset()` method sets CH1_INTSTATUS1 to value 0"] +impl crate::Resettable for CH1_INTSTATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_intstatus_enable0.rs b/esp32p4/src/dma/ch1_intstatus_enable0.rs new file mode 100644 index 0000000000..d0ba94f4d0 --- /dev/null +++ b/esp32p4/src/dma/ch1_intstatus_enable0.rs @@ -0,0 +1,596 @@ +#[doc = "Register `CH1_INTSTATUS_ENABLE0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_INTSTATUS_ENABLE0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT` reader - NA"] +pub type CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT` writer - NA"] +pub type CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_DMA_TFR_DONE_INTSTAT` reader - NA"] +pub type CH1_ENABLE_DMA_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_DMA_TFR_DONE_INTSTAT` writer - NA"] +pub type CH1_ENABLE_DMA_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SRC_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SRC_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_DST_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH1_ENABLE_DST_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_DST_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH1_ENABLE_DST_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SRC_DEC_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SRC_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SRC_DEC_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_SRC_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_DST_DEC_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_DST_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_DST_DEC_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_DST_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SRC_SLV_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SRC_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SRC_SLV_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_SRC_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_DST_SLV_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_DST_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_DST_SLV_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_DST_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT` writer - NA"] +pub type CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT` reader - NA"] +pub type CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT` writer - NA"] +pub type CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT` reader - NA"] +pub type CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT` writer - NA"] +pub type CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_CH_SUSPENDED_INTSTAT` reader - NA"] +pub type CH1_ENABLE_CH_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_SUSPENDED_INTSTAT` writer - NA"] +pub type CH1_ENABLE_CH_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_CH_DISABLED_INTSTAT` reader - NA"] +pub type CH1_ENABLE_CH_DISABLED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_DISABLED_INTSTAT` writer - NA"] +pub type CH1_ENABLE_CH_DISABLED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ENABLE_CH_ABORTED_INTSTAT` reader - NA"] +pub type CH1_ENABLE_CH_ABORTED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_CH_ABORTED_INTSTAT` writer - NA"] +pub type CH1_ENABLE_CH_ABORTED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_enable_block_tfr_done_intstat(&self) -> CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_R { + CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch1_enable_dma_tfr_done_intstat(&self) -> CH1_ENABLE_DMA_TFR_DONE_INTSTAT_R { + CH1_ENABLE_DMA_TFR_DONE_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch1_enable_src_transcomp_intstat(&self) -> CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_R { + CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch1_enable_dst_transcomp_intstat(&self) -> CH1_ENABLE_DST_TRANSCOMP_INTSTAT_R { + CH1_ENABLE_DST_TRANSCOMP_INTSTAT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch1_enable_src_dec_err_intstat(&self) -> CH1_ENABLE_SRC_DEC_ERR_INTSTAT_R { + CH1_ENABLE_SRC_DEC_ERR_INTSTAT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch1_enable_dst_dec_err_intstat(&self) -> CH1_ENABLE_DST_DEC_ERR_INTSTAT_R { + CH1_ENABLE_DST_DEC_ERR_INTSTAT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch1_enable_src_slv_err_intstat(&self) -> CH1_ENABLE_SRC_SLV_ERR_INTSTAT_R { + CH1_ENABLE_SRC_SLV_ERR_INTSTAT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch1_enable_dst_slv_err_intstat(&self) -> CH1_ENABLE_DST_SLV_ERR_INTSTAT_R { + CH1_ENABLE_DST_SLV_ERR_INTSTAT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch1_enable_lli_rd_dec_err_intstat(&self) -> CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R { + CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch1_enable_lli_wr_dec_err_intstat(&self) -> CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R { + CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch1_enable_lli_rd_slv_err_intstat(&self) -> CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R { + CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch1_enable_lli_wr_slv_err_intstat(&self) -> CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R { + CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch1_enable_shadowreg_or_lli_invalid_err_intstat( + &self, + ) -> CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R { + CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_multiblktype_err_intstat( + &self, + ) -> CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R { + CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_dec_err_intstat(&self) -> CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_R { + CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_wr2ro_err_intstat(&self) -> CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R { + CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_rd2rwo_err_intstat(&self) -> CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R { + CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_wronchen_err_intstat(&self) -> CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R { + CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_shadowreg_wron_valid_err_intstat( + &self, + ) -> CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R { + CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_wronhold_err_intstat(&self) -> CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R { + CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch1_enable_slvif_wrparity_err_intstat(&self) -> CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R { + CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch1_enable_ch_lock_cleared_intstat(&self) -> CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_R { + CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch1_enable_ch_src_suspended_intstat(&self) -> CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R { + CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch1_enable_ch_suspended_intstat(&self) -> CH1_ENABLE_CH_SUSPENDED_INTSTAT_R { + CH1_ENABLE_CH_SUSPENDED_INTSTAT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch1_enable_ch_disabled_intstat(&self) -> CH1_ENABLE_CH_DISABLED_INTSTAT_R { + CH1_ENABLE_CH_DISABLED_INTSTAT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch1_enable_ch_aborted_intstat(&self) -> CH1_ENABLE_CH_ABORTED_INTSTAT_R { + CH1_ENABLE_CH_ABORTED_INTSTAT_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_INTSTATUS_ENABLE0") + .field( + "ch1_enable_block_tfr_done_intstat", + &format_args!("{}", self.ch1_enable_block_tfr_done_intstat().bit()), + ) + .field( + "ch1_enable_dma_tfr_done_intstat", + &format_args!("{}", self.ch1_enable_dma_tfr_done_intstat().bit()), + ) + .field( + "ch1_enable_src_transcomp_intstat", + &format_args!("{}", self.ch1_enable_src_transcomp_intstat().bit()), + ) + .field( + "ch1_enable_dst_transcomp_intstat", + &format_args!("{}", self.ch1_enable_dst_transcomp_intstat().bit()), + ) + .field( + "ch1_enable_src_dec_err_intstat", + &format_args!("{}", self.ch1_enable_src_dec_err_intstat().bit()), + ) + .field( + "ch1_enable_dst_dec_err_intstat", + &format_args!("{}", self.ch1_enable_dst_dec_err_intstat().bit()), + ) + .field( + "ch1_enable_src_slv_err_intstat", + &format_args!("{}", self.ch1_enable_src_slv_err_intstat().bit()), + ) + .field( + "ch1_enable_dst_slv_err_intstat", + &format_args!("{}", self.ch1_enable_dst_slv_err_intstat().bit()), + ) + .field( + "ch1_enable_lli_rd_dec_err_intstat", + &format_args!("{}", self.ch1_enable_lli_rd_dec_err_intstat().bit()), + ) + .field( + "ch1_enable_lli_wr_dec_err_intstat", + &format_args!("{}", self.ch1_enable_lli_wr_dec_err_intstat().bit()), + ) + .field( + "ch1_enable_lli_rd_slv_err_intstat", + &format_args!("{}", self.ch1_enable_lli_rd_slv_err_intstat().bit()), + ) + .field( + "ch1_enable_lli_wr_slv_err_intstat", + &format_args!("{}", self.ch1_enable_lli_wr_slv_err_intstat().bit()), + ) + .field( + "ch1_enable_shadowreg_or_lli_invalid_err_intstat", + &format_args!( + "{}", + self.ch1_enable_shadowreg_or_lli_invalid_err_intstat().bit() + ), + ) + .field( + "ch1_enable_slvif_multiblktype_err_intstat", + &format_args!("{}", self.ch1_enable_slvif_multiblktype_err_intstat().bit()), + ) + .field( + "ch1_enable_slvif_dec_err_intstat", + &format_args!("{}", self.ch1_enable_slvif_dec_err_intstat().bit()), + ) + .field( + "ch1_enable_slvif_wr2ro_err_intstat", + &format_args!("{}", self.ch1_enable_slvif_wr2ro_err_intstat().bit()), + ) + .field( + "ch1_enable_slvif_rd2rwo_err_intstat", + &format_args!("{}", self.ch1_enable_slvif_rd2rwo_err_intstat().bit()), + ) + .field( + "ch1_enable_slvif_wronchen_err_intstat", + &format_args!("{}", self.ch1_enable_slvif_wronchen_err_intstat().bit()), + ) + .field( + "ch1_enable_slvif_shadowreg_wron_valid_err_intstat", + &format_args!( + "{}", + self.ch1_enable_slvif_shadowreg_wron_valid_err_intstat() + .bit() + ), + ) + .field( + "ch1_enable_slvif_wronhold_err_intstat", + &format_args!("{}", self.ch1_enable_slvif_wronhold_err_intstat().bit()), + ) + .field( + "ch1_enable_slvif_wrparity_err_intstat", + &format_args!("{}", self.ch1_enable_slvif_wrparity_err_intstat().bit()), + ) + .field( + "ch1_enable_ch_lock_cleared_intstat", + &format_args!("{}", self.ch1_enable_ch_lock_cleared_intstat().bit()), + ) + .field( + "ch1_enable_ch_src_suspended_intstat", + &format_args!("{}", self.ch1_enable_ch_src_suspended_intstat().bit()), + ) + .field( + "ch1_enable_ch_suspended_intstat", + &format_args!("{}", self.ch1_enable_ch_suspended_intstat().bit()), + ) + .field( + "ch1_enable_ch_disabled_intstat", + &format_args!("{}", self.ch1_enable_ch_disabled_intstat().bit()), + ) + .field( + "ch1_enable_ch_aborted_intstat", + &format_args!("{}", self.ch1_enable_ch_aborted_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_block_tfr_done_intstat( + &mut self, + ) -> CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_W { + CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_dma_tfr_done_intstat( + &mut self, + ) -> CH1_ENABLE_DMA_TFR_DONE_INTSTAT_W { + CH1_ENABLE_DMA_TFR_DONE_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_src_transcomp_intstat( + &mut self, + ) -> CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_W { + CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_dst_transcomp_intstat( + &mut self, + ) -> CH1_ENABLE_DST_TRANSCOMP_INTSTAT_W { + CH1_ENABLE_DST_TRANSCOMP_INTSTAT_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_src_dec_err_intstat( + &mut self, + ) -> CH1_ENABLE_SRC_DEC_ERR_INTSTAT_W { + CH1_ENABLE_SRC_DEC_ERR_INTSTAT_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_dst_dec_err_intstat( + &mut self, + ) -> CH1_ENABLE_DST_DEC_ERR_INTSTAT_W { + CH1_ENABLE_DST_DEC_ERR_INTSTAT_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_src_slv_err_intstat( + &mut self, + ) -> CH1_ENABLE_SRC_SLV_ERR_INTSTAT_W { + CH1_ENABLE_SRC_SLV_ERR_INTSTAT_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_dst_slv_err_intstat( + &mut self, + ) -> CH1_ENABLE_DST_SLV_ERR_INTSTAT_W { + CH1_ENABLE_DST_SLV_ERR_INTSTAT_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_lli_rd_dec_err_intstat( + &mut self, + ) -> CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W { + CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_lli_wr_dec_err_intstat( + &mut self, + ) -> CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W { + CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_lli_rd_slv_err_intstat( + &mut self, + ) -> CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W { + CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_lli_wr_slv_err_intstat( + &mut self, + ) -> CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W { + CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_shadowreg_or_lli_invalid_err_intstat( + &mut self, + ) -> CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W { + CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_multiblktype_err_intstat( + &mut self, + ) -> CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W { + CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_dec_err_intstat( + &mut self, + ) -> CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_W { + CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_wr2ro_err_intstat( + &mut self, + ) -> CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W { + CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_rd2rwo_err_intstat( + &mut self, + ) -> CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W { + CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_wronchen_err_intstat( + &mut self, + ) -> CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W { + CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_shadowreg_wron_valid_err_intstat( + &mut self, + ) -> CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W { + CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_slvif_wronhold_err_intstat( + &mut self, + ) -> CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W { + CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W::new(self, 21) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_ch_lock_cleared_intstat( + &mut self, + ) -> CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_W { + CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_ch_src_suspended_intstat( + &mut self, + ) -> CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W { + CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_ch_suspended_intstat( + &mut self, + ) -> CH1_ENABLE_CH_SUSPENDED_INTSTAT_W { + CH1_ENABLE_CH_SUSPENDED_INTSTAT_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_ch_disabled_intstat( + &mut self, + ) -> CH1_ENABLE_CH_DISABLED_INTSTAT_W { + CH1_ENABLE_CH_DISABLED_INTSTAT_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_enable_ch_aborted_intstat( + &mut self, + ) -> CH1_ENABLE_CH_ABORTED_INTSTAT_W { + CH1_ENABLE_CH_ABORTED_INTSTAT_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intstatus_enable0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_intstatus_enable0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_INTSTATUS_ENABLE0_SPEC; +impl crate::RegisterSpec for CH1_INTSTATUS_ENABLE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_intstatus_enable0::R`](R) reader structure"] +impl crate::Readable for CH1_INTSTATUS_ENABLE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_intstatus_enable0::W`](W) writer structure"] +impl crate::Writable for CH1_INTSTATUS_ENABLE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_INTSTATUS_ENABLE0 to value 0xfa3f_7ffb"] +impl crate::Resettable for CH1_INTSTATUS_ENABLE0_SPEC { + const RESET_VALUE: Self::Ux = 0xfa3f_7ffb; +} diff --git a/esp32p4/src/dma/ch1_intstatus_enable1.rs b/esp32p4/src/dma/ch1_intstatus_enable1.rs new file mode 100644 index 0000000000..2294121efa --- /dev/null +++ b/esp32p4/src/dma/ch1_intstatus_enable1.rs @@ -0,0 +1,89 @@ +#[doc = "Register `CH1_INTSTATUS_ENABLE1` reader"] +pub type R = crate::R; +#[doc = "Field `CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_enable_ecc_prot_chmem_correrr_intstat( + &self, + ) -> CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R { + CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch1_enable_ecc_prot_chmem_uncorrerr_intstat( + &self, + ) -> CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R { + CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch1_enable_ecc_prot_uidmem_correrr_intstat( + &self, + ) -> CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R { + CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch1_enable_ecc_prot_uidmem_uncorrerr_intstat( + &self, + ) -> CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R { + CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_INTSTATUS_ENABLE1") + .field( + "ch1_enable_ecc_prot_chmem_correrr_intstat", + &format_args!("{}", self.ch1_enable_ecc_prot_chmem_correrr_intstat().bit()), + ) + .field( + "ch1_enable_ecc_prot_chmem_uncorrerr_intstat", + &format_args!( + "{}", + self.ch1_enable_ecc_prot_chmem_uncorrerr_intstat().bit() + ), + ) + .field( + "ch1_enable_ecc_prot_uidmem_correrr_intstat", + &format_args!( + "{}", + self.ch1_enable_ecc_prot_uidmem_correrr_intstat().bit() + ), + ) + .field( + "ch1_enable_ecc_prot_uidmem_uncorrerr_intstat", + &format_args!( + "{}", + self.ch1_enable_ecc_prot_uidmem_uncorrerr_intstat().bit() + ), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_intstatus_enable1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_INTSTATUS_ENABLE1_SPEC; +impl crate::RegisterSpec for CH1_INTSTATUS_ENABLE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_intstatus_enable1::R`](R) reader structure"] +impl crate::Readable for CH1_INTSTATUS_ENABLE1_SPEC {} +#[doc = "`reset()` method sets CH1_INTSTATUS_ENABLE1 to value 0x0f"] +impl crate::Resettable for CH1_INTSTATUS_ENABLE1_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/dma/ch1_llp0.rs b/esp32p4/src/dma/ch1_llp0.rs new file mode 100644 index 0000000000..f287c826c4 --- /dev/null +++ b/esp32p4/src/dma/ch1_llp0.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CH1_LLP0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_LLP0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_LMS` reader - NA"] +pub type CH1_LMS_R = crate::BitReader; +#[doc = "Field `CH1_LMS` writer - NA"] +pub type CH1_LMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_LOC0` reader - NA"] +pub type CH1_LOC0_R = crate::FieldReader; +#[doc = "Field `CH1_LOC0` writer - NA"] +pub type CH1_LOC0_W<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_lms(&self) -> CH1_LMS_R { + CH1_LMS_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 6:31 - NA"] + #[inline(always)] + pub fn ch1_loc0(&self) -> CH1_LOC0_R { + CH1_LOC0_R::new((self.bits >> 6) & 0x03ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_LLP0") + .field("ch1_lms", &format_args!("{}", self.ch1_lms().bit())) + .field("ch1_loc0", &format_args!("{}", self.ch1_loc0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_lms(&mut self) -> CH1_LMS_W { + CH1_LMS_W::new(self, 0) + } + #[doc = "Bits 6:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_loc0(&mut self) -> CH1_LOC0_W { + CH1_LOC0_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_llp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_llp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_LLP0_SPEC; +impl crate::RegisterSpec for CH1_LLP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_llp0::R`](R) reader structure"] +impl crate::Readable for CH1_LLP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_llp0::W`](W) writer structure"] +impl crate::Writable for CH1_LLP0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_LLP0 to value 0"] +impl crate::Resettable for CH1_LLP0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_llp1.rs b/esp32p4/src/dma/ch1_llp1.rs new file mode 100644 index 0000000000..cae698a09d --- /dev/null +++ b/esp32p4/src/dma/ch1_llp1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH1_LLP1` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_LLP1` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_LOC1` reader - NA"] +pub type CH1_LOC1_R = crate::FieldReader; +#[doc = "Field `CH1_LOC1` writer - NA"] +pub type CH1_LOC1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch1_loc1(&self) -> CH1_LOC1_R { + CH1_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_LLP1") + .field("ch1_loc1", &format_args!("{}", self.ch1_loc1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_loc1(&mut self) -> CH1_LOC1_W { + CH1_LOC1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_llp1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_llp1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_LLP1_SPEC; +impl crate::RegisterSpec for CH1_LLP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_llp1::R`](R) reader structure"] +impl crate::Readable for CH1_LLP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_llp1::W`](W) writer structure"] +impl crate::Writable for CH1_LLP1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_LLP1 to value 0"] +impl crate::Resettable for CH1_LLP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_sar0.rs b/esp32p4/src/dma/ch1_sar0.rs new file mode 100644 index 0000000000..da75956aa6 --- /dev/null +++ b/esp32p4/src/dma/ch1_sar0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH1_SAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_SAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_SAR0` reader - NA"] +pub type CH1_SAR0_R = crate::FieldReader; +#[doc = "Field `CH1_SAR0` writer - NA"] +pub type CH1_SAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch1_sar0(&self) -> CH1_SAR0_R { + CH1_SAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_SAR0") + .field("ch1_sar0", &format_args!("{}", self.ch1_sar0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_sar0(&mut self) -> CH1_SAR0_W { + CH1_SAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_sar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_sar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_SAR0_SPEC; +impl crate::RegisterSpec for CH1_SAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_sar0::R`](R) reader structure"] +impl crate::Readable for CH1_SAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_sar0::W`](W) writer structure"] +impl crate::Writable for CH1_SAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_SAR0 to value 0"] +impl crate::Resettable for CH1_SAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_sar1.rs b/esp32p4/src/dma/ch1_sar1.rs new file mode 100644 index 0000000000..71fddb7cd5 --- /dev/null +++ b/esp32p4/src/dma/ch1_sar1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH1_SAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_SAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_SAR1` reader - NA"] +pub type CH1_SAR1_R = crate::FieldReader; +#[doc = "Field `CH1_SAR1` writer - NA"] +pub type CH1_SAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch1_sar1(&self) -> CH1_SAR1_R { + CH1_SAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_SAR1") + .field("ch1_sar1", &format_args!("{}", self.ch1_sar1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_sar1(&mut self) -> CH1_SAR1_W { + CH1_SAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_sar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_sar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_SAR1_SPEC; +impl crate::RegisterSpec for CH1_SAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_sar1::R`](R) reader structure"] +impl crate::Readable for CH1_SAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_sar1::W`](W) writer structure"] +impl crate::Writable for CH1_SAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_SAR1 to value 0"] +impl crate::Resettable for CH1_SAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_sstat0.rs b/esp32p4/src/dma/ch1_sstat0.rs new file mode 100644 index 0000000000..ff2a8f2f10 --- /dev/null +++ b/esp32p4/src/dma/ch1_sstat0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `CH1_SSTAT0` reader"] +pub type R = crate::R; +#[doc = "Field `CH1_SSTAT` reader - NA"] +pub type CH1_SSTAT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch1_sstat(&self) -> CH1_SSTAT_R { + CH1_SSTAT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_SSTAT0") + .field("ch1_sstat", &format_args!("{}", self.ch1_sstat().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_sstat0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_SSTAT0_SPEC; +impl crate::RegisterSpec for CH1_SSTAT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_sstat0::R`](R) reader structure"] +impl crate::Readable for CH1_SSTAT0_SPEC {} +#[doc = "`reset()` method sets CH1_SSTAT0 to value 0"] +impl crate::Resettable for CH1_SSTAT0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_sstatar0.rs b/esp32p4/src/dma/ch1_sstatar0.rs new file mode 100644 index 0000000000..cdf245a2c5 --- /dev/null +++ b/esp32p4/src/dma/ch1_sstatar0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH1_SSTATAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_SSTATAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_SSTATAR0` reader - NA"] +pub type CH1_SSTATAR0_R = crate::FieldReader; +#[doc = "Field `CH1_SSTATAR0` writer - NA"] +pub type CH1_SSTATAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch1_sstatar0(&self) -> CH1_SSTATAR0_R { + CH1_SSTATAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_SSTATAR0") + .field( + "ch1_sstatar0", + &format_args!("{}", self.ch1_sstatar0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_sstatar0(&mut self) -> CH1_SSTATAR0_W { + CH1_SSTATAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_sstatar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_sstatar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_SSTATAR0_SPEC; +impl crate::RegisterSpec for CH1_SSTATAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_sstatar0::R`](R) reader structure"] +impl crate::Readable for CH1_SSTATAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_sstatar0::W`](W) writer structure"] +impl crate::Writable for CH1_SSTATAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_SSTATAR0 to value 0"] +impl crate::Resettable for CH1_SSTATAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_sstatar1.rs b/esp32p4/src/dma/ch1_sstatar1.rs new file mode 100644 index 0000000000..6b439fe02f --- /dev/null +++ b/esp32p4/src/dma/ch1_sstatar1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH1_SSTATAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_SSTATAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_SSTATAR1` reader - NA"] +pub type CH1_SSTATAR1_R = crate::FieldReader; +#[doc = "Field `CH1_SSTATAR1` writer - NA"] +pub type CH1_SSTATAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch1_sstatar1(&self) -> CH1_SSTATAR1_R { + CH1_SSTATAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_SSTATAR1") + .field( + "ch1_sstatar1", + &format_args!("{}", self.ch1_sstatar1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_sstatar1(&mut self) -> CH1_SSTATAR1_W { + CH1_SSTATAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_sstatar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_sstatar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_SSTATAR1_SPEC; +impl crate::RegisterSpec for CH1_SSTATAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_sstatar1::R`](R) reader structure"] +impl crate::Readable for CH1_SSTATAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_sstatar1::W`](W) writer structure"] +impl crate::Writable for CH1_SSTATAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_SSTATAR1 to value 0"] +impl crate::Resettable for CH1_SSTATAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_status0.rs b/esp32p4/src/dma/ch1_status0.rs new file mode 100644 index 0000000000..4e79064a8b --- /dev/null +++ b/esp32p4/src/dma/ch1_status0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CH1_STATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `CH1_CMPLTD_BLK_TFR_SIZE` reader - NA"] +pub type CH1_CMPLTD_BLK_TFR_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + pub fn ch1_cmpltd_blk_tfr_size(&self) -> CH1_CMPLTD_BLK_TFR_SIZE_R { + CH1_CMPLTD_BLK_TFR_SIZE_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_STATUS0") + .field( + "ch1_cmpltd_blk_tfr_size", + &format_args!("{}", self.ch1_cmpltd_blk_tfr_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_STATUS0_SPEC; +impl crate::RegisterSpec for CH1_STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_status0::R`](R) reader structure"] +impl crate::Readable for CH1_STATUS0_SPEC {} +#[doc = "`reset()` method sets CH1_STATUS0 to value 0"] +impl crate::Resettable for CH1_STATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_status1.rs b/esp32p4/src/dma/ch1_status1.rs new file mode 100644 index 0000000000..5679d761f6 --- /dev/null +++ b/esp32p4/src/dma/ch1_status1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CH1_STATUS1` reader"] +pub type R = crate::R; +#[doc = "Field `CH1_DATA_LEFT_IN_FIFO` reader - NA"] +pub type CH1_DATA_LEFT_IN_FIFO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + pub fn ch1_data_left_in_fifo(&self) -> CH1_DATA_LEFT_IN_FIFO_R { + CH1_DATA_LEFT_IN_FIFO_R::new((self.bits & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_STATUS1") + .field( + "ch1_data_left_in_fifo", + &format_args!("{}", self.ch1_data_left_in_fifo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_status1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_STATUS1_SPEC; +impl crate::RegisterSpec for CH1_STATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_status1::R`](R) reader structure"] +impl crate::Readable for CH1_STATUS1_SPEC {} +#[doc = "`reset()` method sets CH1_STATUS1 to value 0"] +impl crate::Resettable for CH1_STATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_swhsdst0.rs b/esp32p4/src/dma/ch1_swhsdst0.rs new file mode 100644 index 0000000000..698b2ec58f --- /dev/null +++ b/esp32p4/src/dma/ch1_swhsdst0.rs @@ -0,0 +1,128 @@ +#[doc = "Register `CH1_SWHSDST0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_SWHSDST0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_SWHS_REQ_DST` reader - NA"] +pub type CH1_SWHS_REQ_DST_R = crate::BitReader; +#[doc = "Field `CH1_SWHS_REQ_DST` writer - NA"] +pub type CH1_SWHS_REQ_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SWHS_REQ_DST_WE` writer - NA"] +pub type CH1_SWHS_REQ_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SWHS_SGLREQ_DST` reader - NA"] +pub type CH1_SWHS_SGLREQ_DST_R = crate::BitReader; +#[doc = "Field `CH1_SWHS_SGLREQ_DST` writer - NA"] +pub type CH1_SWHS_SGLREQ_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SWHS_SGLREQ_DST_WE` writer - NA"] +pub type CH1_SWHS_SGLREQ_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SWHS_LST_DST` reader - NA"] +pub type CH1_SWHS_LST_DST_R = crate::BitReader; +#[doc = "Field `CH1_SWHS_LST_DST` writer - NA"] +pub type CH1_SWHS_LST_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SWHS_LST_DST_WE` writer - NA"] +pub type CH1_SWHS_LST_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_swhs_req_dst(&self) -> CH1_SWHS_REQ_DST_R { + CH1_SWHS_REQ_DST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch1_swhs_sglreq_dst(&self) -> CH1_SWHS_SGLREQ_DST_R { + CH1_SWHS_SGLREQ_DST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch1_swhs_lst_dst(&self) -> CH1_SWHS_LST_DST_R { + CH1_SWHS_LST_DST_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_SWHSDST0") + .field( + "ch1_swhs_req_dst", + &format_args!("{}", self.ch1_swhs_req_dst().bit()), + ) + .field( + "ch1_swhs_sglreq_dst", + &format_args!("{}", self.ch1_swhs_sglreq_dst().bit()), + ) + .field( + "ch1_swhs_lst_dst", + &format_args!("{}", self.ch1_swhs_lst_dst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_req_dst(&mut self) -> CH1_SWHS_REQ_DST_W { + CH1_SWHS_REQ_DST_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_req_dst_we(&mut self) -> CH1_SWHS_REQ_DST_WE_W { + CH1_SWHS_REQ_DST_WE_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_sglreq_dst(&mut self) -> CH1_SWHS_SGLREQ_DST_W { + CH1_SWHS_SGLREQ_DST_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_sglreq_dst_we(&mut self) -> CH1_SWHS_SGLREQ_DST_WE_W { + CH1_SWHS_SGLREQ_DST_WE_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_lst_dst(&mut self) -> CH1_SWHS_LST_DST_W { + CH1_SWHS_LST_DST_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_lst_dst_we(&mut self) -> CH1_SWHS_LST_DST_WE_W { + CH1_SWHS_LST_DST_WE_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_swhsdst0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_swhsdst0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_SWHSDST0_SPEC; +impl crate::RegisterSpec for CH1_SWHSDST0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_swhsdst0::R`](R) reader structure"] +impl crate::Readable for CH1_SWHSDST0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_swhsdst0::W`](W) writer structure"] +impl crate::Writable for CH1_SWHSDST0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_SWHSDST0 to value 0"] +impl crate::Resettable for CH1_SWHSDST0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch1_swhssrc0.rs b/esp32p4/src/dma/ch1_swhssrc0.rs new file mode 100644 index 0000000000..a549dbafac --- /dev/null +++ b/esp32p4/src/dma/ch1_swhssrc0.rs @@ -0,0 +1,128 @@ +#[doc = "Register `CH1_SWHSSRC0` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_SWHSSRC0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_SWHS_REQ_SRC` reader - NA"] +pub type CH1_SWHS_REQ_SRC_R = crate::BitReader; +#[doc = "Field `CH1_SWHS_REQ_SRC` writer - NA"] +pub type CH1_SWHS_REQ_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SWHS_REQ_SRC_WE` writer - NA"] +pub type CH1_SWHS_REQ_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SWHS_SGLREQ_SRC` reader - NA"] +pub type CH1_SWHS_SGLREQ_SRC_R = crate::BitReader; +#[doc = "Field `CH1_SWHS_SGLREQ_SRC` writer - NA"] +pub type CH1_SWHS_SGLREQ_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SWHS_SGLREQ_SRC_WE` writer - NA"] +pub type CH1_SWHS_SGLREQ_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SWHS_LST_SRC` reader - NA"] +pub type CH1_SWHS_LST_SRC_R = crate::BitReader; +#[doc = "Field `CH1_SWHS_LST_SRC` writer - NA"] +pub type CH1_SWHS_LST_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SWHS_LST_SRC_WE` writer - NA"] +pub type CH1_SWHS_LST_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_swhs_req_src(&self) -> CH1_SWHS_REQ_SRC_R { + CH1_SWHS_REQ_SRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch1_swhs_sglreq_src(&self) -> CH1_SWHS_SGLREQ_SRC_R { + CH1_SWHS_SGLREQ_SRC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch1_swhs_lst_src(&self) -> CH1_SWHS_LST_SRC_R { + CH1_SWHS_LST_SRC_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_SWHSSRC0") + .field( + "ch1_swhs_req_src", + &format_args!("{}", self.ch1_swhs_req_src().bit()), + ) + .field( + "ch1_swhs_sglreq_src", + &format_args!("{}", self.ch1_swhs_sglreq_src().bit()), + ) + .field( + "ch1_swhs_lst_src", + &format_args!("{}", self.ch1_swhs_lst_src().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_req_src(&mut self) -> CH1_SWHS_REQ_SRC_W { + CH1_SWHS_REQ_SRC_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_req_src_we(&mut self) -> CH1_SWHS_REQ_SRC_WE_W { + CH1_SWHS_REQ_SRC_WE_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_sglreq_src(&mut self) -> CH1_SWHS_SGLREQ_SRC_W { + CH1_SWHS_SGLREQ_SRC_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_sglreq_src_we(&mut self) -> CH1_SWHS_SGLREQ_SRC_WE_W { + CH1_SWHS_SGLREQ_SRC_WE_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_lst_src(&mut self) -> CH1_SWHS_LST_SRC_W { + CH1_SWHS_LST_SRC_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_swhs_lst_src_we(&mut self) -> CH1_SWHS_LST_SRC_WE_W { + CH1_SWHS_LST_SRC_WE_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_swhssrc0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_swhssrc0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_SWHSSRC0_SPEC; +impl crate::RegisterSpec for CH1_SWHSSRC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_swhssrc0::R`](R) reader structure"] +impl crate::Readable for CH1_SWHSSRC0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_swhssrc0::W`](W) writer structure"] +impl crate::Writable for CH1_SWHSSRC0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_SWHSSRC0 to value 0"] +impl crate::Resettable for CH1_SWHSSRC0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_axi_id0.rs b/esp32p4/src/dma/ch2_axi_id0.rs new file mode 100644 index 0000000000..df7839c743 --- /dev/null +++ b/esp32p4/src/dma/ch2_axi_id0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CH2_AXI_ID0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_AXI_ID0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_AXI_READ_ID_SUFFIX` reader - NA"] +pub type CH2_AXI_READ_ID_SUFFIX_R = crate::BitReader; +#[doc = "Field `CH2_AXI_READ_ID_SUFFIX` writer - NA"] +pub type CH2_AXI_READ_ID_SUFFIX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_AXI_WRITE_ID_SUFFIX` reader - NA"] +pub type CH2_AXI_WRITE_ID_SUFFIX_R = crate::BitReader; +#[doc = "Field `CH2_AXI_WRITE_ID_SUFFIX` writer - NA"] +pub type CH2_AXI_WRITE_ID_SUFFIX_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch2_axi_read_id_suffix(&self) -> CH2_AXI_READ_ID_SUFFIX_R { + CH2_AXI_READ_ID_SUFFIX_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch2_axi_write_id_suffix(&self) -> CH2_AXI_WRITE_ID_SUFFIX_R { + CH2_AXI_WRITE_ID_SUFFIX_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_AXI_ID0") + .field( + "ch2_axi_read_id_suffix", + &format_args!("{}", self.ch2_axi_read_id_suffix().bit()), + ) + .field( + "ch2_axi_write_id_suffix", + &format_args!("{}", self.ch2_axi_write_id_suffix().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_axi_read_id_suffix(&mut self) -> CH2_AXI_READ_ID_SUFFIX_W { + CH2_AXI_READ_ID_SUFFIX_W::new(self, 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_axi_write_id_suffix(&mut self) -> CH2_AXI_WRITE_ID_SUFFIX_W { + CH2_AXI_WRITE_ID_SUFFIX_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_axi_id0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_axi_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_AXI_ID0_SPEC; +impl crate::RegisterSpec for CH2_AXI_ID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_axi_id0::R`](R) reader structure"] +impl crate::Readable for CH2_AXI_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_axi_id0::W`](W) writer structure"] +impl crate::Writable for CH2_AXI_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_AXI_ID0 to value 0"] +impl crate::Resettable for CH2_AXI_ID0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_axi_qos0.rs b/esp32p4/src/dma/ch2_axi_qos0.rs new file mode 100644 index 0000000000..6eb37903a7 --- /dev/null +++ b/esp32p4/src/dma/ch2_axi_qos0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CH2_AXI_QOS0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_AXI_QOS0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_AXI_AWQOS` reader - NA"] +pub type CH2_AXI_AWQOS_R = crate::FieldReader; +#[doc = "Field `CH2_AXI_AWQOS` writer - NA"] +pub type CH2_AXI_AWQOS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH2_AXI_ARQOS` reader - NA"] +pub type CH2_AXI_ARQOS_R = crate::FieldReader; +#[doc = "Field `CH2_AXI_ARQOS` writer - NA"] +pub type CH2_AXI_ARQOS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + pub fn ch2_axi_awqos(&self) -> CH2_AXI_AWQOS_R { + CH2_AXI_AWQOS_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - NA"] + #[inline(always)] + pub fn ch2_axi_arqos(&self) -> CH2_AXI_ARQOS_R { + CH2_AXI_ARQOS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_AXI_QOS0") + .field( + "ch2_axi_awqos", + &format_args!("{}", self.ch2_axi_awqos().bits()), + ) + .field( + "ch2_axi_arqos", + &format_args!("{}", self.ch2_axi_arqos().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_axi_awqos(&mut self) -> CH2_AXI_AWQOS_W { + CH2_AXI_AWQOS_W::new(self, 0) + } + #[doc = "Bits 4:7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_axi_arqos(&mut self) -> CH2_AXI_ARQOS_W { + CH2_AXI_ARQOS_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_axi_qos0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_axi_qos0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_AXI_QOS0_SPEC; +impl crate::RegisterSpec for CH2_AXI_QOS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_axi_qos0::R`](R) reader structure"] +impl crate::Readable for CH2_AXI_QOS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_axi_qos0::W`](W) writer structure"] +impl crate::Writable for CH2_AXI_QOS0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_AXI_QOS0 to value 0"] +impl crate::Resettable for CH2_AXI_QOS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_blk_tfr_resumereq0.rs b/esp32p4/src/dma/ch2_blk_tfr_resumereq0.rs new file mode 100644 index 0000000000..944bd4bad6 --- /dev/null +++ b/esp32p4/src/dma/ch2_blk_tfr_resumereq0.rs @@ -0,0 +1,44 @@ +#[doc = "Register `CH2_BLK_TFR_RESUMEREQ0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_BLK_TFR_RESUMEREQ` writer - NA"] +pub type CH2_BLK_TFR_RESUMEREQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_blk_tfr_resumereq( + &mut self, + ) -> CH2_BLK_TFR_RESUMEREQ_W { + CH2_BLK_TFR_RESUMEREQ_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_blk_tfr_resumereq0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_BLK_TFR_RESUMEREQ0_SPEC; +impl crate::RegisterSpec for CH2_BLK_TFR_RESUMEREQ0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch2_blk_tfr_resumereq0::W`](W) writer structure"] +impl crate::Writable for CH2_BLK_TFR_RESUMEREQ0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_BLK_TFR_RESUMEREQ0 to value 0"] +impl crate::Resettable for CH2_BLK_TFR_RESUMEREQ0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_block_ts0.rs b/esp32p4/src/dma/ch2_block_ts0.rs new file mode 100644 index 0000000000..c9bd6dd8eb --- /dev/null +++ b/esp32p4/src/dma/ch2_block_ts0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH2_BLOCK_TS0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_BLOCK_TS0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_BLOCK_TS` reader - NA"] +pub type CH2_BLOCK_TS_R = crate::FieldReader; +#[doc = "Field `CH2_BLOCK_TS` writer - NA"] +pub type CH2_BLOCK_TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + pub fn ch2_block_ts(&self) -> CH2_BLOCK_TS_R { + CH2_BLOCK_TS_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_BLOCK_TS0") + .field( + "ch2_block_ts", + &format_args!("{}", self.ch2_block_ts().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_block_ts(&mut self) -> CH2_BLOCK_TS_W { + CH2_BLOCK_TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_block_ts0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_block_ts0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_BLOCK_TS0_SPEC; +impl crate::RegisterSpec for CH2_BLOCK_TS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_block_ts0::R`](R) reader structure"] +impl crate::Readable for CH2_BLOCK_TS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_block_ts0::W`](W) writer structure"] +impl crate::Writable for CH2_BLOCK_TS0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_BLOCK_TS0 to value 0"] +impl crate::Resettable for CH2_BLOCK_TS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_cfg0.rs b/esp32p4/src/dma/ch2_cfg0.rs new file mode 100644 index 0000000000..c5a8fd90b6 --- /dev/null +++ b/esp32p4/src/dma/ch2_cfg0.rs @@ -0,0 +1,101 @@ +#[doc = "Register `CH2_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_SRC_MULTBLK_TYPE` reader - NA"] +pub type CH2_SRC_MULTBLK_TYPE_R = crate::FieldReader; +#[doc = "Field `CH2_SRC_MULTBLK_TYPE` writer - NA"] +pub type CH2_SRC_MULTBLK_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH2_DST_MULTBLK_TYPE` reader - NA"] +pub type CH2_DST_MULTBLK_TYPE_R = crate::FieldReader; +#[doc = "Field `CH2_DST_MULTBLK_TYPE` writer - NA"] +pub type CH2_DST_MULTBLK_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH2_RD_UID` reader - NA"] +pub type CH2_RD_UID_R = crate::FieldReader; +#[doc = "Field `CH2_WR_UID` reader - NA"] +pub type CH2_WR_UID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn ch2_src_multblk_type(&self) -> CH2_SRC_MULTBLK_TYPE_R { + CH2_SRC_MULTBLK_TYPE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - NA"] + #[inline(always)] + pub fn ch2_dst_multblk_type(&self) -> CH2_DST_MULTBLK_TYPE_R { + CH2_DST_MULTBLK_TYPE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + pub fn ch2_rd_uid(&self) -> CH2_RD_UID_R { + CH2_RD_UID_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bits 25:28 - NA"] + #[inline(always)] + pub fn ch2_wr_uid(&self) -> CH2_WR_UID_R { + CH2_WR_UID_R::new(((self.bits >> 25) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_CFG0") + .field( + "ch2_src_multblk_type", + &format_args!("{}", self.ch2_src_multblk_type().bits()), + ) + .field( + "ch2_dst_multblk_type", + &format_args!("{}", self.ch2_dst_multblk_type().bits()), + ) + .field("ch2_rd_uid", &format_args!("{}", self.ch2_rd_uid().bits())) + .field("ch2_wr_uid", &format_args!("{}", self.ch2_wr_uid().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_src_multblk_type(&mut self) -> CH2_SRC_MULTBLK_TYPE_W { + CH2_SRC_MULTBLK_TYPE_W::new(self, 0) + } + #[doc = "Bits 2:3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dst_multblk_type(&mut self) -> CH2_DST_MULTBLK_TYPE_W { + CH2_DST_MULTBLK_TYPE_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_CFG0_SPEC; +impl crate::RegisterSpec for CH2_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_cfg0::R`](R) reader structure"] +impl crate::Readable for CH2_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_cfg0::W`](W) writer structure"] +impl crate::Writable for CH2_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_CFG0 to value 0"] +impl crate::Resettable for CH2_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_cfg1.rs b/esp32p4/src/dma/ch2_cfg1.rs new file mode 100644 index 0000000000..c5c5a14efe --- /dev/null +++ b/esp32p4/src/dma/ch2_cfg1.rs @@ -0,0 +1,237 @@ +#[doc = "Register `CH2_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_TT_FC` reader - NA"] +pub type CH2_TT_FC_R = crate::FieldReader; +#[doc = "Field `CH2_TT_FC` writer - NA"] +pub type CH2_TT_FC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH2_HS_SEL_SRC` reader - NA"] +pub type CH2_HS_SEL_SRC_R = crate::BitReader; +#[doc = "Field `CH2_HS_SEL_SRC` writer - NA"] +pub type CH2_HS_SEL_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_HS_SEL_DST` reader - NA"] +pub type CH2_HS_SEL_DST_R = crate::BitReader; +#[doc = "Field `CH2_HS_SEL_DST` writer - NA"] +pub type CH2_HS_SEL_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SRC_HWHS_POL` reader - NA"] +pub type CH2_SRC_HWHS_POL_R = crate::BitReader; +#[doc = "Field `CH2_DST_HWHS_POL` reader - NA"] +pub type CH2_DST_HWHS_POL_R = crate::BitReader; +#[doc = "Field `CH2_SRC_PER` reader - NA"] +pub type CH2_SRC_PER_R = crate::FieldReader; +#[doc = "Field `CH2_SRC_PER` writer - NA"] +pub type CH2_SRC_PER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH2_DST_PER` reader - NA"] +pub type CH2_DST_PER_R = crate::FieldReader; +#[doc = "Field `CH2_DST_PER` writer - NA"] +pub type CH2_DST_PER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH2_CH_PRIOR` reader - NA"] +pub type CH2_CH_PRIOR_R = crate::FieldReader; +#[doc = "Field `CH2_CH_PRIOR` writer - NA"] +pub type CH2_CH_PRIOR_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH2_LOCK_CH` reader - NA"] +pub type CH2_LOCK_CH_R = crate::BitReader; +#[doc = "Field `CH2_LOCK_CH_L` reader - NA"] +pub type CH2_LOCK_CH_L_R = crate::FieldReader; +#[doc = "Field `CH2_SRC_OSR_LMT` reader - NA"] +pub type CH2_SRC_OSR_LMT_R = crate::FieldReader; +#[doc = "Field `CH2_SRC_OSR_LMT` writer - NA"] +pub type CH2_SRC_OSR_LMT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH2_DST_OSR_LMT` reader - NA"] +pub type CH2_DST_OSR_LMT_R = crate::FieldReader; +#[doc = "Field `CH2_DST_OSR_LMT` writer - NA"] +pub type CH2_DST_OSR_LMT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + pub fn ch2_tt_fc(&self) -> CH2_TT_FC_R { + CH2_TT_FC_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch2_hs_sel_src(&self) -> CH2_HS_SEL_SRC_R { + CH2_HS_SEL_SRC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch2_hs_sel_dst(&self) -> CH2_HS_SEL_DST_R { + CH2_HS_SEL_DST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch2_src_hwhs_pol(&self) -> CH2_SRC_HWHS_POL_R { + CH2_SRC_HWHS_POL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch2_dst_hwhs_pol(&self) -> CH2_DST_HWHS_POL_R { + CH2_DST_HWHS_POL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:8 - NA"] + #[inline(always)] + pub fn ch2_src_per(&self) -> CH2_SRC_PER_R { + CH2_SRC_PER_R::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 12:13 - NA"] + #[inline(always)] + pub fn ch2_dst_per(&self) -> CH2_DST_PER_R { + CH2_DST_PER_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 17:19 - NA"] + #[inline(always)] + pub fn ch2_ch_prior(&self) -> CH2_CH_PRIOR_R { + CH2_CH_PRIOR_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch2_lock_ch(&self) -> CH2_LOCK_CH_R { + CH2_LOCK_CH_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:22 - NA"] + #[inline(always)] + pub fn ch2_lock_ch_l(&self) -> CH2_LOCK_CH_L_R { + CH2_LOCK_CH_L_R::new(((self.bits >> 21) & 3) as u8) + } + #[doc = "Bits 23:26 - NA"] + #[inline(always)] + pub fn ch2_src_osr_lmt(&self) -> CH2_SRC_OSR_LMT_R { + CH2_SRC_OSR_LMT_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bits 27:30 - NA"] + #[inline(always)] + pub fn ch2_dst_osr_lmt(&self) -> CH2_DST_OSR_LMT_R { + CH2_DST_OSR_LMT_R::new(((self.bits >> 27) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_CFG1") + .field("ch2_tt_fc", &format_args!("{}", self.ch2_tt_fc().bits())) + .field( + "ch2_hs_sel_src", + &format_args!("{}", self.ch2_hs_sel_src().bit()), + ) + .field( + "ch2_hs_sel_dst", + &format_args!("{}", self.ch2_hs_sel_dst().bit()), + ) + .field( + "ch2_src_hwhs_pol", + &format_args!("{}", self.ch2_src_hwhs_pol().bit()), + ) + .field( + "ch2_dst_hwhs_pol", + &format_args!("{}", self.ch2_dst_hwhs_pol().bit()), + ) + .field( + "ch2_src_per", + &format_args!("{}", self.ch2_src_per().bits()), + ) + .field( + "ch2_dst_per", + &format_args!("{}", self.ch2_dst_per().bits()), + ) + .field( + "ch2_ch_prior", + &format_args!("{}", self.ch2_ch_prior().bits()), + ) + .field("ch2_lock_ch", &format_args!("{}", self.ch2_lock_ch().bit())) + .field( + "ch2_lock_ch_l", + &format_args!("{}", self.ch2_lock_ch_l().bits()), + ) + .field( + "ch2_src_osr_lmt", + &format_args!("{}", self.ch2_src_osr_lmt().bits()), + ) + .field( + "ch2_dst_osr_lmt", + &format_args!("{}", self.ch2_dst_osr_lmt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_tt_fc(&mut self) -> CH2_TT_FC_W { + CH2_TT_FC_W::new(self, 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_hs_sel_src(&mut self) -> CH2_HS_SEL_SRC_W { + CH2_HS_SEL_SRC_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_hs_sel_dst(&mut self) -> CH2_HS_SEL_DST_W { + CH2_HS_SEL_DST_W::new(self, 4) + } + #[doc = "Bits 7:8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_src_per(&mut self) -> CH2_SRC_PER_W { + CH2_SRC_PER_W::new(self, 7) + } + #[doc = "Bits 12:13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dst_per(&mut self) -> CH2_DST_PER_W { + CH2_DST_PER_W::new(self, 12) + } + #[doc = "Bits 17:19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_ch_prior(&mut self) -> CH2_CH_PRIOR_W { + CH2_CH_PRIOR_W::new(self, 17) + } + #[doc = "Bits 23:26 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_src_osr_lmt(&mut self) -> CH2_SRC_OSR_LMT_W { + CH2_SRC_OSR_LMT_W::new(self, 23) + } + #[doc = "Bits 27:30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dst_osr_lmt(&mut self) -> CH2_DST_OSR_LMT_W { + CH2_DST_OSR_LMT_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_CFG1_SPEC; +impl crate::RegisterSpec for CH2_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_cfg1::R`](R) reader structure"] +impl crate::Readable for CH2_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_cfg1::W`](W) writer structure"] +impl crate::Writable for CH2_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_CFG1 to value 0x0004_001b"] +impl crate::Resettable for CH2_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0x0004_001b; +} diff --git a/esp32p4/src/dma/ch2_ctl0.rs b/esp32p4/src/dma/ch2_ctl0.rs new file mode 100644 index 0000000000..1dccd70772 --- /dev/null +++ b/esp32p4/src/dma/ch2_ctl0.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CH2_CTL0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_CTL0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_SMS` reader - NA"] +pub type CH2_SMS_R = crate::BitReader; +#[doc = "Field `CH2_SMS` writer - NA"] +pub type CH2_SMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_DMS` reader - NA"] +pub type CH2_DMS_R = crate::BitReader; +#[doc = "Field `CH2_DMS` writer - NA"] +pub type CH2_DMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SINC` reader - NA"] +pub type CH2_SINC_R = crate::BitReader; +#[doc = "Field `CH2_SINC` writer - NA"] +pub type CH2_SINC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_DINC` reader - NA"] +pub type CH2_DINC_R = crate::BitReader; +#[doc = "Field `CH2_DINC` writer - NA"] +pub type CH2_DINC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SRC_TR_WIDTH` reader - NA"] +pub type CH2_SRC_TR_WIDTH_R = crate::FieldReader; +#[doc = "Field `CH2_SRC_TR_WIDTH` writer - NA"] +pub type CH2_SRC_TR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH2_DST_TR_WIDTH` reader - NA"] +pub type CH2_DST_TR_WIDTH_R = crate::FieldReader; +#[doc = "Field `CH2_DST_TR_WIDTH` writer - NA"] +pub type CH2_DST_TR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH2_SRC_MSIZE` reader - NA"] +pub type CH2_SRC_MSIZE_R = crate::FieldReader; +#[doc = "Field `CH2_SRC_MSIZE` writer - NA"] +pub type CH2_SRC_MSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH2_DST_MSIZE` reader - NA"] +pub type CH2_DST_MSIZE_R = crate::FieldReader; +#[doc = "Field `CH2_DST_MSIZE` writer - NA"] +pub type CH2_DST_MSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH2_AR_CACHE` reader - NA"] +pub type CH2_AR_CACHE_R = crate::FieldReader; +#[doc = "Field `CH2_AR_CACHE` writer - NA"] +pub type CH2_AR_CACHE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH2_AW_CACHE` reader - NA"] +pub type CH2_AW_CACHE_R = crate::FieldReader; +#[doc = "Field `CH2_AW_CACHE` writer - NA"] +pub type CH2_AW_CACHE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH2_NONPOSTED_LASTWRITE_EN` reader - NA"] +pub type CH2_NONPOSTED_LASTWRITE_EN_R = crate::BitReader; +#[doc = "Field `CH2_NONPOSTED_LASTWRITE_EN` writer - NA"] +pub type CH2_NONPOSTED_LASTWRITE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch2_sms(&self) -> CH2_SMS_R { + CH2_SMS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch2_dms(&self) -> CH2_DMS_R { + CH2_DMS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch2_sinc(&self) -> CH2_SINC_R { + CH2_SINC_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch2_dinc(&self) -> CH2_DINC_R { + CH2_DINC_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - NA"] + #[inline(always)] + pub fn ch2_src_tr_width(&self) -> CH2_SRC_TR_WIDTH_R { + CH2_SRC_TR_WIDTH_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 11:13 - NA"] + #[inline(always)] + pub fn ch2_dst_tr_width(&self) -> CH2_DST_TR_WIDTH_R { + CH2_DST_TR_WIDTH_R::new(((self.bits >> 11) & 7) as u8) + } + #[doc = "Bits 14:17 - NA"] + #[inline(always)] + pub fn ch2_src_msize(&self) -> CH2_SRC_MSIZE_R { + CH2_SRC_MSIZE_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + pub fn ch2_dst_msize(&self) -> CH2_DST_MSIZE_R { + CH2_DST_MSIZE_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bits 22:25 - NA"] + #[inline(always)] + pub fn ch2_ar_cache(&self) -> CH2_AR_CACHE_R { + CH2_AR_CACHE_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:29 - NA"] + #[inline(always)] + pub fn ch2_aw_cache(&self) -> CH2_AW_CACHE_R { + CH2_AW_CACHE_R::new(((self.bits >> 26) & 0x0f) as u8) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch2_nonposted_lastwrite_en(&self) -> CH2_NONPOSTED_LASTWRITE_EN_R { + CH2_NONPOSTED_LASTWRITE_EN_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_CTL0") + .field("ch2_sms", &format_args!("{}", self.ch2_sms().bit())) + .field("ch2_dms", &format_args!("{}", self.ch2_dms().bit())) + .field("ch2_sinc", &format_args!("{}", self.ch2_sinc().bit())) + .field("ch2_dinc", &format_args!("{}", self.ch2_dinc().bit())) + .field( + "ch2_src_tr_width", + &format_args!("{}", self.ch2_src_tr_width().bits()), + ) + .field( + "ch2_dst_tr_width", + &format_args!("{}", self.ch2_dst_tr_width().bits()), + ) + .field( + "ch2_src_msize", + &format_args!("{}", self.ch2_src_msize().bits()), + ) + .field( + "ch2_dst_msize", + &format_args!("{}", self.ch2_dst_msize().bits()), + ) + .field( + "ch2_ar_cache", + &format_args!("{}", self.ch2_ar_cache().bits()), + ) + .field( + "ch2_aw_cache", + &format_args!("{}", self.ch2_aw_cache().bits()), + ) + .field( + "ch2_nonposted_lastwrite_en", + &format_args!("{}", self.ch2_nonposted_lastwrite_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_sms(&mut self) -> CH2_SMS_W { + CH2_SMS_W::new(self, 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dms(&mut self) -> CH2_DMS_W { + CH2_DMS_W::new(self, 2) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_sinc(&mut self) -> CH2_SINC_W { + CH2_SINC_W::new(self, 4) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dinc(&mut self) -> CH2_DINC_W { + CH2_DINC_W::new(self, 6) + } + #[doc = "Bits 8:10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_src_tr_width(&mut self) -> CH2_SRC_TR_WIDTH_W { + CH2_SRC_TR_WIDTH_W::new(self, 8) + } + #[doc = "Bits 11:13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dst_tr_width(&mut self) -> CH2_DST_TR_WIDTH_W { + CH2_DST_TR_WIDTH_W::new(self, 11) + } + #[doc = "Bits 14:17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_src_msize(&mut self) -> CH2_SRC_MSIZE_W { + CH2_SRC_MSIZE_W::new(self, 14) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dst_msize(&mut self) -> CH2_DST_MSIZE_W { + CH2_DST_MSIZE_W::new(self, 18) + } + #[doc = "Bits 22:25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_ar_cache(&mut self) -> CH2_AR_CACHE_W { + CH2_AR_CACHE_W::new(self, 22) + } + #[doc = "Bits 26:29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_aw_cache(&mut self) -> CH2_AW_CACHE_W { + CH2_AW_CACHE_W::new(self, 26) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_nonposted_lastwrite_en(&mut self) -> CH2_NONPOSTED_LASTWRITE_EN_W { + CH2_NONPOSTED_LASTWRITE_EN_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_CTL0_SPEC; +impl crate::RegisterSpec for CH2_CTL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_ctl0::R`](R) reader structure"] +impl crate::Readable for CH2_CTL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_ctl0::W`](W) writer structure"] +impl crate::Writable for CH2_CTL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_CTL0 to value 0x1200"] +impl crate::Resettable for CH2_CTL0_SPEC { + const RESET_VALUE: Self::Ux = 0x1200; +} diff --git a/esp32p4/src/dma/ch2_ctl1.rs b/esp32p4/src/dma/ch2_ctl1.rs new file mode 100644 index 0000000000..dc0945451f --- /dev/null +++ b/esp32p4/src/dma/ch2_ctl1.rs @@ -0,0 +1,250 @@ +#[doc = "Register `CH2_CTL1` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_CTL1` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_AR_PROT` reader - NA"] +pub type CH2_AR_PROT_R = crate::FieldReader; +#[doc = "Field `CH2_AR_PROT` writer - NA"] +pub type CH2_AR_PROT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH2_AW_PROT` reader - NA"] +pub type CH2_AW_PROT_R = crate::FieldReader; +#[doc = "Field `CH2_AW_PROT` writer - NA"] +pub type CH2_AW_PROT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH2_ARLEN_EN` reader - NA"] +pub type CH2_ARLEN_EN_R = crate::BitReader; +#[doc = "Field `CH2_ARLEN_EN` writer - NA"] +pub type CH2_ARLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ARLEN` reader - NA"] +pub type CH2_ARLEN_R = crate::FieldReader; +#[doc = "Field `CH2_ARLEN` writer - NA"] +pub type CH2_ARLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CH2_AWLEN_EN` reader - NA"] +pub type CH2_AWLEN_EN_R = crate::BitReader; +#[doc = "Field `CH2_AWLEN_EN` writer - NA"] +pub type CH2_AWLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_AWLEN` reader - NA"] +pub type CH2_AWLEN_R = crate::FieldReader; +#[doc = "Field `CH2_AWLEN` writer - NA"] +pub type CH2_AWLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CH2_SRC_STAT_EN` reader - NA"] +pub type CH2_SRC_STAT_EN_R = crate::BitReader; +#[doc = "Field `CH2_SRC_STAT_EN` writer - NA"] +pub type CH2_SRC_STAT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_DST_STAT_EN` reader - NA"] +pub type CH2_DST_STAT_EN_R = crate::BitReader; +#[doc = "Field `CH2_DST_STAT_EN` writer - NA"] +pub type CH2_DST_STAT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_IOC_BLKTFR` reader - NA"] +pub type CH2_IOC_BLKTFR_R = crate::BitReader; +#[doc = "Field `CH2_IOC_BLKTFR` writer - NA"] +pub type CH2_IOC_BLKTFR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SHADOWREG_OR_LLI_LAST` reader - NA"] +pub type CH2_SHADOWREG_OR_LLI_LAST_R = crate::BitReader; +#[doc = "Field `CH2_SHADOWREG_OR_LLI_LAST` writer - NA"] +pub type CH2_SHADOWREG_OR_LLI_LAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SHADOWREG_OR_LLI_VALID` reader - NA"] +pub type CH2_SHADOWREG_OR_LLI_VALID_R = crate::BitReader; +#[doc = "Field `CH2_SHADOWREG_OR_LLI_VALID` writer - NA"] +pub type CH2_SHADOWREG_OR_LLI_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + pub fn ch2_ar_prot(&self) -> CH2_AR_PROT_R { + CH2_AR_PROT_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - NA"] + #[inline(always)] + pub fn ch2_aw_prot(&self) -> CH2_AW_PROT_R { + CH2_AW_PROT_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch2_arlen_en(&self) -> CH2_ARLEN_EN_R { + CH2_ARLEN_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:14 - NA"] + #[inline(always)] + pub fn ch2_arlen(&self) -> CH2_ARLEN_R { + CH2_ARLEN_R::new(((self.bits >> 7) & 0xff) as u8) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn ch2_awlen_en(&self) -> CH2_AWLEN_EN_R { + CH2_AWLEN_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn ch2_awlen(&self) -> CH2_AWLEN_R { + CH2_AWLEN_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + pub fn ch2_src_stat_en(&self) -> CH2_SRC_STAT_EN_R { + CH2_SRC_STAT_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch2_dst_stat_en(&self) -> CH2_DST_STAT_EN_R { + CH2_DST_STAT_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - NA"] + #[inline(always)] + pub fn ch2_ioc_blktfr(&self) -> CH2_IOC_BLKTFR_R { + CH2_IOC_BLKTFR_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch2_shadowreg_or_lli_last(&self) -> CH2_SHADOWREG_OR_LLI_LAST_R { + CH2_SHADOWREG_OR_LLI_LAST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch2_shadowreg_or_lli_valid(&self) -> CH2_SHADOWREG_OR_LLI_VALID_R { + CH2_SHADOWREG_OR_LLI_VALID_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_CTL1") + .field( + "ch2_ar_prot", + &format_args!("{}", self.ch2_ar_prot().bits()), + ) + .field( + "ch2_aw_prot", + &format_args!("{}", self.ch2_aw_prot().bits()), + ) + .field( + "ch2_arlen_en", + &format_args!("{}", self.ch2_arlen_en().bit()), + ) + .field("ch2_arlen", &format_args!("{}", self.ch2_arlen().bits())) + .field( + "ch2_awlen_en", + &format_args!("{}", self.ch2_awlen_en().bit()), + ) + .field("ch2_awlen", &format_args!("{}", self.ch2_awlen().bits())) + .field( + "ch2_src_stat_en", + &format_args!("{}", self.ch2_src_stat_en().bit()), + ) + .field( + "ch2_dst_stat_en", + &format_args!("{}", self.ch2_dst_stat_en().bit()), + ) + .field( + "ch2_ioc_blktfr", + &format_args!("{}", self.ch2_ioc_blktfr().bit()), + ) + .field( + "ch2_shadowreg_or_lli_last", + &format_args!("{}", self.ch2_shadowreg_or_lli_last().bit()), + ) + .field( + "ch2_shadowreg_or_lli_valid", + &format_args!("{}", self.ch2_shadowreg_or_lli_valid().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_ar_prot(&mut self) -> CH2_AR_PROT_W { + CH2_AR_PROT_W::new(self, 0) + } + #[doc = "Bits 3:5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_aw_prot(&mut self) -> CH2_AW_PROT_W { + CH2_AW_PROT_W::new(self, 3) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_arlen_en(&mut self) -> CH2_ARLEN_EN_W { + CH2_ARLEN_EN_W::new(self, 6) + } + #[doc = "Bits 7:14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_arlen(&mut self) -> CH2_ARLEN_W { + CH2_ARLEN_W::new(self, 7) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_awlen_en(&mut self) -> CH2_AWLEN_EN_W { + CH2_AWLEN_EN_W::new(self, 15) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_awlen(&mut self) -> CH2_AWLEN_W { + CH2_AWLEN_W::new(self, 16) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_src_stat_en(&mut self) -> CH2_SRC_STAT_EN_W { + CH2_SRC_STAT_EN_W::new(self, 24) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dst_stat_en(&mut self) -> CH2_DST_STAT_EN_W { + CH2_DST_STAT_EN_W::new(self, 25) + } + #[doc = "Bit 26 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_ioc_blktfr(&mut self) -> CH2_IOC_BLKTFR_W { + CH2_IOC_BLKTFR_W::new(self, 26) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_shadowreg_or_lli_last(&mut self) -> CH2_SHADOWREG_OR_LLI_LAST_W { + CH2_SHADOWREG_OR_LLI_LAST_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_shadowreg_or_lli_valid(&mut self) -> CH2_SHADOWREG_OR_LLI_VALID_W { + CH2_SHADOWREG_OR_LLI_VALID_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_ctl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_CTL1_SPEC; +impl crate::RegisterSpec for CH2_CTL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_ctl1::R`](R) reader structure"] +impl crate::Readable for CH2_CTL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_ctl1::W`](W) writer structure"] +impl crate::Writable for CH2_CTL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_CTL1 to value 0"] +impl crate::Resettable for CH2_CTL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_dar0.rs b/esp32p4/src/dma/ch2_dar0.rs new file mode 100644 index 0000000000..6d4ca6fee7 --- /dev/null +++ b/esp32p4/src/dma/ch2_dar0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH2_DAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_DAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_DAR0` reader - NA"] +pub type CH2_DAR0_R = crate::FieldReader; +#[doc = "Field `CH2_DAR0` writer - NA"] +pub type CH2_DAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch2_dar0(&self) -> CH2_DAR0_R { + CH2_DAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_DAR0") + .field("ch2_dar0", &format_args!("{}", self.ch2_dar0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dar0(&mut self) -> CH2_DAR0_W { + CH2_DAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_dar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_DAR0_SPEC; +impl crate::RegisterSpec for CH2_DAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_dar0::R`](R) reader structure"] +impl crate::Readable for CH2_DAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_dar0::W`](W) writer structure"] +impl crate::Writable for CH2_DAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_DAR0 to value 0"] +impl crate::Resettable for CH2_DAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_dar1.rs b/esp32p4/src/dma/ch2_dar1.rs new file mode 100644 index 0000000000..3f52cd8220 --- /dev/null +++ b/esp32p4/src/dma/ch2_dar1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH2_DAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_DAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_DAR1` reader - NA"] +pub type CH2_DAR1_R = crate::FieldReader; +#[doc = "Field `CH2_DAR1` writer - NA"] +pub type CH2_DAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch2_dar1(&self) -> CH2_DAR1_R { + CH2_DAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_DAR1") + .field("ch2_dar1", &format_args!("{}", self.ch2_dar1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dar1(&mut self) -> CH2_DAR1_W { + CH2_DAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_dar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_DAR1_SPEC; +impl crate::RegisterSpec for CH2_DAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_dar1::R`](R) reader structure"] +impl crate::Readable for CH2_DAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_dar1::W`](W) writer structure"] +impl crate::Writable for CH2_DAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_DAR1 to value 0"] +impl crate::Resettable for CH2_DAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_dstat0.rs b/esp32p4/src/dma/ch2_dstat0.rs new file mode 100644 index 0000000000..8b3b6eb29d --- /dev/null +++ b/esp32p4/src/dma/ch2_dstat0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `CH2_DSTAT0` reader"] +pub type R = crate::R; +#[doc = "Field `CH2_DSTAT` reader - NA"] +pub type CH2_DSTAT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch2_dstat(&self) -> CH2_DSTAT_R { + CH2_DSTAT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_DSTAT0") + .field("ch2_dstat", &format_args!("{}", self.ch2_dstat().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_dstat0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_DSTAT0_SPEC; +impl crate::RegisterSpec for CH2_DSTAT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_dstat0::R`](R) reader structure"] +impl crate::Readable for CH2_DSTAT0_SPEC {} +#[doc = "`reset()` method sets CH2_DSTAT0 to value 0"] +impl crate::Resettable for CH2_DSTAT0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_dstatar0.rs b/esp32p4/src/dma/ch2_dstatar0.rs new file mode 100644 index 0000000000..c1939cd81a --- /dev/null +++ b/esp32p4/src/dma/ch2_dstatar0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH2_DSTATAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_DSTATAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_DSTATAR0` reader - NA"] +pub type CH2_DSTATAR0_R = crate::FieldReader; +#[doc = "Field `CH2_DSTATAR0` writer - NA"] +pub type CH2_DSTATAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch2_dstatar0(&self) -> CH2_DSTATAR0_R { + CH2_DSTATAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_DSTATAR0") + .field( + "ch2_dstatar0", + &format_args!("{}", self.ch2_dstatar0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dstatar0(&mut self) -> CH2_DSTATAR0_W { + CH2_DSTATAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_dstatar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dstatar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_DSTATAR0_SPEC; +impl crate::RegisterSpec for CH2_DSTATAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_dstatar0::R`](R) reader structure"] +impl crate::Readable for CH2_DSTATAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_dstatar0::W`](W) writer structure"] +impl crate::Writable for CH2_DSTATAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_DSTATAR0 to value 0"] +impl crate::Resettable for CH2_DSTATAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_dstatar1.rs b/esp32p4/src/dma/ch2_dstatar1.rs new file mode 100644 index 0000000000..b999a7e9be --- /dev/null +++ b/esp32p4/src/dma/ch2_dstatar1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH2_DSTATAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_DSTATAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_DSTATAR1` reader - NA"] +pub type CH2_DSTATAR1_R = crate::FieldReader; +#[doc = "Field `CH2_DSTATAR1` writer - NA"] +pub type CH2_DSTATAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch2_dstatar1(&self) -> CH2_DSTATAR1_R { + CH2_DSTATAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_DSTATAR1") + .field( + "ch2_dstatar1", + &format_args!("{}", self.ch2_dstatar1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_dstatar1(&mut self) -> CH2_DSTATAR1_W { + CH2_DSTATAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_dstatar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_dstatar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_DSTATAR1_SPEC; +impl crate::RegisterSpec for CH2_DSTATAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_dstatar1::R`](R) reader structure"] +impl crate::Readable for CH2_DSTATAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_dstatar1::W`](W) writer structure"] +impl crate::Writable for CH2_DSTATAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_DSTATAR1 to value 0"] +impl crate::Resettable for CH2_DSTATAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_intclear0.rs b/esp32p4/src/dma/ch2_intclear0.rs new file mode 100644 index 0000000000..8f912f36ee --- /dev/null +++ b/esp32p4/src/dma/ch2_intclear0.rs @@ -0,0 +1,294 @@ +#[doc = "Register `CH2_INTCLEAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT` writer - NA"] +pub type CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_DMA_TFR_DONE_INTSTAT` writer - NA"] +pub type CH2_CLEAR_DMA_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SRC_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_DST_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH2_CLEAR_DST_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SRC_DEC_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SRC_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_DST_DEC_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_DST_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SRC_SLV_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SRC_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_DST_SLV_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_DST_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT` writer - NA"] +pub type CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT` writer - NA"] +pub type CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_CH_SUSPENDED_INTSTAT` writer - NA"] +pub type CH2_CLEAR_CH_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_CH_DISABLED_INTSTAT` writer - NA"] +pub type CH2_CLEAR_CH_DISABLED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_CH_ABORTED_INTSTAT` writer - NA"] +pub type CH2_CLEAR_CH_ABORTED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_block_tfr_done_intstat( + &mut self, + ) -> CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_W { + CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_dma_tfr_done_intstat( + &mut self, + ) -> CH2_CLEAR_DMA_TFR_DONE_INTSTAT_W { + CH2_CLEAR_DMA_TFR_DONE_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_src_transcomp_intstat( + &mut self, + ) -> CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_W { + CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_dst_transcomp_intstat( + &mut self, + ) -> CH2_CLEAR_DST_TRANSCOMP_INTSTAT_W { + CH2_CLEAR_DST_TRANSCOMP_INTSTAT_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_src_dec_err_intstat( + &mut self, + ) -> CH2_CLEAR_SRC_DEC_ERR_INTSTAT_W { + CH2_CLEAR_SRC_DEC_ERR_INTSTAT_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_dst_dec_err_intstat( + &mut self, + ) -> CH2_CLEAR_DST_DEC_ERR_INTSTAT_W { + CH2_CLEAR_DST_DEC_ERR_INTSTAT_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_src_slv_err_intstat( + &mut self, + ) -> CH2_CLEAR_SRC_SLV_ERR_INTSTAT_W { + CH2_CLEAR_SRC_SLV_ERR_INTSTAT_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_dst_slv_err_intstat( + &mut self, + ) -> CH2_CLEAR_DST_SLV_ERR_INTSTAT_W { + CH2_CLEAR_DST_SLV_ERR_INTSTAT_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_lli_rd_dec_err_intstat( + &mut self, + ) -> CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W { + CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_lli_wr_dec_err_intstat( + &mut self, + ) -> CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W { + CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_lli_rd_slv_err_intstat( + &mut self, + ) -> CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W { + CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_lli_wr_slv_err_intstat( + &mut self, + ) -> CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W { + CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_shadowreg_or_lli_invalid_err_intstat( + &mut self, + ) -> CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W { + CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_slvif_multiblktype_err_intstat( + &mut self, + ) -> CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W { + CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_slvif_dec_err_intstat( + &mut self, + ) -> CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_W { + CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_slvif_wr2ro_err_intstat( + &mut self, + ) -> CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W { + CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_slvif_rd2rwo_err_intstat( + &mut self, + ) -> CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W { + CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_slvif_wronchen_err_intstat( + &mut self, + ) -> CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W { + CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_slvif_shadowreg_wron_valid_err_intstat( + &mut self, + ) -> CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W { + CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_slvif_wronhold_err_intstat( + &mut self, + ) -> CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W { + CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W::new(self, 21) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_slvif_wrparity_err_intstat( + &mut self, + ) -> CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W { + CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W::new(self, 25) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_ch_lock_cleared_intstat( + &mut self, + ) -> CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_W { + CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_ch_src_suspended_intstat( + &mut self, + ) -> CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W { + CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_ch_suspended_intstat( + &mut self, + ) -> CH2_CLEAR_CH_SUSPENDED_INTSTAT_W { + CH2_CLEAR_CH_SUSPENDED_INTSTAT_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_ch_disabled_intstat( + &mut self, + ) -> CH2_CLEAR_CH_DISABLED_INTSTAT_W { + CH2_CLEAR_CH_DISABLED_INTSTAT_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_ch_aborted_intstat( + &mut self, + ) -> CH2_CLEAR_CH_ABORTED_INTSTAT_W { + CH2_CLEAR_CH_ABORTED_INTSTAT_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_intclear0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_INTCLEAR0_SPEC; +impl crate::RegisterSpec for CH2_INTCLEAR0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch2_intclear0::W`](W) writer structure"] +impl crate::Writable for CH2_INTCLEAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_INTCLEAR0 to value 0"] +impl crate::Resettable for CH2_INTCLEAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_intclear1.rs b/esp32p4/src/dma/ch2_intclear1.rs new file mode 100644 index 0000000000..9708d9a9ad --- /dev/null +++ b/esp32p4/src/dma/ch2_intclear1.rs @@ -0,0 +1,74 @@ +#[doc = "Register `CH2_INTCLEAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` writer - NA"] +pub type CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_ecc_prot_chmem_correrr_intstat( + &mut self, + ) -> CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W { + CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_ecc_prot_chmem_uncorrerr_intstat( + &mut self, + ) -> CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W { + CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_ecc_prot_uidmem_correrr_intstat( + &mut self, + ) -> CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W { + CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_clear_ecc_prot_uidmem_uncorrerr_intstat( + &mut self, + ) -> CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W { + CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_intclear1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_INTCLEAR1_SPEC; +impl crate::RegisterSpec for CH2_INTCLEAR1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch2_intclear1::W`](W) writer structure"] +impl crate::Writable for CH2_INTCLEAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_INTCLEAR1 to value 0"] +impl crate::Resettable for CH2_INTCLEAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_intsignal_enable0.rs b/esp32p4/src/dma/ch2_intsignal_enable0.rs new file mode 100644 index 0000000000..d50cdf805f --- /dev/null +++ b/esp32p4/src/dma/ch2_intsignal_enable0.rs @@ -0,0 +1,606 @@ +#[doc = "Register `CH2_INTSIGNAL_ENABLE0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_INTSIGNAL_ENABLE0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_DST_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_DST_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_DST_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_DST_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_CH_SUSPENDED_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_SUSPENDED_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_CH_DISABLED_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_CH_DISABLED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_DISABLED_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_CH_DISABLED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_CH_ABORTED_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_CH_ABORTED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_ABORTED_INTSIGNAL` writer - NA"] +pub type CH2_ENABLE_CH_ABORTED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch2_enable_block_tfr_done_intsignal(&self) -> CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R { + CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch2_enable_dma_tfr_done_intsignal(&self) -> CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_R { + CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch2_enable_src_transcomp_intsignal(&self) -> CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R { + CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch2_enable_dst_transcomp_intsignal(&self) -> CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_R { + CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch2_enable_src_dec_err_intsignal(&self) -> CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_R { + CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch2_enable_dst_dec_err_intsignal(&self) -> CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_R { + CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch2_enable_src_slv_err_intsignal(&self) -> CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_R { + CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch2_enable_dst_slv_err_intsignal(&self) -> CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_R { + CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch2_enable_lli_rd_dec_err_intsignal(&self) -> CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R { + CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch2_enable_lli_wr_dec_err_intsignal(&self) -> CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R { + CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch2_enable_lli_rd_slv_err_intsignal(&self) -> CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R { + CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch2_enable_lli_wr_slv_err_intsignal(&self) -> CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R { + CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch2_enable_shadowreg_or_lli_invalid_err_intsignal( + &self, + ) -> CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R { + CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_multiblktype_err_intsignal( + &self, + ) -> CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R { + CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_dec_err_intsignal(&self) -> CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R { + CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_wr2ro_err_intsignal(&self) -> CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R { + CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_rd2rwo_err_intsignal(&self) -> CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R { + CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_wronchen_err_intsignal( + &self, + ) -> CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R { + CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_shadowreg_wron_valid_err_intsignal( + &self, + ) -> CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R { + CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_wronhold_err_intsignal( + &self, + ) -> CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R { + CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_wrparity_err_intsignal( + &self, + ) -> CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R { + CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch2_enable_ch_lock_cleared_intsignal(&self) -> CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R { + CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch2_enable_ch_src_suspended_intsignal(&self) -> CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R { + CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch2_enable_ch_suspended_intsignal(&self) -> CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_R { + CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch2_enable_ch_disabled_intsignal(&self) -> CH2_ENABLE_CH_DISABLED_INTSIGNAL_R { + CH2_ENABLE_CH_DISABLED_INTSIGNAL_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch2_enable_ch_aborted_intsignal(&self) -> CH2_ENABLE_CH_ABORTED_INTSIGNAL_R { + CH2_ENABLE_CH_ABORTED_INTSIGNAL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_INTSIGNAL_ENABLE0") + .field( + "ch2_enable_block_tfr_done_intsignal", + &format_args!("{}", self.ch2_enable_block_tfr_done_intsignal().bit()), + ) + .field( + "ch2_enable_dma_tfr_done_intsignal", + &format_args!("{}", self.ch2_enable_dma_tfr_done_intsignal().bit()), + ) + .field( + "ch2_enable_src_transcomp_intsignal", + &format_args!("{}", self.ch2_enable_src_transcomp_intsignal().bit()), + ) + .field( + "ch2_enable_dst_transcomp_intsignal", + &format_args!("{}", self.ch2_enable_dst_transcomp_intsignal().bit()), + ) + .field( + "ch2_enable_src_dec_err_intsignal", + &format_args!("{}", self.ch2_enable_src_dec_err_intsignal().bit()), + ) + .field( + "ch2_enable_dst_dec_err_intsignal", + &format_args!("{}", self.ch2_enable_dst_dec_err_intsignal().bit()), + ) + .field( + "ch2_enable_src_slv_err_intsignal", + &format_args!("{}", self.ch2_enable_src_slv_err_intsignal().bit()), + ) + .field( + "ch2_enable_dst_slv_err_intsignal", + &format_args!("{}", self.ch2_enable_dst_slv_err_intsignal().bit()), + ) + .field( + "ch2_enable_lli_rd_dec_err_intsignal", + &format_args!("{}", self.ch2_enable_lli_rd_dec_err_intsignal().bit()), + ) + .field( + "ch2_enable_lli_wr_dec_err_intsignal", + &format_args!("{}", self.ch2_enable_lli_wr_dec_err_intsignal().bit()), + ) + .field( + "ch2_enable_lli_rd_slv_err_intsignal", + &format_args!("{}", self.ch2_enable_lli_rd_slv_err_intsignal().bit()), + ) + .field( + "ch2_enable_lli_wr_slv_err_intsignal", + &format_args!("{}", self.ch2_enable_lli_wr_slv_err_intsignal().bit()), + ) + .field( + "ch2_enable_shadowreg_or_lli_invalid_err_intsignal", + &format_args!( + "{}", + self.ch2_enable_shadowreg_or_lli_invalid_err_intsignal() + .bit() + ), + ) + .field( + "ch2_enable_slvif_multiblktype_err_intsignal", + &format_args!( + "{}", + self.ch2_enable_slvif_multiblktype_err_intsignal().bit() + ), + ) + .field( + "ch2_enable_slvif_dec_err_intsignal", + &format_args!("{}", self.ch2_enable_slvif_dec_err_intsignal().bit()), + ) + .field( + "ch2_enable_slvif_wr2ro_err_intsignal", + &format_args!("{}", self.ch2_enable_slvif_wr2ro_err_intsignal().bit()), + ) + .field( + "ch2_enable_slvif_rd2rwo_err_intsignal", + &format_args!("{}", self.ch2_enable_slvif_rd2rwo_err_intsignal().bit()), + ) + .field( + "ch2_enable_slvif_wronchen_err_intsignal", + &format_args!("{}", self.ch2_enable_slvif_wronchen_err_intsignal().bit()), + ) + .field( + "ch2_enable_slvif_shadowreg_wron_valid_err_intsignal", + &format_args!( + "{}", + self.ch2_enable_slvif_shadowreg_wron_valid_err_intsignal() + .bit() + ), + ) + .field( + "ch2_enable_slvif_wronhold_err_intsignal", + &format_args!("{}", self.ch2_enable_slvif_wronhold_err_intsignal().bit()), + ) + .field( + "ch2_enable_slvif_wrparity_err_intsignal", + &format_args!("{}", self.ch2_enable_slvif_wrparity_err_intsignal().bit()), + ) + .field( + "ch2_enable_ch_lock_cleared_intsignal", + &format_args!("{}", self.ch2_enable_ch_lock_cleared_intsignal().bit()), + ) + .field( + "ch2_enable_ch_src_suspended_intsignal", + &format_args!("{}", self.ch2_enable_ch_src_suspended_intsignal().bit()), + ) + .field( + "ch2_enable_ch_suspended_intsignal", + &format_args!("{}", self.ch2_enable_ch_suspended_intsignal().bit()), + ) + .field( + "ch2_enable_ch_disabled_intsignal", + &format_args!("{}", self.ch2_enable_ch_disabled_intsignal().bit()), + ) + .field( + "ch2_enable_ch_aborted_intsignal", + &format_args!("{}", self.ch2_enable_ch_aborted_intsignal().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_block_tfr_done_intsignal( + &mut self, + ) -> CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W { + CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_dma_tfr_done_intsignal( + &mut self, + ) -> CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_W { + CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_src_transcomp_intsignal( + &mut self, + ) -> CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W { + CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_dst_transcomp_intsignal( + &mut self, + ) -> CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_W { + CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_src_dec_err_intsignal( + &mut self, + ) -> CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_W { + CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_dst_dec_err_intsignal( + &mut self, + ) -> CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_W { + CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_src_slv_err_intsignal( + &mut self, + ) -> CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_W { + CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_dst_slv_err_intsignal( + &mut self, + ) -> CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_W { + CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_lli_rd_dec_err_intsignal( + &mut self, + ) -> CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W { + CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_lli_wr_dec_err_intsignal( + &mut self, + ) -> CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W { + CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_lli_rd_slv_err_intsignal( + &mut self, + ) -> CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W { + CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_lli_wr_slv_err_intsignal( + &mut self, + ) -> CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W { + CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_shadowreg_or_lli_invalid_err_intsignal( + &mut self, + ) -> CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W { + CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_multiblktype_err_intsignal( + &mut self, + ) -> CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W { + CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_dec_err_intsignal( + &mut self, + ) -> CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W { + CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_wr2ro_err_intsignal( + &mut self, + ) -> CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W { + CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_rd2rwo_err_intsignal( + &mut self, + ) -> CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W { + CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_wronchen_err_intsignal( + &mut self, + ) -> CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W { + CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_shadowreg_wron_valid_err_intsignal( + &mut self, + ) -> CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W { + CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_wronhold_err_intsignal( + &mut self, + ) -> CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W { + CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W::new(self, 21) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_ch_lock_cleared_intsignal( + &mut self, + ) -> CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W { + CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_ch_src_suspended_intsignal( + &mut self, + ) -> CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W { + CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_ch_suspended_intsignal( + &mut self, + ) -> CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_W { + CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_ch_disabled_intsignal( + &mut self, + ) -> CH2_ENABLE_CH_DISABLED_INTSIGNAL_W { + CH2_ENABLE_CH_DISABLED_INTSIGNAL_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_ch_aborted_intsignal( + &mut self, + ) -> CH2_ENABLE_CH_ABORTED_INTSIGNAL_W { + CH2_ENABLE_CH_ABORTED_INTSIGNAL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intsignal_enable0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_intsignal_enable0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_INTSIGNAL_ENABLE0_SPEC; +impl crate::RegisterSpec for CH2_INTSIGNAL_ENABLE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_intsignal_enable0::R`](R) reader structure"] +impl crate::Readable for CH2_INTSIGNAL_ENABLE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_intsignal_enable0::W`](W) writer structure"] +impl crate::Writable for CH2_INTSIGNAL_ENABLE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_INTSIGNAL_ENABLE0 to value 0xfa3f_7ffb"] +impl crate::Resettable for CH2_INTSIGNAL_ENABLE0_SPEC { + const RESET_VALUE: Self::Ux = 0xfa3f_7ffb; +} diff --git a/esp32p4/src/dma/ch2_intsignal_enable1.rs b/esp32p4/src/dma/ch2_intsignal_enable1.rs new file mode 100644 index 0000000000..a0fff48964 --- /dev/null +++ b/esp32p4/src/dma/ch2_intsignal_enable1.rs @@ -0,0 +1,92 @@ +#[doc = "Register `CH2_INTSIGNAL_ENABLE1` reader"] +pub type R = crate::R; +#[doc = "Field `CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL` reader - NA"] +pub type CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch2_enable_ecc_prot_chmem_correrr_intsignal( + &self, + ) -> CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R { + CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch2_enable_ecc_prot_chmem_uncorrerr_intsignal( + &self, + ) -> CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R { + CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch2_enable_ecc_prot_uidmem_correrr_intsignal( + &self, + ) -> CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R { + CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal( + &self, + ) -> CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R { + CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_INTSIGNAL_ENABLE1") + .field( + "ch2_enable_ecc_prot_chmem_correrr_intsignal", + &format_args!( + "{}", + self.ch2_enable_ecc_prot_chmem_correrr_intsignal().bit() + ), + ) + .field( + "ch2_enable_ecc_prot_chmem_uncorrerr_intsignal", + &format_args!( + "{}", + self.ch2_enable_ecc_prot_chmem_uncorrerr_intsignal().bit() + ), + ) + .field( + "ch2_enable_ecc_prot_uidmem_correrr_intsignal", + &format_args!( + "{}", + self.ch2_enable_ecc_prot_uidmem_correrr_intsignal().bit() + ), + ) + .field( + "ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal", + &format_args!( + "{}", + self.ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal().bit() + ), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intsignal_enable1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_INTSIGNAL_ENABLE1_SPEC; +impl crate::RegisterSpec for CH2_INTSIGNAL_ENABLE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_intsignal_enable1::R`](R) reader structure"] +impl crate::Readable for CH2_INTSIGNAL_ENABLE1_SPEC {} +#[doc = "`reset()` method sets CH2_INTSIGNAL_ENABLE1 to value 0x0f"] +impl crate::Resettable for CH2_INTSIGNAL_ENABLE1_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/dma/ch2_intstatus0.rs b/esp32p4/src/dma/ch2_intstatus0.rs new file mode 100644 index 0000000000..7222ff02b1 --- /dev/null +++ b/esp32p4/src/dma/ch2_intstatus0.rs @@ -0,0 +1,321 @@ +#[doc = "Register `CH2_INTSTATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `CH2_BLOCK_TFR_DONE_INTSTAT` reader - NA"] +pub type CH2_BLOCK_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_DMA_TFR_DONE_INTSTAT` reader - NA"] +pub type CH2_DMA_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SRC_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH2_SRC_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_DST_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH2_DST_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SRC_DEC_ERR_INTSTAT` reader - NA"] +pub type CH2_SRC_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_DST_DEC_ERR_INTSTAT` reader - NA"] +pub type CH2_DST_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SRC_SLV_ERR_INTSTAT` reader - NA"] +pub type CH2_SRC_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_DST_SLV_ERR_INTSTAT` reader - NA"] +pub type CH2_DST_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_LLI_RD_DEC_ERR_INTSTAT` reader - NA"] +pub type CH2_LLI_RD_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_LLI_WR_DEC_ERR_INTSTAT` reader - NA"] +pub type CH2_LLI_WR_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_LLI_RD_SLV_ERR_INTSTAT` reader - NA"] +pub type CH2_LLI_RD_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_LLI_WR_SLV_ERR_INTSTAT` reader - NA"] +pub type CH2_LLI_WR_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` reader - NA"] +pub type CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` reader - NA"] +pub type CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SLVIF_DEC_ERR_INTSTAT` reader - NA"] +pub type CH2_SLVIF_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SLVIF_WR2RO_ERR_INTSTAT` reader - NA"] +pub type CH2_SLVIF_WR2RO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SLVIF_RD2RWO_ERR_INTSTAT` reader - NA"] +pub type CH2_SLVIF_RD2RWO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SLVIF_WRONCHEN_ERR_INTSTAT` reader - NA"] +pub type CH2_SLVIF_WRONCHEN_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` reader - NA"] +pub type CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SLVIF_WRONHOLD_ERR_INTSTAT` reader - NA"] +pub type CH2_SLVIF_WRONHOLD_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_SLVIF_WRPARITY_ERR_INTSTAT` reader - NA"] +pub type CH2_SLVIF_WRPARITY_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_CH_LOCK_CLEARED_INTSTAT` reader - NA"] +pub type CH2_CH_LOCK_CLEARED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_CH_SRC_SUSPENDED_INTSTAT` reader - NA"] +pub type CH2_CH_SRC_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_CH_SUSPENDED_INTSTAT` reader - NA"] +pub type CH2_CH_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_CH_DISABLED_INTSTAT` reader - NA"] +pub type CH2_CH_DISABLED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_CH_ABORTED_INTSTAT` reader - NA"] +pub type CH2_CH_ABORTED_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch2_block_tfr_done_intstat(&self) -> CH2_BLOCK_TFR_DONE_INTSTAT_R { + CH2_BLOCK_TFR_DONE_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch2_dma_tfr_done_intstat(&self) -> CH2_DMA_TFR_DONE_INTSTAT_R { + CH2_DMA_TFR_DONE_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch2_src_transcomp_intstat(&self) -> CH2_SRC_TRANSCOMP_INTSTAT_R { + CH2_SRC_TRANSCOMP_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch2_dst_transcomp_intstat(&self) -> CH2_DST_TRANSCOMP_INTSTAT_R { + CH2_DST_TRANSCOMP_INTSTAT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch2_src_dec_err_intstat(&self) -> CH2_SRC_DEC_ERR_INTSTAT_R { + CH2_SRC_DEC_ERR_INTSTAT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch2_dst_dec_err_intstat(&self) -> CH2_DST_DEC_ERR_INTSTAT_R { + CH2_DST_DEC_ERR_INTSTAT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch2_src_slv_err_intstat(&self) -> CH2_SRC_SLV_ERR_INTSTAT_R { + CH2_SRC_SLV_ERR_INTSTAT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch2_dst_slv_err_intstat(&self) -> CH2_DST_SLV_ERR_INTSTAT_R { + CH2_DST_SLV_ERR_INTSTAT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch2_lli_rd_dec_err_intstat(&self) -> CH2_LLI_RD_DEC_ERR_INTSTAT_R { + CH2_LLI_RD_DEC_ERR_INTSTAT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch2_lli_wr_dec_err_intstat(&self) -> CH2_LLI_WR_DEC_ERR_INTSTAT_R { + CH2_LLI_WR_DEC_ERR_INTSTAT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch2_lli_rd_slv_err_intstat(&self) -> CH2_LLI_RD_SLV_ERR_INTSTAT_R { + CH2_LLI_RD_SLV_ERR_INTSTAT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch2_lli_wr_slv_err_intstat(&self) -> CH2_LLI_WR_SLV_ERR_INTSTAT_R { + CH2_LLI_WR_SLV_ERR_INTSTAT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch2_shadowreg_or_lli_invalid_err_intstat( + &self, + ) -> CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R { + CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch2_slvif_multiblktype_err_intstat(&self) -> CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R { + CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch2_slvif_dec_err_intstat(&self) -> CH2_SLVIF_DEC_ERR_INTSTAT_R { + CH2_SLVIF_DEC_ERR_INTSTAT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch2_slvif_wr2ro_err_intstat(&self) -> CH2_SLVIF_WR2RO_ERR_INTSTAT_R { + CH2_SLVIF_WR2RO_ERR_INTSTAT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch2_slvif_rd2rwo_err_intstat(&self) -> CH2_SLVIF_RD2RWO_ERR_INTSTAT_R { + CH2_SLVIF_RD2RWO_ERR_INTSTAT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch2_slvif_wronchen_err_intstat(&self) -> CH2_SLVIF_WRONCHEN_ERR_INTSTAT_R { + CH2_SLVIF_WRONCHEN_ERR_INTSTAT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch2_slvif_shadowreg_wron_valid_err_intstat( + &self, + ) -> CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R { + CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch2_slvif_wronhold_err_intstat(&self) -> CH2_SLVIF_WRONHOLD_ERR_INTSTAT_R { + CH2_SLVIF_WRONHOLD_ERR_INTSTAT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch2_slvif_wrparity_err_intstat(&self) -> CH2_SLVIF_WRPARITY_ERR_INTSTAT_R { + CH2_SLVIF_WRPARITY_ERR_INTSTAT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch2_ch_lock_cleared_intstat(&self) -> CH2_CH_LOCK_CLEARED_INTSTAT_R { + CH2_CH_LOCK_CLEARED_INTSTAT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch2_ch_src_suspended_intstat(&self) -> CH2_CH_SRC_SUSPENDED_INTSTAT_R { + CH2_CH_SRC_SUSPENDED_INTSTAT_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch2_ch_suspended_intstat(&self) -> CH2_CH_SUSPENDED_INTSTAT_R { + CH2_CH_SUSPENDED_INTSTAT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch2_ch_disabled_intstat(&self) -> CH2_CH_DISABLED_INTSTAT_R { + CH2_CH_DISABLED_INTSTAT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch2_ch_aborted_intstat(&self) -> CH2_CH_ABORTED_INTSTAT_R { + CH2_CH_ABORTED_INTSTAT_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_INTSTATUS0") + .field( + "ch2_block_tfr_done_intstat", + &format_args!("{}", self.ch2_block_tfr_done_intstat().bit()), + ) + .field( + "ch2_dma_tfr_done_intstat", + &format_args!("{}", self.ch2_dma_tfr_done_intstat().bit()), + ) + .field( + "ch2_src_transcomp_intstat", + &format_args!("{}", self.ch2_src_transcomp_intstat().bit()), + ) + .field( + "ch2_dst_transcomp_intstat", + &format_args!("{}", self.ch2_dst_transcomp_intstat().bit()), + ) + .field( + "ch2_src_dec_err_intstat", + &format_args!("{}", self.ch2_src_dec_err_intstat().bit()), + ) + .field( + "ch2_dst_dec_err_intstat", + &format_args!("{}", self.ch2_dst_dec_err_intstat().bit()), + ) + .field( + "ch2_src_slv_err_intstat", + &format_args!("{}", self.ch2_src_slv_err_intstat().bit()), + ) + .field( + "ch2_dst_slv_err_intstat", + &format_args!("{}", self.ch2_dst_slv_err_intstat().bit()), + ) + .field( + "ch2_lli_rd_dec_err_intstat", + &format_args!("{}", self.ch2_lli_rd_dec_err_intstat().bit()), + ) + .field( + "ch2_lli_wr_dec_err_intstat", + &format_args!("{}", self.ch2_lli_wr_dec_err_intstat().bit()), + ) + .field( + "ch2_lli_rd_slv_err_intstat", + &format_args!("{}", self.ch2_lli_rd_slv_err_intstat().bit()), + ) + .field( + "ch2_lli_wr_slv_err_intstat", + &format_args!("{}", self.ch2_lli_wr_slv_err_intstat().bit()), + ) + .field( + "ch2_shadowreg_or_lli_invalid_err_intstat", + &format_args!("{}", self.ch2_shadowreg_or_lli_invalid_err_intstat().bit()), + ) + .field( + "ch2_slvif_multiblktype_err_intstat", + &format_args!("{}", self.ch2_slvif_multiblktype_err_intstat().bit()), + ) + .field( + "ch2_slvif_dec_err_intstat", + &format_args!("{}", self.ch2_slvif_dec_err_intstat().bit()), + ) + .field( + "ch2_slvif_wr2ro_err_intstat", + &format_args!("{}", self.ch2_slvif_wr2ro_err_intstat().bit()), + ) + .field( + "ch2_slvif_rd2rwo_err_intstat", + &format_args!("{}", self.ch2_slvif_rd2rwo_err_intstat().bit()), + ) + .field( + "ch2_slvif_wronchen_err_intstat", + &format_args!("{}", self.ch2_slvif_wronchen_err_intstat().bit()), + ) + .field( + "ch2_slvif_shadowreg_wron_valid_err_intstat", + &format_args!( + "{}", + self.ch2_slvif_shadowreg_wron_valid_err_intstat().bit() + ), + ) + .field( + "ch2_slvif_wronhold_err_intstat", + &format_args!("{}", self.ch2_slvif_wronhold_err_intstat().bit()), + ) + .field( + "ch2_slvif_wrparity_err_intstat", + &format_args!("{}", self.ch2_slvif_wrparity_err_intstat().bit()), + ) + .field( + "ch2_ch_lock_cleared_intstat", + &format_args!("{}", self.ch2_ch_lock_cleared_intstat().bit()), + ) + .field( + "ch2_ch_src_suspended_intstat", + &format_args!("{}", self.ch2_ch_src_suspended_intstat().bit()), + ) + .field( + "ch2_ch_suspended_intstat", + &format_args!("{}", self.ch2_ch_suspended_intstat().bit()), + ) + .field( + "ch2_ch_disabled_intstat", + &format_args!("{}", self.ch2_ch_disabled_intstat().bit()), + ) + .field( + "ch2_ch_aborted_intstat", + &format_args!("{}", self.ch2_ch_aborted_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intstatus0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_INTSTATUS0_SPEC; +impl crate::RegisterSpec for CH2_INTSTATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_intstatus0::R`](R) reader structure"] +impl crate::Readable for CH2_INTSTATUS0_SPEC {} +#[doc = "`reset()` method sets CH2_INTSTATUS0 to value 0"] +impl crate::Resettable for CH2_INTSTATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_intstatus1.rs b/esp32p4/src/dma/ch2_intstatus1.rs new file mode 100644 index 0000000000..7ea5f53626 --- /dev/null +++ b/esp32p4/src/dma/ch2_intstatus1.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CH2_INTSTATUS1` reader"] +pub type R = crate::R; +#[doc = "Field `CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch2_ecc_prot_chmem_correrr_intstat(&self) -> CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_R { + CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch2_ecc_prot_chmem_uncorrerr_intstat(&self) -> CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R { + CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch2_ecc_prot_uidmem_correrr_intstat(&self) -> CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R { + CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch2_ecc_prot_uidmem_uncorrerr_intstat(&self) -> CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R { + CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_INTSTATUS1") + .field( + "ch2_ecc_prot_chmem_correrr_intstat", + &format_args!("{}", self.ch2_ecc_prot_chmem_correrr_intstat().bit()), + ) + .field( + "ch2_ecc_prot_chmem_uncorrerr_intstat", + &format_args!("{}", self.ch2_ecc_prot_chmem_uncorrerr_intstat().bit()), + ) + .field( + "ch2_ecc_prot_uidmem_correrr_intstat", + &format_args!("{}", self.ch2_ecc_prot_uidmem_correrr_intstat().bit()), + ) + .field( + "ch2_ecc_prot_uidmem_uncorrerr_intstat", + &format_args!("{}", self.ch2_ecc_prot_uidmem_uncorrerr_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intstatus1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_INTSTATUS1_SPEC; +impl crate::RegisterSpec for CH2_INTSTATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_intstatus1::R`](R) reader structure"] +impl crate::Readable for CH2_INTSTATUS1_SPEC {} +#[doc = "`reset()` method sets CH2_INTSTATUS1 to value 0"] +impl crate::Resettable for CH2_INTSTATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_intstatus_enable0.rs b/esp32p4/src/dma/ch2_intstatus_enable0.rs new file mode 100644 index 0000000000..bee61d04cd --- /dev/null +++ b/esp32p4/src/dma/ch2_intstatus_enable0.rs @@ -0,0 +1,596 @@ +#[doc = "Register `CH2_INTSTATUS_ENABLE0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_INTSTATUS_ENABLE0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT` reader - NA"] +pub type CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT` writer - NA"] +pub type CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_DMA_TFR_DONE_INTSTAT` reader - NA"] +pub type CH2_ENABLE_DMA_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_DMA_TFR_DONE_INTSTAT` writer - NA"] +pub type CH2_ENABLE_DMA_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SRC_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SRC_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_DST_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH2_ENABLE_DST_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_DST_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH2_ENABLE_DST_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SRC_DEC_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SRC_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SRC_DEC_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_SRC_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_DST_DEC_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_DST_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_DST_DEC_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_DST_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SRC_SLV_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SRC_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SRC_SLV_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_SRC_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_DST_SLV_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_DST_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_DST_SLV_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_DST_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT` writer - NA"] +pub type CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT` reader - NA"] +pub type CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT` writer - NA"] +pub type CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT` reader - NA"] +pub type CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT` writer - NA"] +pub type CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_CH_SUSPENDED_INTSTAT` reader - NA"] +pub type CH2_ENABLE_CH_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_SUSPENDED_INTSTAT` writer - NA"] +pub type CH2_ENABLE_CH_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_CH_DISABLED_INTSTAT` reader - NA"] +pub type CH2_ENABLE_CH_DISABLED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_DISABLED_INTSTAT` writer - NA"] +pub type CH2_ENABLE_CH_DISABLED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ENABLE_CH_ABORTED_INTSTAT` reader - NA"] +pub type CH2_ENABLE_CH_ABORTED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_CH_ABORTED_INTSTAT` writer - NA"] +pub type CH2_ENABLE_CH_ABORTED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch2_enable_block_tfr_done_intstat(&self) -> CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_R { + CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch2_enable_dma_tfr_done_intstat(&self) -> CH2_ENABLE_DMA_TFR_DONE_INTSTAT_R { + CH2_ENABLE_DMA_TFR_DONE_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch2_enable_src_transcomp_intstat(&self) -> CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_R { + CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch2_enable_dst_transcomp_intstat(&self) -> CH2_ENABLE_DST_TRANSCOMP_INTSTAT_R { + CH2_ENABLE_DST_TRANSCOMP_INTSTAT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch2_enable_src_dec_err_intstat(&self) -> CH2_ENABLE_SRC_DEC_ERR_INTSTAT_R { + CH2_ENABLE_SRC_DEC_ERR_INTSTAT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch2_enable_dst_dec_err_intstat(&self) -> CH2_ENABLE_DST_DEC_ERR_INTSTAT_R { + CH2_ENABLE_DST_DEC_ERR_INTSTAT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch2_enable_src_slv_err_intstat(&self) -> CH2_ENABLE_SRC_SLV_ERR_INTSTAT_R { + CH2_ENABLE_SRC_SLV_ERR_INTSTAT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch2_enable_dst_slv_err_intstat(&self) -> CH2_ENABLE_DST_SLV_ERR_INTSTAT_R { + CH2_ENABLE_DST_SLV_ERR_INTSTAT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch2_enable_lli_rd_dec_err_intstat(&self) -> CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R { + CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch2_enable_lli_wr_dec_err_intstat(&self) -> CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R { + CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch2_enable_lli_rd_slv_err_intstat(&self) -> CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R { + CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch2_enable_lli_wr_slv_err_intstat(&self) -> CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R { + CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch2_enable_shadowreg_or_lli_invalid_err_intstat( + &self, + ) -> CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R { + CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_multiblktype_err_intstat( + &self, + ) -> CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R { + CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_dec_err_intstat(&self) -> CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_R { + CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_wr2ro_err_intstat(&self) -> CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R { + CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_rd2rwo_err_intstat(&self) -> CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R { + CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_wronchen_err_intstat(&self) -> CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R { + CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_shadowreg_wron_valid_err_intstat( + &self, + ) -> CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R { + CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_wronhold_err_intstat(&self) -> CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R { + CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch2_enable_slvif_wrparity_err_intstat(&self) -> CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R { + CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch2_enable_ch_lock_cleared_intstat(&self) -> CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_R { + CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch2_enable_ch_src_suspended_intstat(&self) -> CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R { + CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch2_enable_ch_suspended_intstat(&self) -> CH2_ENABLE_CH_SUSPENDED_INTSTAT_R { + CH2_ENABLE_CH_SUSPENDED_INTSTAT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch2_enable_ch_disabled_intstat(&self) -> CH2_ENABLE_CH_DISABLED_INTSTAT_R { + CH2_ENABLE_CH_DISABLED_INTSTAT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch2_enable_ch_aborted_intstat(&self) -> CH2_ENABLE_CH_ABORTED_INTSTAT_R { + CH2_ENABLE_CH_ABORTED_INTSTAT_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_INTSTATUS_ENABLE0") + .field( + "ch2_enable_block_tfr_done_intstat", + &format_args!("{}", self.ch2_enable_block_tfr_done_intstat().bit()), + ) + .field( + "ch2_enable_dma_tfr_done_intstat", + &format_args!("{}", self.ch2_enable_dma_tfr_done_intstat().bit()), + ) + .field( + "ch2_enable_src_transcomp_intstat", + &format_args!("{}", self.ch2_enable_src_transcomp_intstat().bit()), + ) + .field( + "ch2_enable_dst_transcomp_intstat", + &format_args!("{}", self.ch2_enable_dst_transcomp_intstat().bit()), + ) + .field( + "ch2_enable_src_dec_err_intstat", + &format_args!("{}", self.ch2_enable_src_dec_err_intstat().bit()), + ) + .field( + "ch2_enable_dst_dec_err_intstat", + &format_args!("{}", self.ch2_enable_dst_dec_err_intstat().bit()), + ) + .field( + "ch2_enable_src_slv_err_intstat", + &format_args!("{}", self.ch2_enable_src_slv_err_intstat().bit()), + ) + .field( + "ch2_enable_dst_slv_err_intstat", + &format_args!("{}", self.ch2_enable_dst_slv_err_intstat().bit()), + ) + .field( + "ch2_enable_lli_rd_dec_err_intstat", + &format_args!("{}", self.ch2_enable_lli_rd_dec_err_intstat().bit()), + ) + .field( + "ch2_enable_lli_wr_dec_err_intstat", + &format_args!("{}", self.ch2_enable_lli_wr_dec_err_intstat().bit()), + ) + .field( + "ch2_enable_lli_rd_slv_err_intstat", + &format_args!("{}", self.ch2_enable_lli_rd_slv_err_intstat().bit()), + ) + .field( + "ch2_enable_lli_wr_slv_err_intstat", + &format_args!("{}", self.ch2_enable_lli_wr_slv_err_intstat().bit()), + ) + .field( + "ch2_enable_shadowreg_or_lli_invalid_err_intstat", + &format_args!( + "{}", + self.ch2_enable_shadowreg_or_lli_invalid_err_intstat().bit() + ), + ) + .field( + "ch2_enable_slvif_multiblktype_err_intstat", + &format_args!("{}", self.ch2_enable_slvif_multiblktype_err_intstat().bit()), + ) + .field( + "ch2_enable_slvif_dec_err_intstat", + &format_args!("{}", self.ch2_enable_slvif_dec_err_intstat().bit()), + ) + .field( + "ch2_enable_slvif_wr2ro_err_intstat", + &format_args!("{}", self.ch2_enable_slvif_wr2ro_err_intstat().bit()), + ) + .field( + "ch2_enable_slvif_rd2rwo_err_intstat", + &format_args!("{}", self.ch2_enable_slvif_rd2rwo_err_intstat().bit()), + ) + .field( + "ch2_enable_slvif_wronchen_err_intstat", + &format_args!("{}", self.ch2_enable_slvif_wronchen_err_intstat().bit()), + ) + .field( + "ch2_enable_slvif_shadowreg_wron_valid_err_intstat", + &format_args!( + "{}", + self.ch2_enable_slvif_shadowreg_wron_valid_err_intstat() + .bit() + ), + ) + .field( + "ch2_enable_slvif_wronhold_err_intstat", + &format_args!("{}", self.ch2_enable_slvif_wronhold_err_intstat().bit()), + ) + .field( + "ch2_enable_slvif_wrparity_err_intstat", + &format_args!("{}", self.ch2_enable_slvif_wrparity_err_intstat().bit()), + ) + .field( + "ch2_enable_ch_lock_cleared_intstat", + &format_args!("{}", self.ch2_enable_ch_lock_cleared_intstat().bit()), + ) + .field( + "ch2_enable_ch_src_suspended_intstat", + &format_args!("{}", self.ch2_enable_ch_src_suspended_intstat().bit()), + ) + .field( + "ch2_enable_ch_suspended_intstat", + &format_args!("{}", self.ch2_enable_ch_suspended_intstat().bit()), + ) + .field( + "ch2_enable_ch_disabled_intstat", + &format_args!("{}", self.ch2_enable_ch_disabled_intstat().bit()), + ) + .field( + "ch2_enable_ch_aborted_intstat", + &format_args!("{}", self.ch2_enable_ch_aborted_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_block_tfr_done_intstat( + &mut self, + ) -> CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_W { + CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_dma_tfr_done_intstat( + &mut self, + ) -> CH2_ENABLE_DMA_TFR_DONE_INTSTAT_W { + CH2_ENABLE_DMA_TFR_DONE_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_src_transcomp_intstat( + &mut self, + ) -> CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_W { + CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_dst_transcomp_intstat( + &mut self, + ) -> CH2_ENABLE_DST_TRANSCOMP_INTSTAT_W { + CH2_ENABLE_DST_TRANSCOMP_INTSTAT_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_src_dec_err_intstat( + &mut self, + ) -> CH2_ENABLE_SRC_DEC_ERR_INTSTAT_W { + CH2_ENABLE_SRC_DEC_ERR_INTSTAT_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_dst_dec_err_intstat( + &mut self, + ) -> CH2_ENABLE_DST_DEC_ERR_INTSTAT_W { + CH2_ENABLE_DST_DEC_ERR_INTSTAT_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_src_slv_err_intstat( + &mut self, + ) -> CH2_ENABLE_SRC_SLV_ERR_INTSTAT_W { + CH2_ENABLE_SRC_SLV_ERR_INTSTAT_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_dst_slv_err_intstat( + &mut self, + ) -> CH2_ENABLE_DST_SLV_ERR_INTSTAT_W { + CH2_ENABLE_DST_SLV_ERR_INTSTAT_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_lli_rd_dec_err_intstat( + &mut self, + ) -> CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W { + CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_lli_wr_dec_err_intstat( + &mut self, + ) -> CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W { + CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_lli_rd_slv_err_intstat( + &mut self, + ) -> CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W { + CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_lli_wr_slv_err_intstat( + &mut self, + ) -> CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W { + CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_shadowreg_or_lli_invalid_err_intstat( + &mut self, + ) -> CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W { + CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_multiblktype_err_intstat( + &mut self, + ) -> CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W { + CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_dec_err_intstat( + &mut self, + ) -> CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_W { + CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_wr2ro_err_intstat( + &mut self, + ) -> CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W { + CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_rd2rwo_err_intstat( + &mut self, + ) -> CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W { + CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_wronchen_err_intstat( + &mut self, + ) -> CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W { + CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_shadowreg_wron_valid_err_intstat( + &mut self, + ) -> CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W { + CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_slvif_wronhold_err_intstat( + &mut self, + ) -> CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W { + CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W::new(self, 21) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_ch_lock_cleared_intstat( + &mut self, + ) -> CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_W { + CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_ch_src_suspended_intstat( + &mut self, + ) -> CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W { + CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_ch_suspended_intstat( + &mut self, + ) -> CH2_ENABLE_CH_SUSPENDED_INTSTAT_W { + CH2_ENABLE_CH_SUSPENDED_INTSTAT_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_ch_disabled_intstat( + &mut self, + ) -> CH2_ENABLE_CH_DISABLED_INTSTAT_W { + CH2_ENABLE_CH_DISABLED_INTSTAT_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_enable_ch_aborted_intstat( + &mut self, + ) -> CH2_ENABLE_CH_ABORTED_INTSTAT_W { + CH2_ENABLE_CH_ABORTED_INTSTAT_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intstatus_enable0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_intstatus_enable0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_INTSTATUS_ENABLE0_SPEC; +impl crate::RegisterSpec for CH2_INTSTATUS_ENABLE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_intstatus_enable0::R`](R) reader structure"] +impl crate::Readable for CH2_INTSTATUS_ENABLE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_intstatus_enable0::W`](W) writer structure"] +impl crate::Writable for CH2_INTSTATUS_ENABLE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_INTSTATUS_ENABLE0 to value 0xfa3f_7ffb"] +impl crate::Resettable for CH2_INTSTATUS_ENABLE0_SPEC { + const RESET_VALUE: Self::Ux = 0xfa3f_7ffb; +} diff --git a/esp32p4/src/dma/ch2_intstatus_enable1.rs b/esp32p4/src/dma/ch2_intstatus_enable1.rs new file mode 100644 index 0000000000..b7d1ad2a9a --- /dev/null +++ b/esp32p4/src/dma/ch2_intstatus_enable1.rs @@ -0,0 +1,89 @@ +#[doc = "Register `CH2_INTSTATUS_ENABLE1` reader"] +pub type R = crate::R; +#[doc = "Field `CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch2_enable_ecc_prot_chmem_correrr_intstat( + &self, + ) -> CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R { + CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch2_enable_ecc_prot_chmem_uncorrerr_intstat( + &self, + ) -> CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R { + CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch2_enable_ecc_prot_uidmem_correrr_intstat( + &self, + ) -> CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R { + CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch2_enable_ecc_prot_uidmem_uncorrerr_intstat( + &self, + ) -> CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R { + CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_INTSTATUS_ENABLE1") + .field( + "ch2_enable_ecc_prot_chmem_correrr_intstat", + &format_args!("{}", self.ch2_enable_ecc_prot_chmem_correrr_intstat().bit()), + ) + .field( + "ch2_enable_ecc_prot_chmem_uncorrerr_intstat", + &format_args!( + "{}", + self.ch2_enable_ecc_prot_chmem_uncorrerr_intstat().bit() + ), + ) + .field( + "ch2_enable_ecc_prot_uidmem_correrr_intstat", + &format_args!( + "{}", + self.ch2_enable_ecc_prot_uidmem_correrr_intstat().bit() + ), + ) + .field( + "ch2_enable_ecc_prot_uidmem_uncorrerr_intstat", + &format_args!( + "{}", + self.ch2_enable_ecc_prot_uidmem_uncorrerr_intstat().bit() + ), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_intstatus_enable1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_INTSTATUS_ENABLE1_SPEC; +impl crate::RegisterSpec for CH2_INTSTATUS_ENABLE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_intstatus_enable1::R`](R) reader structure"] +impl crate::Readable for CH2_INTSTATUS_ENABLE1_SPEC {} +#[doc = "`reset()` method sets CH2_INTSTATUS_ENABLE1 to value 0x0f"] +impl crate::Resettable for CH2_INTSTATUS_ENABLE1_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/dma/ch2_llp0.rs b/esp32p4/src/dma/ch2_llp0.rs new file mode 100644 index 0000000000..6f894ce7ad --- /dev/null +++ b/esp32p4/src/dma/ch2_llp0.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CH2_LLP0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_LLP0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_LMS` reader - NA"] +pub type CH2_LMS_R = crate::BitReader; +#[doc = "Field `CH2_LMS` writer - NA"] +pub type CH2_LMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_LOC0` reader - NA"] +pub type CH2_LOC0_R = crate::FieldReader; +#[doc = "Field `CH2_LOC0` writer - NA"] +pub type CH2_LOC0_W<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch2_lms(&self) -> CH2_LMS_R { + CH2_LMS_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 6:31 - NA"] + #[inline(always)] + pub fn ch2_loc0(&self) -> CH2_LOC0_R { + CH2_LOC0_R::new((self.bits >> 6) & 0x03ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_LLP0") + .field("ch2_lms", &format_args!("{}", self.ch2_lms().bit())) + .field("ch2_loc0", &format_args!("{}", self.ch2_loc0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_lms(&mut self) -> CH2_LMS_W { + CH2_LMS_W::new(self, 0) + } + #[doc = "Bits 6:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_loc0(&mut self) -> CH2_LOC0_W { + CH2_LOC0_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_llp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_llp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_LLP0_SPEC; +impl crate::RegisterSpec for CH2_LLP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_llp0::R`](R) reader structure"] +impl crate::Readable for CH2_LLP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_llp0::W`](W) writer structure"] +impl crate::Writable for CH2_LLP0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_LLP0 to value 0"] +impl crate::Resettable for CH2_LLP0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_llp1.rs b/esp32p4/src/dma/ch2_llp1.rs new file mode 100644 index 0000000000..3a5fff8ea3 --- /dev/null +++ b/esp32p4/src/dma/ch2_llp1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH2_LLP1` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_LLP1` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_LOC1` reader - NA"] +pub type CH2_LOC1_R = crate::FieldReader; +#[doc = "Field `CH2_LOC1` writer - NA"] +pub type CH2_LOC1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch2_loc1(&self) -> CH2_LOC1_R { + CH2_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_LLP1") + .field("ch2_loc1", &format_args!("{}", self.ch2_loc1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_loc1(&mut self) -> CH2_LOC1_W { + CH2_LOC1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_llp1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_llp1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_LLP1_SPEC; +impl crate::RegisterSpec for CH2_LLP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_llp1::R`](R) reader structure"] +impl crate::Readable for CH2_LLP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_llp1::W`](W) writer structure"] +impl crate::Writable for CH2_LLP1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_LLP1 to value 0"] +impl crate::Resettable for CH2_LLP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_sar0.rs b/esp32p4/src/dma/ch2_sar0.rs new file mode 100644 index 0000000000..3ade0314a4 --- /dev/null +++ b/esp32p4/src/dma/ch2_sar0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH2_SAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_SAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_SAR0` reader - NA"] +pub type CH2_SAR0_R = crate::FieldReader; +#[doc = "Field `CH2_SAR0` writer - NA"] +pub type CH2_SAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch2_sar0(&self) -> CH2_SAR0_R { + CH2_SAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_SAR0") + .field("ch2_sar0", &format_args!("{}", self.ch2_sar0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_sar0(&mut self) -> CH2_SAR0_W { + CH2_SAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_sar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_sar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_SAR0_SPEC; +impl crate::RegisterSpec for CH2_SAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_sar0::R`](R) reader structure"] +impl crate::Readable for CH2_SAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_sar0::W`](W) writer structure"] +impl crate::Writable for CH2_SAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_SAR0 to value 0"] +impl crate::Resettable for CH2_SAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_sar1.rs b/esp32p4/src/dma/ch2_sar1.rs new file mode 100644 index 0000000000..ca3d71c922 --- /dev/null +++ b/esp32p4/src/dma/ch2_sar1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH2_SAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_SAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_SAR1` reader - NA"] +pub type CH2_SAR1_R = crate::FieldReader; +#[doc = "Field `CH2_SAR1` writer - NA"] +pub type CH2_SAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch2_sar1(&self) -> CH2_SAR1_R { + CH2_SAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_SAR1") + .field("ch2_sar1", &format_args!("{}", self.ch2_sar1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_sar1(&mut self) -> CH2_SAR1_W { + CH2_SAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_sar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_sar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_SAR1_SPEC; +impl crate::RegisterSpec for CH2_SAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_sar1::R`](R) reader structure"] +impl crate::Readable for CH2_SAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_sar1::W`](W) writer structure"] +impl crate::Writable for CH2_SAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_SAR1 to value 0"] +impl crate::Resettable for CH2_SAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_sstat0.rs b/esp32p4/src/dma/ch2_sstat0.rs new file mode 100644 index 0000000000..63555e0a76 --- /dev/null +++ b/esp32p4/src/dma/ch2_sstat0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `CH2_SSTAT0` reader"] +pub type R = crate::R; +#[doc = "Field `CH2_SSTAT` reader - NA"] +pub type CH2_SSTAT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch2_sstat(&self) -> CH2_SSTAT_R { + CH2_SSTAT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_SSTAT0") + .field("ch2_sstat", &format_args!("{}", self.ch2_sstat().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_sstat0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_SSTAT0_SPEC; +impl crate::RegisterSpec for CH2_SSTAT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_sstat0::R`](R) reader structure"] +impl crate::Readable for CH2_SSTAT0_SPEC {} +#[doc = "`reset()` method sets CH2_SSTAT0 to value 0"] +impl crate::Resettable for CH2_SSTAT0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_sstatar0.rs b/esp32p4/src/dma/ch2_sstatar0.rs new file mode 100644 index 0000000000..ce61881d35 --- /dev/null +++ b/esp32p4/src/dma/ch2_sstatar0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH2_SSTATAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_SSTATAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_SSTATAR0` reader - NA"] +pub type CH2_SSTATAR0_R = crate::FieldReader; +#[doc = "Field `CH2_SSTATAR0` writer - NA"] +pub type CH2_SSTATAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch2_sstatar0(&self) -> CH2_SSTATAR0_R { + CH2_SSTATAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_SSTATAR0") + .field( + "ch2_sstatar0", + &format_args!("{}", self.ch2_sstatar0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_sstatar0(&mut self) -> CH2_SSTATAR0_W { + CH2_SSTATAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_sstatar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_sstatar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_SSTATAR0_SPEC; +impl crate::RegisterSpec for CH2_SSTATAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_sstatar0::R`](R) reader structure"] +impl crate::Readable for CH2_SSTATAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_sstatar0::W`](W) writer structure"] +impl crate::Writable for CH2_SSTATAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_SSTATAR0 to value 0"] +impl crate::Resettable for CH2_SSTATAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_sstatar1.rs b/esp32p4/src/dma/ch2_sstatar1.rs new file mode 100644 index 0000000000..92ec66f6ae --- /dev/null +++ b/esp32p4/src/dma/ch2_sstatar1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH2_SSTATAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_SSTATAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_SSTATAR1` reader - NA"] +pub type CH2_SSTATAR1_R = crate::FieldReader; +#[doc = "Field `CH2_SSTATAR1` writer - NA"] +pub type CH2_SSTATAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch2_sstatar1(&self) -> CH2_SSTATAR1_R { + CH2_SSTATAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_SSTATAR1") + .field( + "ch2_sstatar1", + &format_args!("{}", self.ch2_sstatar1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_sstatar1(&mut self) -> CH2_SSTATAR1_W { + CH2_SSTATAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_sstatar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_sstatar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_SSTATAR1_SPEC; +impl crate::RegisterSpec for CH2_SSTATAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_sstatar1::R`](R) reader structure"] +impl crate::Readable for CH2_SSTATAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_sstatar1::W`](W) writer structure"] +impl crate::Writable for CH2_SSTATAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_SSTATAR1 to value 0"] +impl crate::Resettable for CH2_SSTATAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_status0.rs b/esp32p4/src/dma/ch2_status0.rs new file mode 100644 index 0000000000..dc58a66d36 --- /dev/null +++ b/esp32p4/src/dma/ch2_status0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CH2_STATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `CH2_CMPLTD_BLK_TFR_SIZE` reader - NA"] +pub type CH2_CMPLTD_BLK_TFR_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + pub fn ch2_cmpltd_blk_tfr_size(&self) -> CH2_CMPLTD_BLK_TFR_SIZE_R { + CH2_CMPLTD_BLK_TFR_SIZE_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_STATUS0") + .field( + "ch2_cmpltd_blk_tfr_size", + &format_args!("{}", self.ch2_cmpltd_blk_tfr_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_STATUS0_SPEC; +impl crate::RegisterSpec for CH2_STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_status0::R`](R) reader structure"] +impl crate::Readable for CH2_STATUS0_SPEC {} +#[doc = "`reset()` method sets CH2_STATUS0 to value 0"] +impl crate::Resettable for CH2_STATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_status1.rs b/esp32p4/src/dma/ch2_status1.rs new file mode 100644 index 0000000000..acfecbfc11 --- /dev/null +++ b/esp32p4/src/dma/ch2_status1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CH2_STATUS1` reader"] +pub type R = crate::R; +#[doc = "Field `CH2_DATA_LEFT_IN_FIFO` reader - NA"] +pub type CH2_DATA_LEFT_IN_FIFO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + pub fn ch2_data_left_in_fifo(&self) -> CH2_DATA_LEFT_IN_FIFO_R { + CH2_DATA_LEFT_IN_FIFO_R::new((self.bits & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_STATUS1") + .field( + "ch2_data_left_in_fifo", + &format_args!("{}", self.ch2_data_left_in_fifo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_status1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_STATUS1_SPEC; +impl crate::RegisterSpec for CH2_STATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_status1::R`](R) reader structure"] +impl crate::Readable for CH2_STATUS1_SPEC {} +#[doc = "`reset()` method sets CH2_STATUS1 to value 0"] +impl crate::Resettable for CH2_STATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_swhsdst0.rs b/esp32p4/src/dma/ch2_swhsdst0.rs new file mode 100644 index 0000000000..c371c35de9 --- /dev/null +++ b/esp32p4/src/dma/ch2_swhsdst0.rs @@ -0,0 +1,128 @@ +#[doc = "Register `CH2_SWHSDST0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_SWHSDST0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_SWHS_REQ_DST` reader - NA"] +pub type CH2_SWHS_REQ_DST_R = crate::BitReader; +#[doc = "Field `CH2_SWHS_REQ_DST` writer - NA"] +pub type CH2_SWHS_REQ_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SWHS_REQ_DST_WE` writer - NA"] +pub type CH2_SWHS_REQ_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SWHS_SGLREQ_DST` reader - NA"] +pub type CH2_SWHS_SGLREQ_DST_R = crate::BitReader; +#[doc = "Field `CH2_SWHS_SGLREQ_DST` writer - NA"] +pub type CH2_SWHS_SGLREQ_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SWHS_SGLREQ_DST_WE` writer - NA"] +pub type CH2_SWHS_SGLREQ_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SWHS_LST_DST` reader - NA"] +pub type CH2_SWHS_LST_DST_R = crate::BitReader; +#[doc = "Field `CH2_SWHS_LST_DST` writer - NA"] +pub type CH2_SWHS_LST_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SWHS_LST_DST_WE` writer - NA"] +pub type CH2_SWHS_LST_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch2_swhs_req_dst(&self) -> CH2_SWHS_REQ_DST_R { + CH2_SWHS_REQ_DST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch2_swhs_sglreq_dst(&self) -> CH2_SWHS_SGLREQ_DST_R { + CH2_SWHS_SGLREQ_DST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch2_swhs_lst_dst(&self) -> CH2_SWHS_LST_DST_R { + CH2_SWHS_LST_DST_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_SWHSDST0") + .field( + "ch2_swhs_req_dst", + &format_args!("{}", self.ch2_swhs_req_dst().bit()), + ) + .field( + "ch2_swhs_sglreq_dst", + &format_args!("{}", self.ch2_swhs_sglreq_dst().bit()), + ) + .field( + "ch2_swhs_lst_dst", + &format_args!("{}", self.ch2_swhs_lst_dst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_req_dst(&mut self) -> CH2_SWHS_REQ_DST_W { + CH2_SWHS_REQ_DST_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_req_dst_we(&mut self) -> CH2_SWHS_REQ_DST_WE_W { + CH2_SWHS_REQ_DST_WE_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_sglreq_dst(&mut self) -> CH2_SWHS_SGLREQ_DST_W { + CH2_SWHS_SGLREQ_DST_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_sglreq_dst_we(&mut self) -> CH2_SWHS_SGLREQ_DST_WE_W { + CH2_SWHS_SGLREQ_DST_WE_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_lst_dst(&mut self) -> CH2_SWHS_LST_DST_W { + CH2_SWHS_LST_DST_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_lst_dst_we(&mut self) -> CH2_SWHS_LST_DST_WE_W { + CH2_SWHS_LST_DST_WE_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_swhsdst0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_swhsdst0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_SWHSDST0_SPEC; +impl crate::RegisterSpec for CH2_SWHSDST0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_swhsdst0::R`](R) reader structure"] +impl crate::Readable for CH2_SWHSDST0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_swhsdst0::W`](W) writer structure"] +impl crate::Writable for CH2_SWHSDST0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_SWHSDST0 to value 0"] +impl crate::Resettable for CH2_SWHSDST0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch2_swhssrc0.rs b/esp32p4/src/dma/ch2_swhssrc0.rs new file mode 100644 index 0000000000..81e31bae90 --- /dev/null +++ b/esp32p4/src/dma/ch2_swhssrc0.rs @@ -0,0 +1,128 @@ +#[doc = "Register `CH2_SWHSSRC0` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_SWHSSRC0` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_SWHS_REQ_SRC` reader - NA"] +pub type CH2_SWHS_REQ_SRC_R = crate::BitReader; +#[doc = "Field `CH2_SWHS_REQ_SRC` writer - NA"] +pub type CH2_SWHS_REQ_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SWHS_REQ_SRC_WE` writer - NA"] +pub type CH2_SWHS_REQ_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SWHS_SGLREQ_SRC` reader - NA"] +pub type CH2_SWHS_SGLREQ_SRC_R = crate::BitReader; +#[doc = "Field `CH2_SWHS_SGLREQ_SRC` writer - NA"] +pub type CH2_SWHS_SGLREQ_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SWHS_SGLREQ_SRC_WE` writer - NA"] +pub type CH2_SWHS_SGLREQ_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SWHS_LST_SRC` reader - NA"] +pub type CH2_SWHS_LST_SRC_R = crate::BitReader; +#[doc = "Field `CH2_SWHS_LST_SRC` writer - NA"] +pub type CH2_SWHS_LST_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SWHS_LST_SRC_WE` writer - NA"] +pub type CH2_SWHS_LST_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch2_swhs_req_src(&self) -> CH2_SWHS_REQ_SRC_R { + CH2_SWHS_REQ_SRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch2_swhs_sglreq_src(&self) -> CH2_SWHS_SGLREQ_SRC_R { + CH2_SWHS_SGLREQ_SRC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch2_swhs_lst_src(&self) -> CH2_SWHS_LST_SRC_R { + CH2_SWHS_LST_SRC_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_SWHSSRC0") + .field( + "ch2_swhs_req_src", + &format_args!("{}", self.ch2_swhs_req_src().bit()), + ) + .field( + "ch2_swhs_sglreq_src", + &format_args!("{}", self.ch2_swhs_sglreq_src().bit()), + ) + .field( + "ch2_swhs_lst_src", + &format_args!("{}", self.ch2_swhs_lst_src().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_req_src(&mut self) -> CH2_SWHS_REQ_SRC_W { + CH2_SWHS_REQ_SRC_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_req_src_we(&mut self) -> CH2_SWHS_REQ_SRC_WE_W { + CH2_SWHS_REQ_SRC_WE_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_sglreq_src(&mut self) -> CH2_SWHS_SGLREQ_SRC_W { + CH2_SWHS_SGLREQ_SRC_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_sglreq_src_we(&mut self) -> CH2_SWHS_SGLREQ_SRC_WE_W { + CH2_SWHS_SGLREQ_SRC_WE_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_lst_src(&mut self) -> CH2_SWHS_LST_SRC_W { + CH2_SWHS_LST_SRC_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_swhs_lst_src_we(&mut self) -> CH2_SWHS_LST_SRC_WE_W { + CH2_SWHS_LST_SRC_WE_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_swhssrc0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_swhssrc0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_SWHSSRC0_SPEC; +impl crate::RegisterSpec for CH2_SWHSSRC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_swhssrc0::R`](R) reader structure"] +impl crate::Readable for CH2_SWHSSRC0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_swhssrc0::W`](W) writer structure"] +impl crate::Writable for CH2_SWHSSRC0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_SWHSSRC0 to value 0"] +impl crate::Resettable for CH2_SWHSSRC0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_axi_id0.rs b/esp32p4/src/dma/ch3_axi_id0.rs new file mode 100644 index 0000000000..14d02342ba --- /dev/null +++ b/esp32p4/src/dma/ch3_axi_id0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CH3_AXI_ID0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_AXI_ID0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_AXI_READ_ID_SUFFIX` reader - NA"] +pub type CH3_AXI_READ_ID_SUFFIX_R = crate::BitReader; +#[doc = "Field `CH3_AXI_READ_ID_SUFFIX` writer - NA"] +pub type CH3_AXI_READ_ID_SUFFIX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_AXI_WRITE_ID_SUFFIX` reader - NA"] +pub type CH3_AXI_WRITE_ID_SUFFIX_R = crate::BitReader; +#[doc = "Field `CH3_AXI_WRITE_ID_SUFFIX` writer - NA"] +pub type CH3_AXI_WRITE_ID_SUFFIX_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch3_axi_read_id_suffix(&self) -> CH3_AXI_READ_ID_SUFFIX_R { + CH3_AXI_READ_ID_SUFFIX_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch3_axi_write_id_suffix(&self) -> CH3_AXI_WRITE_ID_SUFFIX_R { + CH3_AXI_WRITE_ID_SUFFIX_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_AXI_ID0") + .field( + "ch3_axi_read_id_suffix", + &format_args!("{}", self.ch3_axi_read_id_suffix().bit()), + ) + .field( + "ch3_axi_write_id_suffix", + &format_args!("{}", self.ch3_axi_write_id_suffix().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_axi_read_id_suffix(&mut self) -> CH3_AXI_READ_ID_SUFFIX_W { + CH3_AXI_READ_ID_SUFFIX_W::new(self, 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_axi_write_id_suffix(&mut self) -> CH3_AXI_WRITE_ID_SUFFIX_W { + CH3_AXI_WRITE_ID_SUFFIX_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_axi_id0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_axi_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_AXI_ID0_SPEC; +impl crate::RegisterSpec for CH3_AXI_ID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_axi_id0::R`](R) reader structure"] +impl crate::Readable for CH3_AXI_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_axi_id0::W`](W) writer structure"] +impl crate::Writable for CH3_AXI_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_AXI_ID0 to value 0"] +impl crate::Resettable for CH3_AXI_ID0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_axi_qos0.rs b/esp32p4/src/dma/ch3_axi_qos0.rs new file mode 100644 index 0000000000..be8528868e --- /dev/null +++ b/esp32p4/src/dma/ch3_axi_qos0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CH3_AXI_QOS0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_AXI_QOS0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_AXI_AWQOS` reader - NA"] +pub type CH3_AXI_AWQOS_R = crate::FieldReader; +#[doc = "Field `CH3_AXI_AWQOS` writer - NA"] +pub type CH3_AXI_AWQOS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH3_AXI_ARQOS` reader - NA"] +pub type CH3_AXI_ARQOS_R = crate::FieldReader; +#[doc = "Field `CH3_AXI_ARQOS` writer - NA"] +pub type CH3_AXI_ARQOS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + pub fn ch3_axi_awqos(&self) -> CH3_AXI_AWQOS_R { + CH3_AXI_AWQOS_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - NA"] + #[inline(always)] + pub fn ch3_axi_arqos(&self) -> CH3_AXI_ARQOS_R { + CH3_AXI_ARQOS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_AXI_QOS0") + .field( + "ch3_axi_awqos", + &format_args!("{}", self.ch3_axi_awqos().bits()), + ) + .field( + "ch3_axi_arqos", + &format_args!("{}", self.ch3_axi_arqos().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_axi_awqos(&mut self) -> CH3_AXI_AWQOS_W { + CH3_AXI_AWQOS_W::new(self, 0) + } + #[doc = "Bits 4:7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_axi_arqos(&mut self) -> CH3_AXI_ARQOS_W { + CH3_AXI_ARQOS_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_axi_qos0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_axi_qos0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_AXI_QOS0_SPEC; +impl crate::RegisterSpec for CH3_AXI_QOS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_axi_qos0::R`](R) reader structure"] +impl crate::Readable for CH3_AXI_QOS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_axi_qos0::W`](W) writer structure"] +impl crate::Writable for CH3_AXI_QOS0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_AXI_QOS0 to value 0"] +impl crate::Resettable for CH3_AXI_QOS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_blk_tfr_resumereq0.rs b/esp32p4/src/dma/ch3_blk_tfr_resumereq0.rs new file mode 100644 index 0000000000..e265956b8c --- /dev/null +++ b/esp32p4/src/dma/ch3_blk_tfr_resumereq0.rs @@ -0,0 +1,44 @@ +#[doc = "Register `CH3_BLK_TFR_RESUMEREQ0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_BLK_TFR_RESUMEREQ` writer - NA"] +pub type CH3_BLK_TFR_RESUMEREQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_blk_tfr_resumereq( + &mut self, + ) -> CH3_BLK_TFR_RESUMEREQ_W { + CH3_BLK_TFR_RESUMEREQ_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_blk_tfr_resumereq0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_BLK_TFR_RESUMEREQ0_SPEC; +impl crate::RegisterSpec for CH3_BLK_TFR_RESUMEREQ0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch3_blk_tfr_resumereq0::W`](W) writer structure"] +impl crate::Writable for CH3_BLK_TFR_RESUMEREQ0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_BLK_TFR_RESUMEREQ0 to value 0"] +impl crate::Resettable for CH3_BLK_TFR_RESUMEREQ0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_block_ts0.rs b/esp32p4/src/dma/ch3_block_ts0.rs new file mode 100644 index 0000000000..c958101196 --- /dev/null +++ b/esp32p4/src/dma/ch3_block_ts0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH3_BLOCK_TS0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_BLOCK_TS0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_BLOCK_TS` reader - NA"] +pub type CH3_BLOCK_TS_R = crate::FieldReader; +#[doc = "Field `CH3_BLOCK_TS` writer - NA"] +pub type CH3_BLOCK_TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + pub fn ch3_block_ts(&self) -> CH3_BLOCK_TS_R { + CH3_BLOCK_TS_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_BLOCK_TS0") + .field( + "ch3_block_ts", + &format_args!("{}", self.ch3_block_ts().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_block_ts(&mut self) -> CH3_BLOCK_TS_W { + CH3_BLOCK_TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_block_ts0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_block_ts0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_BLOCK_TS0_SPEC; +impl crate::RegisterSpec for CH3_BLOCK_TS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_block_ts0::R`](R) reader structure"] +impl crate::Readable for CH3_BLOCK_TS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_block_ts0::W`](W) writer structure"] +impl crate::Writable for CH3_BLOCK_TS0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_BLOCK_TS0 to value 0"] +impl crate::Resettable for CH3_BLOCK_TS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_cfg0.rs b/esp32p4/src/dma/ch3_cfg0.rs new file mode 100644 index 0000000000..b088c96667 --- /dev/null +++ b/esp32p4/src/dma/ch3_cfg0.rs @@ -0,0 +1,101 @@ +#[doc = "Register `CH3_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_SRC_MULTBLK_TYPE` reader - NA"] +pub type CH3_SRC_MULTBLK_TYPE_R = crate::FieldReader; +#[doc = "Field `CH3_SRC_MULTBLK_TYPE` writer - NA"] +pub type CH3_SRC_MULTBLK_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH3_DST_MULTBLK_TYPE` reader - NA"] +pub type CH3_DST_MULTBLK_TYPE_R = crate::FieldReader; +#[doc = "Field `CH3_DST_MULTBLK_TYPE` writer - NA"] +pub type CH3_DST_MULTBLK_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH3_RD_UID` reader - NA"] +pub type CH3_RD_UID_R = crate::FieldReader; +#[doc = "Field `CH3_WR_UID` reader - NA"] +pub type CH3_WR_UID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn ch3_src_multblk_type(&self) -> CH3_SRC_MULTBLK_TYPE_R { + CH3_SRC_MULTBLK_TYPE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - NA"] + #[inline(always)] + pub fn ch3_dst_multblk_type(&self) -> CH3_DST_MULTBLK_TYPE_R { + CH3_DST_MULTBLK_TYPE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + pub fn ch3_rd_uid(&self) -> CH3_RD_UID_R { + CH3_RD_UID_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bits 25:28 - NA"] + #[inline(always)] + pub fn ch3_wr_uid(&self) -> CH3_WR_UID_R { + CH3_WR_UID_R::new(((self.bits >> 25) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_CFG0") + .field( + "ch3_src_multblk_type", + &format_args!("{}", self.ch3_src_multblk_type().bits()), + ) + .field( + "ch3_dst_multblk_type", + &format_args!("{}", self.ch3_dst_multblk_type().bits()), + ) + .field("ch3_rd_uid", &format_args!("{}", self.ch3_rd_uid().bits())) + .field("ch3_wr_uid", &format_args!("{}", self.ch3_wr_uid().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_src_multblk_type(&mut self) -> CH3_SRC_MULTBLK_TYPE_W { + CH3_SRC_MULTBLK_TYPE_W::new(self, 0) + } + #[doc = "Bits 2:3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dst_multblk_type(&mut self) -> CH3_DST_MULTBLK_TYPE_W { + CH3_DST_MULTBLK_TYPE_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_CFG0_SPEC; +impl crate::RegisterSpec for CH3_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_cfg0::R`](R) reader structure"] +impl crate::Readable for CH3_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_cfg0::W`](W) writer structure"] +impl crate::Writable for CH3_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_CFG0 to value 0"] +impl crate::Resettable for CH3_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_cfg1.rs b/esp32p4/src/dma/ch3_cfg1.rs new file mode 100644 index 0000000000..79f31ae95f --- /dev/null +++ b/esp32p4/src/dma/ch3_cfg1.rs @@ -0,0 +1,237 @@ +#[doc = "Register `CH3_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_TT_FC` reader - NA"] +pub type CH3_TT_FC_R = crate::FieldReader; +#[doc = "Field `CH3_TT_FC` writer - NA"] +pub type CH3_TT_FC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH3_HS_SEL_SRC` reader - NA"] +pub type CH3_HS_SEL_SRC_R = crate::BitReader; +#[doc = "Field `CH3_HS_SEL_SRC` writer - NA"] +pub type CH3_HS_SEL_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_HS_SEL_DST` reader - NA"] +pub type CH3_HS_SEL_DST_R = crate::BitReader; +#[doc = "Field `CH3_HS_SEL_DST` writer - NA"] +pub type CH3_HS_SEL_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SRC_HWHS_POL` reader - NA"] +pub type CH3_SRC_HWHS_POL_R = crate::BitReader; +#[doc = "Field `CH3_DST_HWHS_POL` reader - NA"] +pub type CH3_DST_HWHS_POL_R = crate::BitReader; +#[doc = "Field `CH3_SRC_PER` reader - NA"] +pub type CH3_SRC_PER_R = crate::FieldReader; +#[doc = "Field `CH3_SRC_PER` writer - NA"] +pub type CH3_SRC_PER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH3_DST_PER` reader - NA"] +pub type CH3_DST_PER_R = crate::FieldReader; +#[doc = "Field `CH3_DST_PER` writer - NA"] +pub type CH3_DST_PER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH3_CH_PRIOR` reader - NA"] +pub type CH3_CH_PRIOR_R = crate::FieldReader; +#[doc = "Field `CH3_CH_PRIOR` writer - NA"] +pub type CH3_CH_PRIOR_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH3_LOCK_CH` reader - NA"] +pub type CH3_LOCK_CH_R = crate::BitReader; +#[doc = "Field `CH3_LOCK_CH_L` reader - NA"] +pub type CH3_LOCK_CH_L_R = crate::FieldReader; +#[doc = "Field `CH3_SRC_OSR_LMT` reader - NA"] +pub type CH3_SRC_OSR_LMT_R = crate::FieldReader; +#[doc = "Field `CH3_SRC_OSR_LMT` writer - NA"] +pub type CH3_SRC_OSR_LMT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH3_DST_OSR_LMT` reader - NA"] +pub type CH3_DST_OSR_LMT_R = crate::FieldReader; +#[doc = "Field `CH3_DST_OSR_LMT` writer - NA"] +pub type CH3_DST_OSR_LMT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + pub fn ch3_tt_fc(&self) -> CH3_TT_FC_R { + CH3_TT_FC_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch3_hs_sel_src(&self) -> CH3_HS_SEL_SRC_R { + CH3_HS_SEL_SRC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch3_hs_sel_dst(&self) -> CH3_HS_SEL_DST_R { + CH3_HS_SEL_DST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch3_src_hwhs_pol(&self) -> CH3_SRC_HWHS_POL_R { + CH3_SRC_HWHS_POL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch3_dst_hwhs_pol(&self) -> CH3_DST_HWHS_POL_R { + CH3_DST_HWHS_POL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:8 - NA"] + #[inline(always)] + pub fn ch3_src_per(&self) -> CH3_SRC_PER_R { + CH3_SRC_PER_R::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 12:13 - NA"] + #[inline(always)] + pub fn ch3_dst_per(&self) -> CH3_DST_PER_R { + CH3_DST_PER_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 17:19 - NA"] + #[inline(always)] + pub fn ch3_ch_prior(&self) -> CH3_CH_PRIOR_R { + CH3_CH_PRIOR_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch3_lock_ch(&self) -> CH3_LOCK_CH_R { + CH3_LOCK_CH_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:22 - NA"] + #[inline(always)] + pub fn ch3_lock_ch_l(&self) -> CH3_LOCK_CH_L_R { + CH3_LOCK_CH_L_R::new(((self.bits >> 21) & 3) as u8) + } + #[doc = "Bits 23:26 - NA"] + #[inline(always)] + pub fn ch3_src_osr_lmt(&self) -> CH3_SRC_OSR_LMT_R { + CH3_SRC_OSR_LMT_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bits 27:30 - NA"] + #[inline(always)] + pub fn ch3_dst_osr_lmt(&self) -> CH3_DST_OSR_LMT_R { + CH3_DST_OSR_LMT_R::new(((self.bits >> 27) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_CFG1") + .field("ch3_tt_fc", &format_args!("{}", self.ch3_tt_fc().bits())) + .field( + "ch3_hs_sel_src", + &format_args!("{}", self.ch3_hs_sel_src().bit()), + ) + .field( + "ch3_hs_sel_dst", + &format_args!("{}", self.ch3_hs_sel_dst().bit()), + ) + .field( + "ch3_src_hwhs_pol", + &format_args!("{}", self.ch3_src_hwhs_pol().bit()), + ) + .field( + "ch3_dst_hwhs_pol", + &format_args!("{}", self.ch3_dst_hwhs_pol().bit()), + ) + .field( + "ch3_src_per", + &format_args!("{}", self.ch3_src_per().bits()), + ) + .field( + "ch3_dst_per", + &format_args!("{}", self.ch3_dst_per().bits()), + ) + .field( + "ch3_ch_prior", + &format_args!("{}", self.ch3_ch_prior().bits()), + ) + .field("ch3_lock_ch", &format_args!("{}", self.ch3_lock_ch().bit())) + .field( + "ch3_lock_ch_l", + &format_args!("{}", self.ch3_lock_ch_l().bits()), + ) + .field( + "ch3_src_osr_lmt", + &format_args!("{}", self.ch3_src_osr_lmt().bits()), + ) + .field( + "ch3_dst_osr_lmt", + &format_args!("{}", self.ch3_dst_osr_lmt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_tt_fc(&mut self) -> CH3_TT_FC_W { + CH3_TT_FC_W::new(self, 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_hs_sel_src(&mut self) -> CH3_HS_SEL_SRC_W { + CH3_HS_SEL_SRC_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_hs_sel_dst(&mut self) -> CH3_HS_SEL_DST_W { + CH3_HS_SEL_DST_W::new(self, 4) + } + #[doc = "Bits 7:8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_src_per(&mut self) -> CH3_SRC_PER_W { + CH3_SRC_PER_W::new(self, 7) + } + #[doc = "Bits 12:13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dst_per(&mut self) -> CH3_DST_PER_W { + CH3_DST_PER_W::new(self, 12) + } + #[doc = "Bits 17:19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_ch_prior(&mut self) -> CH3_CH_PRIOR_W { + CH3_CH_PRIOR_W::new(self, 17) + } + #[doc = "Bits 23:26 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_src_osr_lmt(&mut self) -> CH3_SRC_OSR_LMT_W { + CH3_SRC_OSR_LMT_W::new(self, 23) + } + #[doc = "Bits 27:30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dst_osr_lmt(&mut self) -> CH3_DST_OSR_LMT_W { + CH3_DST_OSR_LMT_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_CFG1_SPEC; +impl crate::RegisterSpec for CH3_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_cfg1::R`](R) reader structure"] +impl crate::Readable for CH3_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_cfg1::W`](W) writer structure"] +impl crate::Writable for CH3_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_CFG1 to value 0x0002_001b"] +impl crate::Resettable for CH3_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_001b; +} diff --git a/esp32p4/src/dma/ch3_ctl0.rs b/esp32p4/src/dma/ch3_ctl0.rs new file mode 100644 index 0000000000..d74f7799f3 --- /dev/null +++ b/esp32p4/src/dma/ch3_ctl0.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CH3_CTL0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_CTL0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_SMS` reader - NA"] +pub type CH3_SMS_R = crate::BitReader; +#[doc = "Field `CH3_SMS` writer - NA"] +pub type CH3_SMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_DMS` reader - NA"] +pub type CH3_DMS_R = crate::BitReader; +#[doc = "Field `CH3_DMS` writer - NA"] +pub type CH3_DMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SINC` reader - NA"] +pub type CH3_SINC_R = crate::BitReader; +#[doc = "Field `CH3_SINC` writer - NA"] +pub type CH3_SINC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_DINC` reader - NA"] +pub type CH3_DINC_R = crate::BitReader; +#[doc = "Field `CH3_DINC` writer - NA"] +pub type CH3_DINC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SRC_TR_WIDTH` reader - NA"] +pub type CH3_SRC_TR_WIDTH_R = crate::FieldReader; +#[doc = "Field `CH3_SRC_TR_WIDTH` writer - NA"] +pub type CH3_SRC_TR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH3_DST_TR_WIDTH` reader - NA"] +pub type CH3_DST_TR_WIDTH_R = crate::FieldReader; +#[doc = "Field `CH3_DST_TR_WIDTH` writer - NA"] +pub type CH3_DST_TR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH3_SRC_MSIZE` reader - NA"] +pub type CH3_SRC_MSIZE_R = crate::FieldReader; +#[doc = "Field `CH3_SRC_MSIZE` writer - NA"] +pub type CH3_SRC_MSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH3_DST_MSIZE` reader - NA"] +pub type CH3_DST_MSIZE_R = crate::FieldReader; +#[doc = "Field `CH3_DST_MSIZE` writer - NA"] +pub type CH3_DST_MSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH3_AR_CACHE` reader - NA"] +pub type CH3_AR_CACHE_R = crate::FieldReader; +#[doc = "Field `CH3_AR_CACHE` writer - NA"] +pub type CH3_AR_CACHE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH3_AW_CACHE` reader - NA"] +pub type CH3_AW_CACHE_R = crate::FieldReader; +#[doc = "Field `CH3_AW_CACHE` writer - NA"] +pub type CH3_AW_CACHE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH3_NONPOSTED_LASTWRITE_EN` reader - NA"] +pub type CH3_NONPOSTED_LASTWRITE_EN_R = crate::BitReader; +#[doc = "Field `CH3_NONPOSTED_LASTWRITE_EN` writer - NA"] +pub type CH3_NONPOSTED_LASTWRITE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch3_sms(&self) -> CH3_SMS_R { + CH3_SMS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch3_dms(&self) -> CH3_DMS_R { + CH3_DMS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch3_sinc(&self) -> CH3_SINC_R { + CH3_SINC_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch3_dinc(&self) -> CH3_DINC_R { + CH3_DINC_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - NA"] + #[inline(always)] + pub fn ch3_src_tr_width(&self) -> CH3_SRC_TR_WIDTH_R { + CH3_SRC_TR_WIDTH_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 11:13 - NA"] + #[inline(always)] + pub fn ch3_dst_tr_width(&self) -> CH3_DST_TR_WIDTH_R { + CH3_DST_TR_WIDTH_R::new(((self.bits >> 11) & 7) as u8) + } + #[doc = "Bits 14:17 - NA"] + #[inline(always)] + pub fn ch3_src_msize(&self) -> CH3_SRC_MSIZE_R { + CH3_SRC_MSIZE_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + pub fn ch3_dst_msize(&self) -> CH3_DST_MSIZE_R { + CH3_DST_MSIZE_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bits 22:25 - NA"] + #[inline(always)] + pub fn ch3_ar_cache(&self) -> CH3_AR_CACHE_R { + CH3_AR_CACHE_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:29 - NA"] + #[inline(always)] + pub fn ch3_aw_cache(&self) -> CH3_AW_CACHE_R { + CH3_AW_CACHE_R::new(((self.bits >> 26) & 0x0f) as u8) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch3_nonposted_lastwrite_en(&self) -> CH3_NONPOSTED_LASTWRITE_EN_R { + CH3_NONPOSTED_LASTWRITE_EN_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_CTL0") + .field("ch3_sms", &format_args!("{}", self.ch3_sms().bit())) + .field("ch3_dms", &format_args!("{}", self.ch3_dms().bit())) + .field("ch3_sinc", &format_args!("{}", self.ch3_sinc().bit())) + .field("ch3_dinc", &format_args!("{}", self.ch3_dinc().bit())) + .field( + "ch3_src_tr_width", + &format_args!("{}", self.ch3_src_tr_width().bits()), + ) + .field( + "ch3_dst_tr_width", + &format_args!("{}", self.ch3_dst_tr_width().bits()), + ) + .field( + "ch3_src_msize", + &format_args!("{}", self.ch3_src_msize().bits()), + ) + .field( + "ch3_dst_msize", + &format_args!("{}", self.ch3_dst_msize().bits()), + ) + .field( + "ch3_ar_cache", + &format_args!("{}", self.ch3_ar_cache().bits()), + ) + .field( + "ch3_aw_cache", + &format_args!("{}", self.ch3_aw_cache().bits()), + ) + .field( + "ch3_nonposted_lastwrite_en", + &format_args!("{}", self.ch3_nonposted_lastwrite_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_sms(&mut self) -> CH3_SMS_W { + CH3_SMS_W::new(self, 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dms(&mut self) -> CH3_DMS_W { + CH3_DMS_W::new(self, 2) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_sinc(&mut self) -> CH3_SINC_W { + CH3_SINC_W::new(self, 4) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dinc(&mut self) -> CH3_DINC_W { + CH3_DINC_W::new(self, 6) + } + #[doc = "Bits 8:10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_src_tr_width(&mut self) -> CH3_SRC_TR_WIDTH_W { + CH3_SRC_TR_WIDTH_W::new(self, 8) + } + #[doc = "Bits 11:13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dst_tr_width(&mut self) -> CH3_DST_TR_WIDTH_W { + CH3_DST_TR_WIDTH_W::new(self, 11) + } + #[doc = "Bits 14:17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_src_msize(&mut self) -> CH3_SRC_MSIZE_W { + CH3_SRC_MSIZE_W::new(self, 14) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dst_msize(&mut self) -> CH3_DST_MSIZE_W { + CH3_DST_MSIZE_W::new(self, 18) + } + #[doc = "Bits 22:25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_ar_cache(&mut self) -> CH3_AR_CACHE_W { + CH3_AR_CACHE_W::new(self, 22) + } + #[doc = "Bits 26:29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_aw_cache(&mut self) -> CH3_AW_CACHE_W { + CH3_AW_CACHE_W::new(self, 26) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_nonposted_lastwrite_en(&mut self) -> CH3_NONPOSTED_LASTWRITE_EN_W { + CH3_NONPOSTED_LASTWRITE_EN_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_CTL0_SPEC; +impl crate::RegisterSpec for CH3_CTL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_ctl0::R`](R) reader structure"] +impl crate::Readable for CH3_CTL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_ctl0::W`](W) writer structure"] +impl crate::Writable for CH3_CTL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_CTL0 to value 0x1200"] +impl crate::Resettable for CH3_CTL0_SPEC { + const RESET_VALUE: Self::Ux = 0x1200; +} diff --git a/esp32p4/src/dma/ch3_ctl1.rs b/esp32p4/src/dma/ch3_ctl1.rs new file mode 100644 index 0000000000..73aa7e413d --- /dev/null +++ b/esp32p4/src/dma/ch3_ctl1.rs @@ -0,0 +1,250 @@ +#[doc = "Register `CH3_CTL1` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_CTL1` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_AR_PROT` reader - NA"] +pub type CH3_AR_PROT_R = crate::FieldReader; +#[doc = "Field `CH3_AR_PROT` writer - NA"] +pub type CH3_AR_PROT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH3_AW_PROT` reader - NA"] +pub type CH3_AW_PROT_R = crate::FieldReader; +#[doc = "Field `CH3_AW_PROT` writer - NA"] +pub type CH3_AW_PROT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH3_ARLEN_EN` reader - NA"] +pub type CH3_ARLEN_EN_R = crate::BitReader; +#[doc = "Field `CH3_ARLEN_EN` writer - NA"] +pub type CH3_ARLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ARLEN` reader - NA"] +pub type CH3_ARLEN_R = crate::FieldReader; +#[doc = "Field `CH3_ARLEN` writer - NA"] +pub type CH3_ARLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CH3_AWLEN_EN` reader - NA"] +pub type CH3_AWLEN_EN_R = crate::BitReader; +#[doc = "Field `CH3_AWLEN_EN` writer - NA"] +pub type CH3_AWLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_AWLEN` reader - NA"] +pub type CH3_AWLEN_R = crate::FieldReader; +#[doc = "Field `CH3_AWLEN` writer - NA"] +pub type CH3_AWLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CH3_SRC_STAT_EN` reader - NA"] +pub type CH3_SRC_STAT_EN_R = crate::BitReader; +#[doc = "Field `CH3_SRC_STAT_EN` writer - NA"] +pub type CH3_SRC_STAT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_DST_STAT_EN` reader - NA"] +pub type CH3_DST_STAT_EN_R = crate::BitReader; +#[doc = "Field `CH3_DST_STAT_EN` writer - NA"] +pub type CH3_DST_STAT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_IOC_BLKTFR` reader - NA"] +pub type CH3_IOC_BLKTFR_R = crate::BitReader; +#[doc = "Field `CH3_IOC_BLKTFR` writer - NA"] +pub type CH3_IOC_BLKTFR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SHADOWREG_OR_LLI_LAST` reader - NA"] +pub type CH3_SHADOWREG_OR_LLI_LAST_R = crate::BitReader; +#[doc = "Field `CH3_SHADOWREG_OR_LLI_LAST` writer - NA"] +pub type CH3_SHADOWREG_OR_LLI_LAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SHADOWREG_OR_LLI_VALID` reader - NA"] +pub type CH3_SHADOWREG_OR_LLI_VALID_R = crate::BitReader; +#[doc = "Field `CH3_SHADOWREG_OR_LLI_VALID` writer - NA"] +pub type CH3_SHADOWREG_OR_LLI_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + pub fn ch3_ar_prot(&self) -> CH3_AR_PROT_R { + CH3_AR_PROT_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - NA"] + #[inline(always)] + pub fn ch3_aw_prot(&self) -> CH3_AW_PROT_R { + CH3_AW_PROT_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch3_arlen_en(&self) -> CH3_ARLEN_EN_R { + CH3_ARLEN_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:14 - NA"] + #[inline(always)] + pub fn ch3_arlen(&self) -> CH3_ARLEN_R { + CH3_ARLEN_R::new(((self.bits >> 7) & 0xff) as u8) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn ch3_awlen_en(&self) -> CH3_AWLEN_EN_R { + CH3_AWLEN_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn ch3_awlen(&self) -> CH3_AWLEN_R { + CH3_AWLEN_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + pub fn ch3_src_stat_en(&self) -> CH3_SRC_STAT_EN_R { + CH3_SRC_STAT_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch3_dst_stat_en(&self) -> CH3_DST_STAT_EN_R { + CH3_DST_STAT_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - NA"] + #[inline(always)] + pub fn ch3_ioc_blktfr(&self) -> CH3_IOC_BLKTFR_R { + CH3_IOC_BLKTFR_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch3_shadowreg_or_lli_last(&self) -> CH3_SHADOWREG_OR_LLI_LAST_R { + CH3_SHADOWREG_OR_LLI_LAST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch3_shadowreg_or_lli_valid(&self) -> CH3_SHADOWREG_OR_LLI_VALID_R { + CH3_SHADOWREG_OR_LLI_VALID_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_CTL1") + .field( + "ch3_ar_prot", + &format_args!("{}", self.ch3_ar_prot().bits()), + ) + .field( + "ch3_aw_prot", + &format_args!("{}", self.ch3_aw_prot().bits()), + ) + .field( + "ch3_arlen_en", + &format_args!("{}", self.ch3_arlen_en().bit()), + ) + .field("ch3_arlen", &format_args!("{}", self.ch3_arlen().bits())) + .field( + "ch3_awlen_en", + &format_args!("{}", self.ch3_awlen_en().bit()), + ) + .field("ch3_awlen", &format_args!("{}", self.ch3_awlen().bits())) + .field( + "ch3_src_stat_en", + &format_args!("{}", self.ch3_src_stat_en().bit()), + ) + .field( + "ch3_dst_stat_en", + &format_args!("{}", self.ch3_dst_stat_en().bit()), + ) + .field( + "ch3_ioc_blktfr", + &format_args!("{}", self.ch3_ioc_blktfr().bit()), + ) + .field( + "ch3_shadowreg_or_lli_last", + &format_args!("{}", self.ch3_shadowreg_or_lli_last().bit()), + ) + .field( + "ch3_shadowreg_or_lli_valid", + &format_args!("{}", self.ch3_shadowreg_or_lli_valid().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_ar_prot(&mut self) -> CH3_AR_PROT_W { + CH3_AR_PROT_W::new(self, 0) + } + #[doc = "Bits 3:5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_aw_prot(&mut self) -> CH3_AW_PROT_W { + CH3_AW_PROT_W::new(self, 3) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_arlen_en(&mut self) -> CH3_ARLEN_EN_W { + CH3_ARLEN_EN_W::new(self, 6) + } + #[doc = "Bits 7:14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_arlen(&mut self) -> CH3_ARLEN_W { + CH3_ARLEN_W::new(self, 7) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_awlen_en(&mut self) -> CH3_AWLEN_EN_W { + CH3_AWLEN_EN_W::new(self, 15) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_awlen(&mut self) -> CH3_AWLEN_W { + CH3_AWLEN_W::new(self, 16) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_src_stat_en(&mut self) -> CH3_SRC_STAT_EN_W { + CH3_SRC_STAT_EN_W::new(self, 24) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dst_stat_en(&mut self) -> CH3_DST_STAT_EN_W { + CH3_DST_STAT_EN_W::new(self, 25) + } + #[doc = "Bit 26 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_ioc_blktfr(&mut self) -> CH3_IOC_BLKTFR_W { + CH3_IOC_BLKTFR_W::new(self, 26) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_shadowreg_or_lli_last(&mut self) -> CH3_SHADOWREG_OR_LLI_LAST_W { + CH3_SHADOWREG_OR_LLI_LAST_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_shadowreg_or_lli_valid(&mut self) -> CH3_SHADOWREG_OR_LLI_VALID_W { + CH3_SHADOWREG_OR_LLI_VALID_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_ctl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_CTL1_SPEC; +impl crate::RegisterSpec for CH3_CTL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_ctl1::R`](R) reader structure"] +impl crate::Readable for CH3_CTL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_ctl1::W`](W) writer structure"] +impl crate::Writable for CH3_CTL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_CTL1 to value 0"] +impl crate::Resettable for CH3_CTL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_dar0.rs b/esp32p4/src/dma/ch3_dar0.rs new file mode 100644 index 0000000000..40c03d95fd --- /dev/null +++ b/esp32p4/src/dma/ch3_dar0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH3_DAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_DAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_DAR0` reader - NA"] +pub type CH3_DAR0_R = crate::FieldReader; +#[doc = "Field `CH3_DAR0` writer - NA"] +pub type CH3_DAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch3_dar0(&self) -> CH3_DAR0_R { + CH3_DAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_DAR0") + .field("ch3_dar0", &format_args!("{}", self.ch3_dar0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dar0(&mut self) -> CH3_DAR0_W { + CH3_DAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_dar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_DAR0_SPEC; +impl crate::RegisterSpec for CH3_DAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_dar0::R`](R) reader structure"] +impl crate::Readable for CH3_DAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_dar0::W`](W) writer structure"] +impl crate::Writable for CH3_DAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_DAR0 to value 0"] +impl crate::Resettable for CH3_DAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_dar1.rs b/esp32p4/src/dma/ch3_dar1.rs new file mode 100644 index 0000000000..0aef88fd89 --- /dev/null +++ b/esp32p4/src/dma/ch3_dar1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH3_DAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_DAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_DAR1` reader - NA"] +pub type CH3_DAR1_R = crate::FieldReader; +#[doc = "Field `CH3_DAR1` writer - NA"] +pub type CH3_DAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch3_dar1(&self) -> CH3_DAR1_R { + CH3_DAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_DAR1") + .field("ch3_dar1", &format_args!("{}", self.ch3_dar1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dar1(&mut self) -> CH3_DAR1_W { + CH3_DAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_dar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_DAR1_SPEC; +impl crate::RegisterSpec for CH3_DAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_dar1::R`](R) reader structure"] +impl crate::Readable for CH3_DAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_dar1::W`](W) writer structure"] +impl crate::Writable for CH3_DAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_DAR1 to value 0"] +impl crate::Resettable for CH3_DAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_dstat0.rs b/esp32p4/src/dma/ch3_dstat0.rs new file mode 100644 index 0000000000..b70d1b39a9 --- /dev/null +++ b/esp32p4/src/dma/ch3_dstat0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `CH3_DSTAT0` reader"] +pub type R = crate::R; +#[doc = "Field `CH3_DSTAT` reader - NA"] +pub type CH3_DSTAT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch3_dstat(&self) -> CH3_DSTAT_R { + CH3_DSTAT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_DSTAT0") + .field("ch3_dstat", &format_args!("{}", self.ch3_dstat().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_dstat0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_DSTAT0_SPEC; +impl crate::RegisterSpec for CH3_DSTAT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_dstat0::R`](R) reader structure"] +impl crate::Readable for CH3_DSTAT0_SPEC {} +#[doc = "`reset()` method sets CH3_DSTAT0 to value 0"] +impl crate::Resettable for CH3_DSTAT0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_dstatar0.rs b/esp32p4/src/dma/ch3_dstatar0.rs new file mode 100644 index 0000000000..b29e11b065 --- /dev/null +++ b/esp32p4/src/dma/ch3_dstatar0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH3_DSTATAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_DSTATAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_DSTATAR0` reader - NA"] +pub type CH3_DSTATAR0_R = crate::FieldReader; +#[doc = "Field `CH3_DSTATAR0` writer - NA"] +pub type CH3_DSTATAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch3_dstatar0(&self) -> CH3_DSTATAR0_R { + CH3_DSTATAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_DSTATAR0") + .field( + "ch3_dstatar0", + &format_args!("{}", self.ch3_dstatar0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dstatar0(&mut self) -> CH3_DSTATAR0_W { + CH3_DSTATAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_dstatar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dstatar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_DSTATAR0_SPEC; +impl crate::RegisterSpec for CH3_DSTATAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_dstatar0::R`](R) reader structure"] +impl crate::Readable for CH3_DSTATAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_dstatar0::W`](W) writer structure"] +impl crate::Writable for CH3_DSTATAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_DSTATAR0 to value 0"] +impl crate::Resettable for CH3_DSTATAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_dstatar1.rs b/esp32p4/src/dma/ch3_dstatar1.rs new file mode 100644 index 0000000000..eb67e3fcd1 --- /dev/null +++ b/esp32p4/src/dma/ch3_dstatar1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH3_DSTATAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_DSTATAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_DSTATAR1` reader - NA"] +pub type CH3_DSTATAR1_R = crate::FieldReader; +#[doc = "Field `CH3_DSTATAR1` writer - NA"] +pub type CH3_DSTATAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch3_dstatar1(&self) -> CH3_DSTATAR1_R { + CH3_DSTATAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_DSTATAR1") + .field( + "ch3_dstatar1", + &format_args!("{}", self.ch3_dstatar1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_dstatar1(&mut self) -> CH3_DSTATAR1_W { + CH3_DSTATAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_dstatar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_dstatar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_DSTATAR1_SPEC; +impl crate::RegisterSpec for CH3_DSTATAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_dstatar1::R`](R) reader structure"] +impl crate::Readable for CH3_DSTATAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_dstatar1::W`](W) writer structure"] +impl crate::Writable for CH3_DSTATAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_DSTATAR1 to value 0"] +impl crate::Resettable for CH3_DSTATAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_intclear0.rs b/esp32p4/src/dma/ch3_intclear0.rs new file mode 100644 index 0000000000..3e8bc26236 --- /dev/null +++ b/esp32p4/src/dma/ch3_intclear0.rs @@ -0,0 +1,294 @@ +#[doc = "Register `CH3_INTCLEAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT` writer - NA"] +pub type CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_DMA_TFR_DONE_INTSTAT` writer - NA"] +pub type CH3_CLEAR_DMA_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SRC_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_DST_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH3_CLEAR_DST_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SRC_DEC_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SRC_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_DST_DEC_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_DST_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SRC_SLV_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SRC_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_DST_SLV_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_DST_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT` writer - NA"] +pub type CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT` writer - NA"] +pub type CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_CH_SUSPENDED_INTSTAT` writer - NA"] +pub type CH3_CLEAR_CH_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_CH_DISABLED_INTSTAT` writer - NA"] +pub type CH3_CLEAR_CH_DISABLED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_CH_ABORTED_INTSTAT` writer - NA"] +pub type CH3_CLEAR_CH_ABORTED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_block_tfr_done_intstat( + &mut self, + ) -> CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_W { + CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_dma_tfr_done_intstat( + &mut self, + ) -> CH3_CLEAR_DMA_TFR_DONE_INTSTAT_W { + CH3_CLEAR_DMA_TFR_DONE_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_src_transcomp_intstat( + &mut self, + ) -> CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_W { + CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_dst_transcomp_intstat( + &mut self, + ) -> CH3_CLEAR_DST_TRANSCOMP_INTSTAT_W { + CH3_CLEAR_DST_TRANSCOMP_INTSTAT_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_src_dec_err_intstat( + &mut self, + ) -> CH3_CLEAR_SRC_DEC_ERR_INTSTAT_W { + CH3_CLEAR_SRC_DEC_ERR_INTSTAT_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_dst_dec_err_intstat( + &mut self, + ) -> CH3_CLEAR_DST_DEC_ERR_INTSTAT_W { + CH3_CLEAR_DST_DEC_ERR_INTSTAT_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_src_slv_err_intstat( + &mut self, + ) -> CH3_CLEAR_SRC_SLV_ERR_INTSTAT_W { + CH3_CLEAR_SRC_SLV_ERR_INTSTAT_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_dst_slv_err_intstat( + &mut self, + ) -> CH3_CLEAR_DST_SLV_ERR_INTSTAT_W { + CH3_CLEAR_DST_SLV_ERR_INTSTAT_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_lli_rd_dec_err_intstat( + &mut self, + ) -> CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W { + CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_lli_wr_dec_err_intstat( + &mut self, + ) -> CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W { + CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_lli_rd_slv_err_intstat( + &mut self, + ) -> CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W { + CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_lli_wr_slv_err_intstat( + &mut self, + ) -> CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W { + CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_shadowreg_or_lli_invalid_err_intstat( + &mut self, + ) -> CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W { + CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_slvif_multiblktype_err_intstat( + &mut self, + ) -> CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W { + CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_slvif_dec_err_intstat( + &mut self, + ) -> CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_W { + CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_slvif_wr2ro_err_intstat( + &mut self, + ) -> CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W { + CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_slvif_rd2rwo_err_intstat( + &mut self, + ) -> CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W { + CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_slvif_wronchen_err_intstat( + &mut self, + ) -> CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W { + CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_slvif_shadowreg_wron_valid_err_intstat( + &mut self, + ) -> CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W { + CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_slvif_wronhold_err_intstat( + &mut self, + ) -> CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W { + CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W::new(self, 21) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_slvif_wrparity_err_intstat( + &mut self, + ) -> CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W { + CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W::new(self, 25) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_ch_lock_cleared_intstat( + &mut self, + ) -> CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_W { + CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_ch_src_suspended_intstat( + &mut self, + ) -> CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W { + CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_ch_suspended_intstat( + &mut self, + ) -> CH3_CLEAR_CH_SUSPENDED_INTSTAT_W { + CH3_CLEAR_CH_SUSPENDED_INTSTAT_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_ch_disabled_intstat( + &mut self, + ) -> CH3_CLEAR_CH_DISABLED_INTSTAT_W { + CH3_CLEAR_CH_DISABLED_INTSTAT_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_ch_aborted_intstat( + &mut self, + ) -> CH3_CLEAR_CH_ABORTED_INTSTAT_W { + CH3_CLEAR_CH_ABORTED_INTSTAT_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_intclear0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_INTCLEAR0_SPEC; +impl crate::RegisterSpec for CH3_INTCLEAR0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch3_intclear0::W`](W) writer structure"] +impl crate::Writable for CH3_INTCLEAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_INTCLEAR0 to value 0"] +impl crate::Resettable for CH3_INTCLEAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_intclear1.rs b/esp32p4/src/dma/ch3_intclear1.rs new file mode 100644 index 0000000000..2792a8c4cc --- /dev/null +++ b/esp32p4/src/dma/ch3_intclear1.rs @@ -0,0 +1,74 @@ +#[doc = "Register `CH3_INTCLEAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` writer - NA"] +pub type CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_ecc_prot_chmem_correrr_intstat( + &mut self, + ) -> CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W { + CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_ecc_prot_chmem_uncorrerr_intstat( + &mut self, + ) -> CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W { + CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_ecc_prot_uidmem_correrr_intstat( + &mut self, + ) -> CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W { + CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_clear_ecc_prot_uidmem_uncorrerr_intstat( + &mut self, + ) -> CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W { + CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_intclear1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_INTCLEAR1_SPEC; +impl crate::RegisterSpec for CH3_INTCLEAR1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch3_intclear1::W`](W) writer structure"] +impl crate::Writable for CH3_INTCLEAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_INTCLEAR1 to value 0"] +impl crate::Resettable for CH3_INTCLEAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_intsignal_enable0.rs b/esp32p4/src/dma/ch3_intsignal_enable0.rs new file mode 100644 index 0000000000..7a771ca562 --- /dev/null +++ b/esp32p4/src/dma/ch3_intsignal_enable0.rs @@ -0,0 +1,606 @@ +#[doc = "Register `CH3_INTSIGNAL_ENABLE0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_INTSIGNAL_ENABLE0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_DST_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_DST_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_DST_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_DST_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_CH_SUSPENDED_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_SUSPENDED_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_CH_DISABLED_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_CH_DISABLED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_DISABLED_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_CH_DISABLED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_CH_ABORTED_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_CH_ABORTED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_ABORTED_INTSIGNAL` writer - NA"] +pub type CH3_ENABLE_CH_ABORTED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch3_enable_block_tfr_done_intsignal(&self) -> CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R { + CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch3_enable_dma_tfr_done_intsignal(&self) -> CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_R { + CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch3_enable_src_transcomp_intsignal(&self) -> CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R { + CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch3_enable_dst_transcomp_intsignal(&self) -> CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_R { + CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch3_enable_src_dec_err_intsignal(&self) -> CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_R { + CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch3_enable_dst_dec_err_intsignal(&self) -> CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_R { + CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch3_enable_src_slv_err_intsignal(&self) -> CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_R { + CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch3_enable_dst_slv_err_intsignal(&self) -> CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_R { + CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch3_enable_lli_rd_dec_err_intsignal(&self) -> CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R { + CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch3_enable_lli_wr_dec_err_intsignal(&self) -> CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R { + CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch3_enable_lli_rd_slv_err_intsignal(&self) -> CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R { + CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch3_enable_lli_wr_slv_err_intsignal(&self) -> CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R { + CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch3_enable_shadowreg_or_lli_invalid_err_intsignal( + &self, + ) -> CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R { + CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_multiblktype_err_intsignal( + &self, + ) -> CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R { + CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_dec_err_intsignal(&self) -> CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R { + CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_wr2ro_err_intsignal(&self) -> CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R { + CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_rd2rwo_err_intsignal(&self) -> CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R { + CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_wronchen_err_intsignal( + &self, + ) -> CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R { + CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_shadowreg_wron_valid_err_intsignal( + &self, + ) -> CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R { + CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_wronhold_err_intsignal( + &self, + ) -> CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R { + CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_wrparity_err_intsignal( + &self, + ) -> CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R { + CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch3_enable_ch_lock_cleared_intsignal(&self) -> CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R { + CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch3_enable_ch_src_suspended_intsignal(&self) -> CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R { + CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch3_enable_ch_suspended_intsignal(&self) -> CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_R { + CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch3_enable_ch_disabled_intsignal(&self) -> CH3_ENABLE_CH_DISABLED_INTSIGNAL_R { + CH3_ENABLE_CH_DISABLED_INTSIGNAL_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch3_enable_ch_aborted_intsignal(&self) -> CH3_ENABLE_CH_ABORTED_INTSIGNAL_R { + CH3_ENABLE_CH_ABORTED_INTSIGNAL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_INTSIGNAL_ENABLE0") + .field( + "ch3_enable_block_tfr_done_intsignal", + &format_args!("{}", self.ch3_enable_block_tfr_done_intsignal().bit()), + ) + .field( + "ch3_enable_dma_tfr_done_intsignal", + &format_args!("{}", self.ch3_enable_dma_tfr_done_intsignal().bit()), + ) + .field( + "ch3_enable_src_transcomp_intsignal", + &format_args!("{}", self.ch3_enable_src_transcomp_intsignal().bit()), + ) + .field( + "ch3_enable_dst_transcomp_intsignal", + &format_args!("{}", self.ch3_enable_dst_transcomp_intsignal().bit()), + ) + .field( + "ch3_enable_src_dec_err_intsignal", + &format_args!("{}", self.ch3_enable_src_dec_err_intsignal().bit()), + ) + .field( + "ch3_enable_dst_dec_err_intsignal", + &format_args!("{}", self.ch3_enable_dst_dec_err_intsignal().bit()), + ) + .field( + "ch3_enable_src_slv_err_intsignal", + &format_args!("{}", self.ch3_enable_src_slv_err_intsignal().bit()), + ) + .field( + "ch3_enable_dst_slv_err_intsignal", + &format_args!("{}", self.ch3_enable_dst_slv_err_intsignal().bit()), + ) + .field( + "ch3_enable_lli_rd_dec_err_intsignal", + &format_args!("{}", self.ch3_enable_lli_rd_dec_err_intsignal().bit()), + ) + .field( + "ch3_enable_lli_wr_dec_err_intsignal", + &format_args!("{}", self.ch3_enable_lli_wr_dec_err_intsignal().bit()), + ) + .field( + "ch3_enable_lli_rd_slv_err_intsignal", + &format_args!("{}", self.ch3_enable_lli_rd_slv_err_intsignal().bit()), + ) + .field( + "ch3_enable_lli_wr_slv_err_intsignal", + &format_args!("{}", self.ch3_enable_lli_wr_slv_err_intsignal().bit()), + ) + .field( + "ch3_enable_shadowreg_or_lli_invalid_err_intsignal", + &format_args!( + "{}", + self.ch3_enable_shadowreg_or_lli_invalid_err_intsignal() + .bit() + ), + ) + .field( + "ch3_enable_slvif_multiblktype_err_intsignal", + &format_args!( + "{}", + self.ch3_enable_slvif_multiblktype_err_intsignal().bit() + ), + ) + .field( + "ch3_enable_slvif_dec_err_intsignal", + &format_args!("{}", self.ch3_enable_slvif_dec_err_intsignal().bit()), + ) + .field( + "ch3_enable_slvif_wr2ro_err_intsignal", + &format_args!("{}", self.ch3_enable_slvif_wr2ro_err_intsignal().bit()), + ) + .field( + "ch3_enable_slvif_rd2rwo_err_intsignal", + &format_args!("{}", self.ch3_enable_slvif_rd2rwo_err_intsignal().bit()), + ) + .field( + "ch3_enable_slvif_wronchen_err_intsignal", + &format_args!("{}", self.ch3_enable_slvif_wronchen_err_intsignal().bit()), + ) + .field( + "ch3_enable_slvif_shadowreg_wron_valid_err_intsignal", + &format_args!( + "{}", + self.ch3_enable_slvif_shadowreg_wron_valid_err_intsignal() + .bit() + ), + ) + .field( + "ch3_enable_slvif_wronhold_err_intsignal", + &format_args!("{}", self.ch3_enable_slvif_wronhold_err_intsignal().bit()), + ) + .field( + "ch3_enable_slvif_wrparity_err_intsignal", + &format_args!("{}", self.ch3_enable_slvif_wrparity_err_intsignal().bit()), + ) + .field( + "ch3_enable_ch_lock_cleared_intsignal", + &format_args!("{}", self.ch3_enable_ch_lock_cleared_intsignal().bit()), + ) + .field( + "ch3_enable_ch_src_suspended_intsignal", + &format_args!("{}", self.ch3_enable_ch_src_suspended_intsignal().bit()), + ) + .field( + "ch3_enable_ch_suspended_intsignal", + &format_args!("{}", self.ch3_enable_ch_suspended_intsignal().bit()), + ) + .field( + "ch3_enable_ch_disabled_intsignal", + &format_args!("{}", self.ch3_enable_ch_disabled_intsignal().bit()), + ) + .field( + "ch3_enable_ch_aborted_intsignal", + &format_args!("{}", self.ch3_enable_ch_aborted_intsignal().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_block_tfr_done_intsignal( + &mut self, + ) -> CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W { + CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_dma_tfr_done_intsignal( + &mut self, + ) -> CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_W { + CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_src_transcomp_intsignal( + &mut self, + ) -> CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W { + CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_dst_transcomp_intsignal( + &mut self, + ) -> CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_W { + CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_src_dec_err_intsignal( + &mut self, + ) -> CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_W { + CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_dst_dec_err_intsignal( + &mut self, + ) -> CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_W { + CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_src_slv_err_intsignal( + &mut self, + ) -> CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_W { + CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_dst_slv_err_intsignal( + &mut self, + ) -> CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_W { + CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_lli_rd_dec_err_intsignal( + &mut self, + ) -> CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W { + CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_lli_wr_dec_err_intsignal( + &mut self, + ) -> CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W { + CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_lli_rd_slv_err_intsignal( + &mut self, + ) -> CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W { + CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_lli_wr_slv_err_intsignal( + &mut self, + ) -> CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W { + CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_shadowreg_or_lli_invalid_err_intsignal( + &mut self, + ) -> CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W { + CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_multiblktype_err_intsignal( + &mut self, + ) -> CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W { + CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_dec_err_intsignal( + &mut self, + ) -> CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W { + CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_wr2ro_err_intsignal( + &mut self, + ) -> CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W { + CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_rd2rwo_err_intsignal( + &mut self, + ) -> CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W { + CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_wronchen_err_intsignal( + &mut self, + ) -> CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W { + CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_shadowreg_wron_valid_err_intsignal( + &mut self, + ) -> CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W { + CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_wronhold_err_intsignal( + &mut self, + ) -> CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W { + CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W::new(self, 21) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_ch_lock_cleared_intsignal( + &mut self, + ) -> CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W { + CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_ch_src_suspended_intsignal( + &mut self, + ) -> CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W { + CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_ch_suspended_intsignal( + &mut self, + ) -> CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_W { + CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_ch_disabled_intsignal( + &mut self, + ) -> CH3_ENABLE_CH_DISABLED_INTSIGNAL_W { + CH3_ENABLE_CH_DISABLED_INTSIGNAL_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_ch_aborted_intsignal( + &mut self, + ) -> CH3_ENABLE_CH_ABORTED_INTSIGNAL_W { + CH3_ENABLE_CH_ABORTED_INTSIGNAL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intsignal_enable0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_intsignal_enable0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_INTSIGNAL_ENABLE0_SPEC; +impl crate::RegisterSpec for CH3_INTSIGNAL_ENABLE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_intsignal_enable0::R`](R) reader structure"] +impl crate::Readable for CH3_INTSIGNAL_ENABLE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_intsignal_enable0::W`](W) writer structure"] +impl crate::Writable for CH3_INTSIGNAL_ENABLE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_INTSIGNAL_ENABLE0 to value 0xfa3f_7ffb"] +impl crate::Resettable for CH3_INTSIGNAL_ENABLE0_SPEC { + const RESET_VALUE: Self::Ux = 0xfa3f_7ffb; +} diff --git a/esp32p4/src/dma/ch3_intsignal_enable1.rs b/esp32p4/src/dma/ch3_intsignal_enable1.rs new file mode 100644 index 0000000000..82f51b7122 --- /dev/null +++ b/esp32p4/src/dma/ch3_intsignal_enable1.rs @@ -0,0 +1,92 @@ +#[doc = "Register `CH3_INTSIGNAL_ENABLE1` reader"] +pub type R = crate::R; +#[doc = "Field `CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL` reader - NA"] +pub type CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch3_enable_ecc_prot_chmem_correrr_intsignal( + &self, + ) -> CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R { + CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch3_enable_ecc_prot_chmem_uncorrerr_intsignal( + &self, + ) -> CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R { + CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch3_enable_ecc_prot_uidmem_correrr_intsignal( + &self, + ) -> CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R { + CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal( + &self, + ) -> CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R { + CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_INTSIGNAL_ENABLE1") + .field( + "ch3_enable_ecc_prot_chmem_correrr_intsignal", + &format_args!( + "{}", + self.ch3_enable_ecc_prot_chmem_correrr_intsignal().bit() + ), + ) + .field( + "ch3_enable_ecc_prot_chmem_uncorrerr_intsignal", + &format_args!( + "{}", + self.ch3_enable_ecc_prot_chmem_uncorrerr_intsignal().bit() + ), + ) + .field( + "ch3_enable_ecc_prot_uidmem_correrr_intsignal", + &format_args!( + "{}", + self.ch3_enable_ecc_prot_uidmem_correrr_intsignal().bit() + ), + ) + .field( + "ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal", + &format_args!( + "{}", + self.ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal().bit() + ), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intsignal_enable1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_INTSIGNAL_ENABLE1_SPEC; +impl crate::RegisterSpec for CH3_INTSIGNAL_ENABLE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_intsignal_enable1::R`](R) reader structure"] +impl crate::Readable for CH3_INTSIGNAL_ENABLE1_SPEC {} +#[doc = "`reset()` method sets CH3_INTSIGNAL_ENABLE1 to value 0x0f"] +impl crate::Resettable for CH3_INTSIGNAL_ENABLE1_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/dma/ch3_intstatus0.rs b/esp32p4/src/dma/ch3_intstatus0.rs new file mode 100644 index 0000000000..f040ad003c --- /dev/null +++ b/esp32p4/src/dma/ch3_intstatus0.rs @@ -0,0 +1,321 @@ +#[doc = "Register `CH3_INTSTATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `CH3_BLOCK_TFR_DONE_INTSTAT` reader - NA"] +pub type CH3_BLOCK_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_DMA_TFR_DONE_INTSTAT` reader - NA"] +pub type CH3_DMA_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SRC_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH3_SRC_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_DST_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH3_DST_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SRC_DEC_ERR_INTSTAT` reader - NA"] +pub type CH3_SRC_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_DST_DEC_ERR_INTSTAT` reader - NA"] +pub type CH3_DST_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SRC_SLV_ERR_INTSTAT` reader - NA"] +pub type CH3_SRC_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_DST_SLV_ERR_INTSTAT` reader - NA"] +pub type CH3_DST_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_LLI_RD_DEC_ERR_INTSTAT` reader - NA"] +pub type CH3_LLI_RD_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_LLI_WR_DEC_ERR_INTSTAT` reader - NA"] +pub type CH3_LLI_WR_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_LLI_RD_SLV_ERR_INTSTAT` reader - NA"] +pub type CH3_LLI_RD_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_LLI_WR_SLV_ERR_INTSTAT` reader - NA"] +pub type CH3_LLI_WR_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` reader - NA"] +pub type CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` reader - NA"] +pub type CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SLVIF_DEC_ERR_INTSTAT` reader - NA"] +pub type CH3_SLVIF_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SLVIF_WR2RO_ERR_INTSTAT` reader - NA"] +pub type CH3_SLVIF_WR2RO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SLVIF_RD2RWO_ERR_INTSTAT` reader - NA"] +pub type CH3_SLVIF_RD2RWO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SLVIF_WRONCHEN_ERR_INTSTAT` reader - NA"] +pub type CH3_SLVIF_WRONCHEN_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` reader - NA"] +pub type CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SLVIF_WRONHOLD_ERR_INTSTAT` reader - NA"] +pub type CH3_SLVIF_WRONHOLD_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_SLVIF_WRPARITY_ERR_INTSTAT` reader - NA"] +pub type CH3_SLVIF_WRPARITY_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_CH_LOCK_CLEARED_INTSTAT` reader - NA"] +pub type CH3_CH_LOCK_CLEARED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_CH_SRC_SUSPENDED_INTSTAT` reader - NA"] +pub type CH3_CH_SRC_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_CH_SUSPENDED_INTSTAT` reader - NA"] +pub type CH3_CH_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_CH_DISABLED_INTSTAT` reader - NA"] +pub type CH3_CH_DISABLED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_CH_ABORTED_INTSTAT` reader - NA"] +pub type CH3_CH_ABORTED_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch3_block_tfr_done_intstat(&self) -> CH3_BLOCK_TFR_DONE_INTSTAT_R { + CH3_BLOCK_TFR_DONE_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch3_dma_tfr_done_intstat(&self) -> CH3_DMA_TFR_DONE_INTSTAT_R { + CH3_DMA_TFR_DONE_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch3_src_transcomp_intstat(&self) -> CH3_SRC_TRANSCOMP_INTSTAT_R { + CH3_SRC_TRANSCOMP_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch3_dst_transcomp_intstat(&self) -> CH3_DST_TRANSCOMP_INTSTAT_R { + CH3_DST_TRANSCOMP_INTSTAT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch3_src_dec_err_intstat(&self) -> CH3_SRC_DEC_ERR_INTSTAT_R { + CH3_SRC_DEC_ERR_INTSTAT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch3_dst_dec_err_intstat(&self) -> CH3_DST_DEC_ERR_INTSTAT_R { + CH3_DST_DEC_ERR_INTSTAT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch3_src_slv_err_intstat(&self) -> CH3_SRC_SLV_ERR_INTSTAT_R { + CH3_SRC_SLV_ERR_INTSTAT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch3_dst_slv_err_intstat(&self) -> CH3_DST_SLV_ERR_INTSTAT_R { + CH3_DST_SLV_ERR_INTSTAT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch3_lli_rd_dec_err_intstat(&self) -> CH3_LLI_RD_DEC_ERR_INTSTAT_R { + CH3_LLI_RD_DEC_ERR_INTSTAT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch3_lli_wr_dec_err_intstat(&self) -> CH3_LLI_WR_DEC_ERR_INTSTAT_R { + CH3_LLI_WR_DEC_ERR_INTSTAT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch3_lli_rd_slv_err_intstat(&self) -> CH3_LLI_RD_SLV_ERR_INTSTAT_R { + CH3_LLI_RD_SLV_ERR_INTSTAT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch3_lli_wr_slv_err_intstat(&self) -> CH3_LLI_WR_SLV_ERR_INTSTAT_R { + CH3_LLI_WR_SLV_ERR_INTSTAT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch3_shadowreg_or_lli_invalid_err_intstat( + &self, + ) -> CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R { + CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch3_slvif_multiblktype_err_intstat(&self) -> CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R { + CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch3_slvif_dec_err_intstat(&self) -> CH3_SLVIF_DEC_ERR_INTSTAT_R { + CH3_SLVIF_DEC_ERR_INTSTAT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch3_slvif_wr2ro_err_intstat(&self) -> CH3_SLVIF_WR2RO_ERR_INTSTAT_R { + CH3_SLVIF_WR2RO_ERR_INTSTAT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch3_slvif_rd2rwo_err_intstat(&self) -> CH3_SLVIF_RD2RWO_ERR_INTSTAT_R { + CH3_SLVIF_RD2RWO_ERR_INTSTAT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch3_slvif_wronchen_err_intstat(&self) -> CH3_SLVIF_WRONCHEN_ERR_INTSTAT_R { + CH3_SLVIF_WRONCHEN_ERR_INTSTAT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch3_slvif_shadowreg_wron_valid_err_intstat( + &self, + ) -> CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R { + CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch3_slvif_wronhold_err_intstat(&self) -> CH3_SLVIF_WRONHOLD_ERR_INTSTAT_R { + CH3_SLVIF_WRONHOLD_ERR_INTSTAT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch3_slvif_wrparity_err_intstat(&self) -> CH3_SLVIF_WRPARITY_ERR_INTSTAT_R { + CH3_SLVIF_WRPARITY_ERR_INTSTAT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch3_ch_lock_cleared_intstat(&self) -> CH3_CH_LOCK_CLEARED_INTSTAT_R { + CH3_CH_LOCK_CLEARED_INTSTAT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch3_ch_src_suspended_intstat(&self) -> CH3_CH_SRC_SUSPENDED_INTSTAT_R { + CH3_CH_SRC_SUSPENDED_INTSTAT_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch3_ch_suspended_intstat(&self) -> CH3_CH_SUSPENDED_INTSTAT_R { + CH3_CH_SUSPENDED_INTSTAT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch3_ch_disabled_intstat(&self) -> CH3_CH_DISABLED_INTSTAT_R { + CH3_CH_DISABLED_INTSTAT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch3_ch_aborted_intstat(&self) -> CH3_CH_ABORTED_INTSTAT_R { + CH3_CH_ABORTED_INTSTAT_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_INTSTATUS0") + .field( + "ch3_block_tfr_done_intstat", + &format_args!("{}", self.ch3_block_tfr_done_intstat().bit()), + ) + .field( + "ch3_dma_tfr_done_intstat", + &format_args!("{}", self.ch3_dma_tfr_done_intstat().bit()), + ) + .field( + "ch3_src_transcomp_intstat", + &format_args!("{}", self.ch3_src_transcomp_intstat().bit()), + ) + .field( + "ch3_dst_transcomp_intstat", + &format_args!("{}", self.ch3_dst_transcomp_intstat().bit()), + ) + .field( + "ch3_src_dec_err_intstat", + &format_args!("{}", self.ch3_src_dec_err_intstat().bit()), + ) + .field( + "ch3_dst_dec_err_intstat", + &format_args!("{}", self.ch3_dst_dec_err_intstat().bit()), + ) + .field( + "ch3_src_slv_err_intstat", + &format_args!("{}", self.ch3_src_slv_err_intstat().bit()), + ) + .field( + "ch3_dst_slv_err_intstat", + &format_args!("{}", self.ch3_dst_slv_err_intstat().bit()), + ) + .field( + "ch3_lli_rd_dec_err_intstat", + &format_args!("{}", self.ch3_lli_rd_dec_err_intstat().bit()), + ) + .field( + "ch3_lli_wr_dec_err_intstat", + &format_args!("{}", self.ch3_lli_wr_dec_err_intstat().bit()), + ) + .field( + "ch3_lli_rd_slv_err_intstat", + &format_args!("{}", self.ch3_lli_rd_slv_err_intstat().bit()), + ) + .field( + "ch3_lli_wr_slv_err_intstat", + &format_args!("{}", self.ch3_lli_wr_slv_err_intstat().bit()), + ) + .field( + "ch3_shadowreg_or_lli_invalid_err_intstat", + &format_args!("{}", self.ch3_shadowreg_or_lli_invalid_err_intstat().bit()), + ) + .field( + "ch3_slvif_multiblktype_err_intstat", + &format_args!("{}", self.ch3_slvif_multiblktype_err_intstat().bit()), + ) + .field( + "ch3_slvif_dec_err_intstat", + &format_args!("{}", self.ch3_slvif_dec_err_intstat().bit()), + ) + .field( + "ch3_slvif_wr2ro_err_intstat", + &format_args!("{}", self.ch3_slvif_wr2ro_err_intstat().bit()), + ) + .field( + "ch3_slvif_rd2rwo_err_intstat", + &format_args!("{}", self.ch3_slvif_rd2rwo_err_intstat().bit()), + ) + .field( + "ch3_slvif_wronchen_err_intstat", + &format_args!("{}", self.ch3_slvif_wronchen_err_intstat().bit()), + ) + .field( + "ch3_slvif_shadowreg_wron_valid_err_intstat", + &format_args!( + "{}", + self.ch3_slvif_shadowreg_wron_valid_err_intstat().bit() + ), + ) + .field( + "ch3_slvif_wronhold_err_intstat", + &format_args!("{}", self.ch3_slvif_wronhold_err_intstat().bit()), + ) + .field( + "ch3_slvif_wrparity_err_intstat", + &format_args!("{}", self.ch3_slvif_wrparity_err_intstat().bit()), + ) + .field( + "ch3_ch_lock_cleared_intstat", + &format_args!("{}", self.ch3_ch_lock_cleared_intstat().bit()), + ) + .field( + "ch3_ch_src_suspended_intstat", + &format_args!("{}", self.ch3_ch_src_suspended_intstat().bit()), + ) + .field( + "ch3_ch_suspended_intstat", + &format_args!("{}", self.ch3_ch_suspended_intstat().bit()), + ) + .field( + "ch3_ch_disabled_intstat", + &format_args!("{}", self.ch3_ch_disabled_intstat().bit()), + ) + .field( + "ch3_ch_aborted_intstat", + &format_args!("{}", self.ch3_ch_aborted_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intstatus0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_INTSTATUS0_SPEC; +impl crate::RegisterSpec for CH3_INTSTATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_intstatus0::R`](R) reader structure"] +impl crate::Readable for CH3_INTSTATUS0_SPEC {} +#[doc = "`reset()` method sets CH3_INTSTATUS0 to value 0"] +impl crate::Resettable for CH3_INTSTATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_intstatus1.rs b/esp32p4/src/dma/ch3_intstatus1.rs new file mode 100644 index 0000000000..adef3faa9c --- /dev/null +++ b/esp32p4/src/dma/ch3_intstatus1.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CH3_INTSTATUS1` reader"] +pub type R = crate::R; +#[doc = "Field `CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch3_ecc_prot_chmem_correrr_intstat(&self) -> CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_R { + CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch3_ecc_prot_chmem_uncorrerr_intstat(&self) -> CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R { + CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch3_ecc_prot_uidmem_correrr_intstat(&self) -> CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R { + CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch3_ecc_prot_uidmem_uncorrerr_intstat(&self) -> CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R { + CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_INTSTATUS1") + .field( + "ch3_ecc_prot_chmem_correrr_intstat", + &format_args!("{}", self.ch3_ecc_prot_chmem_correrr_intstat().bit()), + ) + .field( + "ch3_ecc_prot_chmem_uncorrerr_intstat", + &format_args!("{}", self.ch3_ecc_prot_chmem_uncorrerr_intstat().bit()), + ) + .field( + "ch3_ecc_prot_uidmem_correrr_intstat", + &format_args!("{}", self.ch3_ecc_prot_uidmem_correrr_intstat().bit()), + ) + .field( + "ch3_ecc_prot_uidmem_uncorrerr_intstat", + &format_args!("{}", self.ch3_ecc_prot_uidmem_uncorrerr_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intstatus1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_INTSTATUS1_SPEC; +impl crate::RegisterSpec for CH3_INTSTATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_intstatus1::R`](R) reader structure"] +impl crate::Readable for CH3_INTSTATUS1_SPEC {} +#[doc = "`reset()` method sets CH3_INTSTATUS1 to value 0"] +impl crate::Resettable for CH3_INTSTATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_intstatus_enable0.rs b/esp32p4/src/dma/ch3_intstatus_enable0.rs new file mode 100644 index 0000000000..0a57ec6d7e --- /dev/null +++ b/esp32p4/src/dma/ch3_intstatus_enable0.rs @@ -0,0 +1,596 @@ +#[doc = "Register `CH3_INTSTATUS_ENABLE0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_INTSTATUS_ENABLE0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT` reader - NA"] +pub type CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT` writer - NA"] +pub type CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_DMA_TFR_DONE_INTSTAT` reader - NA"] +pub type CH3_ENABLE_DMA_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_DMA_TFR_DONE_INTSTAT` writer - NA"] +pub type CH3_ENABLE_DMA_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SRC_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SRC_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_DST_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH3_ENABLE_DST_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_DST_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH3_ENABLE_DST_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SRC_DEC_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SRC_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SRC_DEC_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_SRC_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_DST_DEC_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_DST_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_DST_DEC_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_DST_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SRC_SLV_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SRC_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SRC_SLV_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_SRC_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_DST_SLV_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_DST_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_DST_SLV_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_DST_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT` writer - NA"] +pub type CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT` reader - NA"] +pub type CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT` writer - NA"] +pub type CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT` reader - NA"] +pub type CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT` writer - NA"] +pub type CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_CH_SUSPENDED_INTSTAT` reader - NA"] +pub type CH3_ENABLE_CH_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_SUSPENDED_INTSTAT` writer - NA"] +pub type CH3_ENABLE_CH_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_CH_DISABLED_INTSTAT` reader - NA"] +pub type CH3_ENABLE_CH_DISABLED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_DISABLED_INTSTAT` writer - NA"] +pub type CH3_ENABLE_CH_DISABLED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ENABLE_CH_ABORTED_INTSTAT` reader - NA"] +pub type CH3_ENABLE_CH_ABORTED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_CH_ABORTED_INTSTAT` writer - NA"] +pub type CH3_ENABLE_CH_ABORTED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch3_enable_block_tfr_done_intstat(&self) -> CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_R { + CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch3_enable_dma_tfr_done_intstat(&self) -> CH3_ENABLE_DMA_TFR_DONE_INTSTAT_R { + CH3_ENABLE_DMA_TFR_DONE_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch3_enable_src_transcomp_intstat(&self) -> CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_R { + CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch3_enable_dst_transcomp_intstat(&self) -> CH3_ENABLE_DST_TRANSCOMP_INTSTAT_R { + CH3_ENABLE_DST_TRANSCOMP_INTSTAT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch3_enable_src_dec_err_intstat(&self) -> CH3_ENABLE_SRC_DEC_ERR_INTSTAT_R { + CH3_ENABLE_SRC_DEC_ERR_INTSTAT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch3_enable_dst_dec_err_intstat(&self) -> CH3_ENABLE_DST_DEC_ERR_INTSTAT_R { + CH3_ENABLE_DST_DEC_ERR_INTSTAT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch3_enable_src_slv_err_intstat(&self) -> CH3_ENABLE_SRC_SLV_ERR_INTSTAT_R { + CH3_ENABLE_SRC_SLV_ERR_INTSTAT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch3_enable_dst_slv_err_intstat(&self) -> CH3_ENABLE_DST_SLV_ERR_INTSTAT_R { + CH3_ENABLE_DST_SLV_ERR_INTSTAT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch3_enable_lli_rd_dec_err_intstat(&self) -> CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R { + CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch3_enable_lli_wr_dec_err_intstat(&self) -> CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R { + CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch3_enable_lli_rd_slv_err_intstat(&self) -> CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R { + CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch3_enable_lli_wr_slv_err_intstat(&self) -> CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R { + CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch3_enable_shadowreg_or_lli_invalid_err_intstat( + &self, + ) -> CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R { + CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_multiblktype_err_intstat( + &self, + ) -> CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R { + CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_dec_err_intstat(&self) -> CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_R { + CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_wr2ro_err_intstat(&self) -> CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R { + CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_rd2rwo_err_intstat(&self) -> CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R { + CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_wronchen_err_intstat(&self) -> CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R { + CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_shadowreg_wron_valid_err_intstat( + &self, + ) -> CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R { + CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_wronhold_err_intstat(&self) -> CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R { + CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch3_enable_slvif_wrparity_err_intstat(&self) -> CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R { + CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch3_enable_ch_lock_cleared_intstat(&self) -> CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_R { + CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch3_enable_ch_src_suspended_intstat(&self) -> CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R { + CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch3_enable_ch_suspended_intstat(&self) -> CH3_ENABLE_CH_SUSPENDED_INTSTAT_R { + CH3_ENABLE_CH_SUSPENDED_INTSTAT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch3_enable_ch_disabled_intstat(&self) -> CH3_ENABLE_CH_DISABLED_INTSTAT_R { + CH3_ENABLE_CH_DISABLED_INTSTAT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch3_enable_ch_aborted_intstat(&self) -> CH3_ENABLE_CH_ABORTED_INTSTAT_R { + CH3_ENABLE_CH_ABORTED_INTSTAT_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_INTSTATUS_ENABLE0") + .field( + "ch3_enable_block_tfr_done_intstat", + &format_args!("{}", self.ch3_enable_block_tfr_done_intstat().bit()), + ) + .field( + "ch3_enable_dma_tfr_done_intstat", + &format_args!("{}", self.ch3_enable_dma_tfr_done_intstat().bit()), + ) + .field( + "ch3_enable_src_transcomp_intstat", + &format_args!("{}", self.ch3_enable_src_transcomp_intstat().bit()), + ) + .field( + "ch3_enable_dst_transcomp_intstat", + &format_args!("{}", self.ch3_enable_dst_transcomp_intstat().bit()), + ) + .field( + "ch3_enable_src_dec_err_intstat", + &format_args!("{}", self.ch3_enable_src_dec_err_intstat().bit()), + ) + .field( + "ch3_enable_dst_dec_err_intstat", + &format_args!("{}", self.ch3_enable_dst_dec_err_intstat().bit()), + ) + .field( + "ch3_enable_src_slv_err_intstat", + &format_args!("{}", self.ch3_enable_src_slv_err_intstat().bit()), + ) + .field( + "ch3_enable_dst_slv_err_intstat", + &format_args!("{}", self.ch3_enable_dst_slv_err_intstat().bit()), + ) + .field( + "ch3_enable_lli_rd_dec_err_intstat", + &format_args!("{}", self.ch3_enable_lli_rd_dec_err_intstat().bit()), + ) + .field( + "ch3_enable_lli_wr_dec_err_intstat", + &format_args!("{}", self.ch3_enable_lli_wr_dec_err_intstat().bit()), + ) + .field( + "ch3_enable_lli_rd_slv_err_intstat", + &format_args!("{}", self.ch3_enable_lli_rd_slv_err_intstat().bit()), + ) + .field( + "ch3_enable_lli_wr_slv_err_intstat", + &format_args!("{}", self.ch3_enable_lli_wr_slv_err_intstat().bit()), + ) + .field( + "ch3_enable_shadowreg_or_lli_invalid_err_intstat", + &format_args!( + "{}", + self.ch3_enable_shadowreg_or_lli_invalid_err_intstat().bit() + ), + ) + .field( + "ch3_enable_slvif_multiblktype_err_intstat", + &format_args!("{}", self.ch3_enable_slvif_multiblktype_err_intstat().bit()), + ) + .field( + "ch3_enable_slvif_dec_err_intstat", + &format_args!("{}", self.ch3_enable_slvif_dec_err_intstat().bit()), + ) + .field( + "ch3_enable_slvif_wr2ro_err_intstat", + &format_args!("{}", self.ch3_enable_slvif_wr2ro_err_intstat().bit()), + ) + .field( + "ch3_enable_slvif_rd2rwo_err_intstat", + &format_args!("{}", self.ch3_enable_slvif_rd2rwo_err_intstat().bit()), + ) + .field( + "ch3_enable_slvif_wronchen_err_intstat", + &format_args!("{}", self.ch3_enable_slvif_wronchen_err_intstat().bit()), + ) + .field( + "ch3_enable_slvif_shadowreg_wron_valid_err_intstat", + &format_args!( + "{}", + self.ch3_enable_slvif_shadowreg_wron_valid_err_intstat() + .bit() + ), + ) + .field( + "ch3_enable_slvif_wronhold_err_intstat", + &format_args!("{}", self.ch3_enable_slvif_wronhold_err_intstat().bit()), + ) + .field( + "ch3_enable_slvif_wrparity_err_intstat", + &format_args!("{}", self.ch3_enable_slvif_wrparity_err_intstat().bit()), + ) + .field( + "ch3_enable_ch_lock_cleared_intstat", + &format_args!("{}", self.ch3_enable_ch_lock_cleared_intstat().bit()), + ) + .field( + "ch3_enable_ch_src_suspended_intstat", + &format_args!("{}", self.ch3_enable_ch_src_suspended_intstat().bit()), + ) + .field( + "ch3_enable_ch_suspended_intstat", + &format_args!("{}", self.ch3_enable_ch_suspended_intstat().bit()), + ) + .field( + "ch3_enable_ch_disabled_intstat", + &format_args!("{}", self.ch3_enable_ch_disabled_intstat().bit()), + ) + .field( + "ch3_enable_ch_aborted_intstat", + &format_args!("{}", self.ch3_enable_ch_aborted_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_block_tfr_done_intstat( + &mut self, + ) -> CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_W { + CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_dma_tfr_done_intstat( + &mut self, + ) -> CH3_ENABLE_DMA_TFR_DONE_INTSTAT_W { + CH3_ENABLE_DMA_TFR_DONE_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_src_transcomp_intstat( + &mut self, + ) -> CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_W { + CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_dst_transcomp_intstat( + &mut self, + ) -> CH3_ENABLE_DST_TRANSCOMP_INTSTAT_W { + CH3_ENABLE_DST_TRANSCOMP_INTSTAT_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_src_dec_err_intstat( + &mut self, + ) -> CH3_ENABLE_SRC_DEC_ERR_INTSTAT_W { + CH3_ENABLE_SRC_DEC_ERR_INTSTAT_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_dst_dec_err_intstat( + &mut self, + ) -> CH3_ENABLE_DST_DEC_ERR_INTSTAT_W { + CH3_ENABLE_DST_DEC_ERR_INTSTAT_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_src_slv_err_intstat( + &mut self, + ) -> CH3_ENABLE_SRC_SLV_ERR_INTSTAT_W { + CH3_ENABLE_SRC_SLV_ERR_INTSTAT_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_dst_slv_err_intstat( + &mut self, + ) -> CH3_ENABLE_DST_SLV_ERR_INTSTAT_W { + CH3_ENABLE_DST_SLV_ERR_INTSTAT_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_lli_rd_dec_err_intstat( + &mut self, + ) -> CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W { + CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_lli_wr_dec_err_intstat( + &mut self, + ) -> CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W { + CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_lli_rd_slv_err_intstat( + &mut self, + ) -> CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W { + CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_lli_wr_slv_err_intstat( + &mut self, + ) -> CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W { + CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_shadowreg_or_lli_invalid_err_intstat( + &mut self, + ) -> CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W { + CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_multiblktype_err_intstat( + &mut self, + ) -> CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W { + CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_dec_err_intstat( + &mut self, + ) -> CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_W { + CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_wr2ro_err_intstat( + &mut self, + ) -> CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W { + CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_rd2rwo_err_intstat( + &mut self, + ) -> CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W { + CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_wronchen_err_intstat( + &mut self, + ) -> CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W { + CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_shadowreg_wron_valid_err_intstat( + &mut self, + ) -> CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W { + CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_slvif_wronhold_err_intstat( + &mut self, + ) -> CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W { + CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W::new(self, 21) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_ch_lock_cleared_intstat( + &mut self, + ) -> CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_W { + CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_ch_src_suspended_intstat( + &mut self, + ) -> CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W { + CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_ch_suspended_intstat( + &mut self, + ) -> CH3_ENABLE_CH_SUSPENDED_INTSTAT_W { + CH3_ENABLE_CH_SUSPENDED_INTSTAT_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_ch_disabled_intstat( + &mut self, + ) -> CH3_ENABLE_CH_DISABLED_INTSTAT_W { + CH3_ENABLE_CH_DISABLED_INTSTAT_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_enable_ch_aborted_intstat( + &mut self, + ) -> CH3_ENABLE_CH_ABORTED_INTSTAT_W { + CH3_ENABLE_CH_ABORTED_INTSTAT_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intstatus_enable0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_intstatus_enable0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_INTSTATUS_ENABLE0_SPEC; +impl crate::RegisterSpec for CH3_INTSTATUS_ENABLE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_intstatus_enable0::R`](R) reader structure"] +impl crate::Readable for CH3_INTSTATUS_ENABLE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_intstatus_enable0::W`](W) writer structure"] +impl crate::Writable for CH3_INTSTATUS_ENABLE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_INTSTATUS_ENABLE0 to value 0xfa3f_7ffb"] +impl crate::Resettable for CH3_INTSTATUS_ENABLE0_SPEC { + const RESET_VALUE: Self::Ux = 0xfa3f_7ffb; +} diff --git a/esp32p4/src/dma/ch3_intstatus_enable1.rs b/esp32p4/src/dma/ch3_intstatus_enable1.rs new file mode 100644 index 0000000000..e8519da281 --- /dev/null +++ b/esp32p4/src/dma/ch3_intstatus_enable1.rs @@ -0,0 +1,89 @@ +#[doc = "Register `CH3_INTSTATUS_ENABLE1` reader"] +pub type R = crate::R; +#[doc = "Field `CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch3_enable_ecc_prot_chmem_correrr_intstat( + &self, + ) -> CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R { + CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch3_enable_ecc_prot_chmem_uncorrerr_intstat( + &self, + ) -> CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R { + CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch3_enable_ecc_prot_uidmem_correrr_intstat( + &self, + ) -> CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R { + CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch3_enable_ecc_prot_uidmem_uncorrerr_intstat( + &self, + ) -> CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R { + CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_INTSTATUS_ENABLE1") + .field( + "ch3_enable_ecc_prot_chmem_correrr_intstat", + &format_args!("{}", self.ch3_enable_ecc_prot_chmem_correrr_intstat().bit()), + ) + .field( + "ch3_enable_ecc_prot_chmem_uncorrerr_intstat", + &format_args!( + "{}", + self.ch3_enable_ecc_prot_chmem_uncorrerr_intstat().bit() + ), + ) + .field( + "ch3_enable_ecc_prot_uidmem_correrr_intstat", + &format_args!( + "{}", + self.ch3_enable_ecc_prot_uidmem_correrr_intstat().bit() + ), + ) + .field( + "ch3_enable_ecc_prot_uidmem_uncorrerr_intstat", + &format_args!( + "{}", + self.ch3_enable_ecc_prot_uidmem_uncorrerr_intstat().bit() + ), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_intstatus_enable1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_INTSTATUS_ENABLE1_SPEC; +impl crate::RegisterSpec for CH3_INTSTATUS_ENABLE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_intstatus_enable1::R`](R) reader structure"] +impl crate::Readable for CH3_INTSTATUS_ENABLE1_SPEC {} +#[doc = "`reset()` method sets CH3_INTSTATUS_ENABLE1 to value 0x0f"] +impl crate::Resettable for CH3_INTSTATUS_ENABLE1_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/dma/ch3_llp0.rs b/esp32p4/src/dma/ch3_llp0.rs new file mode 100644 index 0000000000..2fa612af1c --- /dev/null +++ b/esp32p4/src/dma/ch3_llp0.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CH3_LLP0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_LLP0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_LMS` reader - NA"] +pub type CH3_LMS_R = crate::BitReader; +#[doc = "Field `CH3_LMS` writer - NA"] +pub type CH3_LMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_LOC0` reader - NA"] +pub type CH3_LOC0_R = crate::FieldReader; +#[doc = "Field `CH3_LOC0` writer - NA"] +pub type CH3_LOC0_W<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch3_lms(&self) -> CH3_LMS_R { + CH3_LMS_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 6:31 - NA"] + #[inline(always)] + pub fn ch3_loc0(&self) -> CH3_LOC0_R { + CH3_LOC0_R::new((self.bits >> 6) & 0x03ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_LLP0") + .field("ch3_lms", &format_args!("{}", self.ch3_lms().bit())) + .field("ch3_loc0", &format_args!("{}", self.ch3_loc0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_lms(&mut self) -> CH3_LMS_W { + CH3_LMS_W::new(self, 0) + } + #[doc = "Bits 6:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_loc0(&mut self) -> CH3_LOC0_W { + CH3_LOC0_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_llp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_llp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_LLP0_SPEC; +impl crate::RegisterSpec for CH3_LLP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_llp0::R`](R) reader structure"] +impl crate::Readable for CH3_LLP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_llp0::W`](W) writer structure"] +impl crate::Writable for CH3_LLP0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_LLP0 to value 0"] +impl crate::Resettable for CH3_LLP0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_llp1.rs b/esp32p4/src/dma/ch3_llp1.rs new file mode 100644 index 0000000000..013f837a0c --- /dev/null +++ b/esp32p4/src/dma/ch3_llp1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH3_LLP1` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_LLP1` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_LOC1` reader - NA"] +pub type CH3_LOC1_R = crate::FieldReader; +#[doc = "Field `CH3_LOC1` writer - NA"] +pub type CH3_LOC1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch3_loc1(&self) -> CH3_LOC1_R { + CH3_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_LLP1") + .field("ch3_loc1", &format_args!("{}", self.ch3_loc1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_loc1(&mut self) -> CH3_LOC1_W { + CH3_LOC1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_llp1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_llp1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_LLP1_SPEC; +impl crate::RegisterSpec for CH3_LLP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_llp1::R`](R) reader structure"] +impl crate::Readable for CH3_LLP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_llp1::W`](W) writer structure"] +impl crate::Writable for CH3_LLP1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_LLP1 to value 0"] +impl crate::Resettable for CH3_LLP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_sar0.rs b/esp32p4/src/dma/ch3_sar0.rs new file mode 100644 index 0000000000..e88e67af24 --- /dev/null +++ b/esp32p4/src/dma/ch3_sar0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH3_SAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_SAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_SAR0` reader - NA"] +pub type CH3_SAR0_R = crate::FieldReader; +#[doc = "Field `CH3_SAR0` writer - NA"] +pub type CH3_SAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch3_sar0(&self) -> CH3_SAR0_R { + CH3_SAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_SAR0") + .field("ch3_sar0", &format_args!("{}", self.ch3_sar0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_sar0(&mut self) -> CH3_SAR0_W { + CH3_SAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_sar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_sar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_SAR0_SPEC; +impl crate::RegisterSpec for CH3_SAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_sar0::R`](R) reader structure"] +impl crate::Readable for CH3_SAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_sar0::W`](W) writer structure"] +impl crate::Writable for CH3_SAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_SAR0 to value 0"] +impl crate::Resettable for CH3_SAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_sar1.rs b/esp32p4/src/dma/ch3_sar1.rs new file mode 100644 index 0000000000..a5afd1e040 --- /dev/null +++ b/esp32p4/src/dma/ch3_sar1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH3_SAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_SAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_SAR1` reader - NA"] +pub type CH3_SAR1_R = crate::FieldReader; +#[doc = "Field `CH3_SAR1` writer - NA"] +pub type CH3_SAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch3_sar1(&self) -> CH3_SAR1_R { + CH3_SAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_SAR1") + .field("ch3_sar1", &format_args!("{}", self.ch3_sar1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_sar1(&mut self) -> CH3_SAR1_W { + CH3_SAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_sar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_sar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_SAR1_SPEC; +impl crate::RegisterSpec for CH3_SAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_sar1::R`](R) reader structure"] +impl crate::Readable for CH3_SAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_sar1::W`](W) writer structure"] +impl crate::Writable for CH3_SAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_SAR1 to value 0"] +impl crate::Resettable for CH3_SAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_sstat0.rs b/esp32p4/src/dma/ch3_sstat0.rs new file mode 100644 index 0000000000..44c48f3975 --- /dev/null +++ b/esp32p4/src/dma/ch3_sstat0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `CH3_SSTAT0` reader"] +pub type R = crate::R; +#[doc = "Field `CH3_SSTAT` reader - NA"] +pub type CH3_SSTAT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch3_sstat(&self) -> CH3_SSTAT_R { + CH3_SSTAT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_SSTAT0") + .field("ch3_sstat", &format_args!("{}", self.ch3_sstat().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_sstat0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_SSTAT0_SPEC; +impl crate::RegisterSpec for CH3_SSTAT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_sstat0::R`](R) reader structure"] +impl crate::Readable for CH3_SSTAT0_SPEC {} +#[doc = "`reset()` method sets CH3_SSTAT0 to value 0"] +impl crate::Resettable for CH3_SSTAT0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_sstatar0.rs b/esp32p4/src/dma/ch3_sstatar0.rs new file mode 100644 index 0000000000..d1f24cb06d --- /dev/null +++ b/esp32p4/src/dma/ch3_sstatar0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH3_SSTATAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_SSTATAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_SSTATAR0` reader - NA"] +pub type CH3_SSTATAR0_R = crate::FieldReader; +#[doc = "Field `CH3_SSTATAR0` writer - NA"] +pub type CH3_SSTATAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch3_sstatar0(&self) -> CH3_SSTATAR0_R { + CH3_SSTATAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_SSTATAR0") + .field( + "ch3_sstatar0", + &format_args!("{}", self.ch3_sstatar0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_sstatar0(&mut self) -> CH3_SSTATAR0_W { + CH3_SSTATAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_sstatar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_sstatar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_SSTATAR0_SPEC; +impl crate::RegisterSpec for CH3_SSTATAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_sstatar0::R`](R) reader structure"] +impl crate::Readable for CH3_SSTATAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_sstatar0::W`](W) writer structure"] +impl crate::Writable for CH3_SSTATAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_SSTATAR0 to value 0"] +impl crate::Resettable for CH3_SSTATAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_sstatar1.rs b/esp32p4/src/dma/ch3_sstatar1.rs new file mode 100644 index 0000000000..8ca85f70d9 --- /dev/null +++ b/esp32p4/src/dma/ch3_sstatar1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH3_SSTATAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_SSTATAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_SSTATAR1` reader - NA"] +pub type CH3_SSTATAR1_R = crate::FieldReader; +#[doc = "Field `CH3_SSTATAR1` writer - NA"] +pub type CH3_SSTATAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch3_sstatar1(&self) -> CH3_SSTATAR1_R { + CH3_SSTATAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_SSTATAR1") + .field( + "ch3_sstatar1", + &format_args!("{}", self.ch3_sstatar1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_sstatar1(&mut self) -> CH3_SSTATAR1_W { + CH3_SSTATAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_sstatar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_sstatar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_SSTATAR1_SPEC; +impl crate::RegisterSpec for CH3_SSTATAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_sstatar1::R`](R) reader structure"] +impl crate::Readable for CH3_SSTATAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_sstatar1::W`](W) writer structure"] +impl crate::Writable for CH3_SSTATAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_SSTATAR1 to value 0"] +impl crate::Resettable for CH3_SSTATAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_status0.rs b/esp32p4/src/dma/ch3_status0.rs new file mode 100644 index 0000000000..568cb000a3 --- /dev/null +++ b/esp32p4/src/dma/ch3_status0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CH3_STATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `CH3_CMPLTD_BLK_TFR_SIZE` reader - NA"] +pub type CH3_CMPLTD_BLK_TFR_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + pub fn ch3_cmpltd_blk_tfr_size(&self) -> CH3_CMPLTD_BLK_TFR_SIZE_R { + CH3_CMPLTD_BLK_TFR_SIZE_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_STATUS0") + .field( + "ch3_cmpltd_blk_tfr_size", + &format_args!("{}", self.ch3_cmpltd_blk_tfr_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_STATUS0_SPEC; +impl crate::RegisterSpec for CH3_STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_status0::R`](R) reader structure"] +impl crate::Readable for CH3_STATUS0_SPEC {} +#[doc = "`reset()` method sets CH3_STATUS0 to value 0"] +impl crate::Resettable for CH3_STATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_status1.rs b/esp32p4/src/dma/ch3_status1.rs new file mode 100644 index 0000000000..2d97e9d835 --- /dev/null +++ b/esp32p4/src/dma/ch3_status1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CH3_STATUS1` reader"] +pub type R = crate::R; +#[doc = "Field `CH3_DATA_LEFT_IN_FIFO` reader - NA"] +pub type CH3_DATA_LEFT_IN_FIFO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + pub fn ch3_data_left_in_fifo(&self) -> CH3_DATA_LEFT_IN_FIFO_R { + CH3_DATA_LEFT_IN_FIFO_R::new((self.bits & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_STATUS1") + .field( + "ch3_data_left_in_fifo", + &format_args!("{}", self.ch3_data_left_in_fifo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_status1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_STATUS1_SPEC; +impl crate::RegisterSpec for CH3_STATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_status1::R`](R) reader structure"] +impl crate::Readable for CH3_STATUS1_SPEC {} +#[doc = "`reset()` method sets CH3_STATUS1 to value 0"] +impl crate::Resettable for CH3_STATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_swhsdst0.rs b/esp32p4/src/dma/ch3_swhsdst0.rs new file mode 100644 index 0000000000..aabe269651 --- /dev/null +++ b/esp32p4/src/dma/ch3_swhsdst0.rs @@ -0,0 +1,128 @@ +#[doc = "Register `CH3_SWHSDST0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_SWHSDST0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_SWHS_REQ_DST` reader - NA"] +pub type CH3_SWHS_REQ_DST_R = crate::BitReader; +#[doc = "Field `CH3_SWHS_REQ_DST` writer - NA"] +pub type CH3_SWHS_REQ_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SWHS_REQ_DST_WE` writer - NA"] +pub type CH3_SWHS_REQ_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SWHS_SGLREQ_DST` reader - NA"] +pub type CH3_SWHS_SGLREQ_DST_R = crate::BitReader; +#[doc = "Field `CH3_SWHS_SGLREQ_DST` writer - NA"] +pub type CH3_SWHS_SGLREQ_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SWHS_SGLREQ_DST_WE` writer - NA"] +pub type CH3_SWHS_SGLREQ_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SWHS_LST_DST` reader - NA"] +pub type CH3_SWHS_LST_DST_R = crate::BitReader; +#[doc = "Field `CH3_SWHS_LST_DST` writer - NA"] +pub type CH3_SWHS_LST_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SWHS_LST_DST_WE` writer - NA"] +pub type CH3_SWHS_LST_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch3_swhs_req_dst(&self) -> CH3_SWHS_REQ_DST_R { + CH3_SWHS_REQ_DST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch3_swhs_sglreq_dst(&self) -> CH3_SWHS_SGLREQ_DST_R { + CH3_SWHS_SGLREQ_DST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch3_swhs_lst_dst(&self) -> CH3_SWHS_LST_DST_R { + CH3_SWHS_LST_DST_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_SWHSDST0") + .field( + "ch3_swhs_req_dst", + &format_args!("{}", self.ch3_swhs_req_dst().bit()), + ) + .field( + "ch3_swhs_sglreq_dst", + &format_args!("{}", self.ch3_swhs_sglreq_dst().bit()), + ) + .field( + "ch3_swhs_lst_dst", + &format_args!("{}", self.ch3_swhs_lst_dst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_req_dst(&mut self) -> CH3_SWHS_REQ_DST_W { + CH3_SWHS_REQ_DST_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_req_dst_we(&mut self) -> CH3_SWHS_REQ_DST_WE_W { + CH3_SWHS_REQ_DST_WE_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_sglreq_dst(&mut self) -> CH3_SWHS_SGLREQ_DST_W { + CH3_SWHS_SGLREQ_DST_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_sglreq_dst_we(&mut self) -> CH3_SWHS_SGLREQ_DST_WE_W { + CH3_SWHS_SGLREQ_DST_WE_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_lst_dst(&mut self) -> CH3_SWHS_LST_DST_W { + CH3_SWHS_LST_DST_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_lst_dst_we(&mut self) -> CH3_SWHS_LST_DST_WE_W { + CH3_SWHS_LST_DST_WE_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_swhsdst0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_swhsdst0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_SWHSDST0_SPEC; +impl crate::RegisterSpec for CH3_SWHSDST0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_swhsdst0::R`](R) reader structure"] +impl crate::Readable for CH3_SWHSDST0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_swhsdst0::W`](W) writer structure"] +impl crate::Writable for CH3_SWHSDST0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_SWHSDST0 to value 0"] +impl crate::Resettable for CH3_SWHSDST0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch3_swhssrc0.rs b/esp32p4/src/dma/ch3_swhssrc0.rs new file mode 100644 index 0000000000..4d5bf48266 --- /dev/null +++ b/esp32p4/src/dma/ch3_swhssrc0.rs @@ -0,0 +1,128 @@ +#[doc = "Register `CH3_SWHSSRC0` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_SWHSSRC0` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_SWHS_REQ_SRC` reader - NA"] +pub type CH3_SWHS_REQ_SRC_R = crate::BitReader; +#[doc = "Field `CH3_SWHS_REQ_SRC` writer - NA"] +pub type CH3_SWHS_REQ_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SWHS_REQ_SRC_WE` writer - NA"] +pub type CH3_SWHS_REQ_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SWHS_SGLREQ_SRC` reader - NA"] +pub type CH3_SWHS_SGLREQ_SRC_R = crate::BitReader; +#[doc = "Field `CH3_SWHS_SGLREQ_SRC` writer - NA"] +pub type CH3_SWHS_SGLREQ_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SWHS_SGLREQ_SRC_WE` writer - NA"] +pub type CH3_SWHS_SGLREQ_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SWHS_LST_SRC` reader - NA"] +pub type CH3_SWHS_LST_SRC_R = crate::BitReader; +#[doc = "Field `CH3_SWHS_LST_SRC` writer - NA"] +pub type CH3_SWHS_LST_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SWHS_LST_SRC_WE` writer - NA"] +pub type CH3_SWHS_LST_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch3_swhs_req_src(&self) -> CH3_SWHS_REQ_SRC_R { + CH3_SWHS_REQ_SRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch3_swhs_sglreq_src(&self) -> CH3_SWHS_SGLREQ_SRC_R { + CH3_SWHS_SGLREQ_SRC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch3_swhs_lst_src(&self) -> CH3_SWHS_LST_SRC_R { + CH3_SWHS_LST_SRC_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_SWHSSRC0") + .field( + "ch3_swhs_req_src", + &format_args!("{}", self.ch3_swhs_req_src().bit()), + ) + .field( + "ch3_swhs_sglreq_src", + &format_args!("{}", self.ch3_swhs_sglreq_src().bit()), + ) + .field( + "ch3_swhs_lst_src", + &format_args!("{}", self.ch3_swhs_lst_src().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_req_src(&mut self) -> CH3_SWHS_REQ_SRC_W { + CH3_SWHS_REQ_SRC_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_req_src_we(&mut self) -> CH3_SWHS_REQ_SRC_WE_W { + CH3_SWHS_REQ_SRC_WE_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_sglreq_src(&mut self) -> CH3_SWHS_SGLREQ_SRC_W { + CH3_SWHS_SGLREQ_SRC_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_sglreq_src_we(&mut self) -> CH3_SWHS_SGLREQ_SRC_WE_W { + CH3_SWHS_SGLREQ_SRC_WE_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_lst_src(&mut self) -> CH3_SWHS_LST_SRC_W { + CH3_SWHS_LST_SRC_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_swhs_lst_src_we(&mut self) -> CH3_SWHS_LST_SRC_WE_W { + CH3_SWHS_LST_SRC_WE_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_swhssrc0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_swhssrc0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_SWHSSRC0_SPEC; +impl crate::RegisterSpec for CH3_SWHSSRC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_swhssrc0::R`](R) reader structure"] +impl crate::Readable for CH3_SWHSSRC0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_swhssrc0::W`](W) writer structure"] +impl crate::Writable for CH3_SWHSSRC0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_SWHSSRC0 to value 0"] +impl crate::Resettable for CH3_SWHSSRC0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_axi_id0.rs b/esp32p4/src/dma/ch4_axi_id0.rs new file mode 100644 index 0000000000..cd8c10e8e7 --- /dev/null +++ b/esp32p4/src/dma/ch4_axi_id0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CH4_AXI_ID0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_AXI_ID0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_AXI_READ_ID_SUFFIX` reader - NA"] +pub type CH4_AXI_READ_ID_SUFFIX_R = crate::BitReader; +#[doc = "Field `CH4_AXI_READ_ID_SUFFIX` writer - NA"] +pub type CH4_AXI_READ_ID_SUFFIX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_AXI_WRITE_ID_SUFFIX` reader - NA"] +pub type CH4_AXI_WRITE_ID_SUFFIX_R = crate::BitReader; +#[doc = "Field `CH4_AXI_WRITE_ID_SUFFIX` writer - NA"] +pub type CH4_AXI_WRITE_ID_SUFFIX_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch4_axi_read_id_suffix(&self) -> CH4_AXI_READ_ID_SUFFIX_R { + CH4_AXI_READ_ID_SUFFIX_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch4_axi_write_id_suffix(&self) -> CH4_AXI_WRITE_ID_SUFFIX_R { + CH4_AXI_WRITE_ID_SUFFIX_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_AXI_ID0") + .field( + "ch4_axi_read_id_suffix", + &format_args!("{}", self.ch4_axi_read_id_suffix().bit()), + ) + .field( + "ch4_axi_write_id_suffix", + &format_args!("{}", self.ch4_axi_write_id_suffix().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_axi_read_id_suffix(&mut self) -> CH4_AXI_READ_ID_SUFFIX_W { + CH4_AXI_READ_ID_SUFFIX_W::new(self, 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_axi_write_id_suffix(&mut self) -> CH4_AXI_WRITE_ID_SUFFIX_W { + CH4_AXI_WRITE_ID_SUFFIX_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_axi_id0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_axi_id0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_AXI_ID0_SPEC; +impl crate::RegisterSpec for CH4_AXI_ID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_axi_id0::R`](R) reader structure"] +impl crate::Readable for CH4_AXI_ID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_axi_id0::W`](W) writer structure"] +impl crate::Writable for CH4_AXI_ID0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_AXI_ID0 to value 0"] +impl crate::Resettable for CH4_AXI_ID0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_axi_qos0.rs b/esp32p4/src/dma/ch4_axi_qos0.rs new file mode 100644 index 0000000000..928495cecf --- /dev/null +++ b/esp32p4/src/dma/ch4_axi_qos0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CH4_AXI_QOS0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_AXI_QOS0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_AXI_AWQOS` reader - NA"] +pub type CH4_AXI_AWQOS_R = crate::FieldReader; +#[doc = "Field `CH4_AXI_AWQOS` writer - NA"] +pub type CH4_AXI_AWQOS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH4_AXI_ARQOS` reader - NA"] +pub type CH4_AXI_ARQOS_R = crate::FieldReader; +#[doc = "Field `CH4_AXI_ARQOS` writer - NA"] +pub type CH4_AXI_ARQOS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + pub fn ch4_axi_awqos(&self) -> CH4_AXI_AWQOS_R { + CH4_AXI_AWQOS_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - NA"] + #[inline(always)] + pub fn ch4_axi_arqos(&self) -> CH4_AXI_ARQOS_R { + CH4_AXI_ARQOS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_AXI_QOS0") + .field( + "ch4_axi_awqos", + &format_args!("{}", self.ch4_axi_awqos().bits()), + ) + .field( + "ch4_axi_arqos", + &format_args!("{}", self.ch4_axi_arqos().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_axi_awqos(&mut self) -> CH4_AXI_AWQOS_W { + CH4_AXI_AWQOS_W::new(self, 0) + } + #[doc = "Bits 4:7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_axi_arqos(&mut self) -> CH4_AXI_ARQOS_W { + CH4_AXI_ARQOS_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_axi_qos0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_axi_qos0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_AXI_QOS0_SPEC; +impl crate::RegisterSpec for CH4_AXI_QOS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_axi_qos0::R`](R) reader structure"] +impl crate::Readable for CH4_AXI_QOS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_axi_qos0::W`](W) writer structure"] +impl crate::Writable for CH4_AXI_QOS0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_AXI_QOS0 to value 0"] +impl crate::Resettable for CH4_AXI_QOS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_blk_tfr_resumereq0.rs b/esp32p4/src/dma/ch4_blk_tfr_resumereq0.rs new file mode 100644 index 0000000000..2bc1c03305 --- /dev/null +++ b/esp32p4/src/dma/ch4_blk_tfr_resumereq0.rs @@ -0,0 +1,44 @@ +#[doc = "Register `CH4_BLK_TFR_RESUMEREQ0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_BLK_TFR_RESUMEREQ` writer - NA"] +pub type CH4_BLK_TFR_RESUMEREQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_blk_tfr_resumereq( + &mut self, + ) -> CH4_BLK_TFR_RESUMEREQ_W { + CH4_BLK_TFR_RESUMEREQ_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_blk_tfr_resumereq0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_BLK_TFR_RESUMEREQ0_SPEC; +impl crate::RegisterSpec for CH4_BLK_TFR_RESUMEREQ0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch4_blk_tfr_resumereq0::W`](W) writer structure"] +impl crate::Writable for CH4_BLK_TFR_RESUMEREQ0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_BLK_TFR_RESUMEREQ0 to value 0"] +impl crate::Resettable for CH4_BLK_TFR_RESUMEREQ0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_block_ts0.rs b/esp32p4/src/dma/ch4_block_ts0.rs new file mode 100644 index 0000000000..08bca416c8 --- /dev/null +++ b/esp32p4/src/dma/ch4_block_ts0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH4_BLOCK_TS0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_BLOCK_TS0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_BLOCK_TS` reader - NA"] +pub type CH4_BLOCK_TS_R = crate::FieldReader; +#[doc = "Field `CH4_BLOCK_TS` writer - NA"] +pub type CH4_BLOCK_TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + pub fn ch4_block_ts(&self) -> CH4_BLOCK_TS_R { + CH4_BLOCK_TS_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_BLOCK_TS0") + .field( + "ch4_block_ts", + &format_args!("{}", self.ch4_block_ts().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_block_ts(&mut self) -> CH4_BLOCK_TS_W { + CH4_BLOCK_TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_block_ts0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_block_ts0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_BLOCK_TS0_SPEC; +impl crate::RegisterSpec for CH4_BLOCK_TS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_block_ts0::R`](R) reader structure"] +impl crate::Readable for CH4_BLOCK_TS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_block_ts0::W`](W) writer structure"] +impl crate::Writable for CH4_BLOCK_TS0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_BLOCK_TS0 to value 0"] +impl crate::Resettable for CH4_BLOCK_TS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_cfg0.rs b/esp32p4/src/dma/ch4_cfg0.rs new file mode 100644 index 0000000000..43e61f8ece --- /dev/null +++ b/esp32p4/src/dma/ch4_cfg0.rs @@ -0,0 +1,101 @@ +#[doc = "Register `CH4_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_SRC_MULTBLK_TYPE` reader - NA"] +pub type CH4_SRC_MULTBLK_TYPE_R = crate::FieldReader; +#[doc = "Field `CH4_SRC_MULTBLK_TYPE` writer - NA"] +pub type CH4_SRC_MULTBLK_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH4_DST_MULTBLK_TYPE` reader - NA"] +pub type CH4_DST_MULTBLK_TYPE_R = crate::FieldReader; +#[doc = "Field `CH4_DST_MULTBLK_TYPE` writer - NA"] +pub type CH4_DST_MULTBLK_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH4_RD_UID` reader - NA"] +pub type CH4_RD_UID_R = crate::FieldReader; +#[doc = "Field `CH4_WR_UID` reader - NA"] +pub type CH4_WR_UID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn ch4_src_multblk_type(&self) -> CH4_SRC_MULTBLK_TYPE_R { + CH4_SRC_MULTBLK_TYPE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - NA"] + #[inline(always)] + pub fn ch4_dst_multblk_type(&self) -> CH4_DST_MULTBLK_TYPE_R { + CH4_DST_MULTBLK_TYPE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + pub fn ch4_rd_uid(&self) -> CH4_RD_UID_R { + CH4_RD_UID_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bits 25:28 - NA"] + #[inline(always)] + pub fn ch4_wr_uid(&self) -> CH4_WR_UID_R { + CH4_WR_UID_R::new(((self.bits >> 25) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_CFG0") + .field( + "ch4_src_multblk_type", + &format_args!("{}", self.ch4_src_multblk_type().bits()), + ) + .field( + "ch4_dst_multblk_type", + &format_args!("{}", self.ch4_dst_multblk_type().bits()), + ) + .field("ch4_rd_uid", &format_args!("{}", self.ch4_rd_uid().bits())) + .field("ch4_wr_uid", &format_args!("{}", self.ch4_wr_uid().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_src_multblk_type(&mut self) -> CH4_SRC_MULTBLK_TYPE_W { + CH4_SRC_MULTBLK_TYPE_W::new(self, 0) + } + #[doc = "Bits 2:3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dst_multblk_type(&mut self) -> CH4_DST_MULTBLK_TYPE_W { + CH4_DST_MULTBLK_TYPE_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_CFG0_SPEC; +impl crate::RegisterSpec for CH4_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_cfg0::R`](R) reader structure"] +impl crate::Readable for CH4_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_cfg0::W`](W) writer structure"] +impl crate::Writable for CH4_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_CFG0 to value 0"] +impl crate::Resettable for CH4_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_cfg1.rs b/esp32p4/src/dma/ch4_cfg1.rs new file mode 100644 index 0000000000..21d4e2dc0e --- /dev/null +++ b/esp32p4/src/dma/ch4_cfg1.rs @@ -0,0 +1,237 @@ +#[doc = "Register `CH4_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_TT_FC` reader - NA"] +pub type CH4_TT_FC_R = crate::FieldReader; +#[doc = "Field `CH4_TT_FC` writer - NA"] +pub type CH4_TT_FC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH4_HS_SEL_SRC` reader - NA"] +pub type CH4_HS_SEL_SRC_R = crate::BitReader; +#[doc = "Field `CH4_HS_SEL_SRC` writer - NA"] +pub type CH4_HS_SEL_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_HS_SEL_DST` reader - NA"] +pub type CH4_HS_SEL_DST_R = crate::BitReader; +#[doc = "Field `CH4_HS_SEL_DST` writer - NA"] +pub type CH4_HS_SEL_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SRC_HWHS_POL` reader - NA"] +pub type CH4_SRC_HWHS_POL_R = crate::BitReader; +#[doc = "Field `CH4_DST_HWHS_POL` reader - NA"] +pub type CH4_DST_HWHS_POL_R = crate::BitReader; +#[doc = "Field `CH4_SRC_PER` reader - NA"] +pub type CH4_SRC_PER_R = crate::FieldReader; +#[doc = "Field `CH4_SRC_PER` writer - NA"] +pub type CH4_SRC_PER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH4_DST_PER` reader - NA"] +pub type CH4_DST_PER_R = crate::FieldReader; +#[doc = "Field `CH4_DST_PER` writer - NA"] +pub type CH4_DST_PER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH4_CH_PRIOR` reader - NA"] +pub type CH4_CH_PRIOR_R = crate::FieldReader; +#[doc = "Field `CH4_CH_PRIOR` writer - NA"] +pub type CH4_CH_PRIOR_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH4_LOCK_CH` reader - NA"] +pub type CH4_LOCK_CH_R = crate::BitReader; +#[doc = "Field `CH4_LOCK_CH_L` reader - NA"] +pub type CH4_LOCK_CH_L_R = crate::FieldReader; +#[doc = "Field `CH4_SRC_OSR_LMT` reader - NA"] +pub type CH4_SRC_OSR_LMT_R = crate::FieldReader; +#[doc = "Field `CH4_SRC_OSR_LMT` writer - NA"] +pub type CH4_SRC_OSR_LMT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH4_DST_OSR_LMT` reader - NA"] +pub type CH4_DST_OSR_LMT_R = crate::FieldReader; +#[doc = "Field `CH4_DST_OSR_LMT` writer - NA"] +pub type CH4_DST_OSR_LMT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + pub fn ch4_tt_fc(&self) -> CH4_TT_FC_R { + CH4_TT_FC_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch4_hs_sel_src(&self) -> CH4_HS_SEL_SRC_R { + CH4_HS_SEL_SRC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch4_hs_sel_dst(&self) -> CH4_HS_SEL_DST_R { + CH4_HS_SEL_DST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch4_src_hwhs_pol(&self) -> CH4_SRC_HWHS_POL_R { + CH4_SRC_HWHS_POL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch4_dst_hwhs_pol(&self) -> CH4_DST_HWHS_POL_R { + CH4_DST_HWHS_POL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:8 - NA"] + #[inline(always)] + pub fn ch4_src_per(&self) -> CH4_SRC_PER_R { + CH4_SRC_PER_R::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 12:13 - NA"] + #[inline(always)] + pub fn ch4_dst_per(&self) -> CH4_DST_PER_R { + CH4_DST_PER_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 17:19 - NA"] + #[inline(always)] + pub fn ch4_ch_prior(&self) -> CH4_CH_PRIOR_R { + CH4_CH_PRIOR_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch4_lock_ch(&self) -> CH4_LOCK_CH_R { + CH4_LOCK_CH_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:22 - NA"] + #[inline(always)] + pub fn ch4_lock_ch_l(&self) -> CH4_LOCK_CH_L_R { + CH4_LOCK_CH_L_R::new(((self.bits >> 21) & 3) as u8) + } + #[doc = "Bits 23:26 - NA"] + #[inline(always)] + pub fn ch4_src_osr_lmt(&self) -> CH4_SRC_OSR_LMT_R { + CH4_SRC_OSR_LMT_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bits 27:30 - NA"] + #[inline(always)] + pub fn ch4_dst_osr_lmt(&self) -> CH4_DST_OSR_LMT_R { + CH4_DST_OSR_LMT_R::new(((self.bits >> 27) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_CFG1") + .field("ch4_tt_fc", &format_args!("{}", self.ch4_tt_fc().bits())) + .field( + "ch4_hs_sel_src", + &format_args!("{}", self.ch4_hs_sel_src().bit()), + ) + .field( + "ch4_hs_sel_dst", + &format_args!("{}", self.ch4_hs_sel_dst().bit()), + ) + .field( + "ch4_src_hwhs_pol", + &format_args!("{}", self.ch4_src_hwhs_pol().bit()), + ) + .field( + "ch4_dst_hwhs_pol", + &format_args!("{}", self.ch4_dst_hwhs_pol().bit()), + ) + .field( + "ch4_src_per", + &format_args!("{}", self.ch4_src_per().bits()), + ) + .field( + "ch4_dst_per", + &format_args!("{}", self.ch4_dst_per().bits()), + ) + .field( + "ch4_ch_prior", + &format_args!("{}", self.ch4_ch_prior().bits()), + ) + .field("ch4_lock_ch", &format_args!("{}", self.ch4_lock_ch().bit())) + .field( + "ch4_lock_ch_l", + &format_args!("{}", self.ch4_lock_ch_l().bits()), + ) + .field( + "ch4_src_osr_lmt", + &format_args!("{}", self.ch4_src_osr_lmt().bits()), + ) + .field( + "ch4_dst_osr_lmt", + &format_args!("{}", self.ch4_dst_osr_lmt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_tt_fc(&mut self) -> CH4_TT_FC_W { + CH4_TT_FC_W::new(self, 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_hs_sel_src(&mut self) -> CH4_HS_SEL_SRC_W { + CH4_HS_SEL_SRC_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_hs_sel_dst(&mut self) -> CH4_HS_SEL_DST_W { + CH4_HS_SEL_DST_W::new(self, 4) + } + #[doc = "Bits 7:8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_src_per(&mut self) -> CH4_SRC_PER_W { + CH4_SRC_PER_W::new(self, 7) + } + #[doc = "Bits 12:13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dst_per(&mut self) -> CH4_DST_PER_W { + CH4_DST_PER_W::new(self, 12) + } + #[doc = "Bits 17:19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_ch_prior(&mut self) -> CH4_CH_PRIOR_W { + CH4_CH_PRIOR_W::new(self, 17) + } + #[doc = "Bits 23:26 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_src_osr_lmt(&mut self) -> CH4_SRC_OSR_LMT_W { + CH4_SRC_OSR_LMT_W::new(self, 23) + } + #[doc = "Bits 27:30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dst_osr_lmt(&mut self) -> CH4_DST_OSR_LMT_W { + CH4_DST_OSR_LMT_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_CFG1_SPEC; +impl crate::RegisterSpec for CH4_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_cfg1::R`](R) reader structure"] +impl crate::Readable for CH4_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_cfg1::W`](W) writer structure"] +impl crate::Writable for CH4_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_CFG1 to value 0x1b"] +impl crate::Resettable for CH4_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0x1b; +} diff --git a/esp32p4/src/dma/ch4_ctl0.rs b/esp32p4/src/dma/ch4_ctl0.rs new file mode 100644 index 0000000000..5b691e75df --- /dev/null +++ b/esp32p4/src/dma/ch4_ctl0.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CH4_CTL0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_CTL0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_SMS` reader - NA"] +pub type CH4_SMS_R = crate::BitReader; +#[doc = "Field `CH4_SMS` writer - NA"] +pub type CH4_SMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_DMS` reader - NA"] +pub type CH4_DMS_R = crate::BitReader; +#[doc = "Field `CH4_DMS` writer - NA"] +pub type CH4_DMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SINC` reader - NA"] +pub type CH4_SINC_R = crate::BitReader; +#[doc = "Field `CH4_SINC` writer - NA"] +pub type CH4_SINC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_DINC` reader - NA"] +pub type CH4_DINC_R = crate::BitReader; +#[doc = "Field `CH4_DINC` writer - NA"] +pub type CH4_DINC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SRC_TR_WIDTH` reader - NA"] +pub type CH4_SRC_TR_WIDTH_R = crate::FieldReader; +#[doc = "Field `CH4_SRC_TR_WIDTH` writer - NA"] +pub type CH4_SRC_TR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH4_DST_TR_WIDTH` reader - NA"] +pub type CH4_DST_TR_WIDTH_R = crate::FieldReader; +#[doc = "Field `CH4_DST_TR_WIDTH` writer - NA"] +pub type CH4_DST_TR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH4_SRC_MSIZE` reader - NA"] +pub type CH4_SRC_MSIZE_R = crate::FieldReader; +#[doc = "Field `CH4_SRC_MSIZE` writer - NA"] +pub type CH4_SRC_MSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH4_DST_MSIZE` reader - NA"] +pub type CH4_DST_MSIZE_R = crate::FieldReader; +#[doc = "Field `CH4_DST_MSIZE` writer - NA"] +pub type CH4_DST_MSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH4_AR_CACHE` reader - NA"] +pub type CH4_AR_CACHE_R = crate::FieldReader; +#[doc = "Field `CH4_AR_CACHE` writer - NA"] +pub type CH4_AR_CACHE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH4_AW_CACHE` reader - NA"] +pub type CH4_AW_CACHE_R = crate::FieldReader; +#[doc = "Field `CH4_AW_CACHE` writer - NA"] +pub type CH4_AW_CACHE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CH4_NONPOSTED_LASTWRITE_EN` reader - NA"] +pub type CH4_NONPOSTED_LASTWRITE_EN_R = crate::BitReader; +#[doc = "Field `CH4_NONPOSTED_LASTWRITE_EN` writer - NA"] +pub type CH4_NONPOSTED_LASTWRITE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch4_sms(&self) -> CH4_SMS_R { + CH4_SMS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch4_dms(&self) -> CH4_DMS_R { + CH4_DMS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch4_sinc(&self) -> CH4_SINC_R { + CH4_SINC_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch4_dinc(&self) -> CH4_DINC_R { + CH4_DINC_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - NA"] + #[inline(always)] + pub fn ch4_src_tr_width(&self) -> CH4_SRC_TR_WIDTH_R { + CH4_SRC_TR_WIDTH_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 11:13 - NA"] + #[inline(always)] + pub fn ch4_dst_tr_width(&self) -> CH4_DST_TR_WIDTH_R { + CH4_DST_TR_WIDTH_R::new(((self.bits >> 11) & 7) as u8) + } + #[doc = "Bits 14:17 - NA"] + #[inline(always)] + pub fn ch4_src_msize(&self) -> CH4_SRC_MSIZE_R { + CH4_SRC_MSIZE_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + pub fn ch4_dst_msize(&self) -> CH4_DST_MSIZE_R { + CH4_DST_MSIZE_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bits 22:25 - NA"] + #[inline(always)] + pub fn ch4_ar_cache(&self) -> CH4_AR_CACHE_R { + CH4_AR_CACHE_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:29 - NA"] + #[inline(always)] + pub fn ch4_aw_cache(&self) -> CH4_AW_CACHE_R { + CH4_AW_CACHE_R::new(((self.bits >> 26) & 0x0f) as u8) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch4_nonposted_lastwrite_en(&self) -> CH4_NONPOSTED_LASTWRITE_EN_R { + CH4_NONPOSTED_LASTWRITE_EN_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_CTL0") + .field("ch4_sms", &format_args!("{}", self.ch4_sms().bit())) + .field("ch4_dms", &format_args!("{}", self.ch4_dms().bit())) + .field("ch4_sinc", &format_args!("{}", self.ch4_sinc().bit())) + .field("ch4_dinc", &format_args!("{}", self.ch4_dinc().bit())) + .field( + "ch4_src_tr_width", + &format_args!("{}", self.ch4_src_tr_width().bits()), + ) + .field( + "ch4_dst_tr_width", + &format_args!("{}", self.ch4_dst_tr_width().bits()), + ) + .field( + "ch4_src_msize", + &format_args!("{}", self.ch4_src_msize().bits()), + ) + .field( + "ch4_dst_msize", + &format_args!("{}", self.ch4_dst_msize().bits()), + ) + .field( + "ch4_ar_cache", + &format_args!("{}", self.ch4_ar_cache().bits()), + ) + .field( + "ch4_aw_cache", + &format_args!("{}", self.ch4_aw_cache().bits()), + ) + .field( + "ch4_nonposted_lastwrite_en", + &format_args!("{}", self.ch4_nonposted_lastwrite_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_sms(&mut self) -> CH4_SMS_W { + CH4_SMS_W::new(self, 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dms(&mut self) -> CH4_DMS_W { + CH4_DMS_W::new(self, 2) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_sinc(&mut self) -> CH4_SINC_W { + CH4_SINC_W::new(self, 4) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dinc(&mut self) -> CH4_DINC_W { + CH4_DINC_W::new(self, 6) + } + #[doc = "Bits 8:10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_src_tr_width(&mut self) -> CH4_SRC_TR_WIDTH_W { + CH4_SRC_TR_WIDTH_W::new(self, 8) + } + #[doc = "Bits 11:13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dst_tr_width(&mut self) -> CH4_DST_TR_WIDTH_W { + CH4_DST_TR_WIDTH_W::new(self, 11) + } + #[doc = "Bits 14:17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_src_msize(&mut self) -> CH4_SRC_MSIZE_W { + CH4_SRC_MSIZE_W::new(self, 14) + } + #[doc = "Bits 18:21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dst_msize(&mut self) -> CH4_DST_MSIZE_W { + CH4_DST_MSIZE_W::new(self, 18) + } + #[doc = "Bits 22:25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_ar_cache(&mut self) -> CH4_AR_CACHE_W { + CH4_AR_CACHE_W::new(self, 22) + } + #[doc = "Bits 26:29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_aw_cache(&mut self) -> CH4_AW_CACHE_W { + CH4_AW_CACHE_W::new(self, 26) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_nonposted_lastwrite_en(&mut self) -> CH4_NONPOSTED_LASTWRITE_EN_W { + CH4_NONPOSTED_LASTWRITE_EN_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_ctl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_CTL0_SPEC; +impl crate::RegisterSpec for CH4_CTL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_ctl0::R`](R) reader structure"] +impl crate::Readable for CH4_CTL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_ctl0::W`](W) writer structure"] +impl crate::Writable for CH4_CTL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_CTL0 to value 0x1200"] +impl crate::Resettable for CH4_CTL0_SPEC { + const RESET_VALUE: Self::Ux = 0x1200; +} diff --git a/esp32p4/src/dma/ch4_ctl1.rs b/esp32p4/src/dma/ch4_ctl1.rs new file mode 100644 index 0000000000..0a04bd8ca0 --- /dev/null +++ b/esp32p4/src/dma/ch4_ctl1.rs @@ -0,0 +1,250 @@ +#[doc = "Register `CH4_CTL1` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_CTL1` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_AR_PROT` reader - NA"] +pub type CH4_AR_PROT_R = crate::FieldReader; +#[doc = "Field `CH4_AR_PROT` writer - NA"] +pub type CH4_AR_PROT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH4_AW_PROT` reader - NA"] +pub type CH4_AW_PROT_R = crate::FieldReader; +#[doc = "Field `CH4_AW_PROT` writer - NA"] +pub type CH4_AW_PROT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CH4_ARLEN_EN` reader - NA"] +pub type CH4_ARLEN_EN_R = crate::BitReader; +#[doc = "Field `CH4_ARLEN_EN` writer - NA"] +pub type CH4_ARLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ARLEN` reader - NA"] +pub type CH4_ARLEN_R = crate::FieldReader; +#[doc = "Field `CH4_ARLEN` writer - NA"] +pub type CH4_ARLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CH4_AWLEN_EN` reader - NA"] +pub type CH4_AWLEN_EN_R = crate::BitReader; +#[doc = "Field `CH4_AWLEN_EN` writer - NA"] +pub type CH4_AWLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_AWLEN` reader - NA"] +pub type CH4_AWLEN_R = crate::FieldReader; +#[doc = "Field `CH4_AWLEN` writer - NA"] +pub type CH4_AWLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CH4_SRC_STAT_EN` reader - NA"] +pub type CH4_SRC_STAT_EN_R = crate::BitReader; +#[doc = "Field `CH4_SRC_STAT_EN` writer - NA"] +pub type CH4_SRC_STAT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_DST_STAT_EN` reader - NA"] +pub type CH4_DST_STAT_EN_R = crate::BitReader; +#[doc = "Field `CH4_DST_STAT_EN` writer - NA"] +pub type CH4_DST_STAT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_IOC_BLKTFR` reader - NA"] +pub type CH4_IOC_BLKTFR_R = crate::BitReader; +#[doc = "Field `CH4_IOC_BLKTFR` writer - NA"] +pub type CH4_IOC_BLKTFR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SHADOWREG_OR_LLI_LAST` reader - NA"] +pub type CH4_SHADOWREG_OR_LLI_LAST_R = crate::BitReader; +#[doc = "Field `CH4_SHADOWREG_OR_LLI_LAST` writer - NA"] +pub type CH4_SHADOWREG_OR_LLI_LAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SHADOWREG_OR_LLI_VALID` reader - NA"] +pub type CH4_SHADOWREG_OR_LLI_VALID_R = crate::BitReader; +#[doc = "Field `CH4_SHADOWREG_OR_LLI_VALID` writer - NA"] +pub type CH4_SHADOWREG_OR_LLI_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + pub fn ch4_ar_prot(&self) -> CH4_AR_PROT_R { + CH4_AR_PROT_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - NA"] + #[inline(always)] + pub fn ch4_aw_prot(&self) -> CH4_AW_PROT_R { + CH4_AW_PROT_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch4_arlen_en(&self) -> CH4_ARLEN_EN_R { + CH4_ARLEN_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:14 - NA"] + #[inline(always)] + pub fn ch4_arlen(&self) -> CH4_ARLEN_R { + CH4_ARLEN_R::new(((self.bits >> 7) & 0xff) as u8) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn ch4_awlen_en(&self) -> CH4_AWLEN_EN_R { + CH4_AWLEN_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn ch4_awlen(&self) -> CH4_AWLEN_R { + CH4_AWLEN_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + pub fn ch4_src_stat_en(&self) -> CH4_SRC_STAT_EN_R { + CH4_SRC_STAT_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch4_dst_stat_en(&self) -> CH4_DST_STAT_EN_R { + CH4_DST_STAT_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - NA"] + #[inline(always)] + pub fn ch4_ioc_blktfr(&self) -> CH4_IOC_BLKTFR_R { + CH4_IOC_BLKTFR_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch4_shadowreg_or_lli_last(&self) -> CH4_SHADOWREG_OR_LLI_LAST_R { + CH4_SHADOWREG_OR_LLI_LAST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch4_shadowreg_or_lli_valid(&self) -> CH4_SHADOWREG_OR_LLI_VALID_R { + CH4_SHADOWREG_OR_LLI_VALID_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_CTL1") + .field( + "ch4_ar_prot", + &format_args!("{}", self.ch4_ar_prot().bits()), + ) + .field( + "ch4_aw_prot", + &format_args!("{}", self.ch4_aw_prot().bits()), + ) + .field( + "ch4_arlen_en", + &format_args!("{}", self.ch4_arlen_en().bit()), + ) + .field("ch4_arlen", &format_args!("{}", self.ch4_arlen().bits())) + .field( + "ch4_awlen_en", + &format_args!("{}", self.ch4_awlen_en().bit()), + ) + .field("ch4_awlen", &format_args!("{}", self.ch4_awlen().bits())) + .field( + "ch4_src_stat_en", + &format_args!("{}", self.ch4_src_stat_en().bit()), + ) + .field( + "ch4_dst_stat_en", + &format_args!("{}", self.ch4_dst_stat_en().bit()), + ) + .field( + "ch4_ioc_blktfr", + &format_args!("{}", self.ch4_ioc_blktfr().bit()), + ) + .field( + "ch4_shadowreg_or_lli_last", + &format_args!("{}", self.ch4_shadowreg_or_lli_last().bit()), + ) + .field( + "ch4_shadowreg_or_lli_valid", + &format_args!("{}", self.ch4_shadowreg_or_lli_valid().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_ar_prot(&mut self) -> CH4_AR_PROT_W { + CH4_AR_PROT_W::new(self, 0) + } + #[doc = "Bits 3:5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_aw_prot(&mut self) -> CH4_AW_PROT_W { + CH4_AW_PROT_W::new(self, 3) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_arlen_en(&mut self) -> CH4_ARLEN_EN_W { + CH4_ARLEN_EN_W::new(self, 6) + } + #[doc = "Bits 7:14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_arlen(&mut self) -> CH4_ARLEN_W { + CH4_ARLEN_W::new(self, 7) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_awlen_en(&mut self) -> CH4_AWLEN_EN_W { + CH4_AWLEN_EN_W::new(self, 15) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_awlen(&mut self) -> CH4_AWLEN_W { + CH4_AWLEN_W::new(self, 16) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_src_stat_en(&mut self) -> CH4_SRC_STAT_EN_W { + CH4_SRC_STAT_EN_W::new(self, 24) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dst_stat_en(&mut self) -> CH4_DST_STAT_EN_W { + CH4_DST_STAT_EN_W::new(self, 25) + } + #[doc = "Bit 26 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_ioc_blktfr(&mut self) -> CH4_IOC_BLKTFR_W { + CH4_IOC_BLKTFR_W::new(self, 26) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_shadowreg_or_lli_last(&mut self) -> CH4_SHADOWREG_OR_LLI_LAST_W { + CH4_SHADOWREG_OR_LLI_LAST_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_shadowreg_or_lli_valid(&mut self) -> CH4_SHADOWREG_OR_LLI_VALID_W { + CH4_SHADOWREG_OR_LLI_VALID_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_ctl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_CTL1_SPEC; +impl crate::RegisterSpec for CH4_CTL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_ctl1::R`](R) reader structure"] +impl crate::Readable for CH4_CTL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_ctl1::W`](W) writer structure"] +impl crate::Writable for CH4_CTL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_CTL1 to value 0"] +impl crate::Resettable for CH4_CTL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_dar0.rs b/esp32p4/src/dma/ch4_dar0.rs new file mode 100644 index 0000000000..ea5e6b363b --- /dev/null +++ b/esp32p4/src/dma/ch4_dar0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH4_DAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_DAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_DAR0` reader - NA"] +pub type CH4_DAR0_R = crate::FieldReader; +#[doc = "Field `CH4_DAR0` writer - NA"] +pub type CH4_DAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch4_dar0(&self) -> CH4_DAR0_R { + CH4_DAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_DAR0") + .field("ch4_dar0", &format_args!("{}", self.ch4_dar0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dar0(&mut self) -> CH4_DAR0_W { + CH4_DAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_dar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_DAR0_SPEC; +impl crate::RegisterSpec for CH4_DAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_dar0::R`](R) reader structure"] +impl crate::Readable for CH4_DAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_dar0::W`](W) writer structure"] +impl crate::Writable for CH4_DAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_DAR0 to value 0"] +impl crate::Resettable for CH4_DAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_dar1.rs b/esp32p4/src/dma/ch4_dar1.rs new file mode 100644 index 0000000000..cbd35d8153 --- /dev/null +++ b/esp32p4/src/dma/ch4_dar1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH4_DAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_DAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_DAR1` reader - NA"] +pub type CH4_DAR1_R = crate::FieldReader; +#[doc = "Field `CH4_DAR1` writer - NA"] +pub type CH4_DAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch4_dar1(&self) -> CH4_DAR1_R { + CH4_DAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_DAR1") + .field("ch4_dar1", &format_args!("{}", self.ch4_dar1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dar1(&mut self) -> CH4_DAR1_W { + CH4_DAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_dar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_DAR1_SPEC; +impl crate::RegisterSpec for CH4_DAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_dar1::R`](R) reader structure"] +impl crate::Readable for CH4_DAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_dar1::W`](W) writer structure"] +impl crate::Writable for CH4_DAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_DAR1 to value 0"] +impl crate::Resettable for CH4_DAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_dstat0.rs b/esp32p4/src/dma/ch4_dstat0.rs new file mode 100644 index 0000000000..28a97fb799 --- /dev/null +++ b/esp32p4/src/dma/ch4_dstat0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `CH4_DSTAT0` reader"] +pub type R = crate::R; +#[doc = "Field `CH4_DSTAT` reader - NA"] +pub type CH4_DSTAT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch4_dstat(&self) -> CH4_DSTAT_R { + CH4_DSTAT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_DSTAT0") + .field("ch4_dstat", &format_args!("{}", self.ch4_dstat().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_dstat0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_DSTAT0_SPEC; +impl crate::RegisterSpec for CH4_DSTAT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_dstat0::R`](R) reader structure"] +impl crate::Readable for CH4_DSTAT0_SPEC {} +#[doc = "`reset()` method sets CH4_DSTAT0 to value 0"] +impl crate::Resettable for CH4_DSTAT0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_dstatar0.rs b/esp32p4/src/dma/ch4_dstatar0.rs new file mode 100644 index 0000000000..9646fadb9e --- /dev/null +++ b/esp32p4/src/dma/ch4_dstatar0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH4_DSTATAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_DSTATAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_DSTATAR0` reader - NA"] +pub type CH4_DSTATAR0_R = crate::FieldReader; +#[doc = "Field `CH4_DSTATAR0` writer - NA"] +pub type CH4_DSTATAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch4_dstatar0(&self) -> CH4_DSTATAR0_R { + CH4_DSTATAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_DSTATAR0") + .field( + "ch4_dstatar0", + &format_args!("{}", self.ch4_dstatar0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dstatar0(&mut self) -> CH4_DSTATAR0_W { + CH4_DSTATAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_dstatar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dstatar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_DSTATAR0_SPEC; +impl crate::RegisterSpec for CH4_DSTATAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_dstatar0::R`](R) reader structure"] +impl crate::Readable for CH4_DSTATAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_dstatar0::W`](W) writer structure"] +impl crate::Writable for CH4_DSTATAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_DSTATAR0 to value 0"] +impl crate::Resettable for CH4_DSTATAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_dstatar1.rs b/esp32p4/src/dma/ch4_dstatar1.rs new file mode 100644 index 0000000000..6066276987 --- /dev/null +++ b/esp32p4/src/dma/ch4_dstatar1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH4_DSTATAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_DSTATAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_DSTATAR1` reader - NA"] +pub type CH4_DSTATAR1_R = crate::FieldReader; +#[doc = "Field `CH4_DSTATAR1` writer - NA"] +pub type CH4_DSTATAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch4_dstatar1(&self) -> CH4_DSTATAR1_R { + CH4_DSTATAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_DSTATAR1") + .field( + "ch4_dstatar1", + &format_args!("{}", self.ch4_dstatar1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_dstatar1(&mut self) -> CH4_DSTATAR1_W { + CH4_DSTATAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_dstatar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_dstatar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_DSTATAR1_SPEC; +impl crate::RegisterSpec for CH4_DSTATAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_dstatar1::R`](R) reader structure"] +impl crate::Readable for CH4_DSTATAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_dstatar1::W`](W) writer structure"] +impl crate::Writable for CH4_DSTATAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_DSTATAR1 to value 0"] +impl crate::Resettable for CH4_DSTATAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_intclear0.rs b/esp32p4/src/dma/ch4_intclear0.rs new file mode 100644 index 0000000000..9f51ed97b8 --- /dev/null +++ b/esp32p4/src/dma/ch4_intclear0.rs @@ -0,0 +1,294 @@ +#[doc = "Register `CH4_INTCLEAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT` writer - NA"] +pub type CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_DMA_TFR_DONE_INTSTAT` writer - NA"] +pub type CH4_CLEAR_DMA_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SRC_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_DST_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH4_CLEAR_DST_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SRC_DEC_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SRC_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_DST_DEC_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_DST_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SRC_SLV_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SRC_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_DST_SLV_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_DST_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT` writer - NA"] +pub type CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT` writer - NA"] +pub type CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_CH_SUSPENDED_INTSTAT` writer - NA"] +pub type CH4_CLEAR_CH_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_CH_DISABLED_INTSTAT` writer - NA"] +pub type CH4_CLEAR_CH_DISABLED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_CH_ABORTED_INTSTAT` writer - NA"] +pub type CH4_CLEAR_CH_ABORTED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_block_tfr_done_intstat( + &mut self, + ) -> CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_W { + CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_dma_tfr_done_intstat( + &mut self, + ) -> CH4_CLEAR_DMA_TFR_DONE_INTSTAT_W { + CH4_CLEAR_DMA_TFR_DONE_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_src_transcomp_intstat( + &mut self, + ) -> CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_W { + CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_dst_transcomp_intstat( + &mut self, + ) -> CH4_CLEAR_DST_TRANSCOMP_INTSTAT_W { + CH4_CLEAR_DST_TRANSCOMP_INTSTAT_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_src_dec_err_intstat( + &mut self, + ) -> CH4_CLEAR_SRC_DEC_ERR_INTSTAT_W { + CH4_CLEAR_SRC_DEC_ERR_INTSTAT_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_dst_dec_err_intstat( + &mut self, + ) -> CH4_CLEAR_DST_DEC_ERR_INTSTAT_W { + CH4_CLEAR_DST_DEC_ERR_INTSTAT_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_src_slv_err_intstat( + &mut self, + ) -> CH4_CLEAR_SRC_SLV_ERR_INTSTAT_W { + CH4_CLEAR_SRC_SLV_ERR_INTSTAT_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_dst_slv_err_intstat( + &mut self, + ) -> CH4_CLEAR_DST_SLV_ERR_INTSTAT_W { + CH4_CLEAR_DST_SLV_ERR_INTSTAT_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_lli_rd_dec_err_intstat( + &mut self, + ) -> CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W { + CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_lli_wr_dec_err_intstat( + &mut self, + ) -> CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W { + CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_lli_rd_slv_err_intstat( + &mut self, + ) -> CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W { + CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_lli_wr_slv_err_intstat( + &mut self, + ) -> CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W { + CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_shadowreg_or_lli_invalid_err_intstat( + &mut self, + ) -> CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W { + CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_slvif_multiblktype_err_intstat( + &mut self, + ) -> CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W { + CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_slvif_dec_err_intstat( + &mut self, + ) -> CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_W { + CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_slvif_wr2ro_err_intstat( + &mut self, + ) -> CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W { + CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_slvif_rd2rwo_err_intstat( + &mut self, + ) -> CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W { + CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_slvif_wronchen_err_intstat( + &mut self, + ) -> CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W { + CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_slvif_shadowreg_wron_valid_err_intstat( + &mut self, + ) -> CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W { + CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_slvif_wronhold_err_intstat( + &mut self, + ) -> CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W { + CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_W::new(self, 21) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_slvif_wrparity_err_intstat( + &mut self, + ) -> CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W { + CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_W::new(self, 25) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_ch_lock_cleared_intstat( + &mut self, + ) -> CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_W { + CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_ch_src_suspended_intstat( + &mut self, + ) -> CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W { + CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_ch_suspended_intstat( + &mut self, + ) -> CH4_CLEAR_CH_SUSPENDED_INTSTAT_W { + CH4_CLEAR_CH_SUSPENDED_INTSTAT_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_ch_disabled_intstat( + &mut self, + ) -> CH4_CLEAR_CH_DISABLED_INTSTAT_W { + CH4_CLEAR_CH_DISABLED_INTSTAT_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_ch_aborted_intstat( + &mut self, + ) -> CH4_CLEAR_CH_ABORTED_INTSTAT_W { + CH4_CLEAR_CH_ABORTED_INTSTAT_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_intclear0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_INTCLEAR0_SPEC; +impl crate::RegisterSpec for CH4_INTCLEAR0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch4_intclear0::W`](W) writer structure"] +impl crate::Writable for CH4_INTCLEAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_INTCLEAR0 to value 0"] +impl crate::Resettable for CH4_INTCLEAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_intclear1.rs b/esp32p4/src/dma/ch4_intclear1.rs new file mode 100644 index 0000000000..1290bdc242 --- /dev/null +++ b/esp32p4/src/dma/ch4_intclear1.rs @@ -0,0 +1,74 @@ +#[doc = "Register `CH4_INTCLEAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` writer - NA"] +pub type CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_ecc_prot_chmem_correrr_intstat( + &mut self, + ) -> CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W { + CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_ecc_prot_chmem_uncorrerr_intstat( + &mut self, + ) -> CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W { + CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_ecc_prot_uidmem_correrr_intstat( + &mut self, + ) -> CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W { + CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_clear_ecc_prot_uidmem_uncorrerr_intstat( + &mut self, + ) -> CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W { + CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_intclear1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_INTCLEAR1_SPEC; +impl crate::RegisterSpec for CH4_INTCLEAR1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch4_intclear1::W`](W) writer structure"] +impl crate::Writable for CH4_INTCLEAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_INTCLEAR1 to value 0"] +impl crate::Resettable for CH4_INTCLEAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_intsignal_enable0.rs b/esp32p4/src/dma/ch4_intsignal_enable0.rs new file mode 100644 index 0000000000..9ac421a926 --- /dev/null +++ b/esp32p4/src/dma/ch4_intsignal_enable0.rs @@ -0,0 +1,606 @@ +#[doc = "Register `CH4_INTSIGNAL_ENABLE0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_INTSIGNAL_ENABLE0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_DST_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_DST_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_DST_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_DST_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_CH_SUSPENDED_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_SUSPENDED_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_CH_DISABLED_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_CH_DISABLED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_DISABLED_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_CH_DISABLED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_CH_ABORTED_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_CH_ABORTED_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_ABORTED_INTSIGNAL` writer - NA"] +pub type CH4_ENABLE_CH_ABORTED_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch4_enable_block_tfr_done_intsignal(&self) -> CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R { + CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch4_enable_dma_tfr_done_intsignal(&self) -> CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_R { + CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch4_enable_src_transcomp_intsignal(&self) -> CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R { + CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch4_enable_dst_transcomp_intsignal(&self) -> CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_R { + CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch4_enable_src_dec_err_intsignal(&self) -> CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_R { + CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch4_enable_dst_dec_err_intsignal(&self) -> CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_R { + CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch4_enable_src_slv_err_intsignal(&self) -> CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_R { + CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch4_enable_dst_slv_err_intsignal(&self) -> CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_R { + CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch4_enable_lli_rd_dec_err_intsignal(&self) -> CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R { + CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch4_enable_lli_wr_dec_err_intsignal(&self) -> CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R { + CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch4_enable_lli_rd_slv_err_intsignal(&self) -> CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R { + CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch4_enable_lli_wr_slv_err_intsignal(&self) -> CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R { + CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch4_enable_shadowreg_or_lli_invalid_err_intsignal( + &self, + ) -> CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R { + CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_multiblktype_err_intsignal( + &self, + ) -> CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R { + CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_dec_err_intsignal(&self) -> CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R { + CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_wr2ro_err_intsignal(&self) -> CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R { + CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_rd2rwo_err_intsignal(&self) -> CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R { + CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_wronchen_err_intsignal( + &self, + ) -> CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R { + CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_shadowreg_wron_valid_err_intsignal( + &self, + ) -> CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R { + CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_wronhold_err_intsignal( + &self, + ) -> CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R { + CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_wrparity_err_intsignal( + &self, + ) -> CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R { + CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch4_enable_ch_lock_cleared_intsignal(&self) -> CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R { + CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch4_enable_ch_src_suspended_intsignal(&self) -> CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R { + CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch4_enable_ch_suspended_intsignal(&self) -> CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_R { + CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch4_enable_ch_disabled_intsignal(&self) -> CH4_ENABLE_CH_DISABLED_INTSIGNAL_R { + CH4_ENABLE_CH_DISABLED_INTSIGNAL_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch4_enable_ch_aborted_intsignal(&self) -> CH4_ENABLE_CH_ABORTED_INTSIGNAL_R { + CH4_ENABLE_CH_ABORTED_INTSIGNAL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_INTSIGNAL_ENABLE0") + .field( + "ch4_enable_block_tfr_done_intsignal", + &format_args!("{}", self.ch4_enable_block_tfr_done_intsignal().bit()), + ) + .field( + "ch4_enable_dma_tfr_done_intsignal", + &format_args!("{}", self.ch4_enable_dma_tfr_done_intsignal().bit()), + ) + .field( + "ch4_enable_src_transcomp_intsignal", + &format_args!("{}", self.ch4_enable_src_transcomp_intsignal().bit()), + ) + .field( + "ch4_enable_dst_transcomp_intsignal", + &format_args!("{}", self.ch4_enable_dst_transcomp_intsignal().bit()), + ) + .field( + "ch4_enable_src_dec_err_intsignal", + &format_args!("{}", self.ch4_enable_src_dec_err_intsignal().bit()), + ) + .field( + "ch4_enable_dst_dec_err_intsignal", + &format_args!("{}", self.ch4_enable_dst_dec_err_intsignal().bit()), + ) + .field( + "ch4_enable_src_slv_err_intsignal", + &format_args!("{}", self.ch4_enable_src_slv_err_intsignal().bit()), + ) + .field( + "ch4_enable_dst_slv_err_intsignal", + &format_args!("{}", self.ch4_enable_dst_slv_err_intsignal().bit()), + ) + .field( + "ch4_enable_lli_rd_dec_err_intsignal", + &format_args!("{}", self.ch4_enable_lli_rd_dec_err_intsignal().bit()), + ) + .field( + "ch4_enable_lli_wr_dec_err_intsignal", + &format_args!("{}", self.ch4_enable_lli_wr_dec_err_intsignal().bit()), + ) + .field( + "ch4_enable_lli_rd_slv_err_intsignal", + &format_args!("{}", self.ch4_enable_lli_rd_slv_err_intsignal().bit()), + ) + .field( + "ch4_enable_lli_wr_slv_err_intsignal", + &format_args!("{}", self.ch4_enable_lli_wr_slv_err_intsignal().bit()), + ) + .field( + "ch4_enable_shadowreg_or_lli_invalid_err_intsignal", + &format_args!( + "{}", + self.ch4_enable_shadowreg_or_lli_invalid_err_intsignal() + .bit() + ), + ) + .field( + "ch4_enable_slvif_multiblktype_err_intsignal", + &format_args!( + "{}", + self.ch4_enable_slvif_multiblktype_err_intsignal().bit() + ), + ) + .field( + "ch4_enable_slvif_dec_err_intsignal", + &format_args!("{}", self.ch4_enable_slvif_dec_err_intsignal().bit()), + ) + .field( + "ch4_enable_slvif_wr2ro_err_intsignal", + &format_args!("{}", self.ch4_enable_slvif_wr2ro_err_intsignal().bit()), + ) + .field( + "ch4_enable_slvif_rd2rwo_err_intsignal", + &format_args!("{}", self.ch4_enable_slvif_rd2rwo_err_intsignal().bit()), + ) + .field( + "ch4_enable_slvif_wronchen_err_intsignal", + &format_args!("{}", self.ch4_enable_slvif_wronchen_err_intsignal().bit()), + ) + .field( + "ch4_enable_slvif_shadowreg_wron_valid_err_intsignal", + &format_args!( + "{}", + self.ch4_enable_slvif_shadowreg_wron_valid_err_intsignal() + .bit() + ), + ) + .field( + "ch4_enable_slvif_wronhold_err_intsignal", + &format_args!("{}", self.ch4_enable_slvif_wronhold_err_intsignal().bit()), + ) + .field( + "ch4_enable_slvif_wrparity_err_intsignal", + &format_args!("{}", self.ch4_enable_slvif_wrparity_err_intsignal().bit()), + ) + .field( + "ch4_enable_ch_lock_cleared_intsignal", + &format_args!("{}", self.ch4_enable_ch_lock_cleared_intsignal().bit()), + ) + .field( + "ch4_enable_ch_src_suspended_intsignal", + &format_args!("{}", self.ch4_enable_ch_src_suspended_intsignal().bit()), + ) + .field( + "ch4_enable_ch_suspended_intsignal", + &format_args!("{}", self.ch4_enable_ch_suspended_intsignal().bit()), + ) + .field( + "ch4_enable_ch_disabled_intsignal", + &format_args!("{}", self.ch4_enable_ch_disabled_intsignal().bit()), + ) + .field( + "ch4_enable_ch_aborted_intsignal", + &format_args!("{}", self.ch4_enable_ch_aborted_intsignal().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_block_tfr_done_intsignal( + &mut self, + ) -> CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W { + CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_dma_tfr_done_intsignal( + &mut self, + ) -> CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_W { + CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_src_transcomp_intsignal( + &mut self, + ) -> CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W { + CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_dst_transcomp_intsignal( + &mut self, + ) -> CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_W { + CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_src_dec_err_intsignal( + &mut self, + ) -> CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_W { + CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_dst_dec_err_intsignal( + &mut self, + ) -> CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_W { + CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_src_slv_err_intsignal( + &mut self, + ) -> CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_W { + CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_dst_slv_err_intsignal( + &mut self, + ) -> CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_W { + CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_lli_rd_dec_err_intsignal( + &mut self, + ) -> CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W { + CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_lli_wr_dec_err_intsignal( + &mut self, + ) -> CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W { + CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_lli_rd_slv_err_intsignal( + &mut self, + ) -> CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W { + CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_lli_wr_slv_err_intsignal( + &mut self, + ) -> CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W { + CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_shadowreg_or_lli_invalid_err_intsignal( + &mut self, + ) -> CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W { + CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_multiblktype_err_intsignal( + &mut self, + ) -> CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W { + CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_dec_err_intsignal( + &mut self, + ) -> CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W { + CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_wr2ro_err_intsignal( + &mut self, + ) -> CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W { + CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_rd2rwo_err_intsignal( + &mut self, + ) -> CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W { + CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_wronchen_err_intsignal( + &mut self, + ) -> CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W { + CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_shadowreg_wron_valid_err_intsignal( + &mut self, + ) -> CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W { + CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_wronhold_err_intsignal( + &mut self, + ) -> CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W { + CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_W::new(self, 21) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_ch_lock_cleared_intsignal( + &mut self, + ) -> CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W { + CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_ch_src_suspended_intsignal( + &mut self, + ) -> CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W { + CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_ch_suspended_intsignal( + &mut self, + ) -> CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_W { + CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_ch_disabled_intsignal( + &mut self, + ) -> CH4_ENABLE_CH_DISABLED_INTSIGNAL_W { + CH4_ENABLE_CH_DISABLED_INTSIGNAL_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_ch_aborted_intsignal( + &mut self, + ) -> CH4_ENABLE_CH_ABORTED_INTSIGNAL_W { + CH4_ENABLE_CH_ABORTED_INTSIGNAL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intsignal_enable0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_intsignal_enable0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_INTSIGNAL_ENABLE0_SPEC; +impl crate::RegisterSpec for CH4_INTSIGNAL_ENABLE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_intsignal_enable0::R`](R) reader structure"] +impl crate::Readable for CH4_INTSIGNAL_ENABLE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_intsignal_enable0::W`](W) writer structure"] +impl crate::Writable for CH4_INTSIGNAL_ENABLE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_INTSIGNAL_ENABLE0 to value 0xfa3f_7ffb"] +impl crate::Resettable for CH4_INTSIGNAL_ENABLE0_SPEC { + const RESET_VALUE: Self::Ux = 0xfa3f_7ffb; +} diff --git a/esp32p4/src/dma/ch4_intsignal_enable1.rs b/esp32p4/src/dma/ch4_intsignal_enable1.rs new file mode 100644 index 0000000000..3ec192d334 --- /dev/null +++ b/esp32p4/src/dma/ch4_intsignal_enable1.rs @@ -0,0 +1,92 @@ +#[doc = "Register `CH4_INTSIGNAL_ENABLE1` reader"] +pub type R = crate::R; +#[doc = "Field `CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL` reader - NA"] +pub type CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch4_enable_ecc_prot_chmem_correrr_intsignal( + &self, + ) -> CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R { + CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch4_enable_ecc_prot_chmem_uncorrerr_intsignal( + &self, + ) -> CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R { + CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch4_enable_ecc_prot_uidmem_correrr_intsignal( + &self, + ) -> CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R { + CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal( + &self, + ) -> CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R { + CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_INTSIGNAL_ENABLE1") + .field( + "ch4_enable_ecc_prot_chmem_correrr_intsignal", + &format_args!( + "{}", + self.ch4_enable_ecc_prot_chmem_correrr_intsignal().bit() + ), + ) + .field( + "ch4_enable_ecc_prot_chmem_uncorrerr_intsignal", + &format_args!( + "{}", + self.ch4_enable_ecc_prot_chmem_uncorrerr_intsignal().bit() + ), + ) + .field( + "ch4_enable_ecc_prot_uidmem_correrr_intsignal", + &format_args!( + "{}", + self.ch4_enable_ecc_prot_uidmem_correrr_intsignal().bit() + ), + ) + .field( + "ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal", + &format_args!( + "{}", + self.ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal().bit() + ), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intsignal_enable1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_INTSIGNAL_ENABLE1_SPEC; +impl crate::RegisterSpec for CH4_INTSIGNAL_ENABLE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_intsignal_enable1::R`](R) reader structure"] +impl crate::Readable for CH4_INTSIGNAL_ENABLE1_SPEC {} +#[doc = "`reset()` method sets CH4_INTSIGNAL_ENABLE1 to value 0x0f"] +impl crate::Resettable for CH4_INTSIGNAL_ENABLE1_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/dma/ch4_intstatus0.rs b/esp32p4/src/dma/ch4_intstatus0.rs new file mode 100644 index 0000000000..f6eab8ee75 --- /dev/null +++ b/esp32p4/src/dma/ch4_intstatus0.rs @@ -0,0 +1,321 @@ +#[doc = "Register `CH4_INTSTATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `CH4_BLOCK_TFR_DONE_INTSTAT` reader - NA"] +pub type CH4_BLOCK_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_DMA_TFR_DONE_INTSTAT` reader - NA"] +pub type CH4_DMA_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SRC_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH4_SRC_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_DST_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH4_DST_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SRC_DEC_ERR_INTSTAT` reader - NA"] +pub type CH4_SRC_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_DST_DEC_ERR_INTSTAT` reader - NA"] +pub type CH4_DST_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SRC_SLV_ERR_INTSTAT` reader - NA"] +pub type CH4_SRC_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_DST_SLV_ERR_INTSTAT` reader - NA"] +pub type CH4_DST_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_LLI_RD_DEC_ERR_INTSTAT` reader - NA"] +pub type CH4_LLI_RD_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_LLI_WR_DEC_ERR_INTSTAT` reader - NA"] +pub type CH4_LLI_WR_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_LLI_RD_SLV_ERR_INTSTAT` reader - NA"] +pub type CH4_LLI_RD_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_LLI_WR_SLV_ERR_INTSTAT` reader - NA"] +pub type CH4_LLI_WR_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` reader - NA"] +pub type CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` reader - NA"] +pub type CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SLVIF_DEC_ERR_INTSTAT` reader - NA"] +pub type CH4_SLVIF_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SLVIF_WR2RO_ERR_INTSTAT` reader - NA"] +pub type CH4_SLVIF_WR2RO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SLVIF_RD2RWO_ERR_INTSTAT` reader - NA"] +pub type CH4_SLVIF_RD2RWO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SLVIF_WRONCHEN_ERR_INTSTAT` reader - NA"] +pub type CH4_SLVIF_WRONCHEN_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` reader - NA"] +pub type CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SLVIF_WRONHOLD_ERR_INTSTAT` reader - NA"] +pub type CH4_SLVIF_WRONHOLD_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_SLVIF_WRPARITY_ERR_INTSTAT` reader - NA"] +pub type CH4_SLVIF_WRPARITY_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_CH_LOCK_CLEARED_INTSTAT` reader - NA"] +pub type CH4_CH_LOCK_CLEARED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_CH_SRC_SUSPENDED_INTSTAT` reader - NA"] +pub type CH4_CH_SRC_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_CH_SUSPENDED_INTSTAT` reader - NA"] +pub type CH4_CH_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_CH_DISABLED_INTSTAT` reader - NA"] +pub type CH4_CH_DISABLED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_CH_ABORTED_INTSTAT` reader - NA"] +pub type CH4_CH_ABORTED_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch4_block_tfr_done_intstat(&self) -> CH4_BLOCK_TFR_DONE_INTSTAT_R { + CH4_BLOCK_TFR_DONE_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch4_dma_tfr_done_intstat(&self) -> CH4_DMA_TFR_DONE_INTSTAT_R { + CH4_DMA_TFR_DONE_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch4_src_transcomp_intstat(&self) -> CH4_SRC_TRANSCOMP_INTSTAT_R { + CH4_SRC_TRANSCOMP_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch4_dst_transcomp_intstat(&self) -> CH4_DST_TRANSCOMP_INTSTAT_R { + CH4_DST_TRANSCOMP_INTSTAT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch4_src_dec_err_intstat(&self) -> CH4_SRC_DEC_ERR_INTSTAT_R { + CH4_SRC_DEC_ERR_INTSTAT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch4_dst_dec_err_intstat(&self) -> CH4_DST_DEC_ERR_INTSTAT_R { + CH4_DST_DEC_ERR_INTSTAT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch4_src_slv_err_intstat(&self) -> CH4_SRC_SLV_ERR_INTSTAT_R { + CH4_SRC_SLV_ERR_INTSTAT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch4_dst_slv_err_intstat(&self) -> CH4_DST_SLV_ERR_INTSTAT_R { + CH4_DST_SLV_ERR_INTSTAT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch4_lli_rd_dec_err_intstat(&self) -> CH4_LLI_RD_DEC_ERR_INTSTAT_R { + CH4_LLI_RD_DEC_ERR_INTSTAT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch4_lli_wr_dec_err_intstat(&self) -> CH4_LLI_WR_DEC_ERR_INTSTAT_R { + CH4_LLI_WR_DEC_ERR_INTSTAT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch4_lli_rd_slv_err_intstat(&self) -> CH4_LLI_RD_SLV_ERR_INTSTAT_R { + CH4_LLI_RD_SLV_ERR_INTSTAT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch4_lli_wr_slv_err_intstat(&self) -> CH4_LLI_WR_SLV_ERR_INTSTAT_R { + CH4_LLI_WR_SLV_ERR_INTSTAT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch4_shadowreg_or_lli_invalid_err_intstat( + &self, + ) -> CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R { + CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch4_slvif_multiblktype_err_intstat(&self) -> CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R { + CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch4_slvif_dec_err_intstat(&self) -> CH4_SLVIF_DEC_ERR_INTSTAT_R { + CH4_SLVIF_DEC_ERR_INTSTAT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch4_slvif_wr2ro_err_intstat(&self) -> CH4_SLVIF_WR2RO_ERR_INTSTAT_R { + CH4_SLVIF_WR2RO_ERR_INTSTAT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch4_slvif_rd2rwo_err_intstat(&self) -> CH4_SLVIF_RD2RWO_ERR_INTSTAT_R { + CH4_SLVIF_RD2RWO_ERR_INTSTAT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch4_slvif_wronchen_err_intstat(&self) -> CH4_SLVIF_WRONCHEN_ERR_INTSTAT_R { + CH4_SLVIF_WRONCHEN_ERR_INTSTAT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch4_slvif_shadowreg_wron_valid_err_intstat( + &self, + ) -> CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R { + CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch4_slvif_wronhold_err_intstat(&self) -> CH4_SLVIF_WRONHOLD_ERR_INTSTAT_R { + CH4_SLVIF_WRONHOLD_ERR_INTSTAT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch4_slvif_wrparity_err_intstat(&self) -> CH4_SLVIF_WRPARITY_ERR_INTSTAT_R { + CH4_SLVIF_WRPARITY_ERR_INTSTAT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch4_ch_lock_cleared_intstat(&self) -> CH4_CH_LOCK_CLEARED_INTSTAT_R { + CH4_CH_LOCK_CLEARED_INTSTAT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch4_ch_src_suspended_intstat(&self) -> CH4_CH_SRC_SUSPENDED_INTSTAT_R { + CH4_CH_SRC_SUSPENDED_INTSTAT_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch4_ch_suspended_intstat(&self) -> CH4_CH_SUSPENDED_INTSTAT_R { + CH4_CH_SUSPENDED_INTSTAT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch4_ch_disabled_intstat(&self) -> CH4_CH_DISABLED_INTSTAT_R { + CH4_CH_DISABLED_INTSTAT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch4_ch_aborted_intstat(&self) -> CH4_CH_ABORTED_INTSTAT_R { + CH4_CH_ABORTED_INTSTAT_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_INTSTATUS0") + .field( + "ch4_block_tfr_done_intstat", + &format_args!("{}", self.ch4_block_tfr_done_intstat().bit()), + ) + .field( + "ch4_dma_tfr_done_intstat", + &format_args!("{}", self.ch4_dma_tfr_done_intstat().bit()), + ) + .field( + "ch4_src_transcomp_intstat", + &format_args!("{}", self.ch4_src_transcomp_intstat().bit()), + ) + .field( + "ch4_dst_transcomp_intstat", + &format_args!("{}", self.ch4_dst_transcomp_intstat().bit()), + ) + .field( + "ch4_src_dec_err_intstat", + &format_args!("{}", self.ch4_src_dec_err_intstat().bit()), + ) + .field( + "ch4_dst_dec_err_intstat", + &format_args!("{}", self.ch4_dst_dec_err_intstat().bit()), + ) + .field( + "ch4_src_slv_err_intstat", + &format_args!("{}", self.ch4_src_slv_err_intstat().bit()), + ) + .field( + "ch4_dst_slv_err_intstat", + &format_args!("{}", self.ch4_dst_slv_err_intstat().bit()), + ) + .field( + "ch4_lli_rd_dec_err_intstat", + &format_args!("{}", self.ch4_lli_rd_dec_err_intstat().bit()), + ) + .field( + "ch4_lli_wr_dec_err_intstat", + &format_args!("{}", self.ch4_lli_wr_dec_err_intstat().bit()), + ) + .field( + "ch4_lli_rd_slv_err_intstat", + &format_args!("{}", self.ch4_lli_rd_slv_err_intstat().bit()), + ) + .field( + "ch4_lli_wr_slv_err_intstat", + &format_args!("{}", self.ch4_lli_wr_slv_err_intstat().bit()), + ) + .field( + "ch4_shadowreg_or_lli_invalid_err_intstat", + &format_args!("{}", self.ch4_shadowreg_or_lli_invalid_err_intstat().bit()), + ) + .field( + "ch4_slvif_multiblktype_err_intstat", + &format_args!("{}", self.ch4_slvif_multiblktype_err_intstat().bit()), + ) + .field( + "ch4_slvif_dec_err_intstat", + &format_args!("{}", self.ch4_slvif_dec_err_intstat().bit()), + ) + .field( + "ch4_slvif_wr2ro_err_intstat", + &format_args!("{}", self.ch4_slvif_wr2ro_err_intstat().bit()), + ) + .field( + "ch4_slvif_rd2rwo_err_intstat", + &format_args!("{}", self.ch4_slvif_rd2rwo_err_intstat().bit()), + ) + .field( + "ch4_slvif_wronchen_err_intstat", + &format_args!("{}", self.ch4_slvif_wronchen_err_intstat().bit()), + ) + .field( + "ch4_slvif_shadowreg_wron_valid_err_intstat", + &format_args!( + "{}", + self.ch4_slvif_shadowreg_wron_valid_err_intstat().bit() + ), + ) + .field( + "ch4_slvif_wronhold_err_intstat", + &format_args!("{}", self.ch4_slvif_wronhold_err_intstat().bit()), + ) + .field( + "ch4_slvif_wrparity_err_intstat", + &format_args!("{}", self.ch4_slvif_wrparity_err_intstat().bit()), + ) + .field( + "ch4_ch_lock_cleared_intstat", + &format_args!("{}", self.ch4_ch_lock_cleared_intstat().bit()), + ) + .field( + "ch4_ch_src_suspended_intstat", + &format_args!("{}", self.ch4_ch_src_suspended_intstat().bit()), + ) + .field( + "ch4_ch_suspended_intstat", + &format_args!("{}", self.ch4_ch_suspended_intstat().bit()), + ) + .field( + "ch4_ch_disabled_intstat", + &format_args!("{}", self.ch4_ch_disabled_intstat().bit()), + ) + .field( + "ch4_ch_aborted_intstat", + &format_args!("{}", self.ch4_ch_aborted_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intstatus0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_INTSTATUS0_SPEC; +impl crate::RegisterSpec for CH4_INTSTATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_intstatus0::R`](R) reader structure"] +impl crate::Readable for CH4_INTSTATUS0_SPEC {} +#[doc = "`reset()` method sets CH4_INTSTATUS0 to value 0"] +impl crate::Resettable for CH4_INTSTATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_intstatus1.rs b/esp32p4/src/dma/ch4_intstatus1.rs new file mode 100644 index 0000000000..7a6ead11fa --- /dev/null +++ b/esp32p4/src/dma/ch4_intstatus1.rs @@ -0,0 +1,72 @@ +#[doc = "Register `CH4_INTSTATUS1` reader"] +pub type R = crate::R; +#[doc = "Field `CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch4_ecc_prot_chmem_correrr_intstat(&self) -> CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_R { + CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch4_ecc_prot_chmem_uncorrerr_intstat(&self) -> CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R { + CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch4_ecc_prot_uidmem_correrr_intstat(&self) -> CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R { + CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch4_ecc_prot_uidmem_uncorrerr_intstat(&self) -> CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R { + CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_INTSTATUS1") + .field( + "ch4_ecc_prot_chmem_correrr_intstat", + &format_args!("{}", self.ch4_ecc_prot_chmem_correrr_intstat().bit()), + ) + .field( + "ch4_ecc_prot_chmem_uncorrerr_intstat", + &format_args!("{}", self.ch4_ecc_prot_chmem_uncorrerr_intstat().bit()), + ) + .field( + "ch4_ecc_prot_uidmem_correrr_intstat", + &format_args!("{}", self.ch4_ecc_prot_uidmem_correrr_intstat().bit()), + ) + .field( + "ch4_ecc_prot_uidmem_uncorrerr_intstat", + &format_args!("{}", self.ch4_ecc_prot_uidmem_uncorrerr_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intstatus1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_INTSTATUS1_SPEC; +impl crate::RegisterSpec for CH4_INTSTATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_intstatus1::R`](R) reader structure"] +impl crate::Readable for CH4_INTSTATUS1_SPEC {} +#[doc = "`reset()` method sets CH4_INTSTATUS1 to value 0"] +impl crate::Resettable for CH4_INTSTATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_intstatus_enable0.rs b/esp32p4/src/dma/ch4_intstatus_enable0.rs new file mode 100644 index 0000000000..446589fc06 --- /dev/null +++ b/esp32p4/src/dma/ch4_intstatus_enable0.rs @@ -0,0 +1,596 @@ +#[doc = "Register `CH4_INTSTATUS_ENABLE0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_INTSTATUS_ENABLE0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT` reader - NA"] +pub type CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT` writer - NA"] +pub type CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_DMA_TFR_DONE_INTSTAT` reader - NA"] +pub type CH4_ENABLE_DMA_TFR_DONE_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_DMA_TFR_DONE_INTSTAT` writer - NA"] +pub type CH4_ENABLE_DMA_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SRC_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SRC_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_DST_TRANSCOMP_INTSTAT` reader - NA"] +pub type CH4_ENABLE_DST_TRANSCOMP_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_DST_TRANSCOMP_INTSTAT` writer - NA"] +pub type CH4_ENABLE_DST_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SRC_DEC_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SRC_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SRC_DEC_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_SRC_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_DST_DEC_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_DST_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_DST_DEC_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_DST_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SRC_SLV_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SRC_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SRC_SLV_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_SRC_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_DST_SLV_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_DST_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_DST_SLV_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_DST_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT` writer - NA"] +pub type CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT` reader - NA"] +pub type CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT` writer - NA"] +pub type CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT` reader - NA"] +pub type CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT` writer - NA"] +pub type CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_CH_SUSPENDED_INTSTAT` reader - NA"] +pub type CH4_ENABLE_CH_SUSPENDED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_SUSPENDED_INTSTAT` writer - NA"] +pub type CH4_ENABLE_CH_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_CH_DISABLED_INTSTAT` reader - NA"] +pub type CH4_ENABLE_CH_DISABLED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_DISABLED_INTSTAT` writer - NA"] +pub type CH4_ENABLE_CH_DISABLED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ENABLE_CH_ABORTED_INTSTAT` reader - NA"] +pub type CH4_ENABLE_CH_ABORTED_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_CH_ABORTED_INTSTAT` writer - NA"] +pub type CH4_ENABLE_CH_ABORTED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch4_enable_block_tfr_done_intstat(&self) -> CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_R { + CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch4_enable_dma_tfr_done_intstat(&self) -> CH4_ENABLE_DMA_TFR_DONE_INTSTAT_R { + CH4_ENABLE_DMA_TFR_DONE_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch4_enable_src_transcomp_intstat(&self) -> CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_R { + CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch4_enable_dst_transcomp_intstat(&self) -> CH4_ENABLE_DST_TRANSCOMP_INTSTAT_R { + CH4_ENABLE_DST_TRANSCOMP_INTSTAT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ch4_enable_src_dec_err_intstat(&self) -> CH4_ENABLE_SRC_DEC_ERR_INTSTAT_R { + CH4_ENABLE_SRC_DEC_ERR_INTSTAT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ch4_enable_dst_dec_err_intstat(&self) -> CH4_ENABLE_DST_DEC_ERR_INTSTAT_R { + CH4_ENABLE_DST_DEC_ERR_INTSTAT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ch4_enable_src_slv_err_intstat(&self) -> CH4_ENABLE_SRC_SLV_ERR_INTSTAT_R { + CH4_ENABLE_SRC_SLV_ERR_INTSTAT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ch4_enable_dst_slv_err_intstat(&self) -> CH4_ENABLE_DST_SLV_ERR_INTSTAT_R { + CH4_ENABLE_DST_SLV_ERR_INTSTAT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ch4_enable_lli_rd_dec_err_intstat(&self) -> CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R { + CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ch4_enable_lli_wr_dec_err_intstat(&self) -> CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R { + CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ch4_enable_lli_rd_slv_err_intstat(&self) -> CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R { + CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ch4_enable_lli_wr_slv_err_intstat(&self) -> CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R { + CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ch4_enable_shadowreg_or_lli_invalid_err_intstat( + &self, + ) -> CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R { + CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_multiblktype_err_intstat( + &self, + ) -> CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R { + CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_dec_err_intstat(&self) -> CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_R { + CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_wr2ro_err_intstat(&self) -> CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R { + CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_rd2rwo_err_intstat(&self) -> CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R { + CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_wronchen_err_intstat(&self) -> CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R { + CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_shadowreg_wron_valid_err_intstat( + &self, + ) -> CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R { + CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_wronhold_err_intstat(&self) -> CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R { + CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + pub fn ch4_enable_slvif_wrparity_err_intstat(&self) -> CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R { + CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + pub fn ch4_enable_ch_lock_cleared_intstat(&self) -> CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_R { + CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + pub fn ch4_enable_ch_src_suspended_intstat(&self) -> CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R { + CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + pub fn ch4_enable_ch_suspended_intstat(&self) -> CH4_ENABLE_CH_SUSPENDED_INTSTAT_R { + CH4_ENABLE_CH_SUSPENDED_INTSTAT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn ch4_enable_ch_disabled_intstat(&self) -> CH4_ENABLE_CH_DISABLED_INTSTAT_R { + CH4_ENABLE_CH_DISABLED_INTSTAT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn ch4_enable_ch_aborted_intstat(&self) -> CH4_ENABLE_CH_ABORTED_INTSTAT_R { + CH4_ENABLE_CH_ABORTED_INTSTAT_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_INTSTATUS_ENABLE0") + .field( + "ch4_enable_block_tfr_done_intstat", + &format_args!("{}", self.ch4_enable_block_tfr_done_intstat().bit()), + ) + .field( + "ch4_enable_dma_tfr_done_intstat", + &format_args!("{}", self.ch4_enable_dma_tfr_done_intstat().bit()), + ) + .field( + "ch4_enable_src_transcomp_intstat", + &format_args!("{}", self.ch4_enable_src_transcomp_intstat().bit()), + ) + .field( + "ch4_enable_dst_transcomp_intstat", + &format_args!("{}", self.ch4_enable_dst_transcomp_intstat().bit()), + ) + .field( + "ch4_enable_src_dec_err_intstat", + &format_args!("{}", self.ch4_enable_src_dec_err_intstat().bit()), + ) + .field( + "ch4_enable_dst_dec_err_intstat", + &format_args!("{}", self.ch4_enable_dst_dec_err_intstat().bit()), + ) + .field( + "ch4_enable_src_slv_err_intstat", + &format_args!("{}", self.ch4_enable_src_slv_err_intstat().bit()), + ) + .field( + "ch4_enable_dst_slv_err_intstat", + &format_args!("{}", self.ch4_enable_dst_slv_err_intstat().bit()), + ) + .field( + "ch4_enable_lli_rd_dec_err_intstat", + &format_args!("{}", self.ch4_enable_lli_rd_dec_err_intstat().bit()), + ) + .field( + "ch4_enable_lli_wr_dec_err_intstat", + &format_args!("{}", self.ch4_enable_lli_wr_dec_err_intstat().bit()), + ) + .field( + "ch4_enable_lli_rd_slv_err_intstat", + &format_args!("{}", self.ch4_enable_lli_rd_slv_err_intstat().bit()), + ) + .field( + "ch4_enable_lli_wr_slv_err_intstat", + &format_args!("{}", self.ch4_enable_lli_wr_slv_err_intstat().bit()), + ) + .field( + "ch4_enable_shadowreg_or_lli_invalid_err_intstat", + &format_args!( + "{}", + self.ch4_enable_shadowreg_or_lli_invalid_err_intstat().bit() + ), + ) + .field( + "ch4_enable_slvif_multiblktype_err_intstat", + &format_args!("{}", self.ch4_enable_slvif_multiblktype_err_intstat().bit()), + ) + .field( + "ch4_enable_slvif_dec_err_intstat", + &format_args!("{}", self.ch4_enable_slvif_dec_err_intstat().bit()), + ) + .field( + "ch4_enable_slvif_wr2ro_err_intstat", + &format_args!("{}", self.ch4_enable_slvif_wr2ro_err_intstat().bit()), + ) + .field( + "ch4_enable_slvif_rd2rwo_err_intstat", + &format_args!("{}", self.ch4_enable_slvif_rd2rwo_err_intstat().bit()), + ) + .field( + "ch4_enable_slvif_wronchen_err_intstat", + &format_args!("{}", self.ch4_enable_slvif_wronchen_err_intstat().bit()), + ) + .field( + "ch4_enable_slvif_shadowreg_wron_valid_err_intstat", + &format_args!( + "{}", + self.ch4_enable_slvif_shadowreg_wron_valid_err_intstat() + .bit() + ), + ) + .field( + "ch4_enable_slvif_wronhold_err_intstat", + &format_args!("{}", self.ch4_enable_slvif_wronhold_err_intstat().bit()), + ) + .field( + "ch4_enable_slvif_wrparity_err_intstat", + &format_args!("{}", self.ch4_enable_slvif_wrparity_err_intstat().bit()), + ) + .field( + "ch4_enable_ch_lock_cleared_intstat", + &format_args!("{}", self.ch4_enable_ch_lock_cleared_intstat().bit()), + ) + .field( + "ch4_enable_ch_src_suspended_intstat", + &format_args!("{}", self.ch4_enable_ch_src_suspended_intstat().bit()), + ) + .field( + "ch4_enable_ch_suspended_intstat", + &format_args!("{}", self.ch4_enable_ch_suspended_intstat().bit()), + ) + .field( + "ch4_enable_ch_disabled_intstat", + &format_args!("{}", self.ch4_enable_ch_disabled_intstat().bit()), + ) + .field( + "ch4_enable_ch_aborted_intstat", + &format_args!("{}", self.ch4_enable_ch_aborted_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_block_tfr_done_intstat( + &mut self, + ) -> CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_W { + CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_dma_tfr_done_intstat( + &mut self, + ) -> CH4_ENABLE_DMA_TFR_DONE_INTSTAT_W { + CH4_ENABLE_DMA_TFR_DONE_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_src_transcomp_intstat( + &mut self, + ) -> CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_W { + CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_dst_transcomp_intstat( + &mut self, + ) -> CH4_ENABLE_DST_TRANSCOMP_INTSTAT_W { + CH4_ENABLE_DST_TRANSCOMP_INTSTAT_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_src_dec_err_intstat( + &mut self, + ) -> CH4_ENABLE_SRC_DEC_ERR_INTSTAT_W { + CH4_ENABLE_SRC_DEC_ERR_INTSTAT_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_dst_dec_err_intstat( + &mut self, + ) -> CH4_ENABLE_DST_DEC_ERR_INTSTAT_W { + CH4_ENABLE_DST_DEC_ERR_INTSTAT_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_src_slv_err_intstat( + &mut self, + ) -> CH4_ENABLE_SRC_SLV_ERR_INTSTAT_W { + CH4_ENABLE_SRC_SLV_ERR_INTSTAT_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_dst_slv_err_intstat( + &mut self, + ) -> CH4_ENABLE_DST_SLV_ERR_INTSTAT_W { + CH4_ENABLE_DST_SLV_ERR_INTSTAT_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_lli_rd_dec_err_intstat( + &mut self, + ) -> CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W { + CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_lli_wr_dec_err_intstat( + &mut self, + ) -> CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W { + CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_lli_rd_slv_err_intstat( + &mut self, + ) -> CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W { + CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_lli_wr_slv_err_intstat( + &mut self, + ) -> CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W { + CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_shadowreg_or_lli_invalid_err_intstat( + &mut self, + ) -> CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W { + CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_multiblktype_err_intstat( + &mut self, + ) -> CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W { + CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_dec_err_intstat( + &mut self, + ) -> CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_W { + CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_wr2ro_err_intstat( + &mut self, + ) -> CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W { + CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_rd2rwo_err_intstat( + &mut self, + ) -> CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W { + CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_wronchen_err_intstat( + &mut self, + ) -> CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W { + CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_shadowreg_wron_valid_err_intstat( + &mut self, + ) -> CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W { + CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W::new(self, 20) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_slvif_wronhold_err_intstat( + &mut self, + ) -> CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W { + CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W::new(self, 21) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_ch_lock_cleared_intstat( + &mut self, + ) -> CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_W { + CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_W::new(self, 27) + } + #[doc = "Bit 28 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_ch_src_suspended_intstat( + &mut self, + ) -> CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W { + CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W::new(self, 28) + } + #[doc = "Bit 29 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_ch_suspended_intstat( + &mut self, + ) -> CH4_ENABLE_CH_SUSPENDED_INTSTAT_W { + CH4_ENABLE_CH_SUSPENDED_INTSTAT_W::new(self, 29) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_ch_disabled_intstat( + &mut self, + ) -> CH4_ENABLE_CH_DISABLED_INTSTAT_W { + CH4_ENABLE_CH_DISABLED_INTSTAT_W::new(self, 30) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_enable_ch_aborted_intstat( + &mut self, + ) -> CH4_ENABLE_CH_ABORTED_INTSTAT_W { + CH4_ENABLE_CH_ABORTED_INTSTAT_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intstatus_enable0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_intstatus_enable0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_INTSTATUS_ENABLE0_SPEC; +impl crate::RegisterSpec for CH4_INTSTATUS_ENABLE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_intstatus_enable0::R`](R) reader structure"] +impl crate::Readable for CH4_INTSTATUS_ENABLE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_intstatus_enable0::W`](W) writer structure"] +impl crate::Writable for CH4_INTSTATUS_ENABLE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_INTSTATUS_ENABLE0 to value 0xfa3f_7ffb"] +impl crate::Resettable for CH4_INTSTATUS_ENABLE0_SPEC { + const RESET_VALUE: Self::Ux = 0xfa3f_7ffb; +} diff --git a/esp32p4/src/dma/ch4_intstatus_enable1.rs b/esp32p4/src/dma/ch4_intstatus_enable1.rs new file mode 100644 index 0000000000..33c09cb17f --- /dev/null +++ b/esp32p4/src/dma/ch4_intstatus_enable1.rs @@ -0,0 +1,89 @@ +#[doc = "Register `CH4_INTSTATUS_ENABLE1` reader"] +pub type R = crate::R; +#[doc = "Field `CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT` reader - NA"] +pub type CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch4_enable_ecc_prot_chmem_correrr_intstat( + &self, + ) -> CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R { + CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch4_enable_ecc_prot_chmem_uncorrerr_intstat( + &self, + ) -> CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R { + CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch4_enable_ecc_prot_uidmem_correrr_intstat( + &self, + ) -> CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R { + CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch4_enable_ecc_prot_uidmem_uncorrerr_intstat( + &self, + ) -> CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R { + CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_INTSTATUS_ENABLE1") + .field( + "ch4_enable_ecc_prot_chmem_correrr_intstat", + &format_args!("{}", self.ch4_enable_ecc_prot_chmem_correrr_intstat().bit()), + ) + .field( + "ch4_enable_ecc_prot_chmem_uncorrerr_intstat", + &format_args!( + "{}", + self.ch4_enable_ecc_prot_chmem_uncorrerr_intstat().bit() + ), + ) + .field( + "ch4_enable_ecc_prot_uidmem_correrr_intstat", + &format_args!( + "{}", + self.ch4_enable_ecc_prot_uidmem_correrr_intstat().bit() + ), + ) + .field( + "ch4_enable_ecc_prot_uidmem_uncorrerr_intstat", + &format_args!( + "{}", + self.ch4_enable_ecc_prot_uidmem_uncorrerr_intstat().bit() + ), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_intstatus_enable1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_INTSTATUS_ENABLE1_SPEC; +impl crate::RegisterSpec for CH4_INTSTATUS_ENABLE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_intstatus_enable1::R`](R) reader structure"] +impl crate::Readable for CH4_INTSTATUS_ENABLE1_SPEC {} +#[doc = "`reset()` method sets CH4_INTSTATUS_ENABLE1 to value 0x0f"] +impl crate::Resettable for CH4_INTSTATUS_ENABLE1_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/dma/ch4_llp0.rs b/esp32p4/src/dma/ch4_llp0.rs new file mode 100644 index 0000000000..3212ea11b8 --- /dev/null +++ b/esp32p4/src/dma/ch4_llp0.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CH4_LLP0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_LLP0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_LMS` reader - NA"] +pub type CH4_LMS_R = crate::BitReader; +#[doc = "Field `CH4_LMS` writer - NA"] +pub type CH4_LMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_LOC0` reader - NA"] +pub type CH4_LOC0_R = crate::FieldReader; +#[doc = "Field `CH4_LOC0` writer - NA"] +pub type CH4_LOC0_W<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch4_lms(&self) -> CH4_LMS_R { + CH4_LMS_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 6:31 - NA"] + #[inline(always)] + pub fn ch4_loc0(&self) -> CH4_LOC0_R { + CH4_LOC0_R::new((self.bits >> 6) & 0x03ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_LLP0") + .field("ch4_lms", &format_args!("{}", self.ch4_lms().bit())) + .field("ch4_loc0", &format_args!("{}", self.ch4_loc0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_lms(&mut self) -> CH4_LMS_W { + CH4_LMS_W::new(self, 0) + } + #[doc = "Bits 6:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_loc0(&mut self) -> CH4_LOC0_W { + CH4_LOC0_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_llp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_llp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_LLP0_SPEC; +impl crate::RegisterSpec for CH4_LLP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_llp0::R`](R) reader structure"] +impl crate::Readable for CH4_LLP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_llp0::W`](W) writer structure"] +impl crate::Writable for CH4_LLP0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_LLP0 to value 0"] +impl crate::Resettable for CH4_LLP0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_llp1.rs b/esp32p4/src/dma/ch4_llp1.rs new file mode 100644 index 0000000000..26b8263145 --- /dev/null +++ b/esp32p4/src/dma/ch4_llp1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH4_LLP1` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_LLP1` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_LOC1` reader - NA"] +pub type CH4_LOC1_R = crate::FieldReader; +#[doc = "Field `CH4_LOC1` writer - NA"] +pub type CH4_LOC1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch4_loc1(&self) -> CH4_LOC1_R { + CH4_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_LLP1") + .field("ch4_loc1", &format_args!("{}", self.ch4_loc1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_loc1(&mut self) -> CH4_LOC1_W { + CH4_LOC1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_llp1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_llp1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_LLP1_SPEC; +impl crate::RegisterSpec for CH4_LLP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_llp1::R`](R) reader structure"] +impl crate::Readable for CH4_LLP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_llp1::W`](W) writer structure"] +impl crate::Writable for CH4_LLP1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_LLP1 to value 0"] +impl crate::Resettable for CH4_LLP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_sar0.rs b/esp32p4/src/dma/ch4_sar0.rs new file mode 100644 index 0000000000..5bbce2d8a3 --- /dev/null +++ b/esp32p4/src/dma/ch4_sar0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH4_SAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_SAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_SAR0` reader - NA"] +pub type CH4_SAR0_R = crate::FieldReader; +#[doc = "Field `CH4_SAR0` writer - NA"] +pub type CH4_SAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch4_sar0(&self) -> CH4_SAR0_R { + CH4_SAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_SAR0") + .field("ch4_sar0", &format_args!("{}", self.ch4_sar0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_sar0(&mut self) -> CH4_SAR0_W { + CH4_SAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_sar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_sar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_SAR0_SPEC; +impl crate::RegisterSpec for CH4_SAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_sar0::R`](R) reader structure"] +impl crate::Readable for CH4_SAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_sar0::W`](W) writer structure"] +impl crate::Writable for CH4_SAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_SAR0 to value 0"] +impl crate::Resettable for CH4_SAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_sar1.rs b/esp32p4/src/dma/ch4_sar1.rs new file mode 100644 index 0000000000..385f0b434d --- /dev/null +++ b/esp32p4/src/dma/ch4_sar1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH4_SAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_SAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_SAR1` reader - NA"] +pub type CH4_SAR1_R = crate::FieldReader; +#[doc = "Field `CH4_SAR1` writer - NA"] +pub type CH4_SAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch4_sar1(&self) -> CH4_SAR1_R { + CH4_SAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_SAR1") + .field("ch4_sar1", &format_args!("{}", self.ch4_sar1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_sar1(&mut self) -> CH4_SAR1_W { + CH4_SAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_sar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_sar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_SAR1_SPEC; +impl crate::RegisterSpec for CH4_SAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_sar1::R`](R) reader structure"] +impl crate::Readable for CH4_SAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_sar1::W`](W) writer structure"] +impl crate::Writable for CH4_SAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_SAR1 to value 0"] +impl crate::Resettable for CH4_SAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_sstat0.rs b/esp32p4/src/dma/ch4_sstat0.rs new file mode 100644 index 0000000000..54cd468b1d --- /dev/null +++ b/esp32p4/src/dma/ch4_sstat0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `CH4_SSTAT0` reader"] +pub type R = crate::R; +#[doc = "Field `CH4_SSTAT` reader - NA"] +pub type CH4_SSTAT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch4_sstat(&self) -> CH4_SSTAT_R { + CH4_SSTAT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_SSTAT0") + .field("ch4_sstat", &format_args!("{}", self.ch4_sstat().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_sstat0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_SSTAT0_SPEC; +impl crate::RegisterSpec for CH4_SSTAT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_sstat0::R`](R) reader structure"] +impl crate::Readable for CH4_SSTAT0_SPEC {} +#[doc = "`reset()` method sets CH4_SSTAT0 to value 0"] +impl crate::Resettable for CH4_SSTAT0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_sstatar0.rs b/esp32p4/src/dma/ch4_sstatar0.rs new file mode 100644 index 0000000000..c87cfaacd5 --- /dev/null +++ b/esp32p4/src/dma/ch4_sstatar0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH4_SSTATAR0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_SSTATAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_SSTATAR0` reader - NA"] +pub type CH4_SSTATAR0_R = crate::FieldReader; +#[doc = "Field `CH4_SSTATAR0` writer - NA"] +pub type CH4_SSTATAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch4_sstatar0(&self) -> CH4_SSTATAR0_R { + CH4_SSTATAR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_SSTATAR0") + .field( + "ch4_sstatar0", + &format_args!("{}", self.ch4_sstatar0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_sstatar0(&mut self) -> CH4_SSTATAR0_W { + CH4_SSTATAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_sstatar0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_sstatar0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_SSTATAR0_SPEC; +impl crate::RegisterSpec for CH4_SSTATAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_sstatar0::R`](R) reader structure"] +impl crate::Readable for CH4_SSTATAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_sstatar0::W`](W) writer structure"] +impl crate::Writable for CH4_SSTATAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_SSTATAR0 to value 0"] +impl crate::Resettable for CH4_SSTATAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_sstatar1.rs b/esp32p4/src/dma/ch4_sstatar1.rs new file mode 100644 index 0000000000..4f3be60125 --- /dev/null +++ b/esp32p4/src/dma/ch4_sstatar1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH4_SSTATAR1` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_SSTATAR1` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_SSTATAR1` reader - NA"] +pub type CH4_SSTATAR1_R = crate::FieldReader; +#[doc = "Field `CH4_SSTATAR1` writer - NA"] +pub type CH4_SSTATAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ch4_sstatar1(&self) -> CH4_SSTATAR1_R { + CH4_SSTATAR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_SSTATAR1") + .field( + "ch4_sstatar1", + &format_args!("{}", self.ch4_sstatar1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_sstatar1(&mut self) -> CH4_SSTATAR1_W { + CH4_SSTATAR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_sstatar1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_sstatar1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_SSTATAR1_SPEC; +impl crate::RegisterSpec for CH4_SSTATAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_sstatar1::R`](R) reader structure"] +impl crate::Readable for CH4_SSTATAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_sstatar1::W`](W) writer structure"] +impl crate::Writable for CH4_SSTATAR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_SSTATAR1 to value 0"] +impl crate::Resettable for CH4_SSTATAR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_status0.rs b/esp32p4/src/dma/ch4_status0.rs new file mode 100644 index 0000000000..c43c4ba09c --- /dev/null +++ b/esp32p4/src/dma/ch4_status0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CH4_STATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `CH4_CMPLTD_BLK_TFR_SIZE` reader - NA"] +pub type CH4_CMPLTD_BLK_TFR_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - NA"] + #[inline(always)] + pub fn ch4_cmpltd_blk_tfr_size(&self) -> CH4_CMPLTD_BLK_TFR_SIZE_R { + CH4_CMPLTD_BLK_TFR_SIZE_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_STATUS0") + .field( + "ch4_cmpltd_blk_tfr_size", + &format_args!("{}", self.ch4_cmpltd_blk_tfr_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_STATUS0_SPEC; +impl crate::RegisterSpec for CH4_STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_status0::R`](R) reader structure"] +impl crate::Readable for CH4_STATUS0_SPEC {} +#[doc = "`reset()` method sets CH4_STATUS0 to value 0"] +impl crate::Resettable for CH4_STATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_status1.rs b/esp32p4/src/dma/ch4_status1.rs new file mode 100644 index 0000000000..823df0caef --- /dev/null +++ b/esp32p4/src/dma/ch4_status1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CH4_STATUS1` reader"] +pub type R = crate::R; +#[doc = "Field `CH4_DATA_LEFT_IN_FIFO` reader - NA"] +pub type CH4_DATA_LEFT_IN_FIFO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + pub fn ch4_data_left_in_fifo(&self) -> CH4_DATA_LEFT_IN_FIFO_R { + CH4_DATA_LEFT_IN_FIFO_R::new((self.bits & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_STATUS1") + .field( + "ch4_data_left_in_fifo", + &format_args!("{}", self.ch4_data_left_in_fifo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_status1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_STATUS1_SPEC; +impl crate::RegisterSpec for CH4_STATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_status1::R`](R) reader structure"] +impl crate::Readable for CH4_STATUS1_SPEC {} +#[doc = "`reset()` method sets CH4_STATUS1 to value 0"] +impl crate::Resettable for CH4_STATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_swhsdst0.rs b/esp32p4/src/dma/ch4_swhsdst0.rs new file mode 100644 index 0000000000..52cd7364ad --- /dev/null +++ b/esp32p4/src/dma/ch4_swhsdst0.rs @@ -0,0 +1,128 @@ +#[doc = "Register `CH4_SWHSDST0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_SWHSDST0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_SWHS_REQ_DST` reader - NA"] +pub type CH4_SWHS_REQ_DST_R = crate::BitReader; +#[doc = "Field `CH4_SWHS_REQ_DST` writer - NA"] +pub type CH4_SWHS_REQ_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SWHS_REQ_DST_WE` writer - NA"] +pub type CH4_SWHS_REQ_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SWHS_SGLREQ_DST` reader - NA"] +pub type CH4_SWHS_SGLREQ_DST_R = crate::BitReader; +#[doc = "Field `CH4_SWHS_SGLREQ_DST` writer - NA"] +pub type CH4_SWHS_SGLREQ_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SWHS_SGLREQ_DST_WE` writer - NA"] +pub type CH4_SWHS_SGLREQ_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SWHS_LST_DST` reader - NA"] +pub type CH4_SWHS_LST_DST_R = crate::BitReader; +#[doc = "Field `CH4_SWHS_LST_DST` writer - NA"] +pub type CH4_SWHS_LST_DST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SWHS_LST_DST_WE` writer - NA"] +pub type CH4_SWHS_LST_DST_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch4_swhs_req_dst(&self) -> CH4_SWHS_REQ_DST_R { + CH4_SWHS_REQ_DST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch4_swhs_sglreq_dst(&self) -> CH4_SWHS_SGLREQ_DST_R { + CH4_SWHS_SGLREQ_DST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch4_swhs_lst_dst(&self) -> CH4_SWHS_LST_DST_R { + CH4_SWHS_LST_DST_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_SWHSDST0") + .field( + "ch4_swhs_req_dst", + &format_args!("{}", self.ch4_swhs_req_dst().bit()), + ) + .field( + "ch4_swhs_sglreq_dst", + &format_args!("{}", self.ch4_swhs_sglreq_dst().bit()), + ) + .field( + "ch4_swhs_lst_dst", + &format_args!("{}", self.ch4_swhs_lst_dst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_req_dst(&mut self) -> CH4_SWHS_REQ_DST_W { + CH4_SWHS_REQ_DST_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_req_dst_we(&mut self) -> CH4_SWHS_REQ_DST_WE_W { + CH4_SWHS_REQ_DST_WE_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_sglreq_dst(&mut self) -> CH4_SWHS_SGLREQ_DST_W { + CH4_SWHS_SGLREQ_DST_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_sglreq_dst_we(&mut self) -> CH4_SWHS_SGLREQ_DST_WE_W { + CH4_SWHS_SGLREQ_DST_WE_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_lst_dst(&mut self) -> CH4_SWHS_LST_DST_W { + CH4_SWHS_LST_DST_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_lst_dst_we(&mut self) -> CH4_SWHS_LST_DST_WE_W { + CH4_SWHS_LST_DST_WE_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_swhsdst0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_swhsdst0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_SWHSDST0_SPEC; +impl crate::RegisterSpec for CH4_SWHSDST0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_swhsdst0::R`](R) reader structure"] +impl crate::Readable for CH4_SWHSDST0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_swhsdst0::W`](W) writer structure"] +impl crate::Writable for CH4_SWHSDST0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_SWHSDST0 to value 0"] +impl crate::Resettable for CH4_SWHSDST0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/ch4_swhssrc0.rs b/esp32p4/src/dma/ch4_swhssrc0.rs new file mode 100644 index 0000000000..c949089f80 --- /dev/null +++ b/esp32p4/src/dma/ch4_swhssrc0.rs @@ -0,0 +1,128 @@ +#[doc = "Register `CH4_SWHSSRC0` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_SWHSSRC0` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_SWHS_REQ_SRC` reader - NA"] +pub type CH4_SWHS_REQ_SRC_R = crate::BitReader; +#[doc = "Field `CH4_SWHS_REQ_SRC` writer - NA"] +pub type CH4_SWHS_REQ_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SWHS_REQ_SRC_WE` writer - NA"] +pub type CH4_SWHS_REQ_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SWHS_SGLREQ_SRC` reader - NA"] +pub type CH4_SWHS_SGLREQ_SRC_R = crate::BitReader; +#[doc = "Field `CH4_SWHS_SGLREQ_SRC` writer - NA"] +pub type CH4_SWHS_SGLREQ_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SWHS_SGLREQ_SRC_WE` writer - NA"] +pub type CH4_SWHS_SGLREQ_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SWHS_LST_SRC` reader - NA"] +pub type CH4_SWHS_LST_SRC_R = crate::BitReader; +#[doc = "Field `CH4_SWHS_LST_SRC` writer - NA"] +pub type CH4_SWHS_LST_SRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SWHS_LST_SRC_WE` writer - NA"] +pub type CH4_SWHS_LST_SRC_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch4_swhs_req_src(&self) -> CH4_SWHS_REQ_SRC_R { + CH4_SWHS_REQ_SRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch4_swhs_sglreq_src(&self) -> CH4_SWHS_SGLREQ_SRC_R { + CH4_SWHS_SGLREQ_SRC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ch4_swhs_lst_src(&self) -> CH4_SWHS_LST_SRC_R { + CH4_SWHS_LST_SRC_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_SWHSSRC0") + .field( + "ch4_swhs_req_src", + &format_args!("{}", self.ch4_swhs_req_src().bit()), + ) + .field( + "ch4_swhs_sglreq_src", + &format_args!("{}", self.ch4_swhs_sglreq_src().bit()), + ) + .field( + "ch4_swhs_lst_src", + &format_args!("{}", self.ch4_swhs_lst_src().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_req_src(&mut self) -> CH4_SWHS_REQ_SRC_W { + CH4_SWHS_REQ_SRC_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_req_src_we(&mut self) -> CH4_SWHS_REQ_SRC_WE_W { + CH4_SWHS_REQ_SRC_WE_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_sglreq_src(&mut self) -> CH4_SWHS_SGLREQ_SRC_W { + CH4_SWHS_SGLREQ_SRC_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_sglreq_src_we(&mut self) -> CH4_SWHS_SGLREQ_SRC_WE_W { + CH4_SWHS_SGLREQ_SRC_WE_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_lst_src(&mut self) -> CH4_SWHS_LST_SRC_W { + CH4_SWHS_LST_SRC_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_swhs_lst_src_we(&mut self) -> CH4_SWHS_LST_SRC_WE_W { + CH4_SWHS_LST_SRC_WE_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_swhssrc0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_swhssrc0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_SWHSSRC0_SPEC; +impl crate::RegisterSpec for CH4_SWHSSRC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_swhssrc0::R`](R) reader structure"] +impl crate::Readable for CH4_SWHSSRC0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_swhssrc0::W`](W) writer structure"] +impl crate::Writable for CH4_SWHSSRC0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_SWHSSRC0 to value 0"] +impl crate::Resettable for CH4_SWHSSRC0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/chen0.rs b/esp32p4/src/dma/chen0.rs new file mode 100644 index 0000000000..12286a9e81 --- /dev/null +++ b/esp32p4/src/dma/chen0.rs @@ -0,0 +1,239 @@ +#[doc = "Register `CHEN0` reader"] +pub type R = crate::R; +#[doc = "Register `CHEN0` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_EN` reader - NA"] +pub type CH1_EN_R = crate::BitReader; +#[doc = "Field `CH1_EN` writer - NA"] +pub type CH1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_EN` reader - NA"] +pub type CH2_EN_R = crate::BitReader; +#[doc = "Field `CH2_EN` writer - NA"] +pub type CH2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_EN` reader - NA"] +pub type CH3_EN_R = crate::BitReader; +#[doc = "Field `CH3_EN` writer - NA"] +pub type CH3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_EN` reader - NA"] +pub type CH4_EN_R = crate::BitReader; +#[doc = "Field `CH4_EN` writer - NA"] +pub type CH4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_EN_WE` writer - NA"] +pub type CH1_EN_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_EN_WE` writer - NA"] +pub type CH2_EN_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_EN_WE` writer - NA"] +pub type CH3_EN_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_EN_WE` writer - NA"] +pub type CH4_EN_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SUSP` reader - NA"] +pub type CH1_SUSP_R = crate::BitReader; +#[doc = "Field `CH1_SUSP` writer - NA"] +pub type CH1_SUSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SUSP` reader - NA"] +pub type CH2_SUSP_R = crate::BitReader; +#[doc = "Field `CH2_SUSP` writer - NA"] +pub type CH2_SUSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SUSP` reader - NA"] +pub type CH3_SUSP_R = crate::BitReader; +#[doc = "Field `CH3_SUSP` writer - NA"] +pub type CH3_SUSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SUSP` reader - NA"] +pub type CH4_SUSP_R = crate::BitReader; +#[doc = "Field `CH4_SUSP` writer - NA"] +pub type CH4_SUSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_SUSP_WE` writer - NA"] +pub type CH1_SUSP_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_SUSP_WE` writer - NA"] +pub type CH2_SUSP_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_SUSP_WE` writer - NA"] +pub type CH3_SUSP_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_SUSP_WE` writer - NA"] +pub type CH4_SUSP_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_en(&self) -> CH1_EN_R { + CH1_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch2_en(&self) -> CH2_EN_R { + CH2_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch3_en(&self) -> CH3_EN_R { + CH3_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch4_en(&self) -> CH4_EN_R { + CH4_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn ch1_susp(&self) -> CH1_SUSP_R { + CH1_SUSP_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn ch2_susp(&self) -> CH2_SUSP_R { + CH2_SUSP_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn ch3_susp(&self) -> CH3_SUSP_R { + CH3_SUSP_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn ch4_susp(&self) -> CH4_SUSP_R { + CH4_SUSP_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CHEN0") + .field("ch1_en", &format_args!("{}", self.ch1_en().bit())) + .field("ch2_en", &format_args!("{}", self.ch2_en().bit())) + .field("ch3_en", &format_args!("{}", self.ch3_en().bit())) + .field("ch4_en", &format_args!("{}", self.ch4_en().bit())) + .field("ch1_susp", &format_args!("{}", self.ch1_susp().bit())) + .field("ch2_susp", &format_args!("{}", self.ch2_susp().bit())) + .field("ch3_susp", &format_args!("{}", self.ch3_susp().bit())) + .field("ch4_susp", &format_args!("{}", self.ch4_susp().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_en(&mut self) -> CH1_EN_W { + CH1_EN_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_en(&mut self) -> CH2_EN_W { + CH2_EN_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_en(&mut self) -> CH3_EN_W { + CH3_EN_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_en(&mut self) -> CH4_EN_W { + CH4_EN_W::new(self, 3) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_en_we(&mut self) -> CH1_EN_WE_W { + CH1_EN_WE_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_en_we(&mut self) -> CH2_EN_WE_W { + CH2_EN_WE_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_en_we(&mut self) -> CH3_EN_WE_W { + CH3_EN_WE_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_en_we(&mut self) -> CH4_EN_WE_W { + CH4_EN_WE_W::new(self, 11) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_susp(&mut self) -> CH1_SUSP_W { + CH1_SUSP_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_susp(&mut self) -> CH2_SUSP_W { + CH2_SUSP_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_susp(&mut self) -> CH3_SUSP_W { + CH3_SUSP_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_susp(&mut self) -> CH4_SUSP_W { + CH4_SUSP_W::new(self, 19) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_susp_we(&mut self) -> CH1_SUSP_WE_W { + CH1_SUSP_WE_W::new(self, 24) + } + #[doc = "Bit 25 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_susp_we(&mut self) -> CH2_SUSP_WE_W { + CH2_SUSP_WE_W::new(self, 25) + } + #[doc = "Bit 26 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_susp_we(&mut self) -> CH3_SUSP_WE_W { + CH3_SUSP_WE_W::new(self, 26) + } + #[doc = "Bit 27 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_susp_we(&mut self) -> CH4_SUSP_WE_W { + CH4_SUSP_WE_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chen0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHEN0_SPEC; +impl crate::RegisterSpec for CHEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chen0::R`](R) reader structure"] +impl crate::Readable for CHEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chen0::W`](W) writer structure"] +impl crate::Writable for CHEN0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CHEN0 to value 0"] +impl crate::Resettable for CHEN0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/chen1.rs b/esp32p4/src/dma/chen1.rs new file mode 100644 index 0000000000..0b0fa6357e --- /dev/null +++ b/esp32p4/src/dma/chen1.rs @@ -0,0 +1,143 @@ +#[doc = "Register `CHEN1` reader"] +pub type R = crate::R; +#[doc = "Register `CHEN1` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_ABORT` reader - NA"] +pub type CH1_ABORT_R = crate::BitReader; +#[doc = "Field `CH1_ABORT` writer - NA"] +pub type CH1_ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ABORT` reader - NA"] +pub type CH2_ABORT_R = crate::BitReader; +#[doc = "Field `CH2_ABORT` writer - NA"] +pub type CH2_ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ABORT` reader - NA"] +pub type CH3_ABORT_R = crate::BitReader; +#[doc = "Field `CH3_ABORT` writer - NA"] +pub type CH3_ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ABORT` reader - NA"] +pub type CH4_ABORT_R = crate::BitReader; +#[doc = "Field `CH4_ABORT` writer - NA"] +pub type CH4_ABORT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_ABORT_WE` writer - NA"] +pub type CH1_ABORT_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_ABORT_WE` writer - NA"] +pub type CH2_ABORT_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_ABORT_WE` writer - NA"] +pub type CH3_ABORT_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ABORT_WE` writer - NA"] +pub type CH4_ABORT_WE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_abort(&self) -> CH1_ABORT_R { + CH1_ABORT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch2_abort(&self) -> CH2_ABORT_R { + CH2_ABORT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch3_abort(&self) -> CH3_ABORT_R { + CH3_ABORT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch4_abort(&self) -> CH4_ABORT_R { + CH4_ABORT_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CHEN1") + .field("ch1_abort", &format_args!("{}", self.ch1_abort().bit())) + .field("ch2_abort", &format_args!("{}", self.ch2_abort().bit())) + .field("ch3_abort", &format_args!("{}", self.ch3_abort().bit())) + .field("ch4_abort", &format_args!("{}", self.ch4_abort().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_abort(&mut self) -> CH1_ABORT_W { + CH1_ABORT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_abort(&mut self) -> CH2_ABORT_W { + CH2_ABORT_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_abort(&mut self) -> CH3_ABORT_W { + CH3_ABORT_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_abort(&mut self) -> CH4_ABORT_W { + CH4_ABORT_W::new(self, 3) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn ch1_abort_we(&mut self) -> CH1_ABORT_WE_W { + CH1_ABORT_WE_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn ch2_abort_we(&mut self) -> CH2_ABORT_WE_W { + CH2_ABORT_WE_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn ch3_abort_we(&mut self) -> CH3_ABORT_WE_W { + CH3_ABORT_WE_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ch4_abort_we(&mut self) -> CH4_ABORT_WE_W { + CH4_ABORT_WE_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chen1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chen1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHEN1_SPEC; +impl crate::RegisterSpec for CHEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chen1::R`](R) reader structure"] +impl crate::Readable for CHEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chen1::W`](W) writer structure"] +impl crate::Writable for CHEN1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CHEN1 to value 0"] +impl crate::Resettable for CHEN1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/commonreg_intclear0.rs b/esp32p4/src/dma/commonreg_intclear0.rs new file mode 100644 index 0000000000..a2694d1b1a --- /dev/null +++ b/esp32p4/src/dma/commonreg_intclear0.rs @@ -0,0 +1,214 @@ +#[doc = "Register `COMMONREG_INTCLEAR0` writer"] +pub type W = crate::W; +#[doc = "Field `CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT` writer - NA"] +pub type CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT` writer - NA"] +pub type CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT` writer - NA"] +pub type CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT` writer - NA"] +pub type CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT` writer - NA"] +pub type CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT` writer - NA"] +pub type CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT` writer - NA"] +pub type CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_slvif_commonreg_dec_err_intstat( + &mut self, + ) -> CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_W { + CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_slvif_commonreg_wr2ro_err_intstat( + &mut self, + ) -> CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_W { + CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_slvif_commonreg_rd2wo_err_intstat( + &mut self, + ) -> CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_W { + CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_slvif_commonreg_wronhold_err_intstat( + &mut self, + ) -> CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_W { + CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_W::new(self, 3) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_slvif_commonreg_wrparity_err_intstat( + &mut self, + ) -> CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_W { + CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_slvif_undefinedreg_dec_err_intstat( + &mut self, + ) -> CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_W { + CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif1_rch0_eccprot_correrr_intstat( + &mut self, + ) -> CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_W { + CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif1_rch0_eccprot_uncorrerr_intstat( + &mut self, + ) -> CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_W { + CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif1_rch1_eccprot_correrr_intstat( + &mut self, + ) -> CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_W { + CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif1_rch1_eccprot_uncorrerr_intstat( + &mut self, + ) -> CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_W { + CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif1_bch_eccprot_correrr_intstat( + &mut self, + ) -> CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_W { + CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif1_bch_eccprot_uncorrerr_intstat( + &mut self, + ) -> CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_W { + CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif2_rch0_eccprot_correrr_intstat( + &mut self, + ) -> CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_W { + CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_W::new(self, 15) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif2_rch0_eccprot_uncorrerr_intstat( + &mut self, + ) -> CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_W { + CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif2_rch1_eccprot_correrr_intstat( + &mut self, + ) -> CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_W { + CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif2_rch1_eccprot_uncorrerr_intstat( + &mut self, + ) -> CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_W { + CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif2_bch_eccprot_correrr_intstat( + &mut self, + ) -> CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_W { + CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn clear_mxif2_bch_eccprot_uncorrerr_intstat( + &mut self, + ) -> CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_W { + CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`commonreg_intclear0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMMONREG_INTCLEAR0_SPEC; +impl crate::RegisterSpec for COMMONREG_INTCLEAR0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`commonreg_intclear0::W`](W) writer structure"] +impl crate::Writable for COMMONREG_INTCLEAR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMMONREG_INTCLEAR0 to value 0"] +impl crate::Resettable for COMMONREG_INTCLEAR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/commonreg_intsignal_enable0.rs b/esp32p4/src/dma/commonreg_intsignal_enable0.rs new file mode 100644 index 0000000000..74e18253c0 --- /dev/null +++ b/esp32p4/src/dma/commonreg_intsignal_enable0.rs @@ -0,0 +1,382 @@ +#[doc = "Register `COMMONREG_INTSIGNAL_ENABLE0` reader"] +pub type R = crate::R; +#[doc = "Register `COMMONREG_INTSIGNAL_ENABLE0` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL` reader - NA"] +pub type ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL` writer - NA"] +pub type ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL` reader - NA"] +pub type ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL` writer - NA"] +pub type ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL` reader - NA"] +pub type ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL` writer - NA"] +pub type ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL` reader - NA"] +pub type ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL` writer - NA"] +pub type ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL` reader - NA"] +pub type ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL` reader - NA"] +pub type ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL` writer - NA"] +pub type ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL` reader - NA"] +pub type ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn enable_slvif_commonreg_dec_err_intsignal( + &self, + ) -> ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_R { + ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn enable_slvif_commonreg_wr2ro_err_intsignal( + &self, + ) -> ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_R { + ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn enable_slvif_commonreg_rd2wo_err_intsignal( + &self, + ) -> ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_R { + ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn enable_slvif_commonreg_wronhold_err_intsignal( + &self, + ) -> ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_R { + ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn enable_slvif_commonreg_wrparity_err_intsignal( + &self, + ) -> ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_R { + ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn enable_slvif_undefinedreg_dec_err_intsignal( + &self, + ) -> ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_R { + ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn enable_mxif1_rch0_eccprot_correrr_intsignal( + &self, + ) -> ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_R { + ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn enable_mxif1_rch0_eccprot_uncorrerr_intsignal( + &self, + ) -> ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_R { + ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn enable_mxif1_rch1_eccprot_correrr_intsignal( + &self, + ) -> ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_R { + ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn enable_mxif1_rch1_eccprot_uncorrerr_intsignal( + &self, + ) -> ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_R { + ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn enable_mxif1_bch_eccprot_correrr_intsignal( + &self, + ) -> ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_R { + ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn enable_mxif1_bch_eccprot_uncorrerr_intsignal( + &self, + ) -> ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_R { + ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn enable_mxif2_rch0_eccprot_correrr_intsignal( + &self, + ) -> ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_R { + ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn enable_mxif2_rch0_eccprot_uncorrerr_intsignal( + &self, + ) -> ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_R { + ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn enable_mxif2_rch1_eccprot_correrr_intsignal( + &self, + ) -> ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_R { + ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn enable_mxif2_rch1_eccprot_uncorrerr_intsignal( + &self, + ) -> ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_R { + ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn enable_mxif2_bch_eccprot_correrr_intsignal( + &self, + ) -> ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_R { + ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn enable_mxif2_bch_eccprot_uncorrerr_intsignal( + &self, + ) -> ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_R { + ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMMONREG_INTSIGNAL_ENABLE0") + .field( + "enable_slvif_commonreg_dec_err_intsignal", + &format_args!("{}", self.enable_slvif_commonreg_dec_err_intsignal().bit()), + ) + .field( + "enable_slvif_commonreg_wr2ro_err_intsignal", + &format_args!( + "{}", + self.enable_slvif_commonreg_wr2ro_err_intsignal().bit() + ), + ) + .field( + "enable_slvif_commonreg_rd2wo_err_intsignal", + &format_args!( + "{}", + self.enable_slvif_commonreg_rd2wo_err_intsignal().bit() + ), + ) + .field( + "enable_slvif_commonreg_wronhold_err_intsignal", + &format_args!( + "{}", + self.enable_slvif_commonreg_wronhold_err_intsignal().bit() + ), + ) + .field( + "enable_slvif_commonreg_wrparity_err_intsignal", + &format_args!( + "{}", + self.enable_slvif_commonreg_wrparity_err_intsignal().bit() + ), + ) + .field( + "enable_slvif_undefinedreg_dec_err_intsignal", + &format_args!( + "{}", + self.enable_slvif_undefinedreg_dec_err_intsignal().bit() + ), + ) + .field( + "enable_mxif1_rch0_eccprot_correrr_intsignal", + &format_args!( + "{}", + self.enable_mxif1_rch0_eccprot_correrr_intsignal().bit() + ), + ) + .field( + "enable_mxif1_rch0_eccprot_uncorrerr_intsignal", + &format_args!( + "{}", + self.enable_mxif1_rch0_eccprot_uncorrerr_intsignal().bit() + ), + ) + .field( + "enable_mxif1_rch1_eccprot_correrr_intsignal", + &format_args!( + "{}", + self.enable_mxif1_rch1_eccprot_correrr_intsignal().bit() + ), + ) + .field( + "enable_mxif1_rch1_eccprot_uncorrerr_intsignal", + &format_args!( + "{}", + self.enable_mxif1_rch1_eccprot_uncorrerr_intsignal().bit() + ), + ) + .field( + "enable_mxif1_bch_eccprot_correrr_intsignal", + &format_args!( + "{}", + self.enable_mxif1_bch_eccprot_correrr_intsignal().bit() + ), + ) + .field( + "enable_mxif1_bch_eccprot_uncorrerr_intsignal", + &format_args!( + "{}", + self.enable_mxif1_bch_eccprot_uncorrerr_intsignal().bit() + ), + ) + .field( + "enable_mxif2_rch0_eccprot_correrr_intsignal", + &format_args!( + "{}", + self.enable_mxif2_rch0_eccprot_correrr_intsignal().bit() + ), + ) + .field( + "enable_mxif2_rch0_eccprot_uncorrerr_intsignal", + &format_args!( + "{}", + self.enable_mxif2_rch0_eccprot_uncorrerr_intsignal().bit() + ), + ) + .field( + "enable_mxif2_rch1_eccprot_correrr_intsignal", + &format_args!( + "{}", + self.enable_mxif2_rch1_eccprot_correrr_intsignal().bit() + ), + ) + .field( + "enable_mxif2_rch1_eccprot_uncorrerr_intsignal", + &format_args!( + "{}", + self.enable_mxif2_rch1_eccprot_uncorrerr_intsignal().bit() + ), + ) + .field( + "enable_mxif2_bch_eccprot_correrr_intsignal", + &format_args!( + "{}", + self.enable_mxif2_bch_eccprot_correrr_intsignal().bit() + ), + ) + .field( + "enable_mxif2_bch_eccprot_uncorrerr_intsignal", + &format_args!( + "{}", + self.enable_mxif2_bch_eccprot_uncorrerr_intsignal().bit() + ), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn enable_slvif_commonreg_dec_err_intsignal( + &mut self, + ) -> ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_W { + ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn enable_slvif_commonreg_wr2ro_err_intsignal( + &mut self, + ) -> ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_W { + ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn enable_slvif_commonreg_rd2wo_err_intsignal( + &mut self, + ) -> ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_W { + ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn enable_slvif_commonreg_wronhold_err_intsignal( + &mut self, + ) -> ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_W { + ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_W::new(self, 3) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn enable_slvif_undefinedreg_dec_err_intsignal( + &mut self, + ) -> ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_W { + ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`commonreg_intsignal_enable0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`commonreg_intsignal_enable0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMMONREG_INTSIGNAL_ENABLE0_SPEC; +impl crate::RegisterSpec for COMMONREG_INTSIGNAL_ENABLE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`commonreg_intsignal_enable0::R`](R) reader structure"] +impl crate::Readable for COMMONREG_INTSIGNAL_ENABLE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`commonreg_intsignal_enable0::W`](W) writer structure"] +impl crate::Writable for COMMONREG_INTSIGNAL_ENABLE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMMONREG_INTSIGNAL_ENABLE0 to value 0x001f_ff8f"] +impl crate::Resettable for COMMONREG_INTSIGNAL_ENABLE0_SPEC { + const RESET_VALUE: Self::Ux = 0x001f_ff8f; +} diff --git a/esp32p4/src/dma/commonreg_intstatus0.rs b/esp32p4/src/dma/commonreg_intstatus0.rs new file mode 100644 index 0000000000..1b50762bf7 --- /dev/null +++ b/esp32p4/src/dma/commonreg_intstatus0.rs @@ -0,0 +1,226 @@ +#[doc = "Register `COMMONREG_INTSTATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `SLVIF_COMMONREG_DEC_ERR_INTSTAT` reader - NA"] +pub type SLVIF_COMMONREG_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `SLVIF_COMMONREG_WR2RO_ERR_INTSTAT` reader - NA"] +pub type SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `SLVIF_COMMONREG_RD2WO_ERR_INTSTAT` reader - NA"] +pub type SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT` reader - NA"] +pub type SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT` reader - NA"] +pub type SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT` reader - NA"] +pub type SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF1_BCH_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF2_BCH_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn slvif_commonreg_dec_err_intstat(&self) -> SLVIF_COMMONREG_DEC_ERR_INTSTAT_R { + SLVIF_COMMONREG_DEC_ERR_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn slvif_commonreg_wr2ro_err_intstat(&self) -> SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_R { + SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn slvif_commonreg_rd2wo_err_intstat(&self) -> SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_R { + SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn slvif_commonreg_wronhold_err_intstat(&self) -> SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_R { + SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn slvif_commonreg_wrparity_err_intstat(&self) -> SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_R { + SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn slvif_undefinedreg_dec_err_intstat(&self) -> SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_R { + SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn mxif1_rch0_eccprot_correrr_intstat(&self) -> MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_R { + MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn mxif1_rch0_eccprot_uncorrerr_intstat(&self) -> MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_R { + MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn mxif1_rch1_eccprot_correrr_intstat(&self) -> MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_R { + MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn mxif1_rch1_eccprot_uncorrerr_intstat(&self) -> MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_R { + MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn mxif1_bch_eccprot_correrr_intstat(&self) -> MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_R { + MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn mxif1_bch_eccprot_uncorrerr_intstat(&self) -> MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_R { + MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn mxif2_rch0_eccprot_correrr_intstat(&self) -> MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_R { + MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn mxif2_rch0_eccprot_uncorrerr_intstat(&self) -> MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_R { + MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn mxif2_rch1_eccprot_correrr_intstat(&self) -> MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_R { + MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn mxif2_rch1_eccprot_uncorrerr_intstat(&self) -> MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_R { + MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn mxif2_bch_eccprot_correrr_intstat(&self) -> MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_R { + MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn mxif2_bch_eccprot_uncorrerr_intstat(&self) -> MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_R { + MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMMONREG_INTSTATUS0") + .field( + "slvif_commonreg_dec_err_intstat", + &format_args!("{}", self.slvif_commonreg_dec_err_intstat().bit()), + ) + .field( + "slvif_commonreg_wr2ro_err_intstat", + &format_args!("{}", self.slvif_commonreg_wr2ro_err_intstat().bit()), + ) + .field( + "slvif_commonreg_rd2wo_err_intstat", + &format_args!("{}", self.slvif_commonreg_rd2wo_err_intstat().bit()), + ) + .field( + "slvif_commonreg_wronhold_err_intstat", + &format_args!("{}", self.slvif_commonreg_wronhold_err_intstat().bit()), + ) + .field( + "slvif_commonreg_wrparity_err_intstat", + &format_args!("{}", self.slvif_commonreg_wrparity_err_intstat().bit()), + ) + .field( + "slvif_undefinedreg_dec_err_intstat", + &format_args!("{}", self.slvif_undefinedreg_dec_err_intstat().bit()), + ) + .field( + "mxif1_rch0_eccprot_correrr_intstat", + &format_args!("{}", self.mxif1_rch0_eccprot_correrr_intstat().bit()), + ) + .field( + "mxif1_rch0_eccprot_uncorrerr_intstat", + &format_args!("{}", self.mxif1_rch0_eccprot_uncorrerr_intstat().bit()), + ) + .field( + "mxif1_rch1_eccprot_correrr_intstat", + &format_args!("{}", self.mxif1_rch1_eccprot_correrr_intstat().bit()), + ) + .field( + "mxif1_rch1_eccprot_uncorrerr_intstat", + &format_args!("{}", self.mxif1_rch1_eccprot_uncorrerr_intstat().bit()), + ) + .field( + "mxif1_bch_eccprot_correrr_intstat", + &format_args!("{}", self.mxif1_bch_eccprot_correrr_intstat().bit()), + ) + .field( + "mxif1_bch_eccprot_uncorrerr_intstat", + &format_args!("{}", self.mxif1_bch_eccprot_uncorrerr_intstat().bit()), + ) + .field( + "mxif2_rch0_eccprot_correrr_intstat", + &format_args!("{}", self.mxif2_rch0_eccprot_correrr_intstat().bit()), + ) + .field( + "mxif2_rch0_eccprot_uncorrerr_intstat", + &format_args!("{}", self.mxif2_rch0_eccprot_uncorrerr_intstat().bit()), + ) + .field( + "mxif2_rch1_eccprot_correrr_intstat", + &format_args!("{}", self.mxif2_rch1_eccprot_correrr_intstat().bit()), + ) + .field( + "mxif2_rch1_eccprot_uncorrerr_intstat", + &format_args!("{}", self.mxif2_rch1_eccprot_uncorrerr_intstat().bit()), + ) + .field( + "mxif2_bch_eccprot_correrr_intstat", + &format_args!("{}", self.mxif2_bch_eccprot_correrr_intstat().bit()), + ) + .field( + "mxif2_bch_eccprot_uncorrerr_intstat", + &format_args!("{}", self.mxif2_bch_eccprot_uncorrerr_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`commonreg_intstatus0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMMONREG_INTSTATUS0_SPEC; +impl crate::RegisterSpec for COMMONREG_INTSTATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`commonreg_intstatus0::R`](R) reader structure"] +impl crate::Readable for COMMONREG_INTSTATUS0_SPEC {} +#[doc = "`reset()` method sets COMMONREG_INTSTATUS0 to value 0"] +impl crate::Resettable for COMMONREG_INTSTATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/commonreg_intstatus_enable0.rs b/esp32p4/src/dma/commonreg_intstatus_enable0.rs new file mode 100644 index 0000000000..6bbbb3705b --- /dev/null +++ b/esp32p4/src/dma/commonreg_intstatus_enable0.rs @@ -0,0 +1,355 @@ +#[doc = "Register `COMMONREG_INTSTATUS_ENABLE0` reader"] +pub type R = crate::R; +#[doc = "Register `COMMONREG_INTSTATUS_ENABLE0` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT` reader - NA"] +pub type ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT` writer - NA"] +pub type ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT` reader - NA"] +pub type ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT` writer - NA"] +pub type ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT` reader - NA"] +pub type ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT` writer - NA"] +pub type ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT` reader - NA"] +pub type ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT` writer - NA"] +pub type ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT` reader - NA"] +pub type ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT` reader - NA"] +pub type ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT` writer - NA"] +pub type ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_R = crate::BitReader; +#[doc = "Field `ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT` reader - NA"] +pub type ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn enable_slvif_commonreg_dec_err_intstat( + &self, + ) -> ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_R { + ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn enable_slvif_commonreg_wr2ro_err_intstat( + &self, + ) -> ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_R { + ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn enable_slvif_commonreg_rd2wo_err_intstat( + &self, + ) -> ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_R { + ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn enable_slvif_commonreg_wronhold_err_intstat( + &self, + ) -> ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_R { + ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn enable_slvif_commonreg_wrparity_err_intstat( + &self, + ) -> ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_R { + ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn enable_slvif_undefinedreg_dec_err_intstat( + &self, + ) -> ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_R { + ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn enable_mxif1_rch0_eccprot_correrr_intstat( + &self, + ) -> ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_R { + ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn enable_mxif1_rch0_eccprot_uncorrerr_intstat( + &self, + ) -> ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_R { + ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn enable_mxif1_rch1_eccprot_correrr_intstat( + &self, + ) -> ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_R { + ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn enable_mxif1_rch1_eccprot_uncorrerr_intstat( + &self, + ) -> ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_R { + ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn enable_mxif1_bch_eccprot_correrr_intstat( + &self, + ) -> ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_R { + ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn enable_mxif1_bch_eccprot_uncorrerr_intstat( + &self, + ) -> ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_R { + ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn enable_mxif2_rch0_eccprot_correrr_intstat( + &self, + ) -> ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_R { + ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn enable_mxif2_rch0_eccprot_uncorrerr_intstat( + &self, + ) -> ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_R { + ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn enable_mxif2_rch1_eccprot_correrr_intstat( + &self, + ) -> ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_R { + ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn enable_mxif2_rch1_eccprot_uncorrerr_intstat( + &self, + ) -> ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_R { + ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn enable_mxif2_bch_eccprot_correrr_intstat( + &self, + ) -> ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_R { + ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn enable_mxif2_bch_eccprot_uncorrerr_intstat( + &self, + ) -> ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_R { + ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMMONREG_INTSTATUS_ENABLE0") + .field( + "enable_slvif_commonreg_dec_err_intstat", + &format_args!("{}", self.enable_slvif_commonreg_dec_err_intstat().bit()), + ) + .field( + "enable_slvif_commonreg_wr2ro_err_intstat", + &format_args!("{}", self.enable_slvif_commonreg_wr2ro_err_intstat().bit()), + ) + .field( + "enable_slvif_commonreg_rd2wo_err_intstat", + &format_args!("{}", self.enable_slvif_commonreg_rd2wo_err_intstat().bit()), + ) + .field( + "enable_slvif_commonreg_wronhold_err_intstat", + &format_args!( + "{}", + self.enable_slvif_commonreg_wronhold_err_intstat().bit() + ), + ) + .field( + "enable_slvif_commonreg_wrparity_err_intstat", + &format_args!( + "{}", + self.enable_slvif_commonreg_wrparity_err_intstat().bit() + ), + ) + .field( + "enable_slvif_undefinedreg_dec_err_intstat", + &format_args!("{}", self.enable_slvif_undefinedreg_dec_err_intstat().bit()), + ) + .field( + "enable_mxif1_rch0_eccprot_correrr_intstat", + &format_args!("{}", self.enable_mxif1_rch0_eccprot_correrr_intstat().bit()), + ) + .field( + "enable_mxif1_rch0_eccprot_uncorrerr_intstat", + &format_args!( + "{}", + self.enable_mxif1_rch0_eccprot_uncorrerr_intstat().bit() + ), + ) + .field( + "enable_mxif1_rch1_eccprot_correrr_intstat", + &format_args!("{}", self.enable_mxif1_rch1_eccprot_correrr_intstat().bit()), + ) + .field( + "enable_mxif1_rch1_eccprot_uncorrerr_intstat", + &format_args!( + "{}", + self.enable_mxif1_rch1_eccprot_uncorrerr_intstat().bit() + ), + ) + .field( + "enable_mxif1_bch_eccprot_correrr_intstat", + &format_args!("{}", self.enable_mxif1_bch_eccprot_correrr_intstat().bit()), + ) + .field( + "enable_mxif1_bch_eccprot_uncorrerr_intstat", + &format_args!( + "{}", + self.enable_mxif1_bch_eccprot_uncorrerr_intstat().bit() + ), + ) + .field( + "enable_mxif2_rch0_eccprot_correrr_intstat", + &format_args!("{}", self.enable_mxif2_rch0_eccprot_correrr_intstat().bit()), + ) + .field( + "enable_mxif2_rch0_eccprot_uncorrerr_intstat", + &format_args!( + "{}", + self.enable_mxif2_rch0_eccprot_uncorrerr_intstat().bit() + ), + ) + .field( + "enable_mxif2_rch1_eccprot_correrr_intstat", + &format_args!("{}", self.enable_mxif2_rch1_eccprot_correrr_intstat().bit()), + ) + .field( + "enable_mxif2_rch1_eccprot_uncorrerr_intstat", + &format_args!( + "{}", + self.enable_mxif2_rch1_eccprot_uncorrerr_intstat().bit() + ), + ) + .field( + "enable_mxif2_bch_eccprot_correrr_intstat", + &format_args!("{}", self.enable_mxif2_bch_eccprot_correrr_intstat().bit()), + ) + .field( + "enable_mxif2_bch_eccprot_uncorrerr_intstat", + &format_args!( + "{}", + self.enable_mxif2_bch_eccprot_uncorrerr_intstat().bit() + ), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn enable_slvif_commonreg_dec_err_intstat( + &mut self, + ) -> ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_W { + ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn enable_slvif_commonreg_wr2ro_err_intstat( + &mut self, + ) -> ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_W { + ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn enable_slvif_commonreg_rd2wo_err_intstat( + &mut self, + ) -> ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_W { + ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn enable_slvif_commonreg_wronhold_err_intstat( + &mut self, + ) -> ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_W { + ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_W::new(self, 3) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn enable_slvif_undefinedreg_dec_err_intstat( + &mut self, + ) -> ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_W { + ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`commonreg_intstatus_enable0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`commonreg_intstatus_enable0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMMONREG_INTSTATUS_ENABLE0_SPEC; +impl crate::RegisterSpec for COMMONREG_INTSTATUS_ENABLE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`commonreg_intstatus_enable0::R`](R) reader structure"] +impl crate::Readable for COMMONREG_INTSTATUS_ENABLE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`commonreg_intstatus_enable0::W`](W) writer structure"] +impl crate::Writable for COMMONREG_INTSTATUS_ENABLE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMMONREG_INTSTATUS_ENABLE0 to value 0x001f_ff8f"] +impl crate::Resettable for COMMONREG_INTSTATUS_ENABLE0_SPEC { + const RESET_VALUE: Self::Ux = 0x001f_ff8f; +} diff --git a/esp32p4/src/dma/compver0.rs b/esp32p4/src/dma/compver0.rs new file mode 100644 index 0000000000..c8436479c7 --- /dev/null +++ b/esp32p4/src/dma/compver0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `COMPVER0` reader"] +pub type R = crate::R; +#[doc = "Field `DMAC_COMPVER` reader - NA"] +pub type DMAC_COMPVER_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dmac_compver(&self) -> DMAC_COMPVER_R { + DMAC_COMPVER_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMPVER0") + .field( + "dmac_compver", + &format_args!("{}", self.dmac_compver().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`compver0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMPVER0_SPEC; +impl crate::RegisterSpec for COMPVER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`compver0::R`](R) reader structure"] +impl crate::Readable for COMPVER0_SPEC {} +#[doc = "`reset()` method sets COMPVER0 to value 0x3230_302a"] +impl crate::Resettable for COMPVER0_SPEC { + const RESET_VALUE: Self::Ux = 0x3230_302a; +} diff --git a/esp32p4/src/dma/id0.rs b/esp32p4/src/dma/id0.rs new file mode 100644 index 0000000000..16a3b4ac67 --- /dev/null +++ b/esp32p4/src/dma/id0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `ID0` reader"] +pub type R = crate::R; +#[doc = "Field `DMAC_ID` reader - NA"] +pub type DMAC_ID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dmac_id(&self) -> DMAC_ID_R { + DMAC_ID_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ID0") + .field("dmac_id", &format_args!("{}", self.dmac_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID0_SPEC; +impl crate::RegisterSpec for ID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0::R`](R) reader structure"] +impl crate::Readable for ID0_SPEC {} +#[doc = "`reset()` method sets ID0 to value 0"] +impl crate::Resettable for ID0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/intstatus0.rs b/esp32p4/src/dma/intstatus0.rs new file mode 100644 index 0000000000..58e1b47a4a --- /dev/null +++ b/esp32p4/src/dma/intstatus0.rs @@ -0,0 +1,71 @@ +#[doc = "Register `INTSTATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `CH1_INTSTAT` reader - NA"] +pub type CH1_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH2_INTSTAT` reader - NA"] +pub type CH2_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH3_INTSTAT` reader - NA"] +pub type CH3_INTSTAT_R = crate::BitReader; +#[doc = "Field `CH4_INTSTAT` reader - NA"] +pub type CH4_INTSTAT_R = crate::BitReader; +#[doc = "Field `COMMONREG_INTSTAT` reader - NA"] +pub type COMMONREG_INTSTAT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ch1_intstat(&self) -> CH1_INTSTAT_R { + CH1_INTSTAT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ch2_intstat(&self) -> CH2_INTSTAT_R { + CH2_INTSTAT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ch3_intstat(&self) -> CH3_INTSTAT_R { + CH3_INTSTAT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ch4_intstat(&self) -> CH4_INTSTAT_R { + CH4_INTSTAT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn commonreg_intstat(&self) -> COMMONREG_INTSTAT_R { + COMMONREG_INTSTAT_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTSTATUS0") + .field("ch1_intstat", &format_args!("{}", self.ch1_intstat().bit())) + .field("ch2_intstat", &format_args!("{}", self.ch2_intstat().bit())) + .field("ch3_intstat", &format_args!("{}", self.ch3_intstat().bit())) + .field("ch4_intstat", &format_args!("{}", self.ch4_intstat().bit())) + .field( + "commonreg_intstat", + &format_args!("{}", self.commonreg_intstat().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intstatus0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTSTATUS0_SPEC; +impl crate::RegisterSpec for INTSTATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intstatus0::R`](R) reader structure"] +impl crate::Readable for INTSTATUS0_SPEC {} +#[doc = "`reset()` method sets INTSTATUS0 to value 0"] +impl crate::Resettable for INTSTATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/dma/lowpower_cfg0.rs b/esp32p4/src/dma/lowpower_cfg0.rs new file mode 100644 index 0000000000..f0d21ae151 --- /dev/null +++ b/esp32p4/src/dma/lowpower_cfg0.rs @@ -0,0 +1,120 @@ +#[doc = "Register `LOWPOWER_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `LOWPOWER_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `GBL_CSLP_EN` reader - NA"] +pub type GBL_CSLP_EN_R = crate::BitReader; +#[doc = "Field `GBL_CSLP_EN` writer - NA"] +pub type GBL_CSLP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHNL_CSLP_EN` reader - NA"] +pub type CHNL_CSLP_EN_R = crate::BitReader; +#[doc = "Field `CHNL_CSLP_EN` writer - NA"] +pub type CHNL_CSLP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SBIU_CSLP_EN` reader - NA"] +pub type SBIU_CSLP_EN_R = crate::BitReader; +#[doc = "Field `SBIU_CSLP_EN` writer - NA"] +pub type SBIU_CSLP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MXIF_CSLP_EN` reader - NA"] +pub type MXIF_CSLP_EN_R = crate::BitReader; +#[doc = "Field `MXIF_CSLP_EN` writer - NA"] +pub type MXIF_CSLP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn gbl_cslp_en(&self) -> GBL_CSLP_EN_R { + GBL_CSLP_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn chnl_cslp_en(&self) -> CHNL_CSLP_EN_R { + CHNL_CSLP_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn sbiu_cslp_en(&self) -> SBIU_CSLP_EN_R { + SBIU_CSLP_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn mxif_cslp_en(&self) -> MXIF_CSLP_EN_R { + MXIF_CSLP_EN_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LOWPOWER_CFG0") + .field("gbl_cslp_en", &format_args!("{}", self.gbl_cslp_en().bit())) + .field( + "chnl_cslp_en", + &format_args!("{}", self.chnl_cslp_en().bit()), + ) + .field( + "sbiu_cslp_en", + &format_args!("{}", self.sbiu_cslp_en().bit()), + ) + .field( + "mxif_cslp_en", + &format_args!("{}", self.mxif_cslp_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn gbl_cslp_en(&mut self) -> GBL_CSLP_EN_W { + GBL_CSLP_EN_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn chnl_cslp_en(&mut self) -> CHNL_CSLP_EN_W { + CHNL_CSLP_EN_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn sbiu_cslp_en(&mut self) -> SBIU_CSLP_EN_W { + SBIU_CSLP_EN_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn mxif_cslp_en(&mut self) -> MXIF_CSLP_EN_W { + MXIF_CSLP_EN_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpower_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lowpower_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LOWPOWER_CFG0_SPEC; +impl crate::RegisterSpec for LOWPOWER_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lowpower_cfg0::R`](R) reader structure"] +impl crate::Readable for LOWPOWER_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lowpower_cfg0::W`](W) writer structure"] +impl crate::Writable for LOWPOWER_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LOWPOWER_CFG0 to value 0x0f"] +impl crate::Resettable for LOWPOWER_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/dma/lowpower_cfg1.rs b/esp32p4/src/dma/lowpower_cfg1.rs new file mode 100644 index 0000000000..edb5346450 --- /dev/null +++ b/esp32p4/src/dma/lowpower_cfg1.rs @@ -0,0 +1,95 @@ +#[doc = "Register `LOWPOWER_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `LOWPOWER_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `GLCH_LPDLY` reader - NA"] +pub type GLCH_LPDLY_R = crate::FieldReader; +#[doc = "Field `GLCH_LPDLY` writer - NA"] +pub type GLCH_LPDLY_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SBIU_LPDLY` reader - NA"] +pub type SBIU_LPDLY_R = crate::FieldReader; +#[doc = "Field `SBIU_LPDLY` writer - NA"] +pub type SBIU_LPDLY_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `MXIF_LPDLY` reader - NA"] +pub type MXIF_LPDLY_R = crate::FieldReader; +#[doc = "Field `MXIF_LPDLY` writer - NA"] +pub type MXIF_LPDLY_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + pub fn glch_lpdly(&self) -> GLCH_LPDLY_R { + GLCH_LPDLY_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + pub fn sbiu_lpdly(&self) -> SBIU_LPDLY_R { + SBIU_LPDLY_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn mxif_lpdly(&self) -> MXIF_LPDLY_R { + MXIF_LPDLY_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LOWPOWER_CFG1") + .field("glch_lpdly", &format_args!("{}", self.glch_lpdly().bits())) + .field("sbiu_lpdly", &format_args!("{}", self.sbiu_lpdly().bits())) + .field("mxif_lpdly", &format_args!("{}", self.mxif_lpdly().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + #[must_use] + pub fn glch_lpdly(&mut self) -> GLCH_LPDLY_W { + GLCH_LPDLY_W::new(self, 0) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + #[must_use] + pub fn sbiu_lpdly(&mut self) -> SBIU_LPDLY_W { + SBIU_LPDLY_W::new(self, 8) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + #[must_use] + pub fn mxif_lpdly(&mut self) -> MXIF_LPDLY_W { + MXIF_LPDLY_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpower_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lowpower_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LOWPOWER_CFG1_SPEC; +impl crate::RegisterSpec for LOWPOWER_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lowpower_cfg1::R`](R) reader structure"] +impl crate::Readable for LOWPOWER_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lowpower_cfg1::W`](W) writer structure"] +impl crate::Writable for LOWPOWER_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LOWPOWER_CFG1 to value 0x0040_4040"] +impl crate::Resettable for LOWPOWER_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0x0040_4040; +} diff --git a/esp32p4/src/dma/reset0.rs b/esp32p4/src/dma/reset0.rs new file mode 100644 index 0000000000..3d3f4e504a --- /dev/null +++ b/esp32p4/src/dma/reset0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RESET0` reader"] +pub type R = crate::R; +#[doc = "Register `RESET0` writer"] +pub type W = crate::W; +#[doc = "Field `DMAC_RST` reader - NA"] +pub type DMAC_RST_R = crate::BitReader; +#[doc = "Field `DMAC_RST` writer - NA"] +pub type DMAC_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn dmac_rst(&self) -> DMAC_RST_R { + DMAC_RST_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESET0") + .field("dmac_rst", &format_args!("{}", self.dmac_rst().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn dmac_rst(&mut self) -> DMAC_RST_W { + DMAC_RST_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESET0_SPEC; +impl crate::RegisterSpec for RESET0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reset0::R`](R) reader structure"] +impl crate::Readable for RESET0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reset0::W`](W) writer structure"] +impl crate::Writable for RESET0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESET0 to value 0"] +impl crate::Resettable for RESET0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds.rs b/esp32p4/src/ds.rs new file mode 100644 index 0000000000..bb150ba6e4 --- /dev/null +++ b/esp32p4/src/ds.rs @@ -0,0 +1,150 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + y_mem: [Y_MEM; 512], + m_mem: [M_MEM; 512], + rb_mem: [RB_MEM; 512], + box_mem: [BOX_MEM; 48], + iv_mem: [IV_MEM; 16], + _reserved5: [u8; 0x01c0], + x_mem: [X_MEM; 512], + z_mem: [Z_MEM; 512], + _reserved7: [u8; 0x0200], + set_start: SET_START, + set_continue: SET_CONTINUE, + set_finish: SET_FINISH, + query_busy: QUERY_BUSY, + query_key_wrong: QUERY_KEY_WRONG, + query_check: QUERY_CHECK, + _reserved13: [u8; 0x08], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00..0x200 - memory that stores Y"] + #[inline(always)] + pub const fn y_mem(&self, n: usize) -> &Y_MEM { + &self.y_mem[n] + } + #[doc = "0x200..0x400 - memory that stores M"] + #[inline(always)] + pub const fn m_mem(&self, n: usize) -> &M_MEM { + &self.m_mem[n] + } + #[doc = "0x400..0x600 - memory that stores Rb"] + #[inline(always)] + pub const fn rb_mem(&self, n: usize) -> &RB_MEM { + &self.rb_mem[n] + } + #[doc = "0x600..0x630 - memory that stores BOX"] + #[inline(always)] + pub const fn box_mem(&self, n: usize) -> &BOX_MEM { + &self.box_mem[n] + } + #[doc = "0x630..0x640 - memory that stores IV"] + #[inline(always)] + pub const fn iv_mem(&self, n: usize) -> &IV_MEM { + &self.iv_mem[n] + } + #[doc = "0x800..0xa00 - memory that stores X"] + #[inline(always)] + pub const fn x_mem(&self, n: usize) -> &X_MEM { + &self.x_mem[n] + } + #[doc = "0xa00..0xc00 - memory that stores Z"] + #[inline(always)] + pub const fn z_mem(&self, n: usize) -> &Z_MEM { + &self.z_mem[n] + } + #[doc = "0xe00 - DS start control register"] + #[inline(always)] + pub const fn set_start(&self) -> &SET_START { + &self.set_start + } + #[doc = "0xe04 - DS continue control register"] + #[inline(always)] + pub const fn set_continue(&self) -> &SET_CONTINUE { + &self.set_continue + } + #[doc = "0xe08 - DS finish control register"] + #[inline(always)] + pub const fn set_finish(&self) -> &SET_FINISH { + &self.set_finish + } + #[doc = "0xe0c - DS query busy register"] + #[inline(always)] + pub const fn query_busy(&self) -> &QUERY_BUSY { + &self.query_busy + } + #[doc = "0xe10 - DS query key-wrong counter register"] + #[inline(always)] + pub const fn query_key_wrong(&self) -> &QUERY_KEY_WRONG { + &self.query_key_wrong + } + #[doc = "0xe14 - DS query check result register"] + #[inline(always)] + pub const fn query_check(&self) -> &QUERY_CHECK { + &self.query_check + } + #[doc = "0xe20 - DS version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "Y_MEM (rw) register accessor: memory that stores Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@y_mem`] module"] +pub type Y_MEM = crate::Reg; +#[doc = "memory that stores Y"] +pub mod y_mem; +#[doc = "M_MEM (rw) register accessor: memory that stores M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@m_mem`] module"] +pub type M_MEM = crate::Reg; +#[doc = "memory that stores M"] +pub mod m_mem; +#[doc = "RB_MEM (rw) register accessor: memory that stores Rb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rb_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rb_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rb_mem`] module"] +pub type RB_MEM = crate::Reg; +#[doc = "memory that stores Rb"] +pub mod rb_mem; +#[doc = "BOX_MEM (rw) register accessor: memory that stores BOX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`box_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`box_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@box_mem`] module"] +pub type BOX_MEM = crate::Reg; +#[doc = "memory that stores BOX"] +pub mod box_mem; +#[doc = "IV_MEM (rw) register accessor: memory that stores IV\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iv_mem`] module"] +pub type IV_MEM = crate::Reg; +#[doc = "memory that stores IV"] +pub mod iv_mem; +#[doc = "X_MEM (rw) register accessor: memory that stores X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@x_mem`] module"] +pub type X_MEM = crate::Reg; +#[doc = "memory that stores X"] +pub mod x_mem; +#[doc = "Z_MEM (rw) register accessor: memory that stores Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@z_mem`] module"] +pub type Z_MEM = crate::Reg; +#[doc = "memory that stores Z"] +pub mod z_mem; +#[doc = "SET_START (w) register accessor: DS start control register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_start::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_start`] module"] +pub type SET_START = crate::Reg; +#[doc = "DS start control register"] +pub mod set_start; +#[doc = "SET_CONTINUE (w) register accessor: DS continue control register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_continue::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_continue`] module"] +pub type SET_CONTINUE = crate::Reg; +#[doc = "DS continue control register"] +pub mod set_continue; +#[doc = "SET_FINISH (w) register accessor: DS finish control register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_finish::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_finish`] module"] +pub type SET_FINISH = crate::Reg; +#[doc = "DS finish control register"] +pub mod set_finish; +#[doc = "QUERY_BUSY (r) register accessor: DS query busy register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@query_busy`] module"] +pub type QUERY_BUSY = crate::Reg; +#[doc = "DS query busy register"] +pub mod query_busy; +#[doc = "QUERY_KEY_WRONG (r) register accessor: DS query key-wrong counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_key_wrong::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@query_key_wrong`] module"] +pub type QUERY_KEY_WRONG = crate::Reg; +#[doc = "DS query key-wrong counter register"] +pub mod query_key_wrong; +#[doc = "QUERY_CHECK (r) register accessor: DS query check result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_check::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@query_check`] module"] +pub type QUERY_CHECK = crate::Reg; +#[doc = "DS query check result register"] +pub mod query_check; +#[doc = "DATE (rw) register accessor: DS version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "DS version control register"] +pub mod date; diff --git a/esp32p4/src/ds/box_mem.rs b/esp32p4/src/ds/box_mem.rs new file mode 100644 index 0000000000..3a6c89c5f4 --- /dev/null +++ b/esp32p4/src/ds/box_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `BOX_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `BOX_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "memory that stores BOX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`box_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`box_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOX_MEM_SPEC; +impl crate::RegisterSpec for BOX_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`box_mem::R`](R) reader structure"] +impl crate::Readable for BOX_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`box_mem::W`](W) writer structure"] +impl crate::Writable for BOX_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BOX_MEM[%s] to value 0"] +impl crate::Resettable for BOX_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/date.rs b/esp32p4/src/ds/date.rs new file mode 100644 index 0000000000..601214cd55 --- /dev/null +++ b/esp32p4/src/ds/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - ds version information"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - ds version information"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 0:29 - ds version information"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x3fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:29 - ds version information"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DS version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x2020_0618"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2020_0618; +} diff --git a/esp32p4/src/ds/iv_mem.rs b/esp32p4/src/ds/iv_mem.rs new file mode 100644 index 0000000000..45f47b6701 --- /dev/null +++ b/esp32p4/src/ds/iv_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `IV_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `IV_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "memory that stores IV\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IV_MEM_SPEC; +impl crate::RegisterSpec for IV_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`iv_mem::R`](R) reader structure"] +impl crate::Readable for IV_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`iv_mem::W`](W) writer structure"] +impl crate::Writable for IV_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IV_MEM[%s] to value 0"] +impl crate::Resettable for IV_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/m_mem.rs b/esp32p4/src/ds/m_mem.rs new file mode 100644 index 0000000000..901ef33775 --- /dev/null +++ b/esp32p4/src/ds/m_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `M_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `M_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "memory that stores M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M_MEM_SPEC; +impl crate::RegisterSpec for M_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`m_mem::R`](R) reader structure"] +impl crate::Readable for M_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m_mem::W`](W) writer structure"] +impl crate::Writable for M_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets M_MEM[%s] to value 0"] +impl crate::Resettable for M_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/query_busy.rs b/esp32p4/src/ds/query_busy.rs new file mode 100644 index 0000000000..18c6e4ad22 --- /dev/null +++ b/esp32p4/src/ds/query_busy.rs @@ -0,0 +1,36 @@ +#[doc = "Register `QUERY_BUSY` reader"] +pub type R = crate::R; +#[doc = "Field `QUERY_BUSY` reader - digital signature state. 1'b0: idle, 1'b1: busy"] +pub type QUERY_BUSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - digital signature state. 1'b0: idle, 1'b1: busy"] + #[inline(always)] + pub fn query_busy(&self) -> QUERY_BUSY_R { + QUERY_BUSY_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("QUERY_BUSY") + .field("query_busy", &format_args!("{}", self.query_busy().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "DS query busy register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QUERY_BUSY_SPEC; +impl crate::RegisterSpec for QUERY_BUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`query_busy::R`](R) reader structure"] +impl crate::Readable for QUERY_BUSY_SPEC {} +#[doc = "`reset()` method sets QUERY_BUSY to value 0"] +impl crate::Resettable for QUERY_BUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/query_check.rs b/esp32p4/src/ds/query_check.rs new file mode 100644 index 0000000000..dbd5f627f7 --- /dev/null +++ b/esp32p4/src/ds/query_check.rs @@ -0,0 +1,44 @@ +#[doc = "Register `QUERY_CHECK` reader"] +pub type R = crate::R; +#[doc = "Field `MD_ERROR` reader - MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail"] +pub type MD_ERROR_R = crate::BitReader; +#[doc = "Field `PADDING_BAD` reader - padding checkout result. 1'b0: a good padding, 1'b1: a bad padding"] +pub type PADDING_BAD_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail"] + #[inline(always)] + pub fn md_error(&self) -> MD_ERROR_R { + MD_ERROR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - padding checkout result. 1'b0: a good padding, 1'b1: a bad padding"] + #[inline(always)] + pub fn padding_bad(&self) -> PADDING_BAD_R { + PADDING_BAD_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("QUERY_CHECK") + .field("md_error", &format_args!("{}", self.md_error().bit())) + .field("padding_bad", &format_args!("{}", self.padding_bad().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "DS query check result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_check::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QUERY_CHECK_SPEC; +impl crate::RegisterSpec for QUERY_CHECK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`query_check::R`](R) reader structure"] +impl crate::Readable for QUERY_CHECK_SPEC {} +#[doc = "`reset()` method sets QUERY_CHECK to value 0"] +impl crate::Resettable for QUERY_CHECK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/query_key_wrong.rs b/esp32p4/src/ds/query_key_wrong.rs new file mode 100644 index 0000000000..604f955d55 --- /dev/null +++ b/esp32p4/src/ds/query_key_wrong.rs @@ -0,0 +1,39 @@ +#[doc = "Register `QUERY_KEY_WRONG` reader"] +pub type R = crate::R; +#[doc = "Field `QUERY_KEY_WRONG` reader - digital signature key wrong counter"] +pub type QUERY_KEY_WRONG_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - digital signature key wrong counter"] + #[inline(always)] + pub fn query_key_wrong(&self) -> QUERY_KEY_WRONG_R { + QUERY_KEY_WRONG_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("QUERY_KEY_WRONG") + .field( + "query_key_wrong", + &format_args!("{}", self.query_key_wrong().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "DS query key-wrong counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_key_wrong::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QUERY_KEY_WRONG_SPEC; +impl crate::RegisterSpec for QUERY_KEY_WRONG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`query_key_wrong::R`](R) reader structure"] +impl crate::Readable for QUERY_KEY_WRONG_SPEC {} +#[doc = "`reset()` method sets QUERY_KEY_WRONG to value 0"] +impl crate::Resettable for QUERY_KEY_WRONG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/rb_mem.rs b/esp32p4/src/ds/rb_mem.rs new file mode 100644 index 0000000000..85a432ea1c --- /dev/null +++ b/esp32p4/src/ds/rb_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `RB_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `RB_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "memory that stores Rb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rb_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rb_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RB_MEM_SPEC; +impl crate::RegisterSpec for RB_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`rb_mem::R`](R) reader structure"] +impl crate::Readable for RB_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rb_mem::W`](W) writer structure"] +impl crate::Writable for RB_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RB_MEM[%s] to value 0"] +impl crate::Resettable for RB_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/set_continue.rs b/esp32p4/src/ds/set_continue.rs new file mode 100644 index 0000000000..89a4ca2d61 --- /dev/null +++ b/esp32p4/src/ds/set_continue.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_CONTINUE` writer"] +pub type W = crate::W; +#[doc = "Field `SET_CONTINUE` writer - set this bit to continue DS operation."] +pub type SET_CONTINUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - set this bit to continue DS operation."] + #[inline(always)] + #[must_use] + pub fn set_continue(&mut self) -> SET_CONTINUE_W { + SET_CONTINUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DS continue control register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_continue::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_CONTINUE_SPEC; +impl crate::RegisterSpec for SET_CONTINUE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_continue::W`](W) writer structure"] +impl crate::Writable for SET_CONTINUE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_CONTINUE to value 0"] +impl crate::Resettable for SET_CONTINUE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/set_finish.rs b/esp32p4/src/ds/set_finish.rs new file mode 100644 index 0000000000..ddc1609ab3 --- /dev/null +++ b/esp32p4/src/ds/set_finish.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_FINISH` writer"] +pub type W = crate::W; +#[doc = "Field `SET_FINISH` writer - Set this bit to finish DS process."] +pub type SET_FINISH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to finish DS process."] + #[inline(always)] + #[must_use] + pub fn set_finish(&mut self) -> SET_FINISH_W { + SET_FINISH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DS finish control register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_finish::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_FINISH_SPEC; +impl crate::RegisterSpec for SET_FINISH_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_finish::W`](W) writer structure"] +impl crate::Writable for SET_FINISH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_FINISH to value 0"] +impl crate::Resettable for SET_FINISH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/set_start.rs b/esp32p4/src/ds/set_start.rs new file mode 100644 index 0000000000..f5707e89ea --- /dev/null +++ b/esp32p4/src/ds/set_start.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_START` writer"] +pub type W = crate::W; +#[doc = "Field `SET_START` writer - set this bit to start DS operation."] +pub type SET_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - set this bit to start DS operation."] + #[inline(always)] + #[must_use] + pub fn set_start(&mut self) -> SET_START_W { + SET_START_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DS start control register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_start::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_START_SPEC; +impl crate::RegisterSpec for SET_START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_start::W`](W) writer structure"] +impl crate::Writable for SET_START_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_START to value 0"] +impl crate::Resettable for SET_START_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/x_mem.rs b/esp32p4/src/ds/x_mem.rs new file mode 100644 index 0000000000..8659ee8088 --- /dev/null +++ b/esp32p4/src/ds/x_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `X_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `X_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "memory that stores X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct X_MEM_SPEC; +impl crate::RegisterSpec for X_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`x_mem::R`](R) reader structure"] +impl crate::Readable for X_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`x_mem::W`](W) writer structure"] +impl crate::Writable for X_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets X_MEM[%s] to value 0"] +impl crate::Resettable for X_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/y_mem.rs b/esp32p4/src/ds/y_mem.rs new file mode 100644 index 0000000000..0566342861 --- /dev/null +++ b/esp32p4/src/ds/y_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `Y_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `Y_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "memory that stores Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Y_MEM_SPEC; +impl crate::RegisterSpec for Y_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`y_mem::R`](R) reader structure"] +impl crate::Readable for Y_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`y_mem::W`](W) writer structure"] +impl crate::Writable for Y_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets Y_MEM[%s] to value 0"] +impl crate::Resettable for Y_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ds/z_mem.rs b/esp32p4/src/ds/z_mem.rs new file mode 100644 index 0000000000..f5405f371a --- /dev/null +++ b/esp32p4/src/ds/z_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `Z_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `Z_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "memory that stores Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Z_MEM_SPEC; +impl crate::RegisterSpec for Z_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`z_mem::R`](R) reader structure"] +impl crate::Readable for Z_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`z_mem::W`](W) writer structure"] +impl crate::Writable for Z_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets Z_MEM[%s] to value 0"] +impl crate::Resettable for Z_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecc.rs b/esp32p4/src/ecc.rs new file mode 100644 index 0000000000..98ea602be8 --- /dev/null +++ b/esp32p4/src/ecc.rs @@ -0,0 +1,99 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + _reserved0: [u8; 0x0c], + mult_int_raw: MULT_INT_RAW, + mult_int_st: MULT_INT_ST, + mult_int_ena: MULT_INT_ENA, + mult_int_clr: MULT_INT_CLR, + mult_conf: MULT_CONF, + _reserved5: [u8; 0xdc], + mult_date: MULT_DATE, + k_mem: [K_MEM; 32], + px_mem: [PX_MEM; 32], + py_mem: [PY_MEM; 32], +} +impl RegisterBlock { + #[doc = "0x0c - ECC interrupt raw register, valid in level."] + #[inline(always)] + pub const fn mult_int_raw(&self) -> &MULT_INT_RAW { + &self.mult_int_raw + } + #[doc = "0x10 - ECC interrupt status register."] + #[inline(always)] + pub const fn mult_int_st(&self) -> &MULT_INT_ST { + &self.mult_int_st + } + #[doc = "0x14 - ECC interrupt enable register."] + #[inline(always)] + pub const fn mult_int_ena(&self) -> &MULT_INT_ENA { + &self.mult_int_ena + } + #[doc = "0x18 - ECC interrupt clear register."] + #[inline(always)] + pub const fn mult_int_clr(&self) -> &MULT_INT_CLR { + &self.mult_int_clr + } + #[doc = "0x1c - ECC configure register"] + #[inline(always)] + pub const fn mult_conf(&self) -> &MULT_CONF { + &self.mult_conf + } + #[doc = "0xfc - Version control register"] + #[inline(always)] + pub const fn mult_date(&self) -> &MULT_DATE { + &self.mult_date + } + #[doc = "0x100..0x120 - The memory that stores k."] + #[inline(always)] + pub const fn k_mem(&self, n: usize) -> &K_MEM { + &self.k_mem[n] + } + #[doc = "0x120..0x140 - The memory that stores Px."] + #[inline(always)] + pub const fn px_mem(&self, n: usize) -> &PX_MEM { + &self.px_mem[n] + } + #[doc = "0x140..0x160 - The memory that stores Py."] + #[inline(always)] + pub const fn py_mem(&self, n: usize) -> &PY_MEM { + &self.py_mem[n] + } +} +#[doc = "MULT_INT_RAW (r) register accessor: ECC interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mult_int_raw`] module"] +pub type MULT_INT_RAW = crate::Reg; +#[doc = "ECC interrupt raw register, valid in level."] +pub mod mult_int_raw; +#[doc = "MULT_INT_ST (r) register accessor: ECC interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mult_int_st`] module"] +pub type MULT_INT_ST = crate::Reg; +#[doc = "ECC interrupt status register."] +pub mod mult_int_st; +#[doc = "MULT_INT_ENA (rw) register accessor: ECC interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mult_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mult_int_ena`] module"] +pub type MULT_INT_ENA = crate::Reg; +#[doc = "ECC interrupt enable register."] +pub mod mult_int_ena; +#[doc = "MULT_INT_CLR (w) register accessor: ECC interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mult_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mult_int_clr`] module"] +pub type MULT_INT_CLR = crate::Reg; +#[doc = "ECC interrupt clear register."] +pub mod mult_int_clr; +#[doc = "MULT_CONF (rw) register accessor: ECC configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mult_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mult_conf`] module"] +pub type MULT_CONF = crate::Reg; +#[doc = "ECC configure register"] +pub mod mult_conf; +#[doc = "MULT_DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mult_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mult_date`] module"] +pub type MULT_DATE = crate::Reg; +#[doc = "Version control register"] +pub mod mult_date; +#[doc = "K_MEM (rw) register accessor: The memory that stores k.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`k_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`k_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@k_mem`] module"] +pub type K_MEM = crate::Reg; +#[doc = "The memory that stores k."] +pub mod k_mem; +#[doc = "PX_MEM (rw) register accessor: The memory that stores Px.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`px_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`px_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@px_mem`] module"] +pub type PX_MEM = crate::Reg; +#[doc = "The memory that stores Px."] +pub mod px_mem; +#[doc = "PY_MEM (rw) register accessor: The memory that stores Py.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`py_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`py_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@py_mem`] module"] +pub type PY_MEM = crate::Reg; +#[doc = "The memory that stores Py."] +pub mod py_mem; diff --git a/esp32p4/src/ecc/k_mem.rs b/esp32p4/src/ecc/k_mem.rs new file mode 100644 index 0000000000..d94debd138 --- /dev/null +++ b/esp32p4/src/ecc/k_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `K_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `K_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores k.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`k_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`k_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct K_MEM_SPEC; +impl crate::RegisterSpec for K_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`k_mem::R`](R) reader structure"] +impl crate::Readable for K_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`k_mem::W`](W) writer structure"] +impl crate::Writable for K_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets K_MEM[%s] to value 0"] +impl crate::Resettable for K_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecc/mult_conf.rs b/esp32p4/src/ecc/mult_conf.rs new file mode 100644 index 0000000000..e630fe5f4a --- /dev/null +++ b/esp32p4/src/ecc/mult_conf.rs @@ -0,0 +1,184 @@ +#[doc = "Register `MULT_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `MULT_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `START` reader - Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done."] +pub type START_R = crate::BitReader; +#[doc = "Field `START` writer - Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done."] +pub type START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESET` writer - Write 1 to reset ECC Accelerator."] +pub type RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `KEY_LENGTH` reader - The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256."] +pub type KEY_LENGTH_R = crate::BitReader; +#[doc = "Field `KEY_LENGTH` writer - The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256."] +pub type KEY_LENGTH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MOD_BASE` reader - The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve)"] +pub type MOD_BASE_R = crate::BitReader; +#[doc = "Field `MOD_BASE` writer - The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve)"] +pub type MOD_BASE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WORK_MODE` reader - The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division."] +pub type WORK_MODE_R = crate::FieldReader; +#[doc = "Field `WORK_MODE` writer - The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division."] +pub type WORK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SECURITY_MODE` reader - Reserved"] +pub type SECURITY_MODE_R = crate::BitReader; +#[doc = "Field `SECURITY_MODE` writer - Reserved"] +pub type SECURITY_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VERIFICATION_RESULT` reader - The verification result bit of ECC Accelerator, only valid when calculation is done."] +pub type VERIFICATION_RESULT_R = crate::BitReader; +#[doc = "Field `CLK_EN` reader - Write 1 to force on register clock gate."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Write 1 to force on register clock gate."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_CLOCK_GATE_FORCE_ON` reader - ECC memory clock gate force on register"] +pub type MEM_CLOCK_GATE_FORCE_ON_R = crate::BitReader; +#[doc = "Field `MEM_CLOCK_GATE_FORCE_ON` writer - ECC memory clock gate force on register"] +pub type MEM_CLOCK_GATE_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done."] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256."] + #[inline(always)] + pub fn key_length(&self) -> KEY_LENGTH_R { + KEY_LENGTH_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve)"] + #[inline(always)] + pub fn mod_base(&self) -> MOD_BASE_R { + MOD_BASE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division."] + #[inline(always)] + pub fn work_mode(&self) -> WORK_MODE_R { + WORK_MODE_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn security_mode(&self) -> SECURITY_MODE_R { + SECURITY_MODE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 29 - The verification result bit of ECC Accelerator, only valid when calculation is done."] + #[inline(always)] + pub fn verification_result(&self) -> VERIFICATION_RESULT_R { + VERIFICATION_RESULT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Write 1 to force on register clock gate."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - ECC memory clock gate force on register"] + #[inline(always)] + pub fn mem_clock_gate_force_on(&self) -> MEM_CLOCK_GATE_FORCE_ON_R { + MEM_CLOCK_GATE_FORCE_ON_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MULT_CONF") + .field("start", &format_args!("{}", self.start().bit())) + .field("key_length", &format_args!("{}", self.key_length().bit())) + .field("mod_base", &format_args!("{}", self.mod_base().bit())) + .field("work_mode", &format_args!("{}", self.work_mode().bits())) + .field( + "security_mode", + &format_args!("{}", self.security_mode().bit()), + ) + .field( + "verification_result", + &format_args!("{}", self.verification_result().bit()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field( + "mem_clock_gate_force_on", + &format_args!("{}", self.mem_clock_gate_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done."] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> START_W { + START_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to reset ECC Accelerator."] + #[inline(always)] + #[must_use] + pub fn reset(&mut self) -> RESET_W { + RESET_W::new(self, 1) + } + #[doc = "Bit 2 - The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256."] + #[inline(always)] + #[must_use] + pub fn key_length(&mut self) -> KEY_LENGTH_W { + KEY_LENGTH_W::new(self, 2) + } + #[doc = "Bit 3 - The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve)"] + #[inline(always)] + #[must_use] + pub fn mod_base(&mut self) -> MOD_BASE_W { + MOD_BASE_W::new(self, 3) + } + #[doc = "Bits 4:7 - The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division."] + #[inline(always)] + #[must_use] + pub fn work_mode(&mut self) -> WORK_MODE_W { + WORK_MODE_W::new(self, 4) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn security_mode(&mut self) -> SECURITY_MODE_W { + SECURITY_MODE_W::new(self, 8) + } + #[doc = "Bit 30 - Write 1 to force on register clock gate."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 30) + } + #[doc = "Bit 31 - ECC memory clock gate force on register"] + #[inline(always)] + #[must_use] + pub fn mem_clock_gate_force_on(&mut self) -> MEM_CLOCK_GATE_FORCE_ON_W { + MEM_CLOCK_GATE_FORCE_ON_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECC configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mult_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MULT_CONF_SPEC; +impl crate::RegisterSpec for MULT_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mult_conf::R`](R) reader structure"] +impl crate::Readable for MULT_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mult_conf::W`](W) writer structure"] +impl crate::Writable for MULT_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MULT_CONF to value 0"] +impl crate::Resettable for MULT_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecc/mult_date.rs b/esp32p4/src/ecc/mult_date.rs new file mode 100644 index 0000000000..39b5205f31 --- /dev/null +++ b/esp32p4/src/ecc/mult_date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MULT_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `MULT_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - ECC mult version control register"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - ECC mult version control register"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - ECC mult version control register"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MULT_DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - ECC mult version control register"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mult_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MULT_DATE_SPEC; +impl crate::RegisterSpec for MULT_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mult_date::R`](R) reader structure"] +impl crate::Readable for MULT_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mult_date::W`](W) writer structure"] +impl crate::Writable for MULT_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MULT_DATE to value 0x0230_5040"] +impl crate::Resettable for MULT_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_5040; +} diff --git a/esp32p4/src/ecc/mult_int_clr.rs b/esp32p4/src/ecc/mult_int_clr.rs new file mode 100644 index 0000000000..d2ee95edc6 --- /dev/null +++ b/esp32p4/src/ecc/mult_int_clr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `MULT_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CALC_DONE_INT_CLR` writer - Set this bit to clear the ecc_calc_done_int interrupt"] +pub type CALC_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the ecc_calc_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn calc_done_int_clr(&mut self) -> CALC_DONE_INT_CLR_W { + CALC_DONE_INT_CLR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECC interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mult_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MULT_INT_CLR_SPEC; +impl crate::RegisterSpec for MULT_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mult_int_clr::W`](W) writer structure"] +impl crate::Writable for MULT_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MULT_INT_CLR to value 0"] +impl crate::Resettable for MULT_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecc/mult_int_ena.rs b/esp32p4/src/ecc/mult_int_ena.rs new file mode 100644 index 0000000000..eaebbf97d8 --- /dev/null +++ b/esp32p4/src/ecc/mult_int_ena.rs @@ -0,0 +1,66 @@ +#[doc = "Register `MULT_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `MULT_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `CALC_DONE_INT_ENA` reader - The interrupt enable bit for the ecc_calc_done_int interrupt"] +pub type CALC_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `CALC_DONE_INT_ENA` writer - The interrupt enable bit for the ecc_calc_done_int interrupt"] +pub type CALC_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the ecc_calc_done_int interrupt"] + #[inline(always)] + pub fn calc_done_int_ena(&self) -> CALC_DONE_INT_ENA_R { + CALC_DONE_INT_ENA_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MULT_INT_ENA") + .field( + "calc_done_int_ena", + &format_args!("{}", self.calc_done_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the ecc_calc_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn calc_done_int_ena(&mut self) -> CALC_DONE_INT_ENA_W { + CALC_DONE_INT_ENA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECC interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mult_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MULT_INT_ENA_SPEC; +impl crate::RegisterSpec for MULT_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mult_int_ena::R`](R) reader structure"] +impl crate::Readable for MULT_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mult_int_ena::W`](W) writer structure"] +impl crate::Writable for MULT_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MULT_INT_ENA to value 0"] +impl crate::Resettable for MULT_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecc/mult_int_raw.rs b/esp32p4/src/ecc/mult_int_raw.rs new file mode 100644 index 0000000000..f24e745437 --- /dev/null +++ b/esp32p4/src/ecc/mult_int_raw.rs @@ -0,0 +1,39 @@ +#[doc = "Register `MULT_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `CALC_DONE_INT_RAW` reader - The raw interrupt status bit for the ecc_calc_done_int interrupt"] +pub type CALC_DONE_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the ecc_calc_done_int interrupt"] + #[inline(always)] + pub fn calc_done_int_raw(&self) -> CALC_DONE_INT_RAW_R { + CALC_DONE_INT_RAW_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MULT_INT_RAW") + .field( + "calc_done_int_raw", + &format_args!("{}", self.calc_done_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ECC interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MULT_INT_RAW_SPEC; +impl crate::RegisterSpec for MULT_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mult_int_raw::R`](R) reader structure"] +impl crate::Readable for MULT_INT_RAW_SPEC {} +#[doc = "`reset()` method sets MULT_INT_RAW to value 0"] +impl crate::Resettable for MULT_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecc/mult_int_st.rs b/esp32p4/src/ecc/mult_int_st.rs new file mode 100644 index 0000000000..4c682f4fef --- /dev/null +++ b/esp32p4/src/ecc/mult_int_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `MULT_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `CALC_DONE_INT_ST` reader - The masked interrupt status bit for the ecc_calc_done_int interrupt"] +pub type CALC_DONE_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status bit for the ecc_calc_done_int interrupt"] + #[inline(always)] + pub fn calc_done_int_st(&self) -> CALC_DONE_INT_ST_R { + CALC_DONE_INT_ST_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MULT_INT_ST") + .field( + "calc_done_int_st", + &format_args!("{}", self.calc_done_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ECC interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MULT_INT_ST_SPEC; +impl crate::RegisterSpec for MULT_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mult_int_st::R`](R) reader structure"] +impl crate::Readable for MULT_INT_ST_SPEC {} +#[doc = "`reset()` method sets MULT_INT_ST to value 0"] +impl crate::Resettable for MULT_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecc/px_mem.rs b/esp32p4/src/ecc/px_mem.rs new file mode 100644 index 0000000000..3f3f08815c --- /dev/null +++ b/esp32p4/src/ecc/px_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `PX_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `PX_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores Px.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`px_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`px_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PX_MEM_SPEC; +impl crate::RegisterSpec for PX_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`px_mem::R`](R) reader structure"] +impl crate::Readable for PX_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`px_mem::W`](W) writer structure"] +impl crate::Writable for PX_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PX_MEM[%s] to value 0"] +impl crate::Resettable for PX_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecc/py_mem.rs b/esp32p4/src/ecc/py_mem.rs new file mode 100644 index 0000000000..0baed5c1a4 --- /dev/null +++ b/esp32p4/src/ecc/py_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `PY_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `PY_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores Py.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`py_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`py_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PY_MEM_SPEC; +impl crate::RegisterSpec for PY_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`py_mem::R`](R) reader structure"] +impl crate::Readable for PY_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`py_mem::W`](W) writer structure"] +impl crate::Writable for PY_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PY_MEM[%s] to value 0"] +impl crate::Resettable for PY_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa.rs b/esp32p4/src/ecdsa.rs new file mode 100644 index 0000000000..a52ce96021 --- /dev/null +++ b/esp32p4/src/ecdsa.rs @@ -0,0 +1,213 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + _reserved0: [u8; 0x04], + conf: CONF, + clk: CLK, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + start: START, + state: STATE, + result: RESULT, + _reserved9: [u8; 0xd4], + date: DATE, + _reserved10: [u8; 0x0100], + sha_mode: SHA_MODE, + _reserved11: [u8; 0x0c], + sha_start: SHA_START, + sha_continue: SHA_CONTINUE, + sha_busy: SHA_BUSY, + _reserved14: [u8; 0x64], + message_mem: [MESSAGE_MEM; 32], + _reserved15: [u8; 0x0760], + r_mem: [R_MEM; 32], + s_mem: [S_MEM; 32], + z_mem: [Z_MEM; 32], + qax_mem: [QAX_MEM; 32], + qay_mem: [QAY_MEM; 32], +} +impl RegisterBlock { + #[doc = "0x04 - ECDSA configure register"] + #[inline(always)] + pub const fn conf(&self) -> &CONF { + &self.conf + } + #[doc = "0x08 - ECDSA clock gate register"] + #[inline(always)] + pub const fn clk(&self) -> &CLK { + &self.clk + } + #[doc = "0x0c - ECDSA interrupt raw register, valid in level."] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x10 - ECDSA interrupt status register."] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x14 - ECDSA interrupt enable register."] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x18 - ECDSA interrupt clear register."] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x1c - ECDSA start register"] + #[inline(always)] + pub const fn start(&self) -> &START { + &self.start + } + #[doc = "0x20 - ECDSA status register"] + #[inline(always)] + pub const fn state(&self) -> &STATE { + &self.state + } + #[doc = "0x24 - ECDSA result register"] + #[inline(always)] + pub const fn result(&self) -> &RESULT { + &self.result + } + #[doc = "0xfc - Version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } + #[doc = "0x200 - ECDSA control SHA register"] + #[inline(always)] + pub const fn sha_mode(&self) -> &SHA_MODE { + &self.sha_mode + } + #[doc = "0x210 - ECDSA control SHA register"] + #[inline(always)] + pub const fn sha_start(&self) -> &SHA_START { + &self.sha_start + } + #[doc = "0x214 - ECDSA control SHA register"] + #[inline(always)] + pub const fn sha_continue(&self) -> &SHA_CONTINUE { + &self.sha_continue + } + #[doc = "0x218 - ECDSA status register"] + #[inline(always)] + pub const fn sha_busy(&self) -> &SHA_BUSY { + &self.sha_busy + } + #[doc = "0x280..0x2a0 - The memory that stores message."] + #[inline(always)] + pub const fn message_mem(&self, n: usize) -> &MESSAGE_MEM { + &self.message_mem[n] + } + #[doc = "0xa00..0xa20 - The memory that stores r."] + #[inline(always)] + pub const fn r_mem(&self, n: usize) -> &R_MEM { + &self.r_mem[n] + } + #[doc = "0xa20..0xa40 - The memory that stores s."] + #[inline(always)] + pub const fn s_mem(&self, n: usize) -> &S_MEM { + &self.s_mem[n] + } + #[doc = "0xa40..0xa60 - The memory that stores software written z."] + #[inline(always)] + pub const fn z_mem(&self, n: usize) -> &Z_MEM { + &self.z_mem[n] + } + #[doc = "0xa60..0xa80 - The memory that stores x coordinates of QA or software written k."] + #[inline(always)] + pub const fn qax_mem(&self, n: usize) -> &QAX_MEM { + &self.qax_mem[n] + } + #[doc = "0xa80..0xaa0 - The memory that stores y coordinates of QA."] + #[inline(always)] + pub const fn qay_mem(&self, n: usize) -> &QAY_MEM { + &self.qay_mem[n] + } +} +#[doc = "CONF (rw) register accessor: ECDSA configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"] +pub type CONF = crate::Reg; +#[doc = "ECDSA configure register"] +pub mod conf; +#[doc = "CLK (rw) register accessor: ECDSA clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk`] module"] +pub type CLK = crate::Reg; +#[doc = "ECDSA clock gate register"] +pub mod clk; +#[doc = "INT_RAW (r) register accessor: ECDSA interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "ECDSA interrupt raw register, valid in level."] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: ECDSA interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "ECDSA interrupt status register."] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: ECDSA interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "ECDSA interrupt enable register."] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: ECDSA interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "ECDSA interrupt clear register."] +pub mod int_clr; +#[doc = "START (w) register accessor: ECDSA start register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`start::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@start`] module"] +pub type START = crate::Reg; +#[doc = "ECDSA start register"] +pub mod start; +#[doc = "STATE (r) register accessor: ECDSA status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] +pub type STATE = crate::Reg; +#[doc = "ECDSA status register"] +pub mod state; +#[doc = "RESULT (r) register accessor: ECDSA result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`result::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@result`] module"] +pub type RESULT = crate::Reg; +#[doc = "ECDSA result register"] +pub mod result; +#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version control register"] +pub mod date; +#[doc = "SHA_MODE (rw) register accessor: ECDSA control SHA register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sha_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sha_mode`] module"] +pub type SHA_MODE = crate::Reg; +#[doc = "ECDSA control SHA register"] +pub mod sha_mode; +#[doc = "SHA_START (w) register accessor: ECDSA control SHA register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sha_start::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sha_start`] module"] +pub type SHA_START = crate::Reg; +#[doc = "ECDSA control SHA register"] +pub mod sha_start; +#[doc = "SHA_CONTINUE (w) register accessor: ECDSA control SHA register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sha_continue::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sha_continue`] module"] +pub type SHA_CONTINUE = crate::Reg; +#[doc = "ECDSA control SHA register"] +pub mod sha_continue; +#[doc = "SHA_BUSY (r) register accessor: ECDSA status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha_busy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sha_busy`] module"] +pub type SHA_BUSY = crate::Reg; +#[doc = "ECDSA status register"] +pub mod sha_busy; +#[doc = "MESSAGE_MEM (rw) register accessor: The memory that stores message.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`message_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`message_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@message_mem`] module"] +pub type MESSAGE_MEM = crate::Reg; +#[doc = "The memory that stores message."] +pub mod message_mem; +#[doc = "R_MEM (rw) register accessor: The memory that stores r.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r_mem`] module"] +pub type R_MEM = crate::Reg; +#[doc = "The memory that stores r."] +pub mod r_mem; +#[doc = "S_MEM (rw) register accessor: The memory that stores s.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s_mem`] module"] +pub type S_MEM = crate::Reg; +#[doc = "The memory that stores s."] +pub mod s_mem; +#[doc = "Z_MEM (rw) register accessor: The memory that stores software written z.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@z_mem`] module"] +pub type Z_MEM = crate::Reg; +#[doc = "The memory that stores software written z."] +pub mod z_mem; +#[doc = "QAX_MEM (rw) register accessor: The memory that stores x coordinates of QA or software written k.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qax_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qax_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qax_mem`] module"] +pub type QAX_MEM = crate::Reg; +#[doc = "The memory that stores x coordinates of QA or software written k."] +pub mod qax_mem; +#[doc = "QAY_MEM (rw) register accessor: The memory that stores y coordinates of QA.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qay_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qay_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qay_mem`] module"] +pub type QAY_MEM = crate::Reg; +#[doc = "The memory that stores y coordinates of QA."] +pub mod qay_mem; diff --git a/esp32p4/src/ecdsa/clk.rs b/esp32p4/src/ecdsa/clk.rs new file mode 100644 index 0000000000..5f095dedf3 --- /dev/null +++ b/esp32p4/src/ecdsa/clk.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CLK` reader"] +pub type R = crate::R; +#[doc = "Register `CLK` writer"] +pub type W = crate::W; +#[doc = "Field `GATE_FORCE_ON` reader - Write 1 to force on register clock gate."] +pub type GATE_FORCE_ON_R = crate::BitReader; +#[doc = "Field `GATE_FORCE_ON` writer - Write 1 to force on register clock gate."] +pub type GATE_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 to force on register clock gate."] + #[inline(always)] + pub fn gate_force_on(&self) -> GATE_FORCE_ON_R { + GATE_FORCE_ON_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK") + .field( + "gate_force_on", + &format_args!("{}", self.gate_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to force on register clock gate."] + #[inline(always)] + #[must_use] + pub fn gate_force_on(&mut self) -> GATE_FORCE_ON_W { + GATE_FORCE_ON_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECDSA clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_SPEC; +impl crate::RegisterSpec for CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk::R`](R) reader structure"] +impl crate::Readable for CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"] +impl crate::Writable for CLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK to value 0"] +impl crate::Resettable for CLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/conf.rs b/esp32p4/src/ecdsa/conf.rs new file mode 100644 index 0000000000..7ef2f9c538 --- /dev/null +++ b/esp32p4/src/ecdsa/conf.rs @@ -0,0 +1,155 @@ +#[doc = "Register `CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CONF` writer"] +pub type W = crate::W; +#[doc = "Field `WORK_MODE` reader - The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid."] +pub type WORK_MODE_R = crate::FieldReader; +#[doc = "Field `WORK_MODE` writer - The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid."] +pub type WORK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ECC_CURVE` reader - The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256."] +pub type ECC_CURVE_R = crate::BitReader; +#[doc = "Field `ECC_CURVE` writer - The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256."] +pub type ECC_CURVE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOFTWARE_SET_K` reader - The source of k select bit. 0: k is automatically generated by hardware. 1: k is written by software."] +pub type SOFTWARE_SET_K_R = crate::BitReader; +#[doc = "Field `SOFTWARE_SET_K` writer - The source of k select bit. 0: k is automatically generated by hardware. 1: k is written by software."] +pub type SOFTWARE_SET_K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOFTWARE_SET_Z` reader - The source of z select bit. 0: z is generated from SHA result. 1: z is written by software."] +pub type SOFTWARE_SET_Z_R = crate::BitReader; +#[doc = "Field `SOFTWARE_SET_Z` writer - The source of z select bit. 0: z is generated from SHA result. 1: z is written by software."] +pub type SOFTWARE_SET_Z_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DETERMINISTIC_K` reader - The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by deterministic derivation algorithm."] +pub type DETERMINISTIC_K_R = crate::BitReader; +#[doc = "Field `DETERMINISTIC_K` writer - The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by deterministic derivation algorithm."] +pub type DETERMINISTIC_K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DETERMINISTIC_LOOP` reader - The (loop number - 1) value in the deterministic derivation algorithm to derive k."] +pub type DETERMINISTIC_LOOP_R = crate::FieldReader; +#[doc = "Field `DETERMINISTIC_LOOP` writer - The (loop number - 1) value in the deterministic derivation algorithm to derive k."] +pub type DETERMINISTIC_LOOP_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:1 - The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid."] + #[inline(always)] + pub fn work_mode(&self) -> WORK_MODE_R { + WORK_MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256."] + #[inline(always)] + pub fn ecc_curve(&self) -> ECC_CURVE_R { + ECC_CURVE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The source of k select bit. 0: k is automatically generated by hardware. 1: k is written by software."] + #[inline(always)] + pub fn software_set_k(&self) -> SOFTWARE_SET_K_R { + SOFTWARE_SET_K_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The source of z select bit. 0: z is generated from SHA result. 1: z is written by software."] + #[inline(always)] + pub fn software_set_z(&self) -> SOFTWARE_SET_Z_R { + SOFTWARE_SET_Z_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by deterministic derivation algorithm."] + #[inline(always)] + pub fn deterministic_k(&self) -> DETERMINISTIC_K_R { + DETERMINISTIC_K_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:21 - The (loop number - 1) value in the deterministic derivation algorithm to derive k."] + #[inline(always)] + pub fn deterministic_loop(&self) -> DETERMINISTIC_LOOP_R { + DETERMINISTIC_LOOP_R::new(((self.bits >> 6) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF") + .field("work_mode", &format_args!("{}", self.work_mode().bits())) + .field("ecc_curve", &format_args!("{}", self.ecc_curve().bit())) + .field( + "software_set_k", + &format_args!("{}", self.software_set_k().bit()), + ) + .field( + "software_set_z", + &format_args!("{}", self.software_set_z().bit()), + ) + .field( + "deterministic_k", + &format_args!("{}", self.deterministic_k().bit()), + ) + .field( + "deterministic_loop", + &format_args!("{}", self.deterministic_loop().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid."] + #[inline(always)] + #[must_use] + pub fn work_mode(&mut self) -> WORK_MODE_W { + WORK_MODE_W::new(self, 0) + } + #[doc = "Bit 2 - The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256."] + #[inline(always)] + #[must_use] + pub fn ecc_curve(&mut self) -> ECC_CURVE_W { + ECC_CURVE_W::new(self, 2) + } + #[doc = "Bit 3 - The source of k select bit. 0: k is automatically generated by hardware. 1: k is written by software."] + #[inline(always)] + #[must_use] + pub fn software_set_k(&mut self) -> SOFTWARE_SET_K_W { + SOFTWARE_SET_K_W::new(self, 3) + } + #[doc = "Bit 4 - The source of z select bit. 0: z is generated from SHA result. 1: z is written by software."] + #[inline(always)] + #[must_use] + pub fn software_set_z(&mut self) -> SOFTWARE_SET_Z_W { + SOFTWARE_SET_Z_W::new(self, 4) + } + #[doc = "Bit 5 - The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by deterministic derivation algorithm."] + #[inline(always)] + #[must_use] + pub fn deterministic_k(&mut self) -> DETERMINISTIC_K_W { + DETERMINISTIC_K_W::new(self, 5) + } + #[doc = "Bits 6:21 - The (loop number - 1) value in the deterministic derivation algorithm to derive k."] + #[inline(always)] + #[must_use] + pub fn deterministic_loop(&mut self) -> DETERMINISTIC_LOOP_W { + DETERMINISTIC_LOOP_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECDSA configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SPEC; +impl crate::RegisterSpec for CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf::R`](R) reader structure"] +impl crate::Readable for CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"] +impl crate::Writable for CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF to value 0"] +impl crate::Resettable for CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/date.rs b/esp32p4/src/ecdsa/date.rs new file mode 100644 index 0000000000..e1dd5b5fd9 --- /dev/null +++ b/esp32p4/src/ecdsa/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - ECDSA version control register"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - ECDSA version control register"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - ECDSA version control register"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - ECDSA version control register"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_4070"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_4070; +} diff --git a/esp32p4/src/ecdsa/int_clr.rs b/esp32p4/src/ecdsa/int_clr.rs new file mode 100644 index 0000000000..4261af17e3 --- /dev/null +++ b/esp32p4/src/ecdsa/int_clr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CALC_DONE_INT_CLR` writer - Set this bit to clear the ecdsa_calc_done_int interrupt"] +pub type CALC_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SHA_RELEASE_INT_CLR` writer - Set this bit to clear the ecdsa_sha_release_int interrupt"] +pub type SHA_RELEASE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the ecdsa_calc_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn calc_done_int_clr(&mut self) -> CALC_DONE_INT_CLR_W { + CALC_DONE_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the ecdsa_sha_release_int interrupt"] + #[inline(always)] + #[must_use] + pub fn sha_release_int_clr(&mut self) -> SHA_RELEASE_INT_CLR_W { + SHA_RELEASE_INT_CLR_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECDSA interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/int_ena.rs b/esp32p4/src/ecdsa/int_ena.rs new file mode 100644 index 0000000000..a07e4a4f60 --- /dev/null +++ b/esp32p4/src/ecdsa/int_ena.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `CALC_DONE_INT_ENA` reader - The interrupt enable bit for the ecdsa_calc_done_int interrupt"] +pub type CALC_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `CALC_DONE_INT_ENA` writer - The interrupt enable bit for the ecdsa_calc_done_int interrupt"] +pub type CALC_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SHA_RELEASE_INT_ENA` reader - The interrupt enable bit for the ecdsa_sha_release_int interrupt"] +pub type SHA_RELEASE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SHA_RELEASE_INT_ENA` writer - The interrupt enable bit for the ecdsa_sha_release_int interrupt"] +pub type SHA_RELEASE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the ecdsa_calc_done_int interrupt"] + #[inline(always)] + pub fn calc_done_int_ena(&self) -> CALC_DONE_INT_ENA_R { + CALC_DONE_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the ecdsa_sha_release_int interrupt"] + #[inline(always)] + pub fn sha_release_int_ena(&self) -> SHA_RELEASE_INT_ENA_R { + SHA_RELEASE_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "calc_done_int_ena", + &format_args!("{}", self.calc_done_int_ena().bit()), + ) + .field( + "sha_release_int_ena", + &format_args!("{}", self.sha_release_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the ecdsa_calc_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn calc_done_int_ena(&mut self) -> CALC_DONE_INT_ENA_W { + CALC_DONE_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the ecdsa_sha_release_int interrupt"] + #[inline(always)] + #[must_use] + pub fn sha_release_int_ena(&mut self) -> SHA_RELEASE_INT_ENA_W { + SHA_RELEASE_INT_ENA_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECDSA interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/int_raw.rs b/esp32p4/src/ecdsa/int_raw.rs new file mode 100644 index 0000000000..5530fe7c3c --- /dev/null +++ b/esp32p4/src/ecdsa/int_raw.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `CALC_DONE_INT_RAW` reader - The raw interrupt status bit for the ecdsa_calc_done_int interrupt"] +pub type CALC_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SHA_RELEASE_INT_RAW` reader - The raw interrupt status bit for the ecdsa_sha_release_int interrupt"] +pub type SHA_RELEASE_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the ecdsa_calc_done_int interrupt"] + #[inline(always)] + pub fn calc_done_int_raw(&self) -> CALC_DONE_INT_RAW_R { + CALC_DONE_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the ecdsa_sha_release_int interrupt"] + #[inline(always)] + pub fn sha_release_int_raw(&self) -> SHA_RELEASE_INT_RAW_R { + SHA_RELEASE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "calc_done_int_raw", + &format_args!("{}", self.calc_done_int_raw().bit()), + ) + .field( + "sha_release_int_raw", + &format_args!("{}", self.sha_release_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ECDSA interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/int_st.rs b/esp32p4/src/ecdsa/int_st.rs new file mode 100644 index 0000000000..77cf37954a --- /dev/null +++ b/esp32p4/src/ecdsa/int_st.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `CALC_DONE_INT_ST` reader - The masked interrupt status bit for the ecdsa_calc_done_int interrupt"] +pub type CALC_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SHA_RELEASE_INT_ST` reader - The masked interrupt status bit for the ecdsa_sha_release_int interrupt"] +pub type SHA_RELEASE_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status bit for the ecdsa_calc_done_int interrupt"] + #[inline(always)] + pub fn calc_done_int_st(&self) -> CALC_DONE_INT_ST_R { + CALC_DONE_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status bit for the ecdsa_sha_release_int interrupt"] + #[inline(always)] + pub fn sha_release_int_st(&self) -> SHA_RELEASE_INT_ST_R { + SHA_RELEASE_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "calc_done_int_st", + &format_args!("{}", self.calc_done_int_st().bit()), + ) + .field( + "sha_release_int_st", + &format_args!("{}", self.sha_release_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ECDSA interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/message_mem.rs b/esp32p4/src/ecdsa/message_mem.rs new file mode 100644 index 0000000000..19cb214c23 --- /dev/null +++ b/esp32p4/src/ecdsa/message_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `MESSAGE_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `MESSAGE_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores message.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`message_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`message_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MESSAGE_MEM_SPEC; +impl crate::RegisterSpec for MESSAGE_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`message_mem::R`](R) reader structure"] +impl crate::Readable for MESSAGE_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`message_mem::W`](W) writer structure"] +impl crate::Writable for MESSAGE_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MESSAGE_MEM[%s] to value 0"] +impl crate::Resettable for MESSAGE_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/qax_mem.rs b/esp32p4/src/ecdsa/qax_mem.rs new file mode 100644 index 0000000000..390cf5dd52 --- /dev/null +++ b/esp32p4/src/ecdsa/qax_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `QAX_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `QAX_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores x coordinates of QA or software written k.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qax_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qax_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QAX_MEM_SPEC; +impl crate::RegisterSpec for QAX_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`qax_mem::R`](R) reader structure"] +impl crate::Readable for QAX_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`qax_mem::W`](W) writer structure"] +impl crate::Writable for QAX_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets QAX_MEM[%s] to value 0"] +impl crate::Resettable for QAX_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/qay_mem.rs b/esp32p4/src/ecdsa/qay_mem.rs new file mode 100644 index 0000000000..b874e54cad --- /dev/null +++ b/esp32p4/src/ecdsa/qay_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `QAY_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `QAY_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores y coordinates of QA.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qay_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qay_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QAY_MEM_SPEC; +impl crate::RegisterSpec for QAY_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`qay_mem::R`](R) reader structure"] +impl crate::Readable for QAY_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`qay_mem::W`](W) writer structure"] +impl crate::Writable for QAY_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets QAY_MEM[%s] to value 0"] +impl crate::Resettable for QAY_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/r_mem.rs b/esp32p4/src/ecdsa/r_mem.rs new file mode 100644 index 0000000000..36268cb0fb --- /dev/null +++ b/esp32p4/src/ecdsa/r_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `R_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `R_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores r.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct R_MEM_SPEC; +impl crate::RegisterSpec for R_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`r_mem::R`](R) reader structure"] +impl crate::Readable for R_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`r_mem::W`](W) writer structure"] +impl crate::Writable for R_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets R_MEM[%s] to value 0"] +impl crate::Resettable for R_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/result.rs b/esp32p4/src/ecdsa/result.rs new file mode 100644 index 0000000000..692a6675c4 --- /dev/null +++ b/esp32p4/src/ecdsa/result.rs @@ -0,0 +1,50 @@ +#[doc = "Register `RESULT` reader"] +pub type R = crate::R; +#[doc = "Field `OPERATION_RESULT` reader - The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is done."] +pub type OPERATION_RESULT_R = crate::BitReader; +#[doc = "Field `K_VALUE_WARNING` reader - The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the curve order, then actually taken k = k mod n."] +pub type K_VALUE_WARNING_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is done."] + #[inline(always)] + pub fn operation_result(&self) -> OPERATION_RESULT_R { + OPERATION_RESULT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the curve order, then actually taken k = k mod n."] + #[inline(always)] + pub fn k_value_warning(&self) -> K_VALUE_WARNING_R { + K_VALUE_WARNING_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESULT") + .field( + "operation_result", + &format_args!("{}", self.operation_result().bit()), + ) + .field( + "k_value_warning", + &format_args!("{}", self.k_value_warning().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ECDSA result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`result::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`result::R`](R) reader structure"] +impl crate::Readable for RESULT_SPEC {} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/s_mem.rs b/esp32p4/src/ecdsa/s_mem.rs new file mode 100644 index 0000000000..103283577d --- /dev/null +++ b/esp32p4/src/ecdsa/s_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `S_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `S_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores s.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S_MEM_SPEC; +impl crate::RegisterSpec for S_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`s_mem::R`](R) reader structure"] +impl crate::Readable for S_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`s_mem::W`](W) writer structure"] +impl crate::Writable for S_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets S_MEM[%s] to value 0"] +impl crate::Resettable for S_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/sha_busy.rs b/esp32p4/src/ecdsa/sha_busy.rs new file mode 100644 index 0000000000..339dd0a036 --- /dev/null +++ b/esp32p4/src/ecdsa/sha_busy.rs @@ -0,0 +1,36 @@ +#[doc = "Register `SHA_BUSY` reader"] +pub type R = crate::R; +#[doc = "Field `SHA_BUSY` reader - The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in calculation. 0: SHA is idle."] +pub type SHA_BUSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in calculation. 0: SHA is idle."] + #[inline(always)] + pub fn sha_busy(&self) -> SHA_BUSY_R { + SHA_BUSY_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHA_BUSY") + .field("sha_busy", &format_args!("{}", self.sha_busy().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ECDSA status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha_busy::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHA_BUSY_SPEC; +impl crate::RegisterSpec for SHA_BUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sha_busy::R`](R) reader structure"] +impl crate::Readable for SHA_BUSY_SPEC {} +#[doc = "`reset()` method sets SHA_BUSY to value 0"] +impl crate::Resettable for SHA_BUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/sha_continue.rs b/esp32p4/src/ecdsa/sha_continue.rs new file mode 100644 index 0000000000..d44ab12a50 --- /dev/null +++ b/esp32p4/src/ecdsa/sha_continue.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SHA_CONTINUE` writer"] +pub type W = crate::W; +#[doc = "Field `SHA_CONTINUE` writer - Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration."] +pub type SHA_CONTINUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration."] + #[inline(always)] + #[must_use] + pub fn sha_continue(&mut self) -> SHA_CONTINUE_W { + SHA_CONTINUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECDSA control SHA register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sha_continue::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHA_CONTINUE_SPEC; +impl crate::RegisterSpec for SHA_CONTINUE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`sha_continue::W`](W) writer structure"] +impl crate::Writable for SHA_CONTINUE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SHA_CONTINUE to value 0"] +impl crate::Resettable for SHA_CONTINUE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/sha_mode.rs b/esp32p4/src/ecdsa/sha_mode.rs new file mode 100644 index 0000000000..49c593cc24 --- /dev/null +++ b/esp32p4/src/ecdsa/sha_mode.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SHA_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SHA_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SHA_MODE` reader - The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid."] +pub type SHA_MODE_R = crate::FieldReader; +#[doc = "Field `SHA_MODE` writer - The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid."] +pub type SHA_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid."] + #[inline(always)] + pub fn sha_mode(&self) -> SHA_MODE_R { + SHA_MODE_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHA_MODE") + .field("sha_mode", &format_args!("{}", self.sha_mode().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid."] + #[inline(always)] + #[must_use] + pub fn sha_mode(&mut self) -> SHA_MODE_W { + SHA_MODE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECDSA control SHA register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sha_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHA_MODE_SPEC; +impl crate::RegisterSpec for SHA_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sha_mode::R`](R) reader structure"] +impl crate::Readable for SHA_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sha_mode::W`](W) writer structure"] +impl crate::Writable for SHA_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SHA_MODE to value 0"] +impl crate::Resettable for SHA_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/sha_start.rs b/esp32p4/src/ecdsa/sha_start.rs new file mode 100644 index 0000000000..09cd179ec9 --- /dev/null +++ b/esp32p4/src/ecdsa/sha_start.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SHA_START` writer"] +pub type W = crate::W; +#[doc = "Field `SHA_START` writer - Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration."] +pub type SHA_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration."] + #[inline(always)] + #[must_use] + pub fn sha_start(&mut self) -> SHA_START_W { + SHA_START_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECDSA control SHA register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sha_start::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHA_START_SPEC; +impl crate::RegisterSpec for SHA_START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`sha_start::W`](W) writer structure"] +impl crate::Writable for SHA_START_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SHA_START to value 0"] +impl crate::Resettable for SHA_START_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/start.rs b/esp32p4/src/ecdsa/start.rs new file mode 100644 index 0000000000..66534accbf --- /dev/null +++ b/esp32p4/src/ecdsa/start.rs @@ -0,0 +1,58 @@ +#[doc = "Register `START` writer"] +pub type W = crate::W; +#[doc = "Field `START` writer - Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared after configuration."] +pub type START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOAD_DONE` writer - Write 1 to input load done signal of ECDSA Accelerator. This bit will be self-cleared after configuration."] +pub type LOAD_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GET_DONE` writer - Write 1 to input get done signal of ECDSA Accelerator. This bit will be self-cleared after configuration."] +pub type GET_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared after configuration."] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> START_W { + START_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to input load done signal of ECDSA Accelerator. This bit will be self-cleared after configuration."] + #[inline(always)] + #[must_use] + pub fn load_done(&mut self) -> LOAD_DONE_W { + LOAD_DONE_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to input get done signal of ECDSA Accelerator. This bit will be self-cleared after configuration."] + #[inline(always)] + #[must_use] + pub fn get_done(&mut self) -> GET_DONE_W { + GET_DONE_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECDSA start register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`start::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct START_SPEC; +impl crate::RegisterSpec for START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`start::W`](W) writer structure"] +impl crate::Writable for START_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets START to value 0"] +impl crate::Resettable for START_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/state.rs b/esp32p4/src/ecdsa/state.rs new file mode 100644 index 0000000000..ee37f65b22 --- /dev/null +++ b/esp32p4/src/ecdsa/state.rs @@ -0,0 +1,36 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +#[doc = "Field `BUSY` reader - The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY state."] +pub type BUSY_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY state."] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATE") + .field("busy", &format_args!("{}", self.busy().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ECDSA status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATE_SPEC; +impl crate::RegisterSpec for STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for STATE_SPEC {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for STATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ecdsa/z_mem.rs b/esp32p4/src/ecdsa/z_mem.rs new file mode 100644 index 0000000000..dc573ab265 --- /dev/null +++ b/esp32p4/src/ecdsa/z_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `Z_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `Z_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores software written z.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Z_MEM_SPEC; +impl crate::RegisterSpec for Z_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`z_mem::R`](R) reader structure"] +impl crate::Readable for Z_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`z_mem::W`](W) writer structure"] +impl crate::Writable for Z_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets Z_MEM[%s] to value 0"] +impl crate::Resettable for Z_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse.rs b/esp32p4/src/efuse.rs new file mode 100644 index 0000000000..6526a57c3f --- /dev/null +++ b/esp32p4/src/efuse.rs @@ -0,0 +1,2490 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + pgm_data0: PGM_DATA0, + pgm_data1: PGM_DATA1, + pgm_data2: PGM_DATA2, + pgm_data3: PGM_DATA3, + pgm_data4: PGM_DATA4, + pgm_data5: PGM_DATA5, + pgm_data6: PGM_DATA6, + pgm_data7: PGM_DATA7, + pgm_check_value0: PGM_CHECK_VALUE0, + pgm_check_value1: PGM_CHECK_VALUE1, + pgm_check_value2: PGM_CHECK_VALUE2, + rd_wr_dis: RD_WR_DIS, + rd_repeat_data0: RD_REPEAT_DATA0, + rd_repeat_data1: RD_REPEAT_DATA1, + rd_repeat_data2: RD_REPEAT_DATA2, + rd_repeat_data3: RD_REPEAT_DATA3, + rd_repeat_data4: RD_REPEAT_DATA4, + rd_mac_sys_0: RD_MAC_SYS_0, + rd_mac_sys_1: RD_MAC_SYS_1, + rd_mac_sys_2: RD_MAC_SYS_2, + rd_mac_sys_3: RD_MAC_SYS_3, + rd_mac_sys_4: RD_MAC_SYS_4, + rd_mac_sys_5: RD_MAC_SYS_5, + rd_sys_part1_data0: RD_SYS_PART1_DATA0, + rd_sys_part1_data1: RD_SYS_PART1_DATA1, + rd_sys_part1_data2: RD_SYS_PART1_DATA2, + rd_sys_part1_data3: RD_SYS_PART1_DATA3, + rd_sys_part1_data4: RD_SYS_PART1_DATA4, + rd_sys_part1_data5: RD_SYS_PART1_DATA5, + rd_sys_part1_data6: RD_SYS_PART1_DATA6, + rd_sys_part1_data7: RD_SYS_PART1_DATA7, + rd_usr_data0: RD_USR_DATA0, + rd_usr_data1: RD_USR_DATA1, + rd_usr_data2: RD_USR_DATA2, + rd_usr_data3: RD_USR_DATA3, + rd_usr_data4: RD_USR_DATA4, + rd_usr_data5: RD_USR_DATA5, + rd_usr_data6: RD_USR_DATA6, + rd_usr_data7: RD_USR_DATA7, + rd_key0_data0: RD_KEY0_DATA0, + rd_key0_data1: RD_KEY0_DATA1, + rd_key0_data2: RD_KEY0_DATA2, + rd_key0_data3: RD_KEY0_DATA3, + rd_key0_data4: RD_KEY0_DATA4, + rd_key0_data5: RD_KEY0_DATA5, + rd_key0_data6: RD_KEY0_DATA6, + rd_key0_data7: RD_KEY0_DATA7, + rd_key1_data0: RD_KEY1_DATA0, + rd_key1_data1: RD_KEY1_DATA1, + rd_key1_data2: RD_KEY1_DATA2, + rd_key1_data3: RD_KEY1_DATA3, + rd_key1_data4: RD_KEY1_DATA4, + rd_key1_data5: RD_KEY1_DATA5, + rd_key1_data6: RD_KEY1_DATA6, + rd_key1_data7: RD_KEY1_DATA7, + rd_key2_data0: RD_KEY2_DATA0, + rd_key2_data1: RD_KEY2_DATA1, + rd_key2_data2: RD_KEY2_DATA2, + rd_key2_data3: RD_KEY2_DATA3, + rd_key2_data4: RD_KEY2_DATA4, + rd_key2_data5: RD_KEY2_DATA5, + rd_key2_data6: RD_KEY2_DATA6, + rd_key2_data7: RD_KEY2_DATA7, + rd_key3_data0: RD_KEY3_DATA0, + rd_key3_data1: RD_KEY3_DATA1, + rd_key3_data2: RD_KEY3_DATA2, + rd_key3_data3: RD_KEY3_DATA3, + rd_key3_data4: RD_KEY3_DATA4, + rd_key3_data5: RD_KEY3_DATA5, + rd_key3_data6: RD_KEY3_DATA6, + rd_key3_data7: RD_KEY3_DATA7, + rd_key4_data0: RD_KEY4_DATA0, + rd_key4_data1: RD_KEY4_DATA1, + rd_key4_data2: RD_KEY4_DATA2, + rd_key4_data3: RD_KEY4_DATA3, + rd_key4_data4: RD_KEY4_DATA4, + rd_key4_data5: RD_KEY4_DATA5, + rd_key4_data6: RD_KEY4_DATA6, + rd_key4_data7: RD_KEY4_DATA7, + rd_key5_data0: RD_KEY5_DATA0, + rd_key5_data1: RD_KEY5_DATA1, + rd_key5_data2: RD_KEY5_DATA2, + rd_key5_data3: RD_KEY5_DATA3, + rd_key5_data4: RD_KEY5_DATA4, + rd_key5_data5: RD_KEY5_DATA5, + rd_key5_data6: RD_KEY5_DATA6, + rd_key5_data7: RD_KEY5_DATA7, + rd_sys_part2_data0: RD_SYS_PART2_DATA0, + rd_sys_part2_data1: RD_SYS_PART2_DATA1, + rd_sys_part2_data2: RD_SYS_PART2_DATA2, + rd_sys_part2_data3: RD_SYS_PART2_DATA3, + rd_sys_part2_data4: RD_SYS_PART2_DATA4, + rd_sys_part2_data5: RD_SYS_PART2_DATA5, + rd_sys_part2_data6: RD_SYS_PART2_DATA6, + rd_sys_part2_data7: RD_SYS_PART2_DATA7, + rd_repeat_err0: RD_REPEAT_ERR0, + rd_repeat_err1: RD_REPEAT_ERR1, + rd_repeat_err2: RD_REPEAT_ERR2, + rd_repeat_err3: RD_REPEAT_ERR3, + rd_repeat_err4: RD_REPEAT_ERR4, + _reserved100: [u8; 0x30], + rd_rs_err0: RD_RS_ERR0, + rd_rs_err1: RD_RS_ERR1, + clk: CLK, + conf: CONF, + status: STATUS, + cmd: CMD, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + dac_conf: DAC_CONF, + rd_tim_conf: RD_TIM_CONF, + wr_tim_conf1: WR_TIM_CONF1, + wr_tim_conf2: WR_TIM_CONF2, + wr_tim_conf0_rs_bypass: WR_TIM_CONF0_RS_BYPASS, + date: DATE, + _reserved116: [u8; 0x0600], + apb2otp_wr_dis: APB2OTP_WR_DIS, + apb2otp_blk0_backup1_w1: APB2OTP_BLK0_BACKUP1_W1, + apb2otp_blk0_backup1_w2: APB2OTP_BLK0_BACKUP1_W2, + apb2otp_blk0_backup1_w3: APB2OTP_BLK0_BACKUP1_W3, + apb2otp_blk0_backup1_w4: APB2OTP_BLK0_BACKUP1_W4, + apb2otp_blk0_backup1_w5: APB2OTP_BLK0_BACKUP1_W5, + apb2otp_blk0_backup2_w1: APB2OTP_BLK0_BACKUP2_W1, + apb2otp_blk0_backup2_w2: APB2OTP_BLK0_BACKUP2_W2, + apb2otp_blk0_backup2_w3: APB2OTP_BLK0_BACKUP2_W3, + apb2otp_blk0_backup2_w4: APB2OTP_BLK0_BACKUP2_W4, + apb2otp_blk0_backup2_w5: APB2OTP_BLK0_BACKUP2_W5, + apb2otp_blk0_backup3_w1: APB2OTP_BLK0_BACKUP3_W1, + apb2otp_blk0_backup3_w2: APB2OTP_BLK0_BACKUP3_W2, + apb2otp_blk0_backup3_w3: APB2OTP_BLK0_BACKUP3_W3, + apb2otp_blk0_backup3_w4: APB2OTP_BLK0_BACKUP3_W4, + apb2otp_blk0_backup3_w5: APB2OTP_BLK0_BACKUP3_W5, + apb2otp_blk0_backup4_w1: APB2OTP_BLK0_BACKUP4_W1, + apb2otp_blk0_backup4_w2: APB2OTP_BLK0_BACKUP4_W2, + apb2otp_blk0_backup4_w3: APB2OTP_BLK0_BACKUP4_W3, + apb2otp_blk0_backup4_w4: APB2OTP_BLK0_BACKUP4_W4, + apb2otp_blk0_backup4_w5: APB2OTP_BLK0_BACKUP4_W5, + apb2otp_blk1_w1: APB2OTP_BLK1_W1, + apb2otp_blk1_w2: APB2OTP_BLK1_W2, + apb2otp_blk1_w3: APB2OTP_BLK1_W3, + apb2otp_blk1_w4: APB2OTP_BLK1_W4, + apb2otp_blk1_w5: APB2OTP_BLK1_W5, + apb2otp_blk1_w6: APB2OTP_BLK1_W6, + apb2otp_blk1_w7: APB2OTP_BLK1_W7, + apb2otp_blk1_w8: APB2OTP_BLK1_W8, + apb2otp_blk1_w9: APB2OTP_BLK1_W9, + apb2otp_blk2_w1: APB2OTP_BLK2_W1, + apb2otp_blk2_w2: APB2OTP_BLK2_W2, + apb2otp_blk2_w3: APB2OTP_BLK2_W3, + apb2otp_blk2_w4: APB2OTP_BLK2_W4, + apb2otp_blk2_w5: APB2OTP_BLK2_W5, + apb2otp_blk2_w6: APB2OTP_BLK2_W6, + apb2otp_blk2_w7: APB2OTP_BLK2_W7, + apb2otp_blk2_w8: APB2OTP_BLK2_W8, + apb2otp_blk2_w9: APB2OTP_BLK2_W9, + apb2otp_blk2_w10: APB2OTP_BLK2_W10, + apb2otp_blk2_w11: APB2OTP_BLK2_W11, + apb2otp_blk3_w1: APB2OTP_BLK3_W1, + apb2otp_blk3_w2: APB2OTP_BLK3_W2, + apb2otp_blk3_w3: APB2OTP_BLK3_W3, + apb2otp_blk3_w4: APB2OTP_BLK3_W4, + apb2otp_blk3_w5: APB2OTP_BLK3_W5, + apb2otp_blk3_w6: APB2OTP_BLK3_W6, + apb2otp_blk3_w7: APB2OTP_BLK3_W7, + apb2otp_blk3_w8: APB2OTP_BLK3_W8, + apb2otp_blk3_w9: APB2OTP_BLK3_W9, + apb2otp_blk3_w10: APB2OTP_BLK3_W10, + apb2otp_blk3_w11: APB2OTP_BLK3_W11, + apb2otp_blk4_w1: APB2OTP_BLK4_W1, + apb2otp_blk4_w2: APB2OTP_BLK4_W2, + apb2otp_blk4_w3: APB2OTP_BLK4_W3, + apb2otp_blk4_w4: APB2OTP_BLK4_W4, + apb2otp_blk4_w5: APB2OTP_BLK4_W5, + apb2otp_blk4_w6: APB2OTP_BLK4_W6, + apb2otp_blk4_w7: APB2OTP_BLK4_W7, + apb2otp_blk4_w8: APB2OTP_BLK4_W8, + apb2otp_blk4_w9: APB2OTP_BLK4_W9, + apb2otp_blk4_w10: APB2OTP_BLK4_W10, + apb2otp_blk4_w11: APB2OTP_BLK4_W11, + apb2otp_blk5_w1: APB2OTP_BLK5_W1, + apb2otp_blk5_w2: APB2OTP_BLK5_W2, + apb2otp_blk5_w3: APB2OTP_BLK5_W3, + apb2otp_blk5_w4: APB2OTP_BLK5_W4, + apb2otp_blk5_w5: APB2OTP_BLK5_W5, + apb2otp_blk5_w6: APB2OTP_BLK5_W6, + apb2otp_blk5_w7: APB2OTP_BLK5_W7, + apb2otp_blk5_w8: APB2OTP_BLK5_W8, + apb2otp_blk5_w9: APB2OTP_BLK5_W9, + apb2otp_blk5_w10: APB2OTP_BLK5_W10, + apb2otp_blk5_w11: APB2OTP_BLK5_W11, + apb2otp_blk6_w1: APB2OTP_BLK6_W1, + apb2otp_blk6_w2: APB2OTP_BLK6_W2, + apb2otp_blk6_w3: APB2OTP_BLK6_W3, + apb2otp_blk6_w4: APB2OTP_BLK6_W4, + apb2otp_blk6_w5: APB2OTP_BLK6_W5, + apb2otp_blk6_w6: APB2OTP_BLK6_W6, + apb2otp_blk6_w7: APB2OTP_BLK6_W7, + apb2otp_blk6_w8: APB2OTP_BLK6_W8, + apb2otp_blk6_w9: APB2OTP_BLK6_W9, + apb2otp_blk6_w10: APB2OTP_BLK6_W10, + apb2otp_blk6_w11: APB2OTP_BLK6_W11, + apb2otp_blk7_w1: APB2OTP_BLK7_W1, + apb2otp_blk7_w2: APB2OTP_BLK7_W2, + apb2otp_blk7_w3: APB2OTP_BLK7_W3, + apb2otp_blk7_w4: APB2OTP_BLK7_W4, + apb2otp_blk7_w5: APB2OTP_BLK7_W5, + apb2otp_blk7_w6: APB2OTP_BLK7_W6, + apb2otp_blk7_w7: APB2OTP_BLK7_W7, + apb2otp_blk7_w8: APB2OTP_BLK7_W8, + apb2otp_blk7_w9: APB2OTP_BLK7_W9, + apb2otp_blk7_w10: APB2OTP_BLK7_W10, + apb2otp_blk7_w11: APB2OTP_BLK7_W11, + apb2otp_blk8_w1: APB2OTP_BLK8_W1, + apb2otp_blk8_w2: APB2OTP_BLK8_W2, + apb2otp_blk8_w3: APB2OTP_BLK8_W3, + apb2otp_blk8_w4: APB2OTP_BLK8_W4, + apb2otp_blk8_w5: APB2OTP_BLK8_W5, + apb2otp_blk8_w6: APB2OTP_BLK8_W6, + apb2otp_blk8_w7: APB2OTP_BLK8_W7, + apb2otp_blk8_w8: APB2OTP_BLK8_W8, + apb2otp_blk8_w9: APB2OTP_BLK8_W9, + apb2otp_blk8_w10: APB2OTP_BLK8_W10, + apb2otp_blk8_w11: APB2OTP_BLK8_W11, + apb2otp_blk9_w1: APB2OTP_BLK9_W1, + apb2otp_blk9_w2: APB2OTP_BLK9_W2, + apb2otp_blk9_w3: APB2OTP_BLK9_W3, + apb2otp_blk9_w4: APB2OTP_BLK9_W4, + apb2otp_blk9_w5: APB2OTP_BLK9_W5, + apb2otp_blk9_w6: APB2OTP_BLK9_W6, + apb2otp_blk9_w7: APB2OTP_BLK9_W7, + apb2otp_blk9_w8: APB2OTP_BLK9_W8, + apb2otp_blk9_w9: APB2OTP_BLK9_W9, + apb2otp_blk9_w10: APB2OTP_BLK9_W10, + apb2otp_blk9_w11: APB2OTP_BLK9_W11, + apb2otp_blk10_w1: APB2OTP_BLK10_W1, + apb2otp_blk10_w2: APB2OTP_BLK10_W2, + apb2otp_blk10_w3: APB2OTP_BLK10_W3, + apb2otp_blk10_w4: APB2OTP_BLK10_W4, + apb2otp_blk10_w5: APB2OTP_BLK10_W5, + apb2otp_blk10_w6: APB2OTP_BLK10_W6, + apb2otp_blk10_w7: APB2OTP_BLK10_W7, + apb2otp_blk10_w8: APB2OTP_BLK10_W8, + apb2otp_blk10_w9: APB2OTP_BLK10_W9, + apb2otp_blk10_w10: APB2OTP_BLK10_W10, + apb2otp_blk10_w11: APB2OTP_BLK10_W11, + _reserved245: [u8; 0x04], + apb2otp_en: APB2OTP_EN, +} +impl RegisterBlock { + #[doc = "0x00 - Register 0 that stores data to be programmed."] + #[inline(always)] + pub const fn pgm_data0(&self) -> &PGM_DATA0 { + &self.pgm_data0 + } + #[doc = "0x04 - Register 1 that stores data to be programmed."] + #[inline(always)] + pub const fn pgm_data1(&self) -> &PGM_DATA1 { + &self.pgm_data1 + } + #[doc = "0x08 - Register 2 that stores data to be programmed."] + #[inline(always)] + pub const fn pgm_data2(&self) -> &PGM_DATA2 { + &self.pgm_data2 + } + #[doc = "0x0c - Register 3 that stores data to be programmed."] + #[inline(always)] + pub const fn pgm_data3(&self) -> &PGM_DATA3 { + &self.pgm_data3 + } + #[doc = "0x10 - Register 4 that stores data to be programmed."] + #[inline(always)] + pub const fn pgm_data4(&self) -> &PGM_DATA4 { + &self.pgm_data4 + } + #[doc = "0x14 - Register 5 that stores data to be programmed."] + #[inline(always)] + pub const fn pgm_data5(&self) -> &PGM_DATA5 { + &self.pgm_data5 + } + #[doc = "0x18 - Register 6 that stores data to be programmed."] + #[inline(always)] + pub const fn pgm_data6(&self) -> &PGM_DATA6 { + &self.pgm_data6 + } + #[doc = "0x1c - Register 7 that stores data to be programmed."] + #[inline(always)] + pub const fn pgm_data7(&self) -> &PGM_DATA7 { + &self.pgm_data7 + } + #[doc = "0x20 - Register 0 that stores the RS code to be programmed."] + #[inline(always)] + pub const fn pgm_check_value0(&self) -> &PGM_CHECK_VALUE0 { + &self.pgm_check_value0 + } + #[doc = "0x24 - Register 1 that stores the RS code to be programmed."] + #[inline(always)] + pub const fn pgm_check_value1(&self) -> &PGM_CHECK_VALUE1 { + &self.pgm_check_value1 + } + #[doc = "0x28 - Register 2 that stores the RS code to be programmed."] + #[inline(always)] + pub const fn pgm_check_value2(&self) -> &PGM_CHECK_VALUE2 { + &self.pgm_check_value2 + } + #[doc = "0x2c - BLOCK0 data register 0."] + #[inline(always)] + pub const fn rd_wr_dis(&self) -> &RD_WR_DIS { + &self.rd_wr_dis + } + #[doc = "0x30 - BLOCK0 data register 1."] + #[inline(always)] + pub const fn rd_repeat_data0(&self) -> &RD_REPEAT_DATA0 { + &self.rd_repeat_data0 + } + #[doc = "0x34 - BLOCK0 data register 2."] + #[inline(always)] + pub const fn rd_repeat_data1(&self) -> &RD_REPEAT_DATA1 { + &self.rd_repeat_data1 + } + #[doc = "0x38 - BLOCK0 data register 3."] + #[inline(always)] + pub const fn rd_repeat_data2(&self) -> &RD_REPEAT_DATA2 { + &self.rd_repeat_data2 + } + #[doc = "0x3c - BLOCK0 data register 4."] + #[inline(always)] + pub const fn rd_repeat_data3(&self) -> &RD_REPEAT_DATA3 { + &self.rd_repeat_data3 + } + #[doc = "0x40 - BLOCK0 data register 5."] + #[inline(always)] + pub const fn rd_repeat_data4(&self) -> &RD_REPEAT_DATA4 { + &self.rd_repeat_data4 + } + #[doc = "0x44 - BLOCK1 data register $n."] + #[inline(always)] + pub const fn rd_mac_sys_0(&self) -> &RD_MAC_SYS_0 { + &self.rd_mac_sys_0 + } + #[doc = "0x48 - BLOCK1 data register $n."] + #[inline(always)] + pub const fn rd_mac_sys_1(&self) -> &RD_MAC_SYS_1 { + &self.rd_mac_sys_1 + } + #[doc = "0x4c - BLOCK1 data register $n."] + #[inline(always)] + pub const fn rd_mac_sys_2(&self) -> &RD_MAC_SYS_2 { + &self.rd_mac_sys_2 + } + #[doc = "0x50 - BLOCK1 data register $n."] + #[inline(always)] + pub const fn rd_mac_sys_3(&self) -> &RD_MAC_SYS_3 { + &self.rd_mac_sys_3 + } + #[doc = "0x54 - BLOCK1 data register $n."] + #[inline(always)] + pub const fn rd_mac_sys_4(&self) -> &RD_MAC_SYS_4 { + &self.rd_mac_sys_4 + } + #[doc = "0x58 - BLOCK1 data register $n."] + #[inline(always)] + pub const fn rd_mac_sys_5(&self) -> &RD_MAC_SYS_5 { + &self.rd_mac_sys_5 + } + #[doc = "0x5c - Register $n of BLOCK2 (system)."] + #[inline(always)] + pub const fn rd_sys_part1_data0(&self) -> &RD_SYS_PART1_DATA0 { + &self.rd_sys_part1_data0 + } + #[doc = "0x60 - Register $n of BLOCK2 (system)."] + #[inline(always)] + pub const fn rd_sys_part1_data1(&self) -> &RD_SYS_PART1_DATA1 { + &self.rd_sys_part1_data1 + } + #[doc = "0x64 - Register $n of BLOCK2 (system)."] + #[inline(always)] + pub const fn rd_sys_part1_data2(&self) -> &RD_SYS_PART1_DATA2 { + &self.rd_sys_part1_data2 + } + #[doc = "0x68 - Register $n of BLOCK2 (system)."] + #[inline(always)] + pub const fn rd_sys_part1_data3(&self) -> &RD_SYS_PART1_DATA3 { + &self.rd_sys_part1_data3 + } + #[doc = "0x6c - Register $n of BLOCK2 (system)."] + #[inline(always)] + pub const fn rd_sys_part1_data4(&self) -> &RD_SYS_PART1_DATA4 { + &self.rd_sys_part1_data4 + } + #[doc = "0x70 - Register $n of BLOCK2 (system)."] + #[inline(always)] + pub const fn rd_sys_part1_data5(&self) -> &RD_SYS_PART1_DATA5 { + &self.rd_sys_part1_data5 + } + #[doc = "0x74 - Register $n of BLOCK2 (system)."] + #[inline(always)] + pub const fn rd_sys_part1_data6(&self) -> &RD_SYS_PART1_DATA6 { + &self.rd_sys_part1_data6 + } + #[doc = "0x78 - Register $n of BLOCK2 (system)."] + #[inline(always)] + pub const fn rd_sys_part1_data7(&self) -> &RD_SYS_PART1_DATA7 { + &self.rd_sys_part1_data7 + } + #[doc = "0x7c - Register $n of BLOCK3 (user)."] + #[inline(always)] + pub const fn rd_usr_data0(&self) -> &RD_USR_DATA0 { + &self.rd_usr_data0 + } + #[doc = "0x80 - Register $n of BLOCK3 (user)."] + #[inline(always)] + pub const fn rd_usr_data1(&self) -> &RD_USR_DATA1 { + &self.rd_usr_data1 + } + #[doc = "0x84 - Register $n of BLOCK3 (user)."] + #[inline(always)] + pub const fn rd_usr_data2(&self) -> &RD_USR_DATA2 { + &self.rd_usr_data2 + } + #[doc = "0x88 - Register $n of BLOCK3 (user)."] + #[inline(always)] + pub const fn rd_usr_data3(&self) -> &RD_USR_DATA3 { + &self.rd_usr_data3 + } + #[doc = "0x8c - Register $n of BLOCK3 (user)."] + #[inline(always)] + pub const fn rd_usr_data4(&self) -> &RD_USR_DATA4 { + &self.rd_usr_data4 + } + #[doc = "0x90 - Register $n of BLOCK3 (user)."] + #[inline(always)] + pub const fn rd_usr_data5(&self) -> &RD_USR_DATA5 { + &self.rd_usr_data5 + } + #[doc = "0x94 - Register $n of BLOCK3 (user)."] + #[inline(always)] + pub const fn rd_usr_data6(&self) -> &RD_USR_DATA6 { + &self.rd_usr_data6 + } + #[doc = "0x98 - Register $n of BLOCK3 (user)."] + #[inline(always)] + pub const fn rd_usr_data7(&self) -> &RD_USR_DATA7 { + &self.rd_usr_data7 + } + #[doc = "0x9c - Register $n of BLOCK4 (KEY0)."] + #[inline(always)] + pub const fn rd_key0_data0(&self) -> &RD_KEY0_DATA0 { + &self.rd_key0_data0 + } + #[doc = "0xa0 - Register $n of BLOCK4 (KEY0)."] + #[inline(always)] + pub const fn rd_key0_data1(&self) -> &RD_KEY0_DATA1 { + &self.rd_key0_data1 + } + #[doc = "0xa4 - Register $n of BLOCK4 (KEY0)."] + #[inline(always)] + pub const fn rd_key0_data2(&self) -> &RD_KEY0_DATA2 { + &self.rd_key0_data2 + } + #[doc = "0xa8 - Register $n of BLOCK4 (KEY0)."] + #[inline(always)] + pub const fn rd_key0_data3(&self) -> &RD_KEY0_DATA3 { + &self.rd_key0_data3 + } + #[doc = "0xac - Register $n of BLOCK4 (KEY0)."] + #[inline(always)] + pub const fn rd_key0_data4(&self) -> &RD_KEY0_DATA4 { + &self.rd_key0_data4 + } + #[doc = "0xb0 - Register $n of BLOCK4 (KEY0)."] + #[inline(always)] + pub const fn rd_key0_data5(&self) -> &RD_KEY0_DATA5 { + &self.rd_key0_data5 + } + #[doc = "0xb4 - Register $n of BLOCK4 (KEY0)."] + #[inline(always)] + pub const fn rd_key0_data6(&self) -> &RD_KEY0_DATA6 { + &self.rd_key0_data6 + } + #[doc = "0xb8 - Register $n of BLOCK4 (KEY0)."] + #[inline(always)] + pub const fn rd_key0_data7(&self) -> &RD_KEY0_DATA7 { + &self.rd_key0_data7 + } + #[doc = "0xbc - Register $n of BLOCK5 (KEY1)."] + #[inline(always)] + pub const fn rd_key1_data0(&self) -> &RD_KEY1_DATA0 { + &self.rd_key1_data0 + } + #[doc = "0xc0 - Register $n of BLOCK5 (KEY1)."] + #[inline(always)] + pub const fn rd_key1_data1(&self) -> &RD_KEY1_DATA1 { + &self.rd_key1_data1 + } + #[doc = "0xc4 - Register $n of BLOCK5 (KEY1)."] + #[inline(always)] + pub const fn rd_key1_data2(&self) -> &RD_KEY1_DATA2 { + &self.rd_key1_data2 + } + #[doc = "0xc8 - Register $n of BLOCK5 (KEY1)."] + #[inline(always)] + pub const fn rd_key1_data3(&self) -> &RD_KEY1_DATA3 { + &self.rd_key1_data3 + } + #[doc = "0xcc - Register $n of BLOCK5 (KEY1)."] + #[inline(always)] + pub const fn rd_key1_data4(&self) -> &RD_KEY1_DATA4 { + &self.rd_key1_data4 + } + #[doc = "0xd0 - Register $n of BLOCK5 (KEY1)."] + #[inline(always)] + pub const fn rd_key1_data5(&self) -> &RD_KEY1_DATA5 { + &self.rd_key1_data5 + } + #[doc = "0xd4 - Register $n of BLOCK5 (KEY1)."] + #[inline(always)] + pub const fn rd_key1_data6(&self) -> &RD_KEY1_DATA6 { + &self.rd_key1_data6 + } + #[doc = "0xd8 - Register $n of BLOCK5 (KEY1)."] + #[inline(always)] + pub const fn rd_key1_data7(&self) -> &RD_KEY1_DATA7 { + &self.rd_key1_data7 + } + #[doc = "0xdc - Register $n of BLOCK6 (KEY2)."] + #[inline(always)] + pub const fn rd_key2_data0(&self) -> &RD_KEY2_DATA0 { + &self.rd_key2_data0 + } + #[doc = "0xe0 - Register $n of BLOCK6 (KEY2)."] + #[inline(always)] + pub const fn rd_key2_data1(&self) -> &RD_KEY2_DATA1 { + &self.rd_key2_data1 + } + #[doc = "0xe4 - Register $n of BLOCK6 (KEY2)."] + #[inline(always)] + pub const fn rd_key2_data2(&self) -> &RD_KEY2_DATA2 { + &self.rd_key2_data2 + } + #[doc = "0xe8 - Register $n of BLOCK6 (KEY2)."] + #[inline(always)] + pub const fn rd_key2_data3(&self) -> &RD_KEY2_DATA3 { + &self.rd_key2_data3 + } + #[doc = "0xec - Register $n of BLOCK6 (KEY2)."] + #[inline(always)] + pub const fn rd_key2_data4(&self) -> &RD_KEY2_DATA4 { + &self.rd_key2_data4 + } + #[doc = "0xf0 - Register $n of BLOCK6 (KEY2)."] + #[inline(always)] + pub const fn rd_key2_data5(&self) -> &RD_KEY2_DATA5 { + &self.rd_key2_data5 + } + #[doc = "0xf4 - Register $n of BLOCK6 (KEY2)."] + #[inline(always)] + pub const fn rd_key2_data6(&self) -> &RD_KEY2_DATA6 { + &self.rd_key2_data6 + } + #[doc = "0xf8 - Register $n of BLOCK6 (KEY2)."] + #[inline(always)] + pub const fn rd_key2_data7(&self) -> &RD_KEY2_DATA7 { + &self.rd_key2_data7 + } + #[doc = "0xfc - Register $n of BLOCK7 (KEY3)."] + #[inline(always)] + pub const fn rd_key3_data0(&self) -> &RD_KEY3_DATA0 { + &self.rd_key3_data0 + } + #[doc = "0x100 - Register $n of BLOCK7 (KEY3)."] + #[inline(always)] + pub const fn rd_key3_data1(&self) -> &RD_KEY3_DATA1 { + &self.rd_key3_data1 + } + #[doc = "0x104 - Register $n of BLOCK7 (KEY3)."] + #[inline(always)] + pub const fn rd_key3_data2(&self) -> &RD_KEY3_DATA2 { + &self.rd_key3_data2 + } + #[doc = "0x108 - Register $n of BLOCK7 (KEY3)."] + #[inline(always)] + pub const fn rd_key3_data3(&self) -> &RD_KEY3_DATA3 { + &self.rd_key3_data3 + } + #[doc = "0x10c - Register $n of BLOCK7 (KEY3)."] + #[inline(always)] + pub const fn rd_key3_data4(&self) -> &RD_KEY3_DATA4 { + &self.rd_key3_data4 + } + #[doc = "0x110 - Register $n of BLOCK7 (KEY3)."] + #[inline(always)] + pub const fn rd_key3_data5(&self) -> &RD_KEY3_DATA5 { + &self.rd_key3_data5 + } + #[doc = "0x114 - Register $n of BLOCK7 (KEY3)."] + #[inline(always)] + pub const fn rd_key3_data6(&self) -> &RD_KEY3_DATA6 { + &self.rd_key3_data6 + } + #[doc = "0x118 - Register $n of BLOCK7 (KEY3)."] + #[inline(always)] + pub const fn rd_key3_data7(&self) -> &RD_KEY3_DATA7 { + &self.rd_key3_data7 + } + #[doc = "0x11c - Register $n of BLOCK8 (KEY4)."] + #[inline(always)] + pub const fn rd_key4_data0(&self) -> &RD_KEY4_DATA0 { + &self.rd_key4_data0 + } + #[doc = "0x120 - Register $n of BLOCK8 (KEY4)."] + #[inline(always)] + pub const fn rd_key4_data1(&self) -> &RD_KEY4_DATA1 { + &self.rd_key4_data1 + } + #[doc = "0x124 - Register $n of BLOCK8 (KEY4)."] + #[inline(always)] + pub const fn rd_key4_data2(&self) -> &RD_KEY4_DATA2 { + &self.rd_key4_data2 + } + #[doc = "0x128 - Register $n of BLOCK8 (KEY4)."] + #[inline(always)] + pub const fn rd_key4_data3(&self) -> &RD_KEY4_DATA3 { + &self.rd_key4_data3 + } + #[doc = "0x12c - Register $n of BLOCK8 (KEY4)."] + #[inline(always)] + pub const fn rd_key4_data4(&self) -> &RD_KEY4_DATA4 { + &self.rd_key4_data4 + } + #[doc = "0x130 - Register $n of BLOCK8 (KEY4)."] + #[inline(always)] + pub const fn rd_key4_data5(&self) -> &RD_KEY4_DATA5 { + &self.rd_key4_data5 + } + #[doc = "0x134 - Register $n of BLOCK8 (KEY4)."] + #[inline(always)] + pub const fn rd_key4_data6(&self) -> &RD_KEY4_DATA6 { + &self.rd_key4_data6 + } + #[doc = "0x138 - Register $n of BLOCK8 (KEY4)."] + #[inline(always)] + pub const fn rd_key4_data7(&self) -> &RD_KEY4_DATA7 { + &self.rd_key4_data7 + } + #[doc = "0x13c - Register $n of BLOCK9 (KEY5)."] + #[inline(always)] + pub const fn rd_key5_data0(&self) -> &RD_KEY5_DATA0 { + &self.rd_key5_data0 + } + #[doc = "0x140 - Register $n of BLOCK9 (KEY5)."] + #[inline(always)] + pub const fn rd_key5_data1(&self) -> &RD_KEY5_DATA1 { + &self.rd_key5_data1 + } + #[doc = "0x144 - Register $n of BLOCK9 (KEY5)."] + #[inline(always)] + pub const fn rd_key5_data2(&self) -> &RD_KEY5_DATA2 { + &self.rd_key5_data2 + } + #[doc = "0x148 - Register $n of BLOCK9 (KEY5)."] + #[inline(always)] + pub const fn rd_key5_data3(&self) -> &RD_KEY5_DATA3 { + &self.rd_key5_data3 + } + #[doc = "0x14c - Register $n of BLOCK9 (KEY5)."] + #[inline(always)] + pub const fn rd_key5_data4(&self) -> &RD_KEY5_DATA4 { + &self.rd_key5_data4 + } + #[doc = "0x150 - Register $n of BLOCK9 (KEY5)."] + #[inline(always)] + pub const fn rd_key5_data5(&self) -> &RD_KEY5_DATA5 { + &self.rd_key5_data5 + } + #[doc = "0x154 - Register $n of BLOCK9 (KEY5)."] + #[inline(always)] + pub const fn rd_key5_data6(&self) -> &RD_KEY5_DATA6 { + &self.rd_key5_data6 + } + #[doc = "0x158 - Register $n of BLOCK9 (KEY5)."] + #[inline(always)] + pub const fn rd_key5_data7(&self) -> &RD_KEY5_DATA7 { + &self.rd_key5_data7 + } + #[doc = "0x15c - Register $n of BLOCK10 (system)."] + #[inline(always)] + pub const fn rd_sys_part2_data0(&self) -> &RD_SYS_PART2_DATA0 { + &self.rd_sys_part2_data0 + } + #[doc = "0x160 - Register $n of BLOCK9 (KEY5)."] + #[inline(always)] + pub const fn rd_sys_part2_data1(&self) -> &RD_SYS_PART2_DATA1 { + &self.rd_sys_part2_data1 + } + #[doc = "0x164 - Register $n of BLOCK10 (system)."] + #[inline(always)] + pub const fn rd_sys_part2_data2(&self) -> &RD_SYS_PART2_DATA2 { + &self.rd_sys_part2_data2 + } + #[doc = "0x168 - Register $n of BLOCK10 (system)."] + #[inline(always)] + pub const fn rd_sys_part2_data3(&self) -> &RD_SYS_PART2_DATA3 { + &self.rd_sys_part2_data3 + } + #[doc = "0x16c - Register $n of BLOCK10 (system)."] + #[inline(always)] + pub const fn rd_sys_part2_data4(&self) -> &RD_SYS_PART2_DATA4 { + &self.rd_sys_part2_data4 + } + #[doc = "0x170 - Register $n of BLOCK10 (system)."] + #[inline(always)] + pub const fn rd_sys_part2_data5(&self) -> &RD_SYS_PART2_DATA5 { + &self.rd_sys_part2_data5 + } + #[doc = "0x174 - Register $n of BLOCK10 (system)."] + #[inline(always)] + pub const fn rd_sys_part2_data6(&self) -> &RD_SYS_PART2_DATA6 { + &self.rd_sys_part2_data6 + } + #[doc = "0x178 - Register $n of BLOCK10 (system)."] + #[inline(always)] + pub const fn rd_sys_part2_data7(&self) -> &RD_SYS_PART2_DATA7 { + &self.rd_sys_part2_data7 + } + #[doc = "0x17c - Programming error record register 0 of BLOCK0."] + #[inline(always)] + pub const fn rd_repeat_err0(&self) -> &RD_REPEAT_ERR0 { + &self.rd_repeat_err0 + } + #[doc = "0x180 - Programming error record register 1 of BLOCK0."] + #[inline(always)] + pub const fn rd_repeat_err1(&self) -> &RD_REPEAT_ERR1 { + &self.rd_repeat_err1 + } + #[doc = "0x184 - Programming error record register 2 of BLOCK0."] + #[inline(always)] + pub const fn rd_repeat_err2(&self) -> &RD_REPEAT_ERR2 { + &self.rd_repeat_err2 + } + #[doc = "0x188 - Programming error record register 3 of BLOCK0."] + #[inline(always)] + pub const fn rd_repeat_err3(&self) -> &RD_REPEAT_ERR3 { + &self.rd_repeat_err3 + } + #[doc = "0x18c - Programming error record register 4 of BLOCK0."] + #[inline(always)] + pub const fn rd_repeat_err4(&self) -> &RD_REPEAT_ERR4 { + &self.rd_repeat_err4 + } + #[doc = "0x1c0 - Programming error record register 0 of BLOCK1-10."] + #[inline(always)] + pub const fn rd_rs_err0(&self) -> &RD_RS_ERR0 { + &self.rd_rs_err0 + } + #[doc = "0x1c4 - Programming error record register 1 of BLOCK1-10."] + #[inline(always)] + pub const fn rd_rs_err1(&self) -> &RD_RS_ERR1 { + &self.rd_rs_err1 + } + #[doc = "0x1c8 - eFuse clcok configuration register."] + #[inline(always)] + pub const fn clk(&self) -> &CLK { + &self.clk + } + #[doc = "0x1cc - eFuse operation mode configuraiton register"] + #[inline(always)] + pub const fn conf(&self) -> &CONF { + &self.conf + } + #[doc = "0x1d0 - eFuse status register."] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0x1d4 - eFuse command register."] + #[inline(always)] + pub const fn cmd(&self) -> &CMD { + &self.cmd + } + #[doc = "0x1d8 - eFuse raw interrupt register."] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x1dc - eFuse interrupt status register."] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x1e0 - eFuse interrupt enable register."] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x1e4 - eFuse interrupt clear register."] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x1e8 - Controls the eFuse programming voltage."] + #[inline(always)] + pub const fn dac_conf(&self) -> &DAC_CONF { + &self.dac_conf + } + #[doc = "0x1ec - Configures read timing parameters."] + #[inline(always)] + pub const fn rd_tim_conf(&self) -> &RD_TIM_CONF { + &self.rd_tim_conf + } + #[doc = "0x1f0 - Configurarion register 1 of eFuse programming timing parameters."] + #[inline(always)] + pub const fn wr_tim_conf1(&self) -> &WR_TIM_CONF1 { + &self.wr_tim_conf1 + } + #[doc = "0x1f4 - Configurarion register 2 of eFuse programming timing parameters."] + #[inline(always)] + pub const fn wr_tim_conf2(&self) -> &WR_TIM_CONF2 { + &self.wr_tim_conf2 + } + #[doc = "0x1f8 - Configurarion register0 of eFuse programming time parameters and rs bypass operation."] + #[inline(always)] + pub const fn wr_tim_conf0_rs_bypass(&self) -> &WR_TIM_CONF0_RS_BYPASS { + &self.wr_tim_conf0_rs_bypass + } + #[doc = "0x1fc - eFuse version register."] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } + #[doc = "0x800 - eFuse apb2otp block0 data register1."] + #[inline(always)] + pub const fn apb2otp_wr_dis(&self) -> &APB2OTP_WR_DIS { + &self.apb2otp_wr_dis + } + #[doc = "0x804 - eFuse apb2otp block0 data register2."] + #[inline(always)] + pub const fn apb2otp_blk0_backup1_w1(&self) -> &APB2OTP_BLK0_BACKUP1_W1 { + &self.apb2otp_blk0_backup1_w1 + } + #[doc = "0x808 - eFuse apb2otp block0 data register3."] + #[inline(always)] + pub const fn apb2otp_blk0_backup1_w2(&self) -> &APB2OTP_BLK0_BACKUP1_W2 { + &self.apb2otp_blk0_backup1_w2 + } + #[doc = "0x80c - eFuse apb2otp block0 data register4."] + #[inline(always)] + pub const fn apb2otp_blk0_backup1_w3(&self) -> &APB2OTP_BLK0_BACKUP1_W3 { + &self.apb2otp_blk0_backup1_w3 + } + #[doc = "0x810 - eFuse apb2otp block0 data register5."] + #[inline(always)] + pub const fn apb2otp_blk0_backup1_w4(&self) -> &APB2OTP_BLK0_BACKUP1_W4 { + &self.apb2otp_blk0_backup1_w4 + } + #[doc = "0x814 - eFuse apb2otp block0 data register6."] + #[inline(always)] + pub const fn apb2otp_blk0_backup1_w5(&self) -> &APB2OTP_BLK0_BACKUP1_W5 { + &self.apb2otp_blk0_backup1_w5 + } + #[doc = "0x818 - eFuse apb2otp block0 data register7."] + #[inline(always)] + pub const fn apb2otp_blk0_backup2_w1(&self) -> &APB2OTP_BLK0_BACKUP2_W1 { + &self.apb2otp_blk0_backup2_w1 + } + #[doc = "0x81c - eFuse apb2otp block0 data register8."] + #[inline(always)] + pub const fn apb2otp_blk0_backup2_w2(&self) -> &APB2OTP_BLK0_BACKUP2_W2 { + &self.apb2otp_blk0_backup2_w2 + } + #[doc = "0x820 - eFuse apb2otp block0 data register9."] + #[inline(always)] + pub const fn apb2otp_blk0_backup2_w3(&self) -> &APB2OTP_BLK0_BACKUP2_W3 { + &self.apb2otp_blk0_backup2_w3 + } + #[doc = "0x824 - eFuse apb2otp block0 data register10."] + #[inline(always)] + pub const fn apb2otp_blk0_backup2_w4(&self) -> &APB2OTP_BLK0_BACKUP2_W4 { + &self.apb2otp_blk0_backup2_w4 + } + #[doc = "0x828 - eFuse apb2otp block0 data register11."] + #[inline(always)] + pub const fn apb2otp_blk0_backup2_w5(&self) -> &APB2OTP_BLK0_BACKUP2_W5 { + &self.apb2otp_blk0_backup2_w5 + } + #[doc = "0x82c - eFuse apb2otp block0 data register12."] + #[inline(always)] + pub const fn apb2otp_blk0_backup3_w1(&self) -> &APB2OTP_BLK0_BACKUP3_W1 { + &self.apb2otp_blk0_backup3_w1 + } + #[doc = "0x830 - eFuse apb2otp block0 data register13."] + #[inline(always)] + pub const fn apb2otp_blk0_backup3_w2(&self) -> &APB2OTP_BLK0_BACKUP3_W2 { + &self.apb2otp_blk0_backup3_w2 + } + #[doc = "0x834 - eFuse apb2otp block0 data register14."] + #[inline(always)] + pub const fn apb2otp_blk0_backup3_w3(&self) -> &APB2OTP_BLK0_BACKUP3_W3 { + &self.apb2otp_blk0_backup3_w3 + } + #[doc = "0x838 - eFuse apb2otp block0 data register15."] + #[inline(always)] + pub const fn apb2otp_blk0_backup3_w4(&self) -> &APB2OTP_BLK0_BACKUP3_W4 { + &self.apb2otp_blk0_backup3_w4 + } + #[doc = "0x83c - eFuse apb2otp block0 data register16."] + #[inline(always)] + pub const fn apb2otp_blk0_backup3_w5(&self) -> &APB2OTP_BLK0_BACKUP3_W5 { + &self.apb2otp_blk0_backup3_w5 + } + #[doc = "0x840 - eFuse apb2otp block0 data register17."] + #[inline(always)] + pub const fn apb2otp_blk0_backup4_w1(&self) -> &APB2OTP_BLK0_BACKUP4_W1 { + &self.apb2otp_blk0_backup4_w1 + } + #[doc = "0x844 - eFuse apb2otp block0 data register18."] + #[inline(always)] + pub const fn apb2otp_blk0_backup4_w2(&self) -> &APB2OTP_BLK0_BACKUP4_W2 { + &self.apb2otp_blk0_backup4_w2 + } + #[doc = "0x848 - eFuse apb2otp block0 data register19."] + #[inline(always)] + pub const fn apb2otp_blk0_backup4_w3(&self) -> &APB2OTP_BLK0_BACKUP4_W3 { + &self.apb2otp_blk0_backup4_w3 + } + #[doc = "0x84c - eFuse apb2otp block0 data register20."] + #[inline(always)] + pub const fn apb2otp_blk0_backup4_w4(&self) -> &APB2OTP_BLK0_BACKUP4_W4 { + &self.apb2otp_blk0_backup4_w4 + } + #[doc = "0x850 - eFuse apb2otp block0 data register21."] + #[inline(always)] + pub const fn apb2otp_blk0_backup4_w5(&self) -> &APB2OTP_BLK0_BACKUP4_W5 { + &self.apb2otp_blk0_backup4_w5 + } + #[doc = "0x854 - eFuse apb2otp block1 data register1."] + #[inline(always)] + pub const fn apb2otp_blk1_w1(&self) -> &APB2OTP_BLK1_W1 { + &self.apb2otp_blk1_w1 + } + #[doc = "0x858 - eFuse apb2otp block1 data register2."] + #[inline(always)] + pub const fn apb2otp_blk1_w2(&self) -> &APB2OTP_BLK1_W2 { + &self.apb2otp_blk1_w2 + } + #[doc = "0x85c - eFuse apb2otp block1 data register3."] + #[inline(always)] + pub const fn apb2otp_blk1_w3(&self) -> &APB2OTP_BLK1_W3 { + &self.apb2otp_blk1_w3 + } + #[doc = "0x860 - eFuse apb2otp block1 data register4."] + #[inline(always)] + pub const fn apb2otp_blk1_w4(&self) -> &APB2OTP_BLK1_W4 { + &self.apb2otp_blk1_w4 + } + #[doc = "0x864 - eFuse apb2otp block1 data register5."] + #[inline(always)] + pub const fn apb2otp_blk1_w5(&self) -> &APB2OTP_BLK1_W5 { + &self.apb2otp_blk1_w5 + } + #[doc = "0x868 - eFuse apb2otp block1 data register6."] + #[inline(always)] + pub const fn apb2otp_blk1_w6(&self) -> &APB2OTP_BLK1_W6 { + &self.apb2otp_blk1_w6 + } + #[doc = "0x86c - eFuse apb2otp block1 data register7."] + #[inline(always)] + pub const fn apb2otp_blk1_w7(&self) -> &APB2OTP_BLK1_W7 { + &self.apb2otp_blk1_w7 + } + #[doc = "0x870 - eFuse apb2otp block1 data register8."] + #[inline(always)] + pub const fn apb2otp_blk1_w8(&self) -> &APB2OTP_BLK1_W8 { + &self.apb2otp_blk1_w8 + } + #[doc = "0x874 - eFuse apb2otp block1 data register9."] + #[inline(always)] + pub const fn apb2otp_blk1_w9(&self) -> &APB2OTP_BLK1_W9 { + &self.apb2otp_blk1_w9 + } + #[doc = "0x878 - eFuse apb2otp block2 data register1."] + #[inline(always)] + pub const fn apb2otp_blk2_w1(&self) -> &APB2OTP_BLK2_W1 { + &self.apb2otp_blk2_w1 + } + #[doc = "0x87c - eFuse apb2otp block2 data register2."] + #[inline(always)] + pub const fn apb2otp_blk2_w2(&self) -> &APB2OTP_BLK2_W2 { + &self.apb2otp_blk2_w2 + } + #[doc = "0x880 - eFuse apb2otp block2 data register3."] + #[inline(always)] + pub const fn apb2otp_blk2_w3(&self) -> &APB2OTP_BLK2_W3 { + &self.apb2otp_blk2_w3 + } + #[doc = "0x884 - eFuse apb2otp block2 data register4."] + #[inline(always)] + pub const fn apb2otp_blk2_w4(&self) -> &APB2OTP_BLK2_W4 { + &self.apb2otp_blk2_w4 + } + #[doc = "0x888 - eFuse apb2otp block2 data register5."] + #[inline(always)] + pub const fn apb2otp_blk2_w5(&self) -> &APB2OTP_BLK2_W5 { + &self.apb2otp_blk2_w5 + } + #[doc = "0x88c - eFuse apb2otp block2 data register6."] + #[inline(always)] + pub const fn apb2otp_blk2_w6(&self) -> &APB2OTP_BLK2_W6 { + &self.apb2otp_blk2_w6 + } + #[doc = "0x890 - eFuse apb2otp block2 data register7."] + #[inline(always)] + pub const fn apb2otp_blk2_w7(&self) -> &APB2OTP_BLK2_W7 { + &self.apb2otp_blk2_w7 + } + #[doc = "0x894 - eFuse apb2otp block2 data register8."] + #[inline(always)] + pub const fn apb2otp_blk2_w8(&self) -> &APB2OTP_BLK2_W8 { + &self.apb2otp_blk2_w8 + } + #[doc = "0x898 - eFuse apb2otp block2 data register9."] + #[inline(always)] + pub const fn apb2otp_blk2_w9(&self) -> &APB2OTP_BLK2_W9 { + &self.apb2otp_blk2_w9 + } + #[doc = "0x89c - eFuse apb2otp block2 data register10."] + #[inline(always)] + pub const fn apb2otp_blk2_w10(&self) -> &APB2OTP_BLK2_W10 { + &self.apb2otp_blk2_w10 + } + #[doc = "0x8a0 - eFuse apb2otp block2 data register11."] + #[inline(always)] + pub const fn apb2otp_blk2_w11(&self) -> &APB2OTP_BLK2_W11 { + &self.apb2otp_blk2_w11 + } + #[doc = "0x8a4 - eFuse apb2otp block3 data register1."] + #[inline(always)] + pub const fn apb2otp_blk3_w1(&self) -> &APB2OTP_BLK3_W1 { + &self.apb2otp_blk3_w1 + } + #[doc = "0x8a8 - eFuse apb2otp block3 data register2."] + #[inline(always)] + pub const fn apb2otp_blk3_w2(&self) -> &APB2OTP_BLK3_W2 { + &self.apb2otp_blk3_w2 + } + #[doc = "0x8ac - eFuse apb2otp block3 data register3."] + #[inline(always)] + pub const fn apb2otp_blk3_w3(&self) -> &APB2OTP_BLK3_W3 { + &self.apb2otp_blk3_w3 + } + #[doc = "0x8b0 - eFuse apb2otp block3 data register4."] + #[inline(always)] + pub const fn apb2otp_blk3_w4(&self) -> &APB2OTP_BLK3_W4 { + &self.apb2otp_blk3_w4 + } + #[doc = "0x8b4 - eFuse apb2otp block3 data register5."] + #[inline(always)] + pub const fn apb2otp_blk3_w5(&self) -> &APB2OTP_BLK3_W5 { + &self.apb2otp_blk3_w5 + } + #[doc = "0x8b8 - eFuse apb2otp block3 data register6."] + #[inline(always)] + pub const fn apb2otp_blk3_w6(&self) -> &APB2OTP_BLK3_W6 { + &self.apb2otp_blk3_w6 + } + #[doc = "0x8bc - eFuse apb2otp block3 data register7."] + #[inline(always)] + pub const fn apb2otp_blk3_w7(&self) -> &APB2OTP_BLK3_W7 { + &self.apb2otp_blk3_w7 + } + #[doc = "0x8c0 - eFuse apb2otp block3 data register8."] + #[inline(always)] + pub const fn apb2otp_blk3_w8(&self) -> &APB2OTP_BLK3_W8 { + &self.apb2otp_blk3_w8 + } + #[doc = "0x8c4 - eFuse apb2otp block3 data register9."] + #[inline(always)] + pub const fn apb2otp_blk3_w9(&self) -> &APB2OTP_BLK3_W9 { + &self.apb2otp_blk3_w9 + } + #[doc = "0x8c8 - eFuse apb2otp block3 data register10."] + #[inline(always)] + pub const fn apb2otp_blk3_w10(&self) -> &APB2OTP_BLK3_W10 { + &self.apb2otp_blk3_w10 + } + #[doc = "0x8cc - eFuse apb2otp block3 data register11."] + #[inline(always)] + pub const fn apb2otp_blk3_w11(&self) -> &APB2OTP_BLK3_W11 { + &self.apb2otp_blk3_w11 + } + #[doc = "0x8d0 - eFuse apb2otp block4 data register1."] + #[inline(always)] + pub const fn apb2otp_blk4_w1(&self) -> &APB2OTP_BLK4_W1 { + &self.apb2otp_blk4_w1 + } + #[doc = "0x8d4 - eFuse apb2otp block4 data register2."] + #[inline(always)] + pub const fn apb2otp_blk4_w2(&self) -> &APB2OTP_BLK4_W2 { + &self.apb2otp_blk4_w2 + } + #[doc = "0x8d8 - eFuse apb2otp block4 data register3."] + #[inline(always)] + pub const fn apb2otp_blk4_w3(&self) -> &APB2OTP_BLK4_W3 { + &self.apb2otp_blk4_w3 + } + #[doc = "0x8dc - eFuse apb2otp block4 data register4."] + #[inline(always)] + pub const fn apb2otp_blk4_w4(&self) -> &APB2OTP_BLK4_W4 { + &self.apb2otp_blk4_w4 + } + #[doc = "0x8e0 - eFuse apb2otp block4 data register5."] + #[inline(always)] + pub const fn apb2otp_blk4_w5(&self) -> &APB2OTP_BLK4_W5 { + &self.apb2otp_blk4_w5 + } + #[doc = "0x8e4 - eFuse apb2otp block4 data register6."] + #[inline(always)] + pub const fn apb2otp_blk4_w6(&self) -> &APB2OTP_BLK4_W6 { + &self.apb2otp_blk4_w6 + } + #[doc = "0x8e8 - eFuse apb2otp block4 data register7."] + #[inline(always)] + pub const fn apb2otp_blk4_w7(&self) -> &APB2OTP_BLK4_W7 { + &self.apb2otp_blk4_w7 + } + #[doc = "0x8ec - eFuse apb2otp block4 data register8."] + #[inline(always)] + pub const fn apb2otp_blk4_w8(&self) -> &APB2OTP_BLK4_W8 { + &self.apb2otp_blk4_w8 + } + #[doc = "0x8f0 - eFuse apb2otp block4 data register9."] + #[inline(always)] + pub const fn apb2otp_blk4_w9(&self) -> &APB2OTP_BLK4_W9 { + &self.apb2otp_blk4_w9 + } + #[doc = "0x8f4 - eFuse apb2otp block4 data registe10."] + #[inline(always)] + pub const fn apb2otp_blk4_w10(&self) -> &APB2OTP_BLK4_W10 { + &self.apb2otp_blk4_w10 + } + #[doc = "0x8f8 - eFuse apb2otp block4 data register11."] + #[inline(always)] + pub const fn apb2otp_blk4_w11(&self) -> &APB2OTP_BLK4_W11 { + &self.apb2otp_blk4_w11 + } + #[doc = "0x8fc - eFuse apb2otp block5 data register1."] + #[inline(always)] + pub const fn apb2otp_blk5_w1(&self) -> &APB2OTP_BLK5_W1 { + &self.apb2otp_blk5_w1 + } + #[doc = "0x900 - eFuse apb2otp block5 data register2."] + #[inline(always)] + pub const fn apb2otp_blk5_w2(&self) -> &APB2OTP_BLK5_W2 { + &self.apb2otp_blk5_w2 + } + #[doc = "0x904 - eFuse apb2otp block5 data register3."] + #[inline(always)] + pub const fn apb2otp_blk5_w3(&self) -> &APB2OTP_BLK5_W3 { + &self.apb2otp_blk5_w3 + } + #[doc = "0x908 - eFuse apb2otp block5 data register4."] + #[inline(always)] + pub const fn apb2otp_blk5_w4(&self) -> &APB2OTP_BLK5_W4 { + &self.apb2otp_blk5_w4 + } + #[doc = "0x90c - eFuse apb2otp block5 data register5."] + #[inline(always)] + pub const fn apb2otp_blk5_w5(&self) -> &APB2OTP_BLK5_W5 { + &self.apb2otp_blk5_w5 + } + #[doc = "0x910 - eFuse apb2otp block5 data register6."] + #[inline(always)] + pub const fn apb2otp_blk5_w6(&self) -> &APB2OTP_BLK5_W6 { + &self.apb2otp_blk5_w6 + } + #[doc = "0x914 - eFuse apb2otp block5 data register7."] + #[inline(always)] + pub const fn apb2otp_blk5_w7(&self) -> &APB2OTP_BLK5_W7 { + &self.apb2otp_blk5_w7 + } + #[doc = "0x918 - eFuse apb2otp block5 data register8."] + #[inline(always)] + pub const fn apb2otp_blk5_w8(&self) -> &APB2OTP_BLK5_W8 { + &self.apb2otp_blk5_w8 + } + #[doc = "0x91c - eFuse apb2otp block5 data register9."] + #[inline(always)] + pub const fn apb2otp_blk5_w9(&self) -> &APB2OTP_BLK5_W9 { + &self.apb2otp_blk5_w9 + } + #[doc = "0x920 - eFuse apb2otp block5 data register10."] + #[inline(always)] + pub const fn apb2otp_blk5_w10(&self) -> &APB2OTP_BLK5_W10 { + &self.apb2otp_blk5_w10 + } + #[doc = "0x924 - eFuse apb2otp block5 data register11."] + #[inline(always)] + pub const fn apb2otp_blk5_w11(&self) -> &APB2OTP_BLK5_W11 { + &self.apb2otp_blk5_w11 + } + #[doc = "0x928 - eFuse apb2otp block6 data register1."] + #[inline(always)] + pub const fn apb2otp_blk6_w1(&self) -> &APB2OTP_BLK6_W1 { + &self.apb2otp_blk6_w1 + } + #[doc = "0x92c - eFuse apb2otp block6 data register2."] + #[inline(always)] + pub const fn apb2otp_blk6_w2(&self) -> &APB2OTP_BLK6_W2 { + &self.apb2otp_blk6_w2 + } + #[doc = "0x930 - eFuse apb2otp block6 data register3."] + #[inline(always)] + pub const fn apb2otp_blk6_w3(&self) -> &APB2OTP_BLK6_W3 { + &self.apb2otp_blk6_w3 + } + #[doc = "0x934 - eFuse apb2otp block6 data register4."] + #[inline(always)] + pub const fn apb2otp_blk6_w4(&self) -> &APB2OTP_BLK6_W4 { + &self.apb2otp_blk6_w4 + } + #[doc = "0x938 - eFuse apb2otp block6 data register5."] + #[inline(always)] + pub const fn apb2otp_blk6_w5(&self) -> &APB2OTP_BLK6_W5 { + &self.apb2otp_blk6_w5 + } + #[doc = "0x93c - eFuse apb2otp block6 data register6."] + #[inline(always)] + pub const fn apb2otp_blk6_w6(&self) -> &APB2OTP_BLK6_W6 { + &self.apb2otp_blk6_w6 + } + #[doc = "0x940 - eFuse apb2otp block6 data register7."] + #[inline(always)] + pub const fn apb2otp_blk6_w7(&self) -> &APB2OTP_BLK6_W7 { + &self.apb2otp_blk6_w7 + } + #[doc = "0x944 - eFuse apb2otp block6 data register8."] + #[inline(always)] + pub const fn apb2otp_blk6_w8(&self) -> &APB2OTP_BLK6_W8 { + &self.apb2otp_blk6_w8 + } + #[doc = "0x948 - eFuse apb2otp block6 data register9."] + #[inline(always)] + pub const fn apb2otp_blk6_w9(&self) -> &APB2OTP_BLK6_W9 { + &self.apb2otp_blk6_w9 + } + #[doc = "0x94c - eFuse apb2otp block6 data register10."] + #[inline(always)] + pub const fn apb2otp_blk6_w10(&self) -> &APB2OTP_BLK6_W10 { + &self.apb2otp_blk6_w10 + } + #[doc = "0x950 - eFuse apb2otp block6 data register11."] + #[inline(always)] + pub const fn apb2otp_blk6_w11(&self) -> &APB2OTP_BLK6_W11 { + &self.apb2otp_blk6_w11 + } + #[doc = "0x954 - eFuse apb2otp block7 data register1."] + #[inline(always)] + pub const fn apb2otp_blk7_w1(&self) -> &APB2OTP_BLK7_W1 { + &self.apb2otp_blk7_w1 + } + #[doc = "0x958 - eFuse apb2otp block7 data register2."] + #[inline(always)] + pub const fn apb2otp_blk7_w2(&self) -> &APB2OTP_BLK7_W2 { + &self.apb2otp_blk7_w2 + } + #[doc = "0x95c - eFuse apb2otp block7 data register3."] + #[inline(always)] + pub const fn apb2otp_blk7_w3(&self) -> &APB2OTP_BLK7_W3 { + &self.apb2otp_blk7_w3 + } + #[doc = "0x960 - eFuse apb2otp block7 data register4."] + #[inline(always)] + pub const fn apb2otp_blk7_w4(&self) -> &APB2OTP_BLK7_W4 { + &self.apb2otp_blk7_w4 + } + #[doc = "0x964 - eFuse apb2otp block7 data register5."] + #[inline(always)] + pub const fn apb2otp_blk7_w5(&self) -> &APB2OTP_BLK7_W5 { + &self.apb2otp_blk7_w5 + } + #[doc = "0x968 - eFuse apb2otp block7 data register6."] + #[inline(always)] + pub const fn apb2otp_blk7_w6(&self) -> &APB2OTP_BLK7_W6 { + &self.apb2otp_blk7_w6 + } + #[doc = "0x96c - eFuse apb2otp block7 data register7."] + #[inline(always)] + pub const fn apb2otp_blk7_w7(&self) -> &APB2OTP_BLK7_W7 { + &self.apb2otp_blk7_w7 + } + #[doc = "0x970 - eFuse apb2otp block7 data register8."] + #[inline(always)] + pub const fn apb2otp_blk7_w8(&self) -> &APB2OTP_BLK7_W8 { + &self.apb2otp_blk7_w8 + } + #[doc = "0x974 - eFuse apb2otp block7 data register9."] + #[inline(always)] + pub const fn apb2otp_blk7_w9(&self) -> &APB2OTP_BLK7_W9 { + &self.apb2otp_blk7_w9 + } + #[doc = "0x978 - eFuse apb2otp block7 data register10."] + #[inline(always)] + pub const fn apb2otp_blk7_w10(&self) -> &APB2OTP_BLK7_W10 { + &self.apb2otp_blk7_w10 + } + #[doc = "0x97c - eFuse apb2otp block7 data register11."] + #[inline(always)] + pub const fn apb2otp_blk7_w11(&self) -> &APB2OTP_BLK7_W11 { + &self.apb2otp_blk7_w11 + } + #[doc = "0x980 - eFuse apb2otp block8 data register1."] + #[inline(always)] + pub const fn apb2otp_blk8_w1(&self) -> &APB2OTP_BLK8_W1 { + &self.apb2otp_blk8_w1 + } + #[doc = "0x984 - eFuse apb2otp block8 data register2."] + #[inline(always)] + pub const fn apb2otp_blk8_w2(&self) -> &APB2OTP_BLK8_W2 { + &self.apb2otp_blk8_w2 + } + #[doc = "0x988 - eFuse apb2otp block8 data register3."] + #[inline(always)] + pub const fn apb2otp_blk8_w3(&self) -> &APB2OTP_BLK8_W3 { + &self.apb2otp_blk8_w3 + } + #[doc = "0x98c - eFuse apb2otp block8 data register4."] + #[inline(always)] + pub const fn apb2otp_blk8_w4(&self) -> &APB2OTP_BLK8_W4 { + &self.apb2otp_blk8_w4 + } + #[doc = "0x990 - eFuse apb2otp block8 data register5."] + #[inline(always)] + pub const fn apb2otp_blk8_w5(&self) -> &APB2OTP_BLK8_W5 { + &self.apb2otp_blk8_w5 + } + #[doc = "0x994 - eFuse apb2otp block8 data register6."] + #[inline(always)] + pub const fn apb2otp_blk8_w6(&self) -> &APB2OTP_BLK8_W6 { + &self.apb2otp_blk8_w6 + } + #[doc = "0x998 - eFuse apb2otp block8 data register7."] + #[inline(always)] + pub const fn apb2otp_blk8_w7(&self) -> &APB2OTP_BLK8_W7 { + &self.apb2otp_blk8_w7 + } + #[doc = "0x99c - eFuse apb2otp block8 data register8."] + #[inline(always)] + pub const fn apb2otp_blk8_w8(&self) -> &APB2OTP_BLK8_W8 { + &self.apb2otp_blk8_w8 + } + #[doc = "0x9a0 - eFuse apb2otp block8 data register9."] + #[inline(always)] + pub const fn apb2otp_blk8_w9(&self) -> &APB2OTP_BLK8_W9 { + &self.apb2otp_blk8_w9 + } + #[doc = "0x9a4 - eFuse apb2otp block8 data register10."] + #[inline(always)] + pub const fn apb2otp_blk8_w10(&self) -> &APB2OTP_BLK8_W10 { + &self.apb2otp_blk8_w10 + } + #[doc = "0x9a8 - eFuse apb2otp block8 data register11."] + #[inline(always)] + pub const fn apb2otp_blk8_w11(&self) -> &APB2OTP_BLK8_W11 { + &self.apb2otp_blk8_w11 + } + #[doc = "0x9ac - eFuse apb2otp block9 data register1."] + #[inline(always)] + pub const fn apb2otp_blk9_w1(&self) -> &APB2OTP_BLK9_W1 { + &self.apb2otp_blk9_w1 + } + #[doc = "0x9b0 - eFuse apb2otp block9 data register2."] + #[inline(always)] + pub const fn apb2otp_blk9_w2(&self) -> &APB2OTP_BLK9_W2 { + &self.apb2otp_blk9_w2 + } + #[doc = "0x9b4 - eFuse apb2otp block9 data register3."] + #[inline(always)] + pub const fn apb2otp_blk9_w3(&self) -> &APB2OTP_BLK9_W3 { + &self.apb2otp_blk9_w3 + } + #[doc = "0x9b8 - eFuse apb2otp block9 data register4."] + #[inline(always)] + pub const fn apb2otp_blk9_w4(&self) -> &APB2OTP_BLK9_W4 { + &self.apb2otp_blk9_w4 + } + #[doc = "0x9bc - eFuse apb2otp block9 data register5."] + #[inline(always)] + pub const fn apb2otp_blk9_w5(&self) -> &APB2OTP_BLK9_W5 { + &self.apb2otp_blk9_w5 + } + #[doc = "0x9c0 - eFuse apb2otp block9 data register6."] + #[inline(always)] + pub const fn apb2otp_blk9_w6(&self) -> &APB2OTP_BLK9_W6 { + &self.apb2otp_blk9_w6 + } + #[doc = "0x9c4 - eFuse apb2otp block9 data register7."] + #[inline(always)] + pub const fn apb2otp_blk9_w7(&self) -> &APB2OTP_BLK9_W7 { + &self.apb2otp_blk9_w7 + } + #[doc = "0x9c8 - eFuse apb2otp block9 data register8."] + #[inline(always)] + pub const fn apb2otp_blk9_w8(&self) -> &APB2OTP_BLK9_W8 { + &self.apb2otp_blk9_w8 + } + #[doc = "0x9cc - eFuse apb2otp block9 data register9."] + #[inline(always)] + pub const fn apb2otp_blk9_w9(&self) -> &APB2OTP_BLK9_W9 { + &self.apb2otp_blk9_w9 + } + #[doc = "0x9d0 - eFuse apb2otp block9 data register10."] + #[inline(always)] + pub const fn apb2otp_blk9_w10(&self) -> &APB2OTP_BLK9_W10 { + &self.apb2otp_blk9_w10 + } + #[doc = "0x9d4 - eFuse apb2otp block9 data register11."] + #[inline(always)] + pub const fn apb2otp_blk9_w11(&self) -> &APB2OTP_BLK9_W11 { + &self.apb2otp_blk9_w11 + } + #[doc = "0x9d8 - eFuse apb2otp block10 data register1."] + #[inline(always)] + pub const fn apb2otp_blk10_w1(&self) -> &APB2OTP_BLK10_W1 { + &self.apb2otp_blk10_w1 + } + #[doc = "0x9dc - eFuse apb2otp block10 data register2."] + #[inline(always)] + pub const fn apb2otp_blk10_w2(&self) -> &APB2OTP_BLK10_W2 { + &self.apb2otp_blk10_w2 + } + #[doc = "0x9e0 - eFuse apb2otp block10 data register3."] + #[inline(always)] + pub const fn apb2otp_blk10_w3(&self) -> &APB2OTP_BLK10_W3 { + &self.apb2otp_blk10_w3 + } + #[doc = "0x9e4 - eFuse apb2otp block10 data register4."] + #[inline(always)] + pub const fn apb2otp_blk10_w4(&self) -> &APB2OTP_BLK10_W4 { + &self.apb2otp_blk10_w4 + } + #[doc = "0x9e8 - eFuse apb2otp block10 data register5."] + #[inline(always)] + pub const fn apb2otp_blk10_w5(&self) -> &APB2OTP_BLK10_W5 { + &self.apb2otp_blk10_w5 + } + #[doc = "0x9ec - eFuse apb2otp block10 data register6."] + #[inline(always)] + pub const fn apb2otp_blk10_w6(&self) -> &APB2OTP_BLK10_W6 { + &self.apb2otp_blk10_w6 + } + #[doc = "0x9f0 - eFuse apb2otp block10 data register7."] + #[inline(always)] + pub const fn apb2otp_blk10_w7(&self) -> &APB2OTP_BLK10_W7 { + &self.apb2otp_blk10_w7 + } + #[doc = "0x9f4 - eFuse apb2otp block10 data register8."] + #[inline(always)] + pub const fn apb2otp_blk10_w8(&self) -> &APB2OTP_BLK10_W8 { + &self.apb2otp_blk10_w8 + } + #[doc = "0x9f8 - eFuse apb2otp block10 data register9."] + #[inline(always)] + pub const fn apb2otp_blk10_w9(&self) -> &APB2OTP_BLK10_W9 { + &self.apb2otp_blk10_w9 + } + #[doc = "0x9fc - eFuse apb2otp block10 data register10."] + #[inline(always)] + pub const fn apb2otp_blk10_w10(&self) -> &APB2OTP_BLK10_W10 { + &self.apb2otp_blk10_w10 + } + #[doc = "0xa00 - eFuse apb2otp block10 data register11."] + #[inline(always)] + pub const fn apb2otp_blk10_w11(&self) -> &APB2OTP_BLK10_W11 { + &self.apb2otp_blk10_w11 + } + #[doc = "0xa08 - eFuse apb2otp enable configuration register."] + #[inline(always)] + pub const fn apb2otp_en(&self) -> &APB2OTP_EN { + &self.apb2otp_en + } +} +#[doc = "PGM_DATA0 (rw) register accessor: Register 0 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgm_data0`] module"] +pub type PGM_DATA0 = crate::Reg; +#[doc = "Register 0 that stores data to be programmed."] +pub mod pgm_data0; +#[doc = "PGM_DATA1 (rw) register accessor: Register 1 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgm_data1`] module"] +pub type PGM_DATA1 = crate::Reg; +#[doc = "Register 1 that stores data to be programmed."] +pub mod pgm_data1; +#[doc = "PGM_DATA2 (rw) register accessor: Register 2 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgm_data2`] module"] +pub type PGM_DATA2 = crate::Reg; +#[doc = "Register 2 that stores data to be programmed."] +pub mod pgm_data2; +#[doc = "PGM_DATA3 (rw) register accessor: Register 3 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgm_data3`] module"] +pub type PGM_DATA3 = crate::Reg; +#[doc = "Register 3 that stores data to be programmed."] +pub mod pgm_data3; +#[doc = "PGM_DATA4 (rw) register accessor: Register 4 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgm_data4`] module"] +pub type PGM_DATA4 = crate::Reg; +#[doc = "Register 4 that stores data to be programmed."] +pub mod pgm_data4; +#[doc = "PGM_DATA5 (rw) register accessor: Register 5 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgm_data5`] module"] +pub type PGM_DATA5 = crate::Reg; +#[doc = "Register 5 that stores data to be programmed."] +pub mod pgm_data5; +#[doc = "PGM_DATA6 (rw) register accessor: Register 6 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgm_data6`] module"] +pub type PGM_DATA6 = crate::Reg; +#[doc = "Register 6 that stores data to be programmed."] +pub mod pgm_data6; +#[doc = "PGM_DATA7 (rw) register accessor: Register 7 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgm_data7`] module"] +pub type PGM_DATA7 = crate::Reg; +#[doc = "Register 7 that stores data to be programmed."] +pub mod pgm_data7; +#[doc = "PGM_CHECK_VALUE0 (rw) register accessor: Register 0 that stores the RS code to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_check_value0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_check_value0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgm_check_value0`] module"] +pub type PGM_CHECK_VALUE0 = crate::Reg; +#[doc = "Register 0 that stores the RS code to be programmed."] +pub mod pgm_check_value0; +#[doc = "PGM_CHECK_VALUE1 (rw) register accessor: Register 1 that stores the RS code to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_check_value1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_check_value1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgm_check_value1`] module"] +pub type PGM_CHECK_VALUE1 = crate::Reg; +#[doc = "Register 1 that stores the RS code to be programmed."] +pub mod pgm_check_value1; +#[doc = "PGM_CHECK_VALUE2 (rw) register accessor: Register 2 that stores the RS code to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_check_value2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_check_value2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pgm_check_value2`] module"] +pub type PGM_CHECK_VALUE2 = crate::Reg; +#[doc = "Register 2 that stores the RS code to be programmed."] +pub mod pgm_check_value2; +#[doc = "RD_WR_DIS (r) register accessor: BLOCK0 data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_wr_dis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_wr_dis`] module"] +pub type RD_WR_DIS = crate::Reg; +#[doc = "BLOCK0 data register 0."] +pub mod rd_wr_dis; +#[doc = "RD_REPEAT_DATA0 (r) register accessor: BLOCK0 data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_repeat_data0`] module"] +pub type RD_REPEAT_DATA0 = crate::Reg; +#[doc = "BLOCK0 data register 1."] +pub mod rd_repeat_data0; +#[doc = "RD_REPEAT_DATA1 (r) register accessor: BLOCK0 data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_repeat_data1`] module"] +pub type RD_REPEAT_DATA1 = crate::Reg; +#[doc = "BLOCK0 data register 2."] +pub mod rd_repeat_data1; +#[doc = "RD_REPEAT_DATA2 (r) register accessor: BLOCK0 data register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_repeat_data2`] module"] +pub type RD_REPEAT_DATA2 = crate::Reg; +#[doc = "BLOCK0 data register 3."] +pub mod rd_repeat_data2; +#[doc = "RD_REPEAT_DATA3 (r) register accessor: BLOCK0 data register 4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_repeat_data3`] module"] +pub type RD_REPEAT_DATA3 = crate::Reg; +#[doc = "BLOCK0 data register 4."] +pub mod rd_repeat_data3; +#[doc = "RD_REPEAT_DATA4 (r) register accessor: BLOCK0 data register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_repeat_data4`] module"] +pub type RD_REPEAT_DATA4 = crate::Reg; +#[doc = "BLOCK0 data register 5."] +pub mod rd_repeat_data4; +#[doc = "RD_MAC_SYS_0 (r) register accessor: BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_mac_sys_0`] module"] +pub type RD_MAC_SYS_0 = crate::Reg; +#[doc = "BLOCK1 data register $n."] +pub mod rd_mac_sys_0; +#[doc = "RD_MAC_SYS_1 (r) register accessor: BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_mac_sys_1`] module"] +pub type RD_MAC_SYS_1 = crate::Reg; +#[doc = "BLOCK1 data register $n."] +pub mod rd_mac_sys_1; +#[doc = "RD_MAC_SYS_2 (r) register accessor: BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_mac_sys_2`] module"] +pub type RD_MAC_SYS_2 = crate::Reg; +#[doc = "BLOCK1 data register $n."] +pub mod rd_mac_sys_2; +#[doc = "RD_MAC_SYS_3 (r) register accessor: BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_mac_sys_3`] module"] +pub type RD_MAC_SYS_3 = crate::Reg; +#[doc = "BLOCK1 data register $n."] +pub mod rd_mac_sys_3; +#[doc = "RD_MAC_SYS_4 (r) register accessor: BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_mac_sys_4`] module"] +pub type RD_MAC_SYS_4 = crate::Reg; +#[doc = "BLOCK1 data register $n."] +pub mod rd_mac_sys_4; +#[doc = "RD_MAC_SYS_5 (r) register accessor: BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_mac_sys_5`] module"] +pub type RD_MAC_SYS_5 = crate::Reg; +#[doc = "BLOCK1 data register $n."] +pub mod rd_mac_sys_5; +#[doc = "RD_SYS_PART1_DATA0 (r) register accessor: Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part1_data0`] module"] +pub type RD_SYS_PART1_DATA0 = crate::Reg; +#[doc = "Register $n of BLOCK2 (system)."] +pub mod rd_sys_part1_data0; +#[doc = "RD_SYS_PART1_DATA1 (r) register accessor: Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part1_data1`] module"] +pub type RD_SYS_PART1_DATA1 = crate::Reg; +#[doc = "Register $n of BLOCK2 (system)."] +pub mod rd_sys_part1_data1; +#[doc = "RD_SYS_PART1_DATA2 (r) register accessor: Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part1_data2`] module"] +pub type RD_SYS_PART1_DATA2 = crate::Reg; +#[doc = "Register $n of BLOCK2 (system)."] +pub mod rd_sys_part1_data2; +#[doc = "RD_SYS_PART1_DATA3 (r) register accessor: Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part1_data3`] module"] +pub type RD_SYS_PART1_DATA3 = crate::Reg; +#[doc = "Register $n of BLOCK2 (system)."] +pub mod rd_sys_part1_data3; +#[doc = "RD_SYS_PART1_DATA4 (r) register accessor: Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part1_data4`] module"] +pub type RD_SYS_PART1_DATA4 = crate::Reg; +#[doc = "Register $n of BLOCK2 (system)."] +pub mod rd_sys_part1_data4; +#[doc = "RD_SYS_PART1_DATA5 (r) register accessor: Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part1_data5`] module"] +pub type RD_SYS_PART1_DATA5 = crate::Reg; +#[doc = "Register $n of BLOCK2 (system)."] +pub mod rd_sys_part1_data5; +#[doc = "RD_SYS_PART1_DATA6 (r) register accessor: Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part1_data6`] module"] +pub type RD_SYS_PART1_DATA6 = crate::Reg; +#[doc = "Register $n of BLOCK2 (system)."] +pub mod rd_sys_part1_data6; +#[doc = "RD_SYS_PART1_DATA7 (r) register accessor: Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part1_data7`] module"] +pub type RD_SYS_PART1_DATA7 = crate::Reg; +#[doc = "Register $n of BLOCK2 (system)."] +pub mod rd_sys_part1_data7; +#[doc = "RD_USR_DATA0 (r) register accessor: Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_usr_data0`] module"] +pub type RD_USR_DATA0 = crate::Reg; +#[doc = "Register $n of BLOCK3 (user)."] +pub mod rd_usr_data0; +#[doc = "RD_USR_DATA1 (r) register accessor: Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_usr_data1`] module"] +pub type RD_USR_DATA1 = crate::Reg; +#[doc = "Register $n of BLOCK3 (user)."] +pub mod rd_usr_data1; +#[doc = "RD_USR_DATA2 (r) register accessor: Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_usr_data2`] module"] +pub type RD_USR_DATA2 = crate::Reg; +#[doc = "Register $n of BLOCK3 (user)."] +pub mod rd_usr_data2; +#[doc = "RD_USR_DATA3 (r) register accessor: Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_usr_data3`] module"] +pub type RD_USR_DATA3 = crate::Reg; +#[doc = "Register $n of BLOCK3 (user)."] +pub mod rd_usr_data3; +#[doc = "RD_USR_DATA4 (r) register accessor: Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_usr_data4`] module"] +pub type RD_USR_DATA4 = crate::Reg; +#[doc = "Register $n of BLOCK3 (user)."] +pub mod rd_usr_data4; +#[doc = "RD_USR_DATA5 (r) register accessor: Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_usr_data5`] module"] +pub type RD_USR_DATA5 = crate::Reg; +#[doc = "Register $n of BLOCK3 (user)."] +pub mod rd_usr_data5; +#[doc = "RD_USR_DATA6 (r) register accessor: Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_usr_data6`] module"] +pub type RD_USR_DATA6 = crate::Reg; +#[doc = "Register $n of BLOCK3 (user)."] +pub mod rd_usr_data6; +#[doc = "RD_USR_DATA7 (r) register accessor: Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_usr_data7`] module"] +pub type RD_USR_DATA7 = crate::Reg; +#[doc = "Register $n of BLOCK3 (user)."] +pub mod rd_usr_data7; +#[doc = "RD_KEY0_DATA0 (r) register accessor: Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key0_data0`] module"] +pub type RD_KEY0_DATA0 = crate::Reg; +#[doc = "Register $n of BLOCK4 (KEY0)."] +pub mod rd_key0_data0; +#[doc = "RD_KEY0_DATA1 (r) register accessor: Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key0_data1`] module"] +pub type RD_KEY0_DATA1 = crate::Reg; +#[doc = "Register $n of BLOCK4 (KEY0)."] +pub mod rd_key0_data1; +#[doc = "RD_KEY0_DATA2 (r) register accessor: Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key0_data2`] module"] +pub type RD_KEY0_DATA2 = crate::Reg; +#[doc = "Register $n of BLOCK4 (KEY0)."] +pub mod rd_key0_data2; +#[doc = "RD_KEY0_DATA3 (r) register accessor: Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key0_data3`] module"] +pub type RD_KEY0_DATA3 = crate::Reg; +#[doc = "Register $n of BLOCK4 (KEY0)."] +pub mod rd_key0_data3; +#[doc = "RD_KEY0_DATA4 (r) register accessor: Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key0_data4`] module"] +pub type RD_KEY0_DATA4 = crate::Reg; +#[doc = "Register $n of BLOCK4 (KEY0)."] +pub mod rd_key0_data4; +#[doc = "RD_KEY0_DATA5 (r) register accessor: Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key0_data5`] module"] +pub type RD_KEY0_DATA5 = crate::Reg; +#[doc = "Register $n of BLOCK4 (KEY0)."] +pub mod rd_key0_data5; +#[doc = "RD_KEY0_DATA6 (r) register accessor: Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key0_data6`] module"] +pub type RD_KEY0_DATA6 = crate::Reg; +#[doc = "Register $n of BLOCK4 (KEY0)."] +pub mod rd_key0_data6; +#[doc = "RD_KEY0_DATA7 (r) register accessor: Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key0_data7`] module"] +pub type RD_KEY0_DATA7 = crate::Reg; +#[doc = "Register $n of BLOCK4 (KEY0)."] +pub mod rd_key0_data7; +#[doc = "RD_KEY1_DATA0 (r) register accessor: Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key1_data0`] module"] +pub type RD_KEY1_DATA0 = crate::Reg; +#[doc = "Register $n of BLOCK5 (KEY1)."] +pub mod rd_key1_data0; +#[doc = "RD_KEY1_DATA1 (r) register accessor: Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key1_data1`] module"] +pub type RD_KEY1_DATA1 = crate::Reg; +#[doc = "Register $n of BLOCK5 (KEY1)."] +pub mod rd_key1_data1; +#[doc = "RD_KEY1_DATA2 (r) register accessor: Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key1_data2`] module"] +pub type RD_KEY1_DATA2 = crate::Reg; +#[doc = "Register $n of BLOCK5 (KEY1)."] +pub mod rd_key1_data2; +#[doc = "RD_KEY1_DATA3 (r) register accessor: Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key1_data3`] module"] +pub type RD_KEY1_DATA3 = crate::Reg; +#[doc = "Register $n of BLOCK5 (KEY1)."] +pub mod rd_key1_data3; +#[doc = "RD_KEY1_DATA4 (r) register accessor: Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key1_data4`] module"] +pub type RD_KEY1_DATA4 = crate::Reg; +#[doc = "Register $n of BLOCK5 (KEY1)."] +pub mod rd_key1_data4; +#[doc = "RD_KEY1_DATA5 (r) register accessor: Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key1_data5`] module"] +pub type RD_KEY1_DATA5 = crate::Reg; +#[doc = "Register $n of BLOCK5 (KEY1)."] +pub mod rd_key1_data5; +#[doc = "RD_KEY1_DATA6 (r) register accessor: Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key1_data6`] module"] +pub type RD_KEY1_DATA6 = crate::Reg; +#[doc = "Register $n of BLOCK5 (KEY1)."] +pub mod rd_key1_data6; +#[doc = "RD_KEY1_DATA7 (r) register accessor: Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key1_data7`] module"] +pub type RD_KEY1_DATA7 = crate::Reg; +#[doc = "Register $n of BLOCK5 (KEY1)."] +pub mod rd_key1_data7; +#[doc = "RD_KEY2_DATA0 (r) register accessor: Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key2_data0`] module"] +pub type RD_KEY2_DATA0 = crate::Reg; +#[doc = "Register $n of BLOCK6 (KEY2)."] +pub mod rd_key2_data0; +#[doc = "RD_KEY2_DATA1 (r) register accessor: Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key2_data1`] module"] +pub type RD_KEY2_DATA1 = crate::Reg; +#[doc = "Register $n of BLOCK6 (KEY2)."] +pub mod rd_key2_data1; +#[doc = "RD_KEY2_DATA2 (r) register accessor: Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key2_data2`] module"] +pub type RD_KEY2_DATA2 = crate::Reg; +#[doc = "Register $n of BLOCK6 (KEY2)."] +pub mod rd_key2_data2; +#[doc = "RD_KEY2_DATA3 (r) register accessor: Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key2_data3`] module"] +pub type RD_KEY2_DATA3 = crate::Reg; +#[doc = "Register $n of BLOCK6 (KEY2)."] +pub mod rd_key2_data3; +#[doc = "RD_KEY2_DATA4 (r) register accessor: Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key2_data4`] module"] +pub type RD_KEY2_DATA4 = crate::Reg; +#[doc = "Register $n of BLOCK6 (KEY2)."] +pub mod rd_key2_data4; +#[doc = "RD_KEY2_DATA5 (r) register accessor: Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key2_data5`] module"] +pub type RD_KEY2_DATA5 = crate::Reg; +#[doc = "Register $n of BLOCK6 (KEY2)."] +pub mod rd_key2_data5; +#[doc = "RD_KEY2_DATA6 (r) register accessor: Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key2_data6`] module"] +pub type RD_KEY2_DATA6 = crate::Reg; +#[doc = "Register $n of BLOCK6 (KEY2)."] +pub mod rd_key2_data6; +#[doc = "RD_KEY2_DATA7 (r) register accessor: Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key2_data7`] module"] +pub type RD_KEY2_DATA7 = crate::Reg; +#[doc = "Register $n of BLOCK6 (KEY2)."] +pub mod rd_key2_data7; +#[doc = "RD_KEY3_DATA0 (r) register accessor: Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key3_data0`] module"] +pub type RD_KEY3_DATA0 = crate::Reg; +#[doc = "Register $n of BLOCK7 (KEY3)."] +pub mod rd_key3_data0; +#[doc = "RD_KEY3_DATA1 (r) register accessor: Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key3_data1`] module"] +pub type RD_KEY3_DATA1 = crate::Reg; +#[doc = "Register $n of BLOCK7 (KEY3)."] +pub mod rd_key3_data1; +#[doc = "RD_KEY3_DATA2 (r) register accessor: Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key3_data2`] module"] +pub type RD_KEY3_DATA2 = crate::Reg; +#[doc = "Register $n of BLOCK7 (KEY3)."] +pub mod rd_key3_data2; +#[doc = "RD_KEY3_DATA3 (r) register accessor: Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key3_data3`] module"] +pub type RD_KEY3_DATA3 = crate::Reg; +#[doc = "Register $n of BLOCK7 (KEY3)."] +pub mod rd_key3_data3; +#[doc = "RD_KEY3_DATA4 (r) register accessor: Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key3_data4`] module"] +pub type RD_KEY3_DATA4 = crate::Reg; +#[doc = "Register $n of BLOCK7 (KEY3)."] +pub mod rd_key3_data4; +#[doc = "RD_KEY3_DATA5 (r) register accessor: Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key3_data5`] module"] +pub type RD_KEY3_DATA5 = crate::Reg; +#[doc = "Register $n of BLOCK7 (KEY3)."] +pub mod rd_key3_data5; +#[doc = "RD_KEY3_DATA6 (r) register accessor: Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key3_data6`] module"] +pub type RD_KEY3_DATA6 = crate::Reg; +#[doc = "Register $n of BLOCK7 (KEY3)."] +pub mod rd_key3_data6; +#[doc = "RD_KEY3_DATA7 (r) register accessor: Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key3_data7`] module"] +pub type RD_KEY3_DATA7 = crate::Reg; +#[doc = "Register $n of BLOCK7 (KEY3)."] +pub mod rd_key3_data7; +#[doc = "RD_KEY4_DATA0 (r) register accessor: Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key4_data0`] module"] +pub type RD_KEY4_DATA0 = crate::Reg; +#[doc = "Register $n of BLOCK8 (KEY4)."] +pub mod rd_key4_data0; +#[doc = "RD_KEY4_DATA1 (r) register accessor: Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key4_data1`] module"] +pub type RD_KEY4_DATA1 = crate::Reg; +#[doc = "Register $n of BLOCK8 (KEY4)."] +pub mod rd_key4_data1; +#[doc = "RD_KEY4_DATA2 (r) register accessor: Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key4_data2`] module"] +pub type RD_KEY4_DATA2 = crate::Reg; +#[doc = "Register $n of BLOCK8 (KEY4)."] +pub mod rd_key4_data2; +#[doc = "RD_KEY4_DATA3 (r) register accessor: Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key4_data3`] module"] +pub type RD_KEY4_DATA3 = crate::Reg; +#[doc = "Register $n of BLOCK8 (KEY4)."] +pub mod rd_key4_data3; +#[doc = "RD_KEY4_DATA4 (r) register accessor: Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key4_data4`] module"] +pub type RD_KEY4_DATA4 = crate::Reg; +#[doc = "Register $n of BLOCK8 (KEY4)."] +pub mod rd_key4_data4; +#[doc = "RD_KEY4_DATA5 (r) register accessor: Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key4_data5`] module"] +pub type RD_KEY4_DATA5 = crate::Reg; +#[doc = "Register $n of BLOCK8 (KEY4)."] +pub mod rd_key4_data5; +#[doc = "RD_KEY4_DATA6 (r) register accessor: Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key4_data6`] module"] +pub type RD_KEY4_DATA6 = crate::Reg; +#[doc = "Register $n of BLOCK8 (KEY4)."] +pub mod rd_key4_data6; +#[doc = "RD_KEY4_DATA7 (r) register accessor: Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key4_data7`] module"] +pub type RD_KEY4_DATA7 = crate::Reg; +#[doc = "Register $n of BLOCK8 (KEY4)."] +pub mod rd_key4_data7; +#[doc = "RD_KEY5_DATA0 (r) register accessor: Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key5_data0`] module"] +pub type RD_KEY5_DATA0 = crate::Reg; +#[doc = "Register $n of BLOCK9 (KEY5)."] +pub mod rd_key5_data0; +#[doc = "RD_KEY5_DATA1 (r) register accessor: Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key5_data1`] module"] +pub type RD_KEY5_DATA1 = crate::Reg; +#[doc = "Register $n of BLOCK9 (KEY5)."] +pub mod rd_key5_data1; +#[doc = "RD_KEY5_DATA2 (r) register accessor: Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key5_data2`] module"] +pub type RD_KEY5_DATA2 = crate::Reg; +#[doc = "Register $n of BLOCK9 (KEY5)."] +pub mod rd_key5_data2; +#[doc = "RD_KEY5_DATA3 (r) register accessor: Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key5_data3`] module"] +pub type RD_KEY5_DATA3 = crate::Reg; +#[doc = "Register $n of BLOCK9 (KEY5)."] +pub mod rd_key5_data3; +#[doc = "RD_KEY5_DATA4 (r) register accessor: Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key5_data4`] module"] +pub type RD_KEY5_DATA4 = crate::Reg; +#[doc = "Register $n of BLOCK9 (KEY5)."] +pub mod rd_key5_data4; +#[doc = "RD_KEY5_DATA5 (r) register accessor: Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key5_data5`] module"] +pub type RD_KEY5_DATA5 = crate::Reg; +#[doc = "Register $n of BLOCK9 (KEY5)."] +pub mod rd_key5_data5; +#[doc = "RD_KEY5_DATA6 (r) register accessor: Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key5_data6`] module"] +pub type RD_KEY5_DATA6 = crate::Reg; +#[doc = "Register $n of BLOCK9 (KEY5)."] +pub mod rd_key5_data6; +#[doc = "RD_KEY5_DATA7 (r) register accessor: Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_key5_data7`] module"] +pub type RD_KEY5_DATA7 = crate::Reg; +#[doc = "Register $n of BLOCK9 (KEY5)."] +pub mod rd_key5_data7; +#[doc = "RD_SYS_PART2_DATA0 (r) register accessor: Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part2_data0`] module"] +pub type RD_SYS_PART2_DATA0 = crate::Reg; +#[doc = "Register $n of BLOCK10 (system)."] +pub mod rd_sys_part2_data0; +#[doc = "RD_SYS_PART2_DATA1 (r) register accessor: Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part2_data1`] module"] +pub type RD_SYS_PART2_DATA1 = crate::Reg; +#[doc = "Register $n of BLOCK9 (KEY5)."] +pub mod rd_sys_part2_data1; +#[doc = "RD_SYS_PART2_DATA2 (r) register accessor: Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part2_data2`] module"] +pub type RD_SYS_PART2_DATA2 = crate::Reg; +#[doc = "Register $n of BLOCK10 (system)."] +pub mod rd_sys_part2_data2; +#[doc = "RD_SYS_PART2_DATA3 (r) register accessor: Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part2_data3`] module"] +pub type RD_SYS_PART2_DATA3 = crate::Reg; +#[doc = "Register $n of BLOCK10 (system)."] +pub mod rd_sys_part2_data3; +#[doc = "RD_SYS_PART2_DATA4 (r) register accessor: Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part2_data4`] module"] +pub type RD_SYS_PART2_DATA4 = crate::Reg; +#[doc = "Register $n of BLOCK10 (system)."] +pub mod rd_sys_part2_data4; +#[doc = "RD_SYS_PART2_DATA5 (r) register accessor: Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part2_data5`] module"] +pub type RD_SYS_PART2_DATA5 = crate::Reg; +#[doc = "Register $n of BLOCK10 (system)."] +pub mod rd_sys_part2_data5; +#[doc = "RD_SYS_PART2_DATA6 (r) register accessor: Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part2_data6`] module"] +pub type RD_SYS_PART2_DATA6 = crate::Reg; +#[doc = "Register $n of BLOCK10 (system)."] +pub mod rd_sys_part2_data6; +#[doc = "RD_SYS_PART2_DATA7 (r) register accessor: Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_sys_part2_data7`] module"] +pub type RD_SYS_PART2_DATA7 = crate::Reg; +#[doc = "Register $n of BLOCK10 (system)."] +pub mod rd_sys_part2_data7; +#[doc = "RD_REPEAT_ERR0 (r) register accessor: Programming error record register 0 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_repeat_err0`] module"] +pub type RD_REPEAT_ERR0 = crate::Reg; +#[doc = "Programming error record register 0 of BLOCK0."] +pub mod rd_repeat_err0; +#[doc = "RD_REPEAT_ERR1 (r) register accessor: Programming error record register 1 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_repeat_err1`] module"] +pub type RD_REPEAT_ERR1 = crate::Reg; +#[doc = "Programming error record register 1 of BLOCK0."] +pub mod rd_repeat_err1; +#[doc = "RD_REPEAT_ERR2 (r) register accessor: Programming error record register 2 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_repeat_err2`] module"] +pub type RD_REPEAT_ERR2 = crate::Reg; +#[doc = "Programming error record register 2 of BLOCK0."] +pub mod rd_repeat_err2; +#[doc = "RD_REPEAT_ERR3 (r) register accessor: Programming error record register 3 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_repeat_err3`] module"] +pub type RD_REPEAT_ERR3 = crate::Reg; +#[doc = "Programming error record register 3 of BLOCK0."] +pub mod rd_repeat_err3; +#[doc = "RD_REPEAT_ERR4 (r) register accessor: Programming error record register 4 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_repeat_err4`] module"] +pub type RD_REPEAT_ERR4 = crate::Reg; +#[doc = "Programming error record register 4 of BLOCK0."] +pub mod rd_repeat_err4; +#[doc = "RD_RS_ERR0 (r) register accessor: Programming error record register 0 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_rs_err0`] module"] +pub type RD_RS_ERR0 = crate::Reg; +#[doc = "Programming error record register 0 of BLOCK1-10."] +pub mod rd_rs_err0; +#[doc = "RD_RS_ERR1 (r) register accessor: Programming error record register 1 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_rs_err1`] module"] +pub type RD_RS_ERR1 = crate::Reg; +#[doc = "Programming error record register 1 of BLOCK1-10."] +pub mod rd_rs_err1; +#[doc = "CLK (rw) register accessor: eFuse clcok configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk`] module"] +pub type CLK = crate::Reg; +#[doc = "eFuse clcok configuration register."] +pub mod clk; +#[doc = "CONF (rw) register accessor: eFuse operation mode configuraiton register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"] +pub type CONF = crate::Reg; +#[doc = "eFuse operation mode configuraiton register"] +pub mod conf; +#[doc = "STATUS (r) register accessor: eFuse status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +pub type STATUS = crate::Reg; +#[doc = "eFuse status register."] +pub mod status; +#[doc = "CMD (rw) register accessor: eFuse command register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"] +pub type CMD = crate::Reg; +#[doc = "eFuse command register."] +pub mod cmd; +#[doc = "INT_RAW (r) register accessor: eFuse raw interrupt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "eFuse raw interrupt register."] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: eFuse interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "eFuse interrupt status register."] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: eFuse interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "eFuse interrupt enable register."] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: eFuse interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "eFuse interrupt clear register."] +pub mod int_clr; +#[doc = "DAC_CONF (rw) register accessor: Controls the eFuse programming voltage.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dac_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dac_conf`] module"] +pub type DAC_CONF = crate::Reg; +#[doc = "Controls the eFuse programming voltage."] +pub mod dac_conf; +#[doc = "RD_TIM_CONF (rw) register accessor: Configures read timing parameters.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_tim_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_tim_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_tim_conf`] module"] +pub type RD_TIM_CONF = crate::Reg; +#[doc = "Configures read timing parameters."] +pub mod rd_tim_conf; +#[doc = "WR_TIM_CONF1 (rw) register accessor: Configurarion register 1 of eFuse programming timing parameters.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_tim_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_tim_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wr_tim_conf1`] module"] +pub type WR_TIM_CONF1 = crate::Reg; +#[doc = "Configurarion register 1 of eFuse programming timing parameters."] +pub mod wr_tim_conf1; +#[doc = "WR_TIM_CONF2 (rw) register accessor: Configurarion register 2 of eFuse programming timing parameters.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_tim_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_tim_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wr_tim_conf2`] module"] +pub type WR_TIM_CONF2 = crate::Reg; +#[doc = "Configurarion register 2 of eFuse programming timing parameters."] +pub mod wr_tim_conf2; +#[doc = "WR_TIM_CONF0_RS_BYPASS (rw) register accessor: Configurarion register0 of eFuse programming time parameters and rs bypass operation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_tim_conf0_rs_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_tim_conf0_rs_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wr_tim_conf0_rs_bypass`] module"] +pub type WR_TIM_CONF0_RS_BYPASS = crate::Reg; +#[doc = "Configurarion register0 of eFuse programming time parameters and rs bypass operation."] +pub mod wr_tim_conf0_rs_bypass; +#[doc = "DATE (rw) register accessor: eFuse version register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "eFuse version register."] +pub mod date; +#[doc = "APB2OTP_WR_DIS (r) register accessor: eFuse apb2otp block0 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_wr_dis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_wr_dis`] module"] +pub type APB2OTP_WR_DIS = crate::Reg; +#[doc = "eFuse apb2otp block0 data register1."] +pub mod apb2otp_wr_dis; +#[doc = "APB2OTP_BLK0_BACKUP1_W1 (r) register accessor: eFuse apb2otp block0 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup1_w1`] module"] +pub type APB2OTP_BLK0_BACKUP1_W1 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register2."] +pub mod apb2otp_blk0_backup1_w1; +#[doc = "APB2OTP_BLK0_BACKUP1_W2 (r) register accessor: eFuse apb2otp block0 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup1_w2`] module"] +pub type APB2OTP_BLK0_BACKUP1_W2 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register3."] +pub mod apb2otp_blk0_backup1_w2; +#[doc = "APB2OTP_BLK0_BACKUP1_W3 (r) register accessor: eFuse apb2otp block0 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup1_w3`] module"] +pub type APB2OTP_BLK0_BACKUP1_W3 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register4."] +pub mod apb2otp_blk0_backup1_w3; +#[doc = "APB2OTP_BLK0_BACKUP1_W4 (r) register accessor: eFuse apb2otp block0 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup1_w4`] module"] +pub type APB2OTP_BLK0_BACKUP1_W4 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register5."] +pub mod apb2otp_blk0_backup1_w4; +#[doc = "APB2OTP_BLK0_BACKUP1_W5 (r) register accessor: eFuse apb2otp block0 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup1_w5`] module"] +pub type APB2OTP_BLK0_BACKUP1_W5 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register6."] +pub mod apb2otp_blk0_backup1_w5; +#[doc = "APB2OTP_BLK0_BACKUP2_W1 (r) register accessor: eFuse apb2otp block0 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup2_w1`] module"] +pub type APB2OTP_BLK0_BACKUP2_W1 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register7."] +pub mod apb2otp_blk0_backup2_w1; +#[doc = "APB2OTP_BLK0_BACKUP2_W2 (r) register accessor: eFuse apb2otp block0 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup2_w2`] module"] +pub type APB2OTP_BLK0_BACKUP2_W2 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register8."] +pub mod apb2otp_blk0_backup2_w2; +#[doc = "APB2OTP_BLK0_BACKUP2_W3 (r) register accessor: eFuse apb2otp block0 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup2_w3`] module"] +pub type APB2OTP_BLK0_BACKUP2_W3 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register9."] +pub mod apb2otp_blk0_backup2_w3; +#[doc = "APB2OTP_BLK0_BACKUP2_W4 (r) register accessor: eFuse apb2otp block0 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup2_w4`] module"] +pub type APB2OTP_BLK0_BACKUP2_W4 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register10."] +pub mod apb2otp_blk0_backup2_w4; +#[doc = "APB2OTP_BLK0_BACKUP2_W5 (r) register accessor: eFuse apb2otp block0 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup2_w5`] module"] +pub type APB2OTP_BLK0_BACKUP2_W5 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register11."] +pub mod apb2otp_blk0_backup2_w5; +#[doc = "APB2OTP_BLK0_BACKUP3_W1 (r) register accessor: eFuse apb2otp block0 data register12.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup3_w1`] module"] +pub type APB2OTP_BLK0_BACKUP3_W1 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register12."] +pub mod apb2otp_blk0_backup3_w1; +#[doc = "APB2OTP_BLK0_BACKUP3_W2 (r) register accessor: eFuse apb2otp block0 data register13.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup3_w2`] module"] +pub type APB2OTP_BLK0_BACKUP3_W2 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register13."] +pub mod apb2otp_blk0_backup3_w2; +#[doc = "APB2OTP_BLK0_BACKUP3_W3 (r) register accessor: eFuse apb2otp block0 data register14.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup3_w3`] module"] +pub type APB2OTP_BLK0_BACKUP3_W3 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register14."] +pub mod apb2otp_blk0_backup3_w3; +#[doc = "APB2OTP_BLK0_BACKUP3_W4 (r) register accessor: eFuse apb2otp block0 data register15.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup3_w4`] module"] +pub type APB2OTP_BLK0_BACKUP3_W4 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register15."] +pub mod apb2otp_blk0_backup3_w4; +#[doc = "APB2OTP_BLK0_BACKUP3_W5 (r) register accessor: eFuse apb2otp block0 data register16.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup3_w5`] module"] +pub type APB2OTP_BLK0_BACKUP3_W5 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register16."] +pub mod apb2otp_blk0_backup3_w5; +#[doc = "APB2OTP_BLK0_BACKUP4_W1 (r) register accessor: eFuse apb2otp block0 data register17.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup4_w1`] module"] +pub type APB2OTP_BLK0_BACKUP4_W1 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register17."] +pub mod apb2otp_blk0_backup4_w1; +#[doc = "APB2OTP_BLK0_BACKUP4_W2 (r) register accessor: eFuse apb2otp block0 data register18.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup4_w2`] module"] +pub type APB2OTP_BLK0_BACKUP4_W2 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register18."] +pub mod apb2otp_blk0_backup4_w2; +#[doc = "APB2OTP_BLK0_BACKUP4_W3 (r) register accessor: eFuse apb2otp block0 data register19.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup4_w3`] module"] +pub type APB2OTP_BLK0_BACKUP4_W3 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register19."] +pub mod apb2otp_blk0_backup4_w3; +#[doc = "APB2OTP_BLK0_BACKUP4_W4 (r) register accessor: eFuse apb2otp block0 data register20.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup4_w4`] module"] +pub type APB2OTP_BLK0_BACKUP4_W4 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register20."] +pub mod apb2otp_blk0_backup4_w4; +#[doc = "APB2OTP_BLK0_BACKUP4_W5 (r) register accessor: eFuse apb2otp block0 data register21.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk0_backup4_w5`] module"] +pub type APB2OTP_BLK0_BACKUP4_W5 = + crate::Reg; +#[doc = "eFuse apb2otp block0 data register21."] +pub mod apb2otp_blk0_backup4_w5; +#[doc = "APB2OTP_BLK1_W1 (r) register accessor: eFuse apb2otp block1 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk1_w1`] module"] +pub type APB2OTP_BLK1_W1 = crate::Reg; +#[doc = "eFuse apb2otp block1 data register1."] +pub mod apb2otp_blk1_w1; +#[doc = "APB2OTP_BLK1_W2 (r) register accessor: eFuse apb2otp block1 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk1_w2`] module"] +pub type APB2OTP_BLK1_W2 = crate::Reg; +#[doc = "eFuse apb2otp block1 data register2."] +pub mod apb2otp_blk1_w2; +#[doc = "APB2OTP_BLK1_W3 (r) register accessor: eFuse apb2otp block1 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk1_w3`] module"] +pub type APB2OTP_BLK1_W3 = crate::Reg; +#[doc = "eFuse apb2otp block1 data register3."] +pub mod apb2otp_blk1_w3; +#[doc = "APB2OTP_BLK1_W4 (r) register accessor: eFuse apb2otp block1 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk1_w4`] module"] +pub type APB2OTP_BLK1_W4 = crate::Reg; +#[doc = "eFuse apb2otp block1 data register4."] +pub mod apb2otp_blk1_w4; +#[doc = "APB2OTP_BLK1_W5 (r) register accessor: eFuse apb2otp block1 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk1_w5`] module"] +pub type APB2OTP_BLK1_W5 = crate::Reg; +#[doc = "eFuse apb2otp block1 data register5."] +pub mod apb2otp_blk1_w5; +#[doc = "APB2OTP_BLK1_W6 (r) register accessor: eFuse apb2otp block1 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk1_w6`] module"] +pub type APB2OTP_BLK1_W6 = crate::Reg; +#[doc = "eFuse apb2otp block1 data register6."] +pub mod apb2otp_blk1_w6; +#[doc = "APB2OTP_BLK1_W7 (r) register accessor: eFuse apb2otp block1 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk1_w7`] module"] +pub type APB2OTP_BLK1_W7 = crate::Reg; +#[doc = "eFuse apb2otp block1 data register7."] +pub mod apb2otp_blk1_w7; +#[doc = "APB2OTP_BLK1_W8 (r) register accessor: eFuse apb2otp block1 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk1_w8`] module"] +pub type APB2OTP_BLK1_W8 = crate::Reg; +#[doc = "eFuse apb2otp block1 data register8."] +pub mod apb2otp_blk1_w8; +#[doc = "APB2OTP_BLK1_W9 (r) register accessor: eFuse apb2otp block1 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk1_w9`] module"] +pub type APB2OTP_BLK1_W9 = crate::Reg; +#[doc = "eFuse apb2otp block1 data register9."] +pub mod apb2otp_blk1_w9; +#[doc = "APB2OTP_BLK2_W1 (r) register accessor: eFuse apb2otp block2 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk2_w1`] module"] +pub type APB2OTP_BLK2_W1 = crate::Reg; +#[doc = "eFuse apb2otp block2 data register1."] +pub mod apb2otp_blk2_w1; +#[doc = "APB2OTP_BLK2_W2 (r) register accessor: eFuse apb2otp block2 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk2_w2`] module"] +pub type APB2OTP_BLK2_W2 = crate::Reg; +#[doc = "eFuse apb2otp block2 data register2."] +pub mod apb2otp_blk2_w2; +#[doc = "APB2OTP_BLK2_W3 (r) register accessor: eFuse apb2otp block2 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk2_w3`] module"] +pub type APB2OTP_BLK2_W3 = crate::Reg; +#[doc = "eFuse apb2otp block2 data register3."] +pub mod apb2otp_blk2_w3; +#[doc = "APB2OTP_BLK2_W4 (r) register accessor: eFuse apb2otp block2 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk2_w4`] module"] +pub type APB2OTP_BLK2_W4 = crate::Reg; +#[doc = "eFuse apb2otp block2 data register4."] +pub mod apb2otp_blk2_w4; +#[doc = "APB2OTP_BLK2_W5 (r) register accessor: eFuse apb2otp block2 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk2_w5`] module"] +pub type APB2OTP_BLK2_W5 = crate::Reg; +#[doc = "eFuse apb2otp block2 data register5."] +pub mod apb2otp_blk2_w5; +#[doc = "APB2OTP_BLK2_W6 (r) register accessor: eFuse apb2otp block2 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk2_w6`] module"] +pub type APB2OTP_BLK2_W6 = crate::Reg; +#[doc = "eFuse apb2otp block2 data register6."] +pub mod apb2otp_blk2_w6; +#[doc = "APB2OTP_BLK2_W7 (r) register accessor: eFuse apb2otp block2 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk2_w7`] module"] +pub type APB2OTP_BLK2_W7 = crate::Reg; +#[doc = "eFuse apb2otp block2 data register7."] +pub mod apb2otp_blk2_w7; +#[doc = "APB2OTP_BLK2_W8 (r) register accessor: eFuse apb2otp block2 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk2_w8`] module"] +pub type APB2OTP_BLK2_W8 = crate::Reg; +#[doc = "eFuse apb2otp block2 data register8."] +pub mod apb2otp_blk2_w8; +#[doc = "APB2OTP_BLK2_W9 (r) register accessor: eFuse apb2otp block2 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk2_w9`] module"] +pub type APB2OTP_BLK2_W9 = crate::Reg; +#[doc = "eFuse apb2otp block2 data register9."] +pub mod apb2otp_blk2_w9; +#[doc = "APB2OTP_BLK2_W10 (r) register accessor: eFuse apb2otp block2 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk2_w10`] module"] +pub type APB2OTP_BLK2_W10 = crate::Reg; +#[doc = "eFuse apb2otp block2 data register10."] +pub mod apb2otp_blk2_w10; +#[doc = "APB2OTP_BLK2_W11 (r) register accessor: eFuse apb2otp block2 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk2_w11`] module"] +pub type APB2OTP_BLK2_W11 = crate::Reg; +#[doc = "eFuse apb2otp block2 data register11."] +pub mod apb2otp_blk2_w11; +#[doc = "APB2OTP_BLK3_W1 (r) register accessor: eFuse apb2otp block3 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk3_w1`] module"] +pub type APB2OTP_BLK3_W1 = crate::Reg; +#[doc = "eFuse apb2otp block3 data register1."] +pub mod apb2otp_blk3_w1; +#[doc = "APB2OTP_BLK3_W2 (r) register accessor: eFuse apb2otp block3 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk3_w2`] module"] +pub type APB2OTP_BLK3_W2 = crate::Reg; +#[doc = "eFuse apb2otp block3 data register2."] +pub mod apb2otp_blk3_w2; +#[doc = "APB2OTP_BLK3_W3 (r) register accessor: eFuse apb2otp block3 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk3_w3`] module"] +pub type APB2OTP_BLK3_W3 = crate::Reg; +#[doc = "eFuse apb2otp block3 data register3."] +pub mod apb2otp_blk3_w3; +#[doc = "APB2OTP_BLK3_W4 (r) register accessor: eFuse apb2otp block3 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk3_w4`] module"] +pub type APB2OTP_BLK3_W4 = crate::Reg; +#[doc = "eFuse apb2otp block3 data register4."] +pub mod apb2otp_blk3_w4; +#[doc = "APB2OTP_BLK3_W5 (r) register accessor: eFuse apb2otp block3 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk3_w5`] module"] +pub type APB2OTP_BLK3_W5 = crate::Reg; +#[doc = "eFuse apb2otp block3 data register5."] +pub mod apb2otp_blk3_w5; +#[doc = "APB2OTP_BLK3_W6 (r) register accessor: eFuse apb2otp block3 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk3_w6`] module"] +pub type APB2OTP_BLK3_W6 = crate::Reg; +#[doc = "eFuse apb2otp block3 data register6."] +pub mod apb2otp_blk3_w6; +#[doc = "APB2OTP_BLK3_W7 (r) register accessor: eFuse apb2otp block3 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk3_w7`] module"] +pub type APB2OTP_BLK3_W7 = crate::Reg; +#[doc = "eFuse apb2otp block3 data register7."] +pub mod apb2otp_blk3_w7; +#[doc = "APB2OTP_BLK3_W8 (r) register accessor: eFuse apb2otp block3 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk3_w8`] module"] +pub type APB2OTP_BLK3_W8 = crate::Reg; +#[doc = "eFuse apb2otp block3 data register8."] +pub mod apb2otp_blk3_w8; +#[doc = "APB2OTP_BLK3_W9 (r) register accessor: eFuse apb2otp block3 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk3_w9`] module"] +pub type APB2OTP_BLK3_W9 = crate::Reg; +#[doc = "eFuse apb2otp block3 data register9."] +pub mod apb2otp_blk3_w9; +#[doc = "APB2OTP_BLK3_W10 (r) register accessor: eFuse apb2otp block3 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk3_w10`] module"] +pub type APB2OTP_BLK3_W10 = crate::Reg; +#[doc = "eFuse apb2otp block3 data register10."] +pub mod apb2otp_blk3_w10; +#[doc = "APB2OTP_BLK3_W11 (r) register accessor: eFuse apb2otp block3 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk3_w11`] module"] +pub type APB2OTP_BLK3_W11 = crate::Reg; +#[doc = "eFuse apb2otp block3 data register11."] +pub mod apb2otp_blk3_w11; +#[doc = "APB2OTP_BLK4_W1 (r) register accessor: eFuse apb2otp block4 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk4_w1`] module"] +pub type APB2OTP_BLK4_W1 = crate::Reg; +#[doc = "eFuse apb2otp block4 data register1."] +pub mod apb2otp_blk4_w1; +#[doc = "APB2OTP_BLK4_W2 (r) register accessor: eFuse apb2otp block4 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk4_w2`] module"] +pub type APB2OTP_BLK4_W2 = crate::Reg; +#[doc = "eFuse apb2otp block4 data register2."] +pub mod apb2otp_blk4_w2; +#[doc = "APB2OTP_BLK4_W3 (r) register accessor: eFuse apb2otp block4 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk4_w3`] module"] +pub type APB2OTP_BLK4_W3 = crate::Reg; +#[doc = "eFuse apb2otp block4 data register3."] +pub mod apb2otp_blk4_w3; +#[doc = "APB2OTP_BLK4_W4 (r) register accessor: eFuse apb2otp block4 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk4_w4`] module"] +pub type APB2OTP_BLK4_W4 = crate::Reg; +#[doc = "eFuse apb2otp block4 data register4."] +pub mod apb2otp_blk4_w4; +#[doc = "APB2OTP_BLK4_W5 (r) register accessor: eFuse apb2otp block4 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk4_w5`] module"] +pub type APB2OTP_BLK4_W5 = crate::Reg; +#[doc = "eFuse apb2otp block4 data register5."] +pub mod apb2otp_blk4_w5; +#[doc = "APB2OTP_BLK4_W6 (r) register accessor: eFuse apb2otp block4 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk4_w6`] module"] +pub type APB2OTP_BLK4_W6 = crate::Reg; +#[doc = "eFuse apb2otp block4 data register6."] +pub mod apb2otp_blk4_w6; +#[doc = "APB2OTP_BLK4_W7 (r) register accessor: eFuse apb2otp block4 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk4_w7`] module"] +pub type APB2OTP_BLK4_W7 = crate::Reg; +#[doc = "eFuse apb2otp block4 data register7."] +pub mod apb2otp_blk4_w7; +#[doc = "APB2OTP_BLK4_W8 (r) register accessor: eFuse apb2otp block4 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk4_w8`] module"] +pub type APB2OTP_BLK4_W8 = crate::Reg; +#[doc = "eFuse apb2otp block4 data register8."] +pub mod apb2otp_blk4_w8; +#[doc = "APB2OTP_BLK4_W9 (r) register accessor: eFuse apb2otp block4 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk4_w9`] module"] +pub type APB2OTP_BLK4_W9 = crate::Reg; +#[doc = "eFuse apb2otp block4 data register9."] +pub mod apb2otp_blk4_w9; +#[doc = "APB2OTP_BLK4_W10 (r) register accessor: eFuse apb2otp block4 data registe10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk4_w10`] module"] +pub type APB2OTP_BLK4_W10 = crate::Reg; +#[doc = "eFuse apb2otp block4 data registe10."] +pub mod apb2otp_blk4_w10; +#[doc = "APB2OTP_BLK4_W11 (r) register accessor: eFuse apb2otp block4 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk4_w11`] module"] +pub type APB2OTP_BLK4_W11 = crate::Reg; +#[doc = "eFuse apb2otp block4 data register11."] +pub mod apb2otp_blk4_w11; +#[doc = "APB2OTP_BLK5_W1 (r) register accessor: eFuse apb2otp block5 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk5_w1`] module"] +pub type APB2OTP_BLK5_W1 = crate::Reg; +#[doc = "eFuse apb2otp block5 data register1."] +pub mod apb2otp_blk5_w1; +#[doc = "APB2OTP_BLK5_W2 (r) register accessor: eFuse apb2otp block5 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk5_w2`] module"] +pub type APB2OTP_BLK5_W2 = crate::Reg; +#[doc = "eFuse apb2otp block5 data register2."] +pub mod apb2otp_blk5_w2; +#[doc = "APB2OTP_BLK5_W3 (r) register accessor: eFuse apb2otp block5 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk5_w3`] module"] +pub type APB2OTP_BLK5_W3 = crate::Reg; +#[doc = "eFuse apb2otp block5 data register3."] +pub mod apb2otp_blk5_w3; +#[doc = "APB2OTP_BLK5_W4 (r) register accessor: eFuse apb2otp block5 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk5_w4`] module"] +pub type APB2OTP_BLK5_W4 = crate::Reg; +#[doc = "eFuse apb2otp block5 data register4."] +pub mod apb2otp_blk5_w4; +#[doc = "APB2OTP_BLK5_W5 (r) register accessor: eFuse apb2otp block5 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk5_w5`] module"] +pub type APB2OTP_BLK5_W5 = crate::Reg; +#[doc = "eFuse apb2otp block5 data register5."] +pub mod apb2otp_blk5_w5; +#[doc = "APB2OTP_BLK5_W6 (r) register accessor: eFuse apb2otp block5 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk5_w6`] module"] +pub type APB2OTP_BLK5_W6 = crate::Reg; +#[doc = "eFuse apb2otp block5 data register6."] +pub mod apb2otp_blk5_w6; +#[doc = "APB2OTP_BLK5_W7 (r) register accessor: eFuse apb2otp block5 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk5_w7`] module"] +pub type APB2OTP_BLK5_W7 = crate::Reg; +#[doc = "eFuse apb2otp block5 data register7."] +pub mod apb2otp_blk5_w7; +#[doc = "APB2OTP_BLK5_W8 (r) register accessor: eFuse apb2otp block5 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk5_w8`] module"] +pub type APB2OTP_BLK5_W8 = crate::Reg; +#[doc = "eFuse apb2otp block5 data register8."] +pub mod apb2otp_blk5_w8; +#[doc = "APB2OTP_BLK5_W9 (r) register accessor: eFuse apb2otp block5 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk5_w9`] module"] +pub type APB2OTP_BLK5_W9 = crate::Reg; +#[doc = "eFuse apb2otp block5 data register9."] +pub mod apb2otp_blk5_w9; +#[doc = "APB2OTP_BLK5_W10 (r) register accessor: eFuse apb2otp block5 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk5_w10`] module"] +pub type APB2OTP_BLK5_W10 = crate::Reg; +#[doc = "eFuse apb2otp block5 data register10."] +pub mod apb2otp_blk5_w10; +#[doc = "APB2OTP_BLK5_W11 (r) register accessor: eFuse apb2otp block5 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk5_w11`] module"] +pub type APB2OTP_BLK5_W11 = crate::Reg; +#[doc = "eFuse apb2otp block5 data register11."] +pub mod apb2otp_blk5_w11; +#[doc = "APB2OTP_BLK6_W1 (r) register accessor: eFuse apb2otp block6 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk6_w1`] module"] +pub type APB2OTP_BLK6_W1 = crate::Reg; +#[doc = "eFuse apb2otp block6 data register1."] +pub mod apb2otp_blk6_w1; +#[doc = "APB2OTP_BLK6_W2 (r) register accessor: eFuse apb2otp block6 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk6_w2`] module"] +pub type APB2OTP_BLK6_W2 = crate::Reg; +#[doc = "eFuse apb2otp block6 data register2."] +pub mod apb2otp_blk6_w2; +#[doc = "APB2OTP_BLK6_W3 (r) register accessor: eFuse apb2otp block6 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk6_w3`] module"] +pub type APB2OTP_BLK6_W3 = crate::Reg; +#[doc = "eFuse apb2otp block6 data register3."] +pub mod apb2otp_blk6_w3; +#[doc = "APB2OTP_BLK6_W4 (r) register accessor: eFuse apb2otp block6 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk6_w4`] module"] +pub type APB2OTP_BLK6_W4 = crate::Reg; +#[doc = "eFuse apb2otp block6 data register4."] +pub mod apb2otp_blk6_w4; +#[doc = "APB2OTP_BLK6_W5 (r) register accessor: eFuse apb2otp block6 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk6_w5`] module"] +pub type APB2OTP_BLK6_W5 = crate::Reg; +#[doc = "eFuse apb2otp block6 data register5."] +pub mod apb2otp_blk6_w5; +#[doc = "APB2OTP_BLK6_W6 (r) register accessor: eFuse apb2otp block6 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk6_w6`] module"] +pub type APB2OTP_BLK6_W6 = crate::Reg; +#[doc = "eFuse apb2otp block6 data register6."] +pub mod apb2otp_blk6_w6; +#[doc = "APB2OTP_BLK6_W7 (r) register accessor: eFuse apb2otp block6 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk6_w7`] module"] +pub type APB2OTP_BLK6_W7 = crate::Reg; +#[doc = "eFuse apb2otp block6 data register7."] +pub mod apb2otp_blk6_w7; +#[doc = "APB2OTP_BLK6_W8 (r) register accessor: eFuse apb2otp block6 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk6_w8`] module"] +pub type APB2OTP_BLK6_W8 = crate::Reg; +#[doc = "eFuse apb2otp block6 data register8."] +pub mod apb2otp_blk6_w8; +#[doc = "APB2OTP_BLK6_W9 (r) register accessor: eFuse apb2otp block6 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk6_w9`] module"] +pub type APB2OTP_BLK6_W9 = crate::Reg; +#[doc = "eFuse apb2otp block6 data register9."] +pub mod apb2otp_blk6_w9; +#[doc = "APB2OTP_BLK6_W10 (r) register accessor: eFuse apb2otp block6 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk6_w10`] module"] +pub type APB2OTP_BLK6_W10 = crate::Reg; +#[doc = "eFuse apb2otp block6 data register10."] +pub mod apb2otp_blk6_w10; +#[doc = "APB2OTP_BLK6_W11 (r) register accessor: eFuse apb2otp block6 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk6_w11`] module"] +pub type APB2OTP_BLK6_W11 = crate::Reg; +#[doc = "eFuse apb2otp block6 data register11."] +pub mod apb2otp_blk6_w11; +#[doc = "APB2OTP_BLK7_W1 (r) register accessor: eFuse apb2otp block7 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk7_w1`] module"] +pub type APB2OTP_BLK7_W1 = crate::Reg; +#[doc = "eFuse apb2otp block7 data register1."] +pub mod apb2otp_blk7_w1; +#[doc = "APB2OTP_BLK7_W2 (r) register accessor: eFuse apb2otp block7 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk7_w2`] module"] +pub type APB2OTP_BLK7_W2 = crate::Reg; +#[doc = "eFuse apb2otp block7 data register2."] +pub mod apb2otp_blk7_w2; +#[doc = "APB2OTP_BLK7_W3 (r) register accessor: eFuse apb2otp block7 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk7_w3`] module"] +pub type APB2OTP_BLK7_W3 = crate::Reg; +#[doc = "eFuse apb2otp block7 data register3."] +pub mod apb2otp_blk7_w3; +#[doc = "APB2OTP_BLK7_W4 (r) register accessor: eFuse apb2otp block7 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk7_w4`] module"] +pub type APB2OTP_BLK7_W4 = crate::Reg; +#[doc = "eFuse apb2otp block7 data register4."] +pub mod apb2otp_blk7_w4; +#[doc = "APB2OTP_BLK7_W5 (r) register accessor: eFuse apb2otp block7 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk7_w5`] module"] +pub type APB2OTP_BLK7_W5 = crate::Reg; +#[doc = "eFuse apb2otp block7 data register5."] +pub mod apb2otp_blk7_w5; +#[doc = "APB2OTP_BLK7_W6 (r) register accessor: eFuse apb2otp block7 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk7_w6`] module"] +pub type APB2OTP_BLK7_W6 = crate::Reg; +#[doc = "eFuse apb2otp block7 data register6."] +pub mod apb2otp_blk7_w6; +#[doc = "APB2OTP_BLK7_W7 (r) register accessor: eFuse apb2otp block7 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk7_w7`] module"] +pub type APB2OTP_BLK7_W7 = crate::Reg; +#[doc = "eFuse apb2otp block7 data register7."] +pub mod apb2otp_blk7_w7; +#[doc = "APB2OTP_BLK7_W8 (r) register accessor: eFuse apb2otp block7 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk7_w8`] module"] +pub type APB2OTP_BLK7_W8 = crate::Reg; +#[doc = "eFuse apb2otp block7 data register8."] +pub mod apb2otp_blk7_w8; +#[doc = "APB2OTP_BLK7_W9 (r) register accessor: eFuse apb2otp block7 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk7_w9`] module"] +pub type APB2OTP_BLK7_W9 = crate::Reg; +#[doc = "eFuse apb2otp block7 data register9."] +pub mod apb2otp_blk7_w9; +#[doc = "APB2OTP_BLK7_W10 (r) register accessor: eFuse apb2otp block7 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk7_w10`] module"] +pub type APB2OTP_BLK7_W10 = crate::Reg; +#[doc = "eFuse apb2otp block7 data register10."] +pub mod apb2otp_blk7_w10; +#[doc = "APB2OTP_BLK7_W11 (r) register accessor: eFuse apb2otp block7 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk7_w11`] module"] +pub type APB2OTP_BLK7_W11 = crate::Reg; +#[doc = "eFuse apb2otp block7 data register11."] +pub mod apb2otp_blk7_w11; +#[doc = "APB2OTP_BLK8_W1 (r) register accessor: eFuse apb2otp block8 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk8_w1`] module"] +pub type APB2OTP_BLK8_W1 = crate::Reg; +#[doc = "eFuse apb2otp block8 data register1."] +pub mod apb2otp_blk8_w1; +#[doc = "APB2OTP_BLK8_W2 (r) register accessor: eFuse apb2otp block8 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk8_w2`] module"] +pub type APB2OTP_BLK8_W2 = crate::Reg; +#[doc = "eFuse apb2otp block8 data register2."] +pub mod apb2otp_blk8_w2; +#[doc = "APB2OTP_BLK8_W3 (r) register accessor: eFuse apb2otp block8 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk8_w3`] module"] +pub type APB2OTP_BLK8_W3 = crate::Reg; +#[doc = "eFuse apb2otp block8 data register3."] +pub mod apb2otp_blk8_w3; +#[doc = "APB2OTP_BLK8_W4 (r) register accessor: eFuse apb2otp block8 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk8_w4`] module"] +pub type APB2OTP_BLK8_W4 = crate::Reg; +#[doc = "eFuse apb2otp block8 data register4."] +pub mod apb2otp_blk8_w4; +#[doc = "APB2OTP_BLK8_W5 (r) register accessor: eFuse apb2otp block8 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk8_w5`] module"] +pub type APB2OTP_BLK8_W5 = crate::Reg; +#[doc = "eFuse apb2otp block8 data register5."] +pub mod apb2otp_blk8_w5; +#[doc = "APB2OTP_BLK8_W6 (r) register accessor: eFuse apb2otp block8 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk8_w6`] module"] +pub type APB2OTP_BLK8_W6 = crate::Reg; +#[doc = "eFuse apb2otp block8 data register6."] +pub mod apb2otp_blk8_w6; +#[doc = "APB2OTP_BLK8_W7 (r) register accessor: eFuse apb2otp block8 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk8_w7`] module"] +pub type APB2OTP_BLK8_W7 = crate::Reg; +#[doc = "eFuse apb2otp block8 data register7."] +pub mod apb2otp_blk8_w7; +#[doc = "APB2OTP_BLK8_W8 (r) register accessor: eFuse apb2otp block8 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk8_w8`] module"] +pub type APB2OTP_BLK8_W8 = crate::Reg; +#[doc = "eFuse apb2otp block8 data register8."] +pub mod apb2otp_blk8_w8; +#[doc = "APB2OTP_BLK8_W9 (r) register accessor: eFuse apb2otp block8 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk8_w9`] module"] +pub type APB2OTP_BLK8_W9 = crate::Reg; +#[doc = "eFuse apb2otp block8 data register9."] +pub mod apb2otp_blk8_w9; +#[doc = "APB2OTP_BLK8_W10 (r) register accessor: eFuse apb2otp block8 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk8_w10`] module"] +pub type APB2OTP_BLK8_W10 = crate::Reg; +#[doc = "eFuse apb2otp block8 data register10."] +pub mod apb2otp_blk8_w10; +#[doc = "APB2OTP_BLK8_W11 (r) register accessor: eFuse apb2otp block8 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk8_w11`] module"] +pub type APB2OTP_BLK8_W11 = crate::Reg; +#[doc = "eFuse apb2otp block8 data register11."] +pub mod apb2otp_blk8_w11; +#[doc = "APB2OTP_BLK9_W1 (r) register accessor: eFuse apb2otp block9 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk9_w1`] module"] +pub type APB2OTP_BLK9_W1 = crate::Reg; +#[doc = "eFuse apb2otp block9 data register1."] +pub mod apb2otp_blk9_w1; +#[doc = "APB2OTP_BLK9_W2 (r) register accessor: eFuse apb2otp block9 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk9_w2`] module"] +pub type APB2OTP_BLK9_W2 = crate::Reg; +#[doc = "eFuse apb2otp block9 data register2."] +pub mod apb2otp_blk9_w2; +#[doc = "APB2OTP_BLK9_W3 (r) register accessor: eFuse apb2otp block9 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk9_w3`] module"] +pub type APB2OTP_BLK9_W3 = crate::Reg; +#[doc = "eFuse apb2otp block9 data register3."] +pub mod apb2otp_blk9_w3; +#[doc = "APB2OTP_BLK9_W4 (r) register accessor: eFuse apb2otp block9 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk9_w4`] module"] +pub type APB2OTP_BLK9_W4 = crate::Reg; +#[doc = "eFuse apb2otp block9 data register4."] +pub mod apb2otp_blk9_w4; +#[doc = "APB2OTP_BLK9_W5 (r) register accessor: eFuse apb2otp block9 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk9_w5`] module"] +pub type APB2OTP_BLK9_W5 = crate::Reg; +#[doc = "eFuse apb2otp block9 data register5."] +pub mod apb2otp_blk9_w5; +#[doc = "APB2OTP_BLK9_W6 (r) register accessor: eFuse apb2otp block9 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk9_w6`] module"] +pub type APB2OTP_BLK9_W6 = crate::Reg; +#[doc = "eFuse apb2otp block9 data register6."] +pub mod apb2otp_blk9_w6; +#[doc = "APB2OTP_BLK9_W7 (r) register accessor: eFuse apb2otp block9 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk9_w7`] module"] +pub type APB2OTP_BLK9_W7 = crate::Reg; +#[doc = "eFuse apb2otp block9 data register7."] +pub mod apb2otp_blk9_w7; +#[doc = "APB2OTP_BLK9_W8 (r) register accessor: eFuse apb2otp block9 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk9_w8`] module"] +pub type APB2OTP_BLK9_W8 = crate::Reg; +#[doc = "eFuse apb2otp block9 data register8."] +pub mod apb2otp_blk9_w8; +#[doc = "APB2OTP_BLK9_W9 (r) register accessor: eFuse apb2otp block9 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk9_w9`] module"] +pub type APB2OTP_BLK9_W9 = crate::Reg; +#[doc = "eFuse apb2otp block9 data register9."] +pub mod apb2otp_blk9_w9; +#[doc = "APB2OTP_BLK9_W10 (r) register accessor: eFuse apb2otp block9 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk9_w10`] module"] +pub type APB2OTP_BLK9_W10 = crate::Reg; +#[doc = "eFuse apb2otp block9 data register10."] +pub mod apb2otp_blk9_w10; +#[doc = "APB2OTP_BLK9_W11 (r) register accessor: eFuse apb2otp block9 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk9_w11`] module"] +pub type APB2OTP_BLK9_W11 = crate::Reg; +#[doc = "eFuse apb2otp block9 data register11."] +pub mod apb2otp_blk9_w11; +#[doc = "APB2OTP_BLK10_W1 (r) register accessor: eFuse apb2otp block10 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk10_w1`] module"] +pub type APB2OTP_BLK10_W1 = crate::Reg; +#[doc = "eFuse apb2otp block10 data register1."] +pub mod apb2otp_blk10_w1; +#[doc = "APB2OTP_BLK10_W2 (r) register accessor: eFuse apb2otp block10 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk10_w2`] module"] +pub type APB2OTP_BLK10_W2 = crate::Reg; +#[doc = "eFuse apb2otp block10 data register2."] +pub mod apb2otp_blk10_w2; +#[doc = "APB2OTP_BLK10_W3 (r) register accessor: eFuse apb2otp block10 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk10_w3`] module"] +pub type APB2OTP_BLK10_W3 = crate::Reg; +#[doc = "eFuse apb2otp block10 data register3."] +pub mod apb2otp_blk10_w3; +#[doc = "APB2OTP_BLK10_W4 (r) register accessor: eFuse apb2otp block10 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk10_w4`] module"] +pub type APB2OTP_BLK10_W4 = crate::Reg; +#[doc = "eFuse apb2otp block10 data register4."] +pub mod apb2otp_blk10_w4; +#[doc = "APB2OTP_BLK10_W5 (r) register accessor: eFuse apb2otp block10 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk10_w5`] module"] +pub type APB2OTP_BLK10_W5 = crate::Reg; +#[doc = "eFuse apb2otp block10 data register5."] +pub mod apb2otp_blk10_w5; +#[doc = "APB2OTP_BLK10_W6 (r) register accessor: eFuse apb2otp block10 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk10_w6`] module"] +pub type APB2OTP_BLK10_W6 = crate::Reg; +#[doc = "eFuse apb2otp block10 data register6."] +pub mod apb2otp_blk10_w6; +#[doc = "APB2OTP_BLK10_W7 (r) register accessor: eFuse apb2otp block10 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk10_w7`] module"] +pub type APB2OTP_BLK10_W7 = crate::Reg; +#[doc = "eFuse apb2otp block10 data register7."] +pub mod apb2otp_blk10_w7; +#[doc = "APB2OTP_BLK10_W8 (r) register accessor: eFuse apb2otp block10 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk10_w8`] module"] +pub type APB2OTP_BLK10_W8 = crate::Reg; +#[doc = "eFuse apb2otp block10 data register8."] +pub mod apb2otp_blk10_w8; +#[doc = "APB2OTP_BLK10_W9 (r) register accessor: eFuse apb2otp block10 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk10_w9`] module"] +pub type APB2OTP_BLK10_W9 = crate::Reg; +#[doc = "eFuse apb2otp block10 data register9."] +pub mod apb2otp_blk10_w9; +#[doc = "APB2OTP_BLK10_W10 (r) register accessor: eFuse apb2otp block10 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk10_w10`] module"] +pub type APB2OTP_BLK10_W10 = crate::Reg; +#[doc = "eFuse apb2otp block10 data register10."] +pub mod apb2otp_blk10_w10; +#[doc = "APB2OTP_BLK10_W11 (r) register accessor: eFuse apb2otp block10 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_blk10_w11`] module"] +pub type APB2OTP_BLK10_W11 = crate::Reg; +#[doc = "eFuse apb2otp block10 data register11."] +pub mod apb2otp_blk10_w11; +#[doc = "APB2OTP_EN (rw) register accessor: eFuse apb2otp enable configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb2otp_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb2otp_en`] module"] +pub type APB2OTP_EN = crate::Reg; +#[doc = "eFuse apb2otp enable configuration register."] +pub mod apb2otp_en; diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup1_w1.rs b/esp32p4/src/efuse/apb2otp_blk0_backup1_w1.rs new file mode 100644 index 0000000000..1b9297f779 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup1_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP1_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP1_W1` reader - Otp block0 backup1 word1 data."] +pub type APB2OTP_BLOCK0_BACKUP1_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup1 word1 data."] + #[inline(always)] + pub fn apb2otp_block0_backup1_w1(&self) -> APB2OTP_BLOCK0_BACKUP1_W1_R { + APB2OTP_BLOCK0_BACKUP1_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP1_W1") + .field( + "apb2otp_block0_backup1_w1", + &format_args!("{}", self.apb2otp_block0_backup1_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP1_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP1_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup1_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP1_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP1_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP1_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup1_w2.rs b/esp32p4/src/efuse/apb2otp_blk0_backup1_w2.rs new file mode 100644 index 0000000000..35027c0f80 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup1_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP1_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP1_W2` reader - Otp block0 backup1 word2 data."] +pub type APB2OTP_BLOCK0_BACKUP1_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup1 word2 data."] + #[inline(always)] + pub fn apb2otp_block0_backup1_w2(&self) -> APB2OTP_BLOCK0_BACKUP1_W2_R { + APB2OTP_BLOCK0_BACKUP1_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP1_W2") + .field( + "apb2otp_block0_backup1_w2", + &format_args!("{}", self.apb2otp_block0_backup1_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP1_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP1_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup1_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP1_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP1_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP1_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup1_w3.rs b/esp32p4/src/efuse/apb2otp_blk0_backup1_w3.rs new file mode 100644 index 0000000000..9c55d55c97 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup1_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP1_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP1_W3` reader - Otp block0 backup1 word3 data."] +pub type APB2OTP_BLOCK0_BACKUP1_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup1 word3 data."] + #[inline(always)] + pub fn apb2otp_block0_backup1_w3(&self) -> APB2OTP_BLOCK0_BACKUP1_W3_R { + APB2OTP_BLOCK0_BACKUP1_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP1_W3") + .field( + "apb2otp_block0_backup1_w3", + &format_args!("{}", self.apb2otp_block0_backup1_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP1_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP1_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup1_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP1_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP1_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP1_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup1_w4.rs b/esp32p4/src/efuse/apb2otp_blk0_backup1_w4.rs new file mode 100644 index 0000000000..a94442f427 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup1_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP1_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP1_W4` reader - Otp block0 backup1 word4 data."] +pub type APB2OTP_BLOCK0_BACKUP1_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup1 word4 data."] + #[inline(always)] + pub fn apb2otp_block0_backup1_w4(&self) -> APB2OTP_BLOCK0_BACKUP1_W4_R { + APB2OTP_BLOCK0_BACKUP1_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP1_W4") + .field( + "apb2otp_block0_backup1_w4", + &format_args!("{}", self.apb2otp_block0_backup1_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP1_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP1_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup1_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP1_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP1_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP1_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup1_w5.rs b/esp32p4/src/efuse/apb2otp_blk0_backup1_w5.rs new file mode 100644 index 0000000000..b8a2da2495 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup1_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP1_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP1_W5` reader - Otp block0 backup1 word5 data."] +pub type APB2OTP_BLOCK0_BACKUP1_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup1 word5 data."] + #[inline(always)] + pub fn apb2otp_block0_backup1_w5(&self) -> APB2OTP_BLOCK0_BACKUP1_W5_R { + APB2OTP_BLOCK0_BACKUP1_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP1_W5") + .field( + "apb2otp_block0_backup1_w5", + &format_args!("{}", self.apb2otp_block0_backup1_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP1_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP1_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup1_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP1_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP1_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP1_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup2_w1.rs b/esp32p4/src/efuse/apb2otp_blk0_backup2_w1.rs new file mode 100644 index 0000000000..cb62180782 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup2_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP2_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP2_W1` reader - Otp block0 backup2 word1 data."] +pub type APB2OTP_BLOCK0_BACKUP2_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup2 word1 data."] + #[inline(always)] + pub fn apb2otp_block0_backup2_w1(&self) -> APB2OTP_BLOCK0_BACKUP2_W1_R { + APB2OTP_BLOCK0_BACKUP2_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP2_W1") + .field( + "apb2otp_block0_backup2_w1", + &format_args!("{}", self.apb2otp_block0_backup2_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP2_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP2_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup2_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP2_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP2_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP2_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup2_w2.rs b/esp32p4/src/efuse/apb2otp_blk0_backup2_w2.rs new file mode 100644 index 0000000000..f9be19bc56 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup2_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP2_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP2_W2` reader - Otp block0 backup2 word2 data."] +pub type APB2OTP_BLOCK0_BACKUP2_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup2 word2 data."] + #[inline(always)] + pub fn apb2otp_block0_backup2_w2(&self) -> APB2OTP_BLOCK0_BACKUP2_W2_R { + APB2OTP_BLOCK0_BACKUP2_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP2_W2") + .field( + "apb2otp_block0_backup2_w2", + &format_args!("{}", self.apb2otp_block0_backup2_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP2_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP2_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup2_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP2_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP2_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP2_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup2_w3.rs b/esp32p4/src/efuse/apb2otp_blk0_backup2_w3.rs new file mode 100644 index 0000000000..262bb0029d --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup2_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP2_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP2_W3` reader - Otp block0 backup2 word3 data."] +pub type APB2OTP_BLOCK0_BACKUP2_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup2 word3 data."] + #[inline(always)] + pub fn apb2otp_block0_backup2_w3(&self) -> APB2OTP_BLOCK0_BACKUP2_W3_R { + APB2OTP_BLOCK0_BACKUP2_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP2_W3") + .field( + "apb2otp_block0_backup2_w3", + &format_args!("{}", self.apb2otp_block0_backup2_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP2_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP2_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup2_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP2_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP2_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP2_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup2_w4.rs b/esp32p4/src/efuse/apb2otp_blk0_backup2_w4.rs new file mode 100644 index 0000000000..980fbb9a28 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup2_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP2_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP2_W4` reader - Otp block0 backup2 word4 data."] +pub type APB2OTP_BLOCK0_BACKUP2_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup2 word4 data."] + #[inline(always)] + pub fn apb2otp_block0_backup2_w4(&self) -> APB2OTP_BLOCK0_BACKUP2_W4_R { + APB2OTP_BLOCK0_BACKUP2_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP2_W4") + .field( + "apb2otp_block0_backup2_w4", + &format_args!("{}", self.apb2otp_block0_backup2_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP2_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP2_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup2_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP2_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP2_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP2_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup2_w5.rs b/esp32p4/src/efuse/apb2otp_blk0_backup2_w5.rs new file mode 100644 index 0000000000..b22c51f79a --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup2_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP2_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP2_W5` reader - Otp block0 backup2 word5 data."] +pub type APB2OTP_BLOCK0_BACKUP2_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup2 word5 data."] + #[inline(always)] + pub fn apb2otp_block0_backup2_w5(&self) -> APB2OTP_BLOCK0_BACKUP2_W5_R { + APB2OTP_BLOCK0_BACKUP2_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP2_W5") + .field( + "apb2otp_block0_backup2_w5", + &format_args!("{}", self.apb2otp_block0_backup2_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP2_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP2_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup2_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP2_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP2_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP2_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup3_w1.rs b/esp32p4/src/efuse/apb2otp_blk0_backup3_w1.rs new file mode 100644 index 0000000000..7e181bdede --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup3_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP3_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP3_W1` reader - Otp block0 backup3 word1 data."] +pub type APB2OTP_BLOCK0_BACKUP3_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup3 word1 data."] + #[inline(always)] + pub fn apb2otp_block0_backup3_w1(&self) -> APB2OTP_BLOCK0_BACKUP3_W1_R { + APB2OTP_BLOCK0_BACKUP3_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP3_W1") + .field( + "apb2otp_block0_backup3_w1", + &format_args!("{}", self.apb2otp_block0_backup3_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register12.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP3_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP3_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup3_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP3_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP3_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP3_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup3_w2.rs b/esp32p4/src/efuse/apb2otp_blk0_backup3_w2.rs new file mode 100644 index 0000000000..7767361fca --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup3_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP3_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP3_W2` reader - Otp block0 backup3 word2 data."] +pub type APB2OTP_BLOCK0_BACKUP3_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup3 word2 data."] + #[inline(always)] + pub fn apb2otp_block0_backup3_w2(&self) -> APB2OTP_BLOCK0_BACKUP3_W2_R { + APB2OTP_BLOCK0_BACKUP3_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP3_W2") + .field( + "apb2otp_block0_backup3_w2", + &format_args!("{}", self.apb2otp_block0_backup3_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register13.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP3_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP3_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup3_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP3_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP3_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP3_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup3_w3.rs b/esp32p4/src/efuse/apb2otp_blk0_backup3_w3.rs new file mode 100644 index 0000000000..c84676205b --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup3_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP3_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP3_W3` reader - Otp block0 backup3 word3 data."] +pub type APB2OTP_BLOCK0_BACKUP3_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup3 word3 data."] + #[inline(always)] + pub fn apb2otp_block0_backup3_w3(&self) -> APB2OTP_BLOCK0_BACKUP3_W3_R { + APB2OTP_BLOCK0_BACKUP3_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP3_W3") + .field( + "apb2otp_block0_backup3_w3", + &format_args!("{}", self.apb2otp_block0_backup3_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register14.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP3_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP3_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup3_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP3_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP3_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP3_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup3_w4.rs b/esp32p4/src/efuse/apb2otp_blk0_backup3_w4.rs new file mode 100644 index 0000000000..f3466fa66b --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup3_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP3_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP3_W4` reader - Otp block0 backup3 word4 data."] +pub type APB2OTP_BLOCK0_BACKUP3_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup3 word4 data."] + #[inline(always)] + pub fn apb2otp_block0_backup3_w4(&self) -> APB2OTP_BLOCK0_BACKUP3_W4_R { + APB2OTP_BLOCK0_BACKUP3_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP3_W4") + .field( + "apb2otp_block0_backup3_w4", + &format_args!("{}", self.apb2otp_block0_backup3_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register15.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP3_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP3_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup3_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP3_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP3_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP3_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup3_w5.rs b/esp32p4/src/efuse/apb2otp_blk0_backup3_w5.rs new file mode 100644 index 0000000000..a0f43a7ae4 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup3_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP3_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP3_W5` reader - Otp block0 backup3 word5 data."] +pub type APB2OTP_BLOCK0_BACKUP3_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup3 word5 data."] + #[inline(always)] + pub fn apb2otp_block0_backup3_w5(&self) -> APB2OTP_BLOCK0_BACKUP3_W5_R { + APB2OTP_BLOCK0_BACKUP3_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP3_W5") + .field( + "apb2otp_block0_backup3_w5", + &format_args!("{}", self.apb2otp_block0_backup3_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register16.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP3_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP3_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup3_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP3_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP3_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP3_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup4_w1.rs b/esp32p4/src/efuse/apb2otp_blk0_backup4_w1.rs new file mode 100644 index 0000000000..699200e2ad --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup4_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP4_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP4_W1` reader - Otp block0 backup4 word1 data."] +pub type APB2OTP_BLOCK0_BACKUP4_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup4 word1 data."] + #[inline(always)] + pub fn apb2otp_block0_backup4_w1(&self) -> APB2OTP_BLOCK0_BACKUP4_W1_R { + APB2OTP_BLOCK0_BACKUP4_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP4_W1") + .field( + "apb2otp_block0_backup4_w1", + &format_args!("{}", self.apb2otp_block0_backup4_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register17.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP4_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP4_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup4_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP4_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP4_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP4_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup4_w2.rs b/esp32p4/src/efuse/apb2otp_blk0_backup4_w2.rs new file mode 100644 index 0000000000..e70373cc6a --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup4_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP4_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP4_W2` reader - Otp block0 backup4 word2 data."] +pub type APB2OTP_BLOCK0_BACKUP4_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup4 word2 data."] + #[inline(always)] + pub fn apb2otp_block0_backup4_w2(&self) -> APB2OTP_BLOCK0_BACKUP4_W2_R { + APB2OTP_BLOCK0_BACKUP4_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP4_W2") + .field( + "apb2otp_block0_backup4_w2", + &format_args!("{}", self.apb2otp_block0_backup4_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register18.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP4_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP4_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup4_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP4_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP4_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP4_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup4_w3.rs b/esp32p4/src/efuse/apb2otp_blk0_backup4_w3.rs new file mode 100644 index 0000000000..cd683942b8 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup4_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP4_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP4_W3` reader - Otp block0 backup4 word3 data."] +pub type APB2OTP_BLOCK0_BACKUP4_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup4 word3 data."] + #[inline(always)] + pub fn apb2otp_block0_backup4_w3(&self) -> APB2OTP_BLOCK0_BACKUP4_W3_R { + APB2OTP_BLOCK0_BACKUP4_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP4_W3") + .field( + "apb2otp_block0_backup4_w3", + &format_args!("{}", self.apb2otp_block0_backup4_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register19.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP4_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP4_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup4_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP4_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP4_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP4_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup4_w4.rs b/esp32p4/src/efuse/apb2otp_blk0_backup4_w4.rs new file mode 100644 index 0000000000..3a32e2a8db --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup4_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP4_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP4_W4` reader - Otp block0 backup4 word4 data."] +pub type APB2OTP_BLOCK0_BACKUP4_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup4 word4 data."] + #[inline(always)] + pub fn apb2otp_block0_backup4_w4(&self) -> APB2OTP_BLOCK0_BACKUP4_W4_R { + APB2OTP_BLOCK0_BACKUP4_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP4_W4") + .field( + "apb2otp_block0_backup4_w4", + &format_args!("{}", self.apb2otp_block0_backup4_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register20.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP4_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP4_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup4_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP4_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP4_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP4_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup4_w5.rs b/esp32p4/src/efuse/apb2otp_blk0_backup4_w5.rs new file mode 100644 index 0000000000..33096f0d72 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk0_backup4_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK0_BACKUP4_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_BACKUP4_W5` reader - Otp block0 backup4 word5 data."] +pub type APB2OTP_BLOCK0_BACKUP4_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 backup4 word5 data."] + #[inline(always)] + pub fn apb2otp_block0_backup4_w5(&self) -> APB2OTP_BLOCK0_BACKUP4_W5_R { + APB2OTP_BLOCK0_BACKUP4_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK0_BACKUP4_W5") + .field( + "apb2otp_block0_backup4_w5", + &format_args!("{}", self.apb2otp_block0_backup4_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register21.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK0_BACKUP4_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP4_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk0_backup4_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK0_BACKUP4_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK0_BACKUP4_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK0_BACKUP4_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk10_w1.rs b/esp32p4/src/efuse/apb2otp_blk10_w1.rs new file mode 100644 index 0000000000..d06a3666c4 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk10_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK10_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK10_W1` reader - Otp block10 word1 data."] +pub type APB2OTP_BLOCK10_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block10 word1 data."] + #[inline(always)] + pub fn apb2otp_block10_w1(&self) -> APB2OTP_BLOCK10_W1_R { + APB2OTP_BLOCK10_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK10_W1") + .field( + "apb2otp_block10_w1", + &format_args!("{}", self.apb2otp_block10_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block10 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK10_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK10_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk10_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK10_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK10_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK10_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk10_w10.rs b/esp32p4/src/efuse/apb2otp_blk10_w10.rs new file mode 100644 index 0000000000..81a61c5491 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk10_w10.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK10_W10` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK19_W10` reader - Otp block10 word10 data."] +pub type APB2OTP_BLOCK19_W10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block10 word10 data."] + #[inline(always)] + pub fn apb2otp_block19_w10(&self) -> APB2OTP_BLOCK19_W10_R { + APB2OTP_BLOCK19_W10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK10_W10") + .field( + "apb2otp_block19_w10", + &format_args!("{}", self.apb2otp_block19_w10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block10 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK10_W10_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK10_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk10_w10::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK10_W10_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK10_W10 to value 0"] +impl crate::Resettable for APB2OTP_BLK10_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk10_w11.rs b/esp32p4/src/efuse/apb2otp_blk10_w11.rs new file mode 100644 index 0000000000..e01aa6ee41 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk10_w11.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK10_W11` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK10_W11` reader - Otp block10 word11 data."] +pub type APB2OTP_BLOCK10_W11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block10 word11 data."] + #[inline(always)] + pub fn apb2otp_block10_w11(&self) -> APB2OTP_BLOCK10_W11_R { + APB2OTP_BLOCK10_W11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK10_W11") + .field( + "apb2otp_block10_w11", + &format_args!("{}", self.apb2otp_block10_w11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block10 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK10_W11_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK10_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk10_w11::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK10_W11_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK10_W11 to value 0"] +impl crate::Resettable for APB2OTP_BLK10_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk10_w2.rs b/esp32p4/src/efuse/apb2otp_blk10_w2.rs new file mode 100644 index 0000000000..127a5c55c4 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk10_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK10_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK10_W2` reader - Otp block10 word2 data."] +pub type APB2OTP_BLOCK10_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block10 word2 data."] + #[inline(always)] + pub fn apb2otp_block10_w2(&self) -> APB2OTP_BLOCK10_W2_R { + APB2OTP_BLOCK10_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK10_W2") + .field( + "apb2otp_block10_w2", + &format_args!("{}", self.apb2otp_block10_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block10 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK10_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK10_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk10_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK10_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK10_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK10_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk10_w3.rs b/esp32p4/src/efuse/apb2otp_blk10_w3.rs new file mode 100644 index 0000000000..9644fdd9b4 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk10_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK10_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK10_W3` reader - Otp block10 word3 data."] +pub type APB2OTP_BLOCK10_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block10 word3 data."] + #[inline(always)] + pub fn apb2otp_block10_w3(&self) -> APB2OTP_BLOCK10_W3_R { + APB2OTP_BLOCK10_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK10_W3") + .field( + "apb2otp_block10_w3", + &format_args!("{}", self.apb2otp_block10_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block10 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK10_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK10_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk10_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK10_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK10_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK10_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk10_w4.rs b/esp32p4/src/efuse/apb2otp_blk10_w4.rs new file mode 100644 index 0000000000..b297679d08 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk10_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK10_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK10_W4` reader - Otp block10 word4 data."] +pub type APB2OTP_BLOCK10_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block10 word4 data."] + #[inline(always)] + pub fn apb2otp_block10_w4(&self) -> APB2OTP_BLOCK10_W4_R { + APB2OTP_BLOCK10_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK10_W4") + .field( + "apb2otp_block10_w4", + &format_args!("{}", self.apb2otp_block10_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block10 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK10_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK10_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk10_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK10_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK10_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK10_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk10_w5.rs b/esp32p4/src/efuse/apb2otp_blk10_w5.rs new file mode 100644 index 0000000000..ffc6c668d7 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk10_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK10_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK10_W5` reader - Otp block10 word5 data."] +pub type APB2OTP_BLOCK10_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block10 word5 data."] + #[inline(always)] + pub fn apb2otp_block10_w5(&self) -> APB2OTP_BLOCK10_W5_R { + APB2OTP_BLOCK10_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK10_W5") + .field( + "apb2otp_block10_w5", + &format_args!("{}", self.apb2otp_block10_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block10 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK10_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK10_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk10_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK10_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK10_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK10_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk10_w6.rs b/esp32p4/src/efuse/apb2otp_blk10_w6.rs new file mode 100644 index 0000000000..88ca9a13e6 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk10_w6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK10_W6` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK10_W6` reader - Otp block10 word6 data."] +pub type APB2OTP_BLOCK10_W6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block10 word6 data."] + #[inline(always)] + pub fn apb2otp_block10_w6(&self) -> APB2OTP_BLOCK10_W6_R { + APB2OTP_BLOCK10_W6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK10_W6") + .field( + "apb2otp_block10_w6", + &format_args!("{}", self.apb2otp_block10_w6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block10 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK10_W6_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK10_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk10_w6::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK10_W6_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK10_W6 to value 0"] +impl crate::Resettable for APB2OTP_BLK10_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk10_w7.rs b/esp32p4/src/efuse/apb2otp_blk10_w7.rs new file mode 100644 index 0000000000..b14756248b --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk10_w7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK10_W7` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK10_W7` reader - Otp block10 word7 data."] +pub type APB2OTP_BLOCK10_W7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block10 word7 data."] + #[inline(always)] + pub fn apb2otp_block10_w7(&self) -> APB2OTP_BLOCK10_W7_R { + APB2OTP_BLOCK10_W7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK10_W7") + .field( + "apb2otp_block10_w7", + &format_args!("{}", self.apb2otp_block10_w7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block10 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK10_W7_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK10_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk10_w7::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK10_W7_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK10_W7 to value 0"] +impl crate::Resettable for APB2OTP_BLK10_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk10_w8.rs b/esp32p4/src/efuse/apb2otp_blk10_w8.rs new file mode 100644 index 0000000000..8bbd3acf5e --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk10_w8.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK10_W8` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK10_W8` reader - Otp block10 word8 data."] +pub type APB2OTP_BLOCK10_W8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block10 word8 data."] + #[inline(always)] + pub fn apb2otp_block10_w8(&self) -> APB2OTP_BLOCK10_W8_R { + APB2OTP_BLOCK10_W8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK10_W8") + .field( + "apb2otp_block10_w8", + &format_args!("{}", self.apb2otp_block10_w8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block10 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK10_W8_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK10_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk10_w8::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK10_W8_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK10_W8 to value 0"] +impl crate::Resettable for APB2OTP_BLK10_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk10_w9.rs b/esp32p4/src/efuse/apb2otp_blk10_w9.rs new file mode 100644 index 0000000000..dec9b7fade --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk10_w9.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK10_W9` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK10_W9` reader - Otp block10 word9 data."] +pub type APB2OTP_BLOCK10_W9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block10 word9 data."] + #[inline(always)] + pub fn apb2otp_block10_w9(&self) -> APB2OTP_BLOCK10_W9_R { + APB2OTP_BLOCK10_W9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK10_W9") + .field( + "apb2otp_block10_w9", + &format_args!("{}", self.apb2otp_block10_w9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block10 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK10_W9_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK10_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk10_w9::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK10_W9_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK10_W9 to value 0"] +impl crate::Resettable for APB2OTP_BLK10_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk1_w1.rs b/esp32p4/src/efuse/apb2otp_blk1_w1.rs new file mode 100644 index 0000000000..a78f4a9dc0 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk1_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK1_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK1_W1` reader - Otp block1 word1 data."] +pub type APB2OTP_BLOCK1_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block1 word1 data."] + #[inline(always)] + pub fn apb2otp_block1_w1(&self) -> APB2OTP_BLOCK1_W1_R { + APB2OTP_BLOCK1_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK1_W1") + .field( + "apb2otp_block1_w1", + &format_args!("{}", self.apb2otp_block1_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block1 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK1_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK1_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk1_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK1_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK1_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK1_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk1_w2.rs b/esp32p4/src/efuse/apb2otp_blk1_w2.rs new file mode 100644 index 0000000000..927b0ebf39 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk1_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK1_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK1_W2` reader - Otp block1 word2 data."] +pub type APB2OTP_BLOCK1_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block1 word2 data."] + #[inline(always)] + pub fn apb2otp_block1_w2(&self) -> APB2OTP_BLOCK1_W2_R { + APB2OTP_BLOCK1_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK1_W2") + .field( + "apb2otp_block1_w2", + &format_args!("{}", self.apb2otp_block1_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block1 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK1_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK1_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk1_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK1_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK1_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK1_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk1_w3.rs b/esp32p4/src/efuse/apb2otp_blk1_w3.rs new file mode 100644 index 0000000000..7023281050 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk1_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK1_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK1_W3` reader - Otp block1 word3 data."] +pub type APB2OTP_BLOCK1_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block1 word3 data."] + #[inline(always)] + pub fn apb2otp_block1_w3(&self) -> APB2OTP_BLOCK1_W3_R { + APB2OTP_BLOCK1_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK1_W3") + .field( + "apb2otp_block1_w3", + &format_args!("{}", self.apb2otp_block1_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block1 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK1_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK1_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk1_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK1_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK1_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK1_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk1_w4.rs b/esp32p4/src/efuse/apb2otp_blk1_w4.rs new file mode 100644 index 0000000000..ff4d87e07f --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk1_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK1_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK1_W4` reader - Otp block1 word4 data."] +pub type APB2OTP_BLOCK1_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block1 word4 data."] + #[inline(always)] + pub fn apb2otp_block1_w4(&self) -> APB2OTP_BLOCK1_W4_R { + APB2OTP_BLOCK1_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK1_W4") + .field( + "apb2otp_block1_w4", + &format_args!("{}", self.apb2otp_block1_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block1 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK1_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK1_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk1_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK1_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK1_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK1_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk1_w5.rs b/esp32p4/src/efuse/apb2otp_blk1_w5.rs new file mode 100644 index 0000000000..db456befad --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk1_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK1_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK1_W5` reader - Otp block1 word5 data."] +pub type APB2OTP_BLOCK1_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block1 word5 data."] + #[inline(always)] + pub fn apb2otp_block1_w5(&self) -> APB2OTP_BLOCK1_W5_R { + APB2OTP_BLOCK1_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK1_W5") + .field( + "apb2otp_block1_w5", + &format_args!("{}", self.apb2otp_block1_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block1 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK1_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK1_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk1_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK1_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK1_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK1_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk1_w6.rs b/esp32p4/src/efuse/apb2otp_blk1_w6.rs new file mode 100644 index 0000000000..a1bb28b403 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk1_w6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK1_W6` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK1_W6` reader - Otp block1 word6 data."] +pub type APB2OTP_BLOCK1_W6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block1 word6 data."] + #[inline(always)] + pub fn apb2otp_block1_w6(&self) -> APB2OTP_BLOCK1_W6_R { + APB2OTP_BLOCK1_W6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK1_W6") + .field( + "apb2otp_block1_w6", + &format_args!("{}", self.apb2otp_block1_w6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block1 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK1_W6_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK1_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk1_w6::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK1_W6_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK1_W6 to value 0"] +impl crate::Resettable for APB2OTP_BLK1_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk1_w7.rs b/esp32p4/src/efuse/apb2otp_blk1_w7.rs new file mode 100644 index 0000000000..d6e0ab7605 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk1_w7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK1_W7` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK1_W7` reader - Otp block1 word7 data."] +pub type APB2OTP_BLOCK1_W7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block1 word7 data."] + #[inline(always)] + pub fn apb2otp_block1_w7(&self) -> APB2OTP_BLOCK1_W7_R { + APB2OTP_BLOCK1_W7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK1_W7") + .field( + "apb2otp_block1_w7", + &format_args!("{}", self.apb2otp_block1_w7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block1 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK1_W7_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK1_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk1_w7::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK1_W7_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK1_W7 to value 0"] +impl crate::Resettable for APB2OTP_BLK1_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk1_w8.rs b/esp32p4/src/efuse/apb2otp_blk1_w8.rs new file mode 100644 index 0000000000..5eb5699de2 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk1_w8.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK1_W8` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK1_W8` reader - Otp block1 word8 data."] +pub type APB2OTP_BLOCK1_W8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block1 word8 data."] + #[inline(always)] + pub fn apb2otp_block1_w8(&self) -> APB2OTP_BLOCK1_W8_R { + APB2OTP_BLOCK1_W8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK1_W8") + .field( + "apb2otp_block1_w8", + &format_args!("{}", self.apb2otp_block1_w8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block1 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK1_W8_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK1_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk1_w8::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK1_W8_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK1_W8 to value 0"] +impl crate::Resettable for APB2OTP_BLK1_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk1_w9.rs b/esp32p4/src/efuse/apb2otp_blk1_w9.rs new file mode 100644 index 0000000000..845f93f91f --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk1_w9.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK1_W9` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK1_W9` reader - Otp block1 word9 data."] +pub type APB2OTP_BLOCK1_W9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block1 word9 data."] + #[inline(always)] + pub fn apb2otp_block1_w9(&self) -> APB2OTP_BLOCK1_W9_R { + APB2OTP_BLOCK1_W9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK1_W9") + .field( + "apb2otp_block1_w9", + &format_args!("{}", self.apb2otp_block1_w9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block1 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK1_W9_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK1_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk1_w9::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK1_W9_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK1_W9 to value 0"] +impl crate::Resettable for APB2OTP_BLK1_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk2_w1.rs b/esp32p4/src/efuse/apb2otp_blk2_w1.rs new file mode 100644 index 0000000000..7b62b44b04 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk2_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK2_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK2_W1` reader - Otp block2 word1 data."] +pub type APB2OTP_BLOCK2_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block2 word1 data."] + #[inline(always)] + pub fn apb2otp_block2_w1(&self) -> APB2OTP_BLOCK2_W1_R { + APB2OTP_BLOCK2_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK2_W1") + .field( + "apb2otp_block2_w1", + &format_args!("{}", self.apb2otp_block2_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block2 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK2_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK2_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk2_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK2_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK2_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK2_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk2_w10.rs b/esp32p4/src/efuse/apb2otp_blk2_w10.rs new file mode 100644 index 0000000000..65a16ff76a --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk2_w10.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK2_W10` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK2_W10` reader - Otp block2 word10 data."] +pub type APB2OTP_BLOCK2_W10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block2 word10 data."] + #[inline(always)] + pub fn apb2otp_block2_w10(&self) -> APB2OTP_BLOCK2_W10_R { + APB2OTP_BLOCK2_W10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK2_W10") + .field( + "apb2otp_block2_w10", + &format_args!("{}", self.apb2otp_block2_w10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block2 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK2_W10_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK2_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk2_w10::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK2_W10_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK2_W10 to value 0"] +impl crate::Resettable for APB2OTP_BLK2_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk2_w11.rs b/esp32p4/src/efuse/apb2otp_blk2_w11.rs new file mode 100644 index 0000000000..0669998d08 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk2_w11.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK2_W11` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK2_W11` reader - Otp block2 word11 data."] +pub type APB2OTP_BLOCK2_W11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block2 word11 data."] + #[inline(always)] + pub fn apb2otp_block2_w11(&self) -> APB2OTP_BLOCK2_W11_R { + APB2OTP_BLOCK2_W11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK2_W11") + .field( + "apb2otp_block2_w11", + &format_args!("{}", self.apb2otp_block2_w11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block2 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK2_W11_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK2_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk2_w11::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK2_W11_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK2_W11 to value 0"] +impl crate::Resettable for APB2OTP_BLK2_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk2_w2.rs b/esp32p4/src/efuse/apb2otp_blk2_w2.rs new file mode 100644 index 0000000000..cf10ac909f --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk2_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK2_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK2_W2` reader - Otp block2 word2 data."] +pub type APB2OTP_BLOCK2_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block2 word2 data."] + #[inline(always)] + pub fn apb2otp_block2_w2(&self) -> APB2OTP_BLOCK2_W2_R { + APB2OTP_BLOCK2_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK2_W2") + .field( + "apb2otp_block2_w2", + &format_args!("{}", self.apb2otp_block2_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block2 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK2_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK2_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk2_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK2_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK2_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK2_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk2_w3.rs b/esp32p4/src/efuse/apb2otp_blk2_w3.rs new file mode 100644 index 0000000000..eb0f17ce7f --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk2_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK2_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK2_W3` reader - Otp block2 word3 data."] +pub type APB2OTP_BLOCK2_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block2 word3 data."] + #[inline(always)] + pub fn apb2otp_block2_w3(&self) -> APB2OTP_BLOCK2_W3_R { + APB2OTP_BLOCK2_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK2_W3") + .field( + "apb2otp_block2_w3", + &format_args!("{}", self.apb2otp_block2_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block2 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK2_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK2_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk2_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK2_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK2_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK2_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk2_w4.rs b/esp32p4/src/efuse/apb2otp_blk2_w4.rs new file mode 100644 index 0000000000..c5bc2e05d8 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk2_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK2_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK2_W4` reader - Otp block2 word4 data."] +pub type APB2OTP_BLOCK2_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block2 word4 data."] + #[inline(always)] + pub fn apb2otp_block2_w4(&self) -> APB2OTP_BLOCK2_W4_R { + APB2OTP_BLOCK2_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK2_W4") + .field( + "apb2otp_block2_w4", + &format_args!("{}", self.apb2otp_block2_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block2 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK2_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK2_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk2_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK2_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK2_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK2_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk2_w5.rs b/esp32p4/src/efuse/apb2otp_blk2_w5.rs new file mode 100644 index 0000000000..665e5ca4c1 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk2_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK2_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK2_W5` reader - Otp block2 word5 data."] +pub type APB2OTP_BLOCK2_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block2 word5 data."] + #[inline(always)] + pub fn apb2otp_block2_w5(&self) -> APB2OTP_BLOCK2_W5_R { + APB2OTP_BLOCK2_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK2_W5") + .field( + "apb2otp_block2_w5", + &format_args!("{}", self.apb2otp_block2_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block2 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK2_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK2_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk2_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK2_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK2_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK2_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk2_w6.rs b/esp32p4/src/efuse/apb2otp_blk2_w6.rs new file mode 100644 index 0000000000..a08f261661 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk2_w6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK2_W6` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK2_W6` reader - Otp block2 word6 data."] +pub type APB2OTP_BLOCK2_W6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block2 word6 data."] + #[inline(always)] + pub fn apb2otp_block2_w6(&self) -> APB2OTP_BLOCK2_W6_R { + APB2OTP_BLOCK2_W6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK2_W6") + .field( + "apb2otp_block2_w6", + &format_args!("{}", self.apb2otp_block2_w6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block2 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK2_W6_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK2_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk2_w6::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK2_W6_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK2_W6 to value 0"] +impl crate::Resettable for APB2OTP_BLK2_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk2_w7.rs b/esp32p4/src/efuse/apb2otp_blk2_w7.rs new file mode 100644 index 0000000000..90cbd69a71 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk2_w7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK2_W7` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK2_W7` reader - Otp block2 word7 data."] +pub type APB2OTP_BLOCK2_W7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block2 word7 data."] + #[inline(always)] + pub fn apb2otp_block2_w7(&self) -> APB2OTP_BLOCK2_W7_R { + APB2OTP_BLOCK2_W7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK2_W7") + .field( + "apb2otp_block2_w7", + &format_args!("{}", self.apb2otp_block2_w7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block2 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK2_W7_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK2_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk2_w7::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK2_W7_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK2_W7 to value 0"] +impl crate::Resettable for APB2OTP_BLK2_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk2_w8.rs b/esp32p4/src/efuse/apb2otp_blk2_w8.rs new file mode 100644 index 0000000000..11ab801fa7 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk2_w8.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK2_W8` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK2_W8` reader - Otp block2 word8 data."] +pub type APB2OTP_BLOCK2_W8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block2 word8 data."] + #[inline(always)] + pub fn apb2otp_block2_w8(&self) -> APB2OTP_BLOCK2_W8_R { + APB2OTP_BLOCK2_W8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK2_W8") + .field( + "apb2otp_block2_w8", + &format_args!("{}", self.apb2otp_block2_w8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block2 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK2_W8_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK2_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk2_w8::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK2_W8_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK2_W8 to value 0"] +impl crate::Resettable for APB2OTP_BLK2_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk2_w9.rs b/esp32p4/src/efuse/apb2otp_blk2_w9.rs new file mode 100644 index 0000000000..fb5710181d --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk2_w9.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK2_W9` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK2_W9` reader - Otp block2 word9 data."] +pub type APB2OTP_BLOCK2_W9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block2 word9 data."] + #[inline(always)] + pub fn apb2otp_block2_w9(&self) -> APB2OTP_BLOCK2_W9_R { + APB2OTP_BLOCK2_W9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK2_W9") + .field( + "apb2otp_block2_w9", + &format_args!("{}", self.apb2otp_block2_w9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block2 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK2_W9_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK2_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk2_w9::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK2_W9_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK2_W9 to value 0"] +impl crate::Resettable for APB2OTP_BLK2_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk3_w1.rs b/esp32p4/src/efuse/apb2otp_blk3_w1.rs new file mode 100644 index 0000000000..40b7adcfd1 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk3_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK3_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK3_W1` reader - Otp block3 word1 data."] +pub type APB2OTP_BLOCK3_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block3 word1 data."] + #[inline(always)] + pub fn apb2otp_block3_w1(&self) -> APB2OTP_BLOCK3_W1_R { + APB2OTP_BLOCK3_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK3_W1") + .field( + "apb2otp_block3_w1", + &format_args!("{}", self.apb2otp_block3_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block3 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK3_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK3_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk3_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK3_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK3_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK3_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk3_w10.rs b/esp32p4/src/efuse/apb2otp_blk3_w10.rs new file mode 100644 index 0000000000..17438ec98d --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk3_w10.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK3_W10` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK3_W10` reader - Otp block3 word10 data."] +pub type APB2OTP_BLOCK3_W10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block3 word10 data."] + #[inline(always)] + pub fn apb2otp_block3_w10(&self) -> APB2OTP_BLOCK3_W10_R { + APB2OTP_BLOCK3_W10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK3_W10") + .field( + "apb2otp_block3_w10", + &format_args!("{}", self.apb2otp_block3_w10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block3 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK3_W10_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK3_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk3_w10::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK3_W10_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK3_W10 to value 0"] +impl crate::Resettable for APB2OTP_BLK3_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk3_w11.rs b/esp32p4/src/efuse/apb2otp_blk3_w11.rs new file mode 100644 index 0000000000..2d86bf0a44 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk3_w11.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK3_W11` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK3_W11` reader - Otp block3 word11 data."] +pub type APB2OTP_BLOCK3_W11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block3 word11 data."] + #[inline(always)] + pub fn apb2otp_block3_w11(&self) -> APB2OTP_BLOCK3_W11_R { + APB2OTP_BLOCK3_W11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK3_W11") + .field( + "apb2otp_block3_w11", + &format_args!("{}", self.apb2otp_block3_w11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block3 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK3_W11_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK3_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk3_w11::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK3_W11_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK3_W11 to value 0"] +impl crate::Resettable for APB2OTP_BLK3_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk3_w2.rs b/esp32p4/src/efuse/apb2otp_blk3_w2.rs new file mode 100644 index 0000000000..a07bf1ae8a --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk3_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK3_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK3_W2` reader - Otp block3 word2 data."] +pub type APB2OTP_BLOCK3_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block3 word2 data."] + #[inline(always)] + pub fn apb2otp_block3_w2(&self) -> APB2OTP_BLOCK3_W2_R { + APB2OTP_BLOCK3_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK3_W2") + .field( + "apb2otp_block3_w2", + &format_args!("{}", self.apb2otp_block3_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block3 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK3_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK3_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk3_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK3_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK3_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK3_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk3_w3.rs b/esp32p4/src/efuse/apb2otp_blk3_w3.rs new file mode 100644 index 0000000000..7609ef8b49 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk3_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK3_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK3_W3` reader - Otp block3 word3 data."] +pub type APB2OTP_BLOCK3_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block3 word3 data."] + #[inline(always)] + pub fn apb2otp_block3_w3(&self) -> APB2OTP_BLOCK3_W3_R { + APB2OTP_BLOCK3_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK3_W3") + .field( + "apb2otp_block3_w3", + &format_args!("{}", self.apb2otp_block3_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block3 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK3_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK3_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk3_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK3_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK3_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK3_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk3_w4.rs b/esp32p4/src/efuse/apb2otp_blk3_w4.rs new file mode 100644 index 0000000000..815118de5b --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk3_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK3_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK3_W4` reader - Otp block3 word4 data."] +pub type APB2OTP_BLOCK3_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block3 word4 data."] + #[inline(always)] + pub fn apb2otp_block3_w4(&self) -> APB2OTP_BLOCK3_W4_R { + APB2OTP_BLOCK3_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK3_W4") + .field( + "apb2otp_block3_w4", + &format_args!("{}", self.apb2otp_block3_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block3 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK3_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK3_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk3_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK3_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK3_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK3_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk3_w5.rs b/esp32p4/src/efuse/apb2otp_blk3_w5.rs new file mode 100644 index 0000000000..b90bcc7cbc --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk3_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK3_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK3_W5` reader - Otp block3 word5 data."] +pub type APB2OTP_BLOCK3_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block3 word5 data."] + #[inline(always)] + pub fn apb2otp_block3_w5(&self) -> APB2OTP_BLOCK3_W5_R { + APB2OTP_BLOCK3_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK3_W5") + .field( + "apb2otp_block3_w5", + &format_args!("{}", self.apb2otp_block3_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block3 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK3_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK3_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk3_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK3_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK3_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK3_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk3_w6.rs b/esp32p4/src/efuse/apb2otp_blk3_w6.rs new file mode 100644 index 0000000000..a82cf853e5 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk3_w6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK3_W6` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK3_W6` reader - Otp block3 word6 data."] +pub type APB2OTP_BLOCK3_W6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block3 word6 data."] + #[inline(always)] + pub fn apb2otp_block3_w6(&self) -> APB2OTP_BLOCK3_W6_R { + APB2OTP_BLOCK3_W6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK3_W6") + .field( + "apb2otp_block3_w6", + &format_args!("{}", self.apb2otp_block3_w6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block3 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK3_W6_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK3_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk3_w6::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK3_W6_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK3_W6 to value 0"] +impl crate::Resettable for APB2OTP_BLK3_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk3_w7.rs b/esp32p4/src/efuse/apb2otp_blk3_w7.rs new file mode 100644 index 0000000000..b0ff9a7221 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk3_w7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK3_W7` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK3_W7` reader - Otp block3 word7 data."] +pub type APB2OTP_BLOCK3_W7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block3 word7 data."] + #[inline(always)] + pub fn apb2otp_block3_w7(&self) -> APB2OTP_BLOCK3_W7_R { + APB2OTP_BLOCK3_W7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK3_W7") + .field( + "apb2otp_block3_w7", + &format_args!("{}", self.apb2otp_block3_w7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block3 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK3_W7_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK3_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk3_w7::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK3_W7_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK3_W7 to value 0"] +impl crate::Resettable for APB2OTP_BLK3_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk3_w8.rs b/esp32p4/src/efuse/apb2otp_blk3_w8.rs new file mode 100644 index 0000000000..e793555b23 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk3_w8.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK3_W8` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK3_W8` reader - Otp block3 word8 data."] +pub type APB2OTP_BLOCK3_W8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block3 word8 data."] + #[inline(always)] + pub fn apb2otp_block3_w8(&self) -> APB2OTP_BLOCK3_W8_R { + APB2OTP_BLOCK3_W8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK3_W8") + .field( + "apb2otp_block3_w8", + &format_args!("{}", self.apb2otp_block3_w8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block3 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK3_W8_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK3_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk3_w8::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK3_W8_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK3_W8 to value 0"] +impl crate::Resettable for APB2OTP_BLK3_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk3_w9.rs b/esp32p4/src/efuse/apb2otp_blk3_w9.rs new file mode 100644 index 0000000000..428bde8606 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk3_w9.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK3_W9` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK3_W9` reader - Otp block3 word9 data."] +pub type APB2OTP_BLOCK3_W9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block3 word9 data."] + #[inline(always)] + pub fn apb2otp_block3_w9(&self) -> APB2OTP_BLOCK3_W9_R { + APB2OTP_BLOCK3_W9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK3_W9") + .field( + "apb2otp_block3_w9", + &format_args!("{}", self.apb2otp_block3_w9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block3 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK3_W9_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK3_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk3_w9::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK3_W9_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK3_W9 to value 0"] +impl crate::Resettable for APB2OTP_BLK3_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk4_w1.rs b/esp32p4/src/efuse/apb2otp_blk4_w1.rs new file mode 100644 index 0000000000..be90f18b45 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk4_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK4_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK4_W1` reader - Otp block4 word1 data."] +pub type APB2OTP_BLOCK4_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block4 word1 data."] + #[inline(always)] + pub fn apb2otp_block4_w1(&self) -> APB2OTP_BLOCK4_W1_R { + APB2OTP_BLOCK4_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK4_W1") + .field( + "apb2otp_block4_w1", + &format_args!("{}", self.apb2otp_block4_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block4 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK4_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK4_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk4_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK4_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK4_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK4_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk4_w10.rs b/esp32p4/src/efuse/apb2otp_blk4_w10.rs new file mode 100644 index 0000000000..38deccabd6 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk4_w10.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK4_W10` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK4_W10` reader - Otp block4 word10 data."] +pub type APB2OTP_BLOCK4_W10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block4 word10 data."] + #[inline(always)] + pub fn apb2otp_block4_w10(&self) -> APB2OTP_BLOCK4_W10_R { + APB2OTP_BLOCK4_W10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK4_W10") + .field( + "apb2otp_block4_w10", + &format_args!("{}", self.apb2otp_block4_w10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block4 data registe10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK4_W10_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK4_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk4_w10::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK4_W10_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK4_W10 to value 0"] +impl crate::Resettable for APB2OTP_BLK4_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk4_w11.rs b/esp32p4/src/efuse/apb2otp_blk4_w11.rs new file mode 100644 index 0000000000..b8e9f43371 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk4_w11.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK4_W11` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK4_W11` reader - Otp block4 word11 data."] +pub type APB2OTP_BLOCK4_W11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block4 word11 data."] + #[inline(always)] + pub fn apb2otp_block4_w11(&self) -> APB2OTP_BLOCK4_W11_R { + APB2OTP_BLOCK4_W11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK4_W11") + .field( + "apb2otp_block4_w11", + &format_args!("{}", self.apb2otp_block4_w11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block4 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK4_W11_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK4_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk4_w11::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK4_W11_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK4_W11 to value 0"] +impl crate::Resettable for APB2OTP_BLK4_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk4_w2.rs b/esp32p4/src/efuse/apb2otp_blk4_w2.rs new file mode 100644 index 0000000000..22df8f540a --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk4_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK4_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK4_W2` reader - Otp block4 word2 data."] +pub type APB2OTP_BLOCK4_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block4 word2 data."] + #[inline(always)] + pub fn apb2otp_block4_w2(&self) -> APB2OTP_BLOCK4_W2_R { + APB2OTP_BLOCK4_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK4_W2") + .field( + "apb2otp_block4_w2", + &format_args!("{}", self.apb2otp_block4_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block4 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK4_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK4_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk4_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK4_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK4_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK4_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk4_w3.rs b/esp32p4/src/efuse/apb2otp_blk4_w3.rs new file mode 100644 index 0000000000..f218848dbc --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk4_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK4_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK4_W3` reader - Otp block4 word3 data."] +pub type APB2OTP_BLOCK4_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block4 word3 data."] + #[inline(always)] + pub fn apb2otp_block4_w3(&self) -> APB2OTP_BLOCK4_W3_R { + APB2OTP_BLOCK4_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK4_W3") + .field( + "apb2otp_block4_w3", + &format_args!("{}", self.apb2otp_block4_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block4 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK4_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK4_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk4_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK4_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK4_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK4_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk4_w4.rs b/esp32p4/src/efuse/apb2otp_blk4_w4.rs new file mode 100644 index 0000000000..6d6e6aebfc --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk4_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK4_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK4_W4` reader - Otp block4 word4 data."] +pub type APB2OTP_BLOCK4_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block4 word4 data."] + #[inline(always)] + pub fn apb2otp_block4_w4(&self) -> APB2OTP_BLOCK4_W4_R { + APB2OTP_BLOCK4_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK4_W4") + .field( + "apb2otp_block4_w4", + &format_args!("{}", self.apb2otp_block4_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block4 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK4_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK4_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk4_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK4_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK4_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK4_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk4_w5.rs b/esp32p4/src/efuse/apb2otp_blk4_w5.rs new file mode 100644 index 0000000000..ab89ad245c --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk4_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK4_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK4_W5` reader - Otp block4 word5 data."] +pub type APB2OTP_BLOCK4_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block4 word5 data."] + #[inline(always)] + pub fn apb2otp_block4_w5(&self) -> APB2OTP_BLOCK4_W5_R { + APB2OTP_BLOCK4_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK4_W5") + .field( + "apb2otp_block4_w5", + &format_args!("{}", self.apb2otp_block4_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block4 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK4_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK4_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk4_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK4_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK4_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK4_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk4_w6.rs b/esp32p4/src/efuse/apb2otp_blk4_w6.rs new file mode 100644 index 0000000000..e3e8b0f7eb --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk4_w6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK4_W6` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK4_W6` reader - Otp block4 word6 data."] +pub type APB2OTP_BLOCK4_W6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block4 word6 data."] + #[inline(always)] + pub fn apb2otp_block4_w6(&self) -> APB2OTP_BLOCK4_W6_R { + APB2OTP_BLOCK4_W6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK4_W6") + .field( + "apb2otp_block4_w6", + &format_args!("{}", self.apb2otp_block4_w6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block4 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK4_W6_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK4_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk4_w6::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK4_W6_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK4_W6 to value 0"] +impl crate::Resettable for APB2OTP_BLK4_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk4_w7.rs b/esp32p4/src/efuse/apb2otp_blk4_w7.rs new file mode 100644 index 0000000000..2eaca5f7db --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk4_w7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK4_W7` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK4_W7` reader - Otp block4 word7 data."] +pub type APB2OTP_BLOCK4_W7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block4 word7 data."] + #[inline(always)] + pub fn apb2otp_block4_w7(&self) -> APB2OTP_BLOCK4_W7_R { + APB2OTP_BLOCK4_W7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK4_W7") + .field( + "apb2otp_block4_w7", + &format_args!("{}", self.apb2otp_block4_w7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block4 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK4_W7_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK4_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk4_w7::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK4_W7_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK4_W7 to value 0"] +impl crate::Resettable for APB2OTP_BLK4_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk4_w8.rs b/esp32p4/src/efuse/apb2otp_blk4_w8.rs new file mode 100644 index 0000000000..aede86f072 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk4_w8.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK4_W8` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK4_W8` reader - Otp block4 word8 data."] +pub type APB2OTP_BLOCK4_W8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block4 word8 data."] + #[inline(always)] + pub fn apb2otp_block4_w8(&self) -> APB2OTP_BLOCK4_W8_R { + APB2OTP_BLOCK4_W8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK4_W8") + .field( + "apb2otp_block4_w8", + &format_args!("{}", self.apb2otp_block4_w8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block4 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK4_W8_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK4_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk4_w8::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK4_W8_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK4_W8 to value 0"] +impl crate::Resettable for APB2OTP_BLK4_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk4_w9.rs b/esp32p4/src/efuse/apb2otp_blk4_w9.rs new file mode 100644 index 0000000000..d3cb3ee5ef --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk4_w9.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK4_W9` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK4_W9` reader - Otp block4 word9 data."] +pub type APB2OTP_BLOCK4_W9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block4 word9 data."] + #[inline(always)] + pub fn apb2otp_block4_w9(&self) -> APB2OTP_BLOCK4_W9_R { + APB2OTP_BLOCK4_W9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK4_W9") + .field( + "apb2otp_block4_w9", + &format_args!("{}", self.apb2otp_block4_w9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block4 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK4_W9_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK4_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk4_w9::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK4_W9_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK4_W9 to value 0"] +impl crate::Resettable for APB2OTP_BLK4_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk5_w1.rs b/esp32p4/src/efuse/apb2otp_blk5_w1.rs new file mode 100644 index 0000000000..f7e590e48c --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk5_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK5_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK5_W1` reader - Otp block5 word1 data."] +pub type APB2OTP_BLOCK5_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block5 word1 data."] + #[inline(always)] + pub fn apb2otp_block5_w1(&self) -> APB2OTP_BLOCK5_W1_R { + APB2OTP_BLOCK5_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK5_W1") + .field( + "apb2otp_block5_w1", + &format_args!("{}", self.apb2otp_block5_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block5 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK5_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK5_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk5_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK5_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK5_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK5_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk5_w10.rs b/esp32p4/src/efuse/apb2otp_blk5_w10.rs new file mode 100644 index 0000000000..1d5ce63012 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk5_w10.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK5_W10` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK5_W10` reader - Otp block5 word10 data."] +pub type APB2OTP_BLOCK5_W10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block5 word10 data."] + #[inline(always)] + pub fn apb2otp_block5_w10(&self) -> APB2OTP_BLOCK5_W10_R { + APB2OTP_BLOCK5_W10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK5_W10") + .field( + "apb2otp_block5_w10", + &format_args!("{}", self.apb2otp_block5_w10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block5 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK5_W10_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK5_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk5_w10::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK5_W10_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK5_W10 to value 0"] +impl crate::Resettable for APB2OTP_BLK5_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk5_w11.rs b/esp32p4/src/efuse/apb2otp_blk5_w11.rs new file mode 100644 index 0000000000..74afa6be18 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk5_w11.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK5_W11` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK5_W11` reader - Otp block5 word11 data."] +pub type APB2OTP_BLOCK5_W11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block5 word11 data."] + #[inline(always)] + pub fn apb2otp_block5_w11(&self) -> APB2OTP_BLOCK5_W11_R { + APB2OTP_BLOCK5_W11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK5_W11") + .field( + "apb2otp_block5_w11", + &format_args!("{}", self.apb2otp_block5_w11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block5 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK5_W11_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK5_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk5_w11::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK5_W11_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK5_W11 to value 0"] +impl crate::Resettable for APB2OTP_BLK5_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk5_w2.rs b/esp32p4/src/efuse/apb2otp_blk5_w2.rs new file mode 100644 index 0000000000..ac168ad39a --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk5_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK5_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK5_W2` reader - Otp block5 word2 data."] +pub type APB2OTP_BLOCK5_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block5 word2 data."] + #[inline(always)] + pub fn apb2otp_block5_w2(&self) -> APB2OTP_BLOCK5_W2_R { + APB2OTP_BLOCK5_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK5_W2") + .field( + "apb2otp_block5_w2", + &format_args!("{}", self.apb2otp_block5_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block5 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK5_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK5_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk5_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK5_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK5_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK5_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk5_w3.rs b/esp32p4/src/efuse/apb2otp_blk5_w3.rs new file mode 100644 index 0000000000..ddd33ddce1 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk5_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK5_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK5_W3` reader - Otp block5 word3 data."] +pub type APB2OTP_BLOCK5_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block5 word3 data."] + #[inline(always)] + pub fn apb2otp_block5_w3(&self) -> APB2OTP_BLOCK5_W3_R { + APB2OTP_BLOCK5_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK5_W3") + .field( + "apb2otp_block5_w3", + &format_args!("{}", self.apb2otp_block5_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block5 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK5_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK5_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk5_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK5_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK5_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK5_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk5_w4.rs b/esp32p4/src/efuse/apb2otp_blk5_w4.rs new file mode 100644 index 0000000000..33fcd08788 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk5_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK5_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK5_W4` reader - Otp block5 word4 data."] +pub type APB2OTP_BLOCK5_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block5 word4 data."] + #[inline(always)] + pub fn apb2otp_block5_w4(&self) -> APB2OTP_BLOCK5_W4_R { + APB2OTP_BLOCK5_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK5_W4") + .field( + "apb2otp_block5_w4", + &format_args!("{}", self.apb2otp_block5_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block5 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK5_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK5_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk5_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK5_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK5_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK5_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk5_w5.rs b/esp32p4/src/efuse/apb2otp_blk5_w5.rs new file mode 100644 index 0000000000..2af15396a6 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk5_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK5_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK5_W5` reader - Otp block5 word5 data."] +pub type APB2OTP_BLOCK5_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block5 word5 data."] + #[inline(always)] + pub fn apb2otp_block5_w5(&self) -> APB2OTP_BLOCK5_W5_R { + APB2OTP_BLOCK5_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK5_W5") + .field( + "apb2otp_block5_w5", + &format_args!("{}", self.apb2otp_block5_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block5 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK5_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK5_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk5_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK5_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK5_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK5_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk5_w6.rs b/esp32p4/src/efuse/apb2otp_blk5_w6.rs new file mode 100644 index 0000000000..912243e60f --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk5_w6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK5_W6` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK5_W6` reader - Otp block5 word6 data."] +pub type APB2OTP_BLOCK5_W6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block5 word6 data."] + #[inline(always)] + pub fn apb2otp_block5_w6(&self) -> APB2OTP_BLOCK5_W6_R { + APB2OTP_BLOCK5_W6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK5_W6") + .field( + "apb2otp_block5_w6", + &format_args!("{}", self.apb2otp_block5_w6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block5 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK5_W6_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK5_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk5_w6::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK5_W6_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK5_W6 to value 0"] +impl crate::Resettable for APB2OTP_BLK5_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk5_w7.rs b/esp32p4/src/efuse/apb2otp_blk5_w7.rs new file mode 100644 index 0000000000..92b143db0a --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk5_w7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK5_W7` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK5_W7` reader - Otp block5 word7 data."] +pub type APB2OTP_BLOCK5_W7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block5 word7 data."] + #[inline(always)] + pub fn apb2otp_block5_w7(&self) -> APB2OTP_BLOCK5_W7_R { + APB2OTP_BLOCK5_W7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK5_W7") + .field( + "apb2otp_block5_w7", + &format_args!("{}", self.apb2otp_block5_w7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block5 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK5_W7_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK5_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk5_w7::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK5_W7_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK5_W7 to value 0"] +impl crate::Resettable for APB2OTP_BLK5_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk5_w8.rs b/esp32p4/src/efuse/apb2otp_blk5_w8.rs new file mode 100644 index 0000000000..57f517b4b7 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk5_w8.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK5_W8` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK5_W8` reader - Otp block5 word8 data."] +pub type APB2OTP_BLOCK5_W8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block5 word8 data."] + #[inline(always)] + pub fn apb2otp_block5_w8(&self) -> APB2OTP_BLOCK5_W8_R { + APB2OTP_BLOCK5_W8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK5_W8") + .field( + "apb2otp_block5_w8", + &format_args!("{}", self.apb2otp_block5_w8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block5 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK5_W8_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK5_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk5_w8::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK5_W8_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK5_W8 to value 0"] +impl crate::Resettable for APB2OTP_BLK5_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk5_w9.rs b/esp32p4/src/efuse/apb2otp_blk5_w9.rs new file mode 100644 index 0000000000..f847b064f5 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk5_w9.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK5_W9` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK5_W9` reader - Otp block5 word9 data."] +pub type APB2OTP_BLOCK5_W9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block5 word9 data."] + #[inline(always)] + pub fn apb2otp_block5_w9(&self) -> APB2OTP_BLOCK5_W9_R { + APB2OTP_BLOCK5_W9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK5_W9") + .field( + "apb2otp_block5_w9", + &format_args!("{}", self.apb2otp_block5_w9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block5 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK5_W9_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK5_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk5_w9::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK5_W9_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK5_W9 to value 0"] +impl crate::Resettable for APB2OTP_BLK5_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk6_w1.rs b/esp32p4/src/efuse/apb2otp_blk6_w1.rs new file mode 100644 index 0000000000..3dac741a91 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk6_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK6_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK6_W1` reader - Otp block6 word1 data."] +pub type APB2OTP_BLOCK6_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block6 word1 data."] + #[inline(always)] + pub fn apb2otp_block6_w1(&self) -> APB2OTP_BLOCK6_W1_R { + APB2OTP_BLOCK6_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK6_W1") + .field( + "apb2otp_block6_w1", + &format_args!("{}", self.apb2otp_block6_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block6 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK6_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK6_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk6_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK6_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK6_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK6_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk6_w10.rs b/esp32p4/src/efuse/apb2otp_blk6_w10.rs new file mode 100644 index 0000000000..0e876f24fd --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk6_w10.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK6_W10` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK6_W10` reader - Otp block6 word10 data."] +pub type APB2OTP_BLOCK6_W10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block6 word10 data."] + #[inline(always)] + pub fn apb2otp_block6_w10(&self) -> APB2OTP_BLOCK6_W10_R { + APB2OTP_BLOCK6_W10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK6_W10") + .field( + "apb2otp_block6_w10", + &format_args!("{}", self.apb2otp_block6_w10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block6 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK6_W10_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK6_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk6_w10::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK6_W10_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK6_W10 to value 0"] +impl crate::Resettable for APB2OTP_BLK6_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk6_w11.rs b/esp32p4/src/efuse/apb2otp_blk6_w11.rs new file mode 100644 index 0000000000..52408677ff --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk6_w11.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK6_W11` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK6_W11` reader - Otp block6 word11 data."] +pub type APB2OTP_BLOCK6_W11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block6 word11 data."] + #[inline(always)] + pub fn apb2otp_block6_w11(&self) -> APB2OTP_BLOCK6_W11_R { + APB2OTP_BLOCK6_W11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK6_W11") + .field( + "apb2otp_block6_w11", + &format_args!("{}", self.apb2otp_block6_w11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block6 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK6_W11_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK6_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk6_w11::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK6_W11_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK6_W11 to value 0"] +impl crate::Resettable for APB2OTP_BLK6_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk6_w2.rs b/esp32p4/src/efuse/apb2otp_blk6_w2.rs new file mode 100644 index 0000000000..3962c83029 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk6_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK6_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK6_W2` reader - Otp block6 word2 data."] +pub type APB2OTP_BLOCK6_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block6 word2 data."] + #[inline(always)] + pub fn apb2otp_block6_w2(&self) -> APB2OTP_BLOCK6_W2_R { + APB2OTP_BLOCK6_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK6_W2") + .field( + "apb2otp_block6_w2", + &format_args!("{}", self.apb2otp_block6_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block6 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK6_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK6_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk6_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK6_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK6_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK6_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk6_w3.rs b/esp32p4/src/efuse/apb2otp_blk6_w3.rs new file mode 100644 index 0000000000..9a70f3f652 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk6_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK6_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK6_W3` reader - Otp block6 word3 data."] +pub type APB2OTP_BLOCK6_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block6 word3 data."] + #[inline(always)] + pub fn apb2otp_block6_w3(&self) -> APB2OTP_BLOCK6_W3_R { + APB2OTP_BLOCK6_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK6_W3") + .field( + "apb2otp_block6_w3", + &format_args!("{}", self.apb2otp_block6_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block6 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK6_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK6_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk6_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK6_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK6_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK6_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk6_w4.rs b/esp32p4/src/efuse/apb2otp_blk6_w4.rs new file mode 100644 index 0000000000..46334afe5e --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk6_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK6_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK6_W4` reader - Otp block6 word4 data."] +pub type APB2OTP_BLOCK6_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block6 word4 data."] + #[inline(always)] + pub fn apb2otp_block6_w4(&self) -> APB2OTP_BLOCK6_W4_R { + APB2OTP_BLOCK6_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK6_W4") + .field( + "apb2otp_block6_w4", + &format_args!("{}", self.apb2otp_block6_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block6 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK6_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK6_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk6_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK6_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK6_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK6_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk6_w5.rs b/esp32p4/src/efuse/apb2otp_blk6_w5.rs new file mode 100644 index 0000000000..c437737401 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk6_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK6_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK6_W5` reader - Otp block6 word5 data."] +pub type APB2OTP_BLOCK6_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block6 word5 data."] + #[inline(always)] + pub fn apb2otp_block6_w5(&self) -> APB2OTP_BLOCK6_W5_R { + APB2OTP_BLOCK6_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK6_W5") + .field( + "apb2otp_block6_w5", + &format_args!("{}", self.apb2otp_block6_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block6 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK6_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK6_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk6_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK6_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK6_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK6_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk6_w6.rs b/esp32p4/src/efuse/apb2otp_blk6_w6.rs new file mode 100644 index 0000000000..44d9af31a4 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk6_w6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK6_W6` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK6_W6` reader - Otp block6 word6 data."] +pub type APB2OTP_BLOCK6_W6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block6 word6 data."] + #[inline(always)] + pub fn apb2otp_block6_w6(&self) -> APB2OTP_BLOCK6_W6_R { + APB2OTP_BLOCK6_W6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK6_W6") + .field( + "apb2otp_block6_w6", + &format_args!("{}", self.apb2otp_block6_w6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block6 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK6_W6_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK6_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk6_w6::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK6_W6_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK6_W6 to value 0"] +impl crate::Resettable for APB2OTP_BLK6_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk6_w7.rs b/esp32p4/src/efuse/apb2otp_blk6_w7.rs new file mode 100644 index 0000000000..8233947bfc --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk6_w7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK6_W7` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK6_W7` reader - Otp block6 word7 data."] +pub type APB2OTP_BLOCK6_W7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block6 word7 data."] + #[inline(always)] + pub fn apb2otp_block6_w7(&self) -> APB2OTP_BLOCK6_W7_R { + APB2OTP_BLOCK6_W7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK6_W7") + .field( + "apb2otp_block6_w7", + &format_args!("{}", self.apb2otp_block6_w7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block6 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK6_W7_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK6_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk6_w7::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK6_W7_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK6_W7 to value 0"] +impl crate::Resettable for APB2OTP_BLK6_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk6_w8.rs b/esp32p4/src/efuse/apb2otp_blk6_w8.rs new file mode 100644 index 0000000000..cfc379782d --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk6_w8.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK6_W8` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK6_W8` reader - Otp block6 word8 data."] +pub type APB2OTP_BLOCK6_W8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block6 word8 data."] + #[inline(always)] + pub fn apb2otp_block6_w8(&self) -> APB2OTP_BLOCK6_W8_R { + APB2OTP_BLOCK6_W8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK6_W8") + .field( + "apb2otp_block6_w8", + &format_args!("{}", self.apb2otp_block6_w8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block6 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK6_W8_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK6_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk6_w8::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK6_W8_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK6_W8 to value 0"] +impl crate::Resettable for APB2OTP_BLK6_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk6_w9.rs b/esp32p4/src/efuse/apb2otp_blk6_w9.rs new file mode 100644 index 0000000000..09b542ee0b --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk6_w9.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK6_W9` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK6_W9` reader - Otp block6 word9 data."] +pub type APB2OTP_BLOCK6_W9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block6 word9 data."] + #[inline(always)] + pub fn apb2otp_block6_w9(&self) -> APB2OTP_BLOCK6_W9_R { + APB2OTP_BLOCK6_W9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK6_W9") + .field( + "apb2otp_block6_w9", + &format_args!("{}", self.apb2otp_block6_w9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block6 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK6_W9_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK6_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk6_w9::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK6_W9_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK6_W9 to value 0"] +impl crate::Resettable for APB2OTP_BLK6_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk7_w1.rs b/esp32p4/src/efuse/apb2otp_blk7_w1.rs new file mode 100644 index 0000000000..061fd19dea --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk7_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK7_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK7_W1` reader - Otp block7 word1 data."] +pub type APB2OTP_BLOCK7_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block7 word1 data."] + #[inline(always)] + pub fn apb2otp_block7_w1(&self) -> APB2OTP_BLOCK7_W1_R { + APB2OTP_BLOCK7_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK7_W1") + .field( + "apb2otp_block7_w1", + &format_args!("{}", self.apb2otp_block7_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block7 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK7_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK7_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk7_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK7_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK7_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK7_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk7_w10.rs b/esp32p4/src/efuse/apb2otp_blk7_w10.rs new file mode 100644 index 0000000000..6b4a55922f --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk7_w10.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK7_W10` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK7_W10` reader - Otp block7 word10 data."] +pub type APB2OTP_BLOCK7_W10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block7 word10 data."] + #[inline(always)] + pub fn apb2otp_block7_w10(&self) -> APB2OTP_BLOCK7_W10_R { + APB2OTP_BLOCK7_W10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK7_W10") + .field( + "apb2otp_block7_w10", + &format_args!("{}", self.apb2otp_block7_w10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block7 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK7_W10_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK7_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk7_w10::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK7_W10_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK7_W10 to value 0"] +impl crate::Resettable for APB2OTP_BLK7_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk7_w11.rs b/esp32p4/src/efuse/apb2otp_blk7_w11.rs new file mode 100644 index 0000000000..55732564a6 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk7_w11.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK7_W11` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK7_W11` reader - Otp block7 word11 data."] +pub type APB2OTP_BLOCK7_W11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block7 word11 data."] + #[inline(always)] + pub fn apb2otp_block7_w11(&self) -> APB2OTP_BLOCK7_W11_R { + APB2OTP_BLOCK7_W11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK7_W11") + .field( + "apb2otp_block7_w11", + &format_args!("{}", self.apb2otp_block7_w11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block7 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK7_W11_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK7_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk7_w11::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK7_W11_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK7_W11 to value 0"] +impl crate::Resettable for APB2OTP_BLK7_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk7_w2.rs b/esp32p4/src/efuse/apb2otp_blk7_w2.rs new file mode 100644 index 0000000000..9f9fe6c2e0 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk7_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK7_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK7_W2` reader - Otp block7 word2 data."] +pub type APB2OTP_BLOCK7_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block7 word2 data."] + #[inline(always)] + pub fn apb2otp_block7_w2(&self) -> APB2OTP_BLOCK7_W2_R { + APB2OTP_BLOCK7_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK7_W2") + .field( + "apb2otp_block7_w2", + &format_args!("{}", self.apb2otp_block7_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block7 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK7_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK7_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk7_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK7_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK7_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK7_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk7_w3.rs b/esp32p4/src/efuse/apb2otp_blk7_w3.rs new file mode 100644 index 0000000000..71f1425cab --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk7_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK7_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK7_W3` reader - Otp block7 word3 data."] +pub type APB2OTP_BLOCK7_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block7 word3 data."] + #[inline(always)] + pub fn apb2otp_block7_w3(&self) -> APB2OTP_BLOCK7_W3_R { + APB2OTP_BLOCK7_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK7_W3") + .field( + "apb2otp_block7_w3", + &format_args!("{}", self.apb2otp_block7_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block7 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK7_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK7_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk7_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK7_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK7_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK7_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk7_w4.rs b/esp32p4/src/efuse/apb2otp_blk7_w4.rs new file mode 100644 index 0000000000..28b61c87b5 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk7_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK7_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK7_W4` reader - Otp block7 word4 data."] +pub type APB2OTP_BLOCK7_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block7 word4 data."] + #[inline(always)] + pub fn apb2otp_block7_w4(&self) -> APB2OTP_BLOCK7_W4_R { + APB2OTP_BLOCK7_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK7_W4") + .field( + "apb2otp_block7_w4", + &format_args!("{}", self.apb2otp_block7_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block7 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK7_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK7_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk7_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK7_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK7_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK7_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk7_w5.rs b/esp32p4/src/efuse/apb2otp_blk7_w5.rs new file mode 100644 index 0000000000..959bdc9cf0 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk7_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK7_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK7_W5` reader - Otp block7 word5 data."] +pub type APB2OTP_BLOCK7_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block7 word5 data."] + #[inline(always)] + pub fn apb2otp_block7_w5(&self) -> APB2OTP_BLOCK7_W5_R { + APB2OTP_BLOCK7_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK7_W5") + .field( + "apb2otp_block7_w5", + &format_args!("{}", self.apb2otp_block7_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block7 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK7_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK7_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk7_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK7_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK7_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK7_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk7_w6.rs b/esp32p4/src/efuse/apb2otp_blk7_w6.rs new file mode 100644 index 0000000000..765ea96ebf --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk7_w6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK7_W6` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK7_W6` reader - Otp block7 word6 data."] +pub type APB2OTP_BLOCK7_W6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block7 word6 data."] + #[inline(always)] + pub fn apb2otp_block7_w6(&self) -> APB2OTP_BLOCK7_W6_R { + APB2OTP_BLOCK7_W6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK7_W6") + .field( + "apb2otp_block7_w6", + &format_args!("{}", self.apb2otp_block7_w6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block7 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK7_W6_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK7_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk7_w6::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK7_W6_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK7_W6 to value 0"] +impl crate::Resettable for APB2OTP_BLK7_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk7_w7.rs b/esp32p4/src/efuse/apb2otp_blk7_w7.rs new file mode 100644 index 0000000000..b5ed962799 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk7_w7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK7_W7` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK7_W7` reader - Otp block7 word7 data."] +pub type APB2OTP_BLOCK7_W7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block7 word7 data."] + #[inline(always)] + pub fn apb2otp_block7_w7(&self) -> APB2OTP_BLOCK7_W7_R { + APB2OTP_BLOCK7_W7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK7_W7") + .field( + "apb2otp_block7_w7", + &format_args!("{}", self.apb2otp_block7_w7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block7 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK7_W7_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK7_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk7_w7::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK7_W7_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK7_W7 to value 0"] +impl crate::Resettable for APB2OTP_BLK7_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk7_w8.rs b/esp32p4/src/efuse/apb2otp_blk7_w8.rs new file mode 100644 index 0000000000..21b9cbd472 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk7_w8.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK7_W8` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK7_W8` reader - Otp block7 word8 data."] +pub type APB2OTP_BLOCK7_W8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block7 word8 data."] + #[inline(always)] + pub fn apb2otp_block7_w8(&self) -> APB2OTP_BLOCK7_W8_R { + APB2OTP_BLOCK7_W8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK7_W8") + .field( + "apb2otp_block7_w8", + &format_args!("{}", self.apb2otp_block7_w8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block7 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK7_W8_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK7_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk7_w8::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK7_W8_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK7_W8 to value 0"] +impl crate::Resettable for APB2OTP_BLK7_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk7_w9.rs b/esp32p4/src/efuse/apb2otp_blk7_w9.rs new file mode 100644 index 0000000000..f8de50170f --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk7_w9.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK7_W9` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK7_W9` reader - Otp block7 word9 data."] +pub type APB2OTP_BLOCK7_W9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block7 word9 data."] + #[inline(always)] + pub fn apb2otp_block7_w9(&self) -> APB2OTP_BLOCK7_W9_R { + APB2OTP_BLOCK7_W9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK7_W9") + .field( + "apb2otp_block7_w9", + &format_args!("{}", self.apb2otp_block7_w9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block7 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK7_W9_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK7_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk7_w9::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK7_W9_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK7_W9 to value 0"] +impl crate::Resettable for APB2OTP_BLK7_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk8_w1.rs b/esp32p4/src/efuse/apb2otp_blk8_w1.rs new file mode 100644 index 0000000000..74975d8e78 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk8_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK8_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK8_W1` reader - Otp block8 word1 data."] +pub type APB2OTP_BLOCK8_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block8 word1 data."] + #[inline(always)] + pub fn apb2otp_block8_w1(&self) -> APB2OTP_BLOCK8_W1_R { + APB2OTP_BLOCK8_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK8_W1") + .field( + "apb2otp_block8_w1", + &format_args!("{}", self.apb2otp_block8_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block8 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK8_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK8_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk8_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK8_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK8_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK8_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk8_w10.rs b/esp32p4/src/efuse/apb2otp_blk8_w10.rs new file mode 100644 index 0000000000..ce747b777c --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk8_w10.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK8_W10` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK8_W10` reader - Otp block8 word10 data."] +pub type APB2OTP_BLOCK8_W10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block8 word10 data."] + #[inline(always)] + pub fn apb2otp_block8_w10(&self) -> APB2OTP_BLOCK8_W10_R { + APB2OTP_BLOCK8_W10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK8_W10") + .field( + "apb2otp_block8_w10", + &format_args!("{}", self.apb2otp_block8_w10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block8 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK8_W10_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK8_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk8_w10::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK8_W10_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK8_W10 to value 0"] +impl crate::Resettable for APB2OTP_BLK8_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk8_w11.rs b/esp32p4/src/efuse/apb2otp_blk8_w11.rs new file mode 100644 index 0000000000..8b85c3ab8b --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk8_w11.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK8_W11` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK8_W11` reader - Otp block8 word11 data."] +pub type APB2OTP_BLOCK8_W11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block8 word11 data."] + #[inline(always)] + pub fn apb2otp_block8_w11(&self) -> APB2OTP_BLOCK8_W11_R { + APB2OTP_BLOCK8_W11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK8_W11") + .field( + "apb2otp_block8_w11", + &format_args!("{}", self.apb2otp_block8_w11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block8 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK8_W11_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK8_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk8_w11::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK8_W11_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK8_W11 to value 0"] +impl crate::Resettable for APB2OTP_BLK8_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk8_w2.rs b/esp32p4/src/efuse/apb2otp_blk8_w2.rs new file mode 100644 index 0000000000..c9da4bd797 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk8_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK8_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK8_W2` reader - Otp block8 word2 data."] +pub type APB2OTP_BLOCK8_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block8 word2 data."] + #[inline(always)] + pub fn apb2otp_block8_w2(&self) -> APB2OTP_BLOCK8_W2_R { + APB2OTP_BLOCK8_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK8_W2") + .field( + "apb2otp_block8_w2", + &format_args!("{}", self.apb2otp_block8_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block8 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK8_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK8_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk8_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK8_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK8_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK8_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk8_w3.rs b/esp32p4/src/efuse/apb2otp_blk8_w3.rs new file mode 100644 index 0000000000..9fc1bf64a0 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk8_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK8_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK8_W3` reader - Otp block8 word3 data."] +pub type APB2OTP_BLOCK8_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block8 word3 data."] + #[inline(always)] + pub fn apb2otp_block8_w3(&self) -> APB2OTP_BLOCK8_W3_R { + APB2OTP_BLOCK8_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK8_W3") + .field( + "apb2otp_block8_w3", + &format_args!("{}", self.apb2otp_block8_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block8 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK8_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK8_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk8_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK8_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK8_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK8_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk8_w4.rs b/esp32p4/src/efuse/apb2otp_blk8_w4.rs new file mode 100644 index 0000000000..50d7c3bd72 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk8_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK8_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK8_W4` reader - Otp block8 word4 data."] +pub type APB2OTP_BLOCK8_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block8 word4 data."] + #[inline(always)] + pub fn apb2otp_block8_w4(&self) -> APB2OTP_BLOCK8_W4_R { + APB2OTP_BLOCK8_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK8_W4") + .field( + "apb2otp_block8_w4", + &format_args!("{}", self.apb2otp_block8_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block8 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK8_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK8_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk8_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK8_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK8_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK8_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk8_w5.rs b/esp32p4/src/efuse/apb2otp_blk8_w5.rs new file mode 100644 index 0000000000..8d3a36beb5 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk8_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK8_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK8_W5` reader - Otp block8 word5 data."] +pub type APB2OTP_BLOCK8_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block8 word5 data."] + #[inline(always)] + pub fn apb2otp_block8_w5(&self) -> APB2OTP_BLOCK8_W5_R { + APB2OTP_BLOCK8_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK8_W5") + .field( + "apb2otp_block8_w5", + &format_args!("{}", self.apb2otp_block8_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block8 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK8_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK8_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk8_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK8_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK8_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK8_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk8_w6.rs b/esp32p4/src/efuse/apb2otp_blk8_w6.rs new file mode 100644 index 0000000000..2bd71c3598 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk8_w6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK8_W6` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK8_W6` reader - Otp block8 word6 data."] +pub type APB2OTP_BLOCK8_W6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block8 word6 data."] + #[inline(always)] + pub fn apb2otp_block8_w6(&self) -> APB2OTP_BLOCK8_W6_R { + APB2OTP_BLOCK8_W6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK8_W6") + .field( + "apb2otp_block8_w6", + &format_args!("{}", self.apb2otp_block8_w6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block8 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK8_W6_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK8_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk8_w6::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK8_W6_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK8_W6 to value 0"] +impl crate::Resettable for APB2OTP_BLK8_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk8_w7.rs b/esp32p4/src/efuse/apb2otp_blk8_w7.rs new file mode 100644 index 0000000000..0ce39a01e2 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk8_w7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK8_W7` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK8_W7` reader - Otp block8 word7 data."] +pub type APB2OTP_BLOCK8_W7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block8 word7 data."] + #[inline(always)] + pub fn apb2otp_block8_w7(&self) -> APB2OTP_BLOCK8_W7_R { + APB2OTP_BLOCK8_W7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK8_W7") + .field( + "apb2otp_block8_w7", + &format_args!("{}", self.apb2otp_block8_w7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block8 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK8_W7_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK8_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk8_w7::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK8_W7_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK8_W7 to value 0"] +impl crate::Resettable for APB2OTP_BLK8_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk8_w8.rs b/esp32p4/src/efuse/apb2otp_blk8_w8.rs new file mode 100644 index 0000000000..78a0ba1605 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk8_w8.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK8_W8` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK8_W8` reader - Otp block8 word8 data."] +pub type APB2OTP_BLOCK8_W8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block8 word8 data."] + #[inline(always)] + pub fn apb2otp_block8_w8(&self) -> APB2OTP_BLOCK8_W8_R { + APB2OTP_BLOCK8_W8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK8_W8") + .field( + "apb2otp_block8_w8", + &format_args!("{}", self.apb2otp_block8_w8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block8 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK8_W8_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK8_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk8_w8::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK8_W8_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK8_W8 to value 0"] +impl crate::Resettable for APB2OTP_BLK8_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk8_w9.rs b/esp32p4/src/efuse/apb2otp_blk8_w9.rs new file mode 100644 index 0000000000..967364b0db --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk8_w9.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK8_W9` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK8_W9` reader - Otp block8 word9 data."] +pub type APB2OTP_BLOCK8_W9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block8 word9 data."] + #[inline(always)] + pub fn apb2otp_block8_w9(&self) -> APB2OTP_BLOCK8_W9_R { + APB2OTP_BLOCK8_W9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK8_W9") + .field( + "apb2otp_block8_w9", + &format_args!("{}", self.apb2otp_block8_w9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block8 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK8_W9_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK8_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk8_w9::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK8_W9_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK8_W9 to value 0"] +impl crate::Resettable for APB2OTP_BLK8_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk9_w1.rs b/esp32p4/src/efuse/apb2otp_blk9_w1.rs new file mode 100644 index 0000000000..fdab770db2 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk9_w1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK9_W1` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK9_W1` reader - Otp block9 word1 data."] +pub type APB2OTP_BLOCK9_W1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block9 word1 data."] + #[inline(always)] + pub fn apb2otp_block9_w1(&self) -> APB2OTP_BLOCK9_W1_R { + APB2OTP_BLOCK9_W1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK9_W1") + .field( + "apb2otp_block9_w1", + &format_args!("{}", self.apb2otp_block9_w1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block9 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK9_W1_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK9_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk9_w1::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK9_W1_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK9_W1 to value 0"] +impl crate::Resettable for APB2OTP_BLK9_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk9_w10.rs b/esp32p4/src/efuse/apb2otp_blk9_w10.rs new file mode 100644 index 0000000000..5dcd16b1c5 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk9_w10.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK9_W10` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK9_W10` reader - Otp block9 word10 data."] +pub type APB2OTP_BLOCK9_W10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block9 word10 data."] + #[inline(always)] + pub fn apb2otp_block9_w10(&self) -> APB2OTP_BLOCK9_W10_R { + APB2OTP_BLOCK9_W10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK9_W10") + .field( + "apb2otp_block9_w10", + &format_args!("{}", self.apb2otp_block9_w10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block9 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK9_W10_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK9_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk9_w10::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK9_W10_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK9_W10 to value 0"] +impl crate::Resettable for APB2OTP_BLK9_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk9_w11.rs b/esp32p4/src/efuse/apb2otp_blk9_w11.rs new file mode 100644 index 0000000000..6aa7546539 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk9_w11.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK9_W11` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK9_W11` reader - Otp block9 word11 data."] +pub type APB2OTP_BLOCK9_W11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block9 word11 data."] + #[inline(always)] + pub fn apb2otp_block9_w11(&self) -> APB2OTP_BLOCK9_W11_R { + APB2OTP_BLOCK9_W11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK9_W11") + .field( + "apb2otp_block9_w11", + &format_args!("{}", self.apb2otp_block9_w11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block9 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK9_W11_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK9_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk9_w11::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK9_W11_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK9_W11 to value 0"] +impl crate::Resettable for APB2OTP_BLK9_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk9_w2.rs b/esp32p4/src/efuse/apb2otp_blk9_w2.rs new file mode 100644 index 0000000000..987b2d464e --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk9_w2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK9_W2` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK9_W2` reader - Otp block9 word2 data."] +pub type APB2OTP_BLOCK9_W2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block9 word2 data."] + #[inline(always)] + pub fn apb2otp_block9_w2(&self) -> APB2OTP_BLOCK9_W2_R { + APB2OTP_BLOCK9_W2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK9_W2") + .field( + "apb2otp_block9_w2", + &format_args!("{}", self.apb2otp_block9_w2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block9 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK9_W2_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK9_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk9_w2::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK9_W2_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK9_W2 to value 0"] +impl crate::Resettable for APB2OTP_BLK9_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk9_w3.rs b/esp32p4/src/efuse/apb2otp_blk9_w3.rs new file mode 100644 index 0000000000..4abb7d33f2 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk9_w3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK9_W3` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK9_W3` reader - Otp block9 word3 data."] +pub type APB2OTP_BLOCK9_W3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block9 word3 data."] + #[inline(always)] + pub fn apb2otp_block9_w3(&self) -> APB2OTP_BLOCK9_W3_R { + APB2OTP_BLOCK9_W3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK9_W3") + .field( + "apb2otp_block9_w3", + &format_args!("{}", self.apb2otp_block9_w3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block9 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK9_W3_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK9_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk9_w3::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK9_W3_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK9_W3 to value 0"] +impl crate::Resettable for APB2OTP_BLK9_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk9_w4.rs b/esp32p4/src/efuse/apb2otp_blk9_w4.rs new file mode 100644 index 0000000000..ceb233eef2 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk9_w4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK9_W4` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK9_W4` reader - Otp block9 word4 data."] +pub type APB2OTP_BLOCK9_W4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block9 word4 data."] + #[inline(always)] + pub fn apb2otp_block9_w4(&self) -> APB2OTP_BLOCK9_W4_R { + APB2OTP_BLOCK9_W4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK9_W4") + .field( + "apb2otp_block9_w4", + &format_args!("{}", self.apb2otp_block9_w4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block9 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK9_W4_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK9_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk9_w4::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK9_W4_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK9_W4 to value 0"] +impl crate::Resettable for APB2OTP_BLK9_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk9_w5.rs b/esp32p4/src/efuse/apb2otp_blk9_w5.rs new file mode 100644 index 0000000000..31e11ae282 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk9_w5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK9_W5` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK9_W5` reader - Otp block9 word5 data."] +pub type APB2OTP_BLOCK9_W5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block9 word5 data."] + #[inline(always)] + pub fn apb2otp_block9_w5(&self) -> APB2OTP_BLOCK9_W5_R { + APB2OTP_BLOCK9_W5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK9_W5") + .field( + "apb2otp_block9_w5", + &format_args!("{}", self.apb2otp_block9_w5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block9 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK9_W5_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK9_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk9_w5::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK9_W5_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK9_W5 to value 0"] +impl crate::Resettable for APB2OTP_BLK9_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk9_w6.rs b/esp32p4/src/efuse/apb2otp_blk9_w6.rs new file mode 100644 index 0000000000..a4d6f0d8f3 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk9_w6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK9_W6` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK9_W6` reader - Otp block9 word6 data."] +pub type APB2OTP_BLOCK9_W6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block9 word6 data."] + #[inline(always)] + pub fn apb2otp_block9_w6(&self) -> APB2OTP_BLOCK9_W6_R { + APB2OTP_BLOCK9_W6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK9_W6") + .field( + "apb2otp_block9_w6", + &format_args!("{}", self.apb2otp_block9_w6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block9 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK9_W6_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK9_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk9_w6::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK9_W6_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK9_W6 to value 0"] +impl crate::Resettable for APB2OTP_BLK9_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk9_w7.rs b/esp32p4/src/efuse/apb2otp_blk9_w7.rs new file mode 100644 index 0000000000..b88d16e9d1 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk9_w7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK9_W7` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK9_W7` reader - Otp block9 word7 data."] +pub type APB2OTP_BLOCK9_W7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block9 word7 data."] + #[inline(always)] + pub fn apb2otp_block9_w7(&self) -> APB2OTP_BLOCK9_W7_R { + APB2OTP_BLOCK9_W7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK9_W7") + .field( + "apb2otp_block9_w7", + &format_args!("{}", self.apb2otp_block9_w7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block9 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK9_W7_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK9_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk9_w7::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK9_W7_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK9_W7 to value 0"] +impl crate::Resettable for APB2OTP_BLK9_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk9_w8.rs b/esp32p4/src/efuse/apb2otp_blk9_w8.rs new file mode 100644 index 0000000000..f4fc61f93a --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk9_w8.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK9_W8` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK9_W8` reader - Otp block9 word8 data."] +pub type APB2OTP_BLOCK9_W8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block9 word8 data."] + #[inline(always)] + pub fn apb2otp_block9_w8(&self) -> APB2OTP_BLOCK9_W8_R { + APB2OTP_BLOCK9_W8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK9_W8") + .field( + "apb2otp_block9_w8", + &format_args!("{}", self.apb2otp_block9_w8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block9 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK9_W8_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK9_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk9_w8::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK9_W8_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK9_W8 to value 0"] +impl crate::Resettable for APB2OTP_BLK9_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_blk9_w9.rs b/esp32p4/src/efuse/apb2otp_blk9_w9.rs new file mode 100644 index 0000000000..ff24d20dfe --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_blk9_w9.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_BLK9_W9` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK9_W9` reader - Otp block9 word9 data."] +pub type APB2OTP_BLOCK9_W9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block9 word9 data."] + #[inline(always)] + pub fn apb2otp_block9_w9(&self) -> APB2OTP_BLOCK9_W9_R { + APB2OTP_BLOCK9_W9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_BLK9_W9") + .field( + "apb2otp_block9_w9", + &format_args!("{}", self.apb2otp_block9_w9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block9 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_BLK9_W9_SPEC; +impl crate::RegisterSpec for APB2OTP_BLK9_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_blk9_w9::R`](R) reader structure"] +impl crate::Readable for APB2OTP_BLK9_W9_SPEC {} +#[doc = "`reset()` method sets APB2OTP_BLK9_W9 to value 0"] +impl crate::Resettable for APB2OTP_BLK9_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_en.rs b/esp32p4/src/efuse/apb2otp_en.rs new file mode 100644 index 0000000000..d18dc969bf --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_en.rs @@ -0,0 +1,66 @@ +#[doc = "Register `APB2OTP_EN` reader"] +pub type R = crate::R; +#[doc = "Register `APB2OTP_EN` writer"] +pub type W = crate::W; +#[doc = "Field `APB2OTP_APB2OTP_EN` reader - Apb2otp mode enable signal."] +pub type APB2OTP_APB2OTP_EN_R = crate::BitReader; +#[doc = "Field `APB2OTP_APB2OTP_EN` writer - Apb2otp mode enable signal."] +pub type APB2OTP_APB2OTP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Apb2otp mode enable signal."] + #[inline(always)] + pub fn apb2otp_apb2otp_en(&self) -> APB2OTP_APB2OTP_EN_R { + APB2OTP_APB2OTP_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_EN") + .field( + "apb2otp_apb2otp_en", + &format_args!("{}", self.apb2otp_apb2otp_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Apb2otp mode enable signal."] + #[inline(always)] + #[must_use] + pub fn apb2otp_apb2otp_en(&mut self) -> APB2OTP_APB2OTP_EN_W { + APB2OTP_APB2OTP_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "eFuse apb2otp enable configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb2otp_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_EN_SPEC; +impl crate::RegisterSpec for APB2OTP_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_en::R`](R) reader structure"] +impl crate::Readable for APB2OTP_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`apb2otp_en::W`](W) writer structure"] +impl crate::Writable for APB2OTP_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets APB2OTP_EN to value 0"] +impl crate::Resettable for APB2OTP_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/apb2otp_wr_dis.rs b/esp32p4/src/efuse/apb2otp_wr_dis.rs new file mode 100644 index 0000000000..3d4287bc37 --- /dev/null +++ b/esp32p4/src/efuse/apb2otp_wr_dis.rs @@ -0,0 +1,39 @@ +#[doc = "Register `APB2OTP_WR_DIS` reader"] +pub type R = crate::R; +#[doc = "Field `APB2OTP_BLOCK0_WR_DIS` reader - Otp block0 write disable data."] +pub type APB2OTP_BLOCK0_WR_DIS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Otp block0 write disable data."] + #[inline(always)] + pub fn apb2otp_block0_wr_dis(&self) -> APB2OTP_BLOCK0_WR_DIS_R { + APB2OTP_BLOCK0_WR_DIS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB2OTP_WR_DIS") + .field( + "apb2otp_block0_wr_dis", + &format_args!("{}", self.apb2otp_block0_wr_dis().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse apb2otp block0 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_wr_dis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB2OTP_WR_DIS_SPEC; +impl crate::RegisterSpec for APB2OTP_WR_DIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb2otp_wr_dis::R`](R) reader structure"] +impl crate::Readable for APB2OTP_WR_DIS_SPEC {} +#[doc = "`reset()` method sets APB2OTP_WR_DIS to value 0"] +impl crate::Resettable for APB2OTP_WR_DIS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/clk.rs b/esp32p4/src/efuse/clk.rs new file mode 100644 index 0000000000..8a3ed861d0 --- /dev/null +++ b/esp32p4/src/efuse/clk.rs @@ -0,0 +1,120 @@ +#[doc = "Register `CLK` reader"] +pub type R = crate::R; +#[doc = "Register `CLK` writer"] +pub type W = crate::W; +#[doc = "Field `MEM_FORCE_PD` reader - Set this bit to force eFuse SRAM into power-saving mode."] +pub type MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PD` writer - Set this bit to force eFuse SRAM into power-saving mode."] +pub type MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_CLK_FORCE_ON` reader - Set this bit and force to activate clock signal of eFuse SRAM."] +pub type MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `MEM_CLK_FORCE_ON` writer - Set this bit and force to activate clock signal of eFuse SRAM."] +pub type MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_FORCE_PU` reader - Set this bit to force eFuse SRAM into working mode."] +pub type MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PU` writer - Set this bit to force eFuse SRAM into working mode."] +pub type MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN` reader - Set this bit to force enable eFuse register configuration clock signal."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Set this bit to force enable eFuse register configuration clock signal."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to force eFuse SRAM into power-saving mode."] + #[inline(always)] + pub fn mem_force_pd(&self) -> MEM_FORCE_PD_R { + MEM_FORCE_PD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit and force to activate clock signal of eFuse SRAM."] + #[inline(always)] + pub fn mem_clk_force_on(&self) -> MEM_CLK_FORCE_ON_R { + MEM_CLK_FORCE_ON_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to force eFuse SRAM into working mode."] + #[inline(always)] + pub fn mem_force_pu(&self) -> MEM_FORCE_PU_R { + MEM_FORCE_PU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 16 - Set this bit to force enable eFuse register configuration clock signal."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK") + .field( + "mem_force_pd", + &format_args!("{}", self.mem_force_pd().bit()), + ) + .field( + "mem_clk_force_on", + &format_args!("{}", self.mem_clk_force_on().bit()), + ) + .field( + "mem_force_pu", + &format_args!("{}", self.mem_force_pu().bit()), + ) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to force eFuse SRAM into power-saving mode."] + #[inline(always)] + #[must_use] + pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W { + MEM_FORCE_PD_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit and force to activate clock signal of eFuse SRAM."] + #[inline(always)] + #[must_use] + pub fn mem_clk_force_on(&mut self) -> MEM_CLK_FORCE_ON_W { + MEM_CLK_FORCE_ON_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to force eFuse SRAM into working mode."] + #[inline(always)] + #[must_use] + pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W { + MEM_FORCE_PU_W::new(self, 2) + } + #[doc = "Bit 16 - Set this bit to force enable eFuse register configuration clock signal."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "eFuse clcok configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_SPEC; +impl crate::RegisterSpec for CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk::R`](R) reader structure"] +impl crate::Readable for CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"] +impl crate::Writable for CLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK to value 0"] +impl crate::Resettable for CLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/cmd.rs b/esp32p4/src/efuse/cmd.rs new file mode 100644 index 0000000000..56bfed4ee1 --- /dev/null +++ b/esp32p4/src/efuse/cmd.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CMD` reader"] +pub type R = crate::R; +#[doc = "Register `CMD` writer"] +pub type W = crate::W; +#[doc = "Field `READ_CMD` reader - Set this bit to send read command."] +pub type READ_CMD_R = crate::BitReader; +#[doc = "Field `READ_CMD` writer - Set this bit to send read command."] +pub type READ_CMD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PGM_CMD` reader - Set this bit to send programming command."] +pub type PGM_CMD_R = crate::BitReader; +#[doc = "Field `PGM_CMD` writer - Set this bit to send programming command."] +pub type PGM_CMD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLK_NUM` reader - The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively."] +pub type BLK_NUM_R = crate::FieldReader; +#[doc = "Field `BLK_NUM` writer - The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively."] +pub type BLK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - Set this bit to send read command."] + #[inline(always)] + pub fn read_cmd(&self) -> READ_CMD_R { + READ_CMD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to send programming command."] + #[inline(always)] + pub fn pgm_cmd(&self) -> PGM_CMD_R { + PGM_CMD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively."] + #[inline(always)] + pub fn blk_num(&self) -> BLK_NUM_R { + BLK_NUM_R::new(((self.bits >> 2) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CMD") + .field("read_cmd", &format_args!("{}", self.read_cmd().bit())) + .field("pgm_cmd", &format_args!("{}", self.pgm_cmd().bit())) + .field("blk_num", &format_args!("{}", self.blk_num().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to send read command."] + #[inline(always)] + #[must_use] + pub fn read_cmd(&mut self) -> READ_CMD_W { + READ_CMD_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to send programming command."] + #[inline(always)] + #[must_use] + pub fn pgm_cmd(&mut self) -> PGM_CMD_W { + PGM_CMD_W::new(self, 1) + } + #[doc = "Bits 2:5 - The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively."] + #[inline(always)] + #[must_use] + pub fn blk_num(&mut self) -> BLK_NUM_W { + BLK_NUM_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "eFuse command register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CMD_SPEC; +impl crate::RegisterSpec for CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmd::R`](R) reader structure"] +impl crate::Readable for CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"] +impl crate::Writable for CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMD to value 0"] +impl crate::Resettable for CMD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/conf.rs b/esp32p4/src/efuse/conf.rs new file mode 100644 index 0000000000..a3ca9f14ab --- /dev/null +++ b/esp32p4/src/efuse/conf.rs @@ -0,0 +1,82 @@ +#[doc = "Register `CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CONF` writer"] +pub type W = crate::W; +#[doc = "Field `OP_CODE` reader - 0x5A5A: programming operation command 0x5AA5: read operation command."] +pub type OP_CODE_R = crate::FieldReader; +#[doc = "Field `OP_CODE` writer - 0x5A5A: programming operation command 0x5AA5: read operation command."] +pub type OP_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CFG_ECDSA_BLK` reader - Configures which block to use for ECDSA key output."] +pub type CFG_ECDSA_BLK_R = crate::FieldReader; +#[doc = "Field `CFG_ECDSA_BLK` writer - Configures which block to use for ECDSA key output."] +pub type CFG_ECDSA_BLK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - 0x5A5A: programming operation command 0x5AA5: read operation command."] + #[inline(always)] + pub fn op_code(&self) -> OP_CODE_R { + OP_CODE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Configures which block to use for ECDSA key output."] + #[inline(always)] + pub fn cfg_ecdsa_blk(&self) -> CFG_ECDSA_BLK_R { + CFG_ECDSA_BLK_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF") + .field("op_code", &format_args!("{}", self.op_code().bits())) + .field( + "cfg_ecdsa_blk", + &format_args!("{}", self.cfg_ecdsa_blk().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - 0x5A5A: programming operation command 0x5AA5: read operation command."] + #[inline(always)] + #[must_use] + pub fn op_code(&mut self) -> OP_CODE_W { + OP_CODE_W::new(self, 0) + } + #[doc = "Bits 16:19 - Configures which block to use for ECDSA key output."] + #[inline(always)] + #[must_use] + pub fn cfg_ecdsa_blk(&mut self) -> CFG_ECDSA_BLK_W { + CFG_ECDSA_BLK_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "eFuse operation mode configuraiton register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SPEC; +impl crate::RegisterSpec for CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf::R`](R) reader structure"] +impl crate::Readable for CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"] +impl crate::Writable for CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF to value 0"] +impl crate::Resettable for CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/dac_conf.rs b/esp32p4/src/efuse/dac_conf.rs new file mode 100644 index 0000000000..f5b908ab16 --- /dev/null +++ b/esp32p4/src/efuse/dac_conf.rs @@ -0,0 +1,117 @@ +#[doc = "Register `DAC_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `DAC_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `DAC_CLK_DIV` reader - Controls the division factor of the rising clock of the programming voltage."] +pub type DAC_CLK_DIV_R = crate::FieldReader; +#[doc = "Field `DAC_CLK_DIV` writer - Controls the division factor of the rising clock of the programming voltage."] +pub type DAC_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DAC_CLK_PAD_SEL` reader - Don't care."] +pub type DAC_CLK_PAD_SEL_R = crate::BitReader; +#[doc = "Field `DAC_CLK_PAD_SEL` writer - Don't care."] +pub type DAC_CLK_PAD_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DAC_NUM` reader - Controls the rising period of the programming voltage."] +pub type DAC_NUM_R = crate::FieldReader; +#[doc = "Field `DAC_NUM` writer - Controls the rising period of the programming voltage."] +pub type DAC_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `OE_CLR` reader - Reduces the power supply of the programming voltage."] +pub type OE_CLR_R = crate::BitReader; +#[doc = "Field `OE_CLR` writer - Reduces the power supply of the programming voltage."] +pub type OE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Controls the division factor of the rising clock of the programming voltage."] + #[inline(always)] + pub fn dac_clk_div(&self) -> DAC_CLK_DIV_R { + DAC_CLK_DIV_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - Don't care."] + #[inline(always)] + pub fn dac_clk_pad_sel(&self) -> DAC_CLK_PAD_SEL_R { + DAC_CLK_PAD_SEL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:16 - Controls the rising period of the programming voltage."] + #[inline(always)] + pub fn dac_num(&self) -> DAC_NUM_R { + DAC_NUM_R::new(((self.bits >> 9) & 0xff) as u8) + } + #[doc = "Bit 17 - Reduces the power supply of the programming voltage."] + #[inline(always)] + pub fn oe_clr(&self) -> OE_CLR_R { + OE_CLR_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DAC_CONF") + .field( + "dac_clk_div", + &format_args!("{}", self.dac_clk_div().bits()), + ) + .field( + "dac_clk_pad_sel", + &format_args!("{}", self.dac_clk_pad_sel().bit()), + ) + .field("dac_num", &format_args!("{}", self.dac_num().bits())) + .field("oe_clr", &format_args!("{}", self.oe_clr().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Controls the division factor of the rising clock of the programming voltage."] + #[inline(always)] + #[must_use] + pub fn dac_clk_div(&mut self) -> DAC_CLK_DIV_W { + DAC_CLK_DIV_W::new(self, 0) + } + #[doc = "Bit 8 - Don't care."] + #[inline(always)] + #[must_use] + pub fn dac_clk_pad_sel(&mut self) -> DAC_CLK_PAD_SEL_W { + DAC_CLK_PAD_SEL_W::new(self, 8) + } + #[doc = "Bits 9:16 - Controls the rising period of the programming voltage."] + #[inline(always)] + #[must_use] + pub fn dac_num(&mut self) -> DAC_NUM_W { + DAC_NUM_W::new(self, 9) + } + #[doc = "Bit 17 - Reduces the power supply of the programming voltage."] + #[inline(always)] + #[must_use] + pub fn oe_clr(&mut self) -> OE_CLR_W { + OE_CLR_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Controls the eFuse programming voltage.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dac_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DAC_CONF_SPEC; +impl crate::RegisterSpec for DAC_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dac_conf::R`](R) reader structure"] +impl crate::Readable for DAC_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dac_conf::W`](W) writer structure"] +impl crate::Writable for DAC_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DAC_CONF to value 0x0001_fe17"] +impl crate::Resettable for DAC_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_fe17; +} diff --git a/esp32p4/src/efuse/date.rs b/esp32p4/src/efuse/date.rs new file mode 100644 index 0000000000..22333d7978 --- /dev/null +++ b/esp32p4/src/efuse/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - Stores eFuse version."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - Stores eFuse version."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Stores eFuse version."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Stores eFuse version."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "eFuse version register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_5050"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_5050; +} diff --git a/esp32p4/src/efuse/int_clr.rs b/esp32p4/src/efuse/int_clr.rs new file mode 100644 index 0000000000..94d28753fd --- /dev/null +++ b/esp32p4/src/efuse/int_clr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `READ_DONE_INT_CLR` writer - The clear signal for read_done interrupt."] +pub type READ_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PGM_DONE_INT_CLR` writer - The clear signal for pgm_done interrupt."] +pub type PGM_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - The clear signal for read_done interrupt."] + #[inline(always)] + #[must_use] + pub fn read_done_int_clr(&mut self) -> READ_DONE_INT_CLR_W { + READ_DONE_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - The clear signal for pgm_done interrupt."] + #[inline(always)] + #[must_use] + pub fn pgm_done_int_clr(&mut self) -> PGM_DONE_INT_CLR_W { + PGM_DONE_INT_CLR_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "eFuse interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/int_ena.rs b/esp32p4/src/efuse/int_ena.rs new file mode 100644 index 0000000000..b941f9fd93 --- /dev/null +++ b/esp32p4/src/efuse/int_ena.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `READ_DONE_INT_ENA` reader - The enable signal for read_done interrupt."] +pub type READ_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `READ_DONE_INT_ENA` writer - The enable signal for read_done interrupt."] +pub type READ_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PGM_DONE_INT_ENA` reader - The enable signal for pgm_done interrupt."] +pub type PGM_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `PGM_DONE_INT_ENA` writer - The enable signal for pgm_done interrupt."] +pub type PGM_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The enable signal for read_done interrupt."] + #[inline(always)] + pub fn read_done_int_ena(&self) -> READ_DONE_INT_ENA_R { + READ_DONE_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The enable signal for pgm_done interrupt."] + #[inline(always)] + pub fn pgm_done_int_ena(&self) -> PGM_DONE_INT_ENA_R { + PGM_DONE_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "read_done_int_ena", + &format_args!("{}", self.read_done_int_ena().bit()), + ) + .field( + "pgm_done_int_ena", + &format_args!("{}", self.pgm_done_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The enable signal for read_done interrupt."] + #[inline(always)] + #[must_use] + pub fn read_done_int_ena(&mut self) -> READ_DONE_INT_ENA_W { + READ_DONE_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The enable signal for pgm_done interrupt."] + #[inline(always)] + #[must_use] + pub fn pgm_done_int_ena(&mut self) -> PGM_DONE_INT_ENA_W { + PGM_DONE_INT_ENA_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "eFuse interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/int_raw.rs b/esp32p4/src/efuse/int_raw.rs new file mode 100644 index 0000000000..c1212d31cf --- /dev/null +++ b/esp32p4/src/efuse/int_raw.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `READ_DONE_INT_RAW` reader - The raw bit signal for read_done interrupt."] +pub type READ_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `PGM_DONE_INT_RAW` reader - The raw bit signal for pgm_done interrupt."] +pub type PGM_DONE_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw bit signal for read_done interrupt."] + #[inline(always)] + pub fn read_done_int_raw(&self) -> READ_DONE_INT_RAW_R { + READ_DONE_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw bit signal for pgm_done interrupt."] + #[inline(always)] + pub fn pgm_done_int_raw(&self) -> PGM_DONE_INT_RAW_R { + PGM_DONE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "read_done_int_raw", + &format_args!("{}", self.read_done_int_raw().bit()), + ) + .field( + "pgm_done_int_raw", + &format_args!("{}", self.pgm_done_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse raw interrupt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/int_st.rs b/esp32p4/src/efuse/int_st.rs new file mode 100644 index 0000000000..4f89ed1f09 --- /dev/null +++ b/esp32p4/src/efuse/int_st.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `READ_DONE_INT_ST` reader - The status signal for read_done interrupt."] +pub type READ_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `PGM_DONE_INT_ST` reader - The status signal for pgm_done interrupt."] +pub type PGM_DONE_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The status signal for read_done interrupt."] + #[inline(always)] + pub fn read_done_int_st(&self) -> READ_DONE_INT_ST_R { + READ_DONE_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The status signal for pgm_done interrupt."] + #[inline(always)] + pub fn pgm_done_int_st(&self) -> PGM_DONE_INT_ST_R { + PGM_DONE_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "read_done_int_st", + &format_args!("{}", self.read_done_int_st().bit()), + ) + .field( + "pgm_done_int_st", + &format_args!("{}", self.pgm_done_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/pgm_check_value0.rs b/esp32p4/src/efuse/pgm_check_value0.rs new file mode 100644 index 0000000000..e72bf1ceaa --- /dev/null +++ b/esp32p4/src/efuse/pgm_check_value0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PGM_CHECK_VALUE0` reader"] +pub type R = crate::R; +#[doc = "Register `PGM_CHECK_VALUE0` writer"] +pub type W = crate::W; +#[doc = "Field `PGM_RS_DATA_0` reader - Configures the 0th 32-bit RS code to be programmed."] +pub type PGM_RS_DATA_0_R = crate::FieldReader; +#[doc = "Field `PGM_RS_DATA_0` writer - Configures the 0th 32-bit RS code to be programmed."] +pub type PGM_RS_DATA_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures the 0th 32-bit RS code to be programmed."] + #[inline(always)] + pub fn pgm_rs_data_0(&self) -> PGM_RS_DATA_0_R { + PGM_RS_DATA_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PGM_CHECK_VALUE0") + .field( + "pgm_rs_data_0", + &format_args!("{}", self.pgm_rs_data_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures the 0th 32-bit RS code to be programmed."] + #[inline(always)] + #[must_use] + pub fn pgm_rs_data_0(&mut self) -> PGM_RS_DATA_0_W { + PGM_RS_DATA_0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register 0 that stores the RS code to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_check_value0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_check_value0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PGM_CHECK_VALUE0_SPEC; +impl crate::RegisterSpec for PGM_CHECK_VALUE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgm_check_value0::R`](R) reader structure"] +impl crate::Readable for PGM_CHECK_VALUE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pgm_check_value0::W`](W) writer structure"] +impl crate::Writable for PGM_CHECK_VALUE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PGM_CHECK_VALUE0 to value 0"] +impl crate::Resettable for PGM_CHECK_VALUE0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/pgm_check_value1.rs b/esp32p4/src/efuse/pgm_check_value1.rs new file mode 100644 index 0000000000..8d76bce2f1 --- /dev/null +++ b/esp32p4/src/efuse/pgm_check_value1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PGM_CHECK_VALUE1` reader"] +pub type R = crate::R; +#[doc = "Register `PGM_CHECK_VALUE1` writer"] +pub type W = crate::W; +#[doc = "Field `PGM_RS_DATA_1` reader - Configures the 1st 32-bit RS code to be programmed."] +pub type PGM_RS_DATA_1_R = crate::FieldReader; +#[doc = "Field `PGM_RS_DATA_1` writer - Configures the 1st 32-bit RS code to be programmed."] +pub type PGM_RS_DATA_1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures the 1st 32-bit RS code to be programmed."] + #[inline(always)] + pub fn pgm_rs_data_1(&self) -> PGM_RS_DATA_1_R { + PGM_RS_DATA_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PGM_CHECK_VALUE1") + .field( + "pgm_rs_data_1", + &format_args!("{}", self.pgm_rs_data_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures the 1st 32-bit RS code to be programmed."] + #[inline(always)] + #[must_use] + pub fn pgm_rs_data_1(&mut self) -> PGM_RS_DATA_1_W { + PGM_RS_DATA_1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register 1 that stores the RS code to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_check_value1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_check_value1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PGM_CHECK_VALUE1_SPEC; +impl crate::RegisterSpec for PGM_CHECK_VALUE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgm_check_value1::R`](R) reader structure"] +impl crate::Readable for PGM_CHECK_VALUE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pgm_check_value1::W`](W) writer structure"] +impl crate::Writable for PGM_CHECK_VALUE1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PGM_CHECK_VALUE1 to value 0"] +impl crate::Resettable for PGM_CHECK_VALUE1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/pgm_check_value2.rs b/esp32p4/src/efuse/pgm_check_value2.rs new file mode 100644 index 0000000000..b30bb50eb2 --- /dev/null +++ b/esp32p4/src/efuse/pgm_check_value2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PGM_CHECK_VALUE2` reader"] +pub type R = crate::R; +#[doc = "Register `PGM_CHECK_VALUE2` writer"] +pub type W = crate::W; +#[doc = "Field `PGM_RS_DATA_2` reader - Configures the 2nd 32-bit RS code to be programmed."] +pub type PGM_RS_DATA_2_R = crate::FieldReader; +#[doc = "Field `PGM_RS_DATA_2` writer - Configures the 2nd 32-bit RS code to be programmed."] +pub type PGM_RS_DATA_2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures the 2nd 32-bit RS code to be programmed."] + #[inline(always)] + pub fn pgm_rs_data_2(&self) -> PGM_RS_DATA_2_R { + PGM_RS_DATA_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PGM_CHECK_VALUE2") + .field( + "pgm_rs_data_2", + &format_args!("{}", self.pgm_rs_data_2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures the 2nd 32-bit RS code to be programmed."] + #[inline(always)] + #[must_use] + pub fn pgm_rs_data_2(&mut self) -> PGM_RS_DATA_2_W { + PGM_RS_DATA_2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register 2 that stores the RS code to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_check_value2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_check_value2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PGM_CHECK_VALUE2_SPEC; +impl crate::RegisterSpec for PGM_CHECK_VALUE2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgm_check_value2::R`](R) reader structure"] +impl crate::Readable for PGM_CHECK_VALUE2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pgm_check_value2::W`](W) writer structure"] +impl crate::Writable for PGM_CHECK_VALUE2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PGM_CHECK_VALUE2 to value 0"] +impl crate::Resettable for PGM_CHECK_VALUE2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/pgm_data0.rs b/esp32p4/src/efuse/pgm_data0.rs new file mode 100644 index 0000000000..6ff17f4b78 --- /dev/null +++ b/esp32p4/src/efuse/pgm_data0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PGM_DATA0` reader"] +pub type R = crate::R; +#[doc = "Register `PGM_DATA0` writer"] +pub type W = crate::W; +#[doc = "Field `PGM_DATA_0` reader - Configures the 0th 32-bit data to be programmed."] +pub type PGM_DATA_0_R = crate::FieldReader; +#[doc = "Field `PGM_DATA_0` writer - Configures the 0th 32-bit data to be programmed."] +pub type PGM_DATA_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures the 0th 32-bit data to be programmed."] + #[inline(always)] + pub fn pgm_data_0(&self) -> PGM_DATA_0_R { + PGM_DATA_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PGM_DATA0") + .field("pgm_data_0", &format_args!("{}", self.pgm_data_0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures the 0th 32-bit data to be programmed."] + #[inline(always)] + #[must_use] + pub fn pgm_data_0(&mut self) -> PGM_DATA_0_W { + PGM_DATA_0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register 0 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PGM_DATA0_SPEC; +impl crate::RegisterSpec for PGM_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgm_data0::R`](R) reader structure"] +impl crate::Readable for PGM_DATA0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pgm_data0::W`](W) writer structure"] +impl crate::Writable for PGM_DATA0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PGM_DATA0 to value 0"] +impl crate::Resettable for PGM_DATA0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/pgm_data1.rs b/esp32p4/src/efuse/pgm_data1.rs new file mode 100644 index 0000000000..bb655fdc48 --- /dev/null +++ b/esp32p4/src/efuse/pgm_data1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PGM_DATA1` reader"] +pub type R = crate::R; +#[doc = "Register `PGM_DATA1` writer"] +pub type W = crate::W; +#[doc = "Field `PGM_DATA_1` reader - Configures the 1st 32-bit data to be programmed."] +pub type PGM_DATA_1_R = crate::FieldReader; +#[doc = "Field `PGM_DATA_1` writer - Configures the 1st 32-bit data to be programmed."] +pub type PGM_DATA_1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures the 1st 32-bit data to be programmed."] + #[inline(always)] + pub fn pgm_data_1(&self) -> PGM_DATA_1_R { + PGM_DATA_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PGM_DATA1") + .field("pgm_data_1", &format_args!("{}", self.pgm_data_1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures the 1st 32-bit data to be programmed."] + #[inline(always)] + #[must_use] + pub fn pgm_data_1(&mut self) -> PGM_DATA_1_W { + PGM_DATA_1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register 1 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PGM_DATA1_SPEC; +impl crate::RegisterSpec for PGM_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgm_data1::R`](R) reader structure"] +impl crate::Readable for PGM_DATA1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pgm_data1::W`](W) writer structure"] +impl crate::Writable for PGM_DATA1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PGM_DATA1 to value 0"] +impl crate::Resettable for PGM_DATA1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/pgm_data2.rs b/esp32p4/src/efuse/pgm_data2.rs new file mode 100644 index 0000000000..b30654273b --- /dev/null +++ b/esp32p4/src/efuse/pgm_data2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PGM_DATA2` reader"] +pub type R = crate::R; +#[doc = "Register `PGM_DATA2` writer"] +pub type W = crate::W; +#[doc = "Field `PGM_DATA_2` reader - Configures the 2nd 32-bit data to be programmed."] +pub type PGM_DATA_2_R = crate::FieldReader; +#[doc = "Field `PGM_DATA_2` writer - Configures the 2nd 32-bit data to be programmed."] +pub type PGM_DATA_2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures the 2nd 32-bit data to be programmed."] + #[inline(always)] + pub fn pgm_data_2(&self) -> PGM_DATA_2_R { + PGM_DATA_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PGM_DATA2") + .field("pgm_data_2", &format_args!("{}", self.pgm_data_2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures the 2nd 32-bit data to be programmed."] + #[inline(always)] + #[must_use] + pub fn pgm_data_2(&mut self) -> PGM_DATA_2_W { + PGM_DATA_2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register 2 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PGM_DATA2_SPEC; +impl crate::RegisterSpec for PGM_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgm_data2::R`](R) reader structure"] +impl crate::Readable for PGM_DATA2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pgm_data2::W`](W) writer structure"] +impl crate::Writable for PGM_DATA2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PGM_DATA2 to value 0"] +impl crate::Resettable for PGM_DATA2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/pgm_data3.rs b/esp32p4/src/efuse/pgm_data3.rs new file mode 100644 index 0000000000..bc4eed217f --- /dev/null +++ b/esp32p4/src/efuse/pgm_data3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PGM_DATA3` reader"] +pub type R = crate::R; +#[doc = "Register `PGM_DATA3` writer"] +pub type W = crate::W; +#[doc = "Field `PGM_DATA_3` reader - Configures the 3rd 32-bit data to be programmed."] +pub type PGM_DATA_3_R = crate::FieldReader; +#[doc = "Field `PGM_DATA_3` writer - Configures the 3rd 32-bit data to be programmed."] +pub type PGM_DATA_3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures the 3rd 32-bit data to be programmed."] + #[inline(always)] + pub fn pgm_data_3(&self) -> PGM_DATA_3_R { + PGM_DATA_3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PGM_DATA3") + .field("pgm_data_3", &format_args!("{}", self.pgm_data_3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures the 3rd 32-bit data to be programmed."] + #[inline(always)] + #[must_use] + pub fn pgm_data_3(&mut self) -> PGM_DATA_3_W { + PGM_DATA_3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register 3 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PGM_DATA3_SPEC; +impl crate::RegisterSpec for PGM_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgm_data3::R`](R) reader structure"] +impl crate::Readable for PGM_DATA3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pgm_data3::W`](W) writer structure"] +impl crate::Writable for PGM_DATA3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PGM_DATA3 to value 0"] +impl crate::Resettable for PGM_DATA3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/pgm_data4.rs b/esp32p4/src/efuse/pgm_data4.rs new file mode 100644 index 0000000000..7b8e44dbbb --- /dev/null +++ b/esp32p4/src/efuse/pgm_data4.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PGM_DATA4` reader"] +pub type R = crate::R; +#[doc = "Register `PGM_DATA4` writer"] +pub type W = crate::W; +#[doc = "Field `PGM_DATA_4` reader - Configures the 4th 32-bit data to be programmed."] +pub type PGM_DATA_4_R = crate::FieldReader; +#[doc = "Field `PGM_DATA_4` writer - Configures the 4th 32-bit data to be programmed."] +pub type PGM_DATA_4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures the 4th 32-bit data to be programmed."] + #[inline(always)] + pub fn pgm_data_4(&self) -> PGM_DATA_4_R { + PGM_DATA_4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PGM_DATA4") + .field("pgm_data_4", &format_args!("{}", self.pgm_data_4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures the 4th 32-bit data to be programmed."] + #[inline(always)] + #[must_use] + pub fn pgm_data_4(&mut self) -> PGM_DATA_4_W { + PGM_DATA_4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register 4 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PGM_DATA4_SPEC; +impl crate::RegisterSpec for PGM_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgm_data4::R`](R) reader structure"] +impl crate::Readable for PGM_DATA4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pgm_data4::W`](W) writer structure"] +impl crate::Writable for PGM_DATA4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PGM_DATA4 to value 0"] +impl crate::Resettable for PGM_DATA4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/pgm_data5.rs b/esp32p4/src/efuse/pgm_data5.rs new file mode 100644 index 0000000000..ea7b08fbd5 --- /dev/null +++ b/esp32p4/src/efuse/pgm_data5.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PGM_DATA5` reader"] +pub type R = crate::R; +#[doc = "Register `PGM_DATA5` writer"] +pub type W = crate::W; +#[doc = "Field `PGM_DATA_5` reader - Configures the 5th 32-bit data to be programmed."] +pub type PGM_DATA_5_R = crate::FieldReader; +#[doc = "Field `PGM_DATA_5` writer - Configures the 5th 32-bit data to be programmed."] +pub type PGM_DATA_5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures the 5th 32-bit data to be programmed."] + #[inline(always)] + pub fn pgm_data_5(&self) -> PGM_DATA_5_R { + PGM_DATA_5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PGM_DATA5") + .field("pgm_data_5", &format_args!("{}", self.pgm_data_5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures the 5th 32-bit data to be programmed."] + #[inline(always)] + #[must_use] + pub fn pgm_data_5(&mut self) -> PGM_DATA_5_W { + PGM_DATA_5_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register 5 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PGM_DATA5_SPEC; +impl crate::RegisterSpec for PGM_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgm_data5::R`](R) reader structure"] +impl crate::Readable for PGM_DATA5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pgm_data5::W`](W) writer structure"] +impl crate::Writable for PGM_DATA5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PGM_DATA5 to value 0"] +impl crate::Resettable for PGM_DATA5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/pgm_data6.rs b/esp32p4/src/efuse/pgm_data6.rs new file mode 100644 index 0000000000..223528e935 --- /dev/null +++ b/esp32p4/src/efuse/pgm_data6.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PGM_DATA6` reader"] +pub type R = crate::R; +#[doc = "Register `PGM_DATA6` writer"] +pub type W = crate::W; +#[doc = "Field `PGM_DATA_6` reader - Configures the 6th 32-bit data to be programmed."] +pub type PGM_DATA_6_R = crate::FieldReader; +#[doc = "Field `PGM_DATA_6` writer - Configures the 6th 32-bit data to be programmed."] +pub type PGM_DATA_6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures the 6th 32-bit data to be programmed."] + #[inline(always)] + pub fn pgm_data_6(&self) -> PGM_DATA_6_R { + PGM_DATA_6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PGM_DATA6") + .field("pgm_data_6", &format_args!("{}", self.pgm_data_6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures the 6th 32-bit data to be programmed."] + #[inline(always)] + #[must_use] + pub fn pgm_data_6(&mut self) -> PGM_DATA_6_W { + PGM_DATA_6_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register 6 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PGM_DATA6_SPEC; +impl crate::RegisterSpec for PGM_DATA6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgm_data6::R`](R) reader structure"] +impl crate::Readable for PGM_DATA6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pgm_data6::W`](W) writer structure"] +impl crate::Writable for PGM_DATA6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PGM_DATA6 to value 0"] +impl crate::Resettable for PGM_DATA6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/pgm_data7.rs b/esp32p4/src/efuse/pgm_data7.rs new file mode 100644 index 0000000000..de9a3472b1 --- /dev/null +++ b/esp32p4/src/efuse/pgm_data7.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PGM_DATA7` reader"] +pub type R = crate::R; +#[doc = "Register `PGM_DATA7` writer"] +pub type W = crate::W; +#[doc = "Field `PGM_DATA_7` reader - Configures the 7th 32-bit data to be programmed."] +pub type PGM_DATA_7_R = crate::FieldReader; +#[doc = "Field `PGM_DATA_7` writer - Configures the 7th 32-bit data to be programmed."] +pub type PGM_DATA_7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures the 7th 32-bit data to be programmed."] + #[inline(always)] + pub fn pgm_data_7(&self) -> PGM_DATA_7_R { + PGM_DATA_7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PGM_DATA7") + .field("pgm_data_7", &format_args!("{}", self.pgm_data_7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures the 7th 32-bit data to be programmed."] + #[inline(always)] + #[must_use] + pub fn pgm_data_7(&mut self) -> PGM_DATA_7_W { + PGM_DATA_7_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register 7 that stores data to be programmed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pgm_data7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pgm_data7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PGM_DATA7_SPEC; +impl crate::RegisterSpec for PGM_DATA7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pgm_data7::R`](R) reader structure"] +impl crate::Readable for PGM_DATA7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pgm_data7::W`](W) writer structure"] +impl crate::Writable for PGM_DATA7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PGM_DATA7 to value 0"] +impl crate::Resettable for PGM_DATA7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key0_data0.rs b/esp32p4/src/efuse/rd_key0_data0.rs new file mode 100644 index 0000000000..c4b5cc2b62 --- /dev/null +++ b/esp32p4/src/efuse/rd_key0_data0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY0_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `KEY0_DATA0` reader - Stores the zeroth 32 bits of KEY0."] +pub type KEY0_DATA0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the zeroth 32 bits of KEY0."] + #[inline(always)] + pub fn key0_data0(&self) -> KEY0_DATA0_R { + KEY0_DATA0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY0_DATA0") + .field("key0_data0", &format_args!("{}", self.key0_data0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY0_DATA0_SPEC; +impl crate::RegisterSpec for RD_KEY0_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key0_data0::R`](R) reader structure"] +impl crate::Readable for RD_KEY0_DATA0_SPEC {} +#[doc = "`reset()` method sets RD_KEY0_DATA0 to value 0"] +impl crate::Resettable for RD_KEY0_DATA0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key0_data1.rs b/esp32p4/src/efuse/rd_key0_data1.rs new file mode 100644 index 0000000000..b8203862d0 --- /dev/null +++ b/esp32p4/src/efuse/rd_key0_data1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY0_DATA1` reader"] +pub type R = crate::R; +#[doc = "Field `KEY0_DATA1` reader - Stores the first 32 bits of KEY0."] +pub type KEY0_DATA1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the first 32 bits of KEY0."] + #[inline(always)] + pub fn key0_data1(&self) -> KEY0_DATA1_R { + KEY0_DATA1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY0_DATA1") + .field("key0_data1", &format_args!("{}", self.key0_data1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY0_DATA1_SPEC; +impl crate::RegisterSpec for RD_KEY0_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key0_data1::R`](R) reader structure"] +impl crate::Readable for RD_KEY0_DATA1_SPEC {} +#[doc = "`reset()` method sets RD_KEY0_DATA1 to value 0"] +impl crate::Resettable for RD_KEY0_DATA1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key0_data2.rs b/esp32p4/src/efuse/rd_key0_data2.rs new file mode 100644 index 0000000000..9d5269173b --- /dev/null +++ b/esp32p4/src/efuse/rd_key0_data2.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY0_DATA2` reader"] +pub type R = crate::R; +#[doc = "Field `KEY0_DATA2` reader - Stores the second 32 bits of KEY0."] +pub type KEY0_DATA2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the second 32 bits of KEY0."] + #[inline(always)] + pub fn key0_data2(&self) -> KEY0_DATA2_R { + KEY0_DATA2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY0_DATA2") + .field("key0_data2", &format_args!("{}", self.key0_data2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY0_DATA2_SPEC; +impl crate::RegisterSpec for RD_KEY0_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key0_data2::R`](R) reader structure"] +impl crate::Readable for RD_KEY0_DATA2_SPEC {} +#[doc = "`reset()` method sets RD_KEY0_DATA2 to value 0"] +impl crate::Resettable for RD_KEY0_DATA2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key0_data3.rs b/esp32p4/src/efuse/rd_key0_data3.rs new file mode 100644 index 0000000000..43a081e3a3 --- /dev/null +++ b/esp32p4/src/efuse/rd_key0_data3.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY0_DATA3` reader"] +pub type R = crate::R; +#[doc = "Field `KEY0_DATA3` reader - Stores the third 32 bits of KEY0."] +pub type KEY0_DATA3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the third 32 bits of KEY0."] + #[inline(always)] + pub fn key0_data3(&self) -> KEY0_DATA3_R { + KEY0_DATA3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY0_DATA3") + .field("key0_data3", &format_args!("{}", self.key0_data3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY0_DATA3_SPEC; +impl crate::RegisterSpec for RD_KEY0_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key0_data3::R`](R) reader structure"] +impl crate::Readable for RD_KEY0_DATA3_SPEC {} +#[doc = "`reset()` method sets RD_KEY0_DATA3 to value 0"] +impl crate::Resettable for RD_KEY0_DATA3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key0_data4.rs b/esp32p4/src/efuse/rd_key0_data4.rs new file mode 100644 index 0000000000..d2c7c2d88a --- /dev/null +++ b/esp32p4/src/efuse/rd_key0_data4.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY0_DATA4` reader"] +pub type R = crate::R; +#[doc = "Field `KEY0_DATA4` reader - Stores the fourth 32 bits of KEY0."] +pub type KEY0_DATA4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fourth 32 bits of KEY0."] + #[inline(always)] + pub fn key0_data4(&self) -> KEY0_DATA4_R { + KEY0_DATA4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY0_DATA4") + .field("key0_data4", &format_args!("{}", self.key0_data4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY0_DATA4_SPEC; +impl crate::RegisterSpec for RD_KEY0_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key0_data4::R`](R) reader structure"] +impl crate::Readable for RD_KEY0_DATA4_SPEC {} +#[doc = "`reset()` method sets RD_KEY0_DATA4 to value 0"] +impl crate::Resettable for RD_KEY0_DATA4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key0_data5.rs b/esp32p4/src/efuse/rd_key0_data5.rs new file mode 100644 index 0000000000..b267bc27b0 --- /dev/null +++ b/esp32p4/src/efuse/rd_key0_data5.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY0_DATA5` reader"] +pub type R = crate::R; +#[doc = "Field `KEY0_DATA5` reader - Stores the fifth 32 bits of KEY0."] +pub type KEY0_DATA5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fifth 32 bits of KEY0."] + #[inline(always)] + pub fn key0_data5(&self) -> KEY0_DATA5_R { + KEY0_DATA5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY0_DATA5") + .field("key0_data5", &format_args!("{}", self.key0_data5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY0_DATA5_SPEC; +impl crate::RegisterSpec for RD_KEY0_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key0_data5::R`](R) reader structure"] +impl crate::Readable for RD_KEY0_DATA5_SPEC {} +#[doc = "`reset()` method sets RD_KEY0_DATA5 to value 0"] +impl crate::Resettable for RD_KEY0_DATA5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key0_data6.rs b/esp32p4/src/efuse/rd_key0_data6.rs new file mode 100644 index 0000000000..44e44dd54e --- /dev/null +++ b/esp32p4/src/efuse/rd_key0_data6.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY0_DATA6` reader"] +pub type R = crate::R; +#[doc = "Field `KEY0_DATA6` reader - Stores the sixth 32 bits of KEY0."] +pub type KEY0_DATA6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the sixth 32 bits of KEY0."] + #[inline(always)] + pub fn key0_data6(&self) -> KEY0_DATA6_R { + KEY0_DATA6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY0_DATA6") + .field("key0_data6", &format_args!("{}", self.key0_data6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY0_DATA6_SPEC; +impl crate::RegisterSpec for RD_KEY0_DATA6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key0_data6::R`](R) reader structure"] +impl crate::Readable for RD_KEY0_DATA6_SPEC {} +#[doc = "`reset()` method sets RD_KEY0_DATA6 to value 0"] +impl crate::Resettable for RD_KEY0_DATA6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key0_data7.rs b/esp32p4/src/efuse/rd_key0_data7.rs new file mode 100644 index 0000000000..542bb4e738 --- /dev/null +++ b/esp32p4/src/efuse/rd_key0_data7.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY0_DATA7` reader"] +pub type R = crate::R; +#[doc = "Field `KEY0_DATA7` reader - Stores the seventh 32 bits of KEY0."] +pub type KEY0_DATA7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the seventh 32 bits of KEY0."] + #[inline(always)] + pub fn key0_data7(&self) -> KEY0_DATA7_R { + KEY0_DATA7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY0_DATA7") + .field("key0_data7", &format_args!("{}", self.key0_data7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY0_DATA7_SPEC; +impl crate::RegisterSpec for RD_KEY0_DATA7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key0_data7::R`](R) reader structure"] +impl crate::Readable for RD_KEY0_DATA7_SPEC {} +#[doc = "`reset()` method sets RD_KEY0_DATA7 to value 0"] +impl crate::Resettable for RD_KEY0_DATA7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key1_data0.rs b/esp32p4/src/efuse/rd_key1_data0.rs new file mode 100644 index 0000000000..46f597ad78 --- /dev/null +++ b/esp32p4/src/efuse/rd_key1_data0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY1_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `KEY1_DATA0` reader - Stores the zeroth 32 bits of KEY1."] +pub type KEY1_DATA0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the zeroth 32 bits of KEY1."] + #[inline(always)] + pub fn key1_data0(&self) -> KEY1_DATA0_R { + KEY1_DATA0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY1_DATA0") + .field("key1_data0", &format_args!("{}", self.key1_data0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY1_DATA0_SPEC; +impl crate::RegisterSpec for RD_KEY1_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key1_data0::R`](R) reader structure"] +impl crate::Readable for RD_KEY1_DATA0_SPEC {} +#[doc = "`reset()` method sets RD_KEY1_DATA0 to value 0"] +impl crate::Resettable for RD_KEY1_DATA0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key1_data1.rs b/esp32p4/src/efuse/rd_key1_data1.rs new file mode 100644 index 0000000000..91a483bb22 --- /dev/null +++ b/esp32p4/src/efuse/rd_key1_data1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY1_DATA1` reader"] +pub type R = crate::R; +#[doc = "Field `KEY1_DATA1` reader - Stores the first 32 bits of KEY1."] +pub type KEY1_DATA1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the first 32 bits of KEY1."] + #[inline(always)] + pub fn key1_data1(&self) -> KEY1_DATA1_R { + KEY1_DATA1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY1_DATA1") + .field("key1_data1", &format_args!("{}", self.key1_data1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY1_DATA1_SPEC; +impl crate::RegisterSpec for RD_KEY1_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key1_data1::R`](R) reader structure"] +impl crate::Readable for RD_KEY1_DATA1_SPEC {} +#[doc = "`reset()` method sets RD_KEY1_DATA1 to value 0"] +impl crate::Resettable for RD_KEY1_DATA1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key1_data2.rs b/esp32p4/src/efuse/rd_key1_data2.rs new file mode 100644 index 0000000000..6a7af55030 --- /dev/null +++ b/esp32p4/src/efuse/rd_key1_data2.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY1_DATA2` reader"] +pub type R = crate::R; +#[doc = "Field `KEY1_DATA2` reader - Stores the second 32 bits of KEY1."] +pub type KEY1_DATA2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the second 32 bits of KEY1."] + #[inline(always)] + pub fn key1_data2(&self) -> KEY1_DATA2_R { + KEY1_DATA2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY1_DATA2") + .field("key1_data2", &format_args!("{}", self.key1_data2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY1_DATA2_SPEC; +impl crate::RegisterSpec for RD_KEY1_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key1_data2::R`](R) reader structure"] +impl crate::Readable for RD_KEY1_DATA2_SPEC {} +#[doc = "`reset()` method sets RD_KEY1_DATA2 to value 0"] +impl crate::Resettable for RD_KEY1_DATA2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key1_data3.rs b/esp32p4/src/efuse/rd_key1_data3.rs new file mode 100644 index 0000000000..d136137db6 --- /dev/null +++ b/esp32p4/src/efuse/rd_key1_data3.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY1_DATA3` reader"] +pub type R = crate::R; +#[doc = "Field `KEY1_DATA3` reader - Stores the third 32 bits of KEY1."] +pub type KEY1_DATA3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the third 32 bits of KEY1."] + #[inline(always)] + pub fn key1_data3(&self) -> KEY1_DATA3_R { + KEY1_DATA3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY1_DATA3") + .field("key1_data3", &format_args!("{}", self.key1_data3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY1_DATA3_SPEC; +impl crate::RegisterSpec for RD_KEY1_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key1_data3::R`](R) reader structure"] +impl crate::Readable for RD_KEY1_DATA3_SPEC {} +#[doc = "`reset()` method sets RD_KEY1_DATA3 to value 0"] +impl crate::Resettable for RD_KEY1_DATA3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key1_data4.rs b/esp32p4/src/efuse/rd_key1_data4.rs new file mode 100644 index 0000000000..1da3e897a9 --- /dev/null +++ b/esp32p4/src/efuse/rd_key1_data4.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY1_DATA4` reader"] +pub type R = crate::R; +#[doc = "Field `KEY1_DATA4` reader - Stores the fourth 32 bits of KEY1."] +pub type KEY1_DATA4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fourth 32 bits of KEY1."] + #[inline(always)] + pub fn key1_data4(&self) -> KEY1_DATA4_R { + KEY1_DATA4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY1_DATA4") + .field("key1_data4", &format_args!("{}", self.key1_data4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY1_DATA4_SPEC; +impl crate::RegisterSpec for RD_KEY1_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key1_data4::R`](R) reader structure"] +impl crate::Readable for RD_KEY1_DATA4_SPEC {} +#[doc = "`reset()` method sets RD_KEY1_DATA4 to value 0"] +impl crate::Resettable for RD_KEY1_DATA4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key1_data5.rs b/esp32p4/src/efuse/rd_key1_data5.rs new file mode 100644 index 0000000000..309bbb221d --- /dev/null +++ b/esp32p4/src/efuse/rd_key1_data5.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY1_DATA5` reader"] +pub type R = crate::R; +#[doc = "Field `KEY1_DATA5` reader - Stores the fifth 32 bits of KEY1."] +pub type KEY1_DATA5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fifth 32 bits of KEY1."] + #[inline(always)] + pub fn key1_data5(&self) -> KEY1_DATA5_R { + KEY1_DATA5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY1_DATA5") + .field("key1_data5", &format_args!("{}", self.key1_data5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY1_DATA5_SPEC; +impl crate::RegisterSpec for RD_KEY1_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key1_data5::R`](R) reader structure"] +impl crate::Readable for RD_KEY1_DATA5_SPEC {} +#[doc = "`reset()` method sets RD_KEY1_DATA5 to value 0"] +impl crate::Resettable for RD_KEY1_DATA5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key1_data6.rs b/esp32p4/src/efuse/rd_key1_data6.rs new file mode 100644 index 0000000000..889eb7770a --- /dev/null +++ b/esp32p4/src/efuse/rd_key1_data6.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY1_DATA6` reader"] +pub type R = crate::R; +#[doc = "Field `KEY1_DATA6` reader - Stores the sixth 32 bits of KEY1."] +pub type KEY1_DATA6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the sixth 32 bits of KEY1."] + #[inline(always)] + pub fn key1_data6(&self) -> KEY1_DATA6_R { + KEY1_DATA6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY1_DATA6") + .field("key1_data6", &format_args!("{}", self.key1_data6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY1_DATA6_SPEC; +impl crate::RegisterSpec for RD_KEY1_DATA6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key1_data6::R`](R) reader structure"] +impl crate::Readable for RD_KEY1_DATA6_SPEC {} +#[doc = "`reset()` method sets RD_KEY1_DATA6 to value 0"] +impl crate::Resettable for RD_KEY1_DATA6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key1_data7.rs b/esp32p4/src/efuse/rd_key1_data7.rs new file mode 100644 index 0000000000..4654d28e75 --- /dev/null +++ b/esp32p4/src/efuse/rd_key1_data7.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY1_DATA7` reader"] +pub type R = crate::R; +#[doc = "Field `KEY1_DATA7` reader - Stores the seventh 32 bits of KEY1."] +pub type KEY1_DATA7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the seventh 32 bits of KEY1."] + #[inline(always)] + pub fn key1_data7(&self) -> KEY1_DATA7_R { + KEY1_DATA7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY1_DATA7") + .field("key1_data7", &format_args!("{}", self.key1_data7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY1_DATA7_SPEC; +impl crate::RegisterSpec for RD_KEY1_DATA7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key1_data7::R`](R) reader structure"] +impl crate::Readable for RD_KEY1_DATA7_SPEC {} +#[doc = "`reset()` method sets RD_KEY1_DATA7 to value 0"] +impl crate::Resettable for RD_KEY1_DATA7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key2_data0.rs b/esp32p4/src/efuse/rd_key2_data0.rs new file mode 100644 index 0000000000..6a7c364c9d --- /dev/null +++ b/esp32p4/src/efuse/rd_key2_data0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY2_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `KEY2_DATA0` reader - Stores the zeroth 32 bits of KEY2."] +pub type KEY2_DATA0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the zeroth 32 bits of KEY2."] + #[inline(always)] + pub fn key2_data0(&self) -> KEY2_DATA0_R { + KEY2_DATA0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY2_DATA0") + .field("key2_data0", &format_args!("{}", self.key2_data0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY2_DATA0_SPEC; +impl crate::RegisterSpec for RD_KEY2_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key2_data0::R`](R) reader structure"] +impl crate::Readable for RD_KEY2_DATA0_SPEC {} +#[doc = "`reset()` method sets RD_KEY2_DATA0 to value 0"] +impl crate::Resettable for RD_KEY2_DATA0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key2_data1.rs b/esp32p4/src/efuse/rd_key2_data1.rs new file mode 100644 index 0000000000..6df3a0dc4d --- /dev/null +++ b/esp32p4/src/efuse/rd_key2_data1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY2_DATA1` reader"] +pub type R = crate::R; +#[doc = "Field `KEY2_DATA1` reader - Stores the first 32 bits of KEY2."] +pub type KEY2_DATA1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the first 32 bits of KEY2."] + #[inline(always)] + pub fn key2_data1(&self) -> KEY2_DATA1_R { + KEY2_DATA1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY2_DATA1") + .field("key2_data1", &format_args!("{}", self.key2_data1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY2_DATA1_SPEC; +impl crate::RegisterSpec for RD_KEY2_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key2_data1::R`](R) reader structure"] +impl crate::Readable for RD_KEY2_DATA1_SPEC {} +#[doc = "`reset()` method sets RD_KEY2_DATA1 to value 0"] +impl crate::Resettable for RD_KEY2_DATA1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key2_data2.rs b/esp32p4/src/efuse/rd_key2_data2.rs new file mode 100644 index 0000000000..2adb14c39f --- /dev/null +++ b/esp32p4/src/efuse/rd_key2_data2.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY2_DATA2` reader"] +pub type R = crate::R; +#[doc = "Field `KEY2_DATA2` reader - Stores the second 32 bits of KEY2."] +pub type KEY2_DATA2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the second 32 bits of KEY2."] + #[inline(always)] + pub fn key2_data2(&self) -> KEY2_DATA2_R { + KEY2_DATA2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY2_DATA2") + .field("key2_data2", &format_args!("{}", self.key2_data2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY2_DATA2_SPEC; +impl crate::RegisterSpec for RD_KEY2_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key2_data2::R`](R) reader structure"] +impl crate::Readable for RD_KEY2_DATA2_SPEC {} +#[doc = "`reset()` method sets RD_KEY2_DATA2 to value 0"] +impl crate::Resettable for RD_KEY2_DATA2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key2_data3.rs b/esp32p4/src/efuse/rd_key2_data3.rs new file mode 100644 index 0000000000..aa9830747d --- /dev/null +++ b/esp32p4/src/efuse/rd_key2_data3.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY2_DATA3` reader"] +pub type R = crate::R; +#[doc = "Field `KEY2_DATA3` reader - Stores the third 32 bits of KEY2."] +pub type KEY2_DATA3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the third 32 bits of KEY2."] + #[inline(always)] + pub fn key2_data3(&self) -> KEY2_DATA3_R { + KEY2_DATA3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY2_DATA3") + .field("key2_data3", &format_args!("{}", self.key2_data3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY2_DATA3_SPEC; +impl crate::RegisterSpec for RD_KEY2_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key2_data3::R`](R) reader structure"] +impl crate::Readable for RD_KEY2_DATA3_SPEC {} +#[doc = "`reset()` method sets RD_KEY2_DATA3 to value 0"] +impl crate::Resettable for RD_KEY2_DATA3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key2_data4.rs b/esp32p4/src/efuse/rd_key2_data4.rs new file mode 100644 index 0000000000..e6da2fc78e --- /dev/null +++ b/esp32p4/src/efuse/rd_key2_data4.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY2_DATA4` reader"] +pub type R = crate::R; +#[doc = "Field `KEY2_DATA4` reader - Stores the fourth 32 bits of KEY2."] +pub type KEY2_DATA4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fourth 32 bits of KEY2."] + #[inline(always)] + pub fn key2_data4(&self) -> KEY2_DATA4_R { + KEY2_DATA4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY2_DATA4") + .field("key2_data4", &format_args!("{}", self.key2_data4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY2_DATA4_SPEC; +impl crate::RegisterSpec for RD_KEY2_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key2_data4::R`](R) reader structure"] +impl crate::Readable for RD_KEY2_DATA4_SPEC {} +#[doc = "`reset()` method sets RD_KEY2_DATA4 to value 0"] +impl crate::Resettable for RD_KEY2_DATA4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key2_data5.rs b/esp32p4/src/efuse/rd_key2_data5.rs new file mode 100644 index 0000000000..871de5097c --- /dev/null +++ b/esp32p4/src/efuse/rd_key2_data5.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY2_DATA5` reader"] +pub type R = crate::R; +#[doc = "Field `KEY2_DATA5` reader - Stores the fifth 32 bits of KEY2."] +pub type KEY2_DATA5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fifth 32 bits of KEY2."] + #[inline(always)] + pub fn key2_data5(&self) -> KEY2_DATA5_R { + KEY2_DATA5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY2_DATA5") + .field("key2_data5", &format_args!("{}", self.key2_data5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY2_DATA5_SPEC; +impl crate::RegisterSpec for RD_KEY2_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key2_data5::R`](R) reader structure"] +impl crate::Readable for RD_KEY2_DATA5_SPEC {} +#[doc = "`reset()` method sets RD_KEY2_DATA5 to value 0"] +impl crate::Resettable for RD_KEY2_DATA5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key2_data6.rs b/esp32p4/src/efuse/rd_key2_data6.rs new file mode 100644 index 0000000000..80e2f6b19f --- /dev/null +++ b/esp32p4/src/efuse/rd_key2_data6.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY2_DATA6` reader"] +pub type R = crate::R; +#[doc = "Field `KEY2_DATA6` reader - Stores the sixth 32 bits of KEY2."] +pub type KEY2_DATA6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the sixth 32 bits of KEY2."] + #[inline(always)] + pub fn key2_data6(&self) -> KEY2_DATA6_R { + KEY2_DATA6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY2_DATA6") + .field("key2_data6", &format_args!("{}", self.key2_data6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY2_DATA6_SPEC; +impl crate::RegisterSpec for RD_KEY2_DATA6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key2_data6::R`](R) reader structure"] +impl crate::Readable for RD_KEY2_DATA6_SPEC {} +#[doc = "`reset()` method sets RD_KEY2_DATA6 to value 0"] +impl crate::Resettable for RD_KEY2_DATA6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key2_data7.rs b/esp32p4/src/efuse/rd_key2_data7.rs new file mode 100644 index 0000000000..c54ec20dba --- /dev/null +++ b/esp32p4/src/efuse/rd_key2_data7.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY2_DATA7` reader"] +pub type R = crate::R; +#[doc = "Field `KEY2_DATA7` reader - Stores the seventh 32 bits of KEY2."] +pub type KEY2_DATA7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the seventh 32 bits of KEY2."] + #[inline(always)] + pub fn key2_data7(&self) -> KEY2_DATA7_R { + KEY2_DATA7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY2_DATA7") + .field("key2_data7", &format_args!("{}", self.key2_data7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY2_DATA7_SPEC; +impl crate::RegisterSpec for RD_KEY2_DATA7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key2_data7::R`](R) reader structure"] +impl crate::Readable for RD_KEY2_DATA7_SPEC {} +#[doc = "`reset()` method sets RD_KEY2_DATA7 to value 0"] +impl crate::Resettable for RD_KEY2_DATA7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key3_data0.rs b/esp32p4/src/efuse/rd_key3_data0.rs new file mode 100644 index 0000000000..d94bc3633c --- /dev/null +++ b/esp32p4/src/efuse/rd_key3_data0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY3_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `KEY3_DATA0` reader - Stores the zeroth 32 bits of KEY3."] +pub type KEY3_DATA0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the zeroth 32 bits of KEY3."] + #[inline(always)] + pub fn key3_data0(&self) -> KEY3_DATA0_R { + KEY3_DATA0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY3_DATA0") + .field("key3_data0", &format_args!("{}", self.key3_data0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY3_DATA0_SPEC; +impl crate::RegisterSpec for RD_KEY3_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key3_data0::R`](R) reader structure"] +impl crate::Readable for RD_KEY3_DATA0_SPEC {} +#[doc = "`reset()` method sets RD_KEY3_DATA0 to value 0"] +impl crate::Resettable for RD_KEY3_DATA0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key3_data1.rs b/esp32p4/src/efuse/rd_key3_data1.rs new file mode 100644 index 0000000000..0c6f452b88 --- /dev/null +++ b/esp32p4/src/efuse/rd_key3_data1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY3_DATA1` reader"] +pub type R = crate::R; +#[doc = "Field `KEY3_DATA1` reader - Stores the first 32 bits of KEY3."] +pub type KEY3_DATA1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the first 32 bits of KEY3."] + #[inline(always)] + pub fn key3_data1(&self) -> KEY3_DATA1_R { + KEY3_DATA1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY3_DATA1") + .field("key3_data1", &format_args!("{}", self.key3_data1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY3_DATA1_SPEC; +impl crate::RegisterSpec for RD_KEY3_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key3_data1::R`](R) reader structure"] +impl crate::Readable for RD_KEY3_DATA1_SPEC {} +#[doc = "`reset()` method sets RD_KEY3_DATA1 to value 0"] +impl crate::Resettable for RD_KEY3_DATA1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key3_data2.rs b/esp32p4/src/efuse/rd_key3_data2.rs new file mode 100644 index 0000000000..56a1485b1e --- /dev/null +++ b/esp32p4/src/efuse/rd_key3_data2.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY3_DATA2` reader"] +pub type R = crate::R; +#[doc = "Field `KEY3_DATA2` reader - Stores the second 32 bits of KEY3."] +pub type KEY3_DATA2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the second 32 bits of KEY3."] + #[inline(always)] + pub fn key3_data2(&self) -> KEY3_DATA2_R { + KEY3_DATA2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY3_DATA2") + .field("key3_data2", &format_args!("{}", self.key3_data2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY3_DATA2_SPEC; +impl crate::RegisterSpec for RD_KEY3_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key3_data2::R`](R) reader structure"] +impl crate::Readable for RD_KEY3_DATA2_SPEC {} +#[doc = "`reset()` method sets RD_KEY3_DATA2 to value 0"] +impl crate::Resettable for RD_KEY3_DATA2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key3_data3.rs b/esp32p4/src/efuse/rd_key3_data3.rs new file mode 100644 index 0000000000..f1be9d0bf3 --- /dev/null +++ b/esp32p4/src/efuse/rd_key3_data3.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY3_DATA3` reader"] +pub type R = crate::R; +#[doc = "Field `KEY3_DATA3` reader - Stores the third 32 bits of KEY3."] +pub type KEY3_DATA3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the third 32 bits of KEY3."] + #[inline(always)] + pub fn key3_data3(&self) -> KEY3_DATA3_R { + KEY3_DATA3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY3_DATA3") + .field("key3_data3", &format_args!("{}", self.key3_data3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY3_DATA3_SPEC; +impl crate::RegisterSpec for RD_KEY3_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key3_data3::R`](R) reader structure"] +impl crate::Readable for RD_KEY3_DATA3_SPEC {} +#[doc = "`reset()` method sets RD_KEY3_DATA3 to value 0"] +impl crate::Resettable for RD_KEY3_DATA3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key3_data4.rs b/esp32p4/src/efuse/rd_key3_data4.rs new file mode 100644 index 0000000000..477a4e3a0c --- /dev/null +++ b/esp32p4/src/efuse/rd_key3_data4.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY3_DATA4` reader"] +pub type R = crate::R; +#[doc = "Field `KEY3_DATA4` reader - Stores the fourth 32 bits of KEY3."] +pub type KEY3_DATA4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fourth 32 bits of KEY3."] + #[inline(always)] + pub fn key3_data4(&self) -> KEY3_DATA4_R { + KEY3_DATA4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY3_DATA4") + .field("key3_data4", &format_args!("{}", self.key3_data4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY3_DATA4_SPEC; +impl crate::RegisterSpec for RD_KEY3_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key3_data4::R`](R) reader structure"] +impl crate::Readable for RD_KEY3_DATA4_SPEC {} +#[doc = "`reset()` method sets RD_KEY3_DATA4 to value 0"] +impl crate::Resettable for RD_KEY3_DATA4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key3_data5.rs b/esp32p4/src/efuse/rd_key3_data5.rs new file mode 100644 index 0000000000..d617168e22 --- /dev/null +++ b/esp32p4/src/efuse/rd_key3_data5.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY3_DATA5` reader"] +pub type R = crate::R; +#[doc = "Field `KEY3_DATA5` reader - Stores the fifth 32 bits of KEY3."] +pub type KEY3_DATA5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fifth 32 bits of KEY3."] + #[inline(always)] + pub fn key3_data5(&self) -> KEY3_DATA5_R { + KEY3_DATA5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY3_DATA5") + .field("key3_data5", &format_args!("{}", self.key3_data5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY3_DATA5_SPEC; +impl crate::RegisterSpec for RD_KEY3_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key3_data5::R`](R) reader structure"] +impl crate::Readable for RD_KEY3_DATA5_SPEC {} +#[doc = "`reset()` method sets RD_KEY3_DATA5 to value 0"] +impl crate::Resettable for RD_KEY3_DATA5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key3_data6.rs b/esp32p4/src/efuse/rd_key3_data6.rs new file mode 100644 index 0000000000..369b965db3 --- /dev/null +++ b/esp32p4/src/efuse/rd_key3_data6.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY3_DATA6` reader"] +pub type R = crate::R; +#[doc = "Field `KEY3_DATA6` reader - Stores the sixth 32 bits of KEY3."] +pub type KEY3_DATA6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the sixth 32 bits of KEY3."] + #[inline(always)] + pub fn key3_data6(&self) -> KEY3_DATA6_R { + KEY3_DATA6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY3_DATA6") + .field("key3_data6", &format_args!("{}", self.key3_data6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY3_DATA6_SPEC; +impl crate::RegisterSpec for RD_KEY3_DATA6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key3_data6::R`](R) reader structure"] +impl crate::Readable for RD_KEY3_DATA6_SPEC {} +#[doc = "`reset()` method sets RD_KEY3_DATA6 to value 0"] +impl crate::Resettable for RD_KEY3_DATA6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key3_data7.rs b/esp32p4/src/efuse/rd_key3_data7.rs new file mode 100644 index 0000000000..c55db8372c --- /dev/null +++ b/esp32p4/src/efuse/rd_key3_data7.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY3_DATA7` reader"] +pub type R = crate::R; +#[doc = "Field `KEY3_DATA7` reader - Stores the seventh 32 bits of KEY3."] +pub type KEY3_DATA7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the seventh 32 bits of KEY3."] + #[inline(always)] + pub fn key3_data7(&self) -> KEY3_DATA7_R { + KEY3_DATA7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY3_DATA7") + .field("key3_data7", &format_args!("{}", self.key3_data7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY3_DATA7_SPEC; +impl crate::RegisterSpec for RD_KEY3_DATA7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key3_data7::R`](R) reader structure"] +impl crate::Readable for RD_KEY3_DATA7_SPEC {} +#[doc = "`reset()` method sets RD_KEY3_DATA7 to value 0"] +impl crate::Resettable for RD_KEY3_DATA7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key4_data0.rs b/esp32p4/src/efuse/rd_key4_data0.rs new file mode 100644 index 0000000000..dcaf11a5b6 --- /dev/null +++ b/esp32p4/src/efuse/rd_key4_data0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY4_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `KEY4_DATA0` reader - Stores the zeroth 32 bits of KEY4."] +pub type KEY4_DATA0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the zeroth 32 bits of KEY4."] + #[inline(always)] + pub fn key4_data0(&self) -> KEY4_DATA0_R { + KEY4_DATA0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY4_DATA0") + .field("key4_data0", &format_args!("{}", self.key4_data0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY4_DATA0_SPEC; +impl crate::RegisterSpec for RD_KEY4_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key4_data0::R`](R) reader structure"] +impl crate::Readable for RD_KEY4_DATA0_SPEC {} +#[doc = "`reset()` method sets RD_KEY4_DATA0 to value 0"] +impl crate::Resettable for RD_KEY4_DATA0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key4_data1.rs b/esp32p4/src/efuse/rd_key4_data1.rs new file mode 100644 index 0000000000..4b6fbff208 --- /dev/null +++ b/esp32p4/src/efuse/rd_key4_data1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY4_DATA1` reader"] +pub type R = crate::R; +#[doc = "Field `KEY4_DATA1` reader - Stores the first 32 bits of KEY4."] +pub type KEY4_DATA1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the first 32 bits of KEY4."] + #[inline(always)] + pub fn key4_data1(&self) -> KEY4_DATA1_R { + KEY4_DATA1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY4_DATA1") + .field("key4_data1", &format_args!("{}", self.key4_data1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY4_DATA1_SPEC; +impl crate::RegisterSpec for RD_KEY4_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key4_data1::R`](R) reader structure"] +impl crate::Readable for RD_KEY4_DATA1_SPEC {} +#[doc = "`reset()` method sets RD_KEY4_DATA1 to value 0"] +impl crate::Resettable for RD_KEY4_DATA1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key4_data2.rs b/esp32p4/src/efuse/rd_key4_data2.rs new file mode 100644 index 0000000000..80a54f300c --- /dev/null +++ b/esp32p4/src/efuse/rd_key4_data2.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY4_DATA2` reader"] +pub type R = crate::R; +#[doc = "Field `KEY4_DATA2` reader - Stores the second 32 bits of KEY4."] +pub type KEY4_DATA2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the second 32 bits of KEY4."] + #[inline(always)] + pub fn key4_data2(&self) -> KEY4_DATA2_R { + KEY4_DATA2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY4_DATA2") + .field("key4_data2", &format_args!("{}", self.key4_data2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY4_DATA2_SPEC; +impl crate::RegisterSpec for RD_KEY4_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key4_data2::R`](R) reader structure"] +impl crate::Readable for RD_KEY4_DATA2_SPEC {} +#[doc = "`reset()` method sets RD_KEY4_DATA2 to value 0"] +impl crate::Resettable for RD_KEY4_DATA2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key4_data3.rs b/esp32p4/src/efuse/rd_key4_data3.rs new file mode 100644 index 0000000000..bfdd3211c9 --- /dev/null +++ b/esp32p4/src/efuse/rd_key4_data3.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY4_DATA3` reader"] +pub type R = crate::R; +#[doc = "Field `KEY4_DATA3` reader - Stores the third 32 bits of KEY4."] +pub type KEY4_DATA3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the third 32 bits of KEY4."] + #[inline(always)] + pub fn key4_data3(&self) -> KEY4_DATA3_R { + KEY4_DATA3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY4_DATA3") + .field("key4_data3", &format_args!("{}", self.key4_data3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY4_DATA3_SPEC; +impl crate::RegisterSpec for RD_KEY4_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key4_data3::R`](R) reader structure"] +impl crate::Readable for RD_KEY4_DATA3_SPEC {} +#[doc = "`reset()` method sets RD_KEY4_DATA3 to value 0"] +impl crate::Resettable for RD_KEY4_DATA3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key4_data4.rs b/esp32p4/src/efuse/rd_key4_data4.rs new file mode 100644 index 0000000000..db709621bf --- /dev/null +++ b/esp32p4/src/efuse/rd_key4_data4.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY4_DATA4` reader"] +pub type R = crate::R; +#[doc = "Field `KEY4_DATA4` reader - Stores the fourth 32 bits of KEY4."] +pub type KEY4_DATA4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fourth 32 bits of KEY4."] + #[inline(always)] + pub fn key4_data4(&self) -> KEY4_DATA4_R { + KEY4_DATA4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY4_DATA4") + .field("key4_data4", &format_args!("{}", self.key4_data4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY4_DATA4_SPEC; +impl crate::RegisterSpec for RD_KEY4_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key4_data4::R`](R) reader structure"] +impl crate::Readable for RD_KEY4_DATA4_SPEC {} +#[doc = "`reset()` method sets RD_KEY4_DATA4 to value 0"] +impl crate::Resettable for RD_KEY4_DATA4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key4_data5.rs b/esp32p4/src/efuse/rd_key4_data5.rs new file mode 100644 index 0000000000..4181abf38d --- /dev/null +++ b/esp32p4/src/efuse/rd_key4_data5.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY4_DATA5` reader"] +pub type R = crate::R; +#[doc = "Field `KEY4_DATA5` reader - Stores the fifth 32 bits of KEY4."] +pub type KEY4_DATA5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fifth 32 bits of KEY4."] + #[inline(always)] + pub fn key4_data5(&self) -> KEY4_DATA5_R { + KEY4_DATA5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY4_DATA5") + .field("key4_data5", &format_args!("{}", self.key4_data5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY4_DATA5_SPEC; +impl crate::RegisterSpec for RD_KEY4_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key4_data5::R`](R) reader structure"] +impl crate::Readable for RD_KEY4_DATA5_SPEC {} +#[doc = "`reset()` method sets RD_KEY4_DATA5 to value 0"] +impl crate::Resettable for RD_KEY4_DATA5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key4_data6.rs b/esp32p4/src/efuse/rd_key4_data6.rs new file mode 100644 index 0000000000..82ce3f505c --- /dev/null +++ b/esp32p4/src/efuse/rd_key4_data6.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY4_DATA6` reader"] +pub type R = crate::R; +#[doc = "Field `KEY4_DATA6` reader - Stores the sixth 32 bits of KEY4."] +pub type KEY4_DATA6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the sixth 32 bits of KEY4."] + #[inline(always)] + pub fn key4_data6(&self) -> KEY4_DATA6_R { + KEY4_DATA6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY4_DATA6") + .field("key4_data6", &format_args!("{}", self.key4_data6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY4_DATA6_SPEC; +impl crate::RegisterSpec for RD_KEY4_DATA6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key4_data6::R`](R) reader structure"] +impl crate::Readable for RD_KEY4_DATA6_SPEC {} +#[doc = "`reset()` method sets RD_KEY4_DATA6 to value 0"] +impl crate::Resettable for RD_KEY4_DATA6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key4_data7.rs b/esp32p4/src/efuse/rd_key4_data7.rs new file mode 100644 index 0000000000..0b82288456 --- /dev/null +++ b/esp32p4/src/efuse/rd_key4_data7.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY4_DATA7` reader"] +pub type R = crate::R; +#[doc = "Field `KEY4_DATA7` reader - Stores the seventh 32 bits of KEY4."] +pub type KEY4_DATA7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the seventh 32 bits of KEY4."] + #[inline(always)] + pub fn key4_data7(&self) -> KEY4_DATA7_R { + KEY4_DATA7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY4_DATA7") + .field("key4_data7", &format_args!("{}", self.key4_data7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY4_DATA7_SPEC; +impl crate::RegisterSpec for RD_KEY4_DATA7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key4_data7::R`](R) reader structure"] +impl crate::Readable for RD_KEY4_DATA7_SPEC {} +#[doc = "`reset()` method sets RD_KEY4_DATA7 to value 0"] +impl crate::Resettable for RD_KEY4_DATA7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key5_data0.rs b/esp32p4/src/efuse/rd_key5_data0.rs new file mode 100644 index 0000000000..434c85c08d --- /dev/null +++ b/esp32p4/src/efuse/rd_key5_data0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY5_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `KEY5_DATA0` reader - Stores the zeroth 32 bits of KEY5."] +pub type KEY5_DATA0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the zeroth 32 bits of KEY5."] + #[inline(always)] + pub fn key5_data0(&self) -> KEY5_DATA0_R { + KEY5_DATA0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY5_DATA0") + .field("key5_data0", &format_args!("{}", self.key5_data0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY5_DATA0_SPEC; +impl crate::RegisterSpec for RD_KEY5_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key5_data0::R`](R) reader structure"] +impl crate::Readable for RD_KEY5_DATA0_SPEC {} +#[doc = "`reset()` method sets RD_KEY5_DATA0 to value 0"] +impl crate::Resettable for RD_KEY5_DATA0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key5_data1.rs b/esp32p4/src/efuse/rd_key5_data1.rs new file mode 100644 index 0000000000..2e5fb4c55b --- /dev/null +++ b/esp32p4/src/efuse/rd_key5_data1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY5_DATA1` reader"] +pub type R = crate::R; +#[doc = "Field `KEY5_DATA1` reader - Stores the first 32 bits of KEY5."] +pub type KEY5_DATA1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the first 32 bits of KEY5."] + #[inline(always)] + pub fn key5_data1(&self) -> KEY5_DATA1_R { + KEY5_DATA1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY5_DATA1") + .field("key5_data1", &format_args!("{}", self.key5_data1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY5_DATA1_SPEC; +impl crate::RegisterSpec for RD_KEY5_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key5_data1::R`](R) reader structure"] +impl crate::Readable for RD_KEY5_DATA1_SPEC {} +#[doc = "`reset()` method sets RD_KEY5_DATA1 to value 0"] +impl crate::Resettable for RD_KEY5_DATA1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key5_data2.rs b/esp32p4/src/efuse/rd_key5_data2.rs new file mode 100644 index 0000000000..e2ecdc6862 --- /dev/null +++ b/esp32p4/src/efuse/rd_key5_data2.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY5_DATA2` reader"] +pub type R = crate::R; +#[doc = "Field `KEY5_DATA2` reader - Stores the second 32 bits of KEY5."] +pub type KEY5_DATA2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the second 32 bits of KEY5."] + #[inline(always)] + pub fn key5_data2(&self) -> KEY5_DATA2_R { + KEY5_DATA2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY5_DATA2") + .field("key5_data2", &format_args!("{}", self.key5_data2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY5_DATA2_SPEC; +impl crate::RegisterSpec for RD_KEY5_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key5_data2::R`](R) reader structure"] +impl crate::Readable for RD_KEY5_DATA2_SPEC {} +#[doc = "`reset()` method sets RD_KEY5_DATA2 to value 0"] +impl crate::Resettable for RD_KEY5_DATA2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key5_data3.rs b/esp32p4/src/efuse/rd_key5_data3.rs new file mode 100644 index 0000000000..426b55868a --- /dev/null +++ b/esp32p4/src/efuse/rd_key5_data3.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY5_DATA3` reader"] +pub type R = crate::R; +#[doc = "Field `KEY5_DATA3` reader - Stores the third 32 bits of KEY5."] +pub type KEY5_DATA3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the third 32 bits of KEY5."] + #[inline(always)] + pub fn key5_data3(&self) -> KEY5_DATA3_R { + KEY5_DATA3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY5_DATA3") + .field("key5_data3", &format_args!("{}", self.key5_data3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY5_DATA3_SPEC; +impl crate::RegisterSpec for RD_KEY5_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key5_data3::R`](R) reader structure"] +impl crate::Readable for RD_KEY5_DATA3_SPEC {} +#[doc = "`reset()` method sets RD_KEY5_DATA3 to value 0"] +impl crate::Resettable for RD_KEY5_DATA3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key5_data4.rs b/esp32p4/src/efuse/rd_key5_data4.rs new file mode 100644 index 0000000000..0632f2cadf --- /dev/null +++ b/esp32p4/src/efuse/rd_key5_data4.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY5_DATA4` reader"] +pub type R = crate::R; +#[doc = "Field `KEY5_DATA4` reader - Stores the fourth 32 bits of KEY5."] +pub type KEY5_DATA4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fourth 32 bits of KEY5."] + #[inline(always)] + pub fn key5_data4(&self) -> KEY5_DATA4_R { + KEY5_DATA4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY5_DATA4") + .field("key5_data4", &format_args!("{}", self.key5_data4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY5_DATA4_SPEC; +impl crate::RegisterSpec for RD_KEY5_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key5_data4::R`](R) reader structure"] +impl crate::Readable for RD_KEY5_DATA4_SPEC {} +#[doc = "`reset()` method sets RD_KEY5_DATA4 to value 0"] +impl crate::Resettable for RD_KEY5_DATA4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key5_data5.rs b/esp32p4/src/efuse/rd_key5_data5.rs new file mode 100644 index 0000000000..6795d484d4 --- /dev/null +++ b/esp32p4/src/efuse/rd_key5_data5.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY5_DATA5` reader"] +pub type R = crate::R; +#[doc = "Field `KEY5_DATA5` reader - Stores the fifth 32 bits of KEY5."] +pub type KEY5_DATA5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fifth 32 bits of KEY5."] + #[inline(always)] + pub fn key5_data5(&self) -> KEY5_DATA5_R { + KEY5_DATA5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY5_DATA5") + .field("key5_data5", &format_args!("{}", self.key5_data5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY5_DATA5_SPEC; +impl crate::RegisterSpec for RD_KEY5_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key5_data5::R`](R) reader structure"] +impl crate::Readable for RD_KEY5_DATA5_SPEC {} +#[doc = "`reset()` method sets RD_KEY5_DATA5 to value 0"] +impl crate::Resettable for RD_KEY5_DATA5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key5_data6.rs b/esp32p4/src/efuse/rd_key5_data6.rs new file mode 100644 index 0000000000..ee83bd41ca --- /dev/null +++ b/esp32p4/src/efuse/rd_key5_data6.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY5_DATA6` reader"] +pub type R = crate::R; +#[doc = "Field `KEY5_DATA6` reader - Stores the sixth 32 bits of KEY5."] +pub type KEY5_DATA6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the sixth 32 bits of KEY5."] + #[inline(always)] + pub fn key5_data6(&self) -> KEY5_DATA6_R { + KEY5_DATA6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY5_DATA6") + .field("key5_data6", &format_args!("{}", self.key5_data6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY5_DATA6_SPEC; +impl crate::RegisterSpec for RD_KEY5_DATA6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key5_data6::R`](R) reader structure"] +impl crate::Readable for RD_KEY5_DATA6_SPEC {} +#[doc = "`reset()` method sets RD_KEY5_DATA6 to value 0"] +impl crate::Resettable for RD_KEY5_DATA6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_key5_data7.rs b/esp32p4/src/efuse/rd_key5_data7.rs new file mode 100644 index 0000000000..2ac22b6ae8 --- /dev/null +++ b/esp32p4/src/efuse/rd_key5_data7.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_KEY5_DATA7` reader"] +pub type R = crate::R; +#[doc = "Field `KEY5_DATA7` reader - Stores the seventh 32 bits of KEY5."] +pub type KEY5_DATA7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the seventh 32 bits of KEY5."] + #[inline(always)] + pub fn key5_data7(&self) -> KEY5_DATA7_R { + KEY5_DATA7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_KEY5_DATA7") + .field("key5_data7", &format_args!("{}", self.key5_data7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_KEY5_DATA7_SPEC; +impl crate::RegisterSpec for RD_KEY5_DATA7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_key5_data7::R`](R) reader structure"] +impl crate::Readable for RD_KEY5_DATA7_SPEC {} +#[doc = "`reset()` method sets RD_KEY5_DATA7 to value 0"] +impl crate::Resettable for RD_KEY5_DATA7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_mac_sys_0.rs b/esp32p4/src/efuse/rd_mac_sys_0.rs new file mode 100644 index 0000000000..88c9a0cedd --- /dev/null +++ b/esp32p4/src/efuse/rd_mac_sys_0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_MAC_SYS_0` reader"] +pub type R = crate::R; +#[doc = "Field `MAC_0` reader - Stores the low 32 bits of MAC address."] +pub type MAC_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the low 32 bits of MAC address."] + #[inline(always)] + pub fn mac_0(&self) -> MAC_0_R { + MAC_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_MAC_SYS_0") + .field("mac_0", &format_args!("{}", self.mac_0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_MAC_SYS_0_SPEC; +impl crate::RegisterSpec for RD_MAC_SYS_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_mac_sys_0::R`](R) reader structure"] +impl crate::Readable for RD_MAC_SYS_0_SPEC {} +#[doc = "`reset()` method sets RD_MAC_SYS_0 to value 0"] +impl crate::Resettable for RD_MAC_SYS_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_mac_sys_1.rs b/esp32p4/src/efuse/rd_mac_sys_1.rs new file mode 100644 index 0000000000..da97f3b63a --- /dev/null +++ b/esp32p4/src/efuse/rd_mac_sys_1.rs @@ -0,0 +1,44 @@ +#[doc = "Register `RD_MAC_SYS_1` reader"] +pub type R = crate::R; +#[doc = "Field `MAC_1` reader - Stores the high 16 bits of MAC address."] +pub type MAC_1_R = crate::FieldReader; +#[doc = "Field `MAC_EXT` reader - Stores the extended bits of MAC address."] +pub type MAC_EXT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Stores the high 16 bits of MAC address."] + #[inline(always)] + pub fn mac_1(&self) -> MAC_1_R { + MAC_1_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Stores the extended bits of MAC address."] + #[inline(always)] + pub fn mac_ext(&self) -> MAC_EXT_R { + MAC_EXT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_MAC_SYS_1") + .field("mac_1", &format_args!("{}", self.mac_1().bits())) + .field("mac_ext", &format_args!("{}", self.mac_ext().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_MAC_SYS_1_SPEC; +impl crate::RegisterSpec for RD_MAC_SYS_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_mac_sys_1::R`](R) reader structure"] +impl crate::Readable for RD_MAC_SYS_1_SPEC {} +#[doc = "`reset()` method sets RD_MAC_SYS_1 to value 0"] +impl crate::Resettable for RD_MAC_SYS_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_mac_sys_2.rs b/esp32p4/src/efuse/rd_mac_sys_2.rs new file mode 100644 index 0000000000..19a26edf22 --- /dev/null +++ b/esp32p4/src/efuse/rd_mac_sys_2.rs @@ -0,0 +1,50 @@ +#[doc = "Register `RD_MAC_SYS_2` reader"] +pub type R = crate::R; +#[doc = "Field `MAC_RESERVED_1` reader - Reserved."] +pub type MAC_RESERVED_1_R = crate::FieldReader; +#[doc = "Field `MAC_RESERVED_0` reader - Reserved."] +pub type MAC_RESERVED_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:13 - Reserved."] + #[inline(always)] + pub fn mac_reserved_1(&self) -> MAC_RESERVED_1_R { + MAC_RESERVED_1_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 14:31 - Reserved."] + #[inline(always)] + pub fn mac_reserved_0(&self) -> MAC_RESERVED_0_R { + MAC_RESERVED_0_R::new((self.bits >> 14) & 0x0003_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_MAC_SYS_2") + .field( + "mac_reserved_1", + &format_args!("{}", self.mac_reserved_1().bits()), + ) + .field( + "mac_reserved_0", + &format_args!("{}", self.mac_reserved_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_MAC_SYS_2_SPEC; +impl crate::RegisterSpec for RD_MAC_SYS_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_mac_sys_2::R`](R) reader structure"] +impl crate::Readable for RD_MAC_SYS_2_SPEC {} +#[doc = "`reset()` method sets RD_MAC_SYS_2 to value 0"] +impl crate::Resettable for RD_MAC_SYS_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_mac_sys_3.rs b/esp32p4/src/efuse/rd_mac_sys_3.rs new file mode 100644 index 0000000000..39134b40ea --- /dev/null +++ b/esp32p4/src/efuse/rd_mac_sys_3.rs @@ -0,0 +1,50 @@ +#[doc = "Register `RD_MAC_SYS_3` reader"] +pub type R = crate::R; +#[doc = "Field `MAC_RESERVED_2` reader - Reserved."] +pub type MAC_RESERVED_2_R = crate::FieldReader; +#[doc = "Field `SYS_DATA_PART0_0` reader - Stores the first 14 bits of the zeroth part of system data."] +pub type SYS_DATA_PART0_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:17 - Reserved."] + #[inline(always)] + pub fn mac_reserved_2(&self) -> MAC_RESERVED_2_R { + MAC_RESERVED_2_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:31 - Stores the first 14 bits of the zeroth part of system data."] + #[inline(always)] + pub fn sys_data_part0_0(&self) -> SYS_DATA_PART0_0_R { + SYS_DATA_PART0_0_R::new(((self.bits >> 18) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_MAC_SYS_3") + .field( + "mac_reserved_2", + &format_args!("{}", self.mac_reserved_2().bits()), + ) + .field( + "sys_data_part0_0", + &format_args!("{}", self.sys_data_part0_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_MAC_SYS_3_SPEC; +impl crate::RegisterSpec for RD_MAC_SYS_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_mac_sys_3::R`](R) reader structure"] +impl crate::Readable for RD_MAC_SYS_3_SPEC {} +#[doc = "`reset()` method sets RD_MAC_SYS_3 to value 0"] +impl crate::Resettable for RD_MAC_SYS_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_mac_sys_4.rs b/esp32p4/src/efuse/rd_mac_sys_4.rs new file mode 100644 index 0000000000..5de8741466 --- /dev/null +++ b/esp32p4/src/efuse/rd_mac_sys_4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_MAC_SYS_4` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART0_1` reader - Stores the first 32 bits of the zeroth part of system data."] +pub type SYS_DATA_PART0_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the first 32 bits of the zeroth part of system data."] + #[inline(always)] + pub fn sys_data_part0_1(&self) -> SYS_DATA_PART0_1_R { + SYS_DATA_PART0_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_MAC_SYS_4") + .field( + "sys_data_part0_1", + &format_args!("{}", self.sys_data_part0_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_MAC_SYS_4_SPEC; +impl crate::RegisterSpec for RD_MAC_SYS_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_mac_sys_4::R`](R) reader structure"] +impl crate::Readable for RD_MAC_SYS_4_SPEC {} +#[doc = "`reset()` method sets RD_MAC_SYS_4 to value 0"] +impl crate::Resettable for RD_MAC_SYS_4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_mac_sys_5.rs b/esp32p4/src/efuse/rd_mac_sys_5.rs new file mode 100644 index 0000000000..ebe9fffcd5 --- /dev/null +++ b/esp32p4/src/efuse/rd_mac_sys_5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_MAC_SYS_5` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART0_2` reader - Stores the second 32 bits of the zeroth part of system data."] +pub type SYS_DATA_PART0_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the second 32 bits of the zeroth part of system data."] + #[inline(always)] + pub fn sys_data_part0_2(&self) -> SYS_DATA_PART0_2_R { + SYS_DATA_PART0_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_MAC_SYS_5") + .field( + "sys_data_part0_2", + &format_args!("{}", self.sys_data_part0_2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_MAC_SYS_5_SPEC; +impl crate::RegisterSpec for RD_MAC_SYS_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_mac_sys_5::R`](R) reader structure"] +impl crate::Readable for RD_MAC_SYS_5_SPEC {} +#[doc = "`reset()` method sets RD_MAC_SYS_5 to value 0"] +impl crate::Resettable for RD_MAC_SYS_5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_repeat_data0.rs b/esp32p4/src/efuse/rd_repeat_data0.rs new file mode 100644 index 0000000000..814ac1c083 --- /dev/null +++ b/esp32p4/src/efuse/rd_repeat_data0.rs @@ -0,0 +1,206 @@ +#[doc = "Register `RD_REPEAT_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `RD_DIS` reader - Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled."] +pub type RD_DIS_R = crate::FieldReader; +#[doc = "Field `USB_DEVICE_EXCHG_PINS` reader - Enable usb device exchange pins of D+ and D-."] +pub type USB_DEVICE_EXCHG_PINS_R = crate::BitReader; +#[doc = "Field `USB_OTG11_EXCHG_PINS` reader - Enable usb otg11 exchange pins of D+ and D-."] +pub type USB_OTG11_EXCHG_PINS_R = crate::BitReader; +#[doc = "Field `DIS_USB_JTAG` reader - Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled."] +pub type DIS_USB_JTAG_R = crate::BitReader; +#[doc = "Field `POWERGLITCH_EN` reader - Represents whether power glitch function is enabled. 1: enabled. 0: disabled."] +pub type POWERGLITCH_EN_R = crate::BitReader; +#[doc = "Field `DIS_USB_SERIAL_JTAG` reader - Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled."] +pub type DIS_USB_SERIAL_JTAG_R = crate::BitReader; +#[doc = "Field `DIS_FORCE_DOWNLOAD` reader - Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled."] +pub type DIS_FORCE_DOWNLOAD_R = crate::BitReader; +#[doc = "Field `SPI_DOWNLOAD_MSPI_DIS` reader - Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download."] +pub type SPI_DOWNLOAD_MSPI_DIS_R = crate::BitReader; +#[doc = "Field `DIS_TWAI` reader - Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled."] +pub type DIS_TWAI_R = crate::BitReader; +#[doc = "Field `JTAG_SEL_ENABLE` reader - Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled."] +pub type JTAG_SEL_ENABLE_R = crate::BitReader; +#[doc = "Field `SOFT_DIS_JTAG` reader - Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled."] +pub type SOFT_DIS_JTAG_R = crate::FieldReader; +#[doc = "Field `DIS_PAD_JTAG` reader - Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled."] +pub type DIS_PAD_JTAG_R = crate::BitReader; +#[doc = "Field `DIS_DOWNLOAD_MANUAL_ENCRYPT` reader - Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled."] +pub type DIS_DOWNLOAD_MANUAL_ENCRYPT_R = crate::BitReader; +#[doc = "Field `USB_DEVICE_DREFH` reader - USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV"] +pub type USB_DEVICE_DREFH_R = crate::FieldReader; +#[doc = "Field `USB_OTG11_DREFH` reader - USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV"] +pub type USB_OTG11_DREFH_R = crate::FieldReader; +#[doc = "Field `USB_PHY_SEL` reader - TBD"] +pub type USB_PHY_SEL_R = crate::BitReader; +#[doc = "Field `KM_HUK_GEN_STATE_LOW` reader - Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid."] +pub type KM_HUK_GEN_STATE_LOW_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:6 - Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled."] + #[inline(always)] + pub fn rd_dis(&self) -> RD_DIS_R { + RD_DIS_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Enable usb device exchange pins of D+ and D-."] + #[inline(always)] + pub fn usb_device_exchg_pins(&self) -> USB_DEVICE_EXCHG_PINS_R { + USB_DEVICE_EXCHG_PINS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable usb otg11 exchange pins of D+ and D-."] + #[inline(always)] + pub fn usb_otg11_exchg_pins(&self) -> USB_OTG11_EXCHG_PINS_R { + USB_OTG11_EXCHG_PINS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled."] + #[inline(always)] + pub fn dis_usb_jtag(&self) -> DIS_USB_JTAG_R { + DIS_USB_JTAG_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents whether power glitch function is enabled. 1: enabled. 0: disabled."] + #[inline(always)] + pub fn powerglitch_en(&self) -> POWERGLITCH_EN_R { + POWERGLITCH_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled."] + #[inline(always)] + pub fn dis_usb_serial_jtag(&self) -> DIS_USB_SERIAL_JTAG_R { + DIS_USB_SERIAL_JTAG_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled."] + #[inline(always)] + pub fn dis_force_download(&self) -> DIS_FORCE_DOWNLOAD_R { + DIS_FORCE_DOWNLOAD_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download."] + #[inline(always)] + pub fn spi_download_mspi_dis(&self) -> SPI_DOWNLOAD_MSPI_DIS_R { + SPI_DOWNLOAD_MSPI_DIS_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled."] + #[inline(always)] + pub fn dis_twai(&self) -> DIS_TWAI_R { + DIS_TWAI_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled."] + #[inline(always)] + pub fn jtag_sel_enable(&self) -> JTAG_SEL_ENABLE_R { + JTAG_SEL_ENABLE_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled."] + #[inline(always)] + pub fn soft_dis_jtag(&self) -> SOFT_DIS_JTAG_R { + SOFT_DIS_JTAG_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled."] + #[inline(always)] + pub fn dis_pad_jtag(&self) -> DIS_PAD_JTAG_R { + DIS_PAD_JTAG_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled."] + #[inline(always)] + pub fn dis_download_manual_encrypt(&self) -> DIS_DOWNLOAD_MANUAL_ENCRYPT_R { + DIS_DOWNLOAD_MANUAL_ENCRYPT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:22 - USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV"] + #[inline(always)] + pub fn usb_device_drefh(&self) -> USB_DEVICE_DREFH_R { + USB_DEVICE_DREFH_R::new(((self.bits >> 21) & 3) as u8) + } + #[doc = "Bits 23:24 - USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV"] + #[inline(always)] + pub fn usb_otg11_drefh(&self) -> USB_OTG11_DREFH_R { + USB_OTG11_DREFH_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bit 25 - TBD"] + #[inline(always)] + pub fn usb_phy_sel(&self) -> USB_PHY_SEL_R { + USB_PHY_SEL_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 26:31 - Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid."] + #[inline(always)] + pub fn km_huk_gen_state_low(&self) -> KM_HUK_GEN_STATE_LOW_R { + KM_HUK_GEN_STATE_LOW_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_REPEAT_DATA0") + .field("rd_dis", &format_args!("{}", self.rd_dis().bits())) + .field( + "usb_device_exchg_pins", + &format_args!("{}", self.usb_device_exchg_pins().bit()), + ) + .field( + "usb_otg11_exchg_pins", + &format_args!("{}", self.usb_otg11_exchg_pins().bit()), + ) + .field( + "dis_usb_jtag", + &format_args!("{}", self.dis_usb_jtag().bit()), + ) + .field( + "powerglitch_en", + &format_args!("{}", self.powerglitch_en().bit()), + ) + .field( + "dis_usb_serial_jtag", + &format_args!("{}", self.dis_usb_serial_jtag().bit()), + ) + .field( + "dis_force_download", + &format_args!("{}", self.dis_force_download().bit()), + ) + .field( + "spi_download_mspi_dis", + &format_args!("{}", self.spi_download_mspi_dis().bit()), + ) + .field("dis_twai", &format_args!("{}", self.dis_twai().bit())) + .field( + "jtag_sel_enable", + &format_args!("{}", self.jtag_sel_enable().bit()), + ) + .field( + "soft_dis_jtag", + &format_args!("{}", self.soft_dis_jtag().bits()), + ) + .field( + "dis_pad_jtag", + &format_args!("{}", self.dis_pad_jtag().bit()), + ) + .field( + "dis_download_manual_encrypt", + &format_args!("{}", self.dis_download_manual_encrypt().bit()), + ) + .field( + "usb_device_drefh", + &format_args!("{}", self.usb_device_drefh().bits()), + ) + .field( + "usb_otg11_drefh", + &format_args!("{}", self.usb_otg11_drefh().bits()), + ) + .field("usb_phy_sel", &format_args!("{}", self.usb_phy_sel().bit())) + .field( + "km_huk_gen_state_low", + &format_args!("{}", self.km_huk_gen_state_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK0 data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_REPEAT_DATA0_SPEC; +impl crate::RegisterSpec for RD_REPEAT_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_repeat_data0::R`](R) reader structure"] +impl crate::Readable for RD_REPEAT_DATA0_SPEC {} +#[doc = "`reset()` method sets RD_REPEAT_DATA0 to value 0"] +impl crate::Resettable for RD_REPEAT_DATA0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_repeat_data1.rs b/esp32p4/src/efuse/rd_repeat_data1.rs new file mode 100644 index 0000000000..3f61fb5d68 --- /dev/null +++ b/esp32p4/src/efuse/rd_repeat_data1.rs @@ -0,0 +1,171 @@ +#[doc = "Register `RD_REPEAT_DATA1` reader"] +pub type R = crate::R; +#[doc = "Field `KM_HUK_GEN_STATE_HIGH` reader - Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid."] +pub type KM_HUK_GEN_STATE_HIGH_R = crate::FieldReader; +#[doc = "Field `KM_RND_SWITCH_CYCLE` reader - Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles."] +pub type KM_RND_SWITCH_CYCLE_R = crate::FieldReader; +#[doc = "Field `KM_DEPLOY_ONLY_ONCE` reader - Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds."] +pub type KM_DEPLOY_ONLY_ONCE_R = crate::FieldReader; +#[doc = "Field `FORCE_USE_KEY_MANAGER_KEY` reader - Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds."] +pub type FORCE_USE_KEY_MANAGER_KEY_R = crate::FieldReader; +#[doc = "Field `FORCE_DISABLE_SW_INIT_KEY` reader - Set this bit to disable software written init key, and force use efuse_init_key."] +pub type FORCE_DISABLE_SW_INIT_KEY_R = crate::BitReader; +#[doc = "Field `XTS_KEY_LENGTH_256` reader - Set this bit to configure flash encryption use xts-128 key, else use xts-256 key."] +pub type XTS_KEY_LENGTH_256_R = crate::BitReader; +#[doc = "Field `WDT_DELAY_SEL` reader - Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected."] +pub type WDT_DELAY_SEL_R = crate::FieldReader; +#[doc = "Field `SPI_BOOT_CRYPT_CNT` reader - Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled."] +pub type SPI_BOOT_CRYPT_CNT_R = crate::FieldReader; +#[doc = "Field `SECURE_BOOT_KEY_REVOKE0` reader - Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled."] +pub type SECURE_BOOT_KEY_REVOKE0_R = crate::BitReader; +#[doc = "Field `SECURE_BOOT_KEY_REVOKE1` reader - Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled."] +pub type SECURE_BOOT_KEY_REVOKE1_R = crate::BitReader; +#[doc = "Field `SECURE_BOOT_KEY_REVOKE2` reader - Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled."] +pub type SECURE_BOOT_KEY_REVOKE2_R = crate::BitReader; +#[doc = "Field `KEY_PURPOSE_0` reader - Represents the purpose of Key0."] +pub type KEY_PURPOSE_0_R = crate::FieldReader; +#[doc = "Field `KEY_PURPOSE_1` reader - Represents the purpose of Key1."] +pub type KEY_PURPOSE_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid."] + #[inline(always)] + pub fn km_huk_gen_state_high(&self) -> KM_HUK_GEN_STATE_HIGH_R { + KM_HUK_GEN_STATE_HIGH_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles."] + #[inline(always)] + pub fn km_rnd_switch_cycle(&self) -> KM_RND_SWITCH_CYCLE_R { + KM_RND_SWITCH_CYCLE_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bits 5:8 - Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds."] + #[inline(always)] + pub fn km_deploy_only_once(&self) -> KM_DEPLOY_ONLY_ONCE_R { + KM_DEPLOY_ONLY_ONCE_R::new(((self.bits >> 5) & 0x0f) as u8) + } + #[doc = "Bits 9:12 - Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds."] + #[inline(always)] + pub fn force_use_key_manager_key(&self) -> FORCE_USE_KEY_MANAGER_KEY_R { + FORCE_USE_KEY_MANAGER_KEY_R::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bit 13 - Set this bit to disable software written init key, and force use efuse_init_key."] + #[inline(always)] + pub fn force_disable_sw_init_key(&self) -> FORCE_DISABLE_SW_INIT_KEY_R { + FORCE_DISABLE_SW_INIT_KEY_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Set this bit to configure flash encryption use xts-128 key, else use xts-256 key."] + #[inline(always)] + pub fn xts_key_length_256(&self) -> XTS_KEY_LENGTH_256_R { + XTS_KEY_LENGTH_256_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 16:17 - Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected."] + #[inline(always)] + pub fn wdt_delay_sel(&self) -> WDT_DELAY_SEL_R { + WDT_DELAY_SEL_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:20 - Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled."] + #[inline(always)] + pub fn spi_boot_crypt_cnt(&self) -> SPI_BOOT_CRYPT_CNT_R { + SPI_BOOT_CRYPT_CNT_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bit 21 - Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled."] + #[inline(always)] + pub fn secure_boot_key_revoke0(&self) -> SECURE_BOOT_KEY_REVOKE0_R { + SECURE_BOOT_KEY_REVOKE0_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled."] + #[inline(always)] + pub fn secure_boot_key_revoke1(&self) -> SECURE_BOOT_KEY_REVOKE1_R { + SECURE_BOOT_KEY_REVOKE1_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled."] + #[inline(always)] + pub fn secure_boot_key_revoke2(&self) -> SECURE_BOOT_KEY_REVOKE2_R { + SECURE_BOOT_KEY_REVOKE2_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:27 - Represents the purpose of Key0."] + #[inline(always)] + pub fn key_purpose_0(&self) -> KEY_PURPOSE_0_R { + KEY_PURPOSE_0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Represents the purpose of Key1."] + #[inline(always)] + pub fn key_purpose_1(&self) -> KEY_PURPOSE_1_R { + KEY_PURPOSE_1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_REPEAT_DATA1") + .field( + "km_huk_gen_state_high", + &format_args!("{}", self.km_huk_gen_state_high().bits()), + ) + .field( + "km_rnd_switch_cycle", + &format_args!("{}", self.km_rnd_switch_cycle().bits()), + ) + .field( + "km_deploy_only_once", + &format_args!("{}", self.km_deploy_only_once().bits()), + ) + .field( + "force_use_key_manager_key", + &format_args!("{}", self.force_use_key_manager_key().bits()), + ) + .field( + "force_disable_sw_init_key", + &format_args!("{}", self.force_disable_sw_init_key().bit()), + ) + .field( + "xts_key_length_256", + &format_args!("{}", self.xts_key_length_256().bit()), + ) + .field( + "wdt_delay_sel", + &format_args!("{}", self.wdt_delay_sel().bits()), + ) + .field( + "spi_boot_crypt_cnt", + &format_args!("{}", self.spi_boot_crypt_cnt().bits()), + ) + .field( + "secure_boot_key_revoke0", + &format_args!("{}", self.secure_boot_key_revoke0().bit()), + ) + .field( + "secure_boot_key_revoke1", + &format_args!("{}", self.secure_boot_key_revoke1().bit()), + ) + .field( + "secure_boot_key_revoke2", + &format_args!("{}", self.secure_boot_key_revoke2().bit()), + ) + .field( + "key_purpose_0", + &format_args!("{}", self.key_purpose_0().bits()), + ) + .field( + "key_purpose_1", + &format_args!("{}", self.key_purpose_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK0 data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_REPEAT_DATA1_SPEC; +impl crate::RegisterSpec for RD_REPEAT_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_repeat_data1::R`](R) reader structure"] +impl crate::Readable for RD_REPEAT_DATA1_SPEC {} +#[doc = "`reset()` method sets RD_REPEAT_DATA1 to value 0"] +impl crate::Resettable for RD_REPEAT_DATA1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_repeat_data2.rs b/esp32p4/src/efuse/rd_repeat_data2.rs new file mode 100644 index 0000000000..b26d5e5e46 --- /dev/null +++ b/esp32p4/src/efuse/rd_repeat_data2.rs @@ -0,0 +1,176 @@ +#[doc = "Register `RD_REPEAT_DATA2` reader"] +pub type R = crate::R; +#[doc = "Field `KEY_PURPOSE_2` reader - Represents the purpose of Key2."] +pub type KEY_PURPOSE_2_R = crate::FieldReader; +#[doc = "Field `KEY_PURPOSE_3` reader - Represents the purpose of Key3."] +pub type KEY_PURPOSE_3_R = crate::FieldReader; +#[doc = "Field `KEY_PURPOSE_4` reader - Represents the purpose of Key4."] +pub type KEY_PURPOSE_4_R = crate::FieldReader; +#[doc = "Field `KEY_PURPOSE_5` reader - Represents the purpose of Key5."] +pub type KEY_PURPOSE_5_R = crate::FieldReader; +#[doc = "Field `SEC_DPA_LEVEL` reader - Represents the spa secure level by configuring the clock random divide mode."] +pub type SEC_DPA_LEVEL_R = crate::FieldReader; +#[doc = "Field `ECDSA_ENABLE_SOFT_K` reader - Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used."] +pub type ECDSA_ENABLE_SOFT_K_R = crate::BitReader; +#[doc = "Field `CRYPT_DPA_ENABLE` reader - Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled."] +pub type CRYPT_DPA_ENABLE_R = crate::BitReader; +#[doc = "Field `SECURE_BOOT_EN` reader - Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled."] +pub type SECURE_BOOT_EN_R = crate::BitReader; +#[doc = "Field `SECURE_BOOT_AGGRESSIVE_REVOKE` reader - Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled."] +pub type SECURE_BOOT_AGGRESSIVE_REVOKE_R = crate::BitReader; +#[doc = "Field `FLASH_TYPE` reader - The type of interfaced flash. 0: four data lines, 1: eight data lines."] +pub type FLASH_TYPE_R = crate::BitReader; +#[doc = "Field `FLASH_PAGE_SIZE` reader - Set flash page size."] +pub type FLASH_PAGE_SIZE_R = crate::FieldReader; +#[doc = "Field `FLASH_ECC_EN` reader - Set this bit to enable ecc for flash boot."] +pub type FLASH_ECC_EN_R = crate::BitReader; +#[doc = "Field `DIS_USB_OTG_DOWNLOAD_MODE` reader - Set this bit to disable download via USB-OTG."] +pub type DIS_USB_OTG_DOWNLOAD_MODE_R = crate::BitReader; +#[doc = "Field `FLASH_TPUW` reader - Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value."] +pub type FLASH_TPUW_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Represents the purpose of Key2."] + #[inline(always)] + pub fn key_purpose_2(&self) -> KEY_PURPOSE_2_R { + KEY_PURPOSE_2_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Represents the purpose of Key3."] + #[inline(always)] + pub fn key_purpose_3(&self) -> KEY_PURPOSE_3_R { + KEY_PURPOSE_3_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Represents the purpose of Key4."] + #[inline(always)] + pub fn key_purpose_4(&self) -> KEY_PURPOSE_4_R { + KEY_PURPOSE_4_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Represents the purpose of Key5."] + #[inline(always)] + pub fn key_purpose_5(&self) -> KEY_PURPOSE_5_R { + KEY_PURPOSE_5_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:17 - Represents the spa secure level by configuring the clock random divide mode."] + #[inline(always)] + pub fn sec_dpa_level(&self) -> SEC_DPA_LEVEL_R { + SEC_DPA_LEVEL_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used."] + #[inline(always)] + pub fn ecdsa_enable_soft_k(&self) -> ECDSA_ENABLE_SOFT_K_R { + ECDSA_ENABLE_SOFT_K_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled."] + #[inline(always)] + pub fn crypt_dpa_enable(&self) -> CRYPT_DPA_ENABLE_R { + CRYPT_DPA_ENABLE_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled."] + #[inline(always)] + pub fn secure_boot_en(&self) -> SECURE_BOOT_EN_R { + SECURE_BOOT_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled."] + #[inline(always)] + pub fn secure_boot_aggressive_revoke(&self) -> SECURE_BOOT_AGGRESSIVE_REVOKE_R { + SECURE_BOOT_AGGRESSIVE_REVOKE_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - The type of interfaced flash. 0: four data lines, 1: eight data lines."] + #[inline(always)] + pub fn flash_type(&self) -> FLASH_TYPE_R { + FLASH_TYPE_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:25 - Set flash page size."] + #[inline(always)] + pub fn flash_page_size(&self) -> FLASH_PAGE_SIZE_R { + FLASH_PAGE_SIZE_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - Set this bit to enable ecc for flash boot."] + #[inline(always)] + pub fn flash_ecc_en(&self) -> FLASH_ECC_EN_R { + FLASH_ECC_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Set this bit to disable download via USB-OTG."] + #[inline(always)] + pub fn dis_usb_otg_download_mode(&self) -> DIS_USB_OTG_DOWNLOAD_MODE_R { + DIS_USB_OTG_DOWNLOAD_MODE_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value."] + #[inline(always)] + pub fn flash_tpuw(&self) -> FLASH_TPUW_R { + FLASH_TPUW_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_REPEAT_DATA2") + .field( + "key_purpose_2", + &format_args!("{}", self.key_purpose_2().bits()), + ) + .field( + "key_purpose_3", + &format_args!("{}", self.key_purpose_3().bits()), + ) + .field( + "key_purpose_4", + &format_args!("{}", self.key_purpose_4().bits()), + ) + .field( + "key_purpose_5", + &format_args!("{}", self.key_purpose_5().bits()), + ) + .field( + "sec_dpa_level", + &format_args!("{}", self.sec_dpa_level().bits()), + ) + .field( + "ecdsa_enable_soft_k", + &format_args!("{}", self.ecdsa_enable_soft_k().bit()), + ) + .field( + "crypt_dpa_enable", + &format_args!("{}", self.crypt_dpa_enable().bit()), + ) + .field( + "secure_boot_en", + &format_args!("{}", self.secure_boot_en().bit()), + ) + .field( + "secure_boot_aggressive_revoke", + &format_args!("{}", self.secure_boot_aggressive_revoke().bit()), + ) + .field("flash_type", &format_args!("{}", self.flash_type().bit())) + .field( + "flash_page_size", + &format_args!("{}", self.flash_page_size().bits()), + ) + .field( + "flash_ecc_en", + &format_args!("{}", self.flash_ecc_en().bit()), + ) + .field( + "dis_usb_otg_download_mode", + &format_args!("{}", self.dis_usb_otg_download_mode().bit()), + ) + .field("flash_tpuw", &format_args!("{}", self.flash_tpuw().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK0 data register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_REPEAT_DATA2_SPEC; +impl crate::RegisterSpec for RD_REPEAT_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_repeat_data2::R`](R) reader structure"] +impl crate::Readable for RD_REPEAT_DATA2_SPEC {} +#[doc = "`reset()` method sets RD_REPEAT_DATA2 to value 0x0008_0000"] +impl crate::Resettable for RD_REPEAT_DATA2_SPEC { + const RESET_VALUE: Self::Ux = 0x0008_0000; +} diff --git a/esp32p4/src/efuse/rd_repeat_data3.rs b/esp32p4/src/efuse/rd_repeat_data3.rs new file mode 100644 index 0000000000..d8d1892edf --- /dev/null +++ b/esp32p4/src/efuse/rd_repeat_data3.rs @@ -0,0 +1,151 @@ +#[doc = "Register `RD_REPEAT_DATA3` reader"] +pub type R = crate::R; +#[doc = "Field `DIS_DOWNLOAD_MODE` reader - Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled."] +pub type DIS_DOWNLOAD_MODE_R = crate::BitReader; +#[doc = "Field `DIS_DIRECT_BOOT` reader - Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled."] +pub type DIS_DIRECT_BOOT_R = crate::BitReader; +#[doc = "Field `DIS_USB_SERIAL_JTAG_ROM_PRINT` reader - Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled."] +pub type DIS_USB_SERIAL_JTAG_ROM_PRINT_R = crate::BitReader; +#[doc = "Field `LOCK_KM_KEY` reader - TBD"] +pub type LOCK_KM_KEY_R = crate::BitReader; +#[doc = "Field `DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE` reader - Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled."] +pub type DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_R = crate::BitReader; +#[doc = "Field `ENABLE_SECURITY_DOWNLOAD` reader - Represents whether security download is enabled or disabled. 1: enabled. 0: disabled."] +pub type ENABLE_SECURITY_DOWNLOAD_R = crate::BitReader; +#[doc = "Field `UART_PRINT_CONTROL` reader - Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing."] +pub type UART_PRINT_CONTROL_R = crate::FieldReader; +#[doc = "Field `FORCE_SEND_RESUME` reader - Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced."] +pub type FORCE_SEND_RESUME_R = crate::BitReader; +#[doc = "Field `SECURE_VERSION` reader - Represents the version used by ESP-IDF anti-rollback feature."] +pub type SECURE_VERSION_R = crate::FieldReader; +#[doc = "Field `SECURE_BOOT_DISABLE_FAST_WAKE` reader - Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled."] +pub type SECURE_BOOT_DISABLE_FAST_WAKE_R = crate::BitReader; +#[doc = "Field `HYS_EN_PAD` reader - Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled."] +pub type HYS_EN_PAD_R = crate::BitReader; +#[doc = "Field `DCDC_VSET` reader - Set the dcdc voltage default."] +pub type DCDC_VSET_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled."] + #[inline(always)] + pub fn dis_download_mode(&self) -> DIS_DOWNLOAD_MODE_R { + DIS_DOWNLOAD_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled."] + #[inline(always)] + pub fn dis_direct_boot(&self) -> DIS_DIRECT_BOOT_R { + DIS_DIRECT_BOOT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled."] + #[inline(always)] + pub fn dis_usb_serial_jtag_rom_print(&self) -> DIS_USB_SERIAL_JTAG_ROM_PRINT_R { + DIS_USB_SERIAL_JTAG_ROM_PRINT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TBD"] + #[inline(always)] + pub fn lock_km_key(&self) -> LOCK_KM_KEY_R { + LOCK_KM_KEY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled."] + #[inline(always)] + pub fn dis_usb_serial_jtag_download_mode(&self) -> DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_R { + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents whether security download is enabled or disabled. 1: enabled. 0: disabled."] + #[inline(always)] + pub fn enable_security_download(&self) -> ENABLE_SECURITY_DOWNLOAD_R { + ENABLE_SECURITY_DOWNLOAD_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing."] + #[inline(always)] + pub fn uart_print_control(&self) -> UART_PRINT_CONTROL_R { + UART_PRINT_CONTROL_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced."] + #[inline(always)] + pub fn force_send_resume(&self) -> FORCE_SEND_RESUME_R { + FORCE_SEND_RESUME_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:24 - Represents the version used by ESP-IDF anti-rollback feature."] + #[inline(always)] + pub fn secure_version(&self) -> SECURE_VERSION_R { + SECURE_VERSION_R::new(((self.bits >> 9) & 0xffff) as u16) + } + #[doc = "Bit 25 - Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled."] + #[inline(always)] + pub fn secure_boot_disable_fast_wake(&self) -> SECURE_BOOT_DISABLE_FAST_WAKE_R { + SECURE_BOOT_DISABLE_FAST_WAKE_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled."] + #[inline(always)] + pub fn hys_en_pad(&self) -> HYS_EN_PAD_R { + HYS_EN_PAD_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bits 27:31 - Set the dcdc voltage default."] + #[inline(always)] + pub fn dcdc_vset(&self) -> DCDC_VSET_R { + DCDC_VSET_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_REPEAT_DATA3") + .field( + "dis_download_mode", + &format_args!("{}", self.dis_download_mode().bit()), + ) + .field( + "dis_direct_boot", + &format_args!("{}", self.dis_direct_boot().bit()), + ) + .field( + "dis_usb_serial_jtag_rom_print", + &format_args!("{}", self.dis_usb_serial_jtag_rom_print().bit()), + ) + .field("lock_km_key", &format_args!("{}", self.lock_km_key().bit())) + .field( + "dis_usb_serial_jtag_download_mode", + &format_args!("{}", self.dis_usb_serial_jtag_download_mode().bit()), + ) + .field( + "enable_security_download", + &format_args!("{}", self.enable_security_download().bit()), + ) + .field( + "uart_print_control", + &format_args!("{}", self.uart_print_control().bits()), + ) + .field( + "force_send_resume", + &format_args!("{}", self.force_send_resume().bit()), + ) + .field( + "secure_version", + &format_args!("{}", self.secure_version().bits()), + ) + .field( + "secure_boot_disable_fast_wake", + &format_args!("{}", self.secure_boot_disable_fast_wake().bit()), + ) + .field("hys_en_pad", &format_args!("{}", self.hys_en_pad().bit())) + .field("dcdc_vset", &format_args!("{}", self.dcdc_vset().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK0 data register 4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_REPEAT_DATA3_SPEC; +impl crate::RegisterSpec for RD_REPEAT_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_repeat_data3::R`](R) reader structure"] +impl crate::Readable for RD_REPEAT_DATA3_SPEC {} +#[doc = "`reset()` method sets RD_REPEAT_DATA3 to value 0"] +impl crate::Resettable for RD_REPEAT_DATA3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_repeat_data4.rs b/esp32p4/src/efuse/rd_repeat_data4.rs new file mode 100644 index 0000000000..f353d0fda5 --- /dev/null +++ b/esp32p4/src/efuse/rd_repeat_data4.rs @@ -0,0 +1,143 @@ +#[doc = "Register `RD_REPEAT_DATA4` reader"] +pub type R = crate::R; +#[doc = "Field `_0PXA_TIEH_SEL_0` reader - TBD"] +pub type _0PXA_TIEH_SEL_0_R = crate::FieldReader; +#[doc = "Field `_0PXA_TIEH_SEL_1` reader - TBD."] +pub type _0PXA_TIEH_SEL_1_R = crate::FieldReader; +#[doc = "Field `_0PXA_TIEH_SEL_2` reader - TBD."] +pub type _0PXA_TIEH_SEL_2_R = crate::FieldReader; +#[doc = "Field `_0PXA_TIEH_SEL_3` reader - TBD."] +pub type _0PXA_TIEH_SEL_3_R = crate::FieldReader; +#[doc = "Field `KM_DISABLE_DEPLOY_MODE` reader - TBD."] +pub type KM_DISABLE_DEPLOY_MODE_R = crate::FieldReader; +#[doc = "Field `USB_DEVICE_DREFL` reader - Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV."] +pub type USB_DEVICE_DREFL_R = crate::FieldReader; +#[doc = "Field `USB_OTG11_DREFL` reader - Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV."] +pub type USB_OTG11_DREFL_R = crate::FieldReader; +#[doc = "Field `HP_PWR_SRC_SEL` reader - HP system power source select. 0:LDO. 1: DCDC."] +pub type HP_PWR_SRC_SEL_R = crate::BitReader; +#[doc = "Field `DCDC_VSET_EN` reader - Select dcdc vset use efuse_dcdc_vset."] +pub type DCDC_VSET_EN_R = crate::BitReader; +#[doc = "Field `DIS_WDT` reader - Set this bit to disable watch dog."] +pub type DIS_WDT_R = crate::BitReader; +#[doc = "Field `DIS_SWD` reader - Set this bit to disable super-watchdog."] +pub type DIS_SWD_R = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - TBD"] + #[inline(always)] + pub fn _0pxa_tieh_sel_0(&self) -> _0PXA_TIEH_SEL_0_R { + _0PXA_TIEH_SEL_0_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - TBD."] + #[inline(always)] + pub fn _0pxa_tieh_sel_1(&self) -> _0PXA_TIEH_SEL_1_R { + _0PXA_TIEH_SEL_1_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - TBD."] + #[inline(always)] + pub fn _0pxa_tieh_sel_2(&self) -> _0PXA_TIEH_SEL_2_R { + _0PXA_TIEH_SEL_2_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - TBD."] + #[inline(always)] + pub fn _0pxa_tieh_sel_3(&self) -> _0PXA_TIEH_SEL_3_R { + _0PXA_TIEH_SEL_3_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:11 - TBD."] + #[inline(always)] + pub fn km_disable_deploy_mode(&self) -> KM_DISABLE_DEPLOY_MODE_R { + KM_DISABLE_DEPLOY_MODE_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:13 - Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV."] + #[inline(always)] + pub fn usb_device_drefl(&self) -> USB_DEVICE_DREFL_R { + USB_DEVICE_DREFL_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV."] + #[inline(always)] + pub fn usb_otg11_drefl(&self) -> USB_OTG11_DREFL_R { + USB_OTG11_DREFL_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bit 18 - HP system power source select. 0:LDO. 1: DCDC."] + #[inline(always)] + pub fn hp_pwr_src_sel(&self) -> HP_PWR_SRC_SEL_R { + HP_PWR_SRC_SEL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Select dcdc vset use efuse_dcdc_vset."] + #[inline(always)] + pub fn dcdc_vset_en(&self) -> DCDC_VSET_EN_R { + DCDC_VSET_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Set this bit to disable watch dog."] + #[inline(always)] + pub fn dis_wdt(&self) -> DIS_WDT_R { + DIS_WDT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to disable super-watchdog."] + #[inline(always)] + pub fn dis_swd(&self) -> DIS_SWD_R { + DIS_SWD_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_REPEAT_DATA4") + .field( + "_0pxa_tieh_sel_0", + &format_args!("{}", self._0pxa_tieh_sel_0().bits()), + ) + .field( + "_0pxa_tieh_sel_1", + &format_args!("{}", self._0pxa_tieh_sel_1().bits()), + ) + .field( + "_0pxa_tieh_sel_2", + &format_args!("{}", self._0pxa_tieh_sel_2().bits()), + ) + .field( + "_0pxa_tieh_sel_3", + &format_args!("{}", self._0pxa_tieh_sel_3().bits()), + ) + .field( + "km_disable_deploy_mode", + &format_args!("{}", self.km_disable_deploy_mode().bits()), + ) + .field( + "usb_device_drefl", + &format_args!("{}", self.usb_device_drefl().bits()), + ) + .field( + "usb_otg11_drefl", + &format_args!("{}", self.usb_otg11_drefl().bits()), + ) + .field( + "hp_pwr_src_sel", + &format_args!("{}", self.hp_pwr_src_sel().bit()), + ) + .field( + "dcdc_vset_en", + &format_args!("{}", self.dcdc_vset_en().bit()), + ) + .field("dis_wdt", &format_args!("{}", self.dis_wdt().bit())) + .field("dis_swd", &format_args!("{}", self.dis_swd().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK0 data register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_REPEAT_DATA4_SPEC; +impl crate::RegisterSpec for RD_REPEAT_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_repeat_data4::R`](R) reader structure"] +impl crate::Readable for RD_REPEAT_DATA4_SPEC {} +#[doc = "`reset()` method sets RD_REPEAT_DATA4 to value 0"] +impl crate::Resettable for RD_REPEAT_DATA4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_repeat_err0.rs b/esp32p4/src/efuse/rd_repeat_err0.rs new file mode 100644 index 0000000000..50f95c0191 --- /dev/null +++ b/esp32p4/src/efuse/rd_repeat_err0.rs @@ -0,0 +1,212 @@ +#[doc = "Register `RD_REPEAT_ERR0` reader"] +pub type R = crate::R; +#[doc = "Field `RD_DIS_ERR` reader - Indicates a programming error of RD_DIS."] +pub type RD_DIS_ERR_R = crate::FieldReader; +#[doc = "Field `DIS_USB_DEVICE_EXCHG_PINS_ERR` reader - Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS."] +pub type DIS_USB_DEVICE_EXCHG_PINS_ERR_R = crate::BitReader; +#[doc = "Field `DIS_USB_OTG11_EXCHG_PINS_ERR` reader - Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS."] +pub type DIS_USB_OTG11_EXCHG_PINS_ERR_R = crate::BitReader; +#[doc = "Field `DIS_USB_JTAG_ERR` reader - Indicates a programming error of DIS_USB_JTAG."] +pub type DIS_USB_JTAG_ERR_R = crate::BitReader; +#[doc = "Field `POWERGLITCH_EN_ERR` reader - Indicates a programming error of POWERGLITCH_EN."] +pub type POWERGLITCH_EN_ERR_R = crate::BitReader; +#[doc = "Field `DIS_USB_SERIAL_JTAG_ERR` reader - Indicates a programming error of DIS_USB_SERIAL_JTAG."] +pub type DIS_USB_SERIAL_JTAG_ERR_R = crate::BitReader; +#[doc = "Field `DIS_FORCE_DOWNLOAD_ERR` reader - Indicates a programming error of DIS_FORCE_DOWNLOAD."] +pub type DIS_FORCE_DOWNLOAD_ERR_R = crate::BitReader; +#[doc = "Field `SPI_DOWNLOAD_MSPI_DIS_ERR` reader - Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS."] +pub type SPI_DOWNLOAD_MSPI_DIS_ERR_R = crate::BitReader; +#[doc = "Field `DIS_TWAI_ERR` reader - Indicates a programming error of DIS_TWAI."] +pub type DIS_TWAI_ERR_R = crate::BitReader; +#[doc = "Field `JTAG_SEL_ENABLE_ERR` reader - Indicates a programming error of JTAG_SEL_ENABLE."] +pub type JTAG_SEL_ENABLE_ERR_R = crate::BitReader; +#[doc = "Field `SOFT_DIS_JTAG_ERR` reader - Indicates a programming error of SOFT_DIS_JTAG."] +pub type SOFT_DIS_JTAG_ERR_R = crate::FieldReader; +#[doc = "Field `DIS_PAD_JTAG_ERR` reader - Indicates a programming error of DIS_PAD_JTAG."] +pub type DIS_PAD_JTAG_ERR_R = crate::BitReader; +#[doc = "Field `DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR` reader - Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT."] +pub type DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_R = crate::BitReader; +#[doc = "Field `USB_DEVICE_DREFH_ERR` reader - Indicates a programming error of USB_DEVICE_DREFH."] +pub type USB_DEVICE_DREFH_ERR_R = crate::FieldReader; +#[doc = "Field `USB_OTG11_DREFH_ERR` reader - Indicates a programming error of USB_OTG11_DREFH."] +pub type USB_OTG11_DREFH_ERR_R = crate::FieldReader; +#[doc = "Field `USB_PHY_SEL_ERR` reader - Indicates a programming error of USB_PHY_SEL."] +pub type USB_PHY_SEL_ERR_R = crate::BitReader; +#[doc = "Field `HUK_GEN_STATE_LOW_ERR` reader - Indicates a programming error of HUK_GEN_STATE_LOW."] +pub type HUK_GEN_STATE_LOW_ERR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:6 - Indicates a programming error of RD_DIS."] + #[inline(always)] + pub fn rd_dis_err(&self) -> RD_DIS_ERR_R { + RD_DIS_ERR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS."] + #[inline(always)] + pub fn dis_usb_device_exchg_pins_err(&self) -> DIS_USB_DEVICE_EXCHG_PINS_ERR_R { + DIS_USB_DEVICE_EXCHG_PINS_ERR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS."] + #[inline(always)] + pub fn dis_usb_otg11_exchg_pins_err(&self) -> DIS_USB_OTG11_EXCHG_PINS_ERR_R { + DIS_USB_OTG11_EXCHG_PINS_ERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Indicates a programming error of DIS_USB_JTAG."] + #[inline(always)] + pub fn dis_usb_jtag_err(&self) -> DIS_USB_JTAG_ERR_R { + DIS_USB_JTAG_ERR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Indicates a programming error of POWERGLITCH_EN."] + #[inline(always)] + pub fn powerglitch_en_err(&self) -> POWERGLITCH_EN_ERR_R { + POWERGLITCH_EN_ERR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Indicates a programming error of DIS_USB_SERIAL_JTAG."] + #[inline(always)] + pub fn dis_usb_serial_jtag_err(&self) -> DIS_USB_SERIAL_JTAG_ERR_R { + DIS_USB_SERIAL_JTAG_ERR_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Indicates a programming error of DIS_FORCE_DOWNLOAD."] + #[inline(always)] + pub fn dis_force_download_err(&self) -> DIS_FORCE_DOWNLOAD_ERR_R { + DIS_FORCE_DOWNLOAD_ERR_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS."] + #[inline(always)] + pub fn spi_download_mspi_dis_err(&self) -> SPI_DOWNLOAD_MSPI_DIS_ERR_R { + SPI_DOWNLOAD_MSPI_DIS_ERR_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Indicates a programming error of DIS_TWAI."] + #[inline(always)] + pub fn dis_twai_err(&self) -> DIS_TWAI_ERR_R { + DIS_TWAI_ERR_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Indicates a programming error of JTAG_SEL_ENABLE."] + #[inline(always)] + pub fn jtag_sel_enable_err(&self) -> JTAG_SEL_ENABLE_ERR_R { + JTAG_SEL_ENABLE_ERR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Indicates a programming error of SOFT_DIS_JTAG."] + #[inline(always)] + pub fn soft_dis_jtag_err(&self) -> SOFT_DIS_JTAG_ERR_R { + SOFT_DIS_JTAG_ERR_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - Indicates a programming error of DIS_PAD_JTAG."] + #[inline(always)] + pub fn dis_pad_jtag_err(&self) -> DIS_PAD_JTAG_ERR_R { + DIS_PAD_JTAG_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT."] + #[inline(always)] + pub fn dis_download_manual_encrypt_err(&self) -> DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_R { + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:22 - Indicates a programming error of USB_DEVICE_DREFH."] + #[inline(always)] + pub fn usb_device_drefh_err(&self) -> USB_DEVICE_DREFH_ERR_R { + USB_DEVICE_DREFH_ERR_R::new(((self.bits >> 21) & 3) as u8) + } + #[doc = "Bits 23:24 - Indicates a programming error of USB_OTG11_DREFH."] + #[inline(always)] + pub fn usb_otg11_drefh_err(&self) -> USB_OTG11_DREFH_ERR_R { + USB_OTG11_DREFH_ERR_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bit 25 - Indicates a programming error of USB_PHY_SEL."] + #[inline(always)] + pub fn usb_phy_sel_err(&self) -> USB_PHY_SEL_ERR_R { + USB_PHY_SEL_ERR_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 26:31 - Indicates a programming error of HUK_GEN_STATE_LOW."] + #[inline(always)] + pub fn huk_gen_state_low_err(&self) -> HUK_GEN_STATE_LOW_ERR_R { + HUK_GEN_STATE_LOW_ERR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_REPEAT_ERR0") + .field("rd_dis_err", &format_args!("{}", self.rd_dis_err().bits())) + .field( + "dis_usb_device_exchg_pins_err", + &format_args!("{}", self.dis_usb_device_exchg_pins_err().bit()), + ) + .field( + "dis_usb_otg11_exchg_pins_err", + &format_args!("{}", self.dis_usb_otg11_exchg_pins_err().bit()), + ) + .field( + "dis_usb_jtag_err", + &format_args!("{}", self.dis_usb_jtag_err().bit()), + ) + .field( + "powerglitch_en_err", + &format_args!("{}", self.powerglitch_en_err().bit()), + ) + .field( + "dis_usb_serial_jtag_err", + &format_args!("{}", self.dis_usb_serial_jtag_err().bit()), + ) + .field( + "dis_force_download_err", + &format_args!("{}", self.dis_force_download_err().bit()), + ) + .field( + "spi_download_mspi_dis_err", + &format_args!("{}", self.spi_download_mspi_dis_err().bit()), + ) + .field( + "dis_twai_err", + &format_args!("{}", self.dis_twai_err().bit()), + ) + .field( + "jtag_sel_enable_err", + &format_args!("{}", self.jtag_sel_enable_err().bit()), + ) + .field( + "soft_dis_jtag_err", + &format_args!("{}", self.soft_dis_jtag_err().bits()), + ) + .field( + "dis_pad_jtag_err", + &format_args!("{}", self.dis_pad_jtag_err().bit()), + ) + .field( + "dis_download_manual_encrypt_err", + &format_args!("{}", self.dis_download_manual_encrypt_err().bit()), + ) + .field( + "usb_device_drefh_err", + &format_args!("{}", self.usb_device_drefh_err().bits()), + ) + .field( + "usb_otg11_drefh_err", + &format_args!("{}", self.usb_otg11_drefh_err().bits()), + ) + .field( + "usb_phy_sel_err", + &format_args!("{}", self.usb_phy_sel_err().bit()), + ) + .field( + "huk_gen_state_low_err", + &format_args!("{}", self.huk_gen_state_low_err().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Programming error record register 0 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_REPEAT_ERR0_SPEC; +impl crate::RegisterSpec for RD_REPEAT_ERR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_repeat_err0::R`](R) reader structure"] +impl crate::Readable for RD_REPEAT_ERR0_SPEC {} +#[doc = "`reset()` method sets RD_REPEAT_ERR0 to value 0"] +impl crate::Resettable for RD_REPEAT_ERR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_repeat_err1.rs b/esp32p4/src/efuse/rd_repeat_err1.rs new file mode 100644 index 0000000000..67d039a1a2 --- /dev/null +++ b/esp32p4/src/efuse/rd_repeat_err1.rs @@ -0,0 +1,171 @@ +#[doc = "Register `RD_REPEAT_ERR1` reader"] +pub type R = crate::R; +#[doc = "Field `KM_HUK_GEN_STATE_HIGH_ERR` reader - Indicates a programming error of HUK_GEN_STATE_HIGH."] +pub type KM_HUK_GEN_STATE_HIGH_ERR_R = crate::FieldReader; +#[doc = "Field `KM_RND_SWITCH_CYCLE_ERR` reader - Indicates a programming error of KM_RND_SWITCH_CYCLE."] +pub type KM_RND_SWITCH_CYCLE_ERR_R = crate::FieldReader; +#[doc = "Field `KM_DEPLOY_ONLY_ONCE_ERR` reader - Indicates a programming error of KM_DEPLOY_ONLY_ONCE."] +pub type KM_DEPLOY_ONLY_ONCE_ERR_R = crate::FieldReader; +#[doc = "Field `FORCE_USE_KEY_MANAGER_KEY_ERR` reader - Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY."] +pub type FORCE_USE_KEY_MANAGER_KEY_ERR_R = crate::FieldReader; +#[doc = "Field `FORCE_DISABLE_SW_INIT_KEY_ERR` reader - Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY."] +pub type FORCE_DISABLE_SW_INIT_KEY_ERR_R = crate::BitReader; +#[doc = "Field `XTS_KEY_LENGTH_256_ERR` reader - Indicates a programming error of XTS_KEY_LENGTH_256."] +pub type XTS_KEY_LENGTH_256_ERR_R = crate::BitReader; +#[doc = "Field `WDT_DELAY_SEL_ERR` reader - Indicates a programming error of WDT_DELAY_SEL."] +pub type WDT_DELAY_SEL_ERR_R = crate::FieldReader; +#[doc = "Field `SPI_BOOT_CRYPT_CNT_ERR` reader - Indicates a programming error of SPI_BOOT_CRYPT_CNT."] +pub type SPI_BOOT_CRYPT_CNT_ERR_R = crate::FieldReader; +#[doc = "Field `SECURE_BOOT_KEY_REVOKE0_ERR` reader - Indicates a programming error of SECURE_BOOT_KEY_REVOKE0."] +pub type SECURE_BOOT_KEY_REVOKE0_ERR_R = crate::BitReader; +#[doc = "Field `SECURE_BOOT_KEY_REVOKE1_ERR` reader - Indicates a programming error of SECURE_BOOT_KEY_REVOKE1."] +pub type SECURE_BOOT_KEY_REVOKE1_ERR_R = crate::BitReader; +#[doc = "Field `SECURE_BOOT_KEY_REVOKE2_ERR` reader - Indicates a programming error of SECURE_BOOT_KEY_REVOKE2."] +pub type SECURE_BOOT_KEY_REVOKE2_ERR_R = crate::BitReader; +#[doc = "Field `KEY_PURPOSE_0_ERR` reader - Indicates a programming error of KEY_PURPOSE_0."] +pub type KEY_PURPOSE_0_ERR_R = crate::FieldReader; +#[doc = "Field `KEY_PURPOSE_1_ERR` reader - Indicates a programming error of KEY_PURPOSE_1."] +pub type KEY_PURPOSE_1_ERR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Indicates a programming error of HUK_GEN_STATE_HIGH."] + #[inline(always)] + pub fn km_huk_gen_state_high_err(&self) -> KM_HUK_GEN_STATE_HIGH_ERR_R { + KM_HUK_GEN_STATE_HIGH_ERR_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Indicates a programming error of KM_RND_SWITCH_CYCLE."] + #[inline(always)] + pub fn km_rnd_switch_cycle_err(&self) -> KM_RND_SWITCH_CYCLE_ERR_R { + KM_RND_SWITCH_CYCLE_ERR_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bits 5:8 - Indicates a programming error of KM_DEPLOY_ONLY_ONCE."] + #[inline(always)] + pub fn km_deploy_only_once_err(&self) -> KM_DEPLOY_ONLY_ONCE_ERR_R { + KM_DEPLOY_ONLY_ONCE_ERR_R::new(((self.bits >> 5) & 0x0f) as u8) + } + #[doc = "Bits 9:12 - Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY."] + #[inline(always)] + pub fn force_use_key_manager_key_err(&self) -> FORCE_USE_KEY_MANAGER_KEY_ERR_R { + FORCE_USE_KEY_MANAGER_KEY_ERR_R::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bit 13 - Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY."] + #[inline(always)] + pub fn force_disable_sw_init_key_err(&self) -> FORCE_DISABLE_SW_INIT_KEY_ERR_R { + FORCE_DISABLE_SW_INIT_KEY_ERR_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Indicates a programming error of XTS_KEY_LENGTH_256."] + #[inline(always)] + pub fn xts_key_length_256_err(&self) -> XTS_KEY_LENGTH_256_ERR_R { + XTS_KEY_LENGTH_256_ERR_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 16:17 - Indicates a programming error of WDT_DELAY_SEL."] + #[inline(always)] + pub fn wdt_delay_sel_err(&self) -> WDT_DELAY_SEL_ERR_R { + WDT_DELAY_SEL_ERR_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:20 - Indicates a programming error of SPI_BOOT_CRYPT_CNT."] + #[inline(always)] + pub fn spi_boot_crypt_cnt_err(&self) -> SPI_BOOT_CRYPT_CNT_ERR_R { + SPI_BOOT_CRYPT_CNT_ERR_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bit 21 - Indicates a programming error of SECURE_BOOT_KEY_REVOKE0."] + #[inline(always)] + pub fn secure_boot_key_revoke0_err(&self) -> SECURE_BOOT_KEY_REVOKE0_ERR_R { + SECURE_BOOT_KEY_REVOKE0_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Indicates a programming error of SECURE_BOOT_KEY_REVOKE1."] + #[inline(always)] + pub fn secure_boot_key_revoke1_err(&self) -> SECURE_BOOT_KEY_REVOKE1_ERR_R { + SECURE_BOOT_KEY_REVOKE1_ERR_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Indicates a programming error of SECURE_BOOT_KEY_REVOKE2."] + #[inline(always)] + pub fn secure_boot_key_revoke2_err(&self) -> SECURE_BOOT_KEY_REVOKE2_ERR_R { + SECURE_BOOT_KEY_REVOKE2_ERR_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:27 - Indicates a programming error of KEY_PURPOSE_0."] + #[inline(always)] + pub fn key_purpose_0_err(&self) -> KEY_PURPOSE_0_ERR_R { + KEY_PURPOSE_0_ERR_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Indicates a programming error of KEY_PURPOSE_1."] + #[inline(always)] + pub fn key_purpose_1_err(&self) -> KEY_PURPOSE_1_ERR_R { + KEY_PURPOSE_1_ERR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_REPEAT_ERR1") + .field( + "km_huk_gen_state_high_err", + &format_args!("{}", self.km_huk_gen_state_high_err().bits()), + ) + .field( + "km_rnd_switch_cycle_err", + &format_args!("{}", self.km_rnd_switch_cycle_err().bits()), + ) + .field( + "km_deploy_only_once_err", + &format_args!("{}", self.km_deploy_only_once_err().bits()), + ) + .field( + "force_use_key_manager_key_err", + &format_args!("{}", self.force_use_key_manager_key_err().bits()), + ) + .field( + "force_disable_sw_init_key_err", + &format_args!("{}", self.force_disable_sw_init_key_err().bit()), + ) + .field( + "xts_key_length_256_err", + &format_args!("{}", self.xts_key_length_256_err().bit()), + ) + .field( + "wdt_delay_sel_err", + &format_args!("{}", self.wdt_delay_sel_err().bits()), + ) + .field( + "spi_boot_crypt_cnt_err", + &format_args!("{}", self.spi_boot_crypt_cnt_err().bits()), + ) + .field( + "secure_boot_key_revoke0_err", + &format_args!("{}", self.secure_boot_key_revoke0_err().bit()), + ) + .field( + "secure_boot_key_revoke1_err", + &format_args!("{}", self.secure_boot_key_revoke1_err().bit()), + ) + .field( + "secure_boot_key_revoke2_err", + &format_args!("{}", self.secure_boot_key_revoke2_err().bit()), + ) + .field( + "key_purpose_0_err", + &format_args!("{}", self.key_purpose_0_err().bits()), + ) + .field( + "key_purpose_1_err", + &format_args!("{}", self.key_purpose_1_err().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Programming error record register 1 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_REPEAT_ERR1_SPEC; +impl crate::RegisterSpec for RD_REPEAT_ERR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_repeat_err1::R`](R) reader structure"] +impl crate::Readable for RD_REPEAT_ERR1_SPEC {} +#[doc = "`reset()` method sets RD_REPEAT_ERR1 to value 0"] +impl crate::Resettable for RD_REPEAT_ERR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_repeat_err2.rs b/esp32p4/src/efuse/rd_repeat_err2.rs new file mode 100644 index 0000000000..f385408229 --- /dev/null +++ b/esp32p4/src/efuse/rd_repeat_err2.rs @@ -0,0 +1,182 @@ +#[doc = "Register `RD_REPEAT_ERR2` reader"] +pub type R = crate::R; +#[doc = "Field `KEY_PURPOSE_2_ERR` reader - Indicates a programming error of KEY_PURPOSE_2."] +pub type KEY_PURPOSE_2_ERR_R = crate::FieldReader; +#[doc = "Field `KEY_PURPOSE_3_ERR` reader - Indicates a programming error of KEY_PURPOSE_3."] +pub type KEY_PURPOSE_3_ERR_R = crate::FieldReader; +#[doc = "Field `KEY_PURPOSE_4_ERR` reader - Indicates a programming error of KEY_PURPOSE_4."] +pub type KEY_PURPOSE_4_ERR_R = crate::FieldReader; +#[doc = "Field `KEY_PURPOSE_5_ERR` reader - Indicates a programming error of KEY_PURPOSE_5."] +pub type KEY_PURPOSE_5_ERR_R = crate::FieldReader; +#[doc = "Field `SEC_DPA_LEVEL_ERR` reader - Indicates a programming error of SEC_DPA_LEVEL."] +pub type SEC_DPA_LEVEL_ERR_R = crate::FieldReader; +#[doc = "Field `ECDSA_ENABLE_SOFT_K_ERR` reader - Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K."] +pub type ECDSA_ENABLE_SOFT_K_ERR_R = crate::BitReader; +#[doc = "Field `CRYPT_DPA_ENABLE_ERR` reader - Indicates a programming error of CRYPT_DPA_ENABLE."] +pub type CRYPT_DPA_ENABLE_ERR_R = crate::BitReader; +#[doc = "Field `SECURE_BOOT_EN_ERR` reader - Indicates a programming error of SECURE_BOOT_EN."] +pub type SECURE_BOOT_EN_ERR_R = crate::BitReader; +#[doc = "Field `SECURE_BOOT_AGGRESSIVE_REVOKE_ERR` reader - Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE."] +pub type SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_R = crate::BitReader; +#[doc = "Field `FLASH_TYPE_ERR` reader - Indicates a programming error of FLASH_TYPE."] +pub type FLASH_TYPE_ERR_R = crate::BitReader; +#[doc = "Field `FLASH_PAGE_SIZE_ERR` reader - Indicates a programming error of FLASH_PAGE_SIZE."] +pub type FLASH_PAGE_SIZE_ERR_R = crate::FieldReader; +#[doc = "Field `FLASH_ECC_EN_ERR` reader - Indicates a programming error of FLASH_ECC_EN."] +pub type FLASH_ECC_EN_ERR_R = crate::BitReader; +#[doc = "Field `DIS_USB_OTG_DOWNLOAD_MODE_ERR` reader - Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE."] +pub type DIS_USB_OTG_DOWNLOAD_MODE_ERR_R = crate::BitReader; +#[doc = "Field `FLASH_TPUW_ERR` reader - Indicates a programming error of FLASH_TPUW."] +pub type FLASH_TPUW_ERR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Indicates a programming error of KEY_PURPOSE_2."] + #[inline(always)] + pub fn key_purpose_2_err(&self) -> KEY_PURPOSE_2_ERR_R { + KEY_PURPOSE_2_ERR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Indicates a programming error of KEY_PURPOSE_3."] + #[inline(always)] + pub fn key_purpose_3_err(&self) -> KEY_PURPOSE_3_ERR_R { + KEY_PURPOSE_3_ERR_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Indicates a programming error of KEY_PURPOSE_4."] + #[inline(always)] + pub fn key_purpose_4_err(&self) -> KEY_PURPOSE_4_ERR_R { + KEY_PURPOSE_4_ERR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Indicates a programming error of KEY_PURPOSE_5."] + #[inline(always)] + pub fn key_purpose_5_err(&self) -> KEY_PURPOSE_5_ERR_R { + KEY_PURPOSE_5_ERR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:17 - Indicates a programming error of SEC_DPA_LEVEL."] + #[inline(always)] + pub fn sec_dpa_level_err(&self) -> SEC_DPA_LEVEL_ERR_R { + SEC_DPA_LEVEL_ERR_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K."] + #[inline(always)] + pub fn ecdsa_enable_soft_k_err(&self) -> ECDSA_ENABLE_SOFT_K_ERR_R { + ECDSA_ENABLE_SOFT_K_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Indicates a programming error of CRYPT_DPA_ENABLE."] + #[inline(always)] + pub fn crypt_dpa_enable_err(&self) -> CRYPT_DPA_ENABLE_ERR_R { + CRYPT_DPA_ENABLE_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Indicates a programming error of SECURE_BOOT_EN."] + #[inline(always)] + pub fn secure_boot_en_err(&self) -> SECURE_BOOT_EN_ERR_R { + SECURE_BOOT_EN_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE."] + #[inline(always)] + pub fn secure_boot_aggressive_revoke_err(&self) -> SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_R { + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Indicates a programming error of FLASH_TYPE."] + #[inline(always)] + pub fn flash_type_err(&self) -> FLASH_TYPE_ERR_R { + FLASH_TYPE_ERR_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:25 - Indicates a programming error of FLASH_PAGE_SIZE."] + #[inline(always)] + pub fn flash_page_size_err(&self) -> FLASH_PAGE_SIZE_ERR_R { + FLASH_PAGE_SIZE_ERR_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - Indicates a programming error of FLASH_ECC_EN."] + #[inline(always)] + pub fn flash_ecc_en_err(&self) -> FLASH_ECC_EN_ERR_R { + FLASH_ECC_EN_ERR_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE."] + #[inline(always)] + pub fn dis_usb_otg_download_mode_err(&self) -> DIS_USB_OTG_DOWNLOAD_MODE_ERR_R { + DIS_USB_OTG_DOWNLOAD_MODE_ERR_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - Indicates a programming error of FLASH_TPUW."] + #[inline(always)] + pub fn flash_tpuw_err(&self) -> FLASH_TPUW_ERR_R { + FLASH_TPUW_ERR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_REPEAT_ERR2") + .field( + "key_purpose_2_err", + &format_args!("{}", self.key_purpose_2_err().bits()), + ) + .field( + "key_purpose_3_err", + &format_args!("{}", self.key_purpose_3_err().bits()), + ) + .field( + "key_purpose_4_err", + &format_args!("{}", self.key_purpose_4_err().bits()), + ) + .field( + "key_purpose_5_err", + &format_args!("{}", self.key_purpose_5_err().bits()), + ) + .field( + "sec_dpa_level_err", + &format_args!("{}", self.sec_dpa_level_err().bits()), + ) + .field( + "ecdsa_enable_soft_k_err", + &format_args!("{}", self.ecdsa_enable_soft_k_err().bit()), + ) + .field( + "crypt_dpa_enable_err", + &format_args!("{}", self.crypt_dpa_enable_err().bit()), + ) + .field( + "secure_boot_en_err", + &format_args!("{}", self.secure_boot_en_err().bit()), + ) + .field( + "secure_boot_aggressive_revoke_err", + &format_args!("{}", self.secure_boot_aggressive_revoke_err().bit()), + ) + .field( + "flash_type_err", + &format_args!("{}", self.flash_type_err().bit()), + ) + .field( + "flash_page_size_err", + &format_args!("{}", self.flash_page_size_err().bits()), + ) + .field( + "flash_ecc_en_err", + &format_args!("{}", self.flash_ecc_en_err().bit()), + ) + .field( + "dis_usb_otg_download_mode_err", + &format_args!("{}", self.dis_usb_otg_download_mode_err().bit()), + ) + .field( + "flash_tpuw_err", + &format_args!("{}", self.flash_tpuw_err().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Programming error record register 2 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_REPEAT_ERR2_SPEC; +impl crate::RegisterSpec for RD_REPEAT_ERR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_repeat_err2::R`](R) reader structure"] +impl crate::Readable for RD_REPEAT_ERR2_SPEC {} +#[doc = "`reset()` method sets RD_REPEAT_ERR2 to value 0"] +impl crate::Resettable for RD_REPEAT_ERR2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_repeat_err3.rs b/esp32p4/src/efuse/rd_repeat_err3.rs new file mode 100644 index 0000000000..aa702db1e0 --- /dev/null +++ b/esp32p4/src/efuse/rd_repeat_err3.rs @@ -0,0 +1,160 @@ +#[doc = "Register `RD_REPEAT_ERR3` reader"] +pub type R = crate::R; +#[doc = "Field `DIS_DOWNLOAD_MODE_ERR` reader - Indicates a programming error of DIS_DOWNLOAD_MODE."] +pub type DIS_DOWNLOAD_MODE_ERR_R = crate::BitReader; +#[doc = "Field `DIS_DIRECT_BOOT_ERR` reader - Indicates a programming error of DIS_DIRECT_BOOT."] +pub type DIS_DIRECT_BOOT_ERR_R = crate::BitReader; +#[doc = "Field `DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR` reader - Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR."] +pub type DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_R = crate::BitReader; +#[doc = "Field `LOCK_KM_KEY_ERR` reader - TBD"] +pub type LOCK_KM_KEY_ERR_R = crate::BitReader; +#[doc = "Field `DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR` reader - Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE."] +pub type DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_R = crate::BitReader; +#[doc = "Field `ENABLE_SECURITY_DOWNLOAD_ERR` reader - Indicates a programming error of ENABLE_SECURITY_DOWNLOAD."] +pub type ENABLE_SECURITY_DOWNLOAD_ERR_R = crate::BitReader; +#[doc = "Field `UART_PRINT_CONTROL_ERR` reader - Indicates a programming error of UART_PRINT_CONTROL."] +pub type UART_PRINT_CONTROL_ERR_R = crate::FieldReader; +#[doc = "Field `FORCE_SEND_RESUME_ERR` reader - Indicates a programming error of FORCE_SEND_RESUME."] +pub type FORCE_SEND_RESUME_ERR_R = crate::BitReader; +#[doc = "Field `SECURE_VERSION_ERR` reader - Indicates a programming error of SECURE VERSION."] +pub type SECURE_VERSION_ERR_R = crate::FieldReader; +#[doc = "Field `SECURE_BOOT_DISABLE_FAST_WAKE_ERR` reader - Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE."] +pub type SECURE_BOOT_DISABLE_FAST_WAKE_ERR_R = crate::BitReader; +#[doc = "Field `HYS_EN_PAD_ERR` reader - Indicates a programming error of HYS_EN_PAD."] +pub type HYS_EN_PAD_ERR_R = crate::BitReader; +#[doc = "Field `DCDC_VSET_ERR` reader - Indicates a programming error of DCDC_VSET."] +pub type DCDC_VSET_ERR_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Indicates a programming error of DIS_DOWNLOAD_MODE."] + #[inline(always)] + pub fn dis_download_mode_err(&self) -> DIS_DOWNLOAD_MODE_ERR_R { + DIS_DOWNLOAD_MODE_ERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates a programming error of DIS_DIRECT_BOOT."] + #[inline(always)] + pub fn dis_direct_boot_err(&self) -> DIS_DIRECT_BOOT_ERR_R { + DIS_DIRECT_BOOT_ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR."] + #[inline(always)] + pub fn dis_usb_serial_jtag_rom_print_err(&self) -> DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_R { + DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TBD"] + #[inline(always)] + pub fn lock_km_key_err(&self) -> LOCK_KM_KEY_ERR_R { + LOCK_KM_KEY_ERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE."] + #[inline(always)] + pub fn dis_usb_serial_jtag_download_mode_err(&self) -> DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_R { + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates a programming error of ENABLE_SECURITY_DOWNLOAD."] + #[inline(always)] + pub fn enable_security_download_err(&self) -> ENABLE_SECURITY_DOWNLOAD_ERR_R { + ENABLE_SECURITY_DOWNLOAD_ERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - Indicates a programming error of UART_PRINT_CONTROL."] + #[inline(always)] + pub fn uart_print_control_err(&self) -> UART_PRINT_CONTROL_ERR_R { + UART_PRINT_CONTROL_ERR_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - Indicates a programming error of FORCE_SEND_RESUME."] + #[inline(always)] + pub fn force_send_resume_err(&self) -> FORCE_SEND_RESUME_ERR_R { + FORCE_SEND_RESUME_ERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:24 - Indicates a programming error of SECURE VERSION."] + #[inline(always)] + pub fn secure_version_err(&self) -> SECURE_VERSION_ERR_R { + SECURE_VERSION_ERR_R::new(((self.bits >> 9) & 0xffff) as u16) + } + #[doc = "Bit 25 - Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE."] + #[inline(always)] + pub fn secure_boot_disable_fast_wake_err(&self) -> SECURE_BOOT_DISABLE_FAST_WAKE_ERR_R { + SECURE_BOOT_DISABLE_FAST_WAKE_ERR_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Indicates a programming error of HYS_EN_PAD."] + #[inline(always)] + pub fn hys_en_pad_err(&self) -> HYS_EN_PAD_ERR_R { + HYS_EN_PAD_ERR_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bits 27:31 - Indicates a programming error of DCDC_VSET."] + #[inline(always)] + pub fn dcdc_vset_err(&self) -> DCDC_VSET_ERR_R { + DCDC_VSET_ERR_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_REPEAT_ERR3") + .field( + "dis_download_mode_err", + &format_args!("{}", self.dis_download_mode_err().bit()), + ) + .field( + "dis_direct_boot_err", + &format_args!("{}", self.dis_direct_boot_err().bit()), + ) + .field( + "dis_usb_serial_jtag_rom_print_err", + &format_args!("{}", self.dis_usb_serial_jtag_rom_print_err().bit()), + ) + .field( + "lock_km_key_err", + &format_args!("{}", self.lock_km_key_err().bit()), + ) + .field( + "dis_usb_serial_jtag_download_mode_err", + &format_args!("{}", self.dis_usb_serial_jtag_download_mode_err().bit()), + ) + .field( + "enable_security_download_err", + &format_args!("{}", self.enable_security_download_err().bit()), + ) + .field( + "uart_print_control_err", + &format_args!("{}", self.uart_print_control_err().bits()), + ) + .field( + "force_send_resume_err", + &format_args!("{}", self.force_send_resume_err().bit()), + ) + .field( + "secure_version_err", + &format_args!("{}", self.secure_version_err().bits()), + ) + .field( + "secure_boot_disable_fast_wake_err", + &format_args!("{}", self.secure_boot_disable_fast_wake_err().bit()), + ) + .field( + "hys_en_pad_err", + &format_args!("{}", self.hys_en_pad_err().bit()), + ) + .field( + "dcdc_vset_err", + &format_args!("{}", self.dcdc_vset_err().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Programming error record register 3 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_REPEAT_ERR3_SPEC; +impl crate::RegisterSpec for RD_REPEAT_ERR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_repeat_err3::R`](R) reader structure"] +impl crate::Readable for RD_REPEAT_ERR3_SPEC {} +#[doc = "`reset()` method sets RD_REPEAT_ERR3 to value 0"] +impl crate::Resettable for RD_REPEAT_ERR3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_repeat_err4.rs b/esp32p4/src/efuse/rd_repeat_err4.rs new file mode 100644 index 0000000000..b34028e6a8 --- /dev/null +++ b/esp32p4/src/efuse/rd_repeat_err4.rs @@ -0,0 +1,143 @@ +#[doc = "Register `RD_REPEAT_ERR4` reader"] +pub type R = crate::R; +#[doc = "Field `_0PXA_TIEH_SEL_0_ERR` reader - Indicates a programming error of 0PXA_TIEH_SEL_0."] +pub type _0PXA_TIEH_SEL_0_ERR_R = crate::FieldReader; +#[doc = "Field `_0PXA_TIEH_SEL_1_ERR` reader - Indicates a programming error of 0PXA_TIEH_SEL_1."] +pub type _0PXA_TIEH_SEL_1_ERR_R = crate::FieldReader; +#[doc = "Field `_0PXA_TIEH_SEL_2_ERR` reader - Indicates a programming error of 0PXA_TIEH_SEL_2."] +pub type _0PXA_TIEH_SEL_2_ERR_R = crate::FieldReader; +#[doc = "Field `_0PXA_TIEH_SEL_3_ERR` reader - Indicates a programming error of 0PXA_TIEH_SEL_3."] +pub type _0PXA_TIEH_SEL_3_ERR_R = crate::FieldReader; +#[doc = "Field `KM_DISABLE_DEPLOY_MODE_ERR` reader - TBD."] +pub type KM_DISABLE_DEPLOY_MODE_ERR_R = crate::FieldReader; +#[doc = "Field `USB_DEVICE_DREFL_ERR` reader - Indicates a programming error of USB_DEVICE_DREFL."] +pub type USB_DEVICE_DREFL_ERR_R = crate::FieldReader; +#[doc = "Field `USB_OTG11_DREFL_ERR` reader - Indicates a programming error of USB_OTG11_DREFL."] +pub type USB_OTG11_DREFL_ERR_R = crate::FieldReader; +#[doc = "Field `HP_PWR_SRC_SEL_ERR` reader - Indicates a programming error of HP_PWR_SRC_SEL."] +pub type HP_PWR_SRC_SEL_ERR_R = crate::BitReader; +#[doc = "Field `DCDC_VSET_EN_ERR` reader - Indicates a programming error of DCDC_VSET_EN."] +pub type DCDC_VSET_EN_ERR_R = crate::BitReader; +#[doc = "Field `DIS_WDT_ERR` reader - Indicates a programming error of DIS_WDT."] +pub type DIS_WDT_ERR_R = crate::BitReader; +#[doc = "Field `DIS_SWD_ERR` reader - Indicates a programming error of DIS_SWD."] +pub type DIS_SWD_ERR_R = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - Indicates a programming error of 0PXA_TIEH_SEL_0."] + #[inline(always)] + pub fn _0pxa_tieh_sel_0_err(&self) -> _0PXA_TIEH_SEL_0_ERR_R { + _0PXA_TIEH_SEL_0_ERR_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Indicates a programming error of 0PXA_TIEH_SEL_1."] + #[inline(always)] + pub fn _0pxa_tieh_sel_1_err(&self) -> _0PXA_TIEH_SEL_1_ERR_R { + _0PXA_TIEH_SEL_1_ERR_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Indicates a programming error of 0PXA_TIEH_SEL_2."] + #[inline(always)] + pub fn _0pxa_tieh_sel_2_err(&self) -> _0PXA_TIEH_SEL_2_ERR_R { + _0PXA_TIEH_SEL_2_ERR_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Indicates a programming error of 0PXA_TIEH_SEL_3."] + #[inline(always)] + pub fn _0pxa_tieh_sel_3_err(&self) -> _0PXA_TIEH_SEL_3_ERR_R { + _0PXA_TIEH_SEL_3_ERR_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:11 - TBD."] + #[inline(always)] + pub fn km_disable_deploy_mode_err(&self) -> KM_DISABLE_DEPLOY_MODE_ERR_R { + KM_DISABLE_DEPLOY_MODE_ERR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:13 - Indicates a programming error of USB_DEVICE_DREFL."] + #[inline(always)] + pub fn usb_device_drefl_err(&self) -> USB_DEVICE_DREFL_ERR_R { + USB_DEVICE_DREFL_ERR_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Indicates a programming error of USB_OTG11_DREFL."] + #[inline(always)] + pub fn usb_otg11_drefl_err(&self) -> USB_OTG11_DREFL_ERR_R { + USB_OTG11_DREFL_ERR_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bit 18 - Indicates a programming error of HP_PWR_SRC_SEL."] + #[inline(always)] + pub fn hp_pwr_src_sel_err(&self) -> HP_PWR_SRC_SEL_ERR_R { + HP_PWR_SRC_SEL_ERR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Indicates a programming error of DCDC_VSET_EN."] + #[inline(always)] + pub fn dcdc_vset_en_err(&self) -> DCDC_VSET_EN_ERR_R { + DCDC_VSET_EN_ERR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Indicates a programming error of DIS_WDT."] + #[inline(always)] + pub fn dis_wdt_err(&self) -> DIS_WDT_ERR_R { + DIS_WDT_ERR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Indicates a programming error of DIS_SWD."] + #[inline(always)] + pub fn dis_swd_err(&self) -> DIS_SWD_ERR_R { + DIS_SWD_ERR_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_REPEAT_ERR4") + .field( + "_0pxa_tieh_sel_0_err", + &format_args!("{}", self._0pxa_tieh_sel_0_err().bits()), + ) + .field( + "_0pxa_tieh_sel_1_err", + &format_args!("{}", self._0pxa_tieh_sel_1_err().bits()), + ) + .field( + "_0pxa_tieh_sel_2_err", + &format_args!("{}", self._0pxa_tieh_sel_2_err().bits()), + ) + .field( + "_0pxa_tieh_sel_3_err", + &format_args!("{}", self._0pxa_tieh_sel_3_err().bits()), + ) + .field( + "km_disable_deploy_mode_err", + &format_args!("{}", self.km_disable_deploy_mode_err().bits()), + ) + .field( + "usb_device_drefl_err", + &format_args!("{}", self.usb_device_drefl_err().bits()), + ) + .field( + "usb_otg11_drefl_err", + &format_args!("{}", self.usb_otg11_drefl_err().bits()), + ) + .field( + "hp_pwr_src_sel_err", + &format_args!("{}", self.hp_pwr_src_sel_err().bit()), + ) + .field( + "dcdc_vset_en_err", + &format_args!("{}", self.dcdc_vset_en_err().bit()), + ) + .field("dis_wdt_err", &format_args!("{}", self.dis_wdt_err().bit())) + .field("dis_swd_err", &format_args!("{}", self.dis_swd_err().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Programming error record register 4 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_REPEAT_ERR4_SPEC; +impl crate::RegisterSpec for RD_REPEAT_ERR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_repeat_err4::R`](R) reader structure"] +impl crate::Readable for RD_REPEAT_ERR4_SPEC {} +#[doc = "`reset()` method sets RD_REPEAT_ERR4 to value 0"] +impl crate::Resettable for RD_REPEAT_ERR4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_rs_err0.rs b/esp32p4/src/efuse/rd_rs_err0.rs new file mode 100644 index 0000000000..74a5dc04ba --- /dev/null +++ b/esp32p4/src/efuse/rd_rs_err0.rs @@ -0,0 +1,189 @@ +#[doc = "Register `RD_RS_ERR0` reader"] +pub type R = crate::R; +#[doc = "Field `MAC_SYS_ERR_NUM` reader - The value of this signal means the number of error bytes."] +pub type MAC_SYS_ERR_NUM_R = crate::FieldReader; +#[doc = "Field `MAC_SYS_FAIL` reader - 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6."] +pub type MAC_SYS_FAIL_R = crate::BitReader; +#[doc = "Field `SYS_PART1_ERR_NUM` reader - The value of this signal means the number of error bytes."] +pub type SYS_PART1_ERR_NUM_R = crate::FieldReader; +#[doc = "Field `SYS_PART1_FAIL` reader - 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6."] +pub type SYS_PART1_FAIL_R = crate::BitReader; +#[doc = "Field `USR_DATA_ERR_NUM` reader - The value of this signal means the number of error bytes."] +pub type USR_DATA_ERR_NUM_R = crate::FieldReader; +#[doc = "Field `USR_DATA_FAIL` reader - 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6."] +pub type USR_DATA_FAIL_R = crate::BitReader; +#[doc = "Field `KEY0_ERR_NUM` reader - The value of this signal means the number of error bytes."] +pub type KEY0_ERR_NUM_R = crate::FieldReader; +#[doc = "Field `KEY0_FAIL` reader - 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6."] +pub type KEY0_FAIL_R = crate::BitReader; +#[doc = "Field `KEY1_ERR_NUM` reader - The value of this signal means the number of error bytes."] +pub type KEY1_ERR_NUM_R = crate::FieldReader; +#[doc = "Field `KEY1_FAIL` reader - 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6."] +pub type KEY1_FAIL_R = crate::BitReader; +#[doc = "Field `KEY2_ERR_NUM` reader - The value of this signal means the number of error bytes."] +pub type KEY2_ERR_NUM_R = crate::FieldReader; +#[doc = "Field `KEY2_FAIL` reader - 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6."] +pub type KEY2_FAIL_R = crate::BitReader; +#[doc = "Field `KEY3_ERR_NUM` reader - The value of this signal means the number of error bytes."] +pub type KEY3_ERR_NUM_R = crate::FieldReader; +#[doc = "Field `KEY3_FAIL` reader - 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6."] +pub type KEY3_FAIL_R = crate::BitReader; +#[doc = "Field `KEY4_ERR_NUM` reader - The value of this signal means the number of error bytes."] +pub type KEY4_ERR_NUM_R = crate::FieldReader; +#[doc = "Field `KEY4_FAIL` reader - 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6."] +pub type KEY4_FAIL_R = crate::BitReader; +impl R { + #[doc = "Bits 0:2 - The value of this signal means the number of error bytes."] + #[inline(always)] + pub fn mac_sys_err_num(&self) -> MAC_SYS_ERR_NUM_R { + MAC_SYS_ERR_NUM_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6."] + #[inline(always)] + pub fn mac_sys_fail(&self) -> MAC_SYS_FAIL_R { + MAC_SYS_FAIL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - The value of this signal means the number of error bytes."] + #[inline(always)] + pub fn sys_part1_err_num(&self) -> SYS_PART1_ERR_NUM_R { + SYS_PART1_ERR_NUM_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6."] + #[inline(always)] + pub fn sys_part1_fail(&self) -> SYS_PART1_FAIL_R { + SYS_PART1_FAIL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - The value of this signal means the number of error bytes."] + #[inline(always)] + pub fn usr_data_err_num(&self) -> USR_DATA_ERR_NUM_R { + USR_DATA_ERR_NUM_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6."] + #[inline(always)] + pub fn usr_data_fail(&self) -> USR_DATA_FAIL_R { + USR_DATA_FAIL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - The value of this signal means the number of error bytes."] + #[inline(always)] + pub fn key0_err_num(&self) -> KEY0_ERR_NUM_R { + KEY0_ERR_NUM_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6."] + #[inline(always)] + pub fn key0_fail(&self) -> KEY0_FAIL_R { + KEY0_FAIL_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - The value of this signal means the number of error bytes."] + #[inline(always)] + pub fn key1_err_num(&self) -> KEY1_ERR_NUM_R { + KEY1_ERR_NUM_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6."] + #[inline(always)] + pub fn key1_fail(&self) -> KEY1_FAIL_R { + KEY1_FAIL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - The value of this signal means the number of error bytes."] + #[inline(always)] + pub fn key2_err_num(&self) -> KEY2_ERR_NUM_R { + KEY2_ERR_NUM_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6."] + #[inline(always)] + pub fn key2_fail(&self) -> KEY2_FAIL_R { + KEY2_FAIL_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - The value of this signal means the number of error bytes."] + #[inline(always)] + pub fn key3_err_num(&self) -> KEY3_ERR_NUM_R { + KEY3_ERR_NUM_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6."] + #[inline(always)] + pub fn key3_fail(&self) -> KEY3_FAIL_R { + KEY3_FAIL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - The value of this signal means the number of error bytes."] + #[inline(always)] + pub fn key4_err_num(&self) -> KEY4_ERR_NUM_R { + KEY4_ERR_NUM_R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6."] + #[inline(always)] + pub fn key4_fail(&self) -> KEY4_FAIL_R { + KEY4_FAIL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_RS_ERR0") + .field( + "mac_sys_err_num", + &format_args!("{}", self.mac_sys_err_num().bits()), + ) + .field( + "mac_sys_fail", + &format_args!("{}", self.mac_sys_fail().bit()), + ) + .field( + "sys_part1_err_num", + &format_args!("{}", self.sys_part1_err_num().bits()), + ) + .field( + "sys_part1_fail", + &format_args!("{}", self.sys_part1_fail().bit()), + ) + .field( + "usr_data_err_num", + &format_args!("{}", self.usr_data_err_num().bits()), + ) + .field( + "usr_data_fail", + &format_args!("{}", self.usr_data_fail().bit()), + ) + .field( + "key0_err_num", + &format_args!("{}", self.key0_err_num().bits()), + ) + .field("key0_fail", &format_args!("{}", self.key0_fail().bit())) + .field( + "key1_err_num", + &format_args!("{}", self.key1_err_num().bits()), + ) + .field("key1_fail", &format_args!("{}", self.key1_fail().bit())) + .field( + "key2_err_num", + &format_args!("{}", self.key2_err_num().bits()), + ) + .field("key2_fail", &format_args!("{}", self.key2_fail().bit())) + .field( + "key3_err_num", + &format_args!("{}", self.key3_err_num().bits()), + ) + .field("key3_fail", &format_args!("{}", self.key3_fail().bit())) + .field( + "key4_err_num", + &format_args!("{}", self.key4_err_num().bits()), + ) + .field("key4_fail", &format_args!("{}", self.key4_fail().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Programming error record register 0 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_RS_ERR0_SPEC; +impl crate::RegisterSpec for RD_RS_ERR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_rs_err0::R`](R) reader structure"] +impl crate::Readable for RD_RS_ERR0_SPEC {} +#[doc = "`reset()` method sets RD_RS_ERR0 to value 0"] +impl crate::Resettable for RD_RS_ERR0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_rs_err1.rs b/esp32p4/src/efuse/rd_rs_err1.rs new file mode 100644 index 0000000000..7d837dab37 --- /dev/null +++ b/esp32p4/src/efuse/rd_rs_err1.rs @@ -0,0 +1,69 @@ +#[doc = "Register `RD_RS_ERR1` reader"] +pub type R = crate::R; +#[doc = "Field `KEY5_ERR_NUM` reader - The value of this signal means the number of error bytes."] +pub type KEY5_ERR_NUM_R = crate::FieldReader; +#[doc = "Field `KEY5_FAIL` reader - 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6."] +pub type KEY5_FAIL_R = crate::BitReader; +#[doc = "Field `SYS_PART2_ERR_NUM` reader - The value of this signal means the number of error bytes."] +pub type SYS_PART2_ERR_NUM_R = crate::FieldReader; +#[doc = "Field `SYS_PART2_FAIL` reader - 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6."] +pub type SYS_PART2_FAIL_R = crate::BitReader; +impl R { + #[doc = "Bits 0:2 - The value of this signal means the number of error bytes."] + #[inline(always)] + pub fn key5_err_num(&self) -> KEY5_ERR_NUM_R { + KEY5_ERR_NUM_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6."] + #[inline(always)] + pub fn key5_fail(&self) -> KEY5_FAIL_R { + KEY5_FAIL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - The value of this signal means the number of error bytes."] + #[inline(always)] + pub fn sys_part2_err_num(&self) -> SYS_PART2_ERR_NUM_R { + SYS_PART2_ERR_NUM_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6."] + #[inline(always)] + pub fn sys_part2_fail(&self) -> SYS_PART2_FAIL_R { + SYS_PART2_FAIL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_RS_ERR1") + .field( + "key5_err_num", + &format_args!("{}", self.key5_err_num().bits()), + ) + .field("key5_fail", &format_args!("{}", self.key5_fail().bit())) + .field( + "sys_part2_err_num", + &format_args!("{}", self.sys_part2_err_num().bits()), + ) + .field( + "sys_part2_fail", + &format_args!("{}", self.sys_part2_fail().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Programming error record register 1 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_RS_ERR1_SPEC; +impl crate::RegisterSpec for RD_RS_ERR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_rs_err1::R`](R) reader structure"] +impl crate::Readable for RD_RS_ERR1_SPEC {} +#[doc = "`reset()` method sets RD_RS_ERR1 to value 0"] +impl crate::Resettable for RD_RS_ERR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part1_data0.rs b/esp32p4/src/efuse/rd_sys_part1_data0.rs new file mode 100644 index 0000000000..a434c0235d --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part1_data0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART1_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART1_0` reader - Stores the zeroth 32 bits of the first part of system data."] +pub type SYS_DATA_PART1_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the zeroth 32 bits of the first part of system data."] + #[inline(always)] + pub fn sys_data_part1_0(&self) -> SYS_DATA_PART1_0_R { + SYS_DATA_PART1_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART1_DATA0") + .field( + "sys_data_part1_0", + &format_args!("{}", self.sys_data_part1_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART1_DATA0_SPEC; +impl crate::RegisterSpec for RD_SYS_PART1_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part1_data0::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART1_DATA0_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART1_DATA0 to value 0"] +impl crate::Resettable for RD_SYS_PART1_DATA0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part1_data1.rs b/esp32p4/src/efuse/rd_sys_part1_data1.rs new file mode 100644 index 0000000000..1b1158e354 --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part1_data1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART1_DATA1` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART1_1` reader - Stores the first 32 bits of the first part of system data."] +pub type SYS_DATA_PART1_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the first 32 bits of the first part of system data."] + #[inline(always)] + pub fn sys_data_part1_1(&self) -> SYS_DATA_PART1_1_R { + SYS_DATA_PART1_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART1_DATA1") + .field( + "sys_data_part1_1", + &format_args!("{}", self.sys_data_part1_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART1_DATA1_SPEC; +impl crate::RegisterSpec for RD_SYS_PART1_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part1_data1::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART1_DATA1_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART1_DATA1 to value 0"] +impl crate::Resettable for RD_SYS_PART1_DATA1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part1_data2.rs b/esp32p4/src/efuse/rd_sys_part1_data2.rs new file mode 100644 index 0000000000..10c50f368f --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part1_data2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART1_DATA2` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART1_2` reader - Stores the second 32 bits of the first part of system data."] +pub type SYS_DATA_PART1_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the second 32 bits of the first part of system data."] + #[inline(always)] + pub fn sys_data_part1_2(&self) -> SYS_DATA_PART1_2_R { + SYS_DATA_PART1_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART1_DATA2") + .field( + "sys_data_part1_2", + &format_args!("{}", self.sys_data_part1_2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART1_DATA2_SPEC; +impl crate::RegisterSpec for RD_SYS_PART1_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part1_data2::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART1_DATA2_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART1_DATA2 to value 0"] +impl crate::Resettable for RD_SYS_PART1_DATA2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part1_data3.rs b/esp32p4/src/efuse/rd_sys_part1_data3.rs new file mode 100644 index 0000000000..7ee5decf0c --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part1_data3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART1_DATA3` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART1_3` reader - Stores the third 32 bits of the first part of system data."] +pub type SYS_DATA_PART1_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the third 32 bits of the first part of system data."] + #[inline(always)] + pub fn sys_data_part1_3(&self) -> SYS_DATA_PART1_3_R { + SYS_DATA_PART1_3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART1_DATA3") + .field( + "sys_data_part1_3", + &format_args!("{}", self.sys_data_part1_3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART1_DATA3_SPEC; +impl crate::RegisterSpec for RD_SYS_PART1_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part1_data3::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART1_DATA3_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART1_DATA3 to value 0"] +impl crate::Resettable for RD_SYS_PART1_DATA3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part1_data4.rs b/esp32p4/src/efuse/rd_sys_part1_data4.rs new file mode 100644 index 0000000000..470b401479 --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part1_data4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART1_DATA4` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART1_4` reader - Stores the fourth 32 bits of the first part of system data."] +pub type SYS_DATA_PART1_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fourth 32 bits of the first part of system data."] + #[inline(always)] + pub fn sys_data_part1_4(&self) -> SYS_DATA_PART1_4_R { + SYS_DATA_PART1_4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART1_DATA4") + .field( + "sys_data_part1_4", + &format_args!("{}", self.sys_data_part1_4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART1_DATA4_SPEC; +impl crate::RegisterSpec for RD_SYS_PART1_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part1_data4::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART1_DATA4_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART1_DATA4 to value 0"] +impl crate::Resettable for RD_SYS_PART1_DATA4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part1_data5.rs b/esp32p4/src/efuse/rd_sys_part1_data5.rs new file mode 100644 index 0000000000..9784ab2ec6 --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part1_data5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART1_DATA5` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART1_5` reader - Stores the fifth 32 bits of the first part of system data."] +pub type SYS_DATA_PART1_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fifth 32 bits of the first part of system data."] + #[inline(always)] + pub fn sys_data_part1_5(&self) -> SYS_DATA_PART1_5_R { + SYS_DATA_PART1_5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART1_DATA5") + .field( + "sys_data_part1_5", + &format_args!("{}", self.sys_data_part1_5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART1_DATA5_SPEC; +impl crate::RegisterSpec for RD_SYS_PART1_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part1_data5::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART1_DATA5_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART1_DATA5 to value 0"] +impl crate::Resettable for RD_SYS_PART1_DATA5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part1_data6.rs b/esp32p4/src/efuse/rd_sys_part1_data6.rs new file mode 100644 index 0000000000..c27a902451 --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part1_data6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART1_DATA6` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART1_6` reader - Stores the sixth 32 bits of the first part of system data."] +pub type SYS_DATA_PART1_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the sixth 32 bits of the first part of system data."] + #[inline(always)] + pub fn sys_data_part1_6(&self) -> SYS_DATA_PART1_6_R { + SYS_DATA_PART1_6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART1_DATA6") + .field( + "sys_data_part1_6", + &format_args!("{}", self.sys_data_part1_6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART1_DATA6_SPEC; +impl crate::RegisterSpec for RD_SYS_PART1_DATA6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part1_data6::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART1_DATA6_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART1_DATA6 to value 0"] +impl crate::Resettable for RD_SYS_PART1_DATA6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part1_data7.rs b/esp32p4/src/efuse/rd_sys_part1_data7.rs new file mode 100644 index 0000000000..27de154f1a --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part1_data7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART1_DATA7` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART1_7` reader - Stores the seventh 32 bits of the first part of system data."] +pub type SYS_DATA_PART1_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the seventh 32 bits of the first part of system data."] + #[inline(always)] + pub fn sys_data_part1_7(&self) -> SYS_DATA_PART1_7_R { + SYS_DATA_PART1_7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART1_DATA7") + .field( + "sys_data_part1_7", + &format_args!("{}", self.sys_data_part1_7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART1_DATA7_SPEC; +impl crate::RegisterSpec for RD_SYS_PART1_DATA7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part1_data7::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART1_DATA7_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART1_DATA7 to value 0"] +impl crate::Resettable for RD_SYS_PART1_DATA7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part2_data0.rs b/esp32p4/src/efuse/rd_sys_part2_data0.rs new file mode 100644 index 0000000000..816cee3da7 --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part2_data0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART2_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART2_0` reader - Stores the 0th 32 bits of the 2nd part of system data."] +pub type SYS_DATA_PART2_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the 0th 32 bits of the 2nd part of system data."] + #[inline(always)] + pub fn sys_data_part2_0(&self) -> SYS_DATA_PART2_0_R { + SYS_DATA_PART2_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART2_DATA0") + .field( + "sys_data_part2_0", + &format_args!("{}", self.sys_data_part2_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART2_DATA0_SPEC; +impl crate::RegisterSpec for RD_SYS_PART2_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part2_data0::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART2_DATA0_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART2_DATA0 to value 0"] +impl crate::Resettable for RD_SYS_PART2_DATA0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part2_data1.rs b/esp32p4/src/efuse/rd_sys_part2_data1.rs new file mode 100644 index 0000000000..a59b6dc57f --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part2_data1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART2_DATA1` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART2_1` reader - Stores the 0th 32 bits of the 2nd part of system data."] +pub type SYS_DATA_PART2_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the 0th 32 bits of the 2nd part of system data."] + #[inline(always)] + pub fn sys_data_part2_1(&self) -> SYS_DATA_PART2_1_R { + SYS_DATA_PART2_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART2_DATA1") + .field( + "sys_data_part2_1", + &format_args!("{}", self.sys_data_part2_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART2_DATA1_SPEC; +impl crate::RegisterSpec for RD_SYS_PART2_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part2_data1::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART2_DATA1_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART2_DATA1 to value 0"] +impl crate::Resettable for RD_SYS_PART2_DATA1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part2_data2.rs b/esp32p4/src/efuse/rd_sys_part2_data2.rs new file mode 100644 index 0000000000..bffcc3c7f7 --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part2_data2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART2_DATA2` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART2_2` reader - Stores the 0th 32 bits of the 2nd part of system data."] +pub type SYS_DATA_PART2_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the 0th 32 bits of the 2nd part of system data."] + #[inline(always)] + pub fn sys_data_part2_2(&self) -> SYS_DATA_PART2_2_R { + SYS_DATA_PART2_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART2_DATA2") + .field( + "sys_data_part2_2", + &format_args!("{}", self.sys_data_part2_2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART2_DATA2_SPEC; +impl crate::RegisterSpec for RD_SYS_PART2_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part2_data2::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART2_DATA2_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART2_DATA2 to value 0"] +impl crate::Resettable for RD_SYS_PART2_DATA2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part2_data3.rs b/esp32p4/src/efuse/rd_sys_part2_data3.rs new file mode 100644 index 0000000000..4fca64b607 --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part2_data3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART2_DATA3` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART2_3` reader - Stores the 0th 32 bits of the 2nd part of system data."] +pub type SYS_DATA_PART2_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the 0th 32 bits of the 2nd part of system data."] + #[inline(always)] + pub fn sys_data_part2_3(&self) -> SYS_DATA_PART2_3_R { + SYS_DATA_PART2_3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART2_DATA3") + .field( + "sys_data_part2_3", + &format_args!("{}", self.sys_data_part2_3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART2_DATA3_SPEC; +impl crate::RegisterSpec for RD_SYS_PART2_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part2_data3::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART2_DATA3_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART2_DATA3 to value 0"] +impl crate::Resettable for RD_SYS_PART2_DATA3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part2_data4.rs b/esp32p4/src/efuse/rd_sys_part2_data4.rs new file mode 100644 index 0000000000..ad05cc2ae9 --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part2_data4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART2_DATA4` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART2_4` reader - Stores the 0th 32 bits of the 2nd part of system data."] +pub type SYS_DATA_PART2_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the 0th 32 bits of the 2nd part of system data."] + #[inline(always)] + pub fn sys_data_part2_4(&self) -> SYS_DATA_PART2_4_R { + SYS_DATA_PART2_4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART2_DATA4") + .field( + "sys_data_part2_4", + &format_args!("{}", self.sys_data_part2_4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART2_DATA4_SPEC; +impl crate::RegisterSpec for RD_SYS_PART2_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part2_data4::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART2_DATA4_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART2_DATA4 to value 0"] +impl crate::Resettable for RD_SYS_PART2_DATA4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part2_data5.rs b/esp32p4/src/efuse/rd_sys_part2_data5.rs new file mode 100644 index 0000000000..231adf2e63 --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part2_data5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART2_DATA5` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART2_5` reader - Stores the 0th 32 bits of the 2nd part of system data."] +pub type SYS_DATA_PART2_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the 0th 32 bits of the 2nd part of system data."] + #[inline(always)] + pub fn sys_data_part2_5(&self) -> SYS_DATA_PART2_5_R { + SYS_DATA_PART2_5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART2_DATA5") + .field( + "sys_data_part2_5", + &format_args!("{}", self.sys_data_part2_5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART2_DATA5_SPEC; +impl crate::RegisterSpec for RD_SYS_PART2_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part2_data5::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART2_DATA5_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART2_DATA5 to value 0"] +impl crate::Resettable for RD_SYS_PART2_DATA5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part2_data6.rs b/esp32p4/src/efuse/rd_sys_part2_data6.rs new file mode 100644 index 0000000000..57ce5174df --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part2_data6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART2_DATA6` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART2_6` reader - Stores the 0th 32 bits of the 2nd part of system data."] +pub type SYS_DATA_PART2_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the 0th 32 bits of the 2nd part of system data."] + #[inline(always)] + pub fn sys_data_part2_6(&self) -> SYS_DATA_PART2_6_R { + SYS_DATA_PART2_6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART2_DATA6") + .field( + "sys_data_part2_6", + &format_args!("{}", self.sys_data_part2_6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART2_DATA6_SPEC; +impl crate::RegisterSpec for RD_SYS_PART2_DATA6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part2_data6::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART2_DATA6_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART2_DATA6 to value 0"] +impl crate::Resettable for RD_SYS_PART2_DATA6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_sys_part2_data7.rs b/esp32p4/src/efuse/rd_sys_part2_data7.rs new file mode 100644 index 0000000000..45510407f0 --- /dev/null +++ b/esp32p4/src/efuse/rd_sys_part2_data7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RD_SYS_PART2_DATA7` reader"] +pub type R = crate::R; +#[doc = "Field `SYS_DATA_PART2_7` reader - Stores the 0th 32 bits of the 2nd part of system data."] +pub type SYS_DATA_PART2_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the 0th 32 bits of the 2nd part of system data."] + #[inline(always)] + pub fn sys_data_part2_7(&self) -> SYS_DATA_PART2_7_R { + SYS_DATA_PART2_7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_SYS_PART2_DATA7") + .field( + "sys_data_part2_7", + &format_args!("{}", self.sys_data_part2_7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_SYS_PART2_DATA7_SPEC; +impl crate::RegisterSpec for RD_SYS_PART2_DATA7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_sys_part2_data7::R`](R) reader structure"] +impl crate::Readable for RD_SYS_PART2_DATA7_SPEC {} +#[doc = "`reset()` method sets RD_SYS_PART2_DATA7 to value 0"] +impl crate::Resettable for RD_SYS_PART2_DATA7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_tim_conf.rs b/esp32p4/src/efuse/rd_tim_conf.rs new file mode 100644 index 0000000000..2256e7fe73 --- /dev/null +++ b/esp32p4/src/efuse/rd_tim_conf.rs @@ -0,0 +1,114 @@ +#[doc = "Register `RD_TIM_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `RD_TIM_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `THR_A` reader - Configures the read hold time."] +pub type THR_A_R = crate::FieldReader; +#[doc = "Field `THR_A` writer - Configures the read hold time."] +pub type THR_A_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TRD` reader - Configures the read time."] +pub type TRD_R = crate::FieldReader; +#[doc = "Field `TRD` writer - Configures the read time."] +pub type TRD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TSUR_A` reader - Configures the read setup time."] +pub type TSUR_A_R = crate::FieldReader; +#[doc = "Field `TSUR_A` writer - Configures the read setup time."] +pub type TSUR_A_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `READ_INIT_NUM` reader - Configures the waiting time of reading eFuse memory."] +pub type READ_INIT_NUM_R = crate::FieldReader; +#[doc = "Field `READ_INIT_NUM` writer - Configures the waiting time of reading eFuse memory."] +pub type READ_INIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures the read hold time."] + #[inline(always)] + pub fn thr_a(&self) -> THR_A_R { + THR_A_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Configures the read time."] + #[inline(always)] + pub fn trd(&self) -> TRD_R { + TRD_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Configures the read setup time."] + #[inline(always)] + pub fn tsur_a(&self) -> TSUR_A_R { + TSUR_A_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Configures the waiting time of reading eFuse memory."] + #[inline(always)] + pub fn read_init_num(&self) -> READ_INIT_NUM_R { + READ_INIT_NUM_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_TIM_CONF") + .field("thr_a", &format_args!("{}", self.thr_a().bits())) + .field("trd", &format_args!("{}", self.trd().bits())) + .field("tsur_a", &format_args!("{}", self.tsur_a().bits())) + .field( + "read_init_num", + &format_args!("{}", self.read_init_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures the read hold time."] + #[inline(always)] + #[must_use] + pub fn thr_a(&mut self) -> THR_A_W { + THR_A_W::new(self, 0) + } + #[doc = "Bits 8:15 - Configures the read time."] + #[inline(always)] + #[must_use] + pub fn trd(&mut self) -> TRD_W { + TRD_W::new(self, 8) + } + #[doc = "Bits 16:23 - Configures the read setup time."] + #[inline(always)] + #[must_use] + pub fn tsur_a(&mut self) -> TSUR_A_W { + TSUR_A_W::new(self, 16) + } + #[doc = "Bits 24:31 - Configures the waiting time of reading eFuse memory."] + #[inline(always)] + #[must_use] + pub fn read_init_num(&mut self) -> READ_INIT_NUM_W { + READ_INIT_NUM_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures read timing parameters.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_tim_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_tim_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_TIM_CONF_SPEC; +impl crate::RegisterSpec for RD_TIM_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_tim_conf::R`](R) reader structure"] +impl crate::Readable for RD_TIM_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rd_tim_conf::W`](W) writer structure"] +impl crate::Writable for RD_TIM_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RD_TIM_CONF to value 0x0f01_0201"] +impl crate::Resettable for RD_TIM_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0f01_0201; +} diff --git a/esp32p4/src/efuse/rd_usr_data0.rs b/esp32p4/src/efuse/rd_usr_data0.rs new file mode 100644 index 0000000000..f36aa12ed1 --- /dev/null +++ b/esp32p4/src/efuse/rd_usr_data0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_USR_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `USR_DATA0` reader - Stores the zeroth 32 bits of BLOCK3 (user)."] +pub type USR_DATA0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the zeroth 32 bits of BLOCK3 (user)."] + #[inline(always)] + pub fn usr_data0(&self) -> USR_DATA0_R { + USR_DATA0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_USR_DATA0") + .field("usr_data0", &format_args!("{}", self.usr_data0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_USR_DATA0_SPEC; +impl crate::RegisterSpec for RD_USR_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_usr_data0::R`](R) reader structure"] +impl crate::Readable for RD_USR_DATA0_SPEC {} +#[doc = "`reset()` method sets RD_USR_DATA0 to value 0"] +impl crate::Resettable for RD_USR_DATA0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_usr_data1.rs b/esp32p4/src/efuse/rd_usr_data1.rs new file mode 100644 index 0000000000..fe3ace6f0e --- /dev/null +++ b/esp32p4/src/efuse/rd_usr_data1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_USR_DATA1` reader"] +pub type R = crate::R; +#[doc = "Field `USR_DATA1` reader - Stores the first 32 bits of BLOCK3 (user)."] +pub type USR_DATA1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the first 32 bits of BLOCK3 (user)."] + #[inline(always)] + pub fn usr_data1(&self) -> USR_DATA1_R { + USR_DATA1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_USR_DATA1") + .field("usr_data1", &format_args!("{}", self.usr_data1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_USR_DATA1_SPEC; +impl crate::RegisterSpec for RD_USR_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_usr_data1::R`](R) reader structure"] +impl crate::Readable for RD_USR_DATA1_SPEC {} +#[doc = "`reset()` method sets RD_USR_DATA1 to value 0"] +impl crate::Resettable for RD_USR_DATA1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_usr_data2.rs b/esp32p4/src/efuse/rd_usr_data2.rs new file mode 100644 index 0000000000..d7ae7a49fe --- /dev/null +++ b/esp32p4/src/efuse/rd_usr_data2.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_USR_DATA2` reader"] +pub type R = crate::R; +#[doc = "Field `USR_DATA2` reader - Stores the second 32 bits of BLOCK3 (user)."] +pub type USR_DATA2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the second 32 bits of BLOCK3 (user)."] + #[inline(always)] + pub fn usr_data2(&self) -> USR_DATA2_R { + USR_DATA2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_USR_DATA2") + .field("usr_data2", &format_args!("{}", self.usr_data2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_USR_DATA2_SPEC; +impl crate::RegisterSpec for RD_USR_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_usr_data2::R`](R) reader structure"] +impl crate::Readable for RD_USR_DATA2_SPEC {} +#[doc = "`reset()` method sets RD_USR_DATA2 to value 0"] +impl crate::Resettable for RD_USR_DATA2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_usr_data3.rs b/esp32p4/src/efuse/rd_usr_data3.rs new file mode 100644 index 0000000000..c733f048f7 --- /dev/null +++ b/esp32p4/src/efuse/rd_usr_data3.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_USR_DATA3` reader"] +pub type R = crate::R; +#[doc = "Field `USR_DATA3` reader - Stores the third 32 bits of BLOCK3 (user)."] +pub type USR_DATA3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the third 32 bits of BLOCK3 (user)."] + #[inline(always)] + pub fn usr_data3(&self) -> USR_DATA3_R { + USR_DATA3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_USR_DATA3") + .field("usr_data3", &format_args!("{}", self.usr_data3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_USR_DATA3_SPEC; +impl crate::RegisterSpec for RD_USR_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_usr_data3::R`](R) reader structure"] +impl crate::Readable for RD_USR_DATA3_SPEC {} +#[doc = "`reset()` method sets RD_USR_DATA3 to value 0"] +impl crate::Resettable for RD_USR_DATA3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_usr_data4.rs b/esp32p4/src/efuse/rd_usr_data4.rs new file mode 100644 index 0000000000..eb0cacb261 --- /dev/null +++ b/esp32p4/src/efuse/rd_usr_data4.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_USR_DATA4` reader"] +pub type R = crate::R; +#[doc = "Field `USR_DATA4` reader - Stores the fourth 32 bits of BLOCK3 (user)."] +pub type USR_DATA4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fourth 32 bits of BLOCK3 (user)."] + #[inline(always)] + pub fn usr_data4(&self) -> USR_DATA4_R { + USR_DATA4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_USR_DATA4") + .field("usr_data4", &format_args!("{}", self.usr_data4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_USR_DATA4_SPEC; +impl crate::RegisterSpec for RD_USR_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_usr_data4::R`](R) reader structure"] +impl crate::Readable for RD_USR_DATA4_SPEC {} +#[doc = "`reset()` method sets RD_USR_DATA4 to value 0"] +impl crate::Resettable for RD_USR_DATA4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_usr_data5.rs b/esp32p4/src/efuse/rd_usr_data5.rs new file mode 100644 index 0000000000..50dd1b0d79 --- /dev/null +++ b/esp32p4/src/efuse/rd_usr_data5.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_USR_DATA5` reader"] +pub type R = crate::R; +#[doc = "Field `USR_DATA5` reader - Stores the fifth 32 bits of BLOCK3 (user)."] +pub type USR_DATA5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the fifth 32 bits of BLOCK3 (user)."] + #[inline(always)] + pub fn usr_data5(&self) -> USR_DATA5_R { + USR_DATA5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_USR_DATA5") + .field("usr_data5", &format_args!("{}", self.usr_data5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_USR_DATA5_SPEC; +impl crate::RegisterSpec for RD_USR_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_usr_data5::R`](R) reader structure"] +impl crate::Readable for RD_USR_DATA5_SPEC {} +#[doc = "`reset()` method sets RD_USR_DATA5 to value 0"] +impl crate::Resettable for RD_USR_DATA5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_usr_data6.rs b/esp32p4/src/efuse/rd_usr_data6.rs new file mode 100644 index 0000000000..b41f9d9ee6 --- /dev/null +++ b/esp32p4/src/efuse/rd_usr_data6.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_USR_DATA6` reader"] +pub type R = crate::R; +#[doc = "Field `USR_DATA6` reader - Stores the sixth 32 bits of BLOCK3 (user)."] +pub type USR_DATA6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the sixth 32 bits of BLOCK3 (user)."] + #[inline(always)] + pub fn usr_data6(&self) -> USR_DATA6_R { + USR_DATA6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_USR_DATA6") + .field("usr_data6", &format_args!("{}", self.usr_data6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_USR_DATA6_SPEC; +impl crate::RegisterSpec for RD_USR_DATA6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_usr_data6::R`](R) reader structure"] +impl crate::Readable for RD_USR_DATA6_SPEC {} +#[doc = "`reset()` method sets RD_USR_DATA6 to value 0"] +impl crate::Resettable for RD_USR_DATA6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_usr_data7.rs b/esp32p4/src/efuse/rd_usr_data7.rs new file mode 100644 index 0000000000..2d2586bbe0 --- /dev/null +++ b/esp32p4/src/efuse/rd_usr_data7.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_USR_DATA7` reader"] +pub type R = crate::R; +#[doc = "Field `USR_DATA7` reader - Stores the seventh 32 bits of BLOCK3 (user)."] +pub type USR_DATA7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the seventh 32 bits of BLOCK3 (user)."] + #[inline(always)] + pub fn usr_data7(&self) -> USR_DATA7_R { + USR_DATA7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_USR_DATA7") + .field("usr_data7", &format_args!("{}", self.usr_data7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_USR_DATA7_SPEC; +impl crate::RegisterSpec for RD_USR_DATA7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_usr_data7::R`](R) reader structure"] +impl crate::Readable for RD_USR_DATA7_SPEC {} +#[doc = "`reset()` method sets RD_USR_DATA7 to value 0"] +impl crate::Resettable for RD_USR_DATA7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/rd_wr_dis.rs b/esp32p4/src/efuse/rd_wr_dis.rs new file mode 100644 index 0000000000..2ebae079b2 --- /dev/null +++ b/esp32p4/src/efuse/rd_wr_dis.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RD_WR_DIS` reader"] +pub type R = crate::R; +#[doc = "Field `WR_DIS` reader - Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled."] +pub type WR_DIS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled."] + #[inline(always)] + pub fn wr_dis(&self) -> WR_DIS_R { + WR_DIS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RD_WR_DIS") + .field("wr_dis", &format_args!("{}", self.wr_dis().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLOCK0 data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_wr_dis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_WR_DIS_SPEC; +impl crate::RegisterSpec for RD_WR_DIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rd_wr_dis::R`](R) reader structure"] +impl crate::Readable for RD_WR_DIS_SPEC {} +#[doc = "`reset()` method sets RD_WR_DIS to value 0"] +impl crate::Resettable for RD_WR_DIS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/status.rs b/esp32p4/src/efuse/status.rs new file mode 100644 index 0000000000..07a6b386d4 --- /dev/null +++ b/esp32p4/src/efuse/status.rs @@ -0,0 +1,118 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `STATE` reader - Indicates the state of the eFuse state machine."] +pub type STATE_R = crate::FieldReader; +#[doc = "Field `OTP_LOAD_SW` reader - The value of OTP_LOAD_SW."] +pub type OTP_LOAD_SW_R = crate::BitReader; +#[doc = "Field `OTP_VDDQ_C_SYNC2` reader - The value of OTP_VDDQ_C_SYNC2."] +pub type OTP_VDDQ_C_SYNC2_R = crate::BitReader; +#[doc = "Field `OTP_STROBE_SW` reader - The value of OTP_STROBE_SW."] +pub type OTP_STROBE_SW_R = crate::BitReader; +#[doc = "Field `OTP_CSB_SW` reader - The value of OTP_CSB_SW."] +pub type OTP_CSB_SW_R = crate::BitReader; +#[doc = "Field `OTP_PGENB_SW` reader - The value of OTP_PGENB_SW."] +pub type OTP_PGENB_SW_R = crate::BitReader; +#[doc = "Field `OTP_VDDQ_IS_SW` reader - The value of OTP_VDDQ_IS_SW."] +pub type OTP_VDDQ_IS_SW_R = crate::BitReader; +#[doc = "Field `BLK0_VALID_BIT_CNT` reader - Indicates the number of block valid bit."] +pub type BLK0_VALID_BIT_CNT_R = crate::FieldReader; +#[doc = "Field `CUR_ECDSA_BLK` reader - Indicates which block is used for ECDSA key output."] +pub type CUR_ECDSA_BLK_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Indicates the state of the eFuse state machine."] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 4 - The value of OTP_LOAD_SW."] + #[inline(always)] + pub fn otp_load_sw(&self) -> OTP_LOAD_SW_R { + OTP_LOAD_SW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The value of OTP_VDDQ_C_SYNC2."] + #[inline(always)] + pub fn otp_vddq_c_sync2(&self) -> OTP_VDDQ_C_SYNC2_R { + OTP_VDDQ_C_SYNC2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The value of OTP_STROBE_SW."] + #[inline(always)] + pub fn otp_strobe_sw(&self) -> OTP_STROBE_SW_R { + OTP_STROBE_SW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The value of OTP_CSB_SW."] + #[inline(always)] + pub fn otp_csb_sw(&self) -> OTP_CSB_SW_R { + OTP_CSB_SW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The value of OTP_PGENB_SW."] + #[inline(always)] + pub fn otp_pgenb_sw(&self) -> OTP_PGENB_SW_R { + OTP_PGENB_SW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The value of OTP_VDDQ_IS_SW."] + #[inline(always)] + pub fn otp_vddq_is_sw(&self) -> OTP_VDDQ_IS_SW_R { + OTP_VDDQ_IS_SW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:19 - Indicates the number of block valid bit."] + #[inline(always)] + pub fn blk0_valid_bit_cnt(&self) -> BLK0_VALID_BIT_CNT_R { + BLK0_VALID_BIT_CNT_R::new(((self.bits >> 10) & 0x03ff) as u16) + } + #[doc = "Bits 20:23 - Indicates which block is used for ECDSA key output."] + #[inline(always)] + pub fn cur_ecdsa_blk(&self) -> CUR_ECDSA_BLK_R { + CUR_ECDSA_BLK_R::new(((self.bits >> 20) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field("state", &format_args!("{}", self.state().bits())) + .field("otp_load_sw", &format_args!("{}", self.otp_load_sw().bit())) + .field( + "otp_vddq_c_sync2", + &format_args!("{}", self.otp_vddq_c_sync2().bit()), + ) + .field( + "otp_strobe_sw", + &format_args!("{}", self.otp_strobe_sw().bit()), + ) + .field("otp_csb_sw", &format_args!("{}", self.otp_csb_sw().bit())) + .field( + "otp_pgenb_sw", + &format_args!("{}", self.otp_pgenb_sw().bit()), + ) + .field( + "otp_vddq_is_sw", + &format_args!("{}", self.otp_vddq_is_sw().bit()), + ) + .field( + "blk0_valid_bit_cnt", + &format_args!("{}", self.blk0_valid_bit_cnt().bits()), + ) + .field( + "cur_ecdsa_blk", + &format_args!("{}", self.cur_ecdsa_blk().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "eFuse status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/efuse/wr_tim_conf0_rs_bypass.rs b/esp32p4/src/efuse/wr_tim_conf0_rs_bypass.rs new file mode 100644 index 0000000000..67d12f5d2a --- /dev/null +++ b/esp32p4/src/efuse/wr_tim_conf0_rs_bypass.rs @@ -0,0 +1,112 @@ +#[doc = "Register `WR_TIM_CONF0_RS_BYPASS` reader"] +pub type R = crate::R; +#[doc = "Register `WR_TIM_CONF0_RS_BYPASS` writer"] +pub type W = crate::W; +#[doc = "Field `BYPASS_RS_CORRECTION` reader - Set this bit to bypass reed solomon correction step."] +pub type BYPASS_RS_CORRECTION_R = crate::BitReader; +#[doc = "Field `BYPASS_RS_CORRECTION` writer - Set this bit to bypass reed solomon correction step."] +pub type BYPASS_RS_CORRECTION_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BYPASS_RS_BLK_NUM` reader - Configures block number of programming twice operation."] +pub type BYPASS_RS_BLK_NUM_R = crate::FieldReader; +#[doc = "Field `BYPASS_RS_BLK_NUM` writer - Configures block number of programming twice operation."] +pub type BYPASS_RS_BLK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `UPDATE` writer - Set this bit to update multi-bit register signals."] +pub type UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TPGM_INACTIVE` reader - Configures the inactive programming time."] +pub type TPGM_INACTIVE_R = crate::FieldReader; +#[doc = "Field `TPGM_INACTIVE` writer - Configures the inactive programming time."] +pub type TPGM_INACTIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - Set this bit to bypass reed solomon correction step."] + #[inline(always)] + pub fn bypass_rs_correction(&self) -> BYPASS_RS_CORRECTION_R { + BYPASS_RS_CORRECTION_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:11 - Configures block number of programming twice operation."] + #[inline(always)] + pub fn bypass_rs_blk_num(&self) -> BYPASS_RS_BLK_NUM_R { + BYPASS_RS_BLK_NUM_R::new(((self.bits >> 1) & 0x07ff) as u16) + } + #[doc = "Bits 13:20 - Configures the inactive programming time."] + #[inline(always)] + pub fn tpgm_inactive(&self) -> TPGM_INACTIVE_R { + TPGM_INACTIVE_R::new(((self.bits >> 13) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WR_TIM_CONF0_RS_BYPASS") + .field( + "bypass_rs_correction", + &format_args!("{}", self.bypass_rs_correction().bit()), + ) + .field( + "bypass_rs_blk_num", + &format_args!("{}", self.bypass_rs_blk_num().bits()), + ) + .field( + "tpgm_inactive", + &format_args!("{}", self.tpgm_inactive().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to bypass reed solomon correction step."] + #[inline(always)] + #[must_use] + pub fn bypass_rs_correction(&mut self) -> BYPASS_RS_CORRECTION_W { + BYPASS_RS_CORRECTION_W::new(self, 0) + } + #[doc = "Bits 1:11 - Configures block number of programming twice operation."] + #[inline(always)] + #[must_use] + pub fn bypass_rs_blk_num(&mut self) -> BYPASS_RS_BLK_NUM_W { + BYPASS_RS_BLK_NUM_W::new(self, 1) + } + #[doc = "Bit 12 - Set this bit to update multi-bit register signals."] + #[inline(always)] + #[must_use] + pub fn update(&mut self) -> UPDATE_W { + UPDATE_W::new(self, 12) + } + #[doc = "Bits 13:20 - Configures the inactive programming time."] + #[inline(always)] + #[must_use] + pub fn tpgm_inactive(&mut self) -> TPGM_INACTIVE_W { + TPGM_INACTIVE_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configurarion register0 of eFuse programming time parameters and rs bypass operation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_tim_conf0_rs_bypass::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_tim_conf0_rs_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WR_TIM_CONF0_RS_BYPASS_SPEC; +impl crate::RegisterSpec for WR_TIM_CONF0_RS_BYPASS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wr_tim_conf0_rs_bypass::R`](R) reader structure"] +impl crate::Readable for WR_TIM_CONF0_RS_BYPASS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wr_tim_conf0_rs_bypass::W`](W) writer structure"] +impl crate::Writable for WR_TIM_CONF0_RS_BYPASS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WR_TIM_CONF0_RS_BYPASS to value 0x2000"] +impl crate::Resettable for WR_TIM_CONF0_RS_BYPASS_SPEC { + const RESET_VALUE: Self::Ux = 0x2000; +} diff --git a/esp32p4/src/efuse/wr_tim_conf1.rs b/esp32p4/src/efuse/wr_tim_conf1.rs new file mode 100644 index 0000000000..15697bb172 --- /dev/null +++ b/esp32p4/src/efuse/wr_tim_conf1.rs @@ -0,0 +1,95 @@ +#[doc = "Register `WR_TIM_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `WR_TIM_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `TSUP_A` reader - Configures the programming setup time."] +pub type TSUP_A_R = crate::FieldReader; +#[doc = "Field `TSUP_A` writer - Configures the programming setup time."] +pub type TSUP_A_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PWR_ON_NUM` reader - Configures the power up time for VDDQ."] +pub type PWR_ON_NUM_R = crate::FieldReader; +#[doc = "Field `PWR_ON_NUM` writer - Configures the power up time for VDDQ."] +pub type PWR_ON_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `THP_A` reader - Configures the programming hold time."] +pub type THP_A_R = crate::FieldReader; +#[doc = "Field `THP_A` writer - Configures the programming hold time."] +pub type THP_A_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures the programming setup time."] + #[inline(always)] + pub fn tsup_a(&self) -> TSUP_A_R { + TSUP_A_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:23 - Configures the power up time for VDDQ."] + #[inline(always)] + pub fn pwr_on_num(&self) -> PWR_ON_NUM_R { + PWR_ON_NUM_R::new(((self.bits >> 8) & 0xffff) as u16) + } + #[doc = "Bits 24:31 - Configures the programming hold time."] + #[inline(always)] + pub fn thp_a(&self) -> THP_A_R { + THP_A_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WR_TIM_CONF1") + .field("tsup_a", &format_args!("{}", self.tsup_a().bits())) + .field("pwr_on_num", &format_args!("{}", self.pwr_on_num().bits())) + .field("thp_a", &format_args!("{}", self.thp_a().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures the programming setup time."] + #[inline(always)] + #[must_use] + pub fn tsup_a(&mut self) -> TSUP_A_W { + TSUP_A_W::new(self, 0) + } + #[doc = "Bits 8:23 - Configures the power up time for VDDQ."] + #[inline(always)] + #[must_use] + pub fn pwr_on_num(&mut self) -> PWR_ON_NUM_W { + PWR_ON_NUM_W::new(self, 8) + } + #[doc = "Bits 24:31 - Configures the programming hold time."] + #[inline(always)] + #[must_use] + pub fn thp_a(&mut self) -> THP_A_W { + THP_A_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configurarion register 1 of eFuse programming timing parameters.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_tim_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_tim_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WR_TIM_CONF1_SPEC; +impl crate::RegisterSpec for WR_TIM_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wr_tim_conf1::R`](R) reader structure"] +impl crate::Readable for WR_TIM_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wr_tim_conf1::W`](W) writer structure"] +impl crate::Writable for WR_TIM_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WR_TIM_CONF1 to value 0x0126_6701"] +impl crate::Resettable for WR_TIM_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x0126_6701; +} diff --git a/esp32p4/src/efuse/wr_tim_conf2.rs b/esp32p4/src/efuse/wr_tim_conf2.rs new file mode 100644 index 0000000000..128de4d74c --- /dev/null +++ b/esp32p4/src/efuse/wr_tim_conf2.rs @@ -0,0 +1,82 @@ +#[doc = "Register `WR_TIM_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `WR_TIM_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `PWR_OFF_NUM` reader - Configures the power outage time for VDDQ."] +pub type PWR_OFF_NUM_R = crate::FieldReader; +#[doc = "Field `PWR_OFF_NUM` writer - Configures the power outage time for VDDQ."] +pub type PWR_OFF_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `TPGM` reader - Configures the active programming time."] +pub type TPGM_R = crate::FieldReader; +#[doc = "Field `TPGM` writer - Configures the active programming time."] +pub type TPGM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures the power outage time for VDDQ."] + #[inline(always)] + pub fn pwr_off_num(&self) -> PWR_OFF_NUM_R { + PWR_OFF_NUM_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Configures the active programming time."] + #[inline(always)] + pub fn tpgm(&self) -> TPGM_R { + TPGM_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WR_TIM_CONF2") + .field( + "pwr_off_num", + &format_args!("{}", self.pwr_off_num().bits()), + ) + .field("tpgm", &format_args!("{}", self.tpgm().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures the power outage time for VDDQ."] + #[inline(always)] + #[must_use] + pub fn pwr_off_num(&mut self) -> PWR_OFF_NUM_W { + PWR_OFF_NUM_W::new(self, 0) + } + #[doc = "Bits 16:31 - Configures the active programming time."] + #[inline(always)] + #[must_use] + pub fn tpgm(&mut self) -> TPGM_W { + TPGM_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configurarion register 2 of eFuse programming timing parameters.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_tim_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_tim_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WR_TIM_CONF2_SPEC; +impl crate::RegisterSpec for WR_TIM_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wr_tim_conf2::R`](R) reader structure"] +impl crate::Readable for WR_TIM_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wr_tim_conf2::W`](W) writer structure"] +impl crate::Writable for WR_TIM_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WR_TIM_CONF2 to value 0x00a0_0140"] +impl crate::Resettable for WR_TIM_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0x00a0_0140; +} diff --git a/esp32p4/src/generic.rs b/esp32p4/src/generic.rs new file mode 100644 index 0000000000..59c8e74749 --- /dev/null +++ b/esp32p4/src/generic.rs @@ -0,0 +1,522 @@ +use core::marker; +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] +pub trait RawReg: + Copy + + Default + + From + + core::ops::BitOr + + core::ops::BitAnd + + core::ops::BitOrAssign + + core::ops::BitAndAssign + + core::ops::Not + + core::ops::Shl +{ + #[doc = " Mask for bits of width `WI`"] + fn mask() -> Self; + #[doc = " Mask for bits of width 1"] + fn one() -> Self; +} +macro_rules! raw_reg { + ($ U : ty , $ size : literal , $ mask : ident) => { + impl RawReg for $U { + #[inline(always)] + fn mask() -> Self { + $mask::() + } + #[inline(always)] + fn one() -> Self { + 1 + } + } + const fn $mask() -> $U { + <$U>::MAX >> ($size - WI) + } + impl FieldSpec for $U { + type Ux = $U; + } + }; +} +raw_reg!(u8, 8, mask_u8); +raw_reg!(u16, 16, mask_u16); +raw_reg!(u32, 32, mask_u32); +raw_reg!(u64, 64, mask_u64); +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: RawReg; +} +#[doc = " Raw field type"] +pub trait FieldSpec: Sized { + #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy + PartialEq + From; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] +pub trait Readable: RegisterSpec {} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; + #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + const RESET_VALUE: Self::Ux; + #[doc = " Reset value of the register."] + #[inline(always)] + fn reset_value() -> Self::Ux { + Self::RESET_VALUE + } +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> R { + R { + bits: self.register.get(), + _reg: marker::PhantomData, + } + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::RESET_VALUE) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }) + .bits, + ); + } +} +impl Reg { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }, + ) + .bits, + ); + } +} +#[doc(hidden)] +pub mod raw; +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub type R = raw::R; +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub const fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy, + REG::Ux: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(®::Ux::from(*other)) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub type W = raw::W; +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = raw::FieldReader; +#[doc = " Bit-wise field reader"] +pub type BitReader = raw::BitReader; +impl FieldReader { + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub const fn bits(&self) -> FI::Ux { + self.bits + } +} +impl PartialEq for FieldReader +where + FI: FieldSpec + Copy, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&FI::Ux::from(*other)) + } +} +impl PartialEq for BitReader +where + FI: Copy, + bool: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&bool::from(*other)) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub const fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub const fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub const fn bit_is_set(&self) -> bool { + self.bit() + } +} +#[doc(hidden)] +pub struct Safe; +#[doc(hidden)] +pub struct Unsafe; +#[doc = " Write field Proxy with unsafe `bits`"] +pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>; +#[doc = " Write field Proxy with safe `bits`"] +pub type FieldWriterSafe<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Safe>; +impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } +} +impl<'a, REG, const WI: u8, FI> FieldWriterSafe<'a, REG, WI, FI> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bits(FI::Ux::from(variant)) + } +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; + impl<'a, REG, FI> $writer<'a, REG, FI> + where + REG: Writable + RegisterSpec, + bool: From, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + Self::WIDTH + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bit(bool::from(variant)) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +impl<'a, REG, FI> BitWriter<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} diff --git a/esp32p4/src/generic/raw.rs b/esp32p4/src/generic/raw.rs new file mode 100644 index 0000000000..81f5779524 --- /dev/null +++ b/esp32p4/src/generic/raw.rs @@ -0,0 +1,93 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} +pub struct BitWriter<'a, REG, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} diff --git a/esp32p4/src/gpio.rs b/esp32p4/src/gpio.rs new file mode 100644 index 0000000000..29012a885c --- /dev/null +++ b/esp32p4/src/gpio.rs @@ -0,0 +1,3007 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + bt_select: BT_SELECT, + out: OUT, + out_w1ts: OUT_W1TS, + out_w1tc: OUT_W1TC, + out1: OUT1, + out1_w1ts: OUT1_W1TS, + out1_w1tc: OUT1_W1TC, + _reserved7: [u8; 0x04], + enable: ENABLE, + enable_w1ts: ENABLE_W1TS, + enable_w1tc: ENABLE_W1TC, + enable1: ENABLE1, + enable1_w1ts: ENABLE1_W1TS, + enable1_w1tc: ENABLE1_W1TC, + strap: STRAP, + in_: IN, + in1: IN1, + status: STATUS, + status_w1ts: STATUS_W1TS, + status_w1tc: STATUS_W1TC, + status1: STATUS1, + status1_w1ts: STATUS1_W1TS, + status1_w1tc: STATUS1_W1TC, + intr_0: INTR_0, + intr1_0: INTR1_0, + intr_1: INTR_1, + intr1_1: INTR1_1, + status_next: STATUS_NEXT, + status_next1: STATUS_NEXT1, + pin: [PIN; 57], + _reserved29: [u8; 0x04], + func1_in_sel_cfg: FUNC1_IN_SEL_CFG, + func2_in_sel_cfg: FUNC2_IN_SEL_CFG, + func3_in_sel_cfg: FUNC3_IN_SEL_CFG, + func4_in_sel_cfg: FUNC4_IN_SEL_CFG, + func5_in_sel_cfg: FUNC5_IN_SEL_CFG, + func6_in_sel_cfg: FUNC6_IN_SEL_CFG, + func7_in_sel_cfg: FUNC7_IN_SEL_CFG, + func8_in_sel_cfg: FUNC8_IN_SEL_CFG, + func9_in_sel_cfg: FUNC9_IN_SEL_CFG, + func10_in_sel_cfg: FUNC10_IN_SEL_CFG, + func11_in_sel_cfg: FUNC11_IN_SEL_CFG, + func12_in_sel_cfg: FUNC12_IN_SEL_CFG, + func13_in_sel_cfg: FUNC13_IN_SEL_CFG, + func14_in_sel_cfg: FUNC14_IN_SEL_CFG, + func15_in_sel_cfg: FUNC15_IN_SEL_CFG, + func16_in_sel_cfg: FUNC16_IN_SEL_CFG, + func17_in_sel_cfg: FUNC17_IN_SEL_CFG, + func18_in_sel_cfg: FUNC18_IN_SEL_CFG, + func19_in_sel_cfg: FUNC19_IN_SEL_CFG, + func20_in_sel_cfg: FUNC20_IN_SEL_CFG, + func21_in_sel_cfg: FUNC21_IN_SEL_CFG, + func22_in_sel_cfg: FUNC22_IN_SEL_CFG, + func23_in_sel_cfg: FUNC23_IN_SEL_CFG, + func24_in_sel_cfg: FUNC24_IN_SEL_CFG, + func25_in_sel_cfg: FUNC25_IN_SEL_CFG, + func26_in_sel_cfg: FUNC26_IN_SEL_CFG, + func27_in_sel_cfg: FUNC27_IN_SEL_CFG, + func28_in_sel_cfg: FUNC28_IN_SEL_CFG, + func29_in_sel_cfg: FUNC29_IN_SEL_CFG, + func30_in_sel_cfg: FUNC30_IN_SEL_CFG, + func31_in_sel_cfg: FUNC31_IN_SEL_CFG, + func32_in_sel_cfg: FUNC32_IN_SEL_CFG, + func33_in_sel_cfg: FUNC33_IN_SEL_CFG, + func34_in_sel_cfg: FUNC34_IN_SEL_CFG, + func35_in_sel_cfg: FUNC35_IN_SEL_CFG, + func36_in_sel_cfg: FUNC36_IN_SEL_CFG, + func37_in_sel_cfg: FUNC37_IN_SEL_CFG, + func38_in_sel_cfg: FUNC38_IN_SEL_CFG, + func39_in_sel_cfg: FUNC39_IN_SEL_CFG, + func40_in_sel_cfg: FUNC40_IN_SEL_CFG, + func41_in_sel_cfg: FUNC41_IN_SEL_CFG, + func42_in_sel_cfg: FUNC42_IN_SEL_CFG, + func43_in_sel_cfg: FUNC43_IN_SEL_CFG, + func44_in_sel_cfg: FUNC44_IN_SEL_CFG, + func45_in_sel_cfg: FUNC45_IN_SEL_CFG, + _reserved74: [u8; 0x04], + func47_in_sel_cfg: FUNC47_IN_SEL_CFG, + func48_in_sel_cfg: FUNC48_IN_SEL_CFG, + func49_in_sel_cfg: FUNC49_IN_SEL_CFG, + func50_in_sel_cfg: FUNC50_IN_SEL_CFG, + func51_in_sel_cfg: FUNC51_IN_SEL_CFG, + func52_in_sel_cfg: FUNC52_IN_SEL_CFG, + func53_in_sel_cfg: FUNC53_IN_SEL_CFG, + func54_in_sel_cfg: FUNC54_IN_SEL_CFG, + func55_in_sel_cfg: FUNC55_IN_SEL_CFG, + func56_in_sel_cfg: FUNC56_IN_SEL_CFG, + func57_in_sel_cfg: FUNC57_IN_SEL_CFG, + func58_in_sel_cfg: FUNC58_IN_SEL_CFG, + func59_in_sel_cfg: FUNC59_IN_SEL_CFG, + func60_in_sel_cfg: FUNC60_IN_SEL_CFG, + func61_in_sel_cfg: FUNC61_IN_SEL_CFG, + func62_in_sel_cfg: FUNC62_IN_SEL_CFG, + func63_in_sel_cfg: FUNC63_IN_SEL_CFG, + func64_in_sel_cfg: FUNC64_IN_SEL_CFG, + func65_in_sel_cfg: FUNC65_IN_SEL_CFG, + func66_in_sel_cfg: FUNC66_IN_SEL_CFG, + _reserved94: [u8; 0x04], + func68_in_sel_cfg: FUNC68_IN_SEL_CFG, + func69_in_sel_cfg: FUNC69_IN_SEL_CFG, + func70_in_sel_cfg: FUNC70_IN_SEL_CFG, + func71_in_sel_cfg: FUNC71_IN_SEL_CFG, + _reserved98: [u8; 0x08], + func74_in_sel_cfg: FUNC74_IN_SEL_CFG, + func75_in_sel_cfg: FUNC75_IN_SEL_CFG, + func76_in_sel_cfg: FUNC76_IN_SEL_CFG, + func77_in_sel_cfg: FUNC77_IN_SEL_CFG, + func78_in_sel_cfg: FUNC78_IN_SEL_CFG, + _reserved103: [u8; 0x04], + func80_in_sel_cfg: FUNC80_IN_SEL_CFG, + _reserved104: [u8; 0x08], + func83_in_sel_cfg: FUNC83_IN_SEL_CFG, + _reserved105: [u8; 0x08], + func86_in_sel_cfg: FUNC86_IN_SEL_CFG, + _reserved106: [u8; 0x08], + func89_in_sel_cfg: FUNC89_IN_SEL_CFG, + func90_in_sel_cfg: FUNC90_IN_SEL_CFG, + func91_in_sel_cfg: FUNC91_IN_SEL_CFG, + func92_in_sel_cfg: FUNC92_IN_SEL_CFG, + func93_in_sel_cfg: FUNC93_IN_SEL_CFG, + func94_in_sel_cfg: FUNC94_IN_SEL_CFG, + func95_in_sel_cfg: FUNC95_IN_SEL_CFG, + func96_in_sel_cfg: FUNC96_IN_SEL_CFG, + func97_in_sel_cfg: FUNC97_IN_SEL_CFG, + func98_in_sel_cfg: FUNC98_IN_SEL_CFG, + func99_in_sel_cfg: FUNC99_IN_SEL_CFG, + func100_in_sel_cfg: FUNC100_IN_SEL_CFG, + func101_in_sel_cfg: FUNC101_IN_SEL_CFG, + func102_in_sel_cfg: FUNC102_IN_SEL_CFG, + func103_in_sel_cfg: FUNC103_IN_SEL_CFG, + func104_in_sel_cfg: FUNC104_IN_SEL_CFG, + func105_in_sel_cfg: FUNC105_IN_SEL_CFG, + func106_in_sel_cfg: FUNC106_IN_SEL_CFG, + func107_in_sel_cfg: FUNC107_IN_SEL_CFG, + func108_in_sel_cfg: FUNC108_IN_SEL_CFG, + func109_in_sel_cfg: FUNC109_IN_SEL_CFG, + func110_in_sel_cfg: FUNC110_IN_SEL_CFG, + func111_in_sel_cfg: FUNC111_IN_SEL_CFG, + func112_in_sel_cfg: FUNC112_IN_SEL_CFG, + func113_in_sel_cfg: FUNC113_IN_SEL_CFG, + func114_in_sel_cfg: FUNC114_IN_SEL_CFG, + _reserved132: [u8; 0x08], + func117_in_sel_cfg: FUNC117_IN_SEL_CFG, + func118_in_sel_cfg: FUNC118_IN_SEL_CFG, + _reserved134: [u8; 0x1c], + func126_in_sel_cfg: FUNC126_IN_SEL_CFG, + func127_in_sel_cfg: FUNC127_IN_SEL_CFG, + func128_in_sel_cfg: FUNC128_IN_SEL_CFG, + func129_in_sel_cfg: FUNC129_IN_SEL_CFG, + func130_in_sel_cfg: FUNC130_IN_SEL_CFG, + func131_in_sel_cfg: FUNC131_IN_SEL_CFG, + func132_in_sel_cfg: FUNC132_IN_SEL_CFG, + func133_in_sel_cfg: FUNC133_IN_SEL_CFG, + func134_in_sel_cfg: FUNC134_IN_SEL_CFG, + func135_in_sel_cfg: FUNC135_IN_SEL_CFG, + func136_in_sel_cfg: FUNC136_IN_SEL_CFG, + func137_in_sel_cfg: FUNC137_IN_SEL_CFG, + func138_in_sel_cfg: FUNC138_IN_SEL_CFG, + func139_in_sel_cfg: FUNC139_IN_SEL_CFG, + func140_in_sel_cfg: FUNC140_IN_SEL_CFG, + func141_in_sel_cfg: FUNC141_IN_SEL_CFG, + func142_in_sel_cfg: FUNC142_IN_SEL_CFG, + func143_in_sel_cfg: FUNC143_IN_SEL_CFG, + func144_in_sel_cfg: FUNC144_IN_SEL_CFG, + func145_in_sel_cfg: FUNC145_IN_SEL_CFG, + func146_in_sel_cfg: FUNC146_IN_SEL_CFG, + func147_in_sel_cfg: FUNC147_IN_SEL_CFG, + func148_in_sel_cfg: FUNC148_IN_SEL_CFG, + func149_in_sel_cfg: FUNC149_IN_SEL_CFG, + func150_in_sel_cfg: FUNC150_IN_SEL_CFG, + func151_in_sel_cfg: FUNC151_IN_SEL_CFG, + func152_in_sel_cfg: FUNC152_IN_SEL_CFG, + func153_in_sel_cfg: FUNC153_IN_SEL_CFG, + func154_in_sel_cfg: FUNC154_IN_SEL_CFG, + func155_in_sel_cfg: FUNC155_IN_SEL_CFG, + func156_in_sel_cfg: FUNC156_IN_SEL_CFG, + _reserved165: [u8; 0x04], + func158_in_sel_cfg: FUNC158_IN_SEL_CFG, + func159_in_sel_cfg: FUNC159_IN_SEL_CFG, + func160_in_sel_cfg: FUNC160_IN_SEL_CFG, + func161_in_sel_cfg: FUNC161_IN_SEL_CFG, + func162_in_sel_cfg: FUNC162_IN_SEL_CFG, + func163_in_sel_cfg: FUNC163_IN_SEL_CFG, + func164_in_sel_cfg: FUNC164_IN_SEL_CFG, + func165_in_sel_cfg: FUNC165_IN_SEL_CFG, + func166_in_sel_cfg: FUNC166_IN_SEL_CFG, + func167_in_sel_cfg: FUNC167_IN_SEL_CFG, + func168_in_sel_cfg: FUNC168_IN_SEL_CFG, + func169_in_sel_cfg: FUNC169_IN_SEL_CFG, + func170_in_sel_cfg: FUNC170_IN_SEL_CFG, + func171_in_sel_cfg: FUNC171_IN_SEL_CFG, + func172_in_sel_cfg: FUNC172_IN_SEL_CFG, + func173_in_sel_cfg: FUNC173_IN_SEL_CFG, + func174_in_sel_cfg: FUNC174_IN_SEL_CFG, + func175_in_sel_cfg: FUNC175_IN_SEL_CFG, + func176_in_sel_cfg: FUNC176_IN_SEL_CFG, + func177_in_sel_cfg: FUNC177_IN_SEL_CFG, + func178_in_sel_cfg: FUNC178_IN_SEL_CFG, + func179_in_sel_cfg: FUNC179_IN_SEL_CFG, + func180_in_sel_cfg: FUNC180_IN_SEL_CFG, + func181_in_sel_cfg: FUNC181_IN_SEL_CFG, + func182_in_sel_cfg: FUNC182_IN_SEL_CFG, + func183_in_sel_cfg: FUNC183_IN_SEL_CFG, + func184_in_sel_cfg: FUNC184_IN_SEL_CFG, + func185_in_sel_cfg: FUNC185_IN_SEL_CFG, + func186_in_sel_cfg: FUNC186_IN_SEL_CFG, + func187_in_sel_cfg: FUNC187_IN_SEL_CFG, + func188_in_sel_cfg: FUNC188_IN_SEL_CFG, + func189_in_sel_cfg: FUNC189_IN_SEL_CFG, + func190_in_sel_cfg: FUNC190_IN_SEL_CFG, + func191_in_sel_cfg: FUNC191_IN_SEL_CFG, + func192_in_sel_cfg: FUNC192_IN_SEL_CFG, + func193_in_sel_cfg: FUNC193_IN_SEL_CFG, + func194_in_sel_cfg: FUNC194_IN_SEL_CFG, + func195_in_sel_cfg: FUNC195_IN_SEL_CFG, + func196_in_sel_cfg: FUNC196_IN_SEL_CFG, + func197_in_sel_cfg: FUNC197_IN_SEL_CFG, + func198_in_sel_cfg: FUNC198_IN_SEL_CFG, + func199_in_sel_cfg: FUNC199_IN_SEL_CFG, + func200_in_sel_cfg: FUNC200_IN_SEL_CFG, + func201_in_sel_cfg: FUNC201_IN_SEL_CFG, + func202_in_sel_cfg: FUNC202_IN_SEL_CFG, + func203_in_sel_cfg: FUNC203_IN_SEL_CFG, + _reserved211: [u8; 0x28], + func214_in_sel_cfg: FUNC214_IN_SEL_CFG, + func215_in_sel_cfg: FUNC215_IN_SEL_CFG, + func216_in_sel_cfg: FUNC216_IN_SEL_CFG, + func217_in_sel_cfg: FUNC217_IN_SEL_CFG, + func218_in_sel_cfg: FUNC218_IN_SEL_CFG, + func219_in_sel_cfg: FUNC219_IN_SEL_CFG, + func220_in_sel_cfg: FUNC220_IN_SEL_CFG, + func221_in_sel_cfg: FUNC221_IN_SEL_CFG, + func222_in_sel_cfg: FUNC222_IN_SEL_CFG, + func223_in_sel_cfg: FUNC223_IN_SEL_CFG, + func224_in_sel_cfg: FUNC224_IN_SEL_CFG, + func225_in_sel_cfg: FUNC225_IN_SEL_CFG, + func226_in_sel_cfg: FUNC226_IN_SEL_CFG, + func227_in_sel_cfg: FUNC227_IN_SEL_CFG, + func228_in_sel_cfg: FUNC228_IN_SEL_CFG, + func229_in_sel_cfg: FUNC229_IN_SEL_CFG, + func230_in_sel_cfg: FUNC230_IN_SEL_CFG, + func231_in_sel_cfg: FUNC231_IN_SEL_CFG, + func232_in_sel_cfg: FUNC232_IN_SEL_CFG, + func233_in_sel_cfg: FUNC233_IN_SEL_CFG, + func234_in_sel_cfg: FUNC234_IN_SEL_CFG, + func235_in_sel_cfg: FUNC235_IN_SEL_CFG, + func236_in_sel_cfg: FUNC236_IN_SEL_CFG, + func237_in_sel_cfg: FUNC237_IN_SEL_CFG, + func238_in_sel_cfg: FUNC238_IN_SEL_CFG, + func239_in_sel_cfg: FUNC239_IN_SEL_CFG, + func240_in_sel_cfg: FUNC240_IN_SEL_CFG, + func241_in_sel_cfg: FUNC241_IN_SEL_CFG, + func242_in_sel_cfg: FUNC242_IN_SEL_CFG, + func243_in_sel_cfg: FUNC243_IN_SEL_CFG, + func244_in_sel_cfg: FUNC244_IN_SEL_CFG, + func245_in_sel_cfg: FUNC245_IN_SEL_CFG, + func246_in_sel_cfg: FUNC246_IN_SEL_CFG, + func247_in_sel_cfg: FUNC247_IN_SEL_CFG, + func248_in_sel_cfg: FUNC248_IN_SEL_CFG, + func249_in_sel_cfg: FUNC249_IN_SEL_CFG, + func250_in_sel_cfg: FUNC250_IN_SEL_CFG, + func251_in_sel_cfg: FUNC251_IN_SEL_CFG, + func252_in_sel_cfg: FUNC252_IN_SEL_CFG, + func253_in_sel_cfg: FUNC253_IN_SEL_CFG, + func254_in_sel_cfg: FUNC254_IN_SEL_CFG, + func255_in_sel_cfg: FUNC255_IN_SEL_CFG, + func_out_sel_cfg: [FUNC_OUT_SEL_CFG; 57], + intr_2: INTR_2, + intr1_2: INTR1_2, + intr_3: INTR_3, + intr1_3: INTR1_3, + clock_gate: CLOCK_GATE, + _reserved259: [u8; 0xb0], + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + zero_det0_filter_cnt: ZERO_DET0_FILTER_CNT, + zero_det1_filter_cnt: ZERO_DET1_FILTER_CNT, + send_seq: SEND_SEQ, + recive_seq: RECIVE_SEQ, + bistin_sel: BISTIN_SEL, + bist_ctrl: BIST_CTRL, + _reserved269: [u8; 0xd4], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - GPIO bit select register"] + #[inline(always)] + pub const fn bt_select(&self) -> &BT_SELECT { + &self.bt_select + } + #[doc = "0x04 - GPIO output register for GPIO0-31"] + #[inline(always)] + pub const fn out(&self) -> &OUT { + &self.out + } + #[doc = "0x08 - GPIO output set register for GPIO0-31"] + #[inline(always)] + pub const fn out_w1ts(&self) -> &OUT_W1TS { + &self.out_w1ts + } + #[doc = "0x0c - GPIO output clear register for GPIO0-31"] + #[inline(always)] + pub const fn out_w1tc(&self) -> &OUT_W1TC { + &self.out_w1tc + } + #[doc = "0x10 - GPIO output register for GPIO32-56"] + #[inline(always)] + pub const fn out1(&self) -> &OUT1 { + &self.out1 + } + #[doc = "0x14 - GPIO output set register for GPIO32-56"] + #[inline(always)] + pub const fn out1_w1ts(&self) -> &OUT1_W1TS { + &self.out1_w1ts + } + #[doc = "0x18 - GPIO output clear register for GPIO32-56"] + #[inline(always)] + pub const fn out1_w1tc(&self) -> &OUT1_W1TC { + &self.out1_w1tc + } + #[doc = "0x20 - GPIO output enable register for GPIO0-31"] + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } + #[doc = "0x24 - GPIO output enable set register for GPIO0-31"] + #[inline(always)] + pub const fn enable_w1ts(&self) -> &ENABLE_W1TS { + &self.enable_w1ts + } + #[doc = "0x28 - GPIO output enable clear register for GPIO0-31"] + #[inline(always)] + pub const fn enable_w1tc(&self) -> &ENABLE_W1TC { + &self.enable_w1tc + } + #[doc = "0x2c - GPIO output enable register for GPIO32-56"] + #[inline(always)] + pub const fn enable1(&self) -> &ENABLE1 { + &self.enable1 + } + #[doc = "0x30 - GPIO output enable set register for GPIO32-56"] + #[inline(always)] + pub const fn enable1_w1ts(&self) -> &ENABLE1_W1TS { + &self.enable1_w1ts + } + #[doc = "0x34 - GPIO output enable clear register for GPIO32-56"] + #[inline(always)] + pub const fn enable1_w1tc(&self) -> &ENABLE1_W1TC { + &self.enable1_w1tc + } + #[doc = "0x38 - pad strapping register"] + #[inline(always)] + pub const fn strap(&self) -> &STRAP { + &self.strap + } + #[doc = "0x3c - GPIO input register for GPIO0-31"] + #[inline(always)] + pub const fn in_(&self) -> &IN { + &self.in_ + } + #[doc = "0x40 - GPIO input register for GPIO32-56"] + #[inline(always)] + pub const fn in1(&self) -> &IN1 { + &self.in1 + } + #[doc = "0x44 - GPIO interrupt status register for GPIO0-31"] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0x48 - GPIO interrupt status set register for GPIO0-31"] + #[inline(always)] + pub const fn status_w1ts(&self) -> &STATUS_W1TS { + &self.status_w1ts + } + #[doc = "0x4c - GPIO interrupt status clear register for GPIO0-31"] + #[inline(always)] + pub const fn status_w1tc(&self) -> &STATUS_W1TC { + &self.status_w1tc + } + #[doc = "0x50 - GPIO interrupt status register for GPIO32-56"] + #[inline(always)] + pub const fn status1(&self) -> &STATUS1 { + &self.status1 + } + #[doc = "0x54 - GPIO interrupt status set register for GPIO32-56"] + #[inline(always)] + pub const fn status1_w1ts(&self) -> &STATUS1_W1TS { + &self.status1_w1ts + } + #[doc = "0x58 - GPIO interrupt status clear register for GPIO32-56"] + #[inline(always)] + pub const fn status1_w1tc(&self) -> &STATUS1_W1TC { + &self.status1_w1tc + } + #[doc = "0x5c - GPIO interrupt 0 status register for GPIO0-31"] + #[inline(always)] + pub const fn intr_0(&self) -> &INTR_0 { + &self.intr_0 + } + #[doc = "0x60 - GPIO interrupt 0 status register for GPIO32-56"] + #[inline(always)] + pub const fn intr1_0(&self) -> &INTR1_0 { + &self.intr1_0 + } + #[doc = "0x64 - GPIO interrupt 1 status register for GPIO0-31"] + #[inline(always)] + pub const fn intr_1(&self) -> &INTR_1 { + &self.intr_1 + } + #[doc = "0x68 - GPIO interrupt 1 status register for GPIO32-56"] + #[inline(always)] + pub const fn intr1_1(&self) -> &INTR1_1 { + &self.intr1_1 + } + #[doc = "0x6c - GPIO interrupt source register for GPIO0-31"] + #[inline(always)] + pub const fn status_next(&self) -> &STATUS_NEXT { + &self.status_next + } + #[doc = "0x70 - GPIO interrupt source register for GPIO32-56"] + #[inline(always)] + pub const fn status_next1(&self) -> &STATUS_NEXT1 { + &self.status_next1 + } + #[doc = "0x74..0x158 - GPIO pin configuration register"] + #[inline(always)] + pub const fn pin(&self, n: usize) -> &PIN { + &self.pin[n] + } + #[doc = "0x15c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func1_in_sel_cfg(&self) -> &FUNC1_IN_SEL_CFG { + &self.func1_in_sel_cfg + } + #[doc = "0x160 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func2_in_sel_cfg(&self) -> &FUNC2_IN_SEL_CFG { + &self.func2_in_sel_cfg + } + #[doc = "0x164 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func3_in_sel_cfg(&self) -> &FUNC3_IN_SEL_CFG { + &self.func3_in_sel_cfg + } + #[doc = "0x168 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func4_in_sel_cfg(&self) -> &FUNC4_IN_SEL_CFG { + &self.func4_in_sel_cfg + } + #[doc = "0x16c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func5_in_sel_cfg(&self) -> &FUNC5_IN_SEL_CFG { + &self.func5_in_sel_cfg + } + #[doc = "0x170 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func6_in_sel_cfg(&self) -> &FUNC6_IN_SEL_CFG { + &self.func6_in_sel_cfg + } + #[doc = "0x174 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func7_in_sel_cfg(&self) -> &FUNC7_IN_SEL_CFG { + &self.func7_in_sel_cfg + } + #[doc = "0x178 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func8_in_sel_cfg(&self) -> &FUNC8_IN_SEL_CFG { + &self.func8_in_sel_cfg + } + #[doc = "0x17c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func9_in_sel_cfg(&self) -> &FUNC9_IN_SEL_CFG { + &self.func9_in_sel_cfg + } + #[doc = "0x180 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func10_in_sel_cfg(&self) -> &FUNC10_IN_SEL_CFG { + &self.func10_in_sel_cfg + } + #[doc = "0x184 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func11_in_sel_cfg(&self) -> &FUNC11_IN_SEL_CFG { + &self.func11_in_sel_cfg + } + #[doc = "0x188 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func12_in_sel_cfg(&self) -> &FUNC12_IN_SEL_CFG { + &self.func12_in_sel_cfg + } + #[doc = "0x18c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func13_in_sel_cfg(&self) -> &FUNC13_IN_SEL_CFG { + &self.func13_in_sel_cfg + } + #[doc = "0x190 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func14_in_sel_cfg(&self) -> &FUNC14_IN_SEL_CFG { + &self.func14_in_sel_cfg + } + #[doc = "0x194 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func15_in_sel_cfg(&self) -> &FUNC15_IN_SEL_CFG { + &self.func15_in_sel_cfg + } + #[doc = "0x198 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func16_in_sel_cfg(&self) -> &FUNC16_IN_SEL_CFG { + &self.func16_in_sel_cfg + } + #[doc = "0x19c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func17_in_sel_cfg(&self) -> &FUNC17_IN_SEL_CFG { + &self.func17_in_sel_cfg + } + #[doc = "0x1a0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func18_in_sel_cfg(&self) -> &FUNC18_IN_SEL_CFG { + &self.func18_in_sel_cfg + } + #[doc = "0x1a4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func19_in_sel_cfg(&self) -> &FUNC19_IN_SEL_CFG { + &self.func19_in_sel_cfg + } + #[doc = "0x1a8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func20_in_sel_cfg(&self) -> &FUNC20_IN_SEL_CFG { + &self.func20_in_sel_cfg + } + #[doc = "0x1ac - GPIO input function configuration register"] + #[inline(always)] + pub const fn func21_in_sel_cfg(&self) -> &FUNC21_IN_SEL_CFG { + &self.func21_in_sel_cfg + } + #[doc = "0x1b0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func22_in_sel_cfg(&self) -> &FUNC22_IN_SEL_CFG { + &self.func22_in_sel_cfg + } + #[doc = "0x1b4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func23_in_sel_cfg(&self) -> &FUNC23_IN_SEL_CFG { + &self.func23_in_sel_cfg + } + #[doc = "0x1b8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func24_in_sel_cfg(&self) -> &FUNC24_IN_SEL_CFG { + &self.func24_in_sel_cfg + } + #[doc = "0x1bc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func25_in_sel_cfg(&self) -> &FUNC25_IN_SEL_CFG { + &self.func25_in_sel_cfg + } + #[doc = "0x1c0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func26_in_sel_cfg(&self) -> &FUNC26_IN_SEL_CFG { + &self.func26_in_sel_cfg + } + #[doc = "0x1c4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func27_in_sel_cfg(&self) -> &FUNC27_IN_SEL_CFG { + &self.func27_in_sel_cfg + } + #[doc = "0x1c8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func28_in_sel_cfg(&self) -> &FUNC28_IN_SEL_CFG { + &self.func28_in_sel_cfg + } + #[doc = "0x1cc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func29_in_sel_cfg(&self) -> &FUNC29_IN_SEL_CFG { + &self.func29_in_sel_cfg + } + #[doc = "0x1d0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func30_in_sel_cfg(&self) -> &FUNC30_IN_SEL_CFG { + &self.func30_in_sel_cfg + } + #[doc = "0x1d4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func31_in_sel_cfg(&self) -> &FUNC31_IN_SEL_CFG { + &self.func31_in_sel_cfg + } + #[doc = "0x1d8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func32_in_sel_cfg(&self) -> &FUNC32_IN_SEL_CFG { + &self.func32_in_sel_cfg + } + #[doc = "0x1dc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func33_in_sel_cfg(&self) -> &FUNC33_IN_SEL_CFG { + &self.func33_in_sel_cfg + } + #[doc = "0x1e0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func34_in_sel_cfg(&self) -> &FUNC34_IN_SEL_CFG { + &self.func34_in_sel_cfg + } + #[doc = "0x1e4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func35_in_sel_cfg(&self) -> &FUNC35_IN_SEL_CFG { + &self.func35_in_sel_cfg + } + #[doc = "0x1e8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func36_in_sel_cfg(&self) -> &FUNC36_IN_SEL_CFG { + &self.func36_in_sel_cfg + } + #[doc = "0x1ec - GPIO input function configuration register"] + #[inline(always)] + pub const fn func37_in_sel_cfg(&self) -> &FUNC37_IN_SEL_CFG { + &self.func37_in_sel_cfg + } + #[doc = "0x1f0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func38_in_sel_cfg(&self) -> &FUNC38_IN_SEL_CFG { + &self.func38_in_sel_cfg + } + #[doc = "0x1f4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func39_in_sel_cfg(&self) -> &FUNC39_IN_SEL_CFG { + &self.func39_in_sel_cfg + } + #[doc = "0x1f8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func40_in_sel_cfg(&self) -> &FUNC40_IN_SEL_CFG { + &self.func40_in_sel_cfg + } + #[doc = "0x1fc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func41_in_sel_cfg(&self) -> &FUNC41_IN_SEL_CFG { + &self.func41_in_sel_cfg + } + #[doc = "0x200 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func42_in_sel_cfg(&self) -> &FUNC42_IN_SEL_CFG { + &self.func42_in_sel_cfg + } + #[doc = "0x204 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func43_in_sel_cfg(&self) -> &FUNC43_IN_SEL_CFG { + &self.func43_in_sel_cfg + } + #[doc = "0x208 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func44_in_sel_cfg(&self) -> &FUNC44_IN_SEL_CFG { + &self.func44_in_sel_cfg + } + #[doc = "0x20c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func45_in_sel_cfg(&self) -> &FUNC45_IN_SEL_CFG { + &self.func45_in_sel_cfg + } + #[doc = "0x214 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func47_in_sel_cfg(&self) -> &FUNC47_IN_SEL_CFG { + &self.func47_in_sel_cfg + } + #[doc = "0x218 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func48_in_sel_cfg(&self) -> &FUNC48_IN_SEL_CFG { + &self.func48_in_sel_cfg + } + #[doc = "0x21c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func49_in_sel_cfg(&self) -> &FUNC49_IN_SEL_CFG { + &self.func49_in_sel_cfg + } + #[doc = "0x220 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func50_in_sel_cfg(&self) -> &FUNC50_IN_SEL_CFG { + &self.func50_in_sel_cfg + } + #[doc = "0x224 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func51_in_sel_cfg(&self) -> &FUNC51_IN_SEL_CFG { + &self.func51_in_sel_cfg + } + #[doc = "0x228 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func52_in_sel_cfg(&self) -> &FUNC52_IN_SEL_CFG { + &self.func52_in_sel_cfg + } + #[doc = "0x22c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func53_in_sel_cfg(&self) -> &FUNC53_IN_SEL_CFG { + &self.func53_in_sel_cfg + } + #[doc = "0x230 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func54_in_sel_cfg(&self) -> &FUNC54_IN_SEL_CFG { + &self.func54_in_sel_cfg + } + #[doc = "0x234 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func55_in_sel_cfg(&self) -> &FUNC55_IN_SEL_CFG { + &self.func55_in_sel_cfg + } + #[doc = "0x238 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func56_in_sel_cfg(&self) -> &FUNC56_IN_SEL_CFG { + &self.func56_in_sel_cfg + } + #[doc = "0x23c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func57_in_sel_cfg(&self) -> &FUNC57_IN_SEL_CFG { + &self.func57_in_sel_cfg + } + #[doc = "0x240 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func58_in_sel_cfg(&self) -> &FUNC58_IN_SEL_CFG { + &self.func58_in_sel_cfg + } + #[doc = "0x244 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func59_in_sel_cfg(&self) -> &FUNC59_IN_SEL_CFG { + &self.func59_in_sel_cfg + } + #[doc = "0x248 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func60_in_sel_cfg(&self) -> &FUNC60_IN_SEL_CFG { + &self.func60_in_sel_cfg + } + #[doc = "0x24c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func61_in_sel_cfg(&self) -> &FUNC61_IN_SEL_CFG { + &self.func61_in_sel_cfg + } + #[doc = "0x250 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func62_in_sel_cfg(&self) -> &FUNC62_IN_SEL_CFG { + &self.func62_in_sel_cfg + } + #[doc = "0x254 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func63_in_sel_cfg(&self) -> &FUNC63_IN_SEL_CFG { + &self.func63_in_sel_cfg + } + #[doc = "0x258 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func64_in_sel_cfg(&self) -> &FUNC64_IN_SEL_CFG { + &self.func64_in_sel_cfg + } + #[doc = "0x25c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func65_in_sel_cfg(&self) -> &FUNC65_IN_SEL_CFG { + &self.func65_in_sel_cfg + } + #[doc = "0x260 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func66_in_sel_cfg(&self) -> &FUNC66_IN_SEL_CFG { + &self.func66_in_sel_cfg + } + #[doc = "0x268 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func68_in_sel_cfg(&self) -> &FUNC68_IN_SEL_CFG { + &self.func68_in_sel_cfg + } + #[doc = "0x26c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func69_in_sel_cfg(&self) -> &FUNC69_IN_SEL_CFG { + &self.func69_in_sel_cfg + } + #[doc = "0x270 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func70_in_sel_cfg(&self) -> &FUNC70_IN_SEL_CFG { + &self.func70_in_sel_cfg + } + #[doc = "0x274 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func71_in_sel_cfg(&self) -> &FUNC71_IN_SEL_CFG { + &self.func71_in_sel_cfg + } + #[doc = "0x280 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func74_in_sel_cfg(&self) -> &FUNC74_IN_SEL_CFG { + &self.func74_in_sel_cfg + } + #[doc = "0x284 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func75_in_sel_cfg(&self) -> &FUNC75_IN_SEL_CFG { + &self.func75_in_sel_cfg + } + #[doc = "0x288 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func76_in_sel_cfg(&self) -> &FUNC76_IN_SEL_CFG { + &self.func76_in_sel_cfg + } + #[doc = "0x28c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func77_in_sel_cfg(&self) -> &FUNC77_IN_SEL_CFG { + &self.func77_in_sel_cfg + } + #[doc = "0x290 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func78_in_sel_cfg(&self) -> &FUNC78_IN_SEL_CFG { + &self.func78_in_sel_cfg + } + #[doc = "0x298 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func80_in_sel_cfg(&self) -> &FUNC80_IN_SEL_CFG { + &self.func80_in_sel_cfg + } + #[doc = "0x2a4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func83_in_sel_cfg(&self) -> &FUNC83_IN_SEL_CFG { + &self.func83_in_sel_cfg + } + #[doc = "0x2b0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func86_in_sel_cfg(&self) -> &FUNC86_IN_SEL_CFG { + &self.func86_in_sel_cfg + } + #[doc = "0x2bc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func89_in_sel_cfg(&self) -> &FUNC89_IN_SEL_CFG { + &self.func89_in_sel_cfg + } + #[doc = "0x2c0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func90_in_sel_cfg(&self) -> &FUNC90_IN_SEL_CFG { + &self.func90_in_sel_cfg + } + #[doc = "0x2c4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func91_in_sel_cfg(&self) -> &FUNC91_IN_SEL_CFG { + &self.func91_in_sel_cfg + } + #[doc = "0x2c8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func92_in_sel_cfg(&self) -> &FUNC92_IN_SEL_CFG { + &self.func92_in_sel_cfg + } + #[doc = "0x2cc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func93_in_sel_cfg(&self) -> &FUNC93_IN_SEL_CFG { + &self.func93_in_sel_cfg + } + #[doc = "0x2d0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func94_in_sel_cfg(&self) -> &FUNC94_IN_SEL_CFG { + &self.func94_in_sel_cfg + } + #[doc = "0x2d4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func95_in_sel_cfg(&self) -> &FUNC95_IN_SEL_CFG { + &self.func95_in_sel_cfg + } + #[doc = "0x2d8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func96_in_sel_cfg(&self) -> &FUNC96_IN_SEL_CFG { + &self.func96_in_sel_cfg + } + #[doc = "0x2dc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func97_in_sel_cfg(&self) -> &FUNC97_IN_SEL_CFG { + &self.func97_in_sel_cfg + } + #[doc = "0x2e0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func98_in_sel_cfg(&self) -> &FUNC98_IN_SEL_CFG { + &self.func98_in_sel_cfg + } + #[doc = "0x2e4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func99_in_sel_cfg(&self) -> &FUNC99_IN_SEL_CFG { + &self.func99_in_sel_cfg + } + #[doc = "0x2e8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func100_in_sel_cfg(&self) -> &FUNC100_IN_SEL_CFG { + &self.func100_in_sel_cfg + } + #[doc = "0x2ec - GPIO input function configuration register"] + #[inline(always)] + pub const fn func101_in_sel_cfg(&self) -> &FUNC101_IN_SEL_CFG { + &self.func101_in_sel_cfg + } + #[doc = "0x2f0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func102_in_sel_cfg(&self) -> &FUNC102_IN_SEL_CFG { + &self.func102_in_sel_cfg + } + #[doc = "0x2f4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func103_in_sel_cfg(&self) -> &FUNC103_IN_SEL_CFG { + &self.func103_in_sel_cfg + } + #[doc = "0x2f8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func104_in_sel_cfg(&self) -> &FUNC104_IN_SEL_CFG { + &self.func104_in_sel_cfg + } + #[doc = "0x2fc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func105_in_sel_cfg(&self) -> &FUNC105_IN_SEL_CFG { + &self.func105_in_sel_cfg + } + #[doc = "0x300 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func106_in_sel_cfg(&self) -> &FUNC106_IN_SEL_CFG { + &self.func106_in_sel_cfg + } + #[doc = "0x304 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func107_in_sel_cfg(&self) -> &FUNC107_IN_SEL_CFG { + &self.func107_in_sel_cfg + } + #[doc = "0x308 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func108_in_sel_cfg(&self) -> &FUNC108_IN_SEL_CFG { + &self.func108_in_sel_cfg + } + #[doc = "0x30c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func109_in_sel_cfg(&self) -> &FUNC109_IN_SEL_CFG { + &self.func109_in_sel_cfg + } + #[doc = "0x310 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func110_in_sel_cfg(&self) -> &FUNC110_IN_SEL_CFG { + &self.func110_in_sel_cfg + } + #[doc = "0x314 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func111_in_sel_cfg(&self) -> &FUNC111_IN_SEL_CFG { + &self.func111_in_sel_cfg + } + #[doc = "0x318 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func112_in_sel_cfg(&self) -> &FUNC112_IN_SEL_CFG { + &self.func112_in_sel_cfg + } + #[doc = "0x31c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func113_in_sel_cfg(&self) -> &FUNC113_IN_SEL_CFG { + &self.func113_in_sel_cfg + } + #[doc = "0x320 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func114_in_sel_cfg(&self) -> &FUNC114_IN_SEL_CFG { + &self.func114_in_sel_cfg + } + #[doc = "0x32c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func117_in_sel_cfg(&self) -> &FUNC117_IN_SEL_CFG { + &self.func117_in_sel_cfg + } + #[doc = "0x330 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func118_in_sel_cfg(&self) -> &FUNC118_IN_SEL_CFG { + &self.func118_in_sel_cfg + } + #[doc = "0x350 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func126_in_sel_cfg(&self) -> &FUNC126_IN_SEL_CFG { + &self.func126_in_sel_cfg + } + #[doc = "0x354 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func127_in_sel_cfg(&self) -> &FUNC127_IN_SEL_CFG { + &self.func127_in_sel_cfg + } + #[doc = "0x358 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func128_in_sel_cfg(&self) -> &FUNC128_IN_SEL_CFG { + &self.func128_in_sel_cfg + } + #[doc = "0x35c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func129_in_sel_cfg(&self) -> &FUNC129_IN_SEL_CFG { + &self.func129_in_sel_cfg + } + #[doc = "0x360 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func130_in_sel_cfg(&self) -> &FUNC130_IN_SEL_CFG { + &self.func130_in_sel_cfg + } + #[doc = "0x364 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func131_in_sel_cfg(&self) -> &FUNC131_IN_SEL_CFG { + &self.func131_in_sel_cfg + } + #[doc = "0x368 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func132_in_sel_cfg(&self) -> &FUNC132_IN_SEL_CFG { + &self.func132_in_sel_cfg + } + #[doc = "0x36c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func133_in_sel_cfg(&self) -> &FUNC133_IN_SEL_CFG { + &self.func133_in_sel_cfg + } + #[doc = "0x370 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func134_in_sel_cfg(&self) -> &FUNC134_IN_SEL_CFG { + &self.func134_in_sel_cfg + } + #[doc = "0x374 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func135_in_sel_cfg(&self) -> &FUNC135_IN_SEL_CFG { + &self.func135_in_sel_cfg + } + #[doc = "0x378 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func136_in_sel_cfg(&self) -> &FUNC136_IN_SEL_CFG { + &self.func136_in_sel_cfg + } + #[doc = "0x37c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func137_in_sel_cfg(&self) -> &FUNC137_IN_SEL_CFG { + &self.func137_in_sel_cfg + } + #[doc = "0x380 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func138_in_sel_cfg(&self) -> &FUNC138_IN_SEL_CFG { + &self.func138_in_sel_cfg + } + #[doc = "0x384 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func139_in_sel_cfg(&self) -> &FUNC139_IN_SEL_CFG { + &self.func139_in_sel_cfg + } + #[doc = "0x388 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func140_in_sel_cfg(&self) -> &FUNC140_IN_SEL_CFG { + &self.func140_in_sel_cfg + } + #[doc = "0x38c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func141_in_sel_cfg(&self) -> &FUNC141_IN_SEL_CFG { + &self.func141_in_sel_cfg + } + #[doc = "0x390 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func142_in_sel_cfg(&self) -> &FUNC142_IN_SEL_CFG { + &self.func142_in_sel_cfg + } + #[doc = "0x394 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func143_in_sel_cfg(&self) -> &FUNC143_IN_SEL_CFG { + &self.func143_in_sel_cfg + } + #[doc = "0x398 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func144_in_sel_cfg(&self) -> &FUNC144_IN_SEL_CFG { + &self.func144_in_sel_cfg + } + #[doc = "0x39c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func145_in_sel_cfg(&self) -> &FUNC145_IN_SEL_CFG { + &self.func145_in_sel_cfg + } + #[doc = "0x3a0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func146_in_sel_cfg(&self) -> &FUNC146_IN_SEL_CFG { + &self.func146_in_sel_cfg + } + #[doc = "0x3a4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func147_in_sel_cfg(&self) -> &FUNC147_IN_SEL_CFG { + &self.func147_in_sel_cfg + } + #[doc = "0x3a8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func148_in_sel_cfg(&self) -> &FUNC148_IN_SEL_CFG { + &self.func148_in_sel_cfg + } + #[doc = "0x3ac - GPIO input function configuration register"] + #[inline(always)] + pub const fn func149_in_sel_cfg(&self) -> &FUNC149_IN_SEL_CFG { + &self.func149_in_sel_cfg + } + #[doc = "0x3b0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func150_in_sel_cfg(&self) -> &FUNC150_IN_SEL_CFG { + &self.func150_in_sel_cfg + } + #[doc = "0x3b4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func151_in_sel_cfg(&self) -> &FUNC151_IN_SEL_CFG { + &self.func151_in_sel_cfg + } + #[doc = "0x3b8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func152_in_sel_cfg(&self) -> &FUNC152_IN_SEL_CFG { + &self.func152_in_sel_cfg + } + #[doc = "0x3bc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func153_in_sel_cfg(&self) -> &FUNC153_IN_SEL_CFG { + &self.func153_in_sel_cfg + } + #[doc = "0x3c0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func154_in_sel_cfg(&self) -> &FUNC154_IN_SEL_CFG { + &self.func154_in_sel_cfg + } + #[doc = "0x3c4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func155_in_sel_cfg(&self) -> &FUNC155_IN_SEL_CFG { + &self.func155_in_sel_cfg + } + #[doc = "0x3c8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func156_in_sel_cfg(&self) -> &FUNC156_IN_SEL_CFG { + &self.func156_in_sel_cfg + } + #[doc = "0x3d0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func158_in_sel_cfg(&self) -> &FUNC158_IN_SEL_CFG { + &self.func158_in_sel_cfg + } + #[doc = "0x3d4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func159_in_sel_cfg(&self) -> &FUNC159_IN_SEL_CFG { + &self.func159_in_sel_cfg + } + #[doc = "0x3d8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func160_in_sel_cfg(&self) -> &FUNC160_IN_SEL_CFG { + &self.func160_in_sel_cfg + } + #[doc = "0x3dc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func161_in_sel_cfg(&self) -> &FUNC161_IN_SEL_CFG { + &self.func161_in_sel_cfg + } + #[doc = "0x3e0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func162_in_sel_cfg(&self) -> &FUNC162_IN_SEL_CFG { + &self.func162_in_sel_cfg + } + #[doc = "0x3e4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func163_in_sel_cfg(&self) -> &FUNC163_IN_SEL_CFG { + &self.func163_in_sel_cfg + } + #[doc = "0x3e8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func164_in_sel_cfg(&self) -> &FUNC164_IN_SEL_CFG { + &self.func164_in_sel_cfg + } + #[doc = "0x3ec - GPIO input function configuration register"] + #[inline(always)] + pub const fn func165_in_sel_cfg(&self) -> &FUNC165_IN_SEL_CFG { + &self.func165_in_sel_cfg + } + #[doc = "0x3f0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func166_in_sel_cfg(&self) -> &FUNC166_IN_SEL_CFG { + &self.func166_in_sel_cfg + } + #[doc = "0x3f4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func167_in_sel_cfg(&self) -> &FUNC167_IN_SEL_CFG { + &self.func167_in_sel_cfg + } + #[doc = "0x3f8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func168_in_sel_cfg(&self) -> &FUNC168_IN_SEL_CFG { + &self.func168_in_sel_cfg + } + #[doc = "0x3fc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func169_in_sel_cfg(&self) -> &FUNC169_IN_SEL_CFG { + &self.func169_in_sel_cfg + } + #[doc = "0x400 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func170_in_sel_cfg(&self) -> &FUNC170_IN_SEL_CFG { + &self.func170_in_sel_cfg + } + #[doc = "0x404 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func171_in_sel_cfg(&self) -> &FUNC171_IN_SEL_CFG { + &self.func171_in_sel_cfg + } + #[doc = "0x408 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func172_in_sel_cfg(&self) -> &FUNC172_IN_SEL_CFG { + &self.func172_in_sel_cfg + } + #[doc = "0x40c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func173_in_sel_cfg(&self) -> &FUNC173_IN_SEL_CFG { + &self.func173_in_sel_cfg + } + #[doc = "0x410 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func174_in_sel_cfg(&self) -> &FUNC174_IN_SEL_CFG { + &self.func174_in_sel_cfg + } + #[doc = "0x414 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func175_in_sel_cfg(&self) -> &FUNC175_IN_SEL_CFG { + &self.func175_in_sel_cfg + } + #[doc = "0x418 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func176_in_sel_cfg(&self) -> &FUNC176_IN_SEL_CFG { + &self.func176_in_sel_cfg + } + #[doc = "0x41c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func177_in_sel_cfg(&self) -> &FUNC177_IN_SEL_CFG { + &self.func177_in_sel_cfg + } + #[doc = "0x420 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func178_in_sel_cfg(&self) -> &FUNC178_IN_SEL_CFG { + &self.func178_in_sel_cfg + } + #[doc = "0x424 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func179_in_sel_cfg(&self) -> &FUNC179_IN_SEL_CFG { + &self.func179_in_sel_cfg + } + #[doc = "0x428 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func180_in_sel_cfg(&self) -> &FUNC180_IN_SEL_CFG { + &self.func180_in_sel_cfg + } + #[doc = "0x42c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func181_in_sel_cfg(&self) -> &FUNC181_IN_SEL_CFG { + &self.func181_in_sel_cfg + } + #[doc = "0x430 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func182_in_sel_cfg(&self) -> &FUNC182_IN_SEL_CFG { + &self.func182_in_sel_cfg + } + #[doc = "0x434 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func183_in_sel_cfg(&self) -> &FUNC183_IN_SEL_CFG { + &self.func183_in_sel_cfg + } + #[doc = "0x438 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func184_in_sel_cfg(&self) -> &FUNC184_IN_SEL_CFG { + &self.func184_in_sel_cfg + } + #[doc = "0x43c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func185_in_sel_cfg(&self) -> &FUNC185_IN_SEL_CFG { + &self.func185_in_sel_cfg + } + #[doc = "0x440 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func186_in_sel_cfg(&self) -> &FUNC186_IN_SEL_CFG { + &self.func186_in_sel_cfg + } + #[doc = "0x444 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func187_in_sel_cfg(&self) -> &FUNC187_IN_SEL_CFG { + &self.func187_in_sel_cfg + } + #[doc = "0x448 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func188_in_sel_cfg(&self) -> &FUNC188_IN_SEL_CFG { + &self.func188_in_sel_cfg + } + #[doc = "0x44c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func189_in_sel_cfg(&self) -> &FUNC189_IN_SEL_CFG { + &self.func189_in_sel_cfg + } + #[doc = "0x450 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func190_in_sel_cfg(&self) -> &FUNC190_IN_SEL_CFG { + &self.func190_in_sel_cfg + } + #[doc = "0x454 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func191_in_sel_cfg(&self) -> &FUNC191_IN_SEL_CFG { + &self.func191_in_sel_cfg + } + #[doc = "0x458 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func192_in_sel_cfg(&self) -> &FUNC192_IN_SEL_CFG { + &self.func192_in_sel_cfg + } + #[doc = "0x45c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func193_in_sel_cfg(&self) -> &FUNC193_IN_SEL_CFG { + &self.func193_in_sel_cfg + } + #[doc = "0x460 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func194_in_sel_cfg(&self) -> &FUNC194_IN_SEL_CFG { + &self.func194_in_sel_cfg + } + #[doc = "0x464 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func195_in_sel_cfg(&self) -> &FUNC195_IN_SEL_CFG { + &self.func195_in_sel_cfg + } + #[doc = "0x468 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func196_in_sel_cfg(&self) -> &FUNC196_IN_SEL_CFG { + &self.func196_in_sel_cfg + } + #[doc = "0x46c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func197_in_sel_cfg(&self) -> &FUNC197_IN_SEL_CFG { + &self.func197_in_sel_cfg + } + #[doc = "0x470 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func198_in_sel_cfg(&self) -> &FUNC198_IN_SEL_CFG { + &self.func198_in_sel_cfg + } + #[doc = "0x474 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func199_in_sel_cfg(&self) -> &FUNC199_IN_SEL_CFG { + &self.func199_in_sel_cfg + } + #[doc = "0x478 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func200_in_sel_cfg(&self) -> &FUNC200_IN_SEL_CFG { + &self.func200_in_sel_cfg + } + #[doc = "0x47c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func201_in_sel_cfg(&self) -> &FUNC201_IN_SEL_CFG { + &self.func201_in_sel_cfg + } + #[doc = "0x480 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func202_in_sel_cfg(&self) -> &FUNC202_IN_SEL_CFG { + &self.func202_in_sel_cfg + } + #[doc = "0x484 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func203_in_sel_cfg(&self) -> &FUNC203_IN_SEL_CFG { + &self.func203_in_sel_cfg + } + #[doc = "0x4b0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func214_in_sel_cfg(&self) -> &FUNC214_IN_SEL_CFG { + &self.func214_in_sel_cfg + } + #[doc = "0x4b4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func215_in_sel_cfg(&self) -> &FUNC215_IN_SEL_CFG { + &self.func215_in_sel_cfg + } + #[doc = "0x4b8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func216_in_sel_cfg(&self) -> &FUNC216_IN_SEL_CFG { + &self.func216_in_sel_cfg + } + #[doc = "0x4bc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func217_in_sel_cfg(&self) -> &FUNC217_IN_SEL_CFG { + &self.func217_in_sel_cfg + } + #[doc = "0x4c0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func218_in_sel_cfg(&self) -> &FUNC218_IN_SEL_CFG { + &self.func218_in_sel_cfg + } + #[doc = "0x4c4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func219_in_sel_cfg(&self) -> &FUNC219_IN_SEL_CFG { + &self.func219_in_sel_cfg + } + #[doc = "0x4c8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func220_in_sel_cfg(&self) -> &FUNC220_IN_SEL_CFG { + &self.func220_in_sel_cfg + } + #[doc = "0x4cc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func221_in_sel_cfg(&self) -> &FUNC221_IN_SEL_CFG { + &self.func221_in_sel_cfg + } + #[doc = "0x4d0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func222_in_sel_cfg(&self) -> &FUNC222_IN_SEL_CFG { + &self.func222_in_sel_cfg + } + #[doc = "0x4d4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func223_in_sel_cfg(&self) -> &FUNC223_IN_SEL_CFG { + &self.func223_in_sel_cfg + } + #[doc = "0x4d8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func224_in_sel_cfg(&self) -> &FUNC224_IN_SEL_CFG { + &self.func224_in_sel_cfg + } + #[doc = "0x4dc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func225_in_sel_cfg(&self) -> &FUNC225_IN_SEL_CFG { + &self.func225_in_sel_cfg + } + #[doc = "0x4e0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func226_in_sel_cfg(&self) -> &FUNC226_IN_SEL_CFG { + &self.func226_in_sel_cfg + } + #[doc = "0x4e4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func227_in_sel_cfg(&self) -> &FUNC227_IN_SEL_CFG { + &self.func227_in_sel_cfg + } + #[doc = "0x4e8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func228_in_sel_cfg(&self) -> &FUNC228_IN_SEL_CFG { + &self.func228_in_sel_cfg + } + #[doc = "0x4ec - GPIO input function configuration register"] + #[inline(always)] + pub const fn func229_in_sel_cfg(&self) -> &FUNC229_IN_SEL_CFG { + &self.func229_in_sel_cfg + } + #[doc = "0x4f0 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func230_in_sel_cfg(&self) -> &FUNC230_IN_SEL_CFG { + &self.func230_in_sel_cfg + } + #[doc = "0x4f4 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func231_in_sel_cfg(&self) -> &FUNC231_IN_SEL_CFG { + &self.func231_in_sel_cfg + } + #[doc = "0x4f8 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func232_in_sel_cfg(&self) -> &FUNC232_IN_SEL_CFG { + &self.func232_in_sel_cfg + } + #[doc = "0x4fc - GPIO input function configuration register"] + #[inline(always)] + pub const fn func233_in_sel_cfg(&self) -> &FUNC233_IN_SEL_CFG { + &self.func233_in_sel_cfg + } + #[doc = "0x500 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func234_in_sel_cfg(&self) -> &FUNC234_IN_SEL_CFG { + &self.func234_in_sel_cfg + } + #[doc = "0x504 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func235_in_sel_cfg(&self) -> &FUNC235_IN_SEL_CFG { + &self.func235_in_sel_cfg + } + #[doc = "0x508 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func236_in_sel_cfg(&self) -> &FUNC236_IN_SEL_CFG { + &self.func236_in_sel_cfg + } + #[doc = "0x50c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func237_in_sel_cfg(&self) -> &FUNC237_IN_SEL_CFG { + &self.func237_in_sel_cfg + } + #[doc = "0x510 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func238_in_sel_cfg(&self) -> &FUNC238_IN_SEL_CFG { + &self.func238_in_sel_cfg + } + #[doc = "0x514 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func239_in_sel_cfg(&self) -> &FUNC239_IN_SEL_CFG { + &self.func239_in_sel_cfg + } + #[doc = "0x518 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func240_in_sel_cfg(&self) -> &FUNC240_IN_SEL_CFG { + &self.func240_in_sel_cfg + } + #[doc = "0x51c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func241_in_sel_cfg(&self) -> &FUNC241_IN_SEL_CFG { + &self.func241_in_sel_cfg + } + #[doc = "0x520 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func242_in_sel_cfg(&self) -> &FUNC242_IN_SEL_CFG { + &self.func242_in_sel_cfg + } + #[doc = "0x524 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func243_in_sel_cfg(&self) -> &FUNC243_IN_SEL_CFG { + &self.func243_in_sel_cfg + } + #[doc = "0x528 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func244_in_sel_cfg(&self) -> &FUNC244_IN_SEL_CFG { + &self.func244_in_sel_cfg + } + #[doc = "0x52c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func245_in_sel_cfg(&self) -> &FUNC245_IN_SEL_CFG { + &self.func245_in_sel_cfg + } + #[doc = "0x530 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func246_in_sel_cfg(&self) -> &FUNC246_IN_SEL_CFG { + &self.func246_in_sel_cfg + } + #[doc = "0x534 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func247_in_sel_cfg(&self) -> &FUNC247_IN_SEL_CFG { + &self.func247_in_sel_cfg + } + #[doc = "0x538 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func248_in_sel_cfg(&self) -> &FUNC248_IN_SEL_CFG { + &self.func248_in_sel_cfg + } + #[doc = "0x53c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func249_in_sel_cfg(&self) -> &FUNC249_IN_SEL_CFG { + &self.func249_in_sel_cfg + } + #[doc = "0x540 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func250_in_sel_cfg(&self) -> &FUNC250_IN_SEL_CFG { + &self.func250_in_sel_cfg + } + #[doc = "0x544 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func251_in_sel_cfg(&self) -> &FUNC251_IN_SEL_CFG { + &self.func251_in_sel_cfg + } + #[doc = "0x548 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func252_in_sel_cfg(&self) -> &FUNC252_IN_SEL_CFG { + &self.func252_in_sel_cfg + } + #[doc = "0x54c - GPIO input function configuration register"] + #[inline(always)] + pub const fn func253_in_sel_cfg(&self) -> &FUNC253_IN_SEL_CFG { + &self.func253_in_sel_cfg + } + #[doc = "0x550 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func254_in_sel_cfg(&self) -> &FUNC254_IN_SEL_CFG { + &self.func254_in_sel_cfg + } + #[doc = "0x554 - GPIO input function configuration register"] + #[inline(always)] + pub const fn func255_in_sel_cfg(&self) -> &FUNC255_IN_SEL_CFG { + &self.func255_in_sel_cfg + } + #[doc = "0x558..0x63c - GPIO output function select register"] + #[inline(always)] + pub const fn func_out_sel_cfg(&self, n: usize) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg[n] + } + #[doc = "0x558 - GPIO output function select register"] + #[inline(always)] + pub const fn func0_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(0) + } + #[doc = "0x55c - GPIO output function select register"] + #[inline(always)] + pub const fn func1_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(1) + } + #[doc = "0x560 - GPIO output function select register"] + #[inline(always)] + pub const fn func2_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(2) + } + #[doc = "0x564 - GPIO output function select register"] + #[inline(always)] + pub const fn func3_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(3) + } + #[doc = "0x568 - GPIO output function select register"] + #[inline(always)] + pub const fn func4_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(4) + } + #[doc = "0x56c - GPIO output function select register"] + #[inline(always)] + pub const fn func5_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(5) + } + #[doc = "0x570 - GPIO output function select register"] + #[inline(always)] + pub const fn func6_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(6) + } + #[doc = "0x574 - GPIO output function select register"] + #[inline(always)] + pub const fn func7_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(7) + } + #[doc = "0x578 - GPIO output function select register"] + #[inline(always)] + pub const fn func8_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(8) + } + #[doc = "0x57c - GPIO output function select register"] + #[inline(always)] + pub const fn func9_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(9) + } + #[doc = "0x580 - GPIO output function select register"] + #[inline(always)] + pub const fn func10_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(10) + } + #[doc = "0x584 - GPIO output function select register"] + #[inline(always)] + pub const fn func11_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(11) + } + #[doc = "0x588 - GPIO output function select register"] + #[inline(always)] + pub const fn func12_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(12) + } + #[doc = "0x58c - GPIO output function select register"] + #[inline(always)] + pub const fn func13_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(13) + } + #[doc = "0x590 - GPIO output function select register"] + #[inline(always)] + pub const fn func14_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(14) + } + #[doc = "0x594 - GPIO output function select register"] + #[inline(always)] + pub const fn func15_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(15) + } + #[doc = "0x598 - GPIO output function select register"] + #[inline(always)] + pub const fn func16_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(16) + } + #[doc = "0x59c - GPIO output function select register"] + #[inline(always)] + pub const fn func17_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(17) + } + #[doc = "0x5a0 - GPIO output function select register"] + #[inline(always)] + pub const fn func18_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(18) + } + #[doc = "0x5a4 - GPIO output function select register"] + #[inline(always)] + pub const fn func19_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(19) + } + #[doc = "0x5a8 - GPIO output function select register"] + #[inline(always)] + pub const fn func20_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(20) + } + #[doc = "0x5ac - GPIO output function select register"] + #[inline(always)] + pub const fn func21_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(21) + } + #[doc = "0x5b0 - GPIO output function select register"] + #[inline(always)] + pub const fn func22_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(22) + } + #[doc = "0x5b4 - GPIO output function select register"] + #[inline(always)] + pub const fn func23_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(23) + } + #[doc = "0x5b8 - GPIO output function select register"] + #[inline(always)] + pub const fn func24_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(24) + } + #[doc = "0x5bc - GPIO output function select register"] + #[inline(always)] + pub const fn func25_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(25) + } + #[doc = "0x5c0 - GPIO output function select register"] + #[inline(always)] + pub const fn func26_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(26) + } + #[doc = "0x5c4 - GPIO output function select register"] + #[inline(always)] + pub const fn func27_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(27) + } + #[doc = "0x5c8 - GPIO output function select register"] + #[inline(always)] + pub const fn func28_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(28) + } + #[doc = "0x5cc - GPIO output function select register"] + #[inline(always)] + pub const fn func29_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(29) + } + #[doc = "0x5d0 - GPIO output function select register"] + #[inline(always)] + pub const fn func30_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(30) + } + #[doc = "0x5d4 - GPIO output function select register"] + #[inline(always)] + pub const fn func31_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(31) + } + #[doc = "0x5d8 - GPIO output function select register"] + #[inline(always)] + pub const fn func32_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(32) + } + #[doc = "0x5dc - GPIO output function select register"] + #[inline(always)] + pub const fn func33_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(33) + } + #[doc = "0x5e0 - GPIO output function select register"] + #[inline(always)] + pub const fn func34_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(34) + } + #[doc = "0x5e4 - GPIO output function select register"] + #[inline(always)] + pub const fn func35_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(35) + } + #[doc = "0x5e8 - GPIO output function select register"] + #[inline(always)] + pub const fn func36_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(36) + } + #[doc = "0x5ec - GPIO output function select register"] + #[inline(always)] + pub const fn func37_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(37) + } + #[doc = "0x5f0 - GPIO output function select register"] + #[inline(always)] + pub const fn func38_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(38) + } + #[doc = "0x5f4 - GPIO output function select register"] + #[inline(always)] + pub const fn func39_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(39) + } + #[doc = "0x5f8 - GPIO output function select register"] + #[inline(always)] + pub const fn func40_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(40) + } + #[doc = "0x5fc - GPIO output function select register"] + #[inline(always)] + pub const fn func41_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(41) + } + #[doc = "0x600 - GPIO output function select register"] + #[inline(always)] + pub const fn func42_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(42) + } + #[doc = "0x604 - GPIO output function select register"] + #[inline(always)] + pub const fn func43_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(43) + } + #[doc = "0x608 - GPIO output function select register"] + #[inline(always)] + pub const fn func44_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(44) + } + #[doc = "0x60c - GPIO output function select register"] + #[inline(always)] + pub const fn func45_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(45) + } + #[doc = "0x610 - GPIO output function select register"] + #[inline(always)] + pub const fn func46_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(46) + } + #[doc = "0x614 - GPIO output function select register"] + #[inline(always)] + pub const fn func47_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(47) + } + #[doc = "0x618 - GPIO output function select register"] + #[inline(always)] + pub const fn func48_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(48) + } + #[doc = "0x61c - GPIO output function select register"] + #[inline(always)] + pub const fn func49_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(49) + } + #[doc = "0x620 - GPIO output function select register"] + #[inline(always)] + pub const fn func50_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(50) + } + #[doc = "0x624 - GPIO output function select register"] + #[inline(always)] + pub const fn func51_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(51) + } + #[doc = "0x628 - GPIO output function select register"] + #[inline(always)] + pub const fn func52_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(52) + } + #[doc = "0x62c - GPIO output function select register"] + #[inline(always)] + pub const fn func53_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(53) + } + #[doc = "0x630 - GPIO output function select register"] + #[inline(always)] + pub const fn func54_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(54) + } + #[doc = "0x634 - GPIO output function select register"] + #[inline(always)] + pub const fn func55_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(55) + } + #[doc = "0x638 - GPIO output function select register"] + #[inline(always)] + pub const fn func56_out_sel_cfg(&self) -> &FUNC_OUT_SEL_CFG { + &self.func_out_sel_cfg(56) + } + #[doc = "0x63c - GPIO interrupt 2 status register for GPIO0-31"] + #[inline(always)] + pub const fn intr_2(&self) -> &INTR_2 { + &self.intr_2 + } + #[doc = "0x640 - GPIO interrupt 2 status register for GPIO32-56"] + #[inline(always)] + pub const fn intr1_2(&self) -> &INTR1_2 { + &self.intr1_2 + } + #[doc = "0x644 - GPIO interrupt 3 status register for GPIO0-31"] + #[inline(always)] + pub const fn intr_3(&self) -> &INTR_3 { + &self.intr_3 + } + #[doc = "0x648 - GPIO interrupt 3 status register for GPIO32-56"] + #[inline(always)] + pub const fn intr1_3(&self) -> &INTR1_3 { + &self.intr1_3 + } + #[doc = "0x64c - GPIO clock gate register"] + #[inline(always)] + pub const fn clock_gate(&self) -> &CLOCK_GATE { + &self.clock_gate + } + #[doc = "0x700 - analog comparator interrupt raw"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x704 - analog comparator interrupt status"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x708 - analog comparator interrupt enable"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x70c - analog comparator interrupt clear"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x710 - GPIO analog comparator zero detect filter count"] + #[inline(always)] + pub const fn zero_det0_filter_cnt(&self) -> &ZERO_DET0_FILTER_CNT { + &self.zero_det0_filter_cnt + } + #[doc = "0x714 - GPIO analog comparator zero detect filter count"] + #[inline(always)] + pub const fn zero_det1_filter_cnt(&self) -> &ZERO_DET1_FILTER_CNT { + &self.zero_det1_filter_cnt + } + #[doc = "0x718 - High speed sdio pad bist send sequence"] + #[inline(always)] + pub const fn send_seq(&self) -> &SEND_SEQ { + &self.send_seq + } + #[doc = "0x71c - High speed sdio pad bist recive sequence"] + #[inline(always)] + pub const fn recive_seq(&self) -> &RECIVE_SEQ { + &self.recive_seq + } + #[doc = "0x720 - High speed sdio pad bist in pad sel"] + #[inline(always)] + pub const fn bistin_sel(&self) -> &BISTIN_SEL { + &self.bistin_sel + } + #[doc = "0x724 - High speed sdio pad bist control"] + #[inline(always)] + pub const fn bist_ctrl(&self) -> &BIST_CTRL { + &self.bist_ctrl + } + #[doc = "0x7fc - GPIO version register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "BT_SELECT (rw) register accessor: GPIO bit select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_select::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_select::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bt_select`] module"] +pub type BT_SELECT = crate::Reg; +#[doc = "GPIO bit select register"] +pub mod bt_select; +#[doc = "OUT (rw) register accessor: GPIO output register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out`] module"] +pub type OUT = crate::Reg; +#[doc = "GPIO output register for GPIO0-31"] +pub mod out; +#[doc = "OUT_W1TS (w) register accessor: GPIO output set register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_w1ts`] module"] +pub type OUT_W1TS = crate::Reg; +#[doc = "GPIO output set register for GPIO0-31"] +pub mod out_w1ts; +#[doc = "OUT_W1TC (w) register accessor: GPIO output clear register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_w1tc`] module"] +pub type OUT_W1TC = crate::Reg; +#[doc = "GPIO output clear register for GPIO0-31"] +pub mod out_w1tc; +#[doc = "OUT1 (rw) register accessor: GPIO output register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out1`] module"] +pub type OUT1 = crate::Reg; +#[doc = "GPIO output register for GPIO32-56"] +pub mod out1; +#[doc = "OUT1_W1TS (w) register accessor: GPIO output set register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out1_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out1_w1ts`] module"] +pub type OUT1_W1TS = crate::Reg; +#[doc = "GPIO output set register for GPIO32-56"] +pub mod out1_w1ts; +#[doc = "OUT1_W1TC (w) register accessor: GPIO output clear register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out1_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out1_w1tc`] module"] +pub type OUT1_W1TC = crate::Reg; +#[doc = "GPIO output clear register for GPIO32-56"] +pub mod out1_w1tc; +#[doc = "ENABLE (rw) register accessor: GPIO output enable register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] +pub type ENABLE = crate::Reg; +#[doc = "GPIO output enable register for GPIO0-31"] +pub mod enable; +#[doc = "ENABLE_W1TS (w) register accessor: GPIO output enable set register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_w1ts`] module"] +pub type ENABLE_W1TS = crate::Reg; +#[doc = "GPIO output enable set register for GPIO0-31"] +pub mod enable_w1ts; +#[doc = "ENABLE_W1TC (w) register accessor: GPIO output enable clear register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_w1tc`] module"] +pub type ENABLE_W1TC = crate::Reg; +#[doc = "GPIO output enable clear register for GPIO0-31"] +pub mod enable_w1tc; +#[doc = "ENABLE1 (rw) register accessor: GPIO output enable register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable1`] module"] +pub type ENABLE1 = crate::Reg; +#[doc = "GPIO output enable register for GPIO32-56"] +pub mod enable1; +#[doc = "ENABLE1_W1TS (w) register accessor: GPIO output enable set register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable1_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable1_w1ts`] module"] +pub type ENABLE1_W1TS = crate::Reg; +#[doc = "GPIO output enable set register for GPIO32-56"] +pub mod enable1_w1ts; +#[doc = "ENABLE1_W1TC (w) register accessor: GPIO output enable clear register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable1_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable1_w1tc`] module"] +pub type ENABLE1_W1TC = crate::Reg; +#[doc = "GPIO output enable clear register for GPIO32-56"] +pub mod enable1_w1tc; +#[doc = "STRAP (r) register accessor: pad strapping register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`strap::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@strap`] module"] +pub type STRAP = crate::Reg; +#[doc = "pad strapping register"] +pub mod strap; +#[doc = "IN (r) register accessor: GPIO input register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_`] module"] +pub type IN = crate::Reg; +#[doc = "GPIO input register for GPIO0-31"] +pub mod in_; +#[doc = "IN1 (r) register accessor: GPIO input register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in1`] module"] +pub type IN1 = crate::Reg; +#[doc = "GPIO input register for GPIO32-56"] +pub mod in1; +#[doc = "STATUS (rw) register accessor: GPIO interrupt status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +pub type STATUS = crate::Reg; +#[doc = "GPIO interrupt status register for GPIO0-31"] +pub mod status; +#[doc = "STATUS_W1TS (w) register accessor: GPIO interrupt status set register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_w1ts`] module"] +pub type STATUS_W1TS = crate::Reg; +#[doc = "GPIO interrupt status set register for GPIO0-31"] +pub mod status_w1ts; +#[doc = "STATUS_W1TC (w) register accessor: GPIO interrupt status clear register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_w1tc`] module"] +pub type STATUS_W1TC = crate::Reg; +#[doc = "GPIO interrupt status clear register for GPIO0-31"] +pub mod status_w1tc; +#[doc = "STATUS1 (rw) register accessor: GPIO interrupt status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status1`] module"] +pub type STATUS1 = crate::Reg; +#[doc = "GPIO interrupt status register for GPIO32-56"] +pub mod status1; +#[doc = "STATUS1_W1TS (w) register accessor: GPIO interrupt status set register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status1_w1ts`] module"] +pub type STATUS1_W1TS = crate::Reg; +#[doc = "GPIO interrupt status set register for GPIO32-56"] +pub mod status1_w1ts; +#[doc = "STATUS1_W1TC (w) register accessor: GPIO interrupt status clear register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status1_w1tc`] module"] +pub type STATUS1_W1TC = crate::Reg; +#[doc = "GPIO interrupt status clear register for GPIO32-56"] +pub mod status1_w1tc; +#[doc = "INTR_0 (r) register accessor: GPIO interrupt 0 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_0`] module"] +pub type INTR_0 = crate::Reg; +#[doc = "GPIO interrupt 0 status register for GPIO0-31"] +pub mod intr_0; +#[doc = "INTR1_0 (r) register accessor: GPIO interrupt 0 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr1_0`] module"] +pub type INTR1_0 = crate::Reg; +#[doc = "GPIO interrupt 0 status register for GPIO32-56"] +pub mod intr1_0; +#[doc = "INTR_1 (r) register accessor: GPIO interrupt 1 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_1`] module"] +pub type INTR_1 = crate::Reg; +#[doc = "GPIO interrupt 1 status register for GPIO0-31"] +pub mod intr_1; +#[doc = "INTR1_1 (r) register accessor: GPIO interrupt 1 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr1_1`] module"] +pub type INTR1_1 = crate::Reg; +#[doc = "GPIO interrupt 1 status register for GPIO32-56"] +pub mod intr1_1; +#[doc = "STATUS_NEXT (r) register accessor: GPIO interrupt source register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_next`] module"] +pub type STATUS_NEXT = crate::Reg; +#[doc = "GPIO interrupt source register for GPIO0-31"] +pub mod status_next; +#[doc = "STATUS_NEXT1 (r) register accessor: GPIO interrupt source register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_next1`] module"] +pub type STATUS_NEXT1 = crate::Reg; +#[doc = "GPIO interrupt source register for GPIO32-56"] +pub mod status_next1; +#[doc = "PIN (rw) register accessor: GPIO pin configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin`] module"] +pub type PIN = crate::Reg; +#[doc = "GPIO pin configuration register"] +pub mod pin; +#[doc = "FUNC1_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func1_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func1_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func1_in_sel_cfg`] module"] +pub type FUNC1_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func1_in_sel_cfg; +#[doc = "FUNC2_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func2_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func2_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func2_in_sel_cfg`] module"] +pub type FUNC2_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func2_in_sel_cfg; +#[doc = "FUNC3_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func3_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func3_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func3_in_sel_cfg`] module"] +pub type FUNC3_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func3_in_sel_cfg; +#[doc = "FUNC4_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func4_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func4_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func4_in_sel_cfg`] module"] +pub type FUNC4_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func4_in_sel_cfg; +#[doc = "FUNC5_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func5_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func5_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func5_in_sel_cfg`] module"] +pub type FUNC5_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func5_in_sel_cfg; +#[doc = "FUNC6_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func6_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func6_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func6_in_sel_cfg`] module"] +pub type FUNC6_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func6_in_sel_cfg; +#[doc = "FUNC7_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func7_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func7_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func7_in_sel_cfg`] module"] +pub type FUNC7_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func7_in_sel_cfg; +#[doc = "FUNC8_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func8_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func8_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func8_in_sel_cfg`] module"] +pub type FUNC8_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func8_in_sel_cfg; +#[doc = "FUNC9_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func9_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func9_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func9_in_sel_cfg`] module"] +pub type FUNC9_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func9_in_sel_cfg; +#[doc = "FUNC10_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func10_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func10_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func10_in_sel_cfg`] module"] +pub type FUNC10_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func10_in_sel_cfg; +#[doc = "FUNC11_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func11_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func11_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func11_in_sel_cfg`] module"] +pub type FUNC11_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func11_in_sel_cfg; +#[doc = "FUNC12_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func12_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func12_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func12_in_sel_cfg`] module"] +pub type FUNC12_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func12_in_sel_cfg; +#[doc = "FUNC13_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func13_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func13_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func13_in_sel_cfg`] module"] +pub type FUNC13_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func13_in_sel_cfg; +#[doc = "FUNC14_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func14_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func14_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func14_in_sel_cfg`] module"] +pub type FUNC14_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func14_in_sel_cfg; +#[doc = "FUNC15_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func15_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func15_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func15_in_sel_cfg`] module"] +pub type FUNC15_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func15_in_sel_cfg; +#[doc = "FUNC16_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func16_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func16_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func16_in_sel_cfg`] module"] +pub type FUNC16_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func16_in_sel_cfg; +#[doc = "FUNC17_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func17_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func17_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func17_in_sel_cfg`] module"] +pub type FUNC17_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func17_in_sel_cfg; +#[doc = "FUNC18_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func18_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func18_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func18_in_sel_cfg`] module"] +pub type FUNC18_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func18_in_sel_cfg; +#[doc = "FUNC19_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func19_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func19_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func19_in_sel_cfg`] module"] +pub type FUNC19_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func19_in_sel_cfg; +#[doc = "FUNC20_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func20_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func20_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func20_in_sel_cfg`] module"] +pub type FUNC20_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func20_in_sel_cfg; +#[doc = "FUNC21_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func21_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func21_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func21_in_sel_cfg`] module"] +pub type FUNC21_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func21_in_sel_cfg; +#[doc = "FUNC22_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func22_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func22_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func22_in_sel_cfg`] module"] +pub type FUNC22_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func22_in_sel_cfg; +#[doc = "FUNC23_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func23_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func23_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func23_in_sel_cfg`] module"] +pub type FUNC23_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func23_in_sel_cfg; +#[doc = "FUNC24_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func24_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func24_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func24_in_sel_cfg`] module"] +pub type FUNC24_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func24_in_sel_cfg; +#[doc = "FUNC25_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func25_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func25_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func25_in_sel_cfg`] module"] +pub type FUNC25_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func25_in_sel_cfg; +#[doc = "FUNC26_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func26_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func26_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func26_in_sel_cfg`] module"] +pub type FUNC26_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func26_in_sel_cfg; +#[doc = "FUNC27_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func27_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func27_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func27_in_sel_cfg`] module"] +pub type FUNC27_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func27_in_sel_cfg; +#[doc = "FUNC28_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func28_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func28_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func28_in_sel_cfg`] module"] +pub type FUNC28_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func28_in_sel_cfg; +#[doc = "FUNC29_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func29_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func29_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func29_in_sel_cfg`] module"] +pub type FUNC29_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func29_in_sel_cfg; +#[doc = "FUNC30_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func30_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func30_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func30_in_sel_cfg`] module"] +pub type FUNC30_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func30_in_sel_cfg; +#[doc = "FUNC31_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func31_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func31_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func31_in_sel_cfg`] module"] +pub type FUNC31_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func31_in_sel_cfg; +#[doc = "FUNC32_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func32_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func32_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func32_in_sel_cfg`] module"] +pub type FUNC32_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func32_in_sel_cfg; +#[doc = "FUNC33_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func33_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func33_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func33_in_sel_cfg`] module"] +pub type FUNC33_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func33_in_sel_cfg; +#[doc = "FUNC34_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func34_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func34_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func34_in_sel_cfg`] module"] +pub type FUNC34_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func34_in_sel_cfg; +#[doc = "FUNC35_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func35_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func35_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func35_in_sel_cfg`] module"] +pub type FUNC35_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func35_in_sel_cfg; +#[doc = "FUNC36_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func36_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func36_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func36_in_sel_cfg`] module"] +pub type FUNC36_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func36_in_sel_cfg; +#[doc = "FUNC37_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func37_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func37_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func37_in_sel_cfg`] module"] +pub type FUNC37_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func37_in_sel_cfg; +#[doc = "FUNC38_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func38_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func38_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func38_in_sel_cfg`] module"] +pub type FUNC38_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func38_in_sel_cfg; +#[doc = "FUNC39_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func39_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func39_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func39_in_sel_cfg`] module"] +pub type FUNC39_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func39_in_sel_cfg; +#[doc = "FUNC40_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func40_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func40_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func40_in_sel_cfg`] module"] +pub type FUNC40_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func40_in_sel_cfg; +#[doc = "FUNC41_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func41_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func41_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func41_in_sel_cfg`] module"] +pub type FUNC41_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func41_in_sel_cfg; +#[doc = "FUNC42_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func42_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func42_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func42_in_sel_cfg`] module"] +pub type FUNC42_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func42_in_sel_cfg; +#[doc = "FUNC43_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func43_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func43_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func43_in_sel_cfg`] module"] +pub type FUNC43_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func43_in_sel_cfg; +#[doc = "FUNC44_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func44_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func44_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func44_in_sel_cfg`] module"] +pub type FUNC44_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func44_in_sel_cfg; +#[doc = "FUNC45_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func45_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func45_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func45_in_sel_cfg`] module"] +pub type FUNC45_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func45_in_sel_cfg; +#[doc = "FUNC47_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func47_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func47_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func47_in_sel_cfg`] module"] +pub type FUNC47_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func47_in_sel_cfg; +#[doc = "FUNC48_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func48_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func48_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func48_in_sel_cfg`] module"] +pub type FUNC48_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func48_in_sel_cfg; +#[doc = "FUNC49_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func49_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func49_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func49_in_sel_cfg`] module"] +pub type FUNC49_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func49_in_sel_cfg; +#[doc = "FUNC50_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func50_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func50_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func50_in_sel_cfg`] module"] +pub type FUNC50_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func50_in_sel_cfg; +#[doc = "FUNC51_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func51_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func51_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func51_in_sel_cfg`] module"] +pub type FUNC51_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func51_in_sel_cfg; +#[doc = "FUNC52_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func52_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func52_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func52_in_sel_cfg`] module"] +pub type FUNC52_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func52_in_sel_cfg; +#[doc = "FUNC53_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func53_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func53_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func53_in_sel_cfg`] module"] +pub type FUNC53_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func53_in_sel_cfg; +#[doc = "FUNC54_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func54_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func54_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func54_in_sel_cfg`] module"] +pub type FUNC54_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func54_in_sel_cfg; +#[doc = "FUNC55_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func55_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func55_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func55_in_sel_cfg`] module"] +pub type FUNC55_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func55_in_sel_cfg; +#[doc = "FUNC56_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func56_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func56_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func56_in_sel_cfg`] module"] +pub type FUNC56_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func56_in_sel_cfg; +#[doc = "FUNC57_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func57_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func57_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func57_in_sel_cfg`] module"] +pub type FUNC57_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func57_in_sel_cfg; +#[doc = "FUNC58_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func58_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func58_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func58_in_sel_cfg`] module"] +pub type FUNC58_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func58_in_sel_cfg; +#[doc = "FUNC59_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func59_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func59_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func59_in_sel_cfg`] module"] +pub type FUNC59_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func59_in_sel_cfg; +#[doc = "FUNC60_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func60_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func60_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func60_in_sel_cfg`] module"] +pub type FUNC60_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func60_in_sel_cfg; +#[doc = "FUNC61_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func61_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func61_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func61_in_sel_cfg`] module"] +pub type FUNC61_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func61_in_sel_cfg; +#[doc = "FUNC62_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func62_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func62_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func62_in_sel_cfg`] module"] +pub type FUNC62_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func62_in_sel_cfg; +#[doc = "FUNC63_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func63_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func63_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func63_in_sel_cfg`] module"] +pub type FUNC63_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func63_in_sel_cfg; +#[doc = "FUNC64_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func64_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func64_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func64_in_sel_cfg`] module"] +pub type FUNC64_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func64_in_sel_cfg; +#[doc = "FUNC65_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func65_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func65_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func65_in_sel_cfg`] module"] +pub type FUNC65_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func65_in_sel_cfg; +#[doc = "FUNC66_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func66_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func66_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func66_in_sel_cfg`] module"] +pub type FUNC66_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func66_in_sel_cfg; +#[doc = "FUNC68_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func68_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func68_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func68_in_sel_cfg`] module"] +pub type FUNC68_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func68_in_sel_cfg; +#[doc = "FUNC69_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func69_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func69_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func69_in_sel_cfg`] module"] +pub type FUNC69_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func69_in_sel_cfg; +#[doc = "FUNC70_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func70_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func70_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func70_in_sel_cfg`] module"] +pub type FUNC70_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func70_in_sel_cfg; +#[doc = "FUNC71_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func71_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func71_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func71_in_sel_cfg`] module"] +pub type FUNC71_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func71_in_sel_cfg; +#[doc = "FUNC74_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func74_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func74_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func74_in_sel_cfg`] module"] +pub type FUNC74_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func74_in_sel_cfg; +#[doc = "FUNC75_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func75_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func75_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func75_in_sel_cfg`] module"] +pub type FUNC75_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func75_in_sel_cfg; +#[doc = "FUNC76_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func76_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func76_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func76_in_sel_cfg`] module"] +pub type FUNC76_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func76_in_sel_cfg; +#[doc = "FUNC77_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func77_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func77_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func77_in_sel_cfg`] module"] +pub type FUNC77_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func77_in_sel_cfg; +#[doc = "FUNC78_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func78_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func78_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func78_in_sel_cfg`] module"] +pub type FUNC78_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func78_in_sel_cfg; +#[doc = "FUNC80_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func80_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func80_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func80_in_sel_cfg`] module"] +pub type FUNC80_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func80_in_sel_cfg; +#[doc = "FUNC83_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func83_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func83_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func83_in_sel_cfg`] module"] +pub type FUNC83_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func83_in_sel_cfg; +#[doc = "FUNC86_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func86_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func86_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func86_in_sel_cfg`] module"] +pub type FUNC86_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func86_in_sel_cfg; +#[doc = "FUNC89_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func89_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func89_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func89_in_sel_cfg`] module"] +pub type FUNC89_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func89_in_sel_cfg; +#[doc = "FUNC90_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func90_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func90_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func90_in_sel_cfg`] module"] +pub type FUNC90_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func90_in_sel_cfg; +#[doc = "FUNC91_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func91_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func91_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func91_in_sel_cfg`] module"] +pub type FUNC91_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func91_in_sel_cfg; +#[doc = "FUNC92_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func92_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func92_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func92_in_sel_cfg`] module"] +pub type FUNC92_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func92_in_sel_cfg; +#[doc = "FUNC93_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func93_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func93_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func93_in_sel_cfg`] module"] +pub type FUNC93_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func93_in_sel_cfg; +#[doc = "FUNC94_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func94_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func94_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func94_in_sel_cfg`] module"] +pub type FUNC94_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func94_in_sel_cfg; +#[doc = "FUNC95_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func95_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func95_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func95_in_sel_cfg`] module"] +pub type FUNC95_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func95_in_sel_cfg; +#[doc = "FUNC96_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func96_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func96_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func96_in_sel_cfg`] module"] +pub type FUNC96_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func96_in_sel_cfg; +#[doc = "FUNC97_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func97_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func97_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func97_in_sel_cfg`] module"] +pub type FUNC97_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func97_in_sel_cfg; +#[doc = "FUNC98_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func98_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func98_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func98_in_sel_cfg`] module"] +pub type FUNC98_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func98_in_sel_cfg; +#[doc = "FUNC99_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func99_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func99_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func99_in_sel_cfg`] module"] +pub type FUNC99_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func99_in_sel_cfg; +#[doc = "FUNC100_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func100_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func100_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func100_in_sel_cfg`] module"] +pub type FUNC100_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func100_in_sel_cfg; +#[doc = "FUNC101_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func101_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func101_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func101_in_sel_cfg`] module"] +pub type FUNC101_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func101_in_sel_cfg; +#[doc = "FUNC102_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func102_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func102_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func102_in_sel_cfg`] module"] +pub type FUNC102_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func102_in_sel_cfg; +#[doc = "FUNC103_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func103_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func103_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func103_in_sel_cfg`] module"] +pub type FUNC103_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func103_in_sel_cfg; +#[doc = "FUNC104_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func104_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func104_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func104_in_sel_cfg`] module"] +pub type FUNC104_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func104_in_sel_cfg; +#[doc = "FUNC105_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func105_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func105_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func105_in_sel_cfg`] module"] +pub type FUNC105_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func105_in_sel_cfg; +#[doc = "FUNC106_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func106_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func106_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func106_in_sel_cfg`] module"] +pub type FUNC106_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func106_in_sel_cfg; +#[doc = "FUNC107_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func107_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func107_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func107_in_sel_cfg`] module"] +pub type FUNC107_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func107_in_sel_cfg; +#[doc = "FUNC108_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func108_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func108_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func108_in_sel_cfg`] module"] +pub type FUNC108_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func108_in_sel_cfg; +#[doc = "FUNC109_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func109_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func109_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func109_in_sel_cfg`] module"] +pub type FUNC109_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func109_in_sel_cfg; +#[doc = "FUNC110_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func110_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func110_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func110_in_sel_cfg`] module"] +pub type FUNC110_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func110_in_sel_cfg; +#[doc = "FUNC111_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func111_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func111_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func111_in_sel_cfg`] module"] +pub type FUNC111_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func111_in_sel_cfg; +#[doc = "FUNC112_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func112_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func112_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func112_in_sel_cfg`] module"] +pub type FUNC112_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func112_in_sel_cfg; +#[doc = "FUNC113_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func113_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func113_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func113_in_sel_cfg`] module"] +pub type FUNC113_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func113_in_sel_cfg; +#[doc = "FUNC114_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func114_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func114_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func114_in_sel_cfg`] module"] +pub type FUNC114_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func114_in_sel_cfg; +#[doc = "FUNC117_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func117_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func117_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func117_in_sel_cfg`] module"] +pub type FUNC117_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func117_in_sel_cfg; +#[doc = "FUNC118_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func118_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func118_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func118_in_sel_cfg`] module"] +pub type FUNC118_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func118_in_sel_cfg; +#[doc = "FUNC126_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func126_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func126_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func126_in_sel_cfg`] module"] +pub type FUNC126_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func126_in_sel_cfg; +#[doc = "FUNC127_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func127_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func127_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func127_in_sel_cfg`] module"] +pub type FUNC127_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func127_in_sel_cfg; +#[doc = "FUNC128_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func128_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func128_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func128_in_sel_cfg`] module"] +pub type FUNC128_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func128_in_sel_cfg; +#[doc = "FUNC129_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func129_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func129_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func129_in_sel_cfg`] module"] +pub type FUNC129_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func129_in_sel_cfg; +#[doc = "FUNC130_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func130_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func130_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func130_in_sel_cfg`] module"] +pub type FUNC130_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func130_in_sel_cfg; +#[doc = "FUNC131_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func131_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func131_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func131_in_sel_cfg`] module"] +pub type FUNC131_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func131_in_sel_cfg; +#[doc = "FUNC132_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func132_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func132_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func132_in_sel_cfg`] module"] +pub type FUNC132_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func132_in_sel_cfg; +#[doc = "FUNC133_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func133_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func133_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func133_in_sel_cfg`] module"] +pub type FUNC133_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func133_in_sel_cfg; +#[doc = "FUNC134_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func134_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func134_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func134_in_sel_cfg`] module"] +pub type FUNC134_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func134_in_sel_cfg; +#[doc = "FUNC135_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func135_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func135_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func135_in_sel_cfg`] module"] +pub type FUNC135_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func135_in_sel_cfg; +#[doc = "FUNC136_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func136_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func136_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func136_in_sel_cfg`] module"] +pub type FUNC136_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func136_in_sel_cfg; +#[doc = "FUNC137_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func137_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func137_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func137_in_sel_cfg`] module"] +pub type FUNC137_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func137_in_sel_cfg; +#[doc = "FUNC138_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func138_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func138_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func138_in_sel_cfg`] module"] +pub type FUNC138_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func138_in_sel_cfg; +#[doc = "FUNC139_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func139_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func139_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func139_in_sel_cfg`] module"] +pub type FUNC139_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func139_in_sel_cfg; +#[doc = "FUNC140_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func140_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func140_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func140_in_sel_cfg`] module"] +pub type FUNC140_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func140_in_sel_cfg; +#[doc = "FUNC141_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func141_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func141_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func141_in_sel_cfg`] module"] +pub type FUNC141_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func141_in_sel_cfg; +#[doc = "FUNC142_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func142_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func142_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func142_in_sel_cfg`] module"] +pub type FUNC142_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func142_in_sel_cfg; +#[doc = "FUNC143_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func143_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func143_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func143_in_sel_cfg`] module"] +pub type FUNC143_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func143_in_sel_cfg; +#[doc = "FUNC144_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func144_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func144_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func144_in_sel_cfg`] module"] +pub type FUNC144_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func144_in_sel_cfg; +#[doc = "FUNC145_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func145_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func145_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func145_in_sel_cfg`] module"] +pub type FUNC145_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func145_in_sel_cfg; +#[doc = "FUNC146_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func146_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func146_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func146_in_sel_cfg`] module"] +pub type FUNC146_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func146_in_sel_cfg; +#[doc = "FUNC147_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func147_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func147_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func147_in_sel_cfg`] module"] +pub type FUNC147_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func147_in_sel_cfg; +#[doc = "FUNC148_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func148_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func148_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func148_in_sel_cfg`] module"] +pub type FUNC148_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func148_in_sel_cfg; +#[doc = "FUNC149_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func149_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func149_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func149_in_sel_cfg`] module"] +pub type FUNC149_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func149_in_sel_cfg; +#[doc = "FUNC150_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func150_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func150_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func150_in_sel_cfg`] module"] +pub type FUNC150_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func150_in_sel_cfg; +#[doc = "FUNC151_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func151_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func151_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func151_in_sel_cfg`] module"] +pub type FUNC151_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func151_in_sel_cfg; +#[doc = "FUNC152_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func152_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func152_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func152_in_sel_cfg`] module"] +pub type FUNC152_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func152_in_sel_cfg; +#[doc = "FUNC153_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func153_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func153_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func153_in_sel_cfg`] module"] +pub type FUNC153_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func153_in_sel_cfg; +#[doc = "FUNC154_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func154_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func154_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func154_in_sel_cfg`] module"] +pub type FUNC154_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func154_in_sel_cfg; +#[doc = "FUNC155_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func155_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func155_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func155_in_sel_cfg`] module"] +pub type FUNC155_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func155_in_sel_cfg; +#[doc = "FUNC156_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func156_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func156_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func156_in_sel_cfg`] module"] +pub type FUNC156_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func156_in_sel_cfg; +#[doc = "FUNC158_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func158_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func158_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func158_in_sel_cfg`] module"] +pub type FUNC158_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func158_in_sel_cfg; +#[doc = "FUNC159_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func159_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func159_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func159_in_sel_cfg`] module"] +pub type FUNC159_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func159_in_sel_cfg; +#[doc = "FUNC160_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func160_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func160_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func160_in_sel_cfg`] module"] +pub type FUNC160_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func160_in_sel_cfg; +#[doc = "FUNC161_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func161_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func161_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func161_in_sel_cfg`] module"] +pub type FUNC161_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func161_in_sel_cfg; +#[doc = "FUNC162_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func162_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func162_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func162_in_sel_cfg`] module"] +pub type FUNC162_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func162_in_sel_cfg; +#[doc = "FUNC163_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func163_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func163_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func163_in_sel_cfg`] module"] +pub type FUNC163_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func163_in_sel_cfg; +#[doc = "FUNC164_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func164_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func164_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func164_in_sel_cfg`] module"] +pub type FUNC164_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func164_in_sel_cfg; +#[doc = "FUNC165_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func165_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func165_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func165_in_sel_cfg`] module"] +pub type FUNC165_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func165_in_sel_cfg; +#[doc = "FUNC166_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func166_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func166_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func166_in_sel_cfg`] module"] +pub type FUNC166_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func166_in_sel_cfg; +#[doc = "FUNC167_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func167_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func167_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func167_in_sel_cfg`] module"] +pub type FUNC167_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func167_in_sel_cfg; +#[doc = "FUNC168_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func168_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func168_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func168_in_sel_cfg`] module"] +pub type FUNC168_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func168_in_sel_cfg; +#[doc = "FUNC169_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func169_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func169_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func169_in_sel_cfg`] module"] +pub type FUNC169_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func169_in_sel_cfg; +#[doc = "FUNC170_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func170_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func170_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func170_in_sel_cfg`] module"] +pub type FUNC170_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func170_in_sel_cfg; +#[doc = "FUNC171_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func171_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func171_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func171_in_sel_cfg`] module"] +pub type FUNC171_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func171_in_sel_cfg; +#[doc = "FUNC172_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func172_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func172_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func172_in_sel_cfg`] module"] +pub type FUNC172_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func172_in_sel_cfg; +#[doc = "FUNC173_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func173_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func173_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func173_in_sel_cfg`] module"] +pub type FUNC173_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func173_in_sel_cfg; +#[doc = "FUNC174_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func174_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func174_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func174_in_sel_cfg`] module"] +pub type FUNC174_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func174_in_sel_cfg; +#[doc = "FUNC175_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func175_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func175_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func175_in_sel_cfg`] module"] +pub type FUNC175_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func175_in_sel_cfg; +#[doc = "FUNC176_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func176_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func176_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func176_in_sel_cfg`] module"] +pub type FUNC176_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func176_in_sel_cfg; +#[doc = "FUNC177_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func177_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func177_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func177_in_sel_cfg`] module"] +pub type FUNC177_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func177_in_sel_cfg; +#[doc = "FUNC178_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func178_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func178_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func178_in_sel_cfg`] module"] +pub type FUNC178_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func178_in_sel_cfg; +#[doc = "FUNC179_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func179_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func179_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func179_in_sel_cfg`] module"] +pub type FUNC179_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func179_in_sel_cfg; +#[doc = "FUNC180_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func180_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func180_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func180_in_sel_cfg`] module"] +pub type FUNC180_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func180_in_sel_cfg; +#[doc = "FUNC181_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func181_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func181_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func181_in_sel_cfg`] module"] +pub type FUNC181_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func181_in_sel_cfg; +#[doc = "FUNC182_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func182_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func182_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func182_in_sel_cfg`] module"] +pub type FUNC182_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func182_in_sel_cfg; +#[doc = "FUNC183_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func183_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func183_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func183_in_sel_cfg`] module"] +pub type FUNC183_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func183_in_sel_cfg; +#[doc = "FUNC184_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func184_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func184_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func184_in_sel_cfg`] module"] +pub type FUNC184_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func184_in_sel_cfg; +#[doc = "FUNC185_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func185_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func185_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func185_in_sel_cfg`] module"] +pub type FUNC185_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func185_in_sel_cfg; +#[doc = "FUNC186_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func186_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func186_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func186_in_sel_cfg`] module"] +pub type FUNC186_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func186_in_sel_cfg; +#[doc = "FUNC187_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func187_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func187_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func187_in_sel_cfg`] module"] +pub type FUNC187_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func187_in_sel_cfg; +#[doc = "FUNC188_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func188_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func188_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func188_in_sel_cfg`] module"] +pub type FUNC188_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func188_in_sel_cfg; +#[doc = "FUNC189_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func189_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func189_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func189_in_sel_cfg`] module"] +pub type FUNC189_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func189_in_sel_cfg; +#[doc = "FUNC190_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func190_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func190_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func190_in_sel_cfg`] module"] +pub type FUNC190_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func190_in_sel_cfg; +#[doc = "FUNC191_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func191_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func191_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func191_in_sel_cfg`] module"] +pub type FUNC191_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func191_in_sel_cfg; +#[doc = "FUNC192_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func192_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func192_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func192_in_sel_cfg`] module"] +pub type FUNC192_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func192_in_sel_cfg; +#[doc = "FUNC193_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func193_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func193_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func193_in_sel_cfg`] module"] +pub type FUNC193_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func193_in_sel_cfg; +#[doc = "FUNC194_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func194_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func194_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func194_in_sel_cfg`] module"] +pub type FUNC194_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func194_in_sel_cfg; +#[doc = "FUNC195_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func195_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func195_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func195_in_sel_cfg`] module"] +pub type FUNC195_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func195_in_sel_cfg; +#[doc = "FUNC196_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func196_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func196_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func196_in_sel_cfg`] module"] +pub type FUNC196_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func196_in_sel_cfg; +#[doc = "FUNC197_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func197_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func197_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func197_in_sel_cfg`] module"] +pub type FUNC197_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func197_in_sel_cfg; +#[doc = "FUNC198_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func198_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func198_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func198_in_sel_cfg`] module"] +pub type FUNC198_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func198_in_sel_cfg; +#[doc = "FUNC199_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func199_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func199_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func199_in_sel_cfg`] module"] +pub type FUNC199_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func199_in_sel_cfg; +#[doc = "FUNC200_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func200_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func200_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func200_in_sel_cfg`] module"] +pub type FUNC200_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func200_in_sel_cfg; +#[doc = "FUNC201_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func201_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func201_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func201_in_sel_cfg`] module"] +pub type FUNC201_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func201_in_sel_cfg; +#[doc = "FUNC202_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func202_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func202_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func202_in_sel_cfg`] module"] +pub type FUNC202_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func202_in_sel_cfg; +#[doc = "FUNC203_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func203_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func203_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func203_in_sel_cfg`] module"] +pub type FUNC203_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func203_in_sel_cfg; +#[doc = "FUNC214_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func214_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func214_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func214_in_sel_cfg`] module"] +pub type FUNC214_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func214_in_sel_cfg; +#[doc = "FUNC215_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func215_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func215_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func215_in_sel_cfg`] module"] +pub type FUNC215_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func215_in_sel_cfg; +#[doc = "FUNC216_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func216_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func216_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func216_in_sel_cfg`] module"] +pub type FUNC216_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func216_in_sel_cfg; +#[doc = "FUNC217_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func217_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func217_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func217_in_sel_cfg`] module"] +pub type FUNC217_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func217_in_sel_cfg; +#[doc = "FUNC218_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func218_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func218_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func218_in_sel_cfg`] module"] +pub type FUNC218_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func218_in_sel_cfg; +#[doc = "FUNC219_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func219_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func219_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func219_in_sel_cfg`] module"] +pub type FUNC219_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func219_in_sel_cfg; +#[doc = "FUNC220_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func220_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func220_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func220_in_sel_cfg`] module"] +pub type FUNC220_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func220_in_sel_cfg; +#[doc = "FUNC221_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func221_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func221_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func221_in_sel_cfg`] module"] +pub type FUNC221_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func221_in_sel_cfg; +#[doc = "FUNC222_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func222_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func222_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func222_in_sel_cfg`] module"] +pub type FUNC222_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func222_in_sel_cfg; +#[doc = "FUNC223_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func223_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func223_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func223_in_sel_cfg`] module"] +pub type FUNC223_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func223_in_sel_cfg; +#[doc = "FUNC224_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func224_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func224_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func224_in_sel_cfg`] module"] +pub type FUNC224_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func224_in_sel_cfg; +#[doc = "FUNC225_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func225_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func225_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func225_in_sel_cfg`] module"] +pub type FUNC225_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func225_in_sel_cfg; +#[doc = "FUNC226_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func226_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func226_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func226_in_sel_cfg`] module"] +pub type FUNC226_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func226_in_sel_cfg; +#[doc = "FUNC227_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func227_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func227_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func227_in_sel_cfg`] module"] +pub type FUNC227_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func227_in_sel_cfg; +#[doc = "FUNC228_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func228_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func228_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func228_in_sel_cfg`] module"] +pub type FUNC228_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func228_in_sel_cfg; +#[doc = "FUNC229_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func229_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func229_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func229_in_sel_cfg`] module"] +pub type FUNC229_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func229_in_sel_cfg; +#[doc = "FUNC230_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func230_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func230_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func230_in_sel_cfg`] module"] +pub type FUNC230_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func230_in_sel_cfg; +#[doc = "FUNC231_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func231_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func231_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func231_in_sel_cfg`] module"] +pub type FUNC231_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func231_in_sel_cfg; +#[doc = "FUNC232_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func232_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func232_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func232_in_sel_cfg`] module"] +pub type FUNC232_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func232_in_sel_cfg; +#[doc = "FUNC233_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func233_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func233_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func233_in_sel_cfg`] module"] +pub type FUNC233_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func233_in_sel_cfg; +#[doc = "FUNC234_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func234_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func234_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func234_in_sel_cfg`] module"] +pub type FUNC234_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func234_in_sel_cfg; +#[doc = "FUNC235_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func235_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func235_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func235_in_sel_cfg`] module"] +pub type FUNC235_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func235_in_sel_cfg; +#[doc = "FUNC236_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func236_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func236_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func236_in_sel_cfg`] module"] +pub type FUNC236_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func236_in_sel_cfg; +#[doc = "FUNC237_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func237_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func237_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func237_in_sel_cfg`] module"] +pub type FUNC237_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func237_in_sel_cfg; +#[doc = "FUNC238_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func238_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func238_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func238_in_sel_cfg`] module"] +pub type FUNC238_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func238_in_sel_cfg; +#[doc = "FUNC239_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func239_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func239_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func239_in_sel_cfg`] module"] +pub type FUNC239_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func239_in_sel_cfg; +#[doc = "FUNC240_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func240_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func240_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func240_in_sel_cfg`] module"] +pub type FUNC240_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func240_in_sel_cfg; +#[doc = "FUNC241_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func241_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func241_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func241_in_sel_cfg`] module"] +pub type FUNC241_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func241_in_sel_cfg; +#[doc = "FUNC242_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func242_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func242_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func242_in_sel_cfg`] module"] +pub type FUNC242_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func242_in_sel_cfg; +#[doc = "FUNC243_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func243_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func243_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func243_in_sel_cfg`] module"] +pub type FUNC243_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func243_in_sel_cfg; +#[doc = "FUNC244_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func244_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func244_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func244_in_sel_cfg`] module"] +pub type FUNC244_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func244_in_sel_cfg; +#[doc = "FUNC245_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func245_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func245_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func245_in_sel_cfg`] module"] +pub type FUNC245_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func245_in_sel_cfg; +#[doc = "FUNC246_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func246_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func246_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func246_in_sel_cfg`] module"] +pub type FUNC246_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func246_in_sel_cfg; +#[doc = "FUNC247_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func247_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func247_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func247_in_sel_cfg`] module"] +pub type FUNC247_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func247_in_sel_cfg; +#[doc = "FUNC248_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func248_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func248_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func248_in_sel_cfg`] module"] +pub type FUNC248_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func248_in_sel_cfg; +#[doc = "FUNC249_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func249_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func249_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func249_in_sel_cfg`] module"] +pub type FUNC249_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func249_in_sel_cfg; +#[doc = "FUNC250_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func250_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func250_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func250_in_sel_cfg`] module"] +pub type FUNC250_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func250_in_sel_cfg; +#[doc = "FUNC251_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func251_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func251_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func251_in_sel_cfg`] module"] +pub type FUNC251_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func251_in_sel_cfg; +#[doc = "FUNC252_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func252_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func252_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func252_in_sel_cfg`] module"] +pub type FUNC252_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func252_in_sel_cfg; +#[doc = "FUNC253_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func253_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func253_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func253_in_sel_cfg`] module"] +pub type FUNC253_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func253_in_sel_cfg; +#[doc = "FUNC254_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func254_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func254_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func254_in_sel_cfg`] module"] +pub type FUNC254_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func254_in_sel_cfg; +#[doc = "FUNC255_IN_SEL_CFG (rw) register accessor: GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func255_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func255_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func255_in_sel_cfg`] module"] +pub type FUNC255_IN_SEL_CFG = crate::Reg; +#[doc = "GPIO input function configuration register"] +pub mod func255_in_sel_cfg; +#[doc = "FUNC_OUT_SEL_CFG (rw) register accessor: GPIO output function select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_out_sel_cfg`] module"] +pub type FUNC_OUT_SEL_CFG = crate::Reg; +#[doc = "GPIO output function select register"] +pub mod func_out_sel_cfg; +#[doc = "INTR_2 (r) register accessor: GPIO interrupt 2 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_2`] module"] +pub type INTR_2 = crate::Reg; +#[doc = "GPIO interrupt 2 status register for GPIO0-31"] +pub mod intr_2; +#[doc = "INTR1_2 (r) register accessor: GPIO interrupt 2 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr1_2`] module"] +pub type INTR1_2 = crate::Reg; +#[doc = "GPIO interrupt 2 status register for GPIO32-56"] +pub mod intr1_2; +#[doc = "INTR_3 (r) register accessor: GPIO interrupt 3 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_3`] module"] +pub type INTR_3 = crate::Reg; +#[doc = "GPIO interrupt 3 status register for GPIO0-31"] +pub mod intr_3; +#[doc = "INTR1_3 (r) register accessor: GPIO interrupt 3 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr1_3`] module"] +pub type INTR1_3 = crate::Reg; +#[doc = "GPIO interrupt 3 status register for GPIO32-56"] +pub mod intr1_3; +#[doc = "CLOCK_GATE (rw) register accessor: GPIO clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"] +pub type CLOCK_GATE = crate::Reg; +#[doc = "GPIO clock gate register"] +pub mod clock_gate; +#[doc = "INT_RAW (rw) register accessor: analog comparator interrupt raw\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "analog comparator interrupt raw"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: analog comparator interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "analog comparator interrupt status"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: analog comparator interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "analog comparator interrupt enable"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: analog comparator interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "analog comparator interrupt clear"] +pub mod int_clr; +#[doc = "ZERO_DET0_FILTER_CNT (rw) register accessor: GPIO analog comparator zero detect filter count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`zero_det0_filter_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`zero_det0_filter_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@zero_det0_filter_cnt`] module"] +pub type ZERO_DET0_FILTER_CNT = crate::Reg; +#[doc = "GPIO analog comparator zero detect filter count"] +pub mod zero_det0_filter_cnt; +#[doc = "ZERO_DET1_FILTER_CNT (rw) register accessor: GPIO analog comparator zero detect filter count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`zero_det1_filter_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`zero_det1_filter_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@zero_det1_filter_cnt`] module"] +pub type ZERO_DET1_FILTER_CNT = crate::Reg; +#[doc = "GPIO analog comparator zero detect filter count"] +pub mod zero_det1_filter_cnt; +#[doc = "SEND_SEQ (rw) register accessor: High speed sdio pad bist send sequence\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`send_seq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`send_seq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@send_seq`] module"] +pub type SEND_SEQ = crate::Reg; +#[doc = "High speed sdio pad bist send sequence"] +pub mod send_seq; +#[doc = "RECIVE_SEQ (r) register accessor: High speed sdio pad bist recive sequence\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`recive_seq::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@recive_seq`] module"] +pub type RECIVE_SEQ = crate::Reg; +#[doc = "High speed sdio pad bist recive sequence"] +pub mod recive_seq; +#[doc = "BISTIN_SEL (rw) register accessor: High speed sdio pad bist in pad sel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bistin_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bistin_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bistin_sel`] module"] +pub type BISTIN_SEL = crate::Reg; +#[doc = "High speed sdio pad bist in pad sel"] +pub mod bistin_sel; +#[doc = "BIST_CTRL (rw) register accessor: High speed sdio pad bist control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bist_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bist_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bist_ctrl`] module"] +pub type BIST_CTRL = crate::Reg; +#[doc = "High speed sdio pad bist control"] +pub mod bist_ctrl; +#[doc = "DATE (rw) register accessor: GPIO version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "GPIO version register"] +pub mod date; diff --git a/esp32p4/src/gpio/bist_ctrl.rs b/esp32p4/src/gpio/bist_ctrl.rs new file mode 100644 index 0000000000..1ed5bd1870 --- /dev/null +++ b/esp32p4/src/gpio/bist_ctrl.rs @@ -0,0 +1,71 @@ +#[doc = "Register `BIST_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `BIST_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `BIST_PAD_OE` reader - High speed sdio pad bist out pad oe"] +pub type BIST_PAD_OE_R = crate::BitReader; +#[doc = "Field `BIST_PAD_OE` writer - High speed sdio pad bist out pad oe"] +pub type BIST_PAD_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BIST_START` writer - High speed sdio pad bist start"] +pub type BIST_START_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - High speed sdio pad bist out pad oe"] + #[inline(always)] + pub fn bist_pad_oe(&self) -> BIST_PAD_OE_R { + BIST_PAD_OE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BIST_CTRL") + .field("bist_pad_oe", &format_args!("{}", self.bist_pad_oe().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - High speed sdio pad bist out pad oe"] + #[inline(always)] + #[must_use] + pub fn bist_pad_oe(&mut self) -> BIST_PAD_OE_W { + BIST_PAD_OE_W::new(self, 0) + } + #[doc = "Bit 1 - High speed sdio pad bist start"] + #[inline(always)] + #[must_use] + pub fn bist_start(&mut self) -> BIST_START_W { + BIST_START_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "High speed sdio pad bist control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bist_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bist_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BIST_CTRL_SPEC; +impl crate::RegisterSpec for BIST_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bist_ctrl::R`](R) reader structure"] +impl crate::Readable for BIST_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bist_ctrl::W`](W) writer structure"] +impl crate::Writable for BIST_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BIST_CTRL to value 0x01"] +impl crate::Resettable for BIST_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/gpio/bistin_sel.rs b/esp32p4/src/gpio/bistin_sel.rs new file mode 100644 index 0000000000..7b7b34e018 --- /dev/null +++ b/esp32p4/src/gpio/bistin_sel.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BISTIN_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `BISTIN_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `BISTIN_SEL` reader - High speed sdio pad bist in pad sel 0:pad39, 1: pad40..."] +pub type BISTIN_SEL_R = crate::FieldReader; +#[doc = "Field `BISTIN_SEL` writer - High speed sdio pad bist in pad sel 0:pad39, 1: pad40..."] +pub type BISTIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - High speed sdio pad bist in pad sel 0:pad39, 1: pad40..."] + #[inline(always)] + pub fn bistin_sel(&self) -> BISTIN_SEL_R { + BISTIN_SEL_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BISTIN_SEL") + .field("bistin_sel", &format_args!("{}", self.bistin_sel().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - High speed sdio pad bist in pad sel 0:pad39, 1: pad40..."] + #[inline(always)] + #[must_use] + pub fn bistin_sel(&mut self) -> BISTIN_SEL_W { + BISTIN_SEL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "High speed sdio pad bist in pad sel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bistin_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bistin_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BISTIN_SEL_SPEC; +impl crate::RegisterSpec for BISTIN_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bistin_sel::R`](R) reader structure"] +impl crate::Readable for BISTIN_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bistin_sel::W`](W) writer structure"] +impl crate::Writable for BISTIN_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BISTIN_SEL to value 0x0f"] +impl crate::Resettable for BISTIN_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/gpio/bt_select.rs b/esp32p4/src/gpio/bt_select.rs new file mode 100644 index 0000000000..56dab16db1 --- /dev/null +++ b/esp32p4/src/gpio/bt_select.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BT_SELECT` reader"] +pub type R = crate::R; +#[doc = "Register `BT_SELECT` writer"] +pub type W = crate::W; +#[doc = "Field `BT_SEL` reader - GPIO bit select register"] +pub type BT_SEL_R = crate::FieldReader; +#[doc = "Field `BT_SEL` writer - GPIO bit select register"] +pub type BT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - GPIO bit select register"] + #[inline(always)] + pub fn bt_sel(&self) -> BT_SEL_R { + BT_SEL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BT_SELECT") + .field("bt_sel", &format_args!("{}", self.bt_sel().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - GPIO bit select register"] + #[inline(always)] + #[must_use] + pub fn bt_sel(&mut self) -> BT_SEL_W { + BT_SEL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO bit select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bt_select::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bt_select::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BT_SELECT_SPEC; +impl crate::RegisterSpec for BT_SELECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bt_select::R`](R) reader structure"] +impl crate::Readable for BT_SELECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bt_select::W`](W) writer structure"] +impl crate::Writable for BT_SELECT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BT_SELECT to value 0"] +impl crate::Resettable for BT_SELECT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/clock_gate.rs b/esp32p4/src/gpio/clock_gate.rs new file mode 100644 index 0000000000..641a89d455 --- /dev/null +++ b/esp32p4/src/gpio/clock_gate.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLOCK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `CLOCK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - set this bit to enable GPIO clock gate"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - set this bit to enable GPIO clock gate"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - set this bit to enable GPIO clock gate"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCK_GATE") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this bit to enable GPIO clock gate"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLOCK_GATE_SPEC; +impl crate::RegisterSpec for CLOCK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"] +impl crate::Readable for CLOCK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"] +impl crate::Writable for CLOCK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"] +impl crate::Resettable for CLOCK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/gpio/date.rs b/esp32p4/src/gpio/date.rs new file mode 100644 index 0000000000..b63a4aec6a --- /dev/null +++ b/esp32p4/src/gpio/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - version register"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - version register"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - version register"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - version register"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0023_0403"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0023_0403; +} diff --git a/esp32p4/src/gpio/enable.rs b/esp32p4/src/gpio/enable.rs new file mode 100644 index 0000000000..dd0d265f34 --- /dev/null +++ b/esp32p4/src/gpio/enable.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` reader - GPIO output enable register for GPIO0-31"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - GPIO output enable register for GPIO0-31"] +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - GPIO output enable register for GPIO0-31"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - GPIO output enable register for GPIO0-31"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output enable register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`enable::R`](R) reader structure"] +impl crate::Readable for ENABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/enable1.rs b/esp32p4/src/gpio/enable1.rs new file mode 100644 index 0000000000..70ecd9e59a --- /dev/null +++ b/esp32p4/src/gpio/enable1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ENABLE1` reader"] +pub type R = crate::R; +#[doc = "Register `ENABLE1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` reader - GPIO output enable register for GPIO32-56"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - GPIO output enable register for GPIO32-56"] +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +impl R { + #[doc = "Bits 0:24 - GPIO output enable register for GPIO32-56"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE1") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:24 - GPIO output enable register for GPIO32-56"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output enable register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENABLE1_SPEC; +impl crate::RegisterSpec for ENABLE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`enable1::R`](R) reader structure"] +impl crate::Readable for ENABLE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable1::W`](W) writer structure"] +impl crate::Writable for ENABLE1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLE1 to value 0"] +impl crate::Resettable for ENABLE1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/enable1_w1tc.rs b/esp32p4/src/gpio/enable1_w1tc.rs new file mode 100644 index 0000000000..62909c8cf7 --- /dev/null +++ b/esp32p4/src/gpio/enable1_w1tc.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ENABLE1_W1TC` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE1_W1TC` writer - GPIO output enable clear register for GPIO32-56"] +pub type ENABLE1_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:24 - GPIO output enable clear register for GPIO32-56"] + #[inline(always)] + #[must_use] + pub fn enable1_w1tc(&mut self) -> ENABLE1_W1TC_W { + ENABLE1_W1TC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output enable clear register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable1_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENABLE1_W1TC_SPEC; +impl crate::RegisterSpec for ENABLE1_W1TC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`enable1_w1tc::W`](W) writer structure"] +impl crate::Writable for ENABLE1_W1TC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLE1_W1TC to value 0"] +impl crate::Resettable for ENABLE1_W1TC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/enable1_w1ts.rs b/esp32p4/src/gpio/enable1_w1ts.rs new file mode 100644 index 0000000000..63fc0a6330 --- /dev/null +++ b/esp32p4/src/gpio/enable1_w1ts.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ENABLE1_W1TS` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE1_W1TS` writer - GPIO output enable set register for GPIO32-56"] +pub type ENABLE1_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:24 - GPIO output enable set register for GPIO32-56"] + #[inline(always)] + #[must_use] + pub fn enable1_w1ts(&mut self) -> ENABLE1_W1TS_W { + ENABLE1_W1TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output enable set register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable1_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENABLE1_W1TS_SPEC; +impl crate::RegisterSpec for ENABLE1_W1TS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`enable1_w1ts::W`](W) writer structure"] +impl crate::Writable for ENABLE1_W1TS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLE1_W1TS to value 0"] +impl crate::Resettable for ENABLE1_W1TS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/enable_w1tc.rs b/esp32p4/src/gpio/enable_w1tc.rs new file mode 100644 index 0000000000..513b8c12bf --- /dev/null +++ b/esp32p4/src/gpio/enable_w1tc.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ENABLE_W1TC` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE_W1TC` writer - GPIO output enable clear register for GPIO0-31"] +pub type ENABLE_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - GPIO output enable clear register for GPIO0-31"] + #[inline(always)] + #[must_use] + pub fn enable_w1tc(&mut self) -> ENABLE_W1TC_W { + ENABLE_W1TC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output enable clear register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENABLE_W1TC_SPEC; +impl crate::RegisterSpec for ENABLE_W1TC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`enable_w1tc::W`](W) writer structure"] +impl crate::Writable for ENABLE_W1TC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLE_W1TC to value 0"] +impl crate::Resettable for ENABLE_W1TC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/enable_w1ts.rs b/esp32p4/src/gpio/enable_w1ts.rs new file mode 100644 index 0000000000..bfce1f50b6 --- /dev/null +++ b/esp32p4/src/gpio/enable_w1ts.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ENABLE_W1TS` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE_W1TS` writer - GPIO output enable set register for GPIO0-31"] +pub type ENABLE_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - GPIO output enable set register for GPIO0-31"] + #[inline(always)] + #[must_use] + pub fn enable_w1ts(&mut self) -> ENABLE_W1TS_W { + ENABLE_W1TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output enable set register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENABLE_W1TS_SPEC; +impl crate::RegisterSpec for ENABLE_W1TS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`enable_w1ts::W`](W) writer structure"] +impl crate::Writable for ENABLE_W1TS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLE_W1TS to value 0"] +impl crate::Resettable for ENABLE_W1TS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/func100_in_sel_cfg.rs b/esp32p4/src/gpio/func100_in_sel_cfg.rs new file mode 100644 index 0000000000..929bc8d110 --- /dev/null +++ b/esp32p4/src/gpio/func100_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC100_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC100_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC100_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC100_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC100_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC100_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC100_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC100_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC100_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC100_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG100_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG100_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG100_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG100_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func100_in_sel(&self) -> FUNC100_IN_SEL_R { + FUNC100_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func100_in_inv_sel(&self) -> FUNC100_IN_INV_SEL_R { + FUNC100_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig100_in_sel(&self) -> SIG100_IN_SEL_R { + SIG100_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC100_IN_SEL_CFG") + .field( + "func100_in_sel", + &format_args!("{}", self.func100_in_sel().bits()), + ) + .field( + "func100_in_inv_sel", + &format_args!("{}", self.func100_in_inv_sel().bit()), + ) + .field( + "sig100_in_sel", + &format_args!("{}", self.sig100_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func100_in_sel(&mut self) -> FUNC100_IN_SEL_W { + FUNC100_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func100_in_inv_sel(&mut self) -> FUNC100_IN_INV_SEL_W { + FUNC100_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig100_in_sel(&mut self) -> SIG100_IN_SEL_W { + SIG100_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func100_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func100_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC100_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC100_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func100_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC100_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func100_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC100_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC100_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC100_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func101_in_sel_cfg.rs b/esp32p4/src/gpio/func101_in_sel_cfg.rs new file mode 100644 index 0000000000..217ef89a05 --- /dev/null +++ b/esp32p4/src/gpio/func101_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC101_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC101_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC101_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC101_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC101_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC101_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC101_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC101_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC101_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC101_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG101_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG101_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG101_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG101_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func101_in_sel(&self) -> FUNC101_IN_SEL_R { + FUNC101_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func101_in_inv_sel(&self) -> FUNC101_IN_INV_SEL_R { + FUNC101_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig101_in_sel(&self) -> SIG101_IN_SEL_R { + SIG101_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC101_IN_SEL_CFG") + .field( + "func101_in_sel", + &format_args!("{}", self.func101_in_sel().bits()), + ) + .field( + "func101_in_inv_sel", + &format_args!("{}", self.func101_in_inv_sel().bit()), + ) + .field( + "sig101_in_sel", + &format_args!("{}", self.sig101_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func101_in_sel(&mut self) -> FUNC101_IN_SEL_W { + FUNC101_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func101_in_inv_sel(&mut self) -> FUNC101_IN_INV_SEL_W { + FUNC101_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig101_in_sel(&mut self) -> SIG101_IN_SEL_W { + SIG101_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func101_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func101_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC101_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC101_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func101_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC101_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func101_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC101_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC101_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC101_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func102_in_sel_cfg.rs b/esp32p4/src/gpio/func102_in_sel_cfg.rs new file mode 100644 index 0000000000..f1910fbe13 --- /dev/null +++ b/esp32p4/src/gpio/func102_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC102_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC102_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC102_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC102_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC102_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC102_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC102_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC102_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC102_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC102_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG102_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG102_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG102_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG102_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func102_in_sel(&self) -> FUNC102_IN_SEL_R { + FUNC102_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func102_in_inv_sel(&self) -> FUNC102_IN_INV_SEL_R { + FUNC102_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig102_in_sel(&self) -> SIG102_IN_SEL_R { + SIG102_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC102_IN_SEL_CFG") + .field( + "func102_in_sel", + &format_args!("{}", self.func102_in_sel().bits()), + ) + .field( + "func102_in_inv_sel", + &format_args!("{}", self.func102_in_inv_sel().bit()), + ) + .field( + "sig102_in_sel", + &format_args!("{}", self.sig102_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func102_in_sel(&mut self) -> FUNC102_IN_SEL_W { + FUNC102_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func102_in_inv_sel(&mut self) -> FUNC102_IN_INV_SEL_W { + FUNC102_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig102_in_sel(&mut self) -> SIG102_IN_SEL_W { + SIG102_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func102_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func102_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC102_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC102_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func102_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC102_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func102_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC102_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC102_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC102_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func103_in_sel_cfg.rs b/esp32p4/src/gpio/func103_in_sel_cfg.rs new file mode 100644 index 0000000000..63c93def61 --- /dev/null +++ b/esp32p4/src/gpio/func103_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC103_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC103_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC103_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC103_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC103_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC103_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC103_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC103_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC103_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC103_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG103_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG103_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG103_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG103_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func103_in_sel(&self) -> FUNC103_IN_SEL_R { + FUNC103_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func103_in_inv_sel(&self) -> FUNC103_IN_INV_SEL_R { + FUNC103_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig103_in_sel(&self) -> SIG103_IN_SEL_R { + SIG103_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC103_IN_SEL_CFG") + .field( + "func103_in_sel", + &format_args!("{}", self.func103_in_sel().bits()), + ) + .field( + "func103_in_inv_sel", + &format_args!("{}", self.func103_in_inv_sel().bit()), + ) + .field( + "sig103_in_sel", + &format_args!("{}", self.sig103_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func103_in_sel(&mut self) -> FUNC103_IN_SEL_W { + FUNC103_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func103_in_inv_sel(&mut self) -> FUNC103_IN_INV_SEL_W { + FUNC103_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig103_in_sel(&mut self) -> SIG103_IN_SEL_W { + SIG103_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func103_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func103_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC103_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC103_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func103_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC103_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func103_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC103_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC103_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC103_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func104_in_sel_cfg.rs b/esp32p4/src/gpio/func104_in_sel_cfg.rs new file mode 100644 index 0000000000..9544bee4ad --- /dev/null +++ b/esp32p4/src/gpio/func104_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC104_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC104_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC104_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC104_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC104_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC104_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC104_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC104_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC104_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC104_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG104_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG104_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG104_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG104_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func104_in_sel(&self) -> FUNC104_IN_SEL_R { + FUNC104_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func104_in_inv_sel(&self) -> FUNC104_IN_INV_SEL_R { + FUNC104_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig104_in_sel(&self) -> SIG104_IN_SEL_R { + SIG104_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC104_IN_SEL_CFG") + .field( + "func104_in_sel", + &format_args!("{}", self.func104_in_sel().bits()), + ) + .field( + "func104_in_inv_sel", + &format_args!("{}", self.func104_in_inv_sel().bit()), + ) + .field( + "sig104_in_sel", + &format_args!("{}", self.sig104_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func104_in_sel(&mut self) -> FUNC104_IN_SEL_W { + FUNC104_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func104_in_inv_sel(&mut self) -> FUNC104_IN_INV_SEL_W { + FUNC104_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig104_in_sel(&mut self) -> SIG104_IN_SEL_W { + SIG104_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func104_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func104_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC104_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC104_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func104_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC104_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func104_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC104_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC104_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC104_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func105_in_sel_cfg.rs b/esp32p4/src/gpio/func105_in_sel_cfg.rs new file mode 100644 index 0000000000..8b6e63689f --- /dev/null +++ b/esp32p4/src/gpio/func105_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC105_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC105_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC105_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC105_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC105_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC105_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC105_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC105_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC105_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC105_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG105_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG105_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG105_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG105_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func105_in_sel(&self) -> FUNC105_IN_SEL_R { + FUNC105_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func105_in_inv_sel(&self) -> FUNC105_IN_INV_SEL_R { + FUNC105_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig105_in_sel(&self) -> SIG105_IN_SEL_R { + SIG105_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC105_IN_SEL_CFG") + .field( + "func105_in_sel", + &format_args!("{}", self.func105_in_sel().bits()), + ) + .field( + "func105_in_inv_sel", + &format_args!("{}", self.func105_in_inv_sel().bit()), + ) + .field( + "sig105_in_sel", + &format_args!("{}", self.sig105_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func105_in_sel(&mut self) -> FUNC105_IN_SEL_W { + FUNC105_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func105_in_inv_sel(&mut self) -> FUNC105_IN_INV_SEL_W { + FUNC105_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig105_in_sel(&mut self) -> SIG105_IN_SEL_W { + SIG105_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func105_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func105_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC105_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC105_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func105_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC105_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func105_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC105_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC105_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC105_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func106_in_sel_cfg.rs b/esp32p4/src/gpio/func106_in_sel_cfg.rs new file mode 100644 index 0000000000..4b04ed4850 --- /dev/null +++ b/esp32p4/src/gpio/func106_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC106_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC106_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC106_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC106_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC106_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC106_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC106_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC106_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC106_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC106_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG106_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG106_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG106_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG106_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func106_in_sel(&self) -> FUNC106_IN_SEL_R { + FUNC106_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func106_in_inv_sel(&self) -> FUNC106_IN_INV_SEL_R { + FUNC106_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig106_in_sel(&self) -> SIG106_IN_SEL_R { + SIG106_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC106_IN_SEL_CFG") + .field( + "func106_in_sel", + &format_args!("{}", self.func106_in_sel().bits()), + ) + .field( + "func106_in_inv_sel", + &format_args!("{}", self.func106_in_inv_sel().bit()), + ) + .field( + "sig106_in_sel", + &format_args!("{}", self.sig106_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func106_in_sel(&mut self) -> FUNC106_IN_SEL_W { + FUNC106_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func106_in_inv_sel(&mut self) -> FUNC106_IN_INV_SEL_W { + FUNC106_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig106_in_sel(&mut self) -> SIG106_IN_SEL_W { + SIG106_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func106_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func106_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC106_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC106_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func106_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC106_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func106_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC106_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC106_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC106_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func107_in_sel_cfg.rs b/esp32p4/src/gpio/func107_in_sel_cfg.rs new file mode 100644 index 0000000000..7c2d9659e0 --- /dev/null +++ b/esp32p4/src/gpio/func107_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC107_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC107_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC107_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC107_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC107_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC107_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC107_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC107_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC107_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC107_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG107_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG107_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG107_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG107_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func107_in_sel(&self) -> FUNC107_IN_SEL_R { + FUNC107_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func107_in_inv_sel(&self) -> FUNC107_IN_INV_SEL_R { + FUNC107_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig107_in_sel(&self) -> SIG107_IN_SEL_R { + SIG107_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC107_IN_SEL_CFG") + .field( + "func107_in_sel", + &format_args!("{}", self.func107_in_sel().bits()), + ) + .field( + "func107_in_inv_sel", + &format_args!("{}", self.func107_in_inv_sel().bit()), + ) + .field( + "sig107_in_sel", + &format_args!("{}", self.sig107_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func107_in_sel(&mut self) -> FUNC107_IN_SEL_W { + FUNC107_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func107_in_inv_sel(&mut self) -> FUNC107_IN_INV_SEL_W { + FUNC107_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig107_in_sel(&mut self) -> SIG107_IN_SEL_W { + SIG107_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func107_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func107_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC107_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC107_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func107_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC107_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func107_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC107_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC107_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC107_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func108_in_sel_cfg.rs b/esp32p4/src/gpio/func108_in_sel_cfg.rs new file mode 100644 index 0000000000..fb6341759b --- /dev/null +++ b/esp32p4/src/gpio/func108_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC108_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC108_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC108_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC108_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC108_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC108_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC108_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC108_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC108_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC108_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG108_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG108_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG108_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG108_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func108_in_sel(&self) -> FUNC108_IN_SEL_R { + FUNC108_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func108_in_inv_sel(&self) -> FUNC108_IN_INV_SEL_R { + FUNC108_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig108_in_sel(&self) -> SIG108_IN_SEL_R { + SIG108_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC108_IN_SEL_CFG") + .field( + "func108_in_sel", + &format_args!("{}", self.func108_in_sel().bits()), + ) + .field( + "func108_in_inv_sel", + &format_args!("{}", self.func108_in_inv_sel().bit()), + ) + .field( + "sig108_in_sel", + &format_args!("{}", self.sig108_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func108_in_sel(&mut self) -> FUNC108_IN_SEL_W { + FUNC108_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func108_in_inv_sel(&mut self) -> FUNC108_IN_INV_SEL_W { + FUNC108_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig108_in_sel(&mut self) -> SIG108_IN_SEL_W { + SIG108_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func108_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func108_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC108_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC108_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func108_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC108_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func108_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC108_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC108_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC108_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func109_in_sel_cfg.rs b/esp32p4/src/gpio/func109_in_sel_cfg.rs new file mode 100644 index 0000000000..87c51eaff6 --- /dev/null +++ b/esp32p4/src/gpio/func109_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC109_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC109_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC109_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC109_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC109_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC109_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC109_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC109_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC109_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC109_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG109_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG109_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG109_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG109_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func109_in_sel(&self) -> FUNC109_IN_SEL_R { + FUNC109_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func109_in_inv_sel(&self) -> FUNC109_IN_INV_SEL_R { + FUNC109_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig109_in_sel(&self) -> SIG109_IN_SEL_R { + SIG109_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC109_IN_SEL_CFG") + .field( + "func109_in_sel", + &format_args!("{}", self.func109_in_sel().bits()), + ) + .field( + "func109_in_inv_sel", + &format_args!("{}", self.func109_in_inv_sel().bit()), + ) + .field( + "sig109_in_sel", + &format_args!("{}", self.sig109_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func109_in_sel(&mut self) -> FUNC109_IN_SEL_W { + FUNC109_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func109_in_inv_sel(&mut self) -> FUNC109_IN_INV_SEL_W { + FUNC109_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig109_in_sel(&mut self) -> SIG109_IN_SEL_W { + SIG109_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func109_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func109_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC109_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC109_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func109_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC109_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func109_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC109_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC109_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC109_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func10_in_sel_cfg.rs b/esp32p4/src/gpio/func10_in_sel_cfg.rs new file mode 100644 index 0000000000..4e1deb03c1 --- /dev/null +++ b/esp32p4/src/gpio/func10_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC10_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC10_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC10_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC10_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC10_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC10_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC10_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC10_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC10_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC10_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG10_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG10_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG10_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG10_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func10_in_sel(&self) -> FUNC10_IN_SEL_R { + FUNC10_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func10_in_inv_sel(&self) -> FUNC10_IN_INV_SEL_R { + FUNC10_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig10_in_sel(&self) -> SIG10_IN_SEL_R { + SIG10_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC10_IN_SEL_CFG") + .field( + "func10_in_sel", + &format_args!("{}", self.func10_in_sel().bits()), + ) + .field( + "func10_in_inv_sel", + &format_args!("{}", self.func10_in_inv_sel().bit()), + ) + .field( + "sig10_in_sel", + &format_args!("{}", self.sig10_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func10_in_sel(&mut self) -> FUNC10_IN_SEL_W { + FUNC10_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func10_in_inv_sel(&mut self) -> FUNC10_IN_INV_SEL_W { + FUNC10_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig10_in_sel(&mut self) -> SIG10_IN_SEL_W { + SIG10_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func10_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func10_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC10_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC10_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func10_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC10_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func10_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC10_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC10_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC10_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func110_in_sel_cfg.rs b/esp32p4/src/gpio/func110_in_sel_cfg.rs new file mode 100644 index 0000000000..a366d6d486 --- /dev/null +++ b/esp32p4/src/gpio/func110_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC110_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC110_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC110_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC110_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC110_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC110_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC110_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC110_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC110_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC110_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG110_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG110_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG110_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG110_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func110_in_sel(&self) -> FUNC110_IN_SEL_R { + FUNC110_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func110_in_inv_sel(&self) -> FUNC110_IN_INV_SEL_R { + FUNC110_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig110_in_sel(&self) -> SIG110_IN_SEL_R { + SIG110_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC110_IN_SEL_CFG") + .field( + "func110_in_sel", + &format_args!("{}", self.func110_in_sel().bits()), + ) + .field( + "func110_in_inv_sel", + &format_args!("{}", self.func110_in_inv_sel().bit()), + ) + .field( + "sig110_in_sel", + &format_args!("{}", self.sig110_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func110_in_sel(&mut self) -> FUNC110_IN_SEL_W { + FUNC110_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func110_in_inv_sel(&mut self) -> FUNC110_IN_INV_SEL_W { + FUNC110_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig110_in_sel(&mut self) -> SIG110_IN_SEL_W { + SIG110_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func110_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func110_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC110_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC110_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func110_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC110_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func110_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC110_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC110_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC110_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func111_in_sel_cfg.rs b/esp32p4/src/gpio/func111_in_sel_cfg.rs new file mode 100644 index 0000000000..bbc877b3cc --- /dev/null +++ b/esp32p4/src/gpio/func111_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC111_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC111_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC111_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC111_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC111_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC111_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC111_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC111_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC111_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC111_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG111_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG111_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG111_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG111_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func111_in_sel(&self) -> FUNC111_IN_SEL_R { + FUNC111_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func111_in_inv_sel(&self) -> FUNC111_IN_INV_SEL_R { + FUNC111_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig111_in_sel(&self) -> SIG111_IN_SEL_R { + SIG111_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC111_IN_SEL_CFG") + .field( + "func111_in_sel", + &format_args!("{}", self.func111_in_sel().bits()), + ) + .field( + "func111_in_inv_sel", + &format_args!("{}", self.func111_in_inv_sel().bit()), + ) + .field( + "sig111_in_sel", + &format_args!("{}", self.sig111_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func111_in_sel(&mut self) -> FUNC111_IN_SEL_W { + FUNC111_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func111_in_inv_sel(&mut self) -> FUNC111_IN_INV_SEL_W { + FUNC111_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig111_in_sel(&mut self) -> SIG111_IN_SEL_W { + SIG111_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func111_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func111_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC111_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC111_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func111_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC111_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func111_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC111_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC111_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC111_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func112_in_sel_cfg.rs b/esp32p4/src/gpio/func112_in_sel_cfg.rs new file mode 100644 index 0000000000..02a1dc1132 --- /dev/null +++ b/esp32p4/src/gpio/func112_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC112_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC112_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC112_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC112_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC112_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC112_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC112_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC112_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC112_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC112_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG112_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG112_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG112_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG112_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func112_in_sel(&self) -> FUNC112_IN_SEL_R { + FUNC112_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func112_in_inv_sel(&self) -> FUNC112_IN_INV_SEL_R { + FUNC112_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig112_in_sel(&self) -> SIG112_IN_SEL_R { + SIG112_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC112_IN_SEL_CFG") + .field( + "func112_in_sel", + &format_args!("{}", self.func112_in_sel().bits()), + ) + .field( + "func112_in_inv_sel", + &format_args!("{}", self.func112_in_inv_sel().bit()), + ) + .field( + "sig112_in_sel", + &format_args!("{}", self.sig112_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func112_in_sel(&mut self) -> FUNC112_IN_SEL_W { + FUNC112_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func112_in_inv_sel(&mut self) -> FUNC112_IN_INV_SEL_W { + FUNC112_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig112_in_sel(&mut self) -> SIG112_IN_SEL_W { + SIG112_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func112_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func112_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC112_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC112_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func112_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC112_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func112_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC112_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC112_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC112_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func113_in_sel_cfg.rs b/esp32p4/src/gpio/func113_in_sel_cfg.rs new file mode 100644 index 0000000000..ca73639b65 --- /dev/null +++ b/esp32p4/src/gpio/func113_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC113_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC113_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC113_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC113_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC113_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC113_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC113_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC113_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC113_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC113_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG113_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG113_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG113_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG113_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func113_in_sel(&self) -> FUNC113_IN_SEL_R { + FUNC113_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func113_in_inv_sel(&self) -> FUNC113_IN_INV_SEL_R { + FUNC113_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig113_in_sel(&self) -> SIG113_IN_SEL_R { + SIG113_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC113_IN_SEL_CFG") + .field( + "func113_in_sel", + &format_args!("{}", self.func113_in_sel().bits()), + ) + .field( + "func113_in_inv_sel", + &format_args!("{}", self.func113_in_inv_sel().bit()), + ) + .field( + "sig113_in_sel", + &format_args!("{}", self.sig113_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func113_in_sel(&mut self) -> FUNC113_IN_SEL_W { + FUNC113_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func113_in_inv_sel(&mut self) -> FUNC113_IN_INV_SEL_W { + FUNC113_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig113_in_sel(&mut self) -> SIG113_IN_SEL_W { + SIG113_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func113_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func113_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC113_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC113_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func113_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC113_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func113_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC113_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC113_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC113_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func114_in_sel_cfg.rs b/esp32p4/src/gpio/func114_in_sel_cfg.rs new file mode 100644 index 0000000000..d20c09ecec --- /dev/null +++ b/esp32p4/src/gpio/func114_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC114_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC114_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC114_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC114_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC114_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC114_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC114_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC114_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC114_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC114_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG114_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG114_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG114_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG114_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func114_in_sel(&self) -> FUNC114_IN_SEL_R { + FUNC114_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func114_in_inv_sel(&self) -> FUNC114_IN_INV_SEL_R { + FUNC114_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig114_in_sel(&self) -> SIG114_IN_SEL_R { + SIG114_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC114_IN_SEL_CFG") + .field( + "func114_in_sel", + &format_args!("{}", self.func114_in_sel().bits()), + ) + .field( + "func114_in_inv_sel", + &format_args!("{}", self.func114_in_inv_sel().bit()), + ) + .field( + "sig114_in_sel", + &format_args!("{}", self.sig114_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func114_in_sel(&mut self) -> FUNC114_IN_SEL_W { + FUNC114_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func114_in_inv_sel(&mut self) -> FUNC114_IN_INV_SEL_W { + FUNC114_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig114_in_sel(&mut self) -> SIG114_IN_SEL_W { + SIG114_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func114_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func114_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC114_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC114_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func114_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC114_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func114_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC114_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC114_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC114_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func117_in_sel_cfg.rs b/esp32p4/src/gpio/func117_in_sel_cfg.rs new file mode 100644 index 0000000000..b42dac86bc --- /dev/null +++ b/esp32p4/src/gpio/func117_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC117_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC117_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC117_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC117_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC117_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC117_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC117_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC117_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC117_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC117_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG117_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG117_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG117_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG117_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func117_in_sel(&self) -> FUNC117_IN_SEL_R { + FUNC117_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func117_in_inv_sel(&self) -> FUNC117_IN_INV_SEL_R { + FUNC117_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig117_in_sel(&self) -> SIG117_IN_SEL_R { + SIG117_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC117_IN_SEL_CFG") + .field( + "func117_in_sel", + &format_args!("{}", self.func117_in_sel().bits()), + ) + .field( + "func117_in_inv_sel", + &format_args!("{}", self.func117_in_inv_sel().bit()), + ) + .field( + "sig117_in_sel", + &format_args!("{}", self.sig117_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func117_in_sel(&mut self) -> FUNC117_IN_SEL_W { + FUNC117_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func117_in_inv_sel(&mut self) -> FUNC117_IN_INV_SEL_W { + FUNC117_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig117_in_sel(&mut self) -> SIG117_IN_SEL_W { + SIG117_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func117_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func117_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC117_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC117_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func117_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC117_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func117_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC117_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC117_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC117_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func118_in_sel_cfg.rs b/esp32p4/src/gpio/func118_in_sel_cfg.rs new file mode 100644 index 0000000000..e5222f49b6 --- /dev/null +++ b/esp32p4/src/gpio/func118_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC118_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC118_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC118_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC118_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC118_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC118_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC118_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC118_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC118_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC118_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG118_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG118_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG118_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG118_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func118_in_sel(&self) -> FUNC118_IN_SEL_R { + FUNC118_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func118_in_inv_sel(&self) -> FUNC118_IN_INV_SEL_R { + FUNC118_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig118_in_sel(&self) -> SIG118_IN_SEL_R { + SIG118_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC118_IN_SEL_CFG") + .field( + "func118_in_sel", + &format_args!("{}", self.func118_in_sel().bits()), + ) + .field( + "func118_in_inv_sel", + &format_args!("{}", self.func118_in_inv_sel().bit()), + ) + .field( + "sig118_in_sel", + &format_args!("{}", self.sig118_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func118_in_sel(&mut self) -> FUNC118_IN_SEL_W { + FUNC118_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func118_in_inv_sel(&mut self) -> FUNC118_IN_INV_SEL_W { + FUNC118_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig118_in_sel(&mut self) -> SIG118_IN_SEL_W { + SIG118_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func118_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func118_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC118_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC118_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func118_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC118_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func118_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC118_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC118_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC118_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func11_in_sel_cfg.rs b/esp32p4/src/gpio/func11_in_sel_cfg.rs new file mode 100644 index 0000000000..9e49e49d29 --- /dev/null +++ b/esp32p4/src/gpio/func11_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC11_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC11_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC11_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC11_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC11_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC11_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC11_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC11_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC11_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC11_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG11_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG11_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG11_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG11_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func11_in_sel(&self) -> FUNC11_IN_SEL_R { + FUNC11_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func11_in_inv_sel(&self) -> FUNC11_IN_INV_SEL_R { + FUNC11_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig11_in_sel(&self) -> SIG11_IN_SEL_R { + SIG11_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC11_IN_SEL_CFG") + .field( + "func11_in_sel", + &format_args!("{}", self.func11_in_sel().bits()), + ) + .field( + "func11_in_inv_sel", + &format_args!("{}", self.func11_in_inv_sel().bit()), + ) + .field( + "sig11_in_sel", + &format_args!("{}", self.sig11_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func11_in_sel(&mut self) -> FUNC11_IN_SEL_W { + FUNC11_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func11_in_inv_sel(&mut self) -> FUNC11_IN_INV_SEL_W { + FUNC11_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig11_in_sel(&mut self) -> SIG11_IN_SEL_W { + SIG11_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func11_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func11_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC11_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC11_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func11_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC11_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func11_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC11_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC11_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC11_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func126_in_sel_cfg.rs b/esp32p4/src/gpio/func126_in_sel_cfg.rs new file mode 100644 index 0000000000..b1d7a08ba4 --- /dev/null +++ b/esp32p4/src/gpio/func126_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC126_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC126_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC126_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC126_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC126_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC126_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC126_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC126_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC126_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC126_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG126_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG126_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG126_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG126_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func126_in_sel(&self) -> FUNC126_IN_SEL_R { + FUNC126_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func126_in_inv_sel(&self) -> FUNC126_IN_INV_SEL_R { + FUNC126_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig126_in_sel(&self) -> SIG126_IN_SEL_R { + SIG126_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC126_IN_SEL_CFG") + .field( + "func126_in_sel", + &format_args!("{}", self.func126_in_sel().bits()), + ) + .field( + "func126_in_inv_sel", + &format_args!("{}", self.func126_in_inv_sel().bit()), + ) + .field( + "sig126_in_sel", + &format_args!("{}", self.sig126_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func126_in_sel(&mut self) -> FUNC126_IN_SEL_W { + FUNC126_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func126_in_inv_sel(&mut self) -> FUNC126_IN_INV_SEL_W { + FUNC126_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig126_in_sel(&mut self) -> SIG126_IN_SEL_W { + SIG126_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func126_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func126_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC126_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC126_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func126_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC126_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func126_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC126_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC126_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC126_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func127_in_sel_cfg.rs b/esp32p4/src/gpio/func127_in_sel_cfg.rs new file mode 100644 index 0000000000..0e0c445ec7 --- /dev/null +++ b/esp32p4/src/gpio/func127_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC127_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC127_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC127_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC127_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC127_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC127_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC127_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC127_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC127_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC127_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG127_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG127_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG127_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG127_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func127_in_sel(&self) -> FUNC127_IN_SEL_R { + FUNC127_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func127_in_inv_sel(&self) -> FUNC127_IN_INV_SEL_R { + FUNC127_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig127_in_sel(&self) -> SIG127_IN_SEL_R { + SIG127_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC127_IN_SEL_CFG") + .field( + "func127_in_sel", + &format_args!("{}", self.func127_in_sel().bits()), + ) + .field( + "func127_in_inv_sel", + &format_args!("{}", self.func127_in_inv_sel().bit()), + ) + .field( + "sig127_in_sel", + &format_args!("{}", self.sig127_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func127_in_sel(&mut self) -> FUNC127_IN_SEL_W { + FUNC127_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func127_in_inv_sel(&mut self) -> FUNC127_IN_INV_SEL_W { + FUNC127_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig127_in_sel(&mut self) -> SIG127_IN_SEL_W { + SIG127_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func127_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func127_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC127_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC127_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func127_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC127_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func127_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC127_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC127_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC127_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func128_in_sel_cfg.rs b/esp32p4/src/gpio/func128_in_sel_cfg.rs new file mode 100644 index 0000000000..bacdf24f34 --- /dev/null +++ b/esp32p4/src/gpio/func128_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC128_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC128_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC128_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC128_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC128_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC128_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC128_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC128_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC128_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC128_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG128_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG128_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG128_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG128_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func128_in_sel(&self) -> FUNC128_IN_SEL_R { + FUNC128_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func128_in_inv_sel(&self) -> FUNC128_IN_INV_SEL_R { + FUNC128_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig128_in_sel(&self) -> SIG128_IN_SEL_R { + SIG128_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC128_IN_SEL_CFG") + .field( + "func128_in_sel", + &format_args!("{}", self.func128_in_sel().bits()), + ) + .field( + "func128_in_inv_sel", + &format_args!("{}", self.func128_in_inv_sel().bit()), + ) + .field( + "sig128_in_sel", + &format_args!("{}", self.sig128_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func128_in_sel(&mut self) -> FUNC128_IN_SEL_W { + FUNC128_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func128_in_inv_sel(&mut self) -> FUNC128_IN_INV_SEL_W { + FUNC128_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig128_in_sel(&mut self) -> SIG128_IN_SEL_W { + SIG128_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func128_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func128_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC128_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC128_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func128_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC128_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func128_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC128_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC128_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC128_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func129_in_sel_cfg.rs b/esp32p4/src/gpio/func129_in_sel_cfg.rs new file mode 100644 index 0000000000..7070c0769f --- /dev/null +++ b/esp32p4/src/gpio/func129_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC129_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC129_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC129_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC129_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC129_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC129_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC129_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC129_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC129_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC129_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG129_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG129_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG129_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG129_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func129_in_sel(&self) -> FUNC129_IN_SEL_R { + FUNC129_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func129_in_inv_sel(&self) -> FUNC129_IN_INV_SEL_R { + FUNC129_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig129_in_sel(&self) -> SIG129_IN_SEL_R { + SIG129_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC129_IN_SEL_CFG") + .field( + "func129_in_sel", + &format_args!("{}", self.func129_in_sel().bits()), + ) + .field( + "func129_in_inv_sel", + &format_args!("{}", self.func129_in_inv_sel().bit()), + ) + .field( + "sig129_in_sel", + &format_args!("{}", self.sig129_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func129_in_sel(&mut self) -> FUNC129_IN_SEL_W { + FUNC129_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func129_in_inv_sel(&mut self) -> FUNC129_IN_INV_SEL_W { + FUNC129_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig129_in_sel(&mut self) -> SIG129_IN_SEL_W { + SIG129_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func129_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func129_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC129_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC129_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func129_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC129_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func129_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC129_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC129_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC129_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func12_in_sel_cfg.rs b/esp32p4/src/gpio/func12_in_sel_cfg.rs new file mode 100644 index 0000000000..864e03ab8b --- /dev/null +++ b/esp32p4/src/gpio/func12_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC12_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC12_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC12_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC12_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC12_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC12_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC12_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC12_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC12_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC12_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG12_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG12_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG12_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG12_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func12_in_sel(&self) -> FUNC12_IN_SEL_R { + FUNC12_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func12_in_inv_sel(&self) -> FUNC12_IN_INV_SEL_R { + FUNC12_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig12_in_sel(&self) -> SIG12_IN_SEL_R { + SIG12_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC12_IN_SEL_CFG") + .field( + "func12_in_sel", + &format_args!("{}", self.func12_in_sel().bits()), + ) + .field( + "func12_in_inv_sel", + &format_args!("{}", self.func12_in_inv_sel().bit()), + ) + .field( + "sig12_in_sel", + &format_args!("{}", self.sig12_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func12_in_sel(&mut self) -> FUNC12_IN_SEL_W { + FUNC12_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func12_in_inv_sel(&mut self) -> FUNC12_IN_INV_SEL_W { + FUNC12_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig12_in_sel(&mut self) -> SIG12_IN_SEL_W { + SIG12_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func12_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func12_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC12_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC12_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func12_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC12_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func12_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC12_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC12_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC12_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func130_in_sel_cfg.rs b/esp32p4/src/gpio/func130_in_sel_cfg.rs new file mode 100644 index 0000000000..898bf1f07a --- /dev/null +++ b/esp32p4/src/gpio/func130_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC130_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC130_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC130_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC130_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC130_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC130_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC130_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC130_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC130_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC130_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG130_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG130_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG130_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG130_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func130_in_sel(&self) -> FUNC130_IN_SEL_R { + FUNC130_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func130_in_inv_sel(&self) -> FUNC130_IN_INV_SEL_R { + FUNC130_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig130_in_sel(&self) -> SIG130_IN_SEL_R { + SIG130_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC130_IN_SEL_CFG") + .field( + "func130_in_sel", + &format_args!("{}", self.func130_in_sel().bits()), + ) + .field( + "func130_in_inv_sel", + &format_args!("{}", self.func130_in_inv_sel().bit()), + ) + .field( + "sig130_in_sel", + &format_args!("{}", self.sig130_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func130_in_sel(&mut self) -> FUNC130_IN_SEL_W { + FUNC130_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func130_in_inv_sel(&mut self) -> FUNC130_IN_INV_SEL_W { + FUNC130_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig130_in_sel(&mut self) -> SIG130_IN_SEL_W { + SIG130_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func130_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func130_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC130_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC130_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func130_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC130_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func130_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC130_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC130_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC130_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func131_in_sel_cfg.rs b/esp32p4/src/gpio/func131_in_sel_cfg.rs new file mode 100644 index 0000000000..31f491fd13 --- /dev/null +++ b/esp32p4/src/gpio/func131_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC131_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC131_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC131_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC131_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC131_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC131_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC131_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC131_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC131_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC131_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG131_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG131_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG131_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG131_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func131_in_sel(&self) -> FUNC131_IN_SEL_R { + FUNC131_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func131_in_inv_sel(&self) -> FUNC131_IN_INV_SEL_R { + FUNC131_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig131_in_sel(&self) -> SIG131_IN_SEL_R { + SIG131_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC131_IN_SEL_CFG") + .field( + "func131_in_sel", + &format_args!("{}", self.func131_in_sel().bits()), + ) + .field( + "func131_in_inv_sel", + &format_args!("{}", self.func131_in_inv_sel().bit()), + ) + .field( + "sig131_in_sel", + &format_args!("{}", self.sig131_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func131_in_sel(&mut self) -> FUNC131_IN_SEL_W { + FUNC131_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func131_in_inv_sel(&mut self) -> FUNC131_IN_INV_SEL_W { + FUNC131_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig131_in_sel(&mut self) -> SIG131_IN_SEL_W { + SIG131_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func131_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func131_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC131_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC131_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func131_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC131_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func131_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC131_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC131_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC131_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func132_in_sel_cfg.rs b/esp32p4/src/gpio/func132_in_sel_cfg.rs new file mode 100644 index 0000000000..60c8b7cf79 --- /dev/null +++ b/esp32p4/src/gpio/func132_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC132_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC132_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC132_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC132_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC132_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC132_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC132_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC132_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC132_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC132_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG132_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG132_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG132_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG132_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func132_in_sel(&self) -> FUNC132_IN_SEL_R { + FUNC132_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func132_in_inv_sel(&self) -> FUNC132_IN_INV_SEL_R { + FUNC132_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig132_in_sel(&self) -> SIG132_IN_SEL_R { + SIG132_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC132_IN_SEL_CFG") + .field( + "func132_in_sel", + &format_args!("{}", self.func132_in_sel().bits()), + ) + .field( + "func132_in_inv_sel", + &format_args!("{}", self.func132_in_inv_sel().bit()), + ) + .field( + "sig132_in_sel", + &format_args!("{}", self.sig132_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func132_in_sel(&mut self) -> FUNC132_IN_SEL_W { + FUNC132_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func132_in_inv_sel(&mut self) -> FUNC132_IN_INV_SEL_W { + FUNC132_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig132_in_sel(&mut self) -> SIG132_IN_SEL_W { + SIG132_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func132_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func132_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC132_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC132_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func132_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC132_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func132_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC132_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC132_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC132_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func133_in_sel_cfg.rs b/esp32p4/src/gpio/func133_in_sel_cfg.rs new file mode 100644 index 0000000000..55af6e52c0 --- /dev/null +++ b/esp32p4/src/gpio/func133_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC133_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC133_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC133_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC133_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC133_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC133_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC133_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC133_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC133_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC133_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG133_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG133_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG133_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG133_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func133_in_sel(&self) -> FUNC133_IN_SEL_R { + FUNC133_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func133_in_inv_sel(&self) -> FUNC133_IN_INV_SEL_R { + FUNC133_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig133_in_sel(&self) -> SIG133_IN_SEL_R { + SIG133_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC133_IN_SEL_CFG") + .field( + "func133_in_sel", + &format_args!("{}", self.func133_in_sel().bits()), + ) + .field( + "func133_in_inv_sel", + &format_args!("{}", self.func133_in_inv_sel().bit()), + ) + .field( + "sig133_in_sel", + &format_args!("{}", self.sig133_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func133_in_sel(&mut self) -> FUNC133_IN_SEL_W { + FUNC133_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func133_in_inv_sel(&mut self) -> FUNC133_IN_INV_SEL_W { + FUNC133_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig133_in_sel(&mut self) -> SIG133_IN_SEL_W { + SIG133_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func133_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func133_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC133_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC133_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func133_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC133_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func133_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC133_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC133_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC133_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func134_in_sel_cfg.rs b/esp32p4/src/gpio/func134_in_sel_cfg.rs new file mode 100644 index 0000000000..5d58b519f9 --- /dev/null +++ b/esp32p4/src/gpio/func134_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC134_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC134_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC134_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC134_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC134_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC134_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC134_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC134_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC134_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC134_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG134_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG134_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG134_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG134_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func134_in_sel(&self) -> FUNC134_IN_SEL_R { + FUNC134_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func134_in_inv_sel(&self) -> FUNC134_IN_INV_SEL_R { + FUNC134_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig134_in_sel(&self) -> SIG134_IN_SEL_R { + SIG134_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC134_IN_SEL_CFG") + .field( + "func134_in_sel", + &format_args!("{}", self.func134_in_sel().bits()), + ) + .field( + "func134_in_inv_sel", + &format_args!("{}", self.func134_in_inv_sel().bit()), + ) + .field( + "sig134_in_sel", + &format_args!("{}", self.sig134_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func134_in_sel(&mut self) -> FUNC134_IN_SEL_W { + FUNC134_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func134_in_inv_sel(&mut self) -> FUNC134_IN_INV_SEL_W { + FUNC134_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig134_in_sel(&mut self) -> SIG134_IN_SEL_W { + SIG134_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func134_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func134_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC134_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC134_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func134_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC134_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func134_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC134_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC134_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC134_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func135_in_sel_cfg.rs b/esp32p4/src/gpio/func135_in_sel_cfg.rs new file mode 100644 index 0000000000..548e829e39 --- /dev/null +++ b/esp32p4/src/gpio/func135_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC135_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC135_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC135_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC135_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC135_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC135_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC135_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC135_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC135_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC135_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG135_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG135_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG135_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG135_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func135_in_sel(&self) -> FUNC135_IN_SEL_R { + FUNC135_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func135_in_inv_sel(&self) -> FUNC135_IN_INV_SEL_R { + FUNC135_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig135_in_sel(&self) -> SIG135_IN_SEL_R { + SIG135_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC135_IN_SEL_CFG") + .field( + "func135_in_sel", + &format_args!("{}", self.func135_in_sel().bits()), + ) + .field( + "func135_in_inv_sel", + &format_args!("{}", self.func135_in_inv_sel().bit()), + ) + .field( + "sig135_in_sel", + &format_args!("{}", self.sig135_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func135_in_sel(&mut self) -> FUNC135_IN_SEL_W { + FUNC135_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func135_in_inv_sel(&mut self) -> FUNC135_IN_INV_SEL_W { + FUNC135_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig135_in_sel(&mut self) -> SIG135_IN_SEL_W { + SIG135_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func135_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func135_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC135_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC135_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func135_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC135_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func135_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC135_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC135_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC135_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func136_in_sel_cfg.rs b/esp32p4/src/gpio/func136_in_sel_cfg.rs new file mode 100644 index 0000000000..67de754581 --- /dev/null +++ b/esp32p4/src/gpio/func136_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC136_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC136_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC136_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC136_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC136_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC136_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC136_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC136_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC136_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC136_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG136_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG136_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG136_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG136_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func136_in_sel(&self) -> FUNC136_IN_SEL_R { + FUNC136_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func136_in_inv_sel(&self) -> FUNC136_IN_INV_SEL_R { + FUNC136_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig136_in_sel(&self) -> SIG136_IN_SEL_R { + SIG136_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC136_IN_SEL_CFG") + .field( + "func136_in_sel", + &format_args!("{}", self.func136_in_sel().bits()), + ) + .field( + "func136_in_inv_sel", + &format_args!("{}", self.func136_in_inv_sel().bit()), + ) + .field( + "sig136_in_sel", + &format_args!("{}", self.sig136_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func136_in_sel(&mut self) -> FUNC136_IN_SEL_W { + FUNC136_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func136_in_inv_sel(&mut self) -> FUNC136_IN_INV_SEL_W { + FUNC136_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig136_in_sel(&mut self) -> SIG136_IN_SEL_W { + SIG136_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func136_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func136_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC136_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC136_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func136_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC136_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func136_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC136_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC136_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC136_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func137_in_sel_cfg.rs b/esp32p4/src/gpio/func137_in_sel_cfg.rs new file mode 100644 index 0000000000..b26f90668c --- /dev/null +++ b/esp32p4/src/gpio/func137_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC137_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC137_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC137_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC137_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC137_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC137_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC137_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC137_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC137_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC137_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG137_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG137_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG137_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG137_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func137_in_sel(&self) -> FUNC137_IN_SEL_R { + FUNC137_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func137_in_inv_sel(&self) -> FUNC137_IN_INV_SEL_R { + FUNC137_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig137_in_sel(&self) -> SIG137_IN_SEL_R { + SIG137_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC137_IN_SEL_CFG") + .field( + "func137_in_sel", + &format_args!("{}", self.func137_in_sel().bits()), + ) + .field( + "func137_in_inv_sel", + &format_args!("{}", self.func137_in_inv_sel().bit()), + ) + .field( + "sig137_in_sel", + &format_args!("{}", self.sig137_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func137_in_sel(&mut self) -> FUNC137_IN_SEL_W { + FUNC137_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func137_in_inv_sel(&mut self) -> FUNC137_IN_INV_SEL_W { + FUNC137_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig137_in_sel(&mut self) -> SIG137_IN_SEL_W { + SIG137_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func137_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func137_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC137_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC137_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func137_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC137_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func137_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC137_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC137_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC137_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func138_in_sel_cfg.rs b/esp32p4/src/gpio/func138_in_sel_cfg.rs new file mode 100644 index 0000000000..5a8b8a3b6e --- /dev/null +++ b/esp32p4/src/gpio/func138_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC138_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC138_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC138_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC138_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC138_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC138_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC138_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC138_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC138_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC138_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG138_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG138_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG138_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG138_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func138_in_sel(&self) -> FUNC138_IN_SEL_R { + FUNC138_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func138_in_inv_sel(&self) -> FUNC138_IN_INV_SEL_R { + FUNC138_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig138_in_sel(&self) -> SIG138_IN_SEL_R { + SIG138_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC138_IN_SEL_CFG") + .field( + "func138_in_sel", + &format_args!("{}", self.func138_in_sel().bits()), + ) + .field( + "func138_in_inv_sel", + &format_args!("{}", self.func138_in_inv_sel().bit()), + ) + .field( + "sig138_in_sel", + &format_args!("{}", self.sig138_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func138_in_sel(&mut self) -> FUNC138_IN_SEL_W { + FUNC138_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func138_in_inv_sel(&mut self) -> FUNC138_IN_INV_SEL_W { + FUNC138_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig138_in_sel(&mut self) -> SIG138_IN_SEL_W { + SIG138_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func138_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func138_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC138_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC138_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func138_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC138_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func138_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC138_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC138_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC138_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func139_in_sel_cfg.rs b/esp32p4/src/gpio/func139_in_sel_cfg.rs new file mode 100644 index 0000000000..b44460356c --- /dev/null +++ b/esp32p4/src/gpio/func139_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC139_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC139_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC139_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC139_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC139_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC139_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC139_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC139_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC139_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC139_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG139_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG139_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG139_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG139_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func139_in_sel(&self) -> FUNC139_IN_SEL_R { + FUNC139_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func139_in_inv_sel(&self) -> FUNC139_IN_INV_SEL_R { + FUNC139_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig139_in_sel(&self) -> SIG139_IN_SEL_R { + SIG139_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC139_IN_SEL_CFG") + .field( + "func139_in_sel", + &format_args!("{}", self.func139_in_sel().bits()), + ) + .field( + "func139_in_inv_sel", + &format_args!("{}", self.func139_in_inv_sel().bit()), + ) + .field( + "sig139_in_sel", + &format_args!("{}", self.sig139_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func139_in_sel(&mut self) -> FUNC139_IN_SEL_W { + FUNC139_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func139_in_inv_sel(&mut self) -> FUNC139_IN_INV_SEL_W { + FUNC139_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig139_in_sel(&mut self) -> SIG139_IN_SEL_W { + SIG139_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func139_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func139_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC139_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC139_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func139_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC139_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func139_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC139_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC139_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC139_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func13_in_sel_cfg.rs b/esp32p4/src/gpio/func13_in_sel_cfg.rs new file mode 100644 index 0000000000..152e862be4 --- /dev/null +++ b/esp32p4/src/gpio/func13_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC13_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC13_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC13_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC13_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC13_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC13_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC13_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC13_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC13_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC13_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG13_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG13_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG13_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG13_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func13_in_sel(&self) -> FUNC13_IN_SEL_R { + FUNC13_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func13_in_inv_sel(&self) -> FUNC13_IN_INV_SEL_R { + FUNC13_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig13_in_sel(&self) -> SIG13_IN_SEL_R { + SIG13_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC13_IN_SEL_CFG") + .field( + "func13_in_sel", + &format_args!("{}", self.func13_in_sel().bits()), + ) + .field( + "func13_in_inv_sel", + &format_args!("{}", self.func13_in_inv_sel().bit()), + ) + .field( + "sig13_in_sel", + &format_args!("{}", self.sig13_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func13_in_sel(&mut self) -> FUNC13_IN_SEL_W { + FUNC13_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func13_in_inv_sel(&mut self) -> FUNC13_IN_INV_SEL_W { + FUNC13_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig13_in_sel(&mut self) -> SIG13_IN_SEL_W { + SIG13_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func13_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func13_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC13_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC13_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func13_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC13_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func13_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC13_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC13_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC13_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func140_in_sel_cfg.rs b/esp32p4/src/gpio/func140_in_sel_cfg.rs new file mode 100644 index 0000000000..2e9221ca01 --- /dev/null +++ b/esp32p4/src/gpio/func140_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC140_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC140_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC140_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC140_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC140_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC140_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC140_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC140_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC140_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC140_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG140_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG140_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG140_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG140_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func140_in_sel(&self) -> FUNC140_IN_SEL_R { + FUNC140_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func140_in_inv_sel(&self) -> FUNC140_IN_INV_SEL_R { + FUNC140_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig140_in_sel(&self) -> SIG140_IN_SEL_R { + SIG140_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC140_IN_SEL_CFG") + .field( + "func140_in_sel", + &format_args!("{}", self.func140_in_sel().bits()), + ) + .field( + "func140_in_inv_sel", + &format_args!("{}", self.func140_in_inv_sel().bit()), + ) + .field( + "sig140_in_sel", + &format_args!("{}", self.sig140_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func140_in_sel(&mut self) -> FUNC140_IN_SEL_W { + FUNC140_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func140_in_inv_sel(&mut self) -> FUNC140_IN_INV_SEL_W { + FUNC140_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig140_in_sel(&mut self) -> SIG140_IN_SEL_W { + SIG140_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func140_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func140_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC140_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC140_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func140_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC140_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func140_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC140_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC140_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC140_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func141_in_sel_cfg.rs b/esp32p4/src/gpio/func141_in_sel_cfg.rs new file mode 100644 index 0000000000..a0a49fc633 --- /dev/null +++ b/esp32p4/src/gpio/func141_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC141_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC141_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC141_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC141_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC141_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC141_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC141_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC141_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC141_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC141_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG141_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG141_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG141_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG141_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func141_in_sel(&self) -> FUNC141_IN_SEL_R { + FUNC141_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func141_in_inv_sel(&self) -> FUNC141_IN_INV_SEL_R { + FUNC141_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig141_in_sel(&self) -> SIG141_IN_SEL_R { + SIG141_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC141_IN_SEL_CFG") + .field( + "func141_in_sel", + &format_args!("{}", self.func141_in_sel().bits()), + ) + .field( + "func141_in_inv_sel", + &format_args!("{}", self.func141_in_inv_sel().bit()), + ) + .field( + "sig141_in_sel", + &format_args!("{}", self.sig141_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func141_in_sel(&mut self) -> FUNC141_IN_SEL_W { + FUNC141_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func141_in_inv_sel(&mut self) -> FUNC141_IN_INV_SEL_W { + FUNC141_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig141_in_sel(&mut self) -> SIG141_IN_SEL_W { + SIG141_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func141_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func141_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC141_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC141_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func141_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC141_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func141_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC141_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC141_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC141_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func142_in_sel_cfg.rs b/esp32p4/src/gpio/func142_in_sel_cfg.rs new file mode 100644 index 0000000000..8c2cbad1ca --- /dev/null +++ b/esp32p4/src/gpio/func142_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC142_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC142_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC142_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC142_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC142_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC142_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC142_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC142_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC142_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC142_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG142_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG142_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG142_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG142_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func142_in_sel(&self) -> FUNC142_IN_SEL_R { + FUNC142_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func142_in_inv_sel(&self) -> FUNC142_IN_INV_SEL_R { + FUNC142_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig142_in_sel(&self) -> SIG142_IN_SEL_R { + SIG142_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC142_IN_SEL_CFG") + .field( + "func142_in_sel", + &format_args!("{}", self.func142_in_sel().bits()), + ) + .field( + "func142_in_inv_sel", + &format_args!("{}", self.func142_in_inv_sel().bit()), + ) + .field( + "sig142_in_sel", + &format_args!("{}", self.sig142_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func142_in_sel(&mut self) -> FUNC142_IN_SEL_W { + FUNC142_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func142_in_inv_sel(&mut self) -> FUNC142_IN_INV_SEL_W { + FUNC142_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig142_in_sel(&mut self) -> SIG142_IN_SEL_W { + SIG142_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func142_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func142_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC142_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC142_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func142_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC142_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func142_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC142_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC142_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC142_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func143_in_sel_cfg.rs b/esp32p4/src/gpio/func143_in_sel_cfg.rs new file mode 100644 index 0000000000..edba3478ea --- /dev/null +++ b/esp32p4/src/gpio/func143_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC143_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC143_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC143_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC143_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC143_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC143_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC143_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC143_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC143_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC143_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG143_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG143_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG143_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG143_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func143_in_sel(&self) -> FUNC143_IN_SEL_R { + FUNC143_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func143_in_inv_sel(&self) -> FUNC143_IN_INV_SEL_R { + FUNC143_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig143_in_sel(&self) -> SIG143_IN_SEL_R { + SIG143_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC143_IN_SEL_CFG") + .field( + "func143_in_sel", + &format_args!("{}", self.func143_in_sel().bits()), + ) + .field( + "func143_in_inv_sel", + &format_args!("{}", self.func143_in_inv_sel().bit()), + ) + .field( + "sig143_in_sel", + &format_args!("{}", self.sig143_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func143_in_sel(&mut self) -> FUNC143_IN_SEL_W { + FUNC143_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func143_in_inv_sel(&mut self) -> FUNC143_IN_INV_SEL_W { + FUNC143_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig143_in_sel(&mut self) -> SIG143_IN_SEL_W { + SIG143_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func143_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func143_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC143_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC143_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func143_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC143_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func143_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC143_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC143_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC143_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func144_in_sel_cfg.rs b/esp32p4/src/gpio/func144_in_sel_cfg.rs new file mode 100644 index 0000000000..07612e1344 --- /dev/null +++ b/esp32p4/src/gpio/func144_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC144_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC144_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC144_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC144_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC144_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC144_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC144_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC144_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC144_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC144_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG144_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG144_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG144_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG144_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func144_in_sel(&self) -> FUNC144_IN_SEL_R { + FUNC144_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func144_in_inv_sel(&self) -> FUNC144_IN_INV_SEL_R { + FUNC144_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig144_in_sel(&self) -> SIG144_IN_SEL_R { + SIG144_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC144_IN_SEL_CFG") + .field( + "func144_in_sel", + &format_args!("{}", self.func144_in_sel().bits()), + ) + .field( + "func144_in_inv_sel", + &format_args!("{}", self.func144_in_inv_sel().bit()), + ) + .field( + "sig144_in_sel", + &format_args!("{}", self.sig144_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func144_in_sel(&mut self) -> FUNC144_IN_SEL_W { + FUNC144_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func144_in_inv_sel(&mut self) -> FUNC144_IN_INV_SEL_W { + FUNC144_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig144_in_sel(&mut self) -> SIG144_IN_SEL_W { + SIG144_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func144_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func144_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC144_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC144_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func144_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC144_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func144_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC144_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC144_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC144_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func145_in_sel_cfg.rs b/esp32p4/src/gpio/func145_in_sel_cfg.rs new file mode 100644 index 0000000000..942443097c --- /dev/null +++ b/esp32p4/src/gpio/func145_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC145_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC145_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC145_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC145_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC145_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC145_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC145_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC145_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC145_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC145_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG145_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG145_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG145_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG145_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func145_in_sel(&self) -> FUNC145_IN_SEL_R { + FUNC145_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func145_in_inv_sel(&self) -> FUNC145_IN_INV_SEL_R { + FUNC145_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig145_in_sel(&self) -> SIG145_IN_SEL_R { + SIG145_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC145_IN_SEL_CFG") + .field( + "func145_in_sel", + &format_args!("{}", self.func145_in_sel().bits()), + ) + .field( + "func145_in_inv_sel", + &format_args!("{}", self.func145_in_inv_sel().bit()), + ) + .field( + "sig145_in_sel", + &format_args!("{}", self.sig145_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func145_in_sel(&mut self) -> FUNC145_IN_SEL_W { + FUNC145_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func145_in_inv_sel(&mut self) -> FUNC145_IN_INV_SEL_W { + FUNC145_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig145_in_sel(&mut self) -> SIG145_IN_SEL_W { + SIG145_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func145_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func145_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC145_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC145_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func145_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC145_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func145_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC145_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC145_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC145_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func146_in_sel_cfg.rs b/esp32p4/src/gpio/func146_in_sel_cfg.rs new file mode 100644 index 0000000000..f2aca10803 --- /dev/null +++ b/esp32p4/src/gpio/func146_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC146_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC146_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC146_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC146_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC146_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC146_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC146_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC146_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC146_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC146_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG146_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG146_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG146_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG146_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func146_in_sel(&self) -> FUNC146_IN_SEL_R { + FUNC146_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func146_in_inv_sel(&self) -> FUNC146_IN_INV_SEL_R { + FUNC146_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig146_in_sel(&self) -> SIG146_IN_SEL_R { + SIG146_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC146_IN_SEL_CFG") + .field( + "func146_in_sel", + &format_args!("{}", self.func146_in_sel().bits()), + ) + .field( + "func146_in_inv_sel", + &format_args!("{}", self.func146_in_inv_sel().bit()), + ) + .field( + "sig146_in_sel", + &format_args!("{}", self.sig146_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func146_in_sel(&mut self) -> FUNC146_IN_SEL_W { + FUNC146_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func146_in_inv_sel(&mut self) -> FUNC146_IN_INV_SEL_W { + FUNC146_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig146_in_sel(&mut self) -> SIG146_IN_SEL_W { + SIG146_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func146_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func146_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC146_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC146_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func146_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC146_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func146_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC146_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC146_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC146_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func147_in_sel_cfg.rs b/esp32p4/src/gpio/func147_in_sel_cfg.rs new file mode 100644 index 0000000000..c2d0bb700a --- /dev/null +++ b/esp32p4/src/gpio/func147_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC147_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC147_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC147_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC147_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC147_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC147_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC147_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC147_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC147_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC147_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG147_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG147_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG147_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG147_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func147_in_sel(&self) -> FUNC147_IN_SEL_R { + FUNC147_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func147_in_inv_sel(&self) -> FUNC147_IN_INV_SEL_R { + FUNC147_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig147_in_sel(&self) -> SIG147_IN_SEL_R { + SIG147_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC147_IN_SEL_CFG") + .field( + "func147_in_sel", + &format_args!("{}", self.func147_in_sel().bits()), + ) + .field( + "func147_in_inv_sel", + &format_args!("{}", self.func147_in_inv_sel().bit()), + ) + .field( + "sig147_in_sel", + &format_args!("{}", self.sig147_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func147_in_sel(&mut self) -> FUNC147_IN_SEL_W { + FUNC147_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func147_in_inv_sel(&mut self) -> FUNC147_IN_INV_SEL_W { + FUNC147_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig147_in_sel(&mut self) -> SIG147_IN_SEL_W { + SIG147_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func147_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func147_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC147_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC147_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func147_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC147_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func147_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC147_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC147_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC147_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func148_in_sel_cfg.rs b/esp32p4/src/gpio/func148_in_sel_cfg.rs new file mode 100644 index 0000000000..07dc52af46 --- /dev/null +++ b/esp32p4/src/gpio/func148_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC148_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC148_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC148_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC148_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC148_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC148_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC148_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC148_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC148_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC148_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG148_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG148_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG148_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG148_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func148_in_sel(&self) -> FUNC148_IN_SEL_R { + FUNC148_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func148_in_inv_sel(&self) -> FUNC148_IN_INV_SEL_R { + FUNC148_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig148_in_sel(&self) -> SIG148_IN_SEL_R { + SIG148_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC148_IN_SEL_CFG") + .field( + "func148_in_sel", + &format_args!("{}", self.func148_in_sel().bits()), + ) + .field( + "func148_in_inv_sel", + &format_args!("{}", self.func148_in_inv_sel().bit()), + ) + .field( + "sig148_in_sel", + &format_args!("{}", self.sig148_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func148_in_sel(&mut self) -> FUNC148_IN_SEL_W { + FUNC148_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func148_in_inv_sel(&mut self) -> FUNC148_IN_INV_SEL_W { + FUNC148_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig148_in_sel(&mut self) -> SIG148_IN_SEL_W { + SIG148_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func148_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func148_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC148_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC148_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func148_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC148_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func148_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC148_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC148_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC148_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func149_in_sel_cfg.rs b/esp32p4/src/gpio/func149_in_sel_cfg.rs new file mode 100644 index 0000000000..2b200fcf05 --- /dev/null +++ b/esp32p4/src/gpio/func149_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC149_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC149_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC149_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC149_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC149_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC149_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC149_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC149_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC149_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC149_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG149_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG149_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG149_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG149_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func149_in_sel(&self) -> FUNC149_IN_SEL_R { + FUNC149_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func149_in_inv_sel(&self) -> FUNC149_IN_INV_SEL_R { + FUNC149_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig149_in_sel(&self) -> SIG149_IN_SEL_R { + SIG149_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC149_IN_SEL_CFG") + .field( + "func149_in_sel", + &format_args!("{}", self.func149_in_sel().bits()), + ) + .field( + "func149_in_inv_sel", + &format_args!("{}", self.func149_in_inv_sel().bit()), + ) + .field( + "sig149_in_sel", + &format_args!("{}", self.sig149_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func149_in_sel(&mut self) -> FUNC149_IN_SEL_W { + FUNC149_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func149_in_inv_sel(&mut self) -> FUNC149_IN_INV_SEL_W { + FUNC149_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig149_in_sel(&mut self) -> SIG149_IN_SEL_W { + SIG149_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func149_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func149_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC149_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC149_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func149_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC149_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func149_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC149_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC149_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC149_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func14_in_sel_cfg.rs b/esp32p4/src/gpio/func14_in_sel_cfg.rs new file mode 100644 index 0000000000..577e146804 --- /dev/null +++ b/esp32p4/src/gpio/func14_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC14_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC14_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC14_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC14_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC14_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC14_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC14_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC14_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC14_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC14_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG14_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG14_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG14_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG14_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func14_in_sel(&self) -> FUNC14_IN_SEL_R { + FUNC14_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func14_in_inv_sel(&self) -> FUNC14_IN_INV_SEL_R { + FUNC14_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig14_in_sel(&self) -> SIG14_IN_SEL_R { + SIG14_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC14_IN_SEL_CFG") + .field( + "func14_in_sel", + &format_args!("{}", self.func14_in_sel().bits()), + ) + .field( + "func14_in_inv_sel", + &format_args!("{}", self.func14_in_inv_sel().bit()), + ) + .field( + "sig14_in_sel", + &format_args!("{}", self.sig14_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func14_in_sel(&mut self) -> FUNC14_IN_SEL_W { + FUNC14_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func14_in_inv_sel(&mut self) -> FUNC14_IN_INV_SEL_W { + FUNC14_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig14_in_sel(&mut self) -> SIG14_IN_SEL_W { + SIG14_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func14_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func14_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC14_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC14_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func14_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC14_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func14_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC14_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC14_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC14_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func150_in_sel_cfg.rs b/esp32p4/src/gpio/func150_in_sel_cfg.rs new file mode 100644 index 0000000000..c57708e0b6 --- /dev/null +++ b/esp32p4/src/gpio/func150_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC150_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC150_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC150_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC150_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC150_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC150_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC150_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC150_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC150_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC150_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG150_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG150_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG150_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG150_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func150_in_sel(&self) -> FUNC150_IN_SEL_R { + FUNC150_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func150_in_inv_sel(&self) -> FUNC150_IN_INV_SEL_R { + FUNC150_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig150_in_sel(&self) -> SIG150_IN_SEL_R { + SIG150_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC150_IN_SEL_CFG") + .field( + "func150_in_sel", + &format_args!("{}", self.func150_in_sel().bits()), + ) + .field( + "func150_in_inv_sel", + &format_args!("{}", self.func150_in_inv_sel().bit()), + ) + .field( + "sig150_in_sel", + &format_args!("{}", self.sig150_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func150_in_sel(&mut self) -> FUNC150_IN_SEL_W { + FUNC150_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func150_in_inv_sel(&mut self) -> FUNC150_IN_INV_SEL_W { + FUNC150_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig150_in_sel(&mut self) -> SIG150_IN_SEL_W { + SIG150_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func150_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func150_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC150_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC150_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func150_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC150_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func150_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC150_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC150_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC150_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func151_in_sel_cfg.rs b/esp32p4/src/gpio/func151_in_sel_cfg.rs new file mode 100644 index 0000000000..7cb95915e1 --- /dev/null +++ b/esp32p4/src/gpio/func151_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC151_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC151_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC151_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC151_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC151_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC151_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC151_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC151_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC151_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC151_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG151_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG151_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG151_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG151_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func151_in_sel(&self) -> FUNC151_IN_SEL_R { + FUNC151_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func151_in_inv_sel(&self) -> FUNC151_IN_INV_SEL_R { + FUNC151_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig151_in_sel(&self) -> SIG151_IN_SEL_R { + SIG151_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC151_IN_SEL_CFG") + .field( + "func151_in_sel", + &format_args!("{}", self.func151_in_sel().bits()), + ) + .field( + "func151_in_inv_sel", + &format_args!("{}", self.func151_in_inv_sel().bit()), + ) + .field( + "sig151_in_sel", + &format_args!("{}", self.sig151_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func151_in_sel(&mut self) -> FUNC151_IN_SEL_W { + FUNC151_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func151_in_inv_sel(&mut self) -> FUNC151_IN_INV_SEL_W { + FUNC151_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig151_in_sel(&mut self) -> SIG151_IN_SEL_W { + SIG151_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func151_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func151_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC151_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC151_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func151_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC151_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func151_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC151_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC151_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC151_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func152_in_sel_cfg.rs b/esp32p4/src/gpio/func152_in_sel_cfg.rs new file mode 100644 index 0000000000..ab8e0efd1f --- /dev/null +++ b/esp32p4/src/gpio/func152_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC152_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC152_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC152_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC152_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC152_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC152_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC152_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC152_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC152_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC152_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG152_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG152_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG152_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG152_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func152_in_sel(&self) -> FUNC152_IN_SEL_R { + FUNC152_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func152_in_inv_sel(&self) -> FUNC152_IN_INV_SEL_R { + FUNC152_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig152_in_sel(&self) -> SIG152_IN_SEL_R { + SIG152_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC152_IN_SEL_CFG") + .field( + "func152_in_sel", + &format_args!("{}", self.func152_in_sel().bits()), + ) + .field( + "func152_in_inv_sel", + &format_args!("{}", self.func152_in_inv_sel().bit()), + ) + .field( + "sig152_in_sel", + &format_args!("{}", self.sig152_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func152_in_sel(&mut self) -> FUNC152_IN_SEL_W { + FUNC152_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func152_in_inv_sel(&mut self) -> FUNC152_IN_INV_SEL_W { + FUNC152_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig152_in_sel(&mut self) -> SIG152_IN_SEL_W { + SIG152_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func152_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func152_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC152_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC152_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func152_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC152_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func152_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC152_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC152_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC152_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func153_in_sel_cfg.rs b/esp32p4/src/gpio/func153_in_sel_cfg.rs new file mode 100644 index 0000000000..37704d9f50 --- /dev/null +++ b/esp32p4/src/gpio/func153_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC153_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC153_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC153_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC153_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC153_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC153_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC153_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC153_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC153_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC153_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG153_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG153_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG153_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG153_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func153_in_sel(&self) -> FUNC153_IN_SEL_R { + FUNC153_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func153_in_inv_sel(&self) -> FUNC153_IN_INV_SEL_R { + FUNC153_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig153_in_sel(&self) -> SIG153_IN_SEL_R { + SIG153_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC153_IN_SEL_CFG") + .field( + "func153_in_sel", + &format_args!("{}", self.func153_in_sel().bits()), + ) + .field( + "func153_in_inv_sel", + &format_args!("{}", self.func153_in_inv_sel().bit()), + ) + .field( + "sig153_in_sel", + &format_args!("{}", self.sig153_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func153_in_sel(&mut self) -> FUNC153_IN_SEL_W { + FUNC153_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func153_in_inv_sel(&mut self) -> FUNC153_IN_INV_SEL_W { + FUNC153_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig153_in_sel(&mut self) -> SIG153_IN_SEL_W { + SIG153_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func153_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func153_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC153_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC153_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func153_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC153_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func153_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC153_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC153_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC153_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func154_in_sel_cfg.rs b/esp32p4/src/gpio/func154_in_sel_cfg.rs new file mode 100644 index 0000000000..c182246a12 --- /dev/null +++ b/esp32p4/src/gpio/func154_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC154_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC154_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC154_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC154_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC154_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC154_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC154_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC154_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC154_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC154_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG154_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG154_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG154_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG154_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func154_in_sel(&self) -> FUNC154_IN_SEL_R { + FUNC154_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func154_in_inv_sel(&self) -> FUNC154_IN_INV_SEL_R { + FUNC154_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig154_in_sel(&self) -> SIG154_IN_SEL_R { + SIG154_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC154_IN_SEL_CFG") + .field( + "func154_in_sel", + &format_args!("{}", self.func154_in_sel().bits()), + ) + .field( + "func154_in_inv_sel", + &format_args!("{}", self.func154_in_inv_sel().bit()), + ) + .field( + "sig154_in_sel", + &format_args!("{}", self.sig154_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func154_in_sel(&mut self) -> FUNC154_IN_SEL_W { + FUNC154_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func154_in_inv_sel(&mut self) -> FUNC154_IN_INV_SEL_W { + FUNC154_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig154_in_sel(&mut self) -> SIG154_IN_SEL_W { + SIG154_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func154_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func154_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC154_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC154_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func154_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC154_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func154_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC154_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC154_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC154_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func155_in_sel_cfg.rs b/esp32p4/src/gpio/func155_in_sel_cfg.rs new file mode 100644 index 0000000000..fe78d0f4d0 --- /dev/null +++ b/esp32p4/src/gpio/func155_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC155_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC155_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC155_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC155_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC155_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC155_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC155_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC155_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC155_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC155_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG155_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG155_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG155_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG155_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func155_in_sel(&self) -> FUNC155_IN_SEL_R { + FUNC155_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func155_in_inv_sel(&self) -> FUNC155_IN_INV_SEL_R { + FUNC155_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig155_in_sel(&self) -> SIG155_IN_SEL_R { + SIG155_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC155_IN_SEL_CFG") + .field( + "func155_in_sel", + &format_args!("{}", self.func155_in_sel().bits()), + ) + .field( + "func155_in_inv_sel", + &format_args!("{}", self.func155_in_inv_sel().bit()), + ) + .field( + "sig155_in_sel", + &format_args!("{}", self.sig155_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func155_in_sel(&mut self) -> FUNC155_IN_SEL_W { + FUNC155_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func155_in_inv_sel(&mut self) -> FUNC155_IN_INV_SEL_W { + FUNC155_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig155_in_sel(&mut self) -> SIG155_IN_SEL_W { + SIG155_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func155_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func155_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC155_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC155_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func155_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC155_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func155_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC155_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC155_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC155_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func156_in_sel_cfg.rs b/esp32p4/src/gpio/func156_in_sel_cfg.rs new file mode 100644 index 0000000000..93f674b329 --- /dev/null +++ b/esp32p4/src/gpio/func156_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC156_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC156_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC156_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC156_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC156_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC156_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC156_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC156_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC156_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC156_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG156_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG156_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG156_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG156_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func156_in_sel(&self) -> FUNC156_IN_SEL_R { + FUNC156_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func156_in_inv_sel(&self) -> FUNC156_IN_INV_SEL_R { + FUNC156_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig156_in_sel(&self) -> SIG156_IN_SEL_R { + SIG156_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC156_IN_SEL_CFG") + .field( + "func156_in_sel", + &format_args!("{}", self.func156_in_sel().bits()), + ) + .field( + "func156_in_inv_sel", + &format_args!("{}", self.func156_in_inv_sel().bit()), + ) + .field( + "sig156_in_sel", + &format_args!("{}", self.sig156_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func156_in_sel(&mut self) -> FUNC156_IN_SEL_W { + FUNC156_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func156_in_inv_sel(&mut self) -> FUNC156_IN_INV_SEL_W { + FUNC156_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig156_in_sel(&mut self) -> SIG156_IN_SEL_W { + SIG156_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func156_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func156_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC156_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC156_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func156_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC156_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func156_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC156_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC156_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC156_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func158_in_sel_cfg.rs b/esp32p4/src/gpio/func158_in_sel_cfg.rs new file mode 100644 index 0000000000..af8ecb91a2 --- /dev/null +++ b/esp32p4/src/gpio/func158_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC158_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC158_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC158_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC158_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC158_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC158_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC158_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC158_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC158_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC158_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG158_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG158_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG158_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG158_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func158_in_sel(&self) -> FUNC158_IN_SEL_R { + FUNC158_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func158_in_inv_sel(&self) -> FUNC158_IN_INV_SEL_R { + FUNC158_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig158_in_sel(&self) -> SIG158_IN_SEL_R { + SIG158_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC158_IN_SEL_CFG") + .field( + "func158_in_sel", + &format_args!("{}", self.func158_in_sel().bits()), + ) + .field( + "func158_in_inv_sel", + &format_args!("{}", self.func158_in_inv_sel().bit()), + ) + .field( + "sig158_in_sel", + &format_args!("{}", self.sig158_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func158_in_sel(&mut self) -> FUNC158_IN_SEL_W { + FUNC158_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func158_in_inv_sel(&mut self) -> FUNC158_IN_INV_SEL_W { + FUNC158_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig158_in_sel(&mut self) -> SIG158_IN_SEL_W { + SIG158_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func158_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func158_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC158_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC158_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func158_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC158_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func158_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC158_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC158_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC158_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func159_in_sel_cfg.rs b/esp32p4/src/gpio/func159_in_sel_cfg.rs new file mode 100644 index 0000000000..51c381ca48 --- /dev/null +++ b/esp32p4/src/gpio/func159_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC159_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC159_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC159_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC159_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC159_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC159_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC159_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC159_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC159_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC159_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG159_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG159_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG159_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG159_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func159_in_sel(&self) -> FUNC159_IN_SEL_R { + FUNC159_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func159_in_inv_sel(&self) -> FUNC159_IN_INV_SEL_R { + FUNC159_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig159_in_sel(&self) -> SIG159_IN_SEL_R { + SIG159_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC159_IN_SEL_CFG") + .field( + "func159_in_sel", + &format_args!("{}", self.func159_in_sel().bits()), + ) + .field( + "func159_in_inv_sel", + &format_args!("{}", self.func159_in_inv_sel().bit()), + ) + .field( + "sig159_in_sel", + &format_args!("{}", self.sig159_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func159_in_sel(&mut self) -> FUNC159_IN_SEL_W { + FUNC159_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func159_in_inv_sel(&mut self) -> FUNC159_IN_INV_SEL_W { + FUNC159_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig159_in_sel(&mut self) -> SIG159_IN_SEL_W { + SIG159_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func159_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func159_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC159_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC159_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func159_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC159_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func159_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC159_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC159_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC159_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func15_in_sel_cfg.rs b/esp32p4/src/gpio/func15_in_sel_cfg.rs new file mode 100644 index 0000000000..e2693ec86f --- /dev/null +++ b/esp32p4/src/gpio/func15_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC15_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC15_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC15_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC15_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC15_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC15_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC15_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC15_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC15_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC15_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG15_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG15_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG15_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG15_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func15_in_sel(&self) -> FUNC15_IN_SEL_R { + FUNC15_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func15_in_inv_sel(&self) -> FUNC15_IN_INV_SEL_R { + FUNC15_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig15_in_sel(&self) -> SIG15_IN_SEL_R { + SIG15_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC15_IN_SEL_CFG") + .field( + "func15_in_sel", + &format_args!("{}", self.func15_in_sel().bits()), + ) + .field( + "func15_in_inv_sel", + &format_args!("{}", self.func15_in_inv_sel().bit()), + ) + .field( + "sig15_in_sel", + &format_args!("{}", self.sig15_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func15_in_sel(&mut self) -> FUNC15_IN_SEL_W { + FUNC15_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func15_in_inv_sel(&mut self) -> FUNC15_IN_INV_SEL_W { + FUNC15_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig15_in_sel(&mut self) -> SIG15_IN_SEL_W { + SIG15_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func15_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func15_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC15_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC15_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func15_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC15_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func15_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC15_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC15_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC15_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func160_in_sel_cfg.rs b/esp32p4/src/gpio/func160_in_sel_cfg.rs new file mode 100644 index 0000000000..a857e695e2 --- /dev/null +++ b/esp32p4/src/gpio/func160_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC160_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC160_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC160_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC160_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC160_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC160_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC160_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC160_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC160_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC160_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG160_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG160_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG160_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG160_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func160_in_sel(&self) -> FUNC160_IN_SEL_R { + FUNC160_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func160_in_inv_sel(&self) -> FUNC160_IN_INV_SEL_R { + FUNC160_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig160_in_sel(&self) -> SIG160_IN_SEL_R { + SIG160_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC160_IN_SEL_CFG") + .field( + "func160_in_sel", + &format_args!("{}", self.func160_in_sel().bits()), + ) + .field( + "func160_in_inv_sel", + &format_args!("{}", self.func160_in_inv_sel().bit()), + ) + .field( + "sig160_in_sel", + &format_args!("{}", self.sig160_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func160_in_sel(&mut self) -> FUNC160_IN_SEL_W { + FUNC160_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func160_in_inv_sel(&mut self) -> FUNC160_IN_INV_SEL_W { + FUNC160_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig160_in_sel(&mut self) -> SIG160_IN_SEL_W { + SIG160_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func160_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func160_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC160_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC160_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func160_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC160_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func160_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC160_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC160_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC160_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func161_in_sel_cfg.rs b/esp32p4/src/gpio/func161_in_sel_cfg.rs new file mode 100644 index 0000000000..fafa41aa67 --- /dev/null +++ b/esp32p4/src/gpio/func161_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC161_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC161_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC161_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC161_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC161_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC161_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC161_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC161_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC161_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC161_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG161_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG161_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG161_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG161_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func161_in_sel(&self) -> FUNC161_IN_SEL_R { + FUNC161_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func161_in_inv_sel(&self) -> FUNC161_IN_INV_SEL_R { + FUNC161_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig161_in_sel(&self) -> SIG161_IN_SEL_R { + SIG161_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC161_IN_SEL_CFG") + .field( + "func161_in_sel", + &format_args!("{}", self.func161_in_sel().bits()), + ) + .field( + "func161_in_inv_sel", + &format_args!("{}", self.func161_in_inv_sel().bit()), + ) + .field( + "sig161_in_sel", + &format_args!("{}", self.sig161_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func161_in_sel(&mut self) -> FUNC161_IN_SEL_W { + FUNC161_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func161_in_inv_sel(&mut self) -> FUNC161_IN_INV_SEL_W { + FUNC161_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig161_in_sel(&mut self) -> SIG161_IN_SEL_W { + SIG161_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func161_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func161_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC161_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC161_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func161_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC161_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func161_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC161_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC161_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC161_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func162_in_sel_cfg.rs b/esp32p4/src/gpio/func162_in_sel_cfg.rs new file mode 100644 index 0000000000..b6702bc523 --- /dev/null +++ b/esp32p4/src/gpio/func162_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC162_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC162_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC162_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC162_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC162_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC162_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC162_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC162_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC162_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC162_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG162_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG162_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG162_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG162_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func162_in_sel(&self) -> FUNC162_IN_SEL_R { + FUNC162_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func162_in_inv_sel(&self) -> FUNC162_IN_INV_SEL_R { + FUNC162_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig162_in_sel(&self) -> SIG162_IN_SEL_R { + SIG162_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC162_IN_SEL_CFG") + .field( + "func162_in_sel", + &format_args!("{}", self.func162_in_sel().bits()), + ) + .field( + "func162_in_inv_sel", + &format_args!("{}", self.func162_in_inv_sel().bit()), + ) + .field( + "sig162_in_sel", + &format_args!("{}", self.sig162_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func162_in_sel(&mut self) -> FUNC162_IN_SEL_W { + FUNC162_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func162_in_inv_sel(&mut self) -> FUNC162_IN_INV_SEL_W { + FUNC162_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig162_in_sel(&mut self) -> SIG162_IN_SEL_W { + SIG162_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func162_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func162_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC162_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC162_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func162_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC162_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func162_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC162_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC162_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC162_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func163_in_sel_cfg.rs b/esp32p4/src/gpio/func163_in_sel_cfg.rs new file mode 100644 index 0000000000..dc373d8bc6 --- /dev/null +++ b/esp32p4/src/gpio/func163_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC163_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC163_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC163_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC163_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC163_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC163_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC163_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC163_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC163_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC163_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG163_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG163_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG163_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG163_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func163_in_sel(&self) -> FUNC163_IN_SEL_R { + FUNC163_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func163_in_inv_sel(&self) -> FUNC163_IN_INV_SEL_R { + FUNC163_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig163_in_sel(&self) -> SIG163_IN_SEL_R { + SIG163_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC163_IN_SEL_CFG") + .field( + "func163_in_sel", + &format_args!("{}", self.func163_in_sel().bits()), + ) + .field( + "func163_in_inv_sel", + &format_args!("{}", self.func163_in_inv_sel().bit()), + ) + .field( + "sig163_in_sel", + &format_args!("{}", self.sig163_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func163_in_sel(&mut self) -> FUNC163_IN_SEL_W { + FUNC163_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func163_in_inv_sel(&mut self) -> FUNC163_IN_INV_SEL_W { + FUNC163_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig163_in_sel(&mut self) -> SIG163_IN_SEL_W { + SIG163_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func163_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func163_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC163_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC163_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func163_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC163_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func163_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC163_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC163_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC163_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func164_in_sel_cfg.rs b/esp32p4/src/gpio/func164_in_sel_cfg.rs new file mode 100644 index 0000000000..ac5088ebea --- /dev/null +++ b/esp32p4/src/gpio/func164_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC164_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC164_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC164_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC164_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC164_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC164_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC164_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC164_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC164_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC164_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG164_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG164_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG164_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG164_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func164_in_sel(&self) -> FUNC164_IN_SEL_R { + FUNC164_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func164_in_inv_sel(&self) -> FUNC164_IN_INV_SEL_R { + FUNC164_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig164_in_sel(&self) -> SIG164_IN_SEL_R { + SIG164_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC164_IN_SEL_CFG") + .field( + "func164_in_sel", + &format_args!("{}", self.func164_in_sel().bits()), + ) + .field( + "func164_in_inv_sel", + &format_args!("{}", self.func164_in_inv_sel().bit()), + ) + .field( + "sig164_in_sel", + &format_args!("{}", self.sig164_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func164_in_sel(&mut self) -> FUNC164_IN_SEL_W { + FUNC164_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func164_in_inv_sel(&mut self) -> FUNC164_IN_INV_SEL_W { + FUNC164_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig164_in_sel(&mut self) -> SIG164_IN_SEL_W { + SIG164_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func164_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func164_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC164_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC164_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func164_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC164_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func164_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC164_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC164_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC164_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func165_in_sel_cfg.rs b/esp32p4/src/gpio/func165_in_sel_cfg.rs new file mode 100644 index 0000000000..2eb14278b8 --- /dev/null +++ b/esp32p4/src/gpio/func165_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC165_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC165_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC165_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC165_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC165_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC165_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC165_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC165_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC165_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC165_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG165_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG165_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG165_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG165_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func165_in_sel(&self) -> FUNC165_IN_SEL_R { + FUNC165_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func165_in_inv_sel(&self) -> FUNC165_IN_INV_SEL_R { + FUNC165_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig165_in_sel(&self) -> SIG165_IN_SEL_R { + SIG165_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC165_IN_SEL_CFG") + .field( + "func165_in_sel", + &format_args!("{}", self.func165_in_sel().bits()), + ) + .field( + "func165_in_inv_sel", + &format_args!("{}", self.func165_in_inv_sel().bit()), + ) + .field( + "sig165_in_sel", + &format_args!("{}", self.sig165_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func165_in_sel(&mut self) -> FUNC165_IN_SEL_W { + FUNC165_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func165_in_inv_sel(&mut self) -> FUNC165_IN_INV_SEL_W { + FUNC165_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig165_in_sel(&mut self) -> SIG165_IN_SEL_W { + SIG165_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func165_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func165_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC165_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC165_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func165_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC165_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func165_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC165_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC165_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC165_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func166_in_sel_cfg.rs b/esp32p4/src/gpio/func166_in_sel_cfg.rs new file mode 100644 index 0000000000..d66e4936f0 --- /dev/null +++ b/esp32p4/src/gpio/func166_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC166_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC166_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC166_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC166_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC166_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC166_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC166_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC166_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC166_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC166_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG166_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG166_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG166_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG166_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func166_in_sel(&self) -> FUNC166_IN_SEL_R { + FUNC166_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func166_in_inv_sel(&self) -> FUNC166_IN_INV_SEL_R { + FUNC166_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig166_in_sel(&self) -> SIG166_IN_SEL_R { + SIG166_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC166_IN_SEL_CFG") + .field( + "func166_in_sel", + &format_args!("{}", self.func166_in_sel().bits()), + ) + .field( + "func166_in_inv_sel", + &format_args!("{}", self.func166_in_inv_sel().bit()), + ) + .field( + "sig166_in_sel", + &format_args!("{}", self.sig166_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func166_in_sel(&mut self) -> FUNC166_IN_SEL_W { + FUNC166_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func166_in_inv_sel(&mut self) -> FUNC166_IN_INV_SEL_W { + FUNC166_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig166_in_sel(&mut self) -> SIG166_IN_SEL_W { + SIG166_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func166_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func166_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC166_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC166_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func166_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC166_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func166_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC166_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC166_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC166_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func167_in_sel_cfg.rs b/esp32p4/src/gpio/func167_in_sel_cfg.rs new file mode 100644 index 0000000000..3e912614df --- /dev/null +++ b/esp32p4/src/gpio/func167_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC167_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC167_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC167_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC167_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC167_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC167_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC167_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC167_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC167_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC167_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG167_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG167_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG167_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG167_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func167_in_sel(&self) -> FUNC167_IN_SEL_R { + FUNC167_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func167_in_inv_sel(&self) -> FUNC167_IN_INV_SEL_R { + FUNC167_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig167_in_sel(&self) -> SIG167_IN_SEL_R { + SIG167_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC167_IN_SEL_CFG") + .field( + "func167_in_sel", + &format_args!("{}", self.func167_in_sel().bits()), + ) + .field( + "func167_in_inv_sel", + &format_args!("{}", self.func167_in_inv_sel().bit()), + ) + .field( + "sig167_in_sel", + &format_args!("{}", self.sig167_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func167_in_sel(&mut self) -> FUNC167_IN_SEL_W { + FUNC167_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func167_in_inv_sel(&mut self) -> FUNC167_IN_INV_SEL_W { + FUNC167_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig167_in_sel(&mut self) -> SIG167_IN_SEL_W { + SIG167_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func167_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func167_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC167_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC167_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func167_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC167_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func167_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC167_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC167_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC167_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func168_in_sel_cfg.rs b/esp32p4/src/gpio/func168_in_sel_cfg.rs new file mode 100644 index 0000000000..e1d1097d0e --- /dev/null +++ b/esp32p4/src/gpio/func168_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC168_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC168_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC168_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC168_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC168_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC168_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC168_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC168_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC168_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC168_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG168_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG168_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG168_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG168_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func168_in_sel(&self) -> FUNC168_IN_SEL_R { + FUNC168_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func168_in_inv_sel(&self) -> FUNC168_IN_INV_SEL_R { + FUNC168_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig168_in_sel(&self) -> SIG168_IN_SEL_R { + SIG168_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC168_IN_SEL_CFG") + .field( + "func168_in_sel", + &format_args!("{}", self.func168_in_sel().bits()), + ) + .field( + "func168_in_inv_sel", + &format_args!("{}", self.func168_in_inv_sel().bit()), + ) + .field( + "sig168_in_sel", + &format_args!("{}", self.sig168_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func168_in_sel(&mut self) -> FUNC168_IN_SEL_W { + FUNC168_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func168_in_inv_sel(&mut self) -> FUNC168_IN_INV_SEL_W { + FUNC168_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig168_in_sel(&mut self) -> SIG168_IN_SEL_W { + SIG168_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func168_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func168_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC168_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC168_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func168_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC168_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func168_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC168_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC168_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC168_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func169_in_sel_cfg.rs b/esp32p4/src/gpio/func169_in_sel_cfg.rs new file mode 100644 index 0000000000..57f1b9aaf7 --- /dev/null +++ b/esp32p4/src/gpio/func169_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC169_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC169_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC169_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC169_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC169_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC169_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC169_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC169_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC169_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC169_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG169_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG169_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG169_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG169_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func169_in_sel(&self) -> FUNC169_IN_SEL_R { + FUNC169_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func169_in_inv_sel(&self) -> FUNC169_IN_INV_SEL_R { + FUNC169_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig169_in_sel(&self) -> SIG169_IN_SEL_R { + SIG169_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC169_IN_SEL_CFG") + .field( + "func169_in_sel", + &format_args!("{}", self.func169_in_sel().bits()), + ) + .field( + "func169_in_inv_sel", + &format_args!("{}", self.func169_in_inv_sel().bit()), + ) + .field( + "sig169_in_sel", + &format_args!("{}", self.sig169_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func169_in_sel(&mut self) -> FUNC169_IN_SEL_W { + FUNC169_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func169_in_inv_sel(&mut self) -> FUNC169_IN_INV_SEL_W { + FUNC169_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig169_in_sel(&mut self) -> SIG169_IN_SEL_W { + SIG169_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func169_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func169_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC169_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC169_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func169_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC169_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func169_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC169_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC169_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC169_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func16_in_sel_cfg.rs b/esp32p4/src/gpio/func16_in_sel_cfg.rs new file mode 100644 index 0000000000..c50e57ffb8 --- /dev/null +++ b/esp32p4/src/gpio/func16_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC16_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC16_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC16_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC16_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC16_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC16_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC16_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC16_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC16_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC16_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG16_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG16_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG16_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG16_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func16_in_sel(&self) -> FUNC16_IN_SEL_R { + FUNC16_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func16_in_inv_sel(&self) -> FUNC16_IN_INV_SEL_R { + FUNC16_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig16_in_sel(&self) -> SIG16_IN_SEL_R { + SIG16_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC16_IN_SEL_CFG") + .field( + "func16_in_sel", + &format_args!("{}", self.func16_in_sel().bits()), + ) + .field( + "func16_in_inv_sel", + &format_args!("{}", self.func16_in_inv_sel().bit()), + ) + .field( + "sig16_in_sel", + &format_args!("{}", self.sig16_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func16_in_sel(&mut self) -> FUNC16_IN_SEL_W { + FUNC16_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func16_in_inv_sel(&mut self) -> FUNC16_IN_INV_SEL_W { + FUNC16_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig16_in_sel(&mut self) -> SIG16_IN_SEL_W { + SIG16_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func16_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func16_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC16_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC16_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func16_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC16_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func16_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC16_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC16_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC16_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func170_in_sel_cfg.rs b/esp32p4/src/gpio/func170_in_sel_cfg.rs new file mode 100644 index 0000000000..e083246b65 --- /dev/null +++ b/esp32p4/src/gpio/func170_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC170_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC170_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC170_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC170_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC170_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC170_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC170_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC170_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC170_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC170_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG170_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG170_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG170_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG170_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func170_in_sel(&self) -> FUNC170_IN_SEL_R { + FUNC170_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func170_in_inv_sel(&self) -> FUNC170_IN_INV_SEL_R { + FUNC170_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig170_in_sel(&self) -> SIG170_IN_SEL_R { + SIG170_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC170_IN_SEL_CFG") + .field( + "func170_in_sel", + &format_args!("{}", self.func170_in_sel().bits()), + ) + .field( + "func170_in_inv_sel", + &format_args!("{}", self.func170_in_inv_sel().bit()), + ) + .field( + "sig170_in_sel", + &format_args!("{}", self.sig170_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func170_in_sel(&mut self) -> FUNC170_IN_SEL_W { + FUNC170_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func170_in_inv_sel(&mut self) -> FUNC170_IN_INV_SEL_W { + FUNC170_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig170_in_sel(&mut self) -> SIG170_IN_SEL_W { + SIG170_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func170_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func170_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC170_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC170_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func170_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC170_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func170_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC170_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC170_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC170_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func171_in_sel_cfg.rs b/esp32p4/src/gpio/func171_in_sel_cfg.rs new file mode 100644 index 0000000000..5e0fa9cdbf --- /dev/null +++ b/esp32p4/src/gpio/func171_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC171_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC171_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC171_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC171_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC171_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC171_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC171_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC171_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC171_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC171_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG171_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG171_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG171_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG171_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func171_in_sel(&self) -> FUNC171_IN_SEL_R { + FUNC171_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func171_in_inv_sel(&self) -> FUNC171_IN_INV_SEL_R { + FUNC171_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig171_in_sel(&self) -> SIG171_IN_SEL_R { + SIG171_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC171_IN_SEL_CFG") + .field( + "func171_in_sel", + &format_args!("{}", self.func171_in_sel().bits()), + ) + .field( + "func171_in_inv_sel", + &format_args!("{}", self.func171_in_inv_sel().bit()), + ) + .field( + "sig171_in_sel", + &format_args!("{}", self.sig171_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func171_in_sel(&mut self) -> FUNC171_IN_SEL_W { + FUNC171_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func171_in_inv_sel(&mut self) -> FUNC171_IN_INV_SEL_W { + FUNC171_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig171_in_sel(&mut self) -> SIG171_IN_SEL_W { + SIG171_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func171_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func171_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC171_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC171_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func171_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC171_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func171_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC171_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC171_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC171_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func172_in_sel_cfg.rs b/esp32p4/src/gpio/func172_in_sel_cfg.rs new file mode 100644 index 0000000000..43825a9344 --- /dev/null +++ b/esp32p4/src/gpio/func172_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC172_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC172_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC172_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC172_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC172_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC172_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC172_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC172_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC172_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC172_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG172_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG172_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG172_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG172_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func172_in_sel(&self) -> FUNC172_IN_SEL_R { + FUNC172_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func172_in_inv_sel(&self) -> FUNC172_IN_INV_SEL_R { + FUNC172_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig172_in_sel(&self) -> SIG172_IN_SEL_R { + SIG172_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC172_IN_SEL_CFG") + .field( + "func172_in_sel", + &format_args!("{}", self.func172_in_sel().bits()), + ) + .field( + "func172_in_inv_sel", + &format_args!("{}", self.func172_in_inv_sel().bit()), + ) + .field( + "sig172_in_sel", + &format_args!("{}", self.sig172_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func172_in_sel(&mut self) -> FUNC172_IN_SEL_W { + FUNC172_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func172_in_inv_sel(&mut self) -> FUNC172_IN_INV_SEL_W { + FUNC172_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig172_in_sel(&mut self) -> SIG172_IN_SEL_W { + SIG172_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func172_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func172_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC172_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC172_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func172_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC172_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func172_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC172_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC172_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC172_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func173_in_sel_cfg.rs b/esp32p4/src/gpio/func173_in_sel_cfg.rs new file mode 100644 index 0000000000..b87bb3d573 --- /dev/null +++ b/esp32p4/src/gpio/func173_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC173_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC173_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC173_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC173_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC173_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC173_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC173_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC173_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC173_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC173_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG173_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG173_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG173_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG173_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func173_in_sel(&self) -> FUNC173_IN_SEL_R { + FUNC173_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func173_in_inv_sel(&self) -> FUNC173_IN_INV_SEL_R { + FUNC173_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig173_in_sel(&self) -> SIG173_IN_SEL_R { + SIG173_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC173_IN_SEL_CFG") + .field( + "func173_in_sel", + &format_args!("{}", self.func173_in_sel().bits()), + ) + .field( + "func173_in_inv_sel", + &format_args!("{}", self.func173_in_inv_sel().bit()), + ) + .field( + "sig173_in_sel", + &format_args!("{}", self.sig173_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func173_in_sel(&mut self) -> FUNC173_IN_SEL_W { + FUNC173_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func173_in_inv_sel(&mut self) -> FUNC173_IN_INV_SEL_W { + FUNC173_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig173_in_sel(&mut self) -> SIG173_IN_SEL_W { + SIG173_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func173_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func173_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC173_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC173_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func173_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC173_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func173_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC173_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC173_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC173_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func174_in_sel_cfg.rs b/esp32p4/src/gpio/func174_in_sel_cfg.rs new file mode 100644 index 0000000000..424d893e6e --- /dev/null +++ b/esp32p4/src/gpio/func174_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC174_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC174_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC174_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC174_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC174_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC174_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC174_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC174_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC174_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC174_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG174_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG174_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG174_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG174_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func174_in_sel(&self) -> FUNC174_IN_SEL_R { + FUNC174_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func174_in_inv_sel(&self) -> FUNC174_IN_INV_SEL_R { + FUNC174_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig174_in_sel(&self) -> SIG174_IN_SEL_R { + SIG174_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC174_IN_SEL_CFG") + .field( + "func174_in_sel", + &format_args!("{}", self.func174_in_sel().bits()), + ) + .field( + "func174_in_inv_sel", + &format_args!("{}", self.func174_in_inv_sel().bit()), + ) + .field( + "sig174_in_sel", + &format_args!("{}", self.sig174_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func174_in_sel(&mut self) -> FUNC174_IN_SEL_W { + FUNC174_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func174_in_inv_sel(&mut self) -> FUNC174_IN_INV_SEL_W { + FUNC174_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig174_in_sel(&mut self) -> SIG174_IN_SEL_W { + SIG174_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func174_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func174_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC174_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC174_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func174_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC174_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func174_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC174_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC174_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC174_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func175_in_sel_cfg.rs b/esp32p4/src/gpio/func175_in_sel_cfg.rs new file mode 100644 index 0000000000..32b38f2f7e --- /dev/null +++ b/esp32p4/src/gpio/func175_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC175_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC175_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC175_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC175_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC175_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC175_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC175_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC175_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC175_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC175_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG175_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG175_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG175_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG175_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func175_in_sel(&self) -> FUNC175_IN_SEL_R { + FUNC175_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func175_in_inv_sel(&self) -> FUNC175_IN_INV_SEL_R { + FUNC175_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig175_in_sel(&self) -> SIG175_IN_SEL_R { + SIG175_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC175_IN_SEL_CFG") + .field( + "func175_in_sel", + &format_args!("{}", self.func175_in_sel().bits()), + ) + .field( + "func175_in_inv_sel", + &format_args!("{}", self.func175_in_inv_sel().bit()), + ) + .field( + "sig175_in_sel", + &format_args!("{}", self.sig175_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func175_in_sel(&mut self) -> FUNC175_IN_SEL_W { + FUNC175_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func175_in_inv_sel(&mut self) -> FUNC175_IN_INV_SEL_W { + FUNC175_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig175_in_sel(&mut self) -> SIG175_IN_SEL_W { + SIG175_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func175_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func175_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC175_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC175_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func175_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC175_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func175_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC175_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC175_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC175_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func176_in_sel_cfg.rs b/esp32p4/src/gpio/func176_in_sel_cfg.rs new file mode 100644 index 0000000000..2f5340929b --- /dev/null +++ b/esp32p4/src/gpio/func176_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC176_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC176_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC176_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC176_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC176_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC176_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC176_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC176_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC176_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC176_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG176_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG176_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG176_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG176_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func176_in_sel(&self) -> FUNC176_IN_SEL_R { + FUNC176_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func176_in_inv_sel(&self) -> FUNC176_IN_INV_SEL_R { + FUNC176_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig176_in_sel(&self) -> SIG176_IN_SEL_R { + SIG176_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC176_IN_SEL_CFG") + .field( + "func176_in_sel", + &format_args!("{}", self.func176_in_sel().bits()), + ) + .field( + "func176_in_inv_sel", + &format_args!("{}", self.func176_in_inv_sel().bit()), + ) + .field( + "sig176_in_sel", + &format_args!("{}", self.sig176_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func176_in_sel(&mut self) -> FUNC176_IN_SEL_W { + FUNC176_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func176_in_inv_sel(&mut self) -> FUNC176_IN_INV_SEL_W { + FUNC176_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig176_in_sel(&mut self) -> SIG176_IN_SEL_W { + SIG176_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func176_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func176_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC176_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC176_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func176_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC176_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func176_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC176_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC176_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC176_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func177_in_sel_cfg.rs b/esp32p4/src/gpio/func177_in_sel_cfg.rs new file mode 100644 index 0000000000..e459fd1661 --- /dev/null +++ b/esp32p4/src/gpio/func177_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC177_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC177_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC177_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC177_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC177_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC177_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC177_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC177_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC177_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC177_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG177_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG177_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG177_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG177_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func177_in_sel(&self) -> FUNC177_IN_SEL_R { + FUNC177_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func177_in_inv_sel(&self) -> FUNC177_IN_INV_SEL_R { + FUNC177_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig177_in_sel(&self) -> SIG177_IN_SEL_R { + SIG177_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC177_IN_SEL_CFG") + .field( + "func177_in_sel", + &format_args!("{}", self.func177_in_sel().bits()), + ) + .field( + "func177_in_inv_sel", + &format_args!("{}", self.func177_in_inv_sel().bit()), + ) + .field( + "sig177_in_sel", + &format_args!("{}", self.sig177_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func177_in_sel(&mut self) -> FUNC177_IN_SEL_W { + FUNC177_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func177_in_inv_sel(&mut self) -> FUNC177_IN_INV_SEL_W { + FUNC177_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig177_in_sel(&mut self) -> SIG177_IN_SEL_W { + SIG177_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func177_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func177_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC177_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC177_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func177_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC177_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func177_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC177_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC177_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC177_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func178_in_sel_cfg.rs b/esp32p4/src/gpio/func178_in_sel_cfg.rs new file mode 100644 index 0000000000..38e4fa4270 --- /dev/null +++ b/esp32p4/src/gpio/func178_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC178_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC178_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC178_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC178_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC178_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC178_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC178_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC178_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC178_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC178_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG178_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG178_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG178_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG178_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func178_in_sel(&self) -> FUNC178_IN_SEL_R { + FUNC178_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func178_in_inv_sel(&self) -> FUNC178_IN_INV_SEL_R { + FUNC178_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig178_in_sel(&self) -> SIG178_IN_SEL_R { + SIG178_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC178_IN_SEL_CFG") + .field( + "func178_in_sel", + &format_args!("{}", self.func178_in_sel().bits()), + ) + .field( + "func178_in_inv_sel", + &format_args!("{}", self.func178_in_inv_sel().bit()), + ) + .field( + "sig178_in_sel", + &format_args!("{}", self.sig178_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func178_in_sel(&mut self) -> FUNC178_IN_SEL_W { + FUNC178_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func178_in_inv_sel(&mut self) -> FUNC178_IN_INV_SEL_W { + FUNC178_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig178_in_sel(&mut self) -> SIG178_IN_SEL_W { + SIG178_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func178_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func178_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC178_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC178_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func178_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC178_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func178_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC178_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC178_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC178_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func179_in_sel_cfg.rs b/esp32p4/src/gpio/func179_in_sel_cfg.rs new file mode 100644 index 0000000000..ec71b210ae --- /dev/null +++ b/esp32p4/src/gpio/func179_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC179_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC179_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC179_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC179_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC179_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC179_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC179_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC179_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC179_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC179_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG179_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG179_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG179_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG179_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func179_in_sel(&self) -> FUNC179_IN_SEL_R { + FUNC179_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func179_in_inv_sel(&self) -> FUNC179_IN_INV_SEL_R { + FUNC179_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig179_in_sel(&self) -> SIG179_IN_SEL_R { + SIG179_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC179_IN_SEL_CFG") + .field( + "func179_in_sel", + &format_args!("{}", self.func179_in_sel().bits()), + ) + .field( + "func179_in_inv_sel", + &format_args!("{}", self.func179_in_inv_sel().bit()), + ) + .field( + "sig179_in_sel", + &format_args!("{}", self.sig179_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func179_in_sel(&mut self) -> FUNC179_IN_SEL_W { + FUNC179_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func179_in_inv_sel(&mut self) -> FUNC179_IN_INV_SEL_W { + FUNC179_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig179_in_sel(&mut self) -> SIG179_IN_SEL_W { + SIG179_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func179_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func179_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC179_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC179_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func179_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC179_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func179_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC179_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC179_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC179_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func17_in_sel_cfg.rs b/esp32p4/src/gpio/func17_in_sel_cfg.rs new file mode 100644 index 0000000000..431c9b8911 --- /dev/null +++ b/esp32p4/src/gpio/func17_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC17_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC17_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC17_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC17_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC17_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC17_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC17_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC17_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC17_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC17_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG17_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG17_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG17_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG17_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func17_in_sel(&self) -> FUNC17_IN_SEL_R { + FUNC17_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func17_in_inv_sel(&self) -> FUNC17_IN_INV_SEL_R { + FUNC17_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig17_in_sel(&self) -> SIG17_IN_SEL_R { + SIG17_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC17_IN_SEL_CFG") + .field( + "func17_in_sel", + &format_args!("{}", self.func17_in_sel().bits()), + ) + .field( + "func17_in_inv_sel", + &format_args!("{}", self.func17_in_inv_sel().bit()), + ) + .field( + "sig17_in_sel", + &format_args!("{}", self.sig17_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func17_in_sel(&mut self) -> FUNC17_IN_SEL_W { + FUNC17_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func17_in_inv_sel(&mut self) -> FUNC17_IN_INV_SEL_W { + FUNC17_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig17_in_sel(&mut self) -> SIG17_IN_SEL_W { + SIG17_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func17_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func17_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC17_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC17_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func17_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC17_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func17_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC17_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC17_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC17_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func180_in_sel_cfg.rs b/esp32p4/src/gpio/func180_in_sel_cfg.rs new file mode 100644 index 0000000000..f725b65243 --- /dev/null +++ b/esp32p4/src/gpio/func180_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC180_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC180_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC180_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC180_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC180_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC180_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC180_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC180_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC180_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC180_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG180_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG180_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG180_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG180_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func180_in_sel(&self) -> FUNC180_IN_SEL_R { + FUNC180_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func180_in_inv_sel(&self) -> FUNC180_IN_INV_SEL_R { + FUNC180_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig180_in_sel(&self) -> SIG180_IN_SEL_R { + SIG180_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC180_IN_SEL_CFG") + .field( + "func180_in_sel", + &format_args!("{}", self.func180_in_sel().bits()), + ) + .field( + "func180_in_inv_sel", + &format_args!("{}", self.func180_in_inv_sel().bit()), + ) + .field( + "sig180_in_sel", + &format_args!("{}", self.sig180_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func180_in_sel(&mut self) -> FUNC180_IN_SEL_W { + FUNC180_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func180_in_inv_sel(&mut self) -> FUNC180_IN_INV_SEL_W { + FUNC180_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig180_in_sel(&mut self) -> SIG180_IN_SEL_W { + SIG180_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func180_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func180_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC180_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC180_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func180_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC180_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func180_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC180_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC180_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC180_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func181_in_sel_cfg.rs b/esp32p4/src/gpio/func181_in_sel_cfg.rs new file mode 100644 index 0000000000..771d55e01c --- /dev/null +++ b/esp32p4/src/gpio/func181_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC181_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC181_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC181_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC181_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC181_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC181_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC181_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC181_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC181_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC181_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG181_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG181_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG181_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG181_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func181_in_sel(&self) -> FUNC181_IN_SEL_R { + FUNC181_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func181_in_inv_sel(&self) -> FUNC181_IN_INV_SEL_R { + FUNC181_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig181_in_sel(&self) -> SIG181_IN_SEL_R { + SIG181_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC181_IN_SEL_CFG") + .field( + "func181_in_sel", + &format_args!("{}", self.func181_in_sel().bits()), + ) + .field( + "func181_in_inv_sel", + &format_args!("{}", self.func181_in_inv_sel().bit()), + ) + .field( + "sig181_in_sel", + &format_args!("{}", self.sig181_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func181_in_sel(&mut self) -> FUNC181_IN_SEL_W { + FUNC181_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func181_in_inv_sel(&mut self) -> FUNC181_IN_INV_SEL_W { + FUNC181_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig181_in_sel(&mut self) -> SIG181_IN_SEL_W { + SIG181_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func181_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func181_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC181_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC181_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func181_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC181_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func181_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC181_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC181_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC181_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func182_in_sel_cfg.rs b/esp32p4/src/gpio/func182_in_sel_cfg.rs new file mode 100644 index 0000000000..1f64255bfe --- /dev/null +++ b/esp32p4/src/gpio/func182_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC182_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC182_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC182_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC182_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC182_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC182_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC182_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC182_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC182_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC182_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG182_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG182_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG182_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG182_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func182_in_sel(&self) -> FUNC182_IN_SEL_R { + FUNC182_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func182_in_inv_sel(&self) -> FUNC182_IN_INV_SEL_R { + FUNC182_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig182_in_sel(&self) -> SIG182_IN_SEL_R { + SIG182_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC182_IN_SEL_CFG") + .field( + "func182_in_sel", + &format_args!("{}", self.func182_in_sel().bits()), + ) + .field( + "func182_in_inv_sel", + &format_args!("{}", self.func182_in_inv_sel().bit()), + ) + .field( + "sig182_in_sel", + &format_args!("{}", self.sig182_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func182_in_sel(&mut self) -> FUNC182_IN_SEL_W { + FUNC182_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func182_in_inv_sel(&mut self) -> FUNC182_IN_INV_SEL_W { + FUNC182_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig182_in_sel(&mut self) -> SIG182_IN_SEL_W { + SIG182_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func182_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func182_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC182_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC182_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func182_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC182_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func182_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC182_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC182_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC182_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func183_in_sel_cfg.rs b/esp32p4/src/gpio/func183_in_sel_cfg.rs new file mode 100644 index 0000000000..d652053dc9 --- /dev/null +++ b/esp32p4/src/gpio/func183_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC183_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC183_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC183_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC183_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC183_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC183_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC183_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC183_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC183_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC183_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG183_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG183_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG183_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG183_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func183_in_sel(&self) -> FUNC183_IN_SEL_R { + FUNC183_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func183_in_inv_sel(&self) -> FUNC183_IN_INV_SEL_R { + FUNC183_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig183_in_sel(&self) -> SIG183_IN_SEL_R { + SIG183_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC183_IN_SEL_CFG") + .field( + "func183_in_sel", + &format_args!("{}", self.func183_in_sel().bits()), + ) + .field( + "func183_in_inv_sel", + &format_args!("{}", self.func183_in_inv_sel().bit()), + ) + .field( + "sig183_in_sel", + &format_args!("{}", self.sig183_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func183_in_sel(&mut self) -> FUNC183_IN_SEL_W { + FUNC183_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func183_in_inv_sel(&mut self) -> FUNC183_IN_INV_SEL_W { + FUNC183_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig183_in_sel(&mut self) -> SIG183_IN_SEL_W { + SIG183_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func183_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func183_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC183_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC183_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func183_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC183_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func183_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC183_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC183_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC183_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func184_in_sel_cfg.rs b/esp32p4/src/gpio/func184_in_sel_cfg.rs new file mode 100644 index 0000000000..7452404ae8 --- /dev/null +++ b/esp32p4/src/gpio/func184_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC184_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC184_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC184_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC184_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC184_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC184_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC184_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC184_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC184_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC184_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG184_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG184_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG184_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG184_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func184_in_sel(&self) -> FUNC184_IN_SEL_R { + FUNC184_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func184_in_inv_sel(&self) -> FUNC184_IN_INV_SEL_R { + FUNC184_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig184_in_sel(&self) -> SIG184_IN_SEL_R { + SIG184_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC184_IN_SEL_CFG") + .field( + "func184_in_sel", + &format_args!("{}", self.func184_in_sel().bits()), + ) + .field( + "func184_in_inv_sel", + &format_args!("{}", self.func184_in_inv_sel().bit()), + ) + .field( + "sig184_in_sel", + &format_args!("{}", self.sig184_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func184_in_sel(&mut self) -> FUNC184_IN_SEL_W { + FUNC184_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func184_in_inv_sel(&mut self) -> FUNC184_IN_INV_SEL_W { + FUNC184_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig184_in_sel(&mut self) -> SIG184_IN_SEL_W { + SIG184_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func184_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func184_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC184_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC184_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func184_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC184_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func184_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC184_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC184_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC184_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func185_in_sel_cfg.rs b/esp32p4/src/gpio/func185_in_sel_cfg.rs new file mode 100644 index 0000000000..3738b1934d --- /dev/null +++ b/esp32p4/src/gpio/func185_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC185_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC185_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC185_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC185_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC185_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC185_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC185_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC185_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC185_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC185_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG185_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG185_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG185_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG185_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func185_in_sel(&self) -> FUNC185_IN_SEL_R { + FUNC185_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func185_in_inv_sel(&self) -> FUNC185_IN_INV_SEL_R { + FUNC185_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig185_in_sel(&self) -> SIG185_IN_SEL_R { + SIG185_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC185_IN_SEL_CFG") + .field( + "func185_in_sel", + &format_args!("{}", self.func185_in_sel().bits()), + ) + .field( + "func185_in_inv_sel", + &format_args!("{}", self.func185_in_inv_sel().bit()), + ) + .field( + "sig185_in_sel", + &format_args!("{}", self.sig185_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func185_in_sel(&mut self) -> FUNC185_IN_SEL_W { + FUNC185_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func185_in_inv_sel(&mut self) -> FUNC185_IN_INV_SEL_W { + FUNC185_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig185_in_sel(&mut self) -> SIG185_IN_SEL_W { + SIG185_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func185_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func185_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC185_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC185_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func185_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC185_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func185_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC185_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC185_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC185_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func186_in_sel_cfg.rs b/esp32p4/src/gpio/func186_in_sel_cfg.rs new file mode 100644 index 0000000000..390f8cc987 --- /dev/null +++ b/esp32p4/src/gpio/func186_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC186_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC186_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC186_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC186_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC186_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC186_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC186_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC186_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC186_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC186_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG186_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG186_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG186_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG186_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func186_in_sel(&self) -> FUNC186_IN_SEL_R { + FUNC186_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func186_in_inv_sel(&self) -> FUNC186_IN_INV_SEL_R { + FUNC186_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig186_in_sel(&self) -> SIG186_IN_SEL_R { + SIG186_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC186_IN_SEL_CFG") + .field( + "func186_in_sel", + &format_args!("{}", self.func186_in_sel().bits()), + ) + .field( + "func186_in_inv_sel", + &format_args!("{}", self.func186_in_inv_sel().bit()), + ) + .field( + "sig186_in_sel", + &format_args!("{}", self.sig186_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func186_in_sel(&mut self) -> FUNC186_IN_SEL_W { + FUNC186_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func186_in_inv_sel(&mut self) -> FUNC186_IN_INV_SEL_W { + FUNC186_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig186_in_sel(&mut self) -> SIG186_IN_SEL_W { + SIG186_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func186_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func186_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC186_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC186_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func186_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC186_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func186_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC186_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC186_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC186_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func187_in_sel_cfg.rs b/esp32p4/src/gpio/func187_in_sel_cfg.rs new file mode 100644 index 0000000000..c8e4f202be --- /dev/null +++ b/esp32p4/src/gpio/func187_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC187_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC187_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC187_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC187_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC187_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC187_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC187_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC187_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC187_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC187_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG187_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG187_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG187_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG187_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func187_in_sel(&self) -> FUNC187_IN_SEL_R { + FUNC187_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func187_in_inv_sel(&self) -> FUNC187_IN_INV_SEL_R { + FUNC187_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig187_in_sel(&self) -> SIG187_IN_SEL_R { + SIG187_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC187_IN_SEL_CFG") + .field( + "func187_in_sel", + &format_args!("{}", self.func187_in_sel().bits()), + ) + .field( + "func187_in_inv_sel", + &format_args!("{}", self.func187_in_inv_sel().bit()), + ) + .field( + "sig187_in_sel", + &format_args!("{}", self.sig187_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func187_in_sel(&mut self) -> FUNC187_IN_SEL_W { + FUNC187_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func187_in_inv_sel(&mut self) -> FUNC187_IN_INV_SEL_W { + FUNC187_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig187_in_sel(&mut self) -> SIG187_IN_SEL_W { + SIG187_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func187_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func187_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC187_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC187_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func187_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC187_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func187_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC187_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC187_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC187_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func188_in_sel_cfg.rs b/esp32p4/src/gpio/func188_in_sel_cfg.rs new file mode 100644 index 0000000000..355386c0ec --- /dev/null +++ b/esp32p4/src/gpio/func188_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC188_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC188_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC188_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC188_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC188_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC188_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC188_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC188_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC188_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC188_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG188_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG188_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG188_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG188_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func188_in_sel(&self) -> FUNC188_IN_SEL_R { + FUNC188_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func188_in_inv_sel(&self) -> FUNC188_IN_INV_SEL_R { + FUNC188_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig188_in_sel(&self) -> SIG188_IN_SEL_R { + SIG188_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC188_IN_SEL_CFG") + .field( + "func188_in_sel", + &format_args!("{}", self.func188_in_sel().bits()), + ) + .field( + "func188_in_inv_sel", + &format_args!("{}", self.func188_in_inv_sel().bit()), + ) + .field( + "sig188_in_sel", + &format_args!("{}", self.sig188_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func188_in_sel(&mut self) -> FUNC188_IN_SEL_W { + FUNC188_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func188_in_inv_sel(&mut self) -> FUNC188_IN_INV_SEL_W { + FUNC188_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig188_in_sel(&mut self) -> SIG188_IN_SEL_W { + SIG188_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func188_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func188_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC188_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC188_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func188_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC188_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func188_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC188_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC188_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC188_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func189_in_sel_cfg.rs b/esp32p4/src/gpio/func189_in_sel_cfg.rs new file mode 100644 index 0000000000..6f93f4f287 --- /dev/null +++ b/esp32p4/src/gpio/func189_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC189_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC189_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC189_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC189_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC189_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC189_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC189_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC189_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC189_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC189_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG189_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG189_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG189_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG189_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func189_in_sel(&self) -> FUNC189_IN_SEL_R { + FUNC189_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func189_in_inv_sel(&self) -> FUNC189_IN_INV_SEL_R { + FUNC189_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig189_in_sel(&self) -> SIG189_IN_SEL_R { + SIG189_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC189_IN_SEL_CFG") + .field( + "func189_in_sel", + &format_args!("{}", self.func189_in_sel().bits()), + ) + .field( + "func189_in_inv_sel", + &format_args!("{}", self.func189_in_inv_sel().bit()), + ) + .field( + "sig189_in_sel", + &format_args!("{}", self.sig189_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func189_in_sel(&mut self) -> FUNC189_IN_SEL_W { + FUNC189_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func189_in_inv_sel(&mut self) -> FUNC189_IN_INV_SEL_W { + FUNC189_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig189_in_sel(&mut self) -> SIG189_IN_SEL_W { + SIG189_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func189_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func189_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC189_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC189_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func189_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC189_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func189_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC189_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC189_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC189_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func18_in_sel_cfg.rs b/esp32p4/src/gpio/func18_in_sel_cfg.rs new file mode 100644 index 0000000000..fb17832a72 --- /dev/null +++ b/esp32p4/src/gpio/func18_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC18_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC18_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC18_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC18_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC18_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC18_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC18_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC18_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC18_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC18_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG18_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG18_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG18_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG18_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func18_in_sel(&self) -> FUNC18_IN_SEL_R { + FUNC18_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func18_in_inv_sel(&self) -> FUNC18_IN_INV_SEL_R { + FUNC18_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig18_in_sel(&self) -> SIG18_IN_SEL_R { + SIG18_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC18_IN_SEL_CFG") + .field( + "func18_in_sel", + &format_args!("{}", self.func18_in_sel().bits()), + ) + .field( + "func18_in_inv_sel", + &format_args!("{}", self.func18_in_inv_sel().bit()), + ) + .field( + "sig18_in_sel", + &format_args!("{}", self.sig18_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func18_in_sel(&mut self) -> FUNC18_IN_SEL_W { + FUNC18_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func18_in_inv_sel(&mut self) -> FUNC18_IN_INV_SEL_W { + FUNC18_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig18_in_sel(&mut self) -> SIG18_IN_SEL_W { + SIG18_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func18_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func18_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC18_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC18_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func18_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC18_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func18_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC18_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC18_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC18_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func190_in_sel_cfg.rs b/esp32p4/src/gpio/func190_in_sel_cfg.rs new file mode 100644 index 0000000000..3ef3d5c868 --- /dev/null +++ b/esp32p4/src/gpio/func190_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC190_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC190_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC190_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC190_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC190_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC190_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC190_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC190_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC190_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC190_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG190_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG190_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG190_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG190_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func190_in_sel(&self) -> FUNC190_IN_SEL_R { + FUNC190_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func190_in_inv_sel(&self) -> FUNC190_IN_INV_SEL_R { + FUNC190_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig190_in_sel(&self) -> SIG190_IN_SEL_R { + SIG190_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC190_IN_SEL_CFG") + .field( + "func190_in_sel", + &format_args!("{}", self.func190_in_sel().bits()), + ) + .field( + "func190_in_inv_sel", + &format_args!("{}", self.func190_in_inv_sel().bit()), + ) + .field( + "sig190_in_sel", + &format_args!("{}", self.sig190_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func190_in_sel(&mut self) -> FUNC190_IN_SEL_W { + FUNC190_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func190_in_inv_sel(&mut self) -> FUNC190_IN_INV_SEL_W { + FUNC190_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig190_in_sel(&mut self) -> SIG190_IN_SEL_W { + SIG190_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func190_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func190_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC190_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC190_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func190_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC190_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func190_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC190_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC190_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC190_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func191_in_sel_cfg.rs b/esp32p4/src/gpio/func191_in_sel_cfg.rs new file mode 100644 index 0000000000..cb89ee0db5 --- /dev/null +++ b/esp32p4/src/gpio/func191_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC191_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC191_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC191_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC191_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC191_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC191_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC191_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC191_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC191_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC191_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG191_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG191_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG191_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG191_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func191_in_sel(&self) -> FUNC191_IN_SEL_R { + FUNC191_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func191_in_inv_sel(&self) -> FUNC191_IN_INV_SEL_R { + FUNC191_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig191_in_sel(&self) -> SIG191_IN_SEL_R { + SIG191_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC191_IN_SEL_CFG") + .field( + "func191_in_sel", + &format_args!("{}", self.func191_in_sel().bits()), + ) + .field( + "func191_in_inv_sel", + &format_args!("{}", self.func191_in_inv_sel().bit()), + ) + .field( + "sig191_in_sel", + &format_args!("{}", self.sig191_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func191_in_sel(&mut self) -> FUNC191_IN_SEL_W { + FUNC191_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func191_in_inv_sel(&mut self) -> FUNC191_IN_INV_SEL_W { + FUNC191_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig191_in_sel(&mut self) -> SIG191_IN_SEL_W { + SIG191_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func191_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func191_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC191_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC191_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func191_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC191_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func191_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC191_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC191_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC191_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func192_in_sel_cfg.rs b/esp32p4/src/gpio/func192_in_sel_cfg.rs new file mode 100644 index 0000000000..d4183206d3 --- /dev/null +++ b/esp32p4/src/gpio/func192_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC192_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC192_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC192_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC192_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC192_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC192_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC192_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC192_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC192_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC192_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG192_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG192_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG192_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG192_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func192_in_sel(&self) -> FUNC192_IN_SEL_R { + FUNC192_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func192_in_inv_sel(&self) -> FUNC192_IN_INV_SEL_R { + FUNC192_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig192_in_sel(&self) -> SIG192_IN_SEL_R { + SIG192_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC192_IN_SEL_CFG") + .field( + "func192_in_sel", + &format_args!("{}", self.func192_in_sel().bits()), + ) + .field( + "func192_in_inv_sel", + &format_args!("{}", self.func192_in_inv_sel().bit()), + ) + .field( + "sig192_in_sel", + &format_args!("{}", self.sig192_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func192_in_sel(&mut self) -> FUNC192_IN_SEL_W { + FUNC192_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func192_in_inv_sel(&mut self) -> FUNC192_IN_INV_SEL_W { + FUNC192_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig192_in_sel(&mut self) -> SIG192_IN_SEL_W { + SIG192_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func192_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func192_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC192_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC192_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func192_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC192_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func192_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC192_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC192_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC192_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func193_in_sel_cfg.rs b/esp32p4/src/gpio/func193_in_sel_cfg.rs new file mode 100644 index 0000000000..b448efd131 --- /dev/null +++ b/esp32p4/src/gpio/func193_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC193_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC193_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC193_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC193_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC193_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC193_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC193_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC193_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC193_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC193_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG193_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG193_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG193_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG193_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func193_in_sel(&self) -> FUNC193_IN_SEL_R { + FUNC193_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func193_in_inv_sel(&self) -> FUNC193_IN_INV_SEL_R { + FUNC193_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig193_in_sel(&self) -> SIG193_IN_SEL_R { + SIG193_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC193_IN_SEL_CFG") + .field( + "func193_in_sel", + &format_args!("{}", self.func193_in_sel().bits()), + ) + .field( + "func193_in_inv_sel", + &format_args!("{}", self.func193_in_inv_sel().bit()), + ) + .field( + "sig193_in_sel", + &format_args!("{}", self.sig193_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func193_in_sel(&mut self) -> FUNC193_IN_SEL_W { + FUNC193_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func193_in_inv_sel(&mut self) -> FUNC193_IN_INV_SEL_W { + FUNC193_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig193_in_sel(&mut self) -> SIG193_IN_SEL_W { + SIG193_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func193_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func193_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC193_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC193_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func193_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC193_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func193_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC193_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC193_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC193_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func194_in_sel_cfg.rs b/esp32p4/src/gpio/func194_in_sel_cfg.rs new file mode 100644 index 0000000000..6f064ba8b1 --- /dev/null +++ b/esp32p4/src/gpio/func194_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC194_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC194_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC194_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC194_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC194_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC194_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC194_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC194_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC194_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC194_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG194_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG194_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG194_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG194_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func194_in_sel(&self) -> FUNC194_IN_SEL_R { + FUNC194_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func194_in_inv_sel(&self) -> FUNC194_IN_INV_SEL_R { + FUNC194_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig194_in_sel(&self) -> SIG194_IN_SEL_R { + SIG194_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC194_IN_SEL_CFG") + .field( + "func194_in_sel", + &format_args!("{}", self.func194_in_sel().bits()), + ) + .field( + "func194_in_inv_sel", + &format_args!("{}", self.func194_in_inv_sel().bit()), + ) + .field( + "sig194_in_sel", + &format_args!("{}", self.sig194_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func194_in_sel(&mut self) -> FUNC194_IN_SEL_W { + FUNC194_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func194_in_inv_sel(&mut self) -> FUNC194_IN_INV_SEL_W { + FUNC194_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig194_in_sel(&mut self) -> SIG194_IN_SEL_W { + SIG194_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func194_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func194_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC194_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC194_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func194_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC194_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func194_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC194_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC194_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC194_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func195_in_sel_cfg.rs b/esp32p4/src/gpio/func195_in_sel_cfg.rs new file mode 100644 index 0000000000..2a7c157ff0 --- /dev/null +++ b/esp32p4/src/gpio/func195_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC195_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC195_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC195_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC195_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC195_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC195_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC195_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC195_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC195_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC195_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG195_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG195_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG195_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG195_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func195_in_sel(&self) -> FUNC195_IN_SEL_R { + FUNC195_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func195_in_inv_sel(&self) -> FUNC195_IN_INV_SEL_R { + FUNC195_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig195_in_sel(&self) -> SIG195_IN_SEL_R { + SIG195_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC195_IN_SEL_CFG") + .field( + "func195_in_sel", + &format_args!("{}", self.func195_in_sel().bits()), + ) + .field( + "func195_in_inv_sel", + &format_args!("{}", self.func195_in_inv_sel().bit()), + ) + .field( + "sig195_in_sel", + &format_args!("{}", self.sig195_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func195_in_sel(&mut self) -> FUNC195_IN_SEL_W { + FUNC195_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func195_in_inv_sel(&mut self) -> FUNC195_IN_INV_SEL_W { + FUNC195_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig195_in_sel(&mut self) -> SIG195_IN_SEL_W { + SIG195_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func195_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func195_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC195_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC195_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func195_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC195_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func195_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC195_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC195_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC195_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func196_in_sel_cfg.rs b/esp32p4/src/gpio/func196_in_sel_cfg.rs new file mode 100644 index 0000000000..f046b9e506 --- /dev/null +++ b/esp32p4/src/gpio/func196_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC196_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC196_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC196_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC196_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC196_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC196_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC196_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC196_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC196_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC196_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG196_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG196_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG196_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG196_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func196_in_sel(&self) -> FUNC196_IN_SEL_R { + FUNC196_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func196_in_inv_sel(&self) -> FUNC196_IN_INV_SEL_R { + FUNC196_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig196_in_sel(&self) -> SIG196_IN_SEL_R { + SIG196_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC196_IN_SEL_CFG") + .field( + "func196_in_sel", + &format_args!("{}", self.func196_in_sel().bits()), + ) + .field( + "func196_in_inv_sel", + &format_args!("{}", self.func196_in_inv_sel().bit()), + ) + .field( + "sig196_in_sel", + &format_args!("{}", self.sig196_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func196_in_sel(&mut self) -> FUNC196_IN_SEL_W { + FUNC196_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func196_in_inv_sel(&mut self) -> FUNC196_IN_INV_SEL_W { + FUNC196_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig196_in_sel(&mut self) -> SIG196_IN_SEL_W { + SIG196_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func196_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func196_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC196_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC196_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func196_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC196_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func196_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC196_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC196_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC196_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func197_in_sel_cfg.rs b/esp32p4/src/gpio/func197_in_sel_cfg.rs new file mode 100644 index 0000000000..52bbbccbd0 --- /dev/null +++ b/esp32p4/src/gpio/func197_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC197_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC197_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC197_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC197_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC197_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC197_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC197_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC197_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC197_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC197_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG197_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG197_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG197_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG197_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func197_in_sel(&self) -> FUNC197_IN_SEL_R { + FUNC197_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func197_in_inv_sel(&self) -> FUNC197_IN_INV_SEL_R { + FUNC197_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig197_in_sel(&self) -> SIG197_IN_SEL_R { + SIG197_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC197_IN_SEL_CFG") + .field( + "func197_in_sel", + &format_args!("{}", self.func197_in_sel().bits()), + ) + .field( + "func197_in_inv_sel", + &format_args!("{}", self.func197_in_inv_sel().bit()), + ) + .field( + "sig197_in_sel", + &format_args!("{}", self.sig197_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func197_in_sel(&mut self) -> FUNC197_IN_SEL_W { + FUNC197_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func197_in_inv_sel(&mut self) -> FUNC197_IN_INV_SEL_W { + FUNC197_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig197_in_sel(&mut self) -> SIG197_IN_SEL_W { + SIG197_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func197_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func197_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC197_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC197_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func197_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC197_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func197_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC197_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC197_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC197_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func198_in_sel_cfg.rs b/esp32p4/src/gpio/func198_in_sel_cfg.rs new file mode 100644 index 0000000000..78b7fec4f6 --- /dev/null +++ b/esp32p4/src/gpio/func198_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC198_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC198_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC198_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC198_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC198_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC198_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC198_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC198_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC198_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC198_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG198_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG198_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG198_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG198_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func198_in_sel(&self) -> FUNC198_IN_SEL_R { + FUNC198_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func198_in_inv_sel(&self) -> FUNC198_IN_INV_SEL_R { + FUNC198_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig198_in_sel(&self) -> SIG198_IN_SEL_R { + SIG198_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC198_IN_SEL_CFG") + .field( + "func198_in_sel", + &format_args!("{}", self.func198_in_sel().bits()), + ) + .field( + "func198_in_inv_sel", + &format_args!("{}", self.func198_in_inv_sel().bit()), + ) + .field( + "sig198_in_sel", + &format_args!("{}", self.sig198_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func198_in_sel(&mut self) -> FUNC198_IN_SEL_W { + FUNC198_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func198_in_inv_sel(&mut self) -> FUNC198_IN_INV_SEL_W { + FUNC198_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig198_in_sel(&mut self) -> SIG198_IN_SEL_W { + SIG198_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func198_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func198_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC198_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC198_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func198_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC198_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func198_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC198_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC198_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC198_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func199_in_sel_cfg.rs b/esp32p4/src/gpio/func199_in_sel_cfg.rs new file mode 100644 index 0000000000..c215e59da2 --- /dev/null +++ b/esp32p4/src/gpio/func199_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC199_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC199_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC199_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC199_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC199_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC199_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC199_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC199_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC199_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC199_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG199_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG199_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG199_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG199_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func199_in_sel(&self) -> FUNC199_IN_SEL_R { + FUNC199_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func199_in_inv_sel(&self) -> FUNC199_IN_INV_SEL_R { + FUNC199_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig199_in_sel(&self) -> SIG199_IN_SEL_R { + SIG199_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC199_IN_SEL_CFG") + .field( + "func199_in_sel", + &format_args!("{}", self.func199_in_sel().bits()), + ) + .field( + "func199_in_inv_sel", + &format_args!("{}", self.func199_in_inv_sel().bit()), + ) + .field( + "sig199_in_sel", + &format_args!("{}", self.sig199_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func199_in_sel(&mut self) -> FUNC199_IN_SEL_W { + FUNC199_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func199_in_inv_sel(&mut self) -> FUNC199_IN_INV_SEL_W { + FUNC199_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig199_in_sel(&mut self) -> SIG199_IN_SEL_W { + SIG199_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func199_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func199_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC199_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC199_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func199_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC199_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func199_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC199_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC199_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC199_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func19_in_sel_cfg.rs b/esp32p4/src/gpio/func19_in_sel_cfg.rs new file mode 100644 index 0000000000..5ae2bcec14 --- /dev/null +++ b/esp32p4/src/gpio/func19_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC19_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC19_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC19_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC19_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC19_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC19_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC19_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC19_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC19_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC19_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG19_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG19_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG19_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG19_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func19_in_sel(&self) -> FUNC19_IN_SEL_R { + FUNC19_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func19_in_inv_sel(&self) -> FUNC19_IN_INV_SEL_R { + FUNC19_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig19_in_sel(&self) -> SIG19_IN_SEL_R { + SIG19_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC19_IN_SEL_CFG") + .field( + "func19_in_sel", + &format_args!("{}", self.func19_in_sel().bits()), + ) + .field( + "func19_in_inv_sel", + &format_args!("{}", self.func19_in_inv_sel().bit()), + ) + .field( + "sig19_in_sel", + &format_args!("{}", self.sig19_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func19_in_sel(&mut self) -> FUNC19_IN_SEL_W { + FUNC19_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func19_in_inv_sel(&mut self) -> FUNC19_IN_INV_SEL_W { + FUNC19_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig19_in_sel(&mut self) -> SIG19_IN_SEL_W { + SIG19_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func19_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func19_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC19_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC19_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func19_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC19_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func19_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC19_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC19_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC19_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func1_in_sel_cfg.rs b/esp32p4/src/gpio/func1_in_sel_cfg.rs new file mode 100644 index 0000000000..969d01eae1 --- /dev/null +++ b/esp32p4/src/gpio/func1_in_sel_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `FUNC1_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC1_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC1_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC1_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC1_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC1_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC1_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC1_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC1_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC1_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG1_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG1_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG1_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG1_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func1_in_sel(&self) -> FUNC1_IN_SEL_R { + FUNC1_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func1_in_inv_sel(&self) -> FUNC1_IN_INV_SEL_R { + FUNC1_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig1_in_sel(&self) -> SIG1_IN_SEL_R { + SIG1_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC1_IN_SEL_CFG") + .field( + "func1_in_sel", + &format_args!("{}", self.func1_in_sel().bits()), + ) + .field( + "func1_in_inv_sel", + &format_args!("{}", self.func1_in_inv_sel().bit()), + ) + .field("sig1_in_sel", &format_args!("{}", self.sig1_in_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func1_in_sel(&mut self) -> FUNC1_IN_SEL_W { + FUNC1_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func1_in_inv_sel(&mut self) -> FUNC1_IN_INV_SEL_W { + FUNC1_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig1_in_sel(&mut self) -> SIG1_IN_SEL_W { + SIG1_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func1_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func1_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC1_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC1_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func1_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC1_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func1_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC1_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC1_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC1_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func200_in_sel_cfg.rs b/esp32p4/src/gpio/func200_in_sel_cfg.rs new file mode 100644 index 0000000000..ef83786791 --- /dev/null +++ b/esp32p4/src/gpio/func200_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC200_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC200_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC200_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC200_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC200_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC200_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC200_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC200_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC200_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC200_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG200_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG200_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG200_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG200_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func200_in_sel(&self) -> FUNC200_IN_SEL_R { + FUNC200_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func200_in_inv_sel(&self) -> FUNC200_IN_INV_SEL_R { + FUNC200_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig200_in_sel(&self) -> SIG200_IN_SEL_R { + SIG200_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC200_IN_SEL_CFG") + .field( + "func200_in_sel", + &format_args!("{}", self.func200_in_sel().bits()), + ) + .field( + "func200_in_inv_sel", + &format_args!("{}", self.func200_in_inv_sel().bit()), + ) + .field( + "sig200_in_sel", + &format_args!("{}", self.sig200_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func200_in_sel(&mut self) -> FUNC200_IN_SEL_W { + FUNC200_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func200_in_inv_sel(&mut self) -> FUNC200_IN_INV_SEL_W { + FUNC200_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig200_in_sel(&mut self) -> SIG200_IN_SEL_W { + SIG200_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func200_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func200_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC200_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC200_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func200_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC200_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func200_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC200_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC200_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC200_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func201_in_sel_cfg.rs b/esp32p4/src/gpio/func201_in_sel_cfg.rs new file mode 100644 index 0000000000..f5299ea5ad --- /dev/null +++ b/esp32p4/src/gpio/func201_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC201_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC201_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC201_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC201_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC201_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC201_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC201_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC201_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC201_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC201_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG201_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG201_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG201_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG201_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func201_in_sel(&self) -> FUNC201_IN_SEL_R { + FUNC201_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func201_in_inv_sel(&self) -> FUNC201_IN_INV_SEL_R { + FUNC201_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig201_in_sel(&self) -> SIG201_IN_SEL_R { + SIG201_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC201_IN_SEL_CFG") + .field( + "func201_in_sel", + &format_args!("{}", self.func201_in_sel().bits()), + ) + .field( + "func201_in_inv_sel", + &format_args!("{}", self.func201_in_inv_sel().bit()), + ) + .field( + "sig201_in_sel", + &format_args!("{}", self.sig201_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func201_in_sel(&mut self) -> FUNC201_IN_SEL_W { + FUNC201_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func201_in_inv_sel(&mut self) -> FUNC201_IN_INV_SEL_W { + FUNC201_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig201_in_sel(&mut self) -> SIG201_IN_SEL_W { + SIG201_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func201_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func201_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC201_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC201_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func201_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC201_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func201_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC201_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC201_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC201_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func202_in_sel_cfg.rs b/esp32p4/src/gpio/func202_in_sel_cfg.rs new file mode 100644 index 0000000000..bfa474bb34 --- /dev/null +++ b/esp32p4/src/gpio/func202_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC202_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC202_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC202_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC202_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC202_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC202_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC202_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC202_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC202_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC202_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG202_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG202_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG202_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG202_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func202_in_sel(&self) -> FUNC202_IN_SEL_R { + FUNC202_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func202_in_inv_sel(&self) -> FUNC202_IN_INV_SEL_R { + FUNC202_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig202_in_sel(&self) -> SIG202_IN_SEL_R { + SIG202_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC202_IN_SEL_CFG") + .field( + "func202_in_sel", + &format_args!("{}", self.func202_in_sel().bits()), + ) + .field( + "func202_in_inv_sel", + &format_args!("{}", self.func202_in_inv_sel().bit()), + ) + .field( + "sig202_in_sel", + &format_args!("{}", self.sig202_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func202_in_sel(&mut self) -> FUNC202_IN_SEL_W { + FUNC202_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func202_in_inv_sel(&mut self) -> FUNC202_IN_INV_SEL_W { + FUNC202_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig202_in_sel(&mut self) -> SIG202_IN_SEL_W { + SIG202_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func202_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func202_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC202_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC202_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func202_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC202_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func202_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC202_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC202_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC202_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func203_in_sel_cfg.rs b/esp32p4/src/gpio/func203_in_sel_cfg.rs new file mode 100644 index 0000000000..5118935ba6 --- /dev/null +++ b/esp32p4/src/gpio/func203_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC203_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC203_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC203_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC203_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC203_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC203_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC203_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC203_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC203_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC203_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG203_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG203_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG203_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG203_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func203_in_sel(&self) -> FUNC203_IN_SEL_R { + FUNC203_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func203_in_inv_sel(&self) -> FUNC203_IN_INV_SEL_R { + FUNC203_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig203_in_sel(&self) -> SIG203_IN_SEL_R { + SIG203_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC203_IN_SEL_CFG") + .field( + "func203_in_sel", + &format_args!("{}", self.func203_in_sel().bits()), + ) + .field( + "func203_in_inv_sel", + &format_args!("{}", self.func203_in_inv_sel().bit()), + ) + .field( + "sig203_in_sel", + &format_args!("{}", self.sig203_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func203_in_sel(&mut self) -> FUNC203_IN_SEL_W { + FUNC203_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func203_in_inv_sel(&mut self) -> FUNC203_IN_INV_SEL_W { + FUNC203_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig203_in_sel(&mut self) -> SIG203_IN_SEL_W { + SIG203_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func203_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func203_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC203_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC203_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func203_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC203_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func203_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC203_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC203_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC203_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func20_in_sel_cfg.rs b/esp32p4/src/gpio/func20_in_sel_cfg.rs new file mode 100644 index 0000000000..8cf0306254 --- /dev/null +++ b/esp32p4/src/gpio/func20_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC20_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC20_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC20_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC20_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC20_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC20_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC20_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC20_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC20_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC20_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG20_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG20_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG20_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG20_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func20_in_sel(&self) -> FUNC20_IN_SEL_R { + FUNC20_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func20_in_inv_sel(&self) -> FUNC20_IN_INV_SEL_R { + FUNC20_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig20_in_sel(&self) -> SIG20_IN_SEL_R { + SIG20_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC20_IN_SEL_CFG") + .field( + "func20_in_sel", + &format_args!("{}", self.func20_in_sel().bits()), + ) + .field( + "func20_in_inv_sel", + &format_args!("{}", self.func20_in_inv_sel().bit()), + ) + .field( + "sig20_in_sel", + &format_args!("{}", self.sig20_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func20_in_sel(&mut self) -> FUNC20_IN_SEL_W { + FUNC20_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func20_in_inv_sel(&mut self) -> FUNC20_IN_INV_SEL_W { + FUNC20_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig20_in_sel(&mut self) -> SIG20_IN_SEL_W { + SIG20_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func20_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func20_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC20_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC20_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func20_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC20_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func20_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC20_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC20_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC20_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func214_in_sel_cfg.rs b/esp32p4/src/gpio/func214_in_sel_cfg.rs new file mode 100644 index 0000000000..6fb1238b82 --- /dev/null +++ b/esp32p4/src/gpio/func214_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC214_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC214_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC214_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC214_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC214_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC214_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC214_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC214_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC214_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC214_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG214_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG214_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG214_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG214_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func214_in_sel(&self) -> FUNC214_IN_SEL_R { + FUNC214_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func214_in_inv_sel(&self) -> FUNC214_IN_INV_SEL_R { + FUNC214_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig214_in_sel(&self) -> SIG214_IN_SEL_R { + SIG214_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC214_IN_SEL_CFG") + .field( + "func214_in_sel", + &format_args!("{}", self.func214_in_sel().bits()), + ) + .field( + "func214_in_inv_sel", + &format_args!("{}", self.func214_in_inv_sel().bit()), + ) + .field( + "sig214_in_sel", + &format_args!("{}", self.sig214_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func214_in_sel(&mut self) -> FUNC214_IN_SEL_W { + FUNC214_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func214_in_inv_sel(&mut self) -> FUNC214_IN_INV_SEL_W { + FUNC214_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig214_in_sel(&mut self) -> SIG214_IN_SEL_W { + SIG214_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func214_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func214_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC214_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC214_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func214_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC214_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func214_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC214_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC214_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC214_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func215_in_sel_cfg.rs b/esp32p4/src/gpio/func215_in_sel_cfg.rs new file mode 100644 index 0000000000..2eac2c9909 --- /dev/null +++ b/esp32p4/src/gpio/func215_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC215_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC215_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC215_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC215_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC215_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC215_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC215_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC215_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC215_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC215_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG215_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG215_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG215_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG215_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func215_in_sel(&self) -> FUNC215_IN_SEL_R { + FUNC215_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func215_in_inv_sel(&self) -> FUNC215_IN_INV_SEL_R { + FUNC215_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig215_in_sel(&self) -> SIG215_IN_SEL_R { + SIG215_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC215_IN_SEL_CFG") + .field( + "func215_in_sel", + &format_args!("{}", self.func215_in_sel().bits()), + ) + .field( + "func215_in_inv_sel", + &format_args!("{}", self.func215_in_inv_sel().bit()), + ) + .field( + "sig215_in_sel", + &format_args!("{}", self.sig215_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func215_in_sel(&mut self) -> FUNC215_IN_SEL_W { + FUNC215_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func215_in_inv_sel(&mut self) -> FUNC215_IN_INV_SEL_W { + FUNC215_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig215_in_sel(&mut self) -> SIG215_IN_SEL_W { + SIG215_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func215_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func215_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC215_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC215_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func215_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC215_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func215_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC215_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC215_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC215_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func216_in_sel_cfg.rs b/esp32p4/src/gpio/func216_in_sel_cfg.rs new file mode 100644 index 0000000000..71bd28bc64 --- /dev/null +++ b/esp32p4/src/gpio/func216_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC216_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC216_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC216_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC216_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC216_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC216_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC216_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC216_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC216_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC216_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG216_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG216_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG216_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG216_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func216_in_sel(&self) -> FUNC216_IN_SEL_R { + FUNC216_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func216_in_inv_sel(&self) -> FUNC216_IN_INV_SEL_R { + FUNC216_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig216_in_sel(&self) -> SIG216_IN_SEL_R { + SIG216_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC216_IN_SEL_CFG") + .field( + "func216_in_sel", + &format_args!("{}", self.func216_in_sel().bits()), + ) + .field( + "func216_in_inv_sel", + &format_args!("{}", self.func216_in_inv_sel().bit()), + ) + .field( + "sig216_in_sel", + &format_args!("{}", self.sig216_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func216_in_sel(&mut self) -> FUNC216_IN_SEL_W { + FUNC216_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func216_in_inv_sel(&mut self) -> FUNC216_IN_INV_SEL_W { + FUNC216_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig216_in_sel(&mut self) -> SIG216_IN_SEL_W { + SIG216_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func216_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func216_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC216_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC216_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func216_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC216_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func216_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC216_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC216_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC216_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func217_in_sel_cfg.rs b/esp32p4/src/gpio/func217_in_sel_cfg.rs new file mode 100644 index 0000000000..4be80c8f1a --- /dev/null +++ b/esp32p4/src/gpio/func217_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC217_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC217_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC217_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC217_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC217_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC217_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC217_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC217_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC217_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC217_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG217_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG217_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG217_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG217_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func217_in_sel(&self) -> FUNC217_IN_SEL_R { + FUNC217_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func217_in_inv_sel(&self) -> FUNC217_IN_INV_SEL_R { + FUNC217_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig217_in_sel(&self) -> SIG217_IN_SEL_R { + SIG217_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC217_IN_SEL_CFG") + .field( + "func217_in_sel", + &format_args!("{}", self.func217_in_sel().bits()), + ) + .field( + "func217_in_inv_sel", + &format_args!("{}", self.func217_in_inv_sel().bit()), + ) + .field( + "sig217_in_sel", + &format_args!("{}", self.sig217_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func217_in_sel(&mut self) -> FUNC217_IN_SEL_W { + FUNC217_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func217_in_inv_sel(&mut self) -> FUNC217_IN_INV_SEL_W { + FUNC217_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig217_in_sel(&mut self) -> SIG217_IN_SEL_W { + SIG217_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func217_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func217_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC217_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC217_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func217_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC217_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func217_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC217_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC217_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC217_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func218_in_sel_cfg.rs b/esp32p4/src/gpio/func218_in_sel_cfg.rs new file mode 100644 index 0000000000..dfee6debf8 --- /dev/null +++ b/esp32p4/src/gpio/func218_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC218_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC218_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC218_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC218_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC218_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC218_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC218_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC218_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC218_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC218_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG218_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG218_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG218_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG218_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func218_in_sel(&self) -> FUNC218_IN_SEL_R { + FUNC218_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func218_in_inv_sel(&self) -> FUNC218_IN_INV_SEL_R { + FUNC218_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig218_in_sel(&self) -> SIG218_IN_SEL_R { + SIG218_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC218_IN_SEL_CFG") + .field( + "func218_in_sel", + &format_args!("{}", self.func218_in_sel().bits()), + ) + .field( + "func218_in_inv_sel", + &format_args!("{}", self.func218_in_inv_sel().bit()), + ) + .field( + "sig218_in_sel", + &format_args!("{}", self.sig218_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func218_in_sel(&mut self) -> FUNC218_IN_SEL_W { + FUNC218_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func218_in_inv_sel(&mut self) -> FUNC218_IN_INV_SEL_W { + FUNC218_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig218_in_sel(&mut self) -> SIG218_IN_SEL_W { + SIG218_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func218_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func218_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC218_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC218_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func218_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC218_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func218_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC218_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC218_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC218_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func219_in_sel_cfg.rs b/esp32p4/src/gpio/func219_in_sel_cfg.rs new file mode 100644 index 0000000000..8f76f89f71 --- /dev/null +++ b/esp32p4/src/gpio/func219_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC219_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC219_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC219_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC219_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC219_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC219_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC219_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC219_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC219_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC219_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG219_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG219_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG219_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG219_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func219_in_sel(&self) -> FUNC219_IN_SEL_R { + FUNC219_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func219_in_inv_sel(&self) -> FUNC219_IN_INV_SEL_R { + FUNC219_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig219_in_sel(&self) -> SIG219_IN_SEL_R { + SIG219_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC219_IN_SEL_CFG") + .field( + "func219_in_sel", + &format_args!("{}", self.func219_in_sel().bits()), + ) + .field( + "func219_in_inv_sel", + &format_args!("{}", self.func219_in_inv_sel().bit()), + ) + .field( + "sig219_in_sel", + &format_args!("{}", self.sig219_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func219_in_sel(&mut self) -> FUNC219_IN_SEL_W { + FUNC219_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func219_in_inv_sel(&mut self) -> FUNC219_IN_INV_SEL_W { + FUNC219_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig219_in_sel(&mut self) -> SIG219_IN_SEL_W { + SIG219_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func219_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func219_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC219_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC219_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func219_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC219_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func219_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC219_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC219_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC219_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func21_in_sel_cfg.rs b/esp32p4/src/gpio/func21_in_sel_cfg.rs new file mode 100644 index 0000000000..89597fdcf7 --- /dev/null +++ b/esp32p4/src/gpio/func21_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC21_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC21_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC21_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC21_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC21_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC21_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC21_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC21_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC21_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC21_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG21_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG21_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG21_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG21_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func21_in_sel(&self) -> FUNC21_IN_SEL_R { + FUNC21_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func21_in_inv_sel(&self) -> FUNC21_IN_INV_SEL_R { + FUNC21_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig21_in_sel(&self) -> SIG21_IN_SEL_R { + SIG21_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC21_IN_SEL_CFG") + .field( + "func21_in_sel", + &format_args!("{}", self.func21_in_sel().bits()), + ) + .field( + "func21_in_inv_sel", + &format_args!("{}", self.func21_in_inv_sel().bit()), + ) + .field( + "sig21_in_sel", + &format_args!("{}", self.sig21_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func21_in_sel(&mut self) -> FUNC21_IN_SEL_W { + FUNC21_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func21_in_inv_sel(&mut self) -> FUNC21_IN_INV_SEL_W { + FUNC21_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig21_in_sel(&mut self) -> SIG21_IN_SEL_W { + SIG21_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func21_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func21_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC21_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC21_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func21_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC21_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func21_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC21_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC21_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC21_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func220_in_sel_cfg.rs b/esp32p4/src/gpio/func220_in_sel_cfg.rs new file mode 100644 index 0000000000..3e49bf0e38 --- /dev/null +++ b/esp32p4/src/gpio/func220_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC220_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC220_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC220_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC220_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC220_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC220_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC220_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC220_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC220_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC220_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG220_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG220_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG220_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG220_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func220_in_sel(&self) -> FUNC220_IN_SEL_R { + FUNC220_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func220_in_inv_sel(&self) -> FUNC220_IN_INV_SEL_R { + FUNC220_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig220_in_sel(&self) -> SIG220_IN_SEL_R { + SIG220_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC220_IN_SEL_CFG") + .field( + "func220_in_sel", + &format_args!("{}", self.func220_in_sel().bits()), + ) + .field( + "func220_in_inv_sel", + &format_args!("{}", self.func220_in_inv_sel().bit()), + ) + .field( + "sig220_in_sel", + &format_args!("{}", self.sig220_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func220_in_sel(&mut self) -> FUNC220_IN_SEL_W { + FUNC220_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func220_in_inv_sel(&mut self) -> FUNC220_IN_INV_SEL_W { + FUNC220_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig220_in_sel(&mut self) -> SIG220_IN_SEL_W { + SIG220_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func220_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func220_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC220_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC220_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func220_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC220_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func220_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC220_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC220_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC220_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func221_in_sel_cfg.rs b/esp32p4/src/gpio/func221_in_sel_cfg.rs new file mode 100644 index 0000000000..c5c8849a42 --- /dev/null +++ b/esp32p4/src/gpio/func221_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC221_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC221_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC221_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC221_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC221_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC221_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC221_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC221_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC221_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC221_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG221_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG221_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG221_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG221_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func221_in_sel(&self) -> FUNC221_IN_SEL_R { + FUNC221_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func221_in_inv_sel(&self) -> FUNC221_IN_INV_SEL_R { + FUNC221_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig221_in_sel(&self) -> SIG221_IN_SEL_R { + SIG221_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC221_IN_SEL_CFG") + .field( + "func221_in_sel", + &format_args!("{}", self.func221_in_sel().bits()), + ) + .field( + "func221_in_inv_sel", + &format_args!("{}", self.func221_in_inv_sel().bit()), + ) + .field( + "sig221_in_sel", + &format_args!("{}", self.sig221_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func221_in_sel(&mut self) -> FUNC221_IN_SEL_W { + FUNC221_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func221_in_inv_sel(&mut self) -> FUNC221_IN_INV_SEL_W { + FUNC221_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig221_in_sel(&mut self) -> SIG221_IN_SEL_W { + SIG221_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func221_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func221_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC221_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC221_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func221_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC221_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func221_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC221_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC221_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC221_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func222_in_sel_cfg.rs b/esp32p4/src/gpio/func222_in_sel_cfg.rs new file mode 100644 index 0000000000..c365ef1f9a --- /dev/null +++ b/esp32p4/src/gpio/func222_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC222_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC222_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC222_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC222_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC222_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC222_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC222_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC222_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC222_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC222_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG222_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG222_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG222_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG222_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func222_in_sel(&self) -> FUNC222_IN_SEL_R { + FUNC222_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func222_in_inv_sel(&self) -> FUNC222_IN_INV_SEL_R { + FUNC222_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig222_in_sel(&self) -> SIG222_IN_SEL_R { + SIG222_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC222_IN_SEL_CFG") + .field( + "func222_in_sel", + &format_args!("{}", self.func222_in_sel().bits()), + ) + .field( + "func222_in_inv_sel", + &format_args!("{}", self.func222_in_inv_sel().bit()), + ) + .field( + "sig222_in_sel", + &format_args!("{}", self.sig222_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func222_in_sel(&mut self) -> FUNC222_IN_SEL_W { + FUNC222_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func222_in_inv_sel(&mut self) -> FUNC222_IN_INV_SEL_W { + FUNC222_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig222_in_sel(&mut self) -> SIG222_IN_SEL_W { + SIG222_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func222_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func222_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC222_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC222_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func222_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC222_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func222_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC222_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC222_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC222_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func223_in_sel_cfg.rs b/esp32p4/src/gpio/func223_in_sel_cfg.rs new file mode 100644 index 0000000000..52c4a9182c --- /dev/null +++ b/esp32p4/src/gpio/func223_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC223_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC223_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC223_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC223_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC223_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC223_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC223_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC223_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC223_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC223_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG223_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG223_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG223_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG223_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func223_in_sel(&self) -> FUNC223_IN_SEL_R { + FUNC223_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func223_in_inv_sel(&self) -> FUNC223_IN_INV_SEL_R { + FUNC223_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig223_in_sel(&self) -> SIG223_IN_SEL_R { + SIG223_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC223_IN_SEL_CFG") + .field( + "func223_in_sel", + &format_args!("{}", self.func223_in_sel().bits()), + ) + .field( + "func223_in_inv_sel", + &format_args!("{}", self.func223_in_inv_sel().bit()), + ) + .field( + "sig223_in_sel", + &format_args!("{}", self.sig223_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func223_in_sel(&mut self) -> FUNC223_IN_SEL_W { + FUNC223_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func223_in_inv_sel(&mut self) -> FUNC223_IN_INV_SEL_W { + FUNC223_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig223_in_sel(&mut self) -> SIG223_IN_SEL_W { + SIG223_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func223_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func223_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC223_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC223_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func223_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC223_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func223_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC223_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC223_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC223_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func224_in_sel_cfg.rs b/esp32p4/src/gpio/func224_in_sel_cfg.rs new file mode 100644 index 0000000000..b2761a79ad --- /dev/null +++ b/esp32p4/src/gpio/func224_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC224_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC224_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC224_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC224_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC224_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC224_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC224_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC224_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC224_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC224_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG224_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG224_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG224_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG224_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func224_in_sel(&self) -> FUNC224_IN_SEL_R { + FUNC224_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func224_in_inv_sel(&self) -> FUNC224_IN_INV_SEL_R { + FUNC224_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig224_in_sel(&self) -> SIG224_IN_SEL_R { + SIG224_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC224_IN_SEL_CFG") + .field( + "func224_in_sel", + &format_args!("{}", self.func224_in_sel().bits()), + ) + .field( + "func224_in_inv_sel", + &format_args!("{}", self.func224_in_inv_sel().bit()), + ) + .field( + "sig224_in_sel", + &format_args!("{}", self.sig224_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func224_in_sel(&mut self) -> FUNC224_IN_SEL_W { + FUNC224_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func224_in_inv_sel(&mut self) -> FUNC224_IN_INV_SEL_W { + FUNC224_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig224_in_sel(&mut self) -> SIG224_IN_SEL_W { + SIG224_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func224_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func224_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC224_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC224_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func224_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC224_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func224_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC224_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC224_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC224_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func225_in_sel_cfg.rs b/esp32p4/src/gpio/func225_in_sel_cfg.rs new file mode 100644 index 0000000000..895933ed1d --- /dev/null +++ b/esp32p4/src/gpio/func225_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC225_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC225_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC225_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC225_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC225_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC225_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC225_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC225_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC225_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC225_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG225_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG225_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG225_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG225_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func225_in_sel(&self) -> FUNC225_IN_SEL_R { + FUNC225_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func225_in_inv_sel(&self) -> FUNC225_IN_INV_SEL_R { + FUNC225_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig225_in_sel(&self) -> SIG225_IN_SEL_R { + SIG225_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC225_IN_SEL_CFG") + .field( + "func225_in_sel", + &format_args!("{}", self.func225_in_sel().bits()), + ) + .field( + "func225_in_inv_sel", + &format_args!("{}", self.func225_in_inv_sel().bit()), + ) + .field( + "sig225_in_sel", + &format_args!("{}", self.sig225_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func225_in_sel(&mut self) -> FUNC225_IN_SEL_W { + FUNC225_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func225_in_inv_sel(&mut self) -> FUNC225_IN_INV_SEL_W { + FUNC225_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig225_in_sel(&mut self) -> SIG225_IN_SEL_W { + SIG225_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func225_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func225_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC225_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC225_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func225_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC225_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func225_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC225_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC225_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC225_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func226_in_sel_cfg.rs b/esp32p4/src/gpio/func226_in_sel_cfg.rs new file mode 100644 index 0000000000..77f46d2c70 --- /dev/null +++ b/esp32p4/src/gpio/func226_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC226_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC226_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC226_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC226_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC226_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC226_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC226_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC226_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC226_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC226_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG226_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG226_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG226_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG226_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func226_in_sel(&self) -> FUNC226_IN_SEL_R { + FUNC226_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func226_in_inv_sel(&self) -> FUNC226_IN_INV_SEL_R { + FUNC226_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig226_in_sel(&self) -> SIG226_IN_SEL_R { + SIG226_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC226_IN_SEL_CFG") + .field( + "func226_in_sel", + &format_args!("{}", self.func226_in_sel().bits()), + ) + .field( + "func226_in_inv_sel", + &format_args!("{}", self.func226_in_inv_sel().bit()), + ) + .field( + "sig226_in_sel", + &format_args!("{}", self.sig226_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func226_in_sel(&mut self) -> FUNC226_IN_SEL_W { + FUNC226_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func226_in_inv_sel(&mut self) -> FUNC226_IN_INV_SEL_W { + FUNC226_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig226_in_sel(&mut self) -> SIG226_IN_SEL_W { + SIG226_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func226_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func226_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC226_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC226_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func226_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC226_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func226_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC226_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC226_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC226_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func227_in_sel_cfg.rs b/esp32p4/src/gpio/func227_in_sel_cfg.rs new file mode 100644 index 0000000000..49849899ac --- /dev/null +++ b/esp32p4/src/gpio/func227_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC227_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC227_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC227_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC227_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC227_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC227_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC227_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC227_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC227_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC227_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG227_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG227_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG227_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG227_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func227_in_sel(&self) -> FUNC227_IN_SEL_R { + FUNC227_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func227_in_inv_sel(&self) -> FUNC227_IN_INV_SEL_R { + FUNC227_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig227_in_sel(&self) -> SIG227_IN_SEL_R { + SIG227_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC227_IN_SEL_CFG") + .field( + "func227_in_sel", + &format_args!("{}", self.func227_in_sel().bits()), + ) + .field( + "func227_in_inv_sel", + &format_args!("{}", self.func227_in_inv_sel().bit()), + ) + .field( + "sig227_in_sel", + &format_args!("{}", self.sig227_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func227_in_sel(&mut self) -> FUNC227_IN_SEL_W { + FUNC227_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func227_in_inv_sel(&mut self) -> FUNC227_IN_INV_SEL_W { + FUNC227_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig227_in_sel(&mut self) -> SIG227_IN_SEL_W { + SIG227_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func227_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func227_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC227_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC227_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func227_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC227_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func227_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC227_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC227_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC227_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func228_in_sel_cfg.rs b/esp32p4/src/gpio/func228_in_sel_cfg.rs new file mode 100644 index 0000000000..0aa94c1d22 --- /dev/null +++ b/esp32p4/src/gpio/func228_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC228_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC228_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC228_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC228_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC228_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC228_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC228_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC228_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC228_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC228_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG228_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG228_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG228_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG228_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func228_in_sel(&self) -> FUNC228_IN_SEL_R { + FUNC228_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func228_in_inv_sel(&self) -> FUNC228_IN_INV_SEL_R { + FUNC228_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig228_in_sel(&self) -> SIG228_IN_SEL_R { + SIG228_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC228_IN_SEL_CFG") + .field( + "func228_in_sel", + &format_args!("{}", self.func228_in_sel().bits()), + ) + .field( + "func228_in_inv_sel", + &format_args!("{}", self.func228_in_inv_sel().bit()), + ) + .field( + "sig228_in_sel", + &format_args!("{}", self.sig228_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func228_in_sel(&mut self) -> FUNC228_IN_SEL_W { + FUNC228_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func228_in_inv_sel(&mut self) -> FUNC228_IN_INV_SEL_W { + FUNC228_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig228_in_sel(&mut self) -> SIG228_IN_SEL_W { + SIG228_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func228_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func228_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC228_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC228_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func228_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC228_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func228_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC228_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC228_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC228_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func229_in_sel_cfg.rs b/esp32p4/src/gpio/func229_in_sel_cfg.rs new file mode 100644 index 0000000000..5656afc583 --- /dev/null +++ b/esp32p4/src/gpio/func229_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC229_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC229_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC229_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC229_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC229_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC229_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC229_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC229_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC229_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC229_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG229_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG229_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG229_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG229_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func229_in_sel(&self) -> FUNC229_IN_SEL_R { + FUNC229_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func229_in_inv_sel(&self) -> FUNC229_IN_INV_SEL_R { + FUNC229_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig229_in_sel(&self) -> SIG229_IN_SEL_R { + SIG229_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC229_IN_SEL_CFG") + .field( + "func229_in_sel", + &format_args!("{}", self.func229_in_sel().bits()), + ) + .field( + "func229_in_inv_sel", + &format_args!("{}", self.func229_in_inv_sel().bit()), + ) + .field( + "sig229_in_sel", + &format_args!("{}", self.sig229_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func229_in_sel(&mut self) -> FUNC229_IN_SEL_W { + FUNC229_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func229_in_inv_sel(&mut self) -> FUNC229_IN_INV_SEL_W { + FUNC229_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig229_in_sel(&mut self) -> SIG229_IN_SEL_W { + SIG229_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func229_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func229_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC229_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC229_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func229_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC229_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func229_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC229_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC229_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC229_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func22_in_sel_cfg.rs b/esp32p4/src/gpio/func22_in_sel_cfg.rs new file mode 100644 index 0000000000..b365f3c478 --- /dev/null +++ b/esp32p4/src/gpio/func22_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC22_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC22_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC22_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC22_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC22_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC22_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC22_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC22_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC22_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC22_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG22_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG22_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG22_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG22_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func22_in_sel(&self) -> FUNC22_IN_SEL_R { + FUNC22_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func22_in_inv_sel(&self) -> FUNC22_IN_INV_SEL_R { + FUNC22_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig22_in_sel(&self) -> SIG22_IN_SEL_R { + SIG22_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC22_IN_SEL_CFG") + .field( + "func22_in_sel", + &format_args!("{}", self.func22_in_sel().bits()), + ) + .field( + "func22_in_inv_sel", + &format_args!("{}", self.func22_in_inv_sel().bit()), + ) + .field( + "sig22_in_sel", + &format_args!("{}", self.sig22_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func22_in_sel(&mut self) -> FUNC22_IN_SEL_W { + FUNC22_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func22_in_inv_sel(&mut self) -> FUNC22_IN_INV_SEL_W { + FUNC22_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig22_in_sel(&mut self) -> SIG22_IN_SEL_W { + SIG22_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func22_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func22_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC22_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC22_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func22_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC22_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func22_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC22_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC22_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC22_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func230_in_sel_cfg.rs b/esp32p4/src/gpio/func230_in_sel_cfg.rs new file mode 100644 index 0000000000..50dc803223 --- /dev/null +++ b/esp32p4/src/gpio/func230_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC230_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC230_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC230_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC230_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC230_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC230_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC230_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC230_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC230_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC230_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG230_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG230_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG230_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG230_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func230_in_sel(&self) -> FUNC230_IN_SEL_R { + FUNC230_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func230_in_inv_sel(&self) -> FUNC230_IN_INV_SEL_R { + FUNC230_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig230_in_sel(&self) -> SIG230_IN_SEL_R { + SIG230_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC230_IN_SEL_CFG") + .field( + "func230_in_sel", + &format_args!("{}", self.func230_in_sel().bits()), + ) + .field( + "func230_in_inv_sel", + &format_args!("{}", self.func230_in_inv_sel().bit()), + ) + .field( + "sig230_in_sel", + &format_args!("{}", self.sig230_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func230_in_sel(&mut self) -> FUNC230_IN_SEL_W { + FUNC230_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func230_in_inv_sel(&mut self) -> FUNC230_IN_INV_SEL_W { + FUNC230_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig230_in_sel(&mut self) -> SIG230_IN_SEL_W { + SIG230_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func230_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func230_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC230_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC230_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func230_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC230_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func230_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC230_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC230_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC230_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func231_in_sel_cfg.rs b/esp32p4/src/gpio/func231_in_sel_cfg.rs new file mode 100644 index 0000000000..87a9a4a65d --- /dev/null +++ b/esp32p4/src/gpio/func231_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC231_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC231_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC231_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC231_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC231_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC231_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC231_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC231_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC231_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC231_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG231_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG231_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG231_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG231_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func231_in_sel(&self) -> FUNC231_IN_SEL_R { + FUNC231_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func231_in_inv_sel(&self) -> FUNC231_IN_INV_SEL_R { + FUNC231_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig231_in_sel(&self) -> SIG231_IN_SEL_R { + SIG231_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC231_IN_SEL_CFG") + .field( + "func231_in_sel", + &format_args!("{}", self.func231_in_sel().bits()), + ) + .field( + "func231_in_inv_sel", + &format_args!("{}", self.func231_in_inv_sel().bit()), + ) + .field( + "sig231_in_sel", + &format_args!("{}", self.sig231_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func231_in_sel(&mut self) -> FUNC231_IN_SEL_W { + FUNC231_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func231_in_inv_sel(&mut self) -> FUNC231_IN_INV_SEL_W { + FUNC231_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig231_in_sel(&mut self) -> SIG231_IN_SEL_W { + SIG231_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func231_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func231_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC231_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC231_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func231_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC231_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func231_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC231_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC231_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC231_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func232_in_sel_cfg.rs b/esp32p4/src/gpio/func232_in_sel_cfg.rs new file mode 100644 index 0000000000..802bcb46d8 --- /dev/null +++ b/esp32p4/src/gpio/func232_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC232_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC232_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC232_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC232_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC232_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC232_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC232_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC232_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC232_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC232_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG232_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG232_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG232_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG232_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func232_in_sel(&self) -> FUNC232_IN_SEL_R { + FUNC232_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func232_in_inv_sel(&self) -> FUNC232_IN_INV_SEL_R { + FUNC232_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig232_in_sel(&self) -> SIG232_IN_SEL_R { + SIG232_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC232_IN_SEL_CFG") + .field( + "func232_in_sel", + &format_args!("{}", self.func232_in_sel().bits()), + ) + .field( + "func232_in_inv_sel", + &format_args!("{}", self.func232_in_inv_sel().bit()), + ) + .field( + "sig232_in_sel", + &format_args!("{}", self.sig232_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func232_in_sel(&mut self) -> FUNC232_IN_SEL_W { + FUNC232_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func232_in_inv_sel(&mut self) -> FUNC232_IN_INV_SEL_W { + FUNC232_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig232_in_sel(&mut self) -> SIG232_IN_SEL_W { + SIG232_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func232_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func232_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC232_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC232_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func232_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC232_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func232_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC232_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC232_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC232_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func233_in_sel_cfg.rs b/esp32p4/src/gpio/func233_in_sel_cfg.rs new file mode 100644 index 0000000000..386bcf2407 --- /dev/null +++ b/esp32p4/src/gpio/func233_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC233_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC233_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC233_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC233_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC233_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC233_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC233_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC233_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC233_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC233_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG233_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG233_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG233_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG233_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func233_in_sel(&self) -> FUNC233_IN_SEL_R { + FUNC233_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func233_in_inv_sel(&self) -> FUNC233_IN_INV_SEL_R { + FUNC233_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig233_in_sel(&self) -> SIG233_IN_SEL_R { + SIG233_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC233_IN_SEL_CFG") + .field( + "func233_in_sel", + &format_args!("{}", self.func233_in_sel().bits()), + ) + .field( + "func233_in_inv_sel", + &format_args!("{}", self.func233_in_inv_sel().bit()), + ) + .field( + "sig233_in_sel", + &format_args!("{}", self.sig233_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func233_in_sel(&mut self) -> FUNC233_IN_SEL_W { + FUNC233_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func233_in_inv_sel(&mut self) -> FUNC233_IN_INV_SEL_W { + FUNC233_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig233_in_sel(&mut self) -> SIG233_IN_SEL_W { + SIG233_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func233_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func233_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC233_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC233_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func233_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC233_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func233_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC233_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC233_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC233_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func234_in_sel_cfg.rs b/esp32p4/src/gpio/func234_in_sel_cfg.rs new file mode 100644 index 0000000000..1f055bf74a --- /dev/null +++ b/esp32p4/src/gpio/func234_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC234_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC234_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC234_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC234_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC234_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC234_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC234_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC234_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC234_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC234_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG234_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG234_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG234_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG234_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func234_in_sel(&self) -> FUNC234_IN_SEL_R { + FUNC234_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func234_in_inv_sel(&self) -> FUNC234_IN_INV_SEL_R { + FUNC234_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig234_in_sel(&self) -> SIG234_IN_SEL_R { + SIG234_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC234_IN_SEL_CFG") + .field( + "func234_in_sel", + &format_args!("{}", self.func234_in_sel().bits()), + ) + .field( + "func234_in_inv_sel", + &format_args!("{}", self.func234_in_inv_sel().bit()), + ) + .field( + "sig234_in_sel", + &format_args!("{}", self.sig234_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func234_in_sel(&mut self) -> FUNC234_IN_SEL_W { + FUNC234_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func234_in_inv_sel(&mut self) -> FUNC234_IN_INV_SEL_W { + FUNC234_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig234_in_sel(&mut self) -> SIG234_IN_SEL_W { + SIG234_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func234_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func234_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC234_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC234_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func234_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC234_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func234_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC234_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC234_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC234_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func235_in_sel_cfg.rs b/esp32p4/src/gpio/func235_in_sel_cfg.rs new file mode 100644 index 0000000000..da058f47e8 --- /dev/null +++ b/esp32p4/src/gpio/func235_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC235_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC235_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC235_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC235_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC235_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC235_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC235_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC235_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC235_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC235_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG235_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG235_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG235_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG235_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func235_in_sel(&self) -> FUNC235_IN_SEL_R { + FUNC235_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func235_in_inv_sel(&self) -> FUNC235_IN_INV_SEL_R { + FUNC235_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig235_in_sel(&self) -> SIG235_IN_SEL_R { + SIG235_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC235_IN_SEL_CFG") + .field( + "func235_in_sel", + &format_args!("{}", self.func235_in_sel().bits()), + ) + .field( + "func235_in_inv_sel", + &format_args!("{}", self.func235_in_inv_sel().bit()), + ) + .field( + "sig235_in_sel", + &format_args!("{}", self.sig235_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func235_in_sel(&mut self) -> FUNC235_IN_SEL_W { + FUNC235_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func235_in_inv_sel(&mut self) -> FUNC235_IN_INV_SEL_W { + FUNC235_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig235_in_sel(&mut self) -> SIG235_IN_SEL_W { + SIG235_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func235_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func235_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC235_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC235_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func235_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC235_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func235_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC235_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC235_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC235_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func236_in_sel_cfg.rs b/esp32p4/src/gpio/func236_in_sel_cfg.rs new file mode 100644 index 0000000000..afdecf7857 --- /dev/null +++ b/esp32p4/src/gpio/func236_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC236_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC236_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC236_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC236_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC236_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC236_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC236_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC236_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC236_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC236_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG236_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG236_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG236_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG236_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func236_in_sel(&self) -> FUNC236_IN_SEL_R { + FUNC236_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func236_in_inv_sel(&self) -> FUNC236_IN_INV_SEL_R { + FUNC236_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig236_in_sel(&self) -> SIG236_IN_SEL_R { + SIG236_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC236_IN_SEL_CFG") + .field( + "func236_in_sel", + &format_args!("{}", self.func236_in_sel().bits()), + ) + .field( + "func236_in_inv_sel", + &format_args!("{}", self.func236_in_inv_sel().bit()), + ) + .field( + "sig236_in_sel", + &format_args!("{}", self.sig236_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func236_in_sel(&mut self) -> FUNC236_IN_SEL_W { + FUNC236_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func236_in_inv_sel(&mut self) -> FUNC236_IN_INV_SEL_W { + FUNC236_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig236_in_sel(&mut self) -> SIG236_IN_SEL_W { + SIG236_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func236_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func236_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC236_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC236_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func236_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC236_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func236_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC236_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC236_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC236_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func237_in_sel_cfg.rs b/esp32p4/src/gpio/func237_in_sel_cfg.rs new file mode 100644 index 0000000000..8f3477b155 --- /dev/null +++ b/esp32p4/src/gpio/func237_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC237_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC237_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC237_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC237_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC237_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC237_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC237_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC237_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC237_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC237_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG237_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG237_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG237_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG237_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func237_in_sel(&self) -> FUNC237_IN_SEL_R { + FUNC237_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func237_in_inv_sel(&self) -> FUNC237_IN_INV_SEL_R { + FUNC237_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig237_in_sel(&self) -> SIG237_IN_SEL_R { + SIG237_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC237_IN_SEL_CFG") + .field( + "func237_in_sel", + &format_args!("{}", self.func237_in_sel().bits()), + ) + .field( + "func237_in_inv_sel", + &format_args!("{}", self.func237_in_inv_sel().bit()), + ) + .field( + "sig237_in_sel", + &format_args!("{}", self.sig237_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func237_in_sel(&mut self) -> FUNC237_IN_SEL_W { + FUNC237_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func237_in_inv_sel(&mut self) -> FUNC237_IN_INV_SEL_W { + FUNC237_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig237_in_sel(&mut self) -> SIG237_IN_SEL_W { + SIG237_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func237_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func237_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC237_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC237_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func237_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC237_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func237_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC237_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC237_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC237_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func238_in_sel_cfg.rs b/esp32p4/src/gpio/func238_in_sel_cfg.rs new file mode 100644 index 0000000000..e961c7396b --- /dev/null +++ b/esp32p4/src/gpio/func238_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC238_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC238_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC238_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC238_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC238_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC238_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC238_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC238_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC238_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC238_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG238_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG238_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG238_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG238_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func238_in_sel(&self) -> FUNC238_IN_SEL_R { + FUNC238_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func238_in_inv_sel(&self) -> FUNC238_IN_INV_SEL_R { + FUNC238_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig238_in_sel(&self) -> SIG238_IN_SEL_R { + SIG238_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC238_IN_SEL_CFG") + .field( + "func238_in_sel", + &format_args!("{}", self.func238_in_sel().bits()), + ) + .field( + "func238_in_inv_sel", + &format_args!("{}", self.func238_in_inv_sel().bit()), + ) + .field( + "sig238_in_sel", + &format_args!("{}", self.sig238_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func238_in_sel(&mut self) -> FUNC238_IN_SEL_W { + FUNC238_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func238_in_inv_sel(&mut self) -> FUNC238_IN_INV_SEL_W { + FUNC238_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig238_in_sel(&mut self) -> SIG238_IN_SEL_W { + SIG238_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func238_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func238_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC238_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC238_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func238_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC238_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func238_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC238_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC238_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC238_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func239_in_sel_cfg.rs b/esp32p4/src/gpio/func239_in_sel_cfg.rs new file mode 100644 index 0000000000..9f9d4d9672 --- /dev/null +++ b/esp32p4/src/gpio/func239_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC239_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC239_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC239_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC239_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC239_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC239_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC239_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC239_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC239_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC239_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG239_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG239_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG239_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG239_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func239_in_sel(&self) -> FUNC239_IN_SEL_R { + FUNC239_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func239_in_inv_sel(&self) -> FUNC239_IN_INV_SEL_R { + FUNC239_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig239_in_sel(&self) -> SIG239_IN_SEL_R { + SIG239_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC239_IN_SEL_CFG") + .field( + "func239_in_sel", + &format_args!("{}", self.func239_in_sel().bits()), + ) + .field( + "func239_in_inv_sel", + &format_args!("{}", self.func239_in_inv_sel().bit()), + ) + .field( + "sig239_in_sel", + &format_args!("{}", self.sig239_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func239_in_sel(&mut self) -> FUNC239_IN_SEL_W { + FUNC239_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func239_in_inv_sel(&mut self) -> FUNC239_IN_INV_SEL_W { + FUNC239_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig239_in_sel(&mut self) -> SIG239_IN_SEL_W { + SIG239_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func239_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func239_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC239_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC239_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func239_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC239_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func239_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC239_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC239_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC239_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func23_in_sel_cfg.rs b/esp32p4/src/gpio/func23_in_sel_cfg.rs new file mode 100644 index 0000000000..fe6108f32b --- /dev/null +++ b/esp32p4/src/gpio/func23_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC23_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC23_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC23_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC23_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC23_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC23_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC23_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC23_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC23_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC23_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG23_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG23_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG23_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG23_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func23_in_sel(&self) -> FUNC23_IN_SEL_R { + FUNC23_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func23_in_inv_sel(&self) -> FUNC23_IN_INV_SEL_R { + FUNC23_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig23_in_sel(&self) -> SIG23_IN_SEL_R { + SIG23_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC23_IN_SEL_CFG") + .field( + "func23_in_sel", + &format_args!("{}", self.func23_in_sel().bits()), + ) + .field( + "func23_in_inv_sel", + &format_args!("{}", self.func23_in_inv_sel().bit()), + ) + .field( + "sig23_in_sel", + &format_args!("{}", self.sig23_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func23_in_sel(&mut self) -> FUNC23_IN_SEL_W { + FUNC23_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func23_in_inv_sel(&mut self) -> FUNC23_IN_INV_SEL_W { + FUNC23_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig23_in_sel(&mut self) -> SIG23_IN_SEL_W { + SIG23_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func23_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func23_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC23_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC23_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func23_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC23_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func23_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC23_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC23_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC23_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func240_in_sel_cfg.rs b/esp32p4/src/gpio/func240_in_sel_cfg.rs new file mode 100644 index 0000000000..8d188176df --- /dev/null +++ b/esp32p4/src/gpio/func240_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC240_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC240_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC240_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC240_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC240_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC240_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC240_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC240_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC240_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC240_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG240_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG240_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG240_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG240_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func240_in_sel(&self) -> FUNC240_IN_SEL_R { + FUNC240_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func240_in_inv_sel(&self) -> FUNC240_IN_INV_SEL_R { + FUNC240_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig240_in_sel(&self) -> SIG240_IN_SEL_R { + SIG240_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC240_IN_SEL_CFG") + .field( + "func240_in_sel", + &format_args!("{}", self.func240_in_sel().bits()), + ) + .field( + "func240_in_inv_sel", + &format_args!("{}", self.func240_in_inv_sel().bit()), + ) + .field( + "sig240_in_sel", + &format_args!("{}", self.sig240_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func240_in_sel(&mut self) -> FUNC240_IN_SEL_W { + FUNC240_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func240_in_inv_sel(&mut self) -> FUNC240_IN_INV_SEL_W { + FUNC240_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig240_in_sel(&mut self) -> SIG240_IN_SEL_W { + SIG240_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func240_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func240_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC240_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC240_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func240_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC240_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func240_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC240_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC240_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC240_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func241_in_sel_cfg.rs b/esp32p4/src/gpio/func241_in_sel_cfg.rs new file mode 100644 index 0000000000..b564ffa512 --- /dev/null +++ b/esp32p4/src/gpio/func241_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC241_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC241_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC241_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC241_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC241_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC241_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC241_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC241_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC241_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC241_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG241_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG241_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG241_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG241_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func241_in_sel(&self) -> FUNC241_IN_SEL_R { + FUNC241_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func241_in_inv_sel(&self) -> FUNC241_IN_INV_SEL_R { + FUNC241_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig241_in_sel(&self) -> SIG241_IN_SEL_R { + SIG241_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC241_IN_SEL_CFG") + .field( + "func241_in_sel", + &format_args!("{}", self.func241_in_sel().bits()), + ) + .field( + "func241_in_inv_sel", + &format_args!("{}", self.func241_in_inv_sel().bit()), + ) + .field( + "sig241_in_sel", + &format_args!("{}", self.sig241_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func241_in_sel(&mut self) -> FUNC241_IN_SEL_W { + FUNC241_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func241_in_inv_sel(&mut self) -> FUNC241_IN_INV_SEL_W { + FUNC241_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig241_in_sel(&mut self) -> SIG241_IN_SEL_W { + SIG241_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func241_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func241_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC241_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC241_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func241_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC241_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func241_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC241_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC241_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC241_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func242_in_sel_cfg.rs b/esp32p4/src/gpio/func242_in_sel_cfg.rs new file mode 100644 index 0000000000..2a75d90b4e --- /dev/null +++ b/esp32p4/src/gpio/func242_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC242_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC242_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC242_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC242_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC242_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC242_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC242_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC242_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC242_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC242_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG242_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG242_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG242_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG242_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func242_in_sel(&self) -> FUNC242_IN_SEL_R { + FUNC242_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func242_in_inv_sel(&self) -> FUNC242_IN_INV_SEL_R { + FUNC242_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig242_in_sel(&self) -> SIG242_IN_SEL_R { + SIG242_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC242_IN_SEL_CFG") + .field( + "func242_in_sel", + &format_args!("{}", self.func242_in_sel().bits()), + ) + .field( + "func242_in_inv_sel", + &format_args!("{}", self.func242_in_inv_sel().bit()), + ) + .field( + "sig242_in_sel", + &format_args!("{}", self.sig242_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func242_in_sel(&mut self) -> FUNC242_IN_SEL_W { + FUNC242_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func242_in_inv_sel(&mut self) -> FUNC242_IN_INV_SEL_W { + FUNC242_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig242_in_sel(&mut self) -> SIG242_IN_SEL_W { + SIG242_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func242_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func242_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC242_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC242_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func242_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC242_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func242_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC242_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC242_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC242_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func243_in_sel_cfg.rs b/esp32p4/src/gpio/func243_in_sel_cfg.rs new file mode 100644 index 0000000000..fb44a9e88b --- /dev/null +++ b/esp32p4/src/gpio/func243_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC243_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC243_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC243_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC243_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC243_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC243_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC243_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC243_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC243_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC243_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG243_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG243_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG243_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG243_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func243_in_sel(&self) -> FUNC243_IN_SEL_R { + FUNC243_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func243_in_inv_sel(&self) -> FUNC243_IN_INV_SEL_R { + FUNC243_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig243_in_sel(&self) -> SIG243_IN_SEL_R { + SIG243_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC243_IN_SEL_CFG") + .field( + "func243_in_sel", + &format_args!("{}", self.func243_in_sel().bits()), + ) + .field( + "func243_in_inv_sel", + &format_args!("{}", self.func243_in_inv_sel().bit()), + ) + .field( + "sig243_in_sel", + &format_args!("{}", self.sig243_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func243_in_sel(&mut self) -> FUNC243_IN_SEL_W { + FUNC243_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func243_in_inv_sel(&mut self) -> FUNC243_IN_INV_SEL_W { + FUNC243_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig243_in_sel(&mut self) -> SIG243_IN_SEL_W { + SIG243_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func243_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func243_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC243_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC243_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func243_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC243_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func243_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC243_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC243_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC243_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func244_in_sel_cfg.rs b/esp32p4/src/gpio/func244_in_sel_cfg.rs new file mode 100644 index 0000000000..019375e956 --- /dev/null +++ b/esp32p4/src/gpio/func244_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC244_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC244_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC244_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC244_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC244_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC244_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC244_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC244_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC244_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC244_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG244_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG244_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG244_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG244_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func244_in_sel(&self) -> FUNC244_IN_SEL_R { + FUNC244_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func244_in_inv_sel(&self) -> FUNC244_IN_INV_SEL_R { + FUNC244_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig244_in_sel(&self) -> SIG244_IN_SEL_R { + SIG244_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC244_IN_SEL_CFG") + .field( + "func244_in_sel", + &format_args!("{}", self.func244_in_sel().bits()), + ) + .field( + "func244_in_inv_sel", + &format_args!("{}", self.func244_in_inv_sel().bit()), + ) + .field( + "sig244_in_sel", + &format_args!("{}", self.sig244_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func244_in_sel(&mut self) -> FUNC244_IN_SEL_W { + FUNC244_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func244_in_inv_sel(&mut self) -> FUNC244_IN_INV_SEL_W { + FUNC244_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig244_in_sel(&mut self) -> SIG244_IN_SEL_W { + SIG244_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func244_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func244_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC244_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC244_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func244_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC244_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func244_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC244_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC244_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC244_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func245_in_sel_cfg.rs b/esp32p4/src/gpio/func245_in_sel_cfg.rs new file mode 100644 index 0000000000..fd8656cb31 --- /dev/null +++ b/esp32p4/src/gpio/func245_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC245_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC245_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC245_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC245_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC245_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC245_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC245_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC245_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC245_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC245_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG245_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG245_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG245_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG245_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func245_in_sel(&self) -> FUNC245_IN_SEL_R { + FUNC245_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func245_in_inv_sel(&self) -> FUNC245_IN_INV_SEL_R { + FUNC245_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig245_in_sel(&self) -> SIG245_IN_SEL_R { + SIG245_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC245_IN_SEL_CFG") + .field( + "func245_in_sel", + &format_args!("{}", self.func245_in_sel().bits()), + ) + .field( + "func245_in_inv_sel", + &format_args!("{}", self.func245_in_inv_sel().bit()), + ) + .field( + "sig245_in_sel", + &format_args!("{}", self.sig245_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func245_in_sel(&mut self) -> FUNC245_IN_SEL_W { + FUNC245_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func245_in_inv_sel(&mut self) -> FUNC245_IN_INV_SEL_W { + FUNC245_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig245_in_sel(&mut self) -> SIG245_IN_SEL_W { + SIG245_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func245_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func245_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC245_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC245_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func245_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC245_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func245_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC245_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC245_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC245_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func246_in_sel_cfg.rs b/esp32p4/src/gpio/func246_in_sel_cfg.rs new file mode 100644 index 0000000000..e8c2df11e1 --- /dev/null +++ b/esp32p4/src/gpio/func246_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC246_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC246_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC246_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC246_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC246_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC246_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC246_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC246_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC246_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC246_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG246_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG246_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG246_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG246_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func246_in_sel(&self) -> FUNC246_IN_SEL_R { + FUNC246_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func246_in_inv_sel(&self) -> FUNC246_IN_INV_SEL_R { + FUNC246_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig246_in_sel(&self) -> SIG246_IN_SEL_R { + SIG246_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC246_IN_SEL_CFG") + .field( + "func246_in_sel", + &format_args!("{}", self.func246_in_sel().bits()), + ) + .field( + "func246_in_inv_sel", + &format_args!("{}", self.func246_in_inv_sel().bit()), + ) + .field( + "sig246_in_sel", + &format_args!("{}", self.sig246_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func246_in_sel(&mut self) -> FUNC246_IN_SEL_W { + FUNC246_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func246_in_inv_sel(&mut self) -> FUNC246_IN_INV_SEL_W { + FUNC246_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig246_in_sel(&mut self) -> SIG246_IN_SEL_W { + SIG246_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func246_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func246_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC246_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC246_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func246_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC246_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func246_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC246_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC246_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC246_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func247_in_sel_cfg.rs b/esp32p4/src/gpio/func247_in_sel_cfg.rs new file mode 100644 index 0000000000..1070fc289e --- /dev/null +++ b/esp32p4/src/gpio/func247_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC247_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC247_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC247_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC247_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC247_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC247_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC247_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC247_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC247_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC247_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG247_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG247_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG247_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG247_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func247_in_sel(&self) -> FUNC247_IN_SEL_R { + FUNC247_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func247_in_inv_sel(&self) -> FUNC247_IN_INV_SEL_R { + FUNC247_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig247_in_sel(&self) -> SIG247_IN_SEL_R { + SIG247_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC247_IN_SEL_CFG") + .field( + "func247_in_sel", + &format_args!("{}", self.func247_in_sel().bits()), + ) + .field( + "func247_in_inv_sel", + &format_args!("{}", self.func247_in_inv_sel().bit()), + ) + .field( + "sig247_in_sel", + &format_args!("{}", self.sig247_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func247_in_sel(&mut self) -> FUNC247_IN_SEL_W { + FUNC247_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func247_in_inv_sel(&mut self) -> FUNC247_IN_INV_SEL_W { + FUNC247_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig247_in_sel(&mut self) -> SIG247_IN_SEL_W { + SIG247_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func247_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func247_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC247_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC247_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func247_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC247_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func247_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC247_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC247_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC247_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func248_in_sel_cfg.rs b/esp32p4/src/gpio/func248_in_sel_cfg.rs new file mode 100644 index 0000000000..92a3812600 --- /dev/null +++ b/esp32p4/src/gpio/func248_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC248_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC248_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC248_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC248_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC248_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC248_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC248_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC248_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC248_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC248_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG248_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG248_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG248_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG248_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func248_in_sel(&self) -> FUNC248_IN_SEL_R { + FUNC248_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func248_in_inv_sel(&self) -> FUNC248_IN_INV_SEL_R { + FUNC248_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig248_in_sel(&self) -> SIG248_IN_SEL_R { + SIG248_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC248_IN_SEL_CFG") + .field( + "func248_in_sel", + &format_args!("{}", self.func248_in_sel().bits()), + ) + .field( + "func248_in_inv_sel", + &format_args!("{}", self.func248_in_inv_sel().bit()), + ) + .field( + "sig248_in_sel", + &format_args!("{}", self.sig248_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func248_in_sel(&mut self) -> FUNC248_IN_SEL_W { + FUNC248_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func248_in_inv_sel(&mut self) -> FUNC248_IN_INV_SEL_W { + FUNC248_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig248_in_sel(&mut self) -> SIG248_IN_SEL_W { + SIG248_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func248_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func248_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC248_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC248_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func248_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC248_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func248_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC248_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC248_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC248_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func249_in_sel_cfg.rs b/esp32p4/src/gpio/func249_in_sel_cfg.rs new file mode 100644 index 0000000000..8af98da754 --- /dev/null +++ b/esp32p4/src/gpio/func249_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC249_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC249_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC249_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC249_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC249_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC249_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC249_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC249_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC249_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC249_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG249_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG249_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG249_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG249_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func249_in_sel(&self) -> FUNC249_IN_SEL_R { + FUNC249_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func249_in_inv_sel(&self) -> FUNC249_IN_INV_SEL_R { + FUNC249_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig249_in_sel(&self) -> SIG249_IN_SEL_R { + SIG249_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC249_IN_SEL_CFG") + .field( + "func249_in_sel", + &format_args!("{}", self.func249_in_sel().bits()), + ) + .field( + "func249_in_inv_sel", + &format_args!("{}", self.func249_in_inv_sel().bit()), + ) + .field( + "sig249_in_sel", + &format_args!("{}", self.sig249_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func249_in_sel(&mut self) -> FUNC249_IN_SEL_W { + FUNC249_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func249_in_inv_sel(&mut self) -> FUNC249_IN_INV_SEL_W { + FUNC249_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig249_in_sel(&mut self) -> SIG249_IN_SEL_W { + SIG249_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func249_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func249_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC249_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC249_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func249_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC249_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func249_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC249_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC249_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC249_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func24_in_sel_cfg.rs b/esp32p4/src/gpio/func24_in_sel_cfg.rs new file mode 100644 index 0000000000..81d9645c81 --- /dev/null +++ b/esp32p4/src/gpio/func24_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC24_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC24_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC24_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC24_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC24_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC24_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC24_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC24_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC24_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC24_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG24_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG24_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG24_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG24_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func24_in_sel(&self) -> FUNC24_IN_SEL_R { + FUNC24_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func24_in_inv_sel(&self) -> FUNC24_IN_INV_SEL_R { + FUNC24_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig24_in_sel(&self) -> SIG24_IN_SEL_R { + SIG24_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC24_IN_SEL_CFG") + .field( + "func24_in_sel", + &format_args!("{}", self.func24_in_sel().bits()), + ) + .field( + "func24_in_inv_sel", + &format_args!("{}", self.func24_in_inv_sel().bit()), + ) + .field( + "sig24_in_sel", + &format_args!("{}", self.sig24_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func24_in_sel(&mut self) -> FUNC24_IN_SEL_W { + FUNC24_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func24_in_inv_sel(&mut self) -> FUNC24_IN_INV_SEL_W { + FUNC24_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig24_in_sel(&mut self) -> SIG24_IN_SEL_W { + SIG24_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func24_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func24_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC24_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC24_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func24_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC24_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func24_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC24_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC24_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC24_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func250_in_sel_cfg.rs b/esp32p4/src/gpio/func250_in_sel_cfg.rs new file mode 100644 index 0000000000..f8aebe703e --- /dev/null +++ b/esp32p4/src/gpio/func250_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC250_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC250_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC250_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC250_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC250_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC250_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC250_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC250_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC250_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC250_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG250_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG250_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG250_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG250_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func250_in_sel(&self) -> FUNC250_IN_SEL_R { + FUNC250_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func250_in_inv_sel(&self) -> FUNC250_IN_INV_SEL_R { + FUNC250_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig250_in_sel(&self) -> SIG250_IN_SEL_R { + SIG250_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC250_IN_SEL_CFG") + .field( + "func250_in_sel", + &format_args!("{}", self.func250_in_sel().bits()), + ) + .field( + "func250_in_inv_sel", + &format_args!("{}", self.func250_in_inv_sel().bit()), + ) + .field( + "sig250_in_sel", + &format_args!("{}", self.sig250_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func250_in_sel(&mut self) -> FUNC250_IN_SEL_W { + FUNC250_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func250_in_inv_sel(&mut self) -> FUNC250_IN_INV_SEL_W { + FUNC250_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig250_in_sel(&mut self) -> SIG250_IN_SEL_W { + SIG250_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func250_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func250_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC250_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC250_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func250_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC250_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func250_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC250_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC250_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC250_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func251_in_sel_cfg.rs b/esp32p4/src/gpio/func251_in_sel_cfg.rs new file mode 100644 index 0000000000..6744f0b15d --- /dev/null +++ b/esp32p4/src/gpio/func251_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC251_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC251_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC251_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC251_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC251_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC251_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC251_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC251_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC251_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC251_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG251_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG251_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG251_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG251_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func251_in_sel(&self) -> FUNC251_IN_SEL_R { + FUNC251_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func251_in_inv_sel(&self) -> FUNC251_IN_INV_SEL_R { + FUNC251_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig251_in_sel(&self) -> SIG251_IN_SEL_R { + SIG251_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC251_IN_SEL_CFG") + .field( + "func251_in_sel", + &format_args!("{}", self.func251_in_sel().bits()), + ) + .field( + "func251_in_inv_sel", + &format_args!("{}", self.func251_in_inv_sel().bit()), + ) + .field( + "sig251_in_sel", + &format_args!("{}", self.sig251_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func251_in_sel(&mut self) -> FUNC251_IN_SEL_W { + FUNC251_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func251_in_inv_sel(&mut self) -> FUNC251_IN_INV_SEL_W { + FUNC251_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig251_in_sel(&mut self) -> SIG251_IN_SEL_W { + SIG251_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func251_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func251_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC251_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC251_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func251_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC251_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func251_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC251_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC251_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC251_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func252_in_sel_cfg.rs b/esp32p4/src/gpio/func252_in_sel_cfg.rs new file mode 100644 index 0000000000..9fd13284a9 --- /dev/null +++ b/esp32p4/src/gpio/func252_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC252_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC252_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC252_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC252_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC252_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC252_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC252_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC252_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC252_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC252_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG252_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG252_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG252_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG252_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func252_in_sel(&self) -> FUNC252_IN_SEL_R { + FUNC252_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func252_in_inv_sel(&self) -> FUNC252_IN_INV_SEL_R { + FUNC252_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig252_in_sel(&self) -> SIG252_IN_SEL_R { + SIG252_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC252_IN_SEL_CFG") + .field( + "func252_in_sel", + &format_args!("{}", self.func252_in_sel().bits()), + ) + .field( + "func252_in_inv_sel", + &format_args!("{}", self.func252_in_inv_sel().bit()), + ) + .field( + "sig252_in_sel", + &format_args!("{}", self.sig252_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func252_in_sel(&mut self) -> FUNC252_IN_SEL_W { + FUNC252_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func252_in_inv_sel(&mut self) -> FUNC252_IN_INV_SEL_W { + FUNC252_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig252_in_sel(&mut self) -> SIG252_IN_SEL_W { + SIG252_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func252_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func252_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC252_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC252_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func252_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC252_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func252_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC252_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC252_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC252_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func253_in_sel_cfg.rs b/esp32p4/src/gpio/func253_in_sel_cfg.rs new file mode 100644 index 0000000000..2dac53f330 --- /dev/null +++ b/esp32p4/src/gpio/func253_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC253_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC253_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC253_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC253_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC253_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC253_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC253_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC253_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC253_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC253_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG253_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG253_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG253_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG253_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func253_in_sel(&self) -> FUNC253_IN_SEL_R { + FUNC253_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func253_in_inv_sel(&self) -> FUNC253_IN_INV_SEL_R { + FUNC253_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig253_in_sel(&self) -> SIG253_IN_SEL_R { + SIG253_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC253_IN_SEL_CFG") + .field( + "func253_in_sel", + &format_args!("{}", self.func253_in_sel().bits()), + ) + .field( + "func253_in_inv_sel", + &format_args!("{}", self.func253_in_inv_sel().bit()), + ) + .field( + "sig253_in_sel", + &format_args!("{}", self.sig253_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func253_in_sel(&mut self) -> FUNC253_IN_SEL_W { + FUNC253_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func253_in_inv_sel(&mut self) -> FUNC253_IN_INV_SEL_W { + FUNC253_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig253_in_sel(&mut self) -> SIG253_IN_SEL_W { + SIG253_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func253_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func253_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC253_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC253_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func253_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC253_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func253_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC253_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC253_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC253_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func254_in_sel_cfg.rs b/esp32p4/src/gpio/func254_in_sel_cfg.rs new file mode 100644 index 0000000000..3dc7bb22b0 --- /dev/null +++ b/esp32p4/src/gpio/func254_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC254_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC254_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC254_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC254_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC254_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC254_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC254_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC254_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC254_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC254_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG254_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG254_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG254_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG254_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func254_in_sel(&self) -> FUNC254_IN_SEL_R { + FUNC254_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func254_in_inv_sel(&self) -> FUNC254_IN_INV_SEL_R { + FUNC254_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig254_in_sel(&self) -> SIG254_IN_SEL_R { + SIG254_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC254_IN_SEL_CFG") + .field( + "func254_in_sel", + &format_args!("{}", self.func254_in_sel().bits()), + ) + .field( + "func254_in_inv_sel", + &format_args!("{}", self.func254_in_inv_sel().bit()), + ) + .field( + "sig254_in_sel", + &format_args!("{}", self.sig254_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func254_in_sel(&mut self) -> FUNC254_IN_SEL_W { + FUNC254_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func254_in_inv_sel(&mut self) -> FUNC254_IN_INV_SEL_W { + FUNC254_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig254_in_sel(&mut self) -> SIG254_IN_SEL_W { + SIG254_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func254_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func254_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC254_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC254_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func254_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC254_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func254_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC254_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC254_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC254_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func255_in_sel_cfg.rs b/esp32p4/src/gpio/func255_in_sel_cfg.rs new file mode 100644 index 0000000000..abdee1bef1 --- /dev/null +++ b/esp32p4/src/gpio/func255_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC255_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC255_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC255_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC255_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC255_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC255_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC255_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC255_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC255_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC255_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG255_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG255_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG255_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG255_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func255_in_sel(&self) -> FUNC255_IN_SEL_R { + FUNC255_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func255_in_inv_sel(&self) -> FUNC255_IN_INV_SEL_R { + FUNC255_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig255_in_sel(&self) -> SIG255_IN_SEL_R { + SIG255_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC255_IN_SEL_CFG") + .field( + "func255_in_sel", + &format_args!("{}", self.func255_in_sel().bits()), + ) + .field( + "func255_in_inv_sel", + &format_args!("{}", self.func255_in_inv_sel().bit()), + ) + .field( + "sig255_in_sel", + &format_args!("{}", self.sig255_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func255_in_sel(&mut self) -> FUNC255_IN_SEL_W { + FUNC255_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func255_in_inv_sel(&mut self) -> FUNC255_IN_INV_SEL_W { + FUNC255_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig255_in_sel(&mut self) -> SIG255_IN_SEL_W { + SIG255_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func255_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func255_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC255_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC255_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func255_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC255_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func255_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC255_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC255_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC255_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func25_in_sel_cfg.rs b/esp32p4/src/gpio/func25_in_sel_cfg.rs new file mode 100644 index 0000000000..0df6a73fa0 --- /dev/null +++ b/esp32p4/src/gpio/func25_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC25_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC25_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC25_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC25_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC25_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC25_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC25_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC25_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC25_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC25_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG25_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG25_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG25_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG25_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func25_in_sel(&self) -> FUNC25_IN_SEL_R { + FUNC25_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func25_in_inv_sel(&self) -> FUNC25_IN_INV_SEL_R { + FUNC25_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig25_in_sel(&self) -> SIG25_IN_SEL_R { + SIG25_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC25_IN_SEL_CFG") + .field( + "func25_in_sel", + &format_args!("{}", self.func25_in_sel().bits()), + ) + .field( + "func25_in_inv_sel", + &format_args!("{}", self.func25_in_inv_sel().bit()), + ) + .field( + "sig25_in_sel", + &format_args!("{}", self.sig25_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func25_in_sel(&mut self) -> FUNC25_IN_SEL_W { + FUNC25_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func25_in_inv_sel(&mut self) -> FUNC25_IN_INV_SEL_W { + FUNC25_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig25_in_sel(&mut self) -> SIG25_IN_SEL_W { + SIG25_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func25_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func25_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC25_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC25_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func25_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC25_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func25_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC25_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC25_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC25_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func26_in_sel_cfg.rs b/esp32p4/src/gpio/func26_in_sel_cfg.rs new file mode 100644 index 0000000000..157b7dacd7 --- /dev/null +++ b/esp32p4/src/gpio/func26_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC26_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC26_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC26_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC26_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC26_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC26_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC26_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC26_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC26_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC26_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG26_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG26_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG26_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG26_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func26_in_sel(&self) -> FUNC26_IN_SEL_R { + FUNC26_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func26_in_inv_sel(&self) -> FUNC26_IN_INV_SEL_R { + FUNC26_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig26_in_sel(&self) -> SIG26_IN_SEL_R { + SIG26_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC26_IN_SEL_CFG") + .field( + "func26_in_sel", + &format_args!("{}", self.func26_in_sel().bits()), + ) + .field( + "func26_in_inv_sel", + &format_args!("{}", self.func26_in_inv_sel().bit()), + ) + .field( + "sig26_in_sel", + &format_args!("{}", self.sig26_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func26_in_sel(&mut self) -> FUNC26_IN_SEL_W { + FUNC26_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func26_in_inv_sel(&mut self) -> FUNC26_IN_INV_SEL_W { + FUNC26_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig26_in_sel(&mut self) -> SIG26_IN_SEL_W { + SIG26_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func26_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func26_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC26_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC26_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func26_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC26_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func26_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC26_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC26_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC26_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func27_in_sel_cfg.rs b/esp32p4/src/gpio/func27_in_sel_cfg.rs new file mode 100644 index 0000000000..fcaf7a7aff --- /dev/null +++ b/esp32p4/src/gpio/func27_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC27_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC27_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC27_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC27_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC27_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC27_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC27_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC27_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC27_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC27_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG27_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG27_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG27_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG27_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func27_in_sel(&self) -> FUNC27_IN_SEL_R { + FUNC27_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func27_in_inv_sel(&self) -> FUNC27_IN_INV_SEL_R { + FUNC27_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig27_in_sel(&self) -> SIG27_IN_SEL_R { + SIG27_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC27_IN_SEL_CFG") + .field( + "func27_in_sel", + &format_args!("{}", self.func27_in_sel().bits()), + ) + .field( + "func27_in_inv_sel", + &format_args!("{}", self.func27_in_inv_sel().bit()), + ) + .field( + "sig27_in_sel", + &format_args!("{}", self.sig27_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func27_in_sel(&mut self) -> FUNC27_IN_SEL_W { + FUNC27_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func27_in_inv_sel(&mut self) -> FUNC27_IN_INV_SEL_W { + FUNC27_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig27_in_sel(&mut self) -> SIG27_IN_SEL_W { + SIG27_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func27_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func27_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC27_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC27_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func27_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC27_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func27_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC27_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC27_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC27_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func28_in_sel_cfg.rs b/esp32p4/src/gpio/func28_in_sel_cfg.rs new file mode 100644 index 0000000000..781e422dd5 --- /dev/null +++ b/esp32p4/src/gpio/func28_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC28_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC28_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC28_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC28_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC28_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC28_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC28_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC28_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC28_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC28_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG28_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG28_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG28_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG28_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func28_in_sel(&self) -> FUNC28_IN_SEL_R { + FUNC28_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func28_in_inv_sel(&self) -> FUNC28_IN_INV_SEL_R { + FUNC28_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig28_in_sel(&self) -> SIG28_IN_SEL_R { + SIG28_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC28_IN_SEL_CFG") + .field( + "func28_in_sel", + &format_args!("{}", self.func28_in_sel().bits()), + ) + .field( + "func28_in_inv_sel", + &format_args!("{}", self.func28_in_inv_sel().bit()), + ) + .field( + "sig28_in_sel", + &format_args!("{}", self.sig28_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func28_in_sel(&mut self) -> FUNC28_IN_SEL_W { + FUNC28_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func28_in_inv_sel(&mut self) -> FUNC28_IN_INV_SEL_W { + FUNC28_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig28_in_sel(&mut self) -> SIG28_IN_SEL_W { + SIG28_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func28_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func28_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC28_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC28_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func28_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC28_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func28_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC28_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC28_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC28_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func29_in_sel_cfg.rs b/esp32p4/src/gpio/func29_in_sel_cfg.rs new file mode 100644 index 0000000000..6da11fc74b --- /dev/null +++ b/esp32p4/src/gpio/func29_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC29_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC29_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC29_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC29_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC29_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC29_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC29_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC29_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC29_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC29_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG29_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG29_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG29_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG29_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func29_in_sel(&self) -> FUNC29_IN_SEL_R { + FUNC29_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func29_in_inv_sel(&self) -> FUNC29_IN_INV_SEL_R { + FUNC29_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig29_in_sel(&self) -> SIG29_IN_SEL_R { + SIG29_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC29_IN_SEL_CFG") + .field( + "func29_in_sel", + &format_args!("{}", self.func29_in_sel().bits()), + ) + .field( + "func29_in_inv_sel", + &format_args!("{}", self.func29_in_inv_sel().bit()), + ) + .field( + "sig29_in_sel", + &format_args!("{}", self.sig29_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func29_in_sel(&mut self) -> FUNC29_IN_SEL_W { + FUNC29_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func29_in_inv_sel(&mut self) -> FUNC29_IN_INV_SEL_W { + FUNC29_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig29_in_sel(&mut self) -> SIG29_IN_SEL_W { + SIG29_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func29_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func29_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC29_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC29_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func29_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC29_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func29_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC29_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC29_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC29_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func2_in_sel_cfg.rs b/esp32p4/src/gpio/func2_in_sel_cfg.rs new file mode 100644 index 0000000000..f0e86a1c2f --- /dev/null +++ b/esp32p4/src/gpio/func2_in_sel_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `FUNC2_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC2_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC2_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC2_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC2_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC2_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC2_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC2_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC2_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC2_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG2_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG2_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG2_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG2_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func2_in_sel(&self) -> FUNC2_IN_SEL_R { + FUNC2_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func2_in_inv_sel(&self) -> FUNC2_IN_INV_SEL_R { + FUNC2_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig2_in_sel(&self) -> SIG2_IN_SEL_R { + SIG2_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC2_IN_SEL_CFG") + .field( + "func2_in_sel", + &format_args!("{}", self.func2_in_sel().bits()), + ) + .field( + "func2_in_inv_sel", + &format_args!("{}", self.func2_in_inv_sel().bit()), + ) + .field("sig2_in_sel", &format_args!("{}", self.sig2_in_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func2_in_sel(&mut self) -> FUNC2_IN_SEL_W { + FUNC2_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func2_in_inv_sel(&mut self) -> FUNC2_IN_INV_SEL_W { + FUNC2_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig2_in_sel(&mut self) -> SIG2_IN_SEL_W { + SIG2_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func2_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func2_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC2_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC2_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func2_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC2_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func2_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC2_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC2_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC2_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func30_in_sel_cfg.rs b/esp32p4/src/gpio/func30_in_sel_cfg.rs new file mode 100644 index 0000000000..c43fb68292 --- /dev/null +++ b/esp32p4/src/gpio/func30_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC30_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC30_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC30_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC30_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC30_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC30_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC30_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC30_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC30_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC30_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG30_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG30_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG30_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG30_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func30_in_sel(&self) -> FUNC30_IN_SEL_R { + FUNC30_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func30_in_inv_sel(&self) -> FUNC30_IN_INV_SEL_R { + FUNC30_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig30_in_sel(&self) -> SIG30_IN_SEL_R { + SIG30_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC30_IN_SEL_CFG") + .field( + "func30_in_sel", + &format_args!("{}", self.func30_in_sel().bits()), + ) + .field( + "func30_in_inv_sel", + &format_args!("{}", self.func30_in_inv_sel().bit()), + ) + .field( + "sig30_in_sel", + &format_args!("{}", self.sig30_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func30_in_sel(&mut self) -> FUNC30_IN_SEL_W { + FUNC30_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func30_in_inv_sel(&mut self) -> FUNC30_IN_INV_SEL_W { + FUNC30_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig30_in_sel(&mut self) -> SIG30_IN_SEL_W { + SIG30_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func30_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func30_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC30_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC30_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func30_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC30_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func30_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC30_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC30_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC30_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func31_in_sel_cfg.rs b/esp32p4/src/gpio/func31_in_sel_cfg.rs new file mode 100644 index 0000000000..8d761076dd --- /dev/null +++ b/esp32p4/src/gpio/func31_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC31_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC31_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC31_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC31_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC31_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC31_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC31_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC31_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC31_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC31_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG31_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG31_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG31_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG31_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func31_in_sel(&self) -> FUNC31_IN_SEL_R { + FUNC31_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func31_in_inv_sel(&self) -> FUNC31_IN_INV_SEL_R { + FUNC31_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig31_in_sel(&self) -> SIG31_IN_SEL_R { + SIG31_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC31_IN_SEL_CFG") + .field( + "func31_in_sel", + &format_args!("{}", self.func31_in_sel().bits()), + ) + .field( + "func31_in_inv_sel", + &format_args!("{}", self.func31_in_inv_sel().bit()), + ) + .field( + "sig31_in_sel", + &format_args!("{}", self.sig31_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func31_in_sel(&mut self) -> FUNC31_IN_SEL_W { + FUNC31_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func31_in_inv_sel(&mut self) -> FUNC31_IN_INV_SEL_W { + FUNC31_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig31_in_sel(&mut self) -> SIG31_IN_SEL_W { + SIG31_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func31_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func31_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC31_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC31_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func31_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC31_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func31_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC31_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC31_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC31_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func32_in_sel_cfg.rs b/esp32p4/src/gpio/func32_in_sel_cfg.rs new file mode 100644 index 0000000000..ab49038479 --- /dev/null +++ b/esp32p4/src/gpio/func32_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC32_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC32_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC32_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC32_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC32_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC32_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC32_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC32_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC32_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC32_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG32_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG32_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG32_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG32_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func32_in_sel(&self) -> FUNC32_IN_SEL_R { + FUNC32_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func32_in_inv_sel(&self) -> FUNC32_IN_INV_SEL_R { + FUNC32_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig32_in_sel(&self) -> SIG32_IN_SEL_R { + SIG32_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC32_IN_SEL_CFG") + .field( + "func32_in_sel", + &format_args!("{}", self.func32_in_sel().bits()), + ) + .field( + "func32_in_inv_sel", + &format_args!("{}", self.func32_in_inv_sel().bit()), + ) + .field( + "sig32_in_sel", + &format_args!("{}", self.sig32_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func32_in_sel(&mut self) -> FUNC32_IN_SEL_W { + FUNC32_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func32_in_inv_sel(&mut self) -> FUNC32_IN_INV_SEL_W { + FUNC32_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig32_in_sel(&mut self) -> SIG32_IN_SEL_W { + SIG32_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func32_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func32_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC32_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC32_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func32_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC32_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func32_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC32_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC32_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC32_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func33_in_sel_cfg.rs b/esp32p4/src/gpio/func33_in_sel_cfg.rs new file mode 100644 index 0000000000..d2a6eb72b3 --- /dev/null +++ b/esp32p4/src/gpio/func33_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC33_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC33_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC33_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC33_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC33_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC33_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC33_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC33_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC33_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC33_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG33_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG33_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG33_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG33_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func33_in_sel(&self) -> FUNC33_IN_SEL_R { + FUNC33_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func33_in_inv_sel(&self) -> FUNC33_IN_INV_SEL_R { + FUNC33_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig33_in_sel(&self) -> SIG33_IN_SEL_R { + SIG33_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC33_IN_SEL_CFG") + .field( + "func33_in_sel", + &format_args!("{}", self.func33_in_sel().bits()), + ) + .field( + "func33_in_inv_sel", + &format_args!("{}", self.func33_in_inv_sel().bit()), + ) + .field( + "sig33_in_sel", + &format_args!("{}", self.sig33_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func33_in_sel(&mut self) -> FUNC33_IN_SEL_W { + FUNC33_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func33_in_inv_sel(&mut self) -> FUNC33_IN_INV_SEL_W { + FUNC33_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig33_in_sel(&mut self) -> SIG33_IN_SEL_W { + SIG33_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func33_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func33_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC33_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC33_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func33_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC33_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func33_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC33_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC33_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC33_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func34_in_sel_cfg.rs b/esp32p4/src/gpio/func34_in_sel_cfg.rs new file mode 100644 index 0000000000..c694caf56e --- /dev/null +++ b/esp32p4/src/gpio/func34_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC34_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC34_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC34_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC34_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC34_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC34_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC34_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC34_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC34_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC34_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG34_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG34_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG34_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG34_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func34_in_sel(&self) -> FUNC34_IN_SEL_R { + FUNC34_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func34_in_inv_sel(&self) -> FUNC34_IN_INV_SEL_R { + FUNC34_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig34_in_sel(&self) -> SIG34_IN_SEL_R { + SIG34_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC34_IN_SEL_CFG") + .field( + "func34_in_sel", + &format_args!("{}", self.func34_in_sel().bits()), + ) + .field( + "func34_in_inv_sel", + &format_args!("{}", self.func34_in_inv_sel().bit()), + ) + .field( + "sig34_in_sel", + &format_args!("{}", self.sig34_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func34_in_sel(&mut self) -> FUNC34_IN_SEL_W { + FUNC34_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func34_in_inv_sel(&mut self) -> FUNC34_IN_INV_SEL_W { + FUNC34_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig34_in_sel(&mut self) -> SIG34_IN_SEL_W { + SIG34_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func34_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func34_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC34_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC34_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func34_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC34_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func34_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC34_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC34_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC34_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func35_in_sel_cfg.rs b/esp32p4/src/gpio/func35_in_sel_cfg.rs new file mode 100644 index 0000000000..0b0447dc35 --- /dev/null +++ b/esp32p4/src/gpio/func35_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC35_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC35_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC35_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC35_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC35_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC35_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC35_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC35_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC35_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC35_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG35_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG35_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG35_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG35_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func35_in_sel(&self) -> FUNC35_IN_SEL_R { + FUNC35_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func35_in_inv_sel(&self) -> FUNC35_IN_INV_SEL_R { + FUNC35_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig35_in_sel(&self) -> SIG35_IN_SEL_R { + SIG35_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC35_IN_SEL_CFG") + .field( + "func35_in_sel", + &format_args!("{}", self.func35_in_sel().bits()), + ) + .field( + "func35_in_inv_sel", + &format_args!("{}", self.func35_in_inv_sel().bit()), + ) + .field( + "sig35_in_sel", + &format_args!("{}", self.sig35_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func35_in_sel(&mut self) -> FUNC35_IN_SEL_W { + FUNC35_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func35_in_inv_sel(&mut self) -> FUNC35_IN_INV_SEL_W { + FUNC35_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig35_in_sel(&mut self) -> SIG35_IN_SEL_W { + SIG35_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func35_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func35_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC35_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC35_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func35_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC35_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func35_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC35_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC35_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC35_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func36_in_sel_cfg.rs b/esp32p4/src/gpio/func36_in_sel_cfg.rs new file mode 100644 index 0000000000..d62bbcd7e6 --- /dev/null +++ b/esp32p4/src/gpio/func36_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC36_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC36_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC36_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC36_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC36_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC36_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC36_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC36_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC36_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC36_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG36_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG36_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG36_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG36_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func36_in_sel(&self) -> FUNC36_IN_SEL_R { + FUNC36_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func36_in_inv_sel(&self) -> FUNC36_IN_INV_SEL_R { + FUNC36_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig36_in_sel(&self) -> SIG36_IN_SEL_R { + SIG36_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC36_IN_SEL_CFG") + .field( + "func36_in_sel", + &format_args!("{}", self.func36_in_sel().bits()), + ) + .field( + "func36_in_inv_sel", + &format_args!("{}", self.func36_in_inv_sel().bit()), + ) + .field( + "sig36_in_sel", + &format_args!("{}", self.sig36_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func36_in_sel(&mut self) -> FUNC36_IN_SEL_W { + FUNC36_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func36_in_inv_sel(&mut self) -> FUNC36_IN_INV_SEL_W { + FUNC36_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig36_in_sel(&mut self) -> SIG36_IN_SEL_W { + SIG36_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func36_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func36_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC36_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC36_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func36_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC36_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func36_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC36_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC36_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC36_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func37_in_sel_cfg.rs b/esp32p4/src/gpio/func37_in_sel_cfg.rs new file mode 100644 index 0000000000..b131c3ce1b --- /dev/null +++ b/esp32p4/src/gpio/func37_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC37_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC37_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC37_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC37_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC37_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC37_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC37_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC37_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC37_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC37_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG37_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG37_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG37_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG37_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func37_in_sel(&self) -> FUNC37_IN_SEL_R { + FUNC37_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func37_in_inv_sel(&self) -> FUNC37_IN_INV_SEL_R { + FUNC37_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig37_in_sel(&self) -> SIG37_IN_SEL_R { + SIG37_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC37_IN_SEL_CFG") + .field( + "func37_in_sel", + &format_args!("{}", self.func37_in_sel().bits()), + ) + .field( + "func37_in_inv_sel", + &format_args!("{}", self.func37_in_inv_sel().bit()), + ) + .field( + "sig37_in_sel", + &format_args!("{}", self.sig37_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func37_in_sel(&mut self) -> FUNC37_IN_SEL_W { + FUNC37_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func37_in_inv_sel(&mut self) -> FUNC37_IN_INV_SEL_W { + FUNC37_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig37_in_sel(&mut self) -> SIG37_IN_SEL_W { + SIG37_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func37_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func37_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC37_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC37_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func37_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC37_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func37_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC37_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC37_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC37_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func38_in_sel_cfg.rs b/esp32p4/src/gpio/func38_in_sel_cfg.rs new file mode 100644 index 0000000000..bf37b34932 --- /dev/null +++ b/esp32p4/src/gpio/func38_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC38_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC38_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC38_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC38_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC38_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC38_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC38_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC38_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC38_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC38_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG38_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG38_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG38_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG38_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func38_in_sel(&self) -> FUNC38_IN_SEL_R { + FUNC38_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func38_in_inv_sel(&self) -> FUNC38_IN_INV_SEL_R { + FUNC38_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig38_in_sel(&self) -> SIG38_IN_SEL_R { + SIG38_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC38_IN_SEL_CFG") + .field( + "func38_in_sel", + &format_args!("{}", self.func38_in_sel().bits()), + ) + .field( + "func38_in_inv_sel", + &format_args!("{}", self.func38_in_inv_sel().bit()), + ) + .field( + "sig38_in_sel", + &format_args!("{}", self.sig38_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func38_in_sel(&mut self) -> FUNC38_IN_SEL_W { + FUNC38_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func38_in_inv_sel(&mut self) -> FUNC38_IN_INV_SEL_W { + FUNC38_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig38_in_sel(&mut self) -> SIG38_IN_SEL_W { + SIG38_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func38_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func38_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC38_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC38_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func38_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC38_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func38_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC38_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC38_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC38_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func39_in_sel_cfg.rs b/esp32p4/src/gpio/func39_in_sel_cfg.rs new file mode 100644 index 0000000000..e59ab91e87 --- /dev/null +++ b/esp32p4/src/gpio/func39_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC39_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC39_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC39_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC39_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC39_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC39_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC39_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC39_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC39_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC39_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG39_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG39_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG39_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG39_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func39_in_sel(&self) -> FUNC39_IN_SEL_R { + FUNC39_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func39_in_inv_sel(&self) -> FUNC39_IN_INV_SEL_R { + FUNC39_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig39_in_sel(&self) -> SIG39_IN_SEL_R { + SIG39_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC39_IN_SEL_CFG") + .field( + "func39_in_sel", + &format_args!("{}", self.func39_in_sel().bits()), + ) + .field( + "func39_in_inv_sel", + &format_args!("{}", self.func39_in_inv_sel().bit()), + ) + .field( + "sig39_in_sel", + &format_args!("{}", self.sig39_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func39_in_sel(&mut self) -> FUNC39_IN_SEL_W { + FUNC39_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func39_in_inv_sel(&mut self) -> FUNC39_IN_INV_SEL_W { + FUNC39_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig39_in_sel(&mut self) -> SIG39_IN_SEL_W { + SIG39_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func39_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func39_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC39_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC39_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func39_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC39_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func39_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC39_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC39_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC39_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func3_in_sel_cfg.rs b/esp32p4/src/gpio/func3_in_sel_cfg.rs new file mode 100644 index 0000000000..3cdd30e36e --- /dev/null +++ b/esp32p4/src/gpio/func3_in_sel_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `FUNC3_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC3_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC3_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC3_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC3_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC3_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC3_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC3_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC3_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC3_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG3_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG3_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG3_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG3_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func3_in_sel(&self) -> FUNC3_IN_SEL_R { + FUNC3_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func3_in_inv_sel(&self) -> FUNC3_IN_INV_SEL_R { + FUNC3_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig3_in_sel(&self) -> SIG3_IN_SEL_R { + SIG3_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC3_IN_SEL_CFG") + .field( + "func3_in_sel", + &format_args!("{}", self.func3_in_sel().bits()), + ) + .field( + "func3_in_inv_sel", + &format_args!("{}", self.func3_in_inv_sel().bit()), + ) + .field("sig3_in_sel", &format_args!("{}", self.sig3_in_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func3_in_sel(&mut self) -> FUNC3_IN_SEL_W { + FUNC3_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func3_in_inv_sel(&mut self) -> FUNC3_IN_INV_SEL_W { + FUNC3_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig3_in_sel(&mut self) -> SIG3_IN_SEL_W { + SIG3_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func3_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func3_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC3_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC3_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func3_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC3_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func3_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC3_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC3_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC3_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func40_in_sel_cfg.rs b/esp32p4/src/gpio/func40_in_sel_cfg.rs new file mode 100644 index 0000000000..538776c779 --- /dev/null +++ b/esp32p4/src/gpio/func40_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC40_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC40_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC40_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC40_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC40_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC40_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC40_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC40_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC40_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC40_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG40_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG40_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG40_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG40_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func40_in_sel(&self) -> FUNC40_IN_SEL_R { + FUNC40_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func40_in_inv_sel(&self) -> FUNC40_IN_INV_SEL_R { + FUNC40_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig40_in_sel(&self) -> SIG40_IN_SEL_R { + SIG40_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC40_IN_SEL_CFG") + .field( + "func40_in_sel", + &format_args!("{}", self.func40_in_sel().bits()), + ) + .field( + "func40_in_inv_sel", + &format_args!("{}", self.func40_in_inv_sel().bit()), + ) + .field( + "sig40_in_sel", + &format_args!("{}", self.sig40_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func40_in_sel(&mut self) -> FUNC40_IN_SEL_W { + FUNC40_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func40_in_inv_sel(&mut self) -> FUNC40_IN_INV_SEL_W { + FUNC40_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig40_in_sel(&mut self) -> SIG40_IN_SEL_W { + SIG40_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func40_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func40_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC40_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC40_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func40_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC40_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func40_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC40_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC40_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC40_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func41_in_sel_cfg.rs b/esp32p4/src/gpio/func41_in_sel_cfg.rs new file mode 100644 index 0000000000..1804fe9f0d --- /dev/null +++ b/esp32p4/src/gpio/func41_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC41_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC41_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC41_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC41_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC41_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC41_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC41_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC41_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC41_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC41_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG41_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG41_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG41_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG41_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func41_in_sel(&self) -> FUNC41_IN_SEL_R { + FUNC41_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func41_in_inv_sel(&self) -> FUNC41_IN_INV_SEL_R { + FUNC41_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig41_in_sel(&self) -> SIG41_IN_SEL_R { + SIG41_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC41_IN_SEL_CFG") + .field( + "func41_in_sel", + &format_args!("{}", self.func41_in_sel().bits()), + ) + .field( + "func41_in_inv_sel", + &format_args!("{}", self.func41_in_inv_sel().bit()), + ) + .field( + "sig41_in_sel", + &format_args!("{}", self.sig41_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func41_in_sel(&mut self) -> FUNC41_IN_SEL_W { + FUNC41_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func41_in_inv_sel(&mut self) -> FUNC41_IN_INV_SEL_W { + FUNC41_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig41_in_sel(&mut self) -> SIG41_IN_SEL_W { + SIG41_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func41_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func41_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC41_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC41_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func41_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC41_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func41_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC41_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC41_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC41_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func42_in_sel_cfg.rs b/esp32p4/src/gpio/func42_in_sel_cfg.rs new file mode 100644 index 0000000000..39088f91a0 --- /dev/null +++ b/esp32p4/src/gpio/func42_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC42_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC42_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC42_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC42_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC42_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC42_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC42_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC42_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC42_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC42_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG42_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG42_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG42_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG42_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func42_in_sel(&self) -> FUNC42_IN_SEL_R { + FUNC42_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func42_in_inv_sel(&self) -> FUNC42_IN_INV_SEL_R { + FUNC42_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig42_in_sel(&self) -> SIG42_IN_SEL_R { + SIG42_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC42_IN_SEL_CFG") + .field( + "func42_in_sel", + &format_args!("{}", self.func42_in_sel().bits()), + ) + .field( + "func42_in_inv_sel", + &format_args!("{}", self.func42_in_inv_sel().bit()), + ) + .field( + "sig42_in_sel", + &format_args!("{}", self.sig42_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func42_in_sel(&mut self) -> FUNC42_IN_SEL_W { + FUNC42_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func42_in_inv_sel(&mut self) -> FUNC42_IN_INV_SEL_W { + FUNC42_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig42_in_sel(&mut self) -> SIG42_IN_SEL_W { + SIG42_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func42_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func42_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC42_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC42_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func42_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC42_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func42_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC42_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC42_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC42_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func43_in_sel_cfg.rs b/esp32p4/src/gpio/func43_in_sel_cfg.rs new file mode 100644 index 0000000000..7f9c08f144 --- /dev/null +++ b/esp32p4/src/gpio/func43_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC43_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC43_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC43_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC43_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC43_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC43_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC43_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC43_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC43_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC43_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG43_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG43_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG43_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG43_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func43_in_sel(&self) -> FUNC43_IN_SEL_R { + FUNC43_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func43_in_inv_sel(&self) -> FUNC43_IN_INV_SEL_R { + FUNC43_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig43_in_sel(&self) -> SIG43_IN_SEL_R { + SIG43_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC43_IN_SEL_CFG") + .field( + "func43_in_sel", + &format_args!("{}", self.func43_in_sel().bits()), + ) + .field( + "func43_in_inv_sel", + &format_args!("{}", self.func43_in_inv_sel().bit()), + ) + .field( + "sig43_in_sel", + &format_args!("{}", self.sig43_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func43_in_sel(&mut self) -> FUNC43_IN_SEL_W { + FUNC43_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func43_in_inv_sel(&mut self) -> FUNC43_IN_INV_SEL_W { + FUNC43_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig43_in_sel(&mut self) -> SIG43_IN_SEL_W { + SIG43_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func43_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func43_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC43_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC43_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func43_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC43_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func43_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC43_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC43_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC43_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func44_in_sel_cfg.rs b/esp32p4/src/gpio/func44_in_sel_cfg.rs new file mode 100644 index 0000000000..4da3541f37 --- /dev/null +++ b/esp32p4/src/gpio/func44_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC44_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC44_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC44_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC44_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC44_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC44_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC44_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC44_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC44_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC44_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG44_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG44_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG44_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG44_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func44_in_sel(&self) -> FUNC44_IN_SEL_R { + FUNC44_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func44_in_inv_sel(&self) -> FUNC44_IN_INV_SEL_R { + FUNC44_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig44_in_sel(&self) -> SIG44_IN_SEL_R { + SIG44_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC44_IN_SEL_CFG") + .field( + "func44_in_sel", + &format_args!("{}", self.func44_in_sel().bits()), + ) + .field( + "func44_in_inv_sel", + &format_args!("{}", self.func44_in_inv_sel().bit()), + ) + .field( + "sig44_in_sel", + &format_args!("{}", self.sig44_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func44_in_sel(&mut self) -> FUNC44_IN_SEL_W { + FUNC44_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func44_in_inv_sel(&mut self) -> FUNC44_IN_INV_SEL_W { + FUNC44_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig44_in_sel(&mut self) -> SIG44_IN_SEL_W { + SIG44_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func44_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func44_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC44_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC44_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func44_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC44_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func44_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC44_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC44_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC44_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func45_in_sel_cfg.rs b/esp32p4/src/gpio/func45_in_sel_cfg.rs new file mode 100644 index 0000000000..0ef63e72d9 --- /dev/null +++ b/esp32p4/src/gpio/func45_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC45_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC45_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC45_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC45_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC45_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC45_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC45_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC45_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC45_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC45_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG45_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG45_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG45_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG45_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func45_in_sel(&self) -> FUNC45_IN_SEL_R { + FUNC45_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func45_in_inv_sel(&self) -> FUNC45_IN_INV_SEL_R { + FUNC45_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig45_in_sel(&self) -> SIG45_IN_SEL_R { + SIG45_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC45_IN_SEL_CFG") + .field( + "func45_in_sel", + &format_args!("{}", self.func45_in_sel().bits()), + ) + .field( + "func45_in_inv_sel", + &format_args!("{}", self.func45_in_inv_sel().bit()), + ) + .field( + "sig45_in_sel", + &format_args!("{}", self.sig45_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func45_in_sel(&mut self) -> FUNC45_IN_SEL_W { + FUNC45_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func45_in_inv_sel(&mut self) -> FUNC45_IN_INV_SEL_W { + FUNC45_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig45_in_sel(&mut self) -> SIG45_IN_SEL_W { + SIG45_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func45_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func45_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC45_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC45_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func45_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC45_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func45_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC45_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC45_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC45_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func47_in_sel_cfg.rs b/esp32p4/src/gpio/func47_in_sel_cfg.rs new file mode 100644 index 0000000000..a0c5e3e7d4 --- /dev/null +++ b/esp32p4/src/gpio/func47_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC47_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC47_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC47_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC47_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC47_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC47_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC47_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC47_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC47_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC47_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG47_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG47_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG47_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG47_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func47_in_sel(&self) -> FUNC47_IN_SEL_R { + FUNC47_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func47_in_inv_sel(&self) -> FUNC47_IN_INV_SEL_R { + FUNC47_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig47_in_sel(&self) -> SIG47_IN_SEL_R { + SIG47_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC47_IN_SEL_CFG") + .field( + "func47_in_sel", + &format_args!("{}", self.func47_in_sel().bits()), + ) + .field( + "func47_in_inv_sel", + &format_args!("{}", self.func47_in_inv_sel().bit()), + ) + .field( + "sig47_in_sel", + &format_args!("{}", self.sig47_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func47_in_sel(&mut self) -> FUNC47_IN_SEL_W { + FUNC47_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func47_in_inv_sel(&mut self) -> FUNC47_IN_INV_SEL_W { + FUNC47_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig47_in_sel(&mut self) -> SIG47_IN_SEL_W { + SIG47_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func47_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func47_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC47_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC47_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func47_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC47_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func47_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC47_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC47_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC47_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func48_in_sel_cfg.rs b/esp32p4/src/gpio/func48_in_sel_cfg.rs new file mode 100644 index 0000000000..deb39be4e7 --- /dev/null +++ b/esp32p4/src/gpio/func48_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC48_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC48_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC48_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC48_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC48_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC48_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC48_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC48_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC48_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC48_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG48_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG48_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG48_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG48_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func48_in_sel(&self) -> FUNC48_IN_SEL_R { + FUNC48_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func48_in_inv_sel(&self) -> FUNC48_IN_INV_SEL_R { + FUNC48_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig48_in_sel(&self) -> SIG48_IN_SEL_R { + SIG48_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC48_IN_SEL_CFG") + .field( + "func48_in_sel", + &format_args!("{}", self.func48_in_sel().bits()), + ) + .field( + "func48_in_inv_sel", + &format_args!("{}", self.func48_in_inv_sel().bit()), + ) + .field( + "sig48_in_sel", + &format_args!("{}", self.sig48_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func48_in_sel(&mut self) -> FUNC48_IN_SEL_W { + FUNC48_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func48_in_inv_sel(&mut self) -> FUNC48_IN_INV_SEL_W { + FUNC48_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig48_in_sel(&mut self) -> SIG48_IN_SEL_W { + SIG48_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func48_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func48_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC48_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC48_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func48_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC48_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func48_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC48_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC48_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC48_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func49_in_sel_cfg.rs b/esp32p4/src/gpio/func49_in_sel_cfg.rs new file mode 100644 index 0000000000..8a4557796e --- /dev/null +++ b/esp32p4/src/gpio/func49_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC49_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC49_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC49_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC49_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC49_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC49_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC49_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC49_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC49_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC49_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG49_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG49_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG49_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG49_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func49_in_sel(&self) -> FUNC49_IN_SEL_R { + FUNC49_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func49_in_inv_sel(&self) -> FUNC49_IN_INV_SEL_R { + FUNC49_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig49_in_sel(&self) -> SIG49_IN_SEL_R { + SIG49_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC49_IN_SEL_CFG") + .field( + "func49_in_sel", + &format_args!("{}", self.func49_in_sel().bits()), + ) + .field( + "func49_in_inv_sel", + &format_args!("{}", self.func49_in_inv_sel().bit()), + ) + .field( + "sig49_in_sel", + &format_args!("{}", self.sig49_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func49_in_sel(&mut self) -> FUNC49_IN_SEL_W { + FUNC49_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func49_in_inv_sel(&mut self) -> FUNC49_IN_INV_SEL_W { + FUNC49_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig49_in_sel(&mut self) -> SIG49_IN_SEL_W { + SIG49_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func49_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func49_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC49_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC49_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func49_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC49_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func49_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC49_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC49_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC49_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func4_in_sel_cfg.rs b/esp32p4/src/gpio/func4_in_sel_cfg.rs new file mode 100644 index 0000000000..f1ccf14a51 --- /dev/null +++ b/esp32p4/src/gpio/func4_in_sel_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `FUNC4_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC4_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC4_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC4_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC4_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC4_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC4_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC4_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC4_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC4_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG4_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG4_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG4_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG4_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func4_in_sel(&self) -> FUNC4_IN_SEL_R { + FUNC4_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func4_in_inv_sel(&self) -> FUNC4_IN_INV_SEL_R { + FUNC4_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig4_in_sel(&self) -> SIG4_IN_SEL_R { + SIG4_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC4_IN_SEL_CFG") + .field( + "func4_in_sel", + &format_args!("{}", self.func4_in_sel().bits()), + ) + .field( + "func4_in_inv_sel", + &format_args!("{}", self.func4_in_inv_sel().bit()), + ) + .field("sig4_in_sel", &format_args!("{}", self.sig4_in_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func4_in_sel(&mut self) -> FUNC4_IN_SEL_W { + FUNC4_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func4_in_inv_sel(&mut self) -> FUNC4_IN_INV_SEL_W { + FUNC4_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig4_in_sel(&mut self) -> SIG4_IN_SEL_W { + SIG4_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func4_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func4_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC4_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC4_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func4_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC4_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func4_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC4_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC4_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC4_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func50_in_sel_cfg.rs b/esp32p4/src/gpio/func50_in_sel_cfg.rs new file mode 100644 index 0000000000..fd0cc4a08e --- /dev/null +++ b/esp32p4/src/gpio/func50_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC50_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC50_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC50_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC50_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC50_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC50_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC50_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC50_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC50_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC50_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG50_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG50_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG50_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG50_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func50_in_sel(&self) -> FUNC50_IN_SEL_R { + FUNC50_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func50_in_inv_sel(&self) -> FUNC50_IN_INV_SEL_R { + FUNC50_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig50_in_sel(&self) -> SIG50_IN_SEL_R { + SIG50_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC50_IN_SEL_CFG") + .field( + "func50_in_sel", + &format_args!("{}", self.func50_in_sel().bits()), + ) + .field( + "func50_in_inv_sel", + &format_args!("{}", self.func50_in_inv_sel().bit()), + ) + .field( + "sig50_in_sel", + &format_args!("{}", self.sig50_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func50_in_sel(&mut self) -> FUNC50_IN_SEL_W { + FUNC50_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func50_in_inv_sel(&mut self) -> FUNC50_IN_INV_SEL_W { + FUNC50_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig50_in_sel(&mut self) -> SIG50_IN_SEL_W { + SIG50_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func50_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func50_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC50_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC50_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func50_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC50_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func50_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC50_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC50_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC50_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func51_in_sel_cfg.rs b/esp32p4/src/gpio/func51_in_sel_cfg.rs new file mode 100644 index 0000000000..d8696a171b --- /dev/null +++ b/esp32p4/src/gpio/func51_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC51_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC51_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC51_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC51_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC51_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC51_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC51_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC51_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC51_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC51_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG51_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG51_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG51_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG51_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func51_in_sel(&self) -> FUNC51_IN_SEL_R { + FUNC51_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func51_in_inv_sel(&self) -> FUNC51_IN_INV_SEL_R { + FUNC51_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig51_in_sel(&self) -> SIG51_IN_SEL_R { + SIG51_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC51_IN_SEL_CFG") + .field( + "func51_in_sel", + &format_args!("{}", self.func51_in_sel().bits()), + ) + .field( + "func51_in_inv_sel", + &format_args!("{}", self.func51_in_inv_sel().bit()), + ) + .field( + "sig51_in_sel", + &format_args!("{}", self.sig51_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func51_in_sel(&mut self) -> FUNC51_IN_SEL_W { + FUNC51_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func51_in_inv_sel(&mut self) -> FUNC51_IN_INV_SEL_W { + FUNC51_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig51_in_sel(&mut self) -> SIG51_IN_SEL_W { + SIG51_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func51_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func51_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC51_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC51_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func51_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC51_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func51_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC51_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC51_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC51_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func52_in_sel_cfg.rs b/esp32p4/src/gpio/func52_in_sel_cfg.rs new file mode 100644 index 0000000000..5b1ebadee0 --- /dev/null +++ b/esp32p4/src/gpio/func52_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC52_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC52_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC52_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC52_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC52_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC52_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC52_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC52_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC52_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC52_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG52_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG52_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG52_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG52_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func52_in_sel(&self) -> FUNC52_IN_SEL_R { + FUNC52_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func52_in_inv_sel(&self) -> FUNC52_IN_INV_SEL_R { + FUNC52_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig52_in_sel(&self) -> SIG52_IN_SEL_R { + SIG52_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC52_IN_SEL_CFG") + .field( + "func52_in_sel", + &format_args!("{}", self.func52_in_sel().bits()), + ) + .field( + "func52_in_inv_sel", + &format_args!("{}", self.func52_in_inv_sel().bit()), + ) + .field( + "sig52_in_sel", + &format_args!("{}", self.sig52_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func52_in_sel(&mut self) -> FUNC52_IN_SEL_W { + FUNC52_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func52_in_inv_sel(&mut self) -> FUNC52_IN_INV_SEL_W { + FUNC52_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig52_in_sel(&mut self) -> SIG52_IN_SEL_W { + SIG52_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func52_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func52_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC52_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC52_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func52_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC52_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func52_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC52_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC52_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC52_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func53_in_sel_cfg.rs b/esp32p4/src/gpio/func53_in_sel_cfg.rs new file mode 100644 index 0000000000..48e63b0c46 --- /dev/null +++ b/esp32p4/src/gpio/func53_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC53_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC53_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC53_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC53_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC53_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC53_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC53_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC53_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC53_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC53_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG53_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG53_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG53_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG53_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func53_in_sel(&self) -> FUNC53_IN_SEL_R { + FUNC53_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func53_in_inv_sel(&self) -> FUNC53_IN_INV_SEL_R { + FUNC53_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig53_in_sel(&self) -> SIG53_IN_SEL_R { + SIG53_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC53_IN_SEL_CFG") + .field( + "func53_in_sel", + &format_args!("{}", self.func53_in_sel().bits()), + ) + .field( + "func53_in_inv_sel", + &format_args!("{}", self.func53_in_inv_sel().bit()), + ) + .field( + "sig53_in_sel", + &format_args!("{}", self.sig53_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func53_in_sel(&mut self) -> FUNC53_IN_SEL_W { + FUNC53_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func53_in_inv_sel(&mut self) -> FUNC53_IN_INV_SEL_W { + FUNC53_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig53_in_sel(&mut self) -> SIG53_IN_SEL_W { + SIG53_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func53_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func53_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC53_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC53_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func53_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC53_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func53_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC53_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC53_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC53_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func54_in_sel_cfg.rs b/esp32p4/src/gpio/func54_in_sel_cfg.rs new file mode 100644 index 0000000000..2dce02fcb3 --- /dev/null +++ b/esp32p4/src/gpio/func54_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC54_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC54_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC54_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC54_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC54_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC54_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC54_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC54_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC54_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC54_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG54_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG54_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG54_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG54_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func54_in_sel(&self) -> FUNC54_IN_SEL_R { + FUNC54_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func54_in_inv_sel(&self) -> FUNC54_IN_INV_SEL_R { + FUNC54_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig54_in_sel(&self) -> SIG54_IN_SEL_R { + SIG54_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC54_IN_SEL_CFG") + .field( + "func54_in_sel", + &format_args!("{}", self.func54_in_sel().bits()), + ) + .field( + "func54_in_inv_sel", + &format_args!("{}", self.func54_in_inv_sel().bit()), + ) + .field( + "sig54_in_sel", + &format_args!("{}", self.sig54_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func54_in_sel(&mut self) -> FUNC54_IN_SEL_W { + FUNC54_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func54_in_inv_sel(&mut self) -> FUNC54_IN_INV_SEL_W { + FUNC54_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig54_in_sel(&mut self) -> SIG54_IN_SEL_W { + SIG54_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func54_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func54_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC54_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC54_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func54_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC54_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func54_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC54_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC54_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC54_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func55_in_sel_cfg.rs b/esp32p4/src/gpio/func55_in_sel_cfg.rs new file mode 100644 index 0000000000..845cd4295f --- /dev/null +++ b/esp32p4/src/gpio/func55_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC55_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC55_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC55_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC55_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC55_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC55_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC55_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC55_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC55_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC55_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG55_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG55_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG55_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG55_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func55_in_sel(&self) -> FUNC55_IN_SEL_R { + FUNC55_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func55_in_inv_sel(&self) -> FUNC55_IN_INV_SEL_R { + FUNC55_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig55_in_sel(&self) -> SIG55_IN_SEL_R { + SIG55_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC55_IN_SEL_CFG") + .field( + "func55_in_sel", + &format_args!("{}", self.func55_in_sel().bits()), + ) + .field( + "func55_in_inv_sel", + &format_args!("{}", self.func55_in_inv_sel().bit()), + ) + .field( + "sig55_in_sel", + &format_args!("{}", self.sig55_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func55_in_sel(&mut self) -> FUNC55_IN_SEL_W { + FUNC55_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func55_in_inv_sel(&mut self) -> FUNC55_IN_INV_SEL_W { + FUNC55_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig55_in_sel(&mut self) -> SIG55_IN_SEL_W { + SIG55_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func55_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func55_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC55_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC55_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func55_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC55_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func55_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC55_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC55_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC55_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func56_in_sel_cfg.rs b/esp32p4/src/gpio/func56_in_sel_cfg.rs new file mode 100644 index 0000000000..b629ad8487 --- /dev/null +++ b/esp32p4/src/gpio/func56_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC56_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC56_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC56_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC56_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC56_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC56_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC56_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC56_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC56_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC56_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG56_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG56_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG56_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG56_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func56_in_sel(&self) -> FUNC56_IN_SEL_R { + FUNC56_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func56_in_inv_sel(&self) -> FUNC56_IN_INV_SEL_R { + FUNC56_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig56_in_sel(&self) -> SIG56_IN_SEL_R { + SIG56_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC56_IN_SEL_CFG") + .field( + "func56_in_sel", + &format_args!("{}", self.func56_in_sel().bits()), + ) + .field( + "func56_in_inv_sel", + &format_args!("{}", self.func56_in_inv_sel().bit()), + ) + .field( + "sig56_in_sel", + &format_args!("{}", self.sig56_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func56_in_sel(&mut self) -> FUNC56_IN_SEL_W { + FUNC56_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func56_in_inv_sel(&mut self) -> FUNC56_IN_INV_SEL_W { + FUNC56_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig56_in_sel(&mut self) -> SIG56_IN_SEL_W { + SIG56_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func56_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func56_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC56_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC56_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func56_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC56_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func56_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC56_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC56_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC56_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func57_in_sel_cfg.rs b/esp32p4/src/gpio/func57_in_sel_cfg.rs new file mode 100644 index 0000000000..4b63fa4b7d --- /dev/null +++ b/esp32p4/src/gpio/func57_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC57_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC57_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC57_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC57_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC57_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC57_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC57_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC57_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC57_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC57_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG57_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG57_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG57_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG57_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func57_in_sel(&self) -> FUNC57_IN_SEL_R { + FUNC57_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func57_in_inv_sel(&self) -> FUNC57_IN_INV_SEL_R { + FUNC57_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig57_in_sel(&self) -> SIG57_IN_SEL_R { + SIG57_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC57_IN_SEL_CFG") + .field( + "func57_in_sel", + &format_args!("{}", self.func57_in_sel().bits()), + ) + .field( + "func57_in_inv_sel", + &format_args!("{}", self.func57_in_inv_sel().bit()), + ) + .field( + "sig57_in_sel", + &format_args!("{}", self.sig57_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func57_in_sel(&mut self) -> FUNC57_IN_SEL_W { + FUNC57_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func57_in_inv_sel(&mut self) -> FUNC57_IN_INV_SEL_W { + FUNC57_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig57_in_sel(&mut self) -> SIG57_IN_SEL_W { + SIG57_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func57_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func57_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC57_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC57_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func57_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC57_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func57_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC57_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC57_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC57_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func58_in_sel_cfg.rs b/esp32p4/src/gpio/func58_in_sel_cfg.rs new file mode 100644 index 0000000000..fec503bf56 --- /dev/null +++ b/esp32p4/src/gpio/func58_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC58_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC58_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC58_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC58_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC58_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC58_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC58_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC58_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC58_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC58_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG58_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG58_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG58_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG58_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func58_in_sel(&self) -> FUNC58_IN_SEL_R { + FUNC58_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func58_in_inv_sel(&self) -> FUNC58_IN_INV_SEL_R { + FUNC58_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig58_in_sel(&self) -> SIG58_IN_SEL_R { + SIG58_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC58_IN_SEL_CFG") + .field( + "func58_in_sel", + &format_args!("{}", self.func58_in_sel().bits()), + ) + .field( + "func58_in_inv_sel", + &format_args!("{}", self.func58_in_inv_sel().bit()), + ) + .field( + "sig58_in_sel", + &format_args!("{}", self.sig58_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func58_in_sel(&mut self) -> FUNC58_IN_SEL_W { + FUNC58_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func58_in_inv_sel(&mut self) -> FUNC58_IN_INV_SEL_W { + FUNC58_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig58_in_sel(&mut self) -> SIG58_IN_SEL_W { + SIG58_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func58_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func58_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC58_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC58_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func58_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC58_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func58_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC58_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC58_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC58_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func59_in_sel_cfg.rs b/esp32p4/src/gpio/func59_in_sel_cfg.rs new file mode 100644 index 0000000000..5754aa2dd5 --- /dev/null +++ b/esp32p4/src/gpio/func59_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC59_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC59_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC59_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC59_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC59_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC59_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC59_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC59_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC59_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC59_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG59_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG59_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG59_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG59_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func59_in_sel(&self) -> FUNC59_IN_SEL_R { + FUNC59_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func59_in_inv_sel(&self) -> FUNC59_IN_INV_SEL_R { + FUNC59_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig59_in_sel(&self) -> SIG59_IN_SEL_R { + SIG59_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC59_IN_SEL_CFG") + .field( + "func59_in_sel", + &format_args!("{}", self.func59_in_sel().bits()), + ) + .field( + "func59_in_inv_sel", + &format_args!("{}", self.func59_in_inv_sel().bit()), + ) + .field( + "sig59_in_sel", + &format_args!("{}", self.sig59_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func59_in_sel(&mut self) -> FUNC59_IN_SEL_W { + FUNC59_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func59_in_inv_sel(&mut self) -> FUNC59_IN_INV_SEL_W { + FUNC59_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig59_in_sel(&mut self) -> SIG59_IN_SEL_W { + SIG59_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func59_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func59_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC59_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC59_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func59_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC59_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func59_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC59_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC59_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC59_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func5_in_sel_cfg.rs b/esp32p4/src/gpio/func5_in_sel_cfg.rs new file mode 100644 index 0000000000..34976da9dd --- /dev/null +++ b/esp32p4/src/gpio/func5_in_sel_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `FUNC5_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC5_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC5_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC5_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC5_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC5_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC5_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC5_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC5_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC5_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG5_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG5_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG5_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG5_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func5_in_sel(&self) -> FUNC5_IN_SEL_R { + FUNC5_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func5_in_inv_sel(&self) -> FUNC5_IN_INV_SEL_R { + FUNC5_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig5_in_sel(&self) -> SIG5_IN_SEL_R { + SIG5_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC5_IN_SEL_CFG") + .field( + "func5_in_sel", + &format_args!("{}", self.func5_in_sel().bits()), + ) + .field( + "func5_in_inv_sel", + &format_args!("{}", self.func5_in_inv_sel().bit()), + ) + .field("sig5_in_sel", &format_args!("{}", self.sig5_in_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func5_in_sel(&mut self) -> FUNC5_IN_SEL_W { + FUNC5_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func5_in_inv_sel(&mut self) -> FUNC5_IN_INV_SEL_W { + FUNC5_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig5_in_sel(&mut self) -> SIG5_IN_SEL_W { + SIG5_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func5_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func5_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC5_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC5_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func5_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC5_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func5_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC5_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC5_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC5_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func60_in_sel_cfg.rs b/esp32p4/src/gpio/func60_in_sel_cfg.rs new file mode 100644 index 0000000000..e698de8167 --- /dev/null +++ b/esp32p4/src/gpio/func60_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC60_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC60_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC60_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC60_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC60_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC60_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC60_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC60_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC60_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC60_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG60_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG60_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG60_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG60_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func60_in_sel(&self) -> FUNC60_IN_SEL_R { + FUNC60_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func60_in_inv_sel(&self) -> FUNC60_IN_INV_SEL_R { + FUNC60_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig60_in_sel(&self) -> SIG60_IN_SEL_R { + SIG60_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC60_IN_SEL_CFG") + .field( + "func60_in_sel", + &format_args!("{}", self.func60_in_sel().bits()), + ) + .field( + "func60_in_inv_sel", + &format_args!("{}", self.func60_in_inv_sel().bit()), + ) + .field( + "sig60_in_sel", + &format_args!("{}", self.sig60_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func60_in_sel(&mut self) -> FUNC60_IN_SEL_W { + FUNC60_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func60_in_inv_sel(&mut self) -> FUNC60_IN_INV_SEL_W { + FUNC60_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig60_in_sel(&mut self) -> SIG60_IN_SEL_W { + SIG60_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func60_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func60_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC60_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC60_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func60_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC60_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func60_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC60_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC60_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC60_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func61_in_sel_cfg.rs b/esp32p4/src/gpio/func61_in_sel_cfg.rs new file mode 100644 index 0000000000..c1907d9af2 --- /dev/null +++ b/esp32p4/src/gpio/func61_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC61_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC61_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC61_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC61_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC61_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC61_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC61_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC61_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC61_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC61_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG61_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG61_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG61_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG61_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func61_in_sel(&self) -> FUNC61_IN_SEL_R { + FUNC61_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func61_in_inv_sel(&self) -> FUNC61_IN_INV_SEL_R { + FUNC61_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig61_in_sel(&self) -> SIG61_IN_SEL_R { + SIG61_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC61_IN_SEL_CFG") + .field( + "func61_in_sel", + &format_args!("{}", self.func61_in_sel().bits()), + ) + .field( + "func61_in_inv_sel", + &format_args!("{}", self.func61_in_inv_sel().bit()), + ) + .field( + "sig61_in_sel", + &format_args!("{}", self.sig61_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func61_in_sel(&mut self) -> FUNC61_IN_SEL_W { + FUNC61_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func61_in_inv_sel(&mut self) -> FUNC61_IN_INV_SEL_W { + FUNC61_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig61_in_sel(&mut self) -> SIG61_IN_SEL_W { + SIG61_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func61_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func61_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC61_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC61_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func61_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC61_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func61_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC61_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC61_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC61_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func62_in_sel_cfg.rs b/esp32p4/src/gpio/func62_in_sel_cfg.rs new file mode 100644 index 0000000000..03c51cc7a0 --- /dev/null +++ b/esp32p4/src/gpio/func62_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC62_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC62_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC62_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC62_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC62_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC62_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC62_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC62_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC62_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC62_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG62_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG62_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG62_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG62_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func62_in_sel(&self) -> FUNC62_IN_SEL_R { + FUNC62_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func62_in_inv_sel(&self) -> FUNC62_IN_INV_SEL_R { + FUNC62_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig62_in_sel(&self) -> SIG62_IN_SEL_R { + SIG62_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC62_IN_SEL_CFG") + .field( + "func62_in_sel", + &format_args!("{}", self.func62_in_sel().bits()), + ) + .field( + "func62_in_inv_sel", + &format_args!("{}", self.func62_in_inv_sel().bit()), + ) + .field( + "sig62_in_sel", + &format_args!("{}", self.sig62_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func62_in_sel(&mut self) -> FUNC62_IN_SEL_W { + FUNC62_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func62_in_inv_sel(&mut self) -> FUNC62_IN_INV_SEL_W { + FUNC62_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig62_in_sel(&mut self) -> SIG62_IN_SEL_W { + SIG62_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func62_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func62_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC62_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC62_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func62_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC62_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func62_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC62_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC62_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC62_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func63_in_sel_cfg.rs b/esp32p4/src/gpio/func63_in_sel_cfg.rs new file mode 100644 index 0000000000..d00dc35196 --- /dev/null +++ b/esp32p4/src/gpio/func63_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC63_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC63_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC63_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC63_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC63_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC63_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC63_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC63_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC63_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC63_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG63_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG63_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG63_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG63_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func63_in_sel(&self) -> FUNC63_IN_SEL_R { + FUNC63_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func63_in_inv_sel(&self) -> FUNC63_IN_INV_SEL_R { + FUNC63_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig63_in_sel(&self) -> SIG63_IN_SEL_R { + SIG63_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC63_IN_SEL_CFG") + .field( + "func63_in_sel", + &format_args!("{}", self.func63_in_sel().bits()), + ) + .field( + "func63_in_inv_sel", + &format_args!("{}", self.func63_in_inv_sel().bit()), + ) + .field( + "sig63_in_sel", + &format_args!("{}", self.sig63_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func63_in_sel(&mut self) -> FUNC63_IN_SEL_W { + FUNC63_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func63_in_inv_sel(&mut self) -> FUNC63_IN_INV_SEL_W { + FUNC63_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig63_in_sel(&mut self) -> SIG63_IN_SEL_W { + SIG63_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func63_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func63_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC63_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC63_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func63_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC63_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func63_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC63_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC63_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC63_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func64_in_sel_cfg.rs b/esp32p4/src/gpio/func64_in_sel_cfg.rs new file mode 100644 index 0000000000..4a3271a7cd --- /dev/null +++ b/esp32p4/src/gpio/func64_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC64_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC64_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC64_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC64_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC64_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC64_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC64_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC64_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC64_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC64_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG64_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG64_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG64_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG64_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func64_in_sel(&self) -> FUNC64_IN_SEL_R { + FUNC64_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func64_in_inv_sel(&self) -> FUNC64_IN_INV_SEL_R { + FUNC64_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig64_in_sel(&self) -> SIG64_IN_SEL_R { + SIG64_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC64_IN_SEL_CFG") + .field( + "func64_in_sel", + &format_args!("{}", self.func64_in_sel().bits()), + ) + .field( + "func64_in_inv_sel", + &format_args!("{}", self.func64_in_inv_sel().bit()), + ) + .field( + "sig64_in_sel", + &format_args!("{}", self.sig64_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func64_in_sel(&mut self) -> FUNC64_IN_SEL_W { + FUNC64_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func64_in_inv_sel(&mut self) -> FUNC64_IN_INV_SEL_W { + FUNC64_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig64_in_sel(&mut self) -> SIG64_IN_SEL_W { + SIG64_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func64_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func64_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC64_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC64_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func64_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC64_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func64_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC64_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC64_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC64_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func65_in_sel_cfg.rs b/esp32p4/src/gpio/func65_in_sel_cfg.rs new file mode 100644 index 0000000000..af4a2fbe22 --- /dev/null +++ b/esp32p4/src/gpio/func65_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC65_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC65_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC65_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC65_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC65_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC65_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC65_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC65_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC65_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC65_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG65_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG65_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG65_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG65_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func65_in_sel(&self) -> FUNC65_IN_SEL_R { + FUNC65_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func65_in_inv_sel(&self) -> FUNC65_IN_INV_SEL_R { + FUNC65_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig65_in_sel(&self) -> SIG65_IN_SEL_R { + SIG65_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC65_IN_SEL_CFG") + .field( + "func65_in_sel", + &format_args!("{}", self.func65_in_sel().bits()), + ) + .field( + "func65_in_inv_sel", + &format_args!("{}", self.func65_in_inv_sel().bit()), + ) + .field( + "sig65_in_sel", + &format_args!("{}", self.sig65_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func65_in_sel(&mut self) -> FUNC65_IN_SEL_W { + FUNC65_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func65_in_inv_sel(&mut self) -> FUNC65_IN_INV_SEL_W { + FUNC65_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig65_in_sel(&mut self) -> SIG65_IN_SEL_W { + SIG65_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func65_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func65_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC65_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC65_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func65_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC65_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func65_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC65_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC65_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC65_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func66_in_sel_cfg.rs b/esp32p4/src/gpio/func66_in_sel_cfg.rs new file mode 100644 index 0000000000..24b35659ea --- /dev/null +++ b/esp32p4/src/gpio/func66_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC66_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC66_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC66_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC66_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC66_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC66_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC66_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC66_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC66_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC66_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG66_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG66_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG66_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG66_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func66_in_sel(&self) -> FUNC66_IN_SEL_R { + FUNC66_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func66_in_inv_sel(&self) -> FUNC66_IN_INV_SEL_R { + FUNC66_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig66_in_sel(&self) -> SIG66_IN_SEL_R { + SIG66_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC66_IN_SEL_CFG") + .field( + "func66_in_sel", + &format_args!("{}", self.func66_in_sel().bits()), + ) + .field( + "func66_in_inv_sel", + &format_args!("{}", self.func66_in_inv_sel().bit()), + ) + .field( + "sig66_in_sel", + &format_args!("{}", self.sig66_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func66_in_sel(&mut self) -> FUNC66_IN_SEL_W { + FUNC66_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func66_in_inv_sel(&mut self) -> FUNC66_IN_INV_SEL_W { + FUNC66_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig66_in_sel(&mut self) -> SIG66_IN_SEL_W { + SIG66_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func66_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func66_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC66_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC66_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func66_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC66_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func66_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC66_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC66_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC66_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func68_in_sel_cfg.rs b/esp32p4/src/gpio/func68_in_sel_cfg.rs new file mode 100644 index 0000000000..1e7990cbc9 --- /dev/null +++ b/esp32p4/src/gpio/func68_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC68_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC68_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC68_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC68_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC68_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC68_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC68_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC68_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC68_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC68_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG68_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG68_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG68_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG68_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func68_in_sel(&self) -> FUNC68_IN_SEL_R { + FUNC68_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func68_in_inv_sel(&self) -> FUNC68_IN_INV_SEL_R { + FUNC68_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig68_in_sel(&self) -> SIG68_IN_SEL_R { + SIG68_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC68_IN_SEL_CFG") + .field( + "func68_in_sel", + &format_args!("{}", self.func68_in_sel().bits()), + ) + .field( + "func68_in_inv_sel", + &format_args!("{}", self.func68_in_inv_sel().bit()), + ) + .field( + "sig68_in_sel", + &format_args!("{}", self.sig68_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func68_in_sel(&mut self) -> FUNC68_IN_SEL_W { + FUNC68_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func68_in_inv_sel(&mut self) -> FUNC68_IN_INV_SEL_W { + FUNC68_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig68_in_sel(&mut self) -> SIG68_IN_SEL_W { + SIG68_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func68_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func68_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC68_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC68_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func68_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC68_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func68_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC68_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC68_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC68_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func69_in_sel_cfg.rs b/esp32p4/src/gpio/func69_in_sel_cfg.rs new file mode 100644 index 0000000000..0b52d562ec --- /dev/null +++ b/esp32p4/src/gpio/func69_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC69_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC69_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC69_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC69_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC69_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC69_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC69_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC69_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC69_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC69_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG69_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG69_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG69_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG69_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func69_in_sel(&self) -> FUNC69_IN_SEL_R { + FUNC69_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func69_in_inv_sel(&self) -> FUNC69_IN_INV_SEL_R { + FUNC69_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig69_in_sel(&self) -> SIG69_IN_SEL_R { + SIG69_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC69_IN_SEL_CFG") + .field( + "func69_in_sel", + &format_args!("{}", self.func69_in_sel().bits()), + ) + .field( + "func69_in_inv_sel", + &format_args!("{}", self.func69_in_inv_sel().bit()), + ) + .field( + "sig69_in_sel", + &format_args!("{}", self.sig69_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func69_in_sel(&mut self) -> FUNC69_IN_SEL_W { + FUNC69_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func69_in_inv_sel(&mut self) -> FUNC69_IN_INV_SEL_W { + FUNC69_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig69_in_sel(&mut self) -> SIG69_IN_SEL_W { + SIG69_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func69_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func69_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC69_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC69_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func69_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC69_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func69_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC69_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC69_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC69_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func6_in_sel_cfg.rs b/esp32p4/src/gpio/func6_in_sel_cfg.rs new file mode 100644 index 0000000000..583be2c451 --- /dev/null +++ b/esp32p4/src/gpio/func6_in_sel_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `FUNC6_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC6_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC6_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC6_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC6_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC6_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC6_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC6_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC6_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC6_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG6_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG6_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG6_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG6_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func6_in_sel(&self) -> FUNC6_IN_SEL_R { + FUNC6_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func6_in_inv_sel(&self) -> FUNC6_IN_INV_SEL_R { + FUNC6_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig6_in_sel(&self) -> SIG6_IN_SEL_R { + SIG6_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC6_IN_SEL_CFG") + .field( + "func6_in_sel", + &format_args!("{}", self.func6_in_sel().bits()), + ) + .field( + "func6_in_inv_sel", + &format_args!("{}", self.func6_in_inv_sel().bit()), + ) + .field("sig6_in_sel", &format_args!("{}", self.sig6_in_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func6_in_sel(&mut self) -> FUNC6_IN_SEL_W { + FUNC6_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func6_in_inv_sel(&mut self) -> FUNC6_IN_INV_SEL_W { + FUNC6_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig6_in_sel(&mut self) -> SIG6_IN_SEL_W { + SIG6_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func6_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func6_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC6_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC6_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func6_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC6_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func6_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC6_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC6_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC6_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func70_in_sel_cfg.rs b/esp32p4/src/gpio/func70_in_sel_cfg.rs new file mode 100644 index 0000000000..0da4cd8e17 --- /dev/null +++ b/esp32p4/src/gpio/func70_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC70_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC70_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC70_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC70_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC70_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC70_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC70_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC70_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC70_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC70_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG70_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG70_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG70_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG70_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func70_in_sel(&self) -> FUNC70_IN_SEL_R { + FUNC70_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func70_in_inv_sel(&self) -> FUNC70_IN_INV_SEL_R { + FUNC70_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig70_in_sel(&self) -> SIG70_IN_SEL_R { + SIG70_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC70_IN_SEL_CFG") + .field( + "func70_in_sel", + &format_args!("{}", self.func70_in_sel().bits()), + ) + .field( + "func70_in_inv_sel", + &format_args!("{}", self.func70_in_inv_sel().bit()), + ) + .field( + "sig70_in_sel", + &format_args!("{}", self.sig70_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func70_in_sel(&mut self) -> FUNC70_IN_SEL_W { + FUNC70_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func70_in_inv_sel(&mut self) -> FUNC70_IN_INV_SEL_W { + FUNC70_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig70_in_sel(&mut self) -> SIG70_IN_SEL_W { + SIG70_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func70_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func70_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC70_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC70_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func70_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC70_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func70_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC70_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC70_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC70_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func71_in_sel_cfg.rs b/esp32p4/src/gpio/func71_in_sel_cfg.rs new file mode 100644 index 0000000000..555c7d12d9 --- /dev/null +++ b/esp32p4/src/gpio/func71_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC71_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC71_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC71_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC71_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC71_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC71_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC71_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC71_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC71_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC71_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG71_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG71_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG71_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG71_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func71_in_sel(&self) -> FUNC71_IN_SEL_R { + FUNC71_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func71_in_inv_sel(&self) -> FUNC71_IN_INV_SEL_R { + FUNC71_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig71_in_sel(&self) -> SIG71_IN_SEL_R { + SIG71_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC71_IN_SEL_CFG") + .field( + "func71_in_sel", + &format_args!("{}", self.func71_in_sel().bits()), + ) + .field( + "func71_in_inv_sel", + &format_args!("{}", self.func71_in_inv_sel().bit()), + ) + .field( + "sig71_in_sel", + &format_args!("{}", self.sig71_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func71_in_sel(&mut self) -> FUNC71_IN_SEL_W { + FUNC71_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func71_in_inv_sel(&mut self) -> FUNC71_IN_INV_SEL_W { + FUNC71_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig71_in_sel(&mut self) -> SIG71_IN_SEL_W { + SIG71_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func71_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func71_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC71_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC71_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func71_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC71_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func71_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC71_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC71_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC71_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func74_in_sel_cfg.rs b/esp32p4/src/gpio/func74_in_sel_cfg.rs new file mode 100644 index 0000000000..c870b55d71 --- /dev/null +++ b/esp32p4/src/gpio/func74_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC74_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC74_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC74_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC74_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC74_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC74_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC74_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC74_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC74_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC74_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG74_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG74_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG74_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG74_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func74_in_sel(&self) -> FUNC74_IN_SEL_R { + FUNC74_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func74_in_inv_sel(&self) -> FUNC74_IN_INV_SEL_R { + FUNC74_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig74_in_sel(&self) -> SIG74_IN_SEL_R { + SIG74_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC74_IN_SEL_CFG") + .field( + "func74_in_sel", + &format_args!("{}", self.func74_in_sel().bits()), + ) + .field( + "func74_in_inv_sel", + &format_args!("{}", self.func74_in_inv_sel().bit()), + ) + .field( + "sig74_in_sel", + &format_args!("{}", self.sig74_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func74_in_sel(&mut self) -> FUNC74_IN_SEL_W { + FUNC74_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func74_in_inv_sel(&mut self) -> FUNC74_IN_INV_SEL_W { + FUNC74_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig74_in_sel(&mut self) -> SIG74_IN_SEL_W { + SIG74_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func74_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func74_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC74_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC74_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func74_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC74_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func74_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC74_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC74_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC74_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func75_in_sel_cfg.rs b/esp32p4/src/gpio/func75_in_sel_cfg.rs new file mode 100644 index 0000000000..f201b4aca0 --- /dev/null +++ b/esp32p4/src/gpio/func75_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC75_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC75_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC75_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC75_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC75_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC75_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC75_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC75_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC75_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC75_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG75_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG75_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG75_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG75_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func75_in_sel(&self) -> FUNC75_IN_SEL_R { + FUNC75_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func75_in_inv_sel(&self) -> FUNC75_IN_INV_SEL_R { + FUNC75_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig75_in_sel(&self) -> SIG75_IN_SEL_R { + SIG75_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC75_IN_SEL_CFG") + .field( + "func75_in_sel", + &format_args!("{}", self.func75_in_sel().bits()), + ) + .field( + "func75_in_inv_sel", + &format_args!("{}", self.func75_in_inv_sel().bit()), + ) + .field( + "sig75_in_sel", + &format_args!("{}", self.sig75_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func75_in_sel(&mut self) -> FUNC75_IN_SEL_W { + FUNC75_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func75_in_inv_sel(&mut self) -> FUNC75_IN_INV_SEL_W { + FUNC75_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig75_in_sel(&mut self) -> SIG75_IN_SEL_W { + SIG75_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func75_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func75_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC75_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC75_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func75_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC75_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func75_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC75_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC75_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC75_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func76_in_sel_cfg.rs b/esp32p4/src/gpio/func76_in_sel_cfg.rs new file mode 100644 index 0000000000..6f29358dd0 --- /dev/null +++ b/esp32p4/src/gpio/func76_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC76_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC76_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC76_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC76_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC76_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC76_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC76_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC76_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC76_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC76_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG76_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG76_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG76_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG76_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func76_in_sel(&self) -> FUNC76_IN_SEL_R { + FUNC76_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func76_in_inv_sel(&self) -> FUNC76_IN_INV_SEL_R { + FUNC76_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig76_in_sel(&self) -> SIG76_IN_SEL_R { + SIG76_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC76_IN_SEL_CFG") + .field( + "func76_in_sel", + &format_args!("{}", self.func76_in_sel().bits()), + ) + .field( + "func76_in_inv_sel", + &format_args!("{}", self.func76_in_inv_sel().bit()), + ) + .field( + "sig76_in_sel", + &format_args!("{}", self.sig76_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func76_in_sel(&mut self) -> FUNC76_IN_SEL_W { + FUNC76_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func76_in_inv_sel(&mut self) -> FUNC76_IN_INV_SEL_W { + FUNC76_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig76_in_sel(&mut self) -> SIG76_IN_SEL_W { + SIG76_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func76_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func76_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC76_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC76_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func76_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC76_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func76_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC76_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC76_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC76_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func77_in_sel_cfg.rs b/esp32p4/src/gpio/func77_in_sel_cfg.rs new file mode 100644 index 0000000000..7b2e05b7b0 --- /dev/null +++ b/esp32p4/src/gpio/func77_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC77_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC77_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC77_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC77_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC77_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC77_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC77_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC77_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC77_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC77_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG77_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG77_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG77_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG77_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func77_in_sel(&self) -> FUNC77_IN_SEL_R { + FUNC77_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func77_in_inv_sel(&self) -> FUNC77_IN_INV_SEL_R { + FUNC77_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig77_in_sel(&self) -> SIG77_IN_SEL_R { + SIG77_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC77_IN_SEL_CFG") + .field( + "func77_in_sel", + &format_args!("{}", self.func77_in_sel().bits()), + ) + .field( + "func77_in_inv_sel", + &format_args!("{}", self.func77_in_inv_sel().bit()), + ) + .field( + "sig77_in_sel", + &format_args!("{}", self.sig77_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func77_in_sel(&mut self) -> FUNC77_IN_SEL_W { + FUNC77_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func77_in_inv_sel(&mut self) -> FUNC77_IN_INV_SEL_W { + FUNC77_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig77_in_sel(&mut self) -> SIG77_IN_SEL_W { + SIG77_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func77_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func77_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC77_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC77_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func77_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC77_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func77_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC77_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC77_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC77_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func78_in_sel_cfg.rs b/esp32p4/src/gpio/func78_in_sel_cfg.rs new file mode 100644 index 0000000000..e142426d5e --- /dev/null +++ b/esp32p4/src/gpio/func78_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC78_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC78_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC78_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC78_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC78_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC78_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC78_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC78_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC78_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC78_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG78_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG78_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG78_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG78_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func78_in_sel(&self) -> FUNC78_IN_SEL_R { + FUNC78_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func78_in_inv_sel(&self) -> FUNC78_IN_INV_SEL_R { + FUNC78_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig78_in_sel(&self) -> SIG78_IN_SEL_R { + SIG78_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC78_IN_SEL_CFG") + .field( + "func78_in_sel", + &format_args!("{}", self.func78_in_sel().bits()), + ) + .field( + "func78_in_inv_sel", + &format_args!("{}", self.func78_in_inv_sel().bit()), + ) + .field( + "sig78_in_sel", + &format_args!("{}", self.sig78_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func78_in_sel(&mut self) -> FUNC78_IN_SEL_W { + FUNC78_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func78_in_inv_sel(&mut self) -> FUNC78_IN_INV_SEL_W { + FUNC78_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig78_in_sel(&mut self) -> SIG78_IN_SEL_W { + SIG78_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func78_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func78_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC78_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC78_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func78_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC78_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func78_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC78_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC78_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC78_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func7_in_sel_cfg.rs b/esp32p4/src/gpio/func7_in_sel_cfg.rs new file mode 100644 index 0000000000..45f202dc17 --- /dev/null +++ b/esp32p4/src/gpio/func7_in_sel_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `FUNC7_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC7_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC7_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC7_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC7_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC7_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC7_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC7_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC7_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC7_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG7_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG7_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG7_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG7_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func7_in_sel(&self) -> FUNC7_IN_SEL_R { + FUNC7_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func7_in_inv_sel(&self) -> FUNC7_IN_INV_SEL_R { + FUNC7_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig7_in_sel(&self) -> SIG7_IN_SEL_R { + SIG7_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC7_IN_SEL_CFG") + .field( + "func7_in_sel", + &format_args!("{}", self.func7_in_sel().bits()), + ) + .field( + "func7_in_inv_sel", + &format_args!("{}", self.func7_in_inv_sel().bit()), + ) + .field("sig7_in_sel", &format_args!("{}", self.sig7_in_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func7_in_sel(&mut self) -> FUNC7_IN_SEL_W { + FUNC7_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func7_in_inv_sel(&mut self) -> FUNC7_IN_INV_SEL_W { + FUNC7_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig7_in_sel(&mut self) -> SIG7_IN_SEL_W { + SIG7_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func7_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func7_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC7_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC7_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func7_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC7_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func7_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC7_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC7_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC7_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func80_in_sel_cfg.rs b/esp32p4/src/gpio/func80_in_sel_cfg.rs new file mode 100644 index 0000000000..101126b4d4 --- /dev/null +++ b/esp32p4/src/gpio/func80_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC80_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC80_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC80_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC80_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC80_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC80_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC80_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC80_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC80_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC80_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG80_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG80_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG80_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG80_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func80_in_sel(&self) -> FUNC80_IN_SEL_R { + FUNC80_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func80_in_inv_sel(&self) -> FUNC80_IN_INV_SEL_R { + FUNC80_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig80_in_sel(&self) -> SIG80_IN_SEL_R { + SIG80_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC80_IN_SEL_CFG") + .field( + "func80_in_sel", + &format_args!("{}", self.func80_in_sel().bits()), + ) + .field( + "func80_in_inv_sel", + &format_args!("{}", self.func80_in_inv_sel().bit()), + ) + .field( + "sig80_in_sel", + &format_args!("{}", self.sig80_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func80_in_sel(&mut self) -> FUNC80_IN_SEL_W { + FUNC80_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func80_in_inv_sel(&mut self) -> FUNC80_IN_INV_SEL_W { + FUNC80_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig80_in_sel(&mut self) -> SIG80_IN_SEL_W { + SIG80_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func80_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func80_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC80_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC80_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func80_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC80_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func80_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC80_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC80_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC80_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func83_in_sel_cfg.rs b/esp32p4/src/gpio/func83_in_sel_cfg.rs new file mode 100644 index 0000000000..f9c8d9e8b1 --- /dev/null +++ b/esp32p4/src/gpio/func83_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC83_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC83_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC83_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC83_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC83_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC83_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC83_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC83_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC83_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC83_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG83_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG83_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG83_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG83_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func83_in_sel(&self) -> FUNC83_IN_SEL_R { + FUNC83_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func83_in_inv_sel(&self) -> FUNC83_IN_INV_SEL_R { + FUNC83_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig83_in_sel(&self) -> SIG83_IN_SEL_R { + SIG83_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC83_IN_SEL_CFG") + .field( + "func83_in_sel", + &format_args!("{}", self.func83_in_sel().bits()), + ) + .field( + "func83_in_inv_sel", + &format_args!("{}", self.func83_in_inv_sel().bit()), + ) + .field( + "sig83_in_sel", + &format_args!("{}", self.sig83_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func83_in_sel(&mut self) -> FUNC83_IN_SEL_W { + FUNC83_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func83_in_inv_sel(&mut self) -> FUNC83_IN_INV_SEL_W { + FUNC83_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig83_in_sel(&mut self) -> SIG83_IN_SEL_W { + SIG83_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func83_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func83_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC83_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC83_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func83_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC83_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func83_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC83_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC83_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC83_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func86_in_sel_cfg.rs b/esp32p4/src/gpio/func86_in_sel_cfg.rs new file mode 100644 index 0000000000..dabf2876f3 --- /dev/null +++ b/esp32p4/src/gpio/func86_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC86_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC86_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC86_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC86_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC86_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC86_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC86_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC86_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC86_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC86_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG86_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG86_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG86_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG86_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func86_in_sel(&self) -> FUNC86_IN_SEL_R { + FUNC86_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func86_in_inv_sel(&self) -> FUNC86_IN_INV_SEL_R { + FUNC86_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig86_in_sel(&self) -> SIG86_IN_SEL_R { + SIG86_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC86_IN_SEL_CFG") + .field( + "func86_in_sel", + &format_args!("{}", self.func86_in_sel().bits()), + ) + .field( + "func86_in_inv_sel", + &format_args!("{}", self.func86_in_inv_sel().bit()), + ) + .field( + "sig86_in_sel", + &format_args!("{}", self.sig86_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func86_in_sel(&mut self) -> FUNC86_IN_SEL_W { + FUNC86_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func86_in_inv_sel(&mut self) -> FUNC86_IN_INV_SEL_W { + FUNC86_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig86_in_sel(&mut self) -> SIG86_IN_SEL_W { + SIG86_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func86_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func86_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC86_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC86_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func86_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC86_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func86_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC86_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC86_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC86_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func89_in_sel_cfg.rs b/esp32p4/src/gpio/func89_in_sel_cfg.rs new file mode 100644 index 0000000000..0978990c18 --- /dev/null +++ b/esp32p4/src/gpio/func89_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC89_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC89_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC89_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC89_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC89_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC89_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC89_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC89_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC89_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC89_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG89_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG89_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG89_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG89_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func89_in_sel(&self) -> FUNC89_IN_SEL_R { + FUNC89_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func89_in_inv_sel(&self) -> FUNC89_IN_INV_SEL_R { + FUNC89_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig89_in_sel(&self) -> SIG89_IN_SEL_R { + SIG89_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC89_IN_SEL_CFG") + .field( + "func89_in_sel", + &format_args!("{}", self.func89_in_sel().bits()), + ) + .field( + "func89_in_inv_sel", + &format_args!("{}", self.func89_in_inv_sel().bit()), + ) + .field( + "sig89_in_sel", + &format_args!("{}", self.sig89_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func89_in_sel(&mut self) -> FUNC89_IN_SEL_W { + FUNC89_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func89_in_inv_sel(&mut self) -> FUNC89_IN_INV_SEL_W { + FUNC89_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig89_in_sel(&mut self) -> SIG89_IN_SEL_W { + SIG89_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func89_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func89_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC89_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC89_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func89_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC89_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func89_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC89_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC89_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC89_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func8_in_sel_cfg.rs b/esp32p4/src/gpio/func8_in_sel_cfg.rs new file mode 100644 index 0000000000..06c778a955 --- /dev/null +++ b/esp32p4/src/gpio/func8_in_sel_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `FUNC8_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC8_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC8_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC8_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC8_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC8_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC8_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC8_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC8_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC8_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG8_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG8_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG8_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG8_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func8_in_sel(&self) -> FUNC8_IN_SEL_R { + FUNC8_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func8_in_inv_sel(&self) -> FUNC8_IN_INV_SEL_R { + FUNC8_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig8_in_sel(&self) -> SIG8_IN_SEL_R { + SIG8_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC8_IN_SEL_CFG") + .field( + "func8_in_sel", + &format_args!("{}", self.func8_in_sel().bits()), + ) + .field( + "func8_in_inv_sel", + &format_args!("{}", self.func8_in_inv_sel().bit()), + ) + .field("sig8_in_sel", &format_args!("{}", self.sig8_in_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func8_in_sel(&mut self) -> FUNC8_IN_SEL_W { + FUNC8_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func8_in_inv_sel(&mut self) -> FUNC8_IN_INV_SEL_W { + FUNC8_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig8_in_sel(&mut self) -> SIG8_IN_SEL_W { + SIG8_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func8_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func8_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC8_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC8_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func8_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC8_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func8_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC8_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC8_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC8_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func90_in_sel_cfg.rs b/esp32p4/src/gpio/func90_in_sel_cfg.rs new file mode 100644 index 0000000000..883064ff5b --- /dev/null +++ b/esp32p4/src/gpio/func90_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC90_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC90_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC90_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC90_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC90_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC90_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC90_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC90_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC90_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC90_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG90_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG90_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG90_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG90_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func90_in_sel(&self) -> FUNC90_IN_SEL_R { + FUNC90_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func90_in_inv_sel(&self) -> FUNC90_IN_INV_SEL_R { + FUNC90_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig90_in_sel(&self) -> SIG90_IN_SEL_R { + SIG90_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC90_IN_SEL_CFG") + .field( + "func90_in_sel", + &format_args!("{}", self.func90_in_sel().bits()), + ) + .field( + "func90_in_inv_sel", + &format_args!("{}", self.func90_in_inv_sel().bit()), + ) + .field( + "sig90_in_sel", + &format_args!("{}", self.sig90_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func90_in_sel(&mut self) -> FUNC90_IN_SEL_W { + FUNC90_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func90_in_inv_sel(&mut self) -> FUNC90_IN_INV_SEL_W { + FUNC90_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig90_in_sel(&mut self) -> SIG90_IN_SEL_W { + SIG90_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func90_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func90_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC90_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC90_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func90_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC90_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func90_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC90_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC90_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC90_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func91_in_sel_cfg.rs b/esp32p4/src/gpio/func91_in_sel_cfg.rs new file mode 100644 index 0000000000..93e39140d6 --- /dev/null +++ b/esp32p4/src/gpio/func91_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC91_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC91_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC91_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC91_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC91_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC91_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC91_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC91_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC91_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC91_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG91_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG91_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG91_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG91_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func91_in_sel(&self) -> FUNC91_IN_SEL_R { + FUNC91_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func91_in_inv_sel(&self) -> FUNC91_IN_INV_SEL_R { + FUNC91_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig91_in_sel(&self) -> SIG91_IN_SEL_R { + SIG91_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC91_IN_SEL_CFG") + .field( + "func91_in_sel", + &format_args!("{}", self.func91_in_sel().bits()), + ) + .field( + "func91_in_inv_sel", + &format_args!("{}", self.func91_in_inv_sel().bit()), + ) + .field( + "sig91_in_sel", + &format_args!("{}", self.sig91_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func91_in_sel(&mut self) -> FUNC91_IN_SEL_W { + FUNC91_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func91_in_inv_sel(&mut self) -> FUNC91_IN_INV_SEL_W { + FUNC91_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig91_in_sel(&mut self) -> SIG91_IN_SEL_W { + SIG91_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func91_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func91_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC91_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC91_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func91_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC91_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func91_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC91_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC91_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC91_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func92_in_sel_cfg.rs b/esp32p4/src/gpio/func92_in_sel_cfg.rs new file mode 100644 index 0000000000..5e1a1a12d3 --- /dev/null +++ b/esp32p4/src/gpio/func92_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC92_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC92_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC92_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC92_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC92_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC92_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC92_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC92_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC92_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC92_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG92_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG92_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG92_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG92_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func92_in_sel(&self) -> FUNC92_IN_SEL_R { + FUNC92_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func92_in_inv_sel(&self) -> FUNC92_IN_INV_SEL_R { + FUNC92_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig92_in_sel(&self) -> SIG92_IN_SEL_R { + SIG92_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC92_IN_SEL_CFG") + .field( + "func92_in_sel", + &format_args!("{}", self.func92_in_sel().bits()), + ) + .field( + "func92_in_inv_sel", + &format_args!("{}", self.func92_in_inv_sel().bit()), + ) + .field( + "sig92_in_sel", + &format_args!("{}", self.sig92_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func92_in_sel(&mut self) -> FUNC92_IN_SEL_W { + FUNC92_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func92_in_inv_sel(&mut self) -> FUNC92_IN_INV_SEL_W { + FUNC92_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig92_in_sel(&mut self) -> SIG92_IN_SEL_W { + SIG92_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func92_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func92_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC92_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC92_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func92_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC92_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func92_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC92_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC92_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC92_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func93_in_sel_cfg.rs b/esp32p4/src/gpio/func93_in_sel_cfg.rs new file mode 100644 index 0000000000..54fde61ed0 --- /dev/null +++ b/esp32p4/src/gpio/func93_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC93_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC93_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC93_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC93_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC93_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC93_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC93_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC93_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC93_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC93_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG93_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG93_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG93_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG93_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func93_in_sel(&self) -> FUNC93_IN_SEL_R { + FUNC93_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func93_in_inv_sel(&self) -> FUNC93_IN_INV_SEL_R { + FUNC93_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig93_in_sel(&self) -> SIG93_IN_SEL_R { + SIG93_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC93_IN_SEL_CFG") + .field( + "func93_in_sel", + &format_args!("{}", self.func93_in_sel().bits()), + ) + .field( + "func93_in_inv_sel", + &format_args!("{}", self.func93_in_inv_sel().bit()), + ) + .field( + "sig93_in_sel", + &format_args!("{}", self.sig93_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func93_in_sel(&mut self) -> FUNC93_IN_SEL_W { + FUNC93_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func93_in_inv_sel(&mut self) -> FUNC93_IN_INV_SEL_W { + FUNC93_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig93_in_sel(&mut self) -> SIG93_IN_SEL_W { + SIG93_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func93_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func93_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC93_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC93_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func93_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC93_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func93_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC93_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC93_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC93_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func94_in_sel_cfg.rs b/esp32p4/src/gpio/func94_in_sel_cfg.rs new file mode 100644 index 0000000000..48d467aecb --- /dev/null +++ b/esp32p4/src/gpio/func94_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC94_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC94_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC94_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC94_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC94_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC94_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC94_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC94_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC94_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC94_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG94_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG94_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG94_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG94_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func94_in_sel(&self) -> FUNC94_IN_SEL_R { + FUNC94_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func94_in_inv_sel(&self) -> FUNC94_IN_INV_SEL_R { + FUNC94_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig94_in_sel(&self) -> SIG94_IN_SEL_R { + SIG94_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC94_IN_SEL_CFG") + .field( + "func94_in_sel", + &format_args!("{}", self.func94_in_sel().bits()), + ) + .field( + "func94_in_inv_sel", + &format_args!("{}", self.func94_in_inv_sel().bit()), + ) + .field( + "sig94_in_sel", + &format_args!("{}", self.sig94_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func94_in_sel(&mut self) -> FUNC94_IN_SEL_W { + FUNC94_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func94_in_inv_sel(&mut self) -> FUNC94_IN_INV_SEL_W { + FUNC94_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig94_in_sel(&mut self) -> SIG94_IN_SEL_W { + SIG94_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func94_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func94_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC94_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC94_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func94_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC94_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func94_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC94_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC94_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC94_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func95_in_sel_cfg.rs b/esp32p4/src/gpio/func95_in_sel_cfg.rs new file mode 100644 index 0000000000..6a1fcfa26e --- /dev/null +++ b/esp32p4/src/gpio/func95_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC95_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC95_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC95_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC95_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC95_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC95_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC95_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC95_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC95_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC95_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG95_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG95_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG95_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG95_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func95_in_sel(&self) -> FUNC95_IN_SEL_R { + FUNC95_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func95_in_inv_sel(&self) -> FUNC95_IN_INV_SEL_R { + FUNC95_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig95_in_sel(&self) -> SIG95_IN_SEL_R { + SIG95_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC95_IN_SEL_CFG") + .field( + "func95_in_sel", + &format_args!("{}", self.func95_in_sel().bits()), + ) + .field( + "func95_in_inv_sel", + &format_args!("{}", self.func95_in_inv_sel().bit()), + ) + .field( + "sig95_in_sel", + &format_args!("{}", self.sig95_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func95_in_sel(&mut self) -> FUNC95_IN_SEL_W { + FUNC95_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func95_in_inv_sel(&mut self) -> FUNC95_IN_INV_SEL_W { + FUNC95_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig95_in_sel(&mut self) -> SIG95_IN_SEL_W { + SIG95_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func95_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func95_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC95_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC95_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func95_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC95_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func95_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC95_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC95_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC95_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func96_in_sel_cfg.rs b/esp32p4/src/gpio/func96_in_sel_cfg.rs new file mode 100644 index 0000000000..ed55533c44 --- /dev/null +++ b/esp32p4/src/gpio/func96_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC96_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC96_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC96_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC96_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC96_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC96_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC96_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC96_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC96_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC96_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG96_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG96_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG96_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG96_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func96_in_sel(&self) -> FUNC96_IN_SEL_R { + FUNC96_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func96_in_inv_sel(&self) -> FUNC96_IN_INV_SEL_R { + FUNC96_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig96_in_sel(&self) -> SIG96_IN_SEL_R { + SIG96_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC96_IN_SEL_CFG") + .field( + "func96_in_sel", + &format_args!("{}", self.func96_in_sel().bits()), + ) + .field( + "func96_in_inv_sel", + &format_args!("{}", self.func96_in_inv_sel().bit()), + ) + .field( + "sig96_in_sel", + &format_args!("{}", self.sig96_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func96_in_sel(&mut self) -> FUNC96_IN_SEL_W { + FUNC96_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func96_in_inv_sel(&mut self) -> FUNC96_IN_INV_SEL_W { + FUNC96_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig96_in_sel(&mut self) -> SIG96_IN_SEL_W { + SIG96_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func96_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func96_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC96_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC96_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func96_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC96_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func96_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC96_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC96_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC96_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func97_in_sel_cfg.rs b/esp32p4/src/gpio/func97_in_sel_cfg.rs new file mode 100644 index 0000000000..9e6cfebeca --- /dev/null +++ b/esp32p4/src/gpio/func97_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC97_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC97_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC97_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC97_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC97_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC97_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC97_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC97_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC97_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC97_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG97_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG97_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG97_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG97_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func97_in_sel(&self) -> FUNC97_IN_SEL_R { + FUNC97_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func97_in_inv_sel(&self) -> FUNC97_IN_INV_SEL_R { + FUNC97_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig97_in_sel(&self) -> SIG97_IN_SEL_R { + SIG97_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC97_IN_SEL_CFG") + .field( + "func97_in_sel", + &format_args!("{}", self.func97_in_sel().bits()), + ) + .field( + "func97_in_inv_sel", + &format_args!("{}", self.func97_in_inv_sel().bit()), + ) + .field( + "sig97_in_sel", + &format_args!("{}", self.sig97_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func97_in_sel(&mut self) -> FUNC97_IN_SEL_W { + FUNC97_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func97_in_inv_sel(&mut self) -> FUNC97_IN_INV_SEL_W { + FUNC97_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig97_in_sel(&mut self) -> SIG97_IN_SEL_W { + SIG97_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func97_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func97_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC97_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC97_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func97_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC97_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func97_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC97_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC97_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC97_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func98_in_sel_cfg.rs b/esp32p4/src/gpio/func98_in_sel_cfg.rs new file mode 100644 index 0000000000..5d926f49a9 --- /dev/null +++ b/esp32p4/src/gpio/func98_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC98_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC98_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC98_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC98_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC98_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC98_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC98_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC98_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC98_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC98_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG98_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG98_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG98_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG98_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func98_in_sel(&self) -> FUNC98_IN_SEL_R { + FUNC98_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func98_in_inv_sel(&self) -> FUNC98_IN_INV_SEL_R { + FUNC98_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig98_in_sel(&self) -> SIG98_IN_SEL_R { + SIG98_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC98_IN_SEL_CFG") + .field( + "func98_in_sel", + &format_args!("{}", self.func98_in_sel().bits()), + ) + .field( + "func98_in_inv_sel", + &format_args!("{}", self.func98_in_inv_sel().bit()), + ) + .field( + "sig98_in_sel", + &format_args!("{}", self.sig98_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func98_in_sel(&mut self) -> FUNC98_IN_SEL_W { + FUNC98_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func98_in_inv_sel(&mut self) -> FUNC98_IN_INV_SEL_W { + FUNC98_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig98_in_sel(&mut self) -> SIG98_IN_SEL_W { + SIG98_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func98_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func98_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC98_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC98_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func98_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC98_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func98_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC98_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC98_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC98_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func99_in_sel_cfg.rs b/esp32p4/src/gpio/func99_in_sel_cfg.rs new file mode 100644 index 0000000000..0a11a12654 --- /dev/null +++ b/esp32p4/src/gpio/func99_in_sel_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FUNC99_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC99_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC99_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC99_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC99_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC99_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC99_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC99_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC99_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC99_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG99_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG99_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG99_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG99_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func99_in_sel(&self) -> FUNC99_IN_SEL_R { + FUNC99_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func99_in_inv_sel(&self) -> FUNC99_IN_INV_SEL_R { + FUNC99_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig99_in_sel(&self) -> SIG99_IN_SEL_R { + SIG99_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC99_IN_SEL_CFG") + .field( + "func99_in_sel", + &format_args!("{}", self.func99_in_sel().bits()), + ) + .field( + "func99_in_inv_sel", + &format_args!("{}", self.func99_in_inv_sel().bit()), + ) + .field( + "sig99_in_sel", + &format_args!("{}", self.sig99_in_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func99_in_sel(&mut self) -> FUNC99_IN_SEL_W { + FUNC99_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func99_in_inv_sel(&mut self) -> FUNC99_IN_INV_SEL_W { + FUNC99_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig99_in_sel(&mut self) -> SIG99_IN_SEL_W { + SIG99_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func99_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func99_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC99_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC99_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func99_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC99_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func99_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC99_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC99_IN_SEL_CFG to value 0x3e"] +impl crate::Resettable for FUNC99_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/gpio/func9_in_sel_cfg.rs b/esp32p4/src/gpio/func9_in_sel_cfg.rs new file mode 100644 index 0000000000..b2eed6f442 --- /dev/null +++ b/esp32p4/src/gpio/func9_in_sel_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `FUNC9_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC9_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC9_IN_SEL` reader - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC9_IN_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC9_IN_SEL` writer - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] +pub type FUNC9_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FUNC9_IN_INV_SEL` reader - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC9_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC9_IN_INV_SEL` writer - set this bit to invert input signal. 1:invert. 0:not invert."] +pub type FUNC9_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIG9_IN_SEL` reader - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG9_IN_SEL_R = crate::BitReader; +#[doc = "Field `SIG9_IN_SEL` writer - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] +pub type SIG9_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + pub fn func9_in_sel(&self) -> FUNC9_IN_SEL_R { + FUNC9_IN_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + pub fn func9_in_inv_sel(&self) -> FUNC9_IN_INV_SEL_R { + FUNC9_IN_INV_SEL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + pub fn sig9_in_sel(&self) -> SIG9_IN_SEL_R { + SIG9_IN_SEL_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC9_IN_SEL_CFG") + .field( + "func9_in_sel", + &format_args!("{}", self.func9_in_sel().bits()), + ) + .field( + "func9_in_inv_sel", + &format_args!("{}", self.func9_in_inv_sel().bit()), + ) + .field("sig9_in_sel", &format_args!("{}", self.sig9_in_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."] + #[inline(always)] + #[must_use] + pub fn func9_in_sel(&mut self) -> FUNC9_IN_SEL_W { + FUNC9_IN_SEL_W::new(self, 0) + } + #[doc = "Bit 6 - set this bit to invert input signal. 1:invert. 0:not invert."] + #[inline(always)] + #[must_use] + pub fn func9_in_inv_sel(&mut self) -> FUNC9_IN_INV_SEL_W { + FUNC9_IN_INV_SEL_W::new(self, 6) + } + #[doc = "Bit 7 - set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO."] + #[inline(always)] + #[must_use] + pub fn sig9_in_sel(&mut self) -> SIG9_IN_SEL_W { + SIG9_IN_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO input function configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func9_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func9_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC9_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC9_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func9_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC9_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func9_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC9_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC9_IN_SEL_CFG to value 0x3f"] +impl crate::Resettable for FUNC9_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/gpio/func_out_sel_cfg.rs b/esp32p4/src/gpio/func_out_sel_cfg.rs new file mode 100644 index 0000000000..92ff66521b --- /dev/null +++ b/esp32p4/src/gpio/func_out_sel_cfg.rs @@ -0,0 +1,123 @@ +#[doc = "Register `FUNC%s_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC%s_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FUNC_OUT_SEL` reader - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."] +pub type FUNC_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `FUNC_OUT_SEL` writer - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."] +pub type FUNC_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `FUNC_OUT_INV_SEL` reader - set this bit to invert output signal.1:invert.0:not invert."] +pub type FUNC_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC_OUT_INV_SEL` writer - set this bit to invert output signal.1:invert.0:not invert."] +pub type FUNC_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FUNC_OEN_SEL` reader - set this bit to select output enable signal.1:use GPIO_ENABLE_REG\\[n\\] as output enable signal.0:use peripheral output enable signal."] +pub type FUNC_OEN_SEL_R = crate::BitReader; +#[doc = "Field `FUNC_OEN_SEL` writer - set this bit to select output enable signal.1:use GPIO_ENABLE_REG\\[n\\] as output enable signal.0:use peripheral output enable signal."] +pub type FUNC_OEN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FUNC_OEN_INV_SEL` reader - set this bit to invert output enable signal.1:invert.0:not invert."] +pub type FUNC_OEN_INV_SEL_R = crate::BitReader; +#[doc = "Field `FUNC_OEN_INV_SEL` writer - set this bit to invert output enable signal.1:invert.0:not invert."] +pub type FUNC_OEN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:8 - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."] + #[inline(always)] + pub fn func_out_sel(&self) -> FUNC_OUT_SEL_R { + FUNC_OUT_SEL_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bit 9 - set this bit to invert output signal.1:invert.0:not invert."] + #[inline(always)] + pub fn func_out_inv_sel(&self) -> FUNC_OUT_INV_SEL_R { + FUNC_OUT_INV_SEL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - set this bit to select output enable signal.1:use GPIO_ENABLE_REG\\[n\\] as output enable signal.0:use peripheral output enable signal."] + #[inline(always)] + pub fn func_oen_sel(&self) -> FUNC_OEN_SEL_R { + FUNC_OEN_SEL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - set this bit to invert output enable signal.1:invert.0:not invert."] + #[inline(always)] + pub fn func_oen_inv_sel(&self) -> FUNC_OEN_INV_SEL_R { + FUNC_OEN_INV_SEL_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC_OUT_SEL_CFG") + .field( + "func_out_sel", + &format_args!("{}", self.func_out_sel().bits()), + ) + .field( + "func_out_inv_sel", + &format_args!("{}", self.func_out_inv_sel().bit()), + ) + .field( + "func_oen_sel", + &format_args!("{}", self.func_oen_sel().bit()), + ) + .field( + "func_oen_inv_sel", + &format_args!("{}", self.func_oen_inv_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."] + #[inline(always)] + #[must_use] + pub fn func_out_sel(&mut self) -> FUNC_OUT_SEL_W { + FUNC_OUT_SEL_W::new(self, 0) + } + #[doc = "Bit 9 - set this bit to invert output signal.1:invert.0:not invert."] + #[inline(always)] + #[must_use] + pub fn func_out_inv_sel(&mut self) -> FUNC_OUT_INV_SEL_W { + FUNC_OUT_INV_SEL_W::new(self, 9) + } + #[doc = "Bit 10 - set this bit to select output enable signal.1:use GPIO_ENABLE_REG\\[n\\] as output enable signal.0:use peripheral output enable signal."] + #[inline(always)] + #[must_use] + pub fn func_oen_sel(&mut self) -> FUNC_OEN_SEL_W { + FUNC_OEN_SEL_W::new(self, 10) + } + #[doc = "Bit 11 - set this bit to invert output enable signal.1:invert.0:not invert."] + #[inline(always)] + #[must_use] + pub fn func_oen_inv_sel(&mut self) -> FUNC_OEN_INV_SEL_W { + FUNC_OEN_INV_SEL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output function select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC%s_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/gpio/in1.rs b/esp32p4/src/gpio/in1.rs new file mode 100644 index 0000000000..72dacdf1a9 --- /dev/null +++ b/esp32p4/src/gpio/in1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `IN1` reader"] +pub type R = crate::R; +#[doc = "Field `DATA_NEXT` reader - GPIO input register for GPIO32-56"] +pub type DATA_NEXT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:24 - GPIO input register for GPIO32-56"] + #[inline(always)] + pub fn data_next(&self) -> DATA_NEXT_R { + DATA_NEXT_R::new(self.bits & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN1") + .field("data_next", &format_args!("{}", self.data_next().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO input register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN1_SPEC; +impl crate::RegisterSpec for IN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in1::R`](R) reader structure"] +impl crate::Readable for IN1_SPEC {} +#[doc = "`reset()` method sets IN1 to value 0"] +impl crate::Resettable for IN1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/in_.rs b/esp32p4/src/gpio/in_.rs new file mode 100644 index 0000000000..ae2dae600c --- /dev/null +++ b/esp32p4/src/gpio/in_.rs @@ -0,0 +1,36 @@ +#[doc = "Register `IN` reader"] +pub type R = crate::R; +#[doc = "Field `DATA_NEXT` reader - GPIO input register for GPIO0-31"] +pub type DATA_NEXT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - GPIO input register for GPIO0-31"] + #[inline(always)] + pub fn data_next(&self) -> DATA_NEXT_R { + DATA_NEXT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN") + .field("data_next", &format_args!("{}", self.data_next().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO input register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_::R`](R) reader structure"] +impl crate::Readable for IN_SPEC {} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/int_clr.rs b/esp32p4/src/gpio/int_clr.rs new file mode 100644 index 0000000000..5ba3bdd5bb --- /dev/null +++ b/esp32p4/src/gpio/int_clr.rs @@ -0,0 +1,98 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `COMP0_NEG_INT_CLR` writer - analog comparator pos edge interrupt clear"] +pub type COMP0_NEG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP0_POS_INT_CLR` writer - analog comparator neg edge interrupt clear"] +pub type COMP0_POS_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP0_ALL_INT_CLR` writer - analog comparator neg or pos edge interrupt clear"] +pub type COMP0_ALL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP1_NEG_INT_CLR` writer - analog comparator pos edge interrupt clear"] +pub type COMP1_NEG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP1_POS_INT_CLR` writer - analog comparator neg edge interrupt clear"] +pub type COMP1_POS_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP1_ALL_INT_CLR` writer - analog comparator neg or pos edge interrupt clear"] +pub type COMP1_ALL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BISTOK_INT_CLR` writer - pad bistok interrupt enable"] +pub type BISTOK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BISTFAIL_INT_CLR` writer - pad bistfail interrupt enable"] +pub type BISTFAIL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - analog comparator pos edge interrupt clear"] + #[inline(always)] + #[must_use] + pub fn comp0_neg_int_clr(&mut self) -> COMP0_NEG_INT_CLR_W { + COMP0_NEG_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - analog comparator neg edge interrupt clear"] + #[inline(always)] + #[must_use] + pub fn comp0_pos_int_clr(&mut self) -> COMP0_POS_INT_CLR_W { + COMP0_POS_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - analog comparator neg or pos edge interrupt clear"] + #[inline(always)] + #[must_use] + pub fn comp0_all_int_clr(&mut self) -> COMP0_ALL_INT_CLR_W { + COMP0_ALL_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - analog comparator pos edge interrupt clear"] + #[inline(always)] + #[must_use] + pub fn comp1_neg_int_clr(&mut self) -> COMP1_NEG_INT_CLR_W { + COMP1_NEG_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - analog comparator neg edge interrupt clear"] + #[inline(always)] + #[must_use] + pub fn comp1_pos_int_clr(&mut self) -> COMP1_POS_INT_CLR_W { + COMP1_POS_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - analog comparator neg or pos edge interrupt clear"] + #[inline(always)] + #[must_use] + pub fn comp1_all_int_clr(&mut self) -> COMP1_ALL_INT_CLR_W { + COMP1_ALL_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - pad bistok interrupt enable"] + #[inline(always)] + #[must_use] + pub fn bistok_int_clr(&mut self) -> BISTOK_INT_CLR_W { + BISTOK_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - pad bistfail interrupt enable"] + #[inline(always)] + #[must_use] + pub fn bistfail_int_clr(&mut self) -> BISTFAIL_INT_CLR_W { + BISTFAIL_INT_CLR_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "analog comparator interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/int_ena.rs b/esp32p4/src/gpio/int_ena.rs new file mode 100644 index 0000000000..cbfc354523 --- /dev/null +++ b/esp32p4/src/gpio/int_ena.rs @@ -0,0 +1,199 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `COMP0_NEG_INT_ENA` reader - analog comparator pos edge interrupt enable"] +pub type COMP0_NEG_INT_ENA_R = crate::BitReader; +#[doc = "Field `COMP0_NEG_INT_ENA` writer - analog comparator pos edge interrupt enable"] +pub type COMP0_NEG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP0_POS_INT_ENA` reader - analog comparator neg edge interrupt enable"] +pub type COMP0_POS_INT_ENA_R = crate::BitReader; +#[doc = "Field `COMP0_POS_INT_ENA` writer - analog comparator neg edge interrupt enable"] +pub type COMP0_POS_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP0_ALL_INT_ENA` reader - analog comparator neg or pos edge interrupt enable"] +pub type COMP0_ALL_INT_ENA_R = crate::BitReader; +#[doc = "Field `COMP0_ALL_INT_ENA` writer - analog comparator neg or pos edge interrupt enable"] +pub type COMP0_ALL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP1_NEG_INT_ENA` reader - analog comparator pos edge interrupt enable"] +pub type COMP1_NEG_INT_ENA_R = crate::BitReader; +#[doc = "Field `COMP1_NEG_INT_ENA` writer - analog comparator pos edge interrupt enable"] +pub type COMP1_NEG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP1_POS_INT_ENA` reader - analog comparator neg edge interrupt enable"] +pub type COMP1_POS_INT_ENA_R = crate::BitReader; +#[doc = "Field `COMP1_POS_INT_ENA` writer - analog comparator neg edge interrupt enable"] +pub type COMP1_POS_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP1_ALL_INT_ENA` reader - analog comparator neg or pos edge interrupt enable"] +pub type COMP1_ALL_INT_ENA_R = crate::BitReader; +#[doc = "Field `COMP1_ALL_INT_ENA` writer - analog comparator neg or pos edge interrupt enable"] +pub type COMP1_ALL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BISTOK_INT_ENA` reader - pad bistok interrupt enable"] +pub type BISTOK_INT_ENA_R = crate::BitReader; +#[doc = "Field `BISTOK_INT_ENA` writer - pad bistok interrupt enable"] +pub type BISTOK_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BISTFAIL_INT_ENA` reader - pad bistfail interrupt enable"] +pub type BISTFAIL_INT_ENA_R = crate::BitReader; +#[doc = "Field `BISTFAIL_INT_ENA` writer - pad bistfail interrupt enable"] +pub type BISTFAIL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - analog comparator pos edge interrupt enable"] + #[inline(always)] + pub fn comp0_neg_int_ena(&self) -> COMP0_NEG_INT_ENA_R { + COMP0_NEG_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - analog comparator neg edge interrupt enable"] + #[inline(always)] + pub fn comp0_pos_int_ena(&self) -> COMP0_POS_INT_ENA_R { + COMP0_POS_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - analog comparator neg or pos edge interrupt enable"] + #[inline(always)] + pub fn comp0_all_int_ena(&self) -> COMP0_ALL_INT_ENA_R { + COMP0_ALL_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - analog comparator pos edge interrupt enable"] + #[inline(always)] + pub fn comp1_neg_int_ena(&self) -> COMP1_NEG_INT_ENA_R { + COMP1_NEG_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - analog comparator neg edge interrupt enable"] + #[inline(always)] + pub fn comp1_pos_int_ena(&self) -> COMP1_POS_INT_ENA_R { + COMP1_POS_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - analog comparator neg or pos edge interrupt enable"] + #[inline(always)] + pub fn comp1_all_int_ena(&self) -> COMP1_ALL_INT_ENA_R { + COMP1_ALL_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - pad bistok interrupt enable"] + #[inline(always)] + pub fn bistok_int_ena(&self) -> BISTOK_INT_ENA_R { + BISTOK_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - pad bistfail interrupt enable"] + #[inline(always)] + pub fn bistfail_int_ena(&self) -> BISTFAIL_INT_ENA_R { + BISTFAIL_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "comp0_neg_int_ena", + &format_args!("{}", self.comp0_neg_int_ena().bit()), + ) + .field( + "comp0_pos_int_ena", + &format_args!("{}", self.comp0_pos_int_ena().bit()), + ) + .field( + "comp0_all_int_ena", + &format_args!("{}", self.comp0_all_int_ena().bit()), + ) + .field( + "comp1_neg_int_ena", + &format_args!("{}", self.comp1_neg_int_ena().bit()), + ) + .field( + "comp1_pos_int_ena", + &format_args!("{}", self.comp1_pos_int_ena().bit()), + ) + .field( + "comp1_all_int_ena", + &format_args!("{}", self.comp1_all_int_ena().bit()), + ) + .field( + "bistok_int_ena", + &format_args!("{}", self.bistok_int_ena().bit()), + ) + .field( + "bistfail_int_ena", + &format_args!("{}", self.bistfail_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - analog comparator pos edge interrupt enable"] + #[inline(always)] + #[must_use] + pub fn comp0_neg_int_ena(&mut self) -> COMP0_NEG_INT_ENA_W { + COMP0_NEG_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - analog comparator neg edge interrupt enable"] + #[inline(always)] + #[must_use] + pub fn comp0_pos_int_ena(&mut self) -> COMP0_POS_INT_ENA_W { + COMP0_POS_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - analog comparator neg or pos edge interrupt enable"] + #[inline(always)] + #[must_use] + pub fn comp0_all_int_ena(&mut self) -> COMP0_ALL_INT_ENA_W { + COMP0_ALL_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - analog comparator pos edge interrupt enable"] + #[inline(always)] + #[must_use] + pub fn comp1_neg_int_ena(&mut self) -> COMP1_NEG_INT_ENA_W { + COMP1_NEG_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - analog comparator neg edge interrupt enable"] + #[inline(always)] + #[must_use] + pub fn comp1_pos_int_ena(&mut self) -> COMP1_POS_INT_ENA_W { + COMP1_POS_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - analog comparator neg or pos edge interrupt enable"] + #[inline(always)] + #[must_use] + pub fn comp1_all_int_ena(&mut self) -> COMP1_ALL_INT_ENA_W { + COMP1_ALL_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - pad bistok interrupt enable"] + #[inline(always)] + #[must_use] + pub fn bistok_int_ena(&mut self) -> BISTOK_INT_ENA_W { + BISTOK_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - pad bistfail interrupt enable"] + #[inline(always)] + #[must_use] + pub fn bistfail_int_ena(&mut self) -> BISTFAIL_INT_ENA_W { + BISTFAIL_INT_ENA_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "analog comparator interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0xff"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0xff; +} diff --git a/esp32p4/src/gpio/int_raw.rs b/esp32p4/src/gpio/int_raw.rs new file mode 100644 index 0000000000..6340722f7d --- /dev/null +++ b/esp32p4/src/gpio/int_raw.rs @@ -0,0 +1,199 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `COMP0_NEG_INT_RAW` reader - analog comparator pos edge interrupt raw"] +pub type COMP0_NEG_INT_RAW_R = crate::BitReader; +#[doc = "Field `COMP0_NEG_INT_RAW` writer - analog comparator pos edge interrupt raw"] +pub type COMP0_NEG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP0_POS_INT_RAW` reader - analog comparator neg edge interrupt raw"] +pub type COMP0_POS_INT_RAW_R = crate::BitReader; +#[doc = "Field `COMP0_POS_INT_RAW` writer - analog comparator neg edge interrupt raw"] +pub type COMP0_POS_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP0_ALL_INT_RAW` reader - analog comparator neg or pos edge interrupt raw"] +pub type COMP0_ALL_INT_RAW_R = crate::BitReader; +#[doc = "Field `COMP0_ALL_INT_RAW` writer - analog comparator neg or pos edge interrupt raw"] +pub type COMP0_ALL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP1_NEG_INT_RAW` reader - analog comparator pos edge interrupt raw"] +pub type COMP1_NEG_INT_RAW_R = crate::BitReader; +#[doc = "Field `COMP1_NEG_INT_RAW` writer - analog comparator pos edge interrupt raw"] +pub type COMP1_NEG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP1_POS_INT_RAW` reader - analog comparator neg edge interrupt raw"] +pub type COMP1_POS_INT_RAW_R = crate::BitReader; +#[doc = "Field `COMP1_POS_INT_RAW` writer - analog comparator neg edge interrupt raw"] +pub type COMP1_POS_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMP1_ALL_INT_RAW` reader - analog comparator neg or pos edge interrupt raw"] +pub type COMP1_ALL_INT_RAW_R = crate::BitReader; +#[doc = "Field `COMP1_ALL_INT_RAW` writer - analog comparator neg or pos edge interrupt raw"] +pub type COMP1_ALL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BISTOK_INT_RAW` reader - pad bistok interrupt raw"] +pub type BISTOK_INT_RAW_R = crate::BitReader; +#[doc = "Field `BISTOK_INT_RAW` writer - pad bistok interrupt raw"] +pub type BISTOK_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BISTFAIL_INT_RAW` reader - pad bistfail interrupt raw"] +pub type BISTFAIL_INT_RAW_R = crate::BitReader; +#[doc = "Field `BISTFAIL_INT_RAW` writer - pad bistfail interrupt raw"] +pub type BISTFAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - analog comparator pos edge interrupt raw"] + #[inline(always)] + pub fn comp0_neg_int_raw(&self) -> COMP0_NEG_INT_RAW_R { + COMP0_NEG_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - analog comparator neg edge interrupt raw"] + #[inline(always)] + pub fn comp0_pos_int_raw(&self) -> COMP0_POS_INT_RAW_R { + COMP0_POS_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - analog comparator neg or pos edge interrupt raw"] + #[inline(always)] + pub fn comp0_all_int_raw(&self) -> COMP0_ALL_INT_RAW_R { + COMP0_ALL_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - analog comparator pos edge interrupt raw"] + #[inline(always)] + pub fn comp1_neg_int_raw(&self) -> COMP1_NEG_INT_RAW_R { + COMP1_NEG_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - analog comparator neg edge interrupt raw"] + #[inline(always)] + pub fn comp1_pos_int_raw(&self) -> COMP1_POS_INT_RAW_R { + COMP1_POS_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - analog comparator neg or pos edge interrupt raw"] + #[inline(always)] + pub fn comp1_all_int_raw(&self) -> COMP1_ALL_INT_RAW_R { + COMP1_ALL_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - pad bistok interrupt raw"] + #[inline(always)] + pub fn bistok_int_raw(&self) -> BISTOK_INT_RAW_R { + BISTOK_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - pad bistfail interrupt raw"] + #[inline(always)] + pub fn bistfail_int_raw(&self) -> BISTFAIL_INT_RAW_R { + BISTFAIL_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "comp0_neg_int_raw", + &format_args!("{}", self.comp0_neg_int_raw().bit()), + ) + .field( + "comp0_pos_int_raw", + &format_args!("{}", self.comp0_pos_int_raw().bit()), + ) + .field( + "comp0_all_int_raw", + &format_args!("{}", self.comp0_all_int_raw().bit()), + ) + .field( + "comp1_neg_int_raw", + &format_args!("{}", self.comp1_neg_int_raw().bit()), + ) + .field( + "comp1_pos_int_raw", + &format_args!("{}", self.comp1_pos_int_raw().bit()), + ) + .field( + "comp1_all_int_raw", + &format_args!("{}", self.comp1_all_int_raw().bit()), + ) + .field( + "bistok_int_raw", + &format_args!("{}", self.bistok_int_raw().bit()), + ) + .field( + "bistfail_int_raw", + &format_args!("{}", self.bistfail_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - analog comparator pos edge interrupt raw"] + #[inline(always)] + #[must_use] + pub fn comp0_neg_int_raw(&mut self) -> COMP0_NEG_INT_RAW_W { + COMP0_NEG_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - analog comparator neg edge interrupt raw"] + #[inline(always)] + #[must_use] + pub fn comp0_pos_int_raw(&mut self) -> COMP0_POS_INT_RAW_W { + COMP0_POS_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - analog comparator neg or pos edge interrupt raw"] + #[inline(always)] + #[must_use] + pub fn comp0_all_int_raw(&mut self) -> COMP0_ALL_INT_RAW_W { + COMP0_ALL_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - analog comparator pos edge interrupt raw"] + #[inline(always)] + #[must_use] + pub fn comp1_neg_int_raw(&mut self) -> COMP1_NEG_INT_RAW_W { + COMP1_NEG_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - analog comparator neg edge interrupt raw"] + #[inline(always)] + #[must_use] + pub fn comp1_pos_int_raw(&mut self) -> COMP1_POS_INT_RAW_W { + COMP1_POS_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - analog comparator neg or pos edge interrupt raw"] + #[inline(always)] + #[must_use] + pub fn comp1_all_int_raw(&mut self) -> COMP1_ALL_INT_RAW_W { + COMP1_ALL_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - pad bistok interrupt raw"] + #[inline(always)] + #[must_use] + pub fn bistok_int_raw(&mut self) -> BISTOK_INT_RAW_W { + BISTOK_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - pad bistfail interrupt raw"] + #[inline(always)] + #[must_use] + pub fn bistfail_int_raw(&mut self) -> BISTFAIL_INT_RAW_W { + BISTFAIL_INT_RAW_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "analog comparator interrupt raw\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/int_st.rs b/esp32p4/src/gpio/int_st.rs new file mode 100644 index 0000000000..3f54e4f521 --- /dev/null +++ b/esp32p4/src/gpio/int_st.rs @@ -0,0 +1,116 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `COMP0_NEG_INT_ST` reader - analog comparator pos edge interrupt status"] +pub type COMP0_NEG_INT_ST_R = crate::BitReader; +#[doc = "Field `COMP0_POS_INT_ST` reader - analog comparator neg edge interrupt status"] +pub type COMP0_POS_INT_ST_R = crate::BitReader; +#[doc = "Field `COMP0_ALL_INT_ST` reader - analog comparator neg or pos edge interrupt status"] +pub type COMP0_ALL_INT_ST_R = crate::BitReader; +#[doc = "Field `COMP1_NEG_INT_ST` reader - analog comparator pos edge interrupt status"] +pub type COMP1_NEG_INT_ST_R = crate::BitReader; +#[doc = "Field `COMP1_POS_INT_ST` reader - analog comparator neg edge interrupt status"] +pub type COMP1_POS_INT_ST_R = crate::BitReader; +#[doc = "Field `COMP1_ALL_INT_ST` reader - analog comparator neg or pos edge interrupt status"] +pub type COMP1_ALL_INT_ST_R = crate::BitReader; +#[doc = "Field `BISTOK_INT_ST` reader - pad bistok interrupt status"] +pub type BISTOK_INT_ST_R = crate::BitReader; +#[doc = "Field `BISTFAIL_INT_ST` reader - pad bistfail interrupt status"] +pub type BISTFAIL_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - analog comparator pos edge interrupt status"] + #[inline(always)] + pub fn comp0_neg_int_st(&self) -> COMP0_NEG_INT_ST_R { + COMP0_NEG_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - analog comparator neg edge interrupt status"] + #[inline(always)] + pub fn comp0_pos_int_st(&self) -> COMP0_POS_INT_ST_R { + COMP0_POS_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - analog comparator neg or pos edge interrupt status"] + #[inline(always)] + pub fn comp0_all_int_st(&self) -> COMP0_ALL_INT_ST_R { + COMP0_ALL_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - analog comparator pos edge interrupt status"] + #[inline(always)] + pub fn comp1_neg_int_st(&self) -> COMP1_NEG_INT_ST_R { + COMP1_NEG_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - analog comparator neg edge interrupt status"] + #[inline(always)] + pub fn comp1_pos_int_st(&self) -> COMP1_POS_INT_ST_R { + COMP1_POS_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - analog comparator neg or pos edge interrupt status"] + #[inline(always)] + pub fn comp1_all_int_st(&self) -> COMP1_ALL_INT_ST_R { + COMP1_ALL_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - pad bistok interrupt status"] + #[inline(always)] + pub fn bistok_int_st(&self) -> BISTOK_INT_ST_R { + BISTOK_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - pad bistfail interrupt status"] + #[inline(always)] + pub fn bistfail_int_st(&self) -> BISTFAIL_INT_ST_R { + BISTFAIL_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "comp0_neg_int_st", + &format_args!("{}", self.comp0_neg_int_st().bit()), + ) + .field( + "comp0_pos_int_st", + &format_args!("{}", self.comp0_pos_int_st().bit()), + ) + .field( + "comp0_all_int_st", + &format_args!("{}", self.comp0_all_int_st().bit()), + ) + .field( + "comp1_neg_int_st", + &format_args!("{}", self.comp1_neg_int_st().bit()), + ) + .field( + "comp1_pos_int_st", + &format_args!("{}", self.comp1_pos_int_st().bit()), + ) + .field( + "comp1_all_int_st", + &format_args!("{}", self.comp1_all_int_st().bit()), + ) + .field( + "bistok_int_st", + &format_args!("{}", self.bistok_int_st().bit()), + ) + .field( + "bistfail_int_st", + &format_args!("{}", self.bistfail_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "analog comparator interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/intr1_0.rs b/esp32p4/src/gpio/intr1_0.rs new file mode 100644 index 0000000000..33ec71d872 --- /dev/null +++ b/esp32p4/src/gpio/intr1_0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `INTR1_0` reader"] +pub type R = crate::R; +#[doc = "Field `INT1_0` reader - GPIO interrupt 0 status register for GPIO32-56"] +pub type INT1_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:24 - GPIO interrupt 0 status register for GPIO32-56"] + #[inline(always)] + pub fn int1_0(&self) -> INT1_0_R { + INT1_0_R::new(self.bits & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR1_0") + .field("int1_0", &format_args!("{}", self.int1_0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO interrupt 0 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR1_0_SPEC; +impl crate::RegisterSpec for INTR1_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr1_0::R`](R) reader structure"] +impl crate::Readable for INTR1_0_SPEC {} +#[doc = "`reset()` method sets INTR1_0 to value 0"] +impl crate::Resettable for INTR1_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/intr1_1.rs b/esp32p4/src/gpio/intr1_1.rs new file mode 100644 index 0000000000..f1b34d2cd8 --- /dev/null +++ b/esp32p4/src/gpio/intr1_1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `INTR1_1` reader"] +pub type R = crate::R; +#[doc = "Field `INT1_1` reader - GPIO interrupt 1 status register for GPIO32-56"] +pub type INT1_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:24 - GPIO interrupt 1 status register for GPIO32-56"] + #[inline(always)] + pub fn int1_1(&self) -> INT1_1_R { + INT1_1_R::new(self.bits & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR1_1") + .field("int1_1", &format_args!("{}", self.int1_1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO interrupt 1 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR1_1_SPEC; +impl crate::RegisterSpec for INTR1_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr1_1::R`](R) reader structure"] +impl crate::Readable for INTR1_1_SPEC {} +#[doc = "`reset()` method sets INTR1_1 to value 0"] +impl crate::Resettable for INTR1_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/intr1_2.rs b/esp32p4/src/gpio/intr1_2.rs new file mode 100644 index 0000000000..dc8ba811cb --- /dev/null +++ b/esp32p4/src/gpio/intr1_2.rs @@ -0,0 +1,36 @@ +#[doc = "Register `INTR1_2` reader"] +pub type R = crate::R; +#[doc = "Field `INT1_2` reader - GPIO interrupt 2 status register for GPIO32-56"] +pub type INT1_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:24 - GPIO interrupt 2 status register for GPIO32-56"] + #[inline(always)] + pub fn int1_2(&self) -> INT1_2_R { + INT1_2_R::new(self.bits & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR1_2") + .field("int1_2", &format_args!("{}", self.int1_2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO interrupt 2 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR1_2_SPEC; +impl crate::RegisterSpec for INTR1_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr1_2::R`](R) reader structure"] +impl crate::Readable for INTR1_2_SPEC {} +#[doc = "`reset()` method sets INTR1_2 to value 0"] +impl crate::Resettable for INTR1_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/intr1_3.rs b/esp32p4/src/gpio/intr1_3.rs new file mode 100644 index 0000000000..0d87e6a2cb --- /dev/null +++ b/esp32p4/src/gpio/intr1_3.rs @@ -0,0 +1,36 @@ +#[doc = "Register `INTR1_3` reader"] +pub type R = crate::R; +#[doc = "Field `INT1_3` reader - GPIO interrupt 3 status register for GPIO32-56"] +pub type INT1_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:24 - GPIO interrupt 3 status register for GPIO32-56"] + #[inline(always)] + pub fn int1_3(&self) -> INT1_3_R { + INT1_3_R::new(self.bits & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR1_3") + .field("int1_3", &format_args!("{}", self.int1_3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO interrupt 3 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR1_3_SPEC; +impl crate::RegisterSpec for INTR1_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr1_3::R`](R) reader structure"] +impl crate::Readable for INTR1_3_SPEC {} +#[doc = "`reset()` method sets INTR1_3 to value 0"] +impl crate::Resettable for INTR1_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/intr_0.rs b/esp32p4/src/gpio/intr_0.rs new file mode 100644 index 0000000000..0d533c53c9 --- /dev/null +++ b/esp32p4/src/gpio/intr_0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `INTR_0` reader"] +pub type R = crate::R; +#[doc = "Field `INT_0` reader - GPIO interrupt 0 status register for GPIO0-31"] +pub type INT_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - GPIO interrupt 0 status register for GPIO0-31"] + #[inline(always)] + pub fn int_0(&self) -> INT_0_R { + INT_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_0") + .field("int_0", &format_args!("{}", self.int_0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO interrupt 0 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_0_SPEC; +impl crate::RegisterSpec for INTR_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_0::R`](R) reader structure"] +impl crate::Readable for INTR_0_SPEC {} +#[doc = "`reset()` method sets INTR_0 to value 0"] +impl crate::Resettable for INTR_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/intr_1.rs b/esp32p4/src/gpio/intr_1.rs new file mode 100644 index 0000000000..c770334382 --- /dev/null +++ b/esp32p4/src/gpio/intr_1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `INTR_1` reader"] +pub type R = crate::R; +#[doc = "Field `INT_1` reader - GPIO interrupt 1 status register for GPIO0-31"] +pub type INT_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - GPIO interrupt 1 status register for GPIO0-31"] + #[inline(always)] + pub fn int_1(&self) -> INT_1_R { + INT_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_1") + .field("int_1", &format_args!("{}", self.int_1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO interrupt 1 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_1_SPEC; +impl crate::RegisterSpec for INTR_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_1::R`](R) reader structure"] +impl crate::Readable for INTR_1_SPEC {} +#[doc = "`reset()` method sets INTR_1 to value 0"] +impl crate::Resettable for INTR_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/intr_2.rs b/esp32p4/src/gpio/intr_2.rs new file mode 100644 index 0000000000..c2f80be0e2 --- /dev/null +++ b/esp32p4/src/gpio/intr_2.rs @@ -0,0 +1,36 @@ +#[doc = "Register `INTR_2` reader"] +pub type R = crate::R; +#[doc = "Field `INT_2` reader - GPIO interrupt 2 status register for GPIO0-31"] +pub type INT_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - GPIO interrupt 2 status register for GPIO0-31"] + #[inline(always)] + pub fn int_2(&self) -> INT_2_R { + INT_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_2") + .field("int_2", &format_args!("{}", self.int_2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO interrupt 2 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_2_SPEC; +impl crate::RegisterSpec for INTR_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_2::R`](R) reader structure"] +impl crate::Readable for INTR_2_SPEC {} +#[doc = "`reset()` method sets INTR_2 to value 0"] +impl crate::Resettable for INTR_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/intr_3.rs b/esp32p4/src/gpio/intr_3.rs new file mode 100644 index 0000000000..d6a76abe3c --- /dev/null +++ b/esp32p4/src/gpio/intr_3.rs @@ -0,0 +1,36 @@ +#[doc = "Register `INTR_3` reader"] +pub type R = crate::R; +#[doc = "Field `INT_3` reader - GPIO interrupt 3 status register for GPIO0-31"] +pub type INT_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - GPIO interrupt 3 status register for GPIO0-31"] + #[inline(always)] + pub fn int_3(&self) -> INT_3_R { + INT_3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_3") + .field("int_3", &format_args!("{}", self.int_3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO interrupt 3 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_3_SPEC; +impl crate::RegisterSpec for INTR_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_3::R`](R) reader structure"] +impl crate::Readable for INTR_3_SPEC {} +#[doc = "`reset()` method sets INTR_3 to value 0"] +impl crate::Resettable for INTR_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/out.rs b/esp32p4/src/gpio/out.rs new file mode 100644 index 0000000000..174d154db5 --- /dev/null +++ b/esp32p4/src/gpio/out.rs @@ -0,0 +1,63 @@ +#[doc = "Register `OUT` reader"] +pub type R = crate::R; +#[doc = "Register `OUT` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_ORIG` reader - GPIO output register for GPIO0-31"] +pub type DATA_ORIG_R = crate::FieldReader; +#[doc = "Field `DATA_ORIG` writer - GPIO output register for GPIO0-31"] +pub type DATA_ORIG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - GPIO output register for GPIO0-31"] + #[inline(always)] + pub fn data_orig(&self) -> DATA_ORIG_R { + DATA_ORIG_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT") + .field("data_orig", &format_args!("{}", self.data_orig().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - GPIO output register for GPIO0-31"] + #[inline(always)] + #[must_use] + pub fn data_orig(&mut self) -> DATA_ORIG_W { + DATA_ORIG_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out::R`](R) reader structure"] +impl crate::Readable for OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out::W`](W) writer structure"] +impl crate::Writable for OUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/out1.rs b/esp32p4/src/gpio/out1.rs new file mode 100644 index 0000000000..f05888068a --- /dev/null +++ b/esp32p4/src/gpio/out1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `OUT1` reader"] +pub type R = crate::R; +#[doc = "Register `OUT1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_ORIG` reader - GPIO output register for GPIO32-56"] +pub type DATA_ORIG_R = crate::FieldReader; +#[doc = "Field `DATA_ORIG` writer - GPIO output register for GPIO32-56"] +pub type DATA_ORIG_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +impl R { + #[doc = "Bits 0:24 - GPIO output register for GPIO32-56"] + #[inline(always)] + pub fn data_orig(&self) -> DATA_ORIG_R { + DATA_ORIG_R::new(self.bits & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT1") + .field("data_orig", &format_args!("{}", self.data_orig().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:24 - GPIO output register for GPIO32-56"] + #[inline(always)] + #[must_use] + pub fn data_orig(&mut self) -> DATA_ORIG_W { + DATA_ORIG_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT1_SPEC; +impl crate::RegisterSpec for OUT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out1::R`](R) reader structure"] +impl crate::Readable for OUT1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out1::W`](W) writer structure"] +impl crate::Writable for OUT1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT1 to value 0"] +impl crate::Resettable for OUT1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/out1_w1tc.rs b/esp32p4/src/gpio/out1_w1tc.rs new file mode 100644 index 0000000000..0e539c851d --- /dev/null +++ b/esp32p4/src/gpio/out1_w1tc.rs @@ -0,0 +1,42 @@ +#[doc = "Register `OUT1_W1TC` writer"] +pub type W = crate::W; +#[doc = "Field `OUT1_W1TC` writer - GPIO output clear register for GPIO32-56"] +pub type OUT1_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:24 - GPIO output clear register for GPIO32-56"] + #[inline(always)] + #[must_use] + pub fn out1_w1tc(&mut self) -> OUT1_W1TC_W { + OUT1_W1TC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output clear register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out1_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT1_W1TC_SPEC; +impl crate::RegisterSpec for OUT1_W1TC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out1_w1tc::W`](W) writer structure"] +impl crate::Writable for OUT1_W1TC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT1_W1TC to value 0"] +impl crate::Resettable for OUT1_W1TC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/out1_w1ts.rs b/esp32p4/src/gpio/out1_w1ts.rs new file mode 100644 index 0000000000..d14354321b --- /dev/null +++ b/esp32p4/src/gpio/out1_w1ts.rs @@ -0,0 +1,42 @@ +#[doc = "Register `OUT1_W1TS` writer"] +pub type W = crate::W; +#[doc = "Field `OUT1_W1TS` writer - GPIO output set register for GPIO32-56"] +pub type OUT1_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:24 - GPIO output set register for GPIO32-56"] + #[inline(always)] + #[must_use] + pub fn out1_w1ts(&mut self) -> OUT1_W1TS_W { + OUT1_W1TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output set register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out1_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT1_W1TS_SPEC; +impl crate::RegisterSpec for OUT1_W1TS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out1_w1ts::W`](W) writer structure"] +impl crate::Writable for OUT1_W1TS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT1_W1TS to value 0"] +impl crate::Resettable for OUT1_W1TS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/out_w1tc.rs b/esp32p4/src/gpio/out_w1tc.rs new file mode 100644 index 0000000000..4363320eaa --- /dev/null +++ b/esp32p4/src/gpio/out_w1tc.rs @@ -0,0 +1,42 @@ +#[doc = "Register `OUT_W1TC` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_W1TC` writer - GPIO output clear register for GPIO0-31"] +pub type OUT_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - GPIO output clear register for GPIO0-31"] + #[inline(always)] + #[must_use] + pub fn out_w1tc(&mut self) -> OUT_W1TC_W { + OUT_W1TC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output clear register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_W1TC_SPEC; +impl crate::RegisterSpec for OUT_W1TC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out_w1tc::W`](W) writer structure"] +impl crate::Writable for OUT_W1TC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_W1TC to value 0"] +impl crate::Resettable for OUT_W1TC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/out_w1ts.rs b/esp32p4/src/gpio/out_w1ts.rs new file mode 100644 index 0000000000..73b2938e74 --- /dev/null +++ b/esp32p4/src/gpio/out_w1ts.rs @@ -0,0 +1,42 @@ +#[doc = "Register `OUT_W1TS` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_W1TS` writer - GPIO output set register for GPIO0-31"] +pub type OUT_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - GPIO output set register for GPIO0-31"] + #[inline(always)] + #[must_use] + pub fn out_w1ts(&mut self) -> OUT_W1TS_W { + OUT_W1TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO output set register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_W1TS_SPEC; +impl crate::RegisterSpec for OUT_W1TS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out_w1ts::W`](W) writer structure"] +impl crate::Writable for OUT_W1TS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_W1TS to value 0"] +impl crate::Resettable for OUT_W1TS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/pin.rs b/esp32p4/src/gpio/pin.rs new file mode 100644 index 0000000000..56c046021d --- /dev/null +++ b/esp32p4/src/gpio/pin.rs @@ -0,0 +1,168 @@ +#[doc = "Register `PIN%s` reader"] +pub type R = crate::R; +#[doc = "Register `PIN%s` writer"] +pub type W = crate::W; +#[doc = "Field `SYNC2_BYPASS` reader - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."] +pub type SYNC2_BYPASS_R = crate::FieldReader; +#[doc = "Field `SYNC2_BYPASS` writer - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."] +pub type SYNC2_BYPASS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PAD_DRIVER` reader - set this bit to select pad driver. 1:open-drain. 0:normal."] +pub type PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `PAD_DRIVER` writer - set this bit to select pad driver. 1:open-drain. 0:normal."] +pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYNC1_BYPASS` reader - set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."] +pub type SYNC1_BYPASS_R = crate::FieldReader; +#[doc = "Field `SYNC1_BYPASS` writer - set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."] +pub type SYNC1_BYPASS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `INT_TYPE` reader - set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level"] +pub type INT_TYPE_R = crate::FieldReader; +#[doc = "Field `INT_TYPE` writer - set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level"] +pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WAKEUP_ENABLE` reader - set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)"] +pub type WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `WAKEUP_ENABLE` writer - set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)"] +pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CONFIG` reader - reserved"] +pub type CONFIG_R = crate::FieldReader; +#[doc = "Field `CONFIG` writer - reserved"] +pub type CONFIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `INT_ENA` reader - set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt."] +pub type INT_ENA_R = crate::FieldReader; +#[doc = "Field `INT_ENA` writer - set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt."] +pub type INT_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:1 - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."] + #[inline(always)] + pub fn sync2_bypass(&self) -> SYNC2_BYPASS_R { + SYNC2_BYPASS_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - set this bit to select pad driver. 1:open-drain. 0:normal."] + #[inline(always)] + pub fn pad_driver(&self) -> PAD_DRIVER_R { + PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."] + #[inline(always)] + pub fn sync1_bypass(&self) -> SYNC1_BYPASS_R { + SYNC1_BYPASS_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bits 7:9 - set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level"] + #[inline(always)] + pub fn int_type(&self) -> INT_TYPE_R { + INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) + } + #[doc = "Bit 10 - set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)"] + #[inline(always)] + pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { + WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 11:12 - reserved"] + #[inline(always)] + pub fn config(&self) -> CONFIG_R { + CONFIG_R::new(((self.bits >> 11) & 3) as u8) + } + #[doc = "Bits 13:17 - set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt."] + #[inline(always)] + pub fn int_ena(&self) -> INT_ENA_R { + INT_ENA_R::new(((self.bits >> 13) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN") + .field( + "sync2_bypass", + &format_args!("{}", self.sync2_bypass().bits()), + ) + .field("pad_driver", &format_args!("{}", self.pad_driver().bit())) + .field( + "sync1_bypass", + &format_args!("{}", self.sync1_bypass().bits()), + ) + .field("int_type", &format_args!("{}", self.int_type().bits())) + .field( + "wakeup_enable", + &format_args!("{}", self.wakeup_enable().bit()), + ) + .field("config", &format_args!("{}", self.config().bits())) + .field("int_ena", &format_args!("{}", self.int_ena().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."] + #[inline(always)] + #[must_use] + pub fn sync2_bypass(&mut self) -> SYNC2_BYPASS_W { + SYNC2_BYPASS_W::new(self, 0) + } + #[doc = "Bit 2 - set this bit to select pad driver. 1:open-drain. 0:normal."] + #[inline(always)] + #[must_use] + pub fn pad_driver(&mut self) -> PAD_DRIVER_W { + PAD_DRIVER_W::new(self, 2) + } + #[doc = "Bits 3:4 - set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."] + #[inline(always)] + #[must_use] + pub fn sync1_bypass(&mut self) -> SYNC1_BYPASS_W { + SYNC1_BYPASS_W::new(self, 3) + } + #[doc = "Bits 7:9 - set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level"] + #[inline(always)] + #[must_use] + pub fn int_type(&mut self) -> INT_TYPE_W { + INT_TYPE_W::new(self, 7) + } + #[doc = "Bit 10 - set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)"] + #[inline(always)] + #[must_use] + pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W { + WAKEUP_ENABLE_W::new(self, 10) + } + #[doc = "Bits 11:12 - reserved"] + #[inline(always)] + #[must_use] + pub fn config(&mut self) -> CONFIG_W { + CONFIG_W::new(self, 11) + } + #[doc = "Bits 13:17 - set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt."] + #[inline(always)] + #[must_use] + pub fn int_ena(&mut self) -> INT_ENA_W { + INT_ENA_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO pin configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN_SPEC; +impl crate::RegisterSpec for PIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin::R`](R) reader structure"] +impl crate::Readable for PIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin::W`](W) writer structure"] +impl crate::Writable for PIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN%s to value 0"] +impl crate::Resettable for PIN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/recive_seq.rs b/esp32p4/src/gpio/recive_seq.rs new file mode 100644 index 0000000000..9b1f43ac7d --- /dev/null +++ b/esp32p4/src/gpio/recive_seq.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RECIVE_SEQ` reader"] +pub type R = crate::R; +#[doc = "Field `RECIVE_SEQ` reader - High speed sdio pad bist recive sequence"] +pub type RECIVE_SEQ_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - High speed sdio pad bist recive sequence"] + #[inline(always)] + pub fn recive_seq(&self) -> RECIVE_SEQ_R { + RECIVE_SEQ_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RECIVE_SEQ") + .field("recive_seq", &format_args!("{}", self.recive_seq().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "High speed sdio pad bist recive sequence\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`recive_seq::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RECIVE_SEQ_SPEC; +impl crate::RegisterSpec for RECIVE_SEQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`recive_seq::R`](R) reader structure"] +impl crate::Readable for RECIVE_SEQ_SPEC {} +#[doc = "`reset()` method sets RECIVE_SEQ to value 0"] +impl crate::Resettable for RECIVE_SEQ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/send_seq.rs b/esp32p4/src/gpio/send_seq.rs new file mode 100644 index 0000000000..790408707d --- /dev/null +++ b/esp32p4/src/gpio/send_seq.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SEND_SEQ` reader"] +pub type R = crate::R; +#[doc = "Register `SEND_SEQ` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_SEQ` reader - High speed sdio pad bist send sequence"] +pub type SEND_SEQ_R = crate::FieldReader; +#[doc = "Field `SEND_SEQ` writer - High speed sdio pad bist send sequence"] +pub type SEND_SEQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - High speed sdio pad bist send sequence"] + #[inline(always)] + pub fn send_seq(&self) -> SEND_SEQ_R { + SEND_SEQ_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SEND_SEQ") + .field("send_seq", &format_args!("{}", self.send_seq().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - High speed sdio pad bist send sequence"] + #[inline(always)] + #[must_use] + pub fn send_seq(&mut self) -> SEND_SEQ_W { + SEND_SEQ_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "High speed sdio pad bist send sequence\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`send_seq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`send_seq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SEND_SEQ_SPEC; +impl crate::RegisterSpec for SEND_SEQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`send_seq::R`](R) reader structure"] +impl crate::Readable for SEND_SEQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`send_seq::W`](W) writer structure"] +impl crate::Writable for SEND_SEQ_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SEND_SEQ to value 0x1234_5678"] +impl crate::Resettable for SEND_SEQ_SPEC { + const RESET_VALUE: Self::Ux = 0x1234_5678; +} diff --git a/esp32p4/src/gpio/status.rs b/esp32p4/src/gpio/status.rs new file mode 100644 index 0000000000..b9377111d3 --- /dev/null +++ b/esp32p4/src/gpio/status.rs @@ -0,0 +1,63 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `INTERRUPT` reader - GPIO interrupt status register for GPIO0-31"] +pub type INTERRUPT_R = crate::FieldReader; +#[doc = "Field `INTERRUPT` writer - GPIO interrupt status register for GPIO0-31"] +pub type INTERRUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - GPIO interrupt status register for GPIO0-31"] + #[inline(always)] + pub fn interrupt(&self) -> INTERRUPT_R { + INTERRUPT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field("interrupt", &format_args!("{}", self.interrupt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - GPIO interrupt status register for GPIO0-31"] + #[inline(always)] + #[must_use] + pub fn interrupt(&mut self) -> INTERRUPT_W { + INTERRUPT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO interrupt status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/status1.rs b/esp32p4/src/gpio/status1.rs new file mode 100644 index 0000000000..da9232a314 --- /dev/null +++ b/esp32p4/src/gpio/status1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `STATUS1` reader"] +pub type R = crate::R; +#[doc = "Register `STATUS1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERRUPT` reader - GPIO interrupt status register for GPIO32-56"] +pub type INTERRUPT_R = crate::FieldReader; +#[doc = "Field `INTERRUPT` writer - GPIO interrupt status register for GPIO32-56"] +pub type INTERRUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +impl R { + #[doc = "Bits 0:24 - GPIO interrupt status register for GPIO32-56"] + #[inline(always)] + pub fn interrupt(&self) -> INTERRUPT_R { + INTERRUPT_R::new(self.bits & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS1") + .field("interrupt", &format_args!("{}", self.interrupt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:24 - GPIO interrupt status register for GPIO32-56"] + #[inline(always)] + #[must_use] + pub fn interrupt(&mut self) -> INTERRUPT_W { + INTERRUPT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO interrupt status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS1_SPEC; +impl crate::RegisterSpec for STATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status1::R`](R) reader structure"] +impl crate::Readable for STATUS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status1::W`](W) writer structure"] +impl crate::Writable for STATUS1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS1 to value 0"] +impl crate::Resettable for STATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/status1_w1tc.rs b/esp32p4/src/gpio/status1_w1tc.rs new file mode 100644 index 0000000000..32d2b860f0 --- /dev/null +++ b/esp32p4/src/gpio/status1_w1tc.rs @@ -0,0 +1,42 @@ +#[doc = "Register `STATUS1_W1TC` writer"] +pub type W = crate::W; +#[doc = "Field `STATUS1_W1TC` writer - GPIO interrupt status clear register for GPIO32-56"] +pub type STATUS1_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:24 - GPIO interrupt status clear register for GPIO32-56"] + #[inline(always)] + #[must_use] + pub fn status1_w1tc(&mut self) -> STATUS1_W1TC_W { + STATUS1_W1TC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO interrupt status clear register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS1_W1TC_SPEC; +impl crate::RegisterSpec for STATUS1_W1TC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`status1_w1tc::W`](W) writer structure"] +impl crate::Writable for STATUS1_W1TC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS1_W1TC to value 0"] +impl crate::Resettable for STATUS1_W1TC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/status1_w1ts.rs b/esp32p4/src/gpio/status1_w1ts.rs new file mode 100644 index 0000000000..ef50f16208 --- /dev/null +++ b/esp32p4/src/gpio/status1_w1ts.rs @@ -0,0 +1,42 @@ +#[doc = "Register `STATUS1_W1TS` writer"] +pub type W = crate::W; +#[doc = "Field `STATUS1_W1TS` writer - GPIO interrupt status set register for GPIO32-56"] +pub type STATUS1_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:24 - GPIO interrupt status set register for GPIO32-56"] + #[inline(always)] + #[must_use] + pub fn status1_w1ts(&mut self) -> STATUS1_W1TS_W { + STATUS1_W1TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO interrupt status set register for GPIO32-56\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status1_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS1_W1TS_SPEC; +impl crate::RegisterSpec for STATUS1_W1TS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`status1_w1ts::W`](W) writer structure"] +impl crate::Writable for STATUS1_W1TS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS1_W1TS to value 0"] +impl crate::Resettable for STATUS1_W1TS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/status_next.rs b/esp32p4/src/gpio/status_next.rs new file mode 100644 index 0000000000..9c9c5ac993 --- /dev/null +++ b/esp32p4/src/gpio/status_next.rs @@ -0,0 +1,39 @@ +#[doc = "Register `STATUS_NEXT` reader"] +pub type R = crate::R; +#[doc = "Field `STATUS_INTERRUPT_NEXT` reader - GPIO interrupt source register for GPIO0-31"] +pub type STATUS_INTERRUPT_NEXT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - GPIO interrupt source register for GPIO0-31"] + #[inline(always)] + pub fn status_interrupt_next(&self) -> STATUS_INTERRUPT_NEXT_R { + STATUS_INTERRUPT_NEXT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_NEXT") + .field( + "status_interrupt_next", + &format_args!("{}", self.status_interrupt_next().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO interrupt source register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_NEXT_SPEC; +impl crate::RegisterSpec for STATUS_NEXT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_next::R`](R) reader structure"] +impl crate::Readable for STATUS_NEXT_SPEC {} +#[doc = "`reset()` method sets STATUS_NEXT to value 0"] +impl crate::Resettable for STATUS_NEXT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/status_next1.rs b/esp32p4/src/gpio/status_next1.rs new file mode 100644 index 0000000000..ff575a5292 --- /dev/null +++ b/esp32p4/src/gpio/status_next1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `STATUS_NEXT1` reader"] +pub type R = crate::R; +#[doc = "Field `STATUS_INTERRUPT_NEXT1` reader - GPIO interrupt source register for GPIO32-56"] +pub type STATUS_INTERRUPT_NEXT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:24 - GPIO interrupt source register for GPIO32-56"] + #[inline(always)] + pub fn status_interrupt_next1(&self) -> STATUS_INTERRUPT_NEXT1_R { + STATUS_INTERRUPT_NEXT1_R::new(self.bits & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_NEXT1") + .field( + "status_interrupt_next1", + &format_args!("{}", self.status_interrupt_next1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "GPIO interrupt source register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_NEXT1_SPEC; +impl crate::RegisterSpec for STATUS_NEXT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_next1::R`](R) reader structure"] +impl crate::Readable for STATUS_NEXT1_SPEC {} +#[doc = "`reset()` method sets STATUS_NEXT1 to value 0"] +impl crate::Resettable for STATUS_NEXT1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/status_w1tc.rs b/esp32p4/src/gpio/status_w1tc.rs new file mode 100644 index 0000000000..128f9a28d6 --- /dev/null +++ b/esp32p4/src/gpio/status_w1tc.rs @@ -0,0 +1,42 @@ +#[doc = "Register `STATUS_W1TC` writer"] +pub type W = crate::W; +#[doc = "Field `STATUS_W1TC` writer - GPIO interrupt status clear register for GPIO0-31"] +pub type STATUS_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - GPIO interrupt status clear register for GPIO0-31"] + #[inline(always)] + #[must_use] + pub fn status_w1tc(&mut self) -> STATUS_W1TC_W { + STATUS_W1TC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO interrupt status clear register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_W1TC_SPEC; +impl crate::RegisterSpec for STATUS_W1TC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`status_w1tc::W`](W) writer structure"] +impl crate::Writable for STATUS_W1TC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS_W1TC to value 0"] +impl crate::Resettable for STATUS_W1TC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/status_w1ts.rs b/esp32p4/src/gpio/status_w1ts.rs new file mode 100644 index 0000000000..3b4cb2990f --- /dev/null +++ b/esp32p4/src/gpio/status_w1ts.rs @@ -0,0 +1,42 @@ +#[doc = "Register `STATUS_W1TS` writer"] +pub type W = crate::W; +#[doc = "Field `STATUS_W1TS` writer - GPIO interrupt status set register for GPIO0-31"] +pub type STATUS_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - GPIO interrupt status set register for GPIO0-31"] + #[inline(always)] + #[must_use] + pub fn status_w1ts(&mut self) -> STATUS_W1TS_W { + STATUS_W1TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO interrupt status set register for GPIO0-31\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_W1TS_SPEC; +impl crate::RegisterSpec for STATUS_W1TS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`status_w1ts::W`](W) writer structure"] +impl crate::Writable for STATUS_W1TS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS_W1TS to value 0"] +impl crate::Resettable for STATUS_W1TS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/strap.rs b/esp32p4/src/gpio/strap.rs new file mode 100644 index 0000000000..4d14774f46 --- /dev/null +++ b/esp32p4/src/gpio/strap.rs @@ -0,0 +1,36 @@ +#[doc = "Register `STRAP` reader"] +pub type R = crate::R; +#[doc = "Field `STRAPPING` reader - pad strapping register"] +pub type STRAPPING_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - pad strapping register"] + #[inline(always)] + pub fn strapping(&self) -> STRAPPING_R { + STRAPPING_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STRAP") + .field("strapping", &format_args!("{}", self.strapping().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "pad strapping register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`strap::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STRAP_SPEC; +impl crate::RegisterSpec for STRAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`strap::R`](R) reader structure"] +impl crate::Readable for STRAP_SPEC {} +#[doc = "`reset()` method sets STRAP to value 0"] +impl crate::Resettable for STRAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio/zero_det0_filter_cnt.rs b/esp32p4/src/gpio/zero_det0_filter_cnt.rs new file mode 100644 index 0000000000..8a125dc116 --- /dev/null +++ b/esp32p4/src/gpio/zero_det0_filter_cnt.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ZERO_DET0_FILTER_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `ZERO_DET0_FILTER_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `ZERO_DET0_FILTER_CNT` reader - GPIO analog comparator zero detect filter count"] +pub type ZERO_DET0_FILTER_CNT_R = crate::FieldReader; +#[doc = "Field `ZERO_DET0_FILTER_CNT` writer - GPIO analog comparator zero detect filter count"] +pub type ZERO_DET0_FILTER_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - GPIO analog comparator zero detect filter count"] + #[inline(always)] + pub fn zero_det0_filter_cnt(&self) -> ZERO_DET0_FILTER_CNT_R { + ZERO_DET0_FILTER_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ZERO_DET0_FILTER_CNT") + .field( + "zero_det0_filter_cnt", + &format_args!("{}", self.zero_det0_filter_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - GPIO analog comparator zero detect filter count"] + #[inline(always)] + #[must_use] + pub fn zero_det0_filter_cnt(&mut self) -> ZERO_DET0_FILTER_CNT_W { + ZERO_DET0_FILTER_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO analog comparator zero detect filter count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`zero_det0_filter_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`zero_det0_filter_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ZERO_DET0_FILTER_CNT_SPEC; +impl crate::RegisterSpec for ZERO_DET0_FILTER_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`zero_det0_filter_cnt::R`](R) reader structure"] +impl crate::Readable for ZERO_DET0_FILTER_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`zero_det0_filter_cnt::W`](W) writer structure"] +impl crate::Writable for ZERO_DET0_FILTER_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ZERO_DET0_FILTER_CNT to value 0xffff_ffff"] +impl crate::Resettable for ZERO_DET0_FILTER_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/gpio/zero_det1_filter_cnt.rs b/esp32p4/src/gpio/zero_det1_filter_cnt.rs new file mode 100644 index 0000000000..ce2a7db213 --- /dev/null +++ b/esp32p4/src/gpio/zero_det1_filter_cnt.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ZERO_DET1_FILTER_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `ZERO_DET1_FILTER_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `ZERO_DET1_FILTER_CNT` reader - GPIO analog comparator zero detect filter count"] +pub type ZERO_DET1_FILTER_CNT_R = crate::FieldReader; +#[doc = "Field `ZERO_DET1_FILTER_CNT` writer - GPIO analog comparator zero detect filter count"] +pub type ZERO_DET1_FILTER_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - GPIO analog comparator zero detect filter count"] + #[inline(always)] + pub fn zero_det1_filter_cnt(&self) -> ZERO_DET1_FILTER_CNT_R { + ZERO_DET1_FILTER_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ZERO_DET1_FILTER_CNT") + .field( + "zero_det1_filter_cnt", + &format_args!("{}", self.zero_det1_filter_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - GPIO analog comparator zero detect filter count"] + #[inline(always)] + #[must_use] + pub fn zero_det1_filter_cnt(&mut self) -> ZERO_DET1_FILTER_CNT_W { + ZERO_DET1_FILTER_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GPIO analog comparator zero detect filter count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`zero_det1_filter_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`zero_det1_filter_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ZERO_DET1_FILTER_CNT_SPEC; +impl crate::RegisterSpec for ZERO_DET1_FILTER_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`zero_det1_filter_cnt::R`](R) reader structure"] +impl crate::Readable for ZERO_DET1_FILTER_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`zero_det1_filter_cnt::W`](W) writer structure"] +impl crate::Writable for ZERO_DET1_FILTER_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ZERO_DET1_FILTER_CNT to value 0xffff_ffff"] +impl crate::Resettable for ZERO_DET1_FILTER_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/gpio_sd.rs b/esp32p4/src/gpio_sd.rs new file mode 100644 index 0000000000..28003a498b --- /dev/null +++ b/esp32p4/src/gpio_sd.rs @@ -0,0 +1,251 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + sigmadelta: [SIGMADELTA; 8], + clock_gate: CLOCK_GATE, + sigmadelta_misc: SIGMADELTA_MISC, + _reserved3: [u8; 0x08], + glitch_filter_ch: [GLITCH_FILTER_CH; 8], + _reserved4: [u8; 0x10], + etm_event_ch_cfg: [ETM_EVENT_CH_CFG; 8], + _reserved5: [u8; 0x20], + etm_task_p0_cfg: ETM_TASK_P0_CFG, + etm_task_p1_cfg: ETM_TASK_P1_CFG, + etm_task_p2_cfg: ETM_TASK_P2_CFG, + etm_task_p3_cfg: ETM_TASK_P3_CFG, + etm_task_p4_cfg: ETM_TASK_P4_CFG, + etm_task_p5_cfg: ETM_TASK_P5_CFG, + etm_task_p6_cfg: ETM_TASK_P6_CFG, + etm_task_p7_cfg: ETM_TASK_P7_CFG, + etm_task_p8_cfg: ETM_TASK_P8_CFG, + etm_task_p9_cfg: ETM_TASK_P9_CFG, + etm_task_p10_cfg: ETM_TASK_P10_CFG, + etm_task_p11_cfg: ETM_TASK_P11_CFG, + etm_task_p12_cfg: ETM_TASK_P12_CFG, + etm_task_p13_cfg: ETM_TASK_P13_CFG, + _reserved19: [u8; 0x24], + version: VERSION, +} +impl RegisterBlock { + #[doc = "0x00..0x20 - Duty Cycle Configure Register of SDM%s"] + #[inline(always)] + pub const fn sigmadelta(&self, n: usize) -> &SIGMADELTA { + &self.sigmadelta[n] + } + #[doc = "0x20 - Clock Gating Configure Register"] + #[inline(always)] + pub const fn clock_gate(&self) -> &CLOCK_GATE { + &self.clock_gate + } + #[doc = "0x24 - MISC Register"] + #[inline(always)] + pub const fn sigmadelta_misc(&self) -> &SIGMADELTA_MISC { + &self.sigmadelta_misc + } + #[doc = "0x30..0x50 - Glitch Filter Configure Register of Channel%s"] + #[inline(always)] + pub const fn glitch_filter_ch(&self, n: usize) -> &GLITCH_FILTER_CH { + &self.glitch_filter_ch[n] + } + #[doc = "0x60..0x80 - Etm Config register of Channel%s"] + #[inline(always)] + pub const fn etm_event_ch_cfg(&self, n: usize) -> &ETM_EVENT_CH_CFG { + &self.etm_event_ch_cfg[n] + } + #[doc = "0x60 - Etm Config register of Channel0"] + #[inline(always)] + pub const fn etm_event_ch0_cfg(&self) -> &ETM_EVENT_CH_CFG { + &self.etm_event_ch_cfg(0) + } + #[doc = "0x64 - Etm Config register of Channel1"] + #[inline(always)] + pub const fn etm_event_ch1_cfg(&self) -> &ETM_EVENT_CH_CFG { + &self.etm_event_ch_cfg(1) + } + #[doc = "0x68 - Etm Config register of Channel2"] + #[inline(always)] + pub const fn etm_event_ch2_cfg(&self) -> &ETM_EVENT_CH_CFG { + &self.etm_event_ch_cfg(2) + } + #[doc = "0x6c - Etm Config register of Channel3"] + #[inline(always)] + pub const fn etm_event_ch3_cfg(&self) -> &ETM_EVENT_CH_CFG { + &self.etm_event_ch_cfg(3) + } + #[doc = "0x70 - Etm Config register of Channel4"] + #[inline(always)] + pub const fn etm_event_ch4_cfg(&self) -> &ETM_EVENT_CH_CFG { + &self.etm_event_ch_cfg(4) + } + #[doc = "0x74 - Etm Config register of Channel5"] + #[inline(always)] + pub const fn etm_event_ch5_cfg(&self) -> &ETM_EVENT_CH_CFG { + &self.etm_event_ch_cfg(5) + } + #[doc = "0x78 - Etm Config register of Channel6"] + #[inline(always)] + pub const fn etm_event_ch6_cfg(&self) -> &ETM_EVENT_CH_CFG { + &self.etm_event_ch_cfg(6) + } + #[doc = "0x7c - Etm Config register of Channel7"] + #[inline(always)] + pub const fn etm_event_ch7_cfg(&self) -> &ETM_EVENT_CH_CFG { + &self.etm_event_ch_cfg(7) + } + #[doc = "0xa0 - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p0_cfg(&self) -> &ETM_TASK_P0_CFG { + &self.etm_task_p0_cfg + } + #[doc = "0xa4 - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p1_cfg(&self) -> &ETM_TASK_P1_CFG { + &self.etm_task_p1_cfg + } + #[doc = "0xa8 - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p2_cfg(&self) -> &ETM_TASK_P2_CFG { + &self.etm_task_p2_cfg + } + #[doc = "0xac - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p3_cfg(&self) -> &ETM_TASK_P3_CFG { + &self.etm_task_p3_cfg + } + #[doc = "0xb0 - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p4_cfg(&self) -> &ETM_TASK_P4_CFG { + &self.etm_task_p4_cfg + } + #[doc = "0xb4 - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p5_cfg(&self) -> &ETM_TASK_P5_CFG { + &self.etm_task_p5_cfg + } + #[doc = "0xb8 - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p6_cfg(&self) -> &ETM_TASK_P6_CFG { + &self.etm_task_p6_cfg + } + #[doc = "0xbc - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p7_cfg(&self) -> &ETM_TASK_P7_CFG { + &self.etm_task_p7_cfg + } + #[doc = "0xc0 - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p8_cfg(&self) -> &ETM_TASK_P8_CFG { + &self.etm_task_p8_cfg + } + #[doc = "0xc4 - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p9_cfg(&self) -> &ETM_TASK_P9_CFG { + &self.etm_task_p9_cfg + } + #[doc = "0xc8 - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p10_cfg(&self) -> &ETM_TASK_P10_CFG { + &self.etm_task_p10_cfg + } + #[doc = "0xcc - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p11_cfg(&self) -> &ETM_TASK_P11_CFG { + &self.etm_task_p11_cfg + } + #[doc = "0xd0 - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p12_cfg(&self) -> &ETM_TASK_P12_CFG { + &self.etm_task_p12_cfg + } + #[doc = "0xd4 - Etm Configure Register to decide which GPIO been chosen"] + #[inline(always)] + pub const fn etm_task_p13_cfg(&self) -> &ETM_TASK_P13_CFG { + &self.etm_task_p13_cfg + } + #[doc = "0xfc - Version Control Register"] + #[inline(always)] + pub const fn version(&self) -> &VERSION { + &self.version + } +} +#[doc = "SIGMADELTA (rw) register accessor: Duty Cycle Configure Register of SDM%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sigmadelta::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sigmadelta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigmadelta`] module"] +pub type SIGMADELTA = crate::Reg; +#[doc = "Duty Cycle Configure Register of SDM%s"] +pub mod sigmadelta; +#[doc = "CLOCK_GATE (rw) register accessor: Clock Gating Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"] +pub type CLOCK_GATE = crate::Reg; +#[doc = "Clock Gating Configure Register"] +pub mod clock_gate; +#[doc = "SIGMADELTA_MISC (rw) register accessor: MISC Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sigmadelta_misc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sigmadelta_misc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigmadelta_misc`] module"] +pub type SIGMADELTA_MISC = crate::Reg; +#[doc = "MISC Register"] +pub mod sigmadelta_misc; +#[doc = "GLITCH_FILTER_CH (rw) register accessor: Glitch Filter Configure Register of Channel%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`glitch_filter_ch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`glitch_filter_ch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@glitch_filter_ch`] module"] +pub type GLITCH_FILTER_CH = crate::Reg; +#[doc = "Glitch Filter Configure Register of Channel%s"] +pub mod glitch_filter_ch; +#[doc = "ETM_EVENT_CH_CFG (rw) register accessor: Etm Config register of Channel%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_event_ch_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_event_ch_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_event_ch_cfg`] module"] +pub type ETM_EVENT_CH_CFG = crate::Reg; +#[doc = "Etm Config register of Channel%s"] +pub mod etm_event_ch_cfg; +#[doc = "ETM_TASK_P0_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p0_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p0_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p0_cfg`] module"] +pub type ETM_TASK_P0_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p0_cfg; +#[doc = "ETM_TASK_P1_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p1_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p1_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p1_cfg`] module"] +pub type ETM_TASK_P1_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p1_cfg; +#[doc = "ETM_TASK_P2_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p2_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p2_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p2_cfg`] module"] +pub type ETM_TASK_P2_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p2_cfg; +#[doc = "ETM_TASK_P3_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p3_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p3_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p3_cfg`] module"] +pub type ETM_TASK_P3_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p3_cfg; +#[doc = "ETM_TASK_P4_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p4_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p4_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p4_cfg`] module"] +pub type ETM_TASK_P4_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p4_cfg; +#[doc = "ETM_TASK_P5_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p5_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p5_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p5_cfg`] module"] +pub type ETM_TASK_P5_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p5_cfg; +#[doc = "ETM_TASK_P6_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p6_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p6_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p6_cfg`] module"] +pub type ETM_TASK_P6_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p6_cfg; +#[doc = "ETM_TASK_P7_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p7_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p7_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p7_cfg`] module"] +pub type ETM_TASK_P7_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p7_cfg; +#[doc = "ETM_TASK_P8_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p8_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p8_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p8_cfg`] module"] +pub type ETM_TASK_P8_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p8_cfg; +#[doc = "ETM_TASK_P9_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p9_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p9_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p9_cfg`] module"] +pub type ETM_TASK_P9_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p9_cfg; +#[doc = "ETM_TASK_P10_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p10_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p10_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p10_cfg`] module"] +pub type ETM_TASK_P10_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p10_cfg; +#[doc = "ETM_TASK_P11_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p11_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p11_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p11_cfg`] module"] +pub type ETM_TASK_P11_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p11_cfg; +#[doc = "ETM_TASK_P12_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p12_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p12_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p12_cfg`] module"] +pub type ETM_TASK_P12_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p12_cfg; +#[doc = "ETM_TASK_P13_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p13_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p13_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p13_cfg`] module"] +pub type ETM_TASK_P13_CFG = crate::Reg; +#[doc = "Etm Configure Register to decide which GPIO been chosen"] +pub mod etm_task_p13_cfg; +#[doc = "VERSION (rw) register accessor: Version Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"] +pub type VERSION = crate::Reg; +#[doc = "Version Control Register"] +pub mod version; diff --git a/esp32p4/src/gpio_sd/clock_gate.rs b/esp32p4/src/gpio_sd/clock_gate.rs new file mode 100644 index 0000000000..1027c370d8 --- /dev/null +++ b/esp32p4/src/gpio_sd/clock_gate.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLOCK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `CLOCK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - Clock enable bit of configuration registers for sigma delta modulation."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Clock enable bit of configuration registers for sigma delta modulation."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Clock enable bit of configuration registers for sigma delta modulation."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCK_GATE") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Clock enable bit of configuration registers for sigma delta modulation."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock Gating Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLOCK_GATE_SPEC; +impl crate::RegisterSpec for CLOCK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"] +impl crate::Readable for CLOCK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"] +impl crate::Writable for CLOCK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLOCK_GATE to value 0"] +impl crate::Resettable for CLOCK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_event_ch_cfg.rs b/esp32p4/src/gpio_sd/etm_event_ch_cfg.rs new file mode 100644 index 0000000000..7a2e845c46 --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_event_ch_cfg.rs @@ -0,0 +1,85 @@ +#[doc = "Register `ETM_EVENT_CH%s_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_EVENT_CH%s_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_CH0_EVENT_SEL` reader - Etm event channel select gpio."] +pub type ETM_CH0_EVENT_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_CH0_EVENT_SEL` writer - Etm event channel select gpio."] +pub type ETM_CH0_EVENT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `ETM_CH0_EVENT_EN` reader - Etm event send enable bit."] +pub type ETM_CH0_EVENT_EN_R = crate::BitReader; +#[doc = "Field `ETM_CH0_EVENT_EN` writer - Etm event send enable bit."] +pub type ETM_CH0_EVENT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - Etm event channel select gpio."] + #[inline(always)] + pub fn etm_ch0_event_sel(&self) -> ETM_CH0_EVENT_SEL_R { + ETM_CH0_EVENT_SEL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Etm event send enable bit."] + #[inline(always)] + pub fn etm_ch0_event_en(&self) -> ETM_CH0_EVENT_EN_R { + ETM_CH0_EVENT_EN_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_EVENT_CH_CFG") + .field( + "etm_ch0_event_sel", + &format_args!("{}", self.etm_ch0_event_sel().bits()), + ) + .field( + "etm_ch0_event_en", + &format_args!("{}", self.etm_ch0_event_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - Etm event channel select gpio."] + #[inline(always)] + #[must_use] + pub fn etm_ch0_event_sel(&mut self) -> ETM_CH0_EVENT_SEL_W { + ETM_CH0_EVENT_SEL_W::new(self, 0) + } + #[doc = "Bit 7 - Etm event send enable bit."] + #[inline(always)] + #[must_use] + pub fn etm_ch0_event_en(&mut self) -> ETM_CH0_EVENT_EN_W { + ETM_CH0_EVENT_EN_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Config register of Channel%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_event_ch_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_event_ch_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_EVENT_CH_CFG_SPEC; +impl crate::RegisterSpec for ETM_EVENT_CH_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_event_ch_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_EVENT_CH_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_event_ch_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_EVENT_CH_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_EVENT_CH%s_CFG to value 0"] +impl crate::Resettable for ETM_EVENT_CH_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p0_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p0_cfg.rs new file mode 100644 index 0000000000..900d83d9bd --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p0_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P0_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P0_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO0_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO0_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO0_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO0_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO0_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO0_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO1_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO1_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO1_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO1_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO1_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO1_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO2_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO2_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO2_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO2_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO2_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO2_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO2_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO3_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO3_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO3_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO3_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO3_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO3_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO3_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio0_en(&self) -> ETM_TASK_GPIO0_EN_R { + ETM_TASK_GPIO0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio0_sel(&self) -> ETM_TASK_GPIO0_SEL_R { + ETM_TASK_GPIO0_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio1_en(&self) -> ETM_TASK_GPIO1_EN_R { + ETM_TASK_GPIO1_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio1_sel(&self) -> ETM_TASK_GPIO1_SEL_R { + ETM_TASK_GPIO1_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio2_en(&self) -> ETM_TASK_GPIO2_EN_R { + ETM_TASK_GPIO2_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio2_sel(&self) -> ETM_TASK_GPIO2_SEL_R { + ETM_TASK_GPIO2_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio3_en(&self) -> ETM_TASK_GPIO3_EN_R { + ETM_TASK_GPIO3_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio3_sel(&self) -> ETM_TASK_GPIO3_SEL_R { + ETM_TASK_GPIO3_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P0_CFG") + .field( + "etm_task_gpio0_en", + &format_args!("{}", self.etm_task_gpio0_en().bit()), + ) + .field( + "etm_task_gpio0_sel", + &format_args!("{}", self.etm_task_gpio0_sel().bits()), + ) + .field( + "etm_task_gpio1_en", + &format_args!("{}", self.etm_task_gpio1_en().bit()), + ) + .field( + "etm_task_gpio1_sel", + &format_args!("{}", self.etm_task_gpio1_sel().bits()), + ) + .field( + "etm_task_gpio2_en", + &format_args!("{}", self.etm_task_gpio2_en().bit()), + ) + .field( + "etm_task_gpio2_sel", + &format_args!("{}", self.etm_task_gpio2_sel().bits()), + ) + .field( + "etm_task_gpio3_en", + &format_args!("{}", self.etm_task_gpio3_en().bit()), + ) + .field( + "etm_task_gpio3_sel", + &format_args!("{}", self.etm_task_gpio3_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio0_en(&mut self) -> ETM_TASK_GPIO0_EN_W { + ETM_TASK_GPIO0_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio0_sel(&mut self) -> ETM_TASK_GPIO0_SEL_W { + ETM_TASK_GPIO0_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio1_en(&mut self) -> ETM_TASK_GPIO1_EN_W { + ETM_TASK_GPIO1_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio1_sel(&mut self) -> ETM_TASK_GPIO1_SEL_W { + ETM_TASK_GPIO1_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio2_en(&mut self) -> ETM_TASK_GPIO2_EN_W { + ETM_TASK_GPIO2_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio2_sel(&mut self) -> ETM_TASK_GPIO2_SEL_W { + ETM_TASK_GPIO2_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio3_en(&mut self) -> ETM_TASK_GPIO3_EN_W { + ETM_TASK_GPIO3_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio3_sel(&mut self) -> ETM_TASK_GPIO3_SEL_W { + ETM_TASK_GPIO3_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p0_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p0_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P0_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P0_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p0_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P0_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p0_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P0_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P0_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P0_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p10_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p10_cfg.rs new file mode 100644 index 0000000000..16df4098a9 --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p10_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P10_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P10_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO40_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO40_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO40_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO40_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO40_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO40_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO40_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO40_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO41_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO41_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO41_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO41_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO41_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO41_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO41_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO41_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO42_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO42_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO42_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO42_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO42_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO42_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO42_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO42_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO43_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO43_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO43_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO43_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO43_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO43_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO43_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO43_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio40_en(&self) -> ETM_TASK_GPIO40_EN_R { + ETM_TASK_GPIO40_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio40_sel(&self) -> ETM_TASK_GPIO40_SEL_R { + ETM_TASK_GPIO40_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio41_en(&self) -> ETM_TASK_GPIO41_EN_R { + ETM_TASK_GPIO41_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio41_sel(&self) -> ETM_TASK_GPIO41_SEL_R { + ETM_TASK_GPIO41_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio42_en(&self) -> ETM_TASK_GPIO42_EN_R { + ETM_TASK_GPIO42_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio42_sel(&self) -> ETM_TASK_GPIO42_SEL_R { + ETM_TASK_GPIO42_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio43_en(&self) -> ETM_TASK_GPIO43_EN_R { + ETM_TASK_GPIO43_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio43_sel(&self) -> ETM_TASK_GPIO43_SEL_R { + ETM_TASK_GPIO43_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P10_CFG") + .field( + "etm_task_gpio40_en", + &format_args!("{}", self.etm_task_gpio40_en().bit()), + ) + .field( + "etm_task_gpio40_sel", + &format_args!("{}", self.etm_task_gpio40_sel().bits()), + ) + .field( + "etm_task_gpio41_en", + &format_args!("{}", self.etm_task_gpio41_en().bit()), + ) + .field( + "etm_task_gpio41_sel", + &format_args!("{}", self.etm_task_gpio41_sel().bits()), + ) + .field( + "etm_task_gpio42_en", + &format_args!("{}", self.etm_task_gpio42_en().bit()), + ) + .field( + "etm_task_gpio42_sel", + &format_args!("{}", self.etm_task_gpio42_sel().bits()), + ) + .field( + "etm_task_gpio43_en", + &format_args!("{}", self.etm_task_gpio43_en().bit()), + ) + .field( + "etm_task_gpio43_sel", + &format_args!("{}", self.etm_task_gpio43_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio40_en(&mut self) -> ETM_TASK_GPIO40_EN_W { + ETM_TASK_GPIO40_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio40_sel(&mut self) -> ETM_TASK_GPIO40_SEL_W { + ETM_TASK_GPIO40_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio41_en(&mut self) -> ETM_TASK_GPIO41_EN_W { + ETM_TASK_GPIO41_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio41_sel(&mut self) -> ETM_TASK_GPIO41_SEL_W { + ETM_TASK_GPIO41_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio42_en(&mut self) -> ETM_TASK_GPIO42_EN_W { + ETM_TASK_GPIO42_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio42_sel(&mut self) -> ETM_TASK_GPIO42_SEL_W { + ETM_TASK_GPIO42_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio43_en(&mut self) -> ETM_TASK_GPIO43_EN_W { + ETM_TASK_GPIO43_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio43_sel(&mut self) -> ETM_TASK_GPIO43_SEL_W { + ETM_TASK_GPIO43_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p10_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p10_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P10_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P10_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p10_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P10_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p10_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P10_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P10_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P10_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p11_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p11_cfg.rs new file mode 100644 index 0000000000..18a4c29722 --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p11_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P11_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P11_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO44_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO44_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO44_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO44_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO44_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO44_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO44_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO44_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO45_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO45_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO45_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO45_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO45_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO45_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO45_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO45_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO46_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO46_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO46_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO46_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO46_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO46_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO46_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO46_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO47_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO47_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO47_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO47_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO47_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO47_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO47_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO47_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio44_en(&self) -> ETM_TASK_GPIO44_EN_R { + ETM_TASK_GPIO44_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio44_sel(&self) -> ETM_TASK_GPIO44_SEL_R { + ETM_TASK_GPIO44_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio45_en(&self) -> ETM_TASK_GPIO45_EN_R { + ETM_TASK_GPIO45_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio45_sel(&self) -> ETM_TASK_GPIO45_SEL_R { + ETM_TASK_GPIO45_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio46_en(&self) -> ETM_TASK_GPIO46_EN_R { + ETM_TASK_GPIO46_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio46_sel(&self) -> ETM_TASK_GPIO46_SEL_R { + ETM_TASK_GPIO46_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio47_en(&self) -> ETM_TASK_GPIO47_EN_R { + ETM_TASK_GPIO47_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio47_sel(&self) -> ETM_TASK_GPIO47_SEL_R { + ETM_TASK_GPIO47_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P11_CFG") + .field( + "etm_task_gpio44_en", + &format_args!("{}", self.etm_task_gpio44_en().bit()), + ) + .field( + "etm_task_gpio44_sel", + &format_args!("{}", self.etm_task_gpio44_sel().bits()), + ) + .field( + "etm_task_gpio45_en", + &format_args!("{}", self.etm_task_gpio45_en().bit()), + ) + .field( + "etm_task_gpio45_sel", + &format_args!("{}", self.etm_task_gpio45_sel().bits()), + ) + .field( + "etm_task_gpio46_en", + &format_args!("{}", self.etm_task_gpio46_en().bit()), + ) + .field( + "etm_task_gpio46_sel", + &format_args!("{}", self.etm_task_gpio46_sel().bits()), + ) + .field( + "etm_task_gpio47_en", + &format_args!("{}", self.etm_task_gpio47_en().bit()), + ) + .field( + "etm_task_gpio47_sel", + &format_args!("{}", self.etm_task_gpio47_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio44_en(&mut self) -> ETM_TASK_GPIO44_EN_W { + ETM_TASK_GPIO44_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio44_sel(&mut self) -> ETM_TASK_GPIO44_SEL_W { + ETM_TASK_GPIO44_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio45_en(&mut self) -> ETM_TASK_GPIO45_EN_W { + ETM_TASK_GPIO45_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio45_sel(&mut self) -> ETM_TASK_GPIO45_SEL_W { + ETM_TASK_GPIO45_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio46_en(&mut self) -> ETM_TASK_GPIO46_EN_W { + ETM_TASK_GPIO46_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio46_sel(&mut self) -> ETM_TASK_GPIO46_SEL_W { + ETM_TASK_GPIO46_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio47_en(&mut self) -> ETM_TASK_GPIO47_EN_W { + ETM_TASK_GPIO47_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio47_sel(&mut self) -> ETM_TASK_GPIO47_SEL_W { + ETM_TASK_GPIO47_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p11_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p11_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P11_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P11_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p11_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P11_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p11_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P11_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P11_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P11_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p12_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p12_cfg.rs new file mode 100644 index 0000000000..9c91f623a4 --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p12_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P12_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P12_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO48_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO48_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO48_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO48_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO48_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO48_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO48_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO48_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO49_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO49_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO49_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO49_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO49_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO49_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO49_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO49_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO50_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO50_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO50_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO50_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO50_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO50_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO50_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO50_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO51_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO51_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO51_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO51_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO51_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO51_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO51_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO51_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio48_en(&self) -> ETM_TASK_GPIO48_EN_R { + ETM_TASK_GPIO48_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio48_sel(&self) -> ETM_TASK_GPIO48_SEL_R { + ETM_TASK_GPIO48_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio49_en(&self) -> ETM_TASK_GPIO49_EN_R { + ETM_TASK_GPIO49_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio49_sel(&self) -> ETM_TASK_GPIO49_SEL_R { + ETM_TASK_GPIO49_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio50_en(&self) -> ETM_TASK_GPIO50_EN_R { + ETM_TASK_GPIO50_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio50_sel(&self) -> ETM_TASK_GPIO50_SEL_R { + ETM_TASK_GPIO50_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio51_en(&self) -> ETM_TASK_GPIO51_EN_R { + ETM_TASK_GPIO51_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio51_sel(&self) -> ETM_TASK_GPIO51_SEL_R { + ETM_TASK_GPIO51_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P12_CFG") + .field( + "etm_task_gpio48_en", + &format_args!("{}", self.etm_task_gpio48_en().bit()), + ) + .field( + "etm_task_gpio48_sel", + &format_args!("{}", self.etm_task_gpio48_sel().bits()), + ) + .field( + "etm_task_gpio49_en", + &format_args!("{}", self.etm_task_gpio49_en().bit()), + ) + .field( + "etm_task_gpio49_sel", + &format_args!("{}", self.etm_task_gpio49_sel().bits()), + ) + .field( + "etm_task_gpio50_en", + &format_args!("{}", self.etm_task_gpio50_en().bit()), + ) + .field( + "etm_task_gpio50_sel", + &format_args!("{}", self.etm_task_gpio50_sel().bits()), + ) + .field( + "etm_task_gpio51_en", + &format_args!("{}", self.etm_task_gpio51_en().bit()), + ) + .field( + "etm_task_gpio51_sel", + &format_args!("{}", self.etm_task_gpio51_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio48_en(&mut self) -> ETM_TASK_GPIO48_EN_W { + ETM_TASK_GPIO48_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio48_sel(&mut self) -> ETM_TASK_GPIO48_SEL_W { + ETM_TASK_GPIO48_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio49_en(&mut self) -> ETM_TASK_GPIO49_EN_W { + ETM_TASK_GPIO49_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio49_sel(&mut self) -> ETM_TASK_GPIO49_SEL_W { + ETM_TASK_GPIO49_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio50_en(&mut self) -> ETM_TASK_GPIO50_EN_W { + ETM_TASK_GPIO50_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio50_sel(&mut self) -> ETM_TASK_GPIO50_SEL_W { + ETM_TASK_GPIO50_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio51_en(&mut self) -> ETM_TASK_GPIO51_EN_W { + ETM_TASK_GPIO51_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio51_sel(&mut self) -> ETM_TASK_GPIO51_SEL_W { + ETM_TASK_GPIO51_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p12_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p12_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P12_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P12_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p12_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P12_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p12_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P12_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P12_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P12_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p13_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p13_cfg.rs new file mode 100644 index 0000000000..5c51e2e0be --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p13_cfg.rs @@ -0,0 +1,161 @@ +#[doc = "Register `ETM_TASK_P13_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P13_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO52_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO52_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO52_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO52_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO52_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO52_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO52_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO52_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO53_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO53_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO53_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO53_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO53_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO53_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO53_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO53_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO54_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO54_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO54_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO54_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO54_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO54_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO54_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO54_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio52_en(&self) -> ETM_TASK_GPIO52_EN_R { + ETM_TASK_GPIO52_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio52_sel(&self) -> ETM_TASK_GPIO52_SEL_R { + ETM_TASK_GPIO52_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio53_en(&self) -> ETM_TASK_GPIO53_EN_R { + ETM_TASK_GPIO53_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio53_sel(&self) -> ETM_TASK_GPIO53_SEL_R { + ETM_TASK_GPIO53_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio54_en(&self) -> ETM_TASK_GPIO54_EN_R { + ETM_TASK_GPIO54_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio54_sel(&self) -> ETM_TASK_GPIO54_SEL_R { + ETM_TASK_GPIO54_SEL_R::new(((self.bits >> 17) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P13_CFG") + .field( + "etm_task_gpio52_en", + &format_args!("{}", self.etm_task_gpio52_en().bit()), + ) + .field( + "etm_task_gpio52_sel", + &format_args!("{}", self.etm_task_gpio52_sel().bits()), + ) + .field( + "etm_task_gpio53_en", + &format_args!("{}", self.etm_task_gpio53_en().bit()), + ) + .field( + "etm_task_gpio53_sel", + &format_args!("{}", self.etm_task_gpio53_sel().bits()), + ) + .field( + "etm_task_gpio54_en", + &format_args!("{}", self.etm_task_gpio54_en().bit()), + ) + .field( + "etm_task_gpio54_sel", + &format_args!("{}", self.etm_task_gpio54_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio52_en(&mut self) -> ETM_TASK_GPIO52_EN_W { + ETM_TASK_GPIO52_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio52_sel(&mut self) -> ETM_TASK_GPIO52_SEL_W { + ETM_TASK_GPIO52_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio53_en(&mut self) -> ETM_TASK_GPIO53_EN_W { + ETM_TASK_GPIO53_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio53_sel(&mut self) -> ETM_TASK_GPIO53_SEL_W { + ETM_TASK_GPIO53_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio54_en(&mut self) -> ETM_TASK_GPIO54_EN_W { + ETM_TASK_GPIO54_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio54_sel(&mut self) -> ETM_TASK_GPIO54_SEL_W { + ETM_TASK_GPIO54_SEL_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p13_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p13_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P13_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P13_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p13_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P13_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p13_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P13_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P13_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P13_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p1_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p1_cfg.rs new file mode 100644 index 0000000000..1ce6be7e9e --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p1_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P1_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P1_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO4_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO4_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO4_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO4_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO4_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO4_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO4_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO5_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO5_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO5_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO5_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO5_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO5_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO5_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO5_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO6_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO6_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO6_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO6_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO6_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO6_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO6_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO6_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO7_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO7_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO7_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO7_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO7_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO7_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO7_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO7_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio4_en(&self) -> ETM_TASK_GPIO4_EN_R { + ETM_TASK_GPIO4_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio4_sel(&self) -> ETM_TASK_GPIO4_SEL_R { + ETM_TASK_GPIO4_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio5_en(&self) -> ETM_TASK_GPIO5_EN_R { + ETM_TASK_GPIO5_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio5_sel(&self) -> ETM_TASK_GPIO5_SEL_R { + ETM_TASK_GPIO5_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio6_en(&self) -> ETM_TASK_GPIO6_EN_R { + ETM_TASK_GPIO6_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio6_sel(&self) -> ETM_TASK_GPIO6_SEL_R { + ETM_TASK_GPIO6_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio7_en(&self) -> ETM_TASK_GPIO7_EN_R { + ETM_TASK_GPIO7_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio7_sel(&self) -> ETM_TASK_GPIO7_SEL_R { + ETM_TASK_GPIO7_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P1_CFG") + .field( + "etm_task_gpio4_en", + &format_args!("{}", self.etm_task_gpio4_en().bit()), + ) + .field( + "etm_task_gpio4_sel", + &format_args!("{}", self.etm_task_gpio4_sel().bits()), + ) + .field( + "etm_task_gpio5_en", + &format_args!("{}", self.etm_task_gpio5_en().bit()), + ) + .field( + "etm_task_gpio5_sel", + &format_args!("{}", self.etm_task_gpio5_sel().bits()), + ) + .field( + "etm_task_gpio6_en", + &format_args!("{}", self.etm_task_gpio6_en().bit()), + ) + .field( + "etm_task_gpio6_sel", + &format_args!("{}", self.etm_task_gpio6_sel().bits()), + ) + .field( + "etm_task_gpio7_en", + &format_args!("{}", self.etm_task_gpio7_en().bit()), + ) + .field( + "etm_task_gpio7_sel", + &format_args!("{}", self.etm_task_gpio7_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio4_en(&mut self) -> ETM_TASK_GPIO4_EN_W { + ETM_TASK_GPIO4_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio4_sel(&mut self) -> ETM_TASK_GPIO4_SEL_W { + ETM_TASK_GPIO4_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio5_en(&mut self) -> ETM_TASK_GPIO5_EN_W { + ETM_TASK_GPIO5_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio5_sel(&mut self) -> ETM_TASK_GPIO5_SEL_W { + ETM_TASK_GPIO5_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio6_en(&mut self) -> ETM_TASK_GPIO6_EN_W { + ETM_TASK_GPIO6_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio6_sel(&mut self) -> ETM_TASK_GPIO6_SEL_W { + ETM_TASK_GPIO6_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio7_en(&mut self) -> ETM_TASK_GPIO7_EN_W { + ETM_TASK_GPIO7_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio7_sel(&mut self) -> ETM_TASK_GPIO7_SEL_W { + ETM_TASK_GPIO7_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p1_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p1_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P1_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P1_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p1_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P1_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p1_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P1_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P1_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P1_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p2_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p2_cfg.rs new file mode 100644 index 0000000000..b0d6f863bb --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p2_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P2_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P2_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO8_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO8_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO8_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO8_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO8_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO8_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO8_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO8_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO9_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO9_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO9_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO9_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO9_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO9_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO9_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO9_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO10_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO10_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO10_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO10_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO10_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO10_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO10_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO10_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO11_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO11_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO11_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO11_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO11_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO11_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO11_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO11_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio8_en(&self) -> ETM_TASK_GPIO8_EN_R { + ETM_TASK_GPIO8_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio8_sel(&self) -> ETM_TASK_GPIO8_SEL_R { + ETM_TASK_GPIO8_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio9_en(&self) -> ETM_TASK_GPIO9_EN_R { + ETM_TASK_GPIO9_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio9_sel(&self) -> ETM_TASK_GPIO9_SEL_R { + ETM_TASK_GPIO9_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio10_en(&self) -> ETM_TASK_GPIO10_EN_R { + ETM_TASK_GPIO10_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio10_sel(&self) -> ETM_TASK_GPIO10_SEL_R { + ETM_TASK_GPIO10_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio11_en(&self) -> ETM_TASK_GPIO11_EN_R { + ETM_TASK_GPIO11_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio11_sel(&self) -> ETM_TASK_GPIO11_SEL_R { + ETM_TASK_GPIO11_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P2_CFG") + .field( + "etm_task_gpio8_en", + &format_args!("{}", self.etm_task_gpio8_en().bit()), + ) + .field( + "etm_task_gpio8_sel", + &format_args!("{}", self.etm_task_gpio8_sel().bits()), + ) + .field( + "etm_task_gpio9_en", + &format_args!("{}", self.etm_task_gpio9_en().bit()), + ) + .field( + "etm_task_gpio9_sel", + &format_args!("{}", self.etm_task_gpio9_sel().bits()), + ) + .field( + "etm_task_gpio10_en", + &format_args!("{}", self.etm_task_gpio10_en().bit()), + ) + .field( + "etm_task_gpio10_sel", + &format_args!("{}", self.etm_task_gpio10_sel().bits()), + ) + .field( + "etm_task_gpio11_en", + &format_args!("{}", self.etm_task_gpio11_en().bit()), + ) + .field( + "etm_task_gpio11_sel", + &format_args!("{}", self.etm_task_gpio11_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio8_en(&mut self) -> ETM_TASK_GPIO8_EN_W { + ETM_TASK_GPIO8_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio8_sel(&mut self) -> ETM_TASK_GPIO8_SEL_W { + ETM_TASK_GPIO8_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio9_en(&mut self) -> ETM_TASK_GPIO9_EN_W { + ETM_TASK_GPIO9_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio9_sel(&mut self) -> ETM_TASK_GPIO9_SEL_W { + ETM_TASK_GPIO9_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio10_en(&mut self) -> ETM_TASK_GPIO10_EN_W { + ETM_TASK_GPIO10_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio10_sel(&mut self) -> ETM_TASK_GPIO10_SEL_W { + ETM_TASK_GPIO10_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio11_en(&mut self) -> ETM_TASK_GPIO11_EN_W { + ETM_TASK_GPIO11_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio11_sel(&mut self) -> ETM_TASK_GPIO11_SEL_W { + ETM_TASK_GPIO11_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p2_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p2_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P2_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P2_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p2_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P2_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p2_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P2_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P2_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P2_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p3_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p3_cfg.rs new file mode 100644 index 0000000000..3056c5e051 --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p3_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P3_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P3_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO12_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO12_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO12_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO12_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO12_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO12_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO12_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO12_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO13_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO13_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO13_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO13_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO13_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO13_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO13_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO13_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO14_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO14_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO14_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO14_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO14_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO14_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO14_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO14_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO15_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO15_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO15_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO15_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO15_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO15_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO15_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO15_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio12_en(&self) -> ETM_TASK_GPIO12_EN_R { + ETM_TASK_GPIO12_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio12_sel(&self) -> ETM_TASK_GPIO12_SEL_R { + ETM_TASK_GPIO12_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio13_en(&self) -> ETM_TASK_GPIO13_EN_R { + ETM_TASK_GPIO13_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio13_sel(&self) -> ETM_TASK_GPIO13_SEL_R { + ETM_TASK_GPIO13_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio14_en(&self) -> ETM_TASK_GPIO14_EN_R { + ETM_TASK_GPIO14_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio14_sel(&self) -> ETM_TASK_GPIO14_SEL_R { + ETM_TASK_GPIO14_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio15_en(&self) -> ETM_TASK_GPIO15_EN_R { + ETM_TASK_GPIO15_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio15_sel(&self) -> ETM_TASK_GPIO15_SEL_R { + ETM_TASK_GPIO15_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P3_CFG") + .field( + "etm_task_gpio12_en", + &format_args!("{}", self.etm_task_gpio12_en().bit()), + ) + .field( + "etm_task_gpio12_sel", + &format_args!("{}", self.etm_task_gpio12_sel().bits()), + ) + .field( + "etm_task_gpio13_en", + &format_args!("{}", self.etm_task_gpio13_en().bit()), + ) + .field( + "etm_task_gpio13_sel", + &format_args!("{}", self.etm_task_gpio13_sel().bits()), + ) + .field( + "etm_task_gpio14_en", + &format_args!("{}", self.etm_task_gpio14_en().bit()), + ) + .field( + "etm_task_gpio14_sel", + &format_args!("{}", self.etm_task_gpio14_sel().bits()), + ) + .field( + "etm_task_gpio15_en", + &format_args!("{}", self.etm_task_gpio15_en().bit()), + ) + .field( + "etm_task_gpio15_sel", + &format_args!("{}", self.etm_task_gpio15_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio12_en(&mut self) -> ETM_TASK_GPIO12_EN_W { + ETM_TASK_GPIO12_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio12_sel(&mut self) -> ETM_TASK_GPIO12_SEL_W { + ETM_TASK_GPIO12_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio13_en(&mut self) -> ETM_TASK_GPIO13_EN_W { + ETM_TASK_GPIO13_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio13_sel(&mut self) -> ETM_TASK_GPIO13_SEL_W { + ETM_TASK_GPIO13_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio14_en(&mut self) -> ETM_TASK_GPIO14_EN_W { + ETM_TASK_GPIO14_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio14_sel(&mut self) -> ETM_TASK_GPIO14_SEL_W { + ETM_TASK_GPIO14_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio15_en(&mut self) -> ETM_TASK_GPIO15_EN_W { + ETM_TASK_GPIO15_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio15_sel(&mut self) -> ETM_TASK_GPIO15_SEL_W { + ETM_TASK_GPIO15_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p3_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p3_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P3_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P3_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p3_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P3_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p3_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P3_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P3_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P3_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p4_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p4_cfg.rs new file mode 100644 index 0000000000..20bbed02ac --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p4_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P4_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P4_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO16_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO16_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO16_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO16_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO16_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO16_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO16_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO16_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO17_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO17_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO17_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO17_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO17_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO17_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO17_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO17_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO18_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO18_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO18_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO18_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO18_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO18_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO18_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO18_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO19_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO19_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO19_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO19_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO19_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO19_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO19_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO19_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio16_en(&self) -> ETM_TASK_GPIO16_EN_R { + ETM_TASK_GPIO16_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio16_sel(&self) -> ETM_TASK_GPIO16_SEL_R { + ETM_TASK_GPIO16_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio17_en(&self) -> ETM_TASK_GPIO17_EN_R { + ETM_TASK_GPIO17_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio17_sel(&self) -> ETM_TASK_GPIO17_SEL_R { + ETM_TASK_GPIO17_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio18_en(&self) -> ETM_TASK_GPIO18_EN_R { + ETM_TASK_GPIO18_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio18_sel(&self) -> ETM_TASK_GPIO18_SEL_R { + ETM_TASK_GPIO18_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio19_en(&self) -> ETM_TASK_GPIO19_EN_R { + ETM_TASK_GPIO19_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio19_sel(&self) -> ETM_TASK_GPIO19_SEL_R { + ETM_TASK_GPIO19_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P4_CFG") + .field( + "etm_task_gpio16_en", + &format_args!("{}", self.etm_task_gpio16_en().bit()), + ) + .field( + "etm_task_gpio16_sel", + &format_args!("{}", self.etm_task_gpio16_sel().bits()), + ) + .field( + "etm_task_gpio17_en", + &format_args!("{}", self.etm_task_gpio17_en().bit()), + ) + .field( + "etm_task_gpio17_sel", + &format_args!("{}", self.etm_task_gpio17_sel().bits()), + ) + .field( + "etm_task_gpio18_en", + &format_args!("{}", self.etm_task_gpio18_en().bit()), + ) + .field( + "etm_task_gpio18_sel", + &format_args!("{}", self.etm_task_gpio18_sel().bits()), + ) + .field( + "etm_task_gpio19_en", + &format_args!("{}", self.etm_task_gpio19_en().bit()), + ) + .field( + "etm_task_gpio19_sel", + &format_args!("{}", self.etm_task_gpio19_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio16_en(&mut self) -> ETM_TASK_GPIO16_EN_W { + ETM_TASK_GPIO16_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio16_sel(&mut self) -> ETM_TASK_GPIO16_SEL_W { + ETM_TASK_GPIO16_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio17_en(&mut self) -> ETM_TASK_GPIO17_EN_W { + ETM_TASK_GPIO17_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio17_sel(&mut self) -> ETM_TASK_GPIO17_SEL_W { + ETM_TASK_GPIO17_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio18_en(&mut self) -> ETM_TASK_GPIO18_EN_W { + ETM_TASK_GPIO18_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio18_sel(&mut self) -> ETM_TASK_GPIO18_SEL_W { + ETM_TASK_GPIO18_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio19_en(&mut self) -> ETM_TASK_GPIO19_EN_W { + ETM_TASK_GPIO19_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio19_sel(&mut self) -> ETM_TASK_GPIO19_SEL_W { + ETM_TASK_GPIO19_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p4_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p4_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P4_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P4_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p4_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P4_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p4_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P4_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P4_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P4_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p5_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p5_cfg.rs new file mode 100644 index 0000000000..2864db5663 --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p5_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P5_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P5_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO20_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO20_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO20_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO20_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO20_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO20_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO20_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO20_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO21_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO21_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO21_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO21_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO21_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO21_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO21_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO21_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO22_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO22_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO22_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO22_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO22_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO22_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO22_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO22_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO23_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO23_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO23_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO23_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO23_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO23_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO23_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO23_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio20_en(&self) -> ETM_TASK_GPIO20_EN_R { + ETM_TASK_GPIO20_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio20_sel(&self) -> ETM_TASK_GPIO20_SEL_R { + ETM_TASK_GPIO20_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio21_en(&self) -> ETM_TASK_GPIO21_EN_R { + ETM_TASK_GPIO21_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio21_sel(&self) -> ETM_TASK_GPIO21_SEL_R { + ETM_TASK_GPIO21_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio22_en(&self) -> ETM_TASK_GPIO22_EN_R { + ETM_TASK_GPIO22_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio22_sel(&self) -> ETM_TASK_GPIO22_SEL_R { + ETM_TASK_GPIO22_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio23_en(&self) -> ETM_TASK_GPIO23_EN_R { + ETM_TASK_GPIO23_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio23_sel(&self) -> ETM_TASK_GPIO23_SEL_R { + ETM_TASK_GPIO23_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P5_CFG") + .field( + "etm_task_gpio20_en", + &format_args!("{}", self.etm_task_gpio20_en().bit()), + ) + .field( + "etm_task_gpio20_sel", + &format_args!("{}", self.etm_task_gpio20_sel().bits()), + ) + .field( + "etm_task_gpio21_en", + &format_args!("{}", self.etm_task_gpio21_en().bit()), + ) + .field( + "etm_task_gpio21_sel", + &format_args!("{}", self.etm_task_gpio21_sel().bits()), + ) + .field( + "etm_task_gpio22_en", + &format_args!("{}", self.etm_task_gpio22_en().bit()), + ) + .field( + "etm_task_gpio22_sel", + &format_args!("{}", self.etm_task_gpio22_sel().bits()), + ) + .field( + "etm_task_gpio23_en", + &format_args!("{}", self.etm_task_gpio23_en().bit()), + ) + .field( + "etm_task_gpio23_sel", + &format_args!("{}", self.etm_task_gpio23_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio20_en(&mut self) -> ETM_TASK_GPIO20_EN_W { + ETM_TASK_GPIO20_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio20_sel(&mut self) -> ETM_TASK_GPIO20_SEL_W { + ETM_TASK_GPIO20_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio21_en(&mut self) -> ETM_TASK_GPIO21_EN_W { + ETM_TASK_GPIO21_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio21_sel(&mut self) -> ETM_TASK_GPIO21_SEL_W { + ETM_TASK_GPIO21_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio22_en(&mut self) -> ETM_TASK_GPIO22_EN_W { + ETM_TASK_GPIO22_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio22_sel(&mut self) -> ETM_TASK_GPIO22_SEL_W { + ETM_TASK_GPIO22_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio23_en(&mut self) -> ETM_TASK_GPIO23_EN_W { + ETM_TASK_GPIO23_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio23_sel(&mut self) -> ETM_TASK_GPIO23_SEL_W { + ETM_TASK_GPIO23_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p5_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p5_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P5_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P5_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p5_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P5_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p5_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P5_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P5_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P5_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p6_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p6_cfg.rs new file mode 100644 index 0000000000..f1e764701b --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p6_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P6_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P6_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO24_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO24_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO24_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO24_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO24_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO24_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO24_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO24_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO25_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO25_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO25_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO25_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO25_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO25_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO25_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO25_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO26_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO26_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO26_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO26_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO26_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO26_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO26_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO26_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO27_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO27_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO27_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO27_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO27_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO27_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO27_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO27_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio24_en(&self) -> ETM_TASK_GPIO24_EN_R { + ETM_TASK_GPIO24_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio24_sel(&self) -> ETM_TASK_GPIO24_SEL_R { + ETM_TASK_GPIO24_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio25_en(&self) -> ETM_TASK_GPIO25_EN_R { + ETM_TASK_GPIO25_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio25_sel(&self) -> ETM_TASK_GPIO25_SEL_R { + ETM_TASK_GPIO25_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio26_en(&self) -> ETM_TASK_GPIO26_EN_R { + ETM_TASK_GPIO26_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio26_sel(&self) -> ETM_TASK_GPIO26_SEL_R { + ETM_TASK_GPIO26_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio27_en(&self) -> ETM_TASK_GPIO27_EN_R { + ETM_TASK_GPIO27_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio27_sel(&self) -> ETM_TASK_GPIO27_SEL_R { + ETM_TASK_GPIO27_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P6_CFG") + .field( + "etm_task_gpio24_en", + &format_args!("{}", self.etm_task_gpio24_en().bit()), + ) + .field( + "etm_task_gpio24_sel", + &format_args!("{}", self.etm_task_gpio24_sel().bits()), + ) + .field( + "etm_task_gpio25_en", + &format_args!("{}", self.etm_task_gpio25_en().bit()), + ) + .field( + "etm_task_gpio25_sel", + &format_args!("{}", self.etm_task_gpio25_sel().bits()), + ) + .field( + "etm_task_gpio26_en", + &format_args!("{}", self.etm_task_gpio26_en().bit()), + ) + .field( + "etm_task_gpio26_sel", + &format_args!("{}", self.etm_task_gpio26_sel().bits()), + ) + .field( + "etm_task_gpio27_en", + &format_args!("{}", self.etm_task_gpio27_en().bit()), + ) + .field( + "etm_task_gpio27_sel", + &format_args!("{}", self.etm_task_gpio27_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio24_en(&mut self) -> ETM_TASK_GPIO24_EN_W { + ETM_TASK_GPIO24_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio24_sel(&mut self) -> ETM_TASK_GPIO24_SEL_W { + ETM_TASK_GPIO24_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio25_en(&mut self) -> ETM_TASK_GPIO25_EN_W { + ETM_TASK_GPIO25_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio25_sel(&mut self) -> ETM_TASK_GPIO25_SEL_W { + ETM_TASK_GPIO25_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio26_en(&mut self) -> ETM_TASK_GPIO26_EN_W { + ETM_TASK_GPIO26_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio26_sel(&mut self) -> ETM_TASK_GPIO26_SEL_W { + ETM_TASK_GPIO26_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio27_en(&mut self) -> ETM_TASK_GPIO27_EN_W { + ETM_TASK_GPIO27_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio27_sel(&mut self) -> ETM_TASK_GPIO27_SEL_W { + ETM_TASK_GPIO27_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p6_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p6_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P6_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P6_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p6_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P6_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p6_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P6_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P6_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P6_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p7_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p7_cfg.rs new file mode 100644 index 0000000000..7e894397ab --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p7_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P7_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P7_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO28_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO28_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO28_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO28_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO28_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO28_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO28_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO28_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO29_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO29_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO29_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO29_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO29_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO29_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO29_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO29_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO30_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO30_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO30_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO30_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO30_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO30_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO30_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO30_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO31_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO31_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO31_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO31_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO31_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO31_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO31_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO31_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio28_en(&self) -> ETM_TASK_GPIO28_EN_R { + ETM_TASK_GPIO28_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio28_sel(&self) -> ETM_TASK_GPIO28_SEL_R { + ETM_TASK_GPIO28_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio29_en(&self) -> ETM_TASK_GPIO29_EN_R { + ETM_TASK_GPIO29_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio29_sel(&self) -> ETM_TASK_GPIO29_SEL_R { + ETM_TASK_GPIO29_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio30_en(&self) -> ETM_TASK_GPIO30_EN_R { + ETM_TASK_GPIO30_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio30_sel(&self) -> ETM_TASK_GPIO30_SEL_R { + ETM_TASK_GPIO30_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio31_en(&self) -> ETM_TASK_GPIO31_EN_R { + ETM_TASK_GPIO31_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio31_sel(&self) -> ETM_TASK_GPIO31_SEL_R { + ETM_TASK_GPIO31_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P7_CFG") + .field( + "etm_task_gpio28_en", + &format_args!("{}", self.etm_task_gpio28_en().bit()), + ) + .field( + "etm_task_gpio28_sel", + &format_args!("{}", self.etm_task_gpio28_sel().bits()), + ) + .field( + "etm_task_gpio29_en", + &format_args!("{}", self.etm_task_gpio29_en().bit()), + ) + .field( + "etm_task_gpio29_sel", + &format_args!("{}", self.etm_task_gpio29_sel().bits()), + ) + .field( + "etm_task_gpio30_en", + &format_args!("{}", self.etm_task_gpio30_en().bit()), + ) + .field( + "etm_task_gpio30_sel", + &format_args!("{}", self.etm_task_gpio30_sel().bits()), + ) + .field( + "etm_task_gpio31_en", + &format_args!("{}", self.etm_task_gpio31_en().bit()), + ) + .field( + "etm_task_gpio31_sel", + &format_args!("{}", self.etm_task_gpio31_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio28_en(&mut self) -> ETM_TASK_GPIO28_EN_W { + ETM_TASK_GPIO28_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio28_sel(&mut self) -> ETM_TASK_GPIO28_SEL_W { + ETM_TASK_GPIO28_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio29_en(&mut self) -> ETM_TASK_GPIO29_EN_W { + ETM_TASK_GPIO29_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio29_sel(&mut self) -> ETM_TASK_GPIO29_SEL_W { + ETM_TASK_GPIO29_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio30_en(&mut self) -> ETM_TASK_GPIO30_EN_W { + ETM_TASK_GPIO30_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio30_sel(&mut self) -> ETM_TASK_GPIO30_SEL_W { + ETM_TASK_GPIO30_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio31_en(&mut self) -> ETM_TASK_GPIO31_EN_W { + ETM_TASK_GPIO31_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio31_sel(&mut self) -> ETM_TASK_GPIO31_SEL_W { + ETM_TASK_GPIO31_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p7_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p7_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P7_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P7_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p7_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P7_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p7_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P7_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P7_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P7_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p8_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p8_cfg.rs new file mode 100644 index 0000000000..58b19e7ba7 --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p8_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P8_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P8_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO32_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO32_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO32_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO32_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO32_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO32_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO32_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO32_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO33_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO33_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO33_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO33_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO33_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO33_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO33_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO33_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO34_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO34_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO34_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO34_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO34_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO34_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO34_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO34_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO35_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO35_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO35_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO35_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO35_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO35_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO35_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO35_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio32_en(&self) -> ETM_TASK_GPIO32_EN_R { + ETM_TASK_GPIO32_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio32_sel(&self) -> ETM_TASK_GPIO32_SEL_R { + ETM_TASK_GPIO32_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio33_en(&self) -> ETM_TASK_GPIO33_EN_R { + ETM_TASK_GPIO33_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio33_sel(&self) -> ETM_TASK_GPIO33_SEL_R { + ETM_TASK_GPIO33_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio34_en(&self) -> ETM_TASK_GPIO34_EN_R { + ETM_TASK_GPIO34_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio34_sel(&self) -> ETM_TASK_GPIO34_SEL_R { + ETM_TASK_GPIO34_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio35_en(&self) -> ETM_TASK_GPIO35_EN_R { + ETM_TASK_GPIO35_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio35_sel(&self) -> ETM_TASK_GPIO35_SEL_R { + ETM_TASK_GPIO35_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P8_CFG") + .field( + "etm_task_gpio32_en", + &format_args!("{}", self.etm_task_gpio32_en().bit()), + ) + .field( + "etm_task_gpio32_sel", + &format_args!("{}", self.etm_task_gpio32_sel().bits()), + ) + .field( + "etm_task_gpio33_en", + &format_args!("{}", self.etm_task_gpio33_en().bit()), + ) + .field( + "etm_task_gpio33_sel", + &format_args!("{}", self.etm_task_gpio33_sel().bits()), + ) + .field( + "etm_task_gpio34_en", + &format_args!("{}", self.etm_task_gpio34_en().bit()), + ) + .field( + "etm_task_gpio34_sel", + &format_args!("{}", self.etm_task_gpio34_sel().bits()), + ) + .field( + "etm_task_gpio35_en", + &format_args!("{}", self.etm_task_gpio35_en().bit()), + ) + .field( + "etm_task_gpio35_sel", + &format_args!("{}", self.etm_task_gpio35_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio32_en(&mut self) -> ETM_TASK_GPIO32_EN_W { + ETM_TASK_GPIO32_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio32_sel(&mut self) -> ETM_TASK_GPIO32_SEL_W { + ETM_TASK_GPIO32_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio33_en(&mut self) -> ETM_TASK_GPIO33_EN_W { + ETM_TASK_GPIO33_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio33_sel(&mut self) -> ETM_TASK_GPIO33_SEL_W { + ETM_TASK_GPIO33_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio34_en(&mut self) -> ETM_TASK_GPIO34_EN_W { + ETM_TASK_GPIO34_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio34_sel(&mut self) -> ETM_TASK_GPIO34_SEL_W { + ETM_TASK_GPIO34_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio35_en(&mut self) -> ETM_TASK_GPIO35_EN_W { + ETM_TASK_GPIO35_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio35_sel(&mut self) -> ETM_TASK_GPIO35_SEL_W { + ETM_TASK_GPIO35_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p8_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p8_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P8_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P8_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p8_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P8_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p8_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P8_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P8_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P8_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/etm_task_p9_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p9_cfg.rs new file mode 100644 index 0000000000..9b9feaaf49 --- /dev/null +++ b/esp32p4/src/gpio_sd/etm_task_p9_cfg.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ETM_TASK_P9_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_TASK_P9_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TASK_GPIO36_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO36_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO36_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO36_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO36_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO36_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO36_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO36_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO37_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO37_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO37_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO37_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO37_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO37_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO37_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO37_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO38_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO38_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO38_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO38_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO38_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO38_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO38_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO38_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ETM_TASK_GPIO39_EN` reader - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO39_EN_R = crate::BitReader; +#[doc = "Field `ETM_TASK_GPIO39_EN` writer - Enable bit of GPIO response etm task."] +pub type ETM_TASK_GPIO39_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_GPIO39_SEL` reader - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO39_SEL_R = crate::FieldReader; +#[doc = "Field `ETM_TASK_GPIO39_SEL` writer - GPIO choose a etm task channel."] +pub type ETM_TASK_GPIO39_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio36_en(&self) -> ETM_TASK_GPIO36_EN_R { + ETM_TASK_GPIO36_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio36_sel(&self) -> ETM_TASK_GPIO36_SEL_R { + ETM_TASK_GPIO36_SEL_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio37_en(&self) -> ETM_TASK_GPIO37_EN_R { + ETM_TASK_GPIO37_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio37_sel(&self) -> ETM_TASK_GPIO37_SEL_R { + ETM_TASK_GPIO37_SEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio38_en(&self) -> ETM_TASK_GPIO38_EN_R { + ETM_TASK_GPIO38_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio38_sel(&self) -> ETM_TASK_GPIO38_SEL_R { + ETM_TASK_GPIO38_SEL_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + pub fn etm_task_gpio39_en(&self) -> ETM_TASK_GPIO39_EN_R { + ETM_TASK_GPIO39_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + pub fn etm_task_gpio39_sel(&self) -> ETM_TASK_GPIO39_SEL_R { + ETM_TASK_GPIO39_SEL_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_TASK_P9_CFG") + .field( + "etm_task_gpio36_en", + &format_args!("{}", self.etm_task_gpio36_en().bit()), + ) + .field( + "etm_task_gpio36_sel", + &format_args!("{}", self.etm_task_gpio36_sel().bits()), + ) + .field( + "etm_task_gpio37_en", + &format_args!("{}", self.etm_task_gpio37_en().bit()), + ) + .field( + "etm_task_gpio37_sel", + &format_args!("{}", self.etm_task_gpio37_sel().bits()), + ) + .field( + "etm_task_gpio38_en", + &format_args!("{}", self.etm_task_gpio38_en().bit()), + ) + .field( + "etm_task_gpio38_sel", + &format_args!("{}", self.etm_task_gpio38_sel().bits()), + ) + .field( + "etm_task_gpio39_en", + &format_args!("{}", self.etm_task_gpio39_en().bit()), + ) + .field( + "etm_task_gpio39_sel", + &format_args!("{}", self.etm_task_gpio39_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio36_en(&mut self) -> ETM_TASK_GPIO36_EN_W { + ETM_TASK_GPIO36_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio36_sel(&mut self) -> ETM_TASK_GPIO36_SEL_W { + ETM_TASK_GPIO36_SEL_W::new(self, 1) + } + #[doc = "Bit 8 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio37_en(&mut self) -> ETM_TASK_GPIO37_EN_W { + ETM_TASK_GPIO37_EN_W::new(self, 8) + } + #[doc = "Bits 9:11 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio37_sel(&mut self) -> ETM_TASK_GPIO37_SEL_W { + ETM_TASK_GPIO37_SEL_W::new(self, 9) + } + #[doc = "Bit 16 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio38_en(&mut self) -> ETM_TASK_GPIO38_EN_W { + ETM_TASK_GPIO38_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio38_sel(&mut self) -> ETM_TASK_GPIO38_SEL_W { + ETM_TASK_GPIO38_SEL_W::new(self, 17) + } + #[doc = "Bit 24 - Enable bit of GPIO response etm task."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio39_en(&mut self) -> ETM_TASK_GPIO39_EN_W { + ETM_TASK_GPIO39_EN_W::new(self, 24) + } + #[doc = "Bits 25:27 - GPIO choose a etm task channel."] + #[inline(always)] + #[must_use] + pub fn etm_task_gpio39_sel(&mut self) -> ETM_TASK_GPIO39_SEL_W { + ETM_TASK_GPIO39_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_task_p9_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_task_p9_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_TASK_P9_CFG_SPEC; +impl crate::RegisterSpec for ETM_TASK_P9_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_task_p9_cfg::R`](R) reader structure"] +impl crate::Readable for ETM_TASK_P9_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_task_p9_cfg::W`](W) writer structure"] +impl crate::Writable for ETM_TASK_P9_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_TASK_P9_CFG to value 0"] +impl crate::Resettable for ETM_TASK_P9_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/glitch_filter_ch.rs b/esp32p4/src/gpio_sd/glitch_filter_ch.rs new file mode 100644 index 0000000000..2520d9e8d8 --- /dev/null +++ b/esp32p4/src/gpio_sd/glitch_filter_ch.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GLITCH_FILTER_CH%s` reader"] +pub type R = crate::R; +#[doc = "Register `GLITCH_FILTER_CH%s` writer"] +pub type W = crate::W; +#[doc = "Field `FILTER_CH0_EN` reader - Glitch Filter channel enable bit."] +pub type FILTER_CH0_EN_R = crate::BitReader; +#[doc = "Field `FILTER_CH0_EN` writer - Glitch Filter channel enable bit."] +pub type FILTER_CH0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FILTER_CH0_INPUT_IO_NUM` reader - Glitch Filter input io number."] +pub type FILTER_CH0_INPUT_IO_NUM_R = crate::FieldReader; +#[doc = "Field `FILTER_CH0_INPUT_IO_NUM` writer - Glitch Filter input io number."] +pub type FILTER_CH0_INPUT_IO_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FILTER_CH0_WINDOW_THRES` reader - Glitch Filter window threshold."] +pub type FILTER_CH0_WINDOW_THRES_R = crate::FieldReader; +#[doc = "Field `FILTER_CH0_WINDOW_THRES` writer - Glitch Filter window threshold."] +pub type FILTER_CH0_WINDOW_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `FILTER_CH0_WINDOW_WIDTH` reader - Glitch Filter window width."] +pub type FILTER_CH0_WINDOW_WIDTH_R = crate::FieldReader; +#[doc = "Field `FILTER_CH0_WINDOW_WIDTH` writer - Glitch Filter window width."] +pub type FILTER_CH0_WINDOW_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Glitch Filter channel enable bit."] + #[inline(always)] + pub fn filter_ch0_en(&self) -> FILTER_CH0_EN_R { + FILTER_CH0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:6 - Glitch Filter input io number."] + #[inline(always)] + pub fn filter_ch0_input_io_num(&self) -> FILTER_CH0_INPUT_IO_NUM_R { + FILTER_CH0_INPUT_IO_NUM_R::new(((self.bits >> 1) & 0x3f) as u8) + } + #[doc = "Bits 7:12 - Glitch Filter window threshold."] + #[inline(always)] + pub fn filter_ch0_window_thres(&self) -> FILTER_CH0_WINDOW_THRES_R { + FILTER_CH0_WINDOW_THRES_R::new(((self.bits >> 7) & 0x3f) as u8) + } + #[doc = "Bits 13:18 - Glitch Filter window width."] + #[inline(always)] + pub fn filter_ch0_window_width(&self) -> FILTER_CH0_WINDOW_WIDTH_R { + FILTER_CH0_WINDOW_WIDTH_R::new(((self.bits >> 13) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GLITCH_FILTER_CH") + .field( + "filter_ch0_en", + &format_args!("{}", self.filter_ch0_en().bit()), + ) + .field( + "filter_ch0_input_io_num", + &format_args!("{}", self.filter_ch0_input_io_num().bits()), + ) + .field( + "filter_ch0_window_thres", + &format_args!("{}", self.filter_ch0_window_thres().bits()), + ) + .field( + "filter_ch0_window_width", + &format_args!("{}", self.filter_ch0_window_width().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Glitch Filter channel enable bit."] + #[inline(always)] + #[must_use] + pub fn filter_ch0_en(&mut self) -> FILTER_CH0_EN_W { + FILTER_CH0_EN_W::new(self, 0) + } + #[doc = "Bits 1:6 - Glitch Filter input io number."] + #[inline(always)] + #[must_use] + pub fn filter_ch0_input_io_num(&mut self) -> FILTER_CH0_INPUT_IO_NUM_W { + FILTER_CH0_INPUT_IO_NUM_W::new(self, 1) + } + #[doc = "Bits 7:12 - Glitch Filter window threshold."] + #[inline(always)] + #[must_use] + pub fn filter_ch0_window_thres(&mut self) -> FILTER_CH0_WINDOW_THRES_W { + FILTER_CH0_WINDOW_THRES_W::new(self, 7) + } + #[doc = "Bits 13:18 - Glitch Filter window width."] + #[inline(always)] + #[must_use] + pub fn filter_ch0_window_width(&mut self) -> FILTER_CH0_WINDOW_WIDTH_W { + FILTER_CH0_WINDOW_WIDTH_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Glitch Filter Configure Register of Channel%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`glitch_filter_ch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`glitch_filter_ch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GLITCH_FILTER_CH_SPEC; +impl crate::RegisterSpec for GLITCH_FILTER_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`glitch_filter_ch::R`](R) reader structure"] +impl crate::Readable for GLITCH_FILTER_CH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`glitch_filter_ch::W`](W) writer structure"] +impl crate::Writable for GLITCH_FILTER_CH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GLITCH_FILTER_CH%s to value 0"] +impl crate::Resettable for GLITCH_FILTER_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/sigmadelta.rs b/esp32p4/src/gpio_sd/sigmadelta.rs new file mode 100644 index 0000000000..407cf9d85d --- /dev/null +++ b/esp32p4/src/gpio_sd/sigmadelta.rs @@ -0,0 +1,82 @@ +#[doc = "Register `SIGMADELTA%s` reader"] +pub type R = crate::R; +#[doc = "Register `SIGMADELTA%s` writer"] +pub type W = crate::W; +#[doc = "Field `SD_IN` reader - This field is used to configure the duty cycle of sigma delta modulation output."] +pub type SD_IN_R = crate::FieldReader; +#[doc = "Field `SD_IN` writer - This field is used to configure the duty cycle of sigma delta modulation output."] +pub type SD_IN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SD_PRESCALE` reader - This field is used to set a divider value to divide APB clock."] +pub type SD_PRESCALE_R = crate::FieldReader; +#[doc = "Field `SD_PRESCALE` writer - This field is used to set a divider value to divide APB clock."] +pub type SD_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."] + #[inline(always)] + pub fn sd_in(&self) -> SD_IN_R { + SD_IN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - This field is used to set a divider value to divide APB clock."] + #[inline(always)] + pub fn sd_prescale(&self) -> SD_PRESCALE_R { + SD_PRESCALE_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SIGMADELTA") + .field("sd_in", &format_args!("{}", self.sd_in().bits())) + .field( + "sd_prescale", + &format_args!("{}", self.sd_prescale().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."] + #[inline(always)] + #[must_use] + pub fn sd_in(&mut self) -> SD_IN_W { + SD_IN_W::new(self, 0) + } + #[doc = "Bits 8:15 - This field is used to set a divider value to divide APB clock."] + #[inline(always)] + #[must_use] + pub fn sd_prescale(&mut self) -> SD_PRESCALE_W { + SD_PRESCALE_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Duty Cycle Configure Register of SDM%s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sigmadelta::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sigmadelta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SIGMADELTA_SPEC; +impl crate::RegisterSpec for SIGMADELTA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sigmadelta::R`](R) reader structure"] +impl crate::Readable for SIGMADELTA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sigmadelta::W`](W) writer structure"] +impl crate::Writable for SIGMADELTA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SIGMADELTA%s to value 0xff00"] +impl crate::Resettable for SIGMADELTA_SPEC { + const RESET_VALUE: Self::Ux = 0xff00; +} diff --git a/esp32p4/src/gpio_sd/sigmadelta_misc.rs b/esp32p4/src/gpio_sd/sigmadelta_misc.rs new file mode 100644 index 0000000000..7502ddf61c --- /dev/null +++ b/esp32p4/src/gpio_sd/sigmadelta_misc.rs @@ -0,0 +1,82 @@ +#[doc = "Register `SIGMADELTA_MISC` reader"] +pub type R = crate::R; +#[doc = "Register `SIGMADELTA_MISC` writer"] +pub type W = crate::W; +#[doc = "Field `FUNCTION_CLK_EN` reader - Clock enable bit of sigma delta modulation."] +pub type FUNCTION_CLK_EN_R = crate::BitReader; +#[doc = "Field `FUNCTION_CLK_EN` writer - Clock enable bit of sigma delta modulation."] +pub type FUNCTION_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SWAP` reader - Reserved."] +pub type SPI_SWAP_R = crate::BitReader; +#[doc = "Field `SPI_SWAP` writer - Reserved."] +pub type SPI_SWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."] + #[inline(always)] + pub fn function_clk_en(&self) -> FUNCTION_CLK_EN_R { + FUNCTION_CLK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved."] + #[inline(always)] + pub fn spi_swap(&self) -> SPI_SWAP_R { + SPI_SWAP_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SIGMADELTA_MISC") + .field( + "function_clk_en", + &format_args!("{}", self.function_clk_en().bit()), + ) + .field("spi_swap", &format_args!("{}", self.spi_swap().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."] + #[inline(always)] + #[must_use] + pub fn function_clk_en(&mut self) -> FUNCTION_CLK_EN_W { + FUNCTION_CLK_EN_W::new(self, 30) + } + #[doc = "Bit 31 - Reserved."] + #[inline(always)] + #[must_use] + pub fn spi_swap(&mut self) -> SPI_SWAP_W { + SPI_SWAP_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MISC Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sigmadelta_misc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sigmadelta_misc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SIGMADELTA_MISC_SPEC; +impl crate::RegisterSpec for SIGMADELTA_MISC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sigmadelta_misc::R`](R) reader structure"] +impl crate::Readable for SIGMADELTA_MISC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sigmadelta_misc::W`](W) writer structure"] +impl crate::Writable for SIGMADELTA_MISC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SIGMADELTA_MISC to value 0"] +impl crate::Resettable for SIGMADELTA_MISC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/gpio_sd/version.rs b/esp32p4/src/gpio_sd/version.rs new file mode 100644 index 0000000000..8b5da02ed1 --- /dev/null +++ b/esp32p4/src/gpio_sd/version.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VERSION` reader"] +pub type R = crate::R; +#[doc = "Register `VERSION` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_SD_DATE` reader - Version control register."] +pub type GPIO_SD_DATE_R = crate::FieldReader; +#[doc = "Field `GPIO_SD_DATE` writer - Version control register."] +pub type GPIO_SD_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Version control register."] + #[inline(always)] + pub fn gpio_sd_date(&self) -> GPIO_SD_DATE_R { + GPIO_SD_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VERSION") + .field( + "gpio_sd_date", + &format_args!("{}", self.gpio_sd_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Version control register."] + #[inline(always)] + #[must_use] + pub fn gpio_sd_date(&mut self) -> GPIO_SD_DATE_W { + GPIO_SD_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VERSION_SPEC; +impl crate::RegisterSpec for VERSION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`version::R`](R) reader structure"] +impl crate::Readable for VERSION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"] +impl crate::Writable for VERSION_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VERSION to value 0x0220_3050"] +impl crate::Resettable for VERSION_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_3050; +} diff --git a/esp32p4/src/h264.rs b/esp32p4/src/h264.rs new file mode 100644 index 0000000000..46dc97bfed --- /dev/null +++ b/esp32p4/src/h264.rs @@ -0,0 +1,620 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + sys_ctrl: SYS_CTRL, + gop_conf: GOP_CONF, + a_sys_mb_res: A_SYS_MB_RES, + a_sys_conf: A_SYS_CONF, + a_deci_score: A_DECI_SCORE, + a_deci_score_offset: A_DECI_SCORE_OFFSET, + a_rc_conf0: A_RC_CONF0, + a_rc_conf1: A_RC_CONF1, + a_db_bypass: A_DB_BYPASS, + a_roi_region0: A_ROI_REGION0, + a_roi_region1: A_ROI_REGION1, + a_roi_region2: A_ROI_REGION2, + a_roi_region3: A_ROI_REGION3, + a_roi_region4: A_ROI_REGION4, + a_roi_region5: A_ROI_REGION5, + a_roi_region6: A_ROI_REGION6, + a_roi_region7: A_ROI_REGION7, + a_roi_region0_3_qp: A_ROI_REGION0_3_QP, + a_roi_region4_7_qp: A_ROI_REGION4_7_QP, + a_no_roi_region_qp_offset: A_NO_ROI_REGION_QP_OFFSET, + a_roi_config: A_ROI_CONFIG, + b_sys_mb_res: B_SYS_MB_RES, + b_sys_conf: B_SYS_CONF, + b_deci_score: B_DECI_SCORE, + b_deci_score_offset: B_DECI_SCORE_OFFSET, + b_rc_conf0: B_RC_CONF0, + b_rc_conf1: B_RC_CONF1, + b_db_bypass: B_DB_BYPASS, + b_roi_region0: B_ROI_REGION0, + b_roi_region1: B_ROI_REGION1, + b_roi_region2: B_ROI_REGION2, + b_roi_region3: B_ROI_REGION3, + b_roi_region4: B_ROI_REGION4, + b_roi_region5: B_ROI_REGION5, + b_roi_region6: B_ROI_REGION6, + b_roi_region7: B_ROI_REGION7, + b_roi_region0_3_qp: B_ROI_REGION0_3_QP, + b_roi_region4_7_qp: B_ROI_REGION4_7_QP, + b_no_roi_region_qp_offset: B_NO_ROI_REGION_QP_OFFSET, + b_roi_config: B_ROI_CONFIG, + rc_status0: RC_STATUS0, + rc_status1: RC_STATUS1, + rc_status2: RC_STATUS2, + slice_header_remain: SLICE_HEADER_REMAIN, + slice_header_byte_length: SLICE_HEADER_BYTE_LENGTH, + bs_threshold: BS_THRESHOLD, + slice_header_byte0: SLICE_HEADER_BYTE0, + slice_header_byte1: SLICE_HEADER_BYTE1, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + conf: CONF, + mv_merge_config: MV_MERGE_CONFIG, + debug_dma_sel: DEBUG_DMA_SEL, + sys_status: SYS_STATUS, + frame_code_length: FRAME_CODE_LENGTH, + debug_info0: DEBUG_INFO0, + debug_info1: DEBUG_INFO1, + debug_info2: DEBUG_INFO2, + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - H264 system level control register."] + #[inline(always)] + pub const fn sys_ctrl(&self) -> &SYS_CTRL { + &self.sys_ctrl + } + #[doc = "0x04 - GOP related configuration register."] + #[inline(always)] + pub const fn gop_conf(&self) -> &GOP_CONF { + &self.gop_conf + } + #[doc = "0x08 - Video A horizontal and vertical MB resolution register."] + #[inline(always)] + pub const fn a_sys_mb_res(&self) -> &A_SYS_MB_RES { + &self.a_sys_mb_res + } + #[doc = "0x0c - Video A system level configuration register."] + #[inline(always)] + pub const fn a_sys_conf(&self) -> &A_SYS_CONF { + &self.a_sys_conf + } + #[doc = "0x10 - Video A luma and chroma MB decimate score Register."] + #[inline(always)] + pub const fn a_deci_score(&self) -> &A_DECI_SCORE { + &self.a_deci_score + } + #[doc = "0x14 - Video A luma and chroma MB decimate score offset Register."] + #[inline(always)] + pub const fn a_deci_score_offset(&self) -> &A_DECI_SCORE_OFFSET { + &self.a_deci_score_offset + } + #[doc = "0x18 - Video A rate control configuration register0."] + #[inline(always)] + pub const fn a_rc_conf0(&self) -> &A_RC_CONF0 { + &self.a_rc_conf0 + } + #[doc = "0x1c - Video A rate control configuration register1."] + #[inline(always)] + pub const fn a_rc_conf1(&self) -> &A_RC_CONF1 { + &self.a_rc_conf1 + } + #[doc = "0x20 - Video A Deblocking bypass register"] + #[inline(always)] + pub const fn a_db_bypass(&self) -> &A_DB_BYPASS { + &self.a_db_bypass + } + #[doc = "0x24 - Video A H264 ROI region0 range configure register."] + #[inline(always)] + pub const fn a_roi_region0(&self) -> &A_ROI_REGION0 { + &self.a_roi_region0 + } + #[doc = "0x28 - Video A H264 ROI region1 range configure register."] + #[inline(always)] + pub const fn a_roi_region1(&self) -> &A_ROI_REGION1 { + &self.a_roi_region1 + } + #[doc = "0x2c - Video A H264 ROI region2 range configure register."] + #[inline(always)] + pub const fn a_roi_region2(&self) -> &A_ROI_REGION2 { + &self.a_roi_region2 + } + #[doc = "0x30 - Video A H264 ROI region3 range configure register."] + #[inline(always)] + pub const fn a_roi_region3(&self) -> &A_ROI_REGION3 { + &self.a_roi_region3 + } + #[doc = "0x34 - Video A H264 ROI region4 range configure register."] + #[inline(always)] + pub const fn a_roi_region4(&self) -> &A_ROI_REGION4 { + &self.a_roi_region4 + } + #[doc = "0x38 - Video A H264 ROI region5 range configure register."] + #[inline(always)] + pub const fn a_roi_region5(&self) -> &A_ROI_REGION5 { + &self.a_roi_region5 + } + #[doc = "0x3c - Video A H264 ROI region6 range configure register."] + #[inline(always)] + pub const fn a_roi_region6(&self) -> &A_ROI_REGION6 { + &self.a_roi_region6 + } + #[doc = "0x40 - Video A H264 ROI region7 range configure register."] + #[inline(always)] + pub const fn a_roi_region7(&self) -> &A_ROI_REGION7 { + &self.a_roi_region7 + } + #[doc = "0x44 - Video A H264 ROI region0, region1,region2,region3 QP register."] + #[inline(always)] + pub const fn a_roi_region0_3_qp(&self) -> &A_ROI_REGION0_3_QP { + &self.a_roi_region0_3_qp + } + #[doc = "0x48 - Video A H264 ROI region4, region5,region6,region7 QP register."] + #[inline(always)] + pub const fn a_roi_region4_7_qp(&self) -> &A_ROI_REGION4_7_QP { + &self.a_roi_region4_7_qp + } + #[doc = "0x4c - Video A H264 no roi region QP register."] + #[inline(always)] + pub const fn a_no_roi_region_qp_offset(&self) -> &A_NO_ROI_REGION_QP_OFFSET { + &self.a_no_roi_region_qp_offset + } + #[doc = "0x50 - Video A H264 ROI configure register."] + #[inline(always)] + pub const fn a_roi_config(&self) -> &A_ROI_CONFIG { + &self.a_roi_config + } + #[doc = "0x54 - Video B horizontal and vertical MB resolution register."] + #[inline(always)] + pub const fn b_sys_mb_res(&self) -> &B_SYS_MB_RES { + &self.b_sys_mb_res + } + #[doc = "0x58 - Video B system level configuration register."] + #[inline(always)] + pub const fn b_sys_conf(&self) -> &B_SYS_CONF { + &self.b_sys_conf + } + #[doc = "0x5c - Video B luma and chroma MB decimate score Register."] + #[inline(always)] + pub const fn b_deci_score(&self) -> &B_DECI_SCORE { + &self.b_deci_score + } + #[doc = "0x60 - Video B luma and chroma MB decimate score offset Register."] + #[inline(always)] + pub const fn b_deci_score_offset(&self) -> &B_DECI_SCORE_OFFSET { + &self.b_deci_score_offset + } + #[doc = "0x64 - Video B rate control configuration register0."] + #[inline(always)] + pub const fn b_rc_conf0(&self) -> &B_RC_CONF0 { + &self.b_rc_conf0 + } + #[doc = "0x68 - Video B rate control configuration register1."] + #[inline(always)] + pub const fn b_rc_conf1(&self) -> &B_RC_CONF1 { + &self.b_rc_conf1 + } + #[doc = "0x6c - Video B Deblocking bypass register"] + #[inline(always)] + pub const fn b_db_bypass(&self) -> &B_DB_BYPASS { + &self.b_db_bypass + } + #[doc = "0x70 - Video B H264 ROI region0 range configure register."] + #[inline(always)] + pub const fn b_roi_region0(&self) -> &B_ROI_REGION0 { + &self.b_roi_region0 + } + #[doc = "0x74 - Video B H264 ROI region1 range configure register."] + #[inline(always)] + pub const fn b_roi_region1(&self) -> &B_ROI_REGION1 { + &self.b_roi_region1 + } + #[doc = "0x78 - Video B H264 ROI region2 range configure register."] + #[inline(always)] + pub const fn b_roi_region2(&self) -> &B_ROI_REGION2 { + &self.b_roi_region2 + } + #[doc = "0x7c - Video B H264 ROI region3 range configure register."] + #[inline(always)] + pub const fn b_roi_region3(&self) -> &B_ROI_REGION3 { + &self.b_roi_region3 + } + #[doc = "0x80 - Video B H264 ROI region4 range configure register."] + #[inline(always)] + pub const fn b_roi_region4(&self) -> &B_ROI_REGION4 { + &self.b_roi_region4 + } + #[doc = "0x84 - Video B H264 ROI region5 range configure register."] + #[inline(always)] + pub const fn b_roi_region5(&self) -> &B_ROI_REGION5 { + &self.b_roi_region5 + } + #[doc = "0x88 - Video B H264 ROI region6 range configure register."] + #[inline(always)] + pub const fn b_roi_region6(&self) -> &B_ROI_REGION6 { + &self.b_roi_region6 + } + #[doc = "0x8c - Video B H264 ROI region7 range configure register."] + #[inline(always)] + pub const fn b_roi_region7(&self) -> &B_ROI_REGION7 { + &self.b_roi_region7 + } + #[doc = "0x90 - Video B H264 ROI region0, region1,region2,region3 QP register."] + #[inline(always)] + pub const fn b_roi_region0_3_qp(&self) -> &B_ROI_REGION0_3_QP { + &self.b_roi_region0_3_qp + } + #[doc = "0x94 - Video B H264 ROI region4, region5,region6,region7 QP register."] + #[inline(always)] + pub const fn b_roi_region4_7_qp(&self) -> &B_ROI_REGION4_7_QP { + &self.b_roi_region4_7_qp + } + #[doc = "0x98 - Video B H264 no roi region QP register."] + #[inline(always)] + pub const fn b_no_roi_region_qp_offset(&self) -> &B_NO_ROI_REGION_QP_OFFSET { + &self.b_no_roi_region_qp_offset + } + #[doc = "0x9c - Video B H264 ROI configure register."] + #[inline(always)] + pub const fn b_roi_config(&self) -> &B_ROI_CONFIG { + &self.b_roi_config + } + #[doc = "0xa0 - Rate control status register0."] + #[inline(always)] + pub const fn rc_status0(&self) -> &RC_STATUS0 { + &self.rc_status0 + } + #[doc = "0xa4 - Rate control status register1."] + #[inline(always)] + pub const fn rc_status1(&self) -> &RC_STATUS1 { + &self.rc_status1 + } + #[doc = "0xa8 - Rate control status register2."] + #[inline(always)] + pub const fn rc_status2(&self) -> &RC_STATUS2 { + &self.rc_status2 + } + #[doc = "0xac - Frame Slice Header remain bit register."] + #[inline(always)] + pub const fn slice_header_remain(&self) -> &SLICE_HEADER_REMAIN { + &self.slice_header_remain + } + #[doc = "0xb0 - Frame Slice Header byte length register."] + #[inline(always)] + pub const fn slice_header_byte_length(&self) -> &SLICE_HEADER_BYTE_LENGTH { + &self.slice_header_byte_length + } + #[doc = "0xb4 - Bitstream buffer overflow threshold register"] + #[inline(always)] + pub const fn bs_threshold(&self) -> &BS_THRESHOLD { + &self.bs_threshold + } + #[doc = "0xb8 - Frame Slice Header byte low 32 bit register."] + #[inline(always)] + pub const fn slice_header_byte0(&self) -> &SLICE_HEADER_BYTE0 { + &self.slice_header_byte0 + } + #[doc = "0xbc - Frame Slice Header byte high 32 bit register."] + #[inline(always)] + pub const fn slice_header_byte1(&self) -> &SLICE_HEADER_BYTE1 { + &self.slice_header_byte1 + } + #[doc = "0xc0 - Interrupt raw status register"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0xc4 - Interrupt masked status register"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0xc8 - Interrupt enable register"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0xcc - Interrupt clear register"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0xd0 - General configuration register."] + #[inline(always)] + pub const fn conf(&self) -> &CONF { + &self.conf + } + #[doc = "0xd4 - Mv merge configuration register."] + #[inline(always)] + pub const fn mv_merge_config(&self) -> &MV_MERGE_CONFIG { + &self.mv_merge_config + } + #[doc = "0xd8 - Debug H264 DMA select register"] + #[inline(always)] + pub const fn debug_dma_sel(&self) -> &DEBUG_DMA_SEL { + &self.debug_dma_sel + } + #[doc = "0xdc - System status register."] + #[inline(always)] + pub const fn sys_status(&self) -> &SYS_STATUS { + &self.sys_status + } + #[doc = "0xe0 - Frame code byte length register."] + #[inline(always)] + pub const fn frame_code_length(&self) -> &FRAME_CODE_LENGTH { + &self.frame_code_length + } + #[doc = "0xe4 - Debug information register0."] + #[inline(always)] + pub const fn debug_info0(&self) -> &DEBUG_INFO0 { + &self.debug_info0 + } + #[doc = "0xe8 - Debug information register1."] + #[inline(always)] + pub const fn debug_info1(&self) -> &DEBUG_INFO1 { + &self.debug_info1 + } + #[doc = "0xec - Debug information register2."] + #[inline(always)] + pub const fn debug_info2(&self) -> &DEBUG_INFO2 { + &self.debug_info2 + } + #[doc = "0xf0 - Version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "SYS_CTRL (rw) register accessor: H264 system level control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_ctrl`] module"] +pub type SYS_CTRL = crate::Reg; +#[doc = "H264 system level control register."] +pub mod sys_ctrl; +#[doc = "GOP_CONF (rw) register accessor: GOP related configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gop_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gop_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gop_conf`] module"] +pub type GOP_CONF = crate::Reg; +#[doc = "GOP related configuration register."] +pub mod gop_conf; +#[doc = "A_SYS_MB_RES (rw) register accessor: Video A horizontal and vertical MB resolution register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_sys_mb_res::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_sys_mb_res::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_sys_mb_res`] module"] +pub type A_SYS_MB_RES = crate::Reg; +#[doc = "Video A horizontal and vertical MB resolution register."] +pub mod a_sys_mb_res; +#[doc = "A_SYS_CONF (rw) register accessor: Video A system level configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_sys_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_sys_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_sys_conf`] module"] +pub type A_SYS_CONF = crate::Reg; +#[doc = "Video A system level configuration register."] +pub mod a_sys_conf; +#[doc = "A_DECI_SCORE (rw) register accessor: Video A luma and chroma MB decimate score Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_deci_score::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_deci_score::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_deci_score`] module"] +pub type A_DECI_SCORE = crate::Reg; +#[doc = "Video A luma and chroma MB decimate score Register."] +pub mod a_deci_score; +#[doc = "A_DECI_SCORE_OFFSET (rw) register accessor: Video A luma and chroma MB decimate score offset Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_deci_score_offset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_deci_score_offset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_deci_score_offset`] module"] +pub type A_DECI_SCORE_OFFSET = crate::Reg; +#[doc = "Video A luma and chroma MB decimate score offset Register."] +pub mod a_deci_score_offset; +#[doc = "A_RC_CONF0 (rw) register accessor: Video A rate control configuration register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_rc_conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_rc_conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_rc_conf0`] module"] +pub type A_RC_CONF0 = crate::Reg; +#[doc = "Video A rate control configuration register0."] +pub mod a_rc_conf0; +#[doc = "A_RC_CONF1 (rw) register accessor: Video A rate control configuration register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_rc_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_rc_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_rc_conf1`] module"] +pub type A_RC_CONF1 = crate::Reg; +#[doc = "Video A rate control configuration register1."] +pub mod a_rc_conf1; +#[doc = "A_DB_BYPASS (rw) register accessor: Video A Deblocking bypass register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_db_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_db_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_db_bypass`] module"] +pub type A_DB_BYPASS = crate::Reg; +#[doc = "Video A Deblocking bypass register"] +pub mod a_db_bypass; +#[doc = "A_ROI_REGION0 (rw) register accessor: Video A H264 ROI region0 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_roi_region0`] module"] +pub type A_ROI_REGION0 = crate::Reg; +#[doc = "Video A H264 ROI region0 range configure register."] +pub mod a_roi_region0; +#[doc = "A_ROI_REGION1 (rw) register accessor: Video A H264 ROI region1 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_roi_region1`] module"] +pub type A_ROI_REGION1 = crate::Reg; +#[doc = "Video A H264 ROI region1 range configure register."] +pub mod a_roi_region1; +#[doc = "A_ROI_REGION2 (rw) register accessor: Video A H264 ROI region2 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_roi_region2`] module"] +pub type A_ROI_REGION2 = crate::Reg; +#[doc = "Video A H264 ROI region2 range configure register."] +pub mod a_roi_region2; +#[doc = "A_ROI_REGION3 (rw) register accessor: Video A H264 ROI region3 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_roi_region3`] module"] +pub type A_ROI_REGION3 = crate::Reg; +#[doc = "Video A H264 ROI region3 range configure register."] +pub mod a_roi_region3; +#[doc = "A_ROI_REGION4 (rw) register accessor: Video A H264 ROI region4 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_roi_region4`] module"] +pub type A_ROI_REGION4 = crate::Reg; +#[doc = "Video A H264 ROI region4 range configure register."] +pub mod a_roi_region4; +#[doc = "A_ROI_REGION5 (rw) register accessor: Video A H264 ROI region5 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_roi_region5`] module"] +pub type A_ROI_REGION5 = crate::Reg; +#[doc = "Video A H264 ROI region5 range configure register."] +pub mod a_roi_region5; +#[doc = "A_ROI_REGION6 (rw) register accessor: Video A H264 ROI region6 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_roi_region6`] module"] +pub type A_ROI_REGION6 = crate::Reg; +#[doc = "Video A H264 ROI region6 range configure register."] +pub mod a_roi_region6; +#[doc = "A_ROI_REGION7 (rw) register accessor: Video A H264 ROI region7 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_roi_region7`] module"] +pub type A_ROI_REGION7 = crate::Reg; +#[doc = "Video A H264 ROI region7 range configure register."] +pub mod a_roi_region7; +#[doc = "A_ROI_REGION0_3_QP (rw) register accessor: Video A H264 ROI region0, region1,region2,region3 QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region0_3_qp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region0_3_qp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_roi_region0_3_qp`] module"] +pub type A_ROI_REGION0_3_QP = crate::Reg; +#[doc = "Video A H264 ROI region0, region1,region2,region3 QP register."] +pub mod a_roi_region0_3_qp; +#[doc = "A_ROI_REGION4_7_QP (rw) register accessor: Video A H264 ROI region4, region5,region6,region7 QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region4_7_qp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region4_7_qp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_roi_region4_7_qp`] module"] +pub type A_ROI_REGION4_7_QP = crate::Reg; +#[doc = "Video A H264 ROI region4, region5,region6,region7 QP register."] +pub mod a_roi_region4_7_qp; +#[doc = "A_NO_ROI_REGION_QP_OFFSET (rw) register accessor: Video A H264 no roi region QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_no_roi_region_qp_offset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_no_roi_region_qp_offset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_no_roi_region_qp_offset`] module"] +pub type A_NO_ROI_REGION_QP_OFFSET = + crate::Reg; +#[doc = "Video A H264 no roi region QP register."] +pub mod a_no_roi_region_qp_offset; +#[doc = "A_ROI_CONFIG (rw) register accessor: Video A H264 ROI configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a_roi_config`] module"] +pub type A_ROI_CONFIG = crate::Reg; +#[doc = "Video A H264 ROI configure register."] +pub mod a_roi_config; +#[doc = "B_SYS_MB_RES (rw) register accessor: Video B horizontal and vertical MB resolution register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_sys_mb_res::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_sys_mb_res::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_sys_mb_res`] module"] +pub type B_SYS_MB_RES = crate::Reg; +#[doc = "Video B horizontal and vertical MB resolution register."] +pub mod b_sys_mb_res; +#[doc = "B_SYS_CONF (rw) register accessor: Video B system level configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_sys_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_sys_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_sys_conf`] module"] +pub type B_SYS_CONF = crate::Reg; +#[doc = "Video B system level configuration register."] +pub mod b_sys_conf; +#[doc = "B_DECI_SCORE (rw) register accessor: Video B luma and chroma MB decimate score Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_deci_score::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_deci_score::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_deci_score`] module"] +pub type B_DECI_SCORE = crate::Reg; +#[doc = "Video B luma and chroma MB decimate score Register."] +pub mod b_deci_score; +#[doc = "B_DECI_SCORE_OFFSET (rw) register accessor: Video B luma and chroma MB decimate score offset Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_deci_score_offset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_deci_score_offset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_deci_score_offset`] module"] +pub type B_DECI_SCORE_OFFSET = crate::Reg; +#[doc = "Video B luma and chroma MB decimate score offset Register."] +pub mod b_deci_score_offset; +#[doc = "B_RC_CONF0 (rw) register accessor: Video B rate control configuration register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_rc_conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_rc_conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_rc_conf0`] module"] +pub type B_RC_CONF0 = crate::Reg; +#[doc = "Video B rate control configuration register0."] +pub mod b_rc_conf0; +#[doc = "B_RC_CONF1 (rw) register accessor: Video B rate control configuration register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_rc_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_rc_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_rc_conf1`] module"] +pub type B_RC_CONF1 = crate::Reg; +#[doc = "Video B rate control configuration register1."] +pub mod b_rc_conf1; +#[doc = "B_DB_BYPASS (rw) register accessor: Video B Deblocking bypass register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_db_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_db_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_db_bypass`] module"] +pub type B_DB_BYPASS = crate::Reg; +#[doc = "Video B Deblocking bypass register"] +pub mod b_db_bypass; +#[doc = "B_ROI_REGION0 (rw) register accessor: Video B H264 ROI region0 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_roi_region0`] module"] +pub type B_ROI_REGION0 = crate::Reg; +#[doc = "Video B H264 ROI region0 range configure register."] +pub mod b_roi_region0; +#[doc = "B_ROI_REGION1 (rw) register accessor: Video B H264 ROI region1 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_roi_region1`] module"] +pub type B_ROI_REGION1 = crate::Reg; +#[doc = "Video B H264 ROI region1 range configure register."] +pub mod b_roi_region1; +#[doc = "B_ROI_REGION2 (rw) register accessor: Video B H264 ROI region2 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_roi_region2`] module"] +pub type B_ROI_REGION2 = crate::Reg; +#[doc = "Video B H264 ROI region2 range configure register."] +pub mod b_roi_region2; +#[doc = "B_ROI_REGION3 (rw) register accessor: Video B H264 ROI region3 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_roi_region3`] module"] +pub type B_ROI_REGION3 = crate::Reg; +#[doc = "Video B H264 ROI region3 range configure register."] +pub mod b_roi_region3; +#[doc = "B_ROI_REGION4 (rw) register accessor: Video B H264 ROI region4 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_roi_region4`] module"] +pub type B_ROI_REGION4 = crate::Reg; +#[doc = "Video B H264 ROI region4 range configure register."] +pub mod b_roi_region4; +#[doc = "B_ROI_REGION5 (rw) register accessor: Video B H264 ROI region5 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_roi_region5`] module"] +pub type B_ROI_REGION5 = crate::Reg; +#[doc = "Video B H264 ROI region5 range configure register."] +pub mod b_roi_region5; +#[doc = "B_ROI_REGION6 (rw) register accessor: Video B H264 ROI region6 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_roi_region6`] module"] +pub type B_ROI_REGION6 = crate::Reg; +#[doc = "Video B H264 ROI region6 range configure register."] +pub mod b_roi_region6; +#[doc = "B_ROI_REGION7 (rw) register accessor: Video B H264 ROI region7 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_roi_region7`] module"] +pub type B_ROI_REGION7 = crate::Reg; +#[doc = "Video B H264 ROI region7 range configure register."] +pub mod b_roi_region7; +#[doc = "B_ROI_REGION0_3_QP (rw) register accessor: Video B H264 ROI region0, region1,region2,region3 QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region0_3_qp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region0_3_qp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_roi_region0_3_qp`] module"] +pub type B_ROI_REGION0_3_QP = crate::Reg; +#[doc = "Video B H264 ROI region0, region1,region2,region3 QP register."] +pub mod b_roi_region0_3_qp; +#[doc = "B_ROI_REGION4_7_QP (rw) register accessor: Video B H264 ROI region4, region5,region6,region7 QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region4_7_qp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region4_7_qp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_roi_region4_7_qp`] module"] +pub type B_ROI_REGION4_7_QP = crate::Reg; +#[doc = "Video B H264 ROI region4, region5,region6,region7 QP register."] +pub mod b_roi_region4_7_qp; +#[doc = "B_NO_ROI_REGION_QP_OFFSET (rw) register accessor: Video B H264 no roi region QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_no_roi_region_qp_offset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_no_roi_region_qp_offset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_no_roi_region_qp_offset`] module"] +pub type B_NO_ROI_REGION_QP_OFFSET = + crate::Reg; +#[doc = "Video B H264 no roi region QP register."] +pub mod b_no_roi_region_qp_offset; +#[doc = "B_ROI_CONFIG (rw) register accessor: Video B H264 ROI configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@b_roi_config`] module"] +pub type B_ROI_CONFIG = crate::Reg; +#[doc = "Video B H264 ROI configure register."] +pub mod b_roi_config; +#[doc = "RC_STATUS0 (r) register accessor: Rate control status register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc_status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rc_status0`] module"] +pub type RC_STATUS0 = crate::Reg; +#[doc = "Rate control status register0."] +pub mod rc_status0; +#[doc = "RC_STATUS1 (r) register accessor: Rate control status register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc_status1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rc_status1`] module"] +pub type RC_STATUS1 = crate::Reg; +#[doc = "Rate control status register1."] +pub mod rc_status1; +#[doc = "RC_STATUS2 (r) register accessor: Rate control status register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc_status2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rc_status2`] module"] +pub type RC_STATUS2 = crate::Reg; +#[doc = "Rate control status register2."] +pub mod rc_status2; +#[doc = "SLICE_HEADER_REMAIN (rw) register accessor: Frame Slice Header remain bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slice_header_remain::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slice_header_remain::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slice_header_remain`] module"] +pub type SLICE_HEADER_REMAIN = crate::Reg; +#[doc = "Frame Slice Header remain bit register."] +pub mod slice_header_remain; +#[doc = "SLICE_HEADER_BYTE_LENGTH (rw) register accessor: Frame Slice Header byte length register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slice_header_byte_length::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slice_header_byte_length::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slice_header_byte_length`] module"] +pub type SLICE_HEADER_BYTE_LENGTH = + crate::Reg; +#[doc = "Frame Slice Header byte length register."] +pub mod slice_header_byte_length; +#[doc = "BS_THRESHOLD (rw) register accessor: Bitstream buffer overflow threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bs_threshold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bs_threshold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bs_threshold`] module"] +pub type BS_THRESHOLD = crate::Reg; +#[doc = "Bitstream buffer overflow threshold register"] +pub mod bs_threshold; +#[doc = "SLICE_HEADER_BYTE0 (rw) register accessor: Frame Slice Header byte low 32 bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slice_header_byte0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slice_header_byte0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slice_header_byte0`] module"] +pub type SLICE_HEADER_BYTE0 = crate::Reg; +#[doc = "Frame Slice Header byte low 32 bit register."] +pub mod slice_header_byte0; +#[doc = "SLICE_HEADER_BYTE1 (rw) register accessor: Frame Slice Header byte high 32 bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slice_header_byte1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slice_header_byte1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slice_header_byte1`] module"] +pub type SLICE_HEADER_BYTE1 = crate::Reg; +#[doc = "Frame Slice Header byte high 32 bit register."] +pub mod slice_header_byte1; +#[doc = "INT_RAW (rw) register accessor: Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Interrupt raw status register"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Interrupt masked status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Interrupt masked status register"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable register"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear register"] +pub mod int_clr; +#[doc = "CONF (rw) register accessor: General configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"] +pub type CONF = crate::Reg; +#[doc = "General configuration register."] +pub mod conf; +#[doc = "MV_MERGE_CONFIG (rw) register accessor: Mv merge configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mv_merge_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mv_merge_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mv_merge_config`] module"] +pub type MV_MERGE_CONFIG = crate::Reg; +#[doc = "Mv merge configuration register."] +pub mod mv_merge_config; +#[doc = "DEBUG_DMA_SEL (rw) register accessor: Debug H264 DMA select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_dma_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug_dma_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_dma_sel`] module"] +pub type DEBUG_DMA_SEL = crate::Reg; +#[doc = "Debug H264 DMA select register"] +pub mod debug_dma_sel; +#[doc = "SYS_STATUS (r) register accessor: System status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_status`] module"] +pub type SYS_STATUS = crate::Reg; +#[doc = "System status register."] +pub mod sys_status; +#[doc = "FRAME_CODE_LENGTH (r) register accessor: Frame code byte length register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frame_code_length::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frame_code_length`] module"] +pub type FRAME_CODE_LENGTH = crate::Reg; +#[doc = "Frame code byte length register."] +pub mod frame_code_length; +#[doc = "DEBUG_INFO0 (r) register accessor: Debug information register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_info0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_info0`] module"] +pub type DEBUG_INFO0 = crate::Reg; +#[doc = "Debug information register0."] +pub mod debug_info0; +#[doc = "DEBUG_INFO1 (r) register accessor: Debug information register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_info1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_info1`] module"] +pub type DEBUG_INFO1 = crate::Reg; +#[doc = "Debug information register1."] +pub mod debug_info1; +#[doc = "DEBUG_INFO2 (r) register accessor: Debug information register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_info2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_info2`] module"] +pub type DEBUG_INFO2 = crate::Reg; +#[doc = "Debug information register2."] +pub mod debug_info2; +#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version control register"] +pub mod date; diff --git a/esp32p4/src/h264/a_db_bypass.rs b/esp32p4/src/h264/a_db_bypass.rs new file mode 100644 index 0000000000..a3d6a84dd1 --- /dev/null +++ b/esp32p4/src/h264/a_db_bypass.rs @@ -0,0 +1,66 @@ +#[doc = "Register `A_DB_BYPASS` reader"] +pub type R = crate::R; +#[doc = "Register `A_DB_BYPASS` writer"] +pub type W = crate::W; +#[doc = "Field `A_BYPASS_DB_FILTER` reader - Configures whether or not to bypass video A deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter"] +pub type A_BYPASS_DB_FILTER_R = crate::BitReader; +#[doc = "Field `A_BYPASS_DB_FILTER` writer - Configures whether or not to bypass video A deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter"] +pub type A_BYPASS_DB_FILTER_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to bypass video A deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter"] + #[inline(always)] + pub fn a_bypass_db_filter(&self) -> A_BYPASS_DB_FILTER_R { + A_BYPASS_DB_FILTER_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_DB_BYPASS") + .field( + "a_bypass_db_filter", + &format_args!("{}", self.a_bypass_db_filter().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to bypass video A deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter"] + #[inline(always)] + #[must_use] + pub fn a_bypass_db_filter(&mut self) -> A_BYPASS_DB_FILTER_W { + A_BYPASS_DB_FILTER_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A Deblocking bypass register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_db_bypass::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_db_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_DB_BYPASS_SPEC; +impl crate::RegisterSpec for A_DB_BYPASS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_db_bypass::R`](R) reader structure"] +impl crate::Readable for A_DB_BYPASS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_db_bypass::W`](W) writer structure"] +impl crate::Writable for A_DB_BYPASS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_DB_BYPASS to value 0"] +impl crate::Resettable for A_DB_BYPASS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_deci_score.rs b/esp32p4/src/h264/a_deci_score.rs new file mode 100644 index 0000000000..3d0d4de25e --- /dev/null +++ b/esp32p4/src/h264/a_deci_score.rs @@ -0,0 +1,85 @@ +#[doc = "Register `A_DECI_SCORE` reader"] +pub type R = crate::R; +#[doc = "Register `A_DECI_SCORE` writer"] +pub type W = crate::W; +#[doc = "Field `A_C_DECI_SCORE` reader - Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable."] +pub type A_C_DECI_SCORE_R = crate::FieldReader; +#[doc = "Field `A_C_DECI_SCORE` writer - Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable."] +pub type A_C_DECI_SCORE_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `A_L_DECI_SCORE` reader - Configures video A luma MB decimate score. When luma score is smaller than it, luma decimate will be enable."] +pub type A_L_DECI_SCORE_R = crate::FieldReader; +#[doc = "Field `A_L_DECI_SCORE` writer - Configures video A luma MB decimate score. When luma score is smaller than it, luma decimate will be enable."] +pub type A_L_DECI_SCORE_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable."] + #[inline(always)] + pub fn a_c_deci_score(&self) -> A_C_DECI_SCORE_R { + A_C_DECI_SCORE_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:19 - Configures video A luma MB decimate score. When luma score is smaller than it, luma decimate will be enable."] + #[inline(always)] + pub fn a_l_deci_score(&self) -> A_L_DECI_SCORE_R { + A_L_DECI_SCORE_R::new(((self.bits >> 10) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_DECI_SCORE") + .field( + "a_c_deci_score", + &format_args!("{}", self.a_c_deci_score().bits()), + ) + .field( + "a_l_deci_score", + &format_args!("{}", self.a_l_deci_score().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable."] + #[inline(always)] + #[must_use] + pub fn a_c_deci_score(&mut self) -> A_C_DECI_SCORE_W { + A_C_DECI_SCORE_W::new(self, 0) + } + #[doc = "Bits 10:19 - Configures video A luma MB decimate score. When luma score is smaller than it, luma decimate will be enable."] + #[inline(always)] + #[must_use] + pub fn a_l_deci_score(&mut self) -> A_L_DECI_SCORE_W { + A_L_DECI_SCORE_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A luma and chroma MB decimate score Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_deci_score::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_deci_score::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_DECI_SCORE_SPEC; +impl crate::RegisterSpec for A_DECI_SCORE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_deci_score::R`](R) reader structure"] +impl crate::Readable for A_DECI_SCORE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_deci_score::W`](W) writer structure"] +impl crate::Writable for A_DECI_SCORE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_DECI_SCORE to value 0"] +impl crate::Resettable for A_DECI_SCORE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_deci_score_offset.rs b/esp32p4/src/h264/a_deci_score_offset.rs new file mode 100644 index 0000000000..f8d257175b --- /dev/null +++ b/esp32p4/src/h264/a_deci_score_offset.rs @@ -0,0 +1,131 @@ +#[doc = "Register `A_DECI_SCORE_OFFSET` reader"] +pub type R = crate::R; +#[doc = "Register `A_DECI_SCORE_OFFSET` writer"] +pub type W = crate::W; +#[doc = "Field `A_I16X16_DECI_SCORE_OFFSET` reader - Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score."] +pub type A_I16X16_DECI_SCORE_OFFSET_R = crate::FieldReader; +#[doc = "Field `A_I16X16_DECI_SCORE_OFFSET` writer - Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score."] +pub type A_I16X16_DECI_SCORE_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `A_I_CHROMA_DECI_SCORE_OFFSET` reader - Configures video A I chroma MB decimate score offset. This offset will be added to I chroma MB score."] +pub type A_I_CHROMA_DECI_SCORE_OFFSET_R = crate::FieldReader; +#[doc = "Field `A_I_CHROMA_DECI_SCORE_OFFSET` writer - Configures video A I chroma MB decimate score offset. This offset will be added to I chroma MB score."] +pub type A_I_CHROMA_DECI_SCORE_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `A_P16X16_DECI_SCORE_OFFSET` reader - Configures video A p16x16 MB decimate score offset. This offset will be added to p16x16 MB score."] +pub type A_P16X16_DECI_SCORE_OFFSET_R = crate::FieldReader; +#[doc = "Field `A_P16X16_DECI_SCORE_OFFSET` writer - Configures video A p16x16 MB decimate score offset. This offset will be added to p16x16 MB score."] +pub type A_P16X16_DECI_SCORE_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `A_P_CHROMA_DECI_SCORE_OFFSET` reader - Configures video A p chroma MB decimate score offset. This offset will be added to p chroma MB score."] +pub type A_P_CHROMA_DECI_SCORE_OFFSET_R = crate::FieldReader; +#[doc = "Field `A_P_CHROMA_DECI_SCORE_OFFSET` writer - Configures video A p chroma MB decimate score offset. This offset will be added to p chroma MB score."] +pub type A_P_CHROMA_DECI_SCORE_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score."] + #[inline(always)] + pub fn a_i16x16_deci_score_offset(&self) -> A_I16X16_DECI_SCORE_OFFSET_R { + A_I16X16_DECI_SCORE_OFFSET_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Configures video A I chroma MB decimate score offset. This offset will be added to I chroma MB score."] + #[inline(always)] + pub fn a_i_chroma_deci_score_offset(&self) -> A_I_CHROMA_DECI_SCORE_OFFSET_R { + A_I_CHROMA_DECI_SCORE_OFFSET_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:17 - Configures video A p16x16 MB decimate score offset. This offset will be added to p16x16 MB score."] + #[inline(always)] + pub fn a_p16x16_deci_score_offset(&self) -> A_P16X16_DECI_SCORE_OFFSET_R { + A_P16X16_DECI_SCORE_OFFSET_R::new(((self.bits >> 12) & 0x3f) as u8) + } + #[doc = "Bits 18:23 - Configures video A p chroma MB decimate score offset. This offset will be added to p chroma MB score."] + #[inline(always)] + pub fn a_p_chroma_deci_score_offset(&self) -> A_P_CHROMA_DECI_SCORE_OFFSET_R { + A_P_CHROMA_DECI_SCORE_OFFSET_R::new(((self.bits >> 18) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_DECI_SCORE_OFFSET") + .field( + "a_i16x16_deci_score_offset", + &format_args!("{}", self.a_i16x16_deci_score_offset().bits()), + ) + .field( + "a_i_chroma_deci_score_offset", + &format_args!("{}", self.a_i_chroma_deci_score_offset().bits()), + ) + .field( + "a_p16x16_deci_score_offset", + &format_args!("{}", self.a_p16x16_deci_score_offset().bits()), + ) + .field( + "a_p_chroma_deci_score_offset", + &format_args!("{}", self.a_p_chroma_deci_score_offset().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score."] + #[inline(always)] + #[must_use] + pub fn a_i16x16_deci_score_offset( + &mut self, + ) -> A_I16X16_DECI_SCORE_OFFSET_W { + A_I16X16_DECI_SCORE_OFFSET_W::new(self, 0) + } + #[doc = "Bits 6:11 - Configures video A I chroma MB decimate score offset. This offset will be added to I chroma MB score."] + #[inline(always)] + #[must_use] + pub fn a_i_chroma_deci_score_offset( + &mut self, + ) -> A_I_CHROMA_DECI_SCORE_OFFSET_W { + A_I_CHROMA_DECI_SCORE_OFFSET_W::new(self, 6) + } + #[doc = "Bits 12:17 - Configures video A p16x16 MB decimate score offset. This offset will be added to p16x16 MB score."] + #[inline(always)] + #[must_use] + pub fn a_p16x16_deci_score_offset( + &mut self, + ) -> A_P16X16_DECI_SCORE_OFFSET_W { + A_P16X16_DECI_SCORE_OFFSET_W::new(self, 12) + } + #[doc = "Bits 18:23 - Configures video A p chroma MB decimate score offset. This offset will be added to p chroma MB score."] + #[inline(always)] + #[must_use] + pub fn a_p_chroma_deci_score_offset( + &mut self, + ) -> A_P_CHROMA_DECI_SCORE_OFFSET_W { + A_P_CHROMA_DECI_SCORE_OFFSET_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A luma and chroma MB decimate score offset Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_deci_score_offset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_deci_score_offset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_DECI_SCORE_OFFSET_SPEC; +impl crate::RegisterSpec for A_DECI_SCORE_OFFSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_deci_score_offset::R`](R) reader structure"] +impl crate::Readable for A_DECI_SCORE_OFFSET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_deci_score_offset::W`](W) writer structure"] +impl crate::Writable for A_DECI_SCORE_OFFSET_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_DECI_SCORE_OFFSET to value 0"] +impl crate::Resettable for A_DECI_SCORE_OFFSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_no_roi_region_qp_offset.rs b/esp32p4/src/h264/a_no_roi_region_qp_offset.rs new file mode 100644 index 0000000000..51de7f1e6e --- /dev/null +++ b/esp32p4/src/h264/a_no_roi_region_qp_offset.rs @@ -0,0 +1,66 @@ +#[doc = "Register `A_NO_ROI_REGION_QP_OFFSET` reader"] +pub type R = crate::R; +#[doc = "Register `A_NO_ROI_REGION_QP_OFFSET` writer"] +pub type W = crate::W; +#[doc = "Field `A_NO_ROI_REGION_QP` reader - Configure H264 no region qp in video A, delta qp."] +pub type A_NO_ROI_REGION_QP_R = crate::FieldReader; +#[doc = "Field `A_NO_ROI_REGION_QP` writer - Configure H264 no region qp in video A, delta qp."] +pub type A_NO_ROI_REGION_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Configure H264 no region qp in video A, delta qp."] + #[inline(always)] + pub fn a_no_roi_region_qp(&self) -> A_NO_ROI_REGION_QP_R { + A_NO_ROI_REGION_QP_R::new((self.bits & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_NO_ROI_REGION_QP_OFFSET") + .field( + "a_no_roi_region_qp", + &format_args!("{}", self.a_no_roi_region_qp().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configure H264 no region qp in video A, delta qp."] + #[inline(always)] + #[must_use] + pub fn a_no_roi_region_qp(&mut self) -> A_NO_ROI_REGION_QP_W { + A_NO_ROI_REGION_QP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 no roi region QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_no_roi_region_qp_offset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_no_roi_region_qp_offset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_NO_ROI_REGION_QP_OFFSET_SPEC; +impl crate::RegisterSpec for A_NO_ROI_REGION_QP_OFFSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_no_roi_region_qp_offset::R`](R) reader structure"] +impl crate::Readable for A_NO_ROI_REGION_QP_OFFSET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_no_roi_region_qp_offset::W`](W) writer structure"] +impl crate::Writable for A_NO_ROI_REGION_QP_OFFSET_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_NO_ROI_REGION_QP_OFFSET to value 0"] +impl crate::Resettable for A_NO_ROI_REGION_QP_OFFSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_rc_conf0.rs b/esp32p4/src/h264/a_rc_conf0.rs new file mode 100644 index 0000000000..3684b94ce8 --- /dev/null +++ b/esp32p4/src/h264/a_rc_conf0.rs @@ -0,0 +1,101 @@ +#[doc = "Register `A_RC_CONF0` reader"] +pub type R = crate::R; +#[doc = "Register `A_RC_CONF0` writer"] +pub type W = crate::W; +#[doc = "Field `A_QP` reader - Configures video A frame level initial luma QP value."] +pub type A_QP_R = crate::FieldReader; +#[doc = "Field `A_QP` writer - Configures video A frame level initial luma QP value."] +pub type A_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `A_RATE_CTRL_U` reader - Configures video A parameter U value. U = int((float) u << 8)."] +pub type A_RATE_CTRL_U_R = crate::FieldReader; +#[doc = "Field `A_RATE_CTRL_U` writer - Configures video A parameter U value. U = int((float) u << 8)."] +pub type A_RATE_CTRL_U_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `A_MB_RATE_CTRL_EN` reader - Configures video A whether or not to open macro block rate ctrl.\\\\1:Open the macro block rate ctrl\\\\1:Close the macro block rate ctrl."] +pub type A_MB_RATE_CTRL_EN_R = crate::BitReader; +#[doc = "Field `A_MB_RATE_CTRL_EN` writer - Configures video A whether or not to open macro block rate ctrl.\\\\1:Open the macro block rate ctrl\\\\1:Close the macro block rate ctrl."] +pub type A_MB_RATE_CTRL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - Configures video A frame level initial luma QP value."] + #[inline(always)] + pub fn a_qp(&self) -> A_QP_R { + A_QP_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:21 - Configures video A parameter U value. U = int((float) u << 8)."] + #[inline(always)] + pub fn a_rate_ctrl_u(&self) -> A_RATE_CTRL_U_R { + A_RATE_CTRL_U_R::new(((self.bits >> 6) & 0xffff) as u16) + } + #[doc = "Bit 22 - Configures video A whether or not to open macro block rate ctrl.\\\\1:Open the macro block rate ctrl\\\\1:Close the macro block rate ctrl."] + #[inline(always)] + pub fn a_mb_rate_ctrl_en(&self) -> A_MB_RATE_CTRL_EN_R { + A_MB_RATE_CTRL_EN_R::new(((self.bits >> 22) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_RC_CONF0") + .field("a_qp", &format_args!("{}", self.a_qp().bits())) + .field( + "a_rate_ctrl_u", + &format_args!("{}", self.a_rate_ctrl_u().bits()), + ) + .field( + "a_mb_rate_ctrl_en", + &format_args!("{}", self.a_mb_rate_ctrl_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - Configures video A frame level initial luma QP value."] + #[inline(always)] + #[must_use] + pub fn a_qp(&mut self) -> A_QP_W { + A_QP_W::new(self, 0) + } + #[doc = "Bits 6:21 - Configures video A parameter U value. U = int((float) u << 8)."] + #[inline(always)] + #[must_use] + pub fn a_rate_ctrl_u(&mut self) -> A_RATE_CTRL_U_W { + A_RATE_CTRL_U_W::new(self, 6) + } + #[doc = "Bit 22 - Configures video A whether or not to open macro block rate ctrl.\\\\1:Open the macro block rate ctrl\\\\1:Close the macro block rate ctrl."] + #[inline(always)] + #[must_use] + pub fn a_mb_rate_ctrl_en(&mut self) -> A_MB_RATE_CTRL_EN_W { + A_MB_RATE_CTRL_EN_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A rate control configuration register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_rc_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_rc_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_RC_CONF0_SPEC; +impl crate::RegisterSpec for A_RC_CONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_rc_conf0::R`](R) reader structure"] +impl crate::Readable for A_RC_CONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_rc_conf0::W`](W) writer structure"] +impl crate::Writable for A_RC_CONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_RC_CONF0 to value 0"] +impl crate::Resettable for A_RC_CONF0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_rc_conf1.rs b/esp32p4/src/h264/a_rc_conf1.rs new file mode 100644 index 0000000000..d9e67c12d2 --- /dev/null +++ b/esp32p4/src/h264/a_rc_conf1.rs @@ -0,0 +1,136 @@ +#[doc = "Register `A_RC_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `A_RC_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `A_CHROMA_DC_QP_DELTA` reader - Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta."] +pub type A_CHROMA_DC_QP_DELTA_R = crate::FieldReader; +#[doc = "Field `A_CHROMA_DC_QP_DELTA` writer - Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta."] +pub type A_CHROMA_DC_QP_DELTA_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `A_CHROMA_QP_DELTA` reader - Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta."] +pub type A_CHROMA_QP_DELTA_R = crate::FieldReader; +#[doc = "Field `A_CHROMA_QP_DELTA` writer - Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta."] +pub type A_CHROMA_QP_DELTA_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `A_QP_MIN` reader - Configures video A allowed luma QP min value."] +pub type A_QP_MIN_R = crate::FieldReader; +#[doc = "Field `A_QP_MIN` writer - Configures video A allowed luma QP min value."] +pub type A_QP_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `A_QP_MAX` reader - Configures video A allowed luma QP max value."] +pub type A_QP_MAX_R = crate::FieldReader; +#[doc = "Field `A_QP_MAX` writer - Configures video A allowed luma QP max value."] +pub type A_QP_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `A_MAD_FRAME_PRED` reader - Configures vdieo A frame level predicted MB MAD value."] +pub type A_MAD_FRAME_PRED_R = crate::FieldReader; +#[doc = "Field `A_MAD_FRAME_PRED` writer - Configures vdieo A frame level predicted MB MAD value."] +pub type A_MAD_FRAME_PRED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:2 - Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta."] + #[inline(always)] + pub fn a_chroma_dc_qp_delta(&self) -> A_CHROMA_DC_QP_DELTA_R { + A_CHROMA_DC_QP_DELTA_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:6 - Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta."] + #[inline(always)] + pub fn a_chroma_qp_delta(&self) -> A_CHROMA_QP_DELTA_R { + A_CHROMA_QP_DELTA_R::new(((self.bits >> 3) & 0x0f) as u8) + } + #[doc = "Bits 7:12 - Configures video A allowed luma QP min value."] + #[inline(always)] + pub fn a_qp_min(&self) -> A_QP_MIN_R { + A_QP_MIN_R::new(((self.bits >> 7) & 0x3f) as u8) + } + #[doc = "Bits 13:18 - Configures video A allowed luma QP max value."] + #[inline(always)] + pub fn a_qp_max(&self) -> A_QP_MAX_R { + A_QP_MAX_R::new(((self.bits >> 13) & 0x3f) as u8) + } + #[doc = "Bits 19:30 - Configures vdieo A frame level predicted MB MAD value."] + #[inline(always)] + pub fn a_mad_frame_pred(&self) -> A_MAD_FRAME_PRED_R { + A_MAD_FRAME_PRED_R::new(((self.bits >> 19) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_RC_CONF1") + .field( + "a_chroma_dc_qp_delta", + &format_args!("{}", self.a_chroma_dc_qp_delta().bits()), + ) + .field( + "a_chroma_qp_delta", + &format_args!("{}", self.a_chroma_qp_delta().bits()), + ) + .field("a_qp_min", &format_args!("{}", self.a_qp_min().bits())) + .field("a_qp_max", &format_args!("{}", self.a_qp_max().bits())) + .field( + "a_mad_frame_pred", + &format_args!("{}", self.a_mad_frame_pred().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta."] + #[inline(always)] + #[must_use] + pub fn a_chroma_dc_qp_delta(&mut self) -> A_CHROMA_DC_QP_DELTA_W { + A_CHROMA_DC_QP_DELTA_W::new(self, 0) + } + #[doc = "Bits 3:6 - Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta."] + #[inline(always)] + #[must_use] + pub fn a_chroma_qp_delta(&mut self) -> A_CHROMA_QP_DELTA_W { + A_CHROMA_QP_DELTA_W::new(self, 3) + } + #[doc = "Bits 7:12 - Configures video A allowed luma QP min value."] + #[inline(always)] + #[must_use] + pub fn a_qp_min(&mut self) -> A_QP_MIN_W { + A_QP_MIN_W::new(self, 7) + } + #[doc = "Bits 13:18 - Configures video A allowed luma QP max value."] + #[inline(always)] + #[must_use] + pub fn a_qp_max(&mut self) -> A_QP_MAX_W { + A_QP_MAX_W::new(self, 13) + } + #[doc = "Bits 19:30 - Configures vdieo A frame level predicted MB MAD value."] + #[inline(always)] + #[must_use] + pub fn a_mad_frame_pred(&mut self) -> A_MAD_FRAME_PRED_W { + A_MAD_FRAME_PRED_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A rate control configuration register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_rc_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_rc_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_RC_CONF1_SPEC; +impl crate::RegisterSpec for A_RC_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_rc_conf1::R`](R) reader structure"] +impl crate::Readable for A_RC_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_rc_conf1::W`](W) writer structure"] +impl crate::Writable for A_RC_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_RC_CONF1 to value 0"] +impl crate::Resettable for A_RC_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_roi_config.rs b/esp32p4/src/h264/a_roi_config.rs new file mode 100644 index 0000000000..9445244a2f --- /dev/null +++ b/esp32p4/src/h264/a_roi_config.rs @@ -0,0 +1,79 @@ +#[doc = "Register `A_ROI_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `A_ROI_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `A_ROI_EN` reader - Configure whether or not to enable ROI in video A.\\\\0:not enable ROI\\\\1:enable ROI."] +pub type A_ROI_EN_R = crate::BitReader; +#[doc = "Field `A_ROI_EN` writer - Configure whether or not to enable ROI in video A.\\\\0:not enable ROI\\\\1:enable ROI."] +pub type A_ROI_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_ROI_MODE` reader - Configure the mode of ROI in video A.\\\\0:fixed qp\\\\1:delta qp."] +pub type A_ROI_MODE_R = crate::BitReader; +#[doc = "Field `A_ROI_MODE` writer - Configure the mode of ROI in video A.\\\\0:fixed qp\\\\1:delta qp."] +pub type A_ROI_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configure whether or not to enable ROI in video A.\\\\0:not enable ROI\\\\1:enable ROI."] + #[inline(always)] + pub fn a_roi_en(&self) -> A_ROI_EN_R { + A_ROI_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configure the mode of ROI in video A.\\\\0:fixed qp\\\\1:delta qp."] + #[inline(always)] + pub fn a_roi_mode(&self) -> A_ROI_MODE_R { + A_ROI_MODE_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_ROI_CONFIG") + .field("a_roi_en", &format_args!("{}", self.a_roi_en().bit())) + .field("a_roi_mode", &format_args!("{}", self.a_roi_mode().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configure whether or not to enable ROI in video A.\\\\0:not enable ROI\\\\1:enable ROI."] + #[inline(always)] + #[must_use] + pub fn a_roi_en(&mut self) -> A_ROI_EN_W { + A_ROI_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configure the mode of ROI in video A.\\\\0:fixed qp\\\\1:delta qp."] + #[inline(always)] + #[must_use] + pub fn a_roi_mode(&mut self) -> A_ROI_MODE_W { + A_ROI_MODE_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 ROI configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_ROI_CONFIG_SPEC; +impl crate::RegisterSpec for A_ROI_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_roi_config::R`](R) reader structure"] +impl crate::Readable for A_ROI_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_roi_config::W`](W) writer structure"] +impl crate::Writable for A_ROI_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_ROI_CONFIG to value 0"] +impl crate::Resettable for A_ROI_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_roi_region0.rs b/esp32p4/src/h264/a_roi_region0.rs new file mode 100644 index 0000000000..dd851047e6 --- /dev/null +++ b/esp32p4/src/h264/a_roi_region0.rs @@ -0,0 +1,127 @@ +#[doc = "Register `A_ROI_REGION0` reader"] +pub type R = crate::R; +#[doc = "Register `A_ROI_REGION0` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 0 in Video A."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 0 in Video A."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 0 in Video A."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 0 in Video A."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 0 in Video A."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 0 in Video A."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 0 in Video A."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 0 in Video A."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video A ROI of region 0 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video A ROI of region 0 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 0 in Video A."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 0 in Video A."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 0 in Video A."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 0 in Video A."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 0 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_ROI_REGION0") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 0 in Video A."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 0 in Video A."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 0 in Video A."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 0 in Video A."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 0 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 ROI region0 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_ROI_REGION0_SPEC; +impl crate::RegisterSpec for A_ROI_REGION0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_roi_region0::R`](R) reader structure"] +impl crate::Readable for A_ROI_REGION0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_roi_region0::W`](W) writer structure"] +impl crate::Writable for A_ROI_REGION0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_ROI_REGION0 to value 0"] +impl crate::Resettable for A_ROI_REGION0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_roi_region0_3_qp.rs b/esp32p4/src/h264/a_roi_region0_3_qp.rs new file mode 100644 index 0000000000..411ec40e90 --- /dev/null +++ b/esp32p4/src/h264/a_roi_region0_3_qp.rs @@ -0,0 +1,123 @@ +#[doc = "Register `A_ROI_REGION0_3_QP` reader"] +pub type R = crate::R; +#[doc = "Register `A_ROI_REGION0_3_QP` writer"] +pub type W = crate::W; +#[doc = "Field `A_ROI_REGION0_QP` reader - Configure H264 ROI region0 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION0_QP_R = crate::FieldReader; +#[doc = "Field `A_ROI_REGION0_QP` writer - Configure H264 ROI region0 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION0_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `A_ROI_REGION1_QP` reader - Configure H264 ROI region1 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION1_QP_R = crate::FieldReader; +#[doc = "Field `A_ROI_REGION1_QP` writer - Configure H264 ROI region1 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION1_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `A_ROI_REGION2_QP` reader - Configure H264 ROI region2 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION2_QP_R = crate::FieldReader; +#[doc = "Field `A_ROI_REGION2_QP` writer - Configure H264 ROI region2 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION2_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `A_ROI_REGION3_QP` reader - Configure H264 ROI region3 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION3_QP_R = crate::FieldReader; +#[doc = "Field `A_ROI_REGION3_QP` writer - Configure H264 ROI region3 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION3_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Configure H264 ROI region0 qp in video A,fixed qp or delta qp."] + #[inline(always)] + pub fn a_roi_region0_qp(&self) -> A_ROI_REGION0_QP_R { + A_ROI_REGION0_QP_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configure H264 ROI region1 qp in video A,fixed qp or delta qp."] + #[inline(always)] + pub fn a_roi_region1_qp(&self) -> A_ROI_REGION1_QP_R { + A_ROI_REGION1_QP_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configure H264 ROI region2 qp in video A,fixed qp or delta qp."] + #[inline(always)] + pub fn a_roi_region2_qp(&self) -> A_ROI_REGION2_QP_R { + A_ROI_REGION2_QP_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configure H264 ROI region3 qp in video A,fixed qp or delta qp."] + #[inline(always)] + pub fn a_roi_region3_qp(&self) -> A_ROI_REGION3_QP_R { + A_ROI_REGION3_QP_R::new(((self.bits >> 21) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_ROI_REGION0_3_QP") + .field( + "a_roi_region0_qp", + &format_args!("{}", self.a_roi_region0_qp().bits()), + ) + .field( + "a_roi_region1_qp", + &format_args!("{}", self.a_roi_region1_qp().bits()), + ) + .field( + "a_roi_region2_qp", + &format_args!("{}", self.a_roi_region2_qp().bits()), + ) + .field( + "a_roi_region3_qp", + &format_args!("{}", self.a_roi_region3_qp().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configure H264 ROI region0 qp in video A,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn a_roi_region0_qp(&mut self) -> A_ROI_REGION0_QP_W { + A_ROI_REGION0_QP_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configure H264 ROI region1 qp in video A,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn a_roi_region1_qp(&mut self) -> A_ROI_REGION1_QP_W { + A_ROI_REGION1_QP_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configure H264 ROI region2 qp in video A,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn a_roi_region2_qp(&mut self) -> A_ROI_REGION2_QP_W { + A_ROI_REGION2_QP_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configure H264 ROI region3 qp in video A,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn a_roi_region3_qp(&mut self) -> A_ROI_REGION3_QP_W { + A_ROI_REGION3_QP_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 ROI region0, region1,region2,region3 QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region0_3_qp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region0_3_qp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_ROI_REGION0_3_QP_SPEC; +impl crate::RegisterSpec for A_ROI_REGION0_3_QP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_roi_region0_3_qp::R`](R) reader structure"] +impl crate::Readable for A_ROI_REGION0_3_QP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_roi_region0_3_qp::W`](W) writer structure"] +impl crate::Writable for A_ROI_REGION0_3_QP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_ROI_REGION0_3_QP to value 0"] +impl crate::Resettable for A_ROI_REGION0_3_QP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_roi_region1.rs b/esp32p4/src/h264/a_roi_region1.rs new file mode 100644 index 0000000000..cd40f41b98 --- /dev/null +++ b/esp32p4/src/h264/a_roi_region1.rs @@ -0,0 +1,127 @@ +#[doc = "Register `A_ROI_REGION1` reader"] +pub type R = crate::R; +#[doc = "Register `A_ROI_REGION1` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 1 in Video A."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 1 in Video A."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 1 in Video A."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 1 in Video A."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 1 in Video A."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 1 in Video A."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 1 in Video A."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 1 in Video A."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video A ROI of region 1 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video A ROI of region 1 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 1 in Video A."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 1 in Video A."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 1 in Video A."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 1 in Video A."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 1 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_ROI_REGION1") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 1 in Video A."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 1 in Video A."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 1 in Video A."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 1 in Video A."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 1 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 ROI region1 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_ROI_REGION1_SPEC; +impl crate::RegisterSpec for A_ROI_REGION1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_roi_region1::R`](R) reader structure"] +impl crate::Readable for A_ROI_REGION1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_roi_region1::W`](W) writer structure"] +impl crate::Writable for A_ROI_REGION1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_ROI_REGION1 to value 0"] +impl crate::Resettable for A_ROI_REGION1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_roi_region2.rs b/esp32p4/src/h264/a_roi_region2.rs new file mode 100644 index 0000000000..4adaee7e27 --- /dev/null +++ b/esp32p4/src/h264/a_roi_region2.rs @@ -0,0 +1,127 @@ +#[doc = "Register `A_ROI_REGION2` reader"] +pub type R = crate::R; +#[doc = "Register `A_ROI_REGION2` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 2 in Video A."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 2 in Video A."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 2 in Video A."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 2 in Video A."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 2 in Video A."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 2 in Video A."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 2 in Video A."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 2 in Video A."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video A ROI of region 2 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video A ROI of region 2 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 2 in Video A."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 2 in Video A."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 2 in Video A."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 2 in Video A."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 2 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_ROI_REGION2") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 2 in Video A."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 2 in Video A."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 2 in Video A."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 2 in Video A."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 2 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 ROI region2 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_ROI_REGION2_SPEC; +impl crate::RegisterSpec for A_ROI_REGION2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_roi_region2::R`](R) reader structure"] +impl crate::Readable for A_ROI_REGION2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_roi_region2::W`](W) writer structure"] +impl crate::Writable for A_ROI_REGION2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_ROI_REGION2 to value 0"] +impl crate::Resettable for A_ROI_REGION2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_roi_region3.rs b/esp32p4/src/h264/a_roi_region3.rs new file mode 100644 index 0000000000..37460ff724 --- /dev/null +++ b/esp32p4/src/h264/a_roi_region3.rs @@ -0,0 +1,127 @@ +#[doc = "Register `A_ROI_REGION3` reader"] +pub type R = crate::R; +#[doc = "Register `A_ROI_REGION3` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 3 in Video A."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 3 in Video A."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 3 in Video A."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 3 in Video A."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 3 in video A."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 3 in video A."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 3 in video A."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 3 in video A."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video A ROI of region 3 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video A ROI of region 3 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 3 in Video A."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 3 in Video A."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 3 in video A."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 3 in video A."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 3 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_ROI_REGION3") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 3 in Video A."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 3 in Video A."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 3 in video A."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 3 in video A."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 3 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 ROI region3 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_ROI_REGION3_SPEC; +impl crate::RegisterSpec for A_ROI_REGION3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_roi_region3::R`](R) reader structure"] +impl crate::Readable for A_ROI_REGION3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_roi_region3::W`](W) writer structure"] +impl crate::Writable for A_ROI_REGION3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_ROI_REGION3 to value 0"] +impl crate::Resettable for A_ROI_REGION3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_roi_region4.rs b/esp32p4/src/h264/a_roi_region4.rs new file mode 100644 index 0000000000..3dd4fdd60c --- /dev/null +++ b/esp32p4/src/h264/a_roi_region4.rs @@ -0,0 +1,127 @@ +#[doc = "Register `A_ROI_REGION4` reader"] +pub type R = crate::R; +#[doc = "Register `A_ROI_REGION4` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 4 in Video A."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 4 in Video A."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 4 in Video A."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 4 in Video A."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 4 in video A."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 4 in video A."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 4 in video A."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 4 in video A."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video A ROI of region 4 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video A ROI of region 4 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 4 in Video A."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 4 in Video A."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 4 in video A."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 4 in video A."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 4 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_ROI_REGION4") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 4 in Video A."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 4 in Video A."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 4 in video A."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 4 in video A."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 4 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 ROI region4 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_ROI_REGION4_SPEC; +impl crate::RegisterSpec for A_ROI_REGION4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_roi_region4::R`](R) reader structure"] +impl crate::Readable for A_ROI_REGION4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_roi_region4::W`](W) writer structure"] +impl crate::Writable for A_ROI_REGION4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_ROI_REGION4 to value 0"] +impl crate::Resettable for A_ROI_REGION4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_roi_region4_7_qp.rs b/esp32p4/src/h264/a_roi_region4_7_qp.rs new file mode 100644 index 0000000000..f8f1f5c0e3 --- /dev/null +++ b/esp32p4/src/h264/a_roi_region4_7_qp.rs @@ -0,0 +1,123 @@ +#[doc = "Register `A_ROI_REGION4_7_QP` reader"] +pub type R = crate::R; +#[doc = "Register `A_ROI_REGION4_7_QP` writer"] +pub type W = crate::W; +#[doc = "Field `A_ROI_REGION4_QP` reader - Configure H264 ROI region4 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION4_QP_R = crate::FieldReader; +#[doc = "Field `A_ROI_REGION4_QP` writer - Configure H264 ROI region4 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION4_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `A_ROI_REGION5_QP` reader - Configure H264 ROI region5 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION5_QP_R = crate::FieldReader; +#[doc = "Field `A_ROI_REGION5_QP` writer - Configure H264 ROI region5 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION5_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `A_ROI_REGION6_QP` reader - Configure H264 ROI region6 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION6_QP_R = crate::FieldReader; +#[doc = "Field `A_ROI_REGION6_QP` writer - Configure H264 ROI region6 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION6_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `A_ROI_REGION7_QP` reader - Configure H264 ROI region7 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION7_QP_R = crate::FieldReader; +#[doc = "Field `A_ROI_REGION7_QP` writer - Configure H264 ROI region7 qp in video A,fixed qp or delta qp."] +pub type A_ROI_REGION7_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Configure H264 ROI region4 qp in video A,fixed qp or delta qp."] + #[inline(always)] + pub fn a_roi_region4_qp(&self) -> A_ROI_REGION4_QP_R { + A_ROI_REGION4_QP_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configure H264 ROI region5 qp in video A,fixed qp or delta qp."] + #[inline(always)] + pub fn a_roi_region5_qp(&self) -> A_ROI_REGION5_QP_R { + A_ROI_REGION5_QP_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configure H264 ROI region6 qp in video A,fixed qp or delta qp."] + #[inline(always)] + pub fn a_roi_region6_qp(&self) -> A_ROI_REGION6_QP_R { + A_ROI_REGION6_QP_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configure H264 ROI region7 qp in video A,fixed qp or delta qp."] + #[inline(always)] + pub fn a_roi_region7_qp(&self) -> A_ROI_REGION7_QP_R { + A_ROI_REGION7_QP_R::new(((self.bits >> 21) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_ROI_REGION4_7_QP") + .field( + "a_roi_region4_qp", + &format_args!("{}", self.a_roi_region4_qp().bits()), + ) + .field( + "a_roi_region5_qp", + &format_args!("{}", self.a_roi_region5_qp().bits()), + ) + .field( + "a_roi_region6_qp", + &format_args!("{}", self.a_roi_region6_qp().bits()), + ) + .field( + "a_roi_region7_qp", + &format_args!("{}", self.a_roi_region7_qp().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configure H264 ROI region4 qp in video A,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn a_roi_region4_qp(&mut self) -> A_ROI_REGION4_QP_W { + A_ROI_REGION4_QP_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configure H264 ROI region5 qp in video A,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn a_roi_region5_qp(&mut self) -> A_ROI_REGION5_QP_W { + A_ROI_REGION5_QP_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configure H264 ROI region6 qp in video A,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn a_roi_region6_qp(&mut self) -> A_ROI_REGION6_QP_W { + A_ROI_REGION6_QP_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configure H264 ROI region7 qp in video A,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn a_roi_region7_qp(&mut self) -> A_ROI_REGION7_QP_W { + A_ROI_REGION7_QP_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 ROI region4, region5,region6,region7 QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region4_7_qp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region4_7_qp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_ROI_REGION4_7_QP_SPEC; +impl crate::RegisterSpec for A_ROI_REGION4_7_QP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_roi_region4_7_qp::R`](R) reader structure"] +impl crate::Readable for A_ROI_REGION4_7_QP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_roi_region4_7_qp::W`](W) writer structure"] +impl crate::Writable for A_ROI_REGION4_7_QP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_ROI_REGION4_7_QP to value 0"] +impl crate::Resettable for A_ROI_REGION4_7_QP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_roi_region5.rs b/esp32p4/src/h264/a_roi_region5.rs new file mode 100644 index 0000000000..80dcad5b89 --- /dev/null +++ b/esp32p4/src/h264/a_roi_region5.rs @@ -0,0 +1,127 @@ +#[doc = "Register `A_ROI_REGION5` reader"] +pub type R = crate::R; +#[doc = "Register `A_ROI_REGION5` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontial start macroblocks of region 5 video A."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontial start macroblocks of region 5 video A."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 5 video A."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 5 video A."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 5 video A."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 5 video A."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 5 in video A."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 5 in video A."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video A ROI of region 5 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video A ROI of region 5 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 5 video A."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 5 video A."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 5 video A."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 5 in video A."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 5 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_ROI_REGION5") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 5 video A."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 5 video A."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 5 video A."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 5 in video A."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 5 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 ROI region5 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_ROI_REGION5_SPEC; +impl crate::RegisterSpec for A_ROI_REGION5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_roi_region5::R`](R) reader structure"] +impl crate::Readable for A_ROI_REGION5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_roi_region5::W`](W) writer structure"] +impl crate::Writable for A_ROI_REGION5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_ROI_REGION5 to value 0"] +impl crate::Resettable for A_ROI_REGION5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_roi_region6.rs b/esp32p4/src/h264/a_roi_region6.rs new file mode 100644 index 0000000000..a47b2f85f6 --- /dev/null +++ b/esp32p4/src/h264/a_roi_region6.rs @@ -0,0 +1,127 @@ +#[doc = "Register `A_ROI_REGION6` reader"] +pub type R = crate::R; +#[doc = "Register `A_ROI_REGION6` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontial start macroblocks of region 6 video A."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontial start macroblocks of region 6 video A."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 6 in video A."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 6 in video A."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 6 in video A."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 6 in video A."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 6 in video A."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 6 in video A."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video A ROI of region 6 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video A ROI of region 6 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 6 video A."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 6 in video A."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 6 in video A."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 6 in video A."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 6 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_ROI_REGION6") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 6 video A."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 6 in video A."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 6 in video A."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 6 in video A."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 6 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 ROI region6 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_ROI_REGION6_SPEC; +impl crate::RegisterSpec for A_ROI_REGION6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_roi_region6::R`](R) reader structure"] +impl crate::Readable for A_ROI_REGION6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_roi_region6::W`](W) writer structure"] +impl crate::Writable for A_ROI_REGION6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_ROI_REGION6 to value 0"] +impl crate::Resettable for A_ROI_REGION6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_roi_region7.rs b/esp32p4/src/h264/a_roi_region7.rs new file mode 100644 index 0000000000..36719bb84e --- /dev/null +++ b/esp32p4/src/h264/a_roi_region7.rs @@ -0,0 +1,127 @@ +#[doc = "Register `A_ROI_REGION7` reader"] +pub type R = crate::R; +#[doc = "Register `A_ROI_REGION7` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 7 in video A."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 7 in video A."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 7 in video A."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 7 in video A."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 7 in video A."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 7 in video A."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 7 in video A."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 7 in video A."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video A ROI of region 7 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video A ROI of region 7 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 7 in video A."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 7 in video A."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 7 in video A."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 7 in video A."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 7 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_ROI_REGION7") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 7 in video A."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 7 in video A."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 7 in video A."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 7 in video A."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video A ROI of region 7 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A H264 ROI region7 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_roi_region7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_roi_region7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_ROI_REGION7_SPEC; +impl crate::RegisterSpec for A_ROI_REGION7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_roi_region7::R`](R) reader structure"] +impl crate::Readable for A_ROI_REGION7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_roi_region7::W`](W) writer structure"] +impl crate::Writable for A_ROI_REGION7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_ROI_REGION7 to value 0"] +impl crate::Resettable for A_ROI_REGION7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/a_sys_conf.rs b/esp32p4/src/h264/a_sys_conf.rs new file mode 100644 index 0000000000..78a22d3c2d --- /dev/null +++ b/esp32p4/src/h264/a_sys_conf.rs @@ -0,0 +1,108 @@ +#[doc = "Register `A_SYS_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `A_SYS_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `A_DB_TMP_READY_TRIGGER_MB_NUM` reader - Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3."] +pub type A_DB_TMP_READY_TRIGGER_MB_NUM_R = crate::FieldReader; +#[doc = "Field `A_DB_TMP_READY_TRIGGER_MB_NUM` writer - Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3."] +pub type A_DB_TMP_READY_TRIGGER_MB_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `A_REC_READY_TRIGGER_MB_LINES` reader - Configures when to trigger video A H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4."] +pub type A_REC_READY_TRIGGER_MB_LINES_R = crate::FieldReader; +#[doc = "Field `A_REC_READY_TRIGGER_MB_LINES` writer - Configures when to trigger video A H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4."] +pub type A_REC_READY_TRIGGER_MB_LINES_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `A_INTRA_COST_CMP_OFFSET` reader - Configures video A intra cost offset when I MB compared with P MB."] +pub type A_INTRA_COST_CMP_OFFSET_R = crate::FieldReader; +#[doc = "Field `A_INTRA_COST_CMP_OFFSET` writer - Configures video A intra cost offset when I MB compared with P MB."] +pub type A_INTRA_COST_CMP_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:6 - Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3."] + #[inline(always)] + pub fn a_db_tmp_ready_trigger_mb_num(&self) -> A_DB_TMP_READY_TRIGGER_MB_NUM_R { + A_DB_TMP_READY_TRIGGER_MB_NUM_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures when to trigger video A H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4."] + #[inline(always)] + pub fn a_rec_ready_trigger_mb_lines(&self) -> A_REC_READY_TRIGGER_MB_LINES_R { + A_REC_READY_TRIGGER_MB_LINES_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:29 - Configures video A intra cost offset when I MB compared with P MB."] + #[inline(always)] + pub fn a_intra_cost_cmp_offset(&self) -> A_INTRA_COST_CMP_OFFSET_R { + A_INTRA_COST_CMP_OFFSET_R::new(((self.bits >> 14) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_SYS_CONF") + .field( + "a_db_tmp_ready_trigger_mb_num", + &format_args!("{}", self.a_db_tmp_ready_trigger_mb_num().bits()), + ) + .field( + "a_rec_ready_trigger_mb_lines", + &format_args!("{}", self.a_rec_ready_trigger_mb_lines().bits()), + ) + .field( + "a_intra_cost_cmp_offset", + &format_args!("{}", self.a_intra_cost_cmp_offset().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3."] + #[inline(always)] + #[must_use] + pub fn a_db_tmp_ready_trigger_mb_num( + &mut self, + ) -> A_DB_TMP_READY_TRIGGER_MB_NUM_W { + A_DB_TMP_READY_TRIGGER_MB_NUM_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures when to trigger video A H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4."] + #[inline(always)] + #[must_use] + pub fn a_rec_ready_trigger_mb_lines( + &mut self, + ) -> A_REC_READY_TRIGGER_MB_LINES_W { + A_REC_READY_TRIGGER_MB_LINES_W::new(self, 7) + } + #[doc = "Bits 14:29 - Configures video A intra cost offset when I MB compared with P MB."] + #[inline(always)] + #[must_use] + pub fn a_intra_cost_cmp_offset(&mut self) -> A_INTRA_COST_CMP_OFFSET_W { + A_INTRA_COST_CMP_OFFSET_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A system level configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_sys_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_sys_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_SYS_CONF_SPEC; +impl crate::RegisterSpec for A_SYS_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_sys_conf::R`](R) reader structure"] +impl crate::Readable for A_SYS_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_sys_conf::W`](W) writer structure"] +impl crate::Writable for A_SYS_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_SYS_CONF to value 0x0203"] +impl crate::Resettable for A_SYS_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0203; +} diff --git a/esp32p4/src/h264/a_sys_mb_res.rs b/esp32p4/src/h264/a_sys_mb_res.rs new file mode 100644 index 0000000000..5f9a161fba --- /dev/null +++ b/esp32p4/src/h264/a_sys_mb_res.rs @@ -0,0 +1,85 @@ +#[doc = "Register `A_SYS_MB_RES` reader"] +pub type R = crate::R; +#[doc = "Register `A_SYS_MB_RES` writer"] +pub type W = crate::W; +#[doc = "Field `A_SYS_TOTAL_MB_Y` reader - Configures video A vertical MB resolution."] +pub type A_SYS_TOTAL_MB_Y_R = crate::FieldReader; +#[doc = "Field `A_SYS_TOTAL_MB_Y` writer - Configures video A vertical MB resolution."] +pub type A_SYS_TOTAL_MB_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `A_SYS_TOTAL_MB_X` reader - Configures video A horizontal MB resolution."] +pub type A_SYS_TOTAL_MB_X_R = crate::FieldReader; +#[doc = "Field `A_SYS_TOTAL_MB_X` writer - Configures video A horizontal MB resolution."] +pub type A_SYS_TOTAL_MB_X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Configures video A vertical MB resolution."] + #[inline(always)] + pub fn a_sys_total_mb_y(&self) -> A_SYS_TOTAL_MB_Y_R { + A_SYS_TOTAL_MB_Y_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures video A horizontal MB resolution."] + #[inline(always)] + pub fn a_sys_total_mb_x(&self) -> A_SYS_TOTAL_MB_X_R { + A_SYS_TOTAL_MB_X_R::new(((self.bits >> 7) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("A_SYS_MB_RES") + .field( + "a_sys_total_mb_y", + &format_args!("{}", self.a_sys_total_mb_y().bits()), + ) + .field( + "a_sys_total_mb_x", + &format_args!("{}", self.a_sys_total_mb_x().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures video A vertical MB resolution."] + #[inline(always)] + #[must_use] + pub fn a_sys_total_mb_y(&mut self) -> A_SYS_TOTAL_MB_Y_W { + A_SYS_TOTAL_MB_Y_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures video A horizontal MB resolution."] + #[inline(always)] + #[must_use] + pub fn a_sys_total_mb_x(&mut self) -> A_SYS_TOTAL_MB_X_W { + A_SYS_TOTAL_MB_X_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video A horizontal and vertical MB resolution register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a_sys_mb_res::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a_sys_mb_res::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct A_SYS_MB_RES_SPEC; +impl crate::RegisterSpec for A_SYS_MB_RES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`a_sys_mb_res::R`](R) reader structure"] +impl crate::Readable for A_SYS_MB_RES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`a_sys_mb_res::W`](W) writer structure"] +impl crate::Writable for A_SYS_MB_RES_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets A_SYS_MB_RES to value 0"] +impl crate::Resettable for A_SYS_MB_RES_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_db_bypass.rs b/esp32p4/src/h264/b_db_bypass.rs new file mode 100644 index 0000000000..d03f1c7c23 --- /dev/null +++ b/esp32p4/src/h264/b_db_bypass.rs @@ -0,0 +1,66 @@ +#[doc = "Register `B_DB_BYPASS` reader"] +pub type R = crate::R; +#[doc = "Register `B_DB_BYPASS` writer"] +pub type W = crate::W; +#[doc = "Field `B_BYPASS_DB_FILTER` reader - Configures whether or not to bypass video B deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter"] +pub type B_BYPASS_DB_FILTER_R = crate::BitReader; +#[doc = "Field `B_BYPASS_DB_FILTER` writer - Configures whether or not to bypass video B deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter"] +pub type B_BYPASS_DB_FILTER_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to bypass video B deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter"] + #[inline(always)] + pub fn b_bypass_db_filter(&self) -> B_BYPASS_DB_FILTER_R { + B_BYPASS_DB_FILTER_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_DB_BYPASS") + .field( + "b_bypass_db_filter", + &format_args!("{}", self.b_bypass_db_filter().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to bypass video B deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter"] + #[inline(always)] + #[must_use] + pub fn b_bypass_db_filter(&mut self) -> B_BYPASS_DB_FILTER_W { + B_BYPASS_DB_FILTER_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B Deblocking bypass register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_db_bypass::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_db_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_DB_BYPASS_SPEC; +impl crate::RegisterSpec for B_DB_BYPASS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_db_bypass::R`](R) reader structure"] +impl crate::Readable for B_DB_BYPASS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_db_bypass::W`](W) writer structure"] +impl crate::Writable for B_DB_BYPASS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_DB_BYPASS to value 0"] +impl crate::Resettable for B_DB_BYPASS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_deci_score.rs b/esp32p4/src/h264/b_deci_score.rs new file mode 100644 index 0000000000..5722d0aa37 --- /dev/null +++ b/esp32p4/src/h264/b_deci_score.rs @@ -0,0 +1,85 @@ +#[doc = "Register `B_DECI_SCORE` reader"] +pub type R = crate::R; +#[doc = "Register `B_DECI_SCORE` writer"] +pub type W = crate::W; +#[doc = "Field `B_C_DECI_SCORE` reader - Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable."] +pub type B_C_DECI_SCORE_R = crate::FieldReader; +#[doc = "Field `B_C_DECI_SCORE` writer - Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable."] +pub type B_C_DECI_SCORE_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `B_L_DECI_SCORE` reader - Configures video B luma MB decimate score. When luma score is smaller than it, luma decimate will be enable."] +pub type B_L_DECI_SCORE_R = crate::FieldReader; +#[doc = "Field `B_L_DECI_SCORE` writer - Configures video B luma MB decimate score. When luma score is smaller than it, luma decimate will be enable."] +pub type B_L_DECI_SCORE_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable."] + #[inline(always)] + pub fn b_c_deci_score(&self) -> B_C_DECI_SCORE_R { + B_C_DECI_SCORE_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:19 - Configures video B luma MB decimate score. When luma score is smaller than it, luma decimate will be enable."] + #[inline(always)] + pub fn b_l_deci_score(&self) -> B_L_DECI_SCORE_R { + B_L_DECI_SCORE_R::new(((self.bits >> 10) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_DECI_SCORE") + .field( + "b_c_deci_score", + &format_args!("{}", self.b_c_deci_score().bits()), + ) + .field( + "b_l_deci_score", + &format_args!("{}", self.b_l_deci_score().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable."] + #[inline(always)] + #[must_use] + pub fn b_c_deci_score(&mut self) -> B_C_DECI_SCORE_W { + B_C_DECI_SCORE_W::new(self, 0) + } + #[doc = "Bits 10:19 - Configures video B luma MB decimate score. When luma score is smaller than it, luma decimate will be enable."] + #[inline(always)] + #[must_use] + pub fn b_l_deci_score(&mut self) -> B_L_DECI_SCORE_W { + B_L_DECI_SCORE_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B luma and chroma MB decimate score Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_deci_score::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_deci_score::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_DECI_SCORE_SPEC; +impl crate::RegisterSpec for B_DECI_SCORE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_deci_score::R`](R) reader structure"] +impl crate::Readable for B_DECI_SCORE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_deci_score::W`](W) writer structure"] +impl crate::Writable for B_DECI_SCORE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_DECI_SCORE to value 0"] +impl crate::Resettable for B_DECI_SCORE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_deci_score_offset.rs b/esp32p4/src/h264/b_deci_score_offset.rs new file mode 100644 index 0000000000..8eb69f4ef4 --- /dev/null +++ b/esp32p4/src/h264/b_deci_score_offset.rs @@ -0,0 +1,131 @@ +#[doc = "Register `B_DECI_SCORE_OFFSET` reader"] +pub type R = crate::R; +#[doc = "Register `B_DECI_SCORE_OFFSET` writer"] +pub type W = crate::W; +#[doc = "Field `B_I16X16_DECI_SCORE_OFFSET` reader - Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score."] +pub type B_I16X16_DECI_SCORE_OFFSET_R = crate::FieldReader; +#[doc = "Field `B_I16X16_DECI_SCORE_OFFSET` writer - Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score."] +pub type B_I16X16_DECI_SCORE_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `B_I_CHROMA_DECI_SCORE_OFFSET` reader - Configures video B I chroma MB decimate score offset. This offset will be added to I chroma MB score."] +pub type B_I_CHROMA_DECI_SCORE_OFFSET_R = crate::FieldReader; +#[doc = "Field `B_I_CHROMA_DECI_SCORE_OFFSET` writer - Configures video B I chroma MB decimate score offset. This offset will be added to I chroma MB score."] +pub type B_I_CHROMA_DECI_SCORE_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `B_P16X16_DECI_SCORE_OFFSET` reader - Configures video B p16x16 MB decimate score offset. This offset will be added to p16x16 MB score."] +pub type B_P16X16_DECI_SCORE_OFFSET_R = crate::FieldReader; +#[doc = "Field `B_P16X16_DECI_SCORE_OFFSET` writer - Configures video B p16x16 MB decimate score offset. This offset will be added to p16x16 MB score."] +pub type B_P16X16_DECI_SCORE_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `B_P_CHROMA_DECI_SCORE_OFFSET` reader - Configures video B p chroma MB decimate score offset. This offset will be added to p chroma MB score."] +pub type B_P_CHROMA_DECI_SCORE_OFFSET_R = crate::FieldReader; +#[doc = "Field `B_P_CHROMA_DECI_SCORE_OFFSET` writer - Configures video B p chroma MB decimate score offset. This offset will be added to p chroma MB score."] +pub type B_P_CHROMA_DECI_SCORE_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score."] + #[inline(always)] + pub fn b_i16x16_deci_score_offset(&self) -> B_I16X16_DECI_SCORE_OFFSET_R { + B_I16X16_DECI_SCORE_OFFSET_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Configures video B I chroma MB decimate score offset. This offset will be added to I chroma MB score."] + #[inline(always)] + pub fn b_i_chroma_deci_score_offset(&self) -> B_I_CHROMA_DECI_SCORE_OFFSET_R { + B_I_CHROMA_DECI_SCORE_OFFSET_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:17 - Configures video B p16x16 MB decimate score offset. This offset will be added to p16x16 MB score."] + #[inline(always)] + pub fn b_p16x16_deci_score_offset(&self) -> B_P16X16_DECI_SCORE_OFFSET_R { + B_P16X16_DECI_SCORE_OFFSET_R::new(((self.bits >> 12) & 0x3f) as u8) + } + #[doc = "Bits 18:23 - Configures video B p chroma MB decimate score offset. This offset will be added to p chroma MB score."] + #[inline(always)] + pub fn b_p_chroma_deci_score_offset(&self) -> B_P_CHROMA_DECI_SCORE_OFFSET_R { + B_P_CHROMA_DECI_SCORE_OFFSET_R::new(((self.bits >> 18) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_DECI_SCORE_OFFSET") + .field( + "b_i16x16_deci_score_offset", + &format_args!("{}", self.b_i16x16_deci_score_offset().bits()), + ) + .field( + "b_i_chroma_deci_score_offset", + &format_args!("{}", self.b_i_chroma_deci_score_offset().bits()), + ) + .field( + "b_p16x16_deci_score_offset", + &format_args!("{}", self.b_p16x16_deci_score_offset().bits()), + ) + .field( + "b_p_chroma_deci_score_offset", + &format_args!("{}", self.b_p_chroma_deci_score_offset().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score."] + #[inline(always)] + #[must_use] + pub fn b_i16x16_deci_score_offset( + &mut self, + ) -> B_I16X16_DECI_SCORE_OFFSET_W { + B_I16X16_DECI_SCORE_OFFSET_W::new(self, 0) + } + #[doc = "Bits 6:11 - Configures video B I chroma MB decimate score offset. This offset will be added to I chroma MB score."] + #[inline(always)] + #[must_use] + pub fn b_i_chroma_deci_score_offset( + &mut self, + ) -> B_I_CHROMA_DECI_SCORE_OFFSET_W { + B_I_CHROMA_DECI_SCORE_OFFSET_W::new(self, 6) + } + #[doc = "Bits 12:17 - Configures video B p16x16 MB decimate score offset. This offset will be added to p16x16 MB score."] + #[inline(always)] + #[must_use] + pub fn b_p16x16_deci_score_offset( + &mut self, + ) -> B_P16X16_DECI_SCORE_OFFSET_W { + B_P16X16_DECI_SCORE_OFFSET_W::new(self, 12) + } + #[doc = "Bits 18:23 - Configures video B p chroma MB decimate score offset. This offset will be added to p chroma MB score."] + #[inline(always)] + #[must_use] + pub fn b_p_chroma_deci_score_offset( + &mut self, + ) -> B_P_CHROMA_DECI_SCORE_OFFSET_W { + B_P_CHROMA_DECI_SCORE_OFFSET_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B luma and chroma MB decimate score offset Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_deci_score_offset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_deci_score_offset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_DECI_SCORE_OFFSET_SPEC; +impl crate::RegisterSpec for B_DECI_SCORE_OFFSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_deci_score_offset::R`](R) reader structure"] +impl crate::Readable for B_DECI_SCORE_OFFSET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_deci_score_offset::W`](W) writer structure"] +impl crate::Writable for B_DECI_SCORE_OFFSET_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_DECI_SCORE_OFFSET to value 0"] +impl crate::Resettable for B_DECI_SCORE_OFFSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_no_roi_region_qp_offset.rs b/esp32p4/src/h264/b_no_roi_region_qp_offset.rs new file mode 100644 index 0000000000..2c1476ba16 --- /dev/null +++ b/esp32p4/src/h264/b_no_roi_region_qp_offset.rs @@ -0,0 +1,66 @@ +#[doc = "Register `B_NO_ROI_REGION_QP_OFFSET` reader"] +pub type R = crate::R; +#[doc = "Register `B_NO_ROI_REGION_QP_OFFSET` writer"] +pub type W = crate::W; +#[doc = "Field `B_NO_ROI_REGION_QP` reader - Configure H264 no region qp in video B, delta qp."] +pub type B_NO_ROI_REGION_QP_R = crate::FieldReader; +#[doc = "Field `B_NO_ROI_REGION_QP` writer - Configure H264 no region qp in video B, delta qp."] +pub type B_NO_ROI_REGION_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Configure H264 no region qp in video B, delta qp."] + #[inline(always)] + pub fn b_no_roi_region_qp(&self) -> B_NO_ROI_REGION_QP_R { + B_NO_ROI_REGION_QP_R::new((self.bits & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_NO_ROI_REGION_QP_OFFSET") + .field( + "b_no_roi_region_qp", + &format_args!("{}", self.b_no_roi_region_qp().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configure H264 no region qp in video B, delta qp."] + #[inline(always)] + #[must_use] + pub fn b_no_roi_region_qp(&mut self) -> B_NO_ROI_REGION_QP_W { + B_NO_ROI_REGION_QP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 no roi region QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_no_roi_region_qp_offset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_no_roi_region_qp_offset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_NO_ROI_REGION_QP_OFFSET_SPEC; +impl crate::RegisterSpec for B_NO_ROI_REGION_QP_OFFSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_no_roi_region_qp_offset::R`](R) reader structure"] +impl crate::Readable for B_NO_ROI_REGION_QP_OFFSET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_no_roi_region_qp_offset::W`](W) writer structure"] +impl crate::Writable for B_NO_ROI_REGION_QP_OFFSET_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_NO_ROI_REGION_QP_OFFSET to value 0"] +impl crate::Resettable for B_NO_ROI_REGION_QP_OFFSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_rc_conf0.rs b/esp32p4/src/h264/b_rc_conf0.rs new file mode 100644 index 0000000000..4394bb943e --- /dev/null +++ b/esp32p4/src/h264/b_rc_conf0.rs @@ -0,0 +1,101 @@ +#[doc = "Register `B_RC_CONF0` reader"] +pub type R = crate::R; +#[doc = "Register `B_RC_CONF0` writer"] +pub type W = crate::W; +#[doc = "Field `B_QP` reader - Configures video B frame level initial luma QP value."] +pub type B_QP_R = crate::FieldReader; +#[doc = "Field `B_QP` writer - Configures video B frame level initial luma QP value."] +pub type B_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `B_RATE_CTRL_U` reader - Configures video B parameter U value. U = int((float) u << 8)."] +pub type B_RATE_CTRL_U_R = crate::FieldReader; +#[doc = "Field `B_RATE_CTRL_U` writer - Configures video B parameter U value. U = int((float) u << 8)."] +pub type B_RATE_CTRL_U_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `B_MB_RATE_CTRL_EN` reader - Configures video A whether or not to open macro block rate ctrl.\\\\1:Open the macro block rate ctrl\\\\1:Close the macro block rate ctrl."] +pub type B_MB_RATE_CTRL_EN_R = crate::BitReader; +#[doc = "Field `B_MB_RATE_CTRL_EN` writer - Configures video A whether or not to open macro block rate ctrl.\\\\1:Open the macro block rate ctrl\\\\1:Close the macro block rate ctrl."] +pub type B_MB_RATE_CTRL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - Configures video B frame level initial luma QP value."] + #[inline(always)] + pub fn b_qp(&self) -> B_QP_R { + B_QP_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:21 - Configures video B parameter U value. U = int((float) u << 8)."] + #[inline(always)] + pub fn b_rate_ctrl_u(&self) -> B_RATE_CTRL_U_R { + B_RATE_CTRL_U_R::new(((self.bits >> 6) & 0xffff) as u16) + } + #[doc = "Bit 22 - Configures video A whether or not to open macro block rate ctrl.\\\\1:Open the macro block rate ctrl\\\\1:Close the macro block rate ctrl."] + #[inline(always)] + pub fn b_mb_rate_ctrl_en(&self) -> B_MB_RATE_CTRL_EN_R { + B_MB_RATE_CTRL_EN_R::new(((self.bits >> 22) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_RC_CONF0") + .field("b_qp", &format_args!("{}", self.b_qp().bits())) + .field( + "b_rate_ctrl_u", + &format_args!("{}", self.b_rate_ctrl_u().bits()), + ) + .field( + "b_mb_rate_ctrl_en", + &format_args!("{}", self.b_mb_rate_ctrl_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - Configures video B frame level initial luma QP value."] + #[inline(always)] + #[must_use] + pub fn b_qp(&mut self) -> B_QP_W { + B_QP_W::new(self, 0) + } + #[doc = "Bits 6:21 - Configures video B parameter U value. U = int((float) u << 8)."] + #[inline(always)] + #[must_use] + pub fn b_rate_ctrl_u(&mut self) -> B_RATE_CTRL_U_W { + B_RATE_CTRL_U_W::new(self, 6) + } + #[doc = "Bit 22 - Configures video A whether or not to open macro block rate ctrl.\\\\1:Open the macro block rate ctrl\\\\1:Close the macro block rate ctrl."] + #[inline(always)] + #[must_use] + pub fn b_mb_rate_ctrl_en(&mut self) -> B_MB_RATE_CTRL_EN_W { + B_MB_RATE_CTRL_EN_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B rate control configuration register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_rc_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_rc_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_RC_CONF0_SPEC; +impl crate::RegisterSpec for B_RC_CONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_rc_conf0::R`](R) reader structure"] +impl crate::Readable for B_RC_CONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_rc_conf0::W`](W) writer structure"] +impl crate::Writable for B_RC_CONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_RC_CONF0 to value 0"] +impl crate::Resettable for B_RC_CONF0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_rc_conf1.rs b/esp32p4/src/h264/b_rc_conf1.rs new file mode 100644 index 0000000000..3ac0782613 --- /dev/null +++ b/esp32p4/src/h264/b_rc_conf1.rs @@ -0,0 +1,136 @@ +#[doc = "Register `B_RC_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `B_RC_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `B_CHROMA_DC_QP_DELTA` reader - Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta."] +pub type B_CHROMA_DC_QP_DELTA_R = crate::FieldReader; +#[doc = "Field `B_CHROMA_DC_QP_DELTA` writer - Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta."] +pub type B_CHROMA_DC_QP_DELTA_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `B_CHROMA_QP_DELTA` reader - Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta."] +pub type B_CHROMA_QP_DELTA_R = crate::FieldReader; +#[doc = "Field `B_CHROMA_QP_DELTA` writer - Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta."] +pub type B_CHROMA_QP_DELTA_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `B_QP_MIN` reader - Configures video B allowed luma QP min value."] +pub type B_QP_MIN_R = crate::FieldReader; +#[doc = "Field `B_QP_MIN` writer - Configures video B allowed luma QP min value."] +pub type B_QP_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `B_QP_MAX` reader - Configures video B allowed luma QP max value."] +pub type B_QP_MAX_R = crate::FieldReader; +#[doc = "Field `B_QP_MAX` writer - Configures video B allowed luma QP max value."] +pub type B_QP_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `B_MAD_FRAME_PRED` reader - Configures vdieo B frame level predicted MB MAD value."] +pub type B_MAD_FRAME_PRED_R = crate::FieldReader; +#[doc = "Field `B_MAD_FRAME_PRED` writer - Configures vdieo B frame level predicted MB MAD value."] +pub type B_MAD_FRAME_PRED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:2 - Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta."] + #[inline(always)] + pub fn b_chroma_dc_qp_delta(&self) -> B_CHROMA_DC_QP_DELTA_R { + B_CHROMA_DC_QP_DELTA_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:6 - Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta."] + #[inline(always)] + pub fn b_chroma_qp_delta(&self) -> B_CHROMA_QP_DELTA_R { + B_CHROMA_QP_DELTA_R::new(((self.bits >> 3) & 0x0f) as u8) + } + #[doc = "Bits 7:12 - Configures video B allowed luma QP min value."] + #[inline(always)] + pub fn b_qp_min(&self) -> B_QP_MIN_R { + B_QP_MIN_R::new(((self.bits >> 7) & 0x3f) as u8) + } + #[doc = "Bits 13:18 - Configures video B allowed luma QP max value."] + #[inline(always)] + pub fn b_qp_max(&self) -> B_QP_MAX_R { + B_QP_MAX_R::new(((self.bits >> 13) & 0x3f) as u8) + } + #[doc = "Bits 19:30 - Configures vdieo B frame level predicted MB MAD value."] + #[inline(always)] + pub fn b_mad_frame_pred(&self) -> B_MAD_FRAME_PRED_R { + B_MAD_FRAME_PRED_R::new(((self.bits >> 19) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_RC_CONF1") + .field( + "b_chroma_dc_qp_delta", + &format_args!("{}", self.b_chroma_dc_qp_delta().bits()), + ) + .field( + "b_chroma_qp_delta", + &format_args!("{}", self.b_chroma_qp_delta().bits()), + ) + .field("b_qp_min", &format_args!("{}", self.b_qp_min().bits())) + .field("b_qp_max", &format_args!("{}", self.b_qp_max().bits())) + .field( + "b_mad_frame_pred", + &format_args!("{}", self.b_mad_frame_pred().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta."] + #[inline(always)] + #[must_use] + pub fn b_chroma_dc_qp_delta(&mut self) -> B_CHROMA_DC_QP_DELTA_W { + B_CHROMA_DC_QP_DELTA_W::new(self, 0) + } + #[doc = "Bits 3:6 - Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta."] + #[inline(always)] + #[must_use] + pub fn b_chroma_qp_delta(&mut self) -> B_CHROMA_QP_DELTA_W { + B_CHROMA_QP_DELTA_W::new(self, 3) + } + #[doc = "Bits 7:12 - Configures video B allowed luma QP min value."] + #[inline(always)] + #[must_use] + pub fn b_qp_min(&mut self) -> B_QP_MIN_W { + B_QP_MIN_W::new(self, 7) + } + #[doc = "Bits 13:18 - Configures video B allowed luma QP max value."] + #[inline(always)] + #[must_use] + pub fn b_qp_max(&mut self) -> B_QP_MAX_W { + B_QP_MAX_W::new(self, 13) + } + #[doc = "Bits 19:30 - Configures vdieo B frame level predicted MB MAD value."] + #[inline(always)] + #[must_use] + pub fn b_mad_frame_pred(&mut self) -> B_MAD_FRAME_PRED_W { + B_MAD_FRAME_PRED_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B rate control configuration register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_rc_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_rc_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_RC_CONF1_SPEC; +impl crate::RegisterSpec for B_RC_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_rc_conf1::R`](R) reader structure"] +impl crate::Readable for B_RC_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_rc_conf1::W`](W) writer structure"] +impl crate::Writable for B_RC_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_RC_CONF1 to value 0"] +impl crate::Resettable for B_RC_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_roi_config.rs b/esp32p4/src/h264/b_roi_config.rs new file mode 100644 index 0000000000..1eda5fd2df --- /dev/null +++ b/esp32p4/src/h264/b_roi_config.rs @@ -0,0 +1,79 @@ +#[doc = "Register `B_ROI_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `B_ROI_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `B_ROI_EN` reader - Configure whether or not to enable ROI in video B.\\\\0:not enable ROI\\\\1:enable ROI."] +pub type B_ROI_EN_R = crate::BitReader; +#[doc = "Field `B_ROI_EN` writer - Configure whether or not to enable ROI in video B.\\\\0:not enable ROI\\\\1:enable ROI."] +pub type B_ROI_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_ROI_MODE` reader - Configure the mode of ROI in video B.\\\\0:fixed qp\\\\1:delta qp."] +pub type B_ROI_MODE_R = crate::BitReader; +#[doc = "Field `B_ROI_MODE` writer - Configure the mode of ROI in video B.\\\\0:fixed qp\\\\1:delta qp."] +pub type B_ROI_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configure whether or not to enable ROI in video B.\\\\0:not enable ROI\\\\1:enable ROI."] + #[inline(always)] + pub fn b_roi_en(&self) -> B_ROI_EN_R { + B_ROI_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configure the mode of ROI in video B.\\\\0:fixed qp\\\\1:delta qp."] + #[inline(always)] + pub fn b_roi_mode(&self) -> B_ROI_MODE_R { + B_ROI_MODE_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_ROI_CONFIG") + .field("b_roi_en", &format_args!("{}", self.b_roi_en().bit())) + .field("b_roi_mode", &format_args!("{}", self.b_roi_mode().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configure whether or not to enable ROI in video B.\\\\0:not enable ROI\\\\1:enable ROI."] + #[inline(always)] + #[must_use] + pub fn b_roi_en(&mut self) -> B_ROI_EN_W { + B_ROI_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configure the mode of ROI in video B.\\\\0:fixed qp\\\\1:delta qp."] + #[inline(always)] + #[must_use] + pub fn b_roi_mode(&mut self) -> B_ROI_MODE_W { + B_ROI_MODE_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 ROI configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_ROI_CONFIG_SPEC; +impl crate::RegisterSpec for B_ROI_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_roi_config::R`](R) reader structure"] +impl crate::Readable for B_ROI_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_roi_config::W`](W) writer structure"] +impl crate::Writable for B_ROI_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_ROI_CONFIG to value 0"] +impl crate::Resettable for B_ROI_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_roi_region0.rs b/esp32p4/src/h264/b_roi_region0.rs new file mode 100644 index 0000000000..f5211d0506 --- /dev/null +++ b/esp32p4/src/h264/b_roi_region0.rs @@ -0,0 +1,127 @@ +#[doc = "Register `B_ROI_REGION0` reader"] +pub type R = crate::R; +#[doc = "Register `B_ROI_REGION0` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 0 in Video B."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 0 in Video B."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 0 in Video B."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 0 in Video B."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 0 in Video B."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 0 in Video B."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 0 in Video B."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 0 in Video B."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video B ROI of region 0 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video B ROI of region 0 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 0 in Video B."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 0 in Video B."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 0 in Video B."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 0 in Video B."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 0 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_ROI_REGION0") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 0 in Video B."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 0 in Video B."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 0 in Video B."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 0 in Video B."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 0 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 ROI region0 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_ROI_REGION0_SPEC; +impl crate::RegisterSpec for B_ROI_REGION0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_roi_region0::R`](R) reader structure"] +impl crate::Readable for B_ROI_REGION0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_roi_region0::W`](W) writer structure"] +impl crate::Writable for B_ROI_REGION0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_ROI_REGION0 to value 0"] +impl crate::Resettable for B_ROI_REGION0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_roi_region0_3_qp.rs b/esp32p4/src/h264/b_roi_region0_3_qp.rs new file mode 100644 index 0000000000..565fa98a0a --- /dev/null +++ b/esp32p4/src/h264/b_roi_region0_3_qp.rs @@ -0,0 +1,123 @@ +#[doc = "Register `B_ROI_REGION0_3_QP` reader"] +pub type R = crate::R; +#[doc = "Register `B_ROI_REGION0_3_QP` writer"] +pub type W = crate::W; +#[doc = "Field `B_ROI_REGION0_QP` reader - Configure H264 ROI region0 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION0_QP_R = crate::FieldReader; +#[doc = "Field `B_ROI_REGION0_QP` writer - Configure H264 ROI region0 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION0_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `B_ROI_REGION1_QP` reader - Configure H264 ROI region1 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION1_QP_R = crate::FieldReader; +#[doc = "Field `B_ROI_REGION1_QP` writer - Configure H264 ROI region1 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION1_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `B_ROI_REGION2_QP` reader - Configure H264 ROI region2 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION2_QP_R = crate::FieldReader; +#[doc = "Field `B_ROI_REGION2_QP` writer - Configure H264 ROI region2 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION2_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `B_ROI_REGION3_QP` reader - Configure H264 ROI region3 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION3_QP_R = crate::FieldReader; +#[doc = "Field `B_ROI_REGION3_QP` writer - Configure H264 ROI region3 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION3_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Configure H264 ROI region0 qp in video B,fixed qp or delta qp."] + #[inline(always)] + pub fn b_roi_region0_qp(&self) -> B_ROI_REGION0_QP_R { + B_ROI_REGION0_QP_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configure H264 ROI region1 qp in video B,fixed qp or delta qp."] + #[inline(always)] + pub fn b_roi_region1_qp(&self) -> B_ROI_REGION1_QP_R { + B_ROI_REGION1_QP_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configure H264 ROI region2 qp in video B,fixed qp or delta qp."] + #[inline(always)] + pub fn b_roi_region2_qp(&self) -> B_ROI_REGION2_QP_R { + B_ROI_REGION2_QP_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configure H264 ROI region3 qp in video B,fixed qp or delta qp."] + #[inline(always)] + pub fn b_roi_region3_qp(&self) -> B_ROI_REGION3_QP_R { + B_ROI_REGION3_QP_R::new(((self.bits >> 21) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_ROI_REGION0_3_QP") + .field( + "b_roi_region0_qp", + &format_args!("{}", self.b_roi_region0_qp().bits()), + ) + .field( + "b_roi_region1_qp", + &format_args!("{}", self.b_roi_region1_qp().bits()), + ) + .field( + "b_roi_region2_qp", + &format_args!("{}", self.b_roi_region2_qp().bits()), + ) + .field( + "b_roi_region3_qp", + &format_args!("{}", self.b_roi_region3_qp().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configure H264 ROI region0 qp in video B,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn b_roi_region0_qp(&mut self) -> B_ROI_REGION0_QP_W { + B_ROI_REGION0_QP_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configure H264 ROI region1 qp in video B,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn b_roi_region1_qp(&mut self) -> B_ROI_REGION1_QP_W { + B_ROI_REGION1_QP_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configure H264 ROI region2 qp in video B,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn b_roi_region2_qp(&mut self) -> B_ROI_REGION2_QP_W { + B_ROI_REGION2_QP_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configure H264 ROI region3 qp in video B,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn b_roi_region3_qp(&mut self) -> B_ROI_REGION3_QP_W { + B_ROI_REGION3_QP_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 ROI region0, region1,region2,region3 QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region0_3_qp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region0_3_qp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_ROI_REGION0_3_QP_SPEC; +impl crate::RegisterSpec for B_ROI_REGION0_3_QP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_roi_region0_3_qp::R`](R) reader structure"] +impl crate::Readable for B_ROI_REGION0_3_QP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_roi_region0_3_qp::W`](W) writer structure"] +impl crate::Writable for B_ROI_REGION0_3_QP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_ROI_REGION0_3_QP to value 0"] +impl crate::Resettable for B_ROI_REGION0_3_QP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_roi_region1.rs b/esp32p4/src/h264/b_roi_region1.rs new file mode 100644 index 0000000000..517244f1a0 --- /dev/null +++ b/esp32p4/src/h264/b_roi_region1.rs @@ -0,0 +1,127 @@ +#[doc = "Register `B_ROI_REGION1` reader"] +pub type R = crate::R; +#[doc = "Register `B_ROI_REGION1` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 1 in Video B."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 1 in Video B."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 1 in Video B."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 1 in Video B."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 1 in Video B."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 1 in Video B."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 1 in Video B."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 1 in Video B."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video B ROI of region 1 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video B ROI of region 1 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 1 in Video B."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 1 in Video B."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 1 in Video B."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 1 in Video B."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 1 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_ROI_REGION1") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 1 in Video B."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 1 in Video B."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 1 in Video B."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 1 in Video B."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 1 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 ROI region1 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_ROI_REGION1_SPEC; +impl crate::RegisterSpec for B_ROI_REGION1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_roi_region1::R`](R) reader structure"] +impl crate::Readable for B_ROI_REGION1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_roi_region1::W`](W) writer structure"] +impl crate::Writable for B_ROI_REGION1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_ROI_REGION1 to value 0"] +impl crate::Resettable for B_ROI_REGION1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_roi_region2.rs b/esp32p4/src/h264/b_roi_region2.rs new file mode 100644 index 0000000000..4fcec12043 --- /dev/null +++ b/esp32p4/src/h264/b_roi_region2.rs @@ -0,0 +1,127 @@ +#[doc = "Register `B_ROI_REGION2` reader"] +pub type R = crate::R; +#[doc = "Register `B_ROI_REGION2` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 2 in Video B."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 2 in Video B."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 2 in Video B."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 2 in Video B."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 2 in Video B."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 2 in Video B."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 2 in Video B."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 2 in Video B."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video B ROI of region 2 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video B ROI of region 2 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 2 in Video B."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 2 in Video B."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 2 in Video B."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 2 in Video B."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 2 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_ROI_REGION2") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 2 in Video B."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 2 in Video B."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 2 in Video B."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 2 in Video B."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 2 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 ROI region2 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_ROI_REGION2_SPEC; +impl crate::RegisterSpec for B_ROI_REGION2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_roi_region2::R`](R) reader structure"] +impl crate::Readable for B_ROI_REGION2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_roi_region2::W`](W) writer structure"] +impl crate::Writable for B_ROI_REGION2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_ROI_REGION2 to value 0"] +impl crate::Resettable for B_ROI_REGION2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_roi_region3.rs b/esp32p4/src/h264/b_roi_region3.rs new file mode 100644 index 0000000000..0d73de65d4 --- /dev/null +++ b/esp32p4/src/h264/b_roi_region3.rs @@ -0,0 +1,127 @@ +#[doc = "Register `B_ROI_REGION3` reader"] +pub type R = crate::R; +#[doc = "Register `B_ROI_REGION3` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 3 in Video B."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 3 in Video B."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 3 in Video B."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 3 in Video B."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 3 in video B."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 3 in video B."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 3 in video B."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 3 in video B."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video B ROI of region 3 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video B ROI of region 3 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 3 in Video B."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 3 in Video B."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 3 in video B."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 3 in video B."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 3 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_ROI_REGION3") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 3 in Video B."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 3 in Video B."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 3 in video B."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 3 in video B."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 3 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 ROI region3 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_ROI_REGION3_SPEC; +impl crate::RegisterSpec for B_ROI_REGION3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_roi_region3::R`](R) reader structure"] +impl crate::Readable for B_ROI_REGION3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_roi_region3::W`](W) writer structure"] +impl crate::Writable for B_ROI_REGION3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_ROI_REGION3 to value 0"] +impl crate::Resettable for B_ROI_REGION3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_roi_region4.rs b/esp32p4/src/h264/b_roi_region4.rs new file mode 100644 index 0000000000..c4bb96e7e9 --- /dev/null +++ b/esp32p4/src/h264/b_roi_region4.rs @@ -0,0 +1,127 @@ +#[doc = "Register `B_ROI_REGION4` reader"] +pub type R = crate::R; +#[doc = "Register `B_ROI_REGION4` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 4 in Video B."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 4 in Video B."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 4 in Video B."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 4 in Video B."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 4 in video B."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 4 in video B."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 4 in video B."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 4 in video B."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video B ROI of region 4 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video B ROI of region 4 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 4 in Video B."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 4 in Video B."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 4 in video B."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 4 in video B."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 4 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_ROI_REGION4") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 4 in Video B."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 4 in Video B."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 4 in video B."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 4 in video B."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 4 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 ROI region4 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_ROI_REGION4_SPEC; +impl crate::RegisterSpec for B_ROI_REGION4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_roi_region4::R`](R) reader structure"] +impl crate::Readable for B_ROI_REGION4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_roi_region4::W`](W) writer structure"] +impl crate::Writable for B_ROI_REGION4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_ROI_REGION4 to value 0"] +impl crate::Resettable for B_ROI_REGION4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_roi_region4_7_qp.rs b/esp32p4/src/h264/b_roi_region4_7_qp.rs new file mode 100644 index 0000000000..189dee2d20 --- /dev/null +++ b/esp32p4/src/h264/b_roi_region4_7_qp.rs @@ -0,0 +1,123 @@ +#[doc = "Register `B_ROI_REGION4_7_QP` reader"] +pub type R = crate::R; +#[doc = "Register `B_ROI_REGION4_7_QP` writer"] +pub type W = crate::W; +#[doc = "Field `B_ROI_REGION4_QP` reader - Configure H264 ROI region4 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION4_QP_R = crate::FieldReader; +#[doc = "Field `B_ROI_REGION4_QP` writer - Configure H264 ROI region4 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION4_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `B_ROI_REGION5_QP` reader - Configure H264 ROI region5 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION5_QP_R = crate::FieldReader; +#[doc = "Field `B_ROI_REGION5_QP` writer - Configure H264 ROI region5 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION5_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `B_ROI_REGION6_QP` reader - Configure H264 ROI region6 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION6_QP_R = crate::FieldReader; +#[doc = "Field `B_ROI_REGION6_QP` writer - Configure H264 ROI region6 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION6_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `B_ROI_REGION7_QP` reader - Configure H264 ROI region7 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION7_QP_R = crate::FieldReader; +#[doc = "Field `B_ROI_REGION7_QP` writer - Configure H264 ROI region7 qp in video B,fixed qp or delta qp."] +pub type B_ROI_REGION7_QP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Configure H264 ROI region4 qp in video B,fixed qp or delta qp."] + #[inline(always)] + pub fn b_roi_region4_qp(&self) -> B_ROI_REGION4_QP_R { + B_ROI_REGION4_QP_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configure H264 ROI region5 qp in video B,fixed qp or delta qp."] + #[inline(always)] + pub fn b_roi_region5_qp(&self) -> B_ROI_REGION5_QP_R { + B_ROI_REGION5_QP_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configure H264 ROI region6 qp in video B,fixed qp or delta qp."] + #[inline(always)] + pub fn b_roi_region6_qp(&self) -> B_ROI_REGION6_QP_R { + B_ROI_REGION6_QP_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configure H264 ROI region7 qp in video B,fixed qp or delta qp."] + #[inline(always)] + pub fn b_roi_region7_qp(&self) -> B_ROI_REGION7_QP_R { + B_ROI_REGION7_QP_R::new(((self.bits >> 21) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_ROI_REGION4_7_QP") + .field( + "b_roi_region4_qp", + &format_args!("{}", self.b_roi_region4_qp().bits()), + ) + .field( + "b_roi_region5_qp", + &format_args!("{}", self.b_roi_region5_qp().bits()), + ) + .field( + "b_roi_region6_qp", + &format_args!("{}", self.b_roi_region6_qp().bits()), + ) + .field( + "b_roi_region7_qp", + &format_args!("{}", self.b_roi_region7_qp().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configure H264 ROI region4 qp in video B,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn b_roi_region4_qp(&mut self) -> B_ROI_REGION4_QP_W { + B_ROI_REGION4_QP_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configure H264 ROI region5 qp in video B,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn b_roi_region5_qp(&mut self) -> B_ROI_REGION5_QP_W { + B_ROI_REGION5_QP_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configure H264 ROI region6 qp in video B,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn b_roi_region6_qp(&mut self) -> B_ROI_REGION6_QP_W { + B_ROI_REGION6_QP_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configure H264 ROI region7 qp in video B,fixed qp or delta qp."] + #[inline(always)] + #[must_use] + pub fn b_roi_region7_qp(&mut self) -> B_ROI_REGION7_QP_W { + B_ROI_REGION7_QP_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 ROI region4, region5,region6,region7 QP register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region4_7_qp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region4_7_qp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_ROI_REGION4_7_QP_SPEC; +impl crate::RegisterSpec for B_ROI_REGION4_7_QP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_roi_region4_7_qp::R`](R) reader structure"] +impl crate::Readable for B_ROI_REGION4_7_QP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_roi_region4_7_qp::W`](W) writer structure"] +impl crate::Writable for B_ROI_REGION4_7_QP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_ROI_REGION4_7_QP to value 0"] +impl crate::Resettable for B_ROI_REGION4_7_QP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_roi_region5.rs b/esp32p4/src/h264/b_roi_region5.rs new file mode 100644 index 0000000000..4307fd2301 --- /dev/null +++ b/esp32p4/src/h264/b_roi_region5.rs @@ -0,0 +1,127 @@ +#[doc = "Register `B_ROI_REGION5` reader"] +pub type R = crate::R; +#[doc = "Register `B_ROI_REGION5` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontial start macroblocks of region 5 video B."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontial start macroblocks of region 5 video B."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 5 video B."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 5 video B."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 5 video B."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 5 video B."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 5 in video B."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 5 in video B."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video B ROI of region 5 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video B ROI of region 5 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 5 video B."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 5 video B."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 5 video B."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 5 in video B."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 5 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_ROI_REGION5") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 5 video B."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 5 video B."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 5 video B."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 5 in video B."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 5 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 ROI region5 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_ROI_REGION5_SPEC; +impl crate::RegisterSpec for B_ROI_REGION5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_roi_region5::R`](R) reader structure"] +impl crate::Readable for B_ROI_REGION5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_roi_region5::W`](W) writer structure"] +impl crate::Writable for B_ROI_REGION5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_ROI_REGION5 to value 0"] +impl crate::Resettable for B_ROI_REGION5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_roi_region6.rs b/esp32p4/src/h264/b_roi_region6.rs new file mode 100644 index 0000000000..f6bcf39559 --- /dev/null +++ b/esp32p4/src/h264/b_roi_region6.rs @@ -0,0 +1,127 @@ +#[doc = "Register `B_ROI_REGION6` reader"] +pub type R = crate::R; +#[doc = "Register `B_ROI_REGION6` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontial start macroblocks of region 6 video B."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontial start macroblocks of region 6 video B."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 6 in video B."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 6 in video B."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 6 in video B."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 6 in video B."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 6 in video B."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 6 in video B."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video B ROI of region 6 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video B ROI of region 6 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 6 video B."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 6 in video B."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 6 in video B."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 6 in video B."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 6 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_ROI_REGION6") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 6 video B."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 6 in video B."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 6 in video B."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 6 in video B."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 6 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 ROI region6 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_ROI_REGION6_SPEC; +impl crate::RegisterSpec for B_ROI_REGION6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_roi_region6::R`](R) reader structure"] +impl crate::Readable for B_ROI_REGION6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_roi_region6::W`](W) writer structure"] +impl crate::Writable for B_ROI_REGION6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_ROI_REGION6 to value 0"] +impl crate::Resettable for B_ROI_REGION6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_roi_region7.rs b/esp32p4/src/h264/b_roi_region7.rs new file mode 100644 index 0000000000..244a155e2c --- /dev/null +++ b/esp32p4/src/h264/b_roi_region7.rs @@ -0,0 +1,127 @@ +#[doc = "Register `B_ROI_REGION7` reader"] +pub type R = crate::R; +#[doc = "Register `B_ROI_REGION7` writer"] +pub type W = crate::W; +#[doc = "Field `X` reader - Configures the horizontal start macroblocks of region 7 in video B."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Configures the horizontal start macroblocks of region 7 in video B."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y` reader - Configures the vertical start macroblocks of region 7 in video B."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Configures the vertical start macroblocks of region 7 in video B."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `X_LEN` reader - Configures the number of macroblocks in horizontal direction of the region 7 in video B."] +pub type X_LEN_R = crate::FieldReader; +#[doc = "Field `X_LEN` writer - Configures the number of macroblocks in horizontal direction of the region 7 in video B."] +pub type X_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `Y_LEN` reader - Configures the number of macroblocks in vertical direction of the region 7 in video B."] +pub type Y_LEN_R = crate::FieldReader; +#[doc = "Field `Y_LEN` writer - Configures the number of macroblocks in vertical direction of the region 7 in video B."] +pub type Y_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `EN` reader - Configures whether or not to open Video B ROI of region 7 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open Video B ROI of region 7 .\\\\0:Close ROI\\\\1:Open ROI."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 7 in video B."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 7 in video B."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 7 in video B."] + #[inline(always)] + pub fn x_len(&self) -> X_LEN_R { + X_LEN_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 7 in video B."] + #[inline(always)] + pub fn y_len(&self) -> Y_LEN_R { + Y_LEN_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 7 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_ROI_REGION7") + .field("x", &format_args!("{}", self.x().bits())) + .field("y", &format_args!("{}", self.y().bits())) + .field("x_len", &format_args!("{}", self.x_len().bits())) + .field("y_len", &format_args!("{}", self.y_len().bits())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 7 in video B."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures the vertical start macroblocks of region 7 in video B."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 7) + } + #[doc = "Bits 14:20 - Configures the number of macroblocks in horizontal direction of the region 7 in video B."] + #[inline(always)] + #[must_use] + pub fn x_len(&mut self) -> X_LEN_W { + X_LEN_W::new(self, 14) + } + #[doc = "Bits 21:27 - Configures the number of macroblocks in vertical direction of the region 7 in video B."] + #[inline(always)] + #[must_use] + pub fn y_len(&mut self) -> Y_LEN_W { + Y_LEN_W::new(self, 21) + } + #[doc = "Bit 28 - Configures whether or not to open Video B ROI of region 7 .\\\\0:Close ROI\\\\1:Open ROI."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B H264 ROI region7 range configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_roi_region7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_roi_region7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_ROI_REGION7_SPEC; +impl crate::RegisterSpec for B_ROI_REGION7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_roi_region7::R`](R) reader structure"] +impl crate::Readable for B_ROI_REGION7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_roi_region7::W`](W) writer structure"] +impl crate::Writable for B_ROI_REGION7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_ROI_REGION7 to value 0"] +impl crate::Resettable for B_ROI_REGION7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/b_sys_conf.rs b/esp32p4/src/h264/b_sys_conf.rs new file mode 100644 index 0000000000..1a80a87e1e --- /dev/null +++ b/esp32p4/src/h264/b_sys_conf.rs @@ -0,0 +1,108 @@ +#[doc = "Register `B_SYS_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `B_SYS_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `B_DB_TMP_READY_TRIGGER_MB_NUM` reader - Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3."] +pub type B_DB_TMP_READY_TRIGGER_MB_NUM_R = crate::FieldReader; +#[doc = "Field `B_DB_TMP_READY_TRIGGER_MB_NUM` writer - Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3."] +pub type B_DB_TMP_READY_TRIGGER_MB_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `B_REC_READY_TRIGGER_MB_LINES` reader - Configures when to trigger video B H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4."] +pub type B_REC_READY_TRIGGER_MB_LINES_R = crate::FieldReader; +#[doc = "Field `B_REC_READY_TRIGGER_MB_LINES` writer - Configures when to trigger video B H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4."] +pub type B_REC_READY_TRIGGER_MB_LINES_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `B_INTRA_COST_CMP_OFFSET` reader - Configures video B intra cost offset when I MB compared with P MB."] +pub type B_INTRA_COST_CMP_OFFSET_R = crate::FieldReader; +#[doc = "Field `B_INTRA_COST_CMP_OFFSET` writer - Configures video B intra cost offset when I MB compared with P MB."] +pub type B_INTRA_COST_CMP_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:6 - Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3."] + #[inline(always)] + pub fn b_db_tmp_ready_trigger_mb_num(&self) -> B_DB_TMP_READY_TRIGGER_MB_NUM_R { + B_DB_TMP_READY_TRIGGER_MB_NUM_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures when to trigger video B H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4."] + #[inline(always)] + pub fn b_rec_ready_trigger_mb_lines(&self) -> B_REC_READY_TRIGGER_MB_LINES_R { + B_REC_READY_TRIGGER_MB_LINES_R::new(((self.bits >> 7) & 0x7f) as u8) + } + #[doc = "Bits 14:29 - Configures video B intra cost offset when I MB compared with P MB."] + #[inline(always)] + pub fn b_intra_cost_cmp_offset(&self) -> B_INTRA_COST_CMP_OFFSET_R { + B_INTRA_COST_CMP_OFFSET_R::new(((self.bits >> 14) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_SYS_CONF") + .field( + "b_db_tmp_ready_trigger_mb_num", + &format_args!("{}", self.b_db_tmp_ready_trigger_mb_num().bits()), + ) + .field( + "b_rec_ready_trigger_mb_lines", + &format_args!("{}", self.b_rec_ready_trigger_mb_lines().bits()), + ) + .field( + "b_intra_cost_cmp_offset", + &format_args!("{}", self.b_intra_cost_cmp_offset().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3."] + #[inline(always)] + #[must_use] + pub fn b_db_tmp_ready_trigger_mb_num( + &mut self, + ) -> B_DB_TMP_READY_TRIGGER_MB_NUM_W { + B_DB_TMP_READY_TRIGGER_MB_NUM_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures when to trigger video B H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4."] + #[inline(always)] + #[must_use] + pub fn b_rec_ready_trigger_mb_lines( + &mut self, + ) -> B_REC_READY_TRIGGER_MB_LINES_W { + B_REC_READY_TRIGGER_MB_LINES_W::new(self, 7) + } + #[doc = "Bits 14:29 - Configures video B intra cost offset when I MB compared with P MB."] + #[inline(always)] + #[must_use] + pub fn b_intra_cost_cmp_offset(&mut self) -> B_INTRA_COST_CMP_OFFSET_W { + B_INTRA_COST_CMP_OFFSET_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B system level configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_sys_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_sys_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_SYS_CONF_SPEC; +impl crate::RegisterSpec for B_SYS_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_sys_conf::R`](R) reader structure"] +impl crate::Readable for B_SYS_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_sys_conf::W`](W) writer structure"] +impl crate::Writable for B_SYS_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_SYS_CONF to value 0x0203"] +impl crate::Resettable for B_SYS_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0203; +} diff --git a/esp32p4/src/h264/b_sys_mb_res.rs b/esp32p4/src/h264/b_sys_mb_res.rs new file mode 100644 index 0000000000..0c8c2cc72a --- /dev/null +++ b/esp32p4/src/h264/b_sys_mb_res.rs @@ -0,0 +1,85 @@ +#[doc = "Register `B_SYS_MB_RES` reader"] +pub type R = crate::R; +#[doc = "Register `B_SYS_MB_RES` writer"] +pub type W = crate::W; +#[doc = "Field `B_SYS_TOTAL_MB_Y` reader - Configures video B vertical MB resolution."] +pub type B_SYS_TOTAL_MB_Y_R = crate::FieldReader; +#[doc = "Field `B_SYS_TOTAL_MB_Y` writer - Configures video B vertical MB resolution."] +pub type B_SYS_TOTAL_MB_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `B_SYS_TOTAL_MB_X` reader - Configures video B horizontal MB resolution."] +pub type B_SYS_TOTAL_MB_X_R = crate::FieldReader; +#[doc = "Field `B_SYS_TOTAL_MB_X` writer - Configures video B horizontal MB resolution."] +pub type B_SYS_TOTAL_MB_X_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Configures video B vertical MB resolution."] + #[inline(always)] + pub fn b_sys_total_mb_y(&self) -> B_SYS_TOTAL_MB_Y_R { + B_SYS_TOTAL_MB_Y_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:13 - Configures video B horizontal MB resolution."] + #[inline(always)] + pub fn b_sys_total_mb_x(&self) -> B_SYS_TOTAL_MB_X_R { + B_SYS_TOTAL_MB_X_R::new(((self.bits >> 7) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("B_SYS_MB_RES") + .field( + "b_sys_total_mb_y", + &format_args!("{}", self.b_sys_total_mb_y().bits()), + ) + .field( + "b_sys_total_mb_x", + &format_args!("{}", self.b_sys_total_mb_x().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures video B vertical MB resolution."] + #[inline(always)] + #[must_use] + pub fn b_sys_total_mb_y(&mut self) -> B_SYS_TOTAL_MB_Y_W { + B_SYS_TOTAL_MB_Y_W::new(self, 0) + } + #[doc = "Bits 7:13 - Configures video B horizontal MB resolution."] + #[inline(always)] + #[must_use] + pub fn b_sys_total_mb_x(&mut self) -> B_SYS_TOTAL_MB_X_W { + B_SYS_TOTAL_MB_X_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Video B horizontal and vertical MB resolution register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`b_sys_mb_res::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`b_sys_mb_res::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct B_SYS_MB_RES_SPEC; +impl crate::RegisterSpec for B_SYS_MB_RES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`b_sys_mb_res::R`](R) reader structure"] +impl crate::Readable for B_SYS_MB_RES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`b_sys_mb_res::W`](W) writer structure"] +impl crate::Writable for B_SYS_MB_RES_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets B_SYS_MB_RES to value 0"] +impl crate::Resettable for B_SYS_MB_RES_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/bs_threshold.rs b/esp32p4/src/h264/bs_threshold.rs new file mode 100644 index 0000000000..77642489cf --- /dev/null +++ b/esp32p4/src/h264/bs_threshold.rs @@ -0,0 +1,66 @@ +#[doc = "Register `BS_THRESHOLD` reader"] +pub type R = crate::R; +#[doc = "Register `BS_THRESHOLD` writer"] +pub type W = crate::W; +#[doc = "Field `BS_BUFFER_THRESHOLD` reader - Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb."] +pub type BS_BUFFER_THRESHOLD_R = crate::FieldReader; +#[doc = "Field `BS_BUFFER_THRESHOLD` writer - Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb."] +pub type BS_BUFFER_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb."] + #[inline(always)] + pub fn bs_buffer_threshold(&self) -> BS_BUFFER_THRESHOLD_R { + BS_BUFFER_THRESHOLD_R::new((self.bits & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BS_THRESHOLD") + .field( + "bs_buffer_threshold", + &format_args!("{}", self.bs_buffer_threshold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb."] + #[inline(always)] + #[must_use] + pub fn bs_buffer_threshold(&mut self) -> BS_BUFFER_THRESHOLD_W { + BS_BUFFER_THRESHOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Bitstream buffer overflow threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bs_threshold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bs_threshold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BS_THRESHOLD_SPEC; +impl crate::RegisterSpec for BS_THRESHOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bs_threshold::R`](R) reader structure"] +impl crate::Readable for BS_THRESHOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bs_threshold::W`](W) writer structure"] +impl crate::Writable for BS_THRESHOLD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BS_THRESHOLD to value 0x30"] +impl crate::Resettable for BS_THRESHOLD_SPEC { + const RESET_VALUE: Self::Ux = 0x30; +} diff --git a/esp32p4/src/h264/conf.rs b/esp32p4/src/h264/conf.rs new file mode 100644 index 0000000000..e8526fcd5e --- /dev/null +++ b/esp32p4/src/h264/conf.rs @@ -0,0 +1,520 @@ +#[doc = "Register `CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REC_RAM_CLK_EN2` reader - Configures whether or not to open the clock gate for rec ram2.\\\\0: Open the clock gate only when application writes or reads rec ram2\\\\1: Force open the clock gate for rec ram2"] +pub type REC_RAM_CLK_EN2_R = crate::BitReader; +#[doc = "Field `REC_RAM_CLK_EN2` writer - Configures whether or not to open the clock gate for rec ram2.\\\\0: Open the clock gate only when application writes or reads rec ram2\\\\1: Force open the clock gate for rec ram2"] +pub type REC_RAM_CLK_EN2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REC_RAM_CLK_EN1` reader - Configures whether or not to open the clock gate for rec ram1.\\\\0: Open the clock gate only when application writes or reads rec ram1\\\\1: Force open the clock gate for rec ram1"] +pub type REC_RAM_CLK_EN1_R = crate::BitReader; +#[doc = "Field `REC_RAM_CLK_EN1` writer - Configures whether or not to open the clock gate for rec ram1.\\\\0: Open the clock gate only when application writes or reads rec ram1\\\\1: Force open the clock gate for rec ram1"] +pub type REC_RAM_CLK_EN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QUANT_RAM_CLK_EN2` reader - Configures whether or not to open the clock gate for quant ram2.\\\\0: Open the clock gate only when application writes or reads quant ram2\\\\1: Force open the clock gate for quant ram2"] +pub type QUANT_RAM_CLK_EN2_R = crate::BitReader; +#[doc = "Field `QUANT_RAM_CLK_EN2` writer - Configures whether or not to open the clock gate for quant ram2.\\\\0: Open the clock gate only when application writes or reads quant ram2\\\\1: Force open the clock gate for quant ram2"] +pub type QUANT_RAM_CLK_EN2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QUANT_RAM_CLK_EN1` reader - Configures whether or not to open the clock gate for quant ram1.\\\\0: Open the clock gate only when application writes or reads quant ram1\\\\1: Force open the clock gate for quant ram1"] +pub type QUANT_RAM_CLK_EN1_R = crate::BitReader; +#[doc = "Field `QUANT_RAM_CLK_EN1` writer - Configures whether or not to open the clock gate for quant ram1.\\\\0: Open the clock gate only when application writes or reads quant ram1\\\\1: Force open the clock gate for quant ram1"] +pub type QUANT_RAM_CLK_EN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PRE_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for pre ram.\\\\0: Open the clock gate only when application writes or reads pre ram\\\\1: Force open the clock gate for pre ram"] +pub type PRE_RAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `PRE_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for pre ram.\\\\0: Open the clock gate only when application writes or reads pre ram\\\\1: Force open the clock gate for pre ram"] +pub type PRE_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MVD_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for mvd ram.\\\\0: Open the clock gate only when application writes or reads mvd ram\\\\1: Force open the clock gate for mvd ram"] +pub type MVD_RAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `MVD_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for mvd ram.\\\\0: Open the clock gate only when application writes or reads mvd ram\\\\1: Force open the clock gate for mvd ram"] +pub type MVD_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MC_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for mc ram.\\\\0: Open the clock gate only when application writes or reads mc ram\\\\1: Force open the clock gate for mc ram"] +pub type MC_RAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `MC_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for mc ram.\\\\0: Open the clock gate only when application writes or reads mc ram\\\\1: Force open the clock gate for mc ram"] +pub type MC_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REF_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for ref ram.\\\\0: Open the clock gate only when application writes or reads ref ram\\\\1: Force open the clock gate for ref ram"] +pub type REF_RAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REF_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for ref ram.\\\\0: Open the clock gate only when application writes or reads ref ram\\\\1: Force open the clock gate for ref ram"] +pub type REF_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I4X4_REF_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for i4x4_mode ram.\\\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\\\1: Force open the clock gate for i4x4_mode ram"] +pub type I4X4_REF_RAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `I4X4_REF_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for i4x4_mode ram.\\\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\\\1: Force open the clock gate for i4x4_mode ram"] +pub type I4X4_REF_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IME_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for ime ram.\\\\0: Open the clock gate only when application writes or reads ime ram\\\\1: Force open the clock gate for ime ram"] +pub type IME_RAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `IME_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for ime ram.\\\\0: Open the clock gate only when application writes or reads ime ram\\\\1: Force open the clock gate for ime ram"] +pub type IME_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FME_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for fme ram.\\\\0: Open the clock gate only when application writes or readsfme ram\\\\1: Force open the clock gate for fme ram"] +pub type FME_RAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `FME_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for fme ram.\\\\0: Open the clock gate only when application writes or readsfme ram\\\\1: Force open the clock gate for fme ram"] +pub type FME_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FETCH_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for fetch ram.\\\\0: Open the clock gate only when application writes or reads fetch ram\\\\1: Force open the clock gate for fetch ram"] +pub type FETCH_RAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `FETCH_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for fetch ram.\\\\0: Open the clock gate only when application writes or reads fetch ram\\\\1: Force open the clock gate for fetch ram"] +pub type FETCH_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DB_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for db ram.\\\\0: Open the clock gate only when application writes or reads db ram\\\\1: Force open the clock gate for db ram"] +pub type DB_RAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `DB_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for db ram.\\\\0: Open the clock gate only when application writes or reads db ram\\\\1: Force open the clock gate for db ram"] +pub type DB_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CUR_MB_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for cur_mb ram.\\\\0: Open the clock gate only when application writes or reads cur_mb ram\\\\1: Force open the clock gate for cur_mb ram"] +pub type CUR_MB_RAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `CUR_MB_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for cur_mb ram.\\\\0: Open the clock gate only when application writes or reads cur_mb ram\\\\1: Force open the clock gate for cur_mb ram"] +pub type CUR_MB_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAVLC_RAM_CLK_EN` reader - Configures whether or not to open the clock gate for cavlc ram.\\\\0: Open the clock gate only when application writes or reads cavlc ram\\\\1: Force open the clock gate for cavlc ram"] +pub type CAVLC_RAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `CAVLC_RAM_CLK_EN` writer - Configures whether or not to open the clock gate for cavlc ram.\\\\0: Open the clock gate only when application writes or reads cavlc ram\\\\1: Force open the clock gate for cavlc ram"] +pub type CAVLC_RAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IME_CLK_EN` reader - Configures whether or not to open the clock gate for ime.\\\\0: Open the clock gate only when ime work\\\\1: Force open the clock gate for ime"] +pub type IME_CLK_EN_R = crate::BitReader; +#[doc = "Field `IME_CLK_EN` writer - Configures whether or not to open the clock gate for ime.\\\\0: Open the clock gate only when ime work\\\\1: Force open the clock gate for ime"] +pub type IME_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FME_CLK_EN` reader - Configures whether or not to open the clock gate for fme.\\\\0: Open the clock gate only when fme work\\\\1: Force open the clock gate for fme"] +pub type FME_CLK_EN_R = crate::BitReader; +#[doc = "Field `FME_CLK_EN` writer - Configures whether or not to open the clock gate for fme.\\\\0: Open the clock gate only when fme work\\\\1: Force open the clock gate for fme"] +pub type FME_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MC_CLK_EN` reader - Configures whether or not to open the clock gate for mc.\\\\0: Open the clock gate only when mc work\\\\1: Force open the clock gate for mc"] +pub type MC_CLK_EN_R = crate::BitReader; +#[doc = "Field `MC_CLK_EN` writer - Configures whether or not to open the clock gate for mc.\\\\0: Open the clock gate only when mc work\\\\1: Force open the clock gate for mc"] +pub type MC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTERPOLATOR_CLK_EN` reader - Configures whether or not to open the clock gate for interpolator.\\\\0: Open the clock gate only when interpolator work\\\\1: Force open the clock gate for interpolator"] +pub type INTERPOLATOR_CLK_EN_R = crate::BitReader; +#[doc = "Field `INTERPOLATOR_CLK_EN` writer - Configures whether or not to open the clock gate for interpolator.\\\\0: Open the clock gate only when interpolator work\\\\1: Force open the clock gate for interpolator"] +pub type INTERPOLATOR_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DB_CLK_EN` reader - Configures whether or not to open the clock gate for deblocking filter.\\\\0: Open the clock gate only when deblocking filter work\\\\1: Force open the clock gate for deblocking filter"] +pub type DB_CLK_EN_R = crate::BitReader; +#[doc = "Field `DB_CLK_EN` writer - Configures whether or not to open the clock gate for deblocking filter.\\\\0: Open the clock gate only when deblocking filter work\\\\1: Force open the clock gate for deblocking filter"] +pub type DB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLAVLC_CLK_EN` reader - Configures whether or not to open the clock gate for cavlc.\\\\0: Open the clock gate only when cavlc work\\\\1: Force open the clock gate for cavlc"] +pub type CLAVLC_CLK_EN_R = crate::BitReader; +#[doc = "Field `CLAVLC_CLK_EN` writer - Configures whether or not to open the clock gate for cavlc.\\\\0: Open the clock gate only when cavlc work\\\\1: Force open the clock gate for cavlc"] +pub type CLAVLC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTRA_CLK_EN` reader - Configures whether or not to open the clock gate for intra.\\\\0: Open the clock gate only when intra work\\\\1: Force open the clock gate for intra"] +pub type INTRA_CLK_EN_R = crate::BitReader; +#[doc = "Field `INTRA_CLK_EN` writer - Configures whether or not to open the clock gate for intra.\\\\0: Open the clock gate only when intra work\\\\1: Force open the clock gate for intra"] +pub type INTRA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DECI_CLK_EN` reader - Configures whether or not to open the clock gate for decimate.\\\\0: Open the clock gate only when decimate work\\\\1: Force open the clock gate for decimate"] +pub type DECI_CLK_EN_R = crate::BitReader; +#[doc = "Field `DECI_CLK_EN` writer - Configures whether or not to open the clock gate for decimate.\\\\0: Open the clock gate only when decimate work\\\\1: Force open the clock gate for decimate"] +pub type DECI_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BS_CLK_EN` reader - Configures whether or not to open the clock gate for bs buffer.\\\\0: Open the clock gate only when bs buffer work\\\\1: Force open the clock gate for bs buffer"] +pub type BS_CLK_EN_R = crate::BitReader; +#[doc = "Field `BS_CLK_EN` writer - Configures whether or not to open the clock gate for bs buffer.\\\\0: Open the clock gate only when bs buffer work\\\\1: Force open the clock gate for bs buffer"] +pub type BS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MV_MERGE_CLK_EN` reader - Configures whether or not to open the clock gate for mv merge.\\\\0: Open the clock gate only when mv merge work\\\\1: Force open the clock gate for mv merge"] +pub type MV_MERGE_CLK_EN_R = crate::BitReader; +#[doc = "Field `MV_MERGE_CLK_EN` writer - Configures whether or not to open the clock gate for mv merge.\\\\0: Open the clock gate only when mv merge work\\\\1: Force open the clock gate for mv merge"] +pub type MV_MERGE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures whether or not to open the clock gate for rec ram2.\\\\0: Open the clock gate only when application writes or reads rec ram2\\\\1: Force open the clock gate for rec ram2"] + #[inline(always)] + pub fn rec_ram_clk_en2(&self) -> REC_RAM_CLK_EN2_R { + REC_RAM_CLK_EN2_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures whether or not to open the clock gate for rec ram1.\\\\0: Open the clock gate only when application writes or reads rec ram1\\\\1: Force open the clock gate for rec ram1"] + #[inline(always)] + pub fn rec_ram_clk_en1(&self) -> REC_RAM_CLK_EN1_R { + REC_RAM_CLK_EN1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures whether or not to open the clock gate for quant ram2.\\\\0: Open the clock gate only when application writes or reads quant ram2\\\\1: Force open the clock gate for quant ram2"] + #[inline(always)] + pub fn quant_ram_clk_en2(&self) -> QUANT_RAM_CLK_EN2_R { + QUANT_RAM_CLK_EN2_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures whether or not to open the clock gate for quant ram1.\\\\0: Open the clock gate only when application writes or reads quant ram1\\\\1: Force open the clock gate for quant ram1"] + #[inline(always)] + pub fn quant_ram_clk_en1(&self) -> QUANT_RAM_CLK_EN1_R { + QUANT_RAM_CLK_EN1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures whether or not to open the clock gate for pre ram.\\\\0: Open the clock gate only when application writes or reads pre ram\\\\1: Force open the clock gate for pre ram"] + #[inline(always)] + pub fn pre_ram_clk_en(&self) -> PRE_RAM_CLK_EN_R { + PRE_RAM_CLK_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Configures whether or not to open the clock gate for mvd ram.\\\\0: Open the clock gate only when application writes or reads mvd ram\\\\1: Force open the clock gate for mvd ram"] + #[inline(always)] + pub fn mvd_ram_clk_en(&self) -> MVD_RAM_CLK_EN_R { + MVD_RAM_CLK_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures whether or not to open the clock gate for mc ram.\\\\0: Open the clock gate only when application writes or reads mc ram\\\\1: Force open the clock gate for mc ram"] + #[inline(always)] + pub fn mc_ram_clk_en(&self) -> MC_RAM_CLK_EN_R { + MC_RAM_CLK_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configures whether or not to open the clock gate for ref ram.\\\\0: Open the clock gate only when application writes or reads ref ram\\\\1: Force open the clock gate for ref ram"] + #[inline(always)] + pub fn ref_ram_clk_en(&self) -> REF_RAM_CLK_EN_R { + REF_RAM_CLK_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures whether or not to open the clock gate for i4x4_mode ram.\\\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\\\1: Force open the clock gate for i4x4_mode ram"] + #[inline(always)] + pub fn i4x4_ref_ram_clk_en(&self) -> I4X4_REF_RAM_CLK_EN_R { + I4X4_REF_RAM_CLK_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Configures whether or not to open the clock gate for ime ram.\\\\0: Open the clock gate only when application writes or reads ime ram\\\\1: Force open the clock gate for ime ram"] + #[inline(always)] + pub fn ime_ram_clk_en(&self) -> IME_RAM_CLK_EN_R { + IME_RAM_CLK_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Configures whether or not to open the clock gate for fme ram.\\\\0: Open the clock gate only when application writes or readsfme ram\\\\1: Force open the clock gate for fme ram"] + #[inline(always)] + pub fn fme_ram_clk_en(&self) -> FME_RAM_CLK_EN_R { + FME_RAM_CLK_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Configures whether or not to open the clock gate for fetch ram.\\\\0: Open the clock gate only when application writes or reads fetch ram\\\\1: Force open the clock gate for fetch ram"] + #[inline(always)] + pub fn fetch_ram_clk_en(&self) -> FETCH_RAM_CLK_EN_R { + FETCH_RAM_CLK_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures whether or not to open the clock gate for db ram.\\\\0: Open the clock gate only when application writes or reads db ram\\\\1: Force open the clock gate for db ram"] + #[inline(always)] + pub fn db_ram_clk_en(&self) -> DB_RAM_CLK_EN_R { + DB_RAM_CLK_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Configures whether or not to open the clock gate for cur_mb ram.\\\\0: Open the clock gate only when application writes or reads cur_mb ram\\\\1: Force open the clock gate for cur_mb ram"] + #[inline(always)] + pub fn cur_mb_ram_clk_en(&self) -> CUR_MB_RAM_CLK_EN_R { + CUR_MB_RAM_CLK_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Configures whether or not to open the clock gate for cavlc ram.\\\\0: Open the clock gate only when application writes or reads cavlc ram\\\\1: Force open the clock gate for cavlc ram"] + #[inline(always)] + pub fn cavlc_ram_clk_en(&self) -> CAVLC_RAM_CLK_EN_R { + CAVLC_RAM_CLK_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Configures whether or not to open the clock gate for ime.\\\\0: Open the clock gate only when ime work\\\\1: Force open the clock gate for ime"] + #[inline(always)] + pub fn ime_clk_en(&self) -> IME_CLK_EN_R { + IME_CLK_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Configures whether or not to open the clock gate for fme.\\\\0: Open the clock gate only when fme work\\\\1: Force open the clock gate for fme"] + #[inline(always)] + pub fn fme_clk_en(&self) -> FME_CLK_EN_R { + FME_CLK_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Configures whether or not to open the clock gate for mc.\\\\0: Open the clock gate only when mc work\\\\1: Force open the clock gate for mc"] + #[inline(always)] + pub fn mc_clk_en(&self) -> MC_CLK_EN_R { + MC_CLK_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Configures whether or not to open the clock gate for interpolator.\\\\0: Open the clock gate only when interpolator work\\\\1: Force open the clock gate for interpolator"] + #[inline(always)] + pub fn interpolator_clk_en(&self) -> INTERPOLATOR_CLK_EN_R { + INTERPOLATOR_CLK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Configures whether or not to open the clock gate for deblocking filter.\\\\0: Open the clock gate only when deblocking filter work\\\\1: Force open the clock gate for deblocking filter"] + #[inline(always)] + pub fn db_clk_en(&self) -> DB_CLK_EN_R { + DB_CLK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Configures whether or not to open the clock gate for cavlc.\\\\0: Open the clock gate only when cavlc work\\\\1: Force open the clock gate for cavlc"] + #[inline(always)] + pub fn clavlc_clk_en(&self) -> CLAVLC_CLK_EN_R { + CLAVLC_CLK_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Configures whether or not to open the clock gate for intra.\\\\0: Open the clock gate only when intra work\\\\1: Force open the clock gate for intra"] + #[inline(always)] + pub fn intra_clk_en(&self) -> INTRA_CLK_EN_R { + INTRA_CLK_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Configures whether or not to open the clock gate for decimate.\\\\0: Open the clock gate only when decimate work\\\\1: Force open the clock gate for decimate"] + #[inline(always)] + pub fn deci_clk_en(&self) -> DECI_CLK_EN_R { + DECI_CLK_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Configures whether or not to open the clock gate for bs buffer.\\\\0: Open the clock gate only when bs buffer work\\\\1: Force open the clock gate for bs buffer"] + #[inline(always)] + pub fn bs_clk_en(&self) -> BS_CLK_EN_R { + BS_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Configures whether or not to open the clock gate for mv merge.\\\\0: Open the clock gate only when mv merge work\\\\1: Force open the clock gate for mv merge"] + #[inline(always)] + pub fn mv_merge_clk_en(&self) -> MV_MERGE_CLK_EN_R { + MV_MERGE_CLK_EN_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field( + "rec_ram_clk_en2", + &format_args!("{}", self.rec_ram_clk_en2().bit()), + ) + .field( + "rec_ram_clk_en1", + &format_args!("{}", self.rec_ram_clk_en1().bit()), + ) + .field( + "quant_ram_clk_en2", + &format_args!("{}", self.quant_ram_clk_en2().bit()), + ) + .field( + "quant_ram_clk_en1", + &format_args!("{}", self.quant_ram_clk_en1().bit()), + ) + .field( + "pre_ram_clk_en", + &format_args!("{}", self.pre_ram_clk_en().bit()), + ) + .field( + "mvd_ram_clk_en", + &format_args!("{}", self.mvd_ram_clk_en().bit()), + ) + .field( + "mc_ram_clk_en", + &format_args!("{}", self.mc_ram_clk_en().bit()), + ) + .field( + "ref_ram_clk_en", + &format_args!("{}", self.ref_ram_clk_en().bit()), + ) + .field( + "i4x4_ref_ram_clk_en", + &format_args!("{}", self.i4x4_ref_ram_clk_en().bit()), + ) + .field( + "ime_ram_clk_en", + &format_args!("{}", self.ime_ram_clk_en().bit()), + ) + .field( + "fme_ram_clk_en", + &format_args!("{}", self.fme_ram_clk_en().bit()), + ) + .field( + "fetch_ram_clk_en", + &format_args!("{}", self.fetch_ram_clk_en().bit()), + ) + .field( + "db_ram_clk_en", + &format_args!("{}", self.db_ram_clk_en().bit()), + ) + .field( + "cur_mb_ram_clk_en", + &format_args!("{}", self.cur_mb_ram_clk_en().bit()), + ) + .field( + "cavlc_ram_clk_en", + &format_args!("{}", self.cavlc_ram_clk_en().bit()), + ) + .field("ime_clk_en", &format_args!("{}", self.ime_clk_en().bit())) + .field("fme_clk_en", &format_args!("{}", self.fme_clk_en().bit())) + .field("mc_clk_en", &format_args!("{}", self.mc_clk_en().bit())) + .field( + "interpolator_clk_en", + &format_args!("{}", self.interpolator_clk_en().bit()), + ) + .field("db_clk_en", &format_args!("{}", self.db_clk_en().bit())) + .field( + "clavlc_clk_en", + &format_args!("{}", self.clavlc_clk_en().bit()), + ) + .field( + "intra_clk_en", + &format_args!("{}", self.intra_clk_en().bit()), + ) + .field("deci_clk_en", &format_args!("{}", self.deci_clk_en().bit())) + .field("bs_clk_en", &format_args!("{}", self.bs_clk_en().bit())) + .field( + "mv_merge_clk_en", + &format_args!("{}", self.mv_merge_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to open the clock gate for rec ram2.\\\\0: Open the clock gate only when application writes or reads rec ram2\\\\1: Force open the clock gate for rec ram2"] + #[inline(always)] + #[must_use] + pub fn rec_ram_clk_en2(&mut self) -> REC_RAM_CLK_EN2_W { + REC_RAM_CLK_EN2_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to open the clock gate for rec ram1.\\\\0: Open the clock gate only when application writes or reads rec ram1\\\\1: Force open the clock gate for rec ram1"] + #[inline(always)] + #[must_use] + pub fn rec_ram_clk_en1(&mut self) -> REC_RAM_CLK_EN1_W { + REC_RAM_CLK_EN1_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to open the clock gate for quant ram2.\\\\0: Open the clock gate only when application writes or reads quant ram2\\\\1: Force open the clock gate for quant ram2"] + #[inline(always)] + #[must_use] + pub fn quant_ram_clk_en2(&mut self) -> QUANT_RAM_CLK_EN2_W { + QUANT_RAM_CLK_EN2_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to open the clock gate for quant ram1.\\\\0: Open the clock gate only when application writes or reads quant ram1\\\\1: Force open the clock gate for quant ram1"] + #[inline(always)] + #[must_use] + pub fn quant_ram_clk_en1(&mut self) -> QUANT_RAM_CLK_EN1_W { + QUANT_RAM_CLK_EN1_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to open the clock gate for pre ram.\\\\0: Open the clock gate only when application writes or reads pre ram\\\\1: Force open the clock gate for pre ram"] + #[inline(always)] + #[must_use] + pub fn pre_ram_clk_en(&mut self) -> PRE_RAM_CLK_EN_W { + PRE_RAM_CLK_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to open the clock gate for mvd ram.\\\\0: Open the clock gate only when application writes or reads mvd ram\\\\1: Force open the clock gate for mvd ram"] + #[inline(always)] + #[must_use] + pub fn mvd_ram_clk_en(&mut self) -> MVD_RAM_CLK_EN_W { + MVD_RAM_CLK_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to open the clock gate for mc ram.\\\\0: Open the clock gate only when application writes or reads mc ram\\\\1: Force open the clock gate for mc ram"] + #[inline(always)] + #[must_use] + pub fn mc_ram_clk_en(&mut self) -> MC_RAM_CLK_EN_W { + MC_RAM_CLK_EN_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to open the clock gate for ref ram.\\\\0: Open the clock gate only when application writes or reads ref ram\\\\1: Force open the clock gate for ref ram"] + #[inline(always)] + #[must_use] + pub fn ref_ram_clk_en(&mut self) -> REF_RAM_CLK_EN_W { + REF_RAM_CLK_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to open the clock gate for i4x4_mode ram.\\\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\\\1: Force open the clock gate for i4x4_mode ram"] + #[inline(always)] + #[must_use] + pub fn i4x4_ref_ram_clk_en(&mut self) -> I4X4_REF_RAM_CLK_EN_W { + I4X4_REF_RAM_CLK_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to open the clock gate for ime ram.\\\\0: Open the clock gate only when application writes or reads ime ram\\\\1: Force open the clock gate for ime ram"] + #[inline(always)] + #[must_use] + pub fn ime_ram_clk_en(&mut self) -> IME_RAM_CLK_EN_W { + IME_RAM_CLK_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to open the clock gate for fme ram.\\\\0: Open the clock gate only when application writes or readsfme ram\\\\1: Force open the clock gate for fme ram"] + #[inline(always)] + #[must_use] + pub fn fme_ram_clk_en(&mut self) -> FME_RAM_CLK_EN_W { + FME_RAM_CLK_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to open the clock gate for fetch ram.\\\\0: Open the clock gate only when application writes or reads fetch ram\\\\1: Force open the clock gate for fetch ram"] + #[inline(always)] + #[must_use] + pub fn fetch_ram_clk_en(&mut self) -> FETCH_RAM_CLK_EN_W { + FETCH_RAM_CLK_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to open the clock gate for db ram.\\\\0: Open the clock gate only when application writes or reads db ram\\\\1: Force open the clock gate for db ram"] + #[inline(always)] + #[must_use] + pub fn db_ram_clk_en(&mut self) -> DB_RAM_CLK_EN_W { + DB_RAM_CLK_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to open the clock gate for cur_mb ram.\\\\0: Open the clock gate only when application writes or reads cur_mb ram\\\\1: Force open the clock gate for cur_mb ram"] + #[inline(always)] + #[must_use] + pub fn cur_mb_ram_clk_en(&mut self) -> CUR_MB_RAM_CLK_EN_W { + CUR_MB_RAM_CLK_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to open the clock gate for cavlc ram.\\\\0: Open the clock gate only when application writes or reads cavlc ram\\\\1: Force open the clock gate for cavlc ram"] + #[inline(always)] + #[must_use] + pub fn cavlc_ram_clk_en(&mut self) -> CAVLC_RAM_CLK_EN_W { + CAVLC_RAM_CLK_EN_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to open the clock gate for ime.\\\\0: Open the clock gate only when ime work\\\\1: Force open the clock gate for ime"] + #[inline(always)] + #[must_use] + pub fn ime_clk_en(&mut self) -> IME_CLK_EN_W { + IME_CLK_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to open the clock gate for fme.\\\\0: Open the clock gate only when fme work\\\\1: Force open the clock gate for fme"] + #[inline(always)] + #[must_use] + pub fn fme_clk_en(&mut self) -> FME_CLK_EN_W { + FME_CLK_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to open the clock gate for mc.\\\\0: Open the clock gate only when mc work\\\\1: Force open the clock gate for mc"] + #[inline(always)] + #[must_use] + pub fn mc_clk_en(&mut self) -> MC_CLK_EN_W { + MC_CLK_EN_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to open the clock gate for interpolator.\\\\0: Open the clock gate only when interpolator work\\\\1: Force open the clock gate for interpolator"] + #[inline(always)] + #[must_use] + pub fn interpolator_clk_en(&mut self) -> INTERPOLATOR_CLK_EN_W { + INTERPOLATOR_CLK_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to open the clock gate for deblocking filter.\\\\0: Open the clock gate only when deblocking filter work\\\\1: Force open the clock gate for deblocking filter"] + #[inline(always)] + #[must_use] + pub fn db_clk_en(&mut self) -> DB_CLK_EN_W { + DB_CLK_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to open the clock gate for cavlc.\\\\0: Open the clock gate only when cavlc work\\\\1: Force open the clock gate for cavlc"] + #[inline(always)] + #[must_use] + pub fn clavlc_clk_en(&mut self) -> CLAVLC_CLK_EN_W { + CLAVLC_CLK_EN_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to open the clock gate for intra.\\\\0: Open the clock gate only when intra work\\\\1: Force open the clock gate for intra"] + #[inline(always)] + #[must_use] + pub fn intra_clk_en(&mut self) -> INTRA_CLK_EN_W { + INTRA_CLK_EN_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to open the clock gate for decimate.\\\\0: Open the clock gate only when decimate work\\\\1: Force open the clock gate for decimate"] + #[inline(always)] + #[must_use] + pub fn deci_clk_en(&mut self) -> DECI_CLK_EN_W { + DECI_CLK_EN_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to open the clock gate for bs buffer.\\\\0: Open the clock gate only when bs buffer work\\\\1: Force open the clock gate for bs buffer"] + #[inline(always)] + #[must_use] + pub fn bs_clk_en(&mut self) -> BS_CLK_EN_W { + BS_CLK_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to open the clock gate for mv merge.\\\\0: Open the clock gate only when mv merge work\\\\1: Force open the clock gate for mv merge"] + #[inline(always)] + #[must_use] + pub fn mv_merge_clk_en(&mut self) -> MV_MERGE_CLK_EN_W { + MV_MERGE_CLK_EN_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "General configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SPEC; +impl crate::RegisterSpec for CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf::R`](R) reader structure"] +impl crate::Readable for CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"] +impl crate::Writable for CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF to value 0"] +impl crate::Resettable for CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/date.rs b/esp32p4/src/h264/date.rs new file mode 100644 index 0000000000..dfd21bfaff --- /dev/null +++ b/esp32p4/src/h264/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `LEDC_DATE` reader - Configures the version."] +pub type LEDC_DATE_R = crate::FieldReader; +#[doc = "Field `LEDC_DATE` writer - Configures the version."] +pub type LEDC_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Configures the version."] + #[inline(always)] + pub fn ledc_date(&self) -> LEDC_DATE_R { + LEDC_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("ledc_date", &format_args!("{}", self.ledc_date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Configures the version."] + #[inline(always)] + #[must_use] + pub fn ledc_date(&mut self) -> LEDC_DATE_W { + LEDC_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_4240"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_4240; +} diff --git a/esp32p4/src/h264/debug_dma_sel.rs b/esp32p4/src/h264/debug_dma_sel.rs new file mode 100644 index 0000000000..e19629087f --- /dev/null +++ b/esp32p4/src/h264/debug_dma_sel.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DEBUG_DMA_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `DEBUG_DMA_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `DBG_DMA_SEL` reader - Every bit represents a dma in h264"] +pub type DBG_DMA_SEL_R = crate::FieldReader; +#[doc = "Field `DBG_DMA_SEL` writer - Every bit represents a dma in h264"] +pub type DBG_DMA_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Every bit represents a dma in h264"] + #[inline(always)] + pub fn dbg_dma_sel(&self) -> DBG_DMA_SEL_R { + DBG_DMA_SEL_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEBUG_DMA_SEL") + .field( + "dbg_dma_sel", + &format_args!("{}", self.dbg_dma_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Every bit represents a dma in h264"] + #[inline(always)] + #[must_use] + pub fn dbg_dma_sel(&mut self) -> DBG_DMA_SEL_W { + DBG_DMA_SEL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Debug H264 DMA select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_dma_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug_dma_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEBUG_DMA_SEL_SPEC; +impl crate::RegisterSpec for DEBUG_DMA_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`debug_dma_sel::R`](R) reader structure"] +impl crate::Readable for DEBUG_DMA_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`debug_dma_sel::W`](W) writer structure"] +impl crate::Writable for DEBUG_DMA_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEBUG_DMA_SEL to value 0"] +impl crate::Resettable for DEBUG_DMA_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/debug_info0.rs b/esp32p4/src/h264/debug_info0.rs new file mode 100644 index 0000000000..76e0aa7323 --- /dev/null +++ b/esp32p4/src/h264/debug_info0.rs @@ -0,0 +1,127 @@ +#[doc = "Register `DEBUG_INFO0` reader"] +pub type R = crate::R; +#[doc = "Field `TOP_CTRL_INTER_DEBUG_STATE` reader - Represents top_ctrl_inter module FSM info."] +pub type TOP_CTRL_INTER_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `TOP_CTRL_INTRA_DEBUG_STATE` reader - Represents top_ctrl_intra module FSM info."] +pub type TOP_CTRL_INTRA_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `P_I_CMP_DEBUG_STATE` reader - Represents p_i_cmp module FSM info."] +pub type P_I_CMP_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `MVD_DEBUG_STATE` reader - Represents mvd module FSM info."] +pub type MVD_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `MC_CHROMA_IP_DEBUG_STATE` reader - Represents mc_chroma_ip module FSM info."] +pub type MC_CHROMA_IP_DEBUG_STATE_R = crate::BitReader; +#[doc = "Field `INTRA_16X16_CHROMA_CTRL_DEBUG_STATE` reader - Represents intra_16x16_chroma_ctrl module FSM info."] +pub type INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `INTRA_4X4_CTRL_DEBUG_STATE` reader - Represents intra_4x4_ctrl module FSM info."] +pub type INTRA_4X4_CTRL_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `INTRA_TOP_CTRL_DEBUG_STATE` reader - Represents intra_top_ctrl module FSM info."] +pub type INTRA_TOP_CTRL_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `IME_CTRL_DEBUG_STATE` reader - Represents ime_ctrl module FSM info."] +pub type IME_CTRL_DEBUG_STATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Represents top_ctrl_inter module FSM info."] + #[inline(always)] + pub fn top_ctrl_inter_debug_state(&self) -> TOP_CTRL_INTER_DEBUG_STATE_R { + TOP_CTRL_INTER_DEBUG_STATE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Represents top_ctrl_intra module FSM info."] + #[inline(always)] + pub fn top_ctrl_intra_debug_state(&self) -> TOP_CTRL_INTRA_DEBUG_STATE_R { + TOP_CTRL_INTRA_DEBUG_STATE_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bits 7:9 - Represents p_i_cmp module FSM info."] + #[inline(always)] + pub fn p_i_cmp_debug_state(&self) -> P_I_CMP_DEBUG_STATE_R { + P_I_CMP_DEBUG_STATE_R::new(((self.bits >> 7) & 7) as u8) + } + #[doc = "Bits 10:12 - Represents mvd module FSM info."] + #[inline(always)] + pub fn mvd_debug_state(&self) -> MVD_DEBUG_STATE_R { + MVD_DEBUG_STATE_R::new(((self.bits >> 10) & 7) as u8) + } + #[doc = "Bit 13 - Represents mc_chroma_ip module FSM info."] + #[inline(always)] + pub fn mc_chroma_ip_debug_state(&self) -> MC_CHROMA_IP_DEBUG_STATE_R { + MC_CHROMA_IP_DEBUG_STATE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:17 - Represents intra_16x16_chroma_ctrl module FSM info."] + #[inline(always)] + pub fn intra_16x16_chroma_ctrl_debug_state(&self) -> INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_R { + INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_R::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bits 18:21 - Represents intra_4x4_ctrl module FSM info."] + #[inline(always)] + pub fn intra_4x4_ctrl_debug_state(&self) -> INTRA_4X4_CTRL_DEBUG_STATE_R { + INTRA_4X4_CTRL_DEBUG_STATE_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bits 22:24 - Represents intra_top_ctrl module FSM info."] + #[inline(always)] + pub fn intra_top_ctrl_debug_state(&self) -> INTRA_TOP_CTRL_DEBUG_STATE_R { + INTRA_TOP_CTRL_DEBUG_STATE_R::new(((self.bits >> 22) & 7) as u8) + } + #[doc = "Bits 25:27 - Represents ime_ctrl module FSM info."] + #[inline(always)] + pub fn ime_ctrl_debug_state(&self) -> IME_CTRL_DEBUG_STATE_R { + IME_CTRL_DEBUG_STATE_R::new(((self.bits >> 25) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEBUG_INFO0") + .field( + "top_ctrl_inter_debug_state", + &format_args!("{}", self.top_ctrl_inter_debug_state().bits()), + ) + .field( + "top_ctrl_intra_debug_state", + &format_args!("{}", self.top_ctrl_intra_debug_state().bits()), + ) + .field( + "p_i_cmp_debug_state", + &format_args!("{}", self.p_i_cmp_debug_state().bits()), + ) + .field( + "mvd_debug_state", + &format_args!("{}", self.mvd_debug_state().bits()), + ) + .field( + "mc_chroma_ip_debug_state", + &format_args!("{}", self.mc_chroma_ip_debug_state().bit()), + ) + .field( + "intra_16x16_chroma_ctrl_debug_state", + &format_args!("{}", self.intra_16x16_chroma_ctrl_debug_state().bits()), + ) + .field( + "intra_4x4_ctrl_debug_state", + &format_args!("{}", self.intra_4x4_ctrl_debug_state().bits()), + ) + .field( + "intra_top_ctrl_debug_state", + &format_args!("{}", self.intra_top_ctrl_debug_state().bits()), + ) + .field( + "ime_ctrl_debug_state", + &format_args!("{}", self.ime_ctrl_debug_state().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Debug information register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_info0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEBUG_INFO0_SPEC; +impl crate::RegisterSpec for DEBUG_INFO0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`debug_info0::R`](R) reader structure"] +impl crate::Readable for DEBUG_INFO0_SPEC {} +#[doc = "`reset()` method sets DEBUG_INFO0 to value 0"] +impl crate::Resettable for DEBUG_INFO0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/debug_info1.rs b/esp32p4/src/h264/debug_info1.rs new file mode 100644 index 0000000000..28ec7a7063 --- /dev/null +++ b/esp32p4/src/h264/debug_info1.rs @@ -0,0 +1,105 @@ +#[doc = "Register `DEBUG_INFO1` reader"] +pub type R = crate::R; +#[doc = "Field `FME_CTRL_DEBUG_STATE` reader - Represents fme_ctrl module FSM info."] +pub type FME_CTRL_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `DECI_CALC_DEBUG_STATE` reader - Represents deci_calc module's FSM info. DEV use only."] +pub type DECI_CALC_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `DB_DEBUG_STATE` reader - Represents db module FSM info."] +pub type DB_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `CAVLC_ENC_DEBUG_STATE` reader - Represents cavlc module enc FSM info."] +pub type CAVLC_ENC_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `CAVLC_SCAN_DEBUG_STATE` reader - Represents cavlc module scan FSM info."] +pub type CAVLC_SCAN_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `CAVLC_CTRL_DEBUG_STATE` reader - Represents cavlc module ctrl FSM info."] +pub type CAVLC_CTRL_DEBUG_STATE_R = crate::FieldReader; +#[doc = "Field `BS_BUFFER_DEBUG_STATE` reader - Represents bs buffer overflow info."] +pub type BS_BUFFER_DEBUG_STATE_R = crate::BitReader; +impl R { + #[doc = "Bits 0:2 - Represents fme_ctrl module FSM info."] + #[inline(always)] + pub fn fme_ctrl_debug_state(&self) -> FME_CTRL_DEBUG_STATE_R { + FME_CTRL_DEBUG_STATE_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Represents deci_calc module's FSM info. DEV use only."] + #[inline(always)] + pub fn deci_calc_debug_state(&self) -> DECI_CALC_DEBUG_STATE_R { + DECI_CALC_DEBUG_STATE_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bits 5:7 - Represents db module FSM info."] + #[inline(always)] + pub fn db_debug_state(&self) -> DB_DEBUG_STATE_R { + DB_DEBUG_STATE_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bits 8:11 - Represents cavlc module enc FSM info."] + #[inline(always)] + pub fn cavlc_enc_debug_state(&self) -> CAVLC_ENC_DEBUG_STATE_R { + CAVLC_ENC_DEBUG_STATE_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Represents cavlc module scan FSM info."] + #[inline(always)] + pub fn cavlc_scan_debug_state(&self) -> CAVLC_SCAN_DEBUG_STATE_R { + CAVLC_SCAN_DEBUG_STATE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:17 - Represents cavlc module ctrl FSM info."] + #[inline(always)] + pub fn cavlc_ctrl_debug_state(&self) -> CAVLC_CTRL_DEBUG_STATE_R { + CAVLC_CTRL_DEBUG_STATE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - Represents bs buffer overflow info."] + #[inline(always)] + pub fn bs_buffer_debug_state(&self) -> BS_BUFFER_DEBUG_STATE_R { + BS_BUFFER_DEBUG_STATE_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEBUG_INFO1") + .field( + "fme_ctrl_debug_state", + &format_args!("{}", self.fme_ctrl_debug_state().bits()), + ) + .field( + "deci_calc_debug_state", + &format_args!("{}", self.deci_calc_debug_state().bits()), + ) + .field( + "db_debug_state", + &format_args!("{}", self.db_debug_state().bits()), + ) + .field( + "cavlc_enc_debug_state", + &format_args!("{}", self.cavlc_enc_debug_state().bits()), + ) + .field( + "cavlc_scan_debug_state", + &format_args!("{}", self.cavlc_scan_debug_state().bits()), + ) + .field( + "cavlc_ctrl_debug_state", + &format_args!("{}", self.cavlc_ctrl_debug_state().bits()), + ) + .field( + "bs_buffer_debug_state", + &format_args!("{}", self.bs_buffer_debug_state().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Debug information register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_info1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEBUG_INFO1_SPEC; +impl crate::RegisterSpec for DEBUG_INFO1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`debug_info1::R`](R) reader structure"] +impl crate::Readable for DEBUG_INFO1_SPEC {} +#[doc = "`reset()` method sets DEBUG_INFO1 to value 0"] +impl crate::Resettable for DEBUG_INFO1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/debug_info2.rs b/esp32p4/src/h264/debug_info2.rs new file mode 100644 index 0000000000..cf09e39b9b --- /dev/null +++ b/esp32p4/src/h264/debug_info2.rs @@ -0,0 +1,226 @@ +#[doc = "Register `DEBUG_INFO2` reader"] +pub type R = crate::R; +#[doc = "Field `P_RC_DONE_DEBUG_FLAG` reader - Represents p rate ctrl done status.\\\\0: not done\\\\1: done."] +pub type P_RC_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `P_P_I_CMP_DONE_DEBUG_FLAG` reader - Represents p p_i_cmp done status.\\\\0: not done\\\\1: done."] +pub type P_P_I_CMP_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `P_MV_MERGE_DONE_DEBUG_FLAG` reader - Represents p mv merge done status.\\\\0: not done\\\\1: done."] +pub type P_MV_MERGE_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `P_MOVE_ORI_DONE_DEBUG_FLAG` reader - Represents p move origin done status.\\\\0: not done\\\\1: done."] +pub type P_MOVE_ORI_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `P_MC_DONE_DEBUG_FLAG` reader - Represents p mc done status.\\\\0: not done\\\\1: done."] +pub type P_MC_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `P_IME_DONE_DEBUG_FLAG` reader - Represents p ime done status.\\\\0: not done\\\\1: done."] +pub type P_IME_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `P_GET_ORI_DONE_DEBUG_FLAG` reader - Represents p get origin done status.\\\\0: not done\\\\1: done."] +pub type P_GET_ORI_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `P_FME_DONE_DEBUG_FLAG` reader - Represents p fme done status.\\\\0: not done\\\\1: done."] +pub type P_FME_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `P_FETCH_DONE_DEBUG_FLAG` reader - Represents p fetch done status.\\\\0: not done\\\\1: done."] +pub type P_FETCH_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `P_DB_DONE_DEBUG_FLAG` reader - Represents p deblocking done status.\\\\0: not done\\\\1: done."] +pub type P_DB_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `P_BS_BUF_DONE_DEBUG_FLAG` reader - Represents p bitstream buffer done status.\\\\0: not done\\\\1: done."] +pub type P_BS_BUF_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG` reader - Represents dma move 2 ref mb line done status.\\\\0: not done\\\\1: done."] +pub type REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `I_P_I_CMP_DONE_DEBUG_FLAG` reader - Represents I p_i_cmp done status.\\\\0: not done\\\\1: done."] +pub type I_P_I_CMP_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `I_MOVE_ORI_DONE_DEBUG_FLAG` reader - Represents I move origin done status.\\\\0: not done\\\\1: done."] +pub type I_MOVE_ORI_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `I_GET_ORI_DONE_DEBUG_FLAG` reader - Represents I get origin done status.\\\\0: not done\\\\1: done."] +pub type I_GET_ORI_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `I_EC_DONE_DEBUG_FLAG` reader - Represents I encoder done status.\\\\0: not done\\\\1: done."] +pub type I_EC_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `I_DB_DONE_DEBUG_FLAG` reader - Represents I deblocking done status.\\\\0: not done\\\\1: done."] +pub type I_DB_DONE_DEBUG_FLAG_R = crate::BitReader; +#[doc = "Field `I_BS_BUF_DONE_DEBUG_FLAG` reader - Represents I bitstream buffer done status.\\\\0: not done\\\\1: done."] +pub type I_BS_BUF_DONE_DEBUG_FLAG_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Represents p rate ctrl done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn p_rc_done_debug_flag(&self) -> P_RC_DONE_DEBUG_FLAG_R { + P_RC_DONE_DEBUG_FLAG_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents p p_i_cmp done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn p_p_i_cmp_done_debug_flag(&self) -> P_P_I_CMP_DONE_DEBUG_FLAG_R { + P_P_I_CMP_DONE_DEBUG_FLAG_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents p mv merge done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn p_mv_merge_done_debug_flag(&self) -> P_MV_MERGE_DONE_DEBUG_FLAG_R { + P_MV_MERGE_DONE_DEBUG_FLAG_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents p move origin done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn p_move_ori_done_debug_flag(&self) -> P_MOVE_ORI_DONE_DEBUG_FLAG_R { + P_MOVE_ORI_DONE_DEBUG_FLAG_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents p mc done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn p_mc_done_debug_flag(&self) -> P_MC_DONE_DEBUG_FLAG_R { + P_MC_DONE_DEBUG_FLAG_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents p ime done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn p_ime_done_debug_flag(&self) -> P_IME_DONE_DEBUG_FLAG_R { + P_IME_DONE_DEBUG_FLAG_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents p get origin done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn p_get_ori_done_debug_flag(&self) -> P_GET_ORI_DONE_DEBUG_FLAG_R { + P_GET_ORI_DONE_DEBUG_FLAG_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents p fme done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn p_fme_done_debug_flag(&self) -> P_FME_DONE_DEBUG_FLAG_R { + P_FME_DONE_DEBUG_FLAG_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents p fetch done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn p_fetch_done_debug_flag(&self) -> P_FETCH_DONE_DEBUG_FLAG_R { + P_FETCH_DONE_DEBUG_FLAG_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents p deblocking done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn p_db_done_debug_flag(&self) -> P_DB_DONE_DEBUG_FLAG_R { + P_DB_DONE_DEBUG_FLAG_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents p bitstream buffer done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn p_bs_buf_done_debug_flag(&self) -> P_BS_BUF_DONE_DEBUG_FLAG_R { + P_BS_BUF_DONE_DEBUG_FLAG_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents dma move 2 ref mb line done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn ref_move_2mb_line_done_debug_flag(&self) -> REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_R { + REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents I p_i_cmp done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn i_p_i_cmp_done_debug_flag(&self) -> I_P_I_CMP_DONE_DEBUG_FLAG_R { + I_P_I_CMP_DONE_DEBUG_FLAG_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents I move origin done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn i_move_ori_done_debug_flag(&self) -> I_MOVE_ORI_DONE_DEBUG_FLAG_R { + I_MOVE_ORI_DONE_DEBUG_FLAG_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents I get origin done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn i_get_ori_done_debug_flag(&self) -> I_GET_ORI_DONE_DEBUG_FLAG_R { + I_GET_ORI_DONE_DEBUG_FLAG_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents I encoder done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn i_ec_done_debug_flag(&self) -> I_EC_DONE_DEBUG_FLAG_R { + I_EC_DONE_DEBUG_FLAG_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents I deblocking done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn i_db_done_debug_flag(&self) -> I_DB_DONE_DEBUG_FLAG_R { + I_DB_DONE_DEBUG_FLAG_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents I bitstream buffer done status.\\\\0: not done\\\\1: done."] + #[inline(always)] + pub fn i_bs_buf_done_debug_flag(&self) -> I_BS_BUF_DONE_DEBUG_FLAG_R { + I_BS_BUF_DONE_DEBUG_FLAG_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEBUG_INFO2") + .field( + "p_rc_done_debug_flag", + &format_args!("{}", self.p_rc_done_debug_flag().bit()), + ) + .field( + "p_p_i_cmp_done_debug_flag", + &format_args!("{}", self.p_p_i_cmp_done_debug_flag().bit()), + ) + .field( + "p_mv_merge_done_debug_flag", + &format_args!("{}", self.p_mv_merge_done_debug_flag().bit()), + ) + .field( + "p_move_ori_done_debug_flag", + &format_args!("{}", self.p_move_ori_done_debug_flag().bit()), + ) + .field( + "p_mc_done_debug_flag", + &format_args!("{}", self.p_mc_done_debug_flag().bit()), + ) + .field( + "p_ime_done_debug_flag", + &format_args!("{}", self.p_ime_done_debug_flag().bit()), + ) + .field( + "p_get_ori_done_debug_flag", + &format_args!("{}", self.p_get_ori_done_debug_flag().bit()), + ) + .field( + "p_fme_done_debug_flag", + &format_args!("{}", self.p_fme_done_debug_flag().bit()), + ) + .field( + "p_fetch_done_debug_flag", + &format_args!("{}", self.p_fetch_done_debug_flag().bit()), + ) + .field( + "p_db_done_debug_flag", + &format_args!("{}", self.p_db_done_debug_flag().bit()), + ) + .field( + "p_bs_buf_done_debug_flag", + &format_args!("{}", self.p_bs_buf_done_debug_flag().bit()), + ) + .field( + "ref_move_2mb_line_done_debug_flag", + &format_args!("{}", self.ref_move_2mb_line_done_debug_flag().bit()), + ) + .field( + "i_p_i_cmp_done_debug_flag", + &format_args!("{}", self.i_p_i_cmp_done_debug_flag().bit()), + ) + .field( + "i_move_ori_done_debug_flag", + &format_args!("{}", self.i_move_ori_done_debug_flag().bit()), + ) + .field( + "i_get_ori_done_debug_flag", + &format_args!("{}", self.i_get_ori_done_debug_flag().bit()), + ) + .field( + "i_ec_done_debug_flag", + &format_args!("{}", self.i_ec_done_debug_flag().bit()), + ) + .field( + "i_db_done_debug_flag", + &format_args!("{}", self.i_db_done_debug_flag().bit()), + ) + .field( + "i_bs_buf_done_debug_flag", + &format_args!("{}", self.i_bs_buf_done_debug_flag().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Debug information register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_info2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEBUG_INFO2_SPEC; +impl crate::RegisterSpec for DEBUG_INFO2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`debug_info2::R`](R) reader structure"] +impl crate::Readable for DEBUG_INFO2_SPEC {} +#[doc = "`reset()` method sets DEBUG_INFO2 to value 0"] +impl crate::Resettable for DEBUG_INFO2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/frame_code_length.rs b/esp32p4/src/h264/frame_code_length.rs new file mode 100644 index 0000000000..fdcba32f85 --- /dev/null +++ b/esp32p4/src/h264/frame_code_length.rs @@ -0,0 +1,39 @@ +#[doc = "Register `FRAME_CODE_LENGTH` reader"] +pub type R = crate::R; +#[doc = "Field `FRAME_CODE_LENGTH` reader - Represents current frame code byte length."] +pub type FRAME_CODE_LENGTH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - Represents current frame code byte length."] + #[inline(always)] + pub fn frame_code_length(&self) -> FRAME_CODE_LENGTH_R { + FRAME_CODE_LENGTH_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FRAME_CODE_LENGTH") + .field( + "frame_code_length", + &format_args!("{}", self.frame_code_length().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Frame code byte length register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frame_code_length::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FRAME_CODE_LENGTH_SPEC; +impl crate::RegisterSpec for FRAME_CODE_LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`frame_code_length::R`](R) reader structure"] +impl crate::Readable for FRAME_CODE_LENGTH_SPEC {} +#[doc = "`reset()` method sets FRAME_CODE_LENGTH to value 0"] +impl crate::Resettable for FRAME_CODE_LENGTH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/gop_conf.rs b/esp32p4/src/h264/gop_conf.rs new file mode 100644 index 0000000000..67999729be --- /dev/null +++ b/esp32p4/src/h264/gop_conf.rs @@ -0,0 +1,82 @@ +#[doc = "Register `GOP_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `GOP_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `DUAL_STREAM_MODE` reader - Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\\\0: Normal mode\\\\1: Dual stream mode"] +pub type DUAL_STREAM_MODE_R = crate::BitReader; +#[doc = "Field `DUAL_STREAM_MODE` writer - Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\\\0: Normal mode\\\\1: Dual stream mode"] +pub type DUAL_STREAM_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GOP_NUM` reader - Configures the frame number of one GOP.\\\\0: The frame number of one GOP is infinite\\\\Others: Actual frame number of one GOP"] +pub type GOP_NUM_R = crate::FieldReader; +#[doc = "Field `GOP_NUM` writer - Configures the frame number of one GOP.\\\\0: The frame number of one GOP is infinite\\\\Others: Actual frame number of one GOP"] +pub type GOP_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\\\0: Normal mode\\\\1: Dual stream mode"] + #[inline(always)] + pub fn dual_stream_mode(&self) -> DUAL_STREAM_MODE_R { + DUAL_STREAM_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:8 - Configures the frame number of one GOP.\\\\0: The frame number of one GOP is infinite\\\\Others: Actual frame number of one GOP"] + #[inline(always)] + pub fn gop_num(&self) -> GOP_NUM_R { + GOP_NUM_R::new(((self.bits >> 1) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GOP_CONF") + .field( + "dual_stream_mode", + &format_args!("{}", self.dual_stream_mode().bit()), + ) + .field("gop_num", &format_args!("{}", self.gop_num().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\\\0: Normal mode\\\\1: Dual stream mode"] + #[inline(always)] + #[must_use] + pub fn dual_stream_mode(&mut self) -> DUAL_STREAM_MODE_W { + DUAL_STREAM_MODE_W::new(self, 0) + } + #[doc = "Bits 1:8 - Configures the frame number of one GOP.\\\\0: The frame number of one GOP is infinite\\\\Others: Actual frame number of one GOP"] + #[inline(always)] + #[must_use] + pub fn gop_num(&mut self) -> GOP_NUM_W { + GOP_NUM_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "GOP related configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gop_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gop_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GOP_CONF_SPEC; +impl crate::RegisterSpec for GOP_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gop_conf::R`](R) reader structure"] +impl crate::Readable for GOP_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gop_conf::W`](W) writer structure"] +impl crate::Writable for GOP_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GOP_CONF to value 0"] +impl crate::Resettable for GOP_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/int_clr.rs b/esp32p4/src/h264/int_clr.rs new file mode 100644 index 0000000000..c43ab3f2f5 --- /dev/null +++ b/esp32p4/src/h264/int_clr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DB_TMP_READY_INT_CLR` writer - Write 1 to clear H264_DB_TMP_READY_INT."] +pub type DB_TMP_READY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REC_READY_INT_CLR` writer - Write 1 to clear H264_REC_READY_INT."] +pub type REC_READY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRAME_DONE_INT_CLR` writer - Write 1 to clear H264_FRAME_DONE_INT."] +pub type FRAME_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_MOVE_2MB_LINE_DONE_INT_CLR` writer - Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT."] +pub type DMA_MOVE_2MB_LINE_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to clear H264_DB_TMP_READY_INT."] + #[inline(always)] + #[must_use] + pub fn db_tmp_ready_int_clr(&mut self) -> DB_TMP_READY_INT_CLR_W { + DB_TMP_READY_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to clear H264_REC_READY_INT."] + #[inline(always)] + #[must_use] + pub fn rec_ready_int_clr(&mut self) -> REC_READY_INT_CLR_W { + REC_READY_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to clear H264_FRAME_DONE_INT."] + #[inline(always)] + #[must_use] + pub fn frame_done_int_clr(&mut self) -> FRAME_DONE_INT_CLR_W { + FRAME_DONE_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT."] + #[inline(always)] + #[must_use] + pub fn dma_move_2mb_line_done_int_clr( + &mut self, + ) -> DMA_MOVE_2MB_LINE_DONE_INT_CLR_W { + DMA_MOVE_2MB_LINE_DONE_INT_CLR_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/int_ena.rs b/esp32p4/src/h264/int_ena.rs new file mode 100644 index 0000000000..13821ef1f6 --- /dev/null +++ b/esp32p4/src/h264/int_ena.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `DB_TMP_READY_INT_ENA` reader - Write 1 to enable H264_DB_TMP_READY_INT."] +pub type DB_TMP_READY_INT_ENA_R = crate::BitReader; +#[doc = "Field `DB_TMP_READY_INT_ENA` writer - Write 1 to enable H264_DB_TMP_READY_INT."] +pub type DB_TMP_READY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REC_READY_INT_ENA` reader - Write 1 to enable H264_REC_READY_INT."] +pub type REC_READY_INT_ENA_R = crate::BitReader; +#[doc = "Field `REC_READY_INT_ENA` writer - Write 1 to enable H264_REC_READY_INT."] +pub type REC_READY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRAME_DONE_INT_ENA` reader - Write 1 to enable H264_FRAME_DONE_INT."] +pub type FRAME_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `FRAME_DONE_INT_ENA` writer - Write 1 to enable H264_FRAME_DONE_INT."] +pub type FRAME_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_MOVE_2MB_LINE_DONE_INT_ENA` reader - Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT."] +pub type DMA_MOVE_2MB_LINE_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `DMA_MOVE_2MB_LINE_DONE_INT_ENA` writer - Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT."] +pub type DMA_MOVE_2MB_LINE_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 to enable H264_DB_TMP_READY_INT."] + #[inline(always)] + pub fn db_tmp_ready_int_ena(&self) -> DB_TMP_READY_INT_ENA_R { + DB_TMP_READY_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to enable H264_REC_READY_INT."] + #[inline(always)] + pub fn rec_ready_int_ena(&self) -> REC_READY_INT_ENA_R { + REC_READY_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 to enable H264_FRAME_DONE_INT."] + #[inline(always)] + pub fn frame_done_int_ena(&self) -> FRAME_DONE_INT_ENA_R { + FRAME_DONE_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT."] + #[inline(always)] + pub fn dma_move_2mb_line_done_int_ena(&self) -> DMA_MOVE_2MB_LINE_DONE_INT_ENA_R { + DMA_MOVE_2MB_LINE_DONE_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "db_tmp_ready_int_ena", + &format_args!("{}", self.db_tmp_ready_int_ena().bit()), + ) + .field( + "rec_ready_int_ena", + &format_args!("{}", self.rec_ready_int_ena().bit()), + ) + .field( + "frame_done_int_ena", + &format_args!("{}", self.frame_done_int_ena().bit()), + ) + .field( + "dma_move_2mb_line_done_int_ena", + &format_args!("{}", self.dma_move_2mb_line_done_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to enable H264_DB_TMP_READY_INT."] + #[inline(always)] + #[must_use] + pub fn db_tmp_ready_int_ena(&mut self) -> DB_TMP_READY_INT_ENA_W { + DB_TMP_READY_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to enable H264_REC_READY_INT."] + #[inline(always)] + #[must_use] + pub fn rec_ready_int_ena(&mut self) -> REC_READY_INT_ENA_W { + REC_READY_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to enable H264_FRAME_DONE_INT."] + #[inline(always)] + #[must_use] + pub fn frame_done_int_ena(&mut self) -> FRAME_DONE_INT_ENA_W { + FRAME_DONE_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT."] + #[inline(always)] + #[must_use] + pub fn dma_move_2mb_line_done_int_ena( + &mut self, + ) -> DMA_MOVE_2MB_LINE_DONE_INT_ENA_W { + DMA_MOVE_2MB_LINE_DONE_INT_ENA_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/int_raw.rs b/esp32p4/src/h264/int_raw.rs new file mode 100644 index 0000000000..9e91a72357 --- /dev/null +++ b/esp32p4/src/h264/int_raw.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `DB_TMP_READY_INT_RAW` reader - Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel."] +pub type DB_TMP_READY_INT_RAW_R = crate::BitReader; +#[doc = "Field `DB_TMP_READY_INT_RAW` writer - Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel."] +pub type DB_TMP_READY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REC_READY_INT_RAW` reader - Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when H264 encoding enough reconstruct pixel."] +pub type REC_READY_INT_RAW_R = crate::BitReader; +#[doc = "Field `REC_READY_INT_RAW` writer - Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when H264 encoding enough reconstruct pixel."] +pub type REC_READY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRAME_DONE_INT_RAW` reader - Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when H264 encoding one frame done."] +pub type FRAME_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `FRAME_DONE_INT_RAW` writer - Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when H264 encoding one frame done."] +pub type FRAME_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_MOVE_2MB_LINE_DONE_INT_RAW` reader - Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Triggered when H264 move two MB lines of reference frame from external mem to internal mem done."] +pub type DMA_MOVE_2MB_LINE_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `DMA_MOVE_2MB_LINE_DONE_INT_RAW` writer - Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Triggered when H264 move two MB lines of reference frame from external mem to internal mem done."] +pub type DMA_MOVE_2MB_LINE_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel."] + #[inline(always)] + pub fn db_tmp_ready_int_raw(&self) -> DB_TMP_READY_INT_RAW_R { + DB_TMP_READY_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when H264 encoding enough reconstruct pixel."] + #[inline(always)] + pub fn rec_ready_int_raw(&self) -> REC_READY_INT_RAW_R { + REC_READY_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when H264 encoding one frame done."] + #[inline(always)] + pub fn frame_done_int_raw(&self) -> FRAME_DONE_INT_RAW_R { + FRAME_DONE_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Triggered when H264 move two MB lines of reference frame from external mem to internal mem done."] + #[inline(always)] + pub fn dma_move_2mb_line_done_int_raw(&self) -> DMA_MOVE_2MB_LINE_DONE_INT_RAW_R { + DMA_MOVE_2MB_LINE_DONE_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "db_tmp_ready_int_raw", + &format_args!("{}", self.db_tmp_ready_int_raw().bit()), + ) + .field( + "rec_ready_int_raw", + &format_args!("{}", self.rec_ready_int_raw().bit()), + ) + .field( + "frame_done_int_raw", + &format_args!("{}", self.frame_done_int_raw().bit()), + ) + .field( + "dma_move_2mb_line_done_int_raw", + &format_args!("{}", self.dma_move_2mb_line_done_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel."] + #[inline(always)] + #[must_use] + pub fn db_tmp_ready_int_raw(&mut self) -> DB_TMP_READY_INT_RAW_W { + DB_TMP_READY_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when H264 encoding enough reconstruct pixel."] + #[inline(always)] + #[must_use] + pub fn rec_ready_int_raw(&mut self) -> REC_READY_INT_RAW_W { + REC_READY_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when H264 encoding one frame done."] + #[inline(always)] + #[must_use] + pub fn frame_done_int_raw(&mut self) -> FRAME_DONE_INT_RAW_W { + FRAME_DONE_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Triggered when H264 move two MB lines of reference frame from external mem to internal mem done."] + #[inline(always)] + #[must_use] + pub fn dma_move_2mb_line_done_int_raw( + &mut self, + ) -> DMA_MOVE_2MB_LINE_DONE_INT_RAW_W { + DMA_MOVE_2MB_LINE_DONE_INT_RAW_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/int_st.rs b/esp32p4/src/h264/int_st.rs new file mode 100644 index 0000000000..a806ba3b13 --- /dev/null +++ b/esp32p4/src/h264/int_st.rs @@ -0,0 +1,72 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `DB_TMP_READY_INT_ST` reader - The masked interrupt status of H264_DB_TMP_READY_INT. Valid only when the H264_DB_TMP_READY_INT_ENA is set to 1."] +pub type DB_TMP_READY_INT_ST_R = crate::BitReader; +#[doc = "Field `REC_READY_INT_ST` reader - The masked interrupt status of H264_REC_READY_INT. Valid only when the H264_REC_READY_INT_ENA is set to 1."] +pub type REC_READY_INT_ST_R = crate::BitReader; +#[doc = "Field `FRAME_DONE_INT_ST` reader - The masked interrupt status of H264_FRAME_DONE_INT. Valid only when the H264_FRAME_DONE_INT_ENA is set to 1."] +pub type FRAME_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `DMA_MOVE_2MB_LINE_DONE_INT_ST` reader - Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1."] +pub type DMA_MOVE_2MB_LINE_DONE_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status of H264_DB_TMP_READY_INT. Valid only when the H264_DB_TMP_READY_INT_ENA is set to 1."] + #[inline(always)] + pub fn db_tmp_ready_int_st(&self) -> DB_TMP_READY_INT_ST_R { + DB_TMP_READY_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status of H264_REC_READY_INT. Valid only when the H264_REC_READY_INT_ENA is set to 1."] + #[inline(always)] + pub fn rec_ready_int_st(&self) -> REC_READY_INT_ST_R { + REC_READY_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status of H264_FRAME_DONE_INT. Valid only when the H264_FRAME_DONE_INT_ENA is set to 1."] + #[inline(always)] + pub fn frame_done_int_st(&self) -> FRAME_DONE_INT_ST_R { + FRAME_DONE_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1."] + #[inline(always)] + pub fn dma_move_2mb_line_done_int_st(&self) -> DMA_MOVE_2MB_LINE_DONE_INT_ST_R { + DMA_MOVE_2MB_LINE_DONE_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "db_tmp_ready_int_st", + &format_args!("{}", self.db_tmp_ready_int_st().bit()), + ) + .field( + "rec_ready_int_st", + &format_args!("{}", self.rec_ready_int_st().bit()), + ) + .field( + "frame_done_int_st", + &format_args!("{}", self.frame_done_int_st().bit()), + ) + .field( + "dma_move_2mb_line_done_int_st", + &format_args!("{}", self.dma_move_2mb_line_done_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Interrupt masked status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/mv_merge_config.rs b/esp32p4/src/h264/mv_merge_config.rs new file mode 100644 index 0000000000..8a85681475 --- /dev/null +++ b/esp32p4/src/h264/mv_merge_config.rs @@ -0,0 +1,134 @@ +#[doc = "Register `MV_MERGE_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `MV_MERGE_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `MV_MERGE_TYPE` reader - Configure mv merge type.\\\\0: merge p16x16 mv\\\\1: merge min mv\\\\2: merge max mv\\\\3: not valid."] +pub type MV_MERGE_TYPE_R = crate::FieldReader; +#[doc = "Field `MV_MERGE_TYPE` writer - Configure mv merge type.\\\\0: merge p16x16 mv\\\\1: merge min mv\\\\2: merge max mv\\\\3: not valid."] +pub type MV_MERGE_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `INT_MV_OUT_EN` reader - Configure mv merge output integer part not zero mv or all part not zero mv.\\\\0: output all part not zero mv\\\\1: output integer part not zero mv."] +pub type INT_MV_OUT_EN_R = crate::BitReader; +#[doc = "Field `INT_MV_OUT_EN` writer - Configure mv merge output integer part not zero mv or all part not zero mv.\\\\0: output all part not zero mv\\\\1: output integer part not zero mv."] +pub type INT_MV_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_MV_MERGE_EN` reader - Configure whether or not to enable video A mv merge.\\\\0: disable\\\\1: enable."] +pub type A_MV_MERGE_EN_R = crate::BitReader; +#[doc = "Field `A_MV_MERGE_EN` writer - Configure whether or not to enable video A mv merge.\\\\0: disable\\\\1: enable."] +pub type A_MV_MERGE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_MV_MERGE_EN` reader - Configure whether or not to enable video B mv merge.\\\\0: disable\\\\1: enable."] +pub type B_MV_MERGE_EN_R = crate::BitReader; +#[doc = "Field `B_MV_MERGE_EN` writer - Configure whether or not to enable video B mv merge.\\\\0: disable\\\\1: enable."] +pub type B_MV_MERGE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MB_VALID_NUM` reader - Represents the valid mb number of mv merge output."] +pub type MB_VALID_NUM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Configure mv merge type.\\\\0: merge p16x16 mv\\\\1: merge min mv\\\\2: merge max mv\\\\3: not valid."] + #[inline(always)] + pub fn mv_merge_type(&self) -> MV_MERGE_TYPE_R { + MV_MERGE_TYPE_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Configure mv merge output integer part not zero mv or all part not zero mv.\\\\0: output all part not zero mv\\\\1: output integer part not zero mv."] + #[inline(always)] + pub fn int_mv_out_en(&self) -> INT_MV_OUT_EN_R { + INT_MV_OUT_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configure whether or not to enable video A mv merge.\\\\0: disable\\\\1: enable."] + #[inline(always)] + pub fn a_mv_merge_en(&self) -> A_MV_MERGE_EN_R { + A_MV_MERGE_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configure whether or not to enable video B mv merge.\\\\0: disable\\\\1: enable."] + #[inline(always)] + pub fn b_mv_merge_en(&self) -> B_MV_MERGE_EN_R { + B_MV_MERGE_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:17 - Represents the valid mb number of mv merge output."] + #[inline(always)] + pub fn mb_valid_num(&self) -> MB_VALID_NUM_R { + MB_VALID_NUM_R::new(((self.bits >> 5) & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MV_MERGE_CONFIG") + .field( + "mv_merge_type", + &format_args!("{}", self.mv_merge_type().bits()), + ) + .field( + "int_mv_out_en", + &format_args!("{}", self.int_mv_out_en().bit()), + ) + .field( + "a_mv_merge_en", + &format_args!("{}", self.a_mv_merge_en().bit()), + ) + .field( + "b_mv_merge_en", + &format_args!("{}", self.b_mv_merge_en().bit()), + ) + .field( + "mb_valid_num", + &format_args!("{}", self.mb_valid_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Configure mv merge type.\\\\0: merge p16x16 mv\\\\1: merge min mv\\\\2: merge max mv\\\\3: not valid."] + #[inline(always)] + #[must_use] + pub fn mv_merge_type(&mut self) -> MV_MERGE_TYPE_W { + MV_MERGE_TYPE_W::new(self, 0) + } + #[doc = "Bit 2 - Configure mv merge output integer part not zero mv or all part not zero mv.\\\\0: output all part not zero mv\\\\1: output integer part not zero mv."] + #[inline(always)] + #[must_use] + pub fn int_mv_out_en(&mut self) -> INT_MV_OUT_EN_W { + INT_MV_OUT_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Configure whether or not to enable video A mv merge.\\\\0: disable\\\\1: enable."] + #[inline(always)] + #[must_use] + pub fn a_mv_merge_en(&mut self) -> A_MV_MERGE_EN_W { + A_MV_MERGE_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Configure whether or not to enable video B mv merge.\\\\0: disable\\\\1: enable."] + #[inline(always)] + #[must_use] + pub fn b_mv_merge_en(&mut self) -> B_MV_MERGE_EN_W { + B_MV_MERGE_EN_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Mv merge configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mv_merge_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mv_merge_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MV_MERGE_CONFIG_SPEC; +impl crate::RegisterSpec for MV_MERGE_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mv_merge_config::R`](R) reader structure"] +impl crate::Readable for MV_MERGE_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mv_merge_config::W`](W) writer structure"] +impl crate::Writable for MV_MERGE_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MV_MERGE_CONFIG to value 0"] +impl crate::Resettable for MV_MERGE_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/rc_status0.rs b/esp32p4/src/h264/rc_status0.rs new file mode 100644 index 0000000000..4ab11a673c --- /dev/null +++ b/esp32p4/src/h264/rc_status0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RC_STATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `FRAME_MAD_SUM` reader - Represents all MB actual MAD sum value of one frame."] +pub type FRAME_MAD_SUM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:20 - Represents all MB actual MAD sum value of one frame."] + #[inline(always)] + pub fn frame_mad_sum(&self) -> FRAME_MAD_SUM_R { + FRAME_MAD_SUM_R::new(self.bits & 0x001f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RC_STATUS0") + .field( + "frame_mad_sum", + &format_args!("{}", self.frame_mad_sum().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Rate control status register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc_status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RC_STATUS0_SPEC; +impl crate::RegisterSpec for RC_STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rc_status0::R`](R) reader structure"] +impl crate::Readable for RC_STATUS0_SPEC {} +#[doc = "`reset()` method sets RC_STATUS0 to value 0"] +impl crate::Resettable for RC_STATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/rc_status1.rs b/esp32p4/src/h264/rc_status1.rs new file mode 100644 index 0000000000..1f0fe5cb3e --- /dev/null +++ b/esp32p4/src/h264/rc_status1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RC_STATUS1` reader"] +pub type R = crate::R; +#[doc = "Field `FRAME_ENC_BITS` reader - Represents all MB actual encoding bits sum value of one frame."] +pub type FRAME_ENC_BITS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:26 - Represents all MB actual encoding bits sum value of one frame."] + #[inline(always)] + pub fn frame_enc_bits(&self) -> FRAME_ENC_BITS_R { + FRAME_ENC_BITS_R::new(self.bits & 0x07ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RC_STATUS1") + .field( + "frame_enc_bits", + &format_args!("{}", self.frame_enc_bits().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Rate control status register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc_status1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RC_STATUS1_SPEC; +impl crate::RegisterSpec for RC_STATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rc_status1::R`](R) reader structure"] +impl crate::Readable for RC_STATUS1_SPEC {} +#[doc = "`reset()` method sets RC_STATUS1 to value 0"] +impl crate::Resettable for RC_STATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/rc_status2.rs b/esp32p4/src/h264/rc_status2.rs new file mode 100644 index 0000000000..0639e98663 --- /dev/null +++ b/esp32p4/src/h264/rc_status2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RC_STATUS2` reader"] +pub type R = crate::R; +#[doc = "Field `FRAME_QP_SUM` reader - Represents all MB actual luma QP sum value of one frame."] +pub type FRAME_QP_SUM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:18 - Represents all MB actual luma QP sum value of one frame."] + #[inline(always)] + pub fn frame_qp_sum(&self) -> FRAME_QP_SUM_R { + FRAME_QP_SUM_R::new(self.bits & 0x0007_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RC_STATUS2") + .field( + "frame_qp_sum", + &format_args!("{}", self.frame_qp_sum().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Rate control status register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc_status2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RC_STATUS2_SPEC; +impl crate::RegisterSpec for RC_STATUS2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rc_status2::R`](R) reader structure"] +impl crate::Readable for RC_STATUS2_SPEC {} +#[doc = "`reset()` method sets RC_STATUS2 to value 0"] +impl crate::Resettable for RC_STATUS2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/slice_header_byte0.rs b/esp32p4/src/h264/slice_header_byte0.rs new file mode 100644 index 0000000000..e6bec5c3b3 --- /dev/null +++ b/esp32p4/src/h264/slice_header_byte0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SLICE_HEADER_BYTE0` reader"] +pub type R = crate::R; +#[doc = "Register `SLICE_HEADER_BYTE0` writer"] +pub type W = crate::W; +#[doc = "Field `SLICE_BYTE_LSB` reader - Configures Slice Header low 32 bit"] +pub type SLICE_BYTE_LSB_R = crate::FieldReader; +#[doc = "Field `SLICE_BYTE_LSB` writer - Configures Slice Header low 32 bit"] +pub type SLICE_BYTE_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures Slice Header low 32 bit"] + #[inline(always)] + pub fn slice_byte_lsb(&self) -> SLICE_BYTE_LSB_R { + SLICE_BYTE_LSB_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLICE_HEADER_BYTE0") + .field( + "slice_byte_lsb", + &format_args!("{}", self.slice_byte_lsb().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures Slice Header low 32 bit"] + #[inline(always)] + #[must_use] + pub fn slice_byte_lsb(&mut self) -> SLICE_BYTE_LSB_W { + SLICE_BYTE_LSB_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Frame Slice Header byte low 32 bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slice_header_byte0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slice_header_byte0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLICE_HEADER_BYTE0_SPEC; +impl crate::RegisterSpec for SLICE_HEADER_BYTE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slice_header_byte0::R`](R) reader structure"] +impl crate::Readable for SLICE_HEADER_BYTE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slice_header_byte0::W`](W) writer structure"] +impl crate::Writable for SLICE_HEADER_BYTE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLICE_HEADER_BYTE0 to value 0"] +impl crate::Resettable for SLICE_HEADER_BYTE0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/slice_header_byte1.rs b/esp32p4/src/h264/slice_header_byte1.rs new file mode 100644 index 0000000000..469c9fa03a --- /dev/null +++ b/esp32p4/src/h264/slice_header_byte1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SLICE_HEADER_BYTE1` reader"] +pub type R = crate::R; +#[doc = "Register `SLICE_HEADER_BYTE1` writer"] +pub type W = crate::W; +#[doc = "Field `SLICE_BYTE_MSB` reader - Configures Slice Header high 32 bit"] +pub type SLICE_BYTE_MSB_R = crate::FieldReader; +#[doc = "Field `SLICE_BYTE_MSB` writer - Configures Slice Header high 32 bit"] +pub type SLICE_BYTE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures Slice Header high 32 bit"] + #[inline(always)] + pub fn slice_byte_msb(&self) -> SLICE_BYTE_MSB_R { + SLICE_BYTE_MSB_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLICE_HEADER_BYTE1") + .field( + "slice_byte_msb", + &format_args!("{}", self.slice_byte_msb().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures Slice Header high 32 bit"] + #[inline(always)] + #[must_use] + pub fn slice_byte_msb(&mut self) -> SLICE_BYTE_MSB_W { + SLICE_BYTE_MSB_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Frame Slice Header byte high 32 bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slice_header_byte1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slice_header_byte1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLICE_HEADER_BYTE1_SPEC; +impl crate::RegisterSpec for SLICE_HEADER_BYTE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slice_header_byte1::R`](R) reader structure"] +impl crate::Readable for SLICE_HEADER_BYTE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slice_header_byte1::W`](W) writer structure"] +impl crate::Writable for SLICE_HEADER_BYTE1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLICE_HEADER_BYTE1 to value 0"] +impl crate::Resettable for SLICE_HEADER_BYTE1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/slice_header_byte_length.rs b/esp32p4/src/h264/slice_header_byte_length.rs new file mode 100644 index 0000000000..fa49685cc9 --- /dev/null +++ b/esp32p4/src/h264/slice_header_byte_length.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SLICE_HEADER_BYTE_LENGTH` reader"] +pub type R = crate::R; +#[doc = "Register `SLICE_HEADER_BYTE_LENGTH` writer"] +pub type W = crate::W; +#[doc = "Field `SLICE_BYTE_LENGTH` reader - Configures Slice Header byte number"] +pub type SLICE_BYTE_LENGTH_R = crate::FieldReader; +#[doc = "Field `SLICE_BYTE_LENGTH` writer - Configures Slice Header byte number"] +pub type SLICE_BYTE_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Configures Slice Header byte number"] + #[inline(always)] + pub fn slice_byte_length(&self) -> SLICE_BYTE_LENGTH_R { + SLICE_BYTE_LENGTH_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLICE_HEADER_BYTE_LENGTH") + .field( + "slice_byte_length", + &format_args!("{}", self.slice_byte_length().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Configures Slice Header byte number"] + #[inline(always)] + #[must_use] + pub fn slice_byte_length(&mut self) -> SLICE_BYTE_LENGTH_W { + SLICE_BYTE_LENGTH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Frame Slice Header byte length register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slice_header_byte_length::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slice_header_byte_length::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLICE_HEADER_BYTE_LENGTH_SPEC; +impl crate::RegisterSpec for SLICE_HEADER_BYTE_LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slice_header_byte_length::R`](R) reader structure"] +impl crate::Readable for SLICE_HEADER_BYTE_LENGTH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slice_header_byte_length::W`](W) writer structure"] +impl crate::Writable for SLICE_HEADER_BYTE_LENGTH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLICE_HEADER_BYTE_LENGTH to value 0"] +impl crate::Resettable for SLICE_HEADER_BYTE_LENGTH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/slice_header_remain.rs b/esp32p4/src/h264/slice_header_remain.rs new file mode 100644 index 0000000000..d4b68560b8 --- /dev/null +++ b/esp32p4/src/h264/slice_header_remain.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SLICE_HEADER_REMAIN` reader"] +pub type R = crate::R; +#[doc = "Register `SLICE_HEADER_REMAIN` writer"] +pub type W = crate::W; +#[doc = "Field `SLICE_REMAIN_BITLENGTH` reader - Configures Slice Header remain bit number"] +pub type SLICE_REMAIN_BITLENGTH_R = crate::FieldReader; +#[doc = "Field `SLICE_REMAIN_BITLENGTH` writer - Configures Slice Header remain bit number"] +pub type SLICE_REMAIN_BITLENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SLICE_REMAIN_BIT` reader - Configures Slice Header remain bit"] +pub type SLICE_REMAIN_BIT_R = crate::FieldReader; +#[doc = "Field `SLICE_REMAIN_BIT` writer - Configures Slice Header remain bit"] +pub type SLICE_REMAIN_BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:2 - Configures Slice Header remain bit number"] + #[inline(always)] + pub fn slice_remain_bitlength(&self) -> SLICE_REMAIN_BITLENGTH_R { + SLICE_REMAIN_BITLENGTH_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:10 - Configures Slice Header remain bit"] + #[inline(always)] + pub fn slice_remain_bit(&self) -> SLICE_REMAIN_BIT_R { + SLICE_REMAIN_BIT_R::new(((self.bits >> 3) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLICE_HEADER_REMAIN") + .field( + "slice_remain_bitlength", + &format_args!("{}", self.slice_remain_bitlength().bits()), + ) + .field( + "slice_remain_bit", + &format_args!("{}", self.slice_remain_bit().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Configures Slice Header remain bit number"] + #[inline(always)] + #[must_use] + pub fn slice_remain_bitlength(&mut self) -> SLICE_REMAIN_BITLENGTH_W { + SLICE_REMAIN_BITLENGTH_W::new(self, 0) + } + #[doc = "Bits 3:10 - Configures Slice Header remain bit"] + #[inline(always)] + #[must_use] + pub fn slice_remain_bit(&mut self) -> SLICE_REMAIN_BIT_W { + SLICE_REMAIN_BIT_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Frame Slice Header remain bit register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slice_header_remain::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slice_header_remain::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLICE_HEADER_REMAIN_SPEC; +impl crate::RegisterSpec for SLICE_HEADER_REMAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slice_header_remain::R`](R) reader structure"] +impl crate::Readable for SLICE_HEADER_REMAIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slice_header_remain::W`](W) writer structure"] +impl crate::Writable for SLICE_HEADER_REMAIN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLICE_HEADER_REMAIN to value 0"] +impl crate::Resettable for SLICE_HEADER_REMAIN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/sys_ctrl.rs b/esp32p4/src/h264/sys_ctrl.rs new file mode 100644 index 0000000000..849b7c5144 --- /dev/null +++ b/esp32p4/src/h264/sys_ctrl.rs @@ -0,0 +1,87 @@ +#[doc = "Register `SYS_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SYS_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `FRAME_START` writer - Configures whether or not to start encoding one frame.\\\\0: Invalid. No effect\\\\1: Start encoding one frame"] +pub type FRAME_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_MOVE_START` writer - Configures whether or not to start moving reference data from external mem.\\\\0: Invalid. No effect\\\\1: H264 start moving two MB lines of reference frame from external mem to internal mem"] +pub type DMA_MOVE_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRAME_MODE` reader - Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this field must be set to 1 too.\\\\0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA\\\\1: Frame mode. Before every frame start, need reconfig reference frame DMA"] +pub type FRAME_MODE_R = crate::BitReader; +#[doc = "Field `FRAME_MODE` writer - Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this field must be set to 1 too.\\\\0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA\\\\1: Frame mode. Before every frame start, need reconfig reference frame DMA"] +pub type FRAME_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYS_RST_PULSE` writer - Configures whether or not to reset H264 ip.\\\\0: Invalid. No effect\\\\1: Reset H264 ip"] +pub type SYS_RST_PULSE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this field must be set to 1 too.\\\\0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA\\\\1: Frame mode. Before every frame start, need reconfig reference frame DMA"] + #[inline(always)] + pub fn frame_mode(&self) -> FRAME_MODE_R { + FRAME_MODE_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYS_CTRL") + .field("frame_mode", &format_args!("{}", self.frame_mode().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to start encoding one frame.\\\\0: Invalid. No effect\\\\1: Start encoding one frame"] + #[inline(always)] + #[must_use] + pub fn frame_start(&mut self) -> FRAME_START_W { + FRAME_START_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to start moving reference data from external mem.\\\\0: Invalid. No effect\\\\1: H264 start moving two MB lines of reference frame from external mem to internal mem"] + #[inline(always)] + #[must_use] + pub fn dma_move_start(&mut self) -> DMA_MOVE_START_W { + DMA_MOVE_START_W::new(self, 1) + } + #[doc = "Bit 2 - Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this field must be set to 1 too.\\\\0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA\\\\1: Frame mode. Before every frame start, need reconfig reference frame DMA"] + #[inline(always)] + #[must_use] + pub fn frame_mode(&mut self) -> FRAME_MODE_W { + FRAME_MODE_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to reset H264 ip.\\\\0: Invalid. No effect\\\\1: Reset H264 ip"] + #[inline(always)] + #[must_use] + pub fn sys_rst_pulse(&mut self) -> SYS_RST_PULSE_W { + SYS_RST_PULSE_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "H264 system level control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYS_CTRL_SPEC; +impl crate::RegisterSpec for SYS_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sys_ctrl::R`](R) reader structure"] +impl crate::Readable for SYS_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sys_ctrl::W`](W) writer structure"] +impl crate::Writable for SYS_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYS_CTRL to value 0"] +impl crate::Resettable for SYS_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264/sys_status.rs b/esp32p4/src/h264/sys_status.rs new file mode 100644 index 0000000000..fe85ccca9d --- /dev/null +++ b/esp32p4/src/h264/sys_status.rs @@ -0,0 +1,55 @@ +#[doc = "Register `SYS_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `FRAME_NUM` reader - Represents current frame number."] +pub type FRAME_NUM_R = crate::FieldReader; +#[doc = "Field `DUAL_STREAM_SEL` reader - Represents which register group is used for cur frame.\\\\0: Register group A is used\\\\1: Register group B is used."] +pub type DUAL_STREAM_SEL_R = crate::BitReader; +#[doc = "Field `INTRA_FLAG` reader - Represents the type of current encoding frame.\\\\0: P frame\\\\1: I frame."] +pub type INTRA_FLAG_R = crate::BitReader; +impl R { + #[doc = "Bits 0:8 - Represents current frame number."] + #[inline(always)] + pub fn frame_num(&self) -> FRAME_NUM_R { + FRAME_NUM_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bit 9 - Represents which register group is used for cur frame.\\\\0: Register group A is used\\\\1: Register group B is used."] + #[inline(always)] + pub fn dual_stream_sel(&self) -> DUAL_STREAM_SEL_R { + DUAL_STREAM_SEL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents the type of current encoding frame.\\\\0: P frame\\\\1: I frame."] + #[inline(always)] + pub fn intra_flag(&self) -> INTRA_FLAG_R { + INTRA_FLAG_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYS_STATUS") + .field("frame_num", &format_args!("{}", self.frame_num().bits())) + .field( + "dual_stream_sel", + &format_args!("{}", self.dual_stream_sel().bit()), + ) + .field("intra_flag", &format_args!("{}", self.intra_flag().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "System status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYS_STATUS_SPEC; +impl crate::RegisterSpec for SYS_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sys_status::R`](R) reader structure"] +impl crate::Readable for SYS_STATUS_SPEC {} +#[doc = "`reset()` method sets SYS_STATUS to value 0"] +impl crate::Resettable for SYS_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma.rs b/esp32p4/src/h264_dma.rs new file mode 100644 index 0000000000..7c77d52d75 --- /dev/null +++ b/esp32p4/src/h264_dma.rs @@ -0,0 +1,2535 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + out_conf0_ch0: OUT_CONF0_CH0, + out_int_raw_ch0: OUT_INT_RAW_CH0, + out_int_ena_ch0: OUT_INT_ENA_CH0, + out_int_st_ch0: OUT_INT_ST_CH0, + out_int_clr_ch0: OUT_INT_CLR_CH0, + outfifo_status_ch0: OUTFIFO_STATUS_CH0, + out_push_ch0: OUT_PUSH_CH0, + out_link_conf_ch0: OUT_LINK_CONF_CH0, + out_link_addr_ch0: OUT_LINK_ADDR_CH0, + out_state_ch0: OUT_STATE_CH0, + out_eof_des_addr_ch0: OUT_EOF_DES_ADDR_CH0, + out_dscr_ch0: OUT_DSCR_CH0, + out_dscr_bf0_ch0: OUT_DSCR_BF0_CH0, + out_dscr_bf1_ch0: OUT_DSCR_BF1_CH0, + _reserved14: [u8; 0x04], + out_arb_ch0: OUT_ARB_CH0, + out_ro_status_ch0: OUT_RO_STATUS_CH0, + out_ro_pd_conf_ch0: OUT_RO_PD_CONF_CH0, + _reserved17: [u8; 0x08], + out_mode_enable_ch0: OUT_MODE_ENABLE_CH0, + out_mode_yuv_ch0: OUT_MODE_YUV_CH0, + _reserved19: [u8; 0x10], + out_etm_conf_ch0: OUT_ETM_CONF_CH0, + _reserved20: [u8; 0x04], + out_buf_len_ch0: OUT_BUF_LEN_CH0, + out_fifo_bcnt_ch0: OUT_FIFO_BCNT_CH0, + out_push_bytecnt_ch0: OUT_PUSH_BYTECNT_CH0, + out_xaddr_ch0: OUT_XADDR_CH0, + _reserved24: [u8; 0x80], + out_conf0_ch1: OUT_CONF0_CH1, + out_int_raw_ch1: OUT_INT_RAW_CH1, + out_int_ena_ch1: OUT_INT_ENA_CH1, + out_int_st_ch1: OUT_INT_ST_CH1, + out_int_clr_ch1: OUT_INT_CLR_CH1, + outfifo_status_ch1: OUTFIFO_STATUS_CH1, + out_push_ch1: OUT_PUSH_CH1, + out_link_conf_ch1: OUT_LINK_CONF_CH1, + out_link_addr_ch1: OUT_LINK_ADDR_CH1, + out_state_ch1: OUT_STATE_CH1, + out_eof_des_addr_ch1: OUT_EOF_DES_ADDR_CH1, + out_dscr_ch1: OUT_DSCR_CH1, + out_dscr_bf0_ch1: OUT_DSCR_BF0_CH1, + out_dscr_bf1_ch1: OUT_DSCR_BF1_CH1, + _reserved38: [u8; 0x04], + out_arb_ch1: OUT_ARB_CH1, + _reserved39: [u8; 0x28], + out_etm_conf_ch1: OUT_ETM_CONF_CH1, + _reserved40: [u8; 0x04], + out_buf_len_ch1: OUT_BUF_LEN_CH1, + out_fifo_bcnt_ch1: OUT_FIFO_BCNT_CH1, + out_push_bytecnt_ch1: OUT_PUSH_BYTECNT_CH1, + out_xaddr_ch1: OUT_XADDR_CH1, + _reserved44: [u8; 0x80], + out_conf0_ch2: OUT_CONF0_CH2, + out_int_raw_ch2: OUT_INT_RAW_CH2, + out_int_ena_ch2: OUT_INT_ENA_CH2, + out_int_st_ch2: OUT_INT_ST_CH2, + out_int_clr_ch2: OUT_INT_CLR_CH2, + outfifo_status_ch2: OUTFIFO_STATUS_CH2, + out_push_ch2: OUT_PUSH_CH2, + out_link_conf_ch2: OUT_LINK_CONF_CH2, + out_link_addr_ch2: OUT_LINK_ADDR_CH2, + out_state_ch2: OUT_STATE_CH2, + out_eof_des_addr_ch2: OUT_EOF_DES_ADDR_CH2, + out_dscr_ch2: OUT_DSCR_CH2, + out_dscr_bf0_ch2: OUT_DSCR_BF0_CH2, + out_dscr_bf1_ch2: OUT_DSCR_BF1_CH2, + _reserved58: [u8; 0x04], + out_arb_ch2: OUT_ARB_CH2, + _reserved59: [u8; 0x28], + out_etm_conf_ch2: OUT_ETM_CONF_CH2, + _reserved60: [u8; 0x04], + out_buf_len_ch2: OUT_BUF_LEN_CH2, + out_fifo_bcnt_ch2: OUT_FIFO_BCNT_CH2, + out_push_bytecnt_ch2: OUT_PUSH_BYTECNT_CH2, + out_xaddr_ch2: OUT_XADDR_CH2, + _reserved64: [u8; 0x80], + out_conf0_ch3: OUT_CONF0_CH3, + out_int_raw_ch3: OUT_INT_RAW_CH3, + out_int_ena_ch3: OUT_INT_ENA_CH3, + out_int_st_ch3: OUT_INT_ST_CH3, + out_int_clr_ch3: OUT_INT_CLR_CH3, + outfifo_status_ch3: OUTFIFO_STATUS_CH3, + out_push_ch3: OUT_PUSH_CH3, + out_link_conf_ch3: OUT_LINK_CONF_CH3, + out_link_addr_ch3: OUT_LINK_ADDR_CH3, + out_state_ch3: OUT_STATE_CH3, + out_eof_des_addr_ch3: OUT_EOF_DES_ADDR_CH3, + out_dscr_ch3: OUT_DSCR_CH3, + out_dscr_bf0_ch3: OUT_DSCR_BF0_CH3, + out_dscr_bf1_ch3: OUT_DSCR_BF1_CH3, + _reserved78: [u8; 0x04], + out_arb_ch3: OUT_ARB_CH3, + _reserved79: [u8; 0x28], + out_etm_conf_ch3: OUT_ETM_CONF_CH3, + _reserved80: [u8; 0x04], + out_buf_len_ch3: OUT_BUF_LEN_CH3, + out_fifo_bcnt_ch3: OUT_FIFO_BCNT_CH3, + out_push_bytecnt_ch3: OUT_PUSH_BYTECNT_CH3, + out_xaddr_ch3: OUT_XADDR_CH3, + out_block_buf_len_ch3: OUT_BLOCK_BUF_LEN_CH3, + _reserved85: [u8; 0x7c], + out_conf0_ch4: OUT_CONF0_CH4, + out_int_raw_ch4: OUT_INT_RAW_CH4, + out_int_ena_ch4: OUT_INT_ENA_CH4, + out_int_st_ch4: OUT_INT_ST_CH4, + out_int_clr_ch4: OUT_INT_CLR_CH4, + outfifo_status_ch4: OUTFIFO_STATUS_CH4, + out_push_ch4: OUT_PUSH_CH4, + out_link_conf_ch4: OUT_LINK_CONF_CH4, + out_link_addr_ch4: OUT_LINK_ADDR_CH4, + out_state_ch4: OUT_STATE_CH4, + out_eof_des_addr_ch4: OUT_EOF_DES_ADDR_CH4, + out_dscr_ch4: OUT_DSCR_CH4, + out_dscr_bf0_ch4: OUT_DSCR_BF0_CH4, + out_dscr_bf1_ch4: OUT_DSCR_BF1_CH4, + _reserved99: [u8; 0x04], + out_arb_ch4: OUT_ARB_CH4, + _reserved100: [u8; 0x28], + out_etm_conf_ch4: OUT_ETM_CONF_CH4, + _reserved101: [u8; 0x04], + out_buf_len_ch4: OUT_BUF_LEN_CH4, + out_fifo_bcnt_ch4: OUT_FIFO_BCNT_CH4, + out_push_bytecnt_ch4: OUT_PUSH_BYTECNT_CH4, + out_xaddr_ch4: OUT_XADDR_CH4, + out_block_buf_len_ch4: OUT_BLOCK_BUF_LEN_CH4, + _reserved106: [u8; 0x7c], + in_conf0_ch0: IN_CONF0_CH0, + in_int_raw_ch0: IN_INT_RAW_CH0, + in_int_ena_ch0: IN_INT_ENA_CH0, + in_int_st_ch0: IN_INT_ST_CH0, + in_int_clr_ch0: IN_INT_CLR_CH0, + infifo_status_ch0: INFIFO_STATUS_CH0, + in_pop_ch0: IN_POP_CH0, + in_link_conf_ch0: IN_LINK_CONF_CH0, + in_link_addr_ch0: IN_LINK_ADDR_CH0, + in_state_ch0: IN_STATE_CH0, + in_suc_eof_des_addr_ch0: IN_SUC_EOF_DES_ADDR_CH0, + in_err_eof_des_addr_ch0: IN_ERR_EOF_DES_ADDR_CH0, + in_dscr_ch0: IN_DSCR_CH0, + in_dscr_bf0_ch0: IN_DSCR_BF0_CH0, + in_dscr_bf1_ch0: IN_DSCR_BF1_CH0, + _reserved121: [u8; 0x04], + in_arb_ch0: IN_ARB_CH0, + _reserved122: [u8; 0x04], + in_ro_pd_conf_ch0: IN_RO_PD_CONF_CH0, + _reserved123: [u8; 0x20], + in_etm_conf_ch0: IN_ETM_CONF_CH0, + _reserved124: [u8; 0x10], + in_fifo_cnt_ch0: IN_FIFO_CNT_CH0, + in_pop_data_cnt_ch0: IN_POP_DATA_CNT_CH0, + in_xaddr_ch0: IN_XADDR_CH0, + in_buf_hb_rcv_ch0: IN_BUF_HB_RCV_CH0, + _reserved128: [u8; 0x70], + in_conf0_ch1: IN_CONF0_CH1, + in_int_raw_ch1: IN_INT_RAW_CH1, + in_int_ena_ch1: IN_INT_ENA_CH1, + in_int_st_ch1: IN_INT_ST_CH1, + in_int_clr_ch1: IN_INT_CLR_CH1, + infifo_status_ch1: INFIFO_STATUS_CH1, + in_pop_ch1: IN_POP_CH1, + in_link_conf_ch1: IN_LINK_CONF_CH1, + in_link_addr_ch1: IN_LINK_ADDR_CH1, + in_state_ch1: IN_STATE_CH1, + in_suc_eof_des_addr_ch1: IN_SUC_EOF_DES_ADDR_CH1, + in_err_eof_des_addr_ch1: IN_ERR_EOF_DES_ADDR_CH1, + in_dscr_ch1: IN_DSCR_CH1, + in_dscr_bf0_ch1: IN_DSCR_BF0_CH1, + in_dscr_bf1_ch1: IN_DSCR_BF1_CH1, + _reserved143: [u8; 0x04], + in_arb_ch1: IN_ARB_CH1, + _reserved144: [u8; 0x04], + in_etm_conf_ch1: IN_ETM_CONF_CH1, + _reserved145: [u8; 0x34], + in_fifo_cnt_ch1: IN_FIFO_CNT_CH1, + in_pop_data_cnt_ch1: IN_POP_DATA_CNT_CH1, + in_xaddr_ch1: IN_XADDR_CH1, + in_buf_hb_rcv_ch1: IN_BUF_HB_RCV_CH1, + _reserved149: [u8; 0x70], + in_conf0_ch2: IN_CONF0_CH2, + in_int_raw_ch2: IN_INT_RAW_CH2, + in_int_ena_ch2: IN_INT_ENA_CH2, + in_int_st_ch2: IN_INT_ST_CH2, + in_int_clr_ch2: IN_INT_CLR_CH2, + infifo_status_ch2: INFIFO_STATUS_CH2, + in_pop_ch2: IN_POP_CH2, + in_link_conf_ch2: IN_LINK_CONF_CH2, + in_link_addr_ch2: IN_LINK_ADDR_CH2, + in_state_ch2: IN_STATE_CH2, + in_suc_eof_des_addr_ch2: IN_SUC_EOF_DES_ADDR_CH2, + in_err_eof_des_addr_ch2: IN_ERR_EOF_DES_ADDR_CH2, + in_dscr_ch2: IN_DSCR_CH2, + in_dscr_bf0_ch2: IN_DSCR_BF0_CH2, + in_dscr_bf1_ch2: IN_DSCR_BF1_CH2, + _reserved164: [u8; 0x04], + in_arb_ch2: IN_ARB_CH2, + _reserved165: [u8; 0x04], + in_etm_conf_ch2: IN_ETM_CONF_CH2, + _reserved166: [u8; 0x34], + in_fifo_cnt_ch2: IN_FIFO_CNT_CH2, + in_pop_data_cnt_ch2: IN_POP_DATA_CNT_CH2, + in_xaddr_ch2: IN_XADDR_CH2, + in_buf_hb_rcv_ch2: IN_BUF_HB_RCV_CH2, + _reserved170: [u8; 0x70], + in_conf0_ch3: IN_CONF0_CH3, + in_int_raw_ch3: IN_INT_RAW_CH3, + in_int_ena_ch3: IN_INT_ENA_CH3, + in_int_st_ch3: IN_INT_ST_CH3, + in_int_clr_ch3: IN_INT_CLR_CH3, + infifo_status_ch3: INFIFO_STATUS_CH3, + in_pop_ch3: IN_POP_CH3, + in_link_conf_ch3: IN_LINK_CONF_CH3, + in_link_addr_ch3: IN_LINK_ADDR_CH3, + in_state_ch3: IN_STATE_CH3, + in_suc_eof_des_addr_ch3: IN_SUC_EOF_DES_ADDR_CH3, + in_err_eof_des_addr_ch3: IN_ERR_EOF_DES_ADDR_CH3, + in_dscr_ch3: IN_DSCR_CH3, + in_dscr_bf0_ch3: IN_DSCR_BF0_CH3, + in_dscr_bf1_ch3: IN_DSCR_BF1_CH3, + _reserved185: [u8; 0x04], + in_arb_ch3: IN_ARB_CH3, + _reserved186: [u8; 0x04], + in_etm_conf_ch3: IN_ETM_CONF_CH3, + _reserved187: [u8; 0x34], + in_fifo_cnt_ch3: IN_FIFO_CNT_CH3, + in_pop_data_cnt_ch3: IN_POP_DATA_CNT_CH3, + in_xaddr_ch3: IN_XADDR_CH3, + in_buf_hb_rcv_ch3: IN_BUF_HB_RCV_CH3, + _reserved191: [u8; 0x70], + in_conf0_ch4: IN_CONF0_CH4, + in_int_raw_ch4: IN_INT_RAW_CH4, + in_int_ena_ch4: IN_INT_ENA_CH4, + in_int_st_ch4: IN_INT_ST_CH4, + in_int_clr_ch4: IN_INT_CLR_CH4, + infifo_status_ch4: INFIFO_STATUS_CH4, + in_pop_ch4: IN_POP_CH4, + in_link_conf_ch4: IN_LINK_CONF_CH4, + in_link_addr_ch4: IN_LINK_ADDR_CH4, + in_state_ch4: IN_STATE_CH4, + in_suc_eof_des_addr_ch4: IN_SUC_EOF_DES_ADDR_CH4, + in_err_eof_des_addr_ch4: IN_ERR_EOF_DES_ADDR_CH4, + in_dscr_ch4: IN_DSCR_CH4, + in_dscr_bf0_ch4: IN_DSCR_BF0_CH4, + in_dscr_bf1_ch4: IN_DSCR_BF1_CH4, + _reserved206: [u8; 0x04], + in_arb_ch4: IN_ARB_CH4, + _reserved207: [u8; 0x04], + in_etm_conf_ch4: IN_ETM_CONF_CH4, + _reserved208: [u8; 0x34], + in_fifo_cnt_ch4: IN_FIFO_CNT_CH4, + in_pop_data_cnt_ch4: IN_POP_DATA_CNT_CH4, + in_xaddr_ch4: IN_XADDR_CH4, + in_buf_hb_rcv_ch4: IN_BUF_HB_RCV_CH4, + _reserved212: [u8; 0x70], + in_conf0_ch5: IN_CONF0_CH5, + in_conf1_ch5: IN_CONF1_CH5, + in_conf2_ch5: IN_CONF2_CH5, + in_conf3_ch5: IN_CONF3_CH5, + in_int_raw_ch5: IN_INT_RAW_CH5, + in_int_ena_ch5: IN_INT_ENA_CH5, + in_int_st_ch5: IN_INT_ST_CH5, + in_int_clr_ch5: IN_INT_CLR_CH5, + infifo_status_ch5: INFIFO_STATUS_CH5, + in_pop_ch5: IN_POP_CH5, + in_state_ch5: IN_STATE_CH5, + _reserved223: [u8; 0x14], + in_arb_ch5: IN_ARB_CH5, + _reserved224: [u8; 0x3c], + in_fifo_cnt_ch5: IN_FIFO_CNT_CH5, + in_pop_data_cnt_ch5: IN_POP_DATA_CNT_CH5, + in_xaddr_ch5: IN_XADDR_CH5, + in_buf_hb_rcv_ch5: IN_BUF_HB_RCV_CH5, + _reserved228: [u8; 0x70], + inter_axi_err: INTER_AXI_ERR, + exter_axi_err: EXTER_AXI_ERR, + rst_conf: RST_CONF, + inter_mem_start_addr0: INTER_MEM_START_ADDR0, + inter_mem_end_addr0: INTER_MEM_END_ADDR0, + inter_mem_start_addr1: INTER_MEM_START_ADDR1, + inter_mem_end_addr1: INTER_MEM_END_ADDR1, + _reserved235: [u8; 0x04], + exter_mem_start_addr0: EXTER_MEM_START_ADDR0, + exter_mem_end_addr0: EXTER_MEM_END_ADDR0, + exter_mem_start_addr1: EXTER_MEM_START_ADDR1, + exter_mem_end_addr1: EXTER_MEM_END_ADDR1, + out_arb_config: OUT_ARB_CONFIG, + in_arb_config: IN_ARB_CONFIG, + _reserved241: [u8; 0x04], + date: DATE, + _reserved242: [u8; 0x10], + counter_rst: COUNTER_RST, + rx_ch0_counter: RX_CH0_COUNTER, + rx_ch1_counter: RX_CH1_COUNTER, + rx_ch2_counter: RX_CH2_COUNTER, + rx_ch5_counter: RX_CH5_COUNTER, +} +impl RegisterBlock { + #[doc = "0x00 - TX CH0 config0 register"] + #[inline(always)] + pub const fn out_conf0_ch0(&self) -> &OUT_CONF0_CH0 { + &self.out_conf0_ch0 + } + #[doc = "0x04 - TX CH0 interrupt raw register"] + #[inline(always)] + pub const fn out_int_raw_ch0(&self) -> &OUT_INT_RAW_CH0 { + &self.out_int_raw_ch0 + } + #[doc = "0x08 - TX CH0 interrupt ena register"] + #[inline(always)] + pub const fn out_int_ena_ch0(&self) -> &OUT_INT_ENA_CH0 { + &self.out_int_ena_ch0 + } + #[doc = "0x0c - TX CH0 interrupt st register"] + #[inline(always)] + pub const fn out_int_st_ch0(&self) -> &OUT_INT_ST_CH0 { + &self.out_int_st_ch0 + } + #[doc = "0x10 - TX CH0 interrupt clr register"] + #[inline(always)] + pub const fn out_int_clr_ch0(&self) -> &OUT_INT_CLR_CH0 { + &self.out_int_clr_ch0 + } + #[doc = "0x14 - TX CH0 outfifo status register"] + #[inline(always)] + pub const fn outfifo_status_ch0(&self) -> &OUTFIFO_STATUS_CH0 { + &self.outfifo_status_ch0 + } + #[doc = "0x18 - TX CH0 outfifo push register"] + #[inline(always)] + pub const fn out_push_ch0(&self) -> &OUT_PUSH_CH0 { + &self.out_push_ch0 + } + #[doc = "0x1c - TX CH0 out_link dscr ctrl register"] + #[inline(always)] + pub const fn out_link_conf_ch0(&self) -> &OUT_LINK_CONF_CH0 { + &self.out_link_conf_ch0 + } + #[doc = "0x20 - TX CH0 out_link dscr addr register"] + #[inline(always)] + pub const fn out_link_addr_ch0(&self) -> &OUT_LINK_ADDR_CH0 { + &self.out_link_addr_ch0 + } + #[doc = "0x24 - TX CH0 state register"] + #[inline(always)] + pub const fn out_state_ch0(&self) -> &OUT_STATE_CH0 { + &self.out_state_ch0 + } + #[doc = "0x28 - TX CH0 eof des addr register"] + #[inline(always)] + pub const fn out_eof_des_addr_ch0(&self) -> &OUT_EOF_DES_ADDR_CH0 { + &self.out_eof_des_addr_ch0 + } + #[doc = "0x2c - TX CH0 next dscr addr register"] + #[inline(always)] + pub const fn out_dscr_ch0(&self) -> &OUT_DSCR_CH0 { + &self.out_dscr_ch0 + } + #[doc = "0x30 - TX CH0 last dscr addr register"] + #[inline(always)] + pub const fn out_dscr_bf0_ch0(&self) -> &OUT_DSCR_BF0_CH0 { + &self.out_dscr_bf0_ch0 + } + #[doc = "0x34 - TX CH0 second-to-last dscr addr register"] + #[inline(always)] + pub const fn out_dscr_bf1_ch0(&self) -> &OUT_DSCR_BF1_CH0 { + &self.out_dscr_bf1_ch0 + } + #[doc = "0x3c - TX CH0 arb register"] + #[inline(always)] + pub const fn out_arb_ch0(&self) -> &OUT_ARB_CH0 { + &self.out_arb_ch0 + } + #[doc = "0x40 - TX CH0 reorder status register"] + #[inline(always)] + pub const fn out_ro_status_ch0(&self) -> &OUT_RO_STATUS_CH0 { + &self.out_ro_status_ch0 + } + #[doc = "0x44 - TX CH0 reorder power config register"] + #[inline(always)] + pub const fn out_ro_pd_conf_ch0(&self) -> &OUT_RO_PD_CONF_CH0 { + &self.out_ro_pd_conf_ch0 + } + #[doc = "0x50 - tx CH0 mode enable register"] + #[inline(always)] + pub const fn out_mode_enable_ch0(&self) -> &OUT_MODE_ENABLE_CH0 { + &self.out_mode_enable_ch0 + } + #[doc = "0x54 - tx CH0 test mode yuv value register"] + #[inline(always)] + pub const fn out_mode_yuv_ch0(&self) -> &OUT_MODE_YUV_CH0 { + &self.out_mode_yuv_ch0 + } + #[doc = "0x68 - TX CH0 ETM config register"] + #[inline(always)] + pub const fn out_etm_conf_ch0(&self) -> &OUT_ETM_CONF_CH0 { + &self.out_etm_conf_ch0 + } + #[doc = "0x70 - tx CH0 buf len register"] + #[inline(always)] + pub const fn out_buf_len_ch0(&self) -> &OUT_BUF_LEN_CH0 { + &self.out_buf_len_ch0 + } + #[doc = "0x74 - tx CH0 fifo byte cnt register"] + #[inline(always)] + pub const fn out_fifo_bcnt_ch0(&self) -> &OUT_FIFO_BCNT_CH0 { + &self.out_fifo_bcnt_ch0 + } + #[doc = "0x78 - tx CH0 push byte cnt register"] + #[inline(always)] + pub const fn out_push_bytecnt_ch0(&self) -> &OUT_PUSH_BYTECNT_CH0 { + &self.out_push_bytecnt_ch0 + } + #[doc = "0x7c - tx CH0 xaddr register"] + #[inline(always)] + pub const fn out_xaddr_ch0(&self) -> &OUT_XADDR_CH0 { + &self.out_xaddr_ch0 + } + #[doc = "0x100 - TX CH1 config0 register"] + #[inline(always)] + pub const fn out_conf0_ch1(&self) -> &OUT_CONF0_CH1 { + &self.out_conf0_ch1 + } + #[doc = "0x104 - TX CH1 interrupt raw register"] + #[inline(always)] + pub const fn out_int_raw_ch1(&self) -> &OUT_INT_RAW_CH1 { + &self.out_int_raw_ch1 + } + #[doc = "0x108 - TX CH1 interrupt ena register"] + #[inline(always)] + pub const fn out_int_ena_ch1(&self) -> &OUT_INT_ENA_CH1 { + &self.out_int_ena_ch1 + } + #[doc = "0x10c - TX CH1 interrupt st register"] + #[inline(always)] + pub const fn out_int_st_ch1(&self) -> &OUT_INT_ST_CH1 { + &self.out_int_st_ch1 + } + #[doc = "0x110 - TX CH1 interrupt clr register"] + #[inline(always)] + pub const fn out_int_clr_ch1(&self) -> &OUT_INT_CLR_CH1 { + &self.out_int_clr_ch1 + } + #[doc = "0x114 - TX CH1 outfifo status register"] + #[inline(always)] + pub const fn outfifo_status_ch1(&self) -> &OUTFIFO_STATUS_CH1 { + &self.outfifo_status_ch1 + } + #[doc = "0x118 - TX CH1 outfifo push register"] + #[inline(always)] + pub const fn out_push_ch1(&self) -> &OUT_PUSH_CH1 { + &self.out_push_ch1 + } + #[doc = "0x11c - TX CH1 out_link dscr ctrl register"] + #[inline(always)] + pub const fn out_link_conf_ch1(&self) -> &OUT_LINK_CONF_CH1 { + &self.out_link_conf_ch1 + } + #[doc = "0x120 - TX CH1 out_link dscr addr register"] + #[inline(always)] + pub const fn out_link_addr_ch1(&self) -> &OUT_LINK_ADDR_CH1 { + &self.out_link_addr_ch1 + } + #[doc = "0x124 - TX CH1 state register"] + #[inline(always)] + pub const fn out_state_ch1(&self) -> &OUT_STATE_CH1 { + &self.out_state_ch1 + } + #[doc = "0x128 - TX CH1 eof des addr register"] + #[inline(always)] + pub const fn out_eof_des_addr_ch1(&self) -> &OUT_EOF_DES_ADDR_CH1 { + &self.out_eof_des_addr_ch1 + } + #[doc = "0x12c - TX CH1 next dscr addr register"] + #[inline(always)] + pub const fn out_dscr_ch1(&self) -> &OUT_DSCR_CH1 { + &self.out_dscr_ch1 + } + #[doc = "0x130 - TX CH1 last dscr addr register"] + #[inline(always)] + pub const fn out_dscr_bf0_ch1(&self) -> &OUT_DSCR_BF0_CH1 { + &self.out_dscr_bf0_ch1 + } + #[doc = "0x134 - TX CH1 second-to-last dscr addr register"] + #[inline(always)] + pub const fn out_dscr_bf1_ch1(&self) -> &OUT_DSCR_BF1_CH1 { + &self.out_dscr_bf1_ch1 + } + #[doc = "0x13c - TX CH1 arb register"] + #[inline(always)] + pub const fn out_arb_ch1(&self) -> &OUT_ARB_CH1 { + &self.out_arb_ch1 + } + #[doc = "0x168 - TX CH1 ETM config register"] + #[inline(always)] + pub const fn out_etm_conf_ch1(&self) -> &OUT_ETM_CONF_CH1 { + &self.out_etm_conf_ch1 + } + #[doc = "0x170 - tx CH1 buf len register"] + #[inline(always)] + pub const fn out_buf_len_ch1(&self) -> &OUT_BUF_LEN_CH1 { + &self.out_buf_len_ch1 + } + #[doc = "0x174 - tx CH1 fifo byte cnt register"] + #[inline(always)] + pub const fn out_fifo_bcnt_ch1(&self) -> &OUT_FIFO_BCNT_CH1 { + &self.out_fifo_bcnt_ch1 + } + #[doc = "0x178 - tx CH1 push byte cnt register"] + #[inline(always)] + pub const fn out_push_bytecnt_ch1(&self) -> &OUT_PUSH_BYTECNT_CH1 { + &self.out_push_bytecnt_ch1 + } + #[doc = "0x17c - tx CH1 xaddr register"] + #[inline(always)] + pub const fn out_xaddr_ch1(&self) -> &OUT_XADDR_CH1 { + &self.out_xaddr_ch1 + } + #[doc = "0x200 - TX CH2 config0 register"] + #[inline(always)] + pub const fn out_conf0_ch2(&self) -> &OUT_CONF0_CH2 { + &self.out_conf0_ch2 + } + #[doc = "0x204 - TX CH2 interrupt raw register"] + #[inline(always)] + pub const fn out_int_raw_ch2(&self) -> &OUT_INT_RAW_CH2 { + &self.out_int_raw_ch2 + } + #[doc = "0x208 - TX CH2 interrupt ena register"] + #[inline(always)] + pub const fn out_int_ena_ch2(&self) -> &OUT_INT_ENA_CH2 { + &self.out_int_ena_ch2 + } + #[doc = "0x20c - TX CH2 interrupt st register"] + #[inline(always)] + pub const fn out_int_st_ch2(&self) -> &OUT_INT_ST_CH2 { + &self.out_int_st_ch2 + } + #[doc = "0x210 - TX CH2 interrupt clr register"] + #[inline(always)] + pub const fn out_int_clr_ch2(&self) -> &OUT_INT_CLR_CH2 { + &self.out_int_clr_ch2 + } + #[doc = "0x214 - TX CH2 outfifo status register"] + #[inline(always)] + pub const fn outfifo_status_ch2(&self) -> &OUTFIFO_STATUS_CH2 { + &self.outfifo_status_ch2 + } + #[doc = "0x218 - TX CH2 outfifo push register"] + #[inline(always)] + pub const fn out_push_ch2(&self) -> &OUT_PUSH_CH2 { + &self.out_push_ch2 + } + #[doc = "0x21c - TX CH2 out_link dscr ctrl register"] + #[inline(always)] + pub const fn out_link_conf_ch2(&self) -> &OUT_LINK_CONF_CH2 { + &self.out_link_conf_ch2 + } + #[doc = "0x220 - TX CH2 out_link dscr addr register"] + #[inline(always)] + pub const fn out_link_addr_ch2(&self) -> &OUT_LINK_ADDR_CH2 { + &self.out_link_addr_ch2 + } + #[doc = "0x224 - TX CH2 state register"] + #[inline(always)] + pub const fn out_state_ch2(&self) -> &OUT_STATE_CH2 { + &self.out_state_ch2 + } + #[doc = "0x228 - TX CH2 eof des addr register"] + #[inline(always)] + pub const fn out_eof_des_addr_ch2(&self) -> &OUT_EOF_DES_ADDR_CH2 { + &self.out_eof_des_addr_ch2 + } + #[doc = "0x22c - TX CH2 next dscr addr register"] + #[inline(always)] + pub const fn out_dscr_ch2(&self) -> &OUT_DSCR_CH2 { + &self.out_dscr_ch2 + } + #[doc = "0x230 - TX CH2 last dscr addr register"] + #[inline(always)] + pub const fn out_dscr_bf0_ch2(&self) -> &OUT_DSCR_BF0_CH2 { + &self.out_dscr_bf0_ch2 + } + #[doc = "0x234 - TX CH2 second-to-last dscr addr register"] + #[inline(always)] + pub const fn out_dscr_bf1_ch2(&self) -> &OUT_DSCR_BF1_CH2 { + &self.out_dscr_bf1_ch2 + } + #[doc = "0x23c - TX CH2 arb register"] + #[inline(always)] + pub const fn out_arb_ch2(&self) -> &OUT_ARB_CH2 { + &self.out_arb_ch2 + } + #[doc = "0x268 - TX CH2 ETM config register"] + #[inline(always)] + pub const fn out_etm_conf_ch2(&self) -> &OUT_ETM_CONF_CH2 { + &self.out_etm_conf_ch2 + } + #[doc = "0x270 - tx CH2 buf len register"] + #[inline(always)] + pub const fn out_buf_len_ch2(&self) -> &OUT_BUF_LEN_CH2 { + &self.out_buf_len_ch2 + } + #[doc = "0x274 - tx CH2 fifo byte cnt register"] + #[inline(always)] + pub const fn out_fifo_bcnt_ch2(&self) -> &OUT_FIFO_BCNT_CH2 { + &self.out_fifo_bcnt_ch2 + } + #[doc = "0x278 - tx CH2 push byte cnt register"] + #[inline(always)] + pub const fn out_push_bytecnt_ch2(&self) -> &OUT_PUSH_BYTECNT_CH2 { + &self.out_push_bytecnt_ch2 + } + #[doc = "0x27c - tx CH2 xaddr register"] + #[inline(always)] + pub const fn out_xaddr_ch2(&self) -> &OUT_XADDR_CH2 { + &self.out_xaddr_ch2 + } + #[doc = "0x300 - TX CH3 config0 register"] + #[inline(always)] + pub const fn out_conf0_ch3(&self) -> &OUT_CONF0_CH3 { + &self.out_conf0_ch3 + } + #[doc = "0x304 - TX CH3 interrupt raw register"] + #[inline(always)] + pub const fn out_int_raw_ch3(&self) -> &OUT_INT_RAW_CH3 { + &self.out_int_raw_ch3 + } + #[doc = "0x308 - TX CH3 interrupt ena register"] + #[inline(always)] + pub const fn out_int_ena_ch3(&self) -> &OUT_INT_ENA_CH3 { + &self.out_int_ena_ch3 + } + #[doc = "0x30c - TX CH3 interrupt st register"] + #[inline(always)] + pub const fn out_int_st_ch3(&self) -> &OUT_INT_ST_CH3 { + &self.out_int_st_ch3 + } + #[doc = "0x310 - TX CH3 interrupt clr register"] + #[inline(always)] + pub const fn out_int_clr_ch3(&self) -> &OUT_INT_CLR_CH3 { + &self.out_int_clr_ch3 + } + #[doc = "0x314 - TX CH3 outfifo status register"] + #[inline(always)] + pub const fn outfifo_status_ch3(&self) -> &OUTFIFO_STATUS_CH3 { + &self.outfifo_status_ch3 + } + #[doc = "0x318 - TX CH3 outfifo push register"] + #[inline(always)] + pub const fn out_push_ch3(&self) -> &OUT_PUSH_CH3 { + &self.out_push_ch3 + } + #[doc = "0x31c - TX CH3 out_link dscr ctrl register"] + #[inline(always)] + pub const fn out_link_conf_ch3(&self) -> &OUT_LINK_CONF_CH3 { + &self.out_link_conf_ch3 + } + #[doc = "0x320 - TX CH3 out_link dscr addr register"] + #[inline(always)] + pub const fn out_link_addr_ch3(&self) -> &OUT_LINK_ADDR_CH3 { + &self.out_link_addr_ch3 + } + #[doc = "0x324 - TX CH3 state register"] + #[inline(always)] + pub const fn out_state_ch3(&self) -> &OUT_STATE_CH3 { + &self.out_state_ch3 + } + #[doc = "0x328 - TX CH3 eof des addr register"] + #[inline(always)] + pub const fn out_eof_des_addr_ch3(&self) -> &OUT_EOF_DES_ADDR_CH3 { + &self.out_eof_des_addr_ch3 + } + #[doc = "0x32c - TX CH3 next dscr addr register"] + #[inline(always)] + pub const fn out_dscr_ch3(&self) -> &OUT_DSCR_CH3 { + &self.out_dscr_ch3 + } + #[doc = "0x330 - TX CH3 last dscr addr register"] + #[inline(always)] + pub const fn out_dscr_bf0_ch3(&self) -> &OUT_DSCR_BF0_CH3 { + &self.out_dscr_bf0_ch3 + } + #[doc = "0x334 - TX CH3 second-to-last dscr addr register"] + #[inline(always)] + pub const fn out_dscr_bf1_ch3(&self) -> &OUT_DSCR_BF1_CH3 { + &self.out_dscr_bf1_ch3 + } + #[doc = "0x33c - TX CH3 arb register"] + #[inline(always)] + pub const fn out_arb_ch3(&self) -> &OUT_ARB_CH3 { + &self.out_arb_ch3 + } + #[doc = "0x368 - TX CH3 ETM config register"] + #[inline(always)] + pub const fn out_etm_conf_ch3(&self) -> &OUT_ETM_CONF_CH3 { + &self.out_etm_conf_ch3 + } + #[doc = "0x370 - tx CH3 buf len register"] + #[inline(always)] + pub const fn out_buf_len_ch3(&self) -> &OUT_BUF_LEN_CH3 { + &self.out_buf_len_ch3 + } + #[doc = "0x374 - tx CH3 fifo byte cnt register"] + #[inline(always)] + pub const fn out_fifo_bcnt_ch3(&self) -> &OUT_FIFO_BCNT_CH3 { + &self.out_fifo_bcnt_ch3 + } + #[doc = "0x378 - tx CH3 push byte cnt register"] + #[inline(always)] + pub const fn out_push_bytecnt_ch3(&self) -> &OUT_PUSH_BYTECNT_CH3 { + &self.out_push_bytecnt_ch3 + } + #[doc = "0x37c - tx CH3 xaddr register"] + #[inline(always)] + pub const fn out_xaddr_ch3(&self) -> &OUT_XADDR_CH3 { + &self.out_xaddr_ch3 + } + #[doc = "0x380 - tx CH3 block buf len register"] + #[inline(always)] + pub const fn out_block_buf_len_ch3(&self) -> &OUT_BLOCK_BUF_LEN_CH3 { + &self.out_block_buf_len_ch3 + } + #[doc = "0x400 - TX CH4 config0 register"] + #[inline(always)] + pub const fn out_conf0_ch4(&self) -> &OUT_CONF0_CH4 { + &self.out_conf0_ch4 + } + #[doc = "0x404 - TX CH4 interrupt raw register"] + #[inline(always)] + pub const fn out_int_raw_ch4(&self) -> &OUT_INT_RAW_CH4 { + &self.out_int_raw_ch4 + } + #[doc = "0x408 - TX CH4 interrupt ena register"] + #[inline(always)] + pub const fn out_int_ena_ch4(&self) -> &OUT_INT_ENA_CH4 { + &self.out_int_ena_ch4 + } + #[doc = "0x40c - TX CH4 interrupt st register"] + #[inline(always)] + pub const fn out_int_st_ch4(&self) -> &OUT_INT_ST_CH4 { + &self.out_int_st_ch4 + } + #[doc = "0x410 - TX CH4 interrupt clr register"] + #[inline(always)] + pub const fn out_int_clr_ch4(&self) -> &OUT_INT_CLR_CH4 { + &self.out_int_clr_ch4 + } + #[doc = "0x414 - TX CH4 outfifo status register"] + #[inline(always)] + pub const fn outfifo_status_ch4(&self) -> &OUTFIFO_STATUS_CH4 { + &self.outfifo_status_ch4 + } + #[doc = "0x418 - TX CH4 outfifo push register"] + #[inline(always)] + pub const fn out_push_ch4(&self) -> &OUT_PUSH_CH4 { + &self.out_push_ch4 + } + #[doc = "0x41c - TX CH4 out_link dscr ctrl register"] + #[inline(always)] + pub const fn out_link_conf_ch4(&self) -> &OUT_LINK_CONF_CH4 { + &self.out_link_conf_ch4 + } + #[doc = "0x420 - TX CH4 out_link dscr addr register"] + #[inline(always)] + pub const fn out_link_addr_ch4(&self) -> &OUT_LINK_ADDR_CH4 { + &self.out_link_addr_ch4 + } + #[doc = "0x424 - TX CH4 state register"] + #[inline(always)] + pub const fn out_state_ch4(&self) -> &OUT_STATE_CH4 { + &self.out_state_ch4 + } + #[doc = "0x428 - TX CH4 eof des addr register"] + #[inline(always)] + pub const fn out_eof_des_addr_ch4(&self) -> &OUT_EOF_DES_ADDR_CH4 { + &self.out_eof_des_addr_ch4 + } + #[doc = "0x42c - TX CH4 next dscr addr register"] + #[inline(always)] + pub const fn out_dscr_ch4(&self) -> &OUT_DSCR_CH4 { + &self.out_dscr_ch4 + } + #[doc = "0x430 - TX CH4 last dscr addr register"] + #[inline(always)] + pub const fn out_dscr_bf0_ch4(&self) -> &OUT_DSCR_BF0_CH4 { + &self.out_dscr_bf0_ch4 + } + #[doc = "0x434 - TX CH4 second-to-last dscr addr register"] + #[inline(always)] + pub const fn out_dscr_bf1_ch4(&self) -> &OUT_DSCR_BF1_CH4 { + &self.out_dscr_bf1_ch4 + } + #[doc = "0x43c - TX CH4 arb register"] + #[inline(always)] + pub const fn out_arb_ch4(&self) -> &OUT_ARB_CH4 { + &self.out_arb_ch4 + } + #[doc = "0x468 - TX CH4 ETM config register"] + #[inline(always)] + pub const fn out_etm_conf_ch4(&self) -> &OUT_ETM_CONF_CH4 { + &self.out_etm_conf_ch4 + } + #[doc = "0x470 - tx CH4 buf len register"] + #[inline(always)] + pub const fn out_buf_len_ch4(&self) -> &OUT_BUF_LEN_CH4 { + &self.out_buf_len_ch4 + } + #[doc = "0x474 - tx CH4 fifo byte cnt register"] + #[inline(always)] + pub const fn out_fifo_bcnt_ch4(&self) -> &OUT_FIFO_BCNT_CH4 { + &self.out_fifo_bcnt_ch4 + } + #[doc = "0x478 - tx CH4 push byte cnt register"] + #[inline(always)] + pub const fn out_push_bytecnt_ch4(&self) -> &OUT_PUSH_BYTECNT_CH4 { + &self.out_push_bytecnt_ch4 + } + #[doc = "0x47c - tx CH4 xaddr register"] + #[inline(always)] + pub const fn out_xaddr_ch4(&self) -> &OUT_XADDR_CH4 { + &self.out_xaddr_ch4 + } + #[doc = "0x480 - tx CH4 block buf len register"] + #[inline(always)] + pub const fn out_block_buf_len_ch4(&self) -> &OUT_BLOCK_BUF_LEN_CH4 { + &self.out_block_buf_len_ch4 + } + #[doc = "0x500 - RX CH0 config0 register"] + #[inline(always)] + pub const fn in_conf0_ch0(&self) -> &IN_CONF0_CH0 { + &self.in_conf0_ch0 + } + #[doc = "0x504 - RX CH0 interrupt raw register"] + #[inline(always)] + pub const fn in_int_raw_ch0(&self) -> &IN_INT_RAW_CH0 { + &self.in_int_raw_ch0 + } + #[doc = "0x508 - RX CH0 interrupt ena register"] + #[inline(always)] + pub const fn in_int_ena_ch0(&self) -> &IN_INT_ENA_CH0 { + &self.in_int_ena_ch0 + } + #[doc = "0x50c - RX CH0 interrupt st register"] + #[inline(always)] + pub const fn in_int_st_ch0(&self) -> &IN_INT_ST_CH0 { + &self.in_int_st_ch0 + } + #[doc = "0x510 - RX CH0 interrupt clr register"] + #[inline(always)] + pub const fn in_int_clr_ch0(&self) -> &IN_INT_CLR_CH0 { + &self.in_int_clr_ch0 + } + #[doc = "0x514 - RX CH0 INFIFO status register"] + #[inline(always)] + pub const fn infifo_status_ch0(&self) -> &INFIFO_STATUS_CH0 { + &self.infifo_status_ch0 + } + #[doc = "0x518 - RX CH0 INFIFO pop register"] + #[inline(always)] + pub const fn in_pop_ch0(&self) -> &IN_POP_CH0 { + &self.in_pop_ch0 + } + #[doc = "0x51c - RX CH0 in_link dscr ctrl register"] + #[inline(always)] + pub const fn in_link_conf_ch0(&self) -> &IN_LINK_CONF_CH0 { + &self.in_link_conf_ch0 + } + #[doc = "0x520 - RX CH0 in_link dscr addr register"] + #[inline(always)] + pub const fn in_link_addr_ch0(&self) -> &IN_LINK_ADDR_CH0 { + &self.in_link_addr_ch0 + } + #[doc = "0x524 - RX CH0 state register"] + #[inline(always)] + pub const fn in_state_ch0(&self) -> &IN_STATE_CH0 { + &self.in_state_ch0 + } + #[doc = "0x528 - RX CH0 eof des addr register"] + #[inline(always)] + pub const fn in_suc_eof_des_addr_ch0(&self) -> &IN_SUC_EOF_DES_ADDR_CH0 { + &self.in_suc_eof_des_addr_ch0 + } + #[doc = "0x52c - RX CH0 err eof des addr register"] + #[inline(always)] + pub const fn in_err_eof_des_addr_ch0(&self) -> &IN_ERR_EOF_DES_ADDR_CH0 { + &self.in_err_eof_des_addr_ch0 + } + #[doc = "0x530 - RX CH0 next dscr addr register"] + #[inline(always)] + pub const fn in_dscr_ch0(&self) -> &IN_DSCR_CH0 { + &self.in_dscr_ch0 + } + #[doc = "0x534 - RX CH0 last dscr addr register"] + #[inline(always)] + pub const fn in_dscr_bf0_ch0(&self) -> &IN_DSCR_BF0_CH0 { + &self.in_dscr_bf0_ch0 + } + #[doc = "0x538 - RX CH0 second-to-last dscr addr register"] + #[inline(always)] + pub const fn in_dscr_bf1_ch0(&self) -> &IN_DSCR_BF1_CH0 { + &self.in_dscr_bf1_ch0 + } + #[doc = "0x540 - RX CH0 arb register"] + #[inline(always)] + pub const fn in_arb_ch0(&self) -> &IN_ARB_CH0 { + &self.in_arb_ch0 + } + #[doc = "0x548 - RX CH0 reorder power config register"] + #[inline(always)] + pub const fn in_ro_pd_conf_ch0(&self) -> &IN_RO_PD_CONF_CH0 { + &self.in_ro_pd_conf_ch0 + } + #[doc = "0x56c - RX CH0 ETM config register"] + #[inline(always)] + pub const fn in_etm_conf_ch0(&self) -> &IN_ETM_CONF_CH0 { + &self.in_etm_conf_ch0 + } + #[doc = "0x580 - rx CH0 fifo cnt register"] + #[inline(always)] + pub const fn in_fifo_cnt_ch0(&self) -> &IN_FIFO_CNT_CH0 { + &self.in_fifo_cnt_ch0 + } + #[doc = "0x584 - rx CH0 pop data cnt register"] + #[inline(always)] + pub const fn in_pop_data_cnt_ch0(&self) -> &IN_POP_DATA_CNT_CH0 { + &self.in_pop_data_cnt_ch0 + } + #[doc = "0x588 - rx CH0 xaddr register"] + #[inline(always)] + pub const fn in_xaddr_ch0(&self) -> &IN_XADDR_CH0 { + &self.in_xaddr_ch0 + } + #[doc = "0x58c - rx CH0 buf len hb rcv register"] + #[inline(always)] + pub const fn in_buf_hb_rcv_ch0(&self) -> &IN_BUF_HB_RCV_CH0 { + &self.in_buf_hb_rcv_ch0 + } + #[doc = "0x600 - RX CH1 config0 register"] + #[inline(always)] + pub const fn in_conf0_ch1(&self) -> &IN_CONF0_CH1 { + &self.in_conf0_ch1 + } + #[doc = "0x604 - RX CH1 interrupt raw register"] + #[inline(always)] + pub const fn in_int_raw_ch1(&self) -> &IN_INT_RAW_CH1 { + &self.in_int_raw_ch1 + } + #[doc = "0x608 - RX CH1 interrupt ena register"] + #[inline(always)] + pub const fn in_int_ena_ch1(&self) -> &IN_INT_ENA_CH1 { + &self.in_int_ena_ch1 + } + #[doc = "0x60c - RX CH1 interrupt st register"] + #[inline(always)] + pub const fn in_int_st_ch1(&self) -> &IN_INT_ST_CH1 { + &self.in_int_st_ch1 + } + #[doc = "0x610 - RX CH1 interrupt clr register"] + #[inline(always)] + pub const fn in_int_clr_ch1(&self) -> &IN_INT_CLR_CH1 { + &self.in_int_clr_ch1 + } + #[doc = "0x614 - RX CH1 INFIFO status register"] + #[inline(always)] + pub const fn infifo_status_ch1(&self) -> &INFIFO_STATUS_CH1 { + &self.infifo_status_ch1 + } + #[doc = "0x618 - RX CH1 INFIFO pop register"] + #[inline(always)] + pub const fn in_pop_ch1(&self) -> &IN_POP_CH1 { + &self.in_pop_ch1 + } + #[doc = "0x61c - RX CH1 in_link dscr ctrl register"] + #[inline(always)] + pub const fn in_link_conf_ch1(&self) -> &IN_LINK_CONF_CH1 { + &self.in_link_conf_ch1 + } + #[doc = "0x620 - RX CH1 in_link dscr addr register"] + #[inline(always)] + pub const fn in_link_addr_ch1(&self) -> &IN_LINK_ADDR_CH1 { + &self.in_link_addr_ch1 + } + #[doc = "0x624 - RX CH1 state register"] + #[inline(always)] + pub const fn in_state_ch1(&self) -> &IN_STATE_CH1 { + &self.in_state_ch1 + } + #[doc = "0x628 - RX CH1 eof des addr register"] + #[inline(always)] + pub const fn in_suc_eof_des_addr_ch1(&self) -> &IN_SUC_EOF_DES_ADDR_CH1 { + &self.in_suc_eof_des_addr_ch1 + } + #[doc = "0x62c - RX CH1 err eof des addr register"] + #[inline(always)] + pub const fn in_err_eof_des_addr_ch1(&self) -> &IN_ERR_EOF_DES_ADDR_CH1 { + &self.in_err_eof_des_addr_ch1 + } + #[doc = "0x630 - RX CH1 next dscr addr register"] + #[inline(always)] + pub const fn in_dscr_ch1(&self) -> &IN_DSCR_CH1 { + &self.in_dscr_ch1 + } + #[doc = "0x634 - RX CH1 last dscr addr register"] + #[inline(always)] + pub const fn in_dscr_bf0_ch1(&self) -> &IN_DSCR_BF0_CH1 { + &self.in_dscr_bf0_ch1 + } + #[doc = "0x638 - RX CH1 second-to-last dscr addr register"] + #[inline(always)] + pub const fn in_dscr_bf1_ch1(&self) -> &IN_DSCR_BF1_CH1 { + &self.in_dscr_bf1_ch1 + } + #[doc = "0x640 - RX CH1 arb register"] + #[inline(always)] + pub const fn in_arb_ch1(&self) -> &IN_ARB_CH1 { + &self.in_arb_ch1 + } + #[doc = "0x648 - RX CH1 ETM config register"] + #[inline(always)] + pub const fn in_etm_conf_ch1(&self) -> &IN_ETM_CONF_CH1 { + &self.in_etm_conf_ch1 + } + #[doc = "0x680 - rx CH1 fifo cnt register"] + #[inline(always)] + pub const fn in_fifo_cnt_ch1(&self) -> &IN_FIFO_CNT_CH1 { + &self.in_fifo_cnt_ch1 + } + #[doc = "0x684 - rx CH1 pop data cnt register"] + #[inline(always)] + pub const fn in_pop_data_cnt_ch1(&self) -> &IN_POP_DATA_CNT_CH1 { + &self.in_pop_data_cnt_ch1 + } + #[doc = "0x688 - rx CH1 xaddr register"] + #[inline(always)] + pub const fn in_xaddr_ch1(&self) -> &IN_XADDR_CH1 { + &self.in_xaddr_ch1 + } + #[doc = "0x68c - rx CH1 buf len hb rcv register"] + #[inline(always)] + pub const fn in_buf_hb_rcv_ch1(&self) -> &IN_BUF_HB_RCV_CH1 { + &self.in_buf_hb_rcv_ch1 + } + #[doc = "0x700 - RX CH2 config0 register"] + #[inline(always)] + pub const fn in_conf0_ch2(&self) -> &IN_CONF0_CH2 { + &self.in_conf0_ch2 + } + #[doc = "0x704 - RX CH2 interrupt raw register"] + #[inline(always)] + pub const fn in_int_raw_ch2(&self) -> &IN_INT_RAW_CH2 { + &self.in_int_raw_ch2 + } + #[doc = "0x708 - RX CH2 interrupt ena register"] + #[inline(always)] + pub const fn in_int_ena_ch2(&self) -> &IN_INT_ENA_CH2 { + &self.in_int_ena_ch2 + } + #[doc = "0x70c - RX CH2 interrupt st register"] + #[inline(always)] + pub const fn in_int_st_ch2(&self) -> &IN_INT_ST_CH2 { + &self.in_int_st_ch2 + } + #[doc = "0x710 - RX CH2 interrupt clr register"] + #[inline(always)] + pub const fn in_int_clr_ch2(&self) -> &IN_INT_CLR_CH2 { + &self.in_int_clr_ch2 + } + #[doc = "0x714 - RX CH2 INFIFO status register"] + #[inline(always)] + pub const fn infifo_status_ch2(&self) -> &INFIFO_STATUS_CH2 { + &self.infifo_status_ch2 + } + #[doc = "0x718 - RX CH2 INFIFO pop register"] + #[inline(always)] + pub const fn in_pop_ch2(&self) -> &IN_POP_CH2 { + &self.in_pop_ch2 + } + #[doc = "0x71c - RX CH2 in_link dscr ctrl register"] + #[inline(always)] + pub const fn in_link_conf_ch2(&self) -> &IN_LINK_CONF_CH2 { + &self.in_link_conf_ch2 + } + #[doc = "0x720 - RX CH2 in_link dscr addr register"] + #[inline(always)] + pub const fn in_link_addr_ch2(&self) -> &IN_LINK_ADDR_CH2 { + &self.in_link_addr_ch2 + } + #[doc = "0x724 - RX CH2 state register"] + #[inline(always)] + pub const fn in_state_ch2(&self) -> &IN_STATE_CH2 { + &self.in_state_ch2 + } + #[doc = "0x728 - RX CH2 eof des addr register"] + #[inline(always)] + pub const fn in_suc_eof_des_addr_ch2(&self) -> &IN_SUC_EOF_DES_ADDR_CH2 { + &self.in_suc_eof_des_addr_ch2 + } + #[doc = "0x72c - RX CH2 err eof des addr register"] + #[inline(always)] + pub const fn in_err_eof_des_addr_ch2(&self) -> &IN_ERR_EOF_DES_ADDR_CH2 { + &self.in_err_eof_des_addr_ch2 + } + #[doc = "0x730 - RX CH2 next dscr addr register"] + #[inline(always)] + pub const fn in_dscr_ch2(&self) -> &IN_DSCR_CH2 { + &self.in_dscr_ch2 + } + #[doc = "0x734 - RX CH2 last dscr addr register"] + #[inline(always)] + pub const fn in_dscr_bf0_ch2(&self) -> &IN_DSCR_BF0_CH2 { + &self.in_dscr_bf0_ch2 + } + #[doc = "0x738 - RX CH2 second-to-last dscr addr register"] + #[inline(always)] + pub const fn in_dscr_bf1_ch2(&self) -> &IN_DSCR_BF1_CH2 { + &self.in_dscr_bf1_ch2 + } + #[doc = "0x740 - RX CH2 arb register"] + #[inline(always)] + pub const fn in_arb_ch2(&self) -> &IN_ARB_CH2 { + &self.in_arb_ch2 + } + #[doc = "0x748 - RX CH2 ETM config register"] + #[inline(always)] + pub const fn in_etm_conf_ch2(&self) -> &IN_ETM_CONF_CH2 { + &self.in_etm_conf_ch2 + } + #[doc = "0x780 - rx CH2 fifo cnt register"] + #[inline(always)] + pub const fn in_fifo_cnt_ch2(&self) -> &IN_FIFO_CNT_CH2 { + &self.in_fifo_cnt_ch2 + } + #[doc = "0x784 - rx CH2 pop data cnt register"] + #[inline(always)] + pub const fn in_pop_data_cnt_ch2(&self) -> &IN_POP_DATA_CNT_CH2 { + &self.in_pop_data_cnt_ch2 + } + #[doc = "0x788 - rx CH2 xaddr register"] + #[inline(always)] + pub const fn in_xaddr_ch2(&self) -> &IN_XADDR_CH2 { + &self.in_xaddr_ch2 + } + #[doc = "0x78c - rx CH2 buf len hb rcv register"] + #[inline(always)] + pub const fn in_buf_hb_rcv_ch2(&self) -> &IN_BUF_HB_RCV_CH2 { + &self.in_buf_hb_rcv_ch2 + } + #[doc = "0x800 - RX CH3 config0 register"] + #[inline(always)] + pub const fn in_conf0_ch3(&self) -> &IN_CONF0_CH3 { + &self.in_conf0_ch3 + } + #[doc = "0x804 - RX CH3 interrupt raw register"] + #[inline(always)] + pub const fn in_int_raw_ch3(&self) -> &IN_INT_RAW_CH3 { + &self.in_int_raw_ch3 + } + #[doc = "0x808 - RX CH3 interrupt ena register"] + #[inline(always)] + pub const fn in_int_ena_ch3(&self) -> &IN_INT_ENA_CH3 { + &self.in_int_ena_ch3 + } + #[doc = "0x80c - RX CH3 interrupt st register"] + #[inline(always)] + pub const fn in_int_st_ch3(&self) -> &IN_INT_ST_CH3 { + &self.in_int_st_ch3 + } + #[doc = "0x810 - RX CH3 interrupt clr register"] + #[inline(always)] + pub const fn in_int_clr_ch3(&self) -> &IN_INT_CLR_CH3 { + &self.in_int_clr_ch3 + } + #[doc = "0x814 - RX CH3 INFIFO status register"] + #[inline(always)] + pub const fn infifo_status_ch3(&self) -> &INFIFO_STATUS_CH3 { + &self.infifo_status_ch3 + } + #[doc = "0x818 - RX CH3 INFIFO pop register"] + #[inline(always)] + pub const fn in_pop_ch3(&self) -> &IN_POP_CH3 { + &self.in_pop_ch3 + } + #[doc = "0x81c - RX CH3 in_link dscr ctrl register"] + #[inline(always)] + pub const fn in_link_conf_ch3(&self) -> &IN_LINK_CONF_CH3 { + &self.in_link_conf_ch3 + } + #[doc = "0x820 - RX CH3 in_link dscr addr register"] + #[inline(always)] + pub const fn in_link_addr_ch3(&self) -> &IN_LINK_ADDR_CH3 { + &self.in_link_addr_ch3 + } + #[doc = "0x824 - RX CH3 state register"] + #[inline(always)] + pub const fn in_state_ch3(&self) -> &IN_STATE_CH3 { + &self.in_state_ch3 + } + #[doc = "0x828 - RX CH3 eof des addr register"] + #[inline(always)] + pub const fn in_suc_eof_des_addr_ch3(&self) -> &IN_SUC_EOF_DES_ADDR_CH3 { + &self.in_suc_eof_des_addr_ch3 + } + #[doc = "0x82c - RX CH3 err eof des addr register"] + #[inline(always)] + pub const fn in_err_eof_des_addr_ch3(&self) -> &IN_ERR_EOF_DES_ADDR_CH3 { + &self.in_err_eof_des_addr_ch3 + } + #[doc = "0x830 - RX CH3 next dscr addr register"] + #[inline(always)] + pub const fn in_dscr_ch3(&self) -> &IN_DSCR_CH3 { + &self.in_dscr_ch3 + } + #[doc = "0x834 - RX CH3 last dscr addr register"] + #[inline(always)] + pub const fn in_dscr_bf0_ch3(&self) -> &IN_DSCR_BF0_CH3 { + &self.in_dscr_bf0_ch3 + } + #[doc = "0x838 - RX CH3 second-to-last dscr addr register"] + #[inline(always)] + pub const fn in_dscr_bf1_ch3(&self) -> &IN_DSCR_BF1_CH3 { + &self.in_dscr_bf1_ch3 + } + #[doc = "0x840 - RX CH3 arb register"] + #[inline(always)] + pub const fn in_arb_ch3(&self) -> &IN_ARB_CH3 { + &self.in_arb_ch3 + } + #[doc = "0x848 - RX CH3 ETM config register"] + #[inline(always)] + pub const fn in_etm_conf_ch3(&self) -> &IN_ETM_CONF_CH3 { + &self.in_etm_conf_ch3 + } + #[doc = "0x880 - rx CH3 fifo cnt register"] + #[inline(always)] + pub const fn in_fifo_cnt_ch3(&self) -> &IN_FIFO_CNT_CH3 { + &self.in_fifo_cnt_ch3 + } + #[doc = "0x884 - rx CH3 pop data cnt register"] + #[inline(always)] + pub const fn in_pop_data_cnt_ch3(&self) -> &IN_POP_DATA_CNT_CH3 { + &self.in_pop_data_cnt_ch3 + } + #[doc = "0x888 - rx CH3 xaddr register"] + #[inline(always)] + pub const fn in_xaddr_ch3(&self) -> &IN_XADDR_CH3 { + &self.in_xaddr_ch3 + } + #[doc = "0x88c - rx CH3 buf len hb rcv register"] + #[inline(always)] + pub const fn in_buf_hb_rcv_ch3(&self) -> &IN_BUF_HB_RCV_CH3 { + &self.in_buf_hb_rcv_ch3 + } + #[doc = "0x900 - RX CH4 config0 register"] + #[inline(always)] + pub const fn in_conf0_ch4(&self) -> &IN_CONF0_CH4 { + &self.in_conf0_ch4 + } + #[doc = "0x904 - RX CH4 interrupt raw register"] + #[inline(always)] + pub const fn in_int_raw_ch4(&self) -> &IN_INT_RAW_CH4 { + &self.in_int_raw_ch4 + } + #[doc = "0x908 - RX CH4 interrupt ena register"] + #[inline(always)] + pub const fn in_int_ena_ch4(&self) -> &IN_INT_ENA_CH4 { + &self.in_int_ena_ch4 + } + #[doc = "0x90c - RX CH4 interrupt st register"] + #[inline(always)] + pub const fn in_int_st_ch4(&self) -> &IN_INT_ST_CH4 { + &self.in_int_st_ch4 + } + #[doc = "0x910 - RX CH4 interrupt clr register"] + #[inline(always)] + pub const fn in_int_clr_ch4(&self) -> &IN_INT_CLR_CH4 { + &self.in_int_clr_ch4 + } + #[doc = "0x914 - RX CH4 INFIFO status register"] + #[inline(always)] + pub const fn infifo_status_ch4(&self) -> &INFIFO_STATUS_CH4 { + &self.infifo_status_ch4 + } + #[doc = "0x918 - RX CH4 INFIFO pop register"] + #[inline(always)] + pub const fn in_pop_ch4(&self) -> &IN_POP_CH4 { + &self.in_pop_ch4 + } + #[doc = "0x91c - RX CH4 in_link dscr ctrl register"] + #[inline(always)] + pub const fn in_link_conf_ch4(&self) -> &IN_LINK_CONF_CH4 { + &self.in_link_conf_ch4 + } + #[doc = "0x920 - RX CH4 in_link dscr addr register"] + #[inline(always)] + pub const fn in_link_addr_ch4(&self) -> &IN_LINK_ADDR_CH4 { + &self.in_link_addr_ch4 + } + #[doc = "0x924 - RX CH4 state register"] + #[inline(always)] + pub const fn in_state_ch4(&self) -> &IN_STATE_CH4 { + &self.in_state_ch4 + } + #[doc = "0x928 - RX CH4 eof des addr register"] + #[inline(always)] + pub const fn in_suc_eof_des_addr_ch4(&self) -> &IN_SUC_EOF_DES_ADDR_CH4 { + &self.in_suc_eof_des_addr_ch4 + } + #[doc = "0x92c - RX CH4 err eof des addr register"] + #[inline(always)] + pub const fn in_err_eof_des_addr_ch4(&self) -> &IN_ERR_EOF_DES_ADDR_CH4 { + &self.in_err_eof_des_addr_ch4 + } + #[doc = "0x930 - RX CH4 next dscr addr register"] + #[inline(always)] + pub const fn in_dscr_ch4(&self) -> &IN_DSCR_CH4 { + &self.in_dscr_ch4 + } + #[doc = "0x934 - RX CH4 last dscr addr register"] + #[inline(always)] + pub const fn in_dscr_bf0_ch4(&self) -> &IN_DSCR_BF0_CH4 { + &self.in_dscr_bf0_ch4 + } + #[doc = "0x938 - RX CH4 second-to-last dscr addr register"] + #[inline(always)] + pub const fn in_dscr_bf1_ch4(&self) -> &IN_DSCR_BF1_CH4 { + &self.in_dscr_bf1_ch4 + } + #[doc = "0x940 - RX CH4 arb register"] + #[inline(always)] + pub const fn in_arb_ch4(&self) -> &IN_ARB_CH4 { + &self.in_arb_ch4 + } + #[doc = "0x948 - RX CH4 ETM config register"] + #[inline(always)] + pub const fn in_etm_conf_ch4(&self) -> &IN_ETM_CONF_CH4 { + &self.in_etm_conf_ch4 + } + #[doc = "0x980 - rx CH4 fifo cnt register"] + #[inline(always)] + pub const fn in_fifo_cnt_ch4(&self) -> &IN_FIFO_CNT_CH4 { + &self.in_fifo_cnt_ch4 + } + #[doc = "0x984 - rx CH4 pop data cnt register"] + #[inline(always)] + pub const fn in_pop_data_cnt_ch4(&self) -> &IN_POP_DATA_CNT_CH4 { + &self.in_pop_data_cnt_ch4 + } + #[doc = "0x988 - rx CH4 xaddr register"] + #[inline(always)] + pub const fn in_xaddr_ch4(&self) -> &IN_XADDR_CH4 { + &self.in_xaddr_ch4 + } + #[doc = "0x98c - rx CH4 buf len hb rcv register"] + #[inline(always)] + pub const fn in_buf_hb_rcv_ch4(&self) -> &IN_BUF_HB_RCV_CH4 { + &self.in_buf_hb_rcv_ch4 + } + #[doc = "0xa00 - RX CH5 config0 register"] + #[inline(always)] + pub const fn in_conf0_ch5(&self) -> &IN_CONF0_CH5 { + &self.in_conf0_ch5 + } + #[doc = "0xa04 - RX CH5 config1 register"] + #[inline(always)] + pub const fn in_conf1_ch5(&self) -> &IN_CONF1_CH5 { + &self.in_conf1_ch5 + } + #[doc = "0xa08 - RX CH5 config2 register"] + #[inline(always)] + pub const fn in_conf2_ch5(&self) -> &IN_CONF2_CH5 { + &self.in_conf2_ch5 + } + #[doc = "0xa0c - RX CH5 config3 register"] + #[inline(always)] + pub const fn in_conf3_ch5(&self) -> &IN_CONF3_CH5 { + &self.in_conf3_ch5 + } + #[doc = "0xa10 - RX CH5 interrupt raw register"] + #[inline(always)] + pub const fn in_int_raw_ch5(&self) -> &IN_INT_RAW_CH5 { + &self.in_int_raw_ch5 + } + #[doc = "0xa14 - RX CH5 interrupt ena register"] + #[inline(always)] + pub const fn in_int_ena_ch5(&self) -> &IN_INT_ENA_CH5 { + &self.in_int_ena_ch5 + } + #[doc = "0xa18 - RX CH5 interrupt st register"] + #[inline(always)] + pub const fn in_int_st_ch5(&self) -> &IN_INT_ST_CH5 { + &self.in_int_st_ch5 + } + #[doc = "0xa1c - RX CH5 interrupt clr register"] + #[inline(always)] + pub const fn in_int_clr_ch5(&self) -> &IN_INT_CLR_CH5 { + &self.in_int_clr_ch5 + } + #[doc = "0xa20 - RX CH5 INFIFO status register"] + #[inline(always)] + pub const fn infifo_status_ch5(&self) -> &INFIFO_STATUS_CH5 { + &self.infifo_status_ch5 + } + #[doc = "0xa24 - RX CH5 INFIFO pop register"] + #[inline(always)] + pub const fn in_pop_ch5(&self) -> &IN_POP_CH5 { + &self.in_pop_ch5 + } + #[doc = "0xa28 - RX CH5 state register"] + #[inline(always)] + pub const fn in_state_ch5(&self) -> &IN_STATE_CH5 { + &self.in_state_ch5 + } + #[doc = "0xa40 - RX CH5 arb register"] + #[inline(always)] + pub const fn in_arb_ch5(&self) -> &IN_ARB_CH5 { + &self.in_arb_ch5 + } + #[doc = "0xa80 - rx CH5 fifo cnt register"] + #[inline(always)] + pub const fn in_fifo_cnt_ch5(&self) -> &IN_FIFO_CNT_CH5 { + &self.in_fifo_cnt_ch5 + } + #[doc = "0xa84 - rx CH5 pop data cnt register"] + #[inline(always)] + pub const fn in_pop_data_cnt_ch5(&self) -> &IN_POP_DATA_CNT_CH5 { + &self.in_pop_data_cnt_ch5 + } + #[doc = "0xa88 - rx CH5 xaddr register"] + #[inline(always)] + pub const fn in_xaddr_ch5(&self) -> &IN_XADDR_CH5 { + &self.in_xaddr_ch5 + } + #[doc = "0xa8c - rx CH5 buf len hb rcv register"] + #[inline(always)] + pub const fn in_buf_hb_rcv_ch5(&self) -> &IN_BUF_HB_RCV_CH5 { + &self.in_buf_hb_rcv_ch5 + } + #[doc = "0xb00 - inter memory axi err register"] + #[inline(always)] + pub const fn inter_axi_err(&self) -> &INTER_AXI_ERR { + &self.inter_axi_err + } + #[doc = "0xb04 - exter memory axi err register"] + #[inline(always)] + pub const fn exter_axi_err(&self) -> &EXTER_AXI_ERR { + &self.exter_axi_err + } + #[doc = "0xb08 - axi reset config register"] + #[inline(always)] + pub const fn rst_conf(&self) -> &RST_CONF { + &self.rst_conf + } + #[doc = "0xb0c - Start address of inter memory range0 register"] + #[inline(always)] + pub const fn inter_mem_start_addr0(&self) -> &INTER_MEM_START_ADDR0 { + &self.inter_mem_start_addr0 + } + #[doc = "0xb10 - end address of inter memory range0 register"] + #[inline(always)] + pub const fn inter_mem_end_addr0(&self) -> &INTER_MEM_END_ADDR0 { + &self.inter_mem_end_addr0 + } + #[doc = "0xb14 - Start address of inter memory range1 register"] + #[inline(always)] + pub const fn inter_mem_start_addr1(&self) -> &INTER_MEM_START_ADDR1 { + &self.inter_mem_start_addr1 + } + #[doc = "0xb18 - end address of inter memory range1 register"] + #[inline(always)] + pub const fn inter_mem_end_addr1(&self) -> &INTER_MEM_END_ADDR1 { + &self.inter_mem_end_addr1 + } + #[doc = "0xb20 - Start address of exter memory range0 register"] + #[inline(always)] + pub const fn exter_mem_start_addr0(&self) -> &EXTER_MEM_START_ADDR0 { + &self.exter_mem_start_addr0 + } + #[doc = "0xb24 - end address of exter memory range0 register"] + #[inline(always)] + pub const fn exter_mem_end_addr0(&self) -> &EXTER_MEM_END_ADDR0 { + &self.exter_mem_end_addr0 + } + #[doc = "0xb28 - Start address of exter memory range1 register"] + #[inline(always)] + pub const fn exter_mem_start_addr1(&self) -> &EXTER_MEM_START_ADDR1 { + &self.exter_mem_start_addr1 + } + #[doc = "0xb2c - end address of exter memory range1 register"] + #[inline(always)] + pub const fn exter_mem_end_addr1(&self) -> &EXTER_MEM_END_ADDR1 { + &self.exter_mem_end_addr1 + } + #[doc = "0xb30 - reserved"] + #[inline(always)] + pub const fn out_arb_config(&self) -> &OUT_ARB_CONFIG { + &self.out_arb_config + } + #[doc = "0xb34 - reserved"] + #[inline(always)] + pub const fn in_arb_config(&self) -> &IN_ARB_CONFIG { + &self.in_arb_config + } + #[doc = "0xb3c - reserved"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } + #[doc = "0xb50 - counter reset register"] + #[inline(always)] + pub const fn counter_rst(&self) -> &COUNTER_RST { + &self.counter_rst + } + #[doc = "0xb54 - rx ch0 counter register"] + #[inline(always)] + pub const fn rx_ch0_counter(&self) -> &RX_CH0_COUNTER { + &self.rx_ch0_counter + } + #[doc = "0xb58 - rx ch1 counter register"] + #[inline(always)] + pub const fn rx_ch1_counter(&self) -> &RX_CH1_COUNTER { + &self.rx_ch1_counter + } + #[doc = "0xb5c - rx ch2 counter register"] + #[inline(always)] + pub const fn rx_ch2_counter(&self) -> &RX_CH2_COUNTER { + &self.rx_ch2_counter + } + #[doc = "0xb60 - rx ch5 counter register"] + #[inline(always)] + pub const fn rx_ch5_counter(&self) -> &RX_CH5_COUNTER { + &self.rx_ch5_counter + } +} +#[doc = "OUT_CONF0_CH0 (rw) register accessor: TX CH0 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0_ch0`] module"] +pub type OUT_CONF0_CH0 = crate::Reg; +#[doc = "TX CH0 config0 register"] +pub mod out_conf0_ch0; +#[doc = "OUT_INT_RAW_CH0 (rw) register accessor: TX CH0 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_raw_ch0`] module"] +pub type OUT_INT_RAW_CH0 = crate::Reg; +#[doc = "TX CH0 interrupt raw register"] +pub mod out_int_raw_ch0; +#[doc = "OUT_INT_ENA_CH0 (rw) register accessor: TX CH0 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_ena_ch0`] module"] +pub type OUT_INT_ENA_CH0 = crate::Reg; +#[doc = "TX CH0 interrupt ena register"] +pub mod out_int_ena_ch0; +#[doc = "OUT_INT_ST_CH0 (r) register accessor: TX CH0 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_st_ch0`] module"] +pub type OUT_INT_ST_CH0 = crate::Reg; +#[doc = "TX CH0 interrupt st register"] +pub mod out_int_st_ch0; +#[doc = "OUT_INT_CLR_CH0 (w) register accessor: TX CH0 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_clr_ch0`] module"] +pub type OUT_INT_CLR_CH0 = crate::Reg; +#[doc = "TX CH0 interrupt clr register"] +pub mod out_int_clr_ch0; +#[doc = "OUTFIFO_STATUS_CH0 (r) register accessor: TX CH0 outfifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outfifo_status_ch0`] module"] +pub type OUTFIFO_STATUS_CH0 = crate::Reg; +#[doc = "TX CH0 outfifo status register"] +pub mod outfifo_status_ch0; +#[doc = "OUT_PUSH_CH0 (rw) register accessor: TX CH0 outfifo push register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_ch0`] module"] +pub type OUT_PUSH_CH0 = crate::Reg; +#[doc = "TX CH0 outfifo push register"] +pub mod out_push_ch0; +#[doc = "OUT_LINK_CONF_CH0 (rw) register accessor: TX CH0 out_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_conf_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_conf_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_conf_ch0`] module"] +pub type OUT_LINK_CONF_CH0 = crate::Reg; +#[doc = "TX CH0 out_link dscr ctrl register"] +pub mod out_link_conf_ch0; +#[doc = "OUT_LINK_ADDR_CH0 (rw) register accessor: TX CH0 out_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_addr_ch0`] module"] +pub type OUT_LINK_ADDR_CH0 = crate::Reg; +#[doc = "TX CH0 out_link dscr addr register"] +pub mod out_link_addr_ch0; +#[doc = "OUT_STATE_CH0 (r) register accessor: TX CH0 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_state_ch0`] module"] +pub type OUT_STATE_CH0 = crate::Reg; +#[doc = "TX CH0 state register"] +pub mod out_state_ch0; +#[doc = "OUT_EOF_DES_ADDR_CH0 (r) register accessor: TX CH0 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr_ch0`] module"] +pub type OUT_EOF_DES_ADDR_CH0 = crate::Reg; +#[doc = "TX CH0 eof des addr register"] +pub mod out_eof_des_addr_ch0; +#[doc = "OUT_DSCR_CH0 (r) register accessor: TX CH0 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_ch0`] module"] +pub type OUT_DSCR_CH0 = crate::Reg; +#[doc = "TX CH0 next dscr addr register"] +pub mod out_dscr_ch0; +#[doc = "OUT_DSCR_BF0_CH0 (r) register accessor: TX CH0 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf0_ch0`] module"] +pub type OUT_DSCR_BF0_CH0 = crate::Reg; +#[doc = "TX CH0 last dscr addr register"] +pub mod out_dscr_bf0_ch0; +#[doc = "OUT_DSCR_BF1_CH0 (r) register accessor: TX CH0 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf1_ch0`] module"] +pub type OUT_DSCR_BF1_CH0 = crate::Reg; +#[doc = "TX CH0 second-to-last dscr addr register"] +pub mod out_dscr_bf1_ch0; +#[doc = "OUT_ARB_CH0 (rw) register accessor: TX CH0 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_arb_ch0`] module"] +pub type OUT_ARB_CH0 = crate::Reg; +#[doc = "TX CH0 arb register"] +pub mod out_arb_ch0; +#[doc = "OUT_RO_STATUS_CH0 (r) register accessor: TX CH0 reorder status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ro_status_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_ro_status_ch0`] module"] +pub type OUT_RO_STATUS_CH0 = crate::Reg; +#[doc = "TX CH0 reorder status register"] +pub mod out_ro_status_ch0; +#[doc = "OUT_RO_PD_CONF_CH0 (rw) register accessor: TX CH0 reorder power config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ro_pd_conf_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_ro_pd_conf_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_ro_pd_conf_ch0`] module"] +pub type OUT_RO_PD_CONF_CH0 = crate::Reg; +#[doc = "TX CH0 reorder power config register"] +pub mod out_ro_pd_conf_ch0; +#[doc = "OUT_MODE_ENABLE_CH0 (rw) register accessor: tx CH0 mode enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_mode_enable_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_mode_enable_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_mode_enable_ch0`] module"] +pub type OUT_MODE_ENABLE_CH0 = crate::Reg; +#[doc = "tx CH0 mode enable register"] +pub mod out_mode_enable_ch0; +#[doc = "OUT_MODE_YUV_CH0 (rw) register accessor: tx CH0 test mode yuv value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_mode_yuv_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_mode_yuv_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_mode_yuv_ch0`] module"] +pub type OUT_MODE_YUV_CH0 = crate::Reg; +#[doc = "tx CH0 test mode yuv value register"] +pub mod out_mode_yuv_ch0; +#[doc = "OUT_ETM_CONF_CH0 (rw) register accessor: TX CH0 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_etm_conf_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_etm_conf_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_etm_conf_ch0`] module"] +pub type OUT_ETM_CONF_CH0 = crate::Reg; +#[doc = "TX CH0 ETM config register"] +pub mod out_etm_conf_ch0; +#[doc = "OUT_BUF_LEN_CH0 (r) register accessor: tx CH0 buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_buf_len_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_buf_len_ch0`] module"] +pub type OUT_BUF_LEN_CH0 = crate::Reg; +#[doc = "tx CH0 buf len register"] +pub mod out_buf_len_ch0; +#[doc = "OUT_FIFO_BCNT_CH0 (r) register accessor: tx CH0 fifo byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_fifo_bcnt_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_fifo_bcnt_ch0`] module"] +pub type OUT_FIFO_BCNT_CH0 = crate::Reg; +#[doc = "tx CH0 fifo byte cnt register"] +pub mod out_fifo_bcnt_ch0; +#[doc = "OUT_PUSH_BYTECNT_CH0 (r) register accessor: tx CH0 push byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_bytecnt_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_bytecnt_ch0`] module"] +pub type OUT_PUSH_BYTECNT_CH0 = crate::Reg; +#[doc = "tx CH0 push byte cnt register"] +pub mod out_push_bytecnt_ch0; +#[doc = "OUT_XADDR_CH0 (r) register accessor: tx CH0 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_xaddr_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_xaddr_ch0`] module"] +pub type OUT_XADDR_CH0 = crate::Reg; +#[doc = "tx CH0 xaddr register"] +pub mod out_xaddr_ch0; +#[doc = "OUT_CONF0_CH1 (rw) register accessor: TX CH1 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0_ch1`] module"] +pub type OUT_CONF0_CH1 = crate::Reg; +#[doc = "TX CH1 config0 register"] +pub mod out_conf0_ch1; +#[doc = "OUT_INT_RAW_CH1 (rw) register accessor: TX CH1 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_raw_ch1`] module"] +pub type OUT_INT_RAW_CH1 = crate::Reg; +#[doc = "TX CH1 interrupt raw register"] +pub mod out_int_raw_ch1; +#[doc = "OUT_INT_ENA_CH1 (rw) register accessor: TX CH1 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_ena_ch1`] module"] +pub type OUT_INT_ENA_CH1 = crate::Reg; +#[doc = "TX CH1 interrupt ena register"] +pub mod out_int_ena_ch1; +#[doc = "OUT_INT_ST_CH1 (r) register accessor: TX CH1 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_st_ch1`] module"] +pub type OUT_INT_ST_CH1 = crate::Reg; +#[doc = "TX CH1 interrupt st register"] +pub mod out_int_st_ch1; +#[doc = "OUT_INT_CLR_CH1 (w) register accessor: TX CH1 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_clr_ch1`] module"] +pub type OUT_INT_CLR_CH1 = crate::Reg; +#[doc = "TX CH1 interrupt clr register"] +pub mod out_int_clr_ch1; +#[doc = "OUTFIFO_STATUS_CH1 (r) register accessor: TX CH1 outfifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outfifo_status_ch1`] module"] +pub type OUTFIFO_STATUS_CH1 = crate::Reg; +#[doc = "TX CH1 outfifo status register"] +pub mod outfifo_status_ch1; +#[doc = "OUT_PUSH_CH1 (rw) register accessor: TX CH1 outfifo push register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_ch1`] module"] +pub type OUT_PUSH_CH1 = crate::Reg; +#[doc = "TX CH1 outfifo push register"] +pub mod out_push_ch1; +#[doc = "OUT_LINK_CONF_CH1 (rw) register accessor: TX CH1 out_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_conf_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_conf_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_conf_ch1`] module"] +pub type OUT_LINK_CONF_CH1 = crate::Reg; +#[doc = "TX CH1 out_link dscr ctrl register"] +pub mod out_link_conf_ch1; +#[doc = "OUT_LINK_ADDR_CH1 (rw) register accessor: TX CH1 out_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_addr_ch1`] module"] +pub type OUT_LINK_ADDR_CH1 = crate::Reg; +#[doc = "TX CH1 out_link dscr addr register"] +pub mod out_link_addr_ch1; +#[doc = "OUT_STATE_CH1 (r) register accessor: TX CH1 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_state_ch1`] module"] +pub type OUT_STATE_CH1 = crate::Reg; +#[doc = "TX CH1 state register"] +pub mod out_state_ch1; +#[doc = "OUT_EOF_DES_ADDR_CH1 (r) register accessor: TX CH1 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr_ch1`] module"] +pub type OUT_EOF_DES_ADDR_CH1 = crate::Reg; +#[doc = "TX CH1 eof des addr register"] +pub mod out_eof_des_addr_ch1; +#[doc = "OUT_DSCR_CH1 (r) register accessor: TX CH1 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_ch1`] module"] +pub type OUT_DSCR_CH1 = crate::Reg; +#[doc = "TX CH1 next dscr addr register"] +pub mod out_dscr_ch1; +#[doc = "OUT_DSCR_BF0_CH1 (r) register accessor: TX CH1 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf0_ch1`] module"] +pub type OUT_DSCR_BF0_CH1 = crate::Reg; +#[doc = "TX CH1 last dscr addr register"] +pub mod out_dscr_bf0_ch1; +#[doc = "OUT_DSCR_BF1_CH1 (r) register accessor: TX CH1 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf1_ch1`] module"] +pub type OUT_DSCR_BF1_CH1 = crate::Reg; +#[doc = "TX CH1 second-to-last dscr addr register"] +pub mod out_dscr_bf1_ch1; +#[doc = "OUT_ARB_CH1 (rw) register accessor: TX CH1 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_arb_ch1`] module"] +pub type OUT_ARB_CH1 = crate::Reg; +#[doc = "TX CH1 arb register"] +pub mod out_arb_ch1; +#[doc = "OUT_ETM_CONF_CH1 (rw) register accessor: TX CH1 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_etm_conf_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_etm_conf_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_etm_conf_ch1`] module"] +pub type OUT_ETM_CONF_CH1 = crate::Reg; +#[doc = "TX CH1 ETM config register"] +pub mod out_etm_conf_ch1; +#[doc = "OUT_BUF_LEN_CH1 (r) register accessor: tx CH1 buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_buf_len_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_buf_len_ch1`] module"] +pub type OUT_BUF_LEN_CH1 = crate::Reg; +#[doc = "tx CH1 buf len register"] +pub mod out_buf_len_ch1; +#[doc = "OUT_FIFO_BCNT_CH1 (r) register accessor: tx CH1 fifo byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_fifo_bcnt_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_fifo_bcnt_ch1`] module"] +pub type OUT_FIFO_BCNT_CH1 = crate::Reg; +#[doc = "tx CH1 fifo byte cnt register"] +pub mod out_fifo_bcnt_ch1; +#[doc = "OUT_PUSH_BYTECNT_CH1 (r) register accessor: tx CH1 push byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_bytecnt_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_bytecnt_ch1`] module"] +pub type OUT_PUSH_BYTECNT_CH1 = crate::Reg; +#[doc = "tx CH1 push byte cnt register"] +pub mod out_push_bytecnt_ch1; +#[doc = "OUT_XADDR_CH1 (r) register accessor: tx CH1 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_xaddr_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_xaddr_ch1`] module"] +pub type OUT_XADDR_CH1 = crate::Reg; +#[doc = "tx CH1 xaddr register"] +pub mod out_xaddr_ch1; +#[doc = "OUT_CONF0_CH2 (rw) register accessor: TX CH2 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0_ch2`] module"] +pub type OUT_CONF0_CH2 = crate::Reg; +#[doc = "TX CH2 config0 register"] +pub mod out_conf0_ch2; +#[doc = "OUT_INT_RAW_CH2 (rw) register accessor: TX CH2 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_raw_ch2`] module"] +pub type OUT_INT_RAW_CH2 = crate::Reg; +#[doc = "TX CH2 interrupt raw register"] +pub mod out_int_raw_ch2; +#[doc = "OUT_INT_ENA_CH2 (rw) register accessor: TX CH2 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_ena_ch2`] module"] +pub type OUT_INT_ENA_CH2 = crate::Reg; +#[doc = "TX CH2 interrupt ena register"] +pub mod out_int_ena_ch2; +#[doc = "OUT_INT_ST_CH2 (r) register accessor: TX CH2 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_st_ch2`] module"] +pub type OUT_INT_ST_CH2 = crate::Reg; +#[doc = "TX CH2 interrupt st register"] +pub mod out_int_st_ch2; +#[doc = "OUT_INT_CLR_CH2 (w) register accessor: TX CH2 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_clr_ch2`] module"] +pub type OUT_INT_CLR_CH2 = crate::Reg; +#[doc = "TX CH2 interrupt clr register"] +pub mod out_int_clr_ch2; +#[doc = "OUTFIFO_STATUS_CH2 (r) register accessor: TX CH2 outfifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outfifo_status_ch2`] module"] +pub type OUTFIFO_STATUS_CH2 = crate::Reg; +#[doc = "TX CH2 outfifo status register"] +pub mod outfifo_status_ch2; +#[doc = "OUT_PUSH_CH2 (rw) register accessor: TX CH2 outfifo push register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_ch2`] module"] +pub type OUT_PUSH_CH2 = crate::Reg; +#[doc = "TX CH2 outfifo push register"] +pub mod out_push_ch2; +#[doc = "OUT_LINK_CONF_CH2 (rw) register accessor: TX CH2 out_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_conf_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_conf_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_conf_ch2`] module"] +pub type OUT_LINK_CONF_CH2 = crate::Reg; +#[doc = "TX CH2 out_link dscr ctrl register"] +pub mod out_link_conf_ch2; +#[doc = "OUT_LINK_ADDR_CH2 (rw) register accessor: TX CH2 out_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_addr_ch2`] module"] +pub type OUT_LINK_ADDR_CH2 = crate::Reg; +#[doc = "TX CH2 out_link dscr addr register"] +pub mod out_link_addr_ch2; +#[doc = "OUT_STATE_CH2 (r) register accessor: TX CH2 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_state_ch2`] module"] +pub type OUT_STATE_CH2 = crate::Reg; +#[doc = "TX CH2 state register"] +pub mod out_state_ch2; +#[doc = "OUT_EOF_DES_ADDR_CH2 (r) register accessor: TX CH2 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr_ch2`] module"] +pub type OUT_EOF_DES_ADDR_CH2 = crate::Reg; +#[doc = "TX CH2 eof des addr register"] +pub mod out_eof_des_addr_ch2; +#[doc = "OUT_DSCR_CH2 (r) register accessor: TX CH2 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_ch2`] module"] +pub type OUT_DSCR_CH2 = crate::Reg; +#[doc = "TX CH2 next dscr addr register"] +pub mod out_dscr_ch2; +#[doc = "OUT_DSCR_BF0_CH2 (r) register accessor: TX CH2 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf0_ch2`] module"] +pub type OUT_DSCR_BF0_CH2 = crate::Reg; +#[doc = "TX CH2 last dscr addr register"] +pub mod out_dscr_bf0_ch2; +#[doc = "OUT_DSCR_BF1_CH2 (r) register accessor: TX CH2 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf1_ch2`] module"] +pub type OUT_DSCR_BF1_CH2 = crate::Reg; +#[doc = "TX CH2 second-to-last dscr addr register"] +pub mod out_dscr_bf1_ch2; +#[doc = "OUT_ARB_CH2 (rw) register accessor: TX CH2 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_arb_ch2`] module"] +pub type OUT_ARB_CH2 = crate::Reg; +#[doc = "TX CH2 arb register"] +pub mod out_arb_ch2; +#[doc = "OUT_ETM_CONF_CH2 (rw) register accessor: TX CH2 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_etm_conf_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_etm_conf_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_etm_conf_ch2`] module"] +pub type OUT_ETM_CONF_CH2 = crate::Reg; +#[doc = "TX CH2 ETM config register"] +pub mod out_etm_conf_ch2; +#[doc = "OUT_BUF_LEN_CH2 (r) register accessor: tx CH2 buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_buf_len_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_buf_len_ch2`] module"] +pub type OUT_BUF_LEN_CH2 = crate::Reg; +#[doc = "tx CH2 buf len register"] +pub mod out_buf_len_ch2; +#[doc = "OUT_FIFO_BCNT_CH2 (r) register accessor: tx CH2 fifo byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_fifo_bcnt_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_fifo_bcnt_ch2`] module"] +pub type OUT_FIFO_BCNT_CH2 = crate::Reg; +#[doc = "tx CH2 fifo byte cnt register"] +pub mod out_fifo_bcnt_ch2; +#[doc = "OUT_PUSH_BYTECNT_CH2 (r) register accessor: tx CH2 push byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_bytecnt_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_bytecnt_ch2`] module"] +pub type OUT_PUSH_BYTECNT_CH2 = crate::Reg; +#[doc = "tx CH2 push byte cnt register"] +pub mod out_push_bytecnt_ch2; +#[doc = "OUT_XADDR_CH2 (r) register accessor: tx CH2 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_xaddr_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_xaddr_ch2`] module"] +pub type OUT_XADDR_CH2 = crate::Reg; +#[doc = "tx CH2 xaddr register"] +pub mod out_xaddr_ch2; +#[doc = "OUT_CONF0_CH3 (rw) register accessor: TX CH3 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0_ch3`] module"] +pub type OUT_CONF0_CH3 = crate::Reg; +#[doc = "TX CH3 config0 register"] +pub mod out_conf0_ch3; +#[doc = "OUT_INT_RAW_CH3 (rw) register accessor: TX CH3 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_raw_ch3`] module"] +pub type OUT_INT_RAW_CH3 = crate::Reg; +#[doc = "TX CH3 interrupt raw register"] +pub mod out_int_raw_ch3; +#[doc = "OUT_INT_ENA_CH3 (rw) register accessor: TX CH3 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_ena_ch3`] module"] +pub type OUT_INT_ENA_CH3 = crate::Reg; +#[doc = "TX CH3 interrupt ena register"] +pub mod out_int_ena_ch3; +#[doc = "OUT_INT_ST_CH3 (r) register accessor: TX CH3 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_st_ch3`] module"] +pub type OUT_INT_ST_CH3 = crate::Reg; +#[doc = "TX CH3 interrupt st register"] +pub mod out_int_st_ch3; +#[doc = "OUT_INT_CLR_CH3 (w) register accessor: TX CH3 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch3::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_clr_ch3`] module"] +pub type OUT_INT_CLR_CH3 = crate::Reg; +#[doc = "TX CH3 interrupt clr register"] +pub mod out_int_clr_ch3; +#[doc = "OUTFIFO_STATUS_CH3 (r) register accessor: TX CH3 outfifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outfifo_status_ch3`] module"] +pub type OUTFIFO_STATUS_CH3 = crate::Reg; +#[doc = "TX CH3 outfifo status register"] +pub mod outfifo_status_ch3; +#[doc = "OUT_PUSH_CH3 (rw) register accessor: TX CH3 outfifo push register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_ch3`] module"] +pub type OUT_PUSH_CH3 = crate::Reg; +#[doc = "TX CH3 outfifo push register"] +pub mod out_push_ch3; +#[doc = "OUT_LINK_CONF_CH3 (rw) register accessor: TX CH3 out_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_conf_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_conf_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_conf_ch3`] module"] +pub type OUT_LINK_CONF_CH3 = crate::Reg; +#[doc = "TX CH3 out_link dscr ctrl register"] +pub mod out_link_conf_ch3; +#[doc = "OUT_LINK_ADDR_CH3 (rw) register accessor: TX CH3 out_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_addr_ch3`] module"] +pub type OUT_LINK_ADDR_CH3 = crate::Reg; +#[doc = "TX CH3 out_link dscr addr register"] +pub mod out_link_addr_ch3; +#[doc = "OUT_STATE_CH3 (r) register accessor: TX CH3 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_state_ch3`] module"] +pub type OUT_STATE_CH3 = crate::Reg; +#[doc = "TX CH3 state register"] +pub mod out_state_ch3; +#[doc = "OUT_EOF_DES_ADDR_CH3 (r) register accessor: TX CH3 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr_ch3`] module"] +pub type OUT_EOF_DES_ADDR_CH3 = crate::Reg; +#[doc = "TX CH3 eof des addr register"] +pub mod out_eof_des_addr_ch3; +#[doc = "OUT_DSCR_CH3 (r) register accessor: TX CH3 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_ch3`] module"] +pub type OUT_DSCR_CH3 = crate::Reg; +#[doc = "TX CH3 next dscr addr register"] +pub mod out_dscr_ch3; +#[doc = "OUT_DSCR_BF0_CH3 (r) register accessor: TX CH3 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf0_ch3`] module"] +pub type OUT_DSCR_BF0_CH3 = crate::Reg; +#[doc = "TX CH3 last dscr addr register"] +pub mod out_dscr_bf0_ch3; +#[doc = "OUT_DSCR_BF1_CH3 (r) register accessor: TX CH3 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf1_ch3`] module"] +pub type OUT_DSCR_BF1_CH3 = crate::Reg; +#[doc = "TX CH3 second-to-last dscr addr register"] +pub mod out_dscr_bf1_ch3; +#[doc = "OUT_ARB_CH3 (rw) register accessor: TX CH3 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_arb_ch3`] module"] +pub type OUT_ARB_CH3 = crate::Reg; +#[doc = "TX CH3 arb register"] +pub mod out_arb_ch3; +#[doc = "OUT_ETM_CONF_CH3 (rw) register accessor: TX CH3 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_etm_conf_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_etm_conf_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_etm_conf_ch3`] module"] +pub type OUT_ETM_CONF_CH3 = crate::Reg; +#[doc = "TX CH3 ETM config register"] +pub mod out_etm_conf_ch3; +#[doc = "OUT_BUF_LEN_CH3 (r) register accessor: tx CH3 buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_buf_len_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_buf_len_ch3`] module"] +pub type OUT_BUF_LEN_CH3 = crate::Reg; +#[doc = "tx CH3 buf len register"] +pub mod out_buf_len_ch3; +#[doc = "OUT_FIFO_BCNT_CH3 (r) register accessor: tx CH3 fifo byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_fifo_bcnt_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_fifo_bcnt_ch3`] module"] +pub type OUT_FIFO_BCNT_CH3 = crate::Reg; +#[doc = "tx CH3 fifo byte cnt register"] +pub mod out_fifo_bcnt_ch3; +#[doc = "OUT_PUSH_BYTECNT_CH3 (r) register accessor: tx CH3 push byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_bytecnt_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_bytecnt_ch3`] module"] +pub type OUT_PUSH_BYTECNT_CH3 = crate::Reg; +#[doc = "tx CH3 push byte cnt register"] +pub mod out_push_bytecnt_ch3; +#[doc = "OUT_XADDR_CH3 (r) register accessor: tx CH3 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_xaddr_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_xaddr_ch3`] module"] +pub type OUT_XADDR_CH3 = crate::Reg; +#[doc = "tx CH3 xaddr register"] +pub mod out_xaddr_ch3; +#[doc = "OUT_BLOCK_BUF_LEN_CH3 (r) register accessor: tx CH3 block buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_block_buf_len_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_block_buf_len_ch3`] module"] +pub type OUT_BLOCK_BUF_LEN_CH3 = crate::Reg; +#[doc = "tx CH3 block buf len register"] +pub mod out_block_buf_len_ch3; +#[doc = "OUT_CONF0_CH4 (rw) register accessor: TX CH4 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0_ch4`] module"] +pub type OUT_CONF0_CH4 = crate::Reg; +#[doc = "TX CH4 config0 register"] +pub mod out_conf0_ch4; +#[doc = "OUT_INT_RAW_CH4 (rw) register accessor: TX CH4 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_raw_ch4`] module"] +pub type OUT_INT_RAW_CH4 = crate::Reg; +#[doc = "TX CH4 interrupt raw register"] +pub mod out_int_raw_ch4; +#[doc = "OUT_INT_ENA_CH4 (rw) register accessor: TX CH4 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_ena_ch4`] module"] +pub type OUT_INT_ENA_CH4 = crate::Reg; +#[doc = "TX CH4 interrupt ena register"] +pub mod out_int_ena_ch4; +#[doc = "OUT_INT_ST_CH4 (r) register accessor: TX CH4 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_st_ch4`] module"] +pub type OUT_INT_ST_CH4 = crate::Reg; +#[doc = "TX CH4 interrupt st register"] +pub mod out_int_st_ch4; +#[doc = "OUT_INT_CLR_CH4 (w) register accessor: TX CH4 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch4::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_int_clr_ch4`] module"] +pub type OUT_INT_CLR_CH4 = crate::Reg; +#[doc = "TX CH4 interrupt clr register"] +pub mod out_int_clr_ch4; +#[doc = "OUTFIFO_STATUS_CH4 (r) register accessor: TX CH4 outfifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outfifo_status_ch4`] module"] +pub type OUTFIFO_STATUS_CH4 = crate::Reg; +#[doc = "TX CH4 outfifo status register"] +pub mod outfifo_status_ch4; +#[doc = "OUT_PUSH_CH4 (rw) register accessor: TX CH4 outfifo push register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_ch4`] module"] +pub type OUT_PUSH_CH4 = crate::Reg; +#[doc = "TX CH4 outfifo push register"] +pub mod out_push_ch4; +#[doc = "OUT_LINK_CONF_CH4 (rw) register accessor: TX CH4 out_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_conf_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_conf_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_conf_ch4`] module"] +pub type OUT_LINK_CONF_CH4 = crate::Reg; +#[doc = "TX CH4 out_link dscr ctrl register"] +pub mod out_link_conf_ch4; +#[doc = "OUT_LINK_ADDR_CH4 (rw) register accessor: TX CH4 out_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link_addr_ch4`] module"] +pub type OUT_LINK_ADDR_CH4 = crate::Reg; +#[doc = "TX CH4 out_link dscr addr register"] +pub mod out_link_addr_ch4; +#[doc = "OUT_STATE_CH4 (r) register accessor: TX CH4 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_state_ch4`] module"] +pub type OUT_STATE_CH4 = crate::Reg; +#[doc = "TX CH4 state register"] +pub mod out_state_ch4; +#[doc = "OUT_EOF_DES_ADDR_CH4 (r) register accessor: TX CH4 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr_ch4`] module"] +pub type OUT_EOF_DES_ADDR_CH4 = crate::Reg; +#[doc = "TX CH4 eof des addr register"] +pub mod out_eof_des_addr_ch4; +#[doc = "OUT_DSCR_CH4 (r) register accessor: TX CH4 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_ch4`] module"] +pub type OUT_DSCR_CH4 = crate::Reg; +#[doc = "TX CH4 next dscr addr register"] +pub mod out_dscr_ch4; +#[doc = "OUT_DSCR_BF0_CH4 (r) register accessor: TX CH4 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf0_ch4`] module"] +pub type OUT_DSCR_BF0_CH4 = crate::Reg; +#[doc = "TX CH4 last dscr addr register"] +pub mod out_dscr_bf0_ch4; +#[doc = "OUT_DSCR_BF1_CH4 (r) register accessor: TX CH4 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf1_ch4`] module"] +pub type OUT_DSCR_BF1_CH4 = crate::Reg; +#[doc = "TX CH4 second-to-last dscr addr register"] +pub mod out_dscr_bf1_ch4; +#[doc = "OUT_ARB_CH4 (rw) register accessor: TX CH4 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_arb_ch4`] module"] +pub type OUT_ARB_CH4 = crate::Reg; +#[doc = "TX CH4 arb register"] +pub mod out_arb_ch4; +#[doc = "OUT_ETM_CONF_CH4 (rw) register accessor: TX CH4 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_etm_conf_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_etm_conf_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_etm_conf_ch4`] module"] +pub type OUT_ETM_CONF_CH4 = crate::Reg; +#[doc = "TX CH4 ETM config register"] +pub mod out_etm_conf_ch4; +#[doc = "OUT_BUF_LEN_CH4 (r) register accessor: tx CH4 buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_buf_len_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_buf_len_ch4`] module"] +pub type OUT_BUF_LEN_CH4 = crate::Reg; +#[doc = "tx CH4 buf len register"] +pub mod out_buf_len_ch4; +#[doc = "OUT_FIFO_BCNT_CH4 (r) register accessor: tx CH4 fifo byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_fifo_bcnt_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_fifo_bcnt_ch4`] module"] +pub type OUT_FIFO_BCNT_CH4 = crate::Reg; +#[doc = "tx CH4 fifo byte cnt register"] +pub mod out_fifo_bcnt_ch4; +#[doc = "OUT_PUSH_BYTECNT_CH4 (r) register accessor: tx CH4 push byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_bytecnt_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push_bytecnt_ch4`] module"] +pub type OUT_PUSH_BYTECNT_CH4 = crate::Reg; +#[doc = "tx CH4 push byte cnt register"] +pub mod out_push_bytecnt_ch4; +#[doc = "OUT_XADDR_CH4 (r) register accessor: tx CH4 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_xaddr_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_xaddr_ch4`] module"] +pub type OUT_XADDR_CH4 = crate::Reg; +#[doc = "tx CH4 xaddr register"] +pub mod out_xaddr_ch4; +#[doc = "OUT_BLOCK_BUF_LEN_CH4 (r) register accessor: tx CH4 block buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_block_buf_len_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_block_buf_len_ch4`] module"] +pub type OUT_BLOCK_BUF_LEN_CH4 = crate::Reg; +#[doc = "tx CH4 block buf len register"] +pub mod out_block_buf_len_ch4; +#[doc = "IN_CONF0_CH0 (rw) register accessor: RX CH0 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf0_ch0`] module"] +pub type IN_CONF0_CH0 = crate::Reg; +#[doc = "RX CH0 config0 register"] +pub mod in_conf0_ch0; +#[doc = "IN_INT_RAW_CH0 (rw) register accessor: RX CH0 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_raw_ch0`] module"] +pub type IN_INT_RAW_CH0 = crate::Reg; +#[doc = "RX CH0 interrupt raw register"] +pub mod in_int_raw_ch0; +#[doc = "IN_INT_ENA_CH0 (rw) register accessor: RX CH0 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_ena_ch0`] module"] +pub type IN_INT_ENA_CH0 = crate::Reg; +#[doc = "RX CH0 interrupt ena register"] +pub mod in_int_ena_ch0; +#[doc = "IN_INT_ST_CH0 (r) register accessor: RX CH0 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_st_ch0`] module"] +pub type IN_INT_ST_CH0 = crate::Reg; +#[doc = "RX CH0 interrupt st register"] +pub mod in_int_st_ch0; +#[doc = "IN_INT_CLR_CH0 (w) register accessor: RX CH0 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_clr_ch0`] module"] +pub type IN_INT_CLR_CH0 = crate::Reg; +#[doc = "RX CH0 interrupt clr register"] +pub mod in_int_clr_ch0; +#[doc = "INFIFO_STATUS_CH0 (r) register accessor: RX CH0 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@infifo_status_ch0`] module"] +pub type INFIFO_STATUS_CH0 = crate::Reg; +#[doc = "RX CH0 INFIFO status register"] +pub mod infifo_status_ch0; +#[doc = "IN_POP_CH0 (rw) register accessor: RX CH0 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_ch0`] module"] +pub type IN_POP_CH0 = crate::Reg; +#[doc = "RX CH0 INFIFO pop register"] +pub mod in_pop_ch0; +#[doc = "IN_LINK_CONF_CH0 (rw) register accessor: RX CH0 in_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_conf_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_conf_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_conf_ch0`] module"] +pub type IN_LINK_CONF_CH0 = crate::Reg; +#[doc = "RX CH0 in_link dscr ctrl register"] +pub mod in_link_conf_ch0; +#[doc = "IN_LINK_ADDR_CH0 (rw) register accessor: RX CH0 in_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_addr_ch0`] module"] +pub type IN_LINK_ADDR_CH0 = crate::Reg; +#[doc = "RX CH0 in_link dscr addr register"] +pub mod in_link_addr_ch0; +#[doc = "IN_STATE_CH0 (r) register accessor: RX CH0 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_state_ch0`] module"] +pub type IN_STATE_CH0 = crate::Reg; +#[doc = "RX CH0 state register"] +pub mod in_state_ch0; +#[doc = "IN_SUC_EOF_DES_ADDR_CH0 (r) register accessor: RX CH0 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_suc_eof_des_addr_ch0`] module"] +pub type IN_SUC_EOF_DES_ADDR_CH0 = + crate::Reg; +#[doc = "RX CH0 eof des addr register"] +pub mod in_suc_eof_des_addr_ch0; +#[doc = "IN_ERR_EOF_DES_ADDR_CH0 (r) register accessor: RX CH0 err eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_err_eof_des_addr_ch0`] module"] +pub type IN_ERR_EOF_DES_ADDR_CH0 = + crate::Reg; +#[doc = "RX CH0 err eof des addr register"] +pub mod in_err_eof_des_addr_ch0; +#[doc = "IN_DSCR_CH0 (r) register accessor: RX CH0 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_ch0`] module"] +pub type IN_DSCR_CH0 = crate::Reg; +#[doc = "RX CH0 next dscr addr register"] +pub mod in_dscr_ch0; +#[doc = "IN_DSCR_BF0_CH0 (r) register accessor: RX CH0 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf0_ch0`] module"] +pub type IN_DSCR_BF0_CH0 = crate::Reg; +#[doc = "RX CH0 last dscr addr register"] +pub mod in_dscr_bf0_ch0; +#[doc = "IN_DSCR_BF1_CH0 (r) register accessor: RX CH0 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf1_ch0`] module"] +pub type IN_DSCR_BF1_CH0 = crate::Reg; +#[doc = "RX CH0 second-to-last dscr addr register"] +pub mod in_dscr_bf1_ch0; +#[doc = "IN_ARB_CH0 (rw) register accessor: RX CH0 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_arb_ch0`] module"] +pub type IN_ARB_CH0 = crate::Reg; +#[doc = "RX CH0 arb register"] +pub mod in_arb_ch0; +#[doc = "IN_RO_PD_CONF_CH0 (rw) register accessor: RX CH0 reorder power config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ro_pd_conf_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_ro_pd_conf_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_ro_pd_conf_ch0`] module"] +pub type IN_RO_PD_CONF_CH0 = crate::Reg; +#[doc = "RX CH0 reorder power config register"] +pub mod in_ro_pd_conf_ch0; +#[doc = "IN_ETM_CONF_CH0 (rw) register accessor: RX CH0 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_etm_conf_ch0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_etm_conf_ch0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_etm_conf_ch0`] module"] +pub type IN_ETM_CONF_CH0 = crate::Reg; +#[doc = "RX CH0 ETM config register"] +pub mod in_etm_conf_ch0; +#[doc = "IN_FIFO_CNT_CH0 (r) register accessor: rx CH0 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_fifo_cnt_ch0`] module"] +pub type IN_FIFO_CNT_CH0 = crate::Reg; +#[doc = "rx CH0 fifo cnt register"] +pub mod in_fifo_cnt_ch0; +#[doc = "IN_POP_DATA_CNT_CH0 (r) register accessor: rx CH0 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_data_cnt_ch0`] module"] +pub type IN_POP_DATA_CNT_CH0 = crate::Reg; +#[doc = "rx CH0 pop data cnt register"] +pub mod in_pop_data_cnt_ch0; +#[doc = "IN_XADDR_CH0 (r) register accessor: rx CH0 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_xaddr_ch0`] module"] +pub type IN_XADDR_CH0 = crate::Reg; +#[doc = "rx CH0 xaddr register"] +pub mod in_xaddr_ch0; +#[doc = "IN_BUF_HB_RCV_CH0 (r) register accessor: rx CH0 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_buf_hb_rcv_ch0`] module"] +pub type IN_BUF_HB_RCV_CH0 = crate::Reg; +#[doc = "rx CH0 buf len hb rcv register"] +pub mod in_buf_hb_rcv_ch0; +#[doc = "IN_CONF0_CH1 (rw) register accessor: RX CH1 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf0_ch1`] module"] +pub type IN_CONF0_CH1 = crate::Reg; +#[doc = "RX CH1 config0 register"] +pub mod in_conf0_ch1; +#[doc = "IN_INT_RAW_CH1 (rw) register accessor: RX CH1 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_raw_ch1`] module"] +pub type IN_INT_RAW_CH1 = crate::Reg; +#[doc = "RX CH1 interrupt raw register"] +pub mod in_int_raw_ch1; +#[doc = "IN_INT_ENA_CH1 (rw) register accessor: RX CH1 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_ena_ch1`] module"] +pub type IN_INT_ENA_CH1 = crate::Reg; +#[doc = "RX CH1 interrupt ena register"] +pub mod in_int_ena_ch1; +#[doc = "IN_INT_ST_CH1 (r) register accessor: RX CH1 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_st_ch1`] module"] +pub type IN_INT_ST_CH1 = crate::Reg; +#[doc = "RX CH1 interrupt st register"] +pub mod in_int_st_ch1; +#[doc = "IN_INT_CLR_CH1 (w) register accessor: RX CH1 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_clr_ch1`] module"] +pub type IN_INT_CLR_CH1 = crate::Reg; +#[doc = "RX CH1 interrupt clr register"] +pub mod in_int_clr_ch1; +#[doc = "INFIFO_STATUS_CH1 (r) register accessor: RX CH1 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@infifo_status_ch1`] module"] +pub type INFIFO_STATUS_CH1 = crate::Reg; +#[doc = "RX CH1 INFIFO status register"] +pub mod infifo_status_ch1; +#[doc = "IN_POP_CH1 (rw) register accessor: RX CH1 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_ch1`] module"] +pub type IN_POP_CH1 = crate::Reg; +#[doc = "RX CH1 INFIFO pop register"] +pub mod in_pop_ch1; +#[doc = "IN_LINK_CONF_CH1 (rw) register accessor: RX CH1 in_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_conf_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_conf_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_conf_ch1`] module"] +pub type IN_LINK_CONF_CH1 = crate::Reg; +#[doc = "RX CH1 in_link dscr ctrl register"] +pub mod in_link_conf_ch1; +#[doc = "IN_LINK_ADDR_CH1 (rw) register accessor: RX CH1 in_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_addr_ch1`] module"] +pub type IN_LINK_ADDR_CH1 = crate::Reg; +#[doc = "RX CH1 in_link dscr addr register"] +pub mod in_link_addr_ch1; +#[doc = "IN_STATE_CH1 (r) register accessor: RX CH1 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_state_ch1`] module"] +pub type IN_STATE_CH1 = crate::Reg; +#[doc = "RX CH1 state register"] +pub mod in_state_ch1; +#[doc = "IN_SUC_EOF_DES_ADDR_CH1 (r) register accessor: RX CH1 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_suc_eof_des_addr_ch1`] module"] +pub type IN_SUC_EOF_DES_ADDR_CH1 = + crate::Reg; +#[doc = "RX CH1 eof des addr register"] +pub mod in_suc_eof_des_addr_ch1; +#[doc = "IN_ERR_EOF_DES_ADDR_CH1 (r) register accessor: RX CH1 err eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_err_eof_des_addr_ch1`] module"] +pub type IN_ERR_EOF_DES_ADDR_CH1 = + crate::Reg; +#[doc = "RX CH1 err eof des addr register"] +pub mod in_err_eof_des_addr_ch1; +#[doc = "IN_DSCR_CH1 (r) register accessor: RX CH1 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_ch1`] module"] +pub type IN_DSCR_CH1 = crate::Reg; +#[doc = "RX CH1 next dscr addr register"] +pub mod in_dscr_ch1; +#[doc = "IN_DSCR_BF0_CH1 (r) register accessor: RX CH1 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf0_ch1`] module"] +pub type IN_DSCR_BF0_CH1 = crate::Reg; +#[doc = "RX CH1 last dscr addr register"] +pub mod in_dscr_bf0_ch1; +#[doc = "IN_DSCR_BF1_CH1 (r) register accessor: RX CH1 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf1_ch1`] module"] +pub type IN_DSCR_BF1_CH1 = crate::Reg; +#[doc = "RX CH1 second-to-last dscr addr register"] +pub mod in_dscr_bf1_ch1; +#[doc = "IN_ARB_CH1 (rw) register accessor: RX CH1 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_arb_ch1`] module"] +pub type IN_ARB_CH1 = crate::Reg; +#[doc = "RX CH1 arb register"] +pub mod in_arb_ch1; +#[doc = "IN_ETM_CONF_CH1 (rw) register accessor: RX CH1 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_etm_conf_ch1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_etm_conf_ch1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_etm_conf_ch1`] module"] +pub type IN_ETM_CONF_CH1 = crate::Reg; +#[doc = "RX CH1 ETM config register"] +pub mod in_etm_conf_ch1; +#[doc = "IN_FIFO_CNT_CH1 (r) register accessor: rx CH1 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_fifo_cnt_ch1`] module"] +pub type IN_FIFO_CNT_CH1 = crate::Reg; +#[doc = "rx CH1 fifo cnt register"] +pub mod in_fifo_cnt_ch1; +#[doc = "IN_POP_DATA_CNT_CH1 (r) register accessor: rx CH1 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_data_cnt_ch1`] module"] +pub type IN_POP_DATA_CNT_CH1 = crate::Reg; +#[doc = "rx CH1 pop data cnt register"] +pub mod in_pop_data_cnt_ch1; +#[doc = "IN_XADDR_CH1 (r) register accessor: rx CH1 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_xaddr_ch1`] module"] +pub type IN_XADDR_CH1 = crate::Reg; +#[doc = "rx CH1 xaddr register"] +pub mod in_xaddr_ch1; +#[doc = "IN_BUF_HB_RCV_CH1 (r) register accessor: rx CH1 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_buf_hb_rcv_ch1`] module"] +pub type IN_BUF_HB_RCV_CH1 = crate::Reg; +#[doc = "rx CH1 buf len hb rcv register"] +pub mod in_buf_hb_rcv_ch1; +#[doc = "IN_CONF0_CH2 (rw) register accessor: RX CH2 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf0_ch2`] module"] +pub type IN_CONF0_CH2 = crate::Reg; +#[doc = "RX CH2 config0 register"] +pub mod in_conf0_ch2; +#[doc = "IN_INT_RAW_CH2 (rw) register accessor: RX CH2 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_raw_ch2`] module"] +pub type IN_INT_RAW_CH2 = crate::Reg; +#[doc = "RX CH2 interrupt raw register"] +pub mod in_int_raw_ch2; +#[doc = "IN_INT_ENA_CH2 (rw) register accessor: RX CH2 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_ena_ch2`] module"] +pub type IN_INT_ENA_CH2 = crate::Reg; +#[doc = "RX CH2 interrupt ena register"] +pub mod in_int_ena_ch2; +#[doc = "IN_INT_ST_CH2 (r) register accessor: RX CH2 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_st_ch2`] module"] +pub type IN_INT_ST_CH2 = crate::Reg; +#[doc = "RX CH2 interrupt st register"] +pub mod in_int_st_ch2; +#[doc = "IN_INT_CLR_CH2 (w) register accessor: RX CH2 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_clr_ch2`] module"] +pub type IN_INT_CLR_CH2 = crate::Reg; +#[doc = "RX CH2 interrupt clr register"] +pub mod in_int_clr_ch2; +#[doc = "INFIFO_STATUS_CH2 (r) register accessor: RX CH2 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@infifo_status_ch2`] module"] +pub type INFIFO_STATUS_CH2 = crate::Reg; +#[doc = "RX CH2 INFIFO status register"] +pub mod infifo_status_ch2; +#[doc = "IN_POP_CH2 (rw) register accessor: RX CH2 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_ch2`] module"] +pub type IN_POP_CH2 = crate::Reg; +#[doc = "RX CH2 INFIFO pop register"] +pub mod in_pop_ch2; +#[doc = "IN_LINK_CONF_CH2 (rw) register accessor: RX CH2 in_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_conf_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_conf_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_conf_ch2`] module"] +pub type IN_LINK_CONF_CH2 = crate::Reg; +#[doc = "RX CH2 in_link dscr ctrl register"] +pub mod in_link_conf_ch2; +#[doc = "IN_LINK_ADDR_CH2 (rw) register accessor: RX CH2 in_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_addr_ch2`] module"] +pub type IN_LINK_ADDR_CH2 = crate::Reg; +#[doc = "RX CH2 in_link dscr addr register"] +pub mod in_link_addr_ch2; +#[doc = "IN_STATE_CH2 (r) register accessor: RX CH2 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_state_ch2`] module"] +pub type IN_STATE_CH2 = crate::Reg; +#[doc = "RX CH2 state register"] +pub mod in_state_ch2; +#[doc = "IN_SUC_EOF_DES_ADDR_CH2 (r) register accessor: RX CH2 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_suc_eof_des_addr_ch2`] module"] +pub type IN_SUC_EOF_DES_ADDR_CH2 = + crate::Reg; +#[doc = "RX CH2 eof des addr register"] +pub mod in_suc_eof_des_addr_ch2; +#[doc = "IN_ERR_EOF_DES_ADDR_CH2 (r) register accessor: RX CH2 err eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_err_eof_des_addr_ch2`] module"] +pub type IN_ERR_EOF_DES_ADDR_CH2 = + crate::Reg; +#[doc = "RX CH2 err eof des addr register"] +pub mod in_err_eof_des_addr_ch2; +#[doc = "IN_DSCR_CH2 (r) register accessor: RX CH2 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_ch2`] module"] +pub type IN_DSCR_CH2 = crate::Reg; +#[doc = "RX CH2 next dscr addr register"] +pub mod in_dscr_ch2; +#[doc = "IN_DSCR_BF0_CH2 (r) register accessor: RX CH2 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf0_ch2`] module"] +pub type IN_DSCR_BF0_CH2 = crate::Reg; +#[doc = "RX CH2 last dscr addr register"] +pub mod in_dscr_bf0_ch2; +#[doc = "IN_DSCR_BF1_CH2 (r) register accessor: RX CH2 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf1_ch2`] module"] +pub type IN_DSCR_BF1_CH2 = crate::Reg; +#[doc = "RX CH2 second-to-last dscr addr register"] +pub mod in_dscr_bf1_ch2; +#[doc = "IN_ARB_CH2 (rw) register accessor: RX CH2 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_arb_ch2`] module"] +pub type IN_ARB_CH2 = crate::Reg; +#[doc = "RX CH2 arb register"] +pub mod in_arb_ch2; +#[doc = "IN_ETM_CONF_CH2 (rw) register accessor: RX CH2 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_etm_conf_ch2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_etm_conf_ch2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_etm_conf_ch2`] module"] +pub type IN_ETM_CONF_CH2 = crate::Reg; +#[doc = "RX CH2 ETM config register"] +pub mod in_etm_conf_ch2; +#[doc = "IN_FIFO_CNT_CH2 (r) register accessor: rx CH2 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_fifo_cnt_ch2`] module"] +pub type IN_FIFO_CNT_CH2 = crate::Reg; +#[doc = "rx CH2 fifo cnt register"] +pub mod in_fifo_cnt_ch2; +#[doc = "IN_POP_DATA_CNT_CH2 (r) register accessor: rx CH2 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_data_cnt_ch2`] module"] +pub type IN_POP_DATA_CNT_CH2 = crate::Reg; +#[doc = "rx CH2 pop data cnt register"] +pub mod in_pop_data_cnt_ch2; +#[doc = "IN_XADDR_CH2 (r) register accessor: rx CH2 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_xaddr_ch2`] module"] +pub type IN_XADDR_CH2 = crate::Reg; +#[doc = "rx CH2 xaddr register"] +pub mod in_xaddr_ch2; +#[doc = "IN_BUF_HB_RCV_CH2 (r) register accessor: rx CH2 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_buf_hb_rcv_ch2`] module"] +pub type IN_BUF_HB_RCV_CH2 = crate::Reg; +#[doc = "rx CH2 buf len hb rcv register"] +pub mod in_buf_hb_rcv_ch2; +#[doc = "IN_CONF0_CH3 (rw) register accessor: RX CH3 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf0_ch3`] module"] +pub type IN_CONF0_CH3 = crate::Reg; +#[doc = "RX CH3 config0 register"] +pub mod in_conf0_ch3; +#[doc = "IN_INT_RAW_CH3 (rw) register accessor: RX CH3 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_raw_ch3`] module"] +pub type IN_INT_RAW_CH3 = crate::Reg; +#[doc = "RX CH3 interrupt raw register"] +pub mod in_int_raw_ch3; +#[doc = "IN_INT_ENA_CH3 (rw) register accessor: RX CH3 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_ena_ch3`] module"] +pub type IN_INT_ENA_CH3 = crate::Reg; +#[doc = "RX CH3 interrupt ena register"] +pub mod in_int_ena_ch3; +#[doc = "IN_INT_ST_CH3 (r) register accessor: RX CH3 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_st_ch3`] module"] +pub type IN_INT_ST_CH3 = crate::Reg; +#[doc = "RX CH3 interrupt st register"] +pub mod in_int_st_ch3; +#[doc = "IN_INT_CLR_CH3 (w) register accessor: RX CH3 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch3::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_clr_ch3`] module"] +pub type IN_INT_CLR_CH3 = crate::Reg; +#[doc = "RX CH3 interrupt clr register"] +pub mod in_int_clr_ch3; +#[doc = "INFIFO_STATUS_CH3 (r) register accessor: RX CH3 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@infifo_status_ch3`] module"] +pub type INFIFO_STATUS_CH3 = crate::Reg; +#[doc = "RX CH3 INFIFO status register"] +pub mod infifo_status_ch3; +#[doc = "IN_POP_CH3 (rw) register accessor: RX CH3 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_ch3`] module"] +pub type IN_POP_CH3 = crate::Reg; +#[doc = "RX CH3 INFIFO pop register"] +pub mod in_pop_ch3; +#[doc = "IN_LINK_CONF_CH3 (rw) register accessor: RX CH3 in_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_conf_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_conf_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_conf_ch3`] module"] +pub type IN_LINK_CONF_CH3 = crate::Reg; +#[doc = "RX CH3 in_link dscr ctrl register"] +pub mod in_link_conf_ch3; +#[doc = "IN_LINK_ADDR_CH3 (rw) register accessor: RX CH3 in_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_addr_ch3`] module"] +pub type IN_LINK_ADDR_CH3 = crate::Reg; +#[doc = "RX CH3 in_link dscr addr register"] +pub mod in_link_addr_ch3; +#[doc = "IN_STATE_CH3 (r) register accessor: RX CH3 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_state_ch3`] module"] +pub type IN_STATE_CH3 = crate::Reg; +#[doc = "RX CH3 state register"] +pub mod in_state_ch3; +#[doc = "IN_SUC_EOF_DES_ADDR_CH3 (r) register accessor: RX CH3 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_suc_eof_des_addr_ch3`] module"] +pub type IN_SUC_EOF_DES_ADDR_CH3 = + crate::Reg; +#[doc = "RX CH3 eof des addr register"] +pub mod in_suc_eof_des_addr_ch3; +#[doc = "IN_ERR_EOF_DES_ADDR_CH3 (r) register accessor: RX CH3 err eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_err_eof_des_addr_ch3`] module"] +pub type IN_ERR_EOF_DES_ADDR_CH3 = + crate::Reg; +#[doc = "RX CH3 err eof des addr register"] +pub mod in_err_eof_des_addr_ch3; +#[doc = "IN_DSCR_CH3 (r) register accessor: RX CH3 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_ch3`] module"] +pub type IN_DSCR_CH3 = crate::Reg; +#[doc = "RX CH3 next dscr addr register"] +pub mod in_dscr_ch3; +#[doc = "IN_DSCR_BF0_CH3 (r) register accessor: RX CH3 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf0_ch3`] module"] +pub type IN_DSCR_BF0_CH3 = crate::Reg; +#[doc = "RX CH3 last dscr addr register"] +pub mod in_dscr_bf0_ch3; +#[doc = "IN_DSCR_BF1_CH3 (r) register accessor: RX CH3 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf1_ch3`] module"] +pub type IN_DSCR_BF1_CH3 = crate::Reg; +#[doc = "RX CH3 second-to-last dscr addr register"] +pub mod in_dscr_bf1_ch3; +#[doc = "IN_ARB_CH3 (rw) register accessor: RX CH3 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_arb_ch3`] module"] +pub type IN_ARB_CH3 = crate::Reg; +#[doc = "RX CH3 arb register"] +pub mod in_arb_ch3; +#[doc = "IN_ETM_CONF_CH3 (rw) register accessor: RX CH3 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_etm_conf_ch3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_etm_conf_ch3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_etm_conf_ch3`] module"] +pub type IN_ETM_CONF_CH3 = crate::Reg; +#[doc = "RX CH3 ETM config register"] +pub mod in_etm_conf_ch3; +#[doc = "IN_FIFO_CNT_CH3 (r) register accessor: rx CH3 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_fifo_cnt_ch3`] module"] +pub type IN_FIFO_CNT_CH3 = crate::Reg; +#[doc = "rx CH3 fifo cnt register"] +pub mod in_fifo_cnt_ch3; +#[doc = "IN_POP_DATA_CNT_CH3 (r) register accessor: rx CH3 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_data_cnt_ch3`] module"] +pub type IN_POP_DATA_CNT_CH3 = crate::Reg; +#[doc = "rx CH3 pop data cnt register"] +pub mod in_pop_data_cnt_ch3; +#[doc = "IN_XADDR_CH3 (r) register accessor: rx CH3 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_xaddr_ch3`] module"] +pub type IN_XADDR_CH3 = crate::Reg; +#[doc = "rx CH3 xaddr register"] +pub mod in_xaddr_ch3; +#[doc = "IN_BUF_HB_RCV_CH3 (r) register accessor: rx CH3 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_buf_hb_rcv_ch3`] module"] +pub type IN_BUF_HB_RCV_CH3 = crate::Reg; +#[doc = "rx CH3 buf len hb rcv register"] +pub mod in_buf_hb_rcv_ch3; +#[doc = "IN_CONF0_CH4 (rw) register accessor: RX CH4 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf0_ch4`] module"] +pub type IN_CONF0_CH4 = crate::Reg; +#[doc = "RX CH4 config0 register"] +pub mod in_conf0_ch4; +#[doc = "IN_INT_RAW_CH4 (rw) register accessor: RX CH4 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_raw_ch4`] module"] +pub type IN_INT_RAW_CH4 = crate::Reg; +#[doc = "RX CH4 interrupt raw register"] +pub mod in_int_raw_ch4; +#[doc = "IN_INT_ENA_CH4 (rw) register accessor: RX CH4 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_ena_ch4`] module"] +pub type IN_INT_ENA_CH4 = crate::Reg; +#[doc = "RX CH4 interrupt ena register"] +pub mod in_int_ena_ch4; +#[doc = "IN_INT_ST_CH4 (r) register accessor: RX CH4 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_st_ch4`] module"] +pub type IN_INT_ST_CH4 = crate::Reg; +#[doc = "RX CH4 interrupt st register"] +pub mod in_int_st_ch4; +#[doc = "IN_INT_CLR_CH4 (w) register accessor: RX CH4 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch4::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_clr_ch4`] module"] +pub type IN_INT_CLR_CH4 = crate::Reg; +#[doc = "RX CH4 interrupt clr register"] +pub mod in_int_clr_ch4; +#[doc = "INFIFO_STATUS_CH4 (r) register accessor: RX CH4 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@infifo_status_ch4`] module"] +pub type INFIFO_STATUS_CH4 = crate::Reg; +#[doc = "RX CH4 INFIFO status register"] +pub mod infifo_status_ch4; +#[doc = "IN_POP_CH4 (rw) register accessor: RX CH4 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_ch4`] module"] +pub type IN_POP_CH4 = crate::Reg; +#[doc = "RX CH4 INFIFO pop register"] +pub mod in_pop_ch4; +#[doc = "IN_LINK_CONF_CH4 (rw) register accessor: RX CH4 in_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_conf_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_conf_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_conf_ch4`] module"] +pub type IN_LINK_CONF_CH4 = crate::Reg; +#[doc = "RX CH4 in_link dscr ctrl register"] +pub mod in_link_conf_ch4; +#[doc = "IN_LINK_ADDR_CH4 (rw) register accessor: RX CH4 in_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link_addr_ch4`] module"] +pub type IN_LINK_ADDR_CH4 = crate::Reg; +#[doc = "RX CH4 in_link dscr addr register"] +pub mod in_link_addr_ch4; +#[doc = "IN_STATE_CH4 (r) register accessor: RX CH4 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_state_ch4`] module"] +pub type IN_STATE_CH4 = crate::Reg; +#[doc = "RX CH4 state register"] +pub mod in_state_ch4; +#[doc = "IN_SUC_EOF_DES_ADDR_CH4 (r) register accessor: RX CH4 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_suc_eof_des_addr_ch4`] module"] +pub type IN_SUC_EOF_DES_ADDR_CH4 = + crate::Reg; +#[doc = "RX CH4 eof des addr register"] +pub mod in_suc_eof_des_addr_ch4; +#[doc = "IN_ERR_EOF_DES_ADDR_CH4 (r) register accessor: RX CH4 err eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_err_eof_des_addr_ch4`] module"] +pub type IN_ERR_EOF_DES_ADDR_CH4 = + crate::Reg; +#[doc = "RX CH4 err eof des addr register"] +pub mod in_err_eof_des_addr_ch4; +#[doc = "IN_DSCR_CH4 (r) register accessor: RX CH4 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_ch4`] module"] +pub type IN_DSCR_CH4 = crate::Reg; +#[doc = "RX CH4 next dscr addr register"] +pub mod in_dscr_ch4; +#[doc = "IN_DSCR_BF0_CH4 (r) register accessor: RX CH4 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf0_ch4`] module"] +pub type IN_DSCR_BF0_CH4 = crate::Reg; +#[doc = "RX CH4 last dscr addr register"] +pub mod in_dscr_bf0_ch4; +#[doc = "IN_DSCR_BF1_CH4 (r) register accessor: RX CH4 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf1_ch4`] module"] +pub type IN_DSCR_BF1_CH4 = crate::Reg; +#[doc = "RX CH4 second-to-last dscr addr register"] +pub mod in_dscr_bf1_ch4; +#[doc = "IN_ARB_CH4 (rw) register accessor: RX CH4 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_arb_ch4`] module"] +pub type IN_ARB_CH4 = crate::Reg; +#[doc = "RX CH4 arb register"] +pub mod in_arb_ch4; +#[doc = "IN_ETM_CONF_CH4 (rw) register accessor: RX CH4 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_etm_conf_ch4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_etm_conf_ch4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_etm_conf_ch4`] module"] +pub type IN_ETM_CONF_CH4 = crate::Reg; +#[doc = "RX CH4 ETM config register"] +pub mod in_etm_conf_ch4; +#[doc = "IN_FIFO_CNT_CH4 (r) register accessor: rx CH4 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_fifo_cnt_ch4`] module"] +pub type IN_FIFO_CNT_CH4 = crate::Reg; +#[doc = "rx CH4 fifo cnt register"] +pub mod in_fifo_cnt_ch4; +#[doc = "IN_POP_DATA_CNT_CH4 (r) register accessor: rx CH4 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_data_cnt_ch4`] module"] +pub type IN_POP_DATA_CNT_CH4 = crate::Reg; +#[doc = "rx CH4 pop data cnt register"] +pub mod in_pop_data_cnt_ch4; +#[doc = "IN_XADDR_CH4 (r) register accessor: rx CH4 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_xaddr_ch4`] module"] +pub type IN_XADDR_CH4 = crate::Reg; +#[doc = "rx CH4 xaddr register"] +pub mod in_xaddr_ch4; +#[doc = "IN_BUF_HB_RCV_CH4 (r) register accessor: rx CH4 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_buf_hb_rcv_ch4`] module"] +pub type IN_BUF_HB_RCV_CH4 = crate::Reg; +#[doc = "rx CH4 buf len hb rcv register"] +pub mod in_buf_hb_rcv_ch4; +#[doc = "IN_CONF0_CH5 (rw) register accessor: RX CH5 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf0_ch5`] module"] +pub type IN_CONF0_CH5 = crate::Reg; +#[doc = "RX CH5 config0 register"] +pub mod in_conf0_ch5; +#[doc = "IN_CONF1_CH5 (rw) register accessor: RX CH5 config1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf1_ch5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf1_ch5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf1_ch5`] module"] +pub type IN_CONF1_CH5 = crate::Reg; +#[doc = "RX CH5 config1 register"] +pub mod in_conf1_ch5; +#[doc = "IN_CONF2_CH5 (rw) register accessor: RX CH5 config2 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf2_ch5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf2_ch5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf2_ch5`] module"] +pub type IN_CONF2_CH5 = crate::Reg; +#[doc = "RX CH5 config2 register"] +pub mod in_conf2_ch5; +#[doc = "IN_CONF3_CH5 (rw) register accessor: RX CH5 config3 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf3_ch5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf3_ch5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf3_ch5`] module"] +pub type IN_CONF3_CH5 = crate::Reg; +#[doc = "RX CH5 config3 register"] +pub mod in_conf3_ch5; +#[doc = "IN_INT_RAW_CH5 (rw) register accessor: RX CH5 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_raw_ch5`] module"] +pub type IN_INT_RAW_CH5 = crate::Reg; +#[doc = "RX CH5 interrupt raw register"] +pub mod in_int_raw_ch5; +#[doc = "IN_INT_ENA_CH5 (rw) register accessor: RX CH5 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_ena_ch5`] module"] +pub type IN_INT_ENA_CH5 = crate::Reg; +#[doc = "RX CH5 interrupt ena register"] +pub mod in_int_ena_ch5; +#[doc = "IN_INT_ST_CH5 (r) register accessor: RX CH5 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_st_ch5`] module"] +pub type IN_INT_ST_CH5 = crate::Reg; +#[doc = "RX CH5 interrupt st register"] +pub mod in_int_st_ch5; +#[doc = "IN_INT_CLR_CH5 (w) register accessor: RX CH5 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch5::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_int_clr_ch5`] module"] +pub type IN_INT_CLR_CH5 = crate::Reg; +#[doc = "RX CH5 interrupt clr register"] +pub mod in_int_clr_ch5; +#[doc = "INFIFO_STATUS_CH5 (r) register accessor: RX CH5 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@infifo_status_ch5`] module"] +pub type INFIFO_STATUS_CH5 = crate::Reg; +#[doc = "RX CH5 INFIFO status register"] +pub mod infifo_status_ch5; +#[doc = "IN_POP_CH5 (rw) register accessor: RX CH5 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_ch5`] module"] +pub type IN_POP_CH5 = crate::Reg; +#[doc = "RX CH5 INFIFO pop register"] +pub mod in_pop_ch5; +#[doc = "IN_STATE_CH5 (r) register accessor: RX CH5 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_state_ch5`] module"] +pub type IN_STATE_CH5 = crate::Reg; +#[doc = "RX CH5 state register"] +pub mod in_state_ch5; +#[doc = "IN_ARB_CH5 (rw) register accessor: RX CH5 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_arb_ch5`] module"] +pub type IN_ARB_CH5 = crate::Reg; +#[doc = "RX CH5 arb register"] +pub mod in_arb_ch5; +#[doc = "IN_FIFO_CNT_CH5 (r) register accessor: rx CH5 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_fifo_cnt_ch5`] module"] +pub type IN_FIFO_CNT_CH5 = crate::Reg; +#[doc = "rx CH5 fifo cnt register"] +pub mod in_fifo_cnt_ch5; +#[doc = "IN_POP_DATA_CNT_CH5 (r) register accessor: rx CH5 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop_data_cnt_ch5`] module"] +pub type IN_POP_DATA_CNT_CH5 = crate::Reg; +#[doc = "rx CH5 pop data cnt register"] +pub mod in_pop_data_cnt_ch5; +#[doc = "IN_XADDR_CH5 (r) register accessor: rx CH5 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_xaddr_ch5`] module"] +pub type IN_XADDR_CH5 = crate::Reg; +#[doc = "rx CH5 xaddr register"] +pub mod in_xaddr_ch5; +#[doc = "IN_BUF_HB_RCV_CH5 (r) register accessor: rx CH5 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_buf_hb_rcv_ch5`] module"] +pub type IN_BUF_HB_RCV_CH5 = crate::Reg; +#[doc = "rx CH5 buf len hb rcv register"] +pub mod in_buf_hb_rcv_ch5; +#[doc = "INTER_AXI_ERR (r) register accessor: inter memory axi err register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_axi_err::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inter_axi_err`] module"] +pub type INTER_AXI_ERR = crate::Reg; +#[doc = "inter memory axi err register"] +pub mod inter_axi_err; +#[doc = "EXTER_AXI_ERR (r) register accessor: exter memory axi err register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exter_axi_err::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exter_axi_err`] module"] +pub type EXTER_AXI_ERR = crate::Reg; +#[doc = "exter memory axi err register"] +pub mod exter_axi_err; +#[doc = "RST_CONF (rw) register accessor: axi reset config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_conf`] module"] +pub type RST_CONF = crate::Reg; +#[doc = "axi reset config register"] +pub mod rst_conf; +#[doc = "INTER_MEM_START_ADDR0 (rw) register accessor: Start address of inter memory range0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_mem_start_addr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inter_mem_start_addr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inter_mem_start_addr0`] module"] +pub type INTER_MEM_START_ADDR0 = crate::Reg; +#[doc = "Start address of inter memory range0 register"] +pub mod inter_mem_start_addr0; +#[doc = "INTER_MEM_END_ADDR0 (rw) register accessor: end address of inter memory range0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_mem_end_addr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inter_mem_end_addr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inter_mem_end_addr0`] module"] +pub type INTER_MEM_END_ADDR0 = crate::Reg; +#[doc = "end address of inter memory range0 register"] +pub mod inter_mem_end_addr0; +#[doc = "INTER_MEM_START_ADDR1 (rw) register accessor: Start address of inter memory range1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_mem_start_addr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inter_mem_start_addr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inter_mem_start_addr1`] module"] +pub type INTER_MEM_START_ADDR1 = crate::Reg; +#[doc = "Start address of inter memory range1 register"] +pub mod inter_mem_start_addr1; +#[doc = "INTER_MEM_END_ADDR1 (rw) register accessor: end address of inter memory range1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_mem_end_addr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inter_mem_end_addr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inter_mem_end_addr1`] module"] +pub type INTER_MEM_END_ADDR1 = crate::Reg; +#[doc = "end address of inter memory range1 register"] +pub mod inter_mem_end_addr1; +#[doc = "EXTER_MEM_START_ADDR0 (rw) register accessor: Start address of exter memory range0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exter_mem_start_addr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exter_mem_start_addr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exter_mem_start_addr0`] module"] +pub type EXTER_MEM_START_ADDR0 = crate::Reg; +#[doc = "Start address of exter memory range0 register"] +pub mod exter_mem_start_addr0; +#[doc = "EXTER_MEM_END_ADDR0 (rw) register accessor: end address of exter memory range0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exter_mem_end_addr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exter_mem_end_addr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exter_mem_end_addr0`] module"] +pub type EXTER_MEM_END_ADDR0 = crate::Reg; +#[doc = "end address of exter memory range0 register"] +pub mod exter_mem_end_addr0; +#[doc = "EXTER_MEM_START_ADDR1 (rw) register accessor: Start address of exter memory range1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exter_mem_start_addr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exter_mem_start_addr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exter_mem_start_addr1`] module"] +pub type EXTER_MEM_START_ADDR1 = crate::Reg; +#[doc = "Start address of exter memory range1 register"] +pub mod exter_mem_start_addr1; +#[doc = "EXTER_MEM_END_ADDR1 (rw) register accessor: end address of exter memory range1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exter_mem_end_addr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exter_mem_end_addr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exter_mem_end_addr1`] module"] +pub type EXTER_MEM_END_ADDR1 = crate::Reg; +#[doc = "end address of exter memory range1 register"] +pub mod exter_mem_end_addr1; +#[doc = "OUT_ARB_CONFIG (rw) register accessor: reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_arb_config`] module"] +pub type OUT_ARB_CONFIG = crate::Reg; +#[doc = "reserved"] +pub mod out_arb_config; +#[doc = "IN_ARB_CONFIG (rw) register accessor: reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_arb_config`] module"] +pub type IN_ARB_CONFIG = crate::Reg; +#[doc = "reserved"] +pub mod in_arb_config; +#[doc = "DATE (rw) register accessor: reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "reserved"] +pub mod date; +#[doc = "COUNTER_RST (rw) register accessor: counter reset register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`counter_rst::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`counter_rst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@counter_rst`] module"] +pub type COUNTER_RST = crate::Reg; +#[doc = "counter reset register"] +pub mod counter_rst; +#[doc = "RX_CH0_COUNTER (r) register accessor: rx ch0 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch0_counter::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_ch0_counter`] module"] +pub type RX_CH0_COUNTER = crate::Reg; +#[doc = "rx ch0 counter register"] +pub mod rx_ch0_counter; +#[doc = "RX_CH1_COUNTER (r) register accessor: rx ch1 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch1_counter::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_ch1_counter`] module"] +pub type RX_CH1_COUNTER = crate::Reg; +#[doc = "rx ch1 counter register"] +pub mod rx_ch1_counter; +#[doc = "RX_CH2_COUNTER (r) register accessor: rx ch2 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch2_counter::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_ch2_counter`] module"] +pub type RX_CH2_COUNTER = crate::Reg; +#[doc = "rx ch2 counter register"] +pub mod rx_ch2_counter; +#[doc = "RX_CH5_COUNTER (r) register accessor: rx ch5 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch5_counter::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_ch5_counter`] module"] +pub type RX_CH5_COUNTER = crate::Reg; +#[doc = "rx ch5 counter register"] +pub mod rx_ch5_counter; diff --git a/esp32p4/src/h264_dma/counter_rst.rs b/esp32p4/src/h264_dma/counter_rst.rs new file mode 100644 index 0000000000..f921d48156 --- /dev/null +++ b/esp32p4/src/h264_dma/counter_rst.rs @@ -0,0 +1,123 @@ +#[doc = "Register `COUNTER_RST` reader"] +pub type R = crate::R; +#[doc = "Register `COUNTER_RST` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CH0_EXTER_COUNTER_RST` reader - Write 1 then write 0 to this bit to reset rx ch0 counter."] +pub type RX_CH0_EXTER_COUNTER_RST_R = crate::BitReader; +#[doc = "Field `RX_CH0_EXTER_COUNTER_RST` writer - Write 1 then write 0 to this bit to reset rx ch0 counter."] +pub type RX_CH0_EXTER_COUNTER_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH1_EXTER_COUNTER_RST` reader - Write 1 then write 0 to this bit to reset rx ch1 counter."] +pub type RX_CH1_EXTER_COUNTER_RST_R = crate::BitReader; +#[doc = "Field `RX_CH1_EXTER_COUNTER_RST` writer - Write 1 then write 0 to this bit to reset rx ch1 counter."] +pub type RX_CH1_EXTER_COUNTER_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH2_INTER_COUNTER_RST` reader - Write 1 then write 0 to this bit to reset rx ch2 counter."] +pub type RX_CH2_INTER_COUNTER_RST_R = crate::BitReader; +#[doc = "Field `RX_CH2_INTER_COUNTER_RST` writer - Write 1 then write 0 to this bit to reset rx ch2 counter."] +pub type RX_CH2_INTER_COUNTER_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH5_INTER_COUNTER_RST` reader - Write 1 then write 0 to this bit to reset rx ch5 counter."] +pub type RX_CH5_INTER_COUNTER_RST_R = crate::BitReader; +#[doc = "Field `RX_CH5_INTER_COUNTER_RST` writer - Write 1 then write 0 to this bit to reset rx ch5 counter."] +pub type RX_CH5_INTER_COUNTER_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 then write 0 to this bit to reset rx ch0 counter."] + #[inline(always)] + pub fn rx_ch0_exter_counter_rst(&self) -> RX_CH0_EXTER_COUNTER_RST_R { + RX_CH0_EXTER_COUNTER_RST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 then write 0 to this bit to reset rx ch1 counter."] + #[inline(always)] + pub fn rx_ch1_exter_counter_rst(&self) -> RX_CH1_EXTER_COUNTER_RST_R { + RX_CH1_EXTER_COUNTER_RST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 then write 0 to this bit to reset rx ch2 counter."] + #[inline(always)] + pub fn rx_ch2_inter_counter_rst(&self) -> RX_CH2_INTER_COUNTER_RST_R { + RX_CH2_INTER_COUNTER_RST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1 then write 0 to this bit to reset rx ch5 counter."] + #[inline(always)] + pub fn rx_ch5_inter_counter_rst(&self) -> RX_CH5_INTER_COUNTER_RST_R { + RX_CH5_INTER_COUNTER_RST_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COUNTER_RST") + .field( + "rx_ch0_exter_counter_rst", + &format_args!("{}", self.rx_ch0_exter_counter_rst().bit()), + ) + .field( + "rx_ch1_exter_counter_rst", + &format_args!("{}", self.rx_ch1_exter_counter_rst().bit()), + ) + .field( + "rx_ch2_inter_counter_rst", + &format_args!("{}", self.rx_ch2_inter_counter_rst().bit()), + ) + .field( + "rx_ch5_inter_counter_rst", + &format_args!("{}", self.rx_ch5_inter_counter_rst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 then write 0 to this bit to reset rx ch0 counter."] + #[inline(always)] + #[must_use] + pub fn rx_ch0_exter_counter_rst(&mut self) -> RX_CH0_EXTER_COUNTER_RST_W { + RX_CH0_EXTER_COUNTER_RST_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 then write 0 to this bit to reset rx ch1 counter."] + #[inline(always)] + #[must_use] + pub fn rx_ch1_exter_counter_rst(&mut self) -> RX_CH1_EXTER_COUNTER_RST_W { + RX_CH1_EXTER_COUNTER_RST_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 then write 0 to this bit to reset rx ch2 counter."] + #[inline(always)] + #[must_use] + pub fn rx_ch2_inter_counter_rst(&mut self) -> RX_CH2_INTER_COUNTER_RST_W { + RX_CH2_INTER_COUNTER_RST_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 then write 0 to this bit to reset rx ch5 counter."] + #[inline(always)] + #[must_use] + pub fn rx_ch5_inter_counter_rst(&mut self) -> RX_CH5_INTER_COUNTER_RST_W { + RX_CH5_INTER_COUNTER_RST_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "counter reset register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`counter_rst::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`counter_rst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COUNTER_RST_SPEC; +impl crate::RegisterSpec for COUNTER_RST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`counter_rst::R`](R) reader structure"] +impl crate::Readable for COUNTER_RST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`counter_rst::W`](W) writer structure"] +impl crate::Writable for COUNTER_RST_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COUNTER_RST to value 0"] +impl crate::Resettable for COUNTER_RST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/date.rs b/esp32p4/src/h264_dma/date.rs new file mode 100644 index 0000000000..badc8eeed5 --- /dev/null +++ b/esp32p4/src/h264_dma/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - register version."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - register version."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - register version."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - register version."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x2023_0403"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2023_0403; +} diff --git a/esp32p4/src/h264_dma/exter_axi_err.rs b/esp32p4/src/h264_dma/exter_axi_err.rs new file mode 100644 index 0000000000..d70c948034 --- /dev/null +++ b/esp32p4/src/h264_dma/exter_axi_err.rs @@ -0,0 +1,105 @@ +#[doc = "Register `EXTER_AXI_ERR` reader"] +pub type R = crate::R; +#[doc = "Field `EXTER_RID_ERR_CNT` reader - AXI read id err cnt"] +pub type EXTER_RID_ERR_CNT_R = crate::FieldReader; +#[doc = "Field `EXTER_RRESP_ERR_CNT` reader - AXI read resp err cnt"] +pub type EXTER_RRESP_ERR_CNT_R = crate::FieldReader; +#[doc = "Field `EXTER_WRESP_ERR_CNT` reader - AXI write resp err cnt"] +pub type EXTER_WRESP_ERR_CNT_R = crate::FieldReader; +#[doc = "Field `EXTER_RD_FIFO_CNT` reader - AXI read cmd fifo remain cmd count"] +pub type EXTER_RD_FIFO_CNT_R = crate::FieldReader; +#[doc = "Field `EXTER_RD_BAK_FIFO_CNT` reader - AXI read backup cmd fifo remain cmd count"] +pub type EXTER_RD_BAK_FIFO_CNT_R = crate::FieldReader; +#[doc = "Field `EXTER_WR_FIFO_CNT` reader - AXI write cmd fifo remain cmd count"] +pub type EXTER_WR_FIFO_CNT_R = crate::FieldReader; +#[doc = "Field `EXTER_WR_BAK_FIFO_CNT` reader - AXI write backup cmd fifo remain cmd count"] +pub type EXTER_WR_BAK_FIFO_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - AXI read id err cnt"] + #[inline(always)] + pub fn exter_rid_err_cnt(&self) -> EXTER_RID_ERR_CNT_R { + EXTER_RID_ERR_CNT_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - AXI read resp err cnt"] + #[inline(always)] + pub fn exter_rresp_err_cnt(&self) -> EXTER_RRESP_ERR_CNT_R { + EXTER_RRESP_ERR_CNT_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - AXI write resp err cnt"] + #[inline(always)] + pub fn exter_wresp_err_cnt(&self) -> EXTER_WRESP_ERR_CNT_R { + EXTER_WRESP_ERR_CNT_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:14 - AXI read cmd fifo remain cmd count"] + #[inline(always)] + pub fn exter_rd_fifo_cnt(&self) -> EXTER_RD_FIFO_CNT_R { + EXTER_RD_FIFO_CNT_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:18 - AXI read backup cmd fifo remain cmd count"] + #[inline(always)] + pub fn exter_rd_bak_fifo_cnt(&self) -> EXTER_RD_BAK_FIFO_CNT_R { + EXTER_RD_BAK_FIFO_CNT_R::new(((self.bits >> 15) & 0x0f) as u8) + } + #[doc = "Bits 19:21 - AXI write cmd fifo remain cmd count"] + #[inline(always)] + pub fn exter_wr_fifo_cnt(&self) -> EXTER_WR_FIFO_CNT_R { + EXTER_WR_FIFO_CNT_R::new(((self.bits >> 19) & 7) as u8) + } + #[doc = "Bits 22:25 - AXI write backup cmd fifo remain cmd count"] + #[inline(always)] + pub fn exter_wr_bak_fifo_cnt(&self) -> EXTER_WR_BAK_FIFO_CNT_R { + EXTER_WR_BAK_FIFO_CNT_R::new(((self.bits >> 22) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXTER_AXI_ERR") + .field( + "exter_rid_err_cnt", + &format_args!("{}", self.exter_rid_err_cnt().bits()), + ) + .field( + "exter_rresp_err_cnt", + &format_args!("{}", self.exter_rresp_err_cnt().bits()), + ) + .field( + "exter_wresp_err_cnt", + &format_args!("{}", self.exter_wresp_err_cnt().bits()), + ) + .field( + "exter_rd_fifo_cnt", + &format_args!("{}", self.exter_rd_fifo_cnt().bits()), + ) + .field( + "exter_rd_bak_fifo_cnt", + &format_args!("{}", self.exter_rd_bak_fifo_cnt().bits()), + ) + .field( + "exter_wr_fifo_cnt", + &format_args!("{}", self.exter_wr_fifo_cnt().bits()), + ) + .field( + "exter_wr_bak_fifo_cnt", + &format_args!("{}", self.exter_wr_bak_fifo_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "exter memory axi err register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exter_axi_err::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXTER_AXI_ERR_SPEC; +impl crate::RegisterSpec for EXTER_AXI_ERR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`exter_axi_err::R`](R) reader structure"] +impl crate::Readable for EXTER_AXI_ERR_SPEC {} +#[doc = "`reset()` method sets EXTER_AXI_ERR to value 0"] +impl crate::Resettable for EXTER_AXI_ERR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/exter_mem_end_addr0.rs b/esp32p4/src/h264_dma/exter_mem_end_addr0.rs new file mode 100644 index 0000000000..f31097b2b1 --- /dev/null +++ b/esp32p4/src/h264_dma/exter_mem_end_addr0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `EXTER_MEM_END_ADDR0` reader"] +pub type R = crate::R; +#[doc = "Register `EXTER_MEM_END_ADDR0` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_EXTER_MEM_END_ADDR0` reader - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_EXTER_MEM_END_ADDR0_R = crate::FieldReader; +#[doc = "Field `ACCESS_EXTER_MEM_END_ADDR0` writer - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_EXTER_MEM_END_ADDR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + pub fn access_exter_mem_end_addr0(&self) -> ACCESS_EXTER_MEM_END_ADDR0_R { + ACCESS_EXTER_MEM_END_ADDR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXTER_MEM_END_ADDR0") + .field( + "access_exter_mem_end_addr0", + &format_args!("{}", self.access_exter_mem_end_addr0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + #[must_use] + pub fn access_exter_mem_end_addr0( + &mut self, + ) -> ACCESS_EXTER_MEM_END_ADDR0_W { + ACCESS_EXTER_MEM_END_ADDR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "end address of exter memory range0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exter_mem_end_addr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exter_mem_end_addr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXTER_MEM_END_ADDR0_SPEC; +impl crate::RegisterSpec for EXTER_MEM_END_ADDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`exter_mem_end_addr0::R`](R) reader structure"] +impl crate::Readable for EXTER_MEM_END_ADDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`exter_mem_end_addr0::W`](W) writer structure"] +impl crate::Writable for EXTER_MEM_END_ADDR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXTER_MEM_END_ADDR0 to value 0x8fff_ffff"] +impl crate::Resettable for EXTER_MEM_END_ADDR0_SPEC { + const RESET_VALUE: Self::Ux = 0x8fff_ffff; +} diff --git a/esp32p4/src/h264_dma/exter_mem_end_addr1.rs b/esp32p4/src/h264_dma/exter_mem_end_addr1.rs new file mode 100644 index 0000000000..47c7e6ac32 --- /dev/null +++ b/esp32p4/src/h264_dma/exter_mem_end_addr1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `EXTER_MEM_END_ADDR1` reader"] +pub type R = crate::R; +#[doc = "Register `EXTER_MEM_END_ADDR1` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_EXTER_MEM_END_ADDR1` reader - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_EXTER_MEM_END_ADDR1_R = crate::FieldReader; +#[doc = "Field `ACCESS_EXTER_MEM_END_ADDR1` writer - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_EXTER_MEM_END_ADDR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + pub fn access_exter_mem_end_addr1(&self) -> ACCESS_EXTER_MEM_END_ADDR1_R { + ACCESS_EXTER_MEM_END_ADDR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXTER_MEM_END_ADDR1") + .field( + "access_exter_mem_end_addr1", + &format_args!("{}", self.access_exter_mem_end_addr1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + #[must_use] + pub fn access_exter_mem_end_addr1( + &mut self, + ) -> ACCESS_EXTER_MEM_END_ADDR1_W { + ACCESS_EXTER_MEM_END_ADDR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "end address of exter memory range1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exter_mem_end_addr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exter_mem_end_addr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXTER_MEM_END_ADDR1_SPEC; +impl crate::RegisterSpec for EXTER_MEM_END_ADDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`exter_mem_end_addr1::R`](R) reader structure"] +impl crate::Readable for EXTER_MEM_END_ADDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`exter_mem_end_addr1::W`](W) writer structure"] +impl crate::Writable for EXTER_MEM_END_ADDR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXTER_MEM_END_ADDR1 to value 0x8fff_ffff"] +impl crate::Resettable for EXTER_MEM_END_ADDR1_SPEC { + const RESET_VALUE: Self::Ux = 0x8fff_ffff; +} diff --git a/esp32p4/src/h264_dma/exter_mem_start_addr0.rs b/esp32p4/src/h264_dma/exter_mem_start_addr0.rs new file mode 100644 index 0000000000..819f3c8224 --- /dev/null +++ b/esp32p4/src/h264_dma/exter_mem_start_addr0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `EXTER_MEM_START_ADDR0` reader"] +pub type R = crate::R; +#[doc = "Register `EXTER_MEM_START_ADDR0` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_EXTER_MEM_START_ADDR0` reader - The start address of accessible address space."] +pub type ACCESS_EXTER_MEM_START_ADDR0_R = crate::FieldReader; +#[doc = "Field `ACCESS_EXTER_MEM_START_ADDR0` writer - The start address of accessible address space."] +pub type ACCESS_EXTER_MEM_START_ADDR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + pub fn access_exter_mem_start_addr0(&self) -> ACCESS_EXTER_MEM_START_ADDR0_R { + ACCESS_EXTER_MEM_START_ADDR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXTER_MEM_START_ADDR0") + .field( + "access_exter_mem_start_addr0", + &format_args!("{}", self.access_exter_mem_start_addr0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + #[must_use] + pub fn access_exter_mem_start_addr0( + &mut self, + ) -> ACCESS_EXTER_MEM_START_ADDR0_W { + ACCESS_EXTER_MEM_START_ADDR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Start address of exter memory range0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exter_mem_start_addr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exter_mem_start_addr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXTER_MEM_START_ADDR0_SPEC; +impl crate::RegisterSpec for EXTER_MEM_START_ADDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`exter_mem_start_addr0::R`](R) reader structure"] +impl crate::Readable for EXTER_MEM_START_ADDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`exter_mem_start_addr0::W`](W) writer structure"] +impl crate::Writable for EXTER_MEM_START_ADDR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXTER_MEM_START_ADDR0 to value 0x3010_0000"] +impl crate::Resettable for EXTER_MEM_START_ADDR0_SPEC { + const RESET_VALUE: Self::Ux = 0x3010_0000; +} diff --git a/esp32p4/src/h264_dma/exter_mem_start_addr1.rs b/esp32p4/src/h264_dma/exter_mem_start_addr1.rs new file mode 100644 index 0000000000..3c8d500ecf --- /dev/null +++ b/esp32p4/src/h264_dma/exter_mem_start_addr1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `EXTER_MEM_START_ADDR1` reader"] +pub type R = crate::R; +#[doc = "Register `EXTER_MEM_START_ADDR1` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_EXTER_MEM_START_ADDR1` reader - The start address of accessible address space."] +pub type ACCESS_EXTER_MEM_START_ADDR1_R = crate::FieldReader; +#[doc = "Field `ACCESS_EXTER_MEM_START_ADDR1` writer - The start address of accessible address space."] +pub type ACCESS_EXTER_MEM_START_ADDR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + pub fn access_exter_mem_start_addr1(&self) -> ACCESS_EXTER_MEM_START_ADDR1_R { + ACCESS_EXTER_MEM_START_ADDR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXTER_MEM_START_ADDR1") + .field( + "access_exter_mem_start_addr1", + &format_args!("{}", self.access_exter_mem_start_addr1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + #[must_use] + pub fn access_exter_mem_start_addr1( + &mut self, + ) -> ACCESS_EXTER_MEM_START_ADDR1_W { + ACCESS_EXTER_MEM_START_ADDR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Start address of exter memory range1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exter_mem_start_addr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exter_mem_start_addr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXTER_MEM_START_ADDR1_SPEC; +impl crate::RegisterSpec for EXTER_MEM_START_ADDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`exter_mem_start_addr1::R`](R) reader structure"] +impl crate::Readable for EXTER_MEM_START_ADDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`exter_mem_start_addr1::W`](W) writer structure"] +impl crate::Writable for EXTER_MEM_START_ADDR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXTER_MEM_START_ADDR1 to value 0x3010_0000"] +impl crate::Resettable for EXTER_MEM_START_ADDR1_SPEC { + const RESET_VALUE: Self::Ux = 0x3010_0000; +} diff --git a/esp32p4/src/h264_dma/in_arb_ch0.rs b/esp32p4/src/h264_dma/in_arb_ch0.rs new file mode 100644 index 0000000000..164cc9f1b9 --- /dev/null +++ b/esp32p4/src/h264_dma/in_arb_ch0.rs @@ -0,0 +1,104 @@ +#[doc = "Register `IN_ARB_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ARB_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH0` reader - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH0_R = crate::FieldReader; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH0` writer - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `EXTER_IN_ARB_PRIORITY_CH0` reader - Set the priority of channel"] +pub type EXTER_IN_ARB_PRIORITY_CH0_R = crate::FieldReader; +#[doc = "Field `EXTER_IN_ARB_PRIORITY_CH0` writer - Set the priority of channel"] +pub type EXTER_IN_ARB_PRIORITY_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH0` reader - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH0_R = crate::FieldReader; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH0` writer - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + pub fn in_arb_token_num_ch0(&self) -> IN_ARB_TOKEN_NUM_CH0_R { + IN_ARB_TOKEN_NUM_CH0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + pub fn exter_in_arb_priority_ch0(&self) -> EXTER_IN_ARB_PRIORITY_CH0_R { + EXTER_IN_ARB_PRIORITY_CH0_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + pub fn inter_in_arb_priority_ch0(&self) -> INTER_IN_ARB_PRIORITY_CH0_R { + INTER_IN_ARB_PRIORITY_CH0_R::new(((self.bits >> 6) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ARB_CH0") + .field( + "in_arb_token_num_ch0", + &format_args!("{}", self.in_arb_token_num_ch0().bits()), + ) + .field( + "exter_in_arb_priority_ch0", + &format_args!("{}", self.exter_in_arb_priority_ch0().bits()), + ) + .field( + "inter_in_arb_priority_ch0", + &format_args!("{}", self.inter_in_arb_priority_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + #[must_use] + pub fn in_arb_token_num_ch0(&mut self) -> IN_ARB_TOKEN_NUM_CH0_W { + IN_ARB_TOKEN_NUM_CH0_W::new(self, 0) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn exter_in_arb_priority_ch0(&mut self) -> EXTER_IN_ARB_PRIORITY_CH0_W { + EXTER_IN_ARB_PRIORITY_CH0_W::new(self, 4) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn inter_in_arb_priority_ch0(&mut self) -> INTER_IN_ARB_PRIORITY_CH0_W { + INTER_IN_ARB_PRIORITY_CH0_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH0 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ARB_CH0_SPEC; +impl crate::RegisterSpec for IN_ARB_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_arb_ch0::R`](R) reader structure"] +impl crate::Readable for IN_ARB_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_arb_ch0::W`](W) writer structure"] +impl crate::Writable for IN_ARB_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ARB_CH0 to value 0x51"] +impl crate::Resettable for IN_ARB_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x51; +} diff --git a/esp32p4/src/h264_dma/in_arb_ch1.rs b/esp32p4/src/h264_dma/in_arb_ch1.rs new file mode 100644 index 0000000000..c111a3cc9d --- /dev/null +++ b/esp32p4/src/h264_dma/in_arb_ch1.rs @@ -0,0 +1,104 @@ +#[doc = "Register `IN_ARB_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ARB_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH1` reader - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH1_R = crate::FieldReader; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH1` writer - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `EXTER_IN_ARB_PRIORITY_CH1` reader - Set the priority of channel"] +pub type EXTER_IN_ARB_PRIORITY_CH1_R = crate::FieldReader; +#[doc = "Field `EXTER_IN_ARB_PRIORITY_CH1` writer - Set the priority of channel"] +pub type EXTER_IN_ARB_PRIORITY_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH1` reader - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH1_R = crate::FieldReader; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH1` writer - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + pub fn in_arb_token_num_ch1(&self) -> IN_ARB_TOKEN_NUM_CH1_R { + IN_ARB_TOKEN_NUM_CH1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + pub fn exter_in_arb_priority_ch1(&self) -> EXTER_IN_ARB_PRIORITY_CH1_R { + EXTER_IN_ARB_PRIORITY_CH1_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + pub fn inter_in_arb_priority_ch1(&self) -> INTER_IN_ARB_PRIORITY_CH1_R { + INTER_IN_ARB_PRIORITY_CH1_R::new(((self.bits >> 6) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ARB_CH1") + .field( + "in_arb_token_num_ch1", + &format_args!("{}", self.in_arb_token_num_ch1().bits()), + ) + .field( + "exter_in_arb_priority_ch1", + &format_args!("{}", self.exter_in_arb_priority_ch1().bits()), + ) + .field( + "inter_in_arb_priority_ch1", + &format_args!("{}", self.inter_in_arb_priority_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + #[must_use] + pub fn in_arb_token_num_ch1(&mut self) -> IN_ARB_TOKEN_NUM_CH1_W { + IN_ARB_TOKEN_NUM_CH1_W::new(self, 0) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn exter_in_arb_priority_ch1(&mut self) -> EXTER_IN_ARB_PRIORITY_CH1_W { + EXTER_IN_ARB_PRIORITY_CH1_W::new(self, 4) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn inter_in_arb_priority_ch1(&mut self) -> INTER_IN_ARB_PRIORITY_CH1_W { + INTER_IN_ARB_PRIORITY_CH1_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH1 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ARB_CH1_SPEC; +impl crate::RegisterSpec for IN_ARB_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_arb_ch1::R`](R) reader structure"] +impl crate::Readable for IN_ARB_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_arb_ch1::W`](W) writer structure"] +impl crate::Writable for IN_ARB_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ARB_CH1 to value 0x51"] +impl crate::Resettable for IN_ARB_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x51; +} diff --git a/esp32p4/src/h264_dma/in_arb_ch2.rs b/esp32p4/src/h264_dma/in_arb_ch2.rs new file mode 100644 index 0000000000..108405106a --- /dev/null +++ b/esp32p4/src/h264_dma/in_arb_ch2.rs @@ -0,0 +1,85 @@ +#[doc = "Register `IN_ARB_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ARB_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH2` reader - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH2_R = crate::FieldReader; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH2` writer - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH2` reader - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH2_R = crate::FieldReader; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH2` writer - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + pub fn in_arb_token_num_ch2(&self) -> IN_ARB_TOKEN_NUM_CH2_R { + IN_ARB_TOKEN_NUM_CH2_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + pub fn inter_in_arb_priority_ch2(&self) -> INTER_IN_ARB_PRIORITY_CH2_R { + INTER_IN_ARB_PRIORITY_CH2_R::new(((self.bits >> 6) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ARB_CH2") + .field( + "in_arb_token_num_ch2", + &format_args!("{}", self.in_arb_token_num_ch2().bits()), + ) + .field( + "inter_in_arb_priority_ch2", + &format_args!("{}", self.inter_in_arb_priority_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + #[must_use] + pub fn in_arb_token_num_ch2(&mut self) -> IN_ARB_TOKEN_NUM_CH2_W { + IN_ARB_TOKEN_NUM_CH2_W::new(self, 0) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn inter_in_arb_priority_ch2(&mut self) -> INTER_IN_ARB_PRIORITY_CH2_W { + INTER_IN_ARB_PRIORITY_CH2_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH2 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ARB_CH2_SPEC; +impl crate::RegisterSpec for IN_ARB_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_arb_ch2::R`](R) reader structure"] +impl crate::Readable for IN_ARB_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_arb_ch2::W`](W) writer structure"] +impl crate::Writable for IN_ARB_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ARB_CH2 to value 0x41"] +impl crate::Resettable for IN_ARB_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x41; +} diff --git a/esp32p4/src/h264_dma/in_arb_ch3.rs b/esp32p4/src/h264_dma/in_arb_ch3.rs new file mode 100644 index 0000000000..40442cecb5 --- /dev/null +++ b/esp32p4/src/h264_dma/in_arb_ch3.rs @@ -0,0 +1,85 @@ +#[doc = "Register `IN_ARB_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ARB_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH3` reader - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH3_R = crate::FieldReader; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH3` writer - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH3` reader - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH3_R = crate::FieldReader; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH3` writer - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + pub fn in_arb_token_num_ch3(&self) -> IN_ARB_TOKEN_NUM_CH3_R { + IN_ARB_TOKEN_NUM_CH3_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + pub fn inter_in_arb_priority_ch3(&self) -> INTER_IN_ARB_PRIORITY_CH3_R { + INTER_IN_ARB_PRIORITY_CH3_R::new(((self.bits >> 6) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ARB_CH3") + .field( + "in_arb_token_num_ch3", + &format_args!("{}", self.in_arb_token_num_ch3().bits()), + ) + .field( + "inter_in_arb_priority_ch3", + &format_args!("{}", self.inter_in_arb_priority_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + #[must_use] + pub fn in_arb_token_num_ch3(&mut self) -> IN_ARB_TOKEN_NUM_CH3_W { + IN_ARB_TOKEN_NUM_CH3_W::new(self, 0) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn inter_in_arb_priority_ch3(&mut self) -> INTER_IN_ARB_PRIORITY_CH3_W { + INTER_IN_ARB_PRIORITY_CH3_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH3 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ARB_CH3_SPEC; +impl crate::RegisterSpec for IN_ARB_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_arb_ch3::R`](R) reader structure"] +impl crate::Readable for IN_ARB_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_arb_ch3::W`](W) writer structure"] +impl crate::Writable for IN_ARB_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ARB_CH3 to value 0x41"] +impl crate::Resettable for IN_ARB_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x41; +} diff --git a/esp32p4/src/h264_dma/in_arb_ch4.rs b/esp32p4/src/h264_dma/in_arb_ch4.rs new file mode 100644 index 0000000000..3efaf788b0 --- /dev/null +++ b/esp32p4/src/h264_dma/in_arb_ch4.rs @@ -0,0 +1,104 @@ +#[doc = "Register `IN_ARB_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ARB_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH4` reader - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH4_R = crate::FieldReader; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH4` writer - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `EXTER_IN_ARB_PRIORITY_CH4` reader - Set the priority of channel"] +pub type EXTER_IN_ARB_PRIORITY_CH4_R = crate::FieldReader; +#[doc = "Field `EXTER_IN_ARB_PRIORITY_CH4` writer - Set the priority of channel"] +pub type EXTER_IN_ARB_PRIORITY_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH4` reader - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH4_R = crate::FieldReader; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH4` writer - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + pub fn in_arb_token_num_ch4(&self) -> IN_ARB_TOKEN_NUM_CH4_R { + IN_ARB_TOKEN_NUM_CH4_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + pub fn exter_in_arb_priority_ch4(&self) -> EXTER_IN_ARB_PRIORITY_CH4_R { + EXTER_IN_ARB_PRIORITY_CH4_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + pub fn inter_in_arb_priority_ch4(&self) -> INTER_IN_ARB_PRIORITY_CH4_R { + INTER_IN_ARB_PRIORITY_CH4_R::new(((self.bits >> 6) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ARB_CH4") + .field( + "in_arb_token_num_ch4", + &format_args!("{}", self.in_arb_token_num_ch4().bits()), + ) + .field( + "exter_in_arb_priority_ch4", + &format_args!("{}", self.exter_in_arb_priority_ch4().bits()), + ) + .field( + "inter_in_arb_priority_ch4", + &format_args!("{}", self.inter_in_arb_priority_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + #[must_use] + pub fn in_arb_token_num_ch4(&mut self) -> IN_ARB_TOKEN_NUM_CH4_W { + IN_ARB_TOKEN_NUM_CH4_W::new(self, 0) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn exter_in_arb_priority_ch4(&mut self) -> EXTER_IN_ARB_PRIORITY_CH4_W { + EXTER_IN_ARB_PRIORITY_CH4_W::new(self, 4) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn inter_in_arb_priority_ch4(&mut self) -> INTER_IN_ARB_PRIORITY_CH4_W { + INTER_IN_ARB_PRIORITY_CH4_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH4 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ARB_CH4_SPEC; +impl crate::RegisterSpec for IN_ARB_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_arb_ch4::R`](R) reader structure"] +impl crate::Readable for IN_ARB_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_arb_ch4::W`](W) writer structure"] +impl crate::Writable for IN_ARB_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ARB_CH4 to value 0x51"] +impl crate::Resettable for IN_ARB_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x51; +} diff --git a/esp32p4/src/h264_dma/in_arb_ch5.rs b/esp32p4/src/h264_dma/in_arb_ch5.rs new file mode 100644 index 0000000000..eeaec0fb69 --- /dev/null +++ b/esp32p4/src/h264_dma/in_arb_ch5.rs @@ -0,0 +1,85 @@ +#[doc = "Register `IN_ARB_CH5` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ARB_CH5` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH5` reader - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH5_R = crate::FieldReader; +#[doc = "Field `IN_ARB_TOKEN_NUM_CH5` writer - Set the max number of token count of arbiter"] +pub type IN_ARB_TOKEN_NUM_CH5_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH5` reader - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH5_R = crate::FieldReader; +#[doc = "Field `INTER_IN_ARB_PRIORITY_CH5` writer - Set the priority of channel"] +pub type INTER_IN_ARB_PRIORITY_CH5_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + pub fn in_arb_token_num_ch5(&self) -> IN_ARB_TOKEN_NUM_CH5_R { + IN_ARB_TOKEN_NUM_CH5_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + pub fn inter_in_arb_priority_ch5(&self) -> INTER_IN_ARB_PRIORITY_CH5_R { + INTER_IN_ARB_PRIORITY_CH5_R::new(((self.bits >> 6) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ARB_CH5") + .field( + "in_arb_token_num_ch5", + &format_args!("{}", self.in_arb_token_num_ch5().bits()), + ) + .field( + "inter_in_arb_priority_ch5", + &format_args!("{}", self.inter_in_arb_priority_ch5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + #[must_use] + pub fn in_arb_token_num_ch5(&mut self) -> IN_ARB_TOKEN_NUM_CH5_W { + IN_ARB_TOKEN_NUM_CH5_W::new(self, 0) + } + #[doc = "Bits 6:8 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn inter_in_arb_priority_ch5(&mut self) -> INTER_IN_ARB_PRIORITY_CH5_W { + INTER_IN_ARB_PRIORITY_CH5_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH5 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_ch5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_ch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ARB_CH5_SPEC; +impl crate::RegisterSpec for IN_ARB_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_arb_ch5::R`](R) reader structure"] +impl crate::Readable for IN_ARB_CH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_arb_ch5::W`](W) writer structure"] +impl crate::Writable for IN_ARB_CH5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ARB_CH5 to value 0x41"] +impl crate::Resettable for IN_ARB_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0x41; +} diff --git a/esp32p4/src/h264_dma/in_arb_config.rs b/esp32p4/src/h264_dma/in_arb_config.rs new file mode 100644 index 0000000000..45afca1ce6 --- /dev/null +++ b/esp32p4/src/h264_dma/in_arb_config.rs @@ -0,0 +1,85 @@ +#[doc = "Register `IN_ARB_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ARB_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ARB_TIMEOUT_NUM` reader - Set the max number of timeout count of arbiter"] +pub type IN_ARB_TIMEOUT_NUM_R = crate::FieldReader; +#[doc = "Field `IN_ARB_TIMEOUT_NUM` writer - Set the max number of timeout count of arbiter"] +pub type IN_ARB_TIMEOUT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `IN_WEIGHT_EN` reader - reserved"] +pub type IN_WEIGHT_EN_R = crate::BitReader; +#[doc = "Field `IN_WEIGHT_EN` writer - reserved"] +pub type IN_WEIGHT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Set the max number of timeout count of arbiter"] + #[inline(always)] + pub fn in_arb_timeout_num(&self) -> IN_ARB_TIMEOUT_NUM_R { + IN_ARB_TIMEOUT_NUM_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - reserved"] + #[inline(always)] + pub fn in_weight_en(&self) -> IN_WEIGHT_EN_R { + IN_WEIGHT_EN_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ARB_CONFIG") + .field( + "in_arb_timeout_num", + &format_args!("{}", self.in_arb_timeout_num().bits()), + ) + .field( + "in_weight_en", + &format_args!("{}", self.in_weight_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Set the max number of timeout count of arbiter"] + #[inline(always)] + #[must_use] + pub fn in_arb_timeout_num(&mut self) -> IN_ARB_TIMEOUT_NUM_W { + IN_ARB_TIMEOUT_NUM_W::new(self, 0) + } + #[doc = "Bit 16 - reserved"] + #[inline(always)] + #[must_use] + pub fn in_weight_en(&mut self) -> IN_WEIGHT_EN_W { + IN_WEIGHT_EN_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_arb_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_arb_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ARB_CONFIG_SPEC; +impl crate::RegisterSpec for IN_ARB_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_arb_config::R`](R) reader structure"] +impl crate::Readable for IN_ARB_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_arb_config::W`](W) writer structure"] +impl crate::Writable for IN_ARB_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ARB_CONFIG to value 0"] +impl crate::Resettable for IN_ARB_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_buf_hb_rcv_ch0.rs b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch0.rs new file mode 100644 index 0000000000..d0bf130b6f --- /dev/null +++ b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_BUF_HB_RCV_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_BUF_HB_RCV_CH0` reader - only for debug"] +pub type IN_CMDFIFO_BUF_HB_RCV_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:28 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_buf_hb_rcv_ch0(&self) -> IN_CMDFIFO_BUF_HB_RCV_CH0_R { + IN_CMDFIFO_BUF_HB_RCV_CH0_R::new(self.bits & 0x1fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_BUF_HB_RCV_CH0") + .field( + "in_cmdfifo_buf_hb_rcv_ch0", + &format_args!("{}", self.in_cmdfifo_buf_hb_rcv_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH0 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_BUF_HB_RCV_CH0_SPEC; +impl crate::RegisterSpec for IN_BUF_HB_RCV_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_buf_hb_rcv_ch0::R`](R) reader structure"] +impl crate::Readable for IN_BUF_HB_RCV_CH0_SPEC {} +#[doc = "`reset()` method sets IN_BUF_HB_RCV_CH0 to value 0"] +impl crate::Resettable for IN_BUF_HB_RCV_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_buf_hb_rcv_ch1.rs b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch1.rs new file mode 100644 index 0000000000..c0f73802f7 --- /dev/null +++ b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_BUF_HB_RCV_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_BUF_HB_RCV_CH1` reader - only for debug"] +pub type IN_CMDFIFO_BUF_HB_RCV_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:28 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_buf_hb_rcv_ch1(&self) -> IN_CMDFIFO_BUF_HB_RCV_CH1_R { + IN_CMDFIFO_BUF_HB_RCV_CH1_R::new(self.bits & 0x1fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_BUF_HB_RCV_CH1") + .field( + "in_cmdfifo_buf_hb_rcv_ch1", + &format_args!("{}", self.in_cmdfifo_buf_hb_rcv_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH1 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_BUF_HB_RCV_CH1_SPEC; +impl crate::RegisterSpec for IN_BUF_HB_RCV_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_buf_hb_rcv_ch1::R`](R) reader structure"] +impl crate::Readable for IN_BUF_HB_RCV_CH1_SPEC {} +#[doc = "`reset()` method sets IN_BUF_HB_RCV_CH1 to value 0"] +impl crate::Resettable for IN_BUF_HB_RCV_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_buf_hb_rcv_ch2.rs b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch2.rs new file mode 100644 index 0000000000..4eb4f15e74 --- /dev/null +++ b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_BUF_HB_RCV_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_BUF_HB_RCV_CH2` reader - only for debug"] +pub type IN_CMDFIFO_BUF_HB_RCV_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:28 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_buf_hb_rcv_ch2(&self) -> IN_CMDFIFO_BUF_HB_RCV_CH2_R { + IN_CMDFIFO_BUF_HB_RCV_CH2_R::new(self.bits & 0x1fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_BUF_HB_RCV_CH2") + .field( + "in_cmdfifo_buf_hb_rcv_ch2", + &format_args!("{}", self.in_cmdfifo_buf_hb_rcv_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH2 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_BUF_HB_RCV_CH2_SPEC; +impl crate::RegisterSpec for IN_BUF_HB_RCV_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_buf_hb_rcv_ch2::R`](R) reader structure"] +impl crate::Readable for IN_BUF_HB_RCV_CH2_SPEC {} +#[doc = "`reset()` method sets IN_BUF_HB_RCV_CH2 to value 0"] +impl crate::Resettable for IN_BUF_HB_RCV_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_buf_hb_rcv_ch3.rs b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch3.rs new file mode 100644 index 0000000000..9f879d2fd2 --- /dev/null +++ b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_BUF_HB_RCV_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_BUF_HB_RCV_CH3` reader - only for debug"] +pub type IN_CMDFIFO_BUF_HB_RCV_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:28 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_buf_hb_rcv_ch3(&self) -> IN_CMDFIFO_BUF_HB_RCV_CH3_R { + IN_CMDFIFO_BUF_HB_RCV_CH3_R::new(self.bits & 0x1fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_BUF_HB_RCV_CH3") + .field( + "in_cmdfifo_buf_hb_rcv_ch3", + &format_args!("{}", self.in_cmdfifo_buf_hb_rcv_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH3 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_BUF_HB_RCV_CH3_SPEC; +impl crate::RegisterSpec for IN_BUF_HB_RCV_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_buf_hb_rcv_ch3::R`](R) reader structure"] +impl crate::Readable for IN_BUF_HB_RCV_CH3_SPEC {} +#[doc = "`reset()` method sets IN_BUF_HB_RCV_CH3 to value 0"] +impl crate::Resettable for IN_BUF_HB_RCV_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_buf_hb_rcv_ch4.rs b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch4.rs new file mode 100644 index 0000000000..b2b478eb48 --- /dev/null +++ b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_BUF_HB_RCV_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_BUF_HB_RCV_CH4` reader - only for debug"] +pub type IN_CMDFIFO_BUF_HB_RCV_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:28 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_buf_hb_rcv_ch4(&self) -> IN_CMDFIFO_BUF_HB_RCV_CH4_R { + IN_CMDFIFO_BUF_HB_RCV_CH4_R::new(self.bits & 0x1fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_BUF_HB_RCV_CH4") + .field( + "in_cmdfifo_buf_hb_rcv_ch4", + &format_args!("{}", self.in_cmdfifo_buf_hb_rcv_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH4 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_BUF_HB_RCV_CH4_SPEC; +impl crate::RegisterSpec for IN_BUF_HB_RCV_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_buf_hb_rcv_ch4::R`](R) reader structure"] +impl crate::Readable for IN_BUF_HB_RCV_CH4_SPEC {} +#[doc = "`reset()` method sets IN_BUF_HB_RCV_CH4 to value 0"] +impl crate::Resettable for IN_BUF_HB_RCV_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_buf_hb_rcv_ch5.rs b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch5.rs new file mode 100644 index 0000000000..b4faf19411 --- /dev/null +++ b/esp32p4/src/h264_dma/in_buf_hb_rcv_ch5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_BUF_HB_RCV_CH5` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_BUF_HB_RCV_CH5` reader - only for debug"] +pub type IN_CMDFIFO_BUF_HB_RCV_CH5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:28 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_buf_hb_rcv_ch5(&self) -> IN_CMDFIFO_BUF_HB_RCV_CH5_R { + IN_CMDFIFO_BUF_HB_RCV_CH5_R::new(self.bits & 0x1fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_BUF_HB_RCV_CH5") + .field( + "in_cmdfifo_buf_hb_rcv_ch5", + &format_args!("{}", self.in_cmdfifo_buf_hb_rcv_ch5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH5 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_buf_hb_rcv_ch5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_BUF_HB_RCV_CH5_SPEC; +impl crate::RegisterSpec for IN_BUF_HB_RCV_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_buf_hb_rcv_ch5::R`](R) reader structure"] +impl crate::Readable for IN_BUF_HB_RCV_CH5_SPEC {} +#[doc = "`reset()` method sets IN_BUF_HB_RCV_CH5 to value 0"] +impl crate::Resettable for IN_BUF_HB_RCV_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_conf0_ch0.rs b/esp32p4/src/h264_dma/in_conf0_ch0.rs new file mode 100644 index 0000000000..a526a4f1dd --- /dev/null +++ b/esp32p4/src/h264_dma/in_conf0_ch0.rs @@ -0,0 +1,196 @@ +#[doc = "Register `IN_CONF0_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF0_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `INDSCR_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] +pub type INDSCR_BURST_EN_CH0_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] +pub type INDSCR_BURST_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ECC_AES_EN_CH0` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH0_R = crate::BitReader; +#[doc = "Field `IN_ECC_AES_EN_CH0` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_CHECK_OWNER_CH0` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH0_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER_CH0` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH0` reader - Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH0_R = crate::FieldReader; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH0` writer - Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IN_PAGE_BOUND_EN_CH0` reader - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH0_R = crate::BitReader; +#[doc = "Field `IN_PAGE_BOUND_EN_CH0` writer - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_RST_CH0` reader - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH0_R = crate::BitReader; +#[doc = "Field `IN_RST_CH0` writer - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_CMD_DISABLE_CH0` reader - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH0_R = crate::BitReader; +#[doc = "Field `IN_CMD_DISABLE_CH0` writer - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ARB_WEIGHT_OPT_DIS_CH0` reader - Set this bit to 1 to disable arbiter optimum weight function."] +pub type IN_ARB_WEIGHT_OPT_DIS_CH0_R = crate::BitReader; +#[doc = "Field `IN_ARB_WEIGHT_OPT_DIS_CH0` writer - Set this bit to 1 to disable arbiter optimum weight function."] +pub type IN_ARB_WEIGHT_OPT_DIS_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] + #[inline(always)] + pub fn indscr_burst_en_ch0(&self) -> INDSCR_BURST_EN_CH0_R { + INDSCR_BURST_EN_CH0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + pub fn in_ecc_aes_en_ch0(&self) -> IN_ECC_AES_EN_CH0_R { + IN_ECC_AES_EN_CH0_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn in_check_owner_ch0(&self) -> IN_CHECK_OWNER_CH0_R { + IN_CHECK_OWNER_CH0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 6:8 - Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + pub fn in_mem_burst_length_ch0(&self) -> IN_MEM_BURST_LENGTH_CH0_R { + IN_MEM_BURST_LENGTH_CH0_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + pub fn in_page_bound_en_ch0(&self) -> IN_PAGE_BOUND_EN_CH0_R { + IN_PAGE_BOUND_EN_CH0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + pub fn in_rst_ch0(&self) -> IN_RST_CH0_R { + IN_RST_CH0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + pub fn in_cmd_disable_ch0(&self) -> IN_CMD_DISABLE_CH0_R { + IN_CMD_DISABLE_CH0_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + pub fn in_arb_weight_opt_dis_ch0(&self) -> IN_ARB_WEIGHT_OPT_DIS_CH0_R { + IN_ARB_WEIGHT_OPT_DIS_CH0_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF0_CH0") + .field( + "indscr_burst_en_ch0", + &format_args!("{}", self.indscr_burst_en_ch0().bit()), + ) + .field( + "in_ecc_aes_en_ch0", + &format_args!("{}", self.in_ecc_aes_en_ch0().bit()), + ) + .field( + "in_check_owner_ch0", + &format_args!("{}", self.in_check_owner_ch0().bit()), + ) + .field( + "in_mem_burst_length_ch0", + &format_args!("{}", self.in_mem_burst_length_ch0().bits()), + ) + .field( + "in_page_bound_en_ch0", + &format_args!("{}", self.in_page_bound_en_ch0().bit()), + ) + .field("in_rst_ch0", &format_args!("{}", self.in_rst_ch0().bit())) + .field( + "in_cmd_disable_ch0", + &format_args!("{}", self.in_cmd_disable_ch0().bit()), + ) + .field( + "in_arb_weight_opt_dis_ch0", + &format_args!("{}", self.in_arb_weight_opt_dis_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] + #[inline(always)] + #[must_use] + pub fn indscr_burst_en_ch0(&mut self) -> INDSCR_BURST_EN_CH0_W { + INDSCR_BURST_EN_CH0_W::new(self, 2) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + #[must_use] + pub fn in_ecc_aes_en_ch0(&mut self) -> IN_ECC_AES_EN_CH0_W { + IN_ECC_AES_EN_CH0_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn in_check_owner_ch0(&mut self) -> IN_CHECK_OWNER_CH0_W { + IN_CHECK_OWNER_CH0_W::new(self, 4) + } + #[doc = "Bits 6:8 - Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + #[must_use] + pub fn in_mem_burst_length_ch0(&mut self) -> IN_MEM_BURST_LENGTH_CH0_W { + IN_MEM_BURST_LENGTH_CH0_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + #[must_use] + pub fn in_page_bound_en_ch0(&mut self) -> IN_PAGE_BOUND_EN_CH0_W { + IN_PAGE_BOUND_EN_CH0_W::new(self, 12) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + #[must_use] + pub fn in_rst_ch0(&mut self) -> IN_RST_CH0_W { + IN_RST_CH0_W::new(self, 24) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + #[must_use] + pub fn in_cmd_disable_ch0(&mut self) -> IN_CMD_DISABLE_CH0_W { + IN_CMD_DISABLE_CH0_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + #[must_use] + pub fn in_arb_weight_opt_dis_ch0(&mut self) -> IN_ARB_WEIGHT_OPT_DIS_CH0_W { + IN_ARB_WEIGHT_OPT_DIS_CH0_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH0 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF0_CH0_SPEC; +impl crate::RegisterSpec for IN_CONF0_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf0_ch0::R`](R) reader structure"] +impl crate::Readable for IN_CONF0_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf0_ch0::W`](W) writer structure"] +impl crate::Writable for IN_CONF0_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF0_CH0 to value 0"] +impl crate::Resettable for IN_CONF0_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_conf0_ch1.rs b/esp32p4/src/h264_dma/in_conf0_ch1.rs new file mode 100644 index 0000000000..d61c73e0ee --- /dev/null +++ b/esp32p4/src/h264_dma/in_conf0_ch1.rs @@ -0,0 +1,196 @@ +#[doc = "Register `IN_CONF0_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF0_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `INDSCR_BURST_EN_CH1` reader - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] +pub type INDSCR_BURST_EN_CH1_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN_CH1` writer - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] +pub type INDSCR_BURST_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ECC_AES_EN_CH1` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH1_R = crate::BitReader; +#[doc = "Field `IN_ECC_AES_EN_CH1` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_CHECK_OWNER_CH1` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH1_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER_CH1` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH1` reader - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH1_R = crate::FieldReader; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH1` writer - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IN_PAGE_BOUND_EN_CH1` reader - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH1_R = crate::BitReader; +#[doc = "Field `IN_PAGE_BOUND_EN_CH1` writer - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_RST_CH1` reader - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH1_R = crate::BitReader; +#[doc = "Field `IN_RST_CH1` writer - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_CMD_DISABLE_CH1` reader - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH1_R = crate::BitReader; +#[doc = "Field `IN_CMD_DISABLE_CH1` writer - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ARB_WEIGHT_OPT_DIS_CH1` reader - Set this bit to 1 to disable arbiter optimum weight function."] +pub type IN_ARB_WEIGHT_OPT_DIS_CH1_R = crate::BitReader; +#[doc = "Field `IN_ARB_WEIGHT_OPT_DIS_CH1` writer - Set this bit to 1 to disable arbiter optimum weight function."] +pub type IN_ARB_WEIGHT_OPT_DIS_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] + #[inline(always)] + pub fn indscr_burst_en_ch1(&self) -> INDSCR_BURST_EN_CH1_R { + INDSCR_BURST_EN_CH1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + pub fn in_ecc_aes_en_ch1(&self) -> IN_ECC_AES_EN_CH1_R { + IN_ECC_AES_EN_CH1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn in_check_owner_ch1(&self) -> IN_CHECK_OWNER_CH1_R { + IN_CHECK_OWNER_CH1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 6:8 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + pub fn in_mem_burst_length_ch1(&self) -> IN_MEM_BURST_LENGTH_CH1_R { + IN_MEM_BURST_LENGTH_CH1_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + pub fn in_page_bound_en_ch1(&self) -> IN_PAGE_BOUND_EN_CH1_R { + IN_PAGE_BOUND_EN_CH1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + pub fn in_rst_ch1(&self) -> IN_RST_CH1_R { + IN_RST_CH1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + pub fn in_cmd_disable_ch1(&self) -> IN_CMD_DISABLE_CH1_R { + IN_CMD_DISABLE_CH1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + pub fn in_arb_weight_opt_dis_ch1(&self) -> IN_ARB_WEIGHT_OPT_DIS_CH1_R { + IN_ARB_WEIGHT_OPT_DIS_CH1_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF0_CH1") + .field( + "indscr_burst_en_ch1", + &format_args!("{}", self.indscr_burst_en_ch1().bit()), + ) + .field( + "in_ecc_aes_en_ch1", + &format_args!("{}", self.in_ecc_aes_en_ch1().bit()), + ) + .field( + "in_check_owner_ch1", + &format_args!("{}", self.in_check_owner_ch1().bit()), + ) + .field( + "in_mem_burst_length_ch1", + &format_args!("{}", self.in_mem_burst_length_ch1().bits()), + ) + .field( + "in_page_bound_en_ch1", + &format_args!("{}", self.in_page_bound_en_ch1().bit()), + ) + .field("in_rst_ch1", &format_args!("{}", self.in_rst_ch1().bit())) + .field( + "in_cmd_disable_ch1", + &format_args!("{}", self.in_cmd_disable_ch1().bit()), + ) + .field( + "in_arb_weight_opt_dis_ch1", + &format_args!("{}", self.in_arb_weight_opt_dis_ch1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] + #[inline(always)] + #[must_use] + pub fn indscr_burst_en_ch1(&mut self) -> INDSCR_BURST_EN_CH1_W { + INDSCR_BURST_EN_CH1_W::new(self, 2) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + #[must_use] + pub fn in_ecc_aes_en_ch1(&mut self) -> IN_ECC_AES_EN_CH1_W { + IN_ECC_AES_EN_CH1_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn in_check_owner_ch1(&mut self) -> IN_CHECK_OWNER_CH1_W { + IN_CHECK_OWNER_CH1_W::new(self, 4) + } + #[doc = "Bits 6:8 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + #[must_use] + pub fn in_mem_burst_length_ch1(&mut self) -> IN_MEM_BURST_LENGTH_CH1_W { + IN_MEM_BURST_LENGTH_CH1_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + #[must_use] + pub fn in_page_bound_en_ch1(&mut self) -> IN_PAGE_BOUND_EN_CH1_W { + IN_PAGE_BOUND_EN_CH1_W::new(self, 12) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + #[must_use] + pub fn in_rst_ch1(&mut self) -> IN_RST_CH1_W { + IN_RST_CH1_W::new(self, 24) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + #[must_use] + pub fn in_cmd_disable_ch1(&mut self) -> IN_CMD_DISABLE_CH1_W { + IN_CMD_DISABLE_CH1_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + #[must_use] + pub fn in_arb_weight_opt_dis_ch1(&mut self) -> IN_ARB_WEIGHT_OPT_DIS_CH1_W { + IN_ARB_WEIGHT_OPT_DIS_CH1_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH1 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF0_CH1_SPEC; +impl crate::RegisterSpec for IN_CONF0_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf0_ch1::R`](R) reader structure"] +impl crate::Readable for IN_CONF0_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf0_ch1::W`](W) writer structure"] +impl crate::Writable for IN_CONF0_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF0_CH1 to value 0"] +impl crate::Resettable for IN_CONF0_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_conf0_ch2.rs b/esp32p4/src/h264_dma/in_conf0_ch2.rs new file mode 100644 index 0000000000..9ce099a73a --- /dev/null +++ b/esp32p4/src/h264_dma/in_conf0_ch2.rs @@ -0,0 +1,196 @@ +#[doc = "Register `IN_CONF0_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF0_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `INDSCR_BURST_EN_CH2` reader - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] +pub type INDSCR_BURST_EN_CH2_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN_CH2` writer - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] +pub type INDSCR_BURST_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ECC_AES_EN_CH2` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH2_R = crate::BitReader; +#[doc = "Field `IN_ECC_AES_EN_CH2` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_CHECK_OWNER_CH2` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH2_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER_CH2` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH2` reader - Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH2_R = crate::FieldReader; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH2` writer - Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IN_PAGE_BOUND_EN_CH2` reader - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH2_R = crate::BitReader; +#[doc = "Field `IN_PAGE_BOUND_EN_CH2` writer - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_RST_CH2` reader - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH2_R = crate::BitReader; +#[doc = "Field `IN_RST_CH2` writer - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_CMD_DISABLE_CH2` reader - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH2_R = crate::BitReader; +#[doc = "Field `IN_CMD_DISABLE_CH2` writer - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ARB_WEIGHT_OPT_DIS_CH2` reader - Set this bit to 1 to disable arbiter optimum weight function."] +pub type IN_ARB_WEIGHT_OPT_DIS_CH2_R = crate::BitReader; +#[doc = "Field `IN_ARB_WEIGHT_OPT_DIS_CH2` writer - Set this bit to 1 to disable arbiter optimum weight function."] +pub type IN_ARB_WEIGHT_OPT_DIS_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] + #[inline(always)] + pub fn indscr_burst_en_ch2(&self) -> INDSCR_BURST_EN_CH2_R { + INDSCR_BURST_EN_CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + pub fn in_ecc_aes_en_ch2(&self) -> IN_ECC_AES_EN_CH2_R { + IN_ECC_AES_EN_CH2_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn in_check_owner_ch2(&self) -> IN_CHECK_OWNER_CH2_R { + IN_CHECK_OWNER_CH2_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 6:8 - Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + pub fn in_mem_burst_length_ch2(&self) -> IN_MEM_BURST_LENGTH_CH2_R { + IN_MEM_BURST_LENGTH_CH2_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + pub fn in_page_bound_en_ch2(&self) -> IN_PAGE_BOUND_EN_CH2_R { + IN_PAGE_BOUND_EN_CH2_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + pub fn in_rst_ch2(&self) -> IN_RST_CH2_R { + IN_RST_CH2_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + pub fn in_cmd_disable_ch2(&self) -> IN_CMD_DISABLE_CH2_R { + IN_CMD_DISABLE_CH2_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + pub fn in_arb_weight_opt_dis_ch2(&self) -> IN_ARB_WEIGHT_OPT_DIS_CH2_R { + IN_ARB_WEIGHT_OPT_DIS_CH2_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF0_CH2") + .field( + "indscr_burst_en_ch2", + &format_args!("{}", self.indscr_burst_en_ch2().bit()), + ) + .field( + "in_ecc_aes_en_ch2", + &format_args!("{}", self.in_ecc_aes_en_ch2().bit()), + ) + .field( + "in_check_owner_ch2", + &format_args!("{}", self.in_check_owner_ch2().bit()), + ) + .field( + "in_mem_burst_length_ch2", + &format_args!("{}", self.in_mem_burst_length_ch2().bits()), + ) + .field( + "in_page_bound_en_ch2", + &format_args!("{}", self.in_page_bound_en_ch2().bit()), + ) + .field("in_rst_ch2", &format_args!("{}", self.in_rst_ch2().bit())) + .field( + "in_cmd_disable_ch2", + &format_args!("{}", self.in_cmd_disable_ch2().bit()), + ) + .field( + "in_arb_weight_opt_dis_ch2", + &format_args!("{}", self.in_arb_weight_opt_dis_ch2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] + #[inline(always)] + #[must_use] + pub fn indscr_burst_en_ch2(&mut self) -> INDSCR_BURST_EN_CH2_W { + INDSCR_BURST_EN_CH2_W::new(self, 2) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + #[must_use] + pub fn in_ecc_aes_en_ch2(&mut self) -> IN_ECC_AES_EN_CH2_W { + IN_ECC_AES_EN_CH2_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn in_check_owner_ch2(&mut self) -> IN_CHECK_OWNER_CH2_W { + IN_CHECK_OWNER_CH2_W::new(self, 4) + } + #[doc = "Bits 6:8 - Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + #[must_use] + pub fn in_mem_burst_length_ch2(&mut self) -> IN_MEM_BURST_LENGTH_CH2_W { + IN_MEM_BURST_LENGTH_CH2_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + #[must_use] + pub fn in_page_bound_en_ch2(&mut self) -> IN_PAGE_BOUND_EN_CH2_W { + IN_PAGE_BOUND_EN_CH2_W::new(self, 12) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + #[must_use] + pub fn in_rst_ch2(&mut self) -> IN_RST_CH2_W { + IN_RST_CH2_W::new(self, 24) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + #[must_use] + pub fn in_cmd_disable_ch2(&mut self) -> IN_CMD_DISABLE_CH2_W { + IN_CMD_DISABLE_CH2_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + #[must_use] + pub fn in_arb_weight_opt_dis_ch2(&mut self) -> IN_ARB_WEIGHT_OPT_DIS_CH2_W { + IN_ARB_WEIGHT_OPT_DIS_CH2_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH2 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF0_CH2_SPEC; +impl crate::RegisterSpec for IN_CONF0_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf0_ch2::R`](R) reader structure"] +impl crate::Readable for IN_CONF0_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf0_ch2::W`](W) writer structure"] +impl crate::Writable for IN_CONF0_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF0_CH2 to value 0"] +impl crate::Resettable for IN_CONF0_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_conf0_ch3.rs b/esp32p4/src/h264_dma/in_conf0_ch3.rs new file mode 100644 index 0000000000..ae5df54a53 --- /dev/null +++ b/esp32p4/src/h264_dma/in_conf0_ch3.rs @@ -0,0 +1,196 @@ +#[doc = "Register `IN_CONF0_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF0_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `INDSCR_BURST_EN_CH3` reader - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] +pub type INDSCR_BURST_EN_CH3_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN_CH3` writer - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] +pub type INDSCR_BURST_EN_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ECC_AES_EN_CH3` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH3_R = crate::BitReader; +#[doc = "Field `IN_ECC_AES_EN_CH3` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_CHECK_OWNER_CH3` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH3_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER_CH3` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH3` reader - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH3_R = crate::FieldReader; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH3` writer - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IN_PAGE_BOUND_EN_CH3` reader - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH3_R = crate::BitReader; +#[doc = "Field `IN_PAGE_BOUND_EN_CH3` writer - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_RST_CH3` reader - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH3_R = crate::BitReader; +#[doc = "Field `IN_RST_CH3` writer - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_CMD_DISABLE_CH3` reader - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH3_R = crate::BitReader; +#[doc = "Field `IN_CMD_DISABLE_CH3` writer - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ARB_WEIGHT_OPT_DIS_CH3` reader - Set this bit to 1 to disable arbiter optimum weight function."] +pub type IN_ARB_WEIGHT_OPT_DIS_CH3_R = crate::BitReader; +#[doc = "Field `IN_ARB_WEIGHT_OPT_DIS_CH3` writer - Set this bit to 1 to disable arbiter optimum weight function."] +pub type IN_ARB_WEIGHT_OPT_DIS_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] + #[inline(always)] + pub fn indscr_burst_en_ch3(&self) -> INDSCR_BURST_EN_CH3_R { + INDSCR_BURST_EN_CH3_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + pub fn in_ecc_aes_en_ch3(&self) -> IN_ECC_AES_EN_CH3_R { + IN_ECC_AES_EN_CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn in_check_owner_ch3(&self) -> IN_CHECK_OWNER_CH3_R { + IN_CHECK_OWNER_CH3_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 6:8 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + pub fn in_mem_burst_length_ch3(&self) -> IN_MEM_BURST_LENGTH_CH3_R { + IN_MEM_BURST_LENGTH_CH3_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + pub fn in_page_bound_en_ch3(&self) -> IN_PAGE_BOUND_EN_CH3_R { + IN_PAGE_BOUND_EN_CH3_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + pub fn in_rst_ch3(&self) -> IN_RST_CH3_R { + IN_RST_CH3_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + pub fn in_cmd_disable_ch3(&self) -> IN_CMD_DISABLE_CH3_R { + IN_CMD_DISABLE_CH3_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + pub fn in_arb_weight_opt_dis_ch3(&self) -> IN_ARB_WEIGHT_OPT_DIS_CH3_R { + IN_ARB_WEIGHT_OPT_DIS_CH3_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF0_CH3") + .field( + "indscr_burst_en_ch3", + &format_args!("{}", self.indscr_burst_en_ch3().bit()), + ) + .field( + "in_ecc_aes_en_ch3", + &format_args!("{}", self.in_ecc_aes_en_ch3().bit()), + ) + .field( + "in_check_owner_ch3", + &format_args!("{}", self.in_check_owner_ch3().bit()), + ) + .field( + "in_mem_burst_length_ch3", + &format_args!("{}", self.in_mem_burst_length_ch3().bits()), + ) + .field( + "in_page_bound_en_ch3", + &format_args!("{}", self.in_page_bound_en_ch3().bit()), + ) + .field("in_rst_ch3", &format_args!("{}", self.in_rst_ch3().bit())) + .field( + "in_cmd_disable_ch3", + &format_args!("{}", self.in_cmd_disable_ch3().bit()), + ) + .field( + "in_arb_weight_opt_dis_ch3", + &format_args!("{}", self.in_arb_weight_opt_dis_ch3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] + #[inline(always)] + #[must_use] + pub fn indscr_burst_en_ch3(&mut self) -> INDSCR_BURST_EN_CH3_W { + INDSCR_BURST_EN_CH3_W::new(self, 2) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + #[must_use] + pub fn in_ecc_aes_en_ch3(&mut self) -> IN_ECC_AES_EN_CH3_W { + IN_ECC_AES_EN_CH3_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn in_check_owner_ch3(&mut self) -> IN_CHECK_OWNER_CH3_W { + IN_CHECK_OWNER_CH3_W::new(self, 4) + } + #[doc = "Bits 6:8 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + #[must_use] + pub fn in_mem_burst_length_ch3(&mut self) -> IN_MEM_BURST_LENGTH_CH3_W { + IN_MEM_BURST_LENGTH_CH3_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + #[must_use] + pub fn in_page_bound_en_ch3(&mut self) -> IN_PAGE_BOUND_EN_CH3_W { + IN_PAGE_BOUND_EN_CH3_W::new(self, 12) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + #[must_use] + pub fn in_rst_ch3(&mut self) -> IN_RST_CH3_W { + IN_RST_CH3_W::new(self, 24) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + #[must_use] + pub fn in_cmd_disable_ch3(&mut self) -> IN_CMD_DISABLE_CH3_W { + IN_CMD_DISABLE_CH3_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + #[must_use] + pub fn in_arb_weight_opt_dis_ch3(&mut self) -> IN_ARB_WEIGHT_OPT_DIS_CH3_W { + IN_ARB_WEIGHT_OPT_DIS_CH3_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH3 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF0_CH3_SPEC; +impl crate::RegisterSpec for IN_CONF0_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf0_ch3::R`](R) reader structure"] +impl crate::Readable for IN_CONF0_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf0_ch3::W`](W) writer structure"] +impl crate::Writable for IN_CONF0_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF0_CH3 to value 0"] +impl crate::Resettable for IN_CONF0_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_conf0_ch4.rs b/esp32p4/src/h264_dma/in_conf0_ch4.rs new file mode 100644 index 0000000000..e526aa367a --- /dev/null +++ b/esp32p4/src/h264_dma/in_conf0_ch4.rs @@ -0,0 +1,196 @@ +#[doc = "Register `IN_CONF0_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF0_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `INDSCR_BURST_EN_CH4` reader - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] +pub type INDSCR_BURST_EN_CH4_R = crate::BitReader; +#[doc = "Field `INDSCR_BURST_EN_CH4` writer - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] +pub type INDSCR_BURST_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ECC_AES_EN_CH4` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH4_R = crate::BitReader; +#[doc = "Field `IN_ECC_AES_EN_CH4` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_CHECK_OWNER_CH4` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH4_R = crate::BitReader; +#[doc = "Field `IN_CHECK_OWNER_CH4` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type IN_CHECK_OWNER_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH4` reader - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH4_R = crate::FieldReader; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH4` writer - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IN_PAGE_BOUND_EN_CH4` reader - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH4_R = crate::BitReader; +#[doc = "Field `IN_PAGE_BOUND_EN_CH4` writer - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_RST_CH4` reader - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH4_R = crate::BitReader; +#[doc = "Field `IN_RST_CH4` writer - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_CMD_DISABLE_CH4` reader - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH4_R = crate::BitReader; +#[doc = "Field `IN_CMD_DISABLE_CH4` writer - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ARB_WEIGHT_OPT_DIS_CH4` reader - Set this bit to 1 to disable arbiter optimum weight function."] +pub type IN_ARB_WEIGHT_OPT_DIS_CH4_R = crate::BitReader; +#[doc = "Field `IN_ARB_WEIGHT_OPT_DIS_CH4` writer - Set this bit to 1 to disable arbiter optimum weight function."] +pub type IN_ARB_WEIGHT_OPT_DIS_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] + #[inline(always)] + pub fn indscr_burst_en_ch4(&self) -> INDSCR_BURST_EN_CH4_R { + INDSCR_BURST_EN_CH4_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + pub fn in_ecc_aes_en_ch4(&self) -> IN_ECC_AES_EN_CH4_R { + IN_ECC_AES_EN_CH4_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn in_check_owner_ch4(&self) -> IN_CHECK_OWNER_CH4_R { + IN_CHECK_OWNER_CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 6:8 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + pub fn in_mem_burst_length_ch4(&self) -> IN_MEM_BURST_LENGTH_CH4_R { + IN_MEM_BURST_LENGTH_CH4_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + pub fn in_page_bound_en_ch4(&self) -> IN_PAGE_BOUND_EN_CH4_R { + IN_PAGE_BOUND_EN_CH4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + pub fn in_rst_ch4(&self) -> IN_RST_CH4_R { + IN_RST_CH4_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + pub fn in_cmd_disable_ch4(&self) -> IN_CMD_DISABLE_CH4_R { + IN_CMD_DISABLE_CH4_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + pub fn in_arb_weight_opt_dis_ch4(&self) -> IN_ARB_WEIGHT_OPT_DIS_CH4_R { + IN_ARB_WEIGHT_OPT_DIS_CH4_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF0_CH4") + .field( + "indscr_burst_en_ch4", + &format_args!("{}", self.indscr_burst_en_ch4().bit()), + ) + .field( + "in_ecc_aes_en_ch4", + &format_args!("{}", self.in_ecc_aes_en_ch4().bit()), + ) + .field( + "in_check_owner_ch4", + &format_args!("{}", self.in_check_owner_ch4().bit()), + ) + .field( + "in_mem_burst_length_ch4", + &format_args!("{}", self.in_mem_burst_length_ch4().bits()), + ) + .field( + "in_page_bound_en_ch4", + &format_args!("{}", self.in_page_bound_en_ch4().bit()), + ) + .field("in_rst_ch4", &format_args!("{}", self.in_rst_ch4().bit())) + .field( + "in_cmd_disable_ch4", + &format_args!("{}", self.in_cmd_disable_ch4().bit()), + ) + .field( + "in_arb_weight_opt_dis_ch4", + &format_args!("{}", self.in_arb_weight_opt_dis_ch4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."] + #[inline(always)] + #[must_use] + pub fn indscr_burst_en_ch4(&mut self) -> INDSCR_BURST_EN_CH4_W { + INDSCR_BURST_EN_CH4_W::new(self, 2) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + #[must_use] + pub fn in_ecc_aes_en_ch4(&mut self) -> IN_ECC_AES_EN_CH4_W { + IN_ECC_AES_EN_CH4_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn in_check_owner_ch4(&mut self) -> IN_CHECK_OWNER_CH4_W { + IN_CHECK_OWNER_CH4_W::new(self, 4) + } + #[doc = "Bits 6:8 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + #[must_use] + pub fn in_mem_burst_length_ch4(&mut self) -> IN_MEM_BURST_LENGTH_CH4_W { + IN_MEM_BURST_LENGTH_CH4_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + #[must_use] + pub fn in_page_bound_en_ch4(&mut self) -> IN_PAGE_BOUND_EN_CH4_W { + IN_PAGE_BOUND_EN_CH4_W::new(self, 12) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + #[must_use] + pub fn in_rst_ch4(&mut self) -> IN_RST_CH4_W { + IN_RST_CH4_W::new(self, 24) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + #[must_use] + pub fn in_cmd_disable_ch4(&mut self) -> IN_CMD_DISABLE_CH4_W { + IN_CMD_DISABLE_CH4_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + #[must_use] + pub fn in_arb_weight_opt_dis_ch4(&mut self) -> IN_ARB_WEIGHT_OPT_DIS_CH4_W { + IN_ARB_WEIGHT_OPT_DIS_CH4_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH4 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF0_CH4_SPEC; +impl crate::RegisterSpec for IN_CONF0_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf0_ch4::R`](R) reader structure"] +impl crate::Readable for IN_CONF0_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf0_ch4::W`](W) writer structure"] +impl crate::Writable for IN_CONF0_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF0_CH4 to value 0"] +impl crate::Resettable for IN_CONF0_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_conf0_ch5.rs b/esp32p4/src/h264_dma/in_conf0_ch5.rs new file mode 100644 index 0000000000..c432514992 --- /dev/null +++ b/esp32p4/src/h264_dma/in_conf0_ch5.rs @@ -0,0 +1,139 @@ +#[doc = "Register `IN_CONF0_CH5` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF0_CH5` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ECC_AES_EN_CH5` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH5_R = crate::BitReader; +#[doc = "Field `IN_ECC_AES_EN_CH5` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type IN_ECC_AES_EN_CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH5` reader - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH5_R = crate::FieldReader; +#[doc = "Field `IN_MEM_BURST_LENGTH_CH5` writer - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type IN_MEM_BURST_LENGTH_CH5_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IN_PAGE_BOUND_EN_CH5` reader - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH5_R = crate::BitReader; +#[doc = "Field `IN_PAGE_BOUND_EN_CH5` writer - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] +pub type IN_PAGE_BOUND_EN_CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_RST_CH5` reader - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH5_R = crate::BitReader; +#[doc = "Field `IN_RST_CH5` writer - Write 1 then write 0 to this bit to reset Rx channel"] +pub type IN_RST_CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_CMD_DISABLE_CH5` reader - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH5_R = crate::BitReader; +#[doc = "Field `IN_CMD_DISABLE_CH5` writer - Write 1 before reset and write 0 after reset"] +pub type IN_CMD_DISABLE_CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + pub fn in_ecc_aes_en_ch5(&self) -> IN_ECC_AES_EN_CH5_R { + IN_ECC_AES_EN_CH5_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 6:8 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + pub fn in_mem_burst_length_ch5(&self) -> IN_MEM_BURST_LENGTH_CH5_R { + IN_MEM_BURST_LENGTH_CH5_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + pub fn in_page_bound_en_ch5(&self) -> IN_PAGE_BOUND_EN_CH5_R { + IN_PAGE_BOUND_EN_CH5_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + pub fn in_rst_ch5(&self) -> IN_RST_CH5_R { + IN_RST_CH5_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + pub fn in_cmd_disable_ch5(&self) -> IN_CMD_DISABLE_CH5_R { + IN_CMD_DISABLE_CH5_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF0_CH5") + .field( + "in_ecc_aes_en_ch5", + &format_args!("{}", self.in_ecc_aes_en_ch5().bit()), + ) + .field( + "in_mem_burst_length_ch5", + &format_args!("{}", self.in_mem_burst_length_ch5().bits()), + ) + .field( + "in_page_bound_en_ch5", + &format_args!("{}", self.in_page_bound_en_ch5().bit()), + ) + .field("in_rst_ch5", &format_args!("{}", self.in_rst_ch5().bit())) + .field( + "in_cmd_disable_ch5", + &format_args!("{}", self.in_cmd_disable_ch5().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + #[must_use] + pub fn in_ecc_aes_en_ch5(&mut self) -> IN_ECC_AES_EN_CH5_W { + IN_ECC_AES_EN_CH5_W::new(self, 3) + } + #[doc = "Bits 6:8 - Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + #[must_use] + pub fn in_mem_burst_length_ch5(&mut self) -> IN_MEM_BURST_LENGTH_CH5_W { + IN_MEM_BURST_LENGTH_CH5_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + #[must_use] + pub fn in_page_bound_en_ch5(&mut self) -> IN_PAGE_BOUND_EN_CH5_W { + IN_PAGE_BOUND_EN_CH5_W::new(self, 12) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset Rx channel"] + #[inline(always)] + #[must_use] + pub fn in_rst_ch5(&mut self) -> IN_RST_CH5_W { + IN_RST_CH5_W::new(self, 24) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + #[must_use] + pub fn in_cmd_disable_ch5(&mut self) -> IN_CMD_DISABLE_CH5_W { + IN_CMD_DISABLE_CH5_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH5 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf0_ch5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf0_ch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF0_CH5_SPEC; +impl crate::RegisterSpec for IN_CONF0_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf0_ch5::R`](R) reader structure"] +impl crate::Readable for IN_CONF0_CH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf0_ch5::W`](W) writer structure"] +impl crate::Writable for IN_CONF0_CH5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF0_CH5 to value 0"] +impl crate::Resettable for IN_CONF0_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_conf1_ch5.rs b/esp32p4/src/h264_dma/in_conf1_ch5.rs new file mode 100644 index 0000000000..2f89563474 --- /dev/null +++ b/esp32p4/src/h264_dma/in_conf1_ch5.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_CONF1_CH5` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF1_CH5` writer"] +pub type W = crate::W; +#[doc = "Field `BLOCK_START_ADDR_CH5` reader - RX Channel 5 destination start address"] +pub type BLOCK_START_ADDR_CH5_R = crate::FieldReader; +#[doc = "Field `BLOCK_START_ADDR_CH5` writer - RX Channel 5 destination start address"] +pub type BLOCK_START_ADDR_CH5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - RX Channel 5 destination start address"] + #[inline(always)] + pub fn block_start_addr_ch5(&self) -> BLOCK_START_ADDR_CH5_R { + BLOCK_START_ADDR_CH5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF1_CH5") + .field( + "block_start_addr_ch5", + &format_args!("{}", self.block_start_addr_ch5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - RX Channel 5 destination start address"] + #[inline(always)] + #[must_use] + pub fn block_start_addr_ch5(&mut self) -> BLOCK_START_ADDR_CH5_W { + BLOCK_START_ADDR_CH5_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH5 config1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf1_ch5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf1_ch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF1_CH5_SPEC; +impl crate::RegisterSpec for IN_CONF1_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf1_ch5::R`](R) reader structure"] +impl crate::Readable for IN_CONF1_CH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf1_ch5::W`](W) writer structure"] +impl crate::Writable for IN_CONF1_CH5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF1_CH5 to value 0"] +impl crate::Resettable for IN_CONF1_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_conf2_ch5.rs b/esp32p4/src/h264_dma/in_conf2_ch5.rs new file mode 100644 index 0000000000..fb30190c02 --- /dev/null +++ b/esp32p4/src/h264_dma/in_conf2_ch5.rs @@ -0,0 +1,89 @@ +#[doc = "Register `IN_CONF2_CH5` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF2_CH5` writer"] +pub type W = crate::W; +#[doc = "Field `BLOCK_ROW_LENGTH_12LINE_CH5` reader - The number of bytes contained in a row block 12line in RX channel 5"] +pub type BLOCK_ROW_LENGTH_12LINE_CH5_R = crate::FieldReader; +#[doc = "Field `BLOCK_ROW_LENGTH_12LINE_CH5` writer - The number of bytes contained in a row block 12line in RX channel 5"] +pub type BLOCK_ROW_LENGTH_12LINE_CH5_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `BLOCK_ROW_LENGTH_4LINE_CH5` reader - The number of bytes contained in a row block 4line in RX channel 5"] +pub type BLOCK_ROW_LENGTH_4LINE_CH5_R = crate::FieldReader; +#[doc = "Field `BLOCK_ROW_LENGTH_4LINE_CH5` writer - The number of bytes contained in a row block 4line in RX channel 5"] +pub type BLOCK_ROW_LENGTH_4LINE_CH5_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - The number of bytes contained in a row block 12line in RX channel 5"] + #[inline(always)] + pub fn block_row_length_12line_ch5(&self) -> BLOCK_ROW_LENGTH_12LINE_CH5_R { + BLOCK_ROW_LENGTH_12LINE_CH5_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - The number of bytes contained in a row block 4line in RX channel 5"] + #[inline(always)] + pub fn block_row_length_4line_ch5(&self) -> BLOCK_ROW_LENGTH_4LINE_CH5_R { + BLOCK_ROW_LENGTH_4LINE_CH5_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF2_CH5") + .field( + "block_row_length_12line_ch5", + &format_args!("{}", self.block_row_length_12line_ch5().bits()), + ) + .field( + "block_row_length_4line_ch5", + &format_args!("{}", self.block_row_length_4line_ch5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - The number of bytes contained in a row block 12line in RX channel 5"] + #[inline(always)] + #[must_use] + pub fn block_row_length_12line_ch5( + &mut self, + ) -> BLOCK_ROW_LENGTH_12LINE_CH5_W { + BLOCK_ROW_LENGTH_12LINE_CH5_W::new(self, 0) + } + #[doc = "Bits 16:31 - The number of bytes contained in a row block 4line in RX channel 5"] + #[inline(always)] + #[must_use] + pub fn block_row_length_4line_ch5( + &mut self, + ) -> BLOCK_ROW_LENGTH_4LINE_CH5_W { + BLOCK_ROW_LENGTH_4LINE_CH5_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH5 config2 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf2_ch5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf2_ch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF2_CH5_SPEC; +impl crate::RegisterSpec for IN_CONF2_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf2_ch5::R`](R) reader structure"] +impl crate::Readable for IN_CONF2_CH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf2_ch5::W`](W) writer structure"] +impl crate::Writable for IN_CONF2_CH5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF2_CH5 to value 0x3c00_7800"] +impl crate::Resettable for IN_CONF2_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0x3c00_7800; +} diff --git a/esp32p4/src/h264_dma/in_conf3_ch5.rs b/esp32p4/src/h264_dma/in_conf3_ch5.rs new file mode 100644 index 0000000000..a3ab229888 --- /dev/null +++ b/esp32p4/src/h264_dma/in_conf3_ch5.rs @@ -0,0 +1,85 @@ +#[doc = "Register `IN_CONF3_CH5` reader"] +pub type R = crate::R; +#[doc = "Register `IN_CONF3_CH5` writer"] +pub type W = crate::W; +#[doc = "Field `BLOCK_LENGTH_12LINE_CH5` reader - The number of bytes contained in a block 12line"] +pub type BLOCK_LENGTH_12LINE_CH5_R = crate::FieldReader; +#[doc = "Field `BLOCK_LENGTH_12LINE_CH5` writer - The number of bytes contained in a block 12line"] +pub type BLOCK_LENGTH_12LINE_CH5_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `BLOCK_LENGTH_4LINE_CH5` reader - The number of bytes contained in a block 4line"] +pub type BLOCK_LENGTH_4LINE_CH5_R = crate::FieldReader; +#[doc = "Field `BLOCK_LENGTH_4LINE_CH5` writer - The number of bytes contained in a block 4line"] +pub type BLOCK_LENGTH_4LINE_CH5_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - The number of bytes contained in a block 12line"] + #[inline(always)] + pub fn block_length_12line_ch5(&self) -> BLOCK_LENGTH_12LINE_CH5_R { + BLOCK_LENGTH_12LINE_CH5_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 14:27 - The number of bytes contained in a block 4line"] + #[inline(always)] + pub fn block_length_4line_ch5(&self) -> BLOCK_LENGTH_4LINE_CH5_R { + BLOCK_LENGTH_4LINE_CH5_R::new(((self.bits >> 14) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_CONF3_CH5") + .field( + "block_length_12line_ch5", + &format_args!("{}", self.block_length_12line_ch5().bits()), + ) + .field( + "block_length_4line_ch5", + &format_args!("{}", self.block_length_4line_ch5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - The number of bytes contained in a block 12line"] + #[inline(always)] + #[must_use] + pub fn block_length_12line_ch5(&mut self) -> BLOCK_LENGTH_12LINE_CH5_W { + BLOCK_LENGTH_12LINE_CH5_W::new(self, 0) + } + #[doc = "Bits 14:27 - The number of bytes contained in a block 4line"] + #[inline(always)] + #[must_use] + pub fn block_length_4line_ch5(&mut self) -> BLOCK_LENGTH_4LINE_CH5_W { + BLOCK_LENGTH_4LINE_CH5_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH5 config3 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_conf3_ch5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_conf3_ch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_CONF3_CH5_SPEC; +impl crate::RegisterSpec for IN_CONF3_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_conf3_ch5::R`](R) reader structure"] +impl crate::Readable for IN_CONF3_CH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_conf3_ch5::W`](W) writer structure"] +impl crate::Writable for IN_CONF3_CH5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_CONF3_CH5 to value 0x0020_0100"] +impl crate::Resettable for IN_CONF3_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0x0020_0100; +} diff --git a/esp32p4/src/h264_dma/in_dscr_bf0_ch0.rs b/esp32p4/src/h264_dma/in_dscr_bf0_ch0.rs new file mode 100644 index 0000000000..f636a36874 --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_bf0_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF0_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF0_CH0` reader - The address of the last inlink descriptor's next address x-1."] +pub type INLINK_DSCR_BF0_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last inlink descriptor's next address x-1."] + #[inline(always)] + pub fn inlink_dscr_bf0_ch0(&self) -> INLINK_DSCR_BF0_CH0_R { + INLINK_DSCR_BF0_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF0_CH0") + .field( + "inlink_dscr_bf0_ch0", + &format_args!("{}", self.inlink_dscr_bf0_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH0 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF0_CH0_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF0_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf0_ch0::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF0_CH0_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF0_CH0 to value 0"] +impl crate::Resettable for IN_DSCR_BF0_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_bf0_ch1.rs b/esp32p4/src/h264_dma/in_dscr_bf0_ch1.rs new file mode 100644 index 0000000000..2863ace857 --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_bf0_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF0_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF0_CH1` reader - The address of the last inlink descriptor's next address x-1."] +pub type INLINK_DSCR_BF0_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last inlink descriptor's next address x-1."] + #[inline(always)] + pub fn inlink_dscr_bf0_ch1(&self) -> INLINK_DSCR_BF0_CH1_R { + INLINK_DSCR_BF0_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF0_CH1") + .field( + "inlink_dscr_bf0_ch1", + &format_args!("{}", self.inlink_dscr_bf0_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH1 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF0_CH1_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF0_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf0_ch1::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF0_CH1_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF0_CH1 to value 0"] +impl crate::Resettable for IN_DSCR_BF0_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_bf0_ch2.rs b/esp32p4/src/h264_dma/in_dscr_bf0_ch2.rs new file mode 100644 index 0000000000..ef8bb54fdc --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_bf0_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF0_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF0_CH2` reader - The address of the last inlink descriptor's next address x-1."] +pub type INLINK_DSCR_BF0_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last inlink descriptor's next address x-1."] + #[inline(always)] + pub fn inlink_dscr_bf0_ch2(&self) -> INLINK_DSCR_BF0_CH2_R { + INLINK_DSCR_BF0_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF0_CH2") + .field( + "inlink_dscr_bf0_ch2", + &format_args!("{}", self.inlink_dscr_bf0_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH2 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF0_CH2_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF0_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf0_ch2::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF0_CH2_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF0_CH2 to value 0"] +impl crate::Resettable for IN_DSCR_BF0_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_bf0_ch3.rs b/esp32p4/src/h264_dma/in_dscr_bf0_ch3.rs new file mode 100644 index 0000000000..dc35344c21 --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_bf0_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF0_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF0_CH3` reader - The address of the last inlink descriptor's next address x-1."] +pub type INLINK_DSCR_BF0_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last inlink descriptor's next address x-1."] + #[inline(always)] + pub fn inlink_dscr_bf0_ch3(&self) -> INLINK_DSCR_BF0_CH3_R { + INLINK_DSCR_BF0_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF0_CH3") + .field( + "inlink_dscr_bf0_ch3", + &format_args!("{}", self.inlink_dscr_bf0_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH3 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF0_CH3_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF0_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf0_ch3::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF0_CH3_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF0_CH3 to value 0"] +impl crate::Resettable for IN_DSCR_BF0_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_bf0_ch4.rs b/esp32p4/src/h264_dma/in_dscr_bf0_ch4.rs new file mode 100644 index 0000000000..1c4f050a2e --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_bf0_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF0_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF0_CH4` reader - The address of the last inlink descriptor's next address x-1."] +pub type INLINK_DSCR_BF0_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last inlink descriptor's next address x-1."] + #[inline(always)] + pub fn inlink_dscr_bf0_ch4(&self) -> INLINK_DSCR_BF0_CH4_R { + INLINK_DSCR_BF0_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF0_CH4") + .field( + "inlink_dscr_bf0_ch4", + &format_args!("{}", self.inlink_dscr_bf0_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH4 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF0_CH4_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF0_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf0_ch4::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF0_CH4_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF0_CH4 to value 0"] +impl crate::Resettable for IN_DSCR_BF0_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_bf1_ch0.rs b/esp32p4/src/h264_dma/in_dscr_bf1_ch0.rs new file mode 100644 index 0000000000..b6e3c8d3b0 --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_bf1_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF1_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF1_CH0` reader - The address of the second-to-last inlink descriptor's next address x-2."] +pub type INLINK_DSCR_BF1_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor's next address x-2."] + #[inline(always)] + pub fn inlink_dscr_bf1_ch0(&self) -> INLINK_DSCR_BF1_CH0_R { + INLINK_DSCR_BF1_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF1_CH0") + .field( + "inlink_dscr_bf1_ch0", + &format_args!("{}", self.inlink_dscr_bf1_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH0 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF1_CH0_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF1_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf1_ch0::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF1_CH0_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF1_CH0 to value 0"] +impl crate::Resettable for IN_DSCR_BF1_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_bf1_ch1.rs b/esp32p4/src/h264_dma/in_dscr_bf1_ch1.rs new file mode 100644 index 0000000000..b85689a831 --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_bf1_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF1_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF1_CH1` reader - The address of the second-to-last inlink descriptor's next address x-2."] +pub type INLINK_DSCR_BF1_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor's next address x-2."] + #[inline(always)] + pub fn inlink_dscr_bf1_ch1(&self) -> INLINK_DSCR_BF1_CH1_R { + INLINK_DSCR_BF1_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF1_CH1") + .field( + "inlink_dscr_bf1_ch1", + &format_args!("{}", self.inlink_dscr_bf1_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH1 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF1_CH1_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF1_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf1_ch1::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF1_CH1_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF1_CH1 to value 0"] +impl crate::Resettable for IN_DSCR_BF1_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_bf1_ch2.rs b/esp32p4/src/h264_dma/in_dscr_bf1_ch2.rs new file mode 100644 index 0000000000..87ac4a6961 --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_bf1_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF1_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF1_CH2` reader - The address of the second-to-last inlink descriptor's next address x-2."] +pub type INLINK_DSCR_BF1_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor's next address x-2."] + #[inline(always)] + pub fn inlink_dscr_bf1_ch2(&self) -> INLINK_DSCR_BF1_CH2_R { + INLINK_DSCR_BF1_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF1_CH2") + .field( + "inlink_dscr_bf1_ch2", + &format_args!("{}", self.inlink_dscr_bf1_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH2 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF1_CH2_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF1_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf1_ch2::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF1_CH2_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF1_CH2 to value 0"] +impl crate::Resettable for IN_DSCR_BF1_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_bf1_ch3.rs b/esp32p4/src/h264_dma/in_dscr_bf1_ch3.rs new file mode 100644 index 0000000000..09a4e44927 --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_bf1_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF1_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF1_CH3` reader - The address of the second-to-last inlink descriptor's next address x-2."] +pub type INLINK_DSCR_BF1_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor's next address x-2."] + #[inline(always)] + pub fn inlink_dscr_bf1_ch3(&self) -> INLINK_DSCR_BF1_CH3_R { + INLINK_DSCR_BF1_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF1_CH3") + .field( + "inlink_dscr_bf1_ch3", + &format_args!("{}", self.inlink_dscr_bf1_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH3 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF1_CH3_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF1_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf1_ch3::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF1_CH3_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF1_CH3 to value 0"] +impl crate::Resettable for IN_DSCR_BF1_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_bf1_ch4.rs b/esp32p4/src/h264_dma/in_dscr_bf1_ch4.rs new file mode 100644 index 0000000000..423629cccf --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_bf1_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_BF1_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_BF1_CH4` reader - The address of the second-to-last inlink descriptor's next address x-2."] +pub type INLINK_DSCR_BF1_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor's next address x-2."] + #[inline(always)] + pub fn inlink_dscr_bf1_ch4(&self) -> INLINK_DSCR_BF1_CH4_R { + INLINK_DSCR_BF1_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_BF1_CH4") + .field( + "inlink_dscr_bf1_ch4", + &format_args!("{}", self.inlink_dscr_bf1_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH4 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_BF1_CH4_SPEC; +impl crate::RegisterSpec for IN_DSCR_BF1_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_bf1_ch4::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_BF1_CH4_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_BF1_CH4 to value 0"] +impl crate::Resettable for IN_DSCR_BF1_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_ch0.rs b/esp32p4/src/h264_dma/in_dscr_ch0.rs new file mode 100644 index 0000000000..fbcf032c53 --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_CH0` reader - The address of the next inlink descriptor address x."] +pub type INLINK_DSCR_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the next inlink descriptor address x."] + #[inline(always)] + pub fn inlink_dscr_ch0(&self) -> INLINK_DSCR_CH0_R { + INLINK_DSCR_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_CH0") + .field( + "inlink_dscr_ch0", + &format_args!("{}", self.inlink_dscr_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH0 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_CH0_SPEC; +impl crate::RegisterSpec for IN_DSCR_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_ch0::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_CH0_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_CH0 to value 0"] +impl crate::Resettable for IN_DSCR_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_ch1.rs b/esp32p4/src/h264_dma/in_dscr_ch1.rs new file mode 100644 index 0000000000..83484ab0c9 --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_CH1` reader - The address of the next inlink descriptor address x."] +pub type INLINK_DSCR_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the next inlink descriptor address x."] + #[inline(always)] + pub fn inlink_dscr_ch1(&self) -> INLINK_DSCR_CH1_R { + INLINK_DSCR_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_CH1") + .field( + "inlink_dscr_ch1", + &format_args!("{}", self.inlink_dscr_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH1 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_CH1_SPEC; +impl crate::RegisterSpec for IN_DSCR_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_ch1::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_CH1_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_CH1 to value 0"] +impl crate::Resettable for IN_DSCR_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_ch2.rs b/esp32p4/src/h264_dma/in_dscr_ch2.rs new file mode 100644 index 0000000000..506073022e --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_CH2` reader - The address of the next inlink descriptor address x."] +pub type INLINK_DSCR_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the next inlink descriptor address x."] + #[inline(always)] + pub fn inlink_dscr_ch2(&self) -> INLINK_DSCR_CH2_R { + INLINK_DSCR_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_CH2") + .field( + "inlink_dscr_ch2", + &format_args!("{}", self.inlink_dscr_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH2 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_CH2_SPEC; +impl crate::RegisterSpec for IN_DSCR_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_ch2::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_CH2_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_CH2 to value 0"] +impl crate::Resettable for IN_DSCR_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_ch3.rs b/esp32p4/src/h264_dma/in_dscr_ch3.rs new file mode 100644 index 0000000000..0cf0c64176 --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_CH3` reader - The address of the next inlink descriptor address x."] +pub type INLINK_DSCR_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the next inlink descriptor address x."] + #[inline(always)] + pub fn inlink_dscr_ch3(&self) -> INLINK_DSCR_CH3_R { + INLINK_DSCR_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_CH3") + .field( + "inlink_dscr_ch3", + &format_args!("{}", self.inlink_dscr_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH3 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_CH3_SPEC; +impl crate::RegisterSpec for IN_DSCR_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_ch3::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_CH3_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_CH3 to value 0"] +impl crate::Resettable for IN_DSCR_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_dscr_ch4.rs b/esp32p4/src/h264_dma/in_dscr_ch4.rs new file mode 100644 index 0000000000..0cbd21ddbd --- /dev/null +++ b/esp32p4/src/h264_dma/in_dscr_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_DSCR_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_CH4` reader - The address of the next inlink descriptor address x."] +pub type INLINK_DSCR_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the next inlink descriptor address x."] + #[inline(always)] + pub fn inlink_dscr_ch4(&self) -> INLINK_DSCR_CH4_R { + INLINK_DSCR_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_DSCR_CH4") + .field( + "inlink_dscr_ch4", + &format_args!("{}", self.inlink_dscr_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH4 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_DSCR_CH4_SPEC; +impl crate::RegisterSpec for IN_DSCR_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_dscr_ch4::R`](R) reader structure"] +impl crate::Readable for IN_DSCR_CH4_SPEC {} +#[doc = "`reset()` method sets IN_DSCR_CH4 to value 0"] +impl crate::Resettable for IN_DSCR_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_err_eof_des_addr_ch0.rs b/esp32p4/src/h264_dma/in_err_eof_des_addr_ch0.rs new file mode 100644 index 0000000000..d9bfbebd71 --- /dev/null +++ b/esp32p4/src/h264_dma/in_err_eof_des_addr_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_ERR_EOF_DES_ADDR_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH0` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data."] +pub type IN_ERR_EOF_DES_ADDR_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data."] + #[inline(always)] + pub fn in_err_eof_des_addr_ch0(&self) -> IN_ERR_EOF_DES_ADDR_CH0_R { + IN_ERR_EOF_DES_ADDR_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ERR_EOF_DES_ADDR_CH0") + .field( + "in_err_eof_des_addr_ch0", + &format_args!("{}", self.in_err_eof_des_addr_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH0 err eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ERR_EOF_DES_ADDR_CH0_SPEC; +impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_err_eof_des_addr_ch0::R`](R) reader structure"] +impl crate::Readable for IN_ERR_EOF_DES_ADDR_CH0_SPEC {} +#[doc = "`reset()` method sets IN_ERR_EOF_DES_ADDR_CH0 to value 0"] +impl crate::Resettable for IN_ERR_EOF_DES_ADDR_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_err_eof_des_addr_ch1.rs b/esp32p4/src/h264_dma/in_err_eof_des_addr_ch1.rs new file mode 100644 index 0000000000..03bf569dd8 --- /dev/null +++ b/esp32p4/src/h264_dma/in_err_eof_des_addr_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_ERR_EOF_DES_ADDR_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH1` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data."] +pub type IN_ERR_EOF_DES_ADDR_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data."] + #[inline(always)] + pub fn in_err_eof_des_addr_ch1(&self) -> IN_ERR_EOF_DES_ADDR_CH1_R { + IN_ERR_EOF_DES_ADDR_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ERR_EOF_DES_ADDR_CH1") + .field( + "in_err_eof_des_addr_ch1", + &format_args!("{}", self.in_err_eof_des_addr_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH1 err eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ERR_EOF_DES_ADDR_CH1_SPEC; +impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_err_eof_des_addr_ch1::R`](R) reader structure"] +impl crate::Readable for IN_ERR_EOF_DES_ADDR_CH1_SPEC {} +#[doc = "`reset()` method sets IN_ERR_EOF_DES_ADDR_CH1 to value 0"] +impl crate::Resettable for IN_ERR_EOF_DES_ADDR_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_err_eof_des_addr_ch2.rs b/esp32p4/src/h264_dma/in_err_eof_des_addr_ch2.rs new file mode 100644 index 0000000000..0df6c07f43 --- /dev/null +++ b/esp32p4/src/h264_dma/in_err_eof_des_addr_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_ERR_EOF_DES_ADDR_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH2` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data."] +pub type IN_ERR_EOF_DES_ADDR_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data."] + #[inline(always)] + pub fn in_err_eof_des_addr_ch2(&self) -> IN_ERR_EOF_DES_ADDR_CH2_R { + IN_ERR_EOF_DES_ADDR_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ERR_EOF_DES_ADDR_CH2") + .field( + "in_err_eof_des_addr_ch2", + &format_args!("{}", self.in_err_eof_des_addr_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH2 err eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ERR_EOF_DES_ADDR_CH2_SPEC; +impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_err_eof_des_addr_ch2::R`](R) reader structure"] +impl crate::Readable for IN_ERR_EOF_DES_ADDR_CH2_SPEC {} +#[doc = "`reset()` method sets IN_ERR_EOF_DES_ADDR_CH2 to value 0"] +impl crate::Resettable for IN_ERR_EOF_DES_ADDR_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_err_eof_des_addr_ch3.rs b/esp32p4/src/h264_dma/in_err_eof_des_addr_ch3.rs new file mode 100644 index 0000000000..3c99f8ac76 --- /dev/null +++ b/esp32p4/src/h264_dma/in_err_eof_des_addr_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_ERR_EOF_DES_ADDR_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH3` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data."] +pub type IN_ERR_EOF_DES_ADDR_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data."] + #[inline(always)] + pub fn in_err_eof_des_addr_ch3(&self) -> IN_ERR_EOF_DES_ADDR_CH3_R { + IN_ERR_EOF_DES_ADDR_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ERR_EOF_DES_ADDR_CH3") + .field( + "in_err_eof_des_addr_ch3", + &format_args!("{}", self.in_err_eof_des_addr_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH3 err eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ERR_EOF_DES_ADDR_CH3_SPEC; +impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_err_eof_des_addr_ch3::R`](R) reader structure"] +impl crate::Readable for IN_ERR_EOF_DES_ADDR_CH3_SPEC {} +#[doc = "`reset()` method sets IN_ERR_EOF_DES_ADDR_CH3 to value 0"] +impl crate::Resettable for IN_ERR_EOF_DES_ADDR_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_err_eof_des_addr_ch4.rs b/esp32p4/src/h264_dma/in_err_eof_des_addr_ch4.rs new file mode 100644 index 0000000000..f15d27dae3 --- /dev/null +++ b/esp32p4/src/h264_dma/in_err_eof_des_addr_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_ERR_EOF_DES_ADDR_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `IN_ERR_EOF_DES_ADDR_CH4` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data."] +pub type IN_ERR_EOF_DES_ADDR_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data."] + #[inline(always)] + pub fn in_err_eof_des_addr_ch4(&self) -> IN_ERR_EOF_DES_ADDR_CH4_R { + IN_ERR_EOF_DES_ADDR_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ERR_EOF_DES_ADDR_CH4") + .field( + "in_err_eof_des_addr_ch4", + &format_args!("{}", self.in_err_eof_des_addr_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH4 err eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ERR_EOF_DES_ADDR_CH4_SPEC; +impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_err_eof_des_addr_ch4::R`](R) reader structure"] +impl crate::Readable for IN_ERR_EOF_DES_ADDR_CH4_SPEC {} +#[doc = "`reset()` method sets IN_ERR_EOF_DES_ADDR_CH4 to value 0"] +impl crate::Resettable for IN_ERR_EOF_DES_ADDR_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_etm_conf_ch0.rs b/esp32p4/src/h264_dma/in_etm_conf_ch0.rs new file mode 100644 index 0000000000..97b429f0ab --- /dev/null +++ b/esp32p4/src/h264_dma/in_etm_conf_ch0.rs @@ -0,0 +1,104 @@ +#[doc = "Register `IN_ETM_CONF_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ETM_CONF_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ETM_EN_CH0` reader - Set this bit to 1 to enable ETM task function"] +pub type IN_ETM_EN_CH0_R = crate::BitReader; +#[doc = "Field `IN_ETM_EN_CH0` writer - Set this bit to 1 to enable ETM task function"] +pub type IN_ETM_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ETM_LOOP_EN_CH0` reader - when this bit is 1, dscr can be processed after receiving a task"] +pub type IN_ETM_LOOP_EN_CH0_R = crate::BitReader; +#[doc = "Field `IN_ETM_LOOP_EN_CH0` writer - when this bit is 1, dscr can be processed after receiving a task"] +pub type IN_ETM_LOOP_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_MAK_CH0` reader - ETM dscr_ready maximum cache numbers"] +pub type IN_DSCR_TASK_MAK_CH0_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_TASK_MAK_CH0` writer - ETM dscr_ready maximum cache numbers"] +pub type IN_DSCR_TASK_MAK_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + pub fn in_etm_en_ch0(&self) -> IN_ETM_EN_CH0_R { + IN_ETM_EN_CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + pub fn in_etm_loop_en_ch0(&self) -> IN_ETM_LOOP_EN_CH0_R { + IN_ETM_LOOP_EN_CH0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + pub fn in_dscr_task_mak_ch0(&self) -> IN_DSCR_TASK_MAK_CH0_R { + IN_DSCR_TASK_MAK_CH0_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ETM_CONF_CH0") + .field( + "in_etm_en_ch0", + &format_args!("{}", self.in_etm_en_ch0().bit()), + ) + .field( + "in_etm_loop_en_ch0", + &format_args!("{}", self.in_etm_loop_en_ch0().bit()), + ) + .field( + "in_dscr_task_mak_ch0", + &format_args!("{}", self.in_dscr_task_mak_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + #[must_use] + pub fn in_etm_en_ch0(&mut self) -> IN_ETM_EN_CH0_W { + IN_ETM_EN_CH0_W::new(self, 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + #[must_use] + pub fn in_etm_loop_en_ch0(&mut self) -> IN_ETM_LOOP_EN_CH0_W { + IN_ETM_LOOP_EN_CH0_W::new(self, 1) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_mak_ch0(&mut self) -> IN_DSCR_TASK_MAK_CH0_W { + IN_DSCR_TASK_MAK_CH0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH0 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_etm_conf_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_etm_conf_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ETM_CONF_CH0_SPEC; +impl crate::RegisterSpec for IN_ETM_CONF_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_etm_conf_ch0::R`](R) reader structure"] +impl crate::Readable for IN_ETM_CONF_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_etm_conf_ch0::W`](W) writer structure"] +impl crate::Writable for IN_ETM_CONF_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ETM_CONF_CH0 to value 0x04"] +impl crate::Resettable for IN_ETM_CONF_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/h264_dma/in_etm_conf_ch1.rs b/esp32p4/src/h264_dma/in_etm_conf_ch1.rs new file mode 100644 index 0000000000..1affcbb065 --- /dev/null +++ b/esp32p4/src/h264_dma/in_etm_conf_ch1.rs @@ -0,0 +1,104 @@ +#[doc = "Register `IN_ETM_CONF_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ETM_CONF_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ETM_EN_CH1` reader - Set this bit to 1 to enable ETM task function"] +pub type IN_ETM_EN_CH1_R = crate::BitReader; +#[doc = "Field `IN_ETM_EN_CH1` writer - Set this bit to 1 to enable ETM task function"] +pub type IN_ETM_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ETM_LOOP_EN_CH1` reader - when this bit is 1, dscr can be processed after receiving a task"] +pub type IN_ETM_LOOP_EN_CH1_R = crate::BitReader; +#[doc = "Field `IN_ETM_LOOP_EN_CH1` writer - when this bit is 1, dscr can be processed after receiving a task"] +pub type IN_ETM_LOOP_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_MAK_CH1` reader - ETM dscr_ready maximum cache numbers"] +pub type IN_DSCR_TASK_MAK_CH1_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_TASK_MAK_CH1` writer - ETM dscr_ready maximum cache numbers"] +pub type IN_DSCR_TASK_MAK_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + pub fn in_etm_en_ch1(&self) -> IN_ETM_EN_CH1_R { + IN_ETM_EN_CH1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + pub fn in_etm_loop_en_ch1(&self) -> IN_ETM_LOOP_EN_CH1_R { + IN_ETM_LOOP_EN_CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + pub fn in_dscr_task_mak_ch1(&self) -> IN_DSCR_TASK_MAK_CH1_R { + IN_DSCR_TASK_MAK_CH1_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ETM_CONF_CH1") + .field( + "in_etm_en_ch1", + &format_args!("{}", self.in_etm_en_ch1().bit()), + ) + .field( + "in_etm_loop_en_ch1", + &format_args!("{}", self.in_etm_loop_en_ch1().bit()), + ) + .field( + "in_dscr_task_mak_ch1", + &format_args!("{}", self.in_dscr_task_mak_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + #[must_use] + pub fn in_etm_en_ch1(&mut self) -> IN_ETM_EN_CH1_W { + IN_ETM_EN_CH1_W::new(self, 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + #[must_use] + pub fn in_etm_loop_en_ch1(&mut self) -> IN_ETM_LOOP_EN_CH1_W { + IN_ETM_LOOP_EN_CH1_W::new(self, 1) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_mak_ch1(&mut self) -> IN_DSCR_TASK_MAK_CH1_W { + IN_DSCR_TASK_MAK_CH1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH1 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_etm_conf_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_etm_conf_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ETM_CONF_CH1_SPEC; +impl crate::RegisterSpec for IN_ETM_CONF_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_etm_conf_ch1::R`](R) reader structure"] +impl crate::Readable for IN_ETM_CONF_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_etm_conf_ch1::W`](W) writer structure"] +impl crate::Writable for IN_ETM_CONF_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ETM_CONF_CH1 to value 0x04"] +impl crate::Resettable for IN_ETM_CONF_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/h264_dma/in_etm_conf_ch2.rs b/esp32p4/src/h264_dma/in_etm_conf_ch2.rs new file mode 100644 index 0000000000..b56b685fa7 --- /dev/null +++ b/esp32p4/src/h264_dma/in_etm_conf_ch2.rs @@ -0,0 +1,104 @@ +#[doc = "Register `IN_ETM_CONF_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ETM_CONF_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ETM_EN_CH2` reader - Set this bit to 1 to enable ETM task function"] +pub type IN_ETM_EN_CH2_R = crate::BitReader; +#[doc = "Field `IN_ETM_EN_CH2` writer - Set this bit to 1 to enable ETM task function"] +pub type IN_ETM_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ETM_LOOP_EN_CH2` reader - when this bit is 1, dscr can be processed after receiving a task"] +pub type IN_ETM_LOOP_EN_CH2_R = crate::BitReader; +#[doc = "Field `IN_ETM_LOOP_EN_CH2` writer - when this bit is 1, dscr can be processed after receiving a task"] +pub type IN_ETM_LOOP_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_MAK_CH2` reader - ETM dscr_ready maximum cache numbers"] +pub type IN_DSCR_TASK_MAK_CH2_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_TASK_MAK_CH2` writer - ETM dscr_ready maximum cache numbers"] +pub type IN_DSCR_TASK_MAK_CH2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + pub fn in_etm_en_ch2(&self) -> IN_ETM_EN_CH2_R { + IN_ETM_EN_CH2_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + pub fn in_etm_loop_en_ch2(&self) -> IN_ETM_LOOP_EN_CH2_R { + IN_ETM_LOOP_EN_CH2_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + pub fn in_dscr_task_mak_ch2(&self) -> IN_DSCR_TASK_MAK_CH2_R { + IN_DSCR_TASK_MAK_CH2_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ETM_CONF_CH2") + .field( + "in_etm_en_ch2", + &format_args!("{}", self.in_etm_en_ch2().bit()), + ) + .field( + "in_etm_loop_en_ch2", + &format_args!("{}", self.in_etm_loop_en_ch2().bit()), + ) + .field( + "in_dscr_task_mak_ch2", + &format_args!("{}", self.in_dscr_task_mak_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + #[must_use] + pub fn in_etm_en_ch2(&mut self) -> IN_ETM_EN_CH2_W { + IN_ETM_EN_CH2_W::new(self, 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + #[must_use] + pub fn in_etm_loop_en_ch2(&mut self) -> IN_ETM_LOOP_EN_CH2_W { + IN_ETM_LOOP_EN_CH2_W::new(self, 1) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_mak_ch2(&mut self) -> IN_DSCR_TASK_MAK_CH2_W { + IN_DSCR_TASK_MAK_CH2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH2 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_etm_conf_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_etm_conf_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ETM_CONF_CH2_SPEC; +impl crate::RegisterSpec for IN_ETM_CONF_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_etm_conf_ch2::R`](R) reader structure"] +impl crate::Readable for IN_ETM_CONF_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_etm_conf_ch2::W`](W) writer structure"] +impl crate::Writable for IN_ETM_CONF_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ETM_CONF_CH2 to value 0x04"] +impl crate::Resettable for IN_ETM_CONF_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/h264_dma/in_etm_conf_ch3.rs b/esp32p4/src/h264_dma/in_etm_conf_ch3.rs new file mode 100644 index 0000000000..2f5f3bec66 --- /dev/null +++ b/esp32p4/src/h264_dma/in_etm_conf_ch3.rs @@ -0,0 +1,104 @@ +#[doc = "Register `IN_ETM_CONF_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ETM_CONF_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ETM_EN_CH3` reader - Set this bit to 1 to enable ETM task function"] +pub type IN_ETM_EN_CH3_R = crate::BitReader; +#[doc = "Field `IN_ETM_EN_CH3` writer - Set this bit to 1 to enable ETM task function"] +pub type IN_ETM_EN_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ETM_LOOP_EN_CH3` reader - when this bit is 1, dscr can be processed after receiving a task"] +pub type IN_ETM_LOOP_EN_CH3_R = crate::BitReader; +#[doc = "Field `IN_ETM_LOOP_EN_CH3` writer - when this bit is 1, dscr can be processed after receiving a task"] +pub type IN_ETM_LOOP_EN_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_MAK_CH3` reader - ETM dscr_ready maximum cache numbers"] +pub type IN_DSCR_TASK_MAK_CH3_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_TASK_MAK_CH3` writer - ETM dscr_ready maximum cache numbers"] +pub type IN_DSCR_TASK_MAK_CH3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + pub fn in_etm_en_ch3(&self) -> IN_ETM_EN_CH3_R { + IN_ETM_EN_CH3_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + pub fn in_etm_loop_en_ch3(&self) -> IN_ETM_LOOP_EN_CH3_R { + IN_ETM_LOOP_EN_CH3_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + pub fn in_dscr_task_mak_ch3(&self) -> IN_DSCR_TASK_MAK_CH3_R { + IN_DSCR_TASK_MAK_CH3_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ETM_CONF_CH3") + .field( + "in_etm_en_ch3", + &format_args!("{}", self.in_etm_en_ch3().bit()), + ) + .field( + "in_etm_loop_en_ch3", + &format_args!("{}", self.in_etm_loop_en_ch3().bit()), + ) + .field( + "in_dscr_task_mak_ch3", + &format_args!("{}", self.in_dscr_task_mak_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + #[must_use] + pub fn in_etm_en_ch3(&mut self) -> IN_ETM_EN_CH3_W { + IN_ETM_EN_CH3_W::new(self, 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + #[must_use] + pub fn in_etm_loop_en_ch3(&mut self) -> IN_ETM_LOOP_EN_CH3_W { + IN_ETM_LOOP_EN_CH3_W::new(self, 1) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_mak_ch3(&mut self) -> IN_DSCR_TASK_MAK_CH3_W { + IN_DSCR_TASK_MAK_CH3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH3 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_etm_conf_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_etm_conf_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ETM_CONF_CH3_SPEC; +impl crate::RegisterSpec for IN_ETM_CONF_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_etm_conf_ch3::R`](R) reader structure"] +impl crate::Readable for IN_ETM_CONF_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_etm_conf_ch3::W`](W) writer structure"] +impl crate::Writable for IN_ETM_CONF_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ETM_CONF_CH3 to value 0x04"] +impl crate::Resettable for IN_ETM_CONF_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/h264_dma/in_etm_conf_ch4.rs b/esp32p4/src/h264_dma/in_etm_conf_ch4.rs new file mode 100644 index 0000000000..d2f74658b6 --- /dev/null +++ b/esp32p4/src/h264_dma/in_etm_conf_ch4.rs @@ -0,0 +1,104 @@ +#[doc = "Register `IN_ETM_CONF_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `IN_ETM_CONF_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `IN_ETM_EN_CH4` reader - Set this bit to 1 to enable ETM task function"] +pub type IN_ETM_EN_CH4_R = crate::BitReader; +#[doc = "Field `IN_ETM_EN_CH4` writer - Set this bit to 1 to enable ETM task function"] +pub type IN_ETM_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ETM_LOOP_EN_CH4` reader - when this bit is 1, dscr can be processed after receiving a task"] +pub type IN_ETM_LOOP_EN_CH4_R = crate::BitReader; +#[doc = "Field `IN_ETM_LOOP_EN_CH4` writer - when this bit is 1, dscr can be processed after receiving a task"] +pub type IN_ETM_LOOP_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_MAK_CH4` reader - ETM dscr_ready maximum cache numbers"] +pub type IN_DSCR_TASK_MAK_CH4_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_TASK_MAK_CH4` writer - ETM dscr_ready maximum cache numbers"] +pub type IN_DSCR_TASK_MAK_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + pub fn in_etm_en_ch4(&self) -> IN_ETM_EN_CH4_R { + IN_ETM_EN_CH4_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + pub fn in_etm_loop_en_ch4(&self) -> IN_ETM_LOOP_EN_CH4_R { + IN_ETM_LOOP_EN_CH4_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + pub fn in_dscr_task_mak_ch4(&self) -> IN_DSCR_TASK_MAK_CH4_R { + IN_DSCR_TASK_MAK_CH4_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_ETM_CONF_CH4") + .field( + "in_etm_en_ch4", + &format_args!("{}", self.in_etm_en_ch4().bit()), + ) + .field( + "in_etm_loop_en_ch4", + &format_args!("{}", self.in_etm_loop_en_ch4().bit()), + ) + .field( + "in_dscr_task_mak_ch4", + &format_args!("{}", self.in_dscr_task_mak_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + #[must_use] + pub fn in_etm_en_ch4(&mut self) -> IN_ETM_EN_CH4_W { + IN_ETM_EN_CH4_W::new(self, 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + #[must_use] + pub fn in_etm_loop_en_ch4(&mut self) -> IN_ETM_LOOP_EN_CH4_W { + IN_ETM_LOOP_EN_CH4_W::new(self, 1) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_mak_ch4(&mut self) -> IN_DSCR_TASK_MAK_CH4_W { + IN_DSCR_TASK_MAK_CH4_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH4 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_etm_conf_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_etm_conf_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_ETM_CONF_CH4_SPEC; +impl crate::RegisterSpec for IN_ETM_CONF_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_etm_conf_ch4::R`](R) reader structure"] +impl crate::Readable for IN_ETM_CONF_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_etm_conf_ch4::W`](W) writer structure"] +impl crate::Writable for IN_ETM_CONF_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_ETM_CONF_CH4 to value 0x04"] +impl crate::Resettable for IN_ETM_CONF_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/h264_dma/in_fifo_cnt_ch0.rs b/esp32p4/src/h264_dma/in_fifo_cnt_ch0.rs new file mode 100644 index 0000000000..5a561badcc --- /dev/null +++ b/esp32p4/src/h264_dma/in_fifo_cnt_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_FIFO_CNT_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_INFIFO_CNT_CH0` reader - only for debug"] +pub type IN_CMDFIFO_INFIFO_CNT_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_infifo_cnt_ch0(&self) -> IN_CMDFIFO_INFIFO_CNT_CH0_R { + IN_CMDFIFO_INFIFO_CNT_CH0_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_FIFO_CNT_CH0") + .field( + "in_cmdfifo_infifo_cnt_ch0", + &format_args!("{}", self.in_cmdfifo_infifo_cnt_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH0 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_FIFO_CNT_CH0_SPEC; +impl crate::RegisterSpec for IN_FIFO_CNT_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_fifo_cnt_ch0::R`](R) reader structure"] +impl crate::Readable for IN_FIFO_CNT_CH0_SPEC {} +#[doc = "`reset()` method sets IN_FIFO_CNT_CH0 to value 0"] +impl crate::Resettable for IN_FIFO_CNT_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_fifo_cnt_ch1.rs b/esp32p4/src/h264_dma/in_fifo_cnt_ch1.rs new file mode 100644 index 0000000000..ff497977fc --- /dev/null +++ b/esp32p4/src/h264_dma/in_fifo_cnt_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_FIFO_CNT_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_INFIFO_CNT_CH1` reader - only for debug"] +pub type IN_CMDFIFO_INFIFO_CNT_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_infifo_cnt_ch1(&self) -> IN_CMDFIFO_INFIFO_CNT_CH1_R { + IN_CMDFIFO_INFIFO_CNT_CH1_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_FIFO_CNT_CH1") + .field( + "in_cmdfifo_infifo_cnt_ch1", + &format_args!("{}", self.in_cmdfifo_infifo_cnt_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH1 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_FIFO_CNT_CH1_SPEC; +impl crate::RegisterSpec for IN_FIFO_CNT_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_fifo_cnt_ch1::R`](R) reader structure"] +impl crate::Readable for IN_FIFO_CNT_CH1_SPEC {} +#[doc = "`reset()` method sets IN_FIFO_CNT_CH1 to value 0"] +impl crate::Resettable for IN_FIFO_CNT_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_fifo_cnt_ch2.rs b/esp32p4/src/h264_dma/in_fifo_cnt_ch2.rs new file mode 100644 index 0000000000..d67ea0ca7e --- /dev/null +++ b/esp32p4/src/h264_dma/in_fifo_cnt_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_FIFO_CNT_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_INFIFO_CNT_CH2` reader - only for debug"] +pub type IN_CMDFIFO_INFIFO_CNT_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_infifo_cnt_ch2(&self) -> IN_CMDFIFO_INFIFO_CNT_CH2_R { + IN_CMDFIFO_INFIFO_CNT_CH2_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_FIFO_CNT_CH2") + .field( + "in_cmdfifo_infifo_cnt_ch2", + &format_args!("{}", self.in_cmdfifo_infifo_cnt_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH2 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_FIFO_CNT_CH2_SPEC; +impl crate::RegisterSpec for IN_FIFO_CNT_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_fifo_cnt_ch2::R`](R) reader structure"] +impl crate::Readable for IN_FIFO_CNT_CH2_SPEC {} +#[doc = "`reset()` method sets IN_FIFO_CNT_CH2 to value 0"] +impl crate::Resettable for IN_FIFO_CNT_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_fifo_cnt_ch3.rs b/esp32p4/src/h264_dma/in_fifo_cnt_ch3.rs new file mode 100644 index 0000000000..3e19b47c14 --- /dev/null +++ b/esp32p4/src/h264_dma/in_fifo_cnt_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_FIFO_CNT_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_INFIFO_CNT_CH3` reader - only for debug"] +pub type IN_CMDFIFO_INFIFO_CNT_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_infifo_cnt_ch3(&self) -> IN_CMDFIFO_INFIFO_CNT_CH3_R { + IN_CMDFIFO_INFIFO_CNT_CH3_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_FIFO_CNT_CH3") + .field( + "in_cmdfifo_infifo_cnt_ch3", + &format_args!("{}", self.in_cmdfifo_infifo_cnt_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH3 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_FIFO_CNT_CH3_SPEC; +impl crate::RegisterSpec for IN_FIFO_CNT_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_fifo_cnt_ch3::R`](R) reader structure"] +impl crate::Readable for IN_FIFO_CNT_CH3_SPEC {} +#[doc = "`reset()` method sets IN_FIFO_CNT_CH3 to value 0"] +impl crate::Resettable for IN_FIFO_CNT_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_fifo_cnt_ch4.rs b/esp32p4/src/h264_dma/in_fifo_cnt_ch4.rs new file mode 100644 index 0000000000..0d9bf494d1 --- /dev/null +++ b/esp32p4/src/h264_dma/in_fifo_cnt_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_FIFO_CNT_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_INFIFO_CNT_CH4` reader - only for debug"] +pub type IN_CMDFIFO_INFIFO_CNT_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_infifo_cnt_ch4(&self) -> IN_CMDFIFO_INFIFO_CNT_CH4_R { + IN_CMDFIFO_INFIFO_CNT_CH4_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_FIFO_CNT_CH4") + .field( + "in_cmdfifo_infifo_cnt_ch4", + &format_args!("{}", self.in_cmdfifo_infifo_cnt_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH4 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_FIFO_CNT_CH4_SPEC; +impl crate::RegisterSpec for IN_FIFO_CNT_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_fifo_cnt_ch4::R`](R) reader structure"] +impl crate::Readable for IN_FIFO_CNT_CH4_SPEC {} +#[doc = "`reset()` method sets IN_FIFO_CNT_CH4 to value 0"] +impl crate::Resettable for IN_FIFO_CNT_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_fifo_cnt_ch5.rs b/esp32p4/src/h264_dma/in_fifo_cnt_ch5.rs new file mode 100644 index 0000000000..a9410ef01c --- /dev/null +++ b/esp32p4/src/h264_dma/in_fifo_cnt_ch5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_FIFO_CNT_CH5` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_INFIFO_CNT_CH5` reader - only for debug"] +pub type IN_CMDFIFO_INFIFO_CNT_CH5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_infifo_cnt_ch5(&self) -> IN_CMDFIFO_INFIFO_CNT_CH5_R { + IN_CMDFIFO_INFIFO_CNT_CH5_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_FIFO_CNT_CH5") + .field( + "in_cmdfifo_infifo_cnt_ch5", + &format_args!("{}", self.in_cmdfifo_infifo_cnt_ch5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH5 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_fifo_cnt_ch5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_FIFO_CNT_CH5_SPEC; +impl crate::RegisterSpec for IN_FIFO_CNT_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_fifo_cnt_ch5::R`](R) reader structure"] +impl crate::Readable for IN_FIFO_CNT_CH5_SPEC {} +#[doc = "`reset()` method sets IN_FIFO_CNT_CH5 to value 0"] +impl crate::Resettable for IN_FIFO_CNT_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_clr_ch0.rs b/esp32p4/src/h264_dma/in_int_clr_ch0.rs new file mode 100644 index 0000000000..2383fc3c9b --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_clr_ch0.rs @@ -0,0 +1,126 @@ +#[doc = "Register `IN_INT_CLR_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH0_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH0_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH0_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH0_INT_CLR` writer - Set this bit to clear the INDSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH0_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH0_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH0_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH0_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH0_INT_CLR` writer - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch0_int_clr(&mut self) -> IN_DONE_CH0_INT_CLR_W { + IN_DONE_CH0_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch0_int_clr(&mut self) -> IN_SUC_EOF_CH0_INT_CLR_W { + IN_SUC_EOF_CH0_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch0_int_clr(&mut self) -> IN_ERR_EOF_CH0_INT_CLR_W { + IN_ERR_EOF_CH0_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the INDSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch0_int_clr(&mut self) -> IN_DSCR_ERR_CH0_INT_CLR_W { + IN_DSCR_ERR_CH0_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch0_int_clr( + &mut self, + ) -> INFIFO_OVF_L1_CH0_INT_CLR_W { + INFIFO_OVF_L1_CH0_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch0_int_clr( + &mut self, + ) -> INFIFO_UDF_L1_CH0_INT_CLR_W { + INFIFO_UDF_L1_CH0_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch0_int_clr( + &mut self, + ) -> INFIFO_OVF_L2_CH0_INT_CLR_W { + INFIFO_OVF_L2_CH0_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch0_int_clr( + &mut self, + ) -> INFIFO_UDF_L2_CH0_INT_CLR_W { + INFIFO_UDF_L2_CH0_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch0_int_clr( + &mut self, + ) -> IN_DSCR_EMPTY_CH0_INT_CLR_W { + IN_DSCR_EMPTY_CH0_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch0_int_clr( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH0_INT_CLR_W { + IN_DSCR_TASK_OVF_CH0_INT_CLR_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH0 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_CLR_CH0_SPEC; +impl crate::RegisterSpec for IN_INT_CLR_CH0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`in_int_clr_ch0::W`](W) writer structure"] +impl crate::Writable for IN_INT_CLR_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_CLR_CH0 to value 0"] +impl crate::Resettable for IN_INT_CLR_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_clr_ch1.rs b/esp32p4/src/h264_dma/in_int_clr_ch1.rs new file mode 100644 index 0000000000..1e896bc87d --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_clr_ch1.rs @@ -0,0 +1,126 @@ +#[doc = "Register `IN_INT_CLR_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH1_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH1_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH1_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH1_INT_CLR` writer - Set this bit to clear the INDSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH1_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH1_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH1_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH1_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH1_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH1_INT_CLR` writer - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch1_int_clr(&mut self) -> IN_DONE_CH1_INT_CLR_W { + IN_DONE_CH1_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch1_int_clr(&mut self) -> IN_SUC_EOF_CH1_INT_CLR_W { + IN_SUC_EOF_CH1_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch1_int_clr(&mut self) -> IN_ERR_EOF_CH1_INT_CLR_W { + IN_ERR_EOF_CH1_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the INDSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch1_int_clr(&mut self) -> IN_DSCR_ERR_CH1_INT_CLR_W { + IN_DSCR_ERR_CH1_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch1_int_clr( + &mut self, + ) -> INFIFO_OVF_L1_CH1_INT_CLR_W { + INFIFO_OVF_L1_CH1_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch1_int_clr( + &mut self, + ) -> INFIFO_UDF_L1_CH1_INT_CLR_W { + INFIFO_UDF_L1_CH1_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch1_int_clr( + &mut self, + ) -> INFIFO_OVF_L2_CH1_INT_CLR_W { + INFIFO_OVF_L2_CH1_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch1_int_clr( + &mut self, + ) -> INFIFO_UDF_L2_CH1_INT_CLR_W { + INFIFO_UDF_L2_CH1_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch1_int_clr( + &mut self, + ) -> IN_DSCR_EMPTY_CH1_INT_CLR_W { + IN_DSCR_EMPTY_CH1_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch1_int_clr( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH1_INT_CLR_W { + IN_DSCR_TASK_OVF_CH1_INT_CLR_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH1 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_CLR_CH1_SPEC; +impl crate::RegisterSpec for IN_INT_CLR_CH1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`in_int_clr_ch1::W`](W) writer structure"] +impl crate::Writable for IN_INT_CLR_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_CLR_CH1 to value 0"] +impl crate::Resettable for IN_INT_CLR_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_clr_ch2.rs b/esp32p4/src/h264_dma/in_int_clr_ch2.rs new file mode 100644 index 0000000000..5a7b3e436a --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_clr_ch2.rs @@ -0,0 +1,126 @@ +#[doc = "Register `IN_INT_CLR_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH2_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH2_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH2_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH2_INT_CLR` writer - Set this bit to clear the INDSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH2_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH2_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH2_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH2_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH2_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH2_INT_CLR` writer - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch2_int_clr(&mut self) -> IN_DONE_CH2_INT_CLR_W { + IN_DONE_CH2_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch2_int_clr(&mut self) -> IN_SUC_EOF_CH2_INT_CLR_W { + IN_SUC_EOF_CH2_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch2_int_clr(&mut self) -> IN_ERR_EOF_CH2_INT_CLR_W { + IN_ERR_EOF_CH2_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the INDSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch2_int_clr(&mut self) -> IN_DSCR_ERR_CH2_INT_CLR_W { + IN_DSCR_ERR_CH2_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch2_int_clr( + &mut self, + ) -> INFIFO_OVF_L1_CH2_INT_CLR_W { + INFIFO_OVF_L1_CH2_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch2_int_clr( + &mut self, + ) -> INFIFO_UDF_L1_CH2_INT_CLR_W { + INFIFO_UDF_L1_CH2_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch2_int_clr( + &mut self, + ) -> INFIFO_OVF_L2_CH2_INT_CLR_W { + INFIFO_OVF_L2_CH2_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch2_int_clr( + &mut self, + ) -> INFIFO_UDF_L2_CH2_INT_CLR_W { + INFIFO_UDF_L2_CH2_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch2_int_clr( + &mut self, + ) -> IN_DSCR_EMPTY_CH2_INT_CLR_W { + IN_DSCR_EMPTY_CH2_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch2_int_clr( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH2_INT_CLR_W { + IN_DSCR_TASK_OVF_CH2_INT_CLR_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH2 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_CLR_CH2_SPEC; +impl crate::RegisterSpec for IN_INT_CLR_CH2_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`in_int_clr_ch2::W`](W) writer structure"] +impl crate::Writable for IN_INT_CLR_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_CLR_CH2 to value 0"] +impl crate::Resettable for IN_INT_CLR_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_clr_ch3.rs b/esp32p4/src/h264_dma/in_int_clr_ch3.rs new file mode 100644 index 0000000000..9668061737 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_clr_ch3.rs @@ -0,0 +1,126 @@ +#[doc = "Register `IN_INT_CLR_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH3_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH3_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH3_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH3_INT_CLR` writer - Set this bit to clear the INDSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH3_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH3_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH3_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH3_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH3_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH3_INT_CLR` writer - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch3_int_clr(&mut self) -> IN_DONE_CH3_INT_CLR_W { + IN_DONE_CH3_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch3_int_clr(&mut self) -> IN_SUC_EOF_CH3_INT_CLR_W { + IN_SUC_EOF_CH3_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch3_int_clr(&mut self) -> IN_ERR_EOF_CH3_INT_CLR_W { + IN_ERR_EOF_CH3_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the INDSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch3_int_clr(&mut self) -> IN_DSCR_ERR_CH3_INT_CLR_W { + IN_DSCR_ERR_CH3_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch3_int_clr( + &mut self, + ) -> INFIFO_OVF_L1_CH3_INT_CLR_W { + INFIFO_OVF_L1_CH3_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch3_int_clr( + &mut self, + ) -> INFIFO_UDF_L1_CH3_INT_CLR_W { + INFIFO_UDF_L1_CH3_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch3_int_clr( + &mut self, + ) -> INFIFO_OVF_L2_CH3_INT_CLR_W { + INFIFO_OVF_L2_CH3_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch3_int_clr( + &mut self, + ) -> INFIFO_UDF_L2_CH3_INT_CLR_W { + INFIFO_UDF_L2_CH3_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch3_int_clr( + &mut self, + ) -> IN_DSCR_EMPTY_CH3_INT_CLR_W { + IN_DSCR_EMPTY_CH3_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch3_int_clr( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH3_INT_CLR_W { + IN_DSCR_TASK_OVF_CH3_INT_CLR_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH3 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch3::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_CLR_CH3_SPEC; +impl crate::RegisterSpec for IN_INT_CLR_CH3_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`in_int_clr_ch3::W`](W) writer structure"] +impl crate::Writable for IN_INT_CLR_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_CLR_CH3 to value 0"] +impl crate::Resettable for IN_INT_CLR_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_clr_ch4.rs b/esp32p4/src/h264_dma/in_int_clr_ch4.rs new file mode 100644 index 0000000000..c7a58d97db --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_clr_ch4.rs @@ -0,0 +1,126 @@ +#[doc = "Register `IN_INT_CLR_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH4_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH4_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH4_INT_CLR` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH4_INT_CLR` writer - Set this bit to clear the INDSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH4_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH4_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH4_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH4_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH4_INT_CLR` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH4_INT_CLR` writer - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch4_int_clr(&mut self) -> IN_DONE_CH4_INT_CLR_W { + IN_DONE_CH4_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch4_int_clr(&mut self) -> IN_SUC_EOF_CH4_INT_CLR_W { + IN_SUC_EOF_CH4_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch4_int_clr(&mut self) -> IN_ERR_EOF_CH4_INT_CLR_W { + IN_ERR_EOF_CH4_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the INDSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch4_int_clr(&mut self) -> IN_DSCR_ERR_CH4_INT_CLR_W { + IN_DSCR_ERR_CH4_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch4_int_clr( + &mut self, + ) -> INFIFO_OVF_L1_CH4_INT_CLR_W { + INFIFO_OVF_L1_CH4_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch4_int_clr( + &mut self, + ) -> INFIFO_UDF_L1_CH4_INT_CLR_W { + INFIFO_UDF_L1_CH4_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch4_int_clr( + &mut self, + ) -> INFIFO_OVF_L2_CH4_INT_CLR_W { + INFIFO_OVF_L2_CH4_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch4_int_clr( + &mut self, + ) -> INFIFO_UDF_L2_CH4_INT_CLR_W { + INFIFO_UDF_L2_CH4_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch4_int_clr( + &mut self, + ) -> IN_DSCR_EMPTY_CH4_INT_CLR_W { + IN_DSCR_EMPTY_CH4_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch4_int_clr( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH4_INT_CLR_W { + IN_DSCR_TASK_OVF_CH4_INT_CLR_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH4 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch4::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_CLR_CH4_SPEC; +impl crate::RegisterSpec for IN_INT_CLR_CH4_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`in_int_clr_ch4::W`](W) writer structure"] +impl crate::Writable for IN_INT_CLR_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_CLR_CH4 to value 0"] +impl crate::Resettable for IN_INT_CLR_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_clr_ch5.rs b/esp32p4/src/h264_dma/in_int_clr_ch5.rs new file mode 100644 index 0000000000..dc57685fc1 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_clr_ch5.rs @@ -0,0 +1,80 @@ +#[doc = "Register `IN_INT_CLR_CH5` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH5_INT_CLR` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH5_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH5_INT_CLR` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH5_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH5_INT_CLR` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH5_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH5_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH5_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FETCH_MB_COL_CNT_OVF_CH5_INT_CLR` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] +pub type FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch5_int_clr(&mut self) -> IN_DONE_CH5_INT_CLR_W { + IN_DONE_CH5_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch5_int_clr(&mut self) -> IN_SUC_EOF_CH5_INT_CLR_W { + IN_SUC_EOF_CH5_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch5_int_clr( + &mut self, + ) -> INFIFO_OVF_L1_CH5_INT_CLR_W { + INFIFO_OVF_L1_CH5_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch5_int_clr( + &mut self, + ) -> INFIFO_UDF_L1_CH5_INT_CLR_W { + INFIFO_UDF_L1_CH5_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn fetch_mb_col_cnt_ovf_ch5_int_clr( + &mut self, + ) -> FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_W { + FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH5 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_clr_ch5::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_CLR_CH5_SPEC; +impl crate::RegisterSpec for IN_INT_CLR_CH5_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`in_int_clr_ch5::W`](W) writer structure"] +impl crate::Writable for IN_INT_CLR_CH5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_CLR_CH5 to value 0"] +impl crate::Resettable for IN_INT_CLR_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_ena_ch0.rs b/esp32p4/src/h264_dma/in_int_ena_ch0.rs new file mode 100644 index 0000000000..436db5468e --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_ena_ch0.rs @@ -0,0 +1,249 @@ +#[doc = "Register `IN_INT_ENA_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_ENA_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH0_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH0_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH0_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH0_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH0_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH0_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH0_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH0_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH0_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH0_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH0_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH0_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH0_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH0_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch0_int_ena(&self) -> IN_DONE_CH0_INT_ENA_R { + IN_DONE_CH0_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch0_int_ena(&self) -> IN_SUC_EOF_CH0_INT_ENA_R { + IN_SUC_EOF_CH0_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch0_int_ena(&self) -> IN_ERR_EOF_CH0_INT_ENA_R { + IN_ERR_EOF_CH0_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch0_int_ena(&self) -> IN_DSCR_ERR_CH0_INT_ENA_R { + IN_DSCR_ERR_CH0_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch0_int_ena(&self) -> INFIFO_OVF_L1_CH0_INT_ENA_R { + INFIFO_OVF_L1_CH0_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch0_int_ena(&self) -> INFIFO_UDF_L1_CH0_INT_ENA_R { + INFIFO_UDF_L1_CH0_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l2_ch0_int_ena(&self) -> INFIFO_OVF_L2_CH0_INT_ENA_R { + INFIFO_OVF_L2_CH0_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l2_ch0_int_ena(&self) -> INFIFO_UDF_L2_CH0_INT_ENA_R { + INFIFO_UDF_L2_CH0_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch0_int_ena(&self) -> IN_DSCR_EMPTY_CH0_INT_ENA_R { + IN_DSCR_EMPTY_CH0_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch0_int_ena(&self) -> IN_DSCR_TASK_OVF_CH0_INT_ENA_R { + IN_DSCR_TASK_OVF_CH0_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ENA_CH0") + .field( + "in_done_ch0_int_ena", + &format_args!("{}", self.in_done_ch0_int_ena().bit()), + ) + .field( + "in_suc_eof_ch0_int_ena", + &format_args!("{}", self.in_suc_eof_ch0_int_ena().bit()), + ) + .field( + "in_err_eof_ch0_int_ena", + &format_args!("{}", self.in_err_eof_ch0_int_ena().bit()), + ) + .field( + "in_dscr_err_ch0_int_ena", + &format_args!("{}", self.in_dscr_err_ch0_int_ena().bit()), + ) + .field( + "infifo_ovf_l1_ch0_int_ena", + &format_args!("{}", self.infifo_ovf_l1_ch0_int_ena().bit()), + ) + .field( + "infifo_udf_l1_ch0_int_ena", + &format_args!("{}", self.infifo_udf_l1_ch0_int_ena().bit()), + ) + .field( + "infifo_ovf_l2_ch0_int_ena", + &format_args!("{}", self.infifo_ovf_l2_ch0_int_ena().bit()), + ) + .field( + "infifo_udf_l2_ch0_int_ena", + &format_args!("{}", self.infifo_udf_l2_ch0_int_ena().bit()), + ) + .field( + "in_dscr_empty_ch0_int_ena", + &format_args!("{}", self.in_dscr_empty_ch0_int_ena().bit()), + ) + .field( + "in_dscr_task_ovf_ch0_int_ena", + &format_args!("{}", self.in_dscr_task_ovf_ch0_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch0_int_ena(&mut self) -> IN_DONE_CH0_INT_ENA_W { + IN_DONE_CH0_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch0_int_ena(&mut self) -> IN_SUC_EOF_CH0_INT_ENA_W { + IN_SUC_EOF_CH0_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch0_int_ena(&mut self) -> IN_ERR_EOF_CH0_INT_ENA_W { + IN_ERR_EOF_CH0_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch0_int_ena(&mut self) -> IN_DSCR_ERR_CH0_INT_ENA_W { + IN_DSCR_ERR_CH0_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch0_int_ena( + &mut self, + ) -> INFIFO_OVF_L1_CH0_INT_ENA_W { + INFIFO_OVF_L1_CH0_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch0_int_ena( + &mut self, + ) -> INFIFO_UDF_L1_CH0_INT_ENA_W { + INFIFO_UDF_L1_CH0_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch0_int_ena( + &mut self, + ) -> INFIFO_OVF_L2_CH0_INT_ENA_W { + INFIFO_OVF_L2_CH0_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch0_int_ena( + &mut self, + ) -> INFIFO_UDF_L2_CH0_INT_ENA_W { + INFIFO_UDF_L2_CH0_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch0_int_ena( + &mut self, + ) -> IN_DSCR_EMPTY_CH0_INT_ENA_W { + IN_DSCR_EMPTY_CH0_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch0_int_ena( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH0_INT_ENA_W { + IN_DSCR_TASK_OVF_CH0_INT_ENA_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH0 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ENA_CH0_SPEC; +impl crate::RegisterSpec for IN_INT_ENA_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_ena_ch0::R`](R) reader structure"] +impl crate::Readable for IN_INT_ENA_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_ena_ch0::W`](W) writer structure"] +impl crate::Writable for IN_INT_ENA_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_ENA_CH0 to value 0"] +impl crate::Resettable for IN_INT_ENA_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_ena_ch1.rs b/esp32p4/src/h264_dma/in_int_ena_ch1.rs new file mode 100644 index 0000000000..9c4b7341ce --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_ena_ch1.rs @@ -0,0 +1,249 @@ +#[doc = "Register `IN_INT_ENA_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_ENA_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH1_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH1_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH1_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH1_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH1_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH1_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH1_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH1_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH1_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH1_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH1_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH1_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH1_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH1_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH1_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH1_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH1_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH1_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH1_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH1_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch1_int_ena(&self) -> IN_DONE_CH1_INT_ENA_R { + IN_DONE_CH1_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch1_int_ena(&self) -> IN_SUC_EOF_CH1_INT_ENA_R { + IN_SUC_EOF_CH1_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch1_int_ena(&self) -> IN_ERR_EOF_CH1_INT_ENA_R { + IN_ERR_EOF_CH1_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch1_int_ena(&self) -> IN_DSCR_ERR_CH1_INT_ENA_R { + IN_DSCR_ERR_CH1_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch1_int_ena(&self) -> INFIFO_OVF_L1_CH1_INT_ENA_R { + INFIFO_OVF_L1_CH1_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch1_int_ena(&self) -> INFIFO_UDF_L1_CH1_INT_ENA_R { + INFIFO_UDF_L1_CH1_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l2_ch1_int_ena(&self) -> INFIFO_OVF_L2_CH1_INT_ENA_R { + INFIFO_OVF_L2_CH1_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l2_ch1_int_ena(&self) -> INFIFO_UDF_L2_CH1_INT_ENA_R { + INFIFO_UDF_L2_CH1_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch1_int_ena(&self) -> IN_DSCR_EMPTY_CH1_INT_ENA_R { + IN_DSCR_EMPTY_CH1_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch1_int_ena(&self) -> IN_DSCR_TASK_OVF_CH1_INT_ENA_R { + IN_DSCR_TASK_OVF_CH1_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ENA_CH1") + .field( + "in_done_ch1_int_ena", + &format_args!("{}", self.in_done_ch1_int_ena().bit()), + ) + .field( + "in_suc_eof_ch1_int_ena", + &format_args!("{}", self.in_suc_eof_ch1_int_ena().bit()), + ) + .field( + "in_err_eof_ch1_int_ena", + &format_args!("{}", self.in_err_eof_ch1_int_ena().bit()), + ) + .field( + "in_dscr_err_ch1_int_ena", + &format_args!("{}", self.in_dscr_err_ch1_int_ena().bit()), + ) + .field( + "infifo_ovf_l1_ch1_int_ena", + &format_args!("{}", self.infifo_ovf_l1_ch1_int_ena().bit()), + ) + .field( + "infifo_udf_l1_ch1_int_ena", + &format_args!("{}", self.infifo_udf_l1_ch1_int_ena().bit()), + ) + .field( + "infifo_ovf_l2_ch1_int_ena", + &format_args!("{}", self.infifo_ovf_l2_ch1_int_ena().bit()), + ) + .field( + "infifo_udf_l2_ch1_int_ena", + &format_args!("{}", self.infifo_udf_l2_ch1_int_ena().bit()), + ) + .field( + "in_dscr_empty_ch1_int_ena", + &format_args!("{}", self.in_dscr_empty_ch1_int_ena().bit()), + ) + .field( + "in_dscr_task_ovf_ch1_int_ena", + &format_args!("{}", self.in_dscr_task_ovf_ch1_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch1_int_ena(&mut self) -> IN_DONE_CH1_INT_ENA_W { + IN_DONE_CH1_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch1_int_ena(&mut self) -> IN_SUC_EOF_CH1_INT_ENA_W { + IN_SUC_EOF_CH1_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch1_int_ena(&mut self) -> IN_ERR_EOF_CH1_INT_ENA_W { + IN_ERR_EOF_CH1_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch1_int_ena(&mut self) -> IN_DSCR_ERR_CH1_INT_ENA_W { + IN_DSCR_ERR_CH1_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch1_int_ena( + &mut self, + ) -> INFIFO_OVF_L1_CH1_INT_ENA_W { + INFIFO_OVF_L1_CH1_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch1_int_ena( + &mut self, + ) -> INFIFO_UDF_L1_CH1_INT_ENA_W { + INFIFO_UDF_L1_CH1_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch1_int_ena( + &mut self, + ) -> INFIFO_OVF_L2_CH1_INT_ENA_W { + INFIFO_OVF_L2_CH1_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch1_int_ena( + &mut self, + ) -> INFIFO_UDF_L2_CH1_INT_ENA_W { + INFIFO_UDF_L2_CH1_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch1_int_ena( + &mut self, + ) -> IN_DSCR_EMPTY_CH1_INT_ENA_W { + IN_DSCR_EMPTY_CH1_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch1_int_ena( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH1_INT_ENA_W { + IN_DSCR_TASK_OVF_CH1_INT_ENA_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH1 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ENA_CH1_SPEC; +impl crate::RegisterSpec for IN_INT_ENA_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_ena_ch1::R`](R) reader structure"] +impl crate::Readable for IN_INT_ENA_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_ena_ch1::W`](W) writer structure"] +impl crate::Writable for IN_INT_ENA_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_ENA_CH1 to value 0"] +impl crate::Resettable for IN_INT_ENA_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_ena_ch2.rs b/esp32p4/src/h264_dma/in_int_ena_ch2.rs new file mode 100644 index 0000000000..9640bb6e4e --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_ena_ch2.rs @@ -0,0 +1,249 @@ +#[doc = "Register `IN_INT_ENA_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_ENA_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH2_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH2_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH2_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH2_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH2_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH2_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH2_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH2_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH2_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH2_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH2_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH2_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH2_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH2_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH2_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH2_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH2_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH2_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH2_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH2_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch2_int_ena(&self) -> IN_DONE_CH2_INT_ENA_R { + IN_DONE_CH2_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch2_int_ena(&self) -> IN_SUC_EOF_CH2_INT_ENA_R { + IN_SUC_EOF_CH2_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch2_int_ena(&self) -> IN_ERR_EOF_CH2_INT_ENA_R { + IN_ERR_EOF_CH2_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch2_int_ena(&self) -> IN_DSCR_ERR_CH2_INT_ENA_R { + IN_DSCR_ERR_CH2_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch2_int_ena(&self) -> INFIFO_OVF_L1_CH2_INT_ENA_R { + INFIFO_OVF_L1_CH2_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch2_int_ena(&self) -> INFIFO_UDF_L1_CH2_INT_ENA_R { + INFIFO_UDF_L1_CH2_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l2_ch2_int_ena(&self) -> INFIFO_OVF_L2_CH2_INT_ENA_R { + INFIFO_OVF_L2_CH2_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l2_ch2_int_ena(&self) -> INFIFO_UDF_L2_CH2_INT_ENA_R { + INFIFO_UDF_L2_CH2_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch2_int_ena(&self) -> IN_DSCR_EMPTY_CH2_INT_ENA_R { + IN_DSCR_EMPTY_CH2_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch2_int_ena(&self) -> IN_DSCR_TASK_OVF_CH2_INT_ENA_R { + IN_DSCR_TASK_OVF_CH2_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ENA_CH2") + .field( + "in_done_ch2_int_ena", + &format_args!("{}", self.in_done_ch2_int_ena().bit()), + ) + .field( + "in_suc_eof_ch2_int_ena", + &format_args!("{}", self.in_suc_eof_ch2_int_ena().bit()), + ) + .field( + "in_err_eof_ch2_int_ena", + &format_args!("{}", self.in_err_eof_ch2_int_ena().bit()), + ) + .field( + "in_dscr_err_ch2_int_ena", + &format_args!("{}", self.in_dscr_err_ch2_int_ena().bit()), + ) + .field( + "infifo_ovf_l1_ch2_int_ena", + &format_args!("{}", self.infifo_ovf_l1_ch2_int_ena().bit()), + ) + .field( + "infifo_udf_l1_ch2_int_ena", + &format_args!("{}", self.infifo_udf_l1_ch2_int_ena().bit()), + ) + .field( + "infifo_ovf_l2_ch2_int_ena", + &format_args!("{}", self.infifo_ovf_l2_ch2_int_ena().bit()), + ) + .field( + "infifo_udf_l2_ch2_int_ena", + &format_args!("{}", self.infifo_udf_l2_ch2_int_ena().bit()), + ) + .field( + "in_dscr_empty_ch2_int_ena", + &format_args!("{}", self.in_dscr_empty_ch2_int_ena().bit()), + ) + .field( + "in_dscr_task_ovf_ch2_int_ena", + &format_args!("{}", self.in_dscr_task_ovf_ch2_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch2_int_ena(&mut self) -> IN_DONE_CH2_INT_ENA_W { + IN_DONE_CH2_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch2_int_ena(&mut self) -> IN_SUC_EOF_CH2_INT_ENA_W { + IN_SUC_EOF_CH2_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch2_int_ena(&mut self) -> IN_ERR_EOF_CH2_INT_ENA_W { + IN_ERR_EOF_CH2_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch2_int_ena(&mut self) -> IN_DSCR_ERR_CH2_INT_ENA_W { + IN_DSCR_ERR_CH2_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch2_int_ena( + &mut self, + ) -> INFIFO_OVF_L1_CH2_INT_ENA_W { + INFIFO_OVF_L1_CH2_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch2_int_ena( + &mut self, + ) -> INFIFO_UDF_L1_CH2_INT_ENA_W { + INFIFO_UDF_L1_CH2_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch2_int_ena( + &mut self, + ) -> INFIFO_OVF_L2_CH2_INT_ENA_W { + INFIFO_OVF_L2_CH2_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch2_int_ena( + &mut self, + ) -> INFIFO_UDF_L2_CH2_INT_ENA_W { + INFIFO_UDF_L2_CH2_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch2_int_ena( + &mut self, + ) -> IN_DSCR_EMPTY_CH2_INT_ENA_W { + IN_DSCR_EMPTY_CH2_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch2_int_ena( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH2_INT_ENA_W { + IN_DSCR_TASK_OVF_CH2_INT_ENA_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH2 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ENA_CH2_SPEC; +impl crate::RegisterSpec for IN_INT_ENA_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_ena_ch2::R`](R) reader structure"] +impl crate::Readable for IN_INT_ENA_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_ena_ch2::W`](W) writer structure"] +impl crate::Writable for IN_INT_ENA_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_ENA_CH2 to value 0"] +impl crate::Resettable for IN_INT_ENA_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_ena_ch3.rs b/esp32p4/src/h264_dma/in_int_ena_ch3.rs new file mode 100644 index 0000000000..fef8c8e2cb --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_ena_ch3.rs @@ -0,0 +1,249 @@ +#[doc = "Register `IN_INT_ENA_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_ENA_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH3_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH3_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH3_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH3_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH3_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH3_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH3_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH3_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH3_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH3_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH3_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH3_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH3_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH3_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH3_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH3_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH3_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH3_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH3_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH3_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch3_int_ena(&self) -> IN_DONE_CH3_INT_ENA_R { + IN_DONE_CH3_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch3_int_ena(&self) -> IN_SUC_EOF_CH3_INT_ENA_R { + IN_SUC_EOF_CH3_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch3_int_ena(&self) -> IN_ERR_EOF_CH3_INT_ENA_R { + IN_ERR_EOF_CH3_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch3_int_ena(&self) -> IN_DSCR_ERR_CH3_INT_ENA_R { + IN_DSCR_ERR_CH3_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch3_int_ena(&self) -> INFIFO_OVF_L1_CH3_INT_ENA_R { + INFIFO_OVF_L1_CH3_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch3_int_ena(&self) -> INFIFO_UDF_L1_CH3_INT_ENA_R { + INFIFO_UDF_L1_CH3_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l2_ch3_int_ena(&self) -> INFIFO_OVF_L2_CH3_INT_ENA_R { + INFIFO_OVF_L2_CH3_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l2_ch3_int_ena(&self) -> INFIFO_UDF_L2_CH3_INT_ENA_R { + INFIFO_UDF_L2_CH3_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch3_int_ena(&self) -> IN_DSCR_EMPTY_CH3_INT_ENA_R { + IN_DSCR_EMPTY_CH3_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch3_int_ena(&self) -> IN_DSCR_TASK_OVF_CH3_INT_ENA_R { + IN_DSCR_TASK_OVF_CH3_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ENA_CH3") + .field( + "in_done_ch3_int_ena", + &format_args!("{}", self.in_done_ch3_int_ena().bit()), + ) + .field( + "in_suc_eof_ch3_int_ena", + &format_args!("{}", self.in_suc_eof_ch3_int_ena().bit()), + ) + .field( + "in_err_eof_ch3_int_ena", + &format_args!("{}", self.in_err_eof_ch3_int_ena().bit()), + ) + .field( + "in_dscr_err_ch3_int_ena", + &format_args!("{}", self.in_dscr_err_ch3_int_ena().bit()), + ) + .field( + "infifo_ovf_l1_ch3_int_ena", + &format_args!("{}", self.infifo_ovf_l1_ch3_int_ena().bit()), + ) + .field( + "infifo_udf_l1_ch3_int_ena", + &format_args!("{}", self.infifo_udf_l1_ch3_int_ena().bit()), + ) + .field( + "infifo_ovf_l2_ch3_int_ena", + &format_args!("{}", self.infifo_ovf_l2_ch3_int_ena().bit()), + ) + .field( + "infifo_udf_l2_ch3_int_ena", + &format_args!("{}", self.infifo_udf_l2_ch3_int_ena().bit()), + ) + .field( + "in_dscr_empty_ch3_int_ena", + &format_args!("{}", self.in_dscr_empty_ch3_int_ena().bit()), + ) + .field( + "in_dscr_task_ovf_ch3_int_ena", + &format_args!("{}", self.in_dscr_task_ovf_ch3_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch3_int_ena(&mut self) -> IN_DONE_CH3_INT_ENA_W { + IN_DONE_CH3_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch3_int_ena(&mut self) -> IN_SUC_EOF_CH3_INT_ENA_W { + IN_SUC_EOF_CH3_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch3_int_ena(&mut self) -> IN_ERR_EOF_CH3_INT_ENA_W { + IN_ERR_EOF_CH3_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch3_int_ena(&mut self) -> IN_DSCR_ERR_CH3_INT_ENA_W { + IN_DSCR_ERR_CH3_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch3_int_ena( + &mut self, + ) -> INFIFO_OVF_L1_CH3_INT_ENA_W { + INFIFO_OVF_L1_CH3_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch3_int_ena( + &mut self, + ) -> INFIFO_UDF_L1_CH3_INT_ENA_W { + INFIFO_UDF_L1_CH3_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch3_int_ena( + &mut self, + ) -> INFIFO_OVF_L2_CH3_INT_ENA_W { + INFIFO_OVF_L2_CH3_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch3_int_ena( + &mut self, + ) -> INFIFO_UDF_L2_CH3_INT_ENA_W { + INFIFO_UDF_L2_CH3_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch3_int_ena( + &mut self, + ) -> IN_DSCR_EMPTY_CH3_INT_ENA_W { + IN_DSCR_EMPTY_CH3_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch3_int_ena( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH3_INT_ENA_W { + IN_DSCR_TASK_OVF_CH3_INT_ENA_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH3 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ENA_CH3_SPEC; +impl crate::RegisterSpec for IN_INT_ENA_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_ena_ch3::R`](R) reader structure"] +impl crate::Readable for IN_INT_ENA_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_ena_ch3::W`](W) writer structure"] +impl crate::Writable for IN_INT_ENA_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_ENA_CH3 to value 0"] +impl crate::Resettable for IN_INT_ENA_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_ena_ch4.rs b/esp32p4/src/h264_dma/in_int_ena_ch4.rs new file mode 100644 index 0000000000..47da91b4ae --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_ena_ch4.rs @@ -0,0 +1,249 @@ +#[doc = "Register `IN_INT_ENA_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_ENA_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH4_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH4_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH4_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH4_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH4_INT_ENA` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH4_INT_ENA` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH4_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH4_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH4_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH4_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH4_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH4_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH4_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH4_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH4_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH4_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH4_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH4_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH4_INT_ENA` reader - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH4_INT_ENA` writer - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch4_int_ena(&self) -> IN_DONE_CH4_INT_ENA_R { + IN_DONE_CH4_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch4_int_ena(&self) -> IN_SUC_EOF_CH4_INT_ENA_R { + IN_SUC_EOF_CH4_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch4_int_ena(&self) -> IN_ERR_EOF_CH4_INT_ENA_R { + IN_ERR_EOF_CH4_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch4_int_ena(&self) -> IN_DSCR_ERR_CH4_INT_ENA_R { + IN_DSCR_ERR_CH4_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch4_int_ena(&self) -> INFIFO_OVF_L1_CH4_INT_ENA_R { + INFIFO_OVF_L1_CH4_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch4_int_ena(&self) -> INFIFO_UDF_L1_CH4_INT_ENA_R { + INFIFO_UDF_L1_CH4_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l2_ch4_int_ena(&self) -> INFIFO_OVF_L2_CH4_INT_ENA_R { + INFIFO_OVF_L2_CH4_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l2_ch4_int_ena(&self) -> INFIFO_UDF_L2_CH4_INT_ENA_R { + INFIFO_UDF_L2_CH4_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch4_int_ena(&self) -> IN_DSCR_EMPTY_CH4_INT_ENA_R { + IN_DSCR_EMPTY_CH4_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch4_int_ena(&self) -> IN_DSCR_TASK_OVF_CH4_INT_ENA_R { + IN_DSCR_TASK_OVF_CH4_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ENA_CH4") + .field( + "in_done_ch4_int_ena", + &format_args!("{}", self.in_done_ch4_int_ena().bit()), + ) + .field( + "in_suc_eof_ch4_int_ena", + &format_args!("{}", self.in_suc_eof_ch4_int_ena().bit()), + ) + .field( + "in_err_eof_ch4_int_ena", + &format_args!("{}", self.in_err_eof_ch4_int_ena().bit()), + ) + .field( + "in_dscr_err_ch4_int_ena", + &format_args!("{}", self.in_dscr_err_ch4_int_ena().bit()), + ) + .field( + "infifo_ovf_l1_ch4_int_ena", + &format_args!("{}", self.infifo_ovf_l1_ch4_int_ena().bit()), + ) + .field( + "infifo_udf_l1_ch4_int_ena", + &format_args!("{}", self.infifo_udf_l1_ch4_int_ena().bit()), + ) + .field( + "infifo_ovf_l2_ch4_int_ena", + &format_args!("{}", self.infifo_ovf_l2_ch4_int_ena().bit()), + ) + .field( + "infifo_udf_l2_ch4_int_ena", + &format_args!("{}", self.infifo_udf_l2_ch4_int_ena().bit()), + ) + .field( + "in_dscr_empty_ch4_int_ena", + &format_args!("{}", self.in_dscr_empty_ch4_int_ena().bit()), + ) + .field( + "in_dscr_task_ovf_ch4_int_ena", + &format_args!("{}", self.in_dscr_task_ovf_ch4_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch4_int_ena(&mut self) -> IN_DONE_CH4_INT_ENA_W { + IN_DONE_CH4_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch4_int_ena(&mut self) -> IN_SUC_EOF_CH4_INT_ENA_W { + IN_SUC_EOF_CH4_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch4_int_ena(&mut self) -> IN_ERR_EOF_CH4_INT_ENA_W { + IN_ERR_EOF_CH4_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch4_int_ena(&mut self) -> IN_DSCR_ERR_CH4_INT_ENA_W { + IN_DSCR_ERR_CH4_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch4_int_ena( + &mut self, + ) -> INFIFO_OVF_L1_CH4_INT_ENA_W { + INFIFO_OVF_L1_CH4_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch4_int_ena( + &mut self, + ) -> INFIFO_UDF_L1_CH4_INT_ENA_W { + INFIFO_UDF_L1_CH4_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch4_int_ena( + &mut self, + ) -> INFIFO_OVF_L2_CH4_INT_ENA_W { + INFIFO_OVF_L2_CH4_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch4_int_ena( + &mut self, + ) -> INFIFO_UDF_L2_CH4_INT_ENA_W { + INFIFO_UDF_L2_CH4_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch4_int_ena( + &mut self, + ) -> IN_DSCR_EMPTY_CH4_INT_ENA_W { + IN_DSCR_EMPTY_CH4_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch4_int_ena( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH4_INT_ENA_W { + IN_DSCR_TASK_OVF_CH4_INT_ENA_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH4 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ENA_CH4_SPEC; +impl crate::RegisterSpec for IN_INT_ENA_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_ena_ch4::R`](R) reader structure"] +impl crate::Readable for IN_INT_ENA_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_ena_ch4::W`](W) writer structure"] +impl crate::Writable for IN_INT_ENA_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_ENA_CH4 to value 0"] +impl crate::Resettable for IN_INT_ENA_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_ena_ch5.rs b/esp32p4/src/h264_dma/in_int_ena_ch5.rs new file mode 100644 index 0000000000..8d034744ed --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_ena_ch5.rs @@ -0,0 +1,148 @@ +#[doc = "Register `IN_INT_ENA_CH5` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_ENA_CH5` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH5_INT_ENA` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH5_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH5_INT_ENA` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH5_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH5_INT_ENA` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH5_INT_ENA_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH5_INT_ENA` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH5_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH5_INT_ENA` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH5_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH5_INT_ENA` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH5_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH5_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH5_INT_ENA_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH5_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH5_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FETCH_MB_COL_CNT_OVF_CH5_INT_ENA` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_R = crate::BitReader; +#[doc = "Field `FETCH_MB_COL_CNT_OVF_CH5_INT_ENA` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch5_int_ena(&self) -> IN_DONE_CH5_INT_ENA_R { + IN_DONE_CH5_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch5_int_ena(&self) -> IN_SUC_EOF_CH5_INT_ENA_R { + IN_SUC_EOF_CH5_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch5_int_ena(&self) -> INFIFO_OVF_L1_CH5_INT_ENA_R { + INFIFO_OVF_L1_CH5_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch5_int_ena(&self) -> INFIFO_UDF_L1_CH5_INT_ENA_R { + INFIFO_UDF_L1_CH5_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn fetch_mb_col_cnt_ovf_ch5_int_ena(&self) -> FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_R { + FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ENA_CH5") + .field( + "in_done_ch5_int_ena", + &format_args!("{}", self.in_done_ch5_int_ena().bit()), + ) + .field( + "in_suc_eof_ch5_int_ena", + &format_args!("{}", self.in_suc_eof_ch5_int_ena().bit()), + ) + .field( + "infifo_ovf_l1_ch5_int_ena", + &format_args!("{}", self.infifo_ovf_l1_ch5_int_ena().bit()), + ) + .field( + "infifo_udf_l1_ch5_int_ena", + &format_args!("{}", self.infifo_udf_l1_ch5_int_ena().bit()), + ) + .field( + "fetch_mb_col_cnt_ovf_ch5_int_ena", + &format_args!("{}", self.fetch_mb_col_cnt_ovf_ch5_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_done_ch5_int_ena(&mut self) -> IN_DONE_CH5_INT_ENA_W { + IN_DONE_CH5_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch5_int_ena(&mut self) -> IN_SUC_EOF_CH5_INT_ENA_W { + IN_SUC_EOF_CH5_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch5_int_ena( + &mut self, + ) -> INFIFO_OVF_L1_CH5_INT_ENA_W { + INFIFO_OVF_L1_CH5_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch5_int_ena( + &mut self, + ) -> INFIFO_UDF_L1_CH5_INT_ENA_W { + INFIFO_UDF_L1_CH5_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn fetch_mb_col_cnt_ovf_ch5_int_ena( + &mut self, + ) -> FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_W { + FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH5 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_ena_ch5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_ena_ch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ENA_CH5_SPEC; +impl crate::RegisterSpec for IN_INT_ENA_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_ena_ch5::R`](R) reader structure"] +impl crate::Readable for IN_INT_ENA_CH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_ena_ch5::W`](W) writer structure"] +impl crate::Writable for IN_INT_ENA_CH5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_ENA_CH5 to value 0"] +impl crate::Resettable for IN_INT_ENA_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_raw_ch0.rs b/esp32p4/src/h264_dma/in_int_raw_ch0.rs new file mode 100644 index 0000000000..7377ea8661 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_raw_ch0.rs @@ -0,0 +1,249 @@ +#[doc = "Register `IN_INT_RAW_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_RAW_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0."] +pub type IN_DONE_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0."] +pub type IN_DONE_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] +pub type IN_SUC_EOF_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] +pub type IN_SUC_EOF_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] +pub type IN_ERR_EOF_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] +pub type IN_ERR_EOF_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] +pub type IN_DSCR_ERR_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] +pub type IN_DSCR_ERR_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L2_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L2_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L2_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L2_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] +pub type IN_DSCR_EMPTY_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] +pub type IN_DSCR_EMPTY_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type IN_DSCR_TASK_OVF_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type IN_DSCR_TASK_OVF_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0."] + #[inline(always)] + pub fn in_done_ch0_int_raw(&self) -> IN_DONE_CH0_INT_RAW_R { + IN_DONE_CH0_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] + #[inline(always)] + pub fn in_suc_eof_ch0_int_raw(&self) -> IN_SUC_EOF_CH0_INT_RAW_R { + IN_SUC_EOF_CH0_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] + #[inline(always)] + pub fn in_err_eof_ch0_int_raw(&self) -> IN_ERR_EOF_CH0_INT_RAW_R { + IN_ERR_EOF_CH0_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] + #[inline(always)] + pub fn in_dscr_err_ch0_int_raw(&self) -> IN_DSCR_ERR_CH0_INT_RAW_R { + IN_DSCR_ERR_CH0_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + pub fn infifo_ovf_l1_ch0_int_raw(&self) -> INFIFO_OVF_L1_CH0_INT_RAW_R { + INFIFO_OVF_L1_CH0_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn infifo_udf_l1_ch0_int_raw(&self) -> INFIFO_UDF_L1_CH0_INT_RAW_R { + INFIFO_UDF_L1_CH0_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + pub fn infifo_ovf_l2_ch0_int_raw(&self) -> INFIFO_OVF_L2_CH0_INT_RAW_R { + INFIFO_OVF_L2_CH0_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn infifo_udf_l2_ch0_int_raw(&self) -> INFIFO_UDF_L2_CH0_INT_RAW_R { + INFIFO_UDF_L2_CH0_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] + #[inline(always)] + pub fn in_dscr_empty_ch0_int_raw(&self) -> IN_DSCR_EMPTY_CH0_INT_RAW_R { + IN_DSCR_EMPTY_CH0_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch0_int_raw(&self) -> IN_DSCR_TASK_OVF_CH0_INT_RAW_R { + IN_DSCR_TASK_OVF_CH0_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_RAW_CH0") + .field( + "in_done_ch0_int_raw", + &format_args!("{}", self.in_done_ch0_int_raw().bit()), + ) + .field( + "in_suc_eof_ch0_int_raw", + &format_args!("{}", self.in_suc_eof_ch0_int_raw().bit()), + ) + .field( + "in_err_eof_ch0_int_raw", + &format_args!("{}", self.in_err_eof_ch0_int_raw().bit()), + ) + .field( + "in_dscr_err_ch0_int_raw", + &format_args!("{}", self.in_dscr_err_ch0_int_raw().bit()), + ) + .field( + "infifo_ovf_l1_ch0_int_raw", + &format_args!("{}", self.infifo_ovf_l1_ch0_int_raw().bit()), + ) + .field( + "infifo_udf_l1_ch0_int_raw", + &format_args!("{}", self.infifo_udf_l1_ch0_int_raw().bit()), + ) + .field( + "infifo_ovf_l2_ch0_int_raw", + &format_args!("{}", self.infifo_ovf_l2_ch0_int_raw().bit()), + ) + .field( + "infifo_udf_l2_ch0_int_raw", + &format_args!("{}", self.infifo_udf_l2_ch0_int_raw().bit()), + ) + .field( + "in_dscr_empty_ch0_int_raw", + &format_args!("{}", self.in_dscr_empty_ch0_int_raw().bit()), + ) + .field( + "in_dscr_task_ovf_ch0_int_raw", + &format_args!("{}", self.in_dscr_task_ovf_ch0_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0."] + #[inline(always)] + #[must_use] + pub fn in_done_ch0_int_raw(&mut self) -> IN_DONE_CH0_INT_RAW_W { + IN_DONE_CH0_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch0_int_raw(&mut self) -> IN_SUC_EOF_CH0_INT_RAW_W { + IN_SUC_EOF_CH0_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch0_int_raw(&mut self) -> IN_ERR_EOF_CH0_INT_RAW_W { + IN_ERR_EOF_CH0_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch0_int_raw(&mut self) -> IN_DSCR_ERR_CH0_INT_RAW_W { + IN_DSCR_ERR_CH0_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch0_int_raw( + &mut self, + ) -> INFIFO_OVF_L1_CH0_INT_RAW_W { + INFIFO_OVF_L1_CH0_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch0_int_raw( + &mut self, + ) -> INFIFO_UDF_L1_CH0_INT_RAW_W { + INFIFO_UDF_L1_CH0_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch0_int_raw( + &mut self, + ) -> INFIFO_OVF_L2_CH0_INT_RAW_W { + INFIFO_OVF_L2_CH0_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch0_int_raw( + &mut self, + ) -> INFIFO_UDF_L2_CH0_INT_RAW_W { + INFIFO_UDF_L2_CH0_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch0_int_raw( + &mut self, + ) -> IN_DSCR_EMPTY_CH0_INT_RAW_W { + IN_DSCR_EMPTY_CH0_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch0_int_raw( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH0_INT_RAW_W { + IN_DSCR_TASK_OVF_CH0_INT_RAW_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH0 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_RAW_CH0_SPEC; +impl crate::RegisterSpec for IN_INT_RAW_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_raw_ch0::R`](R) reader structure"] +impl crate::Readable for IN_INT_RAW_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_raw_ch0::W`](W) writer structure"] +impl crate::Writable for IN_INT_RAW_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_RAW_CH0 to value 0"] +impl crate::Resettable for IN_INT_RAW_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_raw_ch1.rs b/esp32p4/src/h264_dma/in_int_raw_ch1.rs new file mode 100644 index 0000000000..b62f8541cc --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_raw_ch1.rs @@ -0,0 +1,249 @@ +#[doc = "Register `IN_INT_RAW_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_RAW_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] +pub type IN_DONE_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] +pub type IN_DONE_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] +pub type IN_SUC_EOF_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] +pub type IN_SUC_EOF_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] +pub type IN_ERR_EOF_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] +pub type IN_ERR_EOF_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] +pub type IN_DSCR_ERR_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] +pub type IN_DSCR_ERR_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH1_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH1_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH1_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH1_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH1_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L2_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH1_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L2_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH1_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L2_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH1_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L2_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] +pub type IN_DSCR_EMPTY_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] +pub type IN_DSCR_EMPTY_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type IN_DSCR_TASK_OVF_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type IN_DSCR_TASK_OVF_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] + #[inline(always)] + pub fn in_done_ch1_int_raw(&self) -> IN_DONE_CH1_INT_RAW_R { + IN_DONE_CH1_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] + #[inline(always)] + pub fn in_suc_eof_ch1_int_raw(&self) -> IN_SUC_EOF_CH1_INT_RAW_R { + IN_SUC_EOF_CH1_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] + #[inline(always)] + pub fn in_err_eof_ch1_int_raw(&self) -> IN_ERR_EOF_CH1_INT_RAW_R { + IN_ERR_EOF_CH1_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] + #[inline(always)] + pub fn in_dscr_err_ch1_int_raw(&self) -> IN_DSCR_ERR_CH1_INT_RAW_R { + IN_DSCR_ERR_CH1_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + pub fn infifo_ovf_l1_ch1_int_raw(&self) -> INFIFO_OVF_L1_CH1_INT_RAW_R { + INFIFO_OVF_L1_CH1_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn infifo_udf_l1_ch1_int_raw(&self) -> INFIFO_UDF_L1_CH1_INT_RAW_R { + INFIFO_UDF_L1_CH1_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + pub fn infifo_ovf_l2_ch1_int_raw(&self) -> INFIFO_OVF_L2_CH1_INT_RAW_R { + INFIFO_OVF_L2_CH1_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn infifo_udf_l2_ch1_int_raw(&self) -> INFIFO_UDF_L2_CH1_INT_RAW_R { + INFIFO_UDF_L2_CH1_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] + #[inline(always)] + pub fn in_dscr_empty_ch1_int_raw(&self) -> IN_DSCR_EMPTY_CH1_INT_RAW_R { + IN_DSCR_EMPTY_CH1_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch1_int_raw(&self) -> IN_DSCR_TASK_OVF_CH1_INT_RAW_R { + IN_DSCR_TASK_OVF_CH1_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_RAW_CH1") + .field( + "in_done_ch1_int_raw", + &format_args!("{}", self.in_done_ch1_int_raw().bit()), + ) + .field( + "in_suc_eof_ch1_int_raw", + &format_args!("{}", self.in_suc_eof_ch1_int_raw().bit()), + ) + .field( + "in_err_eof_ch1_int_raw", + &format_args!("{}", self.in_err_eof_ch1_int_raw().bit()), + ) + .field( + "in_dscr_err_ch1_int_raw", + &format_args!("{}", self.in_dscr_err_ch1_int_raw().bit()), + ) + .field( + "infifo_ovf_l1_ch1_int_raw", + &format_args!("{}", self.infifo_ovf_l1_ch1_int_raw().bit()), + ) + .field( + "infifo_udf_l1_ch1_int_raw", + &format_args!("{}", self.infifo_udf_l1_ch1_int_raw().bit()), + ) + .field( + "infifo_ovf_l2_ch1_int_raw", + &format_args!("{}", self.infifo_ovf_l2_ch1_int_raw().bit()), + ) + .field( + "infifo_udf_l2_ch1_int_raw", + &format_args!("{}", self.infifo_udf_l2_ch1_int_raw().bit()), + ) + .field( + "in_dscr_empty_ch1_int_raw", + &format_args!("{}", self.in_dscr_empty_ch1_int_raw().bit()), + ) + .field( + "in_dscr_task_ovf_ch1_int_raw", + &format_args!("{}", self.in_dscr_task_ovf_ch1_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_done_ch1_int_raw(&mut self) -> IN_DONE_CH1_INT_RAW_W { + IN_DONE_CH1_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch1_int_raw(&mut self) -> IN_SUC_EOF_CH1_INT_RAW_W { + IN_SUC_EOF_CH1_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch1_int_raw(&mut self) -> IN_ERR_EOF_CH1_INT_RAW_W { + IN_ERR_EOF_CH1_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch1_int_raw(&mut self) -> IN_DSCR_ERR_CH1_INT_RAW_W { + IN_DSCR_ERR_CH1_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch1_int_raw( + &mut self, + ) -> INFIFO_OVF_L1_CH1_INT_RAW_W { + INFIFO_OVF_L1_CH1_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch1_int_raw( + &mut self, + ) -> INFIFO_UDF_L1_CH1_INT_RAW_W { + INFIFO_UDF_L1_CH1_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch1_int_raw( + &mut self, + ) -> INFIFO_OVF_L2_CH1_INT_RAW_W { + INFIFO_OVF_L2_CH1_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch1_int_raw( + &mut self, + ) -> INFIFO_UDF_L2_CH1_INT_RAW_W { + INFIFO_UDF_L2_CH1_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch1_int_raw( + &mut self, + ) -> IN_DSCR_EMPTY_CH1_INT_RAW_W { + IN_DSCR_EMPTY_CH1_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch1_int_raw( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH1_INT_RAW_W { + IN_DSCR_TASK_OVF_CH1_INT_RAW_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH1 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_RAW_CH1_SPEC; +impl crate::RegisterSpec for IN_INT_RAW_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_raw_ch1::R`](R) reader structure"] +impl crate::Readable for IN_INT_RAW_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_raw_ch1::W`](W) writer structure"] +impl crate::Writable for IN_INT_RAW_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_RAW_CH1 to value 0"] +impl crate::Resettable for IN_INT_RAW_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_raw_ch2.rs b/esp32p4/src/h264_dma/in_int_raw_ch2.rs new file mode 100644 index 0000000000..46badfd0c1 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_raw_ch2.rs @@ -0,0 +1,249 @@ +#[doc = "Register `IN_INT_RAW_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_RAW_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] +pub type IN_DONE_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] +pub type IN_DONE_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] +pub type IN_SUC_EOF_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] +pub type IN_SUC_EOF_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] +pub type IN_ERR_EOF_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] +pub type IN_ERR_EOF_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] +pub type IN_DSCR_ERR_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] +pub type IN_DSCR_ERR_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH2_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH2_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH2_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH2_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH2_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L2_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH2_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L2_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH2_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L2_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH2_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L2_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] +pub type IN_DSCR_EMPTY_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] +pub type IN_DSCR_EMPTY_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type IN_DSCR_TASK_OVF_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type IN_DSCR_TASK_OVF_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] + #[inline(always)] + pub fn in_done_ch2_int_raw(&self) -> IN_DONE_CH2_INT_RAW_R { + IN_DONE_CH2_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] + #[inline(always)] + pub fn in_suc_eof_ch2_int_raw(&self) -> IN_SUC_EOF_CH2_INT_RAW_R { + IN_SUC_EOF_CH2_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] + #[inline(always)] + pub fn in_err_eof_ch2_int_raw(&self) -> IN_ERR_EOF_CH2_INT_RAW_R { + IN_ERR_EOF_CH2_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] + #[inline(always)] + pub fn in_dscr_err_ch2_int_raw(&self) -> IN_DSCR_ERR_CH2_INT_RAW_R { + IN_DSCR_ERR_CH2_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + pub fn infifo_ovf_l1_ch2_int_raw(&self) -> INFIFO_OVF_L1_CH2_INT_RAW_R { + INFIFO_OVF_L1_CH2_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn infifo_udf_l1_ch2_int_raw(&self) -> INFIFO_UDF_L1_CH2_INT_RAW_R { + INFIFO_UDF_L1_CH2_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + pub fn infifo_ovf_l2_ch2_int_raw(&self) -> INFIFO_OVF_L2_CH2_INT_RAW_R { + INFIFO_OVF_L2_CH2_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn infifo_udf_l2_ch2_int_raw(&self) -> INFIFO_UDF_L2_CH2_INT_RAW_R { + INFIFO_UDF_L2_CH2_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] + #[inline(always)] + pub fn in_dscr_empty_ch2_int_raw(&self) -> IN_DSCR_EMPTY_CH2_INT_RAW_R { + IN_DSCR_EMPTY_CH2_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch2_int_raw(&self) -> IN_DSCR_TASK_OVF_CH2_INT_RAW_R { + IN_DSCR_TASK_OVF_CH2_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_RAW_CH2") + .field( + "in_done_ch2_int_raw", + &format_args!("{}", self.in_done_ch2_int_raw().bit()), + ) + .field( + "in_suc_eof_ch2_int_raw", + &format_args!("{}", self.in_suc_eof_ch2_int_raw().bit()), + ) + .field( + "in_err_eof_ch2_int_raw", + &format_args!("{}", self.in_err_eof_ch2_int_raw().bit()), + ) + .field( + "in_dscr_err_ch2_int_raw", + &format_args!("{}", self.in_dscr_err_ch2_int_raw().bit()), + ) + .field( + "infifo_ovf_l1_ch2_int_raw", + &format_args!("{}", self.infifo_ovf_l1_ch2_int_raw().bit()), + ) + .field( + "infifo_udf_l1_ch2_int_raw", + &format_args!("{}", self.infifo_udf_l1_ch2_int_raw().bit()), + ) + .field( + "infifo_ovf_l2_ch2_int_raw", + &format_args!("{}", self.infifo_ovf_l2_ch2_int_raw().bit()), + ) + .field( + "infifo_udf_l2_ch2_int_raw", + &format_args!("{}", self.infifo_udf_l2_ch2_int_raw().bit()), + ) + .field( + "in_dscr_empty_ch2_int_raw", + &format_args!("{}", self.in_dscr_empty_ch2_int_raw().bit()), + ) + .field( + "in_dscr_task_ovf_ch2_int_raw", + &format_args!("{}", self.in_dscr_task_ovf_ch2_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_done_ch2_int_raw(&mut self) -> IN_DONE_CH2_INT_RAW_W { + IN_DONE_CH2_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch2_int_raw(&mut self) -> IN_SUC_EOF_CH2_INT_RAW_W { + IN_SUC_EOF_CH2_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch2_int_raw(&mut self) -> IN_ERR_EOF_CH2_INT_RAW_W { + IN_ERR_EOF_CH2_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch2_int_raw(&mut self) -> IN_DSCR_ERR_CH2_INT_RAW_W { + IN_DSCR_ERR_CH2_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch2_int_raw( + &mut self, + ) -> INFIFO_OVF_L1_CH2_INT_RAW_W { + INFIFO_OVF_L1_CH2_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch2_int_raw( + &mut self, + ) -> INFIFO_UDF_L1_CH2_INT_RAW_W { + INFIFO_UDF_L1_CH2_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch2_int_raw( + &mut self, + ) -> INFIFO_OVF_L2_CH2_INT_RAW_W { + INFIFO_OVF_L2_CH2_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch2_int_raw( + &mut self, + ) -> INFIFO_UDF_L2_CH2_INT_RAW_W { + INFIFO_UDF_L2_CH2_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch2_int_raw( + &mut self, + ) -> IN_DSCR_EMPTY_CH2_INT_RAW_W { + IN_DSCR_EMPTY_CH2_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch2_int_raw( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH2_INT_RAW_W { + IN_DSCR_TASK_OVF_CH2_INT_RAW_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH2 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_RAW_CH2_SPEC; +impl crate::RegisterSpec for IN_INT_RAW_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_raw_ch2::R`](R) reader structure"] +impl crate::Readable for IN_INT_RAW_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_raw_ch2::W`](W) writer structure"] +impl crate::Writable for IN_INT_RAW_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_RAW_CH2 to value 0"] +impl crate::Resettable for IN_INT_RAW_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_raw_ch3.rs b/esp32p4/src/h264_dma/in_int_raw_ch3.rs new file mode 100644 index 0000000000..d33b47b107 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_raw_ch3.rs @@ -0,0 +1,249 @@ +#[doc = "Register `IN_INT_RAW_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_RAW_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] +pub type IN_DONE_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] +pub type IN_DONE_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] +pub type IN_SUC_EOF_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] +pub type IN_SUC_EOF_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] +pub type IN_ERR_EOF_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] +pub type IN_ERR_EOF_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] +pub type IN_DSCR_ERR_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] +pub type IN_DSCR_ERR_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH3_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH3_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH3_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH3_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH3_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L2_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH3_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L2_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH3_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L2_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH3_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L2_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] +pub type IN_DSCR_EMPTY_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] +pub type IN_DSCR_EMPTY_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type IN_DSCR_TASK_OVF_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type IN_DSCR_TASK_OVF_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] + #[inline(always)] + pub fn in_done_ch3_int_raw(&self) -> IN_DONE_CH3_INT_RAW_R { + IN_DONE_CH3_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] + #[inline(always)] + pub fn in_suc_eof_ch3_int_raw(&self) -> IN_SUC_EOF_CH3_INT_RAW_R { + IN_SUC_EOF_CH3_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] + #[inline(always)] + pub fn in_err_eof_ch3_int_raw(&self) -> IN_ERR_EOF_CH3_INT_RAW_R { + IN_ERR_EOF_CH3_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] + #[inline(always)] + pub fn in_dscr_err_ch3_int_raw(&self) -> IN_DSCR_ERR_CH3_INT_RAW_R { + IN_DSCR_ERR_CH3_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + pub fn infifo_ovf_l1_ch3_int_raw(&self) -> INFIFO_OVF_L1_CH3_INT_RAW_R { + INFIFO_OVF_L1_CH3_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn infifo_udf_l1_ch3_int_raw(&self) -> INFIFO_UDF_L1_CH3_INT_RAW_R { + INFIFO_UDF_L1_CH3_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + pub fn infifo_ovf_l2_ch3_int_raw(&self) -> INFIFO_OVF_L2_CH3_INT_RAW_R { + INFIFO_OVF_L2_CH3_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn infifo_udf_l2_ch3_int_raw(&self) -> INFIFO_UDF_L2_CH3_INT_RAW_R { + INFIFO_UDF_L2_CH3_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] + #[inline(always)] + pub fn in_dscr_empty_ch3_int_raw(&self) -> IN_DSCR_EMPTY_CH3_INT_RAW_R { + IN_DSCR_EMPTY_CH3_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch3_int_raw(&self) -> IN_DSCR_TASK_OVF_CH3_INT_RAW_R { + IN_DSCR_TASK_OVF_CH3_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_RAW_CH3") + .field( + "in_done_ch3_int_raw", + &format_args!("{}", self.in_done_ch3_int_raw().bit()), + ) + .field( + "in_suc_eof_ch3_int_raw", + &format_args!("{}", self.in_suc_eof_ch3_int_raw().bit()), + ) + .field( + "in_err_eof_ch3_int_raw", + &format_args!("{}", self.in_err_eof_ch3_int_raw().bit()), + ) + .field( + "in_dscr_err_ch3_int_raw", + &format_args!("{}", self.in_dscr_err_ch3_int_raw().bit()), + ) + .field( + "infifo_ovf_l1_ch3_int_raw", + &format_args!("{}", self.infifo_ovf_l1_ch3_int_raw().bit()), + ) + .field( + "infifo_udf_l1_ch3_int_raw", + &format_args!("{}", self.infifo_udf_l1_ch3_int_raw().bit()), + ) + .field( + "infifo_ovf_l2_ch3_int_raw", + &format_args!("{}", self.infifo_ovf_l2_ch3_int_raw().bit()), + ) + .field( + "infifo_udf_l2_ch3_int_raw", + &format_args!("{}", self.infifo_udf_l2_ch3_int_raw().bit()), + ) + .field( + "in_dscr_empty_ch3_int_raw", + &format_args!("{}", self.in_dscr_empty_ch3_int_raw().bit()), + ) + .field( + "in_dscr_task_ovf_ch3_int_raw", + &format_args!("{}", self.in_dscr_task_ovf_ch3_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_done_ch3_int_raw(&mut self) -> IN_DONE_CH3_INT_RAW_W { + IN_DONE_CH3_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch3_int_raw(&mut self) -> IN_SUC_EOF_CH3_INT_RAW_W { + IN_SUC_EOF_CH3_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch3_int_raw(&mut self) -> IN_ERR_EOF_CH3_INT_RAW_W { + IN_ERR_EOF_CH3_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch3_int_raw(&mut self) -> IN_DSCR_ERR_CH3_INT_RAW_W { + IN_DSCR_ERR_CH3_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch3_int_raw( + &mut self, + ) -> INFIFO_OVF_L1_CH3_INT_RAW_W { + INFIFO_OVF_L1_CH3_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch3_int_raw( + &mut self, + ) -> INFIFO_UDF_L1_CH3_INT_RAW_W { + INFIFO_UDF_L1_CH3_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch3_int_raw( + &mut self, + ) -> INFIFO_OVF_L2_CH3_INT_RAW_W { + INFIFO_OVF_L2_CH3_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch3_int_raw( + &mut self, + ) -> INFIFO_UDF_L2_CH3_INT_RAW_W { + INFIFO_UDF_L2_CH3_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch3_int_raw( + &mut self, + ) -> IN_DSCR_EMPTY_CH3_INT_RAW_W { + IN_DSCR_EMPTY_CH3_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch3_int_raw( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH3_INT_RAW_W { + IN_DSCR_TASK_OVF_CH3_INT_RAW_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH3 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_RAW_CH3_SPEC; +impl crate::RegisterSpec for IN_INT_RAW_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_raw_ch3::R`](R) reader structure"] +impl crate::Readable for IN_INT_RAW_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_raw_ch3::W`](W) writer structure"] +impl crate::Writable for IN_INT_RAW_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_RAW_CH3 to value 0"] +impl crate::Resettable for IN_INT_RAW_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_raw_ch4.rs b/esp32p4/src/h264_dma/in_int_raw_ch4.rs new file mode 100644 index 0000000000..1f16127934 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_raw_ch4.rs @@ -0,0 +1,249 @@ +#[doc = "Register `IN_INT_RAW_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_RAW_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] +pub type IN_DONE_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] +pub type IN_DONE_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] +pub type IN_SUC_EOF_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] +pub type IN_SUC_EOF_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_ERR_EOF_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] +pub type IN_ERR_EOF_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] +pub type IN_ERR_EOF_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_ERR_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] +pub type IN_DSCR_ERR_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] +pub type IN_DSCR_ERR_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH4_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH4_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH4_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH4_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L2_CH4_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L2_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH4_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L2_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L2_CH4_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L2_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH4_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L2_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_EMPTY_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] +pub type IN_DSCR_EMPTY_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] +pub type IN_DSCR_EMPTY_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_DSCR_TASK_OVF_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type IN_DSCR_TASK_OVF_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type IN_DSCR_TASK_OVF_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] + #[inline(always)] + pub fn in_done_ch4_int_raw(&self) -> IN_DONE_CH4_INT_RAW_R { + IN_DONE_CH4_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] + #[inline(always)] + pub fn in_suc_eof_ch4_int_raw(&self) -> IN_SUC_EOF_CH4_INT_RAW_R { + IN_SUC_EOF_CH4_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] + #[inline(always)] + pub fn in_err_eof_ch4_int_raw(&self) -> IN_ERR_EOF_CH4_INT_RAW_R { + IN_ERR_EOF_CH4_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] + #[inline(always)] + pub fn in_dscr_err_ch4_int_raw(&self) -> IN_DSCR_ERR_CH4_INT_RAW_R { + IN_DSCR_ERR_CH4_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + pub fn infifo_ovf_l1_ch4_int_raw(&self) -> INFIFO_OVF_L1_CH4_INT_RAW_R { + INFIFO_OVF_L1_CH4_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn infifo_udf_l1_ch4_int_raw(&self) -> INFIFO_UDF_L1_CH4_INT_RAW_R { + INFIFO_UDF_L1_CH4_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + pub fn infifo_ovf_l2_ch4_int_raw(&self) -> INFIFO_OVF_L2_CH4_INT_RAW_R { + INFIFO_OVF_L2_CH4_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn infifo_udf_l2_ch4_int_raw(&self) -> INFIFO_UDF_L2_CH4_INT_RAW_R { + INFIFO_UDF_L2_CH4_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] + #[inline(always)] + pub fn in_dscr_empty_ch4_int_raw(&self) -> IN_DSCR_EMPTY_CH4_INT_RAW_R { + IN_DSCR_EMPTY_CH4_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch4_int_raw(&self) -> IN_DSCR_TASK_OVF_CH4_INT_RAW_R { + IN_DSCR_TASK_OVF_CH4_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_RAW_CH4") + .field( + "in_done_ch4_int_raw", + &format_args!("{}", self.in_done_ch4_int_raw().bit()), + ) + .field( + "in_suc_eof_ch4_int_raw", + &format_args!("{}", self.in_suc_eof_ch4_int_raw().bit()), + ) + .field( + "in_err_eof_ch4_int_raw", + &format_args!("{}", self.in_err_eof_ch4_int_raw().bit()), + ) + .field( + "in_dscr_err_ch4_int_raw", + &format_args!("{}", self.in_dscr_err_ch4_int_raw().bit()), + ) + .field( + "infifo_ovf_l1_ch4_int_raw", + &format_args!("{}", self.infifo_ovf_l1_ch4_int_raw().bit()), + ) + .field( + "infifo_udf_l1_ch4_int_raw", + &format_args!("{}", self.infifo_udf_l1_ch4_int_raw().bit()), + ) + .field( + "infifo_ovf_l2_ch4_int_raw", + &format_args!("{}", self.infifo_ovf_l2_ch4_int_raw().bit()), + ) + .field( + "infifo_udf_l2_ch4_int_raw", + &format_args!("{}", self.infifo_udf_l2_ch4_int_raw().bit()), + ) + .field( + "in_dscr_empty_ch4_int_raw", + &format_args!("{}", self.in_dscr_empty_ch4_int_raw().bit()), + ) + .field( + "in_dscr_task_ovf_ch4_int_raw", + &format_args!("{}", self.in_dscr_task_ovf_ch4_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_done_ch4_int_raw(&mut self) -> IN_DONE_CH4_INT_RAW_W { + IN_DONE_CH4_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch4_int_raw(&mut self) -> IN_SUC_EOF_CH4_INT_RAW_W { + IN_SUC_EOF_CH4_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected"] + #[inline(always)] + #[must_use] + pub fn in_err_eof_ch4_int_raw(&mut self) -> IN_ERR_EOF_CH4_INT_RAW_W { + IN_ERR_EOF_CH4_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_dscr_err_ch4_int_raw(&mut self) -> IN_DSCR_ERR_CH4_INT_RAW_W { + IN_DSCR_ERR_CH4_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch4_int_raw( + &mut self, + ) -> INFIFO_OVF_L1_CH4_INT_RAW_W { + INFIFO_OVF_L1_CH4_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch4_int_raw( + &mut self, + ) -> INFIFO_UDF_L1_CH4_INT_RAW_W { + INFIFO_UDF_L1_CH4_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l2_ch4_int_raw( + &mut self, + ) -> INFIFO_OVF_L2_CH4_INT_RAW_W { + INFIFO_OVF_L2_CH4_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l2_ch4_int_raw( + &mut self, + ) -> INFIFO_UDF_L2_CH4_INT_RAW_W { + INFIFO_UDF_L2_CH4_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data."] + #[inline(always)] + #[must_use] + pub fn in_dscr_empty_ch4_int_raw( + &mut self, + ) -> IN_DSCR_EMPTY_CH4_INT_RAW_W { + IN_DSCR_EMPTY_CH4_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn in_dscr_task_ovf_ch4_int_raw( + &mut self, + ) -> IN_DSCR_TASK_OVF_CH4_INT_RAW_W { + IN_DSCR_TASK_OVF_CH4_INT_RAW_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH4 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_RAW_CH4_SPEC; +impl crate::RegisterSpec for IN_INT_RAW_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_raw_ch4::R`](R) reader structure"] +impl crate::Readable for IN_INT_RAW_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_raw_ch4::W`](W) writer structure"] +impl crate::Writable for IN_INT_RAW_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_RAW_CH4 to value 0"] +impl crate::Resettable for IN_INT_RAW_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_raw_ch5.rs b/esp32p4/src/h264_dma/in_int_raw_ch5.rs new file mode 100644 index 0000000000..845e0ee3b7 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_raw_ch5.rs @@ -0,0 +1,148 @@ +#[doc = "Register `IN_INT_RAW_CH5` reader"] +pub type R = crate::R; +#[doc = "Register `IN_INT_RAW_CH5` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DONE_CH5_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] +pub type IN_DONE_CH5_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_DONE_CH5_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] +pub type IN_DONE_CH5_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SUC_EOF_CH5_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] +pub type IN_SUC_EOF_CH5_INT_RAW_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH5_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] +pub type IN_SUC_EOF_CH5_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_OVF_L1_CH5_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH5_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH5_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] +pub type INFIFO_OVF_L1_CH5_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INFIFO_UDF_L1_CH5_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH5_INT_RAW_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH5_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type INFIFO_UDF_L1_CH5_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FETCH_MB_COL_CNT_OVF_CH5_INT_RAW` reader - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_R = crate::BitReader; +#[doc = "Field `FETCH_MB_COL_CNT_OVF_CH5_INT_RAW` writer - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] +pub type FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] + #[inline(always)] + pub fn in_done_ch5_int_raw(&self) -> IN_DONE_CH5_INT_RAW_R { + IN_DONE_CH5_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] + #[inline(always)] + pub fn in_suc_eof_ch5_int_raw(&self) -> IN_SUC_EOF_CH5_INT_RAW_R { + IN_SUC_EOF_CH5_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + pub fn infifo_ovf_l1_ch5_int_raw(&self) -> INFIFO_OVF_L1_CH5_INT_RAW_R { + INFIFO_OVF_L1_CH5_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn infifo_udf_l1_ch5_int_raw(&self) -> INFIFO_UDF_L1_CH5_INT_RAW_R { + INFIFO_UDF_L1_CH5_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + pub fn fetch_mb_col_cnt_ovf_ch5_int_raw(&self) -> FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_R { + FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_RAW_CH5") + .field( + "in_done_ch5_int_raw", + &format_args!("{}", self.in_done_ch5_int_raw().bit()), + ) + .field( + "in_suc_eof_ch5_int_raw", + &format_args!("{}", self.in_suc_eof_ch5_int_raw().bit()), + ) + .field( + "infifo_ovf_l1_ch5_int_raw", + &format_args!("{}", self.infifo_ovf_l1_ch5_int_raw().bit()), + ) + .field( + "infifo_udf_l1_ch5_int_raw", + &format_args!("{}", self.infifo_udf_l1_ch5_int_raw().bit()), + ) + .field( + "fetch_mb_col_cnt_ovf_ch5_int_raw", + &format_args!("{}", self.fetch_mb_col_cnt_ovf_ch5_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_done_ch5_int_raw(&mut self) -> IN_DONE_CH5_INT_RAW_W { + IN_DONE_CH5_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1."] + #[inline(always)] + #[must_use] + pub fn in_suc_eof_ch5_int_raw(&mut self) -> IN_SUC_EOF_CH5_INT_RAW_W { + IN_SUC_EOF_CH5_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - This raw interrupt bit turns to high level when fifo of Rx channel is overflow."] + #[inline(always)] + #[must_use] + pub fn infifo_ovf_l1_ch5_int_raw( + &mut self, + ) -> INFIFO_OVF_L1_CH5_INT_RAW_W { + INFIFO_OVF_L1_CH5_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn infifo_udf_l1_ch5_int_raw( + &mut self, + ) -> INFIFO_UDF_L1_CH5_INT_RAW_W { + INFIFO_UDF_L1_CH5_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - This raw interrupt bit turns to high level when fifo of Rx channel is underflow."] + #[inline(always)] + #[must_use] + pub fn fetch_mb_col_cnt_ovf_ch5_int_raw( + &mut self, + ) -> FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_W { + FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH5 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_raw_ch5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_int_raw_ch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_RAW_CH5_SPEC; +impl crate::RegisterSpec for IN_INT_RAW_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_raw_ch5::R`](R) reader structure"] +impl crate::Readable for IN_INT_RAW_CH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_int_raw_ch5::W`](W) writer structure"] +impl crate::Writable for IN_INT_RAW_CH5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_INT_RAW_CH5 to value 0"] +impl crate::Resettable for IN_INT_RAW_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_st_ch0.rs b/esp32p4/src/h264_dma/in_int_st_ch0.rs new file mode 100644 index 0000000000..82d2755150 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_st_ch0.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IN_INT_ST_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE_CH0_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH0_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH0_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH0_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH0_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH0_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH0_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH0_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH0_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch0_int_st(&self) -> IN_DONE_CH0_INT_ST_R { + IN_DONE_CH0_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch0_int_st(&self) -> IN_SUC_EOF_CH0_INT_ST_R { + IN_SUC_EOF_CH0_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch0_int_st(&self) -> IN_ERR_EOF_CH0_INT_ST_R { + IN_ERR_EOF_CH0_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch0_int_st(&self) -> IN_DSCR_ERR_CH0_INT_ST_R { + IN_DSCR_ERR_CH0_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch0_int_st(&self) -> INFIFO_OVF_L1_CH0_INT_ST_R { + INFIFO_OVF_L1_CH0_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch0_int_st(&self) -> INFIFO_UDF_L1_CH0_INT_ST_R { + INFIFO_UDF_L1_CH0_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l2_ch0_int_st(&self) -> INFIFO_OVF_L2_CH0_INT_ST_R { + INFIFO_OVF_L2_CH0_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l2_ch0_int_st(&self) -> INFIFO_UDF_L2_CH0_INT_ST_R { + INFIFO_UDF_L2_CH0_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch0_int_st(&self) -> IN_DSCR_EMPTY_CH0_INT_ST_R { + IN_DSCR_EMPTY_CH0_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch0_int_st(&self) -> IN_DSCR_TASK_OVF_CH0_INT_ST_R { + IN_DSCR_TASK_OVF_CH0_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ST_CH0") + .field( + "in_done_ch0_int_st", + &format_args!("{}", self.in_done_ch0_int_st().bit()), + ) + .field( + "in_suc_eof_ch0_int_st", + &format_args!("{}", self.in_suc_eof_ch0_int_st().bit()), + ) + .field( + "in_err_eof_ch0_int_st", + &format_args!("{}", self.in_err_eof_ch0_int_st().bit()), + ) + .field( + "in_dscr_err_ch0_int_st", + &format_args!("{}", self.in_dscr_err_ch0_int_st().bit()), + ) + .field( + "infifo_ovf_l1_ch0_int_st", + &format_args!("{}", self.infifo_ovf_l1_ch0_int_st().bit()), + ) + .field( + "infifo_udf_l1_ch0_int_st", + &format_args!("{}", self.infifo_udf_l1_ch0_int_st().bit()), + ) + .field( + "infifo_ovf_l2_ch0_int_st", + &format_args!("{}", self.infifo_ovf_l2_ch0_int_st().bit()), + ) + .field( + "infifo_udf_l2_ch0_int_st", + &format_args!("{}", self.infifo_udf_l2_ch0_int_st().bit()), + ) + .field( + "in_dscr_empty_ch0_int_st", + &format_args!("{}", self.in_dscr_empty_ch0_int_st().bit()), + ) + .field( + "in_dscr_task_ovf_ch0_int_st", + &format_args!("{}", self.in_dscr_task_ovf_ch0_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH0 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ST_CH0_SPEC; +impl crate::RegisterSpec for IN_INT_ST_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_st_ch0::R`](R) reader structure"] +impl crate::Readable for IN_INT_ST_CH0_SPEC {} +#[doc = "`reset()` method sets IN_INT_ST_CH0 to value 0"] +impl crate::Resettable for IN_INT_ST_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_st_ch1.rs b/esp32p4/src/h264_dma/in_int_st_ch1.rs new file mode 100644 index 0000000000..528342aa8d --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_st_ch1.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IN_INT_ST_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE_CH1_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH1_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH1_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH1_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH1_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH1_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH1_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH1_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH1_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH1_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH1_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch1_int_st(&self) -> IN_DONE_CH1_INT_ST_R { + IN_DONE_CH1_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch1_int_st(&self) -> IN_SUC_EOF_CH1_INT_ST_R { + IN_SUC_EOF_CH1_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch1_int_st(&self) -> IN_ERR_EOF_CH1_INT_ST_R { + IN_ERR_EOF_CH1_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch1_int_st(&self) -> IN_DSCR_ERR_CH1_INT_ST_R { + IN_DSCR_ERR_CH1_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch1_int_st(&self) -> INFIFO_OVF_L1_CH1_INT_ST_R { + INFIFO_OVF_L1_CH1_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch1_int_st(&self) -> INFIFO_UDF_L1_CH1_INT_ST_R { + INFIFO_UDF_L1_CH1_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l2_ch1_int_st(&self) -> INFIFO_OVF_L2_CH1_INT_ST_R { + INFIFO_OVF_L2_CH1_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l2_ch1_int_st(&self) -> INFIFO_UDF_L2_CH1_INT_ST_R { + INFIFO_UDF_L2_CH1_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch1_int_st(&self) -> IN_DSCR_EMPTY_CH1_INT_ST_R { + IN_DSCR_EMPTY_CH1_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch1_int_st(&self) -> IN_DSCR_TASK_OVF_CH1_INT_ST_R { + IN_DSCR_TASK_OVF_CH1_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ST_CH1") + .field( + "in_done_ch1_int_st", + &format_args!("{}", self.in_done_ch1_int_st().bit()), + ) + .field( + "in_suc_eof_ch1_int_st", + &format_args!("{}", self.in_suc_eof_ch1_int_st().bit()), + ) + .field( + "in_err_eof_ch1_int_st", + &format_args!("{}", self.in_err_eof_ch1_int_st().bit()), + ) + .field( + "in_dscr_err_ch1_int_st", + &format_args!("{}", self.in_dscr_err_ch1_int_st().bit()), + ) + .field( + "infifo_ovf_l1_ch1_int_st", + &format_args!("{}", self.infifo_ovf_l1_ch1_int_st().bit()), + ) + .field( + "infifo_udf_l1_ch1_int_st", + &format_args!("{}", self.infifo_udf_l1_ch1_int_st().bit()), + ) + .field( + "infifo_ovf_l2_ch1_int_st", + &format_args!("{}", self.infifo_ovf_l2_ch1_int_st().bit()), + ) + .field( + "infifo_udf_l2_ch1_int_st", + &format_args!("{}", self.infifo_udf_l2_ch1_int_st().bit()), + ) + .field( + "in_dscr_empty_ch1_int_st", + &format_args!("{}", self.in_dscr_empty_ch1_int_st().bit()), + ) + .field( + "in_dscr_task_ovf_ch1_int_st", + &format_args!("{}", self.in_dscr_task_ovf_ch1_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH1 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ST_CH1_SPEC; +impl crate::RegisterSpec for IN_INT_ST_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_st_ch1::R`](R) reader structure"] +impl crate::Readable for IN_INT_ST_CH1_SPEC {} +#[doc = "`reset()` method sets IN_INT_ST_CH1 to value 0"] +impl crate::Resettable for IN_INT_ST_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_st_ch2.rs b/esp32p4/src/h264_dma/in_int_st_ch2.rs new file mode 100644 index 0000000000..89273e55e2 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_st_ch2.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IN_INT_ST_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE_CH2_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH2_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH2_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH2_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH2_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH2_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH2_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH2_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH2_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH2_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH2_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch2_int_st(&self) -> IN_DONE_CH2_INT_ST_R { + IN_DONE_CH2_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch2_int_st(&self) -> IN_SUC_EOF_CH2_INT_ST_R { + IN_SUC_EOF_CH2_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch2_int_st(&self) -> IN_ERR_EOF_CH2_INT_ST_R { + IN_ERR_EOF_CH2_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch2_int_st(&self) -> IN_DSCR_ERR_CH2_INT_ST_R { + IN_DSCR_ERR_CH2_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch2_int_st(&self) -> INFIFO_OVF_L1_CH2_INT_ST_R { + INFIFO_OVF_L1_CH2_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch2_int_st(&self) -> INFIFO_UDF_L1_CH2_INT_ST_R { + INFIFO_UDF_L1_CH2_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l2_ch2_int_st(&self) -> INFIFO_OVF_L2_CH2_INT_ST_R { + INFIFO_OVF_L2_CH2_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l2_ch2_int_st(&self) -> INFIFO_UDF_L2_CH2_INT_ST_R { + INFIFO_UDF_L2_CH2_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch2_int_st(&self) -> IN_DSCR_EMPTY_CH2_INT_ST_R { + IN_DSCR_EMPTY_CH2_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch2_int_st(&self) -> IN_DSCR_TASK_OVF_CH2_INT_ST_R { + IN_DSCR_TASK_OVF_CH2_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ST_CH2") + .field( + "in_done_ch2_int_st", + &format_args!("{}", self.in_done_ch2_int_st().bit()), + ) + .field( + "in_suc_eof_ch2_int_st", + &format_args!("{}", self.in_suc_eof_ch2_int_st().bit()), + ) + .field( + "in_err_eof_ch2_int_st", + &format_args!("{}", self.in_err_eof_ch2_int_st().bit()), + ) + .field( + "in_dscr_err_ch2_int_st", + &format_args!("{}", self.in_dscr_err_ch2_int_st().bit()), + ) + .field( + "infifo_ovf_l1_ch2_int_st", + &format_args!("{}", self.infifo_ovf_l1_ch2_int_st().bit()), + ) + .field( + "infifo_udf_l1_ch2_int_st", + &format_args!("{}", self.infifo_udf_l1_ch2_int_st().bit()), + ) + .field( + "infifo_ovf_l2_ch2_int_st", + &format_args!("{}", self.infifo_ovf_l2_ch2_int_st().bit()), + ) + .field( + "infifo_udf_l2_ch2_int_st", + &format_args!("{}", self.infifo_udf_l2_ch2_int_st().bit()), + ) + .field( + "in_dscr_empty_ch2_int_st", + &format_args!("{}", self.in_dscr_empty_ch2_int_st().bit()), + ) + .field( + "in_dscr_task_ovf_ch2_int_st", + &format_args!("{}", self.in_dscr_task_ovf_ch2_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH2 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ST_CH2_SPEC; +impl crate::RegisterSpec for IN_INT_ST_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_st_ch2::R`](R) reader structure"] +impl crate::Readable for IN_INT_ST_CH2_SPEC {} +#[doc = "`reset()` method sets IN_INT_ST_CH2 to value 0"] +impl crate::Resettable for IN_INT_ST_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_st_ch3.rs b/esp32p4/src/h264_dma/in_int_st_ch3.rs new file mode 100644 index 0000000000..da3549fd27 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_st_ch3.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IN_INT_ST_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE_CH3_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH3_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH3_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH3_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH3_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH3_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH3_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH3_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH3_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH3_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH3_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch3_int_st(&self) -> IN_DONE_CH3_INT_ST_R { + IN_DONE_CH3_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch3_int_st(&self) -> IN_SUC_EOF_CH3_INT_ST_R { + IN_SUC_EOF_CH3_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch3_int_st(&self) -> IN_ERR_EOF_CH3_INT_ST_R { + IN_ERR_EOF_CH3_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch3_int_st(&self) -> IN_DSCR_ERR_CH3_INT_ST_R { + IN_DSCR_ERR_CH3_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch3_int_st(&self) -> INFIFO_OVF_L1_CH3_INT_ST_R { + INFIFO_OVF_L1_CH3_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch3_int_st(&self) -> INFIFO_UDF_L1_CH3_INT_ST_R { + INFIFO_UDF_L1_CH3_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l2_ch3_int_st(&self) -> INFIFO_OVF_L2_CH3_INT_ST_R { + INFIFO_OVF_L2_CH3_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l2_ch3_int_st(&self) -> INFIFO_UDF_L2_CH3_INT_ST_R { + INFIFO_UDF_L2_CH3_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch3_int_st(&self) -> IN_DSCR_EMPTY_CH3_INT_ST_R { + IN_DSCR_EMPTY_CH3_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch3_int_st(&self) -> IN_DSCR_TASK_OVF_CH3_INT_ST_R { + IN_DSCR_TASK_OVF_CH3_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ST_CH3") + .field( + "in_done_ch3_int_st", + &format_args!("{}", self.in_done_ch3_int_st().bit()), + ) + .field( + "in_suc_eof_ch3_int_st", + &format_args!("{}", self.in_suc_eof_ch3_int_st().bit()), + ) + .field( + "in_err_eof_ch3_int_st", + &format_args!("{}", self.in_err_eof_ch3_int_st().bit()), + ) + .field( + "in_dscr_err_ch3_int_st", + &format_args!("{}", self.in_dscr_err_ch3_int_st().bit()), + ) + .field( + "infifo_ovf_l1_ch3_int_st", + &format_args!("{}", self.infifo_ovf_l1_ch3_int_st().bit()), + ) + .field( + "infifo_udf_l1_ch3_int_st", + &format_args!("{}", self.infifo_udf_l1_ch3_int_st().bit()), + ) + .field( + "infifo_ovf_l2_ch3_int_st", + &format_args!("{}", self.infifo_ovf_l2_ch3_int_st().bit()), + ) + .field( + "infifo_udf_l2_ch3_int_st", + &format_args!("{}", self.infifo_udf_l2_ch3_int_st().bit()), + ) + .field( + "in_dscr_empty_ch3_int_st", + &format_args!("{}", self.in_dscr_empty_ch3_int_st().bit()), + ) + .field( + "in_dscr_task_ovf_ch3_int_st", + &format_args!("{}", self.in_dscr_task_ovf_ch3_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH3 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ST_CH3_SPEC; +impl crate::RegisterSpec for IN_INT_ST_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_st_ch3::R`](R) reader structure"] +impl crate::Readable for IN_INT_ST_CH3_SPEC {} +#[doc = "`reset()` method sets IN_INT_ST_CH3 to value 0"] +impl crate::Resettable for IN_INT_ST_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_st_ch4.rs b/esp32p4/src/h264_dma/in_int_st_ch4.rs new file mode 100644 index 0000000000..6f0446e706 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_st_ch4.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IN_INT_ST_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE_CH4_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH4_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_ERR_EOF_CH4_INT_ST` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] +pub type IN_ERR_EOF_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_ERR_CH4_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] +pub type IN_DSCR_ERR_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH4_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH4_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L2_CH4_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] +pub type INFIFO_OVF_L2_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L2_CH4_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] +pub type INFIFO_UDF_L2_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_EMPTY_CH4_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] +pub type IN_DSCR_EMPTY_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_DSCR_TASK_OVF_CH4_INT_ST` reader - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] +pub type IN_DSCR_TASK_OVF_CH4_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch4_int_st(&self) -> IN_DONE_CH4_INT_ST_R { + IN_DONE_CH4_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch4_int_st(&self) -> IN_SUC_EOF_CH4_INT_ST_R { + IN_SUC_EOF_CH4_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_err_eof_ch4_int_st(&self) -> IN_ERR_EOF_CH4_INT_ST_R { + IN_ERR_EOF_CH4_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_err_ch4_int_st(&self) -> IN_DSCR_ERR_CH4_INT_ST_R { + IN_DSCR_ERR_CH4_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch4_int_st(&self) -> INFIFO_OVF_L1_CH4_INT_ST_R { + INFIFO_OVF_L1_CH4_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch4_int_st(&self) -> INFIFO_UDF_L1_CH4_INT_ST_R { + INFIFO_UDF_L1_CH4_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l2_ch4_int_st(&self) -> INFIFO_OVF_L2_CH4_INT_ST_R { + INFIFO_OVF_L2_CH4_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l2_ch4_int_st(&self) -> INFIFO_UDF_L2_CH4_INT_ST_R { + INFIFO_UDF_L2_CH4_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_empty_ch4_int_st(&self) -> IN_DSCR_EMPTY_CH4_INT_ST_R { + IN_DSCR_EMPTY_CH4_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn in_dscr_task_ovf_ch4_int_st(&self) -> IN_DSCR_TASK_OVF_CH4_INT_ST_R { + IN_DSCR_TASK_OVF_CH4_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ST_CH4") + .field( + "in_done_ch4_int_st", + &format_args!("{}", self.in_done_ch4_int_st().bit()), + ) + .field( + "in_suc_eof_ch4_int_st", + &format_args!("{}", self.in_suc_eof_ch4_int_st().bit()), + ) + .field( + "in_err_eof_ch4_int_st", + &format_args!("{}", self.in_err_eof_ch4_int_st().bit()), + ) + .field( + "in_dscr_err_ch4_int_st", + &format_args!("{}", self.in_dscr_err_ch4_int_st().bit()), + ) + .field( + "infifo_ovf_l1_ch4_int_st", + &format_args!("{}", self.infifo_ovf_l1_ch4_int_st().bit()), + ) + .field( + "infifo_udf_l1_ch4_int_st", + &format_args!("{}", self.infifo_udf_l1_ch4_int_st().bit()), + ) + .field( + "infifo_ovf_l2_ch4_int_st", + &format_args!("{}", self.infifo_ovf_l2_ch4_int_st().bit()), + ) + .field( + "infifo_udf_l2_ch4_int_st", + &format_args!("{}", self.infifo_udf_l2_ch4_int_st().bit()), + ) + .field( + "in_dscr_empty_ch4_int_st", + &format_args!("{}", self.in_dscr_empty_ch4_int_st().bit()), + ) + .field( + "in_dscr_task_ovf_ch4_int_st", + &format_args!("{}", self.in_dscr_task_ovf_ch4_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH4 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ST_CH4_SPEC; +impl crate::RegisterSpec for IN_INT_ST_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_st_ch4::R`](R) reader structure"] +impl crate::Readable for IN_INT_ST_CH4_SPEC {} +#[doc = "`reset()` method sets IN_INT_ST_CH4 to value 0"] +impl crate::Resettable for IN_INT_ST_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_int_st_ch5.rs b/esp32p4/src/h264_dma/in_int_st_ch5.rs new file mode 100644 index 0000000000..91706d5380 --- /dev/null +++ b/esp32p4/src/h264_dma/in_int_st_ch5.rs @@ -0,0 +1,83 @@ +#[doc = "Register `IN_INT_ST_CH5` reader"] +pub type R = crate::R; +#[doc = "Field `IN_DONE_CH5_INT_ST` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] +pub type IN_DONE_CH5_INT_ST_R = crate::BitReader; +#[doc = "Field `IN_SUC_EOF_CH5_INT_ST` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] +pub type IN_SUC_EOF_CH5_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_OVF_L1_CH5_INT_ST` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] +pub type INFIFO_OVF_L1_CH5_INT_ST_R = crate::BitReader; +#[doc = "Field `INFIFO_UDF_L1_CH5_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type INFIFO_UDF_L1_CH5_INT_ST_R = crate::BitReader; +#[doc = "Field `FETCH_MB_COL_CNT_OVF_CH5_INT_ST` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] +pub type FETCH_MB_COL_CNT_OVF_CH5_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn in_done_ch5_int_st(&self) -> IN_DONE_CH5_INT_ST_R { + IN_DONE_CH5_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn in_suc_eof_ch5_int_st(&self) -> IN_SUC_EOF_CH5_INT_ST_R { + IN_SUC_EOF_CH5_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_ovf_l1_ch5_int_st(&self) -> INFIFO_OVF_L1_CH5_INT_ST_R { + INFIFO_OVF_L1_CH5_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn infifo_udf_l1_ch5_int_st(&self) -> INFIFO_UDF_L1_CH5_INT_ST_R { + INFIFO_UDF_L1_CH5_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn fetch_mb_col_cnt_ovf_ch5_int_st(&self) -> FETCH_MB_COL_CNT_OVF_CH5_INT_ST_R { + FETCH_MB_COL_CNT_OVF_CH5_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_INT_ST_CH5") + .field( + "in_done_ch5_int_st", + &format_args!("{}", self.in_done_ch5_int_st().bit()), + ) + .field( + "in_suc_eof_ch5_int_st", + &format_args!("{}", self.in_suc_eof_ch5_int_st().bit()), + ) + .field( + "infifo_ovf_l1_ch5_int_st", + &format_args!("{}", self.infifo_ovf_l1_ch5_int_st().bit()), + ) + .field( + "infifo_udf_l1_ch5_int_st", + &format_args!("{}", self.infifo_udf_l1_ch5_int_st().bit()), + ) + .field( + "fetch_mb_col_cnt_ovf_ch5_int_st", + &format_args!("{}", self.fetch_mb_col_cnt_ovf_ch5_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH5 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_int_st_ch5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_INT_ST_CH5_SPEC; +impl crate::RegisterSpec for IN_INT_ST_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_int_st_ch5::R`](R) reader structure"] +impl crate::Readable for IN_INT_ST_CH5_SPEC {} +#[doc = "`reset()` method sets IN_INT_ST_CH5 to value 0"] +impl crate::Resettable for IN_INT_ST_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_link_addr_ch0.rs b/esp32p4/src/h264_dma/in_link_addr_ch0.rs new file mode 100644 index 0000000000..dbc48df6c0 --- /dev/null +++ b/esp32p4/src/h264_dma/in_link_addr_ch0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_LINK_ADDR_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_ADDR_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_ADDR_CH0` reader - This register stores the first inlink descriptor's address."] +pub type INLINK_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR_CH0` writer - This register stores the first inlink descriptor's address."] +pub type INLINK_ADDR_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the first inlink descriptor's address."] + #[inline(always)] + pub fn inlink_addr_ch0(&self) -> INLINK_ADDR_CH0_R { + INLINK_ADDR_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_ADDR_CH0") + .field( + "inlink_addr_ch0", + &format_args!("{}", self.inlink_addr_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the first inlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn inlink_addr_ch0(&mut self) -> INLINK_ADDR_CH0_W { + INLINK_ADDR_CH0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH0 in_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_ADDR_CH0_SPEC; +impl crate::RegisterSpec for IN_LINK_ADDR_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_addr_ch0::R`](R) reader structure"] +impl crate::Readable for IN_LINK_ADDR_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_addr_ch0::W`](W) writer structure"] +impl crate::Writable for IN_LINK_ADDR_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_ADDR_CH0 to value 0"] +impl crate::Resettable for IN_LINK_ADDR_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_link_addr_ch1.rs b/esp32p4/src/h264_dma/in_link_addr_ch1.rs new file mode 100644 index 0000000000..4f21a1cc27 --- /dev/null +++ b/esp32p4/src/h264_dma/in_link_addr_ch1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_LINK_ADDR_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_ADDR_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_ADDR_CH1` reader - This register stores the first inlink descriptor's address."] +pub type INLINK_ADDR_CH1_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR_CH1` writer - This register stores the first inlink descriptor's address."] +pub type INLINK_ADDR_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the first inlink descriptor's address."] + #[inline(always)] + pub fn inlink_addr_ch1(&self) -> INLINK_ADDR_CH1_R { + INLINK_ADDR_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_ADDR_CH1") + .field( + "inlink_addr_ch1", + &format_args!("{}", self.inlink_addr_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the first inlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn inlink_addr_ch1(&mut self) -> INLINK_ADDR_CH1_W { + INLINK_ADDR_CH1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH1 in_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_ADDR_CH1_SPEC; +impl crate::RegisterSpec for IN_LINK_ADDR_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_addr_ch1::R`](R) reader structure"] +impl crate::Readable for IN_LINK_ADDR_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_addr_ch1::W`](W) writer structure"] +impl crate::Writable for IN_LINK_ADDR_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_ADDR_CH1 to value 0"] +impl crate::Resettable for IN_LINK_ADDR_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_link_addr_ch2.rs b/esp32p4/src/h264_dma/in_link_addr_ch2.rs new file mode 100644 index 0000000000..a96e74cdb4 --- /dev/null +++ b/esp32p4/src/h264_dma/in_link_addr_ch2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_LINK_ADDR_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_ADDR_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_ADDR_CH2` reader - This register stores the first inlink descriptor's address."] +pub type INLINK_ADDR_CH2_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR_CH2` writer - This register stores the first inlink descriptor's address."] +pub type INLINK_ADDR_CH2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the first inlink descriptor's address."] + #[inline(always)] + pub fn inlink_addr_ch2(&self) -> INLINK_ADDR_CH2_R { + INLINK_ADDR_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_ADDR_CH2") + .field( + "inlink_addr_ch2", + &format_args!("{}", self.inlink_addr_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the first inlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn inlink_addr_ch2(&mut self) -> INLINK_ADDR_CH2_W { + INLINK_ADDR_CH2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH2 in_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_ADDR_CH2_SPEC; +impl crate::RegisterSpec for IN_LINK_ADDR_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_addr_ch2::R`](R) reader structure"] +impl crate::Readable for IN_LINK_ADDR_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_addr_ch2::W`](W) writer structure"] +impl crate::Writable for IN_LINK_ADDR_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_ADDR_CH2 to value 0"] +impl crate::Resettable for IN_LINK_ADDR_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_link_addr_ch3.rs b/esp32p4/src/h264_dma/in_link_addr_ch3.rs new file mode 100644 index 0000000000..2e576fe756 --- /dev/null +++ b/esp32p4/src/h264_dma/in_link_addr_ch3.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_LINK_ADDR_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_ADDR_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_ADDR_CH3` reader - This register stores the first inlink descriptor's address."] +pub type INLINK_ADDR_CH3_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR_CH3` writer - This register stores the first inlink descriptor's address."] +pub type INLINK_ADDR_CH3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the first inlink descriptor's address."] + #[inline(always)] + pub fn inlink_addr_ch3(&self) -> INLINK_ADDR_CH3_R { + INLINK_ADDR_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_ADDR_CH3") + .field( + "inlink_addr_ch3", + &format_args!("{}", self.inlink_addr_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the first inlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn inlink_addr_ch3(&mut self) -> INLINK_ADDR_CH3_W { + INLINK_ADDR_CH3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH3 in_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_ADDR_CH3_SPEC; +impl crate::RegisterSpec for IN_LINK_ADDR_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_addr_ch3::R`](R) reader structure"] +impl crate::Readable for IN_LINK_ADDR_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_addr_ch3::W`](W) writer structure"] +impl crate::Writable for IN_LINK_ADDR_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_ADDR_CH3 to value 0"] +impl crate::Resettable for IN_LINK_ADDR_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_link_addr_ch4.rs b/esp32p4/src/h264_dma/in_link_addr_ch4.rs new file mode 100644 index 0000000000..e3afc3576c --- /dev/null +++ b/esp32p4/src/h264_dma/in_link_addr_ch4.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_LINK_ADDR_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_ADDR_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_ADDR_CH4` reader - This register stores the first inlink descriptor's address."] +pub type INLINK_ADDR_CH4_R = crate::FieldReader; +#[doc = "Field `INLINK_ADDR_CH4` writer - This register stores the first inlink descriptor's address."] +pub type INLINK_ADDR_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the first inlink descriptor's address."] + #[inline(always)] + pub fn inlink_addr_ch4(&self) -> INLINK_ADDR_CH4_R { + INLINK_ADDR_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_ADDR_CH4") + .field( + "inlink_addr_ch4", + &format_args!("{}", self.inlink_addr_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the first inlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn inlink_addr_ch4(&mut self) -> INLINK_ADDR_CH4_W { + INLINK_ADDR_CH4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH4 in_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_addr_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_addr_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_ADDR_CH4_SPEC; +impl crate::RegisterSpec for IN_LINK_ADDR_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_addr_ch4::R`](R) reader structure"] +impl crate::Readable for IN_LINK_ADDR_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_addr_ch4::W`](W) writer structure"] +impl crate::Writable for IN_LINK_ADDR_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_ADDR_CH4 to value 0"] +impl crate::Resettable for IN_LINK_ADDR_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_link_conf_ch0.rs b/esp32p4/src/h264_dma/in_link_conf_ch0.rs new file mode 100644 index 0000000000..0961428384 --- /dev/null +++ b/esp32p4/src/h264_dma/in_link_conf_ch0.rs @@ -0,0 +1,134 @@ +#[doc = "Register `IN_LINK_CONF_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_CONF_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_AUTO_RET_CH0` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH0_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET_CH0` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_STOP_CH0` reader - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH0_R = crate::BitReader; +#[doc = "Field `INLINK_STOP_CH0` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_START_CH0` reader - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH0_R = crate::BitReader; +#[doc = "Field `INLINK_START_CH0` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_RESTART_CH0` reader - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH0_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART_CH0` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_PARK_CH0` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_CH0_R = crate::BitReader; +impl R { + #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] + #[inline(always)] + pub fn inlink_auto_ret_ch0(&self) -> INLINK_AUTO_RET_CH0_R { + INLINK_AUTO_RET_CH0_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + pub fn inlink_stop_ch0(&self) -> INLINK_STOP_CH0_R { + INLINK_STOP_CH0_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + pub fn inlink_start_ch0(&self) -> INLINK_START_CH0_R { + INLINK_START_CH0_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + pub fn inlink_restart_ch0(&self) -> INLINK_RESTART_CH0_R { + INLINK_RESTART_CH0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] + #[inline(always)] + pub fn inlink_park_ch0(&self) -> INLINK_PARK_CH0_R { + INLINK_PARK_CH0_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_CONF_CH0") + .field( + "inlink_auto_ret_ch0", + &format_args!("{}", self.inlink_auto_ret_ch0().bit()), + ) + .field( + "inlink_stop_ch0", + &format_args!("{}", self.inlink_stop_ch0().bit()), + ) + .field( + "inlink_start_ch0", + &format_args!("{}", self.inlink_start_ch0().bit()), + ) + .field( + "inlink_restart_ch0", + &format_args!("{}", self.inlink_restart_ch0().bit()), + ) + .field( + "inlink_park_ch0", + &format_args!("{}", self.inlink_park_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] + #[inline(always)] + #[must_use] + pub fn inlink_auto_ret_ch0(&mut self) -> INLINK_AUTO_RET_CH0_W { + INLINK_AUTO_RET_CH0_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_stop_ch0(&mut self) -> INLINK_STOP_CH0_W { + INLINK_STOP_CH0_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_start_ch0(&mut self) -> INLINK_START_CH0_W { + INLINK_START_CH0_W::new(self, 22) + } + #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + #[must_use] + pub fn inlink_restart_ch0(&mut self) -> INLINK_RESTART_CH0_W { + INLINK_RESTART_CH0_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH0 in_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_conf_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_conf_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_CONF_CH0_SPEC; +impl crate::RegisterSpec for IN_LINK_CONF_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_conf_ch0::R`](R) reader structure"] +impl crate::Readable for IN_LINK_CONF_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_conf_ch0::W`](W) writer structure"] +impl crate::Writable for IN_LINK_CONF_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_CONF_CH0 to value 0x0110_0000"] +impl crate::Resettable for IN_LINK_CONF_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x0110_0000; +} diff --git a/esp32p4/src/h264_dma/in_link_conf_ch1.rs b/esp32p4/src/h264_dma/in_link_conf_ch1.rs new file mode 100644 index 0000000000..87c9a3630a --- /dev/null +++ b/esp32p4/src/h264_dma/in_link_conf_ch1.rs @@ -0,0 +1,134 @@ +#[doc = "Register `IN_LINK_CONF_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_CONF_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_AUTO_RET_CH1` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH1_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET_CH1` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_STOP_CH1` reader - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH1_R = crate::BitReader; +#[doc = "Field `INLINK_STOP_CH1` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_START_CH1` reader - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH1_R = crate::BitReader; +#[doc = "Field `INLINK_START_CH1` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_RESTART_CH1` reader - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH1_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART_CH1` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_PARK_CH1` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_CH1_R = crate::BitReader; +impl R { + #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] + #[inline(always)] + pub fn inlink_auto_ret_ch1(&self) -> INLINK_AUTO_RET_CH1_R { + INLINK_AUTO_RET_CH1_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + pub fn inlink_stop_ch1(&self) -> INLINK_STOP_CH1_R { + INLINK_STOP_CH1_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + pub fn inlink_start_ch1(&self) -> INLINK_START_CH1_R { + INLINK_START_CH1_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + pub fn inlink_restart_ch1(&self) -> INLINK_RESTART_CH1_R { + INLINK_RESTART_CH1_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] + #[inline(always)] + pub fn inlink_park_ch1(&self) -> INLINK_PARK_CH1_R { + INLINK_PARK_CH1_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_CONF_CH1") + .field( + "inlink_auto_ret_ch1", + &format_args!("{}", self.inlink_auto_ret_ch1().bit()), + ) + .field( + "inlink_stop_ch1", + &format_args!("{}", self.inlink_stop_ch1().bit()), + ) + .field( + "inlink_start_ch1", + &format_args!("{}", self.inlink_start_ch1().bit()), + ) + .field( + "inlink_restart_ch1", + &format_args!("{}", self.inlink_restart_ch1().bit()), + ) + .field( + "inlink_park_ch1", + &format_args!("{}", self.inlink_park_ch1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] + #[inline(always)] + #[must_use] + pub fn inlink_auto_ret_ch1(&mut self) -> INLINK_AUTO_RET_CH1_W { + INLINK_AUTO_RET_CH1_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_stop_ch1(&mut self) -> INLINK_STOP_CH1_W { + INLINK_STOP_CH1_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_start_ch1(&mut self) -> INLINK_START_CH1_W { + INLINK_START_CH1_W::new(self, 22) + } + #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + #[must_use] + pub fn inlink_restart_ch1(&mut self) -> INLINK_RESTART_CH1_W { + INLINK_RESTART_CH1_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH1 in_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_conf_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_conf_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_CONF_CH1_SPEC; +impl crate::RegisterSpec for IN_LINK_CONF_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_conf_ch1::R`](R) reader structure"] +impl crate::Readable for IN_LINK_CONF_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_conf_ch1::W`](W) writer structure"] +impl crate::Writable for IN_LINK_CONF_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_CONF_CH1 to value 0x0110_0000"] +impl crate::Resettable for IN_LINK_CONF_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x0110_0000; +} diff --git a/esp32p4/src/h264_dma/in_link_conf_ch2.rs b/esp32p4/src/h264_dma/in_link_conf_ch2.rs new file mode 100644 index 0000000000..8314d25963 --- /dev/null +++ b/esp32p4/src/h264_dma/in_link_conf_ch2.rs @@ -0,0 +1,134 @@ +#[doc = "Register `IN_LINK_CONF_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_CONF_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_AUTO_RET_CH2` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH2_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET_CH2` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_STOP_CH2` reader - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH2_R = crate::BitReader; +#[doc = "Field `INLINK_STOP_CH2` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_START_CH2` reader - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH2_R = crate::BitReader; +#[doc = "Field `INLINK_START_CH2` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_RESTART_CH2` reader - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH2_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART_CH2` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_PARK_CH2` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_CH2_R = crate::BitReader; +impl R { + #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] + #[inline(always)] + pub fn inlink_auto_ret_ch2(&self) -> INLINK_AUTO_RET_CH2_R { + INLINK_AUTO_RET_CH2_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + pub fn inlink_stop_ch2(&self) -> INLINK_STOP_CH2_R { + INLINK_STOP_CH2_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + pub fn inlink_start_ch2(&self) -> INLINK_START_CH2_R { + INLINK_START_CH2_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + pub fn inlink_restart_ch2(&self) -> INLINK_RESTART_CH2_R { + INLINK_RESTART_CH2_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] + #[inline(always)] + pub fn inlink_park_ch2(&self) -> INLINK_PARK_CH2_R { + INLINK_PARK_CH2_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_CONF_CH2") + .field( + "inlink_auto_ret_ch2", + &format_args!("{}", self.inlink_auto_ret_ch2().bit()), + ) + .field( + "inlink_stop_ch2", + &format_args!("{}", self.inlink_stop_ch2().bit()), + ) + .field( + "inlink_start_ch2", + &format_args!("{}", self.inlink_start_ch2().bit()), + ) + .field( + "inlink_restart_ch2", + &format_args!("{}", self.inlink_restart_ch2().bit()), + ) + .field( + "inlink_park_ch2", + &format_args!("{}", self.inlink_park_ch2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] + #[inline(always)] + #[must_use] + pub fn inlink_auto_ret_ch2(&mut self) -> INLINK_AUTO_RET_CH2_W { + INLINK_AUTO_RET_CH2_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_stop_ch2(&mut self) -> INLINK_STOP_CH2_W { + INLINK_STOP_CH2_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_start_ch2(&mut self) -> INLINK_START_CH2_W { + INLINK_START_CH2_W::new(self, 22) + } + #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + #[must_use] + pub fn inlink_restart_ch2(&mut self) -> INLINK_RESTART_CH2_W { + INLINK_RESTART_CH2_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH2 in_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_conf_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_conf_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_CONF_CH2_SPEC; +impl crate::RegisterSpec for IN_LINK_CONF_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_conf_ch2::R`](R) reader structure"] +impl crate::Readable for IN_LINK_CONF_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_conf_ch2::W`](W) writer structure"] +impl crate::Writable for IN_LINK_CONF_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_CONF_CH2 to value 0x0110_0000"] +impl crate::Resettable for IN_LINK_CONF_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x0110_0000; +} diff --git a/esp32p4/src/h264_dma/in_link_conf_ch3.rs b/esp32p4/src/h264_dma/in_link_conf_ch3.rs new file mode 100644 index 0000000000..ba0d5dd254 --- /dev/null +++ b/esp32p4/src/h264_dma/in_link_conf_ch3.rs @@ -0,0 +1,134 @@ +#[doc = "Register `IN_LINK_CONF_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_CONF_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_AUTO_RET_CH3` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH3_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET_CH3` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_STOP_CH3` reader - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH3_R = crate::BitReader; +#[doc = "Field `INLINK_STOP_CH3` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_START_CH3` reader - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH3_R = crate::BitReader; +#[doc = "Field `INLINK_START_CH3` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_RESTART_CH3` reader - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH3_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART_CH3` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_PARK_CH3` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_CH3_R = crate::BitReader; +impl R { + #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] + #[inline(always)] + pub fn inlink_auto_ret_ch3(&self) -> INLINK_AUTO_RET_CH3_R { + INLINK_AUTO_RET_CH3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + pub fn inlink_stop_ch3(&self) -> INLINK_STOP_CH3_R { + INLINK_STOP_CH3_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + pub fn inlink_start_ch3(&self) -> INLINK_START_CH3_R { + INLINK_START_CH3_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + pub fn inlink_restart_ch3(&self) -> INLINK_RESTART_CH3_R { + INLINK_RESTART_CH3_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] + #[inline(always)] + pub fn inlink_park_ch3(&self) -> INLINK_PARK_CH3_R { + INLINK_PARK_CH3_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_CONF_CH3") + .field( + "inlink_auto_ret_ch3", + &format_args!("{}", self.inlink_auto_ret_ch3().bit()), + ) + .field( + "inlink_stop_ch3", + &format_args!("{}", self.inlink_stop_ch3().bit()), + ) + .field( + "inlink_start_ch3", + &format_args!("{}", self.inlink_start_ch3().bit()), + ) + .field( + "inlink_restart_ch3", + &format_args!("{}", self.inlink_restart_ch3().bit()), + ) + .field( + "inlink_park_ch3", + &format_args!("{}", self.inlink_park_ch3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] + #[inline(always)] + #[must_use] + pub fn inlink_auto_ret_ch3(&mut self) -> INLINK_AUTO_RET_CH3_W { + INLINK_AUTO_RET_CH3_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_stop_ch3(&mut self) -> INLINK_STOP_CH3_W { + INLINK_STOP_CH3_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_start_ch3(&mut self) -> INLINK_START_CH3_W { + INLINK_START_CH3_W::new(self, 22) + } + #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + #[must_use] + pub fn inlink_restart_ch3(&mut self) -> INLINK_RESTART_CH3_W { + INLINK_RESTART_CH3_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH3 in_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_conf_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_conf_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_CONF_CH3_SPEC; +impl crate::RegisterSpec for IN_LINK_CONF_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_conf_ch3::R`](R) reader structure"] +impl crate::Readable for IN_LINK_CONF_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_conf_ch3::W`](W) writer structure"] +impl crate::Writable for IN_LINK_CONF_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_CONF_CH3 to value 0x0110_0000"] +impl crate::Resettable for IN_LINK_CONF_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x0110_0000; +} diff --git a/esp32p4/src/h264_dma/in_link_conf_ch4.rs b/esp32p4/src/h264_dma/in_link_conf_ch4.rs new file mode 100644 index 0000000000..5df1e0bdca --- /dev/null +++ b/esp32p4/src/h264_dma/in_link_conf_ch4.rs @@ -0,0 +1,134 @@ +#[doc = "Register `IN_LINK_CONF_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `IN_LINK_CONF_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `INLINK_AUTO_RET_CH4` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH4_R = crate::BitReader; +#[doc = "Field `INLINK_AUTO_RET_CH4` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] +pub type INLINK_AUTO_RET_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_STOP_CH4` reader - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH4_R = crate::BitReader; +#[doc = "Field `INLINK_STOP_CH4` writer - Set this bit to stop dealing with the inlink descriptors."] +pub type INLINK_STOP_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_START_CH4` reader - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH4_R = crate::BitReader; +#[doc = "Field `INLINK_START_CH4` writer - Set this bit to start dealing with the inlink descriptors."] +pub type INLINK_START_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_RESTART_CH4` reader - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH4_R = crate::BitReader; +#[doc = "Field `INLINK_RESTART_CH4` writer - Set this bit to mount a new inlink descriptor."] +pub type INLINK_RESTART_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINK_PARK_CH4` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] +pub type INLINK_PARK_CH4_R = crate::BitReader; +impl R { + #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] + #[inline(always)] + pub fn inlink_auto_ret_ch4(&self) -> INLINK_AUTO_RET_CH4_R { + INLINK_AUTO_RET_CH4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + pub fn inlink_stop_ch4(&self) -> INLINK_STOP_CH4_R { + INLINK_STOP_CH4_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + pub fn inlink_start_ch4(&self) -> INLINK_START_CH4_R { + INLINK_START_CH4_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + pub fn inlink_restart_ch4(&self) -> INLINK_RESTART_CH4_R { + INLINK_RESTART_CH4_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."] + #[inline(always)] + pub fn inlink_park_ch4(&self) -> INLINK_PARK_CH4_R { + INLINK_PARK_CH4_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_LINK_CONF_CH4") + .field( + "inlink_auto_ret_ch4", + &format_args!("{}", self.inlink_auto_ret_ch4().bit()), + ) + .field( + "inlink_stop_ch4", + &format_args!("{}", self.inlink_stop_ch4().bit()), + ) + .field( + "inlink_start_ch4", + &format_args!("{}", self.inlink_start_ch4().bit()), + ) + .field( + "inlink_restart_ch4", + &format_args!("{}", self.inlink_restart_ch4().bit()), + ) + .field( + "inlink_park_ch4", + &format_args!("{}", self.inlink_park_ch4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."] + #[inline(always)] + #[must_use] + pub fn inlink_auto_ret_ch4(&mut self) -> INLINK_AUTO_RET_CH4_W { + INLINK_AUTO_RET_CH4_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_stop_ch4(&mut self) -> INLINK_STOP_CH4_W { + INLINK_STOP_CH4_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."] + #[inline(always)] + #[must_use] + pub fn inlink_start_ch4(&mut self) -> INLINK_START_CH4_W { + INLINK_START_CH4_W::new(self, 22) + } + #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."] + #[inline(always)] + #[must_use] + pub fn inlink_restart_ch4(&mut self) -> INLINK_RESTART_CH4_W { + INLINK_RESTART_CH4_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH4 in_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_link_conf_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_link_conf_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_LINK_CONF_CH4_SPEC; +impl crate::RegisterSpec for IN_LINK_CONF_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_link_conf_ch4::R`](R) reader structure"] +impl crate::Readable for IN_LINK_CONF_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_link_conf_ch4::W`](W) writer structure"] +impl crate::Writable for IN_LINK_CONF_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_LINK_CONF_CH4 to value 0x0110_0000"] +impl crate::Resettable for IN_LINK_CONF_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x0110_0000; +} diff --git a/esp32p4/src/h264_dma/in_pop_ch0.rs b/esp32p4/src/h264_dma/in_pop_ch0.rs new file mode 100644 index 0000000000..7e2ff86361 --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_ch0.rs @@ -0,0 +1,77 @@ +#[doc = "Register `IN_POP_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `IN_POP_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `INFIFO_RDATA_CH0` reader - This register stores the data popping from DMA Rx FIFO."] +pub type INFIFO_RDATA_CH0_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP_CH0` reader - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH0_R = crate::BitReader; +#[doc = "Field `INFIFO_POP_CH0` writer - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:10 - This register stores the data popping from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_rdata_ch0(&self) -> INFIFO_RDATA_CH0_R { + INFIFO_RDATA_CH0_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_pop_ch0(&self) -> INFIFO_POP_CH0_R { + INFIFO_POP_CH0_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_CH0") + .field( + "infifo_rdata_ch0", + &format_args!("{}", self.infifo_rdata_ch0().bits()), + ) + .field( + "infifo_pop_ch0", + &format_args!("{}", self.infifo_pop_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + #[must_use] + pub fn infifo_pop_ch0(&mut self) -> INFIFO_POP_CH0_W { + INFIFO_POP_CH0_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH0 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_CH0_SPEC; +impl crate::RegisterSpec for IN_POP_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_ch0::R`](R) reader structure"] +impl crate::Readable for IN_POP_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_pop_ch0::W`](W) writer structure"] +impl crate::Writable for IN_POP_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_POP_CH0 to value 0x0400"] +impl crate::Resettable for IN_POP_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x0400; +} diff --git a/esp32p4/src/h264_dma/in_pop_ch1.rs b/esp32p4/src/h264_dma/in_pop_ch1.rs new file mode 100644 index 0000000000..85a4fa5c2b --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_ch1.rs @@ -0,0 +1,77 @@ +#[doc = "Register `IN_POP_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `IN_POP_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `INFIFO_RDATA_CH1` reader - This register stores the data popping from DMA Rx FIFO."] +pub type INFIFO_RDATA_CH1_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP_CH1` reader - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH1_R = crate::BitReader; +#[doc = "Field `INFIFO_POP_CH1` writer - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:10 - This register stores the data popping from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_rdata_ch1(&self) -> INFIFO_RDATA_CH1_R { + INFIFO_RDATA_CH1_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_pop_ch1(&self) -> INFIFO_POP_CH1_R { + INFIFO_POP_CH1_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_CH1") + .field( + "infifo_rdata_ch1", + &format_args!("{}", self.infifo_rdata_ch1().bits()), + ) + .field( + "infifo_pop_ch1", + &format_args!("{}", self.infifo_pop_ch1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + #[must_use] + pub fn infifo_pop_ch1(&mut self) -> INFIFO_POP_CH1_W { + INFIFO_POP_CH1_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH1 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_CH1_SPEC; +impl crate::RegisterSpec for IN_POP_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_ch1::R`](R) reader structure"] +impl crate::Readable for IN_POP_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_pop_ch1::W`](W) writer structure"] +impl crate::Writable for IN_POP_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_POP_CH1 to value 0x0400"] +impl crate::Resettable for IN_POP_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x0400; +} diff --git a/esp32p4/src/h264_dma/in_pop_ch2.rs b/esp32p4/src/h264_dma/in_pop_ch2.rs new file mode 100644 index 0000000000..f29783b05c --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_ch2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `IN_POP_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `IN_POP_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `INFIFO_RDATA_CH2` reader - This register stores the data popping from DMA Rx FIFO."] +pub type INFIFO_RDATA_CH2_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP_CH2` reader - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH2_R = crate::BitReader; +#[doc = "Field `INFIFO_POP_CH2` writer - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:10 - This register stores the data popping from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_rdata_ch2(&self) -> INFIFO_RDATA_CH2_R { + INFIFO_RDATA_CH2_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_pop_ch2(&self) -> INFIFO_POP_CH2_R { + INFIFO_POP_CH2_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_CH2") + .field( + "infifo_rdata_ch2", + &format_args!("{}", self.infifo_rdata_ch2().bits()), + ) + .field( + "infifo_pop_ch2", + &format_args!("{}", self.infifo_pop_ch2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + #[must_use] + pub fn infifo_pop_ch2(&mut self) -> INFIFO_POP_CH2_W { + INFIFO_POP_CH2_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH2 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_CH2_SPEC; +impl crate::RegisterSpec for IN_POP_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_ch2::R`](R) reader structure"] +impl crate::Readable for IN_POP_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_pop_ch2::W`](W) writer structure"] +impl crate::Writable for IN_POP_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_POP_CH2 to value 0x0400"] +impl crate::Resettable for IN_POP_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x0400; +} diff --git a/esp32p4/src/h264_dma/in_pop_ch3.rs b/esp32p4/src/h264_dma/in_pop_ch3.rs new file mode 100644 index 0000000000..6244603f8c --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_ch3.rs @@ -0,0 +1,77 @@ +#[doc = "Register `IN_POP_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `IN_POP_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `INFIFO_RDATA_CH3` reader - This register stores the data popping from DMA Rx FIFO."] +pub type INFIFO_RDATA_CH3_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP_CH3` reader - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH3_R = crate::BitReader; +#[doc = "Field `INFIFO_POP_CH3` writer - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:10 - This register stores the data popping from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_rdata_ch3(&self) -> INFIFO_RDATA_CH3_R { + INFIFO_RDATA_CH3_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_pop_ch3(&self) -> INFIFO_POP_CH3_R { + INFIFO_POP_CH3_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_CH3") + .field( + "infifo_rdata_ch3", + &format_args!("{}", self.infifo_rdata_ch3().bits()), + ) + .field( + "infifo_pop_ch3", + &format_args!("{}", self.infifo_pop_ch3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + #[must_use] + pub fn infifo_pop_ch3(&mut self) -> INFIFO_POP_CH3_W { + INFIFO_POP_CH3_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH3 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_CH3_SPEC; +impl crate::RegisterSpec for IN_POP_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_ch3::R`](R) reader structure"] +impl crate::Readable for IN_POP_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_pop_ch3::W`](W) writer structure"] +impl crate::Writable for IN_POP_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_POP_CH3 to value 0x0400"] +impl crate::Resettable for IN_POP_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x0400; +} diff --git a/esp32p4/src/h264_dma/in_pop_ch4.rs b/esp32p4/src/h264_dma/in_pop_ch4.rs new file mode 100644 index 0000000000..cee18cbbe2 --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_ch4.rs @@ -0,0 +1,77 @@ +#[doc = "Register `IN_POP_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `IN_POP_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `INFIFO_RDATA_CH4` reader - This register stores the data popping from DMA Rx FIFO."] +pub type INFIFO_RDATA_CH4_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP_CH4` reader - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH4_R = crate::BitReader; +#[doc = "Field `INFIFO_POP_CH4` writer - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:10 - This register stores the data popping from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_rdata_ch4(&self) -> INFIFO_RDATA_CH4_R { + INFIFO_RDATA_CH4_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_pop_ch4(&self) -> INFIFO_POP_CH4_R { + INFIFO_POP_CH4_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_CH4") + .field( + "infifo_rdata_ch4", + &format_args!("{}", self.infifo_rdata_ch4().bits()), + ) + .field( + "infifo_pop_ch4", + &format_args!("{}", self.infifo_pop_ch4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + #[must_use] + pub fn infifo_pop_ch4(&mut self) -> INFIFO_POP_CH4_W { + INFIFO_POP_CH4_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH4 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_CH4_SPEC; +impl crate::RegisterSpec for IN_POP_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_ch4::R`](R) reader structure"] +impl crate::Readable for IN_POP_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_pop_ch4::W`](W) writer structure"] +impl crate::Writable for IN_POP_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_POP_CH4 to value 0x0400"] +impl crate::Resettable for IN_POP_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x0400; +} diff --git a/esp32p4/src/h264_dma/in_pop_ch5.rs b/esp32p4/src/h264_dma/in_pop_ch5.rs new file mode 100644 index 0000000000..14adf4ebbe --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_ch5.rs @@ -0,0 +1,77 @@ +#[doc = "Register `IN_POP_CH5` reader"] +pub type R = crate::R; +#[doc = "Register `IN_POP_CH5` writer"] +pub type W = crate::W; +#[doc = "Field `INFIFO_RDATA_CH5` reader - This register stores the data popping from DMA Rx FIFO."] +pub type INFIFO_RDATA_CH5_R = crate::FieldReader; +#[doc = "Field `INFIFO_POP_CH5` reader - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH5_R = crate::BitReader; +#[doc = "Field `INFIFO_POP_CH5` writer - Set this bit to pop data from DMA Rx FIFO."] +pub type INFIFO_POP_CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:10 - This register stores the data popping from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_rdata_ch5(&self) -> INFIFO_RDATA_CH5_R { + INFIFO_RDATA_CH5_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + pub fn infifo_pop_ch5(&self) -> INFIFO_POP_CH5_R { + INFIFO_POP_CH5_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_CH5") + .field( + "infifo_rdata_ch5", + &format_args!("{}", self.infifo_rdata_ch5().bits()), + ) + .field( + "infifo_pop_ch5", + &format_args!("{}", self.infifo_pop_ch5().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."] + #[inline(always)] + #[must_use] + pub fn infifo_pop_ch5(&mut self) -> INFIFO_POP_CH5_W { + INFIFO_POP_CH5_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH5 INFIFO pop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_ch5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_pop_ch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_CH5_SPEC; +impl crate::RegisterSpec for IN_POP_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_ch5::R`](R) reader structure"] +impl crate::Readable for IN_POP_CH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_pop_ch5::W`](W) writer structure"] +impl crate::Writable for IN_POP_CH5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_POP_CH5 to value 0x0400"] +impl crate::Resettable for IN_POP_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0x0400; +} diff --git a/esp32p4/src/h264_dma/in_pop_data_cnt_ch0.rs b/esp32p4/src/h264_dma/in_pop_data_cnt_ch0.rs new file mode 100644 index 0000000000..4acecb968b --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_data_cnt_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_POP_DATA_CNT_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_POP_DATA_CNT_CH0` reader - only for debug"] +pub type IN_CMDFIFO_POP_DATA_CNT_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_pop_data_cnt_ch0(&self) -> IN_CMDFIFO_POP_DATA_CNT_CH0_R { + IN_CMDFIFO_POP_DATA_CNT_CH0_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_DATA_CNT_CH0") + .field( + "in_cmdfifo_pop_data_cnt_ch0", + &format_args!("{}", self.in_cmdfifo_pop_data_cnt_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH0 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_DATA_CNT_CH0_SPEC; +impl crate::RegisterSpec for IN_POP_DATA_CNT_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_data_cnt_ch0::R`](R) reader structure"] +impl crate::Readable for IN_POP_DATA_CNT_CH0_SPEC {} +#[doc = "`reset()` method sets IN_POP_DATA_CNT_CH0 to value 0x07"] +impl crate::Resettable for IN_POP_DATA_CNT_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x07; +} diff --git a/esp32p4/src/h264_dma/in_pop_data_cnt_ch1.rs b/esp32p4/src/h264_dma/in_pop_data_cnt_ch1.rs new file mode 100644 index 0000000000..7b9a4195f8 --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_data_cnt_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_POP_DATA_CNT_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_POP_DATA_CNT_CH1` reader - only for debug"] +pub type IN_CMDFIFO_POP_DATA_CNT_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_pop_data_cnt_ch1(&self) -> IN_CMDFIFO_POP_DATA_CNT_CH1_R { + IN_CMDFIFO_POP_DATA_CNT_CH1_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_DATA_CNT_CH1") + .field( + "in_cmdfifo_pop_data_cnt_ch1", + &format_args!("{}", self.in_cmdfifo_pop_data_cnt_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH1 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_DATA_CNT_CH1_SPEC; +impl crate::RegisterSpec for IN_POP_DATA_CNT_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_data_cnt_ch1::R`](R) reader structure"] +impl crate::Readable for IN_POP_DATA_CNT_CH1_SPEC {} +#[doc = "`reset()` method sets IN_POP_DATA_CNT_CH1 to value 0x07"] +impl crate::Resettable for IN_POP_DATA_CNT_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x07; +} diff --git a/esp32p4/src/h264_dma/in_pop_data_cnt_ch2.rs b/esp32p4/src/h264_dma/in_pop_data_cnt_ch2.rs new file mode 100644 index 0000000000..6e79ad519d --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_data_cnt_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_POP_DATA_CNT_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_POP_DATA_CNT_CH2` reader - only for debug"] +pub type IN_CMDFIFO_POP_DATA_CNT_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_pop_data_cnt_ch2(&self) -> IN_CMDFIFO_POP_DATA_CNT_CH2_R { + IN_CMDFIFO_POP_DATA_CNT_CH2_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_DATA_CNT_CH2") + .field( + "in_cmdfifo_pop_data_cnt_ch2", + &format_args!("{}", self.in_cmdfifo_pop_data_cnt_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH2 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_DATA_CNT_CH2_SPEC; +impl crate::RegisterSpec for IN_POP_DATA_CNT_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_data_cnt_ch2::R`](R) reader structure"] +impl crate::Readable for IN_POP_DATA_CNT_CH2_SPEC {} +#[doc = "`reset()` method sets IN_POP_DATA_CNT_CH2 to value 0x07"] +impl crate::Resettable for IN_POP_DATA_CNT_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x07; +} diff --git a/esp32p4/src/h264_dma/in_pop_data_cnt_ch3.rs b/esp32p4/src/h264_dma/in_pop_data_cnt_ch3.rs new file mode 100644 index 0000000000..f7e72ae71c --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_data_cnt_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_POP_DATA_CNT_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_POP_DATA_CNT_CH3` reader - only for debug"] +pub type IN_CMDFIFO_POP_DATA_CNT_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_pop_data_cnt_ch3(&self) -> IN_CMDFIFO_POP_DATA_CNT_CH3_R { + IN_CMDFIFO_POP_DATA_CNT_CH3_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_DATA_CNT_CH3") + .field( + "in_cmdfifo_pop_data_cnt_ch3", + &format_args!("{}", self.in_cmdfifo_pop_data_cnt_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH3 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_DATA_CNT_CH3_SPEC; +impl crate::RegisterSpec for IN_POP_DATA_CNT_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_data_cnt_ch3::R`](R) reader structure"] +impl crate::Readable for IN_POP_DATA_CNT_CH3_SPEC {} +#[doc = "`reset()` method sets IN_POP_DATA_CNT_CH3 to value 0x07"] +impl crate::Resettable for IN_POP_DATA_CNT_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x07; +} diff --git a/esp32p4/src/h264_dma/in_pop_data_cnt_ch4.rs b/esp32p4/src/h264_dma/in_pop_data_cnt_ch4.rs new file mode 100644 index 0000000000..ed294e2275 --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_data_cnt_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_POP_DATA_CNT_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_POP_DATA_CNT_CH4` reader - only for debug"] +pub type IN_CMDFIFO_POP_DATA_CNT_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_pop_data_cnt_ch4(&self) -> IN_CMDFIFO_POP_DATA_CNT_CH4_R { + IN_CMDFIFO_POP_DATA_CNT_CH4_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_DATA_CNT_CH4") + .field( + "in_cmdfifo_pop_data_cnt_ch4", + &format_args!("{}", self.in_cmdfifo_pop_data_cnt_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH4 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_DATA_CNT_CH4_SPEC; +impl crate::RegisterSpec for IN_POP_DATA_CNT_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_data_cnt_ch4::R`](R) reader structure"] +impl crate::Readable for IN_POP_DATA_CNT_CH4_SPEC {} +#[doc = "`reset()` method sets IN_POP_DATA_CNT_CH4 to value 0x07"] +impl crate::Resettable for IN_POP_DATA_CNT_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x07; +} diff --git a/esp32p4/src/h264_dma/in_pop_data_cnt_ch5.rs b/esp32p4/src/h264_dma/in_pop_data_cnt_ch5.rs new file mode 100644 index 0000000000..91dc5545c1 --- /dev/null +++ b/esp32p4/src/h264_dma/in_pop_data_cnt_ch5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_POP_DATA_CNT_CH5` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_POP_DATA_CNT_CH5` reader - only for debug"] +pub type IN_CMDFIFO_POP_DATA_CNT_CH5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_pop_data_cnt_ch5(&self) -> IN_CMDFIFO_POP_DATA_CNT_CH5_R { + IN_CMDFIFO_POP_DATA_CNT_CH5_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_POP_DATA_CNT_CH5") + .field( + "in_cmdfifo_pop_data_cnt_ch5", + &format_args!("{}", self.in_cmdfifo_pop_data_cnt_ch5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH5 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_pop_data_cnt_ch5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_POP_DATA_CNT_CH5_SPEC; +impl crate::RegisterSpec for IN_POP_DATA_CNT_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_pop_data_cnt_ch5::R`](R) reader structure"] +impl crate::Readable for IN_POP_DATA_CNT_CH5_SPEC {} +#[doc = "`reset()` method sets IN_POP_DATA_CNT_CH5 to value 0xff"] +impl crate::Resettable for IN_POP_DATA_CNT_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0xff; +} diff --git a/esp32p4/src/h264_dma/in_ro_pd_conf_ch0.rs b/esp32p4/src/h264_dma/in_ro_pd_conf_ch0.rs new file mode 100644 index 0000000000..de2e42ee41 --- /dev/null +++ b/esp32p4/src/h264_dma/in_ro_pd_conf_ch0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IN_RO_PD_CONF_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `IN_RO_PD_CONF_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `IN_RO_RAM_CLK_FO_CH0` reader - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] +pub type IN_RO_RAM_CLK_FO_CH0_R = crate::BitReader; +#[doc = "Field `IN_RO_RAM_CLK_FO_CH0` writer - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] +pub type IN_RO_RAM_CLK_FO_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 6 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] + #[inline(always)] + pub fn in_ro_ram_clk_fo_ch0(&self) -> IN_RO_RAM_CLK_FO_CH0_R { + IN_RO_RAM_CLK_FO_CH0_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_RO_PD_CONF_CH0") + .field( + "in_ro_ram_clk_fo_ch0", + &format_args!("{}", self.in_ro_ram_clk_fo_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 6 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] + #[inline(always)] + #[must_use] + pub fn in_ro_ram_clk_fo_ch0(&mut self) -> IN_RO_RAM_CLK_FO_CH0_W { + IN_RO_RAM_CLK_FO_CH0_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RX CH0 reorder power config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ro_pd_conf_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_ro_pd_conf_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_RO_PD_CONF_CH0_SPEC; +impl crate::RegisterSpec for IN_RO_PD_CONF_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_ro_pd_conf_ch0::R`](R) reader structure"] +impl crate::Readable for IN_RO_PD_CONF_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`in_ro_pd_conf_ch0::W`](W) writer structure"] +impl crate::Writable for IN_RO_PD_CONF_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IN_RO_PD_CONF_CH0 to value 0"] +impl crate::Resettable for IN_RO_PD_CONF_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_state_ch0.rs b/esp32p4/src/h264_dma/in_state_ch0.rs new file mode 100644 index 0000000000..932e1666bd --- /dev/null +++ b/esp32p4/src/h264_dma/in_state_ch0.rs @@ -0,0 +1,72 @@ +#[doc = "Register `IN_STATE_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_ADDR_CH0` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE_CH0` reader - This register stores the current descriptor state machine state."] +pub type IN_DSCR_STATE_CH0_R = crate::FieldReader; +#[doc = "Field `IN_STATE_CH0` reader - This register stores the current control module state machine state."] +pub type IN_STATE_CH0_R = crate::FieldReader; +#[doc = "Field `IN_RESET_AVAIL_CH0` reader - This register indicate that if the channel reset is safety."] +pub type IN_RESET_AVAIL_CH0_R = crate::BitReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] + #[inline(always)] + pub fn inlink_dscr_addr_ch0(&self) -> INLINK_DSCR_ADDR_CH0_R { + INLINK_DSCR_ADDR_CH0_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - This register stores the current descriptor state machine state."] + #[inline(always)] + pub fn in_dscr_state_ch0(&self) -> IN_DSCR_STATE_CH0_R { + IN_DSCR_STATE_CH0_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - This register stores the current control module state machine state."] + #[inline(always)] + pub fn in_state_ch0(&self) -> IN_STATE_CH0_R { + IN_STATE_CH0_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - This register indicate that if the channel reset is safety."] + #[inline(always)] + pub fn in_reset_avail_ch0(&self) -> IN_RESET_AVAIL_CH0_R { + IN_RESET_AVAIL_CH0_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_STATE_CH0") + .field( + "inlink_dscr_addr_ch0", + &format_args!("{}", self.inlink_dscr_addr_ch0().bits()), + ) + .field( + "in_dscr_state_ch0", + &format_args!("{}", self.in_dscr_state_ch0().bits()), + ) + .field( + "in_state_ch0", + &format_args!("{}", self.in_state_ch0().bits()), + ) + .field( + "in_reset_avail_ch0", + &format_args!("{}", self.in_reset_avail_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH0 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_STATE_CH0_SPEC; +impl crate::RegisterSpec for IN_STATE_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_state_ch0::R`](R) reader structure"] +impl crate::Readable for IN_STATE_CH0_SPEC {} +#[doc = "`reset()` method sets IN_STATE_CH0 to value 0x0080_0000"] +impl crate::Resettable for IN_STATE_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_0000; +} diff --git a/esp32p4/src/h264_dma/in_state_ch1.rs b/esp32p4/src/h264_dma/in_state_ch1.rs new file mode 100644 index 0000000000..02d6c6c2d4 --- /dev/null +++ b/esp32p4/src/h264_dma/in_state_ch1.rs @@ -0,0 +1,72 @@ +#[doc = "Register `IN_STATE_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_ADDR_CH1` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_CH1_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE_CH1` reader - This register stores the current descriptor state machine state."] +pub type IN_DSCR_STATE_CH1_R = crate::FieldReader; +#[doc = "Field `IN_STATE_CH1` reader - This register stores the current control module state machine state."] +pub type IN_STATE_CH1_R = crate::FieldReader; +#[doc = "Field `IN_RESET_AVAIL_CH1` reader - This register indicate that if the channel reset is safety."] +pub type IN_RESET_AVAIL_CH1_R = crate::BitReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] + #[inline(always)] + pub fn inlink_dscr_addr_ch1(&self) -> INLINK_DSCR_ADDR_CH1_R { + INLINK_DSCR_ADDR_CH1_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - This register stores the current descriptor state machine state."] + #[inline(always)] + pub fn in_dscr_state_ch1(&self) -> IN_DSCR_STATE_CH1_R { + IN_DSCR_STATE_CH1_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - This register stores the current control module state machine state."] + #[inline(always)] + pub fn in_state_ch1(&self) -> IN_STATE_CH1_R { + IN_STATE_CH1_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - This register indicate that if the channel reset is safety."] + #[inline(always)] + pub fn in_reset_avail_ch1(&self) -> IN_RESET_AVAIL_CH1_R { + IN_RESET_AVAIL_CH1_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_STATE_CH1") + .field( + "inlink_dscr_addr_ch1", + &format_args!("{}", self.inlink_dscr_addr_ch1().bits()), + ) + .field( + "in_dscr_state_ch1", + &format_args!("{}", self.in_dscr_state_ch1().bits()), + ) + .field( + "in_state_ch1", + &format_args!("{}", self.in_state_ch1().bits()), + ) + .field( + "in_reset_avail_ch1", + &format_args!("{}", self.in_reset_avail_ch1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH1 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_STATE_CH1_SPEC; +impl crate::RegisterSpec for IN_STATE_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_state_ch1::R`](R) reader structure"] +impl crate::Readable for IN_STATE_CH1_SPEC {} +#[doc = "`reset()` method sets IN_STATE_CH1 to value 0x0080_0000"] +impl crate::Resettable for IN_STATE_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_0000; +} diff --git a/esp32p4/src/h264_dma/in_state_ch2.rs b/esp32p4/src/h264_dma/in_state_ch2.rs new file mode 100644 index 0000000000..77efa4ef3a --- /dev/null +++ b/esp32p4/src/h264_dma/in_state_ch2.rs @@ -0,0 +1,72 @@ +#[doc = "Register `IN_STATE_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_ADDR_CH2` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_CH2_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE_CH2` reader - This register stores the current descriptor state machine state."] +pub type IN_DSCR_STATE_CH2_R = crate::FieldReader; +#[doc = "Field `IN_STATE_CH2` reader - This register stores the current control module state machine state."] +pub type IN_STATE_CH2_R = crate::FieldReader; +#[doc = "Field `IN_RESET_AVAIL_CH2` reader - This register indicate that if the channel reset is safety."] +pub type IN_RESET_AVAIL_CH2_R = crate::BitReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] + #[inline(always)] + pub fn inlink_dscr_addr_ch2(&self) -> INLINK_DSCR_ADDR_CH2_R { + INLINK_DSCR_ADDR_CH2_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - This register stores the current descriptor state machine state."] + #[inline(always)] + pub fn in_dscr_state_ch2(&self) -> IN_DSCR_STATE_CH2_R { + IN_DSCR_STATE_CH2_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - This register stores the current control module state machine state."] + #[inline(always)] + pub fn in_state_ch2(&self) -> IN_STATE_CH2_R { + IN_STATE_CH2_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - This register indicate that if the channel reset is safety."] + #[inline(always)] + pub fn in_reset_avail_ch2(&self) -> IN_RESET_AVAIL_CH2_R { + IN_RESET_AVAIL_CH2_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_STATE_CH2") + .field( + "inlink_dscr_addr_ch2", + &format_args!("{}", self.inlink_dscr_addr_ch2().bits()), + ) + .field( + "in_dscr_state_ch2", + &format_args!("{}", self.in_dscr_state_ch2().bits()), + ) + .field( + "in_state_ch2", + &format_args!("{}", self.in_state_ch2().bits()), + ) + .field( + "in_reset_avail_ch2", + &format_args!("{}", self.in_reset_avail_ch2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH2 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_STATE_CH2_SPEC; +impl crate::RegisterSpec for IN_STATE_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_state_ch2::R`](R) reader structure"] +impl crate::Readable for IN_STATE_CH2_SPEC {} +#[doc = "`reset()` method sets IN_STATE_CH2 to value 0x0080_0000"] +impl crate::Resettable for IN_STATE_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_0000; +} diff --git a/esp32p4/src/h264_dma/in_state_ch3.rs b/esp32p4/src/h264_dma/in_state_ch3.rs new file mode 100644 index 0000000000..6356adcb9a --- /dev/null +++ b/esp32p4/src/h264_dma/in_state_ch3.rs @@ -0,0 +1,72 @@ +#[doc = "Register `IN_STATE_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_ADDR_CH3` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_CH3_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE_CH3` reader - This register stores the current descriptor state machine state."] +pub type IN_DSCR_STATE_CH3_R = crate::FieldReader; +#[doc = "Field `IN_STATE_CH3` reader - This register stores the current control module state machine state."] +pub type IN_STATE_CH3_R = crate::FieldReader; +#[doc = "Field `IN_RESET_AVAIL_CH3` reader - This register indicate that if the channel reset is safety."] +pub type IN_RESET_AVAIL_CH3_R = crate::BitReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] + #[inline(always)] + pub fn inlink_dscr_addr_ch3(&self) -> INLINK_DSCR_ADDR_CH3_R { + INLINK_DSCR_ADDR_CH3_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - This register stores the current descriptor state machine state."] + #[inline(always)] + pub fn in_dscr_state_ch3(&self) -> IN_DSCR_STATE_CH3_R { + IN_DSCR_STATE_CH3_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - This register stores the current control module state machine state."] + #[inline(always)] + pub fn in_state_ch3(&self) -> IN_STATE_CH3_R { + IN_STATE_CH3_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - This register indicate that if the channel reset is safety."] + #[inline(always)] + pub fn in_reset_avail_ch3(&self) -> IN_RESET_AVAIL_CH3_R { + IN_RESET_AVAIL_CH3_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_STATE_CH3") + .field( + "inlink_dscr_addr_ch3", + &format_args!("{}", self.inlink_dscr_addr_ch3().bits()), + ) + .field( + "in_dscr_state_ch3", + &format_args!("{}", self.in_dscr_state_ch3().bits()), + ) + .field( + "in_state_ch3", + &format_args!("{}", self.in_state_ch3().bits()), + ) + .field( + "in_reset_avail_ch3", + &format_args!("{}", self.in_reset_avail_ch3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH3 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_STATE_CH3_SPEC; +impl crate::RegisterSpec for IN_STATE_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_state_ch3::R`](R) reader structure"] +impl crate::Readable for IN_STATE_CH3_SPEC {} +#[doc = "`reset()` method sets IN_STATE_CH3 to value 0x0080_0000"] +impl crate::Resettable for IN_STATE_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_0000; +} diff --git a/esp32p4/src/h264_dma/in_state_ch4.rs b/esp32p4/src/h264_dma/in_state_ch4.rs new file mode 100644 index 0000000000..af4a4e9717 --- /dev/null +++ b/esp32p4/src/h264_dma/in_state_ch4.rs @@ -0,0 +1,72 @@ +#[doc = "Register `IN_STATE_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `INLINK_DSCR_ADDR_CH4` reader - This register stores the current inlink descriptor's address."] +pub type INLINK_DSCR_ADDR_CH4_R = crate::FieldReader; +#[doc = "Field `IN_DSCR_STATE_CH4` reader - This register stores the current descriptor state machine state."] +pub type IN_DSCR_STATE_CH4_R = crate::FieldReader; +#[doc = "Field `IN_STATE_CH4` reader - This register stores the current control module state machine state."] +pub type IN_STATE_CH4_R = crate::FieldReader; +#[doc = "Field `IN_RESET_AVAIL_CH4` reader - This register indicate that if the channel reset is safety."] +pub type IN_RESET_AVAIL_CH4_R = crate::BitReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."] + #[inline(always)] + pub fn inlink_dscr_addr_ch4(&self) -> INLINK_DSCR_ADDR_CH4_R { + INLINK_DSCR_ADDR_CH4_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - This register stores the current descriptor state machine state."] + #[inline(always)] + pub fn in_dscr_state_ch4(&self) -> IN_DSCR_STATE_CH4_R { + IN_DSCR_STATE_CH4_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:22 - This register stores the current control module state machine state."] + #[inline(always)] + pub fn in_state_ch4(&self) -> IN_STATE_CH4_R { + IN_STATE_CH4_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - This register indicate that if the channel reset is safety."] + #[inline(always)] + pub fn in_reset_avail_ch4(&self) -> IN_RESET_AVAIL_CH4_R { + IN_RESET_AVAIL_CH4_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_STATE_CH4") + .field( + "inlink_dscr_addr_ch4", + &format_args!("{}", self.inlink_dscr_addr_ch4().bits()), + ) + .field( + "in_dscr_state_ch4", + &format_args!("{}", self.in_dscr_state_ch4().bits()), + ) + .field( + "in_state_ch4", + &format_args!("{}", self.in_state_ch4().bits()), + ) + .field( + "in_reset_avail_ch4", + &format_args!("{}", self.in_reset_avail_ch4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH4 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_STATE_CH4_SPEC; +impl crate::RegisterSpec for IN_STATE_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_state_ch4::R`](R) reader structure"] +impl crate::Readable for IN_STATE_CH4_SPEC {} +#[doc = "`reset()` method sets IN_STATE_CH4 to value 0x0080_0000"] +impl crate::Resettable for IN_STATE_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_0000; +} diff --git a/esp32p4/src/h264_dma/in_state_ch5.rs b/esp32p4/src/h264_dma/in_state_ch5.rs new file mode 100644 index 0000000000..1d4481a802 --- /dev/null +++ b/esp32p4/src/h264_dma/in_state_ch5.rs @@ -0,0 +1,50 @@ +#[doc = "Register `IN_STATE_CH5` reader"] +pub type R = crate::R; +#[doc = "Field `IN_STATE_CH5` reader - This register stores the current control module state machine state."] +pub type IN_STATE_CH5_R = crate::FieldReader; +#[doc = "Field `IN_RESET_AVAIL_CH5` reader - This register indicate that if the channel reset is safety."] +pub type IN_RESET_AVAIL_CH5_R = crate::BitReader; +impl R { + #[doc = "Bits 0:2 - This register stores the current control module state machine state."] + #[inline(always)] + pub fn in_state_ch5(&self) -> IN_STATE_CH5_R { + IN_STATE_CH5_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - This register indicate that if the channel reset is safety."] + #[inline(always)] + pub fn in_reset_avail_ch5(&self) -> IN_RESET_AVAIL_CH5_R { + IN_RESET_AVAIL_CH5_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_STATE_CH5") + .field( + "in_state_ch5", + &format_args!("{}", self.in_state_ch5().bits()), + ) + .field( + "in_reset_avail_ch5", + &format_args!("{}", self.in_reset_avail_ch5().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH5 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state_ch5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_STATE_CH5_SPEC; +impl crate::RegisterSpec for IN_STATE_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_state_ch5::R`](R) reader structure"] +impl crate::Readable for IN_STATE_CH5_SPEC {} +#[doc = "`reset()` method sets IN_STATE_CH5 to value 0x08"] +impl crate::Resettable for IN_STATE_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch0.rs b/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch0.rs new file mode 100644 index 0000000000..9426829c94 --- /dev/null +++ b/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_SUC_EOF_DES_ADDR_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH0` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn in_suc_eof_des_addr_ch0(&self) -> IN_SUC_EOF_DES_ADDR_CH0_R { + IN_SUC_EOF_DES_ADDR_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_SUC_EOF_DES_ADDR_CH0") + .field( + "in_suc_eof_des_addr_ch0", + &format_args!("{}", self.in_suc_eof_des_addr_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH0 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_SUC_EOF_DES_ADDR_CH0_SPEC; +impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_suc_eof_des_addr_ch0::R`](R) reader structure"] +impl crate::Readable for IN_SUC_EOF_DES_ADDR_CH0_SPEC {} +#[doc = "`reset()` method sets IN_SUC_EOF_DES_ADDR_CH0 to value 0"] +impl crate::Resettable for IN_SUC_EOF_DES_ADDR_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch1.rs b/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch1.rs new file mode 100644 index 0000000000..f4ea988200 --- /dev/null +++ b/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_SUC_EOF_DES_ADDR_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH1` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn in_suc_eof_des_addr_ch1(&self) -> IN_SUC_EOF_DES_ADDR_CH1_R { + IN_SUC_EOF_DES_ADDR_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_SUC_EOF_DES_ADDR_CH1") + .field( + "in_suc_eof_des_addr_ch1", + &format_args!("{}", self.in_suc_eof_des_addr_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH1 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_SUC_EOF_DES_ADDR_CH1_SPEC; +impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_suc_eof_des_addr_ch1::R`](R) reader structure"] +impl crate::Readable for IN_SUC_EOF_DES_ADDR_CH1_SPEC {} +#[doc = "`reset()` method sets IN_SUC_EOF_DES_ADDR_CH1 to value 0"] +impl crate::Resettable for IN_SUC_EOF_DES_ADDR_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch2.rs b/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch2.rs new file mode 100644 index 0000000000..f8f8eaf88f --- /dev/null +++ b/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_SUC_EOF_DES_ADDR_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH2` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn in_suc_eof_des_addr_ch2(&self) -> IN_SUC_EOF_DES_ADDR_CH2_R { + IN_SUC_EOF_DES_ADDR_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_SUC_EOF_DES_ADDR_CH2") + .field( + "in_suc_eof_des_addr_ch2", + &format_args!("{}", self.in_suc_eof_des_addr_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH2 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_SUC_EOF_DES_ADDR_CH2_SPEC; +impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_suc_eof_des_addr_ch2::R`](R) reader structure"] +impl crate::Readable for IN_SUC_EOF_DES_ADDR_CH2_SPEC {} +#[doc = "`reset()` method sets IN_SUC_EOF_DES_ADDR_CH2 to value 0"] +impl crate::Resettable for IN_SUC_EOF_DES_ADDR_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch3.rs b/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch3.rs new file mode 100644 index 0000000000..7af6fd6f11 --- /dev/null +++ b/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_SUC_EOF_DES_ADDR_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH3` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn in_suc_eof_des_addr_ch3(&self) -> IN_SUC_EOF_DES_ADDR_CH3_R { + IN_SUC_EOF_DES_ADDR_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_SUC_EOF_DES_ADDR_CH3") + .field( + "in_suc_eof_des_addr_ch3", + &format_args!("{}", self.in_suc_eof_des_addr_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH3 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_SUC_EOF_DES_ADDR_CH3_SPEC; +impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_suc_eof_des_addr_ch3::R`](R) reader structure"] +impl crate::Readable for IN_SUC_EOF_DES_ADDR_CH3_SPEC {} +#[doc = "`reset()` method sets IN_SUC_EOF_DES_ADDR_CH3 to value 0"] +impl crate::Resettable for IN_SUC_EOF_DES_ADDR_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch4.rs b/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch4.rs new file mode 100644 index 0000000000..06074948bc --- /dev/null +++ b/esp32p4/src/h264_dma/in_suc_eof_des_addr_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_SUC_EOF_DES_ADDR_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `IN_SUC_EOF_DES_ADDR_CH4` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type IN_SUC_EOF_DES_ADDR_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn in_suc_eof_des_addr_ch4(&self) -> IN_SUC_EOF_DES_ADDR_CH4_R { + IN_SUC_EOF_DES_ADDR_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_SUC_EOF_DES_ADDR_CH4") + .field( + "in_suc_eof_des_addr_ch4", + &format_args!("{}", self.in_suc_eof_des_addr_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH4 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_SUC_EOF_DES_ADDR_CH4_SPEC; +impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_suc_eof_des_addr_ch4::R`](R) reader structure"] +impl crate::Readable for IN_SUC_EOF_DES_ADDR_CH4_SPEC {} +#[doc = "`reset()` method sets IN_SUC_EOF_DES_ADDR_CH4 to value 0"] +impl crate::Resettable for IN_SUC_EOF_DES_ADDR_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_xaddr_ch0.rs b/esp32p4/src/h264_dma/in_xaddr_ch0.rs new file mode 100644 index 0000000000..c51c12f7be --- /dev/null +++ b/esp32p4/src/h264_dma/in_xaddr_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_XADDR_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_XADDR_CH0` reader - only for debug"] +pub type IN_CMDFIFO_XADDR_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_xaddr_ch0(&self) -> IN_CMDFIFO_XADDR_CH0_R { + IN_CMDFIFO_XADDR_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_XADDR_CH0") + .field( + "in_cmdfifo_xaddr_ch0", + &format_args!("{}", self.in_cmdfifo_xaddr_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH0 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_XADDR_CH0_SPEC; +impl crate::RegisterSpec for IN_XADDR_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_xaddr_ch0::R`](R) reader structure"] +impl crate::Readable for IN_XADDR_CH0_SPEC {} +#[doc = "`reset()` method sets IN_XADDR_CH0 to value 0"] +impl crate::Resettable for IN_XADDR_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_xaddr_ch1.rs b/esp32p4/src/h264_dma/in_xaddr_ch1.rs new file mode 100644 index 0000000000..c07f145b3f --- /dev/null +++ b/esp32p4/src/h264_dma/in_xaddr_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_XADDR_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_XADDR_CH1` reader - only for debug"] +pub type IN_CMDFIFO_XADDR_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_xaddr_ch1(&self) -> IN_CMDFIFO_XADDR_CH1_R { + IN_CMDFIFO_XADDR_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_XADDR_CH1") + .field( + "in_cmdfifo_xaddr_ch1", + &format_args!("{}", self.in_cmdfifo_xaddr_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH1 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_XADDR_CH1_SPEC; +impl crate::RegisterSpec for IN_XADDR_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_xaddr_ch1::R`](R) reader structure"] +impl crate::Readable for IN_XADDR_CH1_SPEC {} +#[doc = "`reset()` method sets IN_XADDR_CH1 to value 0"] +impl crate::Resettable for IN_XADDR_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_xaddr_ch2.rs b/esp32p4/src/h264_dma/in_xaddr_ch2.rs new file mode 100644 index 0000000000..5b0eec31fd --- /dev/null +++ b/esp32p4/src/h264_dma/in_xaddr_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_XADDR_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_XADDR_CH2` reader - only for debug"] +pub type IN_CMDFIFO_XADDR_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_xaddr_ch2(&self) -> IN_CMDFIFO_XADDR_CH2_R { + IN_CMDFIFO_XADDR_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_XADDR_CH2") + .field( + "in_cmdfifo_xaddr_ch2", + &format_args!("{}", self.in_cmdfifo_xaddr_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH2 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_XADDR_CH2_SPEC; +impl crate::RegisterSpec for IN_XADDR_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_xaddr_ch2::R`](R) reader structure"] +impl crate::Readable for IN_XADDR_CH2_SPEC {} +#[doc = "`reset()` method sets IN_XADDR_CH2 to value 0"] +impl crate::Resettable for IN_XADDR_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_xaddr_ch3.rs b/esp32p4/src/h264_dma/in_xaddr_ch3.rs new file mode 100644 index 0000000000..a1b73b3d01 --- /dev/null +++ b/esp32p4/src/h264_dma/in_xaddr_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_XADDR_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_XADDR_CH3` reader - only for debug"] +pub type IN_CMDFIFO_XADDR_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_xaddr_ch3(&self) -> IN_CMDFIFO_XADDR_CH3_R { + IN_CMDFIFO_XADDR_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_XADDR_CH3") + .field( + "in_cmdfifo_xaddr_ch3", + &format_args!("{}", self.in_cmdfifo_xaddr_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH3 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_XADDR_CH3_SPEC; +impl crate::RegisterSpec for IN_XADDR_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_xaddr_ch3::R`](R) reader structure"] +impl crate::Readable for IN_XADDR_CH3_SPEC {} +#[doc = "`reset()` method sets IN_XADDR_CH3 to value 0"] +impl crate::Resettable for IN_XADDR_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_xaddr_ch4.rs b/esp32p4/src/h264_dma/in_xaddr_ch4.rs new file mode 100644 index 0000000000..0a933b2c0d --- /dev/null +++ b/esp32p4/src/h264_dma/in_xaddr_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_XADDR_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_XADDR_CH4` reader - only for debug"] +pub type IN_CMDFIFO_XADDR_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_xaddr_ch4(&self) -> IN_CMDFIFO_XADDR_CH4_R { + IN_CMDFIFO_XADDR_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_XADDR_CH4") + .field( + "in_cmdfifo_xaddr_ch4", + &format_args!("{}", self.in_cmdfifo_xaddr_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH4 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_XADDR_CH4_SPEC; +impl crate::RegisterSpec for IN_XADDR_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_xaddr_ch4::R`](R) reader structure"] +impl crate::Readable for IN_XADDR_CH4_SPEC {} +#[doc = "`reset()` method sets IN_XADDR_CH4 to value 0"] +impl crate::Resettable for IN_XADDR_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/in_xaddr_ch5.rs b/esp32p4/src/h264_dma/in_xaddr_ch5.rs new file mode 100644 index 0000000000..806c143024 --- /dev/null +++ b/esp32p4/src/h264_dma/in_xaddr_ch5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN_XADDR_CH5` reader"] +pub type R = crate::R; +#[doc = "Field `IN_CMDFIFO_XADDR_CH5` reader - only for debug"] +pub type IN_CMDFIFO_XADDR_CH5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - only for debug"] + #[inline(always)] + pub fn in_cmdfifo_xaddr_ch5(&self) -> IN_CMDFIFO_XADDR_CH5_R { + IN_CMDFIFO_XADDR_CH5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_XADDR_CH5") + .field( + "in_cmdfifo_xaddr_ch5", + &format_args!("{}", self.in_cmdfifo_xaddr_ch5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx CH5 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_xaddr_ch5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_XADDR_CH5_SPEC; +impl crate::RegisterSpec for IN_XADDR_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_xaddr_ch5::R`](R) reader structure"] +impl crate::Readable for IN_XADDR_CH5_SPEC {} +#[doc = "`reset()` method sets IN_XADDR_CH5 to value 0"] +impl crate::Resettable for IN_XADDR_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/infifo_status_ch0.rs b/esp32p4/src/h264_dma/infifo_status_ch0.rs new file mode 100644 index 0000000000..0fdd8681d4 --- /dev/null +++ b/esp32p4/src/h264_dma/infifo_status_ch0.rs @@ -0,0 +1,127 @@ +#[doc = "Register `INFIFO_STATUS_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `INFIFO_FULL_L2_CH0` reader - Rx FIFO full signal for Rx channel."] +pub type INFIFO_FULL_L2_CH0_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L2_CH0` reader - Rx FIFO empty signal for Rx channel."] +pub type INFIFO_EMPTY_L2_CH0_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L2_CH0` reader - The register stores the byte number of the data in Rx FIFO for Rx channel."] +pub type INFIFO_CNT_L2_CH0_R = crate::FieldReader; +#[doc = "Field `INFIFO_FULL_L1_CH0` reader - Tx FIFO full signal for Tx channel 0."] +pub type INFIFO_FULL_L1_CH0_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L1_CH0` reader - Tx FIFO empty signal for Tx channel 0."] +pub type INFIFO_EMPTY_L1_CH0_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L1_CH0` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 0."] +pub type INFIFO_CNT_L1_CH0_R = crate::FieldReader; +#[doc = "Field `INFIFO_FULL_L3_CH0` reader - Tx FIFO full signal for Tx channel 0."] +pub type INFIFO_FULL_L3_CH0_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L3_CH0` reader - Tx FIFO empty signal for Tx channel 0."] +pub type INFIFO_EMPTY_L3_CH0_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L3_CH0` reader - The register stores the 8byte number of the data in Tx FIFO for Tx channel 0."] +pub type INFIFO_CNT_L3_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Rx FIFO full signal for Rx channel."] + #[inline(always)] + pub fn infifo_full_l2_ch0(&self) -> INFIFO_FULL_L2_CH0_R { + INFIFO_FULL_L2_CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Rx FIFO empty signal for Rx channel."] + #[inline(always)] + pub fn infifo_empty_l2_ch0(&self) -> INFIFO_EMPTY_L2_CH0_R { + INFIFO_EMPTY_L2_CH0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The register stores the byte number of the data in Rx FIFO for Rx channel."] + #[inline(always)] + pub fn infifo_cnt_l2_ch0(&self) -> INFIFO_CNT_L2_CH0_R { + INFIFO_CNT_L2_CH0_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - Tx FIFO full signal for Tx channel 0."] + #[inline(always)] + pub fn infifo_full_l1_ch0(&self) -> INFIFO_FULL_L1_CH0_R { + INFIFO_FULL_L1_CH0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tx FIFO empty signal for Tx channel 0."] + #[inline(always)] + pub fn infifo_empty_l1_ch0(&self) -> INFIFO_EMPTY_L1_CH0_R { + INFIFO_EMPTY_L1_CH0_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - The register stores the byte number of the data in Tx FIFO for Tx channel 0."] + #[inline(always)] + pub fn infifo_cnt_l1_ch0(&self) -> INFIFO_CNT_L1_CH0_R { + INFIFO_CNT_L1_CH0_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Tx FIFO full signal for Tx channel 0."] + #[inline(always)] + pub fn infifo_full_l3_ch0(&self) -> INFIFO_FULL_L3_CH0_R { + INFIFO_FULL_L3_CH0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tx FIFO empty signal for Tx channel 0."] + #[inline(always)] + pub fn infifo_empty_l3_ch0(&self) -> INFIFO_EMPTY_L3_CH0_R { + INFIFO_EMPTY_L3_CH0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - The register stores the 8byte number of the data in Tx FIFO for Tx channel 0."] + #[inline(always)] + pub fn infifo_cnt_l3_ch0(&self) -> INFIFO_CNT_L3_CH0_R { + INFIFO_CNT_L3_CH0_R::new(((self.bits >> 18) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INFIFO_STATUS_CH0") + .field( + "infifo_full_l2_ch0", + &format_args!("{}", self.infifo_full_l2_ch0().bit()), + ) + .field( + "infifo_empty_l2_ch0", + &format_args!("{}", self.infifo_empty_l2_ch0().bit()), + ) + .field( + "infifo_cnt_l2_ch0", + &format_args!("{}", self.infifo_cnt_l2_ch0().bits()), + ) + .field( + "infifo_full_l1_ch0", + &format_args!("{}", self.infifo_full_l1_ch0().bit()), + ) + .field( + "infifo_empty_l1_ch0", + &format_args!("{}", self.infifo_empty_l1_ch0().bit()), + ) + .field( + "infifo_cnt_l1_ch0", + &format_args!("{}", self.infifo_cnt_l1_ch0().bits()), + ) + .field( + "infifo_full_l3_ch0", + &format_args!("{}", self.infifo_full_l3_ch0().bit()), + ) + .field( + "infifo_empty_l3_ch0", + &format_args!("{}", self.infifo_empty_l3_ch0().bit()), + ) + .field( + "infifo_cnt_l3_ch0", + &format_args!("{}", self.infifo_cnt_l3_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH0 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFIFO_STATUS_CH0_SPEC; +impl crate::RegisterSpec for INFIFO_STATUS_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`infifo_status_ch0::R`](R) reader structure"] +impl crate::Readable for INFIFO_STATUS_CH0_SPEC {} +#[doc = "`reset()` method sets INFIFO_STATUS_CH0 to value 0x0002_0082"] +impl crate::Resettable for INFIFO_STATUS_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_0082; +} diff --git a/esp32p4/src/h264_dma/infifo_status_ch1.rs b/esp32p4/src/h264_dma/infifo_status_ch1.rs new file mode 100644 index 0000000000..ecfe0ea138 --- /dev/null +++ b/esp32p4/src/h264_dma/infifo_status_ch1.rs @@ -0,0 +1,127 @@ +#[doc = "Register `INFIFO_STATUS_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `INFIFO_FULL_L2_CH1` reader - Rx FIFO full signal for Rx channel."] +pub type INFIFO_FULL_L2_CH1_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L2_CH1` reader - Rx FIFO empty signal for Rx channel."] +pub type INFIFO_EMPTY_L2_CH1_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L2_CH1` reader - The register stores the byte number of the data in Rx FIFO for Rx channel."] +pub type INFIFO_CNT_L2_CH1_R = crate::FieldReader; +#[doc = "Field `INFIFO_FULL_L1_CH1` reader - Tx FIFO full signal for Tx channel 1."] +pub type INFIFO_FULL_L1_CH1_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L1_CH1` reader - Tx FIFO empty signal for Tx channel 1."] +pub type INFIFO_EMPTY_L1_CH1_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L1_CH1` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type INFIFO_CNT_L1_CH1_R = crate::FieldReader; +#[doc = "Field `INFIFO_FULL_L3_CH1` reader - Tx FIFO full signal for Tx channel 1."] +pub type INFIFO_FULL_L3_CH1_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L3_CH1` reader - Tx FIFO empty signal for Tx channel 1."] +pub type INFIFO_EMPTY_L3_CH1_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L3_CH1` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type INFIFO_CNT_L3_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Rx FIFO full signal for Rx channel."] + #[inline(always)] + pub fn infifo_full_l2_ch1(&self) -> INFIFO_FULL_L2_CH1_R { + INFIFO_FULL_L2_CH1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Rx FIFO empty signal for Rx channel."] + #[inline(always)] + pub fn infifo_empty_l2_ch1(&self) -> INFIFO_EMPTY_L2_CH1_R { + INFIFO_EMPTY_L2_CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The register stores the byte number of the data in Rx FIFO for Rx channel."] + #[inline(always)] + pub fn infifo_cnt_l2_ch1(&self) -> INFIFO_CNT_L2_CH1_R { + INFIFO_CNT_L2_CH1_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_full_l1_ch1(&self) -> INFIFO_FULL_L1_CH1_R { + INFIFO_FULL_L1_CH1_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_empty_l1_ch1(&self) -> INFIFO_EMPTY_L1_CH1_R { + INFIFO_EMPTY_L1_CH1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn infifo_cnt_l1_ch1(&self) -> INFIFO_CNT_L1_CH1_R { + INFIFO_CNT_L1_CH1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_full_l3_ch1(&self) -> INFIFO_FULL_L3_CH1_R { + INFIFO_FULL_L3_CH1_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_empty_l3_ch1(&self) -> INFIFO_EMPTY_L3_CH1_R { + INFIFO_EMPTY_L3_CH1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn infifo_cnt_l3_ch1(&self) -> INFIFO_CNT_L3_CH1_R { + INFIFO_CNT_L3_CH1_R::new(((self.bits >> 18) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INFIFO_STATUS_CH1") + .field( + "infifo_full_l2_ch1", + &format_args!("{}", self.infifo_full_l2_ch1().bit()), + ) + .field( + "infifo_empty_l2_ch1", + &format_args!("{}", self.infifo_empty_l2_ch1().bit()), + ) + .field( + "infifo_cnt_l2_ch1", + &format_args!("{}", self.infifo_cnt_l2_ch1().bits()), + ) + .field( + "infifo_full_l1_ch1", + &format_args!("{}", self.infifo_full_l1_ch1().bit()), + ) + .field( + "infifo_empty_l1_ch1", + &format_args!("{}", self.infifo_empty_l1_ch1().bit()), + ) + .field( + "infifo_cnt_l1_ch1", + &format_args!("{}", self.infifo_cnt_l1_ch1().bits()), + ) + .field( + "infifo_full_l3_ch1", + &format_args!("{}", self.infifo_full_l3_ch1().bit()), + ) + .field( + "infifo_empty_l3_ch1", + &format_args!("{}", self.infifo_empty_l3_ch1().bit()), + ) + .field( + "infifo_cnt_l3_ch1", + &format_args!("{}", self.infifo_cnt_l3_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH1 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFIFO_STATUS_CH1_SPEC; +impl crate::RegisterSpec for INFIFO_STATUS_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`infifo_status_ch1::R`](R) reader structure"] +impl crate::Readable for INFIFO_STATUS_CH1_SPEC {} +#[doc = "`reset()` method sets INFIFO_STATUS_CH1 to value 0x0002_0082"] +impl crate::Resettable for INFIFO_STATUS_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_0082; +} diff --git a/esp32p4/src/h264_dma/infifo_status_ch2.rs b/esp32p4/src/h264_dma/infifo_status_ch2.rs new file mode 100644 index 0000000000..48292f600a --- /dev/null +++ b/esp32p4/src/h264_dma/infifo_status_ch2.rs @@ -0,0 +1,127 @@ +#[doc = "Register `INFIFO_STATUS_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `INFIFO_FULL_L2_CH2` reader - Rx FIFO full signal for Rx channel."] +pub type INFIFO_FULL_L2_CH2_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L2_CH2` reader - Rx FIFO empty signal for Rx channel."] +pub type INFIFO_EMPTY_L2_CH2_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L2_CH2` reader - The register stores the byte number of the data in Rx FIFO for Rx channel."] +pub type INFIFO_CNT_L2_CH2_R = crate::FieldReader; +#[doc = "Field `INFIFO_FULL_L1_CH2` reader - Tx FIFO full signal for Tx channel 1."] +pub type INFIFO_FULL_L1_CH2_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L1_CH2` reader - Tx FIFO empty signal for Tx channel 1."] +pub type INFIFO_EMPTY_L1_CH2_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L1_CH2` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type INFIFO_CNT_L1_CH2_R = crate::FieldReader; +#[doc = "Field `INFIFO_FULL_L3_CH2` reader - Tx FIFO full signal for Tx channel 1."] +pub type INFIFO_FULL_L3_CH2_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L3_CH2` reader - Tx FIFO empty signal for Tx channel 1."] +pub type INFIFO_EMPTY_L3_CH2_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L3_CH2` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type INFIFO_CNT_L3_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Rx FIFO full signal for Rx channel."] + #[inline(always)] + pub fn infifo_full_l2_ch2(&self) -> INFIFO_FULL_L2_CH2_R { + INFIFO_FULL_L2_CH2_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Rx FIFO empty signal for Rx channel."] + #[inline(always)] + pub fn infifo_empty_l2_ch2(&self) -> INFIFO_EMPTY_L2_CH2_R { + INFIFO_EMPTY_L2_CH2_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The register stores the byte number of the data in Rx FIFO for Rx channel."] + #[inline(always)] + pub fn infifo_cnt_l2_ch2(&self) -> INFIFO_CNT_L2_CH2_R { + INFIFO_CNT_L2_CH2_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_full_l1_ch2(&self) -> INFIFO_FULL_L1_CH2_R { + INFIFO_FULL_L1_CH2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_empty_l1_ch2(&self) -> INFIFO_EMPTY_L1_CH2_R { + INFIFO_EMPTY_L1_CH2_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn infifo_cnt_l1_ch2(&self) -> INFIFO_CNT_L1_CH2_R { + INFIFO_CNT_L1_CH2_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_full_l3_ch2(&self) -> INFIFO_FULL_L3_CH2_R { + INFIFO_FULL_L3_CH2_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_empty_l3_ch2(&self) -> INFIFO_EMPTY_L3_CH2_R { + INFIFO_EMPTY_L3_CH2_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn infifo_cnt_l3_ch2(&self) -> INFIFO_CNT_L3_CH2_R { + INFIFO_CNT_L3_CH2_R::new(((self.bits >> 18) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INFIFO_STATUS_CH2") + .field( + "infifo_full_l2_ch2", + &format_args!("{}", self.infifo_full_l2_ch2().bit()), + ) + .field( + "infifo_empty_l2_ch2", + &format_args!("{}", self.infifo_empty_l2_ch2().bit()), + ) + .field( + "infifo_cnt_l2_ch2", + &format_args!("{}", self.infifo_cnt_l2_ch2().bits()), + ) + .field( + "infifo_full_l1_ch2", + &format_args!("{}", self.infifo_full_l1_ch2().bit()), + ) + .field( + "infifo_empty_l1_ch2", + &format_args!("{}", self.infifo_empty_l1_ch2().bit()), + ) + .field( + "infifo_cnt_l1_ch2", + &format_args!("{}", self.infifo_cnt_l1_ch2().bits()), + ) + .field( + "infifo_full_l3_ch2", + &format_args!("{}", self.infifo_full_l3_ch2().bit()), + ) + .field( + "infifo_empty_l3_ch2", + &format_args!("{}", self.infifo_empty_l3_ch2().bit()), + ) + .field( + "infifo_cnt_l3_ch2", + &format_args!("{}", self.infifo_cnt_l3_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH2 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFIFO_STATUS_CH2_SPEC; +impl crate::RegisterSpec for INFIFO_STATUS_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`infifo_status_ch2::R`](R) reader structure"] +impl crate::Readable for INFIFO_STATUS_CH2_SPEC {} +#[doc = "`reset()` method sets INFIFO_STATUS_CH2 to value 0x0002_0082"] +impl crate::Resettable for INFIFO_STATUS_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_0082; +} diff --git a/esp32p4/src/h264_dma/infifo_status_ch3.rs b/esp32p4/src/h264_dma/infifo_status_ch3.rs new file mode 100644 index 0000000000..101e6637d6 --- /dev/null +++ b/esp32p4/src/h264_dma/infifo_status_ch3.rs @@ -0,0 +1,127 @@ +#[doc = "Register `INFIFO_STATUS_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `INFIFO_FULL_L2_CH3` reader - Rx FIFO full signal for Rx channel."] +pub type INFIFO_FULL_L2_CH3_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L2_CH3` reader - Rx FIFO empty signal for Rx channel."] +pub type INFIFO_EMPTY_L2_CH3_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L2_CH3` reader - The register stores the byte number of the data in Rx FIFO for Rx channel."] +pub type INFIFO_CNT_L2_CH3_R = crate::FieldReader; +#[doc = "Field `INFIFO_FULL_L1_CH3` reader - Tx FIFO full signal for Tx channel 1."] +pub type INFIFO_FULL_L1_CH3_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L1_CH3` reader - Tx FIFO empty signal for Tx channel 1."] +pub type INFIFO_EMPTY_L1_CH3_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L1_CH3` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type INFIFO_CNT_L1_CH3_R = crate::FieldReader; +#[doc = "Field `INFIFO_FULL_L3_CH3` reader - Tx FIFO full signal for Tx channel 1."] +pub type INFIFO_FULL_L3_CH3_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L3_CH3` reader - Tx FIFO empty signal for Tx channel 1."] +pub type INFIFO_EMPTY_L3_CH3_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L3_CH3` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type INFIFO_CNT_L3_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Rx FIFO full signal for Rx channel."] + #[inline(always)] + pub fn infifo_full_l2_ch3(&self) -> INFIFO_FULL_L2_CH3_R { + INFIFO_FULL_L2_CH3_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Rx FIFO empty signal for Rx channel."] + #[inline(always)] + pub fn infifo_empty_l2_ch3(&self) -> INFIFO_EMPTY_L2_CH3_R { + INFIFO_EMPTY_L2_CH3_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The register stores the byte number of the data in Rx FIFO for Rx channel."] + #[inline(always)] + pub fn infifo_cnt_l2_ch3(&self) -> INFIFO_CNT_L2_CH3_R { + INFIFO_CNT_L2_CH3_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_full_l1_ch3(&self) -> INFIFO_FULL_L1_CH3_R { + INFIFO_FULL_L1_CH3_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_empty_l1_ch3(&self) -> INFIFO_EMPTY_L1_CH3_R { + INFIFO_EMPTY_L1_CH3_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn infifo_cnt_l1_ch3(&self) -> INFIFO_CNT_L1_CH3_R { + INFIFO_CNT_L1_CH3_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_full_l3_ch3(&self) -> INFIFO_FULL_L3_CH3_R { + INFIFO_FULL_L3_CH3_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_empty_l3_ch3(&self) -> INFIFO_EMPTY_L3_CH3_R { + INFIFO_EMPTY_L3_CH3_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn infifo_cnt_l3_ch3(&self) -> INFIFO_CNT_L3_CH3_R { + INFIFO_CNT_L3_CH3_R::new(((self.bits >> 18) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INFIFO_STATUS_CH3") + .field( + "infifo_full_l2_ch3", + &format_args!("{}", self.infifo_full_l2_ch3().bit()), + ) + .field( + "infifo_empty_l2_ch3", + &format_args!("{}", self.infifo_empty_l2_ch3().bit()), + ) + .field( + "infifo_cnt_l2_ch3", + &format_args!("{}", self.infifo_cnt_l2_ch3().bits()), + ) + .field( + "infifo_full_l1_ch3", + &format_args!("{}", self.infifo_full_l1_ch3().bit()), + ) + .field( + "infifo_empty_l1_ch3", + &format_args!("{}", self.infifo_empty_l1_ch3().bit()), + ) + .field( + "infifo_cnt_l1_ch3", + &format_args!("{}", self.infifo_cnt_l1_ch3().bits()), + ) + .field( + "infifo_full_l3_ch3", + &format_args!("{}", self.infifo_full_l3_ch3().bit()), + ) + .field( + "infifo_empty_l3_ch3", + &format_args!("{}", self.infifo_empty_l3_ch3().bit()), + ) + .field( + "infifo_cnt_l3_ch3", + &format_args!("{}", self.infifo_cnt_l3_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH3 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFIFO_STATUS_CH3_SPEC; +impl crate::RegisterSpec for INFIFO_STATUS_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`infifo_status_ch3::R`](R) reader structure"] +impl crate::Readable for INFIFO_STATUS_CH3_SPEC {} +#[doc = "`reset()` method sets INFIFO_STATUS_CH3 to value 0x0002_0082"] +impl crate::Resettable for INFIFO_STATUS_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_0082; +} diff --git a/esp32p4/src/h264_dma/infifo_status_ch4.rs b/esp32p4/src/h264_dma/infifo_status_ch4.rs new file mode 100644 index 0000000000..f9f0682498 --- /dev/null +++ b/esp32p4/src/h264_dma/infifo_status_ch4.rs @@ -0,0 +1,127 @@ +#[doc = "Register `INFIFO_STATUS_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `INFIFO_FULL_L2_CH4` reader - Rx FIFO full signal for Rx channel."] +pub type INFIFO_FULL_L2_CH4_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L2_CH4` reader - Rx FIFO empty signal for Rx channel."] +pub type INFIFO_EMPTY_L2_CH4_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L2_CH4` reader - The register stores the byte number of the data in Rx FIFO for Rx channel."] +pub type INFIFO_CNT_L2_CH4_R = crate::FieldReader; +#[doc = "Field `INFIFO_FULL_L1_CH4` reader - Tx FIFO full signal for Tx channel 1."] +pub type INFIFO_FULL_L1_CH4_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L1_CH4` reader - Tx FIFO empty signal for Tx channel 1."] +pub type INFIFO_EMPTY_L1_CH4_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L1_CH4` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type INFIFO_CNT_L1_CH4_R = crate::FieldReader; +#[doc = "Field `INFIFO_FULL_L3_CH4` reader - Tx FIFO full signal for Tx channel 1."] +pub type INFIFO_FULL_L3_CH4_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L3_CH4` reader - Tx FIFO empty signal for Tx channel 1."] +pub type INFIFO_EMPTY_L3_CH4_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L3_CH4` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type INFIFO_CNT_L3_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Rx FIFO full signal for Rx channel."] + #[inline(always)] + pub fn infifo_full_l2_ch4(&self) -> INFIFO_FULL_L2_CH4_R { + INFIFO_FULL_L2_CH4_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Rx FIFO empty signal for Rx channel."] + #[inline(always)] + pub fn infifo_empty_l2_ch4(&self) -> INFIFO_EMPTY_L2_CH4_R { + INFIFO_EMPTY_L2_CH4_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The register stores the byte number of the data in Rx FIFO for Rx channel."] + #[inline(always)] + pub fn infifo_cnt_l2_ch4(&self) -> INFIFO_CNT_L2_CH4_R { + INFIFO_CNT_L2_CH4_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_full_l1_ch4(&self) -> INFIFO_FULL_L1_CH4_R { + INFIFO_FULL_L1_CH4_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_empty_l1_ch4(&self) -> INFIFO_EMPTY_L1_CH4_R { + INFIFO_EMPTY_L1_CH4_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn infifo_cnt_l1_ch4(&self) -> INFIFO_CNT_L1_CH4_R { + INFIFO_CNT_L1_CH4_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_full_l3_ch4(&self) -> INFIFO_FULL_L3_CH4_R { + INFIFO_FULL_L3_CH4_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_empty_l3_ch4(&self) -> INFIFO_EMPTY_L3_CH4_R { + INFIFO_EMPTY_L3_CH4_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn infifo_cnt_l3_ch4(&self) -> INFIFO_CNT_L3_CH4_R { + INFIFO_CNT_L3_CH4_R::new(((self.bits >> 18) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INFIFO_STATUS_CH4") + .field( + "infifo_full_l2_ch4", + &format_args!("{}", self.infifo_full_l2_ch4().bit()), + ) + .field( + "infifo_empty_l2_ch4", + &format_args!("{}", self.infifo_empty_l2_ch4().bit()), + ) + .field( + "infifo_cnt_l2_ch4", + &format_args!("{}", self.infifo_cnt_l2_ch4().bits()), + ) + .field( + "infifo_full_l1_ch4", + &format_args!("{}", self.infifo_full_l1_ch4().bit()), + ) + .field( + "infifo_empty_l1_ch4", + &format_args!("{}", self.infifo_empty_l1_ch4().bit()), + ) + .field( + "infifo_cnt_l1_ch4", + &format_args!("{}", self.infifo_cnt_l1_ch4().bits()), + ) + .field( + "infifo_full_l3_ch4", + &format_args!("{}", self.infifo_full_l3_ch4().bit()), + ) + .field( + "infifo_empty_l3_ch4", + &format_args!("{}", self.infifo_empty_l3_ch4().bit()), + ) + .field( + "infifo_cnt_l3_ch4", + &format_args!("{}", self.infifo_cnt_l3_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH4 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFIFO_STATUS_CH4_SPEC; +impl crate::RegisterSpec for INFIFO_STATUS_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`infifo_status_ch4::R`](R) reader structure"] +impl crate::Readable for INFIFO_STATUS_CH4_SPEC {} +#[doc = "`reset()` method sets INFIFO_STATUS_CH4 to value 0x0002_0082"] +impl crate::Resettable for INFIFO_STATUS_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_0082; +} diff --git a/esp32p4/src/h264_dma/infifo_status_ch5.rs b/esp32p4/src/h264_dma/infifo_status_ch5.rs new file mode 100644 index 0000000000..313e01044e --- /dev/null +++ b/esp32p4/src/h264_dma/infifo_status_ch5.rs @@ -0,0 +1,61 @@ +#[doc = "Register `INFIFO_STATUS_CH5` reader"] +pub type R = crate::R; +#[doc = "Field `INFIFO_FULL_L1_CH5` reader - Tx FIFO full signal for Tx channel 1."] +pub type INFIFO_FULL_L1_CH5_R = crate::BitReader; +#[doc = "Field `INFIFO_EMPTY_L1_CH5` reader - Tx FIFO empty signal for Tx channel 1."] +pub type INFIFO_EMPTY_L1_CH5_R = crate::BitReader; +#[doc = "Field `INFIFO_CNT_L1_CH5` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type INFIFO_CNT_L1_CH5_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_full_l1_ch5(&self) -> INFIFO_FULL_L1_CH5_R { + INFIFO_FULL_L1_CH5_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn infifo_empty_l1_ch5(&self) -> INFIFO_EMPTY_L1_CH5_R { + INFIFO_EMPTY_L1_CH5_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:6 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn infifo_cnt_l1_ch5(&self) -> INFIFO_CNT_L1_CH5_R { + INFIFO_CNT_L1_CH5_R::new(((self.bits >> 2) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INFIFO_STATUS_CH5") + .field( + "infifo_full_l1_ch5", + &format_args!("{}", self.infifo_full_l1_ch5().bit()), + ) + .field( + "infifo_empty_l1_ch5", + &format_args!("{}", self.infifo_empty_l1_ch5().bit()), + ) + .field( + "infifo_cnt_l1_ch5", + &format_args!("{}", self.infifo_cnt_l1_ch5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RX CH5 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status_ch5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFIFO_STATUS_CH5_SPEC; +impl crate::RegisterSpec for INFIFO_STATUS_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`infifo_status_ch5::R`](R) reader structure"] +impl crate::Readable for INFIFO_STATUS_CH5_SPEC {} +#[doc = "`reset()` method sets INFIFO_STATUS_CH5 to value 0x02"] +impl crate::Resettable for INFIFO_STATUS_CH5_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/h264_dma/inter_axi_err.rs b/esp32p4/src/h264_dma/inter_axi_err.rs new file mode 100644 index 0000000000..ce95e35564 --- /dev/null +++ b/esp32p4/src/h264_dma/inter_axi_err.rs @@ -0,0 +1,105 @@ +#[doc = "Register `INTER_AXI_ERR` reader"] +pub type R = crate::R; +#[doc = "Field `INTER_RID_ERR_CNT` reader - AXI read id err cnt"] +pub type INTER_RID_ERR_CNT_R = crate::FieldReader; +#[doc = "Field `INTER_RRESP_ERR_CNT` reader - AXI read resp err cnt"] +pub type INTER_RRESP_ERR_CNT_R = crate::FieldReader; +#[doc = "Field `INTER_WRESP_ERR_CNT` reader - AXI write resp err cnt"] +pub type INTER_WRESP_ERR_CNT_R = crate::FieldReader; +#[doc = "Field `INTER_RD_FIFO_CNT` reader - AXI read cmd fifo remain cmd count"] +pub type INTER_RD_FIFO_CNT_R = crate::FieldReader; +#[doc = "Field `INTER_RD_BAK_FIFO_CNT` reader - AXI read backup cmd fifo remain cmd count"] +pub type INTER_RD_BAK_FIFO_CNT_R = crate::FieldReader; +#[doc = "Field `INTER_WR_FIFO_CNT` reader - AXI write cmd fifo remain cmd count"] +pub type INTER_WR_FIFO_CNT_R = crate::FieldReader; +#[doc = "Field `INTER_WR_BAK_FIFO_CNT` reader - AXI write backup cmd fifo remain cmd count"] +pub type INTER_WR_BAK_FIFO_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - AXI read id err cnt"] + #[inline(always)] + pub fn inter_rid_err_cnt(&self) -> INTER_RID_ERR_CNT_R { + INTER_RID_ERR_CNT_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - AXI read resp err cnt"] + #[inline(always)] + pub fn inter_rresp_err_cnt(&self) -> INTER_RRESP_ERR_CNT_R { + INTER_RRESP_ERR_CNT_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - AXI write resp err cnt"] + #[inline(always)] + pub fn inter_wresp_err_cnt(&self) -> INTER_WRESP_ERR_CNT_R { + INTER_WRESP_ERR_CNT_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:14 - AXI read cmd fifo remain cmd count"] + #[inline(always)] + pub fn inter_rd_fifo_cnt(&self) -> INTER_RD_FIFO_CNT_R { + INTER_RD_FIFO_CNT_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:18 - AXI read backup cmd fifo remain cmd count"] + #[inline(always)] + pub fn inter_rd_bak_fifo_cnt(&self) -> INTER_RD_BAK_FIFO_CNT_R { + INTER_RD_BAK_FIFO_CNT_R::new(((self.bits >> 15) & 0x0f) as u8) + } + #[doc = "Bits 19:21 - AXI write cmd fifo remain cmd count"] + #[inline(always)] + pub fn inter_wr_fifo_cnt(&self) -> INTER_WR_FIFO_CNT_R { + INTER_WR_FIFO_CNT_R::new(((self.bits >> 19) & 7) as u8) + } + #[doc = "Bits 22:25 - AXI write backup cmd fifo remain cmd count"] + #[inline(always)] + pub fn inter_wr_bak_fifo_cnt(&self) -> INTER_WR_BAK_FIFO_CNT_R { + INTER_WR_BAK_FIFO_CNT_R::new(((self.bits >> 22) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTER_AXI_ERR") + .field( + "inter_rid_err_cnt", + &format_args!("{}", self.inter_rid_err_cnt().bits()), + ) + .field( + "inter_rresp_err_cnt", + &format_args!("{}", self.inter_rresp_err_cnt().bits()), + ) + .field( + "inter_wresp_err_cnt", + &format_args!("{}", self.inter_wresp_err_cnt().bits()), + ) + .field( + "inter_rd_fifo_cnt", + &format_args!("{}", self.inter_rd_fifo_cnt().bits()), + ) + .field( + "inter_rd_bak_fifo_cnt", + &format_args!("{}", self.inter_rd_bak_fifo_cnt().bits()), + ) + .field( + "inter_wr_fifo_cnt", + &format_args!("{}", self.inter_wr_fifo_cnt().bits()), + ) + .field( + "inter_wr_bak_fifo_cnt", + &format_args!("{}", self.inter_wr_bak_fifo_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "inter memory axi err register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_axi_err::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTER_AXI_ERR_SPEC; +impl crate::RegisterSpec for INTER_AXI_ERR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inter_axi_err::R`](R) reader structure"] +impl crate::Readable for INTER_AXI_ERR_SPEC {} +#[doc = "`reset()` method sets INTER_AXI_ERR to value 0"] +impl crate::Resettable for INTER_AXI_ERR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/inter_mem_end_addr0.rs b/esp32p4/src/h264_dma/inter_mem_end_addr0.rs new file mode 100644 index 0000000000..8f9deabbc4 --- /dev/null +++ b/esp32p4/src/h264_dma/inter_mem_end_addr0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `INTER_MEM_END_ADDR0` reader"] +pub type R = crate::R; +#[doc = "Register `INTER_MEM_END_ADDR0` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_INTER_MEM_END_ADDR0` reader - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_INTER_MEM_END_ADDR0_R = crate::FieldReader; +#[doc = "Field `ACCESS_INTER_MEM_END_ADDR0` writer - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_INTER_MEM_END_ADDR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + pub fn access_inter_mem_end_addr0(&self) -> ACCESS_INTER_MEM_END_ADDR0_R { + ACCESS_INTER_MEM_END_ADDR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTER_MEM_END_ADDR0") + .field( + "access_inter_mem_end_addr0", + &format_args!("{}", self.access_inter_mem_end_addr0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + #[must_use] + pub fn access_inter_mem_end_addr0( + &mut self, + ) -> ACCESS_INTER_MEM_END_ADDR0_W { + ACCESS_INTER_MEM_END_ADDR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "end address of inter memory range0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_mem_end_addr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inter_mem_end_addr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTER_MEM_END_ADDR0_SPEC; +impl crate::RegisterSpec for INTER_MEM_END_ADDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inter_mem_end_addr0::R`](R) reader structure"] +impl crate::Readable for INTER_MEM_END_ADDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inter_mem_end_addr0::W`](W) writer structure"] +impl crate::Writable for INTER_MEM_END_ADDR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTER_MEM_END_ADDR0 to value 0x8fff_ffff"] +impl crate::Resettable for INTER_MEM_END_ADDR0_SPEC { + const RESET_VALUE: Self::Ux = 0x8fff_ffff; +} diff --git a/esp32p4/src/h264_dma/inter_mem_end_addr1.rs b/esp32p4/src/h264_dma/inter_mem_end_addr1.rs new file mode 100644 index 0000000000..f58841d7d6 --- /dev/null +++ b/esp32p4/src/h264_dma/inter_mem_end_addr1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `INTER_MEM_END_ADDR1` reader"] +pub type R = crate::R; +#[doc = "Register `INTER_MEM_END_ADDR1` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_INTER_MEM_END_ADDR1` reader - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_INTER_MEM_END_ADDR1_R = crate::FieldReader; +#[doc = "Field `ACCESS_INTER_MEM_END_ADDR1` writer - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] +pub type ACCESS_INTER_MEM_END_ADDR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + pub fn access_inter_mem_end_addr1(&self) -> ACCESS_INTER_MEM_END_ADDR1_R { + ACCESS_INTER_MEM_END_ADDR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTER_MEM_END_ADDR1") + .field( + "access_inter_mem_end_addr1", + &format_args!("{}", self.access_inter_mem_end_addr1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."] + #[inline(always)] + #[must_use] + pub fn access_inter_mem_end_addr1( + &mut self, + ) -> ACCESS_INTER_MEM_END_ADDR1_W { + ACCESS_INTER_MEM_END_ADDR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "end address of inter memory range1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_mem_end_addr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inter_mem_end_addr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTER_MEM_END_ADDR1_SPEC; +impl crate::RegisterSpec for INTER_MEM_END_ADDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inter_mem_end_addr1::R`](R) reader structure"] +impl crate::Readable for INTER_MEM_END_ADDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inter_mem_end_addr1::W`](W) writer structure"] +impl crate::Writable for INTER_MEM_END_ADDR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTER_MEM_END_ADDR1 to value 0x8fff_ffff"] +impl crate::Resettable for INTER_MEM_END_ADDR1_SPEC { + const RESET_VALUE: Self::Ux = 0x8fff_ffff; +} diff --git a/esp32p4/src/h264_dma/inter_mem_start_addr0.rs b/esp32p4/src/h264_dma/inter_mem_start_addr0.rs new file mode 100644 index 0000000000..9627c4c15c --- /dev/null +++ b/esp32p4/src/h264_dma/inter_mem_start_addr0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `INTER_MEM_START_ADDR0` reader"] +pub type R = crate::R; +#[doc = "Register `INTER_MEM_START_ADDR0` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_INTER_MEM_START_ADDR0` reader - The start address of accessible address space."] +pub type ACCESS_INTER_MEM_START_ADDR0_R = crate::FieldReader; +#[doc = "Field `ACCESS_INTER_MEM_START_ADDR0` writer - The start address of accessible address space."] +pub type ACCESS_INTER_MEM_START_ADDR0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + pub fn access_inter_mem_start_addr0(&self) -> ACCESS_INTER_MEM_START_ADDR0_R { + ACCESS_INTER_MEM_START_ADDR0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTER_MEM_START_ADDR0") + .field( + "access_inter_mem_start_addr0", + &format_args!("{}", self.access_inter_mem_start_addr0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + #[must_use] + pub fn access_inter_mem_start_addr0( + &mut self, + ) -> ACCESS_INTER_MEM_START_ADDR0_W { + ACCESS_INTER_MEM_START_ADDR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Start address of inter memory range0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_mem_start_addr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inter_mem_start_addr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTER_MEM_START_ADDR0_SPEC; +impl crate::RegisterSpec for INTER_MEM_START_ADDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inter_mem_start_addr0::R`](R) reader structure"] +impl crate::Readable for INTER_MEM_START_ADDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inter_mem_start_addr0::W`](W) writer structure"] +impl crate::Writable for INTER_MEM_START_ADDR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTER_MEM_START_ADDR0 to value 0x3010_0000"] +impl crate::Resettable for INTER_MEM_START_ADDR0_SPEC { + const RESET_VALUE: Self::Ux = 0x3010_0000; +} diff --git a/esp32p4/src/h264_dma/inter_mem_start_addr1.rs b/esp32p4/src/h264_dma/inter_mem_start_addr1.rs new file mode 100644 index 0000000000..dac230d09f --- /dev/null +++ b/esp32p4/src/h264_dma/inter_mem_start_addr1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `INTER_MEM_START_ADDR1` reader"] +pub type R = crate::R; +#[doc = "Register `INTER_MEM_START_ADDR1` writer"] +pub type W = crate::W; +#[doc = "Field `ACCESS_INTER_MEM_START_ADDR1` reader - The start address of accessible address space."] +pub type ACCESS_INTER_MEM_START_ADDR1_R = crate::FieldReader; +#[doc = "Field `ACCESS_INTER_MEM_START_ADDR1` writer - The start address of accessible address space."] +pub type ACCESS_INTER_MEM_START_ADDR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + pub fn access_inter_mem_start_addr1(&self) -> ACCESS_INTER_MEM_START_ADDR1_R { + ACCESS_INTER_MEM_START_ADDR1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTER_MEM_START_ADDR1") + .field( + "access_inter_mem_start_addr1", + &format_args!("{}", self.access_inter_mem_start_addr1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The start address of accessible address space."] + #[inline(always)] + #[must_use] + pub fn access_inter_mem_start_addr1( + &mut self, + ) -> ACCESS_INTER_MEM_START_ADDR1_W { + ACCESS_INTER_MEM_START_ADDR1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Start address of inter memory range1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_mem_start_addr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inter_mem_start_addr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTER_MEM_START_ADDR1_SPEC; +impl crate::RegisterSpec for INTER_MEM_START_ADDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inter_mem_start_addr1::R`](R) reader structure"] +impl crate::Readable for INTER_MEM_START_ADDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inter_mem_start_addr1::W`](W) writer structure"] +impl crate::Writable for INTER_MEM_START_ADDR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTER_MEM_START_ADDR1 to value 0x3010_0000"] +impl crate::Resettable for INTER_MEM_START_ADDR1_SPEC { + const RESET_VALUE: Self::Ux = 0x3010_0000; +} diff --git a/esp32p4/src/h264_dma/out_arb_ch0.rs b/esp32p4/src/h264_dma/out_arb_ch0.rs new file mode 100644 index 0000000000..e027497266 --- /dev/null +++ b/esp32p4/src/h264_dma/out_arb_ch0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `OUT_ARB_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_ARB_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_ARB_TOKEN_NUM_CH0` reader - Set the max number of token count of arbiter"] +pub type OUT_ARB_TOKEN_NUM_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_ARB_TOKEN_NUM_CH0` writer - Set the max number of token count of arbiter"] +pub type OUT_ARB_TOKEN_NUM_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `EXTER_OUT_ARB_PRIORITY_CH0` reader - Set the priority of channel"] +pub type EXTER_OUT_ARB_PRIORITY_CH0_R = crate::FieldReader; +#[doc = "Field `EXTER_OUT_ARB_PRIORITY_CH0` writer - Set the priority of channel"] +pub type EXTER_OUT_ARB_PRIORITY_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + pub fn out_arb_token_num_ch0(&self) -> OUT_ARB_TOKEN_NUM_CH0_R { + OUT_ARB_TOKEN_NUM_CH0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + pub fn exter_out_arb_priority_ch0(&self) -> EXTER_OUT_ARB_PRIORITY_CH0_R { + EXTER_OUT_ARB_PRIORITY_CH0_R::new(((self.bits >> 4) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ARB_CH0") + .field( + "out_arb_token_num_ch0", + &format_args!("{}", self.out_arb_token_num_ch0().bits()), + ) + .field( + "exter_out_arb_priority_ch0", + &format_args!("{}", self.exter_out_arb_priority_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + #[must_use] + pub fn out_arb_token_num_ch0(&mut self) -> OUT_ARB_TOKEN_NUM_CH0_W { + OUT_ARB_TOKEN_NUM_CH0_W::new(self, 0) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn exter_out_arb_priority_ch0(&mut self) -> EXTER_OUT_ARB_PRIORITY_CH0_W { + EXTER_OUT_ARB_PRIORITY_CH0_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH0 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ARB_CH0_SPEC; +impl crate::RegisterSpec for OUT_ARB_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_arb_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_ARB_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_arb_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_ARB_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_ARB_CH0 to value 0x11"] +impl crate::Resettable for OUT_ARB_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x11; +} diff --git a/esp32p4/src/h264_dma/out_arb_ch1.rs b/esp32p4/src/h264_dma/out_arb_ch1.rs new file mode 100644 index 0000000000..4218d17b25 --- /dev/null +++ b/esp32p4/src/h264_dma/out_arb_ch1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `OUT_ARB_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_ARB_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_ARB_TOKEN_NUM_CH1` reader - Set the max number of token count of arbiter"] +pub type OUT_ARB_TOKEN_NUM_CH1_R = crate::FieldReader; +#[doc = "Field `OUT_ARB_TOKEN_NUM_CH1` writer - Set the max number of token count of arbiter"] +pub type OUT_ARB_TOKEN_NUM_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `INTER_OUT_ARB_PRIORITY_CH1` reader - Set the priority of channel"] +pub type INTER_OUT_ARB_PRIORITY_CH1_R = crate::BitReader; +#[doc = "Field `INTER_OUT_ARB_PRIORITY_CH1` writer - Set the priority of channel"] +pub type INTER_OUT_ARB_PRIORITY_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + pub fn out_arb_token_num_ch1(&self) -> OUT_ARB_TOKEN_NUM_CH1_R { + OUT_ARB_TOKEN_NUM_CH1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - Set the priority of channel"] + #[inline(always)] + pub fn inter_out_arb_priority_ch1(&self) -> INTER_OUT_ARB_PRIORITY_CH1_R { + INTER_OUT_ARB_PRIORITY_CH1_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ARB_CH1") + .field( + "out_arb_token_num_ch1", + &format_args!("{}", self.out_arb_token_num_ch1().bits()), + ) + .field( + "inter_out_arb_priority_ch1", + &format_args!("{}", self.inter_out_arb_priority_ch1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + #[must_use] + pub fn out_arb_token_num_ch1(&mut self) -> OUT_ARB_TOKEN_NUM_CH1_W { + OUT_ARB_TOKEN_NUM_CH1_W::new(self, 0) + } + #[doc = "Bit 6 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn inter_out_arb_priority_ch1(&mut self) -> INTER_OUT_ARB_PRIORITY_CH1_W { + INTER_OUT_ARB_PRIORITY_CH1_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH1 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ARB_CH1_SPEC; +impl crate::RegisterSpec for OUT_ARB_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_arb_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_ARB_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_arb_ch1::W`](W) writer structure"] +impl crate::Writable for OUT_ARB_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_ARB_CH1 to value 0x41"] +impl crate::Resettable for OUT_ARB_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x41; +} diff --git a/esp32p4/src/h264_dma/out_arb_ch2.rs b/esp32p4/src/h264_dma/out_arb_ch2.rs new file mode 100644 index 0000000000..56354fc30d --- /dev/null +++ b/esp32p4/src/h264_dma/out_arb_ch2.rs @@ -0,0 +1,85 @@ +#[doc = "Register `OUT_ARB_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_ARB_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_ARB_TOKEN_NUM_CH2` reader - Set the max number of token count of arbiter"] +pub type OUT_ARB_TOKEN_NUM_CH2_R = crate::FieldReader; +#[doc = "Field `OUT_ARB_TOKEN_NUM_CH2` writer - Set the max number of token count of arbiter"] +pub type OUT_ARB_TOKEN_NUM_CH2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `INTER_OUT_ARB_PRIORITY_CH2` reader - Set the priority of channel"] +pub type INTER_OUT_ARB_PRIORITY_CH2_R = crate::BitReader; +#[doc = "Field `INTER_OUT_ARB_PRIORITY_CH2` writer - Set the priority of channel"] +pub type INTER_OUT_ARB_PRIORITY_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + pub fn out_arb_token_num_ch2(&self) -> OUT_ARB_TOKEN_NUM_CH2_R { + OUT_ARB_TOKEN_NUM_CH2_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - Set the priority of channel"] + #[inline(always)] + pub fn inter_out_arb_priority_ch2(&self) -> INTER_OUT_ARB_PRIORITY_CH2_R { + INTER_OUT_ARB_PRIORITY_CH2_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ARB_CH2") + .field( + "out_arb_token_num_ch2", + &format_args!("{}", self.out_arb_token_num_ch2().bits()), + ) + .field( + "inter_out_arb_priority_ch2", + &format_args!("{}", self.inter_out_arb_priority_ch2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + #[must_use] + pub fn out_arb_token_num_ch2(&mut self) -> OUT_ARB_TOKEN_NUM_CH2_W { + OUT_ARB_TOKEN_NUM_CH2_W::new(self, 0) + } + #[doc = "Bit 6 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn inter_out_arb_priority_ch2(&mut self) -> INTER_OUT_ARB_PRIORITY_CH2_W { + INTER_OUT_ARB_PRIORITY_CH2_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH2 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ARB_CH2_SPEC; +impl crate::RegisterSpec for OUT_ARB_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_arb_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_ARB_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_arb_ch2::W`](W) writer structure"] +impl crate::Writable for OUT_ARB_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_ARB_CH2 to value 0x41"] +impl crate::Resettable for OUT_ARB_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x41; +} diff --git a/esp32p4/src/h264_dma/out_arb_ch3.rs b/esp32p4/src/h264_dma/out_arb_ch3.rs new file mode 100644 index 0000000000..168816ea72 --- /dev/null +++ b/esp32p4/src/h264_dma/out_arb_ch3.rs @@ -0,0 +1,85 @@ +#[doc = "Register `OUT_ARB_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_ARB_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_ARB_TOKEN_NUM_CH3` reader - Set the max number of token count of arbiter"] +pub type OUT_ARB_TOKEN_NUM_CH3_R = crate::FieldReader; +#[doc = "Field `OUT_ARB_TOKEN_NUM_CH3` writer - Set the max number of token count of arbiter"] +pub type OUT_ARB_TOKEN_NUM_CH3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `EXTER_OUT_ARB_PRIORITY_CH3` reader - Set the priority of channel"] +pub type EXTER_OUT_ARB_PRIORITY_CH3_R = crate::FieldReader; +#[doc = "Field `EXTER_OUT_ARB_PRIORITY_CH3` writer - Set the priority of channel"] +pub type EXTER_OUT_ARB_PRIORITY_CH3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + pub fn out_arb_token_num_ch3(&self) -> OUT_ARB_TOKEN_NUM_CH3_R { + OUT_ARB_TOKEN_NUM_CH3_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + pub fn exter_out_arb_priority_ch3(&self) -> EXTER_OUT_ARB_PRIORITY_CH3_R { + EXTER_OUT_ARB_PRIORITY_CH3_R::new(((self.bits >> 4) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ARB_CH3") + .field( + "out_arb_token_num_ch3", + &format_args!("{}", self.out_arb_token_num_ch3().bits()), + ) + .field( + "exter_out_arb_priority_ch3", + &format_args!("{}", self.exter_out_arb_priority_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + #[must_use] + pub fn out_arb_token_num_ch3(&mut self) -> OUT_ARB_TOKEN_NUM_CH3_W { + OUT_ARB_TOKEN_NUM_CH3_W::new(self, 0) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn exter_out_arb_priority_ch3(&mut self) -> EXTER_OUT_ARB_PRIORITY_CH3_W { + EXTER_OUT_ARB_PRIORITY_CH3_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH3 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ARB_CH3_SPEC; +impl crate::RegisterSpec for OUT_ARB_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_arb_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_ARB_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_arb_ch3::W`](W) writer structure"] +impl crate::Writable for OUT_ARB_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_ARB_CH3 to value 0x11"] +impl crate::Resettable for OUT_ARB_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x11; +} diff --git a/esp32p4/src/h264_dma/out_arb_ch4.rs b/esp32p4/src/h264_dma/out_arb_ch4.rs new file mode 100644 index 0000000000..a7a407f59b --- /dev/null +++ b/esp32p4/src/h264_dma/out_arb_ch4.rs @@ -0,0 +1,85 @@ +#[doc = "Register `OUT_ARB_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_ARB_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_ARB_TOKEN_NUM_CH4` reader - Set the max number of token count of arbiter"] +pub type OUT_ARB_TOKEN_NUM_CH4_R = crate::FieldReader; +#[doc = "Field `OUT_ARB_TOKEN_NUM_CH4` writer - Set the max number of token count of arbiter"] +pub type OUT_ARB_TOKEN_NUM_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `EXTER_OUT_ARB_PRIORITY_CH4` reader - Set the priority of channel"] +pub type EXTER_OUT_ARB_PRIORITY_CH4_R = crate::FieldReader; +#[doc = "Field `EXTER_OUT_ARB_PRIORITY_CH4` writer - Set the priority of channel"] +pub type EXTER_OUT_ARB_PRIORITY_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + pub fn out_arb_token_num_ch4(&self) -> OUT_ARB_TOKEN_NUM_CH4_R { + OUT_ARB_TOKEN_NUM_CH4_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + pub fn exter_out_arb_priority_ch4(&self) -> EXTER_OUT_ARB_PRIORITY_CH4_R { + EXTER_OUT_ARB_PRIORITY_CH4_R::new(((self.bits >> 4) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ARB_CH4") + .field( + "out_arb_token_num_ch4", + &format_args!("{}", self.out_arb_token_num_ch4().bits()), + ) + .field( + "exter_out_arb_priority_ch4", + &format_args!("{}", self.exter_out_arb_priority_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set the max number of token count of arbiter"] + #[inline(always)] + #[must_use] + pub fn out_arb_token_num_ch4(&mut self) -> OUT_ARB_TOKEN_NUM_CH4_W { + OUT_ARB_TOKEN_NUM_CH4_W::new(self, 0) + } + #[doc = "Bits 4:5 - Set the priority of channel"] + #[inline(always)] + #[must_use] + pub fn exter_out_arb_priority_ch4(&mut self) -> EXTER_OUT_ARB_PRIORITY_CH4_W { + EXTER_OUT_ARB_PRIORITY_CH4_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH4 arb register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ARB_CH4_SPEC; +impl crate::RegisterSpec for OUT_ARB_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_arb_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_ARB_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_arb_ch4::W`](W) writer structure"] +impl crate::Writable for OUT_ARB_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_ARB_CH4 to value 0x11"] +impl crate::Resettable for OUT_ARB_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x11; +} diff --git a/esp32p4/src/h264_dma/out_arb_config.rs b/esp32p4/src/h264_dma/out_arb_config.rs new file mode 100644 index 0000000000..9c6369ec04 --- /dev/null +++ b/esp32p4/src/h264_dma/out_arb_config.rs @@ -0,0 +1,85 @@ +#[doc = "Register `OUT_ARB_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_ARB_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_ARB_TIMEOUT_NUM` reader - Set the max number of timeout count of arbiter"] +pub type OUT_ARB_TIMEOUT_NUM_R = crate::FieldReader; +#[doc = "Field `OUT_ARB_TIMEOUT_NUM` writer - Set the max number of timeout count of arbiter"] +pub type OUT_ARB_TIMEOUT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `OUT_WEIGHT_EN` reader - reserved"] +pub type OUT_WEIGHT_EN_R = crate::BitReader; +#[doc = "Field `OUT_WEIGHT_EN` writer - reserved"] +pub type OUT_WEIGHT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Set the max number of timeout count of arbiter"] + #[inline(always)] + pub fn out_arb_timeout_num(&self) -> OUT_ARB_TIMEOUT_NUM_R { + OUT_ARB_TIMEOUT_NUM_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - reserved"] + #[inline(always)] + pub fn out_weight_en(&self) -> OUT_WEIGHT_EN_R { + OUT_WEIGHT_EN_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ARB_CONFIG") + .field( + "out_arb_timeout_num", + &format_args!("{}", self.out_arb_timeout_num().bits()), + ) + .field( + "out_weight_en", + &format_args!("{}", self.out_weight_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Set the max number of timeout count of arbiter"] + #[inline(always)] + #[must_use] + pub fn out_arb_timeout_num(&mut self) -> OUT_ARB_TIMEOUT_NUM_W { + OUT_ARB_TIMEOUT_NUM_W::new(self, 0) + } + #[doc = "Bit 16 - reserved"] + #[inline(always)] + #[must_use] + pub fn out_weight_en(&mut self) -> OUT_WEIGHT_EN_W { + OUT_WEIGHT_EN_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_arb_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_arb_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ARB_CONFIG_SPEC; +impl crate::RegisterSpec for OUT_ARB_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_arb_config::R`](R) reader structure"] +impl crate::Readable for OUT_ARB_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_arb_config::W`](W) writer structure"] +impl crate::Writable for OUT_ARB_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_ARB_CONFIG to value 0"] +impl crate::Resettable for OUT_ARB_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_block_buf_len_ch3.rs b/esp32p4/src/h264_dma/out_block_buf_len_ch3.rs new file mode 100644 index 0000000000..06755541f8 --- /dev/null +++ b/esp32p4/src/h264_dma/out_block_buf_len_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_BLOCK_BUF_LEN_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_BLOCK_BUF_LEN_CH3` reader - only for debug"] +pub type OUT_BLOCK_BUF_LEN_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:27 - only for debug"] + #[inline(always)] + pub fn out_block_buf_len_ch3(&self) -> OUT_BLOCK_BUF_LEN_CH3_R { + OUT_BLOCK_BUF_LEN_CH3_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_BLOCK_BUF_LEN_CH3") + .field( + "out_block_buf_len_ch3", + &format_args!("{}", self.out_block_buf_len_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH3 block buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_block_buf_len_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_BLOCK_BUF_LEN_CH3_SPEC; +impl crate::RegisterSpec for OUT_BLOCK_BUF_LEN_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_block_buf_len_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_BLOCK_BUF_LEN_CH3_SPEC {} +#[doc = "`reset()` method sets OUT_BLOCK_BUF_LEN_CH3 to value 0"] +impl crate::Resettable for OUT_BLOCK_BUF_LEN_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_block_buf_len_ch4.rs b/esp32p4/src/h264_dma/out_block_buf_len_ch4.rs new file mode 100644 index 0000000000..2bf8ddd97e --- /dev/null +++ b/esp32p4/src/h264_dma/out_block_buf_len_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_BLOCK_BUF_LEN_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_BLOCK_BUF_LEN_CH4` reader - only for debug"] +pub type OUT_BLOCK_BUF_LEN_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:27 - only for debug"] + #[inline(always)] + pub fn out_block_buf_len_ch4(&self) -> OUT_BLOCK_BUF_LEN_CH4_R { + OUT_BLOCK_BUF_LEN_CH4_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_BLOCK_BUF_LEN_CH4") + .field( + "out_block_buf_len_ch4", + &format_args!("{}", self.out_block_buf_len_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH4 block buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_block_buf_len_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_BLOCK_BUF_LEN_CH4_SPEC; +impl crate::RegisterSpec for OUT_BLOCK_BUF_LEN_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_block_buf_len_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_BLOCK_BUF_LEN_CH4_SPEC {} +#[doc = "`reset()` method sets OUT_BLOCK_BUF_LEN_CH4 to value 0"] +impl crate::Resettable for OUT_BLOCK_BUF_LEN_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_buf_len_ch0.rs b/esp32p4/src/h264_dma/out_buf_len_ch0.rs new file mode 100644 index 0000000000..2248d9b49f --- /dev/null +++ b/esp32p4/src/h264_dma/out_buf_len_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_BUF_LEN_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_BUF_LEN_HB_CH0` reader - only for debug"] +pub type OUT_CMDFIFO_BUF_LEN_HB_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_buf_len_hb_ch0(&self) -> OUT_CMDFIFO_BUF_LEN_HB_CH0_R { + OUT_CMDFIFO_BUF_LEN_HB_CH0_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_BUF_LEN_CH0") + .field( + "out_cmdfifo_buf_len_hb_ch0", + &format_args!("{}", self.out_cmdfifo_buf_len_hb_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH0 buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_buf_len_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_BUF_LEN_CH0_SPEC; +impl crate::RegisterSpec for OUT_BUF_LEN_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_buf_len_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_BUF_LEN_CH0_SPEC {} +#[doc = "`reset()` method sets OUT_BUF_LEN_CH0 to value 0"] +impl crate::Resettable for OUT_BUF_LEN_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_buf_len_ch1.rs b/esp32p4/src/h264_dma/out_buf_len_ch1.rs new file mode 100644 index 0000000000..8ef13801d4 --- /dev/null +++ b/esp32p4/src/h264_dma/out_buf_len_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_BUF_LEN_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_BUF_LEN_HB_CH1` reader - only for debug"] +pub type OUT_CMDFIFO_BUF_LEN_HB_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_buf_len_hb_ch1(&self) -> OUT_CMDFIFO_BUF_LEN_HB_CH1_R { + OUT_CMDFIFO_BUF_LEN_HB_CH1_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_BUF_LEN_CH1") + .field( + "out_cmdfifo_buf_len_hb_ch1", + &format_args!("{}", self.out_cmdfifo_buf_len_hb_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH1 buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_buf_len_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_BUF_LEN_CH1_SPEC; +impl crate::RegisterSpec for OUT_BUF_LEN_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_buf_len_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_BUF_LEN_CH1_SPEC {} +#[doc = "`reset()` method sets OUT_BUF_LEN_CH1 to value 0"] +impl crate::Resettable for OUT_BUF_LEN_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_buf_len_ch2.rs b/esp32p4/src/h264_dma/out_buf_len_ch2.rs new file mode 100644 index 0000000000..81438147d9 --- /dev/null +++ b/esp32p4/src/h264_dma/out_buf_len_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_BUF_LEN_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_BUF_LEN_HB_CH2` reader - only for debug"] +pub type OUT_CMDFIFO_BUF_LEN_HB_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_buf_len_hb_ch2(&self) -> OUT_CMDFIFO_BUF_LEN_HB_CH2_R { + OUT_CMDFIFO_BUF_LEN_HB_CH2_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_BUF_LEN_CH2") + .field( + "out_cmdfifo_buf_len_hb_ch2", + &format_args!("{}", self.out_cmdfifo_buf_len_hb_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH2 buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_buf_len_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_BUF_LEN_CH2_SPEC; +impl crate::RegisterSpec for OUT_BUF_LEN_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_buf_len_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_BUF_LEN_CH2_SPEC {} +#[doc = "`reset()` method sets OUT_BUF_LEN_CH2 to value 0"] +impl crate::Resettable for OUT_BUF_LEN_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_buf_len_ch3.rs b/esp32p4/src/h264_dma/out_buf_len_ch3.rs new file mode 100644 index 0000000000..d633dae035 --- /dev/null +++ b/esp32p4/src/h264_dma/out_buf_len_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_BUF_LEN_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_BUF_LEN_HB_CH3` reader - only for debug"] +pub type OUT_CMDFIFO_BUF_LEN_HB_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_buf_len_hb_ch3(&self) -> OUT_CMDFIFO_BUF_LEN_HB_CH3_R { + OUT_CMDFIFO_BUF_LEN_HB_CH3_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_BUF_LEN_CH3") + .field( + "out_cmdfifo_buf_len_hb_ch3", + &format_args!("{}", self.out_cmdfifo_buf_len_hb_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH3 buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_buf_len_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_BUF_LEN_CH3_SPEC; +impl crate::RegisterSpec for OUT_BUF_LEN_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_buf_len_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_BUF_LEN_CH3_SPEC {} +#[doc = "`reset()` method sets OUT_BUF_LEN_CH3 to value 0"] +impl crate::Resettable for OUT_BUF_LEN_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_buf_len_ch4.rs b/esp32p4/src/h264_dma/out_buf_len_ch4.rs new file mode 100644 index 0000000000..0548d18403 --- /dev/null +++ b/esp32p4/src/h264_dma/out_buf_len_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_BUF_LEN_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_BUF_LEN_HB_CH4` reader - only for debug"] +pub type OUT_CMDFIFO_BUF_LEN_HB_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_buf_len_hb_ch4(&self) -> OUT_CMDFIFO_BUF_LEN_HB_CH4_R { + OUT_CMDFIFO_BUF_LEN_HB_CH4_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_BUF_LEN_CH4") + .field( + "out_cmdfifo_buf_len_hb_ch4", + &format_args!("{}", self.out_cmdfifo_buf_len_hb_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH4 buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_buf_len_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_BUF_LEN_CH4_SPEC; +impl crate::RegisterSpec for OUT_BUF_LEN_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_buf_len_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_BUF_LEN_CH4_SPEC {} +#[doc = "`reset()` method sets OUT_BUF_LEN_CH4 to value 0"] +impl crate::Resettable for OUT_BUF_LEN_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_conf0_ch0.rs b/esp32p4/src/h264_dma/out_conf0_ch0.rs new file mode 100644 index 0000000000..e799541d42 --- /dev/null +++ b/esp32p4/src/h264_dma/out_conf0_ch0.rs @@ -0,0 +1,255 @@ +#[doc = "Register `OUT_CONF0_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF0_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_AUTO_WRBACK_CH0` reader - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] +pub type OUT_AUTO_WRBACK_CH0_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK_CH0` writer - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] +pub type OUT_AUTO_WRBACK_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_MODE_CH0` reader - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_CH0_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE_CH0` writer - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTDSCR_BURST_EN_CH0` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN_CH0` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ECC_AES_EN_CH0` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type OUT_ECC_AES_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUT_ECC_AES_EN_CH0` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type OUT_ECC_AES_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_CHECK_OWNER_CH0` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH0_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER_CH0` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_MEM_BURST_LENGTH_CH0` reader - Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type OUT_MEM_BURST_LENGTH_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_MEM_BURST_LENGTH_CH0` writer - Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type OUT_MEM_BURST_LENGTH_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OUT_PAGE_BOUND_EN_CH0` reader - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] +pub type OUT_PAGE_BOUND_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUT_PAGE_BOUND_EN_CH0` writer - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] +pub type OUT_PAGE_BOUND_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_REORDER_EN_CH0` reader - Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection"] +pub type OUT_REORDER_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUT_REORDER_EN_CH0` writer - Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection"] +pub type OUT_REORDER_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_RST_CH0` reader - Write 1 then write 0 to this bit to reset TX channel"] +pub type OUT_RST_CH0_R = crate::BitReader; +#[doc = "Field `OUT_RST_CH0` writer - Write 1 then write 0 to this bit to reset TX channel"] +pub type OUT_RST_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_CMD_DISABLE_CH0` reader - Write 1 before reset and write 0 after reset"] +pub type OUT_CMD_DISABLE_CH0_R = crate::BitReader; +#[doc = "Field `OUT_CMD_DISABLE_CH0` writer - Write 1 before reset and write 0 after reset"] +pub type OUT_CMD_DISABLE_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ARB_WEIGHT_OPT_DIS_CH0` reader - Set this bit to 1 to disable arbiter optimum weight function."] +pub type OUT_ARB_WEIGHT_OPT_DIS_CH0_R = crate::BitReader; +#[doc = "Field `OUT_ARB_WEIGHT_OPT_DIS_CH0` writer - Set this bit to 1 to disable arbiter optimum weight function."] +pub type OUT_ARB_WEIGHT_OPT_DIS_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] + #[inline(always)] + pub fn out_auto_wrback_ch0(&self) -> OUT_AUTO_WRBACK_CH0_R { + OUT_AUTO_WRBACK_CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] + #[inline(always)] + pub fn out_eof_mode_ch0(&self) -> OUT_EOF_MODE_CH0_R { + OUT_EOF_MODE_CH0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn outdscr_burst_en_ch0(&self) -> OUTDSCR_BURST_EN_CH0_R { + OUTDSCR_BURST_EN_CH0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + pub fn out_ecc_aes_en_ch0(&self) -> OUT_ECC_AES_EN_CH0_R { + OUT_ECC_AES_EN_CH0_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn out_check_owner_ch0(&self) -> OUT_CHECK_OWNER_CH0_R { + OUT_CHECK_OWNER_CH0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 6:8 - Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + pub fn out_mem_burst_length_ch0(&self) -> OUT_MEM_BURST_LENGTH_CH0_R { + OUT_MEM_BURST_LENGTH_CH0_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + pub fn out_page_bound_en_ch0(&self) -> OUT_PAGE_BOUND_EN_CH0_R { + OUT_PAGE_BOUND_EN_CH0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection"] + #[inline(always)] + pub fn out_reorder_en_ch0(&self) -> OUT_REORDER_EN_CH0_R { + OUT_REORDER_EN_CH0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset TX channel"] + #[inline(always)] + pub fn out_rst_ch0(&self) -> OUT_RST_CH0_R { + OUT_RST_CH0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + pub fn out_cmd_disable_ch0(&self) -> OUT_CMD_DISABLE_CH0_R { + OUT_CMD_DISABLE_CH0_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + pub fn out_arb_weight_opt_dis_ch0(&self) -> OUT_ARB_WEIGHT_OPT_DIS_CH0_R { + OUT_ARB_WEIGHT_OPT_DIS_CH0_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF0_CH0") + .field( + "out_auto_wrback_ch0", + &format_args!("{}", self.out_auto_wrback_ch0().bit()), + ) + .field( + "out_eof_mode_ch0", + &format_args!("{}", self.out_eof_mode_ch0().bit()), + ) + .field( + "outdscr_burst_en_ch0", + &format_args!("{}", self.outdscr_burst_en_ch0().bit()), + ) + .field( + "out_ecc_aes_en_ch0", + &format_args!("{}", self.out_ecc_aes_en_ch0().bit()), + ) + .field( + "out_check_owner_ch0", + &format_args!("{}", self.out_check_owner_ch0().bit()), + ) + .field( + "out_mem_burst_length_ch0", + &format_args!("{}", self.out_mem_burst_length_ch0().bits()), + ) + .field( + "out_page_bound_en_ch0", + &format_args!("{}", self.out_page_bound_en_ch0().bit()), + ) + .field( + "out_reorder_en_ch0", + &format_args!("{}", self.out_reorder_en_ch0().bit()), + ) + .field("out_rst_ch0", &format_args!("{}", self.out_rst_ch0().bit())) + .field( + "out_cmd_disable_ch0", + &format_args!("{}", self.out_cmd_disable_ch0().bit()), + ) + .field( + "out_arb_weight_opt_dis_ch0", + &format_args!("{}", self.out_arb_weight_opt_dis_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] + #[inline(always)] + #[must_use] + pub fn out_auto_wrback_ch0(&mut self) -> OUT_AUTO_WRBACK_CH0_W { + OUT_AUTO_WRBACK_CH0_W::new(self, 0) + } + #[doc = "Bit 1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] + #[inline(always)] + #[must_use] + pub fn out_eof_mode_ch0(&mut self) -> OUT_EOF_MODE_CH0_W { + OUT_EOF_MODE_CH0_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn outdscr_burst_en_ch0(&mut self) -> OUTDSCR_BURST_EN_CH0_W { + OUTDSCR_BURST_EN_CH0_W::new(self, 2) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + #[must_use] + pub fn out_ecc_aes_en_ch0(&mut self) -> OUT_ECC_AES_EN_CH0_W { + OUT_ECC_AES_EN_CH0_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn out_check_owner_ch0(&mut self) -> OUT_CHECK_OWNER_CH0_W { + OUT_CHECK_OWNER_CH0_W::new(self, 4) + } + #[doc = "Bits 6:8 - Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + #[must_use] + pub fn out_mem_burst_length_ch0(&mut self) -> OUT_MEM_BURST_LENGTH_CH0_W { + OUT_MEM_BURST_LENGTH_CH0_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + #[must_use] + pub fn out_page_bound_en_ch0(&mut self) -> OUT_PAGE_BOUND_EN_CH0_W { + OUT_PAGE_BOUND_EN_CH0_W::new(self, 12) + } + #[doc = "Bit 16 - Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection"] + #[inline(always)] + #[must_use] + pub fn out_reorder_en_ch0(&mut self) -> OUT_REORDER_EN_CH0_W { + OUT_REORDER_EN_CH0_W::new(self, 16) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset TX channel"] + #[inline(always)] + #[must_use] + pub fn out_rst_ch0(&mut self) -> OUT_RST_CH0_W { + OUT_RST_CH0_W::new(self, 24) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + #[must_use] + pub fn out_cmd_disable_ch0(&mut self) -> OUT_CMD_DISABLE_CH0_W { + OUT_CMD_DISABLE_CH0_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + #[must_use] + pub fn out_arb_weight_opt_dis_ch0( + &mut self, + ) -> OUT_ARB_WEIGHT_OPT_DIS_CH0_W { + OUT_ARB_WEIGHT_OPT_DIS_CH0_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH0 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF0_CH0_SPEC; +impl crate::RegisterSpec for OUT_CONF0_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf0_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_CONF0_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf0_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_CONF0_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF0_CH0 to value 0x02"] +impl crate::Resettable for OUT_CONF0_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/h264_dma/out_conf0_ch1.rs b/esp32p4/src/h264_dma/out_conf0_ch1.rs new file mode 100644 index 0000000000..41690f6dcc --- /dev/null +++ b/esp32p4/src/h264_dma/out_conf0_ch1.rs @@ -0,0 +1,236 @@ +#[doc = "Register `OUT_CONF0_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF0_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_AUTO_WRBACK_CH1` reader - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] +pub type OUT_AUTO_WRBACK_CH1_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK_CH1` writer - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] +pub type OUT_AUTO_WRBACK_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_MODE_CH1` reader - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_CH1_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE_CH1` writer - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTDSCR_BURST_EN_CH1` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH1_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN_CH1` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ECC_AES_EN_CH1` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type OUT_ECC_AES_EN_CH1_R = crate::BitReader; +#[doc = "Field `OUT_ECC_AES_EN_CH1` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type OUT_ECC_AES_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_CHECK_OWNER_CH1` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH1_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER_CH1` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_MEM_BURST_LENGTH_CH1` reader - Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 64 bytes"] +pub type OUT_MEM_BURST_LENGTH_CH1_R = crate::FieldReader; +#[doc = "Field `OUT_MEM_BURST_LENGTH_CH1` writer - Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 64 bytes"] +pub type OUT_MEM_BURST_LENGTH_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OUT_PAGE_BOUND_EN_CH1` reader - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] +pub type OUT_PAGE_BOUND_EN_CH1_R = crate::BitReader; +#[doc = "Field `OUT_PAGE_BOUND_EN_CH1` writer - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] +pub type OUT_PAGE_BOUND_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_RST_CH1` reader - Write 1 then write 0 to this bit to reset TX channel"] +pub type OUT_RST_CH1_R = crate::BitReader; +#[doc = "Field `OUT_RST_CH1` writer - Write 1 then write 0 to this bit to reset TX channel"] +pub type OUT_RST_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_CMD_DISABLE_CH1` reader - Write 1 before reset and write 0 after reset"] +pub type OUT_CMD_DISABLE_CH1_R = crate::BitReader; +#[doc = "Field `OUT_CMD_DISABLE_CH1` writer - Write 1 before reset and write 0 after reset"] +pub type OUT_CMD_DISABLE_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ARB_WEIGHT_OPT_DIS_CH1` reader - Set this bit to 1 to disable arbiter optimum weight function."] +pub type OUT_ARB_WEIGHT_OPT_DIS_CH1_R = crate::BitReader; +#[doc = "Field `OUT_ARB_WEIGHT_OPT_DIS_CH1` writer - Set this bit to 1 to disable arbiter optimum weight function."] +pub type OUT_ARB_WEIGHT_OPT_DIS_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] + #[inline(always)] + pub fn out_auto_wrback_ch1(&self) -> OUT_AUTO_WRBACK_CH1_R { + OUT_AUTO_WRBACK_CH1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] + #[inline(always)] + pub fn out_eof_mode_ch1(&self) -> OUT_EOF_MODE_CH1_R { + OUT_EOF_MODE_CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn outdscr_burst_en_ch1(&self) -> OUTDSCR_BURST_EN_CH1_R { + OUTDSCR_BURST_EN_CH1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + pub fn out_ecc_aes_en_ch1(&self) -> OUT_ECC_AES_EN_CH1_R { + OUT_ECC_AES_EN_CH1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn out_check_owner_ch1(&self) -> OUT_CHECK_OWNER_CH1_R { + OUT_CHECK_OWNER_CH1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 6:8 - Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 64 bytes"] + #[inline(always)] + pub fn out_mem_burst_length_ch1(&self) -> OUT_MEM_BURST_LENGTH_CH1_R { + OUT_MEM_BURST_LENGTH_CH1_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + pub fn out_page_bound_en_ch1(&self) -> OUT_PAGE_BOUND_EN_CH1_R { + OUT_PAGE_BOUND_EN_CH1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset TX channel"] + #[inline(always)] + pub fn out_rst_ch1(&self) -> OUT_RST_CH1_R { + OUT_RST_CH1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + pub fn out_cmd_disable_ch1(&self) -> OUT_CMD_DISABLE_CH1_R { + OUT_CMD_DISABLE_CH1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + pub fn out_arb_weight_opt_dis_ch1(&self) -> OUT_ARB_WEIGHT_OPT_DIS_CH1_R { + OUT_ARB_WEIGHT_OPT_DIS_CH1_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF0_CH1") + .field( + "out_auto_wrback_ch1", + &format_args!("{}", self.out_auto_wrback_ch1().bit()), + ) + .field( + "out_eof_mode_ch1", + &format_args!("{}", self.out_eof_mode_ch1().bit()), + ) + .field( + "outdscr_burst_en_ch1", + &format_args!("{}", self.outdscr_burst_en_ch1().bit()), + ) + .field( + "out_ecc_aes_en_ch1", + &format_args!("{}", self.out_ecc_aes_en_ch1().bit()), + ) + .field( + "out_check_owner_ch1", + &format_args!("{}", self.out_check_owner_ch1().bit()), + ) + .field( + "out_mem_burst_length_ch1", + &format_args!("{}", self.out_mem_burst_length_ch1().bits()), + ) + .field( + "out_page_bound_en_ch1", + &format_args!("{}", self.out_page_bound_en_ch1().bit()), + ) + .field("out_rst_ch1", &format_args!("{}", self.out_rst_ch1().bit())) + .field( + "out_cmd_disable_ch1", + &format_args!("{}", self.out_cmd_disable_ch1().bit()), + ) + .field( + "out_arb_weight_opt_dis_ch1", + &format_args!("{}", self.out_arb_weight_opt_dis_ch1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] + #[inline(always)] + #[must_use] + pub fn out_auto_wrback_ch1(&mut self) -> OUT_AUTO_WRBACK_CH1_W { + OUT_AUTO_WRBACK_CH1_W::new(self, 0) + } + #[doc = "Bit 1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] + #[inline(always)] + #[must_use] + pub fn out_eof_mode_ch1(&mut self) -> OUT_EOF_MODE_CH1_W { + OUT_EOF_MODE_CH1_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn outdscr_burst_en_ch1(&mut self) -> OUTDSCR_BURST_EN_CH1_W { + OUTDSCR_BURST_EN_CH1_W::new(self, 2) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + #[must_use] + pub fn out_ecc_aes_en_ch1(&mut self) -> OUT_ECC_AES_EN_CH1_W { + OUT_ECC_AES_EN_CH1_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn out_check_owner_ch1(&mut self) -> OUT_CHECK_OWNER_CH1_W { + OUT_CHECK_OWNER_CH1_W::new(self, 4) + } + #[doc = "Bits 6:8 - Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 64 bytes"] + #[inline(always)] + #[must_use] + pub fn out_mem_burst_length_ch1(&mut self) -> OUT_MEM_BURST_LENGTH_CH1_W { + OUT_MEM_BURST_LENGTH_CH1_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + #[must_use] + pub fn out_page_bound_en_ch1(&mut self) -> OUT_PAGE_BOUND_EN_CH1_W { + OUT_PAGE_BOUND_EN_CH1_W::new(self, 12) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset TX channel"] + #[inline(always)] + #[must_use] + pub fn out_rst_ch1(&mut self) -> OUT_RST_CH1_W { + OUT_RST_CH1_W::new(self, 24) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + #[must_use] + pub fn out_cmd_disable_ch1(&mut self) -> OUT_CMD_DISABLE_CH1_W { + OUT_CMD_DISABLE_CH1_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + #[must_use] + pub fn out_arb_weight_opt_dis_ch1( + &mut self, + ) -> OUT_ARB_WEIGHT_OPT_DIS_CH1_W { + OUT_ARB_WEIGHT_OPT_DIS_CH1_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH1 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF0_CH1_SPEC; +impl crate::RegisterSpec for OUT_CONF0_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf0_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_CONF0_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf0_ch1::W`](W) writer structure"] +impl crate::Writable for OUT_CONF0_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF0_CH1 to value 0x02"] +impl crate::Resettable for OUT_CONF0_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/h264_dma/out_conf0_ch2.rs b/esp32p4/src/h264_dma/out_conf0_ch2.rs new file mode 100644 index 0000000000..af66090324 --- /dev/null +++ b/esp32p4/src/h264_dma/out_conf0_ch2.rs @@ -0,0 +1,236 @@ +#[doc = "Register `OUT_CONF0_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF0_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_AUTO_WRBACK_CH2` reader - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] +pub type OUT_AUTO_WRBACK_CH2_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK_CH2` writer - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] +pub type OUT_AUTO_WRBACK_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_MODE_CH2` reader - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_CH2_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE_CH2` writer - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTDSCR_BURST_EN_CH2` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH2_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN_CH2` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ECC_AES_EN_CH2` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type OUT_ECC_AES_EN_CH2_R = crate::BitReader; +#[doc = "Field `OUT_ECC_AES_EN_CH2` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type OUT_ECC_AES_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_CHECK_OWNER_CH2` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH2_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER_CH2` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_MEM_BURST_LENGTH_CH2` reader - Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type OUT_MEM_BURST_LENGTH_CH2_R = crate::FieldReader; +#[doc = "Field `OUT_MEM_BURST_LENGTH_CH2` writer - Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type OUT_MEM_BURST_LENGTH_CH2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OUT_PAGE_BOUND_EN_CH2` reader - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] +pub type OUT_PAGE_BOUND_EN_CH2_R = crate::BitReader; +#[doc = "Field `OUT_PAGE_BOUND_EN_CH2` writer - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] +pub type OUT_PAGE_BOUND_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_RST_CH2` reader - Write 1 then write 0 to this bit to reset TX channel"] +pub type OUT_RST_CH2_R = crate::BitReader; +#[doc = "Field `OUT_RST_CH2` writer - Write 1 then write 0 to this bit to reset TX channel"] +pub type OUT_RST_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_CMD_DISABLE_CH2` reader - Write 1 before reset and write 0 after reset"] +pub type OUT_CMD_DISABLE_CH2_R = crate::BitReader; +#[doc = "Field `OUT_CMD_DISABLE_CH2` writer - Write 1 before reset and write 0 after reset"] +pub type OUT_CMD_DISABLE_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ARB_WEIGHT_OPT_DIS_CH2` reader - Set this bit to 1 to disable arbiter optimum weight function."] +pub type OUT_ARB_WEIGHT_OPT_DIS_CH2_R = crate::BitReader; +#[doc = "Field `OUT_ARB_WEIGHT_OPT_DIS_CH2` writer - Set this bit to 1 to disable arbiter optimum weight function."] +pub type OUT_ARB_WEIGHT_OPT_DIS_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] + #[inline(always)] + pub fn out_auto_wrback_ch2(&self) -> OUT_AUTO_WRBACK_CH2_R { + OUT_AUTO_WRBACK_CH2_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] + #[inline(always)] + pub fn out_eof_mode_ch2(&self) -> OUT_EOF_MODE_CH2_R { + OUT_EOF_MODE_CH2_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn outdscr_burst_en_ch2(&self) -> OUTDSCR_BURST_EN_CH2_R { + OUTDSCR_BURST_EN_CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + pub fn out_ecc_aes_en_ch2(&self) -> OUT_ECC_AES_EN_CH2_R { + OUT_ECC_AES_EN_CH2_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn out_check_owner_ch2(&self) -> OUT_CHECK_OWNER_CH2_R { + OUT_CHECK_OWNER_CH2_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 6:8 - Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + pub fn out_mem_burst_length_ch2(&self) -> OUT_MEM_BURST_LENGTH_CH2_R { + OUT_MEM_BURST_LENGTH_CH2_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + pub fn out_page_bound_en_ch2(&self) -> OUT_PAGE_BOUND_EN_CH2_R { + OUT_PAGE_BOUND_EN_CH2_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset TX channel"] + #[inline(always)] + pub fn out_rst_ch2(&self) -> OUT_RST_CH2_R { + OUT_RST_CH2_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + pub fn out_cmd_disable_ch2(&self) -> OUT_CMD_DISABLE_CH2_R { + OUT_CMD_DISABLE_CH2_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + pub fn out_arb_weight_opt_dis_ch2(&self) -> OUT_ARB_WEIGHT_OPT_DIS_CH2_R { + OUT_ARB_WEIGHT_OPT_DIS_CH2_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF0_CH2") + .field( + "out_auto_wrback_ch2", + &format_args!("{}", self.out_auto_wrback_ch2().bit()), + ) + .field( + "out_eof_mode_ch2", + &format_args!("{}", self.out_eof_mode_ch2().bit()), + ) + .field( + "outdscr_burst_en_ch2", + &format_args!("{}", self.outdscr_burst_en_ch2().bit()), + ) + .field( + "out_ecc_aes_en_ch2", + &format_args!("{}", self.out_ecc_aes_en_ch2().bit()), + ) + .field( + "out_check_owner_ch2", + &format_args!("{}", self.out_check_owner_ch2().bit()), + ) + .field( + "out_mem_burst_length_ch2", + &format_args!("{}", self.out_mem_burst_length_ch2().bits()), + ) + .field( + "out_page_bound_en_ch2", + &format_args!("{}", self.out_page_bound_en_ch2().bit()), + ) + .field("out_rst_ch2", &format_args!("{}", self.out_rst_ch2().bit())) + .field( + "out_cmd_disable_ch2", + &format_args!("{}", self.out_cmd_disable_ch2().bit()), + ) + .field( + "out_arb_weight_opt_dis_ch2", + &format_args!("{}", self.out_arb_weight_opt_dis_ch2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] + #[inline(always)] + #[must_use] + pub fn out_auto_wrback_ch2(&mut self) -> OUT_AUTO_WRBACK_CH2_W { + OUT_AUTO_WRBACK_CH2_W::new(self, 0) + } + #[doc = "Bit 1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] + #[inline(always)] + #[must_use] + pub fn out_eof_mode_ch2(&mut self) -> OUT_EOF_MODE_CH2_W { + OUT_EOF_MODE_CH2_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn outdscr_burst_en_ch2(&mut self) -> OUTDSCR_BURST_EN_CH2_W { + OUTDSCR_BURST_EN_CH2_W::new(self, 2) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + #[must_use] + pub fn out_ecc_aes_en_ch2(&mut self) -> OUT_ECC_AES_EN_CH2_W { + OUT_ECC_AES_EN_CH2_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn out_check_owner_ch2(&mut self) -> OUT_CHECK_OWNER_CH2_W { + OUT_CHECK_OWNER_CH2_W::new(self, 4) + } + #[doc = "Bits 6:8 - Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + #[must_use] + pub fn out_mem_burst_length_ch2(&mut self) -> OUT_MEM_BURST_LENGTH_CH2_W { + OUT_MEM_BURST_LENGTH_CH2_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + #[must_use] + pub fn out_page_bound_en_ch2(&mut self) -> OUT_PAGE_BOUND_EN_CH2_W { + OUT_PAGE_BOUND_EN_CH2_W::new(self, 12) + } + #[doc = "Bit 24 - Write 1 then write 0 to this bit to reset TX channel"] + #[inline(always)] + #[must_use] + pub fn out_rst_ch2(&mut self) -> OUT_RST_CH2_W { + OUT_RST_CH2_W::new(self, 24) + } + #[doc = "Bit 25 - Write 1 before reset and write 0 after reset"] + #[inline(always)] + #[must_use] + pub fn out_cmd_disable_ch2(&mut self) -> OUT_CMD_DISABLE_CH2_W { + OUT_CMD_DISABLE_CH2_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + #[must_use] + pub fn out_arb_weight_opt_dis_ch2( + &mut self, + ) -> OUT_ARB_WEIGHT_OPT_DIS_CH2_W { + OUT_ARB_WEIGHT_OPT_DIS_CH2_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH2 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF0_CH2_SPEC; +impl crate::RegisterSpec for OUT_CONF0_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf0_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_CONF0_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf0_ch2::W`](W) writer structure"] +impl crate::Writable for OUT_CONF0_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF0_CH2 to value 0x02"] +impl crate::Resettable for OUT_CONF0_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/h264_dma/out_conf0_ch3.rs b/esp32p4/src/h264_dma/out_conf0_ch3.rs new file mode 100644 index 0000000000..5a0be914cc --- /dev/null +++ b/esp32p4/src/h264_dma/out_conf0_ch3.rs @@ -0,0 +1,201 @@ +#[doc = "Register `OUT_CONF0_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF0_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_AUTO_WRBACK_CH3` reader - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] +pub type OUT_AUTO_WRBACK_CH3_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK_CH3` writer - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] +pub type OUT_AUTO_WRBACK_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_MODE_CH3` reader - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_CH3_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE_CH3` writer - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTDSCR_BURST_EN_CH3` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH3_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN_CH3` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ECC_AES_EN_CH3` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type OUT_ECC_AES_EN_CH3_R = crate::BitReader; +#[doc = "Field `OUT_ECC_AES_EN_CH3` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type OUT_ECC_AES_EN_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_CHECK_OWNER_CH3` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH3_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER_CH3` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_MEM_BURST_LENGTH_CH3` reader - Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type OUT_MEM_BURST_LENGTH_CH3_R = crate::FieldReader; +#[doc = "Field `OUT_MEM_BURST_LENGTH_CH3` writer - Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type OUT_MEM_BURST_LENGTH_CH3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OUT_PAGE_BOUND_EN_CH3` reader - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] +pub type OUT_PAGE_BOUND_EN_CH3_R = crate::BitReader; +#[doc = "Field `OUT_PAGE_BOUND_EN_CH3` writer - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] +pub type OUT_PAGE_BOUND_EN_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ARB_WEIGHT_OPT_DIS_CH3` reader - Set this bit to 1 to disable arbiter optimum weight function."] +pub type OUT_ARB_WEIGHT_OPT_DIS_CH3_R = crate::BitReader; +#[doc = "Field `OUT_ARB_WEIGHT_OPT_DIS_CH3` writer - Set this bit to 1 to disable arbiter optimum weight function."] +pub type OUT_ARB_WEIGHT_OPT_DIS_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] + #[inline(always)] + pub fn out_auto_wrback_ch3(&self) -> OUT_AUTO_WRBACK_CH3_R { + OUT_AUTO_WRBACK_CH3_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] + #[inline(always)] + pub fn out_eof_mode_ch3(&self) -> OUT_EOF_MODE_CH3_R { + OUT_EOF_MODE_CH3_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn outdscr_burst_en_ch3(&self) -> OUTDSCR_BURST_EN_CH3_R { + OUTDSCR_BURST_EN_CH3_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + pub fn out_ecc_aes_en_ch3(&self) -> OUT_ECC_AES_EN_CH3_R { + OUT_ECC_AES_EN_CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn out_check_owner_ch3(&self) -> OUT_CHECK_OWNER_CH3_R { + OUT_CHECK_OWNER_CH3_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 6:8 - Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + pub fn out_mem_burst_length_ch3(&self) -> OUT_MEM_BURST_LENGTH_CH3_R { + OUT_MEM_BURST_LENGTH_CH3_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + pub fn out_page_bound_en_ch3(&self) -> OUT_PAGE_BOUND_EN_CH3_R { + OUT_PAGE_BOUND_EN_CH3_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + pub fn out_arb_weight_opt_dis_ch3(&self) -> OUT_ARB_WEIGHT_OPT_DIS_CH3_R { + OUT_ARB_WEIGHT_OPT_DIS_CH3_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF0_CH3") + .field( + "out_auto_wrback_ch3", + &format_args!("{}", self.out_auto_wrback_ch3().bit()), + ) + .field( + "out_eof_mode_ch3", + &format_args!("{}", self.out_eof_mode_ch3().bit()), + ) + .field( + "outdscr_burst_en_ch3", + &format_args!("{}", self.outdscr_burst_en_ch3().bit()), + ) + .field( + "out_ecc_aes_en_ch3", + &format_args!("{}", self.out_ecc_aes_en_ch3().bit()), + ) + .field( + "out_check_owner_ch3", + &format_args!("{}", self.out_check_owner_ch3().bit()), + ) + .field( + "out_mem_burst_length_ch3", + &format_args!("{}", self.out_mem_burst_length_ch3().bits()), + ) + .field( + "out_page_bound_en_ch3", + &format_args!("{}", self.out_page_bound_en_ch3().bit()), + ) + .field( + "out_arb_weight_opt_dis_ch3", + &format_args!("{}", self.out_arb_weight_opt_dis_ch3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] + #[inline(always)] + #[must_use] + pub fn out_auto_wrback_ch3(&mut self) -> OUT_AUTO_WRBACK_CH3_W { + OUT_AUTO_WRBACK_CH3_W::new(self, 0) + } + #[doc = "Bit 1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] + #[inline(always)] + #[must_use] + pub fn out_eof_mode_ch3(&mut self) -> OUT_EOF_MODE_CH3_W { + OUT_EOF_MODE_CH3_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn outdscr_burst_en_ch3(&mut self) -> OUTDSCR_BURST_EN_CH3_W { + OUTDSCR_BURST_EN_CH3_W::new(self, 2) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + #[must_use] + pub fn out_ecc_aes_en_ch3(&mut self) -> OUT_ECC_AES_EN_CH3_W { + OUT_ECC_AES_EN_CH3_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn out_check_owner_ch3(&mut self) -> OUT_CHECK_OWNER_CH3_W { + OUT_CHECK_OWNER_CH3_W::new(self, 4) + } + #[doc = "Bits 6:8 - Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + #[must_use] + pub fn out_mem_burst_length_ch3(&mut self) -> OUT_MEM_BURST_LENGTH_CH3_W { + OUT_MEM_BURST_LENGTH_CH3_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + #[must_use] + pub fn out_page_bound_en_ch3(&mut self) -> OUT_PAGE_BOUND_EN_CH3_W { + OUT_PAGE_BOUND_EN_CH3_W::new(self, 12) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + #[must_use] + pub fn out_arb_weight_opt_dis_ch3( + &mut self, + ) -> OUT_ARB_WEIGHT_OPT_DIS_CH3_W { + OUT_ARB_WEIGHT_OPT_DIS_CH3_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH3 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF0_CH3_SPEC; +impl crate::RegisterSpec for OUT_CONF0_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf0_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_CONF0_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf0_ch3::W`](W) writer structure"] +impl crate::Writable for OUT_CONF0_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF0_CH3 to value 0x02"] +impl crate::Resettable for OUT_CONF0_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/h264_dma/out_conf0_ch4.rs b/esp32p4/src/h264_dma/out_conf0_ch4.rs new file mode 100644 index 0000000000..e968d8997c --- /dev/null +++ b/esp32p4/src/h264_dma/out_conf0_ch4.rs @@ -0,0 +1,201 @@ +#[doc = "Register `OUT_CONF0_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_CONF0_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_AUTO_WRBACK_CH4` reader - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] +pub type OUT_AUTO_WRBACK_CH4_R = crate::BitReader; +#[doc = "Field `OUT_AUTO_WRBACK_CH4` writer - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] +pub type OUT_AUTO_WRBACK_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_MODE_CH4` reader - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_CH4_R = crate::BitReader; +#[doc = "Field `OUT_EOF_MODE_CH4` writer - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] +pub type OUT_EOF_MODE_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTDSCR_BURST_EN_CH4` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH4_R = crate::BitReader; +#[doc = "Field `OUTDSCR_BURST_EN_CH4` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] +pub type OUTDSCR_BURST_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ECC_AES_EN_CH4` reader - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type OUT_ECC_AES_EN_CH4_R = crate::BitReader; +#[doc = "Field `OUT_ECC_AES_EN_CH4` writer - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] +pub type OUT_ECC_AES_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_CHECK_OWNER_CH4` reader - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH4_R = crate::BitReader; +#[doc = "Field `OUT_CHECK_OWNER_CH4` writer - Set this bit to enable checking the owner attribute of the link descriptor."] +pub type OUT_CHECK_OWNER_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_MEM_BURST_LENGTH_CH4` reader - Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type OUT_MEM_BURST_LENGTH_CH4_R = crate::FieldReader; +#[doc = "Field `OUT_MEM_BURST_LENGTH_CH4` writer - Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] +pub type OUT_MEM_BURST_LENGTH_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OUT_PAGE_BOUND_EN_CH4` reader - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] +pub type OUT_PAGE_BOUND_EN_CH4_R = crate::BitReader; +#[doc = "Field `OUT_PAGE_BOUND_EN_CH4` writer - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] +pub type OUT_PAGE_BOUND_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ARB_WEIGHT_OPT_DIS_CH4` reader - Set this bit to 1 to disable arbiter optimum weight function."] +pub type OUT_ARB_WEIGHT_OPT_DIS_CH4_R = crate::BitReader; +#[doc = "Field `OUT_ARB_WEIGHT_OPT_DIS_CH4` writer - Set this bit to 1 to disable arbiter optimum weight function."] +pub type OUT_ARB_WEIGHT_OPT_DIS_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] + #[inline(always)] + pub fn out_auto_wrback_ch4(&self) -> OUT_AUTO_WRBACK_CH4_R { + OUT_AUTO_WRBACK_CH4_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] + #[inline(always)] + pub fn out_eof_mode_ch4(&self) -> OUT_EOF_MODE_CH4_R { + OUT_EOF_MODE_CH4_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + pub fn outdscr_burst_en_ch4(&self) -> OUTDSCR_BURST_EN_CH4_R { + OUTDSCR_BURST_EN_CH4_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + pub fn out_ecc_aes_en_ch4(&self) -> OUT_ECC_AES_EN_CH4_R { + OUT_ECC_AES_EN_CH4_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + pub fn out_check_owner_ch4(&self) -> OUT_CHECK_OWNER_CH4_R { + OUT_CHECK_OWNER_CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 6:8 - Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + pub fn out_mem_burst_length_ch4(&self) -> OUT_MEM_BURST_LENGTH_CH4_R { + OUT_MEM_BURST_LENGTH_CH4_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + pub fn out_page_bound_en_ch4(&self) -> OUT_PAGE_BOUND_EN_CH4_R { + OUT_PAGE_BOUND_EN_CH4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + pub fn out_arb_weight_opt_dis_ch4(&self) -> OUT_ARB_WEIGHT_OPT_DIS_CH4_R { + OUT_ARB_WEIGHT_OPT_DIS_CH4_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_CONF0_CH4") + .field( + "out_auto_wrback_ch4", + &format_args!("{}", self.out_auto_wrback_ch4().bit()), + ) + .field( + "out_eof_mode_ch4", + &format_args!("{}", self.out_eof_mode_ch4().bit()), + ) + .field( + "outdscr_burst_en_ch4", + &format_args!("{}", self.outdscr_burst_en_ch4().bit()), + ) + .field( + "out_ecc_aes_en_ch4", + &format_args!("{}", self.out_ecc_aes_en_ch4().bit()), + ) + .field( + "out_check_owner_ch4", + &format_args!("{}", self.out_check_owner_ch4().bit()), + ) + .field( + "out_mem_burst_length_ch4", + &format_args!("{}", self.out_mem_burst_length_ch4().bits()), + ) + .field( + "out_page_bound_en_ch4", + &format_args!("{}", self.out_page_bound_en_ch4().bit()), + ) + .field( + "out_arb_weight_opt_dis_ch4", + &format_args!("{}", self.out_arb_weight_opt_dis_ch4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."] + #[inline(always)] + #[must_use] + pub fn out_auto_wrback_ch4(&mut self) -> OUT_AUTO_WRBACK_CH4_W { + OUT_AUTO_WRBACK_CH4_W::new(self, 0) + } + #[doc = "Bit 1 - EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA"] + #[inline(always)] + #[must_use] + pub fn out_eof_mode_ch4(&mut self) -> OUT_EOF_MODE_CH4_W { + OUT_EOF_MODE_CH4_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."] + #[inline(always)] + #[must_use] + pub fn outdscr_burst_en_ch4(&mut self) -> OUTDSCR_BURST_EN_CH4_W { + OUTDSCR_BURST_EN_CH4_W::new(self, 2) + } + #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."] + #[inline(always)] + #[must_use] + pub fn out_ecc_aes_en_ch4(&mut self) -> OUT_ECC_AES_EN_CH4_W { + OUT_ECC_AES_EN_CH4_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable checking the owner attribute of the link descriptor."] + #[inline(always)] + #[must_use] + pub fn out_check_owner_ch4(&mut self) -> OUT_CHECK_OWNER_CH4_W { + OUT_CHECK_OWNER_CH4_W::new(self, 4) + } + #[doc = "Bits 6:8 - Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes"] + #[inline(always)] + #[must_use] + pub fn out_mem_burst_length_ch4(&mut self) -> OUT_MEM_BURST_LENGTH_CH4_W { + OUT_MEM_BURST_LENGTH_CH4_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length"] + #[inline(always)] + #[must_use] + pub fn out_page_bound_en_ch4(&mut self) -> OUT_PAGE_BOUND_EN_CH4_W { + OUT_PAGE_BOUND_EN_CH4_W::new(self, 12) + } + #[doc = "Bit 26 - Set this bit to 1 to disable arbiter optimum weight function."] + #[inline(always)] + #[must_use] + pub fn out_arb_weight_opt_dis_ch4( + &mut self, + ) -> OUT_ARB_WEIGHT_OPT_DIS_CH4_W { + OUT_ARB_WEIGHT_OPT_DIS_CH4_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH4 config0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_conf0_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_conf0_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_CONF0_CH4_SPEC; +impl crate::RegisterSpec for OUT_CONF0_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_conf0_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_CONF0_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_conf0_ch4::W`](W) writer structure"] +impl crate::Writable for OUT_CONF0_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_CONF0_CH4 to value 0x02"] +impl crate::Resettable for OUT_CONF0_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/h264_dma/out_dscr_bf0_ch0.rs b/esp32p4/src/h264_dma/out_dscr_bf0_ch0.rs new file mode 100644 index 0000000000..2f85884e71 --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_bf0_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF0_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF0_CH0` reader - The address of the last outlink descriptor's next address y-1."] +pub type OUTLINK_DSCR_BF0_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last outlink descriptor's next address y-1."] + #[inline(always)] + pub fn outlink_dscr_bf0_ch0(&self) -> OUTLINK_DSCR_BF0_CH0_R { + OUTLINK_DSCR_BF0_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF0_CH0") + .field( + "outlink_dscr_bf0_ch0", + &format_args!("{}", self.outlink_dscr_bf0_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH0 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF0_CH0_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF0_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf0_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF0_CH0_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF0_CH0 to value 0"] +impl crate::Resettable for OUT_DSCR_BF0_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_bf0_ch1.rs b/esp32p4/src/h264_dma/out_dscr_bf0_ch1.rs new file mode 100644 index 0000000000..d7da8cdd68 --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_bf0_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF0_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF0_CH1` reader - The address of the last outlink descriptor's next address y-1."] +pub type OUTLINK_DSCR_BF0_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last outlink descriptor's next address y-1."] + #[inline(always)] + pub fn outlink_dscr_bf0_ch1(&self) -> OUTLINK_DSCR_BF0_CH1_R { + OUTLINK_DSCR_BF0_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF0_CH1") + .field( + "outlink_dscr_bf0_ch1", + &format_args!("{}", self.outlink_dscr_bf0_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH1 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF0_CH1_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF0_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf0_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF0_CH1_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF0_CH1 to value 0"] +impl crate::Resettable for OUT_DSCR_BF0_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_bf0_ch2.rs b/esp32p4/src/h264_dma/out_dscr_bf0_ch2.rs new file mode 100644 index 0000000000..bb3b85d921 --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_bf0_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF0_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF0_CH2` reader - The address of the last outlink descriptor's next address y-1."] +pub type OUTLINK_DSCR_BF0_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last outlink descriptor's next address y-1."] + #[inline(always)] + pub fn outlink_dscr_bf0_ch2(&self) -> OUTLINK_DSCR_BF0_CH2_R { + OUTLINK_DSCR_BF0_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF0_CH2") + .field( + "outlink_dscr_bf0_ch2", + &format_args!("{}", self.outlink_dscr_bf0_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH2 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF0_CH2_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF0_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf0_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF0_CH2_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF0_CH2 to value 0"] +impl crate::Resettable for OUT_DSCR_BF0_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_bf0_ch3.rs b/esp32p4/src/h264_dma/out_dscr_bf0_ch3.rs new file mode 100644 index 0000000000..61c499e56d --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_bf0_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF0_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF0_CH3` reader - The address of the last outlink descriptor's next address y-1."] +pub type OUTLINK_DSCR_BF0_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last outlink descriptor's next address y-1."] + #[inline(always)] + pub fn outlink_dscr_bf0_ch3(&self) -> OUTLINK_DSCR_BF0_CH3_R { + OUTLINK_DSCR_BF0_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF0_CH3") + .field( + "outlink_dscr_bf0_ch3", + &format_args!("{}", self.outlink_dscr_bf0_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH3 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF0_CH3_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF0_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf0_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF0_CH3_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF0_CH3 to value 0"] +impl crate::Resettable for OUT_DSCR_BF0_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_bf0_ch4.rs b/esp32p4/src/h264_dma/out_dscr_bf0_ch4.rs new file mode 100644 index 0000000000..3485a576b0 --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_bf0_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF0_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF0_CH4` reader - The address of the last outlink descriptor's next address y-1."] +pub type OUTLINK_DSCR_BF0_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the last outlink descriptor's next address y-1."] + #[inline(always)] + pub fn outlink_dscr_bf0_ch4(&self) -> OUTLINK_DSCR_BF0_CH4_R { + OUTLINK_DSCR_BF0_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF0_CH4") + .field( + "outlink_dscr_bf0_ch4", + &format_args!("{}", self.outlink_dscr_bf0_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH4 last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF0_CH4_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF0_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf0_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF0_CH4_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF0_CH4 to value 0"] +impl crate::Resettable for OUT_DSCR_BF0_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_bf1_ch0.rs b/esp32p4/src/h264_dma/out_dscr_bf1_ch0.rs new file mode 100644 index 0000000000..6b7ce7bf3d --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_bf1_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF1_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF1_CH0` reader - The address of the second-to-last outlink descriptor's next address y-2."] +pub type OUTLINK_DSCR_BF1_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last outlink descriptor's next address y-2."] + #[inline(always)] + pub fn outlink_dscr_bf1_ch0(&self) -> OUTLINK_DSCR_BF1_CH0_R { + OUTLINK_DSCR_BF1_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF1_CH0") + .field( + "outlink_dscr_bf1_ch0", + &format_args!("{}", self.outlink_dscr_bf1_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH0 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF1_CH0_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF1_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf1_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF1_CH0_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF1_CH0 to value 0"] +impl crate::Resettable for OUT_DSCR_BF1_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_bf1_ch1.rs b/esp32p4/src/h264_dma/out_dscr_bf1_ch1.rs new file mode 100644 index 0000000000..18895fd2c6 --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_bf1_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF1_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF1_CH1` reader - The address of the second-to-last outlink descriptor's next address y-2."] +pub type OUTLINK_DSCR_BF1_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last outlink descriptor's next address y-2."] + #[inline(always)] + pub fn outlink_dscr_bf1_ch1(&self) -> OUTLINK_DSCR_BF1_CH1_R { + OUTLINK_DSCR_BF1_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF1_CH1") + .field( + "outlink_dscr_bf1_ch1", + &format_args!("{}", self.outlink_dscr_bf1_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH1 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF1_CH1_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF1_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf1_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF1_CH1_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF1_CH1 to value 0"] +impl crate::Resettable for OUT_DSCR_BF1_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_bf1_ch2.rs b/esp32p4/src/h264_dma/out_dscr_bf1_ch2.rs new file mode 100644 index 0000000000..be66aeea85 --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_bf1_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF1_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF1_CH2` reader - The address of the second-to-last outlink descriptor's next address y-2."] +pub type OUTLINK_DSCR_BF1_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last outlink descriptor's next address y-2."] + #[inline(always)] + pub fn outlink_dscr_bf1_ch2(&self) -> OUTLINK_DSCR_BF1_CH2_R { + OUTLINK_DSCR_BF1_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF1_CH2") + .field( + "outlink_dscr_bf1_ch2", + &format_args!("{}", self.outlink_dscr_bf1_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH2 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF1_CH2_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF1_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf1_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF1_CH2_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF1_CH2 to value 0"] +impl crate::Resettable for OUT_DSCR_BF1_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_bf1_ch3.rs b/esp32p4/src/h264_dma/out_dscr_bf1_ch3.rs new file mode 100644 index 0000000000..4efede1623 --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_bf1_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF1_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF1_CH3` reader - The address of the second-to-last outlink descriptor's next address y-2."] +pub type OUTLINK_DSCR_BF1_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last outlink descriptor's next address y-2."] + #[inline(always)] + pub fn outlink_dscr_bf1_ch3(&self) -> OUTLINK_DSCR_BF1_CH3_R { + OUTLINK_DSCR_BF1_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF1_CH3") + .field( + "outlink_dscr_bf1_ch3", + &format_args!("{}", self.outlink_dscr_bf1_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH3 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF1_CH3_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF1_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf1_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF1_CH3_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF1_CH3 to value 0"] +impl crate::Resettable for OUT_DSCR_BF1_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_bf1_ch4.rs b/esp32p4/src/h264_dma/out_dscr_bf1_ch4.rs new file mode 100644 index 0000000000..c5f124ec3e --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_bf1_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_BF1_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_BF1_CH4` reader - The address of the second-to-last outlink descriptor's next address y-2."] +pub type OUTLINK_DSCR_BF1_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the second-to-last outlink descriptor's next address y-2."] + #[inline(always)] + pub fn outlink_dscr_bf1_ch4(&self) -> OUTLINK_DSCR_BF1_CH4_R { + OUTLINK_DSCR_BF1_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_BF1_CH4") + .field( + "outlink_dscr_bf1_ch4", + &format_args!("{}", self.outlink_dscr_bf1_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH4 second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_BF1_CH4_SPEC; +impl crate::RegisterSpec for OUT_DSCR_BF1_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_bf1_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_BF1_CH4_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_BF1_CH4 to value 0"] +impl crate::Resettable for OUT_DSCR_BF1_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_ch0.rs b/esp32p4/src/h264_dma/out_dscr_ch0.rs new file mode 100644 index 0000000000..349976e407 --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_CH0` reader - The address of the next outlink descriptor address y."] +pub type OUTLINK_DSCR_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the next outlink descriptor address y."] + #[inline(always)] + pub fn outlink_dscr_ch0(&self) -> OUTLINK_DSCR_CH0_R { + OUTLINK_DSCR_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_CH0") + .field( + "outlink_dscr_ch0", + &format_args!("{}", self.outlink_dscr_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH0 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_CH0_SPEC; +impl crate::RegisterSpec for OUT_DSCR_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_CH0_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_CH0 to value 0"] +impl crate::Resettable for OUT_DSCR_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_ch1.rs b/esp32p4/src/h264_dma/out_dscr_ch1.rs new file mode 100644 index 0000000000..44b251a0dd --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_CH1` reader - The address of the next outlink descriptor address y."] +pub type OUTLINK_DSCR_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the next outlink descriptor address y."] + #[inline(always)] + pub fn outlink_dscr_ch1(&self) -> OUTLINK_DSCR_CH1_R { + OUTLINK_DSCR_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_CH1") + .field( + "outlink_dscr_ch1", + &format_args!("{}", self.outlink_dscr_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH1 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_CH1_SPEC; +impl crate::RegisterSpec for OUT_DSCR_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_CH1_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_CH1 to value 0"] +impl crate::Resettable for OUT_DSCR_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_ch2.rs b/esp32p4/src/h264_dma/out_dscr_ch2.rs new file mode 100644 index 0000000000..dd9d26f530 --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_CH2` reader - The address of the next outlink descriptor address y."] +pub type OUTLINK_DSCR_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the next outlink descriptor address y."] + #[inline(always)] + pub fn outlink_dscr_ch2(&self) -> OUTLINK_DSCR_CH2_R { + OUTLINK_DSCR_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_CH2") + .field( + "outlink_dscr_ch2", + &format_args!("{}", self.outlink_dscr_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH2 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_CH2_SPEC; +impl crate::RegisterSpec for OUT_DSCR_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_CH2_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_CH2 to value 0"] +impl crate::Resettable for OUT_DSCR_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_ch3.rs b/esp32p4/src/h264_dma/out_dscr_ch3.rs new file mode 100644 index 0000000000..3a0c0cabca --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_CH3` reader - The address of the next outlink descriptor address y."] +pub type OUTLINK_DSCR_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the next outlink descriptor address y."] + #[inline(always)] + pub fn outlink_dscr_ch3(&self) -> OUTLINK_DSCR_CH3_R { + OUTLINK_DSCR_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_CH3") + .field( + "outlink_dscr_ch3", + &format_args!("{}", self.outlink_dscr_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH3 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_CH3_SPEC; +impl crate::RegisterSpec for OUT_DSCR_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_CH3_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_CH3 to value 0"] +impl crate::Resettable for OUT_DSCR_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_dscr_ch4.rs b/esp32p4/src/h264_dma/out_dscr_ch4.rs new file mode 100644 index 0000000000..73b64644e6 --- /dev/null +++ b/esp32p4/src/h264_dma/out_dscr_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_DSCR_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_CH4` reader - The address of the next outlink descriptor address y."] +pub type OUTLINK_DSCR_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The address of the next outlink descriptor address y."] + #[inline(always)] + pub fn outlink_dscr_ch4(&self) -> OUTLINK_DSCR_CH4_R { + OUTLINK_DSCR_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_DSCR_CH4") + .field( + "outlink_dscr_ch4", + &format_args!("{}", self.outlink_dscr_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH4 next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_DSCR_CH4_SPEC; +impl crate::RegisterSpec for OUT_DSCR_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_dscr_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_DSCR_CH4_SPEC {} +#[doc = "`reset()` method sets OUT_DSCR_CH4 to value 0"] +impl crate::Resettable for OUT_DSCR_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_eof_des_addr_ch0.rs b/esp32p4/src/h264_dma/out_eof_des_addr_ch0.rs new file mode 100644 index 0000000000..2022e52ef4 --- /dev/null +++ b/esp32p4/src/h264_dma/out_eof_des_addr_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_EOF_DES_ADDR_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_DES_ADDR_CH0` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn out_eof_des_addr_ch0(&self) -> OUT_EOF_DES_ADDR_CH0_R { + OUT_EOF_DES_ADDR_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_DES_ADDR_CH0") + .field( + "out_eof_des_addr_ch0", + &format_args!("{}", self.out_eof_des_addr_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH0 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_DES_ADDR_CH0_SPEC; +impl crate::RegisterSpec for OUT_EOF_DES_ADDR_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_des_addr_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_DES_ADDR_CH0_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_DES_ADDR_CH0 to value 0"] +impl crate::Resettable for OUT_EOF_DES_ADDR_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_eof_des_addr_ch1.rs b/esp32p4/src/h264_dma/out_eof_des_addr_ch1.rs new file mode 100644 index 0000000000..bfca8395a5 --- /dev/null +++ b/esp32p4/src/h264_dma/out_eof_des_addr_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_EOF_DES_ADDR_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_DES_ADDR_CH1` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn out_eof_des_addr_ch1(&self) -> OUT_EOF_DES_ADDR_CH1_R { + OUT_EOF_DES_ADDR_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_DES_ADDR_CH1") + .field( + "out_eof_des_addr_ch1", + &format_args!("{}", self.out_eof_des_addr_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH1 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_DES_ADDR_CH1_SPEC; +impl crate::RegisterSpec for OUT_EOF_DES_ADDR_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_des_addr_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_DES_ADDR_CH1_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_DES_ADDR_CH1 to value 0"] +impl crate::Resettable for OUT_EOF_DES_ADDR_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_eof_des_addr_ch2.rs b/esp32p4/src/h264_dma/out_eof_des_addr_ch2.rs new file mode 100644 index 0000000000..720a44a5a4 --- /dev/null +++ b/esp32p4/src/h264_dma/out_eof_des_addr_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_EOF_DES_ADDR_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_DES_ADDR_CH2` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn out_eof_des_addr_ch2(&self) -> OUT_EOF_DES_ADDR_CH2_R { + OUT_EOF_DES_ADDR_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_DES_ADDR_CH2") + .field( + "out_eof_des_addr_ch2", + &format_args!("{}", self.out_eof_des_addr_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH2 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_DES_ADDR_CH2_SPEC; +impl crate::RegisterSpec for OUT_EOF_DES_ADDR_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_des_addr_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_DES_ADDR_CH2_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_DES_ADDR_CH2 to value 0"] +impl crate::Resettable for OUT_EOF_DES_ADDR_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_eof_des_addr_ch3.rs b/esp32p4/src/h264_dma/out_eof_des_addr_ch3.rs new file mode 100644 index 0000000000..a42ce8d8fb --- /dev/null +++ b/esp32p4/src/h264_dma/out_eof_des_addr_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_EOF_DES_ADDR_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_DES_ADDR_CH3` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn out_eof_des_addr_ch3(&self) -> OUT_EOF_DES_ADDR_CH3_R { + OUT_EOF_DES_ADDR_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_DES_ADDR_CH3") + .field( + "out_eof_des_addr_ch3", + &format_args!("{}", self.out_eof_des_addr_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH3 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_DES_ADDR_CH3_SPEC; +impl crate::RegisterSpec for OUT_EOF_DES_ADDR_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_des_addr_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_DES_ADDR_CH3_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_DES_ADDR_CH3 to value 0"] +impl crate::Resettable for OUT_EOF_DES_ADDR_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_eof_des_addr_ch4.rs b/esp32p4/src/h264_dma/out_eof_des_addr_ch4.rs new file mode 100644 index 0000000000..170a1c1865 --- /dev/null +++ b/esp32p4/src/h264_dma/out_eof_des_addr_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_EOF_DES_ADDR_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_EOF_DES_ADDR_CH4` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] +pub type OUT_EOF_DES_ADDR_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."] + #[inline(always)] + pub fn out_eof_des_addr_ch4(&self) -> OUT_EOF_DES_ADDR_CH4_R { + OUT_EOF_DES_ADDR_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EOF_DES_ADDR_CH4") + .field( + "out_eof_des_addr_ch4", + &format_args!("{}", self.out_eof_des_addr_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH4 eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EOF_DES_ADDR_CH4_SPEC; +impl crate::RegisterSpec for OUT_EOF_DES_ADDR_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_eof_des_addr_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_EOF_DES_ADDR_CH4_SPEC {} +#[doc = "`reset()` method sets OUT_EOF_DES_ADDR_CH4 to value 0"] +impl crate::Resettable for OUT_EOF_DES_ADDR_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_etm_conf_ch0.rs b/esp32p4/src/h264_dma/out_etm_conf_ch0.rs new file mode 100644 index 0000000000..5f25cfa0ce --- /dev/null +++ b/esp32p4/src/h264_dma/out_etm_conf_ch0.rs @@ -0,0 +1,104 @@ +#[doc = "Register `OUT_ETM_CONF_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_ETM_CONF_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_ETM_EN_CH0` reader - Set this bit to 1 to enable ETM task function"] +pub type OUT_ETM_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUT_ETM_EN_CH0` writer - Set this bit to 1 to enable ETM task function"] +pub type OUT_ETM_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ETM_LOOP_EN_CH0` reader - when this bit is 1, dscr can be processed after receiving a task"] +pub type OUT_ETM_LOOP_EN_CH0_R = crate::BitReader; +#[doc = "Field `OUT_ETM_LOOP_EN_CH0` writer - when this bit is 1, dscr can be processed after receiving a task"] +pub type OUT_ETM_LOOP_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_MAK_CH0` reader - ETM dscr_ready maximum cache numbers"] +pub type OUT_DSCR_TASK_MAK_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_TASK_MAK_CH0` writer - ETM dscr_ready maximum cache numbers"] +pub type OUT_DSCR_TASK_MAK_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + pub fn out_etm_en_ch0(&self) -> OUT_ETM_EN_CH0_R { + OUT_ETM_EN_CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + pub fn out_etm_loop_en_ch0(&self) -> OUT_ETM_LOOP_EN_CH0_R { + OUT_ETM_LOOP_EN_CH0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + pub fn out_dscr_task_mak_ch0(&self) -> OUT_DSCR_TASK_MAK_CH0_R { + OUT_DSCR_TASK_MAK_CH0_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ETM_CONF_CH0") + .field( + "out_etm_en_ch0", + &format_args!("{}", self.out_etm_en_ch0().bit()), + ) + .field( + "out_etm_loop_en_ch0", + &format_args!("{}", self.out_etm_loop_en_ch0().bit()), + ) + .field( + "out_dscr_task_mak_ch0", + &format_args!("{}", self.out_dscr_task_mak_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + #[must_use] + pub fn out_etm_en_ch0(&mut self) -> OUT_ETM_EN_CH0_W { + OUT_ETM_EN_CH0_W::new(self, 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + #[must_use] + pub fn out_etm_loop_en_ch0(&mut self) -> OUT_ETM_LOOP_EN_CH0_W { + OUT_ETM_LOOP_EN_CH0_W::new(self, 1) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_mak_ch0(&mut self) -> OUT_DSCR_TASK_MAK_CH0_W { + OUT_DSCR_TASK_MAK_CH0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH0 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_etm_conf_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_etm_conf_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ETM_CONF_CH0_SPEC; +impl crate::RegisterSpec for OUT_ETM_CONF_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_etm_conf_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_ETM_CONF_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_etm_conf_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_ETM_CONF_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_ETM_CONF_CH0 to value 0x04"] +impl crate::Resettable for OUT_ETM_CONF_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/h264_dma/out_etm_conf_ch1.rs b/esp32p4/src/h264_dma/out_etm_conf_ch1.rs new file mode 100644 index 0000000000..42f5e03720 --- /dev/null +++ b/esp32p4/src/h264_dma/out_etm_conf_ch1.rs @@ -0,0 +1,104 @@ +#[doc = "Register `OUT_ETM_CONF_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_ETM_CONF_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_ETM_EN_CH1` reader - Set this bit to 1 to enable ETM task function"] +pub type OUT_ETM_EN_CH1_R = crate::BitReader; +#[doc = "Field `OUT_ETM_EN_CH1` writer - Set this bit to 1 to enable ETM task function"] +pub type OUT_ETM_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ETM_LOOP_EN_CH1` reader - when this bit is 1, dscr can be processed after receiving a task"] +pub type OUT_ETM_LOOP_EN_CH1_R = crate::BitReader; +#[doc = "Field `OUT_ETM_LOOP_EN_CH1` writer - when this bit is 1, dscr can be processed after receiving a task"] +pub type OUT_ETM_LOOP_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_MAK_CH1` reader - ETM dscr_ready maximum cache numbers"] +pub type OUT_DSCR_TASK_MAK_CH1_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_TASK_MAK_CH1` writer - ETM dscr_ready maximum cache numbers"] +pub type OUT_DSCR_TASK_MAK_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + pub fn out_etm_en_ch1(&self) -> OUT_ETM_EN_CH1_R { + OUT_ETM_EN_CH1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + pub fn out_etm_loop_en_ch1(&self) -> OUT_ETM_LOOP_EN_CH1_R { + OUT_ETM_LOOP_EN_CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + pub fn out_dscr_task_mak_ch1(&self) -> OUT_DSCR_TASK_MAK_CH1_R { + OUT_DSCR_TASK_MAK_CH1_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ETM_CONF_CH1") + .field( + "out_etm_en_ch1", + &format_args!("{}", self.out_etm_en_ch1().bit()), + ) + .field( + "out_etm_loop_en_ch1", + &format_args!("{}", self.out_etm_loop_en_ch1().bit()), + ) + .field( + "out_dscr_task_mak_ch1", + &format_args!("{}", self.out_dscr_task_mak_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + #[must_use] + pub fn out_etm_en_ch1(&mut self) -> OUT_ETM_EN_CH1_W { + OUT_ETM_EN_CH1_W::new(self, 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + #[must_use] + pub fn out_etm_loop_en_ch1(&mut self) -> OUT_ETM_LOOP_EN_CH1_W { + OUT_ETM_LOOP_EN_CH1_W::new(self, 1) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_mak_ch1(&mut self) -> OUT_DSCR_TASK_MAK_CH1_W { + OUT_DSCR_TASK_MAK_CH1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH1 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_etm_conf_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_etm_conf_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ETM_CONF_CH1_SPEC; +impl crate::RegisterSpec for OUT_ETM_CONF_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_etm_conf_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_ETM_CONF_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_etm_conf_ch1::W`](W) writer structure"] +impl crate::Writable for OUT_ETM_CONF_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_ETM_CONF_CH1 to value 0x04"] +impl crate::Resettable for OUT_ETM_CONF_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/h264_dma/out_etm_conf_ch2.rs b/esp32p4/src/h264_dma/out_etm_conf_ch2.rs new file mode 100644 index 0000000000..1164702276 --- /dev/null +++ b/esp32p4/src/h264_dma/out_etm_conf_ch2.rs @@ -0,0 +1,104 @@ +#[doc = "Register `OUT_ETM_CONF_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_ETM_CONF_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_ETM_EN_CH2` reader - Set this bit to 1 to enable ETM task function"] +pub type OUT_ETM_EN_CH2_R = crate::BitReader; +#[doc = "Field `OUT_ETM_EN_CH2` writer - Set this bit to 1 to enable ETM task function"] +pub type OUT_ETM_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ETM_LOOP_EN_CH2` reader - when this bit is 1, dscr can be processed after receiving a task"] +pub type OUT_ETM_LOOP_EN_CH2_R = crate::BitReader; +#[doc = "Field `OUT_ETM_LOOP_EN_CH2` writer - when this bit is 1, dscr can be processed after receiving a task"] +pub type OUT_ETM_LOOP_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_MAK_CH2` reader - ETM dscr_ready maximum cache numbers"] +pub type OUT_DSCR_TASK_MAK_CH2_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_TASK_MAK_CH2` writer - ETM dscr_ready maximum cache numbers"] +pub type OUT_DSCR_TASK_MAK_CH2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + pub fn out_etm_en_ch2(&self) -> OUT_ETM_EN_CH2_R { + OUT_ETM_EN_CH2_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + pub fn out_etm_loop_en_ch2(&self) -> OUT_ETM_LOOP_EN_CH2_R { + OUT_ETM_LOOP_EN_CH2_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + pub fn out_dscr_task_mak_ch2(&self) -> OUT_DSCR_TASK_MAK_CH2_R { + OUT_DSCR_TASK_MAK_CH2_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ETM_CONF_CH2") + .field( + "out_etm_en_ch2", + &format_args!("{}", self.out_etm_en_ch2().bit()), + ) + .field( + "out_etm_loop_en_ch2", + &format_args!("{}", self.out_etm_loop_en_ch2().bit()), + ) + .field( + "out_dscr_task_mak_ch2", + &format_args!("{}", self.out_dscr_task_mak_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + #[must_use] + pub fn out_etm_en_ch2(&mut self) -> OUT_ETM_EN_CH2_W { + OUT_ETM_EN_CH2_W::new(self, 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + #[must_use] + pub fn out_etm_loop_en_ch2(&mut self) -> OUT_ETM_LOOP_EN_CH2_W { + OUT_ETM_LOOP_EN_CH2_W::new(self, 1) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_mak_ch2(&mut self) -> OUT_DSCR_TASK_MAK_CH2_W { + OUT_DSCR_TASK_MAK_CH2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH2 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_etm_conf_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_etm_conf_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ETM_CONF_CH2_SPEC; +impl crate::RegisterSpec for OUT_ETM_CONF_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_etm_conf_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_ETM_CONF_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_etm_conf_ch2::W`](W) writer structure"] +impl crate::Writable for OUT_ETM_CONF_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_ETM_CONF_CH2 to value 0x04"] +impl crate::Resettable for OUT_ETM_CONF_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/h264_dma/out_etm_conf_ch3.rs b/esp32p4/src/h264_dma/out_etm_conf_ch3.rs new file mode 100644 index 0000000000..373eec480d --- /dev/null +++ b/esp32p4/src/h264_dma/out_etm_conf_ch3.rs @@ -0,0 +1,104 @@ +#[doc = "Register `OUT_ETM_CONF_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_ETM_CONF_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_ETM_EN_CH3` reader - Set this bit to 1 to enable ETM task function"] +pub type OUT_ETM_EN_CH3_R = crate::BitReader; +#[doc = "Field `OUT_ETM_EN_CH3` writer - Set this bit to 1 to enable ETM task function"] +pub type OUT_ETM_EN_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ETM_LOOP_EN_CH3` reader - when this bit is 1, dscr can be processed after receiving a task"] +pub type OUT_ETM_LOOP_EN_CH3_R = crate::BitReader; +#[doc = "Field `OUT_ETM_LOOP_EN_CH3` writer - when this bit is 1, dscr can be processed after receiving a task"] +pub type OUT_ETM_LOOP_EN_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_MAK_CH3` reader - ETM dscr_ready maximum cache numbers"] +pub type OUT_DSCR_TASK_MAK_CH3_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_TASK_MAK_CH3` writer - ETM dscr_ready maximum cache numbers"] +pub type OUT_DSCR_TASK_MAK_CH3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + pub fn out_etm_en_ch3(&self) -> OUT_ETM_EN_CH3_R { + OUT_ETM_EN_CH3_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + pub fn out_etm_loop_en_ch3(&self) -> OUT_ETM_LOOP_EN_CH3_R { + OUT_ETM_LOOP_EN_CH3_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + pub fn out_dscr_task_mak_ch3(&self) -> OUT_DSCR_TASK_MAK_CH3_R { + OUT_DSCR_TASK_MAK_CH3_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ETM_CONF_CH3") + .field( + "out_etm_en_ch3", + &format_args!("{}", self.out_etm_en_ch3().bit()), + ) + .field( + "out_etm_loop_en_ch3", + &format_args!("{}", self.out_etm_loop_en_ch3().bit()), + ) + .field( + "out_dscr_task_mak_ch3", + &format_args!("{}", self.out_dscr_task_mak_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + #[must_use] + pub fn out_etm_en_ch3(&mut self) -> OUT_ETM_EN_CH3_W { + OUT_ETM_EN_CH3_W::new(self, 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + #[must_use] + pub fn out_etm_loop_en_ch3(&mut self) -> OUT_ETM_LOOP_EN_CH3_W { + OUT_ETM_LOOP_EN_CH3_W::new(self, 1) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_mak_ch3(&mut self) -> OUT_DSCR_TASK_MAK_CH3_W { + OUT_DSCR_TASK_MAK_CH3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH3 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_etm_conf_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_etm_conf_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ETM_CONF_CH3_SPEC; +impl crate::RegisterSpec for OUT_ETM_CONF_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_etm_conf_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_ETM_CONF_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_etm_conf_ch3::W`](W) writer structure"] +impl crate::Writable for OUT_ETM_CONF_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_ETM_CONF_CH3 to value 0x04"] +impl crate::Resettable for OUT_ETM_CONF_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/h264_dma/out_etm_conf_ch4.rs b/esp32p4/src/h264_dma/out_etm_conf_ch4.rs new file mode 100644 index 0000000000..662358d603 --- /dev/null +++ b/esp32p4/src/h264_dma/out_etm_conf_ch4.rs @@ -0,0 +1,104 @@ +#[doc = "Register `OUT_ETM_CONF_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_ETM_CONF_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_ETM_EN_CH4` reader - Set this bit to 1 to enable ETM task function"] +pub type OUT_ETM_EN_CH4_R = crate::BitReader; +#[doc = "Field `OUT_ETM_EN_CH4` writer - Set this bit to 1 to enable ETM task function"] +pub type OUT_ETM_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_ETM_LOOP_EN_CH4` reader - when this bit is 1, dscr can be processed after receiving a task"] +pub type OUT_ETM_LOOP_EN_CH4_R = crate::BitReader; +#[doc = "Field `OUT_ETM_LOOP_EN_CH4` writer - when this bit is 1, dscr can be processed after receiving a task"] +pub type OUT_ETM_LOOP_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_MAK_CH4` reader - ETM dscr_ready maximum cache numbers"] +pub type OUT_DSCR_TASK_MAK_CH4_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_TASK_MAK_CH4` writer - ETM dscr_ready maximum cache numbers"] +pub type OUT_DSCR_TASK_MAK_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + pub fn out_etm_en_ch4(&self) -> OUT_ETM_EN_CH4_R { + OUT_ETM_EN_CH4_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + pub fn out_etm_loop_en_ch4(&self) -> OUT_ETM_LOOP_EN_CH4_R { + OUT_ETM_LOOP_EN_CH4_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + pub fn out_dscr_task_mak_ch4(&self) -> OUT_DSCR_TASK_MAK_CH4_R { + OUT_DSCR_TASK_MAK_CH4_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_ETM_CONF_CH4") + .field( + "out_etm_en_ch4", + &format_args!("{}", self.out_etm_en_ch4().bit()), + ) + .field( + "out_etm_loop_en_ch4", + &format_args!("{}", self.out_etm_loop_en_ch4().bit()), + ) + .field( + "out_dscr_task_mak_ch4", + &format_args!("{}", self.out_dscr_task_mak_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"] + #[inline(always)] + #[must_use] + pub fn out_etm_en_ch4(&mut self) -> OUT_ETM_EN_CH4_W { + OUT_ETM_EN_CH4_W::new(self, 0) + } + #[doc = "Bit 1 - when this bit is 1, dscr can be processed after receiving a task"] + #[inline(always)] + #[must_use] + pub fn out_etm_loop_en_ch4(&mut self) -> OUT_ETM_LOOP_EN_CH4_W { + OUT_ETM_LOOP_EN_CH4_W::new(self, 1) + } + #[doc = "Bits 2:3 - ETM dscr_ready maximum cache numbers"] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_mak_ch4(&mut self) -> OUT_DSCR_TASK_MAK_CH4_W { + OUT_DSCR_TASK_MAK_CH4_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH4 ETM config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_etm_conf_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_etm_conf_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_ETM_CONF_CH4_SPEC; +impl crate::RegisterSpec for OUT_ETM_CONF_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_etm_conf_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_ETM_CONF_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_etm_conf_ch4::W`](W) writer structure"] +impl crate::Writable for OUT_ETM_CONF_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_ETM_CONF_CH4 to value 0x04"] +impl crate::Resettable for OUT_ETM_CONF_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/h264_dma/out_fifo_bcnt_ch0.rs b/esp32p4/src/h264_dma/out_fifo_bcnt_ch0.rs new file mode 100644 index 0000000000..6127ddbefd --- /dev/null +++ b/esp32p4/src/h264_dma/out_fifo_bcnt_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_FIFO_BCNT_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_OUTFIFO_BCNT_CH0` reader - only for debug"] +pub type OUT_CMDFIFO_OUTFIFO_BCNT_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_outfifo_bcnt_ch0(&self) -> OUT_CMDFIFO_OUTFIFO_BCNT_CH0_R { + OUT_CMDFIFO_OUTFIFO_BCNT_CH0_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_FIFO_BCNT_CH0") + .field( + "out_cmdfifo_outfifo_bcnt_ch0", + &format_args!("{}", self.out_cmdfifo_outfifo_bcnt_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH0 fifo byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_fifo_bcnt_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_FIFO_BCNT_CH0_SPEC; +impl crate::RegisterSpec for OUT_FIFO_BCNT_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_fifo_bcnt_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_FIFO_BCNT_CH0_SPEC {} +#[doc = "`reset()` method sets OUT_FIFO_BCNT_CH0 to value 0"] +impl crate::Resettable for OUT_FIFO_BCNT_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_fifo_bcnt_ch1.rs b/esp32p4/src/h264_dma/out_fifo_bcnt_ch1.rs new file mode 100644 index 0000000000..127c08964b --- /dev/null +++ b/esp32p4/src/h264_dma/out_fifo_bcnt_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_FIFO_BCNT_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_OUTFIFO_BCNT_CH1` reader - only for debug"] +pub type OUT_CMDFIFO_OUTFIFO_BCNT_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_outfifo_bcnt_ch1(&self) -> OUT_CMDFIFO_OUTFIFO_BCNT_CH1_R { + OUT_CMDFIFO_OUTFIFO_BCNT_CH1_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_FIFO_BCNT_CH1") + .field( + "out_cmdfifo_outfifo_bcnt_ch1", + &format_args!("{}", self.out_cmdfifo_outfifo_bcnt_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH1 fifo byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_fifo_bcnt_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_FIFO_BCNT_CH1_SPEC; +impl crate::RegisterSpec for OUT_FIFO_BCNT_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_fifo_bcnt_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_FIFO_BCNT_CH1_SPEC {} +#[doc = "`reset()` method sets OUT_FIFO_BCNT_CH1 to value 0"] +impl crate::Resettable for OUT_FIFO_BCNT_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_fifo_bcnt_ch2.rs b/esp32p4/src/h264_dma/out_fifo_bcnt_ch2.rs new file mode 100644 index 0000000000..fa15802791 --- /dev/null +++ b/esp32p4/src/h264_dma/out_fifo_bcnt_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_FIFO_BCNT_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_OUTFIFO_BCNT_CH2` reader - only for debug"] +pub type OUT_CMDFIFO_OUTFIFO_BCNT_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_outfifo_bcnt_ch2(&self) -> OUT_CMDFIFO_OUTFIFO_BCNT_CH2_R { + OUT_CMDFIFO_OUTFIFO_BCNT_CH2_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_FIFO_BCNT_CH2") + .field( + "out_cmdfifo_outfifo_bcnt_ch2", + &format_args!("{}", self.out_cmdfifo_outfifo_bcnt_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH2 fifo byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_fifo_bcnt_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_FIFO_BCNT_CH2_SPEC; +impl crate::RegisterSpec for OUT_FIFO_BCNT_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_fifo_bcnt_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_FIFO_BCNT_CH2_SPEC {} +#[doc = "`reset()` method sets OUT_FIFO_BCNT_CH2 to value 0"] +impl crate::Resettable for OUT_FIFO_BCNT_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_fifo_bcnt_ch3.rs b/esp32p4/src/h264_dma/out_fifo_bcnt_ch3.rs new file mode 100644 index 0000000000..d3227c8f50 --- /dev/null +++ b/esp32p4/src/h264_dma/out_fifo_bcnt_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_FIFO_BCNT_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_OUTFIFO_BCNT_CH3` reader - only for debug"] +pub type OUT_CMDFIFO_OUTFIFO_BCNT_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_outfifo_bcnt_ch3(&self) -> OUT_CMDFIFO_OUTFIFO_BCNT_CH3_R { + OUT_CMDFIFO_OUTFIFO_BCNT_CH3_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_FIFO_BCNT_CH3") + .field( + "out_cmdfifo_outfifo_bcnt_ch3", + &format_args!("{}", self.out_cmdfifo_outfifo_bcnt_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH3 fifo byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_fifo_bcnt_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_FIFO_BCNT_CH3_SPEC; +impl crate::RegisterSpec for OUT_FIFO_BCNT_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_fifo_bcnt_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_FIFO_BCNT_CH3_SPEC {} +#[doc = "`reset()` method sets OUT_FIFO_BCNT_CH3 to value 0"] +impl crate::Resettable for OUT_FIFO_BCNT_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_fifo_bcnt_ch4.rs b/esp32p4/src/h264_dma/out_fifo_bcnt_ch4.rs new file mode 100644 index 0000000000..f1d6e74b98 --- /dev/null +++ b/esp32p4/src/h264_dma/out_fifo_bcnt_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_FIFO_BCNT_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_OUTFIFO_BCNT_CH4` reader - only for debug"] +pub type OUT_CMDFIFO_OUTFIFO_BCNT_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_outfifo_bcnt_ch4(&self) -> OUT_CMDFIFO_OUTFIFO_BCNT_CH4_R { + OUT_CMDFIFO_OUTFIFO_BCNT_CH4_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_FIFO_BCNT_CH4") + .field( + "out_cmdfifo_outfifo_bcnt_ch4", + &format_args!("{}", self.out_cmdfifo_outfifo_bcnt_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH4 fifo byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_fifo_bcnt_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_FIFO_BCNT_CH4_SPEC; +impl crate::RegisterSpec for OUT_FIFO_BCNT_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_fifo_bcnt_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_FIFO_BCNT_CH4_SPEC {} +#[doc = "`reset()` method sets OUT_FIFO_BCNT_CH4 to value 0"] +impl crate::Resettable for OUT_FIFO_BCNT_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_clr_ch0.rs b/esp32p4/src/h264_dma/out_int_clr_ch0.rs new file mode 100644 index 0000000000..333dd9b3f2 --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_clr_ch0.rs @@ -0,0 +1,118 @@ +#[doc = "Register `OUT_INT_CLR_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH0_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH0_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH0_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH0_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH0_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH0_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH0_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH0_INT_CLR` writer - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch0_int_clr(&mut self) -> OUT_DONE_CH0_INT_CLR_W { + OUT_DONE_CH0_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch0_int_clr(&mut self) -> OUT_EOF_CH0_INT_CLR_W { + OUT_EOF_CH0_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch0_int_clr(&mut self) -> OUT_DSCR_ERR_CH0_INT_CLR_W { + OUT_DSCR_ERR_CH0_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch0_int_clr( + &mut self, + ) -> OUT_TOTAL_EOF_CH0_INT_CLR_W { + OUT_TOTAL_EOF_CH0_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch0_int_clr( + &mut self, + ) -> OUTFIFO_OVF_L1_CH0_INT_CLR_W { + OUTFIFO_OVF_L1_CH0_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch0_int_clr( + &mut self, + ) -> OUTFIFO_UDF_L1_CH0_INT_CLR_W { + OUTFIFO_UDF_L1_CH0_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch0_int_clr( + &mut self, + ) -> OUTFIFO_OVF_L2_CH0_INT_CLR_W { + OUTFIFO_OVF_L2_CH0_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch0_int_clr( + &mut self, + ) -> OUTFIFO_UDF_L2_CH0_INT_CLR_W { + OUTFIFO_UDF_L2_CH0_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch0_int_clr( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH0_INT_CLR_W { + OUT_DSCR_TASK_OVF_CH0_INT_CLR_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH0 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_CLR_CH0_SPEC; +impl crate::RegisterSpec for OUT_INT_CLR_CH0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out_int_clr_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_INT_CLR_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_CLR_CH0 to value 0"] +impl crate::Resettable for OUT_INT_CLR_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_clr_ch1.rs b/esp32p4/src/h264_dma/out_int_clr_ch1.rs new file mode 100644 index 0000000000..ccd526d6e1 --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_clr_ch1.rs @@ -0,0 +1,118 @@ +#[doc = "Register `OUT_INT_CLR_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH1_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH1_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH1_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH1_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH1_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH1_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH1_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH1_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH1_INT_CLR` writer - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch1_int_clr(&mut self) -> OUT_DONE_CH1_INT_CLR_W { + OUT_DONE_CH1_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch1_int_clr(&mut self) -> OUT_EOF_CH1_INT_CLR_W { + OUT_EOF_CH1_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch1_int_clr(&mut self) -> OUT_DSCR_ERR_CH1_INT_CLR_W { + OUT_DSCR_ERR_CH1_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch1_int_clr( + &mut self, + ) -> OUT_TOTAL_EOF_CH1_INT_CLR_W { + OUT_TOTAL_EOF_CH1_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch1_int_clr( + &mut self, + ) -> OUTFIFO_OVF_L1_CH1_INT_CLR_W { + OUTFIFO_OVF_L1_CH1_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch1_int_clr( + &mut self, + ) -> OUTFIFO_UDF_L1_CH1_INT_CLR_W { + OUTFIFO_UDF_L1_CH1_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch1_int_clr( + &mut self, + ) -> OUTFIFO_OVF_L2_CH1_INT_CLR_W { + OUTFIFO_OVF_L2_CH1_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch1_int_clr( + &mut self, + ) -> OUTFIFO_UDF_L2_CH1_INT_CLR_W { + OUTFIFO_UDF_L2_CH1_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch1_int_clr( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH1_INT_CLR_W { + OUT_DSCR_TASK_OVF_CH1_INT_CLR_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH1 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_CLR_CH1_SPEC; +impl crate::RegisterSpec for OUT_INT_CLR_CH1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out_int_clr_ch1::W`](W) writer structure"] +impl crate::Writable for OUT_INT_CLR_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_CLR_CH1 to value 0"] +impl crate::Resettable for OUT_INT_CLR_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_clr_ch2.rs b/esp32p4/src/h264_dma/out_int_clr_ch2.rs new file mode 100644 index 0000000000..7bc6f6fbe6 --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_clr_ch2.rs @@ -0,0 +1,118 @@ +#[doc = "Register `OUT_INT_CLR_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH2_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH2_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH2_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH2_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH2_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH2_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH2_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH2_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH2_INT_CLR` writer - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch2_int_clr(&mut self) -> OUT_DONE_CH2_INT_CLR_W { + OUT_DONE_CH2_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch2_int_clr(&mut self) -> OUT_EOF_CH2_INT_CLR_W { + OUT_EOF_CH2_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch2_int_clr(&mut self) -> OUT_DSCR_ERR_CH2_INT_CLR_W { + OUT_DSCR_ERR_CH2_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch2_int_clr( + &mut self, + ) -> OUT_TOTAL_EOF_CH2_INT_CLR_W { + OUT_TOTAL_EOF_CH2_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch2_int_clr( + &mut self, + ) -> OUTFIFO_OVF_L1_CH2_INT_CLR_W { + OUTFIFO_OVF_L1_CH2_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch2_int_clr( + &mut self, + ) -> OUTFIFO_UDF_L1_CH2_INT_CLR_W { + OUTFIFO_UDF_L1_CH2_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch2_int_clr( + &mut self, + ) -> OUTFIFO_OVF_L2_CH2_INT_CLR_W { + OUTFIFO_OVF_L2_CH2_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch2_int_clr( + &mut self, + ) -> OUTFIFO_UDF_L2_CH2_INT_CLR_W { + OUTFIFO_UDF_L2_CH2_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch2_int_clr( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH2_INT_CLR_W { + OUT_DSCR_TASK_OVF_CH2_INT_CLR_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH2 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_CLR_CH2_SPEC; +impl crate::RegisterSpec for OUT_INT_CLR_CH2_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out_int_clr_ch2::W`](W) writer structure"] +impl crate::Writable for OUT_INT_CLR_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_CLR_CH2 to value 0"] +impl crate::Resettable for OUT_INT_CLR_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_clr_ch3.rs b/esp32p4/src/h264_dma/out_int_clr_ch3.rs new file mode 100644 index 0000000000..3e4cb09df1 --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_clr_ch3.rs @@ -0,0 +1,118 @@ +#[doc = "Register `OUT_INT_CLR_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH3_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH3_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH3_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH3_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH3_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH3_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH3_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH3_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH3_INT_CLR` writer - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch3_int_clr(&mut self) -> OUT_DONE_CH3_INT_CLR_W { + OUT_DONE_CH3_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch3_int_clr(&mut self) -> OUT_EOF_CH3_INT_CLR_W { + OUT_EOF_CH3_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch3_int_clr(&mut self) -> OUT_DSCR_ERR_CH3_INT_CLR_W { + OUT_DSCR_ERR_CH3_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch3_int_clr( + &mut self, + ) -> OUT_TOTAL_EOF_CH3_INT_CLR_W { + OUT_TOTAL_EOF_CH3_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch3_int_clr( + &mut self, + ) -> OUTFIFO_OVF_L1_CH3_INT_CLR_W { + OUTFIFO_OVF_L1_CH3_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch3_int_clr( + &mut self, + ) -> OUTFIFO_UDF_L1_CH3_INT_CLR_W { + OUTFIFO_UDF_L1_CH3_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch3_int_clr( + &mut self, + ) -> OUTFIFO_OVF_L2_CH3_INT_CLR_W { + OUTFIFO_OVF_L2_CH3_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch3_int_clr( + &mut self, + ) -> OUTFIFO_UDF_L2_CH3_INT_CLR_W { + OUTFIFO_UDF_L2_CH3_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch3_int_clr( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH3_INT_CLR_W { + OUT_DSCR_TASK_OVF_CH3_INT_CLR_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH3 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch3::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_CLR_CH3_SPEC; +impl crate::RegisterSpec for OUT_INT_CLR_CH3_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out_int_clr_ch3::W`](W) writer structure"] +impl crate::Writable for OUT_INT_CLR_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_CLR_CH3 to value 0"] +impl crate::Resettable for OUT_INT_CLR_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_clr_ch4.rs b/esp32p4/src/h264_dma/out_int_clr_ch4.rs new file mode 100644 index 0000000000..a025c79604 --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_clr_ch4.rs @@ -0,0 +1,118 @@ +#[doc = "Register `OUT_INT_CLR_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH4_INT_CLR` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH4_INT_CLR` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH4_INT_CLR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH4_INT_CLR` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH4_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH4_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH4_INT_CLR` writer - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH4_INT_CLR` writer - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH4_INT_CLR` writer - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch4_int_clr(&mut self) -> OUT_DONE_CH4_INT_CLR_W { + OUT_DONE_CH4_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch4_int_clr(&mut self) -> OUT_EOF_CH4_INT_CLR_W { + OUT_EOF_CH4_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch4_int_clr(&mut self) -> OUT_DSCR_ERR_CH4_INT_CLR_W { + OUT_DSCR_ERR_CH4_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch4_int_clr( + &mut self, + ) -> OUT_TOTAL_EOF_CH4_INT_CLR_W { + OUT_TOTAL_EOF_CH4_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch4_int_clr( + &mut self, + ) -> OUTFIFO_OVF_L1_CH4_INT_CLR_W { + OUTFIFO_OVF_L1_CH4_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch4_int_clr( + &mut self, + ) -> OUTFIFO_UDF_L1_CH4_INT_CLR_W { + OUTFIFO_UDF_L1_CH4_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch4_int_clr( + &mut self, + ) -> OUTFIFO_OVF_L2_CH4_INT_CLR_W { + OUTFIFO_OVF_L2_CH4_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch4_int_clr( + &mut self, + ) -> OUTFIFO_UDF_L2_CH4_INT_CLR_W { + OUTFIFO_UDF_L2_CH4_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch4_int_clr( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH4_INT_CLR_W { + OUT_DSCR_TASK_OVF_CH4_INT_CLR_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH4 interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_clr_ch4::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_CLR_CH4_SPEC; +impl crate::RegisterSpec for OUT_INT_CLR_CH4_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out_int_clr_ch4::W`](W) writer structure"] +impl crate::Writable for OUT_INT_CLR_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_CLR_CH4 to value 0"] +impl crate::Resettable for OUT_INT_CLR_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_ena_ch0.rs b/esp32p4/src/h264_dma/out_int_ena_ch0.rs new file mode 100644 index 0000000000..704ae4e2de --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_ena_ch0.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OUT_INT_ENA_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_ENA_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH0_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH0_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH0_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH0_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH0_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH0_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH0_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH0_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH0_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH0_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch0_int_ena(&self) -> OUT_DONE_CH0_INT_ENA_R { + OUT_DONE_CH0_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch0_int_ena(&self) -> OUT_EOF_CH0_INT_ENA_R { + OUT_EOF_CH0_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch0_int_ena(&self) -> OUT_DSCR_ERR_CH0_INT_ENA_R { + OUT_DSCR_ERR_CH0_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch0_int_ena(&self) -> OUT_TOTAL_EOF_CH0_INT_ENA_R { + OUT_TOTAL_EOF_CH0_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch0_int_ena(&self) -> OUTFIFO_OVF_L1_CH0_INT_ENA_R { + OUTFIFO_OVF_L1_CH0_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l1_ch0_int_ena(&self) -> OUTFIFO_UDF_L1_CH0_INT_ENA_R { + OUTFIFO_UDF_L1_CH0_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch0_int_ena(&self) -> OUTFIFO_OVF_L2_CH0_INT_ENA_R { + OUTFIFO_OVF_L2_CH0_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l2_ch0_int_ena(&self) -> OUTFIFO_UDF_L2_CH0_INT_ENA_R { + OUTFIFO_UDF_L2_CH0_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch0_int_ena(&self) -> OUT_DSCR_TASK_OVF_CH0_INT_ENA_R { + OUT_DSCR_TASK_OVF_CH0_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ENA_CH0") + .field( + "out_done_ch0_int_ena", + &format_args!("{}", self.out_done_ch0_int_ena().bit()), + ) + .field( + "out_eof_ch0_int_ena", + &format_args!("{}", self.out_eof_ch0_int_ena().bit()), + ) + .field( + "out_dscr_err_ch0_int_ena", + &format_args!("{}", self.out_dscr_err_ch0_int_ena().bit()), + ) + .field( + "out_total_eof_ch0_int_ena", + &format_args!("{}", self.out_total_eof_ch0_int_ena().bit()), + ) + .field( + "outfifo_ovf_l1_ch0_int_ena", + &format_args!("{}", self.outfifo_ovf_l1_ch0_int_ena().bit()), + ) + .field( + "outfifo_udf_l1_ch0_int_ena", + &format_args!("{}", self.outfifo_udf_l1_ch0_int_ena().bit()), + ) + .field( + "outfifo_ovf_l2_ch0_int_ena", + &format_args!("{}", self.outfifo_ovf_l2_ch0_int_ena().bit()), + ) + .field( + "outfifo_udf_l2_ch0_int_ena", + &format_args!("{}", self.outfifo_udf_l2_ch0_int_ena().bit()), + ) + .field( + "out_dscr_task_ovf_ch0_int_ena", + &format_args!("{}", self.out_dscr_task_ovf_ch0_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch0_int_ena(&mut self) -> OUT_DONE_CH0_INT_ENA_W { + OUT_DONE_CH0_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch0_int_ena(&mut self) -> OUT_EOF_CH0_INT_ENA_W { + OUT_EOF_CH0_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch0_int_ena(&mut self) -> OUT_DSCR_ERR_CH0_INT_ENA_W { + OUT_DSCR_ERR_CH0_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch0_int_ena( + &mut self, + ) -> OUT_TOTAL_EOF_CH0_INT_ENA_W { + OUT_TOTAL_EOF_CH0_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch0_int_ena( + &mut self, + ) -> OUTFIFO_OVF_L1_CH0_INT_ENA_W { + OUTFIFO_OVF_L1_CH0_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch0_int_ena( + &mut self, + ) -> OUTFIFO_UDF_L1_CH0_INT_ENA_W { + OUTFIFO_UDF_L1_CH0_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch0_int_ena( + &mut self, + ) -> OUTFIFO_OVF_L2_CH0_INT_ENA_W { + OUTFIFO_OVF_L2_CH0_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch0_int_ena( + &mut self, + ) -> OUTFIFO_UDF_L2_CH0_INT_ENA_W { + OUTFIFO_UDF_L2_CH0_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch0_int_ena( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH0_INT_ENA_W { + OUT_DSCR_TASK_OVF_CH0_INT_ENA_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH0 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ENA_CH0_SPEC; +impl crate::RegisterSpec for OUT_INT_ENA_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_ena_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ENA_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_ena_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_INT_ENA_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_ENA_CH0 to value 0"] +impl crate::Resettable for OUT_INT_ENA_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_ena_ch1.rs b/esp32p4/src/h264_dma/out_int_ena_ch1.rs new file mode 100644 index 0000000000..1e98f5391c --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_ena_ch1.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OUT_INT_ENA_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_ENA_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH1_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH1_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH1_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH1_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH1_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH1_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH1_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH1_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH1_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH1_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH1_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH1_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH1_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH1_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH1_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH1_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH1_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH1_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch1_int_ena(&self) -> OUT_DONE_CH1_INT_ENA_R { + OUT_DONE_CH1_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch1_int_ena(&self) -> OUT_EOF_CH1_INT_ENA_R { + OUT_EOF_CH1_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch1_int_ena(&self) -> OUT_DSCR_ERR_CH1_INT_ENA_R { + OUT_DSCR_ERR_CH1_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch1_int_ena(&self) -> OUT_TOTAL_EOF_CH1_INT_ENA_R { + OUT_TOTAL_EOF_CH1_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch1_int_ena(&self) -> OUTFIFO_OVF_L1_CH1_INT_ENA_R { + OUTFIFO_OVF_L1_CH1_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l1_ch1_int_ena(&self) -> OUTFIFO_UDF_L1_CH1_INT_ENA_R { + OUTFIFO_UDF_L1_CH1_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch1_int_ena(&self) -> OUTFIFO_OVF_L2_CH1_INT_ENA_R { + OUTFIFO_OVF_L2_CH1_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l2_ch1_int_ena(&self) -> OUTFIFO_UDF_L2_CH1_INT_ENA_R { + OUTFIFO_UDF_L2_CH1_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch1_int_ena(&self) -> OUT_DSCR_TASK_OVF_CH1_INT_ENA_R { + OUT_DSCR_TASK_OVF_CH1_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ENA_CH1") + .field( + "out_done_ch1_int_ena", + &format_args!("{}", self.out_done_ch1_int_ena().bit()), + ) + .field( + "out_eof_ch1_int_ena", + &format_args!("{}", self.out_eof_ch1_int_ena().bit()), + ) + .field( + "out_dscr_err_ch1_int_ena", + &format_args!("{}", self.out_dscr_err_ch1_int_ena().bit()), + ) + .field( + "out_total_eof_ch1_int_ena", + &format_args!("{}", self.out_total_eof_ch1_int_ena().bit()), + ) + .field( + "outfifo_ovf_l1_ch1_int_ena", + &format_args!("{}", self.outfifo_ovf_l1_ch1_int_ena().bit()), + ) + .field( + "outfifo_udf_l1_ch1_int_ena", + &format_args!("{}", self.outfifo_udf_l1_ch1_int_ena().bit()), + ) + .field( + "outfifo_ovf_l2_ch1_int_ena", + &format_args!("{}", self.outfifo_ovf_l2_ch1_int_ena().bit()), + ) + .field( + "outfifo_udf_l2_ch1_int_ena", + &format_args!("{}", self.outfifo_udf_l2_ch1_int_ena().bit()), + ) + .field( + "out_dscr_task_ovf_ch1_int_ena", + &format_args!("{}", self.out_dscr_task_ovf_ch1_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch1_int_ena(&mut self) -> OUT_DONE_CH1_INT_ENA_W { + OUT_DONE_CH1_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch1_int_ena(&mut self) -> OUT_EOF_CH1_INT_ENA_W { + OUT_EOF_CH1_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch1_int_ena(&mut self) -> OUT_DSCR_ERR_CH1_INT_ENA_W { + OUT_DSCR_ERR_CH1_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch1_int_ena( + &mut self, + ) -> OUT_TOTAL_EOF_CH1_INT_ENA_W { + OUT_TOTAL_EOF_CH1_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch1_int_ena( + &mut self, + ) -> OUTFIFO_OVF_L1_CH1_INT_ENA_W { + OUTFIFO_OVF_L1_CH1_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch1_int_ena( + &mut self, + ) -> OUTFIFO_UDF_L1_CH1_INT_ENA_W { + OUTFIFO_UDF_L1_CH1_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch1_int_ena( + &mut self, + ) -> OUTFIFO_OVF_L2_CH1_INT_ENA_W { + OUTFIFO_OVF_L2_CH1_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch1_int_ena( + &mut self, + ) -> OUTFIFO_UDF_L2_CH1_INT_ENA_W { + OUTFIFO_UDF_L2_CH1_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch1_int_ena( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH1_INT_ENA_W { + OUT_DSCR_TASK_OVF_CH1_INT_ENA_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH1 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ENA_CH1_SPEC; +impl crate::RegisterSpec for OUT_INT_ENA_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_ena_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ENA_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_ena_ch1::W`](W) writer structure"] +impl crate::Writable for OUT_INT_ENA_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_ENA_CH1 to value 0"] +impl crate::Resettable for OUT_INT_ENA_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_ena_ch2.rs b/esp32p4/src/h264_dma/out_int_ena_ch2.rs new file mode 100644 index 0000000000..c7f84c071a --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_ena_ch2.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OUT_INT_ENA_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_ENA_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH2_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH2_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH2_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH2_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH2_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH2_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH2_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH2_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH2_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH2_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH2_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH2_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH2_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH2_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH2_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH2_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH2_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH2_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch2_int_ena(&self) -> OUT_DONE_CH2_INT_ENA_R { + OUT_DONE_CH2_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch2_int_ena(&self) -> OUT_EOF_CH2_INT_ENA_R { + OUT_EOF_CH2_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch2_int_ena(&self) -> OUT_DSCR_ERR_CH2_INT_ENA_R { + OUT_DSCR_ERR_CH2_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch2_int_ena(&self) -> OUT_TOTAL_EOF_CH2_INT_ENA_R { + OUT_TOTAL_EOF_CH2_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch2_int_ena(&self) -> OUTFIFO_OVF_L1_CH2_INT_ENA_R { + OUTFIFO_OVF_L1_CH2_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l1_ch2_int_ena(&self) -> OUTFIFO_UDF_L1_CH2_INT_ENA_R { + OUTFIFO_UDF_L1_CH2_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch2_int_ena(&self) -> OUTFIFO_OVF_L2_CH2_INT_ENA_R { + OUTFIFO_OVF_L2_CH2_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l2_ch2_int_ena(&self) -> OUTFIFO_UDF_L2_CH2_INT_ENA_R { + OUTFIFO_UDF_L2_CH2_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch2_int_ena(&self) -> OUT_DSCR_TASK_OVF_CH2_INT_ENA_R { + OUT_DSCR_TASK_OVF_CH2_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ENA_CH2") + .field( + "out_done_ch2_int_ena", + &format_args!("{}", self.out_done_ch2_int_ena().bit()), + ) + .field( + "out_eof_ch2_int_ena", + &format_args!("{}", self.out_eof_ch2_int_ena().bit()), + ) + .field( + "out_dscr_err_ch2_int_ena", + &format_args!("{}", self.out_dscr_err_ch2_int_ena().bit()), + ) + .field( + "out_total_eof_ch2_int_ena", + &format_args!("{}", self.out_total_eof_ch2_int_ena().bit()), + ) + .field( + "outfifo_ovf_l1_ch2_int_ena", + &format_args!("{}", self.outfifo_ovf_l1_ch2_int_ena().bit()), + ) + .field( + "outfifo_udf_l1_ch2_int_ena", + &format_args!("{}", self.outfifo_udf_l1_ch2_int_ena().bit()), + ) + .field( + "outfifo_ovf_l2_ch2_int_ena", + &format_args!("{}", self.outfifo_ovf_l2_ch2_int_ena().bit()), + ) + .field( + "outfifo_udf_l2_ch2_int_ena", + &format_args!("{}", self.outfifo_udf_l2_ch2_int_ena().bit()), + ) + .field( + "out_dscr_task_ovf_ch2_int_ena", + &format_args!("{}", self.out_dscr_task_ovf_ch2_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch2_int_ena(&mut self) -> OUT_DONE_CH2_INT_ENA_W { + OUT_DONE_CH2_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch2_int_ena(&mut self) -> OUT_EOF_CH2_INT_ENA_W { + OUT_EOF_CH2_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch2_int_ena(&mut self) -> OUT_DSCR_ERR_CH2_INT_ENA_W { + OUT_DSCR_ERR_CH2_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch2_int_ena( + &mut self, + ) -> OUT_TOTAL_EOF_CH2_INT_ENA_W { + OUT_TOTAL_EOF_CH2_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch2_int_ena( + &mut self, + ) -> OUTFIFO_OVF_L1_CH2_INT_ENA_W { + OUTFIFO_OVF_L1_CH2_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch2_int_ena( + &mut self, + ) -> OUTFIFO_UDF_L1_CH2_INT_ENA_W { + OUTFIFO_UDF_L1_CH2_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch2_int_ena( + &mut self, + ) -> OUTFIFO_OVF_L2_CH2_INT_ENA_W { + OUTFIFO_OVF_L2_CH2_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch2_int_ena( + &mut self, + ) -> OUTFIFO_UDF_L2_CH2_INT_ENA_W { + OUTFIFO_UDF_L2_CH2_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch2_int_ena( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH2_INT_ENA_W { + OUT_DSCR_TASK_OVF_CH2_INT_ENA_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH2 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ENA_CH2_SPEC; +impl crate::RegisterSpec for OUT_INT_ENA_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_ena_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ENA_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_ena_ch2::W`](W) writer structure"] +impl crate::Writable for OUT_INT_ENA_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_ENA_CH2 to value 0"] +impl crate::Resettable for OUT_INT_ENA_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_ena_ch3.rs b/esp32p4/src/h264_dma/out_int_ena_ch3.rs new file mode 100644 index 0000000000..2fd5478b30 --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_ena_ch3.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OUT_INT_ENA_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_ENA_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH3_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH3_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH3_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH3_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH3_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH3_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH3_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH3_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH3_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH3_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH3_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH3_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH3_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH3_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH3_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH3_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH3_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH3_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch3_int_ena(&self) -> OUT_DONE_CH3_INT_ENA_R { + OUT_DONE_CH3_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch3_int_ena(&self) -> OUT_EOF_CH3_INT_ENA_R { + OUT_EOF_CH3_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch3_int_ena(&self) -> OUT_DSCR_ERR_CH3_INT_ENA_R { + OUT_DSCR_ERR_CH3_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch3_int_ena(&self) -> OUT_TOTAL_EOF_CH3_INT_ENA_R { + OUT_TOTAL_EOF_CH3_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch3_int_ena(&self) -> OUTFIFO_OVF_L1_CH3_INT_ENA_R { + OUTFIFO_OVF_L1_CH3_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l1_ch3_int_ena(&self) -> OUTFIFO_UDF_L1_CH3_INT_ENA_R { + OUTFIFO_UDF_L1_CH3_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch3_int_ena(&self) -> OUTFIFO_OVF_L2_CH3_INT_ENA_R { + OUTFIFO_OVF_L2_CH3_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l2_ch3_int_ena(&self) -> OUTFIFO_UDF_L2_CH3_INT_ENA_R { + OUTFIFO_UDF_L2_CH3_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch3_int_ena(&self) -> OUT_DSCR_TASK_OVF_CH3_INT_ENA_R { + OUT_DSCR_TASK_OVF_CH3_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ENA_CH3") + .field( + "out_done_ch3_int_ena", + &format_args!("{}", self.out_done_ch3_int_ena().bit()), + ) + .field( + "out_eof_ch3_int_ena", + &format_args!("{}", self.out_eof_ch3_int_ena().bit()), + ) + .field( + "out_dscr_err_ch3_int_ena", + &format_args!("{}", self.out_dscr_err_ch3_int_ena().bit()), + ) + .field( + "out_total_eof_ch3_int_ena", + &format_args!("{}", self.out_total_eof_ch3_int_ena().bit()), + ) + .field( + "outfifo_ovf_l1_ch3_int_ena", + &format_args!("{}", self.outfifo_ovf_l1_ch3_int_ena().bit()), + ) + .field( + "outfifo_udf_l1_ch3_int_ena", + &format_args!("{}", self.outfifo_udf_l1_ch3_int_ena().bit()), + ) + .field( + "outfifo_ovf_l2_ch3_int_ena", + &format_args!("{}", self.outfifo_ovf_l2_ch3_int_ena().bit()), + ) + .field( + "outfifo_udf_l2_ch3_int_ena", + &format_args!("{}", self.outfifo_udf_l2_ch3_int_ena().bit()), + ) + .field( + "out_dscr_task_ovf_ch3_int_ena", + &format_args!("{}", self.out_dscr_task_ovf_ch3_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch3_int_ena(&mut self) -> OUT_DONE_CH3_INT_ENA_W { + OUT_DONE_CH3_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch3_int_ena(&mut self) -> OUT_EOF_CH3_INT_ENA_W { + OUT_EOF_CH3_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch3_int_ena(&mut self) -> OUT_DSCR_ERR_CH3_INT_ENA_W { + OUT_DSCR_ERR_CH3_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch3_int_ena( + &mut self, + ) -> OUT_TOTAL_EOF_CH3_INT_ENA_W { + OUT_TOTAL_EOF_CH3_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch3_int_ena( + &mut self, + ) -> OUTFIFO_OVF_L1_CH3_INT_ENA_W { + OUTFIFO_OVF_L1_CH3_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch3_int_ena( + &mut self, + ) -> OUTFIFO_UDF_L1_CH3_INT_ENA_W { + OUTFIFO_UDF_L1_CH3_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch3_int_ena( + &mut self, + ) -> OUTFIFO_OVF_L2_CH3_INT_ENA_W { + OUTFIFO_OVF_L2_CH3_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch3_int_ena( + &mut self, + ) -> OUTFIFO_UDF_L2_CH3_INT_ENA_W { + OUTFIFO_UDF_L2_CH3_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch3_int_ena( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH3_INT_ENA_W { + OUT_DSCR_TASK_OVF_CH3_INT_ENA_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH3 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ENA_CH3_SPEC; +impl crate::RegisterSpec for OUT_INT_ENA_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_ena_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ENA_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_ena_ch3::W`](W) writer structure"] +impl crate::Writable for OUT_INT_ENA_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_ENA_CH3 to value 0"] +impl crate::Resettable for OUT_INT_ENA_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_ena_ch4.rs b/esp32p4/src/h264_dma/out_int_ena_ch4.rs new file mode 100644 index 0000000000..cd7d7aa43f --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_ena_ch4.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OUT_INT_ENA_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_ENA_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH4_INT_ENA` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH4_INT_ENA` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH4_INT_ENA` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH4_INT_ENA` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH4_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH4_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH4_INT_ENA` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH4_INT_ENA` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH4_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH4_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH4_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH4_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH4_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH4_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH4_INT_ENA` reader - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH4_INT_ENA` writer - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH4_INT_ENA` reader - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH4_INT_ENA` writer - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch4_int_ena(&self) -> OUT_DONE_CH4_INT_ENA_R { + OUT_DONE_CH4_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch4_int_ena(&self) -> OUT_EOF_CH4_INT_ENA_R { + OUT_EOF_CH4_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch4_int_ena(&self) -> OUT_DSCR_ERR_CH4_INT_ENA_R { + OUT_DSCR_ERR_CH4_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch4_int_ena(&self) -> OUT_TOTAL_EOF_CH4_INT_ENA_R { + OUT_TOTAL_EOF_CH4_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch4_int_ena(&self) -> OUTFIFO_OVF_L1_CH4_INT_ENA_R { + OUTFIFO_OVF_L1_CH4_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l1_ch4_int_ena(&self) -> OUTFIFO_UDF_L1_CH4_INT_ENA_R { + OUTFIFO_UDF_L1_CH4_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch4_int_ena(&self) -> OUTFIFO_OVF_L2_CH4_INT_ENA_R { + OUTFIFO_OVF_L2_CH4_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l2_ch4_int_ena(&self) -> OUTFIFO_UDF_L2_CH4_INT_ENA_R { + OUTFIFO_UDF_L2_CH4_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch4_int_ena(&self) -> OUT_DSCR_TASK_OVF_CH4_INT_ENA_R { + OUT_DSCR_TASK_OVF_CH4_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ENA_CH4") + .field( + "out_done_ch4_int_ena", + &format_args!("{}", self.out_done_ch4_int_ena().bit()), + ) + .field( + "out_eof_ch4_int_ena", + &format_args!("{}", self.out_eof_ch4_int_ena().bit()), + ) + .field( + "out_dscr_err_ch4_int_ena", + &format_args!("{}", self.out_dscr_err_ch4_int_ena().bit()), + ) + .field( + "out_total_eof_ch4_int_ena", + &format_args!("{}", self.out_total_eof_ch4_int_ena().bit()), + ) + .field( + "outfifo_ovf_l1_ch4_int_ena", + &format_args!("{}", self.outfifo_ovf_l1_ch4_int_ena().bit()), + ) + .field( + "outfifo_udf_l1_ch4_int_ena", + &format_args!("{}", self.outfifo_udf_l1_ch4_int_ena().bit()), + ) + .field( + "outfifo_ovf_l2_ch4_int_ena", + &format_args!("{}", self.outfifo_ovf_l2_ch4_int_ena().bit()), + ) + .field( + "outfifo_udf_l2_ch4_int_ena", + &format_args!("{}", self.outfifo_udf_l2_ch4_int_ena().bit()), + ) + .field( + "out_dscr_task_ovf_ch4_int_ena", + &format_args!("{}", self.out_dscr_task_ovf_ch4_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_done_ch4_int_ena(&mut self) -> OUT_DONE_CH4_INT_ENA_W { + OUT_DONE_CH4_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch4_int_ena(&mut self) -> OUT_EOF_CH4_INT_ENA_W { + OUT_EOF_CH4_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch4_int_ena(&mut self) -> OUT_DSCR_ERR_CH4_INT_ENA_W { + OUT_DSCR_ERR_CH4_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch4_int_ena( + &mut self, + ) -> OUT_TOTAL_EOF_CH4_INT_ENA_W { + OUT_TOTAL_EOF_CH4_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch4_int_ena( + &mut self, + ) -> OUTFIFO_OVF_L1_CH4_INT_ENA_W { + OUTFIFO_OVF_L1_CH4_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch4_int_ena( + &mut self, + ) -> OUTFIFO_UDF_L1_CH4_INT_ENA_W { + OUTFIFO_UDF_L1_CH4_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch4_int_ena( + &mut self, + ) -> OUTFIFO_OVF_L2_CH4_INT_ENA_W { + OUTFIFO_OVF_L2_CH4_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch4_int_ena( + &mut self, + ) -> OUTFIFO_UDF_L2_CH4_INT_ENA_W { + OUTFIFO_UDF_L2_CH4_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch4_int_ena( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH4_INT_ENA_W { + OUT_DSCR_TASK_OVF_CH4_INT_ENA_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH4 interrupt ena register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_ena_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_ena_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ENA_CH4_SPEC; +impl crate::RegisterSpec for OUT_INT_ENA_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_ena_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ENA_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_ena_ch4::W`](W) writer structure"] +impl crate::Writable for OUT_INT_ENA_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_ENA_CH4 to value 0"] +impl crate::Resettable for OUT_INT_ENA_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_raw_ch0.rs b/esp32p4/src/h264_dma/out_int_raw_ch0.rs new file mode 100644 index 0000000000..136d304275 --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_raw_ch0.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OUT_INT_RAW_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_RAW_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L1_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L1_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L1_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L1_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L2_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L2_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L2_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L2_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH0_INT_RAW` reader - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type OUT_DSCR_TASK_OVF_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH0_INT_RAW` writer - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type OUT_DSCR_TASK_OVF_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + pub fn out_done_ch0_int_raw(&self) -> OUT_DONE_CH0_INT_RAW_R { + OUT_DONE_CH0_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + pub fn out_eof_ch0_int_raw(&self) -> OUT_EOF_CH0_INT_RAW_R { + OUT_EOF_CH0_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + pub fn out_dscr_err_ch0_int_raw(&self) -> OUT_DSCR_ERR_CH0_INT_RAW_R { + OUT_DSCR_ERR_CH0_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + pub fn out_total_eof_ch0_int_raw(&self) -> OUT_TOTAL_EOF_CH0_INT_RAW_R { + OUT_TOTAL_EOF_CH0_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch0_int_raw(&self) -> OUTFIFO_OVF_L1_CH0_INT_RAW_R { + OUTFIFO_OVF_L1_CH0_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + pub fn outfifo_udf_l1_ch0_int_raw(&self) -> OUTFIFO_UDF_L1_CH0_INT_RAW_R { + OUTFIFO_UDF_L1_CH0_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch0_int_raw(&self) -> OUTFIFO_OVF_L2_CH0_INT_RAW_R { + OUTFIFO_OVF_L2_CH0_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + pub fn outfifo_udf_l2_ch0_int_raw(&self) -> OUTFIFO_UDF_L2_CH0_INT_RAW_R { + OUTFIFO_UDF_L2_CH0_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch0_int_raw(&self) -> OUT_DSCR_TASK_OVF_CH0_INT_RAW_R { + OUT_DSCR_TASK_OVF_CH0_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_RAW_CH0") + .field( + "out_done_ch0_int_raw", + &format_args!("{}", self.out_done_ch0_int_raw().bit()), + ) + .field( + "out_eof_ch0_int_raw", + &format_args!("{}", self.out_eof_ch0_int_raw().bit()), + ) + .field( + "out_dscr_err_ch0_int_raw", + &format_args!("{}", self.out_dscr_err_ch0_int_raw().bit()), + ) + .field( + "out_total_eof_ch0_int_raw", + &format_args!("{}", self.out_total_eof_ch0_int_raw().bit()), + ) + .field( + "outfifo_ovf_l1_ch0_int_raw", + &format_args!("{}", self.outfifo_ovf_l1_ch0_int_raw().bit()), + ) + .field( + "outfifo_udf_l1_ch0_int_raw", + &format_args!("{}", self.outfifo_udf_l1_ch0_int_raw().bit()), + ) + .field( + "outfifo_ovf_l2_ch0_int_raw", + &format_args!("{}", self.outfifo_ovf_l2_ch0_int_raw().bit()), + ) + .field( + "outfifo_udf_l2_ch0_int_raw", + &format_args!("{}", self.outfifo_udf_l2_ch0_int_raw().bit()), + ) + .field( + "out_dscr_task_ovf_ch0_int_raw", + &format_args!("{}", self.out_dscr_task_ovf_ch0_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_done_ch0_int_raw(&mut self) -> OUT_DONE_CH0_INT_RAW_W { + OUT_DONE_CH0_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch0_int_raw(&mut self) -> OUT_EOF_CH0_INT_RAW_W { + OUT_EOF_CH0_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch0_int_raw(&mut self) -> OUT_DSCR_ERR_CH0_INT_RAW_W { + OUT_DSCR_ERR_CH0_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch0_int_raw( + &mut self, + ) -> OUT_TOTAL_EOF_CH0_INT_RAW_W { + OUT_TOTAL_EOF_CH0_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch0_int_raw( + &mut self, + ) -> OUTFIFO_OVF_L1_CH0_INT_RAW_W { + OUTFIFO_OVF_L1_CH0_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch0_int_raw( + &mut self, + ) -> OUTFIFO_UDF_L1_CH0_INT_RAW_W { + OUTFIFO_UDF_L1_CH0_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch0_int_raw( + &mut self, + ) -> OUTFIFO_OVF_L2_CH0_INT_RAW_W { + OUTFIFO_OVF_L2_CH0_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch0_int_raw( + &mut self, + ) -> OUTFIFO_UDF_L2_CH0_INT_RAW_W { + OUTFIFO_UDF_L2_CH0_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch0_int_raw( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH0_INT_RAW_W { + OUT_DSCR_TASK_OVF_CH0_INT_RAW_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH0 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_RAW_CH0_SPEC; +impl crate::RegisterSpec for OUT_INT_RAW_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_raw_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_INT_RAW_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_raw_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_INT_RAW_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_RAW_CH0 to value 0"] +impl crate::Resettable for OUT_INT_RAW_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_raw_ch1.rs b/esp32p4/src/h264_dma/out_int_raw_ch1.rs new file mode 100644 index 0000000000..552e16213a --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_raw_ch1.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OUT_INT_RAW_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_RAW_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L1_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L1_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L1_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L1_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L2_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L2_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L2_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L2_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH1_INT_RAW` reader - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type OUT_DSCR_TASK_OVF_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH1_INT_RAW` writer - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type OUT_DSCR_TASK_OVF_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + pub fn out_done_ch1_int_raw(&self) -> OUT_DONE_CH1_INT_RAW_R { + OUT_DONE_CH1_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + pub fn out_eof_ch1_int_raw(&self) -> OUT_EOF_CH1_INT_RAW_R { + OUT_EOF_CH1_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + pub fn out_dscr_err_ch1_int_raw(&self) -> OUT_DSCR_ERR_CH1_INT_RAW_R { + OUT_DSCR_ERR_CH1_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + pub fn out_total_eof_ch1_int_raw(&self) -> OUT_TOTAL_EOF_CH1_INT_RAW_R { + OUT_TOTAL_EOF_CH1_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch1_int_raw(&self) -> OUTFIFO_OVF_L1_CH1_INT_RAW_R { + OUTFIFO_OVF_L1_CH1_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + pub fn outfifo_udf_l1_ch1_int_raw(&self) -> OUTFIFO_UDF_L1_CH1_INT_RAW_R { + OUTFIFO_UDF_L1_CH1_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch1_int_raw(&self) -> OUTFIFO_OVF_L2_CH1_INT_RAW_R { + OUTFIFO_OVF_L2_CH1_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + pub fn outfifo_udf_l2_ch1_int_raw(&self) -> OUTFIFO_UDF_L2_CH1_INT_RAW_R { + OUTFIFO_UDF_L2_CH1_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch1_int_raw(&self) -> OUT_DSCR_TASK_OVF_CH1_INT_RAW_R { + OUT_DSCR_TASK_OVF_CH1_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_RAW_CH1") + .field( + "out_done_ch1_int_raw", + &format_args!("{}", self.out_done_ch1_int_raw().bit()), + ) + .field( + "out_eof_ch1_int_raw", + &format_args!("{}", self.out_eof_ch1_int_raw().bit()), + ) + .field( + "out_dscr_err_ch1_int_raw", + &format_args!("{}", self.out_dscr_err_ch1_int_raw().bit()), + ) + .field( + "out_total_eof_ch1_int_raw", + &format_args!("{}", self.out_total_eof_ch1_int_raw().bit()), + ) + .field( + "outfifo_ovf_l1_ch1_int_raw", + &format_args!("{}", self.outfifo_ovf_l1_ch1_int_raw().bit()), + ) + .field( + "outfifo_udf_l1_ch1_int_raw", + &format_args!("{}", self.outfifo_udf_l1_ch1_int_raw().bit()), + ) + .field( + "outfifo_ovf_l2_ch1_int_raw", + &format_args!("{}", self.outfifo_ovf_l2_ch1_int_raw().bit()), + ) + .field( + "outfifo_udf_l2_ch1_int_raw", + &format_args!("{}", self.outfifo_udf_l2_ch1_int_raw().bit()), + ) + .field( + "out_dscr_task_ovf_ch1_int_raw", + &format_args!("{}", self.out_dscr_task_ovf_ch1_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_done_ch1_int_raw(&mut self) -> OUT_DONE_CH1_INT_RAW_W { + OUT_DONE_CH1_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch1_int_raw(&mut self) -> OUT_EOF_CH1_INT_RAW_W { + OUT_EOF_CH1_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch1_int_raw(&mut self) -> OUT_DSCR_ERR_CH1_INT_RAW_W { + OUT_DSCR_ERR_CH1_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch1_int_raw( + &mut self, + ) -> OUT_TOTAL_EOF_CH1_INT_RAW_W { + OUT_TOTAL_EOF_CH1_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch1_int_raw( + &mut self, + ) -> OUTFIFO_OVF_L1_CH1_INT_RAW_W { + OUTFIFO_OVF_L1_CH1_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch1_int_raw( + &mut self, + ) -> OUTFIFO_UDF_L1_CH1_INT_RAW_W { + OUTFIFO_UDF_L1_CH1_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch1_int_raw( + &mut self, + ) -> OUTFIFO_OVF_L2_CH1_INT_RAW_W { + OUTFIFO_OVF_L2_CH1_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch1_int_raw( + &mut self, + ) -> OUTFIFO_UDF_L2_CH1_INT_RAW_W { + OUTFIFO_UDF_L2_CH1_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch1_int_raw( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH1_INT_RAW_W { + OUT_DSCR_TASK_OVF_CH1_INT_RAW_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH1 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_RAW_CH1_SPEC; +impl crate::RegisterSpec for OUT_INT_RAW_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_raw_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_INT_RAW_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_raw_ch1::W`](W) writer structure"] +impl crate::Writable for OUT_INT_RAW_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_RAW_CH1 to value 0"] +impl crate::Resettable for OUT_INT_RAW_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_raw_ch2.rs b/esp32p4/src/h264_dma/out_int_raw_ch2.rs new file mode 100644 index 0000000000..6c6c334bc4 --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_raw_ch2.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OUT_INT_RAW_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_RAW_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L1_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L1_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L1_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L1_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L2_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L2_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L2_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L2_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH2_INT_RAW` reader - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type OUT_DSCR_TASK_OVF_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH2_INT_RAW` writer - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type OUT_DSCR_TASK_OVF_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + pub fn out_done_ch2_int_raw(&self) -> OUT_DONE_CH2_INT_RAW_R { + OUT_DONE_CH2_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + pub fn out_eof_ch2_int_raw(&self) -> OUT_EOF_CH2_INT_RAW_R { + OUT_EOF_CH2_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + pub fn out_dscr_err_ch2_int_raw(&self) -> OUT_DSCR_ERR_CH2_INT_RAW_R { + OUT_DSCR_ERR_CH2_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + pub fn out_total_eof_ch2_int_raw(&self) -> OUT_TOTAL_EOF_CH2_INT_RAW_R { + OUT_TOTAL_EOF_CH2_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch2_int_raw(&self) -> OUTFIFO_OVF_L1_CH2_INT_RAW_R { + OUTFIFO_OVF_L1_CH2_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + pub fn outfifo_udf_l1_ch2_int_raw(&self) -> OUTFIFO_UDF_L1_CH2_INT_RAW_R { + OUTFIFO_UDF_L1_CH2_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch2_int_raw(&self) -> OUTFIFO_OVF_L2_CH2_INT_RAW_R { + OUTFIFO_OVF_L2_CH2_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + pub fn outfifo_udf_l2_ch2_int_raw(&self) -> OUTFIFO_UDF_L2_CH2_INT_RAW_R { + OUTFIFO_UDF_L2_CH2_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch2_int_raw(&self) -> OUT_DSCR_TASK_OVF_CH2_INT_RAW_R { + OUT_DSCR_TASK_OVF_CH2_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_RAW_CH2") + .field( + "out_done_ch2_int_raw", + &format_args!("{}", self.out_done_ch2_int_raw().bit()), + ) + .field( + "out_eof_ch2_int_raw", + &format_args!("{}", self.out_eof_ch2_int_raw().bit()), + ) + .field( + "out_dscr_err_ch2_int_raw", + &format_args!("{}", self.out_dscr_err_ch2_int_raw().bit()), + ) + .field( + "out_total_eof_ch2_int_raw", + &format_args!("{}", self.out_total_eof_ch2_int_raw().bit()), + ) + .field( + "outfifo_ovf_l1_ch2_int_raw", + &format_args!("{}", self.outfifo_ovf_l1_ch2_int_raw().bit()), + ) + .field( + "outfifo_udf_l1_ch2_int_raw", + &format_args!("{}", self.outfifo_udf_l1_ch2_int_raw().bit()), + ) + .field( + "outfifo_ovf_l2_ch2_int_raw", + &format_args!("{}", self.outfifo_ovf_l2_ch2_int_raw().bit()), + ) + .field( + "outfifo_udf_l2_ch2_int_raw", + &format_args!("{}", self.outfifo_udf_l2_ch2_int_raw().bit()), + ) + .field( + "out_dscr_task_ovf_ch2_int_raw", + &format_args!("{}", self.out_dscr_task_ovf_ch2_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_done_ch2_int_raw(&mut self) -> OUT_DONE_CH2_INT_RAW_W { + OUT_DONE_CH2_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch2_int_raw(&mut self) -> OUT_EOF_CH2_INT_RAW_W { + OUT_EOF_CH2_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch2_int_raw(&mut self) -> OUT_DSCR_ERR_CH2_INT_RAW_W { + OUT_DSCR_ERR_CH2_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch2_int_raw( + &mut self, + ) -> OUT_TOTAL_EOF_CH2_INT_RAW_W { + OUT_TOTAL_EOF_CH2_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch2_int_raw( + &mut self, + ) -> OUTFIFO_OVF_L1_CH2_INT_RAW_W { + OUTFIFO_OVF_L1_CH2_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch2_int_raw( + &mut self, + ) -> OUTFIFO_UDF_L1_CH2_INT_RAW_W { + OUTFIFO_UDF_L1_CH2_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch2_int_raw( + &mut self, + ) -> OUTFIFO_OVF_L2_CH2_INT_RAW_W { + OUTFIFO_OVF_L2_CH2_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch2_int_raw( + &mut self, + ) -> OUTFIFO_UDF_L2_CH2_INT_RAW_W { + OUTFIFO_UDF_L2_CH2_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch2_int_raw( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH2_INT_RAW_W { + OUT_DSCR_TASK_OVF_CH2_INT_RAW_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH2 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_RAW_CH2_SPEC; +impl crate::RegisterSpec for OUT_INT_RAW_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_raw_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_INT_RAW_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_raw_ch2::W`](W) writer structure"] +impl crate::Writable for OUT_INT_RAW_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_RAW_CH2 to value 0"] +impl crate::Resettable for OUT_INT_RAW_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_raw_ch3.rs b/esp32p4/src/h264_dma/out_int_raw_ch3.rs new file mode 100644 index 0000000000..f9118ffe8f --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_raw_ch3.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OUT_INT_RAW_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_RAW_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L1_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L1_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L1_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L1_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L2_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L2_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L2_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L2_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH3_INT_RAW` reader - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type OUT_DSCR_TASK_OVF_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH3_INT_RAW` writer - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type OUT_DSCR_TASK_OVF_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + pub fn out_done_ch3_int_raw(&self) -> OUT_DONE_CH3_INT_RAW_R { + OUT_DONE_CH3_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + pub fn out_eof_ch3_int_raw(&self) -> OUT_EOF_CH3_INT_RAW_R { + OUT_EOF_CH3_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + pub fn out_dscr_err_ch3_int_raw(&self) -> OUT_DSCR_ERR_CH3_INT_RAW_R { + OUT_DSCR_ERR_CH3_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + pub fn out_total_eof_ch3_int_raw(&self) -> OUT_TOTAL_EOF_CH3_INT_RAW_R { + OUT_TOTAL_EOF_CH3_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch3_int_raw(&self) -> OUTFIFO_OVF_L1_CH3_INT_RAW_R { + OUTFIFO_OVF_L1_CH3_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + pub fn outfifo_udf_l1_ch3_int_raw(&self) -> OUTFIFO_UDF_L1_CH3_INT_RAW_R { + OUTFIFO_UDF_L1_CH3_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch3_int_raw(&self) -> OUTFIFO_OVF_L2_CH3_INT_RAW_R { + OUTFIFO_OVF_L2_CH3_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + pub fn outfifo_udf_l2_ch3_int_raw(&self) -> OUTFIFO_UDF_L2_CH3_INT_RAW_R { + OUTFIFO_UDF_L2_CH3_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch3_int_raw(&self) -> OUT_DSCR_TASK_OVF_CH3_INT_RAW_R { + OUT_DSCR_TASK_OVF_CH3_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_RAW_CH3") + .field( + "out_done_ch3_int_raw", + &format_args!("{}", self.out_done_ch3_int_raw().bit()), + ) + .field( + "out_eof_ch3_int_raw", + &format_args!("{}", self.out_eof_ch3_int_raw().bit()), + ) + .field( + "out_dscr_err_ch3_int_raw", + &format_args!("{}", self.out_dscr_err_ch3_int_raw().bit()), + ) + .field( + "out_total_eof_ch3_int_raw", + &format_args!("{}", self.out_total_eof_ch3_int_raw().bit()), + ) + .field( + "outfifo_ovf_l1_ch3_int_raw", + &format_args!("{}", self.outfifo_ovf_l1_ch3_int_raw().bit()), + ) + .field( + "outfifo_udf_l1_ch3_int_raw", + &format_args!("{}", self.outfifo_udf_l1_ch3_int_raw().bit()), + ) + .field( + "outfifo_ovf_l2_ch3_int_raw", + &format_args!("{}", self.outfifo_ovf_l2_ch3_int_raw().bit()), + ) + .field( + "outfifo_udf_l2_ch3_int_raw", + &format_args!("{}", self.outfifo_udf_l2_ch3_int_raw().bit()), + ) + .field( + "out_dscr_task_ovf_ch3_int_raw", + &format_args!("{}", self.out_dscr_task_ovf_ch3_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_done_ch3_int_raw(&mut self) -> OUT_DONE_CH3_INT_RAW_W { + OUT_DONE_CH3_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch3_int_raw(&mut self) -> OUT_EOF_CH3_INT_RAW_W { + OUT_EOF_CH3_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch3_int_raw(&mut self) -> OUT_DSCR_ERR_CH3_INT_RAW_W { + OUT_DSCR_ERR_CH3_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch3_int_raw( + &mut self, + ) -> OUT_TOTAL_EOF_CH3_INT_RAW_W { + OUT_TOTAL_EOF_CH3_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch3_int_raw( + &mut self, + ) -> OUTFIFO_OVF_L1_CH3_INT_RAW_W { + OUTFIFO_OVF_L1_CH3_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch3_int_raw( + &mut self, + ) -> OUTFIFO_UDF_L1_CH3_INT_RAW_W { + OUTFIFO_UDF_L1_CH3_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch3_int_raw( + &mut self, + ) -> OUTFIFO_OVF_L2_CH3_INT_RAW_W { + OUTFIFO_OVF_L2_CH3_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch3_int_raw( + &mut self, + ) -> OUTFIFO_UDF_L2_CH3_INT_RAW_W { + OUTFIFO_UDF_L2_CH3_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch3_int_raw( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH3_INT_RAW_W { + OUT_DSCR_TASK_OVF_CH3_INT_RAW_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH3 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_RAW_CH3_SPEC; +impl crate::RegisterSpec for OUT_INT_RAW_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_raw_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_INT_RAW_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_raw_ch3::W`](W) writer structure"] +impl crate::Writable for OUT_INT_RAW_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_RAW_CH3 to value 0"] +impl crate::Resettable for OUT_INT_RAW_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_raw_ch4.rs b/esp32p4/src/h264_dma/out_int_raw_ch4.rs new file mode 100644 index 0000000000..10dacb744e --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_raw_ch4.rs @@ -0,0 +1,230 @@ +#[doc = "Register `OUT_INT_RAW_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_INT_RAW_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_DONE_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DONE_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] +pub type OUT_DONE_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] +pub type OUT_EOF_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_ERR_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] +pub type OUT_DSCR_ERR_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_TOTAL_EOF_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] +pub type OUT_TOTAL_EOF_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L1_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L1_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L1_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L1_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L1_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L1_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_OVF_L2_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L2_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is overflow."] +pub type OUTFIFO_OVF_L2_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTFIFO_UDF_L2_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L2_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when fifo is underflow."] +pub type OUTFIFO_UDF_L2_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH4_INT_RAW` reader - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type OUT_DSCR_TASK_OVF_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH4_INT_RAW` writer - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] +pub type OUT_DSCR_TASK_OVF_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + pub fn out_done_ch4_int_raw(&self) -> OUT_DONE_CH4_INT_RAW_R { + OUT_DONE_CH4_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + pub fn out_eof_ch4_int_raw(&self) -> OUT_EOF_CH4_INT_RAW_R { + OUT_EOF_CH4_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + pub fn out_dscr_err_ch4_int_raw(&self) -> OUT_DSCR_ERR_CH4_INT_RAW_R { + OUT_DSCR_ERR_CH4_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + pub fn out_total_eof_ch4_int_raw(&self) -> OUT_TOTAL_EOF_CH4_INT_RAW_R { + OUT_TOTAL_EOF_CH4_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch4_int_raw(&self) -> OUTFIFO_OVF_L1_CH4_INT_RAW_R { + OUTFIFO_OVF_L1_CH4_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + pub fn outfifo_udf_l1_ch4_int_raw(&self) -> OUTFIFO_UDF_L1_CH4_INT_RAW_R { + OUTFIFO_UDF_L1_CH4_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch4_int_raw(&self) -> OUTFIFO_OVF_L2_CH4_INT_RAW_R { + OUTFIFO_OVF_L2_CH4_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + pub fn outfifo_udf_l2_ch4_int_raw(&self) -> OUTFIFO_UDF_L2_CH4_INT_RAW_R { + OUTFIFO_UDF_L2_CH4_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch4_int_raw(&self) -> OUT_DSCR_TASK_OVF_CH4_INT_RAW_R { + OUT_DSCR_TASK_OVF_CH4_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_RAW_CH4") + .field( + "out_done_ch4_int_raw", + &format_args!("{}", self.out_done_ch4_int_raw().bit()), + ) + .field( + "out_eof_ch4_int_raw", + &format_args!("{}", self.out_eof_ch4_int_raw().bit()), + ) + .field( + "out_dscr_err_ch4_int_raw", + &format_args!("{}", self.out_dscr_err_ch4_int_raw().bit()), + ) + .field( + "out_total_eof_ch4_int_raw", + &format_args!("{}", self.out_total_eof_ch4_int_raw().bit()), + ) + .field( + "outfifo_ovf_l1_ch4_int_raw", + &format_args!("{}", self.outfifo_ovf_l1_ch4_int_raw().bit()), + ) + .field( + "outfifo_udf_l1_ch4_int_raw", + &format_args!("{}", self.outfifo_udf_l1_ch4_int_raw().bit()), + ) + .field( + "outfifo_ovf_l2_ch4_int_raw", + &format_args!("{}", self.outfifo_ovf_l2_ch4_int_raw().bit()), + ) + .field( + "outfifo_udf_l2_ch4_int_raw", + &format_args!("{}", self.outfifo_udf_l2_ch4_int_raw().bit()), + ) + .field( + "out_dscr_task_ovf_ch4_int_raw", + &format_args!("{}", self.out_dscr_task_ovf_ch4_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_done_ch4_int_raw(&mut self) -> OUT_DONE_CH4_INT_RAW_W { + OUT_DONE_CH4_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_eof_ch4_int_raw(&mut self) -> OUT_EOF_CH4_INT_RAW_W { + OUT_EOF_CH4_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_dscr_err_ch4_int_raw(&mut self) -> OUT_DSCR_ERR_CH4_INT_RAW_W { + OUT_DSCR_ERR_CH4_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."] + #[inline(always)] + #[must_use] + pub fn out_total_eof_ch4_int_raw( + &mut self, + ) -> OUT_TOTAL_EOF_CH4_INT_RAW_W { + OUT_TOTAL_EOF_CH4_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l1_ch4_int_raw( + &mut self, + ) -> OUTFIFO_OVF_L1_CH4_INT_RAW_W { + OUTFIFO_OVF_L1_CH4_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l1_ch4_int_raw( + &mut self, + ) -> OUTFIFO_UDF_L1_CH4_INT_RAW_W { + OUTFIFO_UDF_L1_CH4_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_ovf_l2_ch4_int_raw( + &mut self, + ) -> OUTFIFO_OVF_L2_CH4_INT_RAW_W { + OUTFIFO_OVF_L2_CH4_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when fifo is underflow."] + #[inline(always)] + #[must_use] + pub fn outfifo_udf_l2_ch4_int_raw( + &mut self, + ) -> OUTFIFO_UDF_L2_CH4_INT_RAW_W { + OUTFIFO_UDF_L2_CH4_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when dscr ready task fifo is overflow."] + #[inline(always)] + #[must_use] + pub fn out_dscr_task_ovf_ch4_int_raw( + &mut self, + ) -> OUT_DSCR_TASK_OVF_CH4_INT_RAW_W { + OUT_DSCR_TASK_OVF_CH4_INT_RAW_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH4 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_raw_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_int_raw_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_RAW_CH4_SPEC; +impl crate::RegisterSpec for OUT_INT_RAW_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_raw_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_INT_RAW_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_int_raw_ch4::W`](W) writer structure"] +impl crate::Writable for OUT_INT_RAW_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_INT_RAW_CH4 to value 0"] +impl crate::Resettable for OUT_INT_RAW_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_st_ch0.rs b/esp32p4/src/h264_dma/out_int_st_ch0.rs new file mode 100644 index 0000000000..86cdd200a8 --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_st_ch0.rs @@ -0,0 +1,127 @@ +#[doc = "Register `OUT_INT_ST_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_DONE_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH0_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH0_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH0_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH0_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH0_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH0_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch0_int_st(&self) -> OUT_DONE_CH0_INT_ST_R { + OUT_DONE_CH0_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch0_int_st(&self) -> OUT_EOF_CH0_INT_ST_R { + OUT_EOF_CH0_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch0_int_st(&self) -> OUT_DSCR_ERR_CH0_INT_ST_R { + OUT_DSCR_ERR_CH0_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch0_int_st(&self) -> OUT_TOTAL_EOF_CH0_INT_ST_R { + OUT_TOTAL_EOF_CH0_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch0_int_st(&self) -> OUTFIFO_OVF_L1_CH0_INT_ST_R { + OUTFIFO_OVF_L1_CH0_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l1_ch0_int_st(&self) -> OUTFIFO_UDF_L1_CH0_INT_ST_R { + OUTFIFO_UDF_L1_CH0_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch0_int_st(&self) -> OUTFIFO_OVF_L2_CH0_INT_ST_R { + OUTFIFO_OVF_L2_CH0_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l2_ch0_int_st(&self) -> OUTFIFO_UDF_L2_CH0_INT_ST_R { + OUTFIFO_UDF_L2_CH0_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch0_int_st(&self) -> OUT_DSCR_TASK_OVF_CH0_INT_ST_R { + OUT_DSCR_TASK_OVF_CH0_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ST_CH0") + .field( + "out_done_ch0_int_st", + &format_args!("{}", self.out_done_ch0_int_st().bit()), + ) + .field( + "out_eof_ch0_int_st", + &format_args!("{}", self.out_eof_ch0_int_st().bit()), + ) + .field( + "out_dscr_err_ch0_int_st", + &format_args!("{}", self.out_dscr_err_ch0_int_st().bit()), + ) + .field( + "out_total_eof_ch0_int_st", + &format_args!("{}", self.out_total_eof_ch0_int_st().bit()), + ) + .field( + "outfifo_ovf_l1_ch0_int_st", + &format_args!("{}", self.outfifo_ovf_l1_ch0_int_st().bit()), + ) + .field( + "outfifo_udf_l1_ch0_int_st", + &format_args!("{}", self.outfifo_udf_l1_ch0_int_st().bit()), + ) + .field( + "outfifo_ovf_l2_ch0_int_st", + &format_args!("{}", self.outfifo_ovf_l2_ch0_int_st().bit()), + ) + .field( + "outfifo_udf_l2_ch0_int_st", + &format_args!("{}", self.outfifo_udf_l2_ch0_int_st().bit()), + ) + .field( + "out_dscr_task_ovf_ch0_int_st", + &format_args!("{}", self.out_dscr_task_ovf_ch0_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH0 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ST_CH0_SPEC; +impl crate::RegisterSpec for OUT_INT_ST_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_st_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ST_CH0_SPEC {} +#[doc = "`reset()` method sets OUT_INT_ST_CH0 to value 0"] +impl crate::Resettable for OUT_INT_ST_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_st_ch1.rs b/esp32p4/src/h264_dma/out_int_st_ch1.rs new file mode 100644 index 0000000000..c4fedb08e9 --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_st_ch1.rs @@ -0,0 +1,127 @@ +#[doc = "Register `OUT_INT_ST_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_DONE_CH1_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH1_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH1_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH1_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH1_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH1_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH1_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH1_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH1_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH1_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch1_int_st(&self) -> OUT_DONE_CH1_INT_ST_R { + OUT_DONE_CH1_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch1_int_st(&self) -> OUT_EOF_CH1_INT_ST_R { + OUT_EOF_CH1_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch1_int_st(&self) -> OUT_DSCR_ERR_CH1_INT_ST_R { + OUT_DSCR_ERR_CH1_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch1_int_st(&self) -> OUT_TOTAL_EOF_CH1_INT_ST_R { + OUT_TOTAL_EOF_CH1_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch1_int_st(&self) -> OUTFIFO_OVF_L1_CH1_INT_ST_R { + OUTFIFO_OVF_L1_CH1_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l1_ch1_int_st(&self) -> OUTFIFO_UDF_L1_CH1_INT_ST_R { + OUTFIFO_UDF_L1_CH1_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch1_int_st(&self) -> OUTFIFO_OVF_L2_CH1_INT_ST_R { + OUTFIFO_OVF_L2_CH1_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l2_ch1_int_st(&self) -> OUTFIFO_UDF_L2_CH1_INT_ST_R { + OUTFIFO_UDF_L2_CH1_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch1_int_st(&self) -> OUT_DSCR_TASK_OVF_CH1_INT_ST_R { + OUT_DSCR_TASK_OVF_CH1_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ST_CH1") + .field( + "out_done_ch1_int_st", + &format_args!("{}", self.out_done_ch1_int_st().bit()), + ) + .field( + "out_eof_ch1_int_st", + &format_args!("{}", self.out_eof_ch1_int_st().bit()), + ) + .field( + "out_dscr_err_ch1_int_st", + &format_args!("{}", self.out_dscr_err_ch1_int_st().bit()), + ) + .field( + "out_total_eof_ch1_int_st", + &format_args!("{}", self.out_total_eof_ch1_int_st().bit()), + ) + .field( + "outfifo_ovf_l1_ch1_int_st", + &format_args!("{}", self.outfifo_ovf_l1_ch1_int_st().bit()), + ) + .field( + "outfifo_udf_l1_ch1_int_st", + &format_args!("{}", self.outfifo_udf_l1_ch1_int_st().bit()), + ) + .field( + "outfifo_ovf_l2_ch1_int_st", + &format_args!("{}", self.outfifo_ovf_l2_ch1_int_st().bit()), + ) + .field( + "outfifo_udf_l2_ch1_int_st", + &format_args!("{}", self.outfifo_udf_l2_ch1_int_st().bit()), + ) + .field( + "out_dscr_task_ovf_ch1_int_st", + &format_args!("{}", self.out_dscr_task_ovf_ch1_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH1 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ST_CH1_SPEC; +impl crate::RegisterSpec for OUT_INT_ST_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_st_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ST_CH1_SPEC {} +#[doc = "`reset()` method sets OUT_INT_ST_CH1 to value 0"] +impl crate::Resettable for OUT_INT_ST_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_st_ch2.rs b/esp32p4/src/h264_dma/out_int_st_ch2.rs new file mode 100644 index 0000000000..3bfebf9ee2 --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_st_ch2.rs @@ -0,0 +1,127 @@ +#[doc = "Register `OUT_INT_ST_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_DONE_CH2_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH2_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH2_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH2_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH2_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH2_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH2_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH2_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH2_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH2_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch2_int_st(&self) -> OUT_DONE_CH2_INT_ST_R { + OUT_DONE_CH2_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch2_int_st(&self) -> OUT_EOF_CH2_INT_ST_R { + OUT_EOF_CH2_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch2_int_st(&self) -> OUT_DSCR_ERR_CH2_INT_ST_R { + OUT_DSCR_ERR_CH2_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch2_int_st(&self) -> OUT_TOTAL_EOF_CH2_INT_ST_R { + OUT_TOTAL_EOF_CH2_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch2_int_st(&self) -> OUTFIFO_OVF_L1_CH2_INT_ST_R { + OUTFIFO_OVF_L1_CH2_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l1_ch2_int_st(&self) -> OUTFIFO_UDF_L1_CH2_INT_ST_R { + OUTFIFO_UDF_L1_CH2_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch2_int_st(&self) -> OUTFIFO_OVF_L2_CH2_INT_ST_R { + OUTFIFO_OVF_L2_CH2_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l2_ch2_int_st(&self) -> OUTFIFO_UDF_L2_CH2_INT_ST_R { + OUTFIFO_UDF_L2_CH2_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch2_int_st(&self) -> OUT_DSCR_TASK_OVF_CH2_INT_ST_R { + OUT_DSCR_TASK_OVF_CH2_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ST_CH2") + .field( + "out_done_ch2_int_st", + &format_args!("{}", self.out_done_ch2_int_st().bit()), + ) + .field( + "out_eof_ch2_int_st", + &format_args!("{}", self.out_eof_ch2_int_st().bit()), + ) + .field( + "out_dscr_err_ch2_int_st", + &format_args!("{}", self.out_dscr_err_ch2_int_st().bit()), + ) + .field( + "out_total_eof_ch2_int_st", + &format_args!("{}", self.out_total_eof_ch2_int_st().bit()), + ) + .field( + "outfifo_ovf_l1_ch2_int_st", + &format_args!("{}", self.outfifo_ovf_l1_ch2_int_st().bit()), + ) + .field( + "outfifo_udf_l1_ch2_int_st", + &format_args!("{}", self.outfifo_udf_l1_ch2_int_st().bit()), + ) + .field( + "outfifo_ovf_l2_ch2_int_st", + &format_args!("{}", self.outfifo_ovf_l2_ch2_int_st().bit()), + ) + .field( + "outfifo_udf_l2_ch2_int_st", + &format_args!("{}", self.outfifo_udf_l2_ch2_int_st().bit()), + ) + .field( + "out_dscr_task_ovf_ch2_int_st", + &format_args!("{}", self.out_dscr_task_ovf_ch2_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH2 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ST_CH2_SPEC; +impl crate::RegisterSpec for OUT_INT_ST_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_st_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ST_CH2_SPEC {} +#[doc = "`reset()` method sets OUT_INT_ST_CH2 to value 0"] +impl crate::Resettable for OUT_INT_ST_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_st_ch3.rs b/esp32p4/src/h264_dma/out_int_st_ch3.rs new file mode 100644 index 0000000000..9e9b9a189b --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_st_ch3.rs @@ -0,0 +1,127 @@ +#[doc = "Register `OUT_INT_ST_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_DONE_CH3_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH3_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH3_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH3_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH3_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH3_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH3_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH3_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH3_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH3_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch3_int_st(&self) -> OUT_DONE_CH3_INT_ST_R { + OUT_DONE_CH3_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch3_int_st(&self) -> OUT_EOF_CH3_INT_ST_R { + OUT_EOF_CH3_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch3_int_st(&self) -> OUT_DSCR_ERR_CH3_INT_ST_R { + OUT_DSCR_ERR_CH3_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch3_int_st(&self) -> OUT_TOTAL_EOF_CH3_INT_ST_R { + OUT_TOTAL_EOF_CH3_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch3_int_st(&self) -> OUTFIFO_OVF_L1_CH3_INT_ST_R { + OUTFIFO_OVF_L1_CH3_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l1_ch3_int_st(&self) -> OUTFIFO_UDF_L1_CH3_INT_ST_R { + OUTFIFO_UDF_L1_CH3_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch3_int_st(&self) -> OUTFIFO_OVF_L2_CH3_INT_ST_R { + OUTFIFO_OVF_L2_CH3_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l2_ch3_int_st(&self) -> OUTFIFO_UDF_L2_CH3_INT_ST_R { + OUTFIFO_UDF_L2_CH3_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch3_int_st(&self) -> OUT_DSCR_TASK_OVF_CH3_INT_ST_R { + OUT_DSCR_TASK_OVF_CH3_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ST_CH3") + .field( + "out_done_ch3_int_st", + &format_args!("{}", self.out_done_ch3_int_st().bit()), + ) + .field( + "out_eof_ch3_int_st", + &format_args!("{}", self.out_eof_ch3_int_st().bit()), + ) + .field( + "out_dscr_err_ch3_int_st", + &format_args!("{}", self.out_dscr_err_ch3_int_st().bit()), + ) + .field( + "out_total_eof_ch3_int_st", + &format_args!("{}", self.out_total_eof_ch3_int_st().bit()), + ) + .field( + "outfifo_ovf_l1_ch3_int_st", + &format_args!("{}", self.outfifo_ovf_l1_ch3_int_st().bit()), + ) + .field( + "outfifo_udf_l1_ch3_int_st", + &format_args!("{}", self.outfifo_udf_l1_ch3_int_st().bit()), + ) + .field( + "outfifo_ovf_l2_ch3_int_st", + &format_args!("{}", self.outfifo_ovf_l2_ch3_int_st().bit()), + ) + .field( + "outfifo_udf_l2_ch3_int_st", + &format_args!("{}", self.outfifo_udf_l2_ch3_int_st().bit()), + ) + .field( + "out_dscr_task_ovf_ch3_int_st", + &format_args!("{}", self.out_dscr_task_ovf_ch3_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH3 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ST_CH3_SPEC; +impl crate::RegisterSpec for OUT_INT_ST_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_st_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ST_CH3_SPEC {} +#[doc = "`reset()` method sets OUT_INT_ST_CH3 to value 0"] +impl crate::Resettable for OUT_INT_ST_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_int_st_ch4.rs b/esp32p4/src/h264_dma/out_int_st_ch4.rs new file mode 100644 index 0000000000..f0eddd70ce --- /dev/null +++ b/esp32p4/src/h264_dma/out_int_st_ch4.rs @@ -0,0 +1,127 @@ +#[doc = "Register `OUT_INT_ST_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_DONE_CH4_INT_ST` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] +pub type OUT_DONE_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_EOF_CH4_INT_ST` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] +pub type OUT_EOF_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_ERR_CH4_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] +pub type OUT_DSCR_ERR_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_TOTAL_EOF_CH4_INT_ST` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] +pub type OUT_TOTAL_EOF_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L1_CH4_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] +pub type OUTFIFO_OVF_L1_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L1_CH4_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] +pub type OUTFIFO_UDF_L1_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_OVF_L2_CH4_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] +pub type OUTFIFO_OVF_L2_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTFIFO_UDF_L2_CH4_INT_ST` reader - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] +pub type OUTFIFO_UDF_L2_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_DSCR_TASK_OVF_CH4_INT_ST` reader - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] +pub type OUT_DSCR_TASK_OVF_CH4_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."] + #[inline(always)] + pub fn out_done_ch4_int_st(&self) -> OUT_DONE_CH4_INT_ST_R { + OUT_DONE_CH4_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_eof_ch4_int_st(&self) -> OUT_EOF_CH4_INT_ST_R { + OUT_EOF_CH4_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_err_ch4_int_st(&self) -> OUT_DSCR_ERR_CH4_INT_ST_R { + OUT_DSCR_ERR_CH4_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."] + #[inline(always)] + pub fn out_total_eof_ch4_int_st(&self) -> OUT_TOTAL_EOF_CH4_INT_ST_R { + OUT_TOTAL_EOF_CH4_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l1_ch4_int_st(&self) -> OUTFIFO_OVF_L1_CH4_INT_ST_R { + OUTFIFO_OVF_L1_CH4_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l1_ch4_int_st(&self) -> OUTFIFO_UDF_L1_CH4_INT_ST_R { + OUTFIFO_UDF_L1_CH4_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_ovf_l2_ch4_int_st(&self) -> OUTFIFO_OVF_L2_CH4_INT_ST_R { + OUTFIFO_OVF_L2_CH4_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt."] + #[inline(always)] + pub fn outfifo_udf_l2_ch4_int_st(&self) -> OUTFIFO_UDF_L2_CH4_INT_ST_R { + OUTFIFO_UDF_L2_CH4_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt."] + #[inline(always)] + pub fn out_dscr_task_ovf_ch4_int_st(&self) -> OUT_DSCR_TASK_OVF_CH4_INT_ST_R { + OUT_DSCR_TASK_OVF_CH4_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_INT_ST_CH4") + .field( + "out_done_ch4_int_st", + &format_args!("{}", self.out_done_ch4_int_st().bit()), + ) + .field( + "out_eof_ch4_int_st", + &format_args!("{}", self.out_eof_ch4_int_st().bit()), + ) + .field( + "out_dscr_err_ch4_int_st", + &format_args!("{}", self.out_dscr_err_ch4_int_st().bit()), + ) + .field( + "out_total_eof_ch4_int_st", + &format_args!("{}", self.out_total_eof_ch4_int_st().bit()), + ) + .field( + "outfifo_ovf_l1_ch4_int_st", + &format_args!("{}", self.outfifo_ovf_l1_ch4_int_st().bit()), + ) + .field( + "outfifo_udf_l1_ch4_int_st", + &format_args!("{}", self.outfifo_udf_l1_ch4_int_st().bit()), + ) + .field( + "outfifo_ovf_l2_ch4_int_st", + &format_args!("{}", self.outfifo_ovf_l2_ch4_int_st().bit()), + ) + .field( + "outfifo_udf_l2_ch4_int_st", + &format_args!("{}", self.outfifo_udf_l2_ch4_int_st().bit()), + ) + .field( + "out_dscr_task_ovf_ch4_int_st", + &format_args!("{}", self.out_dscr_task_ovf_ch4_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH4 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_int_st_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_INT_ST_CH4_SPEC; +impl crate::RegisterSpec for OUT_INT_ST_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_int_st_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_INT_ST_CH4_SPEC {} +#[doc = "`reset()` method sets OUT_INT_ST_CH4 to value 0"] +impl crate::Resettable for OUT_INT_ST_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_link_addr_ch0.rs b/esp32p4/src/h264_dma/out_link_addr_ch0.rs new file mode 100644 index 0000000000..570141ddb9 --- /dev/null +++ b/esp32p4/src/h264_dma/out_link_addr_ch0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_LINK_ADDR_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_ADDR_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_ADDR_CH0` reader - This register stores the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR_CH0` writer - This register stores the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the first outlink descriptor's address."] + #[inline(always)] + pub fn outlink_addr_ch0(&self) -> OUTLINK_ADDR_CH0_R { + OUTLINK_ADDR_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_ADDR_CH0") + .field( + "outlink_addr_ch0", + &format_args!("{}", self.outlink_addr_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the first outlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn outlink_addr_ch0(&mut self) -> OUTLINK_ADDR_CH0_W { + OUTLINK_ADDR_CH0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH0 out_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_ADDR_CH0_SPEC; +impl crate::RegisterSpec for OUT_LINK_ADDR_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_addr_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_ADDR_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_addr_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_ADDR_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_ADDR_CH0 to value 0"] +impl crate::Resettable for OUT_LINK_ADDR_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_link_addr_ch1.rs b/esp32p4/src/h264_dma/out_link_addr_ch1.rs new file mode 100644 index 0000000000..c75ed6e291 --- /dev/null +++ b/esp32p4/src/h264_dma/out_link_addr_ch1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_LINK_ADDR_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_ADDR_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_ADDR_CH1` reader - This register stores the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH1_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR_CH1` writer - This register stores the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the first outlink descriptor's address."] + #[inline(always)] + pub fn outlink_addr_ch1(&self) -> OUTLINK_ADDR_CH1_R { + OUTLINK_ADDR_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_ADDR_CH1") + .field( + "outlink_addr_ch1", + &format_args!("{}", self.outlink_addr_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the first outlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn outlink_addr_ch1(&mut self) -> OUTLINK_ADDR_CH1_W { + OUTLINK_ADDR_CH1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH1 out_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_ADDR_CH1_SPEC; +impl crate::RegisterSpec for OUT_LINK_ADDR_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_addr_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_ADDR_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_addr_ch1::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_ADDR_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_ADDR_CH1 to value 0"] +impl crate::Resettable for OUT_LINK_ADDR_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_link_addr_ch2.rs b/esp32p4/src/h264_dma/out_link_addr_ch2.rs new file mode 100644 index 0000000000..41b31570e6 --- /dev/null +++ b/esp32p4/src/h264_dma/out_link_addr_ch2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_LINK_ADDR_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_ADDR_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_ADDR_CH2` reader - This register stores the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH2_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR_CH2` writer - This register stores the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the first outlink descriptor's address."] + #[inline(always)] + pub fn outlink_addr_ch2(&self) -> OUTLINK_ADDR_CH2_R { + OUTLINK_ADDR_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_ADDR_CH2") + .field( + "outlink_addr_ch2", + &format_args!("{}", self.outlink_addr_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the first outlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn outlink_addr_ch2(&mut self) -> OUTLINK_ADDR_CH2_W { + OUTLINK_ADDR_CH2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH2 out_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_ADDR_CH2_SPEC; +impl crate::RegisterSpec for OUT_LINK_ADDR_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_addr_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_ADDR_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_addr_ch2::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_ADDR_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_ADDR_CH2 to value 0"] +impl crate::Resettable for OUT_LINK_ADDR_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_link_addr_ch3.rs b/esp32p4/src/h264_dma/out_link_addr_ch3.rs new file mode 100644 index 0000000000..03fe81081b --- /dev/null +++ b/esp32p4/src/h264_dma/out_link_addr_ch3.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_LINK_ADDR_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_ADDR_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_ADDR_CH3` reader - This register stores the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH3_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR_CH3` writer - This register stores the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the first outlink descriptor's address."] + #[inline(always)] + pub fn outlink_addr_ch3(&self) -> OUTLINK_ADDR_CH3_R { + OUTLINK_ADDR_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_ADDR_CH3") + .field( + "outlink_addr_ch3", + &format_args!("{}", self.outlink_addr_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the first outlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn outlink_addr_ch3(&mut self) -> OUTLINK_ADDR_CH3_W { + OUTLINK_ADDR_CH3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH3 out_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_ADDR_CH3_SPEC; +impl crate::RegisterSpec for OUT_LINK_ADDR_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_addr_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_ADDR_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_addr_ch3::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_ADDR_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_ADDR_CH3 to value 0"] +impl crate::Resettable for OUT_LINK_ADDR_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_link_addr_ch4.rs b/esp32p4/src/h264_dma/out_link_addr_ch4.rs new file mode 100644 index 0000000000..12cfc98844 --- /dev/null +++ b/esp32p4/src/h264_dma/out_link_addr_ch4.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT_LINK_ADDR_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_ADDR_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_ADDR_CH4` reader - This register stores the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH4_R = crate::FieldReader; +#[doc = "Field `OUTLINK_ADDR_CH4` writer - This register stores the first outlink descriptor's address."] +pub type OUTLINK_ADDR_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register stores the first outlink descriptor's address."] + #[inline(always)] + pub fn outlink_addr_ch4(&self) -> OUTLINK_ADDR_CH4_R { + OUTLINK_ADDR_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_ADDR_CH4") + .field( + "outlink_addr_ch4", + &format_args!("{}", self.outlink_addr_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register stores the first outlink descriptor's address."] + #[inline(always)] + #[must_use] + pub fn outlink_addr_ch4(&mut self) -> OUTLINK_ADDR_CH4_W { + OUTLINK_ADDR_CH4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH4 out_link dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_addr_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_addr_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_ADDR_CH4_SPEC; +impl crate::RegisterSpec for OUT_LINK_ADDR_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_addr_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_ADDR_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_addr_ch4::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_ADDR_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_ADDR_CH4 to value 0"] +impl crate::Resettable for OUT_LINK_ADDR_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_link_conf_ch0.rs b/esp32p4/src/h264_dma/out_link_conf_ch0.rs new file mode 100644 index 0000000000..3136e09d4b --- /dev/null +++ b/esp32p4/src/h264_dma/out_link_conf_ch0.rs @@ -0,0 +1,115 @@ +#[doc = "Register `OUT_LINK_CONF_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_CONF_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_STOP_CH0` reader - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH0_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP_CH0` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_START_CH0` reader - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH0_R = crate::BitReader; +#[doc = "Field `OUTLINK_START_CH0` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_RESTART_CH0` reader - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH0_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART_CH0` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_PARK_CH0` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_CH0_R = crate::BitReader; +impl R { + #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + pub fn outlink_stop_ch0(&self) -> OUTLINK_STOP_CH0_R { + OUTLINK_STOP_CH0_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + pub fn outlink_start_ch0(&self) -> OUTLINK_START_CH0_R { + OUTLINK_START_CH0_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + pub fn outlink_restart_ch0(&self) -> OUTLINK_RESTART_CH0_R { + OUTLINK_RESTART_CH0_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] + #[inline(always)] + pub fn outlink_park_ch0(&self) -> OUTLINK_PARK_CH0_R { + OUTLINK_PARK_CH0_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_CONF_CH0") + .field( + "outlink_stop_ch0", + &format_args!("{}", self.outlink_stop_ch0().bit()), + ) + .field( + "outlink_start_ch0", + &format_args!("{}", self.outlink_start_ch0().bit()), + ) + .field( + "outlink_restart_ch0", + &format_args!("{}", self.outlink_restart_ch0().bit()), + ) + .field( + "outlink_park_ch0", + &format_args!("{}", self.outlink_park_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_stop_ch0(&mut self) -> OUTLINK_STOP_CH0_W { + OUTLINK_STOP_CH0_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_start_ch0(&mut self) -> OUTLINK_START_CH0_W { + OUTLINK_START_CH0_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + #[must_use] + pub fn outlink_restart_ch0(&mut self) -> OUTLINK_RESTART_CH0_W { + OUTLINK_RESTART_CH0_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH0 out_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_conf_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_conf_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_CONF_CH0_SPEC; +impl crate::RegisterSpec for OUT_LINK_CONF_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_conf_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_CONF_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_conf_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_CONF_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_CONF_CH0 to value 0x0080_0000"] +impl crate::Resettable for OUT_LINK_CONF_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_0000; +} diff --git a/esp32p4/src/h264_dma/out_link_conf_ch1.rs b/esp32p4/src/h264_dma/out_link_conf_ch1.rs new file mode 100644 index 0000000000..5432f8a927 --- /dev/null +++ b/esp32p4/src/h264_dma/out_link_conf_ch1.rs @@ -0,0 +1,115 @@ +#[doc = "Register `OUT_LINK_CONF_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_CONF_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_STOP_CH1` reader - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH1_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP_CH1` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_START_CH1` reader - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH1_R = crate::BitReader; +#[doc = "Field `OUTLINK_START_CH1` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_RESTART_CH1` reader - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH1_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART_CH1` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_PARK_CH1` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_CH1_R = crate::BitReader; +impl R { + #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + pub fn outlink_stop_ch1(&self) -> OUTLINK_STOP_CH1_R { + OUTLINK_STOP_CH1_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + pub fn outlink_start_ch1(&self) -> OUTLINK_START_CH1_R { + OUTLINK_START_CH1_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + pub fn outlink_restart_ch1(&self) -> OUTLINK_RESTART_CH1_R { + OUTLINK_RESTART_CH1_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] + #[inline(always)] + pub fn outlink_park_ch1(&self) -> OUTLINK_PARK_CH1_R { + OUTLINK_PARK_CH1_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_CONF_CH1") + .field( + "outlink_stop_ch1", + &format_args!("{}", self.outlink_stop_ch1().bit()), + ) + .field( + "outlink_start_ch1", + &format_args!("{}", self.outlink_start_ch1().bit()), + ) + .field( + "outlink_restart_ch1", + &format_args!("{}", self.outlink_restart_ch1().bit()), + ) + .field( + "outlink_park_ch1", + &format_args!("{}", self.outlink_park_ch1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_stop_ch1(&mut self) -> OUTLINK_STOP_CH1_W { + OUTLINK_STOP_CH1_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_start_ch1(&mut self) -> OUTLINK_START_CH1_W { + OUTLINK_START_CH1_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + #[must_use] + pub fn outlink_restart_ch1(&mut self) -> OUTLINK_RESTART_CH1_W { + OUTLINK_RESTART_CH1_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH1 out_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_conf_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_conf_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_CONF_CH1_SPEC; +impl crate::RegisterSpec for OUT_LINK_CONF_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_conf_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_CONF_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_conf_ch1::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_CONF_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_CONF_CH1 to value 0x0080_0000"] +impl crate::Resettable for OUT_LINK_CONF_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_0000; +} diff --git a/esp32p4/src/h264_dma/out_link_conf_ch2.rs b/esp32p4/src/h264_dma/out_link_conf_ch2.rs new file mode 100644 index 0000000000..e4f674fa81 --- /dev/null +++ b/esp32p4/src/h264_dma/out_link_conf_ch2.rs @@ -0,0 +1,115 @@ +#[doc = "Register `OUT_LINK_CONF_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_CONF_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_STOP_CH2` reader - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH2_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP_CH2` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_START_CH2` reader - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH2_R = crate::BitReader; +#[doc = "Field `OUTLINK_START_CH2` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_RESTART_CH2` reader - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH2_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART_CH2` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_PARK_CH2` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_CH2_R = crate::BitReader; +impl R { + #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + pub fn outlink_stop_ch2(&self) -> OUTLINK_STOP_CH2_R { + OUTLINK_STOP_CH2_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + pub fn outlink_start_ch2(&self) -> OUTLINK_START_CH2_R { + OUTLINK_START_CH2_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + pub fn outlink_restart_ch2(&self) -> OUTLINK_RESTART_CH2_R { + OUTLINK_RESTART_CH2_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] + #[inline(always)] + pub fn outlink_park_ch2(&self) -> OUTLINK_PARK_CH2_R { + OUTLINK_PARK_CH2_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_CONF_CH2") + .field( + "outlink_stop_ch2", + &format_args!("{}", self.outlink_stop_ch2().bit()), + ) + .field( + "outlink_start_ch2", + &format_args!("{}", self.outlink_start_ch2().bit()), + ) + .field( + "outlink_restart_ch2", + &format_args!("{}", self.outlink_restart_ch2().bit()), + ) + .field( + "outlink_park_ch2", + &format_args!("{}", self.outlink_park_ch2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_stop_ch2(&mut self) -> OUTLINK_STOP_CH2_W { + OUTLINK_STOP_CH2_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_start_ch2(&mut self) -> OUTLINK_START_CH2_W { + OUTLINK_START_CH2_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + #[must_use] + pub fn outlink_restart_ch2(&mut self) -> OUTLINK_RESTART_CH2_W { + OUTLINK_RESTART_CH2_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH2 out_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_conf_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_conf_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_CONF_CH2_SPEC; +impl crate::RegisterSpec for OUT_LINK_CONF_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_conf_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_CONF_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_conf_ch2::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_CONF_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_CONF_CH2 to value 0x0080_0000"] +impl crate::Resettable for OUT_LINK_CONF_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_0000; +} diff --git a/esp32p4/src/h264_dma/out_link_conf_ch3.rs b/esp32p4/src/h264_dma/out_link_conf_ch3.rs new file mode 100644 index 0000000000..5f6898479b --- /dev/null +++ b/esp32p4/src/h264_dma/out_link_conf_ch3.rs @@ -0,0 +1,115 @@ +#[doc = "Register `OUT_LINK_CONF_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_CONF_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_STOP_CH3` reader - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH3_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP_CH3` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_START_CH3` reader - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH3_R = crate::BitReader; +#[doc = "Field `OUTLINK_START_CH3` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_RESTART_CH3` reader - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH3_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART_CH3` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_PARK_CH3` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_CH3_R = crate::BitReader; +impl R { + #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + pub fn outlink_stop_ch3(&self) -> OUTLINK_STOP_CH3_R { + OUTLINK_STOP_CH3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + pub fn outlink_start_ch3(&self) -> OUTLINK_START_CH3_R { + OUTLINK_START_CH3_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + pub fn outlink_restart_ch3(&self) -> OUTLINK_RESTART_CH3_R { + OUTLINK_RESTART_CH3_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] + #[inline(always)] + pub fn outlink_park_ch3(&self) -> OUTLINK_PARK_CH3_R { + OUTLINK_PARK_CH3_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_CONF_CH3") + .field( + "outlink_stop_ch3", + &format_args!("{}", self.outlink_stop_ch3().bit()), + ) + .field( + "outlink_start_ch3", + &format_args!("{}", self.outlink_start_ch3().bit()), + ) + .field( + "outlink_restart_ch3", + &format_args!("{}", self.outlink_restart_ch3().bit()), + ) + .field( + "outlink_park_ch3", + &format_args!("{}", self.outlink_park_ch3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_stop_ch3(&mut self) -> OUTLINK_STOP_CH3_W { + OUTLINK_STOP_CH3_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_start_ch3(&mut self) -> OUTLINK_START_CH3_W { + OUTLINK_START_CH3_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + #[must_use] + pub fn outlink_restart_ch3(&mut self) -> OUTLINK_RESTART_CH3_W { + OUTLINK_RESTART_CH3_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH3 out_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_conf_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_conf_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_CONF_CH3_SPEC; +impl crate::RegisterSpec for OUT_LINK_CONF_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_conf_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_CONF_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_conf_ch3::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_CONF_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_CONF_CH3 to value 0x0080_0000"] +impl crate::Resettable for OUT_LINK_CONF_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_0000; +} diff --git a/esp32p4/src/h264_dma/out_link_conf_ch4.rs b/esp32p4/src/h264_dma/out_link_conf_ch4.rs new file mode 100644 index 0000000000..830a375eb4 --- /dev/null +++ b/esp32p4/src/h264_dma/out_link_conf_ch4.rs @@ -0,0 +1,115 @@ +#[doc = "Register `OUT_LINK_CONF_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_LINK_CONF_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `OUTLINK_STOP_CH4` reader - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH4_R = crate::BitReader; +#[doc = "Field `OUTLINK_STOP_CH4` writer - Set this bit to stop dealing with the outlink descriptors."] +pub type OUTLINK_STOP_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_START_CH4` reader - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH4_R = crate::BitReader; +#[doc = "Field `OUTLINK_START_CH4` writer - Set this bit to start dealing with the outlink descriptors."] +pub type OUTLINK_START_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_RESTART_CH4` reader - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH4_R = crate::BitReader; +#[doc = "Field `OUTLINK_RESTART_CH4` writer - Set this bit to restart a new outlink from the last address."] +pub type OUTLINK_RESTART_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_PARK_CH4` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] +pub type OUTLINK_PARK_CH4_R = crate::BitReader; +impl R { + #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + pub fn outlink_stop_ch4(&self) -> OUTLINK_STOP_CH4_R { + OUTLINK_STOP_CH4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + pub fn outlink_start_ch4(&self) -> OUTLINK_START_CH4_R { + OUTLINK_START_CH4_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + pub fn outlink_restart_ch4(&self) -> OUTLINK_RESTART_CH4_R { + OUTLINK_RESTART_CH4_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."] + #[inline(always)] + pub fn outlink_park_ch4(&self) -> OUTLINK_PARK_CH4_R { + OUTLINK_PARK_CH4_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_LINK_CONF_CH4") + .field( + "outlink_stop_ch4", + &format_args!("{}", self.outlink_stop_ch4().bit()), + ) + .field( + "outlink_start_ch4", + &format_args!("{}", self.outlink_start_ch4().bit()), + ) + .field( + "outlink_restart_ch4", + &format_args!("{}", self.outlink_restart_ch4().bit()), + ) + .field( + "outlink_park_ch4", + &format_args!("{}", self.outlink_park_ch4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_stop_ch4(&mut self) -> OUTLINK_STOP_CH4_W { + OUTLINK_STOP_CH4_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."] + #[inline(always)] + #[must_use] + pub fn outlink_start_ch4(&mut self) -> OUTLINK_START_CH4_W { + OUTLINK_START_CH4_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."] + #[inline(always)] + #[must_use] + pub fn outlink_restart_ch4(&mut self) -> OUTLINK_RESTART_CH4_W { + OUTLINK_RESTART_CH4_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH4 out_link dscr ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_link_conf_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_link_conf_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_LINK_CONF_CH4_SPEC; +impl crate::RegisterSpec for OUT_LINK_CONF_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_link_conf_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_LINK_CONF_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_link_conf_ch4::W`](W) writer structure"] +impl crate::Writable for OUT_LINK_CONF_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_LINK_CONF_CH4 to value 0x0080_0000"] +impl crate::Resettable for OUT_LINK_CONF_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_0000; +} diff --git a/esp32p4/src/h264_dma/out_mode_enable_ch0.rs b/esp32p4/src/h264_dma/out_mode_enable_ch0.rs new file mode 100644 index 0000000000..768d87dae4 --- /dev/null +++ b/esp32p4/src/h264_dma/out_mode_enable_ch0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `OUT_MODE_ENABLE_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_MODE_ENABLE_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_TEST_MODE_ENABLE_CH0` reader - tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode"] +pub type OUT_TEST_MODE_ENABLE_CH0_R = crate::BitReader; +#[doc = "Field `OUT_TEST_MODE_ENABLE_CH0` writer - tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode"] +pub type OUT_TEST_MODE_ENABLE_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode"] + #[inline(always)] + pub fn out_test_mode_enable_ch0(&self) -> OUT_TEST_MODE_ENABLE_CH0_R { + OUT_TEST_MODE_ENABLE_CH0_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_MODE_ENABLE_CH0") + .field( + "out_test_mode_enable_ch0", + &format_args!("{}", self.out_test_mode_enable_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode"] + #[inline(always)] + #[must_use] + pub fn out_test_mode_enable_ch0( + &mut self, + ) -> OUT_TEST_MODE_ENABLE_CH0_W { + OUT_TEST_MODE_ENABLE_CH0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "tx CH0 mode enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_mode_enable_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_mode_enable_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_MODE_ENABLE_CH0_SPEC; +impl crate::RegisterSpec for OUT_MODE_ENABLE_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_mode_enable_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_MODE_ENABLE_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_mode_enable_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_MODE_ENABLE_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_MODE_ENABLE_CH0 to value 0"] +impl crate::Resettable for OUT_MODE_ENABLE_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_mode_yuv_ch0.rs b/esp32p4/src/h264_dma/out_mode_yuv_ch0.rs new file mode 100644 index 0000000000..89242db1f7 --- /dev/null +++ b/esp32p4/src/h264_dma/out_mode_yuv_ch0.rs @@ -0,0 +1,104 @@ +#[doc = "Register `OUT_MODE_YUV_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_MODE_YUV_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_TEST_Y_VALUE_CH0` reader - tx CH0 test mode y value"] +pub type OUT_TEST_Y_VALUE_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_TEST_Y_VALUE_CH0` writer - tx CH0 test mode y value"] +pub type OUT_TEST_Y_VALUE_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `OUT_TEST_U_VALUE_CH0` reader - tx CH0 test mode u value"] +pub type OUT_TEST_U_VALUE_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_TEST_U_VALUE_CH0` writer - tx CH0 test mode u value"] +pub type OUT_TEST_U_VALUE_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `OUT_TEST_V_VALUE_CH0` reader - tx CH0 test mode v value"] +pub type OUT_TEST_V_VALUE_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_TEST_V_VALUE_CH0` writer - tx CH0 test mode v value"] +pub type OUT_TEST_V_VALUE_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - tx CH0 test mode y value"] + #[inline(always)] + pub fn out_test_y_value_ch0(&self) -> OUT_TEST_Y_VALUE_CH0_R { + OUT_TEST_Y_VALUE_CH0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - tx CH0 test mode u value"] + #[inline(always)] + pub fn out_test_u_value_ch0(&self) -> OUT_TEST_U_VALUE_CH0_R { + OUT_TEST_U_VALUE_CH0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - tx CH0 test mode v value"] + #[inline(always)] + pub fn out_test_v_value_ch0(&self) -> OUT_TEST_V_VALUE_CH0_R { + OUT_TEST_V_VALUE_CH0_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_MODE_YUV_CH0") + .field( + "out_test_y_value_ch0", + &format_args!("{}", self.out_test_y_value_ch0().bits()), + ) + .field( + "out_test_u_value_ch0", + &format_args!("{}", self.out_test_u_value_ch0().bits()), + ) + .field( + "out_test_v_value_ch0", + &format_args!("{}", self.out_test_v_value_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - tx CH0 test mode y value"] + #[inline(always)] + #[must_use] + pub fn out_test_y_value_ch0(&mut self) -> OUT_TEST_Y_VALUE_CH0_W { + OUT_TEST_Y_VALUE_CH0_W::new(self, 0) + } + #[doc = "Bits 8:15 - tx CH0 test mode u value"] + #[inline(always)] + #[must_use] + pub fn out_test_u_value_ch0(&mut self) -> OUT_TEST_U_VALUE_CH0_W { + OUT_TEST_U_VALUE_CH0_W::new(self, 8) + } + #[doc = "Bits 16:23 - tx CH0 test mode v value"] + #[inline(always)] + #[must_use] + pub fn out_test_v_value_ch0(&mut self) -> OUT_TEST_V_VALUE_CH0_W { + OUT_TEST_V_VALUE_CH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "tx CH0 test mode yuv value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_mode_yuv_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_mode_yuv_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_MODE_YUV_CH0_SPEC; +impl crate::RegisterSpec for OUT_MODE_YUV_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_mode_yuv_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_MODE_YUV_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_mode_yuv_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_MODE_YUV_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_MODE_YUV_CH0 to value 0"] +impl crate::Resettable for OUT_MODE_YUV_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_push_bytecnt_ch0.rs b/esp32p4/src/h264_dma/out_push_bytecnt_ch0.rs new file mode 100644 index 0000000000..e280dece18 --- /dev/null +++ b/esp32p4/src/h264_dma/out_push_bytecnt_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_PUSH_BYTECNT_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_PUSH_BYTECNT_CH0` reader - only for debug"] +pub type OUT_CMDFIFO_PUSH_BYTECNT_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_push_bytecnt_ch0(&self) -> OUT_CMDFIFO_PUSH_BYTECNT_CH0_R { + OUT_CMDFIFO_PUSH_BYTECNT_CH0_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_BYTECNT_CH0") + .field( + "out_cmdfifo_push_bytecnt_ch0", + &format_args!("{}", self.out_cmdfifo_push_bytecnt_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH0 push byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_bytecnt_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_BYTECNT_CH0_SPEC; +impl crate::RegisterSpec for OUT_PUSH_BYTECNT_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_bytecnt_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_BYTECNT_CH0_SPEC {} +#[doc = "`reset()` method sets OUT_PUSH_BYTECNT_CH0 to value 0xff"] +impl crate::Resettable for OUT_PUSH_BYTECNT_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0xff; +} diff --git a/esp32p4/src/h264_dma/out_push_bytecnt_ch1.rs b/esp32p4/src/h264_dma/out_push_bytecnt_ch1.rs new file mode 100644 index 0000000000..b64549ab42 --- /dev/null +++ b/esp32p4/src/h264_dma/out_push_bytecnt_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_PUSH_BYTECNT_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_PUSH_BYTECNT_CH1` reader - only for debug"] +pub type OUT_CMDFIFO_PUSH_BYTECNT_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_push_bytecnt_ch1(&self) -> OUT_CMDFIFO_PUSH_BYTECNT_CH1_R { + OUT_CMDFIFO_PUSH_BYTECNT_CH1_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_BYTECNT_CH1") + .field( + "out_cmdfifo_push_bytecnt_ch1", + &format_args!("{}", self.out_cmdfifo_push_bytecnt_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH1 push byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_bytecnt_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_BYTECNT_CH1_SPEC; +impl crate::RegisterSpec for OUT_PUSH_BYTECNT_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_bytecnt_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_BYTECNT_CH1_SPEC {} +#[doc = "`reset()` method sets OUT_PUSH_BYTECNT_CH1 to value 0xff"] +impl crate::Resettable for OUT_PUSH_BYTECNT_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0xff; +} diff --git a/esp32p4/src/h264_dma/out_push_bytecnt_ch2.rs b/esp32p4/src/h264_dma/out_push_bytecnt_ch2.rs new file mode 100644 index 0000000000..5e39504531 --- /dev/null +++ b/esp32p4/src/h264_dma/out_push_bytecnt_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_PUSH_BYTECNT_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_PUSH_BYTECNT_CH2` reader - only for debug"] +pub type OUT_CMDFIFO_PUSH_BYTECNT_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_push_bytecnt_ch2(&self) -> OUT_CMDFIFO_PUSH_BYTECNT_CH2_R { + OUT_CMDFIFO_PUSH_BYTECNT_CH2_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_BYTECNT_CH2") + .field( + "out_cmdfifo_push_bytecnt_ch2", + &format_args!("{}", self.out_cmdfifo_push_bytecnt_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH2 push byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_bytecnt_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_BYTECNT_CH2_SPEC; +impl crate::RegisterSpec for OUT_PUSH_BYTECNT_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_bytecnt_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_BYTECNT_CH2_SPEC {} +#[doc = "`reset()` method sets OUT_PUSH_BYTECNT_CH2 to value 0xff"] +impl crate::Resettable for OUT_PUSH_BYTECNT_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0xff; +} diff --git a/esp32p4/src/h264_dma/out_push_bytecnt_ch3.rs b/esp32p4/src/h264_dma/out_push_bytecnt_ch3.rs new file mode 100644 index 0000000000..31722b0d50 --- /dev/null +++ b/esp32p4/src/h264_dma/out_push_bytecnt_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_PUSH_BYTECNT_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_PUSH_BYTECNT_CH3` reader - only for debug"] +pub type OUT_CMDFIFO_PUSH_BYTECNT_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_push_bytecnt_ch3(&self) -> OUT_CMDFIFO_PUSH_BYTECNT_CH3_R { + OUT_CMDFIFO_PUSH_BYTECNT_CH3_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_BYTECNT_CH3") + .field( + "out_cmdfifo_push_bytecnt_ch3", + &format_args!("{}", self.out_cmdfifo_push_bytecnt_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH3 push byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_bytecnt_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_BYTECNT_CH3_SPEC; +impl crate::RegisterSpec for OUT_PUSH_BYTECNT_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_bytecnt_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_BYTECNT_CH3_SPEC {} +#[doc = "`reset()` method sets OUT_PUSH_BYTECNT_CH3 to value 0x3f"] +impl crate::Resettable for OUT_PUSH_BYTECNT_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/h264_dma/out_push_bytecnt_ch4.rs b/esp32p4/src/h264_dma/out_push_bytecnt_ch4.rs new file mode 100644 index 0000000000..98eff64961 --- /dev/null +++ b/esp32p4/src/h264_dma/out_push_bytecnt_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_PUSH_BYTECNT_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_PUSH_BYTECNT_CH4` reader - only for debug"] +pub type OUT_CMDFIFO_PUSH_BYTECNT_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_push_bytecnt_ch4(&self) -> OUT_CMDFIFO_PUSH_BYTECNT_CH4_R { + OUT_CMDFIFO_PUSH_BYTECNT_CH4_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_BYTECNT_CH4") + .field( + "out_cmdfifo_push_bytecnt_ch4", + &format_args!("{}", self.out_cmdfifo_push_bytecnt_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH4 push byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_bytecnt_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_BYTECNT_CH4_SPEC; +impl crate::RegisterSpec for OUT_PUSH_BYTECNT_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_bytecnt_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_BYTECNT_CH4_SPEC {} +#[doc = "`reset()` method sets OUT_PUSH_BYTECNT_CH4 to value 0x3f"] +impl crate::Resettable for OUT_PUSH_BYTECNT_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x3f; +} diff --git a/esp32p4/src/h264_dma/out_push_ch0.rs b/esp32p4/src/h264_dma/out_push_ch0.rs new file mode 100644 index 0000000000..6e2915b87c --- /dev/null +++ b/esp32p4/src/h264_dma/out_push_ch0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `OUT_PUSH_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_PUSH_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUTFIFO_WDATA_CH0` reader - This register stores the data that need to be pushed into DMA Tx FIFO."] +pub type OUTFIFO_WDATA_CH0_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA_CH0` writer - This register stores the data that need to be pushed into DMA Tx FIFO."] +pub type OUTFIFO_WDATA_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `OUTFIFO_PUSH_CH0` reader - Set this bit to push data into DMA Tx FIFO."] +pub type OUTFIFO_PUSH_CH0_R = crate::BitReader; +#[doc = "Field `OUTFIFO_PUSH_CH0` writer - Set this bit to push data into DMA Tx FIFO."] +pub type OUTFIFO_PUSH_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:9 - This register stores the data that need to be pushed into DMA Tx FIFO."] + #[inline(always)] + pub fn outfifo_wdata_ch0(&self) -> OUTFIFO_WDATA_CH0_R { + OUTFIFO_WDATA_CH0_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bit 10 - Set this bit to push data into DMA Tx FIFO."] + #[inline(always)] + pub fn outfifo_push_ch0(&self) -> OUTFIFO_PUSH_CH0_R { + OUTFIFO_PUSH_CH0_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_CH0") + .field( + "outfifo_wdata_ch0", + &format_args!("{}", self.outfifo_wdata_ch0().bits()), + ) + .field( + "outfifo_push_ch0", + &format_args!("{}", self.outfifo_push_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - This register stores the data that need to be pushed into DMA Tx FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_wdata_ch0(&mut self) -> OUTFIFO_WDATA_CH0_W { + OUTFIFO_WDATA_CH0_W::new(self, 0) + } + #[doc = "Bit 10 - Set this bit to push data into DMA Tx FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_push_ch0(&mut self) -> OUTFIFO_PUSH_CH0_W { + OUTFIFO_PUSH_CH0_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH0 outfifo push register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_CH0_SPEC; +impl crate::RegisterSpec for OUT_PUSH_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_push_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_PUSH_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_PUSH_CH0 to value 0"] +impl crate::Resettable for OUT_PUSH_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_push_ch1.rs b/esp32p4/src/h264_dma/out_push_ch1.rs new file mode 100644 index 0000000000..21bd725636 --- /dev/null +++ b/esp32p4/src/h264_dma/out_push_ch1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `OUT_PUSH_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_PUSH_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `OUTFIFO_WDATA_CH1` reader - This register stores the data that need to be pushed into DMA Tx FIFO."] +pub type OUTFIFO_WDATA_CH1_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA_CH1` writer - This register stores the data that need to be pushed into DMA Tx FIFO."] +pub type OUTFIFO_WDATA_CH1_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `OUTFIFO_PUSH_CH1` reader - Set this bit to push data into DMA Tx FIFO."] +pub type OUTFIFO_PUSH_CH1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_PUSH_CH1` writer - Set this bit to push data into DMA Tx FIFO."] +pub type OUTFIFO_PUSH_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:9 - This register stores the data that need to be pushed into DMA Tx FIFO."] + #[inline(always)] + pub fn outfifo_wdata_ch1(&self) -> OUTFIFO_WDATA_CH1_R { + OUTFIFO_WDATA_CH1_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bit 10 - Set this bit to push data into DMA Tx FIFO."] + #[inline(always)] + pub fn outfifo_push_ch1(&self) -> OUTFIFO_PUSH_CH1_R { + OUTFIFO_PUSH_CH1_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_CH1") + .field( + "outfifo_wdata_ch1", + &format_args!("{}", self.outfifo_wdata_ch1().bits()), + ) + .field( + "outfifo_push_ch1", + &format_args!("{}", self.outfifo_push_ch1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - This register stores the data that need to be pushed into DMA Tx FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_wdata_ch1(&mut self) -> OUTFIFO_WDATA_CH1_W { + OUTFIFO_WDATA_CH1_W::new(self, 0) + } + #[doc = "Bit 10 - Set this bit to push data into DMA Tx FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_push_ch1(&mut self) -> OUTFIFO_PUSH_CH1_W { + OUTFIFO_PUSH_CH1_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH1 outfifo push register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_CH1_SPEC; +impl crate::RegisterSpec for OUT_PUSH_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_push_ch1::W`](W) writer structure"] +impl crate::Writable for OUT_PUSH_CH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_PUSH_CH1 to value 0"] +impl crate::Resettable for OUT_PUSH_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_push_ch2.rs b/esp32p4/src/h264_dma/out_push_ch2.rs new file mode 100644 index 0000000000..fe6eb337b2 --- /dev/null +++ b/esp32p4/src/h264_dma/out_push_ch2.rs @@ -0,0 +1,85 @@ +#[doc = "Register `OUT_PUSH_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_PUSH_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `OUTFIFO_WDATA_CH2` reader - This register stores the data that need to be pushed into DMA Tx FIFO."] +pub type OUTFIFO_WDATA_CH2_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA_CH2` writer - This register stores the data that need to be pushed into DMA Tx FIFO."] +pub type OUTFIFO_WDATA_CH2_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `OUTFIFO_PUSH_CH2` reader - Set this bit to push data into DMA Tx FIFO."] +pub type OUTFIFO_PUSH_CH2_R = crate::BitReader; +#[doc = "Field `OUTFIFO_PUSH_CH2` writer - Set this bit to push data into DMA Tx FIFO."] +pub type OUTFIFO_PUSH_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:9 - This register stores the data that need to be pushed into DMA Tx FIFO."] + #[inline(always)] + pub fn outfifo_wdata_ch2(&self) -> OUTFIFO_WDATA_CH2_R { + OUTFIFO_WDATA_CH2_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bit 10 - Set this bit to push data into DMA Tx FIFO."] + #[inline(always)] + pub fn outfifo_push_ch2(&self) -> OUTFIFO_PUSH_CH2_R { + OUTFIFO_PUSH_CH2_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_CH2") + .field( + "outfifo_wdata_ch2", + &format_args!("{}", self.outfifo_wdata_ch2().bits()), + ) + .field( + "outfifo_push_ch2", + &format_args!("{}", self.outfifo_push_ch2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - This register stores the data that need to be pushed into DMA Tx FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_wdata_ch2(&mut self) -> OUTFIFO_WDATA_CH2_W { + OUTFIFO_WDATA_CH2_W::new(self, 0) + } + #[doc = "Bit 10 - Set this bit to push data into DMA Tx FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_push_ch2(&mut self) -> OUTFIFO_PUSH_CH2_W { + OUTFIFO_PUSH_CH2_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH2 outfifo push register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_CH2_SPEC; +impl crate::RegisterSpec for OUT_PUSH_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_push_ch2::W`](W) writer structure"] +impl crate::Writable for OUT_PUSH_CH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_PUSH_CH2 to value 0"] +impl crate::Resettable for OUT_PUSH_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_push_ch3.rs b/esp32p4/src/h264_dma/out_push_ch3.rs new file mode 100644 index 0000000000..aaeee882e1 --- /dev/null +++ b/esp32p4/src/h264_dma/out_push_ch3.rs @@ -0,0 +1,85 @@ +#[doc = "Register `OUT_PUSH_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_PUSH_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `OUTFIFO_WDATA_CH3` reader - This register stores the data that need to be pushed into DMA Tx FIFO."] +pub type OUTFIFO_WDATA_CH3_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA_CH3` writer - This register stores the data that need to be pushed into DMA Tx FIFO."] +pub type OUTFIFO_WDATA_CH3_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `OUTFIFO_PUSH_CH3` reader - Set this bit to push data into DMA Tx FIFO."] +pub type OUTFIFO_PUSH_CH3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_PUSH_CH3` writer - Set this bit to push data into DMA Tx FIFO."] +pub type OUTFIFO_PUSH_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:9 - This register stores the data that need to be pushed into DMA Tx FIFO."] + #[inline(always)] + pub fn outfifo_wdata_ch3(&self) -> OUTFIFO_WDATA_CH3_R { + OUTFIFO_WDATA_CH3_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bit 10 - Set this bit to push data into DMA Tx FIFO."] + #[inline(always)] + pub fn outfifo_push_ch3(&self) -> OUTFIFO_PUSH_CH3_R { + OUTFIFO_PUSH_CH3_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_CH3") + .field( + "outfifo_wdata_ch3", + &format_args!("{}", self.outfifo_wdata_ch3().bits()), + ) + .field( + "outfifo_push_ch3", + &format_args!("{}", self.outfifo_push_ch3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - This register stores the data that need to be pushed into DMA Tx FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_wdata_ch3(&mut self) -> OUTFIFO_WDATA_CH3_W { + OUTFIFO_WDATA_CH3_W::new(self, 0) + } + #[doc = "Bit 10 - Set this bit to push data into DMA Tx FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_push_ch3(&mut self) -> OUTFIFO_PUSH_CH3_W { + OUTFIFO_PUSH_CH3_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH3 outfifo push register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_CH3_SPEC; +impl crate::RegisterSpec for OUT_PUSH_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_push_ch3::W`](W) writer structure"] +impl crate::Writable for OUT_PUSH_CH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_PUSH_CH3 to value 0"] +impl crate::Resettable for OUT_PUSH_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_push_ch4.rs b/esp32p4/src/h264_dma/out_push_ch4.rs new file mode 100644 index 0000000000..fc8f21072d --- /dev/null +++ b/esp32p4/src/h264_dma/out_push_ch4.rs @@ -0,0 +1,85 @@ +#[doc = "Register `OUT_PUSH_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_PUSH_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `OUTFIFO_WDATA_CH4` reader - This register stores the data that need to be pushed into DMA Tx FIFO."] +pub type OUTFIFO_WDATA_CH4_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_WDATA_CH4` writer - This register stores the data that need to be pushed into DMA Tx FIFO."] +pub type OUTFIFO_WDATA_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `OUTFIFO_PUSH_CH4` reader - Set this bit to push data into DMA Tx FIFO."] +pub type OUTFIFO_PUSH_CH4_R = crate::BitReader; +#[doc = "Field `OUTFIFO_PUSH_CH4` writer - Set this bit to push data into DMA Tx FIFO."] +pub type OUTFIFO_PUSH_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:9 - This register stores the data that need to be pushed into DMA Tx FIFO."] + #[inline(always)] + pub fn outfifo_wdata_ch4(&self) -> OUTFIFO_WDATA_CH4_R { + OUTFIFO_WDATA_CH4_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bit 10 - Set this bit to push data into DMA Tx FIFO."] + #[inline(always)] + pub fn outfifo_push_ch4(&self) -> OUTFIFO_PUSH_CH4_R { + OUTFIFO_PUSH_CH4_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_PUSH_CH4") + .field( + "outfifo_wdata_ch4", + &format_args!("{}", self.outfifo_wdata_ch4().bits()), + ) + .field( + "outfifo_push_ch4", + &format_args!("{}", self.outfifo_push_ch4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - This register stores the data that need to be pushed into DMA Tx FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_wdata_ch4(&mut self) -> OUTFIFO_WDATA_CH4_W { + OUTFIFO_WDATA_CH4_W::new(self, 0) + } + #[doc = "Bit 10 - Set this bit to push data into DMA Tx FIFO."] + #[inline(always)] + #[must_use] + pub fn outfifo_push_ch4(&mut self) -> OUTFIFO_PUSH_CH4_W { + OUTFIFO_PUSH_CH4_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH4 outfifo push register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_push_ch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_push_ch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_PUSH_CH4_SPEC; +impl crate::RegisterSpec for OUT_PUSH_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_push_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_PUSH_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_push_ch4::W`](W) writer structure"] +impl crate::Writable for OUT_PUSH_CH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_PUSH_CH4 to value 0"] +impl crate::Resettable for OUT_PUSH_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_ro_pd_conf_ch0.rs b/esp32p4/src/h264_dma/out_ro_pd_conf_ch0.rs new file mode 100644 index 0000000000..28b2e05d04 --- /dev/null +++ b/esp32p4/src/h264_dma/out_ro_pd_conf_ch0.rs @@ -0,0 +1,108 @@ +#[doc = "Register `OUT_RO_PD_CONF_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `OUT_RO_PD_CONF_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_RO_RAM_FORCE_PD_CH0` reader - dma reorder ram power down"] +pub type OUT_RO_RAM_FORCE_PD_CH0_R = crate::BitReader; +#[doc = "Field `OUT_RO_RAM_FORCE_PD_CH0` writer - dma reorder ram power down"] +pub type OUT_RO_RAM_FORCE_PD_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_RO_RAM_FORCE_PU_CH0` reader - dma reorder ram power up"] +pub type OUT_RO_RAM_FORCE_PU_CH0_R = crate::BitReader; +#[doc = "Field `OUT_RO_RAM_FORCE_PU_CH0` writer - dma reorder ram power up"] +pub type OUT_RO_RAM_FORCE_PU_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_RO_RAM_CLK_FO_CH0` reader - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] +pub type OUT_RO_RAM_CLK_FO_CH0_R = crate::BitReader; +#[doc = "Field `OUT_RO_RAM_CLK_FO_CH0` writer - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] +pub type OUT_RO_RAM_CLK_FO_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 4 - dma reorder ram power down"] + #[inline(always)] + pub fn out_ro_ram_force_pd_ch0(&self) -> OUT_RO_RAM_FORCE_PD_CH0_R { + OUT_RO_RAM_FORCE_PD_CH0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - dma reorder ram power up"] + #[inline(always)] + pub fn out_ro_ram_force_pu_ch0(&self) -> OUT_RO_RAM_FORCE_PU_CH0_R { + OUT_RO_RAM_FORCE_PU_CH0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] + #[inline(always)] + pub fn out_ro_ram_clk_fo_ch0(&self) -> OUT_RO_RAM_CLK_FO_CH0_R { + OUT_RO_RAM_CLK_FO_CH0_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_RO_PD_CONF_CH0") + .field( + "out_ro_ram_force_pd_ch0", + &format_args!("{}", self.out_ro_ram_force_pd_ch0().bit()), + ) + .field( + "out_ro_ram_force_pu_ch0", + &format_args!("{}", self.out_ro_ram_force_pu_ch0().bit()), + ) + .field( + "out_ro_ram_clk_fo_ch0", + &format_args!("{}", self.out_ro_ram_clk_fo_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 4 - dma reorder ram power down"] + #[inline(always)] + #[must_use] + pub fn out_ro_ram_force_pd_ch0( + &mut self, + ) -> OUT_RO_RAM_FORCE_PD_CH0_W { + OUT_RO_RAM_FORCE_PD_CH0_W::new(self, 4) + } + #[doc = "Bit 5 - dma reorder ram power up"] + #[inline(always)] + #[must_use] + pub fn out_ro_ram_force_pu_ch0( + &mut self, + ) -> OUT_RO_RAM_FORCE_PU_CH0_W { + OUT_RO_RAM_FORCE_PU_CH0_W::new(self, 5) + } + #[doc = "Bit 6 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."] + #[inline(always)] + #[must_use] + pub fn out_ro_ram_clk_fo_ch0(&mut self) -> OUT_RO_RAM_CLK_FO_CH0_W { + OUT_RO_RAM_CLK_FO_CH0_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TX CH0 reorder power config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ro_pd_conf_ch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_ro_pd_conf_ch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_RO_PD_CONF_CH0_SPEC; +impl crate::RegisterSpec for OUT_RO_PD_CONF_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_ro_pd_conf_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_RO_PD_CONF_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out_ro_pd_conf_ch0::W`](W) writer structure"] +impl crate::Writable for OUT_RO_PD_CONF_CH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_RO_PD_CONF_CH0 to value 0x20"] +impl crate::Resettable for OUT_RO_PD_CONF_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x20; +} diff --git a/esp32p4/src/h264_dma/out_ro_status_ch0.rs b/esp32p4/src/h264_dma/out_ro_status_ch0.rs new file mode 100644 index 0000000000..7b9ca5ef9c --- /dev/null +++ b/esp32p4/src/h264_dma/out_ro_status_ch0.rs @@ -0,0 +1,83 @@ +#[doc = "Register `OUT_RO_STATUS_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUTFIFO_RO_CNT_CH0` reader - The register stores the 8byte number of the data in reorder Tx FIFO for channel 0."] +pub type OUTFIFO_RO_CNT_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_RO_WR_STATE_CH0` reader - The register stores the state of read ram of reorder"] +pub type OUT_RO_WR_STATE_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_RO_RD_STATE_CH0` reader - The register stores the state of write ram of reorder"] +pub type OUT_RO_RD_STATE_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_PIXEL_BYTE_CH0` reader - the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes"] +pub type OUT_PIXEL_BYTE_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_BURST_BLOCK_NUM_CH0` reader - the number of macro blocks contained in a burst of data at TX channel"] +pub type OUT_BURST_BLOCK_NUM_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - The register stores the 8byte number of the data in reorder Tx FIFO for channel 0."] + #[inline(always)] + pub fn outfifo_ro_cnt_ch0(&self) -> OUTFIFO_RO_CNT_CH0_R { + OUTFIFO_RO_CNT_CH0_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 6:7 - The register stores the state of read ram of reorder"] + #[inline(always)] + pub fn out_ro_wr_state_ch0(&self) -> OUT_RO_WR_STATE_CH0_R { + OUT_RO_WR_STATE_CH0_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - The register stores the state of write ram of reorder"] + #[inline(always)] + pub fn out_ro_rd_state_ch0(&self) -> OUT_RO_RD_STATE_CH0_R { + OUT_RO_RD_STATE_CH0_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:13 - the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes"] + #[inline(always)] + pub fn out_pixel_byte_ch0(&self) -> OUT_PIXEL_BYTE_CH0_R { + OUT_PIXEL_BYTE_CH0_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 14:17 - the number of macro blocks contained in a burst of data at TX channel"] + #[inline(always)] + pub fn out_burst_block_num_ch0(&self) -> OUT_BURST_BLOCK_NUM_CH0_R { + OUT_BURST_BLOCK_NUM_CH0_R::new(((self.bits >> 14) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_RO_STATUS_CH0") + .field( + "outfifo_ro_cnt_ch0", + &format_args!("{}", self.outfifo_ro_cnt_ch0().bits()), + ) + .field( + "out_ro_wr_state_ch0", + &format_args!("{}", self.out_ro_wr_state_ch0().bits()), + ) + .field( + "out_ro_rd_state_ch0", + &format_args!("{}", self.out_ro_rd_state_ch0().bits()), + ) + .field( + "out_pixel_byte_ch0", + &format_args!("{}", self.out_pixel_byte_ch0().bits()), + ) + .field( + "out_burst_block_num_ch0", + &format_args!("{}", self.out_burst_block_num_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH0 reorder status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ro_status_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_RO_STATUS_CH0_SPEC; +impl crate::RegisterSpec for OUT_RO_STATUS_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_ro_status_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_RO_STATUS_CH0_SPEC {} +#[doc = "`reset()` method sets OUT_RO_STATUS_CH0 to value 0x0800"] +impl crate::Resettable for OUT_RO_STATUS_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/h264_dma/out_state_ch0.rs b/esp32p4/src/h264_dma/out_state_ch0.rs new file mode 100644 index 0000000000..1418b22974 --- /dev/null +++ b/esp32p4/src/h264_dma/out_state_ch0.rs @@ -0,0 +1,72 @@ +#[doc = "Register `OUT_STATE_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_ADDR_CH0` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE_CH0` reader - This register stores the current descriptor state machine state."] +pub type OUT_DSCR_STATE_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_STATE_CH0` reader - This register stores the current control module state machine state."] +pub type OUT_STATE_CH0_R = crate::FieldReader; +#[doc = "Field `OUT_RESET_AVAIL_CH0` reader - This register indicate that if the channel reset is safety."] +pub type OUT_RESET_AVAIL_CH0_R = crate::BitReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] + #[inline(always)] + pub fn outlink_dscr_addr_ch0(&self) -> OUTLINK_DSCR_ADDR_CH0_R { + OUTLINK_DSCR_ADDR_CH0_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - This register stores the current descriptor state machine state."] + #[inline(always)] + pub fn out_dscr_state_ch0(&self) -> OUT_DSCR_STATE_CH0_R { + OUT_DSCR_STATE_CH0_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:23 - This register stores the current control module state machine state."] + #[inline(always)] + pub fn out_state_ch0(&self) -> OUT_STATE_CH0_R { + OUT_STATE_CH0_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bit 24 - This register indicate that if the channel reset is safety."] + #[inline(always)] + pub fn out_reset_avail_ch0(&self) -> OUT_RESET_AVAIL_CH0_R { + OUT_RESET_AVAIL_CH0_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_STATE_CH0") + .field( + "outlink_dscr_addr_ch0", + &format_args!("{}", self.outlink_dscr_addr_ch0().bits()), + ) + .field( + "out_dscr_state_ch0", + &format_args!("{}", self.out_dscr_state_ch0().bits()), + ) + .field( + "out_state_ch0", + &format_args!("{}", self.out_state_ch0().bits()), + ) + .field( + "out_reset_avail_ch0", + &format_args!("{}", self.out_reset_avail_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH0 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_STATE_CH0_SPEC; +impl crate::RegisterSpec for OUT_STATE_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_state_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_STATE_CH0_SPEC {} +#[doc = "`reset()` method sets OUT_STATE_CH0 to value 0x0100_0000"] +impl crate::Resettable for OUT_STATE_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x0100_0000; +} diff --git a/esp32p4/src/h264_dma/out_state_ch1.rs b/esp32p4/src/h264_dma/out_state_ch1.rs new file mode 100644 index 0000000000..3400594bdf --- /dev/null +++ b/esp32p4/src/h264_dma/out_state_ch1.rs @@ -0,0 +1,72 @@ +#[doc = "Register `OUT_STATE_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_ADDR_CH1` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_CH1_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE_CH1` reader - This register stores the current descriptor state machine state."] +pub type OUT_DSCR_STATE_CH1_R = crate::FieldReader; +#[doc = "Field `OUT_STATE_CH1` reader - This register stores the current control module state machine state."] +pub type OUT_STATE_CH1_R = crate::FieldReader; +#[doc = "Field `OUT_RESET_AVAIL_CH1` reader - This register indicate that if the channel reset is safety."] +pub type OUT_RESET_AVAIL_CH1_R = crate::BitReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] + #[inline(always)] + pub fn outlink_dscr_addr_ch1(&self) -> OUTLINK_DSCR_ADDR_CH1_R { + OUTLINK_DSCR_ADDR_CH1_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - This register stores the current descriptor state machine state."] + #[inline(always)] + pub fn out_dscr_state_ch1(&self) -> OUT_DSCR_STATE_CH1_R { + OUT_DSCR_STATE_CH1_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:23 - This register stores the current control module state machine state."] + #[inline(always)] + pub fn out_state_ch1(&self) -> OUT_STATE_CH1_R { + OUT_STATE_CH1_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bit 24 - This register indicate that if the channel reset is safety."] + #[inline(always)] + pub fn out_reset_avail_ch1(&self) -> OUT_RESET_AVAIL_CH1_R { + OUT_RESET_AVAIL_CH1_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_STATE_CH1") + .field( + "outlink_dscr_addr_ch1", + &format_args!("{}", self.outlink_dscr_addr_ch1().bits()), + ) + .field( + "out_dscr_state_ch1", + &format_args!("{}", self.out_dscr_state_ch1().bits()), + ) + .field( + "out_state_ch1", + &format_args!("{}", self.out_state_ch1().bits()), + ) + .field( + "out_reset_avail_ch1", + &format_args!("{}", self.out_reset_avail_ch1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH1 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_STATE_CH1_SPEC; +impl crate::RegisterSpec for OUT_STATE_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_state_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_STATE_CH1_SPEC {} +#[doc = "`reset()` method sets OUT_STATE_CH1 to value 0x0100_0000"] +impl crate::Resettable for OUT_STATE_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x0100_0000; +} diff --git a/esp32p4/src/h264_dma/out_state_ch2.rs b/esp32p4/src/h264_dma/out_state_ch2.rs new file mode 100644 index 0000000000..354e2f5e9c --- /dev/null +++ b/esp32p4/src/h264_dma/out_state_ch2.rs @@ -0,0 +1,72 @@ +#[doc = "Register `OUT_STATE_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_ADDR_CH2` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_CH2_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE_CH2` reader - This register stores the current descriptor state machine state."] +pub type OUT_DSCR_STATE_CH2_R = crate::FieldReader; +#[doc = "Field `OUT_STATE_CH2` reader - This register stores the current control module state machine state."] +pub type OUT_STATE_CH2_R = crate::FieldReader; +#[doc = "Field `OUT_RESET_AVAIL_CH2` reader - This register indicate that if the channel reset is safety."] +pub type OUT_RESET_AVAIL_CH2_R = crate::BitReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] + #[inline(always)] + pub fn outlink_dscr_addr_ch2(&self) -> OUTLINK_DSCR_ADDR_CH2_R { + OUTLINK_DSCR_ADDR_CH2_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - This register stores the current descriptor state machine state."] + #[inline(always)] + pub fn out_dscr_state_ch2(&self) -> OUT_DSCR_STATE_CH2_R { + OUT_DSCR_STATE_CH2_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:23 - This register stores the current control module state machine state."] + #[inline(always)] + pub fn out_state_ch2(&self) -> OUT_STATE_CH2_R { + OUT_STATE_CH2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bit 24 - This register indicate that if the channel reset is safety."] + #[inline(always)] + pub fn out_reset_avail_ch2(&self) -> OUT_RESET_AVAIL_CH2_R { + OUT_RESET_AVAIL_CH2_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_STATE_CH2") + .field( + "outlink_dscr_addr_ch2", + &format_args!("{}", self.outlink_dscr_addr_ch2().bits()), + ) + .field( + "out_dscr_state_ch2", + &format_args!("{}", self.out_dscr_state_ch2().bits()), + ) + .field( + "out_state_ch2", + &format_args!("{}", self.out_state_ch2().bits()), + ) + .field( + "out_reset_avail_ch2", + &format_args!("{}", self.out_reset_avail_ch2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH2 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_STATE_CH2_SPEC; +impl crate::RegisterSpec for OUT_STATE_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_state_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_STATE_CH2_SPEC {} +#[doc = "`reset()` method sets OUT_STATE_CH2 to value 0x0100_0000"] +impl crate::Resettable for OUT_STATE_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x0100_0000; +} diff --git a/esp32p4/src/h264_dma/out_state_ch3.rs b/esp32p4/src/h264_dma/out_state_ch3.rs new file mode 100644 index 0000000000..0eaace59b4 --- /dev/null +++ b/esp32p4/src/h264_dma/out_state_ch3.rs @@ -0,0 +1,61 @@ +#[doc = "Register `OUT_STATE_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_ADDR_CH3` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_CH3_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE_CH3` reader - This register stores the current descriptor state machine state."] +pub type OUT_DSCR_STATE_CH3_R = crate::FieldReader; +#[doc = "Field `OUT_STATE_CH3` reader - This register stores the current control module state machine state."] +pub type OUT_STATE_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] + #[inline(always)] + pub fn outlink_dscr_addr_ch3(&self) -> OUTLINK_DSCR_ADDR_CH3_R { + OUTLINK_DSCR_ADDR_CH3_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - This register stores the current descriptor state machine state."] + #[inline(always)] + pub fn out_dscr_state_ch3(&self) -> OUT_DSCR_STATE_CH3_R { + OUT_DSCR_STATE_CH3_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:23 - This register stores the current control module state machine state."] + #[inline(always)] + pub fn out_state_ch3(&self) -> OUT_STATE_CH3_R { + OUT_STATE_CH3_R::new(((self.bits >> 20) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_STATE_CH3") + .field( + "outlink_dscr_addr_ch3", + &format_args!("{}", self.outlink_dscr_addr_ch3().bits()), + ) + .field( + "out_dscr_state_ch3", + &format_args!("{}", self.out_dscr_state_ch3().bits()), + ) + .field( + "out_state_ch3", + &format_args!("{}", self.out_state_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH3 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_STATE_CH3_SPEC; +impl crate::RegisterSpec for OUT_STATE_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_state_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_STATE_CH3_SPEC {} +#[doc = "`reset()` method sets OUT_STATE_CH3 to value 0"] +impl crate::Resettable for OUT_STATE_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_state_ch4.rs b/esp32p4/src/h264_dma/out_state_ch4.rs new file mode 100644 index 0000000000..b2f8929ece --- /dev/null +++ b/esp32p4/src/h264_dma/out_state_ch4.rs @@ -0,0 +1,61 @@ +#[doc = "Register `OUT_STATE_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUTLINK_DSCR_ADDR_CH4` reader - This register stores the current outlink descriptor's address."] +pub type OUTLINK_DSCR_ADDR_CH4_R = crate::FieldReader; +#[doc = "Field `OUT_DSCR_STATE_CH4` reader - This register stores the current descriptor state machine state."] +pub type OUT_DSCR_STATE_CH4_R = crate::FieldReader; +#[doc = "Field `OUT_STATE_CH4` reader - This register stores the current control module state machine state."] +pub type OUT_STATE_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."] + #[inline(always)] + pub fn outlink_dscr_addr_ch4(&self) -> OUTLINK_DSCR_ADDR_CH4_R { + OUTLINK_DSCR_ADDR_CH4_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:19 - This register stores the current descriptor state machine state."] + #[inline(always)] + pub fn out_dscr_state_ch4(&self) -> OUT_DSCR_STATE_CH4_R { + OUT_DSCR_STATE_CH4_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:23 - This register stores the current control module state machine state."] + #[inline(always)] + pub fn out_state_ch4(&self) -> OUT_STATE_CH4_R { + OUT_STATE_CH4_R::new(((self.bits >> 20) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_STATE_CH4") + .field( + "outlink_dscr_addr_ch4", + &format_args!("{}", self.outlink_dscr_addr_ch4().bits()), + ) + .field( + "out_dscr_state_ch4", + &format_args!("{}", self.out_dscr_state_ch4().bits()), + ) + .field( + "out_state_ch4", + &format_args!("{}", self.out_state_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH4 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_STATE_CH4_SPEC; +impl crate::RegisterSpec for OUT_STATE_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_state_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_STATE_CH4_SPEC {} +#[doc = "`reset()` method sets OUT_STATE_CH4 to value 0"] +impl crate::Resettable for OUT_STATE_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_xaddr_ch0.rs b/esp32p4/src/h264_dma/out_xaddr_ch0.rs new file mode 100644 index 0000000000..498fd9993c --- /dev/null +++ b/esp32p4/src/h264_dma/out_xaddr_ch0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_XADDR_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_XADDR_CH0` reader - only for debug"] +pub type OUT_CMDFIFO_XADDR_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_xaddr_ch0(&self) -> OUT_CMDFIFO_XADDR_CH0_R { + OUT_CMDFIFO_XADDR_CH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_XADDR_CH0") + .field( + "out_cmdfifo_xaddr_ch0", + &format_args!("{}", self.out_cmdfifo_xaddr_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH0 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_xaddr_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_XADDR_CH0_SPEC; +impl crate::RegisterSpec for OUT_XADDR_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_xaddr_ch0::R`](R) reader structure"] +impl crate::Readable for OUT_XADDR_CH0_SPEC {} +#[doc = "`reset()` method sets OUT_XADDR_CH0 to value 0"] +impl crate::Resettable for OUT_XADDR_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_xaddr_ch1.rs b/esp32p4/src/h264_dma/out_xaddr_ch1.rs new file mode 100644 index 0000000000..4fcb3faf98 --- /dev/null +++ b/esp32p4/src/h264_dma/out_xaddr_ch1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_XADDR_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_XADDR_CH1` reader - only for debug"] +pub type OUT_CMDFIFO_XADDR_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_xaddr_ch1(&self) -> OUT_CMDFIFO_XADDR_CH1_R { + OUT_CMDFIFO_XADDR_CH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_XADDR_CH1") + .field( + "out_cmdfifo_xaddr_ch1", + &format_args!("{}", self.out_cmdfifo_xaddr_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH1 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_xaddr_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_XADDR_CH1_SPEC; +impl crate::RegisterSpec for OUT_XADDR_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_xaddr_ch1::R`](R) reader structure"] +impl crate::Readable for OUT_XADDR_CH1_SPEC {} +#[doc = "`reset()` method sets OUT_XADDR_CH1 to value 0"] +impl crate::Resettable for OUT_XADDR_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_xaddr_ch2.rs b/esp32p4/src/h264_dma/out_xaddr_ch2.rs new file mode 100644 index 0000000000..b79cade428 --- /dev/null +++ b/esp32p4/src/h264_dma/out_xaddr_ch2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_XADDR_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_XADDR_CH2` reader - only for debug"] +pub type OUT_CMDFIFO_XADDR_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_xaddr_ch2(&self) -> OUT_CMDFIFO_XADDR_CH2_R { + OUT_CMDFIFO_XADDR_CH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_XADDR_CH2") + .field( + "out_cmdfifo_xaddr_ch2", + &format_args!("{}", self.out_cmdfifo_xaddr_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH2 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_xaddr_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_XADDR_CH2_SPEC; +impl crate::RegisterSpec for OUT_XADDR_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_xaddr_ch2::R`](R) reader structure"] +impl crate::Readable for OUT_XADDR_CH2_SPEC {} +#[doc = "`reset()` method sets OUT_XADDR_CH2 to value 0"] +impl crate::Resettable for OUT_XADDR_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_xaddr_ch3.rs b/esp32p4/src/h264_dma/out_xaddr_ch3.rs new file mode 100644 index 0000000000..c7452f24ca --- /dev/null +++ b/esp32p4/src/h264_dma/out_xaddr_ch3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_XADDR_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_XADDR_CH3` reader - only for debug"] +pub type OUT_CMDFIFO_XADDR_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_xaddr_ch3(&self) -> OUT_CMDFIFO_XADDR_CH3_R { + OUT_CMDFIFO_XADDR_CH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_XADDR_CH3") + .field( + "out_cmdfifo_xaddr_ch3", + &format_args!("{}", self.out_cmdfifo_xaddr_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH3 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_xaddr_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_XADDR_CH3_SPEC; +impl crate::RegisterSpec for OUT_XADDR_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_xaddr_ch3::R`](R) reader structure"] +impl crate::Readable for OUT_XADDR_CH3_SPEC {} +#[doc = "`reset()` method sets OUT_XADDR_CH3 to value 0"] +impl crate::Resettable for OUT_XADDR_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/out_xaddr_ch4.rs b/esp32p4/src/h264_dma/out_xaddr_ch4.rs new file mode 100644 index 0000000000..b6243847d8 --- /dev/null +++ b/esp32p4/src/h264_dma/out_xaddr_ch4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `OUT_XADDR_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUT_CMDFIFO_XADDR_CH4` reader - only for debug"] +pub type OUT_CMDFIFO_XADDR_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - only for debug"] + #[inline(always)] + pub fn out_cmdfifo_xaddr_ch4(&self) -> OUT_CMDFIFO_XADDR_CH4_R { + OUT_CMDFIFO_XADDR_CH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_XADDR_CH4") + .field( + "out_cmdfifo_xaddr_ch4", + &format_args!("{}", self.out_cmdfifo_xaddr_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "tx CH4 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_xaddr_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_XADDR_CH4_SPEC; +impl crate::RegisterSpec for OUT_XADDR_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_xaddr_ch4::R`](R) reader structure"] +impl crate::Readable for OUT_XADDR_CH4_SPEC {} +#[doc = "`reset()` method sets OUT_XADDR_CH4 to value 0"] +impl crate::Resettable for OUT_XADDR_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/outfifo_status_ch0.rs b/esp32p4/src/h264_dma/outfifo_status_ch0.rs new file mode 100644 index 0000000000..cb7917b196 --- /dev/null +++ b/esp32p4/src/h264_dma/outfifo_status_ch0.rs @@ -0,0 +1,127 @@ +#[doc = "Register `OUTFIFO_STATUS_CH0` reader"] +pub type R = crate::R; +#[doc = "Field `OUTFIFO_FULL_L2_CH0` reader - Tx FIFO full signal for Tx channel 0."] +pub type OUTFIFO_FULL_L2_CH0_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L2_CH0` reader - Tx FIFO empty signal for Tx channel 0."] +pub type OUTFIFO_EMPTY_L2_CH0_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L2_CH0` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 0."] +pub type OUTFIFO_CNT_L2_CH0_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_FULL_L1_CH0` reader - Tx FIFO full signal for Tx channel 0."] +pub type OUTFIFO_FULL_L1_CH0_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L1_CH0` reader - Tx FIFO empty signal for Tx channel 0."] +pub type OUTFIFO_EMPTY_L1_CH0_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L1_CH0` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 0."] +pub type OUTFIFO_CNT_L1_CH0_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_FULL_L3_CH0` reader - Tx FIFO full signal for Tx channel 0."] +pub type OUTFIFO_FULL_L3_CH0_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L3_CH0` reader - Tx FIFO empty signal for Tx channel 0."] +pub type OUTFIFO_EMPTY_L3_CH0_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L3_CH0` reader - The register stores the 8byte number of the data in Tx FIFO for Tx channel 0."] +pub type OUTFIFO_CNT_L3_CH0_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Tx FIFO full signal for Tx channel 0."] + #[inline(always)] + pub fn outfifo_full_l2_ch0(&self) -> OUTFIFO_FULL_L2_CH0_R { + OUTFIFO_FULL_L2_CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tx FIFO empty signal for Tx channel 0."] + #[inline(always)] + pub fn outfifo_empty_l2_ch0(&self) -> OUTFIFO_EMPTY_L2_CH0_R { + OUTFIFO_EMPTY_L2_CH0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The register stores the byte number of the data in Tx FIFO for Tx channel 0."] + #[inline(always)] + pub fn outfifo_cnt_l2_ch0(&self) -> OUTFIFO_CNT_L2_CH0_R { + OUTFIFO_CNT_L2_CH0_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - Tx FIFO full signal for Tx channel 0."] + #[inline(always)] + pub fn outfifo_full_l1_ch0(&self) -> OUTFIFO_FULL_L1_CH0_R { + OUTFIFO_FULL_L1_CH0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tx FIFO empty signal for Tx channel 0."] + #[inline(always)] + pub fn outfifo_empty_l1_ch0(&self) -> OUTFIFO_EMPTY_L1_CH0_R { + OUTFIFO_EMPTY_L1_CH0_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - The register stores the byte number of the data in Tx FIFO for Tx channel 0."] + #[inline(always)] + pub fn outfifo_cnt_l1_ch0(&self) -> OUTFIFO_CNT_L1_CH0_R { + OUTFIFO_CNT_L1_CH0_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Tx FIFO full signal for Tx channel 0."] + #[inline(always)] + pub fn outfifo_full_l3_ch0(&self) -> OUTFIFO_FULL_L3_CH0_R { + OUTFIFO_FULL_L3_CH0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tx FIFO empty signal for Tx channel 0."] + #[inline(always)] + pub fn outfifo_empty_l3_ch0(&self) -> OUTFIFO_EMPTY_L3_CH0_R { + OUTFIFO_EMPTY_L3_CH0_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - The register stores the 8byte number of the data in Tx FIFO for Tx channel 0."] + #[inline(always)] + pub fn outfifo_cnt_l3_ch0(&self) -> OUTFIFO_CNT_L3_CH0_R { + OUTFIFO_CNT_L3_CH0_R::new(((self.bits >> 18) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUTFIFO_STATUS_CH0") + .field( + "outfifo_full_l2_ch0", + &format_args!("{}", self.outfifo_full_l2_ch0().bit()), + ) + .field( + "outfifo_empty_l2_ch0", + &format_args!("{}", self.outfifo_empty_l2_ch0().bit()), + ) + .field( + "outfifo_cnt_l2_ch0", + &format_args!("{}", self.outfifo_cnt_l2_ch0().bits()), + ) + .field( + "outfifo_full_l1_ch0", + &format_args!("{}", self.outfifo_full_l1_ch0().bit()), + ) + .field( + "outfifo_empty_l1_ch0", + &format_args!("{}", self.outfifo_empty_l1_ch0().bit()), + ) + .field( + "outfifo_cnt_l1_ch0", + &format_args!("{}", self.outfifo_cnt_l1_ch0().bits()), + ) + .field( + "outfifo_full_l3_ch0", + &format_args!("{}", self.outfifo_full_l3_ch0().bit()), + ) + .field( + "outfifo_empty_l3_ch0", + &format_args!("{}", self.outfifo_empty_l3_ch0().bit()), + ) + .field( + "outfifo_cnt_l3_ch0", + &format_args!("{}", self.outfifo_cnt_l3_ch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH0 outfifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUTFIFO_STATUS_CH0_SPEC; +impl crate::RegisterSpec for OUTFIFO_STATUS_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`outfifo_status_ch0::R`](R) reader structure"] +impl crate::Readable for OUTFIFO_STATUS_CH0_SPEC {} +#[doc = "`reset()` method sets OUTFIFO_STATUS_CH0 to value 0x0002_0082"] +impl crate::Resettable for OUTFIFO_STATUS_CH0_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_0082; +} diff --git a/esp32p4/src/h264_dma/outfifo_status_ch1.rs b/esp32p4/src/h264_dma/outfifo_status_ch1.rs new file mode 100644 index 0000000000..63bf559059 --- /dev/null +++ b/esp32p4/src/h264_dma/outfifo_status_ch1.rs @@ -0,0 +1,127 @@ +#[doc = "Register `OUTFIFO_STATUS_CH1` reader"] +pub type R = crate::R; +#[doc = "Field `OUTFIFO_FULL_L2_CH1` reader - Tx FIFO full signal for Tx channel 1."] +pub type OUTFIFO_FULL_L2_CH1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L2_CH1` reader - Tx FIFO empty signal for Tx channel 1."] +pub type OUTFIFO_EMPTY_L2_CH1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L2_CH1` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type OUTFIFO_CNT_L2_CH1_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_FULL_L1_CH1` reader - Tx FIFO full signal for Tx channel 1."] +pub type OUTFIFO_FULL_L1_CH1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L1_CH1` reader - Tx FIFO empty signal for Tx channel 1."] +pub type OUTFIFO_EMPTY_L1_CH1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L1_CH1` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type OUTFIFO_CNT_L1_CH1_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_FULL_L3_CH1` reader - Tx FIFO full signal for Tx channel 1."] +pub type OUTFIFO_FULL_L3_CH1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L3_CH1` reader - Tx FIFO empty signal for Tx channel 1."] +pub type OUTFIFO_EMPTY_L3_CH1_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L3_CH1` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] +pub type OUTFIFO_CNT_L3_CH1_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn outfifo_full_l2_ch1(&self) -> OUTFIFO_FULL_L2_CH1_R { + OUTFIFO_FULL_L2_CH1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn outfifo_empty_l2_ch1(&self) -> OUTFIFO_EMPTY_L2_CH1_R { + OUTFIFO_EMPTY_L2_CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn outfifo_cnt_l2_ch1(&self) -> OUTFIFO_CNT_L2_CH1_R { + OUTFIFO_CNT_L2_CH1_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn outfifo_full_l1_ch1(&self) -> OUTFIFO_FULL_L1_CH1_R { + OUTFIFO_FULL_L1_CH1_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn outfifo_empty_l1_ch1(&self) -> OUTFIFO_EMPTY_L1_CH1_R { + OUTFIFO_EMPTY_L1_CH1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn outfifo_cnt_l1_ch1(&self) -> OUTFIFO_CNT_L1_CH1_R { + OUTFIFO_CNT_L1_CH1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Tx FIFO full signal for Tx channel 1."] + #[inline(always)] + pub fn outfifo_full_l3_ch1(&self) -> OUTFIFO_FULL_L3_CH1_R { + OUTFIFO_FULL_L3_CH1_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tx FIFO empty signal for Tx channel 1."] + #[inline(always)] + pub fn outfifo_empty_l3_ch1(&self) -> OUTFIFO_EMPTY_L3_CH1_R { + OUTFIFO_EMPTY_L3_CH1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - The register stores the byte number of the data in Tx FIFO for Tx channel 1."] + #[inline(always)] + pub fn outfifo_cnt_l3_ch1(&self) -> OUTFIFO_CNT_L3_CH1_R { + OUTFIFO_CNT_L3_CH1_R::new(((self.bits >> 18) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUTFIFO_STATUS_CH1") + .field( + "outfifo_full_l2_ch1", + &format_args!("{}", self.outfifo_full_l2_ch1().bit()), + ) + .field( + "outfifo_empty_l2_ch1", + &format_args!("{}", self.outfifo_empty_l2_ch1().bit()), + ) + .field( + "outfifo_cnt_l2_ch1", + &format_args!("{}", self.outfifo_cnt_l2_ch1().bits()), + ) + .field( + "outfifo_full_l1_ch1", + &format_args!("{}", self.outfifo_full_l1_ch1().bit()), + ) + .field( + "outfifo_empty_l1_ch1", + &format_args!("{}", self.outfifo_empty_l1_ch1().bit()), + ) + .field( + "outfifo_cnt_l1_ch1", + &format_args!("{}", self.outfifo_cnt_l1_ch1().bits()), + ) + .field( + "outfifo_full_l3_ch1", + &format_args!("{}", self.outfifo_full_l3_ch1().bit()), + ) + .field( + "outfifo_empty_l3_ch1", + &format_args!("{}", self.outfifo_empty_l3_ch1().bit()), + ) + .field( + "outfifo_cnt_l3_ch1", + &format_args!("{}", self.outfifo_cnt_l3_ch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH1 outfifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUTFIFO_STATUS_CH1_SPEC; +impl crate::RegisterSpec for OUTFIFO_STATUS_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`outfifo_status_ch1::R`](R) reader structure"] +impl crate::Readable for OUTFIFO_STATUS_CH1_SPEC {} +#[doc = "`reset()` method sets OUTFIFO_STATUS_CH1 to value 0x0002_0082"] +impl crate::Resettable for OUTFIFO_STATUS_CH1_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_0082; +} diff --git a/esp32p4/src/h264_dma/outfifo_status_ch2.rs b/esp32p4/src/h264_dma/outfifo_status_ch2.rs new file mode 100644 index 0000000000..899f5e7c5c --- /dev/null +++ b/esp32p4/src/h264_dma/outfifo_status_ch2.rs @@ -0,0 +1,127 @@ +#[doc = "Register `OUTFIFO_STATUS_CH2` reader"] +pub type R = crate::R; +#[doc = "Field `OUTFIFO_FULL_L2_CH2` reader - Tx FIFO full signal for Tx channel 2."] +pub type OUTFIFO_FULL_L2_CH2_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L2_CH2` reader - Tx FIFO empty signal for Tx channel 2."] +pub type OUTFIFO_EMPTY_L2_CH2_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L2_CH2` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] +pub type OUTFIFO_CNT_L2_CH2_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_FULL_L1_CH2` reader - Tx FIFO full signal for Tx channel 2."] +pub type OUTFIFO_FULL_L1_CH2_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L1_CH2` reader - Tx FIFO empty signal for Tx channel 2."] +pub type OUTFIFO_EMPTY_L1_CH2_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L1_CH2` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] +pub type OUTFIFO_CNT_L1_CH2_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_FULL_L3_CH2` reader - Tx FIFO full signal for Tx channel 2."] +pub type OUTFIFO_FULL_L3_CH2_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L3_CH2` reader - Tx FIFO empty signal for Tx channel 2."] +pub type OUTFIFO_EMPTY_L3_CH2_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L3_CH2` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] +pub type OUTFIFO_CNT_L3_CH2_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Tx FIFO full signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_full_l2_ch2(&self) -> OUTFIFO_FULL_L2_CH2_R { + OUTFIFO_FULL_L2_CH2_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tx FIFO empty signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_empty_l2_ch2(&self) -> OUTFIFO_EMPTY_L2_CH2_R { + OUTFIFO_EMPTY_L2_CH2_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] + #[inline(always)] + pub fn outfifo_cnt_l2_ch2(&self) -> OUTFIFO_CNT_L2_CH2_R { + OUTFIFO_CNT_L2_CH2_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - Tx FIFO full signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_full_l1_ch2(&self) -> OUTFIFO_FULL_L1_CH2_R { + OUTFIFO_FULL_L1_CH2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tx FIFO empty signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_empty_l1_ch2(&self) -> OUTFIFO_EMPTY_L1_CH2_R { + OUTFIFO_EMPTY_L1_CH2_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] + #[inline(always)] + pub fn outfifo_cnt_l1_ch2(&self) -> OUTFIFO_CNT_L1_CH2_R { + OUTFIFO_CNT_L1_CH2_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Tx FIFO full signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_full_l3_ch2(&self) -> OUTFIFO_FULL_L3_CH2_R { + OUTFIFO_FULL_L3_CH2_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tx FIFO empty signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_empty_l3_ch2(&self) -> OUTFIFO_EMPTY_L3_CH2_R { + OUTFIFO_EMPTY_L3_CH2_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] + #[inline(always)] + pub fn outfifo_cnt_l3_ch2(&self) -> OUTFIFO_CNT_L3_CH2_R { + OUTFIFO_CNT_L3_CH2_R::new(((self.bits >> 18) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUTFIFO_STATUS_CH2") + .field( + "outfifo_full_l2_ch2", + &format_args!("{}", self.outfifo_full_l2_ch2().bit()), + ) + .field( + "outfifo_empty_l2_ch2", + &format_args!("{}", self.outfifo_empty_l2_ch2().bit()), + ) + .field( + "outfifo_cnt_l2_ch2", + &format_args!("{}", self.outfifo_cnt_l2_ch2().bits()), + ) + .field( + "outfifo_full_l1_ch2", + &format_args!("{}", self.outfifo_full_l1_ch2().bit()), + ) + .field( + "outfifo_empty_l1_ch2", + &format_args!("{}", self.outfifo_empty_l1_ch2().bit()), + ) + .field( + "outfifo_cnt_l1_ch2", + &format_args!("{}", self.outfifo_cnt_l1_ch2().bits()), + ) + .field( + "outfifo_full_l3_ch2", + &format_args!("{}", self.outfifo_full_l3_ch2().bit()), + ) + .field( + "outfifo_empty_l3_ch2", + &format_args!("{}", self.outfifo_empty_l3_ch2().bit()), + ) + .field( + "outfifo_cnt_l3_ch2", + &format_args!("{}", self.outfifo_cnt_l3_ch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH2 outfifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUTFIFO_STATUS_CH2_SPEC; +impl crate::RegisterSpec for OUTFIFO_STATUS_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`outfifo_status_ch2::R`](R) reader structure"] +impl crate::Readable for OUTFIFO_STATUS_CH2_SPEC {} +#[doc = "`reset()` method sets OUTFIFO_STATUS_CH2 to value 0x0002_0082"] +impl crate::Resettable for OUTFIFO_STATUS_CH2_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_0082; +} diff --git a/esp32p4/src/h264_dma/outfifo_status_ch3.rs b/esp32p4/src/h264_dma/outfifo_status_ch3.rs new file mode 100644 index 0000000000..a0212bf888 --- /dev/null +++ b/esp32p4/src/h264_dma/outfifo_status_ch3.rs @@ -0,0 +1,127 @@ +#[doc = "Register `OUTFIFO_STATUS_CH3` reader"] +pub type R = crate::R; +#[doc = "Field `OUTFIFO_FULL_L2_CH3` reader - Tx FIFO full signal for Tx channel 2."] +pub type OUTFIFO_FULL_L2_CH3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L2_CH3` reader - Tx FIFO empty signal for Tx channel 2."] +pub type OUTFIFO_EMPTY_L2_CH3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L2_CH3` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] +pub type OUTFIFO_CNT_L2_CH3_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_FULL_L1_CH3` reader - Tx FIFO full signal for Tx channel 2."] +pub type OUTFIFO_FULL_L1_CH3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L1_CH3` reader - Tx FIFO empty signal for Tx channel 2."] +pub type OUTFIFO_EMPTY_L1_CH3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L1_CH3` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] +pub type OUTFIFO_CNT_L1_CH3_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_FULL_L3_CH3` reader - Tx FIFO full signal for Tx channel 2."] +pub type OUTFIFO_FULL_L3_CH3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L3_CH3` reader - Tx FIFO empty signal for Tx channel 2."] +pub type OUTFIFO_EMPTY_L3_CH3_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L3_CH3` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] +pub type OUTFIFO_CNT_L3_CH3_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Tx FIFO full signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_full_l2_ch3(&self) -> OUTFIFO_FULL_L2_CH3_R { + OUTFIFO_FULL_L2_CH3_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tx FIFO empty signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_empty_l2_ch3(&self) -> OUTFIFO_EMPTY_L2_CH3_R { + OUTFIFO_EMPTY_L2_CH3_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] + #[inline(always)] + pub fn outfifo_cnt_l2_ch3(&self) -> OUTFIFO_CNT_L2_CH3_R { + OUTFIFO_CNT_L2_CH3_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - Tx FIFO full signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_full_l1_ch3(&self) -> OUTFIFO_FULL_L1_CH3_R { + OUTFIFO_FULL_L1_CH3_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tx FIFO empty signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_empty_l1_ch3(&self) -> OUTFIFO_EMPTY_L1_CH3_R { + OUTFIFO_EMPTY_L1_CH3_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] + #[inline(always)] + pub fn outfifo_cnt_l1_ch3(&self) -> OUTFIFO_CNT_L1_CH3_R { + OUTFIFO_CNT_L1_CH3_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Tx FIFO full signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_full_l3_ch3(&self) -> OUTFIFO_FULL_L3_CH3_R { + OUTFIFO_FULL_L3_CH3_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tx FIFO empty signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_empty_l3_ch3(&self) -> OUTFIFO_EMPTY_L3_CH3_R { + OUTFIFO_EMPTY_L3_CH3_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] + #[inline(always)] + pub fn outfifo_cnt_l3_ch3(&self) -> OUTFIFO_CNT_L3_CH3_R { + OUTFIFO_CNT_L3_CH3_R::new(((self.bits >> 18) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUTFIFO_STATUS_CH3") + .field( + "outfifo_full_l2_ch3", + &format_args!("{}", self.outfifo_full_l2_ch3().bit()), + ) + .field( + "outfifo_empty_l2_ch3", + &format_args!("{}", self.outfifo_empty_l2_ch3().bit()), + ) + .field( + "outfifo_cnt_l2_ch3", + &format_args!("{}", self.outfifo_cnt_l2_ch3().bits()), + ) + .field( + "outfifo_full_l1_ch3", + &format_args!("{}", self.outfifo_full_l1_ch3().bit()), + ) + .field( + "outfifo_empty_l1_ch3", + &format_args!("{}", self.outfifo_empty_l1_ch3().bit()), + ) + .field( + "outfifo_cnt_l1_ch3", + &format_args!("{}", self.outfifo_cnt_l1_ch3().bits()), + ) + .field( + "outfifo_full_l3_ch3", + &format_args!("{}", self.outfifo_full_l3_ch3().bit()), + ) + .field( + "outfifo_empty_l3_ch3", + &format_args!("{}", self.outfifo_empty_l3_ch3().bit()), + ) + .field( + "outfifo_cnt_l3_ch3", + &format_args!("{}", self.outfifo_cnt_l3_ch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH3 outfifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUTFIFO_STATUS_CH3_SPEC; +impl crate::RegisterSpec for OUTFIFO_STATUS_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`outfifo_status_ch3::R`](R) reader structure"] +impl crate::Readable for OUTFIFO_STATUS_CH3_SPEC {} +#[doc = "`reset()` method sets OUTFIFO_STATUS_CH3 to value 0x0002_0082"] +impl crate::Resettable for OUTFIFO_STATUS_CH3_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_0082; +} diff --git a/esp32p4/src/h264_dma/outfifo_status_ch4.rs b/esp32p4/src/h264_dma/outfifo_status_ch4.rs new file mode 100644 index 0000000000..7248b6e706 --- /dev/null +++ b/esp32p4/src/h264_dma/outfifo_status_ch4.rs @@ -0,0 +1,127 @@ +#[doc = "Register `OUTFIFO_STATUS_CH4` reader"] +pub type R = crate::R; +#[doc = "Field `OUTFIFO_FULL_L2_CH4` reader - Tx FIFO full signal for Tx channel 2."] +pub type OUTFIFO_FULL_L2_CH4_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L2_CH4` reader - Tx FIFO empty signal for Tx channel 2."] +pub type OUTFIFO_EMPTY_L2_CH4_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L2_CH4` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] +pub type OUTFIFO_CNT_L2_CH4_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_FULL_L1_CH4` reader - Tx FIFO full signal for Tx channel 2."] +pub type OUTFIFO_FULL_L1_CH4_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L1_CH4` reader - Tx FIFO empty signal for Tx channel 2."] +pub type OUTFIFO_EMPTY_L1_CH4_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L1_CH4` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] +pub type OUTFIFO_CNT_L1_CH4_R = crate::FieldReader; +#[doc = "Field `OUTFIFO_FULL_L3_CH4` reader - Tx FIFO full signal for Tx channel 2."] +pub type OUTFIFO_FULL_L3_CH4_R = crate::BitReader; +#[doc = "Field `OUTFIFO_EMPTY_L3_CH4` reader - Tx FIFO empty signal for Tx channel 2."] +pub type OUTFIFO_EMPTY_L3_CH4_R = crate::BitReader; +#[doc = "Field `OUTFIFO_CNT_L3_CH4` reader - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] +pub type OUTFIFO_CNT_L3_CH4_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Tx FIFO full signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_full_l2_ch4(&self) -> OUTFIFO_FULL_L2_CH4_R { + OUTFIFO_FULL_L2_CH4_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tx FIFO empty signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_empty_l2_ch4(&self) -> OUTFIFO_EMPTY_L2_CH4_R { + OUTFIFO_EMPTY_L2_CH4_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] + #[inline(always)] + pub fn outfifo_cnt_l2_ch4(&self) -> OUTFIFO_CNT_L2_CH4_R { + OUTFIFO_CNT_L2_CH4_R::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - Tx FIFO full signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_full_l1_ch4(&self) -> OUTFIFO_FULL_L1_CH4_R { + OUTFIFO_FULL_L1_CH4_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Tx FIFO empty signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_empty_l1_ch4(&self) -> OUTFIFO_EMPTY_L1_CH4_R { + OUTFIFO_EMPTY_L1_CH4_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] + #[inline(always)] + pub fn outfifo_cnt_l1_ch4(&self) -> OUTFIFO_CNT_L1_CH4_R { + OUTFIFO_CNT_L1_CH4_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Tx FIFO full signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_full_l3_ch4(&self) -> OUTFIFO_FULL_L3_CH4_R { + OUTFIFO_FULL_L3_CH4_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tx FIFO empty signal for Tx channel 2."] + #[inline(always)] + pub fn outfifo_empty_l3_ch4(&self) -> OUTFIFO_EMPTY_L3_CH4_R { + OUTFIFO_EMPTY_L3_CH4_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - The register stores the byte number of the data in Tx FIFO for Tx channel 2."] + #[inline(always)] + pub fn outfifo_cnt_l3_ch4(&self) -> OUTFIFO_CNT_L3_CH4_R { + OUTFIFO_CNT_L3_CH4_R::new(((self.bits >> 18) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUTFIFO_STATUS_CH4") + .field( + "outfifo_full_l2_ch4", + &format_args!("{}", self.outfifo_full_l2_ch4().bit()), + ) + .field( + "outfifo_empty_l2_ch4", + &format_args!("{}", self.outfifo_empty_l2_ch4().bit()), + ) + .field( + "outfifo_cnt_l2_ch4", + &format_args!("{}", self.outfifo_cnt_l2_ch4().bits()), + ) + .field( + "outfifo_full_l1_ch4", + &format_args!("{}", self.outfifo_full_l1_ch4().bit()), + ) + .field( + "outfifo_empty_l1_ch4", + &format_args!("{}", self.outfifo_empty_l1_ch4().bit()), + ) + .field( + "outfifo_cnt_l1_ch4", + &format_args!("{}", self.outfifo_cnt_l1_ch4().bits()), + ) + .field( + "outfifo_full_l3_ch4", + &format_args!("{}", self.outfifo_full_l3_ch4().bit()), + ) + .field( + "outfifo_empty_l3_ch4", + &format_args!("{}", self.outfifo_empty_l3_ch4().bit()), + ) + .field( + "outfifo_cnt_l3_ch4", + &format_args!("{}", self.outfifo_cnt_l3_ch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TX CH4 outfifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status_ch4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUTFIFO_STATUS_CH4_SPEC; +impl crate::RegisterSpec for OUTFIFO_STATUS_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`outfifo_status_ch4::R`](R) reader structure"] +impl crate::Readable for OUTFIFO_STATUS_CH4_SPEC {} +#[doc = "`reset()` method sets OUTFIFO_STATUS_CH4 to value 0x0002_0082"] +impl crate::Resettable for OUTFIFO_STATUS_CH4_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_0082; +} diff --git a/esp32p4/src/h264_dma/rst_conf.rs b/esp32p4/src/h264_dma/rst_conf.rs new file mode 100644 index 0000000000..2c438cde78 --- /dev/null +++ b/esp32p4/src/h264_dma/rst_conf.rs @@ -0,0 +1,139 @@ +#[doc = "Register `RST_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `RST_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `INTER_AXIM_RD_RST` reader - Write 1 then write 0 to this bit to reset axi master read data FIFO."] +pub type INTER_AXIM_RD_RST_R = crate::BitReader; +#[doc = "Field `INTER_AXIM_RD_RST` writer - Write 1 then write 0 to this bit to reset axi master read data FIFO."] +pub type INTER_AXIM_RD_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTER_AXIM_WR_RST` reader - Write 1 then write 0 to this bit to reset axi master write data FIFO."] +pub type INTER_AXIM_WR_RST_R = crate::BitReader; +#[doc = "Field `INTER_AXIM_WR_RST` writer - Write 1 then write 0 to this bit to reset axi master write data FIFO."] +pub type INTER_AXIM_WR_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXTER_AXIM_RD_RST` reader - Write 1 then write 0 to this bit to reset axi master read data FIFO."] +pub type EXTER_AXIM_RD_RST_R = crate::BitReader; +#[doc = "Field `EXTER_AXIM_RD_RST` writer - Write 1 then write 0 to this bit to reset axi master read data FIFO."] +pub type EXTER_AXIM_RD_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXTER_AXIM_WR_RST` reader - Write 1 then write 0 to this bit to reset axi master write data FIFO."] +pub type EXTER_AXIM_WR_RST_R = crate::BitReader; +#[doc = "Field `EXTER_AXIM_WR_RST` writer - Write 1 then write 0 to this bit to reset axi master write data FIFO."] +pub type EXTER_AXIM_WR_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 then write 0 to this bit to reset axi master read data FIFO."] + #[inline(always)] + pub fn inter_axim_rd_rst(&self) -> INTER_AXIM_RD_RST_R { + INTER_AXIM_RD_RST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 then write 0 to this bit to reset axi master write data FIFO."] + #[inline(always)] + pub fn inter_axim_wr_rst(&self) -> INTER_AXIM_WR_RST_R { + INTER_AXIM_WR_RST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 then write 0 to this bit to reset axi master read data FIFO."] + #[inline(always)] + pub fn exter_axim_rd_rst(&self) -> EXTER_AXIM_RD_RST_R { + EXTER_AXIM_RD_RST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1 then write 0 to this bit to reset axi master write data FIFO."] + #[inline(always)] + pub fn exter_axim_wr_rst(&self) -> EXTER_AXIM_WR_RST_R { + EXTER_AXIM_WR_RST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RST_CONF") + .field( + "inter_axim_rd_rst", + &format_args!("{}", self.inter_axim_rd_rst().bit()), + ) + .field( + "inter_axim_wr_rst", + &format_args!("{}", self.inter_axim_wr_rst().bit()), + ) + .field( + "exter_axim_rd_rst", + &format_args!("{}", self.exter_axim_rd_rst().bit()), + ) + .field( + "exter_axim_wr_rst", + &format_args!("{}", self.exter_axim_wr_rst().bit()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 then write 0 to this bit to reset axi master read data FIFO."] + #[inline(always)] + #[must_use] + pub fn inter_axim_rd_rst(&mut self) -> INTER_AXIM_RD_RST_W { + INTER_AXIM_RD_RST_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 then write 0 to this bit to reset axi master write data FIFO."] + #[inline(always)] + #[must_use] + pub fn inter_axim_wr_rst(&mut self) -> INTER_AXIM_WR_RST_W { + INTER_AXIM_WR_RST_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 then write 0 to this bit to reset axi master read data FIFO."] + #[inline(always)] + #[must_use] + pub fn exter_axim_rd_rst(&mut self) -> EXTER_AXIM_RD_RST_W { + EXTER_AXIM_RD_RST_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 then write 0 to this bit to reset axi master write data FIFO."] + #[inline(always)] + #[must_use] + pub fn exter_axim_wr_rst(&mut self) -> EXTER_AXIM_WR_RST_W { + EXTER_AXIM_WR_RST_W::new(self, 3) + } + #[doc = "Bit 4 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "axi reset config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RST_CONF_SPEC; +impl crate::RegisterSpec for RST_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rst_conf::R`](R) reader structure"] +impl crate::Readable for RST_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rst_conf::W`](W) writer structure"] +impl crate::Writable for RST_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RST_CONF to value 0"] +impl crate::Resettable for RST_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/rx_ch0_counter.rs b/esp32p4/src/h264_dma/rx_ch0_counter.rs new file mode 100644 index 0000000000..2b1fe5d527 --- /dev/null +++ b/esp32p4/src/h264_dma/rx_ch0_counter.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RX_CH0_COUNTER` reader"] +pub type R = crate::R; +#[doc = "Field `RX_CH0_CNT` reader - rx ch0 counter register"] +pub type RX_CH0_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:22 - rx ch0 counter register"] + #[inline(always)] + pub fn rx_ch0_cnt(&self) -> RX_CH0_CNT_R { + RX_CH0_CNT_R::new(self.bits & 0x007f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CH0_COUNTER") + .field("rx_ch0_cnt", &format_args!("{}", self.rx_ch0_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx ch0 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch0_counter::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CH0_COUNTER_SPEC; +impl crate::RegisterSpec for RX_CH0_COUNTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_ch0_counter::R`](R) reader structure"] +impl crate::Readable for RX_CH0_COUNTER_SPEC {} +#[doc = "`reset()` method sets RX_CH0_COUNTER to value 0"] +impl crate::Resettable for RX_CH0_COUNTER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/rx_ch1_counter.rs b/esp32p4/src/h264_dma/rx_ch1_counter.rs new file mode 100644 index 0000000000..07c31384d2 --- /dev/null +++ b/esp32p4/src/h264_dma/rx_ch1_counter.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RX_CH1_COUNTER` reader"] +pub type R = crate::R; +#[doc = "Field `RX_CH1_CNT` reader - rx ch1 counter register"] +pub type RX_CH1_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:20 - rx ch1 counter register"] + #[inline(always)] + pub fn rx_ch1_cnt(&self) -> RX_CH1_CNT_R { + RX_CH1_CNT_R::new(self.bits & 0x001f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CH1_COUNTER") + .field("rx_ch1_cnt", &format_args!("{}", self.rx_ch1_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx ch1 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch1_counter::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CH1_COUNTER_SPEC; +impl crate::RegisterSpec for RX_CH1_COUNTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_ch1_counter::R`](R) reader structure"] +impl crate::Readable for RX_CH1_COUNTER_SPEC {} +#[doc = "`reset()` method sets RX_CH1_COUNTER to value 0"] +impl crate::Resettable for RX_CH1_COUNTER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/rx_ch2_counter.rs b/esp32p4/src/h264_dma/rx_ch2_counter.rs new file mode 100644 index 0000000000..a1f345863b --- /dev/null +++ b/esp32p4/src/h264_dma/rx_ch2_counter.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RX_CH2_COUNTER` reader"] +pub type R = crate::R; +#[doc = "Field `RX_CH2_CNT` reader - rx ch2 counter register"] +pub type RX_CH2_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:10 - rx ch2 counter register"] + #[inline(always)] + pub fn rx_ch2_cnt(&self) -> RX_CH2_CNT_R { + RX_CH2_CNT_R::new((self.bits & 0x07ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CH2_COUNTER") + .field("rx_ch2_cnt", &format_args!("{}", self.rx_ch2_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx ch2 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch2_counter::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CH2_COUNTER_SPEC; +impl crate::RegisterSpec for RX_CH2_COUNTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_ch2_counter::R`](R) reader structure"] +impl crate::Readable for RX_CH2_COUNTER_SPEC {} +#[doc = "`reset()` method sets RX_CH2_COUNTER to value 0"] +impl crate::Resettable for RX_CH2_COUNTER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/h264_dma/rx_ch5_counter.rs b/esp32p4/src/h264_dma/rx_ch5_counter.rs new file mode 100644 index 0000000000..2bd84a91c8 --- /dev/null +++ b/esp32p4/src/h264_dma/rx_ch5_counter.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RX_CH5_COUNTER` reader"] +pub type R = crate::R; +#[doc = "Field `RX_CH5_CNT` reader - rx ch5 counter register"] +pub type RX_CH5_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - rx ch5 counter register"] + #[inline(always)] + pub fn rx_ch5_cnt(&self) -> RX_CH5_CNT_R { + RX_CH5_CNT_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CH5_COUNTER") + .field("rx_ch5_cnt", &format_args!("{}", self.rx_ch5_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rx ch5 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch5_counter::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CH5_COUNTER_SPEC; +impl crate::RegisterSpec for RX_CH5_COUNTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_ch5_counter::R`](R) reader structure"] +impl crate::Readable for RX_CH5_COUNTER_SPEC {} +#[doc = "`reset()` method sets RX_CH5_COUNTER to value 0"] +impl crate::Resettable for RX_CH5_COUNTER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac.rs b/esp32p4/src/hmac.rs new file mode 100644 index 0000000000..c5db36526d --- /dev/null +++ b/esp32p4/src/hmac.rs @@ -0,0 +1,201 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + _reserved0: [u8; 0x40], + set_start: SET_START, + set_para_purpose: SET_PARA_PURPOSE, + set_para_key: SET_PARA_KEY, + set_para_finish: SET_PARA_FINISH, + set_message_one: SET_MESSAGE_ONE, + set_message_ing: SET_MESSAGE_ING, + set_message_end: SET_MESSAGE_END, + set_result_finish: SET_RESULT_FINISH, + set_invalidate_jtag: SET_INVALIDATE_JTAG, + set_invalidate_ds: SET_INVALIDATE_DS, + query_error: QUERY_ERROR, + query_busy: QUERY_BUSY, + _reserved12: [u8; 0x10], + wr_message_mem: [WR_MESSAGE_MEM; 64], + rd_result_mem: [RD_RESULT_MEM; 32], + _reserved14: [u8; 0x10], + set_message_pad: SET_MESSAGE_PAD, + one_block: ONE_BLOCK, + soft_jtag_ctrl: SOFT_JTAG_CTRL, + wr_jtag: WR_JTAG, + _reserved18: [u8; 0xfc], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x40 - Process control register 0."] + #[inline(always)] + pub const fn set_start(&self) -> &SET_START { + &self.set_start + } + #[doc = "0x44 - Configure purpose."] + #[inline(always)] + pub const fn set_para_purpose(&self) -> &SET_PARA_PURPOSE { + &self.set_para_purpose + } + #[doc = "0x48 - Configure key."] + #[inline(always)] + pub const fn set_para_key(&self) -> &SET_PARA_KEY { + &self.set_para_key + } + #[doc = "0x4c - Finish initial configuration."] + #[inline(always)] + pub const fn set_para_finish(&self) -> &SET_PARA_FINISH { + &self.set_para_finish + } + #[doc = "0x50 - Process control register 1."] + #[inline(always)] + pub const fn set_message_one(&self) -> &SET_MESSAGE_ONE { + &self.set_message_one + } + #[doc = "0x54 - Process control register 2."] + #[inline(always)] + pub const fn set_message_ing(&self) -> &SET_MESSAGE_ING { + &self.set_message_ing + } + #[doc = "0x58 - Process control register 3."] + #[inline(always)] + pub const fn set_message_end(&self) -> &SET_MESSAGE_END { + &self.set_message_end + } + #[doc = "0x5c - Process control register 4."] + #[inline(always)] + pub const fn set_result_finish(&self) -> &SET_RESULT_FINISH { + &self.set_result_finish + } + #[doc = "0x60 - Invalidate register 0."] + #[inline(always)] + pub const fn set_invalidate_jtag(&self) -> &SET_INVALIDATE_JTAG { + &self.set_invalidate_jtag + } + #[doc = "0x64 - Invalidate register 1."] + #[inline(always)] + pub const fn set_invalidate_ds(&self) -> &SET_INVALIDATE_DS { + &self.set_invalidate_ds + } + #[doc = "0x68 - Error register."] + #[inline(always)] + pub const fn query_error(&self) -> &QUERY_ERROR { + &self.query_error + } + #[doc = "0x6c - Busy register."] + #[inline(always)] + pub const fn query_busy(&self) -> &QUERY_BUSY { + &self.query_busy + } + #[doc = "0x80..0xc0 - Message block memory."] + #[inline(always)] + pub const fn wr_message_mem(&self, n: usize) -> &WR_MESSAGE_MEM { + &self.wr_message_mem[n] + } + #[doc = "0xc0..0xe0 - Result from upstream."] + #[inline(always)] + pub const fn rd_result_mem(&self, n: usize) -> &RD_RESULT_MEM { + &self.rd_result_mem[n] + } + #[doc = "0xf0 - Process control register 5."] + #[inline(always)] + pub const fn set_message_pad(&self) -> &SET_MESSAGE_PAD { + &self.set_message_pad + } + #[doc = "0xf4 - Process control register 6."] + #[inline(always)] + pub const fn one_block(&self) -> &ONE_BLOCK { + &self.one_block + } + #[doc = "0xf8 - Jtag register 0."] + #[inline(always)] + pub const fn soft_jtag_ctrl(&self) -> &SOFT_JTAG_CTRL { + &self.soft_jtag_ctrl + } + #[doc = "0xfc - Jtag register 1."] + #[inline(always)] + pub const fn wr_jtag(&self) -> &WR_JTAG { + &self.wr_jtag + } + #[doc = "0x1fc - Date register."] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "SET_START (w) register accessor: Process control register 0.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_start::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_start`] module"] +pub type SET_START = crate::Reg; +#[doc = "Process control register 0."] +pub mod set_start; +#[doc = "SET_PARA_PURPOSE (w) register accessor: Configure purpose.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_para_purpose::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_para_purpose`] module"] +pub type SET_PARA_PURPOSE = crate::Reg; +#[doc = "Configure purpose."] +pub mod set_para_purpose; +#[doc = "SET_PARA_KEY (w) register accessor: Configure key.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_para_key::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_para_key`] module"] +pub type SET_PARA_KEY = crate::Reg; +#[doc = "Configure key."] +pub mod set_para_key; +#[doc = "SET_PARA_FINISH (w) register accessor: Finish initial configuration.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_para_finish::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_para_finish`] module"] +pub type SET_PARA_FINISH = crate::Reg; +#[doc = "Finish initial configuration."] +pub mod set_para_finish; +#[doc = "SET_MESSAGE_ONE (w) register accessor: Process control register 1.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_message_one::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_message_one`] module"] +pub type SET_MESSAGE_ONE = crate::Reg; +#[doc = "Process control register 1."] +pub mod set_message_one; +#[doc = "SET_MESSAGE_ING (w) register accessor: Process control register 2.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_message_ing::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_message_ing`] module"] +pub type SET_MESSAGE_ING = crate::Reg; +#[doc = "Process control register 2."] +pub mod set_message_ing; +#[doc = "SET_MESSAGE_END (w) register accessor: Process control register 3.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_message_end::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_message_end`] module"] +pub type SET_MESSAGE_END = crate::Reg; +#[doc = "Process control register 3."] +pub mod set_message_end; +#[doc = "SET_RESULT_FINISH (w) register accessor: Process control register 4.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_result_finish::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_result_finish`] module"] +pub type SET_RESULT_FINISH = crate::Reg; +#[doc = "Process control register 4."] +pub mod set_result_finish; +#[doc = "SET_INVALIDATE_JTAG (w) register accessor: Invalidate register 0.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_invalidate_jtag::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_invalidate_jtag`] module"] +pub type SET_INVALIDATE_JTAG = crate::Reg; +#[doc = "Invalidate register 0."] +pub mod set_invalidate_jtag; +#[doc = "SET_INVALIDATE_DS (w) register accessor: Invalidate register 1.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_invalidate_ds::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_invalidate_ds`] module"] +pub type SET_INVALIDATE_DS = crate::Reg; +#[doc = "Invalidate register 1."] +pub mod set_invalidate_ds; +#[doc = "QUERY_ERROR (r) register accessor: Error register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_error::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@query_error`] module"] +pub type QUERY_ERROR = crate::Reg; +#[doc = "Error register."] +pub mod query_error; +#[doc = "QUERY_BUSY (r) register accessor: Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@query_busy`] module"] +pub type QUERY_BUSY = crate::Reg; +#[doc = "Busy register."] +pub mod query_busy; +#[doc = "WR_MESSAGE_MEM (rw) register accessor: Message block memory.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_message_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_message_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wr_message_mem`] module"] +pub type WR_MESSAGE_MEM = crate::Reg; +#[doc = "Message block memory."] +pub mod wr_message_mem; +#[doc = "RD_RESULT_MEM (rw) register accessor: Result from upstream.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_result_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_result_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_result_mem`] module"] +pub type RD_RESULT_MEM = crate::Reg; +#[doc = "Result from upstream."] +pub mod rd_result_mem; +#[doc = "SET_MESSAGE_PAD (w) register accessor: Process control register 5.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_message_pad::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_message_pad`] module"] +pub type SET_MESSAGE_PAD = crate::Reg; +#[doc = "Process control register 5."] +pub mod set_message_pad; +#[doc = "ONE_BLOCK (w) register accessor: Process control register 6.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`one_block::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@one_block`] module"] +pub type ONE_BLOCK = crate::Reg; +#[doc = "Process control register 6."] +pub mod one_block; +#[doc = "SOFT_JTAG_CTRL (w) register accessor: Jtag register 0.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_jtag_ctrl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_jtag_ctrl`] module"] +pub type SOFT_JTAG_CTRL = crate::Reg; +#[doc = "Jtag register 0."] +pub mod soft_jtag_ctrl; +#[doc = "WR_JTAG (w) register accessor: Jtag register 1.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_jtag::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wr_jtag`] module"] +pub type WR_JTAG = crate::Reg; +#[doc = "Jtag register 1."] +pub mod wr_jtag; +#[doc = "DATE (rw) register accessor: Date register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Date register."] +pub mod date; diff --git a/esp32p4/src/hmac/date.rs b/esp32p4/src/hmac/date.rs new file mode 100644 index 0000000000..d376dea075 --- /dev/null +++ b/esp32p4/src/hmac/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - Hmac date information/ hmac version information."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - Hmac date information/ hmac version information."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 0:29 - Hmac date information/ hmac version information."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x3fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:29 - Hmac date information/ hmac version information."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Date register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x2020_0618"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2020_0618; +} diff --git a/esp32p4/src/hmac/one_block.rs b/esp32p4/src/hmac/one_block.rs new file mode 100644 index 0000000000..6551b2f205 --- /dev/null +++ b/esp32p4/src/hmac/one_block.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ONE_BLOCK` writer"] +pub type W = crate::W; +#[doc = "Field `SET_ONE_BLOCK` writer - Don't have to do padding."] +pub type SET_ONE_BLOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Don't have to do padding."] + #[inline(always)] + #[must_use] + pub fn set_one_block(&mut self) -> SET_ONE_BLOCK_W { + SET_ONE_BLOCK_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Process control register 6.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`one_block::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ONE_BLOCK_SPEC; +impl crate::RegisterSpec for ONE_BLOCK_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`one_block::W`](W) writer structure"] +impl crate::Writable for ONE_BLOCK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ONE_BLOCK to value 0"] +impl crate::Resettable for ONE_BLOCK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/query_busy.rs b/esp32p4/src/hmac/query_busy.rs new file mode 100644 index 0000000000..a12aeba724 --- /dev/null +++ b/esp32p4/src/hmac/query_busy.rs @@ -0,0 +1,36 @@ +#[doc = "Register `QUERY_BUSY` reader"] +pub type R = crate::R; +#[doc = "Field `BUSY_STATE` reader - Hmac state. 1'b0: idle. 1'b1: busy"] +pub type BUSY_STATE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Hmac state. 1'b0: idle. 1'b1: busy"] + #[inline(always)] + pub fn busy_state(&self) -> BUSY_STATE_R { + BUSY_STATE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("QUERY_BUSY") + .field("busy_state", &format_args!("{}", self.busy_state().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QUERY_BUSY_SPEC; +impl crate::RegisterSpec for QUERY_BUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`query_busy::R`](R) reader structure"] +impl crate::Readable for QUERY_BUSY_SPEC {} +#[doc = "`reset()` method sets QUERY_BUSY to value 0"] +impl crate::Resettable for QUERY_BUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/query_error.rs b/esp32p4/src/hmac/query_error.rs new file mode 100644 index 0000000000..026e4675b8 --- /dev/null +++ b/esp32p4/src/hmac/query_error.rs @@ -0,0 +1,36 @@ +#[doc = "Register `QUERY_ERROR` reader"] +pub type R = crate::R; +#[doc = "Field `QUERY_CHECK` reader - Hmac configuration state. 0: key are agree with purpose. 1: error"] +pub type QUERY_CHECK_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Hmac configuration state. 0: key are agree with purpose. 1: error"] + #[inline(always)] + pub fn query_check(&self) -> QUERY_CHECK_R { + QUERY_CHECK_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("QUERY_ERROR") + .field("query_check", &format_args!("{}", self.query_check().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Error register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_error::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QUERY_ERROR_SPEC; +impl crate::RegisterSpec for QUERY_ERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`query_error::R`](R) reader structure"] +impl crate::Readable for QUERY_ERROR_SPEC {} +#[doc = "`reset()` method sets QUERY_ERROR to value 0"] +impl crate::Resettable for QUERY_ERROR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/rd_result_mem.rs b/esp32p4/src/hmac/rd_result_mem.rs new file mode 100644 index 0000000000..7cf7d2a0ba --- /dev/null +++ b/esp32p4/src/hmac/rd_result_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `RD_RESULT_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `RD_RESULT_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Result from upstream.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_result_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_result_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RD_RESULT_MEM_SPEC; +impl crate::RegisterSpec for RD_RESULT_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`rd_result_mem::R`](R) reader structure"] +impl crate::Readable for RD_RESULT_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rd_result_mem::W`](W) writer structure"] +impl crate::Writable for RD_RESULT_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RD_RESULT_MEM[%s] to value 0"] +impl crate::Resettable for RD_RESULT_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/set_invalidate_ds.rs b/esp32p4/src/hmac/set_invalidate_ds.rs new file mode 100644 index 0000000000..a6d7d2fe1a --- /dev/null +++ b/esp32p4/src/hmac/set_invalidate_ds.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_INVALIDATE_DS` writer"] +pub type W = crate::W; +#[doc = "Field `SET_INVALIDATE_DS` writer - Clear result from hmac downstream DS."] +pub type SET_INVALIDATE_DS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Clear result from hmac downstream DS."] + #[inline(always)] + #[must_use] + pub fn set_invalidate_ds(&mut self) -> SET_INVALIDATE_DS_W { + SET_INVALIDATE_DS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Invalidate register 1.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_invalidate_ds::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_INVALIDATE_DS_SPEC; +impl crate::RegisterSpec for SET_INVALIDATE_DS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_invalidate_ds::W`](W) writer structure"] +impl crate::Writable for SET_INVALIDATE_DS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_INVALIDATE_DS to value 0"] +impl crate::Resettable for SET_INVALIDATE_DS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/set_invalidate_jtag.rs b/esp32p4/src/hmac/set_invalidate_jtag.rs new file mode 100644 index 0000000000..e356bafdae --- /dev/null +++ b/esp32p4/src/hmac/set_invalidate_jtag.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_INVALIDATE_JTAG` writer"] +pub type W = crate::W; +#[doc = "Field `SET_INVALIDATE_JTAG` writer - Clear result from hmac downstream JTAG."] +pub type SET_INVALIDATE_JTAG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Clear result from hmac downstream JTAG."] + #[inline(always)] + #[must_use] + pub fn set_invalidate_jtag(&mut self) -> SET_INVALIDATE_JTAG_W { + SET_INVALIDATE_JTAG_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Invalidate register 0.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_invalidate_jtag::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_INVALIDATE_JTAG_SPEC; +impl crate::RegisterSpec for SET_INVALIDATE_JTAG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_invalidate_jtag::W`](W) writer structure"] +impl crate::Writable for SET_INVALIDATE_JTAG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_INVALIDATE_JTAG to value 0"] +impl crate::Resettable for SET_INVALIDATE_JTAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/set_message_end.rs b/esp32p4/src/hmac/set_message_end.rs new file mode 100644 index 0000000000..37aa3d9b0b --- /dev/null +++ b/esp32p4/src/hmac/set_message_end.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_MESSAGE_END` writer"] +pub type W = crate::W; +#[doc = "Field `SET_TEXT_END` writer - Start hardware padding."] +pub type SET_TEXT_END_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Start hardware padding."] + #[inline(always)] + #[must_use] + pub fn set_text_end(&mut self) -> SET_TEXT_END_W { + SET_TEXT_END_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Process control register 3.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_message_end::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_MESSAGE_END_SPEC; +impl crate::RegisterSpec for SET_MESSAGE_END_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_message_end::W`](W) writer structure"] +impl crate::Writable for SET_MESSAGE_END_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_MESSAGE_END to value 0"] +impl crate::Resettable for SET_MESSAGE_END_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/set_message_ing.rs b/esp32p4/src/hmac/set_message_ing.rs new file mode 100644 index 0000000000..0a27e7272e --- /dev/null +++ b/esp32p4/src/hmac/set_message_ing.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_MESSAGE_ING` writer"] +pub type W = crate::W; +#[doc = "Field `SET_TEXT_ING` writer - Continue typical hmac."] +pub type SET_TEXT_ING_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Continue typical hmac."] + #[inline(always)] + #[must_use] + pub fn set_text_ing(&mut self) -> SET_TEXT_ING_W { + SET_TEXT_ING_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Process control register 2.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_message_ing::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_MESSAGE_ING_SPEC; +impl crate::RegisterSpec for SET_MESSAGE_ING_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_message_ing::W`](W) writer structure"] +impl crate::Writable for SET_MESSAGE_ING_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_MESSAGE_ING to value 0"] +impl crate::Resettable for SET_MESSAGE_ING_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/set_message_one.rs b/esp32p4/src/hmac/set_message_one.rs new file mode 100644 index 0000000000..7ef543a005 --- /dev/null +++ b/esp32p4/src/hmac/set_message_one.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_MESSAGE_ONE` writer"] +pub type W = crate::W; +#[doc = "Field `SET_TEXT_ONE` writer - Call SHA to calculate one message block."] +pub type SET_TEXT_ONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Call SHA to calculate one message block."] + #[inline(always)] + #[must_use] + pub fn set_text_one(&mut self) -> SET_TEXT_ONE_W { + SET_TEXT_ONE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Process control register 1.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_message_one::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_MESSAGE_ONE_SPEC; +impl crate::RegisterSpec for SET_MESSAGE_ONE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_message_one::W`](W) writer structure"] +impl crate::Writable for SET_MESSAGE_ONE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_MESSAGE_ONE to value 0"] +impl crate::Resettable for SET_MESSAGE_ONE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/set_message_pad.rs b/esp32p4/src/hmac/set_message_pad.rs new file mode 100644 index 0000000000..6e79aac507 --- /dev/null +++ b/esp32p4/src/hmac/set_message_pad.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_MESSAGE_PAD` writer"] +pub type W = crate::W; +#[doc = "Field `SET_TEXT_PAD` writer - Start software padding."] +pub type SET_TEXT_PAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Start software padding."] + #[inline(always)] + #[must_use] + pub fn set_text_pad(&mut self) -> SET_TEXT_PAD_W { + SET_TEXT_PAD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Process control register 5.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_message_pad::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_MESSAGE_PAD_SPEC; +impl crate::RegisterSpec for SET_MESSAGE_PAD_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_message_pad::W`](W) writer structure"] +impl crate::Writable for SET_MESSAGE_PAD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_MESSAGE_PAD to value 0"] +impl crate::Resettable for SET_MESSAGE_PAD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/set_para_finish.rs b/esp32p4/src/hmac/set_para_finish.rs new file mode 100644 index 0000000000..16302b4172 --- /dev/null +++ b/esp32p4/src/hmac/set_para_finish.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_PARA_FINISH` writer"] +pub type W = crate::W; +#[doc = "Field `SET_PARA_END` writer - Finish hmac configuration."] +pub type SET_PARA_END_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Finish hmac configuration."] + #[inline(always)] + #[must_use] + pub fn set_para_end(&mut self) -> SET_PARA_END_W { + SET_PARA_END_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Finish initial configuration.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_para_finish::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_PARA_FINISH_SPEC; +impl crate::RegisterSpec for SET_PARA_FINISH_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_para_finish::W`](W) writer structure"] +impl crate::Writable for SET_PARA_FINISH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_PARA_FINISH to value 0"] +impl crate::Resettable for SET_PARA_FINISH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/set_para_key.rs b/esp32p4/src/hmac/set_para_key.rs new file mode 100644 index 0000000000..77a2ad3e01 --- /dev/null +++ b/esp32p4/src/hmac/set_para_key.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_PARA_KEY` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_SET` writer - Set hmac parameter key."] +pub type KEY_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:2 - Set hmac parameter key."] + #[inline(always)] + #[must_use] + pub fn key_set(&mut self) -> KEY_SET_W { + KEY_SET_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure key.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_para_key::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_PARA_KEY_SPEC; +impl crate::RegisterSpec for SET_PARA_KEY_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_para_key::W`](W) writer structure"] +impl crate::Writable for SET_PARA_KEY_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_PARA_KEY to value 0"] +impl crate::Resettable for SET_PARA_KEY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/set_para_purpose.rs b/esp32p4/src/hmac/set_para_purpose.rs new file mode 100644 index 0000000000..e7faa4f444 --- /dev/null +++ b/esp32p4/src/hmac/set_para_purpose.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_PARA_PURPOSE` writer"] +pub type W = crate::W; +#[doc = "Field `PURPOSE_SET` writer - Set hmac parameter purpose."] +pub type PURPOSE_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:3 - Set hmac parameter purpose."] + #[inline(always)] + #[must_use] + pub fn purpose_set(&mut self) -> PURPOSE_SET_W { + PURPOSE_SET_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure purpose.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_para_purpose::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_PARA_PURPOSE_SPEC; +impl crate::RegisterSpec for SET_PARA_PURPOSE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_para_purpose::W`](W) writer structure"] +impl crate::Writable for SET_PARA_PURPOSE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_PARA_PURPOSE to value 0"] +impl crate::Resettable for SET_PARA_PURPOSE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/set_result_finish.rs b/esp32p4/src/hmac/set_result_finish.rs new file mode 100644 index 0000000000..e310833d72 --- /dev/null +++ b/esp32p4/src/hmac/set_result_finish.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_RESULT_FINISH` writer"] +pub type W = crate::W; +#[doc = "Field `SET_RESULT_END` writer - After read result from upstream, then let hmac back to idle."] +pub type SET_RESULT_END_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - After read result from upstream, then let hmac back to idle."] + #[inline(always)] + #[must_use] + pub fn set_result_end(&mut self) -> SET_RESULT_END_W { + SET_RESULT_END_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Process control register 4.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_result_finish::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_RESULT_FINISH_SPEC; +impl crate::RegisterSpec for SET_RESULT_FINISH_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_result_finish::W`](W) writer structure"] +impl crate::Writable for SET_RESULT_FINISH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_RESULT_FINISH to value 0"] +impl crate::Resettable for SET_RESULT_FINISH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/set_start.rs b/esp32p4/src/hmac/set_start.rs new file mode 100644 index 0000000000..0acb96a0fe --- /dev/null +++ b/esp32p4/src/hmac/set_start.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_START` writer"] +pub type W = crate::W; +#[doc = "Field `SET_START` writer - Start hmac operation."] +pub type SET_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Start hmac operation."] + #[inline(always)] + #[must_use] + pub fn set_start(&mut self) -> SET_START_W { + SET_START_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Process control register 0.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_start::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_START_SPEC; +impl crate::RegisterSpec for SET_START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_start::W`](W) writer structure"] +impl crate::Writable for SET_START_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_START to value 0"] +impl crate::Resettable for SET_START_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/soft_jtag_ctrl.rs b/esp32p4/src/hmac/soft_jtag_ctrl.rs new file mode 100644 index 0000000000..b60eeaeecd --- /dev/null +++ b/esp32p4/src/hmac/soft_jtag_ctrl.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SOFT_JTAG_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SOFT_JTAG_CTRL` writer - Turn on JTAG verification."] +pub type SOFT_JTAG_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Turn on JTAG verification."] + #[inline(always)] + #[must_use] + pub fn soft_jtag_ctrl(&mut self) -> SOFT_JTAG_CTRL_W { + SOFT_JTAG_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Jtag register 0.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soft_jtag_ctrl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOFT_JTAG_CTRL_SPEC; +impl crate::RegisterSpec for SOFT_JTAG_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`soft_jtag_ctrl::W`](W) writer structure"] +impl crate::Writable for SOFT_JTAG_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SOFT_JTAG_CTRL to value 0"] +impl crate::Resettable for SOFT_JTAG_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/wr_jtag.rs b/esp32p4/src/hmac/wr_jtag.rs new file mode 100644 index 0000000000..6afc939750 --- /dev/null +++ b/esp32p4/src/hmac/wr_jtag.rs @@ -0,0 +1,42 @@ +#[doc = "Register `WR_JTAG` writer"] +pub type W = crate::W; +#[doc = "Field `WR_JTAG` writer - 32-bit of key to be compared."] +pub type WR_JTAG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - 32-bit of key to be compared."] + #[inline(always)] + #[must_use] + pub fn wr_jtag(&mut self) -> WR_JTAG_W { + WR_JTAG_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Jtag register 1.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_jtag::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WR_JTAG_SPEC; +impl crate::RegisterSpec for WR_JTAG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`wr_jtag::W`](W) writer structure"] +impl crate::Writable for WR_JTAG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WR_JTAG to value 0"] +impl crate::Resettable for WR_JTAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hmac/wr_message_mem.rs b/esp32p4/src/hmac/wr_message_mem.rs new file mode 100644 index 0000000000..8961075a44 --- /dev/null +++ b/esp32p4/src/hmac/wr_message_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `WR_MESSAGE_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `WR_MESSAGE_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Message block memory.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_message_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_message_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WR_MESSAGE_MEM_SPEC; +impl crate::RegisterSpec for WR_MESSAGE_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`wr_message_mem::R`](R) reader structure"] +impl crate::Readable for WR_MESSAGE_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wr_message_mem::W`](W) writer structure"] +impl crate::Writable for WR_MESSAGE_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WR_MESSAGE_MEM[%s] to value 0"] +impl crate::Resettable for WR_MESSAGE_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys.rs b/esp32p4/src/hp_sys.rs new file mode 100644 index 0000000000..6cd2f60592 --- /dev/null +++ b/esp32p4/src/hp_sys.rs @@ -0,0 +1,952 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + ver_date: VER_DATE, + hp_clk_en: HP_CLK_EN, + _reserved2: [u8; 0x08], + hp_cpu_int_from_cpu_0: HP_CPU_INT_FROM_CPU_0, + hp_cpu_int_from_cpu_1: HP_CPU_INT_FROM_CPU_1, + hp_cpu_int_from_cpu_2: HP_CPU_INT_FROM_CPU_2, + hp_cpu_int_from_cpu_3: HP_CPU_INT_FROM_CPU_3, + hp_cache_clk_config: HP_CACHE_CLK_CONFIG, + hp_cache_reset_config: HP_CACHE_RESET_CONFIG, + _reserved8: [u8; 0x04], + dma_addr_ctrl: DMA_ADDR_CTRL, + _reserved9: [u8; 0x04], + hp_tcm_ram_wrr_config: HP_TCM_RAM_WRR_CONFIG, + hp_tcm_sw_parity_bwe_mask: HP_TCM_SW_PARITY_BWE_MASK, + hp_tcm_ram_pwr_ctrl0: HP_TCM_RAM_PWR_CTRL0, + hp_l2_rom_pwr_ctrl0: HP_L2_ROM_PWR_CTRL0, + _reserved13: [u8; 0x0c], + hp_probea_ctrl: HP_PROBEA_CTRL, + hp_probeb_ctrl: HP_PROBEB_CTRL, + _reserved15: [u8; 0x04], + hp_probe_out: HP_PROBE_OUT, + hp_l2_mem_ram_pwr_ctrl0: HP_L2_MEM_RAM_PWR_CTRL0, + hp_cpu_corestalled_st: HP_CPU_CORESTALLED_ST, + _reserved18: [u8; 0x08], + hp_crypto_ctrl: HP_CRYPTO_CTRL, + hp_gpio_o_hold_ctrl0: HP_GPIO_O_HOLD_CTRL0, + hp_gpio_o_hold_ctrl1: HP_GPIO_O_HOLD_CTRL1, + rdn_eco_cs: RDN_ECO_CS, + hp_cache_apb_postw_en: HP_CACHE_APB_POSTW_EN, + hp_l2_mem_subsize: HP_L2_MEM_SUBSIZE, + _reserved24: [u8; 0x14], + hp_l2_mem_int_raw: HP_L2_MEM_INT_RAW, + hp_l2_mem_int_st: HP_L2_MEM_INT_ST, + hp_l2_mem_int_ena: HP_L2_MEM_INT_ENA, + hp_l2_mem_int_clr: HP_L2_MEM_INT_CLR, + hp_l2_mem_l2_ram_ecc: HP_L2_MEM_L2_RAM_ECC, + hp_l2_mem_int_record0: HP_L2_MEM_INT_RECORD0, + hp_l2_mem_int_record1: HP_L2_MEM_INT_RECORD1, + _reserved31: [u8; 0x0c], + hp_l2_mem_l2_cache_ecc: HP_L2_MEM_L2_CACHE_ECC, + hp_l1cache_bus0_id: HP_L1CACHE_BUS0_ID, + hp_l1cache_bus1_id: HP_L1CACHE_BUS1_ID, + _reserved34: [u8; 0x08], + hp_l2_mem_rdn_eco_cs: HP_L2_MEM_RDN_ECO_CS, + hp_l2_mem_rdn_eco_low: HP_L2_MEM_RDN_ECO_LOW, + hp_l2_mem_rdn_eco_high: HP_L2_MEM_RDN_ECO_HIGH, + hp_tcm_rdn_eco_cs: HP_TCM_RDN_ECO_CS, + hp_tcm_rdn_eco_low: HP_TCM_RDN_ECO_LOW, + hp_tcm_rdn_eco_high: HP_TCM_RDN_ECO_HIGH, + hp_gpio_ded_hold_ctrl: HP_GPIO_DED_HOLD_CTRL, + hp_l2_mem_sw_ecc_bwe_mask: HP_L2_MEM_SW_ECC_BWE_MASK, + hp_usb20otg_mem_ctrl: HP_USB20OTG_MEM_CTRL, + hp_tcm_int_raw: HP_TCM_INT_RAW, + hp_tcm_int_st: HP_TCM_INT_ST, + hp_tcm_int_ena: HP_TCM_INT_ENA, + hp_tcm_int_clr: HP_TCM_INT_CLR, + hp_tcm_parity_int_record: HP_TCM_PARITY_INT_RECORD, + hp_l1_cache_pwr_ctrl: HP_L1_CACHE_PWR_CTRL, + hp_l2_cache_pwr_ctrl: HP_L2_CACHE_PWR_CTRL, + hp_cpu_waiti_conf: HP_CPU_WAITI_CONF, + core_debug_runstall_conf: CORE_DEBUG_RUNSTALL_CONF, + hp_core_ahb_timeout: HP_CORE_AHB_TIMEOUT, + hp_core_ibus_timeout: HP_CORE_IBUS_TIMEOUT, + hp_core_dbus_timeout: HP_CORE_DBUS_TIMEOUT, + _reserved55: [u8; 0x0c], + hp_icm_cpu_h2x_cfg: HP_ICM_CPU_H2X_CFG, + hp_peri1_apb_postw_en: HP_PERI1_APB_POSTW_EN, + hp_bitscrambler_peri_sel: HP_BITSCRAMBLER_PERI_SEL, + apb_sync_postw_en: APB_SYNC_POSTW_EN, + gdma_ctrl: GDMA_CTRL, + gmac_ctrl0: GMAC_CTRL0, + gmac_ctrl1: GMAC_CTRL1, + gmac_ctrl2: GMAC_CTRL2, + vpu_ctrl: VPU_CTRL, + usbotg20_ctrl: USBOTG20_CTRL, + hp_tcm_err_resp_ctrl: HP_TCM_ERR_RESP_CTRL, + hp_l2_mem_refresh: HP_L2_MEM_REFRESH, + hp_tcm_init: HP_TCM_INIT, + hp_tcm_parity_check_ctrl: HP_TCM_PARITY_CHECK_CTRL, + hp_design_for_verification0: HP_DESIGN_FOR_VERIFICATION0, + hp_design_for_verification1: HP_DESIGN_FOR_VERIFICATION1, + _reserved71: [u8; 0x08], + hp_psram_flash_addr_interchange: HP_PSRAM_FLASH_ADDR_INTERCHANGE, + _reserved72: [u8; 0x04], + hp_ahb2axi_bresp_err_int_raw: HP_AHB2AXI_BRESP_ERR_INT_RAW, + hp_ahb2axi_bresp_err_int_st: HP_AHB2AXI_BRESP_ERR_INT_ST, + hp_ahb2axi_bresp_err_int_ena: HP_AHB2AXI_BRESP_ERR_INT_ENA, + hp_ahb2axi_bresp_err_int_clr: HP_AHB2AXI_BRESP_ERR_INT_CLR, + hp_l2_mem_err_resp_ctrl: HP_L2_MEM_ERR_RESP_CTRL, + hp_l2_mem_ahb_buffer_ctrl: HP_L2_MEM_AHB_BUFFER_CTRL, + hp_core_dmactive_lpcore: HP_CORE_DMACTIVE_LPCORE, + hp_core_err_resp_dis: HP_CORE_ERR_RESP_DIS, + hp_core_timeout_int_raw: HP_CORE_TIMEOUT_INT_RAW, + hp_core_timeout_int_st: HP_CORE_TIMEOUT_INT_ST, + hp_core_timeout_int_ena: HP_CORE_TIMEOUT_INT_ENA, + hp_core_timeout_int_clr: HP_CORE_TIMEOUT_INT_CLR, + _reserved84: [u8; 0x08], + hp_gpio_o_hys_ctrl0: HP_GPIO_O_HYS_CTRL0, + hp_gpio_o_hys_ctrl1: HP_GPIO_O_HYS_CTRL1, + _reserved86: [u8; 0x08], + hp_rsa_pd_ctrl: HP_RSA_PD_CTRL, + hp_ecc_pd_ctrl: HP_ECC_PD_CTRL, + hp_rng_cfg: HP_RNG_CFG, + hp_uart_pd_ctrl: HP_UART_PD_CTRL, + hp_peri_mem_clk_force_on: HP_PERI_MEM_CLK_FORCE_ON, +} +impl RegisterBlock { + #[doc = "0x00 - NA"] + #[inline(always)] + pub const fn ver_date(&self) -> &VER_DATE { + &self.ver_date + } + #[doc = "0x04 - NA"] + #[inline(always)] + pub const fn hp_clk_en(&self) -> &HP_CLK_EN { + &self.hp_clk_en + } + #[doc = "0x10 - NA"] + #[inline(always)] + pub const fn hp_cpu_int_from_cpu_0(&self) -> &HP_CPU_INT_FROM_CPU_0 { + &self.hp_cpu_int_from_cpu_0 + } + #[doc = "0x14 - NA"] + #[inline(always)] + pub const fn hp_cpu_int_from_cpu_1(&self) -> &HP_CPU_INT_FROM_CPU_1 { + &self.hp_cpu_int_from_cpu_1 + } + #[doc = "0x18 - NA"] + #[inline(always)] + pub const fn hp_cpu_int_from_cpu_2(&self) -> &HP_CPU_INT_FROM_CPU_2 { + &self.hp_cpu_int_from_cpu_2 + } + #[doc = "0x1c - NA"] + #[inline(always)] + pub const fn hp_cpu_int_from_cpu_3(&self) -> &HP_CPU_INT_FROM_CPU_3 { + &self.hp_cpu_int_from_cpu_3 + } + #[doc = "0x20 - NA"] + #[inline(always)] + pub const fn hp_cache_clk_config(&self) -> &HP_CACHE_CLK_CONFIG { + &self.hp_cache_clk_config + } + #[doc = "0x24 - NA"] + #[inline(always)] + pub const fn hp_cache_reset_config(&self) -> &HP_CACHE_RESET_CONFIG { + &self.hp_cache_reset_config + } + #[doc = "0x2c - NA"] + #[inline(always)] + pub const fn dma_addr_ctrl(&self) -> &DMA_ADDR_CTRL { + &self.dma_addr_ctrl + } + #[doc = "0x34 - NA"] + #[inline(always)] + pub const fn hp_tcm_ram_wrr_config(&self) -> &HP_TCM_RAM_WRR_CONFIG { + &self.hp_tcm_ram_wrr_config + } + #[doc = "0x38 - NA"] + #[inline(always)] + pub const fn hp_tcm_sw_parity_bwe_mask(&self) -> &HP_TCM_SW_PARITY_BWE_MASK { + &self.hp_tcm_sw_parity_bwe_mask + } + #[doc = "0x3c - NA"] + #[inline(always)] + pub const fn hp_tcm_ram_pwr_ctrl0(&self) -> &HP_TCM_RAM_PWR_CTRL0 { + &self.hp_tcm_ram_pwr_ctrl0 + } + #[doc = "0x40 - NA"] + #[inline(always)] + pub const fn hp_l2_rom_pwr_ctrl0(&self) -> &HP_L2_ROM_PWR_CTRL0 { + &self.hp_l2_rom_pwr_ctrl0 + } + #[doc = "0x50 - NA"] + #[inline(always)] + pub const fn hp_probea_ctrl(&self) -> &HP_PROBEA_CTRL { + &self.hp_probea_ctrl + } + #[doc = "0x54 - NA"] + #[inline(always)] + pub const fn hp_probeb_ctrl(&self) -> &HP_PROBEB_CTRL { + &self.hp_probeb_ctrl + } + #[doc = "0x5c - NA"] + #[inline(always)] + pub const fn hp_probe_out(&self) -> &HP_PROBE_OUT { + &self.hp_probe_out + } + #[doc = "0x60 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_ram_pwr_ctrl0(&self) -> &HP_L2_MEM_RAM_PWR_CTRL0 { + &self.hp_l2_mem_ram_pwr_ctrl0 + } + #[doc = "0x64 - NA"] + #[inline(always)] + pub const fn hp_cpu_corestalled_st(&self) -> &HP_CPU_CORESTALLED_ST { + &self.hp_cpu_corestalled_st + } + #[doc = "0x70 - NA"] + #[inline(always)] + pub const fn hp_crypto_ctrl(&self) -> &HP_CRYPTO_CTRL { + &self.hp_crypto_ctrl + } + #[doc = "0x74 - NA"] + #[inline(always)] + pub const fn hp_gpio_o_hold_ctrl0(&self) -> &HP_GPIO_O_HOLD_CTRL0 { + &self.hp_gpio_o_hold_ctrl0 + } + #[doc = "0x78 - NA"] + #[inline(always)] + pub const fn hp_gpio_o_hold_ctrl1(&self) -> &HP_GPIO_O_HOLD_CTRL1 { + &self.hp_gpio_o_hold_ctrl1 + } + #[doc = "0x7c - NA"] + #[inline(always)] + pub const fn rdn_eco_cs(&self) -> &RDN_ECO_CS { + &self.rdn_eco_cs + } + #[doc = "0x80 - NA"] + #[inline(always)] + pub const fn hp_cache_apb_postw_en(&self) -> &HP_CACHE_APB_POSTW_EN { + &self.hp_cache_apb_postw_en + } + #[doc = "0x84 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_subsize(&self) -> &HP_L2_MEM_SUBSIZE { + &self.hp_l2_mem_subsize + } + #[doc = "0x9c - NA"] + #[inline(always)] + pub const fn hp_l2_mem_int_raw(&self) -> &HP_L2_MEM_INT_RAW { + &self.hp_l2_mem_int_raw + } + #[doc = "0xa0 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_int_st(&self) -> &HP_L2_MEM_INT_ST { + &self.hp_l2_mem_int_st + } + #[doc = "0xa4 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_int_ena(&self) -> &HP_L2_MEM_INT_ENA { + &self.hp_l2_mem_int_ena + } + #[doc = "0xa8 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_int_clr(&self) -> &HP_L2_MEM_INT_CLR { + &self.hp_l2_mem_int_clr + } + #[doc = "0xac - NA"] + #[inline(always)] + pub const fn hp_l2_mem_l2_ram_ecc(&self) -> &HP_L2_MEM_L2_RAM_ECC { + &self.hp_l2_mem_l2_ram_ecc + } + #[doc = "0xb0 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_int_record0(&self) -> &HP_L2_MEM_INT_RECORD0 { + &self.hp_l2_mem_int_record0 + } + #[doc = "0xb4 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_int_record1(&self) -> &HP_L2_MEM_INT_RECORD1 { + &self.hp_l2_mem_int_record1 + } + #[doc = "0xc4 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_l2_cache_ecc(&self) -> &HP_L2_MEM_L2_CACHE_ECC { + &self.hp_l2_mem_l2_cache_ecc + } + #[doc = "0xc8 - NA"] + #[inline(always)] + pub const fn hp_l1cache_bus0_id(&self) -> &HP_L1CACHE_BUS0_ID { + &self.hp_l1cache_bus0_id + } + #[doc = "0xcc - NA"] + #[inline(always)] + pub const fn hp_l1cache_bus1_id(&self) -> &HP_L1CACHE_BUS1_ID { + &self.hp_l1cache_bus1_id + } + #[doc = "0xd8 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_rdn_eco_cs(&self) -> &HP_L2_MEM_RDN_ECO_CS { + &self.hp_l2_mem_rdn_eco_cs + } + #[doc = "0xdc - NA"] + #[inline(always)] + pub const fn hp_l2_mem_rdn_eco_low(&self) -> &HP_L2_MEM_RDN_ECO_LOW { + &self.hp_l2_mem_rdn_eco_low + } + #[doc = "0xe0 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_rdn_eco_high(&self) -> &HP_L2_MEM_RDN_ECO_HIGH { + &self.hp_l2_mem_rdn_eco_high + } + #[doc = "0xe4 - NA"] + #[inline(always)] + pub const fn hp_tcm_rdn_eco_cs(&self) -> &HP_TCM_RDN_ECO_CS { + &self.hp_tcm_rdn_eco_cs + } + #[doc = "0xe8 - NA"] + #[inline(always)] + pub const fn hp_tcm_rdn_eco_low(&self) -> &HP_TCM_RDN_ECO_LOW { + &self.hp_tcm_rdn_eco_low + } + #[doc = "0xec - NA"] + #[inline(always)] + pub const fn hp_tcm_rdn_eco_high(&self) -> &HP_TCM_RDN_ECO_HIGH { + &self.hp_tcm_rdn_eco_high + } + #[doc = "0xf0 - NA"] + #[inline(always)] + pub const fn hp_gpio_ded_hold_ctrl(&self) -> &HP_GPIO_DED_HOLD_CTRL { + &self.hp_gpio_ded_hold_ctrl + } + #[doc = "0xf4 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_sw_ecc_bwe_mask(&self) -> &HP_L2_MEM_SW_ECC_BWE_MASK { + &self.hp_l2_mem_sw_ecc_bwe_mask + } + #[doc = "0xf8 - NA"] + #[inline(always)] + pub const fn hp_usb20otg_mem_ctrl(&self) -> &HP_USB20OTG_MEM_CTRL { + &self.hp_usb20otg_mem_ctrl + } + #[doc = "0xfc - need_des"] + #[inline(always)] + pub const fn hp_tcm_int_raw(&self) -> &HP_TCM_INT_RAW { + &self.hp_tcm_int_raw + } + #[doc = "0x100 - need_des"] + #[inline(always)] + pub const fn hp_tcm_int_st(&self) -> &HP_TCM_INT_ST { + &self.hp_tcm_int_st + } + #[doc = "0x104 - need_des"] + #[inline(always)] + pub const fn hp_tcm_int_ena(&self) -> &HP_TCM_INT_ENA { + &self.hp_tcm_int_ena + } + #[doc = "0x108 - need_des"] + #[inline(always)] + pub const fn hp_tcm_int_clr(&self) -> &HP_TCM_INT_CLR { + &self.hp_tcm_int_clr + } + #[doc = "0x10c - need_des"] + #[inline(always)] + pub const fn hp_tcm_parity_int_record(&self) -> &HP_TCM_PARITY_INT_RECORD { + &self.hp_tcm_parity_int_record + } + #[doc = "0x110 - NA"] + #[inline(always)] + pub const fn hp_l1_cache_pwr_ctrl(&self) -> &HP_L1_CACHE_PWR_CTRL { + &self.hp_l1_cache_pwr_ctrl + } + #[doc = "0x114 - NA"] + #[inline(always)] + pub const fn hp_l2_cache_pwr_ctrl(&self) -> &HP_L2_CACHE_PWR_CTRL { + &self.hp_l2_cache_pwr_ctrl + } + #[doc = "0x118 - CPU_WAITI configuration register"] + #[inline(always)] + pub const fn hp_cpu_waiti_conf(&self) -> &HP_CPU_WAITI_CONF { + &self.hp_cpu_waiti_conf + } + #[doc = "0x11c - Core Debug runstall configure register"] + #[inline(always)] + pub const fn core_debug_runstall_conf(&self) -> &CORE_DEBUG_RUNSTALL_CONF { + &self.core_debug_runstall_conf + } + #[doc = "0x120 - need_des"] + #[inline(always)] + pub const fn hp_core_ahb_timeout(&self) -> &HP_CORE_AHB_TIMEOUT { + &self.hp_core_ahb_timeout + } + #[doc = "0x124 - need_des"] + #[inline(always)] + pub const fn hp_core_ibus_timeout(&self) -> &HP_CORE_IBUS_TIMEOUT { + &self.hp_core_ibus_timeout + } + #[doc = "0x128 - need_des"] + #[inline(always)] + pub const fn hp_core_dbus_timeout(&self) -> &HP_CORE_DBUS_TIMEOUT { + &self.hp_core_dbus_timeout + } + #[doc = "0x138 - need_des"] + #[inline(always)] + pub const fn hp_icm_cpu_h2x_cfg(&self) -> &HP_ICM_CPU_H2X_CFG { + &self.hp_icm_cpu_h2x_cfg + } + #[doc = "0x13c - NA"] + #[inline(always)] + pub const fn hp_peri1_apb_postw_en(&self) -> &HP_PERI1_APB_POSTW_EN { + &self.hp_peri1_apb_postw_en + } + #[doc = "0x140 - Bitscrambler Peri Sel"] + #[inline(always)] + pub const fn hp_bitscrambler_peri_sel(&self) -> &HP_BITSCRAMBLER_PERI_SEL { + &self.hp_bitscrambler_peri_sel + } + #[doc = "0x144 - N/A"] + #[inline(always)] + pub const fn apb_sync_postw_en(&self) -> &APB_SYNC_POSTW_EN { + &self.apb_sync_postw_en + } + #[doc = "0x148 - N/A"] + #[inline(always)] + pub const fn gdma_ctrl(&self) -> &GDMA_CTRL { + &self.gdma_ctrl + } + #[doc = "0x14c - N/A"] + #[inline(always)] + pub const fn gmac_ctrl0(&self) -> &GMAC_CTRL0 { + &self.gmac_ctrl0 + } + #[doc = "0x150 - N/A"] + #[inline(always)] + pub const fn gmac_ctrl1(&self) -> &GMAC_CTRL1 { + &self.gmac_ctrl1 + } + #[doc = "0x154 - N/A"] + #[inline(always)] + pub const fn gmac_ctrl2(&self) -> &GMAC_CTRL2 { + &self.gmac_ctrl2 + } + #[doc = "0x158 - N/A"] + #[inline(always)] + pub const fn vpu_ctrl(&self) -> &VPU_CTRL { + &self.vpu_ctrl + } + #[doc = "0x15c - N/A"] + #[inline(always)] + pub const fn usbotg20_ctrl(&self) -> &USBOTG20_CTRL { + &self.usbotg20_ctrl + } + #[doc = "0x160 - need_des"] + #[inline(always)] + pub const fn hp_tcm_err_resp_ctrl(&self) -> &HP_TCM_ERR_RESP_CTRL { + &self.hp_tcm_err_resp_ctrl + } + #[doc = "0x164 - NA"] + #[inline(always)] + pub const fn hp_l2_mem_refresh(&self) -> &HP_L2_MEM_REFRESH { + &self.hp_l2_mem_refresh + } + #[doc = "0x168 - NA"] + #[inline(always)] + pub const fn hp_tcm_init(&self) -> &HP_TCM_INIT { + &self.hp_tcm_init + } + #[doc = "0x16c - need_des"] + #[inline(always)] + pub const fn hp_tcm_parity_check_ctrl(&self) -> &HP_TCM_PARITY_CHECK_CTRL { + &self.hp_tcm_parity_check_ctrl + } + #[doc = "0x170 - need_des"] + #[inline(always)] + pub const fn hp_design_for_verification0(&self) -> &HP_DESIGN_FOR_VERIFICATION0 { + &self.hp_design_for_verification0 + } + #[doc = "0x174 - need_des"] + #[inline(always)] + pub const fn hp_design_for_verification1(&self) -> &HP_DESIGN_FOR_VERIFICATION1 { + &self.hp_design_for_verification1 + } + #[doc = "0x180 - need_des"] + #[inline(always)] + pub const fn hp_psram_flash_addr_interchange(&self) -> &HP_PSRAM_FLASH_ADDR_INTERCHANGE { + &self.hp_psram_flash_addr_interchange + } + #[doc = "0x188 - NA"] + #[inline(always)] + pub const fn hp_ahb2axi_bresp_err_int_raw(&self) -> &HP_AHB2AXI_BRESP_ERR_INT_RAW { + &self.hp_ahb2axi_bresp_err_int_raw + } + #[doc = "0x18c - need_des"] + #[inline(always)] + pub const fn hp_ahb2axi_bresp_err_int_st(&self) -> &HP_AHB2AXI_BRESP_ERR_INT_ST { + &self.hp_ahb2axi_bresp_err_int_st + } + #[doc = "0x190 - need_des"] + #[inline(always)] + pub const fn hp_ahb2axi_bresp_err_int_ena(&self) -> &HP_AHB2AXI_BRESP_ERR_INT_ENA { + &self.hp_ahb2axi_bresp_err_int_ena + } + #[doc = "0x194 - need_des"] + #[inline(always)] + pub const fn hp_ahb2axi_bresp_err_int_clr(&self) -> &HP_AHB2AXI_BRESP_ERR_INT_CLR { + &self.hp_ahb2axi_bresp_err_int_clr + } + #[doc = "0x198 - need_des"] + #[inline(always)] + pub const fn hp_l2_mem_err_resp_ctrl(&self) -> &HP_L2_MEM_ERR_RESP_CTRL { + &self.hp_l2_mem_err_resp_ctrl + } + #[doc = "0x19c - need_des"] + #[inline(always)] + pub const fn hp_l2_mem_ahb_buffer_ctrl(&self) -> &HP_L2_MEM_AHB_BUFFER_CTRL { + &self.hp_l2_mem_ahb_buffer_ctrl + } + #[doc = "0x1a0 - need_des"] + #[inline(always)] + pub const fn hp_core_dmactive_lpcore(&self) -> &HP_CORE_DMACTIVE_LPCORE { + &self.hp_core_dmactive_lpcore + } + #[doc = "0x1a4 - need_des"] + #[inline(always)] + pub const fn hp_core_err_resp_dis(&self) -> &HP_CORE_ERR_RESP_DIS { + &self.hp_core_err_resp_dis + } + #[doc = "0x1a8 - Hp core bus timeout interrupt raw register"] + #[inline(always)] + pub const fn hp_core_timeout_int_raw(&self) -> &HP_CORE_TIMEOUT_INT_RAW { + &self.hp_core_timeout_int_raw + } + #[doc = "0x1ac - masked interrupt register"] + #[inline(always)] + pub const fn hp_core_timeout_int_st(&self) -> &HP_CORE_TIMEOUT_INT_ST { + &self.hp_core_timeout_int_st + } + #[doc = "0x1b0 - masked interrupt register"] + #[inline(always)] + pub const fn hp_core_timeout_int_ena(&self) -> &HP_CORE_TIMEOUT_INT_ENA { + &self.hp_core_timeout_int_ena + } + #[doc = "0x1b4 - interrupt clear register"] + #[inline(always)] + pub const fn hp_core_timeout_int_clr(&self) -> &HP_CORE_TIMEOUT_INT_CLR { + &self.hp_core_timeout_int_clr + } + #[doc = "0x1c0 - NA"] + #[inline(always)] + pub const fn hp_gpio_o_hys_ctrl0(&self) -> &HP_GPIO_O_HYS_CTRL0 { + &self.hp_gpio_o_hys_ctrl0 + } + #[doc = "0x1c4 - NA"] + #[inline(always)] + pub const fn hp_gpio_o_hys_ctrl1(&self) -> &HP_GPIO_O_HYS_CTRL1 { + &self.hp_gpio_o_hys_ctrl1 + } + #[doc = "0x1d0 - rsa pd ctrl register"] + #[inline(always)] + pub const fn hp_rsa_pd_ctrl(&self) -> &HP_RSA_PD_CTRL { + &self.hp_rsa_pd_ctrl + } + #[doc = "0x1d4 - ecc pd ctrl register"] + #[inline(always)] + pub const fn hp_ecc_pd_ctrl(&self) -> &HP_ECC_PD_CTRL { + &self.hp_ecc_pd_ctrl + } + #[doc = "0x1d8 - rng cfg register"] + #[inline(always)] + pub const fn hp_rng_cfg(&self) -> &HP_RNG_CFG { + &self.hp_rng_cfg + } + #[doc = "0x1dc - ecc pd ctrl register"] + #[inline(always)] + pub const fn hp_uart_pd_ctrl(&self) -> &HP_UART_PD_CTRL { + &self.hp_uart_pd_ctrl + } + #[doc = "0x1e0 - hp peri mem clk force on regpster"] + #[inline(always)] + pub const fn hp_peri_mem_clk_force_on(&self) -> &HP_PERI_MEM_CLK_FORCE_ON { + &self.hp_peri_mem_clk_force_on + } +} +#[doc = "VER_DATE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ver_date`] module"] +pub type VER_DATE = crate::Reg; +#[doc = "NA"] +pub mod ver_date; +#[doc = "HP_CLK_EN (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_clk_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_clk_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_clk_en`] module"] +pub type HP_CLK_EN = crate::Reg; +#[doc = "NA"] +pub mod hp_clk_en; +#[doc = "HP_CPU_INT_FROM_CPU_0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_int_from_cpu_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cpu_int_from_cpu_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_cpu_int_from_cpu_0`] module"] +pub type HP_CPU_INT_FROM_CPU_0 = crate::Reg; +#[doc = "NA"] +pub mod hp_cpu_int_from_cpu_0; +#[doc = "HP_CPU_INT_FROM_CPU_1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_int_from_cpu_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cpu_int_from_cpu_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_cpu_int_from_cpu_1`] module"] +pub type HP_CPU_INT_FROM_CPU_1 = crate::Reg; +#[doc = "NA"] +pub mod hp_cpu_int_from_cpu_1; +#[doc = "HP_CPU_INT_FROM_CPU_2 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_int_from_cpu_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cpu_int_from_cpu_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_cpu_int_from_cpu_2`] module"] +pub type HP_CPU_INT_FROM_CPU_2 = crate::Reg; +#[doc = "NA"] +pub mod hp_cpu_int_from_cpu_2; +#[doc = "HP_CPU_INT_FROM_CPU_3 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_int_from_cpu_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cpu_int_from_cpu_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_cpu_int_from_cpu_3`] module"] +pub type HP_CPU_INT_FROM_CPU_3 = crate::Reg; +#[doc = "NA"] +pub mod hp_cpu_int_from_cpu_3; +#[doc = "HP_CACHE_CLK_CONFIG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cache_clk_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cache_clk_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_cache_clk_config`] module"] +pub type HP_CACHE_CLK_CONFIG = crate::Reg; +#[doc = "NA"] +pub mod hp_cache_clk_config; +#[doc = "HP_CACHE_RESET_CONFIG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cache_reset_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cache_reset_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_cache_reset_config`] module"] +pub type HP_CACHE_RESET_CONFIG = crate::Reg; +#[doc = "NA"] +pub mod hp_cache_reset_config; +#[doc = "DMA_ADDR_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_addr_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_addr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_addr_ctrl`] module"] +pub type DMA_ADDR_CTRL = crate::Reg; +#[doc = "NA"] +pub mod dma_addr_ctrl; +#[doc = "HP_TCM_RAM_WRR_CONFIG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_ram_wrr_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_ram_wrr_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_ram_wrr_config`] module"] +pub type HP_TCM_RAM_WRR_CONFIG = crate::Reg; +#[doc = "NA"] +pub mod hp_tcm_ram_wrr_config; +#[doc = "HP_TCM_SW_PARITY_BWE_MASK (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_sw_parity_bwe_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_sw_parity_bwe_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_sw_parity_bwe_mask`] module"] +pub type HP_TCM_SW_PARITY_BWE_MASK = + crate::Reg; +#[doc = "NA"] +pub mod hp_tcm_sw_parity_bwe_mask; +#[doc = "HP_TCM_RAM_PWR_CTRL0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_ram_pwr_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_ram_pwr_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_ram_pwr_ctrl0`] module"] +pub type HP_TCM_RAM_PWR_CTRL0 = crate::Reg; +#[doc = "NA"] +pub mod hp_tcm_ram_pwr_ctrl0; +#[doc = "HP_L2_ROM_PWR_CTRL0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_rom_pwr_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_rom_pwr_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_rom_pwr_ctrl0`] module"] +pub type HP_L2_ROM_PWR_CTRL0 = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_rom_pwr_ctrl0; +#[doc = "HP_PROBEA_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_probea_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_probea_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_probea_ctrl`] module"] +pub type HP_PROBEA_CTRL = crate::Reg; +#[doc = "NA"] +pub mod hp_probea_ctrl; +#[doc = "HP_PROBEB_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_probeb_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_probeb_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_probeb_ctrl`] module"] +pub type HP_PROBEB_CTRL = crate::Reg; +#[doc = "NA"] +pub mod hp_probeb_ctrl; +#[doc = "HP_PROBE_OUT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_probe_out::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_probe_out`] module"] +pub type HP_PROBE_OUT = crate::Reg; +#[doc = "NA"] +pub mod hp_probe_out; +#[doc = "HP_L2_MEM_RAM_PWR_CTRL0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_ram_pwr_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_ram_pwr_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_ram_pwr_ctrl0`] module"] +pub type HP_L2_MEM_RAM_PWR_CTRL0 = + crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_ram_pwr_ctrl0; +#[doc = "HP_CPU_CORESTALLED_ST (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_corestalled_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_cpu_corestalled_st`] module"] +pub type HP_CPU_CORESTALLED_ST = crate::Reg; +#[doc = "NA"] +pub mod hp_cpu_corestalled_st; +#[doc = "HP_CRYPTO_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_crypto_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_crypto_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_crypto_ctrl`] module"] +pub type HP_CRYPTO_CTRL = crate::Reg; +#[doc = "NA"] +pub mod hp_crypto_ctrl; +#[doc = "HP_GPIO_O_HOLD_CTRL0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_gpio_o_hold_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_gpio_o_hold_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_gpio_o_hold_ctrl0`] module"] +pub type HP_GPIO_O_HOLD_CTRL0 = crate::Reg; +#[doc = "NA"] +pub mod hp_gpio_o_hold_ctrl0; +#[doc = "HP_GPIO_O_HOLD_CTRL1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_gpio_o_hold_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_gpio_o_hold_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_gpio_o_hold_ctrl1`] module"] +pub type HP_GPIO_O_HOLD_CTRL1 = crate::Reg; +#[doc = "NA"] +pub mod hp_gpio_o_hold_ctrl1; +#[doc = "RDN_ECO_CS (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_cs`] module"] +pub type RDN_ECO_CS = crate::Reg; +#[doc = "NA"] +pub mod rdn_eco_cs; +#[doc = "HP_CACHE_APB_POSTW_EN (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cache_apb_postw_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cache_apb_postw_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_cache_apb_postw_en`] module"] +pub type HP_CACHE_APB_POSTW_EN = crate::Reg; +#[doc = "NA"] +pub mod hp_cache_apb_postw_en; +#[doc = "HP_L2_MEM_SUBSIZE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_subsize::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_subsize::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_subsize`] module"] +pub type HP_L2_MEM_SUBSIZE = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_subsize; +#[doc = "HP_L2_MEM_INT_RAW (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_int_raw`] module"] +pub type HP_L2_MEM_INT_RAW = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_int_raw; +#[doc = "HP_L2_MEM_INT_ST (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_int_st`] module"] +pub type HP_L2_MEM_INT_ST = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_int_st; +#[doc = "HP_L2_MEM_INT_ENA (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_int_ena`] module"] +pub type HP_L2_MEM_INT_ENA = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_int_ena; +#[doc = "HP_L2_MEM_INT_CLR (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_int_clr`] module"] +pub type HP_L2_MEM_INT_CLR = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_int_clr; +#[doc = "HP_L2_MEM_L2_RAM_ECC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_l2_ram_ecc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_l2_ram_ecc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_l2_ram_ecc`] module"] +pub type HP_L2_MEM_L2_RAM_ECC = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_l2_ram_ecc; +#[doc = "HP_L2_MEM_INT_RECORD0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_int_record0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_int_record0`] module"] +pub type HP_L2_MEM_INT_RECORD0 = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_int_record0; +#[doc = "HP_L2_MEM_INT_RECORD1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_int_record1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_int_record1`] module"] +pub type HP_L2_MEM_INT_RECORD1 = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_int_record1; +#[doc = "HP_L2_MEM_L2_CACHE_ECC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_l2_cache_ecc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_l2_cache_ecc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_l2_cache_ecc`] module"] +pub type HP_L2_MEM_L2_CACHE_ECC = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_l2_cache_ecc; +#[doc = "HP_L1CACHE_BUS0_ID (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l1cache_bus0_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l1cache_bus0_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l1cache_bus0_id`] module"] +pub type HP_L1CACHE_BUS0_ID = crate::Reg; +#[doc = "NA"] +pub mod hp_l1cache_bus0_id; +#[doc = "HP_L1CACHE_BUS1_ID (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l1cache_bus1_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l1cache_bus1_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l1cache_bus1_id`] module"] +pub type HP_L1CACHE_BUS1_ID = crate::Reg; +#[doc = "NA"] +pub mod hp_l1cache_bus1_id; +#[doc = "HP_L2_MEM_RDN_ECO_CS (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_rdn_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_rdn_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_rdn_eco_cs`] module"] +pub type HP_L2_MEM_RDN_ECO_CS = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_rdn_eco_cs; +#[doc = "HP_L2_MEM_RDN_ECO_LOW (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_rdn_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_rdn_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_rdn_eco_low`] module"] +pub type HP_L2_MEM_RDN_ECO_LOW = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_rdn_eco_low; +#[doc = "HP_L2_MEM_RDN_ECO_HIGH (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_rdn_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_rdn_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_rdn_eco_high`] module"] +pub type HP_L2_MEM_RDN_ECO_HIGH = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_rdn_eco_high; +#[doc = "HP_TCM_RDN_ECO_CS (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_rdn_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_rdn_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_rdn_eco_cs`] module"] +pub type HP_TCM_RDN_ECO_CS = crate::Reg; +#[doc = "NA"] +pub mod hp_tcm_rdn_eco_cs; +#[doc = "HP_TCM_RDN_ECO_LOW (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_rdn_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_rdn_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_rdn_eco_low`] module"] +pub type HP_TCM_RDN_ECO_LOW = crate::Reg; +#[doc = "NA"] +pub mod hp_tcm_rdn_eco_low; +#[doc = "HP_TCM_RDN_ECO_HIGH (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_rdn_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_rdn_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_rdn_eco_high`] module"] +pub type HP_TCM_RDN_ECO_HIGH = crate::Reg; +#[doc = "NA"] +pub mod hp_tcm_rdn_eco_high; +#[doc = "HP_GPIO_DED_HOLD_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_gpio_ded_hold_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_gpio_ded_hold_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_gpio_ded_hold_ctrl`] module"] +pub type HP_GPIO_DED_HOLD_CTRL = crate::Reg; +#[doc = "NA"] +pub mod hp_gpio_ded_hold_ctrl; +#[doc = "HP_L2_MEM_SW_ECC_BWE_MASK (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_sw_ecc_bwe_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_sw_ecc_bwe_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_sw_ecc_bwe_mask`] module"] +pub type HP_L2_MEM_SW_ECC_BWE_MASK = + crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_sw_ecc_bwe_mask; +#[doc = "HP_USB20OTG_MEM_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_usb20otg_mem_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_usb20otg_mem_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_usb20otg_mem_ctrl`] module"] +pub type HP_USB20OTG_MEM_CTRL = crate::Reg; +#[doc = "NA"] +pub mod hp_usb20otg_mem_ctrl; +#[doc = "HP_TCM_INT_RAW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_int_raw`] module"] +pub type HP_TCM_INT_RAW = crate::Reg; +#[doc = "need_des"] +pub mod hp_tcm_int_raw; +#[doc = "HP_TCM_INT_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_int_st`] module"] +pub type HP_TCM_INT_ST = crate::Reg; +#[doc = "need_des"] +pub mod hp_tcm_int_st; +#[doc = "HP_TCM_INT_ENA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_int_ena`] module"] +pub type HP_TCM_INT_ENA = crate::Reg; +#[doc = "need_des"] +pub mod hp_tcm_int_ena; +#[doc = "HP_TCM_INT_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_int_clr`] module"] +pub type HP_TCM_INT_CLR = crate::Reg; +#[doc = "need_des"] +pub mod hp_tcm_int_clr; +#[doc = "HP_TCM_PARITY_INT_RECORD (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_parity_int_record::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_parity_int_record`] module"] +pub type HP_TCM_PARITY_INT_RECORD = + crate::Reg; +#[doc = "need_des"] +pub mod hp_tcm_parity_int_record; +#[doc = "HP_L1_CACHE_PWR_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l1_cache_pwr_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l1_cache_pwr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l1_cache_pwr_ctrl`] module"] +pub type HP_L1_CACHE_PWR_CTRL = crate::Reg; +#[doc = "NA"] +pub mod hp_l1_cache_pwr_ctrl; +#[doc = "HP_L2_CACHE_PWR_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_cache_pwr_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_cache_pwr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_cache_pwr_ctrl`] module"] +pub type HP_L2_CACHE_PWR_CTRL = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_cache_pwr_ctrl; +#[doc = "HP_CPU_WAITI_CONF (rw) register accessor: CPU_WAITI configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_waiti_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cpu_waiti_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_cpu_waiti_conf`] module"] +pub type HP_CPU_WAITI_CONF = crate::Reg; +#[doc = "CPU_WAITI configuration register"] +pub mod hp_cpu_waiti_conf; +#[doc = "CORE_DEBUG_RUNSTALL_CONF (rw) register accessor: Core Debug runstall configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_debug_runstall_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_debug_runstall_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_debug_runstall_conf`] module"] +pub type CORE_DEBUG_RUNSTALL_CONF = + crate::Reg; +#[doc = "Core Debug runstall configure register"] +pub mod core_debug_runstall_conf; +#[doc = "HP_CORE_AHB_TIMEOUT (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_ahb_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_ahb_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_core_ahb_timeout`] module"] +pub type HP_CORE_AHB_TIMEOUT = crate::Reg; +#[doc = "need_des"] +pub mod hp_core_ahb_timeout; +#[doc = "HP_CORE_IBUS_TIMEOUT (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_ibus_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_ibus_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_core_ibus_timeout`] module"] +pub type HP_CORE_IBUS_TIMEOUT = crate::Reg; +#[doc = "need_des"] +pub mod hp_core_ibus_timeout; +#[doc = "HP_CORE_DBUS_TIMEOUT (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_dbus_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_dbus_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_core_dbus_timeout`] module"] +pub type HP_CORE_DBUS_TIMEOUT = crate::Reg; +#[doc = "need_des"] +pub mod hp_core_dbus_timeout; +#[doc = "HP_ICM_CPU_H2X_CFG (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_icm_cpu_h2x_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_icm_cpu_h2x_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_icm_cpu_h2x_cfg`] module"] +pub type HP_ICM_CPU_H2X_CFG = crate::Reg; +#[doc = "need_des"] +pub mod hp_icm_cpu_h2x_cfg; +#[doc = "HP_PERI1_APB_POSTW_EN (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_peri1_apb_postw_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_peri1_apb_postw_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_peri1_apb_postw_en`] module"] +pub type HP_PERI1_APB_POSTW_EN = crate::Reg; +#[doc = "NA"] +pub mod hp_peri1_apb_postw_en; +#[doc = "HP_BITSCRAMBLER_PERI_SEL (rw) register accessor: Bitscrambler Peri Sel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_bitscrambler_peri_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_bitscrambler_peri_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_bitscrambler_peri_sel`] module"] +pub type HP_BITSCRAMBLER_PERI_SEL = + crate::Reg; +#[doc = "Bitscrambler Peri Sel"] +pub mod hp_bitscrambler_peri_sel; +#[doc = "APB_SYNC_POSTW_EN (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb_sync_postw_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb_sync_postw_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_sync_postw_en`] module"] +pub type APB_SYNC_POSTW_EN = crate::Reg; +#[doc = "N/A"] +pub mod apb_sync_postw_en; +#[doc = "GDMA_CTRL (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdma_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdma_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gdma_ctrl`] module"] +pub type GDMA_CTRL = crate::Reg; +#[doc = "N/A"] +pub mod gdma_ctrl; +#[doc = "GMAC_CTRL0 (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac_ctrl0`] module"] +pub type GMAC_CTRL0 = crate::Reg; +#[doc = "N/A"] +pub mod gmac_ctrl0; +#[doc = "GMAC_CTRL1 (r) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac_ctrl1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac_ctrl1`] module"] +pub type GMAC_CTRL1 = crate::Reg; +#[doc = "N/A"] +pub mod gmac_ctrl1; +#[doc = "GMAC_CTRL2 (r) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac_ctrl2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmac_ctrl2`] module"] +pub type GMAC_CTRL2 = crate::Reg; +#[doc = "N/A"] +pub mod gmac_ctrl2; +#[doc = "VPU_CTRL (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vpu_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vpu_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vpu_ctrl`] module"] +pub type VPU_CTRL = crate::Reg; +#[doc = "N/A"] +pub mod vpu_ctrl; +#[doc = "USBOTG20_CTRL (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbotg20_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbotg20_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbotg20_ctrl`] module"] +pub type USBOTG20_CTRL = crate::Reg; +#[doc = "N/A"] +pub mod usbotg20_ctrl; +#[doc = "HP_TCM_ERR_RESP_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_err_resp_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_err_resp_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_err_resp_ctrl`] module"] +pub type HP_TCM_ERR_RESP_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod hp_tcm_err_resp_ctrl; +#[doc = "HP_L2_MEM_REFRESH (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_refresh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_refresh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_refresh`] module"] +pub type HP_L2_MEM_REFRESH = crate::Reg; +#[doc = "NA"] +pub mod hp_l2_mem_refresh; +#[doc = "HP_TCM_INIT (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_init::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_init::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_init`] module"] +pub type HP_TCM_INIT = crate::Reg; +#[doc = "NA"] +pub mod hp_tcm_init; +#[doc = "HP_TCM_PARITY_CHECK_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_parity_check_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_parity_check_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_tcm_parity_check_ctrl`] module"] +pub type HP_TCM_PARITY_CHECK_CTRL = + crate::Reg; +#[doc = "need_des"] +pub mod hp_tcm_parity_check_ctrl; +#[doc = "HP_DESIGN_FOR_VERIFICATION0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_design_for_verification0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_design_for_verification0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_design_for_verification0`] module"] +pub type HP_DESIGN_FOR_VERIFICATION0 = + crate::Reg; +#[doc = "need_des"] +pub mod hp_design_for_verification0; +#[doc = "HP_DESIGN_FOR_VERIFICATION1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_design_for_verification1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_design_for_verification1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_design_for_verification1`] module"] +pub type HP_DESIGN_FOR_VERIFICATION1 = + crate::Reg; +#[doc = "need_des"] +pub mod hp_design_for_verification1; +#[doc = "HP_PSRAM_FLASH_ADDR_INTERCHANGE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_psram_flash_addr_interchange::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_psram_flash_addr_interchange::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_psram_flash_addr_interchange`] module"] +pub type HP_PSRAM_FLASH_ADDR_INTERCHANGE = + crate::Reg; +#[doc = "need_des"] +pub mod hp_psram_flash_addr_interchange; +#[doc = "HP_AHB2AXI_BRESP_ERR_INT_RAW (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ahb2axi_bresp_err_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ahb2axi_bresp_err_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_ahb2axi_bresp_err_int_raw`] module"] +pub type HP_AHB2AXI_BRESP_ERR_INT_RAW = + crate::Reg; +#[doc = "NA"] +pub mod hp_ahb2axi_bresp_err_int_raw; +#[doc = "HP_AHB2AXI_BRESP_ERR_INT_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ahb2axi_bresp_err_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_ahb2axi_bresp_err_int_st`] module"] +pub type HP_AHB2AXI_BRESP_ERR_INT_ST = + crate::Reg; +#[doc = "need_des"] +pub mod hp_ahb2axi_bresp_err_int_st; +#[doc = "HP_AHB2AXI_BRESP_ERR_INT_ENA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ahb2axi_bresp_err_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ahb2axi_bresp_err_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_ahb2axi_bresp_err_int_ena`] module"] +pub type HP_AHB2AXI_BRESP_ERR_INT_ENA = + crate::Reg; +#[doc = "need_des"] +pub mod hp_ahb2axi_bresp_err_int_ena; +#[doc = "HP_AHB2AXI_BRESP_ERR_INT_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ahb2axi_bresp_err_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_ahb2axi_bresp_err_int_clr`] module"] +pub type HP_AHB2AXI_BRESP_ERR_INT_CLR = + crate::Reg; +#[doc = "need_des"] +pub mod hp_ahb2axi_bresp_err_int_clr; +#[doc = "HP_L2_MEM_ERR_RESP_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_err_resp_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_err_resp_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_err_resp_ctrl`] module"] +pub type HP_L2_MEM_ERR_RESP_CTRL = + crate::Reg; +#[doc = "need_des"] +pub mod hp_l2_mem_err_resp_ctrl; +#[doc = "HP_L2_MEM_AHB_BUFFER_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_ahb_buffer_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_ahb_buffer_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_l2_mem_ahb_buffer_ctrl`] module"] +pub type HP_L2_MEM_AHB_BUFFER_CTRL = + crate::Reg; +#[doc = "need_des"] +pub mod hp_l2_mem_ahb_buffer_ctrl; +#[doc = "HP_CORE_DMACTIVE_LPCORE (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_dmactive_lpcore::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_core_dmactive_lpcore`] module"] +pub type HP_CORE_DMACTIVE_LPCORE = + crate::Reg; +#[doc = "need_des"] +pub mod hp_core_dmactive_lpcore; +#[doc = "HP_CORE_ERR_RESP_DIS (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_err_resp_dis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_err_resp_dis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_core_err_resp_dis`] module"] +pub type HP_CORE_ERR_RESP_DIS = crate::Reg; +#[doc = "need_des"] +pub mod hp_core_err_resp_dis; +#[doc = "HP_CORE_TIMEOUT_INT_RAW (rw) register accessor: Hp core bus timeout interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_timeout_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_timeout_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_core_timeout_int_raw`] module"] +pub type HP_CORE_TIMEOUT_INT_RAW = + crate::Reg; +#[doc = "Hp core bus timeout interrupt raw register"] +pub mod hp_core_timeout_int_raw; +#[doc = "HP_CORE_TIMEOUT_INT_ST (r) register accessor: masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_timeout_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_core_timeout_int_st`] module"] +pub type HP_CORE_TIMEOUT_INT_ST = crate::Reg; +#[doc = "masked interrupt register"] +pub mod hp_core_timeout_int_st; +#[doc = "HP_CORE_TIMEOUT_INT_ENA (rw) register accessor: masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_timeout_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_timeout_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_core_timeout_int_ena`] module"] +pub type HP_CORE_TIMEOUT_INT_ENA = + crate::Reg; +#[doc = "masked interrupt register"] +pub mod hp_core_timeout_int_ena; +#[doc = "HP_CORE_TIMEOUT_INT_CLR (w) register accessor: interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_timeout_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_core_timeout_int_clr`] module"] +pub type HP_CORE_TIMEOUT_INT_CLR = + crate::Reg; +#[doc = "interrupt clear register"] +pub mod hp_core_timeout_int_clr; +#[doc = "HP_GPIO_O_HYS_CTRL0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_gpio_o_hys_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_gpio_o_hys_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_gpio_o_hys_ctrl0`] module"] +pub type HP_GPIO_O_HYS_CTRL0 = crate::Reg; +#[doc = "NA"] +pub mod hp_gpio_o_hys_ctrl0; +#[doc = "HP_GPIO_O_HYS_CTRL1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_gpio_o_hys_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_gpio_o_hys_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_gpio_o_hys_ctrl1`] module"] +pub type HP_GPIO_O_HYS_CTRL1 = crate::Reg; +#[doc = "NA"] +pub mod hp_gpio_o_hys_ctrl1; +#[doc = "HP_RSA_PD_CTRL (rw) register accessor: rsa pd ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rsa_pd_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rsa_pd_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_rsa_pd_ctrl`] module"] +pub type HP_RSA_PD_CTRL = crate::Reg; +#[doc = "rsa pd ctrl register"] +pub mod hp_rsa_pd_ctrl; +#[doc = "HP_ECC_PD_CTRL (rw) register accessor: ecc pd ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ecc_pd_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ecc_pd_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_ecc_pd_ctrl`] module"] +pub type HP_ECC_PD_CTRL = crate::Reg; +#[doc = "ecc pd ctrl register"] +pub mod hp_ecc_pd_ctrl; +#[doc = "HP_RNG_CFG (rw) register accessor: rng cfg register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rng_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rng_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_rng_cfg`] module"] +pub type HP_RNG_CFG = crate::Reg; +#[doc = "rng cfg register"] +pub mod hp_rng_cfg; +#[doc = "HP_UART_PD_CTRL (rw) register accessor: ecc pd ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_uart_pd_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_uart_pd_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_uart_pd_ctrl`] module"] +pub type HP_UART_PD_CTRL = crate::Reg; +#[doc = "ecc pd ctrl register"] +pub mod hp_uart_pd_ctrl; +#[doc = "HP_PERI_MEM_CLK_FORCE_ON (rw) register accessor: hp peri mem clk force on regpster\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_peri_mem_clk_force_on::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_peri_mem_clk_force_on::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_peri_mem_clk_force_on`] module"] +pub type HP_PERI_MEM_CLK_FORCE_ON = + crate::Reg; +#[doc = "hp peri mem clk force on regpster"] +pub mod hp_peri_mem_clk_force_on; diff --git a/esp32p4/src/hp_sys/apb_sync_postw_en.rs b/esp32p4/src/hp_sys/apb_sync_postw_en.rs new file mode 100644 index 0000000000..e10b21fd55 --- /dev/null +++ b/esp32p4/src/hp_sys/apb_sync_postw_en.rs @@ -0,0 +1,127 @@ +#[doc = "Register `APB_SYNC_POSTW_EN` reader"] +pub type R = crate::R; +#[doc = "Register `APB_SYNC_POSTW_EN` writer"] +pub type W = crate::W; +#[doc = "Field `GMAC_APB_POSTW_EN` reader - N/A"] +pub type GMAC_APB_POSTW_EN_R = crate::BitReader; +#[doc = "Field `GMAC_APB_POSTW_EN` writer - N/A"] +pub type GMAC_APB_POSTW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSI_HOST_APB_POSTW_EN` reader - N/A"] +pub type DSI_HOST_APB_POSTW_EN_R = crate::BitReader; +#[doc = "Field `DSI_HOST_APB_POSTW_EN` writer - N/A"] +pub type DSI_HOST_APB_POSTW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSI_HOST_APB_SYNC_POSTW_EN` reader - N/A"] +pub type CSI_HOST_APB_SYNC_POSTW_EN_R = crate::BitReader; +#[doc = "Field `CSI_HOST_APB_SYNC_POSTW_EN` writer - N/A"] +pub type CSI_HOST_APB_SYNC_POSTW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSI_HOST_APB_ASYNC_POSTW_EN` reader - N/A"] +pub type CSI_HOST_APB_ASYNC_POSTW_EN_R = crate::BitReader; +#[doc = "Field `CSI_HOST_APB_ASYNC_POSTW_EN` writer - N/A"] +pub type CSI_HOST_APB_ASYNC_POSTW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + pub fn gmac_apb_postw_en(&self) -> GMAC_APB_POSTW_EN_R { + GMAC_APB_POSTW_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + pub fn dsi_host_apb_postw_en(&self) -> DSI_HOST_APB_POSTW_EN_R { + DSI_HOST_APB_POSTW_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - N/A"] + #[inline(always)] + pub fn csi_host_apb_sync_postw_en(&self) -> CSI_HOST_APB_SYNC_POSTW_EN_R { + CSI_HOST_APB_SYNC_POSTW_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - N/A"] + #[inline(always)] + pub fn csi_host_apb_async_postw_en(&self) -> CSI_HOST_APB_ASYNC_POSTW_EN_R { + CSI_HOST_APB_ASYNC_POSTW_EN_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("APB_SYNC_POSTW_EN") + .field( + "gmac_apb_postw_en", + &format_args!("{}", self.gmac_apb_postw_en().bit()), + ) + .field( + "dsi_host_apb_postw_en", + &format_args!("{}", self.dsi_host_apb_postw_en().bit()), + ) + .field( + "csi_host_apb_sync_postw_en", + &format_args!("{}", self.csi_host_apb_sync_postw_en().bit()), + ) + .field( + "csi_host_apb_async_postw_en", + &format_args!("{}", self.csi_host_apb_async_postw_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + #[must_use] + pub fn gmac_apb_postw_en(&mut self) -> GMAC_APB_POSTW_EN_W { + GMAC_APB_POSTW_EN_W::new(self, 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + #[must_use] + pub fn dsi_host_apb_postw_en(&mut self) -> DSI_HOST_APB_POSTW_EN_W { + DSI_HOST_APB_POSTW_EN_W::new(self, 1) + } + #[doc = "Bit 2 - N/A"] + #[inline(always)] + #[must_use] + pub fn csi_host_apb_sync_postw_en( + &mut self, + ) -> CSI_HOST_APB_SYNC_POSTW_EN_W { + CSI_HOST_APB_SYNC_POSTW_EN_W::new(self, 2) + } + #[doc = "Bit 3 - N/A"] + #[inline(always)] + #[must_use] + pub fn csi_host_apb_async_postw_en( + &mut self, + ) -> CSI_HOST_APB_ASYNC_POSTW_EN_W { + CSI_HOST_APB_ASYNC_POSTW_EN_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb_sync_postw_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb_sync_postw_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct APB_SYNC_POSTW_EN_SPEC; +impl crate::RegisterSpec for APB_SYNC_POSTW_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`apb_sync_postw_en::R`](R) reader structure"] +impl crate::Readable for APB_SYNC_POSTW_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`apb_sync_postw_en::W`](W) writer structure"] +impl crate::Writable for APB_SYNC_POSTW_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets APB_SYNC_POSTW_EN to value 0"] +impl crate::Resettable for APB_SYNC_POSTW_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/core_debug_runstall_conf.rs b/esp32p4/src/hp_sys/core_debug_runstall_conf.rs new file mode 100644 index 0000000000..716888bc57 --- /dev/null +++ b/esp32p4/src/hp_sys/core_debug_runstall_conf.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE_DEBUG_RUNSTALL_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_DEBUG_RUNSTALL_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CORE_DEBUG_RUNSTALL_ENABLE` reader - Set this field to 1 to enable debug runstall feature between HP-core and LP-core."] +pub type CORE_DEBUG_RUNSTALL_ENABLE_R = crate::BitReader; +#[doc = "Field `CORE_DEBUG_RUNSTALL_ENABLE` writer - Set this field to 1 to enable debug runstall feature between HP-core and LP-core."] +pub type CORE_DEBUG_RUNSTALL_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this field to 1 to enable debug runstall feature between HP-core and LP-core."] + #[inline(always)] + pub fn core_debug_runstall_enable(&self) -> CORE_DEBUG_RUNSTALL_ENABLE_R { + CORE_DEBUG_RUNSTALL_ENABLE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_DEBUG_RUNSTALL_CONF") + .field( + "core_debug_runstall_enable", + &format_args!("{}", self.core_debug_runstall_enable().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this field to 1 to enable debug runstall feature between HP-core and LP-core."] + #[inline(always)] + #[must_use] + pub fn core_debug_runstall_enable( + &mut self, + ) -> CORE_DEBUG_RUNSTALL_ENABLE_W { + CORE_DEBUG_RUNSTALL_ENABLE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Core Debug runstall configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_debug_runstall_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_debug_runstall_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_DEBUG_RUNSTALL_CONF_SPEC; +impl crate::RegisterSpec for CORE_DEBUG_RUNSTALL_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_debug_runstall_conf::R`](R) reader structure"] +impl crate::Readable for CORE_DEBUG_RUNSTALL_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_debug_runstall_conf::W`](W) writer structure"] +impl crate::Writable for CORE_DEBUG_RUNSTALL_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_DEBUG_RUNSTALL_CONF to value 0"] +impl crate::Resettable for CORE_DEBUG_RUNSTALL_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/dma_addr_ctrl.rs b/esp32p4/src/hp_sys/dma_addr_ctrl.rs new file mode 100644 index 0000000000..9a6dc8f5d9 --- /dev/null +++ b/esp32p4/src/hp_sys/dma_addr_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DMA_ADDR_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_ADDR_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_SYS_DMA_ADDR_SEL` reader - 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx"] +pub type HP_REG_SYS_DMA_ADDR_SEL_R = crate::BitReader; +#[doc = "Field `HP_REG_SYS_DMA_ADDR_SEL` writer - 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx"] +pub type HP_REG_SYS_DMA_ADDR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx"] + #[inline(always)] + pub fn hp_reg_sys_dma_addr_sel(&self) -> HP_REG_SYS_DMA_ADDR_SEL_R { + HP_REG_SYS_DMA_ADDR_SEL_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_ADDR_CTRL") + .field( + "hp_reg_sys_dma_addr_sel", + &format_args!("{}", self.hp_reg_sys_dma_addr_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx"] + #[inline(always)] + #[must_use] + pub fn hp_reg_sys_dma_addr_sel(&mut self) -> HP_REG_SYS_DMA_ADDR_SEL_W { + HP_REG_SYS_DMA_ADDR_SEL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_addr_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_addr_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_ADDR_CTRL_SPEC; +impl crate::RegisterSpec for DMA_ADDR_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_addr_ctrl::R`](R) reader structure"] +impl crate::Readable for DMA_ADDR_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_addr_ctrl::W`](W) writer structure"] +impl crate::Writable for DMA_ADDR_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_ADDR_CTRL to value 0"] +impl crate::Resettable for DMA_ADDR_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/gdma_ctrl.rs b/esp32p4/src/hp_sys/gdma_ctrl.rs new file mode 100644 index 0000000000..81adce0d7c --- /dev/null +++ b/esp32p4/src/hp_sys/gdma_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GDMA_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `GDMA_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DEBUG_CH_NUM` reader - N/A"] +pub type DEBUG_CH_NUM_R = crate::FieldReader; +#[doc = "Field `DEBUG_CH_NUM` writer - N/A"] +pub type DEBUG_CH_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - N/A"] + #[inline(always)] + pub fn debug_ch_num(&self) -> DEBUG_CH_NUM_R { + DEBUG_CH_NUM_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GDMA_CTRL") + .field( + "debug_ch_num", + &format_args!("{}", self.debug_ch_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - N/A"] + #[inline(always)] + #[must_use] + pub fn debug_ch_num(&mut self) -> DEBUG_CH_NUM_W { + DEBUG_CH_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdma_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdma_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GDMA_CTRL_SPEC; +impl crate::RegisterSpec for GDMA_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gdma_ctrl::R`](R) reader structure"] +impl crate::Readable for GDMA_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gdma_ctrl::W`](W) writer structure"] +impl crate::Writable for GDMA_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GDMA_CTRL to value 0"] +impl crate::Resettable for GDMA_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/gmac_ctrl0.rs b/esp32p4/src/hp_sys/gmac_ctrl0.rs new file mode 100644 index 0000000000..97862c470d --- /dev/null +++ b/esp32p4/src/hp_sys/gmac_ctrl0.rs @@ -0,0 +1,134 @@ +#[doc = "Register `GMAC_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `GMAC_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `PTP_PPS` reader - N/A"] +pub type PTP_PPS_R = crate::BitReader; +#[doc = "Field `SBD_FLOWCTRL` reader - N/A"] +pub type SBD_FLOWCTRL_R = crate::BitReader; +#[doc = "Field `SBD_FLOWCTRL` writer - N/A"] +pub type SBD_FLOWCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_INTF_SEL` reader - N/A"] +pub type PHY_INTF_SEL_R = crate::FieldReader; +#[doc = "Field `PHY_INTF_SEL` writer - N/A"] +pub type PHY_INTF_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GMAC_MEM_CLK_FORCE_ON` reader - N/A"] +pub type GMAC_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `GMAC_MEM_CLK_FORCE_ON` writer - N/A"] +pub type GMAC_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GMAC_RST_CLK_TX_N` reader - N/A"] +pub type GMAC_RST_CLK_TX_N_R = crate::BitReader; +#[doc = "Field `GMAC_RST_CLK_RX_N` reader - N/A"] +pub type GMAC_RST_CLK_RX_N_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + pub fn ptp_pps(&self) -> PTP_PPS_R { + PTP_PPS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + pub fn sbd_flowctrl(&self) -> SBD_FLOWCTRL_R { + SBD_FLOWCTRL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - N/A"] + #[inline(always)] + pub fn phy_intf_sel(&self) -> PHY_INTF_SEL_R { + PHY_INTF_SEL_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bit 5 - N/A"] + #[inline(always)] + pub fn gmac_mem_clk_force_on(&self) -> GMAC_MEM_CLK_FORCE_ON_R { + GMAC_MEM_CLK_FORCE_ON_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - N/A"] + #[inline(always)] + pub fn gmac_rst_clk_tx_n(&self) -> GMAC_RST_CLK_TX_N_R { + GMAC_RST_CLK_TX_N_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - N/A"] + #[inline(always)] + pub fn gmac_rst_clk_rx_n(&self) -> GMAC_RST_CLK_RX_N_R { + GMAC_RST_CLK_RX_N_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GMAC_CTRL0") + .field("ptp_pps", &format_args!("{}", self.ptp_pps().bit())) + .field( + "sbd_flowctrl", + &format_args!("{}", self.sbd_flowctrl().bit()), + ) + .field( + "phy_intf_sel", + &format_args!("{}", self.phy_intf_sel().bits()), + ) + .field( + "gmac_mem_clk_force_on", + &format_args!("{}", self.gmac_mem_clk_force_on().bit()), + ) + .field( + "gmac_rst_clk_tx_n", + &format_args!("{}", self.gmac_rst_clk_tx_n().bit()), + ) + .field( + "gmac_rst_clk_rx_n", + &format_args!("{}", self.gmac_rst_clk_rx_n().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 1 - N/A"] + #[inline(always)] + #[must_use] + pub fn sbd_flowctrl(&mut self) -> SBD_FLOWCTRL_W { + SBD_FLOWCTRL_W::new(self, 1) + } + #[doc = "Bits 2:4 - N/A"] + #[inline(always)] + #[must_use] + pub fn phy_intf_sel(&mut self) -> PHY_INTF_SEL_W { + PHY_INTF_SEL_W::new(self, 2) + } + #[doc = "Bit 5 - N/A"] + #[inline(always)] + #[must_use] + pub fn gmac_mem_clk_force_on(&mut self) -> GMAC_MEM_CLK_FORCE_ON_W { + GMAC_MEM_CLK_FORCE_ON_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmac_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC_CTRL0_SPEC; +impl crate::RegisterSpec for GMAC_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac_ctrl0::R`](R) reader structure"] +impl crate::Readable for GMAC_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmac_ctrl0::W`](W) writer structure"] +impl crate::Writable for GMAC_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GMAC_CTRL0 to value 0"] +impl crate::Resettable for GMAC_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/gmac_ctrl1.rs b/esp32p4/src/hp_sys/gmac_ctrl1.rs new file mode 100644 index 0000000000..ccb7b109fe --- /dev/null +++ b/esp32p4/src/hp_sys/gmac_ctrl1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `GMAC_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Field `PTP_TIMESTAMP_L` reader - N/A"] +pub type PTP_TIMESTAMP_L_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + pub fn ptp_timestamp_l(&self) -> PTP_TIMESTAMP_L_R { + PTP_TIMESTAMP_L_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GMAC_CTRL1") + .field( + "ptp_timestamp_l", + &format_args!("{}", self.ptp_timestamp_l().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac_ctrl1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC_CTRL1_SPEC; +impl crate::RegisterSpec for GMAC_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac_ctrl1::R`](R) reader structure"] +impl crate::Readable for GMAC_CTRL1_SPEC {} +#[doc = "`reset()` method sets GMAC_CTRL1 to value 0"] +impl crate::Resettable for GMAC_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/gmac_ctrl2.rs b/esp32p4/src/hp_sys/gmac_ctrl2.rs new file mode 100644 index 0000000000..3c8092ecbf --- /dev/null +++ b/esp32p4/src/hp_sys/gmac_ctrl2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `GMAC_CTRL2` reader"] +pub type R = crate::R; +#[doc = "Field `PTP_TIMESTAMP_H` reader - N/A"] +pub type PTP_TIMESTAMP_H_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + pub fn ptp_timestamp_h(&self) -> PTP_TIMESTAMP_H_R { + PTP_TIMESTAMP_H_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GMAC_CTRL2") + .field( + "ptp_timestamp_h", + &format_args!("{}", self.ptp_timestamp_h().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac_ctrl2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMAC_CTRL2_SPEC; +impl crate::RegisterSpec for GMAC_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmac_ctrl2::R`](R) reader structure"] +impl crate::Readable for GMAC_CTRL2_SPEC {} +#[doc = "`reset()` method sets GMAC_CTRL2 to value 0"] +impl crate::Resettable for GMAC_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_clr.rs b/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_clr.rs new file mode 100644 index 0000000000..24d7549071 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_clr.rs @@ -0,0 +1,44 @@ +#[doc = "Register `HP_AHB2AXI_BRESP_ERR_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR` writer - Write 1 to clear cpu_icm_h2x_bresp_err int"] +pub type HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - Write 1 to clear cpu_icm_h2x_bresp_err int"] + #[inline(always)] + #[must_use] + pub fn hp_cpu_icm_h2x_bresp_err_int_clr( + &mut self, + ) -> HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR_W { + HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ahb2axi_bresp_err_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_AHB2AXI_BRESP_ERR_INT_CLR_SPEC; +impl crate::RegisterSpec for HP_AHB2AXI_BRESP_ERR_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_ahb2axi_bresp_err_int_clr::W`](W) writer structure"] +impl crate::Writable for HP_AHB2AXI_BRESP_ERR_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_AHB2AXI_BRESP_ERR_INT_CLR to value 0"] +impl crate::Resettable for HP_AHB2AXI_BRESP_ERR_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_ena.rs b/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_ena.rs new file mode 100644 index 0000000000..3fe2594ace --- /dev/null +++ b/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_ena.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_AHB2AXI_BRESP_ERR_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `HP_AHB2AXI_BRESP_ERR_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA` reader - Write 1 to enable cpu_icm_h2x_bresp_err int"] +pub type HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA` writer - Write 1 to enable cpu_icm_h2x_bresp_err int"] +pub type HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - Write 1 to enable cpu_icm_h2x_bresp_err int"] + #[inline(always)] + pub fn hp_cpu_icm_h2x_bresp_err_int_ena(&self) -> HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA_R { + HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_AHB2AXI_BRESP_ERR_INT_ENA") + .field( + "hp_cpu_icm_h2x_bresp_err_int_ena", + &format_args!("{}", self.hp_cpu_icm_h2x_bresp_err_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - Write 1 to enable cpu_icm_h2x_bresp_err int"] + #[inline(always)] + #[must_use] + pub fn hp_cpu_icm_h2x_bresp_err_int_ena( + &mut self, + ) -> HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA_W { + HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ahb2axi_bresp_err_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ahb2axi_bresp_err_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_AHB2AXI_BRESP_ERR_INT_ENA_SPEC; +impl crate::RegisterSpec for HP_AHB2AXI_BRESP_ERR_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_ahb2axi_bresp_err_int_ena::R`](R) reader structure"] +impl crate::Readable for HP_AHB2AXI_BRESP_ERR_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_ahb2axi_bresp_err_int_ena::W`](W) writer structure"] +impl crate::Writable for HP_AHB2AXI_BRESP_ERR_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_AHB2AXI_BRESP_ERR_INT_ENA to value 0"] +impl crate::Resettable for HP_AHB2AXI_BRESP_ERR_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_raw.rs b/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_raw.rs new file mode 100644 index 0000000000..3228604cfa --- /dev/null +++ b/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_raw.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_AHB2AXI_BRESP_ERR_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `HP_AHB2AXI_BRESP_ERR_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW` reader - the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi."] +pub type HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW` writer - the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi."] +pub type HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi."] + #[inline(always)] + pub fn hp_cpu_icm_h2x_bresp_err_int_raw(&self) -> HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW_R { + HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_AHB2AXI_BRESP_ERR_INT_RAW") + .field( + "hp_cpu_icm_h2x_bresp_err_int_raw", + &format_args!("{}", self.hp_cpu_icm_h2x_bresp_err_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi."] + #[inline(always)] + #[must_use] + pub fn hp_cpu_icm_h2x_bresp_err_int_raw( + &mut self, + ) -> HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW_W { + HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ahb2axi_bresp_err_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ahb2axi_bresp_err_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_AHB2AXI_BRESP_ERR_INT_RAW_SPEC; +impl crate::RegisterSpec for HP_AHB2AXI_BRESP_ERR_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_ahb2axi_bresp_err_int_raw::R`](R) reader structure"] +impl crate::Readable for HP_AHB2AXI_BRESP_ERR_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_ahb2axi_bresp_err_int_raw::W`](W) writer structure"] +impl crate::Writable for HP_AHB2AXI_BRESP_ERR_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_AHB2AXI_BRESP_ERR_INT_RAW to value 0"] +impl crate::Resettable for HP_AHB2AXI_BRESP_ERR_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_st.rs b/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_st.rs new file mode 100644 index 0000000000..0f1905a220 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_ahb2axi_bresp_err_int_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `HP_AHB2AXI_BRESP_ERR_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `HP_CPU_ICM_H2X_BRESP_ERR_INT_ST` reader - the masked interrupt status of cpu_icm_h2x_bresp_err"] +pub type HP_CPU_ICM_H2X_BRESP_ERR_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 31 - the masked interrupt status of cpu_icm_h2x_bresp_err"] + #[inline(always)] + pub fn hp_cpu_icm_h2x_bresp_err_int_st(&self) -> HP_CPU_ICM_H2X_BRESP_ERR_INT_ST_R { + HP_CPU_ICM_H2X_BRESP_ERR_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_AHB2AXI_BRESP_ERR_INT_ST") + .field( + "hp_cpu_icm_h2x_bresp_err_int_st", + &format_args!("{}", self.hp_cpu_icm_h2x_bresp_err_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ahb2axi_bresp_err_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_AHB2AXI_BRESP_ERR_INT_ST_SPEC; +impl crate::RegisterSpec for HP_AHB2AXI_BRESP_ERR_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_ahb2axi_bresp_err_int_st::R`](R) reader structure"] +impl crate::Readable for HP_AHB2AXI_BRESP_ERR_INT_ST_SPEC {} +#[doc = "`reset()` method sets HP_AHB2AXI_BRESP_ERR_INT_ST to value 0"] +impl crate::Resettable for HP_AHB2AXI_BRESP_ERR_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_bitscrambler_peri_sel.rs b/esp32p4/src/hp_sys/hp_bitscrambler_peri_sel.rs new file mode 100644 index 0000000000..5256de9dae --- /dev/null +++ b/esp32p4/src/hp_sys/hp_bitscrambler_peri_sel.rs @@ -0,0 +1,89 @@ +#[doc = "Register `HP_BITSCRAMBLER_PERI_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_BITSCRAMBLER_PERI_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_BITSCRAMBLER_PERI_RX_SEL` reader - Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"] +pub type HP_BITSCRAMBLER_PERI_RX_SEL_R = crate::FieldReader; +#[doc = "Field `HP_BITSCRAMBLER_PERI_RX_SEL` writer - Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"] +pub type HP_BITSCRAMBLER_PERI_RX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_BITSCRAMBLER_PERI_TX_SEL` reader - Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"] +pub type HP_BITSCRAMBLER_PERI_TX_SEL_R = crate::FieldReader; +#[doc = "Field `HP_BITSCRAMBLER_PERI_TX_SEL` writer - Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"] +pub type HP_BITSCRAMBLER_PERI_TX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"] + #[inline(always)] + pub fn hp_bitscrambler_peri_rx_sel(&self) -> HP_BITSCRAMBLER_PERI_RX_SEL_R { + HP_BITSCRAMBLER_PERI_RX_SEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"] + #[inline(always)] + pub fn hp_bitscrambler_peri_tx_sel(&self) -> HP_BITSCRAMBLER_PERI_TX_SEL_R { + HP_BITSCRAMBLER_PERI_TX_SEL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_BITSCRAMBLER_PERI_SEL") + .field( + "hp_bitscrambler_peri_rx_sel", + &format_args!("{}", self.hp_bitscrambler_peri_rx_sel().bits()), + ) + .field( + "hp_bitscrambler_peri_tx_sel", + &format_args!("{}", self.hp_bitscrambler_peri_tx_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"] + #[inline(always)] + #[must_use] + pub fn hp_bitscrambler_peri_rx_sel( + &mut self, + ) -> HP_BITSCRAMBLER_PERI_RX_SEL_W { + HP_BITSCRAMBLER_PERI_RX_SEL_W::new(self, 0) + } + #[doc = "Bits 4:7 - Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"] + #[inline(always)] + #[must_use] + pub fn hp_bitscrambler_peri_tx_sel( + &mut self, + ) -> HP_BITSCRAMBLER_PERI_TX_SEL_W { + HP_BITSCRAMBLER_PERI_TX_SEL_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Bitscrambler Peri Sel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_bitscrambler_peri_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_bitscrambler_peri_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_BITSCRAMBLER_PERI_SEL_SPEC; +impl crate::RegisterSpec for HP_BITSCRAMBLER_PERI_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_bitscrambler_peri_sel::R`](R) reader structure"] +impl crate::Readable for HP_BITSCRAMBLER_PERI_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_bitscrambler_peri_sel::W`](W) writer structure"] +impl crate::Writable for HP_BITSCRAMBLER_PERI_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_BITSCRAMBLER_PERI_SEL to value 0xff"] +impl crate::Resettable for HP_BITSCRAMBLER_PERI_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0xff; +} diff --git a/esp32p4/src/hp_sys/hp_cache_apb_postw_en.rs b/esp32p4/src/hp_sys/hp_cache_apb_postw_en.rs new file mode 100644 index 0000000000..3b3801f4f9 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_cache_apb_postw_en.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_CACHE_APB_POSTW_EN` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CACHE_APB_POSTW_EN` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_CACHE_APB_POSTW_EN` reader - cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"] +pub type HP_REG_CACHE_APB_POSTW_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_CACHE_APB_POSTW_EN` writer - cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"] +pub type HP_REG_CACHE_APB_POSTW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"] + #[inline(always)] + pub fn hp_reg_cache_apb_postw_en(&self) -> HP_REG_CACHE_APB_POSTW_EN_R { + HP_REG_CACHE_APB_POSTW_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CACHE_APB_POSTW_EN") + .field( + "hp_reg_cache_apb_postw_en", + &format_args!("{}", self.hp_reg_cache_apb_postw_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"] + #[inline(always)] + #[must_use] + pub fn hp_reg_cache_apb_postw_en( + &mut self, + ) -> HP_REG_CACHE_APB_POSTW_EN_W { + HP_REG_CACHE_APB_POSTW_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cache_apb_postw_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cache_apb_postw_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CACHE_APB_POSTW_EN_SPEC; +impl crate::RegisterSpec for HP_CACHE_APB_POSTW_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_cache_apb_postw_en::R`](R) reader structure"] +impl crate::Readable for HP_CACHE_APB_POSTW_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_cache_apb_postw_en::W`](W) writer structure"] +impl crate::Writable for HP_CACHE_APB_POSTW_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CACHE_APB_POSTW_EN to value 0"] +impl crate::Resettable for HP_CACHE_APB_POSTW_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_cache_clk_config.rs b/esp32p4/src/hp_sys/hp_cache_clk_config.rs new file mode 100644 index 0000000000..0b9c472425 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_cache_clk_config.rs @@ -0,0 +1,129 @@ +#[doc = "Register `HP_CACHE_CLK_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CACHE_CLK_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_CACHE_CLK_ON` reader - l2 cahce clk enable"] +pub type HP_REG_L2_CACHE_CLK_ON_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_CACHE_CLK_ON` writer - l2 cahce clk enable"] +pub type HP_REG_L2_CACHE_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L1_D_CACHE_CLK_ON` reader - l1 dcahce clk enable"] +pub type HP_REG_L1_D_CACHE_CLK_ON_R = crate::BitReader; +#[doc = "Field `HP_REG_L1_D_CACHE_CLK_ON` writer - l1 dcahce clk enable"] +pub type HP_REG_L1_D_CACHE_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L1_I1_CACHE_CLK_ON` reader - l1 icahce1 clk enable"] +pub type HP_REG_L1_I1_CACHE_CLK_ON_R = crate::BitReader; +#[doc = "Field `HP_REG_L1_I1_CACHE_CLK_ON` writer - l1 icahce1 clk enable"] +pub type HP_REG_L1_I1_CACHE_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L1_I0_CACHE_CLK_ON` reader - l1 icahce0 clk enable"] +pub type HP_REG_L1_I0_CACHE_CLK_ON_R = crate::BitReader; +#[doc = "Field `HP_REG_L1_I0_CACHE_CLK_ON` writer - l1 icahce0 clk enable"] +pub type HP_REG_L1_I0_CACHE_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - l2 cahce clk enable"] + #[inline(always)] + pub fn hp_reg_l2_cache_clk_on(&self) -> HP_REG_L2_CACHE_CLK_ON_R { + HP_REG_L2_CACHE_CLK_ON_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - l1 dcahce clk enable"] + #[inline(always)] + pub fn hp_reg_l1_d_cache_clk_on(&self) -> HP_REG_L1_D_CACHE_CLK_ON_R { + HP_REG_L1_D_CACHE_CLK_ON_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - l1 icahce1 clk enable"] + #[inline(always)] + pub fn hp_reg_l1_i1_cache_clk_on(&self) -> HP_REG_L1_I1_CACHE_CLK_ON_R { + HP_REG_L1_I1_CACHE_CLK_ON_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - l1 icahce0 clk enable"] + #[inline(always)] + pub fn hp_reg_l1_i0_cache_clk_on(&self) -> HP_REG_L1_I0_CACHE_CLK_ON_R { + HP_REG_L1_I0_CACHE_CLK_ON_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CACHE_CLK_CONFIG") + .field( + "hp_reg_l2_cache_clk_on", + &format_args!("{}", self.hp_reg_l2_cache_clk_on().bit()), + ) + .field( + "hp_reg_l1_d_cache_clk_on", + &format_args!("{}", self.hp_reg_l1_d_cache_clk_on().bit()), + ) + .field( + "hp_reg_l1_i1_cache_clk_on", + &format_args!("{}", self.hp_reg_l1_i1_cache_clk_on().bit()), + ) + .field( + "hp_reg_l1_i0_cache_clk_on", + &format_args!("{}", self.hp_reg_l1_i0_cache_clk_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - l2 cahce clk enable"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_cache_clk_on(&mut self) -> HP_REG_L2_CACHE_CLK_ON_W { + HP_REG_L2_CACHE_CLK_ON_W::new(self, 0) + } + #[doc = "Bit 1 - l1 dcahce clk enable"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l1_d_cache_clk_on( + &mut self, + ) -> HP_REG_L1_D_CACHE_CLK_ON_W { + HP_REG_L1_D_CACHE_CLK_ON_W::new(self, 1) + } + #[doc = "Bit 4 - l1 icahce1 clk enable"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l1_i1_cache_clk_on( + &mut self, + ) -> HP_REG_L1_I1_CACHE_CLK_ON_W { + HP_REG_L1_I1_CACHE_CLK_ON_W::new(self, 4) + } + #[doc = "Bit 5 - l1 icahce0 clk enable"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l1_i0_cache_clk_on( + &mut self, + ) -> HP_REG_L1_I0_CACHE_CLK_ON_W { + HP_REG_L1_I0_CACHE_CLK_ON_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cache_clk_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cache_clk_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CACHE_CLK_CONFIG_SPEC; +impl crate::RegisterSpec for HP_CACHE_CLK_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_cache_clk_config::R`](R) reader structure"] +impl crate::Readable for HP_CACHE_CLK_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_cache_clk_config::W`](W) writer structure"] +impl crate::Writable for HP_CACHE_CLK_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CACHE_CLK_CONFIG to value 0x33"] +impl crate::Resettable for HP_CACHE_CLK_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0x33; +} diff --git a/esp32p4/src/hp_sys/hp_cache_reset_config.rs b/esp32p4/src/hp_sys/hp_cache_reset_config.rs new file mode 100644 index 0000000000..9146b8845f --- /dev/null +++ b/esp32p4/src/hp_sys/hp_cache_reset_config.rs @@ -0,0 +1,110 @@ +#[doc = "Register `HP_CACHE_RESET_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CACHE_RESET_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L1_D_CACHE_RESET` reader - set 1 to reset l1 dcahce"] +pub type HP_REG_L1_D_CACHE_RESET_R = crate::BitReader; +#[doc = "Field `HP_REG_L1_D_CACHE_RESET` writer - set 1 to reset l1 dcahce"] +pub type HP_REG_L1_D_CACHE_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L1_I1_CACHE_RESET` reader - set 1 to reset l1 icahce1"] +pub type HP_REG_L1_I1_CACHE_RESET_R = crate::BitReader; +#[doc = "Field `HP_REG_L1_I1_CACHE_RESET` writer - set 1 to reset l1 icahce1"] +pub type HP_REG_L1_I1_CACHE_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L1_I0_CACHE_RESET` reader - set 1 to reset l1 icahce0"] +pub type HP_REG_L1_I0_CACHE_RESET_R = crate::BitReader; +#[doc = "Field `HP_REG_L1_I0_CACHE_RESET` writer - set 1 to reset l1 icahce0"] +pub type HP_REG_L1_I0_CACHE_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - set 1 to reset l1 dcahce"] + #[inline(always)] + pub fn hp_reg_l1_d_cache_reset(&self) -> HP_REG_L1_D_CACHE_RESET_R { + HP_REG_L1_D_CACHE_RESET_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - set 1 to reset l1 icahce1"] + #[inline(always)] + pub fn hp_reg_l1_i1_cache_reset(&self) -> HP_REG_L1_I1_CACHE_RESET_R { + HP_REG_L1_I1_CACHE_RESET_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - set 1 to reset l1 icahce0"] + #[inline(always)] + pub fn hp_reg_l1_i0_cache_reset(&self) -> HP_REG_L1_I0_CACHE_RESET_R { + HP_REG_L1_I0_CACHE_RESET_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CACHE_RESET_CONFIG") + .field( + "hp_reg_l1_d_cache_reset", + &format_args!("{}", self.hp_reg_l1_d_cache_reset().bit()), + ) + .field( + "hp_reg_l1_i1_cache_reset", + &format_args!("{}", self.hp_reg_l1_i1_cache_reset().bit()), + ) + .field( + "hp_reg_l1_i0_cache_reset", + &format_args!("{}", self.hp_reg_l1_i0_cache_reset().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 1 - set 1 to reset l1 dcahce"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l1_d_cache_reset( + &mut self, + ) -> HP_REG_L1_D_CACHE_RESET_W { + HP_REG_L1_D_CACHE_RESET_W::new(self, 1) + } + #[doc = "Bit 4 - set 1 to reset l1 icahce1"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l1_i1_cache_reset( + &mut self, + ) -> HP_REG_L1_I1_CACHE_RESET_W { + HP_REG_L1_I1_CACHE_RESET_W::new(self, 4) + } + #[doc = "Bit 5 - set 1 to reset l1 icahce0"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l1_i0_cache_reset( + &mut self, + ) -> HP_REG_L1_I0_CACHE_RESET_W { + HP_REG_L1_I0_CACHE_RESET_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cache_reset_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cache_reset_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CACHE_RESET_CONFIG_SPEC; +impl crate::RegisterSpec for HP_CACHE_RESET_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_cache_reset_config::R`](R) reader structure"] +impl crate::Readable for HP_CACHE_RESET_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_cache_reset_config::W`](W) writer structure"] +impl crate::Writable for HP_CACHE_RESET_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CACHE_RESET_CONFIG to value 0"] +impl crate::Resettable for HP_CACHE_RESET_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_clk_en.rs b/esp32p4/src/hp_sys/hp_clk_en.rs new file mode 100644 index 0000000000..f2a30e43ae --- /dev/null +++ b/esp32p4/src/hp_sys/hp_clk_en.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_CLK_EN` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CLK_EN` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_CLK_EN` reader - NA"] +pub type HP_REG_CLK_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_CLK_EN` writer - NA"] +pub type HP_REG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_clk_en(&self) -> HP_REG_CLK_EN_R { + HP_REG_CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CLK_EN") + .field( + "hp_reg_clk_en", + &format_args!("{}", self.hp_reg_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_clk_en(&mut self) -> HP_REG_CLK_EN_W { + HP_REG_CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_clk_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_clk_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CLK_EN_SPEC; +impl crate::RegisterSpec for HP_CLK_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_clk_en::R`](R) reader structure"] +impl crate::Readable for HP_CLK_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_clk_en::W`](W) writer structure"] +impl crate::Writable for HP_CLK_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CLK_EN to value 0"] +impl crate::Resettable for HP_CLK_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_core_ahb_timeout.rs b/esp32p4/src/hp_sys/hp_core_ahb_timeout.rs new file mode 100644 index 0000000000..ad6fafd0ba --- /dev/null +++ b/esp32p4/src/hp_sys/hp_core_ahb_timeout.rs @@ -0,0 +1,79 @@ +#[doc = "Register `HP_CORE_AHB_TIMEOUT` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CORE_AHB_TIMEOUT` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - set this field to 1 to enable hp core0&1 ahb timeout handle"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - set this field to 1 to enable hp core0&1 ahb timeout handle"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES` reader - This field used to set hp core0&1 ahb bus timeout threshold"] +pub type THRES_R = crate::FieldReader; +#[doc = "Field `THRES` writer - This field used to set hp core0&1 ahb bus timeout threshold"] +pub type THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - set this field to 1 to enable hp core0&1 ahb timeout handle"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - This field used to set hp core0&1 ahb bus timeout threshold"] + #[inline(always)] + pub fn thres(&self) -> THRES_R { + THRES_R::new(((self.bits >> 1) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CORE_AHB_TIMEOUT") + .field("en", &format_args!("{}", self.en().bit())) + .field("thres", &format_args!("{}", self.thres().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this field to 1 to enable hp core0&1 ahb timeout handle"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 1:16 - This field used to set hp core0&1 ahb bus timeout threshold"] + #[inline(always)] + #[must_use] + pub fn thres(&mut self) -> THRES_W { + THRES_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_ahb_timeout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_ahb_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CORE_AHB_TIMEOUT_SPEC; +impl crate::RegisterSpec for HP_CORE_AHB_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_core_ahb_timeout::R`](R) reader structure"] +impl crate::Readable for HP_CORE_AHB_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_core_ahb_timeout::W`](W) writer structure"] +impl crate::Writable for HP_CORE_AHB_TIMEOUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CORE_AHB_TIMEOUT to value 0x0001_ffff"] +impl crate::Resettable for HP_CORE_AHB_TIMEOUT_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_ffff; +} diff --git a/esp32p4/src/hp_sys/hp_core_dbus_timeout.rs b/esp32p4/src/hp_sys/hp_core_dbus_timeout.rs new file mode 100644 index 0000000000..4f8a048b92 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_core_dbus_timeout.rs @@ -0,0 +1,79 @@ +#[doc = "Register `HP_CORE_DBUS_TIMEOUT` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CORE_DBUS_TIMEOUT` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - set this field to 1 to enable hp core0&1 dbus timeout handle"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - set this field to 1 to enable hp core0&1 dbus timeout handle"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES` reader - This field used to set hp core0&1 dbus timeout threshold"] +pub type THRES_R = crate::FieldReader; +#[doc = "Field `THRES` writer - This field used to set hp core0&1 dbus timeout threshold"] +pub type THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - set this field to 1 to enable hp core0&1 dbus timeout handle"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - This field used to set hp core0&1 dbus timeout threshold"] + #[inline(always)] + pub fn thres(&self) -> THRES_R { + THRES_R::new(((self.bits >> 1) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CORE_DBUS_TIMEOUT") + .field("en", &format_args!("{}", self.en().bit())) + .field("thres", &format_args!("{}", self.thres().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this field to 1 to enable hp core0&1 dbus timeout handle"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 1:16 - This field used to set hp core0&1 dbus timeout threshold"] + #[inline(always)] + #[must_use] + pub fn thres(&mut self) -> THRES_W { + THRES_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_dbus_timeout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_dbus_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CORE_DBUS_TIMEOUT_SPEC; +impl crate::RegisterSpec for HP_CORE_DBUS_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_core_dbus_timeout::R`](R) reader structure"] +impl crate::Readable for HP_CORE_DBUS_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_core_dbus_timeout::W`](W) writer structure"] +impl crate::Writable for HP_CORE_DBUS_TIMEOUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CORE_DBUS_TIMEOUT to value 0x0001_ffff"] +impl crate::Resettable for HP_CORE_DBUS_TIMEOUT_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_ffff; +} diff --git a/esp32p4/src/hp_sys/hp_core_dmactive_lpcore.rs b/esp32p4/src/hp_sys/hp_core_dmactive_lpcore.rs new file mode 100644 index 0000000000..0ae7510e4f --- /dev/null +++ b/esp32p4/src/hp_sys/hp_core_dmactive_lpcore.rs @@ -0,0 +1,39 @@ +#[doc = "Register `HP_CORE_DMACTIVE_LPCORE` reader"] +pub type R = crate::R; +#[doc = "Field `HP_CORE_DMACTIVE_LPCORE` reader - hp core dmactive_lpcore value"] +pub type HP_CORE_DMACTIVE_LPCORE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - hp core dmactive_lpcore value"] + #[inline(always)] + pub fn hp_core_dmactive_lpcore(&self) -> HP_CORE_DMACTIVE_LPCORE_R { + HP_CORE_DMACTIVE_LPCORE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CORE_DMACTIVE_LPCORE") + .field( + "hp_core_dmactive_lpcore", + &format_args!("{}", self.hp_core_dmactive_lpcore().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_dmactive_lpcore::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CORE_DMACTIVE_LPCORE_SPEC; +impl crate::RegisterSpec for HP_CORE_DMACTIVE_LPCORE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_core_dmactive_lpcore::R`](R) reader structure"] +impl crate::Readable for HP_CORE_DMACTIVE_LPCORE_SPEC {} +#[doc = "`reset()` method sets HP_CORE_DMACTIVE_LPCORE to value 0"] +impl crate::Resettable for HP_CORE_DMACTIVE_LPCORE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_core_err_resp_dis.rs b/esp32p4/src/hp_sys/hp_core_err_resp_dis.rs new file mode 100644 index 0000000000..979630ad62 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_core_err_resp_dis.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_CORE_ERR_RESP_DIS` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CORE_ERR_RESP_DIS` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CORE_ERR_RESP_DIS` reader - Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp."] +pub type HP_CORE_ERR_RESP_DIS_R = crate::FieldReader; +#[doc = "Field `HP_CORE_ERR_RESP_DIS` writer - Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp."] +pub type HP_CORE_ERR_RESP_DIS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp."] + #[inline(always)] + pub fn hp_core_err_resp_dis(&self) -> HP_CORE_ERR_RESP_DIS_R { + HP_CORE_ERR_RESP_DIS_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CORE_ERR_RESP_DIS") + .field( + "hp_core_err_resp_dis", + &format_args!("{}", self.hp_core_err_resp_dis().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp."] + #[inline(always)] + #[must_use] + pub fn hp_core_err_resp_dis(&mut self) -> HP_CORE_ERR_RESP_DIS_W { + HP_CORE_ERR_RESP_DIS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_err_resp_dis::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_err_resp_dis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CORE_ERR_RESP_DIS_SPEC; +impl crate::RegisterSpec for HP_CORE_ERR_RESP_DIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_core_err_resp_dis::R`](R) reader structure"] +impl crate::Readable for HP_CORE_ERR_RESP_DIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_core_err_resp_dis::W`](W) writer structure"] +impl crate::Writable for HP_CORE_ERR_RESP_DIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CORE_ERR_RESP_DIS to value 0"] +impl crate::Resettable for HP_CORE_ERR_RESP_DIS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_core_ibus_timeout.rs b/esp32p4/src/hp_sys/hp_core_ibus_timeout.rs new file mode 100644 index 0000000000..3c82565530 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_core_ibus_timeout.rs @@ -0,0 +1,79 @@ +#[doc = "Register `HP_CORE_IBUS_TIMEOUT` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CORE_IBUS_TIMEOUT` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - set this field to 1 to enable hp core0&1 ibus timeout handle"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - set this field to 1 to enable hp core0&1 ibus timeout handle"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES` reader - This field used to set hp core0&1 ibus timeout threshold"] +pub type THRES_R = crate::FieldReader; +#[doc = "Field `THRES` writer - This field used to set hp core0&1 ibus timeout threshold"] +pub type THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - set this field to 1 to enable hp core0&1 ibus timeout handle"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - This field used to set hp core0&1 ibus timeout threshold"] + #[inline(always)] + pub fn thres(&self) -> THRES_R { + THRES_R::new(((self.bits >> 1) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CORE_IBUS_TIMEOUT") + .field("en", &format_args!("{}", self.en().bit())) + .field("thres", &format_args!("{}", self.thres().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this field to 1 to enable hp core0&1 ibus timeout handle"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 1:16 - This field used to set hp core0&1 ibus timeout threshold"] + #[inline(always)] + #[must_use] + pub fn thres(&mut self) -> THRES_W { + THRES_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_ibus_timeout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_ibus_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CORE_IBUS_TIMEOUT_SPEC; +impl crate::RegisterSpec for HP_CORE_IBUS_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_core_ibus_timeout::R`](R) reader structure"] +impl crate::Readable for HP_CORE_IBUS_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_core_ibus_timeout::W`](W) writer structure"] +impl crate::Writable for HP_CORE_IBUS_TIMEOUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CORE_IBUS_TIMEOUT to value 0x0001_ffff"] +impl crate::Resettable for HP_CORE_IBUS_TIMEOUT_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_ffff; +} diff --git a/esp32p4/src/hp_sys/hp_core_timeout_int_clr.rs b/esp32p4/src/hp_sys/hp_core_timeout_int_clr.rs new file mode 100644 index 0000000000..9d6a86e0d8 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_core_timeout_int_clr.rs @@ -0,0 +1,94 @@ +#[doc = "Register `HP_CORE_TIMEOUT_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CORE0_AHB_TIMEOUT_INT_CLR` writer - Write 1 to clear hp_core0_ahb_timeout int"] +pub type HP_CORE0_AHB_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE1_AHB_TIMEOUT_INT_CLR` writer - Write 1 to clear hp_core1_ahb_timeout int"] +pub type HP_CORE1_AHB_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE0_IBUS_TIMEOUT_INT_CLR` writer - Write 1 to clear hp_core0_ibus_timeout int"] +pub type HP_CORE0_IBUS_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE1_IBUS_TIMEOUT_INT_CLR` writer - Write 1 to clear hp_core1_ibus_timeout int"] +pub type HP_CORE1_IBUS_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE0_DBUS_TIMEOUT_INT_CLR` writer - Write 1 to clear hp_core0_dbus_timeout int"] +pub type HP_CORE0_DBUS_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE1_DBUS_TIMEOUT_INT_CLR` writer - Write 1 to clear hp_core1_dbus_timeout int"] +pub type HP_CORE1_DBUS_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to clear hp_core0_ahb_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core0_ahb_timeout_int_clr( + &mut self, + ) -> HP_CORE0_AHB_TIMEOUT_INT_CLR_W { + HP_CORE0_AHB_TIMEOUT_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to clear hp_core1_ahb_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core1_ahb_timeout_int_clr( + &mut self, + ) -> HP_CORE1_AHB_TIMEOUT_INT_CLR_W { + HP_CORE1_AHB_TIMEOUT_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to clear hp_core0_ibus_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core0_ibus_timeout_int_clr( + &mut self, + ) -> HP_CORE0_IBUS_TIMEOUT_INT_CLR_W { + HP_CORE0_IBUS_TIMEOUT_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to clear hp_core1_ibus_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core1_ibus_timeout_int_clr( + &mut self, + ) -> HP_CORE1_IBUS_TIMEOUT_INT_CLR_W { + HP_CORE1_IBUS_TIMEOUT_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to clear hp_core0_dbus_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core0_dbus_timeout_int_clr( + &mut self, + ) -> HP_CORE0_DBUS_TIMEOUT_INT_CLR_W { + HP_CORE0_DBUS_TIMEOUT_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to clear hp_core1_dbus_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core1_dbus_timeout_int_clr( + &mut self, + ) -> HP_CORE1_DBUS_TIMEOUT_INT_CLR_W { + HP_CORE1_DBUS_TIMEOUT_INT_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_timeout_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CORE_TIMEOUT_INT_CLR_SPEC; +impl crate::RegisterSpec for HP_CORE_TIMEOUT_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_core_timeout_int_clr::W`](W) writer structure"] +impl crate::Writable for HP_CORE_TIMEOUT_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CORE_TIMEOUT_INT_CLR to value 0"] +impl crate::Resettable for HP_CORE_TIMEOUT_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_core_timeout_int_ena.rs b/esp32p4/src/hp_sys/hp_core_timeout_int_ena.rs new file mode 100644 index 0000000000..f7c52bfc24 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_core_timeout_int_ena.rs @@ -0,0 +1,173 @@ +#[doc = "Register `HP_CORE_TIMEOUT_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CORE_TIMEOUT_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CORE0_AHB_TIMEOUT_INT_ENA` reader - Write 1 to enable hp_core0_ahb_timeout int"] +pub type HP_CORE0_AHB_TIMEOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_CORE0_AHB_TIMEOUT_INT_ENA` writer - Write 1 to enable hp_core0_ahb_timeout int"] +pub type HP_CORE0_AHB_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE1_AHB_TIMEOUT_INT_ENA` reader - Write 1 to enable hp_core1_ahb_timeout int"] +pub type HP_CORE1_AHB_TIMEOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_CORE1_AHB_TIMEOUT_INT_ENA` writer - Write 1 to enable hp_core1_ahb_timeout int"] +pub type HP_CORE1_AHB_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE0_IBUS_TIMEOUT_INT_ENA` reader - Write 1 to enable hp_core0_ibus_timeout int"] +pub type HP_CORE0_IBUS_TIMEOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_CORE0_IBUS_TIMEOUT_INT_ENA` writer - Write 1 to enable hp_core0_ibus_timeout int"] +pub type HP_CORE0_IBUS_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE1_IBUS_TIMEOUT_INT_ENA` reader - Write 1 to enable hp_core1_ibus_timeout int"] +pub type HP_CORE1_IBUS_TIMEOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_CORE1_IBUS_TIMEOUT_INT_ENA` writer - Write 1 to enable hp_core1_ibus_timeout int"] +pub type HP_CORE1_IBUS_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE0_DBUS_TIMEOUT_INT_ENA` reader - Write 1 to enable hp_core0_dbus_timeout int"] +pub type HP_CORE0_DBUS_TIMEOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_CORE0_DBUS_TIMEOUT_INT_ENA` writer - Write 1 to enable hp_core0_dbus_timeout int"] +pub type HP_CORE0_DBUS_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE1_DBUS_TIMEOUT_INT_ENA` reader - Write 1 to enable hp_core1_dbus_timeout int"] +pub type HP_CORE1_DBUS_TIMEOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_CORE1_DBUS_TIMEOUT_INT_ENA` writer - Write 1 to enable hp_core1_dbus_timeout int"] +pub type HP_CORE1_DBUS_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 to enable hp_core0_ahb_timeout int"] + #[inline(always)] + pub fn hp_core0_ahb_timeout_int_ena(&self) -> HP_CORE0_AHB_TIMEOUT_INT_ENA_R { + HP_CORE0_AHB_TIMEOUT_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to enable hp_core1_ahb_timeout int"] + #[inline(always)] + pub fn hp_core1_ahb_timeout_int_ena(&self) -> HP_CORE1_AHB_TIMEOUT_INT_ENA_R { + HP_CORE1_AHB_TIMEOUT_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 to enable hp_core0_ibus_timeout int"] + #[inline(always)] + pub fn hp_core0_ibus_timeout_int_ena(&self) -> HP_CORE0_IBUS_TIMEOUT_INT_ENA_R { + HP_CORE0_IBUS_TIMEOUT_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1 to enable hp_core1_ibus_timeout int"] + #[inline(always)] + pub fn hp_core1_ibus_timeout_int_ena(&self) -> HP_CORE1_IBUS_TIMEOUT_INT_ENA_R { + HP_CORE1_IBUS_TIMEOUT_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write 1 to enable hp_core0_dbus_timeout int"] + #[inline(always)] + pub fn hp_core0_dbus_timeout_int_ena(&self) -> HP_CORE0_DBUS_TIMEOUT_INT_ENA_R { + HP_CORE0_DBUS_TIMEOUT_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write 1 to enable hp_core1_dbus_timeout int"] + #[inline(always)] + pub fn hp_core1_dbus_timeout_int_ena(&self) -> HP_CORE1_DBUS_TIMEOUT_INT_ENA_R { + HP_CORE1_DBUS_TIMEOUT_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CORE_TIMEOUT_INT_ENA") + .field( + "hp_core0_ahb_timeout_int_ena", + &format_args!("{}", self.hp_core0_ahb_timeout_int_ena().bit()), + ) + .field( + "hp_core1_ahb_timeout_int_ena", + &format_args!("{}", self.hp_core1_ahb_timeout_int_ena().bit()), + ) + .field( + "hp_core0_ibus_timeout_int_ena", + &format_args!("{}", self.hp_core0_ibus_timeout_int_ena().bit()), + ) + .field( + "hp_core1_ibus_timeout_int_ena", + &format_args!("{}", self.hp_core1_ibus_timeout_int_ena().bit()), + ) + .field( + "hp_core0_dbus_timeout_int_ena", + &format_args!("{}", self.hp_core0_dbus_timeout_int_ena().bit()), + ) + .field( + "hp_core1_dbus_timeout_int_ena", + &format_args!("{}", self.hp_core1_dbus_timeout_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to enable hp_core0_ahb_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core0_ahb_timeout_int_ena( + &mut self, + ) -> HP_CORE0_AHB_TIMEOUT_INT_ENA_W { + HP_CORE0_AHB_TIMEOUT_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to enable hp_core1_ahb_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core1_ahb_timeout_int_ena( + &mut self, + ) -> HP_CORE1_AHB_TIMEOUT_INT_ENA_W { + HP_CORE1_AHB_TIMEOUT_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to enable hp_core0_ibus_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core0_ibus_timeout_int_ena( + &mut self, + ) -> HP_CORE0_IBUS_TIMEOUT_INT_ENA_W { + HP_CORE0_IBUS_TIMEOUT_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to enable hp_core1_ibus_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core1_ibus_timeout_int_ena( + &mut self, + ) -> HP_CORE1_IBUS_TIMEOUT_INT_ENA_W { + HP_CORE1_IBUS_TIMEOUT_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to enable hp_core0_dbus_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core0_dbus_timeout_int_ena( + &mut self, + ) -> HP_CORE0_DBUS_TIMEOUT_INT_ENA_W { + HP_CORE0_DBUS_TIMEOUT_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to enable hp_core1_dbus_timeout int"] + #[inline(always)] + #[must_use] + pub fn hp_core1_dbus_timeout_int_ena( + &mut self, + ) -> HP_CORE1_DBUS_TIMEOUT_INT_ENA_W { + HP_CORE1_DBUS_TIMEOUT_INT_ENA_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_timeout_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_timeout_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CORE_TIMEOUT_INT_ENA_SPEC; +impl crate::RegisterSpec for HP_CORE_TIMEOUT_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_core_timeout_int_ena::R`](R) reader structure"] +impl crate::Readable for HP_CORE_TIMEOUT_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_core_timeout_int_ena::W`](W) writer structure"] +impl crate::Writable for HP_CORE_TIMEOUT_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CORE_TIMEOUT_INT_ENA to value 0"] +impl crate::Resettable for HP_CORE_TIMEOUT_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_core_timeout_int_raw.rs b/esp32p4/src/hp_sys/hp_core_timeout_int_raw.rs new file mode 100644 index 0000000000..feda230350 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_core_timeout_int_raw.rs @@ -0,0 +1,173 @@ +#[doc = "Register `HP_CORE_TIMEOUT_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CORE_TIMEOUT_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CORE0_AHB_TIMEOUT_INT_RAW` reader - the raw interrupt status of hp core0 ahb timeout"] +pub type HP_CORE0_AHB_TIMEOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_CORE0_AHB_TIMEOUT_INT_RAW` writer - the raw interrupt status of hp core0 ahb timeout"] +pub type HP_CORE0_AHB_TIMEOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE1_AHB_TIMEOUT_INT_RAW` reader - the raw interrupt status of hp core1 ahb timeout"] +pub type HP_CORE1_AHB_TIMEOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_CORE1_AHB_TIMEOUT_INT_RAW` writer - the raw interrupt status of hp core1 ahb timeout"] +pub type HP_CORE1_AHB_TIMEOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE0_IBUS_TIMEOUT_INT_RAW` reader - the raw interrupt status of hp core0 ibus timeout"] +pub type HP_CORE0_IBUS_TIMEOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_CORE0_IBUS_TIMEOUT_INT_RAW` writer - the raw interrupt status of hp core0 ibus timeout"] +pub type HP_CORE0_IBUS_TIMEOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE1_IBUS_TIMEOUT_INT_RAW` reader - the raw interrupt status of hp core1 ibus timeout"] +pub type HP_CORE1_IBUS_TIMEOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_CORE1_IBUS_TIMEOUT_INT_RAW` writer - the raw interrupt status of hp core1 ibus timeout"] +pub type HP_CORE1_IBUS_TIMEOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE0_DBUS_TIMEOUT_INT_RAW` reader - the raw interrupt status of hp core0 dbus timeout"] +pub type HP_CORE0_DBUS_TIMEOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_CORE0_DBUS_TIMEOUT_INT_RAW` writer - the raw interrupt status of hp core0 dbus timeout"] +pub type HP_CORE0_DBUS_TIMEOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CORE1_DBUS_TIMEOUT_INT_RAW` reader - the raw interrupt status of hp core1 dbus timeout"] +pub type HP_CORE1_DBUS_TIMEOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_CORE1_DBUS_TIMEOUT_INT_RAW` writer - the raw interrupt status of hp core1 dbus timeout"] +pub type HP_CORE1_DBUS_TIMEOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - the raw interrupt status of hp core0 ahb timeout"] + #[inline(always)] + pub fn hp_core0_ahb_timeout_int_raw(&self) -> HP_CORE0_AHB_TIMEOUT_INT_RAW_R { + HP_CORE0_AHB_TIMEOUT_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - the raw interrupt status of hp core1 ahb timeout"] + #[inline(always)] + pub fn hp_core1_ahb_timeout_int_raw(&self) -> HP_CORE1_AHB_TIMEOUT_INT_RAW_R { + HP_CORE1_AHB_TIMEOUT_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - the raw interrupt status of hp core0 ibus timeout"] + #[inline(always)] + pub fn hp_core0_ibus_timeout_int_raw(&self) -> HP_CORE0_IBUS_TIMEOUT_INT_RAW_R { + HP_CORE0_IBUS_TIMEOUT_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - the raw interrupt status of hp core1 ibus timeout"] + #[inline(always)] + pub fn hp_core1_ibus_timeout_int_raw(&self) -> HP_CORE1_IBUS_TIMEOUT_INT_RAW_R { + HP_CORE1_IBUS_TIMEOUT_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the raw interrupt status of hp core0 dbus timeout"] + #[inline(always)] + pub fn hp_core0_dbus_timeout_int_raw(&self) -> HP_CORE0_DBUS_TIMEOUT_INT_RAW_R { + HP_CORE0_DBUS_TIMEOUT_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - the raw interrupt status of hp core1 dbus timeout"] + #[inline(always)] + pub fn hp_core1_dbus_timeout_int_raw(&self) -> HP_CORE1_DBUS_TIMEOUT_INT_RAW_R { + HP_CORE1_DBUS_TIMEOUT_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CORE_TIMEOUT_INT_RAW") + .field( + "hp_core0_ahb_timeout_int_raw", + &format_args!("{}", self.hp_core0_ahb_timeout_int_raw().bit()), + ) + .field( + "hp_core1_ahb_timeout_int_raw", + &format_args!("{}", self.hp_core1_ahb_timeout_int_raw().bit()), + ) + .field( + "hp_core0_ibus_timeout_int_raw", + &format_args!("{}", self.hp_core0_ibus_timeout_int_raw().bit()), + ) + .field( + "hp_core1_ibus_timeout_int_raw", + &format_args!("{}", self.hp_core1_ibus_timeout_int_raw().bit()), + ) + .field( + "hp_core0_dbus_timeout_int_raw", + &format_args!("{}", self.hp_core0_dbus_timeout_int_raw().bit()), + ) + .field( + "hp_core1_dbus_timeout_int_raw", + &format_args!("{}", self.hp_core1_dbus_timeout_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - the raw interrupt status of hp core0 ahb timeout"] + #[inline(always)] + #[must_use] + pub fn hp_core0_ahb_timeout_int_raw( + &mut self, + ) -> HP_CORE0_AHB_TIMEOUT_INT_RAW_W { + HP_CORE0_AHB_TIMEOUT_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - the raw interrupt status of hp core1 ahb timeout"] + #[inline(always)] + #[must_use] + pub fn hp_core1_ahb_timeout_int_raw( + &mut self, + ) -> HP_CORE1_AHB_TIMEOUT_INT_RAW_W { + HP_CORE1_AHB_TIMEOUT_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - the raw interrupt status of hp core0 ibus timeout"] + #[inline(always)] + #[must_use] + pub fn hp_core0_ibus_timeout_int_raw( + &mut self, + ) -> HP_CORE0_IBUS_TIMEOUT_INT_RAW_W { + HP_CORE0_IBUS_TIMEOUT_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - the raw interrupt status of hp core1 ibus timeout"] + #[inline(always)] + #[must_use] + pub fn hp_core1_ibus_timeout_int_raw( + &mut self, + ) -> HP_CORE1_IBUS_TIMEOUT_INT_RAW_W { + HP_CORE1_IBUS_TIMEOUT_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - the raw interrupt status of hp core0 dbus timeout"] + #[inline(always)] + #[must_use] + pub fn hp_core0_dbus_timeout_int_raw( + &mut self, + ) -> HP_CORE0_DBUS_TIMEOUT_INT_RAW_W { + HP_CORE0_DBUS_TIMEOUT_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - the raw interrupt status of hp core1 dbus timeout"] + #[inline(always)] + #[must_use] + pub fn hp_core1_dbus_timeout_int_raw( + &mut self, + ) -> HP_CORE1_DBUS_TIMEOUT_INT_RAW_W { + HP_CORE1_DBUS_TIMEOUT_INT_RAW_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Hp core bus timeout interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_timeout_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_timeout_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CORE_TIMEOUT_INT_RAW_SPEC; +impl crate::RegisterSpec for HP_CORE_TIMEOUT_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_core_timeout_int_raw::R`](R) reader structure"] +impl crate::Readable for HP_CORE_TIMEOUT_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_core_timeout_int_raw::W`](W) writer structure"] +impl crate::Writable for HP_CORE_TIMEOUT_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CORE_TIMEOUT_INT_RAW to value 0"] +impl crate::Resettable for HP_CORE_TIMEOUT_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_core_timeout_int_st.rs b/esp32p4/src/hp_sys/hp_core_timeout_int_st.rs new file mode 100644 index 0000000000..b5301c26c5 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_core_timeout_int_st.rs @@ -0,0 +1,94 @@ +#[doc = "Register `HP_CORE_TIMEOUT_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `HP_CORE0_AHB_TIMEOUT_INT_ST` reader - the masked interrupt status of hp core0 ahb timeout"] +pub type HP_CORE0_AHB_TIMEOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `HP_CORE1_AHB_TIMEOUT_INT_ST` reader - the masked interrupt status of hp core1 ahb timeout"] +pub type HP_CORE1_AHB_TIMEOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `HP_CORE0_IBUS_TIMEOUT_INT_ST` reader - the masked interrupt status of hp core0 ibus timeout"] +pub type HP_CORE0_IBUS_TIMEOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `HP_CORE1_IBUS_TIMEOUT_INT_ST` reader - the masked interrupt status of hp core1 ibus timeout"] +pub type HP_CORE1_IBUS_TIMEOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `HP_CORE0_DBUS_TIMEOUT_INT_ST` reader - the masked interrupt status of hp core0 dbus timeout"] +pub type HP_CORE0_DBUS_TIMEOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `HP_CORE1_DBUS_TIMEOUT_INT_ST` reader - the masked interrupt status of hp core1 dbus timeout"] +pub type HP_CORE1_DBUS_TIMEOUT_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - the masked interrupt status of hp core0 ahb timeout"] + #[inline(always)] + pub fn hp_core0_ahb_timeout_int_st(&self) -> HP_CORE0_AHB_TIMEOUT_INT_ST_R { + HP_CORE0_AHB_TIMEOUT_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - the masked interrupt status of hp core1 ahb timeout"] + #[inline(always)] + pub fn hp_core1_ahb_timeout_int_st(&self) -> HP_CORE1_AHB_TIMEOUT_INT_ST_R { + HP_CORE1_AHB_TIMEOUT_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - the masked interrupt status of hp core0 ibus timeout"] + #[inline(always)] + pub fn hp_core0_ibus_timeout_int_st(&self) -> HP_CORE0_IBUS_TIMEOUT_INT_ST_R { + HP_CORE0_IBUS_TIMEOUT_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - the masked interrupt status of hp core1 ibus timeout"] + #[inline(always)] + pub fn hp_core1_ibus_timeout_int_st(&self) -> HP_CORE1_IBUS_TIMEOUT_INT_ST_R { + HP_CORE1_IBUS_TIMEOUT_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the masked interrupt status of hp core0 dbus timeout"] + #[inline(always)] + pub fn hp_core0_dbus_timeout_int_st(&self) -> HP_CORE0_DBUS_TIMEOUT_INT_ST_R { + HP_CORE0_DBUS_TIMEOUT_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - the masked interrupt status of hp core1 dbus timeout"] + #[inline(always)] + pub fn hp_core1_dbus_timeout_int_st(&self) -> HP_CORE1_DBUS_TIMEOUT_INT_ST_R { + HP_CORE1_DBUS_TIMEOUT_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CORE_TIMEOUT_INT_ST") + .field( + "hp_core0_ahb_timeout_int_st", + &format_args!("{}", self.hp_core0_ahb_timeout_int_st().bit()), + ) + .field( + "hp_core1_ahb_timeout_int_st", + &format_args!("{}", self.hp_core1_ahb_timeout_int_st().bit()), + ) + .field( + "hp_core0_ibus_timeout_int_st", + &format_args!("{}", self.hp_core0_ibus_timeout_int_st().bit()), + ) + .field( + "hp_core1_ibus_timeout_int_st", + &format_args!("{}", self.hp_core1_ibus_timeout_int_st().bit()), + ) + .field( + "hp_core0_dbus_timeout_int_st", + &format_args!("{}", self.hp_core0_dbus_timeout_int_st().bit()), + ) + .field( + "hp_core1_dbus_timeout_int_st", + &format_args!("{}", self.hp_core1_dbus_timeout_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_timeout_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CORE_TIMEOUT_INT_ST_SPEC; +impl crate::RegisterSpec for HP_CORE_TIMEOUT_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_core_timeout_int_st::R`](R) reader structure"] +impl crate::Readable for HP_CORE_TIMEOUT_INT_ST_SPEC {} +#[doc = "`reset()` method sets HP_CORE_TIMEOUT_INT_ST to value 0"] +impl crate::Resettable for HP_CORE_TIMEOUT_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_cpu_corestalled_st.rs b/esp32p4/src/hp_sys/hp_cpu_corestalled_st.rs new file mode 100644 index 0000000000..7c03c559c5 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_cpu_corestalled_st.rs @@ -0,0 +1,50 @@ +#[doc = "Register `HP_CPU_CORESTALLED_ST` reader"] +pub type R = crate::R; +#[doc = "Field `HP_REG_CORE0_CORESTALLED_ST` reader - hp core0 corestalled status"] +pub type HP_REG_CORE0_CORESTALLED_ST_R = crate::BitReader; +#[doc = "Field `HP_REG_CORE1_CORESTALLED_ST` reader - hp core1 corestalled status"] +pub type HP_REG_CORE1_CORESTALLED_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - hp core0 corestalled status"] + #[inline(always)] + pub fn hp_reg_core0_corestalled_st(&self) -> HP_REG_CORE0_CORESTALLED_ST_R { + HP_REG_CORE0_CORESTALLED_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - hp core1 corestalled status"] + #[inline(always)] + pub fn hp_reg_core1_corestalled_st(&self) -> HP_REG_CORE1_CORESTALLED_ST_R { + HP_REG_CORE1_CORESTALLED_ST_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CPU_CORESTALLED_ST") + .field( + "hp_reg_core0_corestalled_st", + &format_args!("{}", self.hp_reg_core0_corestalled_st().bit()), + ) + .field( + "hp_reg_core1_corestalled_st", + &format_args!("{}", self.hp_reg_core1_corestalled_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_corestalled_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CPU_CORESTALLED_ST_SPEC; +impl crate::RegisterSpec for HP_CPU_CORESTALLED_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_cpu_corestalled_st::R`](R) reader structure"] +impl crate::Readable for HP_CPU_CORESTALLED_ST_SPEC {} +#[doc = "`reset()` method sets HP_CPU_CORESTALLED_ST to value 0"] +impl crate::Resettable for HP_CPU_CORESTALLED_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_0.rs b/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_0.rs new file mode 100644 index 0000000000..261acdd041 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_CPU_INT_FROM_CPU_0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CPU_INT_FROM_CPU_0` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CPU_INT_FROM_CPU_0` reader - set 1 will triger a interrupt"] +pub type HP_CPU_INT_FROM_CPU_0_R = crate::BitReader; +#[doc = "Field `HP_CPU_INT_FROM_CPU_0` writer - set 1 will triger a interrupt"] +pub type HP_CPU_INT_FROM_CPU_0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - set 1 will triger a interrupt"] + #[inline(always)] + pub fn hp_cpu_int_from_cpu_0(&self) -> HP_CPU_INT_FROM_CPU_0_R { + HP_CPU_INT_FROM_CPU_0_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CPU_INT_FROM_CPU_0") + .field( + "hp_cpu_int_from_cpu_0", + &format_args!("{}", self.hp_cpu_int_from_cpu_0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set 1 will triger a interrupt"] + #[inline(always)] + #[must_use] + pub fn hp_cpu_int_from_cpu_0(&mut self) -> HP_CPU_INT_FROM_CPU_0_W { + HP_CPU_INT_FROM_CPU_0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_int_from_cpu_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cpu_int_from_cpu_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CPU_INT_FROM_CPU_0_SPEC; +impl crate::RegisterSpec for HP_CPU_INT_FROM_CPU_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_cpu_int_from_cpu_0::R`](R) reader structure"] +impl crate::Readable for HP_CPU_INT_FROM_CPU_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_cpu_int_from_cpu_0::W`](W) writer structure"] +impl crate::Writable for HP_CPU_INT_FROM_CPU_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CPU_INT_FROM_CPU_0 to value 0"] +impl crate::Resettable for HP_CPU_INT_FROM_CPU_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_1.rs b/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_1.rs new file mode 100644 index 0000000000..de2d2e9f33 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_CPU_INT_FROM_CPU_1` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CPU_INT_FROM_CPU_1` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CPU_INT_FROM_CPU_1` reader - set 1 will triger a interrupt"] +pub type HP_CPU_INT_FROM_CPU_1_R = crate::BitReader; +#[doc = "Field `HP_CPU_INT_FROM_CPU_1` writer - set 1 will triger a interrupt"] +pub type HP_CPU_INT_FROM_CPU_1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - set 1 will triger a interrupt"] + #[inline(always)] + pub fn hp_cpu_int_from_cpu_1(&self) -> HP_CPU_INT_FROM_CPU_1_R { + HP_CPU_INT_FROM_CPU_1_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CPU_INT_FROM_CPU_1") + .field( + "hp_cpu_int_from_cpu_1", + &format_args!("{}", self.hp_cpu_int_from_cpu_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set 1 will triger a interrupt"] + #[inline(always)] + #[must_use] + pub fn hp_cpu_int_from_cpu_1(&mut self) -> HP_CPU_INT_FROM_CPU_1_W { + HP_CPU_INT_FROM_CPU_1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_int_from_cpu_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cpu_int_from_cpu_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CPU_INT_FROM_CPU_1_SPEC; +impl crate::RegisterSpec for HP_CPU_INT_FROM_CPU_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_cpu_int_from_cpu_1::R`](R) reader structure"] +impl crate::Readable for HP_CPU_INT_FROM_CPU_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_cpu_int_from_cpu_1::W`](W) writer structure"] +impl crate::Writable for HP_CPU_INT_FROM_CPU_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CPU_INT_FROM_CPU_1 to value 0"] +impl crate::Resettable for HP_CPU_INT_FROM_CPU_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_2.rs b/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_2.rs new file mode 100644 index 0000000000..8690bdca6c --- /dev/null +++ b/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_CPU_INT_FROM_CPU_2` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CPU_INT_FROM_CPU_2` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CPU_INT_FROM_CPU_2` reader - set 1 will triger a interrupt"] +pub type HP_CPU_INT_FROM_CPU_2_R = crate::BitReader; +#[doc = "Field `HP_CPU_INT_FROM_CPU_2` writer - set 1 will triger a interrupt"] +pub type HP_CPU_INT_FROM_CPU_2_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - set 1 will triger a interrupt"] + #[inline(always)] + pub fn hp_cpu_int_from_cpu_2(&self) -> HP_CPU_INT_FROM_CPU_2_R { + HP_CPU_INT_FROM_CPU_2_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CPU_INT_FROM_CPU_2") + .field( + "hp_cpu_int_from_cpu_2", + &format_args!("{}", self.hp_cpu_int_from_cpu_2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set 1 will triger a interrupt"] + #[inline(always)] + #[must_use] + pub fn hp_cpu_int_from_cpu_2(&mut self) -> HP_CPU_INT_FROM_CPU_2_W { + HP_CPU_INT_FROM_CPU_2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_int_from_cpu_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cpu_int_from_cpu_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CPU_INT_FROM_CPU_2_SPEC; +impl crate::RegisterSpec for HP_CPU_INT_FROM_CPU_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_cpu_int_from_cpu_2::R`](R) reader structure"] +impl crate::Readable for HP_CPU_INT_FROM_CPU_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_cpu_int_from_cpu_2::W`](W) writer structure"] +impl crate::Writable for HP_CPU_INT_FROM_CPU_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CPU_INT_FROM_CPU_2 to value 0"] +impl crate::Resettable for HP_CPU_INT_FROM_CPU_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_3.rs b/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_3.rs new file mode 100644 index 0000000000..bf63c97d55 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_cpu_int_from_cpu_3.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_CPU_INT_FROM_CPU_3` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CPU_INT_FROM_CPU_3` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CPU_INT_FROM_CPU_3` reader - set 1 will triger a interrupt"] +pub type HP_CPU_INT_FROM_CPU_3_R = crate::BitReader; +#[doc = "Field `HP_CPU_INT_FROM_CPU_3` writer - set 1 will triger a interrupt"] +pub type HP_CPU_INT_FROM_CPU_3_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - set 1 will triger a interrupt"] + #[inline(always)] + pub fn hp_cpu_int_from_cpu_3(&self) -> HP_CPU_INT_FROM_CPU_3_R { + HP_CPU_INT_FROM_CPU_3_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CPU_INT_FROM_CPU_3") + .field( + "hp_cpu_int_from_cpu_3", + &format_args!("{}", self.hp_cpu_int_from_cpu_3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set 1 will triger a interrupt"] + #[inline(always)] + #[must_use] + pub fn hp_cpu_int_from_cpu_3(&mut self) -> HP_CPU_INT_FROM_CPU_3_W { + HP_CPU_INT_FROM_CPU_3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_int_from_cpu_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cpu_int_from_cpu_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CPU_INT_FROM_CPU_3_SPEC; +impl crate::RegisterSpec for HP_CPU_INT_FROM_CPU_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_cpu_int_from_cpu_3::R`](R) reader structure"] +impl crate::Readable for HP_CPU_INT_FROM_CPU_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_cpu_int_from_cpu_3::W`](W) writer structure"] +impl crate::Writable for HP_CPU_INT_FROM_CPU_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CPU_INT_FROM_CPU_3 to value 0"] +impl crate::Resettable for HP_CPU_INT_FROM_CPU_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_cpu_waiti_conf.rs b/esp32p4/src/hp_sys/hp_cpu_waiti_conf.rs new file mode 100644 index 0000000000..c5c34ff58d --- /dev/null +++ b/esp32p4/src/hp_sys/hp_cpu_waiti_conf.rs @@ -0,0 +1,87 @@ +#[doc = "Register `HP_CPU_WAITI_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CPU_WAITI_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CPU_WAIT_MODE_FORCE_ON` reader - Set 1 to force cpu_waiti_clk enable."] +pub type HP_CPU_WAIT_MODE_FORCE_ON_R = crate::BitReader; +#[doc = "Field `HP_CPU_WAIT_MODE_FORCE_ON` writer - Set 1 to force cpu_waiti_clk enable."] +pub type HP_CPU_WAIT_MODE_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CPU_WAITI_DELAY_NUM` reader - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"] +pub type HP_CPU_WAITI_DELAY_NUM_R = crate::FieldReader; +#[doc = "Field `HP_CPU_WAITI_DELAY_NUM` writer - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"] +pub type HP_CPU_WAITI_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - Set 1 to force cpu_waiti_clk enable."] + #[inline(always)] + pub fn hp_cpu_wait_mode_force_on(&self) -> HP_CPU_WAIT_MODE_FORCE_ON_R { + HP_CPU_WAIT_MODE_FORCE_ON_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:4 - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"] + #[inline(always)] + pub fn hp_cpu_waiti_delay_num(&self) -> HP_CPU_WAITI_DELAY_NUM_R { + HP_CPU_WAITI_DELAY_NUM_R::new(((self.bits >> 1) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CPU_WAITI_CONF") + .field( + "hp_cpu_wait_mode_force_on", + &format_args!("{}", self.hp_cpu_wait_mode_force_on().bit()), + ) + .field( + "hp_cpu_waiti_delay_num", + &format_args!("{}", self.hp_cpu_waiti_delay_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 to force cpu_waiti_clk enable."] + #[inline(always)] + #[must_use] + pub fn hp_cpu_wait_mode_force_on( + &mut self, + ) -> HP_CPU_WAIT_MODE_FORCE_ON_W { + HP_CPU_WAIT_MODE_FORCE_ON_W::new(self, 0) + } + #[doc = "Bits 1:4 - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"] + #[inline(always)] + #[must_use] + pub fn hp_cpu_waiti_delay_num(&mut self) -> HP_CPU_WAITI_DELAY_NUM_W { + HP_CPU_WAITI_DELAY_NUM_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "CPU_WAITI configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_cpu_waiti_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_cpu_waiti_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CPU_WAITI_CONF_SPEC; +impl crate::RegisterSpec for HP_CPU_WAITI_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_cpu_waiti_conf::R`](R) reader structure"] +impl crate::Readable for HP_CPU_WAITI_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_cpu_waiti_conf::W`](W) writer structure"] +impl crate::Writable for HP_CPU_WAITI_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CPU_WAITI_CONF to value 0x01"] +impl crate::Resettable for HP_CPU_WAITI_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/hp_sys/hp_crypto_ctrl.rs b/esp32p4/src/hp_sys/hp_crypto_ctrl.rs new file mode 100644 index 0000000000..957b9c1860 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_crypto_ctrl.rs @@ -0,0 +1,131 @@ +#[doc = "Register `HP_CRYPTO_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CRYPTO_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_ENABLE_SPI_MANUAL_ENCRYPT` reader - NA"] +pub type HP_REG_ENABLE_SPI_MANUAL_ENCRYPT_R = crate::BitReader; +#[doc = "Field `HP_REG_ENABLE_SPI_MANUAL_ENCRYPT` writer - NA"] +pub type HP_REG_ENABLE_SPI_MANUAL_ENCRYPT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT` reader - NA"] +pub type HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_R = crate::BitReader; +#[doc = "Field `HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT` writer - NA"] +pub type HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT` reader - NA"] +pub type HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_R = crate::BitReader; +#[doc = "Field `HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT` writer - NA"] +pub type HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT` reader - NA"] +pub type HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_R = crate::BitReader; +#[doc = "Field `HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT` writer - NA"] +pub type HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_enable_spi_manual_encrypt(&self) -> HP_REG_ENABLE_SPI_MANUAL_ENCRYPT_R { + HP_REG_ENABLE_SPI_MANUAL_ENCRYPT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn hp_reg_enable_download_db_encrypt(&self) -> HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_R { + HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn hp_reg_enable_download_g0cb_decrypt(&self) -> HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_R { + HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn hp_reg_enable_download_manual_encrypt(&self) -> HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_R { + HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CRYPTO_CTRL") + .field( + "hp_reg_enable_spi_manual_encrypt", + &format_args!("{}", self.hp_reg_enable_spi_manual_encrypt().bit()), + ) + .field( + "hp_reg_enable_download_db_encrypt", + &format_args!("{}", self.hp_reg_enable_download_db_encrypt().bit()), + ) + .field( + "hp_reg_enable_download_g0cb_decrypt", + &format_args!("{}", self.hp_reg_enable_download_g0cb_decrypt().bit()), + ) + .field( + "hp_reg_enable_download_manual_encrypt", + &format_args!("{}", self.hp_reg_enable_download_manual_encrypt().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_enable_spi_manual_encrypt( + &mut self, + ) -> HP_REG_ENABLE_SPI_MANUAL_ENCRYPT_W { + HP_REG_ENABLE_SPI_MANUAL_ENCRYPT_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_enable_download_db_encrypt( + &mut self, + ) -> HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_W { + HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_enable_download_g0cb_decrypt( + &mut self, + ) -> HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_W { + HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_enable_download_manual_encrypt( + &mut self, + ) -> HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_W { + HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_crypto_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_crypto_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CRYPTO_CTRL_SPEC; +impl crate::RegisterSpec for HP_CRYPTO_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_crypto_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_CRYPTO_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_crypto_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_CRYPTO_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CRYPTO_CTRL to value 0"] +impl crate::Resettable for HP_CRYPTO_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_design_for_verification0.rs b/esp32p4/src/hp_sys/hp_design_for_verification0.rs new file mode 100644 index 0000000000..9e9d1fb62e --- /dev/null +++ b/esp32p4/src/hp_sys/hp_design_for_verification0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `HP_DESIGN_FOR_VERIFICATION0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_DESIGN_FOR_VERIFICATION0` writer"] +pub type W = crate::W; +#[doc = "Field `HP_DFV0` reader - register for DV"] +pub type HP_DFV0_R = crate::FieldReader; +#[doc = "Field `HP_DFV0` writer - register for DV"] +pub type HP_DFV0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - register for DV"] + #[inline(always)] + pub fn hp_dfv0(&self) -> HP_DFV0_R { + HP_DFV0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_DESIGN_FOR_VERIFICATION0") + .field("hp_dfv0", &format_args!("{}", self.hp_dfv0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - register for DV"] + #[inline(always)] + #[must_use] + pub fn hp_dfv0(&mut self) -> HP_DFV0_W { + HP_DFV0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_design_for_verification0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_design_for_verification0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_DESIGN_FOR_VERIFICATION0_SPEC; +impl crate::RegisterSpec for HP_DESIGN_FOR_VERIFICATION0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_design_for_verification0::R`](R) reader structure"] +impl crate::Readable for HP_DESIGN_FOR_VERIFICATION0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_design_for_verification0::W`](W) writer structure"] +impl crate::Writable for HP_DESIGN_FOR_VERIFICATION0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_DESIGN_FOR_VERIFICATION0 to value 0"] +impl crate::Resettable for HP_DESIGN_FOR_VERIFICATION0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_design_for_verification1.rs b/esp32p4/src/hp_sys/hp_design_for_verification1.rs new file mode 100644 index 0000000000..4441327880 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_design_for_verification1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `HP_DESIGN_FOR_VERIFICATION1` reader"] +pub type R = crate::R; +#[doc = "Register `HP_DESIGN_FOR_VERIFICATION1` writer"] +pub type W = crate::W; +#[doc = "Field `HP_DFV1` reader - register for DV"] +pub type HP_DFV1_R = crate::FieldReader; +#[doc = "Field `HP_DFV1` writer - register for DV"] +pub type HP_DFV1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - register for DV"] + #[inline(always)] + pub fn hp_dfv1(&self) -> HP_DFV1_R { + HP_DFV1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_DESIGN_FOR_VERIFICATION1") + .field("hp_dfv1", &format_args!("{}", self.hp_dfv1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - register for DV"] + #[inline(always)] + #[must_use] + pub fn hp_dfv1(&mut self) -> HP_DFV1_W { + HP_DFV1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_design_for_verification1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_design_for_verification1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_DESIGN_FOR_VERIFICATION1_SPEC; +impl crate::RegisterSpec for HP_DESIGN_FOR_VERIFICATION1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_design_for_verification1::R`](R) reader structure"] +impl crate::Readable for HP_DESIGN_FOR_VERIFICATION1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_design_for_verification1::W`](W) writer structure"] +impl crate::Writable for HP_DESIGN_FOR_VERIFICATION1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_DESIGN_FOR_VERIFICATION1 to value 0"] +impl crate::Resettable for HP_DESIGN_FOR_VERIFICATION1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_ecc_pd_ctrl.rs b/esp32p4/src/hp_sys/hp_ecc_pd_ctrl.rs new file mode 100644 index 0000000000..faf835340d --- /dev/null +++ b/esp32p4/src/hp_sys/hp_ecc_pd_ctrl.rs @@ -0,0 +1,104 @@ +#[doc = "Register `HP_ECC_PD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ECC_PD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ECC_MEM_FORCE_PD` reader - Set this bit to power down ecc internal memory."] +pub type HP_ECC_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `HP_ECC_MEM_FORCE_PD` writer - Set this bit to power down ecc internal memory."] +pub type HP_ECC_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ECC_MEM_FORCE_PU` reader - Set this bit to force power up ecc internal memory"] +pub type HP_ECC_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `HP_ECC_MEM_FORCE_PU` writer - Set this bit to force power up ecc internal memory"] +pub type HP_ECC_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ECC_MEM_PD` reader - Set this bit to force power down ecc internal memory."] +pub type HP_ECC_MEM_PD_R = crate::BitReader; +#[doc = "Field `HP_ECC_MEM_PD` writer - Set this bit to force power down ecc internal memory."] +pub type HP_ECC_MEM_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to power down ecc internal memory."] + #[inline(always)] + pub fn hp_ecc_mem_force_pd(&self) -> HP_ECC_MEM_FORCE_PD_R { + HP_ECC_MEM_FORCE_PD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to force power up ecc internal memory"] + #[inline(always)] + pub fn hp_ecc_mem_force_pu(&self) -> HP_ECC_MEM_FORCE_PU_R { + HP_ECC_MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to force power down ecc internal memory."] + #[inline(always)] + pub fn hp_ecc_mem_pd(&self) -> HP_ECC_MEM_PD_R { + HP_ECC_MEM_PD_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ECC_PD_CTRL") + .field( + "hp_ecc_mem_force_pd", + &format_args!("{}", self.hp_ecc_mem_force_pd().bit()), + ) + .field( + "hp_ecc_mem_force_pu", + &format_args!("{}", self.hp_ecc_mem_force_pu().bit()), + ) + .field( + "hp_ecc_mem_pd", + &format_args!("{}", self.hp_ecc_mem_pd().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to power down ecc internal memory."] + #[inline(always)] + #[must_use] + pub fn hp_ecc_mem_force_pd(&mut self) -> HP_ECC_MEM_FORCE_PD_W { + HP_ECC_MEM_FORCE_PD_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to force power up ecc internal memory"] + #[inline(always)] + #[must_use] + pub fn hp_ecc_mem_force_pu(&mut self) -> HP_ECC_MEM_FORCE_PU_W { + HP_ECC_MEM_FORCE_PU_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to force power down ecc internal memory."] + #[inline(always)] + #[must_use] + pub fn hp_ecc_mem_pd(&mut self) -> HP_ECC_MEM_PD_W { + HP_ECC_MEM_PD_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ecc pd ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ecc_pd_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ecc_pd_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ECC_PD_CTRL_SPEC; +impl crate::RegisterSpec for HP_ECC_PD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_ecc_pd_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_ECC_PD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_ecc_pd_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_ECC_PD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ECC_PD_CTRL to value 0x02"] +impl crate::Resettable for HP_ECC_PD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/hp_sys/hp_gpio_ded_hold_ctrl.rs b/esp32p4/src/hp_sys/hp_gpio_ded_hold_ctrl.rs new file mode 100644 index 0000000000..94fd354df3 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_gpio_ded_hold_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_GPIO_DED_HOLD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_GPIO_DED_HOLD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_GPIO_DED_HOLD` reader - hold control for gpio63~56"] +pub type HP_REG_GPIO_DED_HOLD_R = crate::FieldReader; +#[doc = "Field `HP_REG_GPIO_DED_HOLD` writer - hold control for gpio63~56"] +pub type HP_REG_GPIO_DED_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>; +impl R { + #[doc = "Bits 0:25 - hold control for gpio63~56"] + #[inline(always)] + pub fn hp_reg_gpio_ded_hold(&self) -> HP_REG_GPIO_DED_HOLD_R { + HP_REG_GPIO_DED_HOLD_R::new(self.bits & 0x03ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_GPIO_DED_HOLD_CTRL") + .field( + "hp_reg_gpio_ded_hold", + &format_args!("{}", self.hp_reg_gpio_ded_hold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:25 - hold control for gpio63~56"] + #[inline(always)] + #[must_use] + pub fn hp_reg_gpio_ded_hold(&mut self) -> HP_REG_GPIO_DED_HOLD_W { + HP_REG_GPIO_DED_HOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_gpio_ded_hold_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_gpio_ded_hold_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_GPIO_DED_HOLD_CTRL_SPEC; +impl crate::RegisterSpec for HP_GPIO_DED_HOLD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_gpio_ded_hold_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_GPIO_DED_HOLD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_gpio_ded_hold_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_GPIO_DED_HOLD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_GPIO_DED_HOLD_CTRL to value 0"] +impl crate::Resettable for HP_GPIO_DED_HOLD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_gpio_o_hold_ctrl0.rs b/esp32p4/src/hp_sys/hp_gpio_o_hold_ctrl0.rs new file mode 100644 index 0000000000..8198d8d128 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_gpio_o_hold_ctrl0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_GPIO_O_HOLD_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_GPIO_O_HOLD_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_GPIO_0_HOLD_LOW` reader - hold control for gpio47~16"] +pub type HP_REG_GPIO_0_HOLD_LOW_R = crate::FieldReader; +#[doc = "Field `HP_REG_GPIO_0_HOLD_LOW` writer - hold control for gpio47~16"] +pub type HP_REG_GPIO_0_HOLD_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - hold control for gpio47~16"] + #[inline(always)] + pub fn hp_reg_gpio_0_hold_low(&self) -> HP_REG_GPIO_0_HOLD_LOW_R { + HP_REG_GPIO_0_HOLD_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_GPIO_O_HOLD_CTRL0") + .field( + "hp_reg_gpio_0_hold_low", + &format_args!("{}", self.hp_reg_gpio_0_hold_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - hold control for gpio47~16"] + #[inline(always)] + #[must_use] + pub fn hp_reg_gpio_0_hold_low( + &mut self, + ) -> HP_REG_GPIO_0_HOLD_LOW_W { + HP_REG_GPIO_0_HOLD_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_gpio_o_hold_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_gpio_o_hold_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_GPIO_O_HOLD_CTRL0_SPEC; +impl crate::RegisterSpec for HP_GPIO_O_HOLD_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_gpio_o_hold_ctrl0::R`](R) reader structure"] +impl crate::Readable for HP_GPIO_O_HOLD_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_gpio_o_hold_ctrl0::W`](W) writer structure"] +impl crate::Writable for HP_GPIO_O_HOLD_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_GPIO_O_HOLD_CTRL0 to value 0"] +impl crate::Resettable for HP_GPIO_O_HOLD_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_gpio_o_hold_ctrl1.rs b/esp32p4/src/hp_sys/hp_gpio_o_hold_ctrl1.rs new file mode 100644 index 0000000000..61c7b5695b --- /dev/null +++ b/esp32p4/src/hp_sys/hp_gpio_o_hold_ctrl1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_GPIO_O_HOLD_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `HP_GPIO_O_HOLD_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_GPIO_0_HOLD_HIGH` reader - hold control for gpio56~48"] +pub type HP_REG_GPIO_0_HOLD_HIGH_R = crate::FieldReader; +#[doc = "Field `HP_REG_GPIO_0_HOLD_HIGH` writer - hold control for gpio56~48"] +pub type HP_REG_GPIO_0_HOLD_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - hold control for gpio56~48"] + #[inline(always)] + pub fn hp_reg_gpio_0_hold_high(&self) -> HP_REG_GPIO_0_HOLD_HIGH_R { + HP_REG_GPIO_0_HOLD_HIGH_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_GPIO_O_HOLD_CTRL1") + .field( + "hp_reg_gpio_0_hold_high", + &format_args!("{}", self.hp_reg_gpio_0_hold_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - hold control for gpio56~48"] + #[inline(always)] + #[must_use] + pub fn hp_reg_gpio_0_hold_high( + &mut self, + ) -> HP_REG_GPIO_0_HOLD_HIGH_W { + HP_REG_GPIO_0_HOLD_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_gpio_o_hold_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_gpio_o_hold_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_GPIO_O_HOLD_CTRL1_SPEC; +impl crate::RegisterSpec for HP_GPIO_O_HOLD_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_gpio_o_hold_ctrl1::R`](R) reader structure"] +impl crate::Readable for HP_GPIO_O_HOLD_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_gpio_o_hold_ctrl1::W`](W) writer structure"] +impl crate::Writable for HP_GPIO_O_HOLD_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_GPIO_O_HOLD_CTRL1 to value 0"] +impl crate::Resettable for HP_GPIO_O_HOLD_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_gpio_o_hys_ctrl0.rs b/esp32p4/src/hp_sys/hp_gpio_o_hys_ctrl0.rs new file mode 100644 index 0000000000..628610f16d --- /dev/null +++ b/esp32p4/src/hp_sys/hp_gpio_o_hys_ctrl0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_GPIO_O_HYS_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_GPIO_O_HYS_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_GPIO_0_HYS_LOW` reader - hys control for gpio47~16"] +pub type HP_REG_GPIO_0_HYS_LOW_R = crate::FieldReader; +#[doc = "Field `HP_REG_GPIO_0_HYS_LOW` writer - hys control for gpio47~16"] +pub type HP_REG_GPIO_0_HYS_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - hys control for gpio47~16"] + #[inline(always)] + pub fn hp_reg_gpio_0_hys_low(&self) -> HP_REG_GPIO_0_HYS_LOW_R { + HP_REG_GPIO_0_HYS_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_GPIO_O_HYS_CTRL0") + .field( + "hp_reg_gpio_0_hys_low", + &format_args!("{}", self.hp_reg_gpio_0_hys_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - hys control for gpio47~16"] + #[inline(always)] + #[must_use] + pub fn hp_reg_gpio_0_hys_low(&mut self) -> HP_REG_GPIO_0_HYS_LOW_W { + HP_REG_GPIO_0_HYS_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_gpio_o_hys_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_gpio_o_hys_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_GPIO_O_HYS_CTRL0_SPEC; +impl crate::RegisterSpec for HP_GPIO_O_HYS_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_gpio_o_hys_ctrl0::R`](R) reader structure"] +impl crate::Readable for HP_GPIO_O_HYS_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_gpio_o_hys_ctrl0::W`](W) writer structure"] +impl crate::Writable for HP_GPIO_O_HYS_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_GPIO_O_HYS_CTRL0 to value 0"] +impl crate::Resettable for HP_GPIO_O_HYS_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_gpio_o_hys_ctrl1.rs b/esp32p4/src/hp_sys/hp_gpio_o_hys_ctrl1.rs new file mode 100644 index 0000000000..379c4b4c1b --- /dev/null +++ b/esp32p4/src/hp_sys/hp_gpio_o_hys_ctrl1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_GPIO_O_HYS_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `HP_GPIO_O_HYS_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_GPIO_0_HYS_HIGH` reader - hys control for gpio56~48"] +pub type HP_REG_GPIO_0_HYS_HIGH_R = crate::FieldReader; +#[doc = "Field `HP_REG_GPIO_0_HYS_HIGH` writer - hys control for gpio56~48"] +pub type HP_REG_GPIO_0_HYS_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - hys control for gpio56~48"] + #[inline(always)] + pub fn hp_reg_gpio_0_hys_high(&self) -> HP_REG_GPIO_0_HYS_HIGH_R { + HP_REG_GPIO_0_HYS_HIGH_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_GPIO_O_HYS_CTRL1") + .field( + "hp_reg_gpio_0_hys_high", + &format_args!("{}", self.hp_reg_gpio_0_hys_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - hys control for gpio56~48"] + #[inline(always)] + #[must_use] + pub fn hp_reg_gpio_0_hys_high(&mut self) -> HP_REG_GPIO_0_HYS_HIGH_W { + HP_REG_GPIO_0_HYS_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_gpio_o_hys_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_gpio_o_hys_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_GPIO_O_HYS_CTRL1_SPEC; +impl crate::RegisterSpec for HP_GPIO_O_HYS_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_gpio_o_hys_ctrl1::R`](R) reader structure"] +impl crate::Readable for HP_GPIO_O_HYS_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_gpio_o_hys_ctrl1::W`](W) writer structure"] +impl crate::Writable for HP_GPIO_O_HYS_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_GPIO_O_HYS_CTRL1 to value 0"] +impl crate::Resettable for HP_GPIO_O_HYS_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_icm_cpu_h2x_cfg.rs b/esp32p4/src/hp_sys/hp_icm_cpu_h2x_cfg.rs new file mode 100644 index 0000000000..f604a718c1 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_icm_cpu_h2x_cfg.rs @@ -0,0 +1,100 @@ +#[doc = "Register `HP_ICM_CPU_H2X_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ICM_CPU_H2X_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `HP_CPU_ICM_H2X_POST_WR_EN` reader - need_des"] +pub type HP_CPU_ICM_H2X_POST_WR_EN_R = crate::BitReader; +#[doc = "Field `HP_CPU_ICM_H2X_POST_WR_EN` writer - need_des"] +pub type HP_CPU_ICM_H2X_POST_WR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CPU_ICM_H2X_CUT_THROUGH_EN` reader - need_des"] +pub type HP_CPU_ICM_H2X_CUT_THROUGH_EN_R = crate::BitReader; +#[doc = "Field `HP_CPU_ICM_H2X_CUT_THROUGH_EN` writer - need_des"] +pub type HP_CPU_ICM_H2X_CUT_THROUGH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_CPU_ICM_H2X_BRIDGE_BUSY` reader - need_des"] +pub type HP_CPU_ICM_H2X_BRIDGE_BUSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn hp_cpu_icm_h2x_post_wr_en(&self) -> HP_CPU_ICM_H2X_POST_WR_EN_R { + HP_CPU_ICM_H2X_POST_WR_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn hp_cpu_icm_h2x_cut_through_en(&self) -> HP_CPU_ICM_H2X_CUT_THROUGH_EN_R { + HP_CPU_ICM_H2X_CUT_THROUGH_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + pub fn hp_cpu_icm_h2x_bridge_busy(&self) -> HP_CPU_ICM_H2X_BRIDGE_BUSY_R { + HP_CPU_ICM_H2X_BRIDGE_BUSY_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ICM_CPU_H2X_CFG") + .field( + "hp_cpu_icm_h2x_post_wr_en", + &format_args!("{}", self.hp_cpu_icm_h2x_post_wr_en().bit()), + ) + .field( + "hp_cpu_icm_h2x_cut_through_en", + &format_args!("{}", self.hp_cpu_icm_h2x_cut_through_en().bit()), + ) + .field( + "hp_cpu_icm_h2x_bridge_busy", + &format_args!("{}", self.hp_cpu_icm_h2x_bridge_busy().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_cpu_icm_h2x_post_wr_en( + &mut self, + ) -> HP_CPU_ICM_H2X_POST_WR_EN_W { + HP_CPU_ICM_H2X_POST_WR_EN_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_cpu_icm_h2x_cut_through_en( + &mut self, + ) -> HP_CPU_ICM_H2X_CUT_THROUGH_EN_W { + HP_CPU_ICM_H2X_CUT_THROUGH_EN_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_icm_cpu_h2x_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_icm_cpu_h2x_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ICM_CPU_H2X_CFG_SPEC; +impl crate::RegisterSpec for HP_ICM_CPU_H2X_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_icm_cpu_h2x_cfg::R`](R) reader structure"] +impl crate::Readable for HP_ICM_CPU_H2X_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_icm_cpu_h2x_cfg::W`](W) writer structure"] +impl crate::Writable for HP_ICM_CPU_H2X_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ICM_CPU_H2X_CFG to value 0x03"] +impl crate::Resettable for HP_ICM_CPU_H2X_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/hp_sys/hp_l1_cache_pwr_ctrl.rs b/esp32p4/src/hp_sys/hp_l1_cache_pwr_ctrl.rs new file mode 100644 index 0000000000..c7d40b1d44 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l1_cache_pwr_ctrl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L1_CACHE_PWR_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L1_CACHE_PWR_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L1_CACHE_MEM_FO` reader - need_des"] +pub type HP_REG_L1_CACHE_MEM_FO_R = crate::FieldReader; +#[doc = "Field `HP_REG_L1_CACHE_MEM_FO` writer - need_des"] +pub type HP_REG_L1_CACHE_MEM_FO_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - need_des"] + #[inline(always)] + pub fn hp_reg_l1_cache_mem_fo(&self) -> HP_REG_L1_CACHE_MEM_FO_R { + HP_REG_L1_CACHE_MEM_FO_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L1_CACHE_PWR_CTRL") + .field( + "hp_reg_l1_cache_mem_fo", + &format_args!("{}", self.hp_reg_l1_cache_mem_fo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l1_cache_mem_fo( + &mut self, + ) -> HP_REG_L1_CACHE_MEM_FO_W { + HP_REG_L1_CACHE_MEM_FO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l1_cache_pwr_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l1_cache_pwr_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L1_CACHE_PWR_CTRL_SPEC; +impl crate::RegisterSpec for HP_L1_CACHE_PWR_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l1_cache_pwr_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_L1_CACHE_PWR_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l1_cache_pwr_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_L1_CACHE_PWR_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L1_CACHE_PWR_CTRL to value 0"] +impl crate::Resettable for HP_L1_CACHE_PWR_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l1cache_bus0_id.rs b/esp32p4/src/hp_sys/hp_l1cache_bus0_id.rs new file mode 100644 index 0000000000..06de3aff14 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l1cache_bus0_id.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L1CACHE_BUS0_ID` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L1CACHE_BUS0_ID` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L1_CACHE_BUS0_ID` reader - NA"] +pub type HP_REG_L1_CACHE_BUS0_ID_R = crate::FieldReader; +#[doc = "Field `HP_REG_L1_CACHE_BUS0_ID` writer - NA"] +pub type HP_REG_L1_CACHE_BUS0_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + pub fn hp_reg_l1_cache_bus0_id(&self) -> HP_REG_L1_CACHE_BUS0_ID_R { + HP_REG_L1_CACHE_BUS0_ID_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L1CACHE_BUS0_ID") + .field( + "hp_reg_l1_cache_bus0_id", + &format_args!("{}", self.hp_reg_l1_cache_bus0_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l1_cache_bus0_id( + &mut self, + ) -> HP_REG_L1_CACHE_BUS0_ID_W { + HP_REG_L1_CACHE_BUS0_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l1cache_bus0_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l1cache_bus0_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L1CACHE_BUS0_ID_SPEC; +impl crate::RegisterSpec for HP_L1CACHE_BUS0_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l1cache_bus0_id::R`](R) reader structure"] +impl crate::Readable for HP_L1CACHE_BUS0_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l1cache_bus0_id::W`](W) writer structure"] +impl crate::Writable for HP_L1CACHE_BUS0_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L1CACHE_BUS0_ID to value 0"] +impl crate::Resettable for HP_L1CACHE_BUS0_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l1cache_bus1_id.rs b/esp32p4/src/hp_sys/hp_l1cache_bus1_id.rs new file mode 100644 index 0000000000..ce5ea9b001 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l1cache_bus1_id.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L1CACHE_BUS1_ID` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L1CACHE_BUS1_ID` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L1_CACHE_BUS1_ID` reader - NA"] +pub type HP_REG_L1_CACHE_BUS1_ID_R = crate::FieldReader; +#[doc = "Field `HP_REG_L1_CACHE_BUS1_ID` writer - NA"] +pub type HP_REG_L1_CACHE_BUS1_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + pub fn hp_reg_l1_cache_bus1_id(&self) -> HP_REG_L1_CACHE_BUS1_ID_R { + HP_REG_L1_CACHE_BUS1_ID_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L1CACHE_BUS1_ID") + .field( + "hp_reg_l1_cache_bus1_id", + &format_args!("{}", self.hp_reg_l1_cache_bus1_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l1_cache_bus1_id( + &mut self, + ) -> HP_REG_L1_CACHE_BUS1_ID_W { + HP_REG_L1_CACHE_BUS1_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l1cache_bus1_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l1cache_bus1_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L1CACHE_BUS1_ID_SPEC; +impl crate::RegisterSpec for HP_L1CACHE_BUS1_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l1cache_bus1_id::R`](R) reader structure"] +impl crate::Readable for HP_L1CACHE_BUS1_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l1cache_bus1_id::W`](W) writer structure"] +impl crate::Writable for HP_L1CACHE_BUS1_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L1CACHE_BUS1_ID to value 0"] +impl crate::Resettable for HP_L1CACHE_BUS1_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_cache_pwr_ctrl.rs b/esp32p4/src/hp_sys/hp_l2_cache_pwr_ctrl.rs new file mode 100644 index 0000000000..1776b5a67f --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_cache_pwr_ctrl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L2_CACHE_PWR_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_CACHE_PWR_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_CACHE_MEM_FO` reader - need_des"] +pub type HP_REG_L2_CACHE_MEM_FO_R = crate::FieldReader; +#[doc = "Field `HP_REG_L2_CACHE_MEM_FO` writer - need_des"] +pub type HP_REG_L2_CACHE_MEM_FO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - need_des"] + #[inline(always)] + pub fn hp_reg_l2_cache_mem_fo(&self) -> HP_REG_L2_CACHE_MEM_FO_R { + HP_REG_L2_CACHE_MEM_FO_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_CACHE_PWR_CTRL") + .field( + "hp_reg_l2_cache_mem_fo", + &format_args!("{}", self.hp_reg_l2_cache_mem_fo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_cache_mem_fo( + &mut self, + ) -> HP_REG_L2_CACHE_MEM_FO_W { + HP_REG_L2_CACHE_MEM_FO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_cache_pwr_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_cache_pwr_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_CACHE_PWR_CTRL_SPEC; +impl crate::RegisterSpec for HP_L2_CACHE_PWR_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_cache_pwr_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_L2_CACHE_PWR_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_cache_pwr_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_L2_CACHE_PWR_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_CACHE_PWR_CTRL to value 0"] +impl crate::Resettable for HP_L2_CACHE_PWR_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_ahb_buffer_ctrl.rs b/esp32p4/src/hp_sys/hp_l2_mem_ahb_buffer_ctrl.rs new file mode 100644 index 0000000000..460c1ad256 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_ahb_buffer_ctrl.rs @@ -0,0 +1,89 @@ +#[doc = "Register `HP_L2_MEM_AHB_BUFFER_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_AHB_BUFFER_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_L2_MEM_AHB_WRBUFFER_EN` reader - Set 1 to turn on l2mem ahb wr buffer"] +pub type HP_L2_MEM_AHB_WRBUFFER_EN_R = crate::BitReader; +#[doc = "Field `HP_L2_MEM_AHB_WRBUFFER_EN` writer - Set 1 to turn on l2mem ahb wr buffer"] +pub type HP_L2_MEM_AHB_WRBUFFER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_L2_MEM_AHB_RDBUFFER_EN` reader - Set 1 to turn on l2mem ahb rd buffer"] +pub type HP_L2_MEM_AHB_RDBUFFER_EN_R = crate::BitReader; +#[doc = "Field `HP_L2_MEM_AHB_RDBUFFER_EN` writer - Set 1 to turn on l2mem ahb rd buffer"] +pub type HP_L2_MEM_AHB_RDBUFFER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 to turn on l2mem ahb wr buffer"] + #[inline(always)] + pub fn hp_l2_mem_ahb_wrbuffer_en(&self) -> HP_L2_MEM_AHB_WRBUFFER_EN_R { + HP_L2_MEM_AHB_WRBUFFER_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set 1 to turn on l2mem ahb rd buffer"] + #[inline(always)] + pub fn hp_l2_mem_ahb_rdbuffer_en(&self) -> HP_L2_MEM_AHB_RDBUFFER_EN_R { + HP_L2_MEM_AHB_RDBUFFER_EN_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_AHB_BUFFER_CTRL") + .field( + "hp_l2_mem_ahb_wrbuffer_en", + &format_args!("{}", self.hp_l2_mem_ahb_wrbuffer_en().bit()), + ) + .field( + "hp_l2_mem_ahb_rdbuffer_en", + &format_args!("{}", self.hp_l2_mem_ahb_rdbuffer_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 to turn on l2mem ahb wr buffer"] + #[inline(always)] + #[must_use] + pub fn hp_l2_mem_ahb_wrbuffer_en( + &mut self, + ) -> HP_L2_MEM_AHB_WRBUFFER_EN_W { + HP_L2_MEM_AHB_WRBUFFER_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set 1 to turn on l2mem ahb rd buffer"] + #[inline(always)] + #[must_use] + pub fn hp_l2_mem_ahb_rdbuffer_en( + &mut self, + ) -> HP_L2_MEM_AHB_RDBUFFER_EN_W { + HP_L2_MEM_AHB_RDBUFFER_EN_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_ahb_buffer_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_ahb_buffer_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_AHB_BUFFER_CTRL_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_AHB_BUFFER_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_ahb_buffer_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_AHB_BUFFER_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_ahb_buffer_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_AHB_BUFFER_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_AHB_BUFFER_CTRL to value 0"] +impl crate::Resettable for HP_L2_MEM_AHB_BUFFER_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_err_resp_ctrl.rs b/esp32p4/src/hp_sys/hp_l2_mem_err_resp_ctrl.rs new file mode 100644 index 0000000000..35788b69d5 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_err_resp_ctrl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L2_MEM_ERR_RESP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_ERR_RESP_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_L2_MEM_ERR_RESP_EN` reader - Set 1 to turn on l2mem error response"] +pub type HP_L2_MEM_ERR_RESP_EN_R = crate::BitReader; +#[doc = "Field `HP_L2_MEM_ERR_RESP_EN` writer - Set 1 to turn on l2mem error response"] +pub type HP_L2_MEM_ERR_RESP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 to turn on l2mem error response"] + #[inline(always)] + pub fn hp_l2_mem_err_resp_en(&self) -> HP_L2_MEM_ERR_RESP_EN_R { + HP_L2_MEM_ERR_RESP_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_ERR_RESP_CTRL") + .field( + "hp_l2_mem_err_resp_en", + &format_args!("{}", self.hp_l2_mem_err_resp_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 to turn on l2mem error response"] + #[inline(always)] + #[must_use] + pub fn hp_l2_mem_err_resp_en( + &mut self, + ) -> HP_L2_MEM_ERR_RESP_EN_W { + HP_L2_MEM_ERR_RESP_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_err_resp_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_err_resp_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_ERR_RESP_CTRL_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_ERR_RESP_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_err_resp_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_ERR_RESP_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_err_resp_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_ERR_RESP_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_ERR_RESP_CTRL to value 0"] +impl crate::Resettable for HP_L2_MEM_ERR_RESP_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_int_clr.rs b/esp32p4/src/hp_sys/hp_l2_mem_int_clr.rs new file mode 100644 index 0000000000..2d10d2ab5c --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_int_clr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `HP_L2_MEM_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_MEM_ECC_ERR_INT_CLR` writer - NA"] +pub type HP_REG_L2_MEM_ECC_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR` writer - NA"] +pub type HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_ERR_RESP_INT_CLR` writer - NA"] +pub type HP_REG_L2_MEM_ERR_RESP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_ecc_err_int_clr( + &mut self, + ) -> HP_REG_L2_MEM_ECC_ERR_INT_CLR_W { + HP_REG_L2_MEM_ECC_ERR_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_exceed_addr_int_clr( + &mut self, + ) -> HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR_W { + HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_err_resp_int_clr( + &mut self, + ) -> HP_REG_L2_MEM_ERR_RESP_INT_CLR_W { + HP_REG_L2_MEM_ERR_RESP_INT_CLR_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_INT_CLR_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_int_clr::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_INT_CLR to value 0"] +impl crate::Resettable for HP_L2_MEM_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_int_ena.rs b/esp32p4/src/hp_sys/hp_l2_mem_int_ena.rs new file mode 100644 index 0000000000..7e9a7e0d80 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_int_ena.rs @@ -0,0 +1,110 @@ +#[doc = "Register `HP_L2_MEM_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_MEM_ECC_ERR_INT_ENA` reader - NA"] +pub type HP_REG_L2_MEM_ECC_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_ECC_ERR_INT_ENA` writer - NA"] +pub type HP_REG_L2_MEM_ECC_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA` reader - NA"] +pub type HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA` writer - NA"] +pub type HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_ERR_RESP_INT_ENA` reader - NA"] +pub type HP_REG_L2_MEM_ERR_RESP_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_ERR_RESP_INT_ENA` writer - NA"] +pub type HP_REG_L2_MEM_ERR_RESP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_ecc_err_int_ena(&self) -> HP_REG_L2_MEM_ECC_ERR_INT_ENA_R { + HP_REG_L2_MEM_ECC_ERR_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_exceed_addr_int_ena(&self) -> HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA_R { + HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_err_resp_int_ena(&self) -> HP_REG_L2_MEM_ERR_RESP_INT_ENA_R { + HP_REG_L2_MEM_ERR_RESP_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_INT_ENA") + .field( + "hp_reg_l2_mem_ecc_err_int_ena", + &format_args!("{}", self.hp_reg_l2_mem_ecc_err_int_ena().bit()), + ) + .field( + "hp_reg_l2_mem_exceed_addr_int_ena", + &format_args!("{}", self.hp_reg_l2_mem_exceed_addr_int_ena().bit()), + ) + .field( + "hp_reg_l2_mem_err_resp_int_ena", + &format_args!("{}", self.hp_reg_l2_mem_err_resp_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_ecc_err_int_ena( + &mut self, + ) -> HP_REG_L2_MEM_ECC_ERR_INT_ENA_W { + HP_REG_L2_MEM_ECC_ERR_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_exceed_addr_int_ena( + &mut self, + ) -> HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA_W { + HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_err_resp_int_ena( + &mut self, + ) -> HP_REG_L2_MEM_ERR_RESP_INT_ENA_W { + HP_REG_L2_MEM_ERR_RESP_INT_ENA_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_INT_ENA_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_int_ena::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_int_ena::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_INT_ENA to value 0"] +impl crate::Resettable for HP_L2_MEM_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_int_raw.rs b/esp32p4/src/hp_sys/hp_l2_mem_int_raw.rs new file mode 100644 index 0000000000..f0d3751061 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_int_raw.rs @@ -0,0 +1,110 @@ +#[doc = "Register `HP_L2_MEM_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_MEM_ECC_ERR_INT_RAW` reader - intr triggered when two bit error detected and corrected from ecc"] +pub type HP_REG_L2_MEM_ECC_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_ECC_ERR_INT_RAW` writer - intr triggered when two bit error detected and corrected from ecc"] +pub type HP_REG_L2_MEM_ECC_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW` reader - intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode"] +pub type HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW` writer - intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode"] +pub type HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_ERR_RESP_INT_RAW` reader - intr triggered when err response occurs"] +pub type HP_REG_L2_MEM_ERR_RESP_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_ERR_RESP_INT_RAW` writer - intr triggered when err response occurs"] +pub type HP_REG_L2_MEM_ERR_RESP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - intr triggered when two bit error detected and corrected from ecc"] + #[inline(always)] + pub fn hp_reg_l2_mem_ecc_err_int_raw(&self) -> HP_REG_L2_MEM_ECC_ERR_INT_RAW_R { + HP_REG_L2_MEM_ECC_ERR_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode"] + #[inline(always)] + pub fn hp_reg_l2_mem_exceed_addr_int_raw(&self) -> HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW_R { + HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - intr triggered when err response occurs"] + #[inline(always)] + pub fn hp_reg_l2_mem_err_resp_int_raw(&self) -> HP_REG_L2_MEM_ERR_RESP_INT_RAW_R { + HP_REG_L2_MEM_ERR_RESP_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_INT_RAW") + .field( + "hp_reg_l2_mem_ecc_err_int_raw", + &format_args!("{}", self.hp_reg_l2_mem_ecc_err_int_raw().bit()), + ) + .field( + "hp_reg_l2_mem_exceed_addr_int_raw", + &format_args!("{}", self.hp_reg_l2_mem_exceed_addr_int_raw().bit()), + ) + .field( + "hp_reg_l2_mem_err_resp_int_raw", + &format_args!("{}", self.hp_reg_l2_mem_err_resp_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - intr triggered when two bit error detected and corrected from ecc"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_ecc_err_int_raw( + &mut self, + ) -> HP_REG_L2_MEM_ECC_ERR_INT_RAW_W { + HP_REG_L2_MEM_ECC_ERR_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_exceed_addr_int_raw( + &mut self, + ) -> HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW_W { + HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - intr triggered when err response occurs"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_err_resp_int_raw( + &mut self, + ) -> HP_REG_L2_MEM_ERR_RESP_INT_RAW_W { + HP_REG_L2_MEM_ERR_RESP_INT_RAW_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_INT_RAW_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_int_raw::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_int_raw::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_INT_RAW to value 0"] +impl crate::Resettable for HP_L2_MEM_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_int_record0.rs b/esp32p4/src/hp_sys/hp_l2_mem_int_record0.rs new file mode 100644 index 0000000000..ada12e3a19 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_int_record0.rs @@ -0,0 +1,61 @@ +#[doc = "Register `HP_L2_MEM_INT_RECORD0` reader"] +pub type R = crate::R; +#[doc = "Field `HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR` reader - NA"] +pub type HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_R = crate::FieldReader; +#[doc = "Field `HP_REG_L2_MEM_EXCEED_ADDR_INT_WE` reader - NA"] +pub type HP_REG_L2_MEM_EXCEED_ADDR_INT_WE_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER` reader - NA"] +pub type HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:20 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_exceed_addr_int_addr(&self) -> HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_R { + HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_R::new(self.bits & 0x001f_ffff) + } + #[doc = "Bit 21 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_exceed_addr_int_we(&self) -> HP_REG_L2_MEM_EXCEED_ADDR_INT_WE_R { + HP_REG_L2_MEM_EXCEED_ADDR_INT_WE_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 22:24 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_exceed_addr_int_master(&self) -> HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_R { + HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_R::new(((self.bits >> 22) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_INT_RECORD0") + .field( + "hp_reg_l2_mem_exceed_addr_int_addr", + &format_args!("{}", self.hp_reg_l2_mem_exceed_addr_int_addr().bits()), + ) + .field( + "hp_reg_l2_mem_exceed_addr_int_we", + &format_args!("{}", self.hp_reg_l2_mem_exceed_addr_int_we().bit()), + ) + .field( + "hp_reg_l2_mem_exceed_addr_int_master", + &format_args!("{}", self.hp_reg_l2_mem_exceed_addr_int_master().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_int_record0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_INT_RECORD0_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_INT_RECORD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_int_record0::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_INT_RECORD0_SPEC {} +#[doc = "`reset()` method sets HP_L2_MEM_INT_RECORD0 to value 0"] +impl crate::Resettable for HP_L2_MEM_INT_RECORD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_int_record1.rs b/esp32p4/src/hp_sys/hp_l2_mem_int_record1.rs new file mode 100644 index 0000000000..23ec9644ed --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_int_record1.rs @@ -0,0 +1,83 @@ +#[doc = "Register `HP_L2_MEM_INT_RECORD1` reader"] +pub type R = crate::R; +#[doc = "Field `HP_REG_L2_MEM_ECC_ERR_INT_ADDR` reader - NA"] +pub type HP_REG_L2_MEM_ECC_ERR_INT_ADDR_R = crate::FieldReader; +#[doc = "Field `HP_REG_L2_MEM_ECC_ONE_BIT_ERR` reader - NA"] +pub type HP_REG_L2_MEM_ECC_ONE_BIT_ERR_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_ECC_TWO_BIT_ERR` reader - NA"] +pub type HP_REG_L2_MEM_ECC_TWO_BIT_ERR_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_ECC_ERR_BIT` reader - NA"] +pub type HP_REG_L2_MEM_ECC_ERR_BIT_R = crate::FieldReader; +#[doc = "Field `HP_REG_L2_CACHE_ERR_BANK` reader - NA"] +pub type HP_REG_L2_CACHE_ERR_BANK_R = crate::BitReader; +impl R { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_ecc_err_int_addr(&self) -> HP_REG_L2_MEM_ECC_ERR_INT_ADDR_R { + HP_REG_L2_MEM_ECC_ERR_INT_ADDR_R::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_ecc_one_bit_err(&self) -> HP_REG_L2_MEM_ECC_ONE_BIT_ERR_R { + HP_REG_L2_MEM_ECC_ONE_BIT_ERR_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_ecc_two_bit_err(&self) -> HP_REG_L2_MEM_ECC_TWO_BIT_ERR_R { + HP_REG_L2_MEM_ECC_TWO_BIT_ERR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:25 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_ecc_err_bit(&self) -> HP_REG_L2_MEM_ECC_ERR_BIT_R { + HP_REG_L2_MEM_ECC_ERR_BIT_R::new(((self.bits >> 17) & 0x01ff) as u16) + } + #[doc = "Bit 26 - NA"] + #[inline(always)] + pub fn hp_reg_l2_cache_err_bank(&self) -> HP_REG_L2_CACHE_ERR_BANK_R { + HP_REG_L2_CACHE_ERR_BANK_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_INT_RECORD1") + .field( + "hp_reg_l2_mem_ecc_err_int_addr", + &format_args!("{}", self.hp_reg_l2_mem_ecc_err_int_addr().bits()), + ) + .field( + "hp_reg_l2_mem_ecc_one_bit_err", + &format_args!("{}", self.hp_reg_l2_mem_ecc_one_bit_err().bit()), + ) + .field( + "hp_reg_l2_mem_ecc_two_bit_err", + &format_args!("{}", self.hp_reg_l2_mem_ecc_two_bit_err().bit()), + ) + .field( + "hp_reg_l2_mem_ecc_err_bit", + &format_args!("{}", self.hp_reg_l2_mem_ecc_err_bit().bits()), + ) + .field( + "hp_reg_l2_cache_err_bank", + &format_args!("{}", self.hp_reg_l2_cache_err_bank().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_int_record1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_INT_RECORD1_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_INT_RECORD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_int_record1::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_INT_RECORD1_SPEC {} +#[doc = "`reset()` method sets HP_L2_MEM_INT_RECORD1 to value 0"] +impl crate::Resettable for HP_L2_MEM_INT_RECORD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_int_st.rs b/esp32p4/src/hp_sys/hp_l2_mem_int_st.rs new file mode 100644 index 0000000000..cfafca63ce --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_int_st.rs @@ -0,0 +1,61 @@ +#[doc = "Register `HP_L2_MEM_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `HP_REG_L2_MEM_ECC_ERR_INT_ST` reader - NA"] +pub type HP_REG_L2_MEM_ECC_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_EXCEED_ADDR_INT_ST` reader - NA"] +pub type HP_REG_L2_MEM_EXCEED_ADDR_INT_ST_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_ERR_RESP_INT_ST` reader - NA"] +pub type HP_REG_L2_MEM_ERR_RESP_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_ecc_err_int_st(&self) -> HP_REG_L2_MEM_ECC_ERR_INT_ST_R { + HP_REG_L2_MEM_ECC_ERR_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_exceed_addr_int_st(&self) -> HP_REG_L2_MEM_EXCEED_ADDR_INT_ST_R { + HP_REG_L2_MEM_EXCEED_ADDR_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_err_resp_int_st(&self) -> HP_REG_L2_MEM_ERR_RESP_INT_ST_R { + HP_REG_L2_MEM_ERR_RESP_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_INT_ST") + .field( + "hp_reg_l2_mem_ecc_err_int_st", + &format_args!("{}", self.hp_reg_l2_mem_ecc_err_int_st().bit()), + ) + .field( + "hp_reg_l2_mem_exceed_addr_int_st", + &format_args!("{}", self.hp_reg_l2_mem_exceed_addr_int_st().bit()), + ) + .field( + "hp_reg_l2_mem_err_resp_int_st", + &format_args!("{}", self.hp_reg_l2_mem_err_resp_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_INT_ST_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_int_st::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_INT_ST_SPEC {} +#[doc = "`reset()` method sets HP_L2_MEM_INT_ST to value 0"] +impl crate::Resettable for HP_L2_MEM_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_l2_cache_ecc.rs b/esp32p4/src/hp_sys/hp_l2_mem_l2_cache_ecc.rs new file mode 100644 index 0000000000..01efee5722 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_l2_cache_ecc.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L2_MEM_L2_CACHE_ECC` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_L2_CACHE_ECC` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_CACHE_ECC_EN` reader - NA"] +pub type HP_REG_L2_CACHE_ECC_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_CACHE_ECC_EN` writer - NA"] +pub type HP_REG_L2_CACHE_ECC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_l2_cache_ecc_en(&self) -> HP_REG_L2_CACHE_ECC_EN_R { + HP_REG_L2_CACHE_ECC_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_L2_CACHE_ECC") + .field( + "hp_reg_l2_cache_ecc_en", + &format_args!("{}", self.hp_reg_l2_cache_ecc_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_cache_ecc_en( + &mut self, + ) -> HP_REG_L2_CACHE_ECC_EN_W { + HP_REG_L2_CACHE_ECC_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_l2_cache_ecc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_l2_cache_ecc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_L2_CACHE_ECC_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_L2_CACHE_ECC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_l2_cache_ecc::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_L2_CACHE_ECC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_l2_cache_ecc::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_L2_CACHE_ECC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_L2_CACHE_ECC to value 0"] +impl crate::Resettable for HP_L2_MEM_L2_CACHE_ECC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_l2_ram_ecc.rs b/esp32p4/src/hp_sys/hp_l2_mem_l2_ram_ecc.rs new file mode 100644 index 0000000000..d4f7345261 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_l2_ram_ecc.rs @@ -0,0 +1,173 @@ +#[doc = "Register `HP_L2_MEM_L2_RAM_ECC` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_L2_RAM_ECC` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_RAM_UNIT0_ECC_EN` reader - NA"] +pub type HP_REG_L2_RAM_UNIT0_ECC_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_RAM_UNIT0_ECC_EN` writer - NA"] +pub type HP_REG_L2_RAM_UNIT0_ECC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_RAM_UNIT1_ECC_EN` reader - NA"] +pub type HP_REG_L2_RAM_UNIT1_ECC_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_RAM_UNIT1_ECC_EN` writer - NA"] +pub type HP_REG_L2_RAM_UNIT1_ECC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_RAM_UNIT2_ECC_EN` reader - NA"] +pub type HP_REG_L2_RAM_UNIT2_ECC_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_RAM_UNIT2_ECC_EN` writer - NA"] +pub type HP_REG_L2_RAM_UNIT2_ECC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_RAM_UNIT3_ECC_EN` reader - NA"] +pub type HP_REG_L2_RAM_UNIT3_ECC_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_RAM_UNIT3_ECC_EN` writer - NA"] +pub type HP_REG_L2_RAM_UNIT3_ECC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_RAM_UNIT4_ECC_EN` reader - NA"] +pub type HP_REG_L2_RAM_UNIT4_ECC_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_RAM_UNIT4_ECC_EN` writer - NA"] +pub type HP_REG_L2_RAM_UNIT4_ECC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_RAM_UNIT5_ECC_EN` reader - NA"] +pub type HP_REG_L2_RAM_UNIT5_ECC_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_RAM_UNIT5_ECC_EN` writer - NA"] +pub type HP_REG_L2_RAM_UNIT5_ECC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_l2_ram_unit0_ecc_en(&self) -> HP_REG_L2_RAM_UNIT0_ECC_EN_R { + HP_REG_L2_RAM_UNIT0_ECC_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn hp_reg_l2_ram_unit1_ecc_en(&self) -> HP_REG_L2_RAM_UNIT1_ECC_EN_R { + HP_REG_L2_RAM_UNIT1_ECC_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn hp_reg_l2_ram_unit2_ecc_en(&self) -> HP_REG_L2_RAM_UNIT2_ECC_EN_R { + HP_REG_L2_RAM_UNIT2_ECC_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn hp_reg_l2_ram_unit3_ecc_en(&self) -> HP_REG_L2_RAM_UNIT3_ECC_EN_R { + HP_REG_L2_RAM_UNIT3_ECC_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn hp_reg_l2_ram_unit4_ecc_en(&self) -> HP_REG_L2_RAM_UNIT4_ECC_EN_R { + HP_REG_L2_RAM_UNIT4_ECC_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn hp_reg_l2_ram_unit5_ecc_en(&self) -> HP_REG_L2_RAM_UNIT5_ECC_EN_R { + HP_REG_L2_RAM_UNIT5_ECC_EN_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_L2_RAM_ECC") + .field( + "hp_reg_l2_ram_unit0_ecc_en", + &format_args!("{}", self.hp_reg_l2_ram_unit0_ecc_en().bit()), + ) + .field( + "hp_reg_l2_ram_unit1_ecc_en", + &format_args!("{}", self.hp_reg_l2_ram_unit1_ecc_en().bit()), + ) + .field( + "hp_reg_l2_ram_unit2_ecc_en", + &format_args!("{}", self.hp_reg_l2_ram_unit2_ecc_en().bit()), + ) + .field( + "hp_reg_l2_ram_unit3_ecc_en", + &format_args!("{}", self.hp_reg_l2_ram_unit3_ecc_en().bit()), + ) + .field( + "hp_reg_l2_ram_unit4_ecc_en", + &format_args!("{}", self.hp_reg_l2_ram_unit4_ecc_en().bit()), + ) + .field( + "hp_reg_l2_ram_unit5_ecc_en", + &format_args!("{}", self.hp_reg_l2_ram_unit5_ecc_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_ram_unit0_ecc_en( + &mut self, + ) -> HP_REG_L2_RAM_UNIT0_ECC_EN_W { + HP_REG_L2_RAM_UNIT0_ECC_EN_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_ram_unit1_ecc_en( + &mut self, + ) -> HP_REG_L2_RAM_UNIT1_ECC_EN_W { + HP_REG_L2_RAM_UNIT1_ECC_EN_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_ram_unit2_ecc_en( + &mut self, + ) -> HP_REG_L2_RAM_UNIT2_ECC_EN_W { + HP_REG_L2_RAM_UNIT2_ECC_EN_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_ram_unit3_ecc_en( + &mut self, + ) -> HP_REG_L2_RAM_UNIT3_ECC_EN_W { + HP_REG_L2_RAM_UNIT3_ECC_EN_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_ram_unit4_ecc_en( + &mut self, + ) -> HP_REG_L2_RAM_UNIT4_ECC_EN_W { + HP_REG_L2_RAM_UNIT4_ECC_EN_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_ram_unit5_ecc_en( + &mut self, + ) -> HP_REG_L2_RAM_UNIT5_ECC_EN_W { + HP_REG_L2_RAM_UNIT5_ECC_EN_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_l2_ram_ecc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_l2_ram_ecc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_L2_RAM_ECC_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_L2_RAM_ECC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_l2_ram_ecc::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_L2_RAM_ECC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_l2_ram_ecc::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_L2_RAM_ECC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_L2_RAM_ECC to value 0"] +impl crate::Resettable for HP_L2_MEM_L2_RAM_ECC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_ram_pwr_ctrl0.rs b/esp32p4/src/hp_sys/hp_l2_mem_ram_pwr_ctrl0.rs new file mode 100644 index 0000000000..19d84a89fc --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_ram_pwr_ctrl0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L2_MEM_RAM_PWR_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_RAM_PWR_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_MEM_CLK_FORCE_ON` reader - l2ram clk_gating force on"] +pub type HP_REG_L2_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_CLK_FORCE_ON` writer - l2ram clk_gating force on"] +pub type HP_REG_L2_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - l2ram clk_gating force on"] + #[inline(always)] + pub fn hp_reg_l2_mem_clk_force_on(&self) -> HP_REG_L2_MEM_CLK_FORCE_ON_R { + HP_REG_L2_MEM_CLK_FORCE_ON_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_RAM_PWR_CTRL0") + .field( + "hp_reg_l2_mem_clk_force_on", + &format_args!("{}", self.hp_reg_l2_mem_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - l2ram clk_gating force on"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_clk_force_on( + &mut self, + ) -> HP_REG_L2_MEM_CLK_FORCE_ON_W { + HP_REG_L2_MEM_CLK_FORCE_ON_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_ram_pwr_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_ram_pwr_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_RAM_PWR_CTRL0_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_RAM_PWR_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_ram_pwr_ctrl0::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_RAM_PWR_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_ram_pwr_ctrl0::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_RAM_PWR_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_RAM_PWR_CTRL0 to value 0"] +impl crate::Resettable for HP_L2_MEM_RAM_PWR_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_rdn_eco_cs.rs b/esp32p4/src/hp_sys/hp_l2_mem_rdn_eco_cs.rs new file mode 100644 index 0000000000..b9e0cefb71 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_rdn_eco_cs.rs @@ -0,0 +1,79 @@ +#[doc = "Register `HP_L2_MEM_RDN_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_RDN_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_MEM_RDN_ECO_EN` reader - NA"] +pub type HP_REG_L2_MEM_RDN_ECO_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_RDN_ECO_EN` writer - NA"] +pub type HP_REG_L2_MEM_RDN_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_RDN_ECO_RESULT` reader - NA"] +pub type HP_REG_L2_MEM_RDN_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_rdn_eco_en(&self) -> HP_REG_L2_MEM_RDN_ECO_EN_R { + HP_REG_L2_MEM_RDN_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_rdn_eco_result(&self) -> HP_REG_L2_MEM_RDN_ECO_RESULT_R { + HP_REG_L2_MEM_RDN_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_RDN_ECO_CS") + .field( + "hp_reg_l2_mem_rdn_eco_en", + &format_args!("{}", self.hp_reg_l2_mem_rdn_eco_en().bit()), + ) + .field( + "hp_reg_l2_mem_rdn_eco_result", + &format_args!("{}", self.hp_reg_l2_mem_rdn_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_rdn_eco_en( + &mut self, + ) -> HP_REG_L2_MEM_RDN_ECO_EN_W { + HP_REG_L2_MEM_RDN_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_rdn_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_rdn_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_RDN_ECO_CS_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_RDN_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_rdn_eco_cs::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_RDN_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_rdn_eco_cs::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_RDN_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_RDN_ECO_CS to value 0"] +impl crate::Resettable for HP_L2_MEM_RDN_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_rdn_eco_high.rs b/esp32p4/src/hp_sys/hp_l2_mem_rdn_eco_high.rs new file mode 100644 index 0000000000..b58f54662a --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_rdn_eco_high.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L2_MEM_RDN_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_RDN_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_MEM_RDN_ECO_HIGH` reader - NA"] +pub type HP_REG_L2_MEM_RDN_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `HP_REG_L2_MEM_RDN_ECO_HIGH` writer - NA"] +pub type HP_REG_L2_MEM_RDN_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_rdn_eco_high(&self) -> HP_REG_L2_MEM_RDN_ECO_HIGH_R { + HP_REG_L2_MEM_RDN_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_RDN_ECO_HIGH") + .field( + "hp_reg_l2_mem_rdn_eco_high", + &format_args!("{}", self.hp_reg_l2_mem_rdn_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_rdn_eco_high( + &mut self, + ) -> HP_REG_L2_MEM_RDN_ECO_HIGH_W { + HP_REG_L2_MEM_RDN_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_rdn_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_rdn_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_RDN_ECO_HIGH_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_RDN_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_rdn_eco_high::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_RDN_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_rdn_eco_high::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_RDN_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_RDN_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for HP_L2_MEM_RDN_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_rdn_eco_low.rs b/esp32p4/src/hp_sys/hp_l2_mem_rdn_eco_low.rs new file mode 100644 index 0000000000..6a47e6d48b --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_rdn_eco_low.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L2_MEM_RDN_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_RDN_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_MEM_RDN_ECO_LOW` reader - NA"] +pub type HP_REG_L2_MEM_RDN_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `HP_REG_L2_MEM_RDN_ECO_LOW` writer - NA"] +pub type HP_REG_L2_MEM_RDN_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_rdn_eco_low(&self) -> HP_REG_L2_MEM_RDN_ECO_LOW_R { + HP_REG_L2_MEM_RDN_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_RDN_ECO_LOW") + .field( + "hp_reg_l2_mem_rdn_eco_low", + &format_args!("{}", self.hp_reg_l2_mem_rdn_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_rdn_eco_low( + &mut self, + ) -> HP_REG_L2_MEM_RDN_ECO_LOW_W { + HP_REG_L2_MEM_RDN_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_rdn_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_rdn_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_RDN_ECO_LOW_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_RDN_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_rdn_eco_low::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_RDN_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_rdn_eco_low::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_RDN_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_RDN_ECO_LOW to value 0"] +impl crate::Resettable for HP_L2_MEM_RDN_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_refresh.rs b/esp32p4/src/hp_sys/hp_l2_mem_refresh.rs new file mode 100644 index 0000000000..872afb1bb6 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_refresh.rs @@ -0,0 +1,260 @@ +#[doc = "Register `HP_L2_MEM_REFRESH` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_REFRESH` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_MEM_UNIT0_REFERSH_EN` reader - NA"] +pub type HP_REG_L2_MEM_UNIT0_REFERSH_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_UNIT0_REFERSH_EN` writer - NA"] +pub type HP_REG_L2_MEM_UNIT0_REFERSH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_UNIT1_REFERSH_EN` reader - NA"] +pub type HP_REG_L2_MEM_UNIT1_REFERSH_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_UNIT1_REFERSH_EN` writer - NA"] +pub type HP_REG_L2_MEM_UNIT1_REFERSH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_UNIT2_REFERSH_EN` reader - NA"] +pub type HP_REG_L2_MEM_UNIT2_REFERSH_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_UNIT2_REFERSH_EN` writer - NA"] +pub type HP_REG_L2_MEM_UNIT2_REFERSH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_UNIT3_REFERSH_EN` reader - NA"] +pub type HP_REG_L2_MEM_UNIT3_REFERSH_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_UNIT3_REFERSH_EN` writer - NA"] +pub type HP_REG_L2_MEM_UNIT3_REFERSH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_UNIT4_REFERSH_EN` reader - NA"] +pub type HP_REG_L2_MEM_UNIT4_REFERSH_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_UNIT4_REFERSH_EN` writer - NA"] +pub type HP_REG_L2_MEM_UNIT4_REFERSH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_UNIT5_REFERSH_EN` reader - NA"] +pub type HP_REG_L2_MEM_UNIT5_REFERSH_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_UNIT5_REFERSH_EN` writer - NA"] +pub type HP_REG_L2_MEM_UNIT5_REFERSH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_REFERSH_CNT_RESET` reader - Set 1 to reset l2mem_refresh_cnt"] +pub type HP_REG_L2_MEM_REFERSH_CNT_RESET_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_REFERSH_CNT_RESET` writer - Set 1 to reset l2mem_refresh_cnt"] +pub type HP_REG_L2_MEM_REFERSH_CNT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_L2_MEM_UNIT0_REFRESH_DONE` reader - NA"] +pub type HP_REG_L2_MEM_UNIT0_REFRESH_DONE_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_UNIT1_REFRESH_DONE` reader - NA"] +pub type HP_REG_L2_MEM_UNIT1_REFRESH_DONE_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_UNIT2_REFRESH_DONE` reader - NA"] +pub type HP_REG_L2_MEM_UNIT2_REFRESH_DONE_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_UNIT3_REFRESH_DONE` reader - NA"] +pub type HP_REG_L2_MEM_UNIT3_REFRESH_DONE_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_UNIT4_REFRESH_DONE` reader - NA"] +pub type HP_REG_L2_MEM_UNIT4_REFRESH_DONE_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_UNIT5_REFRESH_DONE` reader - NA"] +pub type HP_REG_L2_MEM_UNIT5_REFRESH_DONE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit0_refersh_en(&self) -> HP_REG_L2_MEM_UNIT0_REFERSH_EN_R { + HP_REG_L2_MEM_UNIT0_REFERSH_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit1_refersh_en(&self) -> HP_REG_L2_MEM_UNIT1_REFERSH_EN_R { + HP_REG_L2_MEM_UNIT1_REFERSH_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit2_refersh_en(&self) -> HP_REG_L2_MEM_UNIT2_REFERSH_EN_R { + HP_REG_L2_MEM_UNIT2_REFERSH_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit3_refersh_en(&self) -> HP_REG_L2_MEM_UNIT3_REFERSH_EN_R { + HP_REG_L2_MEM_UNIT3_REFERSH_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit4_refersh_en(&self) -> HP_REG_L2_MEM_UNIT4_REFERSH_EN_R { + HP_REG_L2_MEM_UNIT4_REFERSH_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit5_refersh_en(&self) -> HP_REG_L2_MEM_UNIT5_REFERSH_EN_R { + HP_REG_L2_MEM_UNIT5_REFERSH_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set 1 to reset l2mem_refresh_cnt"] + #[inline(always)] + pub fn hp_reg_l2_mem_refersh_cnt_reset(&self) -> HP_REG_L2_MEM_REFERSH_CNT_RESET_R { + HP_REG_L2_MEM_REFERSH_CNT_RESET_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit0_refresh_done(&self) -> HP_REG_L2_MEM_UNIT0_REFRESH_DONE_R { + HP_REG_L2_MEM_UNIT0_REFRESH_DONE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit1_refresh_done(&self) -> HP_REG_L2_MEM_UNIT1_REFRESH_DONE_R { + HP_REG_L2_MEM_UNIT1_REFRESH_DONE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit2_refresh_done(&self) -> HP_REG_L2_MEM_UNIT2_REFRESH_DONE_R { + HP_REG_L2_MEM_UNIT2_REFRESH_DONE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit3_refresh_done(&self) -> HP_REG_L2_MEM_UNIT3_REFRESH_DONE_R { + HP_REG_L2_MEM_UNIT3_REFRESH_DONE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit4_refresh_done(&self) -> HP_REG_L2_MEM_UNIT4_REFRESH_DONE_R { + HP_REG_L2_MEM_UNIT4_REFRESH_DONE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn hp_reg_l2_mem_unit5_refresh_done(&self) -> HP_REG_L2_MEM_UNIT5_REFRESH_DONE_R { + HP_REG_L2_MEM_UNIT5_REFRESH_DONE_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_REFRESH") + .field( + "hp_reg_l2_mem_unit0_refersh_en", + &format_args!("{}", self.hp_reg_l2_mem_unit0_refersh_en().bit()), + ) + .field( + "hp_reg_l2_mem_unit1_refersh_en", + &format_args!("{}", self.hp_reg_l2_mem_unit1_refersh_en().bit()), + ) + .field( + "hp_reg_l2_mem_unit2_refersh_en", + &format_args!("{}", self.hp_reg_l2_mem_unit2_refersh_en().bit()), + ) + .field( + "hp_reg_l2_mem_unit3_refersh_en", + &format_args!("{}", self.hp_reg_l2_mem_unit3_refersh_en().bit()), + ) + .field( + "hp_reg_l2_mem_unit4_refersh_en", + &format_args!("{}", self.hp_reg_l2_mem_unit4_refersh_en().bit()), + ) + .field( + "hp_reg_l2_mem_unit5_refersh_en", + &format_args!("{}", self.hp_reg_l2_mem_unit5_refersh_en().bit()), + ) + .field( + "hp_reg_l2_mem_refersh_cnt_reset", + &format_args!("{}", self.hp_reg_l2_mem_refersh_cnt_reset().bit()), + ) + .field( + "hp_reg_l2_mem_unit0_refresh_done", + &format_args!("{}", self.hp_reg_l2_mem_unit0_refresh_done().bit()), + ) + .field( + "hp_reg_l2_mem_unit1_refresh_done", + &format_args!("{}", self.hp_reg_l2_mem_unit1_refresh_done().bit()), + ) + .field( + "hp_reg_l2_mem_unit2_refresh_done", + &format_args!("{}", self.hp_reg_l2_mem_unit2_refresh_done().bit()), + ) + .field( + "hp_reg_l2_mem_unit3_refresh_done", + &format_args!("{}", self.hp_reg_l2_mem_unit3_refresh_done().bit()), + ) + .field( + "hp_reg_l2_mem_unit4_refresh_done", + &format_args!("{}", self.hp_reg_l2_mem_unit4_refresh_done().bit()), + ) + .field( + "hp_reg_l2_mem_unit5_refresh_done", + &format_args!("{}", self.hp_reg_l2_mem_unit5_refresh_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_unit0_refersh_en( + &mut self, + ) -> HP_REG_L2_MEM_UNIT0_REFERSH_EN_W { + HP_REG_L2_MEM_UNIT0_REFERSH_EN_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_unit1_refersh_en( + &mut self, + ) -> HP_REG_L2_MEM_UNIT1_REFERSH_EN_W { + HP_REG_L2_MEM_UNIT1_REFERSH_EN_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_unit2_refersh_en( + &mut self, + ) -> HP_REG_L2_MEM_UNIT2_REFERSH_EN_W { + HP_REG_L2_MEM_UNIT2_REFERSH_EN_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_unit3_refersh_en( + &mut self, + ) -> HP_REG_L2_MEM_UNIT3_REFERSH_EN_W { + HP_REG_L2_MEM_UNIT3_REFERSH_EN_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_unit4_refersh_en( + &mut self, + ) -> HP_REG_L2_MEM_UNIT4_REFERSH_EN_W { + HP_REG_L2_MEM_UNIT4_REFERSH_EN_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_unit5_refersh_en( + &mut self, + ) -> HP_REG_L2_MEM_UNIT5_REFERSH_EN_W { + HP_REG_L2_MEM_UNIT5_REFERSH_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Set 1 to reset l2mem_refresh_cnt"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_refersh_cnt_reset( + &mut self, + ) -> HP_REG_L2_MEM_REFERSH_CNT_RESET_W { + HP_REG_L2_MEM_REFERSH_CNT_RESET_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_refresh::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_refresh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_REFRESH_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_REFRESH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_refresh::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_REFRESH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_refresh::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_REFRESH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_REFRESH to value 0x40"] +impl crate::Resettable for HP_L2_MEM_REFRESH_SPEC { + const RESET_VALUE: Self::Ux = 0x40; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_subsize.rs b/esp32p4/src/hp_sys/hp_l2_mem_subsize.rs new file mode 100644 index 0000000000..ea16afcfb3 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_subsize.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L2_MEM_SUBSIZE` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_SUBSIZE` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_MEM_SUB_BLKSIZE` reader - l2mem sub block size 00=>32 01=>64 10=>128 11=>256"] +pub type HP_REG_L2_MEM_SUB_BLKSIZE_R = crate::FieldReader; +#[doc = "Field `HP_REG_L2_MEM_SUB_BLKSIZE` writer - l2mem sub block size 00=>32 01=>64 10=>128 11=>256"] +pub type HP_REG_L2_MEM_SUB_BLKSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - l2mem sub block size 00=>32 01=>64 10=>128 11=>256"] + #[inline(always)] + pub fn hp_reg_l2_mem_sub_blksize(&self) -> HP_REG_L2_MEM_SUB_BLKSIZE_R { + HP_REG_L2_MEM_SUB_BLKSIZE_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_SUBSIZE") + .field( + "hp_reg_l2_mem_sub_blksize", + &format_args!("{}", self.hp_reg_l2_mem_sub_blksize().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - l2mem sub block size 00=>32 01=>64 10=>128 11=>256"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_sub_blksize( + &mut self, + ) -> HP_REG_L2_MEM_SUB_BLKSIZE_W { + HP_REG_L2_MEM_SUB_BLKSIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_subsize::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_subsize::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_SUBSIZE_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_SUBSIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_subsize::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_SUBSIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_subsize::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_SUBSIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_SUBSIZE to value 0"] +impl crate::Resettable for HP_L2_MEM_SUBSIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_mem_sw_ecc_bwe_mask.rs b/esp32p4/src/hp_sys/hp_l2_mem_sw_ecc_bwe_mask.rs new file mode 100644 index 0000000000..eb3613bee4 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_mem_sw_ecc_bwe_mask.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L2_MEM_SW_ECC_BWE_MASK` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_MEM_SW_ECC_BWE_MASK` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL` reader - Set 1 to mask bwe hamming code bit"] +pub type HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL` writer - Set 1 to mask bwe hamming code bit"] +pub type HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 to mask bwe hamming code bit"] + #[inline(always)] + pub fn hp_reg_l2_mem_sw_ecc_bwe_mask_ctrl(&self) -> HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_R { + HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_MEM_SW_ECC_BWE_MASK") + .field( + "hp_reg_l2_mem_sw_ecc_bwe_mask_ctrl", + &format_args!("{}", self.hp_reg_l2_mem_sw_ecc_bwe_mask_ctrl().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 to mask bwe hamming code bit"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_mem_sw_ecc_bwe_mask_ctrl( + &mut self, + ) -> HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_W { + HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_mem_sw_ecc_bwe_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_mem_sw_ecc_bwe_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_MEM_SW_ECC_BWE_MASK_SPEC; +impl crate::RegisterSpec for HP_L2_MEM_SW_ECC_BWE_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_mem_sw_ecc_bwe_mask::R`](R) reader structure"] +impl crate::Readable for HP_L2_MEM_SW_ECC_BWE_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_mem_sw_ecc_bwe_mask::W`](W) writer structure"] +impl crate::Writable for HP_L2_MEM_SW_ECC_BWE_MASK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_MEM_SW_ECC_BWE_MASK to value 0"] +impl crate::Resettable for HP_L2_MEM_SW_ECC_BWE_MASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_l2_rom_pwr_ctrl0.rs b/esp32p4/src/hp_sys/hp_l2_rom_pwr_ctrl0.rs new file mode 100644 index 0000000000..2b2b424eac --- /dev/null +++ b/esp32p4/src/hp_sys/hp_l2_rom_pwr_ctrl0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_L2_ROM_PWR_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_L2_ROM_PWR_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_L2_ROM_CLK_FORCE_ON` reader - l2_rom clk gating force on"] +pub type HP_REG_L2_ROM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `HP_REG_L2_ROM_CLK_FORCE_ON` writer - l2_rom clk gating force on"] +pub type HP_REG_L2_ROM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - l2_rom clk gating force on"] + #[inline(always)] + pub fn hp_reg_l2_rom_clk_force_on(&self) -> HP_REG_L2_ROM_CLK_FORCE_ON_R { + HP_REG_L2_ROM_CLK_FORCE_ON_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_L2_ROM_PWR_CTRL0") + .field( + "hp_reg_l2_rom_clk_force_on", + &format_args!("{}", self.hp_reg_l2_rom_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - l2_rom clk gating force on"] + #[inline(always)] + #[must_use] + pub fn hp_reg_l2_rom_clk_force_on( + &mut self, + ) -> HP_REG_L2_ROM_CLK_FORCE_ON_W { + HP_REG_L2_ROM_CLK_FORCE_ON_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_l2_rom_pwr_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_l2_rom_pwr_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_L2_ROM_PWR_CTRL0_SPEC; +impl crate::RegisterSpec for HP_L2_ROM_PWR_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_l2_rom_pwr_ctrl0::R`](R) reader structure"] +impl crate::Readable for HP_L2_ROM_PWR_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_l2_rom_pwr_ctrl0::W`](W) writer structure"] +impl crate::Writable for HP_L2_ROM_PWR_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_L2_ROM_PWR_CTRL0 to value 0"] +impl crate::Resettable for HP_L2_ROM_PWR_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_peri1_apb_postw_en.rs b/esp32p4/src/hp_sys/hp_peri1_apb_postw_en.rs new file mode 100644 index 0000000000..ee814c4d0c --- /dev/null +++ b/esp32p4/src/hp_sys/hp_peri1_apb_postw_en.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_PERI1_APB_POSTW_EN` reader"] +pub type R = crate::R; +#[doc = "Register `HP_PERI1_APB_POSTW_EN` writer"] +pub type W = crate::W; +#[doc = "Field `HP_PERI1_APB_POSTW_EN` reader - hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"] +pub type HP_PERI1_APB_POSTW_EN_R = crate::BitReader; +#[doc = "Field `HP_PERI1_APB_POSTW_EN` writer - hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"] +pub type HP_PERI1_APB_POSTW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"] + #[inline(always)] + pub fn hp_peri1_apb_postw_en(&self) -> HP_PERI1_APB_POSTW_EN_R { + HP_PERI1_APB_POSTW_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PERI1_APB_POSTW_EN") + .field( + "hp_peri1_apb_postw_en", + &format_args!("{}", self.hp_peri1_apb_postw_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"] + #[inline(always)] + #[must_use] + pub fn hp_peri1_apb_postw_en(&mut self) -> HP_PERI1_APB_POSTW_EN_W { + HP_PERI1_APB_POSTW_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_peri1_apb_postw_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_peri1_apb_postw_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PERI1_APB_POSTW_EN_SPEC; +impl crate::RegisterSpec for HP_PERI1_APB_POSTW_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_peri1_apb_postw_en::R`](R) reader structure"] +impl crate::Readable for HP_PERI1_APB_POSTW_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_peri1_apb_postw_en::W`](W) writer structure"] +impl crate::Writable for HP_PERI1_APB_POSTW_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_PERI1_APB_POSTW_EN to value 0"] +impl crate::Resettable for HP_PERI1_APB_POSTW_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_peri_mem_clk_force_on.rs b/esp32p4/src/hp_sys/hp_peri_mem_clk_force_on.rs new file mode 100644 index 0000000000..b721bd7a98 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_peri_mem_clk_force_on.rs @@ -0,0 +1,131 @@ +#[doc = "Register `HP_PERI_MEM_CLK_FORCE_ON` reader"] +pub type R = crate::R; +#[doc = "Register `HP_PERI_MEM_CLK_FORCE_ON` writer"] +pub type W = crate::W; +#[doc = "Field `HP_RMT_MEM_CLK_FORCE_ON` reader - Set this bit to force on mem clk in rmt"] +pub type HP_RMT_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `HP_RMT_MEM_CLK_FORCE_ON` writer - Set this bit to force on mem clk in rmt"] +pub type HP_RMT_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON` reader - Set this bit to force on tx mem clk in bitscrambler"] +pub type HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON` writer - Set this bit to force on tx mem clk in bitscrambler"] +pub type HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON` reader - Set this bit to force on rx mem clk in bitscrambler"] +pub type HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON` writer - Set this bit to force on rx mem clk in bitscrambler"] +pub type HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_GDMA_MEM_CLK_FORCE_ON` reader - Set this bit to force on mem clk in gdma"] +pub type HP_GDMA_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `HP_GDMA_MEM_CLK_FORCE_ON` writer - Set this bit to force on mem clk in gdma"] +pub type HP_GDMA_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to force on mem clk in rmt"] + #[inline(always)] + pub fn hp_rmt_mem_clk_force_on(&self) -> HP_RMT_MEM_CLK_FORCE_ON_R { + HP_RMT_MEM_CLK_FORCE_ON_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to force on tx mem clk in bitscrambler"] + #[inline(always)] + pub fn hp_bitscrambler_tx_mem_clk_force_on(&self) -> HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_R { + HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to force on rx mem clk in bitscrambler"] + #[inline(always)] + pub fn hp_bitscrambler_rx_mem_clk_force_on(&self) -> HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_R { + HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to force on mem clk in gdma"] + #[inline(always)] + pub fn hp_gdma_mem_clk_force_on(&self) -> HP_GDMA_MEM_CLK_FORCE_ON_R { + HP_GDMA_MEM_CLK_FORCE_ON_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PERI_MEM_CLK_FORCE_ON") + .field( + "hp_rmt_mem_clk_force_on", + &format_args!("{}", self.hp_rmt_mem_clk_force_on().bit()), + ) + .field( + "hp_bitscrambler_tx_mem_clk_force_on", + &format_args!("{}", self.hp_bitscrambler_tx_mem_clk_force_on().bit()), + ) + .field( + "hp_bitscrambler_rx_mem_clk_force_on", + &format_args!("{}", self.hp_bitscrambler_rx_mem_clk_force_on().bit()), + ) + .field( + "hp_gdma_mem_clk_force_on", + &format_args!("{}", self.hp_gdma_mem_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to force on mem clk in rmt"] + #[inline(always)] + #[must_use] + pub fn hp_rmt_mem_clk_force_on( + &mut self, + ) -> HP_RMT_MEM_CLK_FORCE_ON_W { + HP_RMT_MEM_CLK_FORCE_ON_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to force on tx mem clk in bitscrambler"] + #[inline(always)] + #[must_use] + pub fn hp_bitscrambler_tx_mem_clk_force_on( + &mut self, + ) -> HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_W { + HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to force on rx mem clk in bitscrambler"] + #[inline(always)] + #[must_use] + pub fn hp_bitscrambler_rx_mem_clk_force_on( + &mut self, + ) -> HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_W { + HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to force on mem clk in gdma"] + #[inline(always)] + #[must_use] + pub fn hp_gdma_mem_clk_force_on( + &mut self, + ) -> HP_GDMA_MEM_CLK_FORCE_ON_W { + HP_GDMA_MEM_CLK_FORCE_ON_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "hp peri mem clk force on regpster\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_peri_mem_clk_force_on::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_peri_mem_clk_force_on::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PERI_MEM_CLK_FORCE_ON_SPEC; +impl crate::RegisterSpec for HP_PERI_MEM_CLK_FORCE_ON_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_peri_mem_clk_force_on::R`](R) reader structure"] +impl crate::Readable for HP_PERI_MEM_CLK_FORCE_ON_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_peri_mem_clk_force_on::W`](W) writer structure"] +impl crate::Writable for HP_PERI_MEM_CLK_FORCE_ON_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_PERI_MEM_CLK_FORCE_ON to value 0"] +impl crate::Resettable for HP_PERI_MEM_CLK_FORCE_ON_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_probe_out.rs b/esp32p4/src/hp_sys/hp_probe_out.rs new file mode 100644 index 0000000000..482516a9d9 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_probe_out.rs @@ -0,0 +1,39 @@ +#[doc = "Register `HP_PROBE_OUT` reader"] +pub type R = crate::R; +#[doc = "Field `HP_REG_PROBE_TOP_OUT` reader - NA"] +pub type HP_REG_PROBE_TOP_OUT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn hp_reg_probe_top_out(&self) -> HP_REG_PROBE_TOP_OUT_R { + HP_REG_PROBE_TOP_OUT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PROBE_OUT") + .field( + "hp_reg_probe_top_out", + &format_args!("{}", self.hp_reg_probe_top_out().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_probe_out::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PROBE_OUT_SPEC; +impl crate::RegisterSpec for HP_PROBE_OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_probe_out::R`](R) reader structure"] +impl crate::Readable for HP_PROBE_OUT_SPEC {} +#[doc = "`reset()` method sets HP_PROBE_OUT to value 0"] +impl crate::Resettable for HP_PROBE_OUT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_probea_ctrl.rs b/esp32p4/src/hp_sys/hp_probea_ctrl.rs new file mode 100644 index 0000000000..e2fcfd9d4b --- /dev/null +++ b/esp32p4/src/hp_sys/hp_probea_ctrl.rs @@ -0,0 +1,142 @@ +#[doc = "Register `HP_PROBEA_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_PROBEA_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_PROBE_A_MOD_SEL` reader - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out\\[31:0\\] in a mode"] +pub type HP_REG_PROBE_A_MOD_SEL_R = crate::FieldReader; +#[doc = "Field `HP_REG_PROBE_A_MOD_SEL` writer - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out\\[31:0\\] in a mode"] +pub type HP_REG_PROBE_A_MOD_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `HP_REG_PROBE_A_TOP_SEL` reader - Tihs field is used to selec module's probe_out\\[31:0\\] as probe out in a mode"] +pub type HP_REG_PROBE_A_TOP_SEL_R = crate::FieldReader; +#[doc = "Field `HP_REG_PROBE_A_TOP_SEL` writer - Tihs field is used to selec module's probe_out\\[31:0\\] as probe out in a mode"] +pub type HP_REG_PROBE_A_TOP_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HP_REG_PROBE_L_SEL` reader - Tihs field is used to selec probe_out\\[31:16\\]"] +pub type HP_REG_PROBE_L_SEL_R = crate::FieldReader; +#[doc = "Field `HP_REG_PROBE_L_SEL` writer - Tihs field is used to selec probe_out\\[31:16\\]"] +pub type HP_REG_PROBE_L_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_REG_PROBE_H_SEL` reader - Tihs field is used to selec probe_out\\[31:16\\]"] +pub type HP_REG_PROBE_H_SEL_R = crate::FieldReader; +#[doc = "Field `HP_REG_PROBE_H_SEL` writer - Tihs field is used to selec probe_out\\[31:16\\]"] +pub type HP_REG_PROBE_H_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_REG_PROBE_GLOBAL_EN` reader - Set this bit to enable global debug probe in hp system."] +pub type HP_REG_PROBE_GLOBAL_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_PROBE_GLOBAL_EN` writer - Set this bit to enable global debug probe in hp system."] +pub type HP_REG_PROBE_GLOBAL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out\\[31:0\\] in a mode"] + #[inline(always)] + pub fn hp_reg_probe_a_mod_sel(&self) -> HP_REG_PROBE_A_MOD_SEL_R { + HP_REG_PROBE_A_MOD_SEL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Tihs field is used to selec module's probe_out\\[31:0\\] as probe out in a mode"] + #[inline(always)] + pub fn hp_reg_probe_a_top_sel(&self) -> HP_REG_PROBE_A_TOP_SEL_R { + HP_REG_PROBE_A_TOP_SEL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:25 - Tihs field is used to selec probe_out\\[31:16\\]"] + #[inline(always)] + pub fn hp_reg_probe_l_sel(&self) -> HP_REG_PROBE_L_SEL_R { + HP_REG_PROBE_L_SEL_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Tihs field is used to selec probe_out\\[31:16\\]"] + #[inline(always)] + pub fn hp_reg_probe_h_sel(&self) -> HP_REG_PROBE_H_SEL_R { + HP_REG_PROBE_H_SEL_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bit 28 - Set this bit to enable global debug probe in hp system."] + #[inline(always)] + pub fn hp_reg_probe_global_en(&self) -> HP_REG_PROBE_GLOBAL_EN_R { + HP_REG_PROBE_GLOBAL_EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PROBEA_CTRL") + .field( + "hp_reg_probe_a_mod_sel", + &format_args!("{}", self.hp_reg_probe_a_mod_sel().bits()), + ) + .field( + "hp_reg_probe_a_top_sel", + &format_args!("{}", self.hp_reg_probe_a_top_sel().bits()), + ) + .field( + "hp_reg_probe_l_sel", + &format_args!("{}", self.hp_reg_probe_l_sel().bits()), + ) + .field( + "hp_reg_probe_h_sel", + &format_args!("{}", self.hp_reg_probe_h_sel().bits()), + ) + .field( + "hp_reg_probe_global_en", + &format_args!("{}", self.hp_reg_probe_global_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out\\[31:0\\] in a mode"] + #[inline(always)] + #[must_use] + pub fn hp_reg_probe_a_mod_sel(&mut self) -> HP_REG_PROBE_A_MOD_SEL_W { + HP_REG_PROBE_A_MOD_SEL_W::new(self, 0) + } + #[doc = "Bits 16:23 - Tihs field is used to selec module's probe_out\\[31:0\\] as probe out in a mode"] + #[inline(always)] + #[must_use] + pub fn hp_reg_probe_a_top_sel(&mut self) -> HP_REG_PROBE_A_TOP_SEL_W { + HP_REG_PROBE_A_TOP_SEL_W::new(self, 16) + } + #[doc = "Bits 24:25 - Tihs field is used to selec probe_out\\[31:16\\]"] + #[inline(always)] + #[must_use] + pub fn hp_reg_probe_l_sel(&mut self) -> HP_REG_PROBE_L_SEL_W { + HP_REG_PROBE_L_SEL_W::new(self, 24) + } + #[doc = "Bits 26:27 - Tihs field is used to selec probe_out\\[31:16\\]"] + #[inline(always)] + #[must_use] + pub fn hp_reg_probe_h_sel(&mut self) -> HP_REG_PROBE_H_SEL_W { + HP_REG_PROBE_H_SEL_W::new(self, 26) + } + #[doc = "Bit 28 - Set this bit to enable global debug probe in hp system."] + #[inline(always)] + #[must_use] + pub fn hp_reg_probe_global_en(&mut self) -> HP_REG_PROBE_GLOBAL_EN_W { + HP_REG_PROBE_GLOBAL_EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_probea_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_probea_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PROBEA_CTRL_SPEC; +impl crate::RegisterSpec for HP_PROBEA_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_probea_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_PROBEA_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_probea_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_PROBEA_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_PROBEA_CTRL to value 0"] +impl crate::Resettable for HP_PROBEA_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_probeb_ctrl.rs b/esp32p4/src/hp_sys/hp_probeb_ctrl.rs new file mode 100644 index 0000000000..83780cd81e --- /dev/null +++ b/esp32p4/src/hp_sys/hp_probeb_ctrl.rs @@ -0,0 +1,104 @@ +#[doc = "Register `HP_PROBEB_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_PROBEB_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_PROBE_B_MOD_SEL` reader - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out\\[31:0\\] in b mode."] +pub type HP_REG_PROBE_B_MOD_SEL_R = crate::FieldReader; +#[doc = "Field `HP_REG_PROBE_B_MOD_SEL` writer - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out\\[31:0\\] in b mode."] +pub type HP_REG_PROBE_B_MOD_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `HP_REG_PROBE_B_TOP_SEL` reader - Tihs field is used to select module's probe_out\\[31:0\\] as probe_out in b mode"] +pub type HP_REG_PROBE_B_TOP_SEL_R = crate::FieldReader; +#[doc = "Field `HP_REG_PROBE_B_TOP_SEL` writer - Tihs field is used to select module's probe_out\\[31:0\\] as probe_out in b mode"] +pub type HP_REG_PROBE_B_TOP_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HP_REG_PROBE_B_EN` reader - Set this bit to enable b mode for debug probe. 1: b mode, 0: a mode."] +pub type HP_REG_PROBE_B_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_PROBE_B_EN` writer - Set this bit to enable b mode for debug probe. 1: b mode, 0: a mode."] +pub type HP_REG_PROBE_B_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out\\[31:0\\] in b mode."] + #[inline(always)] + pub fn hp_reg_probe_b_mod_sel(&self) -> HP_REG_PROBE_B_MOD_SEL_R { + HP_REG_PROBE_B_MOD_SEL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Tihs field is used to select module's probe_out\\[31:0\\] as probe_out in b mode"] + #[inline(always)] + pub fn hp_reg_probe_b_top_sel(&self) -> HP_REG_PROBE_B_TOP_SEL_R { + HP_REG_PROBE_B_TOP_SEL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - Set this bit to enable b mode for debug probe. 1: b mode, 0: a mode."] + #[inline(always)] + pub fn hp_reg_probe_b_en(&self) -> HP_REG_PROBE_B_EN_R { + HP_REG_PROBE_B_EN_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PROBEB_CTRL") + .field( + "hp_reg_probe_b_mod_sel", + &format_args!("{}", self.hp_reg_probe_b_mod_sel().bits()), + ) + .field( + "hp_reg_probe_b_top_sel", + &format_args!("{}", self.hp_reg_probe_b_top_sel().bits()), + ) + .field( + "hp_reg_probe_b_en", + &format_args!("{}", self.hp_reg_probe_b_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out\\[31:0\\] in b mode."] + #[inline(always)] + #[must_use] + pub fn hp_reg_probe_b_mod_sel(&mut self) -> HP_REG_PROBE_B_MOD_SEL_W { + HP_REG_PROBE_B_MOD_SEL_W::new(self, 0) + } + #[doc = "Bits 16:23 - Tihs field is used to select module's probe_out\\[31:0\\] as probe_out in b mode"] + #[inline(always)] + #[must_use] + pub fn hp_reg_probe_b_top_sel(&mut self) -> HP_REG_PROBE_B_TOP_SEL_W { + HP_REG_PROBE_B_TOP_SEL_W::new(self, 16) + } + #[doc = "Bit 24 - Set this bit to enable b mode for debug probe. 1: b mode, 0: a mode."] + #[inline(always)] + #[must_use] + pub fn hp_reg_probe_b_en(&mut self) -> HP_REG_PROBE_B_EN_W { + HP_REG_PROBE_B_EN_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_probeb_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_probeb_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PROBEB_CTRL_SPEC; +impl crate::RegisterSpec for HP_PROBEB_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_probeb_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_PROBEB_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_probeb_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_PROBEB_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_PROBEB_CTRL to value 0"] +impl crate::Resettable for HP_PROBEB_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_psram_flash_addr_interchange.rs b/esp32p4/src/hp_sys/hp_psram_flash_addr_interchange.rs new file mode 100644 index 0000000000..e3ca9d7ebd --- /dev/null +++ b/esp32p4/src/hp_sys/hp_psram_flash_addr_interchange.rs @@ -0,0 +1,79 @@ +#[doc = "Register `HP_PSRAM_FLASH_ADDR_INTERCHANGE` reader"] +pub type R = crate::R; +#[doc = "Register `HP_PSRAM_FLASH_ADDR_INTERCHANGE` writer"] +pub type W = crate::W; +#[doc = "Field `CPU` reader - Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache"] +pub type CPU_R = crate::BitReader; +#[doc = "Field `CPU` writer - Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache"] +pub type CPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb"] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb"] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache"] + #[inline(always)] + pub fn cpu(&self) -> CPU_R { + CPU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb"] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PSRAM_FLASH_ADDR_INTERCHANGE") + .field("cpu", &format_args!("{}", self.cpu().bit())) + .field("dma", &format_args!("{}", self.dma().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache"] + #[inline(always)] + #[must_use] + pub fn cpu(&mut self) -> CPU_W { + CPU_W::new(self, 0) + } + #[doc = "Bit 1 - Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb"] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_psram_flash_addr_interchange::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_psram_flash_addr_interchange::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PSRAM_FLASH_ADDR_INTERCHANGE_SPEC; +impl crate::RegisterSpec for HP_PSRAM_FLASH_ADDR_INTERCHANGE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_psram_flash_addr_interchange::R`](R) reader structure"] +impl crate::Readable for HP_PSRAM_FLASH_ADDR_INTERCHANGE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_psram_flash_addr_interchange::W`](W) writer structure"] +impl crate::Writable for HP_PSRAM_FLASH_ADDR_INTERCHANGE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_PSRAM_FLASH_ADDR_INTERCHANGE to value 0"] +impl crate::Resettable for HP_PSRAM_FLASH_ADDR_INTERCHANGE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_rng_cfg.rs b/esp32p4/src/hp_sys/hp_rng_cfg.rs new file mode 100644 index 0000000000..39711ab5bb --- /dev/null +++ b/esp32p4/src/hp_sys/hp_rng_cfg.rs @@ -0,0 +1,96 @@ +#[doc = "Register `HP_RNG_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `HP_RNG_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `HP_RNG_SAMPLE_ENABLE` reader - enable rng sample chain"] +pub type HP_RNG_SAMPLE_ENABLE_R = crate::BitReader; +#[doc = "Field `HP_RNG_SAMPLE_ENABLE` writer - enable rng sample chain"] +pub type HP_RNG_SAMPLE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_RNG_CHAIN_CLK_DIV_NUM` reader - chain clk div num to pad for debug"] +pub type HP_RNG_CHAIN_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `HP_RNG_CHAIN_CLK_DIV_NUM` writer - chain clk div num to pad for debug"] +pub type HP_RNG_CHAIN_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HP_RNG_SAMPLE_CNT` reader - debug rng sample cnt"] +pub type HP_RNG_SAMPLE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - enable rng sample chain"] + #[inline(always)] + pub fn hp_rng_sample_enable(&self) -> HP_RNG_SAMPLE_ENABLE_R { + HP_RNG_SAMPLE_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 16:23 - chain clk div num to pad for debug"] + #[inline(always)] + pub fn hp_rng_chain_clk_div_num(&self) -> HP_RNG_CHAIN_CLK_DIV_NUM_R { + HP_RNG_CHAIN_CLK_DIV_NUM_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - debug rng sample cnt"] + #[inline(always)] + pub fn hp_rng_sample_cnt(&self) -> HP_RNG_SAMPLE_CNT_R { + HP_RNG_SAMPLE_CNT_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_RNG_CFG") + .field( + "hp_rng_sample_enable", + &format_args!("{}", self.hp_rng_sample_enable().bit()), + ) + .field( + "hp_rng_chain_clk_div_num", + &format_args!("{}", self.hp_rng_chain_clk_div_num().bits()), + ) + .field( + "hp_rng_sample_cnt", + &format_args!("{}", self.hp_rng_sample_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - enable rng sample chain"] + #[inline(always)] + #[must_use] + pub fn hp_rng_sample_enable(&mut self) -> HP_RNG_SAMPLE_ENABLE_W { + HP_RNG_SAMPLE_ENABLE_W::new(self, 0) + } + #[doc = "Bits 16:23 - chain clk div num to pad for debug"] + #[inline(always)] + #[must_use] + pub fn hp_rng_chain_clk_div_num(&mut self) -> HP_RNG_CHAIN_CLK_DIV_NUM_W { + HP_RNG_CHAIN_CLK_DIV_NUM_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "rng cfg register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rng_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rng_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_RNG_CFG_SPEC; +impl crate::RegisterSpec for HP_RNG_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_rng_cfg::R`](R) reader structure"] +impl crate::Readable for HP_RNG_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_rng_cfg::W`](W) writer structure"] +impl crate::Writable for HP_RNG_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_RNG_CFG to value 0"] +impl crate::Resettable for HP_RNG_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_rsa_pd_ctrl.rs b/esp32p4/src/hp_sys/hp_rsa_pd_ctrl.rs new file mode 100644 index 0000000000..78b6bca33e --- /dev/null +++ b/esp32p4/src/hp_sys/hp_rsa_pd_ctrl.rs @@ -0,0 +1,104 @@ +#[doc = "Register `HP_RSA_PD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_RSA_PD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_RSA_MEM_FORCE_PD` reader - Set this bit to power down rsa internal memory."] +pub type HP_RSA_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `HP_RSA_MEM_FORCE_PD` writer - Set this bit to power down rsa internal memory."] +pub type HP_RSA_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_RSA_MEM_FORCE_PU` reader - Set this bit to force power up rsa internal memory"] +pub type HP_RSA_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `HP_RSA_MEM_FORCE_PU` writer - Set this bit to force power up rsa internal memory"] +pub type HP_RSA_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_RSA_MEM_PD` reader - Set this bit to force power down rsa internal memory."] +pub type HP_RSA_MEM_PD_R = crate::BitReader; +#[doc = "Field `HP_RSA_MEM_PD` writer - Set this bit to force power down rsa internal memory."] +pub type HP_RSA_MEM_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to power down rsa internal memory."] + #[inline(always)] + pub fn hp_rsa_mem_force_pd(&self) -> HP_RSA_MEM_FORCE_PD_R { + HP_RSA_MEM_FORCE_PD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to force power up rsa internal memory"] + #[inline(always)] + pub fn hp_rsa_mem_force_pu(&self) -> HP_RSA_MEM_FORCE_PU_R { + HP_RSA_MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to force power down rsa internal memory."] + #[inline(always)] + pub fn hp_rsa_mem_pd(&self) -> HP_RSA_MEM_PD_R { + HP_RSA_MEM_PD_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_RSA_PD_CTRL") + .field( + "hp_rsa_mem_force_pd", + &format_args!("{}", self.hp_rsa_mem_force_pd().bit()), + ) + .field( + "hp_rsa_mem_force_pu", + &format_args!("{}", self.hp_rsa_mem_force_pu().bit()), + ) + .field( + "hp_rsa_mem_pd", + &format_args!("{}", self.hp_rsa_mem_pd().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to power down rsa internal memory."] + #[inline(always)] + #[must_use] + pub fn hp_rsa_mem_force_pd(&mut self) -> HP_RSA_MEM_FORCE_PD_W { + HP_RSA_MEM_FORCE_PD_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to force power up rsa internal memory"] + #[inline(always)] + #[must_use] + pub fn hp_rsa_mem_force_pu(&mut self) -> HP_RSA_MEM_FORCE_PU_W { + HP_RSA_MEM_FORCE_PU_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to force power down rsa internal memory."] + #[inline(always)] + #[must_use] + pub fn hp_rsa_mem_pd(&mut self) -> HP_RSA_MEM_PD_W { + HP_RSA_MEM_PD_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "rsa pd ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rsa_pd_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rsa_pd_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_RSA_PD_CTRL_SPEC; +impl crate::RegisterSpec for HP_RSA_PD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_rsa_pd_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_RSA_PD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_rsa_pd_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_RSA_PD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_RSA_PD_CTRL to value 0x02"] +impl crate::Resettable for HP_RSA_PD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_err_resp_ctrl.rs b/esp32p4/src/hp_sys/hp_tcm_err_resp_ctrl.rs new file mode 100644 index 0000000000..92be47c0be --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_err_resp_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_TCM_ERR_RESP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_TCM_ERR_RESP_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_TCM_ERR_RESP_EN` reader - Set 1 to turn on tcm error response"] +pub type HP_TCM_ERR_RESP_EN_R = crate::BitReader; +#[doc = "Field `HP_TCM_ERR_RESP_EN` writer - Set 1 to turn on tcm error response"] +pub type HP_TCM_ERR_RESP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 to turn on tcm error response"] + #[inline(always)] + pub fn hp_tcm_err_resp_en(&self) -> HP_TCM_ERR_RESP_EN_R { + HP_TCM_ERR_RESP_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_ERR_RESP_CTRL") + .field( + "hp_tcm_err_resp_en", + &format_args!("{}", self.hp_tcm_err_resp_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 to turn on tcm error response"] + #[inline(always)] + #[must_use] + pub fn hp_tcm_err_resp_en(&mut self) -> HP_TCM_ERR_RESP_EN_W { + HP_TCM_ERR_RESP_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_err_resp_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_err_resp_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_ERR_RESP_CTRL_SPEC; +impl crate::RegisterSpec for HP_TCM_ERR_RESP_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_err_resp_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_TCM_ERR_RESP_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_err_resp_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_TCM_ERR_RESP_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_ERR_RESP_CTRL to value 0"] +impl crate::Resettable for HP_TCM_ERR_RESP_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_init.rs b/esp32p4/src/hp_sys/hp_tcm_init.rs new file mode 100644 index 0000000000..90c665ee22 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_init.rs @@ -0,0 +1,96 @@ +#[doc = "Register `HP_TCM_INIT` reader"] +pub type R = crate::R; +#[doc = "Register `HP_TCM_INIT` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_TCM_INIT_EN` reader - NA"] +pub type HP_REG_TCM_INIT_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_TCM_INIT_EN` writer - NA"] +pub type HP_REG_TCM_INIT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_TCM_INIT_CNT_RESET` reader - Set 1 to reset tcm init cnt"] +pub type HP_REG_TCM_INIT_CNT_RESET_R = crate::BitReader; +#[doc = "Field `HP_REG_TCM_INIT_CNT_RESET` writer - Set 1 to reset tcm init cnt"] +pub type HP_REG_TCM_INIT_CNT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_TCM_INIT_DONE` reader - NA"] +pub type HP_REG_TCM_INIT_DONE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_tcm_init_en(&self) -> HP_REG_TCM_INIT_EN_R { + HP_REG_TCM_INIT_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set 1 to reset tcm init cnt"] + #[inline(always)] + pub fn hp_reg_tcm_init_cnt_reset(&self) -> HP_REG_TCM_INIT_CNT_RESET_R { + HP_REG_TCM_INIT_CNT_RESET_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn hp_reg_tcm_init_done(&self) -> HP_REG_TCM_INIT_DONE_R { + HP_REG_TCM_INIT_DONE_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_INIT") + .field( + "hp_reg_tcm_init_en", + &format_args!("{}", self.hp_reg_tcm_init_en().bit()), + ) + .field( + "hp_reg_tcm_init_cnt_reset", + &format_args!("{}", self.hp_reg_tcm_init_cnt_reset().bit()), + ) + .field( + "hp_reg_tcm_init_done", + &format_args!("{}", self.hp_reg_tcm_init_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_init_en(&mut self) -> HP_REG_TCM_INIT_EN_W { + HP_REG_TCM_INIT_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set 1 to reset tcm init cnt"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_init_cnt_reset(&mut self) -> HP_REG_TCM_INIT_CNT_RESET_W { + HP_REG_TCM_INIT_CNT_RESET_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_init::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_init::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_INIT_SPEC; +impl crate::RegisterSpec for HP_TCM_INIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_init::R`](R) reader structure"] +impl crate::Readable for HP_TCM_INIT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_init::W`](W) writer structure"] +impl crate::Writable for HP_TCM_INIT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_INIT to value 0x02"] +impl crate::Resettable for HP_TCM_INIT_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_int_clr.rs b/esp32p4/src/hp_sys/hp_tcm_int_clr.rs new file mode 100644 index 0000000000..3e0381d705 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_int_clr.rs @@ -0,0 +1,44 @@ +#[doc = "Register `HP_TCM_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `HP_TCM_PARITY_ERR_INT_CLR` writer - need_des"] +pub type HP_TCM_PARITY_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_tcm_parity_err_int_clr( + &mut self, + ) -> HP_TCM_PARITY_ERR_INT_CLR_W { + HP_TCM_PARITY_ERR_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_INT_CLR_SPEC; +impl crate::RegisterSpec for HP_TCM_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_int_clr::W`](W) writer structure"] +impl crate::Writable for HP_TCM_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_INT_CLR to value 0"] +impl crate::Resettable for HP_TCM_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_int_ena.rs b/esp32p4/src/hp_sys/hp_tcm_int_ena.rs new file mode 100644 index 0000000000..e41b74a0fe --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_int_ena.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_TCM_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `HP_TCM_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `HP_TCM_PARITY_ERR_INT_ENA` reader - need_des"] +pub type HP_TCM_PARITY_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_TCM_PARITY_ERR_INT_ENA` writer - need_des"] +pub type HP_TCM_PARITY_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_tcm_parity_err_int_ena(&self) -> HP_TCM_PARITY_ERR_INT_ENA_R { + HP_TCM_PARITY_ERR_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_INT_ENA") + .field( + "hp_tcm_parity_err_int_ena", + &format_args!("{}", self.hp_tcm_parity_err_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_tcm_parity_err_int_ena( + &mut self, + ) -> HP_TCM_PARITY_ERR_INT_ENA_W { + HP_TCM_PARITY_ERR_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_INT_ENA_SPEC; +impl crate::RegisterSpec for HP_TCM_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_int_ena::R`](R) reader structure"] +impl crate::Readable for HP_TCM_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_int_ena::W`](W) writer structure"] +impl crate::Writable for HP_TCM_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_INT_ENA to value 0"] +impl crate::Resettable for HP_TCM_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_int_raw.rs b/esp32p4/src/hp_sys/hp_tcm_int_raw.rs new file mode 100644 index 0000000000..d0505454b9 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_int_raw.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_TCM_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `HP_TCM_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `HP_TCM_PARITY_ERR_INT_RAW` reader - need_des"] +pub type HP_TCM_PARITY_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_TCM_PARITY_ERR_INT_RAW` writer - need_des"] +pub type HP_TCM_PARITY_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_tcm_parity_err_int_raw(&self) -> HP_TCM_PARITY_ERR_INT_RAW_R { + HP_TCM_PARITY_ERR_INT_RAW_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_INT_RAW") + .field( + "hp_tcm_parity_err_int_raw", + &format_args!("{}", self.hp_tcm_parity_err_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_tcm_parity_err_int_raw( + &mut self, + ) -> HP_TCM_PARITY_ERR_INT_RAW_W { + HP_TCM_PARITY_ERR_INT_RAW_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_INT_RAW_SPEC; +impl crate::RegisterSpec for HP_TCM_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_int_raw::R`](R) reader structure"] +impl crate::Readable for HP_TCM_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_int_raw::W`](W) writer structure"] +impl crate::Writable for HP_TCM_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_INT_RAW to value 0"] +impl crate::Resettable for HP_TCM_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_int_st.rs b/esp32p4/src/hp_sys/hp_tcm_int_st.rs new file mode 100644 index 0000000000..02fafaac5e --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_int_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `HP_TCM_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `HP_TCM_PARITY_ERR_INT_ST` reader - need_des"] +pub type HP_TCM_PARITY_ERR_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_tcm_parity_err_int_st(&self) -> HP_TCM_PARITY_ERR_INT_ST_R { + HP_TCM_PARITY_ERR_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_INT_ST") + .field( + "hp_tcm_parity_err_int_st", + &format_args!("{}", self.hp_tcm_parity_err_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_INT_ST_SPEC; +impl crate::RegisterSpec for HP_TCM_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_int_st::R`](R) reader structure"] +impl crate::Readable for HP_TCM_INT_ST_SPEC {} +#[doc = "`reset()` method sets HP_TCM_INT_ST to value 0"] +impl crate::Resettable for HP_TCM_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_parity_check_ctrl.rs b/esp32p4/src/hp_sys/hp_tcm_parity_check_ctrl.rs new file mode 100644 index 0000000000..031291b879 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_parity_check_ctrl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_TCM_PARITY_CHECK_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_TCM_PARITY_CHECK_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_TCM_PARITY_CHECK_EN` reader - Set 1 to turn on tcm parity check"] +pub type HP_TCM_PARITY_CHECK_EN_R = crate::BitReader; +#[doc = "Field `HP_TCM_PARITY_CHECK_EN` writer - Set 1 to turn on tcm parity check"] +pub type HP_TCM_PARITY_CHECK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 to turn on tcm parity check"] + #[inline(always)] + pub fn hp_tcm_parity_check_en(&self) -> HP_TCM_PARITY_CHECK_EN_R { + HP_TCM_PARITY_CHECK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_PARITY_CHECK_CTRL") + .field( + "hp_tcm_parity_check_en", + &format_args!("{}", self.hp_tcm_parity_check_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 to turn on tcm parity check"] + #[inline(always)] + #[must_use] + pub fn hp_tcm_parity_check_en( + &mut self, + ) -> HP_TCM_PARITY_CHECK_EN_W { + HP_TCM_PARITY_CHECK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_parity_check_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_parity_check_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_PARITY_CHECK_CTRL_SPEC; +impl crate::RegisterSpec for HP_TCM_PARITY_CHECK_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_parity_check_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_TCM_PARITY_CHECK_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_parity_check_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_TCM_PARITY_CHECK_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_PARITY_CHECK_CTRL to value 0"] +impl crate::Resettable for HP_TCM_PARITY_CHECK_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_parity_int_record.rs b/esp32p4/src/hp_sys/hp_tcm_parity_int_record.rs new file mode 100644 index 0000000000..c6c466d41e --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_parity_int_record.rs @@ -0,0 +1,39 @@ +#[doc = "Register `HP_TCM_PARITY_INT_RECORD` reader"] +pub type R = crate::R; +#[doc = "Field `HP_TCM_PARITY_ERR_INT_ADDR` reader - hp tcm_parity_err_addr"] +pub type HP_TCM_PARITY_ERR_INT_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - hp tcm_parity_err_addr"] + #[inline(always)] + pub fn hp_tcm_parity_err_int_addr(&self) -> HP_TCM_PARITY_ERR_INT_ADDR_R { + HP_TCM_PARITY_ERR_INT_ADDR_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_PARITY_INT_RECORD") + .field( + "hp_tcm_parity_err_int_addr", + &format_args!("{}", self.hp_tcm_parity_err_int_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_parity_int_record::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_PARITY_INT_RECORD_SPEC; +impl crate::RegisterSpec for HP_TCM_PARITY_INT_RECORD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_parity_int_record::R`](R) reader structure"] +impl crate::Readable for HP_TCM_PARITY_INT_RECORD_SPEC {} +#[doc = "`reset()` method sets HP_TCM_PARITY_INT_RECORD to value 0"] +impl crate::Resettable for HP_TCM_PARITY_INT_RECORD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_ram_pwr_ctrl0.rs b/esp32p4/src/hp_sys/hp_tcm_ram_pwr_ctrl0.rs new file mode 100644 index 0000000000..768e95b560 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_ram_pwr_ctrl0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_TCM_RAM_PWR_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_TCM_RAM_PWR_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_HP_TCM_CLK_FORCE_ON` reader - hp_tcm clk gatig force on"] +pub type HP_REG_HP_TCM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `HP_REG_HP_TCM_CLK_FORCE_ON` writer - hp_tcm clk gatig force on"] +pub type HP_REG_HP_TCM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - hp_tcm clk gatig force on"] + #[inline(always)] + pub fn hp_reg_hp_tcm_clk_force_on(&self) -> HP_REG_HP_TCM_CLK_FORCE_ON_R { + HP_REG_HP_TCM_CLK_FORCE_ON_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_RAM_PWR_CTRL0") + .field( + "hp_reg_hp_tcm_clk_force_on", + &format_args!("{}", self.hp_reg_hp_tcm_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - hp_tcm clk gatig force on"] + #[inline(always)] + #[must_use] + pub fn hp_reg_hp_tcm_clk_force_on( + &mut self, + ) -> HP_REG_HP_TCM_CLK_FORCE_ON_W { + HP_REG_HP_TCM_CLK_FORCE_ON_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_ram_pwr_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_ram_pwr_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_RAM_PWR_CTRL0_SPEC; +impl crate::RegisterSpec for HP_TCM_RAM_PWR_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_ram_pwr_ctrl0::R`](R) reader structure"] +impl crate::Readable for HP_TCM_RAM_PWR_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_ram_pwr_ctrl0::W`](W) writer structure"] +impl crate::Writable for HP_TCM_RAM_PWR_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_RAM_PWR_CTRL0 to value 0"] +impl crate::Resettable for HP_TCM_RAM_PWR_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_ram_wrr_config.rs b/esp32p4/src/hp_sys/hp_tcm_ram_wrr_config.rs new file mode 100644 index 0000000000..c8fe20da01 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_ram_wrr_config.rs @@ -0,0 +1,255 @@ +#[doc = "Register `HP_TCM_RAM_WRR_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `HP_TCM_RAM_WRR_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_TCM_RAM_IBUS0_WT` reader - weight value of ibus0"] +pub type HP_REG_TCM_RAM_IBUS0_WT_R = crate::FieldReader; +#[doc = "Field `HP_REG_TCM_RAM_IBUS0_WT` writer - weight value of ibus0"] +pub type HP_REG_TCM_RAM_IBUS0_WT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_REG_TCM_RAM_IBUS1_WT` reader - weight value of ibus1"] +pub type HP_REG_TCM_RAM_IBUS1_WT_R = crate::FieldReader; +#[doc = "Field `HP_REG_TCM_RAM_IBUS1_WT` writer - weight value of ibus1"] +pub type HP_REG_TCM_RAM_IBUS1_WT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_REG_TCM_RAM_IBUS2_WT` reader - weight value of ibus2"] +pub type HP_REG_TCM_RAM_IBUS2_WT_R = crate::FieldReader; +#[doc = "Field `HP_REG_TCM_RAM_IBUS2_WT` writer - weight value of ibus2"] +pub type HP_REG_TCM_RAM_IBUS2_WT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_REG_TCM_RAM_IBUS3_WT` reader - weight value of ibus3"] +pub type HP_REG_TCM_RAM_IBUS3_WT_R = crate::FieldReader; +#[doc = "Field `HP_REG_TCM_RAM_IBUS3_WT` writer - weight value of ibus3"] +pub type HP_REG_TCM_RAM_IBUS3_WT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_REG_TCM_RAM_DBUS0_WT` reader - weight value of dbus0"] +pub type HP_REG_TCM_RAM_DBUS0_WT_R = crate::FieldReader; +#[doc = "Field `HP_REG_TCM_RAM_DBUS0_WT` writer - weight value of dbus0"] +pub type HP_REG_TCM_RAM_DBUS0_WT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_REG_TCM_RAM_DBUS1_WT` reader - weight value of dbus1"] +pub type HP_REG_TCM_RAM_DBUS1_WT_R = crate::FieldReader; +#[doc = "Field `HP_REG_TCM_RAM_DBUS1_WT` writer - weight value of dbus1"] +pub type HP_REG_TCM_RAM_DBUS1_WT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_REG_TCM_RAM_DBUS2_WT` reader - weight value of dbus2"] +pub type HP_REG_TCM_RAM_DBUS2_WT_R = crate::FieldReader; +#[doc = "Field `HP_REG_TCM_RAM_DBUS2_WT` writer - weight value of dbus2"] +pub type HP_REG_TCM_RAM_DBUS2_WT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_REG_TCM_RAM_DBUS3_WT` reader - weight value of dbus3"] +pub type HP_REG_TCM_RAM_DBUS3_WT_R = crate::FieldReader; +#[doc = "Field `HP_REG_TCM_RAM_DBUS3_WT` writer - weight value of dbus3"] +pub type HP_REG_TCM_RAM_DBUS3_WT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_REG_TCM_RAM_DMA_WT` reader - weight value of dma"] +pub type HP_REG_TCM_RAM_DMA_WT_R = crate::FieldReader; +#[doc = "Field `HP_REG_TCM_RAM_DMA_WT` writer - weight value of dma"] +pub type HP_REG_TCM_RAM_DMA_WT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_REG_TCM_RAM_WRR_HIGH` reader - enable weighted round robin arbitration"] +pub type HP_REG_TCM_RAM_WRR_HIGH_R = crate::BitReader; +#[doc = "Field `HP_REG_TCM_RAM_WRR_HIGH` writer - enable weighted round robin arbitration"] +pub type HP_REG_TCM_RAM_WRR_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - weight value of ibus0"] + #[inline(always)] + pub fn hp_reg_tcm_ram_ibus0_wt(&self) -> HP_REG_TCM_RAM_IBUS0_WT_R { + HP_REG_TCM_RAM_IBUS0_WT_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - weight value of ibus1"] + #[inline(always)] + pub fn hp_reg_tcm_ram_ibus1_wt(&self) -> HP_REG_TCM_RAM_IBUS1_WT_R { + HP_REG_TCM_RAM_IBUS1_WT_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - weight value of ibus2"] + #[inline(always)] + pub fn hp_reg_tcm_ram_ibus2_wt(&self) -> HP_REG_TCM_RAM_IBUS2_WT_R { + HP_REG_TCM_RAM_IBUS2_WT_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - weight value of ibus3"] + #[inline(always)] + pub fn hp_reg_tcm_ram_ibus3_wt(&self) -> HP_REG_TCM_RAM_IBUS3_WT_R { + HP_REG_TCM_RAM_IBUS3_WT_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - weight value of dbus0"] + #[inline(always)] + pub fn hp_reg_tcm_ram_dbus0_wt(&self) -> HP_REG_TCM_RAM_DBUS0_WT_R { + HP_REG_TCM_RAM_DBUS0_WT_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - weight value of dbus1"] + #[inline(always)] + pub fn hp_reg_tcm_ram_dbus1_wt(&self) -> HP_REG_TCM_RAM_DBUS1_WT_R { + HP_REG_TCM_RAM_DBUS1_WT_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - weight value of dbus2"] + #[inline(always)] + pub fn hp_reg_tcm_ram_dbus2_wt(&self) -> HP_REG_TCM_RAM_DBUS2_WT_R { + HP_REG_TCM_RAM_DBUS2_WT_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - weight value of dbus3"] + #[inline(always)] + pub fn hp_reg_tcm_ram_dbus3_wt(&self) -> HP_REG_TCM_RAM_DBUS3_WT_R { + HP_REG_TCM_RAM_DBUS3_WT_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - weight value of dma"] + #[inline(always)] + pub fn hp_reg_tcm_ram_dma_wt(&self) -> HP_REG_TCM_RAM_DMA_WT_R { + HP_REG_TCM_RAM_DMA_WT_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 31 - enable weighted round robin arbitration"] + #[inline(always)] + pub fn hp_reg_tcm_ram_wrr_high(&self) -> HP_REG_TCM_RAM_WRR_HIGH_R { + HP_REG_TCM_RAM_WRR_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_RAM_WRR_CONFIG") + .field( + "hp_reg_tcm_ram_ibus0_wt", + &format_args!("{}", self.hp_reg_tcm_ram_ibus0_wt().bits()), + ) + .field( + "hp_reg_tcm_ram_ibus1_wt", + &format_args!("{}", self.hp_reg_tcm_ram_ibus1_wt().bits()), + ) + .field( + "hp_reg_tcm_ram_ibus2_wt", + &format_args!("{}", self.hp_reg_tcm_ram_ibus2_wt().bits()), + ) + .field( + "hp_reg_tcm_ram_ibus3_wt", + &format_args!("{}", self.hp_reg_tcm_ram_ibus3_wt().bits()), + ) + .field( + "hp_reg_tcm_ram_dbus0_wt", + &format_args!("{}", self.hp_reg_tcm_ram_dbus0_wt().bits()), + ) + .field( + "hp_reg_tcm_ram_dbus1_wt", + &format_args!("{}", self.hp_reg_tcm_ram_dbus1_wt().bits()), + ) + .field( + "hp_reg_tcm_ram_dbus2_wt", + &format_args!("{}", self.hp_reg_tcm_ram_dbus2_wt().bits()), + ) + .field( + "hp_reg_tcm_ram_dbus3_wt", + &format_args!("{}", self.hp_reg_tcm_ram_dbus3_wt().bits()), + ) + .field( + "hp_reg_tcm_ram_dma_wt", + &format_args!("{}", self.hp_reg_tcm_ram_dma_wt().bits()), + ) + .field( + "hp_reg_tcm_ram_wrr_high", + &format_args!("{}", self.hp_reg_tcm_ram_wrr_high().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - weight value of ibus0"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_ram_ibus0_wt( + &mut self, + ) -> HP_REG_TCM_RAM_IBUS0_WT_W { + HP_REG_TCM_RAM_IBUS0_WT_W::new(self, 0) + } + #[doc = "Bits 3:5 - weight value of ibus1"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_ram_ibus1_wt( + &mut self, + ) -> HP_REG_TCM_RAM_IBUS1_WT_W { + HP_REG_TCM_RAM_IBUS1_WT_W::new(self, 3) + } + #[doc = "Bits 6:8 - weight value of ibus2"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_ram_ibus2_wt( + &mut self, + ) -> HP_REG_TCM_RAM_IBUS2_WT_W { + HP_REG_TCM_RAM_IBUS2_WT_W::new(self, 6) + } + #[doc = "Bits 9:11 - weight value of ibus3"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_ram_ibus3_wt( + &mut self, + ) -> HP_REG_TCM_RAM_IBUS3_WT_W { + HP_REG_TCM_RAM_IBUS3_WT_W::new(self, 9) + } + #[doc = "Bits 12:14 - weight value of dbus0"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_ram_dbus0_wt( + &mut self, + ) -> HP_REG_TCM_RAM_DBUS0_WT_W { + HP_REG_TCM_RAM_DBUS0_WT_W::new(self, 12) + } + #[doc = "Bits 15:17 - weight value of dbus1"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_ram_dbus1_wt( + &mut self, + ) -> HP_REG_TCM_RAM_DBUS1_WT_W { + HP_REG_TCM_RAM_DBUS1_WT_W::new(self, 15) + } + #[doc = "Bits 18:20 - weight value of dbus2"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_ram_dbus2_wt( + &mut self, + ) -> HP_REG_TCM_RAM_DBUS2_WT_W { + HP_REG_TCM_RAM_DBUS2_WT_W::new(self, 18) + } + #[doc = "Bits 21:23 - weight value of dbus3"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_ram_dbus3_wt( + &mut self, + ) -> HP_REG_TCM_RAM_DBUS3_WT_W { + HP_REG_TCM_RAM_DBUS3_WT_W::new(self, 21) + } + #[doc = "Bits 24:26 - weight value of dma"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_ram_dma_wt(&mut self) -> HP_REG_TCM_RAM_DMA_WT_W { + HP_REG_TCM_RAM_DMA_WT_W::new(self, 24) + } + #[doc = "Bit 31 - enable weighted round robin arbitration"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_ram_wrr_high( + &mut self, + ) -> HP_REG_TCM_RAM_WRR_HIGH_W { + HP_REG_TCM_RAM_WRR_HIGH_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_ram_wrr_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_ram_wrr_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_RAM_WRR_CONFIG_SPEC; +impl crate::RegisterSpec for HP_TCM_RAM_WRR_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_ram_wrr_config::R`](R) reader structure"] +impl crate::Readable for HP_TCM_RAM_WRR_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_ram_wrr_config::W`](W) writer structure"] +impl crate::Writable for HP_TCM_RAM_WRR_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_RAM_WRR_CONFIG to value 0x826e_d93f"] +impl crate::Resettable for HP_TCM_RAM_WRR_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0x826e_d93f; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_rdn_eco_cs.rs b/esp32p4/src/hp_sys/hp_tcm_rdn_eco_cs.rs new file mode 100644 index 0000000000..f4d4a1c1df --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_rdn_eco_cs.rs @@ -0,0 +1,79 @@ +#[doc = "Register `HP_TCM_RDN_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `HP_TCM_RDN_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_HP_TCM_RDN_ECO_EN` reader - NA"] +pub type HP_REG_HP_TCM_RDN_ECO_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_HP_TCM_RDN_ECO_EN` writer - NA"] +pub type HP_REG_HP_TCM_RDN_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_HP_TCM_RDN_ECO_RESULT` reader - NA"] +pub type HP_REG_HP_TCM_RDN_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_hp_tcm_rdn_eco_en(&self) -> HP_REG_HP_TCM_RDN_ECO_EN_R { + HP_REG_HP_TCM_RDN_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn hp_reg_hp_tcm_rdn_eco_result(&self) -> HP_REG_HP_TCM_RDN_ECO_RESULT_R { + HP_REG_HP_TCM_RDN_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_RDN_ECO_CS") + .field( + "hp_reg_hp_tcm_rdn_eco_en", + &format_args!("{}", self.hp_reg_hp_tcm_rdn_eco_en().bit()), + ) + .field( + "hp_reg_hp_tcm_rdn_eco_result", + &format_args!("{}", self.hp_reg_hp_tcm_rdn_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_hp_tcm_rdn_eco_en( + &mut self, + ) -> HP_REG_HP_TCM_RDN_ECO_EN_W { + HP_REG_HP_TCM_RDN_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_rdn_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_rdn_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_RDN_ECO_CS_SPEC; +impl crate::RegisterSpec for HP_TCM_RDN_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_rdn_eco_cs::R`](R) reader structure"] +impl crate::Readable for HP_TCM_RDN_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_rdn_eco_cs::W`](W) writer structure"] +impl crate::Writable for HP_TCM_RDN_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_RDN_ECO_CS to value 0"] +impl crate::Resettable for HP_TCM_RDN_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_rdn_eco_high.rs b/esp32p4/src/hp_sys/hp_tcm_rdn_eco_high.rs new file mode 100644 index 0000000000..d422ed002d --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_rdn_eco_high.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_TCM_RDN_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `HP_TCM_RDN_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_HP_TCM_RDN_ECO_HIGH` reader - NA"] +pub type HP_REG_HP_TCM_RDN_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `HP_REG_HP_TCM_RDN_ECO_HIGH` writer - NA"] +pub type HP_REG_HP_TCM_RDN_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn hp_reg_hp_tcm_rdn_eco_high(&self) -> HP_REG_HP_TCM_RDN_ECO_HIGH_R { + HP_REG_HP_TCM_RDN_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_RDN_ECO_HIGH") + .field( + "hp_reg_hp_tcm_rdn_eco_high", + &format_args!("{}", self.hp_reg_hp_tcm_rdn_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_hp_tcm_rdn_eco_high( + &mut self, + ) -> HP_REG_HP_TCM_RDN_ECO_HIGH_W { + HP_REG_HP_TCM_RDN_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_rdn_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_rdn_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_RDN_ECO_HIGH_SPEC; +impl crate::RegisterSpec for HP_TCM_RDN_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_rdn_eco_high::R`](R) reader structure"] +impl crate::Readable for HP_TCM_RDN_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_rdn_eco_high::W`](W) writer structure"] +impl crate::Writable for HP_TCM_RDN_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_RDN_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for HP_TCM_RDN_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_rdn_eco_low.rs b/esp32p4/src/hp_sys/hp_tcm_rdn_eco_low.rs new file mode 100644 index 0000000000..f8435f7bde --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_rdn_eco_low.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_TCM_RDN_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `HP_TCM_RDN_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_HP_TCM_RDN_ECO_LOW` reader - NA"] +pub type HP_REG_HP_TCM_RDN_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `HP_REG_HP_TCM_RDN_ECO_LOW` writer - NA"] +pub type HP_REG_HP_TCM_RDN_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn hp_reg_hp_tcm_rdn_eco_low(&self) -> HP_REG_HP_TCM_RDN_ECO_LOW_R { + HP_REG_HP_TCM_RDN_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_RDN_ECO_LOW") + .field( + "hp_reg_hp_tcm_rdn_eco_low", + &format_args!("{}", self.hp_reg_hp_tcm_rdn_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_hp_tcm_rdn_eco_low( + &mut self, + ) -> HP_REG_HP_TCM_RDN_ECO_LOW_W { + HP_REG_HP_TCM_RDN_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_rdn_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_rdn_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_RDN_ECO_LOW_SPEC; +impl crate::RegisterSpec for HP_TCM_RDN_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_rdn_eco_low::R`](R) reader structure"] +impl crate::Readable for HP_TCM_RDN_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_rdn_eco_low::W`](W) writer structure"] +impl crate::Writable for HP_TCM_RDN_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_RDN_ECO_LOW to value 0"] +impl crate::Resettable for HP_TCM_RDN_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_tcm_sw_parity_bwe_mask.rs b/esp32p4/src/hp_sys/hp_tcm_sw_parity_bwe_mask.rs new file mode 100644 index 0000000000..d1512e3772 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_tcm_sw_parity_bwe_mask.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_TCM_SW_PARITY_BWE_MASK` reader"] +pub type R = crate::R; +#[doc = "Register `HP_TCM_SW_PARITY_BWE_MASK` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL` reader - Set 1 to mask tcm bwe parity code bit"] +pub type HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL_R = crate::BitReader; +#[doc = "Field `HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL` writer - Set 1 to mask tcm bwe parity code bit"] +pub type HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 to mask tcm bwe parity code bit"] + #[inline(always)] + pub fn hp_reg_tcm_sw_parity_bwe_mask_ctrl(&self) -> HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL_R { + HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_TCM_SW_PARITY_BWE_MASK") + .field( + "hp_reg_tcm_sw_parity_bwe_mask_ctrl", + &format_args!("{}", self.hp_reg_tcm_sw_parity_bwe_mask_ctrl().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 to mask tcm bwe parity code bit"] + #[inline(always)] + #[must_use] + pub fn hp_reg_tcm_sw_parity_bwe_mask_ctrl( + &mut self, + ) -> HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL_W { + HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_tcm_sw_parity_bwe_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_tcm_sw_parity_bwe_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_TCM_SW_PARITY_BWE_MASK_SPEC; +impl crate::RegisterSpec for HP_TCM_SW_PARITY_BWE_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_tcm_sw_parity_bwe_mask::R`](R) reader structure"] +impl crate::Readable for HP_TCM_SW_PARITY_BWE_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_tcm_sw_parity_bwe_mask::W`](W) writer structure"] +impl crate::Writable for HP_TCM_SW_PARITY_BWE_MASK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_TCM_SW_PARITY_BWE_MASK to value 0"] +impl crate::Resettable for HP_TCM_SW_PARITY_BWE_MASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/hp_uart_pd_ctrl.rs b/esp32p4/src/hp_sys/hp_uart_pd_ctrl.rs new file mode 100644 index 0000000000..4a3b736a06 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_uart_pd_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `HP_UART_PD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_UART_PD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_UART_MEM_FORCE_PD` reader - Set this bit to power down hp uart internal memory."] +pub type HP_UART_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `HP_UART_MEM_FORCE_PD` writer - Set this bit to power down hp uart internal memory."] +pub type HP_UART_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_UART_MEM_FORCE_PU` reader - Set this bit to force power up hp uart internal memory"] +pub type HP_UART_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `HP_UART_MEM_FORCE_PU` writer - Set this bit to force power up hp uart internal memory"] +pub type HP_UART_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to power down hp uart internal memory."] + #[inline(always)] + pub fn hp_uart_mem_force_pd(&self) -> HP_UART_MEM_FORCE_PD_R { + HP_UART_MEM_FORCE_PD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to force power up hp uart internal memory"] + #[inline(always)] + pub fn hp_uart_mem_force_pu(&self) -> HP_UART_MEM_FORCE_PU_R { + HP_UART_MEM_FORCE_PU_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_UART_PD_CTRL") + .field( + "hp_uart_mem_force_pd", + &format_args!("{}", self.hp_uart_mem_force_pd().bit()), + ) + .field( + "hp_uart_mem_force_pu", + &format_args!("{}", self.hp_uart_mem_force_pu().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to power down hp uart internal memory."] + #[inline(always)] + #[must_use] + pub fn hp_uart_mem_force_pd(&mut self) -> HP_UART_MEM_FORCE_PD_W { + HP_UART_MEM_FORCE_PD_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to force power up hp uart internal memory"] + #[inline(always)] + #[must_use] + pub fn hp_uart_mem_force_pu(&mut self) -> HP_UART_MEM_FORCE_PU_W { + HP_UART_MEM_FORCE_PU_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ecc pd ctrl register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_uart_pd_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_uart_pd_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_UART_PD_CTRL_SPEC; +impl crate::RegisterSpec for HP_UART_PD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_uart_pd_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_UART_PD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_uart_pd_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_UART_PD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_UART_PD_CTRL to value 0x02"] +impl crate::Resettable for HP_UART_PD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/hp_sys/hp_usb20otg_mem_ctrl.rs b/esp32p4/src/hp_sys/hp_usb20otg_mem_ctrl.rs new file mode 100644 index 0000000000..db644b2027 --- /dev/null +++ b/esp32p4/src/hp_sys/hp_usb20otg_mem_ctrl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_USB20OTG_MEM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_USB20OTG_MEM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_USB20_MEM_CLK_FORCE_ON` reader - NA"] +pub type HP_REG_USB20_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `HP_REG_USB20_MEM_CLK_FORCE_ON` writer - NA"] +pub type HP_REG_USB20_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_usb20_mem_clk_force_on(&self) -> HP_REG_USB20_MEM_CLK_FORCE_ON_R { + HP_REG_USB20_MEM_CLK_FORCE_ON_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_USB20OTG_MEM_CTRL") + .field( + "hp_reg_usb20_mem_clk_force_on", + &format_args!("{}", self.hp_reg_usb20_mem_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_usb20_mem_clk_force_on( + &mut self, + ) -> HP_REG_USB20_MEM_CLK_FORCE_ON_W { + HP_REG_USB20_MEM_CLK_FORCE_ON_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_usb20otg_mem_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_usb20otg_mem_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_USB20OTG_MEM_CTRL_SPEC; +impl crate::RegisterSpec for HP_USB20OTG_MEM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_usb20otg_mem_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_USB20OTG_MEM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_usb20otg_mem_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_USB20OTG_MEM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_USB20OTG_MEM_CTRL to value 0"] +impl crate::Resettable for HP_USB20OTG_MEM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/rdn_eco_cs.rs b/esp32p4/src/hp_sys/rdn_eco_cs.rs new file mode 100644 index 0000000000..0edc17bcb3 --- /dev/null +++ b/esp32p4/src/hp_sys/rdn_eco_cs.rs @@ -0,0 +1,77 @@ +#[doc = "Register `RDN_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_HP_SYS_RDN_ECO_EN` reader - NA"] +pub type HP_REG_HP_SYS_RDN_ECO_EN_R = crate::BitReader; +#[doc = "Field `HP_REG_HP_SYS_RDN_ECO_EN` writer - NA"] +pub type HP_REG_HP_SYS_RDN_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_REG_HP_SYS_RDN_ECO_RESULT` reader - NA"] +pub type HP_REG_HP_SYS_RDN_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hp_reg_hp_sys_rdn_eco_en(&self) -> HP_REG_HP_SYS_RDN_ECO_EN_R { + HP_REG_HP_SYS_RDN_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn hp_reg_hp_sys_rdn_eco_result(&self) -> HP_REG_HP_SYS_RDN_ECO_RESULT_R { + HP_REG_HP_SYS_RDN_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_CS") + .field( + "hp_reg_hp_sys_rdn_eco_en", + &format_args!("{}", self.hp_reg_hp_sys_rdn_eco_en().bit()), + ) + .field( + "hp_reg_hp_sys_rdn_eco_result", + &format_args!("{}", self.hp_reg_hp_sys_rdn_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_hp_sys_rdn_eco_en(&mut self) -> HP_REG_HP_SYS_RDN_ECO_EN_W { + HP_REG_HP_SYS_RDN_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_CS_SPEC; +impl crate::RegisterSpec for RDN_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_cs::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_cs::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_CS to value 0"] +impl crate::Resettable for RDN_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys/usbotg20_ctrl.rs b/esp32p4/src/hp_sys/usbotg20_ctrl.rs new file mode 100644 index 0000000000..e730a9e6f5 --- /dev/null +++ b/esp32p4/src/hp_sys/usbotg20_ctrl.rs @@ -0,0 +1,261 @@ +#[doc = "Register `USBOTG20_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `USBOTG20_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `OTG_PHY_TEST_DONE` reader - N/A"] +pub type OTG_PHY_TEST_DONE_R = crate::BitReader; +#[doc = "Field `USB_MEM_AUX_CTRL` reader - N/A"] +pub type USB_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `USB_MEM_AUX_CTRL` writer - N/A"] +pub type USB_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `PHY_SUSPENDM` reader - N/A"] +pub type PHY_SUSPENDM_R = crate::BitReader; +#[doc = "Field `PHY_SUSPENDM` writer - N/A"] +pub type PHY_SUSPENDM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_SUSPEND_FORCE_EN` reader - N/A"] +pub type PHY_SUSPEND_FORCE_EN_R = crate::BitReader; +#[doc = "Field `PHY_SUSPEND_FORCE_EN` writer - N/A"] +pub type PHY_SUSPEND_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_RSTN` reader - N/A"] +pub type PHY_RSTN_R = crate::BitReader; +#[doc = "Field `PHY_RSTN` writer - N/A"] +pub type PHY_RSTN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_RESET_FORCE_EN` reader - N/A"] +pub type PHY_RESET_FORCE_EN_R = crate::BitReader; +#[doc = "Field `PHY_RESET_FORCE_EN` writer - N/A"] +pub type PHY_RESET_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_PLL_FORCE_EN` reader - N/A"] +pub type PHY_PLL_FORCE_EN_R = crate::BitReader; +#[doc = "Field `PHY_PLL_FORCE_EN` writer - N/A"] +pub type PHY_PLL_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_PLL_EN` reader - N/A"] +pub type PHY_PLL_EN_R = crate::BitReader; +#[doc = "Field `PHY_PLL_EN` writer - N/A"] +pub type PHY_PLL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OTG_SUSPENDM` reader - N/A"] +pub type OTG_SUSPENDM_R = crate::BitReader; +#[doc = "Field `OTG_SUSPENDM` writer - N/A"] +pub type OTG_SUSPENDM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OTG_PHY_TXBITSTUFF_EN` reader - N/A"] +pub type OTG_PHY_TXBITSTUFF_EN_R = crate::BitReader; +#[doc = "Field `OTG_PHY_TXBITSTUFF_EN` writer - N/A"] +pub type OTG_PHY_TXBITSTUFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OTG_PHY_REFCLK_MODE` reader - N/A"] +pub type OTG_PHY_REFCLK_MODE_R = crate::BitReader; +#[doc = "Field `OTG_PHY_REFCLK_MODE` writer - N/A"] +pub type OTG_PHY_REFCLK_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OTG_PHY_BISTEN` reader - N/A"] +pub type OTG_PHY_BISTEN_R = crate::BitReader; +#[doc = "Field `OTG_PHY_BISTEN` writer - N/A"] +pub type OTG_PHY_BISTEN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + pub fn otg_phy_test_done(&self) -> OTG_PHY_TEST_DONE_R { + OTG_PHY_TEST_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:14 - N/A"] + #[inline(always)] + pub fn usb_mem_aux_ctrl(&self) -> USB_MEM_AUX_CTRL_R { + USB_MEM_AUX_CTRL_R::new(((self.bits >> 1) & 0x3fff) as u16) + } + #[doc = "Bit 15 - N/A"] + #[inline(always)] + pub fn phy_suspendm(&self) -> PHY_SUSPENDM_R { + PHY_SUSPENDM_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - N/A"] + #[inline(always)] + pub fn phy_suspend_force_en(&self) -> PHY_SUSPEND_FORCE_EN_R { + PHY_SUSPEND_FORCE_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - N/A"] + #[inline(always)] + pub fn phy_rstn(&self) -> PHY_RSTN_R { + PHY_RSTN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - N/A"] + #[inline(always)] + pub fn phy_reset_force_en(&self) -> PHY_RESET_FORCE_EN_R { + PHY_RESET_FORCE_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - N/A"] + #[inline(always)] + pub fn phy_pll_force_en(&self) -> PHY_PLL_FORCE_EN_R { + PHY_PLL_FORCE_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - N/A"] + #[inline(always)] + pub fn phy_pll_en(&self) -> PHY_PLL_EN_R { + PHY_PLL_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - N/A"] + #[inline(always)] + pub fn otg_suspendm(&self) -> OTG_SUSPENDM_R { + OTG_SUSPENDM_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - N/A"] + #[inline(always)] + pub fn otg_phy_txbitstuff_en(&self) -> OTG_PHY_TXBITSTUFF_EN_R { + OTG_PHY_TXBITSTUFF_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - N/A"] + #[inline(always)] + pub fn otg_phy_refclk_mode(&self) -> OTG_PHY_REFCLK_MODE_R { + OTG_PHY_REFCLK_MODE_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - N/A"] + #[inline(always)] + pub fn otg_phy_bisten(&self) -> OTG_PHY_BISTEN_R { + OTG_PHY_BISTEN_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USBOTG20_CTRL") + .field( + "otg_phy_test_done", + &format_args!("{}", self.otg_phy_test_done().bit()), + ) + .field( + "usb_mem_aux_ctrl", + &format_args!("{}", self.usb_mem_aux_ctrl().bits()), + ) + .field( + "phy_suspendm", + &format_args!("{}", self.phy_suspendm().bit()), + ) + .field( + "phy_suspend_force_en", + &format_args!("{}", self.phy_suspend_force_en().bit()), + ) + .field("phy_rstn", &format_args!("{}", self.phy_rstn().bit())) + .field( + "phy_reset_force_en", + &format_args!("{}", self.phy_reset_force_en().bit()), + ) + .field( + "phy_pll_force_en", + &format_args!("{}", self.phy_pll_force_en().bit()), + ) + .field("phy_pll_en", &format_args!("{}", self.phy_pll_en().bit())) + .field( + "otg_suspendm", + &format_args!("{}", self.otg_suspendm().bit()), + ) + .field( + "otg_phy_txbitstuff_en", + &format_args!("{}", self.otg_phy_txbitstuff_en().bit()), + ) + .field( + "otg_phy_refclk_mode", + &format_args!("{}", self.otg_phy_refclk_mode().bit()), + ) + .field( + "otg_phy_bisten", + &format_args!("{}", self.otg_phy_bisten().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 1:14 - N/A"] + #[inline(always)] + #[must_use] + pub fn usb_mem_aux_ctrl(&mut self) -> USB_MEM_AUX_CTRL_W { + USB_MEM_AUX_CTRL_W::new(self, 1) + } + #[doc = "Bit 15 - N/A"] + #[inline(always)] + #[must_use] + pub fn phy_suspendm(&mut self) -> PHY_SUSPENDM_W { + PHY_SUSPENDM_W::new(self, 15) + } + #[doc = "Bit 16 - N/A"] + #[inline(always)] + #[must_use] + pub fn phy_suspend_force_en(&mut self) -> PHY_SUSPEND_FORCE_EN_W { + PHY_SUSPEND_FORCE_EN_W::new(self, 16) + } + #[doc = "Bit 17 - N/A"] + #[inline(always)] + #[must_use] + pub fn phy_rstn(&mut self) -> PHY_RSTN_W { + PHY_RSTN_W::new(self, 17) + } + #[doc = "Bit 18 - N/A"] + #[inline(always)] + #[must_use] + pub fn phy_reset_force_en(&mut self) -> PHY_RESET_FORCE_EN_W { + PHY_RESET_FORCE_EN_W::new(self, 18) + } + #[doc = "Bit 19 - N/A"] + #[inline(always)] + #[must_use] + pub fn phy_pll_force_en(&mut self) -> PHY_PLL_FORCE_EN_W { + PHY_PLL_FORCE_EN_W::new(self, 19) + } + #[doc = "Bit 20 - N/A"] + #[inline(always)] + #[must_use] + pub fn phy_pll_en(&mut self) -> PHY_PLL_EN_W { + PHY_PLL_EN_W::new(self, 20) + } + #[doc = "Bit 21 - N/A"] + #[inline(always)] + #[must_use] + pub fn otg_suspendm(&mut self) -> OTG_SUSPENDM_W { + OTG_SUSPENDM_W::new(self, 21) + } + #[doc = "Bit 22 - N/A"] + #[inline(always)] + #[must_use] + pub fn otg_phy_txbitstuff_en(&mut self) -> OTG_PHY_TXBITSTUFF_EN_W { + OTG_PHY_TXBITSTUFF_EN_W::new(self, 22) + } + #[doc = "Bit 23 - N/A"] + #[inline(always)] + #[must_use] + pub fn otg_phy_refclk_mode(&mut self) -> OTG_PHY_REFCLK_MODE_W { + OTG_PHY_REFCLK_MODE_W::new(self, 23) + } + #[doc = "Bit 24 - N/A"] + #[inline(always)] + #[must_use] + pub fn otg_phy_bisten(&mut self) -> OTG_PHY_BISTEN_W { + OTG_PHY_BISTEN_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbotg20_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbotg20_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USBOTG20_CTRL_SPEC; +impl crate::RegisterSpec for USBOTG20_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usbotg20_ctrl::R`](R) reader structure"] +impl crate::Readable for USBOTG20_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbotg20_ctrl::W`](W) writer structure"] +impl crate::Writable for USBOTG20_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USBOTG20_CTRL to value 0x0082_2640"] +impl crate::Resettable for USBOTG20_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0082_2640; +} diff --git a/esp32p4/src/hp_sys/ver_date.rs b/esp32p4/src/hp_sys/ver_date.rs new file mode 100644 index 0000000000..a32b9e4be7 --- /dev/null +++ b/esp32p4/src/hp_sys/ver_date.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VER_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `VER_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `HP_REG_VER_DATE` reader - NA"] +pub type HP_REG_VER_DATE_R = crate::FieldReader; +#[doc = "Field `HP_REG_VER_DATE` writer - NA"] +pub type HP_REG_VER_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn hp_reg_ver_date(&self) -> HP_REG_VER_DATE_R { + HP_REG_VER_DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VER_DATE") + .field( + "hp_reg_ver_date", + &format_args!("{}", self.hp_reg_ver_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn hp_reg_ver_date(&mut self) -> HP_REG_VER_DATE_W { + HP_REG_VER_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VER_DATE_SPEC; +impl crate::RegisterSpec for VER_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ver_date::R`](R) reader structure"] +impl crate::Readable for VER_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ver_date::W`](W) writer structure"] +impl crate::Writable for VER_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VER_DATE to value 0x2023_0519"] +impl crate::Resettable for VER_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2023_0519; +} diff --git a/esp32p4/src/hp_sys/vpu_ctrl.rs b/esp32p4/src/hp_sys/vpu_ctrl.rs new file mode 100644 index 0000000000..87084d1ad9 --- /dev/null +++ b/esp32p4/src/hp_sys/vpu_ctrl.rs @@ -0,0 +1,142 @@ +#[doc = "Register `VPU_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `VPU_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `PPA_LSLP_MEM_PD` reader - N/A"] +pub type PPA_LSLP_MEM_PD_R = crate::BitReader; +#[doc = "Field `PPA_LSLP_MEM_PD` writer - N/A"] +pub type PPA_LSLP_MEM_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JPEG_SDSLP_MEM_PD` reader - N/A"] +pub type JPEG_SDSLP_MEM_PD_R = crate::BitReader; +#[doc = "Field `JPEG_SDSLP_MEM_PD` writer - N/A"] +pub type JPEG_SDSLP_MEM_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JPEG_LSLP_MEM_PD` reader - N/A"] +pub type JPEG_LSLP_MEM_PD_R = crate::BitReader; +#[doc = "Field `JPEG_LSLP_MEM_PD` writer - N/A"] +pub type JPEG_LSLP_MEM_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JPEG_DSLP_MEM_PD` reader - N/A"] +pub type JPEG_DSLP_MEM_PD_R = crate::BitReader; +#[doc = "Field `JPEG_DSLP_MEM_PD` writer - N/A"] +pub type JPEG_DSLP_MEM_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_LSLP_MEM_PD` reader - N/A"] +pub type DMA2D_LSLP_MEM_PD_R = crate::BitReader; +#[doc = "Field `DMA2D_LSLP_MEM_PD` writer - N/A"] +pub type DMA2D_LSLP_MEM_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + pub fn ppa_lslp_mem_pd(&self) -> PPA_LSLP_MEM_PD_R { + PPA_LSLP_MEM_PD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + pub fn jpeg_sdslp_mem_pd(&self) -> JPEG_SDSLP_MEM_PD_R { + JPEG_SDSLP_MEM_PD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - N/A"] + #[inline(always)] + pub fn jpeg_lslp_mem_pd(&self) -> JPEG_LSLP_MEM_PD_R { + JPEG_LSLP_MEM_PD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - N/A"] + #[inline(always)] + pub fn jpeg_dslp_mem_pd(&self) -> JPEG_DSLP_MEM_PD_R { + JPEG_DSLP_MEM_PD_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - N/A"] + #[inline(always)] + pub fn dma2d_lslp_mem_pd(&self) -> DMA2D_LSLP_MEM_PD_R { + DMA2D_LSLP_MEM_PD_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VPU_CTRL") + .field( + "ppa_lslp_mem_pd", + &format_args!("{}", self.ppa_lslp_mem_pd().bit()), + ) + .field( + "jpeg_sdslp_mem_pd", + &format_args!("{}", self.jpeg_sdslp_mem_pd().bit()), + ) + .field( + "jpeg_lslp_mem_pd", + &format_args!("{}", self.jpeg_lslp_mem_pd().bit()), + ) + .field( + "jpeg_dslp_mem_pd", + &format_args!("{}", self.jpeg_dslp_mem_pd().bit()), + ) + .field( + "dma2d_lslp_mem_pd", + &format_args!("{}", self.dma2d_lslp_mem_pd().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + #[must_use] + pub fn ppa_lslp_mem_pd(&mut self) -> PPA_LSLP_MEM_PD_W { + PPA_LSLP_MEM_PD_W::new(self, 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + #[must_use] + pub fn jpeg_sdslp_mem_pd(&mut self) -> JPEG_SDSLP_MEM_PD_W { + JPEG_SDSLP_MEM_PD_W::new(self, 1) + } + #[doc = "Bit 2 - N/A"] + #[inline(always)] + #[must_use] + pub fn jpeg_lslp_mem_pd(&mut self) -> JPEG_LSLP_MEM_PD_W { + JPEG_LSLP_MEM_PD_W::new(self, 2) + } + #[doc = "Bit 3 - N/A"] + #[inline(always)] + #[must_use] + pub fn jpeg_dslp_mem_pd(&mut self) -> JPEG_DSLP_MEM_PD_W { + JPEG_DSLP_MEM_PD_W::new(self, 3) + } + #[doc = "Bit 4 - N/A"] + #[inline(always)] + #[must_use] + pub fn dma2d_lslp_mem_pd(&mut self) -> DMA2D_LSLP_MEM_PD_W { + DMA2D_LSLP_MEM_PD_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vpu_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vpu_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VPU_CTRL_SPEC; +impl crate::RegisterSpec for VPU_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vpu_ctrl::R`](R) reader structure"] +impl crate::Readable for VPU_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vpu_ctrl::W`](W) writer structure"] +impl crate::Writable for VPU_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VPU_CTRL to value 0"] +impl crate::Resettable for VPU_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst.rs b/esp32p4/src/hp_sys_clkrst.rs new file mode 100644 index 0000000000..38d5a5808f --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst.rs @@ -0,0 +1,608 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + clk_en0: CLK_EN0, + root_clk_ctrl0: ROOT_CLK_CTRL0, + root_clk_ctrl1: ROOT_CLK_CTRL1, + root_clk_ctrl2: ROOT_CLK_CTRL2, + root_clk_ctrl3: ROOT_CLK_CTRL3, + soc_clk_ctrl0: SOC_CLK_CTRL0, + soc_clk_ctrl1: SOC_CLK_CTRL1, + soc_clk_ctrl2: SOC_CLK_CTRL2, + soc_clk_ctrl3: SOC_CLK_CTRL3, + ref_clk_ctrl0: REF_CLK_CTRL0, + ref_clk_ctrl1: REF_CLK_CTRL1, + ref_clk_ctrl2: REF_CLK_CTRL2, + peri_clk_ctrl00: PERI_CLK_CTRL00, + peri_clk_ctrl01: PERI_CLK_CTRL01, + peri_clk_ctrl02: PERI_CLK_CTRL02, + peri_clk_ctrl03: PERI_CLK_CTRL03, + peri_clk_ctrl10: PERI_CLK_CTRL10, + peri_clk_ctrl11: PERI_CLK_CTRL11, + peri_clk_ctrl12: PERI_CLK_CTRL12, + peri_clk_ctrl13: PERI_CLK_CTRL13, + peri_clk_ctrl14: PERI_CLK_CTRL14, + peri_clk_ctrl15: PERI_CLK_CTRL15, + peri_clk_ctrl16: PERI_CLK_CTRL16, + peri_clk_ctrl17: PERI_CLK_CTRL17, + peri_clk_ctrl18: PERI_CLK_CTRL18, + peri_clk_ctrl19: PERI_CLK_CTRL19, + peri_clk_ctrl110: PERI_CLK_CTRL110, + peri_clk_ctrl111: PERI_CLK_CTRL111, + peri_clk_ctrl112: PERI_CLK_CTRL112, + peri_clk_ctrl113: PERI_CLK_CTRL113, + peri_clk_ctrl114: PERI_CLK_CTRL114, + peri_clk_ctrl115: PERI_CLK_CTRL115, + peri_clk_ctrl116: PERI_CLK_CTRL116, + peri_clk_ctrl117: PERI_CLK_CTRL117, + peri_clk_ctrl118: PERI_CLK_CTRL118, + peri_clk_ctrl119: PERI_CLK_CTRL119, + peri_clk_ctrl120: PERI_CLK_CTRL120, + peri_clk_ctrl20: PERI_CLK_CTRL20, + peri_clk_ctrl21: PERI_CLK_CTRL21, + peri_clk_ctrl22: PERI_CLK_CTRL22, + peri_clk_ctrl23: PERI_CLK_CTRL23, + peri_clk_ctrl24: PERI_CLK_CTRL24, + peri_clk_ctrl25: PERI_CLK_CTRL25, + peri_clk_ctrl26: PERI_CLK_CTRL26, + peri_clk_ctrl27: PERI_CLK_CTRL27, + clk_force_on_ctrl0: CLK_FORCE_ON_CTRL0, + dpa_ctrl0: DPA_CTRL0, + ana_pll_ctrl0: ANA_PLL_CTRL0, + hp_rst_en0: HP_RST_EN0, + hp_rst_en1: HP_RST_EN1, + hp_rst_en2: HP_RST_EN2, + hp_force_norst0: HP_FORCE_NORST0, + hp_force_norst1: HP_FORCE_NORST1, + hpwdt_core0_rst_ctrl0: HPWDT_CORE0_RST_CTRL0, + hpwdt_core1_rst_ctrl0: HPWDT_CORE1_RST_CTRL0, + cpu_src_freq0: CPU_SRC_FREQ0, + cpu_clk_status0: CPU_CLK_STATUS0, + dbg_clk_ctrl0: DBG_CLK_CTRL0, + dbg_clk_ctrl1: DBG_CLK_CTRL1, + hpcore_wdt_reset_source0: HPCORE_WDT_RESET_SOURCE0, +} +impl RegisterBlock { + #[doc = "0x00 - Reserved"] + #[inline(always)] + pub const fn clk_en0(&self) -> &CLK_EN0 { + &self.clk_en0 + } + #[doc = "0x04 - Reserved"] + #[inline(always)] + pub const fn root_clk_ctrl0(&self) -> &ROOT_CLK_CTRL0 { + &self.root_clk_ctrl0 + } + #[doc = "0x08 - Reserved"] + #[inline(always)] + pub const fn root_clk_ctrl1(&self) -> &ROOT_CLK_CTRL1 { + &self.root_clk_ctrl1 + } + #[doc = "0x0c - Reserved"] + #[inline(always)] + pub const fn root_clk_ctrl2(&self) -> &ROOT_CLK_CTRL2 { + &self.root_clk_ctrl2 + } + #[doc = "0x10 - Reserved"] + #[inline(always)] + pub const fn root_clk_ctrl3(&self) -> &ROOT_CLK_CTRL3 { + &self.root_clk_ctrl3 + } + #[doc = "0x14 - Reserved"] + #[inline(always)] + pub const fn soc_clk_ctrl0(&self) -> &SOC_CLK_CTRL0 { + &self.soc_clk_ctrl0 + } + #[doc = "0x18 - Reserved"] + #[inline(always)] + pub const fn soc_clk_ctrl1(&self) -> &SOC_CLK_CTRL1 { + &self.soc_clk_ctrl1 + } + #[doc = "0x1c - Reserved"] + #[inline(always)] + pub const fn soc_clk_ctrl2(&self) -> &SOC_CLK_CTRL2 { + &self.soc_clk_ctrl2 + } + #[doc = "0x20 - Reserved"] + #[inline(always)] + pub const fn soc_clk_ctrl3(&self) -> &SOC_CLK_CTRL3 { + &self.soc_clk_ctrl3 + } + #[doc = "0x24 - Reserved"] + #[inline(always)] + pub const fn ref_clk_ctrl0(&self) -> &REF_CLK_CTRL0 { + &self.ref_clk_ctrl0 + } + #[doc = "0x28 - Reserved"] + #[inline(always)] + pub const fn ref_clk_ctrl1(&self) -> &REF_CLK_CTRL1 { + &self.ref_clk_ctrl1 + } + #[doc = "0x2c - Reserved"] + #[inline(always)] + pub const fn ref_clk_ctrl2(&self) -> &REF_CLK_CTRL2 { + &self.ref_clk_ctrl2 + } + #[doc = "0x30 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl00(&self) -> &PERI_CLK_CTRL00 { + &self.peri_clk_ctrl00 + } + #[doc = "0x34 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl01(&self) -> &PERI_CLK_CTRL01 { + &self.peri_clk_ctrl01 + } + #[doc = "0x38 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl02(&self) -> &PERI_CLK_CTRL02 { + &self.peri_clk_ctrl02 + } + #[doc = "0x3c - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl03(&self) -> &PERI_CLK_CTRL03 { + &self.peri_clk_ctrl03 + } + #[doc = "0x40 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl10(&self) -> &PERI_CLK_CTRL10 { + &self.peri_clk_ctrl10 + } + #[doc = "0x44 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl11(&self) -> &PERI_CLK_CTRL11 { + &self.peri_clk_ctrl11 + } + #[doc = "0x48 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl12(&self) -> &PERI_CLK_CTRL12 { + &self.peri_clk_ctrl12 + } + #[doc = "0x4c - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl13(&self) -> &PERI_CLK_CTRL13 { + &self.peri_clk_ctrl13 + } + #[doc = "0x50 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl14(&self) -> &PERI_CLK_CTRL14 { + &self.peri_clk_ctrl14 + } + #[doc = "0x54 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl15(&self) -> &PERI_CLK_CTRL15 { + &self.peri_clk_ctrl15 + } + #[doc = "0x58 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl16(&self) -> &PERI_CLK_CTRL16 { + &self.peri_clk_ctrl16 + } + #[doc = "0x5c - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl17(&self) -> &PERI_CLK_CTRL17 { + &self.peri_clk_ctrl17 + } + #[doc = "0x60 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl18(&self) -> &PERI_CLK_CTRL18 { + &self.peri_clk_ctrl18 + } + #[doc = "0x64 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl19(&self) -> &PERI_CLK_CTRL19 { + &self.peri_clk_ctrl19 + } + #[doc = "0x68 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl110(&self) -> &PERI_CLK_CTRL110 { + &self.peri_clk_ctrl110 + } + #[doc = "0x6c - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl111(&self) -> &PERI_CLK_CTRL111 { + &self.peri_clk_ctrl111 + } + #[doc = "0x70 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl112(&self) -> &PERI_CLK_CTRL112 { + &self.peri_clk_ctrl112 + } + #[doc = "0x74 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl113(&self) -> &PERI_CLK_CTRL113 { + &self.peri_clk_ctrl113 + } + #[doc = "0x78 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl114(&self) -> &PERI_CLK_CTRL114 { + &self.peri_clk_ctrl114 + } + #[doc = "0x7c - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl115(&self) -> &PERI_CLK_CTRL115 { + &self.peri_clk_ctrl115 + } + #[doc = "0x80 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl116(&self) -> &PERI_CLK_CTRL116 { + &self.peri_clk_ctrl116 + } + #[doc = "0x84 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl117(&self) -> &PERI_CLK_CTRL117 { + &self.peri_clk_ctrl117 + } + #[doc = "0x88 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl118(&self) -> &PERI_CLK_CTRL118 { + &self.peri_clk_ctrl118 + } + #[doc = "0x8c - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl119(&self) -> &PERI_CLK_CTRL119 { + &self.peri_clk_ctrl119 + } + #[doc = "0x90 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl120(&self) -> &PERI_CLK_CTRL120 { + &self.peri_clk_ctrl120 + } + #[doc = "0x94 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl20(&self) -> &PERI_CLK_CTRL20 { + &self.peri_clk_ctrl20 + } + #[doc = "0x98 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl21(&self) -> &PERI_CLK_CTRL21 { + &self.peri_clk_ctrl21 + } + #[doc = "0x9c - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl22(&self) -> &PERI_CLK_CTRL22 { + &self.peri_clk_ctrl22 + } + #[doc = "0xa0 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl23(&self) -> &PERI_CLK_CTRL23 { + &self.peri_clk_ctrl23 + } + #[doc = "0xa4 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl24(&self) -> &PERI_CLK_CTRL24 { + &self.peri_clk_ctrl24 + } + #[doc = "0xa8 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl25(&self) -> &PERI_CLK_CTRL25 { + &self.peri_clk_ctrl25 + } + #[doc = "0xac - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl26(&self) -> &PERI_CLK_CTRL26 { + &self.peri_clk_ctrl26 + } + #[doc = "0xb0 - Reserved"] + #[inline(always)] + pub const fn peri_clk_ctrl27(&self) -> &PERI_CLK_CTRL27 { + &self.peri_clk_ctrl27 + } + #[doc = "0xb4 - Reserved"] + #[inline(always)] + pub const fn clk_force_on_ctrl0(&self) -> &CLK_FORCE_ON_CTRL0 { + &self.clk_force_on_ctrl0 + } + #[doc = "0xb8 - Reserved"] + #[inline(always)] + pub const fn dpa_ctrl0(&self) -> &DPA_CTRL0 { + &self.dpa_ctrl0 + } + #[doc = "0xbc - Reserved"] + #[inline(always)] + pub const fn ana_pll_ctrl0(&self) -> &ANA_PLL_CTRL0 { + &self.ana_pll_ctrl0 + } + #[doc = "0xc0 - Reserved"] + #[inline(always)] + pub const fn hp_rst_en0(&self) -> &HP_RST_EN0 { + &self.hp_rst_en0 + } + #[doc = "0xc4 - Reserved"] + #[inline(always)] + pub const fn hp_rst_en1(&self) -> &HP_RST_EN1 { + &self.hp_rst_en1 + } + #[doc = "0xc8 - Reserved"] + #[inline(always)] + pub const fn hp_rst_en2(&self) -> &HP_RST_EN2 { + &self.hp_rst_en2 + } + #[doc = "0xcc - Reserved"] + #[inline(always)] + pub const fn hp_force_norst0(&self) -> &HP_FORCE_NORST0 { + &self.hp_force_norst0 + } + #[doc = "0xd0 - Reserved"] + #[inline(always)] + pub const fn hp_force_norst1(&self) -> &HP_FORCE_NORST1 { + &self.hp_force_norst1 + } + #[doc = "0xd4 - Reserved"] + #[inline(always)] + pub const fn hpwdt_core0_rst_ctrl0(&self) -> &HPWDT_CORE0_RST_CTRL0 { + &self.hpwdt_core0_rst_ctrl0 + } + #[doc = "0xd8 - Reserved"] + #[inline(always)] + pub const fn hpwdt_core1_rst_ctrl0(&self) -> &HPWDT_CORE1_RST_CTRL0 { + &self.hpwdt_core1_rst_ctrl0 + } + #[doc = "0xdc - CPU Source Frequency"] + #[inline(always)] + pub const fn cpu_src_freq0(&self) -> &CPU_SRC_FREQ0 { + &self.cpu_src_freq0 + } + #[doc = "0xe0 - CPU Clock Status"] + #[inline(always)] + pub const fn cpu_clk_status0(&self) -> &CPU_CLK_STATUS0 { + &self.cpu_clk_status0 + } + #[doc = "0xe4 - Reserved"] + #[inline(always)] + pub const fn dbg_clk_ctrl0(&self) -> &DBG_CLK_CTRL0 { + &self.dbg_clk_ctrl0 + } + #[doc = "0xe8 - Reserved"] + #[inline(always)] + pub const fn dbg_clk_ctrl1(&self) -> &DBG_CLK_CTRL1 { + &self.dbg_clk_ctrl1 + } + #[doc = "0xec - Reserved"] + #[inline(always)] + pub const fn hpcore_wdt_reset_source0(&self) -> &HPCORE_WDT_RESET_SOURCE0 { + &self.hpcore_wdt_reset_source0 + } +} +#[doc = "CLK_EN0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_en0`] module"] +pub type CLK_EN0 = crate::Reg; +#[doc = "Reserved"] +pub mod clk_en0; +#[doc = "ROOT_CLK_CTRL0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`root_clk_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`root_clk_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@root_clk_ctrl0`] module"] +pub type ROOT_CLK_CTRL0 = crate::Reg; +#[doc = "Reserved"] +pub mod root_clk_ctrl0; +#[doc = "ROOT_CLK_CTRL1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`root_clk_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`root_clk_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@root_clk_ctrl1`] module"] +pub type ROOT_CLK_CTRL1 = crate::Reg; +#[doc = "Reserved"] +pub mod root_clk_ctrl1; +#[doc = "ROOT_CLK_CTRL2 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`root_clk_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`root_clk_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@root_clk_ctrl2`] module"] +pub type ROOT_CLK_CTRL2 = crate::Reg; +#[doc = "Reserved"] +pub mod root_clk_ctrl2; +#[doc = "ROOT_CLK_CTRL3 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`root_clk_ctrl3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`root_clk_ctrl3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@root_clk_ctrl3`] module"] +pub type ROOT_CLK_CTRL3 = crate::Reg; +#[doc = "Reserved"] +pub mod root_clk_ctrl3; +#[doc = "SOC_CLK_CTRL0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soc_clk_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soc_clk_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soc_clk_ctrl0`] module"] +pub type SOC_CLK_CTRL0 = crate::Reg; +#[doc = "Reserved"] +pub mod soc_clk_ctrl0; +#[doc = "SOC_CLK_CTRL1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soc_clk_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soc_clk_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soc_clk_ctrl1`] module"] +pub type SOC_CLK_CTRL1 = crate::Reg; +#[doc = "Reserved"] +pub mod soc_clk_ctrl1; +#[doc = "SOC_CLK_CTRL2 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soc_clk_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soc_clk_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soc_clk_ctrl2`] module"] +pub type SOC_CLK_CTRL2 = crate::Reg; +#[doc = "Reserved"] +pub mod soc_clk_ctrl2; +#[doc = "SOC_CLK_CTRL3 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soc_clk_ctrl3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soc_clk_ctrl3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soc_clk_ctrl3`] module"] +pub type SOC_CLK_CTRL3 = crate::Reg; +#[doc = "Reserved"] +pub mod soc_clk_ctrl3; +#[doc = "REF_CLK_CTRL0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_clk_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_clk_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ref_clk_ctrl0`] module"] +pub type REF_CLK_CTRL0 = crate::Reg; +#[doc = "Reserved"] +pub mod ref_clk_ctrl0; +#[doc = "REF_CLK_CTRL1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_clk_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_clk_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ref_clk_ctrl1`] module"] +pub type REF_CLK_CTRL1 = crate::Reg; +#[doc = "Reserved"] +pub mod ref_clk_ctrl1; +#[doc = "REF_CLK_CTRL2 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_clk_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_clk_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ref_clk_ctrl2`] module"] +pub type REF_CLK_CTRL2 = crate::Reg; +#[doc = "Reserved"] +pub mod ref_clk_ctrl2; +#[doc = "PERI_CLK_CTRL00 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl00::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl00::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl00`] module"] +pub type PERI_CLK_CTRL00 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl00; +#[doc = "PERI_CLK_CTRL01 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl01::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl01`] module"] +pub type PERI_CLK_CTRL01 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl01; +#[doc = "PERI_CLK_CTRL02 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl02::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl02::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl02`] module"] +pub type PERI_CLK_CTRL02 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl02; +#[doc = "PERI_CLK_CTRL03 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl03::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl03::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl03`] module"] +pub type PERI_CLK_CTRL03 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl03; +#[doc = "PERI_CLK_CTRL10 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl10`] module"] +pub type PERI_CLK_CTRL10 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl10; +#[doc = "PERI_CLK_CTRL11 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl11`] module"] +pub type PERI_CLK_CTRL11 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl11; +#[doc = "PERI_CLK_CTRL12 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl12`] module"] +pub type PERI_CLK_CTRL12 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl12; +#[doc = "PERI_CLK_CTRL13 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl13`] module"] +pub type PERI_CLK_CTRL13 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl13; +#[doc = "PERI_CLK_CTRL14 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl14`] module"] +pub type PERI_CLK_CTRL14 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl14; +#[doc = "PERI_CLK_CTRL15 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl15`] module"] +pub type PERI_CLK_CTRL15 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl15; +#[doc = "PERI_CLK_CTRL16 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl16`] module"] +pub type PERI_CLK_CTRL16 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl16; +#[doc = "PERI_CLK_CTRL17 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl17::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl17`] module"] +pub type PERI_CLK_CTRL17 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl17; +#[doc = "PERI_CLK_CTRL18 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl18::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl18`] module"] +pub type PERI_CLK_CTRL18 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl18; +#[doc = "PERI_CLK_CTRL19 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl19`] module"] +pub type PERI_CLK_CTRL19 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl19; +#[doc = "PERI_CLK_CTRL110 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl110::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl110::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl110`] module"] +pub type PERI_CLK_CTRL110 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl110; +#[doc = "PERI_CLK_CTRL111 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl111::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl111::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl111`] module"] +pub type PERI_CLK_CTRL111 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl111; +#[doc = "PERI_CLK_CTRL112 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl112::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl112::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl112`] module"] +pub type PERI_CLK_CTRL112 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl112; +#[doc = "PERI_CLK_CTRL113 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl113::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl113::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl113`] module"] +pub type PERI_CLK_CTRL113 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl113; +#[doc = "PERI_CLK_CTRL114 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl114::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl114::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl114`] module"] +pub type PERI_CLK_CTRL114 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl114; +#[doc = "PERI_CLK_CTRL115 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl115::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl115::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl115`] module"] +pub type PERI_CLK_CTRL115 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl115; +#[doc = "PERI_CLK_CTRL116 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl116::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl116::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl116`] module"] +pub type PERI_CLK_CTRL116 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl116; +#[doc = "PERI_CLK_CTRL117 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl117::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl117::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl117`] module"] +pub type PERI_CLK_CTRL117 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl117; +#[doc = "PERI_CLK_CTRL118 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl118::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl118::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl118`] module"] +pub type PERI_CLK_CTRL118 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl118; +#[doc = "PERI_CLK_CTRL119 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl119::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl119::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl119`] module"] +pub type PERI_CLK_CTRL119 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl119; +#[doc = "PERI_CLK_CTRL120 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl120::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl120`] module"] +pub type PERI_CLK_CTRL120 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl120; +#[doc = "PERI_CLK_CTRL20 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl20`] module"] +pub type PERI_CLK_CTRL20 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl20; +#[doc = "PERI_CLK_CTRL21 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl21::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl21`] module"] +pub type PERI_CLK_CTRL21 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl21; +#[doc = "PERI_CLK_CTRL22 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl22::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl22`] module"] +pub type PERI_CLK_CTRL22 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl22; +#[doc = "PERI_CLK_CTRL23 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl23`] module"] +pub type PERI_CLK_CTRL23 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl23; +#[doc = "PERI_CLK_CTRL24 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl24`] module"] +pub type PERI_CLK_CTRL24 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl24; +#[doc = "PERI_CLK_CTRL25 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl25::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl25`] module"] +pub type PERI_CLK_CTRL25 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl25; +#[doc = "PERI_CLK_CTRL26 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl26::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl26`] module"] +pub type PERI_CLK_CTRL26 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl26; +#[doc = "PERI_CLK_CTRL27 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peri_clk_ctrl27`] module"] +pub type PERI_CLK_CTRL27 = crate::Reg; +#[doc = "Reserved"] +pub mod peri_clk_ctrl27; +#[doc = "CLK_FORCE_ON_CTRL0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_force_on_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_force_on_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_force_on_ctrl0`] module"] +pub type CLK_FORCE_ON_CTRL0 = crate::Reg; +#[doc = "Reserved"] +pub mod clk_force_on_ctrl0; +#[doc = "DPA_CTRL0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpa_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpa_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpa_ctrl0`] module"] +pub type DPA_CTRL0 = crate::Reg; +#[doc = "Reserved"] +pub mod dpa_ctrl0; +#[doc = "ANA_PLL_CTRL0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_pll_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_pll_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_pll_ctrl0`] module"] +pub type ANA_PLL_CTRL0 = crate::Reg; +#[doc = "Reserved"] +pub mod ana_pll_ctrl0; +#[doc = "HP_RST_EN0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rst_en0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rst_en0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_rst_en0`] module"] +pub type HP_RST_EN0 = crate::Reg; +#[doc = "Reserved"] +pub mod hp_rst_en0; +#[doc = "HP_RST_EN1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rst_en1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rst_en1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_rst_en1`] module"] +pub type HP_RST_EN1 = crate::Reg; +#[doc = "Reserved"] +pub mod hp_rst_en1; +#[doc = "HP_RST_EN2 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rst_en2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rst_en2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_rst_en2`] module"] +pub type HP_RST_EN2 = crate::Reg; +#[doc = "Reserved"] +pub mod hp_rst_en2; +#[doc = "HP_FORCE_NORST0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_force_norst0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_force_norst0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_force_norst0`] module"] +pub type HP_FORCE_NORST0 = crate::Reg; +#[doc = "Reserved"] +pub mod hp_force_norst0; +#[doc = "HP_FORCE_NORST1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_force_norst1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_force_norst1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_force_norst1`] module"] +pub type HP_FORCE_NORST1 = crate::Reg; +#[doc = "Reserved"] +pub mod hp_force_norst1; +#[doc = "HPWDT_CORE0_RST_CTRL0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpwdt_core0_rst_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hpwdt_core0_rst_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hpwdt_core0_rst_ctrl0`] module"] +pub type HPWDT_CORE0_RST_CTRL0 = crate::Reg; +#[doc = "Reserved"] +pub mod hpwdt_core0_rst_ctrl0; +#[doc = "HPWDT_CORE1_RST_CTRL0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpwdt_core1_rst_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hpwdt_core1_rst_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hpwdt_core1_rst_ctrl0`] module"] +pub type HPWDT_CORE1_RST_CTRL0 = crate::Reg; +#[doc = "Reserved"] +pub mod hpwdt_core1_rst_ctrl0; +#[doc = "CPU_SRC_FREQ0 (r) register accessor: CPU Source Frequency\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_src_freq0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_src_freq0`] module"] +pub type CPU_SRC_FREQ0 = crate::Reg; +#[doc = "CPU Source Frequency"] +pub mod cpu_src_freq0; +#[doc = "CPU_CLK_STATUS0 (r) register accessor: CPU Clock Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_clk_status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_clk_status0`] module"] +pub type CPU_CLK_STATUS0 = crate::Reg; +#[doc = "CPU Clock Status"] +pub mod cpu_clk_status0; +#[doc = "DBG_CLK_CTRL0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_clk_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_clk_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbg_clk_ctrl0`] module"] +pub type DBG_CLK_CTRL0 = crate::Reg; +#[doc = "Reserved"] +pub mod dbg_clk_ctrl0; +#[doc = "DBG_CLK_CTRL1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_clk_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_clk_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbg_clk_ctrl1`] module"] +pub type DBG_CLK_CTRL1 = crate::Reg; +#[doc = "Reserved"] +pub mod dbg_clk_ctrl1; +#[doc = "HPCORE_WDT_RESET_SOURCE0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpcore_wdt_reset_source0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hpcore_wdt_reset_source0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hpcore_wdt_reset_source0`] module"] +pub type HPCORE_WDT_RESET_SOURCE0 = + crate::Reg; +#[doc = "Reserved"] +pub mod hpcore_wdt_reset_source0; diff --git a/esp32p4/src/hp_sys_clkrst/ana_pll_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/ana_pll_ctrl0.rs new file mode 100644 index 0000000000..9135c6c5ee --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/ana_pll_ctrl0.rs @@ -0,0 +1,197 @@ +#[doc = "Register `ANA_PLL_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_PLL_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PLLA_CAL_END` reader - Reserved"] +pub type REG_PLLA_CAL_END_R = crate::BitReader; +#[doc = "Field `REG_PLLA_CAL_STOP` reader - Reserved"] +pub type REG_PLLA_CAL_STOP_R = crate::BitReader; +#[doc = "Field `REG_PLLA_CAL_STOP` writer - Reserved"] +pub type REG_PLLA_CAL_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CPU_PLL_CAL_END` reader - Reserved"] +pub type REG_CPU_PLL_CAL_END_R = crate::BitReader; +#[doc = "Field `REG_CPU_PLL_CAL_STOP` reader - Reserved"] +pub type REG_CPU_PLL_CAL_STOP_R = crate::BitReader; +#[doc = "Field `REG_CPU_PLL_CAL_STOP` writer - Reserved"] +pub type REG_CPU_PLL_CAL_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SDIO_PLL_CAL_END` reader - Reserved"] +pub type REG_SDIO_PLL_CAL_END_R = crate::BitReader; +#[doc = "Field `REG_SDIO_PLL_CAL_STOP` reader - Reserved"] +pub type REG_SDIO_PLL_CAL_STOP_R = crate::BitReader; +#[doc = "Field `REG_SDIO_PLL_CAL_STOP` writer - Reserved"] +pub type REG_SDIO_PLL_CAL_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SYS_PLL_CAL_END` reader - Reserved"] +pub type REG_SYS_PLL_CAL_END_R = crate::BitReader; +#[doc = "Field `REG_SYS_PLL_CAL_STOP` reader - Reserved"] +pub type REG_SYS_PLL_CAL_STOP_R = crate::BitReader; +#[doc = "Field `REG_SYS_PLL_CAL_STOP` writer - Reserved"] +pub type REG_SYS_PLL_CAL_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MSPI_CAL_END` reader - Reserved"] +pub type REG_MSPI_CAL_END_R = crate::BitReader; +#[doc = "Field `REG_MSPI_CAL_STOP` reader - Reserved"] +pub type REG_MSPI_CAL_STOP_R = crate::BitReader; +#[doc = "Field `REG_MSPI_CAL_STOP` writer - Reserved"] +pub type REG_MSPI_CAL_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_plla_cal_end(&self) -> REG_PLLA_CAL_END_R { + REG_PLLA_CAL_END_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_plla_cal_stop(&self) -> REG_PLLA_CAL_STOP_R { + REG_PLLA_CAL_STOP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_cpu_pll_cal_end(&self) -> REG_CPU_PLL_CAL_END_R { + REG_CPU_PLL_CAL_END_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_cpu_pll_cal_stop(&self) -> REG_CPU_PLL_CAL_STOP_R { + REG_CPU_PLL_CAL_STOP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_sdio_pll_cal_end(&self) -> REG_SDIO_PLL_CAL_END_R { + REG_SDIO_PLL_CAL_END_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_sdio_pll_cal_stop(&self) -> REG_SDIO_PLL_CAL_STOP_R { + REG_SDIO_PLL_CAL_STOP_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn reg_sys_pll_cal_end(&self) -> REG_SYS_PLL_CAL_END_R { + REG_SYS_PLL_CAL_END_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_sys_pll_cal_stop(&self) -> REG_SYS_PLL_CAL_STOP_R { + REG_SYS_PLL_CAL_STOP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_mspi_cal_end(&self) -> REG_MSPI_CAL_END_R { + REG_MSPI_CAL_END_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_mspi_cal_stop(&self) -> REG_MSPI_CAL_STOP_R { + REG_MSPI_CAL_STOP_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_PLL_CTRL0") + .field( + "reg_plla_cal_end", + &format_args!("{}", self.reg_plla_cal_end().bit()), + ) + .field( + "reg_plla_cal_stop", + &format_args!("{}", self.reg_plla_cal_stop().bit()), + ) + .field( + "reg_cpu_pll_cal_end", + &format_args!("{}", self.reg_cpu_pll_cal_end().bit()), + ) + .field( + "reg_cpu_pll_cal_stop", + &format_args!("{}", self.reg_cpu_pll_cal_stop().bit()), + ) + .field( + "reg_sdio_pll_cal_end", + &format_args!("{}", self.reg_sdio_pll_cal_end().bit()), + ) + .field( + "reg_sdio_pll_cal_stop", + &format_args!("{}", self.reg_sdio_pll_cal_stop().bit()), + ) + .field( + "reg_sys_pll_cal_end", + &format_args!("{}", self.reg_sys_pll_cal_end().bit()), + ) + .field( + "reg_sys_pll_cal_stop", + &format_args!("{}", self.reg_sys_pll_cal_stop().bit()), + ) + .field( + "reg_mspi_cal_end", + &format_args!("{}", self.reg_mspi_cal_end().bit()), + ) + .field( + "reg_mspi_cal_stop", + &format_args!("{}", self.reg_mspi_cal_stop().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_plla_cal_stop(&mut self) -> REG_PLLA_CAL_STOP_W { + REG_PLLA_CAL_STOP_W::new(self, 1) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_cpu_pll_cal_stop(&mut self) -> REG_CPU_PLL_CAL_STOP_W { + REG_CPU_PLL_CAL_STOP_W::new(self, 3) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_pll_cal_stop(&mut self) -> REG_SDIO_PLL_CAL_STOP_W { + REG_SDIO_PLL_CAL_STOP_W::new(self, 5) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sys_pll_cal_stop(&mut self) -> REG_SYS_PLL_CAL_STOP_W { + REG_SYS_PLL_CAL_STOP_W::new(self, 7) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mspi_cal_stop(&mut self) -> REG_MSPI_CAL_STOP_W { + REG_MSPI_CAL_STOP_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_pll_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_pll_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_PLL_CTRL0_SPEC; +impl crate::RegisterSpec for ANA_PLL_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_pll_ctrl0::R`](R) reader structure"] +impl crate::Readable for ANA_PLL_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_pll_ctrl0::W`](W) writer structure"] +impl crate::Writable for ANA_PLL_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ANA_PLL_CTRL0 to value 0"] +impl crate::Resettable for ANA_PLL_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/clk_en0.rs b/esp32p4/src/hp_sys_clkrst/clk_en0.rs new file mode 100644 index 0000000000..ded7eaeb38 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/clk_en0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLK_EN0` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_EN0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_CLK_EN` reader - Reserved"] +pub type REG_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CLK_EN` writer - Reserved"] +pub type REG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_clk_en(&self) -> REG_CLK_EN_R { + REG_CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_EN0") + .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_clk_en(&mut self) -> REG_CLK_EN_W { + REG_CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_EN0_SPEC; +impl crate::RegisterSpec for CLK_EN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_en0::R`](R) reader structure"] +impl crate::Readable for CLK_EN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_en0::W`](W) writer structure"] +impl crate::Writable for CLK_EN0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_EN0 to value 0x01"] +impl crate::Resettable for CLK_EN0_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/hp_sys_clkrst/clk_force_on_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/clk_force_on_ctrl0.rs new file mode 100644 index 0000000000..baac56bb58 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/clk_force_on_ctrl0.rs @@ -0,0 +1,421 @@ +#[doc = "Register `CLK_FORCE_ON_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_FORCE_ON_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_CPUICM_GATED_CLK_FORCE_ON` reader - Reserved"] +pub type REG_CPUICM_GATED_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_CPUICM_GATED_CLK_FORCE_ON` writer - Reserved"] +pub type REG_CPUICM_GATED_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TCM_CPU_CLK_FORCE_ON` reader - Reserved"] +pub type REG_TCM_CPU_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_TCM_CPU_CLK_FORCE_ON` writer - Reserved"] +pub type REG_TCM_CPU_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_BUSMON_CPU_CLK_FORCE_ON` reader - Reserved"] +pub type REG_BUSMON_CPU_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_BUSMON_CPU_CLK_FORCE_ON` writer - Reserved"] +pub type REG_BUSMON_CPU_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_CPU_CLK_FORCE_ON` reader - Reserved"] +pub type REG_L1CACHE_CPU_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_CPU_CLK_FORCE_ON` writer - Reserved"] +pub type REG_L1CACHE_CPU_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_D_CPU_CLK_FORCE_ON` reader - Reserved"] +pub type REG_L1CACHE_D_CPU_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_D_CPU_CLK_FORCE_ON` writer - Reserved"] +pub type REG_L1CACHE_D_CPU_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_I0_CPU_CLK_FORCE_ON` reader - Reserved"] +pub type REG_L1CACHE_I0_CPU_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_I0_CPU_CLK_FORCE_ON` writer - Reserved"] +pub type REG_L1CACHE_I0_CPU_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_I1_CPU_CLK_FORCE_ON` reader - Reserved"] +pub type REG_L1CACHE_I1_CPU_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_I1_CPU_CLK_FORCE_ON` writer - Reserved"] +pub type REG_L1CACHE_I1_CPU_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TRACE_CPU_CLK_FORCE_ON` reader - Reserved"] +pub type REG_TRACE_CPU_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_TRACE_CPU_CLK_FORCE_ON` writer - Reserved"] +pub type REG_TRACE_CPU_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TRACE_SYS_CLK_FORCE_ON` reader - Reserved"] +pub type REG_TRACE_SYS_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_TRACE_SYS_CLK_FORCE_ON` writer - Reserved"] +pub type REG_TRACE_SYS_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_MEM_CLK_FORCE_ON` reader - Reserved"] +pub type REG_L1CACHE_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_MEM_CLK_FORCE_ON` writer - Reserved"] +pub type REG_L1CACHE_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_D_MEM_CLK_FORCE_ON` reader - Reserved"] +pub type REG_L1CACHE_D_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_D_MEM_CLK_FORCE_ON` writer - Reserved"] +pub type REG_L1CACHE_D_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_I0_MEM_CLK_FORCE_ON` reader - Reserved"] +pub type REG_L1CACHE_I0_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_I0_MEM_CLK_FORCE_ON` writer - Reserved"] +pub type REG_L1CACHE_I0_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_I1_MEM_CLK_FORCE_ON` reader - Reserved"] +pub type REG_L1CACHE_I1_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_I1_MEM_CLK_FORCE_ON` writer - Reserved"] +pub type REG_L1CACHE_I1_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L2CACHE_MEM_CLK_FORCE_ON` reader - Reserved"] +pub type REG_L2CACHE_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_L2CACHE_MEM_CLK_FORCE_ON` writer - Reserved"] +pub type REG_L2CACHE_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L2MEM_MEM_CLK_FORCE_ON` reader - Reserved"] +pub type REG_L2MEM_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_L2MEM_MEM_CLK_FORCE_ON` writer - Reserved"] +pub type REG_L2MEM_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SAR1_CLK_FORCE_ON` reader - Reserved"] +pub type REG_SAR1_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_SAR1_CLK_FORCE_ON` writer - Reserved"] +pub type REG_SAR1_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SAR2_CLK_FORCE_ON` reader - Reserved"] +pub type REG_SAR2_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_SAR2_CLK_FORCE_ON` writer - Reserved"] +pub type REG_SAR2_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GMAC_TX_CLK_FORCE_ON` reader - Reserved"] +pub type REG_GMAC_TX_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_GMAC_TX_CLK_FORCE_ON` writer - Reserved"] +pub type REG_GMAC_TX_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_cpuicm_gated_clk_force_on(&self) -> REG_CPUICM_GATED_CLK_FORCE_ON_R { + REG_CPUICM_GATED_CLK_FORCE_ON_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_tcm_cpu_clk_force_on(&self) -> REG_TCM_CPU_CLK_FORCE_ON_R { + REG_TCM_CPU_CLK_FORCE_ON_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_busmon_cpu_clk_force_on(&self) -> REG_BUSMON_CPU_CLK_FORCE_ON_R { + REG_BUSMON_CPU_CLK_FORCE_ON_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_cpu_clk_force_on(&self) -> REG_L1CACHE_CPU_CLK_FORCE_ON_R { + REG_L1CACHE_CPU_CLK_FORCE_ON_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_d_cpu_clk_force_on(&self) -> REG_L1CACHE_D_CPU_CLK_FORCE_ON_R { + REG_L1CACHE_D_CPU_CLK_FORCE_ON_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_i0_cpu_clk_force_on(&self) -> REG_L1CACHE_I0_CPU_CLK_FORCE_ON_R { + REG_L1CACHE_I0_CPU_CLK_FORCE_ON_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_i1_cpu_clk_force_on(&self) -> REG_L1CACHE_I1_CPU_CLK_FORCE_ON_R { + REG_L1CACHE_I1_CPU_CLK_FORCE_ON_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_trace_cpu_clk_force_on(&self) -> REG_TRACE_CPU_CLK_FORCE_ON_R { + REG_TRACE_CPU_CLK_FORCE_ON_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_trace_sys_clk_force_on(&self) -> REG_TRACE_SYS_CLK_FORCE_ON_R { + REG_TRACE_SYS_CLK_FORCE_ON_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_mem_clk_force_on(&self) -> REG_L1CACHE_MEM_CLK_FORCE_ON_R { + REG_L1CACHE_MEM_CLK_FORCE_ON_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_d_mem_clk_force_on(&self) -> REG_L1CACHE_D_MEM_CLK_FORCE_ON_R { + REG_L1CACHE_D_MEM_CLK_FORCE_ON_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_i0_mem_clk_force_on(&self) -> REG_L1CACHE_I0_MEM_CLK_FORCE_ON_R { + REG_L1CACHE_I0_MEM_CLK_FORCE_ON_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_i1_mem_clk_force_on(&self) -> REG_L1CACHE_I1_MEM_CLK_FORCE_ON_R { + REG_L1CACHE_I1_MEM_CLK_FORCE_ON_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn reg_l2cache_mem_clk_force_on(&self) -> REG_L2CACHE_MEM_CLK_FORCE_ON_R { + REG_L2CACHE_MEM_CLK_FORCE_ON_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn reg_l2mem_mem_clk_force_on(&self) -> REG_L2MEM_MEM_CLK_FORCE_ON_R { + REG_L2MEM_MEM_CLK_FORCE_ON_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn reg_sar1_clk_force_on(&self) -> REG_SAR1_CLK_FORCE_ON_R { + REG_SAR1_CLK_FORCE_ON_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_sar2_clk_force_on(&self) -> REG_SAR2_CLK_FORCE_ON_R { + REG_SAR2_CLK_FORCE_ON_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + pub fn reg_gmac_tx_clk_force_on(&self) -> REG_GMAC_TX_CLK_FORCE_ON_R { + REG_GMAC_TX_CLK_FORCE_ON_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_FORCE_ON_CTRL0") + .field( + "reg_cpuicm_gated_clk_force_on", + &format_args!("{}", self.reg_cpuicm_gated_clk_force_on().bit()), + ) + .field( + "reg_tcm_cpu_clk_force_on", + &format_args!("{}", self.reg_tcm_cpu_clk_force_on().bit()), + ) + .field( + "reg_busmon_cpu_clk_force_on", + &format_args!("{}", self.reg_busmon_cpu_clk_force_on().bit()), + ) + .field( + "reg_l1cache_cpu_clk_force_on", + &format_args!("{}", self.reg_l1cache_cpu_clk_force_on().bit()), + ) + .field( + "reg_l1cache_d_cpu_clk_force_on", + &format_args!("{}", self.reg_l1cache_d_cpu_clk_force_on().bit()), + ) + .field( + "reg_l1cache_i0_cpu_clk_force_on", + &format_args!("{}", self.reg_l1cache_i0_cpu_clk_force_on().bit()), + ) + .field( + "reg_l1cache_i1_cpu_clk_force_on", + &format_args!("{}", self.reg_l1cache_i1_cpu_clk_force_on().bit()), + ) + .field( + "reg_trace_cpu_clk_force_on", + &format_args!("{}", self.reg_trace_cpu_clk_force_on().bit()), + ) + .field( + "reg_trace_sys_clk_force_on", + &format_args!("{}", self.reg_trace_sys_clk_force_on().bit()), + ) + .field( + "reg_l1cache_mem_clk_force_on", + &format_args!("{}", self.reg_l1cache_mem_clk_force_on().bit()), + ) + .field( + "reg_l1cache_d_mem_clk_force_on", + &format_args!("{}", self.reg_l1cache_d_mem_clk_force_on().bit()), + ) + .field( + "reg_l1cache_i0_mem_clk_force_on", + &format_args!("{}", self.reg_l1cache_i0_mem_clk_force_on().bit()), + ) + .field( + "reg_l1cache_i1_mem_clk_force_on", + &format_args!("{}", self.reg_l1cache_i1_mem_clk_force_on().bit()), + ) + .field( + "reg_l2cache_mem_clk_force_on", + &format_args!("{}", self.reg_l2cache_mem_clk_force_on().bit()), + ) + .field( + "reg_l2mem_mem_clk_force_on", + &format_args!("{}", self.reg_l2mem_mem_clk_force_on().bit()), + ) + .field( + "reg_sar1_clk_force_on", + &format_args!("{}", self.reg_sar1_clk_force_on().bit()), + ) + .field( + "reg_sar2_clk_force_on", + &format_args!("{}", self.reg_sar2_clk_force_on().bit()), + ) + .field( + "reg_gmac_tx_clk_force_on", + &format_args!("{}", self.reg_gmac_tx_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_cpuicm_gated_clk_force_on( + &mut self, + ) -> REG_CPUICM_GATED_CLK_FORCE_ON_W { + REG_CPUICM_GATED_CLK_FORCE_ON_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tcm_cpu_clk_force_on( + &mut self, + ) -> REG_TCM_CPU_CLK_FORCE_ON_W { + REG_TCM_CPU_CLK_FORCE_ON_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_busmon_cpu_clk_force_on( + &mut self, + ) -> REG_BUSMON_CPU_CLK_FORCE_ON_W { + REG_BUSMON_CPU_CLK_FORCE_ON_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_cpu_clk_force_on( + &mut self, + ) -> REG_L1CACHE_CPU_CLK_FORCE_ON_W { + REG_L1CACHE_CPU_CLK_FORCE_ON_W::new(self, 3) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_d_cpu_clk_force_on( + &mut self, + ) -> REG_L1CACHE_D_CPU_CLK_FORCE_ON_W { + REG_L1CACHE_D_CPU_CLK_FORCE_ON_W::new(self, 4) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_i0_cpu_clk_force_on( + &mut self, + ) -> REG_L1CACHE_I0_CPU_CLK_FORCE_ON_W { + REG_L1CACHE_I0_CPU_CLK_FORCE_ON_W::new(self, 5) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_i1_cpu_clk_force_on( + &mut self, + ) -> REG_L1CACHE_I1_CPU_CLK_FORCE_ON_W { + REG_L1CACHE_I1_CPU_CLK_FORCE_ON_W::new(self, 6) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_trace_cpu_clk_force_on( + &mut self, + ) -> REG_TRACE_CPU_CLK_FORCE_ON_W { + REG_TRACE_CPU_CLK_FORCE_ON_W::new(self, 7) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_trace_sys_clk_force_on( + &mut self, + ) -> REG_TRACE_SYS_CLK_FORCE_ON_W { + REG_TRACE_SYS_CLK_FORCE_ON_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_mem_clk_force_on( + &mut self, + ) -> REG_L1CACHE_MEM_CLK_FORCE_ON_W { + REG_L1CACHE_MEM_CLK_FORCE_ON_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_d_mem_clk_force_on( + &mut self, + ) -> REG_L1CACHE_D_MEM_CLK_FORCE_ON_W { + REG_L1CACHE_D_MEM_CLK_FORCE_ON_W::new(self, 10) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_i0_mem_clk_force_on( + &mut self, + ) -> REG_L1CACHE_I0_MEM_CLK_FORCE_ON_W { + REG_L1CACHE_I0_MEM_CLK_FORCE_ON_W::new(self, 11) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_i1_mem_clk_force_on( + &mut self, + ) -> REG_L1CACHE_I1_MEM_CLK_FORCE_ON_W { + REG_L1CACHE_I1_MEM_CLK_FORCE_ON_W::new(self, 12) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l2cache_mem_clk_force_on( + &mut self, + ) -> REG_L2CACHE_MEM_CLK_FORCE_ON_W { + REG_L2CACHE_MEM_CLK_FORCE_ON_W::new(self, 13) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l2mem_mem_clk_force_on( + &mut self, + ) -> REG_L2MEM_MEM_CLK_FORCE_ON_W { + REG_L2MEM_MEM_CLK_FORCE_ON_W::new(self, 14) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sar1_clk_force_on(&mut self) -> REG_SAR1_CLK_FORCE_ON_W { + REG_SAR1_CLK_FORCE_ON_W::new(self, 15) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sar2_clk_force_on(&mut self) -> REG_SAR2_CLK_FORCE_ON_W { + REG_SAR2_CLK_FORCE_ON_W::new(self, 16) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gmac_tx_clk_force_on( + &mut self, + ) -> REG_GMAC_TX_CLK_FORCE_ON_W { + REG_GMAC_TX_CLK_FORCE_ON_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_force_on_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_force_on_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_FORCE_ON_CTRL0_SPEC; +impl crate::RegisterSpec for CLK_FORCE_ON_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_force_on_ctrl0::R`](R) reader structure"] +impl crate::Readable for CLK_FORCE_ON_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_force_on_ctrl0::W`](W) writer structure"] +impl crate::Writable for CLK_FORCE_ON_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_FORCE_ON_CTRL0 to value 0x0003_ffff"] +impl crate::Resettable for CLK_FORCE_ON_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0x0003_ffff; +} diff --git a/esp32p4/src/hp_sys_clkrst/cpu_clk_status0.rs b/esp32p4/src/hp_sys_clkrst/cpu_clk_status0.rs new file mode 100644 index 0000000000..3994e584a7 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/cpu_clk_status0.rs @@ -0,0 +1,94 @@ +#[doc = "Register `CPU_CLK_STATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `REG_ASIC_OR_FPGA` reader - 0: ASIC mode, 1: FPGA mode"] +pub type REG_ASIC_OR_FPGA_R = crate::BitReader; +#[doc = "Field `REG_CPU_DIV_EFFECT` reader - 0: Divider bypass, 1: Divider takes effect"] +pub type REG_CPU_DIV_EFFECT_R = crate::BitReader; +#[doc = "Field `REG_CPU_SRC_IS_CPLL` reader - 0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m"] +pub type REG_CPU_SRC_IS_CPLL_R = crate::BitReader; +#[doc = "Field `REG_CPU_DIV_NUM_CUR` reader - cpu current div number"] +pub type REG_CPU_DIV_NUM_CUR_R = crate::FieldReader; +#[doc = "Field `REG_CPU_DIV_NUMERATOR_CUR` reader - cpu current div numerator"] +pub type REG_CPU_DIV_NUMERATOR_CUR_R = crate::FieldReader; +#[doc = "Field `REG_CPU_DIV_DENOMINATOR_CUR` reader - cpu current div denominator"] +pub type REG_CPU_DIV_DENOMINATOR_CUR_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - 0: ASIC mode, 1: FPGA mode"] + #[inline(always)] + pub fn reg_asic_or_fpga(&self) -> REG_ASIC_OR_FPGA_R { + REG_ASIC_OR_FPGA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 0: Divider bypass, 1: Divider takes effect"] + #[inline(always)] + pub fn reg_cpu_div_effect(&self) -> REG_CPU_DIV_EFFECT_R { + REG_CPU_DIV_EFFECT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m"] + #[inline(always)] + pub fn reg_cpu_src_is_cpll(&self) -> REG_CPU_SRC_IS_CPLL_R { + REG_CPU_SRC_IS_CPLL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:10 - cpu current div number"] + #[inline(always)] + pub fn reg_cpu_div_num_cur(&self) -> REG_CPU_DIV_NUM_CUR_R { + REG_CPU_DIV_NUM_CUR_R::new(((self.bits >> 3) & 0xff) as u8) + } + #[doc = "Bits 11:18 - cpu current div numerator"] + #[inline(always)] + pub fn reg_cpu_div_numerator_cur(&self) -> REG_CPU_DIV_NUMERATOR_CUR_R { + REG_CPU_DIV_NUMERATOR_CUR_R::new(((self.bits >> 11) & 0xff) as u8) + } + #[doc = "Bits 19:26 - cpu current div denominator"] + #[inline(always)] + pub fn reg_cpu_div_denominator_cur(&self) -> REG_CPU_DIV_DENOMINATOR_CUR_R { + REG_CPU_DIV_DENOMINATOR_CUR_R::new(((self.bits >> 19) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU_CLK_STATUS0") + .field( + "reg_asic_or_fpga", + &format_args!("{}", self.reg_asic_or_fpga().bit()), + ) + .field( + "reg_cpu_div_effect", + &format_args!("{}", self.reg_cpu_div_effect().bit()), + ) + .field( + "reg_cpu_src_is_cpll", + &format_args!("{}", self.reg_cpu_src_is_cpll().bit()), + ) + .field( + "reg_cpu_div_num_cur", + &format_args!("{}", self.reg_cpu_div_num_cur().bits()), + ) + .field( + "reg_cpu_div_numerator_cur", + &format_args!("{}", self.reg_cpu_div_numerator_cur().bits()), + ) + .field( + "reg_cpu_div_denominator_cur", + &format_args!("{}", self.reg_cpu_div_denominator_cur().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "CPU Clock Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_clk_status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_CLK_STATUS0_SPEC; +impl crate::RegisterSpec for CPU_CLK_STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu_clk_status0::R`](R) reader structure"] +impl crate::Readable for CPU_CLK_STATUS0_SPEC {} +#[doc = "`reset()` method sets CPU_CLK_STATUS0 to value 0"] +impl crate::Resettable for CPU_CLK_STATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/cpu_src_freq0.rs b/esp32p4/src/hp_sys_clkrst/cpu_src_freq0.rs new file mode 100644 index 0000000000..48e8e62a7a --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/cpu_src_freq0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CPU_SRC_FREQ0` reader"] +pub type R = crate::R; +#[doc = "Field `REG_CPU_SRC_FREQ` reader - cpu source clock frequency, step by 0.25MHz"] +pub type REG_CPU_SRC_FREQ_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - cpu source clock frequency, step by 0.25MHz"] + #[inline(always)] + pub fn reg_cpu_src_freq(&self) -> REG_CPU_SRC_FREQ_R { + REG_CPU_SRC_FREQ_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU_SRC_FREQ0") + .field( + "reg_cpu_src_freq", + &format_args!("{}", self.reg_cpu_src_freq().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "CPU Source Frequency\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_src_freq0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_SRC_FREQ0_SPEC; +impl crate::RegisterSpec for CPU_SRC_FREQ0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu_src_freq0::R`](R) reader structure"] +impl crate::Readable for CPU_SRC_FREQ0_SPEC {} +#[doc = "`reset()` method sets CPU_SRC_FREQ0 to value 0"] +impl crate::Resettable for CPU_SRC_FREQ0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl0.rs new file mode 100644 index 0000000000..4050522440 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl0.rs @@ -0,0 +1,123 @@ +#[doc = "Register `DBG_CLK_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `DBG_CLK_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DBG_CH0_SEL` reader - Reserved"] +pub type REG_DBG_CH0_SEL_R = crate::FieldReader; +#[doc = "Field `REG_DBG_CH0_SEL` writer - Reserved"] +pub type REG_DBG_CH0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DBG_CH1_SEL` reader - Reserved"] +pub type REG_DBG_CH1_SEL_R = crate::FieldReader; +#[doc = "Field `REG_DBG_CH1_SEL` writer - Reserved"] +pub type REG_DBG_CH1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DBG_CH2_SEL` reader - Reserved"] +pub type REG_DBG_CH2_SEL_R = crate::FieldReader; +#[doc = "Field `REG_DBG_CH2_SEL` writer - Reserved"] +pub type REG_DBG_CH2_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DBG_CH0_DIV_NUM` reader - Reserved"] +pub type REG_DBG_CH0_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_DBG_CH0_DIV_NUM` writer - Reserved"] +pub type REG_DBG_CH0_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_dbg_ch0_sel(&self) -> REG_DBG_CH0_SEL_R { + REG_DBG_CH0_SEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_dbg_ch1_sel(&self) -> REG_DBG_CH1_SEL_R { + REG_DBG_CH1_SEL_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_dbg_ch2_sel(&self) -> REG_DBG_CH2_SEL_R { + REG_DBG_CH2_SEL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Reserved"] + #[inline(always)] + pub fn reg_dbg_ch0_div_num(&self) -> REG_DBG_CH0_DIV_NUM_R { + REG_DBG_CH0_DIV_NUM_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBG_CLK_CTRL0") + .field( + "reg_dbg_ch0_sel", + &format_args!("{}", self.reg_dbg_ch0_sel().bits()), + ) + .field( + "reg_dbg_ch1_sel", + &format_args!("{}", self.reg_dbg_ch1_sel().bits()), + ) + .field( + "reg_dbg_ch2_sel", + &format_args!("{}", self.reg_dbg_ch2_sel().bits()), + ) + .field( + "reg_dbg_ch0_div_num", + &format_args!("{}", self.reg_dbg_ch0_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dbg_ch0_sel(&mut self) -> REG_DBG_CH0_SEL_W { + REG_DBG_CH0_SEL_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dbg_ch1_sel(&mut self) -> REG_DBG_CH1_SEL_W { + REG_DBG_CH1_SEL_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dbg_ch2_sel(&mut self) -> REG_DBG_CH2_SEL_W { + REG_DBG_CH2_SEL_W::new(self, 16) + } + #[doc = "Bits 24:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dbg_ch0_div_num(&mut self) -> REG_DBG_CH0_DIV_NUM_W { + REG_DBG_CH0_DIV_NUM_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_clk_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_clk_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBG_CLK_CTRL0_SPEC; +impl crate::RegisterSpec for DBG_CLK_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbg_clk_ctrl0::R`](R) reader structure"] +impl crate::Readable for DBG_CLK_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_clk_ctrl0::W`](W) writer structure"] +impl crate::Writable for DBG_CLK_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBG_CLK_CTRL0 to value 0x03ff_ffff"] +impl crate::Resettable for DBG_CLK_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0x03ff_ffff; +} diff --git a/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl1.rs b/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl1.rs new file mode 100644 index 0000000000..a323678294 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl1.rs @@ -0,0 +1,142 @@ +#[doc = "Register `DBG_CLK_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `DBG_CLK_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DBG_CH1_DIV_NUM` reader - Reserved"] +pub type REG_DBG_CH1_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_DBG_CH1_DIV_NUM` writer - Reserved"] +pub type REG_DBG_CH1_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DBG_CH2_DIV_NUM` reader - Reserved"] +pub type REG_DBG_CH2_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_DBG_CH2_DIV_NUM` writer - Reserved"] +pub type REG_DBG_CH2_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DBG_CH0_EN` reader - Reserved"] +pub type REG_DBG_CH0_EN_R = crate::BitReader; +#[doc = "Field `REG_DBG_CH0_EN` writer - Reserved"] +pub type REG_DBG_CH0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_DBG_CH1_EN` reader - Reserved"] +pub type REG_DBG_CH1_EN_R = crate::BitReader; +#[doc = "Field `REG_DBG_CH1_EN` writer - Reserved"] +pub type REG_DBG_CH1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_DBG_CH2_EN` reader - Reserved"] +pub type REG_DBG_CH2_EN_R = crate::BitReader; +#[doc = "Field `REG_DBG_CH2_EN` writer - Reserved"] +pub type REG_DBG_CH2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_dbg_ch1_div_num(&self) -> REG_DBG_CH1_DIV_NUM_R { + REG_DBG_CH1_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_dbg_ch2_div_num(&self) -> REG_DBG_CH2_DIV_NUM_R { + REG_DBG_CH2_DIV_NUM_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_dbg_ch0_en(&self) -> REG_DBG_CH0_EN_R { + REG_DBG_CH0_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + pub fn reg_dbg_ch1_en(&self) -> REG_DBG_CH1_EN_R { + REG_DBG_CH1_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_dbg_ch2_en(&self) -> REG_DBG_CH2_EN_R { + REG_DBG_CH2_EN_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBG_CLK_CTRL1") + .field( + "reg_dbg_ch1_div_num", + &format_args!("{}", self.reg_dbg_ch1_div_num().bits()), + ) + .field( + "reg_dbg_ch2_div_num", + &format_args!("{}", self.reg_dbg_ch2_div_num().bits()), + ) + .field( + "reg_dbg_ch0_en", + &format_args!("{}", self.reg_dbg_ch0_en().bit()), + ) + .field( + "reg_dbg_ch1_en", + &format_args!("{}", self.reg_dbg_ch1_en().bit()), + ) + .field( + "reg_dbg_ch2_en", + &format_args!("{}", self.reg_dbg_ch2_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dbg_ch1_div_num(&mut self) -> REG_DBG_CH1_DIV_NUM_W { + REG_DBG_CH1_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dbg_ch2_div_num(&mut self) -> REG_DBG_CH2_DIV_NUM_W { + REG_DBG_CH2_DIV_NUM_W::new(self, 8) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dbg_ch0_en(&mut self) -> REG_DBG_CH0_EN_W { + REG_DBG_CH0_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dbg_ch1_en(&mut self) -> REG_DBG_CH1_EN_W { + REG_DBG_CH1_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dbg_ch2_en(&mut self) -> REG_DBG_CH2_EN_W { + REG_DBG_CH2_EN_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbg_clk_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbg_clk_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBG_CLK_CTRL1_SPEC; +impl crate::RegisterSpec for DBG_CLK_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbg_clk_ctrl1::R`](R) reader structure"] +impl crate::Readable for DBG_CLK_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_clk_ctrl1::W`](W) writer structure"] +impl crate::Writable for DBG_CLK_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBG_CLK_CTRL1 to value 0x0303"] +impl crate::Resettable for DBG_CLK_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0x0303; +} diff --git a/esp32p4/src/hp_sys_clkrst/dpa_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/dpa_ctrl0.rs new file mode 100644 index 0000000000..fa9df4ad9d --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/dpa_ctrl0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DPA_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `DPA_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_SEC_DPA_LEVEL` reader - Reserved"] +pub type REG_SEC_DPA_LEVEL_R = crate::FieldReader; +#[doc = "Field `REG_SEC_DPA_LEVEL` writer - Reserved"] +pub type REG_SEC_DPA_LEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_SEC_DPA_CFG_SEL` reader - Reserved"] +pub type REG_SEC_DPA_CFG_SEL_R = crate::BitReader; +#[doc = "Field `REG_SEC_DPA_CFG_SEL` writer - Reserved"] +pub type REG_SEC_DPA_CFG_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_sec_dpa_level(&self) -> REG_SEC_DPA_LEVEL_R { + REG_SEC_DPA_LEVEL_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_sec_dpa_cfg_sel(&self) -> REG_SEC_DPA_CFG_SEL_R { + REG_SEC_DPA_CFG_SEL_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPA_CTRL0") + .field( + "reg_sec_dpa_level", + &format_args!("{}", self.reg_sec_dpa_level().bits()), + ) + .field( + "reg_sec_dpa_cfg_sel", + &format_args!("{}", self.reg_sec_dpa_cfg_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sec_dpa_level(&mut self) -> REG_SEC_DPA_LEVEL_W { + REG_SEC_DPA_LEVEL_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sec_dpa_cfg_sel(&mut self) -> REG_SEC_DPA_CFG_SEL_W { + REG_SEC_DPA_CFG_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpa_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpa_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPA_CTRL0_SPEC; +impl crate::RegisterSpec for DPA_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpa_ctrl0::R`](R) reader structure"] +impl crate::Readable for DPA_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpa_ctrl0::W`](W) writer structure"] +impl crate::Writable for DPA_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPA_CTRL0 to value 0"] +impl crate::Resettable for DPA_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/hp_force_norst0.rs b/esp32p4/src/hp_sys_clkrst/hp_force_norst0.rs new file mode 100644 index 0000000000..11c8988cbe --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/hp_force_norst0.rs @@ -0,0 +1,667 @@ +#[doc = "Register `HP_FORCE_NORST0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_FORCE_NORST0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_FORCE_NORST_CORE0` reader - Reserved"] +pub type REG_FORCE_NORST_CORE0_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_CORE0` writer - Reserved"] +pub type REG_FORCE_NORST_CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_CORE1` reader - Reserved"] +pub type REG_FORCE_NORST_CORE1_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_CORE1` writer - Reserved"] +pub type REG_FORCE_NORST_CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_CORETRACE0` reader - Reserved"] +pub type REG_FORCE_NORST_CORETRACE0_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_CORETRACE0` writer - Reserved"] +pub type REG_FORCE_NORST_CORETRACE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_CORETRACE1` reader - Reserved"] +pub type REG_FORCE_NORST_CORETRACE1_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_CORETRACE1` writer - Reserved"] +pub type REG_FORCE_NORST_CORETRACE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_L2MEMMON` reader - Reserved"] +pub type REG_FORCE_NORST_L2MEMMON_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_L2MEMMON` writer - Reserved"] +pub type REG_FORCE_NORST_L2MEMMON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_TCMMON` reader - Reserved"] +pub type REG_FORCE_NORST_TCMMON_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_TCMMON` writer - Reserved"] +pub type REG_FORCE_NORST_TCMMON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_GDMA` reader - Reserved"] +pub type REG_FORCE_NORST_GDMA_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_GDMA` writer - Reserved"] +pub type REG_FORCE_NORST_GDMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_MSPI_AXI` reader - Reserved"] +pub type REG_FORCE_NORST_MSPI_AXI_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_MSPI_AXI` writer - Reserved"] +pub type REG_FORCE_NORST_MSPI_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_DUAL_MSPI_AXI` reader - Reserved"] +pub type REG_FORCE_NORST_DUAL_MSPI_AXI_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_DUAL_MSPI_AXI` writer - Reserved"] +pub type REG_FORCE_NORST_DUAL_MSPI_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_MSPI_APB` reader - Reserved"] +pub type REG_FORCE_NORST_MSPI_APB_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_MSPI_APB` writer - Reserved"] +pub type REG_FORCE_NORST_MSPI_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_DUAL_MSPI_APB` reader - Reserved"] +pub type REG_FORCE_NORST_DUAL_MSPI_APB_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_DUAL_MSPI_APB` writer - Reserved"] +pub type REG_FORCE_NORST_DUAL_MSPI_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_DSI_BRG` reader - Reserved"] +pub type REG_FORCE_NORST_DSI_BRG_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_DSI_BRG` writer - Reserved"] +pub type REG_FORCE_NORST_DSI_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_CSI_HOST` reader - Reserved"] +pub type REG_FORCE_NORST_CSI_HOST_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_CSI_HOST` writer - Reserved"] +pub type REG_FORCE_NORST_CSI_HOST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_CSI_BRG` reader - Reserved"] +pub type REG_FORCE_NORST_CSI_BRG_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_CSI_BRG` writer - Reserved"] +pub type REG_FORCE_NORST_CSI_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_ISP` reader - Reserved"] +pub type REG_FORCE_NORST_ISP_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_ISP` writer - Reserved"] +pub type REG_FORCE_NORST_ISP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_JPEG` reader - Reserved"] +pub type REG_FORCE_NORST_JPEG_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_JPEG` writer - Reserved"] +pub type REG_FORCE_NORST_JPEG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_DMA2D` reader - Reserved"] +pub type REG_FORCE_NORST_DMA2D_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_DMA2D` writer - Reserved"] +pub type REG_FORCE_NORST_DMA2D_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_PPA` reader - Reserved"] +pub type REG_FORCE_NORST_PPA_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_PPA` writer - Reserved"] +pub type REG_FORCE_NORST_PPA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_AHB_PDMA` reader - Reserved"] +pub type REG_FORCE_NORST_AHB_PDMA_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_AHB_PDMA` writer - Reserved"] +pub type REG_FORCE_NORST_AHB_PDMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_AXI_PDMA` reader - Reserved"] +pub type REG_FORCE_NORST_AXI_PDMA_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_AXI_PDMA` writer - Reserved"] +pub type REG_FORCE_NORST_AXI_PDMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_IOMUX` reader - Reserved"] +pub type REG_FORCE_NORST_IOMUX_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_IOMUX` writer - Reserved"] +pub type REG_FORCE_NORST_IOMUX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_PADBIST` reader - Reserved"] +pub type REG_FORCE_NORST_PADBIST_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_PADBIST` writer - Reserved"] +pub type REG_FORCE_NORST_PADBIST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_STIMER` reader - Reserved"] +pub type REG_FORCE_NORST_STIMER_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_STIMER` writer - Reserved"] +pub type REG_FORCE_NORST_STIMER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_TIMERGRP0` reader - Reserved"] +pub type REG_FORCE_NORST_TIMERGRP0_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_TIMERGRP0` writer - Reserved"] +pub type REG_FORCE_NORST_TIMERGRP0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_TIMERGRP1` reader - Reserved"] +pub type REG_FORCE_NORST_TIMERGRP1_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_TIMERGRP1` writer - Reserved"] +pub type REG_FORCE_NORST_TIMERGRP1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_UART0` reader - Reserved"] +pub type REG_FORCE_NORST_UART0_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_UART0` writer - Reserved"] +pub type REG_FORCE_NORST_UART0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_UART1` reader - Reserved"] +pub type REG_FORCE_NORST_UART1_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_UART1` writer - Reserved"] +pub type REG_FORCE_NORST_UART1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_UART2` reader - Reserved"] +pub type REG_FORCE_NORST_UART2_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_UART2` writer - Reserved"] +pub type REG_FORCE_NORST_UART2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_UART3` reader - Reserved"] +pub type REG_FORCE_NORST_UART3_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_UART3` writer - Reserved"] +pub type REG_FORCE_NORST_UART3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_UART4` reader - Reserved"] +pub type REG_FORCE_NORST_UART4_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_UART4` writer - Reserved"] +pub type REG_FORCE_NORST_UART4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_UHCI` reader - Reserved"] +pub type REG_FORCE_NORST_UHCI_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_UHCI` writer - Reserved"] +pub type REG_FORCE_NORST_UHCI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_I3CMST` reader - Reserved"] +pub type REG_FORCE_NORST_I3CMST_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_I3CMST` writer - Reserved"] +pub type REG_FORCE_NORST_I3CMST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_core0(&self) -> REG_FORCE_NORST_CORE0_R { + REG_FORCE_NORST_CORE0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_core1(&self) -> REG_FORCE_NORST_CORE1_R { + REG_FORCE_NORST_CORE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_coretrace0(&self) -> REG_FORCE_NORST_CORETRACE0_R { + REG_FORCE_NORST_CORETRACE0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_coretrace1(&self) -> REG_FORCE_NORST_CORETRACE1_R { + REG_FORCE_NORST_CORETRACE1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_l2memmon(&self) -> REG_FORCE_NORST_L2MEMMON_R { + REG_FORCE_NORST_L2MEMMON_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_tcmmon(&self) -> REG_FORCE_NORST_TCMMON_R { + REG_FORCE_NORST_TCMMON_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_gdma(&self) -> REG_FORCE_NORST_GDMA_R { + REG_FORCE_NORST_GDMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_mspi_axi(&self) -> REG_FORCE_NORST_MSPI_AXI_R { + REG_FORCE_NORST_MSPI_AXI_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_dual_mspi_axi(&self) -> REG_FORCE_NORST_DUAL_MSPI_AXI_R { + REG_FORCE_NORST_DUAL_MSPI_AXI_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_mspi_apb(&self) -> REG_FORCE_NORST_MSPI_APB_R { + REG_FORCE_NORST_MSPI_APB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_dual_mspi_apb(&self) -> REG_FORCE_NORST_DUAL_MSPI_APB_R { + REG_FORCE_NORST_DUAL_MSPI_APB_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_dsi_brg(&self) -> REG_FORCE_NORST_DSI_BRG_R { + REG_FORCE_NORST_DSI_BRG_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_csi_host(&self) -> REG_FORCE_NORST_CSI_HOST_R { + REG_FORCE_NORST_CSI_HOST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_csi_brg(&self) -> REG_FORCE_NORST_CSI_BRG_R { + REG_FORCE_NORST_CSI_BRG_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_isp(&self) -> REG_FORCE_NORST_ISP_R { + REG_FORCE_NORST_ISP_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_jpeg(&self) -> REG_FORCE_NORST_JPEG_R { + REG_FORCE_NORST_JPEG_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_dma2d(&self) -> REG_FORCE_NORST_DMA2D_R { + REG_FORCE_NORST_DMA2D_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_ppa(&self) -> REG_FORCE_NORST_PPA_R { + REG_FORCE_NORST_PPA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_ahb_pdma(&self) -> REG_FORCE_NORST_AHB_PDMA_R { + REG_FORCE_NORST_AHB_PDMA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_axi_pdma(&self) -> REG_FORCE_NORST_AXI_PDMA_R { + REG_FORCE_NORST_AXI_PDMA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_iomux(&self) -> REG_FORCE_NORST_IOMUX_R { + REG_FORCE_NORST_IOMUX_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_padbist(&self) -> REG_FORCE_NORST_PADBIST_R { + REG_FORCE_NORST_PADBIST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_stimer(&self) -> REG_FORCE_NORST_STIMER_R { + REG_FORCE_NORST_STIMER_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_timergrp0(&self) -> REG_FORCE_NORST_TIMERGRP0_R { + REG_FORCE_NORST_TIMERGRP0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_timergrp1(&self) -> REG_FORCE_NORST_TIMERGRP1_R { + REG_FORCE_NORST_TIMERGRP1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_uart0(&self) -> REG_FORCE_NORST_UART0_R { + REG_FORCE_NORST_UART0_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_uart1(&self) -> REG_FORCE_NORST_UART1_R { + REG_FORCE_NORST_UART1_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_uart2(&self) -> REG_FORCE_NORST_UART2_R { + REG_FORCE_NORST_UART2_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_uart3(&self) -> REG_FORCE_NORST_UART3_R { + REG_FORCE_NORST_UART3_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_uart4(&self) -> REG_FORCE_NORST_UART4_R { + REG_FORCE_NORST_UART4_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_uhci(&self) -> REG_FORCE_NORST_UHCI_R { + REG_FORCE_NORST_UHCI_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_i3cmst(&self) -> REG_FORCE_NORST_I3CMST_R { + REG_FORCE_NORST_I3CMST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_FORCE_NORST0") + .field( + "reg_force_norst_core0", + &format_args!("{}", self.reg_force_norst_core0().bit()), + ) + .field( + "reg_force_norst_core1", + &format_args!("{}", self.reg_force_norst_core1().bit()), + ) + .field( + "reg_force_norst_coretrace0", + &format_args!("{}", self.reg_force_norst_coretrace0().bit()), + ) + .field( + "reg_force_norst_coretrace1", + &format_args!("{}", self.reg_force_norst_coretrace1().bit()), + ) + .field( + "reg_force_norst_l2memmon", + &format_args!("{}", self.reg_force_norst_l2memmon().bit()), + ) + .field( + "reg_force_norst_tcmmon", + &format_args!("{}", self.reg_force_norst_tcmmon().bit()), + ) + .field( + "reg_force_norst_gdma", + &format_args!("{}", self.reg_force_norst_gdma().bit()), + ) + .field( + "reg_force_norst_mspi_axi", + &format_args!("{}", self.reg_force_norst_mspi_axi().bit()), + ) + .field( + "reg_force_norst_dual_mspi_axi", + &format_args!("{}", self.reg_force_norst_dual_mspi_axi().bit()), + ) + .field( + "reg_force_norst_mspi_apb", + &format_args!("{}", self.reg_force_norst_mspi_apb().bit()), + ) + .field( + "reg_force_norst_dual_mspi_apb", + &format_args!("{}", self.reg_force_norst_dual_mspi_apb().bit()), + ) + .field( + "reg_force_norst_dsi_brg", + &format_args!("{}", self.reg_force_norst_dsi_brg().bit()), + ) + .field( + "reg_force_norst_csi_host", + &format_args!("{}", self.reg_force_norst_csi_host().bit()), + ) + .field( + "reg_force_norst_csi_brg", + &format_args!("{}", self.reg_force_norst_csi_brg().bit()), + ) + .field( + "reg_force_norst_isp", + &format_args!("{}", self.reg_force_norst_isp().bit()), + ) + .field( + "reg_force_norst_jpeg", + &format_args!("{}", self.reg_force_norst_jpeg().bit()), + ) + .field( + "reg_force_norst_dma2d", + &format_args!("{}", self.reg_force_norst_dma2d().bit()), + ) + .field( + "reg_force_norst_ppa", + &format_args!("{}", self.reg_force_norst_ppa().bit()), + ) + .field( + "reg_force_norst_ahb_pdma", + &format_args!("{}", self.reg_force_norst_ahb_pdma().bit()), + ) + .field( + "reg_force_norst_axi_pdma", + &format_args!("{}", self.reg_force_norst_axi_pdma().bit()), + ) + .field( + "reg_force_norst_iomux", + &format_args!("{}", self.reg_force_norst_iomux().bit()), + ) + .field( + "reg_force_norst_padbist", + &format_args!("{}", self.reg_force_norst_padbist().bit()), + ) + .field( + "reg_force_norst_stimer", + &format_args!("{}", self.reg_force_norst_stimer().bit()), + ) + .field( + "reg_force_norst_timergrp0", + &format_args!("{}", self.reg_force_norst_timergrp0().bit()), + ) + .field( + "reg_force_norst_timergrp1", + &format_args!("{}", self.reg_force_norst_timergrp1().bit()), + ) + .field( + "reg_force_norst_uart0", + &format_args!("{}", self.reg_force_norst_uart0().bit()), + ) + .field( + "reg_force_norst_uart1", + &format_args!("{}", self.reg_force_norst_uart1().bit()), + ) + .field( + "reg_force_norst_uart2", + &format_args!("{}", self.reg_force_norst_uart2().bit()), + ) + .field( + "reg_force_norst_uart3", + &format_args!("{}", self.reg_force_norst_uart3().bit()), + ) + .field( + "reg_force_norst_uart4", + &format_args!("{}", self.reg_force_norst_uart4().bit()), + ) + .field( + "reg_force_norst_uhci", + &format_args!("{}", self.reg_force_norst_uhci().bit()), + ) + .field( + "reg_force_norst_i3cmst", + &format_args!("{}", self.reg_force_norst_i3cmst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_core0(&mut self) -> REG_FORCE_NORST_CORE0_W { + REG_FORCE_NORST_CORE0_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_core1(&mut self) -> REG_FORCE_NORST_CORE1_W { + REG_FORCE_NORST_CORE1_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_coretrace0( + &mut self, + ) -> REG_FORCE_NORST_CORETRACE0_W { + REG_FORCE_NORST_CORETRACE0_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_coretrace1( + &mut self, + ) -> REG_FORCE_NORST_CORETRACE1_W { + REG_FORCE_NORST_CORETRACE1_W::new(self, 3) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_l2memmon(&mut self) -> REG_FORCE_NORST_L2MEMMON_W { + REG_FORCE_NORST_L2MEMMON_W::new(self, 4) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_tcmmon(&mut self) -> REG_FORCE_NORST_TCMMON_W { + REG_FORCE_NORST_TCMMON_W::new(self, 5) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_gdma(&mut self) -> REG_FORCE_NORST_GDMA_W { + REG_FORCE_NORST_GDMA_W::new(self, 6) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_mspi_axi(&mut self) -> REG_FORCE_NORST_MSPI_AXI_W { + REG_FORCE_NORST_MSPI_AXI_W::new(self, 7) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_dual_mspi_axi( + &mut self, + ) -> REG_FORCE_NORST_DUAL_MSPI_AXI_W { + REG_FORCE_NORST_DUAL_MSPI_AXI_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_mspi_apb(&mut self) -> REG_FORCE_NORST_MSPI_APB_W { + REG_FORCE_NORST_MSPI_APB_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_dual_mspi_apb( + &mut self, + ) -> REG_FORCE_NORST_DUAL_MSPI_APB_W { + REG_FORCE_NORST_DUAL_MSPI_APB_W::new(self, 10) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_dsi_brg(&mut self) -> REG_FORCE_NORST_DSI_BRG_W { + REG_FORCE_NORST_DSI_BRG_W::new(self, 11) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_csi_host(&mut self) -> REG_FORCE_NORST_CSI_HOST_W { + REG_FORCE_NORST_CSI_HOST_W::new(self, 12) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_csi_brg(&mut self) -> REG_FORCE_NORST_CSI_BRG_W { + REG_FORCE_NORST_CSI_BRG_W::new(self, 13) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_isp(&mut self) -> REG_FORCE_NORST_ISP_W { + REG_FORCE_NORST_ISP_W::new(self, 14) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_jpeg(&mut self) -> REG_FORCE_NORST_JPEG_W { + REG_FORCE_NORST_JPEG_W::new(self, 15) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_dma2d(&mut self) -> REG_FORCE_NORST_DMA2D_W { + REG_FORCE_NORST_DMA2D_W::new(self, 16) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_ppa(&mut self) -> REG_FORCE_NORST_PPA_W { + REG_FORCE_NORST_PPA_W::new(self, 17) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_ahb_pdma(&mut self) -> REG_FORCE_NORST_AHB_PDMA_W { + REG_FORCE_NORST_AHB_PDMA_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_axi_pdma(&mut self) -> REG_FORCE_NORST_AXI_PDMA_W { + REG_FORCE_NORST_AXI_PDMA_W::new(self, 19) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_iomux(&mut self) -> REG_FORCE_NORST_IOMUX_W { + REG_FORCE_NORST_IOMUX_W::new(self, 20) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_padbist(&mut self) -> REG_FORCE_NORST_PADBIST_W { + REG_FORCE_NORST_PADBIST_W::new(self, 21) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_stimer(&mut self) -> REG_FORCE_NORST_STIMER_W { + REG_FORCE_NORST_STIMER_W::new(self, 22) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_timergrp0( + &mut self, + ) -> REG_FORCE_NORST_TIMERGRP0_W { + REG_FORCE_NORST_TIMERGRP0_W::new(self, 23) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_timergrp1( + &mut self, + ) -> REG_FORCE_NORST_TIMERGRP1_W { + REG_FORCE_NORST_TIMERGRP1_W::new(self, 24) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_uart0(&mut self) -> REG_FORCE_NORST_UART0_W { + REG_FORCE_NORST_UART0_W::new(self, 25) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_uart1(&mut self) -> REG_FORCE_NORST_UART1_W { + REG_FORCE_NORST_UART1_W::new(self, 26) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_uart2(&mut self) -> REG_FORCE_NORST_UART2_W { + REG_FORCE_NORST_UART2_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_uart3(&mut self) -> REG_FORCE_NORST_UART3_W { + REG_FORCE_NORST_UART3_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_uart4(&mut self) -> REG_FORCE_NORST_UART4_W { + REG_FORCE_NORST_UART4_W::new(self, 29) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_uhci(&mut self) -> REG_FORCE_NORST_UHCI_W { + REG_FORCE_NORST_UHCI_W::new(self, 30) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_i3cmst(&mut self) -> REG_FORCE_NORST_I3CMST_W { + REG_FORCE_NORST_I3CMST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_force_norst0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_force_norst0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_FORCE_NORST0_SPEC; +impl crate::RegisterSpec for HP_FORCE_NORST0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_force_norst0::R`](R) reader structure"] +impl crate::Readable for HP_FORCE_NORST0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_force_norst0::W`](W) writer structure"] +impl crate::Writable for HP_FORCE_NORST0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_FORCE_NORST0 to value 0"] +impl crate::Resettable for HP_FORCE_NORST0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/hp_force_norst1.rs b/esp32p4/src/hp_sys_clkrst/hp_force_norst1.rs new file mode 100644 index 0000000000..eb925b4183 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/hp_force_norst1.rs @@ -0,0 +1,570 @@ +#[doc = "Register `HP_FORCE_NORST1` reader"] +pub type R = crate::R; +#[doc = "Register `HP_FORCE_NORST1` writer"] +pub type W = crate::W; +#[doc = "Field `REG_FORCE_NORST_I3CSLV` reader - Reserved"] +pub type REG_FORCE_NORST_I3CSLV_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_I3CSLV` writer - Reserved"] +pub type REG_FORCE_NORST_I3CSLV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_I2C1` reader - Reserved"] +pub type REG_FORCE_NORST_I2C1_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_I2C1` writer - Reserved"] +pub type REG_FORCE_NORST_I2C1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_I2C0` reader - Reserved"] +pub type REG_FORCE_NORST_I2C0_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_I2C0` writer - Reserved"] +pub type REG_FORCE_NORST_I2C0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_RMT` reader - Reserved"] +pub type REG_FORCE_NORST_RMT_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_RMT` writer - Reserved"] +pub type REG_FORCE_NORST_RMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_PWM0` reader - Reserved"] +pub type REG_FORCE_NORST_PWM0_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_PWM0` writer - Reserved"] +pub type REG_FORCE_NORST_PWM0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_PWM1` reader - Reserved"] +pub type REG_FORCE_NORST_PWM1_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_PWM1` writer - Reserved"] +pub type REG_FORCE_NORST_PWM1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_CAN0` reader - Reserved"] +pub type REG_FORCE_NORST_CAN0_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_CAN0` writer - Reserved"] +pub type REG_FORCE_NORST_CAN0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_CAN1` reader - Reserved"] +pub type REG_FORCE_NORST_CAN1_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_CAN1` writer - Reserved"] +pub type REG_FORCE_NORST_CAN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_CAN2` reader - Reserved"] +pub type REG_FORCE_NORST_CAN2_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_CAN2` writer - Reserved"] +pub type REG_FORCE_NORST_CAN2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_LEDC` reader - Reserved"] +pub type REG_FORCE_NORST_LEDC_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_LEDC` writer - Reserved"] +pub type REG_FORCE_NORST_LEDC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_PCNT` reader - Reserved"] +pub type REG_FORCE_NORST_PCNT_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_PCNT` writer - Reserved"] +pub type REG_FORCE_NORST_PCNT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_ETM` reader - Reserved"] +pub type REG_FORCE_NORST_ETM_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_ETM` writer - Reserved"] +pub type REG_FORCE_NORST_ETM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_INTRMTX` reader - Reserved"] +pub type REG_FORCE_NORST_INTRMTX_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_INTRMTX` writer - Reserved"] +pub type REG_FORCE_NORST_INTRMTX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_PARLIO` reader - Reserved"] +pub type REG_FORCE_NORST_PARLIO_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_PARLIO` writer - Reserved"] +pub type REG_FORCE_NORST_PARLIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_PARLIO_RX` reader - Reserved"] +pub type REG_FORCE_NORST_PARLIO_RX_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_PARLIO_RX` writer - Reserved"] +pub type REG_FORCE_NORST_PARLIO_RX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_PARLIO_TX` reader - Reserved"] +pub type REG_FORCE_NORST_PARLIO_TX_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_PARLIO_TX` writer - Reserved"] +pub type REG_FORCE_NORST_PARLIO_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_I2S0` reader - Reserved"] +pub type REG_FORCE_NORST_I2S0_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_I2S0` writer - Reserved"] +pub type REG_FORCE_NORST_I2S0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_I2S1` reader - Reserved"] +pub type REG_FORCE_NORST_I2S1_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_I2S1` writer - Reserved"] +pub type REG_FORCE_NORST_I2S1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_I2S2` reader - Reserved"] +pub type REG_FORCE_NORST_I2S2_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_I2S2` writer - Reserved"] +pub type REG_FORCE_NORST_I2S2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_SPI2` reader - Reserved"] +pub type REG_FORCE_NORST_SPI2_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_SPI2` writer - Reserved"] +pub type REG_FORCE_NORST_SPI2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_SPI3` reader - Reserved"] +pub type REG_FORCE_NORST_SPI3_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_SPI3` writer - Reserved"] +pub type REG_FORCE_NORST_SPI3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_LCDCAM` reader - Reserved"] +pub type REG_FORCE_NORST_LCDCAM_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_LCDCAM` writer - Reserved"] +pub type REG_FORCE_NORST_LCDCAM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_ADC` reader - Reserved"] +pub type REG_FORCE_NORST_ADC_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_ADC` writer - Reserved"] +pub type REG_FORCE_NORST_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_BITSRAMBLER` reader - Reserved"] +pub type REG_FORCE_NORST_BITSRAMBLER_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_BITSRAMBLER` writer - Reserved"] +pub type REG_FORCE_NORST_BITSRAMBLER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_BITSRAMBLER_RX` reader - Reserved"] +pub type REG_FORCE_NORST_BITSRAMBLER_RX_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_BITSRAMBLER_RX` writer - Reserved"] +pub type REG_FORCE_NORST_BITSRAMBLER_RX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_BITSRAMBLER_TX` reader - Reserved"] +pub type REG_FORCE_NORST_BITSRAMBLER_TX_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_BITSRAMBLER_TX` writer - Reserved"] +pub type REG_FORCE_NORST_BITSRAMBLER_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FORCE_NORST_H264` reader - Reserved"] +pub type REG_FORCE_NORST_H264_R = crate::BitReader; +#[doc = "Field `REG_FORCE_NORST_H264` writer - Reserved"] +pub type REG_FORCE_NORST_H264_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_i3cslv(&self) -> REG_FORCE_NORST_I3CSLV_R { + REG_FORCE_NORST_I3CSLV_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_i2c1(&self) -> REG_FORCE_NORST_I2C1_R { + REG_FORCE_NORST_I2C1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_i2c0(&self) -> REG_FORCE_NORST_I2C0_R { + REG_FORCE_NORST_I2C0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_rmt(&self) -> REG_FORCE_NORST_RMT_R { + REG_FORCE_NORST_RMT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_pwm0(&self) -> REG_FORCE_NORST_PWM0_R { + REG_FORCE_NORST_PWM0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_pwm1(&self) -> REG_FORCE_NORST_PWM1_R { + REG_FORCE_NORST_PWM1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_can0(&self) -> REG_FORCE_NORST_CAN0_R { + REG_FORCE_NORST_CAN0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_can1(&self) -> REG_FORCE_NORST_CAN1_R { + REG_FORCE_NORST_CAN1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_can2(&self) -> REG_FORCE_NORST_CAN2_R { + REG_FORCE_NORST_CAN2_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_ledc(&self) -> REG_FORCE_NORST_LEDC_R { + REG_FORCE_NORST_LEDC_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_pcnt(&self) -> REG_FORCE_NORST_PCNT_R { + REG_FORCE_NORST_PCNT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_etm(&self) -> REG_FORCE_NORST_ETM_R { + REG_FORCE_NORST_ETM_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_intrmtx(&self) -> REG_FORCE_NORST_INTRMTX_R { + REG_FORCE_NORST_INTRMTX_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_parlio(&self) -> REG_FORCE_NORST_PARLIO_R { + REG_FORCE_NORST_PARLIO_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_parlio_rx(&self) -> REG_FORCE_NORST_PARLIO_RX_R { + REG_FORCE_NORST_PARLIO_RX_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_parlio_tx(&self) -> REG_FORCE_NORST_PARLIO_TX_R { + REG_FORCE_NORST_PARLIO_TX_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_i2s0(&self) -> REG_FORCE_NORST_I2S0_R { + REG_FORCE_NORST_I2S0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_i2s1(&self) -> REG_FORCE_NORST_I2S1_R { + REG_FORCE_NORST_I2S1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_i2s2(&self) -> REG_FORCE_NORST_I2S2_R { + REG_FORCE_NORST_I2S2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_spi2(&self) -> REG_FORCE_NORST_SPI2_R { + REG_FORCE_NORST_SPI2_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_spi3(&self) -> REG_FORCE_NORST_SPI3_R { + REG_FORCE_NORST_SPI3_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_lcdcam(&self) -> REG_FORCE_NORST_LCDCAM_R { + REG_FORCE_NORST_LCDCAM_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_adc(&self) -> REG_FORCE_NORST_ADC_R { + REG_FORCE_NORST_ADC_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_bitsrambler(&self) -> REG_FORCE_NORST_BITSRAMBLER_R { + REG_FORCE_NORST_BITSRAMBLER_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_bitsrambler_rx(&self) -> REG_FORCE_NORST_BITSRAMBLER_RX_R { + REG_FORCE_NORST_BITSRAMBLER_RX_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_bitsrambler_tx(&self) -> REG_FORCE_NORST_BITSRAMBLER_TX_R { + REG_FORCE_NORST_BITSRAMBLER_TX_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_force_norst_h264(&self) -> REG_FORCE_NORST_H264_R { + REG_FORCE_NORST_H264_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_FORCE_NORST1") + .field( + "reg_force_norst_i3cslv", + &format_args!("{}", self.reg_force_norst_i3cslv().bit()), + ) + .field( + "reg_force_norst_i2c1", + &format_args!("{}", self.reg_force_norst_i2c1().bit()), + ) + .field( + "reg_force_norst_i2c0", + &format_args!("{}", self.reg_force_norst_i2c0().bit()), + ) + .field( + "reg_force_norst_rmt", + &format_args!("{}", self.reg_force_norst_rmt().bit()), + ) + .field( + "reg_force_norst_pwm0", + &format_args!("{}", self.reg_force_norst_pwm0().bit()), + ) + .field( + "reg_force_norst_pwm1", + &format_args!("{}", self.reg_force_norst_pwm1().bit()), + ) + .field( + "reg_force_norst_can0", + &format_args!("{}", self.reg_force_norst_can0().bit()), + ) + .field( + "reg_force_norst_can1", + &format_args!("{}", self.reg_force_norst_can1().bit()), + ) + .field( + "reg_force_norst_can2", + &format_args!("{}", self.reg_force_norst_can2().bit()), + ) + .field( + "reg_force_norst_ledc", + &format_args!("{}", self.reg_force_norst_ledc().bit()), + ) + .field( + "reg_force_norst_pcnt", + &format_args!("{}", self.reg_force_norst_pcnt().bit()), + ) + .field( + "reg_force_norst_etm", + &format_args!("{}", self.reg_force_norst_etm().bit()), + ) + .field( + "reg_force_norst_intrmtx", + &format_args!("{}", self.reg_force_norst_intrmtx().bit()), + ) + .field( + "reg_force_norst_parlio", + &format_args!("{}", self.reg_force_norst_parlio().bit()), + ) + .field( + "reg_force_norst_parlio_rx", + &format_args!("{}", self.reg_force_norst_parlio_rx().bit()), + ) + .field( + "reg_force_norst_parlio_tx", + &format_args!("{}", self.reg_force_norst_parlio_tx().bit()), + ) + .field( + "reg_force_norst_i2s0", + &format_args!("{}", self.reg_force_norst_i2s0().bit()), + ) + .field( + "reg_force_norst_i2s1", + &format_args!("{}", self.reg_force_norst_i2s1().bit()), + ) + .field( + "reg_force_norst_i2s2", + &format_args!("{}", self.reg_force_norst_i2s2().bit()), + ) + .field( + "reg_force_norst_spi2", + &format_args!("{}", self.reg_force_norst_spi2().bit()), + ) + .field( + "reg_force_norst_spi3", + &format_args!("{}", self.reg_force_norst_spi3().bit()), + ) + .field( + "reg_force_norst_lcdcam", + &format_args!("{}", self.reg_force_norst_lcdcam().bit()), + ) + .field( + "reg_force_norst_adc", + &format_args!("{}", self.reg_force_norst_adc().bit()), + ) + .field( + "reg_force_norst_bitsrambler", + &format_args!("{}", self.reg_force_norst_bitsrambler().bit()), + ) + .field( + "reg_force_norst_bitsrambler_rx", + &format_args!("{}", self.reg_force_norst_bitsrambler_rx().bit()), + ) + .field( + "reg_force_norst_bitsrambler_tx", + &format_args!("{}", self.reg_force_norst_bitsrambler_tx().bit()), + ) + .field( + "reg_force_norst_h264", + &format_args!("{}", self.reg_force_norst_h264().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_i3cslv(&mut self) -> REG_FORCE_NORST_I3CSLV_W { + REG_FORCE_NORST_I3CSLV_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_i2c1(&mut self) -> REG_FORCE_NORST_I2C1_W { + REG_FORCE_NORST_I2C1_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_i2c0(&mut self) -> REG_FORCE_NORST_I2C0_W { + REG_FORCE_NORST_I2C0_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_rmt(&mut self) -> REG_FORCE_NORST_RMT_W { + REG_FORCE_NORST_RMT_W::new(self, 3) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_pwm0(&mut self) -> REG_FORCE_NORST_PWM0_W { + REG_FORCE_NORST_PWM0_W::new(self, 4) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_pwm1(&mut self) -> REG_FORCE_NORST_PWM1_W { + REG_FORCE_NORST_PWM1_W::new(self, 5) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_can0(&mut self) -> REG_FORCE_NORST_CAN0_W { + REG_FORCE_NORST_CAN0_W::new(self, 6) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_can1(&mut self) -> REG_FORCE_NORST_CAN1_W { + REG_FORCE_NORST_CAN1_W::new(self, 7) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_can2(&mut self) -> REG_FORCE_NORST_CAN2_W { + REG_FORCE_NORST_CAN2_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_ledc(&mut self) -> REG_FORCE_NORST_LEDC_W { + REG_FORCE_NORST_LEDC_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_pcnt(&mut self) -> REG_FORCE_NORST_PCNT_W { + REG_FORCE_NORST_PCNT_W::new(self, 10) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_etm(&mut self) -> REG_FORCE_NORST_ETM_W { + REG_FORCE_NORST_ETM_W::new(self, 11) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_intrmtx(&mut self) -> REG_FORCE_NORST_INTRMTX_W { + REG_FORCE_NORST_INTRMTX_W::new(self, 12) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_parlio(&mut self) -> REG_FORCE_NORST_PARLIO_W { + REG_FORCE_NORST_PARLIO_W::new(self, 13) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_parlio_rx( + &mut self, + ) -> REG_FORCE_NORST_PARLIO_RX_W { + REG_FORCE_NORST_PARLIO_RX_W::new(self, 14) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_parlio_tx( + &mut self, + ) -> REG_FORCE_NORST_PARLIO_TX_W { + REG_FORCE_NORST_PARLIO_TX_W::new(self, 15) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_i2s0(&mut self) -> REG_FORCE_NORST_I2S0_W { + REG_FORCE_NORST_I2S0_W::new(self, 16) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_i2s1(&mut self) -> REG_FORCE_NORST_I2S1_W { + REG_FORCE_NORST_I2S1_W::new(self, 17) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_i2s2(&mut self) -> REG_FORCE_NORST_I2S2_W { + REG_FORCE_NORST_I2S2_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_spi2(&mut self) -> REG_FORCE_NORST_SPI2_W { + REG_FORCE_NORST_SPI2_W::new(self, 19) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_spi3(&mut self) -> REG_FORCE_NORST_SPI3_W { + REG_FORCE_NORST_SPI3_W::new(self, 20) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_lcdcam(&mut self) -> REG_FORCE_NORST_LCDCAM_W { + REG_FORCE_NORST_LCDCAM_W::new(self, 21) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_adc(&mut self) -> REG_FORCE_NORST_ADC_W { + REG_FORCE_NORST_ADC_W::new(self, 22) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_bitsrambler( + &mut self, + ) -> REG_FORCE_NORST_BITSRAMBLER_W { + REG_FORCE_NORST_BITSRAMBLER_W::new(self, 23) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_bitsrambler_rx( + &mut self, + ) -> REG_FORCE_NORST_BITSRAMBLER_RX_W { + REG_FORCE_NORST_BITSRAMBLER_RX_W::new(self, 24) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_bitsrambler_tx( + &mut self, + ) -> REG_FORCE_NORST_BITSRAMBLER_TX_W { + REG_FORCE_NORST_BITSRAMBLER_TX_W::new(self, 25) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_force_norst_h264(&mut self) -> REG_FORCE_NORST_H264_W { + REG_FORCE_NORST_H264_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_force_norst1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_force_norst1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_FORCE_NORST1_SPEC; +impl crate::RegisterSpec for HP_FORCE_NORST1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_force_norst1::R`](R) reader structure"] +impl crate::Readable for HP_FORCE_NORST1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_force_norst1::W`](W) writer structure"] +impl crate::Writable for HP_FORCE_NORST1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_FORCE_NORST1 to value 0"] +impl crate::Resettable for HP_FORCE_NORST1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/hp_rst_en0.rs b/esp32p4/src/hp_sys_clkrst/hp_rst_en0.rs new file mode 100644 index 0000000000..a078472294 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/hp_rst_en0.rs @@ -0,0 +1,655 @@ +#[doc = "Register `HP_RST_EN0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_RST_EN0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_RST_EN_CORECTRL` reader - Reserved"] +pub type REG_RST_EN_CORECTRL_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_CORECTRL` writer - Reserved"] +pub type REG_RST_EN_CORECTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PVT_TOP` reader - Reserved"] +pub type REG_RST_EN_PVT_TOP_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PVT_TOP` writer - Reserved"] +pub type REG_RST_EN_PVT_TOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PVT_PERI_GROUP1` reader - Reserved"] +pub type REG_RST_EN_PVT_PERI_GROUP1_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PVT_PERI_GROUP1` writer - Reserved"] +pub type REG_RST_EN_PVT_PERI_GROUP1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PVT_PERI_GROUP2` reader - Reserved"] +pub type REG_RST_EN_PVT_PERI_GROUP2_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PVT_PERI_GROUP2` writer - Reserved"] +pub type REG_RST_EN_PVT_PERI_GROUP2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PVT_PERI_GROUP3` reader - Reserved"] +pub type REG_RST_EN_PVT_PERI_GROUP3_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PVT_PERI_GROUP3` writer - Reserved"] +pub type REG_RST_EN_PVT_PERI_GROUP3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PVT_PERI_GROUP4` reader - Reserved"] +pub type REG_RST_EN_PVT_PERI_GROUP4_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PVT_PERI_GROUP4` writer - Reserved"] +pub type REG_RST_EN_PVT_PERI_GROUP4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_REGDMA` reader - Reserved"] +pub type REG_RST_EN_REGDMA_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_REGDMA` writer - Reserved"] +pub type REG_RST_EN_REGDMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_CORE0_GLOBAL` reader - Reserved"] +pub type REG_RST_EN_CORE0_GLOBAL_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_CORE0_GLOBAL` writer - Reserved"] +pub type REG_RST_EN_CORE0_GLOBAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_CORE1_GLOBAL` reader - Reserved"] +pub type REG_RST_EN_CORE1_GLOBAL_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_CORE1_GLOBAL` writer - Reserved"] +pub type REG_RST_EN_CORE1_GLOBAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_CORETRACE0` reader - Reserved"] +pub type REG_RST_EN_CORETRACE0_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_CORETRACE0` writer - Reserved"] +pub type REG_RST_EN_CORETRACE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_CORETRACE1` reader - Reserved"] +pub type REG_RST_EN_CORETRACE1_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_CORETRACE1` writer - Reserved"] +pub type REG_RST_EN_CORETRACE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_HP_TCM` reader - Reserved"] +pub type REG_RST_EN_HP_TCM_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_HP_TCM` writer - Reserved"] +pub type REG_RST_EN_HP_TCM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_HP_CACHE` reader - Reserved"] +pub type REG_RST_EN_HP_CACHE_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_HP_CACHE` writer - Reserved"] +pub type REG_RST_EN_HP_CACHE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_L1_I0_CACHE` reader - Reserved"] +pub type REG_RST_EN_L1_I0_CACHE_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_L1_I0_CACHE` writer - Reserved"] +pub type REG_RST_EN_L1_I0_CACHE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_L1_I1_CACHE` reader - Reserved"] +pub type REG_RST_EN_L1_I1_CACHE_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_L1_I1_CACHE` writer - Reserved"] +pub type REG_RST_EN_L1_I1_CACHE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_L1_D_CACHE` reader - Reserved"] +pub type REG_RST_EN_L1_D_CACHE_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_L1_D_CACHE` writer - Reserved"] +pub type REG_RST_EN_L1_D_CACHE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_L2_CACHE` reader - Reserved"] +pub type REG_RST_EN_L2_CACHE_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_L2_CACHE` writer - Reserved"] +pub type REG_RST_EN_L2_CACHE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_L2_MEM` reader - Reserved"] +pub type REG_RST_EN_L2_MEM_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_L2_MEM` writer - Reserved"] +pub type REG_RST_EN_L2_MEM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_L2MEMMON` reader - Reserved"] +pub type REG_RST_EN_L2MEMMON_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_L2MEMMON` writer - Reserved"] +pub type REG_RST_EN_L2MEMMON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_TCMMON` reader - Reserved"] +pub type REG_RST_EN_TCMMON_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_TCMMON` writer - Reserved"] +pub type REG_RST_EN_TCMMON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PVT_APB` reader - Reserved"] +pub type REG_RST_EN_PVT_APB_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PVT_APB` writer - Reserved"] +pub type REG_RST_EN_PVT_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_GDMA` reader - Reserved"] +pub type REG_RST_EN_GDMA_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_GDMA` writer - Reserved"] +pub type REG_RST_EN_GDMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_MSPI_AXI` reader - Reserved"] +pub type REG_RST_EN_MSPI_AXI_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_MSPI_AXI` writer - Reserved"] +pub type REG_RST_EN_MSPI_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_DUAL_MSPI_AXI` reader - Reserved"] +pub type REG_RST_EN_DUAL_MSPI_AXI_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_DUAL_MSPI_AXI` writer - Reserved"] +pub type REG_RST_EN_DUAL_MSPI_AXI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_MSPI_APB` reader - Reserved"] +pub type REG_RST_EN_MSPI_APB_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_MSPI_APB` writer - Reserved"] +pub type REG_RST_EN_MSPI_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_DUAL_MSPI_APB` reader - Reserved"] +pub type REG_RST_EN_DUAL_MSPI_APB_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_DUAL_MSPI_APB` writer - Reserved"] +pub type REG_RST_EN_DUAL_MSPI_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_DSI_BRG` reader - Reserved"] +pub type REG_RST_EN_DSI_BRG_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_DSI_BRG` writer - Reserved"] +pub type REG_RST_EN_DSI_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_CSI_HOST` reader - Reserved"] +pub type REG_RST_EN_CSI_HOST_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_CSI_HOST` writer - Reserved"] +pub type REG_RST_EN_CSI_HOST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_CSI_BRG` reader - Reserved"] +pub type REG_RST_EN_CSI_BRG_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_CSI_BRG` writer - Reserved"] +pub type REG_RST_EN_CSI_BRG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_ISP` reader - Reserved"] +pub type REG_RST_EN_ISP_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_ISP` writer - Reserved"] +pub type REG_RST_EN_ISP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_JPEG` reader - Reserved"] +pub type REG_RST_EN_JPEG_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_JPEG` writer - Reserved"] +pub type REG_RST_EN_JPEG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_DMA2D` reader - Reserved"] +pub type REG_RST_EN_DMA2D_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_DMA2D` writer - Reserved"] +pub type REG_RST_EN_DMA2D_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_corectrl(&self) -> REG_RST_EN_CORECTRL_R { + REG_RST_EN_CORECTRL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_pvt_top(&self) -> REG_RST_EN_PVT_TOP_R { + REG_RST_EN_PVT_TOP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_pvt_peri_group1(&self) -> REG_RST_EN_PVT_PERI_GROUP1_R { + REG_RST_EN_PVT_PERI_GROUP1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_pvt_peri_group2(&self) -> REG_RST_EN_PVT_PERI_GROUP2_R { + REG_RST_EN_PVT_PERI_GROUP2_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_pvt_peri_group3(&self) -> REG_RST_EN_PVT_PERI_GROUP3_R { + REG_RST_EN_PVT_PERI_GROUP3_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_pvt_peri_group4(&self) -> REG_RST_EN_PVT_PERI_GROUP4_R { + REG_RST_EN_PVT_PERI_GROUP4_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_regdma(&self) -> REG_RST_EN_REGDMA_R { + REG_RST_EN_REGDMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_core0_global(&self) -> REG_RST_EN_CORE0_GLOBAL_R { + REG_RST_EN_CORE0_GLOBAL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_core1_global(&self) -> REG_RST_EN_CORE1_GLOBAL_R { + REG_RST_EN_CORE1_GLOBAL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_coretrace0(&self) -> REG_RST_EN_CORETRACE0_R { + REG_RST_EN_CORETRACE0_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_coretrace1(&self) -> REG_RST_EN_CORETRACE1_R { + REG_RST_EN_CORETRACE1_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_hp_tcm(&self) -> REG_RST_EN_HP_TCM_R { + REG_RST_EN_HP_TCM_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_hp_cache(&self) -> REG_RST_EN_HP_CACHE_R { + REG_RST_EN_HP_CACHE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_l1_i0_cache(&self) -> REG_RST_EN_L1_I0_CACHE_R { + REG_RST_EN_L1_I0_CACHE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_l1_i1_cache(&self) -> REG_RST_EN_L1_I1_CACHE_R { + REG_RST_EN_L1_I1_CACHE_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_l1_d_cache(&self) -> REG_RST_EN_L1_D_CACHE_R { + REG_RST_EN_L1_D_CACHE_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_l2_cache(&self) -> REG_RST_EN_L2_CACHE_R { + REG_RST_EN_L2_CACHE_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_l2_mem(&self) -> REG_RST_EN_L2_MEM_R { + REG_RST_EN_L2_MEM_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_l2memmon(&self) -> REG_RST_EN_L2MEMMON_R { + REG_RST_EN_L2MEMMON_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_tcmmon(&self) -> REG_RST_EN_TCMMON_R { + REG_RST_EN_TCMMON_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_pvt_apb(&self) -> REG_RST_EN_PVT_APB_R { + REG_RST_EN_PVT_APB_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_gdma(&self) -> REG_RST_EN_GDMA_R { + REG_RST_EN_GDMA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_mspi_axi(&self) -> REG_RST_EN_MSPI_AXI_R { + REG_RST_EN_MSPI_AXI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_dual_mspi_axi(&self) -> REG_RST_EN_DUAL_MSPI_AXI_R { + REG_RST_EN_DUAL_MSPI_AXI_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_mspi_apb(&self) -> REG_RST_EN_MSPI_APB_R { + REG_RST_EN_MSPI_APB_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_dual_mspi_apb(&self) -> REG_RST_EN_DUAL_MSPI_APB_R { + REG_RST_EN_DUAL_MSPI_APB_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_dsi_brg(&self) -> REG_RST_EN_DSI_BRG_R { + REG_RST_EN_DSI_BRG_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_csi_host(&self) -> REG_RST_EN_CSI_HOST_R { + REG_RST_EN_CSI_HOST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_csi_brg(&self) -> REG_RST_EN_CSI_BRG_R { + REG_RST_EN_CSI_BRG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_isp(&self) -> REG_RST_EN_ISP_R { + REG_RST_EN_ISP_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_jpeg(&self) -> REG_RST_EN_JPEG_R { + REG_RST_EN_JPEG_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_dma2d(&self) -> REG_RST_EN_DMA2D_R { + REG_RST_EN_DMA2D_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_RST_EN0") + .field( + "reg_rst_en_corectrl", + &format_args!("{}", self.reg_rst_en_corectrl().bit()), + ) + .field( + "reg_rst_en_pvt_top", + &format_args!("{}", self.reg_rst_en_pvt_top().bit()), + ) + .field( + "reg_rst_en_pvt_peri_group1", + &format_args!("{}", self.reg_rst_en_pvt_peri_group1().bit()), + ) + .field( + "reg_rst_en_pvt_peri_group2", + &format_args!("{}", self.reg_rst_en_pvt_peri_group2().bit()), + ) + .field( + "reg_rst_en_pvt_peri_group3", + &format_args!("{}", self.reg_rst_en_pvt_peri_group3().bit()), + ) + .field( + "reg_rst_en_pvt_peri_group4", + &format_args!("{}", self.reg_rst_en_pvt_peri_group4().bit()), + ) + .field( + "reg_rst_en_regdma", + &format_args!("{}", self.reg_rst_en_regdma().bit()), + ) + .field( + "reg_rst_en_core0_global", + &format_args!("{}", self.reg_rst_en_core0_global().bit()), + ) + .field( + "reg_rst_en_core1_global", + &format_args!("{}", self.reg_rst_en_core1_global().bit()), + ) + .field( + "reg_rst_en_coretrace0", + &format_args!("{}", self.reg_rst_en_coretrace0().bit()), + ) + .field( + "reg_rst_en_coretrace1", + &format_args!("{}", self.reg_rst_en_coretrace1().bit()), + ) + .field( + "reg_rst_en_hp_tcm", + &format_args!("{}", self.reg_rst_en_hp_tcm().bit()), + ) + .field( + "reg_rst_en_hp_cache", + &format_args!("{}", self.reg_rst_en_hp_cache().bit()), + ) + .field( + "reg_rst_en_l1_i0_cache", + &format_args!("{}", self.reg_rst_en_l1_i0_cache().bit()), + ) + .field( + "reg_rst_en_l1_i1_cache", + &format_args!("{}", self.reg_rst_en_l1_i1_cache().bit()), + ) + .field( + "reg_rst_en_l1_d_cache", + &format_args!("{}", self.reg_rst_en_l1_d_cache().bit()), + ) + .field( + "reg_rst_en_l2_cache", + &format_args!("{}", self.reg_rst_en_l2_cache().bit()), + ) + .field( + "reg_rst_en_l2_mem", + &format_args!("{}", self.reg_rst_en_l2_mem().bit()), + ) + .field( + "reg_rst_en_l2memmon", + &format_args!("{}", self.reg_rst_en_l2memmon().bit()), + ) + .field( + "reg_rst_en_tcmmon", + &format_args!("{}", self.reg_rst_en_tcmmon().bit()), + ) + .field( + "reg_rst_en_pvt_apb", + &format_args!("{}", self.reg_rst_en_pvt_apb().bit()), + ) + .field( + "reg_rst_en_gdma", + &format_args!("{}", self.reg_rst_en_gdma().bit()), + ) + .field( + "reg_rst_en_mspi_axi", + &format_args!("{}", self.reg_rst_en_mspi_axi().bit()), + ) + .field( + "reg_rst_en_dual_mspi_axi", + &format_args!("{}", self.reg_rst_en_dual_mspi_axi().bit()), + ) + .field( + "reg_rst_en_mspi_apb", + &format_args!("{}", self.reg_rst_en_mspi_apb().bit()), + ) + .field( + "reg_rst_en_dual_mspi_apb", + &format_args!("{}", self.reg_rst_en_dual_mspi_apb().bit()), + ) + .field( + "reg_rst_en_dsi_brg", + &format_args!("{}", self.reg_rst_en_dsi_brg().bit()), + ) + .field( + "reg_rst_en_csi_host", + &format_args!("{}", self.reg_rst_en_csi_host().bit()), + ) + .field( + "reg_rst_en_csi_brg", + &format_args!("{}", self.reg_rst_en_csi_brg().bit()), + ) + .field( + "reg_rst_en_isp", + &format_args!("{}", self.reg_rst_en_isp().bit()), + ) + .field( + "reg_rst_en_jpeg", + &format_args!("{}", self.reg_rst_en_jpeg().bit()), + ) + .field( + "reg_rst_en_dma2d", + &format_args!("{}", self.reg_rst_en_dma2d().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_corectrl(&mut self) -> REG_RST_EN_CORECTRL_W { + REG_RST_EN_CORECTRL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_pvt_top(&mut self) -> REG_RST_EN_PVT_TOP_W { + REG_RST_EN_PVT_TOP_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_pvt_peri_group1(&mut self) -> REG_RST_EN_PVT_PERI_GROUP1_W { + REG_RST_EN_PVT_PERI_GROUP1_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_pvt_peri_group2(&mut self) -> REG_RST_EN_PVT_PERI_GROUP2_W { + REG_RST_EN_PVT_PERI_GROUP2_W::new(self, 3) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_pvt_peri_group3(&mut self) -> REG_RST_EN_PVT_PERI_GROUP3_W { + REG_RST_EN_PVT_PERI_GROUP3_W::new(self, 4) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_pvt_peri_group4(&mut self) -> REG_RST_EN_PVT_PERI_GROUP4_W { + REG_RST_EN_PVT_PERI_GROUP4_W::new(self, 5) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_regdma(&mut self) -> REG_RST_EN_REGDMA_W { + REG_RST_EN_REGDMA_W::new(self, 6) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_core0_global(&mut self) -> REG_RST_EN_CORE0_GLOBAL_W { + REG_RST_EN_CORE0_GLOBAL_W::new(self, 7) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_core1_global(&mut self) -> REG_RST_EN_CORE1_GLOBAL_W { + REG_RST_EN_CORE1_GLOBAL_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_coretrace0(&mut self) -> REG_RST_EN_CORETRACE0_W { + REG_RST_EN_CORETRACE0_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_coretrace1(&mut self) -> REG_RST_EN_CORETRACE1_W { + REG_RST_EN_CORETRACE1_W::new(self, 10) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_hp_tcm(&mut self) -> REG_RST_EN_HP_TCM_W { + REG_RST_EN_HP_TCM_W::new(self, 11) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_hp_cache(&mut self) -> REG_RST_EN_HP_CACHE_W { + REG_RST_EN_HP_CACHE_W::new(self, 12) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_l1_i0_cache(&mut self) -> REG_RST_EN_L1_I0_CACHE_W { + REG_RST_EN_L1_I0_CACHE_W::new(self, 13) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_l1_i1_cache(&mut self) -> REG_RST_EN_L1_I1_CACHE_W { + REG_RST_EN_L1_I1_CACHE_W::new(self, 14) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_l1_d_cache(&mut self) -> REG_RST_EN_L1_D_CACHE_W { + REG_RST_EN_L1_D_CACHE_W::new(self, 15) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_l2_cache(&mut self) -> REG_RST_EN_L2_CACHE_W { + REG_RST_EN_L2_CACHE_W::new(self, 16) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_l2_mem(&mut self) -> REG_RST_EN_L2_MEM_W { + REG_RST_EN_L2_MEM_W::new(self, 17) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_l2memmon(&mut self) -> REG_RST_EN_L2MEMMON_W { + REG_RST_EN_L2MEMMON_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_tcmmon(&mut self) -> REG_RST_EN_TCMMON_W { + REG_RST_EN_TCMMON_W::new(self, 19) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_pvt_apb(&mut self) -> REG_RST_EN_PVT_APB_W { + REG_RST_EN_PVT_APB_W::new(self, 20) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_gdma(&mut self) -> REG_RST_EN_GDMA_W { + REG_RST_EN_GDMA_W::new(self, 21) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_mspi_axi(&mut self) -> REG_RST_EN_MSPI_AXI_W { + REG_RST_EN_MSPI_AXI_W::new(self, 22) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_dual_mspi_axi(&mut self) -> REG_RST_EN_DUAL_MSPI_AXI_W { + REG_RST_EN_DUAL_MSPI_AXI_W::new(self, 23) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_mspi_apb(&mut self) -> REG_RST_EN_MSPI_APB_W { + REG_RST_EN_MSPI_APB_W::new(self, 24) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_dual_mspi_apb(&mut self) -> REG_RST_EN_DUAL_MSPI_APB_W { + REG_RST_EN_DUAL_MSPI_APB_W::new(self, 25) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_dsi_brg(&mut self) -> REG_RST_EN_DSI_BRG_W { + REG_RST_EN_DSI_BRG_W::new(self, 26) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_csi_host(&mut self) -> REG_RST_EN_CSI_HOST_W { + REG_RST_EN_CSI_HOST_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_csi_brg(&mut self) -> REG_RST_EN_CSI_BRG_W { + REG_RST_EN_CSI_BRG_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_isp(&mut self) -> REG_RST_EN_ISP_W { + REG_RST_EN_ISP_W::new(self, 29) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_jpeg(&mut self) -> REG_RST_EN_JPEG_W { + REG_RST_EN_JPEG_W::new(self, 30) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_dma2d(&mut self) -> REG_RST_EN_DMA2D_W { + REG_RST_EN_DMA2D_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rst_en0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rst_en0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_RST_EN0_SPEC; +impl crate::RegisterSpec for HP_RST_EN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_rst_en0::R`](R) reader structure"] +impl crate::Readable for HP_RST_EN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_rst_en0::W`](W) writer structure"] +impl crate::Writable for HP_RST_EN0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_RST_EN0 to value 0x0100"] +impl crate::Resettable for HP_RST_EN0_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/hp_sys_clkrst/hp_rst_en1.rs b/esp32p4/src/hp_sys_clkrst/hp_rst_en1.rs new file mode 100644 index 0000000000..73ed03ae18 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/hp_rst_en1.rs @@ -0,0 +1,655 @@ +#[doc = "Register `HP_RST_EN1` reader"] +pub type R = crate::R; +#[doc = "Register `HP_RST_EN1` writer"] +pub type W = crate::W; +#[doc = "Field `REG_RST_EN_PPA` reader - Reserved"] +pub type REG_RST_EN_PPA_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PPA` writer - Reserved"] +pub type REG_RST_EN_PPA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_AHB_PDMA` reader - Reserved"] +pub type REG_RST_EN_AHB_PDMA_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_AHB_PDMA` writer - Reserved"] +pub type REG_RST_EN_AHB_PDMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_AXI_PDMA` reader - Reserved"] +pub type REG_RST_EN_AXI_PDMA_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_AXI_PDMA` writer - Reserved"] +pub type REG_RST_EN_AXI_PDMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_IOMUX` reader - Reserved"] +pub type REG_RST_EN_IOMUX_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_IOMUX` writer - Reserved"] +pub type REG_RST_EN_IOMUX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PADBIST` reader - Reserved"] +pub type REG_RST_EN_PADBIST_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PADBIST` writer - Reserved"] +pub type REG_RST_EN_PADBIST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_STIMER` reader - Reserved"] +pub type REG_RST_EN_STIMER_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_STIMER` writer - Reserved"] +pub type REG_RST_EN_STIMER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_TIMERGRP0` reader - Reserved"] +pub type REG_RST_EN_TIMERGRP0_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_TIMERGRP0` writer - Reserved"] +pub type REG_RST_EN_TIMERGRP0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_TIMERGRP1` reader - Reserved"] +pub type REG_RST_EN_TIMERGRP1_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_TIMERGRP1` writer - Reserved"] +pub type REG_RST_EN_TIMERGRP1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_UART0_CORE` reader - Reserved"] +pub type REG_RST_EN_UART0_CORE_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_UART0_CORE` writer - Reserved"] +pub type REG_RST_EN_UART0_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_UART1_CORE` reader - Reserved"] +pub type REG_RST_EN_UART1_CORE_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_UART1_CORE` writer - Reserved"] +pub type REG_RST_EN_UART1_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_UART2_CORE` reader - Reserved"] +pub type REG_RST_EN_UART2_CORE_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_UART2_CORE` writer - Reserved"] +pub type REG_RST_EN_UART2_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_UART3_CORE` reader - Reserved"] +pub type REG_RST_EN_UART3_CORE_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_UART3_CORE` writer - Reserved"] +pub type REG_RST_EN_UART3_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_UART4_CORE` reader - Reserved"] +pub type REG_RST_EN_UART4_CORE_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_UART4_CORE` writer - Reserved"] +pub type REG_RST_EN_UART4_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_UART0_APB` reader - Reserved"] +pub type REG_RST_EN_UART0_APB_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_UART0_APB` writer - Reserved"] +pub type REG_RST_EN_UART0_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_UART1_APB` reader - Reserved"] +pub type REG_RST_EN_UART1_APB_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_UART1_APB` writer - Reserved"] +pub type REG_RST_EN_UART1_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_UART2_APB` reader - Reserved"] +pub type REG_RST_EN_UART2_APB_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_UART2_APB` writer - Reserved"] +pub type REG_RST_EN_UART2_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_UART3_APB` reader - Reserved"] +pub type REG_RST_EN_UART3_APB_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_UART3_APB` writer - Reserved"] +pub type REG_RST_EN_UART3_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_UART4_APB` reader - Reserved"] +pub type REG_RST_EN_UART4_APB_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_UART4_APB` writer - Reserved"] +pub type REG_RST_EN_UART4_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_UHCI` reader - Reserved"] +pub type REG_RST_EN_UHCI_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_UHCI` writer - Reserved"] +pub type REG_RST_EN_UHCI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_I3CMST` reader - Reserved"] +pub type REG_RST_EN_I3CMST_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_I3CMST` writer - Reserved"] +pub type REG_RST_EN_I3CMST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_I3CSLV` reader - Reserved"] +pub type REG_RST_EN_I3CSLV_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_I3CSLV` writer - Reserved"] +pub type REG_RST_EN_I3CSLV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_I2C1` reader - Reserved"] +pub type REG_RST_EN_I2C1_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_I2C1` writer - Reserved"] +pub type REG_RST_EN_I2C1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_I2C0` reader - Reserved"] +pub type REG_RST_EN_I2C0_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_I2C0` writer - Reserved"] +pub type REG_RST_EN_I2C0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_RMT` reader - Reserved"] +pub type REG_RST_EN_RMT_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_RMT` writer - Reserved"] +pub type REG_RST_EN_RMT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PWM0` reader - Reserved"] +pub type REG_RST_EN_PWM0_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PWM0` writer - Reserved"] +pub type REG_RST_EN_PWM0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PWM1` reader - Reserved"] +pub type REG_RST_EN_PWM1_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PWM1` writer - Reserved"] +pub type REG_RST_EN_PWM1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_CAN0` reader - Reserved"] +pub type REG_RST_EN_CAN0_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_CAN0` writer - Reserved"] +pub type REG_RST_EN_CAN0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_CAN1` reader - Reserved"] +pub type REG_RST_EN_CAN1_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_CAN1` writer - Reserved"] +pub type REG_RST_EN_CAN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_CAN2` reader - Reserved"] +pub type REG_RST_EN_CAN2_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_CAN2` writer - Reserved"] +pub type REG_RST_EN_CAN2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_LEDC` reader - Reserved"] +pub type REG_RST_EN_LEDC_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_LEDC` writer - Reserved"] +pub type REG_RST_EN_LEDC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PCNT` reader - Reserved"] +pub type REG_RST_EN_PCNT_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PCNT` writer - Reserved"] +pub type REG_RST_EN_PCNT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_ETM` reader - Reserved"] +pub type REG_RST_EN_ETM_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_ETM` writer - Reserved"] +pub type REG_RST_EN_ETM_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_ppa(&self) -> REG_RST_EN_PPA_R { + REG_RST_EN_PPA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_ahb_pdma(&self) -> REG_RST_EN_AHB_PDMA_R { + REG_RST_EN_AHB_PDMA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_axi_pdma(&self) -> REG_RST_EN_AXI_PDMA_R { + REG_RST_EN_AXI_PDMA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_iomux(&self) -> REG_RST_EN_IOMUX_R { + REG_RST_EN_IOMUX_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_padbist(&self) -> REG_RST_EN_PADBIST_R { + REG_RST_EN_PADBIST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_stimer(&self) -> REG_RST_EN_STIMER_R { + REG_RST_EN_STIMER_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_timergrp0(&self) -> REG_RST_EN_TIMERGRP0_R { + REG_RST_EN_TIMERGRP0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_timergrp1(&self) -> REG_RST_EN_TIMERGRP1_R { + REG_RST_EN_TIMERGRP1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_uart0_core(&self) -> REG_RST_EN_UART0_CORE_R { + REG_RST_EN_UART0_CORE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_uart1_core(&self) -> REG_RST_EN_UART1_CORE_R { + REG_RST_EN_UART1_CORE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_uart2_core(&self) -> REG_RST_EN_UART2_CORE_R { + REG_RST_EN_UART2_CORE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_uart3_core(&self) -> REG_RST_EN_UART3_CORE_R { + REG_RST_EN_UART3_CORE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_uart4_core(&self) -> REG_RST_EN_UART4_CORE_R { + REG_RST_EN_UART4_CORE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_uart0_apb(&self) -> REG_RST_EN_UART0_APB_R { + REG_RST_EN_UART0_APB_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_uart1_apb(&self) -> REG_RST_EN_UART1_APB_R { + REG_RST_EN_UART1_APB_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_uart2_apb(&self) -> REG_RST_EN_UART2_APB_R { + REG_RST_EN_UART2_APB_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_uart3_apb(&self) -> REG_RST_EN_UART3_APB_R { + REG_RST_EN_UART3_APB_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_uart4_apb(&self) -> REG_RST_EN_UART4_APB_R { + REG_RST_EN_UART4_APB_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_uhci(&self) -> REG_RST_EN_UHCI_R { + REG_RST_EN_UHCI_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_i3cmst(&self) -> REG_RST_EN_I3CMST_R { + REG_RST_EN_I3CMST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_i3cslv(&self) -> REG_RST_EN_I3CSLV_R { + REG_RST_EN_I3CSLV_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_i2c1(&self) -> REG_RST_EN_I2C1_R { + REG_RST_EN_I2C1_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_i2c0(&self) -> REG_RST_EN_I2C0_R { + REG_RST_EN_I2C0_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_rmt(&self) -> REG_RST_EN_RMT_R { + REG_RST_EN_RMT_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_pwm0(&self) -> REG_RST_EN_PWM0_R { + REG_RST_EN_PWM0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_pwm1(&self) -> REG_RST_EN_PWM1_R { + REG_RST_EN_PWM1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_can0(&self) -> REG_RST_EN_CAN0_R { + REG_RST_EN_CAN0_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_can1(&self) -> REG_RST_EN_CAN1_R { + REG_RST_EN_CAN1_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_can2(&self) -> REG_RST_EN_CAN2_R { + REG_RST_EN_CAN2_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_ledc(&self) -> REG_RST_EN_LEDC_R { + REG_RST_EN_LEDC_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_pcnt(&self) -> REG_RST_EN_PCNT_R { + REG_RST_EN_PCNT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_etm(&self) -> REG_RST_EN_ETM_R { + REG_RST_EN_ETM_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_RST_EN1") + .field( + "reg_rst_en_ppa", + &format_args!("{}", self.reg_rst_en_ppa().bit()), + ) + .field( + "reg_rst_en_ahb_pdma", + &format_args!("{}", self.reg_rst_en_ahb_pdma().bit()), + ) + .field( + "reg_rst_en_axi_pdma", + &format_args!("{}", self.reg_rst_en_axi_pdma().bit()), + ) + .field( + "reg_rst_en_iomux", + &format_args!("{}", self.reg_rst_en_iomux().bit()), + ) + .field( + "reg_rst_en_padbist", + &format_args!("{}", self.reg_rst_en_padbist().bit()), + ) + .field( + "reg_rst_en_stimer", + &format_args!("{}", self.reg_rst_en_stimer().bit()), + ) + .field( + "reg_rst_en_timergrp0", + &format_args!("{}", self.reg_rst_en_timergrp0().bit()), + ) + .field( + "reg_rst_en_timergrp1", + &format_args!("{}", self.reg_rst_en_timergrp1().bit()), + ) + .field( + "reg_rst_en_uart0_core", + &format_args!("{}", self.reg_rst_en_uart0_core().bit()), + ) + .field( + "reg_rst_en_uart1_core", + &format_args!("{}", self.reg_rst_en_uart1_core().bit()), + ) + .field( + "reg_rst_en_uart2_core", + &format_args!("{}", self.reg_rst_en_uart2_core().bit()), + ) + .field( + "reg_rst_en_uart3_core", + &format_args!("{}", self.reg_rst_en_uart3_core().bit()), + ) + .field( + "reg_rst_en_uart4_core", + &format_args!("{}", self.reg_rst_en_uart4_core().bit()), + ) + .field( + "reg_rst_en_uart0_apb", + &format_args!("{}", self.reg_rst_en_uart0_apb().bit()), + ) + .field( + "reg_rst_en_uart1_apb", + &format_args!("{}", self.reg_rst_en_uart1_apb().bit()), + ) + .field( + "reg_rst_en_uart2_apb", + &format_args!("{}", self.reg_rst_en_uart2_apb().bit()), + ) + .field( + "reg_rst_en_uart3_apb", + &format_args!("{}", self.reg_rst_en_uart3_apb().bit()), + ) + .field( + "reg_rst_en_uart4_apb", + &format_args!("{}", self.reg_rst_en_uart4_apb().bit()), + ) + .field( + "reg_rst_en_uhci", + &format_args!("{}", self.reg_rst_en_uhci().bit()), + ) + .field( + "reg_rst_en_i3cmst", + &format_args!("{}", self.reg_rst_en_i3cmst().bit()), + ) + .field( + "reg_rst_en_i3cslv", + &format_args!("{}", self.reg_rst_en_i3cslv().bit()), + ) + .field( + "reg_rst_en_i2c1", + &format_args!("{}", self.reg_rst_en_i2c1().bit()), + ) + .field( + "reg_rst_en_i2c0", + &format_args!("{}", self.reg_rst_en_i2c0().bit()), + ) + .field( + "reg_rst_en_rmt", + &format_args!("{}", self.reg_rst_en_rmt().bit()), + ) + .field( + "reg_rst_en_pwm0", + &format_args!("{}", self.reg_rst_en_pwm0().bit()), + ) + .field( + "reg_rst_en_pwm1", + &format_args!("{}", self.reg_rst_en_pwm1().bit()), + ) + .field( + "reg_rst_en_can0", + &format_args!("{}", self.reg_rst_en_can0().bit()), + ) + .field( + "reg_rst_en_can1", + &format_args!("{}", self.reg_rst_en_can1().bit()), + ) + .field( + "reg_rst_en_can2", + &format_args!("{}", self.reg_rst_en_can2().bit()), + ) + .field( + "reg_rst_en_ledc", + &format_args!("{}", self.reg_rst_en_ledc().bit()), + ) + .field( + "reg_rst_en_pcnt", + &format_args!("{}", self.reg_rst_en_pcnt().bit()), + ) + .field( + "reg_rst_en_etm", + &format_args!("{}", self.reg_rst_en_etm().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_ppa(&mut self) -> REG_RST_EN_PPA_W { + REG_RST_EN_PPA_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_ahb_pdma(&mut self) -> REG_RST_EN_AHB_PDMA_W { + REG_RST_EN_AHB_PDMA_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_axi_pdma(&mut self) -> REG_RST_EN_AXI_PDMA_W { + REG_RST_EN_AXI_PDMA_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_iomux(&mut self) -> REG_RST_EN_IOMUX_W { + REG_RST_EN_IOMUX_W::new(self, 3) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_padbist(&mut self) -> REG_RST_EN_PADBIST_W { + REG_RST_EN_PADBIST_W::new(self, 4) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_stimer(&mut self) -> REG_RST_EN_STIMER_W { + REG_RST_EN_STIMER_W::new(self, 5) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_timergrp0(&mut self) -> REG_RST_EN_TIMERGRP0_W { + REG_RST_EN_TIMERGRP0_W::new(self, 6) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_timergrp1(&mut self) -> REG_RST_EN_TIMERGRP1_W { + REG_RST_EN_TIMERGRP1_W::new(self, 7) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_uart0_core(&mut self) -> REG_RST_EN_UART0_CORE_W { + REG_RST_EN_UART0_CORE_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_uart1_core(&mut self) -> REG_RST_EN_UART1_CORE_W { + REG_RST_EN_UART1_CORE_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_uart2_core(&mut self) -> REG_RST_EN_UART2_CORE_W { + REG_RST_EN_UART2_CORE_W::new(self, 10) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_uart3_core(&mut self) -> REG_RST_EN_UART3_CORE_W { + REG_RST_EN_UART3_CORE_W::new(self, 11) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_uart4_core(&mut self) -> REG_RST_EN_UART4_CORE_W { + REG_RST_EN_UART4_CORE_W::new(self, 12) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_uart0_apb(&mut self) -> REG_RST_EN_UART0_APB_W { + REG_RST_EN_UART0_APB_W::new(self, 13) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_uart1_apb(&mut self) -> REG_RST_EN_UART1_APB_W { + REG_RST_EN_UART1_APB_W::new(self, 14) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_uart2_apb(&mut self) -> REG_RST_EN_UART2_APB_W { + REG_RST_EN_UART2_APB_W::new(self, 15) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_uart3_apb(&mut self) -> REG_RST_EN_UART3_APB_W { + REG_RST_EN_UART3_APB_W::new(self, 16) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_uart4_apb(&mut self) -> REG_RST_EN_UART4_APB_W { + REG_RST_EN_UART4_APB_W::new(self, 17) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_uhci(&mut self) -> REG_RST_EN_UHCI_W { + REG_RST_EN_UHCI_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_i3cmst(&mut self) -> REG_RST_EN_I3CMST_W { + REG_RST_EN_I3CMST_W::new(self, 19) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_i3cslv(&mut self) -> REG_RST_EN_I3CSLV_W { + REG_RST_EN_I3CSLV_W::new(self, 20) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_i2c1(&mut self) -> REG_RST_EN_I2C1_W { + REG_RST_EN_I2C1_W::new(self, 21) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_i2c0(&mut self) -> REG_RST_EN_I2C0_W { + REG_RST_EN_I2C0_W::new(self, 22) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_rmt(&mut self) -> REG_RST_EN_RMT_W { + REG_RST_EN_RMT_W::new(self, 23) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_pwm0(&mut self) -> REG_RST_EN_PWM0_W { + REG_RST_EN_PWM0_W::new(self, 24) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_pwm1(&mut self) -> REG_RST_EN_PWM1_W { + REG_RST_EN_PWM1_W::new(self, 25) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_can0(&mut self) -> REG_RST_EN_CAN0_W { + REG_RST_EN_CAN0_W::new(self, 26) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_can1(&mut self) -> REG_RST_EN_CAN1_W { + REG_RST_EN_CAN1_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_can2(&mut self) -> REG_RST_EN_CAN2_W { + REG_RST_EN_CAN2_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_ledc(&mut self) -> REG_RST_EN_LEDC_W { + REG_RST_EN_LEDC_W::new(self, 29) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_pcnt(&mut self) -> REG_RST_EN_PCNT_W { + REG_RST_EN_PCNT_W::new(self, 30) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_etm(&mut self) -> REG_RST_EN_ETM_W { + REG_RST_EN_ETM_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rst_en1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rst_en1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_RST_EN1_SPEC; +impl crate::RegisterSpec for HP_RST_EN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_rst_en1::R`](R) reader structure"] +impl crate::Readable for HP_RST_EN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_rst_en1::W`](W) writer structure"] +impl crate::Writable for HP_RST_EN1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_RST_EN1 to value 0"] +impl crate::Resettable for HP_RST_EN1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/hp_rst_en2.rs b/esp32p4/src/hp_sys_clkrst/hp_rst_en2.rs new file mode 100644 index 0000000000..750e9463db --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/hp_rst_en2.rs @@ -0,0 +1,522 @@ +#[doc = "Register `HP_RST_EN2` reader"] +pub type R = crate::R; +#[doc = "Register `HP_RST_EN2` writer"] +pub type W = crate::W; +#[doc = "Field `REG_RST_EN_INTRMTX` reader - Reserved"] +pub type REG_RST_EN_INTRMTX_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_INTRMTX` writer - Reserved"] +pub type REG_RST_EN_INTRMTX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PARLIO` reader - Reserved"] +pub type REG_RST_EN_PARLIO_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PARLIO` writer - Reserved"] +pub type REG_RST_EN_PARLIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PARLIO_RX` reader - Reserved"] +pub type REG_RST_EN_PARLIO_RX_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PARLIO_RX` writer - Reserved"] +pub type REG_RST_EN_PARLIO_RX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_PARLIO_TX` reader - Reserved"] +pub type REG_RST_EN_PARLIO_TX_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_PARLIO_TX` writer - Reserved"] +pub type REG_RST_EN_PARLIO_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_I2S0_APB` reader - Reserved"] +pub type REG_RST_EN_I2S0_APB_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_I2S0_APB` writer - Reserved"] +pub type REG_RST_EN_I2S0_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_I2S1_APB` reader - Reserved"] +pub type REG_RST_EN_I2S1_APB_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_I2S1_APB` writer - Reserved"] +pub type REG_RST_EN_I2S1_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_I2S2_APB` reader - Reserved"] +pub type REG_RST_EN_I2S2_APB_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_I2S2_APB` writer - Reserved"] +pub type REG_RST_EN_I2S2_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_SPI2` reader - Reserved"] +pub type REG_RST_EN_SPI2_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_SPI2` writer - Reserved"] +pub type REG_RST_EN_SPI2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_SPI3` reader - Reserved"] +pub type REG_RST_EN_SPI3_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_SPI3` writer - Reserved"] +pub type REG_RST_EN_SPI3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_LCDCAM` reader - Reserved"] +pub type REG_RST_EN_LCDCAM_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_LCDCAM` writer - Reserved"] +pub type REG_RST_EN_LCDCAM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_ADC` reader - Reserved"] +pub type REG_RST_EN_ADC_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_ADC` writer - Reserved"] +pub type REG_RST_EN_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_BITSRAMBLER` reader - Reserved"] +pub type REG_RST_EN_BITSRAMBLER_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_BITSRAMBLER` writer - Reserved"] +pub type REG_RST_EN_BITSRAMBLER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_BITSRAMBLER_RX` reader - Reserved"] +pub type REG_RST_EN_BITSRAMBLER_RX_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_BITSRAMBLER_RX` writer - Reserved"] +pub type REG_RST_EN_BITSRAMBLER_RX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_BITSRAMBLER_TX` reader - Reserved"] +pub type REG_RST_EN_BITSRAMBLER_TX_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_BITSRAMBLER_TX` writer - Reserved"] +pub type REG_RST_EN_BITSRAMBLER_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_CRYPTO` reader - Reserved"] +pub type REG_RST_EN_CRYPTO_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_CRYPTO` writer - Reserved"] +pub type REG_RST_EN_CRYPTO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_SEC` reader - Reserved"] +pub type REG_RST_EN_SEC_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_SEC` writer - Reserved"] +pub type REG_RST_EN_SEC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_AES` reader - Reserved"] +pub type REG_RST_EN_AES_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_AES` writer - Reserved"] +pub type REG_RST_EN_AES_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_DS` reader - Reserved"] +pub type REG_RST_EN_DS_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_DS` writer - Reserved"] +pub type REG_RST_EN_DS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_SHA` reader - Reserved"] +pub type REG_RST_EN_SHA_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_SHA` writer - Reserved"] +pub type REG_RST_EN_SHA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_HMAC` reader - Reserved"] +pub type REG_RST_EN_HMAC_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_HMAC` writer - Reserved"] +pub type REG_RST_EN_HMAC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_ECDSA` reader - Reserved"] +pub type REG_RST_EN_ECDSA_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_ECDSA` writer - Reserved"] +pub type REG_RST_EN_ECDSA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_RSA` reader - Reserved"] +pub type REG_RST_EN_RSA_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_RSA` writer - Reserved"] +pub type REG_RST_EN_RSA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_ECC` reader - Reserved"] +pub type REG_RST_EN_ECC_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_ECC` writer - Reserved"] +pub type REG_RST_EN_ECC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_KM` reader - Reserved"] +pub type REG_RST_EN_KM_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_KM` writer - Reserved"] +pub type REG_RST_EN_KM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RST_EN_H264` reader - Reserved"] +pub type REG_RST_EN_H264_R = crate::BitReader; +#[doc = "Field `REG_RST_EN_H264` writer - Reserved"] +pub type REG_RST_EN_H264_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_intrmtx(&self) -> REG_RST_EN_INTRMTX_R { + REG_RST_EN_INTRMTX_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_parlio(&self) -> REG_RST_EN_PARLIO_R { + REG_RST_EN_PARLIO_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_parlio_rx(&self) -> REG_RST_EN_PARLIO_RX_R { + REG_RST_EN_PARLIO_RX_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_parlio_tx(&self) -> REG_RST_EN_PARLIO_TX_R { + REG_RST_EN_PARLIO_TX_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_i2s0_apb(&self) -> REG_RST_EN_I2S0_APB_R { + REG_RST_EN_I2S0_APB_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_i2s1_apb(&self) -> REG_RST_EN_I2S1_APB_R { + REG_RST_EN_I2S1_APB_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_i2s2_apb(&self) -> REG_RST_EN_I2S2_APB_R { + REG_RST_EN_I2S2_APB_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_spi2(&self) -> REG_RST_EN_SPI2_R { + REG_RST_EN_SPI2_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_spi3(&self) -> REG_RST_EN_SPI3_R { + REG_RST_EN_SPI3_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_lcdcam(&self) -> REG_RST_EN_LCDCAM_R { + REG_RST_EN_LCDCAM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_adc(&self) -> REG_RST_EN_ADC_R { + REG_RST_EN_ADC_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_bitsrambler(&self) -> REG_RST_EN_BITSRAMBLER_R { + REG_RST_EN_BITSRAMBLER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_bitsrambler_rx(&self) -> REG_RST_EN_BITSRAMBLER_RX_R { + REG_RST_EN_BITSRAMBLER_RX_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_bitsrambler_tx(&self) -> REG_RST_EN_BITSRAMBLER_TX_R { + REG_RST_EN_BITSRAMBLER_TX_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_crypto(&self) -> REG_RST_EN_CRYPTO_R { + REG_RST_EN_CRYPTO_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_sec(&self) -> REG_RST_EN_SEC_R { + REG_RST_EN_SEC_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_aes(&self) -> REG_RST_EN_AES_R { + REG_RST_EN_AES_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_ds(&self) -> REG_RST_EN_DS_R { + REG_RST_EN_DS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_sha(&self) -> REG_RST_EN_SHA_R { + REG_RST_EN_SHA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_hmac(&self) -> REG_RST_EN_HMAC_R { + REG_RST_EN_HMAC_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_ecdsa(&self) -> REG_RST_EN_ECDSA_R { + REG_RST_EN_ECDSA_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_rsa(&self) -> REG_RST_EN_RSA_R { + REG_RST_EN_RSA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_ecc(&self) -> REG_RST_EN_ECC_R { + REG_RST_EN_ECC_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_km(&self) -> REG_RST_EN_KM_R { + REG_RST_EN_KM_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_rst_en_h264(&self) -> REG_RST_EN_H264_R { + REG_RST_EN_H264_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_RST_EN2") + .field( + "reg_rst_en_intrmtx", + &format_args!("{}", self.reg_rst_en_intrmtx().bit()), + ) + .field( + "reg_rst_en_parlio", + &format_args!("{}", self.reg_rst_en_parlio().bit()), + ) + .field( + "reg_rst_en_parlio_rx", + &format_args!("{}", self.reg_rst_en_parlio_rx().bit()), + ) + .field( + "reg_rst_en_parlio_tx", + &format_args!("{}", self.reg_rst_en_parlio_tx().bit()), + ) + .field( + "reg_rst_en_i2s0_apb", + &format_args!("{}", self.reg_rst_en_i2s0_apb().bit()), + ) + .field( + "reg_rst_en_i2s1_apb", + &format_args!("{}", self.reg_rst_en_i2s1_apb().bit()), + ) + .field( + "reg_rst_en_i2s2_apb", + &format_args!("{}", self.reg_rst_en_i2s2_apb().bit()), + ) + .field( + "reg_rst_en_spi2", + &format_args!("{}", self.reg_rst_en_spi2().bit()), + ) + .field( + "reg_rst_en_spi3", + &format_args!("{}", self.reg_rst_en_spi3().bit()), + ) + .field( + "reg_rst_en_lcdcam", + &format_args!("{}", self.reg_rst_en_lcdcam().bit()), + ) + .field( + "reg_rst_en_adc", + &format_args!("{}", self.reg_rst_en_adc().bit()), + ) + .field( + "reg_rst_en_bitsrambler", + &format_args!("{}", self.reg_rst_en_bitsrambler().bit()), + ) + .field( + "reg_rst_en_bitsrambler_rx", + &format_args!("{}", self.reg_rst_en_bitsrambler_rx().bit()), + ) + .field( + "reg_rst_en_bitsrambler_tx", + &format_args!("{}", self.reg_rst_en_bitsrambler_tx().bit()), + ) + .field( + "reg_rst_en_crypto", + &format_args!("{}", self.reg_rst_en_crypto().bit()), + ) + .field( + "reg_rst_en_sec", + &format_args!("{}", self.reg_rst_en_sec().bit()), + ) + .field( + "reg_rst_en_aes", + &format_args!("{}", self.reg_rst_en_aes().bit()), + ) + .field( + "reg_rst_en_ds", + &format_args!("{}", self.reg_rst_en_ds().bit()), + ) + .field( + "reg_rst_en_sha", + &format_args!("{}", self.reg_rst_en_sha().bit()), + ) + .field( + "reg_rst_en_hmac", + &format_args!("{}", self.reg_rst_en_hmac().bit()), + ) + .field( + "reg_rst_en_ecdsa", + &format_args!("{}", self.reg_rst_en_ecdsa().bit()), + ) + .field( + "reg_rst_en_rsa", + &format_args!("{}", self.reg_rst_en_rsa().bit()), + ) + .field( + "reg_rst_en_ecc", + &format_args!("{}", self.reg_rst_en_ecc().bit()), + ) + .field( + "reg_rst_en_km", + &format_args!("{}", self.reg_rst_en_km().bit()), + ) + .field( + "reg_rst_en_h264", + &format_args!("{}", self.reg_rst_en_h264().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_intrmtx(&mut self) -> REG_RST_EN_INTRMTX_W { + REG_RST_EN_INTRMTX_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_parlio(&mut self) -> REG_RST_EN_PARLIO_W { + REG_RST_EN_PARLIO_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_parlio_rx(&mut self) -> REG_RST_EN_PARLIO_RX_W { + REG_RST_EN_PARLIO_RX_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_parlio_tx(&mut self) -> REG_RST_EN_PARLIO_TX_W { + REG_RST_EN_PARLIO_TX_W::new(self, 3) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_i2s0_apb(&mut self) -> REG_RST_EN_I2S0_APB_W { + REG_RST_EN_I2S0_APB_W::new(self, 4) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_i2s1_apb(&mut self) -> REG_RST_EN_I2S1_APB_W { + REG_RST_EN_I2S1_APB_W::new(self, 5) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_i2s2_apb(&mut self) -> REG_RST_EN_I2S2_APB_W { + REG_RST_EN_I2S2_APB_W::new(self, 6) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_spi2(&mut self) -> REG_RST_EN_SPI2_W { + REG_RST_EN_SPI2_W::new(self, 7) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_spi3(&mut self) -> REG_RST_EN_SPI3_W { + REG_RST_EN_SPI3_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_lcdcam(&mut self) -> REG_RST_EN_LCDCAM_W { + REG_RST_EN_LCDCAM_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_adc(&mut self) -> REG_RST_EN_ADC_W { + REG_RST_EN_ADC_W::new(self, 10) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_bitsrambler(&mut self) -> REG_RST_EN_BITSRAMBLER_W { + REG_RST_EN_BITSRAMBLER_W::new(self, 11) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_bitsrambler_rx(&mut self) -> REG_RST_EN_BITSRAMBLER_RX_W { + REG_RST_EN_BITSRAMBLER_RX_W::new(self, 12) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_bitsrambler_tx(&mut self) -> REG_RST_EN_BITSRAMBLER_TX_W { + REG_RST_EN_BITSRAMBLER_TX_W::new(self, 13) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_crypto(&mut self) -> REG_RST_EN_CRYPTO_W { + REG_RST_EN_CRYPTO_W::new(self, 14) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_sec(&mut self) -> REG_RST_EN_SEC_W { + REG_RST_EN_SEC_W::new(self, 15) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_aes(&mut self) -> REG_RST_EN_AES_W { + REG_RST_EN_AES_W::new(self, 16) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_ds(&mut self) -> REG_RST_EN_DS_W { + REG_RST_EN_DS_W::new(self, 17) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_sha(&mut self) -> REG_RST_EN_SHA_W { + REG_RST_EN_SHA_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_hmac(&mut self) -> REG_RST_EN_HMAC_W { + REG_RST_EN_HMAC_W::new(self, 19) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_ecdsa(&mut self) -> REG_RST_EN_ECDSA_W { + REG_RST_EN_ECDSA_W::new(self, 20) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_rsa(&mut self) -> REG_RST_EN_RSA_W { + REG_RST_EN_RSA_W::new(self, 21) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_ecc(&mut self) -> REG_RST_EN_ECC_W { + REG_RST_EN_ECC_W::new(self, 22) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_km(&mut self) -> REG_RST_EN_KM_W { + REG_RST_EN_KM_W::new(self, 23) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rst_en_h264(&mut self) -> REG_RST_EN_H264_W { + REG_RST_EN_H264_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rst_en2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rst_en2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_RST_EN2_SPEC; +impl crate::RegisterSpec for HP_RST_EN2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_rst_en2::R`](R) reader structure"] +impl crate::Readable for HP_RST_EN2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_rst_en2::W`](W) writer structure"] +impl crate::Writable for HP_RST_EN2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_RST_EN2 to value 0"] +impl crate::Resettable for HP_RST_EN2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/hpcore_wdt_reset_source0.rs b/esp32p4/src/hp_sys_clkrst/hpcore_wdt_reset_source0.rs new file mode 100644 index 0000000000..69d936f3de --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/hpcore_wdt_reset_source0.rs @@ -0,0 +1,89 @@ +#[doc = "Register `HPCORE_WDT_RESET_SOURCE0` reader"] +pub type R = crate::R; +#[doc = "Register `HPCORE_WDT_RESET_SOURCE0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_HPCORE0_WDT_RESET_SOURCE_SEL` reader - 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0"] +pub type REG_HPCORE0_WDT_RESET_SOURCE_SEL_R = crate::BitReader; +#[doc = "Field `REG_HPCORE0_WDT_RESET_SOURCE_SEL` writer - 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0"] +pub type REG_HPCORE0_WDT_RESET_SOURCE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_HPCORE1_WDT_RESET_SOURCE_SEL` reader - 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1"] +pub type REG_HPCORE1_WDT_RESET_SOURCE_SEL_R = crate::BitReader; +#[doc = "Field `REG_HPCORE1_WDT_RESET_SOURCE_SEL` writer - 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1"] +pub type REG_HPCORE1_WDT_RESET_SOURCE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0"] + #[inline(always)] + pub fn reg_hpcore0_wdt_reset_source_sel(&self) -> REG_HPCORE0_WDT_RESET_SOURCE_SEL_R { + REG_HPCORE0_WDT_RESET_SOURCE_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1"] + #[inline(always)] + pub fn reg_hpcore1_wdt_reset_source_sel(&self) -> REG_HPCORE1_WDT_RESET_SOURCE_SEL_R { + REG_HPCORE1_WDT_RESET_SOURCE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPCORE_WDT_RESET_SOURCE0") + .field( + "reg_hpcore0_wdt_reset_source_sel", + &format_args!("{}", self.reg_hpcore0_wdt_reset_source_sel().bit()), + ) + .field( + "reg_hpcore1_wdt_reset_source_sel", + &format_args!("{}", self.reg_hpcore1_wdt_reset_source_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0"] + #[inline(always)] + #[must_use] + pub fn reg_hpcore0_wdt_reset_source_sel( + &mut self, + ) -> REG_HPCORE0_WDT_RESET_SOURCE_SEL_W { + REG_HPCORE0_WDT_RESET_SOURCE_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1"] + #[inline(always)] + #[must_use] + pub fn reg_hpcore1_wdt_reset_source_sel( + &mut self, + ) -> REG_HPCORE1_WDT_RESET_SOURCE_SEL_W { + REG_HPCORE1_WDT_RESET_SOURCE_SEL_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpcore_wdt_reset_source0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hpcore_wdt_reset_source0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HPCORE_WDT_RESET_SOURCE0_SPEC; +impl crate::RegisterSpec for HPCORE_WDT_RESET_SOURCE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hpcore_wdt_reset_source0::R`](R) reader structure"] +impl crate::Readable for HPCORE_WDT_RESET_SOURCE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hpcore_wdt_reset_source0::W`](W) writer structure"] +impl crate::Writable for HPCORE_WDT_RESET_SOURCE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPCORE_WDT_RESET_SOURCE0 to value 0x02"] +impl crate::Resettable for HPCORE_WDT_RESET_SOURCE0_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/hp_sys_clkrst/hpwdt_core0_rst_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/hpwdt_core0_rst_ctrl0.rs new file mode 100644 index 0000000000..2e7392c238 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/hpwdt_core0_rst_ctrl0.rs @@ -0,0 +1,108 @@ +#[doc = "Register `HPWDT_CORE0_RST_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `HPWDT_CORE0_RST_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_HPCORE0_STALL_EN` reader - Reserved"] +pub type REG_HPCORE0_STALL_EN_R = crate::BitReader; +#[doc = "Field `REG_HPCORE0_STALL_EN` writer - Reserved"] +pub type REG_HPCORE0_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_HPCORE0_STALL_WAIT_NUM` reader - Reserved"] +pub type REG_HPCORE0_STALL_WAIT_NUM_R = crate::FieldReader; +#[doc = "Field `REG_HPCORE0_STALL_WAIT_NUM` writer - Reserved"] +pub type REG_HPCORE0_STALL_WAIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_WDT_HPCORE0_RST_LEN` reader - Reserved"] +pub type REG_WDT_HPCORE0_RST_LEN_R = crate::FieldReader; +#[doc = "Field `REG_WDT_HPCORE0_RST_LEN` writer - Reserved"] +pub type REG_WDT_HPCORE0_RST_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_hpcore0_stall_en(&self) -> REG_HPCORE0_STALL_EN_R { + REG_HPCORE0_STALL_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:8 - Reserved"] + #[inline(always)] + pub fn reg_hpcore0_stall_wait_num(&self) -> REG_HPCORE0_STALL_WAIT_NUM_R { + REG_HPCORE0_STALL_WAIT_NUM_R::new(((self.bits >> 1) & 0xff) as u8) + } + #[doc = "Bits 9:16 - Reserved"] + #[inline(always)] + pub fn reg_wdt_hpcore0_rst_len(&self) -> REG_WDT_HPCORE0_RST_LEN_R { + REG_WDT_HPCORE0_RST_LEN_R::new(((self.bits >> 9) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPWDT_CORE0_RST_CTRL0") + .field( + "reg_hpcore0_stall_en", + &format_args!("{}", self.reg_hpcore0_stall_en().bit()), + ) + .field( + "reg_hpcore0_stall_wait_num", + &format_args!("{}", self.reg_hpcore0_stall_wait_num().bits()), + ) + .field( + "reg_wdt_hpcore0_rst_len", + &format_args!("{}", self.reg_wdt_hpcore0_rst_len().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_hpcore0_stall_en(&mut self) -> REG_HPCORE0_STALL_EN_W { + REG_HPCORE0_STALL_EN_W::new(self, 0) + } + #[doc = "Bits 1:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_hpcore0_stall_wait_num( + &mut self, + ) -> REG_HPCORE0_STALL_WAIT_NUM_W { + REG_HPCORE0_STALL_WAIT_NUM_W::new(self, 1) + } + #[doc = "Bits 9:16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_wdt_hpcore0_rst_len( + &mut self, + ) -> REG_WDT_HPCORE0_RST_LEN_W { + REG_WDT_HPCORE0_RST_LEN_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpwdt_core0_rst_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hpwdt_core0_rst_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HPWDT_CORE0_RST_CTRL0_SPEC; +impl crate::RegisterSpec for HPWDT_CORE0_RST_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hpwdt_core0_rst_ctrl0::R`](R) reader structure"] +impl crate::Readable for HPWDT_CORE0_RST_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hpwdt_core0_rst_ctrl0::W`](W) writer structure"] +impl crate::Writable for HPWDT_CORE0_RST_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPWDT_CORE0_RST_CTRL0 to value 0x1011"] +impl crate::Resettable for HPWDT_CORE0_RST_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0x1011; +} diff --git a/esp32p4/src/hp_sys_clkrst/hpwdt_core1_rst_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/hpwdt_core1_rst_ctrl0.rs new file mode 100644 index 0000000000..b72a0168cb --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/hpwdt_core1_rst_ctrl0.rs @@ -0,0 +1,108 @@ +#[doc = "Register `HPWDT_CORE1_RST_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `HPWDT_CORE1_RST_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_HPCORE1_STALL_EN` reader - Reserved"] +pub type REG_HPCORE1_STALL_EN_R = crate::BitReader; +#[doc = "Field `REG_HPCORE1_STALL_EN` writer - Reserved"] +pub type REG_HPCORE1_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_HPCORE1_STALL_WAIT_NUM` reader - Reserved"] +pub type REG_HPCORE1_STALL_WAIT_NUM_R = crate::FieldReader; +#[doc = "Field `REG_HPCORE1_STALL_WAIT_NUM` writer - Reserved"] +pub type REG_HPCORE1_STALL_WAIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_WDT_HPCORE1_RST_LEN` reader - Reserved"] +pub type REG_WDT_HPCORE1_RST_LEN_R = crate::FieldReader; +#[doc = "Field `REG_WDT_HPCORE1_RST_LEN` writer - Reserved"] +pub type REG_WDT_HPCORE1_RST_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_hpcore1_stall_en(&self) -> REG_HPCORE1_STALL_EN_R { + REG_HPCORE1_STALL_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:8 - Reserved"] + #[inline(always)] + pub fn reg_hpcore1_stall_wait_num(&self) -> REG_HPCORE1_STALL_WAIT_NUM_R { + REG_HPCORE1_STALL_WAIT_NUM_R::new(((self.bits >> 1) & 0xff) as u8) + } + #[doc = "Bits 9:16 - Reserved"] + #[inline(always)] + pub fn reg_wdt_hpcore1_rst_len(&self) -> REG_WDT_HPCORE1_RST_LEN_R { + REG_WDT_HPCORE1_RST_LEN_R::new(((self.bits >> 9) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HPWDT_CORE1_RST_CTRL0") + .field( + "reg_hpcore1_stall_en", + &format_args!("{}", self.reg_hpcore1_stall_en().bit()), + ) + .field( + "reg_hpcore1_stall_wait_num", + &format_args!("{}", self.reg_hpcore1_stall_wait_num().bits()), + ) + .field( + "reg_wdt_hpcore1_rst_len", + &format_args!("{}", self.reg_wdt_hpcore1_rst_len().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_hpcore1_stall_en(&mut self) -> REG_HPCORE1_STALL_EN_W { + REG_HPCORE1_STALL_EN_W::new(self, 0) + } + #[doc = "Bits 1:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_hpcore1_stall_wait_num( + &mut self, + ) -> REG_HPCORE1_STALL_WAIT_NUM_W { + REG_HPCORE1_STALL_WAIT_NUM_W::new(self, 1) + } + #[doc = "Bits 9:16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_wdt_hpcore1_rst_len( + &mut self, + ) -> REG_WDT_HPCORE1_RST_LEN_W { + REG_WDT_HPCORE1_RST_LEN_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpwdt_core1_rst_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hpwdt_core1_rst_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HPWDT_CORE1_RST_CTRL0_SPEC; +impl crate::RegisterSpec for HPWDT_CORE1_RST_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hpwdt_core1_rst_ctrl0::R`](R) reader structure"] +impl crate::Readable for HPWDT_CORE1_RST_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hpwdt_core1_rst_ctrl0::W`](W) writer structure"] +impl crate::Writable for HPWDT_CORE1_RST_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HPWDT_CORE1_RST_CTRL0 to value 0x1011"] +impl crate::Resettable for HPWDT_CORE1_RST_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0x1011; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl00.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl00.rs new file mode 100644 index 0000000000..4607966dea --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl00.rs @@ -0,0 +1,300 @@ +#[doc = "Register `PERI_CLK_CTRL00` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL00` writer"] +pub type W = crate::W; +#[doc = "Field `REG_FLASH_CLK_SRC_SEL` reader - Reserved"] +pub type REG_FLASH_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_FLASH_CLK_SRC_SEL` writer - Reserved"] +pub type REG_FLASH_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_FLASH_PLL_CLK_EN` reader - Reserved"] +pub type REG_FLASH_PLL_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_FLASH_PLL_CLK_EN` writer - Reserved"] +pub type REG_FLASH_PLL_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FLASH_CORE_CLK_EN` reader - Reserved"] +pub type REG_FLASH_CORE_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_FLASH_CORE_CLK_EN` writer - Reserved"] +pub type REG_FLASH_CORE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FLASH_CORE_CLK_DIV_NUM` reader - Reserved"] +pub type REG_FLASH_CORE_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_FLASH_CORE_CLK_DIV_NUM` writer - Reserved"] +pub type REG_FLASH_CORE_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_PSRAM_CLK_SRC_SEL` reader - Reserved"] +pub type REG_PSRAM_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PSRAM_CLK_SRC_SEL` writer - Reserved"] +pub type REG_PSRAM_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PSRAM_PLL_CLK_EN` reader - Reserved"] +pub type REG_PSRAM_PLL_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PSRAM_PLL_CLK_EN` writer - Reserved"] +pub type REG_PSRAM_PLL_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PSRAM_CORE_CLK_EN` reader - Reserved"] +pub type REG_PSRAM_CORE_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PSRAM_CORE_CLK_EN` writer - Reserved"] +pub type REG_PSRAM_CORE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PSRAM_CORE_CLK_DIV_NUM` reader - Reserved"] +pub type REG_PSRAM_CORE_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_PSRAM_CORE_CLK_DIV_NUM` writer - Reserved"] +pub type REG_PSRAM_CORE_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_PAD_EMAC_REF_CLK_EN` reader - Reserved"] +pub type REG_PAD_EMAC_REF_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD_EMAC_REF_CLK_EN` writer - Reserved"] +pub type REG_PAD_EMAC_REF_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_EMAC_RMII_CLK_SRC_SEL` reader - Reserved"] +pub type REG_EMAC_RMII_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_EMAC_RMII_CLK_SRC_SEL` writer - Reserved"] +pub type REG_EMAC_RMII_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_EMAC_RMII_CLK_EN` reader - Reserved"] +pub type REG_EMAC_RMII_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_EMAC_RMII_CLK_EN` writer - Reserved"] +pub type REG_EMAC_RMII_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_EMAC_RX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_EMAC_RX_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_EMAC_RX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_EMAC_RX_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_EMAC_RX_CLK_EN` reader - Reserved"] +pub type REG_EMAC_RX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_EMAC_RX_CLK_EN` writer - Reserved"] +pub type REG_EMAC_RX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_flash_clk_src_sel(&self) -> REG_FLASH_CLK_SRC_SEL_R { + REG_FLASH_CLK_SRC_SEL_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_flash_pll_clk_en(&self) -> REG_FLASH_PLL_CLK_EN_R { + REG_FLASH_PLL_CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_flash_core_clk_en(&self) -> REG_FLASH_CORE_CLK_EN_R { + REG_FLASH_CORE_CLK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:11 - Reserved"] + #[inline(always)] + pub fn reg_flash_core_clk_div_num(&self) -> REG_FLASH_CORE_CLK_DIV_NUM_R { + REG_FLASH_CORE_CLK_DIV_NUM_R::new(((self.bits >> 4) & 0xff) as u8) + } + #[doc = "Bits 12:13 - Reserved"] + #[inline(always)] + pub fn reg_psram_clk_src_sel(&self) -> REG_PSRAM_CLK_SRC_SEL_R { + REG_PSRAM_CLK_SRC_SEL_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn reg_psram_pll_clk_en(&self) -> REG_PSRAM_PLL_CLK_EN_R { + REG_PSRAM_PLL_CLK_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn reg_psram_core_clk_en(&self) -> REG_PSRAM_CORE_CLK_EN_R { + REG_PSRAM_CORE_CLK_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_psram_core_clk_div_num(&self) -> REG_PSRAM_CORE_CLK_DIV_NUM_R { + REG_PSRAM_CORE_CLK_DIV_NUM_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_pad_emac_ref_clk_en(&self) -> REG_PAD_EMAC_REF_CLK_EN_R { + REG_PAD_EMAC_REF_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:26 - Reserved"] + #[inline(always)] + pub fn reg_emac_rmii_clk_src_sel(&self) -> REG_EMAC_RMII_CLK_SRC_SEL_R { + REG_EMAC_RMII_CLK_SRC_SEL_R::new(((self.bits >> 25) & 3) as u8) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_emac_rmii_clk_en(&self) -> REG_EMAC_RMII_CLK_EN_R { + REG_EMAC_RMII_CLK_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_emac_rx_clk_src_sel(&self) -> REG_EMAC_RX_CLK_SRC_SEL_R { + REG_EMAC_RX_CLK_SRC_SEL_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_emac_rx_clk_en(&self) -> REG_EMAC_RX_CLK_EN_R { + REG_EMAC_RX_CLK_EN_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL00") + .field( + "reg_flash_clk_src_sel", + &format_args!("{}", self.reg_flash_clk_src_sel().bits()), + ) + .field( + "reg_flash_pll_clk_en", + &format_args!("{}", self.reg_flash_pll_clk_en().bit()), + ) + .field( + "reg_flash_core_clk_en", + &format_args!("{}", self.reg_flash_core_clk_en().bit()), + ) + .field( + "reg_flash_core_clk_div_num", + &format_args!("{}", self.reg_flash_core_clk_div_num().bits()), + ) + .field( + "reg_psram_clk_src_sel", + &format_args!("{}", self.reg_psram_clk_src_sel().bits()), + ) + .field( + "reg_psram_pll_clk_en", + &format_args!("{}", self.reg_psram_pll_clk_en().bit()), + ) + .field( + "reg_psram_core_clk_en", + &format_args!("{}", self.reg_psram_core_clk_en().bit()), + ) + .field( + "reg_psram_core_clk_div_num", + &format_args!("{}", self.reg_psram_core_clk_div_num().bits()), + ) + .field( + "reg_pad_emac_ref_clk_en", + &format_args!("{}", self.reg_pad_emac_ref_clk_en().bit()), + ) + .field( + "reg_emac_rmii_clk_src_sel", + &format_args!("{}", self.reg_emac_rmii_clk_src_sel().bits()), + ) + .field( + "reg_emac_rmii_clk_en", + &format_args!("{}", self.reg_emac_rmii_clk_en().bit()), + ) + .field( + "reg_emac_rx_clk_src_sel", + &format_args!("{}", self.reg_emac_rx_clk_src_sel().bit()), + ) + .field( + "reg_emac_rx_clk_en", + &format_args!("{}", self.reg_emac_rx_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_flash_clk_src_sel(&mut self) -> REG_FLASH_CLK_SRC_SEL_W { + REG_FLASH_CLK_SRC_SEL_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_flash_pll_clk_en(&mut self) -> REG_FLASH_PLL_CLK_EN_W { + REG_FLASH_PLL_CLK_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_flash_core_clk_en(&mut self) -> REG_FLASH_CORE_CLK_EN_W { + REG_FLASH_CORE_CLK_EN_W::new(self, 3) + } + #[doc = "Bits 4:11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_flash_core_clk_div_num( + &mut self, + ) -> REG_FLASH_CORE_CLK_DIV_NUM_W { + REG_FLASH_CORE_CLK_DIV_NUM_W::new(self, 4) + } + #[doc = "Bits 12:13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_psram_clk_src_sel(&mut self) -> REG_PSRAM_CLK_SRC_SEL_W { + REG_PSRAM_CLK_SRC_SEL_W::new(self, 12) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_psram_pll_clk_en(&mut self) -> REG_PSRAM_PLL_CLK_EN_W { + REG_PSRAM_PLL_CLK_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_psram_core_clk_en(&mut self) -> REG_PSRAM_CORE_CLK_EN_W { + REG_PSRAM_CORE_CLK_EN_W::new(self, 15) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_psram_core_clk_div_num( + &mut self, + ) -> REG_PSRAM_CORE_CLK_DIV_NUM_W { + REG_PSRAM_CORE_CLK_DIV_NUM_W::new(self, 16) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad_emac_ref_clk_en(&mut self) -> REG_PAD_EMAC_REF_CLK_EN_W { + REG_PAD_EMAC_REF_CLK_EN_W::new(self, 24) + } + #[doc = "Bits 25:26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_rmii_clk_src_sel( + &mut self, + ) -> REG_EMAC_RMII_CLK_SRC_SEL_W { + REG_EMAC_RMII_CLK_SRC_SEL_W::new(self, 25) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_rmii_clk_en(&mut self) -> REG_EMAC_RMII_CLK_EN_W { + REG_EMAC_RMII_CLK_EN_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_rx_clk_src_sel(&mut self) -> REG_EMAC_RX_CLK_SRC_SEL_W { + REG_EMAC_RX_CLK_SRC_SEL_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_rx_clk_en(&mut self) -> REG_EMAC_RX_CLK_EN_W { + REG_EMAC_RX_CLK_EN_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl00::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl00::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL00_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL00_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl00::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL00_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl00::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL00_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL00 to value 0xc03c"] +impl crate::Resettable for PERI_CLK_CTRL00_SPEC { + const RESET_VALUE: Self::Ux = 0xc03c; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl01.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl01.rs new file mode 100644 index 0000000000..e97ea85eeb --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl01.rs @@ -0,0 +1,258 @@ +#[doc = "Register `PERI_CLK_CTRL01` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL01` writer"] +pub type W = crate::W; +#[doc = "Field `REG_EMAC_RX_CLK_DIV_NUM` reader - Reserved"] +pub type REG_EMAC_RX_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_EMAC_RX_CLK_DIV_NUM` writer - Reserved"] +pub type REG_EMAC_RX_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_EMAC_TX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_EMAC_TX_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_EMAC_TX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_EMAC_TX_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_EMAC_TX_CLK_EN` reader - Reserved"] +pub type REG_EMAC_TX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_EMAC_TX_CLK_EN` writer - Reserved"] +pub type REG_EMAC_TX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_EMAC_TX_CLK_DIV_NUM` reader - Reserved"] +pub type REG_EMAC_TX_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_EMAC_TX_CLK_DIV_NUM` writer - Reserved"] +pub type REG_EMAC_TX_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_EMAC_PTP_REF_CLK_SRC_SEL` reader - Reserved"] +pub type REG_EMAC_PTP_REF_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_EMAC_PTP_REF_CLK_SRC_SEL` writer - Reserved"] +pub type REG_EMAC_PTP_REF_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_EMAC_PTP_REF_CLK_EN` reader - Reserved"] +pub type REG_EMAC_PTP_REF_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_EMAC_PTP_REF_CLK_EN` writer - Reserved"] +pub type REG_EMAC_PTP_REF_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_EMAC_UNUSED0_CLK_EN` reader - Reserved"] +pub type REG_EMAC_UNUSED0_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_EMAC_UNUSED0_CLK_EN` writer - Reserved"] +pub type REG_EMAC_UNUSED0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_EMAC_UNUSED1_CLK_EN` reader - Reserved"] +pub type REG_EMAC_UNUSED1_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_EMAC_UNUSED1_CLK_EN` writer - Reserved"] +pub type REG_EMAC_UNUSED1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SDIO_HS_MODE` reader - Reserved"] +pub type REG_SDIO_HS_MODE_R = crate::BitReader; +#[doc = "Field `REG_SDIO_HS_MODE` writer - Reserved"] +pub type REG_SDIO_HS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SDIO_LS_CLK_SRC_SEL` reader - Reserved"] +pub type REG_SDIO_LS_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_SDIO_LS_CLK_SRC_SEL` writer - Reserved"] +pub type REG_SDIO_LS_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SDIO_LS_CLK_EN` reader - Reserved"] +pub type REG_SDIO_LS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_SDIO_LS_CLK_EN` writer - Reserved"] +pub type REG_SDIO_LS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_emac_rx_clk_div_num(&self) -> REG_EMAC_RX_CLK_DIV_NUM_R { + REG_EMAC_RX_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_emac_tx_clk_src_sel(&self) -> REG_EMAC_TX_CLK_SRC_SEL_R { + REG_EMAC_TX_CLK_SRC_SEL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_emac_tx_clk_en(&self) -> REG_EMAC_TX_CLK_EN_R { + REG_EMAC_TX_CLK_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:17 - Reserved"] + #[inline(always)] + pub fn reg_emac_tx_clk_div_num(&self) -> REG_EMAC_TX_CLK_DIV_NUM_R { + REG_EMAC_TX_CLK_DIV_NUM_R::new(((self.bits >> 10) & 0xff) as u8) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_emac_ptp_ref_clk_src_sel(&self) -> REG_EMAC_PTP_REF_CLK_SRC_SEL_R { + REG_EMAC_PTP_REF_CLK_SRC_SEL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_emac_ptp_ref_clk_en(&self) -> REG_EMAC_PTP_REF_CLK_EN_R { + REG_EMAC_PTP_REF_CLK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_emac_unused0_clk_en(&self) -> REG_EMAC_UNUSED0_CLK_EN_R { + REG_EMAC_UNUSED0_CLK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + pub fn reg_emac_unused1_clk_en(&self) -> REG_EMAC_UNUSED1_CLK_EN_R { + REG_EMAC_UNUSED1_CLK_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn reg_sdio_hs_mode(&self) -> REG_SDIO_HS_MODE_R { + REG_SDIO_HS_MODE_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_clk_src_sel(&self) -> REG_SDIO_LS_CLK_SRC_SEL_R { + REG_SDIO_LS_CLK_SRC_SEL_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_clk_en(&self) -> REG_SDIO_LS_CLK_EN_R { + REG_SDIO_LS_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL01") + .field( + "reg_emac_rx_clk_div_num", + &format_args!("{}", self.reg_emac_rx_clk_div_num().bits()), + ) + .field( + "reg_emac_tx_clk_src_sel", + &format_args!("{}", self.reg_emac_tx_clk_src_sel().bit()), + ) + .field( + "reg_emac_tx_clk_en", + &format_args!("{}", self.reg_emac_tx_clk_en().bit()), + ) + .field( + "reg_emac_tx_clk_div_num", + &format_args!("{}", self.reg_emac_tx_clk_div_num().bits()), + ) + .field( + "reg_emac_ptp_ref_clk_src_sel", + &format_args!("{}", self.reg_emac_ptp_ref_clk_src_sel().bit()), + ) + .field( + "reg_emac_ptp_ref_clk_en", + &format_args!("{}", self.reg_emac_ptp_ref_clk_en().bit()), + ) + .field( + "reg_emac_unused0_clk_en", + &format_args!("{}", self.reg_emac_unused0_clk_en().bit()), + ) + .field( + "reg_emac_unused1_clk_en", + &format_args!("{}", self.reg_emac_unused1_clk_en().bit()), + ) + .field( + "reg_sdio_hs_mode", + &format_args!("{}", self.reg_sdio_hs_mode().bit()), + ) + .field( + "reg_sdio_ls_clk_src_sel", + &format_args!("{}", self.reg_sdio_ls_clk_src_sel().bit()), + ) + .field( + "reg_sdio_ls_clk_en", + &format_args!("{}", self.reg_sdio_ls_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_rx_clk_div_num(&mut self) -> REG_EMAC_RX_CLK_DIV_NUM_W { + REG_EMAC_RX_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_tx_clk_src_sel(&mut self) -> REG_EMAC_TX_CLK_SRC_SEL_W { + REG_EMAC_TX_CLK_SRC_SEL_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_tx_clk_en(&mut self) -> REG_EMAC_TX_CLK_EN_W { + REG_EMAC_TX_CLK_EN_W::new(self, 9) + } + #[doc = "Bits 10:17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_tx_clk_div_num(&mut self) -> REG_EMAC_TX_CLK_DIV_NUM_W { + REG_EMAC_TX_CLK_DIV_NUM_W::new(self, 10) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_ptp_ref_clk_src_sel( + &mut self, + ) -> REG_EMAC_PTP_REF_CLK_SRC_SEL_W { + REG_EMAC_PTP_REF_CLK_SRC_SEL_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_ptp_ref_clk_en(&mut self) -> REG_EMAC_PTP_REF_CLK_EN_W { + REG_EMAC_PTP_REF_CLK_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_unused0_clk_en(&mut self) -> REG_EMAC_UNUSED0_CLK_EN_W { + REG_EMAC_UNUSED0_CLK_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_unused1_clk_en(&mut self) -> REG_EMAC_UNUSED1_CLK_EN_W { + REG_EMAC_UNUSED1_CLK_EN_W::new(self, 21) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_hs_mode(&mut self) -> REG_SDIO_HS_MODE_W { + REG_SDIO_HS_MODE_W::new(self, 22) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_clk_src_sel(&mut self) -> REG_SDIO_LS_CLK_SRC_SEL_W { + REG_SDIO_LS_CLK_SRC_SEL_W::new(self, 23) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_clk_en(&mut self) -> REG_SDIO_LS_CLK_EN_W { + REG_SDIO_LS_CLK_EN_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl01::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL01_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL01_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl01::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL01_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl01::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL01_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL01 to value 0x0401"] +impl crate::Resettable for PERI_CLK_CTRL01_SPEC { + const RESET_VALUE: Self::Ux = 0x0401; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl02.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl02.rs new file mode 100644 index 0000000000..dfb4bd72cc --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl02.rs @@ -0,0 +1,274 @@ +#[doc = "Register `PERI_CLK_CTRL02` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL02` writer"] +pub type W = crate::W; +#[doc = "Field `REG_SDIO_LS_CLK_DIV_NUM` reader - Reserved"] +pub type REG_SDIO_LS_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_SDIO_LS_CLK_DIV_NUM` writer - Reserved"] +pub type REG_SDIO_LS_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_SDIO_LS_CLK_EDGE_CFG_UPDATE` writer - Reserved"] +pub type REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SDIO_LS_CLK_EDGE_L` reader - Reserved"] +pub type REG_SDIO_LS_CLK_EDGE_L_R = crate::FieldReader; +#[doc = "Field `REG_SDIO_LS_CLK_EDGE_L` writer - Reserved"] +pub type REG_SDIO_LS_CLK_EDGE_L_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `REG_SDIO_LS_CLK_EDGE_H` reader - Reserved"] +pub type REG_SDIO_LS_CLK_EDGE_H_R = crate::FieldReader; +#[doc = "Field `REG_SDIO_LS_CLK_EDGE_H` writer - Reserved"] +pub type REG_SDIO_LS_CLK_EDGE_H_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `REG_SDIO_LS_CLK_EDGE_N` reader - Reserved"] +pub type REG_SDIO_LS_CLK_EDGE_N_R = crate::FieldReader; +#[doc = "Field `REG_SDIO_LS_CLK_EDGE_N` writer - Reserved"] +pub type REG_SDIO_LS_CLK_EDGE_N_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `REG_SDIO_LS_SLF_CLK_EDGE_SEL` reader - Reserved"] +pub type REG_SDIO_LS_SLF_CLK_EDGE_SEL_R = crate::FieldReader; +#[doc = "Field `REG_SDIO_LS_SLF_CLK_EDGE_SEL` writer - Reserved"] +pub type REG_SDIO_LS_SLF_CLK_EDGE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_SDIO_LS_DRV_CLK_EDGE_SEL` reader - Reserved"] +pub type REG_SDIO_LS_DRV_CLK_EDGE_SEL_R = crate::FieldReader; +#[doc = "Field `REG_SDIO_LS_DRV_CLK_EDGE_SEL` writer - Reserved"] +pub type REG_SDIO_LS_DRV_CLK_EDGE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_SDIO_LS_SAM_CLK_EDGE_SEL` reader - Reserved"] +pub type REG_SDIO_LS_SAM_CLK_EDGE_SEL_R = crate::FieldReader; +#[doc = "Field `REG_SDIO_LS_SAM_CLK_EDGE_SEL` writer - Reserved"] +pub type REG_SDIO_LS_SAM_CLK_EDGE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_SDIO_LS_SLF_CLK_EN` reader - Reserved"] +pub type REG_SDIO_LS_SLF_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_SDIO_LS_SLF_CLK_EN` writer - Reserved"] +pub type REG_SDIO_LS_SLF_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SDIO_LS_DRV_CLK_EN` reader - Reserved"] +pub type REG_SDIO_LS_DRV_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_SDIO_LS_DRV_CLK_EN` writer - Reserved"] +pub type REG_SDIO_LS_DRV_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SDIO_LS_SAM_CLK_EN` reader - Reserved"] +pub type REG_SDIO_LS_SAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_SDIO_LS_SAM_CLK_EN` writer - Reserved"] +pub type REG_SDIO_LS_SAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MIPI_DSI_DPHY_CLK_SRC_SEL` reader - Reserved"] +pub type REG_MIPI_DSI_DPHY_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_MIPI_DSI_DPHY_CLK_SRC_SEL` writer - Reserved"] +pub type REG_MIPI_DSI_DPHY_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_clk_div_num(&self) -> REG_SDIO_LS_CLK_DIV_NUM_R { + REG_SDIO_LS_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 9:12 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_clk_edge_l(&self) -> REG_SDIO_LS_CLK_EDGE_L_R { + REG_SDIO_LS_CLK_EDGE_L_R::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bits 13:16 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_clk_edge_h(&self) -> REG_SDIO_LS_CLK_EDGE_H_R { + REG_SDIO_LS_CLK_EDGE_H_R::new(((self.bits >> 13) & 0x0f) as u8) + } + #[doc = "Bits 17:20 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_clk_edge_n(&self) -> REG_SDIO_LS_CLK_EDGE_N_R { + REG_SDIO_LS_CLK_EDGE_N_R::new(((self.bits >> 17) & 0x0f) as u8) + } + #[doc = "Bits 21:22 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_slf_clk_edge_sel(&self) -> REG_SDIO_LS_SLF_CLK_EDGE_SEL_R { + REG_SDIO_LS_SLF_CLK_EDGE_SEL_R::new(((self.bits >> 21) & 3) as u8) + } + #[doc = "Bits 23:24 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_drv_clk_edge_sel(&self) -> REG_SDIO_LS_DRV_CLK_EDGE_SEL_R { + REG_SDIO_LS_DRV_CLK_EDGE_SEL_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bits 25:26 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_sam_clk_edge_sel(&self) -> REG_SDIO_LS_SAM_CLK_EDGE_SEL_R { + REG_SDIO_LS_SAM_CLK_EDGE_SEL_R::new(((self.bits >> 25) & 3) as u8) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_slf_clk_en(&self) -> REG_SDIO_LS_SLF_CLK_EN_R { + REG_SDIO_LS_SLF_CLK_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_drv_clk_en(&self) -> REG_SDIO_LS_DRV_CLK_EN_R { + REG_SDIO_LS_DRV_CLK_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_sdio_ls_sam_clk_en(&self) -> REG_SDIO_LS_SAM_CLK_EN_R { + REG_SDIO_LS_SAM_CLK_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bits 30:31 - Reserved"] + #[inline(always)] + pub fn reg_mipi_dsi_dphy_clk_src_sel(&self) -> REG_MIPI_DSI_DPHY_CLK_SRC_SEL_R { + REG_MIPI_DSI_DPHY_CLK_SRC_SEL_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL02") + .field( + "reg_sdio_ls_clk_div_num", + &format_args!("{}", self.reg_sdio_ls_clk_div_num().bits()), + ) + .field( + "reg_sdio_ls_clk_edge_l", + &format_args!("{}", self.reg_sdio_ls_clk_edge_l().bits()), + ) + .field( + "reg_sdio_ls_clk_edge_h", + &format_args!("{}", self.reg_sdio_ls_clk_edge_h().bits()), + ) + .field( + "reg_sdio_ls_clk_edge_n", + &format_args!("{}", self.reg_sdio_ls_clk_edge_n().bits()), + ) + .field( + "reg_sdio_ls_slf_clk_edge_sel", + &format_args!("{}", self.reg_sdio_ls_slf_clk_edge_sel().bits()), + ) + .field( + "reg_sdio_ls_drv_clk_edge_sel", + &format_args!("{}", self.reg_sdio_ls_drv_clk_edge_sel().bits()), + ) + .field( + "reg_sdio_ls_sam_clk_edge_sel", + &format_args!("{}", self.reg_sdio_ls_sam_clk_edge_sel().bits()), + ) + .field( + "reg_sdio_ls_slf_clk_en", + &format_args!("{}", self.reg_sdio_ls_slf_clk_en().bit()), + ) + .field( + "reg_sdio_ls_drv_clk_en", + &format_args!("{}", self.reg_sdio_ls_drv_clk_en().bit()), + ) + .field( + "reg_sdio_ls_sam_clk_en", + &format_args!("{}", self.reg_sdio_ls_sam_clk_en().bit()), + ) + .field( + "reg_mipi_dsi_dphy_clk_src_sel", + &format_args!("{}", self.reg_mipi_dsi_dphy_clk_src_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_clk_div_num(&mut self) -> REG_SDIO_LS_CLK_DIV_NUM_W { + REG_SDIO_LS_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_clk_edge_cfg_update( + &mut self, + ) -> REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_W { + REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_W::new(self, 8) + } + #[doc = "Bits 9:12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_clk_edge_l(&mut self) -> REG_SDIO_LS_CLK_EDGE_L_W { + REG_SDIO_LS_CLK_EDGE_L_W::new(self, 9) + } + #[doc = "Bits 13:16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_clk_edge_h(&mut self) -> REG_SDIO_LS_CLK_EDGE_H_W { + REG_SDIO_LS_CLK_EDGE_H_W::new(self, 13) + } + #[doc = "Bits 17:20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_clk_edge_n(&mut self) -> REG_SDIO_LS_CLK_EDGE_N_W { + REG_SDIO_LS_CLK_EDGE_N_W::new(self, 17) + } + #[doc = "Bits 21:22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_slf_clk_edge_sel( + &mut self, + ) -> REG_SDIO_LS_SLF_CLK_EDGE_SEL_W { + REG_SDIO_LS_SLF_CLK_EDGE_SEL_W::new(self, 21) + } + #[doc = "Bits 23:24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_drv_clk_edge_sel( + &mut self, + ) -> REG_SDIO_LS_DRV_CLK_EDGE_SEL_W { + REG_SDIO_LS_DRV_CLK_EDGE_SEL_W::new(self, 23) + } + #[doc = "Bits 25:26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_sam_clk_edge_sel( + &mut self, + ) -> REG_SDIO_LS_SAM_CLK_EDGE_SEL_W { + REG_SDIO_LS_SAM_CLK_EDGE_SEL_W::new(self, 25) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_slf_clk_en(&mut self) -> REG_SDIO_LS_SLF_CLK_EN_W { + REG_SDIO_LS_SLF_CLK_EN_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_drv_clk_en(&mut self) -> REG_SDIO_LS_DRV_CLK_EN_W { + REG_SDIO_LS_DRV_CLK_EN_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdio_ls_sam_clk_en(&mut self) -> REG_SDIO_LS_SAM_CLK_EN_W { + REG_SDIO_LS_SAM_CLK_EN_W::new(self, 29) + } + #[doc = "Bits 30:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mipi_dsi_dphy_clk_src_sel( + &mut self, + ) -> REG_MIPI_DSI_DPHY_CLK_SRC_SEL_W { + REG_MIPI_DSI_DPHY_CLK_SRC_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl02::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl02::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL02_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL02_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl02::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL02_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl02::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL02_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL02 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL02_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl03.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl03.rs new file mode 100644 index 0000000000..cccd562525 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl03.rs @@ -0,0 +1,192 @@ +#[doc = "Register `PERI_CLK_CTRL03` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL03` writer"] +pub type W = crate::W; +#[doc = "Field `REG_MIPI_DSI_DPHY_CFG_CLK_EN` reader - Reserved"] +pub type REG_MIPI_DSI_DPHY_CFG_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_MIPI_DSI_DPHY_CFG_CLK_EN` writer - Reserved"] +pub type REG_MIPI_DSI_DPHY_CFG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MIPI_DSI_DPHY_PLL_REFCLK_EN` reader - Reserved"] +pub type REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_R = crate::BitReader; +#[doc = "Field `REG_MIPI_DSI_DPHY_PLL_REFCLK_EN` writer - Reserved"] +pub type REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MIPI_CSI_DPHY_CLK_SRC_SEL` reader - Reserved"] +pub type REG_MIPI_CSI_DPHY_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_MIPI_CSI_DPHY_CLK_SRC_SEL` writer - Reserved"] +pub type REG_MIPI_CSI_DPHY_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_MIPI_CSI_DPHY_CFG_CLK_EN` reader - Reserved"] +pub type REG_MIPI_CSI_DPHY_CFG_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_MIPI_CSI_DPHY_CFG_CLK_EN` writer - Reserved"] +pub type REG_MIPI_CSI_DPHY_CFG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MIPI_DSI_DPICLK_SRC_SEL` reader - Reserved"] +pub type REG_MIPI_DSI_DPICLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_MIPI_DSI_DPICLK_SRC_SEL` writer - Reserved"] +pub type REG_MIPI_DSI_DPICLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_MIPI_DSI_DPICLK_EN` reader - Reserved"] +pub type REG_MIPI_DSI_DPICLK_EN_R = crate::BitReader; +#[doc = "Field `REG_MIPI_DSI_DPICLK_EN` writer - Reserved"] +pub type REG_MIPI_DSI_DPICLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MIPI_DSI_DPICLK_DIV_NUM` reader - Reserved"] +pub type REG_MIPI_DSI_DPICLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_MIPI_DSI_DPICLK_DIV_NUM` writer - Reserved"] +pub type REG_MIPI_DSI_DPICLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_mipi_dsi_dphy_cfg_clk_en(&self) -> REG_MIPI_DSI_DPHY_CFG_CLK_EN_R { + REG_MIPI_DSI_DPHY_CFG_CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_mipi_dsi_dphy_pll_refclk_en(&self) -> REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_R { + REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Reserved"] + #[inline(always)] + pub fn reg_mipi_csi_dphy_clk_src_sel(&self) -> REG_MIPI_CSI_DPHY_CLK_SRC_SEL_R { + REG_MIPI_CSI_DPHY_CLK_SRC_SEL_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_mipi_csi_dphy_cfg_clk_en(&self) -> REG_MIPI_CSI_DPHY_CFG_CLK_EN_R { + REG_MIPI_CSI_DPHY_CFG_CLK_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Reserved"] + #[inline(always)] + pub fn reg_mipi_dsi_dpiclk_src_sel(&self) -> REG_MIPI_DSI_DPICLK_SRC_SEL_R { + REG_MIPI_DSI_DPICLK_SRC_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_mipi_dsi_dpiclk_en(&self) -> REG_MIPI_DSI_DPICLK_EN_R { + REG_MIPI_DSI_DPICLK_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_mipi_dsi_dpiclk_div_num(&self) -> REG_MIPI_DSI_DPICLK_DIV_NUM_R { + REG_MIPI_DSI_DPICLK_DIV_NUM_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL03") + .field( + "reg_mipi_dsi_dphy_cfg_clk_en", + &format_args!("{}", self.reg_mipi_dsi_dphy_cfg_clk_en().bit()), + ) + .field( + "reg_mipi_dsi_dphy_pll_refclk_en", + &format_args!("{}", self.reg_mipi_dsi_dphy_pll_refclk_en().bit()), + ) + .field( + "reg_mipi_csi_dphy_clk_src_sel", + &format_args!("{}", self.reg_mipi_csi_dphy_clk_src_sel().bits()), + ) + .field( + "reg_mipi_csi_dphy_cfg_clk_en", + &format_args!("{}", self.reg_mipi_csi_dphy_cfg_clk_en().bit()), + ) + .field( + "reg_mipi_dsi_dpiclk_src_sel", + &format_args!("{}", self.reg_mipi_dsi_dpiclk_src_sel().bits()), + ) + .field( + "reg_mipi_dsi_dpiclk_en", + &format_args!("{}", self.reg_mipi_dsi_dpiclk_en().bit()), + ) + .field( + "reg_mipi_dsi_dpiclk_div_num", + &format_args!("{}", self.reg_mipi_dsi_dpiclk_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mipi_dsi_dphy_cfg_clk_en( + &mut self, + ) -> REG_MIPI_DSI_DPHY_CFG_CLK_EN_W { + REG_MIPI_DSI_DPHY_CFG_CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mipi_dsi_dphy_pll_refclk_en( + &mut self, + ) -> REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_W { + REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_W::new(self, 1) + } + #[doc = "Bits 2:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mipi_csi_dphy_clk_src_sel( + &mut self, + ) -> REG_MIPI_CSI_DPHY_CLK_SRC_SEL_W { + REG_MIPI_CSI_DPHY_CLK_SRC_SEL_W::new(self, 2) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mipi_csi_dphy_cfg_clk_en( + &mut self, + ) -> REG_MIPI_CSI_DPHY_CFG_CLK_EN_W { + REG_MIPI_CSI_DPHY_CFG_CLK_EN_W::new(self, 4) + } + #[doc = "Bits 5:6 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mipi_dsi_dpiclk_src_sel( + &mut self, + ) -> REG_MIPI_DSI_DPICLK_SRC_SEL_W { + REG_MIPI_DSI_DPICLK_SRC_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mipi_dsi_dpiclk_en(&mut self) -> REG_MIPI_DSI_DPICLK_EN_W { + REG_MIPI_DSI_DPICLK_EN_W::new(self, 7) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mipi_dsi_dpiclk_div_num( + &mut self, + ) -> REG_MIPI_DSI_DPICLK_DIV_NUM_W { + REG_MIPI_DSI_DPICLK_DIV_NUM_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl03::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl03::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL03_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL03_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl03::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL03_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl03::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL03_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL03 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL03_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl10.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl10.rs new file mode 100644 index 0000000000..cb4bbd4992 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl10.rs @@ -0,0 +1,184 @@ +#[doc = "Register `PERI_CLK_CTRL10` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL10` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2C0_CLK_SRC_SEL` reader - Reserved"] +pub type REG_I2C0_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_I2C0_CLK_SRC_SEL` writer - Reserved"] +pub type REG_I2C0_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2C0_CLK_EN` reader - Reserved"] +pub type REG_I2C0_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2C0_CLK_EN` writer - Reserved"] +pub type REG_I2C0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2C0_CLK_DIV_NUM` reader - Reserved"] +pub type REG_I2C0_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_I2C0_CLK_DIV_NUM` writer - Reserved"] +pub type REG_I2C0_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I2C0_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_I2C0_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_I2C0_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_I2C0_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I2C0_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_I2C0_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_I2C0_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_I2C0_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I2C1_CLK_SRC_SEL` reader - Reserved"] +pub type REG_I2C1_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_I2C1_CLK_SRC_SEL` writer - Reserved"] +pub type REG_I2C1_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2C1_CLK_EN` reader - Reserved"] +pub type REG_I2C1_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2C1_CLK_EN` writer - Reserved"] +pub type REG_I2C1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_i2c0_clk_src_sel(&self) -> REG_I2C0_CLK_SRC_SEL_R { + REG_I2C0_CLK_SRC_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_i2c0_clk_en(&self) -> REG_I2C0_CLK_EN_R { + REG_I2C0_CLK_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:9 - Reserved"] + #[inline(always)] + pub fn reg_i2c0_clk_div_num(&self) -> REG_I2C0_CLK_DIV_NUM_R { + REG_I2C0_CLK_DIV_NUM_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 10:17 - Reserved"] + #[inline(always)] + pub fn reg_i2c0_clk_div_numerator(&self) -> REG_I2C0_CLK_DIV_NUMERATOR_R { + REG_I2C0_CLK_DIV_NUMERATOR_R::new(((self.bits >> 10) & 0xff) as u8) + } + #[doc = "Bits 18:25 - Reserved"] + #[inline(always)] + pub fn reg_i2c0_clk_div_denominator(&self) -> REG_I2C0_CLK_DIV_DENOMINATOR_R { + REG_I2C0_CLK_DIV_DENOMINATOR_R::new(((self.bits >> 18) & 0xff) as u8) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_i2c1_clk_src_sel(&self) -> REG_I2C1_CLK_SRC_SEL_R { + REG_I2C1_CLK_SRC_SEL_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_i2c1_clk_en(&self) -> REG_I2C1_CLK_EN_R { + REG_I2C1_CLK_EN_R::new(((self.bits >> 27) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL10") + .field( + "reg_i2c0_clk_src_sel", + &format_args!("{}", self.reg_i2c0_clk_src_sel().bit()), + ) + .field( + "reg_i2c0_clk_en", + &format_args!("{}", self.reg_i2c0_clk_en().bit()), + ) + .field( + "reg_i2c0_clk_div_num", + &format_args!("{}", self.reg_i2c0_clk_div_num().bits()), + ) + .field( + "reg_i2c0_clk_div_numerator", + &format_args!("{}", self.reg_i2c0_clk_div_numerator().bits()), + ) + .field( + "reg_i2c0_clk_div_denominator", + &format_args!("{}", self.reg_i2c0_clk_div_denominator().bits()), + ) + .field( + "reg_i2c1_clk_src_sel", + &format_args!("{}", self.reg_i2c1_clk_src_sel().bit()), + ) + .field( + "reg_i2c1_clk_en", + &format_args!("{}", self.reg_i2c1_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c0_clk_src_sel(&mut self) -> REG_I2C0_CLK_SRC_SEL_W { + REG_I2C0_CLK_SRC_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c0_clk_en(&mut self) -> REG_I2C0_CLK_EN_W { + REG_I2C0_CLK_EN_W::new(self, 1) + } + #[doc = "Bits 2:9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c0_clk_div_num(&mut self) -> REG_I2C0_CLK_DIV_NUM_W { + REG_I2C0_CLK_DIV_NUM_W::new(self, 2) + } + #[doc = "Bits 10:17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c0_clk_div_numerator( + &mut self, + ) -> REG_I2C0_CLK_DIV_NUMERATOR_W { + REG_I2C0_CLK_DIV_NUMERATOR_W::new(self, 10) + } + #[doc = "Bits 18:25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c0_clk_div_denominator( + &mut self, + ) -> REG_I2C0_CLK_DIV_DENOMINATOR_W { + REG_I2C0_CLK_DIV_DENOMINATOR_W::new(self, 18) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c1_clk_src_sel(&mut self) -> REG_I2C1_CLK_SRC_SEL_W { + REG_I2C1_CLK_SRC_SEL_W::new(self, 26) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c1_clk_en(&mut self) -> REG_I2C1_CLK_EN_W { + REG_I2C1_CLK_EN_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL10_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl10::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl10::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL10_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL10 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl11.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl11.rs new file mode 100644 index 0000000000..54ea727ced --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl11.rs @@ -0,0 +1,146 @@ +#[doc = "Register `PERI_CLK_CTRL11` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL11` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2C1_CLK_DIV_NUM` reader - Reserved"] +pub type REG_I2C1_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_I2C1_CLK_DIV_NUM` writer - Reserved"] +pub type REG_I2C1_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I2C1_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_I2C1_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_I2C1_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_I2C1_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I2C1_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_I2C1_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_I2C1_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_I2C1_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I2S0_RX_CLK_EN` reader - Reserved"] +pub type REG_I2S0_RX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2S0_RX_CLK_EN` writer - Reserved"] +pub type REG_I2S0_RX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S0_RX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_I2S0_RX_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_I2S0_RX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_I2S0_RX_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_i2c1_clk_div_num(&self) -> REG_I2C1_CLK_DIV_NUM_R { + REG_I2C1_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_i2c1_clk_div_numerator(&self) -> REG_I2C1_CLK_DIV_NUMERATOR_R { + REG_I2C1_CLK_DIV_NUMERATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_i2c1_clk_div_denominator(&self) -> REG_I2C1_CLK_DIV_DENOMINATOR_R { + REG_I2C1_CLK_DIV_DENOMINATOR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_rx_clk_en(&self) -> REG_I2S0_RX_CLK_EN_R { + REG_I2S0_RX_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:26 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_rx_clk_src_sel(&self) -> REG_I2S0_RX_CLK_SRC_SEL_R { + REG_I2S0_RX_CLK_SRC_SEL_R::new(((self.bits >> 25) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL11") + .field( + "reg_i2c1_clk_div_num", + &format_args!("{}", self.reg_i2c1_clk_div_num().bits()), + ) + .field( + "reg_i2c1_clk_div_numerator", + &format_args!("{}", self.reg_i2c1_clk_div_numerator().bits()), + ) + .field( + "reg_i2c1_clk_div_denominator", + &format_args!("{}", self.reg_i2c1_clk_div_denominator().bits()), + ) + .field( + "reg_i2s0_rx_clk_en", + &format_args!("{}", self.reg_i2s0_rx_clk_en().bit()), + ) + .field( + "reg_i2s0_rx_clk_src_sel", + &format_args!("{}", self.reg_i2s0_rx_clk_src_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c1_clk_div_num(&mut self) -> REG_I2C1_CLK_DIV_NUM_W { + REG_I2C1_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c1_clk_div_numerator( + &mut self, + ) -> REG_I2C1_CLK_DIV_NUMERATOR_W { + REG_I2C1_CLK_DIV_NUMERATOR_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c1_clk_div_denominator( + &mut self, + ) -> REG_I2C1_CLK_DIV_DENOMINATOR_W { + REG_I2C1_CLK_DIV_DENOMINATOR_W::new(self, 16) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_rx_clk_en(&mut self) -> REG_I2S0_RX_CLK_EN_W { + REG_I2S0_RX_CLK_EN_W::new(self, 24) + } + #[doc = "Bits 25:26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_rx_clk_src_sel(&mut self) -> REG_I2S0_RX_CLK_SRC_SEL_W { + REG_I2S0_RX_CLK_SRC_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL11_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl11::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl11::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL11_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL11 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl110.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl110.rs new file mode 100644 index 0000000000..a7ab0e371e --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl110.rs @@ -0,0 +1,146 @@ +#[doc = "Register `PERI_CLK_CTRL110` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL110` writer"] +pub type W = crate::W; +#[doc = "Field `REG_LCD_CLK_DIV_NUM` reader - Reserved"] +pub type REG_LCD_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_LCD_CLK_DIV_NUM` writer - Reserved"] +pub type REG_LCD_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_LCD_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_LCD_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_LCD_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_LCD_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_LCD_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_LCD_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_LCD_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_LCD_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART0_CLK_SRC_SEL` reader - Reserved"] +pub type REG_UART0_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_UART0_CLK_SRC_SEL` writer - Reserved"] +pub type REG_UART0_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_UART0_CLK_EN` reader - Reserved"] +pub type REG_UART0_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART0_CLK_EN` writer - Reserved"] +pub type REG_UART0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_lcd_clk_div_num(&self) -> REG_LCD_CLK_DIV_NUM_R { + REG_LCD_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_lcd_clk_div_numerator(&self) -> REG_LCD_CLK_DIV_NUMERATOR_R { + REG_LCD_CLK_DIV_NUMERATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_lcd_clk_div_denominator(&self) -> REG_LCD_CLK_DIV_DENOMINATOR_R { + REG_LCD_CLK_DIV_DENOMINATOR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:25 - Reserved"] + #[inline(always)] + pub fn reg_uart0_clk_src_sel(&self) -> REG_UART0_CLK_SRC_SEL_R { + REG_UART0_CLK_SRC_SEL_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_uart0_clk_en(&self) -> REG_UART0_CLK_EN_R { + REG_UART0_CLK_EN_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL110") + .field( + "reg_lcd_clk_div_num", + &format_args!("{}", self.reg_lcd_clk_div_num().bits()), + ) + .field( + "reg_lcd_clk_div_numerator", + &format_args!("{}", self.reg_lcd_clk_div_numerator().bits()), + ) + .field( + "reg_lcd_clk_div_denominator", + &format_args!("{}", self.reg_lcd_clk_div_denominator().bits()), + ) + .field( + "reg_uart0_clk_src_sel", + &format_args!("{}", self.reg_uart0_clk_src_sel().bits()), + ) + .field( + "reg_uart0_clk_en", + &format_args!("{}", self.reg_uart0_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_lcd_clk_div_num(&mut self) -> REG_LCD_CLK_DIV_NUM_W { + REG_LCD_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_lcd_clk_div_numerator( + &mut self, + ) -> REG_LCD_CLK_DIV_NUMERATOR_W { + REG_LCD_CLK_DIV_NUMERATOR_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_lcd_clk_div_denominator( + &mut self, + ) -> REG_LCD_CLK_DIV_DENOMINATOR_W { + REG_LCD_CLK_DIV_DENOMINATOR_W::new(self, 16) + } + #[doc = "Bits 24:25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart0_clk_src_sel(&mut self) -> REG_UART0_CLK_SRC_SEL_W { + REG_UART0_CLK_SRC_SEL_W::new(self, 24) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart0_clk_en(&mut self) -> REG_UART0_CLK_EN_W { + REG_UART0_CLK_EN_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl110::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl110::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL110_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL110_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl110::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL110_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl110::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL110_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL110 to value 0x0400_0000"] +impl crate::Resettable for PERI_CLK_CTRL110_SPEC { + const RESET_VALUE: Self::Ux = 0x0400_0000; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl111.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl111.rs new file mode 100644 index 0000000000..995a3eddfb --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl111.rs @@ -0,0 +1,146 @@ +#[doc = "Register `PERI_CLK_CTRL111` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL111` writer"] +pub type W = crate::W; +#[doc = "Field `REG_UART0_SCLK_DIV_NUM` reader - Reserved"] +pub type REG_UART0_SCLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_UART0_SCLK_DIV_NUM` writer - Reserved"] +pub type REG_UART0_SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART0_SCLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_UART0_SCLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_UART0_SCLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_UART0_SCLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART0_SCLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_UART0_SCLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_UART0_SCLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_UART0_SCLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART1_CLK_SRC_SEL` reader - Reserved"] +pub type REG_UART1_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_UART1_CLK_SRC_SEL` writer - Reserved"] +pub type REG_UART1_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_UART1_CLK_EN` reader - Reserved"] +pub type REG_UART1_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART1_CLK_EN` writer - Reserved"] +pub type REG_UART1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_uart0_sclk_div_num(&self) -> REG_UART0_SCLK_DIV_NUM_R { + REG_UART0_SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_uart0_sclk_div_numerator(&self) -> REG_UART0_SCLK_DIV_NUMERATOR_R { + REG_UART0_SCLK_DIV_NUMERATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_uart0_sclk_div_denominator(&self) -> REG_UART0_SCLK_DIV_DENOMINATOR_R { + REG_UART0_SCLK_DIV_DENOMINATOR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:25 - Reserved"] + #[inline(always)] + pub fn reg_uart1_clk_src_sel(&self) -> REG_UART1_CLK_SRC_SEL_R { + REG_UART1_CLK_SRC_SEL_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_uart1_clk_en(&self) -> REG_UART1_CLK_EN_R { + REG_UART1_CLK_EN_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL111") + .field( + "reg_uart0_sclk_div_num", + &format_args!("{}", self.reg_uart0_sclk_div_num().bits()), + ) + .field( + "reg_uart0_sclk_div_numerator", + &format_args!("{}", self.reg_uart0_sclk_div_numerator().bits()), + ) + .field( + "reg_uart0_sclk_div_denominator", + &format_args!("{}", self.reg_uart0_sclk_div_denominator().bits()), + ) + .field( + "reg_uart1_clk_src_sel", + &format_args!("{}", self.reg_uart1_clk_src_sel().bits()), + ) + .field( + "reg_uart1_clk_en", + &format_args!("{}", self.reg_uart1_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart0_sclk_div_num(&mut self) -> REG_UART0_SCLK_DIV_NUM_W { + REG_UART0_SCLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart0_sclk_div_numerator( + &mut self, + ) -> REG_UART0_SCLK_DIV_NUMERATOR_W { + REG_UART0_SCLK_DIV_NUMERATOR_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart0_sclk_div_denominator( + &mut self, + ) -> REG_UART0_SCLK_DIV_DENOMINATOR_W { + REG_UART0_SCLK_DIV_DENOMINATOR_W::new(self, 16) + } + #[doc = "Bits 24:25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart1_clk_src_sel(&mut self) -> REG_UART1_CLK_SRC_SEL_W { + REG_UART1_CLK_SRC_SEL_W::new(self, 24) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart1_clk_en(&mut self) -> REG_UART1_CLK_EN_W { + REG_UART1_CLK_EN_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl111::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl111::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL111_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL111_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl111::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL111_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl111::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL111_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL111 to value 0x0400_0000"] +impl crate::Resettable for PERI_CLK_CTRL111_SPEC { + const RESET_VALUE: Self::Ux = 0x0400_0000; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl112.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl112.rs new file mode 100644 index 0000000000..b6840f9eab --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl112.rs @@ -0,0 +1,146 @@ +#[doc = "Register `PERI_CLK_CTRL112` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL112` writer"] +pub type W = crate::W; +#[doc = "Field `REG_UART1_SCLK_DIV_NUM` reader - Reserved"] +pub type REG_UART1_SCLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_UART1_SCLK_DIV_NUM` writer - Reserved"] +pub type REG_UART1_SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART1_SCLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_UART1_SCLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_UART1_SCLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_UART1_SCLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART1_SCLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_UART1_SCLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_UART1_SCLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_UART1_SCLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART2_CLK_SRC_SEL` reader - Reserved"] +pub type REG_UART2_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_UART2_CLK_SRC_SEL` writer - Reserved"] +pub type REG_UART2_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_UART2_CLK_EN` reader - Reserved"] +pub type REG_UART2_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART2_CLK_EN` writer - Reserved"] +pub type REG_UART2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_uart1_sclk_div_num(&self) -> REG_UART1_SCLK_DIV_NUM_R { + REG_UART1_SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_uart1_sclk_div_numerator(&self) -> REG_UART1_SCLK_DIV_NUMERATOR_R { + REG_UART1_SCLK_DIV_NUMERATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_uart1_sclk_div_denominator(&self) -> REG_UART1_SCLK_DIV_DENOMINATOR_R { + REG_UART1_SCLK_DIV_DENOMINATOR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:25 - Reserved"] + #[inline(always)] + pub fn reg_uart2_clk_src_sel(&self) -> REG_UART2_CLK_SRC_SEL_R { + REG_UART2_CLK_SRC_SEL_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_uart2_clk_en(&self) -> REG_UART2_CLK_EN_R { + REG_UART2_CLK_EN_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL112") + .field( + "reg_uart1_sclk_div_num", + &format_args!("{}", self.reg_uart1_sclk_div_num().bits()), + ) + .field( + "reg_uart1_sclk_div_numerator", + &format_args!("{}", self.reg_uart1_sclk_div_numerator().bits()), + ) + .field( + "reg_uart1_sclk_div_denominator", + &format_args!("{}", self.reg_uart1_sclk_div_denominator().bits()), + ) + .field( + "reg_uart2_clk_src_sel", + &format_args!("{}", self.reg_uart2_clk_src_sel().bits()), + ) + .field( + "reg_uart2_clk_en", + &format_args!("{}", self.reg_uart2_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart1_sclk_div_num(&mut self) -> REG_UART1_SCLK_DIV_NUM_W { + REG_UART1_SCLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart1_sclk_div_numerator( + &mut self, + ) -> REG_UART1_SCLK_DIV_NUMERATOR_W { + REG_UART1_SCLK_DIV_NUMERATOR_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart1_sclk_div_denominator( + &mut self, + ) -> REG_UART1_SCLK_DIV_DENOMINATOR_W { + REG_UART1_SCLK_DIV_DENOMINATOR_W::new(self, 16) + } + #[doc = "Bits 24:25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart2_clk_src_sel(&mut self) -> REG_UART2_CLK_SRC_SEL_W { + REG_UART2_CLK_SRC_SEL_W::new(self, 24) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart2_clk_en(&mut self) -> REG_UART2_CLK_EN_W { + REG_UART2_CLK_EN_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl112::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl112::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL112_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL112_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl112::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL112_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl112::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL112_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL112 to value 0x0400_0000"] +impl crate::Resettable for PERI_CLK_CTRL112_SPEC { + const RESET_VALUE: Self::Ux = 0x0400_0000; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl113.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl113.rs new file mode 100644 index 0000000000..6594eba4ca --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl113.rs @@ -0,0 +1,146 @@ +#[doc = "Register `PERI_CLK_CTRL113` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL113` writer"] +pub type W = crate::W; +#[doc = "Field `REG_UART2_SCLK_DIV_NUM` reader - Reserved"] +pub type REG_UART2_SCLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_UART2_SCLK_DIV_NUM` writer - Reserved"] +pub type REG_UART2_SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART2_SCLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_UART2_SCLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_UART2_SCLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_UART2_SCLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART2_SCLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_UART2_SCLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_UART2_SCLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_UART2_SCLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART3_CLK_SRC_SEL` reader - Reserved"] +pub type REG_UART3_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_UART3_CLK_SRC_SEL` writer - Reserved"] +pub type REG_UART3_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_UART3_CLK_EN` reader - Reserved"] +pub type REG_UART3_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART3_CLK_EN` writer - Reserved"] +pub type REG_UART3_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_uart2_sclk_div_num(&self) -> REG_UART2_SCLK_DIV_NUM_R { + REG_UART2_SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_uart2_sclk_div_numerator(&self) -> REG_UART2_SCLK_DIV_NUMERATOR_R { + REG_UART2_SCLK_DIV_NUMERATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_uart2_sclk_div_denominator(&self) -> REG_UART2_SCLK_DIV_DENOMINATOR_R { + REG_UART2_SCLK_DIV_DENOMINATOR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:25 - Reserved"] + #[inline(always)] + pub fn reg_uart3_clk_src_sel(&self) -> REG_UART3_CLK_SRC_SEL_R { + REG_UART3_CLK_SRC_SEL_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_uart3_clk_en(&self) -> REG_UART3_CLK_EN_R { + REG_UART3_CLK_EN_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL113") + .field( + "reg_uart2_sclk_div_num", + &format_args!("{}", self.reg_uart2_sclk_div_num().bits()), + ) + .field( + "reg_uart2_sclk_div_numerator", + &format_args!("{}", self.reg_uart2_sclk_div_numerator().bits()), + ) + .field( + "reg_uart2_sclk_div_denominator", + &format_args!("{}", self.reg_uart2_sclk_div_denominator().bits()), + ) + .field( + "reg_uart3_clk_src_sel", + &format_args!("{}", self.reg_uart3_clk_src_sel().bits()), + ) + .field( + "reg_uart3_clk_en", + &format_args!("{}", self.reg_uart3_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart2_sclk_div_num(&mut self) -> REG_UART2_SCLK_DIV_NUM_W { + REG_UART2_SCLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart2_sclk_div_numerator( + &mut self, + ) -> REG_UART2_SCLK_DIV_NUMERATOR_W { + REG_UART2_SCLK_DIV_NUMERATOR_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart2_sclk_div_denominator( + &mut self, + ) -> REG_UART2_SCLK_DIV_DENOMINATOR_W { + REG_UART2_SCLK_DIV_DENOMINATOR_W::new(self, 16) + } + #[doc = "Bits 24:25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart3_clk_src_sel(&mut self) -> REG_UART3_CLK_SRC_SEL_W { + REG_UART3_CLK_SRC_SEL_W::new(self, 24) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart3_clk_en(&mut self) -> REG_UART3_CLK_EN_W { + REG_UART3_CLK_EN_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl113::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl113::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL113_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL113_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl113::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL113_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl113::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL113_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL113 to value 0x0400_0000"] +impl crate::Resettable for PERI_CLK_CTRL113_SPEC { + const RESET_VALUE: Self::Ux = 0x0400_0000; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl114.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl114.rs new file mode 100644 index 0000000000..ee08f06fc4 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl114.rs @@ -0,0 +1,146 @@ +#[doc = "Register `PERI_CLK_CTRL114` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL114` writer"] +pub type W = crate::W; +#[doc = "Field `REG_UART3_SCLK_DIV_NUM` reader - Reserved"] +pub type REG_UART3_SCLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_UART3_SCLK_DIV_NUM` writer - Reserved"] +pub type REG_UART3_SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART3_SCLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_UART3_SCLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_UART3_SCLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_UART3_SCLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART3_SCLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_UART3_SCLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_UART3_SCLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_UART3_SCLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART4_CLK_SRC_SEL` reader - Reserved"] +pub type REG_UART4_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_UART4_CLK_SRC_SEL` writer - Reserved"] +pub type REG_UART4_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_UART4_CLK_EN` reader - Reserved"] +pub type REG_UART4_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART4_CLK_EN` writer - Reserved"] +pub type REG_UART4_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_uart3_sclk_div_num(&self) -> REG_UART3_SCLK_DIV_NUM_R { + REG_UART3_SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_uart3_sclk_div_numerator(&self) -> REG_UART3_SCLK_DIV_NUMERATOR_R { + REG_UART3_SCLK_DIV_NUMERATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_uart3_sclk_div_denominator(&self) -> REG_UART3_SCLK_DIV_DENOMINATOR_R { + REG_UART3_SCLK_DIV_DENOMINATOR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:25 - Reserved"] + #[inline(always)] + pub fn reg_uart4_clk_src_sel(&self) -> REG_UART4_CLK_SRC_SEL_R { + REG_UART4_CLK_SRC_SEL_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_uart4_clk_en(&self) -> REG_UART4_CLK_EN_R { + REG_UART4_CLK_EN_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL114") + .field( + "reg_uart3_sclk_div_num", + &format_args!("{}", self.reg_uart3_sclk_div_num().bits()), + ) + .field( + "reg_uart3_sclk_div_numerator", + &format_args!("{}", self.reg_uart3_sclk_div_numerator().bits()), + ) + .field( + "reg_uart3_sclk_div_denominator", + &format_args!("{}", self.reg_uart3_sclk_div_denominator().bits()), + ) + .field( + "reg_uart4_clk_src_sel", + &format_args!("{}", self.reg_uart4_clk_src_sel().bits()), + ) + .field( + "reg_uart4_clk_en", + &format_args!("{}", self.reg_uart4_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart3_sclk_div_num(&mut self) -> REG_UART3_SCLK_DIV_NUM_W { + REG_UART3_SCLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart3_sclk_div_numerator( + &mut self, + ) -> REG_UART3_SCLK_DIV_NUMERATOR_W { + REG_UART3_SCLK_DIV_NUMERATOR_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart3_sclk_div_denominator( + &mut self, + ) -> REG_UART3_SCLK_DIV_DENOMINATOR_W { + REG_UART3_SCLK_DIV_DENOMINATOR_W::new(self, 16) + } + #[doc = "Bits 24:25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart4_clk_src_sel(&mut self) -> REG_UART4_CLK_SRC_SEL_W { + REG_UART4_CLK_SRC_SEL_W::new(self, 24) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart4_clk_en(&mut self) -> REG_UART4_CLK_EN_W { + REG_UART4_CLK_EN_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl114::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl114::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL114_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL114_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl114::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL114_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl114::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL114_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL114 to value 0x0400_0000"] +impl crate::Resettable for PERI_CLK_CTRL114_SPEC { + const RESET_VALUE: Self::Ux = 0x0400_0000; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl115.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl115.rs new file mode 100644 index 0000000000..df49f8e261 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl115.rs @@ -0,0 +1,222 @@ +#[doc = "Register `PERI_CLK_CTRL115` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL115` writer"] +pub type W = crate::W; +#[doc = "Field `REG_UART4_SCLK_DIV_NUM` reader - Reserved"] +pub type REG_UART4_SCLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_UART4_SCLK_DIV_NUM` writer - Reserved"] +pub type REG_UART4_SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART4_SCLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_UART4_SCLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_UART4_SCLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_UART4_SCLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_UART4_SCLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_UART4_SCLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_UART4_SCLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_UART4_SCLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_TWAI0_CLK_SRC_SEL` reader - Reserved"] +pub type REG_TWAI0_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_TWAI0_CLK_SRC_SEL` writer - Reserved"] +pub type REG_TWAI0_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TWAI0_CLK_EN` reader - Reserved"] +pub type REG_TWAI0_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TWAI0_CLK_EN` writer - Reserved"] +pub type REG_TWAI0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TWAI1_CLK_SRC_SEL` reader - Reserved"] +pub type REG_TWAI1_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_TWAI1_CLK_SRC_SEL` writer - Reserved"] +pub type REG_TWAI1_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TWAI1_CLK_EN` reader - Reserved"] +pub type REG_TWAI1_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TWAI1_CLK_EN` writer - Reserved"] +pub type REG_TWAI1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TWAI2_CLK_SRC_SEL` reader - Reserved"] +pub type REG_TWAI2_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_TWAI2_CLK_SRC_SEL` writer - Reserved"] +pub type REG_TWAI2_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TWAI2_CLK_EN` reader - Reserved"] +pub type REG_TWAI2_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TWAI2_CLK_EN` writer - Reserved"] +pub type REG_TWAI2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_uart4_sclk_div_num(&self) -> REG_UART4_SCLK_DIV_NUM_R { + REG_UART4_SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_uart4_sclk_div_numerator(&self) -> REG_UART4_SCLK_DIV_NUMERATOR_R { + REG_UART4_SCLK_DIV_NUMERATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_uart4_sclk_div_denominator(&self) -> REG_UART4_SCLK_DIV_DENOMINATOR_R { + REG_UART4_SCLK_DIV_DENOMINATOR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_twai0_clk_src_sel(&self) -> REG_TWAI0_CLK_SRC_SEL_R { + REG_TWAI0_CLK_SRC_SEL_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + pub fn reg_twai0_clk_en(&self) -> REG_TWAI0_CLK_EN_R { + REG_TWAI0_CLK_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_twai1_clk_src_sel(&self) -> REG_TWAI1_CLK_SRC_SEL_R { + REG_TWAI1_CLK_SRC_SEL_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_twai1_clk_en(&self) -> REG_TWAI1_CLK_EN_R { + REG_TWAI1_CLK_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_twai2_clk_src_sel(&self) -> REG_TWAI2_CLK_SRC_SEL_R { + REG_TWAI2_CLK_SRC_SEL_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_twai2_clk_en(&self) -> REG_TWAI2_CLK_EN_R { + REG_TWAI2_CLK_EN_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL115") + .field( + "reg_uart4_sclk_div_num", + &format_args!("{}", self.reg_uart4_sclk_div_num().bits()), + ) + .field( + "reg_uart4_sclk_div_numerator", + &format_args!("{}", self.reg_uart4_sclk_div_numerator().bits()), + ) + .field( + "reg_uart4_sclk_div_denominator", + &format_args!("{}", self.reg_uart4_sclk_div_denominator().bits()), + ) + .field( + "reg_twai0_clk_src_sel", + &format_args!("{}", self.reg_twai0_clk_src_sel().bit()), + ) + .field( + "reg_twai0_clk_en", + &format_args!("{}", self.reg_twai0_clk_en().bit()), + ) + .field( + "reg_twai1_clk_src_sel", + &format_args!("{}", self.reg_twai1_clk_src_sel().bit()), + ) + .field( + "reg_twai1_clk_en", + &format_args!("{}", self.reg_twai1_clk_en().bit()), + ) + .field( + "reg_twai2_clk_src_sel", + &format_args!("{}", self.reg_twai2_clk_src_sel().bit()), + ) + .field( + "reg_twai2_clk_en", + &format_args!("{}", self.reg_twai2_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart4_sclk_div_num(&mut self) -> REG_UART4_SCLK_DIV_NUM_W { + REG_UART4_SCLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart4_sclk_div_numerator( + &mut self, + ) -> REG_UART4_SCLK_DIV_NUMERATOR_W { + REG_UART4_SCLK_DIV_NUMERATOR_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart4_sclk_div_denominator( + &mut self, + ) -> REG_UART4_SCLK_DIV_DENOMINATOR_W { + REG_UART4_SCLK_DIV_DENOMINATOR_W::new(self, 16) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_twai0_clk_src_sel(&mut self) -> REG_TWAI0_CLK_SRC_SEL_W { + REG_TWAI0_CLK_SRC_SEL_W::new(self, 24) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_twai0_clk_en(&mut self) -> REG_TWAI0_CLK_EN_W { + REG_TWAI0_CLK_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_twai1_clk_src_sel(&mut self) -> REG_TWAI1_CLK_SRC_SEL_W { + REG_TWAI1_CLK_SRC_SEL_W::new(self, 26) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_twai1_clk_en(&mut self) -> REG_TWAI1_CLK_EN_W { + REG_TWAI1_CLK_EN_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_twai2_clk_src_sel(&mut self) -> REG_TWAI2_CLK_SRC_SEL_W { + REG_TWAI2_CLK_SRC_SEL_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_twai2_clk_en(&mut self) -> REG_TWAI2_CLK_EN_W { + REG_TWAI2_CLK_EN_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl115::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl115::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL115_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL115_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl115::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL115_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl115::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL115_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL115 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL115_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl116.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl116.rs new file mode 100644 index 0000000000..ec924ce0a1 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl116.rs @@ -0,0 +1,184 @@ +#[doc = "Register `PERI_CLK_CTRL116` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL116` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPSPI2_CLK_SRC_SEL` reader - Reserved"] +pub type REG_GPSPI2_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPSPI2_CLK_SRC_SEL` writer - Reserved"] +pub type REG_GPSPI2_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPSPI2_HS_CLK_EN` reader - Reserved"] +pub type REG_GPSPI2_HS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_GPSPI2_HS_CLK_EN` writer - Reserved"] +pub type REG_GPSPI2_HS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPSPI2_HS_CLK_DIV_NUM` reader - Reserved"] +pub type REG_GPSPI2_HS_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_GPSPI2_HS_CLK_DIV_NUM` writer - Reserved"] +pub type REG_GPSPI2_HS_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_GPSPI2_MST_CLK_DIV_NUM` reader - Reserved"] +pub type REG_GPSPI2_MST_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_GPSPI2_MST_CLK_DIV_NUM` writer - Reserved"] +pub type REG_GPSPI2_MST_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_GPSPI2_MST_CLK_EN` reader - Reserved"] +pub type REG_GPSPI2_MST_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_GPSPI2_MST_CLK_EN` writer - Reserved"] +pub type REG_GPSPI2_MST_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPSPI3_CLK_SRC_SEL` reader - Reserved"] +pub type REG_GPSPI3_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPSPI3_CLK_SRC_SEL` writer - Reserved"] +pub type REG_GPSPI3_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPSPI3_HS_CLK_EN` reader - Reserved"] +pub type REG_GPSPI3_HS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_GPSPI3_HS_CLK_EN` writer - Reserved"] +pub type REG_GPSPI3_HS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - Reserved"] + #[inline(always)] + pub fn reg_gpspi2_clk_src_sel(&self) -> REG_GPSPI2_CLK_SRC_SEL_R { + REG_GPSPI2_CLK_SRC_SEL_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_gpspi2_hs_clk_en(&self) -> REG_GPSPI2_HS_CLK_EN_R { + REG_GPSPI2_HS_CLK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:11 - Reserved"] + #[inline(always)] + pub fn reg_gpspi2_hs_clk_div_num(&self) -> REG_GPSPI2_HS_CLK_DIV_NUM_R { + REG_GPSPI2_HS_CLK_DIV_NUM_R::new(((self.bits >> 4) & 0xff) as u8) + } + #[doc = "Bits 12:19 - Reserved"] + #[inline(always)] + pub fn reg_gpspi2_mst_clk_div_num(&self) -> REG_GPSPI2_MST_CLK_DIV_NUM_R { + REG_GPSPI2_MST_CLK_DIV_NUM_R::new(((self.bits >> 12) & 0xff) as u8) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_gpspi2_mst_clk_en(&self) -> REG_GPSPI2_MST_CLK_EN_R { + REG_GPSPI2_MST_CLK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:23 - Reserved"] + #[inline(always)] + pub fn reg_gpspi3_clk_src_sel(&self) -> REG_GPSPI3_CLK_SRC_SEL_R { + REG_GPSPI3_CLK_SRC_SEL_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_gpspi3_hs_clk_en(&self) -> REG_GPSPI3_HS_CLK_EN_R { + REG_GPSPI3_HS_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL116") + .field( + "reg_gpspi2_clk_src_sel", + &format_args!("{}", self.reg_gpspi2_clk_src_sel().bits()), + ) + .field( + "reg_gpspi2_hs_clk_en", + &format_args!("{}", self.reg_gpspi2_hs_clk_en().bit()), + ) + .field( + "reg_gpspi2_hs_clk_div_num", + &format_args!("{}", self.reg_gpspi2_hs_clk_div_num().bits()), + ) + .field( + "reg_gpspi2_mst_clk_div_num", + &format_args!("{}", self.reg_gpspi2_mst_clk_div_num().bits()), + ) + .field( + "reg_gpspi2_mst_clk_en", + &format_args!("{}", self.reg_gpspi2_mst_clk_en().bit()), + ) + .field( + "reg_gpspi3_clk_src_sel", + &format_args!("{}", self.reg_gpspi3_clk_src_sel().bits()), + ) + .field( + "reg_gpspi3_hs_clk_en", + &format_args!("{}", self.reg_gpspi3_hs_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi2_clk_src_sel(&mut self) -> REG_GPSPI2_CLK_SRC_SEL_W { + REG_GPSPI2_CLK_SRC_SEL_W::new(self, 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi2_hs_clk_en(&mut self) -> REG_GPSPI2_HS_CLK_EN_W { + REG_GPSPI2_HS_CLK_EN_W::new(self, 3) + } + #[doc = "Bits 4:11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi2_hs_clk_div_num( + &mut self, + ) -> REG_GPSPI2_HS_CLK_DIV_NUM_W { + REG_GPSPI2_HS_CLK_DIV_NUM_W::new(self, 4) + } + #[doc = "Bits 12:19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi2_mst_clk_div_num( + &mut self, + ) -> REG_GPSPI2_MST_CLK_DIV_NUM_W { + REG_GPSPI2_MST_CLK_DIV_NUM_W::new(self, 12) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi2_mst_clk_en(&mut self) -> REG_GPSPI2_MST_CLK_EN_W { + REG_GPSPI2_MST_CLK_EN_W::new(self, 20) + } + #[doc = "Bits 21:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi3_clk_src_sel(&mut self) -> REG_GPSPI3_CLK_SRC_SEL_W { + REG_GPSPI3_CLK_SRC_SEL_W::new(self, 21) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi3_hs_clk_en(&mut self) -> REG_GPSPI3_HS_CLK_EN_W { + REG_GPSPI3_HS_CLK_EN_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl116::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl116::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL116_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL116_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl116::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL116_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl116::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL116_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL116 to value 0x0110_0008"] +impl crate::Resettable for PERI_CLK_CTRL116_SPEC { + const RESET_VALUE: Self::Ux = 0x0110_0008; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl117.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl117.rs new file mode 100644 index 0000000000..6ab751fb2e --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl117.rs @@ -0,0 +1,169 @@ +#[doc = "Register `PERI_CLK_CTRL117` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL117` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPSPI3_HS_CLK_DIV_NUM` reader - Reserved"] +pub type REG_GPSPI3_HS_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_GPSPI3_HS_CLK_DIV_NUM` writer - Reserved"] +pub type REG_GPSPI3_HS_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_GPSPI3_MST_CLK_DIV_NUM` reader - Reserved"] +pub type REG_GPSPI3_MST_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_GPSPI3_MST_CLK_DIV_NUM` writer - Reserved"] +pub type REG_GPSPI3_MST_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_GPSPI3_MST_CLK_EN` reader - Reserved"] +pub type REG_GPSPI3_MST_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_GPSPI3_MST_CLK_EN` writer - Reserved"] +pub type REG_GPSPI3_MST_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PARLIO_RX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_PARLIO_RX_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PARLIO_RX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_PARLIO_RX_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PARLIO_RX_CLK_EN` reader - Reserved"] +pub type REG_PARLIO_RX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PARLIO_RX_CLK_EN` writer - Reserved"] +pub type REG_PARLIO_RX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PARLIO_RX_CLK_DIV_NUM` reader - Reserved"] +pub type REG_PARLIO_RX_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_PARLIO_RX_CLK_DIV_NUM` writer - Reserved"] +pub type REG_PARLIO_RX_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_gpspi3_hs_clk_div_num(&self) -> REG_GPSPI3_HS_CLK_DIV_NUM_R { + REG_GPSPI3_HS_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_gpspi3_mst_clk_div_num(&self) -> REG_GPSPI3_MST_CLK_DIV_NUM_R { + REG_GPSPI3_MST_CLK_DIV_NUM_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_gpspi3_mst_clk_en(&self) -> REG_GPSPI3_MST_CLK_EN_R { + REG_GPSPI3_MST_CLK_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:18 - Reserved"] + #[inline(always)] + pub fn reg_parlio_rx_clk_src_sel(&self) -> REG_PARLIO_RX_CLK_SRC_SEL_R { + REG_PARLIO_RX_CLK_SRC_SEL_R::new(((self.bits >> 17) & 3) as u8) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_parlio_rx_clk_en(&self) -> REG_PARLIO_RX_CLK_EN_R { + REG_PARLIO_RX_CLK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:27 - Reserved"] + #[inline(always)] + pub fn reg_parlio_rx_clk_div_num(&self) -> REG_PARLIO_RX_CLK_DIV_NUM_R { + REG_PARLIO_RX_CLK_DIV_NUM_R::new(((self.bits >> 20) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL117") + .field( + "reg_gpspi3_hs_clk_div_num", + &format_args!("{}", self.reg_gpspi3_hs_clk_div_num().bits()), + ) + .field( + "reg_gpspi3_mst_clk_div_num", + &format_args!("{}", self.reg_gpspi3_mst_clk_div_num().bits()), + ) + .field( + "reg_gpspi3_mst_clk_en", + &format_args!("{}", self.reg_gpspi3_mst_clk_en().bit()), + ) + .field( + "reg_parlio_rx_clk_src_sel", + &format_args!("{}", self.reg_parlio_rx_clk_src_sel().bits()), + ) + .field( + "reg_parlio_rx_clk_en", + &format_args!("{}", self.reg_parlio_rx_clk_en().bit()), + ) + .field( + "reg_parlio_rx_clk_div_num", + &format_args!("{}", self.reg_parlio_rx_clk_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi3_hs_clk_div_num( + &mut self, + ) -> REG_GPSPI3_HS_CLK_DIV_NUM_W { + REG_GPSPI3_HS_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi3_mst_clk_div_num( + &mut self, + ) -> REG_GPSPI3_MST_CLK_DIV_NUM_W { + REG_GPSPI3_MST_CLK_DIV_NUM_W::new(self, 8) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi3_mst_clk_en(&mut self) -> REG_GPSPI3_MST_CLK_EN_W { + REG_GPSPI3_MST_CLK_EN_W::new(self, 16) + } + #[doc = "Bits 17:18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_rx_clk_src_sel( + &mut self, + ) -> REG_PARLIO_RX_CLK_SRC_SEL_W { + REG_PARLIO_RX_CLK_SRC_SEL_W::new(self, 17) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_rx_clk_en(&mut self) -> REG_PARLIO_RX_CLK_EN_W { + REG_PARLIO_RX_CLK_EN_W::new(self, 19) + } + #[doc = "Bits 20:27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_rx_clk_div_num( + &mut self, + ) -> REG_PARLIO_RX_CLK_DIV_NUM_W { + REG_PARLIO_RX_CLK_DIV_NUM_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl117::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl117::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL117_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL117_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl117::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL117_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl117::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL117_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL117 to value 0x0001_0000"] +impl crate::Resettable for PERI_CLK_CTRL117_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0000; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl118.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl118.rs new file mode 100644 index 0000000000..cdfb5c6ce1 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl118.rs @@ -0,0 +1,150 @@ +#[doc = "Register `PERI_CLK_CTRL118` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL118` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PARLIO_RX_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_PARLIO_RX_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_PARLIO_RX_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_PARLIO_RX_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_PARLIO_RX_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_PARLIO_RX_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_PARLIO_RX_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_PARLIO_RX_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_PARLIO_TX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_PARLIO_TX_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PARLIO_TX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_PARLIO_TX_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PARLIO_TX_CLK_EN` reader - Reserved"] +pub type REG_PARLIO_TX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PARLIO_TX_CLK_EN` writer - Reserved"] +pub type REG_PARLIO_TX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PARLIO_TX_CLK_DIV_NUM` reader - Reserved"] +pub type REG_PARLIO_TX_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_PARLIO_TX_CLK_DIV_NUM` writer - Reserved"] +pub type REG_PARLIO_TX_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_parlio_rx_clk_div_numerator(&self) -> REG_PARLIO_RX_CLK_DIV_NUMERATOR_R { + REG_PARLIO_RX_CLK_DIV_NUMERATOR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_parlio_rx_clk_div_denominator(&self) -> REG_PARLIO_RX_CLK_DIV_DENOMINATOR_R { + REG_PARLIO_RX_CLK_DIV_DENOMINATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:17 - Reserved"] + #[inline(always)] + pub fn reg_parlio_tx_clk_src_sel(&self) -> REG_PARLIO_TX_CLK_SRC_SEL_R { + REG_PARLIO_TX_CLK_SRC_SEL_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_parlio_tx_clk_en(&self) -> REG_PARLIO_TX_CLK_EN_R { + REG_PARLIO_TX_CLK_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:26 - Reserved"] + #[inline(always)] + pub fn reg_parlio_tx_clk_div_num(&self) -> REG_PARLIO_TX_CLK_DIV_NUM_R { + REG_PARLIO_TX_CLK_DIV_NUM_R::new(((self.bits >> 19) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL118") + .field( + "reg_parlio_rx_clk_div_numerator", + &format_args!("{}", self.reg_parlio_rx_clk_div_numerator().bits()), + ) + .field( + "reg_parlio_rx_clk_div_denominator", + &format_args!("{}", self.reg_parlio_rx_clk_div_denominator().bits()), + ) + .field( + "reg_parlio_tx_clk_src_sel", + &format_args!("{}", self.reg_parlio_tx_clk_src_sel().bits()), + ) + .field( + "reg_parlio_tx_clk_en", + &format_args!("{}", self.reg_parlio_tx_clk_en().bit()), + ) + .field( + "reg_parlio_tx_clk_div_num", + &format_args!("{}", self.reg_parlio_tx_clk_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_rx_clk_div_numerator( + &mut self, + ) -> REG_PARLIO_RX_CLK_DIV_NUMERATOR_W { + REG_PARLIO_RX_CLK_DIV_NUMERATOR_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_rx_clk_div_denominator( + &mut self, + ) -> REG_PARLIO_RX_CLK_DIV_DENOMINATOR_W { + REG_PARLIO_RX_CLK_DIV_DENOMINATOR_W::new(self, 8) + } + #[doc = "Bits 16:17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_tx_clk_src_sel( + &mut self, + ) -> REG_PARLIO_TX_CLK_SRC_SEL_W { + REG_PARLIO_TX_CLK_SRC_SEL_W::new(self, 16) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_tx_clk_en(&mut self) -> REG_PARLIO_TX_CLK_EN_W { + REG_PARLIO_TX_CLK_EN_W::new(self, 18) + } + #[doc = "Bits 19:26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_tx_clk_div_num( + &mut self, + ) -> REG_PARLIO_TX_CLK_DIV_NUM_W { + REG_PARLIO_TX_CLK_DIV_NUM_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl118::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl118::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL118_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL118_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl118::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL118_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl118::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL118_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL118 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL118_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl119.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl119.rs new file mode 100644 index 0000000000..1271007644 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl119.rs @@ -0,0 +1,184 @@ +#[doc = "Register `PERI_CLK_CTRL119` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL119` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PARLIO_TX_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_PARLIO_TX_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_PARLIO_TX_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_PARLIO_TX_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_PARLIO_TX_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_PARLIO_TX_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_PARLIO_TX_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_PARLIO_TX_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I3C_MST_CLK_SRC_SEL` reader - Reserved"] +pub type REG_I3C_MST_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_CLK_SRC_SEL` writer - Reserved"] +pub type REG_I3C_MST_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_I3C_MST_CLK_EN` reader - Reserved"] +pub type REG_I3C_MST_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I3C_MST_CLK_EN` writer - Reserved"] +pub type REG_I3C_MST_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I3C_MST_CLK_DIV_NUM` reader - Reserved"] +pub type REG_I3C_MST_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_CLK_DIV_NUM` writer - Reserved"] +pub type REG_I3C_MST_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_CAM_CLK_SRC_SEL` reader - Reserved"] +pub type REG_CAM_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_CAM_CLK_SRC_SEL` writer - Reserved"] +pub type REG_CAM_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_CAM_CLK_EN` reader - Reserved"] +pub type REG_CAM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CAM_CLK_EN` writer - Reserved"] +pub type REG_CAM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_parlio_tx_clk_div_numerator(&self) -> REG_PARLIO_TX_CLK_DIV_NUMERATOR_R { + REG_PARLIO_TX_CLK_DIV_NUMERATOR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_parlio_tx_clk_div_denominator(&self) -> REG_PARLIO_TX_CLK_DIV_DENOMINATOR_R { + REG_PARLIO_TX_CLK_DIV_DENOMINATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:17 - Reserved"] + #[inline(always)] + pub fn reg_i3c_mst_clk_src_sel(&self) -> REG_I3C_MST_CLK_SRC_SEL_R { + REG_I3C_MST_CLK_SRC_SEL_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_i3c_mst_clk_en(&self) -> REG_I3C_MST_CLK_EN_R { + REG_I3C_MST_CLK_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:26 - Reserved"] + #[inline(always)] + pub fn reg_i3c_mst_clk_div_num(&self) -> REG_I3C_MST_CLK_DIV_NUM_R { + REG_I3C_MST_CLK_DIV_NUM_R::new(((self.bits >> 19) & 0xff) as u8) + } + #[doc = "Bits 27:28 - Reserved"] + #[inline(always)] + pub fn reg_cam_clk_src_sel(&self) -> REG_CAM_CLK_SRC_SEL_R { + REG_CAM_CLK_SRC_SEL_R::new(((self.bits >> 27) & 3) as u8) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_cam_clk_en(&self) -> REG_CAM_CLK_EN_R { + REG_CAM_CLK_EN_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL119") + .field( + "reg_parlio_tx_clk_div_numerator", + &format_args!("{}", self.reg_parlio_tx_clk_div_numerator().bits()), + ) + .field( + "reg_parlio_tx_clk_div_denominator", + &format_args!("{}", self.reg_parlio_tx_clk_div_denominator().bits()), + ) + .field( + "reg_i3c_mst_clk_src_sel", + &format_args!("{}", self.reg_i3c_mst_clk_src_sel().bits()), + ) + .field( + "reg_i3c_mst_clk_en", + &format_args!("{}", self.reg_i3c_mst_clk_en().bit()), + ) + .field( + "reg_i3c_mst_clk_div_num", + &format_args!("{}", self.reg_i3c_mst_clk_div_num().bits()), + ) + .field( + "reg_cam_clk_src_sel", + &format_args!("{}", self.reg_cam_clk_src_sel().bits()), + ) + .field( + "reg_cam_clk_en", + &format_args!("{}", self.reg_cam_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_tx_clk_div_numerator( + &mut self, + ) -> REG_PARLIO_TX_CLK_DIV_NUMERATOR_W { + REG_PARLIO_TX_CLK_DIV_NUMERATOR_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_tx_clk_div_denominator( + &mut self, + ) -> REG_PARLIO_TX_CLK_DIV_DENOMINATOR_W { + REG_PARLIO_TX_CLK_DIV_DENOMINATOR_W::new(self, 8) + } + #[doc = "Bits 16:17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_clk_src_sel(&mut self) -> REG_I3C_MST_CLK_SRC_SEL_W { + REG_I3C_MST_CLK_SRC_SEL_W::new(self, 16) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_clk_en(&mut self) -> REG_I3C_MST_CLK_EN_W { + REG_I3C_MST_CLK_EN_W::new(self, 18) + } + #[doc = "Bits 19:26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_clk_div_num(&mut self) -> REG_I3C_MST_CLK_DIV_NUM_W { + REG_I3C_MST_CLK_DIV_NUM_W::new(self, 19) + } + #[doc = "Bits 27:28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_cam_clk_src_sel(&mut self) -> REG_CAM_CLK_SRC_SEL_W { + REG_CAM_CLK_SRC_SEL_W::new(self, 27) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_cam_clk_en(&mut self) -> REG_CAM_CLK_EN_W { + REG_CAM_CLK_EN_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl119::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl119::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL119_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL119_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl119::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL119_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl119::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL119_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL119 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL119_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl12.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl12.rs new file mode 100644 index 0000000000..3577f915e9 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl12.rs @@ -0,0 +1,104 @@ +#[doc = "Register `PERI_CLK_CTRL12` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL12` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2S0_RX_DIV_N` reader - Reserved"] +pub type REG_I2S0_RX_DIV_N_R = crate::FieldReader; +#[doc = "Field `REG_I2S0_RX_DIV_N` writer - Reserved"] +pub type REG_I2S0_RX_DIV_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I2S0_RX_DIV_X` reader - Reserved"] +pub type REG_I2S0_RX_DIV_X_R = crate::FieldReader; +#[doc = "Field `REG_I2S0_RX_DIV_X` writer - Reserved"] +pub type REG_I2S0_RX_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S0_RX_DIV_Y` reader - Reserved"] +pub type REG_I2S0_RX_DIV_Y_R = crate::FieldReader; +#[doc = "Field `REG_I2S0_RX_DIV_Y` writer - Reserved"] +pub type REG_I2S0_RX_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_rx_div_n(&self) -> REG_I2S0_RX_DIV_N_R { + REG_I2S0_RX_DIV_N_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:16 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_rx_div_x(&self) -> REG_I2S0_RX_DIV_X_R { + REG_I2S0_RX_DIV_X_R::new(((self.bits >> 8) & 0x01ff) as u16) + } + #[doc = "Bits 17:25 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_rx_div_y(&self) -> REG_I2S0_RX_DIV_Y_R { + REG_I2S0_RX_DIV_Y_R::new(((self.bits >> 17) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL12") + .field( + "reg_i2s0_rx_div_n", + &format_args!("{}", self.reg_i2s0_rx_div_n().bits()), + ) + .field( + "reg_i2s0_rx_div_x", + &format_args!("{}", self.reg_i2s0_rx_div_x().bits()), + ) + .field( + "reg_i2s0_rx_div_y", + &format_args!("{}", self.reg_i2s0_rx_div_y().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_rx_div_n(&mut self) -> REG_I2S0_RX_DIV_N_W { + REG_I2S0_RX_DIV_N_W::new(self, 0) + } + #[doc = "Bits 8:16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_rx_div_x(&mut self) -> REG_I2S0_RX_DIV_X_W { + REG_I2S0_RX_DIV_X_W::new(self, 8) + } + #[doc = "Bits 17:25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_rx_div_y(&mut self) -> REG_I2S0_RX_DIV_Y_W { + REG_I2S0_RX_DIV_Y_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL12_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl12::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl12::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL12_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL12 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl120.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl120.rs new file mode 100644 index 0000000000..4e53d88fda --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl120.rs @@ -0,0 +1,108 @@ +#[doc = "Register `PERI_CLK_CTRL120` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL120` writer"] +pub type W = crate::W; +#[doc = "Field `REG_CAM_CLK_DIV_NUM` reader - Reserved"] +pub type REG_CAM_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_CAM_CLK_DIV_NUM` writer - Reserved"] +pub type REG_CAM_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_CAM_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_CAM_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_CAM_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_CAM_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_CAM_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_CAM_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_CAM_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_CAM_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_cam_clk_div_num(&self) -> REG_CAM_CLK_DIV_NUM_R { + REG_CAM_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_cam_clk_div_numerator(&self) -> REG_CAM_CLK_DIV_NUMERATOR_R { + REG_CAM_CLK_DIV_NUMERATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_cam_clk_div_denominator(&self) -> REG_CAM_CLK_DIV_DENOMINATOR_R { + REG_CAM_CLK_DIV_DENOMINATOR_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL120") + .field( + "reg_cam_clk_div_num", + &format_args!("{}", self.reg_cam_clk_div_num().bits()), + ) + .field( + "reg_cam_clk_div_numerator", + &format_args!("{}", self.reg_cam_clk_div_numerator().bits()), + ) + .field( + "reg_cam_clk_div_denominator", + &format_args!("{}", self.reg_cam_clk_div_denominator().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_cam_clk_div_num(&mut self) -> REG_CAM_CLK_DIV_NUM_W { + REG_CAM_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_cam_clk_div_numerator( + &mut self, + ) -> REG_CAM_CLK_DIV_NUMERATOR_W { + REG_CAM_CLK_DIV_NUMERATOR_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_cam_clk_div_denominator( + &mut self, + ) -> REG_CAM_CLK_DIV_DENOMINATOR_W { + REG_CAM_CLK_DIV_DENOMINATOR_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl120::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl120::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL120_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL120_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl120::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL120_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl120::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL120_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL120 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL120_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl13.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl13.rs new file mode 100644 index 0000000000..3402758257 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl13.rs @@ -0,0 +1,161 @@ +#[doc = "Register `PERI_CLK_CTRL13` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL13` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2S0_RX_DIV_Z` reader - Reserved"] +pub type REG_I2S0_RX_DIV_Z_R = crate::FieldReader; +#[doc = "Field `REG_I2S0_RX_DIV_Z` writer - Reserved"] +pub type REG_I2S0_RX_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S0_RX_DIV_YN1` reader - Reserved"] +pub type REG_I2S0_RX_DIV_YN1_R = crate::BitReader; +#[doc = "Field `REG_I2S0_RX_DIV_YN1` writer - Reserved"] +pub type REG_I2S0_RX_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S0_TX_CLK_EN` reader - Reserved"] +pub type REG_I2S0_TX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2S0_TX_CLK_EN` writer - Reserved"] +pub type REG_I2S0_TX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S0_TX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_I2S0_TX_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_I2S0_TX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_I2S0_TX_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_I2S0_TX_DIV_N` reader - Reserved"] +pub type REG_I2S0_TX_DIV_N_R = crate::FieldReader; +#[doc = "Field `REG_I2S0_TX_DIV_N` writer - Reserved"] +pub type REG_I2S0_TX_DIV_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I2S0_TX_DIV_X` reader - Reserved"] +pub type REG_I2S0_TX_DIV_X_R = crate::FieldReader; +#[doc = "Field `REG_I2S0_TX_DIV_X` writer - Reserved"] +pub type REG_I2S0_TX_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_rx_div_z(&self) -> REG_I2S0_RX_DIV_Z_R { + REG_I2S0_RX_DIV_Z_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_rx_div_yn1(&self) -> REG_I2S0_RX_DIV_YN1_R { + REG_I2S0_RX_DIV_YN1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_tx_clk_en(&self) -> REG_I2S0_TX_CLK_EN_R { + REG_I2S0_TX_CLK_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 11:12 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_tx_clk_src_sel(&self) -> REG_I2S0_TX_CLK_SRC_SEL_R { + REG_I2S0_TX_CLK_SRC_SEL_R::new(((self.bits >> 11) & 3) as u8) + } + #[doc = "Bits 13:20 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_tx_div_n(&self) -> REG_I2S0_TX_DIV_N_R { + REG_I2S0_TX_DIV_N_R::new(((self.bits >> 13) & 0xff) as u8) + } + #[doc = "Bits 21:29 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_tx_div_x(&self) -> REG_I2S0_TX_DIV_X_R { + REG_I2S0_TX_DIV_X_R::new(((self.bits >> 21) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL13") + .field( + "reg_i2s0_rx_div_z", + &format_args!("{}", self.reg_i2s0_rx_div_z().bits()), + ) + .field( + "reg_i2s0_rx_div_yn1", + &format_args!("{}", self.reg_i2s0_rx_div_yn1().bit()), + ) + .field( + "reg_i2s0_tx_clk_en", + &format_args!("{}", self.reg_i2s0_tx_clk_en().bit()), + ) + .field( + "reg_i2s0_tx_clk_src_sel", + &format_args!("{}", self.reg_i2s0_tx_clk_src_sel().bits()), + ) + .field( + "reg_i2s0_tx_div_n", + &format_args!("{}", self.reg_i2s0_tx_div_n().bits()), + ) + .field( + "reg_i2s0_tx_div_x", + &format_args!("{}", self.reg_i2s0_tx_div_x().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_rx_div_z(&mut self) -> REG_I2S0_RX_DIV_Z_W { + REG_I2S0_RX_DIV_Z_W::new(self, 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_rx_div_yn1(&mut self) -> REG_I2S0_RX_DIV_YN1_W { + REG_I2S0_RX_DIV_YN1_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_tx_clk_en(&mut self) -> REG_I2S0_TX_CLK_EN_W { + REG_I2S0_TX_CLK_EN_W::new(self, 10) + } + #[doc = "Bits 11:12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_tx_clk_src_sel(&mut self) -> REG_I2S0_TX_CLK_SRC_SEL_W { + REG_I2S0_TX_CLK_SRC_SEL_W::new(self, 11) + } + #[doc = "Bits 13:20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_tx_div_n(&mut self) -> REG_I2S0_TX_DIV_N_W { + REG_I2S0_TX_DIV_N_W::new(self, 13) + } + #[doc = "Bits 21:29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_tx_div_x(&mut self) -> REG_I2S0_TX_DIV_X_W { + REG_I2S0_TX_DIV_X_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL13_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl13::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl13::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL13_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL13 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL13_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl14.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl14.rs new file mode 100644 index 0000000000..01d08e6522 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl14.rs @@ -0,0 +1,180 @@ +#[doc = "Register `PERI_CLK_CTRL14` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL14` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2S0_TX_DIV_Y` reader - Reserved"] +pub type REG_I2S0_TX_DIV_Y_R = crate::FieldReader; +#[doc = "Field `REG_I2S0_TX_DIV_Y` writer - Reserved"] +pub type REG_I2S0_TX_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S0_TX_DIV_Z` reader - Reserved"] +pub type REG_I2S0_TX_DIV_Z_R = crate::FieldReader; +#[doc = "Field `REG_I2S0_TX_DIV_Z` writer - Reserved"] +pub type REG_I2S0_TX_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S0_TX_DIV_YN1` reader - Reserved"] +pub type REG_I2S0_TX_DIV_YN1_R = crate::BitReader; +#[doc = "Field `REG_I2S0_TX_DIV_YN1` writer - Reserved"] +pub type REG_I2S0_TX_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S0_MST_CLK_SEL` reader - Reserved"] +pub type REG_I2S0_MST_CLK_SEL_R = crate::BitReader; +#[doc = "Field `REG_I2S0_MST_CLK_SEL` writer - Reserved"] +pub type REG_I2S0_MST_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S1_RX_CLK_EN` reader - Reserved"] +pub type REG_I2S1_RX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2S1_RX_CLK_EN` writer - Reserved"] +pub type REG_I2S1_RX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S1_RX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_I2S1_RX_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_I2S1_RX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_I2S1_RX_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_I2S1_RX_DIV_N` reader - Reserved"] +pub type REG_I2S1_RX_DIV_N_R = crate::FieldReader; +#[doc = "Field `REG_I2S1_RX_DIV_N` writer - Reserved"] +pub type REG_I2S1_RX_DIV_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_tx_div_y(&self) -> REG_I2S0_TX_DIV_Y_R { + REG_I2S0_TX_DIV_Y_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:17 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_tx_div_z(&self) -> REG_I2S0_TX_DIV_Z_R { + REG_I2S0_TX_DIV_Z_R::new(((self.bits >> 9) & 0x01ff) as u16) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_tx_div_yn1(&self) -> REG_I2S0_TX_DIV_YN1_R { + REG_I2S0_TX_DIV_YN1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_mst_clk_sel(&self) -> REG_I2S0_MST_CLK_SEL_R { + REG_I2S0_MST_CLK_SEL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_rx_clk_en(&self) -> REG_I2S1_RX_CLK_EN_R { + REG_I2S1_RX_CLK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:22 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_rx_clk_src_sel(&self) -> REG_I2S1_RX_CLK_SRC_SEL_R { + REG_I2S1_RX_CLK_SRC_SEL_R::new(((self.bits >> 21) & 3) as u8) + } + #[doc = "Bits 23:30 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_rx_div_n(&self) -> REG_I2S1_RX_DIV_N_R { + REG_I2S1_RX_DIV_N_R::new(((self.bits >> 23) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL14") + .field( + "reg_i2s0_tx_div_y", + &format_args!("{}", self.reg_i2s0_tx_div_y().bits()), + ) + .field( + "reg_i2s0_tx_div_z", + &format_args!("{}", self.reg_i2s0_tx_div_z().bits()), + ) + .field( + "reg_i2s0_tx_div_yn1", + &format_args!("{}", self.reg_i2s0_tx_div_yn1().bit()), + ) + .field( + "reg_i2s0_mst_clk_sel", + &format_args!("{}", self.reg_i2s0_mst_clk_sel().bit()), + ) + .field( + "reg_i2s1_rx_clk_en", + &format_args!("{}", self.reg_i2s1_rx_clk_en().bit()), + ) + .field( + "reg_i2s1_rx_clk_src_sel", + &format_args!("{}", self.reg_i2s1_rx_clk_src_sel().bits()), + ) + .field( + "reg_i2s1_rx_div_n", + &format_args!("{}", self.reg_i2s1_rx_div_n().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_tx_div_y(&mut self) -> REG_I2S0_TX_DIV_Y_W { + REG_I2S0_TX_DIV_Y_W::new(self, 0) + } + #[doc = "Bits 9:17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_tx_div_z(&mut self) -> REG_I2S0_TX_DIV_Z_W { + REG_I2S0_TX_DIV_Z_W::new(self, 9) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_tx_div_yn1(&mut self) -> REG_I2S0_TX_DIV_YN1_W { + REG_I2S0_TX_DIV_YN1_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_mst_clk_sel(&mut self) -> REG_I2S0_MST_CLK_SEL_W { + REG_I2S0_MST_CLK_SEL_W::new(self, 19) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_rx_clk_en(&mut self) -> REG_I2S1_RX_CLK_EN_W { + REG_I2S1_RX_CLK_EN_W::new(self, 20) + } + #[doc = "Bits 21:22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_rx_clk_src_sel(&mut self) -> REG_I2S1_RX_CLK_SRC_SEL_W { + REG_I2S1_RX_CLK_SRC_SEL_W::new(self, 21) + } + #[doc = "Bits 23:30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_rx_div_n(&mut self) -> REG_I2S1_RX_DIV_N_W { + REG_I2S1_RX_DIV_N_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL14_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl14::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl14::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL14_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL14 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL14_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl15.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl15.rs new file mode 100644 index 0000000000..053572d77d --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl15.rs @@ -0,0 +1,161 @@ +#[doc = "Register `PERI_CLK_CTRL15` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL15` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2S1_RX_DIV_X` reader - Reserved"] +pub type REG_I2S1_RX_DIV_X_R = crate::FieldReader; +#[doc = "Field `REG_I2S1_RX_DIV_X` writer - Reserved"] +pub type REG_I2S1_RX_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S1_RX_DIV_Y` reader - Reserved"] +pub type REG_I2S1_RX_DIV_Y_R = crate::FieldReader; +#[doc = "Field `REG_I2S1_RX_DIV_Y` writer - Reserved"] +pub type REG_I2S1_RX_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S1_RX_DIV_Z` reader - Reserved"] +pub type REG_I2S1_RX_DIV_Z_R = crate::FieldReader; +#[doc = "Field `REG_I2S1_RX_DIV_Z` writer - Reserved"] +pub type REG_I2S1_RX_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S1_RX_DIV_YN1` reader - Reserved"] +pub type REG_I2S1_RX_DIV_YN1_R = crate::BitReader; +#[doc = "Field `REG_I2S1_RX_DIV_YN1` writer - Reserved"] +pub type REG_I2S1_RX_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S1_TX_CLK_EN` reader - Reserved"] +pub type REG_I2S1_TX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2S1_TX_CLK_EN` writer - Reserved"] +pub type REG_I2S1_TX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S1_TX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_I2S1_TX_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_I2S1_TX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_I2S1_TX_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_rx_div_x(&self) -> REG_I2S1_RX_DIV_X_R { + REG_I2S1_RX_DIV_X_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:17 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_rx_div_y(&self) -> REG_I2S1_RX_DIV_Y_R { + REG_I2S1_RX_DIV_Y_R::new(((self.bits >> 9) & 0x01ff) as u16) + } + #[doc = "Bits 18:26 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_rx_div_z(&self) -> REG_I2S1_RX_DIV_Z_R { + REG_I2S1_RX_DIV_Z_R::new(((self.bits >> 18) & 0x01ff) as u16) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_rx_div_yn1(&self) -> REG_I2S1_RX_DIV_YN1_R { + REG_I2S1_RX_DIV_YN1_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_tx_clk_en(&self) -> REG_I2S1_TX_CLK_EN_R { + REG_I2S1_TX_CLK_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bits 29:30 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_tx_clk_src_sel(&self) -> REG_I2S1_TX_CLK_SRC_SEL_R { + REG_I2S1_TX_CLK_SRC_SEL_R::new(((self.bits >> 29) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL15") + .field( + "reg_i2s1_rx_div_x", + &format_args!("{}", self.reg_i2s1_rx_div_x().bits()), + ) + .field( + "reg_i2s1_rx_div_y", + &format_args!("{}", self.reg_i2s1_rx_div_y().bits()), + ) + .field( + "reg_i2s1_rx_div_z", + &format_args!("{}", self.reg_i2s1_rx_div_z().bits()), + ) + .field( + "reg_i2s1_rx_div_yn1", + &format_args!("{}", self.reg_i2s1_rx_div_yn1().bit()), + ) + .field( + "reg_i2s1_tx_clk_en", + &format_args!("{}", self.reg_i2s1_tx_clk_en().bit()), + ) + .field( + "reg_i2s1_tx_clk_src_sel", + &format_args!("{}", self.reg_i2s1_tx_clk_src_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_rx_div_x(&mut self) -> REG_I2S1_RX_DIV_X_W { + REG_I2S1_RX_DIV_X_W::new(self, 0) + } + #[doc = "Bits 9:17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_rx_div_y(&mut self) -> REG_I2S1_RX_DIV_Y_W { + REG_I2S1_RX_DIV_Y_W::new(self, 9) + } + #[doc = "Bits 18:26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_rx_div_z(&mut self) -> REG_I2S1_RX_DIV_Z_W { + REG_I2S1_RX_DIV_Z_W::new(self, 18) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_rx_div_yn1(&mut self) -> REG_I2S1_RX_DIV_YN1_W { + REG_I2S1_RX_DIV_YN1_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_tx_clk_en(&mut self) -> REG_I2S1_TX_CLK_EN_W { + REG_I2S1_TX_CLK_EN_W::new(self, 28) + } + #[doc = "Bits 29:30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_tx_clk_src_sel(&mut self) -> REG_I2S1_TX_CLK_SRC_SEL_W { + REG_I2S1_TX_CLK_SRC_SEL_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL15_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl15::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl15::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL15_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL15 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL15_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl16.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl16.rs new file mode 100644 index 0000000000..dfbe840c71 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl16.rs @@ -0,0 +1,104 @@ +#[doc = "Register `PERI_CLK_CTRL16` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL16` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2S1_TX_DIV_N` reader - Reserved"] +pub type REG_I2S1_TX_DIV_N_R = crate::FieldReader; +#[doc = "Field `REG_I2S1_TX_DIV_N` writer - Reserved"] +pub type REG_I2S1_TX_DIV_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I2S1_TX_DIV_X` reader - Reserved"] +pub type REG_I2S1_TX_DIV_X_R = crate::FieldReader; +#[doc = "Field `REG_I2S1_TX_DIV_X` writer - Reserved"] +pub type REG_I2S1_TX_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S1_TX_DIV_Y` reader - Reserved"] +pub type REG_I2S1_TX_DIV_Y_R = crate::FieldReader; +#[doc = "Field `REG_I2S1_TX_DIV_Y` writer - Reserved"] +pub type REG_I2S1_TX_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_tx_div_n(&self) -> REG_I2S1_TX_DIV_N_R { + REG_I2S1_TX_DIV_N_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:16 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_tx_div_x(&self) -> REG_I2S1_TX_DIV_X_R { + REG_I2S1_TX_DIV_X_R::new(((self.bits >> 8) & 0x01ff) as u16) + } + #[doc = "Bits 17:25 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_tx_div_y(&self) -> REG_I2S1_TX_DIV_Y_R { + REG_I2S1_TX_DIV_Y_R::new(((self.bits >> 17) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL16") + .field( + "reg_i2s1_tx_div_n", + &format_args!("{}", self.reg_i2s1_tx_div_n().bits()), + ) + .field( + "reg_i2s1_tx_div_x", + &format_args!("{}", self.reg_i2s1_tx_div_x().bits()), + ) + .field( + "reg_i2s1_tx_div_y", + &format_args!("{}", self.reg_i2s1_tx_div_y().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_tx_div_n(&mut self) -> REG_I2S1_TX_DIV_N_W { + REG_I2S1_TX_DIV_N_W::new(self, 0) + } + #[doc = "Bits 8:16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_tx_div_x(&mut self) -> REG_I2S1_TX_DIV_X_W { + REG_I2S1_TX_DIV_X_W::new(self, 8) + } + #[doc = "Bits 17:25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_tx_div_y(&mut self) -> REG_I2S1_TX_DIV_Y_W { + REG_I2S1_TX_DIV_Y_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl16::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl16::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL16_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL16_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl16::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL16_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl16::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL16_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL16 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL16_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl17.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl17.rs new file mode 100644 index 0000000000..90f4140532 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl17.rs @@ -0,0 +1,180 @@ +#[doc = "Register `PERI_CLK_CTRL17` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL17` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2S1_TX_DIV_Z` reader - Reserved"] +pub type REG_I2S1_TX_DIV_Z_R = crate::FieldReader; +#[doc = "Field `REG_I2S1_TX_DIV_Z` writer - Reserved"] +pub type REG_I2S1_TX_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S1_TX_DIV_YN1` reader - Reserved"] +pub type REG_I2S1_TX_DIV_YN1_R = crate::BitReader; +#[doc = "Field `REG_I2S1_TX_DIV_YN1` writer - Reserved"] +pub type REG_I2S1_TX_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S1_MST_CLK_SEL` reader - Reserved"] +pub type REG_I2S1_MST_CLK_SEL_R = crate::BitReader; +#[doc = "Field `REG_I2S1_MST_CLK_SEL` writer - Reserved"] +pub type REG_I2S1_MST_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S2_RX_CLK_EN` reader - Reserved"] +pub type REG_I2S2_RX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2S2_RX_CLK_EN` writer - Reserved"] +pub type REG_I2S2_RX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S2_RX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_I2S2_RX_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_I2S2_RX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_I2S2_RX_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_I2S2_RX_DIV_N` reader - Reserved"] +pub type REG_I2S2_RX_DIV_N_R = crate::FieldReader; +#[doc = "Field `REG_I2S2_RX_DIV_N` writer - Reserved"] +pub type REG_I2S2_RX_DIV_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I2S2_RX_DIV_X` reader - Reserved"] +pub type REG_I2S2_RX_DIV_X_R = crate::FieldReader; +#[doc = "Field `REG_I2S2_RX_DIV_X` writer - Reserved"] +pub type REG_I2S2_RX_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_tx_div_z(&self) -> REG_I2S1_TX_DIV_Z_R { + REG_I2S1_TX_DIV_Z_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_tx_div_yn1(&self) -> REG_I2S1_TX_DIV_YN1_R { + REG_I2S1_TX_DIV_YN1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_mst_clk_sel(&self) -> REG_I2S1_MST_CLK_SEL_R { + REG_I2S1_MST_CLK_SEL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_rx_clk_en(&self) -> REG_I2S2_RX_CLK_EN_R { + REG_I2S2_RX_CLK_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:13 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_rx_clk_src_sel(&self) -> REG_I2S2_RX_CLK_SRC_SEL_R { + REG_I2S2_RX_CLK_SRC_SEL_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:21 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_rx_div_n(&self) -> REG_I2S2_RX_DIV_N_R { + REG_I2S2_RX_DIV_N_R::new(((self.bits >> 14) & 0xff) as u8) + } + #[doc = "Bits 22:30 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_rx_div_x(&self) -> REG_I2S2_RX_DIV_X_R { + REG_I2S2_RX_DIV_X_R::new(((self.bits >> 22) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL17") + .field( + "reg_i2s1_tx_div_z", + &format_args!("{}", self.reg_i2s1_tx_div_z().bits()), + ) + .field( + "reg_i2s1_tx_div_yn1", + &format_args!("{}", self.reg_i2s1_tx_div_yn1().bit()), + ) + .field( + "reg_i2s1_mst_clk_sel", + &format_args!("{}", self.reg_i2s1_mst_clk_sel().bit()), + ) + .field( + "reg_i2s2_rx_clk_en", + &format_args!("{}", self.reg_i2s2_rx_clk_en().bit()), + ) + .field( + "reg_i2s2_rx_clk_src_sel", + &format_args!("{}", self.reg_i2s2_rx_clk_src_sel().bits()), + ) + .field( + "reg_i2s2_rx_div_n", + &format_args!("{}", self.reg_i2s2_rx_div_n().bits()), + ) + .field( + "reg_i2s2_rx_div_x", + &format_args!("{}", self.reg_i2s2_rx_div_x().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_tx_div_z(&mut self) -> REG_I2S1_TX_DIV_Z_W { + REG_I2S1_TX_DIV_Z_W::new(self, 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_tx_div_yn1(&mut self) -> REG_I2S1_TX_DIV_YN1_W { + REG_I2S1_TX_DIV_YN1_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_mst_clk_sel(&mut self) -> REG_I2S1_MST_CLK_SEL_W { + REG_I2S1_MST_CLK_SEL_W::new(self, 10) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_rx_clk_en(&mut self) -> REG_I2S2_RX_CLK_EN_W { + REG_I2S2_RX_CLK_EN_W::new(self, 11) + } + #[doc = "Bits 12:13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_rx_clk_src_sel(&mut self) -> REG_I2S2_RX_CLK_SRC_SEL_W { + REG_I2S2_RX_CLK_SRC_SEL_W::new(self, 12) + } + #[doc = "Bits 14:21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_rx_div_n(&mut self) -> REG_I2S2_RX_DIV_N_W { + REG_I2S2_RX_DIV_N_W::new(self, 14) + } + #[doc = "Bits 22:30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_rx_div_x(&mut self) -> REG_I2S2_RX_DIV_X_W { + REG_I2S2_RX_DIV_X_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl17::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl17::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL17_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL17_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl17::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL17_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl17::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL17_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL17 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL17_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl18.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl18.rs new file mode 100644 index 0000000000..397e23991a --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl18.rs @@ -0,0 +1,161 @@ +#[doc = "Register `PERI_CLK_CTRL18` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL18` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2S2_RX_DIV_Y` reader - Reserved"] +pub type REG_I2S2_RX_DIV_Y_R = crate::FieldReader; +#[doc = "Field `REG_I2S2_RX_DIV_Y` writer - Reserved"] +pub type REG_I2S2_RX_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S2_RX_DIV_Z` reader - Reserved"] +pub type REG_I2S2_RX_DIV_Z_R = crate::FieldReader; +#[doc = "Field `REG_I2S2_RX_DIV_Z` writer - Reserved"] +pub type REG_I2S2_RX_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S2_RX_DIV_YN1` reader - Reserved"] +pub type REG_I2S2_RX_DIV_YN1_R = crate::BitReader; +#[doc = "Field `REG_I2S2_RX_DIV_YN1` writer - Reserved"] +pub type REG_I2S2_RX_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S2_TX_CLK_EN` reader - Reserved"] +pub type REG_I2S2_TX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2S2_TX_CLK_EN` writer - Reserved"] +pub type REG_I2S2_TX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S2_TX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_I2S2_TX_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_I2S2_TX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_I2S2_TX_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_I2S2_TX_DIV_N` reader - Reserved"] +pub type REG_I2S2_TX_DIV_N_R = crate::FieldReader; +#[doc = "Field `REG_I2S2_TX_DIV_N` writer - Reserved"] +pub type REG_I2S2_TX_DIV_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_rx_div_y(&self) -> REG_I2S2_RX_DIV_Y_R { + REG_I2S2_RX_DIV_Y_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:17 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_rx_div_z(&self) -> REG_I2S2_RX_DIV_Z_R { + REG_I2S2_RX_DIV_Z_R::new(((self.bits >> 9) & 0x01ff) as u16) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_rx_div_yn1(&self) -> REG_I2S2_RX_DIV_YN1_R { + REG_I2S2_RX_DIV_YN1_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_tx_clk_en(&self) -> REG_I2S2_TX_CLK_EN_R { + REG_I2S2_TX_CLK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:21 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_tx_clk_src_sel(&self) -> REG_I2S2_TX_CLK_SRC_SEL_R { + REG_I2S2_TX_CLK_SRC_SEL_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:29 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_tx_div_n(&self) -> REG_I2S2_TX_DIV_N_R { + REG_I2S2_TX_DIV_N_R::new(((self.bits >> 22) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL18") + .field( + "reg_i2s2_rx_div_y", + &format_args!("{}", self.reg_i2s2_rx_div_y().bits()), + ) + .field( + "reg_i2s2_rx_div_z", + &format_args!("{}", self.reg_i2s2_rx_div_z().bits()), + ) + .field( + "reg_i2s2_rx_div_yn1", + &format_args!("{}", self.reg_i2s2_rx_div_yn1().bit()), + ) + .field( + "reg_i2s2_tx_clk_en", + &format_args!("{}", self.reg_i2s2_tx_clk_en().bit()), + ) + .field( + "reg_i2s2_tx_clk_src_sel", + &format_args!("{}", self.reg_i2s2_tx_clk_src_sel().bits()), + ) + .field( + "reg_i2s2_tx_div_n", + &format_args!("{}", self.reg_i2s2_tx_div_n().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_rx_div_y(&mut self) -> REG_I2S2_RX_DIV_Y_W { + REG_I2S2_RX_DIV_Y_W::new(self, 0) + } + #[doc = "Bits 9:17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_rx_div_z(&mut self) -> REG_I2S2_RX_DIV_Z_W { + REG_I2S2_RX_DIV_Z_W::new(self, 9) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_rx_div_yn1(&mut self) -> REG_I2S2_RX_DIV_YN1_W { + REG_I2S2_RX_DIV_YN1_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_tx_clk_en(&mut self) -> REG_I2S2_TX_CLK_EN_W { + REG_I2S2_TX_CLK_EN_W::new(self, 19) + } + #[doc = "Bits 20:21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_tx_clk_src_sel(&mut self) -> REG_I2S2_TX_CLK_SRC_SEL_W { + REG_I2S2_TX_CLK_SRC_SEL_W::new(self, 20) + } + #[doc = "Bits 22:29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_tx_div_n(&mut self) -> REG_I2S2_TX_DIV_N_W { + REG_I2S2_TX_DIV_N_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl18::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl18::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL18_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL18_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl18::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL18_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl18::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL18_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL18 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL18_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl19.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl19.rs new file mode 100644 index 0000000000..b39d897803 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl19.rs @@ -0,0 +1,180 @@ +#[doc = "Register `PERI_CLK_CTRL19` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL19` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2S2_TX_DIV_X` reader - Reserved"] +pub type REG_I2S2_TX_DIV_X_R = crate::FieldReader; +#[doc = "Field `REG_I2S2_TX_DIV_X` writer - Reserved"] +pub type REG_I2S2_TX_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S2_TX_DIV_Y` reader - Reserved"] +pub type REG_I2S2_TX_DIV_Y_R = crate::FieldReader; +#[doc = "Field `REG_I2S2_TX_DIV_Y` writer - Reserved"] +pub type REG_I2S2_TX_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S2_TX_DIV_Z` reader - Reserved"] +pub type REG_I2S2_TX_DIV_Z_R = crate::FieldReader; +#[doc = "Field `REG_I2S2_TX_DIV_Z` writer - Reserved"] +pub type REG_I2S2_TX_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_I2S2_TX_DIV_YN1` reader - Reserved"] +pub type REG_I2S2_TX_DIV_YN1_R = crate::BitReader; +#[doc = "Field `REG_I2S2_TX_DIV_YN1` writer - Reserved"] +pub type REG_I2S2_TX_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S2_MST_CLK_SEL` reader - Reserved"] +pub type REG_I2S2_MST_CLK_SEL_R = crate::BitReader; +#[doc = "Field `REG_I2S2_MST_CLK_SEL` writer - Reserved"] +pub type REG_I2S2_MST_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_LCD_CLK_SRC_SEL` reader - Reserved"] +pub type REG_LCD_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_LCD_CLK_SRC_SEL` writer - Reserved"] +pub type REG_LCD_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_LCD_CLK_EN` reader - Reserved"] +pub type REG_LCD_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_LCD_CLK_EN` writer - Reserved"] +pub type REG_LCD_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_tx_div_x(&self) -> REG_I2S2_TX_DIV_X_R { + REG_I2S2_TX_DIV_X_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:17 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_tx_div_y(&self) -> REG_I2S2_TX_DIV_Y_R { + REG_I2S2_TX_DIV_Y_R::new(((self.bits >> 9) & 0x01ff) as u16) + } + #[doc = "Bits 18:26 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_tx_div_z(&self) -> REG_I2S2_TX_DIV_Z_R { + REG_I2S2_TX_DIV_Z_R::new(((self.bits >> 18) & 0x01ff) as u16) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_tx_div_yn1(&self) -> REG_I2S2_TX_DIV_YN1_R { + REG_I2S2_TX_DIV_YN1_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_mst_clk_sel(&self) -> REG_I2S2_MST_CLK_SEL_R { + REG_I2S2_MST_CLK_SEL_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bits 29:30 - Reserved"] + #[inline(always)] + pub fn reg_lcd_clk_src_sel(&self) -> REG_LCD_CLK_SRC_SEL_R { + REG_LCD_CLK_SRC_SEL_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn reg_lcd_clk_en(&self) -> REG_LCD_CLK_EN_R { + REG_LCD_CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL19") + .field( + "reg_i2s2_tx_div_x", + &format_args!("{}", self.reg_i2s2_tx_div_x().bits()), + ) + .field( + "reg_i2s2_tx_div_y", + &format_args!("{}", self.reg_i2s2_tx_div_y().bits()), + ) + .field( + "reg_i2s2_tx_div_z", + &format_args!("{}", self.reg_i2s2_tx_div_z().bits()), + ) + .field( + "reg_i2s2_tx_div_yn1", + &format_args!("{}", self.reg_i2s2_tx_div_yn1().bit()), + ) + .field( + "reg_i2s2_mst_clk_sel", + &format_args!("{}", self.reg_i2s2_mst_clk_sel().bit()), + ) + .field( + "reg_lcd_clk_src_sel", + &format_args!("{}", self.reg_lcd_clk_src_sel().bits()), + ) + .field( + "reg_lcd_clk_en", + &format_args!("{}", self.reg_lcd_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_tx_div_x(&mut self) -> REG_I2S2_TX_DIV_X_W { + REG_I2S2_TX_DIV_X_W::new(self, 0) + } + #[doc = "Bits 9:17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_tx_div_y(&mut self) -> REG_I2S2_TX_DIV_Y_W { + REG_I2S2_TX_DIV_Y_W::new(self, 9) + } + #[doc = "Bits 18:26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_tx_div_z(&mut self) -> REG_I2S2_TX_DIV_Z_W { + REG_I2S2_TX_DIV_Z_W::new(self, 18) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_tx_div_yn1(&mut self) -> REG_I2S2_TX_DIV_YN1_W { + REG_I2S2_TX_DIV_YN1_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_mst_clk_sel(&mut self) -> REG_I2S2_MST_CLK_SEL_W { + REG_I2S2_MST_CLK_SEL_W::new(self, 28) + } + #[doc = "Bits 29:30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_lcd_clk_src_sel(&mut self) -> REG_LCD_CLK_SRC_SEL_W { + REG_LCD_CLK_SRC_SEL_W::new(self, 29) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_lcd_clk_en(&mut self) -> REG_LCD_CLK_EN_W { + REG_LCD_CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl19::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl19::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL19_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL19_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl19::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL19_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl19::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL19_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL19 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL19_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl20.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl20.rs new file mode 100644 index 0000000000..2063fdea66 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl20.rs @@ -0,0 +1,298 @@ +#[doc = "Register `PERI_CLK_CTRL20` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL20` writer"] +pub type W = crate::W; +#[doc = "Field `REG_MCPWM0_CLK_SRC_SEL` reader - Reserved"] +pub type REG_MCPWM0_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_MCPWM0_CLK_SRC_SEL` writer - Reserved"] +pub type REG_MCPWM0_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_MCPWM0_CLK_EN` reader - Reserved"] +pub type REG_MCPWM0_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_MCPWM0_CLK_EN` writer - Reserved"] +pub type REG_MCPWM0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MCPWM0_CLK_DIV_NUM` reader - Reserved"] +pub type REG_MCPWM0_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_MCPWM0_CLK_DIV_NUM` writer - Reserved"] +pub type REG_MCPWM0_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_MCPWM1_CLK_SRC_SEL` reader - Reserved"] +pub type REG_MCPWM1_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_MCPWM1_CLK_SRC_SEL` writer - Reserved"] +pub type REG_MCPWM1_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_MCPWM1_CLK_EN` reader - Reserved"] +pub type REG_MCPWM1_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_MCPWM1_CLK_EN` writer - Reserved"] +pub type REG_MCPWM1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MCPWM1_CLK_DIV_NUM` reader - Reserved"] +pub type REG_MCPWM1_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_MCPWM1_CLK_DIV_NUM` writer - Reserved"] +pub type REG_MCPWM1_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_TIMERGRP0_T0_SRC_SEL` reader - Reserved"] +pub type REG_TIMERGRP0_T0_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_TIMERGRP0_T0_SRC_SEL` writer - Reserved"] +pub type REG_TIMERGRP0_T0_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_TIMERGRP0_T0_CLK_EN` reader - Reserved"] +pub type REG_TIMERGRP0_T0_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TIMERGRP0_T0_CLK_EN` writer - Reserved"] +pub type REG_TIMERGRP0_T0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TIMERGRP0_T1_SRC_SEL` reader - Reserved"] +pub type REG_TIMERGRP0_T1_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_TIMERGRP0_T1_SRC_SEL` writer - Reserved"] +pub type REG_TIMERGRP0_T1_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_TIMERGRP0_T1_CLK_EN` reader - Reserved"] +pub type REG_TIMERGRP0_T1_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TIMERGRP0_T1_CLK_EN` writer - Reserved"] +pub type REG_TIMERGRP0_T1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TIMERGRP0_WDT_SRC_SEL` reader - Reserved"] +pub type REG_TIMERGRP0_WDT_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_TIMERGRP0_WDT_SRC_SEL` writer - Reserved"] +pub type REG_TIMERGRP0_WDT_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_TIMERGRP0_WDT_CLK_EN` reader - Reserved"] +pub type REG_TIMERGRP0_WDT_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TIMERGRP0_WDT_CLK_EN` writer - Reserved"] +pub type REG_TIMERGRP0_WDT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TIMERGRP0_TGRT_CLK_EN` reader - Reserved"] +pub type REG_TIMERGRP0_TGRT_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TIMERGRP0_TGRT_CLK_EN` writer - Reserved"] +pub type REG_TIMERGRP0_TGRT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_mcpwm0_clk_src_sel(&self) -> REG_MCPWM0_CLK_SRC_SEL_R { + REG_MCPWM0_CLK_SRC_SEL_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_mcpwm0_clk_en(&self) -> REG_MCPWM0_CLK_EN_R { + REG_MCPWM0_CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:10 - Reserved"] + #[inline(always)] + pub fn reg_mcpwm0_clk_div_num(&self) -> REG_MCPWM0_CLK_DIV_NUM_R { + REG_MCPWM0_CLK_DIV_NUM_R::new(((self.bits >> 3) & 0xff) as u8) + } + #[doc = "Bits 11:12 - Reserved"] + #[inline(always)] + pub fn reg_mcpwm1_clk_src_sel(&self) -> REG_MCPWM1_CLK_SRC_SEL_R { + REG_MCPWM1_CLK_SRC_SEL_R::new(((self.bits >> 11) & 3) as u8) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn reg_mcpwm1_clk_en(&self) -> REG_MCPWM1_CLK_EN_R { + REG_MCPWM1_CLK_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:21 - Reserved"] + #[inline(always)] + pub fn reg_mcpwm1_clk_div_num(&self) -> REG_MCPWM1_CLK_DIV_NUM_R { + REG_MCPWM1_CLK_DIV_NUM_R::new(((self.bits >> 14) & 0xff) as u8) + } + #[doc = "Bits 22:23 - Reserved"] + #[inline(always)] + pub fn reg_timergrp0_t0_src_sel(&self) -> REG_TIMERGRP0_T0_SRC_SEL_R { + REG_TIMERGRP0_T0_SRC_SEL_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_timergrp0_t0_clk_en(&self) -> REG_TIMERGRP0_T0_CLK_EN_R { + REG_TIMERGRP0_T0_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:26 - Reserved"] + #[inline(always)] + pub fn reg_timergrp0_t1_src_sel(&self) -> REG_TIMERGRP0_T1_SRC_SEL_R { + REG_TIMERGRP0_T1_SRC_SEL_R::new(((self.bits >> 25) & 3) as u8) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_timergrp0_t1_clk_en(&self) -> REG_TIMERGRP0_T1_CLK_EN_R { + REG_TIMERGRP0_T1_CLK_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:29 - Reserved"] + #[inline(always)] + pub fn reg_timergrp0_wdt_src_sel(&self) -> REG_TIMERGRP0_WDT_SRC_SEL_R { + REG_TIMERGRP0_WDT_SRC_SEL_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + pub fn reg_timergrp0_wdt_clk_en(&self) -> REG_TIMERGRP0_WDT_CLK_EN_R { + REG_TIMERGRP0_WDT_CLK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn reg_timergrp0_tgrt_clk_en(&self) -> REG_TIMERGRP0_TGRT_CLK_EN_R { + REG_TIMERGRP0_TGRT_CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL20") + .field( + "reg_mcpwm0_clk_src_sel", + &format_args!("{}", self.reg_mcpwm0_clk_src_sel().bits()), + ) + .field( + "reg_mcpwm0_clk_en", + &format_args!("{}", self.reg_mcpwm0_clk_en().bit()), + ) + .field( + "reg_mcpwm0_clk_div_num", + &format_args!("{}", self.reg_mcpwm0_clk_div_num().bits()), + ) + .field( + "reg_mcpwm1_clk_src_sel", + &format_args!("{}", self.reg_mcpwm1_clk_src_sel().bits()), + ) + .field( + "reg_mcpwm1_clk_en", + &format_args!("{}", self.reg_mcpwm1_clk_en().bit()), + ) + .field( + "reg_mcpwm1_clk_div_num", + &format_args!("{}", self.reg_mcpwm1_clk_div_num().bits()), + ) + .field( + "reg_timergrp0_t0_src_sel", + &format_args!("{}", self.reg_timergrp0_t0_src_sel().bits()), + ) + .field( + "reg_timergrp0_t0_clk_en", + &format_args!("{}", self.reg_timergrp0_t0_clk_en().bit()), + ) + .field( + "reg_timergrp0_t1_src_sel", + &format_args!("{}", self.reg_timergrp0_t1_src_sel().bits()), + ) + .field( + "reg_timergrp0_t1_clk_en", + &format_args!("{}", self.reg_timergrp0_t1_clk_en().bit()), + ) + .field( + "reg_timergrp0_wdt_src_sel", + &format_args!("{}", self.reg_timergrp0_wdt_src_sel().bits()), + ) + .field( + "reg_timergrp0_wdt_clk_en", + &format_args!("{}", self.reg_timergrp0_wdt_clk_en().bit()), + ) + .field( + "reg_timergrp0_tgrt_clk_en", + &format_args!("{}", self.reg_timergrp0_tgrt_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mcpwm0_clk_src_sel(&mut self) -> REG_MCPWM0_CLK_SRC_SEL_W { + REG_MCPWM0_CLK_SRC_SEL_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mcpwm0_clk_en(&mut self) -> REG_MCPWM0_CLK_EN_W { + REG_MCPWM0_CLK_EN_W::new(self, 2) + } + #[doc = "Bits 3:10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mcpwm0_clk_div_num(&mut self) -> REG_MCPWM0_CLK_DIV_NUM_W { + REG_MCPWM0_CLK_DIV_NUM_W::new(self, 3) + } + #[doc = "Bits 11:12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mcpwm1_clk_src_sel(&mut self) -> REG_MCPWM1_CLK_SRC_SEL_W { + REG_MCPWM1_CLK_SRC_SEL_W::new(self, 11) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mcpwm1_clk_en(&mut self) -> REG_MCPWM1_CLK_EN_W { + REG_MCPWM1_CLK_EN_W::new(self, 13) + } + #[doc = "Bits 14:21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mcpwm1_clk_div_num(&mut self) -> REG_MCPWM1_CLK_DIV_NUM_W { + REG_MCPWM1_CLK_DIV_NUM_W::new(self, 14) + } + #[doc = "Bits 22:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp0_t0_src_sel(&mut self) -> REG_TIMERGRP0_T0_SRC_SEL_W { + REG_TIMERGRP0_T0_SRC_SEL_W::new(self, 22) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp0_t0_clk_en(&mut self) -> REG_TIMERGRP0_T0_CLK_EN_W { + REG_TIMERGRP0_T0_CLK_EN_W::new(self, 24) + } + #[doc = "Bits 25:26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp0_t1_src_sel(&mut self) -> REG_TIMERGRP0_T1_SRC_SEL_W { + REG_TIMERGRP0_T1_SRC_SEL_W::new(self, 25) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp0_t1_clk_en(&mut self) -> REG_TIMERGRP0_T1_CLK_EN_W { + REG_TIMERGRP0_T1_CLK_EN_W::new(self, 27) + } + #[doc = "Bits 28:29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp0_wdt_src_sel( + &mut self, + ) -> REG_TIMERGRP0_WDT_SRC_SEL_W { + REG_TIMERGRP0_WDT_SRC_SEL_W::new(self, 28) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp0_wdt_clk_en(&mut self) -> REG_TIMERGRP0_WDT_CLK_EN_W { + REG_TIMERGRP0_WDT_CLK_EN_W::new(self, 30) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp0_tgrt_clk_en( + &mut self, + ) -> REG_TIMERGRP0_TGRT_CLK_EN_W { + REG_TIMERGRP0_TGRT_CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl20::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl20::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL20_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL20_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl20::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL20_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl20::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL20_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL20 to value 0xc900_0000"] +impl crate::Resettable for PERI_CLK_CTRL20_SPEC { + const RESET_VALUE: Self::Ux = 0xc900_0000; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl21.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl21.rs new file mode 100644 index 0000000000..d526606177 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl21.rs @@ -0,0 +1,243 @@ +#[doc = "Register `PERI_CLK_CTRL21` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL21` writer"] +pub type W = crate::W; +#[doc = "Field `REG_TIMERGRP0_TGRT_CLK_SRC_SEL` reader - Reserved"] +pub type REG_TIMERGRP0_TGRT_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_TIMERGRP0_TGRT_CLK_SRC_SEL` writer - Reserved"] +pub type REG_TIMERGRP0_TGRT_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `REG_TIMERGRP0_TGRT_CLK_DIV_NUM` reader - Reserved"] +pub type REG_TIMERGRP0_TGRT_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_TIMERGRP0_TGRT_CLK_DIV_NUM` writer - Reserved"] +pub type REG_TIMERGRP0_TGRT_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `REG_TIMERGRP1_T0_SRC_SEL` reader - Reserved"] +pub type REG_TIMERGRP1_T0_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_TIMERGRP1_T0_SRC_SEL` writer - Reserved"] +pub type REG_TIMERGRP1_T0_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_TIMERGRP1_T0_CLK_EN` reader - Reserved"] +pub type REG_TIMERGRP1_T0_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TIMERGRP1_T0_CLK_EN` writer - Reserved"] +pub type REG_TIMERGRP1_T0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TIMERGRP1_T1_SRC_SEL` reader - Reserved"] +pub type REG_TIMERGRP1_T1_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_TIMERGRP1_T1_SRC_SEL` writer - Reserved"] +pub type REG_TIMERGRP1_T1_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_TIMERGRP1_T1_CLK_EN` reader - Reserved"] +pub type REG_TIMERGRP1_T1_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TIMERGRP1_T1_CLK_EN` writer - Reserved"] +pub type REG_TIMERGRP1_T1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TIMERGRP1_WDT_SRC_SEL` reader - Reserved"] +pub type REG_TIMERGRP1_WDT_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_TIMERGRP1_WDT_SRC_SEL` writer - Reserved"] +pub type REG_TIMERGRP1_WDT_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_TIMERGRP1_WDT_CLK_EN` reader - Reserved"] +pub type REG_TIMERGRP1_WDT_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TIMERGRP1_WDT_CLK_EN` writer - Reserved"] +pub type REG_TIMERGRP1_WDT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SYSTIMER_CLK_SRC_SEL` reader - Reserved"] +pub type REG_SYSTIMER_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_SYSTIMER_CLK_SRC_SEL` writer - Reserved"] +pub type REG_SYSTIMER_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SYSTIMER_CLK_EN` reader - Reserved"] +pub type REG_SYSTIMER_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_SYSTIMER_CLK_EN` writer - Reserved"] +pub type REG_SYSTIMER_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Reserved"] + #[inline(always)] + pub fn reg_timergrp0_tgrt_clk_src_sel(&self) -> REG_TIMERGRP0_TGRT_CLK_SRC_SEL_R { + REG_TIMERGRP0_TGRT_CLK_SRC_SEL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:19 - Reserved"] + #[inline(always)] + pub fn reg_timergrp0_tgrt_clk_div_num(&self) -> REG_TIMERGRP0_TGRT_CLK_DIV_NUM_R { + REG_TIMERGRP0_TGRT_CLK_DIV_NUM_R::new(((self.bits >> 4) & 0xffff) as u16) + } + #[doc = "Bits 20:21 - Reserved"] + #[inline(always)] + pub fn reg_timergrp1_t0_src_sel(&self) -> REG_TIMERGRP1_T0_SRC_SEL_R { + REG_TIMERGRP1_T0_SRC_SEL_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn reg_timergrp1_t0_clk_en(&self) -> REG_TIMERGRP1_T0_CLK_EN_R { + REG_TIMERGRP1_T0_CLK_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 23:24 - Reserved"] + #[inline(always)] + pub fn reg_timergrp1_t1_src_sel(&self) -> REG_TIMERGRP1_T1_SRC_SEL_R { + REG_TIMERGRP1_T1_SRC_SEL_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + pub fn reg_timergrp1_t1_clk_en(&self) -> REG_TIMERGRP1_T1_CLK_EN_R { + REG_TIMERGRP1_T1_CLK_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 26:27 - Reserved"] + #[inline(always)] + pub fn reg_timergrp1_wdt_src_sel(&self) -> REG_TIMERGRP1_WDT_SRC_SEL_R { + REG_TIMERGRP1_WDT_SRC_SEL_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_timergrp1_wdt_clk_en(&self) -> REG_TIMERGRP1_WDT_CLK_EN_R { + REG_TIMERGRP1_WDT_CLK_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_systimer_clk_src_sel(&self) -> REG_SYSTIMER_CLK_SRC_SEL_R { + REG_SYSTIMER_CLK_SRC_SEL_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + pub fn reg_systimer_clk_en(&self) -> REG_SYSTIMER_CLK_EN_R { + REG_SYSTIMER_CLK_EN_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL21") + .field( + "reg_timergrp0_tgrt_clk_src_sel", + &format_args!("{}", self.reg_timergrp0_tgrt_clk_src_sel().bits()), + ) + .field( + "reg_timergrp0_tgrt_clk_div_num", + &format_args!("{}", self.reg_timergrp0_tgrt_clk_div_num().bits()), + ) + .field( + "reg_timergrp1_t0_src_sel", + &format_args!("{}", self.reg_timergrp1_t0_src_sel().bits()), + ) + .field( + "reg_timergrp1_t0_clk_en", + &format_args!("{}", self.reg_timergrp1_t0_clk_en().bit()), + ) + .field( + "reg_timergrp1_t1_src_sel", + &format_args!("{}", self.reg_timergrp1_t1_src_sel().bits()), + ) + .field( + "reg_timergrp1_t1_clk_en", + &format_args!("{}", self.reg_timergrp1_t1_clk_en().bit()), + ) + .field( + "reg_timergrp1_wdt_src_sel", + &format_args!("{}", self.reg_timergrp1_wdt_src_sel().bits()), + ) + .field( + "reg_timergrp1_wdt_clk_en", + &format_args!("{}", self.reg_timergrp1_wdt_clk_en().bit()), + ) + .field( + "reg_systimer_clk_src_sel", + &format_args!("{}", self.reg_systimer_clk_src_sel().bit()), + ) + .field( + "reg_systimer_clk_en", + &format_args!("{}", self.reg_systimer_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp0_tgrt_clk_src_sel( + &mut self, + ) -> REG_TIMERGRP0_TGRT_CLK_SRC_SEL_W { + REG_TIMERGRP0_TGRT_CLK_SRC_SEL_W::new(self, 0) + } + #[doc = "Bits 4:19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp0_tgrt_clk_div_num( + &mut self, + ) -> REG_TIMERGRP0_TGRT_CLK_DIV_NUM_W { + REG_TIMERGRP0_TGRT_CLK_DIV_NUM_W::new(self, 4) + } + #[doc = "Bits 20:21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp1_t0_src_sel(&mut self) -> REG_TIMERGRP1_T0_SRC_SEL_W { + REG_TIMERGRP1_T0_SRC_SEL_W::new(self, 20) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp1_t0_clk_en(&mut self) -> REG_TIMERGRP1_T0_CLK_EN_W { + REG_TIMERGRP1_T0_CLK_EN_W::new(self, 22) + } + #[doc = "Bits 23:24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp1_t1_src_sel(&mut self) -> REG_TIMERGRP1_T1_SRC_SEL_W { + REG_TIMERGRP1_T1_SRC_SEL_W::new(self, 23) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp1_t1_clk_en(&mut self) -> REG_TIMERGRP1_T1_CLK_EN_W { + REG_TIMERGRP1_T1_CLK_EN_W::new(self, 25) + } + #[doc = "Bits 26:27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp1_wdt_src_sel( + &mut self, + ) -> REG_TIMERGRP1_WDT_SRC_SEL_W { + REG_TIMERGRP1_WDT_SRC_SEL_W::new(self, 26) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp1_wdt_clk_en(&mut self) -> REG_TIMERGRP1_WDT_CLK_EN_W { + REG_TIMERGRP1_WDT_CLK_EN_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_systimer_clk_src_sel(&mut self) -> REG_SYSTIMER_CLK_SRC_SEL_W { + REG_SYSTIMER_CLK_SRC_SEL_W::new(self, 29) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_systimer_clk_en(&mut self) -> REG_SYSTIMER_CLK_EN_W { + REG_SYSTIMER_CLK_EN_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl21::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl21::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL21_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL21_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl21::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL21_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl21::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL21_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL21 to value 0x5240_0000"] +impl crate::Resettable for PERI_CLK_CTRL21_SPEC { + const RESET_VALUE: Self::Ux = 0x5240_0000; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl22.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl22.rs new file mode 100644 index 0000000000..d7c6d6f574 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl22.rs @@ -0,0 +1,203 @@ +#[doc = "Register `PERI_CLK_CTRL22` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL22` writer"] +pub type W = crate::W; +#[doc = "Field `REG_LEDC_CLK_SRC_SEL` reader - Reserved"] +pub type REG_LEDC_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_LEDC_CLK_SRC_SEL` writer - Reserved"] +pub type REG_LEDC_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_LEDC_CLK_EN` reader - Reserved"] +pub type REG_LEDC_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_LEDC_CLK_EN` writer - Reserved"] +pub type REG_LEDC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RMT_CLK_SRC_SEL` reader - Reserved"] +pub type REG_RMT_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_RMT_CLK_SRC_SEL` writer - Reserved"] +pub type REG_RMT_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_RMT_CLK_EN` reader - Reserved"] +pub type REG_RMT_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_RMT_CLK_EN` writer - Reserved"] +pub type REG_RMT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RMT_CLK_DIV_NUM` reader - Reserved"] +pub type REG_RMT_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_RMT_CLK_DIV_NUM` writer - Reserved"] +pub type REG_RMT_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_RMT_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_RMT_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_RMT_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_RMT_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_RMT_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_RMT_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_RMT_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_RMT_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_ADC_CLK_SRC_SEL` reader - Reserved"] +pub type REG_ADC_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_ADC_CLK_SRC_SEL` writer - Reserved"] +pub type REG_ADC_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_ledc_clk_src_sel(&self) -> REG_LEDC_CLK_SRC_SEL_R { + REG_LEDC_CLK_SRC_SEL_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_ledc_clk_en(&self) -> REG_LEDC_CLK_EN_R { + REG_LEDC_CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - Reserved"] + #[inline(always)] + pub fn reg_rmt_clk_src_sel(&self) -> REG_RMT_CLK_SRC_SEL_R { + REG_RMT_CLK_SRC_SEL_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_rmt_clk_en(&self) -> REG_RMT_CLK_EN_R { + REG_RMT_CLK_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:13 - Reserved"] + #[inline(always)] + pub fn reg_rmt_clk_div_num(&self) -> REG_RMT_CLK_DIV_NUM_R { + REG_RMT_CLK_DIV_NUM_R::new(((self.bits >> 6) & 0xff) as u8) + } + #[doc = "Bits 14:21 - Reserved"] + #[inline(always)] + pub fn reg_rmt_clk_div_numerator(&self) -> REG_RMT_CLK_DIV_NUMERATOR_R { + REG_RMT_CLK_DIV_NUMERATOR_R::new(((self.bits >> 14) & 0xff) as u8) + } + #[doc = "Bits 22:29 - Reserved"] + #[inline(always)] + pub fn reg_rmt_clk_div_denominator(&self) -> REG_RMT_CLK_DIV_DENOMINATOR_R { + REG_RMT_CLK_DIV_DENOMINATOR_R::new(((self.bits >> 22) & 0xff) as u8) + } + #[doc = "Bits 30:31 - Reserved"] + #[inline(always)] + pub fn reg_adc_clk_src_sel(&self) -> REG_ADC_CLK_SRC_SEL_R { + REG_ADC_CLK_SRC_SEL_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL22") + .field( + "reg_ledc_clk_src_sel", + &format_args!("{}", self.reg_ledc_clk_src_sel().bits()), + ) + .field( + "reg_ledc_clk_en", + &format_args!("{}", self.reg_ledc_clk_en().bit()), + ) + .field( + "reg_rmt_clk_src_sel", + &format_args!("{}", self.reg_rmt_clk_src_sel().bits()), + ) + .field( + "reg_rmt_clk_en", + &format_args!("{}", self.reg_rmt_clk_en().bit()), + ) + .field( + "reg_rmt_clk_div_num", + &format_args!("{}", self.reg_rmt_clk_div_num().bits()), + ) + .field( + "reg_rmt_clk_div_numerator", + &format_args!("{}", self.reg_rmt_clk_div_numerator().bits()), + ) + .field( + "reg_rmt_clk_div_denominator", + &format_args!("{}", self.reg_rmt_clk_div_denominator().bits()), + ) + .field( + "reg_adc_clk_src_sel", + &format_args!("{}", self.reg_adc_clk_src_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ledc_clk_src_sel(&mut self) -> REG_LEDC_CLK_SRC_SEL_W { + REG_LEDC_CLK_SRC_SEL_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ledc_clk_en(&mut self) -> REG_LEDC_CLK_EN_W { + REG_LEDC_CLK_EN_W::new(self, 2) + } + #[doc = "Bits 3:4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rmt_clk_src_sel(&mut self) -> REG_RMT_CLK_SRC_SEL_W { + REG_RMT_CLK_SRC_SEL_W::new(self, 3) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rmt_clk_en(&mut self) -> REG_RMT_CLK_EN_W { + REG_RMT_CLK_EN_W::new(self, 5) + } + #[doc = "Bits 6:13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rmt_clk_div_num(&mut self) -> REG_RMT_CLK_DIV_NUM_W { + REG_RMT_CLK_DIV_NUM_W::new(self, 6) + } + #[doc = "Bits 14:21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rmt_clk_div_numerator( + &mut self, + ) -> REG_RMT_CLK_DIV_NUMERATOR_W { + REG_RMT_CLK_DIV_NUMERATOR_W::new(self, 14) + } + #[doc = "Bits 22:29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rmt_clk_div_denominator( + &mut self, + ) -> REG_RMT_CLK_DIV_DENOMINATOR_W { + REG_RMT_CLK_DIV_DENOMINATOR_W::new(self, 22) + } + #[doc = "Bits 30:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_adc_clk_src_sel(&mut self) -> REG_ADC_CLK_SRC_SEL_W { + REG_ADC_CLK_SRC_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl22::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl22::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL22_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL22_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl22::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL22_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl22::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL22_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL22 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL22_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl23.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl23.rs new file mode 100644 index 0000000000..9bf138c0f2 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl23.rs @@ -0,0 +1,127 @@ +#[doc = "Register `PERI_CLK_CTRL23` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL23` writer"] +pub type W = crate::W; +#[doc = "Field `REG_ADC_CLK_EN` reader - Reserved"] +pub type REG_ADC_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_ADC_CLK_EN` writer - Reserved"] +pub type REG_ADC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_ADC_CLK_DIV_NUM` reader - Reserved"] +pub type REG_ADC_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_ADC_CLK_DIV_NUM` writer - Reserved"] +pub type REG_ADC_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_ADC_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_ADC_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_ADC_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_ADC_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_ADC_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_ADC_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_ADC_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_ADC_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_adc_clk_en(&self) -> REG_ADC_CLK_EN_R { + REG_ADC_CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:8 - Reserved"] + #[inline(always)] + pub fn reg_adc_clk_div_num(&self) -> REG_ADC_CLK_DIV_NUM_R { + REG_ADC_CLK_DIV_NUM_R::new(((self.bits >> 1) & 0xff) as u8) + } + #[doc = "Bits 9:16 - Reserved"] + #[inline(always)] + pub fn reg_adc_clk_div_numerator(&self) -> REG_ADC_CLK_DIV_NUMERATOR_R { + REG_ADC_CLK_DIV_NUMERATOR_R::new(((self.bits >> 9) & 0xff) as u8) + } + #[doc = "Bits 17:24 - Reserved"] + #[inline(always)] + pub fn reg_adc_clk_div_denominator(&self) -> REG_ADC_CLK_DIV_DENOMINATOR_R { + REG_ADC_CLK_DIV_DENOMINATOR_R::new(((self.bits >> 17) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL23") + .field( + "reg_adc_clk_en", + &format_args!("{}", self.reg_adc_clk_en().bit()), + ) + .field( + "reg_adc_clk_div_num", + &format_args!("{}", self.reg_adc_clk_div_num().bits()), + ) + .field( + "reg_adc_clk_div_numerator", + &format_args!("{}", self.reg_adc_clk_div_numerator().bits()), + ) + .field( + "reg_adc_clk_div_denominator", + &format_args!("{}", self.reg_adc_clk_div_denominator().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_adc_clk_en(&mut self) -> REG_ADC_CLK_EN_W { + REG_ADC_CLK_EN_W::new(self, 0) + } + #[doc = "Bits 1:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_adc_clk_div_num(&mut self) -> REG_ADC_CLK_DIV_NUM_W { + REG_ADC_CLK_DIV_NUM_W::new(self, 1) + } + #[doc = "Bits 9:16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_adc_clk_div_numerator( + &mut self, + ) -> REG_ADC_CLK_DIV_NUMERATOR_W { + REG_ADC_CLK_DIV_NUMERATOR_W::new(self, 9) + } + #[doc = "Bits 17:24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_adc_clk_div_denominator( + &mut self, + ) -> REG_ADC_CLK_DIV_DENOMINATOR_W { + REG_ADC_CLK_DIV_DENOMINATOR_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl23::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl23::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL23_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL23_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl23::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL23_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl23::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL23_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL23 to value 0x08"] +impl crate::Resettable for PERI_CLK_CTRL23_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl24.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl24.rs new file mode 100644 index 0000000000..5be836b8a4 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl24.rs @@ -0,0 +1,123 @@ +#[doc = "Register `PERI_CLK_CTRL24` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL24` writer"] +pub type W = crate::W; +#[doc = "Field `REG_ADC_SAR1_CLK_DIV_NUM` reader - Reserved"] +pub type REG_ADC_SAR1_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_ADC_SAR1_CLK_DIV_NUM` writer - Reserved"] +pub type REG_ADC_SAR1_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_ADC_SAR2_CLK_DIV_NUM` reader - Reserved"] +pub type REG_ADC_SAR2_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_ADC_SAR2_CLK_DIV_NUM` writer - Reserved"] +pub type REG_ADC_SAR2_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_PVT_CLK_DIV_NUM` reader - Reserved"] +pub type REG_PVT_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_PVT_CLK_DIV_NUM` writer - Reserved"] +pub type REG_PVT_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_PVT_CLK_EN` reader - Reserved"] +pub type REG_PVT_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PVT_CLK_EN` writer - Reserved"] +pub type REG_PVT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_adc_sar1_clk_div_num(&self) -> REG_ADC_SAR1_CLK_DIV_NUM_R { + REG_ADC_SAR1_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_adc_sar2_clk_div_num(&self) -> REG_ADC_SAR2_CLK_DIV_NUM_R { + REG_ADC_SAR2_CLK_DIV_NUM_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_pvt_clk_div_num(&self) -> REG_PVT_CLK_DIV_NUM_R { + REG_PVT_CLK_DIV_NUM_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_pvt_clk_en(&self) -> REG_PVT_CLK_EN_R { + REG_PVT_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL24") + .field( + "reg_adc_sar1_clk_div_num", + &format_args!("{}", self.reg_adc_sar1_clk_div_num().bits()), + ) + .field( + "reg_adc_sar2_clk_div_num", + &format_args!("{}", self.reg_adc_sar2_clk_div_num().bits()), + ) + .field( + "reg_pvt_clk_div_num", + &format_args!("{}", self.reg_pvt_clk_div_num().bits()), + ) + .field( + "reg_pvt_clk_en", + &format_args!("{}", self.reg_pvt_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_adc_sar1_clk_div_num(&mut self) -> REG_ADC_SAR1_CLK_DIV_NUM_W { + REG_ADC_SAR1_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_adc_sar2_clk_div_num(&mut self) -> REG_ADC_SAR2_CLK_DIV_NUM_W { + REG_ADC_SAR2_CLK_DIV_NUM_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pvt_clk_div_num(&mut self) -> REG_PVT_CLK_DIV_NUM_W { + REG_PVT_CLK_DIV_NUM_W::new(self, 16) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pvt_clk_en(&mut self) -> REG_PVT_CLK_EN_W { + REG_PVT_CLK_EN_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl24::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl24::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL24_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL24_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl24::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL24_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl24::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL24_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL24 to value 0x0404"] +impl crate::Resettable for PERI_CLK_CTRL24_SPEC { + const RESET_VALUE: Self::Ux = 0x0404; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl25.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl25.rs new file mode 100644 index 0000000000..e600fd6ac8 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl25.rs @@ -0,0 +1,380 @@ +#[doc = "Register `PERI_CLK_CTRL25` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL25` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PVT_PERI_GROUP_CLK_DIV_NUM` reader - Reserved"] +pub type REG_PVT_PERI_GROUP_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_PVT_PERI_GROUP_CLK_DIV_NUM` writer - Reserved"] +pub type REG_PVT_PERI_GROUP_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_PVT_PERI_GROUP1_CLK_EN` reader - Reserved"] +pub type REG_PVT_PERI_GROUP1_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PVT_PERI_GROUP1_CLK_EN` writer - Reserved"] +pub type REG_PVT_PERI_GROUP1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PVT_PERI_GROUP2_CLK_EN` reader - Reserved"] +pub type REG_PVT_PERI_GROUP2_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PVT_PERI_GROUP2_CLK_EN` writer - Reserved"] +pub type REG_PVT_PERI_GROUP2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PVT_PERI_GROUP3_CLK_EN` reader - Reserved"] +pub type REG_PVT_PERI_GROUP3_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PVT_PERI_GROUP3_CLK_EN` writer - Reserved"] +pub type REG_PVT_PERI_GROUP3_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PVT_PERI_GROUP4_CLK_EN` reader - Reserved"] +pub type REG_PVT_PERI_GROUP4_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PVT_PERI_GROUP4_CLK_EN` writer - Reserved"] +pub type REG_PVT_PERI_GROUP4_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CRYPTO_CLK_SRC_SEL` reader - Reserved"] +pub type REG_CRYPTO_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_CRYPTO_CLK_SRC_SEL` writer - Reserved"] +pub type REG_CRYPTO_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_CRYPTO_AES_CLK_EN` reader - Reserved"] +pub type REG_CRYPTO_AES_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CRYPTO_AES_CLK_EN` writer - Reserved"] +pub type REG_CRYPTO_AES_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CRYPTO_DS_CLK_EN` reader - Reserved"] +pub type REG_CRYPTO_DS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CRYPTO_DS_CLK_EN` writer - Reserved"] +pub type REG_CRYPTO_DS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CRYPTO_ECC_CLK_EN` reader - Reserved"] +pub type REG_CRYPTO_ECC_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CRYPTO_ECC_CLK_EN` writer - Reserved"] +pub type REG_CRYPTO_ECC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CRYPTO_HMAC_CLK_EN` reader - Reserved"] +pub type REG_CRYPTO_HMAC_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CRYPTO_HMAC_CLK_EN` writer - Reserved"] +pub type REG_CRYPTO_HMAC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CRYPTO_RSA_CLK_EN` reader - Reserved"] +pub type REG_CRYPTO_RSA_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CRYPTO_RSA_CLK_EN` writer - Reserved"] +pub type REG_CRYPTO_RSA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CRYPTO_SEC_CLK_EN` reader - Reserved"] +pub type REG_CRYPTO_SEC_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CRYPTO_SEC_CLK_EN` writer - Reserved"] +pub type REG_CRYPTO_SEC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CRYPTO_SHA_CLK_EN` reader - Reserved"] +pub type REG_CRYPTO_SHA_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CRYPTO_SHA_CLK_EN` writer - Reserved"] +pub type REG_CRYPTO_SHA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CRYPTO_ECDSA_CLK_EN` reader - Reserved"] +pub type REG_CRYPTO_ECDSA_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CRYPTO_ECDSA_CLK_EN` writer - Reserved"] +pub type REG_CRYPTO_ECDSA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CRYPTO_KM_CLK_EN` reader - Reserved"] +pub type REG_CRYPTO_KM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CRYPTO_KM_CLK_EN` writer - Reserved"] +pub type REG_CRYPTO_KM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_ISP_CLK_SRC_SEL` reader - Reserved"] +pub type REG_ISP_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `REG_ISP_CLK_SRC_SEL` writer - Reserved"] +pub type REG_ISP_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_ISP_CLK_EN` reader - Reserved"] +pub type REG_ISP_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_ISP_CLK_EN` writer - Reserved"] +pub type REG_ISP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_pvt_peri_group_clk_div_num(&self) -> REG_PVT_PERI_GROUP_CLK_DIV_NUM_R { + REG_PVT_PERI_GROUP_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_pvt_peri_group1_clk_en(&self) -> REG_PVT_PERI_GROUP1_CLK_EN_R { + REG_PVT_PERI_GROUP1_CLK_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_pvt_peri_group2_clk_en(&self) -> REG_PVT_PERI_GROUP2_CLK_EN_R { + REG_PVT_PERI_GROUP2_CLK_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_pvt_peri_group3_clk_en(&self) -> REG_PVT_PERI_GROUP3_CLK_EN_R { + REG_PVT_PERI_GROUP3_CLK_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn reg_pvt_peri_group4_clk_en(&self) -> REG_PVT_PERI_GROUP4_CLK_EN_R { + REG_PVT_PERI_GROUP4_CLK_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:13 - Reserved"] + #[inline(always)] + pub fn reg_crypto_clk_src_sel(&self) -> REG_CRYPTO_CLK_SRC_SEL_R { + REG_CRYPTO_CLK_SRC_SEL_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn reg_crypto_aes_clk_en(&self) -> REG_CRYPTO_AES_CLK_EN_R { + REG_CRYPTO_AES_CLK_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn reg_crypto_ds_clk_en(&self) -> REG_CRYPTO_DS_CLK_EN_R { + REG_CRYPTO_DS_CLK_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_crypto_ecc_clk_en(&self) -> REG_CRYPTO_ECC_CLK_EN_R { + REG_CRYPTO_ECC_CLK_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + pub fn reg_crypto_hmac_clk_en(&self) -> REG_CRYPTO_HMAC_CLK_EN_R { + REG_CRYPTO_HMAC_CLK_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_crypto_rsa_clk_en(&self) -> REG_CRYPTO_RSA_CLK_EN_R { + REG_CRYPTO_RSA_CLK_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_crypto_sec_clk_en(&self) -> REG_CRYPTO_SEC_CLK_EN_R { + REG_CRYPTO_SEC_CLK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_crypto_sha_clk_en(&self) -> REG_CRYPTO_SHA_CLK_EN_R { + REG_CRYPTO_SHA_CLK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + pub fn reg_crypto_ecdsa_clk_en(&self) -> REG_CRYPTO_ECDSA_CLK_EN_R { + REG_CRYPTO_ECDSA_CLK_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn reg_crypto_km_clk_en(&self) -> REG_CRYPTO_KM_CLK_EN_R { + REG_CRYPTO_KM_CLK_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 23:24 - Reserved"] + #[inline(always)] + pub fn reg_isp_clk_src_sel(&self) -> REG_ISP_CLK_SRC_SEL_R { + REG_ISP_CLK_SRC_SEL_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + pub fn reg_isp_clk_en(&self) -> REG_ISP_CLK_EN_R { + REG_ISP_CLK_EN_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL25") + .field( + "reg_pvt_peri_group_clk_div_num", + &format_args!("{}", self.reg_pvt_peri_group_clk_div_num().bits()), + ) + .field( + "reg_pvt_peri_group1_clk_en", + &format_args!("{}", self.reg_pvt_peri_group1_clk_en().bit()), + ) + .field( + "reg_pvt_peri_group2_clk_en", + &format_args!("{}", self.reg_pvt_peri_group2_clk_en().bit()), + ) + .field( + "reg_pvt_peri_group3_clk_en", + &format_args!("{}", self.reg_pvt_peri_group3_clk_en().bit()), + ) + .field( + "reg_pvt_peri_group4_clk_en", + &format_args!("{}", self.reg_pvt_peri_group4_clk_en().bit()), + ) + .field( + "reg_crypto_clk_src_sel", + &format_args!("{}", self.reg_crypto_clk_src_sel().bits()), + ) + .field( + "reg_crypto_aes_clk_en", + &format_args!("{}", self.reg_crypto_aes_clk_en().bit()), + ) + .field( + "reg_crypto_ds_clk_en", + &format_args!("{}", self.reg_crypto_ds_clk_en().bit()), + ) + .field( + "reg_crypto_ecc_clk_en", + &format_args!("{}", self.reg_crypto_ecc_clk_en().bit()), + ) + .field( + "reg_crypto_hmac_clk_en", + &format_args!("{}", self.reg_crypto_hmac_clk_en().bit()), + ) + .field( + "reg_crypto_rsa_clk_en", + &format_args!("{}", self.reg_crypto_rsa_clk_en().bit()), + ) + .field( + "reg_crypto_sec_clk_en", + &format_args!("{}", self.reg_crypto_sec_clk_en().bit()), + ) + .field( + "reg_crypto_sha_clk_en", + &format_args!("{}", self.reg_crypto_sha_clk_en().bit()), + ) + .field( + "reg_crypto_ecdsa_clk_en", + &format_args!("{}", self.reg_crypto_ecdsa_clk_en().bit()), + ) + .field( + "reg_crypto_km_clk_en", + &format_args!("{}", self.reg_crypto_km_clk_en().bit()), + ) + .field( + "reg_isp_clk_src_sel", + &format_args!("{}", self.reg_isp_clk_src_sel().bits()), + ) + .field( + "reg_isp_clk_en", + &format_args!("{}", self.reg_isp_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pvt_peri_group_clk_div_num( + &mut self, + ) -> REG_PVT_PERI_GROUP_CLK_DIV_NUM_W { + REG_PVT_PERI_GROUP_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pvt_peri_group1_clk_en( + &mut self, + ) -> REG_PVT_PERI_GROUP1_CLK_EN_W { + REG_PVT_PERI_GROUP1_CLK_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pvt_peri_group2_clk_en( + &mut self, + ) -> REG_PVT_PERI_GROUP2_CLK_EN_W { + REG_PVT_PERI_GROUP2_CLK_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pvt_peri_group3_clk_en( + &mut self, + ) -> REG_PVT_PERI_GROUP3_CLK_EN_W { + REG_PVT_PERI_GROUP3_CLK_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pvt_peri_group4_clk_en( + &mut self, + ) -> REG_PVT_PERI_GROUP4_CLK_EN_W { + REG_PVT_PERI_GROUP4_CLK_EN_W::new(self, 11) + } + #[doc = "Bits 12:13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_crypto_clk_src_sel(&mut self) -> REG_CRYPTO_CLK_SRC_SEL_W { + REG_CRYPTO_CLK_SRC_SEL_W::new(self, 12) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_crypto_aes_clk_en(&mut self) -> REG_CRYPTO_AES_CLK_EN_W { + REG_CRYPTO_AES_CLK_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_crypto_ds_clk_en(&mut self) -> REG_CRYPTO_DS_CLK_EN_W { + REG_CRYPTO_DS_CLK_EN_W::new(self, 15) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_crypto_ecc_clk_en(&mut self) -> REG_CRYPTO_ECC_CLK_EN_W { + REG_CRYPTO_ECC_CLK_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_crypto_hmac_clk_en(&mut self) -> REG_CRYPTO_HMAC_CLK_EN_W { + REG_CRYPTO_HMAC_CLK_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_crypto_rsa_clk_en(&mut self) -> REG_CRYPTO_RSA_CLK_EN_W { + REG_CRYPTO_RSA_CLK_EN_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_crypto_sec_clk_en(&mut self) -> REG_CRYPTO_SEC_CLK_EN_W { + REG_CRYPTO_SEC_CLK_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_crypto_sha_clk_en(&mut self) -> REG_CRYPTO_SHA_CLK_EN_W { + REG_CRYPTO_SHA_CLK_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_crypto_ecdsa_clk_en(&mut self) -> REG_CRYPTO_ECDSA_CLK_EN_W { + REG_CRYPTO_ECDSA_CLK_EN_W::new(self, 21) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_crypto_km_clk_en(&mut self) -> REG_CRYPTO_KM_CLK_EN_W { + REG_CRYPTO_KM_CLK_EN_W::new(self, 22) + } + #[doc = "Bits 23:24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_isp_clk_src_sel(&mut self) -> REG_ISP_CLK_SRC_SEL_W { + REG_ISP_CLK_SRC_SEL_W::new(self, 23) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_isp_clk_en(&mut self) -> REG_ISP_CLK_EN_W { + REG_ISP_CLK_EN_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl25::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl25::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL25_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL25_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl25::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL25_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl25::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL25_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL25 to value 0x007f_c000"] +impl crate::Resettable for PERI_CLK_CTRL25_SPEC { + const RESET_VALUE: Self::Ux = 0x007f_c000; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl26.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl26.rs new file mode 100644 index 0000000000..714fd9c5a3 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl26.rs @@ -0,0 +1,220 @@ +#[doc = "Register `PERI_CLK_CTRL26` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL26` writer"] +pub type W = crate::W; +#[doc = "Field `REG_ISP_CLK_DIV_NUM` reader - Reserved"] +pub type REG_ISP_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_ISP_CLK_DIV_NUM` writer - Reserved"] +pub type REG_ISP_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_IOMUX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_IOMUX_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_IOMUX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_IOMUX_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_IOMUX_CLK_EN` reader - Reserved"] +pub type REG_IOMUX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_IOMUX_CLK_EN` writer - Reserved"] +pub type REG_IOMUX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_IOMUX_CLK_DIV_NUM` reader - Reserved"] +pub type REG_IOMUX_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_IOMUX_CLK_DIV_NUM` writer - Reserved"] +pub type REG_IOMUX_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_H264_CLK_SRC_SEL` reader - Reserved"] +pub type REG_H264_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_H264_CLK_SRC_SEL` writer - Reserved"] +pub type REG_H264_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_H264_CLK_EN` reader - Reserved"] +pub type REG_H264_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_H264_CLK_EN` writer - Reserved"] +pub type REG_H264_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_H264_CLK_DIV_NUM` reader - Reserved"] +pub type REG_H264_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_H264_CLK_DIV_NUM` writer - Reserved"] +pub type REG_H264_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_PADBIST_RX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_PADBIST_RX_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_PADBIST_RX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_PADBIST_RX_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PADBIST_RX_CLK_EN` reader - Reserved"] +pub type REG_PADBIST_RX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PADBIST_RX_CLK_EN` writer - Reserved"] +pub type REG_PADBIST_RX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_isp_clk_div_num(&self) -> REG_ISP_CLK_DIV_NUM_R { + REG_ISP_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_iomux_clk_src_sel(&self) -> REG_IOMUX_CLK_SRC_SEL_R { + REG_IOMUX_CLK_SRC_SEL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_iomux_clk_en(&self) -> REG_IOMUX_CLK_EN_R { + REG_IOMUX_CLK_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:17 - Reserved"] + #[inline(always)] + pub fn reg_iomux_clk_div_num(&self) -> REG_IOMUX_CLK_DIV_NUM_R { + REG_IOMUX_CLK_DIV_NUM_R::new(((self.bits >> 10) & 0xff) as u8) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_h264_clk_src_sel(&self) -> REG_H264_CLK_SRC_SEL_R { + REG_H264_CLK_SRC_SEL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_h264_clk_en(&self) -> REG_H264_CLK_EN_R { + REG_H264_CLK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:27 - Reserved"] + #[inline(always)] + pub fn reg_h264_clk_div_num(&self) -> REG_H264_CLK_DIV_NUM_R { + REG_H264_CLK_DIV_NUM_R::new(((self.bits >> 20) & 0xff) as u8) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_padbist_rx_clk_src_sel(&self) -> REG_PADBIST_RX_CLK_SRC_SEL_R { + REG_PADBIST_RX_CLK_SRC_SEL_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_padbist_rx_clk_en(&self) -> REG_PADBIST_RX_CLK_EN_R { + REG_PADBIST_RX_CLK_EN_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL26") + .field( + "reg_isp_clk_div_num", + &format_args!("{}", self.reg_isp_clk_div_num().bits()), + ) + .field( + "reg_iomux_clk_src_sel", + &format_args!("{}", self.reg_iomux_clk_src_sel().bit()), + ) + .field( + "reg_iomux_clk_en", + &format_args!("{}", self.reg_iomux_clk_en().bit()), + ) + .field( + "reg_iomux_clk_div_num", + &format_args!("{}", self.reg_iomux_clk_div_num().bits()), + ) + .field( + "reg_h264_clk_src_sel", + &format_args!("{}", self.reg_h264_clk_src_sel().bit()), + ) + .field( + "reg_h264_clk_en", + &format_args!("{}", self.reg_h264_clk_en().bit()), + ) + .field( + "reg_h264_clk_div_num", + &format_args!("{}", self.reg_h264_clk_div_num().bits()), + ) + .field( + "reg_padbist_rx_clk_src_sel", + &format_args!("{}", self.reg_padbist_rx_clk_src_sel().bit()), + ) + .field( + "reg_padbist_rx_clk_en", + &format_args!("{}", self.reg_padbist_rx_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_isp_clk_div_num(&mut self) -> REG_ISP_CLK_DIV_NUM_W { + REG_ISP_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_iomux_clk_src_sel(&mut self) -> REG_IOMUX_CLK_SRC_SEL_W { + REG_IOMUX_CLK_SRC_SEL_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_iomux_clk_en(&mut self) -> REG_IOMUX_CLK_EN_W { + REG_IOMUX_CLK_EN_W::new(self, 9) + } + #[doc = "Bits 10:17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_iomux_clk_div_num(&mut self) -> REG_IOMUX_CLK_DIV_NUM_W { + REG_IOMUX_CLK_DIV_NUM_W::new(self, 10) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_h264_clk_src_sel(&mut self) -> REG_H264_CLK_SRC_SEL_W { + REG_H264_CLK_SRC_SEL_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_h264_clk_en(&mut self) -> REG_H264_CLK_EN_W { + REG_H264_CLK_EN_W::new(self, 19) + } + #[doc = "Bits 20:27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_h264_clk_div_num(&mut self) -> REG_H264_CLK_DIV_NUM_W { + REG_H264_CLK_DIV_NUM_W::new(self, 20) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_padbist_rx_clk_src_sel( + &mut self, + ) -> REG_PADBIST_RX_CLK_SRC_SEL_W { + REG_PADBIST_RX_CLK_SRC_SEL_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_padbist_rx_clk_en(&mut self) -> REG_PADBIST_RX_CLK_EN_W { + REG_PADBIST_RX_CLK_EN_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl26::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl26::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL26_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL26_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl26::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL26_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl26::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL26_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL26 to value 0x0200"] +impl crate::Resettable for PERI_CLK_CTRL26_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl27.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl27.rs new file mode 100644 index 0000000000..f807ac4fa2 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl27.rs @@ -0,0 +1,129 @@ +#[doc = "Register `PERI_CLK_CTRL27` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_CLK_CTRL27` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PADBIST_RX_CLK_DIV_NUM` reader - Reserved"] +pub type REG_PADBIST_RX_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_PADBIST_RX_CLK_DIV_NUM` writer - Reserved"] +pub type REG_PADBIST_RX_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_PADBIST_TX_CLK_SRC_SEL` reader - Reserved"] +pub type REG_PADBIST_TX_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `REG_PADBIST_TX_CLK_SRC_SEL` writer - Reserved"] +pub type REG_PADBIST_TX_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PADBIST_TX_CLK_EN` reader - Reserved"] +pub type REG_PADBIST_TX_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PADBIST_TX_CLK_EN` writer - Reserved"] +pub type REG_PADBIST_TX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PADBIST_TX_CLK_DIV_NUM` reader - Reserved"] +pub type REG_PADBIST_TX_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_PADBIST_TX_CLK_DIV_NUM` writer - Reserved"] +pub type REG_PADBIST_TX_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_padbist_rx_clk_div_num(&self) -> REG_PADBIST_RX_CLK_DIV_NUM_R { + REG_PADBIST_RX_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_padbist_tx_clk_src_sel(&self) -> REG_PADBIST_TX_CLK_SRC_SEL_R { + REG_PADBIST_TX_CLK_SRC_SEL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_padbist_tx_clk_en(&self) -> REG_PADBIST_TX_CLK_EN_R { + REG_PADBIST_TX_CLK_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:17 - Reserved"] + #[inline(always)] + pub fn reg_padbist_tx_clk_div_num(&self) -> REG_PADBIST_TX_CLK_DIV_NUM_R { + REG_PADBIST_TX_CLK_DIV_NUM_R::new(((self.bits >> 10) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PERI_CLK_CTRL27") + .field( + "reg_padbist_rx_clk_div_num", + &format_args!("{}", self.reg_padbist_rx_clk_div_num().bits()), + ) + .field( + "reg_padbist_tx_clk_src_sel", + &format_args!("{}", self.reg_padbist_tx_clk_src_sel().bit()), + ) + .field( + "reg_padbist_tx_clk_en", + &format_args!("{}", self.reg_padbist_tx_clk_en().bit()), + ) + .field( + "reg_padbist_tx_clk_div_num", + &format_args!("{}", self.reg_padbist_tx_clk_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_padbist_rx_clk_div_num( + &mut self, + ) -> REG_PADBIST_RX_CLK_DIV_NUM_W { + REG_PADBIST_RX_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_padbist_tx_clk_src_sel( + &mut self, + ) -> REG_PADBIST_TX_CLK_SRC_SEL_W { + REG_PADBIST_TX_CLK_SRC_SEL_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_padbist_tx_clk_en(&mut self) -> REG_PADBIST_TX_CLK_EN_W { + REG_PADBIST_TX_CLK_EN_W::new(self, 9) + } + #[doc = "Bits 10:17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_padbist_tx_clk_div_num( + &mut self, + ) -> REG_PADBIST_TX_CLK_DIV_NUM_W { + REG_PADBIST_TX_CLK_DIV_NUM_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl27::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl27::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_CLK_CTRL27_SPEC; +impl crate::RegisterSpec for PERI_CLK_CTRL27_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_clk_ctrl27::R`](R) reader structure"] +impl crate::Readable for PERI_CLK_CTRL27_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl27::W`](W) writer structure"] +impl crate::Writable for PERI_CLK_CTRL27_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERI_CLK_CTRL27 to value 0"] +impl crate::Resettable for PERI_CLK_CTRL27_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl0.rs new file mode 100644 index 0000000000..0c82e1683d --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl0.rs @@ -0,0 +1,123 @@ +#[doc = "Register `REF_CLK_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `REF_CLK_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_REF_50M_CLK_DIV_NUM` reader - Reserved"] +pub type REG_REF_50M_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_REF_50M_CLK_DIV_NUM` writer - Reserved"] +pub type REG_REF_50M_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_REF_25M_CLK_DIV_NUM` reader - Reserved"] +pub type REG_REF_25M_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_REF_25M_CLK_DIV_NUM` writer - Reserved"] +pub type REG_REF_25M_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_REF_240M_CLK_DIV_NUM` reader - Reserved"] +pub type REG_REF_240M_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_REF_240M_CLK_DIV_NUM` writer - Reserved"] +pub type REG_REF_240M_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_REF_160M_CLK_DIV_NUM` reader - Reserved"] +pub type REG_REF_160M_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_REF_160M_CLK_DIV_NUM` writer - Reserved"] +pub type REG_REF_160M_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_ref_50m_clk_div_num(&self) -> REG_REF_50M_CLK_DIV_NUM_R { + REG_REF_50M_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_ref_25m_clk_div_num(&self) -> REG_REF_25M_CLK_DIV_NUM_R { + REG_REF_25M_CLK_DIV_NUM_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_ref_240m_clk_div_num(&self) -> REG_REF_240M_CLK_DIV_NUM_R { + REG_REF_240M_CLK_DIV_NUM_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Reserved"] + #[inline(always)] + pub fn reg_ref_160m_clk_div_num(&self) -> REG_REF_160M_CLK_DIV_NUM_R { + REG_REF_160M_CLK_DIV_NUM_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REF_CLK_CTRL0") + .field( + "reg_ref_50m_clk_div_num", + &format_args!("{}", self.reg_ref_50m_clk_div_num().bits()), + ) + .field( + "reg_ref_25m_clk_div_num", + &format_args!("{}", self.reg_ref_25m_clk_div_num().bits()), + ) + .field( + "reg_ref_240m_clk_div_num", + &format_args!("{}", self.reg_ref_240m_clk_div_num().bits()), + ) + .field( + "reg_ref_160m_clk_div_num", + &format_args!("{}", self.reg_ref_160m_clk_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_50m_clk_div_num(&mut self) -> REG_REF_50M_CLK_DIV_NUM_W { + REG_REF_50M_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_25m_clk_div_num(&mut self) -> REG_REF_25M_CLK_DIV_NUM_W { + REG_REF_25M_CLK_DIV_NUM_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_240m_clk_div_num(&mut self) -> REG_REF_240M_CLK_DIV_NUM_W { + REG_REF_240M_CLK_DIV_NUM_W::new(self, 16) + } + #[doc = "Bits 24:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_160m_clk_div_num(&mut self) -> REG_REF_160M_CLK_DIV_NUM_W { + REG_REF_160M_CLK_DIV_NUM_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_clk_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_clk_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REF_CLK_CTRL0_SPEC; +impl crate::RegisterSpec for REF_CLK_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ref_clk_ctrl0::R`](R) reader structure"] +impl crate::Readable for REF_CLK_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ref_clk_ctrl0::W`](W) writer structure"] +impl crate::Writable for REF_CLK_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REF_CLK_CTRL0 to value 0x0201_1309"] +impl crate::Resettable for REF_CLK_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0x0201_1309; +} diff --git a/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl1.rs b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl1.rs new file mode 100644 index 0000000000..9e87981214 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl1.rs @@ -0,0 +1,256 @@ +#[doc = "Register `REF_CLK_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `REF_CLK_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `REG_REF_120M_CLK_DIV_NUM` reader - Reserved"] +pub type REG_REF_120M_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_REF_120M_CLK_DIV_NUM` writer - Reserved"] +pub type REG_REF_120M_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_REF_80M_CLK_DIV_NUM` reader - Reserved"] +pub type REG_REF_80M_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_REF_80M_CLK_DIV_NUM` writer - Reserved"] +pub type REG_REF_80M_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_REF_20M_CLK_DIV_NUM` reader - Reserved"] +pub type REG_REF_20M_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_REF_20M_CLK_DIV_NUM` writer - Reserved"] +pub type REG_REF_20M_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_TM_400M_CLK_EN` reader - Reserved"] +pub type REG_TM_400M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TM_400M_CLK_EN` writer - Reserved"] +pub type REG_TM_400M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TM_200M_CLK_EN` reader - Reserved"] +pub type REG_TM_200M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TM_200M_CLK_EN` writer - Reserved"] +pub type REG_TM_200M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TM_100M_CLK_EN` reader - Reserved"] +pub type REG_TM_100M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TM_100M_CLK_EN` writer - Reserved"] +pub type REG_TM_100M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_REF_50M_CLK_EN` reader - Reserved"] +pub type REG_REF_50M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_REF_50M_CLK_EN` writer - Reserved"] +pub type REG_REF_50M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_REF_25M_CLK_EN` reader - Reserved"] +pub type REG_REF_25M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_REF_25M_CLK_EN` writer - Reserved"] +pub type REG_REF_25M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TM_480M_CLK_EN` reader - Reserved"] +pub type REG_TM_480M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TM_480M_CLK_EN` writer - Reserved"] +pub type REG_TM_480M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_REF_240M_CLK_EN` reader - Reserved"] +pub type REG_REF_240M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_REF_240M_CLK_EN` writer - Reserved"] +pub type REG_REF_240M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TM_240M_CLK_EN` reader - Reserved"] +pub type REG_TM_240M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TM_240M_CLK_EN` writer - Reserved"] +pub type REG_TM_240M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_ref_120m_clk_div_num(&self) -> REG_REF_120M_CLK_DIV_NUM_R { + REG_REF_120M_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_ref_80m_clk_div_num(&self) -> REG_REF_80M_CLK_DIV_NUM_R { + REG_REF_80M_CLK_DIV_NUM_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_ref_20m_clk_div_num(&self) -> REG_REF_20M_CLK_DIV_NUM_R { + REG_REF_20M_CLK_DIV_NUM_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_tm_400m_clk_en(&self) -> REG_TM_400M_CLK_EN_R { + REG_TM_400M_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + pub fn reg_tm_200m_clk_en(&self) -> REG_TM_200M_CLK_EN_R { + REG_TM_200M_CLK_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_tm_100m_clk_en(&self) -> REG_TM_100M_CLK_EN_R { + REG_TM_100M_CLK_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_ref_50m_clk_en(&self) -> REG_REF_50M_CLK_EN_R { + REG_REF_50M_CLK_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_ref_25m_clk_en(&self) -> REG_REF_25M_CLK_EN_R { + REG_REF_25M_CLK_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_tm_480m_clk_en(&self) -> REG_TM_480M_CLK_EN_R { + REG_TM_480M_CLK_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + pub fn reg_ref_240m_clk_en(&self) -> REG_REF_240M_CLK_EN_R { + REG_REF_240M_CLK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn reg_tm_240m_clk_en(&self) -> REG_TM_240M_CLK_EN_R { + REG_TM_240M_CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REF_CLK_CTRL1") + .field( + "reg_ref_120m_clk_div_num", + &format_args!("{}", self.reg_ref_120m_clk_div_num().bits()), + ) + .field( + "reg_ref_80m_clk_div_num", + &format_args!("{}", self.reg_ref_80m_clk_div_num().bits()), + ) + .field( + "reg_ref_20m_clk_div_num", + &format_args!("{}", self.reg_ref_20m_clk_div_num().bits()), + ) + .field( + "reg_tm_400m_clk_en", + &format_args!("{}", self.reg_tm_400m_clk_en().bit()), + ) + .field( + "reg_tm_200m_clk_en", + &format_args!("{}", self.reg_tm_200m_clk_en().bit()), + ) + .field( + "reg_tm_100m_clk_en", + &format_args!("{}", self.reg_tm_100m_clk_en().bit()), + ) + .field( + "reg_ref_50m_clk_en", + &format_args!("{}", self.reg_ref_50m_clk_en().bit()), + ) + .field( + "reg_ref_25m_clk_en", + &format_args!("{}", self.reg_ref_25m_clk_en().bit()), + ) + .field( + "reg_tm_480m_clk_en", + &format_args!("{}", self.reg_tm_480m_clk_en().bit()), + ) + .field( + "reg_ref_240m_clk_en", + &format_args!("{}", self.reg_ref_240m_clk_en().bit()), + ) + .field( + "reg_tm_240m_clk_en", + &format_args!("{}", self.reg_tm_240m_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_120m_clk_div_num(&mut self) -> REG_REF_120M_CLK_DIV_NUM_W { + REG_REF_120M_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_80m_clk_div_num(&mut self) -> REG_REF_80M_CLK_DIV_NUM_W { + REG_REF_80M_CLK_DIV_NUM_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_20m_clk_div_num(&mut self) -> REG_REF_20M_CLK_DIV_NUM_W { + REG_REF_20M_CLK_DIV_NUM_W::new(self, 16) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tm_400m_clk_en(&mut self) -> REG_TM_400M_CLK_EN_W { + REG_TM_400M_CLK_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tm_200m_clk_en(&mut self) -> REG_TM_200M_CLK_EN_W { + REG_TM_200M_CLK_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tm_100m_clk_en(&mut self) -> REG_TM_100M_CLK_EN_W { + REG_TM_100M_CLK_EN_W::new(self, 26) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_50m_clk_en(&mut self) -> REG_REF_50M_CLK_EN_W { + REG_REF_50M_CLK_EN_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_25m_clk_en(&mut self) -> REG_REF_25M_CLK_EN_W { + REG_REF_25M_CLK_EN_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tm_480m_clk_en(&mut self) -> REG_TM_480M_CLK_EN_W { + REG_TM_480M_CLK_EN_W::new(self, 29) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_240m_clk_en(&mut self) -> REG_REF_240M_CLK_EN_W { + REG_REF_240M_CLK_EN_W::new(self, 30) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tm_240m_clk_en(&mut self) -> REG_TM_240M_CLK_EN_W { + REG_TM_240M_CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_clk_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_clk_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REF_CLK_CTRL1_SPEC; +impl crate::RegisterSpec for REF_CLK_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ref_clk_ctrl1::R`](R) reader structure"] +impl crate::Readable for REF_CLK_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ref_clk_ctrl1::W`](W) writer structure"] +impl crate::Writable for REF_CLK_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REF_CLK_CTRL1 to value 0x5817_0503"] +impl crate::Resettable for REF_CLK_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0x5817_0503; +} diff --git a/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl2.rs b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl2.rs new file mode 100644 index 0000000000..8350f73319 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl2.rs @@ -0,0 +1,237 @@ +#[doc = "Register `REF_CLK_CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `REF_CLK_CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `REG_REF_160M_CLK_EN` reader - Reserved"] +pub type REG_REF_160M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_REF_160M_CLK_EN` writer - Reserved"] +pub type REG_REF_160M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TM_160M_CLK_EN` reader - Reserved"] +pub type REG_TM_160M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TM_160M_CLK_EN` writer - Reserved"] +pub type REG_TM_160M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_REF_120M_CLK_EN` reader - Reserved"] +pub type REG_REF_120M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_REF_120M_CLK_EN` writer - Reserved"] +pub type REG_REF_120M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TM_120M_CLK_EN` reader - Reserved"] +pub type REG_TM_120M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TM_120M_CLK_EN` writer - Reserved"] +pub type REG_TM_120M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_REF_80M_CLK_EN` reader - Reserved"] +pub type REG_REF_80M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_REF_80M_CLK_EN` writer - Reserved"] +pub type REG_REF_80M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TM_80M_CLK_EN` reader - Reserved"] +pub type REG_TM_80M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TM_80M_CLK_EN` writer - Reserved"] +pub type REG_TM_80M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TM_60M_CLK_EN` reader - Reserved"] +pub type REG_TM_60M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TM_60M_CLK_EN` writer - Reserved"] +pub type REG_TM_60M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TM_48M_CLK_EN` reader - Reserved"] +pub type REG_TM_48M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TM_48M_CLK_EN` writer - Reserved"] +pub type REG_TM_48M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_REF_20M_CLK_EN` reader - Reserved"] +pub type REG_REF_20M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_REF_20M_CLK_EN` writer - Reserved"] +pub type REG_REF_20M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TM_20M_CLK_EN` reader - Reserved"] +pub type REG_TM_20M_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TM_20M_CLK_EN` writer - Reserved"] +pub type REG_TM_20M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_ref_160m_clk_en(&self) -> REG_REF_160M_CLK_EN_R { + REG_REF_160M_CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_tm_160m_clk_en(&self) -> REG_TM_160M_CLK_EN_R { + REG_TM_160M_CLK_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_ref_120m_clk_en(&self) -> REG_REF_120M_CLK_EN_R { + REG_REF_120M_CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_tm_120m_clk_en(&self) -> REG_TM_120M_CLK_EN_R { + REG_TM_120M_CLK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_ref_80m_clk_en(&self) -> REG_REF_80M_CLK_EN_R { + REG_REF_80M_CLK_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_tm_80m_clk_en(&self) -> REG_TM_80M_CLK_EN_R { + REG_TM_80M_CLK_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn reg_tm_60m_clk_en(&self) -> REG_TM_60M_CLK_EN_R { + REG_TM_60M_CLK_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_tm_48m_clk_en(&self) -> REG_TM_48M_CLK_EN_R { + REG_TM_48M_CLK_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_ref_20m_clk_en(&self) -> REG_REF_20M_CLK_EN_R { + REG_REF_20M_CLK_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_tm_20m_clk_en(&self) -> REG_TM_20M_CLK_EN_R { + REG_TM_20M_CLK_EN_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REF_CLK_CTRL2") + .field( + "reg_ref_160m_clk_en", + &format_args!("{}", self.reg_ref_160m_clk_en().bit()), + ) + .field( + "reg_tm_160m_clk_en", + &format_args!("{}", self.reg_tm_160m_clk_en().bit()), + ) + .field( + "reg_ref_120m_clk_en", + &format_args!("{}", self.reg_ref_120m_clk_en().bit()), + ) + .field( + "reg_tm_120m_clk_en", + &format_args!("{}", self.reg_tm_120m_clk_en().bit()), + ) + .field( + "reg_ref_80m_clk_en", + &format_args!("{}", self.reg_ref_80m_clk_en().bit()), + ) + .field( + "reg_tm_80m_clk_en", + &format_args!("{}", self.reg_tm_80m_clk_en().bit()), + ) + .field( + "reg_tm_60m_clk_en", + &format_args!("{}", self.reg_tm_60m_clk_en().bit()), + ) + .field( + "reg_tm_48m_clk_en", + &format_args!("{}", self.reg_tm_48m_clk_en().bit()), + ) + .field( + "reg_ref_20m_clk_en", + &format_args!("{}", self.reg_ref_20m_clk_en().bit()), + ) + .field( + "reg_tm_20m_clk_en", + &format_args!("{}", self.reg_tm_20m_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_160m_clk_en(&mut self) -> REG_REF_160M_CLK_EN_W { + REG_REF_160M_CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tm_160m_clk_en(&mut self) -> REG_TM_160M_CLK_EN_W { + REG_TM_160M_CLK_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_120m_clk_en(&mut self) -> REG_REF_120M_CLK_EN_W { + REG_REF_120M_CLK_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tm_120m_clk_en(&mut self) -> REG_TM_120M_CLK_EN_W { + REG_TM_120M_CLK_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_80m_clk_en(&mut self) -> REG_REF_80M_CLK_EN_W { + REG_REF_80M_CLK_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tm_80m_clk_en(&mut self) -> REG_TM_80M_CLK_EN_W { + REG_TM_80M_CLK_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tm_60m_clk_en(&mut self) -> REG_TM_60M_CLK_EN_W { + REG_TM_60M_CLK_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tm_48m_clk_en(&mut self) -> REG_TM_48M_CLK_EN_W { + REG_TM_48M_CLK_EN_W::new(self, 7) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ref_20m_clk_en(&mut self) -> REG_REF_20M_CLK_EN_W { + REG_REF_20M_CLK_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tm_20m_clk_en(&mut self) -> REG_TM_20M_CLK_EN_W { + REG_TM_20M_CLK_EN_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_clk_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_clk_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REF_CLK_CTRL2_SPEC; +impl crate::RegisterSpec for REF_CLK_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ref_clk_ctrl2::R`](R) reader structure"] +impl crate::Readable for REF_CLK_CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ref_clk_ctrl2::W`](W) writer structure"] +impl crate::Writable for REF_CLK_CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REF_CLK_CTRL2 to value 0x0115"] +impl crate::Resettable for REF_CLK_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0x0115; +} diff --git a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl0.rs new file mode 100644 index 0000000000..383b756761 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl0.rs @@ -0,0 +1,135 @@ +#[doc = "Register `ROOT_CLK_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `ROOT_CLK_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_CPUICM_DELAY_NUM` reader - Reserved"] +pub type REG_CPUICM_DELAY_NUM_R = crate::FieldReader; +#[doc = "Field `REG_CPUICM_DELAY_NUM` writer - Reserved"] +pub type REG_CPUICM_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `REG_SOC_CLK_DIV_UPDATE` writer - Reserved"] +pub type REG_SOC_CLK_DIV_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CPU_CLK_DIV_NUM` reader - Reserved"] +pub type REG_CPU_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_CPU_CLK_DIV_NUM` writer - Reserved"] +pub type REG_CPU_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_CPU_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_CPU_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_CPU_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_CPU_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_CPU_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_CPU_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_CPU_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_CPU_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:3 - Reserved"] + #[inline(always)] + pub fn reg_cpuicm_delay_num(&self) -> REG_CPUICM_DELAY_NUM_R { + REG_CPUICM_DELAY_NUM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 5:12 - Reserved"] + #[inline(always)] + pub fn reg_cpu_clk_div_num(&self) -> REG_CPU_CLK_DIV_NUM_R { + REG_CPU_CLK_DIV_NUM_R::new(((self.bits >> 5) & 0xff) as u8) + } + #[doc = "Bits 13:20 - Reserved"] + #[inline(always)] + pub fn reg_cpu_clk_div_numerator(&self) -> REG_CPU_CLK_DIV_NUMERATOR_R { + REG_CPU_CLK_DIV_NUMERATOR_R::new(((self.bits >> 13) & 0xff) as u8) + } + #[doc = "Bits 21:28 - Reserved"] + #[inline(always)] + pub fn reg_cpu_clk_div_denominator(&self) -> REG_CPU_CLK_DIV_DENOMINATOR_R { + REG_CPU_CLK_DIV_DENOMINATOR_R::new(((self.bits >> 21) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ROOT_CLK_CTRL0") + .field( + "reg_cpuicm_delay_num", + &format_args!("{}", self.reg_cpuicm_delay_num().bits()), + ) + .field( + "reg_cpu_clk_div_num", + &format_args!("{}", self.reg_cpu_clk_div_num().bits()), + ) + .field( + "reg_cpu_clk_div_numerator", + &format_args!("{}", self.reg_cpu_clk_div_numerator().bits()), + ) + .field( + "reg_cpu_clk_div_denominator", + &format_args!("{}", self.reg_cpu_clk_div_denominator().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_cpuicm_delay_num(&mut self) -> REG_CPUICM_DELAY_NUM_W { + REG_CPUICM_DELAY_NUM_W::new(self, 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_soc_clk_div_update(&mut self) -> REG_SOC_CLK_DIV_UPDATE_W { + REG_SOC_CLK_DIV_UPDATE_W::new(self, 4) + } + #[doc = "Bits 5:12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_cpu_clk_div_num(&mut self) -> REG_CPU_CLK_DIV_NUM_W { + REG_CPU_CLK_DIV_NUM_W::new(self, 5) + } + #[doc = "Bits 13:20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_cpu_clk_div_numerator( + &mut self, + ) -> REG_CPU_CLK_DIV_NUMERATOR_W { + REG_CPU_CLK_DIV_NUMERATOR_W::new(self, 13) + } + #[doc = "Bits 21:28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_cpu_clk_div_denominator( + &mut self, + ) -> REG_CPU_CLK_DIV_DENOMINATOR_W { + REG_CPU_CLK_DIV_DENOMINATOR_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`root_clk_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`root_clk_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ROOT_CLK_CTRL0_SPEC; +impl crate::RegisterSpec for ROOT_CLK_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`root_clk_ctrl0::R`](R) reader structure"] +impl crate::Readable for ROOT_CLK_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`root_clk_ctrl0::W`](W) writer structure"] +impl crate::Writable for ROOT_CLK_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ROOT_CLK_CTRL0 to value 0"] +impl crate::Resettable for ROOT_CLK_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl1.rs b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl1.rs new file mode 100644 index 0000000000..997751f783 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl1.rs @@ -0,0 +1,127 @@ +#[doc = "Register `ROOT_CLK_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `ROOT_CLK_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `REG_MEM_CLK_DIV_NUM` reader - Reserved"] +pub type REG_MEM_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_MEM_CLK_DIV_NUM` writer - Reserved"] +pub type REG_MEM_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_MEM_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_MEM_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_MEM_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_MEM_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_MEM_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_MEM_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_MEM_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_MEM_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_SYS_CLK_DIV_NUM` reader - Reserved"] +pub type REG_SYS_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_SYS_CLK_DIV_NUM` writer - Reserved"] +pub type REG_SYS_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_mem_clk_div_num(&self) -> REG_MEM_CLK_DIV_NUM_R { + REG_MEM_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_mem_clk_div_numerator(&self) -> REG_MEM_CLK_DIV_NUMERATOR_R { + REG_MEM_CLK_DIV_NUMERATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_mem_clk_div_denominator(&self) -> REG_MEM_CLK_DIV_DENOMINATOR_R { + REG_MEM_CLK_DIV_DENOMINATOR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Reserved"] + #[inline(always)] + pub fn reg_sys_clk_div_num(&self) -> REG_SYS_CLK_DIV_NUM_R { + REG_SYS_CLK_DIV_NUM_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ROOT_CLK_CTRL1") + .field( + "reg_mem_clk_div_num", + &format_args!("{}", self.reg_mem_clk_div_num().bits()), + ) + .field( + "reg_mem_clk_div_numerator", + &format_args!("{}", self.reg_mem_clk_div_numerator().bits()), + ) + .field( + "reg_mem_clk_div_denominator", + &format_args!("{}", self.reg_mem_clk_div_denominator().bits()), + ) + .field( + "reg_sys_clk_div_num", + &format_args!("{}", self.reg_sys_clk_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mem_clk_div_num(&mut self) -> REG_MEM_CLK_DIV_NUM_W { + REG_MEM_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mem_clk_div_numerator( + &mut self, + ) -> REG_MEM_CLK_DIV_NUMERATOR_W { + REG_MEM_CLK_DIV_NUMERATOR_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mem_clk_div_denominator( + &mut self, + ) -> REG_MEM_CLK_DIV_DENOMINATOR_W { + REG_MEM_CLK_DIV_DENOMINATOR_W::new(self, 16) + } + #[doc = "Bits 24:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sys_clk_div_num(&mut self) -> REG_SYS_CLK_DIV_NUM_W { + REG_SYS_CLK_DIV_NUM_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`root_clk_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`root_clk_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ROOT_CLK_CTRL1_SPEC; +impl crate::RegisterSpec for ROOT_CLK_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`root_clk_ctrl1::R`](R) reader structure"] +impl crate::Readable for ROOT_CLK_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`root_clk_ctrl1::W`](W) writer structure"] +impl crate::Writable for ROOT_CLK_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ROOT_CLK_CTRL1 to value 0x01"] +impl crate::Resettable for ROOT_CLK_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl2.rs b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl2.rs new file mode 100644 index 0000000000..e6ef1f9cd9 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl2.rs @@ -0,0 +1,129 @@ +#[doc = "Register `ROOT_CLK_CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `ROOT_CLK_CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `REG_SYS_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_SYS_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_SYS_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_SYS_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_SYS_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_SYS_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_SYS_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_SYS_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_APB_CLK_DIV_NUM` reader - Reserved"] +pub type REG_APB_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `REG_APB_CLK_DIV_NUM` writer - Reserved"] +pub type REG_APB_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_APB_CLK_DIV_NUMERATOR` reader - Reserved"] +pub type REG_APB_CLK_DIV_NUMERATOR_R = crate::FieldReader; +#[doc = "Field `REG_APB_CLK_DIV_NUMERATOR` writer - Reserved"] +pub type REG_APB_CLK_DIV_NUMERATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_sys_clk_div_numerator(&self) -> REG_SYS_CLK_DIV_NUMERATOR_R { + REG_SYS_CLK_DIV_NUMERATOR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + pub fn reg_sys_clk_div_denominator(&self) -> REG_SYS_CLK_DIV_DENOMINATOR_R { + REG_SYS_CLK_DIV_DENOMINATOR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + pub fn reg_apb_clk_div_num(&self) -> REG_APB_CLK_DIV_NUM_R { + REG_APB_CLK_DIV_NUM_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Reserved"] + #[inline(always)] + pub fn reg_apb_clk_div_numerator(&self) -> REG_APB_CLK_DIV_NUMERATOR_R { + REG_APB_CLK_DIV_NUMERATOR_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ROOT_CLK_CTRL2") + .field( + "reg_sys_clk_div_numerator", + &format_args!("{}", self.reg_sys_clk_div_numerator().bits()), + ) + .field( + "reg_sys_clk_div_denominator", + &format_args!("{}", self.reg_sys_clk_div_denominator().bits()), + ) + .field( + "reg_apb_clk_div_num", + &format_args!("{}", self.reg_apb_clk_div_num().bits()), + ) + .field( + "reg_apb_clk_div_numerator", + &format_args!("{}", self.reg_apb_clk_div_numerator().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sys_clk_div_numerator( + &mut self, + ) -> REG_SYS_CLK_DIV_NUMERATOR_W { + REG_SYS_CLK_DIV_NUMERATOR_W::new(self, 0) + } + #[doc = "Bits 8:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sys_clk_div_denominator( + &mut self, + ) -> REG_SYS_CLK_DIV_DENOMINATOR_W { + REG_SYS_CLK_DIV_DENOMINATOR_W::new(self, 8) + } + #[doc = "Bits 16:23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_apb_clk_div_num(&mut self) -> REG_APB_CLK_DIV_NUM_W { + REG_APB_CLK_DIV_NUM_W::new(self, 16) + } + #[doc = "Bits 24:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_apb_clk_div_numerator( + &mut self, + ) -> REG_APB_CLK_DIV_NUMERATOR_W { + REG_APB_CLK_DIV_NUMERATOR_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`root_clk_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`root_clk_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ROOT_CLK_CTRL2_SPEC; +impl crate::RegisterSpec for ROOT_CLK_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`root_clk_ctrl2::R`](R) reader structure"] +impl crate::Readable for ROOT_CLK_CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`root_clk_ctrl2::W`](W) writer structure"] +impl crate::Writable for ROOT_CLK_CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ROOT_CLK_CTRL2 to value 0x0001_0000"] +impl crate::Resettable for ROOT_CLK_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0000; +} diff --git a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl3.rs b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl3.rs new file mode 100644 index 0000000000..4cb6715e4c --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl3.rs @@ -0,0 +1,68 @@ +#[doc = "Register `ROOT_CLK_CTRL3` reader"] +pub type R = crate::R; +#[doc = "Register `ROOT_CLK_CTRL3` writer"] +pub type W = crate::W; +#[doc = "Field `REG_APB_CLK_DIV_DENOMINATOR` reader - Reserved"] +pub type REG_APB_CLK_DIV_DENOMINATOR_R = crate::FieldReader; +#[doc = "Field `REG_APB_CLK_DIV_DENOMINATOR` writer - Reserved"] +pub type REG_APB_CLK_DIV_DENOMINATOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + pub fn reg_apb_clk_div_denominator(&self) -> REG_APB_CLK_DIV_DENOMINATOR_R { + REG_APB_CLK_DIV_DENOMINATOR_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ROOT_CLK_CTRL3") + .field( + "reg_apb_clk_div_denominator", + &format_args!("{}", self.reg_apb_clk_div_denominator().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_apb_clk_div_denominator( + &mut self, + ) -> REG_APB_CLK_DIV_DENOMINATOR_W { + REG_APB_CLK_DIV_DENOMINATOR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`root_clk_ctrl3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`root_clk_ctrl3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ROOT_CLK_CTRL3_SPEC; +impl crate::RegisterSpec for ROOT_CLK_CTRL3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`root_clk_ctrl3::R`](R) reader structure"] +impl crate::Readable for ROOT_CLK_CTRL3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`root_clk_ctrl3::W`](W) writer structure"] +impl crate::Writable for ROOT_CLK_CTRL3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ROOT_CLK_CTRL3 to value 0"] +impl crate::Resettable for ROOT_CLK_CTRL3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl0.rs new file mode 100644 index 0000000000..b304490a3d --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl0.rs @@ -0,0 +1,655 @@ +#[doc = "Register `SOC_CLK_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `SOC_CLK_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_CORE0_CLIC_CLK_EN` reader - Reserved"] +pub type REG_CORE0_CLIC_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CORE0_CLIC_CLK_EN` writer - Reserved"] +pub type REG_CORE0_CLIC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CORE1_CLIC_CLK_EN` reader - Reserved"] +pub type REG_CORE1_CLIC_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CORE1_CLIC_CLK_EN` writer - Reserved"] +pub type REG_CORE1_CLIC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MISC_CPU_CLK_EN` reader - Reserved"] +pub type REG_MISC_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_MISC_CPU_CLK_EN` writer - Reserved"] +pub type REG_MISC_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CORE0_CPU_CLK_EN` reader - Reserved"] +pub type REG_CORE0_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CORE0_CPU_CLK_EN` writer - Reserved"] +pub type REG_CORE0_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CORE1_CPU_CLK_EN` reader - Reserved"] +pub type REG_CORE1_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CORE1_CPU_CLK_EN` writer - Reserved"] +pub type REG_CORE1_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TCM_CPU_CLK_EN` reader - Reserved"] +pub type REG_TCM_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TCM_CPU_CLK_EN` writer - Reserved"] +pub type REG_TCM_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_BUSMON_CPU_CLK_EN` reader - Reserved"] +pub type REG_BUSMON_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_BUSMON_CPU_CLK_EN` writer - Reserved"] +pub type REG_BUSMON_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_CPU_CLK_EN` reader - Reserved"] +pub type REG_L1CACHE_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_CPU_CLK_EN` writer - Reserved"] +pub type REG_L1CACHE_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_D_CPU_CLK_EN` reader - Reserved"] +pub type REG_L1CACHE_D_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_D_CPU_CLK_EN` writer - Reserved"] +pub type REG_L1CACHE_D_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_I0_CPU_CLK_EN` reader - Reserved"] +pub type REG_L1CACHE_I0_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_I0_CPU_CLK_EN` writer - Reserved"] +pub type REG_L1CACHE_I0_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_I1_CPU_CLK_EN` reader - Reserved"] +pub type REG_L1CACHE_I1_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_I1_CPU_CLK_EN` writer - Reserved"] +pub type REG_L1CACHE_I1_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TRACE_CPU_CLK_EN` reader - Reserved"] +pub type REG_TRACE_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TRACE_CPU_CLK_EN` writer - Reserved"] +pub type REG_TRACE_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_ICM_CPU_CLK_EN` reader - Reserved"] +pub type REG_ICM_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_ICM_CPU_CLK_EN` writer - Reserved"] +pub type REG_ICM_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GDMA_CPU_CLK_EN` reader - Reserved"] +pub type REG_GDMA_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_GDMA_CPU_CLK_EN` writer - Reserved"] +pub type REG_GDMA_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_VPU_CPU_CLK_EN` reader - Reserved"] +pub type REG_VPU_CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_VPU_CPU_CLK_EN` writer - Reserved"] +pub type REG_VPU_CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_MEM_CLK_EN` reader - Reserved"] +pub type REG_L1CACHE_MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_MEM_CLK_EN` writer - Reserved"] +pub type REG_L1CACHE_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_D_MEM_CLK_EN` reader - Reserved"] +pub type REG_L1CACHE_D_MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_D_MEM_CLK_EN` writer - Reserved"] +pub type REG_L1CACHE_D_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_I0_MEM_CLK_EN` reader - Reserved"] +pub type REG_L1CACHE_I0_MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_I0_MEM_CLK_EN` writer - Reserved"] +pub type REG_L1CACHE_I0_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L1CACHE_I1_MEM_CLK_EN` reader - Reserved"] +pub type REG_L1CACHE_I1_MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L1CACHE_I1_MEM_CLK_EN` writer - Reserved"] +pub type REG_L1CACHE_I1_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L2CACHE_MEM_CLK_EN` reader - Reserved"] +pub type REG_L2CACHE_MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L2CACHE_MEM_CLK_EN` writer - Reserved"] +pub type REG_L2CACHE_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L2MEM_MEM_CLK_EN` reader - Reserved"] +pub type REG_L2MEM_MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L2MEM_MEM_CLK_EN` writer - Reserved"] +pub type REG_L2MEM_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L2MEMMON_MEM_CLK_EN` reader - Reserved"] +pub type REG_L2MEMMON_MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L2MEMMON_MEM_CLK_EN` writer - Reserved"] +pub type REG_L2MEMMON_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_ICM_MEM_CLK_EN` reader - Reserved"] +pub type REG_ICM_MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_ICM_MEM_CLK_EN` writer - Reserved"] +pub type REG_ICM_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MISC_SYS_CLK_EN` reader - Reserved"] +pub type REG_MISC_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_MISC_SYS_CLK_EN` writer - Reserved"] +pub type REG_MISC_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TRACE_SYS_CLK_EN` reader - Reserved"] +pub type REG_TRACE_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TRACE_SYS_CLK_EN` writer - Reserved"] +pub type REG_TRACE_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L2CACHE_SYS_CLK_EN` reader - Reserved"] +pub type REG_L2CACHE_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L2CACHE_SYS_CLK_EN` writer - Reserved"] +pub type REG_L2CACHE_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L2MEM_SYS_CLK_EN` reader - Reserved"] +pub type REG_L2MEM_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L2MEM_SYS_CLK_EN` writer - Reserved"] +pub type REG_L2MEM_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_L2MEMMON_SYS_CLK_EN` reader - Reserved"] +pub type REG_L2MEMMON_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_L2MEMMON_SYS_CLK_EN` writer - Reserved"] +pub type REG_L2MEMMON_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TCMMON_SYS_CLK_EN` reader - Reserved"] +pub type REG_TCMMON_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TCMMON_SYS_CLK_EN` writer - Reserved"] +pub type REG_TCMMON_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_ICM_SYS_CLK_EN` reader - Reserved"] +pub type REG_ICM_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_ICM_SYS_CLK_EN` writer - Reserved"] +pub type REG_ICM_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_FLASH_SYS_CLK_EN` reader - Reserved"] +pub type REG_FLASH_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_FLASH_SYS_CLK_EN` writer - Reserved"] +pub type REG_FLASH_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PSRAM_SYS_CLK_EN` reader - Reserved"] +pub type REG_PSRAM_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PSRAM_SYS_CLK_EN` writer - Reserved"] +pub type REG_PSRAM_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_core0_clic_clk_en(&self) -> REG_CORE0_CLIC_CLK_EN_R { + REG_CORE0_CLIC_CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_core1_clic_clk_en(&self) -> REG_CORE1_CLIC_CLK_EN_R { + REG_CORE1_CLIC_CLK_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_misc_cpu_clk_en(&self) -> REG_MISC_CPU_CLK_EN_R { + REG_MISC_CPU_CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_core0_cpu_clk_en(&self) -> REG_CORE0_CPU_CLK_EN_R { + REG_CORE0_CPU_CLK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_core1_cpu_clk_en(&self) -> REG_CORE1_CPU_CLK_EN_R { + REG_CORE1_CPU_CLK_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_tcm_cpu_clk_en(&self) -> REG_TCM_CPU_CLK_EN_R { + REG_TCM_CPU_CLK_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn reg_busmon_cpu_clk_en(&self) -> REG_BUSMON_CPU_CLK_EN_R { + REG_BUSMON_CPU_CLK_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_cpu_clk_en(&self) -> REG_L1CACHE_CPU_CLK_EN_R { + REG_L1CACHE_CPU_CLK_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_d_cpu_clk_en(&self) -> REG_L1CACHE_D_CPU_CLK_EN_R { + REG_L1CACHE_D_CPU_CLK_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_i0_cpu_clk_en(&self) -> REG_L1CACHE_I0_CPU_CLK_EN_R { + REG_L1CACHE_I0_CPU_CLK_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_i1_cpu_clk_en(&self) -> REG_L1CACHE_I1_CPU_CLK_EN_R { + REG_L1CACHE_I1_CPU_CLK_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn reg_trace_cpu_clk_en(&self) -> REG_TRACE_CPU_CLK_EN_R { + REG_TRACE_CPU_CLK_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn reg_icm_cpu_clk_en(&self) -> REG_ICM_CPU_CLK_EN_R { + REG_ICM_CPU_CLK_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn reg_gdma_cpu_clk_en(&self) -> REG_GDMA_CPU_CLK_EN_R { + REG_GDMA_CPU_CLK_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn reg_vpu_cpu_clk_en(&self) -> REG_VPU_CPU_CLK_EN_R { + REG_VPU_CPU_CLK_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_mem_clk_en(&self) -> REG_L1CACHE_MEM_CLK_EN_R { + REG_L1CACHE_MEM_CLK_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_d_mem_clk_en(&self) -> REG_L1CACHE_D_MEM_CLK_EN_R { + REG_L1CACHE_D_MEM_CLK_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_i0_mem_clk_en(&self) -> REG_L1CACHE_I0_MEM_CLK_EN_R { + REG_L1CACHE_I0_MEM_CLK_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_l1cache_i1_mem_clk_en(&self) -> REG_L1CACHE_I1_MEM_CLK_EN_R { + REG_L1CACHE_I1_MEM_CLK_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_l2cache_mem_clk_en(&self) -> REG_L2CACHE_MEM_CLK_EN_R { + REG_L2CACHE_MEM_CLK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_l2mem_mem_clk_en(&self) -> REG_L2MEM_MEM_CLK_EN_R { + REG_L2MEM_MEM_CLK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + pub fn reg_l2memmon_mem_clk_en(&self) -> REG_L2MEMMON_MEM_CLK_EN_R { + REG_L2MEMMON_MEM_CLK_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn reg_icm_mem_clk_en(&self) -> REG_ICM_MEM_CLK_EN_R { + REG_ICM_MEM_CLK_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + pub fn reg_misc_sys_clk_en(&self) -> REG_MISC_SYS_CLK_EN_R { + REG_MISC_SYS_CLK_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_trace_sys_clk_en(&self) -> REG_TRACE_SYS_CLK_EN_R { + REG_TRACE_SYS_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + pub fn reg_l2cache_sys_clk_en(&self) -> REG_L2CACHE_SYS_CLK_EN_R { + REG_L2CACHE_SYS_CLK_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_l2mem_sys_clk_en(&self) -> REG_L2MEM_SYS_CLK_EN_R { + REG_L2MEM_SYS_CLK_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_l2memmon_sys_clk_en(&self) -> REG_L2MEMMON_SYS_CLK_EN_R { + REG_L2MEMMON_SYS_CLK_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_tcmmon_sys_clk_en(&self) -> REG_TCMMON_SYS_CLK_EN_R { + REG_TCMMON_SYS_CLK_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_icm_sys_clk_en(&self) -> REG_ICM_SYS_CLK_EN_R { + REG_ICM_SYS_CLK_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + pub fn reg_flash_sys_clk_en(&self) -> REG_FLASH_SYS_CLK_EN_R { + REG_FLASH_SYS_CLK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn reg_psram_sys_clk_en(&self) -> REG_PSRAM_SYS_CLK_EN_R { + REG_PSRAM_SYS_CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SOC_CLK_CTRL0") + .field( + "reg_core0_clic_clk_en", + &format_args!("{}", self.reg_core0_clic_clk_en().bit()), + ) + .field( + "reg_core1_clic_clk_en", + &format_args!("{}", self.reg_core1_clic_clk_en().bit()), + ) + .field( + "reg_misc_cpu_clk_en", + &format_args!("{}", self.reg_misc_cpu_clk_en().bit()), + ) + .field( + "reg_core0_cpu_clk_en", + &format_args!("{}", self.reg_core0_cpu_clk_en().bit()), + ) + .field( + "reg_core1_cpu_clk_en", + &format_args!("{}", self.reg_core1_cpu_clk_en().bit()), + ) + .field( + "reg_tcm_cpu_clk_en", + &format_args!("{}", self.reg_tcm_cpu_clk_en().bit()), + ) + .field( + "reg_busmon_cpu_clk_en", + &format_args!("{}", self.reg_busmon_cpu_clk_en().bit()), + ) + .field( + "reg_l1cache_cpu_clk_en", + &format_args!("{}", self.reg_l1cache_cpu_clk_en().bit()), + ) + .field( + "reg_l1cache_d_cpu_clk_en", + &format_args!("{}", self.reg_l1cache_d_cpu_clk_en().bit()), + ) + .field( + "reg_l1cache_i0_cpu_clk_en", + &format_args!("{}", self.reg_l1cache_i0_cpu_clk_en().bit()), + ) + .field( + "reg_l1cache_i1_cpu_clk_en", + &format_args!("{}", self.reg_l1cache_i1_cpu_clk_en().bit()), + ) + .field( + "reg_trace_cpu_clk_en", + &format_args!("{}", self.reg_trace_cpu_clk_en().bit()), + ) + .field( + "reg_icm_cpu_clk_en", + &format_args!("{}", self.reg_icm_cpu_clk_en().bit()), + ) + .field( + "reg_gdma_cpu_clk_en", + &format_args!("{}", self.reg_gdma_cpu_clk_en().bit()), + ) + .field( + "reg_vpu_cpu_clk_en", + &format_args!("{}", self.reg_vpu_cpu_clk_en().bit()), + ) + .field( + "reg_l1cache_mem_clk_en", + &format_args!("{}", self.reg_l1cache_mem_clk_en().bit()), + ) + .field( + "reg_l1cache_d_mem_clk_en", + &format_args!("{}", self.reg_l1cache_d_mem_clk_en().bit()), + ) + .field( + "reg_l1cache_i0_mem_clk_en", + &format_args!("{}", self.reg_l1cache_i0_mem_clk_en().bit()), + ) + .field( + "reg_l1cache_i1_mem_clk_en", + &format_args!("{}", self.reg_l1cache_i1_mem_clk_en().bit()), + ) + .field( + "reg_l2cache_mem_clk_en", + &format_args!("{}", self.reg_l2cache_mem_clk_en().bit()), + ) + .field( + "reg_l2mem_mem_clk_en", + &format_args!("{}", self.reg_l2mem_mem_clk_en().bit()), + ) + .field( + "reg_l2memmon_mem_clk_en", + &format_args!("{}", self.reg_l2memmon_mem_clk_en().bit()), + ) + .field( + "reg_icm_mem_clk_en", + &format_args!("{}", self.reg_icm_mem_clk_en().bit()), + ) + .field( + "reg_misc_sys_clk_en", + &format_args!("{}", self.reg_misc_sys_clk_en().bit()), + ) + .field( + "reg_trace_sys_clk_en", + &format_args!("{}", self.reg_trace_sys_clk_en().bit()), + ) + .field( + "reg_l2cache_sys_clk_en", + &format_args!("{}", self.reg_l2cache_sys_clk_en().bit()), + ) + .field( + "reg_l2mem_sys_clk_en", + &format_args!("{}", self.reg_l2mem_sys_clk_en().bit()), + ) + .field( + "reg_l2memmon_sys_clk_en", + &format_args!("{}", self.reg_l2memmon_sys_clk_en().bit()), + ) + .field( + "reg_tcmmon_sys_clk_en", + &format_args!("{}", self.reg_tcmmon_sys_clk_en().bit()), + ) + .field( + "reg_icm_sys_clk_en", + &format_args!("{}", self.reg_icm_sys_clk_en().bit()), + ) + .field( + "reg_flash_sys_clk_en", + &format_args!("{}", self.reg_flash_sys_clk_en().bit()), + ) + .field( + "reg_psram_sys_clk_en", + &format_args!("{}", self.reg_psram_sys_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_core0_clic_clk_en(&mut self) -> REG_CORE0_CLIC_CLK_EN_W { + REG_CORE0_CLIC_CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_core1_clic_clk_en(&mut self) -> REG_CORE1_CLIC_CLK_EN_W { + REG_CORE1_CLIC_CLK_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_misc_cpu_clk_en(&mut self) -> REG_MISC_CPU_CLK_EN_W { + REG_MISC_CPU_CLK_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_core0_cpu_clk_en(&mut self) -> REG_CORE0_CPU_CLK_EN_W { + REG_CORE0_CPU_CLK_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_core1_cpu_clk_en(&mut self) -> REG_CORE1_CPU_CLK_EN_W { + REG_CORE1_CPU_CLK_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tcm_cpu_clk_en(&mut self) -> REG_TCM_CPU_CLK_EN_W { + REG_TCM_CPU_CLK_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_busmon_cpu_clk_en(&mut self) -> REG_BUSMON_CPU_CLK_EN_W { + REG_BUSMON_CPU_CLK_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_cpu_clk_en(&mut self) -> REG_L1CACHE_CPU_CLK_EN_W { + REG_L1CACHE_CPU_CLK_EN_W::new(self, 7) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_d_cpu_clk_en(&mut self) -> REG_L1CACHE_D_CPU_CLK_EN_W { + REG_L1CACHE_D_CPU_CLK_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_i0_cpu_clk_en(&mut self) -> REG_L1CACHE_I0_CPU_CLK_EN_W { + REG_L1CACHE_I0_CPU_CLK_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_i1_cpu_clk_en(&mut self) -> REG_L1CACHE_I1_CPU_CLK_EN_W { + REG_L1CACHE_I1_CPU_CLK_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_trace_cpu_clk_en(&mut self) -> REG_TRACE_CPU_CLK_EN_W { + REG_TRACE_CPU_CLK_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_icm_cpu_clk_en(&mut self) -> REG_ICM_CPU_CLK_EN_W { + REG_ICM_CPU_CLK_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gdma_cpu_clk_en(&mut self) -> REG_GDMA_CPU_CLK_EN_W { + REG_GDMA_CPU_CLK_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_vpu_cpu_clk_en(&mut self) -> REG_VPU_CPU_CLK_EN_W { + REG_VPU_CPU_CLK_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_mem_clk_en(&mut self) -> REG_L1CACHE_MEM_CLK_EN_W { + REG_L1CACHE_MEM_CLK_EN_W::new(self, 15) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_d_mem_clk_en(&mut self) -> REG_L1CACHE_D_MEM_CLK_EN_W { + REG_L1CACHE_D_MEM_CLK_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_i0_mem_clk_en(&mut self) -> REG_L1CACHE_I0_MEM_CLK_EN_W { + REG_L1CACHE_I0_MEM_CLK_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l1cache_i1_mem_clk_en(&mut self) -> REG_L1CACHE_I1_MEM_CLK_EN_W { + REG_L1CACHE_I1_MEM_CLK_EN_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l2cache_mem_clk_en(&mut self) -> REG_L2CACHE_MEM_CLK_EN_W { + REG_L2CACHE_MEM_CLK_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l2mem_mem_clk_en(&mut self) -> REG_L2MEM_MEM_CLK_EN_W { + REG_L2MEM_MEM_CLK_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l2memmon_mem_clk_en(&mut self) -> REG_L2MEMMON_MEM_CLK_EN_W { + REG_L2MEMMON_MEM_CLK_EN_W::new(self, 21) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_icm_mem_clk_en(&mut self) -> REG_ICM_MEM_CLK_EN_W { + REG_ICM_MEM_CLK_EN_W::new(self, 22) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_misc_sys_clk_en(&mut self) -> REG_MISC_SYS_CLK_EN_W { + REG_MISC_SYS_CLK_EN_W::new(self, 23) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_trace_sys_clk_en(&mut self) -> REG_TRACE_SYS_CLK_EN_W { + REG_TRACE_SYS_CLK_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l2cache_sys_clk_en(&mut self) -> REG_L2CACHE_SYS_CLK_EN_W { + REG_L2CACHE_SYS_CLK_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l2mem_sys_clk_en(&mut self) -> REG_L2MEM_SYS_CLK_EN_W { + REG_L2MEM_SYS_CLK_EN_W::new(self, 26) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_l2memmon_sys_clk_en(&mut self) -> REG_L2MEMMON_SYS_CLK_EN_W { + REG_L2MEMMON_SYS_CLK_EN_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_tcmmon_sys_clk_en(&mut self) -> REG_TCMMON_SYS_CLK_EN_W { + REG_TCMMON_SYS_CLK_EN_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_icm_sys_clk_en(&mut self) -> REG_ICM_SYS_CLK_EN_W { + REG_ICM_SYS_CLK_EN_W::new(self, 29) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_flash_sys_clk_en(&mut self) -> REG_FLASH_SYS_CLK_EN_W { + REG_FLASH_SYS_CLK_EN_W::new(self, 30) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_psram_sys_clk_en(&mut self) -> REG_PSRAM_SYS_CLK_EN_W { + REG_PSRAM_SYS_CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soc_clk_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soc_clk_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOC_CLK_CTRL0_SPEC; +impl crate::RegisterSpec for SOC_CLK_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`soc_clk_ctrl0::R`](R) reader structure"] +impl crate::Readable for SOC_CLK_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`soc_clk_ctrl0::W`](W) writer structure"] +impl crate::Writable for SOC_CLK_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SOC_CLK_CTRL0 to value 0xe6df_97af"] +impl crate::Resettable for SOC_CLK_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0xe6df_97af; +} diff --git a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl1.rs b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl1.rs new file mode 100644 index 0000000000..c8f34a57b2 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl1.rs @@ -0,0 +1,663 @@ +#[doc = "Register `SOC_CLK_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `SOC_CLK_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPSPI2_SYS_CLK_EN` reader - Reserved"] +pub type REG_GPSPI2_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_GPSPI2_SYS_CLK_EN` writer - Reserved"] +pub type REG_GPSPI2_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPSPI3_SYS_CLK_EN` reader - Reserved"] +pub type REG_GPSPI3_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_GPSPI3_SYS_CLK_EN` writer - Reserved"] +pub type REG_GPSPI3_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_REGDMA_SYS_CLK_EN` reader - Reserved"] +pub type REG_REGDMA_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_REGDMA_SYS_CLK_EN` writer - Reserved"] +pub type REG_REGDMA_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_AHB_PDMA_SYS_CLK_EN` reader - Reserved"] +pub type REG_AHB_PDMA_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_AHB_PDMA_SYS_CLK_EN` writer - Reserved"] +pub type REG_AHB_PDMA_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_AXI_PDMA_SYS_CLK_EN` reader - Reserved"] +pub type REG_AXI_PDMA_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_AXI_PDMA_SYS_CLK_EN` writer - Reserved"] +pub type REG_AXI_PDMA_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GDMA_SYS_CLK_EN` reader - Reserved"] +pub type REG_GDMA_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_GDMA_SYS_CLK_EN` writer - Reserved"] +pub type REG_GDMA_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_DMA2D_SYS_CLK_EN` reader - Reserved"] +pub type REG_DMA2D_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_DMA2D_SYS_CLK_EN` writer - Reserved"] +pub type REG_DMA2D_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_VPU_SYS_CLK_EN` reader - Reserved"] +pub type REG_VPU_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_VPU_SYS_CLK_EN` writer - Reserved"] +pub type REG_VPU_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_JPEG_SYS_CLK_EN` reader - Reserved"] +pub type REG_JPEG_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_JPEG_SYS_CLK_EN` writer - Reserved"] +pub type REG_JPEG_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PPA_SYS_CLK_EN` reader - Reserved"] +pub type REG_PPA_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PPA_SYS_CLK_EN` writer - Reserved"] +pub type REG_PPA_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CSI_BRG_SYS_CLK_EN` reader - Reserved"] +pub type REG_CSI_BRG_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CSI_BRG_SYS_CLK_EN` writer - Reserved"] +pub type REG_CSI_BRG_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CSI_HOST_SYS_CLK_EN` reader - Reserved"] +pub type REG_CSI_HOST_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CSI_HOST_SYS_CLK_EN` writer - Reserved"] +pub type REG_CSI_HOST_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_DSI_SYS_CLK_EN` reader - Reserved"] +pub type REG_DSI_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_DSI_SYS_CLK_EN` writer - Reserved"] +pub type REG_DSI_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_EMAC_SYS_CLK_EN` reader - Reserved"] +pub type REG_EMAC_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_EMAC_SYS_CLK_EN` writer - Reserved"] +pub type REG_EMAC_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SDMMC_SYS_CLK_EN` reader - Reserved"] +pub type REG_SDMMC_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_SDMMC_SYS_CLK_EN` writer - Reserved"] +pub type REG_SDMMC_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_USB_OTG11_SYS_CLK_EN` reader - Reserved"] +pub type REG_USB_OTG11_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_USB_OTG11_SYS_CLK_EN` writer - Reserved"] +pub type REG_USB_OTG11_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_USB_OTG20_SYS_CLK_EN` reader - Reserved"] +pub type REG_USB_OTG20_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_USB_OTG20_SYS_CLK_EN` writer - Reserved"] +pub type REG_USB_OTG20_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UHCI_SYS_CLK_EN` reader - Reserved"] +pub type REG_UHCI_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UHCI_SYS_CLK_EN` writer - Reserved"] +pub type REG_UHCI_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UART0_SYS_CLK_EN` reader - Reserved"] +pub type REG_UART0_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART0_SYS_CLK_EN` writer - Reserved"] +pub type REG_UART0_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UART1_SYS_CLK_EN` reader - Reserved"] +pub type REG_UART1_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART1_SYS_CLK_EN` writer - Reserved"] +pub type REG_UART1_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UART2_SYS_CLK_EN` reader - Reserved"] +pub type REG_UART2_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART2_SYS_CLK_EN` writer - Reserved"] +pub type REG_UART2_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UART3_SYS_CLK_EN` reader - Reserved"] +pub type REG_UART3_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART3_SYS_CLK_EN` writer - Reserved"] +pub type REG_UART3_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UART4_SYS_CLK_EN` reader - Reserved"] +pub type REG_UART4_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART4_SYS_CLK_EN` writer - Reserved"] +pub type REG_UART4_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PARLIO_SYS_CLK_EN` reader - Reserved"] +pub type REG_PARLIO_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PARLIO_SYS_CLK_EN` writer - Reserved"] +pub type REG_PARLIO_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_ETM_SYS_CLK_EN` reader - Reserved"] +pub type REG_ETM_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_ETM_SYS_CLK_EN` writer - Reserved"] +pub type REG_ETM_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PVT_SYS_CLK_EN` reader - Reserved"] +pub type REG_PVT_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PVT_SYS_CLK_EN` writer - Reserved"] +pub type REG_PVT_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CRYPTO_SYS_CLK_EN` reader - Reserved"] +pub type REG_CRYPTO_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CRYPTO_SYS_CLK_EN` writer - Reserved"] +pub type REG_CRYPTO_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_KEY_MANAGER_SYS_CLK_EN` reader - Reserved"] +pub type REG_KEY_MANAGER_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_KEY_MANAGER_SYS_CLK_EN` writer - Reserved"] +pub type REG_KEY_MANAGER_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_BITSRAMBLER_SYS_CLK_EN` reader - Reserved"] +pub type REG_BITSRAMBLER_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_BITSRAMBLER_SYS_CLK_EN` writer - Reserved"] +pub type REG_BITSRAMBLER_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_BITSRAMBLER_RX_SYS_CLK_EN` reader - Reserved"] +pub type REG_BITSRAMBLER_RX_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_BITSRAMBLER_RX_SYS_CLK_EN` writer - Reserved"] +pub type REG_BITSRAMBLER_RX_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_BITSRAMBLER_TX_SYS_CLK_EN` reader - Reserved"] +pub type REG_BITSRAMBLER_TX_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_BITSRAMBLER_TX_SYS_CLK_EN` writer - Reserved"] +pub type REG_BITSRAMBLER_TX_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_H264_SYS_CLK_EN` reader - Reserved"] +pub type REG_H264_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_H264_SYS_CLK_EN` writer - Reserved"] +pub type REG_H264_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpspi2_sys_clk_en(&self) -> REG_GPSPI2_SYS_CLK_EN_R { + REG_GPSPI2_SYS_CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpspi3_sys_clk_en(&self) -> REG_GPSPI3_SYS_CLK_EN_R { + REG_GPSPI3_SYS_CLK_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_regdma_sys_clk_en(&self) -> REG_REGDMA_SYS_CLK_EN_R { + REG_REGDMA_SYS_CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_ahb_pdma_sys_clk_en(&self) -> REG_AHB_PDMA_SYS_CLK_EN_R { + REG_AHB_PDMA_SYS_CLK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_axi_pdma_sys_clk_en(&self) -> REG_AXI_PDMA_SYS_CLK_EN_R { + REG_AXI_PDMA_SYS_CLK_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_gdma_sys_clk_en(&self) -> REG_GDMA_SYS_CLK_EN_R { + REG_GDMA_SYS_CLK_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn reg_dma2d_sys_clk_en(&self) -> REG_DMA2D_SYS_CLK_EN_R { + REG_DMA2D_SYS_CLK_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_vpu_sys_clk_en(&self) -> REG_VPU_SYS_CLK_EN_R { + REG_VPU_SYS_CLK_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_jpeg_sys_clk_en(&self) -> REG_JPEG_SYS_CLK_EN_R { + REG_JPEG_SYS_CLK_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_ppa_sys_clk_en(&self) -> REG_PPA_SYS_CLK_EN_R { + REG_PPA_SYS_CLK_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_csi_brg_sys_clk_en(&self) -> REG_CSI_BRG_SYS_CLK_EN_R { + REG_CSI_BRG_SYS_CLK_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn reg_csi_host_sys_clk_en(&self) -> REG_CSI_HOST_SYS_CLK_EN_R { + REG_CSI_HOST_SYS_CLK_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn reg_dsi_sys_clk_en(&self) -> REG_DSI_SYS_CLK_EN_R { + REG_DSI_SYS_CLK_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn reg_emac_sys_clk_en(&self) -> REG_EMAC_SYS_CLK_EN_R { + REG_EMAC_SYS_CLK_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn reg_sdmmc_sys_clk_en(&self) -> REG_SDMMC_SYS_CLK_EN_R { + REG_SDMMC_SYS_CLK_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn reg_usb_otg11_sys_clk_en(&self) -> REG_USB_OTG11_SYS_CLK_EN_R { + REG_USB_OTG11_SYS_CLK_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_usb_otg20_sys_clk_en(&self) -> REG_USB_OTG20_SYS_CLK_EN_R { + REG_USB_OTG20_SYS_CLK_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + pub fn reg_uhci_sys_clk_en(&self) -> REG_UHCI_SYS_CLK_EN_R { + REG_UHCI_SYS_CLK_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_uart0_sys_clk_en(&self) -> REG_UART0_SYS_CLK_EN_R { + REG_UART0_SYS_CLK_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_uart1_sys_clk_en(&self) -> REG_UART1_SYS_CLK_EN_R { + REG_UART1_SYS_CLK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_uart2_sys_clk_en(&self) -> REG_UART2_SYS_CLK_EN_R { + REG_UART2_SYS_CLK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + pub fn reg_uart3_sys_clk_en(&self) -> REG_UART3_SYS_CLK_EN_R { + REG_UART3_SYS_CLK_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn reg_uart4_sys_clk_en(&self) -> REG_UART4_SYS_CLK_EN_R { + REG_UART4_SYS_CLK_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + pub fn reg_parlio_sys_clk_en(&self) -> REG_PARLIO_SYS_CLK_EN_R { + REG_PARLIO_SYS_CLK_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_etm_sys_clk_en(&self) -> REG_ETM_SYS_CLK_EN_R { + REG_ETM_SYS_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + pub fn reg_pvt_sys_clk_en(&self) -> REG_PVT_SYS_CLK_EN_R { + REG_PVT_SYS_CLK_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_crypto_sys_clk_en(&self) -> REG_CRYPTO_SYS_CLK_EN_R { + REG_CRYPTO_SYS_CLK_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_key_manager_sys_clk_en(&self) -> REG_KEY_MANAGER_SYS_CLK_EN_R { + REG_KEY_MANAGER_SYS_CLK_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_bitsrambler_sys_clk_en(&self) -> REG_BITSRAMBLER_SYS_CLK_EN_R { + REG_BITSRAMBLER_SYS_CLK_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_bitsrambler_rx_sys_clk_en(&self) -> REG_BITSRAMBLER_RX_SYS_CLK_EN_R { + REG_BITSRAMBLER_RX_SYS_CLK_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + pub fn reg_bitsrambler_tx_sys_clk_en(&self) -> REG_BITSRAMBLER_TX_SYS_CLK_EN_R { + REG_BITSRAMBLER_TX_SYS_CLK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn reg_h264_sys_clk_en(&self) -> REG_H264_SYS_CLK_EN_R { + REG_H264_SYS_CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SOC_CLK_CTRL1") + .field( + "reg_gpspi2_sys_clk_en", + &format_args!("{}", self.reg_gpspi2_sys_clk_en().bit()), + ) + .field( + "reg_gpspi3_sys_clk_en", + &format_args!("{}", self.reg_gpspi3_sys_clk_en().bit()), + ) + .field( + "reg_regdma_sys_clk_en", + &format_args!("{}", self.reg_regdma_sys_clk_en().bit()), + ) + .field( + "reg_ahb_pdma_sys_clk_en", + &format_args!("{}", self.reg_ahb_pdma_sys_clk_en().bit()), + ) + .field( + "reg_axi_pdma_sys_clk_en", + &format_args!("{}", self.reg_axi_pdma_sys_clk_en().bit()), + ) + .field( + "reg_gdma_sys_clk_en", + &format_args!("{}", self.reg_gdma_sys_clk_en().bit()), + ) + .field( + "reg_dma2d_sys_clk_en", + &format_args!("{}", self.reg_dma2d_sys_clk_en().bit()), + ) + .field( + "reg_vpu_sys_clk_en", + &format_args!("{}", self.reg_vpu_sys_clk_en().bit()), + ) + .field( + "reg_jpeg_sys_clk_en", + &format_args!("{}", self.reg_jpeg_sys_clk_en().bit()), + ) + .field( + "reg_ppa_sys_clk_en", + &format_args!("{}", self.reg_ppa_sys_clk_en().bit()), + ) + .field( + "reg_csi_brg_sys_clk_en", + &format_args!("{}", self.reg_csi_brg_sys_clk_en().bit()), + ) + .field( + "reg_csi_host_sys_clk_en", + &format_args!("{}", self.reg_csi_host_sys_clk_en().bit()), + ) + .field( + "reg_dsi_sys_clk_en", + &format_args!("{}", self.reg_dsi_sys_clk_en().bit()), + ) + .field( + "reg_emac_sys_clk_en", + &format_args!("{}", self.reg_emac_sys_clk_en().bit()), + ) + .field( + "reg_sdmmc_sys_clk_en", + &format_args!("{}", self.reg_sdmmc_sys_clk_en().bit()), + ) + .field( + "reg_usb_otg11_sys_clk_en", + &format_args!("{}", self.reg_usb_otg11_sys_clk_en().bit()), + ) + .field( + "reg_usb_otg20_sys_clk_en", + &format_args!("{}", self.reg_usb_otg20_sys_clk_en().bit()), + ) + .field( + "reg_uhci_sys_clk_en", + &format_args!("{}", self.reg_uhci_sys_clk_en().bit()), + ) + .field( + "reg_uart0_sys_clk_en", + &format_args!("{}", self.reg_uart0_sys_clk_en().bit()), + ) + .field( + "reg_uart1_sys_clk_en", + &format_args!("{}", self.reg_uart1_sys_clk_en().bit()), + ) + .field( + "reg_uart2_sys_clk_en", + &format_args!("{}", self.reg_uart2_sys_clk_en().bit()), + ) + .field( + "reg_uart3_sys_clk_en", + &format_args!("{}", self.reg_uart3_sys_clk_en().bit()), + ) + .field( + "reg_uart4_sys_clk_en", + &format_args!("{}", self.reg_uart4_sys_clk_en().bit()), + ) + .field( + "reg_parlio_sys_clk_en", + &format_args!("{}", self.reg_parlio_sys_clk_en().bit()), + ) + .field( + "reg_etm_sys_clk_en", + &format_args!("{}", self.reg_etm_sys_clk_en().bit()), + ) + .field( + "reg_pvt_sys_clk_en", + &format_args!("{}", self.reg_pvt_sys_clk_en().bit()), + ) + .field( + "reg_crypto_sys_clk_en", + &format_args!("{}", self.reg_crypto_sys_clk_en().bit()), + ) + .field( + "reg_key_manager_sys_clk_en", + &format_args!("{}", self.reg_key_manager_sys_clk_en().bit()), + ) + .field( + "reg_bitsrambler_sys_clk_en", + &format_args!("{}", self.reg_bitsrambler_sys_clk_en().bit()), + ) + .field( + "reg_bitsrambler_rx_sys_clk_en", + &format_args!("{}", self.reg_bitsrambler_rx_sys_clk_en().bit()), + ) + .field( + "reg_bitsrambler_tx_sys_clk_en", + &format_args!("{}", self.reg_bitsrambler_tx_sys_clk_en().bit()), + ) + .field( + "reg_h264_sys_clk_en", + &format_args!("{}", self.reg_h264_sys_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi2_sys_clk_en(&mut self) -> REG_GPSPI2_SYS_CLK_EN_W { + REG_GPSPI2_SYS_CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi3_sys_clk_en(&mut self) -> REG_GPSPI3_SYS_CLK_EN_W { + REG_GPSPI3_SYS_CLK_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_regdma_sys_clk_en(&mut self) -> REG_REGDMA_SYS_CLK_EN_W { + REG_REGDMA_SYS_CLK_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ahb_pdma_sys_clk_en(&mut self) -> REG_AHB_PDMA_SYS_CLK_EN_W { + REG_AHB_PDMA_SYS_CLK_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_axi_pdma_sys_clk_en(&mut self) -> REG_AXI_PDMA_SYS_CLK_EN_W { + REG_AXI_PDMA_SYS_CLK_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gdma_sys_clk_en(&mut self) -> REG_GDMA_SYS_CLK_EN_W { + REG_GDMA_SYS_CLK_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dma2d_sys_clk_en(&mut self) -> REG_DMA2D_SYS_CLK_EN_W { + REG_DMA2D_SYS_CLK_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_vpu_sys_clk_en(&mut self) -> REG_VPU_SYS_CLK_EN_W { + REG_VPU_SYS_CLK_EN_W::new(self, 7) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_jpeg_sys_clk_en(&mut self) -> REG_JPEG_SYS_CLK_EN_W { + REG_JPEG_SYS_CLK_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ppa_sys_clk_en(&mut self) -> REG_PPA_SYS_CLK_EN_W { + REG_PPA_SYS_CLK_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_csi_brg_sys_clk_en(&mut self) -> REG_CSI_BRG_SYS_CLK_EN_W { + REG_CSI_BRG_SYS_CLK_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_csi_host_sys_clk_en(&mut self) -> REG_CSI_HOST_SYS_CLK_EN_W { + REG_CSI_HOST_SYS_CLK_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dsi_sys_clk_en(&mut self) -> REG_DSI_SYS_CLK_EN_W { + REG_DSI_SYS_CLK_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_emac_sys_clk_en(&mut self) -> REG_EMAC_SYS_CLK_EN_W { + REG_EMAC_SYS_CLK_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sdmmc_sys_clk_en(&mut self) -> REG_SDMMC_SYS_CLK_EN_W { + REG_SDMMC_SYS_CLK_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_usb_otg11_sys_clk_en(&mut self) -> REG_USB_OTG11_SYS_CLK_EN_W { + REG_USB_OTG11_SYS_CLK_EN_W::new(self, 15) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_usb_otg20_sys_clk_en(&mut self) -> REG_USB_OTG20_SYS_CLK_EN_W { + REG_USB_OTG20_SYS_CLK_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uhci_sys_clk_en(&mut self) -> REG_UHCI_SYS_CLK_EN_W { + REG_UHCI_SYS_CLK_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart0_sys_clk_en(&mut self) -> REG_UART0_SYS_CLK_EN_W { + REG_UART0_SYS_CLK_EN_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart1_sys_clk_en(&mut self) -> REG_UART1_SYS_CLK_EN_W { + REG_UART1_SYS_CLK_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart2_sys_clk_en(&mut self) -> REG_UART2_SYS_CLK_EN_W { + REG_UART2_SYS_CLK_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart3_sys_clk_en(&mut self) -> REG_UART3_SYS_CLK_EN_W { + REG_UART3_SYS_CLK_EN_W::new(self, 21) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart4_sys_clk_en(&mut self) -> REG_UART4_SYS_CLK_EN_W { + REG_UART4_SYS_CLK_EN_W::new(self, 22) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_sys_clk_en(&mut self) -> REG_PARLIO_SYS_CLK_EN_W { + REG_PARLIO_SYS_CLK_EN_W::new(self, 23) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_etm_sys_clk_en(&mut self) -> REG_ETM_SYS_CLK_EN_W { + REG_ETM_SYS_CLK_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pvt_sys_clk_en(&mut self) -> REG_PVT_SYS_CLK_EN_W { + REG_PVT_SYS_CLK_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_crypto_sys_clk_en(&mut self) -> REG_CRYPTO_SYS_CLK_EN_W { + REG_CRYPTO_SYS_CLK_EN_W::new(self, 26) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_key_manager_sys_clk_en( + &mut self, + ) -> REG_KEY_MANAGER_SYS_CLK_EN_W { + REG_KEY_MANAGER_SYS_CLK_EN_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_bitsrambler_sys_clk_en( + &mut self, + ) -> REG_BITSRAMBLER_SYS_CLK_EN_W { + REG_BITSRAMBLER_SYS_CLK_EN_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_bitsrambler_rx_sys_clk_en( + &mut self, + ) -> REG_BITSRAMBLER_RX_SYS_CLK_EN_W { + REG_BITSRAMBLER_RX_SYS_CLK_EN_W::new(self, 29) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_bitsrambler_tx_sys_clk_en( + &mut self, + ) -> REG_BITSRAMBLER_TX_SYS_CLK_EN_W { + REG_BITSRAMBLER_TX_SYS_CLK_EN_W::new(self, 30) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_h264_sys_clk_en(&mut self) -> REG_H264_SYS_CLK_EN_W { + REG_H264_SYS_CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soc_clk_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soc_clk_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOC_CLK_CTRL1_SPEC; +impl crate::RegisterSpec for SOC_CLK_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`soc_clk_ctrl1::R`](R) reader structure"] +impl crate::Readable for SOC_CLK_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`soc_clk_ctrl1::W`](W) writer structure"] +impl crate::Writable for SOC_CLK_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SOC_CLK_CTRL1 to value 0x7c7f_801f"] +impl crate::Resettable for SOC_CLK_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0x7c7f_801f; +} diff --git a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl2.rs b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl2.rs new file mode 100644 index 0000000000..d24d2d579a --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl2.rs @@ -0,0 +1,655 @@ +#[doc = "Register `SOC_CLK_CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `SOC_CLK_CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `REG_RMT_SYS_CLK_EN` reader - Reserved"] +pub type REG_RMT_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_RMT_SYS_CLK_EN` writer - Reserved"] +pub type REG_RMT_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_HP_CLKRST_APB_CLK_EN` reader - Reserved"] +pub type REG_HP_CLKRST_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_HP_CLKRST_APB_CLK_EN` writer - Reserved"] +pub type REG_HP_CLKRST_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SYSREG_APB_CLK_EN` reader - Reserved"] +pub type REG_SYSREG_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_SYSREG_APB_CLK_EN` writer - Reserved"] +pub type REG_SYSREG_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_ICM_APB_CLK_EN` reader - Reserved"] +pub type REG_ICM_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_ICM_APB_CLK_EN` writer - Reserved"] +pub type REG_ICM_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_INTRMTX_APB_CLK_EN` reader - Reserved"] +pub type REG_INTRMTX_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_INTRMTX_APB_CLK_EN` writer - Reserved"] +pub type REG_INTRMTX_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_ADC_APB_CLK_EN` reader - Reserved"] +pub type REG_ADC_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_ADC_APB_CLK_EN` writer - Reserved"] +pub type REG_ADC_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UHCI_APB_CLK_EN` reader - Reserved"] +pub type REG_UHCI_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UHCI_APB_CLK_EN` writer - Reserved"] +pub type REG_UHCI_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UART0_APB_CLK_EN` reader - Reserved"] +pub type REG_UART0_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART0_APB_CLK_EN` writer - Reserved"] +pub type REG_UART0_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UART1_APB_CLK_EN` reader - Reserved"] +pub type REG_UART1_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART1_APB_CLK_EN` writer - Reserved"] +pub type REG_UART1_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UART2_APB_CLK_EN` reader - Reserved"] +pub type REG_UART2_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART2_APB_CLK_EN` writer - Reserved"] +pub type REG_UART2_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UART3_APB_CLK_EN` reader - Reserved"] +pub type REG_UART3_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART3_APB_CLK_EN` writer - Reserved"] +pub type REG_UART3_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_UART4_APB_CLK_EN` reader - Reserved"] +pub type REG_UART4_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_UART4_APB_CLK_EN` writer - Reserved"] +pub type REG_UART4_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2C0_APB_CLK_EN` reader - Reserved"] +pub type REG_I2C0_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2C0_APB_CLK_EN` writer - Reserved"] +pub type REG_I2C0_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2C1_APB_CLK_EN` reader - Reserved"] +pub type REG_I2C1_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2C1_APB_CLK_EN` writer - Reserved"] +pub type REG_I2C1_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S0_APB_CLK_EN` reader - Reserved"] +pub type REG_I2S0_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2S0_APB_CLK_EN` writer - Reserved"] +pub type REG_I2S0_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S1_APB_CLK_EN` reader - Reserved"] +pub type REG_I2S1_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2S1_APB_CLK_EN` writer - Reserved"] +pub type REG_I2S1_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I2S2_APB_CLK_EN` reader - Reserved"] +pub type REG_I2S2_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I2S2_APB_CLK_EN` writer - Reserved"] +pub type REG_I2S2_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I3C_MST_APB_CLK_EN` reader - Reserved"] +pub type REG_I3C_MST_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I3C_MST_APB_CLK_EN` writer - Reserved"] +pub type REG_I3C_MST_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_I3C_SLV_APB_CLK_EN` reader - Reserved"] +pub type REG_I3C_SLV_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_I3C_SLV_APB_CLK_EN` writer - Reserved"] +pub type REG_I3C_SLV_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPSPI2_APB_CLK_EN` reader - Reserved"] +pub type REG_GPSPI2_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_GPSPI2_APB_CLK_EN` writer - Reserved"] +pub type REG_GPSPI2_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPSPI3_APB_CLK_EN` reader - Reserved"] +pub type REG_GPSPI3_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_GPSPI3_APB_CLK_EN` writer - Reserved"] +pub type REG_GPSPI3_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TIMERGRP0_APB_CLK_EN` reader - Reserved"] +pub type REG_TIMERGRP0_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TIMERGRP0_APB_CLK_EN` writer - Reserved"] +pub type REG_TIMERGRP0_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TIMERGRP1_APB_CLK_EN` reader - Reserved"] +pub type REG_TIMERGRP1_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TIMERGRP1_APB_CLK_EN` writer - Reserved"] +pub type REG_TIMERGRP1_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SYSTIMER_APB_CLK_EN` reader - Reserved"] +pub type REG_SYSTIMER_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_SYSTIMER_APB_CLK_EN` writer - Reserved"] +pub type REG_SYSTIMER_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TWAI0_APB_CLK_EN` reader - Reserved"] +pub type REG_TWAI0_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TWAI0_APB_CLK_EN` writer - Reserved"] +pub type REG_TWAI0_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TWAI1_APB_CLK_EN` reader - Reserved"] +pub type REG_TWAI1_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TWAI1_APB_CLK_EN` writer - Reserved"] +pub type REG_TWAI1_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TWAI2_APB_CLK_EN` reader - Reserved"] +pub type REG_TWAI2_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_TWAI2_APB_CLK_EN` writer - Reserved"] +pub type REG_TWAI2_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MCPWM0_APB_CLK_EN` reader - Reserved"] +pub type REG_MCPWM0_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_MCPWM0_APB_CLK_EN` writer - Reserved"] +pub type REG_MCPWM0_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MCPWM1_APB_CLK_EN` reader - Reserved"] +pub type REG_MCPWM1_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_MCPWM1_APB_CLK_EN` writer - Reserved"] +pub type REG_MCPWM1_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_USB_DEVICE_APB_CLK_EN` reader - Reserved"] +pub type REG_USB_DEVICE_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_USB_DEVICE_APB_CLK_EN` writer - Reserved"] +pub type REG_USB_DEVICE_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PCNT_APB_CLK_EN` reader - Reserved"] +pub type REG_PCNT_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PCNT_APB_CLK_EN` writer - Reserved"] +pub type REG_PCNT_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PARLIO_APB_CLK_EN` reader - Reserved"] +pub type REG_PARLIO_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_PARLIO_APB_CLK_EN` writer - Reserved"] +pub type REG_PARLIO_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_rmt_sys_clk_en(&self) -> REG_RMT_SYS_CLK_EN_R { + REG_RMT_SYS_CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_hp_clkrst_apb_clk_en(&self) -> REG_HP_CLKRST_APB_CLK_EN_R { + REG_HP_CLKRST_APB_CLK_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_sysreg_apb_clk_en(&self) -> REG_SYSREG_APB_CLK_EN_R { + REG_SYSREG_APB_CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_icm_apb_clk_en(&self) -> REG_ICM_APB_CLK_EN_R { + REG_ICM_APB_CLK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_intrmtx_apb_clk_en(&self) -> REG_INTRMTX_APB_CLK_EN_R { + REG_INTRMTX_APB_CLK_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + pub fn reg_adc_apb_clk_en(&self) -> REG_ADC_APB_CLK_EN_R { + REG_ADC_APB_CLK_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + pub fn reg_uhci_apb_clk_en(&self) -> REG_UHCI_APB_CLK_EN_R { + REG_UHCI_APB_CLK_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + pub fn reg_uart0_apb_clk_en(&self) -> REG_UART0_APB_CLK_EN_R { + REG_UART0_APB_CLK_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + pub fn reg_uart1_apb_clk_en(&self) -> REG_UART1_APB_CLK_EN_R { + REG_UART1_APB_CLK_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + pub fn reg_uart2_apb_clk_en(&self) -> REG_UART2_APB_CLK_EN_R { + REG_UART2_APB_CLK_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + pub fn reg_uart3_apb_clk_en(&self) -> REG_UART3_APB_CLK_EN_R { + REG_UART3_APB_CLK_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + pub fn reg_uart4_apb_clk_en(&self) -> REG_UART4_APB_CLK_EN_R { + REG_UART4_APB_CLK_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + pub fn reg_i2c0_apb_clk_en(&self) -> REG_I2C0_APB_CLK_EN_R { + REG_I2C0_APB_CLK_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + pub fn reg_i2c1_apb_clk_en(&self) -> REG_I2C1_APB_CLK_EN_R { + REG_I2C1_APB_CLK_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + pub fn reg_i2s0_apb_clk_en(&self) -> REG_I2S0_APB_CLK_EN_R { + REG_I2S0_APB_CLK_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + pub fn reg_i2s1_apb_clk_en(&self) -> REG_I2S1_APB_CLK_EN_R { + REG_I2S1_APB_CLK_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + pub fn reg_i2s2_apb_clk_en(&self) -> REG_I2S2_APB_CLK_EN_R { + REG_I2S2_APB_CLK_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + pub fn reg_i3c_mst_apb_clk_en(&self) -> REG_I3C_MST_APB_CLK_EN_R { + REG_I3C_MST_APB_CLK_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + pub fn reg_i3c_slv_apb_clk_en(&self) -> REG_I3C_SLV_APB_CLK_EN_R { + REG_I3C_SLV_APB_CLK_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + pub fn reg_gpspi2_apb_clk_en(&self) -> REG_GPSPI2_APB_CLK_EN_R { + REG_GPSPI2_APB_CLK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + pub fn reg_gpspi3_apb_clk_en(&self) -> REG_GPSPI3_APB_CLK_EN_R { + REG_GPSPI3_APB_CLK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + pub fn reg_timergrp0_apb_clk_en(&self) -> REG_TIMERGRP0_APB_CLK_EN_R { + REG_TIMERGRP0_APB_CLK_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + pub fn reg_timergrp1_apb_clk_en(&self) -> REG_TIMERGRP1_APB_CLK_EN_R { + REG_TIMERGRP1_APB_CLK_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + pub fn reg_systimer_apb_clk_en(&self) -> REG_SYSTIMER_APB_CLK_EN_R { + REG_SYSTIMER_APB_CLK_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + pub fn reg_twai0_apb_clk_en(&self) -> REG_TWAI0_APB_CLK_EN_R { + REG_TWAI0_APB_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + pub fn reg_twai1_apb_clk_en(&self) -> REG_TWAI1_APB_CLK_EN_R { + REG_TWAI1_APB_CLK_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn reg_twai2_apb_clk_en(&self) -> REG_TWAI2_APB_CLK_EN_R { + REG_TWAI2_APB_CLK_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn reg_mcpwm0_apb_clk_en(&self) -> REG_MCPWM0_APB_CLK_EN_R { + REG_MCPWM0_APB_CLK_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn reg_mcpwm1_apb_clk_en(&self) -> REG_MCPWM1_APB_CLK_EN_R { + REG_MCPWM1_APB_CLK_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn reg_usb_device_apb_clk_en(&self) -> REG_USB_DEVICE_APB_CLK_EN_R { + REG_USB_DEVICE_APB_CLK_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + pub fn reg_pcnt_apb_clk_en(&self) -> REG_PCNT_APB_CLK_EN_R { + REG_PCNT_APB_CLK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn reg_parlio_apb_clk_en(&self) -> REG_PARLIO_APB_CLK_EN_R { + REG_PARLIO_APB_CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SOC_CLK_CTRL2") + .field( + "reg_rmt_sys_clk_en", + &format_args!("{}", self.reg_rmt_sys_clk_en().bit()), + ) + .field( + "reg_hp_clkrst_apb_clk_en", + &format_args!("{}", self.reg_hp_clkrst_apb_clk_en().bit()), + ) + .field( + "reg_sysreg_apb_clk_en", + &format_args!("{}", self.reg_sysreg_apb_clk_en().bit()), + ) + .field( + "reg_icm_apb_clk_en", + &format_args!("{}", self.reg_icm_apb_clk_en().bit()), + ) + .field( + "reg_intrmtx_apb_clk_en", + &format_args!("{}", self.reg_intrmtx_apb_clk_en().bit()), + ) + .field( + "reg_adc_apb_clk_en", + &format_args!("{}", self.reg_adc_apb_clk_en().bit()), + ) + .field( + "reg_uhci_apb_clk_en", + &format_args!("{}", self.reg_uhci_apb_clk_en().bit()), + ) + .field( + "reg_uart0_apb_clk_en", + &format_args!("{}", self.reg_uart0_apb_clk_en().bit()), + ) + .field( + "reg_uart1_apb_clk_en", + &format_args!("{}", self.reg_uart1_apb_clk_en().bit()), + ) + .field( + "reg_uart2_apb_clk_en", + &format_args!("{}", self.reg_uart2_apb_clk_en().bit()), + ) + .field( + "reg_uart3_apb_clk_en", + &format_args!("{}", self.reg_uart3_apb_clk_en().bit()), + ) + .field( + "reg_uart4_apb_clk_en", + &format_args!("{}", self.reg_uart4_apb_clk_en().bit()), + ) + .field( + "reg_i2c0_apb_clk_en", + &format_args!("{}", self.reg_i2c0_apb_clk_en().bit()), + ) + .field( + "reg_i2c1_apb_clk_en", + &format_args!("{}", self.reg_i2c1_apb_clk_en().bit()), + ) + .field( + "reg_i2s0_apb_clk_en", + &format_args!("{}", self.reg_i2s0_apb_clk_en().bit()), + ) + .field( + "reg_i2s1_apb_clk_en", + &format_args!("{}", self.reg_i2s1_apb_clk_en().bit()), + ) + .field( + "reg_i2s2_apb_clk_en", + &format_args!("{}", self.reg_i2s2_apb_clk_en().bit()), + ) + .field( + "reg_i3c_mst_apb_clk_en", + &format_args!("{}", self.reg_i3c_mst_apb_clk_en().bit()), + ) + .field( + "reg_i3c_slv_apb_clk_en", + &format_args!("{}", self.reg_i3c_slv_apb_clk_en().bit()), + ) + .field( + "reg_gpspi2_apb_clk_en", + &format_args!("{}", self.reg_gpspi2_apb_clk_en().bit()), + ) + .field( + "reg_gpspi3_apb_clk_en", + &format_args!("{}", self.reg_gpspi3_apb_clk_en().bit()), + ) + .field( + "reg_timergrp0_apb_clk_en", + &format_args!("{}", self.reg_timergrp0_apb_clk_en().bit()), + ) + .field( + "reg_timergrp1_apb_clk_en", + &format_args!("{}", self.reg_timergrp1_apb_clk_en().bit()), + ) + .field( + "reg_systimer_apb_clk_en", + &format_args!("{}", self.reg_systimer_apb_clk_en().bit()), + ) + .field( + "reg_twai0_apb_clk_en", + &format_args!("{}", self.reg_twai0_apb_clk_en().bit()), + ) + .field( + "reg_twai1_apb_clk_en", + &format_args!("{}", self.reg_twai1_apb_clk_en().bit()), + ) + .field( + "reg_twai2_apb_clk_en", + &format_args!("{}", self.reg_twai2_apb_clk_en().bit()), + ) + .field( + "reg_mcpwm0_apb_clk_en", + &format_args!("{}", self.reg_mcpwm0_apb_clk_en().bit()), + ) + .field( + "reg_mcpwm1_apb_clk_en", + &format_args!("{}", self.reg_mcpwm1_apb_clk_en().bit()), + ) + .field( + "reg_usb_device_apb_clk_en", + &format_args!("{}", self.reg_usb_device_apb_clk_en().bit()), + ) + .field( + "reg_pcnt_apb_clk_en", + &format_args!("{}", self.reg_pcnt_apb_clk_en().bit()), + ) + .field( + "reg_parlio_apb_clk_en", + &format_args!("{}", self.reg_parlio_apb_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_rmt_sys_clk_en(&mut self) -> REG_RMT_SYS_CLK_EN_W { + REG_RMT_SYS_CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_hp_clkrst_apb_clk_en(&mut self) -> REG_HP_CLKRST_APB_CLK_EN_W { + REG_HP_CLKRST_APB_CLK_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_sysreg_apb_clk_en(&mut self) -> REG_SYSREG_APB_CLK_EN_W { + REG_SYSREG_APB_CLK_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_icm_apb_clk_en(&mut self) -> REG_ICM_APB_CLK_EN_W { + REG_ICM_APB_CLK_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_intrmtx_apb_clk_en(&mut self) -> REG_INTRMTX_APB_CLK_EN_W { + REG_INTRMTX_APB_CLK_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_adc_apb_clk_en(&mut self) -> REG_ADC_APB_CLK_EN_W { + REG_ADC_APB_CLK_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uhci_apb_clk_en(&mut self) -> REG_UHCI_APB_CLK_EN_W { + REG_UHCI_APB_CLK_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart0_apb_clk_en(&mut self) -> REG_UART0_APB_CLK_EN_W { + REG_UART0_APB_CLK_EN_W::new(self, 7) + } + #[doc = "Bit 8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart1_apb_clk_en(&mut self) -> REG_UART1_APB_CLK_EN_W { + REG_UART1_APB_CLK_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart2_apb_clk_en(&mut self) -> REG_UART2_APB_CLK_EN_W { + REG_UART2_APB_CLK_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart3_apb_clk_en(&mut self) -> REG_UART3_APB_CLK_EN_W { + REG_UART3_APB_CLK_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_uart4_apb_clk_en(&mut self) -> REG_UART4_APB_CLK_EN_W { + REG_UART4_APB_CLK_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c0_apb_clk_en(&mut self) -> REG_I2C0_APB_CLK_EN_W { + REG_I2C0_APB_CLK_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2c1_apb_clk_en(&mut self) -> REG_I2C1_APB_CLK_EN_W { + REG_I2C1_APB_CLK_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s0_apb_clk_en(&mut self) -> REG_I2S0_APB_CLK_EN_W { + REG_I2S0_APB_CLK_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s1_apb_clk_en(&mut self) -> REG_I2S1_APB_CLK_EN_W { + REG_I2S1_APB_CLK_EN_W::new(self, 15) + } + #[doc = "Bit 16 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i2s2_apb_clk_en(&mut self) -> REG_I2S2_APB_CLK_EN_W { + REG_I2S2_APB_CLK_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_apb_clk_en(&mut self) -> REG_I3C_MST_APB_CLK_EN_W { + REG_I3C_MST_APB_CLK_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_slv_apb_clk_en(&mut self) -> REG_I3C_SLV_APB_CLK_EN_W { + REG_I3C_SLV_APB_CLK_EN_W::new(self, 18) + } + #[doc = "Bit 19 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi2_apb_clk_en(&mut self) -> REG_GPSPI2_APB_CLK_EN_W { + REG_GPSPI2_APB_CLK_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpspi3_apb_clk_en(&mut self) -> REG_GPSPI3_APB_CLK_EN_W { + REG_GPSPI3_APB_CLK_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp0_apb_clk_en(&mut self) -> REG_TIMERGRP0_APB_CLK_EN_W { + REG_TIMERGRP0_APB_CLK_EN_W::new(self, 21) + } + #[doc = "Bit 22 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_timergrp1_apb_clk_en(&mut self) -> REG_TIMERGRP1_APB_CLK_EN_W { + REG_TIMERGRP1_APB_CLK_EN_W::new(self, 22) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_systimer_apb_clk_en(&mut self) -> REG_SYSTIMER_APB_CLK_EN_W { + REG_SYSTIMER_APB_CLK_EN_W::new(self, 23) + } + #[doc = "Bit 24 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_twai0_apb_clk_en(&mut self) -> REG_TWAI0_APB_CLK_EN_W { + REG_TWAI0_APB_CLK_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_twai1_apb_clk_en(&mut self) -> REG_TWAI1_APB_CLK_EN_W { + REG_TWAI1_APB_CLK_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_twai2_apb_clk_en(&mut self) -> REG_TWAI2_APB_CLK_EN_W { + REG_TWAI2_APB_CLK_EN_W::new(self, 26) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mcpwm0_apb_clk_en(&mut self) -> REG_MCPWM0_APB_CLK_EN_W { + REG_MCPWM0_APB_CLK_EN_W::new(self, 27) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_mcpwm1_apb_clk_en(&mut self) -> REG_MCPWM1_APB_CLK_EN_W { + REG_MCPWM1_APB_CLK_EN_W::new(self, 28) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_usb_device_apb_clk_en(&mut self) -> REG_USB_DEVICE_APB_CLK_EN_W { + REG_USB_DEVICE_APB_CLK_EN_W::new(self, 29) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pcnt_apb_clk_en(&mut self) -> REG_PCNT_APB_CLK_EN_W { + REG_PCNT_APB_CLK_EN_W::new(self, 30) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_parlio_apb_clk_en(&mut self) -> REG_PARLIO_APB_CLK_EN_W { + REG_PARLIO_APB_CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soc_clk_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soc_clk_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOC_CLK_CTRL2_SPEC; +impl crate::RegisterSpec for SOC_CLK_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`soc_clk_ctrl2::R`](R) reader structure"] +impl crate::Readable for SOC_CLK_CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`soc_clk_ctrl2::W`](W) writer structure"] +impl crate::Writable for SOC_CLK_CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SOC_CLK_CTRL2 to value 0x20f8_0fde"] +impl crate::Resettable for SOC_CLK_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0x20f8_0fde; +} diff --git a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl3.rs b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl3.rs new file mode 100644 index 0000000000..c0d3976c00 --- /dev/null +++ b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl3.rs @@ -0,0 +1,123 @@ +#[doc = "Register `SOC_CLK_CTRL3` reader"] +pub type R = crate::R; +#[doc = "Register `SOC_CLK_CTRL3` writer"] +pub type W = crate::W; +#[doc = "Field `REG_LEDC_APB_CLK_EN` reader - Reserved"] +pub type REG_LEDC_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_LEDC_APB_CLK_EN` writer - Reserved"] +pub type REG_LEDC_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_LCDCAM_APB_CLK_EN` reader - Reserved"] +pub type REG_LCDCAM_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_LCDCAM_APB_CLK_EN` writer - Reserved"] +pub type REG_LCDCAM_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_ETM_APB_CLK_EN` reader - Reserved"] +pub type REG_ETM_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_ETM_APB_CLK_EN` writer - Reserved"] +pub type REG_ETM_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_IOMUX_APB_CLK_EN` reader - Reserved"] +pub type REG_IOMUX_APB_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_IOMUX_APB_CLK_EN` writer - Reserved"] +pub type REG_IOMUX_APB_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_ledc_apb_clk_en(&self) -> REG_LEDC_APB_CLK_EN_R { + REG_LEDC_APB_CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_lcdcam_apb_clk_en(&self) -> REG_LCDCAM_APB_CLK_EN_R { + REG_LCDCAM_APB_CLK_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_etm_apb_clk_en(&self) -> REG_ETM_APB_CLK_EN_R { + REG_ETM_APB_CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_iomux_apb_clk_en(&self) -> REG_IOMUX_APB_CLK_EN_R { + REG_IOMUX_APB_CLK_EN_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SOC_CLK_CTRL3") + .field( + "reg_ledc_apb_clk_en", + &format_args!("{}", self.reg_ledc_apb_clk_en().bit()), + ) + .field( + "reg_lcdcam_apb_clk_en", + &format_args!("{}", self.reg_lcdcam_apb_clk_en().bit()), + ) + .field( + "reg_etm_apb_clk_en", + &format_args!("{}", self.reg_etm_apb_clk_en().bit()), + ) + .field( + "reg_iomux_apb_clk_en", + &format_args!("{}", self.reg_iomux_apb_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ledc_apb_clk_en(&mut self) -> REG_LEDC_APB_CLK_EN_W { + REG_LEDC_APB_CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_lcdcam_apb_clk_en(&mut self) -> REG_LCDCAM_APB_CLK_EN_W { + REG_LCDCAM_APB_CLK_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_etm_apb_clk_en(&mut self) -> REG_ETM_APB_CLK_EN_W { + REG_ETM_APB_CLK_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_iomux_apb_clk_en(&mut self) -> REG_IOMUX_APB_CLK_EN_W { + REG_IOMUX_APB_CLK_EN_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soc_clk_ctrl3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soc_clk_ctrl3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOC_CLK_CTRL3_SPEC; +impl crate::RegisterSpec for SOC_CLK_CTRL3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`soc_clk_ctrl3::R`](R) reader structure"] +impl crate::Readable for SOC_CLK_CTRL3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`soc_clk_ctrl3::W`](W) writer structure"] +impl crate::Writable for SOC_CLK_CTRL3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SOC_CLK_CTRL3 to value 0x08"] +impl crate::Resettable for SOC_CLK_CTRL3_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/i2c0.rs b/esp32p4/src/i2c0.rs new file mode 100644 index 0000000000..3a13f9c0ba --- /dev/null +++ b/esp32p4/src/i2c0.rs @@ -0,0 +1,371 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + scl_low_period: SCL_LOW_PERIOD, + ctr: CTR, + sr: SR, + to: TO, + slave_addr: SLAVE_ADDR, + fifo_st: FIFO_ST, + fifo_conf: FIFO_CONF, + data: DATA, + int_raw: INT_RAW, + int_clr: INT_CLR, + int_ena: INT_ENA, + int_status: INT_STATUS, + sda_hold: SDA_HOLD, + sda_sample: SDA_SAMPLE, + scl_high_period: SCL_HIGH_PERIOD, + _reserved15: [u8; 0x04], + scl_start_hold: SCL_START_HOLD, + scl_rstart_setup: SCL_RSTART_SETUP, + scl_stop_hold: SCL_STOP_HOLD, + scl_stop_setup: SCL_STOP_SETUP, + filter_cfg: FILTER_CFG, + clk_conf: CLK_CONF, + comd0: COMD0, + comd1: COMD1, + comd2: COMD2, + comd3: COMD3, + comd4: COMD4, + comd5: COMD5, + comd6: COMD6, + comd7: COMD7, + scl_st_time_out: SCL_ST_TIME_OUT, + scl_main_st_time_out: SCL_MAIN_ST_TIME_OUT, + scl_sp_conf: SCL_SP_CONF, + scl_stretch_conf: SCL_STRETCH_CONF, + _reserved33: [u8; 0x70], + date: DATE, + _reserved34: [u8; 0x04], + txfifo_start_addr: TXFIFO_START_ADDR, + _reserved35: [u8; 0x7c], + rxfifo_start_addr: RXFIFO_START_ADDR, +} +impl RegisterBlock { + #[doc = "0x00 - Configures the low level width of the SCL Clock."] + #[inline(always)] + pub const fn scl_low_period(&self) -> &SCL_LOW_PERIOD { + &self.scl_low_period + } + #[doc = "0x04 - Transmission setting"] + #[inline(always)] + pub const fn ctr(&self) -> &CTR { + &self.ctr + } + #[doc = "0x08 - Describe I2C work status."] + #[inline(always)] + pub const fn sr(&self) -> &SR { + &self.sr + } + #[doc = "0x0c - Setting time out control for receiving data."] + #[inline(always)] + pub const fn to(&self) -> &TO { + &self.to + } + #[doc = "0x10 - Local slave address setting"] + #[inline(always)] + pub const fn slave_addr(&self) -> &SLAVE_ADDR { + &self.slave_addr + } + #[doc = "0x14 - FIFO status register."] + #[inline(always)] + pub const fn fifo_st(&self) -> &FIFO_ST { + &self.fifo_st + } + #[doc = "0x18 - FIFO configuration register."] + #[inline(always)] + pub const fn fifo_conf(&self) -> &FIFO_CONF { + &self.fifo_conf + } + #[doc = "0x1c - Rx FIFO read data."] + #[inline(always)] + pub const fn data(&self) -> &DATA { + &self.data + } + #[doc = "0x20 - Raw interrupt status"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x24 - Interrupt clear bits"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x28 - Interrupt enable bits"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x2c - Status of captured I2C communication events"] + #[inline(always)] + pub const fn int_status(&self) -> &INT_STATUS { + &self.int_status + } + #[doc = "0x30 - Configures the hold time after a negative SCL edge."] + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } + #[doc = "0x34 - Configures the sample time after a positive SCL edge."] + #[inline(always)] + pub const fn sda_sample(&self) -> &SDA_SAMPLE { + &self.sda_sample + } + #[doc = "0x38 - Configures the high level width of SCL"] + #[inline(always)] + pub const fn scl_high_period(&self) -> &SCL_HIGH_PERIOD { + &self.scl_high_period + } + #[doc = "0x40 - Configures the delay between the SDA and SCL negative edge for a start condition"] + #[inline(always)] + pub const fn scl_start_hold(&self) -> &SCL_START_HOLD { + &self.scl_start_hold + } + #[doc = "0x44 - Configures the delay between the positive edge of SCL and the negative edge of SDA"] + #[inline(always)] + pub const fn scl_rstart_setup(&self) -> &SCL_RSTART_SETUP { + &self.scl_rstart_setup + } + #[doc = "0x48 - Configures the delay after the SCL clock edge for a stop condition"] + #[inline(always)] + pub const fn scl_stop_hold(&self) -> &SCL_STOP_HOLD { + &self.scl_stop_hold + } + #[doc = "0x4c - Configures the delay between the SDA and SCL rising edge for a stop condition. Measurement unit: i2c_sclk"] + #[inline(always)] + pub const fn scl_stop_setup(&self) -> &SCL_STOP_SETUP { + &self.scl_stop_setup + } + #[doc = "0x50 - SCL and SDA filter configuration register"] + #[inline(always)] + pub const fn filter_cfg(&self) -> &FILTER_CFG { + &self.filter_cfg + } + #[doc = "0x54 - I2C CLK configuration register"] + #[inline(always)] + pub const fn clk_conf(&self) -> &CLK_CONF { + &self.clk_conf + } + #[doc = "0x58 - I2C command register 0"] + #[inline(always)] + pub const fn comd0(&self) -> &COMD0 { + &self.comd0 + } + #[doc = "0x5c - I2C command register 1"] + #[inline(always)] + pub const fn comd1(&self) -> &COMD1 { + &self.comd1 + } + #[doc = "0x60 - I2C command register 2"] + #[inline(always)] + pub const fn comd2(&self) -> &COMD2 { + &self.comd2 + } + #[doc = "0x64 - I2C command register 3"] + #[inline(always)] + pub const fn comd3(&self) -> &COMD3 { + &self.comd3 + } + #[doc = "0x68 - I2C command register 4"] + #[inline(always)] + pub const fn comd4(&self) -> &COMD4 { + &self.comd4 + } + #[doc = "0x6c - I2C command register 5"] + #[inline(always)] + pub const fn comd5(&self) -> &COMD5 { + &self.comd5 + } + #[doc = "0x70 - I2C command register 6"] + #[inline(always)] + pub const fn comd6(&self) -> &COMD6 { + &self.comd6 + } + #[doc = "0x74 - I2C command register 7"] + #[inline(always)] + pub const fn comd7(&self) -> &COMD7 { + &self.comd7 + } + #[doc = "0x78 - SCL status time out register"] + #[inline(always)] + pub const fn scl_st_time_out(&self) -> &SCL_ST_TIME_OUT { + &self.scl_st_time_out + } + #[doc = "0x7c - SCL main status time out register"] + #[inline(always)] + pub const fn scl_main_st_time_out(&self) -> &SCL_MAIN_ST_TIME_OUT { + &self.scl_main_st_time_out + } + #[doc = "0x80 - Power configuration register"] + #[inline(always)] + pub const fn scl_sp_conf(&self) -> &SCL_SP_CONF { + &self.scl_sp_conf + } + #[doc = "0x84 - Set SCL stretch of I2C slave"] + #[inline(always)] + pub const fn scl_stretch_conf(&self) -> &SCL_STRETCH_CONF { + &self.scl_stretch_conf + } + #[doc = "0xf8 - Version register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } + #[doc = "0x100 - I2C TXFIFO base address register"] + #[inline(always)] + pub const fn txfifo_start_addr(&self) -> &TXFIFO_START_ADDR { + &self.txfifo_start_addr + } + #[doc = "0x180 - I2C RXFIFO base address register"] + #[inline(always)] + pub const fn rxfifo_start_addr(&self) -> &RXFIFO_START_ADDR { + &self.rxfifo_start_addr + } +} +#[doc = "SCL_LOW_PERIOD (rw) register accessor: Configures the low level width of the SCL Clock.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_low_period::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_low_period::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_low_period`] module"] +pub type SCL_LOW_PERIOD = crate::Reg; +#[doc = "Configures the low level width of the SCL Clock."] +pub mod scl_low_period; +#[doc = "CTR (rw) register accessor: Transmission setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] +pub type CTR = crate::Reg; +#[doc = "Transmission setting"] +pub mod ctr; +#[doc = "SR (r) register accessor: Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"] +pub type SR = crate::Reg; +#[doc = "Describe I2C work status."] +pub mod sr; +#[doc = "TO (rw) register accessor: Setting time out control for receiving data.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`to::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`to::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@to`] module"] +pub type TO = crate::Reg; +#[doc = "Setting time out control for receiving data."] +pub mod to; +#[doc = "SLAVE_ADDR (rw) register accessor: Local slave address setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slave_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slave_addr`] module"] +pub type SLAVE_ADDR = crate::Reg; +#[doc = "Local slave address setting"] +pub mod slave_addr; +#[doc = "FIFO_ST (r) register accessor: FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_st`] module"] +pub type FIFO_ST = crate::Reg; +#[doc = "FIFO status register."] +pub mod fifo_st; +#[doc = "FIFO_CONF (rw) register accessor: FIFO configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_conf`] module"] +pub type FIFO_CONF = crate::Reg; +#[doc = "FIFO configuration register."] +pub mod fifo_conf; +#[doc = "DATA (r) register accessor: Rx FIFO read data.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +pub type DATA = crate::Reg; +#[doc = "Rx FIFO read data."] +pub mod data; +#[doc = "INT_RAW (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Raw interrupt status"] +pub mod int_raw; +#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear bits"] +pub mod int_clr; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable bits"] +pub mod int_ena; +#[doc = "INT_STATUS (r) register accessor: Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_status`] module"] +pub type INT_STATUS = crate::Reg; +#[doc = "Status of captured I2C communication events"] +pub mod int_status; +#[doc = "SDA_HOLD (rw) register accessor: Configures the hold time after a negative SCL edge.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] +pub type SDA_HOLD = crate::Reg; +#[doc = "Configures the hold time after a negative SCL edge."] +pub mod sda_hold; +#[doc = "SDA_SAMPLE (rw) register accessor: Configures the sample time after a positive SCL edge.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_sample::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_sample::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_sample`] module"] +pub type SDA_SAMPLE = crate::Reg; +#[doc = "Configures the sample time after a positive SCL edge."] +pub mod sda_sample; +#[doc = "SCL_HIGH_PERIOD (rw) register accessor: Configures the high level width of SCL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_high_period::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_high_period::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_high_period`] module"] +pub type SCL_HIGH_PERIOD = crate::Reg; +#[doc = "Configures the high level width of SCL"] +pub mod scl_high_period; +#[doc = "SCL_START_HOLD (rw) register accessor: Configures the delay between the SDA and SCL negative edge for a start condition\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_start_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_start_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_start_hold`] module"] +pub type SCL_START_HOLD = crate::Reg; +#[doc = "Configures the delay between the SDA and SCL negative edge for a start condition"] +pub mod scl_start_hold; +#[doc = "SCL_RSTART_SETUP (rw) register accessor: Configures the delay between the positive edge of SCL and the negative edge of SDA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_rstart_setup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_rstart_setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_rstart_setup`] module"] +pub type SCL_RSTART_SETUP = crate::Reg; +#[doc = "Configures the delay between the positive edge of SCL and the negative edge of SDA"] +pub mod scl_rstart_setup; +#[doc = "SCL_STOP_HOLD (rw) register accessor: Configures the delay after the SCL clock edge for a stop condition\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stop_hold`] module"] +pub type SCL_STOP_HOLD = crate::Reg; +#[doc = "Configures the delay after the SCL clock edge for a stop condition"] +pub mod scl_stop_hold; +#[doc = "SCL_STOP_SETUP (rw) register accessor: Configures the delay between the SDA and SCL rising edge for a stop condition. Measurement unit: i2c_sclk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_setup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stop_setup`] module"] +pub type SCL_STOP_SETUP = crate::Reg; +#[doc = "Configures the delay between the SDA and SCL rising edge for a stop condition. Measurement unit: i2c_sclk"] +pub mod scl_stop_setup; +#[doc = "FILTER_CFG (rw) register accessor: SCL and SDA filter configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_cfg`] module"] +pub type FILTER_CFG = crate::Reg; +#[doc = "SCL and SDA filter configuration register"] +pub mod filter_cfg; +#[doc = "CLK_CONF (rw) register accessor: I2C CLK configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"] +pub type CLK_CONF = crate::Reg; +#[doc = "I2C CLK configuration register"] +pub mod clk_conf; +#[doc = "COMD0 (rw) register accessor: I2C command register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd0`] module"] +pub type COMD0 = crate::Reg; +#[doc = "I2C command register 0"] +pub mod comd0; +#[doc = "COMD1 (rw) register accessor: I2C command register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd1`] module"] +pub type COMD1 = crate::Reg; +#[doc = "I2C command register 1"] +pub mod comd1; +#[doc = "COMD2 (rw) register accessor: I2C command register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd2`] module"] +pub type COMD2 = crate::Reg; +#[doc = "I2C command register 2"] +pub mod comd2; +#[doc = "COMD3 (rw) register accessor: I2C command register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd3`] module"] +pub type COMD3 = crate::Reg; +#[doc = "I2C command register 3"] +pub mod comd3; +#[doc = "COMD4 (rw) register accessor: I2C command register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd4`] module"] +pub type COMD4 = crate::Reg; +#[doc = "I2C command register 4"] +pub mod comd4; +#[doc = "COMD5 (rw) register accessor: I2C command register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd5`] module"] +pub type COMD5 = crate::Reg; +#[doc = "I2C command register 5"] +pub mod comd5; +#[doc = "COMD6 (rw) register accessor: I2C command register 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd6`] module"] +pub type COMD6 = crate::Reg; +#[doc = "I2C command register 6"] +pub mod comd6; +#[doc = "COMD7 (rw) register accessor: I2C command register 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd7`] module"] +pub type COMD7 = crate::Reg; +#[doc = "I2C command register 7"] +pub mod comd7; +#[doc = "SCL_ST_TIME_OUT (rw) register accessor: SCL status time out register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_st_time_out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_st_time_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_st_time_out`] module"] +pub type SCL_ST_TIME_OUT = crate::Reg; +#[doc = "SCL status time out register"] +pub mod scl_st_time_out; +#[doc = "SCL_MAIN_ST_TIME_OUT (rw) register accessor: SCL main status time out register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_main_st_time_out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_main_st_time_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_main_st_time_out`] module"] +pub type SCL_MAIN_ST_TIME_OUT = crate::Reg; +#[doc = "SCL main status time out register"] +pub mod scl_main_st_time_out; +#[doc = "SCL_SP_CONF (rw) register accessor: Power configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_sp_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_sp_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_sp_conf`] module"] +pub type SCL_SP_CONF = crate::Reg; +#[doc = "Power configuration register"] +pub mod scl_sp_conf; +#[doc = "SCL_STRETCH_CONF (rw) register accessor: Set SCL stretch of I2C slave\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stretch_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stretch_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stretch_conf`] module"] +pub type SCL_STRETCH_CONF = crate::Reg; +#[doc = "Set SCL stretch of I2C slave"] +pub mod scl_stretch_conf; +#[doc = "DATE (rw) register accessor: Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version register"] +pub mod date; +#[doc = "TXFIFO_START_ADDR (r) register accessor: I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifo_start_addr`] module"] +pub type TXFIFO_START_ADDR = crate::Reg; +#[doc = "I2C TXFIFO base address register"] +pub mod txfifo_start_addr; +#[doc = "RXFIFO_START_ADDR (r) register accessor: I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifo_start_addr`] module"] +pub type RXFIFO_START_ADDR = crate::Reg; +#[doc = "I2C RXFIFO base address register"] +pub mod rxfifo_start_addr; diff --git a/esp32p4/src/i2c0/clk_conf.rs b/esp32p4/src/i2c0/clk_conf.rs new file mode 100644 index 0000000000..3fdd0f77db --- /dev/null +++ b/esp32p4/src/i2c0/clk_conf.rs @@ -0,0 +1,130 @@ +#[doc = "Register `CLK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SCLK_DIV_NUM` reader - the integral part of the fractional divisor for i2c module"] +pub type SCLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_NUM` writer - the integral part of the fractional divisor for i2c module"] +pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SCLK_DIV_A` reader - the numerator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_A_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_A` writer - the numerator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_DIV_B` reader - the denominator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_B_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_B` writer - the denominator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_SEL` reader - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] +pub type SCLK_SEL_R = crate::BitReader; +#[doc = "Field `SCLK_SEL` writer - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] +pub type SCLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCLK_ACTIVE` reader - The clock switch for i2c module"] +pub type SCLK_ACTIVE_R = crate::BitReader; +#[doc = "Field `SCLK_ACTIVE` writer - The clock switch for i2c module"] +pub type SCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R { + SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_a(&self) -> SCLK_DIV_A_R { + SCLK_DIV_A_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_b(&self) -> SCLK_DIV_B_R { + SCLK_DIV_B_R::new(((self.bits >> 14) & 0x3f) as u8) + } + #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] + #[inline(always)] + pub fn sclk_sel(&self) -> SCLK_SEL_R { + SCLK_SEL_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The clock switch for i2c module"] + #[inline(always)] + pub fn sclk_active(&self) -> SCLK_ACTIVE_R { + SCLK_ACTIVE_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_CONF") + .field( + "sclk_div_num", + &format_args!("{}", self.sclk_div_num().bits()), + ) + .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits())) + .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits())) + .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit())) + .field("sclk_active", &format_args!("{}", self.sclk_active().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"] + #[inline(always)] + #[must_use] + pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W { + SCLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + #[must_use] + pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W { + SCLK_DIV_A_W::new(self, 8) + } + #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + #[must_use] + pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W { + SCLK_DIV_B_W::new(self, 14) + } + #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] + #[inline(always)] + #[must_use] + pub fn sclk_sel(&mut self) -> SCLK_SEL_W { + SCLK_SEL_W::new(self, 20) + } + #[doc = "Bit 21 - The clock switch for i2c module"] + #[inline(always)] + #[must_use] + pub fn sclk_active(&mut self) -> SCLK_ACTIVE_W { + SCLK_ACTIVE_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C CLK configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_CONF_SPEC; +impl crate::RegisterSpec for CLK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"] +impl crate::Readable for CLK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"] +impl crate::Writable for CLK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_CONF to value 0x0020_0000"] +impl crate::Resettable for CLK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0020_0000; +} diff --git a/esp32p4/src/i2c0/comd0.rs b/esp32p4/src/i2c0/comd0.rs new file mode 100644 index 0000000000..3946fa9327 --- /dev/null +++ b/esp32p4/src/i2c0/comd0.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD0` reader"] +pub type R = crate::R; +#[doc = "Register `COMD0` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND0` reader - Configures command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information."] +pub type COMMAND0_R = crate::FieldReader; +#[doc = "Field `COMMAND0` writer - Configures command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information."] +pub type COMMAND0_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND0_DONE` reader - Represents whether command 0 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND0_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND0_DONE` writer - Represents whether command 0 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND0_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information."] + #[inline(always)] + pub fn command0(&self) -> COMMAND0_R { + COMMAND0_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 0 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command0_done(&self) -> COMMAND0_DONE_R { + COMMAND0_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD0") + .field("command0", &format_args!("{}", self.command0().bits())) + .field( + "command0_done", + &format_args!("{}", self.command0_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information."] + #[inline(always)] + #[must_use] + pub fn command0(&mut self) -> COMMAND0_W { + COMMAND0_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 0 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command0_done(&mut self) -> COMMAND0_DONE_W { + COMMAND0_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD0_SPEC; +impl crate::RegisterSpec for COMD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd0::R`](R) reader structure"] +impl crate::Readable for COMD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd0::W`](W) writer structure"] +impl crate::Writable for COMD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD0 to value 0"] +impl crate::Resettable for COMD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/comd1.rs b/esp32p4/src/i2c0/comd1.rs new file mode 100644 index 0000000000..043bb212fc --- /dev/null +++ b/esp32p4/src/i2c0/comd1.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD1` reader"] +pub type R = crate::R; +#[doc = "Register `COMD1` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND1` reader - Configures command 1. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND1_R = crate::FieldReader; +#[doc = "Field `COMMAND1` writer - Configures command 1. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND1_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND1_DONE` reader - Represents whether command 1 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND1_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND1_DONE` writer - Represents whether command 1 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND1_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 1. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command1(&self) -> COMMAND1_R { + COMMAND1_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 1 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command1_done(&self) -> COMMAND1_DONE_R { + COMMAND1_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD1") + .field("command1", &format_args!("{}", self.command1().bits())) + .field( + "command1_done", + &format_args!("{}", self.command1_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 1. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command1(&mut self) -> COMMAND1_W { + COMMAND1_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 1 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command1_done(&mut self) -> COMMAND1_DONE_W { + COMMAND1_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD1_SPEC; +impl crate::RegisterSpec for COMD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd1::R`](R) reader structure"] +impl crate::Readable for COMD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd1::W`](W) writer structure"] +impl crate::Writable for COMD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD1 to value 0"] +impl crate::Resettable for COMD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/comd2.rs b/esp32p4/src/i2c0/comd2.rs new file mode 100644 index 0000000000..eac951a0aa --- /dev/null +++ b/esp32p4/src/i2c0/comd2.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD2` reader"] +pub type R = crate::R; +#[doc = "Register `COMD2` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND2` reader - Configures command 2. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND2_R = crate::FieldReader; +#[doc = "Field `COMMAND2` writer - Configures command 2. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND2_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND2_DONE` reader - Represents whether command 2 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND2_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND2_DONE` writer - Represents whether command 2 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND2_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 2. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command2(&self) -> COMMAND2_R { + COMMAND2_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 2 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command2_done(&self) -> COMMAND2_DONE_R { + COMMAND2_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD2") + .field("command2", &format_args!("{}", self.command2().bits())) + .field( + "command2_done", + &format_args!("{}", self.command2_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 2. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command2(&mut self) -> COMMAND2_W { + COMMAND2_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 2 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command2_done(&mut self) -> COMMAND2_DONE_W { + COMMAND2_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD2_SPEC; +impl crate::RegisterSpec for COMD2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd2::R`](R) reader structure"] +impl crate::Readable for COMD2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd2::W`](W) writer structure"] +impl crate::Writable for COMD2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD2 to value 0"] +impl crate::Resettable for COMD2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/comd3.rs b/esp32p4/src/i2c0/comd3.rs new file mode 100644 index 0000000000..067c57abc0 --- /dev/null +++ b/esp32p4/src/i2c0/comd3.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD3` reader"] +pub type R = crate::R; +#[doc = "Register `COMD3` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND3` reader - Configures command 3. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND3_R = crate::FieldReader; +#[doc = "Field `COMMAND3` writer - Configures command 3. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND3_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND3_DONE` reader - Represents whether command 3 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND3_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND3_DONE` writer - Represents whether command 3 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND3_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 3. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command3(&self) -> COMMAND3_R { + COMMAND3_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 3 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command3_done(&self) -> COMMAND3_DONE_R { + COMMAND3_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD3") + .field("command3", &format_args!("{}", self.command3().bits())) + .field( + "command3_done", + &format_args!("{}", self.command3_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 3. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command3(&mut self) -> COMMAND3_W { + COMMAND3_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 3 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command3_done(&mut self) -> COMMAND3_DONE_W { + COMMAND3_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD3_SPEC; +impl crate::RegisterSpec for COMD3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd3::R`](R) reader structure"] +impl crate::Readable for COMD3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd3::W`](W) writer structure"] +impl crate::Writable for COMD3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD3 to value 0"] +impl crate::Resettable for COMD3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/comd4.rs b/esp32p4/src/i2c0/comd4.rs new file mode 100644 index 0000000000..1a095d781d --- /dev/null +++ b/esp32p4/src/i2c0/comd4.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD4` reader"] +pub type R = crate::R; +#[doc = "Register `COMD4` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND4` reader - Configures command 4. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND4_R = crate::FieldReader; +#[doc = "Field `COMMAND4` writer - Configures command 4. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND4_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND4_DONE` reader - Represents whether command 4 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND4_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND4_DONE` writer - Represents whether command 4 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND4_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 4. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command4(&self) -> COMMAND4_R { + COMMAND4_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 4 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command4_done(&self) -> COMMAND4_DONE_R { + COMMAND4_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD4") + .field("command4", &format_args!("{}", self.command4().bits())) + .field( + "command4_done", + &format_args!("{}", self.command4_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 4. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command4(&mut self) -> COMMAND4_W { + COMMAND4_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 4 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command4_done(&mut self) -> COMMAND4_DONE_W { + COMMAND4_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD4_SPEC; +impl crate::RegisterSpec for COMD4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd4::R`](R) reader structure"] +impl crate::Readable for COMD4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd4::W`](W) writer structure"] +impl crate::Writable for COMD4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD4 to value 0"] +impl crate::Resettable for COMD4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/comd5.rs b/esp32p4/src/i2c0/comd5.rs new file mode 100644 index 0000000000..62e79ca266 --- /dev/null +++ b/esp32p4/src/i2c0/comd5.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD5` reader"] +pub type R = crate::R; +#[doc = "Register `COMD5` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND5` reader - Configures command 5. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND5_R = crate::FieldReader; +#[doc = "Field `COMMAND5` writer - Configures command 5. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND5_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND5_DONE` reader - Represents whether command 5 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND5_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND5_DONE` writer - Represents whether command 5 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND5_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 5. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command5(&self) -> COMMAND5_R { + COMMAND5_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 5 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command5_done(&self) -> COMMAND5_DONE_R { + COMMAND5_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD5") + .field("command5", &format_args!("{}", self.command5().bits())) + .field( + "command5_done", + &format_args!("{}", self.command5_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 5. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command5(&mut self) -> COMMAND5_W { + COMMAND5_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 5 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command5_done(&mut self) -> COMMAND5_DONE_W { + COMMAND5_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD5_SPEC; +impl crate::RegisterSpec for COMD5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd5::R`](R) reader structure"] +impl crate::Readable for COMD5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd5::W`](W) writer structure"] +impl crate::Writable for COMD5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD5 to value 0"] +impl crate::Resettable for COMD5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/comd6.rs b/esp32p4/src/i2c0/comd6.rs new file mode 100644 index 0000000000..d9cd7d39ab --- /dev/null +++ b/esp32p4/src/i2c0/comd6.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD6` reader"] +pub type R = crate::R; +#[doc = "Register `COMD6` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND6` reader - Configures command 6. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND6_R = crate::FieldReader; +#[doc = "Field `COMMAND6` writer - Configures command 6. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND6_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND6_DONE` reader - Represents whether command 6 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND6_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND6_DONE` writer - Represents whether command 6 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND6_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 6. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command6(&self) -> COMMAND6_R { + COMMAND6_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 6 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command6_done(&self) -> COMMAND6_DONE_R { + COMMAND6_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD6") + .field("command6", &format_args!("{}", self.command6().bits())) + .field( + "command6_done", + &format_args!("{}", self.command6_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 6. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command6(&mut self) -> COMMAND6_W { + COMMAND6_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 6 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command6_done(&mut self) -> COMMAND6_DONE_W { + COMMAND6_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD6_SPEC; +impl crate::RegisterSpec for COMD6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd6::R`](R) reader structure"] +impl crate::Readable for COMD6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd6::W`](W) writer structure"] +impl crate::Writable for COMD6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD6 to value 0"] +impl crate::Resettable for COMD6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/comd7.rs b/esp32p4/src/i2c0/comd7.rs new file mode 100644 index 0000000000..5f80ce68c2 --- /dev/null +++ b/esp32p4/src/i2c0/comd7.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD7` reader"] +pub type R = crate::R; +#[doc = "Register `COMD7` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND7` reader - Configures command 7. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND7_R = crate::FieldReader; +#[doc = "Field `COMMAND7` writer - Configures command 7. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND7_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND7_DONE` reader - Represents whether command 7 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND7_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND7_DONE` writer - Represents whether command 7 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND7_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 7. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command7(&self) -> COMMAND7_R { + COMMAND7_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 7 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command7_done(&self) -> COMMAND7_DONE_R { + COMMAND7_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD7") + .field("command7", &format_args!("{}", self.command7().bits())) + .field( + "command7_done", + &format_args!("{}", self.command7_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 7. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command7(&mut self) -> COMMAND7_W { + COMMAND7_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 7 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command7_done(&mut self) -> COMMAND7_DONE_W { + COMMAND7_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD7_SPEC; +impl crate::RegisterSpec for COMD7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd7::R`](R) reader structure"] +impl crate::Readable for COMD7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd7::W`](W) writer structure"] +impl crate::Writable for COMD7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD7 to value 0"] +impl crate::Resettable for COMD7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/ctr.rs b/esp32p4/src/i2c0/ctr.rs new file mode 100644 index 0000000000..bf48f4a953 --- /dev/null +++ b/esp32p4/src/i2c0/ctr.rs @@ -0,0 +1,293 @@ +#[doc = "Register `CTR` reader"] +pub type R = crate::R; +#[doc = "Register `CTR` writer"] +pub type W = crate::W; +#[doc = "Field `SDA_FORCE_OUT` reader - Configures the SDA output mode 1: Direct output, 0: Open drain output."] +pub type SDA_FORCE_OUT_R = crate::BitReader; +#[doc = "Field `SDA_FORCE_OUT` writer - Configures the SDA output mode 1: Direct output, 0: Open drain output."] +pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_FORCE_OUT` reader - Configures the SCL output mode 1: Direct output, 0: Open drain output."] +pub type SCL_FORCE_OUT_R = crate::BitReader; +#[doc = "Field `SCL_FORCE_OUT` writer - Configures the SCL output mode 1: Direct output, 0: Open drain output."] +pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAMPLE_SCL_LEVEL` reader - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."] +pub type SAMPLE_SCL_LEVEL_R = crate::BitReader; +#[doc = "Field `SAMPLE_SCL_LEVEL` writer - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."] +pub type SAMPLE_SCL_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FULL_ACK_LEVEL` reader - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."] +pub type RX_FULL_ACK_LEVEL_R = crate::BitReader; +#[doc = "Field `RX_FULL_ACK_LEVEL` writer - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."] +pub type RX_FULL_ACK_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MS_MODE` reader - Configures the module as an I2C Master or Slave. 0: Slave 1: Master"] +pub type MS_MODE_R = crate::BitReader; +#[doc = "Field `MS_MODE` writer - Configures the module as an I2C Master or Slave. 0: Slave 1: Master"] +pub type MS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_START` writer - Configures to start sending the data in txfifo for slave. 0: No effect 1: Start"] +pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_LSB_FIRST` reader - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."] +pub type TX_LSB_FIRST_R = crate::BitReader; +#[doc = "Field `TX_LSB_FIRST` writer - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."] +pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_LSB_FIRST` reader - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."] +pub type RX_LSB_FIRST_R = crate::BitReader; +#[doc = "Field `RX_LSB_FIRST` writer - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."] +pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBITRATION_EN` reader - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"] +pub type ARBITRATION_EN_R = crate::BitReader; +#[doc = "Field `ARBITRATION_EN` writer - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"] +pub type ARBITRATION_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FSM_RST` writer - Configures to reset the SCL_FSM. 0: No effect 1: Reset"] +pub type FSM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CONF_UPGATE` writer - Configures this bit for synchronization 0: No effect 1: Synchronize"] +pub type CONF_UPGATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLV_TX_AUTO_START_EN` reader - Configures to enable slave to send data automatically 0: Disable 1: Enable"] +pub type SLV_TX_AUTO_START_EN_R = crate::BitReader; +#[doc = "Field `SLV_TX_AUTO_START_EN` writer - Configures to enable slave to send data automatically 0: Disable 1: Enable"] +pub type SLV_TX_AUTO_START_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDR_10BIT_RW_CHECK_EN` reader - Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. 0: Not check 1: Check"] +pub type ADDR_10BIT_RW_CHECK_EN_R = crate::BitReader; +#[doc = "Field `ADDR_10BIT_RW_CHECK_EN` writer - Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. 0: Not check 1: Check"] +pub type ADDR_10BIT_RW_CHECK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDR_BROADCASTING_EN` reader - Configures to support the 7bit general call function. 0: Not support 1: Support"] +pub type ADDR_BROADCASTING_EN_R = crate::BitReader; +#[doc = "Field `ADDR_BROADCASTING_EN` writer - Configures to support the 7bit general call function. 0: Not support 1: Support"] +pub type ADDR_BROADCASTING_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures the SDA output mode 1: Direct output, 0: Open drain output."] + #[inline(always)] + pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R { + SDA_FORCE_OUT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures the SCL output mode 1: Direct output, 0: Open drain output."] + #[inline(always)] + pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R { + SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."] + #[inline(always)] + pub fn sample_scl_level(&self) -> SAMPLE_SCL_LEVEL_R { + SAMPLE_SCL_LEVEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."] + #[inline(always)] + pub fn rx_full_ack_level(&self) -> RX_FULL_ACK_LEVEL_R { + RX_FULL_ACK_LEVEL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures the module as an I2C Master or Slave. 0: Slave 1: Master"] + #[inline(always)] + pub fn ms_mode(&self) -> MS_MODE_R { + MS_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."] + #[inline(always)] + pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R { + TX_LSB_FIRST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."] + #[inline(always)] + pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R { + RX_LSB_FIRST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"] + #[inline(always)] + pub fn arbitration_en(&self) -> ARBITRATION_EN_R { + ARBITRATION_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - Configures to enable slave to send data automatically 0: Disable 1: Enable"] + #[inline(always)] + pub fn slv_tx_auto_start_en(&self) -> SLV_TX_AUTO_START_EN_R { + SLV_TX_AUTO_START_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. 0: Not check 1: Check"] + #[inline(always)] + pub fn addr_10bit_rw_check_en(&self) -> ADDR_10BIT_RW_CHECK_EN_R { + ADDR_10BIT_RW_CHECK_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Configures to support the 7bit general call function. 0: Not support 1: Support"] + #[inline(always)] + pub fn addr_broadcasting_en(&self) -> ADDR_BROADCASTING_EN_R { + ADDR_BROADCASTING_EN_R::new(((self.bits >> 14) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTR") + .field( + "sda_force_out", + &format_args!("{}", self.sda_force_out().bit()), + ) + .field( + "scl_force_out", + &format_args!("{}", self.scl_force_out().bit()), + ) + .field( + "sample_scl_level", + &format_args!("{}", self.sample_scl_level().bit()), + ) + .field( + "rx_full_ack_level", + &format_args!("{}", self.rx_full_ack_level().bit()), + ) + .field("ms_mode", &format_args!("{}", self.ms_mode().bit())) + .field( + "tx_lsb_first", + &format_args!("{}", self.tx_lsb_first().bit()), + ) + .field( + "rx_lsb_first", + &format_args!("{}", self.rx_lsb_first().bit()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field( + "arbitration_en", + &format_args!("{}", self.arbitration_en().bit()), + ) + .field( + "slv_tx_auto_start_en", + &format_args!("{}", self.slv_tx_auto_start_en().bit()), + ) + .field( + "addr_10bit_rw_check_en", + &format_args!("{}", self.addr_10bit_rw_check_en().bit()), + ) + .field( + "addr_broadcasting_en", + &format_args!("{}", self.addr_broadcasting_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures the SDA output mode 1: Direct output, 0: Open drain output."] + #[inline(always)] + #[must_use] + pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W { + SDA_FORCE_OUT_W::new(self, 0) + } + #[doc = "Bit 1 - Configures the SCL output mode 1: Direct output, 0: Open drain output."] + #[inline(always)] + #[must_use] + pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W { + SCL_FORCE_OUT_W::new(self, 1) + } + #[doc = "Bit 2 - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."] + #[inline(always)] + #[must_use] + pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W { + SAMPLE_SCL_LEVEL_W::new(self, 2) + } + #[doc = "Bit 3 - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."] + #[inline(always)] + #[must_use] + pub fn rx_full_ack_level(&mut self) -> RX_FULL_ACK_LEVEL_W { + RX_FULL_ACK_LEVEL_W::new(self, 3) + } + #[doc = "Bit 4 - Configures the module as an I2C Master or Slave. 0: Slave 1: Master"] + #[inline(always)] + #[must_use] + pub fn ms_mode(&mut self) -> MS_MODE_W { + MS_MODE_W::new(self, 4) + } + #[doc = "Bit 5 - Configures to start sending the data in txfifo for slave. 0: No effect 1: Start"] + #[inline(always)] + #[must_use] + pub fn trans_start(&mut self) -> TRANS_START_W { + TRANS_START_W::new(self, 5) + } + #[doc = "Bit 6 - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."] + #[inline(always)] + #[must_use] + pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W { + TX_LSB_FIRST_W::new(self, 6) + } + #[doc = "Bit 7 - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."] + #[inline(always)] + #[must_use] + pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W { + RX_LSB_FIRST_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"] + #[inline(always)] + #[must_use] + pub fn arbitration_en(&mut self) -> ARBITRATION_EN_W { + ARBITRATION_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Configures to reset the SCL_FSM. 0: No effect 1: Reset"] + #[inline(always)] + #[must_use] + pub fn fsm_rst(&mut self) -> FSM_RST_W { + FSM_RST_W::new(self, 10) + } + #[doc = "Bit 11 - Configures this bit for synchronization 0: No effect 1: Synchronize"] + #[inline(always)] + #[must_use] + pub fn conf_upgate(&mut self) -> CONF_UPGATE_W { + CONF_UPGATE_W::new(self, 11) + } + #[doc = "Bit 12 - Configures to enable slave to send data automatically 0: Disable 1: Enable"] + #[inline(always)] + #[must_use] + pub fn slv_tx_auto_start_en(&mut self) -> SLV_TX_AUTO_START_EN_W { + SLV_TX_AUTO_START_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. 0: Not check 1: Check"] + #[inline(always)] + #[must_use] + pub fn addr_10bit_rw_check_en(&mut self) -> ADDR_10BIT_RW_CHECK_EN_W { + ADDR_10BIT_RW_CHECK_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Configures to support the 7bit general call function. 0: Not support 1: Support"] + #[inline(always)] + #[must_use] + pub fn addr_broadcasting_en(&mut self) -> ADDR_BROADCASTING_EN_W { + ADDR_BROADCASTING_EN_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Transmission setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTR_SPEC; +impl crate::RegisterSpec for CTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctr::R`](R) reader structure"] +impl crate::Readable for CTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"] +impl crate::Writable for CTR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTR to value 0x0208"] +impl crate::Resettable for CTR_SPEC { + const RESET_VALUE: Self::Ux = 0x0208; +} diff --git a/esp32p4/src/i2c0/data.rs b/esp32p4/src/i2c0/data.rs new file mode 100644 index 0000000000..f3bab00b70 --- /dev/null +++ b/esp32p4/src/i2c0/data.rs @@ -0,0 +1,36 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_RDATA` reader - Represents the value of RXFIFO read data."] +pub type FIFO_RDATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Represents the value of RXFIFO read data."] + #[inline(always)] + pub fn fifo_rdata(&self) -> FIFO_RDATA_R { + FIFO_RDATA_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA") + .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Rx FIFO read data.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DATA_SPEC {} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/date.rs b/esp32p4/src/i2c0/date.rs new file mode 100644 index 0000000000..b364444879 --- /dev/null +++ b/esp32p4/src/i2c0/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - Version control register."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - Version control register."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Version control register."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Version control register."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0220_1172"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_1172; +} diff --git a/esp32p4/src/i2c0/fifo_conf.rs b/esp32p4/src/i2c0/fifo_conf.rs new file mode 100644 index 0000000000..37b0edc7ba --- /dev/null +++ b/esp32p4/src/i2c0/fifo_conf.rs @@ -0,0 +1,168 @@ +#[doc = "Register `FIFO_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_WM_THRHD` reader - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[4:0\\], reg_rxfifo_wm_int_raw bit will be valid."] +pub type RXFIFO_WM_THRHD_R = crate::FieldReader; +#[doc = "Field `RXFIFO_WM_THRHD` writer - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[4:0\\], reg_rxfifo_wm_int_raw bit will be valid."] +pub type RXFIFO_WM_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `TXFIFO_WM_THRHD` reader - Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[4:0\\], reg_txfifo_wm_int_raw bit will be valid."] +pub type TXFIFO_WM_THRHD_R = crate::FieldReader; +#[doc = "Field `TXFIFO_WM_THRHD` writer - Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[4:0\\], reg_txfifo_wm_int_raw bit will be valid."] +pub type TXFIFO_WM_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `NONFIFO_EN` reader - Configures to enable APB nonfifo access."] +pub type NONFIFO_EN_R = crate::BitReader; +#[doc = "Field `NONFIFO_EN` writer - Configures to enable APB nonfifo access."] +pub type NONFIFO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_ADDR_CFG_EN` reader - Configures to enable double addressing mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. 0: Disable 1: Enable"] +pub type FIFO_ADDR_CFG_EN_R = crate::BitReader; +#[doc = "Field `FIFO_ADDR_CFG_EN` writer - Configures to enable double addressing mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. 0: Disable 1: Enable"] +pub type FIFO_ADDR_CFG_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFO_RST` reader - Configures to reset RXFIFO. 0: No effect 1: Reset"] +pub type RX_FIFO_RST_R = crate::BitReader; +#[doc = "Field `RX_FIFO_RST` writer - Configures to reset RXFIFO. 0: No effect 1: Reset"] +pub type RX_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_FIFO_RST` reader - Configures to reset TXFIFO. 0: No effect 1: Reset"] +pub type TX_FIFO_RST_R = crate::BitReader; +#[doc = "Field `TX_FIFO_RST` writer - Configures to reset TXFIFO. 0: No effect 1: Reset"] +pub type TX_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_PRT_EN` reader - Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. 0: No effect 1: Enable"] +pub type FIFO_PRT_EN_R = crate::BitReader; +#[doc = "Field `FIFO_PRT_EN` writer - Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. 0: No effect 1: Enable"] +pub type FIFO_PRT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[4:0\\], reg_rxfifo_wm_int_raw bit will be valid."] + #[inline(always)] + pub fn rxfifo_wm_thrhd(&self) -> RXFIFO_WM_THRHD_R { + RXFIFO_WM_THRHD_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[4:0\\], reg_txfifo_wm_int_raw bit will be valid."] + #[inline(always)] + pub fn txfifo_wm_thrhd(&self) -> TXFIFO_WM_THRHD_R { + TXFIFO_WM_THRHD_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bit 10 - Configures to enable APB nonfifo access."] + #[inline(always)] + pub fn nonfifo_en(&self) -> NONFIFO_EN_R { + NONFIFO_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Configures to enable double addressing mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. 0: Disable 1: Enable"] + #[inline(always)] + pub fn fifo_addr_cfg_en(&self) -> FIFO_ADDR_CFG_EN_R { + FIFO_ADDR_CFG_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Configures to reset RXFIFO. 0: No effect 1: Reset"] + #[inline(always)] + pub fn rx_fifo_rst(&self) -> RX_FIFO_RST_R { + RX_FIFO_RST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures to reset TXFIFO. 0: No effect 1: Reset"] + #[inline(always)] + pub fn tx_fifo_rst(&self) -> TX_FIFO_RST_R { + TX_FIFO_RST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. 0: No effect 1: Enable"] + #[inline(always)] + pub fn fifo_prt_en(&self) -> FIFO_PRT_EN_R { + FIFO_PRT_EN_R::new(((self.bits >> 14) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO_CONF") + .field( + "rxfifo_wm_thrhd", + &format_args!("{}", self.rxfifo_wm_thrhd().bits()), + ) + .field( + "txfifo_wm_thrhd", + &format_args!("{}", self.txfifo_wm_thrhd().bits()), + ) + .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit())) + .field( + "fifo_addr_cfg_en", + &format_args!("{}", self.fifo_addr_cfg_en().bit()), + ) + .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit())) + .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit())) + .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[4:0\\], reg_rxfifo_wm_int_raw bit will be valid."] + #[inline(always)] + #[must_use] + pub fn rxfifo_wm_thrhd(&mut self) -> RXFIFO_WM_THRHD_W { + RXFIFO_WM_THRHD_W::new(self, 0) + } + #[doc = "Bits 5:9 - Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[4:0\\], reg_txfifo_wm_int_raw bit will be valid."] + #[inline(always)] + #[must_use] + pub fn txfifo_wm_thrhd(&mut self) -> TXFIFO_WM_THRHD_W { + TXFIFO_WM_THRHD_W::new(self, 5) + } + #[doc = "Bit 10 - Configures to enable APB nonfifo access."] + #[inline(always)] + #[must_use] + pub fn nonfifo_en(&mut self) -> NONFIFO_EN_W { + NONFIFO_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Configures to enable double addressing mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. 0: Disable 1: Enable"] + #[inline(always)] + #[must_use] + pub fn fifo_addr_cfg_en(&mut self) -> FIFO_ADDR_CFG_EN_W { + FIFO_ADDR_CFG_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Configures to reset RXFIFO. 0: No effect 1: Reset"] + #[inline(always)] + #[must_use] + pub fn rx_fifo_rst(&mut self) -> RX_FIFO_RST_W { + RX_FIFO_RST_W::new(self, 12) + } + #[doc = "Bit 13 - Configures to reset TXFIFO. 0: No effect 1: Reset"] + #[inline(always)] + #[must_use] + pub fn tx_fifo_rst(&mut self) -> TX_FIFO_RST_W { + TX_FIFO_RST_W::new(self, 13) + } + #[doc = "Bit 14 - Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. 0: No effect 1: Enable"] + #[inline(always)] + #[must_use] + pub fn fifo_prt_en(&mut self) -> FIFO_PRT_EN_W { + FIFO_PRT_EN_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "FIFO configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_CONF_SPEC; +impl crate::RegisterSpec for FIFO_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_conf::R`](R) reader structure"] +impl crate::Readable for FIFO_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo_conf::W`](W) writer structure"] +impl crate::Writable for FIFO_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIFO_CONF to value 0x408b"] +impl crate::Resettable for FIFO_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x408b; +} diff --git a/esp32p4/src/i2c0/fifo_st.rs b/esp32p4/src/i2c0/fifo_st.rs new file mode 100644 index 0000000000..55a8821779 --- /dev/null +++ b/esp32p4/src/i2c0/fifo_st.rs @@ -0,0 +1,83 @@ +#[doc = "Register `FIFO_ST` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_RADDR` reader - Represents the offset address of the APB reading from RXFIFO"] +pub type RXFIFO_RADDR_R = crate::FieldReader; +#[doc = "Field `RXFIFO_WADDR` reader - Represents the offset address of i2c module receiving data and writing to RXFIFO."] +pub type RXFIFO_WADDR_R = crate::FieldReader; +#[doc = "Field `TXFIFO_RADDR` reader - Represents the offset address of i2c module reading from TXFIFO."] +pub type TXFIFO_RADDR_R = crate::FieldReader; +#[doc = "Field `TXFIFO_WADDR` reader - Represents the offset address of APB bus writing to TXFIFO."] +pub type TXFIFO_WADDR_R = crate::FieldReader; +#[doc = "Field `SLAVE_RW_POINT` reader - Represents the offset address in the I2C Slave RAM addressed by I2C Master when in I2C slave mode."] +pub type SLAVE_RW_POINT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - Represents the offset address of the APB reading from RXFIFO"] + #[inline(always)] + pub fn rxfifo_raddr(&self) -> RXFIFO_RADDR_R { + RXFIFO_RADDR_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - Represents the offset address of i2c module receiving data and writing to RXFIFO."] + #[inline(always)] + pub fn rxfifo_waddr(&self) -> RXFIFO_WADDR_R { + RXFIFO_WADDR_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - Represents the offset address of i2c module reading from TXFIFO."] + #[inline(always)] + pub fn txfifo_raddr(&self) -> TXFIFO_RADDR_R { + TXFIFO_RADDR_R::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bits 15:19 - Represents the offset address of APB bus writing to TXFIFO."] + #[inline(always)] + pub fn txfifo_waddr(&self) -> TXFIFO_WADDR_R { + TXFIFO_WADDR_R::new(((self.bits >> 15) & 0x1f) as u8) + } + #[doc = "Bits 22:29 - Represents the offset address in the I2C Slave RAM addressed by I2C Master when in I2C slave mode."] + #[inline(always)] + pub fn slave_rw_point(&self) -> SLAVE_RW_POINT_R { + SLAVE_RW_POINT_R::new(((self.bits >> 22) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO_ST") + .field( + "rxfifo_raddr", + &format_args!("{}", self.rxfifo_raddr().bits()), + ) + .field( + "rxfifo_waddr", + &format_args!("{}", self.rxfifo_waddr().bits()), + ) + .field( + "txfifo_raddr", + &format_args!("{}", self.txfifo_raddr().bits()), + ) + .field( + "txfifo_waddr", + &format_args!("{}", self.txfifo_waddr().bits()), + ) + .field( + "slave_rw_point", + &format_args!("{}", self.slave_rw_point().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_ST_SPEC; +impl crate::RegisterSpec for FIFO_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_st::R`](R) reader structure"] +impl crate::Readable for FIFO_ST_SPEC {} +#[doc = "`reset()` method sets FIFO_ST to value 0"] +impl crate::Resettable for FIFO_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/filter_cfg.rs b/esp32p4/src/i2c0/filter_cfg.rs new file mode 100644 index 0000000000..6a9d0e9d0d --- /dev/null +++ b/esp32p4/src/i2c0/filter_cfg.rs @@ -0,0 +1,123 @@ +#[doc = "Register `FILTER_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FILTER_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_FILTER_THRES` reader - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] +pub type SCL_FILTER_THRES_R = crate::FieldReader; +#[doc = "Field `SCL_FILTER_THRES` writer - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] +pub type SCL_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SDA_FILTER_THRES` reader - Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] +pub type SDA_FILTER_THRES_R = crate::FieldReader; +#[doc = "Field `SDA_FILTER_THRES` writer - Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] +pub type SDA_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SCL_FILTER_EN` reader - Configures to enable the filter function for SCL."] +pub type SCL_FILTER_EN_R = crate::BitReader; +#[doc = "Field `SCL_FILTER_EN` writer - Configures to enable the filter function for SCL."] +pub type SCL_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDA_FILTER_EN` reader - Configures to enable the filter function for SDA."] +pub type SDA_FILTER_EN_R = crate::BitReader; +#[doc = "Field `SDA_FILTER_EN` writer - Configures to enable the filter function for SDA."] +pub type SDA_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_filter_thres(&self) -> SCL_FILTER_THRES_R { + SCL_FILTER_THRES_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn sda_filter_thres(&self) -> SDA_FILTER_THRES_R { + SDA_FILTER_THRES_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8 - Configures to enable the filter function for SCL."] + #[inline(always)] + pub fn scl_filter_en(&self) -> SCL_FILTER_EN_R { + SCL_FILTER_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures to enable the filter function for SDA."] + #[inline(always)] + pub fn sda_filter_en(&self) -> SDA_FILTER_EN_R { + SDA_FILTER_EN_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FILTER_CFG") + .field( + "scl_filter_thres", + &format_args!("{}", self.scl_filter_thres().bits()), + ) + .field( + "sda_filter_thres", + &format_args!("{}", self.sda_filter_thres().bits()), + ) + .field( + "scl_filter_en", + &format_args!("{}", self.scl_filter_en().bit()), + ) + .field( + "sda_filter_en", + &format_args!("{}", self.sda_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_filter_thres(&mut self) -> SCL_FILTER_THRES_W { + SCL_FILTER_THRES_W::new(self, 0) + } + #[doc = "Bits 4:7 - Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn sda_filter_thres(&mut self) -> SDA_FILTER_THRES_W { + SDA_FILTER_THRES_W::new(self, 4) + } + #[doc = "Bit 8 - Configures to enable the filter function for SCL."] + #[inline(always)] + #[must_use] + pub fn scl_filter_en(&mut self) -> SCL_FILTER_EN_W { + SCL_FILTER_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Configures to enable the filter function for SDA."] + #[inline(always)] + #[must_use] + pub fn sda_filter_en(&mut self) -> SDA_FILTER_EN_W { + SDA_FILTER_EN_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SCL and SDA filter configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FILTER_CFG_SPEC; +impl crate::RegisterSpec for FILTER_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`filter_cfg::R`](R) reader structure"] +impl crate::Readable for FILTER_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`filter_cfg::W`](W) writer structure"] +impl crate::Writable for FILTER_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FILTER_CFG to value 0x0300"] +impl crate::Resettable for FILTER_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0300; +} diff --git a/esp32p4/src/i2c0/int_clr.rs b/esp32p4/src/i2c0/int_clr.rs new file mode 100644 index 0000000000..06d7d12376 --- /dev/null +++ b/esp32p4/src/i2c0/int_clr.rs @@ -0,0 +1,186 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_WM_INT_CLR` writer - Write 1 to clear I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_WM_INT_CLR` writer - Write 1 to clear I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF_INT_CLR` writer - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `END_DETECT_INT_CLR` writer - Write 1 to clear the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BYTE_TRANS_DONE_INT_CLR` writer - Write 1 to clear the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBITRATION_LOST_INT_CLR` writer - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MST_TXFIFO_UDF_INT_CLR` writer - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_COMPLETE_INT_CLR` writer - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIME_OUT_INT_CLR` writer - Write 1 to clear the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_START_INT_CLR` writer - Write 1 to clear the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACK_INT_CLR` writer - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_OVF_INT_CLR` writer - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_UDF_INT_CLR` writer - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_ST_TO_INT_CLR` writer - Write 1 to clear I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_MAIN_ST_TO_INT_CLR` writer - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DET_START_INT_CLR` writer - Write 1 to clear I2C_DET_START_INT interrupt."] +pub type DET_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLAVE_STRETCH_INT_CLR` writer - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."] +pub type SLAVE_STRETCH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GENERAL_CALL_INT_CLR` writer - Write 1 to clear I2C_GENARAL_CALL_INT interrupt."] +pub type GENERAL_CALL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLAVE_ADDR_UNMATCH_INT_CLR` writer - Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt."] +pub type SLAVE_ADDR_UNMATCH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to clear I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_wm_int_clr(&mut self) -> RXFIFO_WM_INT_CLR_W { + RXFIFO_WM_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to clear I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn txfifo_wm_int_clr(&mut self) -> TXFIFO_WM_INT_CLR_W { + TXFIFO_WM_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_ovf_int_clr(&mut self) -> RXFIFO_OVF_INT_CLR_W { + RXFIFO_OVF_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to clear the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn end_detect_int_clr(&mut self) -> END_DETECT_INT_CLR_W { + END_DETECT_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to clear the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn byte_trans_done_int_clr(&mut self) -> BYTE_TRANS_DONE_INT_CLR_W { + BYTE_TRANS_DONE_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn arbitration_lost_int_clr(&mut self) -> ARBITRATION_LOST_INT_CLR_W { + ARBITRATION_LOST_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn mst_txfifo_udf_int_clr(&mut self) -> MST_TXFIFO_UDF_INT_CLR_W { + MST_TXFIFO_UDF_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn trans_complete_int_clr(&mut self) -> TRANS_COMPLETE_INT_CLR_W { + TRANS_COMPLETE_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Write 1 to clear the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn time_out_int_clr(&mut self) -> TIME_OUT_INT_CLR_W { + TIME_OUT_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Write 1 to clear the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn trans_start_int_clr(&mut self) -> TRANS_START_INT_CLR_W { + TRANS_START_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn nack_int_clr(&mut self) -> NACK_INT_CLR_W { + NACK_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn txfifo_ovf_int_clr(&mut self) -> TXFIFO_OVF_INT_CLR_W { + TXFIFO_OVF_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_udf_int_clr(&mut self) -> RXFIFO_UDF_INT_CLR_W { + RXFIFO_UDF_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Write 1 to clear I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn scl_st_to_int_clr(&mut self) -> SCL_ST_TO_INT_CLR_W { + SCL_ST_TO_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn scl_main_st_to_int_clr(&mut self) -> SCL_MAIN_ST_TO_INT_CLR_W { + SCL_MAIN_ST_TO_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Write 1 to clear I2C_DET_START_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn det_start_int_clr(&mut self) -> DET_START_INT_CLR_W { + DET_START_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn slave_stretch_int_clr(&mut self) -> SLAVE_STRETCH_INT_CLR_W { + SLAVE_STRETCH_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Write 1 to clear I2C_GENARAL_CALL_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn general_call_int_clr(&mut self) -> GENERAL_CALL_INT_CLR_W { + GENERAL_CALL_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt."] + #[inline(always)] + #[must_use] + pub fn slave_addr_unmatch_int_clr(&mut self) -> SLAVE_ADDR_UNMATCH_INT_CLR_W { + SLAVE_ADDR_UNMATCH_INT_CLR_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/int_ena.rs b/esp32p4/src/i2c0/int_ena.rs new file mode 100644 index 0000000000..061232757e --- /dev/null +++ b/esp32p4/src/i2c0/int_ena.rs @@ -0,0 +1,408 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_WM_INT_ENA` reader - Write 1 to enable I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_WM_INT_ENA` writer - Write 1 to enable I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_WM_INT_ENA` reader - Write 1 to enable I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_INT_ENA_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM_INT_ENA` writer - Write 1 to enable I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF_INT_ENA` reader - Write 1 to enable I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_ENA` writer - Write 1 to enable I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `END_DETECT_INT_ENA` reader - Write 1 to enable the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_INT_ENA_R = crate::BitReader; +#[doc = "Field `END_DETECT_INT_ENA` writer - Write 1 to enable the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BYTE_TRANS_DONE_INT_ENA` reader - Write 1 to enable the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE_INT_ENA` writer - Write 1 to enable the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBITRATION_LOST_INT_ENA` reader - Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_INT_ENA_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST_INT_ENA` writer - Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MST_TXFIFO_UDF_INT_ENA` reader - Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_INT_ENA_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF_INT_ENA` writer - Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_COMPLETE_INT_ENA` reader - Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_INT_ENA_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE_INT_ENA` writer - Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIME_OUT_INT_ENA` reader - Write 1 to enable the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIME_OUT_INT_ENA` writer - Write 1 to enable the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_START_INT_ENA` reader - Write 1 to enable the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_INT_ENA_R = crate::BitReader; +#[doc = "Field `TRANS_START_INT_ENA` writer - Write 1 to enable the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACK_INT_ENA` reader - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_INT_ENA_R = crate::BitReader; +#[doc = "Field `NACK_INT_ENA` writer - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_OVF_INT_ENA` reader - Write 1 to enable I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF_INT_ENA` writer - Write 1 to enable I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_UDF_INT_ENA` reader - Write 1 to enable I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF_INT_ENA` writer - Write 1 to enable I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_ST_TO_INT_ENA` reader - Write 1 to enable I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_INT_ENA_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO_INT_ENA` writer - Write 1 to enable I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_MAIN_ST_TO_INT_ENA` reader - Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_INT_ENA_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO_INT_ENA` writer - Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DET_START_INT_ENA` reader - Write 1 to enable I2C_DET_START_INT interrupt."] +pub type DET_START_INT_ENA_R = crate::BitReader; +#[doc = "Field `DET_START_INT_ENA` writer - Write 1 to enable I2C_DET_START_INT interrupt."] +pub type DET_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLAVE_STRETCH_INT_ENA` reader - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt."] +pub type SLAVE_STRETCH_INT_ENA_R = crate::BitReader; +#[doc = "Field `SLAVE_STRETCH_INT_ENA` writer - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt."] +pub type SLAVE_STRETCH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GENERAL_CALL_INT_ENA` reader - Write 1 to enable I2C_GENARAL_CALL_INT interrupt."] +pub type GENERAL_CALL_INT_ENA_R = crate::BitReader; +#[doc = "Field `GENERAL_CALL_INT_ENA` writer - Write 1 to enable I2C_GENARAL_CALL_INT interrupt."] +pub type GENERAL_CALL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLAVE_ADDR_UNMATCH_INT_ENA` reader - Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt."] +pub type SLAVE_ADDR_UNMATCH_INT_ENA_R = crate::BitReader; +#[doc = "Field `SLAVE_ADDR_UNMATCH_INT_ENA` writer - Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt."] +pub type SLAVE_ADDR_UNMATCH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 to enable I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn rxfifo_wm_int_ena(&self) -> RXFIFO_WM_INT_ENA_R { + RXFIFO_WM_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to enable I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn txfifo_wm_int_ena(&self) -> TXFIFO_WM_INT_ENA_R { + TXFIFO_WM_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 to enable I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R { + RXFIFO_OVF_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1 to enable the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn end_detect_int_ena(&self) -> END_DETECT_INT_ENA_R { + END_DETECT_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write 1 to enable the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn byte_trans_done_int_ena(&self) -> BYTE_TRANS_DONE_INT_ENA_R { + BYTE_TRANS_DONE_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + pub fn arbitration_lost_int_ena(&self) -> ARBITRATION_LOST_INT_ENA_R { + ARBITRATION_LOST_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn mst_txfifo_udf_int_ena(&self) -> MST_TXFIFO_UDF_INT_ENA_R { + MST_TXFIFO_UDF_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn trans_complete_int_ena(&self) -> TRANS_COMPLETE_INT_ENA_R { + TRANS_COMPLETE_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Write 1 to enable the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + pub fn time_out_int_ena(&self) -> TIME_OUT_INT_ENA_R { + TIME_OUT_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write 1 to enable the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + pub fn trans_start_int_ena(&self) -> TRANS_START_INT_ENA_R { + TRANS_START_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn nack_int_ena(&self) -> NACK_INT_ENA_R { + NACK_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Write 1 to enable I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn txfifo_ovf_int_ena(&self) -> TXFIFO_OVF_INT_ENA_R { + TXFIFO_OVF_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Write 1 to enable I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_udf_int_ena(&self) -> RXFIFO_UDF_INT_ENA_R { + RXFIFO_UDF_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Write 1 to enable I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_st_to_int_ena(&self) -> SCL_ST_TO_INT_ENA_R { + SCL_ST_TO_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_main_st_to_int_ena(&self) -> SCL_MAIN_ST_TO_INT_ENA_R { + SCL_MAIN_ST_TO_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Write 1 to enable I2C_DET_START_INT interrupt."] + #[inline(always)] + pub fn det_start_int_ena(&self) -> DET_START_INT_ENA_R { + DET_START_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn slave_stretch_int_ena(&self) -> SLAVE_STRETCH_INT_ENA_R { + SLAVE_STRETCH_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Write 1 to enable I2C_GENARAL_CALL_INT interrupt."] + #[inline(always)] + pub fn general_call_int_ena(&self) -> GENERAL_CALL_INT_ENA_R { + GENERAL_CALL_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt."] + #[inline(always)] + pub fn slave_addr_unmatch_int_ena(&self) -> SLAVE_ADDR_UNMATCH_INT_ENA_R { + SLAVE_ADDR_UNMATCH_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "rxfifo_wm_int_ena", + &format_args!("{}", self.rxfifo_wm_int_ena().bit()), + ) + .field( + "txfifo_wm_int_ena", + &format_args!("{}", self.txfifo_wm_int_ena().bit()), + ) + .field( + "rxfifo_ovf_int_ena", + &format_args!("{}", self.rxfifo_ovf_int_ena().bit()), + ) + .field( + "end_detect_int_ena", + &format_args!("{}", self.end_detect_int_ena().bit()), + ) + .field( + "byte_trans_done_int_ena", + &format_args!("{}", self.byte_trans_done_int_ena().bit()), + ) + .field( + "arbitration_lost_int_ena", + &format_args!("{}", self.arbitration_lost_int_ena().bit()), + ) + .field( + "mst_txfifo_udf_int_ena", + &format_args!("{}", self.mst_txfifo_udf_int_ena().bit()), + ) + .field( + "trans_complete_int_ena", + &format_args!("{}", self.trans_complete_int_ena().bit()), + ) + .field( + "time_out_int_ena", + &format_args!("{}", self.time_out_int_ena().bit()), + ) + .field( + "trans_start_int_ena", + &format_args!("{}", self.trans_start_int_ena().bit()), + ) + .field( + "nack_int_ena", + &format_args!("{}", self.nack_int_ena().bit()), + ) + .field( + "txfifo_ovf_int_ena", + &format_args!("{}", self.txfifo_ovf_int_ena().bit()), + ) + .field( + "rxfifo_udf_int_ena", + &format_args!("{}", self.rxfifo_udf_int_ena().bit()), + ) + .field( + "scl_st_to_int_ena", + &format_args!("{}", self.scl_st_to_int_ena().bit()), + ) + .field( + "scl_main_st_to_int_ena", + &format_args!("{}", self.scl_main_st_to_int_ena().bit()), + ) + .field( + "det_start_int_ena", + &format_args!("{}", self.det_start_int_ena().bit()), + ) + .field( + "slave_stretch_int_ena", + &format_args!("{}", self.slave_stretch_int_ena().bit()), + ) + .field( + "general_call_int_ena", + &format_args!("{}", self.general_call_int_ena().bit()), + ) + .field( + "slave_addr_unmatch_int_ena", + &format_args!("{}", self.slave_addr_unmatch_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to enable I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_wm_int_ena(&mut self) -> RXFIFO_WM_INT_ENA_W { + RXFIFO_WM_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to enable I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn txfifo_wm_int_ena(&mut self) -> TXFIFO_WM_INT_ENA_W { + TXFIFO_WM_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to enable I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_ovf_int_ena(&mut self) -> RXFIFO_OVF_INT_ENA_W { + RXFIFO_OVF_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to enable the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn end_detect_int_ena(&mut self) -> END_DETECT_INT_ENA_W { + END_DETECT_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to enable the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn byte_trans_done_int_ena(&mut self) -> BYTE_TRANS_DONE_INT_ENA_W { + BYTE_TRANS_DONE_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn arbitration_lost_int_ena(&mut self) -> ARBITRATION_LOST_INT_ENA_W { + ARBITRATION_LOST_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn mst_txfifo_udf_int_ena(&mut self) -> MST_TXFIFO_UDF_INT_ENA_W { + MST_TXFIFO_UDF_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn trans_complete_int_ena(&mut self) -> TRANS_COMPLETE_INT_ENA_W { + TRANS_COMPLETE_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - Write 1 to enable the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn time_out_int_ena(&mut self) -> TIME_OUT_INT_ENA_W { + TIME_OUT_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - Write 1 to enable the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn trans_start_int_ena(&mut self) -> TRANS_START_INT_ENA_W { + TRANS_START_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn nack_int_ena(&mut self) -> NACK_INT_ENA_W { + NACK_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - Write 1 to enable I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn txfifo_ovf_int_ena(&mut self) -> TXFIFO_OVF_INT_ENA_W { + TXFIFO_OVF_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - Write 1 to enable I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_udf_int_ena(&mut self) -> RXFIFO_UDF_INT_ENA_W { + RXFIFO_UDF_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - Write 1 to enable I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn scl_st_to_int_ena(&mut self) -> SCL_ST_TO_INT_ENA_W { + SCL_ST_TO_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn scl_main_st_to_int_ena(&mut self) -> SCL_MAIN_ST_TO_INT_ENA_W { + SCL_MAIN_ST_TO_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - Write 1 to enable I2C_DET_START_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn det_start_int_ena(&mut self) -> DET_START_INT_ENA_W { + DET_START_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn slave_stretch_int_ena(&mut self) -> SLAVE_STRETCH_INT_ENA_W { + SLAVE_STRETCH_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - Write 1 to enable I2C_GENARAL_CALL_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn general_call_int_ena(&mut self) -> GENERAL_CALL_INT_ENA_W { + GENERAL_CALL_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 18 - Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn slave_addr_unmatch_int_ena(&mut self) -> SLAVE_ADDR_UNMATCH_INT_ENA_W { + SLAVE_ADDR_UNMATCH_INT_ENA_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/int_raw.rs b/esp32p4/src/i2c0/int_raw.rs new file mode 100644 index 0000000000..8298745546 --- /dev/null +++ b/esp32p4/src/i2c0/int_raw.rs @@ -0,0 +1,237 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_WM_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_INT_RAW_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM_INT_RAW` reader - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_INT_RAW_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `END_DETECT_INT_RAW` reader - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_INT_RAW_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE_INT_RAW` reader - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST_INT_RAW` reader - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_INT_RAW_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF_INT_RAW` reader - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_INT_RAW_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE_INT_RAW` reader - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIME_OUT_INT_RAW` reader - The raw interrupt status of the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `TRANS_START_INT_RAW` reader - The raw interrupt status of the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `NACK_INT_RAW` reader - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_INT_RAW_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF_INT_RAW` reader - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO_INT_RAW` reader - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_INT_RAW_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO_INT_RAW` reader - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_INT_RAW_R = crate::BitReader; +#[doc = "Field `DET_START_INT_RAW` reader - The raw interrupt status of I2C_DET_START_INT interrupt."] +pub type DET_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `SLAVE_STRETCH_INT_RAW` reader - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt."] +pub type SLAVE_STRETCH_INT_RAW_R = crate::BitReader; +#[doc = "Field `GENERAL_CALL_INT_RAW` reader - The raw interrupt status of I2C_GENARAL_CALL_INT interrupt."] +pub type GENERAL_CALL_INT_RAW_R = crate::BitReader; +#[doc = "Field `SLAVE_ADDR_UNMATCH_INT_RAW` reader - The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt."] +pub type SLAVE_ADDR_UNMATCH_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn rxfifo_wm_int_raw(&self) -> RXFIFO_WM_INT_RAW_R { + RXFIFO_WM_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn txfifo_wm_int_raw(&self) -> TXFIFO_WM_INT_RAW_R { + TXFIFO_WM_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R { + RXFIFO_OVF_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn end_detect_int_raw(&self) -> END_DETECT_INT_RAW_R { + END_DETECT_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn byte_trans_done_int_raw(&self) -> BYTE_TRANS_DONE_INT_RAW_R { + BYTE_TRANS_DONE_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + pub fn arbitration_lost_int_raw(&self) -> ARBITRATION_LOST_INT_RAW_R { + ARBITRATION_LOST_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn mst_txfifo_udf_int_raw(&self) -> MST_TXFIFO_UDF_INT_RAW_R { + MST_TXFIFO_UDF_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn trans_complete_int_raw(&self) -> TRANS_COMPLETE_INT_RAW_R { + TRANS_COMPLETE_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status of the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + pub fn time_out_int_raw(&self) -> TIME_OUT_INT_RAW_R { + TIME_OUT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status of the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + pub fn trans_start_int_raw(&self) -> TRANS_START_INT_RAW_R { + TRANS_START_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn nack_int_raw(&self) -> NACK_INT_RAW_R { + NACK_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn txfifo_ovf_int_raw(&self) -> TXFIFO_OVF_INT_RAW_R { + TXFIFO_OVF_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_udf_int_raw(&self) -> RXFIFO_UDF_INT_RAW_R { + RXFIFO_UDF_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_st_to_int_raw(&self) -> SCL_ST_TO_INT_RAW_R { + SCL_ST_TO_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_main_st_to_int_raw(&self) -> SCL_MAIN_ST_TO_INT_RAW_R { + SCL_MAIN_ST_TO_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The raw interrupt status of I2C_DET_START_INT interrupt."] + #[inline(always)] + pub fn det_start_int_raw(&self) -> DET_START_INT_RAW_R { + DET_START_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn slave_stretch_int_raw(&self) -> SLAVE_STRETCH_INT_RAW_R { + SLAVE_STRETCH_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The raw interrupt status of I2C_GENARAL_CALL_INT interrupt."] + #[inline(always)] + pub fn general_call_int_raw(&self) -> GENERAL_CALL_INT_RAW_R { + GENERAL_CALL_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt."] + #[inline(always)] + pub fn slave_addr_unmatch_int_raw(&self) -> SLAVE_ADDR_UNMATCH_INT_RAW_R { + SLAVE_ADDR_UNMATCH_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "rxfifo_wm_int_raw", + &format_args!("{}", self.rxfifo_wm_int_raw().bit()), + ) + .field( + "txfifo_wm_int_raw", + &format_args!("{}", self.txfifo_wm_int_raw().bit()), + ) + .field( + "rxfifo_ovf_int_raw", + &format_args!("{}", self.rxfifo_ovf_int_raw().bit()), + ) + .field( + "end_detect_int_raw", + &format_args!("{}", self.end_detect_int_raw().bit()), + ) + .field( + "byte_trans_done_int_raw", + &format_args!("{}", self.byte_trans_done_int_raw().bit()), + ) + .field( + "arbitration_lost_int_raw", + &format_args!("{}", self.arbitration_lost_int_raw().bit()), + ) + .field( + "mst_txfifo_udf_int_raw", + &format_args!("{}", self.mst_txfifo_udf_int_raw().bit()), + ) + .field( + "trans_complete_int_raw", + &format_args!("{}", self.trans_complete_int_raw().bit()), + ) + .field( + "time_out_int_raw", + &format_args!("{}", self.time_out_int_raw().bit()), + ) + .field( + "trans_start_int_raw", + &format_args!("{}", self.trans_start_int_raw().bit()), + ) + .field( + "nack_int_raw", + &format_args!("{}", self.nack_int_raw().bit()), + ) + .field( + "txfifo_ovf_int_raw", + &format_args!("{}", self.txfifo_ovf_int_raw().bit()), + ) + .field( + "rxfifo_udf_int_raw", + &format_args!("{}", self.rxfifo_udf_int_raw().bit()), + ) + .field( + "scl_st_to_int_raw", + &format_args!("{}", self.scl_st_to_int_raw().bit()), + ) + .field( + "scl_main_st_to_int_raw", + &format_args!("{}", self.scl_main_st_to_int_raw().bit()), + ) + .field( + "det_start_int_raw", + &format_args!("{}", self.det_start_int_raw().bit()), + ) + .field( + "slave_stretch_int_raw", + &format_args!("{}", self.slave_stretch_int_raw().bit()), + ) + .field( + "general_call_int_raw", + &format_args!("{}", self.general_call_int_raw().bit()), + ) + .field( + "slave_addr_unmatch_int_raw", + &format_args!("{}", self.slave_addr_unmatch_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0x02"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/i2c0/int_status.rs b/esp32p4/src/i2c0/int_status.rs new file mode 100644 index 0000000000..16fc99bb56 --- /dev/null +++ b/esp32p4/src/i2c0/int_status.rs @@ -0,0 +1,234 @@ +#[doc = "Register `INT_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_WM_INT_ST` reader - The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_INT_ST_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM_INT_ST` reader - The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_INT_ST_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_ST` reader - The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `END_DETECT_INT_ST` reader - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_INT_ST_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE_INT_ST` reader - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST_INT_ST` reader - The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_INT_ST_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF_INT_ST` reader - The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_INT_ST_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE_INT_ST` reader - The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_INT_ST_R = crate::BitReader; +#[doc = "Field `TIME_OUT_INT_ST` reader - The masked interrupt status status of the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_INT_ST_R = crate::BitReader; +#[doc = "Field `TRANS_START_INT_ST` reader - The masked interrupt status status of the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_INT_ST_R = crate::BitReader; +#[doc = "Field `NACK_INT_ST` reader - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_INT_ST_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF_INT_ST` reader - The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF_INT_ST` reader - The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_INT_ST_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO_INT_ST` reader - The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_INT_ST_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO_INT_ST` reader - The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_INT_ST_R = crate::BitReader; +#[doc = "Field `DET_START_INT_ST` reader - The masked interrupt status status of I2C_DET_START_INT interrupt."] +pub type DET_START_INT_ST_R = crate::BitReader; +#[doc = "Field `SLAVE_STRETCH_INT_ST` reader - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt."] +pub type SLAVE_STRETCH_INT_ST_R = crate::BitReader; +#[doc = "Field `GENERAL_CALL_INT_ST` reader - The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt."] +pub type GENERAL_CALL_INT_ST_R = crate::BitReader; +#[doc = "Field `SLAVE_ADDR_UNMATCH_INT_ST` reader - The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt."] +pub type SLAVE_ADDR_UNMATCH_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn rxfifo_wm_int_st(&self) -> RXFIFO_WM_INT_ST_R { + RXFIFO_WM_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn txfifo_wm_int_st(&self) -> TXFIFO_WM_INT_ST_R { + TXFIFO_WM_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_ovf_int_st(&self) -> RXFIFO_OVF_INT_ST_R { + RXFIFO_OVF_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn end_detect_int_st(&self) -> END_DETECT_INT_ST_R { + END_DETECT_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn byte_trans_done_int_st(&self) -> BYTE_TRANS_DONE_INT_ST_R { + BYTE_TRANS_DONE_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + pub fn arbitration_lost_int_st(&self) -> ARBITRATION_LOST_INT_ST_R { + ARBITRATION_LOST_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn mst_txfifo_udf_int_st(&self) -> MST_TXFIFO_UDF_INT_ST_R { + MST_TXFIFO_UDF_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn trans_complete_int_st(&self) -> TRANS_COMPLETE_INT_ST_R { + TRANS_COMPLETE_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The masked interrupt status status of the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + pub fn time_out_int_st(&self) -> TIME_OUT_INT_ST_R { + TIME_OUT_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The masked interrupt status status of the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + pub fn trans_start_int_st(&self) -> TRANS_START_INT_ST_R { + TRANS_START_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn nack_int_st(&self) -> NACK_INT_ST_R { + NACK_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn txfifo_ovf_int_st(&self) -> TXFIFO_OVF_INT_ST_R { + TXFIFO_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_udf_int_st(&self) -> RXFIFO_UDF_INT_ST_R { + RXFIFO_UDF_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_st_to_int_st(&self) -> SCL_ST_TO_INT_ST_R { + SCL_ST_TO_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_main_st_to_int_st(&self) -> SCL_MAIN_ST_TO_INT_ST_R { + SCL_MAIN_ST_TO_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The masked interrupt status status of I2C_DET_START_INT interrupt."] + #[inline(always)] + pub fn det_start_int_st(&self) -> DET_START_INT_ST_R { + DET_START_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn slave_stretch_int_st(&self) -> SLAVE_STRETCH_INT_ST_R { + SLAVE_STRETCH_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt."] + #[inline(always)] + pub fn general_call_int_st(&self) -> GENERAL_CALL_INT_ST_R { + GENERAL_CALL_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt."] + #[inline(always)] + pub fn slave_addr_unmatch_int_st(&self) -> SLAVE_ADDR_UNMATCH_INT_ST_R { + SLAVE_ADDR_UNMATCH_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_STATUS") + .field( + "rxfifo_wm_int_st", + &format_args!("{}", self.rxfifo_wm_int_st().bit()), + ) + .field( + "txfifo_wm_int_st", + &format_args!("{}", self.txfifo_wm_int_st().bit()), + ) + .field( + "rxfifo_ovf_int_st", + &format_args!("{}", self.rxfifo_ovf_int_st().bit()), + ) + .field( + "end_detect_int_st", + &format_args!("{}", self.end_detect_int_st().bit()), + ) + .field( + "byte_trans_done_int_st", + &format_args!("{}", self.byte_trans_done_int_st().bit()), + ) + .field( + "arbitration_lost_int_st", + &format_args!("{}", self.arbitration_lost_int_st().bit()), + ) + .field( + "mst_txfifo_udf_int_st", + &format_args!("{}", self.mst_txfifo_udf_int_st().bit()), + ) + .field( + "trans_complete_int_st", + &format_args!("{}", self.trans_complete_int_st().bit()), + ) + .field( + "time_out_int_st", + &format_args!("{}", self.time_out_int_st().bit()), + ) + .field( + "trans_start_int_st", + &format_args!("{}", self.trans_start_int_st().bit()), + ) + .field("nack_int_st", &format_args!("{}", self.nack_int_st().bit())) + .field( + "txfifo_ovf_int_st", + &format_args!("{}", self.txfifo_ovf_int_st().bit()), + ) + .field( + "rxfifo_udf_int_st", + &format_args!("{}", self.rxfifo_udf_int_st().bit()), + ) + .field( + "scl_st_to_int_st", + &format_args!("{}", self.scl_st_to_int_st().bit()), + ) + .field( + "scl_main_st_to_int_st", + &format_args!("{}", self.scl_main_st_to_int_st().bit()), + ) + .field( + "det_start_int_st", + &format_args!("{}", self.det_start_int_st().bit()), + ) + .field( + "slave_stretch_int_st", + &format_args!("{}", self.slave_stretch_int_st().bit()), + ) + .field( + "general_call_int_st", + &format_args!("{}", self.general_call_int_st().bit()), + ) + .field( + "slave_addr_unmatch_int_st", + &format_args!("{}", self.slave_addr_unmatch_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_STATUS_SPEC; +impl crate::RegisterSpec for INT_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_status::R`](R) reader structure"] +impl crate::Readable for INT_STATUS_SPEC {} +#[doc = "`reset()` method sets INT_STATUS to value 0"] +impl crate::Resettable for INT_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/rxfifo_start_addr.rs b/esp32p4/src/i2c0/rxfifo_start_addr.rs new file mode 100644 index 0000000000..fe33026457 --- /dev/null +++ b/esp32p4/src/i2c0/rxfifo_start_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RXFIFO_START_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_START_ADDR` reader - Represents the I2C rxfifo first address."] +pub type RXFIFO_START_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Represents the I2C rxfifo first address."] + #[inline(always)] + pub fn rxfifo_start_addr(&self) -> RXFIFO_START_ADDR_R { + RXFIFO_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RXFIFO_START_ADDR") + .field( + "rxfifo_start_addr", + &format_args!("{}", self.rxfifo_start_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RXFIFO_START_ADDR_SPEC; +impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifo_start_addr::R`](R) reader structure"] +impl crate::Readable for RXFIFO_START_ADDR_SPEC {} +#[doc = "`reset()` method sets RXFIFO_START_ADDR to value 0"] +impl crate::Resettable for RXFIFO_START_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/scl_high_period.rs b/esp32p4/src/i2c0/scl_high_period.rs new file mode 100644 index 0000000000..af1fade8cf --- /dev/null +++ b/esp32p4/src/i2c0/scl_high_period.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SCL_HIGH_PERIOD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_HIGH_PERIOD` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_HIGH_PERIOD` reader - Configures for how long SCL remains high in master mode. Measurement unit: i2c_sclk"] +pub type SCL_HIGH_PERIOD_R = crate::FieldReader; +#[doc = "Field `SCL_HIGH_PERIOD` writer - Configures for how long SCL remains high in master mode. Measurement unit: i2c_sclk"] +pub type SCL_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `SCL_WAIT_HIGH_PERIOD` reader - Configures the SCL_FSM's waiting period for SCL high level in master mode. Measurement unit: i2c_sclk"] +pub type SCL_WAIT_HIGH_PERIOD_R = crate::FieldReader; +#[doc = "Field `SCL_WAIT_HIGH_PERIOD` writer - Configures the SCL_FSM's waiting period for SCL high level in master mode. Measurement unit: i2c_sclk"] +pub type SCL_WAIT_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:8 - Configures for how long SCL remains high in master mode. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_high_period(&self) -> SCL_HIGH_PERIOD_R { + SCL_HIGH_PERIOD_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:15 - Configures the SCL_FSM's waiting period for SCL high level in master mode. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_wait_high_period(&self) -> SCL_WAIT_HIGH_PERIOD_R { + SCL_WAIT_HIGH_PERIOD_R::new(((self.bits >> 9) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_HIGH_PERIOD") + .field( + "scl_high_period", + &format_args!("{}", self.scl_high_period().bits()), + ) + .field( + "scl_wait_high_period", + &format_args!("{}", self.scl_wait_high_period().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures for how long SCL remains high in master mode. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_high_period(&mut self) -> SCL_HIGH_PERIOD_W { + SCL_HIGH_PERIOD_W::new(self, 0) + } + #[doc = "Bits 9:15 - Configures the SCL_FSM's waiting period for SCL high level in master mode. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_wait_high_period(&mut self) -> SCL_WAIT_HIGH_PERIOD_W { + SCL_WAIT_HIGH_PERIOD_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the high level width of SCL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_high_period::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_high_period::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_HIGH_PERIOD_SPEC; +impl crate::RegisterSpec for SCL_HIGH_PERIOD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_high_period::R`](R) reader structure"] +impl crate::Readable for SCL_HIGH_PERIOD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_high_period::W`](W) writer structure"] +impl crate::Writable for SCL_HIGH_PERIOD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_HIGH_PERIOD to value 0"] +impl crate::Resettable for SCL_HIGH_PERIOD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/scl_low_period.rs b/esp32p4/src/i2c0/scl_low_period.rs new file mode 100644 index 0000000000..a173220e64 --- /dev/null +++ b/esp32p4/src/i2c0/scl_low_period.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SCL_LOW_PERIOD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_LOW_PERIOD` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_LOW_PERIOD` reader - Configures the low level width of the SCL Clock. Measurement unit: i2c_sclk."] +pub type SCL_LOW_PERIOD_R = crate::FieldReader; +#[doc = "Field `SCL_LOW_PERIOD` writer - Configures the low level width of the SCL Clock. Measurement unit: i2c_sclk."] +pub type SCL_LOW_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the low level width of the SCL Clock. Measurement unit: i2c_sclk."] + #[inline(always)] + pub fn scl_low_period(&self) -> SCL_LOW_PERIOD_R { + SCL_LOW_PERIOD_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_LOW_PERIOD") + .field( + "scl_low_period", + &format_args!("{}", self.scl_low_period().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the low level width of the SCL Clock. Measurement unit: i2c_sclk."] + #[inline(always)] + #[must_use] + pub fn scl_low_period(&mut self) -> SCL_LOW_PERIOD_W { + SCL_LOW_PERIOD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the low level width of the SCL Clock.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_low_period::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_low_period::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_LOW_PERIOD_SPEC; +impl crate::RegisterSpec for SCL_LOW_PERIOD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_low_period::R`](R) reader structure"] +impl crate::Readable for SCL_LOW_PERIOD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_low_period::W`](W) writer structure"] +impl crate::Writable for SCL_LOW_PERIOD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_LOW_PERIOD to value 0"] +impl crate::Resettable for SCL_LOW_PERIOD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/scl_main_st_time_out.rs b/esp32p4/src/i2c0/scl_main_st_time_out.rs new file mode 100644 index 0000000000..23d278a5f5 --- /dev/null +++ b/esp32p4/src/i2c0/scl_main_st_time_out.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SCL_MAIN_ST_TIME_OUT` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_MAIN_ST_TIME_OUT` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_MAIN_ST_TO_I2C` reader - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. Measurement unit: i2c_sclk"] +pub type SCL_MAIN_ST_TO_I2C_R = crate::FieldReader; +#[doc = "Field `SCL_MAIN_ST_TO_I2C` writer - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. Measurement unit: i2c_sclk"] +pub type SCL_MAIN_ST_TO_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_main_st_to_i2c(&self) -> SCL_MAIN_ST_TO_I2C_R { + SCL_MAIN_ST_TO_I2C_R::new((self.bits & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_MAIN_ST_TIME_OUT") + .field( + "scl_main_st_to_i2c", + &format_args!("{}", self.scl_main_st_to_i2c().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_main_st_to_i2c(&mut self) -> SCL_MAIN_ST_TO_I2C_W { + SCL_MAIN_ST_TO_I2C_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SCL main status time out register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_main_st_time_out::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_main_st_time_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_MAIN_ST_TIME_OUT_SPEC; +impl crate::RegisterSpec for SCL_MAIN_ST_TIME_OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_main_st_time_out::R`](R) reader structure"] +impl crate::Readable for SCL_MAIN_ST_TIME_OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_main_st_time_out::W`](W) writer structure"] +impl crate::Writable for SCL_MAIN_ST_TIME_OUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_MAIN_ST_TIME_OUT to value 0x10"] +impl crate::Resettable for SCL_MAIN_ST_TIME_OUT_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/esp32p4/src/i2c0/scl_rstart_setup.rs b/esp32p4/src/i2c0/scl_rstart_setup.rs new file mode 100644 index 0000000000..81b2c9d683 --- /dev/null +++ b/esp32p4/src/i2c0/scl_rstart_setup.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SCL_RSTART_SETUP` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_RSTART_SETUP` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. Measurement unit: i2c_sclk"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. Measurement unit: i2c_sclk"] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_RSTART_SETUP") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the delay between the positive edge of SCL and the negative edge of SDA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_rstart_setup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_rstart_setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_RSTART_SETUP_SPEC; +impl crate::RegisterSpec for SCL_RSTART_SETUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_rstart_setup::R`](R) reader structure"] +impl crate::Readable for SCL_RSTART_SETUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_rstart_setup::W`](W) writer structure"] +impl crate::Writable for SCL_RSTART_SETUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_RSTART_SETUP to value 0x08"] +impl crate::Resettable for SCL_RSTART_SETUP_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/i2c0/scl_sp_conf.rs b/esp32p4/src/i2c0/scl_sp_conf.rs new file mode 100644 index 0000000000..39cdeec8ed --- /dev/null +++ b/esp32p4/src/i2c0/scl_sp_conf.rs @@ -0,0 +1,117 @@ +#[doc = "Register `SCL_SP_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_SP_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_RST_SLV_EN` reader - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] +pub type SCL_RST_SLV_EN_R = crate::BitReader; +#[doc = "Field `SCL_RST_SLV_EN` writer - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] +pub type SCL_RST_SLV_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_RST_SLV_NUM` reader - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. Measurement unit: i2c_sclk"] +pub type SCL_RST_SLV_NUM_R = crate::FieldReader; +#[doc = "Field `SCL_RST_SLV_NUM` writer - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. Measurement unit: i2c_sclk"] +pub type SCL_RST_SLV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SCL_PD_EN` reader - Configures to power down the I2C output SCL line. 0: Not power down. 1: Power down. Valid only when reg_scl_force_out is 1."] +pub type SCL_PD_EN_R = crate::BitReader; +#[doc = "Field `SCL_PD_EN` writer - Configures to power down the I2C output SCL line. 0: Not power down. 1: Power down. Valid only when reg_scl_force_out is 1."] +pub type SCL_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDA_PD_EN` reader - Configures to power down the I2C output SDA line. 0: Not power down. 1: Power down. Valid only when reg_sda_force_out is 1."] +pub type SDA_PD_EN_R = crate::BitReader; +#[doc = "Field `SDA_PD_EN` writer - Configures to power down the I2C output SDA line. 0: Not power down. 1: Power down. Valid only when reg_sda_force_out is 1."] +pub type SDA_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] + #[inline(always)] + pub fn scl_rst_slv_en(&self) -> SCL_RST_SLV_EN_R { + SCL_RST_SLV_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:5 - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_rst_slv_num(&self) -> SCL_RST_SLV_NUM_R { + SCL_RST_SLV_NUM_R::new(((self.bits >> 1) & 0x1f) as u8) + } + #[doc = "Bit 6 - Configures to power down the I2C output SCL line. 0: Not power down. 1: Power down. Valid only when reg_scl_force_out is 1."] + #[inline(always)] + pub fn scl_pd_en(&self) -> SCL_PD_EN_R { + SCL_PD_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures to power down the I2C output SDA line. 0: Not power down. 1: Power down. Valid only when reg_sda_force_out is 1."] + #[inline(always)] + pub fn sda_pd_en(&self) -> SDA_PD_EN_R { + SDA_PD_EN_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_SP_CONF") + .field( + "scl_rst_slv_en", + &format_args!("{}", self.scl_rst_slv_en().bit()), + ) + .field( + "scl_rst_slv_num", + &format_args!("{}", self.scl_rst_slv_num().bits()), + ) + .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit())) + .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] + #[inline(always)] + #[must_use] + pub fn scl_rst_slv_en(&mut self) -> SCL_RST_SLV_EN_W { + SCL_RST_SLV_EN_W::new(self, 0) + } + #[doc = "Bits 1:5 - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_rst_slv_num(&mut self) -> SCL_RST_SLV_NUM_W { + SCL_RST_SLV_NUM_W::new(self, 1) + } + #[doc = "Bit 6 - Configures to power down the I2C output SCL line. 0: Not power down. 1: Power down. Valid only when reg_scl_force_out is 1."] + #[inline(always)] + #[must_use] + pub fn scl_pd_en(&mut self) -> SCL_PD_EN_W { + SCL_PD_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Configures to power down the I2C output SDA line. 0: Not power down. 1: Power down. Valid only when reg_sda_force_out is 1."] + #[inline(always)] + #[must_use] + pub fn sda_pd_en(&mut self) -> SDA_PD_EN_W { + SDA_PD_EN_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Power configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_sp_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_sp_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_SP_CONF_SPEC; +impl crate::RegisterSpec for SCL_SP_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_sp_conf::R`](R) reader structure"] +impl crate::Readable for SCL_SP_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_sp_conf::W`](W) writer structure"] +impl crate::Writable for SCL_SP_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_SP_CONF to value 0"] +impl crate::Resettable for SCL_SP_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/scl_st_time_out.rs b/esp32p4/src/i2c0/scl_st_time_out.rs new file mode 100644 index 0000000000..3811a9e1fb --- /dev/null +++ b/esp32p4/src/i2c0/scl_st_time_out.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SCL_ST_TIME_OUT` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_ST_TIME_OUT` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_ST_TO_I2C` reader - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. Measurement unit: i2c_sclk"] +pub type SCL_ST_TO_I2C_R = crate::FieldReader; +#[doc = "Field `SCL_ST_TO_I2C` writer - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. Measurement unit: i2c_sclk"] +pub type SCL_ST_TO_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_st_to_i2c(&self) -> SCL_ST_TO_I2C_R { + SCL_ST_TO_I2C_R::new((self.bits & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_ST_TIME_OUT") + .field( + "scl_st_to_i2c", + &format_args!("{}", self.scl_st_to_i2c().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_st_to_i2c(&mut self) -> SCL_ST_TO_I2C_W { + SCL_ST_TO_I2C_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SCL status time out register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_st_time_out::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_st_time_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_ST_TIME_OUT_SPEC; +impl crate::RegisterSpec for SCL_ST_TIME_OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_st_time_out::R`](R) reader structure"] +impl crate::Readable for SCL_ST_TIME_OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_st_time_out::W`](W) writer structure"] +impl crate::Writable for SCL_ST_TIME_OUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_ST_TIME_OUT to value 0x10"] +impl crate::Resettable for SCL_ST_TIME_OUT_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/esp32p4/src/i2c0/scl_start_hold.rs b/esp32p4/src/i2c0/scl_start_hold.rs new file mode 100644 index 0000000000..a1a367768c --- /dev/null +++ b/esp32p4/src/i2c0/scl_start_hold.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SCL_START_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_START_HOLD` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: i2c_sclk."] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: i2c_sclk."] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: i2c_sclk."] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_START_HOLD") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: i2c_sclk."] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the delay between the SDA and SCL negative edge for a start condition\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_start_hold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_start_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_START_HOLD_SPEC; +impl crate::RegisterSpec for SCL_START_HOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_start_hold::R`](R) reader structure"] +impl crate::Readable for SCL_START_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_start_hold::W`](W) writer structure"] +impl crate::Writable for SCL_START_HOLD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_START_HOLD to value 0x08"] +impl crate::Resettable for SCL_START_HOLD_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/i2c0/scl_stop_hold.rs b/esp32p4/src/i2c0/scl_stop_hold.rs new file mode 100644 index 0000000000..866c4b67bc --- /dev/null +++ b/esp32p4/src/i2c0/scl_stop_hold.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SCL_STOP_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_STOP_HOLD` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the delay after the STOP condition. Measurement unit: i2c_sclk"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the delay after the STOP condition. Measurement unit: i2c_sclk"] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the delay after the STOP condition. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_STOP_HOLD") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the delay after the STOP condition. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the delay after the SCL clock edge for a stop condition\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_hold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_STOP_HOLD_SPEC; +impl crate::RegisterSpec for SCL_STOP_HOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_stop_hold::R`](R) reader structure"] +impl crate::Readable for SCL_STOP_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_stop_hold::W`](W) writer structure"] +impl crate::Writable for SCL_STOP_HOLD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_STOP_HOLD to value 0x08"] +impl crate::Resettable for SCL_STOP_HOLD_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/i2c0/scl_stop_setup.rs b/esp32p4/src/i2c0/scl_stop_setup.rs new file mode 100644 index 0000000000..dd58745711 --- /dev/null +++ b/esp32p4/src/i2c0/scl_stop_setup.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SCL_STOP_SETUP` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_STOP_SETUP` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the time between the rising edge of SCL and the rising edge of SDA. Measurement unit: i2c_sclk"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the time between the rising edge of SCL and the rising edge of SDA. Measurement unit: i2c_sclk"] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the time between the rising edge of SCL and the rising edge of SDA. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_STOP_SETUP") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the time between the rising edge of SCL and the rising edge of SDA. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the delay between the SDA and SCL rising edge for a stop condition. Measurement unit: i2c_sclk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_setup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_STOP_SETUP_SPEC; +impl crate::RegisterSpec for SCL_STOP_SETUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_stop_setup::R`](R) reader structure"] +impl crate::Readable for SCL_STOP_SETUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_stop_setup::W`](W) writer structure"] +impl crate::Writable for SCL_STOP_SETUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_STOP_SETUP to value 0x08"] +impl crate::Resettable for SCL_STOP_SETUP_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/i2c0/scl_stretch_conf.rs b/esp32p4/src/i2c0/scl_stretch_conf.rs new file mode 100644 index 0000000000..8c1ae16cef --- /dev/null +++ b/esp32p4/src/i2c0/scl_stretch_conf.rs @@ -0,0 +1,131 @@ +#[doc = "Register `SCL_STRETCH_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_STRETCH_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `STRETCH_PROTECT_NUM` reader - Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. Measurement unit: i2c_sclk"] +pub type STRETCH_PROTECT_NUM_R = crate::FieldReader; +#[doc = "Field `STRETCH_PROTECT_NUM` writer - Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. Measurement unit: i2c_sclk"] +pub type STRETCH_PROTECT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `SLAVE_SCL_STRETCH_EN` reader - Configures to enable slave SCL stretch function. 0: Disable 1: Enable The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause."] +pub type SLAVE_SCL_STRETCH_EN_R = crate::BitReader; +#[doc = "Field `SLAVE_SCL_STRETCH_EN` writer - Configures to enable slave SCL stretch function. 0: Disable 1: Enable The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause."] +pub type SLAVE_SCL_STRETCH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLAVE_SCL_STRETCH_CLR` writer - Configures to clear the I2C slave SCL stretch function. 0: No effect 1: Clear"] +pub type SLAVE_SCL_STRETCH_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLAVE_BYTE_ACK_CTL_EN` reader - Configures to enable the function for slave to control ACK level. 0: Disable 1: Enable"] +pub type SLAVE_BYTE_ACK_CTL_EN_R = crate::BitReader; +#[doc = "Field `SLAVE_BYTE_ACK_CTL_EN` writer - Configures to enable the function for slave to control ACK level. 0: Disable 1: Enable"] +pub type SLAVE_BYTE_ACK_CTL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLAVE_BYTE_ACK_LVL` reader - Set the ACK level when slave controlling ACK level function enables. 0: Low level 1: High level"] +pub type SLAVE_BYTE_ACK_LVL_R = crate::BitReader; +#[doc = "Field `SLAVE_BYTE_ACK_LVL` writer - Set the ACK level when slave controlling ACK level function enables. 0: Low level 1: High level"] +pub type SLAVE_BYTE_ACK_LVL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:9 - Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn stretch_protect_num(&self) -> STRETCH_PROTECT_NUM_R { + STRETCH_PROTECT_NUM_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bit 10 - Configures to enable slave SCL stretch function. 0: Disable 1: Enable The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause."] + #[inline(always)] + pub fn slave_scl_stretch_en(&self) -> SLAVE_SCL_STRETCH_EN_R { + SLAVE_SCL_STRETCH_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - Configures to enable the function for slave to control ACK level. 0: Disable 1: Enable"] + #[inline(always)] + pub fn slave_byte_ack_ctl_en(&self) -> SLAVE_BYTE_ACK_CTL_EN_R { + SLAVE_BYTE_ACK_CTL_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set the ACK level when slave controlling ACK level function enables. 0: Low level 1: High level"] + #[inline(always)] + pub fn slave_byte_ack_lvl(&self) -> SLAVE_BYTE_ACK_LVL_R { + SLAVE_BYTE_ACK_LVL_R::new(((self.bits >> 13) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_STRETCH_CONF") + .field( + "stretch_protect_num", + &format_args!("{}", self.stretch_protect_num().bits()), + ) + .field( + "slave_scl_stretch_en", + &format_args!("{}", self.slave_scl_stretch_en().bit()), + ) + .field( + "slave_byte_ack_ctl_en", + &format_args!("{}", self.slave_byte_ack_ctl_en().bit()), + ) + .field( + "slave_byte_ack_lvl", + &format_args!("{}", self.slave_byte_ack_lvl().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn stretch_protect_num(&mut self) -> STRETCH_PROTECT_NUM_W { + STRETCH_PROTECT_NUM_W::new(self, 0) + } + #[doc = "Bit 10 - Configures to enable slave SCL stretch function. 0: Disable 1: Enable The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause."] + #[inline(always)] + #[must_use] + pub fn slave_scl_stretch_en(&mut self) -> SLAVE_SCL_STRETCH_EN_W { + SLAVE_SCL_STRETCH_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Configures to clear the I2C slave SCL stretch function. 0: No effect 1: Clear"] + #[inline(always)] + #[must_use] + pub fn slave_scl_stretch_clr(&mut self) -> SLAVE_SCL_STRETCH_CLR_W { + SLAVE_SCL_STRETCH_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures to enable the function for slave to control ACK level. 0: Disable 1: Enable"] + #[inline(always)] + #[must_use] + pub fn slave_byte_ack_ctl_en(&mut self) -> SLAVE_BYTE_ACK_CTL_EN_W { + SLAVE_BYTE_ACK_CTL_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Set the ACK level when slave controlling ACK level function enables. 0: Low level 1: High level"] + #[inline(always)] + #[must_use] + pub fn slave_byte_ack_lvl(&mut self) -> SLAVE_BYTE_ACK_LVL_W { + SLAVE_BYTE_ACK_LVL_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Set SCL stretch of I2C slave\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stretch_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stretch_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_STRETCH_CONF_SPEC; +impl crate::RegisterSpec for SCL_STRETCH_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_stretch_conf::R`](R) reader structure"] +impl crate::Readable for SCL_STRETCH_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_stretch_conf::W`](W) writer structure"] +impl crate::Writable for SCL_STRETCH_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_STRETCH_CONF to value 0"] +impl crate::Resettable for SCL_STRETCH_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/sda_hold.rs b/esp32p4/src/i2c0/sda_hold.rs new file mode 100644 index 0000000000..4cba5c0c26 --- /dev/null +++ b/esp32p4/src/i2c0/sda_hold.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SDA_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `SDA_HOLD` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the time to hold the data after the falling edge of SCL. Measurement unit: i2c_sclk"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the time to hold the data after the falling edge of SCL. Measurement unit: i2c_sclk"] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the time to hold the data after the falling edge of SCL. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDA_HOLD") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the time to hold the data after the falling edge of SCL. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the hold time after a negative SCL edge.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDA_HOLD_SPEC; +impl crate::RegisterSpec for SDA_HOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sda_hold::R`](R) reader structure"] +impl crate::Readable for SDA_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sda_hold::W`](W) writer structure"] +impl crate::Writable for SDA_HOLD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDA_HOLD to value 0"] +impl crate::Resettable for SDA_HOLD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/sda_sample.rs b/esp32p4/src/i2c0/sda_sample.rs new file mode 100644 index 0000000000..f733b428d5 --- /dev/null +++ b/esp32p4/src/i2c0/sda_sample.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SDA_SAMPLE` reader"] +pub type R = crate::R; +#[doc = "Register `SDA_SAMPLE` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the sample time after a positive SCL edge. Measurement unit: i2c_sclk"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the sample time after a positive SCL edge. Measurement unit: i2c_sclk"] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the sample time after a positive SCL edge. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDA_SAMPLE") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the sample time after a positive SCL edge. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the sample time after a positive SCL edge.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_sample::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_sample::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDA_SAMPLE_SPEC; +impl crate::RegisterSpec for SDA_SAMPLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sda_sample::R`](R) reader structure"] +impl crate::Readable for SDA_SAMPLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sda_sample::W`](W) writer structure"] +impl crate::Writable for SDA_SAMPLE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDA_SAMPLE to value 0"] +impl crate::Resettable for SDA_SAMPLE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/slave_addr.rs b/esp32p4/src/i2c0/slave_addr.rs new file mode 100644 index 0000000000..f44d131faf --- /dev/null +++ b/esp32p4/src/i2c0/slave_addr.rs @@ -0,0 +1,82 @@ +#[doc = "Register `SLAVE_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SLAVE_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `SLAVE_ADDR` reader - Configure the slave address of I2C Slave."] +pub type SLAVE_ADDR_R = crate::FieldReader; +#[doc = "Field `SLAVE_ADDR` writer - Configure the slave address of I2C Slave."] +pub type SLAVE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `ADDR_10BIT_EN` reader - Configures to enable the slave 10-bit addressing mode in master mode. 0: No effect 1: Enable"] +pub type ADDR_10BIT_EN_R = crate::BitReader; +#[doc = "Field `ADDR_10BIT_EN` writer - Configures to enable the slave 10-bit addressing mode in master mode. 0: No effect 1: Enable"] +pub type ADDR_10BIT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:14 - Configure the slave address of I2C Slave."] + #[inline(always)] + pub fn slave_addr(&self) -> SLAVE_ADDR_R { + SLAVE_ADDR_R::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bit 31 - Configures to enable the slave 10-bit addressing mode in master mode. 0: No effect 1: Enable"] + #[inline(always)] + pub fn addr_10bit_en(&self) -> ADDR_10BIT_EN_R { + ADDR_10BIT_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLAVE_ADDR") + .field("slave_addr", &format_args!("{}", self.slave_addr().bits())) + .field( + "addr_10bit_en", + &format_args!("{}", self.addr_10bit_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:14 - Configure the slave address of I2C Slave."] + #[inline(always)] + #[must_use] + pub fn slave_addr(&mut self) -> SLAVE_ADDR_W { + SLAVE_ADDR_W::new(self, 0) + } + #[doc = "Bit 31 - Configures to enable the slave 10-bit addressing mode in master mode. 0: No effect 1: Enable"] + #[inline(always)] + #[must_use] + pub fn addr_10bit_en(&mut self) -> ADDR_10BIT_EN_W { + ADDR_10BIT_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Local slave address setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slave_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLAVE_ADDR_SPEC; +impl crate::RegisterSpec for SLAVE_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slave_addr::R`](R) reader structure"] +impl crate::Readable for SLAVE_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slave_addr::W`](W) writer structure"] +impl crate::Writable for SLAVE_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLAVE_ADDR to value 0"] +impl crate::Resettable for SLAVE_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2c0/sr.rs b/esp32p4/src/i2c0/sr.rs new file mode 100644 index 0000000000..1fbb1beaeb --- /dev/null +++ b/esp32p4/src/i2c0/sr.rs @@ -0,0 +1,120 @@ +#[doc = "Register `SR` reader"] +pub type R = crate::R; +#[doc = "Field `RESP_REC` reader - Represents the received ACK value in master mode or slave mode. 0: ACK, 1: NACK."] +pub type RESP_REC_R = crate::BitReader; +#[doc = "Field `SLAVE_RW` reader - Represents the transfer direction in slave mode,. 1: Master reads from slave, 0: Master writes to slave."] +pub type SLAVE_RW_R = crate::BitReader; +#[doc = "Field `ARB_LOST` reader - Represents whether the I2C controller loses control of SCL line. 0: No arbitration lost 1: Arbitration lost"] +pub type ARB_LOST_R = crate::BitReader; +#[doc = "Field `BUS_BUSY` reader - Represents the I2C bus state. 1: The I2C bus is busy transferring data, 0: The I2C bus is in idle state."] +pub type BUS_BUSY_R = crate::BitReader; +#[doc = "Field `SLAVE_ADDRESSED` reader - Represents whether the address sent by the master is equal to the address of the slave. Valid only when the module is configured as an I2C Slave. 0: Not equal 1: Equal"] +pub type SLAVE_ADDRESSED_R = crate::BitReader; +#[doc = "Field `RXFIFO_CNT` reader - Represents the number of data bytes to be sent."] +pub type RXFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `STRETCH_CAUSE` reader - Represents the cause of SCL clocking stretching in slave mode. 0: Stretching SCL low when the master starts to read data. 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. 2: Stretching SCL low when I2C RX FIFO is full in slave mode."] +pub type STRETCH_CAUSE_R = crate::FieldReader; +#[doc = "Field `TXFIFO_CNT` reader - Represents the number of data bytes received in RAM."] +pub type TXFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `SCL_MAIN_STATE_LAST` reader - Represents the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"] +pub type SCL_MAIN_STATE_LAST_R = crate::FieldReader; +#[doc = "Field `SCL_STATE_LAST` reader - Represents the states of the state machine used to produce SCL. 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"] +pub type SCL_STATE_LAST_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Represents the received ACK value in master mode or slave mode. 0: ACK, 1: NACK."] + #[inline(always)] + pub fn resp_rec(&self) -> RESP_REC_R { + RESP_REC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents the transfer direction in slave mode,. 1: Master reads from slave, 0: Master writes to slave."] + #[inline(always)] + pub fn slave_rw(&self) -> SLAVE_RW_R { + SLAVE_RW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Represents whether the I2C controller loses control of SCL line. 0: No arbitration lost 1: Arbitration lost"] + #[inline(always)] + pub fn arb_lost(&self) -> ARB_LOST_R { + ARB_LOST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents the I2C bus state. 1: The I2C bus is busy transferring data, 0: The I2C bus is in idle state."] + #[inline(always)] + pub fn bus_busy(&self) -> BUS_BUSY_R { + BUS_BUSY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents whether the address sent by the master is equal to the address of the slave. Valid only when the module is configured as an I2C Slave. 0: Not equal 1: Equal"] + #[inline(always)] + pub fn slave_addressed(&self) -> SLAVE_ADDRESSED_R { + SLAVE_ADDRESSED_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 8:13 - Represents the number of data bytes to be sent."] + #[inline(always)] + pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R { + RXFIFO_CNT_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 14:15 - Represents the cause of SCL clocking stretching in slave mode. 0: Stretching SCL low when the master starts to read data. 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. 2: Stretching SCL low when I2C RX FIFO is full in slave mode."] + #[inline(always)] + pub fn stretch_cause(&self) -> STRETCH_CAUSE_R { + STRETCH_CAUSE_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 18:23 - Represents the number of data bytes received in RAM."] + #[inline(always)] + pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R { + TXFIFO_CNT_R::new(((self.bits >> 18) & 0x3f) as u8) + } + #[doc = "Bits 24:26 - Represents the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"] + #[inline(always)] + pub fn scl_main_state_last(&self) -> SCL_MAIN_STATE_LAST_R { + SCL_MAIN_STATE_LAST_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 28:30 - Represents the states of the state machine used to produce SCL. 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"] + #[inline(always)] + pub fn scl_state_last(&self) -> SCL_STATE_LAST_R { + SCL_STATE_LAST_R::new(((self.bits >> 28) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SR") + .field("resp_rec", &format_args!("{}", self.resp_rec().bit())) + .field("slave_rw", &format_args!("{}", self.slave_rw().bit())) + .field("arb_lost", &format_args!("{}", self.arb_lost().bit())) + .field("bus_busy", &format_args!("{}", self.bus_busy().bit())) + .field( + "slave_addressed", + &format_args!("{}", self.slave_addressed().bit()), + ) + .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits())) + .field( + "stretch_cause", + &format_args!("{}", self.stretch_cause().bits()), + ) + .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits())) + .field( + "scl_main_state_last", + &format_args!("{}", self.scl_main_state_last().bits()), + ) + .field( + "scl_state_last", + &format_args!("{}", self.scl_state_last().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SR_SPEC; +impl crate::RegisterSpec for SR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} +#[doc = "`reset()` method sets SR to value 0xc000"] +impl crate::Resettable for SR_SPEC { + const RESET_VALUE: Self::Ux = 0xc000; +} diff --git a/esp32p4/src/i2c0/to.rs b/esp32p4/src/i2c0/to.rs new file mode 100644 index 0000000000..d6ee8f5140 --- /dev/null +++ b/esp32p4/src/i2c0/to.rs @@ -0,0 +1,82 @@ +#[doc = "Register `TO` reader"] +pub type R = crate::R; +#[doc = "Register `TO` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_OUT_VALUE` reader - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). Measurement unit: i2c_sclk."] +pub type TIME_OUT_VALUE_R = crate::FieldReader; +#[doc = "Field `TIME_OUT_VALUE` writer - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). Measurement unit: i2c_sclk."] +pub type TIME_OUT_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `TIME_OUT_EN` reader - Configures to enable time out control. 0: No effect 1: Enable"] +pub type TIME_OUT_EN_R = crate::BitReader; +#[doc = "Field `TIME_OUT_EN` writer - Configures to enable time out control. 0: No effect 1: Enable"] +pub type TIME_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). Measurement unit: i2c_sclk."] + #[inline(always)] + pub fn time_out_value(&self) -> TIME_OUT_VALUE_R { + TIME_OUT_VALUE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Configures to enable time out control. 0: No effect 1: Enable"] + #[inline(always)] + pub fn time_out_en(&self) -> TIME_OUT_EN_R { + TIME_OUT_EN_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TO") + .field( + "time_out_value", + &format_args!("{}", self.time_out_value().bits()), + ) + .field("time_out_en", &format_args!("{}", self.time_out_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). Measurement unit: i2c_sclk."] + #[inline(always)] + #[must_use] + pub fn time_out_value(&mut self) -> TIME_OUT_VALUE_W { + TIME_OUT_VALUE_W::new(self, 0) + } + #[doc = "Bit 5 - Configures to enable time out control. 0: No effect 1: Enable"] + #[inline(always)] + #[must_use] + pub fn time_out_en(&mut self) -> TIME_OUT_EN_W { + TIME_OUT_EN_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Setting time out control for receiving data.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`to::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`to::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TO_SPEC; +impl crate::RegisterSpec for TO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`to::R`](R) reader structure"] +impl crate::Readable for TO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`to::W`](W) writer structure"] +impl crate::Writable for TO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TO to value 0x10"] +impl crate::Resettable for TO_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/esp32p4/src/i2c0/txfifo_start_addr.rs b/esp32p4/src/i2c0/txfifo_start_addr.rs new file mode 100644 index 0000000000..6fa651b202 --- /dev/null +++ b/esp32p4/src/i2c0/txfifo_start_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `TXFIFO_START_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `TXFIFO_START_ADDR` reader - Represents the I2C txfifo first address."] +pub type TXFIFO_START_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Represents the I2C txfifo first address."] + #[inline(always)] + pub fn txfifo_start_addr(&self) -> TXFIFO_START_ADDR_R { + TXFIFO_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TXFIFO_START_ADDR") + .field( + "txfifo_start_addr", + &format_args!("{}", self.txfifo_start_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TXFIFO_START_ADDR_SPEC; +impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifo_start_addr::R`](R) reader structure"] +impl crate::Readable for TXFIFO_START_ADDR_SPEC {} +#[doc = "`reset()` method sets TXFIFO_START_ADDR to value 0"] +impl crate::Resettable for TXFIFO_START_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2s0.rs b/esp32p4/src/i2s0.rs new file mode 100644 index 0000000000..75bef236bd --- /dev/null +++ b/esp32p4/src/i2s0.rs @@ -0,0 +1,251 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + _reserved0: [u8; 0x0c], + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + _reserved4: [u8; 0x04], + rx_conf: RX_CONF, + tx_conf: TX_CONF, + rx_conf1: RX_CONF1, + tx_conf1: TX_CONF1, + _reserved8: [u8; 0x10], + tx_pcm2pdm_conf: TX_PCM2PDM_CONF, + tx_pcm2pdm_conf1: TX_PCM2PDM_CONF1, + rx_pdm2pcm_conf: RX_PDM2PCM_CONF, + _reserved11: [u8; 0x04], + rx_tdm_ctrl: RX_TDM_CTRL, + tx_tdm_ctrl: TX_TDM_CTRL, + rx_timing: RX_TIMING, + tx_timing: TX_TIMING, + lc_hung_conf: LC_HUNG_CONF, + rxeof_num: RXEOF_NUM, + conf_sigle_data: CONF_SIGLE_DATA, + state: STATE, + etm_conf: ETM_CONF, + fifo_cnt: FIFO_CNT, + bck_cnt: BCK_CNT, + clk_gate: CLK_GATE, + date: DATE, +} +impl RegisterBlock { + #[doc = "0x0c - I2S interrupt raw register, valid in level."] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x10 - I2S interrupt status register."] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x14 - I2S interrupt enable register."] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x18 - I2S interrupt clear register."] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x20 - I2S RX configure register"] + #[inline(always)] + pub const fn rx_conf(&self) -> &RX_CONF { + &self.rx_conf + } + #[doc = "0x24 - I2S TX configure register"] + #[inline(always)] + pub const fn tx_conf(&self) -> &TX_CONF { + &self.tx_conf + } + #[doc = "0x28 - I2S RX configure register 1"] + #[inline(always)] + pub const fn rx_conf1(&self) -> &RX_CONF1 { + &self.rx_conf1 + } + #[doc = "0x2c - I2S TX configure register 1"] + #[inline(always)] + pub const fn tx_conf1(&self) -> &TX_CONF1 { + &self.tx_conf1 + } + #[doc = "0x40 - I2S TX PCM2PDM configuration register"] + #[inline(always)] + pub const fn tx_pcm2pdm_conf(&self) -> &TX_PCM2PDM_CONF { + &self.tx_pcm2pdm_conf + } + #[doc = "0x44 - I2S TX PCM2PDM configuration register"] + #[inline(always)] + pub const fn tx_pcm2pdm_conf1(&self) -> &TX_PCM2PDM_CONF1 { + &self.tx_pcm2pdm_conf1 + } + #[doc = "0x48 - I2S RX configure register"] + #[inline(always)] + pub const fn rx_pdm2pcm_conf(&self) -> &RX_PDM2PCM_CONF { + &self.rx_pdm2pcm_conf + } + #[doc = "0x50 - I2S TX TDM mode control register"] + #[inline(always)] + pub const fn rx_tdm_ctrl(&self) -> &RX_TDM_CTRL { + &self.rx_tdm_ctrl + } + #[doc = "0x54 - I2S TX TDM mode control register"] + #[inline(always)] + pub const fn tx_tdm_ctrl(&self) -> &TX_TDM_CTRL { + &self.tx_tdm_ctrl + } + #[doc = "0x58 - I2S RX timing control register"] + #[inline(always)] + pub const fn rx_timing(&self) -> &RX_TIMING { + &self.rx_timing + } + #[doc = "0x5c - I2S TX timing control register"] + #[inline(always)] + pub const fn tx_timing(&self) -> &TX_TIMING { + &self.tx_timing + } + #[doc = "0x60 - I2S HUNG configure register."] + #[inline(always)] + pub const fn lc_hung_conf(&self) -> &LC_HUNG_CONF { + &self.lc_hung_conf + } + #[doc = "0x64 - I2S RX data number control register."] + #[inline(always)] + pub const fn rxeof_num(&self) -> &RXEOF_NUM { + &self.rxeof_num + } + #[doc = "0x68 - I2S signal data register"] + #[inline(always)] + pub const fn conf_sigle_data(&self) -> &CONF_SIGLE_DATA { + &self.conf_sigle_data + } + #[doc = "0x6c - I2S TX status register"] + #[inline(always)] + pub const fn state(&self) -> &STATE { + &self.state + } + #[doc = "0x70 - I2S ETM configure register"] + #[inline(always)] + pub const fn etm_conf(&self) -> &ETM_CONF { + &self.etm_conf + } + #[doc = "0x74 - I2S sync counter register"] + #[inline(always)] + pub const fn fifo_cnt(&self) -> &FIFO_CNT { + &self.fifo_cnt + } + #[doc = "0x78 - I2S sync counter register"] + #[inline(always)] + pub const fn bck_cnt(&self) -> &BCK_CNT { + &self.bck_cnt + } + #[doc = "0x7c - Clock gate register"] + #[inline(always)] + pub const fn clk_gate(&self) -> &CLK_GATE { + &self.clk_gate + } + #[doc = "0x80 - Version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "INT_RAW (r) register accessor: I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "I2S interrupt raw register, valid in level."] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "I2S interrupt status register."] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: I2S interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "I2S interrupt enable register."] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: I2S interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "I2S interrupt clear register."] +pub mod int_clr; +#[doc = "RX_CONF (rw) register accessor: I2S RX configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_conf`] module"] +pub type RX_CONF = crate::Reg; +#[doc = "I2S RX configure register"] +pub mod rx_conf; +#[doc = "TX_CONF (rw) register accessor: I2S TX configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_conf`] module"] +pub type TX_CONF = crate::Reg; +#[doc = "I2S TX configure register"] +pub mod tx_conf; +#[doc = "RX_CONF1 (rw) register accessor: I2S RX configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_conf1`] module"] +pub type RX_CONF1 = crate::Reg; +#[doc = "I2S RX configure register 1"] +pub mod rx_conf1; +#[doc = "TX_CONF1 (rw) register accessor: I2S TX configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_conf1`] module"] +pub type TX_CONF1 = crate::Reg; +#[doc = "I2S TX configure register 1"] +pub mod tx_conf1; +#[doc = "TX_PCM2PDM_CONF (rw) register accessor: I2S TX PCM2PDM configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_pcm2pdm_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_pcm2pdm_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_pcm2pdm_conf`] module"] +pub type TX_PCM2PDM_CONF = crate::Reg; +#[doc = "I2S TX PCM2PDM configuration register"] +pub mod tx_pcm2pdm_conf; +#[doc = "TX_PCM2PDM_CONF1 (rw) register accessor: I2S TX PCM2PDM configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_pcm2pdm_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_pcm2pdm_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_pcm2pdm_conf1`] module"] +pub type TX_PCM2PDM_CONF1 = crate::Reg; +#[doc = "I2S TX PCM2PDM configuration register"] +pub mod tx_pcm2pdm_conf1; +#[doc = "RX_PDM2PCM_CONF (rw) register accessor: I2S RX configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_pdm2pcm_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_pdm2pcm_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_pdm2pcm_conf`] module"] +pub type RX_PDM2PCM_CONF = crate::Reg; +#[doc = "I2S RX configure register"] +pub mod rx_pdm2pcm_conf; +#[doc = "RX_TDM_CTRL (rw) register accessor: I2S TX TDM mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tdm_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tdm_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tdm_ctrl`] module"] +pub type RX_TDM_CTRL = crate::Reg; +#[doc = "I2S TX TDM mode control register"] +pub mod rx_tdm_ctrl; +#[doc = "TX_TDM_CTRL (rw) register accessor: I2S TX TDM mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tdm_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tdm_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_tdm_ctrl`] module"] +pub type TX_TDM_CTRL = crate::Reg; +#[doc = "I2S TX TDM mode control register"] +pub mod tx_tdm_ctrl; +#[doc = "RX_TIMING (rw) register accessor: I2S RX timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_timing::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_timing::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_timing`] module"] +pub type RX_TIMING = crate::Reg; +#[doc = "I2S RX timing control register"] +pub mod rx_timing; +#[doc = "TX_TIMING (rw) register accessor: I2S TX timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_timing::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_timing::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_timing`] module"] +pub type TX_TIMING = crate::Reg; +#[doc = "I2S TX timing control register"] +pub mod tx_timing; +#[doc = "LC_HUNG_CONF (rw) register accessor: I2S HUNG configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_hung_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lc_hung_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lc_hung_conf`] module"] +pub type LC_HUNG_CONF = crate::Reg; +#[doc = "I2S HUNG configure register."] +pub mod lc_hung_conf; +#[doc = "RXEOF_NUM (rw) register accessor: I2S RX data number control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxeof_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxeof_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxeof_num`] module"] +pub type RXEOF_NUM = crate::Reg; +#[doc = "I2S RX data number control register."] +pub mod rxeof_num; +#[doc = "CONF_SIGLE_DATA (rw) register accessor: I2S signal data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf_sigle_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf_sigle_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf_sigle_data`] module"] +pub type CONF_SIGLE_DATA = crate::Reg; +#[doc = "I2S signal data register"] +pub mod conf_sigle_data; +#[doc = "STATE (r) register accessor: I2S TX status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] +pub type STATE = crate::Reg; +#[doc = "I2S TX status register"] +pub mod state; +#[doc = "ETM_CONF (rw) register accessor: I2S ETM configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_conf`] module"] +pub type ETM_CONF = crate::Reg; +#[doc = "I2S ETM configure register"] +pub mod etm_conf; +#[doc = "FIFO_CNT (rw) register accessor: I2S sync counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_cnt`] module"] +pub type FIFO_CNT = crate::Reg; +#[doc = "I2S sync counter register"] +pub mod fifo_cnt; +#[doc = "BCK_CNT (rw) register accessor: I2S sync counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bck_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bck_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bck_cnt`] module"] +pub type BCK_CNT = crate::Reg; +#[doc = "I2S sync counter register"] +pub mod bck_cnt; +#[doc = "CLK_GATE (rw) register accessor: Clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gate`] module"] +pub type CLK_GATE = crate::Reg; +#[doc = "Clock gate register"] +pub mod clk_gate; +#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version control register"] +pub mod date; diff --git a/esp32p4/src/i2s0/bck_cnt.rs b/esp32p4/src/i2s0/bck_cnt.rs new file mode 100644 index 0000000000..363a51aec9 --- /dev/null +++ b/esp32p4/src/i2s0/bck_cnt.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BCK_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `BCK_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `TX_BCK_CNT` reader - tx bck counter value."] +pub type TX_BCK_CNT_R = crate::FieldReader; +#[doc = "Field `TX_BCK_CNT_RST` writer - Set this bit to reset tx bck counter."] +pub type TX_BCK_CNT_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - tx bck counter value."] + #[inline(always)] + pub fn tx_bck_cnt(&self) -> TX_BCK_CNT_R { + TX_BCK_CNT_R::new(self.bits & 0x7fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BCK_CNT") + .field("tx_bck_cnt", &format_args!("{}", self.tx_bck_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - Set this bit to reset tx bck counter."] + #[inline(always)] + #[must_use] + pub fn tx_bck_cnt_rst(&mut self) -> TX_BCK_CNT_RST_W { + TX_BCK_CNT_RST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S sync counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bck_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bck_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BCK_CNT_SPEC; +impl crate::RegisterSpec for BCK_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bck_cnt::R`](R) reader structure"] +impl crate::Readable for BCK_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bck_cnt::W`](W) writer structure"] +impl crate::Writable for BCK_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BCK_CNT to value 0"] +impl crate::Resettable for BCK_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2s0/clk_gate.rs b/esp32p4/src/i2s0/clk_gate.rs new file mode 100644 index 0000000000..d9114e74a6 --- /dev/null +++ b/esp32p4/src/i2s0/clk_gate.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - set this bit to enable clock gate"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - set this bit to enable clock gate"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - set this bit to enable clock gate"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_GATE") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this bit to enable clock gate"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GATE_SPEC; +impl crate::RegisterSpec for CLK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gate::R`](R) reader structure"] +impl crate::Readable for CLK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gate::W`](W) writer structure"] +impl crate::Writable for CLK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_GATE to value 0"] +impl crate::Resettable for CLK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2s0/conf_sigle_data.rs b/esp32p4/src/i2s0/conf_sigle_data.rs new file mode 100644 index 0000000000..4dced54c8d --- /dev/null +++ b/esp32p4/src/i2s0/conf_sigle_data.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CONF_SIGLE_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `CONF_SIGLE_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `SINGLE_DATA` reader - The configured constant channel data to be sent out."] +pub type SINGLE_DATA_R = crate::FieldReader; +#[doc = "Field `SINGLE_DATA` writer - The configured constant channel data to be sent out."] +pub type SINGLE_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The configured constant channel data to be sent out."] + #[inline(always)] + pub fn single_data(&self) -> SINGLE_DATA_R { + SINGLE_DATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF_SIGLE_DATA") + .field( + "single_data", + &format_args!("{}", self.single_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The configured constant channel data to be sent out."] + #[inline(always)] + #[must_use] + pub fn single_data(&mut self) -> SINGLE_DATA_W { + SINGLE_DATA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S signal data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf_sigle_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf_sigle_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SIGLE_DATA_SPEC; +impl crate::RegisterSpec for CONF_SIGLE_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf_sigle_data::R`](R) reader structure"] +impl crate::Readable for CONF_SIGLE_DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf_sigle_data::W`](W) writer structure"] +impl crate::Writable for CONF_SIGLE_DATA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF_SIGLE_DATA to value 0"] +impl crate::Resettable for CONF_SIGLE_DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2s0/date.rs b/esp32p4/src/i2s0/date.rs new file mode 100644 index 0000000000..efde43989b --- /dev/null +++ b/esp32p4/src/i2s0/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - I2S version control register"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - I2S version control register"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - I2S version control register"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - I2S version control register"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_3240"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_3240; +} diff --git a/esp32p4/src/i2s0/etm_conf.rs b/esp32p4/src/i2s0/etm_conf.rs new file mode 100644 index 0000000000..6050fcf30a --- /dev/null +++ b/esp32p4/src/i2s0/etm_conf.rs @@ -0,0 +1,85 @@ +#[doc = "Register `ETM_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `ETM_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_TX_SEND_WORD_NUM` reader - I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num\\[9:0\\], i2s will trigger an etm event."] +pub type ETM_TX_SEND_WORD_NUM_R = crate::FieldReader; +#[doc = "Field `ETM_TX_SEND_WORD_NUM` writer - I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num\\[9:0\\], i2s will trigger an etm event."] +pub type ETM_TX_SEND_WORD_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `ETM_RX_RECEIVE_WORD_NUM` reader - I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num\\[9:0\\], i2s will trigger an etm event."] +pub type ETM_RX_RECEIVE_WORD_NUM_R = crate::FieldReader; +#[doc = "Field `ETM_RX_RECEIVE_WORD_NUM` writer - I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num\\[9:0\\], i2s will trigger an etm event."] +pub type ETM_RX_RECEIVE_WORD_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num\\[9:0\\], i2s will trigger an etm event."] + #[inline(always)] + pub fn etm_tx_send_word_num(&self) -> ETM_TX_SEND_WORD_NUM_R { + ETM_TX_SEND_WORD_NUM_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:19 - I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num\\[9:0\\], i2s will trigger an etm event."] + #[inline(always)] + pub fn etm_rx_receive_word_num(&self) -> ETM_RX_RECEIVE_WORD_NUM_R { + ETM_RX_RECEIVE_WORD_NUM_R::new(((self.bits >> 10) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ETM_CONF") + .field( + "etm_tx_send_word_num", + &format_args!("{}", self.etm_tx_send_word_num().bits()), + ) + .field( + "etm_rx_receive_word_num", + &format_args!("{}", self.etm_rx_receive_word_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num\\[9:0\\], i2s will trigger an etm event."] + #[inline(always)] + #[must_use] + pub fn etm_tx_send_word_num(&mut self) -> ETM_TX_SEND_WORD_NUM_W { + ETM_TX_SEND_WORD_NUM_W::new(self, 0) + } + #[doc = "Bits 10:19 - I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num\\[9:0\\], i2s will trigger an etm event."] + #[inline(always)] + #[must_use] + pub fn etm_rx_receive_word_num(&mut self) -> ETM_RX_RECEIVE_WORD_NUM_W { + ETM_RX_RECEIVE_WORD_NUM_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S ETM configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etm_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etm_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ETM_CONF_SPEC; +impl crate::RegisterSpec for ETM_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`etm_conf::R`](R) reader structure"] +impl crate::Readable for ETM_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etm_conf::W`](W) writer structure"] +impl crate::Writable for ETM_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ETM_CONF to value 0x0001_0040"] +impl crate::Resettable for ETM_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0040; +} diff --git a/esp32p4/src/i2s0/fifo_cnt.rs b/esp32p4/src/i2s0/fifo_cnt.rs new file mode 100644 index 0000000000..87304e190b --- /dev/null +++ b/esp32p4/src/i2s0/fifo_cnt.rs @@ -0,0 +1,66 @@ +#[doc = "Register `FIFO_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `TX_FIFO_CNT` reader - tx fifo counter value."] +pub type TX_FIFO_CNT_R = crate::FieldReader; +#[doc = "Field `TX_FIFO_CNT_RST` writer - Set this bit to reset tx fifo counter."] +pub type TX_FIFO_CNT_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - tx fifo counter value."] + #[inline(always)] + pub fn tx_fifo_cnt(&self) -> TX_FIFO_CNT_R { + TX_FIFO_CNT_R::new(self.bits & 0x7fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO_CNT") + .field( + "tx_fifo_cnt", + &format_args!("{}", self.tx_fifo_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - Set this bit to reset tx fifo counter."] + #[inline(always)] + #[must_use] + pub fn tx_fifo_cnt_rst(&mut self) -> TX_FIFO_CNT_RST_W { + TX_FIFO_CNT_RST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S sync counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_CNT_SPEC; +impl crate::RegisterSpec for FIFO_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_cnt::R`](R) reader structure"] +impl crate::Readable for FIFO_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo_cnt::W`](W) writer structure"] +impl crate::Writable for FIFO_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIFO_CNT to value 0"] +impl crate::Resettable for FIFO_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2s0/int_clr.rs b/esp32p4/src/i2s0/int_clr.rs new file mode 100644 index 0000000000..c9e0090229 --- /dev/null +++ b/esp32p4/src/i2s0/int_clr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RX_DONE_INT_CLR` writer - Set this bit to clear the i2s_rx_done_int interrupt"] +pub type RX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DONE_INT_CLR` writer - Set this bit to clear the i2s_tx_done_int interrupt"] +pub type TX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_HUNG_INT_CLR` writer - Set this bit to clear the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_HUNG_INT_CLR` writer - Set this bit to clear the i2s_tx_hung_int interrupt"] +pub type TX_HUNG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the i2s_rx_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_done_int_clr(&mut self) -> RX_DONE_INT_CLR_W { + RX_DONE_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the i2s_tx_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn tx_done_int_clr(&mut self) -> TX_DONE_INT_CLR_W { + TX_DONE_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the i2s_rx_hung_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_hung_int_clr(&mut self) -> RX_HUNG_INT_CLR_W { + RX_HUNG_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the i2s_tx_hung_int interrupt"] + #[inline(always)] + #[must_use] + pub fn tx_hung_int_clr(&mut self) -> TX_HUNG_INT_CLR_W { + TX_HUNG_INT_CLR_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2s0/int_ena.rs b/esp32p4/src/i2s0/int_ena.rs new file mode 100644 index 0000000000..5af33727ac --- /dev/null +++ b/esp32p4/src/i2s0/int_ena.rs @@ -0,0 +1,123 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `RX_DONE_INT_ENA` reader - The interrupt enable bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `RX_DONE_INT_ENA` writer - The interrupt enable bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DONE_INT_ENA` reader - The interrupt enable bit for the i2s_tx_done_int interrupt"] +pub type TX_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_DONE_INT_ENA` writer - The interrupt enable bit for the i2s_tx_done_int interrupt"] +pub type TX_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_HUNG_INT_ENA` reader - The interrupt enable bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_INT_ENA_R = crate::BitReader; +#[doc = "Field `RX_HUNG_INT_ENA` writer - The interrupt enable bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_HUNG_INT_ENA` reader - The interrupt enable bit for the i2s_tx_hung_int interrupt"] +pub type TX_HUNG_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_HUNG_INT_ENA` writer - The interrupt enable bit for the i2s_tx_hung_int interrupt"] +pub type TX_HUNG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"] + #[inline(always)] + pub fn rx_done_int_ena(&self) -> RX_DONE_INT_ENA_R { + RX_DONE_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the i2s_tx_done_int interrupt"] + #[inline(always)] + pub fn tx_done_int_ena(&self) -> TX_DONE_INT_ENA_R { + TX_DONE_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the i2s_rx_hung_int interrupt"] + #[inline(always)] + pub fn rx_hung_int_ena(&self) -> RX_HUNG_INT_ENA_R { + RX_HUNG_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the i2s_tx_hung_int interrupt"] + #[inline(always)] + pub fn tx_hung_int_ena(&self) -> TX_HUNG_INT_ENA_R { + TX_HUNG_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "rx_done_int_ena", + &format_args!("{}", self.rx_done_int_ena().bit()), + ) + .field( + "tx_done_int_ena", + &format_args!("{}", self.tx_done_int_ena().bit()), + ) + .field( + "rx_hung_int_ena", + &format_args!("{}", self.rx_hung_int_ena().bit()), + ) + .field( + "tx_hung_int_ena", + &format_args!("{}", self.tx_hung_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_done_int_ena(&mut self) -> RX_DONE_INT_ENA_W { + RX_DONE_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the i2s_tx_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn tx_done_int_ena(&mut self) -> TX_DONE_INT_ENA_W { + TX_DONE_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the i2s_rx_hung_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_hung_int_ena(&mut self) -> RX_HUNG_INT_ENA_W { + RX_HUNG_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the i2s_tx_hung_int interrupt"] + #[inline(always)] + #[must_use] + pub fn tx_hung_int_ena(&mut self) -> TX_HUNG_INT_ENA_W { + TX_HUNG_INT_ENA_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2s0/int_raw.rs b/esp32p4/src/i2s0/int_raw.rs new file mode 100644 index 0000000000..973ab8db7e --- /dev/null +++ b/esp32p4/src/i2s0/int_raw.rs @@ -0,0 +1,72 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `RX_DONE_INT_RAW` reader - The raw interrupt status bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_DONE_INT_RAW` reader - The raw interrupt status bit for the i2s_tx_done_int interrupt"] +pub type TX_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_HUNG_INT_RAW` reader - The raw interrupt status bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_HUNG_INT_RAW` reader - The raw interrupt status bit for the i2s_tx_hung_int interrupt"] +pub type TX_HUNG_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the i2s_rx_done_int interrupt"] + #[inline(always)] + pub fn rx_done_int_raw(&self) -> RX_DONE_INT_RAW_R { + RX_DONE_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the i2s_tx_done_int interrupt"] + #[inline(always)] + pub fn tx_done_int_raw(&self) -> TX_DONE_INT_RAW_R { + TX_DONE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the i2s_rx_hung_int interrupt"] + #[inline(always)] + pub fn rx_hung_int_raw(&self) -> RX_HUNG_INT_RAW_R { + RX_HUNG_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the i2s_tx_hung_int interrupt"] + #[inline(always)] + pub fn tx_hung_int_raw(&self) -> TX_HUNG_INT_RAW_R { + TX_HUNG_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "rx_done_int_raw", + &format_args!("{}", self.rx_done_int_raw().bit()), + ) + .field( + "tx_done_int_raw", + &format_args!("{}", self.tx_done_int_raw().bit()), + ) + .field( + "rx_hung_int_raw", + &format_args!("{}", self.rx_hung_int_raw().bit()), + ) + .field( + "tx_hung_int_raw", + &format_args!("{}", self.tx_hung_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2s0/int_st.rs b/esp32p4/src/i2s0/int_st.rs new file mode 100644 index 0000000000..7684701fe6 --- /dev/null +++ b/esp32p4/src/i2s0/int_st.rs @@ -0,0 +1,72 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `RX_DONE_INT_ST` reader - The masked interrupt status bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_DONE_INT_ST` reader - The masked interrupt status bit for the i2s_tx_done_int interrupt"] +pub type TX_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_HUNG_INT_ST` reader - The masked interrupt status bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_HUNG_INT_ST` reader - The masked interrupt status bit for the i2s_tx_hung_int interrupt"] +pub type TX_HUNG_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status bit for the i2s_rx_done_int interrupt"] + #[inline(always)] + pub fn rx_done_int_st(&self) -> RX_DONE_INT_ST_R { + RX_DONE_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status bit for the i2s_tx_done_int interrupt"] + #[inline(always)] + pub fn tx_done_int_st(&self) -> TX_DONE_INT_ST_R { + TX_DONE_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status bit for the i2s_rx_hung_int interrupt"] + #[inline(always)] + pub fn rx_hung_int_st(&self) -> RX_HUNG_INT_ST_R { + RX_HUNG_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The masked interrupt status bit for the i2s_tx_hung_int interrupt"] + #[inline(always)] + pub fn tx_hung_int_st(&self) -> TX_HUNG_INT_ST_R { + TX_HUNG_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "rx_done_int_st", + &format_args!("{}", self.rx_done_int_st().bit()), + ) + .field( + "tx_done_int_st", + &format_args!("{}", self.tx_done_int_st().bit()), + ) + .field( + "rx_hung_int_st", + &format_args!("{}", self.rx_hung_int_st().bit()), + ) + .field( + "tx_hung_int_st", + &format_args!("{}", self.tx_hung_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2s0/lc_hung_conf.rs b/esp32p4/src/i2s0/lc_hung_conf.rs new file mode 100644 index 0000000000..b10dfd36c9 --- /dev/null +++ b/esp32p4/src/i2s0/lc_hung_conf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `LC_HUNG_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `LC_HUNG_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `LC_FIFO_TIMEOUT` reader - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"] +pub type LC_FIFO_TIMEOUT_R = crate::FieldReader; +#[doc = "Field `LC_FIFO_TIMEOUT` writer - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"] +pub type LC_FIFO_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LC_FIFO_TIMEOUT_SHIFT` reader - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"] +pub type LC_FIFO_TIMEOUT_SHIFT_R = crate::FieldReader; +#[doc = "Field `LC_FIFO_TIMEOUT_SHIFT` writer - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"] +pub type LC_FIFO_TIMEOUT_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LC_FIFO_TIMEOUT_ENA` reader - The enable bit for FIFO timeout"] +pub type LC_FIFO_TIMEOUT_ENA_R = crate::BitReader; +#[doc = "Field `LC_FIFO_TIMEOUT_ENA` writer - The enable bit for FIFO timeout"] +pub type LC_FIFO_TIMEOUT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"] + #[inline(always)] + pub fn lc_fifo_timeout(&self) -> LC_FIFO_TIMEOUT_R { + LC_FIFO_TIMEOUT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"] + #[inline(always)] + pub fn lc_fifo_timeout_shift(&self) -> LC_FIFO_TIMEOUT_SHIFT_R { + LC_FIFO_TIMEOUT_SHIFT_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - The enable bit for FIFO timeout"] + #[inline(always)] + pub fn lc_fifo_timeout_ena(&self) -> LC_FIFO_TIMEOUT_ENA_R { + LC_FIFO_TIMEOUT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LC_HUNG_CONF") + .field( + "lc_fifo_timeout", + &format_args!("{}", self.lc_fifo_timeout().bits()), + ) + .field( + "lc_fifo_timeout_shift", + &format_args!("{}", self.lc_fifo_timeout_shift().bits()), + ) + .field( + "lc_fifo_timeout_ena", + &format_args!("{}", self.lc_fifo_timeout_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"] + #[inline(always)] + #[must_use] + pub fn lc_fifo_timeout(&mut self) -> LC_FIFO_TIMEOUT_W { + LC_FIFO_TIMEOUT_W::new(self, 0) + } + #[doc = "Bits 8:10 - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"] + #[inline(always)] + #[must_use] + pub fn lc_fifo_timeout_shift(&mut self) -> LC_FIFO_TIMEOUT_SHIFT_W { + LC_FIFO_TIMEOUT_SHIFT_W::new(self, 8) + } + #[doc = "Bit 11 - The enable bit for FIFO timeout"] + #[inline(always)] + #[must_use] + pub fn lc_fifo_timeout_ena(&mut self) -> LC_FIFO_TIMEOUT_ENA_W { + LC_FIFO_TIMEOUT_ENA_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S HUNG configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_hung_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lc_hung_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LC_HUNG_CONF_SPEC; +impl crate::RegisterSpec for LC_HUNG_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lc_hung_conf::R`](R) reader structure"] +impl crate::Readable for LC_HUNG_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lc_hung_conf::W`](W) writer structure"] +impl crate::Writable for LC_HUNG_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LC_HUNG_CONF to value 0x0810"] +impl crate::Resettable for LC_HUNG_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0810; +} diff --git a/esp32p4/src/i2s0/rx_conf.rs b/esp32p4/src/i2s0/rx_conf.rs new file mode 100644 index 0000000000..f67cf1f218 --- /dev/null +++ b/esp32p4/src/i2s0/rx_conf.rs @@ -0,0 +1,371 @@ +#[doc = "Register `RX_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `RX_RESET` writer - Set this bit to reset receiver"] +pub type RX_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFO_RESET` writer - Set this bit to reset Rx AFIFO"] +pub type RX_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_START` reader - Set this bit to start receiving data"] +pub type RX_START_R = crate::BitReader; +#[doc = "Field `RX_START` writer - Set this bit to start receiving data"] +pub type RX_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_SLAVE_MOD` reader - Set this bit to enable slave receiver mode"] +pub type RX_SLAVE_MOD_R = crate::BitReader; +#[doc = "Field `RX_SLAVE_MOD` writer - Set this bit to enable slave receiver mode"] +pub type RX_SLAVE_MOD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_STOP_MODE` reader - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."] +pub type RX_STOP_MODE_R = crate::FieldReader; +#[doc = "Field `RX_STOP_MODE` writer - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."] +pub type RX_STOP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_MONO` reader - Set this bit to enable receiver in mono mode"] +pub type RX_MONO_R = crate::BitReader; +#[doc = "Field `RX_MONO` writer - Set this bit to enable receiver in mono mode"] +pub type RX_MONO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_BIG_ENDIAN` reader - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] +pub type RX_BIG_ENDIAN_R = crate::BitReader; +#[doc = "Field `RX_BIG_ENDIAN` writer - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] +pub type RX_BIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_UPDATE` reader - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."] +pub type RX_UPDATE_R = crate::BitReader; +#[doc = "Field `RX_UPDATE` writer - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."] +pub type RX_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_MONO_FST_VLD` reader - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."] +pub type RX_MONO_FST_VLD_R = crate::BitReader; +#[doc = "Field `RX_MONO_FST_VLD` writer - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."] +pub type RX_MONO_FST_VLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PCM_CONF` reader - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] +pub type RX_PCM_CONF_R = crate::FieldReader; +#[doc = "Field `RX_PCM_CONF` writer - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] +pub type RX_PCM_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_PCM_BYPASS` reader - Set this bit to bypass Compress/Decompress module for received data."] +pub type RX_PCM_BYPASS_R = crate::BitReader; +#[doc = "Field `RX_PCM_BYPASS` writer - Set this bit to bypass Compress/Decompress module for received data."] +pub type RX_PCM_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_MSB_SHIFT` reader - Set this bit to enable receiver in Phillips standard mode"] +pub type RX_MSB_SHIFT_R = crate::BitReader; +#[doc = "Field `RX_MSB_SHIFT` writer - Set this bit to enable receiver in Phillips standard mode"] +pub type RX_MSB_SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_LEFT_ALIGN` reader - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."] +pub type RX_LEFT_ALIGN_R = crate::BitReader; +#[doc = "Field `RX_LEFT_ALIGN` writer - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."] +pub type RX_LEFT_ALIGN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_24_FILL_EN` reader - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."] +pub type RX_24_FILL_EN_R = crate::BitReader; +#[doc = "Field `RX_24_FILL_EN` writer - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."] +pub type RX_24_FILL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_WS_IDLE_POL` reader - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."] +pub type RX_WS_IDLE_POL_R = crate::BitReader; +#[doc = "Field `RX_WS_IDLE_POL` writer - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."] +pub type RX_WS_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_BIT_ORDER` reader - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."] +pub type RX_BIT_ORDER_R = crate::BitReader; +#[doc = "Field `RX_BIT_ORDER` writer - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."] +pub type RX_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_EN` reader - 1: Enable I2S TDM Rx mode . 0: Disable."] +pub type RX_TDM_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_EN` writer - 1: Enable I2S TDM Rx mode . 0: Disable."] +pub type RX_TDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PDM_EN` reader - 1: Enable I2S PDM Rx mode . 0: Disable."] +pub type RX_PDM_EN_R = crate::BitReader; +#[doc = "Field `RX_PDM_EN` writer - 1: Enable I2S PDM Rx mode . 0: Disable."] +pub type RX_PDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_BCK_DIV_NUM` reader - Bit clock configuration bits in receiver mode."] +pub type RX_BCK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `RX_BCK_DIV_NUM` writer - Bit clock configuration bits in receiver mode."] +pub type RX_BCK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 2 - Set this bit to start receiving data"] + #[inline(always)] + pub fn rx_start(&self) -> RX_START_R { + RX_START_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to enable slave receiver mode"] + #[inline(always)] + pub fn rx_slave_mod(&self) -> RX_SLAVE_MOD_R { + RX_SLAVE_MOD_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."] + #[inline(always)] + pub fn rx_stop_mode(&self) -> RX_STOP_MODE_R { + RX_STOP_MODE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Set this bit to enable receiver in mono mode"] + #[inline(always)] + pub fn rx_mono(&self) -> RX_MONO_R { + RX_MONO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] + #[inline(always)] + pub fn rx_big_endian(&self) -> RX_BIG_ENDIAN_R { + RX_BIG_ENDIAN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."] + #[inline(always)] + pub fn rx_update(&self) -> RX_UPDATE_R { + RX_UPDATE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."] + #[inline(always)] + pub fn rx_mono_fst_vld(&self) -> RX_MONO_FST_VLD_R { + RX_MONO_FST_VLD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] + #[inline(always)] + pub fn rx_pcm_conf(&self) -> RX_PCM_CONF_R { + RX_PCM_CONF_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for received data."] + #[inline(always)] + pub fn rx_pcm_bypass(&self) -> RX_PCM_BYPASS_R { + RX_PCM_BYPASS_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set this bit to enable receiver in Phillips standard mode"] + #[inline(always)] + pub fn rx_msb_shift(&self) -> RX_MSB_SHIFT_R { + RX_MSB_SHIFT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."] + #[inline(always)] + pub fn rx_left_align(&self) -> RX_LEFT_ALIGN_R { + RX_LEFT_ALIGN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."] + #[inline(always)] + pub fn rx_24_fill_en(&self) -> RX_24_FILL_EN_R { + RX_24_FILL_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."] + #[inline(always)] + pub fn rx_ws_idle_pol(&self) -> RX_WS_IDLE_POL_R { + RX_WS_IDLE_POL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."] + #[inline(always)] + pub fn rx_bit_order(&self) -> RX_BIT_ORDER_R { + RX_BIT_ORDER_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - 1: Enable I2S TDM Rx mode . 0: Disable."] + #[inline(always)] + pub fn rx_tdm_en(&self) -> RX_TDM_EN_R { + RX_TDM_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - 1: Enable I2S PDM Rx mode . 0: Disable."] + #[inline(always)] + pub fn rx_pdm_en(&self) -> RX_PDM_EN_R { + RX_PDM_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:26 - Bit clock configuration bits in receiver mode."] + #[inline(always)] + pub fn rx_bck_div_num(&self) -> RX_BCK_DIV_NUM_R { + RX_BCK_DIV_NUM_R::new(((self.bits >> 21) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CONF") + .field("rx_start", &format_args!("{}", self.rx_start().bit())) + .field( + "rx_slave_mod", + &format_args!("{}", self.rx_slave_mod().bit()), + ) + .field( + "rx_stop_mode", + &format_args!("{}", self.rx_stop_mode().bits()), + ) + .field("rx_mono", &format_args!("{}", self.rx_mono().bit())) + .field( + "rx_big_endian", + &format_args!("{}", self.rx_big_endian().bit()), + ) + .field("rx_update", &format_args!("{}", self.rx_update().bit())) + .field( + "rx_mono_fst_vld", + &format_args!("{}", self.rx_mono_fst_vld().bit()), + ) + .field( + "rx_pcm_conf", + &format_args!("{}", self.rx_pcm_conf().bits()), + ) + .field( + "rx_pcm_bypass", + &format_args!("{}", self.rx_pcm_bypass().bit()), + ) + .field( + "rx_msb_shift", + &format_args!("{}", self.rx_msb_shift().bit()), + ) + .field( + "rx_left_align", + &format_args!("{}", self.rx_left_align().bit()), + ) + .field( + "rx_24_fill_en", + &format_args!("{}", self.rx_24_fill_en().bit()), + ) + .field( + "rx_ws_idle_pol", + &format_args!("{}", self.rx_ws_idle_pol().bit()), + ) + .field( + "rx_bit_order", + &format_args!("{}", self.rx_bit_order().bit()), + ) + .field("rx_tdm_en", &format_args!("{}", self.rx_tdm_en().bit())) + .field("rx_pdm_en", &format_args!("{}", self.rx_pdm_en().bit())) + .field( + "rx_bck_div_num", + &format_args!("{}", self.rx_bck_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to reset receiver"] + #[inline(always)] + #[must_use] + pub fn rx_reset(&mut self) -> RX_RESET_W { + RX_RESET_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to reset Rx AFIFO"] + #[inline(always)] + #[must_use] + pub fn rx_fifo_reset(&mut self) -> RX_FIFO_RESET_W { + RX_FIFO_RESET_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to start receiving data"] + #[inline(always)] + #[must_use] + pub fn rx_start(&mut self) -> RX_START_W { + RX_START_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to enable slave receiver mode"] + #[inline(always)] + #[must_use] + pub fn rx_slave_mod(&mut self) -> RX_SLAVE_MOD_W { + RX_SLAVE_MOD_W::new(self, 3) + } + #[doc = "Bits 4:5 - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."] + #[inline(always)] + #[must_use] + pub fn rx_stop_mode(&mut self) -> RX_STOP_MODE_W { + RX_STOP_MODE_W::new(self, 4) + } + #[doc = "Bit 6 - Set this bit to enable receiver in mono mode"] + #[inline(always)] + #[must_use] + pub fn rx_mono(&mut self) -> RX_MONO_W { + RX_MONO_W::new(self, 6) + } + #[doc = "Bit 7 - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] + #[inline(always)] + #[must_use] + pub fn rx_big_endian(&mut self) -> RX_BIG_ENDIAN_W { + RX_BIG_ENDIAN_W::new(self, 7) + } + #[doc = "Bit 8 - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."] + #[inline(always)] + #[must_use] + pub fn rx_update(&mut self) -> RX_UPDATE_W { + RX_UPDATE_W::new(self, 8) + } + #[doc = "Bit 9 - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."] + #[inline(always)] + #[must_use] + pub fn rx_mono_fst_vld(&mut self) -> RX_MONO_FST_VLD_W { + RX_MONO_FST_VLD_W::new(self, 9) + } + #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] + #[inline(always)] + #[must_use] + pub fn rx_pcm_conf(&mut self) -> RX_PCM_CONF_W { + RX_PCM_CONF_W::new(self, 10) + } + #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for received data."] + #[inline(always)] + #[must_use] + pub fn rx_pcm_bypass(&mut self) -> RX_PCM_BYPASS_W { + RX_PCM_BYPASS_W::new(self, 12) + } + #[doc = "Bit 13 - Set this bit to enable receiver in Phillips standard mode"] + #[inline(always)] + #[must_use] + pub fn rx_msb_shift(&mut self) -> RX_MSB_SHIFT_W { + RX_MSB_SHIFT_W::new(self, 13) + } + #[doc = "Bit 15 - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."] + #[inline(always)] + #[must_use] + pub fn rx_left_align(&mut self) -> RX_LEFT_ALIGN_W { + RX_LEFT_ALIGN_W::new(self, 15) + } + #[doc = "Bit 16 - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."] + #[inline(always)] + #[must_use] + pub fn rx_24_fill_en(&mut self) -> RX_24_FILL_EN_W { + RX_24_FILL_EN_W::new(self, 16) + } + #[doc = "Bit 17 - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."] + #[inline(always)] + #[must_use] + pub fn rx_ws_idle_pol(&mut self) -> RX_WS_IDLE_POL_W { + RX_WS_IDLE_POL_W::new(self, 17) + } + #[doc = "Bit 18 - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."] + #[inline(always)] + #[must_use] + pub fn rx_bit_order(&mut self) -> RX_BIT_ORDER_W { + RX_BIT_ORDER_W::new(self, 18) + } + #[doc = "Bit 19 - 1: Enable I2S TDM Rx mode . 0: Disable."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_en(&mut self) -> RX_TDM_EN_W { + RX_TDM_EN_W::new(self, 19) + } + #[doc = "Bit 20 - 1: Enable I2S PDM Rx mode . 0: Disable."] + #[inline(always)] + #[must_use] + pub fn rx_pdm_en(&mut self) -> RX_PDM_EN_W { + RX_PDM_EN_W::new(self, 20) + } + #[doc = "Bits 21:26 - Bit clock configuration bits in receiver mode."] + #[inline(always)] + #[must_use] + pub fn rx_bck_div_num(&mut self) -> RX_BCK_DIV_NUM_W { + RX_BCK_DIV_NUM_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S RX configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CONF_SPEC; +impl crate::RegisterSpec for RX_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_conf::R`](R) reader structure"] +impl crate::Readable for RX_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_conf::W`](W) writer structure"] +impl crate::Writable for RX_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CONF to value 0x00c0_b600"] +impl crate::Resettable for RX_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x00c0_b600; +} diff --git a/esp32p4/src/i2s0/rx_conf1.rs b/esp32p4/src/i2s0/rx_conf1.rs new file mode 100644 index 0000000000..733280cdc2 --- /dev/null +++ b/esp32p4/src/i2s0/rx_conf1.rs @@ -0,0 +1,123 @@ +#[doc = "Register `RX_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `RX_TDM_WS_WIDTH` reader - The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"] +pub type RX_TDM_WS_WIDTH_R = crate::FieldReader; +#[doc = "Field `RX_TDM_WS_WIDTH` writer - The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"] +pub type RX_TDM_WS_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `RX_BITS_MOD` reader - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] +pub type RX_BITS_MOD_R = crate::FieldReader; +#[doc = "Field `RX_BITS_MOD` writer - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] +pub type RX_BITS_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `RX_HALF_SAMPLE_BITS` reader - I2S Rx half sample bits -1."] +pub type RX_HALF_SAMPLE_BITS_R = crate::FieldReader; +#[doc = "Field `RX_HALF_SAMPLE_BITS` writer - I2S Rx half sample bits -1."] +pub type RX_HALF_SAMPLE_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RX_TDM_CHAN_BITS` reader - The Rx bit number for each channel minus 1in TDM mode."] +pub type RX_TDM_CHAN_BITS_R = crate::FieldReader; +#[doc = "Field `RX_TDM_CHAN_BITS` writer - The Rx bit number for each channel minus 1in TDM mode."] +pub type RX_TDM_CHAN_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:8 - The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"] + #[inline(always)] + pub fn rx_tdm_ws_width(&self) -> RX_TDM_WS_WIDTH_R { + RX_TDM_WS_WIDTH_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 14:18 - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] + #[inline(always)] + pub fn rx_bits_mod(&self) -> RX_BITS_MOD_R { + RX_BITS_MOD_R::new(((self.bits >> 14) & 0x1f) as u8) + } + #[doc = "Bits 19:26 - I2S Rx half sample bits -1."] + #[inline(always)] + pub fn rx_half_sample_bits(&self) -> RX_HALF_SAMPLE_BITS_R { + RX_HALF_SAMPLE_BITS_R::new(((self.bits >> 19) & 0xff) as u8) + } + #[doc = "Bits 27:31 - The Rx bit number for each channel minus 1in TDM mode."] + #[inline(always)] + pub fn rx_tdm_chan_bits(&self) -> RX_TDM_CHAN_BITS_R { + RX_TDM_CHAN_BITS_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CONF1") + .field( + "rx_tdm_ws_width", + &format_args!("{}", self.rx_tdm_ws_width().bits()), + ) + .field( + "rx_bits_mod", + &format_args!("{}", self.rx_bits_mod().bits()), + ) + .field( + "rx_half_sample_bits", + &format_args!("{}", self.rx_half_sample_bits().bits()), + ) + .field( + "rx_tdm_chan_bits", + &format_args!("{}", self.rx_tdm_chan_bits().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"] + #[inline(always)] + #[must_use] + pub fn rx_tdm_ws_width(&mut self) -> RX_TDM_WS_WIDTH_W { + RX_TDM_WS_WIDTH_W::new(self, 0) + } + #[doc = "Bits 14:18 - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] + #[inline(always)] + #[must_use] + pub fn rx_bits_mod(&mut self) -> RX_BITS_MOD_W { + RX_BITS_MOD_W::new(self, 14) + } + #[doc = "Bits 19:26 - I2S Rx half sample bits -1."] + #[inline(always)] + #[must_use] + pub fn rx_half_sample_bits(&mut self) -> RX_HALF_SAMPLE_BITS_W { + RX_HALF_SAMPLE_BITS_W::new(self, 19) + } + #[doc = "Bits 27:31 - The Rx bit number for each channel minus 1in TDM mode."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_chan_bits(&mut self) -> RX_TDM_CHAN_BITS_W { + RX_TDM_CHAN_BITS_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S RX configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CONF1_SPEC; +impl crate::RegisterSpec for RX_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_conf1::R`](R) reader structure"] +impl crate::Readable for RX_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_conf1::W`](W) writer structure"] +impl crate::Writable for RX_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CONF1 to value 0x787b_c000"] +impl crate::Resettable for RX_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x787b_c000; +} diff --git a/esp32p4/src/i2s0/rx_pdm2pcm_conf.rs b/esp32p4/src/i2s0/rx_pdm2pcm_conf.rs new file mode 100644 index 0000000000..7961168c3a --- /dev/null +++ b/esp32p4/src/i2s0/rx_pdm2pcm_conf.rs @@ -0,0 +1,161 @@ +#[doc = "Register `RX_PDM2PCM_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `RX_PDM2PCM_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `RX_PDM2PCM_EN` reader - 1: Enable PDM2PCM RX mode. 0: DIsable."] +pub type RX_PDM2PCM_EN_R = crate::BitReader; +#[doc = "Field `RX_PDM2PCM_EN` writer - 1: Enable PDM2PCM RX mode. 0: DIsable."] +pub type RX_PDM2PCM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PDM_SINC_DSR_16_EN` reader - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."] +pub type RX_PDM_SINC_DSR_16_EN_R = crate::BitReader; +#[doc = "Field `RX_PDM_SINC_DSR_16_EN` writer - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."] +pub type RX_PDM_SINC_DSR_16_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PDM2PCM_AMPLIFY_NUM` reader - Configure PDM RX amplify number."] +pub type RX_PDM2PCM_AMPLIFY_NUM_R = crate::FieldReader; +#[doc = "Field `RX_PDM2PCM_AMPLIFY_NUM` writer - Configure PDM RX amplify number."] +pub type RX_PDM2PCM_AMPLIFY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RX_PDM_HP_BYPASS` reader - I2S PDM RX bypass hp filter or not."] +pub type RX_PDM_HP_BYPASS_R = crate::BitReader; +#[doc = "Field `RX_PDM_HP_BYPASS` writer - I2S PDM RX bypass hp filter or not."] +pub type RX_PDM_HP_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_IIR_HP_MULT12_5` reader - The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5\\[2:0\\])"] +pub type RX_IIR_HP_MULT12_5_R = crate::FieldReader; +#[doc = "Field `RX_IIR_HP_MULT12_5` writer - The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5\\[2:0\\])"] +pub type RX_IIR_HP_MULT12_5_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `RX_IIR_HP_MULT12_0` reader - The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0\\[2:0\\])"] +pub type RX_IIR_HP_MULT12_0_R = crate::FieldReader; +#[doc = "Field `RX_IIR_HP_MULT12_0` writer - The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0\\[2:0\\])"] +pub type RX_IIR_HP_MULT12_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 19 - 1: Enable PDM2PCM RX mode. 0: DIsable."] + #[inline(always)] + pub fn rx_pdm2pcm_en(&self) -> RX_PDM2PCM_EN_R { + RX_PDM2PCM_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."] + #[inline(always)] + pub fn rx_pdm_sinc_dsr_16_en(&self) -> RX_PDM_SINC_DSR_16_EN_R { + RX_PDM_SINC_DSR_16_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:24 - Configure PDM RX amplify number."] + #[inline(always)] + pub fn rx_pdm2pcm_amplify_num(&self) -> RX_PDM2PCM_AMPLIFY_NUM_R { + RX_PDM2PCM_AMPLIFY_NUM_R::new(((self.bits >> 21) & 0x0f) as u8) + } + #[doc = "Bit 25 - I2S PDM RX bypass hp filter or not."] + #[inline(always)] + pub fn rx_pdm_hp_bypass(&self) -> RX_PDM_HP_BYPASS_R { + RX_PDM_HP_BYPASS_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 26:28 - The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5\\[2:0\\])"] + #[inline(always)] + pub fn rx_iir_hp_mult12_5(&self) -> RX_IIR_HP_MULT12_5_R { + RX_IIR_HP_MULT12_5_R::new(((self.bits >> 26) & 7) as u8) + } + #[doc = "Bits 29:31 - The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0\\[2:0\\])"] + #[inline(always)] + pub fn rx_iir_hp_mult12_0(&self) -> RX_IIR_HP_MULT12_0_R { + RX_IIR_HP_MULT12_0_R::new(((self.bits >> 29) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_PDM2PCM_CONF") + .field( + "rx_pdm2pcm_en", + &format_args!("{}", self.rx_pdm2pcm_en().bit()), + ) + .field( + "rx_pdm_sinc_dsr_16_en", + &format_args!("{}", self.rx_pdm_sinc_dsr_16_en().bit()), + ) + .field( + "rx_pdm2pcm_amplify_num", + &format_args!("{}", self.rx_pdm2pcm_amplify_num().bits()), + ) + .field( + "rx_pdm_hp_bypass", + &format_args!("{}", self.rx_pdm_hp_bypass().bit()), + ) + .field( + "rx_iir_hp_mult12_5", + &format_args!("{}", self.rx_iir_hp_mult12_5().bits()), + ) + .field( + "rx_iir_hp_mult12_0", + &format_args!("{}", self.rx_iir_hp_mult12_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 19 - 1: Enable PDM2PCM RX mode. 0: DIsable."] + #[inline(always)] + #[must_use] + pub fn rx_pdm2pcm_en(&mut self) -> RX_PDM2PCM_EN_W { + RX_PDM2PCM_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."] + #[inline(always)] + #[must_use] + pub fn rx_pdm_sinc_dsr_16_en(&mut self) -> RX_PDM_SINC_DSR_16_EN_W { + RX_PDM_SINC_DSR_16_EN_W::new(self, 20) + } + #[doc = "Bits 21:24 - Configure PDM RX amplify number."] + #[inline(always)] + #[must_use] + pub fn rx_pdm2pcm_amplify_num(&mut self) -> RX_PDM2PCM_AMPLIFY_NUM_W { + RX_PDM2PCM_AMPLIFY_NUM_W::new(self, 21) + } + #[doc = "Bit 25 - I2S PDM RX bypass hp filter or not."] + #[inline(always)] + #[must_use] + pub fn rx_pdm_hp_bypass(&mut self) -> RX_PDM_HP_BYPASS_W { + RX_PDM_HP_BYPASS_W::new(self, 25) + } + #[doc = "Bits 26:28 - The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5\\[2:0\\])"] + #[inline(always)] + #[must_use] + pub fn rx_iir_hp_mult12_5(&mut self) -> RX_IIR_HP_MULT12_5_W { + RX_IIR_HP_MULT12_5_W::new(self, 26) + } + #[doc = "Bits 29:31 - The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0\\[2:0\\])"] + #[inline(always)] + #[must_use] + pub fn rx_iir_hp_mult12_0(&mut self) -> RX_IIR_HP_MULT12_0_W { + RX_IIR_HP_MULT12_0_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S RX configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_pdm2pcm_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_pdm2pcm_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_PDM2PCM_CONF_SPEC; +impl crate::RegisterSpec for RX_PDM2PCM_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_pdm2pcm_conf::R`](R) reader structure"] +impl crate::Readable for RX_PDM2PCM_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_pdm2pcm_conf::W`](W) writer structure"] +impl crate::Writable for RX_PDM2PCM_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_PDM2PCM_CONF to value 0xf820_0000"] +impl crate::Resettable for RX_PDM2PCM_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0xf820_0000; +} diff --git a/esp32p4/src/i2s0/rx_tdm_ctrl.rs b/esp32p4/src/i2s0/rx_tdm_ctrl.rs new file mode 100644 index 0000000000..4ab1026b19 --- /dev/null +++ b/esp32p4/src/i2s0/rx_tdm_ctrl.rs @@ -0,0 +1,370 @@ +#[doc = "Register `RX_TDM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `RX_TDM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `RX_TDM_PDM_CHAN0_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN0_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_PDM_CHAN0_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_PDM_CHAN1_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN1_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_PDM_CHAN1_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_PDM_CHAN2_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN2_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_PDM_CHAN2_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_PDM_CHAN3_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN3_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_PDM_CHAN3_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_PDM_CHAN4_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN4_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_PDM_CHAN4_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_PDM_CHAN5_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN5_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_PDM_CHAN5_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN5_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_PDM_CHAN6_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN6_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_PDM_CHAN6_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN6_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_PDM_CHAN7_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN7_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_PDM_CHAN7_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN7_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_CHAN8_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN8_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_CHAN8_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN8_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_CHAN9_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN9_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_CHAN9_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN9_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_CHAN10_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN10_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_CHAN10_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN10_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_CHAN11_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN11_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_CHAN11_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN11_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_CHAN12_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN12_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_CHAN12_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN12_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_CHAN13_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN13_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_CHAN13_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN13_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_CHAN14_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN14_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_CHAN14_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN14_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_CHAN15_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN15_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_CHAN15_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_CHAN15_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_TOT_CHAN_NUM` reader - The total channel number of I2S TX TDM mode."] +pub type RX_TDM_TOT_CHAN_NUM_R = crate::FieldReader; +#[doc = "Field `RX_TDM_TOT_CHAN_NUM` writer - The total channel number of I2S TX TDM mode."] +pub type RX_TDM_TOT_CHAN_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_pdm_chan0_en(&self) -> RX_TDM_PDM_CHAN0_EN_R { + RX_TDM_PDM_CHAN0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_pdm_chan1_en(&self) -> RX_TDM_PDM_CHAN1_EN_R { + RX_TDM_PDM_CHAN1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_pdm_chan2_en(&self) -> RX_TDM_PDM_CHAN2_EN_R { + RX_TDM_PDM_CHAN2_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_pdm_chan3_en(&self) -> RX_TDM_PDM_CHAN3_EN_R { + RX_TDM_PDM_CHAN3_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_pdm_chan4_en(&self) -> RX_TDM_PDM_CHAN4_EN_R { + RX_TDM_PDM_CHAN4_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_pdm_chan5_en(&self) -> RX_TDM_PDM_CHAN5_EN_R { + RX_TDM_PDM_CHAN5_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_pdm_chan6_en(&self) -> RX_TDM_PDM_CHAN6_EN_R { + RX_TDM_PDM_CHAN6_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_pdm_chan7_en(&self) -> RX_TDM_PDM_CHAN7_EN_R { + RX_TDM_PDM_CHAN7_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_chan8_en(&self) -> RX_TDM_CHAN8_EN_R { + RX_TDM_CHAN8_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_chan9_en(&self) -> RX_TDM_CHAN9_EN_R { + RX_TDM_CHAN9_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_chan10_en(&self) -> RX_TDM_CHAN10_EN_R { + RX_TDM_CHAN10_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_chan11_en(&self) -> RX_TDM_CHAN11_EN_R { + RX_TDM_CHAN11_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_chan12_en(&self) -> RX_TDM_CHAN12_EN_R { + RX_TDM_CHAN12_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_chan13_en(&self) -> RX_TDM_CHAN13_EN_R { + RX_TDM_CHAN13_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_chan14_en(&self) -> RX_TDM_CHAN14_EN_R { + RX_TDM_CHAN14_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_chan15_en(&self) -> RX_TDM_CHAN15_EN_R { + RX_TDM_CHAN15_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."] + #[inline(always)] + pub fn rx_tdm_tot_chan_num(&self) -> RX_TDM_TOT_CHAN_NUM_R { + RX_TDM_TOT_CHAN_NUM_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_TDM_CTRL") + .field( + "rx_tdm_pdm_chan0_en", + &format_args!("{}", self.rx_tdm_pdm_chan0_en().bit()), + ) + .field( + "rx_tdm_pdm_chan1_en", + &format_args!("{}", self.rx_tdm_pdm_chan1_en().bit()), + ) + .field( + "rx_tdm_pdm_chan2_en", + &format_args!("{}", self.rx_tdm_pdm_chan2_en().bit()), + ) + .field( + "rx_tdm_pdm_chan3_en", + &format_args!("{}", self.rx_tdm_pdm_chan3_en().bit()), + ) + .field( + "rx_tdm_pdm_chan4_en", + &format_args!("{}", self.rx_tdm_pdm_chan4_en().bit()), + ) + .field( + "rx_tdm_pdm_chan5_en", + &format_args!("{}", self.rx_tdm_pdm_chan5_en().bit()), + ) + .field( + "rx_tdm_pdm_chan6_en", + &format_args!("{}", self.rx_tdm_pdm_chan6_en().bit()), + ) + .field( + "rx_tdm_pdm_chan7_en", + &format_args!("{}", self.rx_tdm_pdm_chan7_en().bit()), + ) + .field( + "rx_tdm_chan8_en", + &format_args!("{}", self.rx_tdm_chan8_en().bit()), + ) + .field( + "rx_tdm_chan9_en", + &format_args!("{}", self.rx_tdm_chan9_en().bit()), + ) + .field( + "rx_tdm_chan10_en", + &format_args!("{}", self.rx_tdm_chan10_en().bit()), + ) + .field( + "rx_tdm_chan11_en", + &format_args!("{}", self.rx_tdm_chan11_en().bit()), + ) + .field( + "rx_tdm_chan12_en", + &format_args!("{}", self.rx_tdm_chan12_en().bit()), + ) + .field( + "rx_tdm_chan13_en", + &format_args!("{}", self.rx_tdm_chan13_en().bit()), + ) + .field( + "rx_tdm_chan14_en", + &format_args!("{}", self.rx_tdm_chan14_en().bit()), + ) + .field( + "rx_tdm_chan15_en", + &format_args!("{}", self.rx_tdm_chan15_en().bit()), + ) + .field( + "rx_tdm_tot_chan_num", + &format_args!("{}", self.rx_tdm_tot_chan_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_pdm_chan0_en(&mut self) -> RX_TDM_PDM_CHAN0_EN_W { + RX_TDM_PDM_CHAN0_EN_W::new(self, 0) + } + #[doc = "Bit 1 - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_pdm_chan1_en(&mut self) -> RX_TDM_PDM_CHAN1_EN_W { + RX_TDM_PDM_CHAN1_EN_W::new(self, 1) + } + #[doc = "Bit 2 - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_pdm_chan2_en(&mut self) -> RX_TDM_PDM_CHAN2_EN_W { + RX_TDM_PDM_CHAN2_EN_W::new(self, 2) + } + #[doc = "Bit 3 - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_pdm_chan3_en(&mut self) -> RX_TDM_PDM_CHAN3_EN_W { + RX_TDM_PDM_CHAN3_EN_W::new(self, 3) + } + #[doc = "Bit 4 - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_pdm_chan4_en(&mut self) -> RX_TDM_PDM_CHAN4_EN_W { + RX_TDM_PDM_CHAN4_EN_W::new(self, 4) + } + #[doc = "Bit 5 - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_pdm_chan5_en(&mut self) -> RX_TDM_PDM_CHAN5_EN_W { + RX_TDM_PDM_CHAN5_EN_W::new(self, 5) + } + #[doc = "Bit 6 - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_pdm_chan6_en(&mut self) -> RX_TDM_PDM_CHAN6_EN_W { + RX_TDM_PDM_CHAN6_EN_W::new(self, 6) + } + #[doc = "Bit 7 - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_pdm_chan7_en(&mut self) -> RX_TDM_PDM_CHAN7_EN_W { + RX_TDM_PDM_CHAN7_EN_W::new(self, 7) + } + #[doc = "Bit 8 - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_chan8_en(&mut self) -> RX_TDM_CHAN8_EN_W { + RX_TDM_CHAN8_EN_W::new(self, 8) + } + #[doc = "Bit 9 - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_chan9_en(&mut self) -> RX_TDM_CHAN9_EN_W { + RX_TDM_CHAN9_EN_W::new(self, 9) + } + #[doc = "Bit 10 - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_chan10_en(&mut self) -> RX_TDM_CHAN10_EN_W { + RX_TDM_CHAN10_EN_W::new(self, 10) + } + #[doc = "Bit 11 - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_chan11_en(&mut self) -> RX_TDM_CHAN11_EN_W { + RX_TDM_CHAN11_EN_W::new(self, 11) + } + #[doc = "Bit 12 - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_chan12_en(&mut self) -> RX_TDM_CHAN12_EN_W { + RX_TDM_CHAN12_EN_W::new(self, 12) + } + #[doc = "Bit 13 - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_chan13_en(&mut self) -> RX_TDM_CHAN13_EN_W { + RX_TDM_CHAN13_EN_W::new(self, 13) + } + #[doc = "Bit 14 - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_chan14_en(&mut self) -> RX_TDM_CHAN14_EN_W { + RX_TDM_CHAN14_EN_W::new(self, 14) + } + #[doc = "Bit 15 - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_chan15_en(&mut self) -> RX_TDM_CHAN15_EN_W { + RX_TDM_CHAN15_EN_W::new(self, 15) + } + #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_tot_chan_num(&mut self) -> RX_TDM_TOT_CHAN_NUM_W { + RX_TDM_TOT_CHAN_NUM_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S TX TDM mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tdm_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tdm_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_TDM_CTRL_SPEC; +impl crate::RegisterSpec for RX_TDM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_tdm_ctrl::R`](R) reader structure"] +impl crate::Readable for RX_TDM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_tdm_ctrl::W`](W) writer structure"] +impl crate::Writable for RX_TDM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_TDM_CTRL to value 0xffff"] +impl crate::Resettable for RX_TDM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0xffff; +} diff --git a/esp32p4/src/i2s0/rx_timing.rs b/esp32p4/src/i2s0/rx_timing.rs new file mode 100644 index 0000000000..f6f85be889 --- /dev/null +++ b/esp32p4/src/i2s0/rx_timing.rs @@ -0,0 +1,199 @@ +#[doc = "Register `RX_TIMING` reader"] +pub type R = crate::R; +#[doc = "Register `RX_TIMING` writer"] +pub type W = crate::W; +#[doc = "Field `RX_SD_IN_DM` reader - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_SD_IN_DM_R = crate::FieldReader; +#[doc = "Field `RX_SD_IN_DM` writer - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_SD_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_SD1_IN_DM` reader - The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_SD1_IN_DM_R = crate::FieldReader; +#[doc = "Field `RX_SD1_IN_DM` writer - The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_SD1_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_SD2_IN_DM` reader - The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_SD2_IN_DM_R = crate::FieldReader; +#[doc = "Field `RX_SD2_IN_DM` writer - The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_SD2_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_SD3_IN_DM` reader - The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_SD3_IN_DM_R = crate::FieldReader; +#[doc = "Field `RX_SD3_IN_DM` writer - The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_SD3_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_WS_OUT_DM` reader - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_WS_OUT_DM_R = crate::FieldReader; +#[doc = "Field `RX_WS_OUT_DM` writer - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_WS_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_BCK_OUT_DM` reader - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_BCK_OUT_DM_R = crate::FieldReader; +#[doc = "Field `RX_BCK_OUT_DM` writer - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_BCK_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_WS_IN_DM` reader - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_WS_IN_DM_R = crate::FieldReader; +#[doc = "Field `RX_WS_IN_DM` writer - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_WS_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_BCK_IN_DM` reader - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_BCK_IN_DM_R = crate::FieldReader; +#[doc = "Field `RX_BCK_IN_DM` writer - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_BCK_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_sd_in_dm(&self) -> RX_SD_IN_DM_R { + RX_SD_IN_DM_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 4:5 - The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_sd1_in_dm(&self) -> RX_SD1_IN_DM_R { + RX_SD1_IN_DM_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:9 - The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_sd2_in_dm(&self) -> RX_SD2_IN_DM_R { + RX_SD2_IN_DM_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 12:13 - The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_sd3_in_dm(&self) -> RX_SD3_IN_DM_R { + RX_SD3_IN_DM_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_ws_out_dm(&self) -> RX_WS_OUT_DM_R { + RX_WS_OUT_DM_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_bck_out_dm(&self) -> RX_BCK_OUT_DM_R { + RX_BCK_OUT_DM_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_ws_in_dm(&self) -> RX_WS_IN_DM_R { + RX_WS_IN_DM_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_bck_in_dm(&self) -> RX_BCK_IN_DM_R { + RX_BCK_IN_DM_R::new(((self.bits >> 28) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_TIMING") + .field( + "rx_sd_in_dm", + &format_args!("{}", self.rx_sd_in_dm().bits()), + ) + .field( + "rx_sd1_in_dm", + &format_args!("{}", self.rx_sd1_in_dm().bits()), + ) + .field( + "rx_sd2_in_dm", + &format_args!("{}", self.rx_sd2_in_dm().bits()), + ) + .field( + "rx_sd3_in_dm", + &format_args!("{}", self.rx_sd3_in_dm().bits()), + ) + .field( + "rx_ws_out_dm", + &format_args!("{}", self.rx_ws_out_dm().bits()), + ) + .field( + "rx_bck_out_dm", + &format_args!("{}", self.rx_bck_out_dm().bits()), + ) + .field( + "rx_ws_in_dm", + &format_args!("{}", self.rx_ws_in_dm().bits()), + ) + .field( + "rx_bck_in_dm", + &format_args!("{}", self.rx_bck_in_dm().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_sd_in_dm(&mut self) -> RX_SD_IN_DM_W { + RX_SD_IN_DM_W::new(self, 0) + } + #[doc = "Bits 4:5 - The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_sd1_in_dm(&mut self) -> RX_SD1_IN_DM_W { + RX_SD1_IN_DM_W::new(self, 4) + } + #[doc = "Bits 8:9 - The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_sd2_in_dm(&mut self) -> RX_SD2_IN_DM_W { + RX_SD2_IN_DM_W::new(self, 8) + } + #[doc = "Bits 12:13 - The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_sd3_in_dm(&mut self) -> RX_SD3_IN_DM_W { + RX_SD3_IN_DM_W::new(self, 12) + } + #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_ws_out_dm(&mut self) -> RX_WS_OUT_DM_W { + RX_WS_OUT_DM_W::new(self, 16) + } + #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_bck_out_dm(&mut self) -> RX_BCK_OUT_DM_W { + RX_BCK_OUT_DM_W::new(self, 20) + } + #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_ws_in_dm(&mut self) -> RX_WS_IN_DM_W { + RX_WS_IN_DM_W::new(self, 24) + } + #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_bck_in_dm(&mut self) -> RX_BCK_IN_DM_W { + RX_BCK_IN_DM_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S RX timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_timing::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_timing::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_TIMING_SPEC; +impl crate::RegisterSpec for RX_TIMING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_timing::R`](R) reader structure"] +impl crate::Readable for RX_TIMING_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_timing::W`](W) writer structure"] +impl crate::Writable for RX_TIMING_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_TIMING to value 0"] +impl crate::Resettable for RX_TIMING_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i2s0/rxeof_num.rs b/esp32p4/src/i2s0/rxeof_num.rs new file mode 100644 index 0000000000..61325d1eb6 --- /dev/null +++ b/esp32p4/src/i2s0/rxeof_num.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RXEOF_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `RXEOF_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `RX_EOF_NUM` reader - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."] +pub type RX_EOF_NUM_R = crate::FieldReader; +#[doc = "Field `RX_EOF_NUM` writer - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."] +pub type RX_EOF_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."] + #[inline(always)] + pub fn rx_eof_num(&self) -> RX_EOF_NUM_R { + RX_EOF_NUM_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RXEOF_NUM") + .field("rx_eof_num", &format_args!("{}", self.rx_eof_num().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."] + #[inline(always)] + #[must_use] + pub fn rx_eof_num(&mut self) -> RX_EOF_NUM_W { + RX_EOF_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S RX data number control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxeof_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxeof_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RXEOF_NUM_SPEC; +impl crate::RegisterSpec for RXEOF_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxeof_num::R`](R) reader structure"] +impl crate::Readable for RXEOF_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxeof_num::W`](W) writer structure"] +impl crate::Writable for RXEOF_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RXEOF_NUM to value 0x40"] +impl crate::Resettable for RXEOF_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0x40; +} diff --git a/esp32p4/src/i2s0/state.rs b/esp32p4/src/i2s0/state.rs new file mode 100644 index 0000000000..265d044d34 --- /dev/null +++ b/esp32p4/src/i2s0/state.rs @@ -0,0 +1,36 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +#[doc = "Field `TX_IDLE` reader - 1: i2s_tx is idle state. 0: i2s_tx is working."] +pub type TX_IDLE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - 1: i2s_tx is idle state. 0: i2s_tx is working."] + #[inline(always)] + pub fn tx_idle(&self) -> TX_IDLE_R { + TX_IDLE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATE") + .field("tx_idle", &format_args!("{}", self.tx_idle().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S TX status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATE_SPEC; +impl crate::RegisterSpec for STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for STATE_SPEC {} +#[doc = "`reset()` method sets STATE to value 0x01"] +impl crate::Resettable for STATE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/i2s0/tx_conf.rs b/esp32p4/src/i2s0/tx_conf.rs new file mode 100644 index 0000000000..3e047dd844 --- /dev/null +++ b/esp32p4/src/i2s0/tx_conf.rs @@ -0,0 +1,444 @@ +#[doc = "Register `TX_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `TX_RESET` writer - Set this bit to reset transmitter"] +pub type TX_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_FIFO_RESET` writer - Set this bit to reset Tx AFIFO"] +pub type TX_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_START` reader - Set this bit to start transmitting data"] +pub type TX_START_R = crate::BitReader; +#[doc = "Field `TX_START` writer - Set this bit to start transmitting data"] +pub type TX_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_SLAVE_MOD` reader - Set this bit to enable slave transmitter mode"] +pub type TX_SLAVE_MOD_R = crate::BitReader; +#[doc = "Field `TX_SLAVE_MOD` writer - Set this bit to enable slave transmitter mode"] +pub type TX_SLAVE_MOD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_STOP_EN` reader - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"] +pub type TX_STOP_EN_R = crate::BitReader; +#[doc = "Field `TX_STOP_EN` writer - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"] +pub type TX_STOP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CHAN_EQUAL` reader - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."] +pub type TX_CHAN_EQUAL_R = crate::BitReader; +#[doc = "Field `TX_CHAN_EQUAL` writer - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."] +pub type TX_CHAN_EQUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_MONO` reader - Set this bit to enable transmitter in mono mode"] +pub type TX_MONO_R = crate::BitReader; +#[doc = "Field `TX_MONO` writer - Set this bit to enable transmitter in mono mode"] +pub type TX_MONO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BIG_ENDIAN` reader - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] +pub type TX_BIG_ENDIAN_R = crate::BitReader; +#[doc = "Field `TX_BIG_ENDIAN` writer - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] +pub type TX_BIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_UPDATE` reader - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."] +pub type TX_UPDATE_R = crate::BitReader; +#[doc = "Field `TX_UPDATE` writer - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."] +pub type TX_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_MONO_FST_VLD` reader - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."] +pub type TX_MONO_FST_VLD_R = crate::BitReader; +#[doc = "Field `TX_MONO_FST_VLD` writer - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."] +pub type TX_MONO_FST_VLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_PCM_CONF` reader - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] +pub type TX_PCM_CONF_R = crate::FieldReader; +#[doc = "Field `TX_PCM_CONF` writer - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] +pub type TX_PCM_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_PCM_BYPASS` reader - Set this bit to bypass Compress/Decompress module for transmitted data."] +pub type TX_PCM_BYPASS_R = crate::BitReader; +#[doc = "Field `TX_PCM_BYPASS` writer - Set this bit to bypass Compress/Decompress module for transmitted data."] +pub type TX_PCM_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_MSB_SHIFT` reader - Set this bit to enable transmitter in Phillips standard mode"] +pub type TX_MSB_SHIFT_R = crate::BitReader; +#[doc = "Field `TX_MSB_SHIFT` writer - Set this bit to enable transmitter in Phillips standard mode"] +pub type TX_MSB_SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BCK_NO_DLY` reader - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."] +pub type TX_BCK_NO_DLY_R = crate::BitReader; +#[doc = "Field `TX_BCK_NO_DLY` writer - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."] +pub type TX_BCK_NO_DLY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_LEFT_ALIGN` reader - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."] +pub type TX_LEFT_ALIGN_R = crate::BitReader; +#[doc = "Field `TX_LEFT_ALIGN` writer - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."] +pub type TX_LEFT_ALIGN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_24_FILL_EN` reader - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"] +pub type TX_24_FILL_EN_R = crate::BitReader; +#[doc = "Field `TX_24_FILL_EN` writer - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"] +pub type TX_24_FILL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_WS_IDLE_POL` reader - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."] +pub type TX_WS_IDLE_POL_R = crate::BitReader; +#[doc = "Field `TX_WS_IDLE_POL` writer - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."] +pub type TX_WS_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BIT_ORDER` reader - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."] +pub type TX_BIT_ORDER_R = crate::BitReader; +#[doc = "Field `TX_BIT_ORDER` writer - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."] +pub type TX_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_EN` reader - 1: Enable I2S TDM Tx mode . 0: Disable."] +pub type TX_TDM_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_EN` writer - 1: Enable I2S TDM Tx mode . 0: Disable."] +pub type TX_TDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_PDM_EN` reader - 1: Enable I2S PDM Tx mode . 0: Disable."] +pub type TX_PDM_EN_R = crate::BitReader; +#[doc = "Field `TX_PDM_EN` writer - 1: Enable I2S PDM Tx mode . 0: Disable."] +pub type TX_PDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BCK_DIV_NUM` reader - Bit clock configuration bits in transmitter mode."] +pub type TX_BCK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `TX_BCK_DIV_NUM` writer - Bit clock configuration bits in transmitter mode."] +pub type TX_BCK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `TX_CHAN_MOD` reader - I2S transmitter channel mode configuration bits."] +pub type TX_CHAN_MOD_R = crate::FieldReader; +#[doc = "Field `TX_CHAN_MOD` writer - I2S transmitter channel mode configuration bits."] +pub type TX_CHAN_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SIG_LOOPBACK` reader - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."] +pub type SIG_LOOPBACK_R = crate::BitReader; +#[doc = "Field `SIG_LOOPBACK` writer - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."] +pub type SIG_LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Set this bit to start transmitting data"] + #[inline(always)] + pub fn tx_start(&self) -> TX_START_R { + TX_START_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to enable slave transmitter mode"] + #[inline(always)] + pub fn tx_slave_mod(&self) -> TX_SLAVE_MOD_R { + TX_SLAVE_MOD_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"] + #[inline(always)] + pub fn tx_stop_en(&self) -> TX_STOP_EN_R { + TX_STOP_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."] + #[inline(always)] + pub fn tx_chan_equal(&self) -> TX_CHAN_EQUAL_R { + TX_CHAN_EQUAL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set this bit to enable transmitter in mono mode"] + #[inline(always)] + pub fn tx_mono(&self) -> TX_MONO_R { + TX_MONO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] + #[inline(always)] + pub fn tx_big_endian(&self) -> TX_BIG_ENDIAN_R { + TX_BIG_ENDIAN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."] + #[inline(always)] + pub fn tx_update(&self) -> TX_UPDATE_R { + TX_UPDATE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."] + #[inline(always)] + pub fn tx_mono_fst_vld(&self) -> TX_MONO_FST_VLD_R { + TX_MONO_FST_VLD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] + #[inline(always)] + pub fn tx_pcm_conf(&self) -> TX_PCM_CONF_R { + TX_PCM_CONF_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for transmitted data."] + #[inline(always)] + pub fn tx_pcm_bypass(&self) -> TX_PCM_BYPASS_R { + TX_PCM_BYPASS_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set this bit to enable transmitter in Phillips standard mode"] + #[inline(always)] + pub fn tx_msb_shift(&self) -> TX_MSB_SHIFT_R { + TX_MSB_SHIFT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."] + #[inline(always)] + pub fn tx_bck_no_dly(&self) -> TX_BCK_NO_DLY_R { + TX_BCK_NO_DLY_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."] + #[inline(always)] + pub fn tx_left_align(&self) -> TX_LEFT_ALIGN_R { + TX_LEFT_ALIGN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"] + #[inline(always)] + pub fn tx_24_fill_en(&self) -> TX_24_FILL_EN_R { + TX_24_FILL_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."] + #[inline(always)] + pub fn tx_ws_idle_pol(&self) -> TX_WS_IDLE_POL_R { + TX_WS_IDLE_POL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."] + #[inline(always)] + pub fn tx_bit_order(&self) -> TX_BIT_ORDER_R { + TX_BIT_ORDER_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - 1: Enable I2S TDM Tx mode . 0: Disable."] + #[inline(always)] + pub fn tx_tdm_en(&self) -> TX_TDM_EN_R { + TX_TDM_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - 1: Enable I2S PDM Tx mode . 0: Disable."] + #[inline(always)] + pub fn tx_pdm_en(&self) -> TX_PDM_EN_R { + TX_PDM_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:26 - Bit clock configuration bits in transmitter mode."] + #[inline(always)] + pub fn tx_bck_div_num(&self) -> TX_BCK_DIV_NUM_R { + TX_BCK_DIV_NUM_R::new(((self.bits >> 21) & 0x3f) as u8) + } + #[doc = "Bits 27:29 - I2S transmitter channel mode configuration bits."] + #[inline(always)] + pub fn tx_chan_mod(&self) -> TX_CHAN_MOD_R { + TX_CHAN_MOD_R::new(((self.bits >> 27) & 7) as u8) + } + #[doc = "Bit 30 - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."] + #[inline(always)] + pub fn sig_loopback(&self) -> SIG_LOOPBACK_R { + SIG_LOOPBACK_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CONF") + .field("tx_start", &format_args!("{}", self.tx_start().bit())) + .field( + "tx_slave_mod", + &format_args!("{}", self.tx_slave_mod().bit()), + ) + .field("tx_stop_en", &format_args!("{}", self.tx_stop_en().bit())) + .field( + "tx_chan_equal", + &format_args!("{}", self.tx_chan_equal().bit()), + ) + .field("tx_mono", &format_args!("{}", self.tx_mono().bit())) + .field( + "tx_big_endian", + &format_args!("{}", self.tx_big_endian().bit()), + ) + .field("tx_update", &format_args!("{}", self.tx_update().bit())) + .field( + "tx_mono_fst_vld", + &format_args!("{}", self.tx_mono_fst_vld().bit()), + ) + .field( + "tx_pcm_conf", + &format_args!("{}", self.tx_pcm_conf().bits()), + ) + .field( + "tx_pcm_bypass", + &format_args!("{}", self.tx_pcm_bypass().bit()), + ) + .field( + "tx_msb_shift", + &format_args!("{}", self.tx_msb_shift().bit()), + ) + .field( + "tx_bck_no_dly", + &format_args!("{}", self.tx_bck_no_dly().bit()), + ) + .field( + "tx_left_align", + &format_args!("{}", self.tx_left_align().bit()), + ) + .field( + "tx_24_fill_en", + &format_args!("{}", self.tx_24_fill_en().bit()), + ) + .field( + "tx_ws_idle_pol", + &format_args!("{}", self.tx_ws_idle_pol().bit()), + ) + .field( + "tx_bit_order", + &format_args!("{}", self.tx_bit_order().bit()), + ) + .field("tx_tdm_en", &format_args!("{}", self.tx_tdm_en().bit())) + .field("tx_pdm_en", &format_args!("{}", self.tx_pdm_en().bit())) + .field( + "tx_bck_div_num", + &format_args!("{}", self.tx_bck_div_num().bits()), + ) + .field( + "tx_chan_mod", + &format_args!("{}", self.tx_chan_mod().bits()), + ) + .field( + "sig_loopback", + &format_args!("{}", self.sig_loopback().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to reset transmitter"] + #[inline(always)] + #[must_use] + pub fn tx_reset(&mut self) -> TX_RESET_W { + TX_RESET_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to reset Tx AFIFO"] + #[inline(always)] + #[must_use] + pub fn tx_fifo_reset(&mut self) -> TX_FIFO_RESET_W { + TX_FIFO_RESET_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to start transmitting data"] + #[inline(always)] + #[must_use] + pub fn tx_start(&mut self) -> TX_START_W { + TX_START_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to enable slave transmitter mode"] + #[inline(always)] + #[must_use] + pub fn tx_slave_mod(&mut self) -> TX_SLAVE_MOD_W { + TX_SLAVE_MOD_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"] + #[inline(always)] + #[must_use] + pub fn tx_stop_en(&mut self) -> TX_STOP_EN_W { + TX_STOP_EN_W::new(self, 4) + } + #[doc = "Bit 5 - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."] + #[inline(always)] + #[must_use] + pub fn tx_chan_equal(&mut self) -> TX_CHAN_EQUAL_W { + TX_CHAN_EQUAL_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to enable transmitter in mono mode"] + #[inline(always)] + #[must_use] + pub fn tx_mono(&mut self) -> TX_MONO_W { + TX_MONO_W::new(self, 6) + } + #[doc = "Bit 7 - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] + #[inline(always)] + #[must_use] + pub fn tx_big_endian(&mut self) -> TX_BIG_ENDIAN_W { + TX_BIG_ENDIAN_W::new(self, 7) + } + #[doc = "Bit 8 - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."] + #[inline(always)] + #[must_use] + pub fn tx_update(&mut self) -> TX_UPDATE_W { + TX_UPDATE_W::new(self, 8) + } + #[doc = "Bit 9 - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."] + #[inline(always)] + #[must_use] + pub fn tx_mono_fst_vld(&mut self) -> TX_MONO_FST_VLD_W { + TX_MONO_FST_VLD_W::new(self, 9) + } + #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] + #[inline(always)] + #[must_use] + pub fn tx_pcm_conf(&mut self) -> TX_PCM_CONF_W { + TX_PCM_CONF_W::new(self, 10) + } + #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for transmitted data."] + #[inline(always)] + #[must_use] + pub fn tx_pcm_bypass(&mut self) -> TX_PCM_BYPASS_W { + TX_PCM_BYPASS_W::new(self, 12) + } + #[doc = "Bit 13 - Set this bit to enable transmitter in Phillips standard mode"] + #[inline(always)] + #[must_use] + pub fn tx_msb_shift(&mut self) -> TX_MSB_SHIFT_W { + TX_MSB_SHIFT_W::new(self, 13) + } + #[doc = "Bit 14 - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."] + #[inline(always)] + #[must_use] + pub fn tx_bck_no_dly(&mut self) -> TX_BCK_NO_DLY_W { + TX_BCK_NO_DLY_W::new(self, 14) + } + #[doc = "Bit 15 - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."] + #[inline(always)] + #[must_use] + pub fn tx_left_align(&mut self) -> TX_LEFT_ALIGN_W { + TX_LEFT_ALIGN_W::new(self, 15) + } + #[doc = "Bit 16 - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"] + #[inline(always)] + #[must_use] + pub fn tx_24_fill_en(&mut self) -> TX_24_FILL_EN_W { + TX_24_FILL_EN_W::new(self, 16) + } + #[doc = "Bit 17 - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."] + #[inline(always)] + #[must_use] + pub fn tx_ws_idle_pol(&mut self) -> TX_WS_IDLE_POL_W { + TX_WS_IDLE_POL_W::new(self, 17) + } + #[doc = "Bit 18 - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."] + #[inline(always)] + #[must_use] + pub fn tx_bit_order(&mut self) -> TX_BIT_ORDER_W { + TX_BIT_ORDER_W::new(self, 18) + } + #[doc = "Bit 19 - 1: Enable I2S TDM Tx mode . 0: Disable."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_en(&mut self) -> TX_TDM_EN_W { + TX_TDM_EN_W::new(self, 19) + } + #[doc = "Bit 20 - 1: Enable I2S PDM Tx mode . 0: Disable."] + #[inline(always)] + #[must_use] + pub fn tx_pdm_en(&mut self) -> TX_PDM_EN_W { + TX_PDM_EN_W::new(self, 20) + } + #[doc = "Bits 21:26 - Bit clock configuration bits in transmitter mode."] + #[inline(always)] + #[must_use] + pub fn tx_bck_div_num(&mut self) -> TX_BCK_DIV_NUM_W { + TX_BCK_DIV_NUM_W::new(self, 21) + } + #[doc = "Bits 27:29 - I2S transmitter channel mode configuration bits."] + #[inline(always)] + #[must_use] + pub fn tx_chan_mod(&mut self) -> TX_CHAN_MOD_W { + TX_CHAN_MOD_W::new(self, 27) + } + #[doc = "Bit 30 - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."] + #[inline(always)] + #[must_use] + pub fn sig_loopback(&mut self) -> SIG_LOOPBACK_W { + SIG_LOOPBACK_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S TX configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CONF_SPEC; +impl crate::RegisterSpec for TX_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_conf::R`](R) reader structure"] +impl crate::Readable for TX_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_conf::W`](W) writer structure"] +impl crate::Writable for TX_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CONF to value 0x00c0_f210"] +impl crate::Resettable for TX_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x00c0_f210; +} diff --git a/esp32p4/src/i2s0/tx_conf1.rs b/esp32p4/src/i2s0/tx_conf1.rs new file mode 100644 index 0000000000..d008a6ed28 --- /dev/null +++ b/esp32p4/src/i2s0/tx_conf1.rs @@ -0,0 +1,123 @@ +#[doc = "Register `TX_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `TX_TDM_WS_WIDTH` reader - The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"] +pub type TX_TDM_WS_WIDTH_R = crate::FieldReader; +#[doc = "Field `TX_TDM_WS_WIDTH` writer - The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"] +pub type TX_TDM_WS_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `TX_BITS_MOD` reader - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] +pub type TX_BITS_MOD_R = crate::FieldReader; +#[doc = "Field `TX_BITS_MOD` writer - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] +pub type TX_BITS_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `TX_HALF_SAMPLE_BITS` reader - I2S Tx half sample bits -1."] +pub type TX_HALF_SAMPLE_BITS_R = crate::FieldReader; +#[doc = "Field `TX_HALF_SAMPLE_BITS` writer - I2S Tx half sample bits -1."] +pub type TX_HALF_SAMPLE_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TX_TDM_CHAN_BITS` reader - The Tx bit number for each channel minus 1in TDM mode."] +pub type TX_TDM_CHAN_BITS_R = crate::FieldReader; +#[doc = "Field `TX_TDM_CHAN_BITS` writer - The Tx bit number for each channel minus 1in TDM mode."] +pub type TX_TDM_CHAN_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:8 - The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"] + #[inline(always)] + pub fn tx_tdm_ws_width(&self) -> TX_TDM_WS_WIDTH_R { + TX_TDM_WS_WIDTH_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 14:18 - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] + #[inline(always)] + pub fn tx_bits_mod(&self) -> TX_BITS_MOD_R { + TX_BITS_MOD_R::new(((self.bits >> 14) & 0x1f) as u8) + } + #[doc = "Bits 19:26 - I2S Tx half sample bits -1."] + #[inline(always)] + pub fn tx_half_sample_bits(&self) -> TX_HALF_SAMPLE_BITS_R { + TX_HALF_SAMPLE_BITS_R::new(((self.bits >> 19) & 0xff) as u8) + } + #[doc = "Bits 27:31 - The Tx bit number for each channel minus 1in TDM mode."] + #[inline(always)] + pub fn tx_tdm_chan_bits(&self) -> TX_TDM_CHAN_BITS_R { + TX_TDM_CHAN_BITS_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CONF1") + .field( + "tx_tdm_ws_width", + &format_args!("{}", self.tx_tdm_ws_width().bits()), + ) + .field( + "tx_bits_mod", + &format_args!("{}", self.tx_bits_mod().bits()), + ) + .field( + "tx_half_sample_bits", + &format_args!("{}", self.tx_half_sample_bits().bits()), + ) + .field( + "tx_tdm_chan_bits", + &format_args!("{}", self.tx_tdm_chan_bits().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"] + #[inline(always)] + #[must_use] + pub fn tx_tdm_ws_width(&mut self) -> TX_TDM_WS_WIDTH_W { + TX_TDM_WS_WIDTH_W::new(self, 0) + } + #[doc = "Bits 14:18 - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] + #[inline(always)] + #[must_use] + pub fn tx_bits_mod(&mut self) -> TX_BITS_MOD_W { + TX_BITS_MOD_W::new(self, 14) + } + #[doc = "Bits 19:26 - I2S Tx half sample bits -1."] + #[inline(always)] + #[must_use] + pub fn tx_half_sample_bits(&mut self) -> TX_HALF_SAMPLE_BITS_W { + TX_HALF_SAMPLE_BITS_W::new(self, 19) + } + #[doc = "Bits 27:31 - The Tx bit number for each channel minus 1in TDM mode."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan_bits(&mut self) -> TX_TDM_CHAN_BITS_W { + TX_TDM_CHAN_BITS_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S TX configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CONF1_SPEC; +impl crate::RegisterSpec for TX_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_conf1::R`](R) reader structure"] +impl crate::Readable for TX_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_conf1::W`](W) writer structure"] +impl crate::Writable for TX_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CONF1 to value 0x787b_c000"] +impl crate::Resettable for TX_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x787b_c000; +} diff --git a/esp32p4/src/i2s0/tx_pcm2pdm_conf.rs b/esp32p4/src/i2s0/tx_pcm2pdm_conf.rs new file mode 100644 index 0000000000..a8214bb331 --- /dev/null +++ b/esp32p4/src/i2s0/tx_pcm2pdm_conf.rs @@ -0,0 +1,279 @@ +#[doc = "Register `TX_PCM2PDM_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `TX_PCM2PDM_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `TX_PDM_HP_BYPASS` reader - I2S TX PDM bypass hp filter or not. The option has been removed."] +pub type TX_PDM_HP_BYPASS_R = crate::BitReader; +#[doc = "Field `TX_PDM_HP_BYPASS` writer - I2S TX PDM bypass hp filter or not. The option has been removed."] +pub type TX_PDM_HP_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_PDM_SINC_OSR2` reader - I2S TX PDM OSR2 value"] +pub type TX_PDM_SINC_OSR2_R = crate::FieldReader; +#[doc = "Field `TX_PDM_SINC_OSR2` writer - I2S TX PDM OSR2 value"] +pub type TX_PDM_SINC_OSR2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TX_PDM_PRESCALE` reader - I2S TX PDM prescale for sigmadelta"] +pub type TX_PDM_PRESCALE_R = crate::FieldReader; +#[doc = "Field `TX_PDM_PRESCALE` writer - I2S TX PDM prescale for sigmadelta"] +pub type TX_PDM_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TX_PDM_HP_IN_SHIFT` reader - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] +pub type TX_PDM_HP_IN_SHIFT_R = crate::FieldReader; +#[doc = "Field `TX_PDM_HP_IN_SHIFT` writer - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] +pub type TX_PDM_HP_IN_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_PDM_LP_IN_SHIFT` reader - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] +pub type TX_PDM_LP_IN_SHIFT_R = crate::FieldReader; +#[doc = "Field `TX_PDM_LP_IN_SHIFT` writer - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] +pub type TX_PDM_LP_IN_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_PDM_SINC_IN_SHIFT` reader - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] +pub type TX_PDM_SINC_IN_SHIFT_R = crate::FieldReader; +#[doc = "Field `TX_PDM_SINC_IN_SHIFT` writer - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] +pub type TX_PDM_SINC_IN_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_PDM_SIGMADELTA_IN_SHIFT` reader - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] +pub type TX_PDM_SIGMADELTA_IN_SHIFT_R = crate::FieldReader; +#[doc = "Field `TX_PDM_SIGMADELTA_IN_SHIFT` writer - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] +pub type TX_PDM_SIGMADELTA_IN_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_PDM_SIGMADELTA_DITHER2` reader - I2S TX PDM sigmadelta dither2 value"] +pub type TX_PDM_SIGMADELTA_DITHER2_R = crate::BitReader; +#[doc = "Field `TX_PDM_SIGMADELTA_DITHER2` writer - I2S TX PDM sigmadelta dither2 value"] +pub type TX_PDM_SIGMADELTA_DITHER2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_PDM_SIGMADELTA_DITHER` reader - I2S TX PDM sigmadelta dither value"] +pub type TX_PDM_SIGMADELTA_DITHER_R = crate::BitReader; +#[doc = "Field `TX_PDM_SIGMADELTA_DITHER` writer - I2S TX PDM sigmadelta dither value"] +pub type TX_PDM_SIGMADELTA_DITHER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_PDM_DAC_2OUT_EN` reader - I2S TX PDM dac mode enable"] +pub type TX_PDM_DAC_2OUT_EN_R = crate::BitReader; +#[doc = "Field `TX_PDM_DAC_2OUT_EN` writer - I2S TX PDM dac mode enable"] +pub type TX_PDM_DAC_2OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_PDM_DAC_MODE_EN` reader - I2S TX PDM dac 2channel enable"] +pub type TX_PDM_DAC_MODE_EN_R = crate::BitReader; +#[doc = "Field `TX_PDM_DAC_MODE_EN` writer - I2S TX PDM dac 2channel enable"] +pub type TX_PDM_DAC_MODE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PCM2PDM_CONV_EN` reader - I2S TX PDM Converter enable"] +pub type PCM2PDM_CONV_EN_R = crate::BitReader; +#[doc = "Field `PCM2PDM_CONV_EN` writer - I2S TX PDM Converter enable"] +pub type PCM2PDM_CONV_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2S TX PDM bypass hp filter or not. The option has been removed."] + #[inline(always)] + pub fn tx_pdm_hp_bypass(&self) -> TX_PDM_HP_BYPASS_R { + TX_PDM_HP_BYPASS_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:4 - I2S TX PDM OSR2 value"] + #[inline(always)] + pub fn tx_pdm_sinc_osr2(&self) -> TX_PDM_SINC_OSR2_R { + TX_PDM_SINC_OSR2_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bits 5:12 - I2S TX PDM prescale for sigmadelta"] + #[inline(always)] + pub fn tx_pdm_prescale(&self) -> TX_PDM_PRESCALE_R { + TX_PDM_PRESCALE_R::new(((self.bits >> 5) & 0xff) as u8) + } + #[doc = "Bits 13:14 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] + #[inline(always)] + pub fn tx_pdm_hp_in_shift(&self) -> TX_PDM_HP_IN_SHIFT_R { + TX_PDM_HP_IN_SHIFT_R::new(((self.bits >> 13) & 3) as u8) + } + #[doc = "Bits 15:16 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] + #[inline(always)] + pub fn tx_pdm_lp_in_shift(&self) -> TX_PDM_LP_IN_SHIFT_R { + TX_PDM_LP_IN_SHIFT_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bits 17:18 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] + #[inline(always)] + pub fn tx_pdm_sinc_in_shift(&self) -> TX_PDM_SINC_IN_SHIFT_R { + TX_PDM_SINC_IN_SHIFT_R::new(((self.bits >> 17) & 3) as u8) + } + #[doc = "Bits 19:20 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] + #[inline(always)] + pub fn tx_pdm_sigmadelta_in_shift(&self) -> TX_PDM_SIGMADELTA_IN_SHIFT_R { + TX_PDM_SIGMADELTA_IN_SHIFT_R::new(((self.bits >> 19) & 3) as u8) + } + #[doc = "Bit 21 - I2S TX PDM sigmadelta dither2 value"] + #[inline(always)] + pub fn tx_pdm_sigmadelta_dither2(&self) -> TX_PDM_SIGMADELTA_DITHER2_R { + TX_PDM_SIGMADELTA_DITHER2_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - I2S TX PDM sigmadelta dither value"] + #[inline(always)] + pub fn tx_pdm_sigmadelta_dither(&self) -> TX_PDM_SIGMADELTA_DITHER_R { + TX_PDM_SIGMADELTA_DITHER_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - I2S TX PDM dac mode enable"] + #[inline(always)] + pub fn tx_pdm_dac_2out_en(&self) -> TX_PDM_DAC_2OUT_EN_R { + TX_PDM_DAC_2OUT_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - I2S TX PDM dac 2channel enable"] + #[inline(always)] + pub fn tx_pdm_dac_mode_en(&self) -> TX_PDM_DAC_MODE_EN_R { + TX_PDM_DAC_MODE_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - I2S TX PDM Converter enable"] + #[inline(always)] + pub fn pcm2pdm_conv_en(&self) -> PCM2PDM_CONV_EN_R { + PCM2PDM_CONV_EN_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_PCM2PDM_CONF") + .field( + "tx_pdm_hp_bypass", + &format_args!("{}", self.tx_pdm_hp_bypass().bit()), + ) + .field( + "tx_pdm_sinc_osr2", + &format_args!("{}", self.tx_pdm_sinc_osr2().bits()), + ) + .field( + "tx_pdm_prescale", + &format_args!("{}", self.tx_pdm_prescale().bits()), + ) + .field( + "tx_pdm_hp_in_shift", + &format_args!("{}", self.tx_pdm_hp_in_shift().bits()), + ) + .field( + "tx_pdm_lp_in_shift", + &format_args!("{}", self.tx_pdm_lp_in_shift().bits()), + ) + .field( + "tx_pdm_sinc_in_shift", + &format_args!("{}", self.tx_pdm_sinc_in_shift().bits()), + ) + .field( + "tx_pdm_sigmadelta_in_shift", + &format_args!("{}", self.tx_pdm_sigmadelta_in_shift().bits()), + ) + .field( + "tx_pdm_sigmadelta_dither2", + &format_args!("{}", self.tx_pdm_sigmadelta_dither2().bit()), + ) + .field( + "tx_pdm_sigmadelta_dither", + &format_args!("{}", self.tx_pdm_sigmadelta_dither().bit()), + ) + .field( + "tx_pdm_dac_2out_en", + &format_args!("{}", self.tx_pdm_dac_2out_en().bit()), + ) + .field( + "tx_pdm_dac_mode_en", + &format_args!("{}", self.tx_pdm_dac_mode_en().bit()), + ) + .field( + "pcm2pdm_conv_en", + &format_args!("{}", self.pcm2pdm_conv_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - I2S TX PDM bypass hp filter or not. The option has been removed."] + #[inline(always)] + #[must_use] + pub fn tx_pdm_hp_bypass(&mut self) -> TX_PDM_HP_BYPASS_W { + TX_PDM_HP_BYPASS_W::new(self, 0) + } + #[doc = "Bits 1:4 - I2S TX PDM OSR2 value"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_sinc_osr2(&mut self) -> TX_PDM_SINC_OSR2_W { + TX_PDM_SINC_OSR2_W::new(self, 1) + } + #[doc = "Bits 5:12 - I2S TX PDM prescale for sigmadelta"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_prescale(&mut self) -> TX_PDM_PRESCALE_W { + TX_PDM_PRESCALE_W::new(self, 5) + } + #[doc = "Bits 13:14 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_hp_in_shift(&mut self) -> TX_PDM_HP_IN_SHIFT_W { + TX_PDM_HP_IN_SHIFT_W::new(self, 13) + } + #[doc = "Bits 15:16 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_lp_in_shift(&mut self) -> TX_PDM_LP_IN_SHIFT_W { + TX_PDM_LP_IN_SHIFT_W::new(self, 15) + } + #[doc = "Bits 17:18 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_sinc_in_shift(&mut self) -> TX_PDM_SINC_IN_SHIFT_W { + TX_PDM_SINC_IN_SHIFT_W::new(self, 17) + } + #[doc = "Bits 19:20 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_sigmadelta_in_shift( + &mut self, + ) -> TX_PDM_SIGMADELTA_IN_SHIFT_W { + TX_PDM_SIGMADELTA_IN_SHIFT_W::new(self, 19) + } + #[doc = "Bit 21 - I2S TX PDM sigmadelta dither2 value"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_sigmadelta_dither2( + &mut self, + ) -> TX_PDM_SIGMADELTA_DITHER2_W { + TX_PDM_SIGMADELTA_DITHER2_W::new(self, 21) + } + #[doc = "Bit 22 - I2S TX PDM sigmadelta dither value"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_sigmadelta_dither(&mut self) -> TX_PDM_SIGMADELTA_DITHER_W { + TX_PDM_SIGMADELTA_DITHER_W::new(self, 22) + } + #[doc = "Bit 23 - I2S TX PDM dac mode enable"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_dac_2out_en(&mut self) -> TX_PDM_DAC_2OUT_EN_W { + TX_PDM_DAC_2OUT_EN_W::new(self, 23) + } + #[doc = "Bit 24 - I2S TX PDM dac 2channel enable"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_dac_mode_en(&mut self) -> TX_PDM_DAC_MODE_EN_W { + TX_PDM_DAC_MODE_EN_W::new(self, 24) + } + #[doc = "Bit 25 - I2S TX PDM Converter enable"] + #[inline(always)] + #[must_use] + pub fn pcm2pdm_conv_en(&mut self) -> PCM2PDM_CONV_EN_W { + PCM2PDM_CONV_EN_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S TX PCM2PDM configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_pcm2pdm_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_pcm2pdm_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_PCM2PDM_CONF_SPEC; +impl crate::RegisterSpec for TX_PCM2PDM_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_pcm2pdm_conf::R`](R) reader structure"] +impl crate::Readable for TX_PCM2PDM_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_pcm2pdm_conf::W`](W) writer structure"] +impl crate::Writable for TX_PCM2PDM_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_PCM2PDM_CONF to value 0x004a_a004"] +impl crate::Resettable for TX_PCM2PDM_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x004a_a004; +} diff --git a/esp32p4/src/i2s0/tx_pcm2pdm_conf1.rs b/esp32p4/src/i2s0/tx_pcm2pdm_conf1.rs new file mode 100644 index 0000000000..ec5f0e8a3e --- /dev/null +++ b/esp32p4/src/i2s0/tx_pcm2pdm_conf1.rs @@ -0,0 +1,117 @@ +#[doc = "Register `TX_PCM2PDM_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `TX_PCM2PDM_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `TX_PDM_FP` reader - I2S TX PDM Fp"] +pub type TX_PDM_FP_R = crate::FieldReader; +#[doc = "Field `TX_PDM_FP` writer - I2S TX PDM Fp"] +pub type TX_PDM_FP_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `TX_PDM_FS` reader - I2S TX PDM Fs"] +pub type TX_PDM_FS_R = crate::FieldReader; +#[doc = "Field `TX_PDM_FS` writer - I2S TX PDM Fs"] +pub type TX_PDM_FS_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `TX_IIR_HP_MULT12_5` reader - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5\\[2:0\\])"] +pub type TX_IIR_HP_MULT12_5_R = crate::FieldReader; +#[doc = "Field `TX_IIR_HP_MULT12_5` writer - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5\\[2:0\\])"] +pub type TX_IIR_HP_MULT12_5_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `TX_IIR_HP_MULT12_0` reader - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0\\[2:0\\])"] +pub type TX_IIR_HP_MULT12_0_R = crate::FieldReader; +#[doc = "Field `TX_IIR_HP_MULT12_0` writer - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0\\[2:0\\])"] +pub type TX_IIR_HP_MULT12_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:9 - I2S TX PDM Fp"] + #[inline(always)] + pub fn tx_pdm_fp(&self) -> TX_PDM_FP_R { + TX_PDM_FP_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:19 - I2S TX PDM Fs"] + #[inline(always)] + pub fn tx_pdm_fs(&self) -> TX_PDM_FS_R { + TX_PDM_FS_R::new(((self.bits >> 10) & 0x03ff) as u16) + } + #[doc = "Bits 20:22 - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5\\[2:0\\])"] + #[inline(always)] + pub fn tx_iir_hp_mult12_5(&self) -> TX_IIR_HP_MULT12_5_R { + TX_IIR_HP_MULT12_5_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bits 23:25 - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0\\[2:0\\])"] + #[inline(always)] + pub fn tx_iir_hp_mult12_0(&self) -> TX_IIR_HP_MULT12_0_R { + TX_IIR_HP_MULT12_0_R::new(((self.bits >> 23) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_PCM2PDM_CONF1") + .field("tx_pdm_fp", &format_args!("{}", self.tx_pdm_fp().bits())) + .field("tx_pdm_fs", &format_args!("{}", self.tx_pdm_fs().bits())) + .field( + "tx_iir_hp_mult12_5", + &format_args!("{}", self.tx_iir_hp_mult12_5().bits()), + ) + .field( + "tx_iir_hp_mult12_0", + &format_args!("{}", self.tx_iir_hp_mult12_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - I2S TX PDM Fp"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_fp(&mut self) -> TX_PDM_FP_W { + TX_PDM_FP_W::new(self, 0) + } + #[doc = "Bits 10:19 - I2S TX PDM Fs"] + #[inline(always)] + #[must_use] + pub fn tx_pdm_fs(&mut self) -> TX_PDM_FS_W { + TX_PDM_FS_W::new(self, 10) + } + #[doc = "Bits 20:22 - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5\\[2:0\\])"] + #[inline(always)] + #[must_use] + pub fn tx_iir_hp_mult12_5(&mut self) -> TX_IIR_HP_MULT12_5_W { + TX_IIR_HP_MULT12_5_W::new(self, 20) + } + #[doc = "Bits 23:25 - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0\\[2:0\\])"] + #[inline(always)] + #[must_use] + pub fn tx_iir_hp_mult12_0(&mut self) -> TX_IIR_HP_MULT12_0_W { + TX_IIR_HP_MULT12_0_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S TX PCM2PDM configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_pcm2pdm_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_pcm2pdm_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_PCM2PDM_CONF1_SPEC; +impl crate::RegisterSpec for TX_PCM2PDM_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_pcm2pdm_conf1::R`](R) reader structure"] +impl crate::Readable for TX_PCM2PDM_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_pcm2pdm_conf1::W`](W) writer structure"] +impl crate::Writable for TX_PCM2PDM_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_PCM2PDM_CONF1 to value 0x03f7_83c0"] +impl crate::Resettable for TX_PCM2PDM_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x03f7_83c0; +} diff --git a/esp32p4/src/i2s0/tx_tdm_ctrl.rs b/esp32p4/src/i2s0/tx_tdm_ctrl.rs new file mode 100644 index 0000000000..ea27da7b8a --- /dev/null +++ b/esp32p4/src/i2s0/tx_tdm_ctrl.rs @@ -0,0 +1,389 @@ +#[doc = "Register `TX_TDM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `TX_TDM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `TX_TDM_CHAN0_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN0_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN0_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN1_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN1_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN1_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN2_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN2_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN2_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN3_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN3_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN3_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN4_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN4_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN4_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN5_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN5_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN5_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN5_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN6_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN6_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN6_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN6_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN7_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN7_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN7_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN7_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN8_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN8_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN8_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN8_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN9_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN9_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN9_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN9_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN10_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN10_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN10_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN10_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN11_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN11_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN11_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN11_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN12_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN12_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN12_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN12_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN13_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN13_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN13_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN13_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN14_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN14_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN14_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN14_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_CHAN15_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN15_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_CHAN15_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel."] +pub type TX_TDM_CHAN15_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_TDM_TOT_CHAN_NUM` reader - The total channel number of I2S TX TDM mode."] +pub type TX_TDM_TOT_CHAN_NUM_R = crate::FieldReader; +#[doc = "Field `TX_TDM_TOT_CHAN_NUM` writer - The total channel number of I2S TX TDM mode."] +pub type TX_TDM_TOT_CHAN_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TX_TDM_SKIP_MSK_EN` reader - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels."] +pub type TX_TDM_SKIP_MSK_EN_R = crate::BitReader; +#[doc = "Field `TX_TDM_SKIP_MSK_EN` writer - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels."] +pub type TX_TDM_SKIP_MSK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan0_en(&self) -> TX_TDM_CHAN0_EN_R { + TX_TDM_CHAN0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan1_en(&self) -> TX_TDM_CHAN1_EN_R { + TX_TDM_CHAN1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan2_en(&self) -> TX_TDM_CHAN2_EN_R { + TX_TDM_CHAN2_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan3_en(&self) -> TX_TDM_CHAN3_EN_R { + TX_TDM_CHAN3_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan4_en(&self) -> TX_TDM_CHAN4_EN_R { + TX_TDM_CHAN4_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan5_en(&self) -> TX_TDM_CHAN5_EN_R { + TX_TDM_CHAN5_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan6_en(&self) -> TX_TDM_CHAN6_EN_R { + TX_TDM_CHAN6_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan7_en(&self) -> TX_TDM_CHAN7_EN_R { + TX_TDM_CHAN7_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan8_en(&self) -> TX_TDM_CHAN8_EN_R { + TX_TDM_CHAN8_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan9_en(&self) -> TX_TDM_CHAN9_EN_R { + TX_TDM_CHAN9_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan10_en(&self) -> TX_TDM_CHAN10_EN_R { + TX_TDM_CHAN10_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan11_en(&self) -> TX_TDM_CHAN11_EN_R { + TX_TDM_CHAN11_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan12_en(&self) -> TX_TDM_CHAN12_EN_R { + TX_TDM_CHAN12_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan13_en(&self) -> TX_TDM_CHAN13_EN_R { + TX_TDM_CHAN13_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan14_en(&self) -> TX_TDM_CHAN14_EN_R { + TX_TDM_CHAN14_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel."] + #[inline(always)] + pub fn tx_tdm_chan15_en(&self) -> TX_TDM_CHAN15_EN_R { + TX_TDM_CHAN15_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."] + #[inline(always)] + pub fn tx_tdm_tot_chan_num(&self) -> TX_TDM_TOT_CHAN_NUM_R { + TX_TDM_TOT_CHAN_NUM_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels."] + #[inline(always)] + pub fn tx_tdm_skip_msk_en(&self) -> TX_TDM_SKIP_MSK_EN_R { + TX_TDM_SKIP_MSK_EN_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_TDM_CTRL") + .field( + "tx_tdm_chan0_en", + &format_args!("{}", self.tx_tdm_chan0_en().bit()), + ) + .field( + "tx_tdm_chan1_en", + &format_args!("{}", self.tx_tdm_chan1_en().bit()), + ) + .field( + "tx_tdm_chan2_en", + &format_args!("{}", self.tx_tdm_chan2_en().bit()), + ) + .field( + "tx_tdm_chan3_en", + &format_args!("{}", self.tx_tdm_chan3_en().bit()), + ) + .field( + "tx_tdm_chan4_en", + &format_args!("{}", self.tx_tdm_chan4_en().bit()), + ) + .field( + "tx_tdm_chan5_en", + &format_args!("{}", self.tx_tdm_chan5_en().bit()), + ) + .field( + "tx_tdm_chan6_en", + &format_args!("{}", self.tx_tdm_chan6_en().bit()), + ) + .field( + "tx_tdm_chan7_en", + &format_args!("{}", self.tx_tdm_chan7_en().bit()), + ) + .field( + "tx_tdm_chan8_en", + &format_args!("{}", self.tx_tdm_chan8_en().bit()), + ) + .field( + "tx_tdm_chan9_en", + &format_args!("{}", self.tx_tdm_chan9_en().bit()), + ) + .field( + "tx_tdm_chan10_en", + &format_args!("{}", self.tx_tdm_chan10_en().bit()), + ) + .field( + "tx_tdm_chan11_en", + &format_args!("{}", self.tx_tdm_chan11_en().bit()), + ) + .field( + "tx_tdm_chan12_en", + &format_args!("{}", self.tx_tdm_chan12_en().bit()), + ) + .field( + "tx_tdm_chan13_en", + &format_args!("{}", self.tx_tdm_chan13_en().bit()), + ) + .field( + "tx_tdm_chan14_en", + &format_args!("{}", self.tx_tdm_chan14_en().bit()), + ) + .field( + "tx_tdm_chan15_en", + &format_args!("{}", self.tx_tdm_chan15_en().bit()), + ) + .field( + "tx_tdm_tot_chan_num", + &format_args!("{}", self.tx_tdm_tot_chan_num().bits()), + ) + .field( + "tx_tdm_skip_msk_en", + &format_args!("{}", self.tx_tdm_skip_msk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan0_en(&mut self) -> TX_TDM_CHAN0_EN_W { + TX_TDM_CHAN0_EN_W::new(self, 0) + } + #[doc = "Bit 1 - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan1_en(&mut self) -> TX_TDM_CHAN1_EN_W { + TX_TDM_CHAN1_EN_W::new(self, 1) + } + #[doc = "Bit 2 - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan2_en(&mut self) -> TX_TDM_CHAN2_EN_W { + TX_TDM_CHAN2_EN_W::new(self, 2) + } + #[doc = "Bit 3 - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan3_en(&mut self) -> TX_TDM_CHAN3_EN_W { + TX_TDM_CHAN3_EN_W::new(self, 3) + } + #[doc = "Bit 4 - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan4_en(&mut self) -> TX_TDM_CHAN4_EN_W { + TX_TDM_CHAN4_EN_W::new(self, 4) + } + #[doc = "Bit 5 - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan5_en(&mut self) -> TX_TDM_CHAN5_EN_W { + TX_TDM_CHAN5_EN_W::new(self, 5) + } + #[doc = "Bit 6 - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan6_en(&mut self) -> TX_TDM_CHAN6_EN_W { + TX_TDM_CHAN6_EN_W::new(self, 6) + } + #[doc = "Bit 7 - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan7_en(&mut self) -> TX_TDM_CHAN7_EN_W { + TX_TDM_CHAN7_EN_W::new(self, 7) + } + #[doc = "Bit 8 - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan8_en(&mut self) -> TX_TDM_CHAN8_EN_W { + TX_TDM_CHAN8_EN_W::new(self, 8) + } + #[doc = "Bit 9 - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan9_en(&mut self) -> TX_TDM_CHAN9_EN_W { + TX_TDM_CHAN9_EN_W::new(self, 9) + } + #[doc = "Bit 10 - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan10_en(&mut self) -> TX_TDM_CHAN10_EN_W { + TX_TDM_CHAN10_EN_W::new(self, 10) + } + #[doc = "Bit 11 - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan11_en(&mut self) -> TX_TDM_CHAN11_EN_W { + TX_TDM_CHAN11_EN_W::new(self, 11) + } + #[doc = "Bit 12 - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan12_en(&mut self) -> TX_TDM_CHAN12_EN_W { + TX_TDM_CHAN12_EN_W::new(self, 12) + } + #[doc = "Bit 13 - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan13_en(&mut self) -> TX_TDM_CHAN13_EN_W { + TX_TDM_CHAN13_EN_W::new(self, 13) + } + #[doc = "Bit 14 - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan14_en(&mut self) -> TX_TDM_CHAN14_EN_W { + TX_TDM_CHAN14_EN_W::new(self, 14) + } + #[doc = "Bit 15 - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_chan15_en(&mut self) -> TX_TDM_CHAN15_EN_W { + TX_TDM_CHAN15_EN_W::new(self, 15) + } + #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_tot_chan_num(&mut self) -> TX_TDM_TOT_CHAN_NUM_W { + TX_TDM_TOT_CHAN_NUM_W::new(self, 16) + } + #[doc = "Bit 20 - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels."] + #[inline(always)] + #[must_use] + pub fn tx_tdm_skip_msk_en(&mut self) -> TX_TDM_SKIP_MSK_EN_W { + TX_TDM_SKIP_MSK_EN_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S TX TDM mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_tdm_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_tdm_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_TDM_CTRL_SPEC; +impl crate::RegisterSpec for TX_TDM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_tdm_ctrl::R`](R) reader structure"] +impl crate::Readable for TX_TDM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_tdm_ctrl::W`](W) writer structure"] +impl crate::Writable for TX_TDM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_TDM_CTRL to value 0xffff"] +impl crate::Resettable for TX_TDM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0xffff; +} diff --git a/esp32p4/src/i2s0/tx_timing.rs b/esp32p4/src/i2s0/tx_timing.rs new file mode 100644 index 0000000000..ea5ec5af3d --- /dev/null +++ b/esp32p4/src/i2s0/tx_timing.rs @@ -0,0 +1,161 @@ +#[doc = "Register `TX_TIMING` reader"] +pub type R = crate::R; +#[doc = "Register `TX_TIMING` writer"] +pub type W = crate::W; +#[doc = "Field `TX_SD_OUT_DM` reader - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_SD_OUT_DM_R = crate::FieldReader; +#[doc = "Field `TX_SD_OUT_DM` writer - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_SD_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_SD1_OUT_DM` reader - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_SD1_OUT_DM_R = crate::FieldReader; +#[doc = "Field `TX_SD1_OUT_DM` writer - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_SD1_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_WS_OUT_DM` reader - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_WS_OUT_DM_R = crate::FieldReader; +#[doc = "Field `TX_WS_OUT_DM` writer - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_WS_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_BCK_OUT_DM` reader - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_BCK_OUT_DM_R = crate::FieldReader; +#[doc = "Field `TX_BCK_OUT_DM` writer - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_BCK_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_WS_IN_DM` reader - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_WS_IN_DM_R = crate::FieldReader; +#[doc = "Field `TX_WS_IN_DM` writer - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_WS_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_BCK_IN_DM` reader - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_BCK_IN_DM_R = crate::FieldReader; +#[doc = "Field `TX_BCK_IN_DM` writer - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type TX_BCK_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn tx_sd_out_dm(&self) -> TX_SD_OUT_DM_R { + TX_SD_OUT_DM_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 4:5 - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn tx_sd1_out_dm(&self) -> TX_SD1_OUT_DM_R { + TX_SD1_OUT_DM_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 16:17 - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn tx_ws_out_dm(&self) -> TX_WS_OUT_DM_R { + TX_WS_OUT_DM_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 20:21 - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn tx_bck_out_dm(&self) -> TX_BCK_OUT_DM_R { + TX_BCK_OUT_DM_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 24:25 - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn tx_ws_in_dm(&self) -> TX_WS_IN_DM_R { + TX_WS_IN_DM_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 28:29 - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn tx_bck_in_dm(&self) -> TX_BCK_IN_DM_R { + TX_BCK_IN_DM_R::new(((self.bits >> 28) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_TIMING") + .field( + "tx_sd_out_dm", + &format_args!("{}", self.tx_sd_out_dm().bits()), + ) + .field( + "tx_sd1_out_dm", + &format_args!("{}", self.tx_sd1_out_dm().bits()), + ) + .field( + "tx_ws_out_dm", + &format_args!("{}", self.tx_ws_out_dm().bits()), + ) + .field( + "tx_bck_out_dm", + &format_args!("{}", self.tx_bck_out_dm().bits()), + ) + .field( + "tx_ws_in_dm", + &format_args!("{}", self.tx_ws_in_dm().bits()), + ) + .field( + "tx_bck_in_dm", + &format_args!("{}", self.tx_bck_in_dm().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn tx_sd_out_dm(&mut self) -> TX_SD_OUT_DM_W { + TX_SD_OUT_DM_W::new(self, 0) + } + #[doc = "Bits 4:5 - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn tx_sd1_out_dm(&mut self) -> TX_SD1_OUT_DM_W { + TX_SD1_OUT_DM_W::new(self, 4) + } + #[doc = "Bits 16:17 - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn tx_ws_out_dm(&mut self) -> TX_WS_OUT_DM_W { + TX_WS_OUT_DM_W::new(self, 16) + } + #[doc = "Bits 20:21 - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn tx_bck_out_dm(&mut self) -> TX_BCK_OUT_DM_W { + TX_BCK_OUT_DM_W::new(self, 20) + } + #[doc = "Bits 24:25 - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn tx_ws_in_dm(&mut self) -> TX_WS_IN_DM_W { + TX_WS_IN_DM_W::new(self, 24) + } + #[doc = "Bits 28:29 - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn tx_bck_in_dm(&mut self) -> TX_BCK_IN_DM_W { + TX_BCK_IN_DM_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S TX timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_timing::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_timing::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_TIMING_SPEC; +impl crate::RegisterSpec for TX_TIMING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_timing::R`](R) reader structure"] +impl crate::Readable for TX_TIMING_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_timing::W`](W) writer structure"] +impl crate::Writable for TX_TIMING_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_TIMING to value 0"] +impl crate::Resettable for TX_TIMING_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst.rs b/esp32p4/src/i3c_mst.rs new file mode 100644 index 0000000000..b5da9296bc --- /dev/null +++ b/esp32p4/src/i3c_mst.rs @@ -0,0 +1,374 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + device_ctrl: DEVICE_CTRL, + _reserved1: [u8; 0x18], + buffer_thld_ctrl: BUFFER_THLD_CTRL, + data_buffer_thld_ctrl: DATA_BUFFER_THLD_CTRL, + ibi_notify_ctrl: IBI_NOTIFY_CTRL, + ibi_sir_req_payload: IBI_SIR_REQ_PAYLOAD, + ibi_sir_req_reject: IBI_SIR_REQ_REJECT, + int_clr: INT_CLR, + int_raw: INT_RAW, + int_st: INT_ST, + int_st_ena: INT_ST_ENA, + _reserved10: [u8; 0x04], + reset_ctrl: RESET_CTRL, + buffer_status_level: BUFFER_STATUS_LEVEL, + data_buffer_status_level: DATA_BUFFER_STATUS_LEVEL, + present_state0: PRESENT_STATE0, + present_state1: PRESENT_STATE1, + device_table: DEVICE_TABLE, + time_out_value: TIME_OUT_VALUE, + scl_i3c_mst_od_time: SCL_I3C_MST_OD_TIME, + scl_i3c_mst_pp_time: SCL_I3C_MST_PP_TIME, + scl_i2c_fm_time: SCL_I2C_FM_TIME, + scl_i2c_fmp_time: SCL_I2C_FMP_TIME, + scl_ext_low_time: SCL_EXT_LOW_TIME, + sda_sample_time: SDA_SAMPLE_TIME, + sda_hold_time: SDA_HOLD_TIME, + scl_start_hold: SCL_START_HOLD, + scl_rstart_setup: SCL_RSTART_SETUP, + scl_stop_hold: SCL_STOP_HOLD, + scl_stop_setup: SCL_STOP_SETUP, + _reserved28: [u8; 0x04], + bus_free_time: BUS_FREE_TIME, + scl_termn_t_ext_low_time: SCL_TERMN_T_EXT_LOW_TIME, + _reserved30: [u8; 0x08], + ver_id: VER_ID, + ver_type: VER_TYPE, + _reserved32: [u8; 0x04], + fpga_debug_probe: FPGA_DEBUG_PROBE, + rnd_eco_cs: RND_ECO_CS, + rnd_eco_low: RND_ECO_LOW, + rnd_eco_high: RND_ECO_HIGH, +} +impl RegisterBlock { + #[doc = "0x00 - DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities."] + #[inline(always)] + pub const fn device_ctrl(&self) -> &DEVICE_CTRL { + &self.device_ctrl + } + #[doc = "0x1c - In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt."] + #[inline(always)] + pub const fn buffer_thld_ctrl(&self) -> &BUFFER_THLD_CTRL { + &self.buffer_thld_ctrl + } + #[doc = "0x20 - NA"] + #[inline(always)] + pub const fn data_buffer_thld_ctrl(&self) -> &DATA_BUFFER_THLD_CTRL { + &self.data_buffer_thld_ctrl + } + #[doc = "0x24 - NA"] + #[inline(always)] + pub const fn ibi_notify_ctrl(&self) -> &IBI_NOTIFY_CTRL { + &self.ibi_notify_ctrl + } + #[doc = "0x28 - NA"] + #[inline(always)] + pub const fn ibi_sir_req_payload(&self) -> &IBI_SIR_REQ_PAYLOAD { + &self.ibi_sir_req_payload + } + #[doc = "0x2c - NA"] + #[inline(always)] + pub const fn ibi_sir_req_reject(&self) -> &IBI_SIR_REQ_REJECT { + &self.ibi_sir_req_reject + } + #[doc = "0x30 - NA"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x34 - NA"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x38 - NA"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x3c - The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set."] + #[inline(always)] + pub const fn int_st_ena(&self) -> &INT_ST_ENA { + &self.int_st_ena + } + #[doc = "0x44 - NA"] + #[inline(always)] + pub const fn reset_ctrl(&self) -> &RESET_CTRL { + &self.reset_ctrl + } + #[doc = "0x48 - BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller."] + #[inline(always)] + pub const fn buffer_status_level(&self) -> &BUFFER_STATUS_LEVEL { + &self.buffer_status_level + } + #[doc = "0x4c - DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller."] + #[inline(always)] + pub const fn data_buffer_status_level(&self) -> &DATA_BUFFER_STATUS_LEVEL { + &self.data_buffer_status_level + } + #[doc = "0x50 - NA"] + #[inline(always)] + pub const fn present_state0(&self) -> &PRESENT_STATE0 { + &self.present_state0 + } + #[doc = "0x54 - NA"] + #[inline(always)] + pub const fn present_state1(&self) -> &PRESENT_STATE1 { + &self.present_state1 + } + #[doc = "0x58 - Pointer for Device Address Table"] + #[inline(always)] + pub const fn device_table(&self) -> &DEVICE_TABLE { + &self.device_table + } + #[doc = "0x5c - NA"] + #[inline(always)] + pub const fn time_out_value(&self) -> &TIME_OUT_VALUE { + &self.time_out_value + } + #[doc = "0x60 - NA"] + #[inline(always)] + pub const fn scl_i3c_mst_od_time(&self) -> &SCL_I3C_MST_OD_TIME { + &self.scl_i3c_mst_od_time + } + #[doc = "0x64 - NA"] + #[inline(always)] + pub const fn scl_i3c_mst_pp_time(&self) -> &SCL_I3C_MST_PP_TIME { + &self.scl_i3c_mst_pp_time + } + #[doc = "0x68 - NA"] + #[inline(always)] + pub const fn scl_i2c_fm_time(&self) -> &SCL_I2C_FM_TIME { + &self.scl_i2c_fm_time + } + #[doc = "0x6c - NA"] + #[inline(always)] + pub const fn scl_i2c_fmp_time(&self) -> &SCL_I2C_FMP_TIME { + &self.scl_i2c_fmp_time + } + #[doc = "0x70 - NA"] + #[inline(always)] + pub const fn scl_ext_low_time(&self) -> &SCL_EXT_LOW_TIME { + &self.scl_ext_low_time + } + #[doc = "0x74 - NA"] + #[inline(always)] + pub const fn sda_sample_time(&self) -> &SDA_SAMPLE_TIME { + &self.sda_sample_time + } + #[doc = "0x78 - NA"] + #[inline(always)] + pub const fn sda_hold_time(&self) -> &SDA_HOLD_TIME { + &self.sda_hold_time + } + #[doc = "0x7c - NA"] + #[inline(always)] + pub const fn scl_start_hold(&self) -> &SCL_START_HOLD { + &self.scl_start_hold + } + #[doc = "0x80 - NA"] + #[inline(always)] + pub const fn scl_rstart_setup(&self) -> &SCL_RSTART_SETUP { + &self.scl_rstart_setup + } + #[doc = "0x84 - NA"] + #[inline(always)] + pub const fn scl_stop_hold(&self) -> &SCL_STOP_HOLD { + &self.scl_stop_hold + } + #[doc = "0x88 - NA"] + #[inline(always)] + pub const fn scl_stop_setup(&self) -> &SCL_STOP_SETUP { + &self.scl_stop_setup + } + #[doc = "0x90 - NA"] + #[inline(always)] + pub const fn bus_free_time(&self) -> &BUS_FREE_TIME { + &self.bus_free_time + } + #[doc = "0x94 - NA"] + #[inline(always)] + pub const fn scl_termn_t_ext_low_time(&self) -> &SCL_TERMN_T_EXT_LOW_TIME { + &self.scl_termn_t_ext_low_time + } + #[doc = "0xa0 - NA"] + #[inline(always)] + pub const fn ver_id(&self) -> &VER_ID { + &self.ver_id + } + #[doc = "0xa4 - NA"] + #[inline(always)] + pub const fn ver_type(&self) -> &VER_TYPE { + &self.ver_type + } + #[doc = "0xac - NA"] + #[inline(always)] + pub const fn fpga_debug_probe(&self) -> &FPGA_DEBUG_PROBE { + &self.fpga_debug_probe + } + #[doc = "0xb0 - NA"] + #[inline(always)] + pub const fn rnd_eco_cs(&self) -> &RND_ECO_CS { + &self.rnd_eco_cs + } + #[doc = "0xb4 - NA"] + #[inline(always)] + pub const fn rnd_eco_low(&self) -> &RND_ECO_LOW { + &self.rnd_eco_low + } + #[doc = "0xb8 - NA"] + #[inline(always)] + pub const fn rnd_eco_high(&self) -> &RND_ECO_HIGH { + &self.rnd_eco_high + } +} +#[doc = "DEVICE_CTRL (rw) register accessor: DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`device_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`device_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@device_ctrl`] module"] +pub type DEVICE_CTRL = crate::Reg; +#[doc = "DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities."] +pub mod device_ctrl; +#[doc = "BUFFER_THLD_CTRL (rw) register accessor: In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buffer_thld_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buffer_thld_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@buffer_thld_ctrl`] module"] +pub type BUFFER_THLD_CTRL = crate::Reg; +#[doc = "In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt."] +pub mod buffer_thld_ctrl; +#[doc = "DATA_BUFFER_THLD_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_buffer_thld_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_buffer_thld_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_buffer_thld_ctrl`] module"] +pub type DATA_BUFFER_THLD_CTRL = crate::Reg; +#[doc = "NA"] +pub mod data_buffer_thld_ctrl; +#[doc = "IBI_NOTIFY_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_notify_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibi_notify_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibi_notify_ctrl`] module"] +pub type IBI_NOTIFY_CTRL = crate::Reg; +#[doc = "NA"] +pub mod ibi_notify_ctrl; +#[doc = "IBI_SIR_REQ_PAYLOAD (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_sir_req_payload::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibi_sir_req_payload::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibi_sir_req_payload`] module"] +pub type IBI_SIR_REQ_PAYLOAD = crate::Reg; +#[doc = "NA"] +pub mod ibi_sir_req_payload; +#[doc = "IBI_SIR_REQ_REJECT (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_sir_req_reject::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibi_sir_req_reject::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibi_sir_req_reject`] module"] +pub type IBI_SIR_REQ_REJECT = crate::Reg; +#[doc = "NA"] +pub mod ibi_sir_req_reject; +#[doc = "INT_CLR (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "NA"] +pub mod int_clr; +#[doc = "INT_RAW (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "NA"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "NA"] +pub mod int_st; +#[doc = "INT_ST_ENA (rw) register accessor: The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_st_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_ena`] module"] +pub type INT_ST_ENA = crate::Reg; +#[doc = "The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set."] +pub mod int_st_ena; +#[doc = "RESET_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_ctrl`] module"] +pub type RESET_CTRL = crate::Reg; +#[doc = "NA"] +pub mod reset_ctrl; +#[doc = "BUFFER_STATUS_LEVEL (r) register accessor: BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buffer_status_level::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@buffer_status_level`] module"] +pub type BUFFER_STATUS_LEVEL = crate::Reg; +#[doc = "BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller."] +pub mod buffer_status_level; +#[doc = "DATA_BUFFER_STATUS_LEVEL (r) register accessor: DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_buffer_status_level::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_buffer_status_level`] module"] +pub type DATA_BUFFER_STATUS_LEVEL = + crate::Reg; +#[doc = "DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller."] +pub mod data_buffer_status_level; +#[doc = "PRESENT_STATE0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`present_state0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@present_state0`] module"] +pub type PRESENT_STATE0 = crate::Reg; +#[doc = "NA"] +pub mod present_state0; +#[doc = "PRESENT_STATE1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`present_state1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@present_state1`] module"] +pub type PRESENT_STATE1 = crate::Reg; +#[doc = "NA"] +pub mod present_state1; +#[doc = "DEVICE_TABLE (rw) register accessor: Pointer for Device Address Table\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`device_table::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`device_table::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@device_table`] module"] +pub type DEVICE_TABLE = crate::Reg; +#[doc = "Pointer for Device Address Table"] +pub mod device_table; +#[doc = "TIME_OUT_VALUE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_out_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time_out_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@time_out_value`] module"] +pub type TIME_OUT_VALUE = crate::Reg; +#[doc = "NA"] +pub mod time_out_value; +#[doc = "SCL_I3C_MST_OD_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_i3c_mst_od_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_i3c_mst_od_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_i3c_mst_od_time`] module"] +pub type SCL_I3C_MST_OD_TIME = crate::Reg; +#[doc = "NA"] +pub mod scl_i3c_mst_od_time; +#[doc = "SCL_I3C_MST_PP_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_i3c_mst_pp_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_i3c_mst_pp_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_i3c_mst_pp_time`] module"] +pub type SCL_I3C_MST_PP_TIME = crate::Reg; +#[doc = "NA"] +pub mod scl_i3c_mst_pp_time; +#[doc = "SCL_I2C_FM_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_i2c_fm_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_i2c_fm_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_i2c_fm_time`] module"] +pub type SCL_I2C_FM_TIME = crate::Reg; +#[doc = "NA"] +pub mod scl_i2c_fm_time; +#[doc = "SCL_I2C_FMP_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_i2c_fmp_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_i2c_fmp_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_i2c_fmp_time`] module"] +pub type SCL_I2C_FMP_TIME = crate::Reg; +#[doc = "NA"] +pub mod scl_i2c_fmp_time; +#[doc = "SCL_EXT_LOW_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_ext_low_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_ext_low_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_ext_low_time`] module"] +pub type SCL_EXT_LOW_TIME = crate::Reg; +#[doc = "NA"] +pub mod scl_ext_low_time; +#[doc = "SDA_SAMPLE_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_sample_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_sample_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_sample_time`] module"] +pub type SDA_SAMPLE_TIME = crate::Reg; +#[doc = "NA"] +pub mod sda_sample_time; +#[doc = "SDA_HOLD_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold_time`] module"] +pub type SDA_HOLD_TIME = crate::Reg; +#[doc = "NA"] +pub mod sda_hold_time; +#[doc = "SCL_START_HOLD (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_start_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_start_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_start_hold`] module"] +pub type SCL_START_HOLD = crate::Reg; +#[doc = "NA"] +pub mod scl_start_hold; +#[doc = "SCL_RSTART_SETUP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_rstart_setup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_rstart_setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_rstart_setup`] module"] +pub type SCL_RSTART_SETUP = crate::Reg; +#[doc = "NA"] +pub mod scl_rstart_setup; +#[doc = "SCL_STOP_HOLD (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stop_hold`] module"] +pub type SCL_STOP_HOLD = crate::Reg; +#[doc = "NA"] +pub mod scl_stop_hold; +#[doc = "SCL_STOP_SETUP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_setup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stop_setup`] module"] +pub type SCL_STOP_SETUP = crate::Reg; +#[doc = "NA"] +pub mod scl_stop_setup; +#[doc = "BUS_FREE_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_free_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_free_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_free_time`] module"] +pub type BUS_FREE_TIME = crate::Reg; +#[doc = "NA"] +pub mod bus_free_time; +#[doc = "SCL_TERMN_T_EXT_LOW_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_termn_t_ext_low_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_termn_t_ext_low_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_termn_t_ext_low_time`] module"] +pub type SCL_TERMN_T_EXT_LOW_TIME = + crate::Reg; +#[doc = "NA"] +pub mod scl_termn_t_ext_low_time; +#[doc = "VER_ID (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ver_id`] module"] +pub type VER_ID = crate::Reg; +#[doc = "NA"] +pub mod ver_id; +#[doc = "VER_TYPE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ver_type`] module"] +pub type VER_TYPE = crate::Reg; +#[doc = "NA"] +pub mod ver_type; +#[doc = "FPGA_DEBUG_PROBE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpga_debug_probe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpga_debug_probe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpga_debug_probe`] module"] +pub type FPGA_DEBUG_PROBE = crate::Reg; +#[doc = "NA"] +pub mod fpga_debug_probe; +#[doc = "RND_ECO_CS (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_cs`] module"] +pub type RND_ECO_CS = crate::Reg; +#[doc = "NA"] +pub mod rnd_eco_cs; +#[doc = "RND_ECO_LOW (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_low`] module"] +pub type RND_ECO_LOW = crate::Reg; +#[doc = "NA"] +pub mod rnd_eco_low; +#[doc = "RND_ECO_HIGH (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_high`] module"] +pub type RND_ECO_HIGH = crate::Reg; +#[doc = "NA"] +pub mod rnd_eco_high; diff --git a/esp32p4/src/i3c_mst/buffer_status_level.rs b/esp32p4/src/i3c_mst/buffer_status_level.rs new file mode 100644 index 0000000000..9d15a71358 --- /dev/null +++ b/esp32p4/src/i3c_mst/buffer_status_level.rs @@ -0,0 +1,72 @@ +#[doc = "Register `BUFFER_STATUS_LEVEL` reader"] +pub type R = crate::R; +#[doc = "Field `CMD_BUF_EMPTY_CNT` reader - Command Buffer Empty Locations contains the number of empty locations in the command buffer."] +pub type CMD_BUF_EMPTY_CNT_R = crate::FieldReader; +#[doc = "Field `RESP_BUF_CNT` reader - Response Buffer Level Value contains the number of valid data entries in the response buffer."] +pub type RESP_BUF_CNT_R = crate::FieldReader; +#[doc = "Field `IBI_DATA_BUF_CNT` reader - IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This is field is used in master mode."] +pub type IBI_DATA_BUF_CNT_R = crate::FieldReader; +#[doc = "Field `IBI_STATUS_BUF_CNT` reader - IBI Buffer Status Count contains the number of IBI status entries in the IBI Buffer. This field is used in master mode."] +pub type IBI_STATUS_BUF_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - Command Buffer Empty Locations contains the number of empty locations in the command buffer."] + #[inline(always)] + pub fn cmd_buf_empty_cnt(&self) -> CMD_BUF_EMPTY_CNT_R { + CMD_BUF_EMPTY_CNT_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:11 - Response Buffer Level Value contains the number of valid data entries in the response buffer."] + #[inline(always)] + pub fn resp_buf_cnt(&self) -> RESP_BUF_CNT_R { + RESP_BUF_CNT_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This is field is used in master mode."] + #[inline(always)] + pub fn ibi_data_buf_cnt(&self) -> IBI_DATA_BUF_CNT_R { + IBI_DATA_BUF_CNT_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - IBI Buffer Status Count contains the number of IBI status entries in the IBI Buffer. This field is used in master mode."] + #[inline(always)] + pub fn ibi_status_buf_cnt(&self) -> IBI_STATUS_BUF_CNT_R { + IBI_STATUS_BUF_CNT_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUFFER_STATUS_LEVEL") + .field( + "cmd_buf_empty_cnt", + &format_args!("{}", self.cmd_buf_empty_cnt().bits()), + ) + .field( + "resp_buf_cnt", + &format_args!("{}", self.resp_buf_cnt().bits()), + ) + .field( + "ibi_data_buf_cnt", + &format_args!("{}", self.ibi_data_buf_cnt().bits()), + ) + .field( + "ibi_status_buf_cnt", + &format_args!("{}", self.ibi_status_buf_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buffer_status_level::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUFFER_STATUS_LEVEL_SPEC; +impl crate::RegisterSpec for BUFFER_STATUS_LEVEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`buffer_status_level::R`](R) reader structure"] +impl crate::Readable for BUFFER_STATUS_LEVEL_SPEC {} +#[doc = "`reset()` method sets BUFFER_STATUS_LEVEL to value 0x10"] +impl crate::Resettable for BUFFER_STATUS_LEVEL_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/esp32p4/src/i3c_mst/buffer_thld_ctrl.rs b/esp32p4/src/i3c_mst/buffer_thld_ctrl.rs new file mode 100644 index 0000000000..3f78420502 --- /dev/null +++ b/esp32p4/src/i3c_mst/buffer_thld_ctrl.rs @@ -0,0 +1,123 @@ +#[doc = "Register `BUFFER_THLD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `BUFFER_THLD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `REG_CMD_BUF_EMPTY_THLD` reader - Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt."] +pub type REG_CMD_BUF_EMPTY_THLD_R = crate::FieldReader; +#[doc = "Field `REG_CMD_BUF_EMPTY_THLD` writer - Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt."] +pub type REG_CMD_BUF_EMPTY_THLD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `REG_RESP_BUF_THLD` reader - Response Buffer Threshold Value is used to control the number of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR."] +pub type REG_RESP_BUF_THLD_R = crate::FieldReader; +#[doc = "Field `REG_RESP_BUF_THLD` writer - Response Buffer Threshold Value is used to control the number of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR."] +pub type REG_RESP_BUF_THLD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_IBI_DATA_BUF_THLD` reader - In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI data entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt."] +pub type REG_IBI_DATA_BUF_THLD_R = crate::FieldReader; +#[doc = "Field `REG_IBI_DATA_BUF_THLD` writer - In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI data entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt."] +pub type REG_IBI_DATA_BUF_THLD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_IBI_STATUS_BUF_THLD` reader - NA"] +pub type REG_IBI_STATUS_BUF_THLD_R = crate::FieldReader; +#[doc = "Field `REG_IBI_STATUS_BUF_THLD` writer - NA"] +pub type REG_IBI_STATUS_BUF_THLD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:3 - Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt."] + #[inline(always)] + pub fn reg_cmd_buf_empty_thld(&self) -> REG_CMD_BUF_EMPTY_THLD_R { + REG_CMD_BUF_EMPTY_THLD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 6:8 - Response Buffer Threshold Value is used to control the number of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR."] + #[inline(always)] + pub fn reg_resp_buf_thld(&self) -> REG_RESP_BUF_THLD_R { + REG_RESP_BUF_THLD_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 12:14 - In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI data entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt."] + #[inline(always)] + pub fn reg_ibi_data_buf_thld(&self) -> REG_IBI_DATA_BUF_THLD_R { + REG_IBI_DATA_BUF_THLD_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 18:20 - NA"] + #[inline(always)] + pub fn reg_ibi_status_buf_thld(&self) -> REG_IBI_STATUS_BUF_THLD_R { + REG_IBI_STATUS_BUF_THLD_R::new(((self.bits >> 18) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUFFER_THLD_CTRL") + .field( + "reg_cmd_buf_empty_thld", + &format_args!("{}", self.reg_cmd_buf_empty_thld().bits()), + ) + .field( + "reg_resp_buf_thld", + &format_args!("{}", self.reg_resp_buf_thld().bits()), + ) + .field( + "reg_ibi_data_buf_thld", + &format_args!("{}", self.reg_ibi_data_buf_thld().bits()), + ) + .field( + "reg_ibi_status_buf_thld", + &format_args!("{}", self.reg_ibi_status_buf_thld().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt."] + #[inline(always)] + #[must_use] + pub fn reg_cmd_buf_empty_thld(&mut self) -> REG_CMD_BUF_EMPTY_THLD_W { + REG_CMD_BUF_EMPTY_THLD_W::new(self, 0) + } + #[doc = "Bits 6:8 - Response Buffer Threshold Value is used to control the number of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR."] + #[inline(always)] + #[must_use] + pub fn reg_resp_buf_thld(&mut self) -> REG_RESP_BUF_THLD_W { + REG_RESP_BUF_THLD_W::new(self, 6) + } + #[doc = "Bits 12:14 - In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI data entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt."] + #[inline(always)] + #[must_use] + pub fn reg_ibi_data_buf_thld(&mut self) -> REG_IBI_DATA_BUF_THLD_W { + REG_IBI_DATA_BUF_THLD_W::new(self, 12) + } + #[doc = "Bits 18:20 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_ibi_status_buf_thld(&mut self) -> REG_IBI_STATUS_BUF_THLD_W { + REG_IBI_STATUS_BUF_THLD_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buffer_thld_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buffer_thld_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUFFER_THLD_CTRL_SPEC; +impl crate::RegisterSpec for BUFFER_THLD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`buffer_thld_ctrl::R`](R) reader structure"] +impl crate::Readable for BUFFER_THLD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`buffer_thld_ctrl::W`](W) writer structure"] +impl crate::Writable for BUFFER_THLD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BUFFER_THLD_CTRL to value 0x0004_1041"] +impl crate::Resettable for BUFFER_THLD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0004_1041; +} diff --git a/esp32p4/src/i3c_mst/bus_free_time.rs b/esp32p4/src/i3c_mst/bus_free_time.rs new file mode 100644 index 0000000000..c1f749987f --- /dev/null +++ b/esp32p4/src/i3c_mst/bus_free_time.rs @@ -0,0 +1,66 @@ +#[doc = "Register `BUS_FREE_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `BUS_FREE_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `REG_BUS_FREE_TIME` reader - I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing."] +pub type REG_BUS_FREE_TIME_R = crate::FieldReader; +#[doc = "Field `REG_BUS_FREE_TIME` writer - I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing."] +pub type REG_BUS_FREE_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing."] + #[inline(always)] + pub fn reg_bus_free_time(&self) -> REG_BUS_FREE_TIME_R { + REG_BUS_FREE_TIME_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUS_FREE_TIME") + .field( + "reg_bus_free_time", + &format_args!("{}", self.reg_bus_free_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing."] + #[inline(always)] + #[must_use] + pub fn reg_bus_free_time(&mut self) -> REG_BUS_FREE_TIME_W { + REG_BUS_FREE_TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_free_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_free_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUS_FREE_TIME_SPEC; +impl crate::RegisterSpec for BUS_FREE_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bus_free_time::R`](R) reader structure"] +impl crate::Readable for BUS_FREE_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bus_free_time::W`](W) writer structure"] +impl crate::Writable for BUS_FREE_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BUS_FREE_TIME to value 0x05"] +impl crate::Resettable for BUS_FREE_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0x05; +} diff --git a/esp32p4/src/i3c_mst/data_buffer_status_level.rs b/esp32p4/src/i3c_mst/data_buffer_status_level.rs new file mode 100644 index 0000000000..4d16535741 --- /dev/null +++ b/esp32p4/src/i3c_mst/data_buffer_status_level.rs @@ -0,0 +1,50 @@ +#[doc = "Register `DATA_BUFFER_STATUS_LEVEL` reader"] +pub type R = crate::R; +#[doc = "Field `TX_DATA_BUF_EMPTY_CNT` reader - Transmit Buffer Empty Level Value contains the number of empty locations in the transmit Buffer."] +pub type TX_DATA_BUF_EMPTY_CNT_R = crate::FieldReader; +#[doc = "Field `RX_DATA_BUF_CNT` reader - Receive Buffer Level value contains the number of valid data entries in the receive buffer."] +pub type RX_DATA_BUF_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:5 - Transmit Buffer Empty Level Value contains the number of empty locations in the transmit Buffer."] + #[inline(always)] + pub fn tx_data_buf_empty_cnt(&self) -> TX_DATA_BUF_EMPTY_CNT_R { + TX_DATA_BUF_EMPTY_CNT_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 16:21 - Receive Buffer Level value contains the number of valid data entries in the receive buffer."] + #[inline(always)] + pub fn rx_data_buf_cnt(&self) -> RX_DATA_BUF_CNT_R { + RX_DATA_BUF_CNT_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_BUFFER_STATUS_LEVEL") + .field( + "tx_data_buf_empty_cnt", + &format_args!("{}", self.tx_data_buf_empty_cnt().bits()), + ) + .field( + "rx_data_buf_cnt", + &format_args!("{}", self.rx_data_buf_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_buffer_status_level::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_BUFFER_STATUS_LEVEL_SPEC; +impl crate::RegisterSpec for DATA_BUFFER_STATUS_LEVEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_buffer_status_level::R`](R) reader structure"] +impl crate::Readable for DATA_BUFFER_STATUS_LEVEL_SPEC {} +#[doc = "`reset()` method sets DATA_BUFFER_STATUS_LEVEL to value 0x20"] +impl crate::Resettable for DATA_BUFFER_STATUS_LEVEL_SPEC { + const RESET_VALUE: Self::Ux = 0x20; +} diff --git a/esp32p4/src/i3c_mst/data_buffer_thld_ctrl.rs b/esp32p4/src/i3c_mst/data_buffer_thld_ctrl.rs new file mode 100644 index 0000000000..e198c72e5c --- /dev/null +++ b/esp32p4/src/i3c_mst/data_buffer_thld_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DATA_BUFFER_THLD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_BUFFER_THLD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `REG_TX_DATA_BUF_THLD` reader - Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31"] +pub type REG_TX_DATA_BUF_THLD_R = crate::FieldReader; +#[doc = "Field `REG_TX_DATA_BUF_THLD` writer - Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31"] +pub type REG_TX_DATA_BUF_THLD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_RX_DATA_BUF_THLD` reader - Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31"] +pub type REG_RX_DATA_BUF_THLD_R = crate::FieldReader; +#[doc = "Field `REG_RX_DATA_BUF_THLD` writer - Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31"] +pub type REG_RX_DATA_BUF_THLD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31"] + #[inline(always)] + pub fn reg_tx_data_buf_thld(&self) -> REG_TX_DATA_BUF_THLD_R { + REG_TX_DATA_BUF_THLD_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31"] + #[inline(always)] + pub fn reg_rx_data_buf_thld(&self) -> REG_RX_DATA_BUF_THLD_R { + REG_RX_DATA_BUF_THLD_R::new(((self.bits >> 3) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_BUFFER_THLD_CTRL") + .field( + "reg_tx_data_buf_thld", + &format_args!("{}", self.reg_tx_data_buf_thld().bits()), + ) + .field( + "reg_rx_data_buf_thld", + &format_args!("{}", self.reg_rx_data_buf_thld().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31"] + #[inline(always)] + #[must_use] + pub fn reg_tx_data_buf_thld(&mut self) -> REG_TX_DATA_BUF_THLD_W { + REG_TX_DATA_BUF_THLD_W::new(self, 0) + } + #[doc = "Bits 3:5 - Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31"] + #[inline(always)] + #[must_use] + pub fn reg_rx_data_buf_thld(&mut self) -> REG_RX_DATA_BUF_THLD_W { + REG_RX_DATA_BUF_THLD_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_buffer_thld_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_buffer_thld_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_BUFFER_THLD_CTRL_SPEC; +impl crate::RegisterSpec for DATA_BUFFER_THLD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_buffer_thld_ctrl::R`](R) reader structure"] +impl crate::Readable for DATA_BUFFER_THLD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_buffer_thld_ctrl::W`](W) writer structure"] +impl crate::Writable for DATA_BUFFER_THLD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_BUFFER_THLD_CTRL to value 0x09"] +impl crate::Resettable for DATA_BUFFER_THLD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x09; +} diff --git a/esp32p4/src/i3c_mst/device_ctrl.rs b/esp32p4/src/i3c_mst/device_ctrl.rs new file mode 100644 index 0000000000..e4048a2940 --- /dev/null +++ b/esp32p4/src/i3c_mst/device_ctrl.rs @@ -0,0 +1,371 @@ +#[doc = "Register `DEVICE_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DEVICE_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `REG_BA_INCLUDE` reader - This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed)"] +pub type REG_BA_INCLUDE_R = crate::BitReader; +#[doc = "Field `REG_BA_INCLUDE` writer - This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed)"] +pub type REG_BA_INCLUDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TRANS_START` reader - Transfer Start"] +pub type REG_TRANS_START_R = crate::BitReader; +#[doc = "Field `REG_TRANS_START` writer - Transfer Start"] +pub type REG_TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CLK_EN` reader - NA"] +pub type REG_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CLK_EN` writer - NA"] +pub type REG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_IBI_RSTART_TRANS_EN` reader - NA"] +pub type REG_IBI_RSTART_TRANS_EN_R = crate::BitReader; +#[doc = "Field `REG_IBI_RSTART_TRANS_EN` writer - NA"] +pub type REG_IBI_RSTART_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_AUTO_DIS_IBI_EN` reader - NA"] +pub type REG_AUTO_DIS_IBI_EN_R = crate::BitReader; +#[doc = "Field `REG_AUTO_DIS_IBI_EN` writer - NA"] +pub type REG_AUTO_DIS_IBI_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_DMA_RX_EN` reader - NA"] +pub type REG_DMA_RX_EN_R = crate::BitReader; +#[doc = "Field `REG_DMA_RX_EN` writer - NA"] +pub type REG_DMA_RX_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_DMA_TX_EN` reader - NA"] +pub type REG_DMA_TX_EN_R = crate::BitReader; +#[doc = "Field `REG_DMA_TX_EN` writer - NA"] +pub type REG_DMA_TX_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MULTI_SLV_SINGLE_CCC_EN` reader - 0: rx high bit first, 1: rx low bit first"] +pub type REG_MULTI_SLV_SINGLE_CCC_EN_R = crate::BitReader; +#[doc = "Field `REG_MULTI_SLV_SINGLE_CCC_EN` writer - 0: rx high bit first, 1: rx low bit first"] +pub type REG_MULTI_SLV_SINGLE_CCC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RX_BIT_ORDER` reader - 0: rx low byte fist, 1: rx high byte first"] +pub type REG_RX_BIT_ORDER_R = crate::BitReader; +#[doc = "Field `REG_RX_BIT_ORDER` writer - 0: rx low byte fist, 1: rx high byte first"] +pub type REG_RX_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RX_BYTE_ORDER` reader - NA"] +pub type REG_RX_BYTE_ORDER_R = crate::BitReader; +#[doc = "Field `REG_RX_BYTE_ORDER` writer - NA"] +pub type REG_RX_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SCL_PULLUP_FORCE_EN` reader - This bit is used to force scl_pullup_en"] +pub type REG_SCL_PULLUP_FORCE_EN_R = crate::BitReader; +#[doc = "Field `REG_SCL_PULLUP_FORCE_EN` writer - This bit is used to force scl_pullup_en"] +pub type REG_SCL_PULLUP_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SCL_OE_FORCE_EN` reader - This bit is used to force scl_oe"] +pub type REG_SCL_OE_FORCE_EN_R = crate::BitReader; +#[doc = "Field `REG_SCL_OE_FORCE_EN` writer - This bit is used to force scl_oe"] +pub type REG_SCL_OE_FORCE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SDA_PP_RD_PULLUP_EN` reader - NA"] +pub type REG_SDA_PP_RD_PULLUP_EN_R = crate::BitReader; +#[doc = "Field `REG_SDA_PP_RD_PULLUP_EN` writer - NA"] +pub type REG_SDA_PP_RD_PULLUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SDA_RD_TBIT_HLVL_PULLUP_EN` reader - NA"] +pub type REG_SDA_RD_TBIT_HLVL_PULLUP_EN_R = crate::BitReader; +#[doc = "Field `REG_SDA_RD_TBIT_HLVL_PULLUP_EN` writer - NA"] +pub type REG_SDA_RD_TBIT_HLVL_PULLUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_SDA_PP_WR_PULLUP_EN` reader - NA"] +pub type REG_SDA_PP_WR_PULLUP_EN_R = crate::BitReader; +#[doc = "Field `REG_SDA_PP_WR_PULLUP_EN` writer - NA"] +pub type REG_SDA_PP_WR_PULLUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_DATA_BYTE_CNT_UNLATCH` reader - 1: read current real-time updated value 0: read latch data byte cnt value"] +pub type REG_DATA_BYTE_CNT_UNLATCH_R = crate::BitReader; +#[doc = "Field `REG_DATA_BYTE_CNT_UNLATCH` writer - 1: read current real-time updated value 0: read latch data byte cnt value"] +pub type REG_DATA_BYTE_CNT_UNLATCH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_MEM_CLK_FORCE_ON` reader - 1: dev characteristic and address table memory clk date force on . 0 : clock gating by rd/wr."] +pub type REG_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `REG_MEM_CLK_FORCE_ON` writer - 1: dev characteristic and address table memory clk date force on . 0 : clock gating by rd/wr."] +pub type REG_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed)"] + #[inline(always)] + pub fn reg_ba_include(&self) -> REG_BA_INCLUDE_R { + REG_BA_INCLUDE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Transfer Start"] + #[inline(always)] + pub fn reg_trans_start(&self) -> REG_TRANS_START_R { + REG_TRANS_START_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn reg_clk_en(&self) -> REG_CLK_EN_R { + REG_CLK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn reg_ibi_rstart_trans_en(&self) -> REG_IBI_RSTART_TRANS_EN_R { + REG_IBI_RSTART_TRANS_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn reg_auto_dis_ibi_en(&self) -> REG_AUTO_DIS_IBI_EN_R { + REG_AUTO_DIS_IBI_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn reg_dma_rx_en(&self) -> REG_DMA_RX_EN_R { + REG_DMA_RX_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn reg_dma_tx_en(&self) -> REG_DMA_TX_EN_R { + REG_DMA_TX_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - 0: rx high bit first, 1: rx low bit first"] + #[inline(always)] + pub fn reg_multi_slv_single_ccc_en(&self) -> REG_MULTI_SLV_SINGLE_CCC_EN_R { + REG_MULTI_SLV_SINGLE_CCC_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 0: rx low byte fist, 1: rx high byte first"] + #[inline(always)] + pub fn reg_rx_bit_order(&self) -> REG_RX_BIT_ORDER_R { + REG_RX_BIT_ORDER_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn reg_rx_byte_order(&self) -> REG_RX_BYTE_ORDER_R { + REG_RX_BYTE_ORDER_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - This bit is used to force scl_pullup_en"] + #[inline(always)] + pub fn reg_scl_pullup_force_en(&self) -> REG_SCL_PULLUP_FORCE_EN_R { + REG_SCL_PULLUP_FORCE_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - This bit is used to force scl_oe"] + #[inline(always)] + pub fn reg_scl_oe_force_en(&self) -> REG_SCL_OE_FORCE_EN_R { + REG_SCL_OE_FORCE_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn reg_sda_pp_rd_pullup_en(&self) -> REG_SDA_PP_RD_PULLUP_EN_R { + REG_SDA_PP_RD_PULLUP_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn reg_sda_rd_tbit_hlvl_pullup_en(&self) -> REG_SDA_RD_TBIT_HLVL_PULLUP_EN_R { + REG_SDA_RD_TBIT_HLVL_PULLUP_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn reg_sda_pp_wr_pullup_en(&self) -> REG_SDA_PP_WR_PULLUP_EN_R { + REG_SDA_PP_WR_PULLUP_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - 1: read current real-time updated value 0: read latch data byte cnt value"] + #[inline(always)] + pub fn reg_data_byte_cnt_unlatch(&self) -> REG_DATA_BYTE_CNT_UNLATCH_R { + REG_DATA_BYTE_CNT_UNLATCH_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - 1: dev characteristic and address table memory clk date force on . 0 : clock gating by rd/wr."] + #[inline(always)] + pub fn reg_mem_clk_force_on(&self) -> REG_MEM_CLK_FORCE_ON_R { + REG_MEM_CLK_FORCE_ON_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEVICE_CTRL") + .field( + "reg_ba_include", + &format_args!("{}", self.reg_ba_include().bit()), + ) + .field( + "reg_trans_start", + &format_args!("{}", self.reg_trans_start().bit()), + ) + .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit())) + .field( + "reg_ibi_rstart_trans_en", + &format_args!("{}", self.reg_ibi_rstart_trans_en().bit()), + ) + .field( + "reg_auto_dis_ibi_en", + &format_args!("{}", self.reg_auto_dis_ibi_en().bit()), + ) + .field( + "reg_dma_rx_en", + &format_args!("{}", self.reg_dma_rx_en().bit()), + ) + .field( + "reg_dma_tx_en", + &format_args!("{}", self.reg_dma_tx_en().bit()), + ) + .field( + "reg_multi_slv_single_ccc_en", + &format_args!("{}", self.reg_multi_slv_single_ccc_en().bit()), + ) + .field( + "reg_rx_bit_order", + &format_args!("{}", self.reg_rx_bit_order().bit()), + ) + .field( + "reg_rx_byte_order", + &format_args!("{}", self.reg_rx_byte_order().bit()), + ) + .field( + "reg_scl_pullup_force_en", + &format_args!("{}", self.reg_scl_pullup_force_en().bit()), + ) + .field( + "reg_scl_oe_force_en", + &format_args!("{}", self.reg_scl_oe_force_en().bit()), + ) + .field( + "reg_sda_pp_rd_pullup_en", + &format_args!("{}", self.reg_sda_pp_rd_pullup_en().bit()), + ) + .field( + "reg_sda_rd_tbit_hlvl_pullup_en", + &format_args!("{}", self.reg_sda_rd_tbit_hlvl_pullup_en().bit()), + ) + .field( + "reg_sda_pp_wr_pullup_en", + &format_args!("{}", self.reg_sda_pp_wr_pullup_en().bit()), + ) + .field( + "reg_data_byte_cnt_unlatch", + &format_args!("{}", self.reg_data_byte_cnt_unlatch().bit()), + ) + .field( + "reg_mem_clk_force_on", + &format_args!("{}", self.reg_mem_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 1 - This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed)"] + #[inline(always)] + #[must_use] + pub fn reg_ba_include(&mut self) -> REG_BA_INCLUDE_W { + REG_BA_INCLUDE_W::new(self, 1) + } + #[doc = "Bit 2 - Transfer Start"] + #[inline(always)] + #[must_use] + pub fn reg_trans_start(&mut self) -> REG_TRANS_START_W { + REG_TRANS_START_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_clk_en(&mut self) -> REG_CLK_EN_W { + REG_CLK_EN_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_ibi_rstart_trans_en(&mut self) -> REG_IBI_RSTART_TRANS_EN_W { + REG_IBI_RSTART_TRANS_EN_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_auto_dis_ibi_en(&mut self) -> REG_AUTO_DIS_IBI_EN_W { + REG_AUTO_DIS_IBI_EN_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dma_rx_en(&mut self) -> REG_DMA_RX_EN_W { + REG_DMA_RX_EN_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dma_tx_en(&mut self) -> REG_DMA_TX_EN_W { + REG_DMA_TX_EN_W::new(self, 7) + } + #[doc = "Bit 8 - 0: rx high bit first, 1: rx low bit first"] + #[inline(always)] + #[must_use] + pub fn reg_multi_slv_single_ccc_en( + &mut self, + ) -> REG_MULTI_SLV_SINGLE_CCC_EN_W { + REG_MULTI_SLV_SINGLE_CCC_EN_W::new(self, 8) + } + #[doc = "Bit 9 - 0: rx low byte fist, 1: rx high byte first"] + #[inline(always)] + #[must_use] + pub fn reg_rx_bit_order(&mut self) -> REG_RX_BIT_ORDER_W { + REG_RX_BIT_ORDER_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_rx_byte_order(&mut self) -> REG_RX_BYTE_ORDER_W { + REG_RX_BYTE_ORDER_W::new(self, 10) + } + #[doc = "Bit 11 - This bit is used to force scl_pullup_en"] + #[inline(always)] + #[must_use] + pub fn reg_scl_pullup_force_en(&mut self) -> REG_SCL_PULLUP_FORCE_EN_W { + REG_SCL_PULLUP_FORCE_EN_W::new(self, 11) + } + #[doc = "Bit 12 - This bit is used to force scl_oe"] + #[inline(always)] + #[must_use] + pub fn reg_scl_oe_force_en(&mut self) -> REG_SCL_OE_FORCE_EN_W { + REG_SCL_OE_FORCE_EN_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_sda_pp_rd_pullup_en(&mut self) -> REG_SDA_PP_RD_PULLUP_EN_W { + REG_SDA_PP_RD_PULLUP_EN_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_sda_rd_tbit_hlvl_pullup_en( + &mut self, + ) -> REG_SDA_RD_TBIT_HLVL_PULLUP_EN_W { + REG_SDA_RD_TBIT_HLVL_PULLUP_EN_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_sda_pp_wr_pullup_en(&mut self) -> REG_SDA_PP_WR_PULLUP_EN_W { + REG_SDA_PP_WR_PULLUP_EN_W::new(self, 15) + } + #[doc = "Bit 16 - 1: read current real-time updated value 0: read latch data byte cnt value"] + #[inline(always)] + #[must_use] + pub fn reg_data_byte_cnt_unlatch(&mut self) -> REG_DATA_BYTE_CNT_UNLATCH_W { + REG_DATA_BYTE_CNT_UNLATCH_W::new(self, 16) + } + #[doc = "Bit 17 - 1: dev characteristic and address table memory clk date force on . 0 : clock gating by rd/wr."] + #[inline(always)] + #[must_use] + pub fn reg_mem_clk_force_on(&mut self) -> REG_MEM_CLK_FORCE_ON_W { + REG_MEM_CLK_FORCE_ON_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`device_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`device_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEVICE_CTRL_SPEC; +impl crate::RegisterSpec for DEVICE_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`device_ctrl::R`](R) reader structure"] +impl crate::Readable for DEVICE_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`device_ctrl::W`](W) writer structure"] +impl crate::Writable for DEVICE_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEVICE_CTRL to value 0x1020"] +impl crate::Resettable for DEVICE_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x1020; +} diff --git a/esp32p4/src/i3c_mst/device_table.rs b/esp32p4/src/i3c_mst/device_table.rs new file mode 100644 index 0000000000..30384c184a --- /dev/null +++ b/esp32p4/src/i3c_mst/device_table.rs @@ -0,0 +1,107 @@ +#[doc = "Register `DEVICE_TABLE` reader"] +pub type R = crate::R; +#[doc = "Register `DEVICE_TABLE` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DCT_DAA_INIT_INDEX` reader - Reserved"] +pub type REG_DCT_DAA_INIT_INDEX_R = crate::FieldReader; +#[doc = "Field `REG_DCT_DAA_INIT_INDEX` writer - Reserved"] +pub type REG_DCT_DAA_INIT_INDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `REG_DAT_DAA_INIT_INDEX` reader - NA"] +pub type REG_DAT_DAA_INIT_INDEX_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DAA_INIT_INDEX` writer - NA"] +pub type REG_DAT_DAA_INIT_INDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRESENT_DCT_INDEX` reader - NA"] +pub type PRESENT_DCT_INDEX_R = crate::FieldReader; +#[doc = "Field `PRESENT_DAT_INDEX` reader - NA"] +pub type PRESENT_DAT_INDEX_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Reserved"] + #[inline(always)] + pub fn reg_dct_daa_init_index(&self) -> REG_DCT_DAA_INIT_INDEX_R { + REG_DCT_DAA_INIT_INDEX_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - NA"] + #[inline(always)] + pub fn reg_dat_daa_init_index(&self) -> REG_DAT_DAA_INIT_INDEX_R { + REG_DAT_DAA_INIT_INDEX_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - NA"] + #[inline(always)] + pub fn present_dct_index(&self) -> PRESENT_DCT_INDEX_R { + PRESENT_DCT_INDEX_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - NA"] + #[inline(always)] + pub fn present_dat_index(&self) -> PRESENT_DAT_INDEX_R { + PRESENT_DAT_INDEX_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEVICE_TABLE") + .field( + "reg_dct_daa_init_index", + &format_args!("{}", self.reg_dct_daa_init_index().bits()), + ) + .field( + "reg_dat_daa_init_index", + &format_args!("{}", self.reg_dat_daa_init_index().bits()), + ) + .field( + "present_dct_index", + &format_args!("{}", self.present_dct_index().bits()), + ) + .field( + "present_dat_index", + &format_args!("{}", self.present_dat_index().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_dct_daa_init_index(&mut self) -> REG_DCT_DAA_INIT_INDEX_W { + REG_DCT_DAA_INIT_INDEX_W::new(self, 0) + } + #[doc = "Bits 4:7 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_daa_init_index(&mut self) -> REG_DAT_DAA_INIT_INDEX_W { + REG_DAT_DAA_INIT_INDEX_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Pointer for Device Address Table\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`device_table::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`device_table::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEVICE_TABLE_SPEC; +impl crate::RegisterSpec for DEVICE_TABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`device_table::R`](R) reader structure"] +impl crate::Readable for DEVICE_TABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`device_table::W`](W) writer structure"] +impl crate::Writable for DEVICE_TABLE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEVICE_TABLE to value 0"] +impl crate::Resettable for DEVICE_TABLE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/fpga_debug_probe.rs b/esp32p4/src/i3c_mst/fpga_debug_probe.rs new file mode 100644 index 0000000000..49f99f62e1 --- /dev/null +++ b/esp32p4/src/i3c_mst/fpga_debug_probe.rs @@ -0,0 +1,68 @@ +#[doc = "Register `FPGA_DEBUG_PROBE` reader"] +pub type R = crate::R; +#[doc = "Register `FPGA_DEBUG_PROBE` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I3C_MST_FPGA_DEBUG_PROBE` reader - For Debug Probe Test on FPGA"] +pub type REG_I3C_MST_FPGA_DEBUG_PROBE_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_FPGA_DEBUG_PROBE` writer - For Debug Probe Test on FPGA"] +pub type REG_I3C_MST_FPGA_DEBUG_PROBE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For Debug Probe Test on FPGA"] + #[inline(always)] + pub fn reg_i3c_mst_fpga_debug_probe(&self) -> REG_I3C_MST_FPGA_DEBUG_PROBE_R { + REG_I3C_MST_FPGA_DEBUG_PROBE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FPGA_DEBUG_PROBE") + .field( + "reg_i3c_mst_fpga_debug_probe", + &format_args!("{}", self.reg_i3c_mst_fpga_debug_probe().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - For Debug Probe Test on FPGA"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_fpga_debug_probe( + &mut self, + ) -> REG_I3C_MST_FPGA_DEBUG_PROBE_W { + REG_I3C_MST_FPGA_DEBUG_PROBE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpga_debug_probe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpga_debug_probe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FPGA_DEBUG_PROBE_SPEC; +impl crate::RegisterSpec for FPGA_DEBUG_PROBE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fpga_debug_probe::R`](R) reader structure"] +impl crate::Readable for FPGA_DEBUG_PROBE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fpga_debug_probe::W`](W) writer structure"] +impl crate::Writable for FPGA_DEBUG_PROBE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FPGA_DEBUG_PROBE to value 0x01"] +impl crate::Resettable for FPGA_DEBUG_PROBE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/i3c_mst/ibi_notify_ctrl.rs b/esp32p4/src/i3c_mst/ibi_notify_ctrl.rs new file mode 100644 index 0000000000..6313d0f04e --- /dev/null +++ b/esp32p4/src/i3c_mst/ibi_notify_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IBI_NOTIFY_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `IBI_NOTIFY_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `REG_NOTIFY_SIR_REJECTED` reader - Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl."] +pub type REG_NOTIFY_SIR_REJECTED_R = crate::BitReader; +#[doc = "Field `REG_NOTIFY_SIR_REJECTED` writer - Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl."] +pub type REG_NOTIFY_SIR_REJECTED_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl."] + #[inline(always)] + pub fn reg_notify_sir_rejected(&self) -> REG_NOTIFY_SIR_REJECTED_R { + REG_NOTIFY_SIR_REJECTED_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IBI_NOTIFY_CTRL") + .field( + "reg_notify_sir_rejected", + &format_args!("{}", self.reg_notify_sir_rejected().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 2 - Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl."] + #[inline(always)] + #[must_use] + pub fn reg_notify_sir_rejected(&mut self) -> REG_NOTIFY_SIR_REJECTED_W { + REG_NOTIFY_SIR_REJECTED_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_notify_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibi_notify_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IBI_NOTIFY_CTRL_SPEC; +impl crate::RegisterSpec for IBI_NOTIFY_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ibi_notify_ctrl::R`](R) reader structure"] +impl crate::Readable for IBI_NOTIFY_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ibi_notify_ctrl::W`](W) writer structure"] +impl crate::Writable for IBI_NOTIFY_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IBI_NOTIFY_CTRL to value 0"] +impl crate::Resettable for IBI_NOTIFY_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/ibi_sir_req_payload.rs b/esp32p4/src/i3c_mst/ibi_sir_req_payload.rs new file mode 100644 index 0000000000..16d1948f22 --- /dev/null +++ b/esp32p4/src/i3c_mst/ibi_sir_req_payload.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IBI_SIR_REQ_PAYLOAD` reader"] +pub type R = crate::R; +#[doc = "Register `IBI_SIR_REQ_PAYLOAD` writer"] +pub type W = crate::W; +#[doc = "Field `REG_SIR_REQ_PAYLOAD` reader - NA"] +pub type REG_SIR_REQ_PAYLOAD_R = crate::FieldReader; +#[doc = "Field `REG_SIR_REQ_PAYLOAD` writer - NA"] +pub type REG_SIR_REQ_PAYLOAD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn reg_sir_req_payload(&self) -> REG_SIR_REQ_PAYLOAD_R { + REG_SIR_REQ_PAYLOAD_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IBI_SIR_REQ_PAYLOAD") + .field( + "reg_sir_req_payload", + &format_args!("{}", self.reg_sir_req_payload().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_sir_req_payload(&mut self) -> REG_SIR_REQ_PAYLOAD_W { + REG_SIR_REQ_PAYLOAD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_sir_req_payload::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibi_sir_req_payload::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IBI_SIR_REQ_PAYLOAD_SPEC; +impl crate::RegisterSpec for IBI_SIR_REQ_PAYLOAD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ibi_sir_req_payload::R`](R) reader structure"] +impl crate::Readable for IBI_SIR_REQ_PAYLOAD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ibi_sir_req_payload::W`](W) writer structure"] +impl crate::Writable for IBI_SIR_REQ_PAYLOAD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IBI_SIR_REQ_PAYLOAD to value 0"] +impl crate::Resettable for IBI_SIR_REQ_PAYLOAD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/ibi_sir_req_reject.rs b/esp32p4/src/i3c_mst/ibi_sir_req_reject.rs new file mode 100644 index 0000000000..abade85dfc --- /dev/null +++ b/esp32p4/src/i3c_mst/ibi_sir_req_reject.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IBI_SIR_REQ_REJECT` reader"] +pub type R = crate::R; +#[doc = "Register `IBI_SIR_REQ_REJECT` writer"] +pub type W = crate::W; +#[doc = "Field `REG_SIR_REQ_REJECT` reader - The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC"] +pub type REG_SIR_REQ_REJECT_R = crate::FieldReader; +#[doc = "Field `REG_SIR_REQ_REJECT` writer - The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC"] +pub type REG_SIR_REQ_REJECT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC"] + #[inline(always)] + pub fn reg_sir_req_reject(&self) -> REG_SIR_REQ_REJECT_R { + REG_SIR_REQ_REJECT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IBI_SIR_REQ_REJECT") + .field( + "reg_sir_req_reject", + &format_args!("{}", self.reg_sir_req_reject().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC"] + #[inline(always)] + #[must_use] + pub fn reg_sir_req_reject(&mut self) -> REG_SIR_REQ_REJECT_W { + REG_SIR_REQ_REJECT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_sir_req_reject::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibi_sir_req_reject::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IBI_SIR_REQ_REJECT_SPEC; +impl crate::RegisterSpec for IBI_SIR_REQ_REJECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ibi_sir_req_reject::R`](R) reader structure"] +impl crate::Readable for IBI_SIR_REQ_REJECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ibi_sir_req_reject::W`](W) writer structure"] +impl crate::Writable for IBI_SIR_REQ_REJECT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IBI_SIR_REQ_REJECT to value 0"] +impl crate::Resettable for IBI_SIR_REQ_REJECT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/int_clr.rs b/esp32p4/src/i3c_mst/int_clr.rs new file mode 100644 index 0000000000..9d7fc513dd --- /dev/null +++ b/esp32p4/src/i3c_mst/int_clr.rs @@ -0,0 +1,162 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `TX_DATA_BUF_THLD_INT_CLR` writer - NA"] +pub type TX_DATA_BUF_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DATA_BUF_THLD_INT_CLR` writer - NA"] +pub type RX_DATA_BUF_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_STATUS_THLD_INT_CLR` writer - NA"] +pub type IBI_STATUS_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_CLR` writer - NA"] +pub type CMD_BUF_EMPTY_THLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESP_READY_INT_CLR` writer - NA"] +pub type RESP_READY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NXT_CMD_REQ_ERR_INT_CLR` writer - NA"] +pub type NXT_CMD_REQ_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSFER_ERR_INT_CLR` writer - NA"] +pub type TRANSFER_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSFER_COMPLETE_INT_CLR` writer - NA"] +pub type TRANSFER_COMPLETE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMMAND_DONE_INT_CLR` writer - NA"] +pub type COMMAND_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DETECT_START_INT_CLR` writer - NA"] +pub type DETECT_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESP_BUF_OVF_INT_CLR` writer - NA"] +pub type RESP_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_DATA_BUF_OVF_INT_CLR` writer - NA"] +pub type IBI_DATA_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_STATUS_BUF_OVF_INT_CLR` writer - NA"] +pub type IBI_STATUS_BUF_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_HANDLE_DONE_INT_CLR` writer - NA"] +pub type IBI_HANDLE_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_DETECT_INT_CLR` writer - NA"] +pub type IBI_DETECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMD_CCC_MISMATCH_INT_CLR` writer - NA"] +pub type CMD_CCC_MISMATCH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn tx_data_buf_thld_int_clr(&mut self) -> TX_DATA_BUF_THLD_INT_CLR_W { + TX_DATA_BUF_THLD_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn rx_data_buf_thld_int_clr(&mut self) -> RX_DATA_BUF_THLD_INT_CLR_W { + RX_DATA_BUF_THLD_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_status_thld_int_clr(&mut self) -> IBI_STATUS_THLD_INT_CLR_W { + IBI_STATUS_THLD_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn cmd_buf_empty_thld_int_clr(&mut self) -> CMD_BUF_EMPTY_THLD_INT_CLR_W { + CMD_BUF_EMPTY_THLD_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn resp_ready_int_clr(&mut self) -> RESP_READY_INT_CLR_W { + RESP_READY_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn nxt_cmd_req_err_int_clr(&mut self) -> NXT_CMD_REQ_ERR_INT_CLR_W { + NXT_CMD_REQ_ERR_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn transfer_err_int_clr(&mut self) -> TRANSFER_ERR_INT_CLR_W { + TRANSFER_ERR_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn transfer_complete_int_clr(&mut self) -> TRANSFER_COMPLETE_INT_CLR_W { + TRANSFER_COMPLETE_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn command_done_int_clr(&mut self) -> COMMAND_DONE_INT_CLR_W { + COMMAND_DONE_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn detect_start_int_clr(&mut self) -> DETECT_START_INT_CLR_W { + DETECT_START_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn resp_buf_ovf_int_clr(&mut self) -> RESP_BUF_OVF_INT_CLR_W { + RESP_BUF_OVF_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_data_buf_ovf_int_clr(&mut self) -> IBI_DATA_BUF_OVF_INT_CLR_W { + IBI_DATA_BUF_OVF_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_status_buf_ovf_int_clr(&mut self) -> IBI_STATUS_BUF_OVF_INT_CLR_W { + IBI_STATUS_BUF_OVF_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_handle_done_int_clr(&mut self) -> IBI_HANDLE_DONE_INT_CLR_W { + IBI_HANDLE_DONE_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_detect_int_clr(&mut self) -> IBI_DETECT_INT_CLR_W { + IBI_DETECT_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn cmd_ccc_mismatch_int_clr(&mut self) -> CMD_CCC_MISMATCH_INT_CLR_W { + CMD_CCC_MISMATCH_INT_CLR_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/int_raw.rs b/esp32p4/src/i3c_mst/int_raw.rs new file mode 100644 index 0000000000..8ad80bdcba --- /dev/null +++ b/esp32p4/src/i3c_mst/int_raw.rs @@ -0,0 +1,351 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `TX_DATA_BUF_THLD_INT_RAW` reader - NA"] +pub type TX_DATA_BUF_THLD_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_DATA_BUF_THLD_INT_RAW` writer - NA"] +pub type TX_DATA_BUF_THLD_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DATA_BUF_THLD_INT_RAW` reader - NA"] +pub type RX_DATA_BUF_THLD_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_DATA_BUF_THLD_INT_RAW` writer - NA"] +pub type RX_DATA_BUF_THLD_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_STATUS_THLD_INT_RAW` reader - NA"] +pub type IBI_STATUS_THLD_INT_RAW_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_THLD_INT_RAW` writer - NA"] +pub type IBI_STATUS_THLD_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_RAW` reader - NA"] +pub type CMD_BUF_EMPTY_THLD_INT_RAW_R = crate::BitReader; +#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_RAW` writer - NA"] +pub type CMD_BUF_EMPTY_THLD_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESP_READY_INT_RAW` reader - NA"] +pub type RESP_READY_INT_RAW_R = crate::BitReader; +#[doc = "Field `RESP_READY_INT_RAW` writer - NA"] +pub type RESP_READY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NXT_CMD_REQ_ERR_INT_RAW` reader - NA"] +pub type NXT_CMD_REQ_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `NXT_CMD_REQ_ERR_INT_RAW` writer - NA"] +pub type NXT_CMD_REQ_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSFER_ERR_INT_RAW` reader - NA"] +pub type TRANSFER_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `TRANSFER_ERR_INT_RAW` writer - NA"] +pub type TRANSFER_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSFER_COMPLETE_INT_RAW` reader - NA"] +pub type TRANSFER_COMPLETE_INT_RAW_R = crate::BitReader; +#[doc = "Field `TRANSFER_COMPLETE_INT_RAW` writer - NA"] +pub type TRANSFER_COMPLETE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMMAND_DONE_INT_RAW` reader - NA"] +pub type COMMAND_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `COMMAND_DONE_INT_RAW` writer - NA"] +pub type COMMAND_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DETECT_START_INT_RAW` reader - NA"] +pub type DETECT_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `DETECT_START_INT_RAW` writer - NA"] +pub type DETECT_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESP_BUF_OVF_INT_RAW` reader - NA"] +pub type RESP_BUF_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `RESP_BUF_OVF_INT_RAW` writer - NA"] +pub type RESP_BUF_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_DATA_BUF_OVF_INT_RAW` reader - NA"] +pub type IBI_DATA_BUF_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `IBI_DATA_BUF_OVF_INT_RAW` writer - NA"] +pub type IBI_DATA_BUF_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_STATUS_BUF_OVF_INT_RAW` reader - NA"] +pub type IBI_STATUS_BUF_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_BUF_OVF_INT_RAW` writer - NA"] +pub type IBI_STATUS_BUF_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_HANDLE_DONE_INT_RAW` reader - NA"] +pub type IBI_HANDLE_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `IBI_HANDLE_DONE_INT_RAW` writer - NA"] +pub type IBI_HANDLE_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_DETECT_INT_RAW` reader - NA"] +pub type IBI_DETECT_INT_RAW_R = crate::BitReader; +#[doc = "Field `IBI_DETECT_INT_RAW` writer - NA"] +pub type IBI_DETECT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMD_CCC_MISMATCH_INT_RAW` reader - NA"] +pub type CMD_CCC_MISMATCH_INT_RAW_R = crate::BitReader; +#[doc = "Field `CMD_CCC_MISMATCH_INT_RAW` writer - NA"] +pub type CMD_CCC_MISMATCH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn tx_data_buf_thld_int_raw(&self) -> TX_DATA_BUF_THLD_INT_RAW_R { + TX_DATA_BUF_THLD_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn rx_data_buf_thld_int_raw(&self) -> RX_DATA_BUF_THLD_INT_RAW_R { + RX_DATA_BUF_THLD_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ibi_status_thld_int_raw(&self) -> IBI_STATUS_THLD_INT_RAW_R { + IBI_STATUS_THLD_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn cmd_buf_empty_thld_int_raw(&self) -> CMD_BUF_EMPTY_THLD_INT_RAW_R { + CMD_BUF_EMPTY_THLD_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn resp_ready_int_raw(&self) -> RESP_READY_INT_RAW_R { + RESP_READY_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn nxt_cmd_req_err_int_raw(&self) -> NXT_CMD_REQ_ERR_INT_RAW_R { + NXT_CMD_REQ_ERR_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn transfer_err_int_raw(&self) -> TRANSFER_ERR_INT_RAW_R { + TRANSFER_ERR_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn transfer_complete_int_raw(&self) -> TRANSFER_COMPLETE_INT_RAW_R { + TRANSFER_COMPLETE_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn command_done_int_raw(&self) -> COMMAND_DONE_INT_RAW_R { + COMMAND_DONE_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn detect_start_int_raw(&self) -> DETECT_START_INT_RAW_R { + DETECT_START_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn resp_buf_ovf_int_raw(&self) -> RESP_BUF_OVF_INT_RAW_R { + RESP_BUF_OVF_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ibi_data_buf_ovf_int_raw(&self) -> IBI_DATA_BUF_OVF_INT_RAW_R { + IBI_DATA_BUF_OVF_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ibi_status_buf_ovf_int_raw(&self) -> IBI_STATUS_BUF_OVF_INT_RAW_R { + IBI_STATUS_BUF_OVF_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ibi_handle_done_int_raw(&self) -> IBI_HANDLE_DONE_INT_RAW_R { + IBI_HANDLE_DONE_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ibi_detect_int_raw(&self) -> IBI_DETECT_INT_RAW_R { + IBI_DETECT_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn cmd_ccc_mismatch_int_raw(&self) -> CMD_CCC_MISMATCH_INT_RAW_R { + CMD_CCC_MISMATCH_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "tx_data_buf_thld_int_raw", + &format_args!("{}", self.tx_data_buf_thld_int_raw().bit()), + ) + .field( + "rx_data_buf_thld_int_raw", + &format_args!("{}", self.rx_data_buf_thld_int_raw().bit()), + ) + .field( + "ibi_status_thld_int_raw", + &format_args!("{}", self.ibi_status_thld_int_raw().bit()), + ) + .field( + "cmd_buf_empty_thld_int_raw", + &format_args!("{}", self.cmd_buf_empty_thld_int_raw().bit()), + ) + .field( + "resp_ready_int_raw", + &format_args!("{}", self.resp_ready_int_raw().bit()), + ) + .field( + "nxt_cmd_req_err_int_raw", + &format_args!("{}", self.nxt_cmd_req_err_int_raw().bit()), + ) + .field( + "transfer_err_int_raw", + &format_args!("{}", self.transfer_err_int_raw().bit()), + ) + .field( + "transfer_complete_int_raw", + &format_args!("{}", self.transfer_complete_int_raw().bit()), + ) + .field( + "command_done_int_raw", + &format_args!("{}", self.command_done_int_raw().bit()), + ) + .field( + "detect_start_int_raw", + &format_args!("{}", self.detect_start_int_raw().bit()), + ) + .field( + "resp_buf_ovf_int_raw", + &format_args!("{}", self.resp_buf_ovf_int_raw().bit()), + ) + .field( + "ibi_data_buf_ovf_int_raw", + &format_args!("{}", self.ibi_data_buf_ovf_int_raw().bit()), + ) + .field( + "ibi_status_buf_ovf_int_raw", + &format_args!("{}", self.ibi_status_buf_ovf_int_raw().bit()), + ) + .field( + "ibi_handle_done_int_raw", + &format_args!("{}", self.ibi_handle_done_int_raw().bit()), + ) + .field( + "ibi_detect_int_raw", + &format_args!("{}", self.ibi_detect_int_raw().bit()), + ) + .field( + "cmd_ccc_mismatch_int_raw", + &format_args!("{}", self.cmd_ccc_mismatch_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn tx_data_buf_thld_int_raw(&mut self) -> TX_DATA_BUF_THLD_INT_RAW_W { + TX_DATA_BUF_THLD_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn rx_data_buf_thld_int_raw(&mut self) -> RX_DATA_BUF_THLD_INT_RAW_W { + RX_DATA_BUF_THLD_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_status_thld_int_raw(&mut self) -> IBI_STATUS_THLD_INT_RAW_W { + IBI_STATUS_THLD_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn cmd_buf_empty_thld_int_raw(&mut self) -> CMD_BUF_EMPTY_THLD_INT_RAW_W { + CMD_BUF_EMPTY_THLD_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn resp_ready_int_raw(&mut self) -> RESP_READY_INT_RAW_W { + RESP_READY_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn nxt_cmd_req_err_int_raw(&mut self) -> NXT_CMD_REQ_ERR_INT_RAW_W { + NXT_CMD_REQ_ERR_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn transfer_err_int_raw(&mut self) -> TRANSFER_ERR_INT_RAW_W { + TRANSFER_ERR_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn transfer_complete_int_raw(&mut self) -> TRANSFER_COMPLETE_INT_RAW_W { + TRANSFER_COMPLETE_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn command_done_int_raw(&mut self) -> COMMAND_DONE_INT_RAW_W { + COMMAND_DONE_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn detect_start_int_raw(&mut self) -> DETECT_START_INT_RAW_W { + DETECT_START_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn resp_buf_ovf_int_raw(&mut self) -> RESP_BUF_OVF_INT_RAW_W { + RESP_BUF_OVF_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_data_buf_ovf_int_raw(&mut self) -> IBI_DATA_BUF_OVF_INT_RAW_W { + IBI_DATA_BUF_OVF_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_status_buf_ovf_int_raw(&mut self) -> IBI_STATUS_BUF_OVF_INT_RAW_W { + IBI_STATUS_BUF_OVF_INT_RAW_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_handle_done_int_raw(&mut self) -> IBI_HANDLE_DONE_INT_RAW_W { + IBI_HANDLE_DONE_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_detect_int_raw(&mut self) -> IBI_DETECT_INT_RAW_W { + IBI_DETECT_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn cmd_ccc_mismatch_int_raw(&mut self) -> CMD_CCC_MISMATCH_INT_RAW_W { + CMD_CCC_MISMATCH_INT_RAW_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0x08"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/i3c_mst/int_st.rs b/esp32p4/src/i3c_mst/int_st.rs new file mode 100644 index 0000000000..601bbddc75 --- /dev/null +++ b/esp32p4/src/i3c_mst/int_st.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `TX_DATA_BUF_THLD_INT_ST` reader - This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value."] +pub type TX_DATA_BUF_THLD_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_DATA_BUF_THLD_INT_ST` reader - This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value."] +pub type RX_DATA_BUF_THLD_INT_ST_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_THLD_INT_ST` reader - Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value."] +pub type IBI_STATUS_THLD_INT_ST_R = crate::BitReader; +#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_ST` reader - This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value."] +pub type CMD_BUF_EMPTY_THLD_INT_ST_R = crate::BitReader; +#[doc = "Field `RESP_READY_INT_ST` reader - This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value."] +pub type RESP_READY_INT_ST_R = crate::BitReader; +#[doc = "Field `NXT_CMD_REQ_ERR_INT_ST` reader - This interrupt is generated if toc is 0(master will restart next command), but command buf is empty."] +pub type NXT_CMD_REQ_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `TRANSFER_ERR_INT_ST` reader - This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1."] +pub type TRANSFER_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `TRANSFER_COMPLETE_INT_ST` reader - NA"] +pub type TRANSFER_COMPLETE_INT_ST_R = crate::BitReader; +#[doc = "Field `COMMAND_DONE_INT_ST` reader - NA"] +pub type COMMAND_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `DETECT_START_INT_ST` reader - NA"] +pub type DETECT_START_INT_ST_R = crate::BitReader; +#[doc = "Field `RESP_BUF_OVF_INT_ST` reader - NA"] +pub type RESP_BUF_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `IBI_DATA_BUF_OVF_INT_ST` reader - NA"] +pub type IBI_DATA_BUF_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_BUF_OVF_INT_ST` reader - NA"] +pub type IBI_STATUS_BUF_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `IBI_HANDLE_DONE_INT_ST` reader - NA"] +pub type IBI_HANDLE_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `IBI_DETECT_INT_ST` reader - NA"] +pub type IBI_DETECT_INT_ST_R = crate::BitReader; +#[doc = "Field `CMD_CCC_MISMATCH_INT_ST` reader - NA"] +pub type CMD_CCC_MISMATCH_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value."] + #[inline(always)] + pub fn tx_data_buf_thld_int_st(&self) -> TX_DATA_BUF_THLD_INT_ST_R { + TX_DATA_BUF_THLD_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value."] + #[inline(always)] + pub fn rx_data_buf_thld_int_st(&self) -> RX_DATA_BUF_THLD_INT_ST_R { + RX_DATA_BUF_THLD_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value."] + #[inline(always)] + pub fn ibi_status_thld_int_st(&self) -> IBI_STATUS_THLD_INT_ST_R { + IBI_STATUS_THLD_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value."] + #[inline(always)] + pub fn cmd_buf_empty_thld_int_st(&self) -> CMD_BUF_EMPTY_THLD_INT_ST_R { + CMD_BUF_EMPTY_THLD_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value."] + #[inline(always)] + pub fn resp_ready_int_st(&self) -> RESP_READY_INT_ST_R { + RESP_READY_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This interrupt is generated if toc is 0(master will restart next command), but command buf is empty."] + #[inline(always)] + pub fn nxt_cmd_req_err_int_st(&self) -> NXT_CMD_REQ_ERR_INT_ST_R { + NXT_CMD_REQ_ERR_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1."] + #[inline(always)] + pub fn transfer_err_int_st(&self) -> TRANSFER_ERR_INT_ST_R { + TRANSFER_ERR_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn transfer_complete_int_st(&self) -> TRANSFER_COMPLETE_INT_ST_R { + TRANSFER_COMPLETE_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn command_done_int_st(&self) -> COMMAND_DONE_INT_ST_R { + COMMAND_DONE_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn detect_start_int_st(&self) -> DETECT_START_INT_ST_R { + DETECT_START_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn resp_buf_ovf_int_st(&self) -> RESP_BUF_OVF_INT_ST_R { + RESP_BUF_OVF_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ibi_data_buf_ovf_int_st(&self) -> IBI_DATA_BUF_OVF_INT_ST_R { + IBI_DATA_BUF_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ibi_status_buf_ovf_int_st(&self) -> IBI_STATUS_BUF_OVF_INT_ST_R { + IBI_STATUS_BUF_OVF_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ibi_handle_done_int_st(&self) -> IBI_HANDLE_DONE_INT_ST_R { + IBI_HANDLE_DONE_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ibi_detect_int_st(&self) -> IBI_DETECT_INT_ST_R { + IBI_DETECT_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn cmd_ccc_mismatch_int_st(&self) -> CMD_CCC_MISMATCH_INT_ST_R { + CMD_CCC_MISMATCH_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "tx_data_buf_thld_int_st", + &format_args!("{}", self.tx_data_buf_thld_int_st().bit()), + ) + .field( + "rx_data_buf_thld_int_st", + &format_args!("{}", self.rx_data_buf_thld_int_st().bit()), + ) + .field( + "ibi_status_thld_int_st", + &format_args!("{}", self.ibi_status_thld_int_st().bit()), + ) + .field( + "cmd_buf_empty_thld_int_st", + &format_args!("{}", self.cmd_buf_empty_thld_int_st().bit()), + ) + .field( + "resp_ready_int_st", + &format_args!("{}", self.resp_ready_int_st().bit()), + ) + .field( + "nxt_cmd_req_err_int_st", + &format_args!("{}", self.nxt_cmd_req_err_int_st().bit()), + ) + .field( + "transfer_err_int_st", + &format_args!("{}", self.transfer_err_int_st().bit()), + ) + .field( + "transfer_complete_int_st", + &format_args!("{}", self.transfer_complete_int_st().bit()), + ) + .field( + "command_done_int_st", + &format_args!("{}", self.command_done_int_st().bit()), + ) + .field( + "detect_start_int_st", + &format_args!("{}", self.detect_start_int_st().bit()), + ) + .field( + "resp_buf_ovf_int_st", + &format_args!("{}", self.resp_buf_ovf_int_st().bit()), + ) + .field( + "ibi_data_buf_ovf_int_st", + &format_args!("{}", self.ibi_data_buf_ovf_int_st().bit()), + ) + .field( + "ibi_status_buf_ovf_int_st", + &format_args!("{}", self.ibi_status_buf_ovf_int_st().bit()), + ) + .field( + "ibi_handle_done_int_st", + &format_args!("{}", self.ibi_handle_done_int_st().bit()), + ) + .field( + "ibi_detect_int_st", + &format_args!("{}", self.ibi_detect_int_st().bit()), + ) + .field( + "cmd_ccc_mismatch_int_st", + &format_args!("{}", self.cmd_ccc_mismatch_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/int_st_ena.rs b/esp32p4/src/i3c_mst/int_st_ena.rs new file mode 100644 index 0000000000..c653859b43 --- /dev/null +++ b/esp32p4/src/i3c_mst/int_st_ena.rs @@ -0,0 +1,351 @@ +#[doc = "Register `INT_ST_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ST_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `TX_DATA_BUF_THLD_INT_ENA` reader - Transmit Buffer threshold status enable."] +pub type TX_DATA_BUF_THLD_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_DATA_BUF_THLD_INT_ENA` writer - Transmit Buffer threshold status enable."] +pub type TX_DATA_BUF_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DATA_BUF_THLD_INT_ENA` reader - Receive Buffer threshold status enable."] +pub type RX_DATA_BUF_THLD_INT_ENA_R = crate::BitReader; +#[doc = "Field `RX_DATA_BUF_THLD_INT_ENA` writer - Receive Buffer threshold status enable."] +pub type RX_DATA_BUF_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_STATUS_THLD_INT_ENA` reader - Only used in master mode. IBI Buffer threshold status enable."] +pub type IBI_STATUS_THLD_INT_ENA_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_THLD_INT_ENA` writer - Only used in master mode. IBI Buffer threshold status enable."] +pub type IBI_STATUS_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_ENA` reader - Command buffer ready status enable."] +pub type CMD_BUF_EMPTY_THLD_INT_ENA_R = crate::BitReader; +#[doc = "Field `CMD_BUF_EMPTY_THLD_INT_ENA` writer - Command buffer ready status enable."] +pub type CMD_BUF_EMPTY_THLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESP_READY_INT_ENA` reader - Response buffer ready status enable."] +pub type RESP_READY_INT_ENA_R = crate::BitReader; +#[doc = "Field `RESP_READY_INT_ENA` writer - Response buffer ready status enable."] +pub type RESP_READY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NXT_CMD_REQ_ERR_INT_ENA` reader - next command request error status enable"] +pub type NXT_CMD_REQ_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `NXT_CMD_REQ_ERR_INT_ENA` writer - next command request error status enable"] +pub type NXT_CMD_REQ_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSFER_ERR_INT_ENA` reader - Transfer error status enable"] +pub type TRANSFER_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `TRANSFER_ERR_INT_ENA` writer - Transfer error status enable"] +pub type TRANSFER_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSFER_COMPLETE_INT_ENA` reader - NA"] +pub type TRANSFER_COMPLETE_INT_ENA_R = crate::BitReader; +#[doc = "Field `TRANSFER_COMPLETE_INT_ENA` writer - NA"] +pub type TRANSFER_COMPLETE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMMAND_DONE_INT_ENA` reader - NA"] +pub type COMMAND_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `COMMAND_DONE_INT_ENA` writer - NA"] +pub type COMMAND_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DETECT_START_INT_ENA` reader - NA"] +pub type DETECT_START_INT_ENA_R = crate::BitReader; +#[doc = "Field `DETECT_START_INT_ENA` writer - NA"] +pub type DETECT_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESP_BUF_OVF_INT_ENA` reader - NA"] +pub type RESP_BUF_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `RESP_BUF_OVF_INT_ENA` writer - NA"] +pub type RESP_BUF_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_DATA_BUF_OVF_INT_ENA` reader - NA"] +pub type IBI_DATA_BUF_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `IBI_DATA_BUF_OVF_INT_ENA` writer - NA"] +pub type IBI_DATA_BUF_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_STATUS_BUF_OVF_INT_ENA` reader - NA"] +pub type IBI_STATUS_BUF_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `IBI_STATUS_BUF_OVF_INT_ENA` writer - NA"] +pub type IBI_STATUS_BUF_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_HANDLE_DONE_INT_ENA` reader - NA"] +pub type IBI_HANDLE_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `IBI_HANDLE_DONE_INT_ENA` writer - NA"] +pub type IBI_HANDLE_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBI_DETECT_INT_ENA` reader - NA"] +pub type IBI_DETECT_INT_ENA_R = crate::BitReader; +#[doc = "Field `IBI_DETECT_INT_ENA` writer - NA"] +pub type IBI_DETECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMD_CCC_MISMATCH_INT_ENA` reader - NA"] +pub type CMD_CCC_MISMATCH_INT_ENA_R = crate::BitReader; +#[doc = "Field `CMD_CCC_MISMATCH_INT_ENA` writer - NA"] +pub type CMD_CCC_MISMATCH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Transmit Buffer threshold status enable."] + #[inline(always)] + pub fn tx_data_buf_thld_int_ena(&self) -> TX_DATA_BUF_THLD_INT_ENA_R { + TX_DATA_BUF_THLD_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Buffer threshold status enable."] + #[inline(always)] + pub fn rx_data_buf_thld_int_ena(&self) -> RX_DATA_BUF_THLD_INT_ENA_R { + RX_DATA_BUF_THLD_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Only used in master mode. IBI Buffer threshold status enable."] + #[inline(always)] + pub fn ibi_status_thld_int_ena(&self) -> IBI_STATUS_THLD_INT_ENA_R { + IBI_STATUS_THLD_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Command buffer ready status enable."] + #[inline(always)] + pub fn cmd_buf_empty_thld_int_ena(&self) -> CMD_BUF_EMPTY_THLD_INT_ENA_R { + CMD_BUF_EMPTY_THLD_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Response buffer ready status enable."] + #[inline(always)] + pub fn resp_ready_int_ena(&self) -> RESP_READY_INT_ENA_R { + RESP_READY_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - next command request error status enable"] + #[inline(always)] + pub fn nxt_cmd_req_err_int_ena(&self) -> NXT_CMD_REQ_ERR_INT_ENA_R { + NXT_CMD_REQ_ERR_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Transfer error status enable"] + #[inline(always)] + pub fn transfer_err_int_ena(&self) -> TRANSFER_ERR_INT_ENA_R { + TRANSFER_ERR_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn transfer_complete_int_ena(&self) -> TRANSFER_COMPLETE_INT_ENA_R { + TRANSFER_COMPLETE_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn command_done_int_ena(&self) -> COMMAND_DONE_INT_ENA_R { + COMMAND_DONE_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn detect_start_int_ena(&self) -> DETECT_START_INT_ENA_R { + DETECT_START_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn resp_buf_ovf_int_ena(&self) -> RESP_BUF_OVF_INT_ENA_R { + RESP_BUF_OVF_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ibi_data_buf_ovf_int_ena(&self) -> IBI_DATA_BUF_OVF_INT_ENA_R { + IBI_DATA_BUF_OVF_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ibi_status_buf_ovf_int_ena(&self) -> IBI_STATUS_BUF_OVF_INT_ENA_R { + IBI_STATUS_BUF_OVF_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ibi_handle_done_int_ena(&self) -> IBI_HANDLE_DONE_INT_ENA_R { + IBI_HANDLE_DONE_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ibi_detect_int_ena(&self) -> IBI_DETECT_INT_ENA_R { + IBI_DETECT_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn cmd_ccc_mismatch_int_ena(&self) -> CMD_CCC_MISMATCH_INT_ENA_R { + CMD_CCC_MISMATCH_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_ENA") + .field( + "tx_data_buf_thld_int_ena", + &format_args!("{}", self.tx_data_buf_thld_int_ena().bit()), + ) + .field( + "rx_data_buf_thld_int_ena", + &format_args!("{}", self.rx_data_buf_thld_int_ena().bit()), + ) + .field( + "ibi_status_thld_int_ena", + &format_args!("{}", self.ibi_status_thld_int_ena().bit()), + ) + .field( + "cmd_buf_empty_thld_int_ena", + &format_args!("{}", self.cmd_buf_empty_thld_int_ena().bit()), + ) + .field( + "resp_ready_int_ena", + &format_args!("{}", self.resp_ready_int_ena().bit()), + ) + .field( + "nxt_cmd_req_err_int_ena", + &format_args!("{}", self.nxt_cmd_req_err_int_ena().bit()), + ) + .field( + "transfer_err_int_ena", + &format_args!("{}", self.transfer_err_int_ena().bit()), + ) + .field( + "transfer_complete_int_ena", + &format_args!("{}", self.transfer_complete_int_ena().bit()), + ) + .field( + "command_done_int_ena", + &format_args!("{}", self.command_done_int_ena().bit()), + ) + .field( + "detect_start_int_ena", + &format_args!("{}", self.detect_start_int_ena().bit()), + ) + .field( + "resp_buf_ovf_int_ena", + &format_args!("{}", self.resp_buf_ovf_int_ena().bit()), + ) + .field( + "ibi_data_buf_ovf_int_ena", + &format_args!("{}", self.ibi_data_buf_ovf_int_ena().bit()), + ) + .field( + "ibi_status_buf_ovf_int_ena", + &format_args!("{}", self.ibi_status_buf_ovf_int_ena().bit()), + ) + .field( + "ibi_handle_done_int_ena", + &format_args!("{}", self.ibi_handle_done_int_ena().bit()), + ) + .field( + "ibi_detect_int_ena", + &format_args!("{}", self.ibi_detect_int_ena().bit()), + ) + .field( + "cmd_ccc_mismatch_int_ena", + &format_args!("{}", self.cmd_ccc_mismatch_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Transmit Buffer threshold status enable."] + #[inline(always)] + #[must_use] + pub fn tx_data_buf_thld_int_ena(&mut self) -> TX_DATA_BUF_THLD_INT_ENA_W { + TX_DATA_BUF_THLD_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Receive Buffer threshold status enable."] + #[inline(always)] + #[must_use] + pub fn rx_data_buf_thld_int_ena(&mut self) -> RX_DATA_BUF_THLD_INT_ENA_W { + RX_DATA_BUF_THLD_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Only used in master mode. IBI Buffer threshold status enable."] + #[inline(always)] + #[must_use] + pub fn ibi_status_thld_int_ena(&mut self) -> IBI_STATUS_THLD_INT_ENA_W { + IBI_STATUS_THLD_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Command buffer ready status enable."] + #[inline(always)] + #[must_use] + pub fn cmd_buf_empty_thld_int_ena(&mut self) -> CMD_BUF_EMPTY_THLD_INT_ENA_W { + CMD_BUF_EMPTY_THLD_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Response buffer ready status enable."] + #[inline(always)] + #[must_use] + pub fn resp_ready_int_ena(&mut self) -> RESP_READY_INT_ENA_W { + RESP_READY_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - next command request error status enable"] + #[inline(always)] + #[must_use] + pub fn nxt_cmd_req_err_int_ena(&mut self) -> NXT_CMD_REQ_ERR_INT_ENA_W { + NXT_CMD_REQ_ERR_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - Transfer error status enable"] + #[inline(always)] + #[must_use] + pub fn transfer_err_int_ena(&mut self) -> TRANSFER_ERR_INT_ENA_W { + TRANSFER_ERR_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn transfer_complete_int_ena(&mut self) -> TRANSFER_COMPLETE_INT_ENA_W { + TRANSFER_COMPLETE_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn command_done_int_ena(&mut self) -> COMMAND_DONE_INT_ENA_W { + COMMAND_DONE_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn detect_start_int_ena(&mut self) -> DETECT_START_INT_ENA_W { + DETECT_START_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn resp_buf_ovf_int_ena(&mut self) -> RESP_BUF_OVF_INT_ENA_W { + RESP_BUF_OVF_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_data_buf_ovf_int_ena(&mut self) -> IBI_DATA_BUF_OVF_INT_ENA_W { + IBI_DATA_BUF_OVF_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_status_buf_ovf_int_ena(&mut self) -> IBI_STATUS_BUF_OVF_INT_ENA_W { + IBI_STATUS_BUF_OVF_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_handle_done_int_ena(&mut self) -> IBI_HANDLE_DONE_INT_ENA_W { + IBI_HANDLE_DONE_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn ibi_detect_int_ena(&mut self) -> IBI_DETECT_INT_ENA_W { + IBI_DETECT_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn cmd_ccc_mismatch_int_ena(&mut self) -> CMD_CCC_MISMATCH_INT_ENA_W { + CMD_CCC_MISMATCH_INT_ENA_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_st_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_ENA_SPEC; +impl crate::RegisterSpec for INT_ST_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_ena::R`](R) reader structure"] +impl crate::Readable for INT_ST_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_st_ena::W`](W) writer structure"] +impl crate::Writable for INT_ST_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ST_ENA to value 0"] +impl crate::Resettable for INT_ST_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/present_state0.rs b/esp32p4/src/i3c_mst/present_state0.rs new file mode 100644 index 0000000000..84ce66bb8e --- /dev/null +++ b/esp32p4/src/i3c_mst/present_state0.rs @@ -0,0 +1,134 @@ +#[doc = "Register `PRESENT_STATE0` reader"] +pub type R = crate::R; +#[doc = "Field `SDA_LVL` reader - This bit is used to check the SCL line level to recover from error and for debugging. This bit reflects the value of synchronized scl_in_a."] +pub type SDA_LVL_R = crate::BitReader; +#[doc = "Field `SCL_LVL` reader - This bit is used to check the SDA line level to recover from error and for debugging. This bit reflects the value of synchronized sda_in_a."] +pub type SCL_LVL_R = crate::BitReader; +#[doc = "Field `BUS_BUSY` reader - NA"] +pub type BUS_BUSY_R = crate::BitReader; +#[doc = "Field `BUS_FREE` reader - NA"] +pub type BUS_FREE_R = crate::BitReader; +#[doc = "Field `CMD_TID` reader - NA"] +pub type CMD_TID_R = crate::FieldReader; +#[doc = "Field `SCL_GEN_FSM_STATE` reader - NA"] +pub type SCL_GEN_FSM_STATE_R = crate::FieldReader; +#[doc = "Field `IBI_EV_HANDLE_FSM_STATE` reader - NA"] +pub type IBI_EV_HANDLE_FSM_STATE_R = crate::FieldReader; +#[doc = "Field `I2C_MODE_FSM_STATE` reader - NA"] +pub type I2C_MODE_FSM_STATE_R = crate::FieldReader; +#[doc = "Field `SDR_MODE_FSM_STATE` reader - NA"] +pub type SDR_MODE_FSM_STATE_R = crate::FieldReader; +#[doc = "Field `DAA_MODE_FSM_STATE` reader - Reflects whether the Master Controller is in IDLE or not. This bit will be set when all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the Master State machine is in idle state. 0X0: not in idle 0x1: in idle"] +pub type DAA_MODE_FSM_STATE_R = crate::FieldReader; +#[doc = "Field `MAIN_FSM_STATE` reader - NA"] +pub type MAIN_FSM_STATE_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - This bit is used to check the SCL line level to recover from error and for debugging. This bit reflects the value of synchronized scl_in_a."] + #[inline(always)] + pub fn sda_lvl(&self) -> SDA_LVL_R { + SDA_LVL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This bit is used to check the SDA line level to recover from error and for debugging. This bit reflects the value of synchronized sda_in_a."] + #[inline(always)] + pub fn scl_lvl(&self) -> SCL_LVL_R { + SCL_LVL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn bus_busy(&self) -> BUS_BUSY_R { + BUS_BUSY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn bus_free(&self) -> BUS_FREE_R { + BUS_FREE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 9:12 - NA"] + #[inline(always)] + pub fn cmd_tid(&self) -> CMD_TID_R { + CMD_TID_R::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bits 13:15 - NA"] + #[inline(always)] + pub fn scl_gen_fsm_state(&self) -> SCL_GEN_FSM_STATE_R { + SCL_GEN_FSM_STATE_R::new(((self.bits >> 13) & 7) as u8) + } + #[doc = "Bits 16:18 - NA"] + #[inline(always)] + pub fn ibi_ev_handle_fsm_state(&self) -> IBI_EV_HANDLE_FSM_STATE_R { + IBI_EV_HANDLE_FSM_STATE_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:21 - NA"] + #[inline(always)] + pub fn i2c_mode_fsm_state(&self) -> I2C_MODE_FSM_STATE_R { + I2C_MODE_FSM_STATE_R::new(((self.bits >> 19) & 7) as u8) + } + #[doc = "Bits 22:25 - NA"] + #[inline(always)] + pub fn sdr_mode_fsm_state(&self) -> SDR_MODE_FSM_STATE_R { + SDR_MODE_FSM_STATE_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:28 - Reflects whether the Master Controller is in IDLE or not. This bit will be set when all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the Master State machine is in idle state. 0X0: not in idle 0x1: in idle"] + #[inline(always)] + pub fn daa_mode_fsm_state(&self) -> DAA_MODE_FSM_STATE_R { + DAA_MODE_FSM_STATE_R::new(((self.bits >> 26) & 7) as u8) + } + #[doc = "Bits 29:31 - NA"] + #[inline(always)] + pub fn main_fsm_state(&self) -> MAIN_FSM_STATE_R { + MAIN_FSM_STATE_R::new(((self.bits >> 29) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PRESENT_STATE0") + .field("sda_lvl", &format_args!("{}", self.sda_lvl().bit())) + .field("scl_lvl", &format_args!("{}", self.scl_lvl().bit())) + .field("bus_busy", &format_args!("{}", self.bus_busy().bit())) + .field("bus_free", &format_args!("{}", self.bus_free().bit())) + .field("cmd_tid", &format_args!("{}", self.cmd_tid().bits())) + .field( + "scl_gen_fsm_state", + &format_args!("{}", self.scl_gen_fsm_state().bits()), + ) + .field( + "ibi_ev_handle_fsm_state", + &format_args!("{}", self.ibi_ev_handle_fsm_state().bits()), + ) + .field( + "i2c_mode_fsm_state", + &format_args!("{}", self.i2c_mode_fsm_state().bits()), + ) + .field( + "sdr_mode_fsm_state", + &format_args!("{}", self.sdr_mode_fsm_state().bits()), + ) + .field( + "daa_mode_fsm_state", + &format_args!("{}", self.daa_mode_fsm_state().bits()), + ) + .field( + "main_fsm_state", + &format_args!("{}", self.main_fsm_state().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`present_state0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PRESENT_STATE0_SPEC; +impl crate::RegisterSpec for PRESENT_STATE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`present_state0::R`](R) reader structure"] +impl crate::Readable for PRESENT_STATE0_SPEC {} +#[doc = "`reset()` method sets PRESENT_STATE0 to value 0x03"] +impl crate::Resettable for PRESENT_STATE0_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/i3c_mst/present_state1.rs b/esp32p4/src/i3c_mst/present_state1.rs new file mode 100644 index 0000000000..fb12f14ecf --- /dev/null +++ b/esp32p4/src/i3c_mst/present_state1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `PRESENT_STATE1` reader"] +pub type R = crate::R; +#[doc = "Field `DATA_BYTE_CNT` reader - Present transfer data byte cnt: tx data byte cnt if write rx data byte cnt if read ibi data byte cnt if IBI handle."] +pub type DATA_BYTE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Present transfer data byte cnt: tx data byte cnt if write rx data byte cnt if read ibi data byte cnt if IBI handle."] + #[inline(always)] + pub fn data_byte_cnt(&self) -> DATA_BYTE_CNT_R { + DATA_BYTE_CNT_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PRESENT_STATE1") + .field( + "data_byte_cnt", + &format_args!("{}", self.data_byte_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`present_state1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PRESENT_STATE1_SPEC; +impl crate::RegisterSpec for PRESENT_STATE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`present_state1::R`](R) reader structure"] +impl crate::Readable for PRESENT_STATE1_SPEC {} +#[doc = "`reset()` method sets PRESENT_STATE1 to value 0"] +impl crate::Resettable for PRESENT_STATE1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/reset_ctrl.rs b/esp32p4/src/i3c_mst/reset_ctrl.rs new file mode 100644 index 0000000000..cc774418d2 --- /dev/null +++ b/esp32p4/src/i3c_mst/reset_ctrl.rs @@ -0,0 +1,169 @@ +#[doc = "Register `RESET_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `RESET_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `REG_CORE_SOFT_RST` writer - NA"] +pub type REG_CORE_SOFT_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_CMD_BUF_RST` reader - NA"] +pub type REG_CMD_BUF_RST_R = crate::BitReader; +#[doc = "Field `REG_CMD_BUF_RST` writer - NA"] +pub type REG_CMD_BUF_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RESP_BUF_RST` reader - NA"] +pub type REG_RESP_BUF_RST_R = crate::BitReader; +#[doc = "Field `REG_RESP_BUF_RST` writer - NA"] +pub type REG_RESP_BUF_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_TX_DATA_BUF_BUF_RST` reader - NA"] +pub type REG_TX_DATA_BUF_BUF_RST_R = crate::BitReader; +#[doc = "Field `REG_TX_DATA_BUF_BUF_RST` writer - NA"] +pub type REG_TX_DATA_BUF_BUF_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RX_DATA_BUF_RST` reader - NA"] +pub type REG_RX_DATA_BUF_RST_R = crate::BitReader; +#[doc = "Field `REG_RX_DATA_BUF_RST` writer - NA"] +pub type REG_RX_DATA_BUF_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_IBI_DATA_BUF_RST` reader - NA"] +pub type REG_IBI_DATA_BUF_RST_R = crate::BitReader; +#[doc = "Field `REG_IBI_DATA_BUF_RST` writer - NA"] +pub type REG_IBI_DATA_BUF_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_IBI_STATUS_BUF_RST` reader - NA"] +pub type REG_IBI_STATUS_BUF_RST_R = crate::BitReader; +#[doc = "Field `REG_IBI_STATUS_BUF_RST` writer - NA"] +pub type REG_IBI_STATUS_BUF_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn reg_cmd_buf_rst(&self) -> REG_CMD_BUF_RST_R { + REG_CMD_BUF_RST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn reg_resp_buf_rst(&self) -> REG_RESP_BUF_RST_R { + REG_RESP_BUF_RST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn reg_tx_data_buf_buf_rst(&self) -> REG_TX_DATA_BUF_BUF_RST_R { + REG_TX_DATA_BUF_BUF_RST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn reg_rx_data_buf_rst(&self) -> REG_RX_DATA_BUF_RST_R { + REG_RX_DATA_BUF_RST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn reg_ibi_data_buf_rst(&self) -> REG_IBI_DATA_BUF_RST_R { + REG_IBI_DATA_BUF_RST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn reg_ibi_status_buf_rst(&self) -> REG_IBI_STATUS_BUF_RST_R { + REG_IBI_STATUS_BUF_RST_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESET_CTRL") + .field( + "reg_cmd_buf_rst", + &format_args!("{}", self.reg_cmd_buf_rst().bit()), + ) + .field( + "reg_resp_buf_rst", + &format_args!("{}", self.reg_resp_buf_rst().bit()), + ) + .field( + "reg_tx_data_buf_buf_rst", + &format_args!("{}", self.reg_tx_data_buf_buf_rst().bit()), + ) + .field( + "reg_rx_data_buf_rst", + &format_args!("{}", self.reg_rx_data_buf_rst().bit()), + ) + .field( + "reg_ibi_data_buf_rst", + &format_args!("{}", self.reg_ibi_data_buf_rst().bit()), + ) + .field( + "reg_ibi_status_buf_rst", + &format_args!("{}", self.reg_ibi_status_buf_rst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_core_soft_rst(&mut self) -> REG_CORE_SOFT_RST_W { + REG_CORE_SOFT_RST_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_cmd_buf_rst(&mut self) -> REG_CMD_BUF_RST_W { + REG_CMD_BUF_RST_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_resp_buf_rst(&mut self) -> REG_RESP_BUF_RST_W { + REG_RESP_BUF_RST_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_tx_data_buf_buf_rst(&mut self) -> REG_TX_DATA_BUF_BUF_RST_W { + REG_TX_DATA_BUF_BUF_RST_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_rx_data_buf_rst(&mut self) -> REG_RX_DATA_BUF_RST_W { + REG_RX_DATA_BUF_RST_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_ibi_data_buf_rst(&mut self) -> REG_IBI_DATA_BUF_RST_W { + REG_IBI_DATA_BUF_RST_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_ibi_status_buf_rst(&mut self) -> REG_IBI_STATUS_BUF_RST_W { + REG_IBI_STATUS_BUF_RST_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESET_CTRL_SPEC; +impl crate::RegisterSpec for RESET_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reset_ctrl::R`](R) reader structure"] +impl crate::Readable for RESET_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reset_ctrl::W`](W) writer structure"] +impl crate::Writable for RESET_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESET_CTRL to value 0"] +impl crate::Resettable for RESET_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/rnd_eco_cs.rs b/esp32p4/src/i3c_mst/rnd_eco_cs.rs new file mode 100644 index 0000000000..d8be6e0d04 --- /dev/null +++ b/esp32p4/src/i3c_mst/rnd_eco_cs.rs @@ -0,0 +1,77 @@ +#[doc = "Register `RND_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `REG_RND_ECO_EN` reader - NA"] +pub type REG_RND_ECO_EN_R = crate::BitReader; +#[doc = "Field `REG_RND_ECO_EN` writer - NA"] +pub type REG_RND_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RND_ECO_RESULT` reader - NA"] +pub type RND_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn reg_rnd_eco_en(&self) -> REG_RND_ECO_EN_R { + REG_RND_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn rnd_eco_result(&self) -> RND_ECO_RESULT_R { + RND_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_CS") + .field( + "reg_rnd_eco_en", + &format_args!("{}", self.reg_rnd_eco_en().bit()), + ) + .field( + "rnd_eco_result", + &format_args!("{}", self.rnd_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_rnd_eco_en(&mut self) -> REG_RND_ECO_EN_W { + REG_RND_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_CS_SPEC; +impl crate::RegisterSpec for RND_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_cs::R`](R) reader structure"] +impl crate::Readable for RND_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_cs::W`](W) writer structure"] +impl crate::Writable for RND_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_CS to value 0"] +impl crate::Resettable for RND_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/rnd_eco_high.rs b/esp32p4/src/i3c_mst/rnd_eco_high.rs new file mode 100644 index 0000000000..7874f07a2c --- /dev/null +++ b/esp32p4/src/i3c_mst/rnd_eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RND_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `REG_RND_ECO_HIGH` reader - NA"] +pub type REG_RND_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `REG_RND_ECO_HIGH` writer - NA"] +pub type REG_RND_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn reg_rnd_eco_high(&self) -> REG_RND_ECO_HIGH_R { + REG_RND_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_HIGH") + .field( + "reg_rnd_eco_high", + &format_args!("{}", self.reg_rnd_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_rnd_eco_high(&mut self) -> REG_RND_ECO_HIGH_W { + REG_RND_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_HIGH_SPEC; +impl crate::RegisterSpec for RND_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_high::R`](R) reader structure"] +impl crate::Readable for RND_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_high::W`](W) writer structure"] +impl crate::Writable for RND_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_HIGH to value 0xffff"] +impl crate::Resettable for RND_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff; +} diff --git a/esp32p4/src/i3c_mst/rnd_eco_low.rs b/esp32p4/src/i3c_mst/rnd_eco_low.rs new file mode 100644 index 0000000000..c2354107ec --- /dev/null +++ b/esp32p4/src/i3c_mst/rnd_eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RND_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `REG_RND_ECO_LOW` reader - NA"] +pub type REG_RND_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `REG_RND_ECO_LOW` writer - NA"] +pub type REG_RND_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn reg_rnd_eco_low(&self) -> REG_RND_ECO_LOW_R { + REG_RND_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_LOW") + .field( + "reg_rnd_eco_low", + &format_args!("{}", self.reg_rnd_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_rnd_eco_low(&mut self) -> REG_RND_ECO_LOW_W { + REG_RND_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_LOW_SPEC; +impl crate::RegisterSpec for RND_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_low::R`](R) reader structure"] +impl crate::Readable for RND_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_low::W`](W) writer structure"] +impl crate::Writable for RND_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_LOW to value 0"] +impl crate::Resettable for RND_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/scl_ext_low_time.rs b/esp32p4/src/i3c_mst/scl_ext_low_time.rs new file mode 100644 index 0000000000..6938147ebd --- /dev/null +++ b/esp32p4/src/i3c_mst/scl_ext_low_time.rs @@ -0,0 +1,131 @@ +#[doc = "Register `SCL_EXT_LOW_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_EXT_LOW_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I3C_MST_EXT_LOW_PERIOD1` reader - NA"] +pub type REG_I3C_MST_EXT_LOW_PERIOD1_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_EXT_LOW_PERIOD1` writer - NA"] +pub type REG_I3C_MST_EXT_LOW_PERIOD1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I3C_MST_EXT_LOW_PERIOD2` reader - NA"] +pub type REG_I3C_MST_EXT_LOW_PERIOD2_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_EXT_LOW_PERIOD2` writer - NA"] +pub type REG_I3C_MST_EXT_LOW_PERIOD2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I3C_MST_EXT_LOW_PERIOD3` reader - NA"] +pub type REG_I3C_MST_EXT_LOW_PERIOD3_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_EXT_LOW_PERIOD3` writer - NA"] +pub type REG_I3C_MST_EXT_LOW_PERIOD3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I3C_MST_EXT_LOW_PERIOD4` reader - NA"] +pub type REG_I3C_MST_EXT_LOW_PERIOD4_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_EXT_LOW_PERIOD4` writer - NA"] +pub type REG_I3C_MST_EXT_LOW_PERIOD4_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + pub fn reg_i3c_mst_ext_low_period1(&self) -> REG_I3C_MST_EXT_LOW_PERIOD1_R { + REG_I3C_MST_EXT_LOW_PERIOD1_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + pub fn reg_i3c_mst_ext_low_period2(&self) -> REG_I3C_MST_EXT_LOW_PERIOD2_R { + REG_I3C_MST_EXT_LOW_PERIOD2_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn reg_i3c_mst_ext_low_period3(&self) -> REG_I3C_MST_EXT_LOW_PERIOD3_R { + REG_I3C_MST_EXT_LOW_PERIOD3_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - NA"] + #[inline(always)] + pub fn reg_i3c_mst_ext_low_period4(&self) -> REG_I3C_MST_EXT_LOW_PERIOD4_R { + REG_I3C_MST_EXT_LOW_PERIOD4_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_EXT_LOW_TIME") + .field( + "reg_i3c_mst_ext_low_period1", + &format_args!("{}", self.reg_i3c_mst_ext_low_period1().bits()), + ) + .field( + "reg_i3c_mst_ext_low_period2", + &format_args!("{}", self.reg_i3c_mst_ext_low_period2().bits()), + ) + .field( + "reg_i3c_mst_ext_low_period3", + &format_args!("{}", self.reg_i3c_mst_ext_low_period3().bits()), + ) + .field( + "reg_i3c_mst_ext_low_period4", + &format_args!("{}", self.reg_i3c_mst_ext_low_period4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_ext_low_period1( + &mut self, + ) -> REG_I3C_MST_EXT_LOW_PERIOD1_W { + REG_I3C_MST_EXT_LOW_PERIOD1_W::new(self, 0) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_ext_low_period2( + &mut self, + ) -> REG_I3C_MST_EXT_LOW_PERIOD2_W { + REG_I3C_MST_EXT_LOW_PERIOD2_W::new(self, 8) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_ext_low_period3( + &mut self, + ) -> REG_I3C_MST_EXT_LOW_PERIOD3_W { + REG_I3C_MST_EXT_LOW_PERIOD3_W::new(self, 16) + } + #[doc = "Bits 24:31 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_ext_low_period4( + &mut self, + ) -> REG_I3C_MST_EXT_LOW_PERIOD4_W { + REG_I3C_MST_EXT_LOW_PERIOD4_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_ext_low_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_ext_low_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_EXT_LOW_TIME_SPEC; +impl crate::RegisterSpec for SCL_EXT_LOW_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_ext_low_time::R`](R) reader structure"] +impl crate::Readable for SCL_EXT_LOW_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_ext_low_time::W`](W) writer structure"] +impl crate::Writable for SCL_EXT_LOW_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_EXT_LOW_TIME to value 0"] +impl crate::Resettable for SCL_EXT_LOW_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/scl_i2c_fm_time.rs b/esp32p4/src/i3c_mst/scl_i2c_fm_time.rs new file mode 100644 index 0000000000..b7a746c7bd --- /dev/null +++ b/esp32p4/src/i3c_mst/scl_i2c_fm_time.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SCL_I2C_FM_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_I2C_FM_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2C_FM_LOW_PERIOD` reader - NA"] +pub type REG_I2C_FM_LOW_PERIOD_R = crate::FieldReader; +#[doc = "Field `REG_I2C_FM_LOW_PERIOD` writer - NA"] +pub type REG_I2C_FM_LOW_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `REG_I2C_FM_HIGH_PERIOD` reader - The SCL open-drain low count timing for I2C Fast Mode transfers."] +pub type REG_I2C_FM_HIGH_PERIOD_R = crate::FieldReader; +#[doc = "Field `REG_I2C_FM_HIGH_PERIOD` writer - The SCL open-drain low count timing for I2C Fast Mode transfers."] +pub type REG_I2C_FM_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn reg_i2c_fm_low_period(&self) -> REG_I2C_FM_LOW_PERIOD_R { + REG_I2C_FM_LOW_PERIOD_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - The SCL open-drain low count timing for I2C Fast Mode transfers."] + #[inline(always)] + pub fn reg_i2c_fm_high_period(&self) -> REG_I2C_FM_HIGH_PERIOD_R { + REG_I2C_FM_HIGH_PERIOD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_I2C_FM_TIME") + .field( + "reg_i2c_fm_low_period", + &format_args!("{}", self.reg_i2c_fm_low_period().bits()), + ) + .field( + "reg_i2c_fm_high_period", + &format_args!("{}", self.reg_i2c_fm_high_period().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_i2c_fm_low_period(&mut self) -> REG_I2C_FM_LOW_PERIOD_W { + REG_I2C_FM_LOW_PERIOD_W::new(self, 0) + } + #[doc = "Bits 16:31 - The SCL open-drain low count timing for I2C Fast Mode transfers."] + #[inline(always)] + #[must_use] + pub fn reg_i2c_fm_high_period(&mut self) -> REG_I2C_FM_HIGH_PERIOD_W { + REG_I2C_FM_HIGH_PERIOD_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_i2c_fm_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_i2c_fm_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_I2C_FM_TIME_SPEC; +impl crate::RegisterSpec for SCL_I2C_FM_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_i2c_fm_time::R`](R) reader structure"] +impl crate::Readable for SCL_I2C_FM_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_i2c_fm_time::W`](W) writer structure"] +impl crate::Writable for SCL_I2C_FM_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_I2C_FM_TIME to value 0x004b_00a3"] +impl crate::Resettable for SCL_I2C_FM_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0x004b_00a3; +} diff --git a/esp32p4/src/i3c_mst/scl_i2c_fmp_time.rs b/esp32p4/src/i3c_mst/scl_i2c_fmp_time.rs new file mode 100644 index 0000000000..025ac00f41 --- /dev/null +++ b/esp32p4/src/i3c_mst/scl_i2c_fmp_time.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SCL_I2C_FMP_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_I2C_FMP_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I2C_FMP_LOW_PERIOD` reader - NA"] +pub type REG_I2C_FMP_LOW_PERIOD_R = crate::FieldReader; +#[doc = "Field `REG_I2C_FMP_LOW_PERIOD` writer - NA"] +pub type REG_I2C_FMP_LOW_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `REG_I2C_FMP_HIGH_PERIOD` reader - NA"] +pub type REG_I2C_FMP_HIGH_PERIOD_R = crate::FieldReader; +#[doc = "Field `REG_I2C_FMP_HIGH_PERIOD` writer - NA"] +pub type REG_I2C_FMP_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn reg_i2c_fmp_low_period(&self) -> REG_I2C_FMP_LOW_PERIOD_R { + REG_I2C_FMP_LOW_PERIOD_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn reg_i2c_fmp_high_period(&self) -> REG_I2C_FMP_HIGH_PERIOD_R { + REG_I2C_FMP_HIGH_PERIOD_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_I2C_FMP_TIME") + .field( + "reg_i2c_fmp_low_period", + &format_args!("{}", self.reg_i2c_fmp_low_period().bits()), + ) + .field( + "reg_i2c_fmp_high_period", + &format_args!("{}", self.reg_i2c_fmp_high_period().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_i2c_fmp_low_period(&mut self) -> REG_I2C_FMP_LOW_PERIOD_W { + REG_I2C_FMP_LOW_PERIOD_W::new(self, 0) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_i2c_fmp_high_period(&mut self) -> REG_I2C_FMP_HIGH_PERIOD_W { + REG_I2C_FMP_HIGH_PERIOD_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_i2c_fmp_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_i2c_fmp_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_I2C_FMP_TIME_SPEC; +impl crate::RegisterSpec for SCL_I2C_FMP_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_i2c_fmp_time::R`](R) reader structure"] +impl crate::Readable for SCL_I2C_FMP_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_i2c_fmp_time::W`](W) writer structure"] +impl crate::Writable for SCL_I2C_FMP_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_I2C_FMP_TIME to value 0x0021_003f"] +impl crate::Resettable for SCL_I2C_FMP_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0x0021_003f; +} diff --git a/esp32p4/src/i3c_mst/scl_i3c_mst_od_time.rs b/esp32p4/src/i3c_mst/scl_i3c_mst_od_time.rs new file mode 100644 index 0000000000..34c36ab887 --- /dev/null +++ b/esp32p4/src/i3c_mst/scl_i3c_mst_od_time.rs @@ -0,0 +1,89 @@ +#[doc = "Register `SCL_I3C_MST_OD_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_I3C_MST_OD_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I3C_MST_OD_LOW_PERIOD` reader - SCL Open-Drain low count for I3C transfers targeted to I3C devices."] +pub type REG_I3C_MST_OD_LOW_PERIOD_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_OD_LOW_PERIOD` writer - SCL Open-Drain low count for I3C transfers targeted to I3C devices."] +pub type REG_I3C_MST_OD_LOW_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `REG_I3C_MST_OD_HIGH_PERIOD` reader - SCL Open-Drain High count for I3C transfers targeted to I3C devices."] +pub type REG_I3C_MST_OD_HIGH_PERIOD_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_OD_HIGH_PERIOD` writer - SCL Open-Drain High count for I3C transfers targeted to I3C devices."] +pub type REG_I3C_MST_OD_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - SCL Open-Drain low count for I3C transfers targeted to I3C devices."] + #[inline(always)] + pub fn reg_i3c_mst_od_low_period(&self) -> REG_I3C_MST_OD_LOW_PERIOD_R { + REG_I3C_MST_OD_LOW_PERIOD_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - SCL Open-Drain High count for I3C transfers targeted to I3C devices."] + #[inline(always)] + pub fn reg_i3c_mst_od_high_period(&self) -> REG_I3C_MST_OD_HIGH_PERIOD_R { + REG_I3C_MST_OD_HIGH_PERIOD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_I3C_MST_OD_TIME") + .field( + "reg_i3c_mst_od_low_period", + &format_args!("{}", self.reg_i3c_mst_od_low_period().bits()), + ) + .field( + "reg_i3c_mst_od_high_period", + &format_args!("{}", self.reg_i3c_mst_od_high_period().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - SCL Open-Drain low count for I3C transfers targeted to I3C devices."] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_od_low_period( + &mut self, + ) -> REG_I3C_MST_OD_LOW_PERIOD_W { + REG_I3C_MST_OD_LOW_PERIOD_W::new(self, 0) + } + #[doc = "Bits 16:31 - SCL Open-Drain High count for I3C transfers targeted to I3C devices."] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_od_high_period( + &mut self, + ) -> REG_I3C_MST_OD_HIGH_PERIOD_W { + REG_I3C_MST_OD_HIGH_PERIOD_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_i3c_mst_od_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_i3c_mst_od_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_I3C_MST_OD_TIME_SPEC; +impl crate::RegisterSpec for SCL_I3C_MST_OD_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_i3c_mst_od_time::R`](R) reader structure"] +impl crate::Readable for SCL_I3C_MST_OD_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_i3c_mst_od_time::W`](W) writer structure"] +impl crate::Writable for SCL_I3C_MST_OD_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_I3C_MST_OD_TIME to value 0x0005_0019"] +impl crate::Resettable for SCL_I3C_MST_OD_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0x0005_0019; +} diff --git a/esp32p4/src/i3c_mst/scl_i3c_mst_pp_time.rs b/esp32p4/src/i3c_mst/scl_i3c_mst_pp_time.rs new file mode 100644 index 0000000000..4026550fb1 --- /dev/null +++ b/esp32p4/src/i3c_mst/scl_i3c_mst_pp_time.rs @@ -0,0 +1,89 @@ +#[doc = "Register `SCL_I3C_MST_PP_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_I3C_MST_PP_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I3C_MST_PP_LOW_PERIOD` reader - NA"] +pub type REG_I3C_MST_PP_LOW_PERIOD_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_PP_LOW_PERIOD` writer - NA"] +pub type REG_I3C_MST_PP_LOW_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_I3C_MST_PP_HIGH_PERIOD` reader - NA"] +pub type REG_I3C_MST_PP_HIGH_PERIOD_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_PP_HIGH_PERIOD` writer - NA"] +pub type REG_I3C_MST_PP_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + pub fn reg_i3c_mst_pp_low_period(&self) -> REG_I3C_MST_PP_LOW_PERIOD_R { + REG_I3C_MST_PP_LOW_PERIOD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn reg_i3c_mst_pp_high_period(&self) -> REG_I3C_MST_PP_HIGH_PERIOD_R { + REG_I3C_MST_PP_HIGH_PERIOD_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_I3C_MST_PP_TIME") + .field( + "reg_i3c_mst_pp_low_period", + &format_args!("{}", self.reg_i3c_mst_pp_low_period().bits()), + ) + .field( + "reg_i3c_mst_pp_high_period", + &format_args!("{}", self.reg_i3c_mst_pp_high_period().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_pp_low_period( + &mut self, + ) -> REG_I3C_MST_PP_LOW_PERIOD_W { + REG_I3C_MST_PP_LOW_PERIOD_W::new(self, 0) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_pp_high_period( + &mut self, + ) -> REG_I3C_MST_PP_HIGH_PERIOD_W { + REG_I3C_MST_PP_HIGH_PERIOD_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_i3c_mst_pp_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_i3c_mst_pp_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_I3C_MST_PP_TIME_SPEC; +impl crate::RegisterSpec for SCL_I3C_MST_PP_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_i3c_mst_pp_time::R`](R) reader structure"] +impl crate::Readable for SCL_I3C_MST_PP_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_i3c_mst_pp_time::W`](W) writer structure"] +impl crate::Writable for SCL_I3C_MST_PP_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_I3C_MST_PP_TIME to value 0x0005_0005"] +impl crate::Resettable for SCL_I3C_MST_PP_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0x0005_0005; +} diff --git a/esp32p4/src/i3c_mst/scl_rstart_setup.rs b/esp32p4/src/i3c_mst/scl_rstart_setup.rs new file mode 100644 index 0000000000..4a86989380 --- /dev/null +++ b/esp32p4/src/i3c_mst/scl_rstart_setup.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SCL_RSTART_SETUP` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_RSTART_SETUP` writer"] +pub type W = crate::W; +#[doc = "Field `REG_SCL_RSTART_SETUP_TIME` reader - I2C_SCL_RSTART_SETUP_TIME"] +pub type REG_SCL_RSTART_SETUP_TIME_R = crate::FieldReader; +#[doc = "Field `REG_SCL_RSTART_SETUP_TIME` writer - I2C_SCL_RSTART_SETUP_TIME"] +pub type REG_SCL_RSTART_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - I2C_SCL_RSTART_SETUP_TIME"] + #[inline(always)] + pub fn reg_scl_rstart_setup_time(&self) -> REG_SCL_RSTART_SETUP_TIME_R { + REG_SCL_RSTART_SETUP_TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_RSTART_SETUP") + .field( + "reg_scl_rstart_setup_time", + &format_args!("{}", self.reg_scl_rstart_setup_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - I2C_SCL_RSTART_SETUP_TIME"] + #[inline(always)] + #[must_use] + pub fn reg_scl_rstart_setup_time( + &mut self, + ) -> REG_SCL_RSTART_SETUP_TIME_W { + REG_SCL_RSTART_SETUP_TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_rstart_setup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_rstart_setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_RSTART_SETUP_SPEC; +impl crate::RegisterSpec for SCL_RSTART_SETUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_rstart_setup::R`](R) reader structure"] +impl crate::Readable for SCL_RSTART_SETUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_rstart_setup::W`](W) writer structure"] +impl crate::Writable for SCL_RSTART_SETUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_RSTART_SETUP to value 0x08"] +impl crate::Resettable for SCL_RSTART_SETUP_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/i3c_mst/scl_start_hold.rs b/esp32p4/src/i3c_mst/scl_start_hold.rs new file mode 100644 index 0000000000..9c2d9b388c --- /dev/null +++ b/esp32p4/src/i3c_mst/scl_start_hold.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SCL_START_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_START_HOLD` writer"] +pub type W = crate::W; +#[doc = "Field `REG_SCL_START_HOLD_TIME` reader - I2C_SCL_START_HOLD_TIME"] +pub type REG_SCL_START_HOLD_TIME_R = crate::FieldReader; +#[doc = "Field `REG_SCL_START_HOLD_TIME` writer - I2C_SCL_START_HOLD_TIME"] +pub type REG_SCL_START_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_START_DET_HOLD_TIME` reader - NA"] +pub type REG_START_DET_HOLD_TIME_R = crate::FieldReader; +#[doc = "Field `REG_START_DET_HOLD_TIME` writer - NA"] +pub type REG_START_DET_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:8 - I2C_SCL_START_HOLD_TIME"] + #[inline(always)] + pub fn reg_scl_start_hold_time(&self) -> REG_SCL_START_HOLD_TIME_R { + REG_SCL_START_HOLD_TIME_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:10 - NA"] + #[inline(always)] + pub fn reg_start_det_hold_time(&self) -> REG_START_DET_HOLD_TIME_R { + REG_START_DET_HOLD_TIME_R::new(((self.bits >> 9) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_START_HOLD") + .field( + "reg_scl_start_hold_time", + &format_args!("{}", self.reg_scl_start_hold_time().bits()), + ) + .field( + "reg_start_det_hold_time", + &format_args!("{}", self.reg_start_det_hold_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - I2C_SCL_START_HOLD_TIME"] + #[inline(always)] + #[must_use] + pub fn reg_scl_start_hold_time(&mut self) -> REG_SCL_START_HOLD_TIME_W { + REG_SCL_START_HOLD_TIME_W::new(self, 0) + } + #[doc = "Bits 9:10 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_start_det_hold_time(&mut self) -> REG_START_DET_HOLD_TIME_W { + REG_START_DET_HOLD_TIME_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_start_hold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_start_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_START_HOLD_SPEC; +impl crate::RegisterSpec for SCL_START_HOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_start_hold::R`](R) reader structure"] +impl crate::Readable for SCL_START_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_start_hold::W`](W) writer structure"] +impl crate::Writable for SCL_START_HOLD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_START_HOLD to value 0x08"] +impl crate::Resettable for SCL_START_HOLD_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/i3c_mst/scl_stop_hold.rs b/esp32p4/src/i3c_mst/scl_stop_hold.rs new file mode 100644 index 0000000000..a1838e5b62 --- /dev/null +++ b/esp32p4/src/i3c_mst/scl_stop_hold.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SCL_STOP_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_STOP_HOLD` writer"] +pub type W = crate::W; +#[doc = "Field `REG_SCL_STOP_HOLD_TIME` reader - I2C_SCL_STOP_HOLD_TIME"] +pub type REG_SCL_STOP_HOLD_TIME_R = crate::FieldReader; +#[doc = "Field `REG_SCL_STOP_HOLD_TIME` writer - I2C_SCL_STOP_HOLD_TIME"] +pub type REG_SCL_STOP_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - I2C_SCL_STOP_HOLD_TIME"] + #[inline(always)] + pub fn reg_scl_stop_hold_time(&self) -> REG_SCL_STOP_HOLD_TIME_R { + REG_SCL_STOP_HOLD_TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_STOP_HOLD") + .field( + "reg_scl_stop_hold_time", + &format_args!("{}", self.reg_scl_stop_hold_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - I2C_SCL_STOP_HOLD_TIME"] + #[inline(always)] + #[must_use] + pub fn reg_scl_stop_hold_time(&mut self) -> REG_SCL_STOP_HOLD_TIME_W { + REG_SCL_STOP_HOLD_TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_hold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_STOP_HOLD_SPEC; +impl crate::RegisterSpec for SCL_STOP_HOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_stop_hold::R`](R) reader structure"] +impl crate::Readable for SCL_STOP_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_stop_hold::W`](W) writer structure"] +impl crate::Writable for SCL_STOP_HOLD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_STOP_HOLD to value 0x08"] +impl crate::Resettable for SCL_STOP_HOLD_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/i3c_mst/scl_stop_setup.rs b/esp32p4/src/i3c_mst/scl_stop_setup.rs new file mode 100644 index 0000000000..751fbcd02d --- /dev/null +++ b/esp32p4/src/i3c_mst/scl_stop_setup.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SCL_STOP_SETUP` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_STOP_SETUP` writer"] +pub type W = crate::W; +#[doc = "Field `REG_SCL_STOP_SETUP_TIME` reader - I2C_SCL_STOP_SETUP_TIME"] +pub type REG_SCL_STOP_SETUP_TIME_R = crate::FieldReader; +#[doc = "Field `REG_SCL_STOP_SETUP_TIME` writer - I2C_SCL_STOP_SETUP_TIME"] +pub type REG_SCL_STOP_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - I2C_SCL_STOP_SETUP_TIME"] + #[inline(always)] + pub fn reg_scl_stop_setup_time(&self) -> REG_SCL_STOP_SETUP_TIME_R { + REG_SCL_STOP_SETUP_TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_STOP_SETUP") + .field( + "reg_scl_stop_setup_time", + &format_args!("{}", self.reg_scl_stop_setup_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - I2C_SCL_STOP_SETUP_TIME"] + #[inline(always)] + #[must_use] + pub fn reg_scl_stop_setup_time(&mut self) -> REG_SCL_STOP_SETUP_TIME_W { + REG_SCL_STOP_SETUP_TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_setup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_STOP_SETUP_SPEC; +impl crate::RegisterSpec for SCL_STOP_SETUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_stop_setup::R`](R) reader structure"] +impl crate::Readable for SCL_STOP_SETUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_stop_setup::W`](W) writer structure"] +impl crate::Writable for SCL_STOP_SETUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_STOP_SETUP to value 0x08"] +impl crate::Resettable for SCL_STOP_SETUP_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/i3c_mst/scl_termn_t_ext_low_time.rs b/esp32p4/src/i3c_mst/scl_termn_t_ext_low_time.rs new file mode 100644 index 0000000000..2420cbb2e3 --- /dev/null +++ b/esp32p4/src/i3c_mst/scl_termn_t_ext_low_time.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SCL_TERMN_T_EXT_LOW_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_TERMN_T_EXT_LOW_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I3C_MST_TERMN_T_EXT_LOW_TIME` reader - NA"] +pub type REG_I3C_MST_TERMN_T_EXT_LOW_TIME_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_TERMN_T_EXT_LOW_TIME` writer - NA"] +pub type REG_I3C_MST_TERMN_T_EXT_LOW_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + pub fn reg_i3c_mst_termn_t_ext_low_time(&self) -> REG_I3C_MST_TERMN_T_EXT_LOW_TIME_R { + REG_I3C_MST_TERMN_T_EXT_LOW_TIME_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_TERMN_T_EXT_LOW_TIME") + .field( + "reg_i3c_mst_termn_t_ext_low_time", + &format_args!("{}", self.reg_i3c_mst_termn_t_ext_low_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_termn_t_ext_low_time( + &mut self, + ) -> REG_I3C_MST_TERMN_T_EXT_LOW_TIME_W { + REG_I3C_MST_TERMN_T_EXT_LOW_TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_termn_t_ext_low_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_termn_t_ext_low_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_TERMN_T_EXT_LOW_TIME_SPEC; +impl crate::RegisterSpec for SCL_TERMN_T_EXT_LOW_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_termn_t_ext_low_time::R`](R) reader structure"] +impl crate::Readable for SCL_TERMN_T_EXT_LOW_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_termn_t_ext_low_time::W`](W) writer structure"] +impl crate::Writable for SCL_TERMN_T_EXT_LOW_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_TERMN_T_EXT_LOW_TIME to value 0x02"] +impl crate::Resettable for SCL_TERMN_T_EXT_LOW_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/i3c_mst/sda_hold_time.rs b/esp32p4/src/i3c_mst/sda_hold_time.rs new file mode 100644 index 0000000000..04f1c660c6 --- /dev/null +++ b/esp32p4/src/i3c_mst/sda_hold_time.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SDA_HOLD_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `SDA_HOLD_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `REG_SDA_OD_TX_HOLD_TIME` reader - It is used to adjust sda drive point after scl neg under open drain speed"] +pub type REG_SDA_OD_TX_HOLD_TIME_R = crate::FieldReader; +#[doc = "Field `REG_SDA_OD_TX_HOLD_TIME` writer - It is used to adjust sda drive point after scl neg under open drain speed"] +pub type REG_SDA_OD_TX_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_SDA_PP_TX_HOLD_TIME` reader - It is used to adjust sda dirve point after scl neg under push pull speed"] +pub type REG_SDA_PP_TX_HOLD_TIME_R = crate::FieldReader; +#[doc = "Field `REG_SDA_PP_TX_HOLD_TIME` writer - It is used to adjust sda dirve point after scl neg under push pull speed"] +pub type REG_SDA_PP_TX_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:8 - It is used to adjust sda drive point after scl neg under open drain speed"] + #[inline(always)] + pub fn reg_sda_od_tx_hold_time(&self) -> REG_SDA_OD_TX_HOLD_TIME_R { + REG_SDA_OD_TX_HOLD_TIME_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:13 - It is used to adjust sda dirve point after scl neg under push pull speed"] + #[inline(always)] + pub fn reg_sda_pp_tx_hold_time(&self) -> REG_SDA_PP_TX_HOLD_TIME_R { + REG_SDA_PP_TX_HOLD_TIME_R::new(((self.bits >> 9) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDA_HOLD_TIME") + .field( + "reg_sda_od_tx_hold_time", + &format_args!("{}", self.reg_sda_od_tx_hold_time().bits()), + ) + .field( + "reg_sda_pp_tx_hold_time", + &format_args!("{}", self.reg_sda_pp_tx_hold_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - It is used to adjust sda drive point after scl neg under open drain speed"] + #[inline(always)] + #[must_use] + pub fn reg_sda_od_tx_hold_time(&mut self) -> REG_SDA_OD_TX_HOLD_TIME_W { + REG_SDA_OD_TX_HOLD_TIME_W::new(self, 0) + } + #[doc = "Bits 9:13 - It is used to adjust sda dirve point after scl neg under push pull speed"] + #[inline(always)] + #[must_use] + pub fn reg_sda_pp_tx_hold_time(&mut self) -> REG_SDA_PP_TX_HOLD_TIME_W { + REG_SDA_PP_TX_HOLD_TIME_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDA_HOLD_TIME_SPEC; +impl crate::RegisterSpec for SDA_HOLD_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sda_hold_time::R`](R) reader structure"] +impl crate::Readable for SDA_HOLD_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sda_hold_time::W`](W) writer structure"] +impl crate::Writable for SDA_HOLD_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDA_HOLD_TIME to value 0x01"] +impl crate::Resettable for SDA_HOLD_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/i3c_mst/sda_sample_time.rs b/esp32p4/src/i3c_mst/sda_sample_time.rs new file mode 100644 index 0000000000..7c55130fcb --- /dev/null +++ b/esp32p4/src/i3c_mst/sda_sample_time.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SDA_SAMPLE_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `SDA_SAMPLE_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `REG_SDA_OD_SAMPLE_TIME` reader - It is used to adjust sda sample point when scl high under open drain speed"] +pub type REG_SDA_OD_SAMPLE_TIME_R = crate::FieldReader; +#[doc = "Field `REG_SDA_OD_SAMPLE_TIME` writer - It is used to adjust sda sample point when scl high under open drain speed"] +pub type REG_SDA_OD_SAMPLE_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `REG_SDA_PP_SAMPLE_TIME` reader - It is used to adjust sda sample point when scl high under push pull speed"] +pub type REG_SDA_PP_SAMPLE_TIME_R = crate::FieldReader; +#[doc = "Field `REG_SDA_PP_SAMPLE_TIME` writer - It is used to adjust sda sample point when scl high under push pull speed"] +pub type REG_SDA_PP_SAMPLE_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:8 - It is used to adjust sda sample point when scl high under open drain speed"] + #[inline(always)] + pub fn reg_sda_od_sample_time(&self) -> REG_SDA_OD_SAMPLE_TIME_R { + REG_SDA_OD_SAMPLE_TIME_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:13 - It is used to adjust sda sample point when scl high under push pull speed"] + #[inline(always)] + pub fn reg_sda_pp_sample_time(&self) -> REG_SDA_PP_SAMPLE_TIME_R { + REG_SDA_PP_SAMPLE_TIME_R::new(((self.bits >> 9) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDA_SAMPLE_TIME") + .field( + "reg_sda_od_sample_time", + &format_args!("{}", self.reg_sda_od_sample_time().bits()), + ) + .field( + "reg_sda_pp_sample_time", + &format_args!("{}", self.reg_sda_pp_sample_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - It is used to adjust sda sample point when scl high under open drain speed"] + #[inline(always)] + #[must_use] + pub fn reg_sda_od_sample_time(&mut self) -> REG_SDA_OD_SAMPLE_TIME_W { + REG_SDA_OD_SAMPLE_TIME_W::new(self, 0) + } + #[doc = "Bits 9:13 - It is used to adjust sda sample point when scl high under push pull speed"] + #[inline(always)] + #[must_use] + pub fn reg_sda_pp_sample_time(&mut self) -> REG_SDA_PP_SAMPLE_TIME_W { + REG_SDA_PP_SAMPLE_TIME_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_sample_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_sample_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDA_SAMPLE_TIME_SPEC; +impl crate::RegisterSpec for SDA_SAMPLE_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sda_sample_time::R`](R) reader structure"] +impl crate::Readable for SDA_SAMPLE_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sda_sample_time::W`](W) writer structure"] +impl crate::Writable for SDA_SAMPLE_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDA_SAMPLE_TIME to value 0"] +impl crate::Resettable for SDA_SAMPLE_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst/time_out_value.rs b/esp32p4/src/i3c_mst/time_out_value.rs new file mode 100644 index 0000000000..a447592ab4 --- /dev/null +++ b/esp32p4/src/i3c_mst/time_out_value.rs @@ -0,0 +1,203 @@ +#[doc = "Register `TIME_OUT_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `TIME_OUT_VALUE` writer"] +pub type W = crate::W; +#[doc = "Field `REG_RESP_BUF_TO_VALUE` reader - NA"] +pub type REG_RESP_BUF_TO_VALUE_R = crate::FieldReader; +#[doc = "Field `REG_RESP_BUF_TO_VALUE` writer - NA"] +pub type REG_RESP_BUF_TO_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `REG_RESP_BUF_TO_EN` reader - NA"] +pub type REG_RESP_BUF_TO_EN_R = crate::BitReader; +#[doc = "Field `REG_RESP_BUF_TO_EN` writer - NA"] +pub type REG_RESP_BUF_TO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_IBI_DATA_BUF_TO_VALUE` reader - NA"] +pub type REG_IBI_DATA_BUF_TO_VALUE_R = crate::FieldReader; +#[doc = "Field `REG_IBI_DATA_BUF_TO_VALUE` writer - NA"] +pub type REG_IBI_DATA_BUF_TO_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `REG_IBI_DATA_BUF_TO_EN` reader - NA"] +pub type REG_IBI_DATA_BUF_TO_EN_R = crate::BitReader; +#[doc = "Field `REG_IBI_DATA_BUF_TO_EN` writer - NA"] +pub type REG_IBI_DATA_BUF_TO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_IBI_STATUS_BUF_TO_VALUE` reader - NA"] +pub type REG_IBI_STATUS_BUF_TO_VALUE_R = crate::FieldReader; +#[doc = "Field `REG_IBI_STATUS_BUF_TO_VALUE` writer - NA"] +pub type REG_IBI_STATUS_BUF_TO_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `REG_IBI_STATUS_BUF_TO_EN` reader - NA"] +pub type REG_IBI_STATUS_BUF_TO_EN_R = crate::BitReader; +#[doc = "Field `REG_IBI_STATUS_BUF_TO_EN` writer - NA"] +pub type REG_IBI_STATUS_BUF_TO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_RX_DATA_BUF_TO_VALUE` reader - NA"] +pub type REG_RX_DATA_BUF_TO_VALUE_R = crate::FieldReader; +#[doc = "Field `REG_RX_DATA_BUF_TO_VALUE` writer - NA"] +pub type REG_RX_DATA_BUF_TO_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `REG_RX_DATA_BUF_TO_EN` reader - NA"] +pub type REG_RX_DATA_BUF_TO_EN_R = crate::BitReader; +#[doc = "Field `REG_RX_DATA_BUF_TO_EN` writer - NA"] +pub type REG_RX_DATA_BUF_TO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - NA"] + #[inline(always)] + pub fn reg_resp_buf_to_value(&self) -> REG_RESP_BUF_TO_VALUE_R { + REG_RESP_BUF_TO_VALUE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn reg_resp_buf_to_en(&self) -> REG_RESP_BUF_TO_EN_R { + REG_RESP_BUF_TO_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:10 - NA"] + #[inline(always)] + pub fn reg_ibi_data_buf_to_value(&self) -> REG_IBI_DATA_BUF_TO_VALUE_R { + REG_IBI_DATA_BUF_TO_VALUE_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn reg_ibi_data_buf_to_en(&self) -> REG_IBI_DATA_BUF_TO_EN_R { + REG_IBI_DATA_BUF_TO_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:16 - NA"] + #[inline(always)] + pub fn reg_ibi_status_buf_to_value(&self) -> REG_IBI_STATUS_BUF_TO_VALUE_R { + REG_IBI_STATUS_BUF_TO_VALUE_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn reg_ibi_status_buf_to_en(&self) -> REG_IBI_STATUS_BUF_TO_EN_R { + REG_IBI_STATUS_BUF_TO_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:22 - NA"] + #[inline(always)] + pub fn reg_rx_data_buf_to_value(&self) -> REG_RX_DATA_BUF_TO_VALUE_R { + REG_RX_DATA_BUF_TO_VALUE_R::new(((self.bits >> 18) & 0x1f) as u8) + } + #[doc = "Bit 23 - NA"] + #[inline(always)] + pub fn reg_rx_data_buf_to_en(&self) -> REG_RX_DATA_BUF_TO_EN_R { + REG_RX_DATA_BUF_TO_EN_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIME_OUT_VALUE") + .field( + "reg_resp_buf_to_value", + &format_args!("{}", self.reg_resp_buf_to_value().bits()), + ) + .field( + "reg_resp_buf_to_en", + &format_args!("{}", self.reg_resp_buf_to_en().bit()), + ) + .field( + "reg_ibi_data_buf_to_value", + &format_args!("{}", self.reg_ibi_data_buf_to_value().bits()), + ) + .field( + "reg_ibi_data_buf_to_en", + &format_args!("{}", self.reg_ibi_data_buf_to_en().bit()), + ) + .field( + "reg_ibi_status_buf_to_value", + &format_args!("{}", self.reg_ibi_status_buf_to_value().bits()), + ) + .field( + "reg_ibi_status_buf_to_en", + &format_args!("{}", self.reg_ibi_status_buf_to_en().bit()), + ) + .field( + "reg_rx_data_buf_to_value", + &format_args!("{}", self.reg_rx_data_buf_to_value().bits()), + ) + .field( + "reg_rx_data_buf_to_en", + &format_args!("{}", self.reg_rx_data_buf_to_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_resp_buf_to_value(&mut self) -> REG_RESP_BUF_TO_VALUE_W { + REG_RESP_BUF_TO_VALUE_W::new(self, 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_resp_buf_to_en(&mut self) -> REG_RESP_BUF_TO_EN_W { + REG_RESP_BUF_TO_EN_W::new(self, 5) + } + #[doc = "Bits 6:10 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_ibi_data_buf_to_value( + &mut self, + ) -> REG_IBI_DATA_BUF_TO_VALUE_W { + REG_IBI_DATA_BUF_TO_VALUE_W::new(self, 6) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_ibi_data_buf_to_en(&mut self) -> REG_IBI_DATA_BUF_TO_EN_W { + REG_IBI_DATA_BUF_TO_EN_W::new(self, 11) + } + #[doc = "Bits 12:16 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_ibi_status_buf_to_value( + &mut self, + ) -> REG_IBI_STATUS_BUF_TO_VALUE_W { + REG_IBI_STATUS_BUF_TO_VALUE_W::new(self, 12) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_ibi_status_buf_to_en(&mut self) -> REG_IBI_STATUS_BUF_TO_EN_W { + REG_IBI_STATUS_BUF_TO_EN_W::new(self, 17) + } + #[doc = "Bits 18:22 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_rx_data_buf_to_value(&mut self) -> REG_RX_DATA_BUF_TO_VALUE_W { + REG_RX_DATA_BUF_TO_VALUE_W::new(self, 18) + } + #[doc = "Bit 23 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_rx_data_buf_to_en(&mut self) -> REG_RX_DATA_BUF_TO_EN_W { + REG_RX_DATA_BUF_TO_EN_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_out_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time_out_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIME_OUT_VALUE_SPEC; +impl crate::RegisterSpec for TIME_OUT_VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`time_out_value::R`](R) reader structure"] +impl crate::Readable for TIME_OUT_VALUE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`time_out_value::W`](W) writer structure"] +impl crate::Writable for TIME_OUT_VALUE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIME_OUT_VALUE to value 0x0041_0410"] +impl crate::Resettable for TIME_OUT_VALUE_SPEC { + const RESET_VALUE: Self::Ux = 0x0041_0410; +} diff --git a/esp32p4/src/i3c_mst/ver_id.rs b/esp32p4/src/i3c_mst/ver_id.rs new file mode 100644 index 0000000000..d7c9f6adbd --- /dev/null +++ b/esp32p4/src/i3c_mst/ver_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VER_ID` reader"] +pub type R = crate::R; +#[doc = "Register `VER_ID` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I3C_MST_VER_ID` reader - This field indicates the controller current release number that is read by an application."] +pub type REG_I3C_MST_VER_ID_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_VER_ID` writer - This field indicates the controller current release number that is read by an application."] +pub type REG_I3C_MST_VER_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This field indicates the controller current release number that is read by an application."] + #[inline(always)] + pub fn reg_i3c_mst_ver_id(&self) -> REG_I3C_MST_VER_ID_R { + REG_I3C_MST_VER_ID_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VER_ID") + .field( + "reg_i3c_mst_ver_id", + &format_args!("{}", self.reg_i3c_mst_ver_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This field indicates the controller current release number that is read by an application."] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_ver_id(&mut self) -> REG_I3C_MST_VER_ID_W { + REG_I3C_MST_VER_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VER_ID_SPEC; +impl crate::RegisterSpec for VER_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ver_id::R`](R) reader structure"] +impl crate::Readable for VER_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ver_id::W`](W) writer structure"] +impl crate::Writable for VER_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VER_ID to value 0x2023_0504"] +impl crate::Resettable for VER_ID_SPEC { + const RESET_VALUE: Self::Ux = 0x2023_0504; +} diff --git a/esp32p4/src/i3c_mst/ver_type.rs b/esp32p4/src/i3c_mst/ver_type.rs new file mode 100644 index 0000000000..bcb6cac151 --- /dev/null +++ b/esp32p4/src/i3c_mst/ver_type.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VER_TYPE` reader"] +pub type R = crate::R; +#[doc = "Register `VER_TYPE` writer"] +pub type W = crate::W; +#[doc = "Field `REG_I3C_MST_VER_TYPE` reader - This field indicates the controller current release type that is read by an application."] +pub type REG_I3C_MST_VER_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_I3C_MST_VER_TYPE` writer - This field indicates the controller current release type that is read by an application."] +pub type REG_I3C_MST_VER_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This field indicates the controller current release type that is read by an application."] + #[inline(always)] + pub fn reg_i3c_mst_ver_type(&self) -> REG_I3C_MST_VER_TYPE_R { + REG_I3C_MST_VER_TYPE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VER_TYPE") + .field( + "reg_i3c_mst_ver_type", + &format_args!("{}", self.reg_i3c_mst_ver_type().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This field indicates the controller current release type that is read by an application."] + #[inline(always)] + #[must_use] + pub fn reg_i3c_mst_ver_type(&mut self) -> REG_I3C_MST_VER_TYPE_W { + REG_I3C_MST_VER_TYPE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_type::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_type::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VER_TYPE_SPEC; +impl crate::RegisterSpec for VER_TYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ver_type::R`](R) reader structure"] +impl crate::Readable for VER_TYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ver_type::W`](W) writer structure"] +impl crate::Writable for VER_TYPE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VER_TYPE to value 0"] +impl crate::Resettable for VER_TYPE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem.rs b/esp32p4/src/i3c_mst_mem.rs new file mode 100644 index 0000000000..a75e9227b0 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem.rs @@ -0,0 +1,671 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + _reserved0: [u8; 0x08], + command_buf_port: COMMAND_BUF_PORT, + response_buf_port: RESPONSE_BUF_PORT, + rx_data_port: RX_DATA_PORT, + tx_data_port: TX_DATA_PORT, + ibi_status_buf: IBI_STATUS_BUF, + _reserved5: [u8; 0x24], + ibi_data_buf: IBI_DATA_BUF, + _reserved6: [u8; 0x7c], + dev_addr_table1_loc: DEV_ADDR_TABLE1_LOC, + dev_addr_table2_loc: DEV_ADDR_TABLE2_LOC, + dev_addr_table3_loc: DEV_ADDR_TABLE3_LOC, + dev_addr_table4_loc: DEV_ADDR_TABLE4_LOC, + dev_addr_table5_loc: DEV_ADDR_TABLE5_LOC, + dev_addr_table6_loc: DEV_ADDR_TABLE6_LOC, + dev_addr_table7_loc: DEV_ADDR_TABLE7_LOC, + dev_addr_table8_loc: DEV_ADDR_TABLE8_LOC, + dev_addr_table9_loc: DEV_ADDR_TABLE9_LOC, + dev_addr_table10_loc: DEV_ADDR_TABLE10_LOC, + dev_addr_table11_loc: DEV_ADDR_TABLE11_LOC, + dev_addr_table12_loc: DEV_ADDR_TABLE12_LOC, + _reserved18: [u8; 0x10], + dev_char_table1_loc1: DEV_CHAR_TABLE1_LOC1, + dev_char_table1_loc2: DEV_CHAR_TABLE1_LOC2, + dev_char_table1_loc3: DEV_CHAR_TABLE1_LOC3, + dev_char_table1_loc4: DEV_CHAR_TABLE1_LOC4, + dev_char_table2_loc1: DEV_CHAR_TABLE2_LOC1, + dev_char_table2_loc2: DEV_CHAR_TABLE2_LOC2, + dev_char_table2_loc3: DEV_CHAR_TABLE2_LOC3, + dev_char_table2_loc4: DEV_CHAR_TABLE2_LOC4, + dev_char_table3_loc1: DEV_CHAR_TABLE3_LOC1, + dev_char_table3_loc2: DEV_CHAR_TABLE3_LOC2, + dev_char_table3_loc3: DEV_CHAR_TABLE3_LOC3, + dev_char_table3_loc4: DEV_CHAR_TABLE3_LOC4, + dev_char_table4_loc1: DEV_CHAR_TABLE4_LOC1, + dev_char_table4_loc2: DEV_CHAR_TABLE4_LOC2, + dev_char_table4_loc3: DEV_CHAR_TABLE4_LOC3, + dev_char_table4_loc4: DEV_CHAR_TABLE4_LOC4, + dev_char_table5_loc1: DEV_CHAR_TABLE5_LOC1, + dev_char_table5_loc2: DEV_CHAR_TABLE5_LOC2, + dev_char_table5_loc3: DEV_CHAR_TABLE5_LOC3, + dev_char_table5_loc4: DEV_CHAR_TABLE5_LOC4, + dev_char_table6_loc1: DEV_CHAR_TABLE6_LOC1, + dev_char_table6_loc2: DEV_CHAR_TABLE6_LOC2, + dev_char_table6_loc3: DEV_CHAR_TABLE6_LOC3, + dev_char_table6_loc4: DEV_CHAR_TABLE6_LOC4, + dev_char_table7_loc1: DEV_CHAR_TABLE7_LOC1, + dev_char_table7_loc2: DEV_CHAR_TABLE7_LOC2, + dev_char_table7_loc3: DEV_CHAR_TABLE7_LOC3, + dev_char_table7_loc4: DEV_CHAR_TABLE7_LOC4, + dev_char_table8_loc1: DEV_CHAR_TABLE8_LOC1, + dev_char_table8_loc2: DEV_CHAR_TABLE8_LOC2, + dev_char_table8_loc3: DEV_CHAR_TABLE8_LOC3, + dev_char_table8_loc4: DEV_CHAR_TABLE8_LOC4, + dev_char_table9_loc1: DEV_CHAR_TABLE9_LOC1, + dev_char_table9_loc2: DEV_CHAR_TABLE9_LOC2, + dev_char_table9_loc3: DEV_CHAR_TABLE9_LOC3, + dev_char_table9_loc4: DEV_CHAR_TABLE9_LOC4, + dev_char_table10_loc1: DEV_CHAR_TABLE10_LOC1, + dev_char_table10_loc2: DEV_CHAR_TABLE10_LOC2, + dev_char_table10_loc3: DEV_CHAR_TABLE10_LOC3, + dev_char_table10_loc4: DEV_CHAR_TABLE10_LOC4, + dev_char_table11_loc1: DEV_CHAR_TABLE11_LOC1, + dev_char_table11_loc2: DEV_CHAR_TABLE11_LOC2, + dev_char_table11_loc3: DEV_CHAR_TABLE11_LOC3, + dev_char_table11_loc4: DEV_CHAR_TABLE11_LOC4, + dev_char_table12_loc1: DEV_CHAR_TABLE12_LOC1, + dev_char_table12_loc2: DEV_CHAR_TABLE12_LOC2, + dev_char_table12_loc3: DEV_CHAR_TABLE12_LOC3, + dev_char_table12_loc4: DEV_CHAR_TABLE12_LOC4, +} +impl RegisterBlock { + #[doc = "0x08 - NA"] + #[inline(always)] + pub const fn command_buf_port(&self) -> &COMMAND_BUF_PORT { + &self.command_buf_port + } + #[doc = "0x0c - NA"] + #[inline(always)] + pub const fn response_buf_port(&self) -> &RESPONSE_BUF_PORT { + &self.response_buf_port + } + #[doc = "0x10 - NA"] + #[inline(always)] + pub const fn rx_data_port(&self) -> &RX_DATA_PORT { + &self.rx_data_port + } + #[doc = "0x14 - NA"] + #[inline(always)] + pub const fn tx_data_port(&self) -> &TX_DATA_PORT { + &self.tx_data_port + } + #[doc = "0x18 - In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)"] + #[inline(always)] + pub const fn ibi_status_buf(&self) -> &IBI_STATUS_BUF { + &self.ibi_status_buf + } + #[doc = "0x40 - NA"] + #[inline(always)] + pub const fn ibi_data_buf(&self) -> &IBI_DATA_BUF { + &self.ibi_data_buf + } + #[doc = "0xc0 - NA"] + #[inline(always)] + pub const fn dev_addr_table1_loc(&self) -> &DEV_ADDR_TABLE1_LOC { + &self.dev_addr_table1_loc + } + #[doc = "0xc4 - NA"] + #[inline(always)] + pub const fn dev_addr_table2_loc(&self) -> &DEV_ADDR_TABLE2_LOC { + &self.dev_addr_table2_loc + } + #[doc = "0xc8 - NA"] + #[inline(always)] + pub const fn dev_addr_table3_loc(&self) -> &DEV_ADDR_TABLE3_LOC { + &self.dev_addr_table3_loc + } + #[doc = "0xcc - NA"] + #[inline(always)] + pub const fn dev_addr_table4_loc(&self) -> &DEV_ADDR_TABLE4_LOC { + &self.dev_addr_table4_loc + } + #[doc = "0xd0 - NA"] + #[inline(always)] + pub const fn dev_addr_table5_loc(&self) -> &DEV_ADDR_TABLE5_LOC { + &self.dev_addr_table5_loc + } + #[doc = "0xd4 - NA"] + #[inline(always)] + pub const fn dev_addr_table6_loc(&self) -> &DEV_ADDR_TABLE6_LOC { + &self.dev_addr_table6_loc + } + #[doc = "0xd8 - NA"] + #[inline(always)] + pub const fn dev_addr_table7_loc(&self) -> &DEV_ADDR_TABLE7_LOC { + &self.dev_addr_table7_loc + } + #[doc = "0xdc - NA"] + #[inline(always)] + pub const fn dev_addr_table8_loc(&self) -> &DEV_ADDR_TABLE8_LOC { + &self.dev_addr_table8_loc + } + #[doc = "0xe0 - NA"] + #[inline(always)] + pub const fn dev_addr_table9_loc(&self) -> &DEV_ADDR_TABLE9_LOC { + &self.dev_addr_table9_loc + } + #[doc = "0xe4 - NA"] + #[inline(always)] + pub const fn dev_addr_table10_loc(&self) -> &DEV_ADDR_TABLE10_LOC { + &self.dev_addr_table10_loc + } + #[doc = "0xe8 - NA"] + #[inline(always)] + pub const fn dev_addr_table11_loc(&self) -> &DEV_ADDR_TABLE11_LOC { + &self.dev_addr_table11_loc + } + #[doc = "0xec - NA"] + #[inline(always)] + pub const fn dev_addr_table12_loc(&self) -> &DEV_ADDR_TABLE12_LOC { + &self.dev_addr_table12_loc + } + #[doc = "0x100 - NA"] + #[inline(always)] + pub const fn dev_char_table1_loc1(&self) -> &DEV_CHAR_TABLE1_LOC1 { + &self.dev_char_table1_loc1 + } + #[doc = "0x104 - NA"] + #[inline(always)] + pub const fn dev_char_table1_loc2(&self) -> &DEV_CHAR_TABLE1_LOC2 { + &self.dev_char_table1_loc2 + } + #[doc = "0x108 - NA"] + #[inline(always)] + pub const fn dev_char_table1_loc3(&self) -> &DEV_CHAR_TABLE1_LOC3 { + &self.dev_char_table1_loc3 + } + #[doc = "0x10c - NA"] + #[inline(always)] + pub const fn dev_char_table1_loc4(&self) -> &DEV_CHAR_TABLE1_LOC4 { + &self.dev_char_table1_loc4 + } + #[doc = "0x110 - NA"] + #[inline(always)] + pub const fn dev_char_table2_loc1(&self) -> &DEV_CHAR_TABLE2_LOC1 { + &self.dev_char_table2_loc1 + } + #[doc = "0x114 - NA"] + #[inline(always)] + pub const fn dev_char_table2_loc2(&self) -> &DEV_CHAR_TABLE2_LOC2 { + &self.dev_char_table2_loc2 + } + #[doc = "0x118 - NA"] + #[inline(always)] + pub const fn dev_char_table2_loc3(&self) -> &DEV_CHAR_TABLE2_LOC3 { + &self.dev_char_table2_loc3 + } + #[doc = "0x11c - NA"] + #[inline(always)] + pub const fn dev_char_table2_loc4(&self) -> &DEV_CHAR_TABLE2_LOC4 { + &self.dev_char_table2_loc4 + } + #[doc = "0x120 - NA"] + #[inline(always)] + pub const fn dev_char_table3_loc1(&self) -> &DEV_CHAR_TABLE3_LOC1 { + &self.dev_char_table3_loc1 + } + #[doc = "0x124 - NA"] + #[inline(always)] + pub const fn dev_char_table3_loc2(&self) -> &DEV_CHAR_TABLE3_LOC2 { + &self.dev_char_table3_loc2 + } + #[doc = "0x128 - NA"] + #[inline(always)] + pub const fn dev_char_table3_loc3(&self) -> &DEV_CHAR_TABLE3_LOC3 { + &self.dev_char_table3_loc3 + } + #[doc = "0x12c - NA"] + #[inline(always)] + pub const fn dev_char_table3_loc4(&self) -> &DEV_CHAR_TABLE3_LOC4 { + &self.dev_char_table3_loc4 + } + #[doc = "0x130 - NA"] + #[inline(always)] + pub const fn dev_char_table4_loc1(&self) -> &DEV_CHAR_TABLE4_LOC1 { + &self.dev_char_table4_loc1 + } + #[doc = "0x134 - NA"] + #[inline(always)] + pub const fn dev_char_table4_loc2(&self) -> &DEV_CHAR_TABLE4_LOC2 { + &self.dev_char_table4_loc2 + } + #[doc = "0x138 - NA"] + #[inline(always)] + pub const fn dev_char_table4_loc3(&self) -> &DEV_CHAR_TABLE4_LOC3 { + &self.dev_char_table4_loc3 + } + #[doc = "0x13c - NA"] + #[inline(always)] + pub const fn dev_char_table4_loc4(&self) -> &DEV_CHAR_TABLE4_LOC4 { + &self.dev_char_table4_loc4 + } + #[doc = "0x140 - NA"] + #[inline(always)] + pub const fn dev_char_table5_loc1(&self) -> &DEV_CHAR_TABLE5_LOC1 { + &self.dev_char_table5_loc1 + } + #[doc = "0x144 - NA"] + #[inline(always)] + pub const fn dev_char_table5_loc2(&self) -> &DEV_CHAR_TABLE5_LOC2 { + &self.dev_char_table5_loc2 + } + #[doc = "0x148 - NA"] + #[inline(always)] + pub const fn dev_char_table5_loc3(&self) -> &DEV_CHAR_TABLE5_LOC3 { + &self.dev_char_table5_loc3 + } + #[doc = "0x14c - NA"] + #[inline(always)] + pub const fn dev_char_table5_loc4(&self) -> &DEV_CHAR_TABLE5_LOC4 { + &self.dev_char_table5_loc4 + } + #[doc = "0x150 - NA"] + #[inline(always)] + pub const fn dev_char_table6_loc1(&self) -> &DEV_CHAR_TABLE6_LOC1 { + &self.dev_char_table6_loc1 + } + #[doc = "0x154 - NA"] + #[inline(always)] + pub const fn dev_char_table6_loc2(&self) -> &DEV_CHAR_TABLE6_LOC2 { + &self.dev_char_table6_loc2 + } + #[doc = "0x158 - NA"] + #[inline(always)] + pub const fn dev_char_table6_loc3(&self) -> &DEV_CHAR_TABLE6_LOC3 { + &self.dev_char_table6_loc3 + } + #[doc = "0x15c - NA"] + #[inline(always)] + pub const fn dev_char_table6_loc4(&self) -> &DEV_CHAR_TABLE6_LOC4 { + &self.dev_char_table6_loc4 + } + #[doc = "0x160 - NA"] + #[inline(always)] + pub const fn dev_char_table7_loc1(&self) -> &DEV_CHAR_TABLE7_LOC1 { + &self.dev_char_table7_loc1 + } + #[doc = "0x164 - NA"] + #[inline(always)] + pub const fn dev_char_table7_loc2(&self) -> &DEV_CHAR_TABLE7_LOC2 { + &self.dev_char_table7_loc2 + } + #[doc = "0x168 - NA"] + #[inline(always)] + pub const fn dev_char_table7_loc3(&self) -> &DEV_CHAR_TABLE7_LOC3 { + &self.dev_char_table7_loc3 + } + #[doc = "0x16c - NA"] + #[inline(always)] + pub const fn dev_char_table7_loc4(&self) -> &DEV_CHAR_TABLE7_LOC4 { + &self.dev_char_table7_loc4 + } + #[doc = "0x170 - NA"] + #[inline(always)] + pub const fn dev_char_table8_loc1(&self) -> &DEV_CHAR_TABLE8_LOC1 { + &self.dev_char_table8_loc1 + } + #[doc = "0x174 - NA"] + #[inline(always)] + pub const fn dev_char_table8_loc2(&self) -> &DEV_CHAR_TABLE8_LOC2 { + &self.dev_char_table8_loc2 + } + #[doc = "0x178 - NA"] + #[inline(always)] + pub const fn dev_char_table8_loc3(&self) -> &DEV_CHAR_TABLE8_LOC3 { + &self.dev_char_table8_loc3 + } + #[doc = "0x17c - NA"] + #[inline(always)] + pub const fn dev_char_table8_loc4(&self) -> &DEV_CHAR_TABLE8_LOC4 { + &self.dev_char_table8_loc4 + } + #[doc = "0x180 - NA"] + #[inline(always)] + pub const fn dev_char_table9_loc1(&self) -> &DEV_CHAR_TABLE9_LOC1 { + &self.dev_char_table9_loc1 + } + #[doc = "0x184 - NA"] + #[inline(always)] + pub const fn dev_char_table9_loc2(&self) -> &DEV_CHAR_TABLE9_LOC2 { + &self.dev_char_table9_loc2 + } + #[doc = "0x188 - NA"] + #[inline(always)] + pub const fn dev_char_table9_loc3(&self) -> &DEV_CHAR_TABLE9_LOC3 { + &self.dev_char_table9_loc3 + } + #[doc = "0x18c - NA"] + #[inline(always)] + pub const fn dev_char_table9_loc4(&self) -> &DEV_CHAR_TABLE9_LOC4 { + &self.dev_char_table9_loc4 + } + #[doc = "0x190 - NA"] + #[inline(always)] + pub const fn dev_char_table10_loc1(&self) -> &DEV_CHAR_TABLE10_LOC1 { + &self.dev_char_table10_loc1 + } + #[doc = "0x194 - NA"] + #[inline(always)] + pub const fn dev_char_table10_loc2(&self) -> &DEV_CHAR_TABLE10_LOC2 { + &self.dev_char_table10_loc2 + } + #[doc = "0x198 - NA"] + #[inline(always)] + pub const fn dev_char_table10_loc3(&self) -> &DEV_CHAR_TABLE10_LOC3 { + &self.dev_char_table10_loc3 + } + #[doc = "0x19c - NA"] + #[inline(always)] + pub const fn dev_char_table10_loc4(&self) -> &DEV_CHAR_TABLE10_LOC4 { + &self.dev_char_table10_loc4 + } + #[doc = "0x1a0 - NA"] + #[inline(always)] + pub const fn dev_char_table11_loc1(&self) -> &DEV_CHAR_TABLE11_LOC1 { + &self.dev_char_table11_loc1 + } + #[doc = "0x1a4 - NA"] + #[inline(always)] + pub const fn dev_char_table11_loc2(&self) -> &DEV_CHAR_TABLE11_LOC2 { + &self.dev_char_table11_loc2 + } + #[doc = "0x1a8 - NA"] + #[inline(always)] + pub const fn dev_char_table11_loc3(&self) -> &DEV_CHAR_TABLE11_LOC3 { + &self.dev_char_table11_loc3 + } + #[doc = "0x1ac - NA"] + #[inline(always)] + pub const fn dev_char_table11_loc4(&self) -> &DEV_CHAR_TABLE11_LOC4 { + &self.dev_char_table11_loc4 + } + #[doc = "0x1b0 - NA"] + #[inline(always)] + pub const fn dev_char_table12_loc1(&self) -> &DEV_CHAR_TABLE12_LOC1 { + &self.dev_char_table12_loc1 + } + #[doc = "0x1b4 - NA"] + #[inline(always)] + pub const fn dev_char_table12_loc2(&self) -> &DEV_CHAR_TABLE12_LOC2 { + &self.dev_char_table12_loc2 + } + #[doc = "0x1b8 - NA"] + #[inline(always)] + pub const fn dev_char_table12_loc3(&self) -> &DEV_CHAR_TABLE12_LOC3 { + &self.dev_char_table12_loc3 + } + #[doc = "0x1bc - NA"] + #[inline(always)] + pub const fn dev_char_table12_loc4(&self) -> &DEV_CHAR_TABLE12_LOC4 { + &self.dev_char_table12_loc4 + } +} +#[doc = "COMMAND_BUF_PORT (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`command_buf_port::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`command_buf_port::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@command_buf_port`] module"] +pub type COMMAND_BUF_PORT = crate::Reg; +#[doc = "NA"] +pub mod command_buf_port; +#[doc = "RESPONSE_BUF_PORT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`response_buf_port::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@response_buf_port`] module"] +pub type RESPONSE_BUF_PORT = crate::Reg; +#[doc = "NA"] +pub mod response_buf_port; +#[doc = "RX_DATA_PORT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_data_port::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_data_port`] module"] +pub type RX_DATA_PORT = crate::Reg; +#[doc = "NA"] +pub mod rx_data_port; +#[doc = "TX_DATA_PORT (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_data_port::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_data_port::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data_port`] module"] +pub type TX_DATA_PORT = crate::Reg; +#[doc = "NA"] +pub mod tx_data_port; +#[doc = "IBI_STATUS_BUF (r) register accessor: In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_status_buf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibi_status_buf`] module"] +pub type IBI_STATUS_BUF = crate::Reg; +#[doc = "In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)"] +pub mod ibi_status_buf; +#[doc = "IBI_DATA_BUF (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_data_buf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibi_data_buf`] module"] +pub type IBI_DATA_BUF = crate::Reg; +#[doc = "NA"] +pub mod ibi_data_buf; +#[doc = "DEV_ADDR_TABLE1_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table1_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table1_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table1_loc`] module"] +pub type DEV_ADDR_TABLE1_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table1_loc; +#[doc = "DEV_ADDR_TABLE2_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table2_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table2_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table2_loc`] module"] +pub type DEV_ADDR_TABLE2_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table2_loc; +#[doc = "DEV_ADDR_TABLE3_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table3_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table3_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table3_loc`] module"] +pub type DEV_ADDR_TABLE3_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table3_loc; +#[doc = "DEV_ADDR_TABLE4_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table4_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table4_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table4_loc`] module"] +pub type DEV_ADDR_TABLE4_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table4_loc; +#[doc = "DEV_ADDR_TABLE5_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table5_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table5_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table5_loc`] module"] +pub type DEV_ADDR_TABLE5_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table5_loc; +#[doc = "DEV_ADDR_TABLE6_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table6_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table6_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table6_loc`] module"] +pub type DEV_ADDR_TABLE6_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table6_loc; +#[doc = "DEV_ADDR_TABLE7_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table7_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table7_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table7_loc`] module"] +pub type DEV_ADDR_TABLE7_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table7_loc; +#[doc = "DEV_ADDR_TABLE8_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table8_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table8_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table8_loc`] module"] +pub type DEV_ADDR_TABLE8_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table8_loc; +#[doc = "DEV_ADDR_TABLE9_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table9_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table9_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table9_loc`] module"] +pub type DEV_ADDR_TABLE9_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table9_loc; +#[doc = "DEV_ADDR_TABLE10_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table10_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table10_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table10_loc`] module"] +pub type DEV_ADDR_TABLE10_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table10_loc; +#[doc = "DEV_ADDR_TABLE11_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table11_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table11_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table11_loc`] module"] +pub type DEV_ADDR_TABLE11_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table11_loc; +#[doc = "DEV_ADDR_TABLE12_LOC (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table12_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table12_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_addr_table12_loc`] module"] +pub type DEV_ADDR_TABLE12_LOC = crate::Reg; +#[doc = "NA"] +pub mod dev_addr_table12_loc; +#[doc = "DEV_CHAR_TABLE1_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table1_loc1`] module"] +pub type DEV_CHAR_TABLE1_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table1_loc1; +#[doc = "DEV_CHAR_TABLE1_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table1_loc2`] module"] +pub type DEV_CHAR_TABLE1_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table1_loc2; +#[doc = "DEV_CHAR_TABLE1_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table1_loc3`] module"] +pub type DEV_CHAR_TABLE1_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table1_loc3; +#[doc = "DEV_CHAR_TABLE1_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table1_loc4`] module"] +pub type DEV_CHAR_TABLE1_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table1_loc4; +#[doc = "DEV_CHAR_TABLE2_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table2_loc1`] module"] +pub type DEV_CHAR_TABLE2_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table2_loc1; +#[doc = "DEV_CHAR_TABLE2_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table2_loc2`] module"] +pub type DEV_CHAR_TABLE2_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table2_loc2; +#[doc = "DEV_CHAR_TABLE2_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table2_loc3`] module"] +pub type DEV_CHAR_TABLE2_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table2_loc3; +#[doc = "DEV_CHAR_TABLE2_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table2_loc4`] module"] +pub type DEV_CHAR_TABLE2_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table2_loc4; +#[doc = "DEV_CHAR_TABLE3_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table3_loc1`] module"] +pub type DEV_CHAR_TABLE3_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table3_loc1; +#[doc = "DEV_CHAR_TABLE3_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table3_loc2`] module"] +pub type DEV_CHAR_TABLE3_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table3_loc2; +#[doc = "DEV_CHAR_TABLE3_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table3_loc3`] module"] +pub type DEV_CHAR_TABLE3_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table3_loc3; +#[doc = "DEV_CHAR_TABLE3_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table3_loc4`] module"] +pub type DEV_CHAR_TABLE3_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table3_loc4; +#[doc = "DEV_CHAR_TABLE4_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table4_loc1`] module"] +pub type DEV_CHAR_TABLE4_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table4_loc1; +#[doc = "DEV_CHAR_TABLE4_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table4_loc2`] module"] +pub type DEV_CHAR_TABLE4_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table4_loc2; +#[doc = "DEV_CHAR_TABLE4_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table4_loc3`] module"] +pub type DEV_CHAR_TABLE4_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table4_loc3; +#[doc = "DEV_CHAR_TABLE4_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table4_loc4`] module"] +pub type DEV_CHAR_TABLE4_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table4_loc4; +#[doc = "DEV_CHAR_TABLE5_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table5_loc1`] module"] +pub type DEV_CHAR_TABLE5_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table5_loc1; +#[doc = "DEV_CHAR_TABLE5_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table5_loc2`] module"] +pub type DEV_CHAR_TABLE5_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table5_loc2; +#[doc = "DEV_CHAR_TABLE5_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table5_loc3`] module"] +pub type DEV_CHAR_TABLE5_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table5_loc3; +#[doc = "DEV_CHAR_TABLE5_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table5_loc4`] module"] +pub type DEV_CHAR_TABLE5_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table5_loc4; +#[doc = "DEV_CHAR_TABLE6_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table6_loc1`] module"] +pub type DEV_CHAR_TABLE6_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table6_loc1; +#[doc = "DEV_CHAR_TABLE6_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table6_loc2`] module"] +pub type DEV_CHAR_TABLE6_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table6_loc2; +#[doc = "DEV_CHAR_TABLE6_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table6_loc3`] module"] +pub type DEV_CHAR_TABLE6_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table6_loc3; +#[doc = "DEV_CHAR_TABLE6_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table6_loc4`] module"] +pub type DEV_CHAR_TABLE6_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table6_loc4; +#[doc = "DEV_CHAR_TABLE7_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table7_loc1`] module"] +pub type DEV_CHAR_TABLE7_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table7_loc1; +#[doc = "DEV_CHAR_TABLE7_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table7_loc2`] module"] +pub type DEV_CHAR_TABLE7_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table7_loc2; +#[doc = "DEV_CHAR_TABLE7_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table7_loc3`] module"] +pub type DEV_CHAR_TABLE7_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table7_loc3; +#[doc = "DEV_CHAR_TABLE7_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table7_loc4`] module"] +pub type DEV_CHAR_TABLE7_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table7_loc4; +#[doc = "DEV_CHAR_TABLE8_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table8_loc1`] module"] +pub type DEV_CHAR_TABLE8_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table8_loc1; +#[doc = "DEV_CHAR_TABLE8_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table8_loc2`] module"] +pub type DEV_CHAR_TABLE8_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table8_loc2; +#[doc = "DEV_CHAR_TABLE8_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table8_loc3`] module"] +pub type DEV_CHAR_TABLE8_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table8_loc3; +#[doc = "DEV_CHAR_TABLE8_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table8_loc4`] module"] +pub type DEV_CHAR_TABLE8_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table8_loc4; +#[doc = "DEV_CHAR_TABLE9_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table9_loc1`] module"] +pub type DEV_CHAR_TABLE9_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table9_loc1; +#[doc = "DEV_CHAR_TABLE9_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table9_loc2`] module"] +pub type DEV_CHAR_TABLE9_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table9_loc2; +#[doc = "DEV_CHAR_TABLE9_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table9_loc3`] module"] +pub type DEV_CHAR_TABLE9_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table9_loc3; +#[doc = "DEV_CHAR_TABLE9_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table9_loc4`] module"] +pub type DEV_CHAR_TABLE9_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table9_loc4; +#[doc = "DEV_CHAR_TABLE10_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table10_loc1`] module"] +pub type DEV_CHAR_TABLE10_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table10_loc1; +#[doc = "DEV_CHAR_TABLE10_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table10_loc2`] module"] +pub type DEV_CHAR_TABLE10_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table10_loc2; +#[doc = "DEV_CHAR_TABLE10_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table10_loc3`] module"] +pub type DEV_CHAR_TABLE10_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table10_loc3; +#[doc = "DEV_CHAR_TABLE10_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table10_loc4`] module"] +pub type DEV_CHAR_TABLE10_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table10_loc4; +#[doc = "DEV_CHAR_TABLE11_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table11_loc1`] module"] +pub type DEV_CHAR_TABLE11_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table11_loc1; +#[doc = "DEV_CHAR_TABLE11_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table11_loc2`] module"] +pub type DEV_CHAR_TABLE11_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table11_loc2; +#[doc = "DEV_CHAR_TABLE11_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table11_loc3`] module"] +pub type DEV_CHAR_TABLE11_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table11_loc3; +#[doc = "DEV_CHAR_TABLE11_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table11_loc4`] module"] +pub type DEV_CHAR_TABLE11_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table11_loc4; +#[doc = "DEV_CHAR_TABLE12_LOC1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table12_loc1`] module"] +pub type DEV_CHAR_TABLE12_LOC1 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table12_loc1; +#[doc = "DEV_CHAR_TABLE12_LOC2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table12_loc2`] module"] +pub type DEV_CHAR_TABLE12_LOC2 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table12_loc2; +#[doc = "DEV_CHAR_TABLE12_LOC3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table12_loc3`] module"] +pub type DEV_CHAR_TABLE12_LOC3 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table12_loc3; +#[doc = "DEV_CHAR_TABLE12_LOC4 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dev_char_table12_loc4`] module"] +pub type DEV_CHAR_TABLE12_LOC4 = crate::Reg; +#[doc = "NA"] +pub mod dev_char_table12_loc4; diff --git a/esp32p4/src/i3c_mst_mem/command_buf_port.rs b/esp32p4/src/i3c_mst_mem/command_buf_port.rs new file mode 100644 index 0000000000..4b3f351cfa --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/command_buf_port.rs @@ -0,0 +1,66 @@ +#[doc = "Register `COMMAND_BUF_PORT` reader"] +pub type R = crate::R; +#[doc = "Register `COMMAND_BUF_PORT` writer"] +pub type W = crate::W; +#[doc = "Field `REG_COMMAND` reader - Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus."] +pub type REG_COMMAND_R = crate::FieldReader; +#[doc = "Field `REG_COMMAND` writer - Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus."] +pub type REG_COMMAND_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus."] + #[inline(always)] + pub fn reg_command(&self) -> REG_COMMAND_R { + REG_COMMAND_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMMAND_BUF_PORT") + .field( + "reg_command", + &format_args!("{}", self.reg_command().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus."] + #[inline(always)] + #[must_use] + pub fn reg_command(&mut self) -> REG_COMMAND_W { + REG_COMMAND_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`command_buf_port::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`command_buf_port::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMMAND_BUF_PORT_SPEC; +impl crate::RegisterSpec for COMMAND_BUF_PORT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`command_buf_port::R`](R) reader structure"] +impl crate::Readable for COMMAND_BUF_PORT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`command_buf_port::W`](W) writer structure"] +impl crate::Writable for COMMAND_BUF_PORT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMMAND_BUF_PORT to value 0"] +impl crate::Resettable for COMMAND_BUF_PORT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table10_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table10_loc.rs new file mode 100644 index 0000000000..e62fa179e3 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table10_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE10_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE10_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV10_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV10_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV10_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV10_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV10_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV10_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV10_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV10_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV10_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV10_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV10_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV10_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV10_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV10_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV10_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV10_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev10_static_addr(&self) -> REG_DAT_DEV10_STATIC_ADDR_R { + REG_DAT_DEV10_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev10_dynamic_addr(&self) -> REG_DAT_DEV10_DYNAMIC_ADDR_R { + REG_DAT_DEV10_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev10_nack_retry_cnt(&self) -> REG_DAT_DEV10_NACK_RETRY_CNT_R { + REG_DAT_DEV10_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev10_i2c(&self) -> REG_DAT_DEV10_I2C_R { + REG_DAT_DEV10_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE10_LOC") + .field( + "reg_dat_dev10_static_addr", + &format_args!("{}", self.reg_dat_dev10_static_addr().bits()), + ) + .field( + "reg_dat_dev10_dynamic_addr", + &format_args!("{}", self.reg_dat_dev10_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev10_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev10_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev10_i2c", + &format_args!("{}", self.reg_dat_dev10_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev10_static_addr( + &mut self, + ) -> REG_DAT_DEV10_STATIC_ADDR_W { + REG_DAT_DEV10_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev10_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV10_DYNAMIC_ADDR_W { + REG_DAT_DEV10_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev10_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV10_NACK_RETRY_CNT_W { + REG_DAT_DEV10_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev10_i2c(&mut self) -> REG_DAT_DEV10_I2C_W { + REG_DAT_DEV10_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table10_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table10_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE10_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE10_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table10_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE10_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table10_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE10_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE10_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE10_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table11_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table11_loc.rs new file mode 100644 index 0000000000..b743569353 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table11_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE11_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE11_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV11_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV11_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV11_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV11_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV11_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV11_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV11_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV11_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV11_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV11_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV11_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV11_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV11_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV11_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV11_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV11_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev11_static_addr(&self) -> REG_DAT_DEV11_STATIC_ADDR_R { + REG_DAT_DEV11_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev11_dynamic_addr(&self) -> REG_DAT_DEV11_DYNAMIC_ADDR_R { + REG_DAT_DEV11_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev11_nack_retry_cnt(&self) -> REG_DAT_DEV11_NACK_RETRY_CNT_R { + REG_DAT_DEV11_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev11_i2c(&self) -> REG_DAT_DEV11_I2C_R { + REG_DAT_DEV11_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE11_LOC") + .field( + "reg_dat_dev11_static_addr", + &format_args!("{}", self.reg_dat_dev11_static_addr().bits()), + ) + .field( + "reg_dat_dev11_dynamic_addr", + &format_args!("{}", self.reg_dat_dev11_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev11_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev11_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev11_i2c", + &format_args!("{}", self.reg_dat_dev11_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev11_static_addr( + &mut self, + ) -> REG_DAT_DEV11_STATIC_ADDR_W { + REG_DAT_DEV11_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev11_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV11_DYNAMIC_ADDR_W { + REG_DAT_DEV11_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev11_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV11_NACK_RETRY_CNT_W { + REG_DAT_DEV11_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev11_i2c(&mut self) -> REG_DAT_DEV11_I2C_W { + REG_DAT_DEV11_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table11_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table11_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE11_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE11_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table11_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE11_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table11_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE11_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE11_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE11_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table12_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table12_loc.rs new file mode 100644 index 0000000000..f83baad43f --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table12_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE12_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE12_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV12_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV12_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV12_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV12_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV12_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV12_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV12_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV12_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV12_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV12_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV12_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV12_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV12_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV12_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV12_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV12_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev12_static_addr(&self) -> REG_DAT_DEV12_STATIC_ADDR_R { + REG_DAT_DEV12_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev12_dynamic_addr(&self) -> REG_DAT_DEV12_DYNAMIC_ADDR_R { + REG_DAT_DEV12_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev12_nack_retry_cnt(&self) -> REG_DAT_DEV12_NACK_RETRY_CNT_R { + REG_DAT_DEV12_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev12_i2c(&self) -> REG_DAT_DEV12_I2C_R { + REG_DAT_DEV12_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE12_LOC") + .field( + "reg_dat_dev12_static_addr", + &format_args!("{}", self.reg_dat_dev12_static_addr().bits()), + ) + .field( + "reg_dat_dev12_dynamic_addr", + &format_args!("{}", self.reg_dat_dev12_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev12_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev12_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev12_i2c", + &format_args!("{}", self.reg_dat_dev12_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev12_static_addr( + &mut self, + ) -> REG_DAT_DEV12_STATIC_ADDR_W { + REG_DAT_DEV12_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev12_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV12_DYNAMIC_ADDR_W { + REG_DAT_DEV12_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev12_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV12_NACK_RETRY_CNT_W { + REG_DAT_DEV12_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev12_i2c(&mut self) -> REG_DAT_DEV12_I2C_W { + REG_DAT_DEV12_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table12_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table12_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE12_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE12_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table12_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE12_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table12_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE12_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE12_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE12_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table1_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table1_loc.rs new file mode 100644 index 0000000000..8fda3d3a98 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table1_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE1_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE1_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV1_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV1_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV1_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV1_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV1_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV1_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV1_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV1_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV1_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV1_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV1_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV1_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV1_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV1_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV1_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV1_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev1_static_addr(&self) -> REG_DAT_DEV1_STATIC_ADDR_R { + REG_DAT_DEV1_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev1_dynamic_addr(&self) -> REG_DAT_DEV1_DYNAMIC_ADDR_R { + REG_DAT_DEV1_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev1_nack_retry_cnt(&self) -> REG_DAT_DEV1_NACK_RETRY_CNT_R { + REG_DAT_DEV1_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev1_i2c(&self) -> REG_DAT_DEV1_I2C_R { + REG_DAT_DEV1_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE1_LOC") + .field( + "reg_dat_dev1_static_addr", + &format_args!("{}", self.reg_dat_dev1_static_addr().bits()), + ) + .field( + "reg_dat_dev1_dynamic_addr", + &format_args!("{}", self.reg_dat_dev1_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev1_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev1_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev1_i2c", + &format_args!("{}", self.reg_dat_dev1_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev1_static_addr( + &mut self, + ) -> REG_DAT_DEV1_STATIC_ADDR_W { + REG_DAT_DEV1_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev1_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV1_DYNAMIC_ADDR_W { + REG_DAT_DEV1_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev1_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV1_NACK_RETRY_CNT_W { + REG_DAT_DEV1_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev1_i2c(&mut self) -> REG_DAT_DEV1_I2C_W { + REG_DAT_DEV1_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table1_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table1_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE1_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE1_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table1_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE1_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table1_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE1_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE1_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE1_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table2_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table2_loc.rs new file mode 100644 index 0000000000..bff1f485a8 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table2_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE2_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE2_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV2_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV2_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV2_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV2_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV2_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV2_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV2_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV2_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV2_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV2_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV2_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV2_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV2_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV2_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV2_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV2_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev2_static_addr(&self) -> REG_DAT_DEV2_STATIC_ADDR_R { + REG_DAT_DEV2_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev2_dynamic_addr(&self) -> REG_DAT_DEV2_DYNAMIC_ADDR_R { + REG_DAT_DEV2_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev2_nack_retry_cnt(&self) -> REG_DAT_DEV2_NACK_RETRY_CNT_R { + REG_DAT_DEV2_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev2_i2c(&self) -> REG_DAT_DEV2_I2C_R { + REG_DAT_DEV2_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE2_LOC") + .field( + "reg_dat_dev2_static_addr", + &format_args!("{}", self.reg_dat_dev2_static_addr().bits()), + ) + .field( + "reg_dat_dev2_dynamic_addr", + &format_args!("{}", self.reg_dat_dev2_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev2_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev2_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev2_i2c", + &format_args!("{}", self.reg_dat_dev2_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev2_static_addr( + &mut self, + ) -> REG_DAT_DEV2_STATIC_ADDR_W { + REG_DAT_DEV2_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev2_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV2_DYNAMIC_ADDR_W { + REG_DAT_DEV2_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev2_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV2_NACK_RETRY_CNT_W { + REG_DAT_DEV2_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev2_i2c(&mut self) -> REG_DAT_DEV2_I2C_W { + REG_DAT_DEV2_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table2_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table2_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE2_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE2_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table2_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE2_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table2_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE2_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE2_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE2_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table3_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table3_loc.rs new file mode 100644 index 0000000000..8f6bb73f19 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table3_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE3_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE3_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV3_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV3_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV3_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV3_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV3_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV3_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV3_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV3_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV3_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV3_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV3_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV3_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV3_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV3_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV3_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV3_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev3_static_addr(&self) -> REG_DAT_DEV3_STATIC_ADDR_R { + REG_DAT_DEV3_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev3_dynamic_addr(&self) -> REG_DAT_DEV3_DYNAMIC_ADDR_R { + REG_DAT_DEV3_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev3_nack_retry_cnt(&self) -> REG_DAT_DEV3_NACK_RETRY_CNT_R { + REG_DAT_DEV3_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev3_i2c(&self) -> REG_DAT_DEV3_I2C_R { + REG_DAT_DEV3_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE3_LOC") + .field( + "reg_dat_dev3_static_addr", + &format_args!("{}", self.reg_dat_dev3_static_addr().bits()), + ) + .field( + "reg_dat_dev3_dynamic_addr", + &format_args!("{}", self.reg_dat_dev3_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev3_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev3_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev3_i2c", + &format_args!("{}", self.reg_dat_dev3_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev3_static_addr( + &mut self, + ) -> REG_DAT_DEV3_STATIC_ADDR_W { + REG_DAT_DEV3_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev3_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV3_DYNAMIC_ADDR_W { + REG_DAT_DEV3_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev3_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV3_NACK_RETRY_CNT_W { + REG_DAT_DEV3_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev3_i2c(&mut self) -> REG_DAT_DEV3_I2C_W { + REG_DAT_DEV3_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table3_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table3_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE3_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE3_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table3_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE3_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table3_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE3_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE3_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE3_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table4_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table4_loc.rs new file mode 100644 index 0000000000..41bd7c23b2 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table4_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE4_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE4_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV4_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV4_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV4_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV4_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV4_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV4_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV4_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV4_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV4_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV4_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV4_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV4_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV4_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV4_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV4_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV4_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev4_static_addr(&self) -> REG_DAT_DEV4_STATIC_ADDR_R { + REG_DAT_DEV4_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev4_dynamic_addr(&self) -> REG_DAT_DEV4_DYNAMIC_ADDR_R { + REG_DAT_DEV4_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev4_nack_retry_cnt(&self) -> REG_DAT_DEV4_NACK_RETRY_CNT_R { + REG_DAT_DEV4_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev4_i2c(&self) -> REG_DAT_DEV4_I2C_R { + REG_DAT_DEV4_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE4_LOC") + .field( + "reg_dat_dev4_static_addr", + &format_args!("{}", self.reg_dat_dev4_static_addr().bits()), + ) + .field( + "reg_dat_dev4_dynamic_addr", + &format_args!("{}", self.reg_dat_dev4_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev4_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev4_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev4_i2c", + &format_args!("{}", self.reg_dat_dev4_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev4_static_addr( + &mut self, + ) -> REG_DAT_DEV4_STATIC_ADDR_W { + REG_DAT_DEV4_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev4_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV4_DYNAMIC_ADDR_W { + REG_DAT_DEV4_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev4_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV4_NACK_RETRY_CNT_W { + REG_DAT_DEV4_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev4_i2c(&mut self) -> REG_DAT_DEV4_I2C_W { + REG_DAT_DEV4_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table4_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table4_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE4_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE4_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table4_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE4_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table4_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE4_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE4_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE4_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table5_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table5_loc.rs new file mode 100644 index 0000000000..cb2c8d49a9 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table5_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE5_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE5_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV5_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV5_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV5_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV5_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV5_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV5_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV5_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV5_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV5_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV5_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV5_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV5_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV5_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV5_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV5_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV5_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev5_static_addr(&self) -> REG_DAT_DEV5_STATIC_ADDR_R { + REG_DAT_DEV5_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev5_dynamic_addr(&self) -> REG_DAT_DEV5_DYNAMIC_ADDR_R { + REG_DAT_DEV5_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev5_nack_retry_cnt(&self) -> REG_DAT_DEV5_NACK_RETRY_CNT_R { + REG_DAT_DEV5_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev5_i2c(&self) -> REG_DAT_DEV5_I2C_R { + REG_DAT_DEV5_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE5_LOC") + .field( + "reg_dat_dev5_static_addr", + &format_args!("{}", self.reg_dat_dev5_static_addr().bits()), + ) + .field( + "reg_dat_dev5_dynamic_addr", + &format_args!("{}", self.reg_dat_dev5_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev5_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev5_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev5_i2c", + &format_args!("{}", self.reg_dat_dev5_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev5_static_addr( + &mut self, + ) -> REG_DAT_DEV5_STATIC_ADDR_W { + REG_DAT_DEV5_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev5_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV5_DYNAMIC_ADDR_W { + REG_DAT_DEV5_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev5_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV5_NACK_RETRY_CNT_W { + REG_DAT_DEV5_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev5_i2c(&mut self) -> REG_DAT_DEV5_I2C_W { + REG_DAT_DEV5_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table5_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table5_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE5_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE5_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table5_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE5_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table5_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE5_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE5_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE5_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table6_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table6_loc.rs new file mode 100644 index 0000000000..d6b2e5ce73 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table6_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE6_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE6_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV6_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV6_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV6_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV6_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV6_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV6_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV6_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV6_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV6_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV6_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV6_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV6_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV6_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV6_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV6_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV6_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev6_static_addr(&self) -> REG_DAT_DEV6_STATIC_ADDR_R { + REG_DAT_DEV6_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev6_dynamic_addr(&self) -> REG_DAT_DEV6_DYNAMIC_ADDR_R { + REG_DAT_DEV6_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev6_nack_retry_cnt(&self) -> REG_DAT_DEV6_NACK_RETRY_CNT_R { + REG_DAT_DEV6_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev6_i2c(&self) -> REG_DAT_DEV6_I2C_R { + REG_DAT_DEV6_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE6_LOC") + .field( + "reg_dat_dev6_static_addr", + &format_args!("{}", self.reg_dat_dev6_static_addr().bits()), + ) + .field( + "reg_dat_dev6_dynamic_addr", + &format_args!("{}", self.reg_dat_dev6_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev6_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev6_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev6_i2c", + &format_args!("{}", self.reg_dat_dev6_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev6_static_addr( + &mut self, + ) -> REG_DAT_DEV6_STATIC_ADDR_W { + REG_DAT_DEV6_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev6_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV6_DYNAMIC_ADDR_W { + REG_DAT_DEV6_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev6_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV6_NACK_RETRY_CNT_W { + REG_DAT_DEV6_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev6_i2c(&mut self) -> REG_DAT_DEV6_I2C_W { + REG_DAT_DEV6_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table6_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table6_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE6_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE6_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table6_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE6_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table6_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE6_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE6_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE6_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table7_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table7_loc.rs new file mode 100644 index 0000000000..7ab0b1e175 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table7_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE7_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE7_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV7_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV7_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV7_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV7_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV7_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV7_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV7_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV7_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV7_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV7_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV7_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV7_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV7_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV7_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV7_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV7_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev7_static_addr(&self) -> REG_DAT_DEV7_STATIC_ADDR_R { + REG_DAT_DEV7_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev7_dynamic_addr(&self) -> REG_DAT_DEV7_DYNAMIC_ADDR_R { + REG_DAT_DEV7_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev7_nack_retry_cnt(&self) -> REG_DAT_DEV7_NACK_RETRY_CNT_R { + REG_DAT_DEV7_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev7_i2c(&self) -> REG_DAT_DEV7_I2C_R { + REG_DAT_DEV7_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE7_LOC") + .field( + "reg_dat_dev7_static_addr", + &format_args!("{}", self.reg_dat_dev7_static_addr().bits()), + ) + .field( + "reg_dat_dev7_dynamic_addr", + &format_args!("{}", self.reg_dat_dev7_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev7_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev7_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev7_i2c", + &format_args!("{}", self.reg_dat_dev7_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev7_static_addr( + &mut self, + ) -> REG_DAT_DEV7_STATIC_ADDR_W { + REG_DAT_DEV7_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev7_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV7_DYNAMIC_ADDR_W { + REG_DAT_DEV7_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev7_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV7_NACK_RETRY_CNT_W { + REG_DAT_DEV7_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev7_i2c(&mut self) -> REG_DAT_DEV7_I2C_W { + REG_DAT_DEV7_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table7_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table7_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE7_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE7_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table7_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE7_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table7_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE7_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE7_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE7_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table8_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table8_loc.rs new file mode 100644 index 0000000000..657e4e73a3 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table8_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE8_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE8_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV8_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV8_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV8_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV8_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV8_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV8_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV8_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV8_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV8_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV8_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV8_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV8_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV8_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV8_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV8_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV8_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev8_static_addr(&self) -> REG_DAT_DEV8_STATIC_ADDR_R { + REG_DAT_DEV8_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev8_dynamic_addr(&self) -> REG_DAT_DEV8_DYNAMIC_ADDR_R { + REG_DAT_DEV8_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev8_nack_retry_cnt(&self) -> REG_DAT_DEV8_NACK_RETRY_CNT_R { + REG_DAT_DEV8_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev8_i2c(&self) -> REG_DAT_DEV8_I2C_R { + REG_DAT_DEV8_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE8_LOC") + .field( + "reg_dat_dev8_static_addr", + &format_args!("{}", self.reg_dat_dev8_static_addr().bits()), + ) + .field( + "reg_dat_dev8_dynamic_addr", + &format_args!("{}", self.reg_dat_dev8_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev8_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev8_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev8_i2c", + &format_args!("{}", self.reg_dat_dev8_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev8_static_addr( + &mut self, + ) -> REG_DAT_DEV8_STATIC_ADDR_W { + REG_DAT_DEV8_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev8_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV8_DYNAMIC_ADDR_W { + REG_DAT_DEV8_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev8_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV8_NACK_RETRY_CNT_W { + REG_DAT_DEV8_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev8_i2c(&mut self) -> REG_DAT_DEV8_I2C_W { + REG_DAT_DEV8_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table8_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table8_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE8_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE8_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table8_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE8_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table8_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE8_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE8_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE8_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table9_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table9_loc.rs new file mode 100644 index 0000000000..26acb1c33a --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_addr_table9_loc.rs @@ -0,0 +1,129 @@ +#[doc = "Register `DEV_ADDR_TABLE9_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_ADDR_TABLE9_LOC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_DAT_DEV9_STATIC_ADDR` reader - NA"] +pub type REG_DAT_DEV9_STATIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV9_STATIC_ADDR` writer - NA"] +pub type REG_DAT_DEV9_STATIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REG_DAT_DEV9_DYNAMIC_ADDR` reader - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV9_DYNAMIC_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV9_DYNAMIC_ADDR` writer - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] +pub type REG_DAT_DEV9_DYNAMIC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REG_DAT_DEV9_NACK_RETRY_CNT` reader - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV9_NACK_RETRY_CNT_R = crate::FieldReader; +#[doc = "Field `REG_DAT_DEV9_NACK_RETRY_CNT` writer - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] +pub type REG_DAT_DEV9_NACK_RETRY_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_DAT_DEV9_I2C` reader - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV9_I2C_R = crate::BitReader; +#[doc = "Field `REG_DAT_DEV9_I2C` writer - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] +pub type REG_DAT_DEV9_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + pub fn reg_dat_dev9_static_addr(&self) -> REG_DAT_DEV9_STATIC_ADDR_R { + REG_DAT_DEV9_STATIC_ADDR_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + pub fn reg_dat_dev9_dynamic_addr(&self) -> REG_DAT_DEV9_DYNAMIC_ADDR_R { + REG_DAT_DEV9_DYNAMIC_ADDR_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + pub fn reg_dat_dev9_nack_retry_cnt(&self) -> REG_DAT_DEV9_NACK_RETRY_CNT_R { + REG_DAT_DEV9_NACK_RETRY_CNT_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + pub fn reg_dat_dev9_i2c(&self) -> REG_DAT_DEV9_I2C_R { + REG_DAT_DEV9_I2C_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_ADDR_TABLE9_LOC") + .field( + "reg_dat_dev9_static_addr", + &format_args!("{}", self.reg_dat_dev9_static_addr().bits()), + ) + .field( + "reg_dat_dev9_dynamic_addr", + &format_args!("{}", self.reg_dat_dev9_dynamic_addr().bits()), + ) + .field( + "reg_dat_dev9_nack_retry_cnt", + &format_args!("{}", self.reg_dat_dev9_nack_retry_cnt().bits()), + ) + .field( + "reg_dat_dev9_i2c", + &format_args!("{}", self.reg_dat_dev9_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - NA"] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev9_static_addr( + &mut self, + ) -> REG_DAT_DEV9_STATIC_ADDR_W { + REG_DAT_DEV9_STATIC_ADDR_W::new(self, 0) + } + #[doc = "Bits 16:23 - Device Dynamic Address with parity, The MSB,bit\\[23\\], should be programmed with parity of dynamic address."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev9_dynamic_addr( + &mut self, + ) -> REG_DAT_DEV9_DYNAMIC_ADDR_W { + REG_DAT_DEV9_DYNAMIC_ADDR_W::new(self, 16) + } + #[doc = "Bits 29:30 - This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev9_nack_retry_cnt( + &mut self, + ) -> REG_DAT_DEV9_NACK_RETRY_CNT_W { + REG_DAT_DEV9_NACK_RETRY_CNT_W::new(self, 29) + } + #[doc = "Bit 31 - Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device."] + #[inline(always)] + #[must_use] + pub fn reg_dat_dev9_i2c(&mut self) -> REG_DAT_DEV9_I2C_W { + REG_DAT_DEV9_I2C_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_addr_table9_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dev_addr_table9_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_ADDR_TABLE9_LOC_SPEC; +impl crate::RegisterSpec for DEV_ADDR_TABLE9_LOC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_addr_table9_loc::R`](R) reader structure"] +impl crate::Readable for DEV_ADDR_TABLE9_LOC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_addr_table9_loc::W`](W) writer structure"] +impl crate::Writable for DEV_ADDR_TABLE9_LOC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEV_ADDR_TABLE9_LOC to value 0"] +impl crate::Resettable for DEV_ADDR_TABLE9_LOC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc1.rs new file mode 100644 index 0000000000..17219684e4 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE10_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV10_LOC1` reader - NA"] +pub type DCT_DEV10_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev10_loc1(&self) -> DCT_DEV10_LOC1_R { + DCT_DEV10_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE10_LOC1") + .field( + "dct_dev10_loc1", + &format_args!("{}", self.dct_dev10_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE10_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE10_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table10_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE10_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE10_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE10_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc2.rs new file mode 100644 index 0000000000..ea7c81fda8 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE10_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV10_LOC2` reader - NA"] +pub type DCT_DEV10_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev10_loc2(&self) -> DCT_DEV10_LOC2_R { + DCT_DEV10_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE10_LOC2") + .field( + "dct_dev10_loc2", + &format_args!("{}", self.dct_dev10_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE10_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE10_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table10_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE10_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE10_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE10_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc3.rs new file mode 100644 index 0000000000..7a18e03727 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE10_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV10_LOC3` reader - NA"] +pub type DCT_DEV10_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev10_loc3(&self) -> DCT_DEV10_LOC3_R { + DCT_DEV10_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE10_LOC3") + .field( + "dct_dev10_loc3", + &format_args!("{}", self.dct_dev10_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE10_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE10_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table10_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE10_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE10_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE10_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc4.rs new file mode 100644 index 0000000000..eafbb1583b --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE10_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV10_LOC4` reader - NA"] +pub type DCT_DEV10_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev10_loc4(&self) -> DCT_DEV10_LOC4_R { + DCT_DEV10_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE10_LOC4") + .field( + "dct_dev10_loc4", + &format_args!("{}", self.dct_dev10_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE10_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE10_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table10_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE10_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE10_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE10_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc1.rs new file mode 100644 index 0000000000..39a32403ac --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE11_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV11_LOC1` reader - NA"] +pub type DCT_DEV11_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev11_loc1(&self) -> DCT_DEV11_LOC1_R { + DCT_DEV11_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE11_LOC1") + .field( + "dct_dev11_loc1", + &format_args!("{}", self.dct_dev11_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE11_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE11_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table11_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE11_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE11_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE11_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc2.rs new file mode 100644 index 0000000000..735df4e696 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE11_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV11_LOC2` reader - NA"] +pub type DCT_DEV11_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev11_loc2(&self) -> DCT_DEV11_LOC2_R { + DCT_DEV11_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE11_LOC2") + .field( + "dct_dev11_loc2", + &format_args!("{}", self.dct_dev11_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE11_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE11_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table11_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE11_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE11_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE11_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc3.rs new file mode 100644 index 0000000000..7acc5555f3 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE11_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV11_LOC3` reader - NA"] +pub type DCT_DEV11_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev11_loc3(&self) -> DCT_DEV11_LOC3_R { + DCT_DEV11_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE11_LOC3") + .field( + "dct_dev11_loc3", + &format_args!("{}", self.dct_dev11_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE11_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE11_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table11_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE11_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE11_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE11_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc4.rs new file mode 100644 index 0000000000..97958940b5 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE11_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV11_LOC4` reader - NA"] +pub type DCT_DEV11_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev11_loc4(&self) -> DCT_DEV11_LOC4_R { + DCT_DEV11_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE11_LOC4") + .field( + "dct_dev11_loc4", + &format_args!("{}", self.dct_dev11_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE11_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE11_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table11_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE11_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE11_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE11_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc1.rs new file mode 100644 index 0000000000..8e1737b9b8 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE12_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV12_LOC1` reader - NA"] +pub type DCT_DEV12_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev12_loc1(&self) -> DCT_DEV12_LOC1_R { + DCT_DEV12_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE12_LOC1") + .field( + "dct_dev12_loc1", + &format_args!("{}", self.dct_dev12_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE12_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE12_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table12_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE12_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE12_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE12_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc2.rs new file mode 100644 index 0000000000..f0ef86ef94 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE12_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV12_LOC2` reader - NA"] +pub type DCT_DEV12_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev12_loc2(&self) -> DCT_DEV12_LOC2_R { + DCT_DEV12_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE12_LOC2") + .field( + "dct_dev12_loc2", + &format_args!("{}", self.dct_dev12_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE12_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE12_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table12_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE12_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE12_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE12_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc3.rs new file mode 100644 index 0000000000..6a41916698 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE12_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV12_LOC3` reader - NA"] +pub type DCT_DEV12_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev12_loc3(&self) -> DCT_DEV12_LOC3_R { + DCT_DEV12_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE12_LOC3") + .field( + "dct_dev12_loc3", + &format_args!("{}", self.dct_dev12_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE12_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE12_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table12_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE12_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE12_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE12_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc4.rs new file mode 100644 index 0000000000..32718be90a --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE12_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV12_LOC4` reader - NA"] +pub type DCT_DEV12_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev12_loc4(&self) -> DCT_DEV12_LOC4_R { + DCT_DEV12_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE12_LOC4") + .field( + "dct_dev12_loc4", + &format_args!("{}", self.dct_dev12_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE12_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE12_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table12_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE12_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE12_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE12_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc1.rs new file mode 100644 index 0000000000..5cb240a357 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE1_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV1_LOC1` reader - NA"] +pub type DCT_DEV1_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev1_loc1(&self) -> DCT_DEV1_LOC1_R { + DCT_DEV1_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE1_LOC1") + .field( + "dct_dev1_loc1", + &format_args!("{}", self.dct_dev1_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE1_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE1_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table1_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE1_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE1_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE1_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc2.rs new file mode 100644 index 0000000000..0822131a1b --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE1_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV1_LOC2` reader - NA"] +pub type DCT_DEV1_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev1_loc2(&self) -> DCT_DEV1_LOC2_R { + DCT_DEV1_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE1_LOC2") + .field( + "dct_dev1_loc2", + &format_args!("{}", self.dct_dev1_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE1_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE1_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table1_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE1_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE1_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE1_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc3.rs new file mode 100644 index 0000000000..214900e614 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE1_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV1_LOC3` reader - NA"] +pub type DCT_DEV1_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev1_loc3(&self) -> DCT_DEV1_LOC3_R { + DCT_DEV1_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE1_LOC3") + .field( + "dct_dev1_loc3", + &format_args!("{}", self.dct_dev1_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE1_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE1_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table1_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE1_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE1_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE1_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc4.rs new file mode 100644 index 0000000000..80d5eb02ea --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE1_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV1_LOC4` reader - NA"] +pub type DCT_DEV1_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev1_loc4(&self) -> DCT_DEV1_LOC4_R { + DCT_DEV1_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE1_LOC4") + .field( + "dct_dev1_loc4", + &format_args!("{}", self.dct_dev1_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE1_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE1_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table1_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE1_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE1_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE1_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc1.rs new file mode 100644 index 0000000000..18b009e336 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE2_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV2_LOC1` reader - NA"] +pub type DCT_DEV2_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev2_loc1(&self) -> DCT_DEV2_LOC1_R { + DCT_DEV2_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE2_LOC1") + .field( + "dct_dev2_loc1", + &format_args!("{}", self.dct_dev2_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE2_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE2_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table2_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE2_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE2_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE2_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc2.rs new file mode 100644 index 0000000000..fb6a09f60b --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE2_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV2_LOC2` reader - NA"] +pub type DCT_DEV2_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev2_loc2(&self) -> DCT_DEV2_LOC2_R { + DCT_DEV2_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE2_LOC2") + .field( + "dct_dev2_loc2", + &format_args!("{}", self.dct_dev2_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE2_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE2_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table2_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE2_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE2_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE2_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc3.rs new file mode 100644 index 0000000000..2275d6c5f2 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE2_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV2_LOC3` reader - NA"] +pub type DCT_DEV2_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev2_loc3(&self) -> DCT_DEV2_LOC3_R { + DCT_DEV2_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE2_LOC3") + .field( + "dct_dev2_loc3", + &format_args!("{}", self.dct_dev2_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE2_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE2_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table2_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE2_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE2_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE2_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc4.rs new file mode 100644 index 0000000000..4150609212 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE2_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV2_LOC4` reader - NA"] +pub type DCT_DEV2_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev2_loc4(&self) -> DCT_DEV2_LOC4_R { + DCT_DEV2_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE2_LOC4") + .field( + "dct_dev2_loc4", + &format_args!("{}", self.dct_dev2_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE2_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE2_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table2_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE2_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE2_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE2_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc1.rs new file mode 100644 index 0000000000..20c9aa4bb3 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE3_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV3_LOC1` reader - NA"] +pub type DCT_DEV3_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev3_loc1(&self) -> DCT_DEV3_LOC1_R { + DCT_DEV3_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE3_LOC1") + .field( + "dct_dev3_loc1", + &format_args!("{}", self.dct_dev3_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE3_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE3_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table3_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE3_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE3_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE3_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc2.rs new file mode 100644 index 0000000000..ac8fb80566 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE3_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV3_LOC2` reader - NA"] +pub type DCT_DEV3_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev3_loc2(&self) -> DCT_DEV3_LOC2_R { + DCT_DEV3_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE3_LOC2") + .field( + "dct_dev3_loc2", + &format_args!("{}", self.dct_dev3_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE3_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE3_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table3_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE3_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE3_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE3_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc3.rs new file mode 100644 index 0000000000..432be614e3 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE3_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV3_LOC3` reader - NA"] +pub type DCT_DEV3_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev3_loc3(&self) -> DCT_DEV3_LOC3_R { + DCT_DEV3_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE3_LOC3") + .field( + "dct_dev3_loc3", + &format_args!("{}", self.dct_dev3_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE3_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE3_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table3_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE3_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE3_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE3_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc4.rs new file mode 100644 index 0000000000..26b6c6fbd3 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE3_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV3_LOC4` reader - NA"] +pub type DCT_DEV3_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev3_loc4(&self) -> DCT_DEV3_LOC4_R { + DCT_DEV3_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE3_LOC4") + .field( + "dct_dev3_loc4", + &format_args!("{}", self.dct_dev3_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE3_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE3_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table3_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE3_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE3_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE3_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc1.rs new file mode 100644 index 0000000000..38114142d9 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE4_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV4_LOC1` reader - NA"] +pub type DCT_DEV4_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev4_loc1(&self) -> DCT_DEV4_LOC1_R { + DCT_DEV4_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE4_LOC1") + .field( + "dct_dev4_loc1", + &format_args!("{}", self.dct_dev4_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE4_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE4_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table4_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE4_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE4_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE4_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc2.rs new file mode 100644 index 0000000000..3be07c9f82 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE4_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV4_LOC2` reader - NA"] +pub type DCT_DEV4_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev4_loc2(&self) -> DCT_DEV4_LOC2_R { + DCT_DEV4_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE4_LOC2") + .field( + "dct_dev4_loc2", + &format_args!("{}", self.dct_dev4_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE4_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE4_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table4_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE4_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE4_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE4_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc3.rs new file mode 100644 index 0000000000..56f81baea1 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE4_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV4_LOC3` reader - NA"] +pub type DCT_DEV4_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev4_loc3(&self) -> DCT_DEV4_LOC3_R { + DCT_DEV4_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE4_LOC3") + .field( + "dct_dev4_loc3", + &format_args!("{}", self.dct_dev4_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE4_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE4_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table4_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE4_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE4_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE4_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc4.rs new file mode 100644 index 0000000000..fb16cf9033 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE4_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV4_LOC4` reader - NA"] +pub type DCT_DEV4_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev4_loc4(&self) -> DCT_DEV4_LOC4_R { + DCT_DEV4_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE4_LOC4") + .field( + "dct_dev4_loc4", + &format_args!("{}", self.dct_dev4_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE4_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE4_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table4_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE4_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE4_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE4_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc1.rs new file mode 100644 index 0000000000..288ca22d1b --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE5_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV5_LOC1` reader - NA"] +pub type DCT_DEV5_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev5_loc1(&self) -> DCT_DEV5_LOC1_R { + DCT_DEV5_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE5_LOC1") + .field( + "dct_dev5_loc1", + &format_args!("{}", self.dct_dev5_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE5_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE5_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table5_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE5_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE5_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE5_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc2.rs new file mode 100644 index 0000000000..3d07d2ec7e --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE5_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV5_LOC2` reader - NA"] +pub type DCT_DEV5_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev5_loc2(&self) -> DCT_DEV5_LOC2_R { + DCT_DEV5_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE5_LOC2") + .field( + "dct_dev5_loc2", + &format_args!("{}", self.dct_dev5_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE5_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE5_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table5_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE5_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE5_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE5_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc3.rs new file mode 100644 index 0000000000..c274b09aac --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE5_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV5_LOC3` reader - NA"] +pub type DCT_DEV5_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev5_loc3(&self) -> DCT_DEV5_LOC3_R { + DCT_DEV5_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE5_LOC3") + .field( + "dct_dev5_loc3", + &format_args!("{}", self.dct_dev5_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE5_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE5_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table5_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE5_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE5_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE5_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc4.rs new file mode 100644 index 0000000000..c4285d356a --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE5_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV5_LOC4` reader - NA"] +pub type DCT_DEV5_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev5_loc4(&self) -> DCT_DEV5_LOC4_R { + DCT_DEV5_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE5_LOC4") + .field( + "dct_dev5_loc4", + &format_args!("{}", self.dct_dev5_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE5_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE5_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table5_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE5_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE5_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE5_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc1.rs new file mode 100644 index 0000000000..3926e6dacb --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE6_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV6_LOC1` reader - NA"] +pub type DCT_DEV6_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev6_loc1(&self) -> DCT_DEV6_LOC1_R { + DCT_DEV6_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE6_LOC1") + .field( + "dct_dev6_loc1", + &format_args!("{}", self.dct_dev6_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE6_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE6_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table6_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE6_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE6_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE6_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc2.rs new file mode 100644 index 0000000000..2b0cc00587 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE6_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV6_LOC2` reader - NA"] +pub type DCT_DEV6_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev6_loc2(&self) -> DCT_DEV6_LOC2_R { + DCT_DEV6_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE6_LOC2") + .field( + "dct_dev6_loc2", + &format_args!("{}", self.dct_dev6_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE6_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE6_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table6_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE6_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE6_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE6_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc3.rs new file mode 100644 index 0000000000..474014e9a2 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE6_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV6_LOC3` reader - NA"] +pub type DCT_DEV6_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev6_loc3(&self) -> DCT_DEV6_LOC3_R { + DCT_DEV6_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE6_LOC3") + .field( + "dct_dev6_loc3", + &format_args!("{}", self.dct_dev6_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE6_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE6_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table6_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE6_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE6_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE6_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc4.rs new file mode 100644 index 0000000000..104655ba6b --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE6_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV6_LOC4` reader - NA"] +pub type DCT_DEV6_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev6_loc4(&self) -> DCT_DEV6_LOC4_R { + DCT_DEV6_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE6_LOC4") + .field( + "dct_dev6_loc4", + &format_args!("{}", self.dct_dev6_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE6_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE6_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table6_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE6_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE6_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE6_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc1.rs new file mode 100644 index 0000000000..3d43bcf6cc --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE7_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV7_LOC1` reader - NA"] +pub type DCT_DEV7_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev7_loc1(&self) -> DCT_DEV7_LOC1_R { + DCT_DEV7_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE7_LOC1") + .field( + "dct_dev7_loc1", + &format_args!("{}", self.dct_dev7_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE7_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE7_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table7_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE7_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE7_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE7_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc2.rs new file mode 100644 index 0000000000..4b14d4b4ce --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE7_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV7_LOC2` reader - NA"] +pub type DCT_DEV7_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev7_loc2(&self) -> DCT_DEV7_LOC2_R { + DCT_DEV7_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE7_LOC2") + .field( + "dct_dev7_loc2", + &format_args!("{}", self.dct_dev7_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE7_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE7_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table7_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE7_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE7_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE7_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc3.rs new file mode 100644 index 0000000000..769c03de68 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE7_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV7_LOC3` reader - NA"] +pub type DCT_DEV7_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev7_loc3(&self) -> DCT_DEV7_LOC3_R { + DCT_DEV7_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE7_LOC3") + .field( + "dct_dev7_loc3", + &format_args!("{}", self.dct_dev7_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE7_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE7_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table7_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE7_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE7_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE7_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc4.rs new file mode 100644 index 0000000000..99ba004211 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE7_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV7_LOC4` reader - NA"] +pub type DCT_DEV7_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev7_loc4(&self) -> DCT_DEV7_LOC4_R { + DCT_DEV7_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE7_LOC4") + .field( + "dct_dev7_loc4", + &format_args!("{}", self.dct_dev7_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE7_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE7_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table7_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE7_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE7_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE7_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc1.rs new file mode 100644 index 0000000000..2149665873 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE8_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV8_LOC1` reader - NA"] +pub type DCT_DEV8_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev8_loc1(&self) -> DCT_DEV8_LOC1_R { + DCT_DEV8_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE8_LOC1") + .field( + "dct_dev8_loc1", + &format_args!("{}", self.dct_dev8_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE8_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE8_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table8_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE8_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE8_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE8_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc2.rs new file mode 100644 index 0000000000..00c5008cd8 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE8_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV8_LOC2` reader - NA"] +pub type DCT_DEV8_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev8_loc2(&self) -> DCT_DEV8_LOC2_R { + DCT_DEV8_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE8_LOC2") + .field( + "dct_dev8_loc2", + &format_args!("{}", self.dct_dev8_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE8_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE8_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table8_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE8_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE8_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE8_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc3.rs new file mode 100644 index 0000000000..e85011a0c4 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE8_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV8_LOC3` reader - NA"] +pub type DCT_DEV8_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev8_loc3(&self) -> DCT_DEV8_LOC3_R { + DCT_DEV8_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE8_LOC3") + .field( + "dct_dev8_loc3", + &format_args!("{}", self.dct_dev8_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE8_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE8_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table8_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE8_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE8_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE8_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc4.rs new file mode 100644 index 0000000000..24a84858a5 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE8_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV8_LOC4` reader - NA"] +pub type DCT_DEV8_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev8_loc4(&self) -> DCT_DEV8_LOC4_R { + DCT_DEV8_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE8_LOC4") + .field( + "dct_dev8_loc4", + &format_args!("{}", self.dct_dev8_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE8_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE8_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table8_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE8_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE8_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE8_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc1.rs new file mode 100644 index 0000000000..a459a90d92 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE9_LOC1` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV9_LOC1` reader - NA"] +pub type DCT_DEV9_LOC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev9_loc1(&self) -> DCT_DEV9_LOC1_R { + DCT_DEV9_LOC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE9_LOC1") + .field( + "dct_dev9_loc1", + &format_args!("{}", self.dct_dev9_loc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE9_LOC1_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE9_LOC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table9_loc1::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE9_LOC1_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE9_LOC1 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE9_LOC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc2.rs new file mode 100644 index 0000000000..dbe46eda53 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE9_LOC2` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV9_LOC2` reader - NA"] +pub type DCT_DEV9_LOC2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev9_loc2(&self) -> DCT_DEV9_LOC2_R { + DCT_DEV9_LOC2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE9_LOC2") + .field( + "dct_dev9_loc2", + &format_args!("{}", self.dct_dev9_loc2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE9_LOC2_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE9_LOC2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table9_loc2::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE9_LOC2_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE9_LOC2 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE9_LOC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc3.rs new file mode 100644 index 0000000000..39bcbc20ac --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE9_LOC3` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV9_LOC3` reader - NA"] +pub type DCT_DEV9_LOC3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev9_loc3(&self) -> DCT_DEV9_LOC3_R { + DCT_DEV9_LOC3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE9_LOC3") + .field( + "dct_dev9_loc3", + &format_args!("{}", self.dct_dev9_loc3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE9_LOC3_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE9_LOC3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table9_loc3::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE9_LOC3_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE9_LOC3 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE9_LOC3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc4.rs new file mode 100644 index 0000000000..a6b56a3c06 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DEV_CHAR_TABLE9_LOC4` reader"] +pub type R = crate::R; +#[doc = "Field `DCT_DEV9_LOC4` reader - NA"] +pub type DCT_DEV9_LOC4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn dct_dev9_loc4(&self) -> DCT_DEV9_LOC4_R { + DCT_DEV9_LOC4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEV_CHAR_TABLE9_LOC4") + .field( + "dct_dev9_loc4", + &format_args!("{}", self.dct_dev9_loc4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_CHAR_TABLE9_LOC4_SPEC; +impl crate::RegisterSpec for DEV_CHAR_TABLE9_LOC4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_char_table9_loc4::R`](R) reader structure"] +impl crate::Readable for DEV_CHAR_TABLE9_LOC4_SPEC {} +#[doc = "`reset()` method sets DEV_CHAR_TABLE9_LOC4 to value 0"] +impl crate::Resettable for DEV_CHAR_TABLE9_LOC4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/ibi_data_buf.rs b/esp32p4/src/i3c_mst_mem/ibi_data_buf.rs new file mode 100644 index 0000000000..b4f7999cbb --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/ibi_data_buf.rs @@ -0,0 +1,36 @@ +#[doc = "Register `IBI_DATA_BUF` reader"] +pub type R = crate::R; +#[doc = "Field `IBI_DATA` reader - NA"] +pub type IBI_DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn ibi_data(&self) -> IBI_DATA_R { + IBI_DATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IBI_DATA_BUF") + .field("ibi_data", &format_args!("{}", self.ibi_data().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_data_buf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IBI_DATA_BUF_SPEC; +impl crate::RegisterSpec for IBI_DATA_BUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ibi_data_buf::R`](R) reader structure"] +impl crate::Readable for IBI_DATA_BUF_SPEC {} +#[doc = "`reset()` method sets IBI_DATA_BUF to value 0"] +impl crate::Resettable for IBI_DATA_BUF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/ibi_status_buf.rs b/esp32p4/src/i3c_mst_mem/ibi_status_buf.rs new file mode 100644 index 0000000000..91cf607acd --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/ibi_status_buf.rs @@ -0,0 +1,55 @@ +#[doc = "Register `IBI_STATUS_BUF` reader"] +pub type R = crate::R; +#[doc = "Field `DATA_LENGTH` reader - This field represents the length of data received along with IBI, in bytes."] +pub type DATA_LENGTH_R = crate::FieldReader; +#[doc = "Field `IBI_ID` reader - IBI Identifier. The byte received after START which includes the address the R/W bit: Device address and R/W bit in case of Slave Interrupt or Master Request."] +pub type IBI_ID_R = crate::FieldReader; +#[doc = "Field `IBI_STS` reader - IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI Data is always packed in4-byte aligned and put to the IBI Buffer. This register When read from, reads the data from the IBI buffer. IBI Status register when read from, returns the data from the IBI Buffer and indicates how the controller responded to incoming IBI(SIR, MR and HJ)."] +pub type IBI_STS_R = crate::BitReader; +impl R { + #[doc = "Bits 0:7 - This field represents the length of data received along with IBI, in bytes."] + #[inline(always)] + pub fn data_length(&self) -> DATA_LENGTH_R { + DATA_LENGTH_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - IBI Identifier. The byte received after START which includes the address the R/W bit: Device address and R/W bit in case of Slave Interrupt or Master Request."] + #[inline(always)] + pub fn ibi_id(&self) -> IBI_ID_R { + IBI_ID_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 28 - IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI Data is always packed in4-byte aligned and put to the IBI Buffer. This register When read from, reads the data from the IBI buffer. IBI Status register when read from, returns the data from the IBI Buffer and indicates how the controller responded to incoming IBI(SIR, MR and HJ)."] + #[inline(always)] + pub fn ibi_sts(&self) -> IBI_STS_R { + IBI_STS_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IBI_STATUS_BUF") + .field( + "data_length", + &format_args!("{}", self.data_length().bits()), + ) + .field("ibi_id", &format_args!("{}", self.ibi_id().bits())) + .field("ibi_sts", &format_args!("{}", self.ibi_sts().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_status_buf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IBI_STATUS_BUF_SPEC; +impl crate::RegisterSpec for IBI_STATUS_BUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ibi_status_buf::R`](R) reader structure"] +impl crate::Readable for IBI_STATUS_BUF_SPEC {} +#[doc = "`reset()` method sets IBI_STATUS_BUF to value 0"] +impl crate::Resettable for IBI_STATUS_BUF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/response_buf_port.rs b/esp32p4/src/i3c_mst_mem/response_buf_port.rs new file mode 100644 index 0000000000..ee836b463b --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/response_buf_port.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RESPONSE_BUF_PORT` reader"] +pub type R = crate::R; +#[doc = "Field `RESPONSE` reader - The Response Buffer can be read through this register. The response status for each Command is written into the Response Buffer by the controller if ROC (Response On Completion) bit is set or if transfer error has occurred. The response buffer can be read through this register."] +pub type RESPONSE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The Response Buffer can be read through this register. The response status for each Command is written into the Response Buffer by the controller if ROC (Response On Completion) bit is set or if transfer error has occurred. The response buffer can be read through this register."] + #[inline(always)] + pub fn response(&self) -> RESPONSE_R { + RESPONSE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESPONSE_BUF_PORT") + .field("response", &format_args!("{}", self.response().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`response_buf_port::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESPONSE_BUF_PORT_SPEC; +impl crate::RegisterSpec for RESPONSE_BUF_PORT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`response_buf_port::R`](R) reader structure"] +impl crate::Readable for RESPONSE_BUF_PORT_SPEC {} +#[doc = "`reset()` method sets RESPONSE_BUF_PORT to value 0"] +impl crate::Resettable for RESPONSE_BUF_PORT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/rx_data_port.rs b/esp32p4/src/i3c_mst_mem/rx_data_port.rs new file mode 100644 index 0000000000..28e184b26d --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/rx_data_port.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RX_DATA_PORT` reader"] +pub type R = crate::R; +#[doc = "Field `RX_DATA_PORT` reader - Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor."] +pub type RX_DATA_PORT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor."] + #[inline(always)] + pub fn rx_data_port(&self) -> RX_DATA_PORT_R { + RX_DATA_PORT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_DATA_PORT") + .field( + "rx_data_port", + &format_args!("{}", self.rx_data_port().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_data_port::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_DATA_PORT_SPEC; +impl crate::RegisterSpec for RX_DATA_PORT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_data_port::R`](R) reader structure"] +impl crate::Readable for RX_DATA_PORT_SPEC {} +#[doc = "`reset()` method sets RX_DATA_PORT to value 0"] +impl crate::Resettable for RX_DATA_PORT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_mst_mem/tx_data_port.rs b/esp32p4/src/i3c_mst_mem/tx_data_port.rs new file mode 100644 index 0000000000..71673f0e69 --- /dev/null +++ b/esp32p4/src/i3c_mst_mem/tx_data_port.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TX_DATA_PORT` reader"] +pub type R = crate::R; +#[doc = "Register `TX_DATA_PORT` writer"] +pub type W = crate::W; +#[doc = "Field `REG_TX_DATA_PORT` reader - Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor."] +pub type REG_TX_DATA_PORT_R = crate::FieldReader; +#[doc = "Field `REG_TX_DATA_PORT` writer - Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor."] +pub type REG_TX_DATA_PORT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor."] + #[inline(always)] + pub fn reg_tx_data_port(&self) -> REG_TX_DATA_PORT_R { + REG_TX_DATA_PORT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_DATA_PORT") + .field( + "reg_tx_data_port", + &format_args!("{}", self.reg_tx_data_port().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor."] + #[inline(always)] + #[must_use] + pub fn reg_tx_data_port(&mut self) -> REG_TX_DATA_PORT_W { + REG_TX_DATA_PORT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_data_port::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_data_port::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_DATA_PORT_SPEC; +impl crate::RegisterSpec for TX_DATA_PORT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_data_port::R`](R) reader structure"] +impl crate::Readable for TX_DATA_PORT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_data_port::W`](W) writer structure"] +impl crate::Writable for TX_DATA_PORT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_DATA_PORT to value 0"] +impl crate::Resettable for TX_DATA_PORT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_slv.rs b/esp32p4/src/i3c_slv.rs new file mode 100644 index 0000000000..0996dca499 --- /dev/null +++ b/esp32p4/src/i3c_slv.rs @@ -0,0 +1,173 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + _reserved0: [u8; 0x04], + config: CONFIG, + status: STATUS, + ctrl: CTRL, + intset: INTSET, + intclr: INTCLR, + intmasked: INTMASKED, + _reserved6: [u8; 0x10], + datactrl: DATACTRL, + wdatab: WDATAB, + wdatabe: WDATABE, + _reserved9: [u8; 0x08], + rdarab: RDARAB, + _reserved10: [u8; 0x04], + rdatah: RDATAH, + _reserved11: [u8; 0x10], + capabilities2: CAPABILITIES2, + capabilities: CAPABILITIES, + _reserved13: [u8; 0x08], + idpartno: IDPARTNO, + idext: IDEXT, + vendorid: VENDORID, +} +impl RegisterBlock { + #[doc = "0x04 - NA"] + #[inline(always)] + pub const fn config(&self) -> &CONFIG { + &self.config + } + #[doc = "0x08 - NA"] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0x0c - NA"] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0x10 - INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor)"] + #[inline(always)] + pub const fn intset(&self) -> &INTSET { + &self.intset + } + #[doc = "0x14 - NA"] + #[inline(always)] + pub const fn intclr(&self) -> &INTCLR { + &self.intclr + } + #[doc = "0x18 - NA"] + #[inline(always)] + pub const fn intmasked(&self) -> &INTMASKED { + &self.intmasked + } + #[doc = "0x2c - NA"] + #[inline(always)] + pub const fn datactrl(&self) -> &DATACTRL { + &self.datactrl + } + #[doc = "0x30 - NA"] + #[inline(always)] + pub const fn wdatab(&self) -> &WDATAB { + &self.wdatab + } + #[doc = "0x34 - NA"] + #[inline(always)] + pub const fn wdatabe(&self) -> &WDATABE { + &self.wdatabe + } + #[doc = "0x40 - Read Byte Data (from-bus) register"] + #[inline(always)] + pub const fn rdarab(&self) -> &RDARAB { + &self.rdarab + } + #[doc = "0x48 - Read Half-word Data (from-bus) register"] + #[inline(always)] + pub const fn rdatah(&self) -> &RDATAH { + &self.rdatah + } + #[doc = "0x5c - NA"] + #[inline(always)] + pub const fn capabilities2(&self) -> &CAPABILITIES2 { + &self.capabilities2 + } + #[doc = "0x60 - NA"] + #[inline(always)] + pub const fn capabilities(&self) -> &CAPABILITIES { + &self.capabilities + } + #[doc = "0x6c - NA"] + #[inline(always)] + pub const fn idpartno(&self) -> &IDPARTNO { + &self.idpartno + } + #[doc = "0x70 - NA"] + #[inline(always)] + pub const fn idext(&self) -> &IDEXT { + &self.idext + } + #[doc = "0x74 - NA"] + #[inline(always)] + pub const fn vendorid(&self) -> &VENDORID { + &self.vendorid + } +} +#[doc = "CONFIG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] +pub type CONFIG = crate::Reg; +#[doc = "NA"] +pub mod config; +#[doc = "STATUS (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +pub type STATUS = crate::Reg; +#[doc = "NA"] +pub mod status; +#[doc = "CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +pub type CTRL = crate::Reg; +#[doc = "NA"] +pub mod ctrl; +#[doc = "INTSET (rw) register accessor: INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intset`] module"] +pub type INTSET = crate::Reg; +#[doc = "INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor)"] +pub mod intset; +#[doc = "INTCLR (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intclr`] module"] +pub type INTCLR = crate::Reg; +#[doc = "NA"] +pub mod intclr; +#[doc = "INTMASKED (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intmasked::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intmasked`] module"] +pub type INTMASKED = crate::Reg; +#[doc = "NA"] +pub mod intmasked; +#[doc = "DATACTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datactrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datactrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datactrl`] module"] +pub type DATACTRL = crate::Reg; +#[doc = "NA"] +pub mod datactrl; +#[doc = "WDATAB (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdatab::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdatab`] module"] +pub type WDATAB = crate::Reg; +#[doc = "NA"] +pub mod wdatab; +#[doc = "WDATABE (w) register accessor: NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdatabe::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdatabe`] module"] +pub type WDATABE = crate::Reg; +#[doc = "NA"] +pub mod wdatabe; +#[doc = "RDARAB (r) register accessor: Read Byte Data (from-bus) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdarab::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdarab`] module"] +pub type RDARAB = crate::Reg; +#[doc = "Read Byte Data (from-bus) register"] +pub mod rdarab; +#[doc = "RDATAH (r) register accessor: Read Half-word Data (from-bus) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdatah::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdatah`] module"] +pub type RDATAH = crate::Reg; +#[doc = "Read Half-word Data (from-bus) register"] +pub mod rdatah; +#[doc = "CAPABILITIES2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capabilities2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capabilities2`] module"] +pub type CAPABILITIES2 = crate::Reg; +#[doc = "NA"] +pub mod capabilities2; +#[doc = "CAPABILITIES (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capabilities::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capabilities`] module"] +pub type CAPABILITIES = crate::Reg; +#[doc = "NA"] +pub mod capabilities; +#[doc = "IDPARTNO (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idpartno::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idpartno::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idpartno`] module"] +pub type IDPARTNO = crate::Reg; +#[doc = "NA"] +pub mod idpartno; +#[doc = "IDEXT (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idext::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idext::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idext`] module"] +pub type IDEXT = crate::Reg; +#[doc = "NA"] +pub mod idext; +#[doc = "VENDORID (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vendorid::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vendorid::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vendorid`] module"] +pub type VENDORID = crate::Reg; +#[doc = "NA"] +pub mod vendorid; diff --git a/esp32p4/src/i3c_slv/capabilities.rs b/esp32p4/src/i3c_slv/capabilities.rs new file mode 100644 index 0000000000..60e249313e --- /dev/null +++ b/esp32p4/src/i3c_slv/capabilities.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CAPABILITIES` reader"] +pub type R = crate::R; +#[doc = "Field `CAPABLITIES` reader - NA"] +pub type CAPABLITIES_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn capablities(&self) -> CAPABLITIES_R { + CAPABLITIES_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAPABILITIES") + .field( + "capablities", + &format_args!("{}", self.capablities().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capabilities::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAPABILITIES_SPEC; +impl crate::RegisterSpec for CAPABILITIES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`capabilities::R`](R) reader structure"] +impl crate::Readable for CAPABILITIES_SPEC {} +#[doc = "`reset()` method sets CAPABILITIES to value 0x7c13_fc1c"] +impl crate::Resettable for CAPABILITIES_SPEC { + const RESET_VALUE: Self::Ux = 0x7c13_fc1c; +} diff --git a/esp32p4/src/i3c_slv/capabilities2.rs b/esp32p4/src/i3c_slv/capabilities2.rs new file mode 100644 index 0000000000..65bd137b9a --- /dev/null +++ b/esp32p4/src/i3c_slv/capabilities2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CAPABILITIES2` reader"] +pub type R = crate::R; +#[doc = "Field `CAPABLITIES2` reader - NA"] +pub type CAPABLITIES2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn capablities2(&self) -> CAPABLITIES2_R { + CAPABLITIES2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAPABILITIES2") + .field( + "capablities2", + &format_args!("{}", self.capablities2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capabilities2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAPABILITIES2_SPEC; +impl crate::RegisterSpec for CAPABILITIES2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`capabilities2::R`](R) reader structure"] +impl crate::Readable for CAPABILITIES2_SPEC {} +#[doc = "`reset()` method sets CAPABILITIES2 to value 0x0100"] +impl crate::Resettable for CAPABILITIES2_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/i3c_slv/config.rs b/esp32p4/src/i3c_slv/config.rs new file mode 100644 index 0000000000..f1c2d877b6 --- /dev/null +++ b/esp32p4/src/i3c_slv/config.rs @@ -0,0 +1,191 @@ +#[doc = "Register `CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `SLVENA` reader - 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master"] +pub type SLVENA_R = crate::BitReader; +#[doc = "Field `SLVENA` writer - 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master"] +pub type SLVENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACK` reader - 1:the slave will NACK all requests to it except CCC broadcast. This should be used with caution as the Master may determine the slave is missing if overused."] +pub type NACK_R = crate::BitReader; +#[doc = "Field `NACK` writer - 1:the slave will NACK all requests to it except CCC broadcast. This should be used with caution as the Master may determine the slave is missing if overused."] +pub type NACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MATCHSS` reader - 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This allows START and STOP to be used to detect end of a message to /from this slave."] +pub type MATCHSS_R = crate::BitReader; +#[doc = "Field `MATCHSS` writer - 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This allows START and STOP to be used to detect end of a message to /from this slave."] +pub type MATCHSS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S0IGNORE` reader - If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an Exit Pattern. This should only be used when the bus will not use HDR."] +pub type S0IGNORE_R = crate::BitReader; +#[doc = "Field `S0IGNORE` writer - If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an Exit Pattern. This should only be used when the bus will not use HDR."] +pub type S0IGNORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DDROK` reader - NA"] +pub type DDROK_R = crate::BitReader; +#[doc = "Field `DDROK` writer - NA"] +pub type DDROK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDRAND` reader - NA"] +pub type IDRAND_R = crate::BitReader; +#[doc = "Field `IDRAND` writer - NA"] +pub type IDRAND_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OFFLINE` reader - NA"] +pub type OFFLINE_R = crate::BitReader; +#[doc = "Field `OFFLINE` writer - NA"] +pub type OFFLINE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BAMATCH` reader - Bus Available condition match value for current ???Slow clock???. This provides the count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low when the Master is not doing so. The max width , and so max value, is controlled by the block. Only if enabled for events such IBI or MR or HJ, and if enabled to provide this as a register. With is limited to CLK_SLOW_BITS"] +pub type BAMATCH_R = crate::FieldReader; +#[doc = "Field `BAMATCH` writer - Bus Available condition match value for current ???Slow clock???. This provides the count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low when the Master is not doing so. The max width , and so max value, is controlled by the block. Only if enabled for events such IBI or MR or HJ, and if enabled to provide this as a register. With is limited to CLK_SLOW_BITS"] +pub type BAMATCH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SADDR` reader - If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled to use one and to be provided by SW. Block may provide in HW as well."] +pub type SADDR_R = crate::FieldReader; +#[doc = "Field `SADDR` writer - If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled to use one and to be provided by SW. Block may provide in HW as well."] +pub type SADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bit 0 - 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master"] + #[inline(always)] + pub fn slvena(&self) -> SLVENA_R { + SLVENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1:the slave will NACK all requests to it except CCC broadcast. This should be used with caution as the Master may determine the slave is missing if overused."] + #[inline(always)] + pub fn nack(&self) -> NACK_R { + NACK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This allows START and STOP to be used to detect end of a message to /from this slave."] + #[inline(always)] + pub fn matchss(&self) -> MATCHSS_R { + MATCHSS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an Exit Pattern. This should only be used when the bus will not use HDR."] + #[inline(always)] + pub fn s0ignore(&self) -> S0IGNORE_R { + S0IGNORE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ddrok(&self) -> DDROK_R { + DDROK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn idrand(&self) -> IDRAND_R { + IDRAND_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn offline(&self) -> OFFLINE_R { + OFFLINE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 16:23 - Bus Available condition match value for current ???Slow clock???. This provides the count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low when the Master is not doing so. The max width , and so max value, is controlled by the block. Only if enabled for events such IBI or MR or HJ, and if enabled to provide this as a register. With is limited to CLK_SLOW_BITS"] + #[inline(always)] + pub fn bamatch(&self) -> BAMATCH_R { + BAMATCH_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 25:31 - If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled to use one and to be provided by SW. Block may provide in HW as well."] + #[inline(always)] + pub fn saddr(&self) -> SADDR_R { + SADDR_R::new(((self.bits >> 25) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG") + .field("slvena", &format_args!("{}", self.slvena().bit())) + .field("nack", &format_args!("{}", self.nack().bit())) + .field("matchss", &format_args!("{}", self.matchss().bit())) + .field("s0ignore", &format_args!("{}", self.s0ignore().bit())) + .field("ddrok", &format_args!("{}", self.ddrok().bit())) + .field("idrand", &format_args!("{}", self.idrand().bit())) + .field("offline", &format_args!("{}", self.offline().bit())) + .field("bamatch", &format_args!("{}", self.bamatch().bits())) + .field("saddr", &format_args!("{}", self.saddr().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master"] + #[inline(always)] + #[must_use] + pub fn slvena(&mut self) -> SLVENA_W { + SLVENA_W::new(self, 0) + } + #[doc = "Bit 1 - 1:the slave will NACK all requests to it except CCC broadcast. This should be used with caution as the Master may determine the slave is missing if overused."] + #[inline(always)] + #[must_use] + pub fn nack(&mut self) -> NACK_W { + NACK_W::new(self, 1) + } + #[doc = "Bit 2 - 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This allows START and STOP to be used to detect end of a message to /from this slave."] + #[inline(always)] + #[must_use] + pub fn matchss(&mut self) -> MATCHSS_W { + MATCHSS_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an Exit Pattern. This should only be used when the bus will not use HDR."] + #[inline(always)] + #[must_use] + pub fn s0ignore(&mut self) -> S0IGNORE_W { + S0IGNORE_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn ddrok(&mut self) -> DDROK_W { + DDROK_W::new(self, 4) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn idrand(&mut self) -> IDRAND_W { + IDRAND_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn offline(&mut self) -> OFFLINE_W { + OFFLINE_W::new(self, 9) + } + #[doc = "Bits 16:23 - Bus Available condition match value for current ???Slow clock???. This provides the count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low when the Master is not doing so. The max width , and so max value, is controlled by the block. Only if enabled for events such IBI or MR or HJ, and if enabled to provide this as a register. With is limited to CLK_SLOW_BITS"] + #[inline(always)] + #[must_use] + pub fn bamatch(&mut self) -> BAMATCH_W { + BAMATCH_W::new(self, 16) + } + #[doc = "Bits 25:31 - If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled to use one and to be provided by SW. Block may provide in HW as well."] + #[inline(always)] + #[must_use] + pub fn saddr(&mut self) -> SADDR_W { + SADDR_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`config::R`](R) reader structure"] +impl crate::Readable for CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONFIG to value 0x002f_0001"] +impl crate::Resettable for CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0x002f_0001; +} diff --git a/esp32p4/src/i3c_slv/ctrl.rs b/esp32p4/src/i3c_slv/ctrl.rs new file mode 100644 index 0000000000..755e4e82ae --- /dev/null +++ b/esp32p4/src/i3c_slv/ctrl.rs @@ -0,0 +1,159 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SLV_EVENT` reader - If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1."] +pub type SLV_EVENT_R = crate::FieldReader; +#[doc = "Field `SLV_EVENT` writer - If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1."] +pub type SLV_EVENT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EXTDATA` reader - reserved"] +pub type EXTDATA_R = crate::BitReader; +#[doc = "Field `EXTDATA` writer - reserved"] +pub type EXTDATA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAPIDX` reader - Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic Address, or can be any valid index."] +pub type MAPIDX_R = crate::FieldReader; +#[doc = "Field `MAPIDX` writer - Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic Address, or can be any valid index."] +pub type MAPIDX_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `IBIDATA` reader - Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is required."] +pub type IBIDATA_R = crate::FieldReader; +#[doc = "Field `IBIDATA` writer - Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is required."] +pub type IBIDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PENDINT` reader - Should be set to the pending interrupt that GETSTATUS CCC will return. This should be maintained by the application if used and configured, as the Master will read this. If not configured, the GETSTATUS field will return 1 if an IBI is pending, and 0 otherwise."] +pub type PENDINT_R = crate::FieldReader; +#[doc = "Field `PENDINT` writer - Should be set to the pending interrupt that GETSTATUS CCC will return. This should be maintained by the application if used and configured, as the Master will read this. If not configured, the GETSTATUS field will return 1 if an IBI is pending, and 0 otherwise."] +pub type PENDINT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ACTSTATE` reader - NA"] +pub type ACTSTATE_R = crate::FieldReader; +#[doc = "Field `ACTSTATE` writer - NA"] +pub type ACTSTATE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `VENDINFO` reader - NA"] +pub type VENDINFO_R = crate::FieldReader; +#[doc = "Field `VENDINFO` writer - NA"] +pub type VENDINFO_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:1 - If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1."] + #[inline(always)] + pub fn slv_event(&self) -> SLV_EVENT_R { + SLV_EVENT_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 3 - reserved"] + #[inline(always)] + pub fn extdata(&self) -> EXTDATA_R { + EXTDATA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic Address, or can be any valid index."] + #[inline(always)] + pub fn mapidx(&self) -> MAPIDX_R { + MAPIDX_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:15 - Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is required."] + #[inline(always)] + pub fn ibidata(&self) -> IBIDATA_R { + IBIDATA_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:19 - Should be set to the pending interrupt that GETSTATUS CCC will return. This should be maintained by the application if used and configured, as the Master will read this. If not configured, the GETSTATUS field will return 1 if an IBI is pending, and 0 otherwise."] + #[inline(always)] + pub fn pendint(&self) -> PENDINT_R { + PENDINT_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:21 - NA"] + #[inline(always)] + pub fn actstate(&self) -> ACTSTATE_R { + ACTSTATE_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 24:31 - NA"] + #[inline(always)] + pub fn vendinfo(&self) -> VENDINFO_R { + VENDINFO_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTRL") + .field("slv_event", &format_args!("{}", self.slv_event().bits())) + .field("extdata", &format_args!("{}", self.extdata().bit())) + .field("mapidx", &format_args!("{}", self.mapidx().bits())) + .field("ibidata", &format_args!("{}", self.ibidata().bits())) + .field("pendint", &format_args!("{}", self.pendint().bits())) + .field("actstate", &format_args!("{}", self.actstate().bits())) + .field("vendinfo", &format_args!("{}", self.vendinfo().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1."] + #[inline(always)] + #[must_use] + pub fn slv_event(&mut self) -> SLV_EVENT_W { + SLV_EVENT_W::new(self, 0) + } + #[doc = "Bit 3 - reserved"] + #[inline(always)] + #[must_use] + pub fn extdata(&mut self) -> EXTDATA_W { + EXTDATA_W::new(self, 3) + } + #[doc = "Bits 4:7 - Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic Address, or can be any valid index."] + #[inline(always)] + #[must_use] + pub fn mapidx(&mut self) -> MAPIDX_W { + MAPIDX_W::new(self, 4) + } + #[doc = "Bits 8:15 - Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is required."] + #[inline(always)] + #[must_use] + pub fn ibidata(&mut self) -> IBIDATA_W { + IBIDATA_W::new(self, 8) + } + #[doc = "Bits 16:19 - Should be set to the pending interrupt that GETSTATUS CCC will return. This should be maintained by the application if used and configured, as the Master will read this. If not configured, the GETSTATUS field will return 1 if an IBI is pending, and 0 otherwise."] + #[inline(always)] + #[must_use] + pub fn pendint(&mut self) -> PENDINT_W { + PENDINT_W::new(self, 16) + } + #[doc = "Bits 20:21 - NA"] + #[inline(always)] + #[must_use] + pub fn actstate(&mut self) -> ACTSTATE_W { + ACTSTATE_W::new(self, 20) + } + #[doc = "Bits 24:31 - NA"] + #[inline(always)] + #[must_use] + pub fn vendinfo(&mut self) -> VENDINFO_W { + VENDINFO_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_slv/datactrl.rs b/esp32p4/src/i3c_slv/datactrl.rs new file mode 100644 index 0000000000..36547de01d --- /dev/null +++ b/esp32p4/src/i3c_slv/datactrl.rs @@ -0,0 +1,135 @@ +#[doc = "Register `DATACTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DATACTRL` writer"] +pub type W = crate::W; +#[doc = "Field `FLUSHTB` writer - Flushes the from-bus buffer/FIFO. Not normally used"] +pub type FLUSHTB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FLUSHFB` writer - Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message prematurely"] +pub type FLUSHFB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UNLOCK` writer - If this bit is not written 1, the register bits from 7 to 4 are not changed on write."] +pub type UNLOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXTRIG` reader - Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3"] +pub type TXTRIG_R = crate::FieldReader; +#[doc = "Field `TXTRIG` writer - Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3"] +pub type TXTRIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RXTRIG` reader - Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3"] +pub type RXTRIG_R = crate::FieldReader; +#[doc = "Field `RXTRIG` writer - Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3"] +pub type RXTRIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TXCOUNT` reader - NA"] +pub type TXCOUNT_R = crate::FieldReader; +#[doc = "Field `RXCOUNT` reader - NA"] +pub type RXCOUNT_R = crate::FieldReader; +#[doc = "Field `TXFULL` reader - NA"] +pub type TXFULL_R = crate::BitReader; +#[doc = "Field `RXEMPTY` reader - NA"] +pub type RXEMPTY_R = crate::BitReader; +impl R { + #[doc = "Bits 4:5 - Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3"] + #[inline(always)] + pub fn txtrig(&self) -> TXTRIG_R { + TXTRIG_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3"] + #[inline(always)] + pub fn rxtrig(&self) -> RXTRIG_R { + RXTRIG_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 16:20 - NA"] + #[inline(always)] + pub fn txcount(&self) -> TXCOUNT_R { + TXCOUNT_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 24:28 - NA"] + #[inline(always)] + pub fn rxcount(&self) -> RXCOUNT_R { + RXCOUNT_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bit 30 - NA"] + #[inline(always)] + pub fn txfull(&self) -> TXFULL_R { + TXFULL_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - NA"] + #[inline(always)] + pub fn rxempty(&self) -> RXEMPTY_R { + RXEMPTY_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATACTRL") + .field("txtrig", &format_args!("{}", self.txtrig().bits())) + .field("rxtrig", &format_args!("{}", self.rxtrig().bits())) + .field("txcount", &format_args!("{}", self.txcount().bits())) + .field("rxcount", &format_args!("{}", self.rxcount().bits())) + .field("txfull", &format_args!("{}", self.txfull().bit())) + .field("rxempty", &format_args!("{}", self.rxempty().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Flushes the from-bus buffer/FIFO. Not normally used"] + #[inline(always)] + #[must_use] + pub fn flushtb(&mut self) -> FLUSHTB_W { + FLUSHTB_W::new(self, 0) + } + #[doc = "Bit 1 - Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message prematurely"] + #[inline(always)] + #[must_use] + pub fn flushfb(&mut self) -> FLUSHFB_W { + FLUSHFB_W::new(self, 1) + } + #[doc = "Bit 3 - If this bit is not written 1, the register bits from 7 to 4 are not changed on write."] + #[inline(always)] + #[must_use] + pub fn unlock(&mut self) -> UNLOCK_W { + UNLOCK_W::new(self, 3) + } + #[doc = "Bits 4:5 - Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3"] + #[inline(always)] + #[must_use] + pub fn txtrig(&mut self) -> TXTRIG_W { + TXTRIG_W::new(self, 4) + } + #[doc = "Bits 6:7 - Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3"] + #[inline(always)] + #[must_use] + pub fn rxtrig(&mut self) -> RXTRIG_W { + RXTRIG_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datactrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datactrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATACTRL_SPEC; +impl crate::RegisterSpec for DATACTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`datactrl::R`](R) reader structure"] +impl crate::Readable for DATACTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`datactrl::W`](W) writer structure"] +impl crate::Writable for DATACTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATACTRL to value 0xb0"] +impl crate::Resettable for DATACTRL_SPEC { + const RESET_VALUE: Self::Ux = 0xb0; +} diff --git a/esp32p4/src/i3c_slv/idext.rs b/esp32p4/src/i3c_slv/idext.rs new file mode 100644 index 0000000000..cded367390 --- /dev/null +++ b/esp32p4/src/i3c_slv/idext.rs @@ -0,0 +1,63 @@ +#[doc = "Register `IDEXT` reader"] +pub type R = crate::R; +#[doc = "Register `IDEXT` writer"] +pub type W = crate::W; +#[doc = "Field `IDEXT` reader - NA"] +pub type IDEXT_R = crate::FieldReader; +#[doc = "Field `IDEXT` writer - NA"] +pub type IDEXT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn idext(&self) -> IDEXT_R { + IDEXT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IDEXT") + .field("idext", &format_args!("{}", self.idext().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn idext(&mut self) -> IDEXT_W { + IDEXT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idext::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idext::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IDEXT_SPEC; +impl crate::RegisterSpec for IDEXT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`idext::R`](R) reader structure"] +impl crate::Readable for IDEXT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`idext::W`](W) writer structure"] +impl crate::Writable for IDEXT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IDEXT to value 0"] +impl crate::Resettable for IDEXT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_slv/idpartno.rs b/esp32p4/src/i3c_slv/idpartno.rs new file mode 100644 index 0000000000..569a28abf4 --- /dev/null +++ b/esp32p4/src/i3c_slv/idpartno.rs @@ -0,0 +1,63 @@ +#[doc = "Register `IDPARTNO` reader"] +pub type R = crate::R; +#[doc = "Register `IDPARTNO` writer"] +pub type W = crate::W; +#[doc = "Field `PARTNO` reader - NA"] +pub type PARTNO_R = crate::FieldReader; +#[doc = "Field `PARTNO` writer - NA"] +pub type PARTNO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IDPARTNO") + .field("partno", &format_args!("{}", self.partno().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + #[must_use] + pub fn partno(&mut self) -> PARTNO_W { + PARTNO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idpartno::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idpartno::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IDPARTNO_SPEC; +impl crate::RegisterSpec for IDPARTNO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`idpartno::R`](R) reader structure"] +impl crate::Readable for IDPARTNO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`idpartno::W`](W) writer structure"] +impl crate::Writable for IDPARTNO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IDPARTNO to value 0"] +impl crate::Resettable for IDPARTNO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_slv/intclr.rs b/esp32p4/src/i3c_slv/intclr.rs new file mode 100644 index 0000000000..3abd0ba599 --- /dev/null +++ b/esp32p4/src/i3c_slv/intclr.rs @@ -0,0 +1,58 @@ +#[doc = "Register `INTCLR` writer"] +pub type W = crate::W; +#[doc = "Field `STOP_CLR` writer - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped."] +pub type STOP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXPEND_CLR` writer - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end."] +pub type RXPEND_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXSEND_CLR` writer - NA"] +pub type TXSEND_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 10 - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped."] + #[inline(always)] + #[must_use] + pub fn stop_clr(&mut self) -> STOP_CLR_W { + STOP_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end."] + #[inline(always)] + #[must_use] + pub fn rxpend_clr(&mut self) -> RXPEND_CLR_W { + RXPEND_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn txsend_clr(&mut self) -> TXSEND_CLR_W { + TXSEND_CLR_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTCLR_SPEC; +impl crate::RegisterSpec for INTCLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`intclr::W`](W) writer structure"] +impl crate::Writable for INTCLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTCLR to value 0"] +impl crate::Resettable for INTCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_slv/intmasked.rs b/esp32p4/src/i3c_slv/intmasked.rs new file mode 100644 index 0000000000..2c99eb19bf --- /dev/null +++ b/esp32p4/src/i3c_slv/intmasked.rs @@ -0,0 +1,52 @@ +#[doc = "Register `INTMASKED` reader"] +pub type R = crate::R; +#[doc = "Field `STOP_MASK` reader - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped."] +pub type STOP_MASK_R = crate::BitReader; +#[doc = "Field `RXPEND_MASK` reader - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end."] +pub type RXPEND_MASK_R = crate::BitReader; +#[doc = "Field `TXSEND_MASK` reader - NA"] +pub type TXSEND_MASK_R = crate::BitReader; +impl R { + #[doc = "Bit 10 - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped."] + #[inline(always)] + pub fn stop_mask(&self) -> STOP_MASK_R { + STOP_MASK_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end."] + #[inline(always)] + pub fn rxpend_mask(&self) -> RXPEND_MASK_R { + RXPEND_MASK_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn txsend_mask(&self) -> TXSEND_MASK_R { + TXSEND_MASK_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTMASKED") + .field("stop_mask", &format_args!("{}", self.stop_mask().bit())) + .field("rxpend_mask", &format_args!("{}", self.rxpend_mask().bit())) + .field("txsend_mask", &format_args!("{}", self.txsend_mask().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intmasked::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTMASKED_SPEC; +impl crate::RegisterSpec for INTMASKED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intmasked::R`](R) reader structure"] +impl crate::Readable for INTMASKED_SPEC {} +#[doc = "`reset()` method sets INTMASKED to value 0"] +impl crate::Resettable for INTMASKED_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_slv/intset.rs b/esp32p4/src/i3c_slv/intset.rs new file mode 100644 index 0000000000..293068e0c2 --- /dev/null +++ b/esp32p4/src/i3c_slv/intset.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INTSET` reader"] +pub type R = crate::R; +#[doc = "Register `INTSET` writer"] +pub type W = crate::W; +#[doc = "Field `STOP_ENA` reader - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped."] +pub type STOP_ENA_R = crate::BitReader; +#[doc = "Field `STOP_ENA` writer - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped."] +pub type STOP_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXPEND_ENA` reader - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end."] +pub type RXPEND_ENA_R = crate::BitReader; +#[doc = "Field `RXPEND_ENA` writer - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end."] +pub type RXPEND_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXSEND_ENA` reader - NA"] +pub type TXSEND_ENA_R = crate::BitReader; +#[doc = "Field `TXSEND_ENA` writer - NA"] +pub type TXSEND_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 10 - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped."] + #[inline(always)] + pub fn stop_ena(&self) -> STOP_ENA_R { + STOP_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end."] + #[inline(always)] + pub fn rxpend_ena(&self) -> RXPEND_ENA_R { + RXPEND_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn txsend_ena(&self) -> TXSEND_ENA_R { + TXSEND_ENA_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTSET") + .field("stop_ena", &format_args!("{}", self.stop_ena().bit())) + .field("rxpend_ena", &format_args!("{}", self.rxpend_ena().bit())) + .field("txsend_ena", &format_args!("{}", self.txsend_ena().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 10 - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped."] + #[inline(always)] + #[must_use] + pub fn stop_ena(&mut self) -> STOP_ENA_W { + STOP_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end."] + #[inline(always)] + #[must_use] + pub fn rxpend_ena(&mut self) -> RXPEND_ENA_W { + RXPEND_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn txsend_ena(&mut self) -> TXSEND_ENA_W { + TXSEND_ENA_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTSET_SPEC; +impl crate::RegisterSpec for INTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intset::R`](R) reader structure"] +impl crate::Readable for INTSET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intset::W`](W) writer structure"] +impl crate::Writable for INTSET_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTSET to value 0"] +impl crate::Resettable for INTSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_slv/rdarab.rs b/esp32p4/src/i3c_slv/rdarab.rs new file mode 100644 index 0000000000..13a3a1c3c0 --- /dev/null +++ b/esp32p4/src/i3c_slv/rdarab.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RDARAB` reader"] +pub type R = crate::R; +#[doc = "Field `DATA0` reader - This register allows reading a byte from the bus unless external FIFO is used. A byte should not be read unless there is data waiting, as indicated by the RXPEND bit being set in the STATUS register"] +pub type DATA0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - This register allows reading a byte from the bus unless external FIFO is used. A byte should not be read unless there is data waiting, as indicated by the RXPEND bit being set in the STATUS register"] + #[inline(always)] + pub fn data0(&self) -> DATA0_R { + DATA0_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDARAB") + .field("data0", &format_args!("{}", self.data0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Read Byte Data (from-bus) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdarab::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDARAB_SPEC; +impl crate::RegisterSpec for RDARAB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdarab::R`](R) reader structure"] +impl crate::Readable for RDARAB_SPEC {} +#[doc = "`reset()` method sets RDARAB to value 0"] +impl crate::Resettable for RDARAB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_slv/rdatah.rs b/esp32p4/src/i3c_slv/rdatah.rs new file mode 100644 index 0000000000..6a58ebb80c --- /dev/null +++ b/esp32p4/src/i3c_slv/rdatah.rs @@ -0,0 +1,44 @@ +#[doc = "Register `RDATAH` reader"] +pub type R = crate::R; +#[doc = "Field `DATA_LSB` reader - NA"] +pub type DATA_LSB_R = crate::FieldReader; +#[doc = "Field `DATA_MSB` reader - This register allows reading a Half-word (byte pair) from the bus unless external FIFO is used. A Half-word should not be read unless there is at least 2 bytes of data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space in the DATACTRL register"] +pub type DATA_MSB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + pub fn data_lsb(&self) -> DATA_LSB_R { + DATA_LSB_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - This register allows reading a Half-word (byte pair) from the bus unless external FIFO is used. A Half-word should not be read unless there is at least 2 bytes of data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space in the DATACTRL register"] + #[inline(always)] + pub fn data_msb(&self) -> DATA_MSB_R { + DATA_MSB_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDATAH") + .field("data_lsb", &format_args!("{}", self.data_lsb().bits())) + .field("data_msb", &format_args!("{}", self.data_msb().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Read Half-word Data (from-bus) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdatah::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDATAH_SPEC; +impl crate::RegisterSpec for RDATAH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdatah::R`](R) reader structure"] +impl crate::Readable for RDATAH_SPEC {} +#[doc = "`reset()` method sets RDATAH to value 0"] +impl crate::Resettable for RDATAH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_slv/status.rs b/esp32p4/src/i3c_slv/status.rs new file mode 100644 index 0000000000..1538047dd1 --- /dev/null +++ b/esp32p4/src/i3c_slv/status.rs @@ -0,0 +1,223 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `STNOTSTOP` reader - Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also set when busy. Note that this can also be true from an S0 or S1 error, which waits for an Exit Pattern."] +pub type STNOTSTOP_R = crate::BitReader; +#[doc = "Field `STMSG` reader - Is 1 if this bus Slave is listening to the bus traffic or repsonding, If STNOSTOP=1, then this will be 0 when a non-matching address seen until next respeated START it STOP."] +pub type STMSG_R = crate::BitReader; +#[doc = "Field `STCCCH` reader - Is 1 if a CCC message is being handled automatically."] +pub type STCCCH_R = crate::BitReader; +#[doc = "Field `STREQRD` reader - 1 if the req in process is an sdr read from this slave or an IBI is being pushed out,"] +pub type STREQRD_R = crate::BitReader; +#[doc = "Field `STREQWR` reader - NA"] +pub type STREQWR_R = crate::BitReader; +#[doc = "Field `STDAA` reader - NA"] +pub type STDAA_R = crate::BitReader; +#[doc = "Field `STHDR` reader - NA"] +pub type STHDR_R = crate::BitReader; +#[doc = "Field `START` reader - NA"] +pub type START_R = crate::BitReader; +#[doc = "Field `START` writer - NA"] +pub type START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MATCHED` reader - NA"] +pub type MATCHED_R = crate::BitReader; +#[doc = "Field `MATCHED` writer - NA"] +pub type MATCHED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STOP` reader - NA"] +pub type STOP_R = crate::BitReader; +#[doc = "Field `STOP` writer - NA"] +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXPEND` reader - Receiving a message from master,which is not being handled by block(not a CCC internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will self-clear if data is read(FIFO and non-FIFO)"] +pub type RXPEND_R = crate::BitReader; +#[doc = "Field `TXNOTFULL` reader - Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is enabled for TX, it will also be signaled to provide more."] +pub type TXNOTFULL_R = crate::BitReader; +#[doc = "Field `DACHG` reader - The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in that state of being valid or none. Actual DA can be seen in the DYNADDR register. Note that this will also be used when MAP Auto feature is configured. This will be changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate if last change was due to Auto MAP."] +pub type DACHG_R = crate::BitReader; +#[doc = "Field `DACHG` writer - The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in that state of being valid or none. Actual DA can be seen in the DYNADDR register. Note that this will also be used when MAP Auto feature is configured. This will be changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate if last change was due to Auto MAP."] +pub type DACHG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CCC` reader - A common -command-code(CCC), not handled by block, has been received. This acts differently between: *Broadcasted ones, which will then also correspond with RXPEND and the 1st byte will be the CCC(command) . *Direct ones, which may never be directed to this device. If it is, then the TXSEND or RXPEND will be triggered with this end the RXPEND will contain the command."] +pub type CCC_R = crate::BitReader; +#[doc = "Field `CCC` writer - A common -command-code(CCC), not handled by block, has been received. This acts differently between: *Broadcasted ones, which will then also correspond with RXPEND and the 1st byte will be the CCC(command) . *Direct ones, which may never be directed to this device. If it is, then the TXSEND or RXPEND will be triggered with this end the RXPEND will contain the command."] +pub type CCC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERRWARN` reader - NA"] +pub type ERRWARN_R = crate::BitReader; +#[doc = "Field `HDRMATCH` reader - NA"] +pub type HDRMATCH_R = crate::BitReader; +#[doc = "Field `HDRMATCH` writer - NA"] +pub type HDRMATCH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also set when busy. Note that this can also be true from an S0 or S1 error, which waits for an Exit Pattern."] + #[inline(always)] + pub fn stnotstop(&self) -> STNOTSTOP_R { + STNOTSTOP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Is 1 if this bus Slave is listening to the bus traffic or repsonding, If STNOSTOP=1, then this will be 0 when a non-matching address seen until next respeated START it STOP."] + #[inline(always)] + pub fn stmsg(&self) -> STMSG_R { + STMSG_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Is 1 if a CCC message is being handled automatically."] + #[inline(always)] + pub fn stccch(&self) -> STCCCH_R { + STCCCH_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1 if the req in process is an sdr read from this slave or an IBI is being pushed out,"] + #[inline(always)] + pub fn streqrd(&self) -> STREQRD_R { + STREQRD_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn streqwr(&self) -> STREQWR_R { + STREQWR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn stdaa(&self) -> STDAA_R { + STDAA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn sthdr(&self) -> STHDR_R { + STHDR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn matched(&self) -> MATCHED_R { + MATCHED_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Receiving a message from master,which is not being handled by block(not a CCC internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will self-clear if data is read(FIFO and non-FIFO)"] + #[inline(always)] + pub fn rxpend(&self) -> RXPEND_R { + RXPEND_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is enabled for TX, it will also be signaled to provide more."] + #[inline(always)] + pub fn txnotfull(&self) -> TXNOTFULL_R { + TXNOTFULL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in that state of being valid or none. Actual DA can be seen in the DYNADDR register. Note that this will also be used when MAP Auto feature is configured. This will be changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate if last change was due to Auto MAP."] + #[inline(always)] + pub fn dachg(&self) -> DACHG_R { + DACHG_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - A common -command-code(CCC), not handled by block, has been received. This acts differently between: *Broadcasted ones, which will then also correspond with RXPEND and the 1st byte will be the CCC(command) . *Direct ones, which may never be directed to this device. If it is, then the TXSEND or RXPEND will be triggered with this end the RXPEND will contain the command."] + #[inline(always)] + pub fn ccc(&self) -> CCC_R { + CCC_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn errwarn(&self) -> ERRWARN_R { + ERRWARN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn hdrmatch(&self) -> HDRMATCH_R { + HDRMATCH_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field("stnotstop", &format_args!("{}", self.stnotstop().bit())) + .field("stmsg", &format_args!("{}", self.stmsg().bit())) + .field("stccch", &format_args!("{}", self.stccch().bit())) + .field("streqrd", &format_args!("{}", self.streqrd().bit())) + .field("streqwr", &format_args!("{}", self.streqwr().bit())) + .field("stdaa", &format_args!("{}", self.stdaa().bit())) + .field("sthdr", &format_args!("{}", self.sthdr().bit())) + .field("start", &format_args!("{}", self.start().bit())) + .field("matched", &format_args!("{}", self.matched().bit())) + .field("stop", &format_args!("{}", self.stop().bit())) + .field("rxpend", &format_args!("{}", self.rxpend().bit())) + .field("txnotfull", &format_args!("{}", self.txnotfull().bit())) + .field("dachg", &format_args!("{}", self.dachg().bit())) + .field("ccc", &format_args!("{}", self.ccc().bit())) + .field("errwarn", &format_args!("{}", self.errwarn().bit())) + .field("hdrmatch", &format_args!("{}", self.hdrmatch().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> START_W { + START_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn matched(&mut self) -> MATCHED_W { + MATCHED_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 10) + } + #[doc = "Bit 13 - The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in that state of being valid or none. Actual DA can be seen in the DYNADDR register. Note that this will also be used when MAP Auto feature is configured. This will be changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate if last change was due to Auto MAP."] + #[inline(always)] + #[must_use] + pub fn dachg(&mut self) -> DACHG_W { + DACHG_W::new(self, 13) + } + #[doc = "Bit 14 - A common -command-code(CCC), not handled by block, has been received. This acts differently between: *Broadcasted ones, which will then also correspond with RXPEND and the 1st byte will be the CCC(command) . *Direct ones, which may never be directed to this device. If it is, then the TXSEND or RXPEND will be triggered with this end the RXPEND will contain the command."] + #[inline(always)] + #[must_use] + pub fn ccc(&mut self) -> CCC_W { + CCC_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn hdrmatch(&mut self) -> HDRMATCH_W { + HDRMATCH_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_slv/vendorid.rs b/esp32p4/src/i3c_slv/vendorid.rs new file mode 100644 index 0000000000..11073edc71 --- /dev/null +++ b/esp32p4/src/i3c_slv/vendorid.rs @@ -0,0 +1,63 @@ +#[doc = "Register `VENDORID` reader"] +pub type R = crate::R; +#[doc = "Register `VENDORID` writer"] +pub type W = crate::W; +#[doc = "Field `VID` reader - NA"] +pub type VID_R = crate::FieldReader; +#[doc = "Field `VID` writer - NA"] +pub type VID_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + pub fn vid(&self) -> VID_R { + VID_R::new((self.bits & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VENDORID") + .field("vid", &format_args!("{}", self.vid().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + #[must_use] + pub fn vid(&mut self) -> VID_W { + VID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vendorid::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vendorid::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VENDORID_SPEC; +impl crate::RegisterSpec for VENDORID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vendorid::R`](R) reader structure"] +impl crate::Readable for VENDORID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vendorid::W`](W) writer structure"] +impl crate::Writable for VENDORID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VENDORID to value 0x5550"] +impl crate::Resettable for VENDORID_SPEC { + const RESET_VALUE: Self::Ux = 0x5550; +} diff --git a/esp32p4/src/i3c_slv/wdatab.rs b/esp32p4/src/i3c_slv/wdatab.rs new file mode 100644 index 0000000000..0e7307d6f0 --- /dev/null +++ b/esp32p4/src/i3c_slv/wdatab.rs @@ -0,0 +1,50 @@ +#[doc = "Register `WDATAB` writer"] +pub type W = crate::W; +#[doc = "Field `WDATAB` writer - NA"] +pub type WDATAB_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WDATA_END` writer - NA"] +pub type WDATA_END_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + #[must_use] + pub fn wdatab(&mut self) -> WDATAB_W { + WDATAB_W::new(self, 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn wdata_end(&mut self) -> WDATA_END_W { + WDATA_END_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdatab::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDATAB_SPEC; +impl crate::RegisterSpec for WDATAB_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`wdatab::W`](W) writer structure"] +impl crate::Writable for WDATAB_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WDATAB to value 0"] +impl crate::Resettable for WDATAB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/i3c_slv/wdatabe.rs b/esp32p4/src/i3c_slv/wdatabe.rs new file mode 100644 index 0000000000..67481cf87b --- /dev/null +++ b/esp32p4/src/i3c_slv/wdatabe.rs @@ -0,0 +1,42 @@ +#[doc = "Register `WDATABE` writer"] +pub type W = crate::W; +#[doc = "Field `WDATABE` writer - NA"] +pub type WDATABE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + #[must_use] + pub fn wdatabe(&mut self) -> WDATABE_W { + WDATABE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdatabe::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDATABE_SPEC; +impl crate::RegisterSpec for WDATABE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`wdatabe::W`](W) writer structure"] +impl crate::Writable for WDATABE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WDATABE to value 0"] +impl crate::Resettable for WDATABE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt.rs b/esp32p4/src/interrupt.rs new file mode 100644 index 0000000000..470c9e0ec5 --- /dev/null +++ b/esp32p4/src/interrupt.rs @@ -0,0 +1,292 @@ +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "1 - LP_WDT"] + LP_WDT = 1, + #[doc = "2 - LP_TIMER0"] + LP_TIMER0 = 2, + #[doc = "3 - LP_TIMER1"] + LP_TIMER1 = 3, + #[doc = "6 - PMU0"] + PMU0 = 6, + #[doc = "7 - PMU1"] + PMU1 = 7, + #[doc = "8 - LP_ANA"] + LP_ANA = 8, + #[doc = "9 - LP_ADC"] + LP_ADC = 9, + #[doc = "10 - LP_GPIO"] + LP_GPIO = 10, + #[doc = "11 - LP_I2C0"] + LP_I2C0 = 11, + #[doc = "12 - LP_I2S0"] + LP_I2S0 = 12, + #[doc = "14 - LP_TOUCH"] + LP_TOUCH = 14, + #[doc = "15 - LP_TSENS"] + LP_TSENS = 15, + #[doc = "16 - LP_UART"] + LP_UART = 16, + #[doc = "19 - LP_SYS"] + LP_SYS = 19, + #[doc = "20 - LP_HUK"] + LP_HUK = 20, + #[doc = "22 - USB_DEVICE"] + USB_DEVICE = 22, + #[doc = "24 - DMA"] + DMA = 24, + #[doc = "25 - SPI2"] + SPI2 = 25, + #[doc = "26 - SPI3"] + SPI3 = 26, + #[doc = "27 - I2S0"] + I2S0 = 27, + #[doc = "28 - I2S1"] + I2S1 = 28, + #[doc = "29 - I2S2"] + I2S2 = 29, + #[doc = "30 - UHCI0"] + UHCI0 = 30, + #[doc = "31 - UART0"] + UART0 = 31, + #[doc = "38 - PWM0"] + PWM0 = 38, + #[doc = "39 - PWM1"] + PWM1 = 39, + #[doc = "40 - TWAI0"] + TWAI0 = 40, + #[doc = "41 - TWAI1"] + TWAI1 = 41, + #[doc = "42 - TWAI2"] + TWAI2 = 42, + #[doc = "43 - RMT"] + RMT = 43, + #[doc = "44 - I2C0"] + I2C0 = 44, + #[doc = "45 - I2C1"] + I2C1 = 45, + #[doc = "46 - TG0_T0"] + TG0_T0 = 46, + #[doc = "47 - TG0_T1"] + TG0_T1 = 47, + #[doc = "48 - TG0_WDT"] + TG0_WDT = 48, + #[doc = "49 - TG1_T0"] + TG1_T0 = 49, + #[doc = "50 - TG1_T1"] + TG1_T1 = 50, + #[doc = "51 - TG1_WDT"] + TG1_WDT = 51, + #[doc = "52 - LEDC"] + LEDC = 52, + #[doc = "53 - SYSTIMER_TARGET0"] + SYSTIMER_TARGET0 = 53, + #[doc = "54 - SYSTIMER_TARGET1"] + SYSTIMER_TARGET1 = 54, + #[doc = "55 - SYSTIMER_TARGET2"] + SYSTIMER_TARGET2 = 55, + #[doc = "68 - RSA"] + RSA = 68, + #[doc = "69 - AES"] + AES = 69, + #[doc = "70 - SHA"] + SHA = 70, + #[doc = "71 - ECC"] + ECC = 71, + #[doc = "74 - GPIO_INT0"] + GPIO_INT0 = 74, + #[doc = "75 - GPIO_INT1"] + GPIO_INT1 = 75, + #[doc = "76 - GPIO_INT2"] + GPIO_INT2 = 76, + #[doc = "77 - GPIO_INT3"] + GPIO_INT3 = 77, + #[doc = "78 - GPIO_PAD_COMP"] + GPIO_PAD_COMP = 78, + #[doc = "83 - CACHE"] + CACHE = 83, + #[doc = "85 - CSI_BRIDGE"] + CSI_BRIDGE = 85, + #[doc = "86 - DSI_BRIDGE"] + DSI_BRIDGE = 86, + #[doc = "87 - CSI"] + CSI = 87, + #[doc = "88 - DSI"] + DSI = 88, + #[doc = "95 - JPEG"] + JPEG = 95, + #[doc = "96 - PPA"] + PPA = 96, + #[doc = "100 - ISP"] + ISP = 100, + #[doc = "101 - I3C"] + I3C = 101, + #[doc = "102 - I3C_SLV"] + I3C_SLV = 102, + #[doc = "110 - HP_SYS"] + HP_SYS = 110, + #[doc = "111 - PCNT"] + PCNT = 111, + #[doc = "112 - PAU"] + PAU = 112, + #[doc = "113 - PARLIO_RX"] + PARLIO_RX = 113, + #[doc = "114 - PARLIO_TX"] + PARLIO_TX = 114, + #[doc = "115 - H264_DMA2D_OUT_CH0"] + H264_DMA2D_OUT_CH0 = 115, + #[doc = "116 - H264_DMA2D_OUT_CH1"] + H264_DMA2D_OUT_CH1 = 116, + #[doc = "117 - H264_DMA2D_OUT_CH2"] + H264_DMA2D_OUT_CH2 = 117, + #[doc = "118 - H264_DMA2D_OUT_CH3"] + H264_DMA2D_OUT_CH3 = 118, + #[doc = "119 - H264_DMA2D_OUT_CH4"] + H264_DMA2D_OUT_CH4 = 119, + #[doc = "120 - H264_DMA2D_IN_CH0"] + H264_DMA2D_IN_CH0 = 120, + #[doc = "121 - H264_DMA2D_IN_CH1"] + H264_DMA2D_IN_CH1 = 121, + #[doc = "122 - H264_DMA2D_IN_CH2"] + H264_DMA2D_IN_CH2 = 122, + #[doc = "123 - H264_DMA2D_IN_CH3"] + H264_DMA2D_IN_CH3 = 123, + #[doc = "124 - H264_DMA2D_IN_CH4"] + H264_DMA2D_IN_CH4 = 124, + #[doc = "125 - H264_DMA2D_IN_CH5"] + H264_DMA2D_IN_CH5 = 125, + #[doc = "126 - H264_REG"] + H264_REG = 126, + #[doc = "127 - ASSIST_DEBUG"] + ASSIST_DEBUG = 127, +} +#[doc = r" TryFromInterruptError"] +#[derive(Debug, Copy, Clone)] +pub struct TryFromInterruptError(()); +impl Interrupt { + #[doc = r" Attempt to convert a given value into an `Interrupt`"] + #[inline] + pub fn try_from(value: u8) -> Result { + match value { + 1 => Ok(Interrupt::LP_WDT), + 2 => Ok(Interrupt::LP_TIMER0), + 3 => Ok(Interrupt::LP_TIMER1), + 6 => Ok(Interrupt::PMU0), + 7 => Ok(Interrupt::PMU1), + 8 => Ok(Interrupt::LP_ANA), + 9 => Ok(Interrupt::LP_ADC), + 10 => Ok(Interrupt::LP_GPIO), + 11 => Ok(Interrupt::LP_I2C0), + 12 => Ok(Interrupt::LP_I2S0), + 14 => Ok(Interrupt::LP_TOUCH), + 15 => Ok(Interrupt::LP_TSENS), + 16 => Ok(Interrupt::LP_UART), + 19 => Ok(Interrupt::LP_SYS), + 20 => Ok(Interrupt::LP_HUK), + 22 => Ok(Interrupt::USB_DEVICE), + 24 => Ok(Interrupt::DMA), + 25 => Ok(Interrupt::SPI2), + 26 => Ok(Interrupt::SPI3), + 27 => Ok(Interrupt::I2S0), + 28 => Ok(Interrupt::I2S1), + 29 => Ok(Interrupt::I2S2), + 30 => Ok(Interrupt::UHCI0), + 31 => Ok(Interrupt::UART0), + 38 => Ok(Interrupt::PWM0), + 39 => Ok(Interrupt::PWM1), + 40 => Ok(Interrupt::TWAI0), + 41 => Ok(Interrupt::TWAI1), + 42 => Ok(Interrupt::TWAI2), + 43 => Ok(Interrupt::RMT), + 44 => Ok(Interrupt::I2C0), + 45 => Ok(Interrupt::I2C1), + 46 => Ok(Interrupt::TG0_T0), + 47 => Ok(Interrupt::TG0_T1), + 48 => Ok(Interrupt::TG0_WDT), + 49 => Ok(Interrupt::TG1_T0), + 50 => Ok(Interrupt::TG1_T1), + 51 => Ok(Interrupt::TG1_WDT), + 52 => Ok(Interrupt::LEDC), + 53 => Ok(Interrupt::SYSTIMER_TARGET0), + 54 => Ok(Interrupt::SYSTIMER_TARGET1), + 55 => Ok(Interrupt::SYSTIMER_TARGET2), + 68 => Ok(Interrupt::RSA), + 69 => Ok(Interrupt::AES), + 70 => Ok(Interrupt::SHA), + 71 => Ok(Interrupt::ECC), + 74 => Ok(Interrupt::GPIO_INT0), + 75 => Ok(Interrupt::GPIO_INT1), + 76 => Ok(Interrupt::GPIO_INT2), + 77 => Ok(Interrupt::GPIO_INT3), + 78 => Ok(Interrupt::GPIO_PAD_COMP), + 83 => Ok(Interrupt::CACHE), + 85 => Ok(Interrupt::CSI_BRIDGE), + 86 => Ok(Interrupt::DSI_BRIDGE), + 87 => Ok(Interrupt::CSI), + 88 => Ok(Interrupt::DSI), + 95 => Ok(Interrupt::JPEG), + 96 => Ok(Interrupt::PPA), + 100 => Ok(Interrupt::ISP), + 101 => Ok(Interrupt::I3C), + 102 => Ok(Interrupt::I3C_SLV), + 110 => Ok(Interrupt::HP_SYS), + 111 => Ok(Interrupt::PCNT), + 112 => Ok(Interrupt::PAU), + 113 => Ok(Interrupt::PARLIO_RX), + 114 => Ok(Interrupt::PARLIO_TX), + 115 => Ok(Interrupt::H264_DMA2D_OUT_CH0), + 116 => Ok(Interrupt::H264_DMA2D_OUT_CH1), + 117 => Ok(Interrupt::H264_DMA2D_OUT_CH2), + 118 => Ok(Interrupt::H264_DMA2D_OUT_CH3), + 119 => Ok(Interrupt::H264_DMA2D_OUT_CH4), + 120 => Ok(Interrupt::H264_DMA2D_IN_CH0), + 121 => Ok(Interrupt::H264_DMA2D_IN_CH1), + 122 => Ok(Interrupt::H264_DMA2D_IN_CH2), + 123 => Ok(Interrupt::H264_DMA2D_IN_CH3), + 124 => Ok(Interrupt::H264_DMA2D_IN_CH4), + 125 => Ok(Interrupt::H264_DMA2D_IN_CH5), + 126 => Ok(Interrupt::H264_REG), + 127 => Ok(Interrupt::ASSIST_DEBUG), + _ => Err(TryFromInterruptError(())), + } + } +} +#[cfg(feature = "rt")] +#[macro_export] +#[doc = r" Assigns a handler to an interrupt"] +#[doc = r""] +#[doc = r" This macro takes two arguments: the name of an interrupt and the path to the"] +#[doc = r" function that will be used as the handler of that interrupt. That function"] +#[doc = r" must have signature `fn()`."] +#[doc = r""] +#[doc = r" Optionally, a third argument may be used to declare interrupt local data."] +#[doc = r" The handler will have exclusive access to these *local* variables on each"] +#[doc = r" invocation. If the third argument is used then the signature of the handler"] +#[doc = r" function must be `fn(&mut $NAME::Locals)` where `$NAME` is the first argument"] +#[doc = r" passed to the macro."] +#[doc = r""] +#[doc = r" # Example"] +#[doc = r""] +#[doc = r" ``` ignore"] +#[doc = r" interrupt!(TIM2, periodic);"] +#[doc = r""] +#[doc = r" fn periodic() {"] +#[doc = r#" print!(".");"#] +#[doc = r" }"] +#[doc = r""] +#[doc = r" interrupt!(TIM3, tick, locals: {"] +#[doc = r" tick: bool = false;"] +#[doc = r" });"] +#[doc = r""] +#[doc = r" fn tick(locals: &mut TIM3::Locals) {"] +#[doc = r" locals.tick = !locals.tick;"] +#[doc = r""] +#[doc = r" if locals.tick {"] +#[doc = r#" println!("Tick");"#] +#[doc = r" } else {"] +#[doc = r#" println!("Tock");"#] +#[doc = r" }"] +#[doc = r" }"] +#[doc = r" ```"] +macro_rules ! interrupt { ($ NAME : ident , $ path : path , locals : { $ ($ lvar : ident : $ lty : ty = $ lval : expr ;) * }) => { # [allow (non_snake_case)] mod $ NAME { pub struct Locals { $ (pub $ lvar : $ lty ,) * } } # [allow (non_snake_case)] # [no_mangle] pub extern "C" fn $ NAME () { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; static mut LOCALS : self :: $ NAME :: Locals = self :: $ NAME :: Locals { $ ($ lvar : $ lval ,) * } ; let f : fn (& mut self :: $ NAME :: Locals) = $ path ; f (unsafe { & mut LOCALS }) ; } } ; ($ NAME : ident , $ path : path) => { # [allow (non_snake_case)] # [no_mangle] pub extern "C" fn $ NAME () { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; let f : fn () = $ path ; f () ; } } } diff --git a/esp32p4/src/interrupt_core0.rs b/esp32p4/src/interrupt_core0.rs new file mode 100644 index 0000000000..064a8d256b --- /dev/null +++ b/esp32p4/src/interrupt_core0.rs @@ -0,0 +1,1375 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + lp_rtc_int_map: LP_RTC_INT_MAP, + lp_wdt_int_map: LP_WDT_INT_MAP, + lp_timer_reg_0_int_map: LP_TIMER_REG_0_INT_MAP, + lp_timer_reg_1_int_map: LP_TIMER_REG_1_INT_MAP, + mb_hp_int_map: MB_HP_INT_MAP, + mb_lp_int_map: MB_LP_INT_MAP, + pmu_reg_0_int_map: PMU_REG_0_INT_MAP, + pmu_reg_1_int_map: PMU_REG_1_INT_MAP, + lp_anaperi_int_map: LP_ANAPERI_INT_MAP, + lp_adc_int_map: LP_ADC_INT_MAP, + lp_gpio_int_map: LP_GPIO_INT_MAP, + lp_i2c_int_map: LP_I2C_INT_MAP, + lp_i2s_int_map: LP_I2S_INT_MAP, + lp_spi_int_map: LP_SPI_INT_MAP, + lp_touch_int_map: LP_TOUCH_INT_MAP, + lp_tsens_int_map: LP_TSENS_INT_MAP, + lp_uart_int_map: LP_UART_INT_MAP, + lp_efuse_int_map: LP_EFUSE_INT_MAP, + lp_sw_int_map: LP_SW_INT_MAP, + lp_sysreg_int_map: LP_SYSREG_INT_MAP, + lp_huk_int_map: LP_HUK_INT_MAP, + sys_icm_int_map: SYS_ICM_INT_MAP, + usb_device_int_map: USB_DEVICE_INT_MAP, + sdio_host_int_map: SDIO_HOST_INT_MAP, + gdma_int_map: GDMA_INT_MAP, + spi2_int_map: SPI2_INT_MAP, + spi3_int_map: SPI3_INT_MAP, + i2s0_int_map: I2S0_INT_MAP, + i2s1_int_map: I2S1_INT_MAP, + i2s2_int_map: I2S2_INT_MAP, + uhci0_int_map: UHCI0_INT_MAP, + uart0_int_map: UART0_INT_MAP, + uart1_int_map: UART1_INT_MAP, + uart2_int_map: UART2_INT_MAP, + uart3_int_map: UART3_INT_MAP, + uart4_int_map: UART4_INT_MAP, + lcd_cam_int_map: LCD_CAM_INT_MAP, + adc_int_map: ADC_INT_MAP, + pwm0_int_map: PWM0_INT_MAP, + pwm1_int_map: PWM1_INT_MAP, + can0_int_map: CAN0_INT_MAP, + can1_int_map: CAN1_INT_MAP, + can2_int_map: CAN2_INT_MAP, + rmt_int_map: RMT_INT_MAP, + i2c0_int_map: I2C0_INT_MAP, + i2c1_int_map: I2C1_INT_MAP, + timergrp0_t0_int_map: TIMERGRP0_T0_INT_MAP, + timergrp0_t1_int_map: TIMERGRP0_T1_INT_MAP, + timergrp0_wdt_int_map: TIMERGRP0_WDT_INT_MAP, + timergrp1_t0_int_map: TIMERGRP1_T0_INT_MAP, + timergrp1_t1_int_map: TIMERGRP1_T1_INT_MAP, + timergrp1_wdt_int_map: TIMERGRP1_WDT_INT_MAP, + ledc_int_map: LEDC_INT_MAP, + systimer_target0_int_map: SYSTIMER_TARGET0_INT_MAP, + systimer_target1_int_map: SYSTIMER_TARGET1_INT_MAP, + systimer_target2_int_map: SYSTIMER_TARGET2_INT_MAP, + ahb_pdma_in_ch0_int_map: AHB_PDMA_IN_CH0_INT_MAP, + ahb_pdma_in_ch1_int_map: AHB_PDMA_IN_CH1_INT_MAP, + ahb_pdma_in_ch2_int_map: AHB_PDMA_IN_CH2_INT_MAP, + ahb_pdma_out_ch0_int_map: AHB_PDMA_OUT_CH0_INT_MAP, + ahb_pdma_out_ch1_int_map: AHB_PDMA_OUT_CH1_INT_MAP, + ahb_pdma_out_ch2_int_map: AHB_PDMA_OUT_CH2_INT_MAP, + axi_pdma_in_ch0_int_map: AXI_PDMA_IN_CH0_INT_MAP, + axi_pdma_in_ch1_int_map: AXI_PDMA_IN_CH1_INT_MAP, + axi_pdma_in_ch2_int_map: AXI_PDMA_IN_CH2_INT_MAP, + axi_pdma_out_ch0_int_map: AXI_PDMA_OUT_CH0_INT_MAP, + axi_pdma_out_ch1_int_map: AXI_PDMA_OUT_CH1_INT_MAP, + axi_pdma_out_ch2_int_map: AXI_PDMA_OUT_CH2_INT_MAP, + rsa_int_map: RSA_INT_MAP, + aes_int_map: AES_INT_MAP, + sha_int_map: SHA_INT_MAP, + ecc_int_map: ECC_INT_MAP, + ecdsa_int_map: ECDSA_INT_MAP, + km_int_map: KM_INT_MAP, + gpio_int0_map: GPIO_INT0_MAP, + gpio_int1_map: GPIO_INT1_MAP, + gpio_int2_map: GPIO_INT2_MAP, + gpio_int3_map: GPIO_INT3_MAP, + gpio_pad_comp_int_map: GPIO_PAD_COMP_INT_MAP, + cpu_int_from_cpu_0_map: CPU_INT_FROM_CPU_0_MAP, + cpu_int_from_cpu_1_map: CPU_INT_FROM_CPU_1_MAP, + cpu_int_from_cpu_2_map: CPU_INT_FROM_CPU_2_MAP, + cpu_int_from_cpu_3_map: CPU_INT_FROM_CPU_3_MAP, + cache_int_map: CACHE_INT_MAP, + flash_mspi_int_map: FLASH_MSPI_INT_MAP, + csi_bridge_int_map: CSI_BRIDGE_INT_MAP, + dsi_bridge_int_map: DSI_BRIDGE_INT_MAP, + csi_int_map: CSI_INT_MAP, + dsi_int_map: DSI_INT_MAP, + gmii_phy_int_map: GMII_PHY_INT_MAP, + lpi_int_map: LPI_INT_MAP, + pmt_int_map: PMT_INT_MAP, + sbd_int_map: SBD_INT_MAP, + usb_otg_int_map: USB_OTG_INT_MAP, + usb_otg_endp_multi_proc_int_map: USB_OTG_ENDP_MULTI_PROC_INT_MAP, + jpeg_int_map: JPEG_INT_MAP, + ppa_int_map: PPA_INT_MAP, + core0_trace_int_map: CORE0_TRACE_INT_MAP, + core1_trace_int_map: CORE1_TRACE_INT_MAP, + hp_core_ctrl_int_map: HP_CORE_CTRL_INT_MAP, + isp_int_map: ISP_INT_MAP, + i3c_mst_int_map: I3C_MST_INT_MAP, + i3c_slv_int_map: I3C_SLV_INT_MAP, + usb_otg11_int_map: USB_OTG11_INT_MAP, + dma2d_in_ch0_int_map: DMA2D_IN_CH0_INT_MAP, + dma2d_in_ch1_int_map: DMA2D_IN_CH1_INT_MAP, + dma2d_out_ch0_int_map: DMA2D_OUT_CH0_INT_MAP, + dma2d_out_ch1_int_map: DMA2D_OUT_CH1_INT_MAP, + dma2d_out_ch2_int_map: DMA2D_OUT_CH2_INT_MAP, + psram_mspi_int_map: PSRAM_MSPI_INT_MAP, + hp_sysreg_int_map: HP_SYSREG_INT_MAP, + pcnt_int_map: PCNT_INT_MAP, + hp_pau_int_map: HP_PAU_INT_MAP, + hp_parlio_rx_int_map: HP_PARLIO_RX_INT_MAP, + hp_parlio_tx_int_map: HP_PARLIO_TX_INT_MAP, + h264_dma2d_out_ch0_int_map: H264_DMA2D_OUT_CH0_INT_MAP, + h264_dma2d_out_ch1_int_map: H264_DMA2D_OUT_CH1_INT_MAP, + h264_dma2d_out_ch2_int_map: H264_DMA2D_OUT_CH2_INT_MAP, + h264_dma2d_out_ch3_int_map: H264_DMA2D_OUT_CH3_INT_MAP, + h264_dma2d_out_ch4_int_map: H264_DMA2D_OUT_CH4_INT_MAP, + h264_dma2d_in_ch0_int_map: H264_DMA2D_IN_CH0_INT_MAP, + h264_dma2d_in_ch1_int_map: H264_DMA2D_IN_CH1_INT_MAP, + h264_dma2d_in_ch2_int_map: H264_DMA2D_IN_CH2_INT_MAP, + h264_dma2d_in_ch3_int_map: H264_DMA2D_IN_CH3_INT_MAP, + h264_dma2d_in_ch4_int_map: H264_DMA2D_IN_CH4_INT_MAP, + h264_dma2d_in_ch5_int_map: H264_DMA2D_IN_CH5_INT_MAP, + h264_reg_int_map: H264_REG_INT_MAP, + assist_debug_int_map: ASSIST_DEBUG_INT_MAP, + intr_status_reg_0: INTR_STATUS_REG_0, + intr_status_reg_1: INTR_STATUS_REG_1, + intr_status_reg_2: INTR_STATUS_REG_2, + intr_status_reg_3: INTR_STATUS_REG_3, + clock_gate: CLOCK_GATE, + _reserved133: [u8; 0x01e8], + interrupt_reg_date: INTERRUPT_REG_DATE, +} +impl RegisterBlock { + #[doc = "0x00 - NA"] + #[inline(always)] + pub const fn lp_rtc_int_map(&self) -> &LP_RTC_INT_MAP { + &self.lp_rtc_int_map + } + #[doc = "0x04 - NA"] + #[inline(always)] + pub const fn lp_wdt_int_map(&self) -> &LP_WDT_INT_MAP { + &self.lp_wdt_int_map + } + #[doc = "0x08 - NA"] + #[inline(always)] + pub const fn lp_timer_reg_0_int_map(&self) -> &LP_TIMER_REG_0_INT_MAP { + &self.lp_timer_reg_0_int_map + } + #[doc = "0x0c - NA"] + #[inline(always)] + pub const fn lp_timer_reg_1_int_map(&self) -> &LP_TIMER_REG_1_INT_MAP { + &self.lp_timer_reg_1_int_map + } + #[doc = "0x10 - NA"] + #[inline(always)] + pub const fn mb_hp_int_map(&self) -> &MB_HP_INT_MAP { + &self.mb_hp_int_map + } + #[doc = "0x14 - NA"] + #[inline(always)] + pub const fn mb_lp_int_map(&self) -> &MB_LP_INT_MAP { + &self.mb_lp_int_map + } + #[doc = "0x18 - NA"] + #[inline(always)] + pub const fn pmu_reg_0_int_map(&self) -> &PMU_REG_0_INT_MAP { + &self.pmu_reg_0_int_map + } + #[doc = "0x1c - NA"] + #[inline(always)] + pub const fn pmu_reg_1_int_map(&self) -> &PMU_REG_1_INT_MAP { + &self.pmu_reg_1_int_map + } + #[doc = "0x20 - NA"] + #[inline(always)] + pub const fn lp_anaperi_int_map(&self) -> &LP_ANAPERI_INT_MAP { + &self.lp_anaperi_int_map + } + #[doc = "0x24 - NA"] + #[inline(always)] + pub const fn lp_adc_int_map(&self) -> &LP_ADC_INT_MAP { + &self.lp_adc_int_map + } + #[doc = "0x28 - NA"] + #[inline(always)] + pub const fn lp_gpio_int_map(&self) -> &LP_GPIO_INT_MAP { + &self.lp_gpio_int_map + } + #[doc = "0x2c - NA"] + #[inline(always)] + pub const fn lp_i2c_int_map(&self) -> &LP_I2C_INT_MAP { + &self.lp_i2c_int_map + } + #[doc = "0x30 - NA"] + #[inline(always)] + pub const fn lp_i2s_int_map(&self) -> &LP_I2S_INT_MAP { + &self.lp_i2s_int_map + } + #[doc = "0x34 - NA"] + #[inline(always)] + pub const fn lp_spi_int_map(&self) -> &LP_SPI_INT_MAP { + &self.lp_spi_int_map + } + #[doc = "0x38 - NA"] + #[inline(always)] + pub const fn lp_touch_int_map(&self) -> &LP_TOUCH_INT_MAP { + &self.lp_touch_int_map + } + #[doc = "0x3c - NA"] + #[inline(always)] + pub const fn lp_tsens_int_map(&self) -> &LP_TSENS_INT_MAP { + &self.lp_tsens_int_map + } + #[doc = "0x40 - NA"] + #[inline(always)] + pub const fn lp_uart_int_map(&self) -> &LP_UART_INT_MAP { + &self.lp_uart_int_map + } + #[doc = "0x44 - NA"] + #[inline(always)] + pub const fn lp_efuse_int_map(&self) -> &LP_EFUSE_INT_MAP { + &self.lp_efuse_int_map + } + #[doc = "0x48 - NA"] + #[inline(always)] + pub const fn lp_sw_int_map(&self) -> &LP_SW_INT_MAP { + &self.lp_sw_int_map + } + #[doc = "0x4c - NA"] + #[inline(always)] + pub const fn lp_sysreg_int_map(&self) -> &LP_SYSREG_INT_MAP { + &self.lp_sysreg_int_map + } + #[doc = "0x50 - NA"] + #[inline(always)] + pub const fn lp_huk_int_map(&self) -> &LP_HUK_INT_MAP { + &self.lp_huk_int_map + } + #[doc = "0x54 - NA"] + #[inline(always)] + pub const fn sys_icm_int_map(&self) -> &SYS_ICM_INT_MAP { + &self.sys_icm_int_map + } + #[doc = "0x58 - NA"] + #[inline(always)] + pub const fn usb_device_int_map(&self) -> &USB_DEVICE_INT_MAP { + &self.usb_device_int_map + } + #[doc = "0x5c - NA"] + #[inline(always)] + pub const fn sdio_host_int_map(&self) -> &SDIO_HOST_INT_MAP { + &self.sdio_host_int_map + } + #[doc = "0x60 - NA"] + #[inline(always)] + pub const fn gdma_int_map(&self) -> &GDMA_INT_MAP { + &self.gdma_int_map + } + #[doc = "0x64 - NA"] + #[inline(always)] + pub const fn spi2_int_map(&self) -> &SPI2_INT_MAP { + &self.spi2_int_map + } + #[doc = "0x68 - NA"] + #[inline(always)] + pub const fn spi3_int_map(&self) -> &SPI3_INT_MAP { + &self.spi3_int_map + } + #[doc = "0x6c - NA"] + #[inline(always)] + pub const fn i2s0_int_map(&self) -> &I2S0_INT_MAP { + &self.i2s0_int_map + } + #[doc = "0x70 - NA"] + #[inline(always)] + pub const fn i2s1_int_map(&self) -> &I2S1_INT_MAP { + &self.i2s1_int_map + } + #[doc = "0x74 - NA"] + #[inline(always)] + pub const fn i2s2_int_map(&self) -> &I2S2_INT_MAP { + &self.i2s2_int_map + } + #[doc = "0x78 - NA"] + #[inline(always)] + pub const fn uhci0_int_map(&self) -> &UHCI0_INT_MAP { + &self.uhci0_int_map + } + #[doc = "0x7c - NA"] + #[inline(always)] + pub const fn uart0_int_map(&self) -> &UART0_INT_MAP { + &self.uart0_int_map + } + #[doc = "0x80 - NA"] + #[inline(always)] + pub const fn uart1_int_map(&self) -> &UART1_INT_MAP { + &self.uart1_int_map + } + #[doc = "0x84 - NA"] + #[inline(always)] + pub const fn uart2_int_map(&self) -> &UART2_INT_MAP { + &self.uart2_int_map + } + #[doc = "0x88 - NA"] + #[inline(always)] + pub const fn uart3_int_map(&self) -> &UART3_INT_MAP { + &self.uart3_int_map + } + #[doc = "0x8c - NA"] + #[inline(always)] + pub const fn uart4_int_map(&self) -> &UART4_INT_MAP { + &self.uart4_int_map + } + #[doc = "0x90 - NA"] + #[inline(always)] + pub const fn lcd_cam_int_map(&self) -> &LCD_CAM_INT_MAP { + &self.lcd_cam_int_map + } + #[doc = "0x94 - NA"] + #[inline(always)] + pub const fn adc_int_map(&self) -> &ADC_INT_MAP { + &self.adc_int_map + } + #[doc = "0x98 - NA"] + #[inline(always)] + pub const fn pwm0_int_map(&self) -> &PWM0_INT_MAP { + &self.pwm0_int_map + } + #[doc = "0x9c - NA"] + #[inline(always)] + pub const fn pwm1_int_map(&self) -> &PWM1_INT_MAP { + &self.pwm1_int_map + } + #[doc = "0xa0 - NA"] + #[inline(always)] + pub const fn can0_int_map(&self) -> &CAN0_INT_MAP { + &self.can0_int_map + } + #[doc = "0xa4 - NA"] + #[inline(always)] + pub const fn can1_int_map(&self) -> &CAN1_INT_MAP { + &self.can1_int_map + } + #[doc = "0xa8 - NA"] + #[inline(always)] + pub const fn can2_int_map(&self) -> &CAN2_INT_MAP { + &self.can2_int_map + } + #[doc = "0xac - NA"] + #[inline(always)] + pub const fn rmt_int_map(&self) -> &RMT_INT_MAP { + &self.rmt_int_map + } + #[doc = "0xb0 - NA"] + #[inline(always)] + pub const fn i2c0_int_map(&self) -> &I2C0_INT_MAP { + &self.i2c0_int_map + } + #[doc = "0xb4 - NA"] + #[inline(always)] + pub const fn i2c1_int_map(&self) -> &I2C1_INT_MAP { + &self.i2c1_int_map + } + #[doc = "0xb8 - NA"] + #[inline(always)] + pub const fn timergrp0_t0_int_map(&self) -> &TIMERGRP0_T0_INT_MAP { + &self.timergrp0_t0_int_map + } + #[doc = "0xbc - NA"] + #[inline(always)] + pub const fn timergrp0_t1_int_map(&self) -> &TIMERGRP0_T1_INT_MAP { + &self.timergrp0_t1_int_map + } + #[doc = "0xc0 - NA"] + #[inline(always)] + pub const fn timergrp0_wdt_int_map(&self) -> &TIMERGRP0_WDT_INT_MAP { + &self.timergrp0_wdt_int_map + } + #[doc = "0xc4 - NA"] + #[inline(always)] + pub const fn timergrp1_t0_int_map(&self) -> &TIMERGRP1_T0_INT_MAP { + &self.timergrp1_t0_int_map + } + #[doc = "0xc8 - NA"] + #[inline(always)] + pub const fn timergrp1_t1_int_map(&self) -> &TIMERGRP1_T1_INT_MAP { + &self.timergrp1_t1_int_map + } + #[doc = "0xcc - NA"] + #[inline(always)] + pub const fn timergrp1_wdt_int_map(&self) -> &TIMERGRP1_WDT_INT_MAP { + &self.timergrp1_wdt_int_map + } + #[doc = "0xd0 - NA"] + #[inline(always)] + pub const fn ledc_int_map(&self) -> &LEDC_INT_MAP { + &self.ledc_int_map + } + #[doc = "0xd4 - NA"] + #[inline(always)] + pub const fn systimer_target0_int_map(&self) -> &SYSTIMER_TARGET0_INT_MAP { + &self.systimer_target0_int_map + } + #[doc = "0xd8 - NA"] + #[inline(always)] + pub const fn systimer_target1_int_map(&self) -> &SYSTIMER_TARGET1_INT_MAP { + &self.systimer_target1_int_map + } + #[doc = "0xdc - NA"] + #[inline(always)] + pub const fn systimer_target2_int_map(&self) -> &SYSTIMER_TARGET2_INT_MAP { + &self.systimer_target2_int_map + } + #[doc = "0xe0 - NA"] + #[inline(always)] + pub const fn ahb_pdma_in_ch0_int_map(&self) -> &AHB_PDMA_IN_CH0_INT_MAP { + &self.ahb_pdma_in_ch0_int_map + } + #[doc = "0xe4 - NA"] + #[inline(always)] + pub const fn ahb_pdma_in_ch1_int_map(&self) -> &AHB_PDMA_IN_CH1_INT_MAP { + &self.ahb_pdma_in_ch1_int_map + } + #[doc = "0xe8 - NA"] + #[inline(always)] + pub const fn ahb_pdma_in_ch2_int_map(&self) -> &AHB_PDMA_IN_CH2_INT_MAP { + &self.ahb_pdma_in_ch2_int_map + } + #[doc = "0xec - NA"] + #[inline(always)] + pub const fn ahb_pdma_out_ch0_int_map(&self) -> &AHB_PDMA_OUT_CH0_INT_MAP { + &self.ahb_pdma_out_ch0_int_map + } + #[doc = "0xf0 - NA"] + #[inline(always)] + pub const fn ahb_pdma_out_ch1_int_map(&self) -> &AHB_PDMA_OUT_CH1_INT_MAP { + &self.ahb_pdma_out_ch1_int_map + } + #[doc = "0xf4 - NA"] + #[inline(always)] + pub const fn ahb_pdma_out_ch2_int_map(&self) -> &AHB_PDMA_OUT_CH2_INT_MAP { + &self.ahb_pdma_out_ch2_int_map + } + #[doc = "0xf8 - NA"] + #[inline(always)] + pub const fn axi_pdma_in_ch0_int_map(&self) -> &AXI_PDMA_IN_CH0_INT_MAP { + &self.axi_pdma_in_ch0_int_map + } + #[doc = "0xfc - NA"] + #[inline(always)] + pub const fn axi_pdma_in_ch1_int_map(&self) -> &AXI_PDMA_IN_CH1_INT_MAP { + &self.axi_pdma_in_ch1_int_map + } + #[doc = "0x100 - NA"] + #[inline(always)] + pub const fn axi_pdma_in_ch2_int_map(&self) -> &AXI_PDMA_IN_CH2_INT_MAP { + &self.axi_pdma_in_ch2_int_map + } + #[doc = "0x104 - NA"] + #[inline(always)] + pub const fn axi_pdma_out_ch0_int_map(&self) -> &AXI_PDMA_OUT_CH0_INT_MAP { + &self.axi_pdma_out_ch0_int_map + } + #[doc = "0x108 - NA"] + #[inline(always)] + pub const fn axi_pdma_out_ch1_int_map(&self) -> &AXI_PDMA_OUT_CH1_INT_MAP { + &self.axi_pdma_out_ch1_int_map + } + #[doc = "0x10c - NA"] + #[inline(always)] + pub const fn axi_pdma_out_ch2_int_map(&self) -> &AXI_PDMA_OUT_CH2_INT_MAP { + &self.axi_pdma_out_ch2_int_map + } + #[doc = "0x110 - NA"] + #[inline(always)] + pub const fn rsa_int_map(&self) -> &RSA_INT_MAP { + &self.rsa_int_map + } + #[doc = "0x114 - NA"] + #[inline(always)] + pub const fn aes_int_map(&self) -> &AES_INT_MAP { + &self.aes_int_map + } + #[doc = "0x118 - NA"] + #[inline(always)] + pub const fn sha_int_map(&self) -> &SHA_INT_MAP { + &self.sha_int_map + } + #[doc = "0x11c - NA"] + #[inline(always)] + pub const fn ecc_int_map(&self) -> &ECC_INT_MAP { + &self.ecc_int_map + } + #[doc = "0x120 - NA"] + #[inline(always)] + pub const fn ecdsa_int_map(&self) -> &ECDSA_INT_MAP { + &self.ecdsa_int_map + } + #[doc = "0x124 - NA"] + #[inline(always)] + pub const fn km_int_map(&self) -> &KM_INT_MAP { + &self.km_int_map + } + #[doc = "0x128 - NA"] + #[inline(always)] + pub const fn gpio_int0_map(&self) -> &GPIO_INT0_MAP { + &self.gpio_int0_map + } + #[doc = "0x12c - NA"] + #[inline(always)] + pub const fn gpio_int1_map(&self) -> &GPIO_INT1_MAP { + &self.gpio_int1_map + } + #[doc = "0x130 - NA"] + #[inline(always)] + pub const fn gpio_int2_map(&self) -> &GPIO_INT2_MAP { + &self.gpio_int2_map + } + #[doc = "0x134 - NA"] + #[inline(always)] + pub const fn gpio_int3_map(&self) -> &GPIO_INT3_MAP { + &self.gpio_int3_map + } + #[doc = "0x138 - NA"] + #[inline(always)] + pub const fn gpio_pad_comp_int_map(&self) -> &GPIO_PAD_COMP_INT_MAP { + &self.gpio_pad_comp_int_map + } + #[doc = "0x13c - NA"] + #[inline(always)] + pub const fn cpu_int_from_cpu_0_map(&self) -> &CPU_INT_FROM_CPU_0_MAP { + &self.cpu_int_from_cpu_0_map + } + #[doc = "0x140 - NA"] + #[inline(always)] + pub const fn cpu_int_from_cpu_1_map(&self) -> &CPU_INT_FROM_CPU_1_MAP { + &self.cpu_int_from_cpu_1_map + } + #[doc = "0x144 - NA"] + #[inline(always)] + pub const fn cpu_int_from_cpu_2_map(&self) -> &CPU_INT_FROM_CPU_2_MAP { + &self.cpu_int_from_cpu_2_map + } + #[doc = "0x148 - NA"] + #[inline(always)] + pub const fn cpu_int_from_cpu_3_map(&self) -> &CPU_INT_FROM_CPU_3_MAP { + &self.cpu_int_from_cpu_3_map + } + #[doc = "0x14c - NA"] + #[inline(always)] + pub const fn cache_int_map(&self) -> &CACHE_INT_MAP { + &self.cache_int_map + } + #[doc = "0x150 - NA"] + #[inline(always)] + pub const fn flash_mspi_int_map(&self) -> &FLASH_MSPI_INT_MAP { + &self.flash_mspi_int_map + } + #[doc = "0x154 - NA"] + #[inline(always)] + pub const fn csi_bridge_int_map(&self) -> &CSI_BRIDGE_INT_MAP { + &self.csi_bridge_int_map + } + #[doc = "0x158 - NA"] + #[inline(always)] + pub const fn dsi_bridge_int_map(&self) -> &DSI_BRIDGE_INT_MAP { + &self.dsi_bridge_int_map + } + #[doc = "0x15c - NA"] + #[inline(always)] + pub const fn csi_int_map(&self) -> &CSI_INT_MAP { + &self.csi_int_map + } + #[doc = "0x160 - NA"] + #[inline(always)] + pub const fn dsi_int_map(&self) -> &DSI_INT_MAP { + &self.dsi_int_map + } + #[doc = "0x164 - NA"] + #[inline(always)] + pub const fn gmii_phy_int_map(&self) -> &GMII_PHY_INT_MAP { + &self.gmii_phy_int_map + } + #[doc = "0x168 - NA"] + #[inline(always)] + pub const fn lpi_int_map(&self) -> &LPI_INT_MAP { + &self.lpi_int_map + } + #[doc = "0x16c - NA"] + #[inline(always)] + pub const fn pmt_int_map(&self) -> &PMT_INT_MAP { + &self.pmt_int_map + } + #[doc = "0x170 - NA"] + #[inline(always)] + pub const fn sbd_int_map(&self) -> &SBD_INT_MAP { + &self.sbd_int_map + } + #[doc = "0x174 - NA"] + #[inline(always)] + pub const fn usb_otg_int_map(&self) -> &USB_OTG_INT_MAP { + &self.usb_otg_int_map + } + #[doc = "0x178 - NA"] + #[inline(always)] + pub const fn usb_otg_endp_multi_proc_int_map(&self) -> &USB_OTG_ENDP_MULTI_PROC_INT_MAP { + &self.usb_otg_endp_multi_proc_int_map + } + #[doc = "0x17c - NA"] + #[inline(always)] + pub const fn jpeg_int_map(&self) -> &JPEG_INT_MAP { + &self.jpeg_int_map + } + #[doc = "0x180 - NA"] + #[inline(always)] + pub const fn ppa_int_map(&self) -> &PPA_INT_MAP { + &self.ppa_int_map + } + #[doc = "0x184 - NA"] + #[inline(always)] + pub const fn core0_trace_int_map(&self) -> &CORE0_TRACE_INT_MAP { + &self.core0_trace_int_map + } + #[doc = "0x188 - NA"] + #[inline(always)] + pub const fn core1_trace_int_map(&self) -> &CORE1_TRACE_INT_MAP { + &self.core1_trace_int_map + } + #[doc = "0x18c - NA"] + #[inline(always)] + pub const fn hp_core_ctrl_int_map(&self) -> &HP_CORE_CTRL_INT_MAP { + &self.hp_core_ctrl_int_map + } + #[doc = "0x190 - NA"] + #[inline(always)] + pub const fn isp_int_map(&self) -> &ISP_INT_MAP { + &self.isp_int_map + } + #[doc = "0x194 - NA"] + #[inline(always)] + pub const fn i3c_mst_int_map(&self) -> &I3C_MST_INT_MAP { + &self.i3c_mst_int_map + } + #[doc = "0x198 - NA"] + #[inline(always)] + pub const fn i3c_slv_int_map(&self) -> &I3C_SLV_INT_MAP { + &self.i3c_slv_int_map + } + #[doc = "0x19c - NA"] + #[inline(always)] + pub const fn usb_otg11_int_map(&self) -> &USB_OTG11_INT_MAP { + &self.usb_otg11_int_map + } + #[doc = "0x1a0 - NA"] + #[inline(always)] + pub const fn dma2d_in_ch0_int_map(&self) -> &DMA2D_IN_CH0_INT_MAP { + &self.dma2d_in_ch0_int_map + } + #[doc = "0x1a4 - NA"] + #[inline(always)] + pub const fn dma2d_in_ch1_int_map(&self) -> &DMA2D_IN_CH1_INT_MAP { + &self.dma2d_in_ch1_int_map + } + #[doc = "0x1a8 - NA"] + #[inline(always)] + pub const fn dma2d_out_ch0_int_map(&self) -> &DMA2D_OUT_CH0_INT_MAP { + &self.dma2d_out_ch0_int_map + } + #[doc = "0x1ac - NA"] + #[inline(always)] + pub const fn dma2d_out_ch1_int_map(&self) -> &DMA2D_OUT_CH1_INT_MAP { + &self.dma2d_out_ch1_int_map + } + #[doc = "0x1b0 - NA"] + #[inline(always)] + pub const fn dma2d_out_ch2_int_map(&self) -> &DMA2D_OUT_CH2_INT_MAP { + &self.dma2d_out_ch2_int_map + } + #[doc = "0x1b4 - NA"] + #[inline(always)] + pub const fn psram_mspi_int_map(&self) -> &PSRAM_MSPI_INT_MAP { + &self.psram_mspi_int_map + } + #[doc = "0x1b8 - NA"] + #[inline(always)] + pub const fn hp_sysreg_int_map(&self) -> &HP_SYSREG_INT_MAP { + &self.hp_sysreg_int_map + } + #[doc = "0x1bc - NA"] + #[inline(always)] + pub const fn pcnt_int_map(&self) -> &PCNT_INT_MAP { + &self.pcnt_int_map + } + #[doc = "0x1c0 - NA"] + #[inline(always)] + pub const fn hp_pau_int_map(&self) -> &HP_PAU_INT_MAP { + &self.hp_pau_int_map + } + #[doc = "0x1c4 - NA"] + #[inline(always)] + pub const fn hp_parlio_rx_int_map(&self) -> &HP_PARLIO_RX_INT_MAP { + &self.hp_parlio_rx_int_map + } + #[doc = "0x1c8 - NA"] + #[inline(always)] + pub const fn hp_parlio_tx_int_map(&self) -> &HP_PARLIO_TX_INT_MAP { + &self.hp_parlio_tx_int_map + } + #[doc = "0x1cc - NA"] + #[inline(always)] + pub const fn h264_dma2d_out_ch0_int_map(&self) -> &H264_DMA2D_OUT_CH0_INT_MAP { + &self.h264_dma2d_out_ch0_int_map + } + #[doc = "0x1d0 - NA"] + #[inline(always)] + pub const fn h264_dma2d_out_ch1_int_map(&self) -> &H264_DMA2D_OUT_CH1_INT_MAP { + &self.h264_dma2d_out_ch1_int_map + } + #[doc = "0x1d4 - NA"] + #[inline(always)] + pub const fn h264_dma2d_out_ch2_int_map(&self) -> &H264_DMA2D_OUT_CH2_INT_MAP { + &self.h264_dma2d_out_ch2_int_map + } + #[doc = "0x1d8 - NA"] + #[inline(always)] + pub const fn h264_dma2d_out_ch3_int_map(&self) -> &H264_DMA2D_OUT_CH3_INT_MAP { + &self.h264_dma2d_out_ch3_int_map + } + #[doc = "0x1dc - NA"] + #[inline(always)] + pub const fn h264_dma2d_out_ch4_int_map(&self) -> &H264_DMA2D_OUT_CH4_INT_MAP { + &self.h264_dma2d_out_ch4_int_map + } + #[doc = "0x1e0 - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch0_int_map(&self) -> &H264_DMA2D_IN_CH0_INT_MAP { + &self.h264_dma2d_in_ch0_int_map + } + #[doc = "0x1e4 - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch1_int_map(&self) -> &H264_DMA2D_IN_CH1_INT_MAP { + &self.h264_dma2d_in_ch1_int_map + } + #[doc = "0x1e8 - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch2_int_map(&self) -> &H264_DMA2D_IN_CH2_INT_MAP { + &self.h264_dma2d_in_ch2_int_map + } + #[doc = "0x1ec - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch3_int_map(&self) -> &H264_DMA2D_IN_CH3_INT_MAP { + &self.h264_dma2d_in_ch3_int_map + } + #[doc = "0x1f0 - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch4_int_map(&self) -> &H264_DMA2D_IN_CH4_INT_MAP { + &self.h264_dma2d_in_ch4_int_map + } + #[doc = "0x1f4 - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch5_int_map(&self) -> &H264_DMA2D_IN_CH5_INT_MAP { + &self.h264_dma2d_in_ch5_int_map + } + #[doc = "0x1f8 - NA"] + #[inline(always)] + pub const fn h264_reg_int_map(&self) -> &H264_REG_INT_MAP { + &self.h264_reg_int_map + } + #[doc = "0x1fc - NA"] + #[inline(always)] + pub const fn assist_debug_int_map(&self) -> &ASSIST_DEBUG_INT_MAP { + &self.assist_debug_int_map + } + #[doc = "0x200 - NA"] + #[inline(always)] + pub const fn intr_status_reg_0(&self) -> &INTR_STATUS_REG_0 { + &self.intr_status_reg_0 + } + #[doc = "0x204 - NA"] + #[inline(always)] + pub const fn intr_status_reg_1(&self) -> &INTR_STATUS_REG_1 { + &self.intr_status_reg_1 + } + #[doc = "0x208 - NA"] + #[inline(always)] + pub const fn intr_status_reg_2(&self) -> &INTR_STATUS_REG_2 { + &self.intr_status_reg_2 + } + #[doc = "0x20c - NA"] + #[inline(always)] + pub const fn intr_status_reg_3(&self) -> &INTR_STATUS_REG_3 { + &self.intr_status_reg_3 + } + #[doc = "0x210 - NA"] + #[inline(always)] + pub const fn clock_gate(&self) -> &CLOCK_GATE { + &self.clock_gate + } + #[doc = "0x3fc - NA"] + #[inline(always)] + pub const fn interrupt_reg_date(&self) -> &INTERRUPT_REG_DATE { + &self.interrupt_reg_date + } +} +#[doc = "LP_RTC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_rtc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_rtc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_rtc_int_map`] module"] +pub type LP_RTC_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_rtc_int_map; +#[doc = "LP_WDT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_wdt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_wdt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_wdt_int_map`] module"] +pub type LP_WDT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_wdt_int_map; +#[doc = "LP_TIMER_REG_0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timer_reg_0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timer_reg_0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_timer_reg_0_int_map`] module"] +pub type LP_TIMER_REG_0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_timer_reg_0_int_map; +#[doc = "LP_TIMER_REG_1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timer_reg_1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timer_reg_1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_timer_reg_1_int_map`] module"] +pub type LP_TIMER_REG_1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_timer_reg_1_int_map; +#[doc = "MB_HP_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mb_hp_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mb_hp_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_hp_int_map`] module"] +pub type MB_HP_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod mb_hp_int_map; +#[doc = "MB_LP_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mb_lp_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mb_lp_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_lp_int_map`] module"] +pub type MB_LP_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod mb_lp_int_map; +#[doc = "PMU_REG_0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_reg_0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_reg_0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmu_reg_0_int_map`] module"] +pub type PMU_REG_0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pmu_reg_0_int_map; +#[doc = "PMU_REG_1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_reg_1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_reg_1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmu_reg_1_int_map`] module"] +pub type PMU_REG_1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pmu_reg_1_int_map; +#[doc = "LP_ANAPERI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_anaperi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_anaperi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_anaperi_int_map`] module"] +pub type LP_ANAPERI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_anaperi_int_map; +#[doc = "LP_ADC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_adc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_adc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_adc_int_map`] module"] +pub type LP_ADC_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_adc_int_map; +#[doc = "LP_GPIO_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_gpio_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_gpio_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_gpio_int_map`] module"] +pub type LP_GPIO_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_gpio_int_map; +#[doc = "LP_I2C_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2c_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2c_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_i2c_int_map`] module"] +pub type LP_I2C_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_i2c_int_map; +#[doc = "LP_I2S_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_i2s_int_map`] module"] +pub type LP_I2S_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_i2s_int_map; +#[doc = "LP_SPI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_spi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_spi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_spi_int_map`] module"] +pub type LP_SPI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_spi_int_map; +#[doc = "LP_TOUCH_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_touch_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_touch_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_touch_int_map`] module"] +pub type LP_TOUCH_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_touch_int_map; +#[doc = "LP_TSENS_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tsens_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tsens_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_tsens_int_map`] module"] +pub type LP_TSENS_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_tsens_int_map; +#[doc = "LP_UART_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_uart_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_uart_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_uart_int_map`] module"] +pub type LP_UART_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_uart_int_map; +#[doc = "LP_EFUSE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_efuse_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_efuse_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_efuse_int_map`] module"] +pub type LP_EFUSE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_efuse_int_map; +#[doc = "LP_SW_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sw_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sw_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sw_int_map`] module"] +pub type LP_SW_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_sw_int_map; +#[doc = "LP_SYSREG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sysreg_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sysreg_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sysreg_int_map`] module"] +pub type LP_SYSREG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_sysreg_int_map; +#[doc = "LP_HUK_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_huk_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_huk_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_huk_int_map`] module"] +pub type LP_HUK_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_huk_int_map; +#[doc = "SYS_ICM_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_icm_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_icm_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_icm_int_map`] module"] +pub type SYS_ICM_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod sys_icm_int_map; +#[doc = "USB_DEVICE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_device_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_device_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb_device_int_map`] module"] +pub type USB_DEVICE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod usb_device_int_map; +#[doc = "SDIO_HOST_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdio_host_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdio_host_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdio_host_int_map`] module"] +pub type SDIO_HOST_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod sdio_host_int_map; +#[doc = "GDMA_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdma_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdma_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gdma_int_map`] module"] +pub type GDMA_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod gdma_int_map; +#[doc = "SPI2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi2_int_map`] module"] +pub type SPI2_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod spi2_int_map; +#[doc = "SPI3_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi3_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi3_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi3_int_map`] module"] +pub type SPI3_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod spi3_int_map; +#[doc = "I2S0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s0_int_map`] module"] +pub type I2S0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i2s0_int_map; +#[doc = "I2S1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s1_int_map`] module"] +pub type I2S1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i2s1_int_map; +#[doc = "I2S2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s2_int_map`] module"] +pub type I2S2_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i2s2_int_map; +#[doc = "UHCI0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uhci0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uhci0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uhci0_int_map`] module"] +pub type UHCI0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uhci0_int_map; +#[doc = "UART0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_int_map`] module"] +pub type UART0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uart0_int_map; +#[doc = "UART1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_int_map`] module"] +pub type UART1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uart1_int_map; +#[doc = "UART2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart2_int_map`] module"] +pub type UART2_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uart2_int_map; +#[doc = "UART3_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart3_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart3_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart3_int_map`] module"] +pub type UART3_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uart3_int_map; +#[doc = "UART4_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart4_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart4_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart4_int_map`] module"] +pub type UART4_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uart4_int_map; +#[doc = "LCD_CAM_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_cam_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_cam_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_cam_int_map`] module"] +pub type LCD_CAM_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lcd_cam_int_map; +#[doc = "ADC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc_int_map`] module"] +pub type ADC_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod adc_int_map; +#[doc = "PWM0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm0_int_map`] module"] +pub type PWM0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pwm0_int_map; +#[doc = "PWM1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm1_int_map`] module"] +pub type PWM1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pwm1_int_map; +#[doc = "CAN0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@can0_int_map`] module"] +pub type CAN0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod can0_int_map; +#[doc = "CAN1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@can1_int_map`] module"] +pub type CAN1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod can1_int_map; +#[doc = "CAN2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@can2_int_map`] module"] +pub type CAN2_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod can2_int_map; +#[doc = "RMT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rmt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rmt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rmt_int_map`] module"] +pub type RMT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod rmt_int_map; +#[doc = "I2C0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c0_int_map`] module"] +pub type I2C0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i2c0_int_map; +#[doc = "I2C1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c1_int_map`] module"] +pub type I2C1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i2c1_int_map; +#[doc = "TIMERGRP0_T0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_t0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_t0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp0_t0_int_map`] module"] +pub type TIMERGRP0_T0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp0_t0_int_map; +#[doc = "TIMERGRP0_T1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_t1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_t1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp0_t1_int_map`] module"] +pub type TIMERGRP0_T1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp0_t1_int_map; +#[doc = "TIMERGRP0_WDT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_wdt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_wdt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp0_wdt_int_map`] module"] +pub type TIMERGRP0_WDT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp0_wdt_int_map; +#[doc = "TIMERGRP1_T0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_t0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_t0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp1_t0_int_map`] module"] +pub type TIMERGRP1_T0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp1_t0_int_map; +#[doc = "TIMERGRP1_T1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_t1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_t1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp1_t1_int_map`] module"] +pub type TIMERGRP1_T1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp1_t1_int_map; +#[doc = "TIMERGRP1_WDT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_wdt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_wdt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp1_wdt_int_map`] module"] +pub type TIMERGRP1_WDT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp1_wdt_int_map; +#[doc = "LEDC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ledc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ledc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ledc_int_map`] module"] +pub type LEDC_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod ledc_int_map; +#[doc = "SYSTIMER_TARGET0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systimer_target0_int_map`] module"] +pub type SYSTIMER_TARGET0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod systimer_target0_int_map; +#[doc = "SYSTIMER_TARGET1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systimer_target1_int_map`] module"] +pub type SYSTIMER_TARGET1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod systimer_target1_int_map; +#[doc = "SYSTIMER_TARGET2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systimer_target2_int_map`] module"] +pub type SYSTIMER_TARGET2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod systimer_target2_int_map; +#[doc = "AHB_PDMA_IN_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_in_ch0_int_map`] module"] +pub type AHB_PDMA_IN_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_in_ch0_int_map; +#[doc = "AHB_PDMA_IN_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_in_ch1_int_map`] module"] +pub type AHB_PDMA_IN_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_in_ch1_int_map; +#[doc = "AHB_PDMA_IN_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_in_ch2_int_map`] module"] +pub type AHB_PDMA_IN_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_in_ch2_int_map; +#[doc = "AHB_PDMA_OUT_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_out_ch0_int_map`] module"] +pub type AHB_PDMA_OUT_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_out_ch0_int_map; +#[doc = "AHB_PDMA_OUT_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_out_ch1_int_map`] module"] +pub type AHB_PDMA_OUT_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_out_ch1_int_map; +#[doc = "AHB_PDMA_OUT_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_out_ch2_int_map`] module"] +pub type AHB_PDMA_OUT_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_out_ch2_int_map; +#[doc = "AXI_PDMA_IN_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_in_ch0_int_map`] module"] +pub type AXI_PDMA_IN_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_in_ch0_int_map; +#[doc = "AXI_PDMA_IN_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_in_ch1_int_map`] module"] +pub type AXI_PDMA_IN_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_in_ch1_int_map; +#[doc = "AXI_PDMA_IN_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_in_ch2_int_map`] module"] +pub type AXI_PDMA_IN_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_in_ch2_int_map; +#[doc = "AXI_PDMA_OUT_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_out_ch0_int_map`] module"] +pub type AXI_PDMA_OUT_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_out_ch0_int_map; +#[doc = "AXI_PDMA_OUT_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_out_ch1_int_map`] module"] +pub type AXI_PDMA_OUT_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_out_ch1_int_map; +#[doc = "AXI_PDMA_OUT_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_out_ch2_int_map`] module"] +pub type AXI_PDMA_OUT_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_out_ch2_int_map; +#[doc = "RSA_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsa_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsa_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsa_int_map`] module"] +pub type RSA_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod rsa_int_map; +#[doc = "AES_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aes_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aes_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aes_int_map`] module"] +pub type AES_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod aes_int_map; +#[doc = "SHA_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sha_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sha_int_map`] module"] +pub type SHA_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod sha_int_map; +#[doc = "ECC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecc_int_map`] module"] +pub type ECC_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod ecc_int_map; +#[doc = "ECDSA_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecdsa_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecdsa_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecdsa_int_map`] module"] +pub type ECDSA_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod ecdsa_int_map; +#[doc = "KM_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`km_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`km_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@km_int_map`] module"] +pub type KM_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod km_int_map; +#[doc = "GPIO_INT0_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int0_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int0_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int0_map`] module"] +pub type GPIO_INT0_MAP = crate::Reg; +#[doc = "NA"] +pub mod gpio_int0_map; +#[doc = "GPIO_INT1_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int1_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int1_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int1_map`] module"] +pub type GPIO_INT1_MAP = crate::Reg; +#[doc = "NA"] +pub mod gpio_int1_map; +#[doc = "GPIO_INT2_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int2_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int2_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int2_map`] module"] +pub type GPIO_INT2_MAP = crate::Reg; +#[doc = "NA"] +pub mod gpio_int2_map; +#[doc = "GPIO_INT3_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int3_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int3_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int3_map`] module"] +pub type GPIO_INT3_MAP = crate::Reg; +#[doc = "NA"] +pub mod gpio_int3_map; +#[doc = "GPIO_PAD_COMP_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pad_comp_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pad_comp_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pad_comp_int_map`] module"] +pub type GPIO_PAD_COMP_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod gpio_pad_comp_int_map; +#[doc = "CPU_INT_FROM_CPU_0_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_0_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_0_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_from_cpu_0_map`] module"] +pub type CPU_INT_FROM_CPU_0_MAP = crate::Reg; +#[doc = "NA"] +pub mod cpu_int_from_cpu_0_map; +#[doc = "CPU_INT_FROM_CPU_1_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_1_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_1_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_from_cpu_1_map`] module"] +pub type CPU_INT_FROM_CPU_1_MAP = crate::Reg; +#[doc = "NA"] +pub mod cpu_int_from_cpu_1_map; +#[doc = "CPU_INT_FROM_CPU_2_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_2_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_2_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_from_cpu_2_map`] module"] +pub type CPU_INT_FROM_CPU_2_MAP = crate::Reg; +#[doc = "NA"] +pub mod cpu_int_from_cpu_2_map; +#[doc = "CPU_INT_FROM_CPU_3_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_3_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_3_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_from_cpu_3_map`] module"] +pub type CPU_INT_FROM_CPU_3_MAP = crate::Reg; +#[doc = "NA"] +pub mod cpu_int_from_cpu_3_map; +#[doc = "CACHE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cache_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_int_map`] module"] +pub type CACHE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod cache_int_map; +#[doc = "FLASH_MSPI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flash_mspi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flash_mspi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_mspi_int_map`] module"] +pub type FLASH_MSPI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod flash_mspi_int_map; +#[doc = "CSI_BRIDGE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_bridge_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_bridge_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csi_bridge_int_map`] module"] +pub type CSI_BRIDGE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod csi_bridge_int_map; +#[doc = "DSI_BRIDGE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsi_bridge_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsi_bridge_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsi_bridge_int_map`] module"] +pub type DSI_BRIDGE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dsi_bridge_int_map; +#[doc = "CSI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csi_int_map`] module"] +pub type CSI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod csi_int_map; +#[doc = "DSI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsi_int_map`] module"] +pub type DSI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dsi_int_map; +#[doc = "GMII_PHY_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmii_phy_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmii_phy_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmii_phy_int_map`] module"] +pub type GMII_PHY_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod gmii_phy_int_map; +#[doc = "LPI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi_int_map`] module"] +pub type LPI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lpi_int_map; +#[doc = "PMT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmt_int_map`] module"] +pub type PMT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pmt_int_map; +#[doc = "SBD_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbd_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbd_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbd_int_map`] module"] +pub type SBD_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod sbd_int_map; +#[doc = "USB_OTG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb_otg_int_map`] module"] +pub type USB_OTG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod usb_otg_int_map; +#[doc = "USB_OTG_ENDP_MULTI_PROC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg_endp_multi_proc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg_endp_multi_proc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb_otg_endp_multi_proc_int_map`] module"] +pub type USB_OTG_ENDP_MULTI_PROC_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod usb_otg_endp_multi_proc_int_map; +#[doc = "JPEG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`jpeg_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`jpeg_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jpeg_int_map`] module"] +pub type JPEG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod jpeg_int_map; +#[doc = "PPA_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppa_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppa_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ppa_int_map`] module"] +pub type PPA_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod ppa_int_map; +#[doc = "CORE0_TRACE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_trace_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core0_trace_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core0_trace_int_map`] module"] +pub type CORE0_TRACE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod core0_trace_int_map; +#[doc = "CORE1_TRACE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core1_trace_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core1_trace_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core1_trace_int_map`] module"] +pub type CORE1_TRACE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod core1_trace_int_map; +#[doc = "HP_CORE_CTRL_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_ctrl_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_ctrl_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_core_ctrl_int_map`] module"] +pub type HP_CORE_CTRL_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod hp_core_ctrl_int_map; +#[doc = "ISP_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isp_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isp_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isp_int_map`] module"] +pub type ISP_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod isp_int_map; +#[doc = "I3C_MST_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i3c_mst_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i3c_mst_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i3c_mst_int_map`] module"] +pub type I3C_MST_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i3c_mst_int_map; +#[doc = "I3C_SLV_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i3c_slv_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i3c_slv_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i3c_slv_int_map`] module"] +pub type I3C_SLV_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i3c_slv_int_map; +#[doc = "USB_OTG11_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg11_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg11_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb_otg11_int_map`] module"] +pub type USB_OTG11_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod usb_otg11_int_map; +#[doc = "DMA2D_IN_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_in_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_in_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2d_in_ch0_int_map`] module"] +pub type DMA2D_IN_CH0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dma2d_in_ch0_int_map; +#[doc = "DMA2D_IN_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_in_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_in_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2d_in_ch1_int_map`] module"] +pub type DMA2D_IN_CH1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dma2d_in_ch1_int_map; +#[doc = "DMA2D_OUT_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2d_out_ch0_int_map`] module"] +pub type DMA2D_OUT_CH0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dma2d_out_ch0_int_map; +#[doc = "DMA2D_OUT_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2d_out_ch1_int_map`] module"] +pub type DMA2D_OUT_CH1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dma2d_out_ch1_int_map; +#[doc = "DMA2D_OUT_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2d_out_ch2_int_map`] module"] +pub type DMA2D_OUT_CH2_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dma2d_out_ch2_int_map; +#[doc = "PSRAM_MSPI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psram_mspi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psram_mspi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psram_mspi_int_map`] module"] +pub type PSRAM_MSPI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod psram_mspi_int_map; +#[doc = "HP_SYSREG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sysreg_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sysreg_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sysreg_int_map`] module"] +pub type HP_SYSREG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod hp_sysreg_int_map; +#[doc = "PCNT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcnt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcnt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcnt_int_map`] module"] +pub type PCNT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pcnt_int_map; +#[doc = "HP_PAU_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_pau_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_pau_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_pau_int_map`] module"] +pub type HP_PAU_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod hp_pau_int_map; +#[doc = "HP_PARLIO_RX_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_parlio_rx_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_parlio_rx_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_parlio_rx_int_map`] module"] +pub type HP_PARLIO_RX_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod hp_parlio_rx_int_map; +#[doc = "HP_PARLIO_TX_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_parlio_tx_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_parlio_tx_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_parlio_tx_int_map`] module"] +pub type HP_PARLIO_TX_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod hp_parlio_tx_int_map; +#[doc = "H264_DMA2D_OUT_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_out_ch0_int_map`] module"] +pub type H264_DMA2D_OUT_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_out_ch0_int_map; +#[doc = "H264_DMA2D_OUT_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_out_ch1_int_map`] module"] +pub type H264_DMA2D_OUT_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_out_ch1_int_map; +#[doc = "H264_DMA2D_OUT_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_out_ch2_int_map`] module"] +pub type H264_DMA2D_OUT_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_out_ch2_int_map; +#[doc = "H264_DMA2D_OUT_CH3_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch3_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch3_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_out_ch3_int_map`] module"] +pub type H264_DMA2D_OUT_CH3_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_out_ch3_int_map; +#[doc = "H264_DMA2D_OUT_CH4_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch4_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch4_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_out_ch4_int_map`] module"] +pub type H264_DMA2D_OUT_CH4_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_out_ch4_int_map; +#[doc = "H264_DMA2D_IN_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch0_int_map`] module"] +pub type H264_DMA2D_IN_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch0_int_map; +#[doc = "H264_DMA2D_IN_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch1_int_map`] module"] +pub type H264_DMA2D_IN_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch1_int_map; +#[doc = "H264_DMA2D_IN_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch2_int_map`] module"] +pub type H264_DMA2D_IN_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch2_int_map; +#[doc = "H264_DMA2D_IN_CH3_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch3_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch3_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch3_int_map`] module"] +pub type H264_DMA2D_IN_CH3_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch3_int_map; +#[doc = "H264_DMA2D_IN_CH4_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch4_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch4_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch4_int_map`] module"] +pub type H264_DMA2D_IN_CH4_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch4_int_map; +#[doc = "H264_DMA2D_IN_CH5_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch5_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch5_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch5_int_map`] module"] +pub type H264_DMA2D_IN_CH5_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch5_int_map; +#[doc = "H264_REG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_reg_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_reg_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_reg_int_map`] module"] +pub type H264_REG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod h264_reg_int_map; +#[doc = "ASSIST_DEBUG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`assist_debug_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`assist_debug_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@assist_debug_int_map`] module"] +pub type ASSIST_DEBUG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod assist_debug_int_map; +#[doc = "INTR_STATUS_REG_0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status_reg_0`] module"] +pub type INTR_STATUS_REG_0 = crate::Reg; +#[doc = "NA"] +pub mod intr_status_reg_0; +#[doc = "INTR_STATUS_REG_1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status_reg_1`] module"] +pub type INTR_STATUS_REG_1 = crate::Reg; +#[doc = "NA"] +pub mod intr_status_reg_1; +#[doc = "INTR_STATUS_REG_2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status_reg_2`] module"] +pub type INTR_STATUS_REG_2 = crate::Reg; +#[doc = "NA"] +pub mod intr_status_reg_2; +#[doc = "INTR_STATUS_REG_3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status_reg_3`] module"] +pub type INTR_STATUS_REG_3 = crate::Reg; +#[doc = "NA"] +pub mod intr_status_reg_3; +#[doc = "CLOCK_GATE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"] +pub type CLOCK_GATE = crate::Reg; +#[doc = "NA"] +pub mod clock_gate; +#[doc = "INTERRUPT_REG_DATE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_reg_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt_reg_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt_reg_date`] module"] +pub type INTERRUPT_REG_DATE = crate::Reg; +#[doc = "NA"] +pub mod interrupt_reg_date; diff --git a/esp32p4/src/interrupt_core0/adc_int_map.rs b/esp32p4/src/interrupt_core0/adc_int_map.rs new file mode 100644 index 0000000000..413736d00b --- /dev/null +++ b/esp32p4/src/interrupt_core0/adc_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ADC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `ADC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_ADC_INT_MAP` reader - NA"] +pub type CORE0_ADC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_ADC_INT_MAP` writer - NA"] +pub type CORE0_ADC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_adc_int_map(&self) -> CORE0_ADC_INT_MAP_R { + CORE0_ADC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC_INT_MAP") + .field( + "core0_adc_int_map", + &format_args!("{}", self.core0_adc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_adc_int_map(&mut self) -> CORE0_ADC_INT_MAP_W { + CORE0_ADC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ADC_INT_MAP_SPEC; +impl crate::RegisterSpec for ADC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`adc_int_map::R`](R) reader structure"] +impl crate::Readable for ADC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`adc_int_map::W`](W) writer structure"] +impl crate::Writable for ADC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ADC_INT_MAP to value 0"] +impl crate::Resettable for ADC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/aes_int_map.rs b/esp32p4/src/interrupt_core0/aes_int_map.rs new file mode 100644 index 0000000000..49c224425c --- /dev/null +++ b/esp32p4/src/interrupt_core0/aes_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AES_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AES_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AES_INT_MAP` reader - NA"] +pub type CORE0_AES_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AES_INT_MAP` writer - NA"] +pub type CORE0_AES_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_aes_int_map(&self) -> CORE0_AES_INT_MAP_R { + CORE0_AES_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AES_INT_MAP") + .field( + "core0_aes_int_map", + &format_args!("{}", self.core0_aes_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_aes_int_map(&mut self) -> CORE0_AES_INT_MAP_W { + CORE0_AES_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aes_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aes_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AES_INT_MAP_SPEC; +impl crate::RegisterSpec for AES_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`aes_int_map::R`](R) reader structure"] +impl crate::Readable for AES_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`aes_int_map::W`](W) writer structure"] +impl crate::Writable for AES_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AES_INT_MAP to value 0"] +impl crate::Resettable for AES_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_in_ch0_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch0_int_map.rs new file mode 100644 index 0000000000..1249f45141 --- /dev/null +++ b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_IN_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_IN_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AHB_PDMA_IN_CH0_INT_MAP` reader - NA"] +pub type CORE0_AHB_PDMA_IN_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AHB_PDMA_IN_CH0_INT_MAP` writer - NA"] +pub type CORE0_AHB_PDMA_IN_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_ahb_pdma_in_ch0_int_map(&self) -> CORE0_AHB_PDMA_IN_CH0_INT_MAP_R { + CORE0_AHB_PDMA_IN_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_IN_CH0_INT_MAP") + .field( + "core0_ahb_pdma_in_ch0_int_map", + &format_args!("{}", self.core0_ahb_pdma_in_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_ahb_pdma_in_ch0_int_map( + &mut self, + ) -> CORE0_AHB_PDMA_IN_CH0_INT_MAP_W { + CORE0_AHB_PDMA_IN_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_IN_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_IN_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_in_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_IN_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_in_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_IN_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_IN_CH0_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_IN_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_in_ch1_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch1_int_map.rs new file mode 100644 index 0000000000..2d5b3e5b89 --- /dev/null +++ b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_IN_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_IN_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AHB_PDMA_IN_CH1_INT_MAP` reader - NA"] +pub type CORE0_AHB_PDMA_IN_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AHB_PDMA_IN_CH1_INT_MAP` writer - NA"] +pub type CORE0_AHB_PDMA_IN_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_ahb_pdma_in_ch1_int_map(&self) -> CORE0_AHB_PDMA_IN_CH1_INT_MAP_R { + CORE0_AHB_PDMA_IN_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_IN_CH1_INT_MAP") + .field( + "core0_ahb_pdma_in_ch1_int_map", + &format_args!("{}", self.core0_ahb_pdma_in_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_ahb_pdma_in_ch1_int_map( + &mut self, + ) -> CORE0_AHB_PDMA_IN_CH1_INT_MAP_W { + CORE0_AHB_PDMA_IN_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_IN_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_IN_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_in_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_IN_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_in_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_IN_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_IN_CH1_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_IN_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_in_ch2_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch2_int_map.rs new file mode 100644 index 0000000000..2c4ff79947 --- /dev/null +++ b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_IN_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_IN_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AHB_PDMA_IN_CH2_INT_MAP` reader - NA"] +pub type CORE0_AHB_PDMA_IN_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AHB_PDMA_IN_CH2_INT_MAP` writer - NA"] +pub type CORE0_AHB_PDMA_IN_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_ahb_pdma_in_ch2_int_map(&self) -> CORE0_AHB_PDMA_IN_CH2_INT_MAP_R { + CORE0_AHB_PDMA_IN_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_IN_CH2_INT_MAP") + .field( + "core0_ahb_pdma_in_ch2_int_map", + &format_args!("{}", self.core0_ahb_pdma_in_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_ahb_pdma_in_ch2_int_map( + &mut self, + ) -> CORE0_AHB_PDMA_IN_CH2_INT_MAP_W { + CORE0_AHB_PDMA_IN_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_IN_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_IN_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_in_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_IN_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_in_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_IN_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_IN_CH2_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_IN_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_out_ch0_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch0_int_map.rs new file mode 100644 index 0000000000..6605502ab8 --- /dev/null +++ b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_OUT_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_OUT_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AHB_PDMA_OUT_CH0_INT_MAP` reader - NA"] +pub type CORE0_AHB_PDMA_OUT_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AHB_PDMA_OUT_CH0_INT_MAP` writer - NA"] +pub type CORE0_AHB_PDMA_OUT_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_ahb_pdma_out_ch0_int_map(&self) -> CORE0_AHB_PDMA_OUT_CH0_INT_MAP_R { + CORE0_AHB_PDMA_OUT_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_OUT_CH0_INT_MAP") + .field( + "core0_ahb_pdma_out_ch0_int_map", + &format_args!("{}", self.core0_ahb_pdma_out_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_ahb_pdma_out_ch0_int_map( + &mut self, + ) -> CORE0_AHB_PDMA_OUT_CH0_INT_MAP_W { + CORE0_AHB_PDMA_OUT_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_OUT_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_OUT_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_out_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_OUT_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_out_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_OUT_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_OUT_CH0_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_OUT_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_out_ch1_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch1_int_map.rs new file mode 100644 index 0000000000..881b5a07f7 --- /dev/null +++ b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_OUT_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_OUT_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AHB_PDMA_OUT_CH1_INT_MAP` reader - NA"] +pub type CORE0_AHB_PDMA_OUT_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AHB_PDMA_OUT_CH1_INT_MAP` writer - NA"] +pub type CORE0_AHB_PDMA_OUT_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_ahb_pdma_out_ch1_int_map(&self) -> CORE0_AHB_PDMA_OUT_CH1_INT_MAP_R { + CORE0_AHB_PDMA_OUT_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_OUT_CH1_INT_MAP") + .field( + "core0_ahb_pdma_out_ch1_int_map", + &format_args!("{}", self.core0_ahb_pdma_out_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_ahb_pdma_out_ch1_int_map( + &mut self, + ) -> CORE0_AHB_PDMA_OUT_CH1_INT_MAP_W { + CORE0_AHB_PDMA_OUT_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_OUT_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_OUT_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_out_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_OUT_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_out_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_OUT_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_OUT_CH1_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_OUT_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_out_ch2_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch2_int_map.rs new file mode 100644 index 0000000000..5e43bd324d --- /dev/null +++ b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_OUT_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_OUT_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AHB_PDMA_OUT_CH2_INT_MAP` reader - NA"] +pub type CORE0_AHB_PDMA_OUT_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AHB_PDMA_OUT_CH2_INT_MAP` writer - NA"] +pub type CORE0_AHB_PDMA_OUT_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_ahb_pdma_out_ch2_int_map(&self) -> CORE0_AHB_PDMA_OUT_CH2_INT_MAP_R { + CORE0_AHB_PDMA_OUT_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_OUT_CH2_INT_MAP") + .field( + "core0_ahb_pdma_out_ch2_int_map", + &format_args!("{}", self.core0_ahb_pdma_out_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_ahb_pdma_out_ch2_int_map( + &mut self, + ) -> CORE0_AHB_PDMA_OUT_CH2_INT_MAP_W { + CORE0_AHB_PDMA_OUT_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_OUT_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_OUT_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_out_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_OUT_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_out_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_OUT_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_OUT_CH2_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_OUT_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/assist_debug_int_map.rs b/esp32p4/src/interrupt_core0/assist_debug_int_map.rs new file mode 100644 index 0000000000..5ef3bf47e1 --- /dev/null +++ b/esp32p4/src/interrupt_core0/assist_debug_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `ASSIST_DEBUG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `ASSIST_DEBUG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_ASSIST_DEBUG_INT_MAP` reader - NA"] +pub type CORE0_ASSIST_DEBUG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_ASSIST_DEBUG_INT_MAP` writer - NA"] +pub type CORE0_ASSIST_DEBUG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_assist_debug_int_map(&self) -> CORE0_ASSIST_DEBUG_INT_MAP_R { + CORE0_ASSIST_DEBUG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ASSIST_DEBUG_INT_MAP") + .field( + "core0_assist_debug_int_map", + &format_args!("{}", self.core0_assist_debug_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_assist_debug_int_map( + &mut self, + ) -> CORE0_ASSIST_DEBUG_INT_MAP_W { + CORE0_ASSIST_DEBUG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`assist_debug_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`assist_debug_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ASSIST_DEBUG_INT_MAP_SPEC; +impl crate::RegisterSpec for ASSIST_DEBUG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`assist_debug_int_map::R`](R) reader structure"] +impl crate::Readable for ASSIST_DEBUG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`assist_debug_int_map::W`](W) writer structure"] +impl crate::Writable for ASSIST_DEBUG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ASSIST_DEBUG_INT_MAP to value 0"] +impl crate::Resettable for ASSIST_DEBUG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/axi_pdma_in_ch0_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_in_ch0_int_map.rs new file mode 100644 index 0000000000..c313facc11 --- /dev/null +++ b/esp32p4/src/interrupt_core0/axi_pdma_in_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_IN_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_IN_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AXI_PDMA_IN_CH0_INT_MAP` reader - NA"] +pub type CORE0_AXI_PDMA_IN_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AXI_PDMA_IN_CH0_INT_MAP` writer - NA"] +pub type CORE0_AXI_PDMA_IN_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_axi_pdma_in_ch0_int_map(&self) -> CORE0_AXI_PDMA_IN_CH0_INT_MAP_R { + CORE0_AXI_PDMA_IN_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_IN_CH0_INT_MAP") + .field( + "core0_axi_pdma_in_ch0_int_map", + &format_args!("{}", self.core0_axi_pdma_in_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_axi_pdma_in_ch0_int_map( + &mut self, + ) -> CORE0_AXI_PDMA_IN_CH0_INT_MAP_W { + CORE0_AXI_PDMA_IN_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_IN_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_IN_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_in_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_IN_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_in_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_IN_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_IN_CH0_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_IN_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/axi_pdma_in_ch1_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_in_ch1_int_map.rs new file mode 100644 index 0000000000..8fb358033e --- /dev/null +++ b/esp32p4/src/interrupt_core0/axi_pdma_in_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_IN_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_IN_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AXI_PDMA_IN_CH1_INT_MAP` reader - NA"] +pub type CORE0_AXI_PDMA_IN_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AXI_PDMA_IN_CH1_INT_MAP` writer - NA"] +pub type CORE0_AXI_PDMA_IN_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_axi_pdma_in_ch1_int_map(&self) -> CORE0_AXI_PDMA_IN_CH1_INT_MAP_R { + CORE0_AXI_PDMA_IN_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_IN_CH1_INT_MAP") + .field( + "core0_axi_pdma_in_ch1_int_map", + &format_args!("{}", self.core0_axi_pdma_in_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_axi_pdma_in_ch1_int_map( + &mut self, + ) -> CORE0_AXI_PDMA_IN_CH1_INT_MAP_W { + CORE0_AXI_PDMA_IN_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_IN_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_IN_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_in_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_IN_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_in_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_IN_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_IN_CH1_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_IN_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/axi_pdma_in_ch2_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_in_ch2_int_map.rs new file mode 100644 index 0000000000..2bf71b7366 --- /dev/null +++ b/esp32p4/src/interrupt_core0/axi_pdma_in_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_IN_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_IN_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AXI_PDMA_IN_CH2_INT_MAP` reader - NA"] +pub type CORE0_AXI_PDMA_IN_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AXI_PDMA_IN_CH2_INT_MAP` writer - NA"] +pub type CORE0_AXI_PDMA_IN_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_axi_pdma_in_ch2_int_map(&self) -> CORE0_AXI_PDMA_IN_CH2_INT_MAP_R { + CORE0_AXI_PDMA_IN_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_IN_CH2_INT_MAP") + .field( + "core0_axi_pdma_in_ch2_int_map", + &format_args!("{}", self.core0_axi_pdma_in_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_axi_pdma_in_ch2_int_map( + &mut self, + ) -> CORE0_AXI_PDMA_IN_CH2_INT_MAP_W { + CORE0_AXI_PDMA_IN_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_IN_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_IN_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_in_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_IN_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_in_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_IN_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_IN_CH2_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_IN_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/axi_pdma_out_ch0_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_out_ch0_int_map.rs new file mode 100644 index 0000000000..de02c4b037 --- /dev/null +++ b/esp32p4/src/interrupt_core0/axi_pdma_out_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_OUT_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_OUT_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AXI_PDMA_OUT_CH0_INT_MAP` reader - NA"] +pub type CORE0_AXI_PDMA_OUT_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AXI_PDMA_OUT_CH0_INT_MAP` writer - NA"] +pub type CORE0_AXI_PDMA_OUT_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_axi_pdma_out_ch0_int_map(&self) -> CORE0_AXI_PDMA_OUT_CH0_INT_MAP_R { + CORE0_AXI_PDMA_OUT_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_OUT_CH0_INT_MAP") + .field( + "core0_axi_pdma_out_ch0_int_map", + &format_args!("{}", self.core0_axi_pdma_out_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_axi_pdma_out_ch0_int_map( + &mut self, + ) -> CORE0_AXI_PDMA_OUT_CH0_INT_MAP_W { + CORE0_AXI_PDMA_OUT_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_OUT_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_OUT_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_out_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_OUT_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_out_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_OUT_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_OUT_CH0_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_OUT_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/axi_pdma_out_ch1_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_out_ch1_int_map.rs new file mode 100644 index 0000000000..05529c75ff --- /dev/null +++ b/esp32p4/src/interrupt_core0/axi_pdma_out_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_OUT_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_OUT_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AXI_PDMA_OUT_CH1_INT_MAP` reader - NA"] +pub type CORE0_AXI_PDMA_OUT_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AXI_PDMA_OUT_CH1_INT_MAP` writer - NA"] +pub type CORE0_AXI_PDMA_OUT_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_axi_pdma_out_ch1_int_map(&self) -> CORE0_AXI_PDMA_OUT_CH1_INT_MAP_R { + CORE0_AXI_PDMA_OUT_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_OUT_CH1_INT_MAP") + .field( + "core0_axi_pdma_out_ch1_int_map", + &format_args!("{}", self.core0_axi_pdma_out_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_axi_pdma_out_ch1_int_map( + &mut self, + ) -> CORE0_AXI_PDMA_OUT_CH1_INT_MAP_W { + CORE0_AXI_PDMA_OUT_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_OUT_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_OUT_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_out_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_OUT_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_out_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_OUT_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_OUT_CH1_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_OUT_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/axi_pdma_out_ch2_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_out_ch2_int_map.rs new file mode 100644 index 0000000000..9f9f7a5096 --- /dev/null +++ b/esp32p4/src/interrupt_core0/axi_pdma_out_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_OUT_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_OUT_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_AXI_PDMA_OUT_CH2_INT_MAP` reader - NA"] +pub type CORE0_AXI_PDMA_OUT_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_AXI_PDMA_OUT_CH2_INT_MAP` writer - NA"] +pub type CORE0_AXI_PDMA_OUT_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_axi_pdma_out_ch2_int_map(&self) -> CORE0_AXI_PDMA_OUT_CH2_INT_MAP_R { + CORE0_AXI_PDMA_OUT_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_OUT_CH2_INT_MAP") + .field( + "core0_axi_pdma_out_ch2_int_map", + &format_args!("{}", self.core0_axi_pdma_out_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_axi_pdma_out_ch2_int_map( + &mut self, + ) -> CORE0_AXI_PDMA_OUT_CH2_INT_MAP_W { + CORE0_AXI_PDMA_OUT_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_OUT_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_OUT_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_out_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_OUT_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_out_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_OUT_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_OUT_CH2_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_OUT_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/cache_int_map.rs b/esp32p4/src/interrupt_core0/cache_int_map.rs new file mode 100644 index 0000000000..3baca1667a --- /dev/null +++ b/esp32p4/src/interrupt_core0/cache_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CACHE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CACHE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CACHE_INT_MAP` reader - NA"] +pub type CORE0_CACHE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CACHE_INT_MAP` writer - NA"] +pub type CORE0_CACHE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_cache_int_map(&self) -> CORE0_CACHE_INT_MAP_R { + CORE0_CACHE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CACHE_INT_MAP") + .field( + "core0_cache_int_map", + &format_args!("{}", self.core0_cache_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_cache_int_map(&mut self) -> CORE0_CACHE_INT_MAP_W { + CORE0_CACHE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cache_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CACHE_INT_MAP_SPEC; +impl crate::RegisterSpec for CACHE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cache_int_map::R`](R) reader structure"] +impl crate::Readable for CACHE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cache_int_map::W`](W) writer structure"] +impl crate::Writable for CACHE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CACHE_INT_MAP to value 0"] +impl crate::Resettable for CACHE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/can0_int_map.rs b/esp32p4/src/interrupt_core0/can0_int_map.rs new file mode 100644 index 0000000000..58b403e356 --- /dev/null +++ b/esp32p4/src/interrupt_core0/can0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CAN0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CAN0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CAN0_INT_MAP` reader - NA"] +pub type CORE0_CAN0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CAN0_INT_MAP` writer - NA"] +pub type CORE0_CAN0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_can0_int_map(&self) -> CORE0_CAN0_INT_MAP_R { + CORE0_CAN0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN0_INT_MAP") + .field( + "core0_can0_int_map", + &format_args!("{}", self.core0_can0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_can0_int_map(&mut self) -> CORE0_CAN0_INT_MAP_W { + CORE0_CAN0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAN0_INT_MAP_SPEC; +impl crate::RegisterSpec for CAN0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`can0_int_map::R`](R) reader structure"] +impl crate::Readable for CAN0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`can0_int_map::W`](W) writer structure"] +impl crate::Writable for CAN0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAN0_INT_MAP to value 0"] +impl crate::Resettable for CAN0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/can1_int_map.rs b/esp32p4/src/interrupt_core0/can1_int_map.rs new file mode 100644 index 0000000000..78d1a25dae --- /dev/null +++ b/esp32p4/src/interrupt_core0/can1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CAN1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CAN1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CAN1_INT_MAP` reader - NA"] +pub type CORE0_CAN1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CAN1_INT_MAP` writer - NA"] +pub type CORE0_CAN1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_can1_int_map(&self) -> CORE0_CAN1_INT_MAP_R { + CORE0_CAN1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN1_INT_MAP") + .field( + "core0_can1_int_map", + &format_args!("{}", self.core0_can1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_can1_int_map(&mut self) -> CORE0_CAN1_INT_MAP_W { + CORE0_CAN1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAN1_INT_MAP_SPEC; +impl crate::RegisterSpec for CAN1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`can1_int_map::R`](R) reader structure"] +impl crate::Readable for CAN1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`can1_int_map::W`](W) writer structure"] +impl crate::Writable for CAN1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAN1_INT_MAP to value 0"] +impl crate::Resettable for CAN1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/can2_int_map.rs b/esp32p4/src/interrupt_core0/can2_int_map.rs new file mode 100644 index 0000000000..92fff47027 --- /dev/null +++ b/esp32p4/src/interrupt_core0/can2_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CAN2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CAN2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CAN2_INT_MAP` reader - NA"] +pub type CORE0_CAN2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CAN2_INT_MAP` writer - NA"] +pub type CORE0_CAN2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_can2_int_map(&self) -> CORE0_CAN2_INT_MAP_R { + CORE0_CAN2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN2_INT_MAP") + .field( + "core0_can2_int_map", + &format_args!("{}", self.core0_can2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_can2_int_map(&mut self) -> CORE0_CAN2_INT_MAP_W { + CORE0_CAN2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAN2_INT_MAP_SPEC; +impl crate::RegisterSpec for CAN2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`can2_int_map::R`](R) reader structure"] +impl crate::Readable for CAN2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`can2_int_map::W`](W) writer structure"] +impl crate::Writable for CAN2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAN2_INT_MAP to value 0"] +impl crate::Resettable for CAN2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/clock_gate.rs b/esp32p4/src/interrupt_core0/clock_gate.rs new file mode 100644 index 0000000000..ef928a25c8 --- /dev/null +++ b/esp32p4/src/interrupt_core0/clock_gate.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CLOCK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `CLOCK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_REG_CLK_EN` reader - NA"] +pub type CORE0_REG_CLK_EN_R = crate::BitReader; +#[doc = "Field `CORE0_REG_CLK_EN` writer - NA"] +pub type CORE0_REG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn core0_reg_clk_en(&self) -> CORE0_REG_CLK_EN_R { + CORE0_REG_CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCK_GATE") + .field( + "core0_reg_clk_en", + &format_args!("{}", self.core0_reg_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_reg_clk_en(&mut self) -> CORE0_REG_CLK_EN_W { + CORE0_REG_CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLOCK_GATE_SPEC; +impl crate::RegisterSpec for CLOCK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"] +impl crate::Readable for CLOCK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"] +impl crate::Writable for CLOCK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"] +impl crate::Resettable for CLOCK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/interrupt_core0/core0_trace_int_map.rs b/esp32p4/src/interrupt_core0/core0_trace_int_map.rs new file mode 100644 index 0000000000..5d2fc5b101 --- /dev/null +++ b/esp32p4/src/interrupt_core0/core0_trace_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE0_TRACE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CORE0_TRACE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CORE0_TRACE_INT_MAP` reader - NA"] +pub type CORE0_CORE0_TRACE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CORE0_TRACE_INT_MAP` writer - NA"] +pub type CORE0_CORE0_TRACE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_core0_trace_int_map(&self) -> CORE0_CORE0_TRACE_INT_MAP_R { + CORE0_CORE0_TRACE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE0_TRACE_INT_MAP") + .field( + "core0_core0_trace_int_map", + &format_args!("{}", self.core0_core0_trace_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_core0_trace_int_map( + &mut self, + ) -> CORE0_CORE0_TRACE_INT_MAP_W { + CORE0_CORE0_TRACE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_trace_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core0_trace_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE0_TRACE_INT_MAP_SPEC; +impl crate::RegisterSpec for CORE0_TRACE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core0_trace_int_map::R`](R) reader structure"] +impl crate::Readable for CORE0_TRACE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core0_trace_int_map::W`](W) writer structure"] +impl crate::Writable for CORE0_TRACE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE0_TRACE_INT_MAP to value 0"] +impl crate::Resettable for CORE0_TRACE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/core1_trace_int_map.rs b/esp32p4/src/interrupt_core0/core1_trace_int_map.rs new file mode 100644 index 0000000000..ce3459db1e --- /dev/null +++ b/esp32p4/src/interrupt_core0/core1_trace_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE1_TRACE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CORE1_TRACE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CORE1_TRACE_INT_MAP` reader - NA"] +pub type CORE0_CORE1_TRACE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CORE1_TRACE_INT_MAP` writer - NA"] +pub type CORE0_CORE1_TRACE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_core1_trace_int_map(&self) -> CORE0_CORE1_TRACE_INT_MAP_R { + CORE0_CORE1_TRACE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE1_TRACE_INT_MAP") + .field( + "core0_core1_trace_int_map", + &format_args!("{}", self.core0_core1_trace_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_core1_trace_int_map( + &mut self, + ) -> CORE0_CORE1_TRACE_INT_MAP_W { + CORE0_CORE1_TRACE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core1_trace_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core1_trace_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE1_TRACE_INT_MAP_SPEC; +impl crate::RegisterSpec for CORE1_TRACE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core1_trace_int_map::R`](R) reader structure"] +impl crate::Readable for CORE1_TRACE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core1_trace_int_map::W`](W) writer structure"] +impl crate::Writable for CORE1_TRACE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE1_TRACE_INT_MAP to value 0"] +impl crate::Resettable for CORE1_TRACE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_0_map.rs b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_0_map.rs new file mode 100644 index 0000000000..1e8b1b3e8c --- /dev/null +++ b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_0_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CPU_INT_FROM_CPU_0_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CPU_INT_FROM_CPU_0_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CPU_INT_FROM_CPU_0_MAP` reader - NA"] +pub type CORE0_CPU_INT_FROM_CPU_0_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CPU_INT_FROM_CPU_0_MAP` writer - NA"] +pub type CORE0_CPU_INT_FROM_CPU_0_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_cpu_int_from_cpu_0_map(&self) -> CORE0_CPU_INT_FROM_CPU_0_MAP_R { + CORE0_CPU_INT_FROM_CPU_0_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU_INT_FROM_CPU_0_MAP") + .field( + "core0_cpu_int_from_cpu_0_map", + &format_args!("{}", self.core0_cpu_int_from_cpu_0_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_cpu_int_from_cpu_0_map( + &mut self, + ) -> CORE0_CPU_INT_FROM_CPU_0_MAP_W { + CORE0_CPU_INT_FROM_CPU_0_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_0_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_0_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_INT_FROM_CPU_0_MAP_SPEC; +impl crate::RegisterSpec for CPU_INT_FROM_CPU_0_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu_int_from_cpu_0_map::R`](R) reader structure"] +impl crate::Readable for CPU_INT_FROM_CPU_0_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpu_int_from_cpu_0_map::W`](W) writer structure"] +impl crate::Writable for CPU_INT_FROM_CPU_0_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CPU_INT_FROM_CPU_0_MAP to value 0"] +impl crate::Resettable for CPU_INT_FROM_CPU_0_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_1_map.rs b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_1_map.rs new file mode 100644 index 0000000000..4ed4dbfb38 --- /dev/null +++ b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_1_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CPU_INT_FROM_CPU_1_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CPU_INT_FROM_CPU_1_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CPU_INT_FROM_CPU_1_MAP` reader - NA"] +pub type CORE0_CPU_INT_FROM_CPU_1_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CPU_INT_FROM_CPU_1_MAP` writer - NA"] +pub type CORE0_CPU_INT_FROM_CPU_1_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_cpu_int_from_cpu_1_map(&self) -> CORE0_CPU_INT_FROM_CPU_1_MAP_R { + CORE0_CPU_INT_FROM_CPU_1_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU_INT_FROM_CPU_1_MAP") + .field( + "core0_cpu_int_from_cpu_1_map", + &format_args!("{}", self.core0_cpu_int_from_cpu_1_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_cpu_int_from_cpu_1_map( + &mut self, + ) -> CORE0_CPU_INT_FROM_CPU_1_MAP_W { + CORE0_CPU_INT_FROM_CPU_1_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_1_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_1_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_INT_FROM_CPU_1_MAP_SPEC; +impl crate::RegisterSpec for CPU_INT_FROM_CPU_1_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu_int_from_cpu_1_map::R`](R) reader structure"] +impl crate::Readable for CPU_INT_FROM_CPU_1_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpu_int_from_cpu_1_map::W`](W) writer structure"] +impl crate::Writable for CPU_INT_FROM_CPU_1_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CPU_INT_FROM_CPU_1_MAP to value 0"] +impl crate::Resettable for CPU_INT_FROM_CPU_1_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_2_map.rs b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_2_map.rs new file mode 100644 index 0000000000..6291e0777b --- /dev/null +++ b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_2_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CPU_INT_FROM_CPU_2_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CPU_INT_FROM_CPU_2_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CPU_INT_FROM_CPU_2_MAP` reader - NA"] +pub type CORE0_CPU_INT_FROM_CPU_2_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CPU_INT_FROM_CPU_2_MAP` writer - NA"] +pub type CORE0_CPU_INT_FROM_CPU_2_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_cpu_int_from_cpu_2_map(&self) -> CORE0_CPU_INT_FROM_CPU_2_MAP_R { + CORE0_CPU_INT_FROM_CPU_2_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU_INT_FROM_CPU_2_MAP") + .field( + "core0_cpu_int_from_cpu_2_map", + &format_args!("{}", self.core0_cpu_int_from_cpu_2_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_cpu_int_from_cpu_2_map( + &mut self, + ) -> CORE0_CPU_INT_FROM_CPU_2_MAP_W { + CORE0_CPU_INT_FROM_CPU_2_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_2_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_2_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_INT_FROM_CPU_2_MAP_SPEC; +impl crate::RegisterSpec for CPU_INT_FROM_CPU_2_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu_int_from_cpu_2_map::R`](R) reader structure"] +impl crate::Readable for CPU_INT_FROM_CPU_2_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpu_int_from_cpu_2_map::W`](W) writer structure"] +impl crate::Writable for CPU_INT_FROM_CPU_2_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CPU_INT_FROM_CPU_2_MAP to value 0"] +impl crate::Resettable for CPU_INT_FROM_CPU_2_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_3_map.rs b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_3_map.rs new file mode 100644 index 0000000000..3600e36787 --- /dev/null +++ b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_3_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CPU_INT_FROM_CPU_3_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CPU_INT_FROM_CPU_3_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CPU_INT_FROM_CPU_3_MAP` reader - NA"] +pub type CORE0_CPU_INT_FROM_CPU_3_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CPU_INT_FROM_CPU_3_MAP` writer - NA"] +pub type CORE0_CPU_INT_FROM_CPU_3_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_cpu_int_from_cpu_3_map(&self) -> CORE0_CPU_INT_FROM_CPU_3_MAP_R { + CORE0_CPU_INT_FROM_CPU_3_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU_INT_FROM_CPU_3_MAP") + .field( + "core0_cpu_int_from_cpu_3_map", + &format_args!("{}", self.core0_cpu_int_from_cpu_3_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_cpu_int_from_cpu_3_map( + &mut self, + ) -> CORE0_CPU_INT_FROM_CPU_3_MAP_W { + CORE0_CPU_INT_FROM_CPU_3_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_3_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_3_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_INT_FROM_CPU_3_MAP_SPEC; +impl crate::RegisterSpec for CPU_INT_FROM_CPU_3_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu_int_from_cpu_3_map::R`](R) reader structure"] +impl crate::Readable for CPU_INT_FROM_CPU_3_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpu_int_from_cpu_3_map::W`](W) writer structure"] +impl crate::Writable for CPU_INT_FROM_CPU_3_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CPU_INT_FROM_CPU_3_MAP to value 0"] +impl crate::Resettable for CPU_INT_FROM_CPU_3_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/csi_bridge_int_map.rs b/esp32p4/src/interrupt_core0/csi_bridge_int_map.rs new file mode 100644 index 0000000000..b213e00a63 --- /dev/null +++ b/esp32p4/src/interrupt_core0/csi_bridge_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CSI_BRIDGE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CSI_BRIDGE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CSI_BRIDGE_INT_MAP` reader - NA"] +pub type CORE0_CSI_BRIDGE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CSI_BRIDGE_INT_MAP` writer - NA"] +pub type CORE0_CSI_BRIDGE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_csi_bridge_int_map(&self) -> CORE0_CSI_BRIDGE_INT_MAP_R { + CORE0_CSI_BRIDGE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CSI_BRIDGE_INT_MAP") + .field( + "core0_csi_bridge_int_map", + &format_args!("{}", self.core0_csi_bridge_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_csi_bridge_int_map( + &mut self, + ) -> CORE0_CSI_BRIDGE_INT_MAP_W { + CORE0_CSI_BRIDGE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_bridge_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_bridge_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CSI_BRIDGE_INT_MAP_SPEC; +impl crate::RegisterSpec for CSI_BRIDGE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`csi_bridge_int_map::R`](R) reader structure"] +impl crate::Readable for CSI_BRIDGE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csi_bridge_int_map::W`](W) writer structure"] +impl crate::Writable for CSI_BRIDGE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CSI_BRIDGE_INT_MAP to value 0"] +impl crate::Resettable for CSI_BRIDGE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/csi_int_map.rs b/esp32p4/src/interrupt_core0/csi_int_map.rs new file mode 100644 index 0000000000..7640fa204e --- /dev/null +++ b/esp32p4/src/interrupt_core0/csi_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CSI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CSI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_CSI_INT_MAP` reader - NA"] +pub type CORE0_CSI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_CSI_INT_MAP` writer - NA"] +pub type CORE0_CSI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_csi_int_map(&self) -> CORE0_CSI_INT_MAP_R { + CORE0_CSI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CSI_INT_MAP") + .field( + "core0_csi_int_map", + &format_args!("{}", self.core0_csi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_csi_int_map(&mut self) -> CORE0_CSI_INT_MAP_W { + CORE0_CSI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CSI_INT_MAP_SPEC; +impl crate::RegisterSpec for CSI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`csi_int_map::R`](R) reader structure"] +impl crate::Readable for CSI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csi_int_map::W`](W) writer structure"] +impl crate::Writable for CSI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CSI_INT_MAP to value 0"] +impl crate::Resettable for CSI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/dma2d_in_ch0_int_map.rs b/esp32p4/src/interrupt_core0/dma2d_in_ch0_int_map.rs new file mode 100644 index 0000000000..8a24746658 --- /dev/null +++ b/esp32p4/src/interrupt_core0/dma2d_in_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DMA2D_IN_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DMA2D_IN_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_DMA2D_IN_CH0_INT_MAP` reader - NA"] +pub type CORE0_DMA2D_IN_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_DMA2D_IN_CH0_INT_MAP` writer - NA"] +pub type CORE0_DMA2D_IN_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_dma2d_in_ch0_int_map(&self) -> CORE0_DMA2D_IN_CH0_INT_MAP_R { + CORE0_DMA2D_IN_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA2D_IN_CH0_INT_MAP") + .field( + "core0_dma2d_in_ch0_int_map", + &format_args!("{}", self.core0_dma2d_in_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_dma2d_in_ch0_int_map( + &mut self, + ) -> CORE0_DMA2D_IN_CH0_INT_MAP_W { + CORE0_DMA2D_IN_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_in_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_in_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA2D_IN_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for DMA2D_IN_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma2d_in_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for DMA2D_IN_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma2d_in_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for DMA2D_IN_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA2D_IN_CH0_INT_MAP to value 0"] +impl crate::Resettable for DMA2D_IN_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/dma2d_in_ch1_int_map.rs b/esp32p4/src/interrupt_core0/dma2d_in_ch1_int_map.rs new file mode 100644 index 0000000000..b7b4618056 --- /dev/null +++ b/esp32p4/src/interrupt_core0/dma2d_in_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DMA2D_IN_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DMA2D_IN_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_DMA2D_IN_CH1_INT_MAP` reader - NA"] +pub type CORE0_DMA2D_IN_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_DMA2D_IN_CH1_INT_MAP` writer - NA"] +pub type CORE0_DMA2D_IN_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_dma2d_in_ch1_int_map(&self) -> CORE0_DMA2D_IN_CH1_INT_MAP_R { + CORE0_DMA2D_IN_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA2D_IN_CH1_INT_MAP") + .field( + "core0_dma2d_in_ch1_int_map", + &format_args!("{}", self.core0_dma2d_in_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_dma2d_in_ch1_int_map( + &mut self, + ) -> CORE0_DMA2D_IN_CH1_INT_MAP_W { + CORE0_DMA2D_IN_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_in_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_in_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA2D_IN_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for DMA2D_IN_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma2d_in_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for DMA2D_IN_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma2d_in_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for DMA2D_IN_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA2D_IN_CH1_INT_MAP to value 0"] +impl crate::Resettable for DMA2D_IN_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/dma2d_out_ch0_int_map.rs b/esp32p4/src/interrupt_core0/dma2d_out_ch0_int_map.rs new file mode 100644 index 0000000000..d478953d5c --- /dev/null +++ b/esp32p4/src/interrupt_core0/dma2d_out_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DMA2D_OUT_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DMA2D_OUT_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_DMA2D_OUT_CH0_INT_MAP` reader - NA"] +pub type CORE0_DMA2D_OUT_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_DMA2D_OUT_CH0_INT_MAP` writer - NA"] +pub type CORE0_DMA2D_OUT_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_dma2d_out_ch0_int_map(&self) -> CORE0_DMA2D_OUT_CH0_INT_MAP_R { + CORE0_DMA2D_OUT_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA2D_OUT_CH0_INT_MAP") + .field( + "core0_dma2d_out_ch0_int_map", + &format_args!("{}", self.core0_dma2d_out_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_dma2d_out_ch0_int_map( + &mut self, + ) -> CORE0_DMA2D_OUT_CH0_INT_MAP_W { + CORE0_DMA2D_OUT_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA2D_OUT_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for DMA2D_OUT_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma2d_out_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for DMA2D_OUT_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma2d_out_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for DMA2D_OUT_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA2D_OUT_CH0_INT_MAP to value 0"] +impl crate::Resettable for DMA2D_OUT_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/dma2d_out_ch1_int_map.rs b/esp32p4/src/interrupt_core0/dma2d_out_ch1_int_map.rs new file mode 100644 index 0000000000..edcae50af1 --- /dev/null +++ b/esp32p4/src/interrupt_core0/dma2d_out_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DMA2D_OUT_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DMA2D_OUT_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_DMA2D_OUT_CH1_INT_MAP` reader - NA"] +pub type CORE0_DMA2D_OUT_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_DMA2D_OUT_CH1_INT_MAP` writer - NA"] +pub type CORE0_DMA2D_OUT_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_dma2d_out_ch1_int_map(&self) -> CORE0_DMA2D_OUT_CH1_INT_MAP_R { + CORE0_DMA2D_OUT_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA2D_OUT_CH1_INT_MAP") + .field( + "core0_dma2d_out_ch1_int_map", + &format_args!("{}", self.core0_dma2d_out_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_dma2d_out_ch1_int_map( + &mut self, + ) -> CORE0_DMA2D_OUT_CH1_INT_MAP_W { + CORE0_DMA2D_OUT_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA2D_OUT_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for DMA2D_OUT_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma2d_out_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for DMA2D_OUT_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma2d_out_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for DMA2D_OUT_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA2D_OUT_CH1_INT_MAP to value 0"] +impl crate::Resettable for DMA2D_OUT_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/dma2d_out_ch2_int_map.rs b/esp32p4/src/interrupt_core0/dma2d_out_ch2_int_map.rs new file mode 100644 index 0000000000..f6ea56a721 --- /dev/null +++ b/esp32p4/src/interrupt_core0/dma2d_out_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DMA2D_OUT_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DMA2D_OUT_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_DMA2D_OUT_CH2_INT_MAP` reader - NA"] +pub type CORE0_DMA2D_OUT_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_DMA2D_OUT_CH2_INT_MAP` writer - NA"] +pub type CORE0_DMA2D_OUT_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_dma2d_out_ch2_int_map(&self) -> CORE0_DMA2D_OUT_CH2_INT_MAP_R { + CORE0_DMA2D_OUT_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA2D_OUT_CH2_INT_MAP") + .field( + "core0_dma2d_out_ch2_int_map", + &format_args!("{}", self.core0_dma2d_out_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_dma2d_out_ch2_int_map( + &mut self, + ) -> CORE0_DMA2D_OUT_CH2_INT_MAP_W { + CORE0_DMA2D_OUT_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA2D_OUT_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for DMA2D_OUT_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma2d_out_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for DMA2D_OUT_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma2d_out_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for DMA2D_OUT_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA2D_OUT_CH2_INT_MAP to value 0"] +impl crate::Resettable for DMA2D_OUT_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/dsi_bridge_int_map.rs b/esp32p4/src/interrupt_core0/dsi_bridge_int_map.rs new file mode 100644 index 0000000000..98d3d321ce --- /dev/null +++ b/esp32p4/src/interrupt_core0/dsi_bridge_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DSI_BRIDGE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DSI_BRIDGE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_DSI_BRIDGE_INT_MAP` reader - NA"] +pub type CORE0_DSI_BRIDGE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_DSI_BRIDGE_INT_MAP` writer - NA"] +pub type CORE0_DSI_BRIDGE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_dsi_bridge_int_map(&self) -> CORE0_DSI_BRIDGE_INT_MAP_R { + CORE0_DSI_BRIDGE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSI_BRIDGE_INT_MAP") + .field( + "core0_dsi_bridge_int_map", + &format_args!("{}", self.core0_dsi_bridge_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_dsi_bridge_int_map( + &mut self, + ) -> CORE0_DSI_BRIDGE_INT_MAP_W { + CORE0_DSI_BRIDGE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsi_bridge_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsi_bridge_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DSI_BRIDGE_INT_MAP_SPEC; +impl crate::RegisterSpec for DSI_BRIDGE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dsi_bridge_int_map::R`](R) reader structure"] +impl crate::Readable for DSI_BRIDGE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dsi_bridge_int_map::W`](W) writer structure"] +impl crate::Writable for DSI_BRIDGE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DSI_BRIDGE_INT_MAP to value 0"] +impl crate::Resettable for DSI_BRIDGE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/dsi_int_map.rs b/esp32p4/src/interrupt_core0/dsi_int_map.rs new file mode 100644 index 0000000000..1a3786677b --- /dev/null +++ b/esp32p4/src/interrupt_core0/dsi_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DSI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DSI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_DSI_INT_MAP` reader - NA"] +pub type CORE0_DSI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_DSI_INT_MAP` writer - NA"] +pub type CORE0_DSI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_dsi_int_map(&self) -> CORE0_DSI_INT_MAP_R { + CORE0_DSI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSI_INT_MAP") + .field( + "core0_dsi_int_map", + &format_args!("{}", self.core0_dsi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_dsi_int_map(&mut self) -> CORE0_DSI_INT_MAP_W { + CORE0_DSI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DSI_INT_MAP_SPEC; +impl crate::RegisterSpec for DSI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dsi_int_map::R`](R) reader structure"] +impl crate::Readable for DSI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dsi_int_map::W`](W) writer structure"] +impl crate::Writable for DSI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DSI_INT_MAP to value 0"] +impl crate::Resettable for DSI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/ecc_int_map.rs b/esp32p4/src/interrupt_core0/ecc_int_map.rs new file mode 100644 index 0000000000..4f11238f6b --- /dev/null +++ b/esp32p4/src/interrupt_core0/ecc_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ECC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `ECC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_ECC_INT_MAP` reader - NA"] +pub type CORE0_ECC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_ECC_INT_MAP` writer - NA"] +pub type CORE0_ECC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_ecc_int_map(&self) -> CORE0_ECC_INT_MAP_R { + CORE0_ECC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECC_INT_MAP") + .field( + "core0_ecc_int_map", + &format_args!("{}", self.core0_ecc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_ecc_int_map(&mut self) -> CORE0_ECC_INT_MAP_W { + CORE0_ECC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECC_INT_MAP_SPEC; +impl crate::RegisterSpec for ECC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ecc_int_map::R`](R) reader structure"] +impl crate::Readable for ECC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ecc_int_map::W`](W) writer structure"] +impl crate::Writable for ECC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECC_INT_MAP to value 0"] +impl crate::Resettable for ECC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/ecdsa_int_map.rs b/esp32p4/src/interrupt_core0/ecdsa_int_map.rs new file mode 100644 index 0000000000..162c9f4d41 --- /dev/null +++ b/esp32p4/src/interrupt_core0/ecdsa_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ECDSA_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `ECDSA_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_ECDSA_INT_MAP` reader - NA"] +pub type CORE0_ECDSA_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_ECDSA_INT_MAP` writer - NA"] +pub type CORE0_ECDSA_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_ecdsa_int_map(&self) -> CORE0_ECDSA_INT_MAP_R { + CORE0_ECDSA_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECDSA_INT_MAP") + .field( + "core0_ecdsa_int_map", + &format_args!("{}", self.core0_ecdsa_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_ecdsa_int_map(&mut self) -> CORE0_ECDSA_INT_MAP_W { + CORE0_ECDSA_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecdsa_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecdsa_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECDSA_INT_MAP_SPEC; +impl crate::RegisterSpec for ECDSA_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ecdsa_int_map::R`](R) reader structure"] +impl crate::Readable for ECDSA_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ecdsa_int_map::W`](W) writer structure"] +impl crate::Writable for ECDSA_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECDSA_INT_MAP to value 0"] +impl crate::Resettable for ECDSA_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/flash_mspi_int_map.rs b/esp32p4/src/interrupt_core0/flash_mspi_int_map.rs new file mode 100644 index 0000000000..1b65e573fd --- /dev/null +++ b/esp32p4/src/interrupt_core0/flash_mspi_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `FLASH_MSPI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `FLASH_MSPI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_FLASH_MSPI_INT_MAP` reader - NA"] +pub type CORE0_FLASH_MSPI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_FLASH_MSPI_INT_MAP` writer - NA"] +pub type CORE0_FLASH_MSPI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_flash_mspi_int_map(&self) -> CORE0_FLASH_MSPI_INT_MAP_R { + CORE0_FLASH_MSPI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FLASH_MSPI_INT_MAP") + .field( + "core0_flash_mspi_int_map", + &format_args!("{}", self.core0_flash_mspi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_flash_mspi_int_map( + &mut self, + ) -> CORE0_FLASH_MSPI_INT_MAP_W { + CORE0_FLASH_MSPI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flash_mspi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flash_mspi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FLASH_MSPI_INT_MAP_SPEC; +impl crate::RegisterSpec for FLASH_MSPI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`flash_mspi_int_map::R`](R) reader structure"] +impl crate::Readable for FLASH_MSPI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`flash_mspi_int_map::W`](W) writer structure"] +impl crate::Writable for FLASH_MSPI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FLASH_MSPI_INT_MAP to value 0"] +impl crate::Resettable for FLASH_MSPI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/gdma_int_map.rs b/esp32p4/src/interrupt_core0/gdma_int_map.rs new file mode 100644 index 0000000000..ec1d2b2ade --- /dev/null +++ b/esp32p4/src/interrupt_core0/gdma_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GDMA_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GDMA_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_GDMA_INT_MAP` reader - NA"] +pub type CORE0_GDMA_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_GDMA_INT_MAP` writer - NA"] +pub type CORE0_GDMA_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_gdma_int_map(&self) -> CORE0_GDMA_INT_MAP_R { + CORE0_GDMA_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GDMA_INT_MAP") + .field( + "core0_gdma_int_map", + &format_args!("{}", self.core0_gdma_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_gdma_int_map(&mut self) -> CORE0_GDMA_INT_MAP_W { + CORE0_GDMA_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdma_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdma_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GDMA_INT_MAP_SPEC; +impl crate::RegisterSpec for GDMA_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gdma_int_map::R`](R) reader structure"] +impl crate::Readable for GDMA_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gdma_int_map::W`](W) writer structure"] +impl crate::Writable for GDMA_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GDMA_INT_MAP to value 0"] +impl crate::Resettable for GDMA_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/gmii_phy_int_map.rs b/esp32p4/src/interrupt_core0/gmii_phy_int_map.rs new file mode 100644 index 0000000000..0c1d391604 --- /dev/null +++ b/esp32p4/src/interrupt_core0/gmii_phy_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GMII_PHY_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GMII_PHY_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_GMII_PHY_INT_MAP` reader - NA"] +pub type CORE0_GMII_PHY_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_GMII_PHY_INT_MAP` writer - NA"] +pub type CORE0_GMII_PHY_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_gmii_phy_int_map(&self) -> CORE0_GMII_PHY_INT_MAP_R { + CORE0_GMII_PHY_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GMII_PHY_INT_MAP") + .field( + "core0_gmii_phy_int_map", + &format_args!("{}", self.core0_gmii_phy_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_gmii_phy_int_map(&mut self) -> CORE0_GMII_PHY_INT_MAP_W { + CORE0_GMII_PHY_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmii_phy_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmii_phy_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMII_PHY_INT_MAP_SPEC; +impl crate::RegisterSpec for GMII_PHY_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmii_phy_int_map::R`](R) reader structure"] +impl crate::Readable for GMII_PHY_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmii_phy_int_map::W`](W) writer structure"] +impl crate::Writable for GMII_PHY_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GMII_PHY_INT_MAP to value 0"] +impl crate::Resettable for GMII_PHY_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/gpio_int0_map.rs b/esp32p4/src/interrupt_core0/gpio_int0_map.rs new file mode 100644 index 0000000000..5a53c2853c --- /dev/null +++ b/esp32p4/src/interrupt_core0/gpio_int0_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GPIO_INT0_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_INT0_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_GPIO_INT0_MAP` reader - NA"] +pub type CORE0_GPIO_INT0_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_GPIO_INT0_MAP` writer - NA"] +pub type CORE0_GPIO_INT0_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_gpio_int0_map(&self) -> CORE0_GPIO_INT0_MAP_R { + CORE0_GPIO_INT0_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_INT0_MAP") + .field( + "core0_gpio_int0_map", + &format_args!("{}", self.core0_gpio_int0_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_gpio_int0_map(&mut self) -> CORE0_GPIO_INT0_MAP_W { + CORE0_GPIO_INT0_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int0_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int0_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_INT0_MAP_SPEC; +impl crate::RegisterSpec for GPIO_INT0_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_int0_map::R`](R) reader structure"] +impl crate::Readable for GPIO_INT0_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_int0_map::W`](W) writer structure"] +impl crate::Writable for GPIO_INT0_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GPIO_INT0_MAP to value 0"] +impl crate::Resettable for GPIO_INT0_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/gpio_int1_map.rs b/esp32p4/src/interrupt_core0/gpio_int1_map.rs new file mode 100644 index 0000000000..31b1ee67e0 --- /dev/null +++ b/esp32p4/src/interrupt_core0/gpio_int1_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GPIO_INT1_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_INT1_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_GPIO_INT1_MAP` reader - NA"] +pub type CORE0_GPIO_INT1_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_GPIO_INT1_MAP` writer - NA"] +pub type CORE0_GPIO_INT1_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_gpio_int1_map(&self) -> CORE0_GPIO_INT1_MAP_R { + CORE0_GPIO_INT1_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_INT1_MAP") + .field( + "core0_gpio_int1_map", + &format_args!("{}", self.core0_gpio_int1_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_gpio_int1_map(&mut self) -> CORE0_GPIO_INT1_MAP_W { + CORE0_GPIO_INT1_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int1_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int1_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_INT1_MAP_SPEC; +impl crate::RegisterSpec for GPIO_INT1_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_int1_map::R`](R) reader structure"] +impl crate::Readable for GPIO_INT1_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_int1_map::W`](W) writer structure"] +impl crate::Writable for GPIO_INT1_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GPIO_INT1_MAP to value 0"] +impl crate::Resettable for GPIO_INT1_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/gpio_int2_map.rs b/esp32p4/src/interrupt_core0/gpio_int2_map.rs new file mode 100644 index 0000000000..c03bf9d1d6 --- /dev/null +++ b/esp32p4/src/interrupt_core0/gpio_int2_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GPIO_INT2_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_INT2_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_GPIO_INT2_MAP` reader - NA"] +pub type CORE0_GPIO_INT2_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_GPIO_INT2_MAP` writer - NA"] +pub type CORE0_GPIO_INT2_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_gpio_int2_map(&self) -> CORE0_GPIO_INT2_MAP_R { + CORE0_GPIO_INT2_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_INT2_MAP") + .field( + "core0_gpio_int2_map", + &format_args!("{}", self.core0_gpio_int2_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_gpio_int2_map(&mut self) -> CORE0_GPIO_INT2_MAP_W { + CORE0_GPIO_INT2_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int2_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int2_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_INT2_MAP_SPEC; +impl crate::RegisterSpec for GPIO_INT2_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_int2_map::R`](R) reader structure"] +impl crate::Readable for GPIO_INT2_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_int2_map::W`](W) writer structure"] +impl crate::Writable for GPIO_INT2_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GPIO_INT2_MAP to value 0"] +impl crate::Resettable for GPIO_INT2_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/gpio_int3_map.rs b/esp32p4/src/interrupt_core0/gpio_int3_map.rs new file mode 100644 index 0000000000..0221dc9414 --- /dev/null +++ b/esp32p4/src/interrupt_core0/gpio_int3_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GPIO_INT3_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_INT3_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_GPIO_INT3_MAP` reader - NA"] +pub type CORE0_GPIO_INT3_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_GPIO_INT3_MAP` writer - NA"] +pub type CORE0_GPIO_INT3_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_gpio_int3_map(&self) -> CORE0_GPIO_INT3_MAP_R { + CORE0_GPIO_INT3_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_INT3_MAP") + .field( + "core0_gpio_int3_map", + &format_args!("{}", self.core0_gpio_int3_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_gpio_int3_map(&mut self) -> CORE0_GPIO_INT3_MAP_W { + CORE0_GPIO_INT3_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int3_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int3_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_INT3_MAP_SPEC; +impl crate::RegisterSpec for GPIO_INT3_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_int3_map::R`](R) reader structure"] +impl crate::Readable for GPIO_INT3_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_int3_map::W`](W) writer structure"] +impl crate::Writable for GPIO_INT3_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GPIO_INT3_MAP to value 0"] +impl crate::Resettable for GPIO_INT3_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/gpio_pad_comp_int_map.rs b/esp32p4/src/interrupt_core0/gpio_pad_comp_int_map.rs new file mode 100644 index 0000000000..cf05a940df --- /dev/null +++ b/esp32p4/src/interrupt_core0/gpio_pad_comp_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `GPIO_PAD_COMP_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_PAD_COMP_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_GPIO_PAD_COMP_INT_MAP` reader - NA"] +pub type CORE0_GPIO_PAD_COMP_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_GPIO_PAD_COMP_INT_MAP` writer - NA"] +pub type CORE0_GPIO_PAD_COMP_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_gpio_pad_comp_int_map(&self) -> CORE0_GPIO_PAD_COMP_INT_MAP_R { + CORE0_GPIO_PAD_COMP_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PAD_COMP_INT_MAP") + .field( + "core0_gpio_pad_comp_int_map", + &format_args!("{}", self.core0_gpio_pad_comp_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_gpio_pad_comp_int_map( + &mut self, + ) -> CORE0_GPIO_PAD_COMP_INT_MAP_W { + CORE0_GPIO_PAD_COMP_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pad_comp_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pad_comp_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_PAD_COMP_INT_MAP_SPEC; +impl crate::RegisterSpec for GPIO_PAD_COMP_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_pad_comp_int_map::R`](R) reader structure"] +impl crate::Readable for GPIO_PAD_COMP_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pad_comp_int_map::W`](W) writer structure"] +impl crate::Writable for GPIO_PAD_COMP_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GPIO_PAD_COMP_INT_MAP to value 0"] +impl crate::Resettable for GPIO_PAD_COMP_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch0_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch0_int_map.rs new file mode 100644 index 0000000000..b923668b53 --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH0_INT_MAP` reader - NA"] +pub type CORE0_H264_DMA2D_IN_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH0_INT_MAP` writer - NA"] +pub type CORE0_H264_DMA2D_IN_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_dma2d_in_ch0_int_map(&self) -> CORE0_H264_DMA2D_IN_CH0_INT_MAP_R { + CORE0_H264_DMA2D_IN_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH0_INT_MAP") + .field( + "core0_h264_dma2d_in_ch0_int_map", + &format_args!("{}", self.core0_h264_dma2d_in_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_dma2d_in_ch0_int_map( + &mut self, + ) -> CORE0_H264_DMA2D_IN_CH0_INT_MAP_W { + CORE0_H264_DMA2D_IN_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH0_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch1_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch1_int_map.rs new file mode 100644 index 0000000000..caca4a761c --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH1_INT_MAP` reader - NA"] +pub type CORE0_H264_DMA2D_IN_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH1_INT_MAP` writer - NA"] +pub type CORE0_H264_DMA2D_IN_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_dma2d_in_ch1_int_map(&self) -> CORE0_H264_DMA2D_IN_CH1_INT_MAP_R { + CORE0_H264_DMA2D_IN_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH1_INT_MAP") + .field( + "core0_h264_dma2d_in_ch1_int_map", + &format_args!("{}", self.core0_h264_dma2d_in_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_dma2d_in_ch1_int_map( + &mut self, + ) -> CORE0_H264_DMA2D_IN_CH1_INT_MAP_W { + CORE0_H264_DMA2D_IN_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH1_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch2_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch2_int_map.rs new file mode 100644 index 0000000000..895760b14f --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH2_INT_MAP` reader - NA"] +pub type CORE0_H264_DMA2D_IN_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH2_INT_MAP` writer - NA"] +pub type CORE0_H264_DMA2D_IN_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_dma2d_in_ch2_int_map(&self) -> CORE0_H264_DMA2D_IN_CH2_INT_MAP_R { + CORE0_H264_DMA2D_IN_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH2_INT_MAP") + .field( + "core0_h264_dma2d_in_ch2_int_map", + &format_args!("{}", self.core0_h264_dma2d_in_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_dma2d_in_ch2_int_map( + &mut self, + ) -> CORE0_H264_DMA2D_IN_CH2_INT_MAP_W { + CORE0_H264_DMA2D_IN_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH2_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch3_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch3_int_map.rs new file mode 100644 index 0000000000..6bbcc3db3c --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch3_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH3_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH3_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH3_INT_MAP` reader - NA"] +pub type CORE0_H264_DMA2D_IN_CH3_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH3_INT_MAP` writer - NA"] +pub type CORE0_H264_DMA2D_IN_CH3_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_dma2d_in_ch3_int_map(&self) -> CORE0_H264_DMA2D_IN_CH3_INT_MAP_R { + CORE0_H264_DMA2D_IN_CH3_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH3_INT_MAP") + .field( + "core0_h264_dma2d_in_ch3_int_map", + &format_args!("{}", self.core0_h264_dma2d_in_ch3_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_dma2d_in_ch3_int_map( + &mut self, + ) -> CORE0_H264_DMA2D_IN_CH3_INT_MAP_W { + CORE0_H264_DMA2D_IN_CH3_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch3_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch3_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH3_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH3_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch3_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH3_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch3_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH3_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH3_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH3_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch4_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch4_int_map.rs new file mode 100644 index 0000000000..db32c0cd72 --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch4_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH4_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH4_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH4_INT_MAP` reader - NA"] +pub type CORE0_H264_DMA2D_IN_CH4_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH4_INT_MAP` writer - NA"] +pub type CORE0_H264_DMA2D_IN_CH4_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_dma2d_in_ch4_int_map(&self) -> CORE0_H264_DMA2D_IN_CH4_INT_MAP_R { + CORE0_H264_DMA2D_IN_CH4_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH4_INT_MAP") + .field( + "core0_h264_dma2d_in_ch4_int_map", + &format_args!("{}", self.core0_h264_dma2d_in_ch4_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_dma2d_in_ch4_int_map( + &mut self, + ) -> CORE0_H264_DMA2D_IN_CH4_INT_MAP_W { + CORE0_H264_DMA2D_IN_CH4_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch4_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch4_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH4_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH4_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch4_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH4_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch4_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH4_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH4_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH4_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch5_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch5_int_map.rs new file mode 100644 index 0000000000..879efbcefb --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch5_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH5_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH5_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH5_INT_MAP` reader - NA"] +pub type CORE0_H264_DMA2D_IN_CH5_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_DMA2D_IN_CH5_INT_MAP` writer - NA"] +pub type CORE0_H264_DMA2D_IN_CH5_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_dma2d_in_ch5_int_map(&self) -> CORE0_H264_DMA2D_IN_CH5_INT_MAP_R { + CORE0_H264_DMA2D_IN_CH5_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH5_INT_MAP") + .field( + "core0_h264_dma2d_in_ch5_int_map", + &format_args!("{}", self.core0_h264_dma2d_in_ch5_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_dma2d_in_ch5_int_map( + &mut self, + ) -> CORE0_H264_DMA2D_IN_CH5_INT_MAP_W { + CORE0_H264_DMA2D_IN_CH5_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch5_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch5_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH5_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH5_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch5_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH5_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch5_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH5_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH5_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH5_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch0_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch0_int_map.rs new file mode 100644 index 0000000000..cf21abb345 --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_OUT_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_OUT_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_DMA2D_OUT_CH0_INT_MAP` reader - NA"] +pub type CORE0_H264_DMA2D_OUT_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_DMA2D_OUT_CH0_INT_MAP` writer - NA"] +pub type CORE0_H264_DMA2D_OUT_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_dma2d_out_ch0_int_map(&self) -> CORE0_H264_DMA2D_OUT_CH0_INT_MAP_R { + CORE0_H264_DMA2D_OUT_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_OUT_CH0_INT_MAP") + .field( + "core0_h264_dma2d_out_ch0_int_map", + &format_args!("{}", self.core0_h264_dma2d_out_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_dma2d_out_ch0_int_map( + &mut self, + ) -> CORE0_H264_DMA2D_OUT_CH0_INT_MAP_W { + CORE0_H264_DMA2D_OUT_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_OUT_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_OUT_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_out_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_OUT_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_out_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_OUT_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_OUT_CH0_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_OUT_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch1_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch1_int_map.rs new file mode 100644 index 0000000000..8a74aaef98 --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_OUT_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_OUT_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_DMA2D_OUT_CH1_INT_MAP` reader - NA"] +pub type CORE0_H264_DMA2D_OUT_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_DMA2D_OUT_CH1_INT_MAP` writer - NA"] +pub type CORE0_H264_DMA2D_OUT_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_dma2d_out_ch1_int_map(&self) -> CORE0_H264_DMA2D_OUT_CH1_INT_MAP_R { + CORE0_H264_DMA2D_OUT_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_OUT_CH1_INT_MAP") + .field( + "core0_h264_dma2d_out_ch1_int_map", + &format_args!("{}", self.core0_h264_dma2d_out_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_dma2d_out_ch1_int_map( + &mut self, + ) -> CORE0_H264_DMA2D_OUT_CH1_INT_MAP_W { + CORE0_H264_DMA2D_OUT_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_OUT_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_OUT_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_out_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_OUT_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_out_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_OUT_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_OUT_CH1_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_OUT_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch2_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch2_int_map.rs new file mode 100644 index 0000000000..d809e5f02c --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_OUT_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_OUT_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_DMA2D_OUT_CH2_INT_MAP` reader - NA"] +pub type CORE0_H264_DMA2D_OUT_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_DMA2D_OUT_CH2_INT_MAP` writer - NA"] +pub type CORE0_H264_DMA2D_OUT_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_dma2d_out_ch2_int_map(&self) -> CORE0_H264_DMA2D_OUT_CH2_INT_MAP_R { + CORE0_H264_DMA2D_OUT_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_OUT_CH2_INT_MAP") + .field( + "core0_h264_dma2d_out_ch2_int_map", + &format_args!("{}", self.core0_h264_dma2d_out_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_dma2d_out_ch2_int_map( + &mut self, + ) -> CORE0_H264_DMA2D_OUT_CH2_INT_MAP_W { + CORE0_H264_DMA2D_OUT_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_OUT_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_OUT_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_out_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_OUT_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_out_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_OUT_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_OUT_CH2_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_OUT_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch3_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch3_int_map.rs new file mode 100644 index 0000000000..7c8b133065 --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch3_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_OUT_CH3_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_OUT_CH3_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_DMA2D_OUT_CH3_INT_MAP` reader - NA"] +pub type CORE0_H264_DMA2D_OUT_CH3_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_DMA2D_OUT_CH3_INT_MAP` writer - NA"] +pub type CORE0_H264_DMA2D_OUT_CH3_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_dma2d_out_ch3_int_map(&self) -> CORE0_H264_DMA2D_OUT_CH3_INT_MAP_R { + CORE0_H264_DMA2D_OUT_CH3_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_OUT_CH3_INT_MAP") + .field( + "core0_h264_dma2d_out_ch3_int_map", + &format_args!("{}", self.core0_h264_dma2d_out_ch3_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_dma2d_out_ch3_int_map( + &mut self, + ) -> CORE0_H264_DMA2D_OUT_CH3_INT_MAP_W { + CORE0_H264_DMA2D_OUT_CH3_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch3_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch3_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_OUT_CH3_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_OUT_CH3_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_out_ch3_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_OUT_CH3_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_out_ch3_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_OUT_CH3_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_OUT_CH3_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_OUT_CH3_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch4_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch4_int_map.rs new file mode 100644 index 0000000000..4f753f3f30 --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch4_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_OUT_CH4_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_OUT_CH4_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_DMA2D_OUT_CH4_INT_MAP` reader - NA"] +pub type CORE0_H264_DMA2D_OUT_CH4_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_DMA2D_OUT_CH4_INT_MAP` writer - NA"] +pub type CORE0_H264_DMA2D_OUT_CH4_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_dma2d_out_ch4_int_map(&self) -> CORE0_H264_DMA2D_OUT_CH4_INT_MAP_R { + CORE0_H264_DMA2D_OUT_CH4_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_OUT_CH4_INT_MAP") + .field( + "core0_h264_dma2d_out_ch4_int_map", + &format_args!("{}", self.core0_h264_dma2d_out_ch4_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_dma2d_out_ch4_int_map( + &mut self, + ) -> CORE0_H264_DMA2D_OUT_CH4_INT_MAP_W { + CORE0_H264_DMA2D_OUT_CH4_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch4_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch4_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_OUT_CH4_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_OUT_CH4_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_out_ch4_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_OUT_CH4_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_out_ch4_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_OUT_CH4_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_OUT_CH4_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_OUT_CH4_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/h264_reg_int_map.rs b/esp32p4/src/interrupt_core0/h264_reg_int_map.rs new file mode 100644 index 0000000000..089f7daafa --- /dev/null +++ b/esp32p4/src/interrupt_core0/h264_reg_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `H264_REG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_REG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_H264_REG_INT_MAP` reader - NA"] +pub type CORE0_H264_REG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_H264_REG_INT_MAP` writer - NA"] +pub type CORE0_H264_REG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_h264_reg_int_map(&self) -> CORE0_H264_REG_INT_MAP_R { + CORE0_H264_REG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_REG_INT_MAP") + .field( + "core0_h264_reg_int_map", + &format_args!("{}", self.core0_h264_reg_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_h264_reg_int_map(&mut self) -> CORE0_H264_REG_INT_MAP_W { + CORE0_H264_REG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_reg_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_reg_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_REG_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_REG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_reg_int_map::R`](R) reader structure"] +impl crate::Readable for H264_REG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_reg_int_map::W`](W) writer structure"] +impl crate::Writable for H264_REG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_REG_INT_MAP to value 0"] +impl crate::Resettable for H264_REG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/hp_core_ctrl_int_map.rs b/esp32p4/src/interrupt_core0/hp_core_ctrl_int_map.rs new file mode 100644 index 0000000000..a3ffed63c6 --- /dev/null +++ b/esp32p4/src/interrupt_core0/hp_core_ctrl_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_CORE_CTRL_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CORE_CTRL_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_HP_CORE_CTRL_INT_MAP` reader - NA"] +pub type CORE0_HP_CORE_CTRL_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_HP_CORE_CTRL_INT_MAP` writer - NA"] +pub type CORE0_HP_CORE_CTRL_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_hp_core_ctrl_int_map(&self) -> CORE0_HP_CORE_CTRL_INT_MAP_R { + CORE0_HP_CORE_CTRL_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CORE_CTRL_INT_MAP") + .field( + "core0_hp_core_ctrl_int_map", + &format_args!("{}", self.core0_hp_core_ctrl_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_hp_core_ctrl_int_map( + &mut self, + ) -> CORE0_HP_CORE_CTRL_INT_MAP_W { + CORE0_HP_CORE_CTRL_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_ctrl_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_ctrl_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CORE_CTRL_INT_MAP_SPEC; +impl crate::RegisterSpec for HP_CORE_CTRL_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_core_ctrl_int_map::R`](R) reader structure"] +impl crate::Readable for HP_CORE_CTRL_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_core_ctrl_int_map::W`](W) writer structure"] +impl crate::Writable for HP_CORE_CTRL_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CORE_CTRL_INT_MAP to value 0"] +impl crate::Resettable for HP_CORE_CTRL_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/hp_parlio_rx_int_map.rs b/esp32p4/src/interrupt_core0/hp_parlio_rx_int_map.rs new file mode 100644 index 0000000000..3db353e0bc --- /dev/null +++ b/esp32p4/src/interrupt_core0/hp_parlio_rx_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_PARLIO_RX_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_PARLIO_RX_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_HP_PARLIO_RX_INT_MAP` reader - NA"] +pub type CORE0_HP_PARLIO_RX_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_HP_PARLIO_RX_INT_MAP` writer - NA"] +pub type CORE0_HP_PARLIO_RX_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_hp_parlio_rx_int_map(&self) -> CORE0_HP_PARLIO_RX_INT_MAP_R { + CORE0_HP_PARLIO_RX_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PARLIO_RX_INT_MAP") + .field( + "core0_hp_parlio_rx_int_map", + &format_args!("{}", self.core0_hp_parlio_rx_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_hp_parlio_rx_int_map( + &mut self, + ) -> CORE0_HP_PARLIO_RX_INT_MAP_W { + CORE0_HP_PARLIO_RX_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_parlio_rx_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_parlio_rx_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PARLIO_RX_INT_MAP_SPEC; +impl crate::RegisterSpec for HP_PARLIO_RX_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_parlio_rx_int_map::R`](R) reader structure"] +impl crate::Readable for HP_PARLIO_RX_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_parlio_rx_int_map::W`](W) writer structure"] +impl crate::Writable for HP_PARLIO_RX_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_PARLIO_RX_INT_MAP to value 0"] +impl crate::Resettable for HP_PARLIO_RX_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/hp_parlio_tx_int_map.rs b/esp32p4/src/interrupt_core0/hp_parlio_tx_int_map.rs new file mode 100644 index 0000000000..95338e6bd2 --- /dev/null +++ b/esp32p4/src/interrupt_core0/hp_parlio_tx_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_PARLIO_TX_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_PARLIO_TX_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_HP_PARLIO_TX_INT_MAP` reader - NA"] +pub type CORE0_HP_PARLIO_TX_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_HP_PARLIO_TX_INT_MAP` writer - NA"] +pub type CORE0_HP_PARLIO_TX_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_hp_parlio_tx_int_map(&self) -> CORE0_HP_PARLIO_TX_INT_MAP_R { + CORE0_HP_PARLIO_TX_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PARLIO_TX_INT_MAP") + .field( + "core0_hp_parlio_tx_int_map", + &format_args!("{}", self.core0_hp_parlio_tx_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_hp_parlio_tx_int_map( + &mut self, + ) -> CORE0_HP_PARLIO_TX_INT_MAP_W { + CORE0_HP_PARLIO_TX_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_parlio_tx_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_parlio_tx_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PARLIO_TX_INT_MAP_SPEC; +impl crate::RegisterSpec for HP_PARLIO_TX_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_parlio_tx_int_map::R`](R) reader structure"] +impl crate::Readable for HP_PARLIO_TX_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_parlio_tx_int_map::W`](W) writer structure"] +impl crate::Writable for HP_PARLIO_TX_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_PARLIO_TX_INT_MAP to value 0"] +impl crate::Resettable for HP_PARLIO_TX_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/hp_pau_int_map.rs b/esp32p4/src/interrupt_core0/hp_pau_int_map.rs new file mode 100644 index 0000000000..c459a23e62 --- /dev/null +++ b/esp32p4/src/interrupt_core0/hp_pau_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_PAU_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_PAU_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_HP_PAU_INT_MAP` reader - NA"] +pub type CORE0_HP_PAU_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_HP_PAU_INT_MAP` writer - NA"] +pub type CORE0_HP_PAU_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_hp_pau_int_map(&self) -> CORE0_HP_PAU_INT_MAP_R { + CORE0_HP_PAU_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PAU_INT_MAP") + .field( + "core0_hp_pau_int_map", + &format_args!("{}", self.core0_hp_pau_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_hp_pau_int_map(&mut self) -> CORE0_HP_PAU_INT_MAP_W { + CORE0_HP_PAU_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_pau_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_pau_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PAU_INT_MAP_SPEC; +impl crate::RegisterSpec for HP_PAU_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_pau_int_map::R`](R) reader structure"] +impl crate::Readable for HP_PAU_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_pau_int_map::W`](W) writer structure"] +impl crate::Writable for HP_PAU_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_PAU_INT_MAP to value 0"] +impl crate::Resettable for HP_PAU_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/hp_sysreg_int_map.rs b/esp32p4/src/interrupt_core0/hp_sysreg_int_map.rs new file mode 100644 index 0000000000..2974642b3e --- /dev/null +++ b/esp32p4/src/interrupt_core0/hp_sysreg_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_SYSREG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SYSREG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_HP_SYSREG_INT_MAP` reader - NA"] +pub type CORE0_HP_SYSREG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_HP_SYSREG_INT_MAP` writer - NA"] +pub type CORE0_HP_SYSREG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_hp_sysreg_int_map(&self) -> CORE0_HP_SYSREG_INT_MAP_R { + CORE0_HP_SYSREG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SYSREG_INT_MAP") + .field( + "core0_hp_sysreg_int_map", + &format_args!("{}", self.core0_hp_sysreg_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_hp_sysreg_int_map(&mut self) -> CORE0_HP_SYSREG_INT_MAP_W { + CORE0_HP_SYSREG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sysreg_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sysreg_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SYSREG_INT_MAP_SPEC; +impl crate::RegisterSpec for HP_SYSREG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sysreg_int_map::R`](R) reader structure"] +impl crate::Readable for HP_SYSREG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sysreg_int_map::W`](W) writer structure"] +impl crate::Writable for HP_SYSREG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SYSREG_INT_MAP to value 0"] +impl crate::Resettable for HP_SYSREG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/i2c0_int_map.rs b/esp32p4/src/interrupt_core0/i2c0_int_map.rs new file mode 100644 index 0000000000..768719eb34 --- /dev/null +++ b/esp32p4/src/interrupt_core0/i2c0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I2C0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I2C0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_I2C0_INT_MAP` reader - NA"] +pub type CORE0_I2C0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_I2C0_INT_MAP` writer - NA"] +pub type CORE0_I2C0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_i2c0_int_map(&self) -> CORE0_I2C0_INT_MAP_R { + CORE0_I2C0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0_INT_MAP") + .field( + "core0_i2c0_int_map", + &format_args!("{}", self.core0_i2c0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_i2c0_int_map(&mut self) -> CORE0_I2C0_INT_MAP_W { + CORE0_I2C0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C0_INT_MAP_SPEC; +impl crate::RegisterSpec for I2C0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c0_int_map::R`](R) reader structure"] +impl crate::Readable for I2C0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c0_int_map::W`](W) writer structure"] +impl crate::Writable for I2C0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C0_INT_MAP to value 0"] +impl crate::Resettable for I2C0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/i2c1_int_map.rs b/esp32p4/src/interrupt_core0/i2c1_int_map.rs new file mode 100644 index 0000000000..3af9f61a72 --- /dev/null +++ b/esp32p4/src/interrupt_core0/i2c1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I2C1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I2C1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_I2C1_INT_MAP` reader - NA"] +pub type CORE0_I2C1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_I2C1_INT_MAP` writer - NA"] +pub type CORE0_I2C1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_i2c1_int_map(&self) -> CORE0_I2C1_INT_MAP_R { + CORE0_I2C1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1_INT_MAP") + .field( + "core0_i2c1_int_map", + &format_args!("{}", self.core0_i2c1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_i2c1_int_map(&mut self) -> CORE0_I2C1_INT_MAP_W { + CORE0_I2C1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C1_INT_MAP_SPEC; +impl crate::RegisterSpec for I2C1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c1_int_map::R`](R) reader structure"] +impl crate::Readable for I2C1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c1_int_map::W`](W) writer structure"] +impl crate::Writable for I2C1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C1_INT_MAP to value 0"] +impl crate::Resettable for I2C1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/i2s0_int_map.rs b/esp32p4/src/interrupt_core0/i2s0_int_map.rs new file mode 100644 index 0000000000..819d83bc9d --- /dev/null +++ b/esp32p4/src/interrupt_core0/i2s0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I2S0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I2S0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_I2S0_INT_MAP` reader - NA"] +pub type CORE0_I2S0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_I2S0_INT_MAP` writer - NA"] +pub type CORE0_I2S0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_i2s0_int_map(&self) -> CORE0_I2S0_INT_MAP_R { + CORE0_I2S0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S0_INT_MAP") + .field( + "core0_i2s0_int_map", + &format_args!("{}", self.core0_i2s0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_i2s0_int_map(&mut self) -> CORE0_I2S0_INT_MAP_W { + CORE0_I2S0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2S0_INT_MAP_SPEC; +impl crate::RegisterSpec for I2S0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2s0_int_map::R`](R) reader structure"] +impl crate::Readable for I2S0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2s0_int_map::W`](W) writer structure"] +impl crate::Writable for I2S0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2S0_INT_MAP to value 0"] +impl crate::Resettable for I2S0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/i2s1_int_map.rs b/esp32p4/src/interrupt_core0/i2s1_int_map.rs new file mode 100644 index 0000000000..bf4c8361c4 --- /dev/null +++ b/esp32p4/src/interrupt_core0/i2s1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I2S1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I2S1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_I2S1_INT_MAP` reader - NA"] +pub type CORE0_I2S1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_I2S1_INT_MAP` writer - NA"] +pub type CORE0_I2S1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_i2s1_int_map(&self) -> CORE0_I2S1_INT_MAP_R { + CORE0_I2S1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S1_INT_MAP") + .field( + "core0_i2s1_int_map", + &format_args!("{}", self.core0_i2s1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_i2s1_int_map(&mut self) -> CORE0_I2S1_INT_MAP_W { + CORE0_I2S1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2S1_INT_MAP_SPEC; +impl crate::RegisterSpec for I2S1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2s1_int_map::R`](R) reader structure"] +impl crate::Readable for I2S1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2s1_int_map::W`](W) writer structure"] +impl crate::Writable for I2S1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2S1_INT_MAP to value 0"] +impl crate::Resettable for I2S1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/i2s2_int_map.rs b/esp32p4/src/interrupt_core0/i2s2_int_map.rs new file mode 100644 index 0000000000..f00ccb1186 --- /dev/null +++ b/esp32p4/src/interrupt_core0/i2s2_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I2S2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I2S2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_I2S2_INT_MAP` reader - NA"] +pub type CORE0_I2S2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_I2S2_INT_MAP` writer - NA"] +pub type CORE0_I2S2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_i2s2_int_map(&self) -> CORE0_I2S2_INT_MAP_R { + CORE0_I2S2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S2_INT_MAP") + .field( + "core0_i2s2_int_map", + &format_args!("{}", self.core0_i2s2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_i2s2_int_map(&mut self) -> CORE0_I2S2_INT_MAP_W { + CORE0_I2S2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2S2_INT_MAP_SPEC; +impl crate::RegisterSpec for I2S2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2s2_int_map::R`](R) reader structure"] +impl crate::Readable for I2S2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2s2_int_map::W`](W) writer structure"] +impl crate::Writable for I2S2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2S2_INT_MAP to value 0"] +impl crate::Resettable for I2S2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/i3c_mst_int_map.rs b/esp32p4/src/interrupt_core0/i3c_mst_int_map.rs new file mode 100644 index 0000000000..bd28686e41 --- /dev/null +++ b/esp32p4/src/interrupt_core0/i3c_mst_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I3C_MST_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I3C_MST_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_I3C_MST_INT_MAP` reader - NA"] +pub type CORE0_I3C_MST_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_I3C_MST_INT_MAP` writer - NA"] +pub type CORE0_I3C_MST_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_i3c_mst_int_map(&self) -> CORE0_I3C_MST_INT_MAP_R { + CORE0_I3C_MST_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I3C_MST_INT_MAP") + .field( + "core0_i3c_mst_int_map", + &format_args!("{}", self.core0_i3c_mst_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_i3c_mst_int_map(&mut self) -> CORE0_I3C_MST_INT_MAP_W { + CORE0_I3C_MST_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i3c_mst_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i3c_mst_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I3C_MST_INT_MAP_SPEC; +impl crate::RegisterSpec for I3C_MST_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i3c_mst_int_map::R`](R) reader structure"] +impl crate::Readable for I3C_MST_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i3c_mst_int_map::W`](W) writer structure"] +impl crate::Writable for I3C_MST_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I3C_MST_INT_MAP to value 0"] +impl crate::Resettable for I3C_MST_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/i3c_slv_int_map.rs b/esp32p4/src/interrupt_core0/i3c_slv_int_map.rs new file mode 100644 index 0000000000..7fed80a331 --- /dev/null +++ b/esp32p4/src/interrupt_core0/i3c_slv_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I3C_SLV_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I3C_SLV_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_I3C_SLV_INT_MAP` reader - NA"] +pub type CORE0_I3C_SLV_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_I3C_SLV_INT_MAP` writer - NA"] +pub type CORE0_I3C_SLV_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_i3c_slv_int_map(&self) -> CORE0_I3C_SLV_INT_MAP_R { + CORE0_I3C_SLV_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I3C_SLV_INT_MAP") + .field( + "core0_i3c_slv_int_map", + &format_args!("{}", self.core0_i3c_slv_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_i3c_slv_int_map(&mut self) -> CORE0_I3C_SLV_INT_MAP_W { + CORE0_I3C_SLV_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i3c_slv_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i3c_slv_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I3C_SLV_INT_MAP_SPEC; +impl crate::RegisterSpec for I3C_SLV_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i3c_slv_int_map::R`](R) reader structure"] +impl crate::Readable for I3C_SLV_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i3c_slv_int_map::W`](W) writer structure"] +impl crate::Writable for I3C_SLV_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I3C_SLV_INT_MAP to value 0"] +impl crate::Resettable for I3C_SLV_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/interrupt_reg_date.rs b/esp32p4/src/interrupt_core0/interrupt_reg_date.rs new file mode 100644 index 0000000000..f71385c364 --- /dev/null +++ b/esp32p4/src/interrupt_core0/interrupt_reg_date.rs @@ -0,0 +1,68 @@ +#[doc = "Register `INTERRUPT_REG_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `INTERRUPT_REG_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_INTERRUPT_REG_DATE` reader - NA"] +pub type CORE0_INTERRUPT_REG_DATE_R = crate::FieldReader; +#[doc = "Field `CORE0_INTERRUPT_REG_DATE` writer - NA"] +pub type CORE0_INTERRUPT_REG_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - NA"] + #[inline(always)] + pub fn core0_interrupt_reg_date(&self) -> CORE0_INTERRUPT_REG_DATE_R { + CORE0_INTERRUPT_REG_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTERRUPT_REG_DATE") + .field( + "core0_interrupt_reg_date", + &format_args!("{}", self.core0_interrupt_reg_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_interrupt_reg_date( + &mut self, + ) -> CORE0_INTERRUPT_REG_DATE_W { + CORE0_INTERRUPT_REG_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_reg_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt_reg_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERRUPT_REG_DATE_SPEC; +impl crate::RegisterSpec for INTERRUPT_REG_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interrupt_reg_date::R`](R) reader structure"] +impl crate::Readable for INTERRUPT_REG_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interrupt_reg_date::W`](W) writer structure"] +impl crate::Writable for INTERRUPT_REG_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTERRUPT_REG_DATE to value 0x0200_3020"] +impl crate::Resettable for INTERRUPT_REG_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_3020; +} diff --git a/esp32p4/src/interrupt_core0/intr_status_reg_0.rs b/esp32p4/src/interrupt_core0/intr_status_reg_0.rs new file mode 100644 index 0000000000..f0bf8c0af6 --- /dev/null +++ b/esp32p4/src/interrupt_core0/intr_status_reg_0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INTR_STATUS_REG_0` reader"] +pub type R = crate::R; +#[doc = "Field `CORE0_INTR_STATUS_0` reader - NA"] +pub type CORE0_INTR_STATUS_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn core0_intr_status_0(&self) -> CORE0_INTR_STATUS_0_R { + CORE0_INTR_STATUS_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_STATUS_REG_0") + .field( + "core0_intr_status_0", + &format_args!("{}", self.core0_intr_status_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_STATUS_REG_0_SPEC; +impl crate::RegisterSpec for INTR_STATUS_REG_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_status_reg_0::R`](R) reader structure"] +impl crate::Readable for INTR_STATUS_REG_0_SPEC {} +#[doc = "`reset()` method sets INTR_STATUS_REG_0 to value 0"] +impl crate::Resettable for INTR_STATUS_REG_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/intr_status_reg_1.rs b/esp32p4/src/interrupt_core0/intr_status_reg_1.rs new file mode 100644 index 0000000000..e3642fb021 --- /dev/null +++ b/esp32p4/src/interrupt_core0/intr_status_reg_1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INTR_STATUS_REG_1` reader"] +pub type R = crate::R; +#[doc = "Field `CORE0_INTR_STATUS_1` reader - NA"] +pub type CORE0_INTR_STATUS_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn core0_intr_status_1(&self) -> CORE0_INTR_STATUS_1_R { + CORE0_INTR_STATUS_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_STATUS_REG_1") + .field( + "core0_intr_status_1", + &format_args!("{}", self.core0_intr_status_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_STATUS_REG_1_SPEC; +impl crate::RegisterSpec for INTR_STATUS_REG_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_status_reg_1::R`](R) reader structure"] +impl crate::Readable for INTR_STATUS_REG_1_SPEC {} +#[doc = "`reset()` method sets INTR_STATUS_REG_1 to value 0"] +impl crate::Resettable for INTR_STATUS_REG_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/intr_status_reg_2.rs b/esp32p4/src/interrupt_core0/intr_status_reg_2.rs new file mode 100644 index 0000000000..4d8f0f7dc8 --- /dev/null +++ b/esp32p4/src/interrupt_core0/intr_status_reg_2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INTR_STATUS_REG_2` reader"] +pub type R = crate::R; +#[doc = "Field `CORE0_INTR_STATUS_2` reader - NA"] +pub type CORE0_INTR_STATUS_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn core0_intr_status_2(&self) -> CORE0_INTR_STATUS_2_R { + CORE0_INTR_STATUS_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_STATUS_REG_2") + .field( + "core0_intr_status_2", + &format_args!("{}", self.core0_intr_status_2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_STATUS_REG_2_SPEC; +impl crate::RegisterSpec for INTR_STATUS_REG_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_status_reg_2::R`](R) reader structure"] +impl crate::Readable for INTR_STATUS_REG_2_SPEC {} +#[doc = "`reset()` method sets INTR_STATUS_REG_2 to value 0"] +impl crate::Resettable for INTR_STATUS_REG_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/intr_status_reg_3.rs b/esp32p4/src/interrupt_core0/intr_status_reg_3.rs new file mode 100644 index 0000000000..4884f41dfc --- /dev/null +++ b/esp32p4/src/interrupt_core0/intr_status_reg_3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INTR_STATUS_REG_3` reader"] +pub type R = crate::R; +#[doc = "Field `CORE0_INTR_STATUS_3` reader - NA"] +pub type CORE0_INTR_STATUS_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn core0_intr_status_3(&self) -> CORE0_INTR_STATUS_3_R { + CORE0_INTR_STATUS_3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_STATUS_REG_3") + .field( + "core0_intr_status_3", + &format_args!("{}", self.core0_intr_status_3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_STATUS_REG_3_SPEC; +impl crate::RegisterSpec for INTR_STATUS_REG_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_status_reg_3::R`](R) reader structure"] +impl crate::Readable for INTR_STATUS_REG_3_SPEC {} +#[doc = "`reset()` method sets INTR_STATUS_REG_3 to value 0"] +impl crate::Resettable for INTR_STATUS_REG_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/isp_int_map.rs b/esp32p4/src/interrupt_core0/isp_int_map.rs new file mode 100644 index 0000000000..6301302223 --- /dev/null +++ b/esp32p4/src/interrupt_core0/isp_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ISP_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `ISP_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_ISP_INT_MAP` reader - NA"] +pub type CORE0_ISP_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_ISP_INT_MAP` writer - NA"] +pub type CORE0_ISP_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_isp_int_map(&self) -> CORE0_ISP_INT_MAP_R { + CORE0_ISP_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ISP_INT_MAP") + .field( + "core0_isp_int_map", + &format_args!("{}", self.core0_isp_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_isp_int_map(&mut self) -> CORE0_ISP_INT_MAP_W { + CORE0_ISP_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isp_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isp_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ISP_INT_MAP_SPEC; +impl crate::RegisterSpec for ISP_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`isp_int_map::R`](R) reader structure"] +impl crate::Readable for ISP_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`isp_int_map::W`](W) writer structure"] +impl crate::Writable for ISP_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ISP_INT_MAP to value 0"] +impl crate::Resettable for ISP_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/jpeg_int_map.rs b/esp32p4/src/interrupt_core0/jpeg_int_map.rs new file mode 100644 index 0000000000..a119a06690 --- /dev/null +++ b/esp32p4/src/interrupt_core0/jpeg_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `JPEG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `JPEG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_JPEG_INT_MAP` reader - NA"] +pub type CORE0_JPEG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_JPEG_INT_MAP` writer - NA"] +pub type CORE0_JPEG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_jpeg_int_map(&self) -> CORE0_JPEG_INT_MAP_R { + CORE0_JPEG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("JPEG_INT_MAP") + .field( + "core0_jpeg_int_map", + &format_args!("{}", self.core0_jpeg_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_jpeg_int_map(&mut self) -> CORE0_JPEG_INT_MAP_W { + CORE0_JPEG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`jpeg_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`jpeg_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct JPEG_INT_MAP_SPEC; +impl crate::RegisterSpec for JPEG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`jpeg_int_map::R`](R) reader structure"] +impl crate::Readable for JPEG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`jpeg_int_map::W`](W) writer structure"] +impl crate::Writable for JPEG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets JPEG_INT_MAP to value 0"] +impl crate::Resettable for JPEG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/km_int_map.rs b/esp32p4/src/interrupt_core0/km_int_map.rs new file mode 100644 index 0000000000..4355b0e4c0 --- /dev/null +++ b/esp32p4/src/interrupt_core0/km_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `KM_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `KM_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_KM_INT_MAP` reader - NA"] +pub type CORE0_KM_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_KM_INT_MAP` writer - NA"] +pub type CORE0_KM_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_km_int_map(&self) -> CORE0_KM_INT_MAP_R { + CORE0_KM_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KM_INT_MAP") + .field( + "core0_km_int_map", + &format_args!("{}", self.core0_km_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_km_int_map(&mut self) -> CORE0_KM_INT_MAP_W { + CORE0_KM_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`km_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`km_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KM_INT_MAP_SPEC; +impl crate::RegisterSpec for KM_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`km_int_map::R`](R) reader structure"] +impl crate::Readable for KM_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`km_int_map::W`](W) writer structure"] +impl crate::Writable for KM_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets KM_INT_MAP to value 0"] +impl crate::Resettable for KM_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lcd_cam_int_map.rs b/esp32p4/src/interrupt_core0/lcd_cam_int_map.rs new file mode 100644 index 0000000000..adfc92b185 --- /dev/null +++ b/esp32p4/src/interrupt_core0/lcd_cam_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LCD_CAM_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_CAM_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LCD_CAM_INT_MAP` reader - NA"] +pub type CORE0_LCD_CAM_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LCD_CAM_INT_MAP` writer - NA"] +pub type CORE0_LCD_CAM_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lcd_cam_int_map(&self) -> CORE0_LCD_CAM_INT_MAP_R { + CORE0_LCD_CAM_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_CAM_INT_MAP") + .field( + "core0_lcd_cam_int_map", + &format_args!("{}", self.core0_lcd_cam_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lcd_cam_int_map(&mut self) -> CORE0_LCD_CAM_INT_MAP_W { + CORE0_LCD_CAM_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_cam_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_cam_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_CAM_INT_MAP_SPEC; +impl crate::RegisterSpec for LCD_CAM_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_cam_int_map::R`](R) reader structure"] +impl crate::Readable for LCD_CAM_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_cam_int_map::W`](W) writer structure"] +impl crate::Writable for LCD_CAM_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_CAM_INT_MAP to value 0"] +impl crate::Resettable for LCD_CAM_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/ledc_int_map.rs b/esp32p4/src/interrupt_core0/ledc_int_map.rs new file mode 100644 index 0000000000..9bab748205 --- /dev/null +++ b/esp32p4/src/interrupt_core0/ledc_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LEDC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LEDC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LEDC_INT_MAP` reader - NA"] +pub type CORE0_LEDC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LEDC_INT_MAP` writer - NA"] +pub type CORE0_LEDC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_ledc_int_map(&self) -> CORE0_LEDC_INT_MAP_R { + CORE0_LEDC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LEDC_INT_MAP") + .field( + "core0_ledc_int_map", + &format_args!("{}", self.core0_ledc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_ledc_int_map(&mut self) -> CORE0_LEDC_INT_MAP_W { + CORE0_LEDC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ledc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ledc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LEDC_INT_MAP_SPEC; +impl crate::RegisterSpec for LEDC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ledc_int_map::R`](R) reader structure"] +impl crate::Readable for LEDC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ledc_int_map::W`](W) writer structure"] +impl crate::Writable for LEDC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LEDC_INT_MAP to value 0"] +impl crate::Resettable for LEDC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_adc_int_map.rs b/esp32p4/src/interrupt_core0/lp_adc_int_map.rs new file mode 100644 index 0000000000..8ca52be579 --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_adc_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ADC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ADC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_ADC_INT_MAP` reader - NA"] +pub type CORE0_LP_ADC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_ADC_INT_MAP` writer - NA"] +pub type CORE0_LP_ADC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_adc_int_map(&self) -> CORE0_LP_ADC_INT_MAP_R { + CORE0_LP_ADC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ADC_INT_MAP") + .field( + "core0_lp_adc_int_map", + &format_args!("{}", self.core0_lp_adc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_adc_int_map(&mut self) -> CORE0_LP_ADC_INT_MAP_W { + CORE0_LP_ADC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_adc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_adc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ADC_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_ADC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_adc_int_map::R`](R) reader structure"] +impl crate::Readable for LP_ADC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_adc_int_map::W`](W) writer structure"] +impl crate::Writable for LP_ADC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ADC_INT_MAP to value 0"] +impl crate::Resettable for LP_ADC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_anaperi_int_map.rs b/esp32p4/src/interrupt_core0/lp_anaperi_int_map.rs new file mode 100644 index 0000000000..b8a648a84d --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_anaperi_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANAPERI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANAPERI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_ANAPERI_INT_MAP` reader - NA"] +pub type CORE0_LP_ANAPERI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_ANAPERI_INT_MAP` writer - NA"] +pub type CORE0_LP_ANAPERI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_anaperi_int_map(&self) -> CORE0_LP_ANAPERI_INT_MAP_R { + CORE0_LP_ANAPERI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANAPERI_INT_MAP") + .field( + "core0_lp_anaperi_int_map", + &format_args!("{}", self.core0_lp_anaperi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_anaperi_int_map( + &mut self, + ) -> CORE0_LP_ANAPERI_INT_MAP_W { + CORE0_LP_ANAPERI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_anaperi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_anaperi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANAPERI_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_ANAPERI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_anaperi_int_map::R`](R) reader structure"] +impl crate::Readable for LP_ANAPERI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_anaperi_int_map::W`](W) writer structure"] +impl crate::Writable for LP_ANAPERI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANAPERI_INT_MAP to value 0"] +impl crate::Resettable for LP_ANAPERI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_efuse_int_map.rs b/esp32p4/src/interrupt_core0/lp_efuse_int_map.rs new file mode 100644 index 0000000000..8377df3507 --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_efuse_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_EFUSE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_EFUSE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_EFUSE_INT_MAP` reader - NA"] +pub type CORE0_LP_EFUSE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_EFUSE_INT_MAP` writer - NA"] +pub type CORE0_LP_EFUSE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_efuse_int_map(&self) -> CORE0_LP_EFUSE_INT_MAP_R { + CORE0_LP_EFUSE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_EFUSE_INT_MAP") + .field( + "core0_lp_efuse_int_map", + &format_args!("{}", self.core0_lp_efuse_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_efuse_int_map(&mut self) -> CORE0_LP_EFUSE_INT_MAP_W { + CORE0_LP_EFUSE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_efuse_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_efuse_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_EFUSE_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_EFUSE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_efuse_int_map::R`](R) reader structure"] +impl crate::Readable for LP_EFUSE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_efuse_int_map::W`](W) writer structure"] +impl crate::Writable for LP_EFUSE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_EFUSE_INT_MAP to value 0"] +impl crate::Resettable for LP_EFUSE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_gpio_int_map.rs b/esp32p4/src/interrupt_core0/lp_gpio_int_map.rs new file mode 100644 index 0000000000..b9d4ab9288 --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_gpio_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_GPIO_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_GPIO_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_GPIO_INT_MAP` reader - NA"] +pub type CORE0_LP_GPIO_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_GPIO_INT_MAP` writer - NA"] +pub type CORE0_LP_GPIO_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_gpio_int_map(&self) -> CORE0_LP_GPIO_INT_MAP_R { + CORE0_LP_GPIO_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_GPIO_INT_MAP") + .field( + "core0_lp_gpio_int_map", + &format_args!("{}", self.core0_lp_gpio_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_gpio_int_map(&mut self) -> CORE0_LP_GPIO_INT_MAP_W { + CORE0_LP_GPIO_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_gpio_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_gpio_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_GPIO_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_GPIO_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_gpio_int_map::R`](R) reader structure"] +impl crate::Readable for LP_GPIO_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_gpio_int_map::W`](W) writer structure"] +impl crate::Writable for LP_GPIO_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_GPIO_INT_MAP to value 0"] +impl crate::Resettable for LP_GPIO_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_huk_int_map.rs b/esp32p4/src/interrupt_core0/lp_huk_int_map.rs new file mode 100644 index 0000000000..d7192e83ed --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_huk_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_HUK_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_HUK_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_HUK_INT_MAP` reader - NA"] +pub type CORE0_LP_HUK_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_HUK_INT_MAP` writer - NA"] +pub type CORE0_LP_HUK_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_huk_int_map(&self) -> CORE0_LP_HUK_INT_MAP_R { + CORE0_LP_HUK_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_HUK_INT_MAP") + .field( + "core0_lp_huk_int_map", + &format_args!("{}", self.core0_lp_huk_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_huk_int_map(&mut self) -> CORE0_LP_HUK_INT_MAP_W { + CORE0_LP_HUK_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_huk_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_huk_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_HUK_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_HUK_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_huk_int_map::R`](R) reader structure"] +impl crate::Readable for LP_HUK_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_huk_int_map::W`](W) writer structure"] +impl crate::Writable for LP_HUK_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_HUK_INT_MAP to value 0"] +impl crate::Resettable for LP_HUK_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_i2c_int_map.rs b/esp32p4/src/interrupt_core0/lp_i2c_int_map.rs new file mode 100644 index 0000000000..86c5213b8b --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_i2c_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_I2C_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_I2C_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_I2C_INT_MAP` reader - NA"] +pub type CORE0_LP_I2C_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_I2C_INT_MAP` writer - NA"] +pub type CORE0_LP_I2C_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_i2c_int_map(&self) -> CORE0_LP_I2C_INT_MAP_R { + CORE0_LP_I2C_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2C_INT_MAP") + .field( + "core0_lp_i2c_int_map", + &format_args!("{}", self.core0_lp_i2c_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_i2c_int_map(&mut self) -> CORE0_LP_I2C_INT_MAP_W { + CORE0_LP_I2C_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2c_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2c_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_I2C_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_I2C_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_i2c_int_map::R`](R) reader structure"] +impl crate::Readable for LP_I2C_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_i2c_int_map::W`](W) writer structure"] +impl crate::Writable for LP_I2C_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_I2C_INT_MAP to value 0"] +impl crate::Resettable for LP_I2C_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_i2s_int_map.rs b/esp32p4/src/interrupt_core0/lp_i2s_int_map.rs new file mode 100644 index 0000000000..1e12ef3a2d --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_i2s_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_I2S_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_I2S_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_I2S_INT_MAP` reader - NA"] +pub type CORE0_LP_I2S_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_I2S_INT_MAP` writer - NA"] +pub type CORE0_LP_I2S_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_i2s_int_map(&self) -> CORE0_LP_I2S_INT_MAP_R { + CORE0_LP_I2S_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2S_INT_MAP") + .field( + "core0_lp_i2s_int_map", + &format_args!("{}", self.core0_lp_i2s_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_i2s_int_map(&mut self) -> CORE0_LP_I2S_INT_MAP_W { + CORE0_LP_I2S_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_I2S_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_I2S_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_i2s_int_map::R`](R) reader structure"] +impl crate::Readable for LP_I2S_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_i2s_int_map::W`](W) writer structure"] +impl crate::Writable for LP_I2S_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_I2S_INT_MAP to value 0"] +impl crate::Resettable for LP_I2S_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_rtc_int_map.rs b/esp32p4/src/interrupt_core0/lp_rtc_int_map.rs new file mode 100644 index 0000000000..0ae2667327 --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_rtc_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_RTC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_RTC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_RTC_INT_MAP` reader - NA"] +pub type CORE0_LP_RTC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_RTC_INT_MAP` writer - NA"] +pub type CORE0_LP_RTC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_rtc_int_map(&self) -> CORE0_LP_RTC_INT_MAP_R { + CORE0_LP_RTC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_RTC_INT_MAP") + .field( + "core0_lp_rtc_int_map", + &format_args!("{}", self.core0_lp_rtc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_rtc_int_map(&mut self) -> CORE0_LP_RTC_INT_MAP_W { + CORE0_LP_RTC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_rtc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_rtc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_RTC_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_RTC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_rtc_int_map::R`](R) reader structure"] +impl crate::Readable for LP_RTC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_rtc_int_map::W`](W) writer structure"] +impl crate::Writable for LP_RTC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_RTC_INT_MAP to value 0"] +impl crate::Resettable for LP_RTC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_spi_int_map.rs b/esp32p4/src/interrupt_core0/lp_spi_int_map.rs new file mode 100644 index 0000000000..19d79b87d0 --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_spi_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_SPI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SPI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_SPI_INT_MAP` reader - NA"] +pub type CORE0_LP_SPI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_SPI_INT_MAP` writer - NA"] +pub type CORE0_LP_SPI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_spi_int_map(&self) -> CORE0_LP_SPI_INT_MAP_R { + CORE0_LP_SPI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SPI_INT_MAP") + .field( + "core0_lp_spi_int_map", + &format_args!("{}", self.core0_lp_spi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_spi_int_map(&mut self) -> CORE0_LP_SPI_INT_MAP_W { + CORE0_LP_SPI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_spi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_spi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SPI_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_SPI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_spi_int_map::R`](R) reader structure"] +impl crate::Readable for LP_SPI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_spi_int_map::W`](W) writer structure"] +impl crate::Writable for LP_SPI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SPI_INT_MAP to value 0"] +impl crate::Resettable for LP_SPI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_sw_int_map.rs b/esp32p4/src/interrupt_core0/lp_sw_int_map.rs new file mode 100644 index 0000000000..b84675cbe9 --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_sw_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_SW_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SW_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_SW_INT_MAP` reader - NA"] +pub type CORE0_LP_SW_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_SW_INT_MAP` writer - NA"] +pub type CORE0_LP_SW_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_sw_int_map(&self) -> CORE0_LP_SW_INT_MAP_R { + CORE0_LP_SW_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SW_INT_MAP") + .field( + "core0_lp_sw_int_map", + &format_args!("{}", self.core0_lp_sw_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_sw_int_map(&mut self) -> CORE0_LP_SW_INT_MAP_W { + CORE0_LP_SW_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sw_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sw_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SW_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_SW_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_sw_int_map::R`](R) reader structure"] +impl crate::Readable for LP_SW_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_sw_int_map::W`](W) writer structure"] +impl crate::Writable for LP_SW_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SW_INT_MAP to value 0"] +impl crate::Resettable for LP_SW_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_sysreg_int_map.rs b/esp32p4/src/interrupt_core0/lp_sysreg_int_map.rs new file mode 100644 index 0000000000..ee3a65dc5b --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_sysreg_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_SYSREG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SYSREG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_SYSREG_INT_MAP` reader - NA"] +pub type CORE0_LP_SYSREG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_SYSREG_INT_MAP` writer - NA"] +pub type CORE0_LP_SYSREG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_sysreg_int_map(&self) -> CORE0_LP_SYSREG_INT_MAP_R { + CORE0_LP_SYSREG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SYSREG_INT_MAP") + .field( + "core0_lp_sysreg_int_map", + &format_args!("{}", self.core0_lp_sysreg_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_sysreg_int_map(&mut self) -> CORE0_LP_SYSREG_INT_MAP_W { + CORE0_LP_SYSREG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sysreg_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sysreg_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SYSREG_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_SYSREG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_sysreg_int_map::R`](R) reader structure"] +impl crate::Readable for LP_SYSREG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_sysreg_int_map::W`](W) writer structure"] +impl crate::Writable for LP_SYSREG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SYSREG_INT_MAP to value 0"] +impl crate::Resettable for LP_SYSREG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_timer_reg_0_int_map.rs b/esp32p4/src/interrupt_core0/lp_timer_reg_0_int_map.rs new file mode 100644 index 0000000000..5e812f66ce --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_timer_reg_0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_TIMER_REG_0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TIMER_REG_0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_TIMER_REG_0_INT_MAP` reader - NA"] +pub type CORE0_LP_TIMER_REG_0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_TIMER_REG_0_INT_MAP` writer - NA"] +pub type CORE0_LP_TIMER_REG_0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_timer_reg_0_int_map(&self) -> CORE0_LP_TIMER_REG_0_INT_MAP_R { + CORE0_LP_TIMER_REG_0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TIMER_REG_0_INT_MAP") + .field( + "core0_lp_timer_reg_0_int_map", + &format_args!("{}", self.core0_lp_timer_reg_0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_timer_reg_0_int_map( + &mut self, + ) -> CORE0_LP_TIMER_REG_0_INT_MAP_W { + CORE0_LP_TIMER_REG_0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timer_reg_0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timer_reg_0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TIMER_REG_0_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_TIMER_REG_0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_timer_reg_0_int_map::R`](R) reader structure"] +impl crate::Readable for LP_TIMER_REG_0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_timer_reg_0_int_map::W`](W) writer structure"] +impl crate::Writable for LP_TIMER_REG_0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TIMER_REG_0_INT_MAP to value 0"] +impl crate::Resettable for LP_TIMER_REG_0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_timer_reg_1_int_map.rs b/esp32p4/src/interrupt_core0/lp_timer_reg_1_int_map.rs new file mode 100644 index 0000000000..1bab20037b --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_timer_reg_1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_TIMER_REG_1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TIMER_REG_1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_TIMER_REG_1_INT_MAP` reader - NA"] +pub type CORE0_LP_TIMER_REG_1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_TIMER_REG_1_INT_MAP` writer - NA"] +pub type CORE0_LP_TIMER_REG_1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_timer_reg_1_int_map(&self) -> CORE0_LP_TIMER_REG_1_INT_MAP_R { + CORE0_LP_TIMER_REG_1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TIMER_REG_1_INT_MAP") + .field( + "core0_lp_timer_reg_1_int_map", + &format_args!("{}", self.core0_lp_timer_reg_1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_timer_reg_1_int_map( + &mut self, + ) -> CORE0_LP_TIMER_REG_1_INT_MAP_W { + CORE0_LP_TIMER_REG_1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timer_reg_1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timer_reg_1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TIMER_REG_1_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_TIMER_REG_1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_timer_reg_1_int_map::R`](R) reader structure"] +impl crate::Readable for LP_TIMER_REG_1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_timer_reg_1_int_map::W`](W) writer structure"] +impl crate::Writable for LP_TIMER_REG_1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TIMER_REG_1_INT_MAP to value 0"] +impl crate::Resettable for LP_TIMER_REG_1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_touch_int_map.rs b/esp32p4/src/interrupt_core0/lp_touch_int_map.rs new file mode 100644 index 0000000000..7dde602182 --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_touch_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_TOUCH_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TOUCH_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_TOUCH_INT_MAP` reader - NA"] +pub type CORE0_LP_TOUCH_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_TOUCH_INT_MAP` writer - NA"] +pub type CORE0_LP_TOUCH_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_touch_int_map(&self) -> CORE0_LP_TOUCH_INT_MAP_R { + CORE0_LP_TOUCH_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TOUCH_INT_MAP") + .field( + "core0_lp_touch_int_map", + &format_args!("{}", self.core0_lp_touch_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_touch_int_map(&mut self) -> CORE0_LP_TOUCH_INT_MAP_W { + CORE0_LP_TOUCH_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_touch_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_touch_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TOUCH_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_TOUCH_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_touch_int_map::R`](R) reader structure"] +impl crate::Readable for LP_TOUCH_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_touch_int_map::W`](W) writer structure"] +impl crate::Writable for LP_TOUCH_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TOUCH_INT_MAP to value 0"] +impl crate::Resettable for LP_TOUCH_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_tsens_int_map.rs b/esp32p4/src/interrupt_core0/lp_tsens_int_map.rs new file mode 100644 index 0000000000..b57ad51763 --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_tsens_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_TSENS_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TSENS_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_TSENS_INT_MAP` reader - NA"] +pub type CORE0_LP_TSENS_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_TSENS_INT_MAP` writer - NA"] +pub type CORE0_LP_TSENS_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_tsens_int_map(&self) -> CORE0_LP_TSENS_INT_MAP_R { + CORE0_LP_TSENS_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TSENS_INT_MAP") + .field( + "core0_lp_tsens_int_map", + &format_args!("{}", self.core0_lp_tsens_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_tsens_int_map(&mut self) -> CORE0_LP_TSENS_INT_MAP_W { + CORE0_LP_TSENS_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tsens_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tsens_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TSENS_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_TSENS_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_tsens_int_map::R`](R) reader structure"] +impl crate::Readable for LP_TSENS_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_tsens_int_map::W`](W) writer structure"] +impl crate::Writable for LP_TSENS_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TSENS_INT_MAP to value 0"] +impl crate::Resettable for LP_TSENS_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_uart_int_map.rs b/esp32p4/src/interrupt_core0/lp_uart_int_map.rs new file mode 100644 index 0000000000..937c6d932c --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_uart_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_UART_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_UART_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_UART_INT_MAP` reader - NA"] +pub type CORE0_LP_UART_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_UART_INT_MAP` writer - NA"] +pub type CORE0_LP_UART_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_uart_int_map(&self) -> CORE0_LP_UART_INT_MAP_R { + CORE0_LP_UART_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_UART_INT_MAP") + .field( + "core0_lp_uart_int_map", + &format_args!("{}", self.core0_lp_uart_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_uart_int_map(&mut self) -> CORE0_LP_UART_INT_MAP_W { + CORE0_LP_UART_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_uart_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_uart_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_UART_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_UART_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_uart_int_map::R`](R) reader structure"] +impl crate::Readable for LP_UART_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_uart_int_map::W`](W) writer structure"] +impl crate::Writable for LP_UART_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_UART_INT_MAP to value 0"] +impl crate::Resettable for LP_UART_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lp_wdt_int_map.rs b/esp32p4/src/interrupt_core0/lp_wdt_int_map.rs new file mode 100644 index 0000000000..da47cdaaa2 --- /dev/null +++ b/esp32p4/src/interrupt_core0/lp_wdt_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_WDT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_WDT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LP_WDT_INT_MAP` reader - NA"] +pub type CORE0_LP_WDT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LP_WDT_INT_MAP` writer - NA"] +pub type CORE0_LP_WDT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lp_wdt_int_map(&self) -> CORE0_LP_WDT_INT_MAP_R { + CORE0_LP_WDT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_WDT_INT_MAP") + .field( + "core0_lp_wdt_int_map", + &format_args!("{}", self.core0_lp_wdt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lp_wdt_int_map(&mut self) -> CORE0_LP_WDT_INT_MAP_W { + CORE0_LP_WDT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_wdt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_wdt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_WDT_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_WDT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_wdt_int_map::R`](R) reader structure"] +impl crate::Readable for LP_WDT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_wdt_int_map::W`](W) writer structure"] +impl crate::Writable for LP_WDT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_WDT_INT_MAP to value 0"] +impl crate::Resettable for LP_WDT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/lpi_int_map.rs b/esp32p4/src/interrupt_core0/lpi_int_map.rs new file mode 100644 index 0000000000..7ffae70deb --- /dev/null +++ b/esp32p4/src/interrupt_core0/lpi_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LPI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LPI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_LPI_INT_MAP` reader - NA"] +pub type CORE0_LPI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_LPI_INT_MAP` writer - NA"] +pub type CORE0_LPI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_lpi_int_map(&self) -> CORE0_LPI_INT_MAP_R { + CORE0_LPI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LPI_INT_MAP") + .field( + "core0_lpi_int_map", + &format_args!("{}", self.core0_lpi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_lpi_int_map(&mut self) -> CORE0_LPI_INT_MAP_W { + CORE0_LPI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LPI_INT_MAP_SPEC; +impl crate::RegisterSpec for LPI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpi_int_map::R`](R) reader structure"] +impl crate::Readable for LPI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lpi_int_map::W`](W) writer structure"] +impl crate::Writable for LPI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LPI_INT_MAP to value 0"] +impl crate::Resettable for LPI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/mb_hp_int_map.rs b/esp32p4/src/interrupt_core0/mb_hp_int_map.rs new file mode 100644 index 0000000000..5be8b30675 --- /dev/null +++ b/esp32p4/src/interrupt_core0/mb_hp_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `MB_HP_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `MB_HP_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_MB_HP_INT_MAP` reader - NA"] +pub type CORE0_MB_HP_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_MB_HP_INT_MAP` writer - NA"] +pub type CORE0_MB_HP_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_mb_hp_int_map(&self) -> CORE0_MB_HP_INT_MAP_R { + CORE0_MB_HP_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MB_HP_INT_MAP") + .field( + "core0_mb_hp_int_map", + &format_args!("{}", self.core0_mb_hp_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_mb_hp_int_map(&mut self) -> CORE0_MB_HP_INT_MAP_W { + CORE0_MB_HP_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mb_hp_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mb_hp_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MB_HP_INT_MAP_SPEC; +impl crate::RegisterSpec for MB_HP_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_hp_int_map::R`](R) reader structure"] +impl crate::Readable for MB_HP_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mb_hp_int_map::W`](W) writer structure"] +impl crate::Writable for MB_HP_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MB_HP_INT_MAP to value 0"] +impl crate::Resettable for MB_HP_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/mb_lp_int_map.rs b/esp32p4/src/interrupt_core0/mb_lp_int_map.rs new file mode 100644 index 0000000000..b94c49957e --- /dev/null +++ b/esp32p4/src/interrupt_core0/mb_lp_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `MB_LP_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `MB_LP_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_MB_LP_INT_MAP` reader - NA"] +pub type CORE0_MB_LP_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_MB_LP_INT_MAP` writer - NA"] +pub type CORE0_MB_LP_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_mb_lp_int_map(&self) -> CORE0_MB_LP_INT_MAP_R { + CORE0_MB_LP_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MB_LP_INT_MAP") + .field( + "core0_mb_lp_int_map", + &format_args!("{}", self.core0_mb_lp_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_mb_lp_int_map(&mut self) -> CORE0_MB_LP_INT_MAP_W { + CORE0_MB_LP_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mb_lp_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mb_lp_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MB_LP_INT_MAP_SPEC; +impl crate::RegisterSpec for MB_LP_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_lp_int_map::R`](R) reader structure"] +impl crate::Readable for MB_LP_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mb_lp_int_map::W`](W) writer structure"] +impl crate::Writable for MB_LP_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MB_LP_INT_MAP to value 0"] +impl crate::Resettable for MB_LP_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/pcnt_int_map.rs b/esp32p4/src/interrupt_core0/pcnt_int_map.rs new file mode 100644 index 0000000000..b92ba7cd3d --- /dev/null +++ b/esp32p4/src/interrupt_core0/pcnt_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PCNT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PCNT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_PCNT_INT_MAP` reader - NA"] +pub type CORE0_PCNT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_PCNT_INT_MAP` writer - NA"] +pub type CORE0_PCNT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_pcnt_int_map(&self) -> CORE0_PCNT_INT_MAP_R { + CORE0_PCNT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PCNT_INT_MAP") + .field( + "core0_pcnt_int_map", + &format_args!("{}", self.core0_pcnt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_pcnt_int_map(&mut self) -> CORE0_PCNT_INT_MAP_W { + CORE0_PCNT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcnt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcnt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PCNT_INT_MAP_SPEC; +impl crate::RegisterSpec for PCNT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcnt_int_map::R`](R) reader structure"] +impl crate::Readable for PCNT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pcnt_int_map::W`](W) writer structure"] +impl crate::Writable for PCNT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PCNT_INT_MAP to value 0"] +impl crate::Resettable for PCNT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/pmt_int_map.rs b/esp32p4/src/interrupt_core0/pmt_int_map.rs new file mode 100644 index 0000000000..3b00b319e7 --- /dev/null +++ b/esp32p4/src/interrupt_core0/pmt_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PMT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_PMT_INT_MAP` reader - NA"] +pub type CORE0_PMT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_PMT_INT_MAP` writer - NA"] +pub type CORE0_PMT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_pmt_int_map(&self) -> CORE0_PMT_INT_MAP_R { + CORE0_PMT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMT_INT_MAP") + .field( + "core0_pmt_int_map", + &format_args!("{}", self.core0_pmt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_pmt_int_map(&mut self) -> CORE0_PMT_INT_MAP_W { + CORE0_PMT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMT_INT_MAP_SPEC; +impl crate::RegisterSpec for PMT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmt_int_map::R`](R) reader structure"] +impl crate::Readable for PMT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmt_int_map::W`](W) writer structure"] +impl crate::Writable for PMT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMT_INT_MAP to value 0"] +impl crate::Resettable for PMT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/pmu_reg_0_int_map.rs b/esp32p4/src/interrupt_core0/pmu_reg_0_int_map.rs new file mode 100644 index 0000000000..e61ad61e65 --- /dev/null +++ b/esp32p4/src/interrupt_core0/pmu_reg_0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMU_REG_0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PMU_REG_0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_PMU_REG_0_INT_MAP` reader - NA"] +pub type CORE0_PMU_REG_0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_PMU_REG_0_INT_MAP` writer - NA"] +pub type CORE0_PMU_REG_0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_pmu_reg_0_int_map(&self) -> CORE0_PMU_REG_0_INT_MAP_R { + CORE0_PMU_REG_0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMU_REG_0_INT_MAP") + .field( + "core0_pmu_reg_0_int_map", + &format_args!("{}", self.core0_pmu_reg_0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_pmu_reg_0_int_map(&mut self) -> CORE0_PMU_REG_0_INT_MAP_W { + CORE0_PMU_REG_0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_reg_0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_reg_0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMU_REG_0_INT_MAP_SPEC; +impl crate::RegisterSpec for PMU_REG_0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmu_reg_0_int_map::R`](R) reader structure"] +impl crate::Readable for PMU_REG_0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmu_reg_0_int_map::W`](W) writer structure"] +impl crate::Writable for PMU_REG_0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMU_REG_0_INT_MAP to value 0"] +impl crate::Resettable for PMU_REG_0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/pmu_reg_1_int_map.rs b/esp32p4/src/interrupt_core0/pmu_reg_1_int_map.rs new file mode 100644 index 0000000000..1286aba848 --- /dev/null +++ b/esp32p4/src/interrupt_core0/pmu_reg_1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMU_REG_1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PMU_REG_1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_PMU_REG_1_INT_MAP` reader - NA"] +pub type CORE0_PMU_REG_1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_PMU_REG_1_INT_MAP` writer - NA"] +pub type CORE0_PMU_REG_1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_pmu_reg_1_int_map(&self) -> CORE0_PMU_REG_1_INT_MAP_R { + CORE0_PMU_REG_1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMU_REG_1_INT_MAP") + .field( + "core0_pmu_reg_1_int_map", + &format_args!("{}", self.core0_pmu_reg_1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_pmu_reg_1_int_map(&mut self) -> CORE0_PMU_REG_1_INT_MAP_W { + CORE0_PMU_REG_1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_reg_1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_reg_1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMU_REG_1_INT_MAP_SPEC; +impl crate::RegisterSpec for PMU_REG_1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmu_reg_1_int_map::R`](R) reader structure"] +impl crate::Readable for PMU_REG_1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmu_reg_1_int_map::W`](W) writer structure"] +impl crate::Writable for PMU_REG_1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMU_REG_1_INT_MAP to value 0"] +impl crate::Resettable for PMU_REG_1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/ppa_int_map.rs b/esp32p4/src/interrupt_core0/ppa_int_map.rs new file mode 100644 index 0000000000..6f5471748d --- /dev/null +++ b/esp32p4/src/interrupt_core0/ppa_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PPA_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PPA_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_PPA_INT_MAP` reader - NA"] +pub type CORE0_PPA_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_PPA_INT_MAP` writer - NA"] +pub type CORE0_PPA_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_ppa_int_map(&self) -> CORE0_PPA_INT_MAP_R { + CORE0_PPA_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PPA_INT_MAP") + .field( + "core0_ppa_int_map", + &format_args!("{}", self.core0_ppa_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_ppa_int_map(&mut self) -> CORE0_PPA_INT_MAP_W { + CORE0_PPA_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppa_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppa_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PPA_INT_MAP_SPEC; +impl crate::RegisterSpec for PPA_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ppa_int_map::R`](R) reader structure"] +impl crate::Readable for PPA_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ppa_int_map::W`](W) writer structure"] +impl crate::Writable for PPA_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PPA_INT_MAP to value 0"] +impl crate::Resettable for PPA_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/psram_mspi_int_map.rs b/esp32p4/src/interrupt_core0/psram_mspi_int_map.rs new file mode 100644 index 0000000000..00b2e3ef2e --- /dev/null +++ b/esp32p4/src/interrupt_core0/psram_mspi_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `PSRAM_MSPI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PSRAM_MSPI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_PSRAM_MSPI_INT_MAP` reader - NA"] +pub type CORE0_PSRAM_MSPI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_PSRAM_MSPI_INT_MAP` writer - NA"] +pub type CORE0_PSRAM_MSPI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_psram_mspi_int_map(&self) -> CORE0_PSRAM_MSPI_INT_MAP_R { + CORE0_PSRAM_MSPI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PSRAM_MSPI_INT_MAP") + .field( + "core0_psram_mspi_int_map", + &format_args!("{}", self.core0_psram_mspi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_psram_mspi_int_map( + &mut self, + ) -> CORE0_PSRAM_MSPI_INT_MAP_W { + CORE0_PSRAM_MSPI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psram_mspi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psram_mspi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PSRAM_MSPI_INT_MAP_SPEC; +impl crate::RegisterSpec for PSRAM_MSPI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`psram_mspi_int_map::R`](R) reader structure"] +impl crate::Readable for PSRAM_MSPI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`psram_mspi_int_map::W`](W) writer structure"] +impl crate::Writable for PSRAM_MSPI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PSRAM_MSPI_INT_MAP to value 0"] +impl crate::Resettable for PSRAM_MSPI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/pwm0_int_map.rs b/esp32p4/src/interrupt_core0/pwm0_int_map.rs new file mode 100644 index 0000000000..b5cffe02eb --- /dev/null +++ b/esp32p4/src/interrupt_core0/pwm0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PWM0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PWM0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_PWM0_INT_MAP` reader - NA"] +pub type CORE0_PWM0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_PWM0_INT_MAP` writer - NA"] +pub type CORE0_PWM0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_pwm0_int_map(&self) -> CORE0_PWM0_INT_MAP_R { + CORE0_PWM0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM0_INT_MAP") + .field( + "core0_pwm0_int_map", + &format_args!("{}", self.core0_pwm0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_pwm0_int_map(&mut self) -> CORE0_PWM0_INT_MAP_W { + CORE0_PWM0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWM0_INT_MAP_SPEC; +impl crate::RegisterSpec for PWM0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm0_int_map::R`](R) reader structure"] +impl crate::Readable for PWM0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwm0_int_map::W`](W) writer structure"] +impl crate::Writable for PWM0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PWM0_INT_MAP to value 0"] +impl crate::Resettable for PWM0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/pwm1_int_map.rs b/esp32p4/src/interrupt_core0/pwm1_int_map.rs new file mode 100644 index 0000000000..6b1b965cee --- /dev/null +++ b/esp32p4/src/interrupt_core0/pwm1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PWM1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PWM1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_PWM1_INT_MAP` reader - NA"] +pub type CORE0_PWM1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_PWM1_INT_MAP` writer - NA"] +pub type CORE0_PWM1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_pwm1_int_map(&self) -> CORE0_PWM1_INT_MAP_R { + CORE0_PWM1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM1_INT_MAP") + .field( + "core0_pwm1_int_map", + &format_args!("{}", self.core0_pwm1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_pwm1_int_map(&mut self) -> CORE0_PWM1_INT_MAP_W { + CORE0_PWM1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWM1_INT_MAP_SPEC; +impl crate::RegisterSpec for PWM1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm1_int_map::R`](R) reader structure"] +impl crate::Readable for PWM1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwm1_int_map::W`](W) writer structure"] +impl crate::Writable for PWM1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PWM1_INT_MAP to value 0"] +impl crate::Resettable for PWM1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/rmt_int_map.rs b/esp32p4/src/interrupt_core0/rmt_int_map.rs new file mode 100644 index 0000000000..fdd4321859 --- /dev/null +++ b/esp32p4/src/interrupt_core0/rmt_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RMT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `RMT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_RMT_INT_MAP` reader - NA"] +pub type CORE0_RMT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_RMT_INT_MAP` writer - NA"] +pub type CORE0_RMT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_rmt_int_map(&self) -> CORE0_RMT_INT_MAP_R { + CORE0_RMT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RMT_INT_MAP") + .field( + "core0_rmt_int_map", + &format_args!("{}", self.core0_rmt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_rmt_int_map(&mut self) -> CORE0_RMT_INT_MAP_W { + CORE0_RMT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rmt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rmt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RMT_INT_MAP_SPEC; +impl crate::RegisterSpec for RMT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rmt_int_map::R`](R) reader structure"] +impl crate::Readable for RMT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rmt_int_map::W`](W) writer structure"] +impl crate::Writable for RMT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RMT_INT_MAP to value 0"] +impl crate::Resettable for RMT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/rsa_int_map.rs b/esp32p4/src/interrupt_core0/rsa_int_map.rs new file mode 100644 index 0000000000..a026822634 --- /dev/null +++ b/esp32p4/src/interrupt_core0/rsa_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RSA_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `RSA_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_RSA_INT_MAP` reader - NA"] +pub type CORE0_RSA_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_RSA_INT_MAP` writer - NA"] +pub type CORE0_RSA_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_rsa_int_map(&self) -> CORE0_RSA_INT_MAP_R { + CORE0_RSA_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSA_INT_MAP") + .field( + "core0_rsa_int_map", + &format_args!("{}", self.core0_rsa_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_rsa_int_map(&mut self) -> CORE0_RSA_INT_MAP_W { + CORE0_RSA_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsa_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsa_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RSA_INT_MAP_SPEC; +impl crate::RegisterSpec for RSA_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rsa_int_map::R`](R) reader structure"] +impl crate::Readable for RSA_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rsa_int_map::W`](W) writer structure"] +impl crate::Writable for RSA_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RSA_INT_MAP to value 0"] +impl crate::Resettable for RSA_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/sbd_int_map.rs b/esp32p4/src/interrupt_core0/sbd_int_map.rs new file mode 100644 index 0000000000..cf5210f6e7 --- /dev/null +++ b/esp32p4/src/interrupt_core0/sbd_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SBD_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SBD_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_SBD_INT_MAP` reader - NA"] +pub type CORE0_SBD_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_SBD_INT_MAP` writer - NA"] +pub type CORE0_SBD_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_sbd_int_map(&self) -> CORE0_SBD_INT_MAP_R { + CORE0_SBD_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SBD_INT_MAP") + .field( + "core0_sbd_int_map", + &format_args!("{}", self.core0_sbd_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_sbd_int_map(&mut self) -> CORE0_SBD_INT_MAP_W { + CORE0_SBD_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbd_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbd_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBD_INT_MAP_SPEC; +impl crate::RegisterSpec for SBD_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbd_int_map::R`](R) reader structure"] +impl crate::Readable for SBD_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbd_int_map::W`](W) writer structure"] +impl crate::Writable for SBD_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SBD_INT_MAP to value 0"] +impl crate::Resettable for SBD_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/sdio_host_int_map.rs b/esp32p4/src/interrupt_core0/sdio_host_int_map.rs new file mode 100644 index 0000000000..afe46c53ec --- /dev/null +++ b/esp32p4/src/interrupt_core0/sdio_host_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SDIO_HOST_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SDIO_HOST_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_SDIO_HOST_INT_MAP` reader - NA"] +pub type CORE0_SDIO_HOST_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_SDIO_HOST_INT_MAP` writer - NA"] +pub type CORE0_SDIO_HOST_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_sdio_host_int_map(&self) -> CORE0_SDIO_HOST_INT_MAP_R { + CORE0_SDIO_HOST_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDIO_HOST_INT_MAP") + .field( + "core0_sdio_host_int_map", + &format_args!("{}", self.core0_sdio_host_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_sdio_host_int_map(&mut self) -> CORE0_SDIO_HOST_INT_MAP_W { + CORE0_SDIO_HOST_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdio_host_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdio_host_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDIO_HOST_INT_MAP_SPEC; +impl crate::RegisterSpec for SDIO_HOST_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sdio_host_int_map::R`](R) reader structure"] +impl crate::Readable for SDIO_HOST_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sdio_host_int_map::W`](W) writer structure"] +impl crate::Writable for SDIO_HOST_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDIO_HOST_INT_MAP to value 0"] +impl crate::Resettable for SDIO_HOST_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/sha_int_map.rs b/esp32p4/src/interrupt_core0/sha_int_map.rs new file mode 100644 index 0000000000..339dd0786f --- /dev/null +++ b/esp32p4/src/interrupt_core0/sha_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SHA_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SHA_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_SHA_INT_MAP` reader - NA"] +pub type CORE0_SHA_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_SHA_INT_MAP` writer - NA"] +pub type CORE0_SHA_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_sha_int_map(&self) -> CORE0_SHA_INT_MAP_R { + CORE0_SHA_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHA_INT_MAP") + .field( + "core0_sha_int_map", + &format_args!("{}", self.core0_sha_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_sha_int_map(&mut self) -> CORE0_SHA_INT_MAP_W { + CORE0_SHA_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sha_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHA_INT_MAP_SPEC; +impl crate::RegisterSpec for SHA_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sha_int_map::R`](R) reader structure"] +impl crate::Readable for SHA_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sha_int_map::W`](W) writer structure"] +impl crate::Writable for SHA_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SHA_INT_MAP to value 0"] +impl crate::Resettable for SHA_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/spi2_int_map.rs b/esp32p4/src/interrupt_core0/spi2_int_map.rs new file mode 100644 index 0000000000..c3b404959f --- /dev/null +++ b/esp32p4/src/interrupt_core0/spi2_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SPI2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_SPI2_INT_MAP` reader - NA"] +pub type CORE0_SPI2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_SPI2_INT_MAP` writer - NA"] +pub type CORE0_SPI2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_spi2_int_map(&self) -> CORE0_SPI2_INT_MAP_R { + CORE0_SPI2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI2_INT_MAP") + .field( + "core0_spi2_int_map", + &format_args!("{}", self.core0_spi2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_spi2_int_map(&mut self) -> CORE0_SPI2_INT_MAP_W { + CORE0_SPI2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI2_INT_MAP_SPEC; +impl crate::RegisterSpec for SPI2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi2_int_map::R`](R) reader structure"] +impl crate::Readable for SPI2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi2_int_map::W`](W) writer structure"] +impl crate::Writable for SPI2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI2_INT_MAP to value 0"] +impl crate::Resettable for SPI2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/spi3_int_map.rs b/esp32p4/src/interrupt_core0/spi3_int_map.rs new file mode 100644 index 0000000000..aada9696b8 --- /dev/null +++ b/esp32p4/src/interrupt_core0/spi3_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI3_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SPI3_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_SPI3_INT_MAP` reader - NA"] +pub type CORE0_SPI3_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_SPI3_INT_MAP` writer - NA"] +pub type CORE0_SPI3_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_spi3_int_map(&self) -> CORE0_SPI3_INT_MAP_R { + CORE0_SPI3_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI3_INT_MAP") + .field( + "core0_spi3_int_map", + &format_args!("{}", self.core0_spi3_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_spi3_int_map(&mut self) -> CORE0_SPI3_INT_MAP_W { + CORE0_SPI3_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi3_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi3_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI3_INT_MAP_SPEC; +impl crate::RegisterSpec for SPI3_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi3_int_map::R`](R) reader structure"] +impl crate::Readable for SPI3_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi3_int_map::W`](W) writer structure"] +impl crate::Writable for SPI3_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI3_INT_MAP to value 0"] +impl crate::Resettable for SPI3_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/sys_icm_int_map.rs b/esp32p4/src/interrupt_core0/sys_icm_int_map.rs new file mode 100644 index 0000000000..ab622c5e78 --- /dev/null +++ b/esp32p4/src/interrupt_core0/sys_icm_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SYS_ICM_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SYS_ICM_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_SYS_ICM_INT_MAP` reader - NA"] +pub type CORE0_SYS_ICM_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_SYS_ICM_INT_MAP` writer - NA"] +pub type CORE0_SYS_ICM_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_sys_icm_int_map(&self) -> CORE0_SYS_ICM_INT_MAP_R { + CORE0_SYS_ICM_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYS_ICM_INT_MAP") + .field( + "core0_sys_icm_int_map", + &format_args!("{}", self.core0_sys_icm_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_sys_icm_int_map(&mut self) -> CORE0_SYS_ICM_INT_MAP_W { + CORE0_SYS_ICM_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_icm_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_icm_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYS_ICM_INT_MAP_SPEC; +impl crate::RegisterSpec for SYS_ICM_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sys_icm_int_map::R`](R) reader structure"] +impl crate::Readable for SYS_ICM_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sys_icm_int_map::W`](W) writer structure"] +impl crate::Writable for SYS_ICM_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYS_ICM_INT_MAP to value 0"] +impl crate::Resettable for SYS_ICM_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/systimer_target0_int_map.rs b/esp32p4/src/interrupt_core0/systimer_target0_int_map.rs new file mode 100644 index 0000000000..d29810fd13 --- /dev/null +++ b/esp32p4/src/interrupt_core0/systimer_target0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SYSTIMER_TARGET0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SYSTIMER_TARGET0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_SYSTIMER_TARGET0_INT_MAP` reader - NA"] +pub type CORE0_SYSTIMER_TARGET0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_SYSTIMER_TARGET0_INT_MAP` writer - NA"] +pub type CORE0_SYSTIMER_TARGET0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_systimer_target0_int_map(&self) -> CORE0_SYSTIMER_TARGET0_INT_MAP_R { + CORE0_SYSTIMER_TARGET0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTIMER_TARGET0_INT_MAP") + .field( + "core0_systimer_target0_int_map", + &format_args!("{}", self.core0_systimer_target0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_systimer_target0_int_map( + &mut self, + ) -> CORE0_SYSTIMER_TARGET0_INT_MAP_W { + CORE0_SYSTIMER_TARGET0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYSTIMER_TARGET0_INT_MAP_SPEC; +impl crate::RegisterSpec for SYSTIMER_TARGET0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`systimer_target0_int_map::R`](R) reader structure"] +impl crate::Readable for SYSTIMER_TARGET0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`systimer_target0_int_map::W`](W) writer structure"] +impl crate::Writable for SYSTIMER_TARGET0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYSTIMER_TARGET0_INT_MAP to value 0"] +impl crate::Resettable for SYSTIMER_TARGET0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/systimer_target1_int_map.rs b/esp32p4/src/interrupt_core0/systimer_target1_int_map.rs new file mode 100644 index 0000000000..9aa2ae90c7 --- /dev/null +++ b/esp32p4/src/interrupt_core0/systimer_target1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SYSTIMER_TARGET1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SYSTIMER_TARGET1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_SYSTIMER_TARGET1_INT_MAP` reader - NA"] +pub type CORE0_SYSTIMER_TARGET1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_SYSTIMER_TARGET1_INT_MAP` writer - NA"] +pub type CORE0_SYSTIMER_TARGET1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_systimer_target1_int_map(&self) -> CORE0_SYSTIMER_TARGET1_INT_MAP_R { + CORE0_SYSTIMER_TARGET1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTIMER_TARGET1_INT_MAP") + .field( + "core0_systimer_target1_int_map", + &format_args!("{}", self.core0_systimer_target1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_systimer_target1_int_map( + &mut self, + ) -> CORE0_SYSTIMER_TARGET1_INT_MAP_W { + CORE0_SYSTIMER_TARGET1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYSTIMER_TARGET1_INT_MAP_SPEC; +impl crate::RegisterSpec for SYSTIMER_TARGET1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`systimer_target1_int_map::R`](R) reader structure"] +impl crate::Readable for SYSTIMER_TARGET1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`systimer_target1_int_map::W`](W) writer structure"] +impl crate::Writable for SYSTIMER_TARGET1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYSTIMER_TARGET1_INT_MAP to value 0"] +impl crate::Resettable for SYSTIMER_TARGET1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/systimer_target2_int_map.rs b/esp32p4/src/interrupt_core0/systimer_target2_int_map.rs new file mode 100644 index 0000000000..cf7ede2a1d --- /dev/null +++ b/esp32p4/src/interrupt_core0/systimer_target2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SYSTIMER_TARGET2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SYSTIMER_TARGET2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_SYSTIMER_TARGET2_INT_MAP` reader - NA"] +pub type CORE0_SYSTIMER_TARGET2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_SYSTIMER_TARGET2_INT_MAP` writer - NA"] +pub type CORE0_SYSTIMER_TARGET2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_systimer_target2_int_map(&self) -> CORE0_SYSTIMER_TARGET2_INT_MAP_R { + CORE0_SYSTIMER_TARGET2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTIMER_TARGET2_INT_MAP") + .field( + "core0_systimer_target2_int_map", + &format_args!("{}", self.core0_systimer_target2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_systimer_target2_int_map( + &mut self, + ) -> CORE0_SYSTIMER_TARGET2_INT_MAP_W { + CORE0_SYSTIMER_TARGET2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYSTIMER_TARGET2_INT_MAP_SPEC; +impl crate::RegisterSpec for SYSTIMER_TARGET2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`systimer_target2_int_map::R`](R) reader structure"] +impl crate::Readable for SYSTIMER_TARGET2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`systimer_target2_int_map::W`](W) writer structure"] +impl crate::Writable for SYSTIMER_TARGET2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYSTIMER_TARGET2_INT_MAP to value 0"] +impl crate::Resettable for SYSTIMER_TARGET2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/timergrp0_t0_int_map.rs b/esp32p4/src/interrupt_core0/timergrp0_t0_int_map.rs new file mode 100644 index 0000000000..2d42795d9f --- /dev/null +++ b/esp32p4/src/interrupt_core0/timergrp0_t0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP0_T0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP0_T0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_TIMERGRP0_T0_INT_MAP` reader - NA"] +pub type CORE0_TIMERGRP0_T0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_TIMERGRP0_T0_INT_MAP` writer - NA"] +pub type CORE0_TIMERGRP0_T0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_timergrp0_t0_int_map(&self) -> CORE0_TIMERGRP0_T0_INT_MAP_R { + CORE0_TIMERGRP0_T0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP0_T0_INT_MAP") + .field( + "core0_timergrp0_t0_int_map", + &format_args!("{}", self.core0_timergrp0_t0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_timergrp0_t0_int_map( + &mut self, + ) -> CORE0_TIMERGRP0_T0_INT_MAP_W { + CORE0_TIMERGRP0_T0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_t0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_t0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP0_T0_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP0_T0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp0_t0_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP0_T0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp0_t0_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP0_T0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP0_T0_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP0_T0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/timergrp0_t1_int_map.rs b/esp32p4/src/interrupt_core0/timergrp0_t1_int_map.rs new file mode 100644 index 0000000000..0a6d966727 --- /dev/null +++ b/esp32p4/src/interrupt_core0/timergrp0_t1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP0_T1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP0_T1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_TIMERGRP0_T1_INT_MAP` reader - NA"] +pub type CORE0_TIMERGRP0_T1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_TIMERGRP0_T1_INT_MAP` writer - NA"] +pub type CORE0_TIMERGRP0_T1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_timergrp0_t1_int_map(&self) -> CORE0_TIMERGRP0_T1_INT_MAP_R { + CORE0_TIMERGRP0_T1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP0_T1_INT_MAP") + .field( + "core0_timergrp0_t1_int_map", + &format_args!("{}", self.core0_timergrp0_t1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_timergrp0_t1_int_map( + &mut self, + ) -> CORE0_TIMERGRP0_T1_INT_MAP_W { + CORE0_TIMERGRP0_T1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_t1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_t1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP0_T1_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP0_T1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp0_t1_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP0_T1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp0_t1_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP0_T1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP0_T1_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP0_T1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/timergrp0_wdt_int_map.rs b/esp32p4/src/interrupt_core0/timergrp0_wdt_int_map.rs new file mode 100644 index 0000000000..768bd7b58e --- /dev/null +++ b/esp32p4/src/interrupt_core0/timergrp0_wdt_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP0_WDT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP0_WDT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_TIMERGRP0_WDT_INT_MAP` reader - NA"] +pub type CORE0_TIMERGRP0_WDT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_TIMERGRP0_WDT_INT_MAP` writer - NA"] +pub type CORE0_TIMERGRP0_WDT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_timergrp0_wdt_int_map(&self) -> CORE0_TIMERGRP0_WDT_INT_MAP_R { + CORE0_TIMERGRP0_WDT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP0_WDT_INT_MAP") + .field( + "core0_timergrp0_wdt_int_map", + &format_args!("{}", self.core0_timergrp0_wdt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_timergrp0_wdt_int_map( + &mut self, + ) -> CORE0_TIMERGRP0_WDT_INT_MAP_W { + CORE0_TIMERGRP0_WDT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_wdt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_wdt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP0_WDT_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP0_WDT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp0_wdt_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP0_WDT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp0_wdt_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP0_WDT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP0_WDT_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP0_WDT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/timergrp1_t0_int_map.rs b/esp32p4/src/interrupt_core0/timergrp1_t0_int_map.rs new file mode 100644 index 0000000000..e1e1c90c5c --- /dev/null +++ b/esp32p4/src/interrupt_core0/timergrp1_t0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP1_T0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP1_T0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_TIMERGRP1_T0_INT_MAP` reader - NA"] +pub type CORE0_TIMERGRP1_T0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_TIMERGRP1_T0_INT_MAP` writer - NA"] +pub type CORE0_TIMERGRP1_T0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_timergrp1_t0_int_map(&self) -> CORE0_TIMERGRP1_T0_INT_MAP_R { + CORE0_TIMERGRP1_T0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP1_T0_INT_MAP") + .field( + "core0_timergrp1_t0_int_map", + &format_args!("{}", self.core0_timergrp1_t0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_timergrp1_t0_int_map( + &mut self, + ) -> CORE0_TIMERGRP1_T0_INT_MAP_W { + CORE0_TIMERGRP1_T0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_t0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_t0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP1_T0_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP1_T0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp1_t0_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP1_T0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp1_t0_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP1_T0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP1_T0_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP1_T0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/timergrp1_t1_int_map.rs b/esp32p4/src/interrupt_core0/timergrp1_t1_int_map.rs new file mode 100644 index 0000000000..abc18d62a7 --- /dev/null +++ b/esp32p4/src/interrupt_core0/timergrp1_t1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP1_T1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP1_T1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_TIMERGRP1_T1_INT_MAP` reader - NA"] +pub type CORE0_TIMERGRP1_T1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_TIMERGRP1_T1_INT_MAP` writer - NA"] +pub type CORE0_TIMERGRP1_T1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_timergrp1_t1_int_map(&self) -> CORE0_TIMERGRP1_T1_INT_MAP_R { + CORE0_TIMERGRP1_T1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP1_T1_INT_MAP") + .field( + "core0_timergrp1_t1_int_map", + &format_args!("{}", self.core0_timergrp1_t1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_timergrp1_t1_int_map( + &mut self, + ) -> CORE0_TIMERGRP1_T1_INT_MAP_W { + CORE0_TIMERGRP1_T1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_t1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_t1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP1_T1_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP1_T1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp1_t1_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP1_T1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp1_t1_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP1_T1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP1_T1_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP1_T1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/timergrp1_wdt_int_map.rs b/esp32p4/src/interrupt_core0/timergrp1_wdt_int_map.rs new file mode 100644 index 0000000000..c92c1b113e --- /dev/null +++ b/esp32p4/src/interrupt_core0/timergrp1_wdt_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP1_WDT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP1_WDT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_TIMERGRP1_WDT_INT_MAP` reader - NA"] +pub type CORE0_TIMERGRP1_WDT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_TIMERGRP1_WDT_INT_MAP` writer - NA"] +pub type CORE0_TIMERGRP1_WDT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_timergrp1_wdt_int_map(&self) -> CORE0_TIMERGRP1_WDT_INT_MAP_R { + CORE0_TIMERGRP1_WDT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP1_WDT_INT_MAP") + .field( + "core0_timergrp1_wdt_int_map", + &format_args!("{}", self.core0_timergrp1_wdt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_timergrp1_wdt_int_map( + &mut self, + ) -> CORE0_TIMERGRP1_WDT_INT_MAP_W { + CORE0_TIMERGRP1_WDT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_wdt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_wdt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP1_WDT_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP1_WDT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp1_wdt_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP1_WDT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp1_wdt_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP1_WDT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP1_WDT_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP1_WDT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/uart0_int_map.rs b/esp32p4/src/interrupt_core0/uart0_int_map.rs new file mode 100644 index 0000000000..7786bfadd9 --- /dev/null +++ b/esp32p4/src/interrupt_core0/uart0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UART0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UART0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_UART0_INT_MAP` reader - NA"] +pub type CORE0_UART0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_UART0_INT_MAP` writer - NA"] +pub type CORE0_UART0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_uart0_int_map(&self) -> CORE0_UART0_INT_MAP_R { + CORE0_UART0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART0_INT_MAP") + .field( + "core0_uart0_int_map", + &format_args!("{}", self.core0_uart0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_uart0_int_map(&mut self) -> CORE0_UART0_INT_MAP_W { + CORE0_UART0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART0_INT_MAP_SPEC; +impl crate::RegisterSpec for UART0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart0_int_map::R`](R) reader structure"] +impl crate::Readable for UART0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart0_int_map::W`](W) writer structure"] +impl crate::Writable for UART0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UART0_INT_MAP to value 0"] +impl crate::Resettable for UART0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/uart1_int_map.rs b/esp32p4/src/interrupt_core0/uart1_int_map.rs new file mode 100644 index 0000000000..5639c124cd --- /dev/null +++ b/esp32p4/src/interrupt_core0/uart1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UART1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UART1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_UART1_INT_MAP` reader - NA"] +pub type CORE0_UART1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_UART1_INT_MAP` writer - NA"] +pub type CORE0_UART1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_uart1_int_map(&self) -> CORE0_UART1_INT_MAP_R { + CORE0_UART1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART1_INT_MAP") + .field( + "core0_uart1_int_map", + &format_args!("{}", self.core0_uart1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_uart1_int_map(&mut self) -> CORE0_UART1_INT_MAP_W { + CORE0_UART1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART1_INT_MAP_SPEC; +impl crate::RegisterSpec for UART1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart1_int_map::R`](R) reader structure"] +impl crate::Readable for UART1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart1_int_map::W`](W) writer structure"] +impl crate::Writable for UART1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UART1_INT_MAP to value 0"] +impl crate::Resettable for UART1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/uart2_int_map.rs b/esp32p4/src/interrupt_core0/uart2_int_map.rs new file mode 100644 index 0000000000..ea239ac710 --- /dev/null +++ b/esp32p4/src/interrupt_core0/uart2_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UART2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UART2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_UART2_INT_MAP` reader - NA"] +pub type CORE0_UART2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_UART2_INT_MAP` writer - NA"] +pub type CORE0_UART2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_uart2_int_map(&self) -> CORE0_UART2_INT_MAP_R { + CORE0_UART2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART2_INT_MAP") + .field( + "core0_uart2_int_map", + &format_args!("{}", self.core0_uart2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_uart2_int_map(&mut self) -> CORE0_UART2_INT_MAP_W { + CORE0_UART2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART2_INT_MAP_SPEC; +impl crate::RegisterSpec for UART2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart2_int_map::R`](R) reader structure"] +impl crate::Readable for UART2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart2_int_map::W`](W) writer structure"] +impl crate::Writable for UART2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UART2_INT_MAP to value 0"] +impl crate::Resettable for UART2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/uart3_int_map.rs b/esp32p4/src/interrupt_core0/uart3_int_map.rs new file mode 100644 index 0000000000..091fa1e09e --- /dev/null +++ b/esp32p4/src/interrupt_core0/uart3_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UART3_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UART3_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_UART3_INT_MAP` reader - NA"] +pub type CORE0_UART3_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_UART3_INT_MAP` writer - NA"] +pub type CORE0_UART3_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_uart3_int_map(&self) -> CORE0_UART3_INT_MAP_R { + CORE0_UART3_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART3_INT_MAP") + .field( + "core0_uart3_int_map", + &format_args!("{}", self.core0_uart3_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_uart3_int_map(&mut self) -> CORE0_UART3_INT_MAP_W { + CORE0_UART3_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart3_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart3_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART3_INT_MAP_SPEC; +impl crate::RegisterSpec for UART3_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart3_int_map::R`](R) reader structure"] +impl crate::Readable for UART3_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart3_int_map::W`](W) writer structure"] +impl crate::Writable for UART3_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UART3_INT_MAP to value 0"] +impl crate::Resettable for UART3_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/uart4_int_map.rs b/esp32p4/src/interrupt_core0/uart4_int_map.rs new file mode 100644 index 0000000000..21b75fa589 --- /dev/null +++ b/esp32p4/src/interrupt_core0/uart4_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UART4_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UART4_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_UART4_INT_MAP` reader - NA"] +pub type CORE0_UART4_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_UART4_INT_MAP` writer - NA"] +pub type CORE0_UART4_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_uart4_int_map(&self) -> CORE0_UART4_INT_MAP_R { + CORE0_UART4_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART4_INT_MAP") + .field( + "core0_uart4_int_map", + &format_args!("{}", self.core0_uart4_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_uart4_int_map(&mut self) -> CORE0_UART4_INT_MAP_W { + CORE0_UART4_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart4_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart4_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART4_INT_MAP_SPEC; +impl crate::RegisterSpec for UART4_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart4_int_map::R`](R) reader structure"] +impl crate::Readable for UART4_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart4_int_map::W`](W) writer structure"] +impl crate::Writable for UART4_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UART4_INT_MAP to value 0"] +impl crate::Resettable for UART4_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/uhci0_int_map.rs b/esp32p4/src/interrupt_core0/uhci0_int_map.rs new file mode 100644 index 0000000000..8426b0b1c2 --- /dev/null +++ b/esp32p4/src/interrupt_core0/uhci0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UHCI0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UHCI0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_UHCI0_INT_MAP` reader - NA"] +pub type CORE0_UHCI0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_UHCI0_INT_MAP` writer - NA"] +pub type CORE0_UHCI0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_uhci0_int_map(&self) -> CORE0_UHCI0_INT_MAP_R { + CORE0_UHCI0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UHCI0_INT_MAP") + .field( + "core0_uhci0_int_map", + &format_args!("{}", self.core0_uhci0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_uhci0_int_map(&mut self) -> CORE0_UHCI0_INT_MAP_W { + CORE0_UHCI0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uhci0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uhci0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UHCI0_INT_MAP_SPEC; +impl crate::RegisterSpec for UHCI0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uhci0_int_map::R`](R) reader structure"] +impl crate::Readable for UHCI0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uhci0_int_map::W`](W) writer structure"] +impl crate::Writable for UHCI0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UHCI0_INT_MAP to value 0"] +impl crate::Resettable for UHCI0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/usb_device_int_map.rs b/esp32p4/src/interrupt_core0/usb_device_int_map.rs new file mode 100644 index 0000000000..00add51c75 --- /dev/null +++ b/esp32p4/src/interrupt_core0/usb_device_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `USB_DEVICE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `USB_DEVICE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_USB_DEVICE_INT_MAP` reader - NA"] +pub type CORE0_USB_DEVICE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_USB_DEVICE_INT_MAP` writer - NA"] +pub type CORE0_USB_DEVICE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_usb_device_int_map(&self) -> CORE0_USB_DEVICE_INT_MAP_R { + CORE0_USB_DEVICE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_DEVICE_INT_MAP") + .field( + "core0_usb_device_int_map", + &format_args!("{}", self.core0_usb_device_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_usb_device_int_map( + &mut self, + ) -> CORE0_USB_DEVICE_INT_MAP_W { + CORE0_USB_DEVICE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_device_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_device_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_DEVICE_INT_MAP_SPEC; +impl crate::RegisterSpec for USB_DEVICE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_device_int_map::R`](R) reader structure"] +impl crate::Readable for USB_DEVICE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_device_int_map::W`](W) writer structure"] +impl crate::Writable for USB_DEVICE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USB_DEVICE_INT_MAP to value 0"] +impl crate::Resettable for USB_DEVICE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/usb_otg11_int_map.rs b/esp32p4/src/interrupt_core0/usb_otg11_int_map.rs new file mode 100644 index 0000000000..699b0e62b6 --- /dev/null +++ b/esp32p4/src/interrupt_core0/usb_otg11_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `USB_OTG11_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `USB_OTG11_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_USB_OTG11_INT_MAP` reader - NA"] +pub type CORE0_USB_OTG11_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_USB_OTG11_INT_MAP` writer - NA"] +pub type CORE0_USB_OTG11_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_usb_otg11_int_map(&self) -> CORE0_USB_OTG11_INT_MAP_R { + CORE0_USB_OTG11_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG11_INT_MAP") + .field( + "core0_usb_otg11_int_map", + &format_args!("{}", self.core0_usb_otg11_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_usb_otg11_int_map(&mut self) -> CORE0_USB_OTG11_INT_MAP_W { + CORE0_USB_OTG11_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg11_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg11_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_OTG11_INT_MAP_SPEC; +impl crate::RegisterSpec for USB_OTG11_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_otg11_int_map::R`](R) reader structure"] +impl crate::Readable for USB_OTG11_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_otg11_int_map::W`](W) writer structure"] +impl crate::Writable for USB_OTG11_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USB_OTG11_INT_MAP to value 0"] +impl crate::Resettable for USB_OTG11_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/usb_otg_endp_multi_proc_int_map.rs b/esp32p4/src/interrupt_core0/usb_otg_endp_multi_proc_int_map.rs new file mode 100644 index 0000000000..195664fb8e --- /dev/null +++ b/esp32p4/src/interrupt_core0/usb_otg_endp_multi_proc_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `USB_OTG_ENDP_MULTI_PROC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `USB_OTG_ENDP_MULTI_PROC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP` reader - NA"] +pub type CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP` writer - NA"] +pub type CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_usb_otg_endp_multi_proc_int_map(&self) -> CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_R { + CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_ENDP_MULTI_PROC_INT_MAP") + .field( + "core0_usb_otg_endp_multi_proc_int_map", + &format_args!("{}", self.core0_usb_otg_endp_multi_proc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_usb_otg_endp_multi_proc_int_map( + &mut self, + ) -> CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_W { + CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg_endp_multi_proc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg_endp_multi_proc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC; +impl crate::RegisterSpec for USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_otg_endp_multi_proc_int_map::R`](R) reader structure"] +impl crate::Readable for USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_otg_endp_multi_proc_int_map::W`](W) writer structure"] +impl crate::Writable for USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USB_OTG_ENDP_MULTI_PROC_INT_MAP to value 0"] +impl crate::Resettable for USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core0/usb_otg_int_map.rs b/esp32p4/src/interrupt_core0/usb_otg_int_map.rs new file mode 100644 index 0000000000..46962010fd --- /dev/null +++ b/esp32p4/src/interrupt_core0/usb_otg_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `USB_OTG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `USB_OTG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_USB_OTG_INT_MAP` reader - NA"] +pub type CORE0_USB_OTG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE0_USB_OTG_INT_MAP` writer - NA"] +pub type CORE0_USB_OTG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core0_usb_otg_int_map(&self) -> CORE0_USB_OTG_INT_MAP_R { + CORE0_USB_OTG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_INT_MAP") + .field( + "core0_usb_otg_int_map", + &format_args!("{}", self.core0_usb_otg_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core0_usb_otg_int_map(&mut self) -> CORE0_USB_OTG_INT_MAP_W { + CORE0_USB_OTG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_OTG_INT_MAP_SPEC; +impl crate::RegisterSpec for USB_OTG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_otg_int_map::R`](R) reader structure"] +impl crate::Readable for USB_OTG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_otg_int_map::W`](W) writer structure"] +impl crate::Writable for USB_OTG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USB_OTG_INT_MAP to value 0"] +impl crate::Resettable for USB_OTG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1.rs b/esp32p4/src/interrupt_core1.rs new file mode 100644 index 0000000000..064a8d256b --- /dev/null +++ b/esp32p4/src/interrupt_core1.rs @@ -0,0 +1,1375 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + lp_rtc_int_map: LP_RTC_INT_MAP, + lp_wdt_int_map: LP_WDT_INT_MAP, + lp_timer_reg_0_int_map: LP_TIMER_REG_0_INT_MAP, + lp_timer_reg_1_int_map: LP_TIMER_REG_1_INT_MAP, + mb_hp_int_map: MB_HP_INT_MAP, + mb_lp_int_map: MB_LP_INT_MAP, + pmu_reg_0_int_map: PMU_REG_0_INT_MAP, + pmu_reg_1_int_map: PMU_REG_1_INT_MAP, + lp_anaperi_int_map: LP_ANAPERI_INT_MAP, + lp_adc_int_map: LP_ADC_INT_MAP, + lp_gpio_int_map: LP_GPIO_INT_MAP, + lp_i2c_int_map: LP_I2C_INT_MAP, + lp_i2s_int_map: LP_I2S_INT_MAP, + lp_spi_int_map: LP_SPI_INT_MAP, + lp_touch_int_map: LP_TOUCH_INT_MAP, + lp_tsens_int_map: LP_TSENS_INT_MAP, + lp_uart_int_map: LP_UART_INT_MAP, + lp_efuse_int_map: LP_EFUSE_INT_MAP, + lp_sw_int_map: LP_SW_INT_MAP, + lp_sysreg_int_map: LP_SYSREG_INT_MAP, + lp_huk_int_map: LP_HUK_INT_MAP, + sys_icm_int_map: SYS_ICM_INT_MAP, + usb_device_int_map: USB_DEVICE_INT_MAP, + sdio_host_int_map: SDIO_HOST_INT_MAP, + gdma_int_map: GDMA_INT_MAP, + spi2_int_map: SPI2_INT_MAP, + spi3_int_map: SPI3_INT_MAP, + i2s0_int_map: I2S0_INT_MAP, + i2s1_int_map: I2S1_INT_MAP, + i2s2_int_map: I2S2_INT_MAP, + uhci0_int_map: UHCI0_INT_MAP, + uart0_int_map: UART0_INT_MAP, + uart1_int_map: UART1_INT_MAP, + uart2_int_map: UART2_INT_MAP, + uart3_int_map: UART3_INT_MAP, + uart4_int_map: UART4_INT_MAP, + lcd_cam_int_map: LCD_CAM_INT_MAP, + adc_int_map: ADC_INT_MAP, + pwm0_int_map: PWM0_INT_MAP, + pwm1_int_map: PWM1_INT_MAP, + can0_int_map: CAN0_INT_MAP, + can1_int_map: CAN1_INT_MAP, + can2_int_map: CAN2_INT_MAP, + rmt_int_map: RMT_INT_MAP, + i2c0_int_map: I2C0_INT_MAP, + i2c1_int_map: I2C1_INT_MAP, + timergrp0_t0_int_map: TIMERGRP0_T0_INT_MAP, + timergrp0_t1_int_map: TIMERGRP0_T1_INT_MAP, + timergrp0_wdt_int_map: TIMERGRP0_WDT_INT_MAP, + timergrp1_t0_int_map: TIMERGRP1_T0_INT_MAP, + timergrp1_t1_int_map: TIMERGRP1_T1_INT_MAP, + timergrp1_wdt_int_map: TIMERGRP1_WDT_INT_MAP, + ledc_int_map: LEDC_INT_MAP, + systimer_target0_int_map: SYSTIMER_TARGET0_INT_MAP, + systimer_target1_int_map: SYSTIMER_TARGET1_INT_MAP, + systimer_target2_int_map: SYSTIMER_TARGET2_INT_MAP, + ahb_pdma_in_ch0_int_map: AHB_PDMA_IN_CH0_INT_MAP, + ahb_pdma_in_ch1_int_map: AHB_PDMA_IN_CH1_INT_MAP, + ahb_pdma_in_ch2_int_map: AHB_PDMA_IN_CH2_INT_MAP, + ahb_pdma_out_ch0_int_map: AHB_PDMA_OUT_CH0_INT_MAP, + ahb_pdma_out_ch1_int_map: AHB_PDMA_OUT_CH1_INT_MAP, + ahb_pdma_out_ch2_int_map: AHB_PDMA_OUT_CH2_INT_MAP, + axi_pdma_in_ch0_int_map: AXI_PDMA_IN_CH0_INT_MAP, + axi_pdma_in_ch1_int_map: AXI_PDMA_IN_CH1_INT_MAP, + axi_pdma_in_ch2_int_map: AXI_PDMA_IN_CH2_INT_MAP, + axi_pdma_out_ch0_int_map: AXI_PDMA_OUT_CH0_INT_MAP, + axi_pdma_out_ch1_int_map: AXI_PDMA_OUT_CH1_INT_MAP, + axi_pdma_out_ch2_int_map: AXI_PDMA_OUT_CH2_INT_MAP, + rsa_int_map: RSA_INT_MAP, + aes_int_map: AES_INT_MAP, + sha_int_map: SHA_INT_MAP, + ecc_int_map: ECC_INT_MAP, + ecdsa_int_map: ECDSA_INT_MAP, + km_int_map: KM_INT_MAP, + gpio_int0_map: GPIO_INT0_MAP, + gpio_int1_map: GPIO_INT1_MAP, + gpio_int2_map: GPIO_INT2_MAP, + gpio_int3_map: GPIO_INT3_MAP, + gpio_pad_comp_int_map: GPIO_PAD_COMP_INT_MAP, + cpu_int_from_cpu_0_map: CPU_INT_FROM_CPU_0_MAP, + cpu_int_from_cpu_1_map: CPU_INT_FROM_CPU_1_MAP, + cpu_int_from_cpu_2_map: CPU_INT_FROM_CPU_2_MAP, + cpu_int_from_cpu_3_map: CPU_INT_FROM_CPU_3_MAP, + cache_int_map: CACHE_INT_MAP, + flash_mspi_int_map: FLASH_MSPI_INT_MAP, + csi_bridge_int_map: CSI_BRIDGE_INT_MAP, + dsi_bridge_int_map: DSI_BRIDGE_INT_MAP, + csi_int_map: CSI_INT_MAP, + dsi_int_map: DSI_INT_MAP, + gmii_phy_int_map: GMII_PHY_INT_MAP, + lpi_int_map: LPI_INT_MAP, + pmt_int_map: PMT_INT_MAP, + sbd_int_map: SBD_INT_MAP, + usb_otg_int_map: USB_OTG_INT_MAP, + usb_otg_endp_multi_proc_int_map: USB_OTG_ENDP_MULTI_PROC_INT_MAP, + jpeg_int_map: JPEG_INT_MAP, + ppa_int_map: PPA_INT_MAP, + core0_trace_int_map: CORE0_TRACE_INT_MAP, + core1_trace_int_map: CORE1_TRACE_INT_MAP, + hp_core_ctrl_int_map: HP_CORE_CTRL_INT_MAP, + isp_int_map: ISP_INT_MAP, + i3c_mst_int_map: I3C_MST_INT_MAP, + i3c_slv_int_map: I3C_SLV_INT_MAP, + usb_otg11_int_map: USB_OTG11_INT_MAP, + dma2d_in_ch0_int_map: DMA2D_IN_CH0_INT_MAP, + dma2d_in_ch1_int_map: DMA2D_IN_CH1_INT_MAP, + dma2d_out_ch0_int_map: DMA2D_OUT_CH0_INT_MAP, + dma2d_out_ch1_int_map: DMA2D_OUT_CH1_INT_MAP, + dma2d_out_ch2_int_map: DMA2D_OUT_CH2_INT_MAP, + psram_mspi_int_map: PSRAM_MSPI_INT_MAP, + hp_sysreg_int_map: HP_SYSREG_INT_MAP, + pcnt_int_map: PCNT_INT_MAP, + hp_pau_int_map: HP_PAU_INT_MAP, + hp_parlio_rx_int_map: HP_PARLIO_RX_INT_MAP, + hp_parlio_tx_int_map: HP_PARLIO_TX_INT_MAP, + h264_dma2d_out_ch0_int_map: H264_DMA2D_OUT_CH0_INT_MAP, + h264_dma2d_out_ch1_int_map: H264_DMA2D_OUT_CH1_INT_MAP, + h264_dma2d_out_ch2_int_map: H264_DMA2D_OUT_CH2_INT_MAP, + h264_dma2d_out_ch3_int_map: H264_DMA2D_OUT_CH3_INT_MAP, + h264_dma2d_out_ch4_int_map: H264_DMA2D_OUT_CH4_INT_MAP, + h264_dma2d_in_ch0_int_map: H264_DMA2D_IN_CH0_INT_MAP, + h264_dma2d_in_ch1_int_map: H264_DMA2D_IN_CH1_INT_MAP, + h264_dma2d_in_ch2_int_map: H264_DMA2D_IN_CH2_INT_MAP, + h264_dma2d_in_ch3_int_map: H264_DMA2D_IN_CH3_INT_MAP, + h264_dma2d_in_ch4_int_map: H264_DMA2D_IN_CH4_INT_MAP, + h264_dma2d_in_ch5_int_map: H264_DMA2D_IN_CH5_INT_MAP, + h264_reg_int_map: H264_REG_INT_MAP, + assist_debug_int_map: ASSIST_DEBUG_INT_MAP, + intr_status_reg_0: INTR_STATUS_REG_0, + intr_status_reg_1: INTR_STATUS_REG_1, + intr_status_reg_2: INTR_STATUS_REG_2, + intr_status_reg_3: INTR_STATUS_REG_3, + clock_gate: CLOCK_GATE, + _reserved133: [u8; 0x01e8], + interrupt_reg_date: INTERRUPT_REG_DATE, +} +impl RegisterBlock { + #[doc = "0x00 - NA"] + #[inline(always)] + pub const fn lp_rtc_int_map(&self) -> &LP_RTC_INT_MAP { + &self.lp_rtc_int_map + } + #[doc = "0x04 - NA"] + #[inline(always)] + pub const fn lp_wdt_int_map(&self) -> &LP_WDT_INT_MAP { + &self.lp_wdt_int_map + } + #[doc = "0x08 - NA"] + #[inline(always)] + pub const fn lp_timer_reg_0_int_map(&self) -> &LP_TIMER_REG_0_INT_MAP { + &self.lp_timer_reg_0_int_map + } + #[doc = "0x0c - NA"] + #[inline(always)] + pub const fn lp_timer_reg_1_int_map(&self) -> &LP_TIMER_REG_1_INT_MAP { + &self.lp_timer_reg_1_int_map + } + #[doc = "0x10 - NA"] + #[inline(always)] + pub const fn mb_hp_int_map(&self) -> &MB_HP_INT_MAP { + &self.mb_hp_int_map + } + #[doc = "0x14 - NA"] + #[inline(always)] + pub const fn mb_lp_int_map(&self) -> &MB_LP_INT_MAP { + &self.mb_lp_int_map + } + #[doc = "0x18 - NA"] + #[inline(always)] + pub const fn pmu_reg_0_int_map(&self) -> &PMU_REG_0_INT_MAP { + &self.pmu_reg_0_int_map + } + #[doc = "0x1c - NA"] + #[inline(always)] + pub const fn pmu_reg_1_int_map(&self) -> &PMU_REG_1_INT_MAP { + &self.pmu_reg_1_int_map + } + #[doc = "0x20 - NA"] + #[inline(always)] + pub const fn lp_anaperi_int_map(&self) -> &LP_ANAPERI_INT_MAP { + &self.lp_anaperi_int_map + } + #[doc = "0x24 - NA"] + #[inline(always)] + pub const fn lp_adc_int_map(&self) -> &LP_ADC_INT_MAP { + &self.lp_adc_int_map + } + #[doc = "0x28 - NA"] + #[inline(always)] + pub const fn lp_gpio_int_map(&self) -> &LP_GPIO_INT_MAP { + &self.lp_gpio_int_map + } + #[doc = "0x2c - NA"] + #[inline(always)] + pub const fn lp_i2c_int_map(&self) -> &LP_I2C_INT_MAP { + &self.lp_i2c_int_map + } + #[doc = "0x30 - NA"] + #[inline(always)] + pub const fn lp_i2s_int_map(&self) -> &LP_I2S_INT_MAP { + &self.lp_i2s_int_map + } + #[doc = "0x34 - NA"] + #[inline(always)] + pub const fn lp_spi_int_map(&self) -> &LP_SPI_INT_MAP { + &self.lp_spi_int_map + } + #[doc = "0x38 - NA"] + #[inline(always)] + pub const fn lp_touch_int_map(&self) -> &LP_TOUCH_INT_MAP { + &self.lp_touch_int_map + } + #[doc = "0x3c - NA"] + #[inline(always)] + pub const fn lp_tsens_int_map(&self) -> &LP_TSENS_INT_MAP { + &self.lp_tsens_int_map + } + #[doc = "0x40 - NA"] + #[inline(always)] + pub const fn lp_uart_int_map(&self) -> &LP_UART_INT_MAP { + &self.lp_uart_int_map + } + #[doc = "0x44 - NA"] + #[inline(always)] + pub const fn lp_efuse_int_map(&self) -> &LP_EFUSE_INT_MAP { + &self.lp_efuse_int_map + } + #[doc = "0x48 - NA"] + #[inline(always)] + pub const fn lp_sw_int_map(&self) -> &LP_SW_INT_MAP { + &self.lp_sw_int_map + } + #[doc = "0x4c - NA"] + #[inline(always)] + pub const fn lp_sysreg_int_map(&self) -> &LP_SYSREG_INT_MAP { + &self.lp_sysreg_int_map + } + #[doc = "0x50 - NA"] + #[inline(always)] + pub const fn lp_huk_int_map(&self) -> &LP_HUK_INT_MAP { + &self.lp_huk_int_map + } + #[doc = "0x54 - NA"] + #[inline(always)] + pub const fn sys_icm_int_map(&self) -> &SYS_ICM_INT_MAP { + &self.sys_icm_int_map + } + #[doc = "0x58 - NA"] + #[inline(always)] + pub const fn usb_device_int_map(&self) -> &USB_DEVICE_INT_MAP { + &self.usb_device_int_map + } + #[doc = "0x5c - NA"] + #[inline(always)] + pub const fn sdio_host_int_map(&self) -> &SDIO_HOST_INT_MAP { + &self.sdio_host_int_map + } + #[doc = "0x60 - NA"] + #[inline(always)] + pub const fn gdma_int_map(&self) -> &GDMA_INT_MAP { + &self.gdma_int_map + } + #[doc = "0x64 - NA"] + #[inline(always)] + pub const fn spi2_int_map(&self) -> &SPI2_INT_MAP { + &self.spi2_int_map + } + #[doc = "0x68 - NA"] + #[inline(always)] + pub const fn spi3_int_map(&self) -> &SPI3_INT_MAP { + &self.spi3_int_map + } + #[doc = "0x6c - NA"] + #[inline(always)] + pub const fn i2s0_int_map(&self) -> &I2S0_INT_MAP { + &self.i2s0_int_map + } + #[doc = "0x70 - NA"] + #[inline(always)] + pub const fn i2s1_int_map(&self) -> &I2S1_INT_MAP { + &self.i2s1_int_map + } + #[doc = "0x74 - NA"] + #[inline(always)] + pub const fn i2s2_int_map(&self) -> &I2S2_INT_MAP { + &self.i2s2_int_map + } + #[doc = "0x78 - NA"] + #[inline(always)] + pub const fn uhci0_int_map(&self) -> &UHCI0_INT_MAP { + &self.uhci0_int_map + } + #[doc = "0x7c - NA"] + #[inline(always)] + pub const fn uart0_int_map(&self) -> &UART0_INT_MAP { + &self.uart0_int_map + } + #[doc = "0x80 - NA"] + #[inline(always)] + pub const fn uart1_int_map(&self) -> &UART1_INT_MAP { + &self.uart1_int_map + } + #[doc = "0x84 - NA"] + #[inline(always)] + pub const fn uart2_int_map(&self) -> &UART2_INT_MAP { + &self.uart2_int_map + } + #[doc = "0x88 - NA"] + #[inline(always)] + pub const fn uart3_int_map(&self) -> &UART3_INT_MAP { + &self.uart3_int_map + } + #[doc = "0x8c - NA"] + #[inline(always)] + pub const fn uart4_int_map(&self) -> &UART4_INT_MAP { + &self.uart4_int_map + } + #[doc = "0x90 - NA"] + #[inline(always)] + pub const fn lcd_cam_int_map(&self) -> &LCD_CAM_INT_MAP { + &self.lcd_cam_int_map + } + #[doc = "0x94 - NA"] + #[inline(always)] + pub const fn adc_int_map(&self) -> &ADC_INT_MAP { + &self.adc_int_map + } + #[doc = "0x98 - NA"] + #[inline(always)] + pub const fn pwm0_int_map(&self) -> &PWM0_INT_MAP { + &self.pwm0_int_map + } + #[doc = "0x9c - NA"] + #[inline(always)] + pub const fn pwm1_int_map(&self) -> &PWM1_INT_MAP { + &self.pwm1_int_map + } + #[doc = "0xa0 - NA"] + #[inline(always)] + pub const fn can0_int_map(&self) -> &CAN0_INT_MAP { + &self.can0_int_map + } + #[doc = "0xa4 - NA"] + #[inline(always)] + pub const fn can1_int_map(&self) -> &CAN1_INT_MAP { + &self.can1_int_map + } + #[doc = "0xa8 - NA"] + #[inline(always)] + pub const fn can2_int_map(&self) -> &CAN2_INT_MAP { + &self.can2_int_map + } + #[doc = "0xac - NA"] + #[inline(always)] + pub const fn rmt_int_map(&self) -> &RMT_INT_MAP { + &self.rmt_int_map + } + #[doc = "0xb0 - NA"] + #[inline(always)] + pub const fn i2c0_int_map(&self) -> &I2C0_INT_MAP { + &self.i2c0_int_map + } + #[doc = "0xb4 - NA"] + #[inline(always)] + pub const fn i2c1_int_map(&self) -> &I2C1_INT_MAP { + &self.i2c1_int_map + } + #[doc = "0xb8 - NA"] + #[inline(always)] + pub const fn timergrp0_t0_int_map(&self) -> &TIMERGRP0_T0_INT_MAP { + &self.timergrp0_t0_int_map + } + #[doc = "0xbc - NA"] + #[inline(always)] + pub const fn timergrp0_t1_int_map(&self) -> &TIMERGRP0_T1_INT_MAP { + &self.timergrp0_t1_int_map + } + #[doc = "0xc0 - NA"] + #[inline(always)] + pub const fn timergrp0_wdt_int_map(&self) -> &TIMERGRP0_WDT_INT_MAP { + &self.timergrp0_wdt_int_map + } + #[doc = "0xc4 - NA"] + #[inline(always)] + pub const fn timergrp1_t0_int_map(&self) -> &TIMERGRP1_T0_INT_MAP { + &self.timergrp1_t0_int_map + } + #[doc = "0xc8 - NA"] + #[inline(always)] + pub const fn timergrp1_t1_int_map(&self) -> &TIMERGRP1_T1_INT_MAP { + &self.timergrp1_t1_int_map + } + #[doc = "0xcc - NA"] + #[inline(always)] + pub const fn timergrp1_wdt_int_map(&self) -> &TIMERGRP1_WDT_INT_MAP { + &self.timergrp1_wdt_int_map + } + #[doc = "0xd0 - NA"] + #[inline(always)] + pub const fn ledc_int_map(&self) -> &LEDC_INT_MAP { + &self.ledc_int_map + } + #[doc = "0xd4 - NA"] + #[inline(always)] + pub const fn systimer_target0_int_map(&self) -> &SYSTIMER_TARGET0_INT_MAP { + &self.systimer_target0_int_map + } + #[doc = "0xd8 - NA"] + #[inline(always)] + pub const fn systimer_target1_int_map(&self) -> &SYSTIMER_TARGET1_INT_MAP { + &self.systimer_target1_int_map + } + #[doc = "0xdc - NA"] + #[inline(always)] + pub const fn systimer_target2_int_map(&self) -> &SYSTIMER_TARGET2_INT_MAP { + &self.systimer_target2_int_map + } + #[doc = "0xe0 - NA"] + #[inline(always)] + pub const fn ahb_pdma_in_ch0_int_map(&self) -> &AHB_PDMA_IN_CH0_INT_MAP { + &self.ahb_pdma_in_ch0_int_map + } + #[doc = "0xe4 - NA"] + #[inline(always)] + pub const fn ahb_pdma_in_ch1_int_map(&self) -> &AHB_PDMA_IN_CH1_INT_MAP { + &self.ahb_pdma_in_ch1_int_map + } + #[doc = "0xe8 - NA"] + #[inline(always)] + pub const fn ahb_pdma_in_ch2_int_map(&self) -> &AHB_PDMA_IN_CH2_INT_MAP { + &self.ahb_pdma_in_ch2_int_map + } + #[doc = "0xec - NA"] + #[inline(always)] + pub const fn ahb_pdma_out_ch0_int_map(&self) -> &AHB_PDMA_OUT_CH0_INT_MAP { + &self.ahb_pdma_out_ch0_int_map + } + #[doc = "0xf0 - NA"] + #[inline(always)] + pub const fn ahb_pdma_out_ch1_int_map(&self) -> &AHB_PDMA_OUT_CH1_INT_MAP { + &self.ahb_pdma_out_ch1_int_map + } + #[doc = "0xf4 - NA"] + #[inline(always)] + pub const fn ahb_pdma_out_ch2_int_map(&self) -> &AHB_PDMA_OUT_CH2_INT_MAP { + &self.ahb_pdma_out_ch2_int_map + } + #[doc = "0xf8 - NA"] + #[inline(always)] + pub const fn axi_pdma_in_ch0_int_map(&self) -> &AXI_PDMA_IN_CH0_INT_MAP { + &self.axi_pdma_in_ch0_int_map + } + #[doc = "0xfc - NA"] + #[inline(always)] + pub const fn axi_pdma_in_ch1_int_map(&self) -> &AXI_PDMA_IN_CH1_INT_MAP { + &self.axi_pdma_in_ch1_int_map + } + #[doc = "0x100 - NA"] + #[inline(always)] + pub const fn axi_pdma_in_ch2_int_map(&self) -> &AXI_PDMA_IN_CH2_INT_MAP { + &self.axi_pdma_in_ch2_int_map + } + #[doc = "0x104 - NA"] + #[inline(always)] + pub const fn axi_pdma_out_ch0_int_map(&self) -> &AXI_PDMA_OUT_CH0_INT_MAP { + &self.axi_pdma_out_ch0_int_map + } + #[doc = "0x108 - NA"] + #[inline(always)] + pub const fn axi_pdma_out_ch1_int_map(&self) -> &AXI_PDMA_OUT_CH1_INT_MAP { + &self.axi_pdma_out_ch1_int_map + } + #[doc = "0x10c - NA"] + #[inline(always)] + pub const fn axi_pdma_out_ch2_int_map(&self) -> &AXI_PDMA_OUT_CH2_INT_MAP { + &self.axi_pdma_out_ch2_int_map + } + #[doc = "0x110 - NA"] + #[inline(always)] + pub const fn rsa_int_map(&self) -> &RSA_INT_MAP { + &self.rsa_int_map + } + #[doc = "0x114 - NA"] + #[inline(always)] + pub const fn aes_int_map(&self) -> &AES_INT_MAP { + &self.aes_int_map + } + #[doc = "0x118 - NA"] + #[inline(always)] + pub const fn sha_int_map(&self) -> &SHA_INT_MAP { + &self.sha_int_map + } + #[doc = "0x11c - NA"] + #[inline(always)] + pub const fn ecc_int_map(&self) -> &ECC_INT_MAP { + &self.ecc_int_map + } + #[doc = "0x120 - NA"] + #[inline(always)] + pub const fn ecdsa_int_map(&self) -> &ECDSA_INT_MAP { + &self.ecdsa_int_map + } + #[doc = "0x124 - NA"] + #[inline(always)] + pub const fn km_int_map(&self) -> &KM_INT_MAP { + &self.km_int_map + } + #[doc = "0x128 - NA"] + #[inline(always)] + pub const fn gpio_int0_map(&self) -> &GPIO_INT0_MAP { + &self.gpio_int0_map + } + #[doc = "0x12c - NA"] + #[inline(always)] + pub const fn gpio_int1_map(&self) -> &GPIO_INT1_MAP { + &self.gpio_int1_map + } + #[doc = "0x130 - NA"] + #[inline(always)] + pub const fn gpio_int2_map(&self) -> &GPIO_INT2_MAP { + &self.gpio_int2_map + } + #[doc = "0x134 - NA"] + #[inline(always)] + pub const fn gpio_int3_map(&self) -> &GPIO_INT3_MAP { + &self.gpio_int3_map + } + #[doc = "0x138 - NA"] + #[inline(always)] + pub const fn gpio_pad_comp_int_map(&self) -> &GPIO_PAD_COMP_INT_MAP { + &self.gpio_pad_comp_int_map + } + #[doc = "0x13c - NA"] + #[inline(always)] + pub const fn cpu_int_from_cpu_0_map(&self) -> &CPU_INT_FROM_CPU_0_MAP { + &self.cpu_int_from_cpu_0_map + } + #[doc = "0x140 - NA"] + #[inline(always)] + pub const fn cpu_int_from_cpu_1_map(&self) -> &CPU_INT_FROM_CPU_1_MAP { + &self.cpu_int_from_cpu_1_map + } + #[doc = "0x144 - NA"] + #[inline(always)] + pub const fn cpu_int_from_cpu_2_map(&self) -> &CPU_INT_FROM_CPU_2_MAP { + &self.cpu_int_from_cpu_2_map + } + #[doc = "0x148 - NA"] + #[inline(always)] + pub const fn cpu_int_from_cpu_3_map(&self) -> &CPU_INT_FROM_CPU_3_MAP { + &self.cpu_int_from_cpu_3_map + } + #[doc = "0x14c - NA"] + #[inline(always)] + pub const fn cache_int_map(&self) -> &CACHE_INT_MAP { + &self.cache_int_map + } + #[doc = "0x150 - NA"] + #[inline(always)] + pub const fn flash_mspi_int_map(&self) -> &FLASH_MSPI_INT_MAP { + &self.flash_mspi_int_map + } + #[doc = "0x154 - NA"] + #[inline(always)] + pub const fn csi_bridge_int_map(&self) -> &CSI_BRIDGE_INT_MAP { + &self.csi_bridge_int_map + } + #[doc = "0x158 - NA"] + #[inline(always)] + pub const fn dsi_bridge_int_map(&self) -> &DSI_BRIDGE_INT_MAP { + &self.dsi_bridge_int_map + } + #[doc = "0x15c - NA"] + #[inline(always)] + pub const fn csi_int_map(&self) -> &CSI_INT_MAP { + &self.csi_int_map + } + #[doc = "0x160 - NA"] + #[inline(always)] + pub const fn dsi_int_map(&self) -> &DSI_INT_MAP { + &self.dsi_int_map + } + #[doc = "0x164 - NA"] + #[inline(always)] + pub const fn gmii_phy_int_map(&self) -> &GMII_PHY_INT_MAP { + &self.gmii_phy_int_map + } + #[doc = "0x168 - NA"] + #[inline(always)] + pub const fn lpi_int_map(&self) -> &LPI_INT_MAP { + &self.lpi_int_map + } + #[doc = "0x16c - NA"] + #[inline(always)] + pub const fn pmt_int_map(&self) -> &PMT_INT_MAP { + &self.pmt_int_map + } + #[doc = "0x170 - NA"] + #[inline(always)] + pub const fn sbd_int_map(&self) -> &SBD_INT_MAP { + &self.sbd_int_map + } + #[doc = "0x174 - NA"] + #[inline(always)] + pub const fn usb_otg_int_map(&self) -> &USB_OTG_INT_MAP { + &self.usb_otg_int_map + } + #[doc = "0x178 - NA"] + #[inline(always)] + pub const fn usb_otg_endp_multi_proc_int_map(&self) -> &USB_OTG_ENDP_MULTI_PROC_INT_MAP { + &self.usb_otg_endp_multi_proc_int_map + } + #[doc = "0x17c - NA"] + #[inline(always)] + pub const fn jpeg_int_map(&self) -> &JPEG_INT_MAP { + &self.jpeg_int_map + } + #[doc = "0x180 - NA"] + #[inline(always)] + pub const fn ppa_int_map(&self) -> &PPA_INT_MAP { + &self.ppa_int_map + } + #[doc = "0x184 - NA"] + #[inline(always)] + pub const fn core0_trace_int_map(&self) -> &CORE0_TRACE_INT_MAP { + &self.core0_trace_int_map + } + #[doc = "0x188 - NA"] + #[inline(always)] + pub const fn core1_trace_int_map(&self) -> &CORE1_TRACE_INT_MAP { + &self.core1_trace_int_map + } + #[doc = "0x18c - NA"] + #[inline(always)] + pub const fn hp_core_ctrl_int_map(&self) -> &HP_CORE_CTRL_INT_MAP { + &self.hp_core_ctrl_int_map + } + #[doc = "0x190 - NA"] + #[inline(always)] + pub const fn isp_int_map(&self) -> &ISP_INT_MAP { + &self.isp_int_map + } + #[doc = "0x194 - NA"] + #[inline(always)] + pub const fn i3c_mst_int_map(&self) -> &I3C_MST_INT_MAP { + &self.i3c_mst_int_map + } + #[doc = "0x198 - NA"] + #[inline(always)] + pub const fn i3c_slv_int_map(&self) -> &I3C_SLV_INT_MAP { + &self.i3c_slv_int_map + } + #[doc = "0x19c - NA"] + #[inline(always)] + pub const fn usb_otg11_int_map(&self) -> &USB_OTG11_INT_MAP { + &self.usb_otg11_int_map + } + #[doc = "0x1a0 - NA"] + #[inline(always)] + pub const fn dma2d_in_ch0_int_map(&self) -> &DMA2D_IN_CH0_INT_MAP { + &self.dma2d_in_ch0_int_map + } + #[doc = "0x1a4 - NA"] + #[inline(always)] + pub const fn dma2d_in_ch1_int_map(&self) -> &DMA2D_IN_CH1_INT_MAP { + &self.dma2d_in_ch1_int_map + } + #[doc = "0x1a8 - NA"] + #[inline(always)] + pub const fn dma2d_out_ch0_int_map(&self) -> &DMA2D_OUT_CH0_INT_MAP { + &self.dma2d_out_ch0_int_map + } + #[doc = "0x1ac - NA"] + #[inline(always)] + pub const fn dma2d_out_ch1_int_map(&self) -> &DMA2D_OUT_CH1_INT_MAP { + &self.dma2d_out_ch1_int_map + } + #[doc = "0x1b0 - NA"] + #[inline(always)] + pub const fn dma2d_out_ch2_int_map(&self) -> &DMA2D_OUT_CH2_INT_MAP { + &self.dma2d_out_ch2_int_map + } + #[doc = "0x1b4 - NA"] + #[inline(always)] + pub const fn psram_mspi_int_map(&self) -> &PSRAM_MSPI_INT_MAP { + &self.psram_mspi_int_map + } + #[doc = "0x1b8 - NA"] + #[inline(always)] + pub const fn hp_sysreg_int_map(&self) -> &HP_SYSREG_INT_MAP { + &self.hp_sysreg_int_map + } + #[doc = "0x1bc - NA"] + #[inline(always)] + pub const fn pcnt_int_map(&self) -> &PCNT_INT_MAP { + &self.pcnt_int_map + } + #[doc = "0x1c0 - NA"] + #[inline(always)] + pub const fn hp_pau_int_map(&self) -> &HP_PAU_INT_MAP { + &self.hp_pau_int_map + } + #[doc = "0x1c4 - NA"] + #[inline(always)] + pub const fn hp_parlio_rx_int_map(&self) -> &HP_PARLIO_RX_INT_MAP { + &self.hp_parlio_rx_int_map + } + #[doc = "0x1c8 - NA"] + #[inline(always)] + pub const fn hp_parlio_tx_int_map(&self) -> &HP_PARLIO_TX_INT_MAP { + &self.hp_parlio_tx_int_map + } + #[doc = "0x1cc - NA"] + #[inline(always)] + pub const fn h264_dma2d_out_ch0_int_map(&self) -> &H264_DMA2D_OUT_CH0_INT_MAP { + &self.h264_dma2d_out_ch0_int_map + } + #[doc = "0x1d0 - NA"] + #[inline(always)] + pub const fn h264_dma2d_out_ch1_int_map(&self) -> &H264_DMA2D_OUT_CH1_INT_MAP { + &self.h264_dma2d_out_ch1_int_map + } + #[doc = "0x1d4 - NA"] + #[inline(always)] + pub const fn h264_dma2d_out_ch2_int_map(&self) -> &H264_DMA2D_OUT_CH2_INT_MAP { + &self.h264_dma2d_out_ch2_int_map + } + #[doc = "0x1d8 - NA"] + #[inline(always)] + pub const fn h264_dma2d_out_ch3_int_map(&self) -> &H264_DMA2D_OUT_CH3_INT_MAP { + &self.h264_dma2d_out_ch3_int_map + } + #[doc = "0x1dc - NA"] + #[inline(always)] + pub const fn h264_dma2d_out_ch4_int_map(&self) -> &H264_DMA2D_OUT_CH4_INT_MAP { + &self.h264_dma2d_out_ch4_int_map + } + #[doc = "0x1e0 - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch0_int_map(&self) -> &H264_DMA2D_IN_CH0_INT_MAP { + &self.h264_dma2d_in_ch0_int_map + } + #[doc = "0x1e4 - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch1_int_map(&self) -> &H264_DMA2D_IN_CH1_INT_MAP { + &self.h264_dma2d_in_ch1_int_map + } + #[doc = "0x1e8 - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch2_int_map(&self) -> &H264_DMA2D_IN_CH2_INT_MAP { + &self.h264_dma2d_in_ch2_int_map + } + #[doc = "0x1ec - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch3_int_map(&self) -> &H264_DMA2D_IN_CH3_INT_MAP { + &self.h264_dma2d_in_ch3_int_map + } + #[doc = "0x1f0 - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch4_int_map(&self) -> &H264_DMA2D_IN_CH4_INT_MAP { + &self.h264_dma2d_in_ch4_int_map + } + #[doc = "0x1f4 - NA"] + #[inline(always)] + pub const fn h264_dma2d_in_ch5_int_map(&self) -> &H264_DMA2D_IN_CH5_INT_MAP { + &self.h264_dma2d_in_ch5_int_map + } + #[doc = "0x1f8 - NA"] + #[inline(always)] + pub const fn h264_reg_int_map(&self) -> &H264_REG_INT_MAP { + &self.h264_reg_int_map + } + #[doc = "0x1fc - NA"] + #[inline(always)] + pub const fn assist_debug_int_map(&self) -> &ASSIST_DEBUG_INT_MAP { + &self.assist_debug_int_map + } + #[doc = "0x200 - NA"] + #[inline(always)] + pub const fn intr_status_reg_0(&self) -> &INTR_STATUS_REG_0 { + &self.intr_status_reg_0 + } + #[doc = "0x204 - NA"] + #[inline(always)] + pub const fn intr_status_reg_1(&self) -> &INTR_STATUS_REG_1 { + &self.intr_status_reg_1 + } + #[doc = "0x208 - NA"] + #[inline(always)] + pub const fn intr_status_reg_2(&self) -> &INTR_STATUS_REG_2 { + &self.intr_status_reg_2 + } + #[doc = "0x20c - NA"] + #[inline(always)] + pub const fn intr_status_reg_3(&self) -> &INTR_STATUS_REG_3 { + &self.intr_status_reg_3 + } + #[doc = "0x210 - NA"] + #[inline(always)] + pub const fn clock_gate(&self) -> &CLOCK_GATE { + &self.clock_gate + } + #[doc = "0x3fc - NA"] + #[inline(always)] + pub const fn interrupt_reg_date(&self) -> &INTERRUPT_REG_DATE { + &self.interrupt_reg_date + } +} +#[doc = "LP_RTC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_rtc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_rtc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_rtc_int_map`] module"] +pub type LP_RTC_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_rtc_int_map; +#[doc = "LP_WDT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_wdt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_wdt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_wdt_int_map`] module"] +pub type LP_WDT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_wdt_int_map; +#[doc = "LP_TIMER_REG_0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timer_reg_0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timer_reg_0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_timer_reg_0_int_map`] module"] +pub type LP_TIMER_REG_0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_timer_reg_0_int_map; +#[doc = "LP_TIMER_REG_1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timer_reg_1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timer_reg_1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_timer_reg_1_int_map`] module"] +pub type LP_TIMER_REG_1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_timer_reg_1_int_map; +#[doc = "MB_HP_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mb_hp_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mb_hp_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_hp_int_map`] module"] +pub type MB_HP_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod mb_hp_int_map; +#[doc = "MB_LP_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mb_lp_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mb_lp_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mb_lp_int_map`] module"] +pub type MB_LP_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod mb_lp_int_map; +#[doc = "PMU_REG_0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_reg_0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_reg_0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmu_reg_0_int_map`] module"] +pub type PMU_REG_0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pmu_reg_0_int_map; +#[doc = "PMU_REG_1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_reg_1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_reg_1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmu_reg_1_int_map`] module"] +pub type PMU_REG_1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pmu_reg_1_int_map; +#[doc = "LP_ANAPERI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_anaperi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_anaperi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_anaperi_int_map`] module"] +pub type LP_ANAPERI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_anaperi_int_map; +#[doc = "LP_ADC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_adc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_adc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_adc_int_map`] module"] +pub type LP_ADC_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_adc_int_map; +#[doc = "LP_GPIO_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_gpio_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_gpio_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_gpio_int_map`] module"] +pub type LP_GPIO_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_gpio_int_map; +#[doc = "LP_I2C_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2c_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2c_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_i2c_int_map`] module"] +pub type LP_I2C_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_i2c_int_map; +#[doc = "LP_I2S_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_i2s_int_map`] module"] +pub type LP_I2S_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_i2s_int_map; +#[doc = "LP_SPI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_spi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_spi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_spi_int_map`] module"] +pub type LP_SPI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_spi_int_map; +#[doc = "LP_TOUCH_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_touch_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_touch_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_touch_int_map`] module"] +pub type LP_TOUCH_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_touch_int_map; +#[doc = "LP_TSENS_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tsens_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tsens_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_tsens_int_map`] module"] +pub type LP_TSENS_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_tsens_int_map; +#[doc = "LP_UART_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_uart_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_uart_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_uart_int_map`] module"] +pub type LP_UART_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_uart_int_map; +#[doc = "LP_EFUSE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_efuse_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_efuse_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_efuse_int_map`] module"] +pub type LP_EFUSE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_efuse_int_map; +#[doc = "LP_SW_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sw_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sw_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sw_int_map`] module"] +pub type LP_SW_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_sw_int_map; +#[doc = "LP_SYSREG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sysreg_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sysreg_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sysreg_int_map`] module"] +pub type LP_SYSREG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_sysreg_int_map; +#[doc = "LP_HUK_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_huk_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_huk_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_huk_int_map`] module"] +pub type LP_HUK_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lp_huk_int_map; +#[doc = "SYS_ICM_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_icm_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_icm_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_icm_int_map`] module"] +pub type SYS_ICM_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod sys_icm_int_map; +#[doc = "USB_DEVICE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_device_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_device_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb_device_int_map`] module"] +pub type USB_DEVICE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod usb_device_int_map; +#[doc = "SDIO_HOST_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdio_host_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdio_host_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdio_host_int_map`] module"] +pub type SDIO_HOST_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod sdio_host_int_map; +#[doc = "GDMA_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdma_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdma_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gdma_int_map`] module"] +pub type GDMA_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod gdma_int_map; +#[doc = "SPI2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi2_int_map`] module"] +pub type SPI2_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod spi2_int_map; +#[doc = "SPI3_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi3_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi3_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi3_int_map`] module"] +pub type SPI3_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod spi3_int_map; +#[doc = "I2S0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s0_int_map`] module"] +pub type I2S0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i2s0_int_map; +#[doc = "I2S1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s1_int_map`] module"] +pub type I2S1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i2s1_int_map; +#[doc = "I2S2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s2_int_map`] module"] +pub type I2S2_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i2s2_int_map; +#[doc = "UHCI0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uhci0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uhci0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uhci0_int_map`] module"] +pub type UHCI0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uhci0_int_map; +#[doc = "UART0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_int_map`] module"] +pub type UART0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uart0_int_map; +#[doc = "UART1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_int_map`] module"] +pub type UART1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uart1_int_map; +#[doc = "UART2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart2_int_map`] module"] +pub type UART2_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uart2_int_map; +#[doc = "UART3_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart3_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart3_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart3_int_map`] module"] +pub type UART3_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uart3_int_map; +#[doc = "UART4_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart4_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart4_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart4_int_map`] module"] +pub type UART4_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod uart4_int_map; +#[doc = "LCD_CAM_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_cam_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_cam_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_cam_int_map`] module"] +pub type LCD_CAM_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lcd_cam_int_map; +#[doc = "ADC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc_int_map`] module"] +pub type ADC_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod adc_int_map; +#[doc = "PWM0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm0_int_map`] module"] +pub type PWM0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pwm0_int_map; +#[doc = "PWM1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm1_int_map`] module"] +pub type PWM1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pwm1_int_map; +#[doc = "CAN0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@can0_int_map`] module"] +pub type CAN0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod can0_int_map; +#[doc = "CAN1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@can1_int_map`] module"] +pub type CAN1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod can1_int_map; +#[doc = "CAN2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@can2_int_map`] module"] +pub type CAN2_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod can2_int_map; +#[doc = "RMT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rmt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rmt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rmt_int_map`] module"] +pub type RMT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod rmt_int_map; +#[doc = "I2C0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c0_int_map`] module"] +pub type I2C0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i2c0_int_map; +#[doc = "I2C1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c1_int_map`] module"] +pub type I2C1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i2c1_int_map; +#[doc = "TIMERGRP0_T0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_t0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_t0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp0_t0_int_map`] module"] +pub type TIMERGRP0_T0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp0_t0_int_map; +#[doc = "TIMERGRP0_T1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_t1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_t1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp0_t1_int_map`] module"] +pub type TIMERGRP0_T1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp0_t1_int_map; +#[doc = "TIMERGRP0_WDT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_wdt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_wdt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp0_wdt_int_map`] module"] +pub type TIMERGRP0_WDT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp0_wdt_int_map; +#[doc = "TIMERGRP1_T0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_t0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_t0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp1_t0_int_map`] module"] +pub type TIMERGRP1_T0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp1_t0_int_map; +#[doc = "TIMERGRP1_T1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_t1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_t1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp1_t1_int_map`] module"] +pub type TIMERGRP1_T1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp1_t1_int_map; +#[doc = "TIMERGRP1_WDT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_wdt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_wdt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timergrp1_wdt_int_map`] module"] +pub type TIMERGRP1_WDT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod timergrp1_wdt_int_map; +#[doc = "LEDC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ledc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ledc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ledc_int_map`] module"] +pub type LEDC_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod ledc_int_map; +#[doc = "SYSTIMER_TARGET0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systimer_target0_int_map`] module"] +pub type SYSTIMER_TARGET0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod systimer_target0_int_map; +#[doc = "SYSTIMER_TARGET1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systimer_target1_int_map`] module"] +pub type SYSTIMER_TARGET1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod systimer_target1_int_map; +#[doc = "SYSTIMER_TARGET2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systimer_target2_int_map`] module"] +pub type SYSTIMER_TARGET2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod systimer_target2_int_map; +#[doc = "AHB_PDMA_IN_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_in_ch0_int_map`] module"] +pub type AHB_PDMA_IN_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_in_ch0_int_map; +#[doc = "AHB_PDMA_IN_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_in_ch1_int_map`] module"] +pub type AHB_PDMA_IN_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_in_ch1_int_map; +#[doc = "AHB_PDMA_IN_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_in_ch2_int_map`] module"] +pub type AHB_PDMA_IN_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_in_ch2_int_map; +#[doc = "AHB_PDMA_OUT_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_out_ch0_int_map`] module"] +pub type AHB_PDMA_OUT_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_out_ch0_int_map; +#[doc = "AHB_PDMA_OUT_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_out_ch1_int_map`] module"] +pub type AHB_PDMA_OUT_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_out_ch1_int_map; +#[doc = "AHB_PDMA_OUT_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_pdma_out_ch2_int_map`] module"] +pub type AHB_PDMA_OUT_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod ahb_pdma_out_ch2_int_map; +#[doc = "AXI_PDMA_IN_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_in_ch0_int_map`] module"] +pub type AXI_PDMA_IN_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_in_ch0_int_map; +#[doc = "AXI_PDMA_IN_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_in_ch1_int_map`] module"] +pub type AXI_PDMA_IN_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_in_ch1_int_map; +#[doc = "AXI_PDMA_IN_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_in_ch2_int_map`] module"] +pub type AXI_PDMA_IN_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_in_ch2_int_map; +#[doc = "AXI_PDMA_OUT_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_out_ch0_int_map`] module"] +pub type AXI_PDMA_OUT_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_out_ch0_int_map; +#[doc = "AXI_PDMA_OUT_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_out_ch1_int_map`] module"] +pub type AXI_PDMA_OUT_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_out_ch1_int_map; +#[doc = "AXI_PDMA_OUT_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@axi_pdma_out_ch2_int_map`] module"] +pub type AXI_PDMA_OUT_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod axi_pdma_out_ch2_int_map; +#[doc = "RSA_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsa_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsa_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsa_int_map`] module"] +pub type RSA_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod rsa_int_map; +#[doc = "AES_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aes_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aes_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aes_int_map`] module"] +pub type AES_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod aes_int_map; +#[doc = "SHA_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sha_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sha_int_map`] module"] +pub type SHA_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod sha_int_map; +#[doc = "ECC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecc_int_map`] module"] +pub type ECC_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod ecc_int_map; +#[doc = "ECDSA_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecdsa_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecdsa_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecdsa_int_map`] module"] +pub type ECDSA_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod ecdsa_int_map; +#[doc = "KM_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`km_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`km_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@km_int_map`] module"] +pub type KM_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod km_int_map; +#[doc = "GPIO_INT0_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int0_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int0_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int0_map`] module"] +pub type GPIO_INT0_MAP = crate::Reg; +#[doc = "NA"] +pub mod gpio_int0_map; +#[doc = "GPIO_INT1_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int1_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int1_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int1_map`] module"] +pub type GPIO_INT1_MAP = crate::Reg; +#[doc = "NA"] +pub mod gpio_int1_map; +#[doc = "GPIO_INT2_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int2_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int2_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int2_map`] module"] +pub type GPIO_INT2_MAP = crate::Reg; +#[doc = "NA"] +pub mod gpio_int2_map; +#[doc = "GPIO_INT3_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int3_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int3_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_int3_map`] module"] +pub type GPIO_INT3_MAP = crate::Reg; +#[doc = "NA"] +pub mod gpio_int3_map; +#[doc = "GPIO_PAD_COMP_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pad_comp_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pad_comp_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio_pad_comp_int_map`] module"] +pub type GPIO_PAD_COMP_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod gpio_pad_comp_int_map; +#[doc = "CPU_INT_FROM_CPU_0_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_0_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_0_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_from_cpu_0_map`] module"] +pub type CPU_INT_FROM_CPU_0_MAP = crate::Reg; +#[doc = "NA"] +pub mod cpu_int_from_cpu_0_map; +#[doc = "CPU_INT_FROM_CPU_1_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_1_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_1_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_from_cpu_1_map`] module"] +pub type CPU_INT_FROM_CPU_1_MAP = crate::Reg; +#[doc = "NA"] +pub mod cpu_int_from_cpu_1_map; +#[doc = "CPU_INT_FROM_CPU_2_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_2_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_2_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_from_cpu_2_map`] module"] +pub type CPU_INT_FROM_CPU_2_MAP = crate::Reg; +#[doc = "NA"] +pub mod cpu_int_from_cpu_2_map; +#[doc = "CPU_INT_FROM_CPU_3_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_3_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_3_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_int_from_cpu_3_map`] module"] +pub type CPU_INT_FROM_CPU_3_MAP = crate::Reg; +#[doc = "NA"] +pub mod cpu_int_from_cpu_3_map; +#[doc = "CACHE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cache_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_int_map`] module"] +pub type CACHE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod cache_int_map; +#[doc = "FLASH_MSPI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flash_mspi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flash_mspi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_mspi_int_map`] module"] +pub type FLASH_MSPI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod flash_mspi_int_map; +#[doc = "CSI_BRIDGE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_bridge_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_bridge_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csi_bridge_int_map`] module"] +pub type CSI_BRIDGE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod csi_bridge_int_map; +#[doc = "DSI_BRIDGE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsi_bridge_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsi_bridge_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsi_bridge_int_map`] module"] +pub type DSI_BRIDGE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dsi_bridge_int_map; +#[doc = "CSI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csi_int_map`] module"] +pub type CSI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod csi_int_map; +#[doc = "DSI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsi_int_map`] module"] +pub type DSI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dsi_int_map; +#[doc = "GMII_PHY_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmii_phy_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmii_phy_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmii_phy_int_map`] module"] +pub type GMII_PHY_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod gmii_phy_int_map; +#[doc = "LPI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi_int_map`] module"] +pub type LPI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod lpi_int_map; +#[doc = "PMT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmt_int_map`] module"] +pub type PMT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pmt_int_map; +#[doc = "SBD_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbd_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbd_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbd_int_map`] module"] +pub type SBD_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod sbd_int_map; +#[doc = "USB_OTG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb_otg_int_map`] module"] +pub type USB_OTG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod usb_otg_int_map; +#[doc = "USB_OTG_ENDP_MULTI_PROC_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg_endp_multi_proc_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg_endp_multi_proc_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb_otg_endp_multi_proc_int_map`] module"] +pub type USB_OTG_ENDP_MULTI_PROC_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod usb_otg_endp_multi_proc_int_map; +#[doc = "JPEG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`jpeg_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`jpeg_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jpeg_int_map`] module"] +pub type JPEG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod jpeg_int_map; +#[doc = "PPA_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppa_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppa_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ppa_int_map`] module"] +pub type PPA_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod ppa_int_map; +#[doc = "CORE0_TRACE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_trace_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core0_trace_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core0_trace_int_map`] module"] +pub type CORE0_TRACE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod core0_trace_int_map; +#[doc = "CORE1_TRACE_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core1_trace_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core1_trace_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core1_trace_int_map`] module"] +pub type CORE1_TRACE_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod core1_trace_int_map; +#[doc = "HP_CORE_CTRL_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_ctrl_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_ctrl_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_core_ctrl_int_map`] module"] +pub type HP_CORE_CTRL_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod hp_core_ctrl_int_map; +#[doc = "ISP_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isp_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isp_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isp_int_map`] module"] +pub type ISP_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod isp_int_map; +#[doc = "I3C_MST_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i3c_mst_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i3c_mst_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i3c_mst_int_map`] module"] +pub type I3C_MST_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i3c_mst_int_map; +#[doc = "I3C_SLV_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i3c_slv_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i3c_slv_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i3c_slv_int_map`] module"] +pub type I3C_SLV_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod i3c_slv_int_map; +#[doc = "USB_OTG11_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg11_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg11_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb_otg11_int_map`] module"] +pub type USB_OTG11_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod usb_otg11_int_map; +#[doc = "DMA2D_IN_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_in_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_in_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2d_in_ch0_int_map`] module"] +pub type DMA2D_IN_CH0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dma2d_in_ch0_int_map; +#[doc = "DMA2D_IN_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_in_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_in_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2d_in_ch1_int_map`] module"] +pub type DMA2D_IN_CH1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dma2d_in_ch1_int_map; +#[doc = "DMA2D_OUT_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2d_out_ch0_int_map`] module"] +pub type DMA2D_OUT_CH0_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dma2d_out_ch0_int_map; +#[doc = "DMA2D_OUT_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2d_out_ch1_int_map`] module"] +pub type DMA2D_OUT_CH1_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dma2d_out_ch1_int_map; +#[doc = "DMA2D_OUT_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2d_out_ch2_int_map`] module"] +pub type DMA2D_OUT_CH2_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod dma2d_out_ch2_int_map; +#[doc = "PSRAM_MSPI_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psram_mspi_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psram_mspi_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psram_mspi_int_map`] module"] +pub type PSRAM_MSPI_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod psram_mspi_int_map; +#[doc = "HP_SYSREG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sysreg_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sysreg_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sysreg_int_map`] module"] +pub type HP_SYSREG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod hp_sysreg_int_map; +#[doc = "PCNT_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcnt_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcnt_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcnt_int_map`] module"] +pub type PCNT_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod pcnt_int_map; +#[doc = "HP_PAU_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_pau_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_pau_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_pau_int_map`] module"] +pub type HP_PAU_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod hp_pau_int_map; +#[doc = "HP_PARLIO_RX_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_parlio_rx_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_parlio_rx_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_parlio_rx_int_map`] module"] +pub type HP_PARLIO_RX_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod hp_parlio_rx_int_map; +#[doc = "HP_PARLIO_TX_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_parlio_tx_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_parlio_tx_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_parlio_tx_int_map`] module"] +pub type HP_PARLIO_TX_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod hp_parlio_tx_int_map; +#[doc = "H264_DMA2D_OUT_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_out_ch0_int_map`] module"] +pub type H264_DMA2D_OUT_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_out_ch0_int_map; +#[doc = "H264_DMA2D_OUT_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_out_ch1_int_map`] module"] +pub type H264_DMA2D_OUT_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_out_ch1_int_map; +#[doc = "H264_DMA2D_OUT_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_out_ch2_int_map`] module"] +pub type H264_DMA2D_OUT_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_out_ch2_int_map; +#[doc = "H264_DMA2D_OUT_CH3_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch3_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch3_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_out_ch3_int_map`] module"] +pub type H264_DMA2D_OUT_CH3_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_out_ch3_int_map; +#[doc = "H264_DMA2D_OUT_CH4_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch4_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch4_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_out_ch4_int_map`] module"] +pub type H264_DMA2D_OUT_CH4_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_out_ch4_int_map; +#[doc = "H264_DMA2D_IN_CH0_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch0_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch0_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch0_int_map`] module"] +pub type H264_DMA2D_IN_CH0_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch0_int_map; +#[doc = "H264_DMA2D_IN_CH1_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch1_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch1_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch1_int_map`] module"] +pub type H264_DMA2D_IN_CH1_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch1_int_map; +#[doc = "H264_DMA2D_IN_CH2_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch2_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch2_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch2_int_map`] module"] +pub type H264_DMA2D_IN_CH2_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch2_int_map; +#[doc = "H264_DMA2D_IN_CH3_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch3_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch3_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch3_int_map`] module"] +pub type H264_DMA2D_IN_CH3_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch3_int_map; +#[doc = "H264_DMA2D_IN_CH4_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch4_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch4_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch4_int_map`] module"] +pub type H264_DMA2D_IN_CH4_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch4_int_map; +#[doc = "H264_DMA2D_IN_CH5_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch5_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch5_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_dma2d_in_ch5_int_map`] module"] +pub type H264_DMA2D_IN_CH5_INT_MAP = + crate::Reg; +#[doc = "NA"] +pub mod h264_dma2d_in_ch5_int_map; +#[doc = "H264_REG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_reg_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_reg_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h264_reg_int_map`] module"] +pub type H264_REG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod h264_reg_int_map; +#[doc = "ASSIST_DEBUG_INT_MAP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`assist_debug_int_map::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`assist_debug_int_map::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@assist_debug_int_map`] module"] +pub type ASSIST_DEBUG_INT_MAP = crate::Reg; +#[doc = "NA"] +pub mod assist_debug_int_map; +#[doc = "INTR_STATUS_REG_0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status_reg_0`] module"] +pub type INTR_STATUS_REG_0 = crate::Reg; +#[doc = "NA"] +pub mod intr_status_reg_0; +#[doc = "INTR_STATUS_REG_1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status_reg_1`] module"] +pub type INTR_STATUS_REG_1 = crate::Reg; +#[doc = "NA"] +pub mod intr_status_reg_1; +#[doc = "INTR_STATUS_REG_2 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status_reg_2`] module"] +pub type INTR_STATUS_REG_2 = crate::Reg; +#[doc = "NA"] +pub mod intr_status_reg_2; +#[doc = "INTR_STATUS_REG_3 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_status_reg_3`] module"] +pub type INTR_STATUS_REG_3 = crate::Reg; +#[doc = "NA"] +pub mod intr_status_reg_3; +#[doc = "CLOCK_GATE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"] +pub type CLOCK_GATE = crate::Reg; +#[doc = "NA"] +pub mod clock_gate; +#[doc = "INTERRUPT_REG_DATE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_reg_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt_reg_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt_reg_date`] module"] +pub type INTERRUPT_REG_DATE = crate::Reg; +#[doc = "NA"] +pub mod interrupt_reg_date; diff --git a/esp32p4/src/interrupt_core1/adc_int_map.rs b/esp32p4/src/interrupt_core1/adc_int_map.rs new file mode 100644 index 0000000000..7ba8679403 --- /dev/null +++ b/esp32p4/src/interrupt_core1/adc_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ADC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `ADC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_ADC_INT_MAP` reader - NA"] +pub type CORE1_ADC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_ADC_INT_MAP` writer - NA"] +pub type CORE1_ADC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_adc_int_map(&self) -> CORE1_ADC_INT_MAP_R { + CORE1_ADC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC_INT_MAP") + .field( + "core1_adc_int_map", + &format_args!("{}", self.core1_adc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_adc_int_map(&mut self) -> CORE1_ADC_INT_MAP_W { + CORE1_ADC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ADC_INT_MAP_SPEC; +impl crate::RegisterSpec for ADC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`adc_int_map::R`](R) reader structure"] +impl crate::Readable for ADC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`adc_int_map::W`](W) writer structure"] +impl crate::Writable for ADC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ADC_INT_MAP to value 0"] +impl crate::Resettable for ADC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/aes_int_map.rs b/esp32p4/src/interrupt_core1/aes_int_map.rs new file mode 100644 index 0000000000..bcec61af22 --- /dev/null +++ b/esp32p4/src/interrupt_core1/aes_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AES_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AES_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AES_INT_MAP` reader - NA"] +pub type CORE1_AES_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AES_INT_MAP` writer - NA"] +pub type CORE1_AES_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_aes_int_map(&self) -> CORE1_AES_INT_MAP_R { + CORE1_AES_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AES_INT_MAP") + .field( + "core1_aes_int_map", + &format_args!("{}", self.core1_aes_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_aes_int_map(&mut self) -> CORE1_AES_INT_MAP_W { + CORE1_AES_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aes_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aes_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AES_INT_MAP_SPEC; +impl crate::RegisterSpec for AES_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`aes_int_map::R`](R) reader structure"] +impl crate::Readable for AES_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`aes_int_map::W`](W) writer structure"] +impl crate::Writable for AES_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AES_INT_MAP to value 0"] +impl crate::Resettable for AES_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_in_ch0_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch0_int_map.rs new file mode 100644 index 0000000000..ee589c480c --- /dev/null +++ b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_IN_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_IN_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AHB_PDMA_IN_CH0_INT_MAP` reader - NA"] +pub type CORE1_AHB_PDMA_IN_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AHB_PDMA_IN_CH0_INT_MAP` writer - NA"] +pub type CORE1_AHB_PDMA_IN_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_ahb_pdma_in_ch0_int_map(&self) -> CORE1_AHB_PDMA_IN_CH0_INT_MAP_R { + CORE1_AHB_PDMA_IN_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_IN_CH0_INT_MAP") + .field( + "core1_ahb_pdma_in_ch0_int_map", + &format_args!("{}", self.core1_ahb_pdma_in_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_ahb_pdma_in_ch0_int_map( + &mut self, + ) -> CORE1_AHB_PDMA_IN_CH0_INT_MAP_W { + CORE1_AHB_PDMA_IN_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_IN_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_IN_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_in_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_IN_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_in_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_IN_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_IN_CH0_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_IN_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_in_ch1_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch1_int_map.rs new file mode 100644 index 0000000000..14fe3f8f96 --- /dev/null +++ b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_IN_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_IN_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AHB_PDMA_IN_CH1_INT_MAP` reader - NA"] +pub type CORE1_AHB_PDMA_IN_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AHB_PDMA_IN_CH1_INT_MAP` writer - NA"] +pub type CORE1_AHB_PDMA_IN_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_ahb_pdma_in_ch1_int_map(&self) -> CORE1_AHB_PDMA_IN_CH1_INT_MAP_R { + CORE1_AHB_PDMA_IN_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_IN_CH1_INT_MAP") + .field( + "core1_ahb_pdma_in_ch1_int_map", + &format_args!("{}", self.core1_ahb_pdma_in_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_ahb_pdma_in_ch1_int_map( + &mut self, + ) -> CORE1_AHB_PDMA_IN_CH1_INT_MAP_W { + CORE1_AHB_PDMA_IN_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_IN_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_IN_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_in_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_IN_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_in_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_IN_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_IN_CH1_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_IN_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_in_ch2_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch2_int_map.rs new file mode 100644 index 0000000000..85628c788f --- /dev/null +++ b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_IN_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_IN_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AHB_PDMA_IN_CH2_INT_MAP` reader - NA"] +pub type CORE1_AHB_PDMA_IN_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AHB_PDMA_IN_CH2_INT_MAP` writer - NA"] +pub type CORE1_AHB_PDMA_IN_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_ahb_pdma_in_ch2_int_map(&self) -> CORE1_AHB_PDMA_IN_CH2_INT_MAP_R { + CORE1_AHB_PDMA_IN_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_IN_CH2_INT_MAP") + .field( + "core1_ahb_pdma_in_ch2_int_map", + &format_args!("{}", self.core1_ahb_pdma_in_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_ahb_pdma_in_ch2_int_map( + &mut self, + ) -> CORE1_AHB_PDMA_IN_CH2_INT_MAP_W { + CORE1_AHB_PDMA_IN_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_in_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_in_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_IN_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_IN_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_in_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_IN_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_in_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_IN_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_IN_CH2_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_IN_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_out_ch0_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch0_int_map.rs new file mode 100644 index 0000000000..1947ce7db2 --- /dev/null +++ b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_OUT_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_OUT_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AHB_PDMA_OUT_CH0_INT_MAP` reader - NA"] +pub type CORE1_AHB_PDMA_OUT_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AHB_PDMA_OUT_CH0_INT_MAP` writer - NA"] +pub type CORE1_AHB_PDMA_OUT_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_ahb_pdma_out_ch0_int_map(&self) -> CORE1_AHB_PDMA_OUT_CH0_INT_MAP_R { + CORE1_AHB_PDMA_OUT_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_OUT_CH0_INT_MAP") + .field( + "core1_ahb_pdma_out_ch0_int_map", + &format_args!("{}", self.core1_ahb_pdma_out_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_ahb_pdma_out_ch0_int_map( + &mut self, + ) -> CORE1_AHB_PDMA_OUT_CH0_INT_MAP_W { + CORE1_AHB_PDMA_OUT_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_OUT_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_OUT_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_out_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_OUT_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_out_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_OUT_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_OUT_CH0_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_OUT_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_out_ch1_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch1_int_map.rs new file mode 100644 index 0000000000..da41a4fecb --- /dev/null +++ b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_OUT_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_OUT_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AHB_PDMA_OUT_CH1_INT_MAP` reader - NA"] +pub type CORE1_AHB_PDMA_OUT_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AHB_PDMA_OUT_CH1_INT_MAP` writer - NA"] +pub type CORE1_AHB_PDMA_OUT_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_ahb_pdma_out_ch1_int_map(&self) -> CORE1_AHB_PDMA_OUT_CH1_INT_MAP_R { + CORE1_AHB_PDMA_OUT_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_OUT_CH1_INT_MAP") + .field( + "core1_ahb_pdma_out_ch1_int_map", + &format_args!("{}", self.core1_ahb_pdma_out_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_ahb_pdma_out_ch1_int_map( + &mut self, + ) -> CORE1_AHB_PDMA_OUT_CH1_INT_MAP_W { + CORE1_AHB_PDMA_OUT_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_OUT_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_OUT_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_out_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_OUT_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_out_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_OUT_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_OUT_CH1_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_OUT_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_out_ch2_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch2_int_map.rs new file mode 100644 index 0000000000..ea819bcba2 --- /dev/null +++ b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AHB_PDMA_OUT_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_PDMA_OUT_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AHB_PDMA_OUT_CH2_INT_MAP` reader - NA"] +pub type CORE1_AHB_PDMA_OUT_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AHB_PDMA_OUT_CH2_INT_MAP` writer - NA"] +pub type CORE1_AHB_PDMA_OUT_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_ahb_pdma_out_ch2_int_map(&self) -> CORE1_AHB_PDMA_OUT_CH2_INT_MAP_R { + CORE1_AHB_PDMA_OUT_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_PDMA_OUT_CH2_INT_MAP") + .field( + "core1_ahb_pdma_out_ch2_int_map", + &format_args!("{}", self.core1_ahb_pdma_out_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_ahb_pdma_out_ch2_int_map( + &mut self, + ) -> CORE1_AHB_PDMA_OUT_CH2_INT_MAP_W { + CORE1_AHB_PDMA_OUT_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_pdma_out_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_pdma_out_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_PDMA_OUT_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for AHB_PDMA_OUT_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_pdma_out_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for AHB_PDMA_OUT_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_pdma_out_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for AHB_PDMA_OUT_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_PDMA_OUT_CH2_INT_MAP to value 0"] +impl crate::Resettable for AHB_PDMA_OUT_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/assist_debug_int_map.rs b/esp32p4/src/interrupt_core1/assist_debug_int_map.rs new file mode 100644 index 0000000000..9620aa7493 --- /dev/null +++ b/esp32p4/src/interrupt_core1/assist_debug_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `ASSIST_DEBUG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `ASSIST_DEBUG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_ASSIST_DEBUG_INT_MAP` reader - NA"] +pub type CORE1_ASSIST_DEBUG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_ASSIST_DEBUG_INT_MAP` writer - NA"] +pub type CORE1_ASSIST_DEBUG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_assist_debug_int_map(&self) -> CORE1_ASSIST_DEBUG_INT_MAP_R { + CORE1_ASSIST_DEBUG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ASSIST_DEBUG_INT_MAP") + .field( + "core1_assist_debug_int_map", + &format_args!("{}", self.core1_assist_debug_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_assist_debug_int_map( + &mut self, + ) -> CORE1_ASSIST_DEBUG_INT_MAP_W { + CORE1_ASSIST_DEBUG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`assist_debug_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`assist_debug_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ASSIST_DEBUG_INT_MAP_SPEC; +impl crate::RegisterSpec for ASSIST_DEBUG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`assist_debug_int_map::R`](R) reader structure"] +impl crate::Readable for ASSIST_DEBUG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`assist_debug_int_map::W`](W) writer structure"] +impl crate::Writable for ASSIST_DEBUG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ASSIST_DEBUG_INT_MAP to value 0"] +impl crate::Resettable for ASSIST_DEBUG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/axi_pdma_in_ch0_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_in_ch0_int_map.rs new file mode 100644 index 0000000000..c495eb6082 --- /dev/null +++ b/esp32p4/src/interrupt_core1/axi_pdma_in_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_IN_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_IN_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AXI_PDMA_IN_CH0_INT_MAP` reader - NA"] +pub type CORE1_AXI_PDMA_IN_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AXI_PDMA_IN_CH0_INT_MAP` writer - NA"] +pub type CORE1_AXI_PDMA_IN_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_axi_pdma_in_ch0_int_map(&self) -> CORE1_AXI_PDMA_IN_CH0_INT_MAP_R { + CORE1_AXI_PDMA_IN_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_IN_CH0_INT_MAP") + .field( + "core1_axi_pdma_in_ch0_int_map", + &format_args!("{}", self.core1_axi_pdma_in_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_axi_pdma_in_ch0_int_map( + &mut self, + ) -> CORE1_AXI_PDMA_IN_CH0_INT_MAP_W { + CORE1_AXI_PDMA_IN_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_IN_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_IN_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_in_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_IN_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_in_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_IN_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_IN_CH0_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_IN_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/axi_pdma_in_ch1_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_in_ch1_int_map.rs new file mode 100644 index 0000000000..c24a6cc8f1 --- /dev/null +++ b/esp32p4/src/interrupt_core1/axi_pdma_in_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_IN_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_IN_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AXI_PDMA_IN_CH1_INT_MAP` reader - NA"] +pub type CORE1_AXI_PDMA_IN_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AXI_PDMA_IN_CH1_INT_MAP` writer - NA"] +pub type CORE1_AXI_PDMA_IN_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_axi_pdma_in_ch1_int_map(&self) -> CORE1_AXI_PDMA_IN_CH1_INT_MAP_R { + CORE1_AXI_PDMA_IN_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_IN_CH1_INT_MAP") + .field( + "core1_axi_pdma_in_ch1_int_map", + &format_args!("{}", self.core1_axi_pdma_in_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_axi_pdma_in_ch1_int_map( + &mut self, + ) -> CORE1_AXI_PDMA_IN_CH1_INT_MAP_W { + CORE1_AXI_PDMA_IN_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_IN_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_IN_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_in_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_IN_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_in_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_IN_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_IN_CH1_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_IN_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/axi_pdma_in_ch2_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_in_ch2_int_map.rs new file mode 100644 index 0000000000..50427d99cb --- /dev/null +++ b/esp32p4/src/interrupt_core1/axi_pdma_in_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_IN_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_IN_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AXI_PDMA_IN_CH2_INT_MAP` reader - NA"] +pub type CORE1_AXI_PDMA_IN_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AXI_PDMA_IN_CH2_INT_MAP` writer - NA"] +pub type CORE1_AXI_PDMA_IN_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_axi_pdma_in_ch2_int_map(&self) -> CORE1_AXI_PDMA_IN_CH2_INT_MAP_R { + CORE1_AXI_PDMA_IN_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_IN_CH2_INT_MAP") + .field( + "core1_axi_pdma_in_ch2_int_map", + &format_args!("{}", self.core1_axi_pdma_in_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_axi_pdma_in_ch2_int_map( + &mut self, + ) -> CORE1_AXI_PDMA_IN_CH2_INT_MAP_W { + CORE1_AXI_PDMA_IN_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_in_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_in_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_IN_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_IN_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_in_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_IN_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_in_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_IN_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_IN_CH2_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_IN_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/axi_pdma_out_ch0_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_out_ch0_int_map.rs new file mode 100644 index 0000000000..721933515d --- /dev/null +++ b/esp32p4/src/interrupt_core1/axi_pdma_out_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_OUT_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_OUT_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AXI_PDMA_OUT_CH0_INT_MAP` reader - NA"] +pub type CORE1_AXI_PDMA_OUT_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AXI_PDMA_OUT_CH0_INT_MAP` writer - NA"] +pub type CORE1_AXI_PDMA_OUT_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_axi_pdma_out_ch0_int_map(&self) -> CORE1_AXI_PDMA_OUT_CH0_INT_MAP_R { + CORE1_AXI_PDMA_OUT_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_OUT_CH0_INT_MAP") + .field( + "core1_axi_pdma_out_ch0_int_map", + &format_args!("{}", self.core1_axi_pdma_out_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_axi_pdma_out_ch0_int_map( + &mut self, + ) -> CORE1_AXI_PDMA_OUT_CH0_INT_MAP_W { + CORE1_AXI_PDMA_OUT_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_OUT_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_OUT_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_out_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_OUT_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_out_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_OUT_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_OUT_CH0_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_OUT_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/axi_pdma_out_ch1_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_out_ch1_int_map.rs new file mode 100644 index 0000000000..39be0f6c6e --- /dev/null +++ b/esp32p4/src/interrupt_core1/axi_pdma_out_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_OUT_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_OUT_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AXI_PDMA_OUT_CH1_INT_MAP` reader - NA"] +pub type CORE1_AXI_PDMA_OUT_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AXI_PDMA_OUT_CH1_INT_MAP` writer - NA"] +pub type CORE1_AXI_PDMA_OUT_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_axi_pdma_out_ch1_int_map(&self) -> CORE1_AXI_PDMA_OUT_CH1_INT_MAP_R { + CORE1_AXI_PDMA_OUT_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_OUT_CH1_INT_MAP") + .field( + "core1_axi_pdma_out_ch1_int_map", + &format_args!("{}", self.core1_axi_pdma_out_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_axi_pdma_out_ch1_int_map( + &mut self, + ) -> CORE1_AXI_PDMA_OUT_CH1_INT_MAP_W { + CORE1_AXI_PDMA_OUT_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_OUT_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_OUT_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_out_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_OUT_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_out_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_OUT_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_OUT_CH1_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_OUT_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/axi_pdma_out_ch2_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_out_ch2_int_map.rs new file mode 100644 index 0000000000..1b7b11833d --- /dev/null +++ b/esp32p4/src/interrupt_core1/axi_pdma_out_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AXI_PDMA_OUT_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `AXI_PDMA_OUT_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_AXI_PDMA_OUT_CH2_INT_MAP` reader - NA"] +pub type CORE1_AXI_PDMA_OUT_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_AXI_PDMA_OUT_CH2_INT_MAP` writer - NA"] +pub type CORE1_AXI_PDMA_OUT_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_axi_pdma_out_ch2_int_map(&self) -> CORE1_AXI_PDMA_OUT_CH2_INT_MAP_R { + CORE1_AXI_PDMA_OUT_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_PDMA_OUT_CH2_INT_MAP") + .field( + "core1_axi_pdma_out_ch2_int_map", + &format_args!("{}", self.core1_axi_pdma_out_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_axi_pdma_out_ch2_int_map( + &mut self, + ) -> CORE1_AXI_PDMA_OUT_CH2_INT_MAP_W { + CORE1_AXI_PDMA_OUT_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_pdma_out_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`axi_pdma_out_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AXI_PDMA_OUT_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for AXI_PDMA_OUT_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`axi_pdma_out_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for AXI_PDMA_OUT_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`axi_pdma_out_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for AXI_PDMA_OUT_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AXI_PDMA_OUT_CH2_INT_MAP to value 0"] +impl crate::Resettable for AXI_PDMA_OUT_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/cache_int_map.rs b/esp32p4/src/interrupt_core1/cache_int_map.rs new file mode 100644 index 0000000000..52df55afa9 --- /dev/null +++ b/esp32p4/src/interrupt_core1/cache_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CACHE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CACHE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CACHE_INT_MAP` reader - NA"] +pub type CORE1_CACHE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CACHE_INT_MAP` writer - NA"] +pub type CORE1_CACHE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_cache_int_map(&self) -> CORE1_CACHE_INT_MAP_R { + CORE1_CACHE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CACHE_INT_MAP") + .field( + "core1_cache_int_map", + &format_args!("{}", self.core1_cache_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_cache_int_map(&mut self) -> CORE1_CACHE_INT_MAP_W { + CORE1_CACHE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cache_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CACHE_INT_MAP_SPEC; +impl crate::RegisterSpec for CACHE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cache_int_map::R`](R) reader structure"] +impl crate::Readable for CACHE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cache_int_map::W`](W) writer structure"] +impl crate::Writable for CACHE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CACHE_INT_MAP to value 0"] +impl crate::Resettable for CACHE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/can0_int_map.rs b/esp32p4/src/interrupt_core1/can0_int_map.rs new file mode 100644 index 0000000000..79db96abd8 --- /dev/null +++ b/esp32p4/src/interrupt_core1/can0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CAN0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CAN0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CAN0_INT_MAP` reader - NA"] +pub type CORE1_CAN0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CAN0_INT_MAP` writer - NA"] +pub type CORE1_CAN0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_can0_int_map(&self) -> CORE1_CAN0_INT_MAP_R { + CORE1_CAN0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN0_INT_MAP") + .field( + "core1_can0_int_map", + &format_args!("{}", self.core1_can0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_can0_int_map(&mut self) -> CORE1_CAN0_INT_MAP_W { + CORE1_CAN0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAN0_INT_MAP_SPEC; +impl crate::RegisterSpec for CAN0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`can0_int_map::R`](R) reader structure"] +impl crate::Readable for CAN0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`can0_int_map::W`](W) writer structure"] +impl crate::Writable for CAN0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAN0_INT_MAP to value 0"] +impl crate::Resettable for CAN0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/can1_int_map.rs b/esp32p4/src/interrupt_core1/can1_int_map.rs new file mode 100644 index 0000000000..7bb5814adc --- /dev/null +++ b/esp32p4/src/interrupt_core1/can1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CAN1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CAN1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CAN1_INT_MAP` reader - NA"] +pub type CORE1_CAN1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CAN1_INT_MAP` writer - NA"] +pub type CORE1_CAN1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_can1_int_map(&self) -> CORE1_CAN1_INT_MAP_R { + CORE1_CAN1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN1_INT_MAP") + .field( + "core1_can1_int_map", + &format_args!("{}", self.core1_can1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_can1_int_map(&mut self) -> CORE1_CAN1_INT_MAP_W { + CORE1_CAN1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAN1_INT_MAP_SPEC; +impl crate::RegisterSpec for CAN1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`can1_int_map::R`](R) reader structure"] +impl crate::Readable for CAN1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`can1_int_map::W`](W) writer structure"] +impl crate::Writable for CAN1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAN1_INT_MAP to value 0"] +impl crate::Resettable for CAN1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/can2_int_map.rs b/esp32p4/src/interrupt_core1/can2_int_map.rs new file mode 100644 index 0000000000..d3c90fcb38 --- /dev/null +++ b/esp32p4/src/interrupt_core1/can2_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CAN2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CAN2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CAN2_INT_MAP` reader - NA"] +pub type CORE1_CAN2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CAN2_INT_MAP` writer - NA"] +pub type CORE1_CAN2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_can2_int_map(&self) -> CORE1_CAN2_INT_MAP_R { + CORE1_CAN2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAN2_INT_MAP") + .field( + "core1_can2_int_map", + &format_args!("{}", self.core1_can2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_can2_int_map(&mut self) -> CORE1_CAN2_INT_MAP_W { + CORE1_CAN2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`can2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`can2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAN2_INT_MAP_SPEC; +impl crate::RegisterSpec for CAN2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`can2_int_map::R`](R) reader structure"] +impl crate::Readable for CAN2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`can2_int_map::W`](W) writer structure"] +impl crate::Writable for CAN2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAN2_INT_MAP to value 0"] +impl crate::Resettable for CAN2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/clock_gate.rs b/esp32p4/src/interrupt_core1/clock_gate.rs new file mode 100644 index 0000000000..d1176b4b71 --- /dev/null +++ b/esp32p4/src/interrupt_core1/clock_gate.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CLOCK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `CLOCK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_REG_CLK_EN` reader - NA"] +pub type CORE1_REG_CLK_EN_R = crate::BitReader; +#[doc = "Field `CORE1_REG_CLK_EN` writer - NA"] +pub type CORE1_REG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn core1_reg_clk_en(&self) -> CORE1_REG_CLK_EN_R { + CORE1_REG_CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCK_GATE") + .field( + "core1_reg_clk_en", + &format_args!("{}", self.core1_reg_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_reg_clk_en(&mut self) -> CORE1_REG_CLK_EN_W { + CORE1_REG_CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLOCK_GATE_SPEC; +impl crate::RegisterSpec for CLOCK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"] +impl crate::Readable for CLOCK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"] +impl crate::Writable for CLOCK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"] +impl crate::Resettable for CLOCK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/interrupt_core1/core0_trace_int_map.rs b/esp32p4/src/interrupt_core1/core0_trace_int_map.rs new file mode 100644 index 0000000000..7776b52474 --- /dev/null +++ b/esp32p4/src/interrupt_core1/core0_trace_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE0_TRACE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CORE0_TRACE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CORE0_TRACE_INT_MAP` reader - NA"] +pub type CORE1_CORE0_TRACE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CORE0_TRACE_INT_MAP` writer - NA"] +pub type CORE1_CORE0_TRACE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_core0_trace_int_map(&self) -> CORE1_CORE0_TRACE_INT_MAP_R { + CORE1_CORE0_TRACE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE0_TRACE_INT_MAP") + .field( + "core1_core0_trace_int_map", + &format_args!("{}", self.core1_core0_trace_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_core0_trace_int_map( + &mut self, + ) -> CORE1_CORE0_TRACE_INT_MAP_W { + CORE1_CORE0_TRACE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_trace_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core0_trace_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE0_TRACE_INT_MAP_SPEC; +impl crate::RegisterSpec for CORE0_TRACE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core0_trace_int_map::R`](R) reader structure"] +impl crate::Readable for CORE0_TRACE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core0_trace_int_map::W`](W) writer structure"] +impl crate::Writable for CORE0_TRACE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE0_TRACE_INT_MAP to value 0"] +impl crate::Resettable for CORE0_TRACE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/core1_trace_int_map.rs b/esp32p4/src/interrupt_core1/core1_trace_int_map.rs new file mode 100644 index 0000000000..2f24680bed --- /dev/null +++ b/esp32p4/src/interrupt_core1/core1_trace_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CORE1_TRACE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CORE1_TRACE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CORE1_TRACE_INT_MAP` reader - NA"] +pub type CORE1_CORE1_TRACE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CORE1_TRACE_INT_MAP` writer - NA"] +pub type CORE1_CORE1_TRACE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_core1_trace_int_map(&self) -> CORE1_CORE1_TRACE_INT_MAP_R { + CORE1_CORE1_TRACE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE1_TRACE_INT_MAP") + .field( + "core1_core1_trace_int_map", + &format_args!("{}", self.core1_core1_trace_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_core1_trace_int_map( + &mut self, + ) -> CORE1_CORE1_TRACE_INT_MAP_W { + CORE1_CORE1_TRACE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core1_trace_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core1_trace_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE1_TRACE_INT_MAP_SPEC; +impl crate::RegisterSpec for CORE1_TRACE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core1_trace_int_map::R`](R) reader structure"] +impl crate::Readable for CORE1_TRACE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core1_trace_int_map::W`](W) writer structure"] +impl crate::Writable for CORE1_TRACE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE1_TRACE_INT_MAP to value 0"] +impl crate::Resettable for CORE1_TRACE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_0_map.rs b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_0_map.rs new file mode 100644 index 0000000000..6547e14949 --- /dev/null +++ b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_0_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CPU_INT_FROM_CPU_0_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CPU_INT_FROM_CPU_0_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CPU_INT_FROM_CPU_0_MAP` reader - NA"] +pub type CORE1_CPU_INT_FROM_CPU_0_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CPU_INT_FROM_CPU_0_MAP` writer - NA"] +pub type CORE1_CPU_INT_FROM_CPU_0_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_cpu_int_from_cpu_0_map(&self) -> CORE1_CPU_INT_FROM_CPU_0_MAP_R { + CORE1_CPU_INT_FROM_CPU_0_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU_INT_FROM_CPU_0_MAP") + .field( + "core1_cpu_int_from_cpu_0_map", + &format_args!("{}", self.core1_cpu_int_from_cpu_0_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_cpu_int_from_cpu_0_map( + &mut self, + ) -> CORE1_CPU_INT_FROM_CPU_0_MAP_W { + CORE1_CPU_INT_FROM_CPU_0_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_0_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_0_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_INT_FROM_CPU_0_MAP_SPEC; +impl crate::RegisterSpec for CPU_INT_FROM_CPU_0_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu_int_from_cpu_0_map::R`](R) reader structure"] +impl crate::Readable for CPU_INT_FROM_CPU_0_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpu_int_from_cpu_0_map::W`](W) writer structure"] +impl crate::Writable for CPU_INT_FROM_CPU_0_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CPU_INT_FROM_CPU_0_MAP to value 0"] +impl crate::Resettable for CPU_INT_FROM_CPU_0_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_1_map.rs b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_1_map.rs new file mode 100644 index 0000000000..1aa9d22baf --- /dev/null +++ b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_1_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CPU_INT_FROM_CPU_1_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CPU_INT_FROM_CPU_1_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CPU_INT_FROM_CPU_1_MAP` reader - NA"] +pub type CORE1_CPU_INT_FROM_CPU_1_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CPU_INT_FROM_CPU_1_MAP` writer - NA"] +pub type CORE1_CPU_INT_FROM_CPU_1_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_cpu_int_from_cpu_1_map(&self) -> CORE1_CPU_INT_FROM_CPU_1_MAP_R { + CORE1_CPU_INT_FROM_CPU_1_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU_INT_FROM_CPU_1_MAP") + .field( + "core1_cpu_int_from_cpu_1_map", + &format_args!("{}", self.core1_cpu_int_from_cpu_1_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_cpu_int_from_cpu_1_map( + &mut self, + ) -> CORE1_CPU_INT_FROM_CPU_1_MAP_W { + CORE1_CPU_INT_FROM_CPU_1_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_1_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_1_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_INT_FROM_CPU_1_MAP_SPEC; +impl crate::RegisterSpec for CPU_INT_FROM_CPU_1_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu_int_from_cpu_1_map::R`](R) reader structure"] +impl crate::Readable for CPU_INT_FROM_CPU_1_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpu_int_from_cpu_1_map::W`](W) writer structure"] +impl crate::Writable for CPU_INT_FROM_CPU_1_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CPU_INT_FROM_CPU_1_MAP to value 0"] +impl crate::Resettable for CPU_INT_FROM_CPU_1_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_2_map.rs b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_2_map.rs new file mode 100644 index 0000000000..51f954ac10 --- /dev/null +++ b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_2_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CPU_INT_FROM_CPU_2_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CPU_INT_FROM_CPU_2_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CPU_INT_FROM_CPU_2_MAP` reader - NA"] +pub type CORE1_CPU_INT_FROM_CPU_2_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CPU_INT_FROM_CPU_2_MAP` writer - NA"] +pub type CORE1_CPU_INT_FROM_CPU_2_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_cpu_int_from_cpu_2_map(&self) -> CORE1_CPU_INT_FROM_CPU_2_MAP_R { + CORE1_CPU_INT_FROM_CPU_2_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU_INT_FROM_CPU_2_MAP") + .field( + "core1_cpu_int_from_cpu_2_map", + &format_args!("{}", self.core1_cpu_int_from_cpu_2_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_cpu_int_from_cpu_2_map( + &mut self, + ) -> CORE1_CPU_INT_FROM_CPU_2_MAP_W { + CORE1_CPU_INT_FROM_CPU_2_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_2_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_2_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_INT_FROM_CPU_2_MAP_SPEC; +impl crate::RegisterSpec for CPU_INT_FROM_CPU_2_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu_int_from_cpu_2_map::R`](R) reader structure"] +impl crate::Readable for CPU_INT_FROM_CPU_2_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpu_int_from_cpu_2_map::W`](W) writer structure"] +impl crate::Writable for CPU_INT_FROM_CPU_2_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CPU_INT_FROM_CPU_2_MAP to value 0"] +impl crate::Resettable for CPU_INT_FROM_CPU_2_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_3_map.rs b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_3_map.rs new file mode 100644 index 0000000000..0848032ae2 --- /dev/null +++ b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_3_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CPU_INT_FROM_CPU_3_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CPU_INT_FROM_CPU_3_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CPU_INT_FROM_CPU_3_MAP` reader - NA"] +pub type CORE1_CPU_INT_FROM_CPU_3_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CPU_INT_FROM_CPU_3_MAP` writer - NA"] +pub type CORE1_CPU_INT_FROM_CPU_3_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_cpu_int_from_cpu_3_map(&self) -> CORE1_CPU_INT_FROM_CPU_3_MAP_R { + CORE1_CPU_INT_FROM_CPU_3_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU_INT_FROM_CPU_3_MAP") + .field( + "core1_cpu_int_from_cpu_3_map", + &format_args!("{}", self.core1_cpu_int_from_cpu_3_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_cpu_int_from_cpu_3_map( + &mut self, + ) -> CORE1_CPU_INT_FROM_CPU_3_MAP_W { + CORE1_CPU_INT_FROM_CPU_3_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_from_cpu_3_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_int_from_cpu_3_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_INT_FROM_CPU_3_MAP_SPEC; +impl crate::RegisterSpec for CPU_INT_FROM_CPU_3_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu_int_from_cpu_3_map::R`](R) reader structure"] +impl crate::Readable for CPU_INT_FROM_CPU_3_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpu_int_from_cpu_3_map::W`](W) writer structure"] +impl crate::Writable for CPU_INT_FROM_CPU_3_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CPU_INT_FROM_CPU_3_MAP to value 0"] +impl crate::Resettable for CPU_INT_FROM_CPU_3_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/csi_bridge_int_map.rs b/esp32p4/src/interrupt_core1/csi_bridge_int_map.rs new file mode 100644 index 0000000000..127cc2291e --- /dev/null +++ b/esp32p4/src/interrupt_core1/csi_bridge_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CSI_BRIDGE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CSI_BRIDGE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CSI_BRIDGE_INT_MAP` reader - NA"] +pub type CORE1_CSI_BRIDGE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CSI_BRIDGE_INT_MAP` writer - NA"] +pub type CORE1_CSI_BRIDGE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_csi_bridge_int_map(&self) -> CORE1_CSI_BRIDGE_INT_MAP_R { + CORE1_CSI_BRIDGE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CSI_BRIDGE_INT_MAP") + .field( + "core1_csi_bridge_int_map", + &format_args!("{}", self.core1_csi_bridge_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_csi_bridge_int_map( + &mut self, + ) -> CORE1_CSI_BRIDGE_INT_MAP_W { + CORE1_CSI_BRIDGE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_bridge_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_bridge_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CSI_BRIDGE_INT_MAP_SPEC; +impl crate::RegisterSpec for CSI_BRIDGE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`csi_bridge_int_map::R`](R) reader structure"] +impl crate::Readable for CSI_BRIDGE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csi_bridge_int_map::W`](W) writer structure"] +impl crate::Writable for CSI_BRIDGE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CSI_BRIDGE_INT_MAP to value 0"] +impl crate::Resettable for CSI_BRIDGE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/csi_int_map.rs b/esp32p4/src/interrupt_core1/csi_int_map.rs new file mode 100644 index 0000000000..e1f5fcdcc8 --- /dev/null +++ b/esp32p4/src/interrupt_core1/csi_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CSI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `CSI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_CSI_INT_MAP` reader - NA"] +pub type CORE1_CSI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_CSI_INT_MAP` writer - NA"] +pub type CORE1_CSI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_csi_int_map(&self) -> CORE1_CSI_INT_MAP_R { + CORE1_CSI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CSI_INT_MAP") + .field( + "core1_csi_int_map", + &format_args!("{}", self.core1_csi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_csi_int_map(&mut self) -> CORE1_CSI_INT_MAP_W { + CORE1_CSI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CSI_INT_MAP_SPEC; +impl crate::RegisterSpec for CSI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`csi_int_map::R`](R) reader structure"] +impl crate::Readable for CSI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csi_int_map::W`](W) writer structure"] +impl crate::Writable for CSI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CSI_INT_MAP to value 0"] +impl crate::Resettable for CSI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/dma2d_in_ch0_int_map.rs b/esp32p4/src/interrupt_core1/dma2d_in_ch0_int_map.rs new file mode 100644 index 0000000000..8353340c84 --- /dev/null +++ b/esp32p4/src/interrupt_core1/dma2d_in_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DMA2D_IN_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DMA2D_IN_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_DMA2D_IN_CH0_INT_MAP` reader - NA"] +pub type CORE1_DMA2D_IN_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_DMA2D_IN_CH0_INT_MAP` writer - NA"] +pub type CORE1_DMA2D_IN_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_dma2d_in_ch0_int_map(&self) -> CORE1_DMA2D_IN_CH0_INT_MAP_R { + CORE1_DMA2D_IN_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA2D_IN_CH0_INT_MAP") + .field( + "core1_dma2d_in_ch0_int_map", + &format_args!("{}", self.core1_dma2d_in_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_dma2d_in_ch0_int_map( + &mut self, + ) -> CORE1_DMA2D_IN_CH0_INT_MAP_W { + CORE1_DMA2D_IN_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_in_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_in_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA2D_IN_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for DMA2D_IN_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma2d_in_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for DMA2D_IN_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma2d_in_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for DMA2D_IN_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA2D_IN_CH0_INT_MAP to value 0"] +impl crate::Resettable for DMA2D_IN_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/dma2d_in_ch1_int_map.rs b/esp32p4/src/interrupt_core1/dma2d_in_ch1_int_map.rs new file mode 100644 index 0000000000..0ad1334016 --- /dev/null +++ b/esp32p4/src/interrupt_core1/dma2d_in_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DMA2D_IN_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DMA2D_IN_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_DMA2D_IN_CH1_INT_MAP` reader - NA"] +pub type CORE1_DMA2D_IN_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_DMA2D_IN_CH1_INT_MAP` writer - NA"] +pub type CORE1_DMA2D_IN_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_dma2d_in_ch1_int_map(&self) -> CORE1_DMA2D_IN_CH1_INT_MAP_R { + CORE1_DMA2D_IN_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA2D_IN_CH1_INT_MAP") + .field( + "core1_dma2d_in_ch1_int_map", + &format_args!("{}", self.core1_dma2d_in_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_dma2d_in_ch1_int_map( + &mut self, + ) -> CORE1_DMA2D_IN_CH1_INT_MAP_W { + CORE1_DMA2D_IN_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_in_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_in_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA2D_IN_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for DMA2D_IN_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma2d_in_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for DMA2D_IN_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma2d_in_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for DMA2D_IN_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA2D_IN_CH1_INT_MAP to value 0"] +impl crate::Resettable for DMA2D_IN_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/dma2d_out_ch0_int_map.rs b/esp32p4/src/interrupt_core1/dma2d_out_ch0_int_map.rs new file mode 100644 index 0000000000..0e32cb579b --- /dev/null +++ b/esp32p4/src/interrupt_core1/dma2d_out_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DMA2D_OUT_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DMA2D_OUT_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_DMA2D_OUT_CH0_INT_MAP` reader - NA"] +pub type CORE1_DMA2D_OUT_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_DMA2D_OUT_CH0_INT_MAP` writer - NA"] +pub type CORE1_DMA2D_OUT_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_dma2d_out_ch0_int_map(&self) -> CORE1_DMA2D_OUT_CH0_INT_MAP_R { + CORE1_DMA2D_OUT_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA2D_OUT_CH0_INT_MAP") + .field( + "core1_dma2d_out_ch0_int_map", + &format_args!("{}", self.core1_dma2d_out_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_dma2d_out_ch0_int_map( + &mut self, + ) -> CORE1_DMA2D_OUT_CH0_INT_MAP_W { + CORE1_DMA2D_OUT_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA2D_OUT_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for DMA2D_OUT_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma2d_out_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for DMA2D_OUT_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma2d_out_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for DMA2D_OUT_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA2D_OUT_CH0_INT_MAP to value 0"] +impl crate::Resettable for DMA2D_OUT_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/dma2d_out_ch1_int_map.rs b/esp32p4/src/interrupt_core1/dma2d_out_ch1_int_map.rs new file mode 100644 index 0000000000..a0089f0ea5 --- /dev/null +++ b/esp32p4/src/interrupt_core1/dma2d_out_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DMA2D_OUT_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DMA2D_OUT_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_DMA2D_OUT_CH1_INT_MAP` reader - NA"] +pub type CORE1_DMA2D_OUT_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_DMA2D_OUT_CH1_INT_MAP` writer - NA"] +pub type CORE1_DMA2D_OUT_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_dma2d_out_ch1_int_map(&self) -> CORE1_DMA2D_OUT_CH1_INT_MAP_R { + CORE1_DMA2D_OUT_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA2D_OUT_CH1_INT_MAP") + .field( + "core1_dma2d_out_ch1_int_map", + &format_args!("{}", self.core1_dma2d_out_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_dma2d_out_ch1_int_map( + &mut self, + ) -> CORE1_DMA2D_OUT_CH1_INT_MAP_W { + CORE1_DMA2D_OUT_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA2D_OUT_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for DMA2D_OUT_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma2d_out_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for DMA2D_OUT_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma2d_out_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for DMA2D_OUT_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA2D_OUT_CH1_INT_MAP to value 0"] +impl crate::Resettable for DMA2D_OUT_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/dma2d_out_ch2_int_map.rs b/esp32p4/src/interrupt_core1/dma2d_out_ch2_int_map.rs new file mode 100644 index 0000000000..8c03f47505 --- /dev/null +++ b/esp32p4/src/interrupt_core1/dma2d_out_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DMA2D_OUT_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DMA2D_OUT_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_DMA2D_OUT_CH2_INT_MAP` reader - NA"] +pub type CORE1_DMA2D_OUT_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_DMA2D_OUT_CH2_INT_MAP` writer - NA"] +pub type CORE1_DMA2D_OUT_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_dma2d_out_ch2_int_map(&self) -> CORE1_DMA2D_OUT_CH2_INT_MAP_R { + CORE1_DMA2D_OUT_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA2D_OUT_CH2_INT_MAP") + .field( + "core1_dma2d_out_ch2_int_map", + &format_args!("{}", self.core1_dma2d_out_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_dma2d_out_ch2_int_map( + &mut self, + ) -> CORE1_DMA2D_OUT_CH2_INT_MAP_W { + CORE1_DMA2D_OUT_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma2d_out_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma2d_out_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA2D_OUT_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for DMA2D_OUT_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma2d_out_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for DMA2D_OUT_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma2d_out_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for DMA2D_OUT_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA2D_OUT_CH2_INT_MAP to value 0"] +impl crate::Resettable for DMA2D_OUT_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/dsi_bridge_int_map.rs b/esp32p4/src/interrupt_core1/dsi_bridge_int_map.rs new file mode 100644 index 0000000000..a438090195 --- /dev/null +++ b/esp32p4/src/interrupt_core1/dsi_bridge_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `DSI_BRIDGE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DSI_BRIDGE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_DSI_BRIDGE_INT_MAP` reader - NA"] +pub type CORE1_DSI_BRIDGE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_DSI_BRIDGE_INT_MAP` writer - NA"] +pub type CORE1_DSI_BRIDGE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_dsi_bridge_int_map(&self) -> CORE1_DSI_BRIDGE_INT_MAP_R { + CORE1_DSI_BRIDGE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSI_BRIDGE_INT_MAP") + .field( + "core1_dsi_bridge_int_map", + &format_args!("{}", self.core1_dsi_bridge_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_dsi_bridge_int_map( + &mut self, + ) -> CORE1_DSI_BRIDGE_INT_MAP_W { + CORE1_DSI_BRIDGE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsi_bridge_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsi_bridge_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DSI_BRIDGE_INT_MAP_SPEC; +impl crate::RegisterSpec for DSI_BRIDGE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dsi_bridge_int_map::R`](R) reader structure"] +impl crate::Readable for DSI_BRIDGE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dsi_bridge_int_map::W`](W) writer structure"] +impl crate::Writable for DSI_BRIDGE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DSI_BRIDGE_INT_MAP to value 0"] +impl crate::Resettable for DSI_BRIDGE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/dsi_int_map.rs b/esp32p4/src/interrupt_core1/dsi_int_map.rs new file mode 100644 index 0000000000..8390bf1ea1 --- /dev/null +++ b/esp32p4/src/interrupt_core1/dsi_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DSI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `DSI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_DSI_INT_MAP` reader - NA"] +pub type CORE1_DSI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_DSI_INT_MAP` writer - NA"] +pub type CORE1_DSI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_dsi_int_map(&self) -> CORE1_DSI_INT_MAP_R { + CORE1_DSI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSI_INT_MAP") + .field( + "core1_dsi_int_map", + &format_args!("{}", self.core1_dsi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_dsi_int_map(&mut self) -> CORE1_DSI_INT_MAP_W { + CORE1_DSI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DSI_INT_MAP_SPEC; +impl crate::RegisterSpec for DSI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dsi_int_map::R`](R) reader structure"] +impl crate::Readable for DSI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dsi_int_map::W`](W) writer structure"] +impl crate::Writable for DSI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DSI_INT_MAP to value 0"] +impl crate::Resettable for DSI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/ecc_int_map.rs b/esp32p4/src/interrupt_core1/ecc_int_map.rs new file mode 100644 index 0000000000..af401afbf6 --- /dev/null +++ b/esp32p4/src/interrupt_core1/ecc_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ECC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `ECC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_ECC_INT_MAP` reader - NA"] +pub type CORE1_ECC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_ECC_INT_MAP` writer - NA"] +pub type CORE1_ECC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_ecc_int_map(&self) -> CORE1_ECC_INT_MAP_R { + CORE1_ECC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECC_INT_MAP") + .field( + "core1_ecc_int_map", + &format_args!("{}", self.core1_ecc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_ecc_int_map(&mut self) -> CORE1_ECC_INT_MAP_W { + CORE1_ECC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECC_INT_MAP_SPEC; +impl crate::RegisterSpec for ECC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ecc_int_map::R`](R) reader structure"] +impl crate::Readable for ECC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ecc_int_map::W`](W) writer structure"] +impl crate::Writable for ECC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECC_INT_MAP to value 0"] +impl crate::Resettable for ECC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/ecdsa_int_map.rs b/esp32p4/src/interrupt_core1/ecdsa_int_map.rs new file mode 100644 index 0000000000..1066bddde9 --- /dev/null +++ b/esp32p4/src/interrupt_core1/ecdsa_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ECDSA_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `ECDSA_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_ECDSA_INT_MAP` reader - NA"] +pub type CORE1_ECDSA_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_ECDSA_INT_MAP` writer - NA"] +pub type CORE1_ECDSA_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_ecdsa_int_map(&self) -> CORE1_ECDSA_INT_MAP_R { + CORE1_ECDSA_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECDSA_INT_MAP") + .field( + "core1_ecdsa_int_map", + &format_args!("{}", self.core1_ecdsa_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_ecdsa_int_map(&mut self) -> CORE1_ECDSA_INT_MAP_W { + CORE1_ECDSA_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecdsa_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecdsa_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECDSA_INT_MAP_SPEC; +impl crate::RegisterSpec for ECDSA_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ecdsa_int_map::R`](R) reader structure"] +impl crate::Readable for ECDSA_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ecdsa_int_map::W`](W) writer structure"] +impl crate::Writable for ECDSA_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECDSA_INT_MAP to value 0"] +impl crate::Resettable for ECDSA_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/flash_mspi_int_map.rs b/esp32p4/src/interrupt_core1/flash_mspi_int_map.rs new file mode 100644 index 0000000000..a8d4ecc4d5 --- /dev/null +++ b/esp32p4/src/interrupt_core1/flash_mspi_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `FLASH_MSPI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `FLASH_MSPI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_FLASH_MSPI_INT_MAP` reader - NA"] +pub type CORE1_FLASH_MSPI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_FLASH_MSPI_INT_MAP` writer - NA"] +pub type CORE1_FLASH_MSPI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_flash_mspi_int_map(&self) -> CORE1_FLASH_MSPI_INT_MAP_R { + CORE1_FLASH_MSPI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FLASH_MSPI_INT_MAP") + .field( + "core1_flash_mspi_int_map", + &format_args!("{}", self.core1_flash_mspi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_flash_mspi_int_map( + &mut self, + ) -> CORE1_FLASH_MSPI_INT_MAP_W { + CORE1_FLASH_MSPI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flash_mspi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flash_mspi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FLASH_MSPI_INT_MAP_SPEC; +impl crate::RegisterSpec for FLASH_MSPI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`flash_mspi_int_map::R`](R) reader structure"] +impl crate::Readable for FLASH_MSPI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`flash_mspi_int_map::W`](W) writer structure"] +impl crate::Writable for FLASH_MSPI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FLASH_MSPI_INT_MAP to value 0"] +impl crate::Resettable for FLASH_MSPI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/gdma_int_map.rs b/esp32p4/src/interrupt_core1/gdma_int_map.rs new file mode 100644 index 0000000000..b712939078 --- /dev/null +++ b/esp32p4/src/interrupt_core1/gdma_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GDMA_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GDMA_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_GDMA_INT_MAP` reader - NA"] +pub type CORE1_GDMA_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_GDMA_INT_MAP` writer - NA"] +pub type CORE1_GDMA_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_gdma_int_map(&self) -> CORE1_GDMA_INT_MAP_R { + CORE1_GDMA_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GDMA_INT_MAP") + .field( + "core1_gdma_int_map", + &format_args!("{}", self.core1_gdma_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_gdma_int_map(&mut self) -> CORE1_GDMA_INT_MAP_W { + CORE1_GDMA_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdma_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdma_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GDMA_INT_MAP_SPEC; +impl crate::RegisterSpec for GDMA_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gdma_int_map::R`](R) reader structure"] +impl crate::Readable for GDMA_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gdma_int_map::W`](W) writer structure"] +impl crate::Writable for GDMA_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GDMA_INT_MAP to value 0"] +impl crate::Resettable for GDMA_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/gmii_phy_int_map.rs b/esp32p4/src/interrupt_core1/gmii_phy_int_map.rs new file mode 100644 index 0000000000..fb9358d2df --- /dev/null +++ b/esp32p4/src/interrupt_core1/gmii_phy_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GMII_PHY_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GMII_PHY_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_GMII_PHY_INT_MAP` reader - NA"] +pub type CORE1_GMII_PHY_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_GMII_PHY_INT_MAP` writer - NA"] +pub type CORE1_GMII_PHY_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_gmii_phy_int_map(&self) -> CORE1_GMII_PHY_INT_MAP_R { + CORE1_GMII_PHY_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GMII_PHY_INT_MAP") + .field( + "core1_gmii_phy_int_map", + &format_args!("{}", self.core1_gmii_phy_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_gmii_phy_int_map(&mut self) -> CORE1_GMII_PHY_INT_MAP_W { + CORE1_GMII_PHY_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmii_phy_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmii_phy_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GMII_PHY_INT_MAP_SPEC; +impl crate::RegisterSpec for GMII_PHY_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmii_phy_int_map::R`](R) reader structure"] +impl crate::Readable for GMII_PHY_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gmii_phy_int_map::W`](W) writer structure"] +impl crate::Writable for GMII_PHY_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GMII_PHY_INT_MAP to value 0"] +impl crate::Resettable for GMII_PHY_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/gpio_int0_map.rs b/esp32p4/src/interrupt_core1/gpio_int0_map.rs new file mode 100644 index 0000000000..e73369f657 --- /dev/null +++ b/esp32p4/src/interrupt_core1/gpio_int0_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GPIO_INT0_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_INT0_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_GPIO_INT0_MAP` reader - NA"] +pub type CORE1_GPIO_INT0_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_GPIO_INT0_MAP` writer - NA"] +pub type CORE1_GPIO_INT0_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_gpio_int0_map(&self) -> CORE1_GPIO_INT0_MAP_R { + CORE1_GPIO_INT0_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_INT0_MAP") + .field( + "core1_gpio_int0_map", + &format_args!("{}", self.core1_gpio_int0_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_gpio_int0_map(&mut self) -> CORE1_GPIO_INT0_MAP_W { + CORE1_GPIO_INT0_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int0_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int0_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_INT0_MAP_SPEC; +impl crate::RegisterSpec for GPIO_INT0_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_int0_map::R`](R) reader structure"] +impl crate::Readable for GPIO_INT0_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_int0_map::W`](W) writer structure"] +impl crate::Writable for GPIO_INT0_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GPIO_INT0_MAP to value 0"] +impl crate::Resettable for GPIO_INT0_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/gpio_int1_map.rs b/esp32p4/src/interrupt_core1/gpio_int1_map.rs new file mode 100644 index 0000000000..a9315ba46d --- /dev/null +++ b/esp32p4/src/interrupt_core1/gpio_int1_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GPIO_INT1_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_INT1_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_GPIO_INT1_MAP` reader - NA"] +pub type CORE1_GPIO_INT1_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_GPIO_INT1_MAP` writer - NA"] +pub type CORE1_GPIO_INT1_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_gpio_int1_map(&self) -> CORE1_GPIO_INT1_MAP_R { + CORE1_GPIO_INT1_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_INT1_MAP") + .field( + "core1_gpio_int1_map", + &format_args!("{}", self.core1_gpio_int1_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_gpio_int1_map(&mut self) -> CORE1_GPIO_INT1_MAP_W { + CORE1_GPIO_INT1_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int1_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int1_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_INT1_MAP_SPEC; +impl crate::RegisterSpec for GPIO_INT1_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_int1_map::R`](R) reader structure"] +impl crate::Readable for GPIO_INT1_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_int1_map::W`](W) writer structure"] +impl crate::Writable for GPIO_INT1_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GPIO_INT1_MAP to value 0"] +impl crate::Resettable for GPIO_INT1_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/gpio_int2_map.rs b/esp32p4/src/interrupt_core1/gpio_int2_map.rs new file mode 100644 index 0000000000..5079468e78 --- /dev/null +++ b/esp32p4/src/interrupt_core1/gpio_int2_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GPIO_INT2_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_INT2_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_GPIO_INT2_MAP` reader - NA"] +pub type CORE1_GPIO_INT2_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_GPIO_INT2_MAP` writer - NA"] +pub type CORE1_GPIO_INT2_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_gpio_int2_map(&self) -> CORE1_GPIO_INT2_MAP_R { + CORE1_GPIO_INT2_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_INT2_MAP") + .field( + "core1_gpio_int2_map", + &format_args!("{}", self.core1_gpio_int2_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_gpio_int2_map(&mut self) -> CORE1_GPIO_INT2_MAP_W { + CORE1_GPIO_INT2_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int2_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int2_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_INT2_MAP_SPEC; +impl crate::RegisterSpec for GPIO_INT2_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_int2_map::R`](R) reader structure"] +impl crate::Readable for GPIO_INT2_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_int2_map::W`](W) writer structure"] +impl crate::Writable for GPIO_INT2_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GPIO_INT2_MAP to value 0"] +impl crate::Resettable for GPIO_INT2_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/gpio_int3_map.rs b/esp32p4/src/interrupt_core1/gpio_int3_map.rs new file mode 100644 index 0000000000..be04d78c74 --- /dev/null +++ b/esp32p4/src/interrupt_core1/gpio_int3_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `GPIO_INT3_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_INT3_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_GPIO_INT3_MAP` reader - NA"] +pub type CORE1_GPIO_INT3_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_GPIO_INT3_MAP` writer - NA"] +pub type CORE1_GPIO_INT3_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_gpio_int3_map(&self) -> CORE1_GPIO_INT3_MAP_R { + CORE1_GPIO_INT3_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_INT3_MAP") + .field( + "core1_gpio_int3_map", + &format_args!("{}", self.core1_gpio_int3_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_gpio_int3_map(&mut self) -> CORE1_GPIO_INT3_MAP_W { + CORE1_GPIO_INT3_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_int3_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_int3_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_INT3_MAP_SPEC; +impl crate::RegisterSpec for GPIO_INT3_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_int3_map::R`](R) reader structure"] +impl crate::Readable for GPIO_INT3_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_int3_map::W`](W) writer structure"] +impl crate::Writable for GPIO_INT3_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GPIO_INT3_MAP to value 0"] +impl crate::Resettable for GPIO_INT3_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/gpio_pad_comp_int_map.rs b/esp32p4/src/interrupt_core1/gpio_pad_comp_int_map.rs new file mode 100644 index 0000000000..c7132293d6 --- /dev/null +++ b/esp32p4/src/interrupt_core1/gpio_pad_comp_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `GPIO_PAD_COMP_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_PAD_COMP_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_GPIO_PAD_COMP_INT_MAP` reader - NA"] +pub type CORE1_GPIO_PAD_COMP_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_GPIO_PAD_COMP_INT_MAP` writer - NA"] +pub type CORE1_GPIO_PAD_COMP_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_gpio_pad_comp_int_map(&self) -> CORE1_GPIO_PAD_COMP_INT_MAP_R { + CORE1_GPIO_PAD_COMP_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_PAD_COMP_INT_MAP") + .field( + "core1_gpio_pad_comp_int_map", + &format_args!("{}", self.core1_gpio_pad_comp_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_gpio_pad_comp_int_map( + &mut self, + ) -> CORE1_GPIO_PAD_COMP_INT_MAP_W { + CORE1_GPIO_PAD_COMP_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_pad_comp_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio_pad_comp_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_PAD_COMP_INT_MAP_SPEC; +impl crate::RegisterSpec for GPIO_PAD_COMP_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_pad_comp_int_map::R`](R) reader structure"] +impl crate::Readable for GPIO_PAD_COMP_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_pad_comp_int_map::W`](W) writer structure"] +impl crate::Writable for GPIO_PAD_COMP_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GPIO_PAD_COMP_INT_MAP to value 0"] +impl crate::Resettable for GPIO_PAD_COMP_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch0_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch0_int_map.rs new file mode 100644 index 0000000000..807c42d3ff --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH0_INT_MAP` reader - NA"] +pub type CORE1_H264_DMA2D_IN_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH0_INT_MAP` writer - NA"] +pub type CORE1_H264_DMA2D_IN_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_dma2d_in_ch0_int_map(&self) -> CORE1_H264_DMA2D_IN_CH0_INT_MAP_R { + CORE1_H264_DMA2D_IN_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH0_INT_MAP") + .field( + "core1_h264_dma2d_in_ch0_int_map", + &format_args!("{}", self.core1_h264_dma2d_in_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_dma2d_in_ch0_int_map( + &mut self, + ) -> CORE1_H264_DMA2D_IN_CH0_INT_MAP_W { + CORE1_H264_DMA2D_IN_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH0_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch1_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch1_int_map.rs new file mode 100644 index 0000000000..08b1f10c83 --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH1_INT_MAP` reader - NA"] +pub type CORE1_H264_DMA2D_IN_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH1_INT_MAP` writer - NA"] +pub type CORE1_H264_DMA2D_IN_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_dma2d_in_ch1_int_map(&self) -> CORE1_H264_DMA2D_IN_CH1_INT_MAP_R { + CORE1_H264_DMA2D_IN_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH1_INT_MAP") + .field( + "core1_h264_dma2d_in_ch1_int_map", + &format_args!("{}", self.core1_h264_dma2d_in_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_dma2d_in_ch1_int_map( + &mut self, + ) -> CORE1_H264_DMA2D_IN_CH1_INT_MAP_W { + CORE1_H264_DMA2D_IN_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH1_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch2_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch2_int_map.rs new file mode 100644 index 0000000000..b06292905f --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH2_INT_MAP` reader - NA"] +pub type CORE1_H264_DMA2D_IN_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH2_INT_MAP` writer - NA"] +pub type CORE1_H264_DMA2D_IN_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_dma2d_in_ch2_int_map(&self) -> CORE1_H264_DMA2D_IN_CH2_INT_MAP_R { + CORE1_H264_DMA2D_IN_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH2_INT_MAP") + .field( + "core1_h264_dma2d_in_ch2_int_map", + &format_args!("{}", self.core1_h264_dma2d_in_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_dma2d_in_ch2_int_map( + &mut self, + ) -> CORE1_H264_DMA2D_IN_CH2_INT_MAP_W { + CORE1_H264_DMA2D_IN_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH2_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch3_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch3_int_map.rs new file mode 100644 index 0000000000..4cdf2f3320 --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch3_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH3_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH3_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH3_INT_MAP` reader - NA"] +pub type CORE1_H264_DMA2D_IN_CH3_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH3_INT_MAP` writer - NA"] +pub type CORE1_H264_DMA2D_IN_CH3_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_dma2d_in_ch3_int_map(&self) -> CORE1_H264_DMA2D_IN_CH3_INT_MAP_R { + CORE1_H264_DMA2D_IN_CH3_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH3_INT_MAP") + .field( + "core1_h264_dma2d_in_ch3_int_map", + &format_args!("{}", self.core1_h264_dma2d_in_ch3_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_dma2d_in_ch3_int_map( + &mut self, + ) -> CORE1_H264_DMA2D_IN_CH3_INT_MAP_W { + CORE1_H264_DMA2D_IN_CH3_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch3_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch3_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH3_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH3_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch3_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH3_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch3_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH3_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH3_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH3_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch4_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch4_int_map.rs new file mode 100644 index 0000000000..e11d7150db --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch4_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH4_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH4_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH4_INT_MAP` reader - NA"] +pub type CORE1_H264_DMA2D_IN_CH4_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH4_INT_MAP` writer - NA"] +pub type CORE1_H264_DMA2D_IN_CH4_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_dma2d_in_ch4_int_map(&self) -> CORE1_H264_DMA2D_IN_CH4_INT_MAP_R { + CORE1_H264_DMA2D_IN_CH4_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH4_INT_MAP") + .field( + "core1_h264_dma2d_in_ch4_int_map", + &format_args!("{}", self.core1_h264_dma2d_in_ch4_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_dma2d_in_ch4_int_map( + &mut self, + ) -> CORE1_H264_DMA2D_IN_CH4_INT_MAP_W { + CORE1_H264_DMA2D_IN_CH4_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch4_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch4_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH4_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH4_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch4_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH4_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch4_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH4_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH4_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH4_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch5_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch5_int_map.rs new file mode 100644 index 0000000000..eea6c81b5f --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch5_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_IN_CH5_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_IN_CH5_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH5_INT_MAP` reader - NA"] +pub type CORE1_H264_DMA2D_IN_CH5_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_DMA2D_IN_CH5_INT_MAP` writer - NA"] +pub type CORE1_H264_DMA2D_IN_CH5_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_dma2d_in_ch5_int_map(&self) -> CORE1_H264_DMA2D_IN_CH5_INT_MAP_R { + CORE1_H264_DMA2D_IN_CH5_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_IN_CH5_INT_MAP") + .field( + "core1_h264_dma2d_in_ch5_int_map", + &format_args!("{}", self.core1_h264_dma2d_in_ch5_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_dma2d_in_ch5_int_map( + &mut self, + ) -> CORE1_H264_DMA2D_IN_CH5_INT_MAP_W { + CORE1_H264_DMA2D_IN_CH5_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_in_ch5_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_in_ch5_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_IN_CH5_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_IN_CH5_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_in_ch5_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_IN_CH5_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_in_ch5_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_IN_CH5_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_IN_CH5_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_IN_CH5_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch0_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch0_int_map.rs new file mode 100644 index 0000000000..29e7bded9c --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_OUT_CH0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_OUT_CH0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_DMA2D_OUT_CH0_INT_MAP` reader - NA"] +pub type CORE1_H264_DMA2D_OUT_CH0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_DMA2D_OUT_CH0_INT_MAP` writer - NA"] +pub type CORE1_H264_DMA2D_OUT_CH0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_dma2d_out_ch0_int_map(&self) -> CORE1_H264_DMA2D_OUT_CH0_INT_MAP_R { + CORE1_H264_DMA2D_OUT_CH0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_OUT_CH0_INT_MAP") + .field( + "core1_h264_dma2d_out_ch0_int_map", + &format_args!("{}", self.core1_h264_dma2d_out_ch0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_dma2d_out_ch0_int_map( + &mut self, + ) -> CORE1_H264_DMA2D_OUT_CH0_INT_MAP_W { + CORE1_H264_DMA2D_OUT_CH0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_OUT_CH0_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_OUT_CH0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_out_ch0_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_OUT_CH0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_out_ch0_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_OUT_CH0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_OUT_CH0_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_OUT_CH0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch1_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch1_int_map.rs new file mode 100644 index 0000000000..a362bcd7c4 --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_OUT_CH1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_OUT_CH1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_DMA2D_OUT_CH1_INT_MAP` reader - NA"] +pub type CORE1_H264_DMA2D_OUT_CH1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_DMA2D_OUT_CH1_INT_MAP` writer - NA"] +pub type CORE1_H264_DMA2D_OUT_CH1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_dma2d_out_ch1_int_map(&self) -> CORE1_H264_DMA2D_OUT_CH1_INT_MAP_R { + CORE1_H264_DMA2D_OUT_CH1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_OUT_CH1_INT_MAP") + .field( + "core1_h264_dma2d_out_ch1_int_map", + &format_args!("{}", self.core1_h264_dma2d_out_ch1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_dma2d_out_ch1_int_map( + &mut self, + ) -> CORE1_H264_DMA2D_OUT_CH1_INT_MAP_W { + CORE1_H264_DMA2D_OUT_CH1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_OUT_CH1_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_OUT_CH1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_out_ch1_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_OUT_CH1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_out_ch1_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_OUT_CH1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_OUT_CH1_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_OUT_CH1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch2_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch2_int_map.rs new file mode 100644 index 0000000000..2283dc79f2 --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_OUT_CH2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_OUT_CH2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_DMA2D_OUT_CH2_INT_MAP` reader - NA"] +pub type CORE1_H264_DMA2D_OUT_CH2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_DMA2D_OUT_CH2_INT_MAP` writer - NA"] +pub type CORE1_H264_DMA2D_OUT_CH2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_dma2d_out_ch2_int_map(&self) -> CORE1_H264_DMA2D_OUT_CH2_INT_MAP_R { + CORE1_H264_DMA2D_OUT_CH2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_OUT_CH2_INT_MAP") + .field( + "core1_h264_dma2d_out_ch2_int_map", + &format_args!("{}", self.core1_h264_dma2d_out_ch2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_dma2d_out_ch2_int_map( + &mut self, + ) -> CORE1_H264_DMA2D_OUT_CH2_INT_MAP_W { + CORE1_H264_DMA2D_OUT_CH2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_OUT_CH2_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_OUT_CH2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_out_ch2_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_OUT_CH2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_out_ch2_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_OUT_CH2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_OUT_CH2_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_OUT_CH2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch3_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch3_int_map.rs new file mode 100644 index 0000000000..8423182d6b --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch3_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_OUT_CH3_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_OUT_CH3_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_DMA2D_OUT_CH3_INT_MAP` reader - NA"] +pub type CORE1_H264_DMA2D_OUT_CH3_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_DMA2D_OUT_CH3_INT_MAP` writer - NA"] +pub type CORE1_H264_DMA2D_OUT_CH3_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_dma2d_out_ch3_int_map(&self) -> CORE1_H264_DMA2D_OUT_CH3_INT_MAP_R { + CORE1_H264_DMA2D_OUT_CH3_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_OUT_CH3_INT_MAP") + .field( + "core1_h264_dma2d_out_ch3_int_map", + &format_args!("{}", self.core1_h264_dma2d_out_ch3_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_dma2d_out_ch3_int_map( + &mut self, + ) -> CORE1_H264_DMA2D_OUT_CH3_INT_MAP_W { + CORE1_H264_DMA2D_OUT_CH3_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch3_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch3_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_OUT_CH3_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_OUT_CH3_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_out_ch3_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_OUT_CH3_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_out_ch3_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_OUT_CH3_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_OUT_CH3_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_OUT_CH3_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch4_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch4_int_map.rs new file mode 100644 index 0000000000..85e6ec5b5c --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch4_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `H264_DMA2D_OUT_CH4_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_DMA2D_OUT_CH4_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_DMA2D_OUT_CH4_INT_MAP` reader - NA"] +pub type CORE1_H264_DMA2D_OUT_CH4_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_DMA2D_OUT_CH4_INT_MAP` writer - NA"] +pub type CORE1_H264_DMA2D_OUT_CH4_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_dma2d_out_ch4_int_map(&self) -> CORE1_H264_DMA2D_OUT_CH4_INT_MAP_R { + CORE1_H264_DMA2D_OUT_CH4_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA2D_OUT_CH4_INT_MAP") + .field( + "core1_h264_dma2d_out_ch4_int_map", + &format_args!("{}", self.core1_h264_dma2d_out_ch4_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_dma2d_out_ch4_int_map( + &mut self, + ) -> CORE1_H264_DMA2D_OUT_CH4_INT_MAP_W { + CORE1_H264_DMA2D_OUT_CH4_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_dma2d_out_ch4_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_dma2d_out_ch4_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_DMA2D_OUT_CH4_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_DMA2D_OUT_CH4_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_dma2d_out_ch4_int_map::R`](R) reader structure"] +impl crate::Readable for H264_DMA2D_OUT_CH4_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_dma2d_out_ch4_int_map::W`](W) writer structure"] +impl crate::Writable for H264_DMA2D_OUT_CH4_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_DMA2D_OUT_CH4_INT_MAP to value 0"] +impl crate::Resettable for H264_DMA2D_OUT_CH4_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/h264_reg_int_map.rs b/esp32p4/src/interrupt_core1/h264_reg_int_map.rs new file mode 100644 index 0000000000..9e67242bc7 --- /dev/null +++ b/esp32p4/src/interrupt_core1/h264_reg_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `H264_REG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `H264_REG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_H264_REG_INT_MAP` reader - NA"] +pub type CORE1_H264_REG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_H264_REG_INT_MAP` writer - NA"] +pub type CORE1_H264_REG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_h264_reg_int_map(&self) -> CORE1_H264_REG_INT_MAP_R { + CORE1_H264_REG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_REG_INT_MAP") + .field( + "core1_h264_reg_int_map", + &format_args!("{}", self.core1_h264_reg_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_h264_reg_int_map(&mut self) -> CORE1_H264_REG_INT_MAP_W { + CORE1_H264_REG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h264_reg_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h264_reg_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H264_REG_INT_MAP_SPEC; +impl crate::RegisterSpec for H264_REG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`h264_reg_int_map::R`](R) reader structure"] +impl crate::Readable for H264_REG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h264_reg_int_map::W`](W) writer structure"] +impl crate::Writable for H264_REG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H264_REG_INT_MAP to value 0"] +impl crate::Resettable for H264_REG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/hp_core_ctrl_int_map.rs b/esp32p4/src/interrupt_core1/hp_core_ctrl_int_map.rs new file mode 100644 index 0000000000..ac853961df --- /dev/null +++ b/esp32p4/src/interrupt_core1/hp_core_ctrl_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_CORE_CTRL_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CORE_CTRL_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_HP_CORE_CTRL_INT_MAP` reader - NA"] +pub type CORE1_HP_CORE_CTRL_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_HP_CORE_CTRL_INT_MAP` writer - NA"] +pub type CORE1_HP_CORE_CTRL_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_hp_core_ctrl_int_map(&self) -> CORE1_HP_CORE_CTRL_INT_MAP_R { + CORE1_HP_CORE_CTRL_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CORE_CTRL_INT_MAP") + .field( + "core1_hp_core_ctrl_int_map", + &format_args!("{}", self.core1_hp_core_ctrl_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_hp_core_ctrl_int_map( + &mut self, + ) -> CORE1_HP_CORE_CTRL_INT_MAP_W { + CORE1_HP_CORE_CTRL_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_core_ctrl_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_core_ctrl_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CORE_CTRL_INT_MAP_SPEC; +impl crate::RegisterSpec for HP_CORE_CTRL_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_core_ctrl_int_map::R`](R) reader structure"] +impl crate::Readable for HP_CORE_CTRL_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_core_ctrl_int_map::W`](W) writer structure"] +impl crate::Writable for HP_CORE_CTRL_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CORE_CTRL_INT_MAP to value 0"] +impl crate::Resettable for HP_CORE_CTRL_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/hp_parlio_rx_int_map.rs b/esp32p4/src/interrupt_core1/hp_parlio_rx_int_map.rs new file mode 100644 index 0000000000..d2c93d7b18 --- /dev/null +++ b/esp32p4/src/interrupt_core1/hp_parlio_rx_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_PARLIO_RX_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_PARLIO_RX_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_HP_PARLIO_RX_INT_MAP` reader - NA"] +pub type CORE1_HP_PARLIO_RX_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_HP_PARLIO_RX_INT_MAP` writer - NA"] +pub type CORE1_HP_PARLIO_RX_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_hp_parlio_rx_int_map(&self) -> CORE1_HP_PARLIO_RX_INT_MAP_R { + CORE1_HP_PARLIO_RX_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PARLIO_RX_INT_MAP") + .field( + "core1_hp_parlio_rx_int_map", + &format_args!("{}", self.core1_hp_parlio_rx_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_hp_parlio_rx_int_map( + &mut self, + ) -> CORE1_HP_PARLIO_RX_INT_MAP_W { + CORE1_HP_PARLIO_RX_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_parlio_rx_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_parlio_rx_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PARLIO_RX_INT_MAP_SPEC; +impl crate::RegisterSpec for HP_PARLIO_RX_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_parlio_rx_int_map::R`](R) reader structure"] +impl crate::Readable for HP_PARLIO_RX_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_parlio_rx_int_map::W`](W) writer structure"] +impl crate::Writable for HP_PARLIO_RX_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_PARLIO_RX_INT_MAP to value 0"] +impl crate::Resettable for HP_PARLIO_RX_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/hp_parlio_tx_int_map.rs b/esp32p4/src/interrupt_core1/hp_parlio_tx_int_map.rs new file mode 100644 index 0000000000..a6bdb85081 --- /dev/null +++ b/esp32p4/src/interrupt_core1/hp_parlio_tx_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_PARLIO_TX_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_PARLIO_TX_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_HP_PARLIO_TX_INT_MAP` reader - NA"] +pub type CORE1_HP_PARLIO_TX_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_HP_PARLIO_TX_INT_MAP` writer - NA"] +pub type CORE1_HP_PARLIO_TX_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_hp_parlio_tx_int_map(&self) -> CORE1_HP_PARLIO_TX_INT_MAP_R { + CORE1_HP_PARLIO_TX_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PARLIO_TX_INT_MAP") + .field( + "core1_hp_parlio_tx_int_map", + &format_args!("{}", self.core1_hp_parlio_tx_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_hp_parlio_tx_int_map( + &mut self, + ) -> CORE1_HP_PARLIO_TX_INT_MAP_W { + CORE1_HP_PARLIO_TX_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_parlio_tx_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_parlio_tx_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PARLIO_TX_INT_MAP_SPEC; +impl crate::RegisterSpec for HP_PARLIO_TX_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_parlio_tx_int_map::R`](R) reader structure"] +impl crate::Readable for HP_PARLIO_TX_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_parlio_tx_int_map::W`](W) writer structure"] +impl crate::Writable for HP_PARLIO_TX_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_PARLIO_TX_INT_MAP to value 0"] +impl crate::Resettable for HP_PARLIO_TX_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/hp_pau_int_map.rs b/esp32p4/src/interrupt_core1/hp_pau_int_map.rs new file mode 100644 index 0000000000..74bd3bbd34 --- /dev/null +++ b/esp32p4/src/interrupt_core1/hp_pau_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_PAU_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_PAU_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_HP_PAU_INT_MAP` reader - NA"] +pub type CORE1_HP_PAU_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_HP_PAU_INT_MAP` writer - NA"] +pub type CORE1_HP_PAU_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_hp_pau_int_map(&self) -> CORE1_HP_PAU_INT_MAP_R { + CORE1_HP_PAU_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_PAU_INT_MAP") + .field( + "core1_hp_pau_int_map", + &format_args!("{}", self.core1_hp_pau_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_hp_pau_int_map(&mut self) -> CORE1_HP_PAU_INT_MAP_W { + CORE1_HP_PAU_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_pau_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_pau_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_PAU_INT_MAP_SPEC; +impl crate::RegisterSpec for HP_PAU_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_pau_int_map::R`](R) reader structure"] +impl crate::Readable for HP_PAU_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_pau_int_map::W`](W) writer structure"] +impl crate::Writable for HP_PAU_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_PAU_INT_MAP to value 0"] +impl crate::Resettable for HP_PAU_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/hp_sysreg_int_map.rs b/esp32p4/src/interrupt_core1/hp_sysreg_int_map.rs new file mode 100644 index 0000000000..6c8327209b --- /dev/null +++ b/esp32p4/src/interrupt_core1/hp_sysreg_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_SYSREG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SYSREG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_HP_SYSREG_INT_MAP` reader - NA"] +pub type CORE1_HP_SYSREG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_HP_SYSREG_INT_MAP` writer - NA"] +pub type CORE1_HP_SYSREG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_hp_sysreg_int_map(&self) -> CORE1_HP_SYSREG_INT_MAP_R { + CORE1_HP_SYSREG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SYSREG_INT_MAP") + .field( + "core1_hp_sysreg_int_map", + &format_args!("{}", self.core1_hp_sysreg_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_hp_sysreg_int_map(&mut self) -> CORE1_HP_SYSREG_INT_MAP_W { + CORE1_HP_SYSREG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sysreg_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sysreg_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SYSREG_INT_MAP_SPEC; +impl crate::RegisterSpec for HP_SYSREG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sysreg_int_map::R`](R) reader structure"] +impl crate::Readable for HP_SYSREG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sysreg_int_map::W`](W) writer structure"] +impl crate::Writable for HP_SYSREG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SYSREG_INT_MAP to value 0"] +impl crate::Resettable for HP_SYSREG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/i2c0_int_map.rs b/esp32p4/src/interrupt_core1/i2c0_int_map.rs new file mode 100644 index 0000000000..469edbd3dd --- /dev/null +++ b/esp32p4/src/interrupt_core1/i2c0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I2C0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I2C0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_I2C0_INT_MAP` reader - NA"] +pub type CORE1_I2C0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_I2C0_INT_MAP` writer - NA"] +pub type CORE1_I2C0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_i2c0_int_map(&self) -> CORE1_I2C0_INT_MAP_R { + CORE1_I2C0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0_INT_MAP") + .field( + "core1_i2c0_int_map", + &format_args!("{}", self.core1_i2c0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_i2c0_int_map(&mut self) -> CORE1_I2C0_INT_MAP_W { + CORE1_I2C0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C0_INT_MAP_SPEC; +impl crate::RegisterSpec for I2C0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c0_int_map::R`](R) reader structure"] +impl crate::Readable for I2C0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c0_int_map::W`](W) writer structure"] +impl crate::Writable for I2C0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C0_INT_MAP to value 0"] +impl crate::Resettable for I2C0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/i2c1_int_map.rs b/esp32p4/src/interrupt_core1/i2c1_int_map.rs new file mode 100644 index 0000000000..7eefebe61c --- /dev/null +++ b/esp32p4/src/interrupt_core1/i2c1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I2C1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I2C1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_I2C1_INT_MAP` reader - NA"] +pub type CORE1_I2C1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_I2C1_INT_MAP` writer - NA"] +pub type CORE1_I2C1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_i2c1_int_map(&self) -> CORE1_I2C1_INT_MAP_R { + CORE1_I2C1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1_INT_MAP") + .field( + "core1_i2c1_int_map", + &format_args!("{}", self.core1_i2c1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_i2c1_int_map(&mut self) -> CORE1_I2C1_INT_MAP_W { + CORE1_I2C1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C1_INT_MAP_SPEC; +impl crate::RegisterSpec for I2C1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c1_int_map::R`](R) reader structure"] +impl crate::Readable for I2C1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c1_int_map::W`](W) writer structure"] +impl crate::Writable for I2C1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C1_INT_MAP to value 0"] +impl crate::Resettable for I2C1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/i2s0_int_map.rs b/esp32p4/src/interrupt_core1/i2s0_int_map.rs new file mode 100644 index 0000000000..e24bc8a6f2 --- /dev/null +++ b/esp32p4/src/interrupt_core1/i2s0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I2S0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I2S0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_I2S0_INT_MAP` reader - NA"] +pub type CORE1_I2S0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_I2S0_INT_MAP` writer - NA"] +pub type CORE1_I2S0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_i2s0_int_map(&self) -> CORE1_I2S0_INT_MAP_R { + CORE1_I2S0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S0_INT_MAP") + .field( + "core1_i2s0_int_map", + &format_args!("{}", self.core1_i2s0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_i2s0_int_map(&mut self) -> CORE1_I2S0_INT_MAP_W { + CORE1_I2S0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2S0_INT_MAP_SPEC; +impl crate::RegisterSpec for I2S0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2s0_int_map::R`](R) reader structure"] +impl crate::Readable for I2S0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2s0_int_map::W`](W) writer structure"] +impl crate::Writable for I2S0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2S0_INT_MAP to value 0"] +impl crate::Resettable for I2S0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/i2s1_int_map.rs b/esp32p4/src/interrupt_core1/i2s1_int_map.rs new file mode 100644 index 0000000000..66211a8f0c --- /dev/null +++ b/esp32p4/src/interrupt_core1/i2s1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I2S1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I2S1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_I2S1_INT_MAP` reader - NA"] +pub type CORE1_I2S1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_I2S1_INT_MAP` writer - NA"] +pub type CORE1_I2S1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_i2s1_int_map(&self) -> CORE1_I2S1_INT_MAP_R { + CORE1_I2S1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S1_INT_MAP") + .field( + "core1_i2s1_int_map", + &format_args!("{}", self.core1_i2s1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_i2s1_int_map(&mut self) -> CORE1_I2S1_INT_MAP_W { + CORE1_I2S1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2S1_INT_MAP_SPEC; +impl crate::RegisterSpec for I2S1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2s1_int_map::R`](R) reader structure"] +impl crate::Readable for I2S1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2s1_int_map::W`](W) writer structure"] +impl crate::Writable for I2S1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2S1_INT_MAP to value 0"] +impl crate::Resettable for I2S1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/i2s2_int_map.rs b/esp32p4/src/interrupt_core1/i2s2_int_map.rs new file mode 100644 index 0000000000..6986867e7f --- /dev/null +++ b/esp32p4/src/interrupt_core1/i2s2_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I2S2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I2S2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_I2S2_INT_MAP` reader - NA"] +pub type CORE1_I2S2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_I2S2_INT_MAP` writer - NA"] +pub type CORE1_I2S2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_i2s2_int_map(&self) -> CORE1_I2S2_INT_MAP_R { + CORE1_I2S2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S2_INT_MAP") + .field( + "core1_i2s2_int_map", + &format_args!("{}", self.core1_i2s2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_i2s2_int_map(&mut self) -> CORE1_I2S2_INT_MAP_W { + CORE1_I2S2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2S2_INT_MAP_SPEC; +impl crate::RegisterSpec for I2S2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2s2_int_map::R`](R) reader structure"] +impl crate::Readable for I2S2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2s2_int_map::W`](W) writer structure"] +impl crate::Writable for I2S2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2S2_INT_MAP to value 0"] +impl crate::Resettable for I2S2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/i3c_mst_int_map.rs b/esp32p4/src/interrupt_core1/i3c_mst_int_map.rs new file mode 100644 index 0000000000..24a7462373 --- /dev/null +++ b/esp32p4/src/interrupt_core1/i3c_mst_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I3C_MST_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I3C_MST_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_I3C_MST_INT_MAP` reader - NA"] +pub type CORE1_I3C_MST_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_I3C_MST_INT_MAP` writer - NA"] +pub type CORE1_I3C_MST_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_i3c_mst_int_map(&self) -> CORE1_I3C_MST_INT_MAP_R { + CORE1_I3C_MST_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I3C_MST_INT_MAP") + .field( + "core1_i3c_mst_int_map", + &format_args!("{}", self.core1_i3c_mst_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_i3c_mst_int_map(&mut self) -> CORE1_I3C_MST_INT_MAP_W { + CORE1_I3C_MST_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i3c_mst_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i3c_mst_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I3C_MST_INT_MAP_SPEC; +impl crate::RegisterSpec for I3C_MST_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i3c_mst_int_map::R`](R) reader structure"] +impl crate::Readable for I3C_MST_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i3c_mst_int_map::W`](W) writer structure"] +impl crate::Writable for I3C_MST_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I3C_MST_INT_MAP to value 0"] +impl crate::Resettable for I3C_MST_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/i3c_slv_int_map.rs b/esp32p4/src/interrupt_core1/i3c_slv_int_map.rs new file mode 100644 index 0000000000..678609df28 --- /dev/null +++ b/esp32p4/src/interrupt_core1/i3c_slv_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I3C_SLV_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `I3C_SLV_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_I3C_SLV_INT_MAP` reader - NA"] +pub type CORE1_I3C_SLV_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_I3C_SLV_INT_MAP` writer - NA"] +pub type CORE1_I3C_SLV_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_i3c_slv_int_map(&self) -> CORE1_I3C_SLV_INT_MAP_R { + CORE1_I3C_SLV_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I3C_SLV_INT_MAP") + .field( + "core1_i3c_slv_int_map", + &format_args!("{}", self.core1_i3c_slv_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_i3c_slv_int_map(&mut self) -> CORE1_I3C_SLV_INT_MAP_W { + CORE1_I3C_SLV_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i3c_slv_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i3c_slv_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I3C_SLV_INT_MAP_SPEC; +impl crate::RegisterSpec for I3C_SLV_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i3c_slv_int_map::R`](R) reader structure"] +impl crate::Readable for I3C_SLV_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i3c_slv_int_map::W`](W) writer structure"] +impl crate::Writable for I3C_SLV_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I3C_SLV_INT_MAP to value 0"] +impl crate::Resettable for I3C_SLV_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/interrupt_reg_date.rs b/esp32p4/src/interrupt_core1/interrupt_reg_date.rs new file mode 100644 index 0000000000..15ca741a2c --- /dev/null +++ b/esp32p4/src/interrupt_core1/interrupt_reg_date.rs @@ -0,0 +1,68 @@ +#[doc = "Register `INTERRUPT_REG_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `INTERRUPT_REG_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_INTERRUPT_REG_DATE` reader - NA"] +pub type CORE1_INTERRUPT_REG_DATE_R = crate::FieldReader; +#[doc = "Field `CORE1_INTERRUPT_REG_DATE` writer - NA"] +pub type CORE1_INTERRUPT_REG_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - NA"] + #[inline(always)] + pub fn core1_interrupt_reg_date(&self) -> CORE1_INTERRUPT_REG_DATE_R { + CORE1_INTERRUPT_REG_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTERRUPT_REG_DATE") + .field( + "core1_interrupt_reg_date", + &format_args!("{}", self.core1_interrupt_reg_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_interrupt_reg_date( + &mut self, + ) -> CORE1_INTERRUPT_REG_DATE_W { + CORE1_INTERRUPT_REG_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_reg_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt_reg_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERRUPT_REG_DATE_SPEC; +impl crate::RegisterSpec for INTERRUPT_REG_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interrupt_reg_date::R`](R) reader structure"] +impl crate::Readable for INTERRUPT_REG_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interrupt_reg_date::W`](W) writer structure"] +impl crate::Writable for INTERRUPT_REG_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTERRUPT_REG_DATE to value 0x0200_3020"] +impl crate::Resettable for INTERRUPT_REG_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_3020; +} diff --git a/esp32p4/src/interrupt_core1/intr_status_reg_0.rs b/esp32p4/src/interrupt_core1/intr_status_reg_0.rs new file mode 100644 index 0000000000..77a2536ff5 --- /dev/null +++ b/esp32p4/src/interrupt_core1/intr_status_reg_0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INTR_STATUS_REG_0` reader"] +pub type R = crate::R; +#[doc = "Field `CORE1_INTR_STATUS_0` reader - NA"] +pub type CORE1_INTR_STATUS_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn core1_intr_status_0(&self) -> CORE1_INTR_STATUS_0_R { + CORE1_INTR_STATUS_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_STATUS_REG_0") + .field( + "core1_intr_status_0", + &format_args!("{}", self.core1_intr_status_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_STATUS_REG_0_SPEC; +impl crate::RegisterSpec for INTR_STATUS_REG_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_status_reg_0::R`](R) reader structure"] +impl crate::Readable for INTR_STATUS_REG_0_SPEC {} +#[doc = "`reset()` method sets INTR_STATUS_REG_0 to value 0"] +impl crate::Resettable for INTR_STATUS_REG_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/intr_status_reg_1.rs b/esp32p4/src/interrupt_core1/intr_status_reg_1.rs new file mode 100644 index 0000000000..045afd9c96 --- /dev/null +++ b/esp32p4/src/interrupt_core1/intr_status_reg_1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INTR_STATUS_REG_1` reader"] +pub type R = crate::R; +#[doc = "Field `CORE1_INTR_STATUS_1` reader - NA"] +pub type CORE1_INTR_STATUS_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn core1_intr_status_1(&self) -> CORE1_INTR_STATUS_1_R { + CORE1_INTR_STATUS_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_STATUS_REG_1") + .field( + "core1_intr_status_1", + &format_args!("{}", self.core1_intr_status_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_STATUS_REG_1_SPEC; +impl crate::RegisterSpec for INTR_STATUS_REG_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_status_reg_1::R`](R) reader structure"] +impl crate::Readable for INTR_STATUS_REG_1_SPEC {} +#[doc = "`reset()` method sets INTR_STATUS_REG_1 to value 0"] +impl crate::Resettable for INTR_STATUS_REG_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/intr_status_reg_2.rs b/esp32p4/src/interrupt_core1/intr_status_reg_2.rs new file mode 100644 index 0000000000..fae5c5cf80 --- /dev/null +++ b/esp32p4/src/interrupt_core1/intr_status_reg_2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INTR_STATUS_REG_2` reader"] +pub type R = crate::R; +#[doc = "Field `CORE1_INTR_STATUS_2` reader - NA"] +pub type CORE1_INTR_STATUS_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn core1_intr_status_2(&self) -> CORE1_INTR_STATUS_2_R { + CORE1_INTR_STATUS_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_STATUS_REG_2") + .field( + "core1_intr_status_2", + &format_args!("{}", self.core1_intr_status_2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_STATUS_REG_2_SPEC; +impl crate::RegisterSpec for INTR_STATUS_REG_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_status_reg_2::R`](R) reader structure"] +impl crate::Readable for INTR_STATUS_REG_2_SPEC {} +#[doc = "`reset()` method sets INTR_STATUS_REG_2 to value 0"] +impl crate::Resettable for INTR_STATUS_REG_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/intr_status_reg_3.rs b/esp32p4/src/interrupt_core1/intr_status_reg_3.rs new file mode 100644 index 0000000000..313ce41012 --- /dev/null +++ b/esp32p4/src/interrupt_core1/intr_status_reg_3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INTR_STATUS_REG_3` reader"] +pub type R = crate::R; +#[doc = "Field `CORE1_INTR_STATUS_3` reader - NA"] +pub type CORE1_INTR_STATUS_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn core1_intr_status_3(&self) -> CORE1_INTR_STATUS_3_R { + CORE1_INTR_STATUS_3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_STATUS_REG_3") + .field( + "core1_intr_status_3", + &format_args!("{}", self.core1_intr_status_3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_STATUS_REG_3_SPEC; +impl crate::RegisterSpec for INTR_STATUS_REG_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_status_reg_3::R`](R) reader structure"] +impl crate::Readable for INTR_STATUS_REG_3_SPEC {} +#[doc = "`reset()` method sets INTR_STATUS_REG_3 to value 0"] +impl crate::Resettable for INTR_STATUS_REG_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/isp_int_map.rs b/esp32p4/src/interrupt_core1/isp_int_map.rs new file mode 100644 index 0000000000..f7fb6ee8f8 --- /dev/null +++ b/esp32p4/src/interrupt_core1/isp_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ISP_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `ISP_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_ISP_INT_MAP` reader - NA"] +pub type CORE1_ISP_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_ISP_INT_MAP` writer - NA"] +pub type CORE1_ISP_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_isp_int_map(&self) -> CORE1_ISP_INT_MAP_R { + CORE1_ISP_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ISP_INT_MAP") + .field( + "core1_isp_int_map", + &format_args!("{}", self.core1_isp_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_isp_int_map(&mut self) -> CORE1_ISP_INT_MAP_W { + CORE1_ISP_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isp_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`isp_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ISP_INT_MAP_SPEC; +impl crate::RegisterSpec for ISP_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`isp_int_map::R`](R) reader structure"] +impl crate::Readable for ISP_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`isp_int_map::W`](W) writer structure"] +impl crate::Writable for ISP_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ISP_INT_MAP to value 0"] +impl crate::Resettable for ISP_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/jpeg_int_map.rs b/esp32p4/src/interrupt_core1/jpeg_int_map.rs new file mode 100644 index 0000000000..e29fa05003 --- /dev/null +++ b/esp32p4/src/interrupt_core1/jpeg_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `JPEG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `JPEG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_JPEG_INT_MAP` reader - NA"] +pub type CORE1_JPEG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_JPEG_INT_MAP` writer - NA"] +pub type CORE1_JPEG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_jpeg_int_map(&self) -> CORE1_JPEG_INT_MAP_R { + CORE1_JPEG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("JPEG_INT_MAP") + .field( + "core1_jpeg_int_map", + &format_args!("{}", self.core1_jpeg_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_jpeg_int_map(&mut self) -> CORE1_JPEG_INT_MAP_W { + CORE1_JPEG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`jpeg_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`jpeg_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct JPEG_INT_MAP_SPEC; +impl crate::RegisterSpec for JPEG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`jpeg_int_map::R`](R) reader structure"] +impl crate::Readable for JPEG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`jpeg_int_map::W`](W) writer structure"] +impl crate::Writable for JPEG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets JPEG_INT_MAP to value 0"] +impl crate::Resettable for JPEG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/km_int_map.rs b/esp32p4/src/interrupt_core1/km_int_map.rs new file mode 100644 index 0000000000..3bccb8c9f9 --- /dev/null +++ b/esp32p4/src/interrupt_core1/km_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `KM_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `KM_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_KM_INT_MAP` reader - NA"] +pub type CORE1_KM_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_KM_INT_MAP` writer - NA"] +pub type CORE1_KM_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_km_int_map(&self) -> CORE1_KM_INT_MAP_R { + CORE1_KM_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("KM_INT_MAP") + .field( + "core1_km_int_map", + &format_args!("{}", self.core1_km_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_km_int_map(&mut self) -> CORE1_KM_INT_MAP_W { + CORE1_KM_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`km_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`km_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KM_INT_MAP_SPEC; +impl crate::RegisterSpec for KM_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`km_int_map::R`](R) reader structure"] +impl crate::Readable for KM_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`km_int_map::W`](W) writer structure"] +impl crate::Writable for KM_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets KM_INT_MAP to value 0"] +impl crate::Resettable for KM_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lcd_cam_int_map.rs b/esp32p4/src/interrupt_core1/lcd_cam_int_map.rs new file mode 100644 index 0000000000..e333199824 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lcd_cam_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LCD_CAM_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_CAM_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LCD_CAM_INT_MAP` reader - NA"] +pub type CORE1_LCD_CAM_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LCD_CAM_INT_MAP` writer - NA"] +pub type CORE1_LCD_CAM_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lcd_cam_int_map(&self) -> CORE1_LCD_CAM_INT_MAP_R { + CORE1_LCD_CAM_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_CAM_INT_MAP") + .field( + "core1_lcd_cam_int_map", + &format_args!("{}", self.core1_lcd_cam_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lcd_cam_int_map(&mut self) -> CORE1_LCD_CAM_INT_MAP_W { + CORE1_LCD_CAM_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_cam_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_cam_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_CAM_INT_MAP_SPEC; +impl crate::RegisterSpec for LCD_CAM_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_cam_int_map::R`](R) reader structure"] +impl crate::Readable for LCD_CAM_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_cam_int_map::W`](W) writer structure"] +impl crate::Writable for LCD_CAM_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_CAM_INT_MAP to value 0"] +impl crate::Resettable for LCD_CAM_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/ledc_int_map.rs b/esp32p4/src/interrupt_core1/ledc_int_map.rs new file mode 100644 index 0000000000..8eea0ffc84 --- /dev/null +++ b/esp32p4/src/interrupt_core1/ledc_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LEDC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LEDC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LEDC_INT_MAP` reader - NA"] +pub type CORE1_LEDC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LEDC_INT_MAP` writer - NA"] +pub type CORE1_LEDC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_ledc_int_map(&self) -> CORE1_LEDC_INT_MAP_R { + CORE1_LEDC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LEDC_INT_MAP") + .field( + "core1_ledc_int_map", + &format_args!("{}", self.core1_ledc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_ledc_int_map(&mut self) -> CORE1_LEDC_INT_MAP_W { + CORE1_LEDC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ledc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ledc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LEDC_INT_MAP_SPEC; +impl crate::RegisterSpec for LEDC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ledc_int_map::R`](R) reader structure"] +impl crate::Readable for LEDC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ledc_int_map::W`](W) writer structure"] +impl crate::Writable for LEDC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LEDC_INT_MAP to value 0"] +impl crate::Resettable for LEDC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_adc_int_map.rs b/esp32p4/src/interrupt_core1/lp_adc_int_map.rs new file mode 100644 index 0000000000..fbc4bab6ec --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_adc_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ADC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ADC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_ADC_INT_MAP` reader - NA"] +pub type CORE1_LP_ADC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_ADC_INT_MAP` writer - NA"] +pub type CORE1_LP_ADC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_adc_int_map(&self) -> CORE1_LP_ADC_INT_MAP_R { + CORE1_LP_ADC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ADC_INT_MAP") + .field( + "core1_lp_adc_int_map", + &format_args!("{}", self.core1_lp_adc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_adc_int_map(&mut self) -> CORE1_LP_ADC_INT_MAP_W { + CORE1_LP_ADC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_adc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_adc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ADC_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_ADC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_adc_int_map::R`](R) reader structure"] +impl crate::Readable for LP_ADC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_adc_int_map::W`](W) writer structure"] +impl crate::Writable for LP_ADC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ADC_INT_MAP to value 0"] +impl crate::Resettable for LP_ADC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_anaperi_int_map.rs b/esp32p4/src/interrupt_core1/lp_anaperi_int_map.rs new file mode 100644 index 0000000000..e87921612c --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_anaperi_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANAPERI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANAPERI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_ANAPERI_INT_MAP` reader - NA"] +pub type CORE1_LP_ANAPERI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_ANAPERI_INT_MAP` writer - NA"] +pub type CORE1_LP_ANAPERI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_anaperi_int_map(&self) -> CORE1_LP_ANAPERI_INT_MAP_R { + CORE1_LP_ANAPERI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANAPERI_INT_MAP") + .field( + "core1_lp_anaperi_int_map", + &format_args!("{}", self.core1_lp_anaperi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_anaperi_int_map( + &mut self, + ) -> CORE1_LP_ANAPERI_INT_MAP_W { + CORE1_LP_ANAPERI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_anaperi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_anaperi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANAPERI_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_ANAPERI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_anaperi_int_map::R`](R) reader structure"] +impl crate::Readable for LP_ANAPERI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_anaperi_int_map::W`](W) writer structure"] +impl crate::Writable for LP_ANAPERI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANAPERI_INT_MAP to value 0"] +impl crate::Resettable for LP_ANAPERI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_efuse_int_map.rs b/esp32p4/src/interrupt_core1/lp_efuse_int_map.rs new file mode 100644 index 0000000000..243fa94fa5 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_efuse_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_EFUSE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_EFUSE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_EFUSE_INT_MAP` reader - NA"] +pub type CORE1_LP_EFUSE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_EFUSE_INT_MAP` writer - NA"] +pub type CORE1_LP_EFUSE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_efuse_int_map(&self) -> CORE1_LP_EFUSE_INT_MAP_R { + CORE1_LP_EFUSE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_EFUSE_INT_MAP") + .field( + "core1_lp_efuse_int_map", + &format_args!("{}", self.core1_lp_efuse_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_efuse_int_map(&mut self) -> CORE1_LP_EFUSE_INT_MAP_W { + CORE1_LP_EFUSE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_efuse_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_efuse_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_EFUSE_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_EFUSE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_efuse_int_map::R`](R) reader structure"] +impl crate::Readable for LP_EFUSE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_efuse_int_map::W`](W) writer structure"] +impl crate::Writable for LP_EFUSE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_EFUSE_INT_MAP to value 0"] +impl crate::Resettable for LP_EFUSE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_gpio_int_map.rs b/esp32p4/src/interrupt_core1/lp_gpio_int_map.rs new file mode 100644 index 0000000000..0f50e0d2b1 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_gpio_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_GPIO_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_GPIO_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_GPIO_INT_MAP` reader - NA"] +pub type CORE1_LP_GPIO_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_GPIO_INT_MAP` writer - NA"] +pub type CORE1_LP_GPIO_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_gpio_int_map(&self) -> CORE1_LP_GPIO_INT_MAP_R { + CORE1_LP_GPIO_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_GPIO_INT_MAP") + .field( + "core1_lp_gpio_int_map", + &format_args!("{}", self.core1_lp_gpio_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_gpio_int_map(&mut self) -> CORE1_LP_GPIO_INT_MAP_W { + CORE1_LP_GPIO_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_gpio_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_gpio_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_GPIO_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_GPIO_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_gpio_int_map::R`](R) reader structure"] +impl crate::Readable for LP_GPIO_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_gpio_int_map::W`](W) writer structure"] +impl crate::Writable for LP_GPIO_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_GPIO_INT_MAP to value 0"] +impl crate::Resettable for LP_GPIO_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_huk_int_map.rs b/esp32p4/src/interrupt_core1/lp_huk_int_map.rs new file mode 100644 index 0000000000..9f36c2c87b --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_huk_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_HUK_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_HUK_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_HUK_INT_MAP` reader - NA"] +pub type CORE1_LP_HUK_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_HUK_INT_MAP` writer - NA"] +pub type CORE1_LP_HUK_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_huk_int_map(&self) -> CORE1_LP_HUK_INT_MAP_R { + CORE1_LP_HUK_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_HUK_INT_MAP") + .field( + "core1_lp_huk_int_map", + &format_args!("{}", self.core1_lp_huk_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_huk_int_map(&mut self) -> CORE1_LP_HUK_INT_MAP_W { + CORE1_LP_HUK_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_huk_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_huk_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_HUK_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_HUK_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_huk_int_map::R`](R) reader structure"] +impl crate::Readable for LP_HUK_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_huk_int_map::W`](W) writer structure"] +impl crate::Writable for LP_HUK_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_HUK_INT_MAP to value 0"] +impl crate::Resettable for LP_HUK_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_i2c_int_map.rs b/esp32p4/src/interrupt_core1/lp_i2c_int_map.rs new file mode 100644 index 0000000000..b6c9124351 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_i2c_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_I2C_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_I2C_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_I2C_INT_MAP` reader - NA"] +pub type CORE1_LP_I2C_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_I2C_INT_MAP` writer - NA"] +pub type CORE1_LP_I2C_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_i2c_int_map(&self) -> CORE1_LP_I2C_INT_MAP_R { + CORE1_LP_I2C_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2C_INT_MAP") + .field( + "core1_lp_i2c_int_map", + &format_args!("{}", self.core1_lp_i2c_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_i2c_int_map(&mut self) -> CORE1_LP_I2C_INT_MAP_W { + CORE1_LP_I2C_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2c_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2c_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_I2C_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_I2C_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_i2c_int_map::R`](R) reader structure"] +impl crate::Readable for LP_I2C_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_i2c_int_map::W`](W) writer structure"] +impl crate::Writable for LP_I2C_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_I2C_INT_MAP to value 0"] +impl crate::Resettable for LP_I2C_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_i2s_int_map.rs b/esp32p4/src/interrupt_core1/lp_i2s_int_map.rs new file mode 100644 index 0000000000..0e4c72668c --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_i2s_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_I2S_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_I2S_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_I2S_INT_MAP` reader - NA"] +pub type CORE1_LP_I2S_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_I2S_INT_MAP` writer - NA"] +pub type CORE1_LP_I2S_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_i2s_int_map(&self) -> CORE1_LP_I2S_INT_MAP_R { + CORE1_LP_I2S_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2S_INT_MAP") + .field( + "core1_lp_i2s_int_map", + &format_args!("{}", self.core1_lp_i2s_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_i2s_int_map(&mut self) -> CORE1_LP_I2S_INT_MAP_W { + CORE1_LP_I2S_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_I2S_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_I2S_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_i2s_int_map::R`](R) reader structure"] +impl crate::Readable for LP_I2S_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_i2s_int_map::W`](W) writer structure"] +impl crate::Writable for LP_I2S_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_I2S_INT_MAP to value 0"] +impl crate::Resettable for LP_I2S_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_rtc_int_map.rs b/esp32p4/src/interrupt_core1/lp_rtc_int_map.rs new file mode 100644 index 0000000000..6553f7e25b --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_rtc_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_RTC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_RTC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_RTC_INT_MAP` reader - NA"] +pub type CORE1_LP_RTC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_RTC_INT_MAP` writer - NA"] +pub type CORE1_LP_RTC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_rtc_int_map(&self) -> CORE1_LP_RTC_INT_MAP_R { + CORE1_LP_RTC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_RTC_INT_MAP") + .field( + "core1_lp_rtc_int_map", + &format_args!("{}", self.core1_lp_rtc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_rtc_int_map(&mut self) -> CORE1_LP_RTC_INT_MAP_W { + CORE1_LP_RTC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_rtc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_rtc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_RTC_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_RTC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_rtc_int_map::R`](R) reader structure"] +impl crate::Readable for LP_RTC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_rtc_int_map::W`](W) writer structure"] +impl crate::Writable for LP_RTC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_RTC_INT_MAP to value 0"] +impl crate::Resettable for LP_RTC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_spi_int_map.rs b/esp32p4/src/interrupt_core1/lp_spi_int_map.rs new file mode 100644 index 0000000000..494e7d4f77 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_spi_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_SPI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SPI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_SPI_INT_MAP` reader - NA"] +pub type CORE1_LP_SPI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_SPI_INT_MAP` writer - NA"] +pub type CORE1_LP_SPI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_spi_int_map(&self) -> CORE1_LP_SPI_INT_MAP_R { + CORE1_LP_SPI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SPI_INT_MAP") + .field( + "core1_lp_spi_int_map", + &format_args!("{}", self.core1_lp_spi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_spi_int_map(&mut self) -> CORE1_LP_SPI_INT_MAP_W { + CORE1_LP_SPI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_spi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_spi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SPI_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_SPI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_spi_int_map::R`](R) reader structure"] +impl crate::Readable for LP_SPI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_spi_int_map::W`](W) writer structure"] +impl crate::Writable for LP_SPI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SPI_INT_MAP to value 0"] +impl crate::Resettable for LP_SPI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_sw_int_map.rs b/esp32p4/src/interrupt_core1/lp_sw_int_map.rs new file mode 100644 index 0000000000..c4b3e23edb --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_sw_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_SW_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SW_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_SW_INT_MAP` reader - NA"] +pub type CORE1_LP_SW_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_SW_INT_MAP` writer - NA"] +pub type CORE1_LP_SW_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_sw_int_map(&self) -> CORE1_LP_SW_INT_MAP_R { + CORE1_LP_SW_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SW_INT_MAP") + .field( + "core1_lp_sw_int_map", + &format_args!("{}", self.core1_lp_sw_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_sw_int_map(&mut self) -> CORE1_LP_SW_INT_MAP_W { + CORE1_LP_SW_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sw_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sw_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SW_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_SW_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_sw_int_map::R`](R) reader structure"] +impl crate::Readable for LP_SW_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_sw_int_map::W`](W) writer structure"] +impl crate::Writable for LP_SW_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SW_INT_MAP to value 0"] +impl crate::Resettable for LP_SW_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_sysreg_int_map.rs b/esp32p4/src/interrupt_core1/lp_sysreg_int_map.rs new file mode 100644 index 0000000000..92eeac65e9 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_sysreg_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_SYSREG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SYSREG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_SYSREG_INT_MAP` reader - NA"] +pub type CORE1_LP_SYSREG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_SYSREG_INT_MAP` writer - NA"] +pub type CORE1_LP_SYSREG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_sysreg_int_map(&self) -> CORE1_LP_SYSREG_INT_MAP_R { + CORE1_LP_SYSREG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SYSREG_INT_MAP") + .field( + "core1_lp_sysreg_int_map", + &format_args!("{}", self.core1_lp_sysreg_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_sysreg_int_map(&mut self) -> CORE1_LP_SYSREG_INT_MAP_W { + CORE1_LP_SYSREG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sysreg_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sysreg_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SYSREG_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_SYSREG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_sysreg_int_map::R`](R) reader structure"] +impl crate::Readable for LP_SYSREG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_sysreg_int_map::W`](W) writer structure"] +impl crate::Writable for LP_SYSREG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SYSREG_INT_MAP to value 0"] +impl crate::Resettable for LP_SYSREG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_timer_reg_0_int_map.rs b/esp32p4/src/interrupt_core1/lp_timer_reg_0_int_map.rs new file mode 100644 index 0000000000..7f8b1461e3 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_timer_reg_0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_TIMER_REG_0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TIMER_REG_0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_TIMER_REG_0_INT_MAP` reader - NA"] +pub type CORE1_LP_TIMER_REG_0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_TIMER_REG_0_INT_MAP` writer - NA"] +pub type CORE1_LP_TIMER_REG_0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_timer_reg_0_int_map(&self) -> CORE1_LP_TIMER_REG_0_INT_MAP_R { + CORE1_LP_TIMER_REG_0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TIMER_REG_0_INT_MAP") + .field( + "core1_lp_timer_reg_0_int_map", + &format_args!("{}", self.core1_lp_timer_reg_0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_timer_reg_0_int_map( + &mut self, + ) -> CORE1_LP_TIMER_REG_0_INT_MAP_W { + CORE1_LP_TIMER_REG_0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timer_reg_0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timer_reg_0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TIMER_REG_0_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_TIMER_REG_0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_timer_reg_0_int_map::R`](R) reader structure"] +impl crate::Readable for LP_TIMER_REG_0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_timer_reg_0_int_map::W`](W) writer structure"] +impl crate::Writable for LP_TIMER_REG_0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TIMER_REG_0_INT_MAP to value 0"] +impl crate::Resettable for LP_TIMER_REG_0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_timer_reg_1_int_map.rs b/esp32p4/src/interrupt_core1/lp_timer_reg_1_int_map.rs new file mode 100644 index 0000000000..33b53e3a25 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_timer_reg_1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_TIMER_REG_1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TIMER_REG_1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_TIMER_REG_1_INT_MAP` reader - NA"] +pub type CORE1_LP_TIMER_REG_1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_TIMER_REG_1_INT_MAP` writer - NA"] +pub type CORE1_LP_TIMER_REG_1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_timer_reg_1_int_map(&self) -> CORE1_LP_TIMER_REG_1_INT_MAP_R { + CORE1_LP_TIMER_REG_1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TIMER_REG_1_INT_MAP") + .field( + "core1_lp_timer_reg_1_int_map", + &format_args!("{}", self.core1_lp_timer_reg_1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_timer_reg_1_int_map( + &mut self, + ) -> CORE1_LP_TIMER_REG_1_INT_MAP_W { + CORE1_LP_TIMER_REG_1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_timer_reg_1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_timer_reg_1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TIMER_REG_1_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_TIMER_REG_1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_timer_reg_1_int_map::R`](R) reader structure"] +impl crate::Readable for LP_TIMER_REG_1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_timer_reg_1_int_map::W`](W) writer structure"] +impl crate::Writable for LP_TIMER_REG_1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TIMER_REG_1_INT_MAP to value 0"] +impl crate::Resettable for LP_TIMER_REG_1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_touch_int_map.rs b/esp32p4/src/interrupt_core1/lp_touch_int_map.rs new file mode 100644 index 0000000000..349046deb7 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_touch_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_TOUCH_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TOUCH_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_TOUCH_INT_MAP` reader - NA"] +pub type CORE1_LP_TOUCH_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_TOUCH_INT_MAP` writer - NA"] +pub type CORE1_LP_TOUCH_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_touch_int_map(&self) -> CORE1_LP_TOUCH_INT_MAP_R { + CORE1_LP_TOUCH_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TOUCH_INT_MAP") + .field( + "core1_lp_touch_int_map", + &format_args!("{}", self.core1_lp_touch_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_touch_int_map(&mut self) -> CORE1_LP_TOUCH_INT_MAP_W { + CORE1_LP_TOUCH_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_touch_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_touch_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TOUCH_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_TOUCH_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_touch_int_map::R`](R) reader structure"] +impl crate::Readable for LP_TOUCH_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_touch_int_map::W`](W) writer structure"] +impl crate::Writable for LP_TOUCH_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TOUCH_INT_MAP to value 0"] +impl crate::Resettable for LP_TOUCH_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_tsens_int_map.rs b/esp32p4/src/interrupt_core1/lp_tsens_int_map.rs new file mode 100644 index 0000000000..e4abd3fdb7 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_tsens_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_TSENS_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TSENS_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_TSENS_INT_MAP` reader - NA"] +pub type CORE1_LP_TSENS_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_TSENS_INT_MAP` writer - NA"] +pub type CORE1_LP_TSENS_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_tsens_int_map(&self) -> CORE1_LP_TSENS_INT_MAP_R { + CORE1_LP_TSENS_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TSENS_INT_MAP") + .field( + "core1_lp_tsens_int_map", + &format_args!("{}", self.core1_lp_tsens_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_tsens_int_map(&mut self) -> CORE1_LP_TSENS_INT_MAP_W { + CORE1_LP_TSENS_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tsens_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tsens_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TSENS_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_TSENS_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_tsens_int_map::R`](R) reader structure"] +impl crate::Readable for LP_TSENS_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_tsens_int_map::W`](W) writer structure"] +impl crate::Writable for LP_TSENS_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TSENS_INT_MAP to value 0"] +impl crate::Resettable for LP_TSENS_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_uart_int_map.rs b/esp32p4/src/interrupt_core1/lp_uart_int_map.rs new file mode 100644 index 0000000000..cf782910b5 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_uart_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_UART_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_UART_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_UART_INT_MAP` reader - NA"] +pub type CORE1_LP_UART_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_UART_INT_MAP` writer - NA"] +pub type CORE1_LP_UART_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_uart_int_map(&self) -> CORE1_LP_UART_INT_MAP_R { + CORE1_LP_UART_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_UART_INT_MAP") + .field( + "core1_lp_uart_int_map", + &format_args!("{}", self.core1_lp_uart_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_uart_int_map(&mut self) -> CORE1_LP_UART_INT_MAP_W { + CORE1_LP_UART_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_uart_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_uart_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_UART_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_UART_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_uart_int_map::R`](R) reader structure"] +impl crate::Readable for LP_UART_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_uart_int_map::W`](W) writer structure"] +impl crate::Writable for LP_UART_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_UART_INT_MAP to value 0"] +impl crate::Resettable for LP_UART_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lp_wdt_int_map.rs b/esp32p4/src/interrupt_core1/lp_wdt_int_map.rs new file mode 100644 index 0000000000..287b13c66b --- /dev/null +++ b/esp32p4/src/interrupt_core1/lp_wdt_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_WDT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_WDT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LP_WDT_INT_MAP` reader - NA"] +pub type CORE1_LP_WDT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LP_WDT_INT_MAP` writer - NA"] +pub type CORE1_LP_WDT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lp_wdt_int_map(&self) -> CORE1_LP_WDT_INT_MAP_R { + CORE1_LP_WDT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_WDT_INT_MAP") + .field( + "core1_lp_wdt_int_map", + &format_args!("{}", self.core1_lp_wdt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lp_wdt_int_map(&mut self) -> CORE1_LP_WDT_INT_MAP_W { + CORE1_LP_WDT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_wdt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_wdt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_WDT_INT_MAP_SPEC; +impl crate::RegisterSpec for LP_WDT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_wdt_int_map::R`](R) reader structure"] +impl crate::Readable for LP_WDT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_wdt_int_map::W`](W) writer structure"] +impl crate::Writable for LP_WDT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_WDT_INT_MAP to value 0"] +impl crate::Resettable for LP_WDT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/lpi_int_map.rs b/esp32p4/src/interrupt_core1/lpi_int_map.rs new file mode 100644 index 0000000000..36e3349a94 --- /dev/null +++ b/esp32p4/src/interrupt_core1/lpi_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LPI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `LPI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_LPI_INT_MAP` reader - NA"] +pub type CORE1_LPI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_LPI_INT_MAP` writer - NA"] +pub type CORE1_LPI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_lpi_int_map(&self) -> CORE1_LPI_INT_MAP_R { + CORE1_LPI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LPI_INT_MAP") + .field( + "core1_lpi_int_map", + &format_args!("{}", self.core1_lpi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_lpi_int_map(&mut self) -> CORE1_LPI_INT_MAP_W { + CORE1_LPI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LPI_INT_MAP_SPEC; +impl crate::RegisterSpec for LPI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpi_int_map::R`](R) reader structure"] +impl crate::Readable for LPI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lpi_int_map::W`](W) writer structure"] +impl crate::Writable for LPI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LPI_INT_MAP to value 0"] +impl crate::Resettable for LPI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/mb_hp_int_map.rs b/esp32p4/src/interrupt_core1/mb_hp_int_map.rs new file mode 100644 index 0000000000..10660f4387 --- /dev/null +++ b/esp32p4/src/interrupt_core1/mb_hp_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `MB_HP_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `MB_HP_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_MB_HP_INT_MAP` reader - NA"] +pub type CORE1_MB_HP_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_MB_HP_INT_MAP` writer - NA"] +pub type CORE1_MB_HP_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_mb_hp_int_map(&self) -> CORE1_MB_HP_INT_MAP_R { + CORE1_MB_HP_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MB_HP_INT_MAP") + .field( + "core1_mb_hp_int_map", + &format_args!("{}", self.core1_mb_hp_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_mb_hp_int_map(&mut self) -> CORE1_MB_HP_INT_MAP_W { + CORE1_MB_HP_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mb_hp_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mb_hp_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MB_HP_INT_MAP_SPEC; +impl crate::RegisterSpec for MB_HP_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_hp_int_map::R`](R) reader structure"] +impl crate::Readable for MB_HP_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mb_hp_int_map::W`](W) writer structure"] +impl crate::Writable for MB_HP_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MB_HP_INT_MAP to value 0"] +impl crate::Resettable for MB_HP_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/mb_lp_int_map.rs b/esp32p4/src/interrupt_core1/mb_lp_int_map.rs new file mode 100644 index 0000000000..974cbb8137 --- /dev/null +++ b/esp32p4/src/interrupt_core1/mb_lp_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `MB_LP_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `MB_LP_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_MB_LP_INT_MAP` reader - NA"] +pub type CORE1_MB_LP_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_MB_LP_INT_MAP` writer - NA"] +pub type CORE1_MB_LP_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_mb_lp_int_map(&self) -> CORE1_MB_LP_INT_MAP_R { + CORE1_MB_LP_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MB_LP_INT_MAP") + .field( + "core1_mb_lp_int_map", + &format_args!("{}", self.core1_mb_lp_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_mb_lp_int_map(&mut self) -> CORE1_MB_LP_INT_MAP_W { + CORE1_MB_LP_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mb_lp_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mb_lp_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MB_LP_INT_MAP_SPEC; +impl crate::RegisterSpec for MB_LP_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mb_lp_int_map::R`](R) reader structure"] +impl crate::Readable for MB_LP_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mb_lp_int_map::W`](W) writer structure"] +impl crate::Writable for MB_LP_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MB_LP_INT_MAP to value 0"] +impl crate::Resettable for MB_LP_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/pcnt_int_map.rs b/esp32p4/src/interrupt_core1/pcnt_int_map.rs new file mode 100644 index 0000000000..7f255cbaf4 --- /dev/null +++ b/esp32p4/src/interrupt_core1/pcnt_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PCNT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PCNT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_PCNT_INT_MAP` reader - NA"] +pub type CORE1_PCNT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_PCNT_INT_MAP` writer - NA"] +pub type CORE1_PCNT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_pcnt_int_map(&self) -> CORE1_PCNT_INT_MAP_R { + CORE1_PCNT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PCNT_INT_MAP") + .field( + "core1_pcnt_int_map", + &format_args!("{}", self.core1_pcnt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_pcnt_int_map(&mut self) -> CORE1_PCNT_INT_MAP_W { + CORE1_PCNT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcnt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcnt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PCNT_INT_MAP_SPEC; +impl crate::RegisterSpec for PCNT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcnt_int_map::R`](R) reader structure"] +impl crate::Readable for PCNT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pcnt_int_map::W`](W) writer structure"] +impl crate::Writable for PCNT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PCNT_INT_MAP to value 0"] +impl crate::Resettable for PCNT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/pmt_int_map.rs b/esp32p4/src/interrupt_core1/pmt_int_map.rs new file mode 100644 index 0000000000..c1e1cbc3df --- /dev/null +++ b/esp32p4/src/interrupt_core1/pmt_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PMT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_PMT_INT_MAP` reader - NA"] +pub type CORE1_PMT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_PMT_INT_MAP` writer - NA"] +pub type CORE1_PMT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_pmt_int_map(&self) -> CORE1_PMT_INT_MAP_R { + CORE1_PMT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMT_INT_MAP") + .field( + "core1_pmt_int_map", + &format_args!("{}", self.core1_pmt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_pmt_int_map(&mut self) -> CORE1_PMT_INT_MAP_W { + CORE1_PMT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMT_INT_MAP_SPEC; +impl crate::RegisterSpec for PMT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmt_int_map::R`](R) reader structure"] +impl crate::Readable for PMT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmt_int_map::W`](W) writer structure"] +impl crate::Writable for PMT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMT_INT_MAP to value 0"] +impl crate::Resettable for PMT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/pmu_reg_0_int_map.rs b/esp32p4/src/interrupt_core1/pmu_reg_0_int_map.rs new file mode 100644 index 0000000000..ec20a16d32 --- /dev/null +++ b/esp32p4/src/interrupt_core1/pmu_reg_0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMU_REG_0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PMU_REG_0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_PMU_REG_0_INT_MAP` reader - NA"] +pub type CORE1_PMU_REG_0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_PMU_REG_0_INT_MAP` writer - NA"] +pub type CORE1_PMU_REG_0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_pmu_reg_0_int_map(&self) -> CORE1_PMU_REG_0_INT_MAP_R { + CORE1_PMU_REG_0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMU_REG_0_INT_MAP") + .field( + "core1_pmu_reg_0_int_map", + &format_args!("{}", self.core1_pmu_reg_0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_pmu_reg_0_int_map(&mut self) -> CORE1_PMU_REG_0_INT_MAP_W { + CORE1_PMU_REG_0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_reg_0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_reg_0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMU_REG_0_INT_MAP_SPEC; +impl crate::RegisterSpec for PMU_REG_0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmu_reg_0_int_map::R`](R) reader structure"] +impl crate::Readable for PMU_REG_0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmu_reg_0_int_map::W`](W) writer structure"] +impl crate::Writable for PMU_REG_0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMU_REG_0_INT_MAP to value 0"] +impl crate::Resettable for PMU_REG_0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/pmu_reg_1_int_map.rs b/esp32p4/src/interrupt_core1/pmu_reg_1_int_map.rs new file mode 100644 index 0000000000..21351c845a --- /dev/null +++ b/esp32p4/src/interrupt_core1/pmu_reg_1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMU_REG_1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PMU_REG_1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_PMU_REG_1_INT_MAP` reader - NA"] +pub type CORE1_PMU_REG_1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_PMU_REG_1_INT_MAP` writer - NA"] +pub type CORE1_PMU_REG_1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_pmu_reg_1_int_map(&self) -> CORE1_PMU_REG_1_INT_MAP_R { + CORE1_PMU_REG_1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMU_REG_1_INT_MAP") + .field( + "core1_pmu_reg_1_int_map", + &format_args!("{}", self.core1_pmu_reg_1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_pmu_reg_1_int_map(&mut self) -> CORE1_PMU_REG_1_INT_MAP_W { + CORE1_PMU_REG_1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_reg_1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_reg_1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMU_REG_1_INT_MAP_SPEC; +impl crate::RegisterSpec for PMU_REG_1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmu_reg_1_int_map::R`](R) reader structure"] +impl crate::Readable for PMU_REG_1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmu_reg_1_int_map::W`](W) writer structure"] +impl crate::Writable for PMU_REG_1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMU_REG_1_INT_MAP to value 0"] +impl crate::Resettable for PMU_REG_1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/ppa_int_map.rs b/esp32p4/src/interrupt_core1/ppa_int_map.rs new file mode 100644 index 0000000000..86363cf79d --- /dev/null +++ b/esp32p4/src/interrupt_core1/ppa_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PPA_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PPA_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_PPA_INT_MAP` reader - NA"] +pub type CORE1_PPA_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_PPA_INT_MAP` writer - NA"] +pub type CORE1_PPA_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_ppa_int_map(&self) -> CORE1_PPA_INT_MAP_R { + CORE1_PPA_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PPA_INT_MAP") + .field( + "core1_ppa_int_map", + &format_args!("{}", self.core1_ppa_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_ppa_int_map(&mut self) -> CORE1_PPA_INT_MAP_W { + CORE1_PPA_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppa_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppa_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PPA_INT_MAP_SPEC; +impl crate::RegisterSpec for PPA_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ppa_int_map::R`](R) reader structure"] +impl crate::Readable for PPA_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ppa_int_map::W`](W) writer structure"] +impl crate::Writable for PPA_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PPA_INT_MAP to value 0"] +impl crate::Resettable for PPA_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/psram_mspi_int_map.rs b/esp32p4/src/interrupt_core1/psram_mspi_int_map.rs new file mode 100644 index 0000000000..2ccf2c218c --- /dev/null +++ b/esp32p4/src/interrupt_core1/psram_mspi_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `PSRAM_MSPI_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PSRAM_MSPI_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_PSRAM_MSPI_INT_MAP` reader - NA"] +pub type CORE1_PSRAM_MSPI_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_PSRAM_MSPI_INT_MAP` writer - NA"] +pub type CORE1_PSRAM_MSPI_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_psram_mspi_int_map(&self) -> CORE1_PSRAM_MSPI_INT_MAP_R { + CORE1_PSRAM_MSPI_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PSRAM_MSPI_INT_MAP") + .field( + "core1_psram_mspi_int_map", + &format_args!("{}", self.core1_psram_mspi_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_psram_mspi_int_map( + &mut self, + ) -> CORE1_PSRAM_MSPI_INT_MAP_W { + CORE1_PSRAM_MSPI_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psram_mspi_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psram_mspi_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PSRAM_MSPI_INT_MAP_SPEC; +impl crate::RegisterSpec for PSRAM_MSPI_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`psram_mspi_int_map::R`](R) reader structure"] +impl crate::Readable for PSRAM_MSPI_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`psram_mspi_int_map::W`](W) writer structure"] +impl crate::Writable for PSRAM_MSPI_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PSRAM_MSPI_INT_MAP to value 0"] +impl crate::Resettable for PSRAM_MSPI_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/pwm0_int_map.rs b/esp32p4/src/interrupt_core1/pwm0_int_map.rs new file mode 100644 index 0000000000..c1e91239bc --- /dev/null +++ b/esp32p4/src/interrupt_core1/pwm0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PWM0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PWM0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_PWM0_INT_MAP` reader - NA"] +pub type CORE1_PWM0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_PWM0_INT_MAP` writer - NA"] +pub type CORE1_PWM0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_pwm0_int_map(&self) -> CORE1_PWM0_INT_MAP_R { + CORE1_PWM0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM0_INT_MAP") + .field( + "core1_pwm0_int_map", + &format_args!("{}", self.core1_pwm0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_pwm0_int_map(&mut self) -> CORE1_PWM0_INT_MAP_W { + CORE1_PWM0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWM0_INT_MAP_SPEC; +impl crate::RegisterSpec for PWM0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm0_int_map::R`](R) reader structure"] +impl crate::Readable for PWM0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwm0_int_map::W`](W) writer structure"] +impl crate::Writable for PWM0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PWM0_INT_MAP to value 0"] +impl crate::Resettable for PWM0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/pwm1_int_map.rs b/esp32p4/src/interrupt_core1/pwm1_int_map.rs new file mode 100644 index 0000000000..a4fb10b575 --- /dev/null +++ b/esp32p4/src/interrupt_core1/pwm1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PWM1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `PWM1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_PWM1_INT_MAP` reader - NA"] +pub type CORE1_PWM1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_PWM1_INT_MAP` writer - NA"] +pub type CORE1_PWM1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_pwm1_int_map(&self) -> CORE1_PWM1_INT_MAP_R { + CORE1_PWM1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM1_INT_MAP") + .field( + "core1_pwm1_int_map", + &format_args!("{}", self.core1_pwm1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_pwm1_int_map(&mut self) -> CORE1_PWM1_INT_MAP_W { + CORE1_PWM1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWM1_INT_MAP_SPEC; +impl crate::RegisterSpec for PWM1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm1_int_map::R`](R) reader structure"] +impl crate::Readable for PWM1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwm1_int_map::W`](W) writer structure"] +impl crate::Writable for PWM1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PWM1_INT_MAP to value 0"] +impl crate::Resettable for PWM1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/rmt_int_map.rs b/esp32p4/src/interrupt_core1/rmt_int_map.rs new file mode 100644 index 0000000000..06c8316461 --- /dev/null +++ b/esp32p4/src/interrupt_core1/rmt_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RMT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `RMT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_RMT_INT_MAP` reader - NA"] +pub type CORE1_RMT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_RMT_INT_MAP` writer - NA"] +pub type CORE1_RMT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_rmt_int_map(&self) -> CORE1_RMT_INT_MAP_R { + CORE1_RMT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RMT_INT_MAP") + .field( + "core1_rmt_int_map", + &format_args!("{}", self.core1_rmt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_rmt_int_map(&mut self) -> CORE1_RMT_INT_MAP_W { + CORE1_RMT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rmt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rmt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RMT_INT_MAP_SPEC; +impl crate::RegisterSpec for RMT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rmt_int_map::R`](R) reader structure"] +impl crate::Readable for RMT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rmt_int_map::W`](W) writer structure"] +impl crate::Writable for RMT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RMT_INT_MAP to value 0"] +impl crate::Resettable for RMT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/rsa_int_map.rs b/esp32p4/src/interrupt_core1/rsa_int_map.rs new file mode 100644 index 0000000000..b32c6c7896 --- /dev/null +++ b/esp32p4/src/interrupt_core1/rsa_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RSA_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `RSA_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_RSA_INT_MAP` reader - NA"] +pub type CORE1_RSA_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_RSA_INT_MAP` writer - NA"] +pub type CORE1_RSA_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_rsa_int_map(&self) -> CORE1_RSA_INT_MAP_R { + CORE1_RSA_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSA_INT_MAP") + .field( + "core1_rsa_int_map", + &format_args!("{}", self.core1_rsa_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_rsa_int_map(&mut self) -> CORE1_RSA_INT_MAP_W { + CORE1_RSA_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsa_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsa_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RSA_INT_MAP_SPEC; +impl crate::RegisterSpec for RSA_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rsa_int_map::R`](R) reader structure"] +impl crate::Readable for RSA_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rsa_int_map::W`](W) writer structure"] +impl crate::Writable for RSA_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RSA_INT_MAP to value 0"] +impl crate::Resettable for RSA_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/sbd_int_map.rs b/esp32p4/src/interrupt_core1/sbd_int_map.rs new file mode 100644 index 0000000000..8eab769861 --- /dev/null +++ b/esp32p4/src/interrupt_core1/sbd_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SBD_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SBD_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_SBD_INT_MAP` reader - NA"] +pub type CORE1_SBD_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_SBD_INT_MAP` writer - NA"] +pub type CORE1_SBD_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_sbd_int_map(&self) -> CORE1_SBD_INT_MAP_R { + CORE1_SBD_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SBD_INT_MAP") + .field( + "core1_sbd_int_map", + &format_args!("{}", self.core1_sbd_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_sbd_int_map(&mut self) -> CORE1_SBD_INT_MAP_W { + CORE1_SBD_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbd_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbd_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBD_INT_MAP_SPEC; +impl crate::RegisterSpec for SBD_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbd_int_map::R`](R) reader structure"] +impl crate::Readable for SBD_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbd_int_map::W`](W) writer structure"] +impl crate::Writable for SBD_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SBD_INT_MAP to value 0"] +impl crate::Resettable for SBD_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/sdio_host_int_map.rs b/esp32p4/src/interrupt_core1/sdio_host_int_map.rs new file mode 100644 index 0000000000..57b8447bc5 --- /dev/null +++ b/esp32p4/src/interrupt_core1/sdio_host_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SDIO_HOST_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SDIO_HOST_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_SDIO_HOST_INT_MAP` reader - NA"] +pub type CORE1_SDIO_HOST_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_SDIO_HOST_INT_MAP` writer - NA"] +pub type CORE1_SDIO_HOST_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_sdio_host_int_map(&self) -> CORE1_SDIO_HOST_INT_MAP_R { + CORE1_SDIO_HOST_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDIO_HOST_INT_MAP") + .field( + "core1_sdio_host_int_map", + &format_args!("{}", self.core1_sdio_host_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_sdio_host_int_map(&mut self) -> CORE1_SDIO_HOST_INT_MAP_W { + CORE1_SDIO_HOST_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdio_host_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdio_host_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDIO_HOST_INT_MAP_SPEC; +impl crate::RegisterSpec for SDIO_HOST_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sdio_host_int_map::R`](R) reader structure"] +impl crate::Readable for SDIO_HOST_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sdio_host_int_map::W`](W) writer structure"] +impl crate::Writable for SDIO_HOST_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDIO_HOST_INT_MAP to value 0"] +impl crate::Resettable for SDIO_HOST_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/sha_int_map.rs b/esp32p4/src/interrupt_core1/sha_int_map.rs new file mode 100644 index 0000000000..9f313337b6 --- /dev/null +++ b/esp32p4/src/interrupt_core1/sha_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SHA_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SHA_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_SHA_INT_MAP` reader - NA"] +pub type CORE1_SHA_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_SHA_INT_MAP` writer - NA"] +pub type CORE1_SHA_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_sha_int_map(&self) -> CORE1_SHA_INT_MAP_R { + CORE1_SHA_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHA_INT_MAP") + .field( + "core1_sha_int_map", + &format_args!("{}", self.core1_sha_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_sha_int_map(&mut self) -> CORE1_SHA_INT_MAP_W { + CORE1_SHA_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sha_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHA_INT_MAP_SPEC; +impl crate::RegisterSpec for SHA_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sha_int_map::R`](R) reader structure"] +impl crate::Readable for SHA_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sha_int_map::W`](W) writer structure"] +impl crate::Writable for SHA_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SHA_INT_MAP to value 0"] +impl crate::Resettable for SHA_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/spi2_int_map.rs b/esp32p4/src/interrupt_core1/spi2_int_map.rs new file mode 100644 index 0000000000..103f5c1149 --- /dev/null +++ b/esp32p4/src/interrupt_core1/spi2_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SPI2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_SPI2_INT_MAP` reader - NA"] +pub type CORE1_SPI2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_SPI2_INT_MAP` writer - NA"] +pub type CORE1_SPI2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_spi2_int_map(&self) -> CORE1_SPI2_INT_MAP_R { + CORE1_SPI2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI2_INT_MAP") + .field( + "core1_spi2_int_map", + &format_args!("{}", self.core1_spi2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_spi2_int_map(&mut self) -> CORE1_SPI2_INT_MAP_W { + CORE1_SPI2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI2_INT_MAP_SPEC; +impl crate::RegisterSpec for SPI2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi2_int_map::R`](R) reader structure"] +impl crate::Readable for SPI2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi2_int_map::W`](W) writer structure"] +impl crate::Writable for SPI2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI2_INT_MAP to value 0"] +impl crate::Resettable for SPI2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/spi3_int_map.rs b/esp32p4/src/interrupt_core1/spi3_int_map.rs new file mode 100644 index 0000000000..16f375c1db --- /dev/null +++ b/esp32p4/src/interrupt_core1/spi3_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI3_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SPI3_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_SPI3_INT_MAP` reader - NA"] +pub type CORE1_SPI3_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_SPI3_INT_MAP` writer - NA"] +pub type CORE1_SPI3_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_spi3_int_map(&self) -> CORE1_SPI3_INT_MAP_R { + CORE1_SPI3_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI3_INT_MAP") + .field( + "core1_spi3_int_map", + &format_args!("{}", self.core1_spi3_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_spi3_int_map(&mut self) -> CORE1_SPI3_INT_MAP_W { + CORE1_SPI3_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi3_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi3_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI3_INT_MAP_SPEC; +impl crate::RegisterSpec for SPI3_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi3_int_map::R`](R) reader structure"] +impl crate::Readable for SPI3_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi3_int_map::W`](W) writer structure"] +impl crate::Writable for SPI3_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI3_INT_MAP to value 0"] +impl crate::Resettable for SPI3_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/sys_icm_int_map.rs b/esp32p4/src/interrupt_core1/sys_icm_int_map.rs new file mode 100644 index 0000000000..3fe4aebbee --- /dev/null +++ b/esp32p4/src/interrupt_core1/sys_icm_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SYS_ICM_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SYS_ICM_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_SYS_ICM_INT_MAP` reader - NA"] +pub type CORE1_SYS_ICM_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_SYS_ICM_INT_MAP` writer - NA"] +pub type CORE1_SYS_ICM_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_sys_icm_int_map(&self) -> CORE1_SYS_ICM_INT_MAP_R { + CORE1_SYS_ICM_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYS_ICM_INT_MAP") + .field( + "core1_sys_icm_int_map", + &format_args!("{}", self.core1_sys_icm_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_sys_icm_int_map(&mut self) -> CORE1_SYS_ICM_INT_MAP_W { + CORE1_SYS_ICM_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_icm_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_icm_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYS_ICM_INT_MAP_SPEC; +impl crate::RegisterSpec for SYS_ICM_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sys_icm_int_map::R`](R) reader structure"] +impl crate::Readable for SYS_ICM_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sys_icm_int_map::W`](W) writer structure"] +impl crate::Writable for SYS_ICM_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYS_ICM_INT_MAP to value 0"] +impl crate::Resettable for SYS_ICM_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/systimer_target0_int_map.rs b/esp32p4/src/interrupt_core1/systimer_target0_int_map.rs new file mode 100644 index 0000000000..eff1c6f769 --- /dev/null +++ b/esp32p4/src/interrupt_core1/systimer_target0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SYSTIMER_TARGET0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SYSTIMER_TARGET0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_SYSTIMER_TARGET0_INT_MAP` reader - NA"] +pub type CORE1_SYSTIMER_TARGET0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_SYSTIMER_TARGET0_INT_MAP` writer - NA"] +pub type CORE1_SYSTIMER_TARGET0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_systimer_target0_int_map(&self) -> CORE1_SYSTIMER_TARGET0_INT_MAP_R { + CORE1_SYSTIMER_TARGET0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTIMER_TARGET0_INT_MAP") + .field( + "core1_systimer_target0_int_map", + &format_args!("{}", self.core1_systimer_target0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_systimer_target0_int_map( + &mut self, + ) -> CORE1_SYSTIMER_TARGET0_INT_MAP_W { + CORE1_SYSTIMER_TARGET0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYSTIMER_TARGET0_INT_MAP_SPEC; +impl crate::RegisterSpec for SYSTIMER_TARGET0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`systimer_target0_int_map::R`](R) reader structure"] +impl crate::Readable for SYSTIMER_TARGET0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`systimer_target0_int_map::W`](W) writer structure"] +impl crate::Writable for SYSTIMER_TARGET0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYSTIMER_TARGET0_INT_MAP to value 0"] +impl crate::Resettable for SYSTIMER_TARGET0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/systimer_target1_int_map.rs b/esp32p4/src/interrupt_core1/systimer_target1_int_map.rs new file mode 100644 index 0000000000..c52e317b9c --- /dev/null +++ b/esp32p4/src/interrupt_core1/systimer_target1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SYSTIMER_TARGET1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SYSTIMER_TARGET1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_SYSTIMER_TARGET1_INT_MAP` reader - NA"] +pub type CORE1_SYSTIMER_TARGET1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_SYSTIMER_TARGET1_INT_MAP` writer - NA"] +pub type CORE1_SYSTIMER_TARGET1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_systimer_target1_int_map(&self) -> CORE1_SYSTIMER_TARGET1_INT_MAP_R { + CORE1_SYSTIMER_TARGET1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTIMER_TARGET1_INT_MAP") + .field( + "core1_systimer_target1_int_map", + &format_args!("{}", self.core1_systimer_target1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_systimer_target1_int_map( + &mut self, + ) -> CORE1_SYSTIMER_TARGET1_INT_MAP_W { + CORE1_SYSTIMER_TARGET1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYSTIMER_TARGET1_INT_MAP_SPEC; +impl crate::RegisterSpec for SYSTIMER_TARGET1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`systimer_target1_int_map::R`](R) reader structure"] +impl crate::Readable for SYSTIMER_TARGET1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`systimer_target1_int_map::W`](W) writer structure"] +impl crate::Writable for SYSTIMER_TARGET1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYSTIMER_TARGET1_INT_MAP to value 0"] +impl crate::Resettable for SYSTIMER_TARGET1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/systimer_target2_int_map.rs b/esp32p4/src/interrupt_core1/systimer_target2_int_map.rs new file mode 100644 index 0000000000..e88ef6c0e5 --- /dev/null +++ b/esp32p4/src/interrupt_core1/systimer_target2_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SYSTIMER_TARGET2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `SYSTIMER_TARGET2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_SYSTIMER_TARGET2_INT_MAP` reader - NA"] +pub type CORE1_SYSTIMER_TARGET2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_SYSTIMER_TARGET2_INT_MAP` writer - NA"] +pub type CORE1_SYSTIMER_TARGET2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_systimer_target2_int_map(&self) -> CORE1_SYSTIMER_TARGET2_INT_MAP_R { + CORE1_SYSTIMER_TARGET2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTIMER_TARGET2_INT_MAP") + .field( + "core1_systimer_target2_int_map", + &format_args!("{}", self.core1_systimer_target2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_systimer_target2_int_map( + &mut self, + ) -> CORE1_SYSTIMER_TARGET2_INT_MAP_W { + CORE1_SYSTIMER_TARGET2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systimer_target2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systimer_target2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYSTIMER_TARGET2_INT_MAP_SPEC; +impl crate::RegisterSpec for SYSTIMER_TARGET2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`systimer_target2_int_map::R`](R) reader structure"] +impl crate::Readable for SYSTIMER_TARGET2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`systimer_target2_int_map::W`](W) writer structure"] +impl crate::Writable for SYSTIMER_TARGET2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYSTIMER_TARGET2_INT_MAP to value 0"] +impl crate::Resettable for SYSTIMER_TARGET2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/timergrp0_t0_int_map.rs b/esp32p4/src/interrupt_core1/timergrp0_t0_int_map.rs new file mode 100644 index 0000000000..2841f8bef9 --- /dev/null +++ b/esp32p4/src/interrupt_core1/timergrp0_t0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP0_T0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP0_T0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_TIMERGRP0_T0_INT_MAP` reader - NA"] +pub type CORE1_TIMERGRP0_T0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_TIMERGRP0_T0_INT_MAP` writer - NA"] +pub type CORE1_TIMERGRP0_T0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_timergrp0_t0_int_map(&self) -> CORE1_TIMERGRP0_T0_INT_MAP_R { + CORE1_TIMERGRP0_T0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP0_T0_INT_MAP") + .field( + "core1_timergrp0_t0_int_map", + &format_args!("{}", self.core1_timergrp0_t0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_timergrp0_t0_int_map( + &mut self, + ) -> CORE1_TIMERGRP0_T0_INT_MAP_W { + CORE1_TIMERGRP0_T0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_t0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_t0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP0_T0_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP0_T0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp0_t0_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP0_T0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp0_t0_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP0_T0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP0_T0_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP0_T0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/timergrp0_t1_int_map.rs b/esp32p4/src/interrupt_core1/timergrp0_t1_int_map.rs new file mode 100644 index 0000000000..dfa1758984 --- /dev/null +++ b/esp32p4/src/interrupt_core1/timergrp0_t1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP0_T1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP0_T1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_TIMERGRP0_T1_INT_MAP` reader - NA"] +pub type CORE1_TIMERGRP0_T1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_TIMERGRP0_T1_INT_MAP` writer - NA"] +pub type CORE1_TIMERGRP0_T1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_timergrp0_t1_int_map(&self) -> CORE1_TIMERGRP0_T1_INT_MAP_R { + CORE1_TIMERGRP0_T1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP0_T1_INT_MAP") + .field( + "core1_timergrp0_t1_int_map", + &format_args!("{}", self.core1_timergrp0_t1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_timergrp0_t1_int_map( + &mut self, + ) -> CORE1_TIMERGRP0_T1_INT_MAP_W { + CORE1_TIMERGRP0_T1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_t1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_t1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP0_T1_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP0_T1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp0_t1_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP0_T1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp0_t1_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP0_T1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP0_T1_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP0_T1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/timergrp0_wdt_int_map.rs b/esp32p4/src/interrupt_core1/timergrp0_wdt_int_map.rs new file mode 100644 index 0000000000..30503ac813 --- /dev/null +++ b/esp32p4/src/interrupt_core1/timergrp0_wdt_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP0_WDT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP0_WDT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_TIMERGRP0_WDT_INT_MAP` reader - NA"] +pub type CORE1_TIMERGRP0_WDT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_TIMERGRP0_WDT_INT_MAP` writer - NA"] +pub type CORE1_TIMERGRP0_WDT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_timergrp0_wdt_int_map(&self) -> CORE1_TIMERGRP0_WDT_INT_MAP_R { + CORE1_TIMERGRP0_WDT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP0_WDT_INT_MAP") + .field( + "core1_timergrp0_wdt_int_map", + &format_args!("{}", self.core1_timergrp0_wdt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_timergrp0_wdt_int_map( + &mut self, + ) -> CORE1_TIMERGRP0_WDT_INT_MAP_W { + CORE1_TIMERGRP0_WDT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp0_wdt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp0_wdt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP0_WDT_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP0_WDT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp0_wdt_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP0_WDT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp0_wdt_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP0_WDT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP0_WDT_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP0_WDT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/timergrp1_t0_int_map.rs b/esp32p4/src/interrupt_core1/timergrp1_t0_int_map.rs new file mode 100644 index 0000000000..310779a6d4 --- /dev/null +++ b/esp32p4/src/interrupt_core1/timergrp1_t0_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP1_T0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP1_T0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_TIMERGRP1_T0_INT_MAP` reader - NA"] +pub type CORE1_TIMERGRP1_T0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_TIMERGRP1_T0_INT_MAP` writer - NA"] +pub type CORE1_TIMERGRP1_T0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_timergrp1_t0_int_map(&self) -> CORE1_TIMERGRP1_T0_INT_MAP_R { + CORE1_TIMERGRP1_T0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP1_T0_INT_MAP") + .field( + "core1_timergrp1_t0_int_map", + &format_args!("{}", self.core1_timergrp1_t0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_timergrp1_t0_int_map( + &mut self, + ) -> CORE1_TIMERGRP1_T0_INT_MAP_W { + CORE1_TIMERGRP1_T0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_t0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_t0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP1_T0_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP1_T0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp1_t0_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP1_T0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp1_t0_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP1_T0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP1_T0_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP1_T0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/timergrp1_t1_int_map.rs b/esp32p4/src/interrupt_core1/timergrp1_t1_int_map.rs new file mode 100644 index 0000000000..8505beb324 --- /dev/null +++ b/esp32p4/src/interrupt_core1/timergrp1_t1_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP1_T1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP1_T1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_TIMERGRP1_T1_INT_MAP` reader - NA"] +pub type CORE1_TIMERGRP1_T1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_TIMERGRP1_T1_INT_MAP` writer - NA"] +pub type CORE1_TIMERGRP1_T1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_timergrp1_t1_int_map(&self) -> CORE1_TIMERGRP1_T1_INT_MAP_R { + CORE1_TIMERGRP1_T1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP1_T1_INT_MAP") + .field( + "core1_timergrp1_t1_int_map", + &format_args!("{}", self.core1_timergrp1_t1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_timergrp1_t1_int_map( + &mut self, + ) -> CORE1_TIMERGRP1_T1_INT_MAP_W { + CORE1_TIMERGRP1_T1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_t1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_t1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP1_T1_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP1_T1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp1_t1_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP1_T1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp1_t1_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP1_T1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP1_T1_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP1_T1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/timergrp1_wdt_int_map.rs b/esp32p4/src/interrupt_core1/timergrp1_wdt_int_map.rs new file mode 100644 index 0000000000..a95c60f9b6 --- /dev/null +++ b/esp32p4/src/interrupt_core1/timergrp1_wdt_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TIMERGRP1_WDT_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERGRP1_WDT_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_TIMERGRP1_WDT_INT_MAP` reader - NA"] +pub type CORE1_TIMERGRP1_WDT_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_TIMERGRP1_WDT_INT_MAP` writer - NA"] +pub type CORE1_TIMERGRP1_WDT_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_timergrp1_wdt_int_map(&self) -> CORE1_TIMERGRP1_WDT_INT_MAP_R { + CORE1_TIMERGRP1_WDT_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMERGRP1_WDT_INT_MAP") + .field( + "core1_timergrp1_wdt_int_map", + &format_args!("{}", self.core1_timergrp1_wdt_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_timergrp1_wdt_int_map( + &mut self, + ) -> CORE1_TIMERGRP1_WDT_INT_MAP_W { + CORE1_TIMERGRP1_WDT_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timergrp1_wdt_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timergrp1_wdt_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERGRP1_WDT_INT_MAP_SPEC; +impl crate::RegisterSpec for TIMERGRP1_WDT_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timergrp1_wdt_int_map::R`](R) reader structure"] +impl crate::Readable for TIMERGRP1_WDT_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timergrp1_wdt_int_map::W`](W) writer structure"] +impl crate::Writable for TIMERGRP1_WDT_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMERGRP1_WDT_INT_MAP to value 0"] +impl crate::Resettable for TIMERGRP1_WDT_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/uart0_int_map.rs b/esp32p4/src/interrupt_core1/uart0_int_map.rs new file mode 100644 index 0000000000..8fbaf35129 --- /dev/null +++ b/esp32p4/src/interrupt_core1/uart0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UART0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UART0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_UART0_INT_MAP` reader - NA"] +pub type CORE1_UART0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_UART0_INT_MAP` writer - NA"] +pub type CORE1_UART0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_uart0_int_map(&self) -> CORE1_UART0_INT_MAP_R { + CORE1_UART0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART0_INT_MAP") + .field( + "core1_uart0_int_map", + &format_args!("{}", self.core1_uart0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_uart0_int_map(&mut self) -> CORE1_UART0_INT_MAP_W { + CORE1_UART0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART0_INT_MAP_SPEC; +impl crate::RegisterSpec for UART0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart0_int_map::R`](R) reader structure"] +impl crate::Readable for UART0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart0_int_map::W`](W) writer structure"] +impl crate::Writable for UART0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UART0_INT_MAP to value 0"] +impl crate::Resettable for UART0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/uart1_int_map.rs b/esp32p4/src/interrupt_core1/uart1_int_map.rs new file mode 100644 index 0000000000..97c10af380 --- /dev/null +++ b/esp32p4/src/interrupt_core1/uart1_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UART1_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UART1_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_UART1_INT_MAP` reader - NA"] +pub type CORE1_UART1_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_UART1_INT_MAP` writer - NA"] +pub type CORE1_UART1_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_uart1_int_map(&self) -> CORE1_UART1_INT_MAP_R { + CORE1_UART1_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART1_INT_MAP") + .field( + "core1_uart1_int_map", + &format_args!("{}", self.core1_uart1_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_uart1_int_map(&mut self) -> CORE1_UART1_INT_MAP_W { + CORE1_UART1_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart1_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart1_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART1_INT_MAP_SPEC; +impl crate::RegisterSpec for UART1_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart1_int_map::R`](R) reader structure"] +impl crate::Readable for UART1_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart1_int_map::W`](W) writer structure"] +impl crate::Writable for UART1_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UART1_INT_MAP to value 0"] +impl crate::Resettable for UART1_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/uart2_int_map.rs b/esp32p4/src/interrupt_core1/uart2_int_map.rs new file mode 100644 index 0000000000..b1f03486bc --- /dev/null +++ b/esp32p4/src/interrupt_core1/uart2_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UART2_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UART2_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_UART2_INT_MAP` reader - NA"] +pub type CORE1_UART2_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_UART2_INT_MAP` writer - NA"] +pub type CORE1_UART2_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_uart2_int_map(&self) -> CORE1_UART2_INT_MAP_R { + CORE1_UART2_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART2_INT_MAP") + .field( + "core1_uart2_int_map", + &format_args!("{}", self.core1_uart2_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_uart2_int_map(&mut self) -> CORE1_UART2_INT_MAP_W { + CORE1_UART2_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart2_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart2_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART2_INT_MAP_SPEC; +impl crate::RegisterSpec for UART2_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart2_int_map::R`](R) reader structure"] +impl crate::Readable for UART2_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart2_int_map::W`](W) writer structure"] +impl crate::Writable for UART2_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UART2_INT_MAP to value 0"] +impl crate::Resettable for UART2_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/uart3_int_map.rs b/esp32p4/src/interrupt_core1/uart3_int_map.rs new file mode 100644 index 0000000000..a5e02fa975 --- /dev/null +++ b/esp32p4/src/interrupt_core1/uart3_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UART3_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UART3_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_UART3_INT_MAP` reader - NA"] +pub type CORE1_UART3_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_UART3_INT_MAP` writer - NA"] +pub type CORE1_UART3_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_uart3_int_map(&self) -> CORE1_UART3_INT_MAP_R { + CORE1_UART3_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART3_INT_MAP") + .field( + "core1_uart3_int_map", + &format_args!("{}", self.core1_uart3_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_uart3_int_map(&mut self) -> CORE1_UART3_INT_MAP_W { + CORE1_UART3_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart3_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart3_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART3_INT_MAP_SPEC; +impl crate::RegisterSpec for UART3_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart3_int_map::R`](R) reader structure"] +impl crate::Readable for UART3_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart3_int_map::W`](W) writer structure"] +impl crate::Writable for UART3_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UART3_INT_MAP to value 0"] +impl crate::Resettable for UART3_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/uart4_int_map.rs b/esp32p4/src/interrupt_core1/uart4_int_map.rs new file mode 100644 index 0000000000..18853ab9b0 --- /dev/null +++ b/esp32p4/src/interrupt_core1/uart4_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UART4_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UART4_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_UART4_INT_MAP` reader - NA"] +pub type CORE1_UART4_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_UART4_INT_MAP` writer - NA"] +pub type CORE1_UART4_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_uart4_int_map(&self) -> CORE1_UART4_INT_MAP_R { + CORE1_UART4_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART4_INT_MAP") + .field( + "core1_uart4_int_map", + &format_args!("{}", self.core1_uart4_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_uart4_int_map(&mut self) -> CORE1_UART4_INT_MAP_W { + CORE1_UART4_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart4_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart4_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART4_INT_MAP_SPEC; +impl crate::RegisterSpec for UART4_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart4_int_map::R`](R) reader structure"] +impl crate::Readable for UART4_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart4_int_map::W`](W) writer structure"] +impl crate::Writable for UART4_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UART4_INT_MAP to value 0"] +impl crate::Resettable for UART4_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/uhci0_int_map.rs b/esp32p4/src/interrupt_core1/uhci0_int_map.rs new file mode 100644 index 0000000000..45ad27e74b --- /dev/null +++ b/esp32p4/src/interrupt_core1/uhci0_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UHCI0_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `UHCI0_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_UHCI0_INT_MAP` reader - NA"] +pub type CORE1_UHCI0_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_UHCI0_INT_MAP` writer - NA"] +pub type CORE1_UHCI0_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_uhci0_int_map(&self) -> CORE1_UHCI0_INT_MAP_R { + CORE1_UHCI0_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UHCI0_INT_MAP") + .field( + "core1_uhci0_int_map", + &format_args!("{}", self.core1_uhci0_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_uhci0_int_map(&mut self) -> CORE1_UHCI0_INT_MAP_W { + CORE1_UHCI0_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uhci0_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uhci0_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UHCI0_INT_MAP_SPEC; +impl crate::RegisterSpec for UHCI0_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uhci0_int_map::R`](R) reader structure"] +impl crate::Readable for UHCI0_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uhci0_int_map::W`](W) writer structure"] +impl crate::Writable for UHCI0_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UHCI0_INT_MAP to value 0"] +impl crate::Resettable for UHCI0_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/usb_device_int_map.rs b/esp32p4/src/interrupt_core1/usb_device_int_map.rs new file mode 100644 index 0000000000..b75a28918c --- /dev/null +++ b/esp32p4/src/interrupt_core1/usb_device_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `USB_DEVICE_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `USB_DEVICE_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_USB_DEVICE_INT_MAP` reader - NA"] +pub type CORE1_USB_DEVICE_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_USB_DEVICE_INT_MAP` writer - NA"] +pub type CORE1_USB_DEVICE_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_usb_device_int_map(&self) -> CORE1_USB_DEVICE_INT_MAP_R { + CORE1_USB_DEVICE_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_DEVICE_INT_MAP") + .field( + "core1_usb_device_int_map", + &format_args!("{}", self.core1_usb_device_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_usb_device_int_map( + &mut self, + ) -> CORE1_USB_DEVICE_INT_MAP_W { + CORE1_USB_DEVICE_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_device_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_device_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_DEVICE_INT_MAP_SPEC; +impl crate::RegisterSpec for USB_DEVICE_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_device_int_map::R`](R) reader structure"] +impl crate::Readable for USB_DEVICE_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_device_int_map::W`](W) writer structure"] +impl crate::Writable for USB_DEVICE_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USB_DEVICE_INT_MAP to value 0"] +impl crate::Resettable for USB_DEVICE_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/usb_otg11_int_map.rs b/esp32p4/src/interrupt_core1/usb_otg11_int_map.rs new file mode 100644 index 0000000000..a20d7a3496 --- /dev/null +++ b/esp32p4/src/interrupt_core1/usb_otg11_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `USB_OTG11_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `USB_OTG11_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_USB_OTG11_INT_MAP` reader - NA"] +pub type CORE1_USB_OTG11_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_USB_OTG11_INT_MAP` writer - NA"] +pub type CORE1_USB_OTG11_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_usb_otg11_int_map(&self) -> CORE1_USB_OTG11_INT_MAP_R { + CORE1_USB_OTG11_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG11_INT_MAP") + .field( + "core1_usb_otg11_int_map", + &format_args!("{}", self.core1_usb_otg11_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_usb_otg11_int_map(&mut self) -> CORE1_USB_OTG11_INT_MAP_W { + CORE1_USB_OTG11_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg11_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg11_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_OTG11_INT_MAP_SPEC; +impl crate::RegisterSpec for USB_OTG11_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_otg11_int_map::R`](R) reader structure"] +impl crate::Readable for USB_OTG11_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_otg11_int_map::W`](W) writer structure"] +impl crate::Writable for USB_OTG11_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USB_OTG11_INT_MAP to value 0"] +impl crate::Resettable for USB_OTG11_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/usb_otg_endp_multi_proc_int_map.rs b/esp32p4/src/interrupt_core1/usb_otg_endp_multi_proc_int_map.rs new file mode 100644 index 0000000000..1d666c9738 --- /dev/null +++ b/esp32p4/src/interrupt_core1/usb_otg_endp_multi_proc_int_map.rs @@ -0,0 +1,68 @@ +#[doc = "Register `USB_OTG_ENDP_MULTI_PROC_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `USB_OTG_ENDP_MULTI_PROC_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP` reader - NA"] +pub type CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP` writer - NA"] +pub type CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_usb_otg_endp_multi_proc_int_map(&self) -> CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_R { + CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_ENDP_MULTI_PROC_INT_MAP") + .field( + "core1_usb_otg_endp_multi_proc_int_map", + &format_args!("{}", self.core1_usb_otg_endp_multi_proc_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_usb_otg_endp_multi_proc_int_map( + &mut self, + ) -> CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_W { + CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg_endp_multi_proc_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg_endp_multi_proc_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC; +impl crate::RegisterSpec for USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_otg_endp_multi_proc_int_map::R`](R) reader structure"] +impl crate::Readable for USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_otg_endp_multi_proc_int_map::W`](W) writer structure"] +impl crate::Writable for USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USB_OTG_ENDP_MULTI_PROC_INT_MAP to value 0"] +impl crate::Resettable for USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/interrupt_core1/usb_otg_int_map.rs b/esp32p4/src/interrupt_core1/usb_otg_int_map.rs new file mode 100644 index 0000000000..2ebaeff249 --- /dev/null +++ b/esp32p4/src/interrupt_core1/usb_otg_int_map.rs @@ -0,0 +1,66 @@ +#[doc = "Register `USB_OTG_INT_MAP` reader"] +pub type R = crate::R; +#[doc = "Register `USB_OTG_INT_MAP` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1_USB_OTG_INT_MAP` reader - NA"] +pub type CORE1_USB_OTG_INT_MAP_R = crate::FieldReader; +#[doc = "Field `CORE1_USB_OTG_INT_MAP` writer - NA"] +pub type CORE1_USB_OTG_INT_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn core1_usb_otg_int_map(&self) -> CORE1_USB_OTG_INT_MAP_R { + CORE1_USB_OTG_INT_MAP_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_OTG_INT_MAP") + .field( + "core1_usb_otg_int_map", + &format_args!("{}", self.core1_usb_otg_int_map().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn core1_usb_otg_int_map(&mut self) -> CORE1_USB_OTG_INT_MAP_W { + CORE1_USB_OTG_INT_MAP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_otg_int_map::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_otg_int_map::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_OTG_INT_MAP_SPEC; +impl crate::RegisterSpec for USB_OTG_INT_MAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_otg_int_map::R`](R) reader structure"] +impl crate::Readable for USB_OTG_INT_MAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_otg_int_map::W`](W) writer structure"] +impl crate::Writable for USB_OTG_INT_MAP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USB_OTG_INT_MAP to value 0"] +impl crate::Resettable for USB_OTG_INT_MAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/io_mux.rs b/esp32p4/src/io_mux.rs new file mode 100644 index 0000000000..5e5fe908b3 --- /dev/null +++ b/esp32p4/src/io_mux.rs @@ -0,0 +1,589 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + _reserved0: [u8; 0x04], + gpio0: GPIO0, + gpio1: GPIO1, + gpio2: GPIO2, + gpio3: GPIO3, + gpio4: GPIO4, + gpio5: GPIO5, + gpio6: GPIO6, + gpio7: GPIO7, + gpio8: GPIO8, + gpio9: GPIO9, + gpio10: GPIO10, + gpio11: GPIO11, + gpio12: GPIO12, + gpio13: GPIO13, + gpio14: GPIO14, + gpio15: GPIO15, + gpio16: GPIO16, + gpio17: GPIO17, + gpio18: GPIO18, + gpio19: GPIO19, + gpio20: GPIO20, + gpio21: GPIO21, + gpio22: GPIO22, + gpio23: GPIO23, + gpio24: GPIO24, + gpio25: GPIO25, + gpio26: GPIO26, + gpio27: GPIO27, + gpio28: GPIO28, + gpio29: GPIO29, + gpio30: GPIO30, + gpio31: GPIO31, + gpio32: GPIO32, + gpio33: GPIO33, + gpio34: GPIO34, + gpio35: GPIO35, + gpio36: GPIO36, + gpio37: GPIO37, + gpio38: GPIO38, + gpio39: GPIO39, + gpio40: GPIO40, + gpio41: GPIO41, + gpio42: GPIO42, + gpio43: GPIO43, + gpio44: GPIO44, + gpio45: GPIO45, + gpio46: GPIO46, + gpio47: GPIO47, + gpio48: GPIO48, + gpio49: GPIO49, + gpio50: GPIO50, + gpio51: GPIO51, + gpio52: GPIO52, + gpio53: GPIO53, + gpio54: GPIO54, + gpio55: GPIO55, + gpio56: GPIO56, + _reserved57: [u8; 0x1c], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x04 - iomux control register for gpio0"] + #[inline(always)] + pub const fn gpio0(&self) -> &GPIO0 { + &self.gpio0 + } + #[doc = "0x08 - iomux control register for gpio1"] + #[inline(always)] + pub const fn gpio1(&self) -> &GPIO1 { + &self.gpio1 + } + #[doc = "0x0c - iomux control register for gpio2"] + #[inline(always)] + pub const fn gpio2(&self) -> &GPIO2 { + &self.gpio2 + } + #[doc = "0x10 - iomux control register for gpio3"] + #[inline(always)] + pub const fn gpio3(&self) -> &GPIO3 { + &self.gpio3 + } + #[doc = "0x14 - iomux control register for gpio4"] + #[inline(always)] + pub const fn gpio4(&self) -> &GPIO4 { + &self.gpio4 + } + #[doc = "0x18 - iomux control register for gpio5"] + #[inline(always)] + pub const fn gpio5(&self) -> &GPIO5 { + &self.gpio5 + } + #[doc = "0x1c - iomux control register for gpio6"] + #[inline(always)] + pub const fn gpio6(&self) -> &GPIO6 { + &self.gpio6 + } + #[doc = "0x20 - iomux control register for gpio7"] + #[inline(always)] + pub const fn gpio7(&self) -> &GPIO7 { + &self.gpio7 + } + #[doc = "0x24 - iomux control register for gpio8"] + #[inline(always)] + pub const fn gpio8(&self) -> &GPIO8 { + &self.gpio8 + } + #[doc = "0x28 - iomux control register for gpio9"] + #[inline(always)] + pub const fn gpio9(&self) -> &GPIO9 { + &self.gpio9 + } + #[doc = "0x2c - iomux control register for gpio10"] + #[inline(always)] + pub const fn gpio10(&self) -> &GPIO10 { + &self.gpio10 + } + #[doc = "0x30 - iomux control register for gpio11"] + #[inline(always)] + pub const fn gpio11(&self) -> &GPIO11 { + &self.gpio11 + } + #[doc = "0x34 - iomux control register for gpio12"] + #[inline(always)] + pub const fn gpio12(&self) -> &GPIO12 { + &self.gpio12 + } + #[doc = "0x38 - iomux control register for gpio13"] + #[inline(always)] + pub const fn gpio13(&self) -> &GPIO13 { + &self.gpio13 + } + #[doc = "0x3c - iomux control register for gpio14"] + #[inline(always)] + pub const fn gpio14(&self) -> &GPIO14 { + &self.gpio14 + } + #[doc = "0x40 - iomux control register for gpio15"] + #[inline(always)] + pub const fn gpio15(&self) -> &GPIO15 { + &self.gpio15 + } + #[doc = "0x44 - iomux control register for gpio16"] + #[inline(always)] + pub const fn gpio16(&self) -> &GPIO16 { + &self.gpio16 + } + #[doc = "0x48 - iomux control register for gpio17"] + #[inline(always)] + pub const fn gpio17(&self) -> &GPIO17 { + &self.gpio17 + } + #[doc = "0x4c - iomux control register for gpio18"] + #[inline(always)] + pub const fn gpio18(&self) -> &GPIO18 { + &self.gpio18 + } + #[doc = "0x50 - iomux control register for gpio19"] + #[inline(always)] + pub const fn gpio19(&self) -> &GPIO19 { + &self.gpio19 + } + #[doc = "0x54 - iomux control register for gpio20"] + #[inline(always)] + pub const fn gpio20(&self) -> &GPIO20 { + &self.gpio20 + } + #[doc = "0x58 - iomux control register for gpio21"] + #[inline(always)] + pub const fn gpio21(&self) -> &GPIO21 { + &self.gpio21 + } + #[doc = "0x5c - iomux control register for gpio22"] + #[inline(always)] + pub const fn gpio22(&self) -> &GPIO22 { + &self.gpio22 + } + #[doc = "0x60 - iomux control register for gpio23"] + #[inline(always)] + pub const fn gpio23(&self) -> &GPIO23 { + &self.gpio23 + } + #[doc = "0x64 - iomux control register for gpio24"] + #[inline(always)] + pub const fn gpio24(&self) -> &GPIO24 { + &self.gpio24 + } + #[doc = "0x68 - iomux control register for gpio25"] + #[inline(always)] + pub const fn gpio25(&self) -> &GPIO25 { + &self.gpio25 + } + #[doc = "0x6c - iomux control register for gpio26"] + #[inline(always)] + pub const fn gpio26(&self) -> &GPIO26 { + &self.gpio26 + } + #[doc = "0x70 - iomux control register for gpio27"] + #[inline(always)] + pub const fn gpio27(&self) -> &GPIO27 { + &self.gpio27 + } + #[doc = "0x74 - iomux control register for gpio28"] + #[inline(always)] + pub const fn gpio28(&self) -> &GPIO28 { + &self.gpio28 + } + #[doc = "0x78 - iomux control register for gpio29"] + #[inline(always)] + pub const fn gpio29(&self) -> &GPIO29 { + &self.gpio29 + } + #[doc = "0x7c - iomux control register for gpio30"] + #[inline(always)] + pub const fn gpio30(&self) -> &GPIO30 { + &self.gpio30 + } + #[doc = "0x80 - iomux control register for gpio31"] + #[inline(always)] + pub const fn gpio31(&self) -> &GPIO31 { + &self.gpio31 + } + #[doc = "0x84 - iomux control register for gpio32"] + #[inline(always)] + pub const fn gpio32(&self) -> &GPIO32 { + &self.gpio32 + } + #[doc = "0x88 - iomux control register for gpio33"] + #[inline(always)] + pub const fn gpio33(&self) -> &GPIO33 { + &self.gpio33 + } + #[doc = "0x8c - iomux control register for gpio34"] + #[inline(always)] + pub const fn gpio34(&self) -> &GPIO34 { + &self.gpio34 + } + #[doc = "0x90 - iomux control register for gpio35"] + #[inline(always)] + pub const fn gpio35(&self) -> &GPIO35 { + &self.gpio35 + } + #[doc = "0x94 - iomux control register for gpio36"] + #[inline(always)] + pub const fn gpio36(&self) -> &GPIO36 { + &self.gpio36 + } + #[doc = "0x98 - iomux control register for gpio37"] + #[inline(always)] + pub const fn gpio37(&self) -> &GPIO37 { + &self.gpio37 + } + #[doc = "0x9c - iomux control register for gpio38"] + #[inline(always)] + pub const fn gpio38(&self) -> &GPIO38 { + &self.gpio38 + } + #[doc = "0xa0 - iomux control register for gpio39"] + #[inline(always)] + pub const fn gpio39(&self) -> &GPIO39 { + &self.gpio39 + } + #[doc = "0xa4 - iomux control register for gpio40"] + #[inline(always)] + pub const fn gpio40(&self) -> &GPIO40 { + &self.gpio40 + } + #[doc = "0xa8 - iomux control register for gpio41"] + #[inline(always)] + pub const fn gpio41(&self) -> &GPIO41 { + &self.gpio41 + } + #[doc = "0xac - iomux control register for gpio42"] + #[inline(always)] + pub const fn gpio42(&self) -> &GPIO42 { + &self.gpio42 + } + #[doc = "0xb0 - iomux control register for gpio43"] + #[inline(always)] + pub const fn gpio43(&self) -> &GPIO43 { + &self.gpio43 + } + #[doc = "0xb4 - iomux control register for gpio44"] + #[inline(always)] + pub const fn gpio44(&self) -> &GPIO44 { + &self.gpio44 + } + #[doc = "0xb8 - iomux control register for gpio45"] + #[inline(always)] + pub const fn gpio45(&self) -> &GPIO45 { + &self.gpio45 + } + #[doc = "0xbc - iomux control register for gpio46"] + #[inline(always)] + pub const fn gpio46(&self) -> &GPIO46 { + &self.gpio46 + } + #[doc = "0xc0 - iomux control register for gpio47"] + #[inline(always)] + pub const fn gpio47(&self) -> &GPIO47 { + &self.gpio47 + } + #[doc = "0xc4 - iomux control register for gpio48"] + #[inline(always)] + pub const fn gpio48(&self) -> &GPIO48 { + &self.gpio48 + } + #[doc = "0xc8 - iomux control register for gpio49"] + #[inline(always)] + pub const fn gpio49(&self) -> &GPIO49 { + &self.gpio49 + } + #[doc = "0xcc - iomux control register for gpio50"] + #[inline(always)] + pub const fn gpio50(&self) -> &GPIO50 { + &self.gpio50 + } + #[doc = "0xd0 - iomux control register for gpio51"] + #[inline(always)] + pub const fn gpio51(&self) -> &GPIO51 { + &self.gpio51 + } + #[doc = "0xd4 - iomux control register for gpio52"] + #[inline(always)] + pub const fn gpio52(&self) -> &GPIO52 { + &self.gpio52 + } + #[doc = "0xd8 - iomux control register for gpio53"] + #[inline(always)] + pub const fn gpio53(&self) -> &GPIO53 { + &self.gpio53 + } + #[doc = "0xdc - iomux control register for gpio54"] + #[inline(always)] + pub const fn gpio54(&self) -> &GPIO54 { + &self.gpio54 + } + #[doc = "0xe0 - iomux control register for gpio55"] + #[inline(always)] + pub const fn gpio55(&self) -> &GPIO55 { + &self.gpio55 + } + #[doc = "0xe4 - iomux control register for gpio56"] + #[inline(always)] + pub const fn gpio56(&self) -> &GPIO56 { + &self.gpio56 + } + #[doc = "0x104 - iomux version"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "gpio0 (rw) register accessor: iomux control register for gpio0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio0`] module"] +pub type GPIO0 = crate::Reg; +#[doc = "iomux control register for gpio0"] +pub mod gpio0; +#[doc = "gpio1 (rw) register accessor: iomux control register for gpio1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio1`] module"] +pub type GPIO1 = crate::Reg; +#[doc = "iomux control register for gpio1"] +pub mod gpio1; +#[doc = "gpio2 (rw) register accessor: iomux control register for gpio2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio2`] module"] +pub type GPIO2 = crate::Reg; +#[doc = "iomux control register for gpio2"] +pub mod gpio2; +#[doc = "gpio3 (rw) register accessor: iomux control register for gpio3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio3`] module"] +pub type GPIO3 = crate::Reg; +#[doc = "iomux control register for gpio3"] +pub mod gpio3; +#[doc = "gpio4 (rw) register accessor: iomux control register for gpio4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio4`] module"] +pub type GPIO4 = crate::Reg; +#[doc = "iomux control register for gpio4"] +pub mod gpio4; +#[doc = "gpio5 (rw) register accessor: iomux control register for gpio5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio5`] module"] +pub type GPIO5 = crate::Reg; +#[doc = "iomux control register for gpio5"] +pub mod gpio5; +#[doc = "gpio6 (rw) register accessor: iomux control register for gpio6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio6`] module"] +pub type GPIO6 = crate::Reg; +#[doc = "iomux control register for gpio6"] +pub mod gpio6; +#[doc = "gpio7 (rw) register accessor: iomux control register for gpio7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio7`] module"] +pub type GPIO7 = crate::Reg; +#[doc = "iomux control register for gpio7"] +pub mod gpio7; +#[doc = "gpio8 (rw) register accessor: iomux control register for gpio8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio8`] module"] +pub type GPIO8 = crate::Reg; +#[doc = "iomux control register for gpio8"] +pub mod gpio8; +#[doc = "gpio9 (rw) register accessor: iomux control register for gpio9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio9`] module"] +pub type GPIO9 = crate::Reg; +#[doc = "iomux control register for gpio9"] +pub mod gpio9; +#[doc = "gpio10 (rw) register accessor: iomux control register for gpio10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio10`] module"] +pub type GPIO10 = crate::Reg; +#[doc = "iomux control register for gpio10"] +pub mod gpio10; +#[doc = "gpio11 (rw) register accessor: iomux control register for gpio11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio11`] module"] +pub type GPIO11 = crate::Reg; +#[doc = "iomux control register for gpio11"] +pub mod gpio11; +#[doc = "gpio12 (rw) register accessor: iomux control register for gpio12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio12`] module"] +pub type GPIO12 = crate::Reg; +#[doc = "iomux control register for gpio12"] +pub mod gpio12; +#[doc = "gpio13 (rw) register accessor: iomux control register for gpio13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio13`] module"] +pub type GPIO13 = crate::Reg; +#[doc = "iomux control register for gpio13"] +pub mod gpio13; +#[doc = "gpio14 (rw) register accessor: iomux control register for gpio14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio14`] module"] +pub type GPIO14 = crate::Reg; +#[doc = "iomux control register for gpio14"] +pub mod gpio14; +#[doc = "gpio15 (rw) register accessor: iomux control register for gpio15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio15`] module"] +pub type GPIO15 = crate::Reg; +#[doc = "iomux control register for gpio15"] +pub mod gpio15; +#[doc = "gpio16 (rw) register accessor: iomux control register for gpio16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio16::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio16`] module"] +pub type GPIO16 = crate::Reg; +#[doc = "iomux control register for gpio16"] +pub mod gpio16; +#[doc = "gpio17 (rw) register accessor: iomux control register for gpio17\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio17::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio17::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio17`] module"] +pub type GPIO17 = crate::Reg; +#[doc = "iomux control register for gpio17"] +pub mod gpio17; +#[doc = "gpio18 (rw) register accessor: iomux control register for gpio18\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio18::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio18::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio18`] module"] +pub type GPIO18 = crate::Reg; +#[doc = "iomux control register for gpio18"] +pub mod gpio18; +#[doc = "gpio19 (rw) register accessor: iomux control register for gpio19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio19::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio19::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio19`] module"] +pub type GPIO19 = crate::Reg; +#[doc = "iomux control register for gpio19"] +pub mod gpio19; +#[doc = "gpio20 (rw) register accessor: iomux control register for gpio20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio20::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio20::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio20`] module"] +pub type GPIO20 = crate::Reg; +#[doc = "iomux control register for gpio20"] +pub mod gpio20; +#[doc = "gpio21 (rw) register accessor: iomux control register for gpio21\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio21::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio21::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio21`] module"] +pub type GPIO21 = crate::Reg; +#[doc = "iomux control register for gpio21"] +pub mod gpio21; +#[doc = "gpio22 (rw) register accessor: iomux control register for gpio22\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio22::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio22::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio22`] module"] +pub type GPIO22 = crate::Reg; +#[doc = "iomux control register for gpio22"] +pub mod gpio22; +#[doc = "gpio23 (rw) register accessor: iomux control register for gpio23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio23::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio23::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio23`] module"] +pub type GPIO23 = crate::Reg; +#[doc = "iomux control register for gpio23"] +pub mod gpio23; +#[doc = "gpio24 (rw) register accessor: iomux control register for gpio24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio24::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio24::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio24`] module"] +pub type GPIO24 = crate::Reg; +#[doc = "iomux control register for gpio24"] +pub mod gpio24; +#[doc = "gpio25 (rw) register accessor: iomux control register for gpio25\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio25::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio25::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio25`] module"] +pub type GPIO25 = crate::Reg; +#[doc = "iomux control register for gpio25"] +pub mod gpio25; +#[doc = "gpio26 (rw) register accessor: iomux control register for gpio26\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio26::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio26::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio26`] module"] +pub type GPIO26 = crate::Reg; +#[doc = "iomux control register for gpio26"] +pub mod gpio26; +#[doc = "gpio27 (rw) register accessor: iomux control register for gpio27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio27::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio27::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio27`] module"] +pub type GPIO27 = crate::Reg; +#[doc = "iomux control register for gpio27"] +pub mod gpio27; +#[doc = "gpio28 (rw) register accessor: iomux control register for gpio28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio28::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio28::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio28`] module"] +pub type GPIO28 = crate::Reg; +#[doc = "iomux control register for gpio28"] +pub mod gpio28; +#[doc = "gpio29 (rw) register accessor: iomux control register for gpio29\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio29::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio29::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio29`] module"] +pub type GPIO29 = crate::Reg; +#[doc = "iomux control register for gpio29"] +pub mod gpio29; +#[doc = "gpio30 (rw) register accessor: iomux control register for gpio30\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio30::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio30::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio30`] module"] +pub type GPIO30 = crate::Reg; +#[doc = "iomux control register for gpio30"] +pub mod gpio30; +#[doc = "gpio31 (rw) register accessor: iomux control register for gpio31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio31::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio31::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio31`] module"] +pub type GPIO31 = crate::Reg; +#[doc = "iomux control register for gpio31"] +pub mod gpio31; +#[doc = "gpio32 (rw) register accessor: iomux control register for gpio32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio32::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio32::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio32`] module"] +pub type GPIO32 = crate::Reg; +#[doc = "iomux control register for gpio32"] +pub mod gpio32; +#[doc = "gpio33 (rw) register accessor: iomux control register for gpio33\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio33::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio33::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio33`] module"] +pub type GPIO33 = crate::Reg; +#[doc = "iomux control register for gpio33"] +pub mod gpio33; +#[doc = "gpio34 (rw) register accessor: iomux control register for gpio34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio34::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio34::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio34`] module"] +pub type GPIO34 = crate::Reg; +#[doc = "iomux control register for gpio34"] +pub mod gpio34; +#[doc = "gpio35 (rw) register accessor: iomux control register for gpio35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio35::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio35::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio35`] module"] +pub type GPIO35 = crate::Reg; +#[doc = "iomux control register for gpio35"] +pub mod gpio35; +#[doc = "gpio36 (rw) register accessor: iomux control register for gpio36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio36::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio36::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio36`] module"] +pub type GPIO36 = crate::Reg; +#[doc = "iomux control register for gpio36"] +pub mod gpio36; +#[doc = "gpio37 (rw) register accessor: iomux control register for gpio37\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio37::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio37::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio37`] module"] +pub type GPIO37 = crate::Reg; +#[doc = "iomux control register for gpio37"] +pub mod gpio37; +#[doc = "gpio38 (rw) register accessor: iomux control register for gpio38\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio38::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio38::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio38`] module"] +pub type GPIO38 = crate::Reg; +#[doc = "iomux control register for gpio38"] +pub mod gpio38; +#[doc = "gpio39 (rw) register accessor: iomux control register for gpio39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio39::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio39::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio39`] module"] +pub type GPIO39 = crate::Reg; +#[doc = "iomux control register for gpio39"] +pub mod gpio39; +#[doc = "gpio40 (rw) register accessor: iomux control register for gpio40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio40::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio40::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio40`] module"] +pub type GPIO40 = crate::Reg; +#[doc = "iomux control register for gpio40"] +pub mod gpio40; +#[doc = "gpio41 (rw) register accessor: iomux control register for gpio41\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio41::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio41::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio41`] module"] +pub type GPIO41 = crate::Reg; +#[doc = "iomux control register for gpio41"] +pub mod gpio41; +#[doc = "gpio42 (rw) register accessor: iomux control register for gpio42\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio42::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio42::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio42`] module"] +pub type GPIO42 = crate::Reg; +#[doc = "iomux control register for gpio42"] +pub mod gpio42; +#[doc = "gpio43 (rw) register accessor: iomux control register for gpio43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio43::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio43::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio43`] module"] +pub type GPIO43 = crate::Reg; +#[doc = "iomux control register for gpio43"] +pub mod gpio43; +#[doc = "gpio44 (rw) register accessor: iomux control register for gpio44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio44`] module"] +pub type GPIO44 = crate::Reg; +#[doc = "iomux control register for gpio44"] +pub mod gpio44; +#[doc = "gpio45 (rw) register accessor: iomux control register for gpio45\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio45::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio45::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio45`] module"] +pub type GPIO45 = crate::Reg; +#[doc = "iomux control register for gpio45"] +pub mod gpio45; +#[doc = "gpio46 (rw) register accessor: iomux control register for gpio46\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio46::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio46::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio46`] module"] +pub type GPIO46 = crate::Reg; +#[doc = "iomux control register for gpio46"] +pub mod gpio46; +#[doc = "gpio47 (rw) register accessor: iomux control register for gpio47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio47::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio47::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio47`] module"] +pub type GPIO47 = crate::Reg; +#[doc = "iomux control register for gpio47"] +pub mod gpio47; +#[doc = "gpio48 (rw) register accessor: iomux control register for gpio48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio48`] module"] +pub type GPIO48 = crate::Reg; +#[doc = "iomux control register for gpio48"] +pub mod gpio48; +#[doc = "gpio49 (rw) register accessor: iomux control register for gpio49\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio49::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio49::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio49`] module"] +pub type GPIO49 = crate::Reg; +#[doc = "iomux control register for gpio49"] +pub mod gpio49; +#[doc = "gpio50 (rw) register accessor: iomux control register for gpio50\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio50::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio50::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio50`] module"] +pub type GPIO50 = crate::Reg; +#[doc = "iomux control register for gpio50"] +pub mod gpio50; +#[doc = "gpio51 (rw) register accessor: iomux control register for gpio51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio51::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio51::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio51`] module"] +pub type GPIO51 = crate::Reg; +#[doc = "iomux control register for gpio51"] +pub mod gpio51; +#[doc = "gpio52 (rw) register accessor: iomux control register for gpio52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio52::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio52::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio52`] module"] +pub type GPIO52 = crate::Reg; +#[doc = "iomux control register for gpio52"] +pub mod gpio52; +#[doc = "gpio53 (rw) register accessor: iomux control register for gpio53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio53::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio53::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio53`] module"] +pub type GPIO53 = crate::Reg; +#[doc = "iomux control register for gpio53"] +pub mod gpio53; +#[doc = "gpio54 (rw) register accessor: iomux control register for gpio54\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio54::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio54::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio54`] module"] +pub type GPIO54 = crate::Reg; +#[doc = "iomux control register for gpio54"] +pub mod gpio54; +#[doc = "gpio55 (rw) register accessor: iomux control register for gpio55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio55::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio55::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio55`] module"] +pub type GPIO55 = crate::Reg; +#[doc = "iomux control register for gpio55"] +pub mod gpio55; +#[doc = "gpio56 (rw) register accessor: iomux control register for gpio56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio56::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio56::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio56`] module"] +pub type GPIO56 = crate::Reg; +#[doc = "iomux control register for gpio56"] +pub mod gpio56; +#[doc = "DATE (rw) register accessor: iomux version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "iomux version"] +pub mod date; diff --git a/esp32p4/src/io_mux/date.rs b/esp32p4/src/io_mux/date.rs new file mode 100644 index 0000000000..9d91015dce --- /dev/null +++ b/esp32p4/src/io_mux/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - csv date"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - csv date"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - csv date"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - csv date"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux version\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0020_1222"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0020_1222; +} diff --git a/esp32p4/src/io_mux/gpio0.rs b/esp32p4/src/io_mux/gpio0.rs new file mode 100644 index 0000000000..9444ab9fc7 --- /dev/null +++ b/esp32p4/src/io_mux/gpio0.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio0` reader"] +pub type R = crate::R; +#[doc = "Register `gpio0` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO0_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO0_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO0_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO0_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO0_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO0_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO0_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO0_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO0_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO0_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO0_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO0_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO0_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO0_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO0_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO0_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO0_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO0_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO0_FUN_WPD` reader - pull-down enable"] +pub type GPIO0_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO0_FUN_WPD` writer - pull-down enable"] +pub type GPIO0_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_FUN_WPU` reader - pull-up enable"] +pub type GPIO0_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO0_FUN_WPU` writer - pull-up enable"] +pub type GPIO0_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_FUN_IE` reader - input enable"] +pub type GPIO0_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO0_FUN_IE` writer - input enable"] +pub type GPIO0_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO0_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO0_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO0_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO0_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO0_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO0_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO0_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO0_FILTER_EN` reader - input filter enable"] +pub type GPIO0_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO0_FILTER_EN` writer - input filter enable"] +pub type GPIO0_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio0_mcu_oe(&self) -> GPIO0_MCU_OE_R { + GPIO0_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio0_slp_sel(&self) -> GPIO0_SLP_SEL_R { + GPIO0_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio0_mcu_wpd(&self) -> GPIO0_MCU_WPD_R { + GPIO0_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio0_mcu_wpu(&self) -> GPIO0_MCU_WPU_R { + GPIO0_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio0_mcu_ie(&self) -> GPIO0_MCU_IE_R { + GPIO0_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio0_mcu_drv(&self) -> GPIO0_MCU_DRV_R { + GPIO0_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio0_fun_wpd(&self) -> GPIO0_FUN_WPD_R { + GPIO0_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio0_fun_wpu(&self) -> GPIO0_FUN_WPU_R { + GPIO0_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio0_fun_ie(&self) -> GPIO0_FUN_IE_R { + GPIO0_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio0_fun_drv(&self) -> GPIO0_FUN_DRV_R { + GPIO0_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio0_mcu_sel(&self) -> GPIO0_MCU_SEL_R { + GPIO0_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio0_filter_en(&self) -> GPIO0_FILTER_EN_R { + GPIO0_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio0") + .field( + "gpio0_mcu_oe", + &format_args!("{}", self.gpio0_mcu_oe().bit()), + ) + .field( + "gpio0_slp_sel", + &format_args!("{}", self.gpio0_slp_sel().bit()), + ) + .field( + "gpio0_mcu_wpd", + &format_args!("{}", self.gpio0_mcu_wpd().bit()), + ) + .field( + "gpio0_mcu_wpu", + &format_args!("{}", self.gpio0_mcu_wpu().bit()), + ) + .field( + "gpio0_mcu_ie", + &format_args!("{}", self.gpio0_mcu_ie().bit()), + ) + .field( + "gpio0_mcu_drv", + &format_args!("{}", self.gpio0_mcu_drv().bits()), + ) + .field( + "gpio0_fun_wpd", + &format_args!("{}", self.gpio0_fun_wpd().bit()), + ) + .field( + "gpio0_fun_wpu", + &format_args!("{}", self.gpio0_fun_wpu().bit()), + ) + .field( + "gpio0_fun_ie", + &format_args!("{}", self.gpio0_fun_ie().bit()), + ) + .field( + "gpio0_fun_drv", + &format_args!("{}", self.gpio0_fun_drv().bits()), + ) + .field( + "gpio0_mcu_sel", + &format_args!("{}", self.gpio0_mcu_sel().bits()), + ) + .field( + "gpio0_filter_en", + &format_args!("{}", self.gpio0_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio0_mcu_oe(&mut self) -> GPIO0_MCU_OE_W { + GPIO0_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio0_slp_sel(&mut self) -> GPIO0_SLP_SEL_W { + GPIO0_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio0_mcu_wpd(&mut self) -> GPIO0_MCU_WPD_W { + GPIO0_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio0_mcu_wpu(&mut self) -> GPIO0_MCU_WPU_W { + GPIO0_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio0_mcu_ie(&mut self) -> GPIO0_MCU_IE_W { + GPIO0_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio0_mcu_drv(&mut self) -> GPIO0_MCU_DRV_W { + GPIO0_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio0_fun_wpd(&mut self) -> GPIO0_FUN_WPD_W { + GPIO0_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio0_fun_wpu(&mut self) -> GPIO0_FUN_WPU_W { + GPIO0_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio0_fun_ie(&mut self) -> GPIO0_FUN_IE_W { + GPIO0_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio0_fun_drv(&mut self) -> GPIO0_FUN_DRV_W { + GPIO0_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio0_mcu_sel(&mut self) -> GPIO0_MCU_SEL_W { + GPIO0_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio0_filter_en(&mut self) -> GPIO0_FILTER_EN_W { + GPIO0_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO0_SPEC; +impl crate::RegisterSpec for GPIO0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio0::R`](R) reader structure"] +impl crate::Readable for GPIO0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio0::W`](W) writer structure"] +impl crate::Writable for GPIO0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio0 to value 0x0800"] +impl crate::Resettable for GPIO0_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio1.rs b/esp32p4/src/io_mux/gpio1.rs new file mode 100644 index 0000000000..4346046157 --- /dev/null +++ b/esp32p4/src/io_mux/gpio1.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio1` reader"] +pub type R = crate::R; +#[doc = "Register `gpio1` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO1_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO1_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO1_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO1_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO1_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO1_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO1_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO1_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO1_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO1_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO1_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO1_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO1_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO1_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO1_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO1_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO1_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO1_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO1_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO1_FUN_WPD` reader - pull-down enable"] +pub type GPIO1_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO1_FUN_WPD` writer - pull-down enable"] +pub type GPIO1_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_FUN_WPU` reader - pull-up enable"] +pub type GPIO1_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO1_FUN_WPU` writer - pull-up enable"] +pub type GPIO1_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_FUN_IE` reader - input enable"] +pub type GPIO1_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO1_FUN_IE` writer - input enable"] +pub type GPIO1_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO1_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO1_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO1_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO1_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO1_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO1_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO1_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO1_FILTER_EN` reader - input filter enable"] +pub type GPIO1_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO1_FILTER_EN` writer - input filter enable"] +pub type GPIO1_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio1_mcu_oe(&self) -> GPIO1_MCU_OE_R { + GPIO1_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio1_slp_sel(&self) -> GPIO1_SLP_SEL_R { + GPIO1_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio1_mcu_wpd(&self) -> GPIO1_MCU_WPD_R { + GPIO1_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio1_mcu_wpu(&self) -> GPIO1_MCU_WPU_R { + GPIO1_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio1_mcu_ie(&self) -> GPIO1_MCU_IE_R { + GPIO1_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio1_mcu_drv(&self) -> GPIO1_MCU_DRV_R { + GPIO1_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio1_fun_wpd(&self) -> GPIO1_FUN_WPD_R { + GPIO1_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio1_fun_wpu(&self) -> GPIO1_FUN_WPU_R { + GPIO1_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio1_fun_ie(&self) -> GPIO1_FUN_IE_R { + GPIO1_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio1_fun_drv(&self) -> GPIO1_FUN_DRV_R { + GPIO1_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio1_mcu_sel(&self) -> GPIO1_MCU_SEL_R { + GPIO1_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio1_filter_en(&self) -> GPIO1_FILTER_EN_R { + GPIO1_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio1") + .field( + "gpio1_mcu_oe", + &format_args!("{}", self.gpio1_mcu_oe().bit()), + ) + .field( + "gpio1_slp_sel", + &format_args!("{}", self.gpio1_slp_sel().bit()), + ) + .field( + "gpio1_mcu_wpd", + &format_args!("{}", self.gpio1_mcu_wpd().bit()), + ) + .field( + "gpio1_mcu_wpu", + &format_args!("{}", self.gpio1_mcu_wpu().bit()), + ) + .field( + "gpio1_mcu_ie", + &format_args!("{}", self.gpio1_mcu_ie().bit()), + ) + .field( + "gpio1_mcu_drv", + &format_args!("{}", self.gpio1_mcu_drv().bits()), + ) + .field( + "gpio1_fun_wpd", + &format_args!("{}", self.gpio1_fun_wpd().bit()), + ) + .field( + "gpio1_fun_wpu", + &format_args!("{}", self.gpio1_fun_wpu().bit()), + ) + .field( + "gpio1_fun_ie", + &format_args!("{}", self.gpio1_fun_ie().bit()), + ) + .field( + "gpio1_fun_drv", + &format_args!("{}", self.gpio1_fun_drv().bits()), + ) + .field( + "gpio1_mcu_sel", + &format_args!("{}", self.gpio1_mcu_sel().bits()), + ) + .field( + "gpio1_filter_en", + &format_args!("{}", self.gpio1_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio1_mcu_oe(&mut self) -> GPIO1_MCU_OE_W { + GPIO1_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio1_slp_sel(&mut self) -> GPIO1_SLP_SEL_W { + GPIO1_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio1_mcu_wpd(&mut self) -> GPIO1_MCU_WPD_W { + GPIO1_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio1_mcu_wpu(&mut self) -> GPIO1_MCU_WPU_W { + GPIO1_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio1_mcu_ie(&mut self) -> GPIO1_MCU_IE_W { + GPIO1_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio1_mcu_drv(&mut self) -> GPIO1_MCU_DRV_W { + GPIO1_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio1_fun_wpd(&mut self) -> GPIO1_FUN_WPD_W { + GPIO1_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio1_fun_wpu(&mut self) -> GPIO1_FUN_WPU_W { + GPIO1_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio1_fun_ie(&mut self) -> GPIO1_FUN_IE_W { + GPIO1_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio1_fun_drv(&mut self) -> GPIO1_FUN_DRV_W { + GPIO1_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio1_mcu_sel(&mut self) -> GPIO1_MCU_SEL_W { + GPIO1_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio1_filter_en(&mut self) -> GPIO1_FILTER_EN_W { + GPIO1_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO1_SPEC; +impl crate::RegisterSpec for GPIO1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio1::R`](R) reader structure"] +impl crate::Readable for GPIO1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio1::W`](W) writer structure"] +impl crate::Writable for GPIO1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio1 to value 0x0800"] +impl crate::Resettable for GPIO1_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio10.rs b/esp32p4/src/io_mux/gpio10.rs new file mode 100644 index 0000000000..fe79cc580d --- /dev/null +++ b/esp32p4/src/io_mux/gpio10.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio10` reader"] +pub type R = crate::R; +#[doc = "Register `gpio10` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO10_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO10_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO10_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO10_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO10_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO10_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO10_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO10_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO10_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO10_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO10_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO10_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO10_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO10_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO10_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO10_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO10_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO10_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO10_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO10_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO10_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO10_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO10_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO10_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO10_FUN_WPD` reader - pull-down enable"] +pub type GPIO10_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO10_FUN_WPD` writer - pull-down enable"] +pub type GPIO10_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO10_FUN_WPU` reader - pull-up enable"] +pub type GPIO10_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO10_FUN_WPU` writer - pull-up enable"] +pub type GPIO10_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO10_FUN_IE` reader - input enable"] +pub type GPIO10_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO10_FUN_IE` writer - input enable"] +pub type GPIO10_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO10_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO10_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO10_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO10_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO10_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO10_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO10_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO10_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO10_FILTER_EN` reader - input filter enable"] +pub type GPIO10_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO10_FILTER_EN` writer - input filter enable"] +pub type GPIO10_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio10_mcu_oe(&self) -> GPIO10_MCU_OE_R { + GPIO10_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio10_slp_sel(&self) -> GPIO10_SLP_SEL_R { + GPIO10_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio10_mcu_wpd(&self) -> GPIO10_MCU_WPD_R { + GPIO10_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio10_mcu_wpu(&self) -> GPIO10_MCU_WPU_R { + GPIO10_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio10_mcu_ie(&self) -> GPIO10_MCU_IE_R { + GPIO10_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio10_mcu_drv(&self) -> GPIO10_MCU_DRV_R { + GPIO10_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio10_fun_wpd(&self) -> GPIO10_FUN_WPD_R { + GPIO10_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio10_fun_wpu(&self) -> GPIO10_FUN_WPU_R { + GPIO10_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio10_fun_ie(&self) -> GPIO10_FUN_IE_R { + GPIO10_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio10_fun_drv(&self) -> GPIO10_FUN_DRV_R { + GPIO10_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio10_mcu_sel(&self) -> GPIO10_MCU_SEL_R { + GPIO10_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio10_filter_en(&self) -> GPIO10_FILTER_EN_R { + GPIO10_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio10") + .field( + "gpio10_mcu_oe", + &format_args!("{}", self.gpio10_mcu_oe().bit()), + ) + .field( + "gpio10_slp_sel", + &format_args!("{}", self.gpio10_slp_sel().bit()), + ) + .field( + "gpio10_mcu_wpd", + &format_args!("{}", self.gpio10_mcu_wpd().bit()), + ) + .field( + "gpio10_mcu_wpu", + &format_args!("{}", self.gpio10_mcu_wpu().bit()), + ) + .field( + "gpio10_mcu_ie", + &format_args!("{}", self.gpio10_mcu_ie().bit()), + ) + .field( + "gpio10_mcu_drv", + &format_args!("{}", self.gpio10_mcu_drv().bits()), + ) + .field( + "gpio10_fun_wpd", + &format_args!("{}", self.gpio10_fun_wpd().bit()), + ) + .field( + "gpio10_fun_wpu", + &format_args!("{}", self.gpio10_fun_wpu().bit()), + ) + .field( + "gpio10_fun_ie", + &format_args!("{}", self.gpio10_fun_ie().bit()), + ) + .field( + "gpio10_fun_drv", + &format_args!("{}", self.gpio10_fun_drv().bits()), + ) + .field( + "gpio10_mcu_sel", + &format_args!("{}", self.gpio10_mcu_sel().bits()), + ) + .field( + "gpio10_filter_en", + &format_args!("{}", self.gpio10_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio10_mcu_oe(&mut self) -> GPIO10_MCU_OE_W { + GPIO10_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio10_slp_sel(&mut self) -> GPIO10_SLP_SEL_W { + GPIO10_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio10_mcu_wpd(&mut self) -> GPIO10_MCU_WPD_W { + GPIO10_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio10_mcu_wpu(&mut self) -> GPIO10_MCU_WPU_W { + GPIO10_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio10_mcu_ie(&mut self) -> GPIO10_MCU_IE_W { + GPIO10_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio10_mcu_drv(&mut self) -> GPIO10_MCU_DRV_W { + GPIO10_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio10_fun_wpd(&mut self) -> GPIO10_FUN_WPD_W { + GPIO10_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio10_fun_wpu(&mut self) -> GPIO10_FUN_WPU_W { + GPIO10_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio10_fun_ie(&mut self) -> GPIO10_FUN_IE_W { + GPIO10_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio10_fun_drv(&mut self) -> GPIO10_FUN_DRV_W { + GPIO10_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio10_mcu_sel(&mut self) -> GPIO10_MCU_SEL_W { + GPIO10_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio10_filter_en(&mut self) -> GPIO10_FILTER_EN_W { + GPIO10_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO10_SPEC; +impl crate::RegisterSpec for GPIO10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio10::R`](R) reader structure"] +impl crate::Readable for GPIO10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio10::W`](W) writer structure"] +impl crate::Writable for GPIO10_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio10 to value 0x0800"] +impl crate::Resettable for GPIO10_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio11.rs b/esp32p4/src/io_mux/gpio11.rs new file mode 100644 index 0000000000..a1de807422 --- /dev/null +++ b/esp32p4/src/io_mux/gpio11.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio11` reader"] +pub type R = crate::R; +#[doc = "Register `gpio11` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO11_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO11_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO11_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO11_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO11_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO11_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO11_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO11_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO11_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO11_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO11_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO11_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO11_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO11_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO11_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO11_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO11_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO11_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO11_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO11_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO11_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO11_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO11_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO11_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO11_FUN_WPD` reader - pull-down enable"] +pub type GPIO11_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO11_FUN_WPD` writer - pull-down enable"] +pub type GPIO11_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO11_FUN_WPU` reader - pull-up enable"] +pub type GPIO11_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO11_FUN_WPU` writer - pull-up enable"] +pub type GPIO11_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO11_FUN_IE` reader - input enable"] +pub type GPIO11_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO11_FUN_IE` writer - input enable"] +pub type GPIO11_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO11_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO11_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO11_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO11_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO11_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO11_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO11_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO11_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO11_FILTER_EN` reader - input filter enable"] +pub type GPIO11_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO11_FILTER_EN` writer - input filter enable"] +pub type GPIO11_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio11_mcu_oe(&self) -> GPIO11_MCU_OE_R { + GPIO11_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio11_slp_sel(&self) -> GPIO11_SLP_SEL_R { + GPIO11_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio11_mcu_wpd(&self) -> GPIO11_MCU_WPD_R { + GPIO11_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio11_mcu_wpu(&self) -> GPIO11_MCU_WPU_R { + GPIO11_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio11_mcu_ie(&self) -> GPIO11_MCU_IE_R { + GPIO11_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio11_mcu_drv(&self) -> GPIO11_MCU_DRV_R { + GPIO11_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio11_fun_wpd(&self) -> GPIO11_FUN_WPD_R { + GPIO11_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio11_fun_wpu(&self) -> GPIO11_FUN_WPU_R { + GPIO11_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio11_fun_ie(&self) -> GPIO11_FUN_IE_R { + GPIO11_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio11_fun_drv(&self) -> GPIO11_FUN_DRV_R { + GPIO11_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio11_mcu_sel(&self) -> GPIO11_MCU_SEL_R { + GPIO11_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio11_filter_en(&self) -> GPIO11_FILTER_EN_R { + GPIO11_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio11") + .field( + "gpio11_mcu_oe", + &format_args!("{}", self.gpio11_mcu_oe().bit()), + ) + .field( + "gpio11_slp_sel", + &format_args!("{}", self.gpio11_slp_sel().bit()), + ) + .field( + "gpio11_mcu_wpd", + &format_args!("{}", self.gpio11_mcu_wpd().bit()), + ) + .field( + "gpio11_mcu_wpu", + &format_args!("{}", self.gpio11_mcu_wpu().bit()), + ) + .field( + "gpio11_mcu_ie", + &format_args!("{}", self.gpio11_mcu_ie().bit()), + ) + .field( + "gpio11_mcu_drv", + &format_args!("{}", self.gpio11_mcu_drv().bits()), + ) + .field( + "gpio11_fun_wpd", + &format_args!("{}", self.gpio11_fun_wpd().bit()), + ) + .field( + "gpio11_fun_wpu", + &format_args!("{}", self.gpio11_fun_wpu().bit()), + ) + .field( + "gpio11_fun_ie", + &format_args!("{}", self.gpio11_fun_ie().bit()), + ) + .field( + "gpio11_fun_drv", + &format_args!("{}", self.gpio11_fun_drv().bits()), + ) + .field( + "gpio11_mcu_sel", + &format_args!("{}", self.gpio11_mcu_sel().bits()), + ) + .field( + "gpio11_filter_en", + &format_args!("{}", self.gpio11_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio11_mcu_oe(&mut self) -> GPIO11_MCU_OE_W { + GPIO11_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio11_slp_sel(&mut self) -> GPIO11_SLP_SEL_W { + GPIO11_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio11_mcu_wpd(&mut self) -> GPIO11_MCU_WPD_W { + GPIO11_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio11_mcu_wpu(&mut self) -> GPIO11_MCU_WPU_W { + GPIO11_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio11_mcu_ie(&mut self) -> GPIO11_MCU_IE_W { + GPIO11_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio11_mcu_drv(&mut self) -> GPIO11_MCU_DRV_W { + GPIO11_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio11_fun_wpd(&mut self) -> GPIO11_FUN_WPD_W { + GPIO11_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio11_fun_wpu(&mut self) -> GPIO11_FUN_WPU_W { + GPIO11_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio11_fun_ie(&mut self) -> GPIO11_FUN_IE_W { + GPIO11_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio11_fun_drv(&mut self) -> GPIO11_FUN_DRV_W { + GPIO11_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio11_mcu_sel(&mut self) -> GPIO11_MCU_SEL_W { + GPIO11_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio11_filter_en(&mut self) -> GPIO11_FILTER_EN_W { + GPIO11_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO11_SPEC; +impl crate::RegisterSpec for GPIO11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio11::R`](R) reader structure"] +impl crate::Readable for GPIO11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio11::W`](W) writer structure"] +impl crate::Writable for GPIO11_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio11 to value 0x0800"] +impl crate::Resettable for GPIO11_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio12.rs b/esp32p4/src/io_mux/gpio12.rs new file mode 100644 index 0000000000..453d72545c --- /dev/null +++ b/esp32p4/src/io_mux/gpio12.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio12` reader"] +pub type R = crate::R; +#[doc = "Register `gpio12` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO12_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO12_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO12_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO12_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO12_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO12_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO12_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO12_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO12_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO12_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO12_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO12_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO12_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO12_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO12_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO12_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO12_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO12_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO12_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO12_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO12_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO12_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO12_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO12_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO12_FUN_WPD` reader - pull-down enable"] +pub type GPIO12_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO12_FUN_WPD` writer - pull-down enable"] +pub type GPIO12_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO12_FUN_WPU` reader - pull-up enable"] +pub type GPIO12_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO12_FUN_WPU` writer - pull-up enable"] +pub type GPIO12_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO12_FUN_IE` reader - input enable"] +pub type GPIO12_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO12_FUN_IE` writer - input enable"] +pub type GPIO12_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO12_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO12_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO12_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO12_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO12_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO12_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO12_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO12_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO12_FILTER_EN` reader - input filter enable"] +pub type GPIO12_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO12_FILTER_EN` writer - input filter enable"] +pub type GPIO12_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio12_mcu_oe(&self) -> GPIO12_MCU_OE_R { + GPIO12_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio12_slp_sel(&self) -> GPIO12_SLP_SEL_R { + GPIO12_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio12_mcu_wpd(&self) -> GPIO12_MCU_WPD_R { + GPIO12_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio12_mcu_wpu(&self) -> GPIO12_MCU_WPU_R { + GPIO12_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio12_mcu_ie(&self) -> GPIO12_MCU_IE_R { + GPIO12_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio12_mcu_drv(&self) -> GPIO12_MCU_DRV_R { + GPIO12_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio12_fun_wpd(&self) -> GPIO12_FUN_WPD_R { + GPIO12_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio12_fun_wpu(&self) -> GPIO12_FUN_WPU_R { + GPIO12_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio12_fun_ie(&self) -> GPIO12_FUN_IE_R { + GPIO12_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio12_fun_drv(&self) -> GPIO12_FUN_DRV_R { + GPIO12_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio12_mcu_sel(&self) -> GPIO12_MCU_SEL_R { + GPIO12_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio12_filter_en(&self) -> GPIO12_FILTER_EN_R { + GPIO12_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio12") + .field( + "gpio12_mcu_oe", + &format_args!("{}", self.gpio12_mcu_oe().bit()), + ) + .field( + "gpio12_slp_sel", + &format_args!("{}", self.gpio12_slp_sel().bit()), + ) + .field( + "gpio12_mcu_wpd", + &format_args!("{}", self.gpio12_mcu_wpd().bit()), + ) + .field( + "gpio12_mcu_wpu", + &format_args!("{}", self.gpio12_mcu_wpu().bit()), + ) + .field( + "gpio12_mcu_ie", + &format_args!("{}", self.gpio12_mcu_ie().bit()), + ) + .field( + "gpio12_mcu_drv", + &format_args!("{}", self.gpio12_mcu_drv().bits()), + ) + .field( + "gpio12_fun_wpd", + &format_args!("{}", self.gpio12_fun_wpd().bit()), + ) + .field( + "gpio12_fun_wpu", + &format_args!("{}", self.gpio12_fun_wpu().bit()), + ) + .field( + "gpio12_fun_ie", + &format_args!("{}", self.gpio12_fun_ie().bit()), + ) + .field( + "gpio12_fun_drv", + &format_args!("{}", self.gpio12_fun_drv().bits()), + ) + .field( + "gpio12_mcu_sel", + &format_args!("{}", self.gpio12_mcu_sel().bits()), + ) + .field( + "gpio12_filter_en", + &format_args!("{}", self.gpio12_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio12_mcu_oe(&mut self) -> GPIO12_MCU_OE_W { + GPIO12_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio12_slp_sel(&mut self) -> GPIO12_SLP_SEL_W { + GPIO12_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio12_mcu_wpd(&mut self) -> GPIO12_MCU_WPD_W { + GPIO12_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio12_mcu_wpu(&mut self) -> GPIO12_MCU_WPU_W { + GPIO12_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio12_mcu_ie(&mut self) -> GPIO12_MCU_IE_W { + GPIO12_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio12_mcu_drv(&mut self) -> GPIO12_MCU_DRV_W { + GPIO12_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio12_fun_wpd(&mut self) -> GPIO12_FUN_WPD_W { + GPIO12_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio12_fun_wpu(&mut self) -> GPIO12_FUN_WPU_W { + GPIO12_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio12_fun_ie(&mut self) -> GPIO12_FUN_IE_W { + GPIO12_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio12_fun_drv(&mut self) -> GPIO12_FUN_DRV_W { + GPIO12_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio12_mcu_sel(&mut self) -> GPIO12_MCU_SEL_W { + GPIO12_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio12_filter_en(&mut self) -> GPIO12_FILTER_EN_W { + GPIO12_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO12_SPEC; +impl crate::RegisterSpec for GPIO12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio12::R`](R) reader structure"] +impl crate::Readable for GPIO12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio12::W`](W) writer structure"] +impl crate::Writable for GPIO12_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio12 to value 0x0800"] +impl crate::Resettable for GPIO12_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio13.rs b/esp32p4/src/io_mux/gpio13.rs new file mode 100644 index 0000000000..f0a39d0a42 --- /dev/null +++ b/esp32p4/src/io_mux/gpio13.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio13` reader"] +pub type R = crate::R; +#[doc = "Register `gpio13` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO13_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO13_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO13_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO13_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO13_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO13_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO13_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO13_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO13_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO13_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO13_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO13_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO13_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO13_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO13_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO13_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO13_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO13_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO13_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO13_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO13_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO13_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO13_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO13_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO13_FUN_WPD` reader - pull-down enable"] +pub type GPIO13_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO13_FUN_WPD` writer - pull-down enable"] +pub type GPIO13_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO13_FUN_WPU` reader - pull-up enable"] +pub type GPIO13_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO13_FUN_WPU` writer - pull-up enable"] +pub type GPIO13_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO13_FUN_IE` reader - input enable"] +pub type GPIO13_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO13_FUN_IE` writer - input enable"] +pub type GPIO13_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO13_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO13_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO13_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO13_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO13_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO13_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO13_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO13_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO13_FILTER_EN` reader - input filter enable"] +pub type GPIO13_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO13_FILTER_EN` writer - input filter enable"] +pub type GPIO13_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio13_mcu_oe(&self) -> GPIO13_MCU_OE_R { + GPIO13_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio13_slp_sel(&self) -> GPIO13_SLP_SEL_R { + GPIO13_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio13_mcu_wpd(&self) -> GPIO13_MCU_WPD_R { + GPIO13_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio13_mcu_wpu(&self) -> GPIO13_MCU_WPU_R { + GPIO13_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio13_mcu_ie(&self) -> GPIO13_MCU_IE_R { + GPIO13_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio13_mcu_drv(&self) -> GPIO13_MCU_DRV_R { + GPIO13_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio13_fun_wpd(&self) -> GPIO13_FUN_WPD_R { + GPIO13_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio13_fun_wpu(&self) -> GPIO13_FUN_WPU_R { + GPIO13_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio13_fun_ie(&self) -> GPIO13_FUN_IE_R { + GPIO13_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio13_fun_drv(&self) -> GPIO13_FUN_DRV_R { + GPIO13_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio13_mcu_sel(&self) -> GPIO13_MCU_SEL_R { + GPIO13_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio13_filter_en(&self) -> GPIO13_FILTER_EN_R { + GPIO13_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio13") + .field( + "gpio13_mcu_oe", + &format_args!("{}", self.gpio13_mcu_oe().bit()), + ) + .field( + "gpio13_slp_sel", + &format_args!("{}", self.gpio13_slp_sel().bit()), + ) + .field( + "gpio13_mcu_wpd", + &format_args!("{}", self.gpio13_mcu_wpd().bit()), + ) + .field( + "gpio13_mcu_wpu", + &format_args!("{}", self.gpio13_mcu_wpu().bit()), + ) + .field( + "gpio13_mcu_ie", + &format_args!("{}", self.gpio13_mcu_ie().bit()), + ) + .field( + "gpio13_mcu_drv", + &format_args!("{}", self.gpio13_mcu_drv().bits()), + ) + .field( + "gpio13_fun_wpd", + &format_args!("{}", self.gpio13_fun_wpd().bit()), + ) + .field( + "gpio13_fun_wpu", + &format_args!("{}", self.gpio13_fun_wpu().bit()), + ) + .field( + "gpio13_fun_ie", + &format_args!("{}", self.gpio13_fun_ie().bit()), + ) + .field( + "gpio13_fun_drv", + &format_args!("{}", self.gpio13_fun_drv().bits()), + ) + .field( + "gpio13_mcu_sel", + &format_args!("{}", self.gpio13_mcu_sel().bits()), + ) + .field( + "gpio13_filter_en", + &format_args!("{}", self.gpio13_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio13_mcu_oe(&mut self) -> GPIO13_MCU_OE_W { + GPIO13_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio13_slp_sel(&mut self) -> GPIO13_SLP_SEL_W { + GPIO13_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio13_mcu_wpd(&mut self) -> GPIO13_MCU_WPD_W { + GPIO13_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio13_mcu_wpu(&mut self) -> GPIO13_MCU_WPU_W { + GPIO13_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio13_mcu_ie(&mut self) -> GPIO13_MCU_IE_W { + GPIO13_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio13_mcu_drv(&mut self) -> GPIO13_MCU_DRV_W { + GPIO13_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio13_fun_wpd(&mut self) -> GPIO13_FUN_WPD_W { + GPIO13_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio13_fun_wpu(&mut self) -> GPIO13_FUN_WPU_W { + GPIO13_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio13_fun_ie(&mut self) -> GPIO13_FUN_IE_W { + GPIO13_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio13_fun_drv(&mut self) -> GPIO13_FUN_DRV_W { + GPIO13_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio13_mcu_sel(&mut self) -> GPIO13_MCU_SEL_W { + GPIO13_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio13_filter_en(&mut self) -> GPIO13_FILTER_EN_W { + GPIO13_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO13_SPEC; +impl crate::RegisterSpec for GPIO13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio13::R`](R) reader structure"] +impl crate::Readable for GPIO13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio13::W`](W) writer structure"] +impl crate::Writable for GPIO13_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio13 to value 0x0800"] +impl crate::Resettable for GPIO13_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio14.rs b/esp32p4/src/io_mux/gpio14.rs new file mode 100644 index 0000000000..b8393c0e27 --- /dev/null +++ b/esp32p4/src/io_mux/gpio14.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio14` reader"] +pub type R = crate::R; +#[doc = "Register `gpio14` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO14_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO14_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO14_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO14_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO14_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO14_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO14_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO14_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO14_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO14_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO14_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO14_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO14_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO14_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO14_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO14_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO14_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO14_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO14_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO14_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO14_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO14_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO14_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO14_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO14_FUN_WPD` reader - pull-down enable"] +pub type GPIO14_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO14_FUN_WPD` writer - pull-down enable"] +pub type GPIO14_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO14_FUN_WPU` reader - pull-up enable"] +pub type GPIO14_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO14_FUN_WPU` writer - pull-up enable"] +pub type GPIO14_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO14_FUN_IE` reader - input enable"] +pub type GPIO14_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO14_FUN_IE` writer - input enable"] +pub type GPIO14_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO14_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO14_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO14_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO14_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO14_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO14_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO14_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO14_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO14_FILTER_EN` reader - input filter enable"] +pub type GPIO14_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO14_FILTER_EN` writer - input filter enable"] +pub type GPIO14_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio14_mcu_oe(&self) -> GPIO14_MCU_OE_R { + GPIO14_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio14_slp_sel(&self) -> GPIO14_SLP_SEL_R { + GPIO14_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio14_mcu_wpd(&self) -> GPIO14_MCU_WPD_R { + GPIO14_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio14_mcu_wpu(&self) -> GPIO14_MCU_WPU_R { + GPIO14_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio14_mcu_ie(&self) -> GPIO14_MCU_IE_R { + GPIO14_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio14_mcu_drv(&self) -> GPIO14_MCU_DRV_R { + GPIO14_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio14_fun_wpd(&self) -> GPIO14_FUN_WPD_R { + GPIO14_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio14_fun_wpu(&self) -> GPIO14_FUN_WPU_R { + GPIO14_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio14_fun_ie(&self) -> GPIO14_FUN_IE_R { + GPIO14_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio14_fun_drv(&self) -> GPIO14_FUN_DRV_R { + GPIO14_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio14_mcu_sel(&self) -> GPIO14_MCU_SEL_R { + GPIO14_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio14_filter_en(&self) -> GPIO14_FILTER_EN_R { + GPIO14_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio14") + .field( + "gpio14_mcu_oe", + &format_args!("{}", self.gpio14_mcu_oe().bit()), + ) + .field( + "gpio14_slp_sel", + &format_args!("{}", self.gpio14_slp_sel().bit()), + ) + .field( + "gpio14_mcu_wpd", + &format_args!("{}", self.gpio14_mcu_wpd().bit()), + ) + .field( + "gpio14_mcu_wpu", + &format_args!("{}", self.gpio14_mcu_wpu().bit()), + ) + .field( + "gpio14_mcu_ie", + &format_args!("{}", self.gpio14_mcu_ie().bit()), + ) + .field( + "gpio14_mcu_drv", + &format_args!("{}", self.gpio14_mcu_drv().bits()), + ) + .field( + "gpio14_fun_wpd", + &format_args!("{}", self.gpio14_fun_wpd().bit()), + ) + .field( + "gpio14_fun_wpu", + &format_args!("{}", self.gpio14_fun_wpu().bit()), + ) + .field( + "gpio14_fun_ie", + &format_args!("{}", self.gpio14_fun_ie().bit()), + ) + .field( + "gpio14_fun_drv", + &format_args!("{}", self.gpio14_fun_drv().bits()), + ) + .field( + "gpio14_mcu_sel", + &format_args!("{}", self.gpio14_mcu_sel().bits()), + ) + .field( + "gpio14_filter_en", + &format_args!("{}", self.gpio14_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio14_mcu_oe(&mut self) -> GPIO14_MCU_OE_W { + GPIO14_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio14_slp_sel(&mut self) -> GPIO14_SLP_SEL_W { + GPIO14_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio14_mcu_wpd(&mut self) -> GPIO14_MCU_WPD_W { + GPIO14_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio14_mcu_wpu(&mut self) -> GPIO14_MCU_WPU_W { + GPIO14_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio14_mcu_ie(&mut self) -> GPIO14_MCU_IE_W { + GPIO14_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio14_mcu_drv(&mut self) -> GPIO14_MCU_DRV_W { + GPIO14_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio14_fun_wpd(&mut self) -> GPIO14_FUN_WPD_W { + GPIO14_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio14_fun_wpu(&mut self) -> GPIO14_FUN_WPU_W { + GPIO14_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio14_fun_ie(&mut self) -> GPIO14_FUN_IE_W { + GPIO14_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio14_fun_drv(&mut self) -> GPIO14_FUN_DRV_W { + GPIO14_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio14_mcu_sel(&mut self) -> GPIO14_MCU_SEL_W { + GPIO14_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio14_filter_en(&mut self) -> GPIO14_FILTER_EN_W { + GPIO14_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO14_SPEC; +impl crate::RegisterSpec for GPIO14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio14::R`](R) reader structure"] +impl crate::Readable for GPIO14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio14::W`](W) writer structure"] +impl crate::Writable for GPIO14_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio14 to value 0x0800"] +impl crate::Resettable for GPIO14_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio15.rs b/esp32p4/src/io_mux/gpio15.rs new file mode 100644 index 0000000000..e6ea5ce338 --- /dev/null +++ b/esp32p4/src/io_mux/gpio15.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio15` reader"] +pub type R = crate::R; +#[doc = "Register `gpio15` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO15_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO15_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO15_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO15_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO15_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO15_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO15_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO15_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO15_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO15_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO15_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO15_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO15_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO15_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO15_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO15_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO15_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO15_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO15_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO15_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO15_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO15_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO15_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO15_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO15_FUN_WPD` reader - pull-down enable"] +pub type GPIO15_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO15_FUN_WPD` writer - pull-down enable"] +pub type GPIO15_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO15_FUN_WPU` reader - pull-up enable"] +pub type GPIO15_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO15_FUN_WPU` writer - pull-up enable"] +pub type GPIO15_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO15_FUN_IE` reader - input enable"] +pub type GPIO15_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO15_FUN_IE` writer - input enable"] +pub type GPIO15_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO15_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO15_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO15_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO15_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO15_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO15_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO15_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO15_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO15_FILTER_EN` reader - input filter enable"] +pub type GPIO15_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO15_FILTER_EN` writer - input filter enable"] +pub type GPIO15_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio15_mcu_oe(&self) -> GPIO15_MCU_OE_R { + GPIO15_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio15_slp_sel(&self) -> GPIO15_SLP_SEL_R { + GPIO15_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio15_mcu_wpd(&self) -> GPIO15_MCU_WPD_R { + GPIO15_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio15_mcu_wpu(&self) -> GPIO15_MCU_WPU_R { + GPIO15_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio15_mcu_ie(&self) -> GPIO15_MCU_IE_R { + GPIO15_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio15_mcu_drv(&self) -> GPIO15_MCU_DRV_R { + GPIO15_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio15_fun_wpd(&self) -> GPIO15_FUN_WPD_R { + GPIO15_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio15_fun_wpu(&self) -> GPIO15_FUN_WPU_R { + GPIO15_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio15_fun_ie(&self) -> GPIO15_FUN_IE_R { + GPIO15_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio15_fun_drv(&self) -> GPIO15_FUN_DRV_R { + GPIO15_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio15_mcu_sel(&self) -> GPIO15_MCU_SEL_R { + GPIO15_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio15_filter_en(&self) -> GPIO15_FILTER_EN_R { + GPIO15_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio15") + .field( + "gpio15_mcu_oe", + &format_args!("{}", self.gpio15_mcu_oe().bit()), + ) + .field( + "gpio15_slp_sel", + &format_args!("{}", self.gpio15_slp_sel().bit()), + ) + .field( + "gpio15_mcu_wpd", + &format_args!("{}", self.gpio15_mcu_wpd().bit()), + ) + .field( + "gpio15_mcu_wpu", + &format_args!("{}", self.gpio15_mcu_wpu().bit()), + ) + .field( + "gpio15_mcu_ie", + &format_args!("{}", self.gpio15_mcu_ie().bit()), + ) + .field( + "gpio15_mcu_drv", + &format_args!("{}", self.gpio15_mcu_drv().bits()), + ) + .field( + "gpio15_fun_wpd", + &format_args!("{}", self.gpio15_fun_wpd().bit()), + ) + .field( + "gpio15_fun_wpu", + &format_args!("{}", self.gpio15_fun_wpu().bit()), + ) + .field( + "gpio15_fun_ie", + &format_args!("{}", self.gpio15_fun_ie().bit()), + ) + .field( + "gpio15_fun_drv", + &format_args!("{}", self.gpio15_fun_drv().bits()), + ) + .field( + "gpio15_mcu_sel", + &format_args!("{}", self.gpio15_mcu_sel().bits()), + ) + .field( + "gpio15_filter_en", + &format_args!("{}", self.gpio15_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio15_mcu_oe(&mut self) -> GPIO15_MCU_OE_W { + GPIO15_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio15_slp_sel(&mut self) -> GPIO15_SLP_SEL_W { + GPIO15_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio15_mcu_wpd(&mut self) -> GPIO15_MCU_WPD_W { + GPIO15_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio15_mcu_wpu(&mut self) -> GPIO15_MCU_WPU_W { + GPIO15_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio15_mcu_ie(&mut self) -> GPIO15_MCU_IE_W { + GPIO15_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio15_mcu_drv(&mut self) -> GPIO15_MCU_DRV_W { + GPIO15_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio15_fun_wpd(&mut self) -> GPIO15_FUN_WPD_W { + GPIO15_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio15_fun_wpu(&mut self) -> GPIO15_FUN_WPU_W { + GPIO15_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio15_fun_ie(&mut self) -> GPIO15_FUN_IE_W { + GPIO15_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio15_fun_drv(&mut self) -> GPIO15_FUN_DRV_W { + GPIO15_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio15_mcu_sel(&mut self) -> GPIO15_MCU_SEL_W { + GPIO15_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio15_filter_en(&mut self) -> GPIO15_FILTER_EN_W { + GPIO15_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO15_SPEC; +impl crate::RegisterSpec for GPIO15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio15::R`](R) reader structure"] +impl crate::Readable for GPIO15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio15::W`](W) writer structure"] +impl crate::Writable for GPIO15_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio15 to value 0x0800"] +impl crate::Resettable for GPIO15_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio16.rs b/esp32p4/src/io_mux/gpio16.rs new file mode 100644 index 0000000000..ad0185b951 --- /dev/null +++ b/esp32p4/src/io_mux/gpio16.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio16` reader"] +pub type R = crate::R; +#[doc = "Register `gpio16` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO16_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO16_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO16_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO16_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO16_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO16_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO16_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO16_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO16_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO16_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO16_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO16_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO16_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO16_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO16_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO16_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO16_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO16_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO16_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO16_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO16_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO16_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO16_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO16_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO16_FUN_WPD` reader - pull-down enable"] +pub type GPIO16_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO16_FUN_WPD` writer - pull-down enable"] +pub type GPIO16_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO16_FUN_WPU` reader - pull-up enable"] +pub type GPIO16_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO16_FUN_WPU` writer - pull-up enable"] +pub type GPIO16_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO16_FUN_IE` reader - input enable"] +pub type GPIO16_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO16_FUN_IE` writer - input enable"] +pub type GPIO16_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO16_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO16_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO16_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO16_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO16_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO16_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO16_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO16_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO16_FILTER_EN` reader - input filter enable"] +pub type GPIO16_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO16_FILTER_EN` writer - input filter enable"] +pub type GPIO16_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio16_mcu_oe(&self) -> GPIO16_MCU_OE_R { + GPIO16_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio16_slp_sel(&self) -> GPIO16_SLP_SEL_R { + GPIO16_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio16_mcu_wpd(&self) -> GPIO16_MCU_WPD_R { + GPIO16_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio16_mcu_wpu(&self) -> GPIO16_MCU_WPU_R { + GPIO16_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio16_mcu_ie(&self) -> GPIO16_MCU_IE_R { + GPIO16_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio16_mcu_drv(&self) -> GPIO16_MCU_DRV_R { + GPIO16_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio16_fun_wpd(&self) -> GPIO16_FUN_WPD_R { + GPIO16_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio16_fun_wpu(&self) -> GPIO16_FUN_WPU_R { + GPIO16_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio16_fun_ie(&self) -> GPIO16_FUN_IE_R { + GPIO16_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio16_fun_drv(&self) -> GPIO16_FUN_DRV_R { + GPIO16_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio16_mcu_sel(&self) -> GPIO16_MCU_SEL_R { + GPIO16_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio16_filter_en(&self) -> GPIO16_FILTER_EN_R { + GPIO16_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio16") + .field( + "gpio16_mcu_oe", + &format_args!("{}", self.gpio16_mcu_oe().bit()), + ) + .field( + "gpio16_slp_sel", + &format_args!("{}", self.gpio16_slp_sel().bit()), + ) + .field( + "gpio16_mcu_wpd", + &format_args!("{}", self.gpio16_mcu_wpd().bit()), + ) + .field( + "gpio16_mcu_wpu", + &format_args!("{}", self.gpio16_mcu_wpu().bit()), + ) + .field( + "gpio16_mcu_ie", + &format_args!("{}", self.gpio16_mcu_ie().bit()), + ) + .field( + "gpio16_mcu_drv", + &format_args!("{}", self.gpio16_mcu_drv().bits()), + ) + .field( + "gpio16_fun_wpd", + &format_args!("{}", self.gpio16_fun_wpd().bit()), + ) + .field( + "gpio16_fun_wpu", + &format_args!("{}", self.gpio16_fun_wpu().bit()), + ) + .field( + "gpio16_fun_ie", + &format_args!("{}", self.gpio16_fun_ie().bit()), + ) + .field( + "gpio16_fun_drv", + &format_args!("{}", self.gpio16_fun_drv().bits()), + ) + .field( + "gpio16_mcu_sel", + &format_args!("{}", self.gpio16_mcu_sel().bits()), + ) + .field( + "gpio16_filter_en", + &format_args!("{}", self.gpio16_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio16_mcu_oe(&mut self) -> GPIO16_MCU_OE_W { + GPIO16_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio16_slp_sel(&mut self) -> GPIO16_SLP_SEL_W { + GPIO16_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio16_mcu_wpd(&mut self) -> GPIO16_MCU_WPD_W { + GPIO16_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio16_mcu_wpu(&mut self) -> GPIO16_MCU_WPU_W { + GPIO16_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio16_mcu_ie(&mut self) -> GPIO16_MCU_IE_W { + GPIO16_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio16_mcu_drv(&mut self) -> GPIO16_MCU_DRV_W { + GPIO16_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio16_fun_wpd(&mut self) -> GPIO16_FUN_WPD_W { + GPIO16_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio16_fun_wpu(&mut self) -> GPIO16_FUN_WPU_W { + GPIO16_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio16_fun_ie(&mut self) -> GPIO16_FUN_IE_W { + GPIO16_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio16_fun_drv(&mut self) -> GPIO16_FUN_DRV_W { + GPIO16_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio16_mcu_sel(&mut self) -> GPIO16_MCU_SEL_W { + GPIO16_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio16_filter_en(&mut self) -> GPIO16_FILTER_EN_W { + GPIO16_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio16::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio16::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO16_SPEC; +impl crate::RegisterSpec for GPIO16_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio16::R`](R) reader structure"] +impl crate::Readable for GPIO16_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio16::W`](W) writer structure"] +impl crate::Writable for GPIO16_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio16 to value 0x0800"] +impl crate::Resettable for GPIO16_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio17.rs b/esp32p4/src/io_mux/gpio17.rs new file mode 100644 index 0000000000..df052122fc --- /dev/null +++ b/esp32p4/src/io_mux/gpio17.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio17` reader"] +pub type R = crate::R; +#[doc = "Register `gpio17` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO17_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO17_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO17_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO17_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO17_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO17_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO17_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO17_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO17_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO17_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO17_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO17_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO17_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO17_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO17_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO17_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO17_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO17_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO17_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO17_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO17_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO17_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO17_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO17_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO17_FUN_WPD` reader - pull-down enable"] +pub type GPIO17_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO17_FUN_WPD` writer - pull-down enable"] +pub type GPIO17_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO17_FUN_WPU` reader - pull-up enable"] +pub type GPIO17_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO17_FUN_WPU` writer - pull-up enable"] +pub type GPIO17_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO17_FUN_IE` reader - input enable"] +pub type GPIO17_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO17_FUN_IE` writer - input enable"] +pub type GPIO17_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO17_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO17_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO17_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO17_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO17_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO17_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO17_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO17_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO17_FILTER_EN` reader - input filter enable"] +pub type GPIO17_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO17_FILTER_EN` writer - input filter enable"] +pub type GPIO17_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio17_mcu_oe(&self) -> GPIO17_MCU_OE_R { + GPIO17_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio17_slp_sel(&self) -> GPIO17_SLP_SEL_R { + GPIO17_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio17_mcu_wpd(&self) -> GPIO17_MCU_WPD_R { + GPIO17_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio17_mcu_wpu(&self) -> GPIO17_MCU_WPU_R { + GPIO17_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio17_mcu_ie(&self) -> GPIO17_MCU_IE_R { + GPIO17_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio17_mcu_drv(&self) -> GPIO17_MCU_DRV_R { + GPIO17_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio17_fun_wpd(&self) -> GPIO17_FUN_WPD_R { + GPIO17_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio17_fun_wpu(&self) -> GPIO17_FUN_WPU_R { + GPIO17_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio17_fun_ie(&self) -> GPIO17_FUN_IE_R { + GPIO17_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio17_fun_drv(&self) -> GPIO17_FUN_DRV_R { + GPIO17_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio17_mcu_sel(&self) -> GPIO17_MCU_SEL_R { + GPIO17_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio17_filter_en(&self) -> GPIO17_FILTER_EN_R { + GPIO17_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio17") + .field( + "gpio17_mcu_oe", + &format_args!("{}", self.gpio17_mcu_oe().bit()), + ) + .field( + "gpio17_slp_sel", + &format_args!("{}", self.gpio17_slp_sel().bit()), + ) + .field( + "gpio17_mcu_wpd", + &format_args!("{}", self.gpio17_mcu_wpd().bit()), + ) + .field( + "gpio17_mcu_wpu", + &format_args!("{}", self.gpio17_mcu_wpu().bit()), + ) + .field( + "gpio17_mcu_ie", + &format_args!("{}", self.gpio17_mcu_ie().bit()), + ) + .field( + "gpio17_mcu_drv", + &format_args!("{}", self.gpio17_mcu_drv().bits()), + ) + .field( + "gpio17_fun_wpd", + &format_args!("{}", self.gpio17_fun_wpd().bit()), + ) + .field( + "gpio17_fun_wpu", + &format_args!("{}", self.gpio17_fun_wpu().bit()), + ) + .field( + "gpio17_fun_ie", + &format_args!("{}", self.gpio17_fun_ie().bit()), + ) + .field( + "gpio17_fun_drv", + &format_args!("{}", self.gpio17_fun_drv().bits()), + ) + .field( + "gpio17_mcu_sel", + &format_args!("{}", self.gpio17_mcu_sel().bits()), + ) + .field( + "gpio17_filter_en", + &format_args!("{}", self.gpio17_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio17_mcu_oe(&mut self) -> GPIO17_MCU_OE_W { + GPIO17_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio17_slp_sel(&mut self) -> GPIO17_SLP_SEL_W { + GPIO17_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio17_mcu_wpd(&mut self) -> GPIO17_MCU_WPD_W { + GPIO17_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio17_mcu_wpu(&mut self) -> GPIO17_MCU_WPU_W { + GPIO17_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio17_mcu_ie(&mut self) -> GPIO17_MCU_IE_W { + GPIO17_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio17_mcu_drv(&mut self) -> GPIO17_MCU_DRV_W { + GPIO17_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio17_fun_wpd(&mut self) -> GPIO17_FUN_WPD_W { + GPIO17_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio17_fun_wpu(&mut self) -> GPIO17_FUN_WPU_W { + GPIO17_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio17_fun_ie(&mut self) -> GPIO17_FUN_IE_W { + GPIO17_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio17_fun_drv(&mut self) -> GPIO17_FUN_DRV_W { + GPIO17_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio17_mcu_sel(&mut self) -> GPIO17_MCU_SEL_W { + GPIO17_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio17_filter_en(&mut self) -> GPIO17_FILTER_EN_W { + GPIO17_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio17\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio17::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio17::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO17_SPEC; +impl crate::RegisterSpec for GPIO17_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio17::R`](R) reader structure"] +impl crate::Readable for GPIO17_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio17::W`](W) writer structure"] +impl crate::Writable for GPIO17_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio17 to value 0x0800"] +impl crate::Resettable for GPIO17_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio18.rs b/esp32p4/src/io_mux/gpio18.rs new file mode 100644 index 0000000000..9ede00bc0f --- /dev/null +++ b/esp32p4/src/io_mux/gpio18.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio18` reader"] +pub type R = crate::R; +#[doc = "Register `gpio18` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO18_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO18_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO18_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO18_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO18_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO18_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO18_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO18_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO18_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO18_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO18_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO18_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO18_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO18_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO18_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO18_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO18_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO18_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO18_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO18_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO18_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO18_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO18_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO18_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO18_FUN_WPD` reader - pull-down enable"] +pub type GPIO18_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO18_FUN_WPD` writer - pull-down enable"] +pub type GPIO18_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO18_FUN_WPU` reader - pull-up enable"] +pub type GPIO18_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO18_FUN_WPU` writer - pull-up enable"] +pub type GPIO18_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO18_FUN_IE` reader - input enable"] +pub type GPIO18_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO18_FUN_IE` writer - input enable"] +pub type GPIO18_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO18_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO18_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO18_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO18_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO18_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO18_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO18_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO18_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO18_FILTER_EN` reader - input filter enable"] +pub type GPIO18_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO18_FILTER_EN` writer - input filter enable"] +pub type GPIO18_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio18_mcu_oe(&self) -> GPIO18_MCU_OE_R { + GPIO18_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio18_slp_sel(&self) -> GPIO18_SLP_SEL_R { + GPIO18_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio18_mcu_wpd(&self) -> GPIO18_MCU_WPD_R { + GPIO18_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio18_mcu_wpu(&self) -> GPIO18_MCU_WPU_R { + GPIO18_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio18_mcu_ie(&self) -> GPIO18_MCU_IE_R { + GPIO18_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio18_mcu_drv(&self) -> GPIO18_MCU_DRV_R { + GPIO18_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio18_fun_wpd(&self) -> GPIO18_FUN_WPD_R { + GPIO18_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio18_fun_wpu(&self) -> GPIO18_FUN_WPU_R { + GPIO18_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio18_fun_ie(&self) -> GPIO18_FUN_IE_R { + GPIO18_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio18_fun_drv(&self) -> GPIO18_FUN_DRV_R { + GPIO18_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio18_mcu_sel(&self) -> GPIO18_MCU_SEL_R { + GPIO18_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio18_filter_en(&self) -> GPIO18_FILTER_EN_R { + GPIO18_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio18") + .field( + "gpio18_mcu_oe", + &format_args!("{}", self.gpio18_mcu_oe().bit()), + ) + .field( + "gpio18_slp_sel", + &format_args!("{}", self.gpio18_slp_sel().bit()), + ) + .field( + "gpio18_mcu_wpd", + &format_args!("{}", self.gpio18_mcu_wpd().bit()), + ) + .field( + "gpio18_mcu_wpu", + &format_args!("{}", self.gpio18_mcu_wpu().bit()), + ) + .field( + "gpio18_mcu_ie", + &format_args!("{}", self.gpio18_mcu_ie().bit()), + ) + .field( + "gpio18_mcu_drv", + &format_args!("{}", self.gpio18_mcu_drv().bits()), + ) + .field( + "gpio18_fun_wpd", + &format_args!("{}", self.gpio18_fun_wpd().bit()), + ) + .field( + "gpio18_fun_wpu", + &format_args!("{}", self.gpio18_fun_wpu().bit()), + ) + .field( + "gpio18_fun_ie", + &format_args!("{}", self.gpio18_fun_ie().bit()), + ) + .field( + "gpio18_fun_drv", + &format_args!("{}", self.gpio18_fun_drv().bits()), + ) + .field( + "gpio18_mcu_sel", + &format_args!("{}", self.gpio18_mcu_sel().bits()), + ) + .field( + "gpio18_filter_en", + &format_args!("{}", self.gpio18_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio18_mcu_oe(&mut self) -> GPIO18_MCU_OE_W { + GPIO18_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio18_slp_sel(&mut self) -> GPIO18_SLP_SEL_W { + GPIO18_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio18_mcu_wpd(&mut self) -> GPIO18_MCU_WPD_W { + GPIO18_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio18_mcu_wpu(&mut self) -> GPIO18_MCU_WPU_W { + GPIO18_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio18_mcu_ie(&mut self) -> GPIO18_MCU_IE_W { + GPIO18_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio18_mcu_drv(&mut self) -> GPIO18_MCU_DRV_W { + GPIO18_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio18_fun_wpd(&mut self) -> GPIO18_FUN_WPD_W { + GPIO18_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio18_fun_wpu(&mut self) -> GPIO18_FUN_WPU_W { + GPIO18_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio18_fun_ie(&mut self) -> GPIO18_FUN_IE_W { + GPIO18_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio18_fun_drv(&mut self) -> GPIO18_FUN_DRV_W { + GPIO18_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio18_mcu_sel(&mut self) -> GPIO18_MCU_SEL_W { + GPIO18_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio18_filter_en(&mut self) -> GPIO18_FILTER_EN_W { + GPIO18_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio18\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio18::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio18::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO18_SPEC; +impl crate::RegisterSpec for GPIO18_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio18::R`](R) reader structure"] +impl crate::Readable for GPIO18_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio18::W`](W) writer structure"] +impl crate::Writable for GPIO18_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio18 to value 0x0800"] +impl crate::Resettable for GPIO18_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio19.rs b/esp32p4/src/io_mux/gpio19.rs new file mode 100644 index 0000000000..920da7523a --- /dev/null +++ b/esp32p4/src/io_mux/gpio19.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio19` reader"] +pub type R = crate::R; +#[doc = "Register `gpio19` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO19_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO19_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO19_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO19_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO19_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO19_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO19_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO19_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO19_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO19_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO19_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO19_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO19_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO19_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO19_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO19_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO19_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO19_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO19_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO19_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO19_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO19_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO19_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO19_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO19_FUN_WPD` reader - pull-down enable"] +pub type GPIO19_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO19_FUN_WPD` writer - pull-down enable"] +pub type GPIO19_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO19_FUN_WPU` reader - pull-up enable"] +pub type GPIO19_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO19_FUN_WPU` writer - pull-up enable"] +pub type GPIO19_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO19_FUN_IE` reader - input enable"] +pub type GPIO19_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO19_FUN_IE` writer - input enable"] +pub type GPIO19_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO19_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO19_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO19_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO19_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO19_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO19_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO19_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO19_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO19_FILTER_EN` reader - input filter enable"] +pub type GPIO19_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO19_FILTER_EN` writer - input filter enable"] +pub type GPIO19_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio19_mcu_oe(&self) -> GPIO19_MCU_OE_R { + GPIO19_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio19_slp_sel(&self) -> GPIO19_SLP_SEL_R { + GPIO19_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio19_mcu_wpd(&self) -> GPIO19_MCU_WPD_R { + GPIO19_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio19_mcu_wpu(&self) -> GPIO19_MCU_WPU_R { + GPIO19_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio19_mcu_ie(&self) -> GPIO19_MCU_IE_R { + GPIO19_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio19_mcu_drv(&self) -> GPIO19_MCU_DRV_R { + GPIO19_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio19_fun_wpd(&self) -> GPIO19_FUN_WPD_R { + GPIO19_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio19_fun_wpu(&self) -> GPIO19_FUN_WPU_R { + GPIO19_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio19_fun_ie(&self) -> GPIO19_FUN_IE_R { + GPIO19_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio19_fun_drv(&self) -> GPIO19_FUN_DRV_R { + GPIO19_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio19_mcu_sel(&self) -> GPIO19_MCU_SEL_R { + GPIO19_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio19_filter_en(&self) -> GPIO19_FILTER_EN_R { + GPIO19_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio19") + .field( + "gpio19_mcu_oe", + &format_args!("{}", self.gpio19_mcu_oe().bit()), + ) + .field( + "gpio19_slp_sel", + &format_args!("{}", self.gpio19_slp_sel().bit()), + ) + .field( + "gpio19_mcu_wpd", + &format_args!("{}", self.gpio19_mcu_wpd().bit()), + ) + .field( + "gpio19_mcu_wpu", + &format_args!("{}", self.gpio19_mcu_wpu().bit()), + ) + .field( + "gpio19_mcu_ie", + &format_args!("{}", self.gpio19_mcu_ie().bit()), + ) + .field( + "gpio19_mcu_drv", + &format_args!("{}", self.gpio19_mcu_drv().bits()), + ) + .field( + "gpio19_fun_wpd", + &format_args!("{}", self.gpio19_fun_wpd().bit()), + ) + .field( + "gpio19_fun_wpu", + &format_args!("{}", self.gpio19_fun_wpu().bit()), + ) + .field( + "gpio19_fun_ie", + &format_args!("{}", self.gpio19_fun_ie().bit()), + ) + .field( + "gpio19_fun_drv", + &format_args!("{}", self.gpio19_fun_drv().bits()), + ) + .field( + "gpio19_mcu_sel", + &format_args!("{}", self.gpio19_mcu_sel().bits()), + ) + .field( + "gpio19_filter_en", + &format_args!("{}", self.gpio19_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio19_mcu_oe(&mut self) -> GPIO19_MCU_OE_W { + GPIO19_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio19_slp_sel(&mut self) -> GPIO19_SLP_SEL_W { + GPIO19_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio19_mcu_wpd(&mut self) -> GPIO19_MCU_WPD_W { + GPIO19_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio19_mcu_wpu(&mut self) -> GPIO19_MCU_WPU_W { + GPIO19_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio19_mcu_ie(&mut self) -> GPIO19_MCU_IE_W { + GPIO19_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio19_mcu_drv(&mut self) -> GPIO19_MCU_DRV_W { + GPIO19_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio19_fun_wpd(&mut self) -> GPIO19_FUN_WPD_W { + GPIO19_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio19_fun_wpu(&mut self) -> GPIO19_FUN_WPU_W { + GPIO19_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio19_fun_ie(&mut self) -> GPIO19_FUN_IE_W { + GPIO19_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio19_fun_drv(&mut self) -> GPIO19_FUN_DRV_W { + GPIO19_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio19_mcu_sel(&mut self) -> GPIO19_MCU_SEL_W { + GPIO19_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio19_filter_en(&mut self) -> GPIO19_FILTER_EN_W { + GPIO19_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio19\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio19::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio19::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO19_SPEC; +impl crate::RegisterSpec for GPIO19_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio19::R`](R) reader structure"] +impl crate::Readable for GPIO19_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio19::W`](W) writer structure"] +impl crate::Writable for GPIO19_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio19 to value 0x0800"] +impl crate::Resettable for GPIO19_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio2.rs b/esp32p4/src/io_mux/gpio2.rs new file mode 100644 index 0000000000..29aee629ca --- /dev/null +++ b/esp32p4/src/io_mux/gpio2.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio2` reader"] +pub type R = crate::R; +#[doc = "Register `gpio2` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO2_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO2_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO2_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO2_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO2_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO2_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO2_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO2_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO2_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO2_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO2_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO2_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO2_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO2_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO2_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO2_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO2_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO2_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO2_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO2_FUN_WPD` reader - pull-down enable"] +pub type GPIO2_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO2_FUN_WPD` writer - pull-down enable"] +pub type GPIO2_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_FUN_WPU` reader - pull-up enable"] +pub type GPIO2_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO2_FUN_WPU` writer - pull-up enable"] +pub type GPIO2_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_FUN_IE` reader - input enable"] +pub type GPIO2_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO2_FUN_IE` writer - input enable"] +pub type GPIO2_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO2_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO2_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO2_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO2_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO2_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO2_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO2_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO2_FILTER_EN` reader - input filter enable"] +pub type GPIO2_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO2_FILTER_EN` writer - input filter enable"] +pub type GPIO2_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio2_mcu_oe(&self) -> GPIO2_MCU_OE_R { + GPIO2_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio2_slp_sel(&self) -> GPIO2_SLP_SEL_R { + GPIO2_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio2_mcu_wpd(&self) -> GPIO2_MCU_WPD_R { + GPIO2_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio2_mcu_wpu(&self) -> GPIO2_MCU_WPU_R { + GPIO2_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio2_mcu_ie(&self) -> GPIO2_MCU_IE_R { + GPIO2_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio2_mcu_drv(&self) -> GPIO2_MCU_DRV_R { + GPIO2_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio2_fun_wpd(&self) -> GPIO2_FUN_WPD_R { + GPIO2_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio2_fun_wpu(&self) -> GPIO2_FUN_WPU_R { + GPIO2_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio2_fun_ie(&self) -> GPIO2_FUN_IE_R { + GPIO2_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio2_fun_drv(&self) -> GPIO2_FUN_DRV_R { + GPIO2_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio2_mcu_sel(&self) -> GPIO2_MCU_SEL_R { + GPIO2_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio2_filter_en(&self) -> GPIO2_FILTER_EN_R { + GPIO2_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio2") + .field( + "gpio2_mcu_oe", + &format_args!("{}", self.gpio2_mcu_oe().bit()), + ) + .field( + "gpio2_slp_sel", + &format_args!("{}", self.gpio2_slp_sel().bit()), + ) + .field( + "gpio2_mcu_wpd", + &format_args!("{}", self.gpio2_mcu_wpd().bit()), + ) + .field( + "gpio2_mcu_wpu", + &format_args!("{}", self.gpio2_mcu_wpu().bit()), + ) + .field( + "gpio2_mcu_ie", + &format_args!("{}", self.gpio2_mcu_ie().bit()), + ) + .field( + "gpio2_mcu_drv", + &format_args!("{}", self.gpio2_mcu_drv().bits()), + ) + .field( + "gpio2_fun_wpd", + &format_args!("{}", self.gpio2_fun_wpd().bit()), + ) + .field( + "gpio2_fun_wpu", + &format_args!("{}", self.gpio2_fun_wpu().bit()), + ) + .field( + "gpio2_fun_ie", + &format_args!("{}", self.gpio2_fun_ie().bit()), + ) + .field( + "gpio2_fun_drv", + &format_args!("{}", self.gpio2_fun_drv().bits()), + ) + .field( + "gpio2_mcu_sel", + &format_args!("{}", self.gpio2_mcu_sel().bits()), + ) + .field( + "gpio2_filter_en", + &format_args!("{}", self.gpio2_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio2_mcu_oe(&mut self) -> GPIO2_MCU_OE_W { + GPIO2_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio2_slp_sel(&mut self) -> GPIO2_SLP_SEL_W { + GPIO2_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio2_mcu_wpd(&mut self) -> GPIO2_MCU_WPD_W { + GPIO2_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio2_mcu_wpu(&mut self) -> GPIO2_MCU_WPU_W { + GPIO2_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio2_mcu_ie(&mut self) -> GPIO2_MCU_IE_W { + GPIO2_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio2_mcu_drv(&mut self) -> GPIO2_MCU_DRV_W { + GPIO2_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio2_fun_wpd(&mut self) -> GPIO2_FUN_WPD_W { + GPIO2_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio2_fun_wpu(&mut self) -> GPIO2_FUN_WPU_W { + GPIO2_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio2_fun_ie(&mut self) -> GPIO2_FUN_IE_W { + GPIO2_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio2_fun_drv(&mut self) -> GPIO2_FUN_DRV_W { + GPIO2_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio2_mcu_sel(&mut self) -> GPIO2_MCU_SEL_W { + GPIO2_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio2_filter_en(&mut self) -> GPIO2_FILTER_EN_W { + GPIO2_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO2_SPEC; +impl crate::RegisterSpec for GPIO2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio2::R`](R) reader structure"] +impl crate::Readable for GPIO2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio2::W`](W) writer structure"] +impl crate::Writable for GPIO2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio2 to value 0x0800"] +impl crate::Resettable for GPIO2_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio20.rs b/esp32p4/src/io_mux/gpio20.rs new file mode 100644 index 0000000000..9cb8ebd115 --- /dev/null +++ b/esp32p4/src/io_mux/gpio20.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio20` reader"] +pub type R = crate::R; +#[doc = "Register `gpio20` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO20_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO20_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO20_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO20_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO20_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO20_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO20_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO20_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO20_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO20_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO20_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO20_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO20_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO20_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO20_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO20_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO20_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO20_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO20_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO20_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO20_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO20_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO20_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO20_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO20_FUN_WPD` reader - pull-down enable"] +pub type GPIO20_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO20_FUN_WPD` writer - pull-down enable"] +pub type GPIO20_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO20_FUN_WPU` reader - pull-up enable"] +pub type GPIO20_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO20_FUN_WPU` writer - pull-up enable"] +pub type GPIO20_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO20_FUN_IE` reader - input enable"] +pub type GPIO20_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO20_FUN_IE` writer - input enable"] +pub type GPIO20_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO20_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO20_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO20_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO20_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO20_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO20_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO20_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO20_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO20_FILTER_EN` reader - input filter enable"] +pub type GPIO20_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO20_FILTER_EN` writer - input filter enable"] +pub type GPIO20_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio20_mcu_oe(&self) -> GPIO20_MCU_OE_R { + GPIO20_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio20_slp_sel(&self) -> GPIO20_SLP_SEL_R { + GPIO20_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio20_mcu_wpd(&self) -> GPIO20_MCU_WPD_R { + GPIO20_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio20_mcu_wpu(&self) -> GPIO20_MCU_WPU_R { + GPIO20_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio20_mcu_ie(&self) -> GPIO20_MCU_IE_R { + GPIO20_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio20_mcu_drv(&self) -> GPIO20_MCU_DRV_R { + GPIO20_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio20_fun_wpd(&self) -> GPIO20_FUN_WPD_R { + GPIO20_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio20_fun_wpu(&self) -> GPIO20_FUN_WPU_R { + GPIO20_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio20_fun_ie(&self) -> GPIO20_FUN_IE_R { + GPIO20_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio20_fun_drv(&self) -> GPIO20_FUN_DRV_R { + GPIO20_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio20_mcu_sel(&self) -> GPIO20_MCU_SEL_R { + GPIO20_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio20_filter_en(&self) -> GPIO20_FILTER_EN_R { + GPIO20_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio20") + .field( + "gpio20_mcu_oe", + &format_args!("{}", self.gpio20_mcu_oe().bit()), + ) + .field( + "gpio20_slp_sel", + &format_args!("{}", self.gpio20_slp_sel().bit()), + ) + .field( + "gpio20_mcu_wpd", + &format_args!("{}", self.gpio20_mcu_wpd().bit()), + ) + .field( + "gpio20_mcu_wpu", + &format_args!("{}", self.gpio20_mcu_wpu().bit()), + ) + .field( + "gpio20_mcu_ie", + &format_args!("{}", self.gpio20_mcu_ie().bit()), + ) + .field( + "gpio20_mcu_drv", + &format_args!("{}", self.gpio20_mcu_drv().bits()), + ) + .field( + "gpio20_fun_wpd", + &format_args!("{}", self.gpio20_fun_wpd().bit()), + ) + .field( + "gpio20_fun_wpu", + &format_args!("{}", self.gpio20_fun_wpu().bit()), + ) + .field( + "gpio20_fun_ie", + &format_args!("{}", self.gpio20_fun_ie().bit()), + ) + .field( + "gpio20_fun_drv", + &format_args!("{}", self.gpio20_fun_drv().bits()), + ) + .field( + "gpio20_mcu_sel", + &format_args!("{}", self.gpio20_mcu_sel().bits()), + ) + .field( + "gpio20_filter_en", + &format_args!("{}", self.gpio20_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio20_mcu_oe(&mut self) -> GPIO20_MCU_OE_W { + GPIO20_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio20_slp_sel(&mut self) -> GPIO20_SLP_SEL_W { + GPIO20_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio20_mcu_wpd(&mut self) -> GPIO20_MCU_WPD_W { + GPIO20_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio20_mcu_wpu(&mut self) -> GPIO20_MCU_WPU_W { + GPIO20_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio20_mcu_ie(&mut self) -> GPIO20_MCU_IE_W { + GPIO20_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio20_mcu_drv(&mut self) -> GPIO20_MCU_DRV_W { + GPIO20_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio20_fun_wpd(&mut self) -> GPIO20_FUN_WPD_W { + GPIO20_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio20_fun_wpu(&mut self) -> GPIO20_FUN_WPU_W { + GPIO20_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio20_fun_ie(&mut self) -> GPIO20_FUN_IE_W { + GPIO20_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio20_fun_drv(&mut self) -> GPIO20_FUN_DRV_W { + GPIO20_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio20_mcu_sel(&mut self) -> GPIO20_MCU_SEL_W { + GPIO20_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio20_filter_en(&mut self) -> GPIO20_FILTER_EN_W { + GPIO20_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio20::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio20::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO20_SPEC; +impl crate::RegisterSpec for GPIO20_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio20::R`](R) reader structure"] +impl crate::Readable for GPIO20_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio20::W`](W) writer structure"] +impl crate::Writable for GPIO20_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio20 to value 0x0800"] +impl crate::Resettable for GPIO20_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio21.rs b/esp32p4/src/io_mux/gpio21.rs new file mode 100644 index 0000000000..71f930fbab --- /dev/null +++ b/esp32p4/src/io_mux/gpio21.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio21` reader"] +pub type R = crate::R; +#[doc = "Register `gpio21` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO21_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO21_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO21_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO21_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO21_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO21_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO21_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO21_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO21_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO21_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO21_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO21_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO21_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO21_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO21_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO21_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO21_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO21_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO21_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO21_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO21_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO21_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO21_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO21_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO21_FUN_WPD` reader - pull-down enable"] +pub type GPIO21_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO21_FUN_WPD` writer - pull-down enable"] +pub type GPIO21_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO21_FUN_WPU` reader - pull-up enable"] +pub type GPIO21_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO21_FUN_WPU` writer - pull-up enable"] +pub type GPIO21_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO21_FUN_IE` reader - input enable"] +pub type GPIO21_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO21_FUN_IE` writer - input enable"] +pub type GPIO21_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO21_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO21_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO21_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO21_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO21_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO21_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO21_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO21_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO21_FILTER_EN` reader - input filter enable"] +pub type GPIO21_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO21_FILTER_EN` writer - input filter enable"] +pub type GPIO21_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio21_mcu_oe(&self) -> GPIO21_MCU_OE_R { + GPIO21_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio21_slp_sel(&self) -> GPIO21_SLP_SEL_R { + GPIO21_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio21_mcu_wpd(&self) -> GPIO21_MCU_WPD_R { + GPIO21_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio21_mcu_wpu(&self) -> GPIO21_MCU_WPU_R { + GPIO21_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio21_mcu_ie(&self) -> GPIO21_MCU_IE_R { + GPIO21_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio21_mcu_drv(&self) -> GPIO21_MCU_DRV_R { + GPIO21_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio21_fun_wpd(&self) -> GPIO21_FUN_WPD_R { + GPIO21_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio21_fun_wpu(&self) -> GPIO21_FUN_WPU_R { + GPIO21_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio21_fun_ie(&self) -> GPIO21_FUN_IE_R { + GPIO21_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio21_fun_drv(&self) -> GPIO21_FUN_DRV_R { + GPIO21_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio21_mcu_sel(&self) -> GPIO21_MCU_SEL_R { + GPIO21_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio21_filter_en(&self) -> GPIO21_FILTER_EN_R { + GPIO21_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio21") + .field( + "gpio21_mcu_oe", + &format_args!("{}", self.gpio21_mcu_oe().bit()), + ) + .field( + "gpio21_slp_sel", + &format_args!("{}", self.gpio21_slp_sel().bit()), + ) + .field( + "gpio21_mcu_wpd", + &format_args!("{}", self.gpio21_mcu_wpd().bit()), + ) + .field( + "gpio21_mcu_wpu", + &format_args!("{}", self.gpio21_mcu_wpu().bit()), + ) + .field( + "gpio21_mcu_ie", + &format_args!("{}", self.gpio21_mcu_ie().bit()), + ) + .field( + "gpio21_mcu_drv", + &format_args!("{}", self.gpio21_mcu_drv().bits()), + ) + .field( + "gpio21_fun_wpd", + &format_args!("{}", self.gpio21_fun_wpd().bit()), + ) + .field( + "gpio21_fun_wpu", + &format_args!("{}", self.gpio21_fun_wpu().bit()), + ) + .field( + "gpio21_fun_ie", + &format_args!("{}", self.gpio21_fun_ie().bit()), + ) + .field( + "gpio21_fun_drv", + &format_args!("{}", self.gpio21_fun_drv().bits()), + ) + .field( + "gpio21_mcu_sel", + &format_args!("{}", self.gpio21_mcu_sel().bits()), + ) + .field( + "gpio21_filter_en", + &format_args!("{}", self.gpio21_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio21_mcu_oe(&mut self) -> GPIO21_MCU_OE_W { + GPIO21_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio21_slp_sel(&mut self) -> GPIO21_SLP_SEL_W { + GPIO21_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio21_mcu_wpd(&mut self) -> GPIO21_MCU_WPD_W { + GPIO21_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio21_mcu_wpu(&mut self) -> GPIO21_MCU_WPU_W { + GPIO21_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio21_mcu_ie(&mut self) -> GPIO21_MCU_IE_W { + GPIO21_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio21_mcu_drv(&mut self) -> GPIO21_MCU_DRV_W { + GPIO21_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio21_fun_wpd(&mut self) -> GPIO21_FUN_WPD_W { + GPIO21_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio21_fun_wpu(&mut self) -> GPIO21_FUN_WPU_W { + GPIO21_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio21_fun_ie(&mut self) -> GPIO21_FUN_IE_W { + GPIO21_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio21_fun_drv(&mut self) -> GPIO21_FUN_DRV_W { + GPIO21_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio21_mcu_sel(&mut self) -> GPIO21_MCU_SEL_W { + GPIO21_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio21_filter_en(&mut self) -> GPIO21_FILTER_EN_W { + GPIO21_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio21\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio21::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio21::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO21_SPEC; +impl crate::RegisterSpec for GPIO21_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio21::R`](R) reader structure"] +impl crate::Readable for GPIO21_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio21::W`](W) writer structure"] +impl crate::Writable for GPIO21_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio21 to value 0x0800"] +impl crate::Resettable for GPIO21_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio22.rs b/esp32p4/src/io_mux/gpio22.rs new file mode 100644 index 0000000000..dc2865ade2 --- /dev/null +++ b/esp32p4/src/io_mux/gpio22.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio22` reader"] +pub type R = crate::R; +#[doc = "Register `gpio22` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO22_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO22_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO22_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO22_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO22_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO22_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO22_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO22_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO22_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO22_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO22_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO22_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO22_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO22_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO22_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO22_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO22_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO22_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO22_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO22_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO22_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO22_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO22_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO22_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO22_FUN_WPD` reader - pull-down enable"] +pub type GPIO22_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO22_FUN_WPD` writer - pull-down enable"] +pub type GPIO22_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO22_FUN_WPU` reader - pull-up enable"] +pub type GPIO22_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO22_FUN_WPU` writer - pull-up enable"] +pub type GPIO22_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO22_FUN_IE` reader - input enable"] +pub type GPIO22_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO22_FUN_IE` writer - input enable"] +pub type GPIO22_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO22_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO22_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO22_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO22_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO22_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO22_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO22_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO22_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO22_FILTER_EN` reader - input filter enable"] +pub type GPIO22_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO22_FILTER_EN` writer - input filter enable"] +pub type GPIO22_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio22_mcu_oe(&self) -> GPIO22_MCU_OE_R { + GPIO22_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio22_slp_sel(&self) -> GPIO22_SLP_SEL_R { + GPIO22_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio22_mcu_wpd(&self) -> GPIO22_MCU_WPD_R { + GPIO22_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio22_mcu_wpu(&self) -> GPIO22_MCU_WPU_R { + GPIO22_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio22_mcu_ie(&self) -> GPIO22_MCU_IE_R { + GPIO22_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio22_mcu_drv(&self) -> GPIO22_MCU_DRV_R { + GPIO22_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio22_fun_wpd(&self) -> GPIO22_FUN_WPD_R { + GPIO22_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio22_fun_wpu(&self) -> GPIO22_FUN_WPU_R { + GPIO22_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio22_fun_ie(&self) -> GPIO22_FUN_IE_R { + GPIO22_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio22_fun_drv(&self) -> GPIO22_FUN_DRV_R { + GPIO22_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio22_mcu_sel(&self) -> GPIO22_MCU_SEL_R { + GPIO22_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio22_filter_en(&self) -> GPIO22_FILTER_EN_R { + GPIO22_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio22") + .field( + "gpio22_mcu_oe", + &format_args!("{}", self.gpio22_mcu_oe().bit()), + ) + .field( + "gpio22_slp_sel", + &format_args!("{}", self.gpio22_slp_sel().bit()), + ) + .field( + "gpio22_mcu_wpd", + &format_args!("{}", self.gpio22_mcu_wpd().bit()), + ) + .field( + "gpio22_mcu_wpu", + &format_args!("{}", self.gpio22_mcu_wpu().bit()), + ) + .field( + "gpio22_mcu_ie", + &format_args!("{}", self.gpio22_mcu_ie().bit()), + ) + .field( + "gpio22_mcu_drv", + &format_args!("{}", self.gpio22_mcu_drv().bits()), + ) + .field( + "gpio22_fun_wpd", + &format_args!("{}", self.gpio22_fun_wpd().bit()), + ) + .field( + "gpio22_fun_wpu", + &format_args!("{}", self.gpio22_fun_wpu().bit()), + ) + .field( + "gpio22_fun_ie", + &format_args!("{}", self.gpio22_fun_ie().bit()), + ) + .field( + "gpio22_fun_drv", + &format_args!("{}", self.gpio22_fun_drv().bits()), + ) + .field( + "gpio22_mcu_sel", + &format_args!("{}", self.gpio22_mcu_sel().bits()), + ) + .field( + "gpio22_filter_en", + &format_args!("{}", self.gpio22_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio22_mcu_oe(&mut self) -> GPIO22_MCU_OE_W { + GPIO22_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio22_slp_sel(&mut self) -> GPIO22_SLP_SEL_W { + GPIO22_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio22_mcu_wpd(&mut self) -> GPIO22_MCU_WPD_W { + GPIO22_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio22_mcu_wpu(&mut self) -> GPIO22_MCU_WPU_W { + GPIO22_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio22_mcu_ie(&mut self) -> GPIO22_MCU_IE_W { + GPIO22_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio22_mcu_drv(&mut self) -> GPIO22_MCU_DRV_W { + GPIO22_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio22_fun_wpd(&mut self) -> GPIO22_FUN_WPD_W { + GPIO22_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio22_fun_wpu(&mut self) -> GPIO22_FUN_WPU_W { + GPIO22_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio22_fun_ie(&mut self) -> GPIO22_FUN_IE_W { + GPIO22_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio22_fun_drv(&mut self) -> GPIO22_FUN_DRV_W { + GPIO22_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio22_mcu_sel(&mut self) -> GPIO22_MCU_SEL_W { + GPIO22_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio22_filter_en(&mut self) -> GPIO22_FILTER_EN_W { + GPIO22_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio22\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio22::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio22::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO22_SPEC; +impl crate::RegisterSpec for GPIO22_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio22::R`](R) reader structure"] +impl crate::Readable for GPIO22_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio22::W`](W) writer structure"] +impl crate::Writable for GPIO22_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio22 to value 0x0800"] +impl crate::Resettable for GPIO22_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio23.rs b/esp32p4/src/io_mux/gpio23.rs new file mode 100644 index 0000000000..1e13c23d07 --- /dev/null +++ b/esp32p4/src/io_mux/gpio23.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio23` reader"] +pub type R = crate::R; +#[doc = "Register `gpio23` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO23_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO23_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO23_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO23_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO23_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO23_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO23_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO23_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO23_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO23_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO23_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO23_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO23_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO23_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO23_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO23_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO23_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO23_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO23_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO23_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO23_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO23_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO23_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO23_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO23_FUN_WPD` reader - pull-down enable"] +pub type GPIO23_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO23_FUN_WPD` writer - pull-down enable"] +pub type GPIO23_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO23_FUN_WPU` reader - pull-up enable"] +pub type GPIO23_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO23_FUN_WPU` writer - pull-up enable"] +pub type GPIO23_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO23_FUN_IE` reader - input enable"] +pub type GPIO23_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO23_FUN_IE` writer - input enable"] +pub type GPIO23_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO23_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO23_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO23_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO23_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO23_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO23_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO23_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO23_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO23_FILTER_EN` reader - input filter enable"] +pub type GPIO23_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO23_FILTER_EN` writer - input filter enable"] +pub type GPIO23_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio23_mcu_oe(&self) -> GPIO23_MCU_OE_R { + GPIO23_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio23_slp_sel(&self) -> GPIO23_SLP_SEL_R { + GPIO23_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio23_mcu_wpd(&self) -> GPIO23_MCU_WPD_R { + GPIO23_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio23_mcu_wpu(&self) -> GPIO23_MCU_WPU_R { + GPIO23_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio23_mcu_ie(&self) -> GPIO23_MCU_IE_R { + GPIO23_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio23_mcu_drv(&self) -> GPIO23_MCU_DRV_R { + GPIO23_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio23_fun_wpd(&self) -> GPIO23_FUN_WPD_R { + GPIO23_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio23_fun_wpu(&self) -> GPIO23_FUN_WPU_R { + GPIO23_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio23_fun_ie(&self) -> GPIO23_FUN_IE_R { + GPIO23_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio23_fun_drv(&self) -> GPIO23_FUN_DRV_R { + GPIO23_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio23_mcu_sel(&self) -> GPIO23_MCU_SEL_R { + GPIO23_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio23_filter_en(&self) -> GPIO23_FILTER_EN_R { + GPIO23_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio23") + .field( + "gpio23_mcu_oe", + &format_args!("{}", self.gpio23_mcu_oe().bit()), + ) + .field( + "gpio23_slp_sel", + &format_args!("{}", self.gpio23_slp_sel().bit()), + ) + .field( + "gpio23_mcu_wpd", + &format_args!("{}", self.gpio23_mcu_wpd().bit()), + ) + .field( + "gpio23_mcu_wpu", + &format_args!("{}", self.gpio23_mcu_wpu().bit()), + ) + .field( + "gpio23_mcu_ie", + &format_args!("{}", self.gpio23_mcu_ie().bit()), + ) + .field( + "gpio23_mcu_drv", + &format_args!("{}", self.gpio23_mcu_drv().bits()), + ) + .field( + "gpio23_fun_wpd", + &format_args!("{}", self.gpio23_fun_wpd().bit()), + ) + .field( + "gpio23_fun_wpu", + &format_args!("{}", self.gpio23_fun_wpu().bit()), + ) + .field( + "gpio23_fun_ie", + &format_args!("{}", self.gpio23_fun_ie().bit()), + ) + .field( + "gpio23_fun_drv", + &format_args!("{}", self.gpio23_fun_drv().bits()), + ) + .field( + "gpio23_mcu_sel", + &format_args!("{}", self.gpio23_mcu_sel().bits()), + ) + .field( + "gpio23_filter_en", + &format_args!("{}", self.gpio23_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio23_mcu_oe(&mut self) -> GPIO23_MCU_OE_W { + GPIO23_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio23_slp_sel(&mut self) -> GPIO23_SLP_SEL_W { + GPIO23_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio23_mcu_wpd(&mut self) -> GPIO23_MCU_WPD_W { + GPIO23_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio23_mcu_wpu(&mut self) -> GPIO23_MCU_WPU_W { + GPIO23_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio23_mcu_ie(&mut self) -> GPIO23_MCU_IE_W { + GPIO23_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio23_mcu_drv(&mut self) -> GPIO23_MCU_DRV_W { + GPIO23_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio23_fun_wpd(&mut self) -> GPIO23_FUN_WPD_W { + GPIO23_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio23_fun_wpu(&mut self) -> GPIO23_FUN_WPU_W { + GPIO23_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio23_fun_ie(&mut self) -> GPIO23_FUN_IE_W { + GPIO23_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio23_fun_drv(&mut self) -> GPIO23_FUN_DRV_W { + GPIO23_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio23_mcu_sel(&mut self) -> GPIO23_MCU_SEL_W { + GPIO23_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio23_filter_en(&mut self) -> GPIO23_FILTER_EN_W { + GPIO23_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio23\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio23::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio23::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO23_SPEC; +impl crate::RegisterSpec for GPIO23_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio23::R`](R) reader structure"] +impl crate::Readable for GPIO23_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio23::W`](W) writer structure"] +impl crate::Writable for GPIO23_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio23 to value 0x0800"] +impl crate::Resettable for GPIO23_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio24.rs b/esp32p4/src/io_mux/gpio24.rs new file mode 100644 index 0000000000..b6c0b7b420 --- /dev/null +++ b/esp32p4/src/io_mux/gpio24.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio24` reader"] +pub type R = crate::R; +#[doc = "Register `gpio24` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO24_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO24_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO24_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO24_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO24_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO24_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO24_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO24_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO24_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO24_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO24_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO24_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO24_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO24_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO24_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO24_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO24_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO24_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO24_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO24_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO24_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO24_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO24_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO24_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO24_FUN_WPD` reader - pull-down enable"] +pub type GPIO24_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO24_FUN_WPD` writer - pull-down enable"] +pub type GPIO24_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO24_FUN_WPU` reader - pull-up enable"] +pub type GPIO24_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO24_FUN_WPU` writer - pull-up enable"] +pub type GPIO24_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO24_FUN_IE` reader - input enable"] +pub type GPIO24_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO24_FUN_IE` writer - input enable"] +pub type GPIO24_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO24_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO24_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO24_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO24_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO24_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO24_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO24_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO24_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO24_FILTER_EN` reader - input filter enable"] +pub type GPIO24_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO24_FILTER_EN` writer - input filter enable"] +pub type GPIO24_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio24_mcu_oe(&self) -> GPIO24_MCU_OE_R { + GPIO24_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio24_slp_sel(&self) -> GPIO24_SLP_SEL_R { + GPIO24_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio24_mcu_wpd(&self) -> GPIO24_MCU_WPD_R { + GPIO24_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio24_mcu_wpu(&self) -> GPIO24_MCU_WPU_R { + GPIO24_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio24_mcu_ie(&self) -> GPIO24_MCU_IE_R { + GPIO24_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio24_mcu_drv(&self) -> GPIO24_MCU_DRV_R { + GPIO24_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio24_fun_wpd(&self) -> GPIO24_FUN_WPD_R { + GPIO24_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio24_fun_wpu(&self) -> GPIO24_FUN_WPU_R { + GPIO24_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio24_fun_ie(&self) -> GPIO24_FUN_IE_R { + GPIO24_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio24_fun_drv(&self) -> GPIO24_FUN_DRV_R { + GPIO24_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio24_mcu_sel(&self) -> GPIO24_MCU_SEL_R { + GPIO24_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio24_filter_en(&self) -> GPIO24_FILTER_EN_R { + GPIO24_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio24") + .field( + "gpio24_mcu_oe", + &format_args!("{}", self.gpio24_mcu_oe().bit()), + ) + .field( + "gpio24_slp_sel", + &format_args!("{}", self.gpio24_slp_sel().bit()), + ) + .field( + "gpio24_mcu_wpd", + &format_args!("{}", self.gpio24_mcu_wpd().bit()), + ) + .field( + "gpio24_mcu_wpu", + &format_args!("{}", self.gpio24_mcu_wpu().bit()), + ) + .field( + "gpio24_mcu_ie", + &format_args!("{}", self.gpio24_mcu_ie().bit()), + ) + .field( + "gpio24_mcu_drv", + &format_args!("{}", self.gpio24_mcu_drv().bits()), + ) + .field( + "gpio24_fun_wpd", + &format_args!("{}", self.gpio24_fun_wpd().bit()), + ) + .field( + "gpio24_fun_wpu", + &format_args!("{}", self.gpio24_fun_wpu().bit()), + ) + .field( + "gpio24_fun_ie", + &format_args!("{}", self.gpio24_fun_ie().bit()), + ) + .field( + "gpio24_fun_drv", + &format_args!("{}", self.gpio24_fun_drv().bits()), + ) + .field( + "gpio24_mcu_sel", + &format_args!("{}", self.gpio24_mcu_sel().bits()), + ) + .field( + "gpio24_filter_en", + &format_args!("{}", self.gpio24_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio24_mcu_oe(&mut self) -> GPIO24_MCU_OE_W { + GPIO24_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio24_slp_sel(&mut self) -> GPIO24_SLP_SEL_W { + GPIO24_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio24_mcu_wpd(&mut self) -> GPIO24_MCU_WPD_W { + GPIO24_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio24_mcu_wpu(&mut self) -> GPIO24_MCU_WPU_W { + GPIO24_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio24_mcu_ie(&mut self) -> GPIO24_MCU_IE_W { + GPIO24_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio24_mcu_drv(&mut self) -> GPIO24_MCU_DRV_W { + GPIO24_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio24_fun_wpd(&mut self) -> GPIO24_FUN_WPD_W { + GPIO24_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio24_fun_wpu(&mut self) -> GPIO24_FUN_WPU_W { + GPIO24_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio24_fun_ie(&mut self) -> GPIO24_FUN_IE_W { + GPIO24_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio24_fun_drv(&mut self) -> GPIO24_FUN_DRV_W { + GPIO24_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio24_mcu_sel(&mut self) -> GPIO24_MCU_SEL_W { + GPIO24_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio24_filter_en(&mut self) -> GPIO24_FILTER_EN_W { + GPIO24_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio24::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio24::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO24_SPEC; +impl crate::RegisterSpec for GPIO24_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio24::R`](R) reader structure"] +impl crate::Readable for GPIO24_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio24::W`](W) writer structure"] +impl crate::Writable for GPIO24_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio24 to value 0x0800"] +impl crate::Resettable for GPIO24_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio25.rs b/esp32p4/src/io_mux/gpio25.rs new file mode 100644 index 0000000000..37463bb371 --- /dev/null +++ b/esp32p4/src/io_mux/gpio25.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio25` reader"] +pub type R = crate::R; +#[doc = "Register `gpio25` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO25_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO25_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO25_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO25_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO25_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO25_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO25_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO25_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO25_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO25_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO25_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO25_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO25_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO25_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO25_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO25_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO25_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO25_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO25_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO25_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO25_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO25_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO25_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO25_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO25_FUN_WPD` reader - pull-down enable"] +pub type GPIO25_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO25_FUN_WPD` writer - pull-down enable"] +pub type GPIO25_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO25_FUN_WPU` reader - pull-up enable"] +pub type GPIO25_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO25_FUN_WPU` writer - pull-up enable"] +pub type GPIO25_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO25_FUN_IE` reader - input enable"] +pub type GPIO25_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO25_FUN_IE` writer - input enable"] +pub type GPIO25_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO25_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO25_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO25_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO25_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO25_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO25_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO25_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO25_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO25_FILTER_EN` reader - input filter enable"] +pub type GPIO25_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO25_FILTER_EN` writer - input filter enable"] +pub type GPIO25_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio25_mcu_oe(&self) -> GPIO25_MCU_OE_R { + GPIO25_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio25_slp_sel(&self) -> GPIO25_SLP_SEL_R { + GPIO25_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio25_mcu_wpd(&self) -> GPIO25_MCU_WPD_R { + GPIO25_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio25_mcu_wpu(&self) -> GPIO25_MCU_WPU_R { + GPIO25_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio25_mcu_ie(&self) -> GPIO25_MCU_IE_R { + GPIO25_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio25_mcu_drv(&self) -> GPIO25_MCU_DRV_R { + GPIO25_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio25_fun_wpd(&self) -> GPIO25_FUN_WPD_R { + GPIO25_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio25_fun_wpu(&self) -> GPIO25_FUN_WPU_R { + GPIO25_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio25_fun_ie(&self) -> GPIO25_FUN_IE_R { + GPIO25_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio25_fun_drv(&self) -> GPIO25_FUN_DRV_R { + GPIO25_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio25_mcu_sel(&self) -> GPIO25_MCU_SEL_R { + GPIO25_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio25_filter_en(&self) -> GPIO25_FILTER_EN_R { + GPIO25_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio25") + .field( + "gpio25_mcu_oe", + &format_args!("{}", self.gpio25_mcu_oe().bit()), + ) + .field( + "gpio25_slp_sel", + &format_args!("{}", self.gpio25_slp_sel().bit()), + ) + .field( + "gpio25_mcu_wpd", + &format_args!("{}", self.gpio25_mcu_wpd().bit()), + ) + .field( + "gpio25_mcu_wpu", + &format_args!("{}", self.gpio25_mcu_wpu().bit()), + ) + .field( + "gpio25_mcu_ie", + &format_args!("{}", self.gpio25_mcu_ie().bit()), + ) + .field( + "gpio25_mcu_drv", + &format_args!("{}", self.gpio25_mcu_drv().bits()), + ) + .field( + "gpio25_fun_wpd", + &format_args!("{}", self.gpio25_fun_wpd().bit()), + ) + .field( + "gpio25_fun_wpu", + &format_args!("{}", self.gpio25_fun_wpu().bit()), + ) + .field( + "gpio25_fun_ie", + &format_args!("{}", self.gpio25_fun_ie().bit()), + ) + .field( + "gpio25_fun_drv", + &format_args!("{}", self.gpio25_fun_drv().bits()), + ) + .field( + "gpio25_mcu_sel", + &format_args!("{}", self.gpio25_mcu_sel().bits()), + ) + .field( + "gpio25_filter_en", + &format_args!("{}", self.gpio25_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio25_mcu_oe(&mut self) -> GPIO25_MCU_OE_W { + GPIO25_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio25_slp_sel(&mut self) -> GPIO25_SLP_SEL_W { + GPIO25_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio25_mcu_wpd(&mut self) -> GPIO25_MCU_WPD_W { + GPIO25_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio25_mcu_wpu(&mut self) -> GPIO25_MCU_WPU_W { + GPIO25_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio25_mcu_ie(&mut self) -> GPIO25_MCU_IE_W { + GPIO25_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio25_mcu_drv(&mut self) -> GPIO25_MCU_DRV_W { + GPIO25_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio25_fun_wpd(&mut self) -> GPIO25_FUN_WPD_W { + GPIO25_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio25_fun_wpu(&mut self) -> GPIO25_FUN_WPU_W { + GPIO25_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio25_fun_ie(&mut self) -> GPIO25_FUN_IE_W { + GPIO25_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio25_fun_drv(&mut self) -> GPIO25_FUN_DRV_W { + GPIO25_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio25_mcu_sel(&mut self) -> GPIO25_MCU_SEL_W { + GPIO25_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio25_filter_en(&mut self) -> GPIO25_FILTER_EN_W { + GPIO25_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio25\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio25::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio25::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO25_SPEC; +impl crate::RegisterSpec for GPIO25_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio25::R`](R) reader structure"] +impl crate::Readable for GPIO25_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio25::W`](W) writer structure"] +impl crate::Writable for GPIO25_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio25 to value 0x0800"] +impl crate::Resettable for GPIO25_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio26.rs b/esp32p4/src/io_mux/gpio26.rs new file mode 100644 index 0000000000..9babcb573d --- /dev/null +++ b/esp32p4/src/io_mux/gpio26.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio26` reader"] +pub type R = crate::R; +#[doc = "Register `gpio26` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO26_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO26_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO26_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO26_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO26_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO26_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO26_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO26_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO26_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO26_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO26_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO26_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO26_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO26_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO26_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO26_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO26_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO26_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO26_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO26_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO26_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO26_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO26_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO26_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO26_FUN_WPD` reader - pull-down enable"] +pub type GPIO26_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO26_FUN_WPD` writer - pull-down enable"] +pub type GPIO26_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO26_FUN_WPU` reader - pull-up enable"] +pub type GPIO26_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO26_FUN_WPU` writer - pull-up enable"] +pub type GPIO26_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO26_FUN_IE` reader - input enable"] +pub type GPIO26_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO26_FUN_IE` writer - input enable"] +pub type GPIO26_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO26_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO26_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO26_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO26_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO26_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO26_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO26_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO26_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO26_FILTER_EN` reader - input filter enable"] +pub type GPIO26_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO26_FILTER_EN` writer - input filter enable"] +pub type GPIO26_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio26_mcu_oe(&self) -> GPIO26_MCU_OE_R { + GPIO26_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio26_slp_sel(&self) -> GPIO26_SLP_SEL_R { + GPIO26_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio26_mcu_wpd(&self) -> GPIO26_MCU_WPD_R { + GPIO26_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio26_mcu_wpu(&self) -> GPIO26_MCU_WPU_R { + GPIO26_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio26_mcu_ie(&self) -> GPIO26_MCU_IE_R { + GPIO26_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio26_mcu_drv(&self) -> GPIO26_MCU_DRV_R { + GPIO26_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio26_fun_wpd(&self) -> GPIO26_FUN_WPD_R { + GPIO26_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio26_fun_wpu(&self) -> GPIO26_FUN_WPU_R { + GPIO26_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio26_fun_ie(&self) -> GPIO26_FUN_IE_R { + GPIO26_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio26_fun_drv(&self) -> GPIO26_FUN_DRV_R { + GPIO26_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio26_mcu_sel(&self) -> GPIO26_MCU_SEL_R { + GPIO26_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio26_filter_en(&self) -> GPIO26_FILTER_EN_R { + GPIO26_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio26") + .field( + "gpio26_mcu_oe", + &format_args!("{}", self.gpio26_mcu_oe().bit()), + ) + .field( + "gpio26_slp_sel", + &format_args!("{}", self.gpio26_slp_sel().bit()), + ) + .field( + "gpio26_mcu_wpd", + &format_args!("{}", self.gpio26_mcu_wpd().bit()), + ) + .field( + "gpio26_mcu_wpu", + &format_args!("{}", self.gpio26_mcu_wpu().bit()), + ) + .field( + "gpio26_mcu_ie", + &format_args!("{}", self.gpio26_mcu_ie().bit()), + ) + .field( + "gpio26_mcu_drv", + &format_args!("{}", self.gpio26_mcu_drv().bits()), + ) + .field( + "gpio26_fun_wpd", + &format_args!("{}", self.gpio26_fun_wpd().bit()), + ) + .field( + "gpio26_fun_wpu", + &format_args!("{}", self.gpio26_fun_wpu().bit()), + ) + .field( + "gpio26_fun_ie", + &format_args!("{}", self.gpio26_fun_ie().bit()), + ) + .field( + "gpio26_fun_drv", + &format_args!("{}", self.gpio26_fun_drv().bits()), + ) + .field( + "gpio26_mcu_sel", + &format_args!("{}", self.gpio26_mcu_sel().bits()), + ) + .field( + "gpio26_filter_en", + &format_args!("{}", self.gpio26_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio26_mcu_oe(&mut self) -> GPIO26_MCU_OE_W { + GPIO26_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio26_slp_sel(&mut self) -> GPIO26_SLP_SEL_W { + GPIO26_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio26_mcu_wpd(&mut self) -> GPIO26_MCU_WPD_W { + GPIO26_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio26_mcu_wpu(&mut self) -> GPIO26_MCU_WPU_W { + GPIO26_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio26_mcu_ie(&mut self) -> GPIO26_MCU_IE_W { + GPIO26_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio26_mcu_drv(&mut self) -> GPIO26_MCU_DRV_W { + GPIO26_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio26_fun_wpd(&mut self) -> GPIO26_FUN_WPD_W { + GPIO26_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio26_fun_wpu(&mut self) -> GPIO26_FUN_WPU_W { + GPIO26_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio26_fun_ie(&mut self) -> GPIO26_FUN_IE_W { + GPIO26_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio26_fun_drv(&mut self) -> GPIO26_FUN_DRV_W { + GPIO26_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio26_mcu_sel(&mut self) -> GPIO26_MCU_SEL_W { + GPIO26_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio26_filter_en(&mut self) -> GPIO26_FILTER_EN_W { + GPIO26_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio26\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio26::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio26::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO26_SPEC; +impl crate::RegisterSpec for GPIO26_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio26::R`](R) reader structure"] +impl crate::Readable for GPIO26_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio26::W`](W) writer structure"] +impl crate::Writable for GPIO26_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio26 to value 0x0800"] +impl crate::Resettable for GPIO26_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio27.rs b/esp32p4/src/io_mux/gpio27.rs new file mode 100644 index 0000000000..e4151cc214 --- /dev/null +++ b/esp32p4/src/io_mux/gpio27.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio27` reader"] +pub type R = crate::R; +#[doc = "Register `gpio27` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO27_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO27_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO27_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO27_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO27_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO27_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO27_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO27_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO27_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO27_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO27_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO27_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO27_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO27_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO27_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO27_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO27_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO27_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO27_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO27_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO27_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO27_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO27_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO27_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO27_FUN_WPD` reader - pull-down enable"] +pub type GPIO27_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO27_FUN_WPD` writer - pull-down enable"] +pub type GPIO27_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO27_FUN_WPU` reader - pull-up enable"] +pub type GPIO27_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO27_FUN_WPU` writer - pull-up enable"] +pub type GPIO27_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO27_FUN_IE` reader - input enable"] +pub type GPIO27_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO27_FUN_IE` writer - input enable"] +pub type GPIO27_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO27_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO27_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO27_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO27_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO27_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO27_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO27_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO27_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO27_FILTER_EN` reader - input filter enable"] +pub type GPIO27_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO27_FILTER_EN` writer - input filter enable"] +pub type GPIO27_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio27_mcu_oe(&self) -> GPIO27_MCU_OE_R { + GPIO27_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio27_slp_sel(&self) -> GPIO27_SLP_SEL_R { + GPIO27_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio27_mcu_wpd(&self) -> GPIO27_MCU_WPD_R { + GPIO27_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio27_mcu_wpu(&self) -> GPIO27_MCU_WPU_R { + GPIO27_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio27_mcu_ie(&self) -> GPIO27_MCU_IE_R { + GPIO27_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio27_mcu_drv(&self) -> GPIO27_MCU_DRV_R { + GPIO27_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio27_fun_wpd(&self) -> GPIO27_FUN_WPD_R { + GPIO27_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio27_fun_wpu(&self) -> GPIO27_FUN_WPU_R { + GPIO27_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio27_fun_ie(&self) -> GPIO27_FUN_IE_R { + GPIO27_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio27_fun_drv(&self) -> GPIO27_FUN_DRV_R { + GPIO27_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio27_mcu_sel(&self) -> GPIO27_MCU_SEL_R { + GPIO27_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio27_filter_en(&self) -> GPIO27_FILTER_EN_R { + GPIO27_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio27") + .field( + "gpio27_mcu_oe", + &format_args!("{}", self.gpio27_mcu_oe().bit()), + ) + .field( + "gpio27_slp_sel", + &format_args!("{}", self.gpio27_slp_sel().bit()), + ) + .field( + "gpio27_mcu_wpd", + &format_args!("{}", self.gpio27_mcu_wpd().bit()), + ) + .field( + "gpio27_mcu_wpu", + &format_args!("{}", self.gpio27_mcu_wpu().bit()), + ) + .field( + "gpio27_mcu_ie", + &format_args!("{}", self.gpio27_mcu_ie().bit()), + ) + .field( + "gpio27_mcu_drv", + &format_args!("{}", self.gpio27_mcu_drv().bits()), + ) + .field( + "gpio27_fun_wpd", + &format_args!("{}", self.gpio27_fun_wpd().bit()), + ) + .field( + "gpio27_fun_wpu", + &format_args!("{}", self.gpio27_fun_wpu().bit()), + ) + .field( + "gpio27_fun_ie", + &format_args!("{}", self.gpio27_fun_ie().bit()), + ) + .field( + "gpio27_fun_drv", + &format_args!("{}", self.gpio27_fun_drv().bits()), + ) + .field( + "gpio27_mcu_sel", + &format_args!("{}", self.gpio27_mcu_sel().bits()), + ) + .field( + "gpio27_filter_en", + &format_args!("{}", self.gpio27_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio27_mcu_oe(&mut self) -> GPIO27_MCU_OE_W { + GPIO27_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio27_slp_sel(&mut self) -> GPIO27_SLP_SEL_W { + GPIO27_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio27_mcu_wpd(&mut self) -> GPIO27_MCU_WPD_W { + GPIO27_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio27_mcu_wpu(&mut self) -> GPIO27_MCU_WPU_W { + GPIO27_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio27_mcu_ie(&mut self) -> GPIO27_MCU_IE_W { + GPIO27_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio27_mcu_drv(&mut self) -> GPIO27_MCU_DRV_W { + GPIO27_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio27_fun_wpd(&mut self) -> GPIO27_FUN_WPD_W { + GPIO27_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio27_fun_wpu(&mut self) -> GPIO27_FUN_WPU_W { + GPIO27_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio27_fun_ie(&mut self) -> GPIO27_FUN_IE_W { + GPIO27_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio27_fun_drv(&mut self) -> GPIO27_FUN_DRV_W { + GPIO27_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio27_mcu_sel(&mut self) -> GPIO27_MCU_SEL_W { + GPIO27_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio27_filter_en(&mut self) -> GPIO27_FILTER_EN_W { + GPIO27_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio27\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio27::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio27::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO27_SPEC; +impl crate::RegisterSpec for GPIO27_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio27::R`](R) reader structure"] +impl crate::Readable for GPIO27_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio27::W`](W) writer structure"] +impl crate::Writable for GPIO27_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio27 to value 0x0800"] +impl crate::Resettable for GPIO27_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio28.rs b/esp32p4/src/io_mux/gpio28.rs new file mode 100644 index 0000000000..78c02a446a --- /dev/null +++ b/esp32p4/src/io_mux/gpio28.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio28` reader"] +pub type R = crate::R; +#[doc = "Register `gpio28` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO28_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO28_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO28_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO28_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO28_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO28_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO28_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO28_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO28_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO28_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO28_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO28_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO28_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO28_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO28_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO28_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO28_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO28_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO28_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO28_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO28_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO28_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO28_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO28_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO28_FUN_WPD` reader - pull-down enable"] +pub type GPIO28_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO28_FUN_WPD` writer - pull-down enable"] +pub type GPIO28_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO28_FUN_WPU` reader - pull-up enable"] +pub type GPIO28_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO28_FUN_WPU` writer - pull-up enable"] +pub type GPIO28_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO28_FUN_IE` reader - input enable"] +pub type GPIO28_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO28_FUN_IE` writer - input enable"] +pub type GPIO28_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO28_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO28_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO28_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO28_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO28_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO28_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO28_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO28_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO28_FILTER_EN` reader - input filter enable"] +pub type GPIO28_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO28_FILTER_EN` writer - input filter enable"] +pub type GPIO28_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio28_mcu_oe(&self) -> GPIO28_MCU_OE_R { + GPIO28_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio28_slp_sel(&self) -> GPIO28_SLP_SEL_R { + GPIO28_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio28_mcu_wpd(&self) -> GPIO28_MCU_WPD_R { + GPIO28_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio28_mcu_wpu(&self) -> GPIO28_MCU_WPU_R { + GPIO28_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio28_mcu_ie(&self) -> GPIO28_MCU_IE_R { + GPIO28_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio28_mcu_drv(&self) -> GPIO28_MCU_DRV_R { + GPIO28_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio28_fun_wpd(&self) -> GPIO28_FUN_WPD_R { + GPIO28_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio28_fun_wpu(&self) -> GPIO28_FUN_WPU_R { + GPIO28_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio28_fun_ie(&self) -> GPIO28_FUN_IE_R { + GPIO28_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio28_fun_drv(&self) -> GPIO28_FUN_DRV_R { + GPIO28_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio28_mcu_sel(&self) -> GPIO28_MCU_SEL_R { + GPIO28_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio28_filter_en(&self) -> GPIO28_FILTER_EN_R { + GPIO28_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio28") + .field( + "gpio28_mcu_oe", + &format_args!("{}", self.gpio28_mcu_oe().bit()), + ) + .field( + "gpio28_slp_sel", + &format_args!("{}", self.gpio28_slp_sel().bit()), + ) + .field( + "gpio28_mcu_wpd", + &format_args!("{}", self.gpio28_mcu_wpd().bit()), + ) + .field( + "gpio28_mcu_wpu", + &format_args!("{}", self.gpio28_mcu_wpu().bit()), + ) + .field( + "gpio28_mcu_ie", + &format_args!("{}", self.gpio28_mcu_ie().bit()), + ) + .field( + "gpio28_mcu_drv", + &format_args!("{}", self.gpio28_mcu_drv().bits()), + ) + .field( + "gpio28_fun_wpd", + &format_args!("{}", self.gpio28_fun_wpd().bit()), + ) + .field( + "gpio28_fun_wpu", + &format_args!("{}", self.gpio28_fun_wpu().bit()), + ) + .field( + "gpio28_fun_ie", + &format_args!("{}", self.gpio28_fun_ie().bit()), + ) + .field( + "gpio28_fun_drv", + &format_args!("{}", self.gpio28_fun_drv().bits()), + ) + .field( + "gpio28_mcu_sel", + &format_args!("{}", self.gpio28_mcu_sel().bits()), + ) + .field( + "gpio28_filter_en", + &format_args!("{}", self.gpio28_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio28_mcu_oe(&mut self) -> GPIO28_MCU_OE_W { + GPIO28_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio28_slp_sel(&mut self) -> GPIO28_SLP_SEL_W { + GPIO28_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio28_mcu_wpd(&mut self) -> GPIO28_MCU_WPD_W { + GPIO28_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio28_mcu_wpu(&mut self) -> GPIO28_MCU_WPU_W { + GPIO28_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio28_mcu_ie(&mut self) -> GPIO28_MCU_IE_W { + GPIO28_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio28_mcu_drv(&mut self) -> GPIO28_MCU_DRV_W { + GPIO28_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio28_fun_wpd(&mut self) -> GPIO28_FUN_WPD_W { + GPIO28_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio28_fun_wpu(&mut self) -> GPIO28_FUN_WPU_W { + GPIO28_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio28_fun_ie(&mut self) -> GPIO28_FUN_IE_W { + GPIO28_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio28_fun_drv(&mut self) -> GPIO28_FUN_DRV_W { + GPIO28_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio28_mcu_sel(&mut self) -> GPIO28_MCU_SEL_W { + GPIO28_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio28_filter_en(&mut self) -> GPIO28_FILTER_EN_W { + GPIO28_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio28::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio28::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO28_SPEC; +impl crate::RegisterSpec for GPIO28_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio28::R`](R) reader structure"] +impl crate::Readable for GPIO28_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio28::W`](W) writer structure"] +impl crate::Writable for GPIO28_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio28 to value 0x0800"] +impl crate::Resettable for GPIO28_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio29.rs b/esp32p4/src/io_mux/gpio29.rs new file mode 100644 index 0000000000..c07282b436 --- /dev/null +++ b/esp32p4/src/io_mux/gpio29.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio29` reader"] +pub type R = crate::R; +#[doc = "Register `gpio29` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO29_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO29_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO29_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO29_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO29_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO29_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO29_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO29_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO29_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO29_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO29_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO29_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO29_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO29_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO29_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO29_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO29_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO29_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO29_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO29_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO29_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO29_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO29_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO29_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO29_FUN_WPD` reader - pull-down enable"] +pub type GPIO29_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO29_FUN_WPD` writer - pull-down enable"] +pub type GPIO29_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO29_FUN_WPU` reader - pull-up enable"] +pub type GPIO29_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO29_FUN_WPU` writer - pull-up enable"] +pub type GPIO29_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO29_FUN_IE` reader - input enable"] +pub type GPIO29_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO29_FUN_IE` writer - input enable"] +pub type GPIO29_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO29_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO29_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO29_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO29_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO29_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO29_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO29_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO29_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO29_FILTER_EN` reader - input filter enable"] +pub type GPIO29_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO29_FILTER_EN` writer - input filter enable"] +pub type GPIO29_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio29_mcu_oe(&self) -> GPIO29_MCU_OE_R { + GPIO29_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio29_slp_sel(&self) -> GPIO29_SLP_SEL_R { + GPIO29_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio29_mcu_wpd(&self) -> GPIO29_MCU_WPD_R { + GPIO29_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio29_mcu_wpu(&self) -> GPIO29_MCU_WPU_R { + GPIO29_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio29_mcu_ie(&self) -> GPIO29_MCU_IE_R { + GPIO29_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio29_mcu_drv(&self) -> GPIO29_MCU_DRV_R { + GPIO29_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio29_fun_wpd(&self) -> GPIO29_FUN_WPD_R { + GPIO29_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio29_fun_wpu(&self) -> GPIO29_FUN_WPU_R { + GPIO29_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio29_fun_ie(&self) -> GPIO29_FUN_IE_R { + GPIO29_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio29_fun_drv(&self) -> GPIO29_FUN_DRV_R { + GPIO29_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio29_mcu_sel(&self) -> GPIO29_MCU_SEL_R { + GPIO29_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio29_filter_en(&self) -> GPIO29_FILTER_EN_R { + GPIO29_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio29") + .field( + "gpio29_mcu_oe", + &format_args!("{}", self.gpio29_mcu_oe().bit()), + ) + .field( + "gpio29_slp_sel", + &format_args!("{}", self.gpio29_slp_sel().bit()), + ) + .field( + "gpio29_mcu_wpd", + &format_args!("{}", self.gpio29_mcu_wpd().bit()), + ) + .field( + "gpio29_mcu_wpu", + &format_args!("{}", self.gpio29_mcu_wpu().bit()), + ) + .field( + "gpio29_mcu_ie", + &format_args!("{}", self.gpio29_mcu_ie().bit()), + ) + .field( + "gpio29_mcu_drv", + &format_args!("{}", self.gpio29_mcu_drv().bits()), + ) + .field( + "gpio29_fun_wpd", + &format_args!("{}", self.gpio29_fun_wpd().bit()), + ) + .field( + "gpio29_fun_wpu", + &format_args!("{}", self.gpio29_fun_wpu().bit()), + ) + .field( + "gpio29_fun_ie", + &format_args!("{}", self.gpio29_fun_ie().bit()), + ) + .field( + "gpio29_fun_drv", + &format_args!("{}", self.gpio29_fun_drv().bits()), + ) + .field( + "gpio29_mcu_sel", + &format_args!("{}", self.gpio29_mcu_sel().bits()), + ) + .field( + "gpio29_filter_en", + &format_args!("{}", self.gpio29_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio29_mcu_oe(&mut self) -> GPIO29_MCU_OE_W { + GPIO29_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio29_slp_sel(&mut self) -> GPIO29_SLP_SEL_W { + GPIO29_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio29_mcu_wpd(&mut self) -> GPIO29_MCU_WPD_W { + GPIO29_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio29_mcu_wpu(&mut self) -> GPIO29_MCU_WPU_W { + GPIO29_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio29_mcu_ie(&mut self) -> GPIO29_MCU_IE_W { + GPIO29_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio29_mcu_drv(&mut self) -> GPIO29_MCU_DRV_W { + GPIO29_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio29_fun_wpd(&mut self) -> GPIO29_FUN_WPD_W { + GPIO29_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio29_fun_wpu(&mut self) -> GPIO29_FUN_WPU_W { + GPIO29_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio29_fun_ie(&mut self) -> GPIO29_FUN_IE_W { + GPIO29_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio29_fun_drv(&mut self) -> GPIO29_FUN_DRV_W { + GPIO29_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio29_mcu_sel(&mut self) -> GPIO29_MCU_SEL_W { + GPIO29_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio29_filter_en(&mut self) -> GPIO29_FILTER_EN_W { + GPIO29_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio29\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio29::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio29::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO29_SPEC; +impl crate::RegisterSpec for GPIO29_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio29::R`](R) reader structure"] +impl crate::Readable for GPIO29_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio29::W`](W) writer structure"] +impl crate::Writable for GPIO29_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio29 to value 0x0800"] +impl crate::Resettable for GPIO29_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio3.rs b/esp32p4/src/io_mux/gpio3.rs new file mode 100644 index 0000000000..f41b9e6de7 --- /dev/null +++ b/esp32p4/src/io_mux/gpio3.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio3` reader"] +pub type R = crate::R; +#[doc = "Register `gpio3` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO3_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO3_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO3_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO3_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO3_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO3_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO3_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO3_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO3_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO3_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO3_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO3_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO3_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO3_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO3_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO3_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO3_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO3_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO3_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO3_FUN_WPD` reader - pull-down enable"] +pub type GPIO3_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO3_FUN_WPD` writer - pull-down enable"] +pub type GPIO3_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_FUN_WPU` reader - pull-up enable"] +pub type GPIO3_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO3_FUN_WPU` writer - pull-up enable"] +pub type GPIO3_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_FUN_IE` reader - input enable"] +pub type GPIO3_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO3_FUN_IE` writer - input enable"] +pub type GPIO3_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO3_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO3_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO3_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO3_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO3_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO3_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO3_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO3_FILTER_EN` reader - input filter enable"] +pub type GPIO3_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO3_FILTER_EN` writer - input filter enable"] +pub type GPIO3_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio3_mcu_oe(&self) -> GPIO3_MCU_OE_R { + GPIO3_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio3_slp_sel(&self) -> GPIO3_SLP_SEL_R { + GPIO3_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio3_mcu_wpd(&self) -> GPIO3_MCU_WPD_R { + GPIO3_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio3_mcu_wpu(&self) -> GPIO3_MCU_WPU_R { + GPIO3_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio3_mcu_ie(&self) -> GPIO3_MCU_IE_R { + GPIO3_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio3_mcu_drv(&self) -> GPIO3_MCU_DRV_R { + GPIO3_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio3_fun_wpd(&self) -> GPIO3_FUN_WPD_R { + GPIO3_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio3_fun_wpu(&self) -> GPIO3_FUN_WPU_R { + GPIO3_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio3_fun_ie(&self) -> GPIO3_FUN_IE_R { + GPIO3_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio3_fun_drv(&self) -> GPIO3_FUN_DRV_R { + GPIO3_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio3_mcu_sel(&self) -> GPIO3_MCU_SEL_R { + GPIO3_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio3_filter_en(&self) -> GPIO3_FILTER_EN_R { + GPIO3_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio3") + .field( + "gpio3_mcu_oe", + &format_args!("{}", self.gpio3_mcu_oe().bit()), + ) + .field( + "gpio3_slp_sel", + &format_args!("{}", self.gpio3_slp_sel().bit()), + ) + .field( + "gpio3_mcu_wpd", + &format_args!("{}", self.gpio3_mcu_wpd().bit()), + ) + .field( + "gpio3_mcu_wpu", + &format_args!("{}", self.gpio3_mcu_wpu().bit()), + ) + .field( + "gpio3_mcu_ie", + &format_args!("{}", self.gpio3_mcu_ie().bit()), + ) + .field( + "gpio3_mcu_drv", + &format_args!("{}", self.gpio3_mcu_drv().bits()), + ) + .field( + "gpio3_fun_wpd", + &format_args!("{}", self.gpio3_fun_wpd().bit()), + ) + .field( + "gpio3_fun_wpu", + &format_args!("{}", self.gpio3_fun_wpu().bit()), + ) + .field( + "gpio3_fun_ie", + &format_args!("{}", self.gpio3_fun_ie().bit()), + ) + .field( + "gpio3_fun_drv", + &format_args!("{}", self.gpio3_fun_drv().bits()), + ) + .field( + "gpio3_mcu_sel", + &format_args!("{}", self.gpio3_mcu_sel().bits()), + ) + .field( + "gpio3_filter_en", + &format_args!("{}", self.gpio3_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio3_mcu_oe(&mut self) -> GPIO3_MCU_OE_W { + GPIO3_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio3_slp_sel(&mut self) -> GPIO3_SLP_SEL_W { + GPIO3_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio3_mcu_wpd(&mut self) -> GPIO3_MCU_WPD_W { + GPIO3_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio3_mcu_wpu(&mut self) -> GPIO3_MCU_WPU_W { + GPIO3_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio3_mcu_ie(&mut self) -> GPIO3_MCU_IE_W { + GPIO3_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio3_mcu_drv(&mut self) -> GPIO3_MCU_DRV_W { + GPIO3_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio3_fun_wpd(&mut self) -> GPIO3_FUN_WPD_W { + GPIO3_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio3_fun_wpu(&mut self) -> GPIO3_FUN_WPU_W { + GPIO3_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio3_fun_ie(&mut self) -> GPIO3_FUN_IE_W { + GPIO3_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio3_fun_drv(&mut self) -> GPIO3_FUN_DRV_W { + GPIO3_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio3_mcu_sel(&mut self) -> GPIO3_MCU_SEL_W { + GPIO3_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio3_filter_en(&mut self) -> GPIO3_FILTER_EN_W { + GPIO3_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO3_SPEC; +impl crate::RegisterSpec for GPIO3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio3::R`](R) reader structure"] +impl crate::Readable for GPIO3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio3::W`](W) writer structure"] +impl crate::Writable for GPIO3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio3 to value 0x0800"] +impl crate::Resettable for GPIO3_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio30.rs b/esp32p4/src/io_mux/gpio30.rs new file mode 100644 index 0000000000..51b993e7d8 --- /dev/null +++ b/esp32p4/src/io_mux/gpio30.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio30` reader"] +pub type R = crate::R; +#[doc = "Register `gpio30` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO30_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO30_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO30_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO30_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO30_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO30_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO30_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO30_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO30_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO30_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO30_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO30_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO30_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO30_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO30_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO30_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO30_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO30_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO30_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO30_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO30_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO30_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO30_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO30_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO30_FUN_WPD` reader - pull-down enable"] +pub type GPIO30_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO30_FUN_WPD` writer - pull-down enable"] +pub type GPIO30_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO30_FUN_WPU` reader - pull-up enable"] +pub type GPIO30_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO30_FUN_WPU` writer - pull-up enable"] +pub type GPIO30_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO30_FUN_IE` reader - input enable"] +pub type GPIO30_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO30_FUN_IE` writer - input enable"] +pub type GPIO30_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO30_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO30_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO30_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO30_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO30_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO30_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO30_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO30_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO30_FILTER_EN` reader - input filter enable"] +pub type GPIO30_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO30_FILTER_EN` writer - input filter enable"] +pub type GPIO30_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio30_mcu_oe(&self) -> GPIO30_MCU_OE_R { + GPIO30_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio30_slp_sel(&self) -> GPIO30_SLP_SEL_R { + GPIO30_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio30_mcu_wpd(&self) -> GPIO30_MCU_WPD_R { + GPIO30_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio30_mcu_wpu(&self) -> GPIO30_MCU_WPU_R { + GPIO30_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio30_mcu_ie(&self) -> GPIO30_MCU_IE_R { + GPIO30_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio30_mcu_drv(&self) -> GPIO30_MCU_DRV_R { + GPIO30_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio30_fun_wpd(&self) -> GPIO30_FUN_WPD_R { + GPIO30_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio30_fun_wpu(&self) -> GPIO30_FUN_WPU_R { + GPIO30_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio30_fun_ie(&self) -> GPIO30_FUN_IE_R { + GPIO30_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio30_fun_drv(&self) -> GPIO30_FUN_DRV_R { + GPIO30_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio30_mcu_sel(&self) -> GPIO30_MCU_SEL_R { + GPIO30_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio30_filter_en(&self) -> GPIO30_FILTER_EN_R { + GPIO30_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio30") + .field( + "gpio30_mcu_oe", + &format_args!("{}", self.gpio30_mcu_oe().bit()), + ) + .field( + "gpio30_slp_sel", + &format_args!("{}", self.gpio30_slp_sel().bit()), + ) + .field( + "gpio30_mcu_wpd", + &format_args!("{}", self.gpio30_mcu_wpd().bit()), + ) + .field( + "gpio30_mcu_wpu", + &format_args!("{}", self.gpio30_mcu_wpu().bit()), + ) + .field( + "gpio30_mcu_ie", + &format_args!("{}", self.gpio30_mcu_ie().bit()), + ) + .field( + "gpio30_mcu_drv", + &format_args!("{}", self.gpio30_mcu_drv().bits()), + ) + .field( + "gpio30_fun_wpd", + &format_args!("{}", self.gpio30_fun_wpd().bit()), + ) + .field( + "gpio30_fun_wpu", + &format_args!("{}", self.gpio30_fun_wpu().bit()), + ) + .field( + "gpio30_fun_ie", + &format_args!("{}", self.gpio30_fun_ie().bit()), + ) + .field( + "gpio30_fun_drv", + &format_args!("{}", self.gpio30_fun_drv().bits()), + ) + .field( + "gpio30_mcu_sel", + &format_args!("{}", self.gpio30_mcu_sel().bits()), + ) + .field( + "gpio30_filter_en", + &format_args!("{}", self.gpio30_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio30_mcu_oe(&mut self) -> GPIO30_MCU_OE_W { + GPIO30_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio30_slp_sel(&mut self) -> GPIO30_SLP_SEL_W { + GPIO30_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio30_mcu_wpd(&mut self) -> GPIO30_MCU_WPD_W { + GPIO30_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio30_mcu_wpu(&mut self) -> GPIO30_MCU_WPU_W { + GPIO30_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio30_mcu_ie(&mut self) -> GPIO30_MCU_IE_W { + GPIO30_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio30_mcu_drv(&mut self) -> GPIO30_MCU_DRV_W { + GPIO30_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio30_fun_wpd(&mut self) -> GPIO30_FUN_WPD_W { + GPIO30_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio30_fun_wpu(&mut self) -> GPIO30_FUN_WPU_W { + GPIO30_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio30_fun_ie(&mut self) -> GPIO30_FUN_IE_W { + GPIO30_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio30_fun_drv(&mut self) -> GPIO30_FUN_DRV_W { + GPIO30_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio30_mcu_sel(&mut self) -> GPIO30_MCU_SEL_W { + GPIO30_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio30_filter_en(&mut self) -> GPIO30_FILTER_EN_W { + GPIO30_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio30\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio30::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio30::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO30_SPEC; +impl crate::RegisterSpec for GPIO30_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio30::R`](R) reader structure"] +impl crate::Readable for GPIO30_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio30::W`](W) writer structure"] +impl crate::Writable for GPIO30_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio30 to value 0x0800"] +impl crate::Resettable for GPIO30_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio31.rs b/esp32p4/src/io_mux/gpio31.rs new file mode 100644 index 0000000000..38a18ee376 --- /dev/null +++ b/esp32p4/src/io_mux/gpio31.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio31` reader"] +pub type R = crate::R; +#[doc = "Register `gpio31` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO31_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO31_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO31_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO31_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO31_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO31_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO31_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO31_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO31_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO31_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO31_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO31_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO31_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO31_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO31_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO31_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO31_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO31_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO31_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO31_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO31_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO31_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO31_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO31_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO31_FUN_WPD` reader - pull-down enable"] +pub type GPIO31_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO31_FUN_WPD` writer - pull-down enable"] +pub type GPIO31_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO31_FUN_WPU` reader - pull-up enable"] +pub type GPIO31_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO31_FUN_WPU` writer - pull-up enable"] +pub type GPIO31_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO31_FUN_IE` reader - input enable"] +pub type GPIO31_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO31_FUN_IE` writer - input enable"] +pub type GPIO31_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO31_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO31_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO31_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO31_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO31_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO31_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO31_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO31_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO31_FILTER_EN` reader - input filter enable"] +pub type GPIO31_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO31_FILTER_EN` writer - input filter enable"] +pub type GPIO31_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio31_mcu_oe(&self) -> GPIO31_MCU_OE_R { + GPIO31_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio31_slp_sel(&self) -> GPIO31_SLP_SEL_R { + GPIO31_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio31_mcu_wpd(&self) -> GPIO31_MCU_WPD_R { + GPIO31_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio31_mcu_wpu(&self) -> GPIO31_MCU_WPU_R { + GPIO31_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio31_mcu_ie(&self) -> GPIO31_MCU_IE_R { + GPIO31_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio31_mcu_drv(&self) -> GPIO31_MCU_DRV_R { + GPIO31_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio31_fun_wpd(&self) -> GPIO31_FUN_WPD_R { + GPIO31_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio31_fun_wpu(&self) -> GPIO31_FUN_WPU_R { + GPIO31_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio31_fun_ie(&self) -> GPIO31_FUN_IE_R { + GPIO31_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio31_fun_drv(&self) -> GPIO31_FUN_DRV_R { + GPIO31_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio31_mcu_sel(&self) -> GPIO31_MCU_SEL_R { + GPIO31_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio31_filter_en(&self) -> GPIO31_FILTER_EN_R { + GPIO31_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio31") + .field( + "gpio31_mcu_oe", + &format_args!("{}", self.gpio31_mcu_oe().bit()), + ) + .field( + "gpio31_slp_sel", + &format_args!("{}", self.gpio31_slp_sel().bit()), + ) + .field( + "gpio31_mcu_wpd", + &format_args!("{}", self.gpio31_mcu_wpd().bit()), + ) + .field( + "gpio31_mcu_wpu", + &format_args!("{}", self.gpio31_mcu_wpu().bit()), + ) + .field( + "gpio31_mcu_ie", + &format_args!("{}", self.gpio31_mcu_ie().bit()), + ) + .field( + "gpio31_mcu_drv", + &format_args!("{}", self.gpio31_mcu_drv().bits()), + ) + .field( + "gpio31_fun_wpd", + &format_args!("{}", self.gpio31_fun_wpd().bit()), + ) + .field( + "gpio31_fun_wpu", + &format_args!("{}", self.gpio31_fun_wpu().bit()), + ) + .field( + "gpio31_fun_ie", + &format_args!("{}", self.gpio31_fun_ie().bit()), + ) + .field( + "gpio31_fun_drv", + &format_args!("{}", self.gpio31_fun_drv().bits()), + ) + .field( + "gpio31_mcu_sel", + &format_args!("{}", self.gpio31_mcu_sel().bits()), + ) + .field( + "gpio31_filter_en", + &format_args!("{}", self.gpio31_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio31_mcu_oe(&mut self) -> GPIO31_MCU_OE_W { + GPIO31_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio31_slp_sel(&mut self) -> GPIO31_SLP_SEL_W { + GPIO31_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio31_mcu_wpd(&mut self) -> GPIO31_MCU_WPD_W { + GPIO31_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio31_mcu_wpu(&mut self) -> GPIO31_MCU_WPU_W { + GPIO31_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio31_mcu_ie(&mut self) -> GPIO31_MCU_IE_W { + GPIO31_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio31_mcu_drv(&mut self) -> GPIO31_MCU_DRV_W { + GPIO31_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio31_fun_wpd(&mut self) -> GPIO31_FUN_WPD_W { + GPIO31_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio31_fun_wpu(&mut self) -> GPIO31_FUN_WPU_W { + GPIO31_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio31_fun_ie(&mut self) -> GPIO31_FUN_IE_W { + GPIO31_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio31_fun_drv(&mut self) -> GPIO31_FUN_DRV_W { + GPIO31_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio31_mcu_sel(&mut self) -> GPIO31_MCU_SEL_W { + GPIO31_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio31_filter_en(&mut self) -> GPIO31_FILTER_EN_W { + GPIO31_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio31::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio31::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO31_SPEC; +impl crate::RegisterSpec for GPIO31_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio31::R`](R) reader structure"] +impl crate::Readable for GPIO31_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio31::W`](W) writer structure"] +impl crate::Writable for GPIO31_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio31 to value 0x0800"] +impl crate::Resettable for GPIO31_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio32.rs b/esp32p4/src/io_mux/gpio32.rs new file mode 100644 index 0000000000..e713e7f2fe --- /dev/null +++ b/esp32p4/src/io_mux/gpio32.rs @@ -0,0 +1,332 @@ +#[doc = "Register `gpio32` reader"] +pub type R = crate::R; +#[doc = "Register `gpio32` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO32_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO32_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO32_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO32_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO32_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO32_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO32_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO32_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO32_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO32_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO32_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO32_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO32_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO32_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO32_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO32_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO32_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO32_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO32_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO32_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO32_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO32_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO32_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO32_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO32_FUN_WPD` reader - pull-down enable"] +pub type GPIO32_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO32_FUN_WPD` writer - pull-down enable"] +pub type GPIO32_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO32_FUN_WPU` reader - pull-up enable"] +pub type GPIO32_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO32_FUN_WPU` writer - pull-up enable"] +pub type GPIO32_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO32_FUN_IE` reader - input enable"] +pub type GPIO32_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO32_FUN_IE` writer - input enable"] +pub type GPIO32_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO32_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO32_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO32_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO32_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO32_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO32_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO32_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO32_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO32_FILTER_EN` reader - input filter enable"] +pub type GPIO32_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO32_FILTER_EN` writer - input filter enable"] +pub type GPIO32_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO32_RUE_I3C` reader - NA"] +pub type GPIO32_RUE_I3C_R = crate::BitReader; +#[doc = "Field `GPIO32_RUE_I3C` writer - NA"] +pub type GPIO32_RUE_I3C_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO32_RU_I3C` reader - NA"] +pub type GPIO32_RU_I3C_R = crate::FieldReader; +#[doc = "Field `GPIO32_RU_I3C` writer - NA"] +pub type GPIO32_RU_I3C_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO32_RUE_SEL_I3C` reader - NA"] +pub type GPIO32_RUE_SEL_I3C_R = crate::BitReader; +#[doc = "Field `GPIO32_RUE_SEL_I3C` writer - NA"] +pub type GPIO32_RUE_SEL_I3C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio32_mcu_oe(&self) -> GPIO32_MCU_OE_R { + GPIO32_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio32_slp_sel(&self) -> GPIO32_SLP_SEL_R { + GPIO32_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio32_mcu_wpd(&self) -> GPIO32_MCU_WPD_R { + GPIO32_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio32_mcu_wpu(&self) -> GPIO32_MCU_WPU_R { + GPIO32_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio32_mcu_ie(&self) -> GPIO32_MCU_IE_R { + GPIO32_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio32_mcu_drv(&self) -> GPIO32_MCU_DRV_R { + GPIO32_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio32_fun_wpd(&self) -> GPIO32_FUN_WPD_R { + GPIO32_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio32_fun_wpu(&self) -> GPIO32_FUN_WPU_R { + GPIO32_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio32_fun_ie(&self) -> GPIO32_FUN_IE_R { + GPIO32_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio32_fun_drv(&self) -> GPIO32_FUN_DRV_R { + GPIO32_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio32_mcu_sel(&self) -> GPIO32_MCU_SEL_R { + GPIO32_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio32_filter_en(&self) -> GPIO32_FILTER_EN_R { + GPIO32_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn gpio32_rue_i3c(&self) -> GPIO32_RUE_I3C_R { + GPIO32_RUE_I3C_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:18 - NA"] + #[inline(always)] + pub fn gpio32_ru_i3c(&self) -> GPIO32_RU_I3C_R { + GPIO32_RU_I3C_R::new(((self.bits >> 17) & 3) as u8) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn gpio32_rue_sel_i3c(&self) -> GPIO32_RUE_SEL_I3C_R { + GPIO32_RUE_SEL_I3C_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio32") + .field( + "gpio32_mcu_oe", + &format_args!("{}", self.gpio32_mcu_oe().bit()), + ) + .field( + "gpio32_slp_sel", + &format_args!("{}", self.gpio32_slp_sel().bit()), + ) + .field( + "gpio32_mcu_wpd", + &format_args!("{}", self.gpio32_mcu_wpd().bit()), + ) + .field( + "gpio32_mcu_wpu", + &format_args!("{}", self.gpio32_mcu_wpu().bit()), + ) + .field( + "gpio32_mcu_ie", + &format_args!("{}", self.gpio32_mcu_ie().bit()), + ) + .field( + "gpio32_mcu_drv", + &format_args!("{}", self.gpio32_mcu_drv().bits()), + ) + .field( + "gpio32_fun_wpd", + &format_args!("{}", self.gpio32_fun_wpd().bit()), + ) + .field( + "gpio32_fun_wpu", + &format_args!("{}", self.gpio32_fun_wpu().bit()), + ) + .field( + "gpio32_fun_ie", + &format_args!("{}", self.gpio32_fun_ie().bit()), + ) + .field( + "gpio32_fun_drv", + &format_args!("{}", self.gpio32_fun_drv().bits()), + ) + .field( + "gpio32_mcu_sel", + &format_args!("{}", self.gpio32_mcu_sel().bits()), + ) + .field( + "gpio32_filter_en", + &format_args!("{}", self.gpio32_filter_en().bit()), + ) + .field( + "gpio32_rue_i3c", + &format_args!("{}", self.gpio32_rue_i3c().bit()), + ) + .field( + "gpio32_ru_i3c", + &format_args!("{}", self.gpio32_ru_i3c().bits()), + ) + .field( + "gpio32_rue_sel_i3c", + &format_args!("{}", self.gpio32_rue_sel_i3c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio32_mcu_oe(&mut self) -> GPIO32_MCU_OE_W { + GPIO32_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio32_slp_sel(&mut self) -> GPIO32_SLP_SEL_W { + GPIO32_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio32_mcu_wpd(&mut self) -> GPIO32_MCU_WPD_W { + GPIO32_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio32_mcu_wpu(&mut self) -> GPIO32_MCU_WPU_W { + GPIO32_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio32_mcu_ie(&mut self) -> GPIO32_MCU_IE_W { + GPIO32_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio32_mcu_drv(&mut self) -> GPIO32_MCU_DRV_W { + GPIO32_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio32_fun_wpd(&mut self) -> GPIO32_FUN_WPD_W { + GPIO32_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio32_fun_wpu(&mut self) -> GPIO32_FUN_WPU_W { + GPIO32_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio32_fun_ie(&mut self) -> GPIO32_FUN_IE_W { + GPIO32_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio32_fun_drv(&mut self) -> GPIO32_FUN_DRV_W { + GPIO32_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio32_mcu_sel(&mut self) -> GPIO32_MCU_SEL_W { + GPIO32_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio32_filter_en(&mut self) -> GPIO32_FILTER_EN_W { + GPIO32_FILTER_EN_W::new(self, 15) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn gpio32_rue_i3c(&mut self) -> GPIO32_RUE_I3C_W { + GPIO32_RUE_I3C_W::new(self, 16) + } + #[doc = "Bits 17:18 - NA"] + #[inline(always)] + #[must_use] + pub fn gpio32_ru_i3c(&mut self) -> GPIO32_RU_I3C_W { + GPIO32_RU_I3C_W::new(self, 17) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn gpio32_rue_sel_i3c(&mut self) -> GPIO32_RUE_SEL_I3C_W { + GPIO32_RUE_SEL_I3C_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio32\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio32::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio32::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO32_SPEC; +impl crate::RegisterSpec for GPIO32_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio32::R`](R) reader structure"] +impl crate::Readable for GPIO32_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio32::W`](W) writer structure"] +impl crate::Writable for GPIO32_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio32 to value 0x0800"] +impl crate::Resettable for GPIO32_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio33.rs b/esp32p4/src/io_mux/gpio33.rs new file mode 100644 index 0000000000..b9f970f694 --- /dev/null +++ b/esp32p4/src/io_mux/gpio33.rs @@ -0,0 +1,332 @@ +#[doc = "Register `gpio33` reader"] +pub type R = crate::R; +#[doc = "Register `gpio33` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO33_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO33_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO33_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO33_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO33_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO33_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO33_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO33_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO33_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO33_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO33_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO33_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO33_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO33_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO33_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO33_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO33_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO33_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO33_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO33_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO33_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO33_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO33_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO33_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO33_FUN_WPD` reader - pull-down enable"] +pub type GPIO33_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO33_FUN_WPD` writer - pull-down enable"] +pub type GPIO33_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO33_FUN_WPU` reader - pull-up enable"] +pub type GPIO33_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO33_FUN_WPU` writer - pull-up enable"] +pub type GPIO33_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO33_FUN_IE` reader - input enable"] +pub type GPIO33_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO33_FUN_IE` writer - input enable"] +pub type GPIO33_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO33_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO33_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO33_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO33_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO33_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO33_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO33_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO33_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO33_FILTER_EN` reader - input filter enable"] +pub type GPIO33_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO33_FILTER_EN` writer - input filter enable"] +pub type GPIO33_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO33_RUE_I3C` reader - NA"] +pub type GPIO33_RUE_I3C_R = crate::BitReader; +#[doc = "Field `GPIO33_RUE_I3C` writer - NA"] +pub type GPIO33_RUE_I3C_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO33_RU_I3C` reader - NA"] +pub type GPIO33_RU_I3C_R = crate::FieldReader; +#[doc = "Field `GPIO33_RU_I3C` writer - NA"] +pub type GPIO33_RU_I3C_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO33_RUE_SEL_I3C` reader - NA"] +pub type GPIO33_RUE_SEL_I3C_R = crate::BitReader; +#[doc = "Field `GPIO33_RUE_SEL_I3C` writer - NA"] +pub type GPIO33_RUE_SEL_I3C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio33_mcu_oe(&self) -> GPIO33_MCU_OE_R { + GPIO33_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio33_slp_sel(&self) -> GPIO33_SLP_SEL_R { + GPIO33_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio33_mcu_wpd(&self) -> GPIO33_MCU_WPD_R { + GPIO33_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio33_mcu_wpu(&self) -> GPIO33_MCU_WPU_R { + GPIO33_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio33_mcu_ie(&self) -> GPIO33_MCU_IE_R { + GPIO33_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio33_mcu_drv(&self) -> GPIO33_MCU_DRV_R { + GPIO33_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio33_fun_wpd(&self) -> GPIO33_FUN_WPD_R { + GPIO33_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio33_fun_wpu(&self) -> GPIO33_FUN_WPU_R { + GPIO33_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio33_fun_ie(&self) -> GPIO33_FUN_IE_R { + GPIO33_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio33_fun_drv(&self) -> GPIO33_FUN_DRV_R { + GPIO33_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio33_mcu_sel(&self) -> GPIO33_MCU_SEL_R { + GPIO33_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio33_filter_en(&self) -> GPIO33_FILTER_EN_R { + GPIO33_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn gpio33_rue_i3c(&self) -> GPIO33_RUE_I3C_R { + GPIO33_RUE_I3C_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:18 - NA"] + #[inline(always)] + pub fn gpio33_ru_i3c(&self) -> GPIO33_RU_I3C_R { + GPIO33_RU_I3C_R::new(((self.bits >> 17) & 3) as u8) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn gpio33_rue_sel_i3c(&self) -> GPIO33_RUE_SEL_I3C_R { + GPIO33_RUE_SEL_I3C_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio33") + .field( + "gpio33_mcu_oe", + &format_args!("{}", self.gpio33_mcu_oe().bit()), + ) + .field( + "gpio33_slp_sel", + &format_args!("{}", self.gpio33_slp_sel().bit()), + ) + .field( + "gpio33_mcu_wpd", + &format_args!("{}", self.gpio33_mcu_wpd().bit()), + ) + .field( + "gpio33_mcu_wpu", + &format_args!("{}", self.gpio33_mcu_wpu().bit()), + ) + .field( + "gpio33_mcu_ie", + &format_args!("{}", self.gpio33_mcu_ie().bit()), + ) + .field( + "gpio33_mcu_drv", + &format_args!("{}", self.gpio33_mcu_drv().bits()), + ) + .field( + "gpio33_fun_wpd", + &format_args!("{}", self.gpio33_fun_wpd().bit()), + ) + .field( + "gpio33_fun_wpu", + &format_args!("{}", self.gpio33_fun_wpu().bit()), + ) + .field( + "gpio33_fun_ie", + &format_args!("{}", self.gpio33_fun_ie().bit()), + ) + .field( + "gpio33_fun_drv", + &format_args!("{}", self.gpio33_fun_drv().bits()), + ) + .field( + "gpio33_mcu_sel", + &format_args!("{}", self.gpio33_mcu_sel().bits()), + ) + .field( + "gpio33_filter_en", + &format_args!("{}", self.gpio33_filter_en().bit()), + ) + .field( + "gpio33_rue_i3c", + &format_args!("{}", self.gpio33_rue_i3c().bit()), + ) + .field( + "gpio33_ru_i3c", + &format_args!("{}", self.gpio33_ru_i3c().bits()), + ) + .field( + "gpio33_rue_sel_i3c", + &format_args!("{}", self.gpio33_rue_sel_i3c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio33_mcu_oe(&mut self) -> GPIO33_MCU_OE_W { + GPIO33_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio33_slp_sel(&mut self) -> GPIO33_SLP_SEL_W { + GPIO33_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio33_mcu_wpd(&mut self) -> GPIO33_MCU_WPD_W { + GPIO33_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio33_mcu_wpu(&mut self) -> GPIO33_MCU_WPU_W { + GPIO33_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio33_mcu_ie(&mut self) -> GPIO33_MCU_IE_W { + GPIO33_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio33_mcu_drv(&mut self) -> GPIO33_MCU_DRV_W { + GPIO33_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio33_fun_wpd(&mut self) -> GPIO33_FUN_WPD_W { + GPIO33_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio33_fun_wpu(&mut self) -> GPIO33_FUN_WPU_W { + GPIO33_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio33_fun_ie(&mut self) -> GPIO33_FUN_IE_W { + GPIO33_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio33_fun_drv(&mut self) -> GPIO33_FUN_DRV_W { + GPIO33_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio33_mcu_sel(&mut self) -> GPIO33_MCU_SEL_W { + GPIO33_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio33_filter_en(&mut self) -> GPIO33_FILTER_EN_W { + GPIO33_FILTER_EN_W::new(self, 15) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn gpio33_rue_i3c(&mut self) -> GPIO33_RUE_I3C_W { + GPIO33_RUE_I3C_W::new(self, 16) + } + #[doc = "Bits 17:18 - NA"] + #[inline(always)] + #[must_use] + pub fn gpio33_ru_i3c(&mut self) -> GPIO33_RU_I3C_W { + GPIO33_RU_I3C_W::new(self, 17) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn gpio33_rue_sel_i3c(&mut self) -> GPIO33_RUE_SEL_I3C_W { + GPIO33_RUE_SEL_I3C_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio33\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio33::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio33::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO33_SPEC; +impl crate::RegisterSpec for GPIO33_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio33::R`](R) reader structure"] +impl crate::Readable for GPIO33_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio33::W`](W) writer structure"] +impl crate::Writable for GPIO33_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio33 to value 0x0800"] +impl crate::Resettable for GPIO33_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio34.rs b/esp32p4/src/io_mux/gpio34.rs new file mode 100644 index 0000000000..628d215124 --- /dev/null +++ b/esp32p4/src/io_mux/gpio34.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio34` reader"] +pub type R = crate::R; +#[doc = "Register `gpio34` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO34_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO34_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO34_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO34_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO34_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO34_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO34_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO34_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO34_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO34_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO34_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO34_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO34_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO34_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO34_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO34_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO34_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO34_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO34_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO34_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO34_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO34_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO34_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO34_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO34_FUN_WPD` reader - pull-down enable"] +pub type GPIO34_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO34_FUN_WPD` writer - pull-down enable"] +pub type GPIO34_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO34_FUN_WPU` reader - pull-up enable"] +pub type GPIO34_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO34_FUN_WPU` writer - pull-up enable"] +pub type GPIO34_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO34_FUN_IE` reader - input enable"] +pub type GPIO34_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO34_FUN_IE` writer - input enable"] +pub type GPIO34_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO34_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO34_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO34_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO34_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO34_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO34_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO34_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO34_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO34_FILTER_EN` reader - input filter enable"] +pub type GPIO34_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO34_FILTER_EN` writer - input filter enable"] +pub type GPIO34_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio34_mcu_oe(&self) -> GPIO34_MCU_OE_R { + GPIO34_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio34_slp_sel(&self) -> GPIO34_SLP_SEL_R { + GPIO34_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio34_mcu_wpd(&self) -> GPIO34_MCU_WPD_R { + GPIO34_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio34_mcu_wpu(&self) -> GPIO34_MCU_WPU_R { + GPIO34_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio34_mcu_ie(&self) -> GPIO34_MCU_IE_R { + GPIO34_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio34_mcu_drv(&self) -> GPIO34_MCU_DRV_R { + GPIO34_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio34_fun_wpd(&self) -> GPIO34_FUN_WPD_R { + GPIO34_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio34_fun_wpu(&self) -> GPIO34_FUN_WPU_R { + GPIO34_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio34_fun_ie(&self) -> GPIO34_FUN_IE_R { + GPIO34_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio34_fun_drv(&self) -> GPIO34_FUN_DRV_R { + GPIO34_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio34_mcu_sel(&self) -> GPIO34_MCU_SEL_R { + GPIO34_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio34_filter_en(&self) -> GPIO34_FILTER_EN_R { + GPIO34_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio34") + .field( + "gpio34_mcu_oe", + &format_args!("{}", self.gpio34_mcu_oe().bit()), + ) + .field( + "gpio34_slp_sel", + &format_args!("{}", self.gpio34_slp_sel().bit()), + ) + .field( + "gpio34_mcu_wpd", + &format_args!("{}", self.gpio34_mcu_wpd().bit()), + ) + .field( + "gpio34_mcu_wpu", + &format_args!("{}", self.gpio34_mcu_wpu().bit()), + ) + .field( + "gpio34_mcu_ie", + &format_args!("{}", self.gpio34_mcu_ie().bit()), + ) + .field( + "gpio34_mcu_drv", + &format_args!("{}", self.gpio34_mcu_drv().bits()), + ) + .field( + "gpio34_fun_wpd", + &format_args!("{}", self.gpio34_fun_wpd().bit()), + ) + .field( + "gpio34_fun_wpu", + &format_args!("{}", self.gpio34_fun_wpu().bit()), + ) + .field( + "gpio34_fun_ie", + &format_args!("{}", self.gpio34_fun_ie().bit()), + ) + .field( + "gpio34_fun_drv", + &format_args!("{}", self.gpio34_fun_drv().bits()), + ) + .field( + "gpio34_mcu_sel", + &format_args!("{}", self.gpio34_mcu_sel().bits()), + ) + .field( + "gpio34_filter_en", + &format_args!("{}", self.gpio34_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio34_mcu_oe(&mut self) -> GPIO34_MCU_OE_W { + GPIO34_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio34_slp_sel(&mut self) -> GPIO34_SLP_SEL_W { + GPIO34_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio34_mcu_wpd(&mut self) -> GPIO34_MCU_WPD_W { + GPIO34_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio34_mcu_wpu(&mut self) -> GPIO34_MCU_WPU_W { + GPIO34_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio34_mcu_ie(&mut self) -> GPIO34_MCU_IE_W { + GPIO34_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio34_mcu_drv(&mut self) -> GPIO34_MCU_DRV_W { + GPIO34_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio34_fun_wpd(&mut self) -> GPIO34_FUN_WPD_W { + GPIO34_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio34_fun_wpu(&mut self) -> GPIO34_FUN_WPU_W { + GPIO34_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio34_fun_ie(&mut self) -> GPIO34_FUN_IE_W { + GPIO34_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio34_fun_drv(&mut self) -> GPIO34_FUN_DRV_W { + GPIO34_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio34_mcu_sel(&mut self) -> GPIO34_MCU_SEL_W { + GPIO34_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio34_filter_en(&mut self) -> GPIO34_FILTER_EN_W { + GPIO34_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio34::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio34::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO34_SPEC; +impl crate::RegisterSpec for GPIO34_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio34::R`](R) reader structure"] +impl crate::Readable for GPIO34_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio34::W`](W) writer structure"] +impl crate::Writable for GPIO34_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio34 to value 0x0800"] +impl crate::Resettable for GPIO34_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio35.rs b/esp32p4/src/io_mux/gpio35.rs new file mode 100644 index 0000000000..3bed67f48c --- /dev/null +++ b/esp32p4/src/io_mux/gpio35.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio35` reader"] +pub type R = crate::R; +#[doc = "Register `gpio35` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO35_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO35_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO35_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO35_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO35_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO35_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO35_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO35_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO35_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO35_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO35_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO35_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO35_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO35_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO35_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO35_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO35_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO35_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO35_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO35_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO35_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO35_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO35_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO35_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO35_FUN_WPD` reader - pull-down enable"] +pub type GPIO35_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO35_FUN_WPD` writer - pull-down enable"] +pub type GPIO35_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO35_FUN_WPU` reader - pull-up enable"] +pub type GPIO35_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO35_FUN_WPU` writer - pull-up enable"] +pub type GPIO35_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO35_FUN_IE` reader - input enable"] +pub type GPIO35_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO35_FUN_IE` writer - input enable"] +pub type GPIO35_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO35_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO35_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO35_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO35_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO35_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO35_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO35_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO35_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO35_FILTER_EN` reader - input filter enable"] +pub type GPIO35_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO35_FILTER_EN` writer - input filter enable"] +pub type GPIO35_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio35_mcu_oe(&self) -> GPIO35_MCU_OE_R { + GPIO35_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio35_slp_sel(&self) -> GPIO35_SLP_SEL_R { + GPIO35_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio35_mcu_wpd(&self) -> GPIO35_MCU_WPD_R { + GPIO35_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio35_mcu_wpu(&self) -> GPIO35_MCU_WPU_R { + GPIO35_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio35_mcu_ie(&self) -> GPIO35_MCU_IE_R { + GPIO35_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio35_mcu_drv(&self) -> GPIO35_MCU_DRV_R { + GPIO35_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio35_fun_wpd(&self) -> GPIO35_FUN_WPD_R { + GPIO35_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio35_fun_wpu(&self) -> GPIO35_FUN_WPU_R { + GPIO35_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio35_fun_ie(&self) -> GPIO35_FUN_IE_R { + GPIO35_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio35_fun_drv(&self) -> GPIO35_FUN_DRV_R { + GPIO35_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio35_mcu_sel(&self) -> GPIO35_MCU_SEL_R { + GPIO35_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio35_filter_en(&self) -> GPIO35_FILTER_EN_R { + GPIO35_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio35") + .field( + "gpio35_mcu_oe", + &format_args!("{}", self.gpio35_mcu_oe().bit()), + ) + .field( + "gpio35_slp_sel", + &format_args!("{}", self.gpio35_slp_sel().bit()), + ) + .field( + "gpio35_mcu_wpd", + &format_args!("{}", self.gpio35_mcu_wpd().bit()), + ) + .field( + "gpio35_mcu_wpu", + &format_args!("{}", self.gpio35_mcu_wpu().bit()), + ) + .field( + "gpio35_mcu_ie", + &format_args!("{}", self.gpio35_mcu_ie().bit()), + ) + .field( + "gpio35_mcu_drv", + &format_args!("{}", self.gpio35_mcu_drv().bits()), + ) + .field( + "gpio35_fun_wpd", + &format_args!("{}", self.gpio35_fun_wpd().bit()), + ) + .field( + "gpio35_fun_wpu", + &format_args!("{}", self.gpio35_fun_wpu().bit()), + ) + .field( + "gpio35_fun_ie", + &format_args!("{}", self.gpio35_fun_ie().bit()), + ) + .field( + "gpio35_fun_drv", + &format_args!("{}", self.gpio35_fun_drv().bits()), + ) + .field( + "gpio35_mcu_sel", + &format_args!("{}", self.gpio35_mcu_sel().bits()), + ) + .field( + "gpio35_filter_en", + &format_args!("{}", self.gpio35_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio35_mcu_oe(&mut self) -> GPIO35_MCU_OE_W { + GPIO35_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio35_slp_sel(&mut self) -> GPIO35_SLP_SEL_W { + GPIO35_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio35_mcu_wpd(&mut self) -> GPIO35_MCU_WPD_W { + GPIO35_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio35_mcu_wpu(&mut self) -> GPIO35_MCU_WPU_W { + GPIO35_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio35_mcu_ie(&mut self) -> GPIO35_MCU_IE_W { + GPIO35_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio35_mcu_drv(&mut self) -> GPIO35_MCU_DRV_W { + GPIO35_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio35_fun_wpd(&mut self) -> GPIO35_FUN_WPD_W { + GPIO35_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio35_fun_wpu(&mut self) -> GPIO35_FUN_WPU_W { + GPIO35_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio35_fun_ie(&mut self) -> GPIO35_FUN_IE_W { + GPIO35_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio35_fun_drv(&mut self) -> GPIO35_FUN_DRV_W { + GPIO35_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio35_mcu_sel(&mut self) -> GPIO35_MCU_SEL_W { + GPIO35_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio35_filter_en(&mut self) -> GPIO35_FILTER_EN_W { + GPIO35_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio35\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio35::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio35::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO35_SPEC; +impl crate::RegisterSpec for GPIO35_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio35::R`](R) reader structure"] +impl crate::Readable for GPIO35_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio35::W`](W) writer structure"] +impl crate::Writable for GPIO35_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio35 to value 0x0800"] +impl crate::Resettable for GPIO35_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio36.rs b/esp32p4/src/io_mux/gpio36.rs new file mode 100644 index 0000000000..bd0d244371 --- /dev/null +++ b/esp32p4/src/io_mux/gpio36.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio36` reader"] +pub type R = crate::R; +#[doc = "Register `gpio36` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO36_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO36_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO36_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO36_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO36_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO36_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO36_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO36_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO36_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO36_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO36_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO36_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO36_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO36_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO36_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO36_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO36_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO36_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO36_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO36_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO36_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO36_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO36_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO36_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO36_FUN_WPD` reader - pull-down enable"] +pub type GPIO36_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO36_FUN_WPD` writer - pull-down enable"] +pub type GPIO36_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO36_FUN_WPU` reader - pull-up enable"] +pub type GPIO36_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO36_FUN_WPU` writer - pull-up enable"] +pub type GPIO36_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO36_FUN_IE` reader - input enable"] +pub type GPIO36_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO36_FUN_IE` writer - input enable"] +pub type GPIO36_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO36_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO36_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO36_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO36_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO36_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO36_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO36_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO36_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO36_FILTER_EN` reader - input filter enable"] +pub type GPIO36_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO36_FILTER_EN` writer - input filter enable"] +pub type GPIO36_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio36_mcu_oe(&self) -> GPIO36_MCU_OE_R { + GPIO36_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio36_slp_sel(&self) -> GPIO36_SLP_SEL_R { + GPIO36_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio36_mcu_wpd(&self) -> GPIO36_MCU_WPD_R { + GPIO36_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio36_mcu_wpu(&self) -> GPIO36_MCU_WPU_R { + GPIO36_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio36_mcu_ie(&self) -> GPIO36_MCU_IE_R { + GPIO36_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio36_mcu_drv(&self) -> GPIO36_MCU_DRV_R { + GPIO36_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio36_fun_wpd(&self) -> GPIO36_FUN_WPD_R { + GPIO36_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio36_fun_wpu(&self) -> GPIO36_FUN_WPU_R { + GPIO36_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio36_fun_ie(&self) -> GPIO36_FUN_IE_R { + GPIO36_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio36_fun_drv(&self) -> GPIO36_FUN_DRV_R { + GPIO36_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio36_mcu_sel(&self) -> GPIO36_MCU_SEL_R { + GPIO36_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio36_filter_en(&self) -> GPIO36_FILTER_EN_R { + GPIO36_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio36") + .field( + "gpio36_mcu_oe", + &format_args!("{}", self.gpio36_mcu_oe().bit()), + ) + .field( + "gpio36_slp_sel", + &format_args!("{}", self.gpio36_slp_sel().bit()), + ) + .field( + "gpio36_mcu_wpd", + &format_args!("{}", self.gpio36_mcu_wpd().bit()), + ) + .field( + "gpio36_mcu_wpu", + &format_args!("{}", self.gpio36_mcu_wpu().bit()), + ) + .field( + "gpio36_mcu_ie", + &format_args!("{}", self.gpio36_mcu_ie().bit()), + ) + .field( + "gpio36_mcu_drv", + &format_args!("{}", self.gpio36_mcu_drv().bits()), + ) + .field( + "gpio36_fun_wpd", + &format_args!("{}", self.gpio36_fun_wpd().bit()), + ) + .field( + "gpio36_fun_wpu", + &format_args!("{}", self.gpio36_fun_wpu().bit()), + ) + .field( + "gpio36_fun_ie", + &format_args!("{}", self.gpio36_fun_ie().bit()), + ) + .field( + "gpio36_fun_drv", + &format_args!("{}", self.gpio36_fun_drv().bits()), + ) + .field( + "gpio36_mcu_sel", + &format_args!("{}", self.gpio36_mcu_sel().bits()), + ) + .field( + "gpio36_filter_en", + &format_args!("{}", self.gpio36_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio36_mcu_oe(&mut self) -> GPIO36_MCU_OE_W { + GPIO36_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio36_slp_sel(&mut self) -> GPIO36_SLP_SEL_W { + GPIO36_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio36_mcu_wpd(&mut self) -> GPIO36_MCU_WPD_W { + GPIO36_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio36_mcu_wpu(&mut self) -> GPIO36_MCU_WPU_W { + GPIO36_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio36_mcu_ie(&mut self) -> GPIO36_MCU_IE_W { + GPIO36_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio36_mcu_drv(&mut self) -> GPIO36_MCU_DRV_W { + GPIO36_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio36_fun_wpd(&mut self) -> GPIO36_FUN_WPD_W { + GPIO36_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio36_fun_wpu(&mut self) -> GPIO36_FUN_WPU_W { + GPIO36_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio36_fun_ie(&mut self) -> GPIO36_FUN_IE_W { + GPIO36_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio36_fun_drv(&mut self) -> GPIO36_FUN_DRV_W { + GPIO36_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio36_mcu_sel(&mut self) -> GPIO36_MCU_SEL_W { + GPIO36_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio36_filter_en(&mut self) -> GPIO36_FILTER_EN_W { + GPIO36_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio36\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio36::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio36::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO36_SPEC; +impl crate::RegisterSpec for GPIO36_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio36::R`](R) reader structure"] +impl crate::Readable for GPIO36_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio36::W`](W) writer structure"] +impl crate::Writable for GPIO36_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio36 to value 0x0800"] +impl crate::Resettable for GPIO36_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio37.rs b/esp32p4/src/io_mux/gpio37.rs new file mode 100644 index 0000000000..7e43d979c4 --- /dev/null +++ b/esp32p4/src/io_mux/gpio37.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio37` reader"] +pub type R = crate::R; +#[doc = "Register `gpio37` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO37_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO37_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO37_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO37_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO37_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO37_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO37_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO37_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO37_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO37_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO37_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO37_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO37_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO37_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO37_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO37_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO37_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO37_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO37_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO37_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO37_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO37_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO37_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO37_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO37_FUN_WPD` reader - pull-down enable"] +pub type GPIO37_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO37_FUN_WPD` writer - pull-down enable"] +pub type GPIO37_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO37_FUN_WPU` reader - pull-up enable"] +pub type GPIO37_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO37_FUN_WPU` writer - pull-up enable"] +pub type GPIO37_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO37_FUN_IE` reader - input enable"] +pub type GPIO37_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO37_FUN_IE` writer - input enable"] +pub type GPIO37_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO37_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO37_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO37_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO37_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO37_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO37_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO37_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO37_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO37_FILTER_EN` reader - input filter enable"] +pub type GPIO37_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO37_FILTER_EN` writer - input filter enable"] +pub type GPIO37_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio37_mcu_oe(&self) -> GPIO37_MCU_OE_R { + GPIO37_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio37_slp_sel(&self) -> GPIO37_SLP_SEL_R { + GPIO37_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio37_mcu_wpd(&self) -> GPIO37_MCU_WPD_R { + GPIO37_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio37_mcu_wpu(&self) -> GPIO37_MCU_WPU_R { + GPIO37_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio37_mcu_ie(&self) -> GPIO37_MCU_IE_R { + GPIO37_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio37_mcu_drv(&self) -> GPIO37_MCU_DRV_R { + GPIO37_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio37_fun_wpd(&self) -> GPIO37_FUN_WPD_R { + GPIO37_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio37_fun_wpu(&self) -> GPIO37_FUN_WPU_R { + GPIO37_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio37_fun_ie(&self) -> GPIO37_FUN_IE_R { + GPIO37_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio37_fun_drv(&self) -> GPIO37_FUN_DRV_R { + GPIO37_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio37_mcu_sel(&self) -> GPIO37_MCU_SEL_R { + GPIO37_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio37_filter_en(&self) -> GPIO37_FILTER_EN_R { + GPIO37_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio37") + .field( + "gpio37_mcu_oe", + &format_args!("{}", self.gpio37_mcu_oe().bit()), + ) + .field( + "gpio37_slp_sel", + &format_args!("{}", self.gpio37_slp_sel().bit()), + ) + .field( + "gpio37_mcu_wpd", + &format_args!("{}", self.gpio37_mcu_wpd().bit()), + ) + .field( + "gpio37_mcu_wpu", + &format_args!("{}", self.gpio37_mcu_wpu().bit()), + ) + .field( + "gpio37_mcu_ie", + &format_args!("{}", self.gpio37_mcu_ie().bit()), + ) + .field( + "gpio37_mcu_drv", + &format_args!("{}", self.gpio37_mcu_drv().bits()), + ) + .field( + "gpio37_fun_wpd", + &format_args!("{}", self.gpio37_fun_wpd().bit()), + ) + .field( + "gpio37_fun_wpu", + &format_args!("{}", self.gpio37_fun_wpu().bit()), + ) + .field( + "gpio37_fun_ie", + &format_args!("{}", self.gpio37_fun_ie().bit()), + ) + .field( + "gpio37_fun_drv", + &format_args!("{}", self.gpio37_fun_drv().bits()), + ) + .field( + "gpio37_mcu_sel", + &format_args!("{}", self.gpio37_mcu_sel().bits()), + ) + .field( + "gpio37_filter_en", + &format_args!("{}", self.gpio37_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio37_mcu_oe(&mut self) -> GPIO37_MCU_OE_W { + GPIO37_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio37_slp_sel(&mut self) -> GPIO37_SLP_SEL_W { + GPIO37_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio37_mcu_wpd(&mut self) -> GPIO37_MCU_WPD_W { + GPIO37_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio37_mcu_wpu(&mut self) -> GPIO37_MCU_WPU_W { + GPIO37_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio37_mcu_ie(&mut self) -> GPIO37_MCU_IE_W { + GPIO37_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio37_mcu_drv(&mut self) -> GPIO37_MCU_DRV_W { + GPIO37_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio37_fun_wpd(&mut self) -> GPIO37_FUN_WPD_W { + GPIO37_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio37_fun_wpu(&mut self) -> GPIO37_FUN_WPU_W { + GPIO37_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio37_fun_ie(&mut self) -> GPIO37_FUN_IE_W { + GPIO37_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio37_fun_drv(&mut self) -> GPIO37_FUN_DRV_W { + GPIO37_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio37_mcu_sel(&mut self) -> GPIO37_MCU_SEL_W { + GPIO37_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio37_filter_en(&mut self) -> GPIO37_FILTER_EN_W { + GPIO37_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio37\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio37::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio37::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO37_SPEC; +impl crate::RegisterSpec for GPIO37_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio37::R`](R) reader structure"] +impl crate::Readable for GPIO37_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio37::W`](W) writer structure"] +impl crate::Writable for GPIO37_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio37 to value 0x0800"] +impl crate::Resettable for GPIO37_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio38.rs b/esp32p4/src/io_mux/gpio38.rs new file mode 100644 index 0000000000..837dcfc208 --- /dev/null +++ b/esp32p4/src/io_mux/gpio38.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio38` reader"] +pub type R = crate::R; +#[doc = "Register `gpio38` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO38_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO38_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO38_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO38_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO38_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO38_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO38_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO38_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO38_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO38_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO38_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO38_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO38_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO38_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO38_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO38_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO38_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO38_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO38_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO38_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO38_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO38_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO38_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO38_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO38_FUN_WPD` reader - pull-down enable"] +pub type GPIO38_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO38_FUN_WPD` writer - pull-down enable"] +pub type GPIO38_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO38_FUN_WPU` reader - pull-up enable"] +pub type GPIO38_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO38_FUN_WPU` writer - pull-up enable"] +pub type GPIO38_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO38_FUN_IE` reader - input enable"] +pub type GPIO38_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO38_FUN_IE` writer - input enable"] +pub type GPIO38_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO38_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO38_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO38_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO38_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO38_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO38_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO38_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO38_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO38_FILTER_EN` reader - input filter enable"] +pub type GPIO38_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO38_FILTER_EN` writer - input filter enable"] +pub type GPIO38_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio38_mcu_oe(&self) -> GPIO38_MCU_OE_R { + GPIO38_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio38_slp_sel(&self) -> GPIO38_SLP_SEL_R { + GPIO38_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio38_mcu_wpd(&self) -> GPIO38_MCU_WPD_R { + GPIO38_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio38_mcu_wpu(&self) -> GPIO38_MCU_WPU_R { + GPIO38_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio38_mcu_ie(&self) -> GPIO38_MCU_IE_R { + GPIO38_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio38_mcu_drv(&self) -> GPIO38_MCU_DRV_R { + GPIO38_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio38_fun_wpd(&self) -> GPIO38_FUN_WPD_R { + GPIO38_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio38_fun_wpu(&self) -> GPIO38_FUN_WPU_R { + GPIO38_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio38_fun_ie(&self) -> GPIO38_FUN_IE_R { + GPIO38_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio38_fun_drv(&self) -> GPIO38_FUN_DRV_R { + GPIO38_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio38_mcu_sel(&self) -> GPIO38_MCU_SEL_R { + GPIO38_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio38_filter_en(&self) -> GPIO38_FILTER_EN_R { + GPIO38_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio38") + .field( + "gpio38_mcu_oe", + &format_args!("{}", self.gpio38_mcu_oe().bit()), + ) + .field( + "gpio38_slp_sel", + &format_args!("{}", self.gpio38_slp_sel().bit()), + ) + .field( + "gpio38_mcu_wpd", + &format_args!("{}", self.gpio38_mcu_wpd().bit()), + ) + .field( + "gpio38_mcu_wpu", + &format_args!("{}", self.gpio38_mcu_wpu().bit()), + ) + .field( + "gpio38_mcu_ie", + &format_args!("{}", self.gpio38_mcu_ie().bit()), + ) + .field( + "gpio38_mcu_drv", + &format_args!("{}", self.gpio38_mcu_drv().bits()), + ) + .field( + "gpio38_fun_wpd", + &format_args!("{}", self.gpio38_fun_wpd().bit()), + ) + .field( + "gpio38_fun_wpu", + &format_args!("{}", self.gpio38_fun_wpu().bit()), + ) + .field( + "gpio38_fun_ie", + &format_args!("{}", self.gpio38_fun_ie().bit()), + ) + .field( + "gpio38_fun_drv", + &format_args!("{}", self.gpio38_fun_drv().bits()), + ) + .field( + "gpio38_mcu_sel", + &format_args!("{}", self.gpio38_mcu_sel().bits()), + ) + .field( + "gpio38_filter_en", + &format_args!("{}", self.gpio38_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio38_mcu_oe(&mut self) -> GPIO38_MCU_OE_W { + GPIO38_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio38_slp_sel(&mut self) -> GPIO38_SLP_SEL_W { + GPIO38_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio38_mcu_wpd(&mut self) -> GPIO38_MCU_WPD_W { + GPIO38_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio38_mcu_wpu(&mut self) -> GPIO38_MCU_WPU_W { + GPIO38_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio38_mcu_ie(&mut self) -> GPIO38_MCU_IE_W { + GPIO38_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio38_mcu_drv(&mut self) -> GPIO38_MCU_DRV_W { + GPIO38_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio38_fun_wpd(&mut self) -> GPIO38_FUN_WPD_W { + GPIO38_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio38_fun_wpu(&mut self) -> GPIO38_FUN_WPU_W { + GPIO38_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio38_fun_ie(&mut self) -> GPIO38_FUN_IE_W { + GPIO38_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio38_fun_drv(&mut self) -> GPIO38_FUN_DRV_W { + GPIO38_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio38_mcu_sel(&mut self) -> GPIO38_MCU_SEL_W { + GPIO38_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio38_filter_en(&mut self) -> GPIO38_FILTER_EN_W { + GPIO38_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio38\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio38::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio38::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO38_SPEC; +impl crate::RegisterSpec for GPIO38_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio38::R`](R) reader structure"] +impl crate::Readable for GPIO38_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio38::W`](W) writer structure"] +impl crate::Writable for GPIO38_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio38 to value 0x0800"] +impl crate::Resettable for GPIO38_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio39.rs b/esp32p4/src/io_mux/gpio39.rs new file mode 100644 index 0000000000..9c481b4dc9 --- /dev/null +++ b/esp32p4/src/io_mux/gpio39.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio39` reader"] +pub type R = crate::R; +#[doc = "Register `gpio39` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO39_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO39_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO39_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO39_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO39_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO39_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO39_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO39_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO39_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO39_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO39_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO39_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO39_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO39_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO39_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO39_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO39_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO39_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO39_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO39_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO39_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO39_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO39_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO39_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO39_FUN_WPD` reader - pull-down enable"] +pub type GPIO39_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO39_FUN_WPD` writer - pull-down enable"] +pub type GPIO39_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO39_FUN_WPU` reader - pull-up enable"] +pub type GPIO39_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO39_FUN_WPU` writer - pull-up enable"] +pub type GPIO39_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO39_FUN_IE` reader - input enable"] +pub type GPIO39_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO39_FUN_IE` writer - input enable"] +pub type GPIO39_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO39_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO39_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO39_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO39_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO39_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO39_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO39_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO39_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO39_FILTER_EN` reader - input filter enable"] +pub type GPIO39_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO39_FILTER_EN` writer - input filter enable"] +pub type GPIO39_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio39_mcu_oe(&self) -> GPIO39_MCU_OE_R { + GPIO39_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio39_slp_sel(&self) -> GPIO39_SLP_SEL_R { + GPIO39_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio39_mcu_wpd(&self) -> GPIO39_MCU_WPD_R { + GPIO39_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio39_mcu_wpu(&self) -> GPIO39_MCU_WPU_R { + GPIO39_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio39_mcu_ie(&self) -> GPIO39_MCU_IE_R { + GPIO39_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio39_mcu_drv(&self) -> GPIO39_MCU_DRV_R { + GPIO39_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio39_fun_wpd(&self) -> GPIO39_FUN_WPD_R { + GPIO39_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio39_fun_wpu(&self) -> GPIO39_FUN_WPU_R { + GPIO39_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio39_fun_ie(&self) -> GPIO39_FUN_IE_R { + GPIO39_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio39_fun_drv(&self) -> GPIO39_FUN_DRV_R { + GPIO39_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio39_mcu_sel(&self) -> GPIO39_MCU_SEL_R { + GPIO39_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio39_filter_en(&self) -> GPIO39_FILTER_EN_R { + GPIO39_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio39") + .field( + "gpio39_mcu_oe", + &format_args!("{}", self.gpio39_mcu_oe().bit()), + ) + .field( + "gpio39_slp_sel", + &format_args!("{}", self.gpio39_slp_sel().bit()), + ) + .field( + "gpio39_mcu_wpd", + &format_args!("{}", self.gpio39_mcu_wpd().bit()), + ) + .field( + "gpio39_mcu_wpu", + &format_args!("{}", self.gpio39_mcu_wpu().bit()), + ) + .field( + "gpio39_mcu_ie", + &format_args!("{}", self.gpio39_mcu_ie().bit()), + ) + .field( + "gpio39_mcu_drv", + &format_args!("{}", self.gpio39_mcu_drv().bits()), + ) + .field( + "gpio39_fun_wpd", + &format_args!("{}", self.gpio39_fun_wpd().bit()), + ) + .field( + "gpio39_fun_wpu", + &format_args!("{}", self.gpio39_fun_wpu().bit()), + ) + .field( + "gpio39_fun_ie", + &format_args!("{}", self.gpio39_fun_ie().bit()), + ) + .field( + "gpio39_fun_drv", + &format_args!("{}", self.gpio39_fun_drv().bits()), + ) + .field( + "gpio39_mcu_sel", + &format_args!("{}", self.gpio39_mcu_sel().bits()), + ) + .field( + "gpio39_filter_en", + &format_args!("{}", self.gpio39_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio39_mcu_oe(&mut self) -> GPIO39_MCU_OE_W { + GPIO39_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio39_slp_sel(&mut self) -> GPIO39_SLP_SEL_W { + GPIO39_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio39_mcu_wpd(&mut self) -> GPIO39_MCU_WPD_W { + GPIO39_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio39_mcu_wpu(&mut self) -> GPIO39_MCU_WPU_W { + GPIO39_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio39_mcu_ie(&mut self) -> GPIO39_MCU_IE_W { + GPIO39_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio39_mcu_drv(&mut self) -> GPIO39_MCU_DRV_W { + GPIO39_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio39_fun_wpd(&mut self) -> GPIO39_FUN_WPD_W { + GPIO39_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio39_fun_wpu(&mut self) -> GPIO39_FUN_WPU_W { + GPIO39_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio39_fun_ie(&mut self) -> GPIO39_FUN_IE_W { + GPIO39_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio39_fun_drv(&mut self) -> GPIO39_FUN_DRV_W { + GPIO39_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio39_mcu_sel(&mut self) -> GPIO39_MCU_SEL_W { + GPIO39_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio39_filter_en(&mut self) -> GPIO39_FILTER_EN_W { + GPIO39_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio39\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio39::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio39::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO39_SPEC; +impl crate::RegisterSpec for GPIO39_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio39::R`](R) reader structure"] +impl crate::Readable for GPIO39_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio39::W`](W) writer structure"] +impl crate::Writable for GPIO39_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio39 to value 0x0800"] +impl crate::Resettable for GPIO39_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio4.rs b/esp32p4/src/io_mux/gpio4.rs new file mode 100644 index 0000000000..91b28eb1aa --- /dev/null +++ b/esp32p4/src/io_mux/gpio4.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio4` reader"] +pub type R = crate::R; +#[doc = "Register `gpio4` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO4_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO4_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO4_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO4_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO4_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO4_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO4_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO4_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO4_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO4_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO4_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO4_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO4_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO4_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO4_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO4_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO4_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO4_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO4_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO4_FUN_WPD` reader - pull-down enable"] +pub type GPIO4_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO4_FUN_WPD` writer - pull-down enable"] +pub type GPIO4_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_FUN_WPU` reader - pull-up enable"] +pub type GPIO4_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO4_FUN_WPU` writer - pull-up enable"] +pub type GPIO4_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_FUN_IE` reader - input enable"] +pub type GPIO4_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO4_FUN_IE` writer - input enable"] +pub type GPIO4_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO4_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO4_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO4_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO4_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO4_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO4_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO4_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO4_FILTER_EN` reader - input filter enable"] +pub type GPIO4_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO4_FILTER_EN` writer - input filter enable"] +pub type GPIO4_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio4_mcu_oe(&self) -> GPIO4_MCU_OE_R { + GPIO4_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio4_slp_sel(&self) -> GPIO4_SLP_SEL_R { + GPIO4_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio4_mcu_wpd(&self) -> GPIO4_MCU_WPD_R { + GPIO4_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio4_mcu_wpu(&self) -> GPIO4_MCU_WPU_R { + GPIO4_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio4_mcu_ie(&self) -> GPIO4_MCU_IE_R { + GPIO4_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio4_mcu_drv(&self) -> GPIO4_MCU_DRV_R { + GPIO4_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio4_fun_wpd(&self) -> GPIO4_FUN_WPD_R { + GPIO4_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio4_fun_wpu(&self) -> GPIO4_FUN_WPU_R { + GPIO4_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio4_fun_ie(&self) -> GPIO4_FUN_IE_R { + GPIO4_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio4_fun_drv(&self) -> GPIO4_FUN_DRV_R { + GPIO4_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio4_mcu_sel(&self) -> GPIO4_MCU_SEL_R { + GPIO4_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio4_filter_en(&self) -> GPIO4_FILTER_EN_R { + GPIO4_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio4") + .field( + "gpio4_mcu_oe", + &format_args!("{}", self.gpio4_mcu_oe().bit()), + ) + .field( + "gpio4_slp_sel", + &format_args!("{}", self.gpio4_slp_sel().bit()), + ) + .field( + "gpio4_mcu_wpd", + &format_args!("{}", self.gpio4_mcu_wpd().bit()), + ) + .field( + "gpio4_mcu_wpu", + &format_args!("{}", self.gpio4_mcu_wpu().bit()), + ) + .field( + "gpio4_mcu_ie", + &format_args!("{}", self.gpio4_mcu_ie().bit()), + ) + .field( + "gpio4_mcu_drv", + &format_args!("{}", self.gpio4_mcu_drv().bits()), + ) + .field( + "gpio4_fun_wpd", + &format_args!("{}", self.gpio4_fun_wpd().bit()), + ) + .field( + "gpio4_fun_wpu", + &format_args!("{}", self.gpio4_fun_wpu().bit()), + ) + .field( + "gpio4_fun_ie", + &format_args!("{}", self.gpio4_fun_ie().bit()), + ) + .field( + "gpio4_fun_drv", + &format_args!("{}", self.gpio4_fun_drv().bits()), + ) + .field( + "gpio4_mcu_sel", + &format_args!("{}", self.gpio4_mcu_sel().bits()), + ) + .field( + "gpio4_filter_en", + &format_args!("{}", self.gpio4_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio4_mcu_oe(&mut self) -> GPIO4_MCU_OE_W { + GPIO4_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio4_slp_sel(&mut self) -> GPIO4_SLP_SEL_W { + GPIO4_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio4_mcu_wpd(&mut self) -> GPIO4_MCU_WPD_W { + GPIO4_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio4_mcu_wpu(&mut self) -> GPIO4_MCU_WPU_W { + GPIO4_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio4_mcu_ie(&mut self) -> GPIO4_MCU_IE_W { + GPIO4_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio4_mcu_drv(&mut self) -> GPIO4_MCU_DRV_W { + GPIO4_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio4_fun_wpd(&mut self) -> GPIO4_FUN_WPD_W { + GPIO4_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio4_fun_wpu(&mut self) -> GPIO4_FUN_WPU_W { + GPIO4_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio4_fun_ie(&mut self) -> GPIO4_FUN_IE_W { + GPIO4_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio4_fun_drv(&mut self) -> GPIO4_FUN_DRV_W { + GPIO4_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio4_mcu_sel(&mut self) -> GPIO4_MCU_SEL_W { + GPIO4_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio4_filter_en(&mut self) -> GPIO4_FILTER_EN_W { + GPIO4_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO4_SPEC; +impl crate::RegisterSpec for GPIO4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio4::R`](R) reader structure"] +impl crate::Readable for GPIO4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio4::W`](W) writer structure"] +impl crate::Writable for GPIO4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio4 to value 0x0800"] +impl crate::Resettable for GPIO4_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio40.rs b/esp32p4/src/io_mux/gpio40.rs new file mode 100644 index 0000000000..f0e4fb11f9 --- /dev/null +++ b/esp32p4/src/io_mux/gpio40.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio40` reader"] +pub type R = crate::R; +#[doc = "Register `gpio40` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO40_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO40_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO40_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO40_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO40_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO40_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO40_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO40_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO40_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO40_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO40_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO40_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO40_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO40_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO40_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO40_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO40_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO40_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO40_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO40_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO40_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO40_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO40_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO40_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO40_FUN_WPD` reader - pull-down enable"] +pub type GPIO40_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO40_FUN_WPD` writer - pull-down enable"] +pub type GPIO40_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO40_FUN_WPU` reader - pull-up enable"] +pub type GPIO40_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO40_FUN_WPU` writer - pull-up enable"] +pub type GPIO40_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO40_FUN_IE` reader - input enable"] +pub type GPIO40_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO40_FUN_IE` writer - input enable"] +pub type GPIO40_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO40_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO40_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO40_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO40_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO40_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO40_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO40_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO40_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO40_FILTER_EN` reader - input filter enable"] +pub type GPIO40_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO40_FILTER_EN` writer - input filter enable"] +pub type GPIO40_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio40_mcu_oe(&self) -> GPIO40_MCU_OE_R { + GPIO40_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio40_slp_sel(&self) -> GPIO40_SLP_SEL_R { + GPIO40_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio40_mcu_wpd(&self) -> GPIO40_MCU_WPD_R { + GPIO40_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio40_mcu_wpu(&self) -> GPIO40_MCU_WPU_R { + GPIO40_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio40_mcu_ie(&self) -> GPIO40_MCU_IE_R { + GPIO40_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio40_mcu_drv(&self) -> GPIO40_MCU_DRV_R { + GPIO40_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio40_fun_wpd(&self) -> GPIO40_FUN_WPD_R { + GPIO40_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio40_fun_wpu(&self) -> GPIO40_FUN_WPU_R { + GPIO40_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio40_fun_ie(&self) -> GPIO40_FUN_IE_R { + GPIO40_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio40_fun_drv(&self) -> GPIO40_FUN_DRV_R { + GPIO40_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio40_mcu_sel(&self) -> GPIO40_MCU_SEL_R { + GPIO40_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio40_filter_en(&self) -> GPIO40_FILTER_EN_R { + GPIO40_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio40") + .field( + "gpio40_mcu_oe", + &format_args!("{}", self.gpio40_mcu_oe().bit()), + ) + .field( + "gpio40_slp_sel", + &format_args!("{}", self.gpio40_slp_sel().bit()), + ) + .field( + "gpio40_mcu_wpd", + &format_args!("{}", self.gpio40_mcu_wpd().bit()), + ) + .field( + "gpio40_mcu_wpu", + &format_args!("{}", self.gpio40_mcu_wpu().bit()), + ) + .field( + "gpio40_mcu_ie", + &format_args!("{}", self.gpio40_mcu_ie().bit()), + ) + .field( + "gpio40_mcu_drv", + &format_args!("{}", self.gpio40_mcu_drv().bits()), + ) + .field( + "gpio40_fun_wpd", + &format_args!("{}", self.gpio40_fun_wpd().bit()), + ) + .field( + "gpio40_fun_wpu", + &format_args!("{}", self.gpio40_fun_wpu().bit()), + ) + .field( + "gpio40_fun_ie", + &format_args!("{}", self.gpio40_fun_ie().bit()), + ) + .field( + "gpio40_fun_drv", + &format_args!("{}", self.gpio40_fun_drv().bits()), + ) + .field( + "gpio40_mcu_sel", + &format_args!("{}", self.gpio40_mcu_sel().bits()), + ) + .field( + "gpio40_filter_en", + &format_args!("{}", self.gpio40_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio40_mcu_oe(&mut self) -> GPIO40_MCU_OE_W { + GPIO40_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio40_slp_sel(&mut self) -> GPIO40_SLP_SEL_W { + GPIO40_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio40_mcu_wpd(&mut self) -> GPIO40_MCU_WPD_W { + GPIO40_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio40_mcu_wpu(&mut self) -> GPIO40_MCU_WPU_W { + GPIO40_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio40_mcu_ie(&mut self) -> GPIO40_MCU_IE_W { + GPIO40_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio40_mcu_drv(&mut self) -> GPIO40_MCU_DRV_W { + GPIO40_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio40_fun_wpd(&mut self) -> GPIO40_FUN_WPD_W { + GPIO40_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio40_fun_wpu(&mut self) -> GPIO40_FUN_WPU_W { + GPIO40_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio40_fun_ie(&mut self) -> GPIO40_FUN_IE_W { + GPIO40_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio40_fun_drv(&mut self) -> GPIO40_FUN_DRV_W { + GPIO40_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio40_mcu_sel(&mut self) -> GPIO40_MCU_SEL_W { + GPIO40_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio40_filter_en(&mut self) -> GPIO40_FILTER_EN_W { + GPIO40_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio40\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio40::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio40::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO40_SPEC; +impl crate::RegisterSpec for GPIO40_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio40::R`](R) reader structure"] +impl crate::Readable for GPIO40_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio40::W`](W) writer structure"] +impl crate::Writable for GPIO40_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio40 to value 0x0800"] +impl crate::Resettable for GPIO40_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio41.rs b/esp32p4/src/io_mux/gpio41.rs new file mode 100644 index 0000000000..d6fda54684 --- /dev/null +++ b/esp32p4/src/io_mux/gpio41.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio41` reader"] +pub type R = crate::R; +#[doc = "Register `gpio41` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO41_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO41_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO41_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO41_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO41_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO41_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO41_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO41_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO41_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO41_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO41_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO41_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO41_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO41_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO41_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO41_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO41_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO41_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO41_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO41_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO41_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO41_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO41_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO41_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO41_FUN_WPD` reader - pull-down enable"] +pub type GPIO41_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO41_FUN_WPD` writer - pull-down enable"] +pub type GPIO41_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO41_FUN_WPU` reader - pull-up enable"] +pub type GPIO41_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO41_FUN_WPU` writer - pull-up enable"] +pub type GPIO41_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO41_FUN_IE` reader - input enable"] +pub type GPIO41_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO41_FUN_IE` writer - input enable"] +pub type GPIO41_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO41_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO41_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO41_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO41_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO41_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO41_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO41_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO41_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO41_FILTER_EN` reader - input filter enable"] +pub type GPIO41_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO41_FILTER_EN` writer - input filter enable"] +pub type GPIO41_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio41_mcu_oe(&self) -> GPIO41_MCU_OE_R { + GPIO41_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio41_slp_sel(&self) -> GPIO41_SLP_SEL_R { + GPIO41_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio41_mcu_wpd(&self) -> GPIO41_MCU_WPD_R { + GPIO41_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio41_mcu_wpu(&self) -> GPIO41_MCU_WPU_R { + GPIO41_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio41_mcu_ie(&self) -> GPIO41_MCU_IE_R { + GPIO41_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio41_mcu_drv(&self) -> GPIO41_MCU_DRV_R { + GPIO41_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio41_fun_wpd(&self) -> GPIO41_FUN_WPD_R { + GPIO41_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio41_fun_wpu(&self) -> GPIO41_FUN_WPU_R { + GPIO41_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio41_fun_ie(&self) -> GPIO41_FUN_IE_R { + GPIO41_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio41_fun_drv(&self) -> GPIO41_FUN_DRV_R { + GPIO41_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio41_mcu_sel(&self) -> GPIO41_MCU_SEL_R { + GPIO41_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio41_filter_en(&self) -> GPIO41_FILTER_EN_R { + GPIO41_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio41") + .field( + "gpio41_mcu_oe", + &format_args!("{}", self.gpio41_mcu_oe().bit()), + ) + .field( + "gpio41_slp_sel", + &format_args!("{}", self.gpio41_slp_sel().bit()), + ) + .field( + "gpio41_mcu_wpd", + &format_args!("{}", self.gpio41_mcu_wpd().bit()), + ) + .field( + "gpio41_mcu_wpu", + &format_args!("{}", self.gpio41_mcu_wpu().bit()), + ) + .field( + "gpio41_mcu_ie", + &format_args!("{}", self.gpio41_mcu_ie().bit()), + ) + .field( + "gpio41_mcu_drv", + &format_args!("{}", self.gpio41_mcu_drv().bits()), + ) + .field( + "gpio41_fun_wpd", + &format_args!("{}", self.gpio41_fun_wpd().bit()), + ) + .field( + "gpio41_fun_wpu", + &format_args!("{}", self.gpio41_fun_wpu().bit()), + ) + .field( + "gpio41_fun_ie", + &format_args!("{}", self.gpio41_fun_ie().bit()), + ) + .field( + "gpio41_fun_drv", + &format_args!("{}", self.gpio41_fun_drv().bits()), + ) + .field( + "gpio41_mcu_sel", + &format_args!("{}", self.gpio41_mcu_sel().bits()), + ) + .field( + "gpio41_filter_en", + &format_args!("{}", self.gpio41_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio41_mcu_oe(&mut self) -> GPIO41_MCU_OE_W { + GPIO41_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio41_slp_sel(&mut self) -> GPIO41_SLP_SEL_W { + GPIO41_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio41_mcu_wpd(&mut self) -> GPIO41_MCU_WPD_W { + GPIO41_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio41_mcu_wpu(&mut self) -> GPIO41_MCU_WPU_W { + GPIO41_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio41_mcu_ie(&mut self) -> GPIO41_MCU_IE_W { + GPIO41_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio41_mcu_drv(&mut self) -> GPIO41_MCU_DRV_W { + GPIO41_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio41_fun_wpd(&mut self) -> GPIO41_FUN_WPD_W { + GPIO41_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio41_fun_wpu(&mut self) -> GPIO41_FUN_WPU_W { + GPIO41_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio41_fun_ie(&mut self) -> GPIO41_FUN_IE_W { + GPIO41_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio41_fun_drv(&mut self) -> GPIO41_FUN_DRV_W { + GPIO41_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio41_mcu_sel(&mut self) -> GPIO41_MCU_SEL_W { + GPIO41_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio41_filter_en(&mut self) -> GPIO41_FILTER_EN_W { + GPIO41_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio41\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio41::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio41::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO41_SPEC; +impl crate::RegisterSpec for GPIO41_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio41::R`](R) reader structure"] +impl crate::Readable for GPIO41_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio41::W`](W) writer structure"] +impl crate::Writable for GPIO41_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio41 to value 0x0800"] +impl crate::Resettable for GPIO41_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio42.rs b/esp32p4/src/io_mux/gpio42.rs new file mode 100644 index 0000000000..1a5d1d7a52 --- /dev/null +++ b/esp32p4/src/io_mux/gpio42.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio42` reader"] +pub type R = crate::R; +#[doc = "Register `gpio42` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO42_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO42_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO42_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO42_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO42_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO42_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO42_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO42_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO42_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO42_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO42_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO42_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO42_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO42_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO42_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO42_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO42_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO42_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO42_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO42_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO42_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO42_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO42_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO42_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO42_FUN_WPD` reader - pull-down enable"] +pub type GPIO42_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO42_FUN_WPD` writer - pull-down enable"] +pub type GPIO42_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO42_FUN_WPU` reader - pull-up enable"] +pub type GPIO42_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO42_FUN_WPU` writer - pull-up enable"] +pub type GPIO42_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO42_FUN_IE` reader - input enable"] +pub type GPIO42_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO42_FUN_IE` writer - input enable"] +pub type GPIO42_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO42_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO42_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO42_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO42_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO42_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO42_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO42_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO42_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO42_FILTER_EN` reader - input filter enable"] +pub type GPIO42_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO42_FILTER_EN` writer - input filter enable"] +pub type GPIO42_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio42_mcu_oe(&self) -> GPIO42_MCU_OE_R { + GPIO42_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio42_slp_sel(&self) -> GPIO42_SLP_SEL_R { + GPIO42_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio42_mcu_wpd(&self) -> GPIO42_MCU_WPD_R { + GPIO42_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio42_mcu_wpu(&self) -> GPIO42_MCU_WPU_R { + GPIO42_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio42_mcu_ie(&self) -> GPIO42_MCU_IE_R { + GPIO42_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio42_mcu_drv(&self) -> GPIO42_MCU_DRV_R { + GPIO42_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio42_fun_wpd(&self) -> GPIO42_FUN_WPD_R { + GPIO42_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio42_fun_wpu(&self) -> GPIO42_FUN_WPU_R { + GPIO42_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio42_fun_ie(&self) -> GPIO42_FUN_IE_R { + GPIO42_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio42_fun_drv(&self) -> GPIO42_FUN_DRV_R { + GPIO42_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio42_mcu_sel(&self) -> GPIO42_MCU_SEL_R { + GPIO42_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio42_filter_en(&self) -> GPIO42_FILTER_EN_R { + GPIO42_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio42") + .field( + "gpio42_mcu_oe", + &format_args!("{}", self.gpio42_mcu_oe().bit()), + ) + .field( + "gpio42_slp_sel", + &format_args!("{}", self.gpio42_slp_sel().bit()), + ) + .field( + "gpio42_mcu_wpd", + &format_args!("{}", self.gpio42_mcu_wpd().bit()), + ) + .field( + "gpio42_mcu_wpu", + &format_args!("{}", self.gpio42_mcu_wpu().bit()), + ) + .field( + "gpio42_mcu_ie", + &format_args!("{}", self.gpio42_mcu_ie().bit()), + ) + .field( + "gpio42_mcu_drv", + &format_args!("{}", self.gpio42_mcu_drv().bits()), + ) + .field( + "gpio42_fun_wpd", + &format_args!("{}", self.gpio42_fun_wpd().bit()), + ) + .field( + "gpio42_fun_wpu", + &format_args!("{}", self.gpio42_fun_wpu().bit()), + ) + .field( + "gpio42_fun_ie", + &format_args!("{}", self.gpio42_fun_ie().bit()), + ) + .field( + "gpio42_fun_drv", + &format_args!("{}", self.gpio42_fun_drv().bits()), + ) + .field( + "gpio42_mcu_sel", + &format_args!("{}", self.gpio42_mcu_sel().bits()), + ) + .field( + "gpio42_filter_en", + &format_args!("{}", self.gpio42_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio42_mcu_oe(&mut self) -> GPIO42_MCU_OE_W { + GPIO42_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio42_slp_sel(&mut self) -> GPIO42_SLP_SEL_W { + GPIO42_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio42_mcu_wpd(&mut self) -> GPIO42_MCU_WPD_W { + GPIO42_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio42_mcu_wpu(&mut self) -> GPIO42_MCU_WPU_W { + GPIO42_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio42_mcu_ie(&mut self) -> GPIO42_MCU_IE_W { + GPIO42_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio42_mcu_drv(&mut self) -> GPIO42_MCU_DRV_W { + GPIO42_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio42_fun_wpd(&mut self) -> GPIO42_FUN_WPD_W { + GPIO42_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio42_fun_wpu(&mut self) -> GPIO42_FUN_WPU_W { + GPIO42_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio42_fun_ie(&mut self) -> GPIO42_FUN_IE_W { + GPIO42_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio42_fun_drv(&mut self) -> GPIO42_FUN_DRV_W { + GPIO42_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio42_mcu_sel(&mut self) -> GPIO42_MCU_SEL_W { + GPIO42_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio42_filter_en(&mut self) -> GPIO42_FILTER_EN_W { + GPIO42_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio42\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio42::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio42::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO42_SPEC; +impl crate::RegisterSpec for GPIO42_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio42::R`](R) reader structure"] +impl crate::Readable for GPIO42_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio42::W`](W) writer structure"] +impl crate::Writable for GPIO42_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio42 to value 0x0800"] +impl crate::Resettable for GPIO42_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio43.rs b/esp32p4/src/io_mux/gpio43.rs new file mode 100644 index 0000000000..1ea2bad2ec --- /dev/null +++ b/esp32p4/src/io_mux/gpio43.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio43` reader"] +pub type R = crate::R; +#[doc = "Register `gpio43` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO43_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO43_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO43_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO43_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO43_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO43_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO43_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO43_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO43_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO43_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO43_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO43_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO43_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO43_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO43_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO43_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO43_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO43_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO43_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO43_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO43_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO43_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO43_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO43_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO43_FUN_WPD` reader - pull-down enable"] +pub type GPIO43_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO43_FUN_WPD` writer - pull-down enable"] +pub type GPIO43_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO43_FUN_WPU` reader - pull-up enable"] +pub type GPIO43_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO43_FUN_WPU` writer - pull-up enable"] +pub type GPIO43_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO43_FUN_IE` reader - input enable"] +pub type GPIO43_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO43_FUN_IE` writer - input enable"] +pub type GPIO43_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO43_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO43_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO43_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO43_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO43_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO43_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO43_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO43_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO43_FILTER_EN` reader - input filter enable"] +pub type GPIO43_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO43_FILTER_EN` writer - input filter enable"] +pub type GPIO43_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio43_mcu_oe(&self) -> GPIO43_MCU_OE_R { + GPIO43_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio43_slp_sel(&self) -> GPIO43_SLP_SEL_R { + GPIO43_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio43_mcu_wpd(&self) -> GPIO43_MCU_WPD_R { + GPIO43_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio43_mcu_wpu(&self) -> GPIO43_MCU_WPU_R { + GPIO43_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio43_mcu_ie(&self) -> GPIO43_MCU_IE_R { + GPIO43_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio43_mcu_drv(&self) -> GPIO43_MCU_DRV_R { + GPIO43_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio43_fun_wpd(&self) -> GPIO43_FUN_WPD_R { + GPIO43_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio43_fun_wpu(&self) -> GPIO43_FUN_WPU_R { + GPIO43_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio43_fun_ie(&self) -> GPIO43_FUN_IE_R { + GPIO43_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio43_fun_drv(&self) -> GPIO43_FUN_DRV_R { + GPIO43_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio43_mcu_sel(&self) -> GPIO43_MCU_SEL_R { + GPIO43_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio43_filter_en(&self) -> GPIO43_FILTER_EN_R { + GPIO43_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio43") + .field( + "gpio43_mcu_oe", + &format_args!("{}", self.gpio43_mcu_oe().bit()), + ) + .field( + "gpio43_slp_sel", + &format_args!("{}", self.gpio43_slp_sel().bit()), + ) + .field( + "gpio43_mcu_wpd", + &format_args!("{}", self.gpio43_mcu_wpd().bit()), + ) + .field( + "gpio43_mcu_wpu", + &format_args!("{}", self.gpio43_mcu_wpu().bit()), + ) + .field( + "gpio43_mcu_ie", + &format_args!("{}", self.gpio43_mcu_ie().bit()), + ) + .field( + "gpio43_mcu_drv", + &format_args!("{}", self.gpio43_mcu_drv().bits()), + ) + .field( + "gpio43_fun_wpd", + &format_args!("{}", self.gpio43_fun_wpd().bit()), + ) + .field( + "gpio43_fun_wpu", + &format_args!("{}", self.gpio43_fun_wpu().bit()), + ) + .field( + "gpio43_fun_ie", + &format_args!("{}", self.gpio43_fun_ie().bit()), + ) + .field( + "gpio43_fun_drv", + &format_args!("{}", self.gpio43_fun_drv().bits()), + ) + .field( + "gpio43_mcu_sel", + &format_args!("{}", self.gpio43_mcu_sel().bits()), + ) + .field( + "gpio43_filter_en", + &format_args!("{}", self.gpio43_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio43_mcu_oe(&mut self) -> GPIO43_MCU_OE_W { + GPIO43_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio43_slp_sel(&mut self) -> GPIO43_SLP_SEL_W { + GPIO43_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio43_mcu_wpd(&mut self) -> GPIO43_MCU_WPD_W { + GPIO43_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio43_mcu_wpu(&mut self) -> GPIO43_MCU_WPU_W { + GPIO43_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio43_mcu_ie(&mut self) -> GPIO43_MCU_IE_W { + GPIO43_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio43_mcu_drv(&mut self) -> GPIO43_MCU_DRV_W { + GPIO43_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio43_fun_wpd(&mut self) -> GPIO43_FUN_WPD_W { + GPIO43_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio43_fun_wpu(&mut self) -> GPIO43_FUN_WPU_W { + GPIO43_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio43_fun_ie(&mut self) -> GPIO43_FUN_IE_W { + GPIO43_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio43_fun_drv(&mut self) -> GPIO43_FUN_DRV_W { + GPIO43_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio43_mcu_sel(&mut self) -> GPIO43_MCU_SEL_W { + GPIO43_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio43_filter_en(&mut self) -> GPIO43_FILTER_EN_W { + GPIO43_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio43\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio43::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio43::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO43_SPEC; +impl crate::RegisterSpec for GPIO43_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio43::R`](R) reader structure"] +impl crate::Readable for GPIO43_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio43::W`](W) writer structure"] +impl crate::Writable for GPIO43_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio43 to value 0x0800"] +impl crate::Resettable for GPIO43_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio44.rs b/esp32p4/src/io_mux/gpio44.rs new file mode 100644 index 0000000000..2d09ddeef6 --- /dev/null +++ b/esp32p4/src/io_mux/gpio44.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio44` reader"] +pub type R = crate::R; +#[doc = "Register `gpio44` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO44_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO44_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO44_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO44_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO44_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO44_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO44_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO44_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO44_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO44_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO44_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO44_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO44_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO44_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO44_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO44_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO44_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO44_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO44_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO44_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO44_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO44_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO44_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO44_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO44_FUN_WPD` reader - pull-down enable"] +pub type GPIO44_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO44_FUN_WPD` writer - pull-down enable"] +pub type GPIO44_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO44_FUN_WPU` reader - pull-up enable"] +pub type GPIO44_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO44_FUN_WPU` writer - pull-up enable"] +pub type GPIO44_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO44_FUN_IE` reader - input enable"] +pub type GPIO44_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO44_FUN_IE` writer - input enable"] +pub type GPIO44_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO44_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO44_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO44_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO44_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO44_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO44_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO44_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO44_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO44_FILTER_EN` reader - input filter enable"] +pub type GPIO44_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO44_FILTER_EN` writer - input filter enable"] +pub type GPIO44_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio44_mcu_oe(&self) -> GPIO44_MCU_OE_R { + GPIO44_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio44_slp_sel(&self) -> GPIO44_SLP_SEL_R { + GPIO44_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio44_mcu_wpd(&self) -> GPIO44_MCU_WPD_R { + GPIO44_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio44_mcu_wpu(&self) -> GPIO44_MCU_WPU_R { + GPIO44_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio44_mcu_ie(&self) -> GPIO44_MCU_IE_R { + GPIO44_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio44_mcu_drv(&self) -> GPIO44_MCU_DRV_R { + GPIO44_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio44_fun_wpd(&self) -> GPIO44_FUN_WPD_R { + GPIO44_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio44_fun_wpu(&self) -> GPIO44_FUN_WPU_R { + GPIO44_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio44_fun_ie(&self) -> GPIO44_FUN_IE_R { + GPIO44_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio44_fun_drv(&self) -> GPIO44_FUN_DRV_R { + GPIO44_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio44_mcu_sel(&self) -> GPIO44_MCU_SEL_R { + GPIO44_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio44_filter_en(&self) -> GPIO44_FILTER_EN_R { + GPIO44_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio44") + .field( + "gpio44_mcu_oe", + &format_args!("{}", self.gpio44_mcu_oe().bit()), + ) + .field( + "gpio44_slp_sel", + &format_args!("{}", self.gpio44_slp_sel().bit()), + ) + .field( + "gpio44_mcu_wpd", + &format_args!("{}", self.gpio44_mcu_wpd().bit()), + ) + .field( + "gpio44_mcu_wpu", + &format_args!("{}", self.gpio44_mcu_wpu().bit()), + ) + .field( + "gpio44_mcu_ie", + &format_args!("{}", self.gpio44_mcu_ie().bit()), + ) + .field( + "gpio44_mcu_drv", + &format_args!("{}", self.gpio44_mcu_drv().bits()), + ) + .field( + "gpio44_fun_wpd", + &format_args!("{}", self.gpio44_fun_wpd().bit()), + ) + .field( + "gpio44_fun_wpu", + &format_args!("{}", self.gpio44_fun_wpu().bit()), + ) + .field( + "gpio44_fun_ie", + &format_args!("{}", self.gpio44_fun_ie().bit()), + ) + .field( + "gpio44_fun_drv", + &format_args!("{}", self.gpio44_fun_drv().bits()), + ) + .field( + "gpio44_mcu_sel", + &format_args!("{}", self.gpio44_mcu_sel().bits()), + ) + .field( + "gpio44_filter_en", + &format_args!("{}", self.gpio44_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio44_mcu_oe(&mut self) -> GPIO44_MCU_OE_W { + GPIO44_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio44_slp_sel(&mut self) -> GPIO44_SLP_SEL_W { + GPIO44_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio44_mcu_wpd(&mut self) -> GPIO44_MCU_WPD_W { + GPIO44_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio44_mcu_wpu(&mut self) -> GPIO44_MCU_WPU_W { + GPIO44_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio44_mcu_ie(&mut self) -> GPIO44_MCU_IE_W { + GPIO44_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio44_mcu_drv(&mut self) -> GPIO44_MCU_DRV_W { + GPIO44_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio44_fun_wpd(&mut self) -> GPIO44_FUN_WPD_W { + GPIO44_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio44_fun_wpu(&mut self) -> GPIO44_FUN_WPU_W { + GPIO44_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio44_fun_ie(&mut self) -> GPIO44_FUN_IE_W { + GPIO44_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio44_fun_drv(&mut self) -> GPIO44_FUN_DRV_W { + GPIO44_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio44_mcu_sel(&mut self) -> GPIO44_MCU_SEL_W { + GPIO44_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio44_filter_en(&mut self) -> GPIO44_FILTER_EN_W { + GPIO44_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio44\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio44::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio44::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO44_SPEC; +impl crate::RegisterSpec for GPIO44_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio44::R`](R) reader structure"] +impl crate::Readable for GPIO44_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio44::W`](W) writer structure"] +impl crate::Writable for GPIO44_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio44 to value 0x0800"] +impl crate::Resettable for GPIO44_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio45.rs b/esp32p4/src/io_mux/gpio45.rs new file mode 100644 index 0000000000..12db222485 --- /dev/null +++ b/esp32p4/src/io_mux/gpio45.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio45` reader"] +pub type R = crate::R; +#[doc = "Register `gpio45` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO45_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO45_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO45_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO45_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO45_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO45_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO45_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO45_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO45_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO45_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO45_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO45_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO45_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO45_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO45_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO45_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO45_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO45_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO45_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO45_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO45_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO45_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO45_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO45_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO45_FUN_WPD` reader - pull-down enable"] +pub type GPIO45_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO45_FUN_WPD` writer - pull-down enable"] +pub type GPIO45_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO45_FUN_WPU` reader - pull-up enable"] +pub type GPIO45_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO45_FUN_WPU` writer - pull-up enable"] +pub type GPIO45_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO45_FUN_IE` reader - input enable"] +pub type GPIO45_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO45_FUN_IE` writer - input enable"] +pub type GPIO45_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO45_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO45_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO45_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO45_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO45_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO45_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO45_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO45_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO45_FILTER_EN` reader - input filter enable"] +pub type GPIO45_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO45_FILTER_EN` writer - input filter enable"] +pub type GPIO45_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio45_mcu_oe(&self) -> GPIO45_MCU_OE_R { + GPIO45_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio45_slp_sel(&self) -> GPIO45_SLP_SEL_R { + GPIO45_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio45_mcu_wpd(&self) -> GPIO45_MCU_WPD_R { + GPIO45_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio45_mcu_wpu(&self) -> GPIO45_MCU_WPU_R { + GPIO45_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio45_mcu_ie(&self) -> GPIO45_MCU_IE_R { + GPIO45_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio45_mcu_drv(&self) -> GPIO45_MCU_DRV_R { + GPIO45_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio45_fun_wpd(&self) -> GPIO45_FUN_WPD_R { + GPIO45_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio45_fun_wpu(&self) -> GPIO45_FUN_WPU_R { + GPIO45_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio45_fun_ie(&self) -> GPIO45_FUN_IE_R { + GPIO45_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio45_fun_drv(&self) -> GPIO45_FUN_DRV_R { + GPIO45_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio45_mcu_sel(&self) -> GPIO45_MCU_SEL_R { + GPIO45_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio45_filter_en(&self) -> GPIO45_FILTER_EN_R { + GPIO45_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio45") + .field( + "gpio45_mcu_oe", + &format_args!("{}", self.gpio45_mcu_oe().bit()), + ) + .field( + "gpio45_slp_sel", + &format_args!("{}", self.gpio45_slp_sel().bit()), + ) + .field( + "gpio45_mcu_wpd", + &format_args!("{}", self.gpio45_mcu_wpd().bit()), + ) + .field( + "gpio45_mcu_wpu", + &format_args!("{}", self.gpio45_mcu_wpu().bit()), + ) + .field( + "gpio45_mcu_ie", + &format_args!("{}", self.gpio45_mcu_ie().bit()), + ) + .field( + "gpio45_mcu_drv", + &format_args!("{}", self.gpio45_mcu_drv().bits()), + ) + .field( + "gpio45_fun_wpd", + &format_args!("{}", self.gpio45_fun_wpd().bit()), + ) + .field( + "gpio45_fun_wpu", + &format_args!("{}", self.gpio45_fun_wpu().bit()), + ) + .field( + "gpio45_fun_ie", + &format_args!("{}", self.gpio45_fun_ie().bit()), + ) + .field( + "gpio45_fun_drv", + &format_args!("{}", self.gpio45_fun_drv().bits()), + ) + .field( + "gpio45_mcu_sel", + &format_args!("{}", self.gpio45_mcu_sel().bits()), + ) + .field( + "gpio45_filter_en", + &format_args!("{}", self.gpio45_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio45_mcu_oe(&mut self) -> GPIO45_MCU_OE_W { + GPIO45_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio45_slp_sel(&mut self) -> GPIO45_SLP_SEL_W { + GPIO45_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio45_mcu_wpd(&mut self) -> GPIO45_MCU_WPD_W { + GPIO45_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio45_mcu_wpu(&mut self) -> GPIO45_MCU_WPU_W { + GPIO45_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio45_mcu_ie(&mut self) -> GPIO45_MCU_IE_W { + GPIO45_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio45_mcu_drv(&mut self) -> GPIO45_MCU_DRV_W { + GPIO45_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio45_fun_wpd(&mut self) -> GPIO45_FUN_WPD_W { + GPIO45_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio45_fun_wpu(&mut self) -> GPIO45_FUN_WPU_W { + GPIO45_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio45_fun_ie(&mut self) -> GPIO45_FUN_IE_W { + GPIO45_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio45_fun_drv(&mut self) -> GPIO45_FUN_DRV_W { + GPIO45_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio45_mcu_sel(&mut self) -> GPIO45_MCU_SEL_W { + GPIO45_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio45_filter_en(&mut self) -> GPIO45_FILTER_EN_W { + GPIO45_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio45\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio45::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio45::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO45_SPEC; +impl crate::RegisterSpec for GPIO45_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio45::R`](R) reader structure"] +impl crate::Readable for GPIO45_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio45::W`](W) writer structure"] +impl crate::Writable for GPIO45_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio45 to value 0x0800"] +impl crate::Resettable for GPIO45_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio46.rs b/esp32p4/src/io_mux/gpio46.rs new file mode 100644 index 0000000000..0b62d69b82 --- /dev/null +++ b/esp32p4/src/io_mux/gpio46.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio46` reader"] +pub type R = crate::R; +#[doc = "Register `gpio46` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO46_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO46_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO46_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO46_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO46_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO46_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO46_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO46_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO46_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO46_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO46_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO46_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO46_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO46_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO46_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO46_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO46_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO46_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO46_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO46_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO46_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO46_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO46_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO46_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO46_FUN_WPD` reader - pull-down enable"] +pub type GPIO46_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO46_FUN_WPD` writer - pull-down enable"] +pub type GPIO46_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO46_FUN_WPU` reader - pull-up enable"] +pub type GPIO46_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO46_FUN_WPU` writer - pull-up enable"] +pub type GPIO46_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO46_FUN_IE` reader - input enable"] +pub type GPIO46_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO46_FUN_IE` writer - input enable"] +pub type GPIO46_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO46_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO46_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO46_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO46_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO46_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO46_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO46_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO46_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO46_FILTER_EN` reader - input filter enable"] +pub type GPIO46_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO46_FILTER_EN` writer - input filter enable"] +pub type GPIO46_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio46_mcu_oe(&self) -> GPIO46_MCU_OE_R { + GPIO46_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio46_slp_sel(&self) -> GPIO46_SLP_SEL_R { + GPIO46_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio46_mcu_wpd(&self) -> GPIO46_MCU_WPD_R { + GPIO46_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio46_mcu_wpu(&self) -> GPIO46_MCU_WPU_R { + GPIO46_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio46_mcu_ie(&self) -> GPIO46_MCU_IE_R { + GPIO46_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio46_mcu_drv(&self) -> GPIO46_MCU_DRV_R { + GPIO46_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio46_fun_wpd(&self) -> GPIO46_FUN_WPD_R { + GPIO46_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio46_fun_wpu(&self) -> GPIO46_FUN_WPU_R { + GPIO46_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio46_fun_ie(&self) -> GPIO46_FUN_IE_R { + GPIO46_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio46_fun_drv(&self) -> GPIO46_FUN_DRV_R { + GPIO46_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio46_mcu_sel(&self) -> GPIO46_MCU_SEL_R { + GPIO46_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio46_filter_en(&self) -> GPIO46_FILTER_EN_R { + GPIO46_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio46") + .field( + "gpio46_mcu_oe", + &format_args!("{}", self.gpio46_mcu_oe().bit()), + ) + .field( + "gpio46_slp_sel", + &format_args!("{}", self.gpio46_slp_sel().bit()), + ) + .field( + "gpio46_mcu_wpd", + &format_args!("{}", self.gpio46_mcu_wpd().bit()), + ) + .field( + "gpio46_mcu_wpu", + &format_args!("{}", self.gpio46_mcu_wpu().bit()), + ) + .field( + "gpio46_mcu_ie", + &format_args!("{}", self.gpio46_mcu_ie().bit()), + ) + .field( + "gpio46_mcu_drv", + &format_args!("{}", self.gpio46_mcu_drv().bits()), + ) + .field( + "gpio46_fun_wpd", + &format_args!("{}", self.gpio46_fun_wpd().bit()), + ) + .field( + "gpio46_fun_wpu", + &format_args!("{}", self.gpio46_fun_wpu().bit()), + ) + .field( + "gpio46_fun_ie", + &format_args!("{}", self.gpio46_fun_ie().bit()), + ) + .field( + "gpio46_fun_drv", + &format_args!("{}", self.gpio46_fun_drv().bits()), + ) + .field( + "gpio46_mcu_sel", + &format_args!("{}", self.gpio46_mcu_sel().bits()), + ) + .field( + "gpio46_filter_en", + &format_args!("{}", self.gpio46_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio46_mcu_oe(&mut self) -> GPIO46_MCU_OE_W { + GPIO46_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio46_slp_sel(&mut self) -> GPIO46_SLP_SEL_W { + GPIO46_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio46_mcu_wpd(&mut self) -> GPIO46_MCU_WPD_W { + GPIO46_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio46_mcu_wpu(&mut self) -> GPIO46_MCU_WPU_W { + GPIO46_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio46_mcu_ie(&mut self) -> GPIO46_MCU_IE_W { + GPIO46_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio46_mcu_drv(&mut self) -> GPIO46_MCU_DRV_W { + GPIO46_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio46_fun_wpd(&mut self) -> GPIO46_FUN_WPD_W { + GPIO46_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio46_fun_wpu(&mut self) -> GPIO46_FUN_WPU_W { + GPIO46_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio46_fun_ie(&mut self) -> GPIO46_FUN_IE_W { + GPIO46_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio46_fun_drv(&mut self) -> GPIO46_FUN_DRV_W { + GPIO46_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio46_mcu_sel(&mut self) -> GPIO46_MCU_SEL_W { + GPIO46_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio46_filter_en(&mut self) -> GPIO46_FILTER_EN_W { + GPIO46_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio46\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio46::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio46::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO46_SPEC; +impl crate::RegisterSpec for GPIO46_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio46::R`](R) reader structure"] +impl crate::Readable for GPIO46_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio46::W`](W) writer structure"] +impl crate::Writable for GPIO46_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio46 to value 0x0800"] +impl crate::Resettable for GPIO46_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio47.rs b/esp32p4/src/io_mux/gpio47.rs new file mode 100644 index 0000000000..72876191cf --- /dev/null +++ b/esp32p4/src/io_mux/gpio47.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio47` reader"] +pub type R = crate::R; +#[doc = "Register `gpio47` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO47_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO47_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO47_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO47_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO47_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO47_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO47_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO47_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO47_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO47_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO47_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO47_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO47_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO47_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO47_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO47_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO47_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO47_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO47_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO47_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO47_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO47_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO47_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO47_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO47_FUN_WPD` reader - pull-down enable"] +pub type GPIO47_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO47_FUN_WPD` writer - pull-down enable"] +pub type GPIO47_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO47_FUN_WPU` reader - pull-up enable"] +pub type GPIO47_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO47_FUN_WPU` writer - pull-up enable"] +pub type GPIO47_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO47_FUN_IE` reader - input enable"] +pub type GPIO47_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO47_FUN_IE` writer - input enable"] +pub type GPIO47_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO47_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO47_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO47_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO47_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO47_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO47_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO47_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO47_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO47_FILTER_EN` reader - input filter enable"] +pub type GPIO47_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO47_FILTER_EN` writer - input filter enable"] +pub type GPIO47_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio47_mcu_oe(&self) -> GPIO47_MCU_OE_R { + GPIO47_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio47_slp_sel(&self) -> GPIO47_SLP_SEL_R { + GPIO47_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio47_mcu_wpd(&self) -> GPIO47_MCU_WPD_R { + GPIO47_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio47_mcu_wpu(&self) -> GPIO47_MCU_WPU_R { + GPIO47_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio47_mcu_ie(&self) -> GPIO47_MCU_IE_R { + GPIO47_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio47_mcu_drv(&self) -> GPIO47_MCU_DRV_R { + GPIO47_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio47_fun_wpd(&self) -> GPIO47_FUN_WPD_R { + GPIO47_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio47_fun_wpu(&self) -> GPIO47_FUN_WPU_R { + GPIO47_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio47_fun_ie(&self) -> GPIO47_FUN_IE_R { + GPIO47_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio47_fun_drv(&self) -> GPIO47_FUN_DRV_R { + GPIO47_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio47_mcu_sel(&self) -> GPIO47_MCU_SEL_R { + GPIO47_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio47_filter_en(&self) -> GPIO47_FILTER_EN_R { + GPIO47_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio47") + .field( + "gpio47_mcu_oe", + &format_args!("{}", self.gpio47_mcu_oe().bit()), + ) + .field( + "gpio47_slp_sel", + &format_args!("{}", self.gpio47_slp_sel().bit()), + ) + .field( + "gpio47_mcu_wpd", + &format_args!("{}", self.gpio47_mcu_wpd().bit()), + ) + .field( + "gpio47_mcu_wpu", + &format_args!("{}", self.gpio47_mcu_wpu().bit()), + ) + .field( + "gpio47_mcu_ie", + &format_args!("{}", self.gpio47_mcu_ie().bit()), + ) + .field( + "gpio47_mcu_drv", + &format_args!("{}", self.gpio47_mcu_drv().bits()), + ) + .field( + "gpio47_fun_wpd", + &format_args!("{}", self.gpio47_fun_wpd().bit()), + ) + .field( + "gpio47_fun_wpu", + &format_args!("{}", self.gpio47_fun_wpu().bit()), + ) + .field( + "gpio47_fun_ie", + &format_args!("{}", self.gpio47_fun_ie().bit()), + ) + .field( + "gpio47_fun_drv", + &format_args!("{}", self.gpio47_fun_drv().bits()), + ) + .field( + "gpio47_mcu_sel", + &format_args!("{}", self.gpio47_mcu_sel().bits()), + ) + .field( + "gpio47_filter_en", + &format_args!("{}", self.gpio47_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio47_mcu_oe(&mut self) -> GPIO47_MCU_OE_W { + GPIO47_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio47_slp_sel(&mut self) -> GPIO47_SLP_SEL_W { + GPIO47_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio47_mcu_wpd(&mut self) -> GPIO47_MCU_WPD_W { + GPIO47_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio47_mcu_wpu(&mut self) -> GPIO47_MCU_WPU_W { + GPIO47_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio47_mcu_ie(&mut self) -> GPIO47_MCU_IE_W { + GPIO47_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio47_mcu_drv(&mut self) -> GPIO47_MCU_DRV_W { + GPIO47_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio47_fun_wpd(&mut self) -> GPIO47_FUN_WPD_W { + GPIO47_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio47_fun_wpu(&mut self) -> GPIO47_FUN_WPU_W { + GPIO47_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio47_fun_ie(&mut self) -> GPIO47_FUN_IE_W { + GPIO47_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio47_fun_drv(&mut self) -> GPIO47_FUN_DRV_W { + GPIO47_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio47_mcu_sel(&mut self) -> GPIO47_MCU_SEL_W { + GPIO47_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio47_filter_en(&mut self) -> GPIO47_FILTER_EN_W { + GPIO47_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio47\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio47::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio47::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO47_SPEC; +impl crate::RegisterSpec for GPIO47_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio47::R`](R) reader structure"] +impl crate::Readable for GPIO47_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio47::W`](W) writer structure"] +impl crate::Writable for GPIO47_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio47 to value 0x0800"] +impl crate::Resettable for GPIO47_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio48.rs b/esp32p4/src/io_mux/gpio48.rs new file mode 100644 index 0000000000..b18f791410 --- /dev/null +++ b/esp32p4/src/io_mux/gpio48.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio48` reader"] +pub type R = crate::R; +#[doc = "Register `gpio48` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO48_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO48_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO48_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO48_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO48_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO48_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO48_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO48_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO48_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO48_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO48_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO48_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO48_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO48_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO48_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO48_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO48_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO48_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO48_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO48_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO48_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO48_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO48_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO48_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO48_FUN_WPD` reader - pull-down enable"] +pub type GPIO48_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO48_FUN_WPD` writer - pull-down enable"] +pub type GPIO48_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO48_FUN_WPU` reader - pull-up enable"] +pub type GPIO48_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO48_FUN_WPU` writer - pull-up enable"] +pub type GPIO48_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO48_FUN_IE` reader - input enable"] +pub type GPIO48_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO48_FUN_IE` writer - input enable"] +pub type GPIO48_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO48_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO48_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO48_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO48_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO48_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO48_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO48_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO48_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO48_FILTER_EN` reader - input filter enable"] +pub type GPIO48_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO48_FILTER_EN` writer - input filter enable"] +pub type GPIO48_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio48_mcu_oe(&self) -> GPIO48_MCU_OE_R { + GPIO48_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio48_slp_sel(&self) -> GPIO48_SLP_SEL_R { + GPIO48_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio48_mcu_wpd(&self) -> GPIO48_MCU_WPD_R { + GPIO48_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio48_mcu_wpu(&self) -> GPIO48_MCU_WPU_R { + GPIO48_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio48_mcu_ie(&self) -> GPIO48_MCU_IE_R { + GPIO48_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio48_mcu_drv(&self) -> GPIO48_MCU_DRV_R { + GPIO48_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio48_fun_wpd(&self) -> GPIO48_FUN_WPD_R { + GPIO48_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio48_fun_wpu(&self) -> GPIO48_FUN_WPU_R { + GPIO48_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio48_fun_ie(&self) -> GPIO48_FUN_IE_R { + GPIO48_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio48_fun_drv(&self) -> GPIO48_FUN_DRV_R { + GPIO48_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio48_mcu_sel(&self) -> GPIO48_MCU_SEL_R { + GPIO48_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio48_filter_en(&self) -> GPIO48_FILTER_EN_R { + GPIO48_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio48") + .field( + "gpio48_mcu_oe", + &format_args!("{}", self.gpio48_mcu_oe().bit()), + ) + .field( + "gpio48_slp_sel", + &format_args!("{}", self.gpio48_slp_sel().bit()), + ) + .field( + "gpio48_mcu_wpd", + &format_args!("{}", self.gpio48_mcu_wpd().bit()), + ) + .field( + "gpio48_mcu_wpu", + &format_args!("{}", self.gpio48_mcu_wpu().bit()), + ) + .field( + "gpio48_mcu_ie", + &format_args!("{}", self.gpio48_mcu_ie().bit()), + ) + .field( + "gpio48_mcu_drv", + &format_args!("{}", self.gpio48_mcu_drv().bits()), + ) + .field( + "gpio48_fun_wpd", + &format_args!("{}", self.gpio48_fun_wpd().bit()), + ) + .field( + "gpio48_fun_wpu", + &format_args!("{}", self.gpio48_fun_wpu().bit()), + ) + .field( + "gpio48_fun_ie", + &format_args!("{}", self.gpio48_fun_ie().bit()), + ) + .field( + "gpio48_fun_drv", + &format_args!("{}", self.gpio48_fun_drv().bits()), + ) + .field( + "gpio48_mcu_sel", + &format_args!("{}", self.gpio48_mcu_sel().bits()), + ) + .field( + "gpio48_filter_en", + &format_args!("{}", self.gpio48_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio48_mcu_oe(&mut self) -> GPIO48_MCU_OE_W { + GPIO48_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio48_slp_sel(&mut self) -> GPIO48_SLP_SEL_W { + GPIO48_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio48_mcu_wpd(&mut self) -> GPIO48_MCU_WPD_W { + GPIO48_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio48_mcu_wpu(&mut self) -> GPIO48_MCU_WPU_W { + GPIO48_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio48_mcu_ie(&mut self) -> GPIO48_MCU_IE_W { + GPIO48_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio48_mcu_drv(&mut self) -> GPIO48_MCU_DRV_W { + GPIO48_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio48_fun_wpd(&mut self) -> GPIO48_FUN_WPD_W { + GPIO48_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio48_fun_wpu(&mut self) -> GPIO48_FUN_WPU_W { + GPIO48_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio48_fun_ie(&mut self) -> GPIO48_FUN_IE_W { + GPIO48_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio48_fun_drv(&mut self) -> GPIO48_FUN_DRV_W { + GPIO48_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio48_mcu_sel(&mut self) -> GPIO48_MCU_SEL_W { + GPIO48_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio48_filter_en(&mut self) -> GPIO48_FILTER_EN_W { + GPIO48_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio48\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio48::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio48::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO48_SPEC; +impl crate::RegisterSpec for GPIO48_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio48::R`](R) reader structure"] +impl crate::Readable for GPIO48_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio48::W`](W) writer structure"] +impl crate::Writable for GPIO48_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio48 to value 0x0800"] +impl crate::Resettable for GPIO48_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio49.rs b/esp32p4/src/io_mux/gpio49.rs new file mode 100644 index 0000000000..19fde06c9b --- /dev/null +++ b/esp32p4/src/io_mux/gpio49.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio49` reader"] +pub type R = crate::R; +#[doc = "Register `gpio49` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO49_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO49_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO49_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO49_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO49_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO49_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO49_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO49_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO49_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO49_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO49_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO49_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO49_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO49_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO49_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO49_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO49_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO49_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO49_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO49_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO49_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO49_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO49_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO49_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO49_FUN_WPD` reader - pull-down enable"] +pub type GPIO49_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO49_FUN_WPD` writer - pull-down enable"] +pub type GPIO49_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO49_FUN_WPU` reader - pull-up enable"] +pub type GPIO49_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO49_FUN_WPU` writer - pull-up enable"] +pub type GPIO49_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO49_FUN_IE` reader - input enable"] +pub type GPIO49_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO49_FUN_IE` writer - input enable"] +pub type GPIO49_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO49_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO49_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO49_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO49_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO49_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO49_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO49_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO49_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO49_FILTER_EN` reader - input filter enable"] +pub type GPIO49_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO49_FILTER_EN` writer - input filter enable"] +pub type GPIO49_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio49_mcu_oe(&self) -> GPIO49_MCU_OE_R { + GPIO49_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio49_slp_sel(&self) -> GPIO49_SLP_SEL_R { + GPIO49_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio49_mcu_wpd(&self) -> GPIO49_MCU_WPD_R { + GPIO49_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio49_mcu_wpu(&self) -> GPIO49_MCU_WPU_R { + GPIO49_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio49_mcu_ie(&self) -> GPIO49_MCU_IE_R { + GPIO49_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio49_mcu_drv(&self) -> GPIO49_MCU_DRV_R { + GPIO49_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio49_fun_wpd(&self) -> GPIO49_FUN_WPD_R { + GPIO49_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio49_fun_wpu(&self) -> GPIO49_FUN_WPU_R { + GPIO49_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio49_fun_ie(&self) -> GPIO49_FUN_IE_R { + GPIO49_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio49_fun_drv(&self) -> GPIO49_FUN_DRV_R { + GPIO49_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio49_mcu_sel(&self) -> GPIO49_MCU_SEL_R { + GPIO49_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio49_filter_en(&self) -> GPIO49_FILTER_EN_R { + GPIO49_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio49") + .field( + "gpio49_mcu_oe", + &format_args!("{}", self.gpio49_mcu_oe().bit()), + ) + .field( + "gpio49_slp_sel", + &format_args!("{}", self.gpio49_slp_sel().bit()), + ) + .field( + "gpio49_mcu_wpd", + &format_args!("{}", self.gpio49_mcu_wpd().bit()), + ) + .field( + "gpio49_mcu_wpu", + &format_args!("{}", self.gpio49_mcu_wpu().bit()), + ) + .field( + "gpio49_mcu_ie", + &format_args!("{}", self.gpio49_mcu_ie().bit()), + ) + .field( + "gpio49_mcu_drv", + &format_args!("{}", self.gpio49_mcu_drv().bits()), + ) + .field( + "gpio49_fun_wpd", + &format_args!("{}", self.gpio49_fun_wpd().bit()), + ) + .field( + "gpio49_fun_wpu", + &format_args!("{}", self.gpio49_fun_wpu().bit()), + ) + .field( + "gpio49_fun_ie", + &format_args!("{}", self.gpio49_fun_ie().bit()), + ) + .field( + "gpio49_fun_drv", + &format_args!("{}", self.gpio49_fun_drv().bits()), + ) + .field( + "gpio49_mcu_sel", + &format_args!("{}", self.gpio49_mcu_sel().bits()), + ) + .field( + "gpio49_filter_en", + &format_args!("{}", self.gpio49_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio49_mcu_oe(&mut self) -> GPIO49_MCU_OE_W { + GPIO49_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio49_slp_sel(&mut self) -> GPIO49_SLP_SEL_W { + GPIO49_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio49_mcu_wpd(&mut self) -> GPIO49_MCU_WPD_W { + GPIO49_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio49_mcu_wpu(&mut self) -> GPIO49_MCU_WPU_W { + GPIO49_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio49_mcu_ie(&mut self) -> GPIO49_MCU_IE_W { + GPIO49_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio49_mcu_drv(&mut self) -> GPIO49_MCU_DRV_W { + GPIO49_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio49_fun_wpd(&mut self) -> GPIO49_FUN_WPD_W { + GPIO49_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio49_fun_wpu(&mut self) -> GPIO49_FUN_WPU_W { + GPIO49_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio49_fun_ie(&mut self) -> GPIO49_FUN_IE_W { + GPIO49_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio49_fun_drv(&mut self) -> GPIO49_FUN_DRV_W { + GPIO49_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio49_mcu_sel(&mut self) -> GPIO49_MCU_SEL_W { + GPIO49_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio49_filter_en(&mut self) -> GPIO49_FILTER_EN_W { + GPIO49_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio49\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio49::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio49::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO49_SPEC; +impl crate::RegisterSpec for GPIO49_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio49::R`](R) reader structure"] +impl crate::Readable for GPIO49_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio49::W`](W) writer structure"] +impl crate::Writable for GPIO49_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio49 to value 0x0800"] +impl crate::Resettable for GPIO49_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio5.rs b/esp32p4/src/io_mux/gpio5.rs new file mode 100644 index 0000000000..cceb82b1b3 --- /dev/null +++ b/esp32p4/src/io_mux/gpio5.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio5` reader"] +pub type R = crate::R; +#[doc = "Register `gpio5` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO5_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO5_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO5_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO5_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO5_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO5_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO5_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO5_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO5_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO5_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO5_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO5_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO5_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO5_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO5_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO5_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO5_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO5_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO5_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO5_FUN_WPD` reader - pull-down enable"] +pub type GPIO5_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO5_FUN_WPD` writer - pull-down enable"] +pub type GPIO5_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_FUN_WPU` reader - pull-up enable"] +pub type GPIO5_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO5_FUN_WPU` writer - pull-up enable"] +pub type GPIO5_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_FUN_IE` reader - input enable"] +pub type GPIO5_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO5_FUN_IE` writer - input enable"] +pub type GPIO5_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO5_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO5_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO5_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO5_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO5_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO5_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO5_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO5_FILTER_EN` reader - input filter enable"] +pub type GPIO5_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO5_FILTER_EN` writer - input filter enable"] +pub type GPIO5_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio5_mcu_oe(&self) -> GPIO5_MCU_OE_R { + GPIO5_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio5_slp_sel(&self) -> GPIO5_SLP_SEL_R { + GPIO5_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio5_mcu_wpd(&self) -> GPIO5_MCU_WPD_R { + GPIO5_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio5_mcu_wpu(&self) -> GPIO5_MCU_WPU_R { + GPIO5_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio5_mcu_ie(&self) -> GPIO5_MCU_IE_R { + GPIO5_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio5_mcu_drv(&self) -> GPIO5_MCU_DRV_R { + GPIO5_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio5_fun_wpd(&self) -> GPIO5_FUN_WPD_R { + GPIO5_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio5_fun_wpu(&self) -> GPIO5_FUN_WPU_R { + GPIO5_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio5_fun_ie(&self) -> GPIO5_FUN_IE_R { + GPIO5_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio5_fun_drv(&self) -> GPIO5_FUN_DRV_R { + GPIO5_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio5_mcu_sel(&self) -> GPIO5_MCU_SEL_R { + GPIO5_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio5_filter_en(&self) -> GPIO5_FILTER_EN_R { + GPIO5_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio5") + .field( + "gpio5_mcu_oe", + &format_args!("{}", self.gpio5_mcu_oe().bit()), + ) + .field( + "gpio5_slp_sel", + &format_args!("{}", self.gpio5_slp_sel().bit()), + ) + .field( + "gpio5_mcu_wpd", + &format_args!("{}", self.gpio5_mcu_wpd().bit()), + ) + .field( + "gpio5_mcu_wpu", + &format_args!("{}", self.gpio5_mcu_wpu().bit()), + ) + .field( + "gpio5_mcu_ie", + &format_args!("{}", self.gpio5_mcu_ie().bit()), + ) + .field( + "gpio5_mcu_drv", + &format_args!("{}", self.gpio5_mcu_drv().bits()), + ) + .field( + "gpio5_fun_wpd", + &format_args!("{}", self.gpio5_fun_wpd().bit()), + ) + .field( + "gpio5_fun_wpu", + &format_args!("{}", self.gpio5_fun_wpu().bit()), + ) + .field( + "gpio5_fun_ie", + &format_args!("{}", self.gpio5_fun_ie().bit()), + ) + .field( + "gpio5_fun_drv", + &format_args!("{}", self.gpio5_fun_drv().bits()), + ) + .field( + "gpio5_mcu_sel", + &format_args!("{}", self.gpio5_mcu_sel().bits()), + ) + .field( + "gpio5_filter_en", + &format_args!("{}", self.gpio5_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio5_mcu_oe(&mut self) -> GPIO5_MCU_OE_W { + GPIO5_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio5_slp_sel(&mut self) -> GPIO5_SLP_SEL_W { + GPIO5_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio5_mcu_wpd(&mut self) -> GPIO5_MCU_WPD_W { + GPIO5_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio5_mcu_wpu(&mut self) -> GPIO5_MCU_WPU_W { + GPIO5_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio5_mcu_ie(&mut self) -> GPIO5_MCU_IE_W { + GPIO5_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio5_mcu_drv(&mut self) -> GPIO5_MCU_DRV_W { + GPIO5_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio5_fun_wpd(&mut self) -> GPIO5_FUN_WPD_W { + GPIO5_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio5_fun_wpu(&mut self) -> GPIO5_FUN_WPU_W { + GPIO5_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio5_fun_ie(&mut self) -> GPIO5_FUN_IE_W { + GPIO5_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio5_fun_drv(&mut self) -> GPIO5_FUN_DRV_W { + GPIO5_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio5_mcu_sel(&mut self) -> GPIO5_MCU_SEL_W { + GPIO5_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio5_filter_en(&mut self) -> GPIO5_FILTER_EN_W { + GPIO5_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO5_SPEC; +impl crate::RegisterSpec for GPIO5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio5::R`](R) reader structure"] +impl crate::Readable for GPIO5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio5::W`](W) writer structure"] +impl crate::Writable for GPIO5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio5 to value 0x0800"] +impl crate::Resettable for GPIO5_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio50.rs b/esp32p4/src/io_mux/gpio50.rs new file mode 100644 index 0000000000..a615536b1f --- /dev/null +++ b/esp32p4/src/io_mux/gpio50.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio50` reader"] +pub type R = crate::R; +#[doc = "Register `gpio50` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO50_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO50_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO50_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO50_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO50_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO50_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO50_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO50_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO50_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO50_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO50_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO50_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO50_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO50_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO50_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO50_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO50_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO50_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO50_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO50_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO50_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO50_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO50_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO50_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO50_FUN_WPD` reader - pull-down enable"] +pub type GPIO50_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO50_FUN_WPD` writer - pull-down enable"] +pub type GPIO50_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO50_FUN_WPU` reader - pull-up enable"] +pub type GPIO50_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO50_FUN_WPU` writer - pull-up enable"] +pub type GPIO50_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO50_FUN_IE` reader - input enable"] +pub type GPIO50_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO50_FUN_IE` writer - input enable"] +pub type GPIO50_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO50_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO50_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO50_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO50_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO50_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO50_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO50_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO50_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO50_FILTER_EN` reader - input filter enable"] +pub type GPIO50_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO50_FILTER_EN` writer - input filter enable"] +pub type GPIO50_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio50_mcu_oe(&self) -> GPIO50_MCU_OE_R { + GPIO50_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio50_slp_sel(&self) -> GPIO50_SLP_SEL_R { + GPIO50_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio50_mcu_wpd(&self) -> GPIO50_MCU_WPD_R { + GPIO50_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio50_mcu_wpu(&self) -> GPIO50_MCU_WPU_R { + GPIO50_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio50_mcu_ie(&self) -> GPIO50_MCU_IE_R { + GPIO50_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio50_mcu_drv(&self) -> GPIO50_MCU_DRV_R { + GPIO50_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio50_fun_wpd(&self) -> GPIO50_FUN_WPD_R { + GPIO50_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio50_fun_wpu(&self) -> GPIO50_FUN_WPU_R { + GPIO50_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio50_fun_ie(&self) -> GPIO50_FUN_IE_R { + GPIO50_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio50_fun_drv(&self) -> GPIO50_FUN_DRV_R { + GPIO50_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio50_mcu_sel(&self) -> GPIO50_MCU_SEL_R { + GPIO50_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio50_filter_en(&self) -> GPIO50_FILTER_EN_R { + GPIO50_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio50") + .field( + "gpio50_mcu_oe", + &format_args!("{}", self.gpio50_mcu_oe().bit()), + ) + .field( + "gpio50_slp_sel", + &format_args!("{}", self.gpio50_slp_sel().bit()), + ) + .field( + "gpio50_mcu_wpd", + &format_args!("{}", self.gpio50_mcu_wpd().bit()), + ) + .field( + "gpio50_mcu_wpu", + &format_args!("{}", self.gpio50_mcu_wpu().bit()), + ) + .field( + "gpio50_mcu_ie", + &format_args!("{}", self.gpio50_mcu_ie().bit()), + ) + .field( + "gpio50_mcu_drv", + &format_args!("{}", self.gpio50_mcu_drv().bits()), + ) + .field( + "gpio50_fun_wpd", + &format_args!("{}", self.gpio50_fun_wpd().bit()), + ) + .field( + "gpio50_fun_wpu", + &format_args!("{}", self.gpio50_fun_wpu().bit()), + ) + .field( + "gpio50_fun_ie", + &format_args!("{}", self.gpio50_fun_ie().bit()), + ) + .field( + "gpio50_fun_drv", + &format_args!("{}", self.gpio50_fun_drv().bits()), + ) + .field( + "gpio50_mcu_sel", + &format_args!("{}", self.gpio50_mcu_sel().bits()), + ) + .field( + "gpio50_filter_en", + &format_args!("{}", self.gpio50_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio50_mcu_oe(&mut self) -> GPIO50_MCU_OE_W { + GPIO50_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio50_slp_sel(&mut self) -> GPIO50_SLP_SEL_W { + GPIO50_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio50_mcu_wpd(&mut self) -> GPIO50_MCU_WPD_W { + GPIO50_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio50_mcu_wpu(&mut self) -> GPIO50_MCU_WPU_W { + GPIO50_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio50_mcu_ie(&mut self) -> GPIO50_MCU_IE_W { + GPIO50_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio50_mcu_drv(&mut self) -> GPIO50_MCU_DRV_W { + GPIO50_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio50_fun_wpd(&mut self) -> GPIO50_FUN_WPD_W { + GPIO50_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio50_fun_wpu(&mut self) -> GPIO50_FUN_WPU_W { + GPIO50_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio50_fun_ie(&mut self) -> GPIO50_FUN_IE_W { + GPIO50_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio50_fun_drv(&mut self) -> GPIO50_FUN_DRV_W { + GPIO50_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio50_mcu_sel(&mut self) -> GPIO50_MCU_SEL_W { + GPIO50_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio50_filter_en(&mut self) -> GPIO50_FILTER_EN_W { + GPIO50_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio50\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio50::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio50::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO50_SPEC; +impl crate::RegisterSpec for GPIO50_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio50::R`](R) reader structure"] +impl crate::Readable for GPIO50_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio50::W`](W) writer structure"] +impl crate::Writable for GPIO50_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio50 to value 0x0800"] +impl crate::Resettable for GPIO50_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio51.rs b/esp32p4/src/io_mux/gpio51.rs new file mode 100644 index 0000000000..fb83fb912f --- /dev/null +++ b/esp32p4/src/io_mux/gpio51.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio51` reader"] +pub type R = crate::R; +#[doc = "Register `gpio51` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO51_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO51_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO51_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO51_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO51_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO51_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO51_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO51_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO51_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO51_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO51_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO51_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO51_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO51_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO51_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO51_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO51_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO51_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO51_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO51_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO51_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO51_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO51_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO51_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO51_FUN_WPD` reader - pull-down enable"] +pub type GPIO51_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO51_FUN_WPD` writer - pull-down enable"] +pub type GPIO51_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO51_FUN_WPU` reader - pull-up enable"] +pub type GPIO51_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO51_FUN_WPU` writer - pull-up enable"] +pub type GPIO51_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO51_FUN_IE` reader - input enable"] +pub type GPIO51_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO51_FUN_IE` writer - input enable"] +pub type GPIO51_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO51_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO51_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO51_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO51_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO51_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO51_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO51_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO51_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO51_FILTER_EN` reader - input filter enable"] +pub type GPIO51_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO51_FILTER_EN` writer - input filter enable"] +pub type GPIO51_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio51_mcu_oe(&self) -> GPIO51_MCU_OE_R { + GPIO51_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio51_slp_sel(&self) -> GPIO51_SLP_SEL_R { + GPIO51_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio51_mcu_wpd(&self) -> GPIO51_MCU_WPD_R { + GPIO51_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio51_mcu_wpu(&self) -> GPIO51_MCU_WPU_R { + GPIO51_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio51_mcu_ie(&self) -> GPIO51_MCU_IE_R { + GPIO51_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio51_mcu_drv(&self) -> GPIO51_MCU_DRV_R { + GPIO51_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio51_fun_wpd(&self) -> GPIO51_FUN_WPD_R { + GPIO51_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio51_fun_wpu(&self) -> GPIO51_FUN_WPU_R { + GPIO51_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio51_fun_ie(&self) -> GPIO51_FUN_IE_R { + GPIO51_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio51_fun_drv(&self) -> GPIO51_FUN_DRV_R { + GPIO51_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio51_mcu_sel(&self) -> GPIO51_MCU_SEL_R { + GPIO51_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio51_filter_en(&self) -> GPIO51_FILTER_EN_R { + GPIO51_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio51") + .field( + "gpio51_mcu_oe", + &format_args!("{}", self.gpio51_mcu_oe().bit()), + ) + .field( + "gpio51_slp_sel", + &format_args!("{}", self.gpio51_slp_sel().bit()), + ) + .field( + "gpio51_mcu_wpd", + &format_args!("{}", self.gpio51_mcu_wpd().bit()), + ) + .field( + "gpio51_mcu_wpu", + &format_args!("{}", self.gpio51_mcu_wpu().bit()), + ) + .field( + "gpio51_mcu_ie", + &format_args!("{}", self.gpio51_mcu_ie().bit()), + ) + .field( + "gpio51_mcu_drv", + &format_args!("{}", self.gpio51_mcu_drv().bits()), + ) + .field( + "gpio51_fun_wpd", + &format_args!("{}", self.gpio51_fun_wpd().bit()), + ) + .field( + "gpio51_fun_wpu", + &format_args!("{}", self.gpio51_fun_wpu().bit()), + ) + .field( + "gpio51_fun_ie", + &format_args!("{}", self.gpio51_fun_ie().bit()), + ) + .field( + "gpio51_fun_drv", + &format_args!("{}", self.gpio51_fun_drv().bits()), + ) + .field( + "gpio51_mcu_sel", + &format_args!("{}", self.gpio51_mcu_sel().bits()), + ) + .field( + "gpio51_filter_en", + &format_args!("{}", self.gpio51_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio51_mcu_oe(&mut self) -> GPIO51_MCU_OE_W { + GPIO51_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio51_slp_sel(&mut self) -> GPIO51_SLP_SEL_W { + GPIO51_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio51_mcu_wpd(&mut self) -> GPIO51_MCU_WPD_W { + GPIO51_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio51_mcu_wpu(&mut self) -> GPIO51_MCU_WPU_W { + GPIO51_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio51_mcu_ie(&mut self) -> GPIO51_MCU_IE_W { + GPIO51_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio51_mcu_drv(&mut self) -> GPIO51_MCU_DRV_W { + GPIO51_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio51_fun_wpd(&mut self) -> GPIO51_FUN_WPD_W { + GPIO51_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio51_fun_wpu(&mut self) -> GPIO51_FUN_WPU_W { + GPIO51_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio51_fun_ie(&mut self) -> GPIO51_FUN_IE_W { + GPIO51_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio51_fun_drv(&mut self) -> GPIO51_FUN_DRV_W { + GPIO51_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio51_mcu_sel(&mut self) -> GPIO51_MCU_SEL_W { + GPIO51_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio51_filter_en(&mut self) -> GPIO51_FILTER_EN_W { + GPIO51_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio51\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio51::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio51::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO51_SPEC; +impl crate::RegisterSpec for GPIO51_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio51::R`](R) reader structure"] +impl crate::Readable for GPIO51_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio51::W`](W) writer structure"] +impl crate::Writable for GPIO51_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio51 to value 0x0800"] +impl crate::Resettable for GPIO51_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio52.rs b/esp32p4/src/io_mux/gpio52.rs new file mode 100644 index 0000000000..baee91462c --- /dev/null +++ b/esp32p4/src/io_mux/gpio52.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio52` reader"] +pub type R = crate::R; +#[doc = "Register `gpio52` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO52_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO52_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO52_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO52_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO52_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO52_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO52_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO52_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO52_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO52_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO52_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO52_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO52_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO52_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO52_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO52_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO52_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO52_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO52_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO52_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO52_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO52_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO52_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO52_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO52_FUN_WPD` reader - pull-down enable"] +pub type GPIO52_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO52_FUN_WPD` writer - pull-down enable"] +pub type GPIO52_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO52_FUN_WPU` reader - pull-up enable"] +pub type GPIO52_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO52_FUN_WPU` writer - pull-up enable"] +pub type GPIO52_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO52_FUN_IE` reader - input enable"] +pub type GPIO52_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO52_FUN_IE` writer - input enable"] +pub type GPIO52_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO52_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO52_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO52_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO52_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO52_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO52_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO52_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO52_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO52_FILTER_EN` reader - input filter enable"] +pub type GPIO52_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO52_FILTER_EN` writer - input filter enable"] +pub type GPIO52_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio52_mcu_oe(&self) -> GPIO52_MCU_OE_R { + GPIO52_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio52_slp_sel(&self) -> GPIO52_SLP_SEL_R { + GPIO52_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio52_mcu_wpd(&self) -> GPIO52_MCU_WPD_R { + GPIO52_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio52_mcu_wpu(&self) -> GPIO52_MCU_WPU_R { + GPIO52_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio52_mcu_ie(&self) -> GPIO52_MCU_IE_R { + GPIO52_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio52_mcu_drv(&self) -> GPIO52_MCU_DRV_R { + GPIO52_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio52_fun_wpd(&self) -> GPIO52_FUN_WPD_R { + GPIO52_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio52_fun_wpu(&self) -> GPIO52_FUN_WPU_R { + GPIO52_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio52_fun_ie(&self) -> GPIO52_FUN_IE_R { + GPIO52_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio52_fun_drv(&self) -> GPIO52_FUN_DRV_R { + GPIO52_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio52_mcu_sel(&self) -> GPIO52_MCU_SEL_R { + GPIO52_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio52_filter_en(&self) -> GPIO52_FILTER_EN_R { + GPIO52_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio52") + .field( + "gpio52_mcu_oe", + &format_args!("{}", self.gpio52_mcu_oe().bit()), + ) + .field( + "gpio52_slp_sel", + &format_args!("{}", self.gpio52_slp_sel().bit()), + ) + .field( + "gpio52_mcu_wpd", + &format_args!("{}", self.gpio52_mcu_wpd().bit()), + ) + .field( + "gpio52_mcu_wpu", + &format_args!("{}", self.gpio52_mcu_wpu().bit()), + ) + .field( + "gpio52_mcu_ie", + &format_args!("{}", self.gpio52_mcu_ie().bit()), + ) + .field( + "gpio52_mcu_drv", + &format_args!("{}", self.gpio52_mcu_drv().bits()), + ) + .field( + "gpio52_fun_wpd", + &format_args!("{}", self.gpio52_fun_wpd().bit()), + ) + .field( + "gpio52_fun_wpu", + &format_args!("{}", self.gpio52_fun_wpu().bit()), + ) + .field( + "gpio52_fun_ie", + &format_args!("{}", self.gpio52_fun_ie().bit()), + ) + .field( + "gpio52_fun_drv", + &format_args!("{}", self.gpio52_fun_drv().bits()), + ) + .field( + "gpio52_mcu_sel", + &format_args!("{}", self.gpio52_mcu_sel().bits()), + ) + .field( + "gpio52_filter_en", + &format_args!("{}", self.gpio52_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio52_mcu_oe(&mut self) -> GPIO52_MCU_OE_W { + GPIO52_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio52_slp_sel(&mut self) -> GPIO52_SLP_SEL_W { + GPIO52_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio52_mcu_wpd(&mut self) -> GPIO52_MCU_WPD_W { + GPIO52_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio52_mcu_wpu(&mut self) -> GPIO52_MCU_WPU_W { + GPIO52_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio52_mcu_ie(&mut self) -> GPIO52_MCU_IE_W { + GPIO52_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio52_mcu_drv(&mut self) -> GPIO52_MCU_DRV_W { + GPIO52_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio52_fun_wpd(&mut self) -> GPIO52_FUN_WPD_W { + GPIO52_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio52_fun_wpu(&mut self) -> GPIO52_FUN_WPU_W { + GPIO52_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio52_fun_ie(&mut self) -> GPIO52_FUN_IE_W { + GPIO52_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio52_fun_drv(&mut self) -> GPIO52_FUN_DRV_W { + GPIO52_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio52_mcu_sel(&mut self) -> GPIO52_MCU_SEL_W { + GPIO52_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio52_filter_en(&mut self) -> GPIO52_FILTER_EN_W { + GPIO52_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio52\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio52::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio52::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO52_SPEC; +impl crate::RegisterSpec for GPIO52_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio52::R`](R) reader structure"] +impl crate::Readable for GPIO52_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio52::W`](W) writer structure"] +impl crate::Writable for GPIO52_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio52 to value 0x0800"] +impl crate::Resettable for GPIO52_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio53.rs b/esp32p4/src/io_mux/gpio53.rs new file mode 100644 index 0000000000..a46512f987 --- /dev/null +++ b/esp32p4/src/io_mux/gpio53.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio53` reader"] +pub type R = crate::R; +#[doc = "Register `gpio53` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO53_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO53_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO53_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO53_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO53_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO53_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO53_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO53_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO53_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO53_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO53_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO53_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO53_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO53_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO53_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO53_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO53_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO53_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO53_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO53_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO53_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO53_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO53_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO53_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO53_FUN_WPD` reader - pull-down enable"] +pub type GPIO53_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO53_FUN_WPD` writer - pull-down enable"] +pub type GPIO53_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO53_FUN_WPU` reader - pull-up enable"] +pub type GPIO53_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO53_FUN_WPU` writer - pull-up enable"] +pub type GPIO53_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO53_FUN_IE` reader - input enable"] +pub type GPIO53_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO53_FUN_IE` writer - input enable"] +pub type GPIO53_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO53_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO53_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO53_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO53_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO53_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO53_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO53_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO53_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO53_FILTER_EN` reader - input filter enable"] +pub type GPIO53_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO53_FILTER_EN` writer - input filter enable"] +pub type GPIO53_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio53_mcu_oe(&self) -> GPIO53_MCU_OE_R { + GPIO53_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio53_slp_sel(&self) -> GPIO53_SLP_SEL_R { + GPIO53_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio53_mcu_wpd(&self) -> GPIO53_MCU_WPD_R { + GPIO53_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio53_mcu_wpu(&self) -> GPIO53_MCU_WPU_R { + GPIO53_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio53_mcu_ie(&self) -> GPIO53_MCU_IE_R { + GPIO53_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio53_mcu_drv(&self) -> GPIO53_MCU_DRV_R { + GPIO53_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio53_fun_wpd(&self) -> GPIO53_FUN_WPD_R { + GPIO53_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio53_fun_wpu(&self) -> GPIO53_FUN_WPU_R { + GPIO53_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio53_fun_ie(&self) -> GPIO53_FUN_IE_R { + GPIO53_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio53_fun_drv(&self) -> GPIO53_FUN_DRV_R { + GPIO53_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio53_mcu_sel(&self) -> GPIO53_MCU_SEL_R { + GPIO53_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio53_filter_en(&self) -> GPIO53_FILTER_EN_R { + GPIO53_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio53") + .field( + "gpio53_mcu_oe", + &format_args!("{}", self.gpio53_mcu_oe().bit()), + ) + .field( + "gpio53_slp_sel", + &format_args!("{}", self.gpio53_slp_sel().bit()), + ) + .field( + "gpio53_mcu_wpd", + &format_args!("{}", self.gpio53_mcu_wpd().bit()), + ) + .field( + "gpio53_mcu_wpu", + &format_args!("{}", self.gpio53_mcu_wpu().bit()), + ) + .field( + "gpio53_mcu_ie", + &format_args!("{}", self.gpio53_mcu_ie().bit()), + ) + .field( + "gpio53_mcu_drv", + &format_args!("{}", self.gpio53_mcu_drv().bits()), + ) + .field( + "gpio53_fun_wpd", + &format_args!("{}", self.gpio53_fun_wpd().bit()), + ) + .field( + "gpio53_fun_wpu", + &format_args!("{}", self.gpio53_fun_wpu().bit()), + ) + .field( + "gpio53_fun_ie", + &format_args!("{}", self.gpio53_fun_ie().bit()), + ) + .field( + "gpio53_fun_drv", + &format_args!("{}", self.gpio53_fun_drv().bits()), + ) + .field( + "gpio53_mcu_sel", + &format_args!("{}", self.gpio53_mcu_sel().bits()), + ) + .field( + "gpio53_filter_en", + &format_args!("{}", self.gpio53_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio53_mcu_oe(&mut self) -> GPIO53_MCU_OE_W { + GPIO53_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio53_slp_sel(&mut self) -> GPIO53_SLP_SEL_W { + GPIO53_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio53_mcu_wpd(&mut self) -> GPIO53_MCU_WPD_W { + GPIO53_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio53_mcu_wpu(&mut self) -> GPIO53_MCU_WPU_W { + GPIO53_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio53_mcu_ie(&mut self) -> GPIO53_MCU_IE_W { + GPIO53_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio53_mcu_drv(&mut self) -> GPIO53_MCU_DRV_W { + GPIO53_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio53_fun_wpd(&mut self) -> GPIO53_FUN_WPD_W { + GPIO53_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio53_fun_wpu(&mut self) -> GPIO53_FUN_WPU_W { + GPIO53_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio53_fun_ie(&mut self) -> GPIO53_FUN_IE_W { + GPIO53_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio53_fun_drv(&mut self) -> GPIO53_FUN_DRV_W { + GPIO53_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio53_mcu_sel(&mut self) -> GPIO53_MCU_SEL_W { + GPIO53_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio53_filter_en(&mut self) -> GPIO53_FILTER_EN_W { + GPIO53_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio53::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio53::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO53_SPEC; +impl crate::RegisterSpec for GPIO53_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio53::R`](R) reader structure"] +impl crate::Readable for GPIO53_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio53::W`](W) writer structure"] +impl crate::Writable for GPIO53_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio53 to value 0x0800"] +impl crate::Resettable for GPIO53_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio54.rs b/esp32p4/src/io_mux/gpio54.rs new file mode 100644 index 0000000000..ee6dba0958 --- /dev/null +++ b/esp32p4/src/io_mux/gpio54.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio54` reader"] +pub type R = crate::R; +#[doc = "Register `gpio54` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO54_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO54_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO54_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO54_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO54_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO54_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO54_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO54_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO54_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO54_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO54_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO54_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO54_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO54_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO54_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO54_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO54_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO54_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO54_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO54_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO54_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO54_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO54_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO54_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO54_FUN_WPD` reader - pull-down enable"] +pub type GPIO54_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO54_FUN_WPD` writer - pull-down enable"] +pub type GPIO54_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO54_FUN_WPU` reader - pull-up enable"] +pub type GPIO54_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO54_FUN_WPU` writer - pull-up enable"] +pub type GPIO54_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO54_FUN_IE` reader - input enable"] +pub type GPIO54_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO54_FUN_IE` writer - input enable"] +pub type GPIO54_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO54_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO54_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO54_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO54_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO54_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO54_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO54_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO54_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO54_FILTER_EN` reader - input filter enable"] +pub type GPIO54_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO54_FILTER_EN` writer - input filter enable"] +pub type GPIO54_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio54_mcu_oe(&self) -> GPIO54_MCU_OE_R { + GPIO54_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio54_slp_sel(&self) -> GPIO54_SLP_SEL_R { + GPIO54_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio54_mcu_wpd(&self) -> GPIO54_MCU_WPD_R { + GPIO54_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio54_mcu_wpu(&self) -> GPIO54_MCU_WPU_R { + GPIO54_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio54_mcu_ie(&self) -> GPIO54_MCU_IE_R { + GPIO54_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio54_mcu_drv(&self) -> GPIO54_MCU_DRV_R { + GPIO54_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio54_fun_wpd(&self) -> GPIO54_FUN_WPD_R { + GPIO54_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio54_fun_wpu(&self) -> GPIO54_FUN_WPU_R { + GPIO54_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio54_fun_ie(&self) -> GPIO54_FUN_IE_R { + GPIO54_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio54_fun_drv(&self) -> GPIO54_FUN_DRV_R { + GPIO54_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio54_mcu_sel(&self) -> GPIO54_MCU_SEL_R { + GPIO54_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio54_filter_en(&self) -> GPIO54_FILTER_EN_R { + GPIO54_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio54") + .field( + "gpio54_mcu_oe", + &format_args!("{}", self.gpio54_mcu_oe().bit()), + ) + .field( + "gpio54_slp_sel", + &format_args!("{}", self.gpio54_slp_sel().bit()), + ) + .field( + "gpio54_mcu_wpd", + &format_args!("{}", self.gpio54_mcu_wpd().bit()), + ) + .field( + "gpio54_mcu_wpu", + &format_args!("{}", self.gpio54_mcu_wpu().bit()), + ) + .field( + "gpio54_mcu_ie", + &format_args!("{}", self.gpio54_mcu_ie().bit()), + ) + .field( + "gpio54_mcu_drv", + &format_args!("{}", self.gpio54_mcu_drv().bits()), + ) + .field( + "gpio54_fun_wpd", + &format_args!("{}", self.gpio54_fun_wpd().bit()), + ) + .field( + "gpio54_fun_wpu", + &format_args!("{}", self.gpio54_fun_wpu().bit()), + ) + .field( + "gpio54_fun_ie", + &format_args!("{}", self.gpio54_fun_ie().bit()), + ) + .field( + "gpio54_fun_drv", + &format_args!("{}", self.gpio54_fun_drv().bits()), + ) + .field( + "gpio54_mcu_sel", + &format_args!("{}", self.gpio54_mcu_sel().bits()), + ) + .field( + "gpio54_filter_en", + &format_args!("{}", self.gpio54_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio54_mcu_oe(&mut self) -> GPIO54_MCU_OE_W { + GPIO54_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio54_slp_sel(&mut self) -> GPIO54_SLP_SEL_W { + GPIO54_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio54_mcu_wpd(&mut self) -> GPIO54_MCU_WPD_W { + GPIO54_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio54_mcu_wpu(&mut self) -> GPIO54_MCU_WPU_W { + GPIO54_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio54_mcu_ie(&mut self) -> GPIO54_MCU_IE_W { + GPIO54_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio54_mcu_drv(&mut self) -> GPIO54_MCU_DRV_W { + GPIO54_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio54_fun_wpd(&mut self) -> GPIO54_FUN_WPD_W { + GPIO54_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio54_fun_wpu(&mut self) -> GPIO54_FUN_WPU_W { + GPIO54_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio54_fun_ie(&mut self) -> GPIO54_FUN_IE_W { + GPIO54_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio54_fun_drv(&mut self) -> GPIO54_FUN_DRV_W { + GPIO54_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio54_mcu_sel(&mut self) -> GPIO54_MCU_SEL_W { + GPIO54_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio54_filter_en(&mut self) -> GPIO54_FILTER_EN_W { + GPIO54_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio54\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio54::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio54::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO54_SPEC; +impl crate::RegisterSpec for GPIO54_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio54::R`](R) reader structure"] +impl crate::Readable for GPIO54_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio54::W`](W) writer structure"] +impl crate::Writable for GPIO54_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio54 to value 0x0800"] +impl crate::Resettable for GPIO54_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio55.rs b/esp32p4/src/io_mux/gpio55.rs new file mode 100644 index 0000000000..8021a3a714 --- /dev/null +++ b/esp32p4/src/io_mux/gpio55.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio55` reader"] +pub type R = crate::R; +#[doc = "Register `gpio55` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO55_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO55_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO55_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO55_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO55_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO55_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO55_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO55_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO55_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO55_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO55_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO55_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO55_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO55_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO55_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO55_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO55_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO55_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO55_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO55_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO55_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO55_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO55_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO55_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO55_FUN_WPD` reader - pull-down enable"] +pub type GPIO55_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO55_FUN_WPD` writer - pull-down enable"] +pub type GPIO55_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO55_FUN_WPU` reader - pull-up enable"] +pub type GPIO55_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO55_FUN_WPU` writer - pull-up enable"] +pub type GPIO55_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO55_FUN_IE` reader - input enable"] +pub type GPIO55_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO55_FUN_IE` writer - input enable"] +pub type GPIO55_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO55_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO55_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO55_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO55_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO55_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO55_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO55_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO55_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO55_FILTER_EN` reader - input filter enable"] +pub type GPIO55_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO55_FILTER_EN` writer - input filter enable"] +pub type GPIO55_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio55_mcu_oe(&self) -> GPIO55_MCU_OE_R { + GPIO55_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio55_slp_sel(&self) -> GPIO55_SLP_SEL_R { + GPIO55_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio55_mcu_wpd(&self) -> GPIO55_MCU_WPD_R { + GPIO55_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio55_mcu_wpu(&self) -> GPIO55_MCU_WPU_R { + GPIO55_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio55_mcu_ie(&self) -> GPIO55_MCU_IE_R { + GPIO55_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio55_mcu_drv(&self) -> GPIO55_MCU_DRV_R { + GPIO55_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio55_fun_wpd(&self) -> GPIO55_FUN_WPD_R { + GPIO55_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio55_fun_wpu(&self) -> GPIO55_FUN_WPU_R { + GPIO55_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio55_fun_ie(&self) -> GPIO55_FUN_IE_R { + GPIO55_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio55_fun_drv(&self) -> GPIO55_FUN_DRV_R { + GPIO55_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio55_mcu_sel(&self) -> GPIO55_MCU_SEL_R { + GPIO55_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio55_filter_en(&self) -> GPIO55_FILTER_EN_R { + GPIO55_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio55") + .field( + "gpio55_mcu_oe", + &format_args!("{}", self.gpio55_mcu_oe().bit()), + ) + .field( + "gpio55_slp_sel", + &format_args!("{}", self.gpio55_slp_sel().bit()), + ) + .field( + "gpio55_mcu_wpd", + &format_args!("{}", self.gpio55_mcu_wpd().bit()), + ) + .field( + "gpio55_mcu_wpu", + &format_args!("{}", self.gpio55_mcu_wpu().bit()), + ) + .field( + "gpio55_mcu_ie", + &format_args!("{}", self.gpio55_mcu_ie().bit()), + ) + .field( + "gpio55_mcu_drv", + &format_args!("{}", self.gpio55_mcu_drv().bits()), + ) + .field( + "gpio55_fun_wpd", + &format_args!("{}", self.gpio55_fun_wpd().bit()), + ) + .field( + "gpio55_fun_wpu", + &format_args!("{}", self.gpio55_fun_wpu().bit()), + ) + .field( + "gpio55_fun_ie", + &format_args!("{}", self.gpio55_fun_ie().bit()), + ) + .field( + "gpio55_fun_drv", + &format_args!("{}", self.gpio55_fun_drv().bits()), + ) + .field( + "gpio55_mcu_sel", + &format_args!("{}", self.gpio55_mcu_sel().bits()), + ) + .field( + "gpio55_filter_en", + &format_args!("{}", self.gpio55_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio55_mcu_oe(&mut self) -> GPIO55_MCU_OE_W { + GPIO55_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio55_slp_sel(&mut self) -> GPIO55_SLP_SEL_W { + GPIO55_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio55_mcu_wpd(&mut self) -> GPIO55_MCU_WPD_W { + GPIO55_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio55_mcu_wpu(&mut self) -> GPIO55_MCU_WPU_W { + GPIO55_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio55_mcu_ie(&mut self) -> GPIO55_MCU_IE_W { + GPIO55_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio55_mcu_drv(&mut self) -> GPIO55_MCU_DRV_W { + GPIO55_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio55_fun_wpd(&mut self) -> GPIO55_FUN_WPD_W { + GPIO55_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio55_fun_wpu(&mut self) -> GPIO55_FUN_WPU_W { + GPIO55_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio55_fun_ie(&mut self) -> GPIO55_FUN_IE_W { + GPIO55_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio55_fun_drv(&mut self) -> GPIO55_FUN_DRV_W { + GPIO55_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio55_mcu_sel(&mut self) -> GPIO55_MCU_SEL_W { + GPIO55_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio55_filter_en(&mut self) -> GPIO55_FILTER_EN_W { + GPIO55_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio55\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio55::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio55::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO55_SPEC; +impl crate::RegisterSpec for GPIO55_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio55::R`](R) reader structure"] +impl crate::Readable for GPIO55_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio55::W`](W) writer structure"] +impl crate::Writable for GPIO55_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio55 to value 0x0800"] +impl crate::Resettable for GPIO55_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio56.rs b/esp32p4/src/io_mux/gpio56.rs new file mode 100644 index 0000000000..42317bab97 --- /dev/null +++ b/esp32p4/src/io_mux/gpio56.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio56` reader"] +pub type R = crate::R; +#[doc = "Register `gpio56` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO56_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO56_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO56_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO56_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO56_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO56_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO56_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO56_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO56_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO56_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO56_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO56_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO56_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO56_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO56_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO56_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO56_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO56_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO56_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO56_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO56_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO56_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO56_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO56_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO56_FUN_WPD` reader - pull-down enable"] +pub type GPIO56_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO56_FUN_WPD` writer - pull-down enable"] +pub type GPIO56_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO56_FUN_WPU` reader - pull-up enable"] +pub type GPIO56_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO56_FUN_WPU` writer - pull-up enable"] +pub type GPIO56_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO56_FUN_IE` reader - input enable"] +pub type GPIO56_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO56_FUN_IE` writer - input enable"] +pub type GPIO56_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO56_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO56_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO56_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO56_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO56_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO56_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO56_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO56_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO56_FILTER_EN` reader - input filter enable"] +pub type GPIO56_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO56_FILTER_EN` writer - input filter enable"] +pub type GPIO56_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio56_mcu_oe(&self) -> GPIO56_MCU_OE_R { + GPIO56_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio56_slp_sel(&self) -> GPIO56_SLP_SEL_R { + GPIO56_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio56_mcu_wpd(&self) -> GPIO56_MCU_WPD_R { + GPIO56_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio56_mcu_wpu(&self) -> GPIO56_MCU_WPU_R { + GPIO56_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio56_mcu_ie(&self) -> GPIO56_MCU_IE_R { + GPIO56_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio56_mcu_drv(&self) -> GPIO56_MCU_DRV_R { + GPIO56_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio56_fun_wpd(&self) -> GPIO56_FUN_WPD_R { + GPIO56_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio56_fun_wpu(&self) -> GPIO56_FUN_WPU_R { + GPIO56_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio56_fun_ie(&self) -> GPIO56_FUN_IE_R { + GPIO56_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio56_fun_drv(&self) -> GPIO56_FUN_DRV_R { + GPIO56_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio56_mcu_sel(&self) -> GPIO56_MCU_SEL_R { + GPIO56_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio56_filter_en(&self) -> GPIO56_FILTER_EN_R { + GPIO56_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio56") + .field( + "gpio56_mcu_oe", + &format_args!("{}", self.gpio56_mcu_oe().bit()), + ) + .field( + "gpio56_slp_sel", + &format_args!("{}", self.gpio56_slp_sel().bit()), + ) + .field( + "gpio56_mcu_wpd", + &format_args!("{}", self.gpio56_mcu_wpd().bit()), + ) + .field( + "gpio56_mcu_wpu", + &format_args!("{}", self.gpio56_mcu_wpu().bit()), + ) + .field( + "gpio56_mcu_ie", + &format_args!("{}", self.gpio56_mcu_ie().bit()), + ) + .field( + "gpio56_mcu_drv", + &format_args!("{}", self.gpio56_mcu_drv().bits()), + ) + .field( + "gpio56_fun_wpd", + &format_args!("{}", self.gpio56_fun_wpd().bit()), + ) + .field( + "gpio56_fun_wpu", + &format_args!("{}", self.gpio56_fun_wpu().bit()), + ) + .field( + "gpio56_fun_ie", + &format_args!("{}", self.gpio56_fun_ie().bit()), + ) + .field( + "gpio56_fun_drv", + &format_args!("{}", self.gpio56_fun_drv().bits()), + ) + .field( + "gpio56_mcu_sel", + &format_args!("{}", self.gpio56_mcu_sel().bits()), + ) + .field( + "gpio56_filter_en", + &format_args!("{}", self.gpio56_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio56_mcu_oe(&mut self) -> GPIO56_MCU_OE_W { + GPIO56_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio56_slp_sel(&mut self) -> GPIO56_SLP_SEL_W { + GPIO56_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio56_mcu_wpd(&mut self) -> GPIO56_MCU_WPD_W { + GPIO56_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio56_mcu_wpu(&mut self) -> GPIO56_MCU_WPU_W { + GPIO56_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio56_mcu_ie(&mut self) -> GPIO56_MCU_IE_W { + GPIO56_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio56_mcu_drv(&mut self) -> GPIO56_MCU_DRV_W { + GPIO56_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio56_fun_wpd(&mut self) -> GPIO56_FUN_WPD_W { + GPIO56_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio56_fun_wpu(&mut self) -> GPIO56_FUN_WPU_W { + GPIO56_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio56_fun_ie(&mut self) -> GPIO56_FUN_IE_W { + GPIO56_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio56_fun_drv(&mut self) -> GPIO56_FUN_DRV_W { + GPIO56_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio56_mcu_sel(&mut self) -> GPIO56_MCU_SEL_W { + GPIO56_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio56_filter_en(&mut self) -> GPIO56_FILTER_EN_W { + GPIO56_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio56::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio56::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO56_SPEC; +impl crate::RegisterSpec for GPIO56_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio56::R`](R) reader structure"] +impl crate::Readable for GPIO56_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio56::W`](W) writer structure"] +impl crate::Writable for GPIO56_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio56 to value 0x0800"] +impl crate::Resettable for GPIO56_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio6.rs b/esp32p4/src/io_mux/gpio6.rs new file mode 100644 index 0000000000..deac9cdfcb --- /dev/null +++ b/esp32p4/src/io_mux/gpio6.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio6` reader"] +pub type R = crate::R; +#[doc = "Register `gpio6` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO6_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO6_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO6_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO6_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO6_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO6_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO6_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO6_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO6_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO6_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO6_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO6_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO6_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO6_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO6_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO6_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO6_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO6_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO6_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO6_FUN_WPD` reader - pull-down enable"] +pub type GPIO6_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO6_FUN_WPD` writer - pull-down enable"] +pub type GPIO6_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_FUN_WPU` reader - pull-up enable"] +pub type GPIO6_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO6_FUN_WPU` writer - pull-up enable"] +pub type GPIO6_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_FUN_IE` reader - input enable"] +pub type GPIO6_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO6_FUN_IE` writer - input enable"] +pub type GPIO6_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO6_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO6_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO6_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO6_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO6_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO6_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO6_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO6_FILTER_EN` reader - input filter enable"] +pub type GPIO6_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO6_FILTER_EN` writer - input filter enable"] +pub type GPIO6_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio6_mcu_oe(&self) -> GPIO6_MCU_OE_R { + GPIO6_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio6_slp_sel(&self) -> GPIO6_SLP_SEL_R { + GPIO6_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio6_mcu_wpd(&self) -> GPIO6_MCU_WPD_R { + GPIO6_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio6_mcu_wpu(&self) -> GPIO6_MCU_WPU_R { + GPIO6_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio6_mcu_ie(&self) -> GPIO6_MCU_IE_R { + GPIO6_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio6_mcu_drv(&self) -> GPIO6_MCU_DRV_R { + GPIO6_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio6_fun_wpd(&self) -> GPIO6_FUN_WPD_R { + GPIO6_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio6_fun_wpu(&self) -> GPIO6_FUN_WPU_R { + GPIO6_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio6_fun_ie(&self) -> GPIO6_FUN_IE_R { + GPIO6_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio6_fun_drv(&self) -> GPIO6_FUN_DRV_R { + GPIO6_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio6_mcu_sel(&self) -> GPIO6_MCU_SEL_R { + GPIO6_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio6_filter_en(&self) -> GPIO6_FILTER_EN_R { + GPIO6_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio6") + .field( + "gpio6_mcu_oe", + &format_args!("{}", self.gpio6_mcu_oe().bit()), + ) + .field( + "gpio6_slp_sel", + &format_args!("{}", self.gpio6_slp_sel().bit()), + ) + .field( + "gpio6_mcu_wpd", + &format_args!("{}", self.gpio6_mcu_wpd().bit()), + ) + .field( + "gpio6_mcu_wpu", + &format_args!("{}", self.gpio6_mcu_wpu().bit()), + ) + .field( + "gpio6_mcu_ie", + &format_args!("{}", self.gpio6_mcu_ie().bit()), + ) + .field( + "gpio6_mcu_drv", + &format_args!("{}", self.gpio6_mcu_drv().bits()), + ) + .field( + "gpio6_fun_wpd", + &format_args!("{}", self.gpio6_fun_wpd().bit()), + ) + .field( + "gpio6_fun_wpu", + &format_args!("{}", self.gpio6_fun_wpu().bit()), + ) + .field( + "gpio6_fun_ie", + &format_args!("{}", self.gpio6_fun_ie().bit()), + ) + .field( + "gpio6_fun_drv", + &format_args!("{}", self.gpio6_fun_drv().bits()), + ) + .field( + "gpio6_mcu_sel", + &format_args!("{}", self.gpio6_mcu_sel().bits()), + ) + .field( + "gpio6_filter_en", + &format_args!("{}", self.gpio6_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio6_mcu_oe(&mut self) -> GPIO6_MCU_OE_W { + GPIO6_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio6_slp_sel(&mut self) -> GPIO6_SLP_SEL_W { + GPIO6_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio6_mcu_wpd(&mut self) -> GPIO6_MCU_WPD_W { + GPIO6_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio6_mcu_wpu(&mut self) -> GPIO6_MCU_WPU_W { + GPIO6_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio6_mcu_ie(&mut self) -> GPIO6_MCU_IE_W { + GPIO6_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio6_mcu_drv(&mut self) -> GPIO6_MCU_DRV_W { + GPIO6_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio6_fun_wpd(&mut self) -> GPIO6_FUN_WPD_W { + GPIO6_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio6_fun_wpu(&mut self) -> GPIO6_FUN_WPU_W { + GPIO6_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio6_fun_ie(&mut self) -> GPIO6_FUN_IE_W { + GPIO6_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio6_fun_drv(&mut self) -> GPIO6_FUN_DRV_W { + GPIO6_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio6_mcu_sel(&mut self) -> GPIO6_MCU_SEL_W { + GPIO6_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio6_filter_en(&mut self) -> GPIO6_FILTER_EN_W { + GPIO6_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO6_SPEC; +impl crate::RegisterSpec for GPIO6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio6::R`](R) reader structure"] +impl crate::Readable for GPIO6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio6::W`](W) writer structure"] +impl crate::Writable for GPIO6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio6 to value 0x0800"] +impl crate::Resettable for GPIO6_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio7.rs b/esp32p4/src/io_mux/gpio7.rs new file mode 100644 index 0000000000..6b2e0e04ef --- /dev/null +++ b/esp32p4/src/io_mux/gpio7.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio7` reader"] +pub type R = crate::R; +#[doc = "Register `gpio7` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO7_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO7_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO7_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO7_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO7_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO7_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO7_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO7_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO7_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO7_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO7_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO7_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO7_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO7_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO7_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO7_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO7_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO7_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO7_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO7_FUN_WPD` reader - pull-down enable"] +pub type GPIO7_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO7_FUN_WPD` writer - pull-down enable"] +pub type GPIO7_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_FUN_WPU` reader - pull-up enable"] +pub type GPIO7_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO7_FUN_WPU` writer - pull-up enable"] +pub type GPIO7_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_FUN_IE` reader - input enable"] +pub type GPIO7_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO7_FUN_IE` writer - input enable"] +pub type GPIO7_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO7_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO7_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO7_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO7_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO7_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO7_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO7_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO7_FILTER_EN` reader - input filter enable"] +pub type GPIO7_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO7_FILTER_EN` writer - input filter enable"] +pub type GPIO7_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio7_mcu_oe(&self) -> GPIO7_MCU_OE_R { + GPIO7_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio7_slp_sel(&self) -> GPIO7_SLP_SEL_R { + GPIO7_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio7_mcu_wpd(&self) -> GPIO7_MCU_WPD_R { + GPIO7_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio7_mcu_wpu(&self) -> GPIO7_MCU_WPU_R { + GPIO7_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio7_mcu_ie(&self) -> GPIO7_MCU_IE_R { + GPIO7_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio7_mcu_drv(&self) -> GPIO7_MCU_DRV_R { + GPIO7_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio7_fun_wpd(&self) -> GPIO7_FUN_WPD_R { + GPIO7_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio7_fun_wpu(&self) -> GPIO7_FUN_WPU_R { + GPIO7_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio7_fun_ie(&self) -> GPIO7_FUN_IE_R { + GPIO7_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio7_fun_drv(&self) -> GPIO7_FUN_DRV_R { + GPIO7_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio7_mcu_sel(&self) -> GPIO7_MCU_SEL_R { + GPIO7_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio7_filter_en(&self) -> GPIO7_FILTER_EN_R { + GPIO7_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio7") + .field( + "gpio7_mcu_oe", + &format_args!("{}", self.gpio7_mcu_oe().bit()), + ) + .field( + "gpio7_slp_sel", + &format_args!("{}", self.gpio7_slp_sel().bit()), + ) + .field( + "gpio7_mcu_wpd", + &format_args!("{}", self.gpio7_mcu_wpd().bit()), + ) + .field( + "gpio7_mcu_wpu", + &format_args!("{}", self.gpio7_mcu_wpu().bit()), + ) + .field( + "gpio7_mcu_ie", + &format_args!("{}", self.gpio7_mcu_ie().bit()), + ) + .field( + "gpio7_mcu_drv", + &format_args!("{}", self.gpio7_mcu_drv().bits()), + ) + .field( + "gpio7_fun_wpd", + &format_args!("{}", self.gpio7_fun_wpd().bit()), + ) + .field( + "gpio7_fun_wpu", + &format_args!("{}", self.gpio7_fun_wpu().bit()), + ) + .field( + "gpio7_fun_ie", + &format_args!("{}", self.gpio7_fun_ie().bit()), + ) + .field( + "gpio7_fun_drv", + &format_args!("{}", self.gpio7_fun_drv().bits()), + ) + .field( + "gpio7_mcu_sel", + &format_args!("{}", self.gpio7_mcu_sel().bits()), + ) + .field( + "gpio7_filter_en", + &format_args!("{}", self.gpio7_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio7_mcu_oe(&mut self) -> GPIO7_MCU_OE_W { + GPIO7_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio7_slp_sel(&mut self) -> GPIO7_SLP_SEL_W { + GPIO7_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio7_mcu_wpd(&mut self) -> GPIO7_MCU_WPD_W { + GPIO7_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio7_mcu_wpu(&mut self) -> GPIO7_MCU_WPU_W { + GPIO7_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio7_mcu_ie(&mut self) -> GPIO7_MCU_IE_W { + GPIO7_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio7_mcu_drv(&mut self) -> GPIO7_MCU_DRV_W { + GPIO7_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio7_fun_wpd(&mut self) -> GPIO7_FUN_WPD_W { + GPIO7_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio7_fun_wpu(&mut self) -> GPIO7_FUN_WPU_W { + GPIO7_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio7_fun_ie(&mut self) -> GPIO7_FUN_IE_W { + GPIO7_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio7_fun_drv(&mut self) -> GPIO7_FUN_DRV_W { + GPIO7_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio7_mcu_sel(&mut self) -> GPIO7_MCU_SEL_W { + GPIO7_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio7_filter_en(&mut self) -> GPIO7_FILTER_EN_W { + GPIO7_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO7_SPEC; +impl crate::RegisterSpec for GPIO7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio7::R`](R) reader structure"] +impl crate::Readable for GPIO7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio7::W`](W) writer structure"] +impl crate::Writable for GPIO7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio7 to value 0x0800"] +impl crate::Resettable for GPIO7_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio8.rs b/esp32p4/src/io_mux/gpio8.rs new file mode 100644 index 0000000000..1c93f551be --- /dev/null +++ b/esp32p4/src/io_mux/gpio8.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio8` reader"] +pub type R = crate::R; +#[doc = "Register `gpio8` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO8_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO8_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO8_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO8_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO8_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO8_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO8_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO8_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO8_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO8_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO8_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO8_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO8_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO8_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO8_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO8_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO8_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO8_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO8_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO8_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO8_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO8_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO8_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO8_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO8_FUN_WPD` reader - pull-down enable"] +pub type GPIO8_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO8_FUN_WPD` writer - pull-down enable"] +pub type GPIO8_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO8_FUN_WPU` reader - pull-up enable"] +pub type GPIO8_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO8_FUN_WPU` writer - pull-up enable"] +pub type GPIO8_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO8_FUN_IE` reader - input enable"] +pub type GPIO8_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO8_FUN_IE` writer - input enable"] +pub type GPIO8_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO8_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO8_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO8_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO8_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO8_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO8_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO8_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO8_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO8_FILTER_EN` reader - input filter enable"] +pub type GPIO8_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO8_FILTER_EN` writer - input filter enable"] +pub type GPIO8_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio8_mcu_oe(&self) -> GPIO8_MCU_OE_R { + GPIO8_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio8_slp_sel(&self) -> GPIO8_SLP_SEL_R { + GPIO8_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio8_mcu_wpd(&self) -> GPIO8_MCU_WPD_R { + GPIO8_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio8_mcu_wpu(&self) -> GPIO8_MCU_WPU_R { + GPIO8_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio8_mcu_ie(&self) -> GPIO8_MCU_IE_R { + GPIO8_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio8_mcu_drv(&self) -> GPIO8_MCU_DRV_R { + GPIO8_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio8_fun_wpd(&self) -> GPIO8_FUN_WPD_R { + GPIO8_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio8_fun_wpu(&self) -> GPIO8_FUN_WPU_R { + GPIO8_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio8_fun_ie(&self) -> GPIO8_FUN_IE_R { + GPIO8_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio8_fun_drv(&self) -> GPIO8_FUN_DRV_R { + GPIO8_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio8_mcu_sel(&self) -> GPIO8_MCU_SEL_R { + GPIO8_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio8_filter_en(&self) -> GPIO8_FILTER_EN_R { + GPIO8_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio8") + .field( + "gpio8_mcu_oe", + &format_args!("{}", self.gpio8_mcu_oe().bit()), + ) + .field( + "gpio8_slp_sel", + &format_args!("{}", self.gpio8_slp_sel().bit()), + ) + .field( + "gpio8_mcu_wpd", + &format_args!("{}", self.gpio8_mcu_wpd().bit()), + ) + .field( + "gpio8_mcu_wpu", + &format_args!("{}", self.gpio8_mcu_wpu().bit()), + ) + .field( + "gpio8_mcu_ie", + &format_args!("{}", self.gpio8_mcu_ie().bit()), + ) + .field( + "gpio8_mcu_drv", + &format_args!("{}", self.gpio8_mcu_drv().bits()), + ) + .field( + "gpio8_fun_wpd", + &format_args!("{}", self.gpio8_fun_wpd().bit()), + ) + .field( + "gpio8_fun_wpu", + &format_args!("{}", self.gpio8_fun_wpu().bit()), + ) + .field( + "gpio8_fun_ie", + &format_args!("{}", self.gpio8_fun_ie().bit()), + ) + .field( + "gpio8_fun_drv", + &format_args!("{}", self.gpio8_fun_drv().bits()), + ) + .field( + "gpio8_mcu_sel", + &format_args!("{}", self.gpio8_mcu_sel().bits()), + ) + .field( + "gpio8_filter_en", + &format_args!("{}", self.gpio8_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio8_mcu_oe(&mut self) -> GPIO8_MCU_OE_W { + GPIO8_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio8_slp_sel(&mut self) -> GPIO8_SLP_SEL_W { + GPIO8_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio8_mcu_wpd(&mut self) -> GPIO8_MCU_WPD_W { + GPIO8_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio8_mcu_wpu(&mut self) -> GPIO8_MCU_WPU_W { + GPIO8_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio8_mcu_ie(&mut self) -> GPIO8_MCU_IE_W { + GPIO8_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio8_mcu_drv(&mut self) -> GPIO8_MCU_DRV_W { + GPIO8_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio8_fun_wpd(&mut self) -> GPIO8_FUN_WPD_W { + GPIO8_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio8_fun_wpu(&mut self) -> GPIO8_FUN_WPU_W { + GPIO8_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio8_fun_ie(&mut self) -> GPIO8_FUN_IE_W { + GPIO8_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio8_fun_drv(&mut self) -> GPIO8_FUN_DRV_W { + GPIO8_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio8_mcu_sel(&mut self) -> GPIO8_MCU_SEL_W { + GPIO8_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio8_filter_en(&mut self) -> GPIO8_FILTER_EN_W { + GPIO8_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO8_SPEC; +impl crate::RegisterSpec for GPIO8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio8::R`](R) reader structure"] +impl crate::Readable for GPIO8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio8::W`](W) writer structure"] +impl crate::Writable for GPIO8_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio8 to value 0x0800"] +impl crate::Resettable for GPIO8_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/io_mux/gpio9.rs b/esp32p4/src/io_mux/gpio9.rs new file mode 100644 index 0000000000..dcc4371401 --- /dev/null +++ b/esp32p4/src/io_mux/gpio9.rs @@ -0,0 +1,275 @@ +#[doc = "Register `gpio9` reader"] +pub type R = crate::R; +#[doc = "Register `gpio9` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO9_MCU_OE` reader - output enable on sleep mode"] +pub type GPIO9_MCU_OE_R = crate::BitReader; +#[doc = "Field `GPIO9_MCU_OE` writer - output enable on sleep mode"] +pub type GPIO9_MCU_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO9_SLP_SEL` reader - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO9_SLP_SEL_R = crate::BitReader; +#[doc = "Field `GPIO9_SLP_SEL` writer - io sleep mode enable. set 1 to enable sleep mode."] +pub type GPIO9_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO9_MCU_WPD` reader - pull-down enable on sleep mode"] +pub type GPIO9_MCU_WPD_R = crate::BitReader; +#[doc = "Field `GPIO9_MCU_WPD` writer - pull-down enable on sleep mode"] +pub type GPIO9_MCU_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO9_MCU_WPU` reader - pull-up enable on sleep mode"] +pub type GPIO9_MCU_WPU_R = crate::BitReader; +#[doc = "Field `GPIO9_MCU_WPU` writer - pull-up enable on sleep mode"] +pub type GPIO9_MCU_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO9_MCU_IE` reader - input enable on sleep mode"] +pub type GPIO9_MCU_IE_R = crate::BitReader; +#[doc = "Field `GPIO9_MCU_IE` writer - input enable on sleep mode"] +pub type GPIO9_MCU_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO9_MCU_DRV` reader - select drive strenth on sleep mode"] +pub type GPIO9_MCU_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO9_MCU_DRV` writer - select drive strenth on sleep mode"] +pub type GPIO9_MCU_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO9_FUN_WPD` reader - pull-down enable"] +pub type GPIO9_FUN_WPD_R = crate::BitReader; +#[doc = "Field `GPIO9_FUN_WPD` writer - pull-down enable"] +pub type GPIO9_FUN_WPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO9_FUN_WPU` reader - pull-up enable"] +pub type GPIO9_FUN_WPU_R = crate::BitReader; +#[doc = "Field `GPIO9_FUN_WPU` writer - pull-up enable"] +pub type GPIO9_FUN_WPU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO9_FUN_IE` reader - input enable"] +pub type GPIO9_FUN_IE_R = crate::BitReader; +#[doc = "Field `GPIO9_FUN_IE` writer - input enable"] +pub type GPIO9_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO9_FUN_DRV` reader - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO9_FUN_DRV_R = crate::FieldReader; +#[doc = "Field `GPIO9_FUN_DRV` writer - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] +pub type GPIO9_FUN_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GPIO9_MCU_SEL` reader - 0:select function0, 1:select function1 ..."] +pub type GPIO9_MCU_SEL_R = crate::FieldReader; +#[doc = "Field `GPIO9_MCU_SEL` writer - 0:select function0, 1:select function1 ..."] +pub type GPIO9_MCU_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GPIO9_FILTER_EN` reader - input filter enable"] +pub type GPIO9_FILTER_EN_R = crate::BitReader; +#[doc = "Field `GPIO9_FILTER_EN` writer - input filter enable"] +pub type GPIO9_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + pub fn gpio9_mcu_oe(&self) -> GPIO9_MCU_OE_R { + GPIO9_MCU_OE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + pub fn gpio9_slp_sel(&self) -> GPIO9_SLP_SEL_R { + GPIO9_SLP_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + pub fn gpio9_mcu_wpd(&self) -> GPIO9_MCU_WPD_R { + GPIO9_MCU_WPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + pub fn gpio9_mcu_wpu(&self) -> GPIO9_MCU_WPU_R { + GPIO9_MCU_WPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + pub fn gpio9_mcu_ie(&self) -> GPIO9_MCU_IE_R { + GPIO9_MCU_IE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + pub fn gpio9_mcu_drv(&self) -> GPIO9_MCU_DRV_R { + GPIO9_MCU_DRV_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + pub fn gpio9_fun_wpd(&self) -> GPIO9_FUN_WPD_R { + GPIO9_FUN_WPD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + pub fn gpio9_fun_wpu(&self) -> GPIO9_FUN_WPU_R { + GPIO9_FUN_WPU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + pub fn gpio9_fun_ie(&self) -> GPIO9_FUN_IE_R { + GPIO9_FUN_IE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + pub fn gpio9_fun_drv(&self) -> GPIO9_FUN_DRV_R { + GPIO9_FUN_DRV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + pub fn gpio9_mcu_sel(&self) -> GPIO9_MCU_SEL_R { + GPIO9_MCU_SEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + pub fn gpio9_filter_en(&self) -> GPIO9_FILTER_EN_R { + GPIO9_FILTER_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("gpio9") + .field( + "gpio9_mcu_oe", + &format_args!("{}", self.gpio9_mcu_oe().bit()), + ) + .field( + "gpio9_slp_sel", + &format_args!("{}", self.gpio9_slp_sel().bit()), + ) + .field( + "gpio9_mcu_wpd", + &format_args!("{}", self.gpio9_mcu_wpd().bit()), + ) + .field( + "gpio9_mcu_wpu", + &format_args!("{}", self.gpio9_mcu_wpu().bit()), + ) + .field( + "gpio9_mcu_ie", + &format_args!("{}", self.gpio9_mcu_ie().bit()), + ) + .field( + "gpio9_mcu_drv", + &format_args!("{}", self.gpio9_mcu_drv().bits()), + ) + .field( + "gpio9_fun_wpd", + &format_args!("{}", self.gpio9_fun_wpd().bit()), + ) + .field( + "gpio9_fun_wpu", + &format_args!("{}", self.gpio9_fun_wpu().bit()), + ) + .field( + "gpio9_fun_ie", + &format_args!("{}", self.gpio9_fun_ie().bit()), + ) + .field( + "gpio9_fun_drv", + &format_args!("{}", self.gpio9_fun_drv().bits()), + ) + .field( + "gpio9_mcu_sel", + &format_args!("{}", self.gpio9_mcu_sel().bits()), + ) + .field( + "gpio9_filter_en", + &format_args!("{}", self.gpio9_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - output enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio9_mcu_oe(&mut self) -> GPIO9_MCU_OE_W { + GPIO9_MCU_OE_W::new(self, 0) + } + #[doc = "Bit 1 - io sleep mode enable. set 1 to enable sleep mode."] + #[inline(always)] + #[must_use] + pub fn gpio9_slp_sel(&mut self) -> GPIO9_SLP_SEL_W { + GPIO9_SLP_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - pull-down enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio9_mcu_wpd(&mut self) -> GPIO9_MCU_WPD_W { + GPIO9_MCU_WPD_W::new(self, 2) + } + #[doc = "Bit 3 - pull-up enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio9_mcu_wpu(&mut self) -> GPIO9_MCU_WPU_W { + GPIO9_MCU_WPU_W::new(self, 3) + } + #[doc = "Bit 4 - input enable on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio9_mcu_ie(&mut self) -> GPIO9_MCU_IE_W { + GPIO9_MCU_IE_W::new(self, 4) + } + #[doc = "Bits 5:6 - select drive strenth on sleep mode"] + #[inline(always)] + #[must_use] + pub fn gpio9_mcu_drv(&mut self) -> GPIO9_MCU_DRV_W { + GPIO9_MCU_DRV_W::new(self, 5) + } + #[doc = "Bit 7 - pull-down enable"] + #[inline(always)] + #[must_use] + pub fn gpio9_fun_wpd(&mut self) -> GPIO9_FUN_WPD_W { + GPIO9_FUN_WPD_W::new(self, 7) + } + #[doc = "Bit 8 - pull-up enable"] + #[inline(always)] + #[must_use] + pub fn gpio9_fun_wpu(&mut self) -> GPIO9_FUN_WPU_W { + GPIO9_FUN_WPU_W::new(self, 8) + } + #[doc = "Bit 9 - input enable"] + #[inline(always)] + #[must_use] + pub fn gpio9_fun_ie(&mut self) -> GPIO9_FUN_IE_W { + GPIO9_FUN_IE_W::new(self, 9) + } + #[doc = "Bits 10:11 - select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA"] + #[inline(always)] + #[must_use] + pub fn gpio9_fun_drv(&mut self) -> GPIO9_FUN_DRV_W { + GPIO9_FUN_DRV_W::new(self, 10) + } + #[doc = "Bits 12:14 - 0:select function0, 1:select function1 ..."] + #[inline(always)] + #[must_use] + pub fn gpio9_mcu_sel(&mut self) -> GPIO9_MCU_SEL_W { + GPIO9_MCU_SEL_W::new(self, 12) + } + #[doc = "Bit 15 - input filter enable"] + #[inline(always)] + #[must_use] + pub fn gpio9_filter_en(&mut self) -> GPIO9_FILTER_EN_W { + GPIO9_FILTER_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "iomux control register for gpio9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpio9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO9_SPEC; +impl crate::RegisterSpec for GPIO9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio9::R`](R) reader structure"] +impl crate::Readable for GPIO9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio9::W`](W) writer structure"] +impl crate::Writable for GPIO9_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets gpio9 to value 0x0800"] +impl crate::Resettable for GPIO9_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/isp.rs b/esp32p4/src/isp.rs new file mode 100644 index 0000000000..aab3f735bc --- /dev/null +++ b/esp32p4/src/isp.rs @@ -0,0 +1,1457 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + ver_date: VER_DATE, + clk_en: CLK_EN, + cntl: CNTL, + hsync_cnt: HSYNC_CNT, + frame_cfg: FRAME_CFG, + ccm_coef0: CCM_COEF0, + ccm_coef1: CCM_COEF1, + ccm_coef3: CCM_COEF3, + ccm_coef4: CCM_COEF4, + ccm_coef5: CCM_COEF5, + bf_matrix_ctrl: BF_MATRIX_CTRL, + bf_sigma: BF_SIGMA, + bf_gau0: BF_GAU0, + bf_gau1: BF_GAU1, + dpc_ctrl: DPC_CTRL, + dpc_conf: DPC_CONF, + dpc_matrix_ctrl: DPC_MATRIX_CTRL, + dpc_deadpix_cnt: DPC_DEADPIX_CNT, + lut_cmd: LUT_CMD, + lut_wdata: LUT_WDATA, + lut_rdata: LUT_RDATA, + lsc_tablesize: LSC_TABLESIZE, + demosaic_matrix_ctrl: DEMOSAIC_MATRIX_CTRL, + demosaic_grad_ratio: DEMOSAIC_GRAD_RATIO, + median_matrix_ctrl: MEDIAN_MATRIX_CTRL, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + gamma_ctrl: GAMMA_CTRL, + gamma_ry1: GAMMA_RY1, + gamma_ry2: GAMMA_RY2, + gamma_ry3: GAMMA_RY3, + gamma_ry4: GAMMA_RY4, + gamma_gy1: GAMMA_GY1, + gamma_gy2: GAMMA_GY2, + gamma_gy3: GAMMA_GY3, + gamma_gy4: GAMMA_GY4, + gamma_by1: GAMMA_BY1, + gamma_by2: GAMMA_BY2, + gamma_by3: GAMMA_BY3, + gamma_by4: GAMMA_BY4, + gamma_rx1: GAMMA_RX1, + gamma_rx2: GAMMA_RX2, + gamma_gx1: GAMMA_GX1, + gamma_gx2: GAMMA_GX2, + gamma_bx1: GAMMA_BX1, + gamma_bx2: GAMMA_BX2, + ae_ctrl: AE_CTRL, + ae_monitor: AE_MONITOR, + ae_bx: AE_BX, + ae_by: AE_BY, + ae_winpixnum: AE_WINPIXNUM, + ae_win_reciprocal: AE_WIN_RECIPROCAL, + ae_block_mean_0: AE_BLOCK_MEAN_0, + ae_block_mean_1: AE_BLOCK_MEAN_1, + ae_block_mean_2: AE_BLOCK_MEAN_2, + ae_block_mean_3: AE_BLOCK_MEAN_3, + ae_block_mean_4: AE_BLOCK_MEAN_4, + ae_block_mean_5: AE_BLOCK_MEAN_5, + ae_block_mean_6: AE_BLOCK_MEAN_6, + sharp_ctrl0: SHARP_CTRL0, + sharp_filter0: SHARP_FILTER0, + sharp_filter1: SHARP_FILTER1, + sharp_filter2: SHARP_FILTER2, + sharp_matrix_ctrl: SHARP_MATRIX_CTRL, + sharp_ctrl1: SHARP_CTRL1, + dma_cntl: DMA_CNTL, + dma_raw_data: DMA_RAW_DATA, + cam_cntl: CAM_CNTL, + cam_conf: CAM_CONF, + af_ctrl0: AF_CTRL0, + af_ctrl1: AF_CTRL1, + af_gen_th_ctrl: AF_GEN_TH_CTRL, + af_env_user_th_sum: AF_ENV_USER_TH_SUM, + af_env_user_th_lum: AF_ENV_USER_TH_LUM, + af_threshold: AF_THRESHOLD, + af_hscale_a: AF_HSCALE_A, + af_vscale_a: AF_VSCALE_A, + af_hscale_b: AF_HSCALE_B, + af_vscale_b: AF_VSCALE_B, + af_hscale_c: AF_HSCALE_C, + af_vscale_c: AF_VSCALE_C, + af_sum_a: AF_SUM_A, + af_sum_b: AF_SUM_B, + af_sum_c: AF_SUM_C, + af_lum_a: AF_LUM_A, + af_lum_b: AF_LUM_B, + af_lum_c: AF_LUM_C, + awb_mode: AWB_MODE, + awb_hscale: AWB_HSCALE, + awb_vscale: AWB_VSCALE, + awb_th_lum: AWB_TH_LUM, + awb_th_rg: AWB_TH_RG, + awb_th_bg: AWB_TH_BG, + awb0_white_cnt: AWB0_WHITE_CNT, + awb0_acc_r: AWB0_ACC_R, + awb0_acc_g: AWB0_ACC_G, + awb0_acc_b: AWB0_ACC_B, + color_ctrl: COLOR_CTRL, + blc_value: BLC_VALUE, + blc_ctrl0: BLC_CTRL0, + blc_ctrl1: BLC_CTRL1, + blc_ctrl2: BLC_CTRL2, + blc_mean: BLC_MEAN, + hist_mode: HIST_MODE, + hist_coeff: HIST_COEFF, + hist_offs: HIST_OFFS, + hist_size: HIST_SIZE, + hist_seg0: HIST_SEG0, + hist_seg1: HIST_SEG1, + hist_seg2: HIST_SEG2, + hist_seg3: HIST_SEG3, + hist_weight0: HIST_WEIGHT0, + hist_weight1: HIST_WEIGHT1, + hist_weight2: HIST_WEIGHT2, + hist_weight3: HIST_WEIGHT3, + hist_weight4: HIST_WEIGHT4, + hist_weight5: HIST_WEIGHT5, + hist_weight6: HIST_WEIGHT6, + hist_bin0: HIST_BIN0, + hist_bin1: HIST_BIN1, + hist_bin2: HIST_BIN2, + hist_bin3: HIST_BIN3, + hist_bin4: HIST_BIN4, + hist_bin5: HIST_BIN5, + hist_bin6: HIST_BIN6, + hist_bin7: HIST_BIN7, + hist_bin8: HIST_BIN8, + hist_bin9: HIST_BIN9, + hist_bin10: HIST_BIN10, + hist_bin11: HIST_BIN11, + hist_bin12: HIST_BIN12, + hist_bin13: HIST_BIN13, + hist_bin14: HIST_BIN14, + hist_bin15: HIST_BIN15, + mem_aux_ctrl_0: MEM_AUX_CTRL_0, + mem_aux_ctrl_1: MEM_AUX_CTRL_1, + mem_aux_ctrl_2: MEM_AUX_CTRL_2, + mem_aux_ctrl_3: MEM_AUX_CTRL_3, + mem_aux_ctrl_4: MEM_AUX_CTRL_4, + yuv_format: YUV_FORMAT, + rdn_eco_cs: RDN_ECO_CS, + rdn_eco_low: RDN_ECO_LOW, + rdn_eco_high: RDN_ECO_HIGH, +} +impl RegisterBlock { + #[doc = "0x00 - version control register"] + #[inline(always)] + pub const fn ver_date(&self) -> &VER_DATE { + &self.ver_date + } + #[doc = "0x04 - isp clk control register"] + #[inline(always)] + pub const fn clk_en(&self) -> &CLK_EN { + &self.clk_en + } + #[doc = "0x08 - isp module enable control register"] + #[inline(always)] + pub const fn cntl(&self) -> &CNTL { + &self.cntl + } + #[doc = "0x0c - header hsync interval control register"] + #[inline(always)] + pub const fn hsync_cnt(&self) -> &HSYNC_CNT { + &self.hsync_cnt + } + #[doc = "0x10 - frame control parameter register"] + #[inline(always)] + pub const fn frame_cfg(&self) -> &FRAME_CFG { + &self.frame_cfg + } + #[doc = "0x14 - ccm coef register 0"] + #[inline(always)] + pub const fn ccm_coef0(&self) -> &CCM_COEF0 { + &self.ccm_coef0 + } + #[doc = "0x18 - ccm coef register 1"] + #[inline(always)] + pub const fn ccm_coef1(&self) -> &CCM_COEF1 { + &self.ccm_coef1 + } + #[doc = "0x1c - ccm coef register 3"] + #[inline(always)] + pub const fn ccm_coef3(&self) -> &CCM_COEF3 { + &self.ccm_coef3 + } + #[doc = "0x20 - ccm coef register 4"] + #[inline(always)] + pub const fn ccm_coef4(&self) -> &CCM_COEF4 { + &self.ccm_coef4 + } + #[doc = "0x24 - ccm coef register 5"] + #[inline(always)] + pub const fn ccm_coef5(&self) -> &CCM_COEF5 { + &self.ccm_coef5 + } + #[doc = "0x28 - bf pix2matrix ctrl"] + #[inline(always)] + pub const fn bf_matrix_ctrl(&self) -> &BF_MATRIX_CTRL { + &self.bf_matrix_ctrl + } + #[doc = "0x2c - bf denoising level control register"] + #[inline(always)] + pub const fn bf_sigma(&self) -> &BF_SIGMA { + &self.bf_sigma + } + #[doc = "0x30 - bf gau template register 0"] + #[inline(always)] + pub const fn bf_gau0(&self) -> &BF_GAU0 { + &self.bf_gau0 + } + #[doc = "0x34 - bf gau template register 1"] + #[inline(always)] + pub const fn bf_gau1(&self) -> &BF_GAU1 { + &self.bf_gau1 + } + #[doc = "0x38 - DPC mode control register"] + #[inline(always)] + pub const fn dpc_ctrl(&self) -> &DPC_CTRL { + &self.dpc_ctrl + } + #[doc = "0x3c - DPC parameter config register"] + #[inline(always)] + pub const fn dpc_conf(&self) -> &DPC_CONF { + &self.dpc_conf + } + #[doc = "0x40 - dpc pix2matrix ctrl"] + #[inline(always)] + pub const fn dpc_matrix_ctrl(&self) -> &DPC_MATRIX_CTRL { + &self.dpc_matrix_ctrl + } + #[doc = "0x44 - DPC dead-pix number register"] + #[inline(always)] + pub const fn dpc_deadpix_cnt(&self) -> &DPC_DEADPIX_CNT { + &self.dpc_deadpix_cnt + } + #[doc = "0x48 - LUT command register"] + #[inline(always)] + pub const fn lut_cmd(&self) -> &LUT_CMD { + &self.lut_cmd + } + #[doc = "0x4c - LUT write data register"] + #[inline(always)] + pub const fn lut_wdata(&self) -> &LUT_WDATA { + &self.lut_wdata + } + #[doc = "0x50 - LUT read data register"] + #[inline(always)] + pub const fn lut_rdata(&self) -> &LUT_RDATA { + &self.lut_rdata + } + #[doc = "0x54 - LSC point in x-direction"] + #[inline(always)] + pub const fn lsc_tablesize(&self) -> &LSC_TABLESIZE { + &self.lsc_tablesize + } + #[doc = "0x58 - demosaic pix2matrix ctrl"] + #[inline(always)] + pub const fn demosaic_matrix_ctrl(&self) -> &DEMOSAIC_MATRIX_CTRL { + &self.demosaic_matrix_ctrl + } + #[doc = "0x5c - demosaic gradient select ratio"] + #[inline(always)] + pub const fn demosaic_grad_ratio(&self) -> &DEMOSAIC_GRAD_RATIO { + &self.demosaic_grad_ratio + } + #[doc = "0x60 - median pix2matrix ctrl"] + #[inline(always)] + pub const fn median_matrix_ctrl(&self) -> &MEDIAN_MATRIX_CTRL { + &self.median_matrix_ctrl + } + #[doc = "0x64 - raw interrupt register"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x68 - masked interrupt register"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x6c - interrupt enable register"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x70 - interrupt clear register"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x74 - gamma control register"] + #[inline(always)] + pub const fn gamma_ctrl(&self) -> &GAMMA_CTRL { + &self.gamma_ctrl + } + #[doc = "0x78 - point of Y-axis of r channel gamma curve register 1"] + #[inline(always)] + pub const fn gamma_ry1(&self) -> &GAMMA_RY1 { + &self.gamma_ry1 + } + #[doc = "0x7c - point of Y-axis of r channel gamma curve register 2"] + #[inline(always)] + pub const fn gamma_ry2(&self) -> &GAMMA_RY2 { + &self.gamma_ry2 + } + #[doc = "0x80 - point of Y-axis of r channel gamma curve register 3"] + #[inline(always)] + pub const fn gamma_ry3(&self) -> &GAMMA_RY3 { + &self.gamma_ry3 + } + #[doc = "0x84 - point of Y-axis of r channel gamma curve register 4"] + #[inline(always)] + pub const fn gamma_ry4(&self) -> &GAMMA_RY4 { + &self.gamma_ry4 + } + #[doc = "0x88 - point of Y-axis of g channel gamma curve register 1"] + #[inline(always)] + pub const fn gamma_gy1(&self) -> &GAMMA_GY1 { + &self.gamma_gy1 + } + #[doc = "0x8c - point of Y-axis of g channel gamma curve register 2"] + #[inline(always)] + pub const fn gamma_gy2(&self) -> &GAMMA_GY2 { + &self.gamma_gy2 + } + #[doc = "0x90 - point of Y-axis of g channel gamma curve register 3"] + #[inline(always)] + pub const fn gamma_gy3(&self) -> &GAMMA_GY3 { + &self.gamma_gy3 + } + #[doc = "0x94 - point of Y-axis of g channel gamma curve register 4"] + #[inline(always)] + pub const fn gamma_gy4(&self) -> &GAMMA_GY4 { + &self.gamma_gy4 + } + #[doc = "0x98 - point of Y-axis of b channel gamma curve register 1"] + #[inline(always)] + pub const fn gamma_by1(&self) -> &GAMMA_BY1 { + &self.gamma_by1 + } + #[doc = "0x9c - point of Y-axis of b channel gamma curve register 2"] + #[inline(always)] + pub const fn gamma_by2(&self) -> &GAMMA_BY2 { + &self.gamma_by2 + } + #[doc = "0xa0 - point of Y-axis of b channel gamma curve register 3"] + #[inline(always)] + pub const fn gamma_by3(&self) -> &GAMMA_BY3 { + &self.gamma_by3 + } + #[doc = "0xa4 - point of Y-axis of b channel gamma curve register 4"] + #[inline(always)] + pub const fn gamma_by4(&self) -> &GAMMA_BY4 { + &self.gamma_by4 + } + #[doc = "0xa8 - point of X-axis of r channel gamma curve register 1"] + #[inline(always)] + pub const fn gamma_rx1(&self) -> &GAMMA_RX1 { + &self.gamma_rx1 + } + #[doc = "0xac - point of X-axis of r channel gamma curve register 2"] + #[inline(always)] + pub const fn gamma_rx2(&self) -> &GAMMA_RX2 { + &self.gamma_rx2 + } + #[doc = "0xb0 - point of X-axis of g channel gamma curve register 1"] + #[inline(always)] + pub const fn gamma_gx1(&self) -> &GAMMA_GX1 { + &self.gamma_gx1 + } + #[doc = "0xb4 - point of X-axis of g channel gamma curve register 2"] + #[inline(always)] + pub const fn gamma_gx2(&self) -> &GAMMA_GX2 { + &self.gamma_gx2 + } + #[doc = "0xb8 - point of X-axis of b channel gamma curve register 1"] + #[inline(always)] + pub const fn gamma_bx1(&self) -> &GAMMA_BX1 { + &self.gamma_bx1 + } + #[doc = "0xbc - point of X-axis of b channel gamma curve register 2"] + #[inline(always)] + pub const fn gamma_bx2(&self) -> &GAMMA_BX2 { + &self.gamma_bx2 + } + #[doc = "0xc0 - ae control register"] + #[inline(always)] + pub const fn ae_ctrl(&self) -> &AE_CTRL { + &self.ae_ctrl + } + #[doc = "0xc4 - ae monitor control register"] + #[inline(always)] + pub const fn ae_monitor(&self) -> &AE_MONITOR { + &self.ae_monitor + } + #[doc = "0xc8 - ae window register in x-direction"] + #[inline(always)] + pub const fn ae_bx(&self) -> &AE_BX { + &self.ae_bx + } + #[doc = "0xcc - ae window register in y-direction"] + #[inline(always)] + pub const fn ae_by(&self) -> &AE_BY { + &self.ae_by + } + #[doc = "0xd0 - ae sub-window pix num register"] + #[inline(always)] + pub const fn ae_winpixnum(&self) -> &AE_WINPIXNUM { + &self.ae_winpixnum + } + #[doc = "0xd4 - reciprocal of ae sub-window pixel number"] + #[inline(always)] + pub const fn ae_win_reciprocal(&self) -> &AE_WIN_RECIPROCAL { + &self.ae_win_reciprocal + } + #[doc = "0xd8 - ae statistic result register 0"] + #[inline(always)] + pub const fn ae_block_mean_0(&self) -> &AE_BLOCK_MEAN_0 { + &self.ae_block_mean_0 + } + #[doc = "0xdc - ae statistic result register 1"] + #[inline(always)] + pub const fn ae_block_mean_1(&self) -> &AE_BLOCK_MEAN_1 { + &self.ae_block_mean_1 + } + #[doc = "0xe0 - ae statistic result register 2"] + #[inline(always)] + pub const fn ae_block_mean_2(&self) -> &AE_BLOCK_MEAN_2 { + &self.ae_block_mean_2 + } + #[doc = "0xe4 - ae statistic result register 3"] + #[inline(always)] + pub const fn ae_block_mean_3(&self) -> &AE_BLOCK_MEAN_3 { + &self.ae_block_mean_3 + } + #[doc = "0xe8 - ae statistic result register 4"] + #[inline(always)] + pub const fn ae_block_mean_4(&self) -> &AE_BLOCK_MEAN_4 { + &self.ae_block_mean_4 + } + #[doc = "0xec - ae statistic result register 5"] + #[inline(always)] + pub const fn ae_block_mean_5(&self) -> &AE_BLOCK_MEAN_5 { + &self.ae_block_mean_5 + } + #[doc = "0xf0 - ae statistic result register 6"] + #[inline(always)] + pub const fn ae_block_mean_6(&self) -> &AE_BLOCK_MEAN_6 { + &self.ae_block_mean_6 + } + #[doc = "0xf4 - sharp control register 0"] + #[inline(always)] + pub const fn sharp_ctrl0(&self) -> &SHARP_CTRL0 { + &self.sharp_ctrl0 + } + #[doc = "0xf8 - sharp usm config register 0"] + #[inline(always)] + pub const fn sharp_filter0(&self) -> &SHARP_FILTER0 { + &self.sharp_filter0 + } + #[doc = "0xfc - sharp usm config register 1"] + #[inline(always)] + pub const fn sharp_filter1(&self) -> &SHARP_FILTER1 { + &self.sharp_filter1 + } + #[doc = "0x100 - sharp usm config register 2"] + #[inline(always)] + pub const fn sharp_filter2(&self) -> &SHARP_FILTER2 { + &self.sharp_filter2 + } + #[doc = "0x104 - sharp pix2matrix ctrl"] + #[inline(always)] + pub const fn sharp_matrix_ctrl(&self) -> &SHARP_MATRIX_CTRL { + &self.sharp_matrix_ctrl + } + #[doc = "0x108 - sharp control register 1"] + #[inline(always)] + pub const fn sharp_ctrl1(&self) -> &SHARP_CTRL1 { + &self.sharp_ctrl1 + } + #[doc = "0x10c - isp dma source trans control register"] + #[inline(always)] + pub const fn dma_cntl(&self) -> &DMA_CNTL { + &self.dma_cntl + } + #[doc = "0x110 - isp dma source total raw number set register"] + #[inline(always)] + pub const fn dma_raw_data(&self) -> &DMA_RAW_DATA { + &self.dma_raw_data + } + #[doc = "0x114 - isp cam source control register"] + #[inline(always)] + pub const fn cam_cntl(&self) -> &CAM_CNTL { + &self.cam_cntl + } + #[doc = "0x118 - isp cam source config register"] + #[inline(always)] + pub const fn cam_conf(&self) -> &CAM_CONF { + &self.cam_conf + } + #[doc = "0x11c - af control register 0"] + #[inline(always)] + pub const fn af_ctrl0(&self) -> &AF_CTRL0 { + &self.af_ctrl0 + } + #[doc = "0x120 - af control register 1"] + #[inline(always)] + pub const fn af_ctrl1(&self) -> &AF_CTRL1 { + &self.af_ctrl1 + } + #[doc = "0x124 - af gen threshold control register"] + #[inline(always)] + pub const fn af_gen_th_ctrl(&self) -> &AF_GEN_TH_CTRL { + &self.af_gen_th_ctrl + } + #[doc = "0x128 - af monitor user sum threshold register"] + #[inline(always)] + pub const fn af_env_user_th_sum(&self) -> &AF_ENV_USER_TH_SUM { + &self.af_env_user_th_sum + } + #[doc = "0x12c - af monitor user lum threshold register"] + #[inline(always)] + pub const fn af_env_user_th_lum(&self) -> &AF_ENV_USER_TH_LUM { + &self.af_env_user_th_lum + } + #[doc = "0x130 - af threshold register"] + #[inline(always)] + pub const fn af_threshold(&self) -> &AF_THRESHOLD { + &self.af_threshold + } + #[doc = "0x134 - h-scale of af window a register"] + #[inline(always)] + pub const fn af_hscale_a(&self) -> &AF_HSCALE_A { + &self.af_hscale_a + } + #[doc = "0x138 - v-scale of af window a register"] + #[inline(always)] + pub const fn af_vscale_a(&self) -> &AF_VSCALE_A { + &self.af_vscale_a + } + #[doc = "0x13c - h-scale of af window b register"] + #[inline(always)] + pub const fn af_hscale_b(&self) -> &AF_HSCALE_B { + &self.af_hscale_b + } + #[doc = "0x140 - v-scale of af window b register"] + #[inline(always)] + pub const fn af_vscale_b(&self) -> &AF_VSCALE_B { + &self.af_vscale_b + } + #[doc = "0x144 - v-scale of af window c register"] + #[inline(always)] + pub const fn af_hscale_c(&self) -> &AF_HSCALE_C { + &self.af_hscale_c + } + #[doc = "0x148 - v-scale of af window c register"] + #[inline(always)] + pub const fn af_vscale_c(&self) -> &AF_VSCALE_C { + &self.af_vscale_c + } + #[doc = "0x14c - result of sum of af window a"] + #[inline(always)] + pub const fn af_sum_a(&self) -> &AF_SUM_A { + &self.af_sum_a + } + #[doc = "0x150 - result of sum of af window b"] + #[inline(always)] + pub const fn af_sum_b(&self) -> &AF_SUM_B { + &self.af_sum_b + } + #[doc = "0x154 - result of sum of af window c"] + #[inline(always)] + pub const fn af_sum_c(&self) -> &AF_SUM_C { + &self.af_sum_c + } + #[doc = "0x158 - result of lum of af window a"] + #[inline(always)] + pub const fn af_lum_a(&self) -> &AF_LUM_A { + &self.af_lum_a + } + #[doc = "0x15c - result of lum of af window b"] + #[inline(always)] + pub const fn af_lum_b(&self) -> &AF_LUM_B { + &self.af_lum_b + } + #[doc = "0x160 - result of lum of af window c"] + #[inline(always)] + pub const fn af_lum_c(&self) -> &AF_LUM_C { + &self.af_lum_c + } + #[doc = "0x164 - awb mode control register"] + #[inline(always)] + pub const fn awb_mode(&self) -> &AWB_MODE { + &self.awb_mode + } + #[doc = "0x168 - h-scale of awb window"] + #[inline(always)] + pub const fn awb_hscale(&self) -> &AWB_HSCALE { + &self.awb_hscale + } + #[doc = "0x16c - v-scale of awb window"] + #[inline(always)] + pub const fn awb_vscale(&self) -> &AWB_VSCALE { + &self.awb_vscale + } + #[doc = "0x170 - awb lum threshold register"] + #[inline(always)] + pub const fn awb_th_lum(&self) -> &AWB_TH_LUM { + &self.awb_th_lum + } + #[doc = "0x174 - awb r/g threshold register"] + #[inline(always)] + pub const fn awb_th_rg(&self) -> &AWB_TH_RG { + &self.awb_th_rg + } + #[doc = "0x178 - awb b/g threshold register"] + #[inline(always)] + pub const fn awb_th_bg(&self) -> &AWB_TH_BG { + &self.awb_th_bg + } + #[doc = "0x17c - result of awb white point number"] + #[inline(always)] + pub const fn awb0_white_cnt(&self) -> &AWB0_WHITE_CNT { + &self.awb0_white_cnt + } + #[doc = "0x180 - result of accumulate of r channel of all white points"] + #[inline(always)] + pub const fn awb0_acc_r(&self) -> &AWB0_ACC_R { + &self.awb0_acc_r + } + #[doc = "0x184 - result of accumulate of g channel of all white points"] + #[inline(always)] + pub const fn awb0_acc_g(&self) -> &AWB0_ACC_G { + &self.awb0_acc_g + } + #[doc = "0x188 - result of accumulate of b channel of all white points"] + #[inline(always)] + pub const fn awb0_acc_b(&self) -> &AWB0_ACC_B { + &self.awb0_acc_b + } + #[doc = "0x18c - color control register"] + #[inline(always)] + pub const fn color_ctrl(&self) -> &COLOR_CTRL { + &self.color_ctrl + } + #[doc = "0x190 - blc black level register"] + #[inline(always)] + pub const fn blc_value(&self) -> &BLC_VALUE { + &self.blc_value + } + #[doc = "0x194 - blc stretch control register"] + #[inline(always)] + pub const fn blc_ctrl0(&self) -> &BLC_CTRL0 { + &self.blc_ctrl0 + } + #[doc = "0x198 - blc window control register"] + #[inline(always)] + pub const fn blc_ctrl1(&self) -> &BLC_CTRL1 { + &self.blc_ctrl1 + } + #[doc = "0x19c - blc black threshold control register"] + #[inline(always)] + pub const fn blc_ctrl2(&self) -> &BLC_CTRL2 { + &self.blc_ctrl2 + } + #[doc = "0x1a0 - results of the average of black window"] + #[inline(always)] + pub const fn blc_mean(&self) -> &BLC_MEAN { + &self.blc_mean + } + #[doc = "0x1a4 - histogram mode control register"] + #[inline(always)] + pub const fn hist_mode(&self) -> &HIST_MODE { + &self.hist_mode + } + #[doc = "0x1a8 - histogram rgb to gray coefficients register"] + #[inline(always)] + pub const fn hist_coeff(&self) -> &HIST_COEFF { + &self.hist_coeff + } + #[doc = "0x1ac - histogram window offsets register"] + #[inline(always)] + pub const fn hist_offs(&self) -> &HIST_OFFS { + &self.hist_offs + } + #[doc = "0x1b0 - histogram sub-window size register"] + #[inline(always)] + pub const fn hist_size(&self) -> &HIST_SIZE { + &self.hist_size + } + #[doc = "0x1b4 - histogram bin control register 0"] + #[inline(always)] + pub const fn hist_seg0(&self) -> &HIST_SEG0 { + &self.hist_seg0 + } + #[doc = "0x1b8 - histogram bin control register 1"] + #[inline(always)] + pub const fn hist_seg1(&self) -> &HIST_SEG1 { + &self.hist_seg1 + } + #[doc = "0x1bc - histogram bin control register 2"] + #[inline(always)] + pub const fn hist_seg2(&self) -> &HIST_SEG2 { + &self.hist_seg2 + } + #[doc = "0x1c0 - histogram bin control register 3"] + #[inline(always)] + pub const fn hist_seg3(&self) -> &HIST_SEG3 { + &self.hist_seg3 + } + #[doc = "0x1c4 - histogram sub-window weight register 0"] + #[inline(always)] + pub const fn hist_weight0(&self) -> &HIST_WEIGHT0 { + &self.hist_weight0 + } + #[doc = "0x1c8 - histogram sub-window weight register 1"] + #[inline(always)] + pub const fn hist_weight1(&self) -> &HIST_WEIGHT1 { + &self.hist_weight1 + } + #[doc = "0x1cc - histogram sub-window weight register 2"] + #[inline(always)] + pub const fn hist_weight2(&self) -> &HIST_WEIGHT2 { + &self.hist_weight2 + } + #[doc = "0x1d0 - histogram sub-window weight register 3"] + #[inline(always)] + pub const fn hist_weight3(&self) -> &HIST_WEIGHT3 { + &self.hist_weight3 + } + #[doc = "0x1d4 - histogram sub-window weight register 4"] + #[inline(always)] + pub const fn hist_weight4(&self) -> &HIST_WEIGHT4 { + &self.hist_weight4 + } + #[doc = "0x1d8 - histogram sub-window weight register 5"] + #[inline(always)] + pub const fn hist_weight5(&self) -> &HIST_WEIGHT5 { + &self.hist_weight5 + } + #[doc = "0x1dc - histogram sub-window weight register 6"] + #[inline(always)] + pub const fn hist_weight6(&self) -> &HIST_WEIGHT6 { + &self.hist_weight6 + } + #[doc = "0x1e0 - result of histogram bin 0"] + #[inline(always)] + pub const fn hist_bin0(&self) -> &HIST_BIN0 { + &self.hist_bin0 + } + #[doc = "0x1e4 - result of histogram bin 1"] + #[inline(always)] + pub const fn hist_bin1(&self) -> &HIST_BIN1 { + &self.hist_bin1 + } + #[doc = "0x1e8 - result of histogram bin 2"] + #[inline(always)] + pub const fn hist_bin2(&self) -> &HIST_BIN2 { + &self.hist_bin2 + } + #[doc = "0x1ec - result of histogram bin 3"] + #[inline(always)] + pub const fn hist_bin3(&self) -> &HIST_BIN3 { + &self.hist_bin3 + } + #[doc = "0x1f0 - result of histogram bin 4"] + #[inline(always)] + pub const fn hist_bin4(&self) -> &HIST_BIN4 { + &self.hist_bin4 + } + #[doc = "0x1f4 - result of histogram bin 5"] + #[inline(always)] + pub const fn hist_bin5(&self) -> &HIST_BIN5 { + &self.hist_bin5 + } + #[doc = "0x1f8 - result of histogram bin 6"] + #[inline(always)] + pub const fn hist_bin6(&self) -> &HIST_BIN6 { + &self.hist_bin6 + } + #[doc = "0x1fc - result of histogram bin 7"] + #[inline(always)] + pub const fn hist_bin7(&self) -> &HIST_BIN7 { + &self.hist_bin7 + } + #[doc = "0x200 - result of histogram bin 8"] + #[inline(always)] + pub const fn hist_bin8(&self) -> &HIST_BIN8 { + &self.hist_bin8 + } + #[doc = "0x204 - result of histogram bin 9"] + #[inline(always)] + pub const fn hist_bin9(&self) -> &HIST_BIN9 { + &self.hist_bin9 + } + #[doc = "0x208 - result of histogram bin 10"] + #[inline(always)] + pub const fn hist_bin10(&self) -> &HIST_BIN10 { + &self.hist_bin10 + } + #[doc = "0x20c - result of histogram bin 11"] + #[inline(always)] + pub const fn hist_bin11(&self) -> &HIST_BIN11 { + &self.hist_bin11 + } + #[doc = "0x210 - result of histogram bin 12"] + #[inline(always)] + pub const fn hist_bin12(&self) -> &HIST_BIN12 { + &self.hist_bin12 + } + #[doc = "0x214 - result of histogram bin 13"] + #[inline(always)] + pub const fn hist_bin13(&self) -> &HIST_BIN13 { + &self.hist_bin13 + } + #[doc = "0x218 - result of histogram bin 14"] + #[inline(always)] + pub const fn hist_bin14(&self) -> &HIST_BIN14 { + &self.hist_bin14 + } + #[doc = "0x21c - result of histogram bin 15"] + #[inline(always)] + pub const fn hist_bin15(&self) -> &HIST_BIN15 { + &self.hist_bin15 + } + #[doc = "0x220 - mem aux control register 0"] + #[inline(always)] + pub const fn mem_aux_ctrl_0(&self) -> &MEM_AUX_CTRL_0 { + &self.mem_aux_ctrl_0 + } + #[doc = "0x224 - mem aux control register 1"] + #[inline(always)] + pub const fn mem_aux_ctrl_1(&self) -> &MEM_AUX_CTRL_1 { + &self.mem_aux_ctrl_1 + } + #[doc = "0x228 - mem aux control register 2"] + #[inline(always)] + pub const fn mem_aux_ctrl_2(&self) -> &MEM_AUX_CTRL_2 { + &self.mem_aux_ctrl_2 + } + #[doc = "0x22c - mem aux control register 3"] + #[inline(always)] + pub const fn mem_aux_ctrl_3(&self) -> &MEM_AUX_CTRL_3 { + &self.mem_aux_ctrl_3 + } + #[doc = "0x230 - mem aux control register 4"] + #[inline(always)] + pub const fn mem_aux_ctrl_4(&self) -> &MEM_AUX_CTRL_4 { + &self.mem_aux_ctrl_4 + } + #[doc = "0x234 - yuv format control register"] + #[inline(always)] + pub const fn yuv_format(&self) -> &YUV_FORMAT { + &self.yuv_format + } + #[doc = "0x238 - rdn eco cs register"] + #[inline(always)] + pub const fn rdn_eco_cs(&self) -> &RDN_ECO_CS { + &self.rdn_eco_cs + } + #[doc = "0x23c - rdn eco all low register"] + #[inline(always)] + pub const fn rdn_eco_low(&self) -> &RDN_ECO_LOW { + &self.rdn_eco_low + } + #[doc = "0x240 - rdn eco all high register"] + #[inline(always)] + pub const fn rdn_eco_high(&self) -> &RDN_ECO_HIGH { + &self.rdn_eco_high + } +} +#[doc = "VER_DATE (rw) register accessor: version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ver_date`] module"] +pub type VER_DATE = crate::Reg; +#[doc = "version control register"] +pub mod ver_date; +#[doc = "CLK_EN (rw) register accessor: isp clk control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_en`] module"] +pub type CLK_EN = crate::Reg; +#[doc = "isp clk control register"] +pub mod clk_en; +#[doc = "CNTL (rw) register accessor: isp module enable control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntl`] module"] +pub type CNTL = crate::Reg; +#[doc = "isp module enable control register"] +pub mod cntl; +#[doc = "HSYNC_CNT (rw) register accessor: header hsync interval control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hsync_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hsync_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hsync_cnt`] module"] +pub type HSYNC_CNT = crate::Reg; +#[doc = "header hsync interval control register"] +pub mod hsync_cnt; +#[doc = "FRAME_CFG (rw) register accessor: frame control parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frame_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frame_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frame_cfg`] module"] +pub type FRAME_CFG = crate::Reg; +#[doc = "frame control parameter register"] +pub mod frame_cfg; +#[doc = "CCM_COEF0 (rw) register accessor: ccm coef register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccm_coef0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccm_coef0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccm_coef0`] module"] +pub type CCM_COEF0 = crate::Reg; +#[doc = "ccm coef register 0"] +pub mod ccm_coef0; +#[doc = "CCM_COEF1 (rw) register accessor: ccm coef register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccm_coef1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccm_coef1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccm_coef1`] module"] +pub type CCM_COEF1 = crate::Reg; +#[doc = "ccm coef register 1"] +pub mod ccm_coef1; +#[doc = "CCM_COEF3 (rw) register accessor: ccm coef register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccm_coef3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccm_coef3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccm_coef3`] module"] +pub type CCM_COEF3 = crate::Reg; +#[doc = "ccm coef register 3"] +pub mod ccm_coef3; +#[doc = "CCM_COEF4 (rw) register accessor: ccm coef register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccm_coef4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccm_coef4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccm_coef4`] module"] +pub type CCM_COEF4 = crate::Reg; +#[doc = "ccm coef register 4"] +pub mod ccm_coef4; +#[doc = "CCM_COEF5 (rw) register accessor: ccm coef register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccm_coef5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccm_coef5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccm_coef5`] module"] +pub type CCM_COEF5 = crate::Reg; +#[doc = "ccm coef register 5"] +pub mod ccm_coef5; +#[doc = "BF_MATRIX_CTRL (rw) register accessor: bf pix2matrix ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bf_matrix_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bf_matrix_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bf_matrix_ctrl`] module"] +pub type BF_MATRIX_CTRL = crate::Reg; +#[doc = "bf pix2matrix ctrl"] +pub mod bf_matrix_ctrl; +#[doc = "BF_SIGMA (rw) register accessor: bf denoising level control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bf_sigma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bf_sigma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bf_sigma`] module"] +pub type BF_SIGMA = crate::Reg; +#[doc = "bf denoising level control register"] +pub mod bf_sigma; +#[doc = "BF_GAU0 (rw) register accessor: bf gau template register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bf_gau0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bf_gau0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bf_gau0`] module"] +pub type BF_GAU0 = crate::Reg; +#[doc = "bf gau template register 0"] +pub mod bf_gau0; +#[doc = "BF_GAU1 (rw) register accessor: bf gau template register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bf_gau1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bf_gau1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bf_gau1`] module"] +pub type BF_GAU1 = crate::Reg; +#[doc = "bf gau template register 1"] +pub mod bf_gau1; +#[doc = "DPC_CTRL (rw) register accessor: DPC mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpc_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpc_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpc_ctrl`] module"] +pub type DPC_CTRL = crate::Reg; +#[doc = "DPC mode control register"] +pub mod dpc_ctrl; +#[doc = "DPC_CONF (rw) register accessor: DPC parameter config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpc_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpc_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpc_conf`] module"] +pub type DPC_CONF = crate::Reg; +#[doc = "DPC parameter config register"] +pub mod dpc_conf; +#[doc = "DPC_MATRIX_CTRL (rw) register accessor: dpc pix2matrix ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpc_matrix_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpc_matrix_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpc_matrix_ctrl`] module"] +pub type DPC_MATRIX_CTRL = crate::Reg; +#[doc = "dpc pix2matrix ctrl"] +pub mod dpc_matrix_ctrl; +#[doc = "DPC_DEADPIX_CNT (r) register accessor: DPC dead-pix number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpc_deadpix_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpc_deadpix_cnt`] module"] +pub type DPC_DEADPIX_CNT = crate::Reg; +#[doc = "DPC dead-pix number register"] +pub mod dpc_deadpix_cnt; +#[doc = "LUT_CMD (w) register accessor: LUT command register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lut_cmd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lut_cmd`] module"] +pub type LUT_CMD = crate::Reg; +#[doc = "LUT command register"] +pub mod lut_cmd; +#[doc = "LUT_WDATA (rw) register accessor: LUT write data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lut_wdata::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lut_wdata::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lut_wdata`] module"] +pub type LUT_WDATA = crate::Reg; +#[doc = "LUT write data register"] +pub mod lut_wdata; +#[doc = "LUT_RDATA (r) register accessor: LUT read data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lut_rdata::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lut_rdata`] module"] +pub type LUT_RDATA = crate::Reg; +#[doc = "LUT read data register"] +pub mod lut_rdata; +#[doc = "LSC_TABLESIZE (rw) register accessor: LSC point in x-direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsc_tablesize::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsc_tablesize::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsc_tablesize`] module"] +pub type LSC_TABLESIZE = crate::Reg; +#[doc = "LSC point in x-direction"] +pub mod lsc_tablesize; +#[doc = "DEMOSAIC_MATRIX_CTRL (rw) register accessor: demosaic pix2matrix ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`demosaic_matrix_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`demosaic_matrix_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@demosaic_matrix_ctrl`] module"] +pub type DEMOSAIC_MATRIX_CTRL = crate::Reg; +#[doc = "demosaic pix2matrix ctrl"] +pub mod demosaic_matrix_ctrl; +#[doc = "DEMOSAIC_GRAD_RATIO (rw) register accessor: demosaic gradient select ratio\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`demosaic_grad_ratio::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`demosaic_grad_ratio::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@demosaic_grad_ratio`] module"] +pub type DEMOSAIC_GRAD_RATIO = crate::Reg; +#[doc = "demosaic gradient select ratio"] +pub mod demosaic_grad_ratio; +#[doc = "MEDIAN_MATRIX_CTRL (rw) register accessor: median pix2matrix ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`median_matrix_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`median_matrix_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@median_matrix_ctrl`] module"] +pub type MEDIAN_MATRIX_CTRL = crate::Reg; +#[doc = "median pix2matrix ctrl"] +pub mod median_matrix_ctrl; +#[doc = "INT_RAW (r) register accessor: raw interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "raw interrupt register"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "masked interrupt register"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "interrupt enable register"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "interrupt clear register"] +pub mod int_clr; +#[doc = "GAMMA_CTRL (rw) register accessor: gamma control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_ctrl`] module"] +pub type GAMMA_CTRL = crate::Reg; +#[doc = "gamma control register"] +pub mod gamma_ctrl; +#[doc = "GAMMA_RY1 (rw) register accessor: point of Y-axis of r channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_ry1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_ry1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_ry1`] module"] +pub type GAMMA_RY1 = crate::Reg; +#[doc = "point of Y-axis of r channel gamma curve register 1"] +pub mod gamma_ry1; +#[doc = "GAMMA_RY2 (rw) register accessor: point of Y-axis of r channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_ry2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_ry2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_ry2`] module"] +pub type GAMMA_RY2 = crate::Reg; +#[doc = "point of Y-axis of r channel gamma curve register 2"] +pub mod gamma_ry2; +#[doc = "GAMMA_RY3 (rw) register accessor: point of Y-axis of r channel gamma curve register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_ry3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_ry3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_ry3`] module"] +pub type GAMMA_RY3 = crate::Reg; +#[doc = "point of Y-axis of r channel gamma curve register 3"] +pub mod gamma_ry3; +#[doc = "GAMMA_RY4 (rw) register accessor: point of Y-axis of r channel gamma curve register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_ry4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_ry4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_ry4`] module"] +pub type GAMMA_RY4 = crate::Reg; +#[doc = "point of Y-axis of r channel gamma curve register 4"] +pub mod gamma_ry4; +#[doc = "GAMMA_GY1 (rw) register accessor: point of Y-axis of g channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gy1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gy1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_gy1`] module"] +pub type GAMMA_GY1 = crate::Reg; +#[doc = "point of Y-axis of g channel gamma curve register 1"] +pub mod gamma_gy1; +#[doc = "GAMMA_GY2 (rw) register accessor: point of Y-axis of g channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gy2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gy2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_gy2`] module"] +pub type GAMMA_GY2 = crate::Reg; +#[doc = "point of Y-axis of g channel gamma curve register 2"] +pub mod gamma_gy2; +#[doc = "GAMMA_GY3 (rw) register accessor: point of Y-axis of g channel gamma curve register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gy3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gy3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_gy3`] module"] +pub type GAMMA_GY3 = crate::Reg; +#[doc = "point of Y-axis of g channel gamma curve register 3"] +pub mod gamma_gy3; +#[doc = "GAMMA_GY4 (rw) register accessor: point of Y-axis of g channel gamma curve register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gy4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gy4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_gy4`] module"] +pub type GAMMA_GY4 = crate::Reg; +#[doc = "point of Y-axis of g channel gamma curve register 4"] +pub mod gamma_gy4; +#[doc = "GAMMA_BY1 (rw) register accessor: point of Y-axis of b channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_by1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_by1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_by1`] module"] +pub type GAMMA_BY1 = crate::Reg; +#[doc = "point of Y-axis of b channel gamma curve register 1"] +pub mod gamma_by1; +#[doc = "GAMMA_BY2 (rw) register accessor: point of Y-axis of b channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_by2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_by2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_by2`] module"] +pub type GAMMA_BY2 = crate::Reg; +#[doc = "point of Y-axis of b channel gamma curve register 2"] +pub mod gamma_by2; +#[doc = "GAMMA_BY3 (rw) register accessor: point of Y-axis of b channel gamma curve register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_by3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_by3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_by3`] module"] +pub type GAMMA_BY3 = crate::Reg; +#[doc = "point of Y-axis of b channel gamma curve register 3"] +pub mod gamma_by3; +#[doc = "GAMMA_BY4 (rw) register accessor: point of Y-axis of b channel gamma curve register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_by4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_by4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_by4`] module"] +pub type GAMMA_BY4 = crate::Reg; +#[doc = "point of Y-axis of b channel gamma curve register 4"] +pub mod gamma_by4; +#[doc = "GAMMA_RX1 (rw) register accessor: point of X-axis of r channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_rx1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_rx1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_rx1`] module"] +pub type GAMMA_RX1 = crate::Reg; +#[doc = "point of X-axis of r channel gamma curve register 1"] +pub mod gamma_rx1; +#[doc = "GAMMA_RX2 (rw) register accessor: point of X-axis of r channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_rx2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_rx2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_rx2`] module"] +pub type GAMMA_RX2 = crate::Reg; +#[doc = "point of X-axis of r channel gamma curve register 2"] +pub mod gamma_rx2; +#[doc = "GAMMA_GX1 (rw) register accessor: point of X-axis of g channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gx1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gx1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_gx1`] module"] +pub type GAMMA_GX1 = crate::Reg; +#[doc = "point of X-axis of g channel gamma curve register 1"] +pub mod gamma_gx1; +#[doc = "GAMMA_GX2 (rw) register accessor: point of X-axis of g channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gx2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gx2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_gx2`] module"] +pub type GAMMA_GX2 = crate::Reg; +#[doc = "point of X-axis of g channel gamma curve register 2"] +pub mod gamma_gx2; +#[doc = "GAMMA_BX1 (rw) register accessor: point of X-axis of b channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_bx1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_bx1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_bx1`] module"] +pub type GAMMA_BX1 = crate::Reg; +#[doc = "point of X-axis of b channel gamma curve register 1"] +pub mod gamma_bx1; +#[doc = "GAMMA_BX2 (rw) register accessor: point of X-axis of b channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_bx2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_bx2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gamma_bx2`] module"] +pub type GAMMA_BX2 = crate::Reg; +#[doc = "point of X-axis of b channel gamma curve register 2"] +pub mod gamma_bx2; +#[doc = "AE_CTRL (rw) register accessor: ae control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_ctrl`] module"] +pub type AE_CTRL = crate::Reg; +#[doc = "ae control register"] +pub mod ae_ctrl; +#[doc = "AE_MONITOR (rw) register accessor: ae monitor control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_monitor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_monitor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_monitor`] module"] +pub type AE_MONITOR = crate::Reg; +#[doc = "ae monitor control register"] +pub mod ae_monitor; +#[doc = "AE_BX (rw) register accessor: ae window register in x-direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_bx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_bx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_bx`] module"] +pub type AE_BX = crate::Reg; +#[doc = "ae window register in x-direction"] +pub mod ae_bx; +#[doc = "AE_BY (rw) register accessor: ae window register in y-direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_by::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_by::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_by`] module"] +pub type AE_BY = crate::Reg; +#[doc = "ae window register in y-direction"] +pub mod ae_by; +#[doc = "AE_WINPIXNUM (rw) register accessor: ae sub-window pix num register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_winpixnum::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_winpixnum::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_winpixnum`] module"] +pub type AE_WINPIXNUM = crate::Reg; +#[doc = "ae sub-window pix num register"] +pub mod ae_winpixnum; +#[doc = "AE_WIN_RECIPROCAL (rw) register accessor: reciprocal of ae sub-window pixel number\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_win_reciprocal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_win_reciprocal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_win_reciprocal`] module"] +pub type AE_WIN_RECIPROCAL = crate::Reg; +#[doc = "reciprocal of ae sub-window pixel number"] +pub mod ae_win_reciprocal; +#[doc = "AE_BLOCK_MEAN_0 (r) register accessor: ae statistic result register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_block_mean_0`] module"] +pub type AE_BLOCK_MEAN_0 = crate::Reg; +#[doc = "ae statistic result register 0"] +pub mod ae_block_mean_0; +#[doc = "AE_BLOCK_MEAN_1 (r) register accessor: ae statistic result register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_block_mean_1`] module"] +pub type AE_BLOCK_MEAN_1 = crate::Reg; +#[doc = "ae statistic result register 1"] +pub mod ae_block_mean_1; +#[doc = "AE_BLOCK_MEAN_2 (r) register accessor: ae statistic result register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_block_mean_2`] module"] +pub type AE_BLOCK_MEAN_2 = crate::Reg; +#[doc = "ae statistic result register 2"] +pub mod ae_block_mean_2; +#[doc = "AE_BLOCK_MEAN_3 (r) register accessor: ae statistic result register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_block_mean_3`] module"] +pub type AE_BLOCK_MEAN_3 = crate::Reg; +#[doc = "ae statistic result register 3"] +pub mod ae_block_mean_3; +#[doc = "AE_BLOCK_MEAN_4 (r) register accessor: ae statistic result register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_block_mean_4`] module"] +pub type AE_BLOCK_MEAN_4 = crate::Reg; +#[doc = "ae statistic result register 4"] +pub mod ae_block_mean_4; +#[doc = "AE_BLOCK_MEAN_5 (r) register accessor: ae statistic result register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_block_mean_5`] module"] +pub type AE_BLOCK_MEAN_5 = crate::Reg; +#[doc = "ae statistic result register 5"] +pub mod ae_block_mean_5; +#[doc = "AE_BLOCK_MEAN_6 (r) register accessor: ae statistic result register 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ae_block_mean_6`] module"] +pub type AE_BLOCK_MEAN_6 = crate::Reg; +#[doc = "ae statistic result register 6"] +pub mod ae_block_mean_6; +#[doc = "SHARP_CTRL0 (rw) register accessor: sharp control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sharp_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sharp_ctrl0`] module"] +pub type SHARP_CTRL0 = crate::Reg; +#[doc = "sharp control register 0"] +pub mod sharp_ctrl0; +#[doc = "SHARP_FILTER0 (rw) register accessor: sharp usm config register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_filter0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sharp_filter0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sharp_filter0`] module"] +pub type SHARP_FILTER0 = crate::Reg; +#[doc = "sharp usm config register 0"] +pub mod sharp_filter0; +#[doc = "SHARP_FILTER1 (rw) register accessor: sharp usm config register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_filter1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sharp_filter1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sharp_filter1`] module"] +pub type SHARP_FILTER1 = crate::Reg; +#[doc = "sharp usm config register 1"] +pub mod sharp_filter1; +#[doc = "SHARP_FILTER2 (rw) register accessor: sharp usm config register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_filter2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sharp_filter2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sharp_filter2`] module"] +pub type SHARP_FILTER2 = crate::Reg; +#[doc = "sharp usm config register 2"] +pub mod sharp_filter2; +#[doc = "SHARP_MATRIX_CTRL (rw) register accessor: sharp pix2matrix ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_matrix_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sharp_matrix_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sharp_matrix_ctrl`] module"] +pub type SHARP_MATRIX_CTRL = crate::Reg; +#[doc = "sharp pix2matrix ctrl"] +pub mod sharp_matrix_ctrl; +#[doc = "SHARP_CTRL1 (r) register accessor: sharp control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_ctrl1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sharp_ctrl1`] module"] +pub type SHARP_CTRL1 = crate::Reg; +#[doc = "sharp control register 1"] +pub mod sharp_ctrl1; +#[doc = "DMA_CNTL (rw) register accessor: isp dma source trans control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_cntl`] module"] +pub type DMA_CNTL = crate::Reg; +#[doc = "isp dma source trans control register"] +pub mod dma_cntl; +#[doc = "DMA_RAW_DATA (rw) register accessor: isp dma source total raw number set register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_raw_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_raw_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_raw_data`] module"] +pub type DMA_RAW_DATA = crate::Reg; +#[doc = "isp dma source total raw number set register"] +pub mod dma_raw_data; +#[doc = "CAM_CNTL (rw) register accessor: isp cam source control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cam_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cam_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cam_cntl`] module"] +pub type CAM_CNTL = crate::Reg; +#[doc = "isp cam source control register"] +pub mod cam_cntl; +#[doc = "CAM_CONF (rw) register accessor: isp cam source config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cam_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cam_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cam_conf`] module"] +pub type CAM_CONF = crate::Reg; +#[doc = "isp cam source config register"] +pub mod cam_conf; +#[doc = "AF_CTRL0 (rw) register accessor: af control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_ctrl0`] module"] +pub type AF_CTRL0 = crate::Reg; +#[doc = "af control register 0"] +pub mod af_ctrl0; +#[doc = "AF_CTRL1 (rw) register accessor: af control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_ctrl1`] module"] +pub type AF_CTRL1 = crate::Reg; +#[doc = "af control register 1"] +pub mod af_ctrl1; +#[doc = "AF_GEN_TH_CTRL (rw) register accessor: af gen threshold control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_gen_th_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_gen_th_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_gen_th_ctrl`] module"] +pub type AF_GEN_TH_CTRL = crate::Reg; +#[doc = "af gen threshold control register"] +pub mod af_gen_th_ctrl; +#[doc = "AF_ENV_USER_TH_SUM (rw) register accessor: af monitor user sum threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_env_user_th_sum::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_env_user_th_sum::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_env_user_th_sum`] module"] +pub type AF_ENV_USER_TH_SUM = crate::Reg; +#[doc = "af monitor user sum threshold register"] +pub mod af_env_user_th_sum; +#[doc = "AF_ENV_USER_TH_LUM (rw) register accessor: af monitor user lum threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_env_user_th_lum::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_env_user_th_lum::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_env_user_th_lum`] module"] +pub type AF_ENV_USER_TH_LUM = crate::Reg; +#[doc = "af monitor user lum threshold register"] +pub mod af_env_user_th_lum; +#[doc = "AF_THRESHOLD (rw) register accessor: af threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_threshold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_threshold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_threshold`] module"] +pub type AF_THRESHOLD = crate::Reg; +#[doc = "af threshold register"] +pub mod af_threshold; +#[doc = "AF_HSCALE_A (rw) register accessor: h-scale of af window a register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_hscale_a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_hscale_a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_hscale_a`] module"] +pub type AF_HSCALE_A = crate::Reg; +#[doc = "h-scale of af window a register"] +pub mod af_hscale_a; +#[doc = "AF_VSCALE_A (rw) register accessor: v-scale of af window a register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_vscale_a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_vscale_a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_vscale_a`] module"] +pub type AF_VSCALE_A = crate::Reg; +#[doc = "v-scale of af window a register"] +pub mod af_vscale_a; +#[doc = "AF_HSCALE_B (rw) register accessor: h-scale of af window b register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_hscale_b::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_hscale_b::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_hscale_b`] module"] +pub type AF_HSCALE_B = crate::Reg; +#[doc = "h-scale of af window b register"] +pub mod af_hscale_b; +#[doc = "AF_VSCALE_B (rw) register accessor: v-scale of af window b register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_vscale_b::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_vscale_b::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_vscale_b`] module"] +pub type AF_VSCALE_B = crate::Reg; +#[doc = "v-scale of af window b register"] +pub mod af_vscale_b; +#[doc = "AF_HSCALE_C (rw) register accessor: v-scale of af window c register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_hscale_c::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_hscale_c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_hscale_c`] module"] +pub type AF_HSCALE_C = crate::Reg; +#[doc = "v-scale of af window c register"] +pub mod af_hscale_c; +#[doc = "AF_VSCALE_C (rw) register accessor: v-scale of af window c register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_vscale_c::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_vscale_c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_vscale_c`] module"] +pub type AF_VSCALE_C = crate::Reg; +#[doc = "v-scale of af window c register"] +pub mod af_vscale_c; +#[doc = "AF_SUM_A (r) register accessor: result of sum of af window a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_sum_a::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_sum_a`] module"] +pub type AF_SUM_A = crate::Reg; +#[doc = "result of sum of af window a"] +pub mod af_sum_a; +#[doc = "AF_SUM_B (r) register accessor: result of sum of af window b\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_sum_b::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_sum_b`] module"] +pub type AF_SUM_B = crate::Reg; +#[doc = "result of sum of af window b"] +pub mod af_sum_b; +#[doc = "AF_SUM_C (r) register accessor: result of sum of af window c\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_sum_c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_sum_c`] module"] +pub type AF_SUM_C = crate::Reg; +#[doc = "result of sum of af window c"] +pub mod af_sum_c; +#[doc = "AF_LUM_A (r) register accessor: result of lum of af window a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_lum_a::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_lum_a`] module"] +pub type AF_LUM_A = crate::Reg; +#[doc = "result of lum of af window a"] +pub mod af_lum_a; +#[doc = "AF_LUM_B (r) register accessor: result of lum of af window b\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_lum_b::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_lum_b`] module"] +pub type AF_LUM_B = crate::Reg; +#[doc = "result of lum of af window b"] +pub mod af_lum_b; +#[doc = "AF_LUM_C (r) register accessor: result of lum of af window c\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_lum_c::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@af_lum_c`] module"] +pub type AF_LUM_C = crate::Reg; +#[doc = "result of lum of af window c"] +pub mod af_lum_c; +#[doc = "AWB_MODE (rw) register accessor: awb mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@awb_mode`] module"] +pub type AWB_MODE = crate::Reg; +#[doc = "awb mode control register"] +pub mod awb_mode; +#[doc = "AWB_HSCALE (rw) register accessor: h-scale of awb window\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_hscale::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_hscale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@awb_hscale`] module"] +pub type AWB_HSCALE = crate::Reg; +#[doc = "h-scale of awb window"] +pub mod awb_hscale; +#[doc = "AWB_VSCALE (rw) register accessor: v-scale of awb window\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_vscale::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_vscale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@awb_vscale`] module"] +pub type AWB_VSCALE = crate::Reg; +#[doc = "v-scale of awb window"] +pub mod awb_vscale; +#[doc = "AWB_TH_LUM (rw) register accessor: awb lum threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_th_lum::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_th_lum::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@awb_th_lum`] module"] +pub type AWB_TH_LUM = crate::Reg; +#[doc = "awb lum threshold register"] +pub mod awb_th_lum; +#[doc = "AWB_TH_RG (rw) register accessor: awb r/g threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_th_rg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_th_rg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@awb_th_rg`] module"] +pub type AWB_TH_RG = crate::Reg; +#[doc = "awb r/g threshold register"] +pub mod awb_th_rg; +#[doc = "AWB_TH_BG (rw) register accessor: awb b/g threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_th_bg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_th_bg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@awb_th_bg`] module"] +pub type AWB_TH_BG = crate::Reg; +#[doc = "awb b/g threshold register"] +pub mod awb_th_bg; +#[doc = "AWB0_WHITE_CNT (r) register accessor: result of awb white point number\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_white_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@awb0_white_cnt`] module"] +pub type AWB0_WHITE_CNT = crate::Reg; +#[doc = "result of awb white point number"] +pub mod awb0_white_cnt; +#[doc = "AWB0_ACC_R (r) register accessor: result of accumulate of r channel of all white points\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_acc_r::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@awb0_acc_r`] module"] +pub type AWB0_ACC_R = crate::Reg; +#[doc = "result of accumulate of r channel of all white points"] +pub mod awb0_acc_r; +#[doc = "AWB0_ACC_G (r) register accessor: result of accumulate of g channel of all white points\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_acc_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@awb0_acc_g`] module"] +pub type AWB0_ACC_G = crate::Reg; +#[doc = "result of accumulate of g channel of all white points"] +pub mod awb0_acc_g; +#[doc = "AWB0_ACC_B (r) register accessor: result of accumulate of b channel of all white points\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_acc_b::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@awb0_acc_b`] module"] +pub type AWB0_ACC_B = crate::Reg; +#[doc = "result of accumulate of b channel of all white points"] +pub mod awb0_acc_b; +#[doc = "COLOR_CTRL (rw) register accessor: color control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`color_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`color_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@color_ctrl`] module"] +pub type COLOR_CTRL = crate::Reg; +#[doc = "color control register"] +pub mod color_ctrl; +#[doc = "BLC_VALUE (rw) register accessor: blc black level register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blc_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blc_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blc_value`] module"] +pub type BLC_VALUE = crate::Reg; +#[doc = "blc black level register"] +pub mod blc_value; +#[doc = "BLC_CTRL0 (rw) register accessor: blc stretch control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blc_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blc_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blc_ctrl0`] module"] +pub type BLC_CTRL0 = crate::Reg; +#[doc = "blc stretch control register"] +pub mod blc_ctrl0; +#[doc = "BLC_CTRL1 (rw) register accessor: blc window control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blc_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blc_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blc_ctrl1`] module"] +pub type BLC_CTRL1 = crate::Reg; +#[doc = "blc window control register"] +pub mod blc_ctrl1; +#[doc = "BLC_CTRL2 (rw) register accessor: blc black threshold control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blc_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blc_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blc_ctrl2`] module"] +pub type BLC_CTRL2 = crate::Reg; +#[doc = "blc black threshold control register"] +pub mod blc_ctrl2; +#[doc = "BLC_MEAN (r) register accessor: results of the average of black window\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blc_mean::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blc_mean`] module"] +pub type BLC_MEAN = crate::Reg; +#[doc = "results of the average of black window"] +pub mod blc_mean; +#[doc = "HIST_MODE (rw) register accessor: histogram mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_mode`] module"] +pub type HIST_MODE = crate::Reg; +#[doc = "histogram mode control register"] +pub mod hist_mode; +#[doc = "HIST_COEFF (rw) register accessor: histogram rgb to gray coefficients register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_coeff::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_coeff::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_coeff`] module"] +pub type HIST_COEFF = crate::Reg; +#[doc = "histogram rgb to gray coefficients register"] +pub mod hist_coeff; +#[doc = "HIST_OFFS (rw) register accessor: histogram window offsets register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_offs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_offs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_offs`] module"] +pub type HIST_OFFS = crate::Reg; +#[doc = "histogram window offsets register"] +pub mod hist_offs; +#[doc = "HIST_SIZE (rw) register accessor: histogram sub-window size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_size`] module"] +pub type HIST_SIZE = crate::Reg; +#[doc = "histogram sub-window size register"] +pub mod hist_size; +#[doc = "HIST_SEG0 (rw) register accessor: histogram bin control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_seg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_seg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_seg0`] module"] +pub type HIST_SEG0 = crate::Reg; +#[doc = "histogram bin control register 0"] +pub mod hist_seg0; +#[doc = "HIST_SEG1 (rw) register accessor: histogram bin control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_seg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_seg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_seg1`] module"] +pub type HIST_SEG1 = crate::Reg; +#[doc = "histogram bin control register 1"] +pub mod hist_seg1; +#[doc = "HIST_SEG2 (rw) register accessor: histogram bin control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_seg2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_seg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_seg2`] module"] +pub type HIST_SEG2 = crate::Reg; +#[doc = "histogram bin control register 2"] +pub mod hist_seg2; +#[doc = "HIST_SEG3 (rw) register accessor: histogram bin control register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_seg3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_seg3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_seg3`] module"] +pub type HIST_SEG3 = crate::Reg; +#[doc = "histogram bin control register 3"] +pub mod hist_seg3; +#[doc = "HIST_WEIGHT0 (rw) register accessor: histogram sub-window weight register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_weight0`] module"] +pub type HIST_WEIGHT0 = crate::Reg; +#[doc = "histogram sub-window weight register 0"] +pub mod hist_weight0; +#[doc = "HIST_WEIGHT1 (rw) register accessor: histogram sub-window weight register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_weight1`] module"] +pub type HIST_WEIGHT1 = crate::Reg; +#[doc = "histogram sub-window weight register 1"] +pub mod hist_weight1; +#[doc = "HIST_WEIGHT2 (rw) register accessor: histogram sub-window weight register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_weight2`] module"] +pub type HIST_WEIGHT2 = crate::Reg; +#[doc = "histogram sub-window weight register 2"] +pub mod hist_weight2; +#[doc = "HIST_WEIGHT3 (rw) register accessor: histogram sub-window weight register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_weight3`] module"] +pub type HIST_WEIGHT3 = crate::Reg; +#[doc = "histogram sub-window weight register 3"] +pub mod hist_weight3; +#[doc = "HIST_WEIGHT4 (rw) register accessor: histogram sub-window weight register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_weight4`] module"] +pub type HIST_WEIGHT4 = crate::Reg; +#[doc = "histogram sub-window weight register 4"] +pub mod hist_weight4; +#[doc = "HIST_WEIGHT5 (rw) register accessor: histogram sub-window weight register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_weight5`] module"] +pub type HIST_WEIGHT5 = crate::Reg; +#[doc = "histogram sub-window weight register 5"] +pub mod hist_weight5; +#[doc = "HIST_WEIGHT6 (rw) register accessor: histogram sub-window weight register 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_weight6`] module"] +pub type HIST_WEIGHT6 = crate::Reg; +#[doc = "histogram sub-window weight register 6"] +pub mod hist_weight6; +#[doc = "HIST_BIN0 (r) register accessor: result of histogram bin 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin0`] module"] +pub type HIST_BIN0 = crate::Reg; +#[doc = "result of histogram bin 0"] +pub mod hist_bin0; +#[doc = "HIST_BIN1 (r) register accessor: result of histogram bin 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin1`] module"] +pub type HIST_BIN1 = crate::Reg; +#[doc = "result of histogram bin 1"] +pub mod hist_bin1; +#[doc = "HIST_BIN2 (r) register accessor: result of histogram bin 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin2`] module"] +pub type HIST_BIN2 = crate::Reg; +#[doc = "result of histogram bin 2"] +pub mod hist_bin2; +#[doc = "HIST_BIN3 (r) register accessor: result of histogram bin 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin3`] module"] +pub type HIST_BIN3 = crate::Reg; +#[doc = "result of histogram bin 3"] +pub mod hist_bin3; +#[doc = "HIST_BIN4 (r) register accessor: result of histogram bin 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin4`] module"] +pub type HIST_BIN4 = crate::Reg; +#[doc = "result of histogram bin 4"] +pub mod hist_bin4; +#[doc = "HIST_BIN5 (r) register accessor: result of histogram bin 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin5`] module"] +pub type HIST_BIN5 = crate::Reg; +#[doc = "result of histogram bin 5"] +pub mod hist_bin5; +#[doc = "HIST_BIN6 (r) register accessor: result of histogram bin 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin6`] module"] +pub type HIST_BIN6 = crate::Reg; +#[doc = "result of histogram bin 6"] +pub mod hist_bin6; +#[doc = "HIST_BIN7 (r) register accessor: result of histogram bin 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin7`] module"] +pub type HIST_BIN7 = crate::Reg; +#[doc = "result of histogram bin 7"] +pub mod hist_bin7; +#[doc = "HIST_BIN8 (r) register accessor: result of histogram bin 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin8`] module"] +pub type HIST_BIN8 = crate::Reg; +#[doc = "result of histogram bin 8"] +pub mod hist_bin8; +#[doc = "HIST_BIN9 (r) register accessor: result of histogram bin 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin9`] module"] +pub type HIST_BIN9 = crate::Reg; +#[doc = "result of histogram bin 9"] +pub mod hist_bin9; +#[doc = "HIST_BIN10 (r) register accessor: result of histogram bin 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin10`] module"] +pub type HIST_BIN10 = crate::Reg; +#[doc = "result of histogram bin 10"] +pub mod hist_bin10; +#[doc = "HIST_BIN11 (r) register accessor: result of histogram bin 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin11`] module"] +pub type HIST_BIN11 = crate::Reg; +#[doc = "result of histogram bin 11"] +pub mod hist_bin11; +#[doc = "HIST_BIN12 (r) register accessor: result of histogram bin 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin12::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin12`] module"] +pub type HIST_BIN12 = crate::Reg; +#[doc = "result of histogram bin 12"] +pub mod hist_bin12; +#[doc = "HIST_BIN13 (r) register accessor: result of histogram bin 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin13::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin13`] module"] +pub type HIST_BIN13 = crate::Reg; +#[doc = "result of histogram bin 13"] +pub mod hist_bin13; +#[doc = "HIST_BIN14 (r) register accessor: result of histogram bin 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin14::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin14`] module"] +pub type HIST_BIN14 = crate::Reg; +#[doc = "result of histogram bin 14"] +pub mod hist_bin14; +#[doc = "HIST_BIN15 (r) register accessor: result of histogram bin 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin15::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hist_bin15`] module"] +pub type HIST_BIN15 = crate::Reg; +#[doc = "result of histogram bin 15"] +pub mod hist_bin15; +#[doc = "MEM_AUX_CTRL_0 (rw) register accessor: mem aux control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_aux_ctrl_0`] module"] +pub type MEM_AUX_CTRL_0 = crate::Reg; +#[doc = "mem aux control register 0"] +pub mod mem_aux_ctrl_0; +#[doc = "MEM_AUX_CTRL_1 (rw) register accessor: mem aux control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_aux_ctrl_1`] module"] +pub type MEM_AUX_CTRL_1 = crate::Reg; +#[doc = "mem aux control register 1"] +pub mod mem_aux_ctrl_1; +#[doc = "MEM_AUX_CTRL_2 (rw) register accessor: mem aux control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_aux_ctrl_2`] module"] +pub type MEM_AUX_CTRL_2 = crate::Reg; +#[doc = "mem aux control register 2"] +pub mod mem_aux_ctrl_2; +#[doc = "MEM_AUX_CTRL_3 (rw) register accessor: mem aux control register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_aux_ctrl_3`] module"] +pub type MEM_AUX_CTRL_3 = crate::Reg; +#[doc = "mem aux control register 3"] +pub mod mem_aux_ctrl_3; +#[doc = "MEM_AUX_CTRL_4 (rw) register accessor: mem aux control register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_aux_ctrl_4`] module"] +pub type MEM_AUX_CTRL_4 = crate::Reg; +#[doc = "mem aux control register 4"] +pub mod mem_aux_ctrl_4; +#[doc = "YUV_FORMAT (rw) register accessor: yuv format control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`yuv_format::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`yuv_format::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@yuv_format`] module"] +pub type YUV_FORMAT = crate::Reg; +#[doc = "yuv format control register"] +pub mod yuv_format; +#[doc = "RDN_ECO_CS (rw) register accessor: rdn eco cs register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_cs`] module"] +pub type RDN_ECO_CS = crate::Reg; +#[doc = "rdn eco cs register"] +pub mod rdn_eco_cs; +#[doc = "RDN_ECO_LOW (rw) register accessor: rdn eco all low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_low`] module"] +pub type RDN_ECO_LOW = crate::Reg; +#[doc = "rdn eco all low register"] +pub mod rdn_eco_low; +#[doc = "RDN_ECO_HIGH (rw) register accessor: rdn eco all high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_high`] module"] +pub type RDN_ECO_HIGH = crate::Reg; +#[doc = "rdn eco all high register"] +pub mod rdn_eco_high; diff --git a/esp32p4/src/isp/ae_block_mean_0.rs b/esp32p4/src/isp/ae_block_mean_0.rs new file mode 100644 index 0000000000..9a0f203e8e --- /dev/null +++ b/esp32p4/src/isp/ae_block_mean_0.rs @@ -0,0 +1,72 @@ +#[doc = "Register `AE_BLOCK_MEAN_0` reader"] +pub type R = crate::R; +#[doc = "Field `AE_B03_MEAN` reader - this field configures block03 Y mean data"] +pub type AE_B03_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B02_MEAN` reader - this field configures block02 Y mean data"] +pub type AE_B02_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B01_MEAN` reader - this field configures block01 Y mean data"] +pub type AE_B01_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B00_MEAN` reader - this field configures block00 Y mean data"] +pub type AE_B00_MEAN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - this field configures block03 Y mean data"] + #[inline(always)] + pub fn ae_b03_mean(&self) -> AE_B03_MEAN_R { + AE_B03_MEAN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures block02 Y mean data"] + #[inline(always)] + pub fn ae_b02_mean(&self) -> AE_B02_MEAN_R { + AE_B02_MEAN_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures block01 Y mean data"] + #[inline(always)] + pub fn ae_b01_mean(&self) -> AE_B01_MEAN_R { + AE_B01_MEAN_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures block00 Y mean data"] + #[inline(always)] + pub fn ae_b00_mean(&self) -> AE_B00_MEAN_R { + AE_B00_MEAN_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_BLOCK_MEAN_0") + .field( + "ae_b03_mean", + &format_args!("{}", self.ae_b03_mean().bits()), + ) + .field( + "ae_b02_mean", + &format_args!("{}", self.ae_b02_mean().bits()), + ) + .field( + "ae_b01_mean", + &format_args!("{}", self.ae_b01_mean().bits()), + ) + .field( + "ae_b00_mean", + &format_args!("{}", self.ae_b00_mean().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ae statistic result register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_BLOCK_MEAN_0_SPEC; +impl crate::RegisterSpec for AE_BLOCK_MEAN_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_block_mean_0::R`](R) reader structure"] +impl crate::Readable for AE_BLOCK_MEAN_0_SPEC {} +#[doc = "`reset()` method sets AE_BLOCK_MEAN_0 to value 0"] +impl crate::Resettable for AE_BLOCK_MEAN_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/ae_block_mean_1.rs b/esp32p4/src/isp/ae_block_mean_1.rs new file mode 100644 index 0000000000..d16484e940 --- /dev/null +++ b/esp32p4/src/isp/ae_block_mean_1.rs @@ -0,0 +1,72 @@ +#[doc = "Register `AE_BLOCK_MEAN_1` reader"] +pub type R = crate::R; +#[doc = "Field `AE_B12_MEAN` reader - this field configures block12 Y mean data"] +pub type AE_B12_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B11_MEAN` reader - this field configures block11 Y mean data"] +pub type AE_B11_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B10_MEAN` reader - this field configures block10 Y mean data"] +pub type AE_B10_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B04_MEAN` reader - this field configures block04 Y mean data"] +pub type AE_B04_MEAN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - this field configures block12 Y mean data"] + #[inline(always)] + pub fn ae_b12_mean(&self) -> AE_B12_MEAN_R { + AE_B12_MEAN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures block11 Y mean data"] + #[inline(always)] + pub fn ae_b11_mean(&self) -> AE_B11_MEAN_R { + AE_B11_MEAN_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures block10 Y mean data"] + #[inline(always)] + pub fn ae_b10_mean(&self) -> AE_B10_MEAN_R { + AE_B10_MEAN_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures block04 Y mean data"] + #[inline(always)] + pub fn ae_b04_mean(&self) -> AE_B04_MEAN_R { + AE_B04_MEAN_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_BLOCK_MEAN_1") + .field( + "ae_b12_mean", + &format_args!("{}", self.ae_b12_mean().bits()), + ) + .field( + "ae_b11_mean", + &format_args!("{}", self.ae_b11_mean().bits()), + ) + .field( + "ae_b10_mean", + &format_args!("{}", self.ae_b10_mean().bits()), + ) + .field( + "ae_b04_mean", + &format_args!("{}", self.ae_b04_mean().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ae statistic result register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_BLOCK_MEAN_1_SPEC; +impl crate::RegisterSpec for AE_BLOCK_MEAN_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_block_mean_1::R`](R) reader structure"] +impl crate::Readable for AE_BLOCK_MEAN_1_SPEC {} +#[doc = "`reset()` method sets AE_BLOCK_MEAN_1 to value 0"] +impl crate::Resettable for AE_BLOCK_MEAN_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/ae_block_mean_2.rs b/esp32p4/src/isp/ae_block_mean_2.rs new file mode 100644 index 0000000000..c864417253 --- /dev/null +++ b/esp32p4/src/isp/ae_block_mean_2.rs @@ -0,0 +1,72 @@ +#[doc = "Register `AE_BLOCK_MEAN_2` reader"] +pub type R = crate::R; +#[doc = "Field `AE_B21_MEAN` reader - this field configures block21 Y mean data"] +pub type AE_B21_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B20_MEAN` reader - this field configures block20 Y mean data"] +pub type AE_B20_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B14_MEAN` reader - this field configures block14 Y mean data"] +pub type AE_B14_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B13_MEAN` reader - this field configures block13 Y mean data"] +pub type AE_B13_MEAN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - this field configures block21 Y mean data"] + #[inline(always)] + pub fn ae_b21_mean(&self) -> AE_B21_MEAN_R { + AE_B21_MEAN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures block20 Y mean data"] + #[inline(always)] + pub fn ae_b20_mean(&self) -> AE_B20_MEAN_R { + AE_B20_MEAN_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures block14 Y mean data"] + #[inline(always)] + pub fn ae_b14_mean(&self) -> AE_B14_MEAN_R { + AE_B14_MEAN_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures block13 Y mean data"] + #[inline(always)] + pub fn ae_b13_mean(&self) -> AE_B13_MEAN_R { + AE_B13_MEAN_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_BLOCK_MEAN_2") + .field( + "ae_b21_mean", + &format_args!("{}", self.ae_b21_mean().bits()), + ) + .field( + "ae_b20_mean", + &format_args!("{}", self.ae_b20_mean().bits()), + ) + .field( + "ae_b14_mean", + &format_args!("{}", self.ae_b14_mean().bits()), + ) + .field( + "ae_b13_mean", + &format_args!("{}", self.ae_b13_mean().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ae statistic result register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_BLOCK_MEAN_2_SPEC; +impl crate::RegisterSpec for AE_BLOCK_MEAN_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_block_mean_2::R`](R) reader structure"] +impl crate::Readable for AE_BLOCK_MEAN_2_SPEC {} +#[doc = "`reset()` method sets AE_BLOCK_MEAN_2 to value 0"] +impl crate::Resettable for AE_BLOCK_MEAN_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/ae_block_mean_3.rs b/esp32p4/src/isp/ae_block_mean_3.rs new file mode 100644 index 0000000000..8f702de3ea --- /dev/null +++ b/esp32p4/src/isp/ae_block_mean_3.rs @@ -0,0 +1,72 @@ +#[doc = "Register `AE_BLOCK_MEAN_3` reader"] +pub type R = crate::R; +#[doc = "Field `AE_B30_MEAN` reader - this field configures block30 Y mean data"] +pub type AE_B30_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B24_MEAN` reader - this field configures block24 Y mean data"] +pub type AE_B24_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B23_MEAN` reader - this field configures block23 Y mean data"] +pub type AE_B23_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B22_MEAN` reader - this field configures block22 Y mean data"] +pub type AE_B22_MEAN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - this field configures block30 Y mean data"] + #[inline(always)] + pub fn ae_b30_mean(&self) -> AE_B30_MEAN_R { + AE_B30_MEAN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures block24 Y mean data"] + #[inline(always)] + pub fn ae_b24_mean(&self) -> AE_B24_MEAN_R { + AE_B24_MEAN_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures block23 Y mean data"] + #[inline(always)] + pub fn ae_b23_mean(&self) -> AE_B23_MEAN_R { + AE_B23_MEAN_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures block22 Y mean data"] + #[inline(always)] + pub fn ae_b22_mean(&self) -> AE_B22_MEAN_R { + AE_B22_MEAN_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_BLOCK_MEAN_3") + .field( + "ae_b30_mean", + &format_args!("{}", self.ae_b30_mean().bits()), + ) + .field( + "ae_b24_mean", + &format_args!("{}", self.ae_b24_mean().bits()), + ) + .field( + "ae_b23_mean", + &format_args!("{}", self.ae_b23_mean().bits()), + ) + .field( + "ae_b22_mean", + &format_args!("{}", self.ae_b22_mean().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ae statistic result register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_BLOCK_MEAN_3_SPEC; +impl crate::RegisterSpec for AE_BLOCK_MEAN_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_block_mean_3::R`](R) reader structure"] +impl crate::Readable for AE_BLOCK_MEAN_3_SPEC {} +#[doc = "`reset()` method sets AE_BLOCK_MEAN_3 to value 0"] +impl crate::Resettable for AE_BLOCK_MEAN_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/ae_block_mean_4.rs b/esp32p4/src/isp/ae_block_mean_4.rs new file mode 100644 index 0000000000..fb00568007 --- /dev/null +++ b/esp32p4/src/isp/ae_block_mean_4.rs @@ -0,0 +1,72 @@ +#[doc = "Register `AE_BLOCK_MEAN_4` reader"] +pub type R = crate::R; +#[doc = "Field `AE_B34_MEAN` reader - this field configures block34 Y mean data"] +pub type AE_B34_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B33_MEAN` reader - this field configures block33 Y mean data"] +pub type AE_B33_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B32_MEAN` reader - this field configures block32 Y mean data"] +pub type AE_B32_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B31_MEAN` reader - this field configures block31 Y mean data"] +pub type AE_B31_MEAN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - this field configures block34 Y mean data"] + #[inline(always)] + pub fn ae_b34_mean(&self) -> AE_B34_MEAN_R { + AE_B34_MEAN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures block33 Y mean data"] + #[inline(always)] + pub fn ae_b33_mean(&self) -> AE_B33_MEAN_R { + AE_B33_MEAN_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures block32 Y mean data"] + #[inline(always)] + pub fn ae_b32_mean(&self) -> AE_B32_MEAN_R { + AE_B32_MEAN_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures block31 Y mean data"] + #[inline(always)] + pub fn ae_b31_mean(&self) -> AE_B31_MEAN_R { + AE_B31_MEAN_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_BLOCK_MEAN_4") + .field( + "ae_b34_mean", + &format_args!("{}", self.ae_b34_mean().bits()), + ) + .field( + "ae_b33_mean", + &format_args!("{}", self.ae_b33_mean().bits()), + ) + .field( + "ae_b32_mean", + &format_args!("{}", self.ae_b32_mean().bits()), + ) + .field( + "ae_b31_mean", + &format_args!("{}", self.ae_b31_mean().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ae statistic result register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_BLOCK_MEAN_4_SPEC; +impl crate::RegisterSpec for AE_BLOCK_MEAN_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_block_mean_4::R`](R) reader structure"] +impl crate::Readable for AE_BLOCK_MEAN_4_SPEC {} +#[doc = "`reset()` method sets AE_BLOCK_MEAN_4 to value 0"] +impl crate::Resettable for AE_BLOCK_MEAN_4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/ae_block_mean_5.rs b/esp32p4/src/isp/ae_block_mean_5.rs new file mode 100644 index 0000000000..ae0bb3dea3 --- /dev/null +++ b/esp32p4/src/isp/ae_block_mean_5.rs @@ -0,0 +1,72 @@ +#[doc = "Register `AE_BLOCK_MEAN_5` reader"] +pub type R = crate::R; +#[doc = "Field `AE_B43_MEAN` reader - this field configures block43 Y mean data"] +pub type AE_B43_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B42_MEAN` reader - this field configures block42 Y mean data"] +pub type AE_B42_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B41_MEAN` reader - this field configures block41 Y mean data"] +pub type AE_B41_MEAN_R = crate::FieldReader; +#[doc = "Field `AE_B40_MEAN` reader - this field configures block40 Y mean data"] +pub type AE_B40_MEAN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - this field configures block43 Y mean data"] + #[inline(always)] + pub fn ae_b43_mean(&self) -> AE_B43_MEAN_R { + AE_B43_MEAN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures block42 Y mean data"] + #[inline(always)] + pub fn ae_b42_mean(&self) -> AE_B42_MEAN_R { + AE_B42_MEAN_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures block41 Y mean data"] + #[inline(always)] + pub fn ae_b41_mean(&self) -> AE_B41_MEAN_R { + AE_B41_MEAN_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures block40 Y mean data"] + #[inline(always)] + pub fn ae_b40_mean(&self) -> AE_B40_MEAN_R { + AE_B40_MEAN_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_BLOCK_MEAN_5") + .field( + "ae_b43_mean", + &format_args!("{}", self.ae_b43_mean().bits()), + ) + .field( + "ae_b42_mean", + &format_args!("{}", self.ae_b42_mean().bits()), + ) + .field( + "ae_b41_mean", + &format_args!("{}", self.ae_b41_mean().bits()), + ) + .field( + "ae_b40_mean", + &format_args!("{}", self.ae_b40_mean().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ae statistic result register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_BLOCK_MEAN_5_SPEC; +impl crate::RegisterSpec for AE_BLOCK_MEAN_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_block_mean_5::R`](R) reader structure"] +impl crate::Readable for AE_BLOCK_MEAN_5_SPEC {} +#[doc = "`reset()` method sets AE_BLOCK_MEAN_5 to value 0"] +impl crate::Resettable for AE_BLOCK_MEAN_5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/ae_block_mean_6.rs b/esp32p4/src/isp/ae_block_mean_6.rs new file mode 100644 index 0000000000..de64d921c4 --- /dev/null +++ b/esp32p4/src/isp/ae_block_mean_6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `AE_BLOCK_MEAN_6` reader"] +pub type R = crate::R; +#[doc = "Field `AE_B44_MEAN` reader - this field configures block44 Y mean data"] +pub type AE_B44_MEAN_R = crate::FieldReader; +impl R { + #[doc = "Bits 24:31 - this field configures block44 Y mean data"] + #[inline(always)] + pub fn ae_b44_mean(&self) -> AE_B44_MEAN_R { + AE_B44_MEAN_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_BLOCK_MEAN_6") + .field( + "ae_b44_mean", + &format_args!("{}", self.ae_b44_mean().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "ae statistic result register 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_BLOCK_MEAN_6_SPEC; +impl crate::RegisterSpec for AE_BLOCK_MEAN_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_block_mean_6::R`](R) reader structure"] +impl crate::Readable for AE_BLOCK_MEAN_6_SPEC {} +#[doc = "`reset()` method sets AE_BLOCK_MEAN_6 to value 0"] +impl crate::Resettable for AE_BLOCK_MEAN_6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/ae_bx.rs b/esp32p4/src/isp/ae_bx.rs new file mode 100644 index 0000000000..372965298a --- /dev/null +++ b/esp32p4/src/isp/ae_bx.rs @@ -0,0 +1,79 @@ +#[doc = "Register `AE_BX` reader"] +pub type R = crate::R; +#[doc = "Register `AE_BX` writer"] +pub type W = crate::W; +#[doc = "Field `AE_X_BSIZE` reader - this field configures every block x size"] +pub type AE_X_BSIZE_R = crate::FieldReader; +#[doc = "Field `AE_X_BSIZE` writer - this field configures every block x size"] +pub type AE_X_BSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `AE_X_START` reader - this field configures first block start x address"] +pub type AE_X_START_R = crate::FieldReader; +#[doc = "Field `AE_X_START` writer - this field configures first block start x address"] +pub type AE_X_START_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - this field configures every block x size"] + #[inline(always)] + pub fn ae_x_bsize(&self) -> AE_X_BSIZE_R { + AE_X_BSIZE_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 11:21 - this field configures first block start x address"] + #[inline(always)] + pub fn ae_x_start(&self) -> AE_X_START_R { + AE_X_START_R::new(((self.bits >> 11) & 0x07ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_BX") + .field("ae_x_bsize", &format_args!("{}", self.ae_x_bsize().bits())) + .field("ae_x_start", &format_args!("{}", self.ae_x_start().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:10 - this field configures every block x size"] + #[inline(always)] + #[must_use] + pub fn ae_x_bsize(&mut self) -> AE_X_BSIZE_W { + AE_X_BSIZE_W::new(self, 0) + } + #[doc = "Bits 11:21 - this field configures first block start x address"] + #[inline(always)] + #[must_use] + pub fn ae_x_start(&mut self) -> AE_X_START_W { + AE_X_START_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ae window register in x-direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_bx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_bx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_BX_SPEC; +impl crate::RegisterSpec for AE_BX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_bx::R`](R) reader structure"] +impl crate::Readable for AE_BX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ae_bx::W`](W) writer structure"] +impl crate::Writable for AE_BX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AE_BX to value 0x0180"] +impl crate::Resettable for AE_BX_SPEC { + const RESET_VALUE: Self::Ux = 0x0180; +} diff --git a/esp32p4/src/isp/ae_by.rs b/esp32p4/src/isp/ae_by.rs new file mode 100644 index 0000000000..bc6efc4080 --- /dev/null +++ b/esp32p4/src/isp/ae_by.rs @@ -0,0 +1,79 @@ +#[doc = "Register `AE_BY` reader"] +pub type R = crate::R; +#[doc = "Register `AE_BY` writer"] +pub type W = crate::W; +#[doc = "Field `AE_Y_BSIZE` reader - this field configures every block y size"] +pub type AE_Y_BSIZE_R = crate::FieldReader; +#[doc = "Field `AE_Y_BSIZE` writer - this field configures every block y size"] +pub type AE_Y_BSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `AE_Y_START` reader - this field configures first block start y address"] +pub type AE_Y_START_R = crate::FieldReader; +#[doc = "Field `AE_Y_START` writer - this field configures first block start y address"] +pub type AE_Y_START_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - this field configures every block y size"] + #[inline(always)] + pub fn ae_y_bsize(&self) -> AE_Y_BSIZE_R { + AE_Y_BSIZE_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 11:21 - this field configures first block start y address"] + #[inline(always)] + pub fn ae_y_start(&self) -> AE_Y_START_R { + AE_Y_START_R::new(((self.bits >> 11) & 0x07ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_BY") + .field("ae_y_bsize", &format_args!("{}", self.ae_y_bsize().bits())) + .field("ae_y_start", &format_args!("{}", self.ae_y_start().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:10 - this field configures every block y size"] + #[inline(always)] + #[must_use] + pub fn ae_y_bsize(&mut self) -> AE_Y_BSIZE_W { + AE_Y_BSIZE_W::new(self, 0) + } + #[doc = "Bits 11:21 - this field configures first block start y address"] + #[inline(always)] + #[must_use] + pub fn ae_y_start(&mut self) -> AE_Y_START_W { + AE_Y_START_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ae window register in y-direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_by::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_by::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_BY_SPEC; +impl crate::RegisterSpec for AE_BY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_by::R`](R) reader structure"] +impl crate::Readable for AE_BY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ae_by::W`](W) writer structure"] +impl crate::Writable for AE_BY_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AE_BY to value 0xd8"] +impl crate::Resettable for AE_BY_SPEC { + const RESET_VALUE: Self::Ux = 0xd8; +} diff --git a/esp32p4/src/isp/ae_ctrl.rs b/esp32p4/src/isp/ae_ctrl.rs new file mode 100644 index 0000000000..4fca0d1d2e --- /dev/null +++ b/esp32p4/src/isp/ae_ctrl.rs @@ -0,0 +1,71 @@ +#[doc = "Register `AE_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `AE_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `AE_UPDATE` writer - write 1 to this bit triggers one statistic event"] +pub type AE_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AE_SELECT` reader - this field configures ae input data source, 0: data from median, 1: data from gama"] +pub type AE_SELECT_R = crate::BitReader; +#[doc = "Field `AE_SELECT` writer - this field configures ae input data source, 0: data from median, 1: data from gama"] +pub type AE_SELECT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - this field configures ae input data source, 0: data from median, 1: data from gama"] + #[inline(always)] + pub fn ae_select(&self) -> AE_SELECT_R { + AE_SELECT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_CTRL") + .field("ae_select", &format_args!("{}", self.ae_select().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - write 1 to this bit triggers one statistic event"] + #[inline(always)] + #[must_use] + pub fn ae_update(&mut self) -> AE_UPDATE_W { + AE_UPDATE_W::new(self, 0) + } + #[doc = "Bit 1 - this field configures ae input data source, 0: data from median, 1: data from gama"] + #[inline(always)] + #[must_use] + pub fn ae_select(&mut self) -> AE_SELECT_W { + AE_SELECT_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ae control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_CTRL_SPEC; +impl crate::RegisterSpec for AE_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_ctrl::R`](R) reader structure"] +impl crate::Readable for AE_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ae_ctrl::W`](W) writer structure"] +impl crate::Writable for AE_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AE_CTRL to value 0"] +impl crate::Resettable for AE_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/ae_monitor.rs b/esp32p4/src/isp/ae_monitor.rs new file mode 100644 index 0000000000..6cf2c9d37a --- /dev/null +++ b/esp32p4/src/isp/ae_monitor.rs @@ -0,0 +1,95 @@ +#[doc = "Register `AE_MONITOR` reader"] +pub type R = crate::R; +#[doc = "Register `AE_MONITOR` writer"] +pub type W = crate::W; +#[doc = "Field `TL` reader - this field configures the lower lum threshold of ae monitor"] +pub type TL_R = crate::FieldReader; +#[doc = "Field `TL` writer - this field configures the lower lum threshold of ae monitor"] +pub type TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TH` reader - this field configures the higher lum threshold of ae monitor"] +pub type TH_R = crate::FieldReader; +#[doc = "Field `TH` writer - this field configures the higher lum threshold of ae monitor"] +pub type TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PERIOD` reader - this field cnfigures ae monitor frame period"] +pub type PERIOD_R = crate::FieldReader; +#[doc = "Field `PERIOD` writer - this field cnfigures ae monitor frame period"] +pub type PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:7 - this field configures the lower lum threshold of ae monitor"] + #[inline(always)] + pub fn tl(&self) -> TL_R { + TL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the higher lum threshold of ae monitor"] + #[inline(always)] + pub fn th(&self) -> TH_R { + TH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:21 - this field cnfigures ae monitor frame period"] + #[inline(always)] + pub fn period(&self) -> PERIOD_R { + PERIOD_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_MONITOR") + .field("tl", &format_args!("{}", self.tl().bits())) + .field("th", &format_args!("{}", self.th().bits())) + .field("period", &format_args!("{}", self.period().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the lower lum threshold of ae monitor"] + #[inline(always)] + #[must_use] + pub fn tl(&mut self) -> TL_W { + TL_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the higher lum threshold of ae monitor"] + #[inline(always)] + #[must_use] + pub fn th(&mut self) -> TH_W { + TH_W::new(self, 8) + } + #[doc = "Bits 16:21 - this field cnfigures ae monitor frame period"] + #[inline(always)] + #[must_use] + pub fn period(&mut self) -> PERIOD_W { + PERIOD_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ae monitor control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_monitor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_monitor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_MONITOR_SPEC; +impl crate::RegisterSpec for AE_MONITOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_monitor::R`](R) reader structure"] +impl crate::Readable for AE_MONITOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ae_monitor::W`](W) writer structure"] +impl crate::Writable for AE_MONITOR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AE_MONITOR to value 0"] +impl crate::Resettable for AE_MONITOR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/ae_win_reciprocal.rs b/esp32p4/src/isp/ae_win_reciprocal.rs new file mode 100644 index 0000000000..25ecb9fd74 --- /dev/null +++ b/esp32p4/src/isp/ae_win_reciprocal.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AE_WIN_RECIPROCAL` reader"] +pub type R = crate::R; +#[doc = "Register `AE_WIN_RECIPROCAL` writer"] +pub type W = crate::W; +#[doc = "Field `AE_SUBWIN_RECIP` reader - this field configures the reciprocal of each subwin_pixnum, 20bit fraction"] +pub type AE_SUBWIN_RECIP_R = crate::FieldReader; +#[doc = "Field `AE_SUBWIN_RECIP` writer - this field configures the reciprocal of each subwin_pixnum, 20bit fraction"] +pub type AE_SUBWIN_RECIP_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - this field configures the reciprocal of each subwin_pixnum, 20bit fraction"] + #[inline(always)] + pub fn ae_subwin_recip(&self) -> AE_SUBWIN_RECIP_R { + AE_SUBWIN_RECIP_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_WIN_RECIPROCAL") + .field( + "ae_subwin_recip", + &format_args!("{}", self.ae_subwin_recip().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - this field configures the reciprocal of each subwin_pixnum, 20bit fraction"] + #[inline(always)] + #[must_use] + pub fn ae_subwin_recip(&mut self) -> AE_SUBWIN_RECIP_W { + AE_SUBWIN_RECIP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "reciprocal of ae sub-window pixel number\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_win_reciprocal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_win_reciprocal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_WIN_RECIPROCAL_SPEC; +impl crate::RegisterSpec for AE_WIN_RECIPROCAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_win_reciprocal::R`](R) reader structure"] +impl crate::Readable for AE_WIN_RECIPROCAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ae_win_reciprocal::W`](W) writer structure"] +impl crate::Writable for AE_WIN_RECIPROCAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AE_WIN_RECIPROCAL to value 0"] +impl crate::Resettable for AE_WIN_RECIPROCAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/ae_winpixnum.rs b/esp32p4/src/isp/ae_winpixnum.rs new file mode 100644 index 0000000000..b79b7ea619 --- /dev/null +++ b/esp32p4/src/isp/ae_winpixnum.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AE_WINPIXNUM` reader"] +pub type R = crate::R; +#[doc = "Register `AE_WINPIXNUM` writer"] +pub type W = crate::W; +#[doc = "Field `AE_SUBWIN_PIXNUM` reader - this field configures the pixel number of each sub win"] +pub type AE_SUBWIN_PIXNUM_R = crate::FieldReader; +#[doc = "Field `AE_SUBWIN_PIXNUM` writer - this field configures the pixel number of each sub win"] +pub type AE_SUBWIN_PIXNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - this field configures the pixel number of each sub win"] + #[inline(always)] + pub fn ae_subwin_pixnum(&self) -> AE_SUBWIN_PIXNUM_R { + AE_SUBWIN_PIXNUM_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AE_WINPIXNUM") + .field( + "ae_subwin_pixnum", + &format_args!("{}", self.ae_subwin_pixnum().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - this field configures the pixel number of each sub win"] + #[inline(always)] + #[must_use] + pub fn ae_subwin_pixnum(&mut self) -> AE_SUBWIN_PIXNUM_W { + AE_SUBWIN_PIXNUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ae sub-window pix num register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_winpixnum::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ae_winpixnum::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AE_WINPIXNUM_SPEC; +impl crate::RegisterSpec for AE_WINPIXNUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ae_winpixnum::R`](R) reader structure"] +impl crate::Readable for AE_WINPIXNUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ae_winpixnum::W`](W) writer structure"] +impl crate::Writable for AE_WINPIXNUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AE_WINPIXNUM to value 0x0001_4400"] +impl crate::Resettable for AE_WINPIXNUM_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_4400; +} diff --git a/esp32p4/src/isp/af_ctrl0.rs b/esp32p4/src/isp/af_ctrl0.rs new file mode 100644 index 0000000000..753a240309 --- /dev/null +++ b/esp32p4/src/isp/af_ctrl0.rs @@ -0,0 +1,112 @@ +#[doc = "Register `AF_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `AF_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `AF_AUTO_UPDATE` reader - this bit configures auto_update enable. when set to 1, will update sum and lum each frame"] +pub type AF_AUTO_UPDATE_R = crate::BitReader; +#[doc = "Field `AF_AUTO_UPDATE` writer - this bit configures auto_update enable. when set to 1, will update sum and lum each frame"] +pub type AF_AUTO_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AF_MANUAL_UPDATE` writer - write 1 to this bit will update the sum and lum once"] +pub type AF_MANUAL_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AF_ENV_THRESHOLD` reader - this field configures env threshold. when both sum and lum changes larger than this value, consider environment changes and need to trigger a new autofocus. 4Bit fractional"] +pub type AF_ENV_THRESHOLD_R = crate::FieldReader; +#[doc = "Field `AF_ENV_THRESHOLD` writer - this field configures env threshold. when both sum and lum changes larger than this value, consider environment changes and need to trigger a new autofocus. 4Bit fractional"] +pub type AF_ENV_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `AF_ENV_PERIOD` reader - this field configures environment changes detection period (frame). When set to 0, disable this function"] +pub type AF_ENV_PERIOD_R = crate::FieldReader; +#[doc = "Field `AF_ENV_PERIOD` writer - this field configures environment changes detection period (frame). When set to 0, disable this function"] +pub type AF_ENV_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - this bit configures auto_update enable. when set to 1, will update sum and lum each frame"] + #[inline(always)] + pub fn af_auto_update(&self) -> AF_AUTO_UPDATE_R { + AF_AUTO_UPDATE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 8:11 - this field configures env threshold. when both sum and lum changes larger than this value, consider environment changes and need to trigger a new autofocus. 4Bit fractional"] + #[inline(always)] + pub fn af_env_threshold(&self) -> AF_ENV_THRESHOLD_R { + AF_ENV_THRESHOLD_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:23 - this field configures environment changes detection period (frame). When set to 0, disable this function"] + #[inline(always)] + pub fn af_env_period(&self) -> AF_ENV_PERIOD_R { + AF_ENV_PERIOD_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_CTRL0") + .field( + "af_auto_update", + &format_args!("{}", self.af_auto_update().bit()), + ) + .field( + "af_env_threshold", + &format_args!("{}", self.af_env_threshold().bits()), + ) + .field( + "af_env_period", + &format_args!("{}", self.af_env_period().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures auto_update enable. when set to 1, will update sum and lum each frame"] + #[inline(always)] + #[must_use] + pub fn af_auto_update(&mut self) -> AF_AUTO_UPDATE_W { + AF_AUTO_UPDATE_W::new(self, 0) + } + #[doc = "Bit 4 - write 1 to this bit will update the sum and lum once"] + #[inline(always)] + #[must_use] + pub fn af_manual_update(&mut self) -> AF_MANUAL_UPDATE_W { + AF_MANUAL_UPDATE_W::new(self, 4) + } + #[doc = "Bits 8:11 - this field configures env threshold. when both sum and lum changes larger than this value, consider environment changes and need to trigger a new autofocus. 4Bit fractional"] + #[inline(always)] + #[must_use] + pub fn af_env_threshold(&mut self) -> AF_ENV_THRESHOLD_W { + AF_ENV_THRESHOLD_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures environment changes detection period (frame). When set to 0, disable this function"] + #[inline(always)] + #[must_use] + pub fn af_env_period(&mut self) -> AF_ENV_PERIOD_W { + AF_ENV_PERIOD_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "af control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_CTRL0_SPEC; +impl crate::RegisterSpec for AF_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_ctrl0::R`](R) reader structure"] +impl crate::Readable for AF_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_ctrl0::W`](W) writer structure"] +impl crate::Writable for AF_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_CTRL0 to value 0"] +impl crate::Resettable for AF_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/af_ctrl1.rs b/esp32p4/src/isp/af_ctrl1.rs new file mode 100644 index 0000000000..e14e86b00f --- /dev/null +++ b/esp32p4/src/isp/af_ctrl1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AF_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `AF_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `AF_THPIXNUM` reader - this field configures pixnum used when calculating the autofocus threshold. Set to 0 to disable threshold calculation"] +pub type AF_THPIXNUM_R = crate::FieldReader; +#[doc = "Field `AF_THPIXNUM` writer - this field configures pixnum used when calculating the autofocus threshold. Set to 0 to disable threshold calculation"] +pub type AF_THPIXNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 0:21 - this field configures pixnum used when calculating the autofocus threshold. Set to 0 to disable threshold calculation"] + #[inline(always)] + pub fn af_thpixnum(&self) -> AF_THPIXNUM_R { + AF_THPIXNUM_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_CTRL1") + .field( + "af_thpixnum", + &format_args!("{}", self.af_thpixnum().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:21 - this field configures pixnum used when calculating the autofocus threshold. Set to 0 to disable threshold calculation"] + #[inline(always)] + #[must_use] + pub fn af_thpixnum(&mut self) -> AF_THPIXNUM_W { + AF_THPIXNUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "af control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_CTRL1_SPEC; +impl crate::RegisterSpec for AF_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_ctrl1::R`](R) reader structure"] +impl crate::Readable for AF_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_ctrl1::W`](W) writer structure"] +impl crate::Writable for AF_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_CTRL1 to value 0"] +impl crate::Resettable for AF_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/af_env_user_th_lum.rs b/esp32p4/src/isp/af_env_user_th_lum.rs new file mode 100644 index 0000000000..c717be6f94 --- /dev/null +++ b/esp32p4/src/isp/af_env_user_th_lum.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AF_ENV_USER_TH_LUM` reader"] +pub type R = crate::R; +#[doc = "Register `AF_ENV_USER_TH_LUM` writer"] +pub type W = crate::W; +#[doc = "Field `AF_ENV_USER_THRESHOLD_LUM` reader - this field configures user setup env detect lum threshold"] +pub type AF_ENV_USER_THRESHOLD_LUM_R = crate::FieldReader; +#[doc = "Field `AF_ENV_USER_THRESHOLD_LUM` writer - this field configures user setup env detect lum threshold"] +pub type AF_ENV_USER_THRESHOLD_LUM_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 0:29 - this field configures user setup env detect lum threshold"] + #[inline(always)] + pub fn af_env_user_threshold_lum(&self) -> AF_ENV_USER_THRESHOLD_LUM_R { + AF_ENV_USER_THRESHOLD_LUM_R::new(self.bits & 0x3fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_ENV_USER_TH_LUM") + .field( + "af_env_user_threshold_lum", + &format_args!("{}", self.af_env_user_threshold_lum().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:29 - this field configures user setup env detect lum threshold"] + #[inline(always)] + #[must_use] + pub fn af_env_user_threshold_lum( + &mut self, + ) -> AF_ENV_USER_THRESHOLD_LUM_W { + AF_ENV_USER_THRESHOLD_LUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "af monitor user lum threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_env_user_th_lum::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_env_user_th_lum::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_ENV_USER_TH_LUM_SPEC; +impl crate::RegisterSpec for AF_ENV_USER_TH_LUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_env_user_th_lum::R`](R) reader structure"] +impl crate::Readable for AF_ENV_USER_TH_LUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_env_user_th_lum::W`](W) writer structure"] +impl crate::Writable for AF_ENV_USER_TH_LUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_ENV_USER_TH_LUM to value 0"] +impl crate::Resettable for AF_ENV_USER_TH_LUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/af_env_user_th_sum.rs b/esp32p4/src/isp/af_env_user_th_sum.rs new file mode 100644 index 0000000000..14d1738897 --- /dev/null +++ b/esp32p4/src/isp/af_env_user_th_sum.rs @@ -0,0 +1,68 @@ +#[doc = "Register `AF_ENV_USER_TH_SUM` reader"] +pub type R = crate::R; +#[doc = "Register `AF_ENV_USER_TH_SUM` writer"] +pub type W = crate::W; +#[doc = "Field `AF_ENV_USER_THRESHOLD_SUM` reader - this field configures user setup env detect sum threshold"] +pub type AF_ENV_USER_THRESHOLD_SUM_R = crate::FieldReader; +#[doc = "Field `AF_ENV_USER_THRESHOLD_SUM` writer - this field configures user setup env detect sum threshold"] +pub type AF_ENV_USER_THRESHOLD_SUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - this field configures user setup env detect sum threshold"] + #[inline(always)] + pub fn af_env_user_threshold_sum(&self) -> AF_ENV_USER_THRESHOLD_SUM_R { + AF_ENV_USER_THRESHOLD_SUM_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_ENV_USER_TH_SUM") + .field( + "af_env_user_threshold_sum", + &format_args!("{}", self.af_env_user_threshold_sum().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - this field configures user setup env detect sum threshold"] + #[inline(always)] + #[must_use] + pub fn af_env_user_threshold_sum( + &mut self, + ) -> AF_ENV_USER_THRESHOLD_SUM_W { + AF_ENV_USER_THRESHOLD_SUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "af monitor user sum threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_env_user_th_sum::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_env_user_th_sum::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_ENV_USER_TH_SUM_SPEC; +impl crate::RegisterSpec for AF_ENV_USER_TH_SUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_env_user_th_sum::R`](R) reader structure"] +impl crate::Readable for AF_ENV_USER_TH_SUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_env_user_th_sum::W`](W) writer structure"] +impl crate::Writable for AF_ENV_USER_TH_SUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_ENV_USER_TH_SUM to value 0"] +impl crate::Resettable for AF_ENV_USER_TH_SUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/af_gen_th_ctrl.rs b/esp32p4/src/isp/af_gen_th_ctrl.rs new file mode 100644 index 0000000000..2bcb5c5b3d --- /dev/null +++ b/esp32p4/src/isp/af_gen_th_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `AF_GEN_TH_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `AF_GEN_TH_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `AF_GEN_THRESHOLD_MIN` reader - this field configures min threshold when use auto_threshold"] +pub type AF_GEN_THRESHOLD_MIN_R = crate::FieldReader; +#[doc = "Field `AF_GEN_THRESHOLD_MIN` writer - this field configures min threshold when use auto_threshold"] +pub type AF_GEN_THRESHOLD_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `AF_GEN_THRESHOLD_MAX` reader - this field configures max threshold when use auto_threshold"] +pub type AF_GEN_THRESHOLD_MAX_R = crate::FieldReader; +#[doc = "Field `AF_GEN_THRESHOLD_MAX` writer - this field configures max threshold when use auto_threshold"] +pub type AF_GEN_THRESHOLD_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - this field configures min threshold when use auto_threshold"] + #[inline(always)] + pub fn af_gen_threshold_min(&self) -> AF_GEN_THRESHOLD_MIN_R { + AF_GEN_THRESHOLD_MIN_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - this field configures max threshold when use auto_threshold"] + #[inline(always)] + pub fn af_gen_threshold_max(&self) -> AF_GEN_THRESHOLD_MAX_R { + AF_GEN_THRESHOLD_MAX_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_GEN_TH_CTRL") + .field( + "af_gen_threshold_min", + &format_args!("{}", self.af_gen_threshold_min().bits()), + ) + .field( + "af_gen_threshold_max", + &format_args!("{}", self.af_gen_threshold_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - this field configures min threshold when use auto_threshold"] + #[inline(always)] + #[must_use] + pub fn af_gen_threshold_min(&mut self) -> AF_GEN_THRESHOLD_MIN_W { + AF_GEN_THRESHOLD_MIN_W::new(self, 0) + } + #[doc = "Bits 16:31 - this field configures max threshold when use auto_threshold"] + #[inline(always)] + #[must_use] + pub fn af_gen_threshold_max(&mut self) -> AF_GEN_THRESHOLD_MAX_W { + AF_GEN_THRESHOLD_MAX_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "af gen threshold control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_gen_th_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_gen_th_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_GEN_TH_CTRL_SPEC; +impl crate::RegisterSpec for AF_GEN_TH_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_gen_th_ctrl::R`](R) reader structure"] +impl crate::Readable for AF_GEN_TH_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_gen_th_ctrl::W`](W) writer structure"] +impl crate::Writable for AF_GEN_TH_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_GEN_TH_CTRL to value 0x0440_0080"] +impl crate::Resettable for AF_GEN_TH_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0440_0080; +} diff --git a/esp32p4/src/isp/af_hscale_a.rs b/esp32p4/src/isp/af_hscale_a.rs new file mode 100644 index 0000000000..3378585ff5 --- /dev/null +++ b/esp32p4/src/isp/af_hscale_a.rs @@ -0,0 +1,85 @@ +#[doc = "Register `AF_HSCALE_A` reader"] +pub type R = crate::R; +#[doc = "Register `AF_HSCALE_A` writer"] +pub type W = crate::W; +#[doc = "Field `AF_RPOINT_A` reader - this field configures left coordinate of focus window a, must >= 2"] +pub type AF_RPOINT_A_R = crate::FieldReader; +#[doc = "Field `AF_RPOINT_A` writer - this field configures left coordinate of focus window a, must >= 2"] +pub type AF_RPOINT_A_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `AF_LPOINT_A` reader - this field configures top coordinate of focus window a, must >= 2"] +pub type AF_LPOINT_A_R = crate::FieldReader; +#[doc = "Field `AF_LPOINT_A` writer - this field configures top coordinate of focus window a, must >= 2"] +pub type AF_LPOINT_A_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures left coordinate of focus window a, must >= 2"] + #[inline(always)] + pub fn af_rpoint_a(&self) -> AF_RPOINT_A_R { + AF_RPOINT_A_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures top coordinate of focus window a, must >= 2"] + #[inline(always)] + pub fn af_lpoint_a(&self) -> AF_LPOINT_A_R { + AF_LPOINT_A_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_HSCALE_A") + .field( + "af_rpoint_a", + &format_args!("{}", self.af_rpoint_a().bits()), + ) + .field( + "af_lpoint_a", + &format_args!("{}", self.af_lpoint_a().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures left coordinate of focus window a, must >= 2"] + #[inline(always)] + #[must_use] + pub fn af_rpoint_a(&mut self) -> AF_RPOINT_A_W { + AF_RPOINT_A_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures top coordinate of focus window a, must >= 2"] + #[inline(always)] + #[must_use] + pub fn af_lpoint_a(&mut self) -> AF_LPOINT_A_W { + AF_LPOINT_A_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "h-scale of af window a register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_hscale_a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_hscale_a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_HSCALE_A_SPEC; +impl crate::RegisterSpec for AF_HSCALE_A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_hscale_a::R`](R) reader structure"] +impl crate::Readable for AF_HSCALE_A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_hscale_a::W`](W) writer structure"] +impl crate::Writable for AF_HSCALE_A_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_HSCALE_A to value 0x0001_0080"] +impl crate::Resettable for AF_HSCALE_A_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0080; +} diff --git a/esp32p4/src/isp/af_hscale_b.rs b/esp32p4/src/isp/af_hscale_b.rs new file mode 100644 index 0000000000..784a25b7cf --- /dev/null +++ b/esp32p4/src/isp/af_hscale_b.rs @@ -0,0 +1,85 @@ +#[doc = "Register `AF_HSCALE_B` reader"] +pub type R = crate::R; +#[doc = "Register `AF_HSCALE_B` writer"] +pub type W = crate::W; +#[doc = "Field `AF_RPOINT_B` reader - this field configures left coordinate of focus window b, must >= 2"] +pub type AF_RPOINT_B_R = crate::FieldReader; +#[doc = "Field `AF_RPOINT_B` writer - this field configures left coordinate of focus window b, must >= 2"] +pub type AF_RPOINT_B_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `AF_LPOINT_B` reader - this field configures top coordinate of focus window b, must >= 2"] +pub type AF_LPOINT_B_R = crate::FieldReader; +#[doc = "Field `AF_LPOINT_B` writer - this field configures top coordinate of focus window b, must >= 2"] +pub type AF_LPOINT_B_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures left coordinate of focus window b, must >= 2"] + #[inline(always)] + pub fn af_rpoint_b(&self) -> AF_RPOINT_B_R { + AF_RPOINT_B_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures top coordinate of focus window b, must >= 2"] + #[inline(always)] + pub fn af_lpoint_b(&self) -> AF_LPOINT_B_R { + AF_LPOINT_B_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_HSCALE_B") + .field( + "af_rpoint_b", + &format_args!("{}", self.af_rpoint_b().bits()), + ) + .field( + "af_lpoint_b", + &format_args!("{}", self.af_lpoint_b().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures left coordinate of focus window b, must >= 2"] + #[inline(always)] + #[must_use] + pub fn af_rpoint_b(&mut self) -> AF_RPOINT_B_W { + AF_RPOINT_B_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures top coordinate of focus window b, must >= 2"] + #[inline(always)] + #[must_use] + pub fn af_lpoint_b(&mut self) -> AF_LPOINT_B_W { + AF_LPOINT_B_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "h-scale of af window b register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_hscale_b::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_hscale_b::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_HSCALE_B_SPEC; +impl crate::RegisterSpec for AF_HSCALE_B_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_hscale_b::R`](R) reader structure"] +impl crate::Readable for AF_HSCALE_B_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_hscale_b::W`](W) writer structure"] +impl crate::Writable for AF_HSCALE_B_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_HSCALE_B to value 0x0001_0080"] +impl crate::Resettable for AF_HSCALE_B_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0080; +} diff --git a/esp32p4/src/isp/af_hscale_c.rs b/esp32p4/src/isp/af_hscale_c.rs new file mode 100644 index 0000000000..50a0107446 --- /dev/null +++ b/esp32p4/src/isp/af_hscale_c.rs @@ -0,0 +1,85 @@ +#[doc = "Register `AF_HSCALE_C` reader"] +pub type R = crate::R; +#[doc = "Register `AF_HSCALE_C` writer"] +pub type W = crate::W; +#[doc = "Field `AF_RPOINT_C` reader - this field configures left coordinate of focus window c, must >= 2"] +pub type AF_RPOINT_C_R = crate::FieldReader; +#[doc = "Field `AF_RPOINT_C` writer - this field configures left coordinate of focus window c, must >= 2"] +pub type AF_RPOINT_C_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `AF_LPOINT_C` reader - this field configures top coordinate of focus window c, must >= 2"] +pub type AF_LPOINT_C_R = crate::FieldReader; +#[doc = "Field `AF_LPOINT_C` writer - this field configures top coordinate of focus window c, must >= 2"] +pub type AF_LPOINT_C_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures left coordinate of focus window c, must >= 2"] + #[inline(always)] + pub fn af_rpoint_c(&self) -> AF_RPOINT_C_R { + AF_RPOINT_C_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures top coordinate of focus window c, must >= 2"] + #[inline(always)] + pub fn af_lpoint_c(&self) -> AF_LPOINT_C_R { + AF_LPOINT_C_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_HSCALE_C") + .field( + "af_rpoint_c", + &format_args!("{}", self.af_rpoint_c().bits()), + ) + .field( + "af_lpoint_c", + &format_args!("{}", self.af_lpoint_c().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures left coordinate of focus window c, must >= 2"] + #[inline(always)] + #[must_use] + pub fn af_rpoint_c(&mut self) -> AF_RPOINT_C_W { + AF_RPOINT_C_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures top coordinate of focus window c, must >= 2"] + #[inline(always)] + #[must_use] + pub fn af_lpoint_c(&mut self) -> AF_LPOINT_C_W { + AF_LPOINT_C_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "v-scale of af window c register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_hscale_c::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_hscale_c::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_HSCALE_C_SPEC; +impl crate::RegisterSpec for AF_HSCALE_C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_hscale_c::R`](R) reader structure"] +impl crate::Readable for AF_HSCALE_C_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_hscale_c::W`](W) writer structure"] +impl crate::Writable for AF_HSCALE_C_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_HSCALE_C to value 0x0001_0080"] +impl crate::Resettable for AF_HSCALE_C_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0080; +} diff --git a/esp32p4/src/isp/af_lum_a.rs b/esp32p4/src/isp/af_lum_a.rs new file mode 100644 index 0000000000..7842b9dbb7 --- /dev/null +++ b/esp32p4/src/isp/af_lum_a.rs @@ -0,0 +1,36 @@ +#[doc = "Register `AF_LUM_A` reader"] +pub type R = crate::R; +#[doc = "Field `AF_LUMA` reader - this field represents the result of accumulation of pix light of focus window a"] +pub type AF_LUMA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:27 - this field represents the result of accumulation of pix light of focus window a"] + #[inline(always)] + pub fn af_luma(&self) -> AF_LUMA_R { + AF_LUMA_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_LUM_A") + .field("af_luma", &format_args!("{}", self.af_luma().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of lum of af window a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_lum_a::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_LUM_A_SPEC; +impl crate::RegisterSpec for AF_LUM_A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_lum_a::R`](R) reader structure"] +impl crate::Readable for AF_LUM_A_SPEC {} +#[doc = "`reset()` method sets AF_LUM_A to value 0"] +impl crate::Resettable for AF_LUM_A_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/af_lum_b.rs b/esp32p4/src/isp/af_lum_b.rs new file mode 100644 index 0000000000..598bd1d6a3 --- /dev/null +++ b/esp32p4/src/isp/af_lum_b.rs @@ -0,0 +1,36 @@ +#[doc = "Register `AF_LUM_B` reader"] +pub type R = crate::R; +#[doc = "Field `AF_LUMB` reader - this field represents the result of accumulation of pix light of focus window b"] +pub type AF_LUMB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:27 - this field represents the result of accumulation of pix light of focus window b"] + #[inline(always)] + pub fn af_lumb(&self) -> AF_LUMB_R { + AF_LUMB_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_LUM_B") + .field("af_lumb", &format_args!("{}", self.af_lumb().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of lum of af window b\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_lum_b::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_LUM_B_SPEC; +impl crate::RegisterSpec for AF_LUM_B_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_lum_b::R`](R) reader structure"] +impl crate::Readable for AF_LUM_B_SPEC {} +#[doc = "`reset()` method sets AF_LUM_B to value 0"] +impl crate::Resettable for AF_LUM_B_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/af_lum_c.rs b/esp32p4/src/isp/af_lum_c.rs new file mode 100644 index 0000000000..fb8f732f81 --- /dev/null +++ b/esp32p4/src/isp/af_lum_c.rs @@ -0,0 +1,36 @@ +#[doc = "Register `AF_LUM_C` reader"] +pub type R = crate::R; +#[doc = "Field `AF_LUMC` reader - this field represents the result of accumulation of pix light of focus window c"] +pub type AF_LUMC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:27 - this field represents the result of accumulation of pix light of focus window c"] + #[inline(always)] + pub fn af_lumc(&self) -> AF_LUMC_R { + AF_LUMC_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_LUM_C") + .field("af_lumc", &format_args!("{}", self.af_lumc().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of lum of af window c\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_lum_c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_LUM_C_SPEC; +impl crate::RegisterSpec for AF_LUM_C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_lum_c::R`](R) reader structure"] +impl crate::Readable for AF_LUM_C_SPEC {} +#[doc = "`reset()` method sets AF_LUM_C to value 0"] +impl crate::Resettable for AF_LUM_C_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/af_sum_a.rs b/esp32p4/src/isp/af_sum_a.rs new file mode 100644 index 0000000000..ce65fa279e --- /dev/null +++ b/esp32p4/src/isp/af_sum_a.rs @@ -0,0 +1,36 @@ +#[doc = "Register `AF_SUM_A` reader"] +pub type R = crate::R; +#[doc = "Field `AF_SUMA` reader - this field represents the result of accumulation of pix grad of focus window a"] +pub type AF_SUMA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:29 - this field represents the result of accumulation of pix grad of focus window a"] + #[inline(always)] + pub fn af_suma(&self) -> AF_SUMA_R { + AF_SUMA_R::new(self.bits & 0x3fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_SUM_A") + .field("af_suma", &format_args!("{}", self.af_suma().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of sum of af window a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_sum_a::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_SUM_A_SPEC; +impl crate::RegisterSpec for AF_SUM_A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_sum_a::R`](R) reader structure"] +impl crate::Readable for AF_SUM_A_SPEC {} +#[doc = "`reset()` method sets AF_SUM_A to value 0"] +impl crate::Resettable for AF_SUM_A_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/af_sum_b.rs b/esp32p4/src/isp/af_sum_b.rs new file mode 100644 index 0000000000..063972e67e --- /dev/null +++ b/esp32p4/src/isp/af_sum_b.rs @@ -0,0 +1,36 @@ +#[doc = "Register `AF_SUM_B` reader"] +pub type R = crate::R; +#[doc = "Field `AF_SUMB` reader - this field represents the result of accumulation of pix grad of focus window b"] +pub type AF_SUMB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:29 - this field represents the result of accumulation of pix grad of focus window b"] + #[inline(always)] + pub fn af_sumb(&self) -> AF_SUMB_R { + AF_SUMB_R::new(self.bits & 0x3fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_SUM_B") + .field("af_sumb", &format_args!("{}", self.af_sumb().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of sum of af window b\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_sum_b::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_SUM_B_SPEC; +impl crate::RegisterSpec for AF_SUM_B_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_sum_b::R`](R) reader structure"] +impl crate::Readable for AF_SUM_B_SPEC {} +#[doc = "`reset()` method sets AF_SUM_B to value 0"] +impl crate::Resettable for AF_SUM_B_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/af_sum_c.rs b/esp32p4/src/isp/af_sum_c.rs new file mode 100644 index 0000000000..f88154331b --- /dev/null +++ b/esp32p4/src/isp/af_sum_c.rs @@ -0,0 +1,36 @@ +#[doc = "Register `AF_SUM_C` reader"] +pub type R = crate::R; +#[doc = "Field `AF_SUMC` reader - this field represents the result of accumulation of pix grad of focus window c"] +pub type AF_SUMC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:29 - this field represents the result of accumulation of pix grad of focus window c"] + #[inline(always)] + pub fn af_sumc(&self) -> AF_SUMC_R { + AF_SUMC_R::new(self.bits & 0x3fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_SUM_C") + .field("af_sumc", &format_args!("{}", self.af_sumc().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of sum of af window c\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_sum_c::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_SUM_C_SPEC; +impl crate::RegisterSpec for AF_SUM_C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_sum_c::R`](R) reader structure"] +impl crate::Readable for AF_SUM_C_SPEC {} +#[doc = "`reset()` method sets AF_SUM_C to value 0"] +impl crate::Resettable for AF_SUM_C_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/af_threshold.rs b/esp32p4/src/isp/af_threshold.rs new file mode 100644 index 0000000000..2a9f2aef66 --- /dev/null +++ b/esp32p4/src/isp/af_threshold.rs @@ -0,0 +1,77 @@ +#[doc = "Register `AF_THRESHOLD` reader"] +pub type R = crate::R; +#[doc = "Register `AF_THRESHOLD` writer"] +pub type W = crate::W; +#[doc = "Field `AF_THRESHOLD` reader - this field configures user threshold. When set to non-zero, autofocus will use this threshold"] +pub type AF_THRESHOLD_R = crate::FieldReader; +#[doc = "Field `AF_THRESHOLD` writer - this field configures user threshold. When set to non-zero, autofocus will use this threshold"] +pub type AF_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `AF_GEN_THRESHOLD` reader - this field represents the last calculated threshold"] +pub type AF_GEN_THRESHOLD_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - this field configures user threshold. When set to non-zero, autofocus will use this threshold"] + #[inline(always)] + pub fn af_threshold(&self) -> AF_THRESHOLD_R { + AF_THRESHOLD_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - this field represents the last calculated threshold"] + #[inline(always)] + pub fn af_gen_threshold(&self) -> AF_GEN_THRESHOLD_R { + AF_GEN_THRESHOLD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_THRESHOLD") + .field( + "af_threshold", + &format_args!("{}", self.af_threshold().bits()), + ) + .field( + "af_gen_threshold", + &format_args!("{}", self.af_gen_threshold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - this field configures user threshold. When set to non-zero, autofocus will use this threshold"] + #[inline(always)] + #[must_use] + pub fn af_threshold(&mut self) -> AF_THRESHOLD_W { + AF_THRESHOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "af threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_threshold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_threshold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_THRESHOLD_SPEC; +impl crate::RegisterSpec for AF_THRESHOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_threshold::R`](R) reader structure"] +impl crate::Readable for AF_THRESHOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_threshold::W`](W) writer structure"] +impl crate::Writable for AF_THRESHOLD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_THRESHOLD to value 0x0100"] +impl crate::Resettable for AF_THRESHOLD_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/isp/af_vscale_a.rs b/esp32p4/src/isp/af_vscale_a.rs new file mode 100644 index 0000000000..03cbfbe095 --- /dev/null +++ b/esp32p4/src/isp/af_vscale_a.rs @@ -0,0 +1,85 @@ +#[doc = "Register `AF_VSCALE_A` reader"] +pub type R = crate::R; +#[doc = "Register `AF_VSCALE_A` writer"] +pub type W = crate::W; +#[doc = "Field `AF_BPOINT_A` reader - this field configures right coordinate of focus window a, must <= hnum-2"] +pub type AF_BPOINT_A_R = crate::FieldReader; +#[doc = "Field `AF_BPOINT_A` writer - this field configures right coordinate of focus window a, must <= hnum-2"] +pub type AF_BPOINT_A_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `AF_TPOINT_A` reader - this field configures bottom coordinate of focus window a, must <= hnum-2"] +pub type AF_TPOINT_A_R = crate::FieldReader; +#[doc = "Field `AF_TPOINT_A` writer - this field configures bottom coordinate of focus window a, must <= hnum-2"] +pub type AF_TPOINT_A_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures right coordinate of focus window a, must <= hnum-2"] + #[inline(always)] + pub fn af_bpoint_a(&self) -> AF_BPOINT_A_R { + AF_BPOINT_A_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures bottom coordinate of focus window a, must <= hnum-2"] + #[inline(always)] + pub fn af_tpoint_a(&self) -> AF_TPOINT_A_R { + AF_TPOINT_A_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_VSCALE_A") + .field( + "af_bpoint_a", + &format_args!("{}", self.af_bpoint_a().bits()), + ) + .field( + "af_tpoint_a", + &format_args!("{}", self.af_tpoint_a().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures right coordinate of focus window a, must <= hnum-2"] + #[inline(always)] + #[must_use] + pub fn af_bpoint_a(&mut self) -> AF_BPOINT_A_W { + AF_BPOINT_A_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures bottom coordinate of focus window a, must <= hnum-2"] + #[inline(always)] + #[must_use] + pub fn af_tpoint_a(&mut self) -> AF_TPOINT_A_W { + AF_TPOINT_A_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "v-scale of af window a register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_vscale_a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_vscale_a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_VSCALE_A_SPEC; +impl crate::RegisterSpec for AF_VSCALE_A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_vscale_a::R`](R) reader structure"] +impl crate::Readable for AF_VSCALE_A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_vscale_a::W`](W) writer structure"] +impl crate::Writable for AF_VSCALE_A_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_VSCALE_A to value 0x0001_0080"] +impl crate::Resettable for AF_VSCALE_A_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0080; +} diff --git a/esp32p4/src/isp/af_vscale_b.rs b/esp32p4/src/isp/af_vscale_b.rs new file mode 100644 index 0000000000..fee701b1ab --- /dev/null +++ b/esp32p4/src/isp/af_vscale_b.rs @@ -0,0 +1,85 @@ +#[doc = "Register `AF_VSCALE_B` reader"] +pub type R = crate::R; +#[doc = "Register `AF_VSCALE_B` writer"] +pub type W = crate::W; +#[doc = "Field `AF_BPOINT_B` reader - this field configures right coordinate of focus window b, must <= hnum-2"] +pub type AF_BPOINT_B_R = crate::FieldReader; +#[doc = "Field `AF_BPOINT_B` writer - this field configures right coordinate of focus window b, must <= hnum-2"] +pub type AF_BPOINT_B_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `AF_TPOINT_B` reader - this field configures bottom coordinate of focus window b, must <= hnum-2"] +pub type AF_TPOINT_B_R = crate::FieldReader; +#[doc = "Field `AF_TPOINT_B` writer - this field configures bottom coordinate of focus window b, must <= hnum-2"] +pub type AF_TPOINT_B_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures right coordinate of focus window b, must <= hnum-2"] + #[inline(always)] + pub fn af_bpoint_b(&self) -> AF_BPOINT_B_R { + AF_BPOINT_B_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures bottom coordinate of focus window b, must <= hnum-2"] + #[inline(always)] + pub fn af_tpoint_b(&self) -> AF_TPOINT_B_R { + AF_TPOINT_B_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_VSCALE_B") + .field( + "af_bpoint_b", + &format_args!("{}", self.af_bpoint_b().bits()), + ) + .field( + "af_tpoint_b", + &format_args!("{}", self.af_tpoint_b().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures right coordinate of focus window b, must <= hnum-2"] + #[inline(always)] + #[must_use] + pub fn af_bpoint_b(&mut self) -> AF_BPOINT_B_W { + AF_BPOINT_B_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures bottom coordinate of focus window b, must <= hnum-2"] + #[inline(always)] + #[must_use] + pub fn af_tpoint_b(&mut self) -> AF_TPOINT_B_W { + AF_TPOINT_B_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "v-scale of af window b register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_vscale_b::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_vscale_b::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_VSCALE_B_SPEC; +impl crate::RegisterSpec for AF_VSCALE_B_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_vscale_b::R`](R) reader structure"] +impl crate::Readable for AF_VSCALE_B_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_vscale_b::W`](W) writer structure"] +impl crate::Writable for AF_VSCALE_B_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_VSCALE_B to value 0x0001_0080"] +impl crate::Resettable for AF_VSCALE_B_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0080; +} diff --git a/esp32p4/src/isp/af_vscale_c.rs b/esp32p4/src/isp/af_vscale_c.rs new file mode 100644 index 0000000000..057dd8fb06 --- /dev/null +++ b/esp32p4/src/isp/af_vscale_c.rs @@ -0,0 +1,85 @@ +#[doc = "Register `AF_VSCALE_C` reader"] +pub type R = crate::R; +#[doc = "Register `AF_VSCALE_C` writer"] +pub type W = crate::W; +#[doc = "Field `AF_BPOINT_C` reader - this field configures right coordinate of focus window c, must <= hnum-2"] +pub type AF_BPOINT_C_R = crate::FieldReader; +#[doc = "Field `AF_BPOINT_C` writer - this field configures right coordinate of focus window c, must <= hnum-2"] +pub type AF_BPOINT_C_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `AF_TPOINT_C` reader - this field configures bottom coordinate of focus window c, must <= hnum-2"] +pub type AF_TPOINT_C_R = crate::FieldReader; +#[doc = "Field `AF_TPOINT_C` writer - this field configures bottom coordinate of focus window c, must <= hnum-2"] +pub type AF_TPOINT_C_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures right coordinate of focus window c, must <= hnum-2"] + #[inline(always)] + pub fn af_bpoint_c(&self) -> AF_BPOINT_C_R { + AF_BPOINT_C_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures bottom coordinate of focus window c, must <= hnum-2"] + #[inline(always)] + pub fn af_tpoint_c(&self) -> AF_TPOINT_C_R { + AF_TPOINT_C_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AF_VSCALE_C") + .field( + "af_bpoint_c", + &format_args!("{}", self.af_bpoint_c().bits()), + ) + .field( + "af_tpoint_c", + &format_args!("{}", self.af_tpoint_c().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures right coordinate of focus window c, must <= hnum-2"] + #[inline(always)] + #[must_use] + pub fn af_bpoint_c(&mut self) -> AF_BPOINT_C_W { + AF_BPOINT_C_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures bottom coordinate of focus window c, must <= hnum-2"] + #[inline(always)] + #[must_use] + pub fn af_tpoint_c(&mut self) -> AF_TPOINT_C_W { + AF_TPOINT_C_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "v-scale of af window c register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_vscale_c::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`af_vscale_c::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AF_VSCALE_C_SPEC; +impl crate::RegisterSpec for AF_VSCALE_C_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`af_vscale_c::R`](R) reader structure"] +impl crate::Readable for AF_VSCALE_C_SPEC {} +#[doc = "`write(|w| ..)` method takes [`af_vscale_c::W`](W) writer structure"] +impl crate::Writable for AF_VSCALE_C_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AF_VSCALE_C to value 0x0001_0080"] +impl crate::Resettable for AF_VSCALE_C_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0080; +} diff --git a/esp32p4/src/isp/awb0_acc_b.rs b/esp32p4/src/isp/awb0_acc_b.rs new file mode 100644 index 0000000000..435560ce29 --- /dev/null +++ b/esp32p4/src/isp/awb0_acc_b.rs @@ -0,0 +1,36 @@ +#[doc = "Register `AWB0_ACC_B` reader"] +pub type R = crate::R; +#[doc = "Field `AWB0_ACC_B` reader - this field represents accumulate of channel b of all white point of algo0"] +pub type AWB0_ACC_B_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - this field represents accumulate of channel b of all white point of algo0"] + #[inline(always)] + pub fn awb0_acc_b(&self) -> AWB0_ACC_B_R { + AWB0_ACC_B_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AWB0_ACC_B") + .field("awb0_acc_b", &format_args!("{}", self.awb0_acc_b().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of accumulate of b channel of all white points\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_acc_b::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AWB0_ACC_B_SPEC; +impl crate::RegisterSpec for AWB0_ACC_B_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`awb0_acc_b::R`](R) reader structure"] +impl crate::Readable for AWB0_ACC_B_SPEC {} +#[doc = "`reset()` method sets AWB0_ACC_B to value 0"] +impl crate::Resettable for AWB0_ACC_B_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/awb0_acc_g.rs b/esp32p4/src/isp/awb0_acc_g.rs new file mode 100644 index 0000000000..e73229a54f --- /dev/null +++ b/esp32p4/src/isp/awb0_acc_g.rs @@ -0,0 +1,36 @@ +#[doc = "Register `AWB0_ACC_G` reader"] +pub type R = crate::R; +#[doc = "Field `AWB0_ACC_G` reader - this field represents accumulate of channel g of all white point of algo0"] +pub type AWB0_ACC_G_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - this field represents accumulate of channel g of all white point of algo0"] + #[inline(always)] + pub fn awb0_acc_g(&self) -> AWB0_ACC_G_R { + AWB0_ACC_G_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AWB0_ACC_G") + .field("awb0_acc_g", &format_args!("{}", self.awb0_acc_g().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of accumulate of g channel of all white points\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_acc_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AWB0_ACC_G_SPEC; +impl crate::RegisterSpec for AWB0_ACC_G_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`awb0_acc_g::R`](R) reader structure"] +impl crate::Readable for AWB0_ACC_G_SPEC {} +#[doc = "`reset()` method sets AWB0_ACC_G to value 0"] +impl crate::Resettable for AWB0_ACC_G_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/awb0_acc_r.rs b/esp32p4/src/isp/awb0_acc_r.rs new file mode 100644 index 0000000000..cb04b1f70a --- /dev/null +++ b/esp32p4/src/isp/awb0_acc_r.rs @@ -0,0 +1,36 @@ +#[doc = "Register `AWB0_ACC_R` reader"] +pub type R = crate::R; +#[doc = "Field `AWB0_ACC_R` reader - this field represents accumulate of channel r of all white point of algo0"] +pub type AWB0_ACC_R_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - this field represents accumulate of channel r of all white point of algo0"] + #[inline(always)] + pub fn awb0_acc_r(&self) -> AWB0_ACC_R_R { + AWB0_ACC_R_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AWB0_ACC_R") + .field("awb0_acc_r", &format_args!("{}", self.awb0_acc_r().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of accumulate of r channel of all white points\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_acc_r::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AWB0_ACC_R_SPEC; +impl crate::RegisterSpec for AWB0_ACC_R_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`awb0_acc_r::R`](R) reader structure"] +impl crate::Readable for AWB0_ACC_R_SPEC {} +#[doc = "`reset()` method sets AWB0_ACC_R to value 0"] +impl crate::Resettable for AWB0_ACC_R_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/awb0_white_cnt.rs b/esp32p4/src/isp/awb0_white_cnt.rs new file mode 100644 index 0000000000..11e39a30d1 --- /dev/null +++ b/esp32p4/src/isp/awb0_white_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `AWB0_WHITE_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `AWB0_WHITE_CNT` reader - this field configures number of white point detected of algo0"] +pub type AWB0_WHITE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - this field configures number of white point detected of algo0"] + #[inline(always)] + pub fn awb0_white_cnt(&self) -> AWB0_WHITE_CNT_R { + AWB0_WHITE_CNT_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AWB0_WHITE_CNT") + .field( + "awb0_white_cnt", + &format_args!("{}", self.awb0_white_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of awb white point number\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_white_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AWB0_WHITE_CNT_SPEC; +impl crate::RegisterSpec for AWB0_WHITE_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`awb0_white_cnt::R`](R) reader structure"] +impl crate::Readable for AWB0_WHITE_CNT_SPEC {} +#[doc = "`reset()` method sets AWB0_WHITE_CNT to value 0"] +impl crate::Resettable for AWB0_WHITE_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/awb_hscale.rs b/esp32p4/src/isp/awb_hscale.rs new file mode 100644 index 0000000000..68a9c603a8 --- /dev/null +++ b/esp32p4/src/isp/awb_hscale.rs @@ -0,0 +1,79 @@ +#[doc = "Register `AWB_HSCALE` reader"] +pub type R = crate::R; +#[doc = "Register `AWB_HSCALE` writer"] +pub type W = crate::W; +#[doc = "Field `AWB_RPOINT` reader - this field configures awb window right coordinate"] +pub type AWB_RPOINT_R = crate::FieldReader; +#[doc = "Field `AWB_RPOINT` writer - this field configures awb window right coordinate"] +pub type AWB_RPOINT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `AWB_LPOINT` reader - this field configures awb window left coordinate"] +pub type AWB_LPOINT_R = crate::FieldReader; +#[doc = "Field `AWB_LPOINT` writer - this field configures awb window left coordinate"] +pub type AWB_LPOINT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures awb window right coordinate"] + #[inline(always)] + pub fn awb_rpoint(&self) -> AWB_RPOINT_R { + AWB_RPOINT_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures awb window left coordinate"] + #[inline(always)] + pub fn awb_lpoint(&self) -> AWB_LPOINT_R { + AWB_LPOINT_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AWB_HSCALE") + .field("awb_rpoint", &format_args!("{}", self.awb_rpoint().bits())) + .field("awb_lpoint", &format_args!("{}", self.awb_lpoint().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures awb window right coordinate"] + #[inline(always)] + #[must_use] + pub fn awb_rpoint(&mut self) -> AWB_RPOINT_W { + AWB_RPOINT_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures awb window left coordinate"] + #[inline(always)] + #[must_use] + pub fn awb_lpoint(&mut self) -> AWB_LPOINT_W { + AWB_LPOINT_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "h-scale of awb window\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_hscale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_hscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AWB_HSCALE_SPEC; +impl crate::RegisterSpec for AWB_HSCALE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`awb_hscale::R`](R) reader structure"] +impl crate::Readable for AWB_HSCALE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`awb_hscale::W`](W) writer structure"] +impl crate::Writable for AWB_HSCALE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AWB_HSCALE to value 0x077f"] +impl crate::Resettable for AWB_HSCALE_SPEC { + const RESET_VALUE: Self::Ux = 0x077f; +} diff --git a/esp32p4/src/isp/awb_mode.rs b/esp32p4/src/isp/awb_mode.rs new file mode 100644 index 0000000000..34f594c92a --- /dev/null +++ b/esp32p4/src/isp/awb_mode.rs @@ -0,0 +1,79 @@ +#[doc = "Register `AWB_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `AWB_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `AWB_MODE` reader - this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel algo1. 11: sel both algo0 and algo1"] +pub type AWB_MODE_R = crate::FieldReader; +#[doc = "Field `AWB_MODE` writer - this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel algo1. 11: sel both algo0 and algo1"] +pub type AWB_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `AWB_SAMPLE` reader - this bit configures awb sample location, 0:before ccm, 1:after ccm"] +pub type AWB_SAMPLE_R = crate::BitReader; +#[doc = "Field `AWB_SAMPLE` writer - this bit configures awb sample location, 0:before ccm, 1:after ccm"] +pub type AWB_SAMPLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel algo1. 11: sel both algo0 and algo1"] + #[inline(always)] + pub fn awb_mode(&self) -> AWB_MODE_R { + AWB_MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 4 - this bit configures awb sample location, 0:before ccm, 1:after ccm"] + #[inline(always)] + pub fn awb_sample(&self) -> AWB_SAMPLE_R { + AWB_SAMPLE_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AWB_MODE") + .field("awb_mode", &format_args!("{}", self.awb_mode().bits())) + .field("awb_sample", &format_args!("{}", self.awb_sample().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel algo1. 11: sel both algo0 and algo1"] + #[inline(always)] + #[must_use] + pub fn awb_mode(&mut self) -> AWB_MODE_W { + AWB_MODE_W::new(self, 0) + } + #[doc = "Bit 4 - this bit configures awb sample location, 0:before ccm, 1:after ccm"] + #[inline(always)] + #[must_use] + pub fn awb_sample(&mut self) -> AWB_SAMPLE_W { + AWB_SAMPLE_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "awb mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AWB_MODE_SPEC; +impl crate::RegisterSpec for AWB_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`awb_mode::R`](R) reader structure"] +impl crate::Readable for AWB_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`awb_mode::W`](W) writer structure"] +impl crate::Writable for AWB_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AWB_MODE to value 0x03"] +impl crate::Resettable for AWB_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/isp/awb_th_bg.rs b/esp32p4/src/isp/awb_th_bg.rs new file mode 100644 index 0000000000..60715bd5b8 --- /dev/null +++ b/esp32p4/src/isp/awb_th_bg.rs @@ -0,0 +1,79 @@ +#[doc = "Register `AWB_TH_BG` reader"] +pub type R = crate::R; +#[doc = "Register `AWB_TH_BG` writer"] +pub type W = crate::W; +#[doc = "Field `AWB_MIN_BG` reader - this field configures lower threshold of b/g, 2bit integer and 8bit fraction"] +pub type AWB_MIN_BG_R = crate::FieldReader; +#[doc = "Field `AWB_MIN_BG` writer - this field configures lower threshold of b/g, 2bit integer and 8bit fraction"] +pub type AWB_MIN_BG_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `AWB_MAX_BG` reader - this field configures upper threshold of b/g, 2bit integer and 8bit fraction"] +pub type AWB_MAX_BG_R = crate::FieldReader; +#[doc = "Field `AWB_MAX_BG` writer - this field configures upper threshold of b/g, 2bit integer and 8bit fraction"] +pub type AWB_MAX_BG_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - this field configures lower threshold of b/g, 2bit integer and 8bit fraction"] + #[inline(always)] + pub fn awb_min_bg(&self) -> AWB_MIN_BG_R { + AWB_MIN_BG_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:25 - this field configures upper threshold of b/g, 2bit integer and 8bit fraction"] + #[inline(always)] + pub fn awb_max_bg(&self) -> AWB_MAX_BG_R { + AWB_MAX_BG_R::new(((self.bits >> 16) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AWB_TH_BG") + .field("awb_min_bg", &format_args!("{}", self.awb_min_bg().bits())) + .field("awb_max_bg", &format_args!("{}", self.awb_max_bg().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - this field configures lower threshold of b/g, 2bit integer and 8bit fraction"] + #[inline(always)] + #[must_use] + pub fn awb_min_bg(&mut self) -> AWB_MIN_BG_W { + AWB_MIN_BG_W::new(self, 0) + } + #[doc = "Bits 16:25 - this field configures upper threshold of b/g, 2bit integer and 8bit fraction"] + #[inline(always)] + #[must_use] + pub fn awb_max_bg(&mut self) -> AWB_MAX_BG_W { + AWB_MAX_BG_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "awb b/g threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_th_bg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_th_bg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AWB_TH_BG_SPEC; +impl crate::RegisterSpec for AWB_TH_BG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`awb_th_bg::R`](R) reader structure"] +impl crate::Readable for AWB_TH_BG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`awb_th_bg::W`](W) writer structure"] +impl crate::Writable for AWB_TH_BG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AWB_TH_BG to value 0x03ff_0000"] +impl crate::Resettable for AWB_TH_BG_SPEC { + const RESET_VALUE: Self::Ux = 0x03ff_0000; +} diff --git a/esp32p4/src/isp/awb_th_lum.rs b/esp32p4/src/isp/awb_th_lum.rs new file mode 100644 index 0000000000..d4b4140511 --- /dev/null +++ b/esp32p4/src/isp/awb_th_lum.rs @@ -0,0 +1,85 @@ +#[doc = "Register `AWB_TH_LUM` reader"] +pub type R = crate::R; +#[doc = "Register `AWB_TH_LUM` writer"] +pub type W = crate::W; +#[doc = "Field `AWB_MIN_LUM` reader - this field configures lower threshold of r+g+b"] +pub type AWB_MIN_LUM_R = crate::FieldReader; +#[doc = "Field `AWB_MIN_LUM` writer - this field configures lower threshold of r+g+b"] +pub type AWB_MIN_LUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `AWB_MAX_LUM` reader - this field configures upper threshold of r+g+b"] +pub type AWB_MAX_LUM_R = crate::FieldReader; +#[doc = "Field `AWB_MAX_LUM` writer - this field configures upper threshold of r+g+b"] +pub type AWB_MAX_LUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - this field configures lower threshold of r+g+b"] + #[inline(always)] + pub fn awb_min_lum(&self) -> AWB_MIN_LUM_R { + AWB_MIN_LUM_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:25 - this field configures upper threshold of r+g+b"] + #[inline(always)] + pub fn awb_max_lum(&self) -> AWB_MAX_LUM_R { + AWB_MAX_LUM_R::new(((self.bits >> 16) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AWB_TH_LUM") + .field( + "awb_min_lum", + &format_args!("{}", self.awb_min_lum().bits()), + ) + .field( + "awb_max_lum", + &format_args!("{}", self.awb_max_lum().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - this field configures lower threshold of r+g+b"] + #[inline(always)] + #[must_use] + pub fn awb_min_lum(&mut self) -> AWB_MIN_LUM_W { + AWB_MIN_LUM_W::new(self, 0) + } + #[doc = "Bits 16:25 - this field configures upper threshold of r+g+b"] + #[inline(always)] + #[must_use] + pub fn awb_max_lum(&mut self) -> AWB_MAX_LUM_W { + AWB_MAX_LUM_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "awb lum threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_th_lum::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_th_lum::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AWB_TH_LUM_SPEC; +impl crate::RegisterSpec for AWB_TH_LUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`awb_th_lum::R`](R) reader structure"] +impl crate::Readable for AWB_TH_LUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`awb_th_lum::W`](W) writer structure"] +impl crate::Writable for AWB_TH_LUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AWB_TH_LUM to value 0x02fd_0000"] +impl crate::Resettable for AWB_TH_LUM_SPEC { + const RESET_VALUE: Self::Ux = 0x02fd_0000; +} diff --git a/esp32p4/src/isp/awb_th_rg.rs b/esp32p4/src/isp/awb_th_rg.rs new file mode 100644 index 0000000000..26673cdb0f --- /dev/null +++ b/esp32p4/src/isp/awb_th_rg.rs @@ -0,0 +1,79 @@ +#[doc = "Register `AWB_TH_RG` reader"] +pub type R = crate::R; +#[doc = "Register `AWB_TH_RG` writer"] +pub type W = crate::W; +#[doc = "Field `AWB_MIN_RG` reader - this field configures lower threshold of r/g, 2bit integer and 8bit fraction"] +pub type AWB_MIN_RG_R = crate::FieldReader; +#[doc = "Field `AWB_MIN_RG` writer - this field configures lower threshold of r/g, 2bit integer and 8bit fraction"] +pub type AWB_MIN_RG_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `AWB_MAX_RG` reader - this field configures upper threshold of r/g, 2bit integer and 8bit fraction"] +pub type AWB_MAX_RG_R = crate::FieldReader; +#[doc = "Field `AWB_MAX_RG` writer - this field configures upper threshold of r/g, 2bit integer and 8bit fraction"] +pub type AWB_MAX_RG_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - this field configures lower threshold of r/g, 2bit integer and 8bit fraction"] + #[inline(always)] + pub fn awb_min_rg(&self) -> AWB_MIN_RG_R { + AWB_MIN_RG_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:25 - this field configures upper threshold of r/g, 2bit integer and 8bit fraction"] + #[inline(always)] + pub fn awb_max_rg(&self) -> AWB_MAX_RG_R { + AWB_MAX_RG_R::new(((self.bits >> 16) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AWB_TH_RG") + .field("awb_min_rg", &format_args!("{}", self.awb_min_rg().bits())) + .field("awb_max_rg", &format_args!("{}", self.awb_max_rg().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - this field configures lower threshold of r/g, 2bit integer and 8bit fraction"] + #[inline(always)] + #[must_use] + pub fn awb_min_rg(&mut self) -> AWB_MIN_RG_W { + AWB_MIN_RG_W::new(self, 0) + } + #[doc = "Bits 16:25 - this field configures upper threshold of r/g, 2bit integer and 8bit fraction"] + #[inline(always)] + #[must_use] + pub fn awb_max_rg(&mut self) -> AWB_MAX_RG_W { + AWB_MAX_RG_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "awb r/g threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_th_rg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_th_rg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AWB_TH_RG_SPEC; +impl crate::RegisterSpec for AWB_TH_RG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`awb_th_rg::R`](R) reader structure"] +impl crate::Readable for AWB_TH_RG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`awb_th_rg::W`](W) writer structure"] +impl crate::Writable for AWB_TH_RG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AWB_TH_RG to value 0x03ff_0000"] +impl crate::Resettable for AWB_TH_RG_SPEC { + const RESET_VALUE: Self::Ux = 0x03ff_0000; +} diff --git a/esp32p4/src/isp/awb_vscale.rs b/esp32p4/src/isp/awb_vscale.rs new file mode 100644 index 0000000000..48f5f5f44b --- /dev/null +++ b/esp32p4/src/isp/awb_vscale.rs @@ -0,0 +1,79 @@ +#[doc = "Register `AWB_VSCALE` reader"] +pub type R = crate::R; +#[doc = "Register `AWB_VSCALE` writer"] +pub type W = crate::W; +#[doc = "Field `AWB_BPOINT` reader - this field configures awb window bottom coordinate"] +pub type AWB_BPOINT_R = crate::FieldReader; +#[doc = "Field `AWB_BPOINT` writer - this field configures awb window bottom coordinate"] +pub type AWB_BPOINT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `AWB_TPOINT` reader - this field configures awb window top coordinate"] +pub type AWB_TPOINT_R = crate::FieldReader; +#[doc = "Field `AWB_TPOINT` writer - this field configures awb window top coordinate"] +pub type AWB_TPOINT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures awb window bottom coordinate"] + #[inline(always)] + pub fn awb_bpoint(&self) -> AWB_BPOINT_R { + AWB_BPOINT_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures awb window top coordinate"] + #[inline(always)] + pub fn awb_tpoint(&self) -> AWB_TPOINT_R { + AWB_TPOINT_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AWB_VSCALE") + .field("awb_bpoint", &format_args!("{}", self.awb_bpoint().bits())) + .field("awb_tpoint", &format_args!("{}", self.awb_tpoint().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures awb window bottom coordinate"] + #[inline(always)] + #[must_use] + pub fn awb_bpoint(&mut self) -> AWB_BPOINT_W { + AWB_BPOINT_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures awb window top coordinate"] + #[inline(always)] + #[must_use] + pub fn awb_tpoint(&mut self) -> AWB_TPOINT_W { + AWB_TPOINT_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "v-scale of awb window\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb_vscale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`awb_vscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AWB_VSCALE_SPEC; +impl crate::RegisterSpec for AWB_VSCALE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`awb_vscale::R`](R) reader structure"] +impl crate::Readable for AWB_VSCALE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`awb_vscale::W`](W) writer structure"] +impl crate::Writable for AWB_VSCALE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AWB_VSCALE to value 0x0437"] +impl crate::Resettable for AWB_VSCALE_SPEC { + const RESET_VALUE: Self::Ux = 0x0437; +} diff --git a/esp32p4/src/isp/bf_gau0.rs b/esp32p4/src/isp/bf_gau0.rs new file mode 100644 index 0000000000..9ceb0114ea --- /dev/null +++ b/esp32p4/src/isp/bf_gau0.rs @@ -0,0 +1,199 @@ +#[doc = "Register `BF_GAU0` reader"] +pub type R = crate::R; +#[doc = "Register `BF_GAU0` writer"] +pub type W = crate::W; +#[doc = "Field `GAU_TEMPLATE21` reader - this field configures index 21 of gausian template"] +pub type GAU_TEMPLATE21_R = crate::FieldReader; +#[doc = "Field `GAU_TEMPLATE21` writer - this field configures index 21 of gausian template"] +pub type GAU_TEMPLATE21_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `GAU_TEMPLATE20` reader - this field configures index 20 of gausian template"] +pub type GAU_TEMPLATE20_R = crate::FieldReader; +#[doc = "Field `GAU_TEMPLATE20` writer - this field configures index 20 of gausian template"] +pub type GAU_TEMPLATE20_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `GAU_TEMPLATE12` reader - this field configures index 12 of gausian template"] +pub type GAU_TEMPLATE12_R = crate::FieldReader; +#[doc = "Field `GAU_TEMPLATE12` writer - this field configures index 12 of gausian template"] +pub type GAU_TEMPLATE12_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `GAU_TEMPLATE11` reader - this field configures index 11 of gausian template"] +pub type GAU_TEMPLATE11_R = crate::FieldReader; +#[doc = "Field `GAU_TEMPLATE11` writer - this field configures index 11 of gausian template"] +pub type GAU_TEMPLATE11_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `GAU_TEMPLATE10` reader - this field configures index 10 of gausian template"] +pub type GAU_TEMPLATE10_R = crate::FieldReader; +#[doc = "Field `GAU_TEMPLATE10` writer - this field configures index 10 of gausian template"] +pub type GAU_TEMPLATE10_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `GAU_TEMPLATE02` reader - this field configures index 02 of gausian template"] +pub type GAU_TEMPLATE02_R = crate::FieldReader; +#[doc = "Field `GAU_TEMPLATE02` writer - this field configures index 02 of gausian template"] +pub type GAU_TEMPLATE02_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `GAU_TEMPLATE01` reader - this field configures index 01 of gausian template"] +pub type GAU_TEMPLATE01_R = crate::FieldReader; +#[doc = "Field `GAU_TEMPLATE01` writer - this field configures index 01 of gausian template"] +pub type GAU_TEMPLATE01_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `GAU_TEMPLATE00` reader - this field configures index 00 of gausian template"] +pub type GAU_TEMPLATE00_R = crate::FieldReader; +#[doc = "Field `GAU_TEMPLATE00` writer - this field configures index 00 of gausian template"] +pub type GAU_TEMPLATE00_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - this field configures index 21 of gausian template"] + #[inline(always)] + pub fn gau_template21(&self) -> GAU_TEMPLATE21_R { + GAU_TEMPLATE21_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - this field configures index 20 of gausian template"] + #[inline(always)] + pub fn gau_template20(&self) -> GAU_TEMPLATE20_R { + GAU_TEMPLATE20_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - this field configures index 12 of gausian template"] + #[inline(always)] + pub fn gau_template12(&self) -> GAU_TEMPLATE12_R { + GAU_TEMPLATE12_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - this field configures index 11 of gausian template"] + #[inline(always)] + pub fn gau_template11(&self) -> GAU_TEMPLATE11_R { + GAU_TEMPLATE11_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - this field configures index 10 of gausian template"] + #[inline(always)] + pub fn gau_template10(&self) -> GAU_TEMPLATE10_R { + GAU_TEMPLATE10_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - this field configures index 02 of gausian template"] + #[inline(always)] + pub fn gau_template02(&self) -> GAU_TEMPLATE02_R { + GAU_TEMPLATE02_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - this field configures index 01 of gausian template"] + #[inline(always)] + pub fn gau_template01(&self) -> GAU_TEMPLATE01_R { + GAU_TEMPLATE01_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - this field configures index 00 of gausian template"] + #[inline(always)] + pub fn gau_template00(&self) -> GAU_TEMPLATE00_R { + GAU_TEMPLATE00_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BF_GAU0") + .field( + "gau_template21", + &format_args!("{}", self.gau_template21().bits()), + ) + .field( + "gau_template20", + &format_args!("{}", self.gau_template20().bits()), + ) + .field( + "gau_template12", + &format_args!("{}", self.gau_template12().bits()), + ) + .field( + "gau_template11", + &format_args!("{}", self.gau_template11().bits()), + ) + .field( + "gau_template10", + &format_args!("{}", self.gau_template10().bits()), + ) + .field( + "gau_template02", + &format_args!("{}", self.gau_template02().bits()), + ) + .field( + "gau_template01", + &format_args!("{}", self.gau_template01().bits()), + ) + .field( + "gau_template00", + &format_args!("{}", self.gau_template00().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - this field configures index 21 of gausian template"] + #[inline(always)] + #[must_use] + pub fn gau_template21(&mut self) -> GAU_TEMPLATE21_W { + GAU_TEMPLATE21_W::new(self, 0) + } + #[doc = "Bits 4:7 - this field configures index 20 of gausian template"] + #[inline(always)] + #[must_use] + pub fn gau_template20(&mut self) -> GAU_TEMPLATE20_W { + GAU_TEMPLATE20_W::new(self, 4) + } + #[doc = "Bits 8:11 - this field configures index 12 of gausian template"] + #[inline(always)] + #[must_use] + pub fn gau_template12(&mut self) -> GAU_TEMPLATE12_W { + GAU_TEMPLATE12_W::new(self, 8) + } + #[doc = "Bits 12:15 - this field configures index 11 of gausian template"] + #[inline(always)] + #[must_use] + pub fn gau_template11(&mut self) -> GAU_TEMPLATE11_W { + GAU_TEMPLATE11_W::new(self, 12) + } + #[doc = "Bits 16:19 - this field configures index 10 of gausian template"] + #[inline(always)] + #[must_use] + pub fn gau_template10(&mut self) -> GAU_TEMPLATE10_W { + GAU_TEMPLATE10_W::new(self, 16) + } + #[doc = "Bits 20:23 - this field configures index 02 of gausian template"] + #[inline(always)] + #[must_use] + pub fn gau_template02(&mut self) -> GAU_TEMPLATE02_W { + GAU_TEMPLATE02_W::new(self, 20) + } + #[doc = "Bits 24:27 - this field configures index 01 of gausian template"] + #[inline(always)] + #[must_use] + pub fn gau_template01(&mut self) -> GAU_TEMPLATE01_W { + GAU_TEMPLATE01_W::new(self, 24) + } + #[doc = "Bits 28:31 - this field configures index 00 of gausian template"] + #[inline(always)] + #[must_use] + pub fn gau_template00(&mut self) -> GAU_TEMPLATE00_W { + GAU_TEMPLATE00_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "bf gau template register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bf_gau0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bf_gau0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BF_GAU0_SPEC; +impl crate::RegisterSpec for BF_GAU0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bf_gau0::R`](R) reader structure"] +impl crate::Readable for BF_GAU0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bf_gau0::W`](W) writer structure"] +impl crate::Writable for BF_GAU0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BF_GAU0 to value 0xffff_ffff"] +impl crate::Resettable for BF_GAU0_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/isp/bf_gau1.rs b/esp32p4/src/isp/bf_gau1.rs new file mode 100644 index 0000000000..1a497002a2 --- /dev/null +++ b/esp32p4/src/isp/bf_gau1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `BF_GAU1` reader"] +pub type R = crate::R; +#[doc = "Register `BF_GAU1` writer"] +pub type W = crate::W; +#[doc = "Field `GAU_TEMPLATE22` reader - this field configures index 22 of gausian template"] +pub type GAU_TEMPLATE22_R = crate::FieldReader; +#[doc = "Field `GAU_TEMPLATE22` writer - this field configures index 22 of gausian template"] +pub type GAU_TEMPLATE22_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - this field configures index 22 of gausian template"] + #[inline(always)] + pub fn gau_template22(&self) -> GAU_TEMPLATE22_R { + GAU_TEMPLATE22_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BF_GAU1") + .field( + "gau_template22", + &format_args!("{}", self.gau_template22().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - this field configures index 22 of gausian template"] + #[inline(always)] + #[must_use] + pub fn gau_template22(&mut self) -> GAU_TEMPLATE22_W { + GAU_TEMPLATE22_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "bf gau template register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bf_gau1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bf_gau1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BF_GAU1_SPEC; +impl crate::RegisterSpec for BF_GAU1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bf_gau1::R`](R) reader structure"] +impl crate::Readable for BF_GAU1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bf_gau1::W`](W) writer structure"] +impl crate::Writable for BF_GAU1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BF_GAU1 to value 0x0f"] +impl crate::Resettable for BF_GAU1_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/isp/bf_matrix_ctrl.rs b/esp32p4/src/isp/bf_matrix_ctrl.rs new file mode 100644 index 0000000000..62c28cda7f --- /dev/null +++ b/esp32p4/src/isp/bf_matrix_ctrl.rs @@ -0,0 +1,123 @@ +#[doc = "Register `BF_MATRIX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `BF_MATRIX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `BF_TAIL_PIXEN_PULSE_TL` reader - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function"] +pub type BF_TAIL_PIXEN_PULSE_TL_R = crate::FieldReader; +#[doc = "Field `BF_TAIL_PIXEN_PULSE_TL` writer - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function"] +pub type BF_TAIL_PIXEN_PULSE_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BF_TAIL_PIXEN_PULSE_TH` reader - matrix tail pixen high level threshold, must < hnum-1, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function"] +pub type BF_TAIL_PIXEN_PULSE_TH_R = crate::FieldReader; +#[doc = "Field `BF_TAIL_PIXEN_PULSE_TH` writer - matrix tail pixen high level threshold, must < hnum-1, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function"] +pub type BF_TAIL_PIXEN_PULSE_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BF_PADDING_DATA` reader - this field configures bf matrix padding data"] +pub type BF_PADDING_DATA_R = crate::FieldReader; +#[doc = "Field `BF_PADDING_DATA` writer - this field configures bf matrix padding data"] +pub type BF_PADDING_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BF_PADDING_MODE` reader - this bit configures the padding mode of bf matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] +pub type BF_PADDING_MODE_R = crate::BitReader; +#[doc = "Field `BF_PADDING_MODE` writer - this bit configures the padding mode of bf matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] +pub type BF_PADDING_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + pub fn bf_tail_pixen_pulse_tl(&self) -> BF_TAIL_PIXEN_PULSE_TL_R { + BF_TAIL_PIXEN_PULSE_TL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - matrix tail pixen high level threshold, must < hnum-1, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + pub fn bf_tail_pixen_pulse_th(&self) -> BF_TAIL_PIXEN_PULSE_TH_R { + BF_TAIL_PIXEN_PULSE_TH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures bf matrix padding data"] + #[inline(always)] + pub fn bf_padding_data(&self) -> BF_PADDING_DATA_R { + BF_PADDING_DATA_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - this bit configures the padding mode of bf matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] + #[inline(always)] + pub fn bf_padding_mode(&self) -> BF_PADDING_MODE_R { + BF_PADDING_MODE_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BF_MATRIX_CTRL") + .field( + "bf_tail_pixen_pulse_tl", + &format_args!("{}", self.bf_tail_pixen_pulse_tl().bits()), + ) + .field( + "bf_tail_pixen_pulse_th", + &format_args!("{}", self.bf_tail_pixen_pulse_th().bits()), + ) + .field( + "bf_padding_data", + &format_args!("{}", self.bf_padding_data().bits()), + ) + .field( + "bf_padding_mode", + &format_args!("{}", self.bf_padding_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + #[must_use] + pub fn bf_tail_pixen_pulse_tl(&mut self) -> BF_TAIL_PIXEN_PULSE_TL_W { + BF_TAIL_PIXEN_PULSE_TL_W::new(self, 0) + } + #[doc = "Bits 8:15 - matrix tail pixen high level threshold, must < hnum-1, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + #[must_use] + pub fn bf_tail_pixen_pulse_th(&mut self) -> BF_TAIL_PIXEN_PULSE_TH_W { + BF_TAIL_PIXEN_PULSE_TH_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures bf matrix padding data"] + #[inline(always)] + #[must_use] + pub fn bf_padding_data(&mut self) -> BF_PADDING_DATA_W { + BF_PADDING_DATA_W::new(self, 16) + } + #[doc = "Bit 24 - this bit configures the padding mode of bf matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] + #[inline(always)] + #[must_use] + pub fn bf_padding_mode(&mut self) -> BF_PADDING_MODE_W { + BF_PADDING_MODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "bf pix2matrix ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bf_matrix_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bf_matrix_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BF_MATRIX_CTRL_SPEC; +impl crate::RegisterSpec for BF_MATRIX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bf_matrix_ctrl::R`](R) reader structure"] +impl crate::Readable for BF_MATRIX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bf_matrix_ctrl::W`](W) writer structure"] +impl crate::Writable for BF_MATRIX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BF_MATRIX_CTRL to value 0"] +impl crate::Resettable for BF_MATRIX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/bf_sigma.rs b/esp32p4/src/isp/bf_sigma.rs new file mode 100644 index 0000000000..bb42fbb4f3 --- /dev/null +++ b/esp32p4/src/isp/bf_sigma.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BF_SIGMA` reader"] +pub type R = crate::R; +#[doc = "Register `BF_SIGMA` writer"] +pub type W = crate::W; +#[doc = "Field `SIGMA` reader - this field configures the bayer denoising level, valid data from 2 to 20"] +pub type SIGMA_R = crate::FieldReader; +#[doc = "Field `SIGMA` writer - this field configures the bayer denoising level, valid data from 2 to 20"] +pub type SIGMA_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - this field configures the bayer denoising level, valid data from 2 to 20"] + #[inline(always)] + pub fn sigma(&self) -> SIGMA_R { + SIGMA_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BF_SIGMA") + .field("sigma", &format_args!("{}", self.sigma().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - this field configures the bayer denoising level, valid data from 2 to 20"] + #[inline(always)] + #[must_use] + pub fn sigma(&mut self) -> SIGMA_W { + SIGMA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "bf denoising level control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bf_sigma::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bf_sigma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BF_SIGMA_SPEC; +impl crate::RegisterSpec for BF_SIGMA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bf_sigma::R`](R) reader structure"] +impl crate::Readable for BF_SIGMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bf_sigma::W`](W) writer structure"] +impl crate::Writable for BF_SIGMA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BF_SIGMA to value 0x02"] +impl crate::Resettable for BF_SIGMA_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/isp/blc_ctrl0.rs b/esp32p4/src/isp/blc_ctrl0.rs new file mode 100644 index 0000000000..8492415a46 --- /dev/null +++ b/esp32p4/src/isp/blc_ctrl0.rs @@ -0,0 +1,123 @@ +#[doc = "Register `BLC_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `BLC_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `BLC_R3_STRETCH` reader - this bit configures the stretch feature of bottom right channel. 0: stretch disable, 1: stretch enable"] +pub type BLC_R3_STRETCH_R = crate::BitReader; +#[doc = "Field `BLC_R3_STRETCH` writer - this bit configures the stretch feature of bottom right channel. 0: stretch disable, 1: stretch enable"] +pub type BLC_R3_STRETCH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLC_R2_STRETCH` reader - this bit configures the stretch feature of bottom left channel. 0: stretch disable, 1: stretch enable"] +pub type BLC_R2_STRETCH_R = crate::BitReader; +#[doc = "Field `BLC_R2_STRETCH` writer - this bit configures the stretch feature of bottom left channel. 0: stretch disable, 1: stretch enable"] +pub type BLC_R2_STRETCH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLC_R1_STRETCH` reader - this bit configures the stretch feature of top right channel. 0: stretch disable, 1: stretch enable"] +pub type BLC_R1_STRETCH_R = crate::BitReader; +#[doc = "Field `BLC_R1_STRETCH` writer - this bit configures the stretch feature of top right channel. 0: stretch disable, 1: stretch enable"] +pub type BLC_R1_STRETCH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLC_R0_STRETCH` reader - this bit configures the stretch feature of top left channel. 0: stretch disable, 1: stretch enable"] +pub type BLC_R0_STRETCH_R = crate::BitReader; +#[doc = "Field `BLC_R0_STRETCH` writer - this bit configures the stretch feature of top left channel. 0: stretch disable, 1: stretch enable"] +pub type BLC_R0_STRETCH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - this bit configures the stretch feature of bottom right channel. 0: stretch disable, 1: stretch enable"] + #[inline(always)] + pub fn blc_r3_stretch(&self) -> BLC_R3_STRETCH_R { + BLC_R3_STRETCH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - this bit configures the stretch feature of bottom left channel. 0: stretch disable, 1: stretch enable"] + #[inline(always)] + pub fn blc_r2_stretch(&self) -> BLC_R2_STRETCH_R { + BLC_R2_STRETCH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - this bit configures the stretch feature of top right channel. 0: stretch disable, 1: stretch enable"] + #[inline(always)] + pub fn blc_r1_stretch(&self) -> BLC_R1_STRETCH_R { + BLC_R1_STRETCH_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - this bit configures the stretch feature of top left channel. 0: stretch disable, 1: stretch enable"] + #[inline(always)] + pub fn blc_r0_stretch(&self) -> BLC_R0_STRETCH_R { + BLC_R0_STRETCH_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLC_CTRL0") + .field( + "blc_r3_stretch", + &format_args!("{}", self.blc_r3_stretch().bit()), + ) + .field( + "blc_r2_stretch", + &format_args!("{}", self.blc_r2_stretch().bit()), + ) + .field( + "blc_r1_stretch", + &format_args!("{}", self.blc_r1_stretch().bit()), + ) + .field( + "blc_r0_stretch", + &format_args!("{}", self.blc_r0_stretch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures the stretch feature of bottom right channel. 0: stretch disable, 1: stretch enable"] + #[inline(always)] + #[must_use] + pub fn blc_r3_stretch(&mut self) -> BLC_R3_STRETCH_W { + BLC_R3_STRETCH_W::new(self, 0) + } + #[doc = "Bit 1 - this bit configures the stretch feature of bottom left channel. 0: stretch disable, 1: stretch enable"] + #[inline(always)] + #[must_use] + pub fn blc_r2_stretch(&mut self) -> BLC_R2_STRETCH_W { + BLC_R2_STRETCH_W::new(self, 1) + } + #[doc = "Bit 2 - this bit configures the stretch feature of top right channel. 0: stretch disable, 1: stretch enable"] + #[inline(always)] + #[must_use] + pub fn blc_r1_stretch(&mut self) -> BLC_R1_STRETCH_W { + BLC_R1_STRETCH_W::new(self, 2) + } + #[doc = "Bit 3 - this bit configures the stretch feature of top left channel. 0: stretch disable, 1: stretch enable"] + #[inline(always)] + #[must_use] + pub fn blc_r0_stretch(&mut self) -> BLC_R0_STRETCH_W { + BLC_R0_STRETCH_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "blc stretch control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blc_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blc_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLC_CTRL0_SPEC; +impl crate::RegisterSpec for BLC_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blc_ctrl0::R`](R) reader structure"] +impl crate::Readable for BLC_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blc_ctrl0::W`](W) writer structure"] +impl crate::Writable for BLC_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLC_CTRL0 to value 0"] +impl crate::Resettable for BLC_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/blc_ctrl1.rs b/esp32p4/src/isp/blc_ctrl1.rs new file mode 100644 index 0000000000..bef073fb4b --- /dev/null +++ b/esp32p4/src/isp/blc_ctrl1.rs @@ -0,0 +1,142 @@ +#[doc = "Register `BLC_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `BLC_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `BLC_WINDOW_TOP` reader - this field configures blc average calculation window top"] +pub type BLC_WINDOW_TOP_R = crate::FieldReader; +#[doc = "Field `BLC_WINDOW_TOP` writer - this field configures blc average calculation window top"] +pub type BLC_WINDOW_TOP_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `BLC_WINDOW_LEFT` reader - this field configures blc average calculation window left"] +pub type BLC_WINDOW_LEFT_R = crate::FieldReader; +#[doc = "Field `BLC_WINDOW_LEFT` writer - this field configures blc average calculation window left"] +pub type BLC_WINDOW_LEFT_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `BLC_WINDOW_VNUM` reader - this field configures blc average calculation window vnum"] +pub type BLC_WINDOW_VNUM_R = crate::FieldReader; +#[doc = "Field `BLC_WINDOW_VNUM` writer - this field configures blc average calculation window vnum"] +pub type BLC_WINDOW_VNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `BLC_WINDOW_HNUM` reader - this field configures blc average calculation window hnum"] +pub type BLC_WINDOW_HNUM_R = crate::FieldReader; +#[doc = "Field `BLC_WINDOW_HNUM` writer - this field configures blc average calculation window hnum"] +pub type BLC_WINDOW_HNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `BLC_FILTER_EN` reader - this bit configures enable blc average input filter. 0: disable, 1: enable"] +pub type BLC_FILTER_EN_R = crate::BitReader; +#[doc = "Field `BLC_FILTER_EN` writer - this bit configures enable blc average input filter. 0: disable, 1: enable"] +pub type BLC_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:10 - this field configures blc average calculation window top"] + #[inline(always)] + pub fn blc_window_top(&self) -> BLC_WINDOW_TOP_R { + BLC_WINDOW_TOP_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 11:21 - this field configures blc average calculation window left"] + #[inline(always)] + pub fn blc_window_left(&self) -> BLC_WINDOW_LEFT_R { + BLC_WINDOW_LEFT_R::new(((self.bits >> 11) & 0x07ff) as u16) + } + #[doc = "Bits 22:25 - this field configures blc average calculation window vnum"] + #[inline(always)] + pub fn blc_window_vnum(&self) -> BLC_WINDOW_VNUM_R { + BLC_WINDOW_VNUM_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:29 - this field configures blc average calculation window hnum"] + #[inline(always)] + pub fn blc_window_hnum(&self) -> BLC_WINDOW_HNUM_R { + BLC_WINDOW_HNUM_R::new(((self.bits >> 26) & 0x0f) as u8) + } + #[doc = "Bit 30 - this bit configures enable blc average input filter. 0: disable, 1: enable"] + #[inline(always)] + pub fn blc_filter_en(&self) -> BLC_FILTER_EN_R { + BLC_FILTER_EN_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLC_CTRL1") + .field( + "blc_window_top", + &format_args!("{}", self.blc_window_top().bits()), + ) + .field( + "blc_window_left", + &format_args!("{}", self.blc_window_left().bits()), + ) + .field( + "blc_window_vnum", + &format_args!("{}", self.blc_window_vnum().bits()), + ) + .field( + "blc_window_hnum", + &format_args!("{}", self.blc_window_hnum().bits()), + ) + .field( + "blc_filter_en", + &format_args!("{}", self.blc_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:10 - this field configures blc average calculation window top"] + #[inline(always)] + #[must_use] + pub fn blc_window_top(&mut self) -> BLC_WINDOW_TOP_W { + BLC_WINDOW_TOP_W::new(self, 0) + } + #[doc = "Bits 11:21 - this field configures blc average calculation window left"] + #[inline(always)] + #[must_use] + pub fn blc_window_left(&mut self) -> BLC_WINDOW_LEFT_W { + BLC_WINDOW_LEFT_W::new(self, 11) + } + #[doc = "Bits 22:25 - this field configures blc average calculation window vnum"] + #[inline(always)] + #[must_use] + pub fn blc_window_vnum(&mut self) -> BLC_WINDOW_VNUM_W { + BLC_WINDOW_VNUM_W::new(self, 22) + } + #[doc = "Bits 26:29 - this field configures blc average calculation window hnum"] + #[inline(always)] + #[must_use] + pub fn blc_window_hnum(&mut self) -> BLC_WINDOW_HNUM_W { + BLC_WINDOW_HNUM_W::new(self, 26) + } + #[doc = "Bit 30 - this bit configures enable blc average input filter. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn blc_filter_en(&mut self) -> BLC_FILTER_EN_W { + BLC_FILTER_EN_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "blc window control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blc_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blc_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLC_CTRL1_SPEC; +impl crate::RegisterSpec for BLC_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blc_ctrl1::R`](R) reader structure"] +impl crate::Readable for BLC_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blc_ctrl1::W`](W) writer structure"] +impl crate::Writable for BLC_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLC_CTRL1 to value 0"] +impl crate::Resettable for BLC_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/blc_ctrl2.rs b/esp32p4/src/isp/blc_ctrl2.rs new file mode 100644 index 0000000000..da07edb463 --- /dev/null +++ b/esp32p4/src/isp/blc_ctrl2.rs @@ -0,0 +1,111 @@ +#[doc = "Register `BLC_CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `BLC_CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `BLC_R3_TH` reader - this field configures black threshold when get blc average of bottom right channel"] +pub type BLC_R3_TH_R = crate::FieldReader; +#[doc = "Field `BLC_R3_TH` writer - this field configures black threshold when get blc average of bottom right channel"] +pub type BLC_R3_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BLC_R2_TH` reader - this field configures black threshold when get blc average of bottom left channel"] +pub type BLC_R2_TH_R = crate::FieldReader; +#[doc = "Field `BLC_R2_TH` writer - this field configures black threshold when get blc average of bottom left channel"] +pub type BLC_R2_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BLC_R1_TH` reader - this field configures black threshold when get blc average of top right channel"] +pub type BLC_R1_TH_R = crate::FieldReader; +#[doc = "Field `BLC_R1_TH` writer - this field configures black threshold when get blc average of top right channel"] +pub type BLC_R1_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BLC_R0_TH` reader - this field configures black threshold when get blc average of top left channel"] +pub type BLC_R0_TH_R = crate::FieldReader; +#[doc = "Field `BLC_R0_TH` writer - this field configures black threshold when get blc average of top left channel"] +pub type BLC_R0_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures black threshold when get blc average of bottom right channel"] + #[inline(always)] + pub fn blc_r3_th(&self) -> BLC_R3_TH_R { + BLC_R3_TH_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures black threshold when get blc average of bottom left channel"] + #[inline(always)] + pub fn blc_r2_th(&self) -> BLC_R2_TH_R { + BLC_R2_TH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures black threshold when get blc average of top right channel"] + #[inline(always)] + pub fn blc_r1_th(&self) -> BLC_R1_TH_R { + BLC_R1_TH_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures black threshold when get blc average of top left channel"] + #[inline(always)] + pub fn blc_r0_th(&self) -> BLC_R0_TH_R { + BLC_R0_TH_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLC_CTRL2") + .field("blc_r3_th", &format_args!("{}", self.blc_r3_th().bits())) + .field("blc_r2_th", &format_args!("{}", self.blc_r2_th().bits())) + .field("blc_r1_th", &format_args!("{}", self.blc_r1_th().bits())) + .field("blc_r0_th", &format_args!("{}", self.blc_r0_th().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures black threshold when get blc average of bottom right channel"] + #[inline(always)] + #[must_use] + pub fn blc_r3_th(&mut self) -> BLC_R3_TH_W { + BLC_R3_TH_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures black threshold when get blc average of bottom left channel"] + #[inline(always)] + #[must_use] + pub fn blc_r2_th(&mut self) -> BLC_R2_TH_W { + BLC_R2_TH_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures black threshold when get blc average of top right channel"] + #[inline(always)] + #[must_use] + pub fn blc_r1_th(&mut self) -> BLC_R1_TH_W { + BLC_R1_TH_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures black threshold when get blc average of top left channel"] + #[inline(always)] + #[must_use] + pub fn blc_r0_th(&mut self) -> BLC_R0_TH_W { + BLC_R0_TH_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "blc black threshold control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blc_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blc_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLC_CTRL2_SPEC; +impl crate::RegisterSpec for BLC_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blc_ctrl2::R`](R) reader structure"] +impl crate::Readable for BLC_CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blc_ctrl2::W`](W) writer structure"] +impl crate::Writable for BLC_CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLC_CTRL2 to value 0"] +impl crate::Resettable for BLC_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/blc_mean.rs b/esp32p4/src/isp/blc_mean.rs new file mode 100644 index 0000000000..d131499994 --- /dev/null +++ b/esp32p4/src/isp/blc_mean.rs @@ -0,0 +1,72 @@ +#[doc = "Register `BLC_MEAN` reader"] +pub type R = crate::R; +#[doc = "Field `BLC_R3_MEAN` reader - this field represents the average black value of bottom right channel"] +pub type BLC_R3_MEAN_R = crate::FieldReader; +#[doc = "Field `BLC_R2_MEAN` reader - this field represents the average black value of bottom left channel"] +pub type BLC_R2_MEAN_R = crate::FieldReader; +#[doc = "Field `BLC_R1_MEAN` reader - this field represents the average black value of top right channel"] +pub type BLC_R1_MEAN_R = crate::FieldReader; +#[doc = "Field `BLC_R0_MEAN` reader - this field represents the average black value of top left channel"] +pub type BLC_R0_MEAN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - this field represents the average black value of bottom right channel"] + #[inline(always)] + pub fn blc_r3_mean(&self) -> BLC_R3_MEAN_R { + BLC_R3_MEAN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field represents the average black value of bottom left channel"] + #[inline(always)] + pub fn blc_r2_mean(&self) -> BLC_R2_MEAN_R { + BLC_R2_MEAN_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field represents the average black value of top right channel"] + #[inline(always)] + pub fn blc_r1_mean(&self) -> BLC_R1_MEAN_R { + BLC_R1_MEAN_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field represents the average black value of top left channel"] + #[inline(always)] + pub fn blc_r0_mean(&self) -> BLC_R0_MEAN_R { + BLC_R0_MEAN_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLC_MEAN") + .field( + "blc_r3_mean", + &format_args!("{}", self.blc_r3_mean().bits()), + ) + .field( + "blc_r2_mean", + &format_args!("{}", self.blc_r2_mean().bits()), + ) + .field( + "blc_r1_mean", + &format_args!("{}", self.blc_r1_mean().bits()), + ) + .field( + "blc_r0_mean", + &format_args!("{}", self.blc_r0_mean().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "results of the average of black window\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blc_mean::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLC_MEAN_SPEC; +impl crate::RegisterSpec for BLC_MEAN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blc_mean::R`](R) reader structure"] +impl crate::Readable for BLC_MEAN_SPEC {} +#[doc = "`reset()` method sets BLC_MEAN to value 0"] +impl crate::Resettable for BLC_MEAN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/blc_value.rs b/esp32p4/src/isp/blc_value.rs new file mode 100644 index 0000000000..dcbb1bea04 --- /dev/null +++ b/esp32p4/src/isp/blc_value.rs @@ -0,0 +1,123 @@ +#[doc = "Register `BLC_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `BLC_VALUE` writer"] +pub type W = crate::W; +#[doc = "Field `BLC_R3_VALUE` reader - this field configures the black level of bottom right channel of bayer img"] +pub type BLC_R3_VALUE_R = crate::FieldReader; +#[doc = "Field `BLC_R3_VALUE` writer - this field configures the black level of bottom right channel of bayer img"] +pub type BLC_R3_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BLC_R2_VALUE` reader - this field configures the black level of bottom left channel of bayer img"] +pub type BLC_R2_VALUE_R = crate::FieldReader; +#[doc = "Field `BLC_R2_VALUE` writer - this field configures the black level of bottom left channel of bayer img"] +pub type BLC_R2_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BLC_R1_VALUE` reader - this field configures the black level of top right channel of bayer img"] +pub type BLC_R1_VALUE_R = crate::FieldReader; +#[doc = "Field `BLC_R1_VALUE` writer - this field configures the black level of top right channel of bayer img"] +pub type BLC_R1_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BLC_R0_VALUE` reader - this field configures the black level of top left channel of bayer img"] +pub type BLC_R0_VALUE_R = crate::FieldReader; +#[doc = "Field `BLC_R0_VALUE` writer - this field configures the black level of top left channel of bayer img"] +pub type BLC_R0_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the black level of bottom right channel of bayer img"] + #[inline(always)] + pub fn blc_r3_value(&self) -> BLC_R3_VALUE_R { + BLC_R3_VALUE_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the black level of bottom left channel of bayer img"] + #[inline(always)] + pub fn blc_r2_value(&self) -> BLC_R2_VALUE_R { + BLC_R2_VALUE_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the black level of top right channel of bayer img"] + #[inline(always)] + pub fn blc_r1_value(&self) -> BLC_R1_VALUE_R { + BLC_R1_VALUE_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the black level of top left channel of bayer img"] + #[inline(always)] + pub fn blc_r0_value(&self) -> BLC_R0_VALUE_R { + BLC_R0_VALUE_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLC_VALUE") + .field( + "blc_r3_value", + &format_args!("{}", self.blc_r3_value().bits()), + ) + .field( + "blc_r2_value", + &format_args!("{}", self.blc_r2_value().bits()), + ) + .field( + "blc_r1_value", + &format_args!("{}", self.blc_r1_value().bits()), + ) + .field( + "blc_r0_value", + &format_args!("{}", self.blc_r0_value().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the black level of bottom right channel of bayer img"] + #[inline(always)] + #[must_use] + pub fn blc_r3_value(&mut self) -> BLC_R3_VALUE_W { + BLC_R3_VALUE_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the black level of bottom left channel of bayer img"] + #[inline(always)] + #[must_use] + pub fn blc_r2_value(&mut self) -> BLC_R2_VALUE_W { + BLC_R2_VALUE_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the black level of top right channel of bayer img"] + #[inline(always)] + #[must_use] + pub fn blc_r1_value(&mut self) -> BLC_R1_VALUE_W { + BLC_R1_VALUE_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the black level of top left channel of bayer img"] + #[inline(always)] + #[must_use] + pub fn blc_r0_value(&mut self) -> BLC_R0_VALUE_W { + BLC_R0_VALUE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "blc black level register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blc_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blc_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLC_VALUE_SPEC; +impl crate::RegisterSpec for BLC_VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blc_value::R`](R) reader structure"] +impl crate::Readable for BLC_VALUE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blc_value::W`](W) writer structure"] +impl crate::Writable for BLC_VALUE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLC_VALUE to value 0"] +impl crate::Resettable for BLC_VALUE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/cam_cntl.rs b/esp32p4/src/isp/cam_cntl.rs new file mode 100644 index 0000000000..facbe8ae90 --- /dev/null +++ b/esp32p4/src/isp/cam_cntl.rs @@ -0,0 +1,111 @@ +#[doc = "Register `CAM_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `CAM_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `CAM_EN` reader - write 1 to start recive camera data, write 0 to disable"] +pub type CAM_EN_R = crate::BitReader; +#[doc = "Field `CAM_EN` writer - write 1 to start recive camera data, write 0 to disable"] +pub type CAM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_UPDATE` reader - write 1 to update ISP_CAM_CONF"] +pub type CAM_UPDATE_R = crate::BitReader; +#[doc = "Field `CAM_UPDATE` writer - write 1 to update ISP_CAM_CONF"] +pub type CAM_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_RESET` reader - this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset"] +pub type CAM_RESET_R = crate::BitReader; +#[doc = "Field `CAM_RESET` writer - this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset"] +pub type CAM_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_CLK_INV` reader - this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1: invert cam clk"] +pub type CAM_CLK_INV_R = crate::BitReader; +#[doc = "Field `CAM_CLK_INV` writer - this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1: invert cam clk"] +pub type CAM_CLK_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - write 1 to start recive camera data, write 0 to disable"] + #[inline(always)] + pub fn cam_en(&self) -> CAM_EN_R { + CAM_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - write 1 to update ISP_CAM_CONF"] + #[inline(always)] + pub fn cam_update(&self) -> CAM_UPDATE_R { + CAM_UPDATE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset"] + #[inline(always)] + pub fn cam_reset(&self) -> CAM_RESET_R { + CAM_RESET_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1: invert cam clk"] + #[inline(always)] + pub fn cam_clk_inv(&self) -> CAM_CLK_INV_R { + CAM_CLK_INV_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAM_CNTL") + .field("cam_en", &format_args!("{}", self.cam_en().bit())) + .field("cam_update", &format_args!("{}", self.cam_update().bit())) + .field("cam_reset", &format_args!("{}", self.cam_reset().bit())) + .field("cam_clk_inv", &format_args!("{}", self.cam_clk_inv().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - write 1 to start recive camera data, write 0 to disable"] + #[inline(always)] + #[must_use] + pub fn cam_en(&mut self) -> CAM_EN_W { + CAM_EN_W::new(self, 0) + } + #[doc = "Bit 1 - write 1 to update ISP_CAM_CONF"] + #[inline(always)] + #[must_use] + pub fn cam_update(&mut self) -> CAM_UPDATE_W { + CAM_UPDATE_W::new(self, 1) + } + #[doc = "Bit 2 - this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset"] + #[inline(always)] + #[must_use] + pub fn cam_reset(&mut self) -> CAM_RESET_W { + CAM_RESET_W::new(self, 2) + } + #[doc = "Bit 3 - this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1: invert cam clk"] + #[inline(always)] + #[must_use] + pub fn cam_clk_inv(&mut self) -> CAM_CLK_INV_W { + CAM_CLK_INV_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "isp cam source control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cam_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cam_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAM_CNTL_SPEC; +impl crate::RegisterSpec for CAM_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cam_cntl::R`](R) reader structure"] +impl crate::Readable for CAM_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cam_cntl::W`](W) writer structure"] +impl crate::Writable for CAM_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAM_CNTL to value 0x04"] +impl crate::Resettable for CAM_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/isp/cam_conf.rs b/esp32p4/src/isp/cam_conf.rs new file mode 100644 index 0000000000..3ab0223097 --- /dev/null +++ b/esp32p4/src/isp/cam_conf.rs @@ -0,0 +1,196 @@ +#[doc = "Register `CAM_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CAM_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CAM_DATA_ORDER` reader - this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in\\[7:0\\], cam_data_in\\[15:8\\]}"] +pub type CAM_DATA_ORDER_R = crate::BitReader; +#[doc = "Field `CAM_DATA_ORDER` writer - this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in\\[7:0\\], cam_data_in\\[15:8\\]}"] +pub type CAM_DATA_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_2BYTE_MODE` reader - this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: disable, 1: enable"] +pub type CAM_2BYTE_MODE_R = crate::BitReader; +#[doc = "Field `CAM_2BYTE_MODE` writer - this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: disable, 1: enable"] +pub type CAM_2BYTE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_DATA_TYPE` reader - this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: RAW12"] +pub type CAM_DATA_TYPE_R = crate::FieldReader; +#[doc = "Field `CAM_DATA_TYPE` writer - this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: RAW12"] +pub type CAM_DATA_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `CAM_DE_INV` reader - this bit configures cam data enable invert. 0: not invert, 1: invert"] +pub type CAM_DE_INV_R = crate::BitReader; +#[doc = "Field `CAM_DE_INV` writer - this bit configures cam data enable invert. 0: not invert, 1: invert"] +pub type CAM_DE_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_HSYNC_INV` reader - this bit configures cam hsync invert. 0: not invert, 1: invert"] +pub type CAM_HSYNC_INV_R = crate::BitReader; +#[doc = "Field `CAM_HSYNC_INV` writer - this bit configures cam hsync invert. 0: not invert, 1: invert"] +pub type CAM_HSYNC_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_VSYNC_INV` reader - this bit configures cam vsync invert. 0: not invert, 1: invert"] +pub type CAM_VSYNC_INV_R = crate::BitReader; +#[doc = "Field `CAM_VSYNC_INV` writer - this bit configures cam vsync invert. 0: not invert, 1: invert"] +pub type CAM_VSYNC_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_VSYNC_FILTER_THRES` reader - this bit configures the number of clock of vsync filter length"] +pub type CAM_VSYNC_FILTER_THRES_R = crate::FieldReader; +#[doc = "Field `CAM_VSYNC_FILTER_THRES` writer - this bit configures the number of clock of vsync filter length"] +pub type CAM_VSYNC_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CAM_VSYNC_FILTER_EN` reader - this bit configures vsync filter en"] +pub type CAM_VSYNC_FILTER_EN_R = crate::BitReader; +#[doc = "Field `CAM_VSYNC_FILTER_EN` writer - this bit configures vsync filter en"] +pub type CAM_VSYNC_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in\\[7:0\\], cam_data_in\\[15:8\\]}"] + #[inline(always)] + pub fn cam_data_order(&self) -> CAM_DATA_ORDER_R { + CAM_DATA_ORDER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: disable, 1: enable"] + #[inline(always)] + pub fn cam_2byte_mode(&self) -> CAM_2BYTE_MODE_R { + CAM_2BYTE_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: RAW12"] + #[inline(always)] + pub fn cam_data_type(&self) -> CAM_DATA_TYPE_R { + CAM_DATA_TYPE_R::new(((self.bits >> 2) & 0x3f) as u8) + } + #[doc = "Bit 8 - this bit configures cam data enable invert. 0: not invert, 1: invert"] + #[inline(always)] + pub fn cam_de_inv(&self) -> CAM_DE_INV_R { + CAM_DE_INV_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - this bit configures cam hsync invert. 0: not invert, 1: invert"] + #[inline(always)] + pub fn cam_hsync_inv(&self) -> CAM_HSYNC_INV_R { + CAM_HSYNC_INV_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - this bit configures cam vsync invert. 0: not invert, 1: invert"] + #[inline(always)] + pub fn cam_vsync_inv(&self) -> CAM_VSYNC_INV_R { + CAM_VSYNC_INV_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 11:13 - this bit configures the number of clock of vsync filter length"] + #[inline(always)] + pub fn cam_vsync_filter_thres(&self) -> CAM_VSYNC_FILTER_THRES_R { + CAM_VSYNC_FILTER_THRES_R::new(((self.bits >> 11) & 7) as u8) + } + #[doc = "Bit 14 - this bit configures vsync filter en"] + #[inline(always)] + pub fn cam_vsync_filter_en(&self) -> CAM_VSYNC_FILTER_EN_R { + CAM_VSYNC_FILTER_EN_R::new(((self.bits >> 14) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAM_CONF") + .field( + "cam_data_order", + &format_args!("{}", self.cam_data_order().bit()), + ) + .field( + "cam_2byte_mode", + &format_args!("{}", self.cam_2byte_mode().bit()), + ) + .field( + "cam_data_type", + &format_args!("{}", self.cam_data_type().bits()), + ) + .field("cam_de_inv", &format_args!("{}", self.cam_de_inv().bit())) + .field( + "cam_hsync_inv", + &format_args!("{}", self.cam_hsync_inv().bit()), + ) + .field( + "cam_vsync_inv", + &format_args!("{}", self.cam_vsync_inv().bit()), + ) + .field( + "cam_vsync_filter_thres", + &format_args!("{}", self.cam_vsync_filter_thres().bits()), + ) + .field( + "cam_vsync_filter_en", + &format_args!("{}", self.cam_vsync_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in\\[7:0\\], cam_data_in\\[15:8\\]}"] + #[inline(always)] + #[must_use] + pub fn cam_data_order(&mut self) -> CAM_DATA_ORDER_W { + CAM_DATA_ORDER_W::new(self, 0) + } + #[doc = "Bit 1 - this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn cam_2byte_mode(&mut self) -> CAM_2BYTE_MODE_W { + CAM_2BYTE_MODE_W::new(self, 1) + } + #[doc = "Bits 2:7 - this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: RAW12"] + #[inline(always)] + #[must_use] + pub fn cam_data_type(&mut self) -> CAM_DATA_TYPE_W { + CAM_DATA_TYPE_W::new(self, 2) + } + #[doc = "Bit 8 - this bit configures cam data enable invert. 0: not invert, 1: invert"] + #[inline(always)] + #[must_use] + pub fn cam_de_inv(&mut self) -> CAM_DE_INV_W { + CAM_DE_INV_W::new(self, 8) + } + #[doc = "Bit 9 - this bit configures cam hsync invert. 0: not invert, 1: invert"] + #[inline(always)] + #[must_use] + pub fn cam_hsync_inv(&mut self) -> CAM_HSYNC_INV_W { + CAM_HSYNC_INV_W::new(self, 9) + } + #[doc = "Bit 10 - this bit configures cam vsync invert. 0: not invert, 1: invert"] + #[inline(always)] + #[must_use] + pub fn cam_vsync_inv(&mut self) -> CAM_VSYNC_INV_W { + CAM_VSYNC_INV_W::new(self, 10) + } + #[doc = "Bits 11:13 - this bit configures the number of clock of vsync filter length"] + #[inline(always)] + #[must_use] + pub fn cam_vsync_filter_thres(&mut self) -> CAM_VSYNC_FILTER_THRES_W { + CAM_VSYNC_FILTER_THRES_W::new(self, 11) + } + #[doc = "Bit 14 - this bit configures vsync filter en"] + #[inline(always)] + #[must_use] + pub fn cam_vsync_filter_en(&mut self) -> CAM_VSYNC_FILTER_EN_W { + CAM_VSYNC_FILTER_EN_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "isp cam source config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cam_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cam_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAM_CONF_SPEC; +impl crate::RegisterSpec for CAM_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cam_conf::R`](R) reader structure"] +impl crate::Readable for CAM_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cam_conf::W`](W) writer structure"] +impl crate::Writable for CAM_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAM_CONF to value 0xa8"] +impl crate::Resettable for CAM_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0xa8; +} diff --git a/esp32p4/src/isp/ccm_coef0.rs b/esp32p4/src/isp/ccm_coef0.rs new file mode 100644 index 0000000000..0c82b88943 --- /dev/null +++ b/esp32p4/src/isp/ccm_coef0.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CCM_COEF0` reader"] +pub type R = crate::R; +#[doc = "Register `CCM_COEF0` writer"] +pub type W = crate::W; +#[doc = "Field `CCM_RR` reader - this field configures the color correction matrix coefficient"] +pub type CCM_RR_R = crate::FieldReader; +#[doc = "Field `CCM_RR` writer - this field configures the color correction matrix coefficient"] +pub type CCM_RR_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +#[doc = "Field `CCM_RG` reader - this field configures the color correction matrix coefficient"] +pub type CCM_RG_R = crate::FieldReader; +#[doc = "Field `CCM_RG` writer - this field configures the color correction matrix coefficient"] +pub type CCM_RG_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"] + #[inline(always)] + pub fn ccm_rr(&self) -> CCM_RR_R { + CCM_RR_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:25 - this field configures the color correction matrix coefficient"] + #[inline(always)] + pub fn ccm_rg(&self) -> CCM_RG_R { + CCM_RG_R::new(((self.bits >> 13) & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCM_COEF0") + .field("ccm_rr", &format_args!("{}", self.ccm_rr().bits())) + .field("ccm_rg", &format_args!("{}", self.ccm_rg().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"] + #[inline(always)] + #[must_use] + pub fn ccm_rr(&mut self) -> CCM_RR_W { + CCM_RR_W::new(self, 0) + } + #[doc = "Bits 13:25 - this field configures the color correction matrix coefficient"] + #[inline(always)] + #[must_use] + pub fn ccm_rg(&mut self) -> CCM_RG_W { + CCM_RG_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ccm coef register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccm_coef0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccm_coef0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CCM_COEF0_SPEC; +impl crate::RegisterSpec for CCM_COEF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccm_coef0::R`](R) reader structure"] +impl crate::Readable for CCM_COEF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccm_coef0::W`](W) writer structure"] +impl crate::Writable for CCM_COEF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCM_COEF0 to value 0x0250_0740"] +impl crate::Resettable for CCM_COEF0_SPEC { + const RESET_VALUE: Self::Ux = 0x0250_0740; +} diff --git a/esp32p4/src/isp/ccm_coef1.rs b/esp32p4/src/isp/ccm_coef1.rs new file mode 100644 index 0000000000..2c370478a9 --- /dev/null +++ b/esp32p4/src/isp/ccm_coef1.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CCM_COEF1` reader"] +pub type R = crate::R; +#[doc = "Register `CCM_COEF1` writer"] +pub type W = crate::W; +#[doc = "Field `CCM_RB` reader - this field configures the color correction matrix coefficient"] +pub type CCM_RB_R = crate::FieldReader; +#[doc = "Field `CCM_RB` writer - this field configures the color correction matrix coefficient"] +pub type CCM_RB_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +#[doc = "Field `CCM_GR` reader - this field configures the color correction matrix coefficient"] +pub type CCM_GR_R = crate::FieldReader; +#[doc = "Field `CCM_GR` writer - this field configures the color correction matrix coefficient"] +pub type CCM_GR_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"] + #[inline(always)] + pub fn ccm_rb(&self) -> CCM_RB_R { + CCM_RB_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:25 - this field configures the color correction matrix coefficient"] + #[inline(always)] + pub fn ccm_gr(&self) -> CCM_GR_R { + CCM_GR_R::new(((self.bits >> 13) & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCM_COEF1") + .field("ccm_rb", &format_args!("{}", self.ccm_rb().bits())) + .field("ccm_gr", &format_args!("{}", self.ccm_gr().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"] + #[inline(always)] + #[must_use] + pub fn ccm_rb(&mut self) -> CCM_RB_W { + CCM_RB_W::new(self, 0) + } + #[doc = "Bits 13:25 - this field configures the color correction matrix coefficient"] + #[inline(always)] + #[must_use] + pub fn ccm_gr(&mut self) -> CCM_GR_W { + CCM_GR_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ccm coef register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccm_coef1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccm_coef1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CCM_COEF1_SPEC; +impl crate::RegisterSpec for CCM_COEF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccm_coef1::R`](R) reader structure"] +impl crate::Readable for CCM_COEF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccm_coef1::W`](W) writer structure"] +impl crate::Writable for CCM_COEF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCM_COEF1 to value 0x0228_10c0"] +impl crate::Resettable for CCM_COEF1_SPEC { + const RESET_VALUE: Self::Ux = 0x0228_10c0; +} diff --git a/esp32p4/src/isp/ccm_coef3.rs b/esp32p4/src/isp/ccm_coef3.rs new file mode 100644 index 0000000000..d3419d150a --- /dev/null +++ b/esp32p4/src/isp/ccm_coef3.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CCM_COEF3` reader"] +pub type R = crate::R; +#[doc = "Register `CCM_COEF3` writer"] +pub type W = crate::W; +#[doc = "Field `CCM_GG` reader - this field configures the color correction matrix coefficient"] +pub type CCM_GG_R = crate::FieldReader; +#[doc = "Field `CCM_GG` writer - this field configures the color correction matrix coefficient"] +pub type CCM_GG_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +#[doc = "Field `CCM_GB` reader - this field configures the color correction matrix coefficient"] +pub type CCM_GB_R = crate::FieldReader; +#[doc = "Field `CCM_GB` writer - this field configures the color correction matrix coefficient"] +pub type CCM_GB_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"] + #[inline(always)] + pub fn ccm_gg(&self) -> CCM_GG_R { + CCM_GG_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:25 - this field configures the color correction matrix coefficient"] + #[inline(always)] + pub fn ccm_gb(&self) -> CCM_GB_R { + CCM_GB_R::new(((self.bits >> 13) & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCM_COEF3") + .field("ccm_gg", &format_args!("{}", self.ccm_gg().bits())) + .field("ccm_gb", &format_args!("{}", self.ccm_gb().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"] + #[inline(always)] + #[must_use] + pub fn ccm_gg(&mut self) -> CCM_GG_W { + CCM_GG_W::new(self, 0) + } + #[doc = "Bits 13:25 - this field configures the color correction matrix coefficient"] + #[inline(always)] + #[must_use] + pub fn ccm_gb(&mut self) -> CCM_GB_W { + CCM_GB_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ccm coef register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccm_coef3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccm_coef3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CCM_COEF3_SPEC; +impl crate::RegisterSpec for CCM_COEF3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccm_coef3::R`](R) reader structure"] +impl crate::Readable for CCM_COEF3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccm_coef3::W`](W) writer structure"] +impl crate::Writable for CCM_COEF3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCM_COEF3 to value 0x0220_0680"] +impl crate::Resettable for CCM_COEF3_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_0680; +} diff --git a/esp32p4/src/isp/ccm_coef4.rs b/esp32p4/src/isp/ccm_coef4.rs new file mode 100644 index 0000000000..2247d190e0 --- /dev/null +++ b/esp32p4/src/isp/ccm_coef4.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CCM_COEF4` reader"] +pub type R = crate::R; +#[doc = "Register `CCM_COEF4` writer"] +pub type W = crate::W; +#[doc = "Field `CCM_BR` reader - this field configures the color correction matrix coefficient"] +pub type CCM_BR_R = crate::FieldReader; +#[doc = "Field `CCM_BR` writer - this field configures the color correction matrix coefficient"] +pub type CCM_BR_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +#[doc = "Field `CCM_BG` reader - this field configures the color correction matrix coefficient"] +pub type CCM_BG_R = crate::FieldReader; +#[doc = "Field `CCM_BG` writer - this field configures the color correction matrix coefficient"] +pub type CCM_BG_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"] + #[inline(always)] + pub fn ccm_br(&self) -> CCM_BR_R { + CCM_BR_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 13:25 - this field configures the color correction matrix coefficient"] + #[inline(always)] + pub fn ccm_bg(&self) -> CCM_BG_R { + CCM_BG_R::new(((self.bits >> 13) & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCM_COEF4") + .field("ccm_br", &format_args!("{}", self.ccm_br().bits())) + .field("ccm_bg", &format_args!("{}", self.ccm_bg().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"] + #[inline(always)] + #[must_use] + pub fn ccm_br(&mut self) -> CCM_BR_W { + CCM_BR_W::new(self, 0) + } + #[doc = "Bits 13:25 - this field configures the color correction matrix coefficient"] + #[inline(always)] + #[must_use] + pub fn ccm_bg(&mut self) -> CCM_BG_W { + CCM_BG_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ccm coef register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccm_coef4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccm_coef4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CCM_COEF4_SPEC; +impl crate::RegisterSpec for CCM_COEF4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccm_coef4::R`](R) reader structure"] +impl crate::Readable for CCM_COEF4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccm_coef4::W`](W) writer structure"] +impl crate::Writable for CCM_COEF4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCM_COEF4 to value 0x0258_1040"] +impl crate::Resettable for CCM_COEF4_SPEC { + const RESET_VALUE: Self::Ux = 0x0258_1040; +} diff --git a/esp32p4/src/isp/ccm_coef5.rs b/esp32p4/src/isp/ccm_coef5.rs new file mode 100644 index 0000000000..c9cce7bde5 --- /dev/null +++ b/esp32p4/src/isp/ccm_coef5.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CCM_COEF5` reader"] +pub type R = crate::R; +#[doc = "Register `CCM_COEF5` writer"] +pub type W = crate::W; +#[doc = "Field `CCM_BB` reader - this field configures the color correction matrix coefficient"] +pub type CCM_BB_R = crate::FieldReader; +#[doc = "Field `CCM_BB` writer - this field configures the color correction matrix coefficient"] +pub type CCM_BB_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"] + #[inline(always)] + pub fn ccm_bb(&self) -> CCM_BB_R { + CCM_BB_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCM_COEF5") + .field("ccm_bb", &format_args!("{}", self.ccm_bb().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"] + #[inline(always)] + #[must_use] + pub fn ccm_bb(&mut self) -> CCM_BB_W { + CCM_BB_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ccm coef register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccm_coef5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccm_coef5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CCM_COEF5_SPEC; +impl crate::RegisterSpec for CCM_COEF5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccm_coef5::R`](R) reader structure"] +impl crate::Readable for CCM_COEF5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccm_coef5::W`](W) writer structure"] +impl crate::Writable for CCM_COEF5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCM_COEF5 to value 0x0740"] +impl crate::Resettable for CCM_COEF5_SPEC { + const RESET_VALUE: Self::Ux = 0x0740; +} diff --git a/esp32p4/src/isp/clk_en.rs b/esp32p4/src/isp/clk_en.rs new file mode 100644 index 0000000000..0a7afb8ae4 --- /dev/null +++ b/esp32p4/src/isp/clk_en.rs @@ -0,0 +1,405 @@ +#[doc = "Register `CLK_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_EN` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - this bit configures the clk force on of isp reg. 0: disable, 1: enable"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - this bit configures the clk force on of isp reg. 0: disable, 1: enable"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_BLC_FORCE_ON` reader - this bit configures the clk force on of blc. 0: disable, 1: enable"] +pub type CLK_BLC_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_BLC_FORCE_ON` writer - this bit configures the clk force on of blc. 0: disable, 1: enable"] +pub type CLK_BLC_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_DPC_FORCE_ON` reader - this bit configures the clk force on of dpc. 0: disable, 1: enable"] +pub type CLK_DPC_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_DPC_FORCE_ON` writer - this bit configures the clk force on of dpc. 0: disable, 1: enable"] +pub type CLK_DPC_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_BF_FORCE_ON` reader - this bit configures the clk force on of bf. 0: disable, 1: enable"] +pub type CLK_BF_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_BF_FORCE_ON` writer - this bit configures the clk force on of bf. 0: disable, 1: enable"] +pub type CLK_BF_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_LSC_FORCE_ON` reader - this bit configures the clk force on of lsc. 0: disable, 1: enable"] +pub type CLK_LSC_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_LSC_FORCE_ON` writer - this bit configures the clk force on of lsc. 0: disable, 1: enable"] +pub type CLK_LSC_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_DEMOSAIC_FORCE_ON` reader - this bit configures the clk force on of demosaic. 0: disable, 1: enable"] +pub type CLK_DEMOSAIC_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_DEMOSAIC_FORCE_ON` writer - this bit configures the clk force on of demosaic. 0: disable, 1: enable"] +pub type CLK_DEMOSAIC_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_MEDIAN_FORCE_ON` reader - this bit configures the clk force on of median. 0: disable, 1: enable"] +pub type CLK_MEDIAN_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_MEDIAN_FORCE_ON` writer - this bit configures the clk force on of median. 0: disable, 1: enable"] +pub type CLK_MEDIAN_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_CCM_FORCE_ON` reader - this bit configures the clk force on of ccm. 0: disable, 1: enable"] +pub type CLK_CCM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_CCM_FORCE_ON` writer - this bit configures the clk force on of ccm. 0: disable, 1: enable"] +pub type CLK_CCM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_GAMMA_FORCE_ON` reader - this bit configures the clk force on of gamma. 0: disable, 1: enable"] +pub type CLK_GAMMA_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_GAMMA_FORCE_ON` writer - this bit configures the clk force on of gamma. 0: disable, 1: enable"] +pub type CLK_GAMMA_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_RGB2YUV_FORCE_ON` reader - this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable"] +pub type CLK_RGB2YUV_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_RGB2YUV_FORCE_ON` writer - this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable"] +pub type CLK_RGB2YUV_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SHARP_FORCE_ON` reader - this bit configures the clk force on of sharp. 0: disable, 1: enable"] +pub type CLK_SHARP_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_SHARP_FORCE_ON` writer - this bit configures the clk force on of sharp. 0: disable, 1: enable"] +pub type CLK_SHARP_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_COLOR_FORCE_ON` reader - this bit configures the clk force on of color. 0: disable, 1: enable"] +pub type CLK_COLOR_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_COLOR_FORCE_ON` writer - this bit configures the clk force on of color. 0: disable, 1: enable"] +pub type CLK_COLOR_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_YUV2RGB_FORCE_ON` reader - this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable"] +pub type CLK_YUV2RGB_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_YUV2RGB_FORCE_ON` writer - this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable"] +pub type CLK_YUV2RGB_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_AE_FORCE_ON` reader - this bit configures the clk force on of ae. 0: disable, 1: enable"] +pub type CLK_AE_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_AE_FORCE_ON` writer - this bit configures the clk force on of ae. 0: disable, 1: enable"] +pub type CLK_AE_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_AF_FORCE_ON` reader - this bit configures the clk force on of af. 0: disable, 1: enable"] +pub type CLK_AF_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_AF_FORCE_ON` writer - this bit configures the clk force on of af. 0: disable, 1: enable"] +pub type CLK_AF_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_AWB_FORCE_ON` reader - this bit configures the clk force on of awb. 0: disable, 1: enable"] +pub type CLK_AWB_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_AWB_FORCE_ON` writer - this bit configures the clk force on of awb. 0: disable, 1: enable"] +pub type CLK_AWB_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_HIST_FORCE_ON` reader - this bit configures the clk force on of hist. 0: disable, 1: enable"] +pub type CLK_HIST_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_HIST_FORCE_ON` writer - this bit configures the clk force on of hist. 0: disable, 1: enable"] +pub type CLK_HIST_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_MIPI_IDI_FORCE_ON` reader - this bit configures the clk force on of mipi idi input. 0: disable, 1: enable"] +pub type CLK_MIPI_IDI_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CLK_MIPI_IDI_FORCE_ON` writer - this bit configures the clk force on of mipi idi input. 0: disable, 1: enable"] +pub type CLK_MIPI_IDI_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_MEM_CLK_FORCE_ON` reader - this bit configures the clk force on of all isp memory. 0: disable, 1: enable"] +pub type ISP_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `ISP_MEM_CLK_FORCE_ON` writer - this bit configures the clk force on of all isp memory. 0: disable, 1: enable"] +pub type ISP_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - this bit configures the clk force on of isp reg. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - this bit configures the clk force on of blc. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_blc_force_on(&self) -> CLK_BLC_FORCE_ON_R { + CLK_BLC_FORCE_ON_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - this bit configures the clk force on of dpc. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_dpc_force_on(&self) -> CLK_DPC_FORCE_ON_R { + CLK_DPC_FORCE_ON_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - this bit configures the clk force on of bf. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_bf_force_on(&self) -> CLK_BF_FORCE_ON_R { + CLK_BF_FORCE_ON_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - this bit configures the clk force on of lsc. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_lsc_force_on(&self) -> CLK_LSC_FORCE_ON_R { + CLK_LSC_FORCE_ON_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - this bit configures the clk force on of demosaic. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_demosaic_force_on(&self) -> CLK_DEMOSAIC_FORCE_ON_R { + CLK_DEMOSAIC_FORCE_ON_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - this bit configures the clk force on of median. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_median_force_on(&self) -> CLK_MEDIAN_FORCE_ON_R { + CLK_MEDIAN_FORCE_ON_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - this bit configures the clk force on of ccm. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_ccm_force_on(&self) -> CLK_CCM_FORCE_ON_R { + CLK_CCM_FORCE_ON_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - this bit configures the clk force on of gamma. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_gamma_force_on(&self) -> CLK_GAMMA_FORCE_ON_R { + CLK_GAMMA_FORCE_ON_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_rgb2yuv_force_on(&self) -> CLK_RGB2YUV_FORCE_ON_R { + CLK_RGB2YUV_FORCE_ON_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - this bit configures the clk force on of sharp. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_sharp_force_on(&self) -> CLK_SHARP_FORCE_ON_R { + CLK_SHARP_FORCE_ON_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - this bit configures the clk force on of color. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_color_force_on(&self) -> CLK_COLOR_FORCE_ON_R { + CLK_COLOR_FORCE_ON_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_yuv2rgb_force_on(&self) -> CLK_YUV2RGB_FORCE_ON_R { + CLK_YUV2RGB_FORCE_ON_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - this bit configures the clk force on of ae. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_ae_force_on(&self) -> CLK_AE_FORCE_ON_R { + CLK_AE_FORCE_ON_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - this bit configures the clk force on of af. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_af_force_on(&self) -> CLK_AF_FORCE_ON_R { + CLK_AF_FORCE_ON_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - this bit configures the clk force on of awb. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_awb_force_on(&self) -> CLK_AWB_FORCE_ON_R { + CLK_AWB_FORCE_ON_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - this bit configures the clk force on of hist. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_hist_force_on(&self) -> CLK_HIST_FORCE_ON_R { + CLK_HIST_FORCE_ON_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - this bit configures the clk force on of mipi idi input. 0: disable, 1: enable"] + #[inline(always)] + pub fn clk_mipi_idi_force_on(&self) -> CLK_MIPI_IDI_FORCE_ON_R { + CLK_MIPI_IDI_FORCE_ON_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - this bit configures the clk force on of all isp memory. 0: disable, 1: enable"] + #[inline(always)] + pub fn isp_mem_clk_force_on(&self) -> ISP_MEM_CLK_FORCE_ON_R { + ISP_MEM_CLK_FORCE_ON_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_EN") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field( + "clk_blc_force_on", + &format_args!("{}", self.clk_blc_force_on().bit()), + ) + .field( + "clk_dpc_force_on", + &format_args!("{}", self.clk_dpc_force_on().bit()), + ) + .field( + "clk_bf_force_on", + &format_args!("{}", self.clk_bf_force_on().bit()), + ) + .field( + "clk_lsc_force_on", + &format_args!("{}", self.clk_lsc_force_on().bit()), + ) + .field( + "clk_demosaic_force_on", + &format_args!("{}", self.clk_demosaic_force_on().bit()), + ) + .field( + "clk_median_force_on", + &format_args!("{}", self.clk_median_force_on().bit()), + ) + .field( + "clk_ccm_force_on", + &format_args!("{}", self.clk_ccm_force_on().bit()), + ) + .field( + "clk_gamma_force_on", + &format_args!("{}", self.clk_gamma_force_on().bit()), + ) + .field( + "clk_rgb2yuv_force_on", + &format_args!("{}", self.clk_rgb2yuv_force_on().bit()), + ) + .field( + "clk_sharp_force_on", + &format_args!("{}", self.clk_sharp_force_on().bit()), + ) + .field( + "clk_color_force_on", + &format_args!("{}", self.clk_color_force_on().bit()), + ) + .field( + "clk_yuv2rgb_force_on", + &format_args!("{}", self.clk_yuv2rgb_force_on().bit()), + ) + .field( + "clk_ae_force_on", + &format_args!("{}", self.clk_ae_force_on().bit()), + ) + .field( + "clk_af_force_on", + &format_args!("{}", self.clk_af_force_on().bit()), + ) + .field( + "clk_awb_force_on", + &format_args!("{}", self.clk_awb_force_on().bit()), + ) + .field( + "clk_hist_force_on", + &format_args!("{}", self.clk_hist_force_on().bit()), + ) + .field( + "clk_mipi_idi_force_on", + &format_args!("{}", self.clk_mipi_idi_force_on().bit()), + ) + .field( + "isp_mem_clk_force_on", + &format_args!("{}", self.isp_mem_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures the clk force on of isp reg. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - this bit configures the clk force on of blc. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_blc_force_on(&mut self) -> CLK_BLC_FORCE_ON_W { + CLK_BLC_FORCE_ON_W::new(self, 1) + } + #[doc = "Bit 2 - this bit configures the clk force on of dpc. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_dpc_force_on(&mut self) -> CLK_DPC_FORCE_ON_W { + CLK_DPC_FORCE_ON_W::new(self, 2) + } + #[doc = "Bit 3 - this bit configures the clk force on of bf. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_bf_force_on(&mut self) -> CLK_BF_FORCE_ON_W { + CLK_BF_FORCE_ON_W::new(self, 3) + } + #[doc = "Bit 4 - this bit configures the clk force on of lsc. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_lsc_force_on(&mut self) -> CLK_LSC_FORCE_ON_W { + CLK_LSC_FORCE_ON_W::new(self, 4) + } + #[doc = "Bit 5 - this bit configures the clk force on of demosaic. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_demosaic_force_on(&mut self) -> CLK_DEMOSAIC_FORCE_ON_W { + CLK_DEMOSAIC_FORCE_ON_W::new(self, 5) + } + #[doc = "Bit 6 - this bit configures the clk force on of median. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_median_force_on(&mut self) -> CLK_MEDIAN_FORCE_ON_W { + CLK_MEDIAN_FORCE_ON_W::new(self, 6) + } + #[doc = "Bit 7 - this bit configures the clk force on of ccm. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_ccm_force_on(&mut self) -> CLK_CCM_FORCE_ON_W { + CLK_CCM_FORCE_ON_W::new(self, 7) + } + #[doc = "Bit 8 - this bit configures the clk force on of gamma. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_gamma_force_on(&mut self) -> CLK_GAMMA_FORCE_ON_W { + CLK_GAMMA_FORCE_ON_W::new(self, 8) + } + #[doc = "Bit 9 - this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_rgb2yuv_force_on(&mut self) -> CLK_RGB2YUV_FORCE_ON_W { + CLK_RGB2YUV_FORCE_ON_W::new(self, 9) + } + #[doc = "Bit 10 - this bit configures the clk force on of sharp. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_sharp_force_on(&mut self) -> CLK_SHARP_FORCE_ON_W { + CLK_SHARP_FORCE_ON_W::new(self, 10) + } + #[doc = "Bit 11 - this bit configures the clk force on of color. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_color_force_on(&mut self) -> CLK_COLOR_FORCE_ON_W { + CLK_COLOR_FORCE_ON_W::new(self, 11) + } + #[doc = "Bit 12 - this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_yuv2rgb_force_on(&mut self) -> CLK_YUV2RGB_FORCE_ON_W { + CLK_YUV2RGB_FORCE_ON_W::new(self, 12) + } + #[doc = "Bit 13 - this bit configures the clk force on of ae. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_ae_force_on(&mut self) -> CLK_AE_FORCE_ON_W { + CLK_AE_FORCE_ON_W::new(self, 13) + } + #[doc = "Bit 14 - this bit configures the clk force on of af. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_af_force_on(&mut self) -> CLK_AF_FORCE_ON_W { + CLK_AF_FORCE_ON_W::new(self, 14) + } + #[doc = "Bit 15 - this bit configures the clk force on of awb. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_awb_force_on(&mut self) -> CLK_AWB_FORCE_ON_W { + CLK_AWB_FORCE_ON_W::new(self, 15) + } + #[doc = "Bit 16 - this bit configures the clk force on of hist. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_hist_force_on(&mut self) -> CLK_HIST_FORCE_ON_W { + CLK_HIST_FORCE_ON_W::new(self, 16) + } + #[doc = "Bit 17 - this bit configures the clk force on of mipi idi input. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn clk_mipi_idi_force_on(&mut self) -> CLK_MIPI_IDI_FORCE_ON_W { + CLK_MIPI_IDI_FORCE_ON_W::new(self, 17) + } + #[doc = "Bit 18 - this bit configures the clk force on of all isp memory. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn isp_mem_clk_force_on(&mut self) -> ISP_MEM_CLK_FORCE_ON_W { + ISP_MEM_CLK_FORCE_ON_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "isp clk control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_EN_SPEC; +impl crate::RegisterSpec for CLK_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_en::R`](R) reader structure"] +impl crate::Readable for CLK_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_en::W`](W) writer structure"] +impl crate::Writable for CLK_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_EN to value 0"] +impl crate::Resettable for CLK_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/cntl.rs b/esp32p4/src/isp/cntl.rs new file mode 100644 index 0000000000..e3c5eae200 --- /dev/null +++ b/esp32p4/src/isp/cntl.rs @@ -0,0 +1,411 @@ +#[doc = "Register `CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `MIPI_DATA_EN` reader - this bit configures mipi input data enable. 0: disable, 1: enable"] +pub type MIPI_DATA_EN_R = crate::BitReader; +#[doc = "Field `MIPI_DATA_EN` writer - this bit configures mipi input data enable. 0: disable, 1: enable"] +pub type MIPI_DATA_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_EN` reader - this bit configures isp global enable. 0: disable, 1: enable"] +pub type ISP_EN_R = crate::BitReader; +#[doc = "Field `ISP_EN` writer - this bit configures isp global enable. 0: disable, 1: enable"] +pub type ISP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLC_EN` reader - this bit configures blc enable. 0: disable, 1: enable"] +pub type BLC_EN_R = crate::BitReader; +#[doc = "Field `BLC_EN` writer - this bit configures blc enable. 0: disable, 1: enable"] +pub type BLC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPC_EN` reader - this bit configures dpc enable. 0: disable, 1: enable"] +pub type DPC_EN_R = crate::BitReader; +#[doc = "Field `DPC_EN` writer - this bit configures dpc enable. 0: disable, 1: enable"] +pub type DPC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BF_EN` reader - this bit configures bf enable. 0: disable, 1: enable"] +pub type BF_EN_R = crate::BitReader; +#[doc = "Field `BF_EN` writer - this bit configures bf enable. 0: disable, 1: enable"] +pub type BF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LSC_EN` reader - this bit configures lsc enable. 0: disable, 1: enable"] +pub type LSC_EN_R = crate::BitReader; +#[doc = "Field `LSC_EN` writer - this bit configures lsc enable. 0: disable, 1: enable"] +pub type LSC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEMOSAIC_EN` reader - this bit configures demosaic enable. 0: disable, 1: enable"] +pub type DEMOSAIC_EN_R = crate::BitReader; +#[doc = "Field `DEMOSAIC_EN` writer - this bit configures demosaic enable. 0: disable, 1: enable"] +pub type DEMOSAIC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEDIAN_EN` reader - this bit configures median enable. 0: disable, 1: enable"] +pub type MEDIAN_EN_R = crate::BitReader; +#[doc = "Field `MEDIAN_EN` writer - this bit configures median enable. 0: disable, 1: enable"] +pub type MEDIAN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CCM_EN` reader - this bit configures ccm enable. 0: disable, 1: enable"] +pub type CCM_EN_R = crate::BitReader; +#[doc = "Field `CCM_EN` writer - this bit configures ccm enable. 0: disable, 1: enable"] +pub type CCM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_EN` reader - this bit configures gamma enable. 0: disable, 1: enable"] +pub type GAMMA_EN_R = crate::BitReader; +#[doc = "Field `GAMMA_EN` writer - this bit configures gamma enable. 0: disable, 1: enable"] +pub type GAMMA_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RGB2YUV_EN` reader - this bit configures rgb2yuv enable. 0: disable, 1: enable"] +pub type RGB2YUV_EN_R = crate::BitReader; +#[doc = "Field `RGB2YUV_EN` writer - this bit configures rgb2yuv enable. 0: disable, 1: enable"] +pub type RGB2YUV_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SHARP_EN` reader - this bit configures sharp enable. 0: disable, 1: enable"] +pub type SHARP_EN_R = crate::BitReader; +#[doc = "Field `SHARP_EN` writer - this bit configures sharp enable. 0: disable, 1: enable"] +pub type SHARP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COLOR_EN` reader - this bit configures color enable. 0: disable, 1: enable"] +pub type COLOR_EN_R = crate::BitReader; +#[doc = "Field `COLOR_EN` writer - this bit configures color enable. 0: disable, 1: enable"] +pub type COLOR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `YUV2RGB_EN` reader - this bit configures yuv2rgb enable. 0: disable, 1: enable"] +pub type YUV2RGB_EN_R = crate::BitReader; +#[doc = "Field `YUV2RGB_EN` writer - this bit configures yuv2rgb enable. 0: disable, 1: enable"] +pub type YUV2RGB_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AE_EN` reader - this bit configures ae enable. 0: disable, 1: enable"] +pub type AE_EN_R = crate::BitReader; +#[doc = "Field `AE_EN` writer - this bit configures ae enable. 0: disable, 1: enable"] +pub type AE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AF_EN` reader - this bit configures af enable. 0: disable, 1: enable"] +pub type AF_EN_R = crate::BitReader; +#[doc = "Field `AF_EN` writer - this bit configures af enable. 0: disable, 1: enable"] +pub type AF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AWB_EN` reader - this bit configures awb enable. 0: disable, 1: enable"] +pub type AWB_EN_R = crate::BitReader; +#[doc = "Field `AWB_EN` writer - this bit configures awb enable. 0: disable, 1: enable"] +pub type AWB_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HIST_EN` reader - this bit configures hist enable. 0: disable, 1: enable"] +pub type HIST_EN_R = crate::BitReader; +#[doc = "Field `HIST_EN` writer - this bit configures hist enable. 0: disable, 1: enable"] +pub type HIST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BYTE_ENDIAN_ORDER` reader - select input idi data byte_endian_order when isp is bypass, 0: csi_data\\[31:0\\], 1: {\\[7:0\\], \\[15:8\\], \\[23:16\\], \\[31:24\\]}"] +pub type BYTE_ENDIAN_ORDER_R = crate::BitReader; +#[doc = "Field `BYTE_ENDIAN_ORDER` writer - select input idi data byte_endian_order when isp is bypass, 0: csi_data\\[31:0\\], 1: {\\[7:0\\], \\[15:8\\], \\[23:16\\], \\[31:24\\]}"] +pub type BYTE_ENDIAN_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_DATA_TYPE` reader - this field configures input data type, 0:RAW8 1:RAW10 2:RAW12"] +pub type ISP_DATA_TYPE_R = crate::FieldReader; +#[doc = "Field `ISP_DATA_TYPE` writer - this field configures input data type, 0:RAW8 1:RAW10 2:RAW12"] +pub type ISP_DATA_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ISP_IN_SRC` reader - this field configures input data source, 0:CSI HOST 1:CAM 2:DMA"] +pub type ISP_IN_SRC_R = crate::FieldReader; +#[doc = "Field `ISP_IN_SRC` writer - this field configures input data source, 0:CSI HOST 1:CAM 2:DMA"] +pub type ISP_IN_SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ISP_OUT_TYPE` reader - this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: RGB565"] +pub type ISP_OUT_TYPE_R = crate::FieldReader; +#[doc = "Field `ISP_OUT_TYPE` writer - this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: RGB565"] +pub type ISP_OUT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - this bit configures mipi input data enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn mipi_data_en(&self) -> MIPI_DATA_EN_R { + MIPI_DATA_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - this bit configures isp global enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn isp_en(&self) -> ISP_EN_R { + ISP_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - this bit configures blc enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn blc_en(&self) -> BLC_EN_R { + BLC_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - this bit configures dpc enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn dpc_en(&self) -> DPC_EN_R { + DPC_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - this bit configures bf enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn bf_en(&self) -> BF_EN_R { + BF_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - this bit configures lsc enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn lsc_en(&self) -> LSC_EN_R { + LSC_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - this bit configures demosaic enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn demosaic_en(&self) -> DEMOSAIC_EN_R { + DEMOSAIC_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - this bit configures median enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn median_en(&self) -> MEDIAN_EN_R { + MEDIAN_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - this bit configures ccm enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn ccm_en(&self) -> CCM_EN_R { + CCM_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - this bit configures gamma enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn gamma_en(&self) -> GAMMA_EN_R { + GAMMA_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - this bit configures rgb2yuv enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn rgb2yuv_en(&self) -> RGB2YUV_EN_R { + RGB2YUV_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - this bit configures sharp enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn sharp_en(&self) -> SHARP_EN_R { + SHARP_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - this bit configures color enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn color_en(&self) -> COLOR_EN_R { + COLOR_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - this bit configures yuv2rgb enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn yuv2rgb_en(&self) -> YUV2RGB_EN_R { + YUV2RGB_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - this bit configures ae enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn ae_en(&self) -> AE_EN_R { + AE_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - this bit configures af enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn af_en(&self) -> AF_EN_R { + AF_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - this bit configures awb enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn awb_en(&self) -> AWB_EN_R { + AWB_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - this bit configures hist enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn hist_en(&self) -> HIST_EN_R { + HIST_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 24 - select input idi data byte_endian_order when isp is bypass, 0: csi_data\\[31:0\\], 1: {\\[7:0\\], \\[15:8\\], \\[23:16\\], \\[31:24\\]}"] + #[inline(always)] + pub fn byte_endian_order(&self) -> BYTE_ENDIAN_ORDER_R { + BYTE_ENDIAN_ORDER_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:26 - this field configures input data type, 0:RAW8 1:RAW10 2:RAW12"] + #[inline(always)] + pub fn isp_data_type(&self) -> ISP_DATA_TYPE_R { + ISP_DATA_TYPE_R::new(((self.bits >> 25) & 3) as u8) + } + #[doc = "Bits 27:28 - this field configures input data source, 0:CSI HOST 1:CAM 2:DMA"] + #[inline(always)] + pub fn isp_in_src(&self) -> ISP_IN_SRC_R { + ISP_IN_SRC_R::new(((self.bits >> 27) & 3) as u8) + } + #[doc = "Bits 29:31 - this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: RGB565"] + #[inline(always)] + pub fn isp_out_type(&self) -> ISP_OUT_TYPE_R { + ISP_OUT_TYPE_R::new(((self.bits >> 29) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CNTL") + .field( + "mipi_data_en", + &format_args!("{}", self.mipi_data_en().bit()), + ) + .field("isp_en", &format_args!("{}", self.isp_en().bit())) + .field("blc_en", &format_args!("{}", self.blc_en().bit())) + .field("dpc_en", &format_args!("{}", self.dpc_en().bit())) + .field("bf_en", &format_args!("{}", self.bf_en().bit())) + .field("lsc_en", &format_args!("{}", self.lsc_en().bit())) + .field("demosaic_en", &format_args!("{}", self.demosaic_en().bit())) + .field("median_en", &format_args!("{}", self.median_en().bit())) + .field("ccm_en", &format_args!("{}", self.ccm_en().bit())) + .field("gamma_en", &format_args!("{}", self.gamma_en().bit())) + .field("rgb2yuv_en", &format_args!("{}", self.rgb2yuv_en().bit())) + .field("sharp_en", &format_args!("{}", self.sharp_en().bit())) + .field("color_en", &format_args!("{}", self.color_en().bit())) + .field("yuv2rgb_en", &format_args!("{}", self.yuv2rgb_en().bit())) + .field("ae_en", &format_args!("{}", self.ae_en().bit())) + .field("af_en", &format_args!("{}", self.af_en().bit())) + .field("awb_en", &format_args!("{}", self.awb_en().bit())) + .field("hist_en", &format_args!("{}", self.hist_en().bit())) + .field( + "byte_endian_order", + &format_args!("{}", self.byte_endian_order().bit()), + ) + .field( + "isp_data_type", + &format_args!("{}", self.isp_data_type().bits()), + ) + .field("isp_in_src", &format_args!("{}", self.isp_in_src().bits())) + .field( + "isp_out_type", + &format_args!("{}", self.isp_out_type().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures mipi input data enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn mipi_data_en(&mut self) -> MIPI_DATA_EN_W { + MIPI_DATA_EN_W::new(self, 0) + } + #[doc = "Bit 1 - this bit configures isp global enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn isp_en(&mut self) -> ISP_EN_W { + ISP_EN_W::new(self, 1) + } + #[doc = "Bit 2 - this bit configures blc enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn blc_en(&mut self) -> BLC_EN_W { + BLC_EN_W::new(self, 2) + } + #[doc = "Bit 3 - this bit configures dpc enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn dpc_en(&mut self) -> DPC_EN_W { + DPC_EN_W::new(self, 3) + } + #[doc = "Bit 4 - this bit configures bf enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn bf_en(&mut self) -> BF_EN_W { + BF_EN_W::new(self, 4) + } + #[doc = "Bit 5 - this bit configures lsc enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn lsc_en(&mut self) -> LSC_EN_W { + LSC_EN_W::new(self, 5) + } + #[doc = "Bit 6 - this bit configures demosaic enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn demosaic_en(&mut self) -> DEMOSAIC_EN_W { + DEMOSAIC_EN_W::new(self, 6) + } + #[doc = "Bit 7 - this bit configures median enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn median_en(&mut self) -> MEDIAN_EN_W { + MEDIAN_EN_W::new(self, 7) + } + #[doc = "Bit 8 - this bit configures ccm enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn ccm_en(&mut self) -> CCM_EN_W { + CCM_EN_W::new(self, 8) + } + #[doc = "Bit 9 - this bit configures gamma enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn gamma_en(&mut self) -> GAMMA_EN_W { + GAMMA_EN_W::new(self, 9) + } + #[doc = "Bit 10 - this bit configures rgb2yuv enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn rgb2yuv_en(&mut self) -> RGB2YUV_EN_W { + RGB2YUV_EN_W::new(self, 10) + } + #[doc = "Bit 11 - this bit configures sharp enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn sharp_en(&mut self) -> SHARP_EN_W { + SHARP_EN_W::new(self, 11) + } + #[doc = "Bit 12 - this bit configures color enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn color_en(&mut self) -> COLOR_EN_W { + COLOR_EN_W::new(self, 12) + } + #[doc = "Bit 13 - this bit configures yuv2rgb enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn yuv2rgb_en(&mut self) -> YUV2RGB_EN_W { + YUV2RGB_EN_W::new(self, 13) + } + #[doc = "Bit 14 - this bit configures ae enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn ae_en(&mut self) -> AE_EN_W { + AE_EN_W::new(self, 14) + } + #[doc = "Bit 15 - this bit configures af enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn af_en(&mut self) -> AF_EN_W { + AF_EN_W::new(self, 15) + } + #[doc = "Bit 16 - this bit configures awb enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn awb_en(&mut self) -> AWB_EN_W { + AWB_EN_W::new(self, 16) + } + #[doc = "Bit 17 - this bit configures hist enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn hist_en(&mut self) -> HIST_EN_W { + HIST_EN_W::new(self, 17) + } + #[doc = "Bit 24 - select input idi data byte_endian_order when isp is bypass, 0: csi_data\\[31:0\\], 1: {\\[7:0\\], \\[15:8\\], \\[23:16\\], \\[31:24\\]}"] + #[inline(always)] + #[must_use] + pub fn byte_endian_order(&mut self) -> BYTE_ENDIAN_ORDER_W { + BYTE_ENDIAN_ORDER_W::new(self, 24) + } + #[doc = "Bits 25:26 - this field configures input data type, 0:RAW8 1:RAW10 2:RAW12"] + #[inline(always)] + #[must_use] + pub fn isp_data_type(&mut self) -> ISP_DATA_TYPE_W { + ISP_DATA_TYPE_W::new(self, 25) + } + #[doc = "Bits 27:28 - this field configures input data source, 0:CSI HOST 1:CAM 2:DMA"] + #[inline(always)] + #[must_use] + pub fn isp_in_src(&mut self) -> ISP_IN_SRC_W { + ISP_IN_SRC_W::new(self, 27) + } + #[doc = "Bits 29:31 - this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: RGB565"] + #[inline(always)] + #[must_use] + pub fn isp_out_type(&mut self) -> ISP_OUT_TYPE_W { + ISP_OUT_TYPE_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "isp module enable control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CNTL_SPEC; +impl crate::RegisterSpec for CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cntl::R`](R) reader structure"] +impl crate::Readable for CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cntl::W`](W) writer structure"] +impl crate::Writable for CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CNTL to value 0x4000_2442"] +impl crate::Resettable for CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x4000_2442; +} diff --git a/esp32p4/src/isp/color_ctrl.rs b/esp32p4/src/isp/color_ctrl.rs new file mode 100644 index 0000000000..9af7c59479 --- /dev/null +++ b/esp32p4/src/isp/color_ctrl.rs @@ -0,0 +1,120 @@ +#[doc = "Register `COLOR_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `COLOR_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `COLOR_SATURATION` reader - this field configures the color saturation value"] +pub type COLOR_SATURATION_R = crate::FieldReader; +#[doc = "Field `COLOR_SATURATION` writer - this field configures the color saturation value"] +pub type COLOR_SATURATION_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLOR_HUE` reader - this field configures the color hue angle"] +pub type COLOR_HUE_R = crate::FieldReader; +#[doc = "Field `COLOR_HUE` writer - this field configures the color hue angle"] +pub type COLOR_HUE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLOR_CONTRAST` reader - this field configures the color contrast value"] +pub type COLOR_CONTRAST_R = crate::FieldReader; +#[doc = "Field `COLOR_CONTRAST` writer - this field configures the color contrast value"] +pub type COLOR_CONTRAST_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLOR_BRIGHTNESS` reader - this field configures the color brightness value, signed 2's complement"] +pub type COLOR_BRIGHTNESS_R = crate::FieldReader; +#[doc = "Field `COLOR_BRIGHTNESS` writer - this field configures the color brightness value, signed 2's complement"] +pub type COLOR_BRIGHTNESS_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the color saturation value"] + #[inline(always)] + pub fn color_saturation(&self) -> COLOR_SATURATION_R { + COLOR_SATURATION_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the color hue angle"] + #[inline(always)] + pub fn color_hue(&self) -> COLOR_HUE_R { + COLOR_HUE_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the color contrast value"] + #[inline(always)] + pub fn color_contrast(&self) -> COLOR_CONTRAST_R { + COLOR_CONTRAST_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the color brightness value, signed 2's complement"] + #[inline(always)] + pub fn color_brightness(&self) -> COLOR_BRIGHTNESS_R { + COLOR_BRIGHTNESS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COLOR_CTRL") + .field( + "color_saturation", + &format_args!("{}", self.color_saturation().bits()), + ) + .field("color_hue", &format_args!("{}", self.color_hue().bits())) + .field( + "color_contrast", + &format_args!("{}", self.color_contrast().bits()), + ) + .field( + "color_brightness", + &format_args!("{}", self.color_brightness().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the color saturation value"] + #[inline(always)] + #[must_use] + pub fn color_saturation(&mut self) -> COLOR_SATURATION_W { + COLOR_SATURATION_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the color hue angle"] + #[inline(always)] + #[must_use] + pub fn color_hue(&mut self) -> COLOR_HUE_W { + COLOR_HUE_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the color contrast value"] + #[inline(always)] + #[must_use] + pub fn color_contrast(&mut self) -> COLOR_CONTRAST_W { + COLOR_CONTRAST_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the color brightness value, signed 2's complement"] + #[inline(always)] + #[must_use] + pub fn color_brightness(&mut self) -> COLOR_BRIGHTNESS_W { + COLOR_BRIGHTNESS_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "color control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`color_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`color_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COLOR_CTRL_SPEC; +impl crate::RegisterSpec for COLOR_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`color_ctrl::R`](R) reader structure"] +impl crate::Readable for COLOR_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`color_ctrl::W`](W) writer structure"] +impl crate::Writable for COLOR_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COLOR_CTRL to value 0x0080_0080"] +impl crate::Resettable for COLOR_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_0080; +} diff --git a/esp32p4/src/isp/demosaic_grad_ratio.rs b/esp32p4/src/isp/demosaic_grad_ratio.rs new file mode 100644 index 0000000000..5db99f062b --- /dev/null +++ b/esp32p4/src/isp/demosaic_grad_ratio.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DEMOSAIC_GRAD_RATIO` reader"] +pub type R = crate::R; +#[doc = "Register `DEMOSAIC_GRAD_RATIO` writer"] +pub type W = crate::W; +#[doc = "Field `DEMOSAIC_GRAD_RATIO` reader - this field configures demosaic gradient select ratio"] +pub type DEMOSAIC_GRAD_RATIO_R = crate::FieldReader; +#[doc = "Field `DEMOSAIC_GRAD_RATIO` writer - this field configures demosaic gradient select ratio"] +pub type DEMOSAIC_GRAD_RATIO_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - this field configures demosaic gradient select ratio"] + #[inline(always)] + pub fn demosaic_grad_ratio(&self) -> DEMOSAIC_GRAD_RATIO_R { + DEMOSAIC_GRAD_RATIO_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEMOSAIC_GRAD_RATIO") + .field( + "demosaic_grad_ratio", + &format_args!("{}", self.demosaic_grad_ratio().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - this field configures demosaic gradient select ratio"] + #[inline(always)] + #[must_use] + pub fn demosaic_grad_ratio(&mut self) -> DEMOSAIC_GRAD_RATIO_W { + DEMOSAIC_GRAD_RATIO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "demosaic gradient select ratio\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`demosaic_grad_ratio::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`demosaic_grad_ratio::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEMOSAIC_GRAD_RATIO_SPEC; +impl crate::RegisterSpec for DEMOSAIC_GRAD_RATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`demosaic_grad_ratio::R`](R) reader structure"] +impl crate::Readable for DEMOSAIC_GRAD_RATIO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`demosaic_grad_ratio::W`](W) writer structure"] +impl crate::Writable for DEMOSAIC_GRAD_RATIO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEMOSAIC_GRAD_RATIO to value 0x10"] +impl crate::Resettable for DEMOSAIC_GRAD_RATIO_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/esp32p4/src/isp/demosaic_matrix_ctrl.rs b/esp32p4/src/isp/demosaic_matrix_ctrl.rs new file mode 100644 index 0000000000..3ac1d806fa --- /dev/null +++ b/esp32p4/src/isp/demosaic_matrix_ctrl.rs @@ -0,0 +1,127 @@ +#[doc = "Register `DEMOSAIC_MATRIX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DEMOSAIC_MATRIX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DEMOSAIC_TAIL_PIXEN_PULSE_TL` reader - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] +pub type DEMOSAIC_TAIL_PIXEN_PULSE_TL_R = crate::FieldReader; +#[doc = "Field `DEMOSAIC_TAIL_PIXEN_PULSE_TL` writer - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] +pub type DEMOSAIC_TAIL_PIXEN_PULSE_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DEMOSAIC_TAIL_PIXEN_PULSE_TH` reader - matrix tail pixen high level threshold, must < hnum-1, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] +pub type DEMOSAIC_TAIL_PIXEN_PULSE_TH_R = crate::FieldReader; +#[doc = "Field `DEMOSAIC_TAIL_PIXEN_PULSE_TH` writer - matrix tail pixen high level threshold, must < hnum-1, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] +pub type DEMOSAIC_TAIL_PIXEN_PULSE_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DEMOSAIC_PADDING_DATA` reader - this field configures demosaic matrix padding data"] +pub type DEMOSAIC_PADDING_DATA_R = crate::FieldReader; +#[doc = "Field `DEMOSAIC_PADDING_DATA` writer - this field configures demosaic matrix padding data"] +pub type DEMOSAIC_PADDING_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DEMOSAIC_PADDING_MODE` reader - this bit configures the padding mode of demosaic matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] +pub type DEMOSAIC_PADDING_MODE_R = crate::BitReader; +#[doc = "Field `DEMOSAIC_PADDING_MODE` writer - this bit configures the padding mode of demosaic matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] +pub type DEMOSAIC_PADDING_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + pub fn demosaic_tail_pixen_pulse_tl(&self) -> DEMOSAIC_TAIL_PIXEN_PULSE_TL_R { + DEMOSAIC_TAIL_PIXEN_PULSE_TL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - matrix tail pixen high level threshold, must < hnum-1, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + pub fn demosaic_tail_pixen_pulse_th(&self) -> DEMOSAIC_TAIL_PIXEN_PULSE_TH_R { + DEMOSAIC_TAIL_PIXEN_PULSE_TH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures demosaic matrix padding data"] + #[inline(always)] + pub fn demosaic_padding_data(&self) -> DEMOSAIC_PADDING_DATA_R { + DEMOSAIC_PADDING_DATA_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - this bit configures the padding mode of demosaic matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] + #[inline(always)] + pub fn demosaic_padding_mode(&self) -> DEMOSAIC_PADDING_MODE_R { + DEMOSAIC_PADDING_MODE_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEMOSAIC_MATRIX_CTRL") + .field( + "demosaic_tail_pixen_pulse_tl", + &format_args!("{}", self.demosaic_tail_pixen_pulse_tl().bits()), + ) + .field( + "demosaic_tail_pixen_pulse_th", + &format_args!("{}", self.demosaic_tail_pixen_pulse_th().bits()), + ) + .field( + "demosaic_padding_data", + &format_args!("{}", self.demosaic_padding_data().bits()), + ) + .field( + "demosaic_padding_mode", + &format_args!("{}", self.demosaic_padding_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + #[must_use] + pub fn demosaic_tail_pixen_pulse_tl( + &mut self, + ) -> DEMOSAIC_TAIL_PIXEN_PULSE_TL_W { + DEMOSAIC_TAIL_PIXEN_PULSE_TL_W::new(self, 0) + } + #[doc = "Bits 8:15 - matrix tail pixen high level threshold, must < hnum-1, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + #[must_use] + pub fn demosaic_tail_pixen_pulse_th( + &mut self, + ) -> DEMOSAIC_TAIL_PIXEN_PULSE_TH_W { + DEMOSAIC_TAIL_PIXEN_PULSE_TH_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures demosaic matrix padding data"] + #[inline(always)] + #[must_use] + pub fn demosaic_padding_data(&mut self) -> DEMOSAIC_PADDING_DATA_W { + DEMOSAIC_PADDING_DATA_W::new(self, 16) + } + #[doc = "Bit 24 - this bit configures the padding mode of demosaic matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] + #[inline(always)] + #[must_use] + pub fn demosaic_padding_mode(&mut self) -> DEMOSAIC_PADDING_MODE_W { + DEMOSAIC_PADDING_MODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "demosaic pix2matrix ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`demosaic_matrix_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`demosaic_matrix_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEMOSAIC_MATRIX_CTRL_SPEC; +impl crate::RegisterSpec for DEMOSAIC_MATRIX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`demosaic_matrix_ctrl::R`](R) reader structure"] +impl crate::Readable for DEMOSAIC_MATRIX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`demosaic_matrix_ctrl::W`](W) writer structure"] +impl crate::Writable for DEMOSAIC_MATRIX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEMOSAIC_MATRIX_CTRL to value 0"] +impl crate::Resettable for DEMOSAIC_MATRIX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/dma_cntl.rs b/esp32p4/src/isp/dma_cntl.rs new file mode 100644 index 0000000000..c9e810975f --- /dev/null +++ b/esp32p4/src/isp/dma_cntl.rs @@ -0,0 +1,128 @@ +#[doc = "Register `DMA_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_EN` writer - write 1 to triger dma to get 1 frame"] +pub type DMA_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_UPDATE` reader - write 1 to update reg_dma_burst_len & reg_dma_data_type"] +pub type DMA_UPDATE_R = crate::BitReader; +#[doc = "Field `DMA_UPDATE` writer - write 1 to update reg_dma_burst_len & reg_dma_data_type"] +pub type DMA_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_DATA_TYPE` reader - this field configures the idi data type for image data"] +pub type DMA_DATA_TYPE_R = crate::FieldReader; +#[doc = "Field `DMA_DATA_TYPE` writer - this field configures the idi data type for image data"] +pub type DMA_DATA_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `DMA_BURST_LEN` reader - this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer"] +pub type DMA_BURST_LEN_R = crate::FieldReader; +#[doc = "Field `DMA_BURST_LEN` writer - this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer"] +pub type DMA_BURST_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `DMA_INTERVAL` reader - this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ..."] +pub type DMA_INTERVAL_R = crate::FieldReader; +#[doc = "Field `DMA_INTERVAL` writer - this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ..."] +pub type DMA_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bit 1 - write 1 to update reg_dma_burst_len & reg_dma_data_type"] + #[inline(always)] + pub fn dma_update(&self) -> DMA_UPDATE_R { + DMA_UPDATE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - this field configures the idi data type for image data"] + #[inline(always)] + pub fn dma_data_type(&self) -> DMA_DATA_TYPE_R { + DMA_DATA_TYPE_R::new(((self.bits >> 2) & 0x3f) as u8) + } + #[doc = "Bits 8:19 - this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer"] + #[inline(always)] + pub fn dma_burst_len(&self) -> DMA_BURST_LEN_R { + DMA_BURST_LEN_R::new(((self.bits >> 8) & 0x0fff) as u16) + } + #[doc = "Bits 20:31 - this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ..."] + #[inline(always)] + pub fn dma_interval(&self) -> DMA_INTERVAL_R { + DMA_INTERVAL_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_CNTL") + .field("dma_update", &format_args!("{}", self.dma_update().bit())) + .field( + "dma_data_type", + &format_args!("{}", self.dma_data_type().bits()), + ) + .field( + "dma_burst_len", + &format_args!("{}", self.dma_burst_len().bits()), + ) + .field( + "dma_interval", + &format_args!("{}", self.dma_interval().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - write 1 to triger dma to get 1 frame"] + #[inline(always)] + #[must_use] + pub fn dma_en(&mut self) -> DMA_EN_W { + DMA_EN_W::new(self, 0) + } + #[doc = "Bit 1 - write 1 to update reg_dma_burst_len & reg_dma_data_type"] + #[inline(always)] + #[must_use] + pub fn dma_update(&mut self) -> DMA_UPDATE_W { + DMA_UPDATE_W::new(self, 1) + } + #[doc = "Bits 2:7 - this field configures the idi data type for image data"] + #[inline(always)] + #[must_use] + pub fn dma_data_type(&mut self) -> DMA_DATA_TYPE_W { + DMA_DATA_TYPE_W::new(self, 2) + } + #[doc = "Bits 8:19 - this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer"] + #[inline(always)] + #[must_use] + pub fn dma_burst_len(&mut self) -> DMA_BURST_LEN_W { + DMA_BURST_LEN_W::new(self, 8) + } + #[doc = "Bits 20:31 - this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ..."] + #[inline(always)] + #[must_use] + pub fn dma_interval(&mut self) -> DMA_INTERVAL_W { + DMA_INTERVAL_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "isp dma source trans control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_CNTL_SPEC; +impl crate::RegisterSpec for DMA_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_cntl::R`](R) reader structure"] +impl crate::Readable for DMA_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_cntl::W`](W) writer structure"] +impl crate::Writable for DMA_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_CNTL to value 0x0010_80a8"] +impl crate::Resettable for DMA_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x0010_80a8; +} diff --git a/esp32p4/src/isp/dma_raw_data.rs b/esp32p4/src/isp/dma_raw_data.rs new file mode 100644 index 0000000000..2daf591282 --- /dev/null +++ b/esp32p4/src/isp/dma_raw_data.rs @@ -0,0 +1,74 @@ +#[doc = "Register `DMA_RAW_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_RAW_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_RAW_NUM_TOTAL` reader - this field configures the the number of 64bits in a frame"] +pub type DMA_RAW_NUM_TOTAL_R = crate::FieldReader; +#[doc = "Field `DMA_RAW_NUM_TOTAL` writer - this field configures the the number of 64bits in a frame"] +pub type DMA_RAW_NUM_TOTAL_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +#[doc = "Field `DMA_RAW_NUM_TOTAL_SET` writer - write 1 to update reg_dma_raw_num_total"] +pub type DMA_RAW_NUM_TOTAL_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:21 - this field configures the the number of 64bits in a frame"] + #[inline(always)] + pub fn dma_raw_num_total(&self) -> DMA_RAW_NUM_TOTAL_R { + DMA_RAW_NUM_TOTAL_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_RAW_DATA") + .field( + "dma_raw_num_total", + &format_args!("{}", self.dma_raw_num_total().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:21 - this field configures the the number of 64bits in a frame"] + #[inline(always)] + #[must_use] + pub fn dma_raw_num_total(&mut self) -> DMA_RAW_NUM_TOTAL_W { + DMA_RAW_NUM_TOTAL_W::new(self, 0) + } + #[doc = "Bit 31 - write 1 to update reg_dma_raw_num_total"] + #[inline(always)] + #[must_use] + pub fn dma_raw_num_total_set(&mut self) -> DMA_RAW_NUM_TOTAL_SET_W { + DMA_RAW_NUM_TOTAL_SET_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "isp dma source total raw number set register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_raw_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_raw_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_RAW_DATA_SPEC; +impl crate::RegisterSpec for DMA_RAW_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_raw_data::R`](R) reader structure"] +impl crate::Readable for DMA_RAW_DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_raw_data::W`](W) writer structure"] +impl crate::Writable for DMA_RAW_DATA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_RAW_DATA to value 0"] +impl crate::Resettable for DMA_RAW_DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/dpc_conf.rs b/esp32p4/src/isp/dpc_conf.rs new file mode 100644 index 0000000000..3b2f87c5d0 --- /dev/null +++ b/esp32p4/src/isp/dpc_conf.rs @@ -0,0 +1,123 @@ +#[doc = "Register `DPC_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `DPC_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `DPC_THRESHOLD_L` reader - this bit configures the threshold to detect black img in check mode, or the low threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1"] +pub type DPC_THRESHOLD_L_R = crate::FieldReader; +#[doc = "Field `DPC_THRESHOLD_L` writer - this bit configures the threshold to detect black img in check mode, or the low threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1"] +pub type DPC_THRESHOLD_L_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DPC_THRESHOLD_H` reader - this bit configures the threshold to detect white img in check mode, or the high threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1"] +pub type DPC_THRESHOLD_H_R = crate::FieldReader; +#[doc = "Field `DPC_THRESHOLD_H` writer - this bit configures the threshold to detect white img in check mode, or the high threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1"] +pub type DPC_THRESHOLD_H_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DPC_FACTOR_DARK` reader - this field configures the dynamic correction method 1 dark factor"] +pub type DPC_FACTOR_DARK_R = crate::FieldReader; +#[doc = "Field `DPC_FACTOR_DARK` writer - this field configures the dynamic correction method 1 dark factor"] +pub type DPC_FACTOR_DARK_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `DPC_FACTOR_BRIG` reader - this field configures the dynamic correction method 1 bright factor"] +pub type DPC_FACTOR_BRIG_R = crate::FieldReader; +#[doc = "Field `DPC_FACTOR_BRIG` writer - this field configures the dynamic correction method 1 bright factor"] +pub type DPC_FACTOR_BRIG_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:7 - this bit configures the threshold to detect black img in check mode, or the low threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1"] + #[inline(always)] + pub fn dpc_threshold_l(&self) -> DPC_THRESHOLD_L_R { + DPC_THRESHOLD_L_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this bit configures the threshold to detect white img in check mode, or the high threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1"] + #[inline(always)] + pub fn dpc_threshold_h(&self) -> DPC_THRESHOLD_H_R { + DPC_THRESHOLD_H_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:21 - this field configures the dynamic correction method 1 dark factor"] + #[inline(always)] + pub fn dpc_factor_dark(&self) -> DPC_FACTOR_DARK_R { + DPC_FACTOR_DARK_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 22:27 - this field configures the dynamic correction method 1 bright factor"] + #[inline(always)] + pub fn dpc_factor_brig(&self) -> DPC_FACTOR_BRIG_R { + DPC_FACTOR_BRIG_R::new(((self.bits >> 22) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPC_CONF") + .field( + "dpc_threshold_l", + &format_args!("{}", self.dpc_threshold_l().bits()), + ) + .field( + "dpc_threshold_h", + &format_args!("{}", self.dpc_threshold_h().bits()), + ) + .field( + "dpc_factor_dark", + &format_args!("{}", self.dpc_factor_dark().bits()), + ) + .field( + "dpc_factor_brig", + &format_args!("{}", self.dpc_factor_brig().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this bit configures the threshold to detect black img in check mode, or the low threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1"] + #[inline(always)] + #[must_use] + pub fn dpc_threshold_l(&mut self) -> DPC_THRESHOLD_L_W { + DPC_THRESHOLD_L_W::new(self, 0) + } + #[doc = "Bits 8:15 - this bit configures the threshold to detect white img in check mode, or the high threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1"] + #[inline(always)] + #[must_use] + pub fn dpc_threshold_h(&mut self) -> DPC_THRESHOLD_H_W { + DPC_THRESHOLD_H_W::new(self, 8) + } + #[doc = "Bits 16:21 - this field configures the dynamic correction method 1 dark factor"] + #[inline(always)] + #[must_use] + pub fn dpc_factor_dark(&mut self) -> DPC_FACTOR_DARK_W { + DPC_FACTOR_DARK_W::new(self, 16) + } + #[doc = "Bits 22:27 - this field configures the dynamic correction method 1 bright factor"] + #[inline(always)] + #[must_use] + pub fn dpc_factor_brig(&mut self) -> DPC_FACTOR_BRIG_W { + DPC_FACTOR_BRIG_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DPC parameter config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpc_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpc_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPC_CONF_SPEC; +impl crate::RegisterSpec for DPC_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpc_conf::R`](R) reader structure"] +impl crate::Readable for DPC_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpc_conf::W`](W) writer structure"] +impl crate::Writable for DPC_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPC_CONF to value 0x0410_3030"] +impl crate::Resettable for DPC_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0410_3030; +} diff --git a/esp32p4/src/isp/dpc_ctrl.rs b/esp32p4/src/isp/dpc_ctrl.rs new file mode 100644 index 0000000000..2bcfc9cf56 --- /dev/null +++ b/esp32p4/src/isp/dpc_ctrl.rs @@ -0,0 +1,155 @@ +#[doc = "Register `DPC_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DPC_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DPC_CHECK_EN` reader - this bit configures the check mode enable. 0: disable, 1: enable"] +pub type DPC_CHECK_EN_R = crate::BitReader; +#[doc = "Field `DPC_CHECK_EN` writer - this bit configures the check mode enable. 0: disable, 1: enable"] +pub type DPC_CHECK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STA_EN` reader - this bit configures the sta dpc enable. 0: disable, 1: enable"] +pub type STA_EN_R = crate::BitReader; +#[doc = "Field `STA_EN` writer - this bit configures the sta dpc enable. 0: disable, 1: enable"] +pub type STA_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DYN_EN` reader - this bit configures the dyn dpc enable. 0: disable, 1: enable"] +pub type DYN_EN_R = crate::BitReader; +#[doc = "Field `DYN_EN` writer - this bit configures the dyn dpc enable. 0: disable, 1: enable"] +pub type DYN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPC_BLACK_EN` reader - this bit configures input image type select when in check mode, 0: white img, 1: black img"] +pub type DPC_BLACK_EN_R = crate::BitReader; +#[doc = "Field `DPC_BLACK_EN` writer - this bit configures input image type select when in check mode, 0: white img, 1: black img"] +pub type DPC_BLACK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPC_METHOD_SEL` reader - this bit configures dyn dpc method select. 0: simple method, 1: hard method"] +pub type DPC_METHOD_SEL_R = crate::BitReader; +#[doc = "Field `DPC_METHOD_SEL` writer - this bit configures dyn dpc method select. 0: simple method, 1: hard method"] +pub type DPC_METHOD_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPC_CHECK_OD_EN` reader - this bit configures output pixel data when in check mode or not. 0: no data output, 1: data output"] +pub type DPC_CHECK_OD_EN_R = crate::BitReader; +#[doc = "Field `DPC_CHECK_OD_EN` writer - this bit configures output pixel data when in check mode or not. 0: no data output, 1: data output"] +pub type DPC_CHECK_OD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - this bit configures the check mode enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn dpc_check_en(&self) -> DPC_CHECK_EN_R { + DPC_CHECK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - this bit configures the sta dpc enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn sta_en(&self) -> STA_EN_R { + STA_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - this bit configures the dyn dpc enable. 0: disable, 1: enable"] + #[inline(always)] + pub fn dyn_en(&self) -> DYN_EN_R { + DYN_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - this bit configures input image type select when in check mode, 0: white img, 1: black img"] + #[inline(always)] + pub fn dpc_black_en(&self) -> DPC_BLACK_EN_R { + DPC_BLACK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - this bit configures dyn dpc method select. 0: simple method, 1: hard method"] + #[inline(always)] + pub fn dpc_method_sel(&self) -> DPC_METHOD_SEL_R { + DPC_METHOD_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - this bit configures output pixel data when in check mode or not. 0: no data output, 1: data output"] + #[inline(always)] + pub fn dpc_check_od_en(&self) -> DPC_CHECK_OD_EN_R { + DPC_CHECK_OD_EN_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPC_CTRL") + .field( + "dpc_check_en", + &format_args!("{}", self.dpc_check_en().bit()), + ) + .field("sta_en", &format_args!("{}", self.sta_en().bit())) + .field("dyn_en", &format_args!("{}", self.dyn_en().bit())) + .field( + "dpc_black_en", + &format_args!("{}", self.dpc_black_en().bit()), + ) + .field( + "dpc_method_sel", + &format_args!("{}", self.dpc_method_sel().bit()), + ) + .field( + "dpc_check_od_en", + &format_args!("{}", self.dpc_check_od_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures the check mode enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn dpc_check_en(&mut self) -> DPC_CHECK_EN_W { + DPC_CHECK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - this bit configures the sta dpc enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn sta_en(&mut self) -> STA_EN_W { + STA_EN_W::new(self, 1) + } + #[doc = "Bit 2 - this bit configures the dyn dpc enable. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn dyn_en(&mut self) -> DYN_EN_W { + DYN_EN_W::new(self, 2) + } + #[doc = "Bit 3 - this bit configures input image type select when in check mode, 0: white img, 1: black img"] + #[inline(always)] + #[must_use] + pub fn dpc_black_en(&mut self) -> DPC_BLACK_EN_W { + DPC_BLACK_EN_W::new(self, 3) + } + #[doc = "Bit 4 - this bit configures dyn dpc method select. 0: simple method, 1: hard method"] + #[inline(always)] + #[must_use] + pub fn dpc_method_sel(&mut self) -> DPC_METHOD_SEL_W { + DPC_METHOD_SEL_W::new(self, 4) + } + #[doc = "Bit 5 - this bit configures output pixel data when in check mode or not. 0: no data output, 1: data output"] + #[inline(always)] + #[must_use] + pub fn dpc_check_od_en(&mut self) -> DPC_CHECK_OD_EN_W { + DPC_CHECK_OD_EN_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DPC mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpc_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpc_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPC_CTRL_SPEC; +impl crate::RegisterSpec for DPC_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpc_ctrl::R`](R) reader structure"] +impl crate::Readable for DPC_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpc_ctrl::W`](W) writer structure"] +impl crate::Writable for DPC_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPC_CTRL to value 0x04"] +impl crate::Resettable for DPC_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/isp/dpc_deadpix_cnt.rs b/esp32p4/src/isp/dpc_deadpix_cnt.rs new file mode 100644 index 0000000000..c2b215740f --- /dev/null +++ b/esp32p4/src/isp/dpc_deadpix_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DPC_DEADPIX_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `DPC_DEADPIX_CNT` reader - this field represents the dead pixel count"] +pub type DPC_DEADPIX_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - this field represents the dead pixel count"] + #[inline(always)] + pub fn dpc_deadpix_cnt(&self) -> DPC_DEADPIX_CNT_R { + DPC_DEADPIX_CNT_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPC_DEADPIX_CNT") + .field( + "dpc_deadpix_cnt", + &format_args!("{}", self.dpc_deadpix_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "DPC dead-pix number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpc_deadpix_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPC_DEADPIX_CNT_SPEC; +impl crate::RegisterSpec for DPC_DEADPIX_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpc_deadpix_cnt::R`](R) reader structure"] +impl crate::Readable for DPC_DEADPIX_CNT_SPEC {} +#[doc = "`reset()` method sets DPC_DEADPIX_CNT to value 0"] +impl crate::Resettable for DPC_DEADPIX_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/dpc_matrix_ctrl.rs b/esp32p4/src/isp/dpc_matrix_ctrl.rs new file mode 100644 index 0000000000..a193ec5bf0 --- /dev/null +++ b/esp32p4/src/isp/dpc_matrix_ctrl.rs @@ -0,0 +1,123 @@ +#[doc = "Register `DPC_MATRIX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DPC_MATRIX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DPC_TAIL_PIXEN_PULSE_TL` reader - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"] +pub type DPC_TAIL_PIXEN_PULSE_TL_R = crate::FieldReader; +#[doc = "Field `DPC_TAIL_PIXEN_PULSE_TL` writer - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"] +pub type DPC_TAIL_PIXEN_PULSE_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DPC_TAIL_PIXEN_PULSE_TH` reader - matrix tail pixen high level threshold, must < hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"] +pub type DPC_TAIL_PIXEN_PULSE_TH_R = crate::FieldReader; +#[doc = "Field `DPC_TAIL_PIXEN_PULSE_TH` writer - matrix tail pixen high level threshold, must < hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"] +pub type DPC_TAIL_PIXEN_PULSE_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DPC_PADDING_DATA` reader - this field configures dpc matrix padding data"] +pub type DPC_PADDING_DATA_R = crate::FieldReader; +#[doc = "Field `DPC_PADDING_DATA` writer - this field configures dpc matrix padding data"] +pub type DPC_PADDING_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DPC_PADDING_MODE` reader - this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] +pub type DPC_PADDING_MODE_R = crate::BitReader; +#[doc = "Field `DPC_PADDING_MODE` writer - this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] +pub type DPC_PADDING_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + pub fn dpc_tail_pixen_pulse_tl(&self) -> DPC_TAIL_PIXEN_PULSE_TL_R { + DPC_TAIL_PIXEN_PULSE_TL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - matrix tail pixen high level threshold, must < hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + pub fn dpc_tail_pixen_pulse_th(&self) -> DPC_TAIL_PIXEN_PULSE_TH_R { + DPC_TAIL_PIXEN_PULSE_TH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures dpc matrix padding data"] + #[inline(always)] + pub fn dpc_padding_data(&self) -> DPC_PADDING_DATA_R { + DPC_PADDING_DATA_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] + #[inline(always)] + pub fn dpc_padding_mode(&self) -> DPC_PADDING_MODE_R { + DPC_PADDING_MODE_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPC_MATRIX_CTRL") + .field( + "dpc_tail_pixen_pulse_tl", + &format_args!("{}", self.dpc_tail_pixen_pulse_tl().bits()), + ) + .field( + "dpc_tail_pixen_pulse_th", + &format_args!("{}", self.dpc_tail_pixen_pulse_th().bits()), + ) + .field( + "dpc_padding_data", + &format_args!("{}", self.dpc_padding_data().bits()), + ) + .field( + "dpc_padding_mode", + &format_args!("{}", self.dpc_padding_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + #[must_use] + pub fn dpc_tail_pixen_pulse_tl(&mut self) -> DPC_TAIL_PIXEN_PULSE_TL_W { + DPC_TAIL_PIXEN_PULSE_TL_W::new(self, 0) + } + #[doc = "Bits 8:15 - matrix tail pixen high level threshold, must < hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + #[must_use] + pub fn dpc_tail_pixen_pulse_th(&mut self) -> DPC_TAIL_PIXEN_PULSE_TH_W { + DPC_TAIL_PIXEN_PULSE_TH_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures dpc matrix padding data"] + #[inline(always)] + #[must_use] + pub fn dpc_padding_data(&mut self) -> DPC_PADDING_DATA_W { + DPC_PADDING_DATA_W::new(self, 16) + } + #[doc = "Bit 24 - this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] + #[inline(always)] + #[must_use] + pub fn dpc_padding_mode(&mut self) -> DPC_PADDING_MODE_W { + DPC_PADDING_MODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dpc pix2matrix ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpc_matrix_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpc_matrix_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPC_MATRIX_CTRL_SPEC; +impl crate::RegisterSpec for DPC_MATRIX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpc_matrix_ctrl::R`](R) reader structure"] +impl crate::Readable for DPC_MATRIX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpc_matrix_ctrl::W`](W) writer structure"] +impl crate::Writable for DPC_MATRIX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPC_MATRIX_CTRL to value 0"] +impl crate::Resettable for DPC_MATRIX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/frame_cfg.rs b/esp32p4/src/isp/frame_cfg.rs new file mode 100644 index 0000000000..cf138397de --- /dev/null +++ b/esp32p4/src/isp/frame_cfg.rs @@ -0,0 +1,133 @@ +#[doc = "Register `FRAME_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FRAME_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `VADR_NUM` reader - this field configures input image size in y-direction, image row number - 1"] +pub type VADR_NUM_R = crate::FieldReader; +#[doc = "Field `VADR_NUM` writer - this field configures input image size in y-direction, image row number - 1"] +pub type VADR_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `HADR_NUM` reader - this field configures input image size in x-direction, image line number - 1"] +pub type HADR_NUM_R = crate::FieldReader; +#[doc = "Field `HADR_NUM` writer - this field configures input image size in x-direction, image line number - 1"] +pub type HADR_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `BAYER_MODE` reader - this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 : GR/BG 11 : RG/GB"] +pub type BAYER_MODE_R = crate::FieldReader; +#[doc = "Field `BAYER_MODE` writer - this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 : GR/BG 11 : RG/GB"] +pub type BAYER_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HSYNC_START_EXIST` reader - this bit configures the line end packet exist or not. 0: not exist, 1: exist"] +pub type HSYNC_START_EXIST_R = crate::BitReader; +#[doc = "Field `HSYNC_START_EXIST` writer - this bit configures the line end packet exist or not. 0: not exist, 1: exist"] +pub type HSYNC_START_EXIST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HSYNC_END_EXIST` reader - this bit configures the line start packet exist or not. 0: not exist, 1: exist"] +pub type HSYNC_END_EXIST_R = crate::BitReader; +#[doc = "Field `HSYNC_END_EXIST` writer - this bit configures the line start packet exist or not. 0: not exist, 1: exist"] +pub type HSYNC_END_EXIST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:11 - this field configures input image size in y-direction, image row number - 1"] + #[inline(always)] + pub fn vadr_num(&self) -> VADR_NUM_R { + VADR_NUM_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:23 - this field configures input image size in x-direction, image line number - 1"] + #[inline(always)] + pub fn hadr_num(&self) -> HADR_NUM_R { + HADR_NUM_R::new(((self.bits >> 12) & 0x0fff) as u16) + } + #[doc = "Bits 27:28 - this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 : GR/BG 11 : RG/GB"] + #[inline(always)] + pub fn bayer_mode(&self) -> BAYER_MODE_R { + BAYER_MODE_R::new(((self.bits >> 27) & 3) as u8) + } + #[doc = "Bit 29 - this bit configures the line end packet exist or not. 0: not exist, 1: exist"] + #[inline(always)] + pub fn hsync_start_exist(&self) -> HSYNC_START_EXIST_R { + HSYNC_START_EXIST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - this bit configures the line start packet exist or not. 0: not exist, 1: exist"] + #[inline(always)] + pub fn hsync_end_exist(&self) -> HSYNC_END_EXIST_R { + HSYNC_END_EXIST_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FRAME_CFG") + .field("vadr_num", &format_args!("{}", self.vadr_num().bits())) + .field("hadr_num", &format_args!("{}", self.hadr_num().bits())) + .field("bayer_mode", &format_args!("{}", self.bayer_mode().bits())) + .field( + "hsync_start_exist", + &format_args!("{}", self.hsync_start_exist().bit()), + ) + .field( + "hsync_end_exist", + &format_args!("{}", self.hsync_end_exist().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures input image size in y-direction, image row number - 1"] + #[inline(always)] + #[must_use] + pub fn vadr_num(&mut self) -> VADR_NUM_W { + VADR_NUM_W::new(self, 0) + } + #[doc = "Bits 12:23 - this field configures input image size in x-direction, image line number - 1"] + #[inline(always)] + #[must_use] + pub fn hadr_num(&mut self) -> HADR_NUM_W { + HADR_NUM_W::new(self, 12) + } + #[doc = "Bits 27:28 - this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 : GR/BG 11 : RG/GB"] + #[inline(always)] + #[must_use] + pub fn bayer_mode(&mut self) -> BAYER_MODE_W { + BAYER_MODE_W::new(self, 27) + } + #[doc = "Bit 29 - this bit configures the line end packet exist or not. 0: not exist, 1: exist"] + #[inline(always)] + #[must_use] + pub fn hsync_start_exist(&mut self) -> HSYNC_START_EXIST_W { + HSYNC_START_EXIST_W::new(self, 29) + } + #[doc = "Bit 30 - this bit configures the line start packet exist or not. 0: not exist, 1: exist"] + #[inline(always)] + #[must_use] + pub fn hsync_end_exist(&mut self) -> HSYNC_END_EXIST_W { + HSYNC_END_EXIST_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "frame control parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frame_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frame_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FRAME_CFG_SPEC; +impl crate::RegisterSpec for FRAME_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`frame_cfg::R`](R) reader structure"] +impl crate::Readable for FRAME_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`frame_cfg::W`](W) writer structure"] +impl crate::Writable for FRAME_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FRAME_CFG to value 0x601e_01e0"] +impl crate::Resettable for FRAME_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x601e_01e0; +} diff --git a/esp32p4/src/isp/gamma_bx1.rs b/esp32p4/src/isp/gamma_bx1.rs new file mode 100644 index 0000000000..69ff89a9a6 --- /dev/null +++ b/esp32p4/src/isp/gamma_bx1.rs @@ -0,0 +1,199 @@ +#[doc = "Register `GAMMA_BX1` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_BX1` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_B_X07` reader - this field configures the point 7 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X07_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X07` writer - this field configures the point 7 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X07_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X06` reader - this field configures the point 6 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X06_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X06` writer - this field configures the point 6 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X06_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X05` reader - this field configures the point 5 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X05_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X05` writer - this field configures the point 5 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X05_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X04` reader - this field configures the point 4 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X04_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X04` writer - this field configures the point 4 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X04_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X03` reader - this field configures the point 3 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X03_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X03` writer - this field configures the point 3 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X03_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X02` reader - this field configures the point 2 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X02_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X02` writer - this field configures the point 2 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X02_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X01` reader - this field configures the point 1 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X01_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X01` writer - this field configures the point 1 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X01_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X00` reader - this field configures the point 0 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X00_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X00` writer - this field configures the point 0 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X00_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - this field configures the point 7 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x07(&self) -> GAMMA_B_X07_R { + GAMMA_B_X07_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - this field configures the point 6 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x06(&self) -> GAMMA_B_X06_R { + GAMMA_B_X06_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - this field configures the point 5 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x05(&self) -> GAMMA_B_X05_R { + GAMMA_B_X05_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - this field configures the point 4 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x04(&self) -> GAMMA_B_X04_R { + GAMMA_B_X04_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - this field configures the point 3 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x03(&self) -> GAMMA_B_X03_R { + GAMMA_B_X03_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - this field configures the point 2 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x02(&self) -> GAMMA_B_X02_R { + GAMMA_B_X02_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - this field configures the point 1 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x01(&self) -> GAMMA_B_X01_R { + GAMMA_B_X01_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - this field configures the point 0 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x00(&self) -> GAMMA_B_X00_R { + GAMMA_B_X00_R::new(((self.bits >> 21) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_BX1") + .field( + "gamma_b_x07", + &format_args!("{}", self.gamma_b_x07().bits()), + ) + .field( + "gamma_b_x06", + &format_args!("{}", self.gamma_b_x06().bits()), + ) + .field( + "gamma_b_x05", + &format_args!("{}", self.gamma_b_x05().bits()), + ) + .field( + "gamma_b_x04", + &format_args!("{}", self.gamma_b_x04().bits()), + ) + .field( + "gamma_b_x03", + &format_args!("{}", self.gamma_b_x03().bits()), + ) + .field( + "gamma_b_x02", + &format_args!("{}", self.gamma_b_x02().bits()), + ) + .field( + "gamma_b_x01", + &format_args!("{}", self.gamma_b_x01().bits()), + ) + .field( + "gamma_b_x00", + &format_args!("{}", self.gamma_b_x00().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - this field configures the point 7 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x07(&mut self) -> GAMMA_B_X07_W { + GAMMA_B_X07_W::new(self, 0) + } + #[doc = "Bits 3:5 - this field configures the point 6 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x06(&mut self) -> GAMMA_B_X06_W { + GAMMA_B_X06_W::new(self, 3) + } + #[doc = "Bits 6:8 - this field configures the point 5 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x05(&mut self) -> GAMMA_B_X05_W { + GAMMA_B_X05_W::new(self, 6) + } + #[doc = "Bits 9:11 - this field configures the point 4 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x04(&mut self) -> GAMMA_B_X04_W { + GAMMA_B_X04_W::new(self, 9) + } + #[doc = "Bits 12:14 - this field configures the point 3 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x03(&mut self) -> GAMMA_B_X03_W { + GAMMA_B_X03_W::new(self, 12) + } + #[doc = "Bits 15:17 - this field configures the point 2 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x02(&mut self) -> GAMMA_B_X02_W { + GAMMA_B_X02_W::new(self, 15) + } + #[doc = "Bits 18:20 - this field configures the point 1 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x01(&mut self) -> GAMMA_B_X01_W { + GAMMA_B_X01_W::new(self, 18) + } + #[doc = "Bits 21:23 - this field configures the point 0 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x00(&mut self) -> GAMMA_B_X00_W { + GAMMA_B_X00_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of X-axis of b channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_bx1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_bx1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_BX1_SPEC; +impl crate::RegisterSpec for GAMMA_BX1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_bx1::R`](R) reader structure"] +impl crate::Readable for GAMMA_BX1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_bx1::W`](W) writer structure"] +impl crate::Writable for GAMMA_BX1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_BX1 to value 0x0092_4924"] +impl crate::Resettable for GAMMA_BX1_SPEC { + const RESET_VALUE: Self::Ux = 0x0092_4924; +} diff --git a/esp32p4/src/isp/gamma_bx2.rs b/esp32p4/src/isp/gamma_bx2.rs new file mode 100644 index 0000000000..31aa44ea23 --- /dev/null +++ b/esp32p4/src/isp/gamma_bx2.rs @@ -0,0 +1,199 @@ +#[doc = "Register `GAMMA_BX2` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_BX2` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_B_X0F` reader - this field configures the point 15 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0F_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X0F` writer - this field configures the point 15 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0F_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X0E` reader - this field configures the point 14 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0E_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X0E` writer - this field configures the point 14 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0E_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X0D` reader - this field configures the point 13 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0D_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X0D` writer - this field configures the point 13 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0D_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X0C` reader - this field configures the point 12 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0C_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X0C` writer - this field configures the point 12 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0C_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X0B` reader - this field configures the point 11 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0B_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X0B` writer - this field configures the point 11 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0B_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X0A` reader - this field configures the point 10 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0A_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X0A` writer - this field configures the point 10 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X0A_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X09` reader - this field configures the point 9 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X09_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X09` writer - this field configures the point 9 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X09_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_B_X08` reader - this field configures the point 8 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X08_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_X08` writer - this field configures the point 8 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_B_X08_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - this field configures the point 15 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x0f(&self) -> GAMMA_B_X0F_R { + GAMMA_B_X0F_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - this field configures the point 14 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x0e(&self) -> GAMMA_B_X0E_R { + GAMMA_B_X0E_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - this field configures the point 13 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x0d(&self) -> GAMMA_B_X0D_R { + GAMMA_B_X0D_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - this field configures the point 12 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x0c(&self) -> GAMMA_B_X0C_R { + GAMMA_B_X0C_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - this field configures the point 11 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x0b(&self) -> GAMMA_B_X0B_R { + GAMMA_B_X0B_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - this field configures the point 10 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x0a(&self) -> GAMMA_B_X0A_R { + GAMMA_B_X0A_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - this field configures the point 9 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x09(&self) -> GAMMA_B_X09_R { + GAMMA_B_X09_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - this field configures the point 8 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_b_x08(&self) -> GAMMA_B_X08_R { + GAMMA_B_X08_R::new(((self.bits >> 21) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_BX2") + .field( + "gamma_b_x0f", + &format_args!("{}", self.gamma_b_x0f().bits()), + ) + .field( + "gamma_b_x0e", + &format_args!("{}", self.gamma_b_x0e().bits()), + ) + .field( + "gamma_b_x0d", + &format_args!("{}", self.gamma_b_x0d().bits()), + ) + .field( + "gamma_b_x0c", + &format_args!("{}", self.gamma_b_x0c().bits()), + ) + .field( + "gamma_b_x0b", + &format_args!("{}", self.gamma_b_x0b().bits()), + ) + .field( + "gamma_b_x0a", + &format_args!("{}", self.gamma_b_x0a().bits()), + ) + .field( + "gamma_b_x09", + &format_args!("{}", self.gamma_b_x09().bits()), + ) + .field( + "gamma_b_x08", + &format_args!("{}", self.gamma_b_x08().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - this field configures the point 15 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x0f(&mut self) -> GAMMA_B_X0F_W { + GAMMA_B_X0F_W::new(self, 0) + } + #[doc = "Bits 3:5 - this field configures the point 14 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x0e(&mut self) -> GAMMA_B_X0E_W { + GAMMA_B_X0E_W::new(self, 3) + } + #[doc = "Bits 6:8 - this field configures the point 13 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x0d(&mut self) -> GAMMA_B_X0D_W { + GAMMA_B_X0D_W::new(self, 6) + } + #[doc = "Bits 9:11 - this field configures the point 12 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x0c(&mut self) -> GAMMA_B_X0C_W { + GAMMA_B_X0C_W::new(self, 9) + } + #[doc = "Bits 12:14 - this field configures the point 11 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x0b(&mut self) -> GAMMA_B_X0B_W { + GAMMA_B_X0B_W::new(self, 12) + } + #[doc = "Bits 15:17 - this field configures the point 10 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x0a(&mut self) -> GAMMA_B_X0A_W { + GAMMA_B_X0A_W::new(self, 15) + } + #[doc = "Bits 18:20 - this field configures the point 9 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x09(&mut self) -> GAMMA_B_X09_W { + GAMMA_B_X09_W::new(self, 18) + } + #[doc = "Bits 21:23 - this field configures the point 8 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_b_x08(&mut self) -> GAMMA_B_X08_W { + GAMMA_B_X08_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of X-axis of b channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_bx2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_bx2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_BX2_SPEC; +impl crate::RegisterSpec for GAMMA_BX2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_bx2::R`](R) reader structure"] +impl crate::Readable for GAMMA_BX2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_bx2::W`](W) writer structure"] +impl crate::Writable for GAMMA_BX2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_BX2 to value 0x0092_4924"] +impl crate::Resettable for GAMMA_BX2_SPEC { + const RESET_VALUE: Self::Ux = 0x0092_4924; +} diff --git a/esp32p4/src/isp/gamma_by1.rs b/esp32p4/src/isp/gamma_by1.rs new file mode 100644 index 0000000000..27feacbf08 --- /dev/null +++ b/esp32p4/src/isp/gamma_by1.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_BY1` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_BY1` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_B_Y03` reader - this field configures the point 3 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y03_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y03` writer - this field configures the point 3 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y03_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y02` reader - this field configures the point 2 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y02_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y02` writer - this field configures the point 2 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y02_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y01` reader - this field configures the point 1 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y01_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y01` writer - this field configures the point 1 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y01_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y00` reader - this field configures the point 0 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y00_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y00` writer - this field configures the point 0 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y00_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 3 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y03(&self) -> GAMMA_B_Y03_R { + GAMMA_B_Y03_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 2 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y02(&self) -> GAMMA_B_Y02_R { + GAMMA_B_Y02_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 1 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y01(&self) -> GAMMA_B_Y01_R { + GAMMA_B_Y01_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 0 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y00(&self) -> GAMMA_B_Y00_R { + GAMMA_B_Y00_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_BY1") + .field( + "gamma_b_y03", + &format_args!("{}", self.gamma_b_y03().bits()), + ) + .field( + "gamma_b_y02", + &format_args!("{}", self.gamma_b_y02().bits()), + ) + .field( + "gamma_b_y01", + &format_args!("{}", self.gamma_b_y01().bits()), + ) + .field( + "gamma_b_y00", + &format_args!("{}", self.gamma_b_y00().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 3 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y03(&mut self) -> GAMMA_B_Y03_W { + GAMMA_B_Y03_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 2 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y02(&mut self) -> GAMMA_B_Y02_W { + GAMMA_B_Y02_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 1 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y01(&mut self) -> GAMMA_B_Y01_W { + GAMMA_B_Y01_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 0 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y00(&mut self) -> GAMMA_B_Y00_W { + GAMMA_B_Y00_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of b channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_by1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_by1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_BY1_SPEC; +impl crate::RegisterSpec for GAMMA_BY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_by1::R`](R) reader structure"] +impl crate::Readable for GAMMA_BY1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_by1::W`](W) writer structure"] +impl crate::Writable for GAMMA_BY1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_BY1 to value 0x1020_3040"] +impl crate::Resettable for GAMMA_BY1_SPEC { + const RESET_VALUE: Self::Ux = 0x1020_3040; +} diff --git a/esp32p4/src/isp/gamma_by2.rs b/esp32p4/src/isp/gamma_by2.rs new file mode 100644 index 0000000000..5162a28ae6 --- /dev/null +++ b/esp32p4/src/isp/gamma_by2.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_BY2` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_BY2` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_B_Y07` reader - this field configures the point 7 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y07_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y07` writer - this field configures the point 7 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y07_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y06` reader - this field configures the point 6 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y06_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y06` writer - this field configures the point 6 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y06_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y05` reader - this field configures the point 5 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y05_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y05` writer - this field configures the point 5 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y05_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y04` reader - this field configures the point 4 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y04_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y04` writer - this field configures the point 4 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y04_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 7 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y07(&self) -> GAMMA_B_Y07_R { + GAMMA_B_Y07_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 6 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y06(&self) -> GAMMA_B_Y06_R { + GAMMA_B_Y06_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 5 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y05(&self) -> GAMMA_B_Y05_R { + GAMMA_B_Y05_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 4 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y04(&self) -> GAMMA_B_Y04_R { + GAMMA_B_Y04_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_BY2") + .field( + "gamma_b_y07", + &format_args!("{}", self.gamma_b_y07().bits()), + ) + .field( + "gamma_b_y06", + &format_args!("{}", self.gamma_b_y06().bits()), + ) + .field( + "gamma_b_y05", + &format_args!("{}", self.gamma_b_y05().bits()), + ) + .field( + "gamma_b_y04", + &format_args!("{}", self.gamma_b_y04().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 7 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y07(&mut self) -> GAMMA_B_Y07_W { + GAMMA_B_Y07_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 6 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y06(&mut self) -> GAMMA_B_Y06_W { + GAMMA_B_Y06_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 5 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y05(&mut self) -> GAMMA_B_Y05_W { + GAMMA_B_Y05_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 4 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y04(&mut self) -> GAMMA_B_Y04_W { + GAMMA_B_Y04_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of b channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_by2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_by2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_BY2_SPEC; +impl crate::RegisterSpec for GAMMA_BY2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_by2::R`](R) reader structure"] +impl crate::Readable for GAMMA_BY2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_by2::W`](W) writer structure"] +impl crate::Writable for GAMMA_BY2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_BY2 to value 0x5060_7080"] +impl crate::Resettable for GAMMA_BY2_SPEC { + const RESET_VALUE: Self::Ux = 0x5060_7080; +} diff --git a/esp32p4/src/isp/gamma_by3.rs b/esp32p4/src/isp/gamma_by3.rs new file mode 100644 index 0000000000..49f1735b64 --- /dev/null +++ b/esp32p4/src/isp/gamma_by3.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_BY3` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_BY3` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_B_Y0B` reader - this field configures the point 11 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0B_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y0B` writer - this field configures the point 11 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0B_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y0A` reader - this field configures the point 10 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0A_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y0A` writer - this field configures the point 10 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0A_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y09` reader - this field configures the point 9 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y09_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y09` writer - this field configures the point 9 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y09_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y08` reader - this field configures the point 8 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y08_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y08` writer - this field configures the point 8 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y08_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 11 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y0b(&self) -> GAMMA_B_Y0B_R { + GAMMA_B_Y0B_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 10 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y0a(&self) -> GAMMA_B_Y0A_R { + GAMMA_B_Y0A_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 9 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y09(&self) -> GAMMA_B_Y09_R { + GAMMA_B_Y09_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 8 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y08(&self) -> GAMMA_B_Y08_R { + GAMMA_B_Y08_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_BY3") + .field( + "gamma_b_y0b", + &format_args!("{}", self.gamma_b_y0b().bits()), + ) + .field( + "gamma_b_y0a", + &format_args!("{}", self.gamma_b_y0a().bits()), + ) + .field( + "gamma_b_y09", + &format_args!("{}", self.gamma_b_y09().bits()), + ) + .field( + "gamma_b_y08", + &format_args!("{}", self.gamma_b_y08().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 11 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y0b(&mut self) -> GAMMA_B_Y0B_W { + GAMMA_B_Y0B_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 10 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y0a(&mut self) -> GAMMA_B_Y0A_W { + GAMMA_B_Y0A_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 9 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y09(&mut self) -> GAMMA_B_Y09_W { + GAMMA_B_Y09_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 8 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y08(&mut self) -> GAMMA_B_Y08_W { + GAMMA_B_Y08_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of b channel gamma curve register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_by3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_by3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_BY3_SPEC; +impl crate::RegisterSpec for GAMMA_BY3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_by3::R`](R) reader structure"] +impl crate::Readable for GAMMA_BY3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_by3::W`](W) writer structure"] +impl crate::Writable for GAMMA_BY3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_BY3 to value 0x90a0_b0c0"] +impl crate::Resettable for GAMMA_BY3_SPEC { + const RESET_VALUE: Self::Ux = 0x90a0_b0c0; +} diff --git a/esp32p4/src/isp/gamma_by4.rs b/esp32p4/src/isp/gamma_by4.rs new file mode 100644 index 0000000000..93df6610e8 --- /dev/null +++ b/esp32p4/src/isp/gamma_by4.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_BY4` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_BY4` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_B_Y0F` reader - this field configures the point 15 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0F_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y0F` writer - this field configures the point 15 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0F_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y0E` reader - this field configures the point 14 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0E_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y0E` writer - this field configures the point 14 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0E_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y0D` reader - this field configures the point 13 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0D_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y0D` writer - this field configures the point 13 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0D_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_B_Y0C` reader - this field configures the point 12 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0C_R = crate::FieldReader; +#[doc = "Field `GAMMA_B_Y0C` writer - this field configures the point 12 of Y-axis of b channel gamma curve"] +pub type GAMMA_B_Y0C_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 15 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y0f(&self) -> GAMMA_B_Y0F_R { + GAMMA_B_Y0F_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 14 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y0e(&self) -> GAMMA_B_Y0E_R { + GAMMA_B_Y0E_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 13 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y0d(&self) -> GAMMA_B_Y0D_R { + GAMMA_B_Y0D_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 12 of Y-axis of b channel gamma curve"] + #[inline(always)] + pub fn gamma_b_y0c(&self) -> GAMMA_B_Y0C_R { + GAMMA_B_Y0C_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_BY4") + .field( + "gamma_b_y0f", + &format_args!("{}", self.gamma_b_y0f().bits()), + ) + .field( + "gamma_b_y0e", + &format_args!("{}", self.gamma_b_y0e().bits()), + ) + .field( + "gamma_b_y0d", + &format_args!("{}", self.gamma_b_y0d().bits()), + ) + .field( + "gamma_b_y0c", + &format_args!("{}", self.gamma_b_y0c().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 15 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y0f(&mut self) -> GAMMA_B_Y0F_W { + GAMMA_B_Y0F_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 14 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y0e(&mut self) -> GAMMA_B_Y0E_W { + GAMMA_B_Y0E_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 13 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y0d(&mut self) -> GAMMA_B_Y0D_W { + GAMMA_B_Y0D_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 12 of Y-axis of b channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_b_y0c(&mut self) -> GAMMA_B_Y0C_W { + GAMMA_B_Y0C_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of b channel gamma curve register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_by4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_by4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_BY4_SPEC; +impl crate::RegisterSpec for GAMMA_BY4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_by4::R`](R) reader structure"] +impl crate::Readable for GAMMA_BY4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_by4::W`](W) writer structure"] +impl crate::Writable for GAMMA_BY4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_BY4 to value 0xd0e0_f0ff"] +impl crate::Resettable for GAMMA_BY4_SPEC { + const RESET_VALUE: Self::Ux = 0xd0e0_f0ff; +} diff --git a/esp32p4/src/isp/gamma_ctrl.rs b/esp32p4/src/isp/gamma_ctrl.rs new file mode 100644 index 0000000000..71529028fd --- /dev/null +++ b/esp32p4/src/isp/gamma_ctrl.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_UPDATE` reader - Indicates that gamma register configuration is complete"] +pub type GAMMA_UPDATE_R = crate::BitReader; +#[doc = "Field `GAMMA_UPDATE` writer - Indicates that gamma register configuration is complete"] +pub type GAMMA_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_B_LAST_CORRECT` reader - this bit configures enable of last b segment correcction. 0: disable, 1: enable"] +pub type GAMMA_B_LAST_CORRECT_R = crate::BitReader; +#[doc = "Field `GAMMA_B_LAST_CORRECT` writer - this bit configures enable of last b segment correcction. 0: disable, 1: enable"] +pub type GAMMA_B_LAST_CORRECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_G_LAST_CORRECT` reader - this bit configures enable of last g segment correcction. 0: disable, 1: enable"] +pub type GAMMA_G_LAST_CORRECT_R = crate::BitReader; +#[doc = "Field `GAMMA_G_LAST_CORRECT` writer - this bit configures enable of last g segment correcction. 0: disable, 1: enable"] +pub type GAMMA_G_LAST_CORRECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_R_LAST_CORRECT` reader - this bit configures enable of last r segment correcction. 0: disable, 1: enable"] +pub type GAMMA_R_LAST_CORRECT_R = crate::BitReader; +#[doc = "Field `GAMMA_R_LAST_CORRECT` writer - this bit configures enable of last r segment correcction. 0: disable, 1: enable"] +pub type GAMMA_R_LAST_CORRECT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Indicates that gamma register configuration is complete"] + #[inline(always)] + pub fn gamma_update(&self) -> GAMMA_UPDATE_R { + GAMMA_UPDATE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - this bit configures enable of last b segment correcction. 0: disable, 1: enable"] + #[inline(always)] + pub fn gamma_b_last_correct(&self) -> GAMMA_B_LAST_CORRECT_R { + GAMMA_B_LAST_CORRECT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - this bit configures enable of last g segment correcction. 0: disable, 1: enable"] + #[inline(always)] + pub fn gamma_g_last_correct(&self) -> GAMMA_G_LAST_CORRECT_R { + GAMMA_G_LAST_CORRECT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - this bit configures enable of last r segment correcction. 0: disable, 1: enable"] + #[inline(always)] + pub fn gamma_r_last_correct(&self) -> GAMMA_R_LAST_CORRECT_R { + GAMMA_R_LAST_CORRECT_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_CTRL") + .field( + "gamma_update", + &format_args!("{}", self.gamma_update().bit()), + ) + .field( + "gamma_b_last_correct", + &format_args!("{}", self.gamma_b_last_correct().bit()), + ) + .field( + "gamma_g_last_correct", + &format_args!("{}", self.gamma_g_last_correct().bit()), + ) + .field( + "gamma_r_last_correct", + &format_args!("{}", self.gamma_r_last_correct().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Indicates that gamma register configuration is complete"] + #[inline(always)] + #[must_use] + pub fn gamma_update(&mut self) -> GAMMA_UPDATE_W { + GAMMA_UPDATE_W::new(self, 0) + } + #[doc = "Bit 1 - this bit configures enable of last b segment correcction. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn gamma_b_last_correct(&mut self) -> GAMMA_B_LAST_CORRECT_W { + GAMMA_B_LAST_CORRECT_W::new(self, 1) + } + #[doc = "Bit 2 - this bit configures enable of last g segment correcction. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn gamma_g_last_correct(&mut self) -> GAMMA_G_LAST_CORRECT_W { + GAMMA_G_LAST_CORRECT_W::new(self, 2) + } + #[doc = "Bit 3 - this bit configures enable of last r segment correcction. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn gamma_r_last_correct(&mut self) -> GAMMA_R_LAST_CORRECT_W { + GAMMA_R_LAST_CORRECT_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "gamma control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_CTRL_SPEC; +impl crate::RegisterSpec for GAMMA_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_ctrl::R`](R) reader structure"] +impl crate::Readable for GAMMA_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_ctrl::W`](W) writer structure"] +impl crate::Writable for GAMMA_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_CTRL to value 0x0e"] +impl crate::Resettable for GAMMA_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0e; +} diff --git a/esp32p4/src/isp/gamma_gx1.rs b/esp32p4/src/isp/gamma_gx1.rs new file mode 100644 index 0000000000..231f1df6a1 --- /dev/null +++ b/esp32p4/src/isp/gamma_gx1.rs @@ -0,0 +1,199 @@ +#[doc = "Register `GAMMA_GX1` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_GX1` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_G_X07` reader - this field configures the point 7 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X07_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X07` writer - this field configures the point 7 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X07_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X06` reader - this field configures the point 6 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X06_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X06` writer - this field configures the point 6 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X06_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X05` reader - this field configures the point 5 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X05_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X05` writer - this field configures the point 5 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X05_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X04` reader - this field configures the point 4 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X04_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X04` writer - this field configures the point 4 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X04_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X03` reader - this field configures the point 3 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X03_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X03` writer - this field configures the point 3 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X03_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X02` reader - this field configures the point 2 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X02_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X02` writer - this field configures the point 2 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X02_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X01` reader - this field configures the point 1 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X01_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X01` writer - this field configures the point 1 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X01_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X00` reader - this field configures the point 0 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X00_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X00` writer - this field configures the point 0 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X00_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - this field configures the point 7 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x07(&self) -> GAMMA_G_X07_R { + GAMMA_G_X07_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - this field configures the point 6 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x06(&self) -> GAMMA_G_X06_R { + GAMMA_G_X06_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - this field configures the point 5 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x05(&self) -> GAMMA_G_X05_R { + GAMMA_G_X05_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - this field configures the point 4 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x04(&self) -> GAMMA_G_X04_R { + GAMMA_G_X04_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - this field configures the point 3 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x03(&self) -> GAMMA_G_X03_R { + GAMMA_G_X03_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - this field configures the point 2 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x02(&self) -> GAMMA_G_X02_R { + GAMMA_G_X02_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - this field configures the point 1 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x01(&self) -> GAMMA_G_X01_R { + GAMMA_G_X01_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - this field configures the point 0 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x00(&self) -> GAMMA_G_X00_R { + GAMMA_G_X00_R::new(((self.bits >> 21) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_GX1") + .field( + "gamma_g_x07", + &format_args!("{}", self.gamma_g_x07().bits()), + ) + .field( + "gamma_g_x06", + &format_args!("{}", self.gamma_g_x06().bits()), + ) + .field( + "gamma_g_x05", + &format_args!("{}", self.gamma_g_x05().bits()), + ) + .field( + "gamma_g_x04", + &format_args!("{}", self.gamma_g_x04().bits()), + ) + .field( + "gamma_g_x03", + &format_args!("{}", self.gamma_g_x03().bits()), + ) + .field( + "gamma_g_x02", + &format_args!("{}", self.gamma_g_x02().bits()), + ) + .field( + "gamma_g_x01", + &format_args!("{}", self.gamma_g_x01().bits()), + ) + .field( + "gamma_g_x00", + &format_args!("{}", self.gamma_g_x00().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - this field configures the point 7 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x07(&mut self) -> GAMMA_G_X07_W { + GAMMA_G_X07_W::new(self, 0) + } + #[doc = "Bits 3:5 - this field configures the point 6 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x06(&mut self) -> GAMMA_G_X06_W { + GAMMA_G_X06_W::new(self, 3) + } + #[doc = "Bits 6:8 - this field configures the point 5 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x05(&mut self) -> GAMMA_G_X05_W { + GAMMA_G_X05_W::new(self, 6) + } + #[doc = "Bits 9:11 - this field configures the point 4 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x04(&mut self) -> GAMMA_G_X04_W { + GAMMA_G_X04_W::new(self, 9) + } + #[doc = "Bits 12:14 - this field configures the point 3 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x03(&mut self) -> GAMMA_G_X03_W { + GAMMA_G_X03_W::new(self, 12) + } + #[doc = "Bits 15:17 - this field configures the point 2 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x02(&mut self) -> GAMMA_G_X02_W { + GAMMA_G_X02_W::new(self, 15) + } + #[doc = "Bits 18:20 - this field configures the point 1 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x01(&mut self) -> GAMMA_G_X01_W { + GAMMA_G_X01_W::new(self, 18) + } + #[doc = "Bits 21:23 - this field configures the point 0 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x00(&mut self) -> GAMMA_G_X00_W { + GAMMA_G_X00_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of X-axis of g channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gx1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gx1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_GX1_SPEC; +impl crate::RegisterSpec for GAMMA_GX1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_gx1::R`](R) reader structure"] +impl crate::Readable for GAMMA_GX1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_gx1::W`](W) writer structure"] +impl crate::Writable for GAMMA_GX1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_GX1 to value 0x0092_4924"] +impl crate::Resettable for GAMMA_GX1_SPEC { + const RESET_VALUE: Self::Ux = 0x0092_4924; +} diff --git a/esp32p4/src/isp/gamma_gx2.rs b/esp32p4/src/isp/gamma_gx2.rs new file mode 100644 index 0000000000..0de5c6a136 --- /dev/null +++ b/esp32p4/src/isp/gamma_gx2.rs @@ -0,0 +1,199 @@ +#[doc = "Register `GAMMA_GX2` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_GX2` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_G_X0F` reader - this field configures the point 15 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0F_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X0F` writer - this field configures the point 15 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0F_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X0E` reader - this field configures the point 14 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0E_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X0E` writer - this field configures the point 14 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0E_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X0D` reader - this field configures the point 13 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0D_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X0D` writer - this field configures the point 13 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0D_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X0C` reader - this field configures the point 12 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0C_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X0C` writer - this field configures the point 12 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0C_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X0B` reader - this field configures the point 11 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0B_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X0B` writer - this field configures the point 11 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0B_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X0A` reader - this field configures the point 10 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0A_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X0A` writer - this field configures the point 10 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X0A_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X09` reader - this field configures the point 9 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X09_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X09` writer - this field configures the point 9 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X09_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_G_X08` reader - this field configures the point 8 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X08_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_X08` writer - this field configures the point 8 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_G_X08_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - this field configures the point 15 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x0f(&self) -> GAMMA_G_X0F_R { + GAMMA_G_X0F_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - this field configures the point 14 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x0e(&self) -> GAMMA_G_X0E_R { + GAMMA_G_X0E_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - this field configures the point 13 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x0d(&self) -> GAMMA_G_X0D_R { + GAMMA_G_X0D_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - this field configures the point 12 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x0c(&self) -> GAMMA_G_X0C_R { + GAMMA_G_X0C_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - this field configures the point 11 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x0b(&self) -> GAMMA_G_X0B_R { + GAMMA_G_X0B_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - this field configures the point 10 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x0a(&self) -> GAMMA_G_X0A_R { + GAMMA_G_X0A_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - this field configures the point 9 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x09(&self) -> GAMMA_G_X09_R { + GAMMA_G_X09_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - this field configures the point 8 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_g_x08(&self) -> GAMMA_G_X08_R { + GAMMA_G_X08_R::new(((self.bits >> 21) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_GX2") + .field( + "gamma_g_x0f", + &format_args!("{}", self.gamma_g_x0f().bits()), + ) + .field( + "gamma_g_x0e", + &format_args!("{}", self.gamma_g_x0e().bits()), + ) + .field( + "gamma_g_x0d", + &format_args!("{}", self.gamma_g_x0d().bits()), + ) + .field( + "gamma_g_x0c", + &format_args!("{}", self.gamma_g_x0c().bits()), + ) + .field( + "gamma_g_x0b", + &format_args!("{}", self.gamma_g_x0b().bits()), + ) + .field( + "gamma_g_x0a", + &format_args!("{}", self.gamma_g_x0a().bits()), + ) + .field( + "gamma_g_x09", + &format_args!("{}", self.gamma_g_x09().bits()), + ) + .field( + "gamma_g_x08", + &format_args!("{}", self.gamma_g_x08().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - this field configures the point 15 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x0f(&mut self) -> GAMMA_G_X0F_W { + GAMMA_G_X0F_W::new(self, 0) + } + #[doc = "Bits 3:5 - this field configures the point 14 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x0e(&mut self) -> GAMMA_G_X0E_W { + GAMMA_G_X0E_W::new(self, 3) + } + #[doc = "Bits 6:8 - this field configures the point 13 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x0d(&mut self) -> GAMMA_G_X0D_W { + GAMMA_G_X0D_W::new(self, 6) + } + #[doc = "Bits 9:11 - this field configures the point 12 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x0c(&mut self) -> GAMMA_G_X0C_W { + GAMMA_G_X0C_W::new(self, 9) + } + #[doc = "Bits 12:14 - this field configures the point 11 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x0b(&mut self) -> GAMMA_G_X0B_W { + GAMMA_G_X0B_W::new(self, 12) + } + #[doc = "Bits 15:17 - this field configures the point 10 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x0a(&mut self) -> GAMMA_G_X0A_W { + GAMMA_G_X0A_W::new(self, 15) + } + #[doc = "Bits 18:20 - this field configures the point 9 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x09(&mut self) -> GAMMA_G_X09_W { + GAMMA_G_X09_W::new(self, 18) + } + #[doc = "Bits 21:23 - this field configures the point 8 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_g_x08(&mut self) -> GAMMA_G_X08_W { + GAMMA_G_X08_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of X-axis of g channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gx2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gx2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_GX2_SPEC; +impl crate::RegisterSpec for GAMMA_GX2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_gx2::R`](R) reader structure"] +impl crate::Readable for GAMMA_GX2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_gx2::W`](W) writer structure"] +impl crate::Writable for GAMMA_GX2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_GX2 to value 0x0092_4924"] +impl crate::Resettable for GAMMA_GX2_SPEC { + const RESET_VALUE: Self::Ux = 0x0092_4924; +} diff --git a/esp32p4/src/isp/gamma_gy1.rs b/esp32p4/src/isp/gamma_gy1.rs new file mode 100644 index 0000000000..d2393b3c8b --- /dev/null +++ b/esp32p4/src/isp/gamma_gy1.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_GY1` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_GY1` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_G_Y03` reader - this field configures the point 3 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y03_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y03` writer - this field configures the point 3 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y03_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y02` reader - this field configures the point 2 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y02_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y02` writer - this field configures the point 2 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y02_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y01` reader - this field configures the point 1 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y01_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y01` writer - this field configures the point 1 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y01_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y00` reader - this field configures the point 0 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y00_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y00` writer - this field configures the point 0 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y00_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 3 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y03(&self) -> GAMMA_G_Y03_R { + GAMMA_G_Y03_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 2 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y02(&self) -> GAMMA_G_Y02_R { + GAMMA_G_Y02_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 1 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y01(&self) -> GAMMA_G_Y01_R { + GAMMA_G_Y01_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 0 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y00(&self) -> GAMMA_G_Y00_R { + GAMMA_G_Y00_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_GY1") + .field( + "gamma_g_y03", + &format_args!("{}", self.gamma_g_y03().bits()), + ) + .field( + "gamma_g_y02", + &format_args!("{}", self.gamma_g_y02().bits()), + ) + .field( + "gamma_g_y01", + &format_args!("{}", self.gamma_g_y01().bits()), + ) + .field( + "gamma_g_y00", + &format_args!("{}", self.gamma_g_y00().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 3 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y03(&mut self) -> GAMMA_G_Y03_W { + GAMMA_G_Y03_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 2 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y02(&mut self) -> GAMMA_G_Y02_W { + GAMMA_G_Y02_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 1 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y01(&mut self) -> GAMMA_G_Y01_W { + GAMMA_G_Y01_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 0 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y00(&mut self) -> GAMMA_G_Y00_W { + GAMMA_G_Y00_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of g channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gy1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gy1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_GY1_SPEC; +impl crate::RegisterSpec for GAMMA_GY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_gy1::R`](R) reader structure"] +impl crate::Readable for GAMMA_GY1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_gy1::W`](W) writer structure"] +impl crate::Writable for GAMMA_GY1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_GY1 to value 0x1020_3040"] +impl crate::Resettable for GAMMA_GY1_SPEC { + const RESET_VALUE: Self::Ux = 0x1020_3040; +} diff --git a/esp32p4/src/isp/gamma_gy2.rs b/esp32p4/src/isp/gamma_gy2.rs new file mode 100644 index 0000000000..8a779a8e6a --- /dev/null +++ b/esp32p4/src/isp/gamma_gy2.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_GY2` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_GY2` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_G_Y07` reader - this field configures the point 7 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y07_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y07` writer - this field configures the point 7 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y07_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y06` reader - this field configures the point 6 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y06_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y06` writer - this field configures the point 6 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y06_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y05` reader - this field configures the point 5 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y05_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y05` writer - this field configures the point 5 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y05_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y04` reader - this field configures the point 4 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y04_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y04` writer - this field configures the point 4 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y04_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 7 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y07(&self) -> GAMMA_G_Y07_R { + GAMMA_G_Y07_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 6 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y06(&self) -> GAMMA_G_Y06_R { + GAMMA_G_Y06_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 5 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y05(&self) -> GAMMA_G_Y05_R { + GAMMA_G_Y05_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 4 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y04(&self) -> GAMMA_G_Y04_R { + GAMMA_G_Y04_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_GY2") + .field( + "gamma_g_y07", + &format_args!("{}", self.gamma_g_y07().bits()), + ) + .field( + "gamma_g_y06", + &format_args!("{}", self.gamma_g_y06().bits()), + ) + .field( + "gamma_g_y05", + &format_args!("{}", self.gamma_g_y05().bits()), + ) + .field( + "gamma_g_y04", + &format_args!("{}", self.gamma_g_y04().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 7 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y07(&mut self) -> GAMMA_G_Y07_W { + GAMMA_G_Y07_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 6 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y06(&mut self) -> GAMMA_G_Y06_W { + GAMMA_G_Y06_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 5 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y05(&mut self) -> GAMMA_G_Y05_W { + GAMMA_G_Y05_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 4 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y04(&mut self) -> GAMMA_G_Y04_W { + GAMMA_G_Y04_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of g channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gy2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gy2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_GY2_SPEC; +impl crate::RegisterSpec for GAMMA_GY2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_gy2::R`](R) reader structure"] +impl crate::Readable for GAMMA_GY2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_gy2::W`](W) writer structure"] +impl crate::Writable for GAMMA_GY2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_GY2 to value 0x5060_7080"] +impl crate::Resettable for GAMMA_GY2_SPEC { + const RESET_VALUE: Self::Ux = 0x5060_7080; +} diff --git a/esp32p4/src/isp/gamma_gy3.rs b/esp32p4/src/isp/gamma_gy3.rs new file mode 100644 index 0000000000..c90f1c7c0f --- /dev/null +++ b/esp32p4/src/isp/gamma_gy3.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_GY3` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_GY3` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_G_Y0B` reader - this field configures the point 11 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0B_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y0B` writer - this field configures the point 11 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0B_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y0A` reader - this field configures the point 10 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0A_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y0A` writer - this field configures the point 10 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0A_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y09` reader - this field configures the point 9 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y09_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y09` writer - this field configures the point 9 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y09_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y08` reader - this field configures the point 8 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y08_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y08` writer - this field configures the point 8 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y08_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 11 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y0b(&self) -> GAMMA_G_Y0B_R { + GAMMA_G_Y0B_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 10 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y0a(&self) -> GAMMA_G_Y0A_R { + GAMMA_G_Y0A_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 9 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y09(&self) -> GAMMA_G_Y09_R { + GAMMA_G_Y09_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 8 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y08(&self) -> GAMMA_G_Y08_R { + GAMMA_G_Y08_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_GY3") + .field( + "gamma_g_y0b", + &format_args!("{}", self.gamma_g_y0b().bits()), + ) + .field( + "gamma_g_y0a", + &format_args!("{}", self.gamma_g_y0a().bits()), + ) + .field( + "gamma_g_y09", + &format_args!("{}", self.gamma_g_y09().bits()), + ) + .field( + "gamma_g_y08", + &format_args!("{}", self.gamma_g_y08().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 11 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y0b(&mut self) -> GAMMA_G_Y0B_W { + GAMMA_G_Y0B_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 10 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y0a(&mut self) -> GAMMA_G_Y0A_W { + GAMMA_G_Y0A_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 9 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y09(&mut self) -> GAMMA_G_Y09_W { + GAMMA_G_Y09_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 8 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y08(&mut self) -> GAMMA_G_Y08_W { + GAMMA_G_Y08_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of g channel gamma curve register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gy3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gy3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_GY3_SPEC; +impl crate::RegisterSpec for GAMMA_GY3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_gy3::R`](R) reader structure"] +impl crate::Readable for GAMMA_GY3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_gy3::W`](W) writer structure"] +impl crate::Writable for GAMMA_GY3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_GY3 to value 0x90a0_b0c0"] +impl crate::Resettable for GAMMA_GY3_SPEC { + const RESET_VALUE: Self::Ux = 0x90a0_b0c0; +} diff --git a/esp32p4/src/isp/gamma_gy4.rs b/esp32p4/src/isp/gamma_gy4.rs new file mode 100644 index 0000000000..39ab631cab --- /dev/null +++ b/esp32p4/src/isp/gamma_gy4.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_GY4` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_GY4` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_G_Y0F` reader - this field configures the point 15 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0F_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y0F` writer - this field configures the point 15 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0F_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y0E` reader - this field configures the point 14 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0E_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y0E` writer - this field configures the point 14 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0E_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y0D` reader - this field configures the point 13 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0D_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y0D` writer - this field configures the point 13 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0D_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_G_Y0C` reader - this field configures the point 12 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0C_R = crate::FieldReader; +#[doc = "Field `GAMMA_G_Y0C` writer - this field configures the point 12 of Y-axis of g channel gamma curve"] +pub type GAMMA_G_Y0C_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 15 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y0f(&self) -> GAMMA_G_Y0F_R { + GAMMA_G_Y0F_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 14 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y0e(&self) -> GAMMA_G_Y0E_R { + GAMMA_G_Y0E_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 13 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y0d(&self) -> GAMMA_G_Y0D_R { + GAMMA_G_Y0D_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 12 of Y-axis of g channel gamma curve"] + #[inline(always)] + pub fn gamma_g_y0c(&self) -> GAMMA_G_Y0C_R { + GAMMA_G_Y0C_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_GY4") + .field( + "gamma_g_y0f", + &format_args!("{}", self.gamma_g_y0f().bits()), + ) + .field( + "gamma_g_y0e", + &format_args!("{}", self.gamma_g_y0e().bits()), + ) + .field( + "gamma_g_y0d", + &format_args!("{}", self.gamma_g_y0d().bits()), + ) + .field( + "gamma_g_y0c", + &format_args!("{}", self.gamma_g_y0c().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 15 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y0f(&mut self) -> GAMMA_G_Y0F_W { + GAMMA_G_Y0F_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 14 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y0e(&mut self) -> GAMMA_G_Y0E_W { + GAMMA_G_Y0E_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 13 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y0d(&mut self) -> GAMMA_G_Y0D_W { + GAMMA_G_Y0D_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 12 of Y-axis of g channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_g_y0c(&mut self) -> GAMMA_G_Y0C_W { + GAMMA_G_Y0C_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of g channel gamma curve register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_gy4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_gy4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_GY4_SPEC; +impl crate::RegisterSpec for GAMMA_GY4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_gy4::R`](R) reader structure"] +impl crate::Readable for GAMMA_GY4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_gy4::W`](W) writer structure"] +impl crate::Writable for GAMMA_GY4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_GY4 to value 0xd0e0_f0ff"] +impl crate::Resettable for GAMMA_GY4_SPEC { + const RESET_VALUE: Self::Ux = 0xd0e0_f0ff; +} diff --git a/esp32p4/src/isp/gamma_rx1.rs b/esp32p4/src/isp/gamma_rx1.rs new file mode 100644 index 0000000000..767f5acea4 --- /dev/null +++ b/esp32p4/src/isp/gamma_rx1.rs @@ -0,0 +1,199 @@ +#[doc = "Register `GAMMA_RX1` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_RX1` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_R_X07` reader - this field configures the point 7 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X07_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X07` writer - this field configures the point 7 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X07_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X06` reader - this field configures the point 6 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X06_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X06` writer - this field configures the point 6 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X06_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X05` reader - this field configures the point 5 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X05_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X05` writer - this field configures the point 5 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X05_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X04` reader - this field configures the point 4 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X04_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X04` writer - this field configures the point 4 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X04_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X03` reader - this field configures the point 3 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X03_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X03` writer - this field configures the point 3 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X03_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X02` reader - this field configures the point 2 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X02_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X02` writer - this field configures the point 2 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X02_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X01` reader - this field configures the point 1 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X01_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X01` writer - this field configures the point 1 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X01_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X00` reader - this field configures the point 0 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X00_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X00` writer - this field configures the point 0 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X00_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - this field configures the point 7 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x07(&self) -> GAMMA_R_X07_R { + GAMMA_R_X07_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - this field configures the point 6 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x06(&self) -> GAMMA_R_X06_R { + GAMMA_R_X06_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - this field configures the point 5 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x05(&self) -> GAMMA_R_X05_R { + GAMMA_R_X05_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - this field configures the point 4 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x04(&self) -> GAMMA_R_X04_R { + GAMMA_R_X04_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - this field configures the point 3 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x03(&self) -> GAMMA_R_X03_R { + GAMMA_R_X03_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - this field configures the point 2 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x02(&self) -> GAMMA_R_X02_R { + GAMMA_R_X02_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - this field configures the point 1 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x01(&self) -> GAMMA_R_X01_R { + GAMMA_R_X01_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - this field configures the point 0 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x00(&self) -> GAMMA_R_X00_R { + GAMMA_R_X00_R::new(((self.bits >> 21) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_RX1") + .field( + "gamma_r_x07", + &format_args!("{}", self.gamma_r_x07().bits()), + ) + .field( + "gamma_r_x06", + &format_args!("{}", self.gamma_r_x06().bits()), + ) + .field( + "gamma_r_x05", + &format_args!("{}", self.gamma_r_x05().bits()), + ) + .field( + "gamma_r_x04", + &format_args!("{}", self.gamma_r_x04().bits()), + ) + .field( + "gamma_r_x03", + &format_args!("{}", self.gamma_r_x03().bits()), + ) + .field( + "gamma_r_x02", + &format_args!("{}", self.gamma_r_x02().bits()), + ) + .field( + "gamma_r_x01", + &format_args!("{}", self.gamma_r_x01().bits()), + ) + .field( + "gamma_r_x00", + &format_args!("{}", self.gamma_r_x00().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - this field configures the point 7 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x07(&mut self) -> GAMMA_R_X07_W { + GAMMA_R_X07_W::new(self, 0) + } + #[doc = "Bits 3:5 - this field configures the point 6 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x06(&mut self) -> GAMMA_R_X06_W { + GAMMA_R_X06_W::new(self, 3) + } + #[doc = "Bits 6:8 - this field configures the point 5 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x05(&mut self) -> GAMMA_R_X05_W { + GAMMA_R_X05_W::new(self, 6) + } + #[doc = "Bits 9:11 - this field configures the point 4 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x04(&mut self) -> GAMMA_R_X04_W { + GAMMA_R_X04_W::new(self, 9) + } + #[doc = "Bits 12:14 - this field configures the point 3 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x03(&mut self) -> GAMMA_R_X03_W { + GAMMA_R_X03_W::new(self, 12) + } + #[doc = "Bits 15:17 - this field configures the point 2 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x02(&mut self) -> GAMMA_R_X02_W { + GAMMA_R_X02_W::new(self, 15) + } + #[doc = "Bits 18:20 - this field configures the point 1 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x01(&mut self) -> GAMMA_R_X01_W { + GAMMA_R_X01_W::new(self, 18) + } + #[doc = "Bits 21:23 - this field configures the point 0 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x00(&mut self) -> GAMMA_R_X00_W { + GAMMA_R_X00_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of X-axis of r channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_rx1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_rx1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_RX1_SPEC; +impl crate::RegisterSpec for GAMMA_RX1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_rx1::R`](R) reader structure"] +impl crate::Readable for GAMMA_RX1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_rx1::W`](W) writer structure"] +impl crate::Writable for GAMMA_RX1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_RX1 to value 0x0092_4924"] +impl crate::Resettable for GAMMA_RX1_SPEC { + const RESET_VALUE: Self::Ux = 0x0092_4924; +} diff --git a/esp32p4/src/isp/gamma_rx2.rs b/esp32p4/src/isp/gamma_rx2.rs new file mode 100644 index 0000000000..1446e554bd --- /dev/null +++ b/esp32p4/src/isp/gamma_rx2.rs @@ -0,0 +1,199 @@ +#[doc = "Register `GAMMA_RX2` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_RX2` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_R_X0F` reader - this field configures the point 15 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0F_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X0F` writer - this field configures the point 15 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0F_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X0E` reader - this field configures the point 14 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0E_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X0E` writer - this field configures the point 14 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0E_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X0D` reader - this field configures the point 13 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0D_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X0D` writer - this field configures the point 13 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0D_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X0C` reader - this field configures the point 12 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0C_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X0C` writer - this field configures the point 12 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0C_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X0B` reader - this field configures the point 11 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0B_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X0B` writer - this field configures the point 11 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0B_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X0A` reader - this field configures the point 10 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0A_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X0A` writer - this field configures the point 10 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X0A_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X09` reader - this field configures the point 9 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X09_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X09` writer - this field configures the point 9 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X09_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GAMMA_R_X08` reader - this field configures the point 8 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X08_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_X08` writer - this field configures the point 8 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] +pub type GAMMA_R_X08_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - this field configures the point 15 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x0f(&self) -> GAMMA_R_X0F_R { + GAMMA_R_X0F_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - this field configures the point 14 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x0e(&self) -> GAMMA_R_X0E_R { + GAMMA_R_X0E_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - this field configures the point 13 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x0d(&self) -> GAMMA_R_X0D_R { + GAMMA_R_X0D_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - this field configures the point 12 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x0c(&self) -> GAMMA_R_X0C_R { + GAMMA_R_X0C_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - this field configures the point 11 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x0b(&self) -> GAMMA_R_X0B_R { + GAMMA_R_X0B_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - this field configures the point 10 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x0a(&self) -> GAMMA_R_X0A_R { + GAMMA_R_X0A_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - this field configures the point 9 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x09(&self) -> GAMMA_R_X09_R { + GAMMA_R_X09_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - this field configures the point 8 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + pub fn gamma_r_x08(&self) -> GAMMA_R_X08_R { + GAMMA_R_X08_R::new(((self.bits >> 21) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_RX2") + .field( + "gamma_r_x0f", + &format_args!("{}", self.gamma_r_x0f().bits()), + ) + .field( + "gamma_r_x0e", + &format_args!("{}", self.gamma_r_x0e().bits()), + ) + .field( + "gamma_r_x0d", + &format_args!("{}", self.gamma_r_x0d().bits()), + ) + .field( + "gamma_r_x0c", + &format_args!("{}", self.gamma_r_x0c().bits()), + ) + .field( + "gamma_r_x0b", + &format_args!("{}", self.gamma_r_x0b().bits()), + ) + .field( + "gamma_r_x0a", + &format_args!("{}", self.gamma_r_x0a().bits()), + ) + .field( + "gamma_r_x09", + &format_args!("{}", self.gamma_r_x09().bits()), + ) + .field( + "gamma_r_x08", + &format_args!("{}", self.gamma_r_x08().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - this field configures the point 15 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x0f(&mut self) -> GAMMA_R_X0F_W { + GAMMA_R_X0F_W::new(self, 0) + } + #[doc = "Bits 3:5 - this field configures the point 14 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x0e(&mut self) -> GAMMA_R_X0E_W { + GAMMA_R_X0E_W::new(self, 3) + } + #[doc = "Bits 6:8 - this field configures the point 13 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x0d(&mut self) -> GAMMA_R_X0D_W { + GAMMA_R_X0D_W::new(self, 6) + } + #[doc = "Bits 9:11 - this field configures the point 12 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x0c(&mut self) -> GAMMA_R_X0C_W { + GAMMA_R_X0C_W::new(self, 9) + } + #[doc = "Bits 12:14 - this field configures the point 11 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x0b(&mut self) -> GAMMA_R_X0B_W { + GAMMA_R_X0B_W::new(self, 12) + } + #[doc = "Bits 15:17 - this field configures the point 10 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x0a(&mut self) -> GAMMA_R_X0A_W { + GAMMA_R_X0A_W::new(self, 15) + } + #[doc = "Bits 18:20 - this field configures the point 9 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x09(&mut self) -> GAMMA_R_X09_W { + GAMMA_R_X09_W::new(self, 18) + } + #[doc = "Bits 21:23 - this field configures the point 8 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"] + #[inline(always)] + #[must_use] + pub fn gamma_r_x08(&mut self) -> GAMMA_R_X08_W { + GAMMA_R_X08_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of X-axis of r channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_rx2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_rx2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_RX2_SPEC; +impl crate::RegisterSpec for GAMMA_RX2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_rx2::R`](R) reader structure"] +impl crate::Readable for GAMMA_RX2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_rx2::W`](W) writer structure"] +impl crate::Writable for GAMMA_RX2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_RX2 to value 0x0092_4924"] +impl crate::Resettable for GAMMA_RX2_SPEC { + const RESET_VALUE: Self::Ux = 0x0092_4924; +} diff --git a/esp32p4/src/isp/gamma_ry1.rs b/esp32p4/src/isp/gamma_ry1.rs new file mode 100644 index 0000000000..894d37dabd --- /dev/null +++ b/esp32p4/src/isp/gamma_ry1.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_RY1` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_RY1` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_R_Y03` reader - this field configures the point 3 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y03_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y03` writer - this field configures the point 3 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y03_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y02` reader - this field configures the point 2 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y02_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y02` writer - this field configures the point 2 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y02_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y01` reader - this field configures the point 1 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y01_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y01` writer - this field configures the point 1 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y01_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y00` reader - this field configures the point 0 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y00_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y00` writer - this field configures the point 0 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y00_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 3 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y03(&self) -> GAMMA_R_Y03_R { + GAMMA_R_Y03_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 2 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y02(&self) -> GAMMA_R_Y02_R { + GAMMA_R_Y02_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 1 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y01(&self) -> GAMMA_R_Y01_R { + GAMMA_R_Y01_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 0 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y00(&self) -> GAMMA_R_Y00_R { + GAMMA_R_Y00_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_RY1") + .field( + "gamma_r_y03", + &format_args!("{}", self.gamma_r_y03().bits()), + ) + .field( + "gamma_r_y02", + &format_args!("{}", self.gamma_r_y02().bits()), + ) + .field( + "gamma_r_y01", + &format_args!("{}", self.gamma_r_y01().bits()), + ) + .field( + "gamma_r_y00", + &format_args!("{}", self.gamma_r_y00().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 3 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y03(&mut self) -> GAMMA_R_Y03_W { + GAMMA_R_Y03_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 2 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y02(&mut self) -> GAMMA_R_Y02_W { + GAMMA_R_Y02_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 1 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y01(&mut self) -> GAMMA_R_Y01_W { + GAMMA_R_Y01_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 0 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y00(&mut self) -> GAMMA_R_Y00_W { + GAMMA_R_Y00_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of r channel gamma curve register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_ry1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_ry1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_RY1_SPEC; +impl crate::RegisterSpec for GAMMA_RY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_ry1::R`](R) reader structure"] +impl crate::Readable for GAMMA_RY1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_ry1::W`](W) writer structure"] +impl crate::Writable for GAMMA_RY1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_RY1 to value 0x1020_3040"] +impl crate::Resettable for GAMMA_RY1_SPEC { + const RESET_VALUE: Self::Ux = 0x1020_3040; +} diff --git a/esp32p4/src/isp/gamma_ry2.rs b/esp32p4/src/isp/gamma_ry2.rs new file mode 100644 index 0000000000..881a1855f1 --- /dev/null +++ b/esp32p4/src/isp/gamma_ry2.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_RY2` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_RY2` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_R_Y07` reader - this field configures the point 7 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y07_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y07` writer - this field configures the point 7 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y07_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y06` reader - this field configures the point 6 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y06_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y06` writer - this field configures the point 6 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y06_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y05` reader - this field configures the point 5 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y05_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y05` writer - this field configures the point 5 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y05_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y04` reader - this field configures the point 4 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y04_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y04` writer - this field configures the point 4 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y04_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 7 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y07(&self) -> GAMMA_R_Y07_R { + GAMMA_R_Y07_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 6 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y06(&self) -> GAMMA_R_Y06_R { + GAMMA_R_Y06_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 5 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y05(&self) -> GAMMA_R_Y05_R { + GAMMA_R_Y05_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 4 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y04(&self) -> GAMMA_R_Y04_R { + GAMMA_R_Y04_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_RY2") + .field( + "gamma_r_y07", + &format_args!("{}", self.gamma_r_y07().bits()), + ) + .field( + "gamma_r_y06", + &format_args!("{}", self.gamma_r_y06().bits()), + ) + .field( + "gamma_r_y05", + &format_args!("{}", self.gamma_r_y05().bits()), + ) + .field( + "gamma_r_y04", + &format_args!("{}", self.gamma_r_y04().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 7 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y07(&mut self) -> GAMMA_R_Y07_W { + GAMMA_R_Y07_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 6 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y06(&mut self) -> GAMMA_R_Y06_W { + GAMMA_R_Y06_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 5 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y05(&mut self) -> GAMMA_R_Y05_W { + GAMMA_R_Y05_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 4 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y04(&mut self) -> GAMMA_R_Y04_W { + GAMMA_R_Y04_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of r channel gamma curve register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_ry2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_ry2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_RY2_SPEC; +impl crate::RegisterSpec for GAMMA_RY2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_ry2::R`](R) reader structure"] +impl crate::Readable for GAMMA_RY2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_ry2::W`](W) writer structure"] +impl crate::Writable for GAMMA_RY2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_RY2 to value 0x5060_7080"] +impl crate::Resettable for GAMMA_RY2_SPEC { + const RESET_VALUE: Self::Ux = 0x5060_7080; +} diff --git a/esp32p4/src/isp/gamma_ry3.rs b/esp32p4/src/isp/gamma_ry3.rs new file mode 100644 index 0000000000..7111639270 --- /dev/null +++ b/esp32p4/src/isp/gamma_ry3.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_RY3` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_RY3` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_R_Y0B` reader - this field configures the point 11 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0B_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y0B` writer - this field configures the point 11 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0B_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y0A` reader - this field configures the point 10 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0A_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y0A` writer - this field configures the point 10 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0A_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y09` reader - this field configures the point 9 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y09_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y09` writer - this field configures the point 9 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y09_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y08` reader - this field configures the point 8 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y08_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y08` writer - this field configures the point 8 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y08_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 11 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y0b(&self) -> GAMMA_R_Y0B_R { + GAMMA_R_Y0B_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 10 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y0a(&self) -> GAMMA_R_Y0A_R { + GAMMA_R_Y0A_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 9 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y09(&self) -> GAMMA_R_Y09_R { + GAMMA_R_Y09_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 8 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y08(&self) -> GAMMA_R_Y08_R { + GAMMA_R_Y08_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_RY3") + .field( + "gamma_r_y0b", + &format_args!("{}", self.gamma_r_y0b().bits()), + ) + .field( + "gamma_r_y0a", + &format_args!("{}", self.gamma_r_y0a().bits()), + ) + .field( + "gamma_r_y09", + &format_args!("{}", self.gamma_r_y09().bits()), + ) + .field( + "gamma_r_y08", + &format_args!("{}", self.gamma_r_y08().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 11 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y0b(&mut self) -> GAMMA_R_Y0B_W { + GAMMA_R_Y0B_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 10 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y0a(&mut self) -> GAMMA_R_Y0A_W { + GAMMA_R_Y0A_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 9 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y09(&mut self) -> GAMMA_R_Y09_W { + GAMMA_R_Y09_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 8 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y08(&mut self) -> GAMMA_R_Y08_W { + GAMMA_R_Y08_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of r channel gamma curve register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_ry3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_ry3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_RY3_SPEC; +impl crate::RegisterSpec for GAMMA_RY3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_ry3::R`](R) reader structure"] +impl crate::Readable for GAMMA_RY3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_ry3::W`](W) writer structure"] +impl crate::Writable for GAMMA_RY3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_RY3 to value 0x90a0_b0c0"] +impl crate::Resettable for GAMMA_RY3_SPEC { + const RESET_VALUE: Self::Ux = 0x90a0_b0c0; +} diff --git a/esp32p4/src/isp/gamma_ry4.rs b/esp32p4/src/isp/gamma_ry4.rs new file mode 100644 index 0000000000..357cd5a82f --- /dev/null +++ b/esp32p4/src/isp/gamma_ry4.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GAMMA_RY4` reader"] +pub type R = crate::R; +#[doc = "Register `GAMMA_RY4` writer"] +pub type W = crate::W; +#[doc = "Field `GAMMA_R_Y0F` reader - this field configures the point 15 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0F_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y0F` writer - this field configures the point 15 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0F_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y0E` reader - this field configures the point 14 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0E_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y0E` writer - this field configures the point 14 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0E_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y0D` reader - this field configures the point 13 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0D_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y0D` writer - this field configures the point 13 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0D_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GAMMA_R_Y0C` reader - this field configures the point 12 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0C_R = crate::FieldReader; +#[doc = "Field `GAMMA_R_Y0C` writer - this field configures the point 12 of Y-axis of r channel gamma curve"] +pub type GAMMA_R_Y0C_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the point 15 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y0f(&self) -> GAMMA_R_Y0F_R { + GAMMA_R_Y0F_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures the point 14 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y0e(&self) -> GAMMA_R_Y0E_R { + GAMMA_R_Y0E_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures the point 13 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y0d(&self) -> GAMMA_R_Y0D_R { + GAMMA_R_Y0D_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures the point 12 of Y-axis of r channel gamma curve"] + #[inline(always)] + pub fn gamma_r_y0c(&self) -> GAMMA_R_Y0C_R { + GAMMA_R_Y0C_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GAMMA_RY4") + .field( + "gamma_r_y0f", + &format_args!("{}", self.gamma_r_y0f().bits()), + ) + .field( + "gamma_r_y0e", + &format_args!("{}", self.gamma_r_y0e().bits()), + ) + .field( + "gamma_r_y0d", + &format_args!("{}", self.gamma_r_y0d().bits()), + ) + .field( + "gamma_r_y0c", + &format_args!("{}", self.gamma_r_y0c().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the point 15 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y0f(&mut self) -> GAMMA_R_Y0F_W { + GAMMA_R_Y0F_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures the point 14 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y0e(&mut self) -> GAMMA_R_Y0E_W { + GAMMA_R_Y0E_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures the point 13 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y0d(&mut self) -> GAMMA_R_Y0D_W { + GAMMA_R_Y0D_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures the point 12 of Y-axis of r channel gamma curve"] + #[inline(always)] + #[must_use] + pub fn gamma_r_y0c(&mut self) -> GAMMA_R_Y0C_W { + GAMMA_R_Y0C_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "point of Y-axis of r channel gamma curve register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gamma_ry4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gamma_ry4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GAMMA_RY4_SPEC; +impl crate::RegisterSpec for GAMMA_RY4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gamma_ry4::R`](R) reader structure"] +impl crate::Readable for GAMMA_RY4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gamma_ry4::W`](W) writer structure"] +impl crate::Writable for GAMMA_RY4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAMMA_RY4 to value 0xd0e0_f0ff"] +impl crate::Resettable for GAMMA_RY4_SPEC { + const RESET_VALUE: Self::Ux = 0xd0e0_f0ff; +} diff --git a/esp32p4/src/isp/hist_bin0.rs b/esp32p4/src/isp/hist_bin0.rs new file mode 100644 index 0000000000..cf8edc6fde --- /dev/null +++ b/esp32p4/src/isp/hist_bin0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `HIST_BIN0` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_0` reader - this field represents result of histogram bin 0"] +pub type HIST_BIN_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 0"] + #[inline(always)] + pub fn hist_bin_0(&self) -> HIST_BIN_0_R { + HIST_BIN_0_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN0") + .field("hist_bin_0", &format_args!("{}", self.hist_bin_0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN0_SPEC; +impl crate::RegisterSpec for HIST_BIN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin0::R`](R) reader structure"] +impl crate::Readable for HIST_BIN0_SPEC {} +#[doc = "`reset()` method sets HIST_BIN0 to value 0"] +impl crate::Resettable for HIST_BIN0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin1.rs b/esp32p4/src/isp/hist_bin1.rs new file mode 100644 index 0000000000..28ccb8b72f --- /dev/null +++ b/esp32p4/src/isp/hist_bin1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `HIST_BIN1` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_1` reader - this field represents result of histogram bin 1"] +pub type HIST_BIN_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 1"] + #[inline(always)] + pub fn hist_bin_1(&self) -> HIST_BIN_1_R { + HIST_BIN_1_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN1") + .field("hist_bin_1", &format_args!("{}", self.hist_bin_1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN1_SPEC; +impl crate::RegisterSpec for HIST_BIN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin1::R`](R) reader structure"] +impl crate::Readable for HIST_BIN1_SPEC {} +#[doc = "`reset()` method sets HIST_BIN1 to value 0"] +impl crate::Resettable for HIST_BIN1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin10.rs b/esp32p4/src/isp/hist_bin10.rs new file mode 100644 index 0000000000..5f702b016c --- /dev/null +++ b/esp32p4/src/isp/hist_bin10.rs @@ -0,0 +1,39 @@ +#[doc = "Register `HIST_BIN10` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_10` reader - this field represents result of histogram bin 10"] +pub type HIST_BIN_10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 10"] + #[inline(always)] + pub fn hist_bin_10(&self) -> HIST_BIN_10_R { + HIST_BIN_10_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN10") + .field( + "hist_bin_10", + &format_args!("{}", self.hist_bin_10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN10_SPEC; +impl crate::RegisterSpec for HIST_BIN10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin10::R`](R) reader structure"] +impl crate::Readable for HIST_BIN10_SPEC {} +#[doc = "`reset()` method sets HIST_BIN10 to value 0"] +impl crate::Resettable for HIST_BIN10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin11.rs b/esp32p4/src/isp/hist_bin11.rs new file mode 100644 index 0000000000..455bf37b37 --- /dev/null +++ b/esp32p4/src/isp/hist_bin11.rs @@ -0,0 +1,39 @@ +#[doc = "Register `HIST_BIN11` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_11` reader - this field represents result of histogram bin 11"] +pub type HIST_BIN_11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 11"] + #[inline(always)] + pub fn hist_bin_11(&self) -> HIST_BIN_11_R { + HIST_BIN_11_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN11") + .field( + "hist_bin_11", + &format_args!("{}", self.hist_bin_11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN11_SPEC; +impl crate::RegisterSpec for HIST_BIN11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin11::R`](R) reader structure"] +impl crate::Readable for HIST_BIN11_SPEC {} +#[doc = "`reset()` method sets HIST_BIN11 to value 0"] +impl crate::Resettable for HIST_BIN11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin12.rs b/esp32p4/src/isp/hist_bin12.rs new file mode 100644 index 0000000000..2a0022ea34 --- /dev/null +++ b/esp32p4/src/isp/hist_bin12.rs @@ -0,0 +1,39 @@ +#[doc = "Register `HIST_BIN12` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_12` reader - this field represents result of histogram bin 12"] +pub type HIST_BIN_12_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 12"] + #[inline(always)] + pub fn hist_bin_12(&self) -> HIST_BIN_12_R { + HIST_BIN_12_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN12") + .field( + "hist_bin_12", + &format_args!("{}", self.hist_bin_12().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin12::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN12_SPEC; +impl crate::RegisterSpec for HIST_BIN12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin12::R`](R) reader structure"] +impl crate::Readable for HIST_BIN12_SPEC {} +#[doc = "`reset()` method sets HIST_BIN12 to value 0"] +impl crate::Resettable for HIST_BIN12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin13.rs b/esp32p4/src/isp/hist_bin13.rs new file mode 100644 index 0000000000..2cbbc7ac11 --- /dev/null +++ b/esp32p4/src/isp/hist_bin13.rs @@ -0,0 +1,39 @@ +#[doc = "Register `HIST_BIN13` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_13` reader - this field represents result of histogram bin 13"] +pub type HIST_BIN_13_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 13"] + #[inline(always)] + pub fn hist_bin_13(&self) -> HIST_BIN_13_R { + HIST_BIN_13_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN13") + .field( + "hist_bin_13", + &format_args!("{}", self.hist_bin_13().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin13::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN13_SPEC; +impl crate::RegisterSpec for HIST_BIN13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin13::R`](R) reader structure"] +impl crate::Readable for HIST_BIN13_SPEC {} +#[doc = "`reset()` method sets HIST_BIN13 to value 0"] +impl crate::Resettable for HIST_BIN13_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin14.rs b/esp32p4/src/isp/hist_bin14.rs new file mode 100644 index 0000000000..c8d5a2e46e --- /dev/null +++ b/esp32p4/src/isp/hist_bin14.rs @@ -0,0 +1,39 @@ +#[doc = "Register `HIST_BIN14` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_14` reader - this field represents result of histogram bin 14"] +pub type HIST_BIN_14_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 14"] + #[inline(always)] + pub fn hist_bin_14(&self) -> HIST_BIN_14_R { + HIST_BIN_14_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN14") + .field( + "hist_bin_14", + &format_args!("{}", self.hist_bin_14().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin14::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN14_SPEC; +impl crate::RegisterSpec for HIST_BIN14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin14::R`](R) reader structure"] +impl crate::Readable for HIST_BIN14_SPEC {} +#[doc = "`reset()` method sets HIST_BIN14 to value 0"] +impl crate::Resettable for HIST_BIN14_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin15.rs b/esp32p4/src/isp/hist_bin15.rs new file mode 100644 index 0000000000..925421be6d --- /dev/null +++ b/esp32p4/src/isp/hist_bin15.rs @@ -0,0 +1,39 @@ +#[doc = "Register `HIST_BIN15` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_15` reader - this field represents result of histogram bin 15"] +pub type HIST_BIN_15_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 15"] + #[inline(always)] + pub fn hist_bin_15(&self) -> HIST_BIN_15_R { + HIST_BIN_15_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN15") + .field( + "hist_bin_15", + &format_args!("{}", self.hist_bin_15().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin15::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN15_SPEC; +impl crate::RegisterSpec for HIST_BIN15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin15::R`](R) reader structure"] +impl crate::Readable for HIST_BIN15_SPEC {} +#[doc = "`reset()` method sets HIST_BIN15 to value 0"] +impl crate::Resettable for HIST_BIN15_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin2.rs b/esp32p4/src/isp/hist_bin2.rs new file mode 100644 index 0000000000..48ecdef386 --- /dev/null +++ b/esp32p4/src/isp/hist_bin2.rs @@ -0,0 +1,36 @@ +#[doc = "Register `HIST_BIN2` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_2` reader - this field represents result of histogram bin 2"] +pub type HIST_BIN_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 2"] + #[inline(always)] + pub fn hist_bin_2(&self) -> HIST_BIN_2_R { + HIST_BIN_2_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN2") + .field("hist_bin_2", &format_args!("{}", self.hist_bin_2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN2_SPEC; +impl crate::RegisterSpec for HIST_BIN2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin2::R`](R) reader structure"] +impl crate::Readable for HIST_BIN2_SPEC {} +#[doc = "`reset()` method sets HIST_BIN2 to value 0"] +impl crate::Resettable for HIST_BIN2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin3.rs b/esp32p4/src/isp/hist_bin3.rs new file mode 100644 index 0000000000..6862a65348 --- /dev/null +++ b/esp32p4/src/isp/hist_bin3.rs @@ -0,0 +1,36 @@ +#[doc = "Register `HIST_BIN3` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_3` reader - this field represents result of histogram bin 3"] +pub type HIST_BIN_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 3"] + #[inline(always)] + pub fn hist_bin_3(&self) -> HIST_BIN_3_R { + HIST_BIN_3_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN3") + .field("hist_bin_3", &format_args!("{}", self.hist_bin_3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN3_SPEC; +impl crate::RegisterSpec for HIST_BIN3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin3::R`](R) reader structure"] +impl crate::Readable for HIST_BIN3_SPEC {} +#[doc = "`reset()` method sets HIST_BIN3 to value 0"] +impl crate::Resettable for HIST_BIN3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin4.rs b/esp32p4/src/isp/hist_bin4.rs new file mode 100644 index 0000000000..f7046fdf7a --- /dev/null +++ b/esp32p4/src/isp/hist_bin4.rs @@ -0,0 +1,36 @@ +#[doc = "Register `HIST_BIN4` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_4` reader - this field represents result of histogram bin 4"] +pub type HIST_BIN_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 4"] + #[inline(always)] + pub fn hist_bin_4(&self) -> HIST_BIN_4_R { + HIST_BIN_4_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN4") + .field("hist_bin_4", &format_args!("{}", self.hist_bin_4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN4_SPEC; +impl crate::RegisterSpec for HIST_BIN4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin4::R`](R) reader structure"] +impl crate::Readable for HIST_BIN4_SPEC {} +#[doc = "`reset()` method sets HIST_BIN4 to value 0"] +impl crate::Resettable for HIST_BIN4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin5.rs b/esp32p4/src/isp/hist_bin5.rs new file mode 100644 index 0000000000..0e4165196b --- /dev/null +++ b/esp32p4/src/isp/hist_bin5.rs @@ -0,0 +1,36 @@ +#[doc = "Register `HIST_BIN5` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_5` reader - this field represents result of histogram bin 5"] +pub type HIST_BIN_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 5"] + #[inline(always)] + pub fn hist_bin_5(&self) -> HIST_BIN_5_R { + HIST_BIN_5_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN5") + .field("hist_bin_5", &format_args!("{}", self.hist_bin_5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN5_SPEC; +impl crate::RegisterSpec for HIST_BIN5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin5::R`](R) reader structure"] +impl crate::Readable for HIST_BIN5_SPEC {} +#[doc = "`reset()` method sets HIST_BIN5 to value 0"] +impl crate::Resettable for HIST_BIN5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin6.rs b/esp32p4/src/isp/hist_bin6.rs new file mode 100644 index 0000000000..ba0d59dbb3 --- /dev/null +++ b/esp32p4/src/isp/hist_bin6.rs @@ -0,0 +1,36 @@ +#[doc = "Register `HIST_BIN6` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_6` reader - this field represents result of histogram bin 6"] +pub type HIST_BIN_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 6"] + #[inline(always)] + pub fn hist_bin_6(&self) -> HIST_BIN_6_R { + HIST_BIN_6_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN6") + .field("hist_bin_6", &format_args!("{}", self.hist_bin_6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN6_SPEC; +impl crate::RegisterSpec for HIST_BIN6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin6::R`](R) reader structure"] +impl crate::Readable for HIST_BIN6_SPEC {} +#[doc = "`reset()` method sets HIST_BIN6 to value 0"] +impl crate::Resettable for HIST_BIN6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin7.rs b/esp32p4/src/isp/hist_bin7.rs new file mode 100644 index 0000000000..92e713dd5d --- /dev/null +++ b/esp32p4/src/isp/hist_bin7.rs @@ -0,0 +1,36 @@ +#[doc = "Register `HIST_BIN7` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_7` reader - this field represents result of histogram bin 7"] +pub type HIST_BIN_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 7"] + #[inline(always)] + pub fn hist_bin_7(&self) -> HIST_BIN_7_R { + HIST_BIN_7_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN7") + .field("hist_bin_7", &format_args!("{}", self.hist_bin_7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN7_SPEC; +impl crate::RegisterSpec for HIST_BIN7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin7::R`](R) reader structure"] +impl crate::Readable for HIST_BIN7_SPEC {} +#[doc = "`reset()` method sets HIST_BIN7 to value 0"] +impl crate::Resettable for HIST_BIN7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin8.rs b/esp32p4/src/isp/hist_bin8.rs new file mode 100644 index 0000000000..48c3c89af7 --- /dev/null +++ b/esp32p4/src/isp/hist_bin8.rs @@ -0,0 +1,36 @@ +#[doc = "Register `HIST_BIN8` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_8` reader - this field represents result of histogram bin 8"] +pub type HIST_BIN_8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 8"] + #[inline(always)] + pub fn hist_bin_8(&self) -> HIST_BIN_8_R { + HIST_BIN_8_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN8") + .field("hist_bin_8", &format_args!("{}", self.hist_bin_8().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN8_SPEC; +impl crate::RegisterSpec for HIST_BIN8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin8::R`](R) reader structure"] +impl crate::Readable for HIST_BIN8_SPEC {} +#[doc = "`reset()` method sets HIST_BIN8 to value 0"] +impl crate::Resettable for HIST_BIN8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_bin9.rs b/esp32p4/src/isp/hist_bin9.rs new file mode 100644 index 0000000000..93a3174fb0 --- /dev/null +++ b/esp32p4/src/isp/hist_bin9.rs @@ -0,0 +1,36 @@ +#[doc = "Register `HIST_BIN9` reader"] +pub type R = crate::R; +#[doc = "Field `HIST_BIN_9` reader - this field represents result of histogram bin 9"] +pub type HIST_BIN_9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:16 - this field represents result of histogram bin 9"] + #[inline(always)] + pub fn hist_bin_9(&self) -> HIST_BIN_9_R { + HIST_BIN_9_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_BIN9") + .field("hist_bin_9", &format_args!("{}", self.hist_bin_9().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "result of histogram bin 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_BIN9_SPEC; +impl crate::RegisterSpec for HIST_BIN9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_bin9::R`](R) reader structure"] +impl crate::Readable for HIST_BIN9_SPEC {} +#[doc = "`reset()` method sets HIST_BIN9 to value 0"] +impl crate::Resettable for HIST_BIN9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_coeff.rs b/esp32p4/src/isp/hist_coeff.rs new file mode 100644 index 0000000000..3d659eda1a --- /dev/null +++ b/esp32p4/src/isp/hist_coeff.rs @@ -0,0 +1,95 @@ +#[doc = "Register `HIST_COEFF` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_COEFF` writer"] +pub type W = crate::W; +#[doc = "Field `B` reader - this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] +pub type B_R = crate::FieldReader; +#[doc = "Field `B` writer - this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] +pub type B_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `G` reader - this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] +pub type G_R = crate::FieldReader; +#[doc = "Field `G` writer - this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] +pub type G_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `R` reader - this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] +pub type R_R = crate::FieldReader; +#[doc = "Field `R` writer - this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] +pub type R_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] + #[inline(always)] + pub fn b(&self) -> B_R { + B_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] + #[inline(always)] + pub fn g(&self) -> G_R { + G_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] + #[inline(always)] + pub fn r(&self) -> R_R { + R_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_COEFF") + .field("b", &format_args!("{}", self.b().bits())) + .field("g", &format_args!("{}", self.g().bits())) + .field("r", &format_args!("{}", self.r().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] + #[inline(always)] + #[must_use] + pub fn b(&mut self) -> B_W { + B_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] + #[inline(always)] + #[must_use] + pub fn g(&mut self) -> G_W { + G_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"] + #[inline(always)] + #[must_use] + pub fn r(&mut self) -> R_W { + R_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram rgb to gray coefficients register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_coeff::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_coeff::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_COEFF_SPEC; +impl crate::RegisterSpec for HIST_COEFF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_coeff::R`](R) reader structure"] +impl crate::Readable for HIST_COEFF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_coeff::W`](W) writer structure"] +impl crate::Writable for HIST_COEFF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_COEFF to value 0x0055_5555"] +impl crate::Resettable for HIST_COEFF_SPEC { + const RESET_VALUE: Self::Ux = 0x0055_5555; +} diff --git a/esp32p4/src/isp/hist_mode.rs b/esp32p4/src/isp/hist_mode.rs new file mode 100644 index 0000000000..d969c05ea1 --- /dev/null +++ b/esp32p4/src/isp/hist_mode.rs @@ -0,0 +1,63 @@ +#[doc = "Register `HIST_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_MODE` reader - this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V"] +pub type HIST_MODE_R = crate::FieldReader; +#[doc = "Field `HIST_MODE` writer - this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V"] +pub type HIST_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V"] + #[inline(always)] + pub fn hist_mode(&self) -> HIST_MODE_R { + HIST_MODE_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_MODE") + .field("hist_mode", &format_args!("{}", self.hist_mode().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V"] + #[inline(always)] + #[must_use] + pub fn hist_mode(&mut self) -> HIST_MODE_W { + HIST_MODE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_MODE_SPEC; +impl crate::RegisterSpec for HIST_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_mode::R`](R) reader structure"] +impl crate::Readable for HIST_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_mode::W`](W) writer structure"] +impl crate::Writable for HIST_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_MODE to value 0x04"] +impl crate::Resettable for HIST_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/isp/hist_offs.rs b/esp32p4/src/isp/hist_offs.rs new file mode 100644 index 0000000000..2ec8d59a9b --- /dev/null +++ b/esp32p4/src/isp/hist_offs.rs @@ -0,0 +1,85 @@ +#[doc = "Register `HIST_OFFS` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_OFFS` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_Y_OFFS` reader - this field configures y coordinate of first window"] +pub type HIST_Y_OFFS_R = crate::FieldReader; +#[doc = "Field `HIST_Y_OFFS` writer - this field configures y coordinate of first window"] +pub type HIST_Y_OFFS_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `HIST_X_OFFS` reader - this field configures x coordinate of first window"] +pub type HIST_X_OFFS_R = crate::FieldReader; +#[doc = "Field `HIST_X_OFFS` writer - this field configures x coordinate of first window"] +pub type HIST_X_OFFS_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures y coordinate of first window"] + #[inline(always)] + pub fn hist_y_offs(&self) -> HIST_Y_OFFS_R { + HIST_Y_OFFS_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures x coordinate of first window"] + #[inline(always)] + pub fn hist_x_offs(&self) -> HIST_X_OFFS_R { + HIST_X_OFFS_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_OFFS") + .field( + "hist_y_offs", + &format_args!("{}", self.hist_y_offs().bits()), + ) + .field( + "hist_x_offs", + &format_args!("{}", self.hist_x_offs().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures y coordinate of first window"] + #[inline(always)] + #[must_use] + pub fn hist_y_offs(&mut self) -> HIST_Y_OFFS_W { + HIST_Y_OFFS_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures x coordinate of first window"] + #[inline(always)] + #[must_use] + pub fn hist_x_offs(&mut self) -> HIST_X_OFFS_W { + HIST_X_OFFS_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram window offsets register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_offs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_offs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_OFFS_SPEC; +impl crate::RegisterSpec for HIST_OFFS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_offs::R`](R) reader structure"] +impl crate::Readable for HIST_OFFS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_offs::W`](W) writer structure"] +impl crate::Writable for HIST_OFFS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_OFFS to value 0"] +impl crate::Resettable for HIST_OFFS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/hist_seg0.rs b/esp32p4/src/isp/hist_seg0.rs new file mode 100644 index 0000000000..638bfa2cc3 --- /dev/null +++ b/esp32p4/src/isp/hist_seg0.rs @@ -0,0 +1,123 @@ +#[doc = "Register `HIST_SEG0` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_SEG0` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_SEG_3_4` reader - this field configures threshold of histogram bin 3 and bin 4"] +pub type HIST_SEG_3_4_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_3_4` writer - this field configures threshold of histogram bin 3 and bin 4"] +pub type HIST_SEG_3_4_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_SEG_2_3` reader - this field configures threshold of histogram bin 2 and bin 3"] +pub type HIST_SEG_2_3_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_2_3` writer - this field configures threshold of histogram bin 2 and bin 3"] +pub type HIST_SEG_2_3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_SEG_1_2` reader - this field configures threshold of histogram bin 1 and bin 2"] +pub type HIST_SEG_1_2_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_1_2` writer - this field configures threshold of histogram bin 1 and bin 2"] +pub type HIST_SEG_1_2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_SEG_0_1` reader - this field configures threshold of histogram bin 0 and bin 1"] +pub type HIST_SEG_0_1_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_0_1` writer - this field configures threshold of histogram bin 0 and bin 1"] +pub type HIST_SEG_0_1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures threshold of histogram bin 3 and bin 4"] + #[inline(always)] + pub fn hist_seg_3_4(&self) -> HIST_SEG_3_4_R { + HIST_SEG_3_4_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures threshold of histogram bin 2 and bin 3"] + #[inline(always)] + pub fn hist_seg_2_3(&self) -> HIST_SEG_2_3_R { + HIST_SEG_2_3_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures threshold of histogram bin 1 and bin 2"] + #[inline(always)] + pub fn hist_seg_1_2(&self) -> HIST_SEG_1_2_R { + HIST_SEG_1_2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures threshold of histogram bin 0 and bin 1"] + #[inline(always)] + pub fn hist_seg_0_1(&self) -> HIST_SEG_0_1_R { + HIST_SEG_0_1_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_SEG0") + .field( + "hist_seg_3_4", + &format_args!("{}", self.hist_seg_3_4().bits()), + ) + .field( + "hist_seg_2_3", + &format_args!("{}", self.hist_seg_2_3().bits()), + ) + .field( + "hist_seg_1_2", + &format_args!("{}", self.hist_seg_1_2().bits()), + ) + .field( + "hist_seg_0_1", + &format_args!("{}", self.hist_seg_0_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures threshold of histogram bin 3 and bin 4"] + #[inline(always)] + #[must_use] + pub fn hist_seg_3_4(&mut self) -> HIST_SEG_3_4_W { + HIST_SEG_3_4_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures threshold of histogram bin 2 and bin 3"] + #[inline(always)] + #[must_use] + pub fn hist_seg_2_3(&mut self) -> HIST_SEG_2_3_W { + HIST_SEG_2_3_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures threshold of histogram bin 1 and bin 2"] + #[inline(always)] + #[must_use] + pub fn hist_seg_1_2(&mut self) -> HIST_SEG_1_2_W { + HIST_SEG_1_2_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures threshold of histogram bin 0 and bin 1"] + #[inline(always)] + #[must_use] + pub fn hist_seg_0_1(&mut self) -> HIST_SEG_0_1_W { + HIST_SEG_0_1_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram bin control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_seg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_seg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_SEG0_SPEC; +impl crate::RegisterSpec for HIST_SEG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_seg0::R`](R) reader structure"] +impl crate::Readable for HIST_SEG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_seg0::W`](W) writer structure"] +impl crate::Writable for HIST_SEG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_SEG0 to value 0x1020_3040"] +impl crate::Resettable for HIST_SEG0_SPEC { + const RESET_VALUE: Self::Ux = 0x1020_3040; +} diff --git a/esp32p4/src/isp/hist_seg1.rs b/esp32p4/src/isp/hist_seg1.rs new file mode 100644 index 0000000000..aee404399a --- /dev/null +++ b/esp32p4/src/isp/hist_seg1.rs @@ -0,0 +1,123 @@ +#[doc = "Register `HIST_SEG1` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_SEG1` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_SEG_7_8` reader - this field configures threshold of histogram bin 7 and bin 8"] +pub type HIST_SEG_7_8_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_7_8` writer - this field configures threshold of histogram bin 7 and bin 8"] +pub type HIST_SEG_7_8_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_SEG_6_7` reader - this field configures threshold of histogram bin 6 and bin 7"] +pub type HIST_SEG_6_7_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_6_7` writer - this field configures threshold of histogram bin 6 and bin 7"] +pub type HIST_SEG_6_7_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_SEG_5_6` reader - this field configures threshold of histogram bin 5 and bin 6"] +pub type HIST_SEG_5_6_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_5_6` writer - this field configures threshold of histogram bin 5 and bin 6"] +pub type HIST_SEG_5_6_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_SEG_4_5` reader - this field configures threshold of histogram bin 4 and bin 5"] +pub type HIST_SEG_4_5_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_4_5` writer - this field configures threshold of histogram bin 4 and bin 5"] +pub type HIST_SEG_4_5_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures threshold of histogram bin 7 and bin 8"] + #[inline(always)] + pub fn hist_seg_7_8(&self) -> HIST_SEG_7_8_R { + HIST_SEG_7_8_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures threshold of histogram bin 6 and bin 7"] + #[inline(always)] + pub fn hist_seg_6_7(&self) -> HIST_SEG_6_7_R { + HIST_SEG_6_7_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures threshold of histogram bin 5 and bin 6"] + #[inline(always)] + pub fn hist_seg_5_6(&self) -> HIST_SEG_5_6_R { + HIST_SEG_5_6_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures threshold of histogram bin 4 and bin 5"] + #[inline(always)] + pub fn hist_seg_4_5(&self) -> HIST_SEG_4_5_R { + HIST_SEG_4_5_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_SEG1") + .field( + "hist_seg_7_8", + &format_args!("{}", self.hist_seg_7_8().bits()), + ) + .field( + "hist_seg_6_7", + &format_args!("{}", self.hist_seg_6_7().bits()), + ) + .field( + "hist_seg_5_6", + &format_args!("{}", self.hist_seg_5_6().bits()), + ) + .field( + "hist_seg_4_5", + &format_args!("{}", self.hist_seg_4_5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures threshold of histogram bin 7 and bin 8"] + #[inline(always)] + #[must_use] + pub fn hist_seg_7_8(&mut self) -> HIST_SEG_7_8_W { + HIST_SEG_7_8_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures threshold of histogram bin 6 and bin 7"] + #[inline(always)] + #[must_use] + pub fn hist_seg_6_7(&mut self) -> HIST_SEG_6_7_W { + HIST_SEG_6_7_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures threshold of histogram bin 5 and bin 6"] + #[inline(always)] + #[must_use] + pub fn hist_seg_5_6(&mut self) -> HIST_SEG_5_6_W { + HIST_SEG_5_6_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures threshold of histogram bin 4 and bin 5"] + #[inline(always)] + #[must_use] + pub fn hist_seg_4_5(&mut self) -> HIST_SEG_4_5_W { + HIST_SEG_4_5_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram bin control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_seg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_seg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_SEG1_SPEC; +impl crate::RegisterSpec for HIST_SEG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_seg1::R`](R) reader structure"] +impl crate::Readable for HIST_SEG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_seg1::W`](W) writer structure"] +impl crate::Writable for HIST_SEG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_SEG1 to value 0x5060_7080"] +impl crate::Resettable for HIST_SEG1_SPEC { + const RESET_VALUE: Self::Ux = 0x5060_7080; +} diff --git a/esp32p4/src/isp/hist_seg2.rs b/esp32p4/src/isp/hist_seg2.rs new file mode 100644 index 0000000000..1ef8ab2b48 --- /dev/null +++ b/esp32p4/src/isp/hist_seg2.rs @@ -0,0 +1,123 @@ +#[doc = "Register `HIST_SEG2` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_SEG2` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_SEG_11_12` reader - this field configures threshold of histogram bin 11 and bin 12"] +pub type HIST_SEG_11_12_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_11_12` writer - this field configures threshold of histogram bin 11 and bin 12"] +pub type HIST_SEG_11_12_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_SEG_10_11` reader - this field configures threshold of histogram bin 10 and bin 11"] +pub type HIST_SEG_10_11_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_10_11` writer - this field configures threshold of histogram bin 10 and bin 11"] +pub type HIST_SEG_10_11_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_SEG_9_10` reader - this field configures threshold of histogram bin 9 and bin 10"] +pub type HIST_SEG_9_10_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_9_10` writer - this field configures threshold of histogram bin 9 and bin 10"] +pub type HIST_SEG_9_10_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_SEG_8_9` reader - this field configures threshold of histogram bin 8 and bin 9"] +pub type HIST_SEG_8_9_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_8_9` writer - this field configures threshold of histogram bin 8 and bin 9"] +pub type HIST_SEG_8_9_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures threshold of histogram bin 11 and bin 12"] + #[inline(always)] + pub fn hist_seg_11_12(&self) -> HIST_SEG_11_12_R { + HIST_SEG_11_12_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures threshold of histogram bin 10 and bin 11"] + #[inline(always)] + pub fn hist_seg_10_11(&self) -> HIST_SEG_10_11_R { + HIST_SEG_10_11_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures threshold of histogram bin 9 and bin 10"] + #[inline(always)] + pub fn hist_seg_9_10(&self) -> HIST_SEG_9_10_R { + HIST_SEG_9_10_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures threshold of histogram bin 8 and bin 9"] + #[inline(always)] + pub fn hist_seg_8_9(&self) -> HIST_SEG_8_9_R { + HIST_SEG_8_9_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_SEG2") + .field( + "hist_seg_11_12", + &format_args!("{}", self.hist_seg_11_12().bits()), + ) + .field( + "hist_seg_10_11", + &format_args!("{}", self.hist_seg_10_11().bits()), + ) + .field( + "hist_seg_9_10", + &format_args!("{}", self.hist_seg_9_10().bits()), + ) + .field( + "hist_seg_8_9", + &format_args!("{}", self.hist_seg_8_9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures threshold of histogram bin 11 and bin 12"] + #[inline(always)] + #[must_use] + pub fn hist_seg_11_12(&mut self) -> HIST_SEG_11_12_W { + HIST_SEG_11_12_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures threshold of histogram bin 10 and bin 11"] + #[inline(always)] + #[must_use] + pub fn hist_seg_10_11(&mut self) -> HIST_SEG_10_11_W { + HIST_SEG_10_11_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures threshold of histogram bin 9 and bin 10"] + #[inline(always)] + #[must_use] + pub fn hist_seg_9_10(&mut self) -> HIST_SEG_9_10_W { + HIST_SEG_9_10_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures threshold of histogram bin 8 and bin 9"] + #[inline(always)] + #[must_use] + pub fn hist_seg_8_9(&mut self) -> HIST_SEG_8_9_W { + HIST_SEG_8_9_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram bin control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_seg2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_seg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_SEG2_SPEC; +impl crate::RegisterSpec for HIST_SEG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_seg2::R`](R) reader structure"] +impl crate::Readable for HIST_SEG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_seg2::W`](W) writer structure"] +impl crate::Writable for HIST_SEG2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_SEG2 to value 0x90a0_b0c0"] +impl crate::Resettable for HIST_SEG2_SPEC { + const RESET_VALUE: Self::Ux = 0x90a0_b0c0; +} diff --git a/esp32p4/src/isp/hist_seg3.rs b/esp32p4/src/isp/hist_seg3.rs new file mode 100644 index 0000000000..7b710c2c20 --- /dev/null +++ b/esp32p4/src/isp/hist_seg3.rs @@ -0,0 +1,104 @@ +#[doc = "Register `HIST_SEG3` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_SEG3` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_SEG_14_15` reader - this field configures threshold of histogram bin 14 and bin 15"] +pub type HIST_SEG_14_15_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_14_15` writer - this field configures threshold of histogram bin 14 and bin 15"] +pub type HIST_SEG_14_15_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_SEG_13_14` reader - this field configures threshold of histogram bin 13 and bin 14"] +pub type HIST_SEG_13_14_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_13_14` writer - this field configures threshold of histogram bin 13 and bin 14"] +pub type HIST_SEG_13_14_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_SEG_12_13` reader - this field configures threshold of histogram bin 12 and bin 13"] +pub type HIST_SEG_12_13_R = crate::FieldReader; +#[doc = "Field `HIST_SEG_12_13` writer - this field configures threshold of histogram bin 12 and bin 13"] +pub type HIST_SEG_12_13_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures threshold of histogram bin 14 and bin 15"] + #[inline(always)] + pub fn hist_seg_14_15(&self) -> HIST_SEG_14_15_R { + HIST_SEG_14_15_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures threshold of histogram bin 13 and bin 14"] + #[inline(always)] + pub fn hist_seg_13_14(&self) -> HIST_SEG_13_14_R { + HIST_SEG_13_14_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures threshold of histogram bin 12 and bin 13"] + #[inline(always)] + pub fn hist_seg_12_13(&self) -> HIST_SEG_12_13_R { + HIST_SEG_12_13_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_SEG3") + .field( + "hist_seg_14_15", + &format_args!("{}", self.hist_seg_14_15().bits()), + ) + .field( + "hist_seg_13_14", + &format_args!("{}", self.hist_seg_13_14().bits()), + ) + .field( + "hist_seg_12_13", + &format_args!("{}", self.hist_seg_12_13().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures threshold of histogram bin 14 and bin 15"] + #[inline(always)] + #[must_use] + pub fn hist_seg_14_15(&mut self) -> HIST_SEG_14_15_W { + HIST_SEG_14_15_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures threshold of histogram bin 13 and bin 14"] + #[inline(always)] + #[must_use] + pub fn hist_seg_13_14(&mut self) -> HIST_SEG_13_14_W { + HIST_SEG_13_14_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures threshold of histogram bin 12 and bin 13"] + #[inline(always)] + #[must_use] + pub fn hist_seg_12_13(&mut self) -> HIST_SEG_12_13_W { + HIST_SEG_12_13_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram bin control register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_seg3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_seg3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_SEG3_SPEC; +impl crate::RegisterSpec for HIST_SEG3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_seg3::R`](R) reader structure"] +impl crate::Readable for HIST_SEG3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_seg3::W`](W) writer structure"] +impl crate::Writable for HIST_SEG3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_SEG3 to value 0x00d0_e0f0"] +impl crate::Resettable for HIST_SEG3_SPEC { + const RESET_VALUE: Self::Ux = 0x00d0_e0f0; +} diff --git a/esp32p4/src/isp/hist_size.rs b/esp32p4/src/isp/hist_size.rs new file mode 100644 index 0000000000..d935184924 --- /dev/null +++ b/esp32p4/src/isp/hist_size.rs @@ -0,0 +1,85 @@ +#[doc = "Register `HIST_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_Y_SIZE` reader - this field configures y direction size of subwindow"] +pub type HIST_Y_SIZE_R = crate::FieldReader; +#[doc = "Field `HIST_Y_SIZE` writer - this field configures y direction size of subwindow"] +pub type HIST_Y_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `HIST_X_SIZE` reader - this field configures x direction size of subwindow"] +pub type HIST_X_SIZE_R = crate::FieldReader; +#[doc = "Field `HIST_X_SIZE` writer - this field configures x direction size of subwindow"] +pub type HIST_X_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - this field configures y direction size of subwindow"] + #[inline(always)] + pub fn hist_y_size(&self) -> HIST_Y_SIZE_R { + HIST_Y_SIZE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 16:24 - this field configures x direction size of subwindow"] + #[inline(always)] + pub fn hist_x_size(&self) -> HIST_X_SIZE_R { + HIST_X_SIZE_R::new(((self.bits >> 16) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_SIZE") + .field( + "hist_y_size", + &format_args!("{}", self.hist_y_size().bits()), + ) + .field( + "hist_x_size", + &format_args!("{}", self.hist_x_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - this field configures y direction size of subwindow"] + #[inline(always)] + #[must_use] + pub fn hist_y_size(&mut self) -> HIST_Y_SIZE_W { + HIST_Y_SIZE_W::new(self, 0) + } + #[doc = "Bits 16:24 - this field configures x direction size of subwindow"] + #[inline(always)] + #[must_use] + pub fn hist_x_size(&mut self) -> HIST_X_SIZE_W { + HIST_X_SIZE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram sub-window size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_SIZE_SPEC; +impl crate::RegisterSpec for HIST_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_size::R`](R) reader structure"] +impl crate::Readable for HIST_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_size::W`](W) writer structure"] +impl crate::Writable for HIST_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_SIZE to value 0x0012_0020"] +impl crate::Resettable for HIST_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0x0012_0020; +} diff --git a/esp32p4/src/isp/hist_weight0.rs b/esp32p4/src/isp/hist_weight0.rs new file mode 100644 index 0000000000..19778e76b9 --- /dev/null +++ b/esp32p4/src/isp/hist_weight0.rs @@ -0,0 +1,123 @@ +#[doc = "Register `HIST_WEIGHT0` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_WEIGHT0` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_WEIGHT_03` reader - this field configures weight of subwindow 03"] +pub type HIST_WEIGHT_03_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_03` writer - this field configures weight of subwindow 03"] +pub type HIST_WEIGHT_03_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_02` reader - this field configures weight of subwindow 02"] +pub type HIST_WEIGHT_02_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_02` writer - this field configures weight of subwindow 02"] +pub type HIST_WEIGHT_02_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_01` reader - this field configures weight of subwindow 01"] +pub type HIST_WEIGHT_01_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_01` writer - this field configures weight of subwindow 01"] +pub type HIST_WEIGHT_01_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_00` reader - this field configures weight of subwindow 00 and sum of all weight should be 256"] +pub type HIST_WEIGHT_00_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_00` writer - this field configures weight of subwindow 00 and sum of all weight should be 256"] +pub type HIST_WEIGHT_00_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures weight of subwindow 03"] + #[inline(always)] + pub fn hist_weight_03(&self) -> HIST_WEIGHT_03_R { + HIST_WEIGHT_03_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 02"] + #[inline(always)] + pub fn hist_weight_02(&self) -> HIST_WEIGHT_02_R { + HIST_WEIGHT_02_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 01"] + #[inline(always)] + pub fn hist_weight_01(&self) -> HIST_WEIGHT_01_R { + HIST_WEIGHT_01_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 00 and sum of all weight should be 256"] + #[inline(always)] + pub fn hist_weight_00(&self) -> HIST_WEIGHT_00_R { + HIST_WEIGHT_00_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_WEIGHT0") + .field( + "hist_weight_03", + &format_args!("{}", self.hist_weight_03().bits()), + ) + .field( + "hist_weight_02", + &format_args!("{}", self.hist_weight_02().bits()), + ) + .field( + "hist_weight_01", + &format_args!("{}", self.hist_weight_01().bits()), + ) + .field( + "hist_weight_00", + &format_args!("{}", self.hist_weight_00().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures weight of subwindow 03"] + #[inline(always)] + #[must_use] + pub fn hist_weight_03(&mut self) -> HIST_WEIGHT_03_W { + HIST_WEIGHT_03_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 02"] + #[inline(always)] + #[must_use] + pub fn hist_weight_02(&mut self) -> HIST_WEIGHT_02_W { + HIST_WEIGHT_02_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 01"] + #[inline(always)] + #[must_use] + pub fn hist_weight_01(&mut self) -> HIST_WEIGHT_01_W { + HIST_WEIGHT_01_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 00 and sum of all weight should be 256"] + #[inline(always)] + #[must_use] + pub fn hist_weight_00(&mut self) -> HIST_WEIGHT_00_W { + HIST_WEIGHT_00_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram sub-window weight register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_WEIGHT0_SPEC; +impl crate::RegisterSpec for HIST_WEIGHT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_weight0::R`](R) reader structure"] +impl crate::Readable for HIST_WEIGHT0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_weight0::W`](W) writer structure"] +impl crate::Writable for HIST_WEIGHT0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_WEIGHT0 to value 0x0101_0101"] +impl crate::Resettable for HIST_WEIGHT0_SPEC { + const RESET_VALUE: Self::Ux = 0x0101_0101; +} diff --git a/esp32p4/src/isp/hist_weight1.rs b/esp32p4/src/isp/hist_weight1.rs new file mode 100644 index 0000000000..2ea041ab24 --- /dev/null +++ b/esp32p4/src/isp/hist_weight1.rs @@ -0,0 +1,123 @@ +#[doc = "Register `HIST_WEIGHT1` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_WEIGHT1` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_WEIGHT_12` reader - this field configures weight of subwindow 12"] +pub type HIST_WEIGHT_12_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_12` writer - this field configures weight of subwindow 12"] +pub type HIST_WEIGHT_12_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_11` reader - this field configures weight of subwindow 11"] +pub type HIST_WEIGHT_11_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_11` writer - this field configures weight of subwindow 11"] +pub type HIST_WEIGHT_11_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_10` reader - this field configures weight of subwindow 10"] +pub type HIST_WEIGHT_10_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_10` writer - this field configures weight of subwindow 10"] +pub type HIST_WEIGHT_10_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_04` reader - this field configures weight of subwindow 04"] +pub type HIST_WEIGHT_04_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_04` writer - this field configures weight of subwindow 04"] +pub type HIST_WEIGHT_04_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures weight of subwindow 12"] + #[inline(always)] + pub fn hist_weight_12(&self) -> HIST_WEIGHT_12_R { + HIST_WEIGHT_12_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 11"] + #[inline(always)] + pub fn hist_weight_11(&self) -> HIST_WEIGHT_11_R { + HIST_WEIGHT_11_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 10"] + #[inline(always)] + pub fn hist_weight_10(&self) -> HIST_WEIGHT_10_R { + HIST_WEIGHT_10_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 04"] + #[inline(always)] + pub fn hist_weight_04(&self) -> HIST_WEIGHT_04_R { + HIST_WEIGHT_04_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_WEIGHT1") + .field( + "hist_weight_12", + &format_args!("{}", self.hist_weight_12().bits()), + ) + .field( + "hist_weight_11", + &format_args!("{}", self.hist_weight_11().bits()), + ) + .field( + "hist_weight_10", + &format_args!("{}", self.hist_weight_10().bits()), + ) + .field( + "hist_weight_04", + &format_args!("{}", self.hist_weight_04().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures weight of subwindow 12"] + #[inline(always)] + #[must_use] + pub fn hist_weight_12(&mut self) -> HIST_WEIGHT_12_W { + HIST_WEIGHT_12_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 11"] + #[inline(always)] + #[must_use] + pub fn hist_weight_11(&mut self) -> HIST_WEIGHT_11_W { + HIST_WEIGHT_11_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 10"] + #[inline(always)] + #[must_use] + pub fn hist_weight_10(&mut self) -> HIST_WEIGHT_10_W { + HIST_WEIGHT_10_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 04"] + #[inline(always)] + #[must_use] + pub fn hist_weight_04(&mut self) -> HIST_WEIGHT_04_W { + HIST_WEIGHT_04_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram sub-window weight register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_WEIGHT1_SPEC; +impl crate::RegisterSpec for HIST_WEIGHT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_weight1::R`](R) reader structure"] +impl crate::Readable for HIST_WEIGHT1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_weight1::W`](W) writer structure"] +impl crate::Writable for HIST_WEIGHT1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_WEIGHT1 to value 0x0101_0101"] +impl crate::Resettable for HIST_WEIGHT1_SPEC { + const RESET_VALUE: Self::Ux = 0x0101_0101; +} diff --git a/esp32p4/src/isp/hist_weight2.rs b/esp32p4/src/isp/hist_weight2.rs new file mode 100644 index 0000000000..c173a2a7b1 --- /dev/null +++ b/esp32p4/src/isp/hist_weight2.rs @@ -0,0 +1,123 @@ +#[doc = "Register `HIST_WEIGHT2` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_WEIGHT2` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_WEIGHT_21` reader - this field configures weight of subwindow 21"] +pub type HIST_WEIGHT_21_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_21` writer - this field configures weight of subwindow 21"] +pub type HIST_WEIGHT_21_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_20` reader - this field configures weight of subwindow 20"] +pub type HIST_WEIGHT_20_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_20` writer - this field configures weight of subwindow 20"] +pub type HIST_WEIGHT_20_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_14` reader - this field configures weight of subwindow 04"] +pub type HIST_WEIGHT_14_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_14` writer - this field configures weight of subwindow 04"] +pub type HIST_WEIGHT_14_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_13` reader - this field configures weight of subwindow 13"] +pub type HIST_WEIGHT_13_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_13` writer - this field configures weight of subwindow 13"] +pub type HIST_WEIGHT_13_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures weight of subwindow 21"] + #[inline(always)] + pub fn hist_weight_21(&self) -> HIST_WEIGHT_21_R { + HIST_WEIGHT_21_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 20"] + #[inline(always)] + pub fn hist_weight_20(&self) -> HIST_WEIGHT_20_R { + HIST_WEIGHT_20_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 04"] + #[inline(always)] + pub fn hist_weight_14(&self) -> HIST_WEIGHT_14_R { + HIST_WEIGHT_14_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 13"] + #[inline(always)] + pub fn hist_weight_13(&self) -> HIST_WEIGHT_13_R { + HIST_WEIGHT_13_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_WEIGHT2") + .field( + "hist_weight_21", + &format_args!("{}", self.hist_weight_21().bits()), + ) + .field( + "hist_weight_20", + &format_args!("{}", self.hist_weight_20().bits()), + ) + .field( + "hist_weight_14", + &format_args!("{}", self.hist_weight_14().bits()), + ) + .field( + "hist_weight_13", + &format_args!("{}", self.hist_weight_13().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures weight of subwindow 21"] + #[inline(always)] + #[must_use] + pub fn hist_weight_21(&mut self) -> HIST_WEIGHT_21_W { + HIST_WEIGHT_21_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 20"] + #[inline(always)] + #[must_use] + pub fn hist_weight_20(&mut self) -> HIST_WEIGHT_20_W { + HIST_WEIGHT_20_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 04"] + #[inline(always)] + #[must_use] + pub fn hist_weight_14(&mut self) -> HIST_WEIGHT_14_W { + HIST_WEIGHT_14_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 13"] + #[inline(always)] + #[must_use] + pub fn hist_weight_13(&mut self) -> HIST_WEIGHT_13_W { + HIST_WEIGHT_13_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram sub-window weight register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_WEIGHT2_SPEC; +impl crate::RegisterSpec for HIST_WEIGHT2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_weight2::R`](R) reader structure"] +impl crate::Readable for HIST_WEIGHT2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_weight2::W`](W) writer structure"] +impl crate::Writable for HIST_WEIGHT2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_WEIGHT2 to value 0x0101_0101"] +impl crate::Resettable for HIST_WEIGHT2_SPEC { + const RESET_VALUE: Self::Ux = 0x0101_0101; +} diff --git a/esp32p4/src/isp/hist_weight3.rs b/esp32p4/src/isp/hist_weight3.rs new file mode 100644 index 0000000000..5d831df98f --- /dev/null +++ b/esp32p4/src/isp/hist_weight3.rs @@ -0,0 +1,123 @@ +#[doc = "Register `HIST_WEIGHT3` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_WEIGHT3` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_WEIGHT_30` reader - this field configures weight of subwindow 30"] +pub type HIST_WEIGHT_30_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_30` writer - this field configures weight of subwindow 30"] +pub type HIST_WEIGHT_30_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_24` reader - this field configures weight of subwindow 24"] +pub type HIST_WEIGHT_24_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_24` writer - this field configures weight of subwindow 24"] +pub type HIST_WEIGHT_24_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_23` reader - this field configures weight of subwindow 23"] +pub type HIST_WEIGHT_23_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_23` writer - this field configures weight of subwindow 23"] +pub type HIST_WEIGHT_23_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_22` reader - this field configures weight of subwindow 22"] +pub type HIST_WEIGHT_22_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_22` writer - this field configures weight of subwindow 22"] +pub type HIST_WEIGHT_22_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures weight of subwindow 30"] + #[inline(always)] + pub fn hist_weight_30(&self) -> HIST_WEIGHT_30_R { + HIST_WEIGHT_30_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 24"] + #[inline(always)] + pub fn hist_weight_24(&self) -> HIST_WEIGHT_24_R { + HIST_WEIGHT_24_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 23"] + #[inline(always)] + pub fn hist_weight_23(&self) -> HIST_WEIGHT_23_R { + HIST_WEIGHT_23_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 22"] + #[inline(always)] + pub fn hist_weight_22(&self) -> HIST_WEIGHT_22_R { + HIST_WEIGHT_22_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_WEIGHT3") + .field( + "hist_weight_30", + &format_args!("{}", self.hist_weight_30().bits()), + ) + .field( + "hist_weight_24", + &format_args!("{}", self.hist_weight_24().bits()), + ) + .field( + "hist_weight_23", + &format_args!("{}", self.hist_weight_23().bits()), + ) + .field( + "hist_weight_22", + &format_args!("{}", self.hist_weight_22().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures weight of subwindow 30"] + #[inline(always)] + #[must_use] + pub fn hist_weight_30(&mut self) -> HIST_WEIGHT_30_W { + HIST_WEIGHT_30_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 24"] + #[inline(always)] + #[must_use] + pub fn hist_weight_24(&mut self) -> HIST_WEIGHT_24_W { + HIST_WEIGHT_24_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 23"] + #[inline(always)] + #[must_use] + pub fn hist_weight_23(&mut self) -> HIST_WEIGHT_23_W { + HIST_WEIGHT_23_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 22"] + #[inline(always)] + #[must_use] + pub fn hist_weight_22(&mut self) -> HIST_WEIGHT_22_W { + HIST_WEIGHT_22_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram sub-window weight register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_WEIGHT3_SPEC; +impl crate::RegisterSpec for HIST_WEIGHT3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_weight3::R`](R) reader structure"] +impl crate::Readable for HIST_WEIGHT3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_weight3::W`](W) writer structure"] +impl crate::Writable for HIST_WEIGHT3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_WEIGHT3 to value 0xe801_0101"] +impl crate::Resettable for HIST_WEIGHT3_SPEC { + const RESET_VALUE: Self::Ux = 0xe801_0101; +} diff --git a/esp32p4/src/isp/hist_weight4.rs b/esp32p4/src/isp/hist_weight4.rs new file mode 100644 index 0000000000..7a6a75601c --- /dev/null +++ b/esp32p4/src/isp/hist_weight4.rs @@ -0,0 +1,123 @@ +#[doc = "Register `HIST_WEIGHT4` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_WEIGHT4` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_WEIGHT_34` reader - this field configures weight of subwindow 34"] +pub type HIST_WEIGHT_34_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_34` writer - this field configures weight of subwindow 34"] +pub type HIST_WEIGHT_34_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_33` reader - this field configures weight of subwindow 33"] +pub type HIST_WEIGHT_33_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_33` writer - this field configures weight of subwindow 33"] +pub type HIST_WEIGHT_33_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_32` reader - this field configures weight of subwindow 32"] +pub type HIST_WEIGHT_32_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_32` writer - this field configures weight of subwindow 32"] +pub type HIST_WEIGHT_32_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_31` reader - this field configures weight of subwindow 31"] +pub type HIST_WEIGHT_31_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_31` writer - this field configures weight of subwindow 31"] +pub type HIST_WEIGHT_31_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures weight of subwindow 34"] + #[inline(always)] + pub fn hist_weight_34(&self) -> HIST_WEIGHT_34_R { + HIST_WEIGHT_34_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 33"] + #[inline(always)] + pub fn hist_weight_33(&self) -> HIST_WEIGHT_33_R { + HIST_WEIGHT_33_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 32"] + #[inline(always)] + pub fn hist_weight_32(&self) -> HIST_WEIGHT_32_R { + HIST_WEIGHT_32_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 31"] + #[inline(always)] + pub fn hist_weight_31(&self) -> HIST_WEIGHT_31_R { + HIST_WEIGHT_31_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_WEIGHT4") + .field( + "hist_weight_34", + &format_args!("{}", self.hist_weight_34().bits()), + ) + .field( + "hist_weight_33", + &format_args!("{}", self.hist_weight_33().bits()), + ) + .field( + "hist_weight_32", + &format_args!("{}", self.hist_weight_32().bits()), + ) + .field( + "hist_weight_31", + &format_args!("{}", self.hist_weight_31().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures weight of subwindow 34"] + #[inline(always)] + #[must_use] + pub fn hist_weight_34(&mut self) -> HIST_WEIGHT_34_W { + HIST_WEIGHT_34_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 33"] + #[inline(always)] + #[must_use] + pub fn hist_weight_33(&mut self) -> HIST_WEIGHT_33_W { + HIST_WEIGHT_33_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 32"] + #[inline(always)] + #[must_use] + pub fn hist_weight_32(&mut self) -> HIST_WEIGHT_32_W { + HIST_WEIGHT_32_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 31"] + #[inline(always)] + #[must_use] + pub fn hist_weight_31(&mut self) -> HIST_WEIGHT_31_W { + HIST_WEIGHT_31_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram sub-window weight register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_WEIGHT4_SPEC; +impl crate::RegisterSpec for HIST_WEIGHT4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_weight4::R`](R) reader structure"] +impl crate::Readable for HIST_WEIGHT4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_weight4::W`](W) writer structure"] +impl crate::Writable for HIST_WEIGHT4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_WEIGHT4 to value 0x0101_0101"] +impl crate::Resettable for HIST_WEIGHT4_SPEC { + const RESET_VALUE: Self::Ux = 0x0101_0101; +} diff --git a/esp32p4/src/isp/hist_weight5.rs b/esp32p4/src/isp/hist_weight5.rs new file mode 100644 index 0000000000..b297b1fbff --- /dev/null +++ b/esp32p4/src/isp/hist_weight5.rs @@ -0,0 +1,123 @@ +#[doc = "Register `HIST_WEIGHT5` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_WEIGHT5` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_WEIGHT_43` reader - this field configures weight of subwindow 43"] +pub type HIST_WEIGHT_43_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_43` writer - this field configures weight of subwindow 43"] +pub type HIST_WEIGHT_43_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_42` reader - this field configures weight of subwindow 42"] +pub type HIST_WEIGHT_42_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_42` writer - this field configures weight of subwindow 42"] +pub type HIST_WEIGHT_42_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_41` reader - this field configures weight of subwindow 41"] +pub type HIST_WEIGHT_41_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_41` writer - this field configures weight of subwindow 41"] +pub type HIST_WEIGHT_41_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HIST_WEIGHT_40` reader - this field configures weight of subwindow 40"] +pub type HIST_WEIGHT_40_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_40` writer - this field configures weight of subwindow 40"] +pub type HIST_WEIGHT_40_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures weight of subwindow 43"] + #[inline(always)] + pub fn hist_weight_43(&self) -> HIST_WEIGHT_43_R { + HIST_WEIGHT_43_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 42"] + #[inline(always)] + pub fn hist_weight_42(&self) -> HIST_WEIGHT_42_R { + HIST_WEIGHT_42_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 41"] + #[inline(always)] + pub fn hist_weight_41(&self) -> HIST_WEIGHT_41_R { + HIST_WEIGHT_41_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 40"] + #[inline(always)] + pub fn hist_weight_40(&self) -> HIST_WEIGHT_40_R { + HIST_WEIGHT_40_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_WEIGHT5") + .field( + "hist_weight_43", + &format_args!("{}", self.hist_weight_43().bits()), + ) + .field( + "hist_weight_42", + &format_args!("{}", self.hist_weight_42().bits()), + ) + .field( + "hist_weight_41", + &format_args!("{}", self.hist_weight_41().bits()), + ) + .field( + "hist_weight_40", + &format_args!("{}", self.hist_weight_40().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures weight of subwindow 43"] + #[inline(always)] + #[must_use] + pub fn hist_weight_43(&mut self) -> HIST_WEIGHT_43_W { + HIST_WEIGHT_43_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures weight of subwindow 42"] + #[inline(always)] + #[must_use] + pub fn hist_weight_42(&mut self) -> HIST_WEIGHT_42_W { + HIST_WEIGHT_42_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures weight of subwindow 41"] + #[inline(always)] + #[must_use] + pub fn hist_weight_41(&mut self) -> HIST_WEIGHT_41_W { + HIST_WEIGHT_41_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures weight of subwindow 40"] + #[inline(always)] + #[must_use] + pub fn hist_weight_40(&mut self) -> HIST_WEIGHT_40_W { + HIST_WEIGHT_40_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram sub-window weight register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_WEIGHT5_SPEC; +impl crate::RegisterSpec for HIST_WEIGHT5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_weight5::R`](R) reader structure"] +impl crate::Readable for HIST_WEIGHT5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_weight5::W`](W) writer structure"] +impl crate::Writable for HIST_WEIGHT5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_WEIGHT5 to value 0x0101_0101"] +impl crate::Resettable for HIST_WEIGHT5_SPEC { + const RESET_VALUE: Self::Ux = 0x0101_0101; +} diff --git a/esp32p4/src/isp/hist_weight6.rs b/esp32p4/src/isp/hist_weight6.rs new file mode 100644 index 0000000000..81e96e2948 --- /dev/null +++ b/esp32p4/src/isp/hist_weight6.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HIST_WEIGHT6` reader"] +pub type R = crate::R; +#[doc = "Register `HIST_WEIGHT6` writer"] +pub type W = crate::W; +#[doc = "Field `HIST_WEIGHT_44` reader - this field configures weight of subwindow 44"] +pub type HIST_WEIGHT_44_R = crate::FieldReader; +#[doc = "Field `HIST_WEIGHT_44` writer - this field configures weight of subwindow 44"] +pub type HIST_WEIGHT_44_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures weight of subwindow 44"] + #[inline(always)] + pub fn hist_weight_44(&self) -> HIST_WEIGHT_44_R { + HIST_WEIGHT_44_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIST_WEIGHT6") + .field( + "hist_weight_44", + &format_args!("{}", self.hist_weight_44().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures weight of subwindow 44"] + #[inline(always)] + #[must_use] + pub fn hist_weight_44(&mut self) -> HIST_WEIGHT_44_W { + HIST_WEIGHT_44_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "histogram sub-window weight register 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_weight6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hist_weight6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIST_WEIGHT6_SPEC; +impl crate::RegisterSpec for HIST_WEIGHT6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hist_weight6::R`](R) reader structure"] +impl crate::Readable for HIST_WEIGHT6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hist_weight6::W`](W) writer structure"] +impl crate::Writable for HIST_WEIGHT6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HIST_WEIGHT6 to value 0x01"] +impl crate::Resettable for HIST_WEIGHT6_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/isp/hsync_cnt.rs b/esp32p4/src/isp/hsync_cnt.rs new file mode 100644 index 0000000000..eaff08d615 --- /dev/null +++ b/esp32p4/src/isp/hsync_cnt.rs @@ -0,0 +1,63 @@ +#[doc = "Register `HSYNC_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `HSYNC_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `HSYNC_CNT` reader - this field configures the number of clock before hsync and after vsync and line_end when decodes pix data from idi to isp"] +pub type HSYNC_CNT_R = crate::FieldReader; +#[doc = "Field `HSYNC_CNT` writer - this field configures the number of clock before hsync and after vsync and line_end when decodes pix data from idi to isp"] +pub type HSYNC_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures the number of clock before hsync and after vsync and line_end when decodes pix data from idi to isp"] + #[inline(always)] + pub fn hsync_cnt(&self) -> HSYNC_CNT_R { + HSYNC_CNT_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HSYNC_CNT") + .field("hsync_cnt", &format_args!("{}", self.hsync_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures the number of clock before hsync and after vsync and line_end when decodes pix data from idi to isp"] + #[inline(always)] + #[must_use] + pub fn hsync_cnt(&mut self) -> HSYNC_CNT_W { + HSYNC_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "header hsync interval control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hsync_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hsync_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HSYNC_CNT_SPEC; +impl crate::RegisterSpec for HSYNC_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hsync_cnt::R`](R) reader structure"] +impl crate::Readable for HSYNC_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hsync_cnt::W`](W) writer structure"] +impl crate::Writable for HSYNC_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HSYNC_CNT to value 0x07"] +impl crate::Resettable for HSYNC_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0x07; +} diff --git a/esp32p4/src/isp/int_clr.rs b/esp32p4/src/isp/int_clr.rs new file mode 100644 index 0000000000..915518cd4e --- /dev/null +++ b/esp32p4/src/isp/int_clr.rs @@ -0,0 +1,272 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `ISP_DATA_TYPE_ERR_INT_CLR` writer - write 1 to clear input data type error"] +pub type ISP_DATA_TYPE_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_CLR` writer - write 1 to clear isp input fifo overflow"] +pub type ISP_ASYNC_FIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_BUF_FULL_INT_CLR` writer - write 1 to clear isp input buffer full"] +pub type ISP_BUF_FULL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_CLR` writer - write 1 to clear hnum and vnum setting format error"] +pub type ISP_HVNUM_SETTING_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_CLR` writer - write 1 to clear setting invalid reg_data_type"] +pub type ISP_DATA_TYPE_SETTING_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_CLR` writer - write 1 to clear hnum setting unmatch with mipi input"] +pub type ISP_MIPI_HNUM_UNMATCH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPC_CHECK_DONE_INT_CLR` writer - write 1 to clear dpc check done"] +pub type DPC_CHECK_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_XCOORD_ERR_INT_CLR` writer - write 1 to clear gamma setting error"] +pub type GAMMA_XCOORD_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AE_MONITOR_INT_CLR` writer - write 1 to clear ae monitor"] +pub type AE_MONITOR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AE_FRAME_DONE_INT_CLR` writer - write 1 to clear ae"] +pub type AE_FRAME_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AF_FDONE_INT_CLR` writer - write 1 to clear af statistic"] +pub type AF_FDONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AF_ENV_INT_CLR` writer - write 1 to clear af monitor"] +pub type AF_ENV_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AWB_FDONE_INT_CLR` writer - write 1 to clear awb"] +pub type AWB_FDONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HIST_FDONE_INT_CLR` writer - write 1 to clear histogram"] +pub type HIST_FDONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRAME_INT_CLR` writer - write 1 to clear isp frame end"] +pub type FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLC_FRAME_INT_CLR` writer - write 1 to clear blc frame done"] +pub type BLC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LSC_FRAME_INT_CLR` writer - write 1 to clear lsc frame done"] +pub type LSC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPC_FRAME_INT_CLR` writer - write 1 to clear dpc frame done"] +pub type DPC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BF_FRAME_INT_CLR` writer - write 1 to clear bf frame done"] +pub type BF_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEMOSAIC_FRAME_INT_CLR` writer - write 1 to clear demosaic frame done"] +pub type DEMOSAIC_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEDIAN_FRAME_INT_CLR` writer - write 1 to clear median frame done"] +pub type MEDIAN_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CCM_FRAME_INT_CLR` writer - write 1 to clear ccm frame done"] +pub type CCM_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_FRAME_INT_CLR` writer - write 1 to clear gamma frame done"] +pub type GAMMA_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RGB2YUV_FRAME_INT_CLR` writer - write 1 to clear rgb2yuv frame done"] +pub type RGB2YUV_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SHARP_FRAME_INT_CLR` writer - write 1 to clear sharp frame done"] +pub type SHARP_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COLOR_FRAME_INT_CLR` writer - write 1 to clear color frame done"] +pub type COLOR_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `YUV2RGB_FRAME_INT_CLR` writer - write 1 to clear yuv2rgb frame done"] +pub type YUV2RGB_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TAIL_IDI_FRAME_INT_CLR` writer - write 1 to clear isp_tail idi frame_end"] +pub type TAIL_IDI_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HEADER_IDI_FRAME_INT_CLR` writer - write 1 to clear real input frame end of isp_input"] +pub type HEADER_IDI_FRAME_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - write 1 to clear input data type error"] + #[inline(always)] + #[must_use] + pub fn isp_data_type_err_int_clr(&mut self) -> ISP_DATA_TYPE_ERR_INT_CLR_W { + ISP_DATA_TYPE_ERR_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - write 1 to clear isp input fifo overflow"] + #[inline(always)] + #[must_use] + pub fn isp_async_fifo_ovf_int_clr(&mut self) -> ISP_ASYNC_FIFO_OVF_INT_CLR_W { + ISP_ASYNC_FIFO_OVF_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - write 1 to clear isp input buffer full"] + #[inline(always)] + #[must_use] + pub fn isp_buf_full_int_clr(&mut self) -> ISP_BUF_FULL_INT_CLR_W { + ISP_BUF_FULL_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - write 1 to clear hnum and vnum setting format error"] + #[inline(always)] + #[must_use] + pub fn isp_hvnum_setting_err_int_clr( + &mut self, + ) -> ISP_HVNUM_SETTING_ERR_INT_CLR_W { + ISP_HVNUM_SETTING_ERR_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - write 1 to clear setting invalid reg_data_type"] + #[inline(always)] + #[must_use] + pub fn isp_data_type_setting_err_int_clr( + &mut self, + ) -> ISP_DATA_TYPE_SETTING_ERR_INT_CLR_W { + ISP_DATA_TYPE_SETTING_ERR_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - write 1 to clear hnum setting unmatch with mipi input"] + #[inline(always)] + #[must_use] + pub fn isp_mipi_hnum_unmatch_int_clr( + &mut self, + ) -> ISP_MIPI_HNUM_UNMATCH_INT_CLR_W { + ISP_MIPI_HNUM_UNMATCH_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - write 1 to clear dpc check done"] + #[inline(always)] + #[must_use] + pub fn dpc_check_done_int_clr(&mut self) -> DPC_CHECK_DONE_INT_CLR_W { + DPC_CHECK_DONE_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - write 1 to clear gamma setting error"] + #[inline(always)] + #[must_use] + pub fn gamma_xcoord_err_int_clr(&mut self) -> GAMMA_XCOORD_ERR_INT_CLR_W { + GAMMA_XCOORD_ERR_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - write 1 to clear ae monitor"] + #[inline(always)] + #[must_use] + pub fn ae_monitor_int_clr(&mut self) -> AE_MONITOR_INT_CLR_W { + AE_MONITOR_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - write 1 to clear ae"] + #[inline(always)] + #[must_use] + pub fn ae_frame_done_int_clr(&mut self) -> AE_FRAME_DONE_INT_CLR_W { + AE_FRAME_DONE_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - write 1 to clear af statistic"] + #[inline(always)] + #[must_use] + pub fn af_fdone_int_clr(&mut self) -> AF_FDONE_INT_CLR_W { + AF_FDONE_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - write 1 to clear af monitor"] + #[inline(always)] + #[must_use] + pub fn af_env_int_clr(&mut self) -> AF_ENV_INT_CLR_W { + AF_ENV_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - write 1 to clear awb"] + #[inline(always)] + #[must_use] + pub fn awb_fdone_int_clr(&mut self) -> AWB_FDONE_INT_CLR_W { + AWB_FDONE_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - write 1 to clear histogram"] + #[inline(always)] + #[must_use] + pub fn hist_fdone_int_clr(&mut self) -> HIST_FDONE_INT_CLR_W { + HIST_FDONE_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - write 1 to clear isp frame end"] + #[inline(always)] + #[must_use] + pub fn frame_int_clr(&mut self) -> FRAME_INT_CLR_W { + FRAME_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - write 1 to clear blc frame done"] + #[inline(always)] + #[must_use] + pub fn blc_frame_int_clr(&mut self) -> BLC_FRAME_INT_CLR_W { + BLC_FRAME_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - write 1 to clear lsc frame done"] + #[inline(always)] + #[must_use] + pub fn lsc_frame_int_clr(&mut self) -> LSC_FRAME_INT_CLR_W { + LSC_FRAME_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - write 1 to clear dpc frame done"] + #[inline(always)] + #[must_use] + pub fn dpc_frame_int_clr(&mut self) -> DPC_FRAME_INT_CLR_W { + DPC_FRAME_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - write 1 to clear bf frame done"] + #[inline(always)] + #[must_use] + pub fn bf_frame_int_clr(&mut self) -> BF_FRAME_INT_CLR_W { + BF_FRAME_INT_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - write 1 to clear demosaic frame done"] + #[inline(always)] + #[must_use] + pub fn demosaic_frame_int_clr(&mut self) -> DEMOSAIC_FRAME_INT_CLR_W { + DEMOSAIC_FRAME_INT_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - write 1 to clear median frame done"] + #[inline(always)] + #[must_use] + pub fn median_frame_int_clr(&mut self) -> MEDIAN_FRAME_INT_CLR_W { + MEDIAN_FRAME_INT_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - write 1 to clear ccm frame done"] + #[inline(always)] + #[must_use] + pub fn ccm_frame_int_clr(&mut self) -> CCM_FRAME_INT_CLR_W { + CCM_FRAME_INT_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - write 1 to clear gamma frame done"] + #[inline(always)] + #[must_use] + pub fn gamma_frame_int_clr(&mut self) -> GAMMA_FRAME_INT_CLR_W { + GAMMA_FRAME_INT_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - write 1 to clear rgb2yuv frame done"] + #[inline(always)] + #[must_use] + pub fn rgb2yuv_frame_int_clr(&mut self) -> RGB2YUV_FRAME_INT_CLR_W { + RGB2YUV_FRAME_INT_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - write 1 to clear sharp frame done"] + #[inline(always)] + #[must_use] + pub fn sharp_frame_int_clr(&mut self) -> SHARP_FRAME_INT_CLR_W { + SHARP_FRAME_INT_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - write 1 to clear color frame done"] + #[inline(always)] + #[must_use] + pub fn color_frame_int_clr(&mut self) -> COLOR_FRAME_INT_CLR_W { + COLOR_FRAME_INT_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - write 1 to clear yuv2rgb frame done"] + #[inline(always)] + #[must_use] + pub fn yuv2rgb_frame_int_clr(&mut self) -> YUV2RGB_FRAME_INT_CLR_W { + YUV2RGB_FRAME_INT_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - write 1 to clear isp_tail idi frame_end"] + #[inline(always)] + #[must_use] + pub fn tail_idi_frame_int_clr(&mut self) -> TAIL_IDI_FRAME_INT_CLR_W { + TAIL_IDI_FRAME_INT_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - write 1 to clear real input frame end of isp_input"] + #[inline(always)] + #[must_use] + pub fn header_idi_frame_int_clr(&mut self) -> HEADER_IDI_FRAME_INT_CLR_W { + HEADER_IDI_FRAME_INT_CLR_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/int_ena.rs b/esp32p4/src/isp/int_ena.rs new file mode 100644 index 0000000000..87540d6034 --- /dev/null +++ b/esp32p4/src/isp/int_ena.rs @@ -0,0 +1,604 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `ISP_DATA_TYPE_ERR_INT_ENA` reader - write 1 to enable input data type error"] +pub type ISP_DATA_TYPE_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `ISP_DATA_TYPE_ERR_INT_ENA` writer - write 1 to enable input data type error"] +pub type ISP_DATA_TYPE_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_ENA` reader - write 1 to enable isp input fifo overflow"] +pub type ISP_ASYNC_FIFO_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_ENA` writer - write 1 to enable isp input fifo overflow"] +pub type ISP_ASYNC_FIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_BUF_FULL_INT_ENA` reader - write 1 to enable isp input buffer full"] +pub type ISP_BUF_FULL_INT_ENA_R = crate::BitReader; +#[doc = "Field `ISP_BUF_FULL_INT_ENA` writer - write 1 to enable isp input buffer full"] +pub type ISP_BUF_FULL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_ENA` reader - write 1 to enable hnum and vnum setting format error"] +pub type ISP_HVNUM_SETTING_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_ENA` writer - write 1 to enable hnum and vnum setting format error"] +pub type ISP_HVNUM_SETTING_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_ENA` reader - write 1 to enable setting invalid reg_data_type"] +pub type ISP_DATA_TYPE_SETTING_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_ENA` writer - write 1 to enable setting invalid reg_data_type"] +pub type ISP_DATA_TYPE_SETTING_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_ENA` reader - write 1 to enable hnum setting unmatch with mipi input"] +pub type ISP_MIPI_HNUM_UNMATCH_INT_ENA_R = crate::BitReader; +#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_ENA` writer - write 1 to enable hnum setting unmatch with mipi input"] +pub type ISP_MIPI_HNUM_UNMATCH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPC_CHECK_DONE_INT_ENA` reader - write 1 to enable dpc check done"] +pub type DPC_CHECK_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `DPC_CHECK_DONE_INT_ENA` writer - write 1 to enable dpc check done"] +pub type DPC_CHECK_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_XCOORD_ERR_INT_ENA` reader - write 1 to enable gamma setting error"] +pub type GAMMA_XCOORD_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `GAMMA_XCOORD_ERR_INT_ENA` writer - write 1 to enable gamma setting error"] +pub type GAMMA_XCOORD_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AE_MONITOR_INT_ENA` reader - write 1 to enable ae monitor"] +pub type AE_MONITOR_INT_ENA_R = crate::BitReader; +#[doc = "Field `AE_MONITOR_INT_ENA` writer - write 1 to enable ae monitor"] +pub type AE_MONITOR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AE_FRAME_DONE_INT_ENA` reader - write 1 to enable ae"] +pub type AE_FRAME_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `AE_FRAME_DONE_INT_ENA` writer - write 1 to enable ae"] +pub type AE_FRAME_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AF_FDONE_INT_ENA` reader - write 1 to enable af statistic"] +pub type AF_FDONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `AF_FDONE_INT_ENA` writer - write 1 to enable af statistic"] +pub type AF_FDONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AF_ENV_INT_ENA` reader - write 1 to enable af monitor"] +pub type AF_ENV_INT_ENA_R = crate::BitReader; +#[doc = "Field `AF_ENV_INT_ENA` writer - write 1 to enable af monitor"] +pub type AF_ENV_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AWB_FDONE_INT_ENA` reader - write 1 to enable awb"] +pub type AWB_FDONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `AWB_FDONE_INT_ENA` writer - write 1 to enable awb"] +pub type AWB_FDONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HIST_FDONE_INT_ENA` reader - write 1 to enable histogram"] +pub type HIST_FDONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `HIST_FDONE_INT_ENA` writer - write 1 to enable histogram"] +pub type HIST_FDONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRAME_INT_ENA` reader - write 1 to enable isp frame end"] +pub type FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `FRAME_INT_ENA` writer - write 1 to enable isp frame end"] +pub type FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLC_FRAME_INT_ENA` reader - write 1 to enable blc frame done"] +pub type BLC_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `BLC_FRAME_INT_ENA` writer - write 1 to enable blc frame done"] +pub type BLC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LSC_FRAME_INT_ENA` reader - write 1 to enable lsc frame done"] +pub type LSC_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `LSC_FRAME_INT_ENA` writer - write 1 to enable lsc frame done"] +pub type LSC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPC_FRAME_INT_ENA` reader - write 1 to enable dpc frame done"] +pub type DPC_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `DPC_FRAME_INT_ENA` writer - write 1 to enable dpc frame done"] +pub type DPC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BF_FRAME_INT_ENA` reader - write 1 to enable bf frame done"] +pub type BF_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `BF_FRAME_INT_ENA` writer - write 1 to enable bf frame done"] +pub type BF_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEMOSAIC_FRAME_INT_ENA` reader - write 1 to enable demosaic frame done"] +pub type DEMOSAIC_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `DEMOSAIC_FRAME_INT_ENA` writer - write 1 to enable demosaic frame done"] +pub type DEMOSAIC_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEDIAN_FRAME_INT_ENA` reader - write 1 to enable median frame done"] +pub type MEDIAN_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `MEDIAN_FRAME_INT_ENA` writer - write 1 to enable median frame done"] +pub type MEDIAN_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CCM_FRAME_INT_ENA` reader - write 1 to enable ccm frame done"] +pub type CCM_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `CCM_FRAME_INT_ENA` writer - write 1 to enable ccm frame done"] +pub type CCM_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_FRAME_INT_ENA` reader - write 1 to enable gamma frame done"] +pub type GAMMA_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `GAMMA_FRAME_INT_ENA` writer - write 1 to enable gamma frame done"] +pub type GAMMA_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RGB2YUV_FRAME_INT_ENA` reader - write 1 to enable rgb2yuv frame done"] +pub type RGB2YUV_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `RGB2YUV_FRAME_INT_ENA` writer - write 1 to enable rgb2yuv frame done"] +pub type RGB2YUV_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SHARP_FRAME_INT_ENA` reader - write 1 to enable sharp frame done"] +pub type SHARP_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `SHARP_FRAME_INT_ENA` writer - write 1 to enable sharp frame done"] +pub type SHARP_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COLOR_FRAME_INT_ENA` reader - write 1 to enable color frame done"] +pub type COLOR_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `COLOR_FRAME_INT_ENA` writer - write 1 to enable color frame done"] +pub type COLOR_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `YUV2RGB_FRAME_INT_ENA` reader - write 1 to enable yuv2rgb frame done"] +pub type YUV2RGB_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `YUV2RGB_FRAME_INT_ENA` writer - write 1 to enable yuv2rgb frame done"] +pub type YUV2RGB_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TAIL_IDI_FRAME_INT_ENA` reader - write 1 to enable isp_tail idi frame_end"] +pub type TAIL_IDI_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `TAIL_IDI_FRAME_INT_ENA` writer - write 1 to enable isp_tail idi frame_end"] +pub type TAIL_IDI_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HEADER_IDI_FRAME_INT_ENA` reader - write 1 to enable real input frame end of isp_input"] +pub type HEADER_IDI_FRAME_INT_ENA_R = crate::BitReader; +#[doc = "Field `HEADER_IDI_FRAME_INT_ENA` writer - write 1 to enable real input frame end of isp_input"] +pub type HEADER_IDI_FRAME_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - write 1 to enable input data type error"] + #[inline(always)] + pub fn isp_data_type_err_int_ena(&self) -> ISP_DATA_TYPE_ERR_INT_ENA_R { + ISP_DATA_TYPE_ERR_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - write 1 to enable isp input fifo overflow"] + #[inline(always)] + pub fn isp_async_fifo_ovf_int_ena(&self) -> ISP_ASYNC_FIFO_OVF_INT_ENA_R { + ISP_ASYNC_FIFO_OVF_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - write 1 to enable isp input buffer full"] + #[inline(always)] + pub fn isp_buf_full_int_ena(&self) -> ISP_BUF_FULL_INT_ENA_R { + ISP_BUF_FULL_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - write 1 to enable hnum and vnum setting format error"] + #[inline(always)] + pub fn isp_hvnum_setting_err_int_ena(&self) -> ISP_HVNUM_SETTING_ERR_INT_ENA_R { + ISP_HVNUM_SETTING_ERR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - write 1 to enable setting invalid reg_data_type"] + #[inline(always)] + pub fn isp_data_type_setting_err_int_ena(&self) -> ISP_DATA_TYPE_SETTING_ERR_INT_ENA_R { + ISP_DATA_TYPE_SETTING_ERR_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - write 1 to enable hnum setting unmatch with mipi input"] + #[inline(always)] + pub fn isp_mipi_hnum_unmatch_int_ena(&self) -> ISP_MIPI_HNUM_UNMATCH_INT_ENA_R { + ISP_MIPI_HNUM_UNMATCH_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - write 1 to enable dpc check done"] + #[inline(always)] + pub fn dpc_check_done_int_ena(&self) -> DPC_CHECK_DONE_INT_ENA_R { + DPC_CHECK_DONE_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - write 1 to enable gamma setting error"] + #[inline(always)] + pub fn gamma_xcoord_err_int_ena(&self) -> GAMMA_XCOORD_ERR_INT_ENA_R { + GAMMA_XCOORD_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - write 1 to enable ae monitor"] + #[inline(always)] + pub fn ae_monitor_int_ena(&self) -> AE_MONITOR_INT_ENA_R { + AE_MONITOR_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - write 1 to enable ae"] + #[inline(always)] + pub fn ae_frame_done_int_ena(&self) -> AE_FRAME_DONE_INT_ENA_R { + AE_FRAME_DONE_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - write 1 to enable af statistic"] + #[inline(always)] + pub fn af_fdone_int_ena(&self) -> AF_FDONE_INT_ENA_R { + AF_FDONE_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - write 1 to enable af monitor"] + #[inline(always)] + pub fn af_env_int_ena(&self) -> AF_ENV_INT_ENA_R { + AF_ENV_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - write 1 to enable awb"] + #[inline(always)] + pub fn awb_fdone_int_ena(&self) -> AWB_FDONE_INT_ENA_R { + AWB_FDONE_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - write 1 to enable histogram"] + #[inline(always)] + pub fn hist_fdone_int_ena(&self) -> HIST_FDONE_INT_ENA_R { + HIST_FDONE_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - write 1 to enable isp frame end"] + #[inline(always)] + pub fn frame_int_ena(&self) -> FRAME_INT_ENA_R { + FRAME_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - write 1 to enable blc frame done"] + #[inline(always)] + pub fn blc_frame_int_ena(&self) -> BLC_FRAME_INT_ENA_R { + BLC_FRAME_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - write 1 to enable lsc frame done"] + #[inline(always)] + pub fn lsc_frame_int_ena(&self) -> LSC_FRAME_INT_ENA_R { + LSC_FRAME_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - write 1 to enable dpc frame done"] + #[inline(always)] + pub fn dpc_frame_int_ena(&self) -> DPC_FRAME_INT_ENA_R { + DPC_FRAME_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - write 1 to enable bf frame done"] + #[inline(always)] + pub fn bf_frame_int_ena(&self) -> BF_FRAME_INT_ENA_R { + BF_FRAME_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - write 1 to enable demosaic frame done"] + #[inline(always)] + pub fn demosaic_frame_int_ena(&self) -> DEMOSAIC_FRAME_INT_ENA_R { + DEMOSAIC_FRAME_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - write 1 to enable median frame done"] + #[inline(always)] + pub fn median_frame_int_ena(&self) -> MEDIAN_FRAME_INT_ENA_R { + MEDIAN_FRAME_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - write 1 to enable ccm frame done"] + #[inline(always)] + pub fn ccm_frame_int_ena(&self) -> CCM_FRAME_INT_ENA_R { + CCM_FRAME_INT_ENA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - write 1 to enable gamma frame done"] + #[inline(always)] + pub fn gamma_frame_int_ena(&self) -> GAMMA_FRAME_INT_ENA_R { + GAMMA_FRAME_INT_ENA_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - write 1 to enable rgb2yuv frame done"] + #[inline(always)] + pub fn rgb2yuv_frame_int_ena(&self) -> RGB2YUV_FRAME_INT_ENA_R { + RGB2YUV_FRAME_INT_ENA_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - write 1 to enable sharp frame done"] + #[inline(always)] + pub fn sharp_frame_int_ena(&self) -> SHARP_FRAME_INT_ENA_R { + SHARP_FRAME_INT_ENA_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - write 1 to enable color frame done"] + #[inline(always)] + pub fn color_frame_int_ena(&self) -> COLOR_FRAME_INT_ENA_R { + COLOR_FRAME_INT_ENA_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - write 1 to enable yuv2rgb frame done"] + #[inline(always)] + pub fn yuv2rgb_frame_int_ena(&self) -> YUV2RGB_FRAME_INT_ENA_R { + YUV2RGB_FRAME_INT_ENA_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - write 1 to enable isp_tail idi frame_end"] + #[inline(always)] + pub fn tail_idi_frame_int_ena(&self) -> TAIL_IDI_FRAME_INT_ENA_R { + TAIL_IDI_FRAME_INT_ENA_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - write 1 to enable real input frame end of isp_input"] + #[inline(always)] + pub fn header_idi_frame_int_ena(&self) -> HEADER_IDI_FRAME_INT_ENA_R { + HEADER_IDI_FRAME_INT_ENA_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "isp_data_type_err_int_ena", + &format_args!("{}", self.isp_data_type_err_int_ena().bit()), + ) + .field( + "isp_async_fifo_ovf_int_ena", + &format_args!("{}", self.isp_async_fifo_ovf_int_ena().bit()), + ) + .field( + "isp_buf_full_int_ena", + &format_args!("{}", self.isp_buf_full_int_ena().bit()), + ) + .field( + "isp_hvnum_setting_err_int_ena", + &format_args!("{}", self.isp_hvnum_setting_err_int_ena().bit()), + ) + .field( + "isp_data_type_setting_err_int_ena", + &format_args!("{}", self.isp_data_type_setting_err_int_ena().bit()), + ) + .field( + "isp_mipi_hnum_unmatch_int_ena", + &format_args!("{}", self.isp_mipi_hnum_unmatch_int_ena().bit()), + ) + .field( + "dpc_check_done_int_ena", + &format_args!("{}", self.dpc_check_done_int_ena().bit()), + ) + .field( + "gamma_xcoord_err_int_ena", + &format_args!("{}", self.gamma_xcoord_err_int_ena().bit()), + ) + .field( + "ae_monitor_int_ena", + &format_args!("{}", self.ae_monitor_int_ena().bit()), + ) + .field( + "ae_frame_done_int_ena", + &format_args!("{}", self.ae_frame_done_int_ena().bit()), + ) + .field( + "af_fdone_int_ena", + &format_args!("{}", self.af_fdone_int_ena().bit()), + ) + .field( + "af_env_int_ena", + &format_args!("{}", self.af_env_int_ena().bit()), + ) + .field( + "awb_fdone_int_ena", + &format_args!("{}", self.awb_fdone_int_ena().bit()), + ) + .field( + "hist_fdone_int_ena", + &format_args!("{}", self.hist_fdone_int_ena().bit()), + ) + .field( + "frame_int_ena", + &format_args!("{}", self.frame_int_ena().bit()), + ) + .field( + "blc_frame_int_ena", + &format_args!("{}", self.blc_frame_int_ena().bit()), + ) + .field( + "lsc_frame_int_ena", + &format_args!("{}", self.lsc_frame_int_ena().bit()), + ) + .field( + "dpc_frame_int_ena", + &format_args!("{}", self.dpc_frame_int_ena().bit()), + ) + .field( + "bf_frame_int_ena", + &format_args!("{}", self.bf_frame_int_ena().bit()), + ) + .field( + "demosaic_frame_int_ena", + &format_args!("{}", self.demosaic_frame_int_ena().bit()), + ) + .field( + "median_frame_int_ena", + &format_args!("{}", self.median_frame_int_ena().bit()), + ) + .field( + "ccm_frame_int_ena", + &format_args!("{}", self.ccm_frame_int_ena().bit()), + ) + .field( + "gamma_frame_int_ena", + &format_args!("{}", self.gamma_frame_int_ena().bit()), + ) + .field( + "rgb2yuv_frame_int_ena", + &format_args!("{}", self.rgb2yuv_frame_int_ena().bit()), + ) + .field( + "sharp_frame_int_ena", + &format_args!("{}", self.sharp_frame_int_ena().bit()), + ) + .field( + "color_frame_int_ena", + &format_args!("{}", self.color_frame_int_ena().bit()), + ) + .field( + "yuv2rgb_frame_int_ena", + &format_args!("{}", self.yuv2rgb_frame_int_ena().bit()), + ) + .field( + "tail_idi_frame_int_ena", + &format_args!("{}", self.tail_idi_frame_int_ena().bit()), + ) + .field( + "header_idi_frame_int_ena", + &format_args!("{}", self.header_idi_frame_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - write 1 to enable input data type error"] + #[inline(always)] + #[must_use] + pub fn isp_data_type_err_int_ena(&mut self) -> ISP_DATA_TYPE_ERR_INT_ENA_W { + ISP_DATA_TYPE_ERR_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - write 1 to enable isp input fifo overflow"] + #[inline(always)] + #[must_use] + pub fn isp_async_fifo_ovf_int_ena(&mut self) -> ISP_ASYNC_FIFO_OVF_INT_ENA_W { + ISP_ASYNC_FIFO_OVF_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - write 1 to enable isp input buffer full"] + #[inline(always)] + #[must_use] + pub fn isp_buf_full_int_ena(&mut self) -> ISP_BUF_FULL_INT_ENA_W { + ISP_BUF_FULL_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - write 1 to enable hnum and vnum setting format error"] + #[inline(always)] + #[must_use] + pub fn isp_hvnum_setting_err_int_ena( + &mut self, + ) -> ISP_HVNUM_SETTING_ERR_INT_ENA_W { + ISP_HVNUM_SETTING_ERR_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - write 1 to enable setting invalid reg_data_type"] + #[inline(always)] + #[must_use] + pub fn isp_data_type_setting_err_int_ena( + &mut self, + ) -> ISP_DATA_TYPE_SETTING_ERR_INT_ENA_W { + ISP_DATA_TYPE_SETTING_ERR_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - write 1 to enable hnum setting unmatch with mipi input"] + #[inline(always)] + #[must_use] + pub fn isp_mipi_hnum_unmatch_int_ena( + &mut self, + ) -> ISP_MIPI_HNUM_UNMATCH_INT_ENA_W { + ISP_MIPI_HNUM_UNMATCH_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - write 1 to enable dpc check done"] + #[inline(always)] + #[must_use] + pub fn dpc_check_done_int_ena(&mut self) -> DPC_CHECK_DONE_INT_ENA_W { + DPC_CHECK_DONE_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - write 1 to enable gamma setting error"] + #[inline(always)] + #[must_use] + pub fn gamma_xcoord_err_int_ena(&mut self) -> GAMMA_XCOORD_ERR_INT_ENA_W { + GAMMA_XCOORD_ERR_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - write 1 to enable ae monitor"] + #[inline(always)] + #[must_use] + pub fn ae_monitor_int_ena(&mut self) -> AE_MONITOR_INT_ENA_W { + AE_MONITOR_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - write 1 to enable ae"] + #[inline(always)] + #[must_use] + pub fn ae_frame_done_int_ena(&mut self) -> AE_FRAME_DONE_INT_ENA_W { + AE_FRAME_DONE_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - write 1 to enable af statistic"] + #[inline(always)] + #[must_use] + pub fn af_fdone_int_ena(&mut self) -> AF_FDONE_INT_ENA_W { + AF_FDONE_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - write 1 to enable af monitor"] + #[inline(always)] + #[must_use] + pub fn af_env_int_ena(&mut self) -> AF_ENV_INT_ENA_W { + AF_ENV_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - write 1 to enable awb"] + #[inline(always)] + #[must_use] + pub fn awb_fdone_int_ena(&mut self) -> AWB_FDONE_INT_ENA_W { + AWB_FDONE_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - write 1 to enable histogram"] + #[inline(always)] + #[must_use] + pub fn hist_fdone_int_ena(&mut self) -> HIST_FDONE_INT_ENA_W { + HIST_FDONE_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - write 1 to enable isp frame end"] + #[inline(always)] + #[must_use] + pub fn frame_int_ena(&mut self) -> FRAME_INT_ENA_W { + FRAME_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - write 1 to enable blc frame done"] + #[inline(always)] + #[must_use] + pub fn blc_frame_int_ena(&mut self) -> BLC_FRAME_INT_ENA_W { + BLC_FRAME_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - write 1 to enable lsc frame done"] + #[inline(always)] + #[must_use] + pub fn lsc_frame_int_ena(&mut self) -> LSC_FRAME_INT_ENA_W { + LSC_FRAME_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - write 1 to enable dpc frame done"] + #[inline(always)] + #[must_use] + pub fn dpc_frame_int_ena(&mut self) -> DPC_FRAME_INT_ENA_W { + DPC_FRAME_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 18 - write 1 to enable bf frame done"] + #[inline(always)] + #[must_use] + pub fn bf_frame_int_ena(&mut self) -> BF_FRAME_INT_ENA_W { + BF_FRAME_INT_ENA_W::new(self, 18) + } + #[doc = "Bit 19 - write 1 to enable demosaic frame done"] + #[inline(always)] + #[must_use] + pub fn demosaic_frame_int_ena(&mut self) -> DEMOSAIC_FRAME_INT_ENA_W { + DEMOSAIC_FRAME_INT_ENA_W::new(self, 19) + } + #[doc = "Bit 20 - write 1 to enable median frame done"] + #[inline(always)] + #[must_use] + pub fn median_frame_int_ena(&mut self) -> MEDIAN_FRAME_INT_ENA_W { + MEDIAN_FRAME_INT_ENA_W::new(self, 20) + } + #[doc = "Bit 21 - write 1 to enable ccm frame done"] + #[inline(always)] + #[must_use] + pub fn ccm_frame_int_ena(&mut self) -> CCM_FRAME_INT_ENA_W { + CCM_FRAME_INT_ENA_W::new(self, 21) + } + #[doc = "Bit 22 - write 1 to enable gamma frame done"] + #[inline(always)] + #[must_use] + pub fn gamma_frame_int_ena(&mut self) -> GAMMA_FRAME_INT_ENA_W { + GAMMA_FRAME_INT_ENA_W::new(self, 22) + } + #[doc = "Bit 23 - write 1 to enable rgb2yuv frame done"] + #[inline(always)] + #[must_use] + pub fn rgb2yuv_frame_int_ena(&mut self) -> RGB2YUV_FRAME_INT_ENA_W { + RGB2YUV_FRAME_INT_ENA_W::new(self, 23) + } + #[doc = "Bit 24 - write 1 to enable sharp frame done"] + #[inline(always)] + #[must_use] + pub fn sharp_frame_int_ena(&mut self) -> SHARP_FRAME_INT_ENA_W { + SHARP_FRAME_INT_ENA_W::new(self, 24) + } + #[doc = "Bit 25 - write 1 to enable color frame done"] + #[inline(always)] + #[must_use] + pub fn color_frame_int_ena(&mut self) -> COLOR_FRAME_INT_ENA_W { + COLOR_FRAME_INT_ENA_W::new(self, 25) + } + #[doc = "Bit 26 - write 1 to enable yuv2rgb frame done"] + #[inline(always)] + #[must_use] + pub fn yuv2rgb_frame_int_ena(&mut self) -> YUV2RGB_FRAME_INT_ENA_W { + YUV2RGB_FRAME_INT_ENA_W::new(self, 26) + } + #[doc = "Bit 27 - write 1 to enable isp_tail idi frame_end"] + #[inline(always)] + #[must_use] + pub fn tail_idi_frame_int_ena(&mut self) -> TAIL_IDI_FRAME_INT_ENA_W { + TAIL_IDI_FRAME_INT_ENA_W::new(self, 27) + } + #[doc = "Bit 28 - write 1 to enable real input frame end of isp_input"] + #[inline(always)] + #[must_use] + pub fn header_idi_frame_int_ena(&mut self) -> HEADER_IDI_FRAME_INT_ENA_W { + HEADER_IDI_FRAME_INT_ENA_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0xc3"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0xc3; +} diff --git a/esp32p4/src/isp/int_raw.rs b/esp32p4/src/isp/int_raw.rs new file mode 100644 index 0000000000..e1a81bf8fe --- /dev/null +++ b/esp32p4/src/isp/int_raw.rs @@ -0,0 +1,347 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `ISP_DATA_TYPE_ERR_INT_RAW` reader - the raw interrupt status of input data type error. isp only support RGB bayer data type, other type will report type_err_int"] +pub type ISP_DATA_TYPE_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_RAW` reader - the raw interrupt status of isp input fifo overflow"] +pub type ISP_ASYNC_FIFO_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `ISP_BUF_FULL_INT_RAW` reader - the raw interrupt status of isp input buffer full"] +pub type ISP_BUF_FULL_INT_RAW_R = crate::BitReader; +#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_RAW` reader - the raw interrupt status of hnum and vnum setting format error"] +pub type ISP_HVNUM_SETTING_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_RAW` reader - the raw interrupt status of setting invalid reg_data_type"] +pub type ISP_DATA_TYPE_SETTING_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_RAW` reader - the raw interrupt status of hnum setting unmatch with mipi input"] +pub type ISP_MIPI_HNUM_UNMATCH_INT_RAW_R = crate::BitReader; +#[doc = "Field `DPC_CHECK_DONE_INT_RAW` reader - the raw interrupt status of dpc check done"] +pub type DPC_CHECK_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `GAMMA_XCOORD_ERR_INT_RAW` reader - the raw interrupt status of gamma setting error. it report the sum of the lengths represented by reg_gamma_x00~x0F isn't equal to 256"] +pub type GAMMA_XCOORD_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `AE_MONITOR_INT_RAW` reader - the raw interrupt status of ae monitor"] +pub type AE_MONITOR_INT_RAW_R = crate::BitReader; +#[doc = "Field `AE_FRAME_DONE_INT_RAW` reader - the raw interrupt status of ae."] +pub type AE_FRAME_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `AF_FDONE_INT_RAW` reader - the raw interrupt status of af statistic. when auto_update enable, each frame done will send one int pulse when manual_update, each time when write 1 to reg_manual_update will send a int pulse when next frame done"] +pub type AF_FDONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `AF_ENV_INT_RAW` reader - the raw interrupt status of af monitor. send a int pulse when env_det function enabled and environment changes detected"] +pub type AF_ENV_INT_RAW_R = crate::BitReader; +#[doc = "Field `AWB_FDONE_INT_RAW` reader - the raw interrupt status of awb. send a int pulse when statistic of one awb frame done"] +pub type AWB_FDONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `HIST_FDONE_INT_RAW` reader - the raw interrupt status of histogram. send a int pulse when statistic of one frame histogram done"] +pub type HIST_FDONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `FRAME_INT_RAW` reader - the raw interrupt status of isp frame end"] +pub type FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `BLC_FRAME_INT_RAW` reader - the raw interrupt status of blc frame done"] +pub type BLC_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `LSC_FRAME_INT_RAW` reader - the raw interrupt status of lsc frame done"] +pub type LSC_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `DPC_FRAME_INT_RAW` reader - the raw interrupt status of dpc frame done"] +pub type DPC_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `BF_FRAME_INT_RAW` reader - the raw interrupt status of bf frame done"] +pub type BF_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `DEMOSAIC_FRAME_INT_RAW` reader - the raw interrupt status of demosaic frame done"] +pub type DEMOSAIC_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `MEDIAN_FRAME_INT_RAW` reader - the raw interrupt status of median frame done"] +pub type MEDIAN_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `CCM_FRAME_INT_RAW` reader - the raw interrupt status of ccm frame done"] +pub type CCM_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `GAMMA_FRAME_INT_RAW` reader - the raw interrupt status of gamma frame done"] +pub type GAMMA_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `RGB2YUV_FRAME_INT_RAW` reader - the raw interrupt status of rgb2yuv frame done"] +pub type RGB2YUV_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `SHARP_FRAME_INT_RAW` reader - the raw interrupt status of sharp frame done"] +pub type SHARP_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `COLOR_FRAME_INT_RAW` reader - the raw interrupt status of color frame done"] +pub type COLOR_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `YUV2RGB_FRAME_INT_RAW` reader - the raw interrupt status of yuv2rgb frame done"] +pub type YUV2RGB_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `TAIL_IDI_FRAME_INT_RAW` reader - the raw interrupt status of isp_tail idi frame_end"] +pub type TAIL_IDI_FRAME_INT_RAW_R = crate::BitReader; +#[doc = "Field `HEADER_IDI_FRAME_INT_RAW` reader - the raw interrupt status of real input frame end of isp_input"] +pub type HEADER_IDI_FRAME_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - the raw interrupt status of input data type error. isp only support RGB bayer data type, other type will report type_err_int"] + #[inline(always)] + pub fn isp_data_type_err_int_raw(&self) -> ISP_DATA_TYPE_ERR_INT_RAW_R { + ISP_DATA_TYPE_ERR_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - the raw interrupt status of isp input fifo overflow"] + #[inline(always)] + pub fn isp_async_fifo_ovf_int_raw(&self) -> ISP_ASYNC_FIFO_OVF_INT_RAW_R { + ISP_ASYNC_FIFO_OVF_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - the raw interrupt status of isp input buffer full"] + #[inline(always)] + pub fn isp_buf_full_int_raw(&self) -> ISP_BUF_FULL_INT_RAW_R { + ISP_BUF_FULL_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - the raw interrupt status of hnum and vnum setting format error"] + #[inline(always)] + pub fn isp_hvnum_setting_err_int_raw(&self) -> ISP_HVNUM_SETTING_ERR_INT_RAW_R { + ISP_HVNUM_SETTING_ERR_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the raw interrupt status of setting invalid reg_data_type"] + #[inline(always)] + pub fn isp_data_type_setting_err_int_raw(&self) -> ISP_DATA_TYPE_SETTING_ERR_INT_RAW_R { + ISP_DATA_TYPE_SETTING_ERR_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - the raw interrupt status of hnum setting unmatch with mipi input"] + #[inline(always)] + pub fn isp_mipi_hnum_unmatch_int_raw(&self) -> ISP_MIPI_HNUM_UNMATCH_INT_RAW_R { + ISP_MIPI_HNUM_UNMATCH_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - the raw interrupt status of dpc check done"] + #[inline(always)] + pub fn dpc_check_done_int_raw(&self) -> DPC_CHECK_DONE_INT_RAW_R { + DPC_CHECK_DONE_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - the raw interrupt status of gamma setting error. it report the sum of the lengths represented by reg_gamma_x00~x0F isn't equal to 256"] + #[inline(always)] + pub fn gamma_xcoord_err_int_raw(&self) -> GAMMA_XCOORD_ERR_INT_RAW_R { + GAMMA_XCOORD_ERR_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - the raw interrupt status of ae monitor"] + #[inline(always)] + pub fn ae_monitor_int_raw(&self) -> AE_MONITOR_INT_RAW_R { + AE_MONITOR_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - the raw interrupt status of ae."] + #[inline(always)] + pub fn ae_frame_done_int_raw(&self) -> AE_FRAME_DONE_INT_RAW_R { + AE_FRAME_DONE_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - the raw interrupt status of af statistic. when auto_update enable, each frame done will send one int pulse when manual_update, each time when write 1 to reg_manual_update will send a int pulse when next frame done"] + #[inline(always)] + pub fn af_fdone_int_raw(&self) -> AF_FDONE_INT_RAW_R { + AF_FDONE_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - the raw interrupt status of af monitor. send a int pulse when env_det function enabled and environment changes detected"] + #[inline(always)] + pub fn af_env_int_raw(&self) -> AF_ENV_INT_RAW_R { + AF_ENV_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - the raw interrupt status of awb. send a int pulse when statistic of one awb frame done"] + #[inline(always)] + pub fn awb_fdone_int_raw(&self) -> AWB_FDONE_INT_RAW_R { + AWB_FDONE_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - the raw interrupt status of histogram. send a int pulse when statistic of one frame histogram done"] + #[inline(always)] + pub fn hist_fdone_int_raw(&self) -> HIST_FDONE_INT_RAW_R { + HIST_FDONE_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - the raw interrupt status of isp frame end"] + #[inline(always)] + pub fn frame_int_raw(&self) -> FRAME_INT_RAW_R { + FRAME_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - the raw interrupt status of blc frame done"] + #[inline(always)] + pub fn blc_frame_int_raw(&self) -> BLC_FRAME_INT_RAW_R { + BLC_FRAME_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - the raw interrupt status of lsc frame done"] + #[inline(always)] + pub fn lsc_frame_int_raw(&self) -> LSC_FRAME_INT_RAW_R { + LSC_FRAME_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - the raw interrupt status of dpc frame done"] + #[inline(always)] + pub fn dpc_frame_int_raw(&self) -> DPC_FRAME_INT_RAW_R { + DPC_FRAME_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - the raw interrupt status of bf frame done"] + #[inline(always)] + pub fn bf_frame_int_raw(&self) -> BF_FRAME_INT_RAW_R { + BF_FRAME_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - the raw interrupt status of demosaic frame done"] + #[inline(always)] + pub fn demosaic_frame_int_raw(&self) -> DEMOSAIC_FRAME_INT_RAW_R { + DEMOSAIC_FRAME_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - the raw interrupt status of median frame done"] + #[inline(always)] + pub fn median_frame_int_raw(&self) -> MEDIAN_FRAME_INT_RAW_R { + MEDIAN_FRAME_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - the raw interrupt status of ccm frame done"] + #[inline(always)] + pub fn ccm_frame_int_raw(&self) -> CCM_FRAME_INT_RAW_R { + CCM_FRAME_INT_RAW_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - the raw interrupt status of gamma frame done"] + #[inline(always)] + pub fn gamma_frame_int_raw(&self) -> GAMMA_FRAME_INT_RAW_R { + GAMMA_FRAME_INT_RAW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - the raw interrupt status of rgb2yuv frame done"] + #[inline(always)] + pub fn rgb2yuv_frame_int_raw(&self) -> RGB2YUV_FRAME_INT_RAW_R { + RGB2YUV_FRAME_INT_RAW_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - the raw interrupt status of sharp frame done"] + #[inline(always)] + pub fn sharp_frame_int_raw(&self) -> SHARP_FRAME_INT_RAW_R { + SHARP_FRAME_INT_RAW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - the raw interrupt status of color frame done"] + #[inline(always)] + pub fn color_frame_int_raw(&self) -> COLOR_FRAME_INT_RAW_R { + COLOR_FRAME_INT_RAW_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - the raw interrupt status of yuv2rgb frame done"] + #[inline(always)] + pub fn yuv2rgb_frame_int_raw(&self) -> YUV2RGB_FRAME_INT_RAW_R { + YUV2RGB_FRAME_INT_RAW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - the raw interrupt status of isp_tail idi frame_end"] + #[inline(always)] + pub fn tail_idi_frame_int_raw(&self) -> TAIL_IDI_FRAME_INT_RAW_R { + TAIL_IDI_FRAME_INT_RAW_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - the raw interrupt status of real input frame end of isp_input"] + #[inline(always)] + pub fn header_idi_frame_int_raw(&self) -> HEADER_IDI_FRAME_INT_RAW_R { + HEADER_IDI_FRAME_INT_RAW_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "isp_data_type_err_int_raw", + &format_args!("{}", self.isp_data_type_err_int_raw().bit()), + ) + .field( + "isp_async_fifo_ovf_int_raw", + &format_args!("{}", self.isp_async_fifo_ovf_int_raw().bit()), + ) + .field( + "isp_buf_full_int_raw", + &format_args!("{}", self.isp_buf_full_int_raw().bit()), + ) + .field( + "isp_hvnum_setting_err_int_raw", + &format_args!("{}", self.isp_hvnum_setting_err_int_raw().bit()), + ) + .field( + "isp_data_type_setting_err_int_raw", + &format_args!("{}", self.isp_data_type_setting_err_int_raw().bit()), + ) + .field( + "isp_mipi_hnum_unmatch_int_raw", + &format_args!("{}", self.isp_mipi_hnum_unmatch_int_raw().bit()), + ) + .field( + "dpc_check_done_int_raw", + &format_args!("{}", self.dpc_check_done_int_raw().bit()), + ) + .field( + "gamma_xcoord_err_int_raw", + &format_args!("{}", self.gamma_xcoord_err_int_raw().bit()), + ) + .field( + "ae_monitor_int_raw", + &format_args!("{}", self.ae_monitor_int_raw().bit()), + ) + .field( + "ae_frame_done_int_raw", + &format_args!("{}", self.ae_frame_done_int_raw().bit()), + ) + .field( + "af_fdone_int_raw", + &format_args!("{}", self.af_fdone_int_raw().bit()), + ) + .field( + "af_env_int_raw", + &format_args!("{}", self.af_env_int_raw().bit()), + ) + .field( + "awb_fdone_int_raw", + &format_args!("{}", self.awb_fdone_int_raw().bit()), + ) + .field( + "hist_fdone_int_raw", + &format_args!("{}", self.hist_fdone_int_raw().bit()), + ) + .field( + "frame_int_raw", + &format_args!("{}", self.frame_int_raw().bit()), + ) + .field( + "blc_frame_int_raw", + &format_args!("{}", self.blc_frame_int_raw().bit()), + ) + .field( + "lsc_frame_int_raw", + &format_args!("{}", self.lsc_frame_int_raw().bit()), + ) + .field( + "dpc_frame_int_raw", + &format_args!("{}", self.dpc_frame_int_raw().bit()), + ) + .field( + "bf_frame_int_raw", + &format_args!("{}", self.bf_frame_int_raw().bit()), + ) + .field( + "demosaic_frame_int_raw", + &format_args!("{}", self.demosaic_frame_int_raw().bit()), + ) + .field( + "median_frame_int_raw", + &format_args!("{}", self.median_frame_int_raw().bit()), + ) + .field( + "ccm_frame_int_raw", + &format_args!("{}", self.ccm_frame_int_raw().bit()), + ) + .field( + "gamma_frame_int_raw", + &format_args!("{}", self.gamma_frame_int_raw().bit()), + ) + .field( + "rgb2yuv_frame_int_raw", + &format_args!("{}", self.rgb2yuv_frame_int_raw().bit()), + ) + .field( + "sharp_frame_int_raw", + &format_args!("{}", self.sharp_frame_int_raw().bit()), + ) + .field( + "color_frame_int_raw", + &format_args!("{}", self.color_frame_int_raw().bit()), + ) + .field( + "yuv2rgb_frame_int_raw", + &format_args!("{}", self.yuv2rgb_frame_int_raw().bit()), + ) + .field( + "tail_idi_frame_int_raw", + &format_args!("{}", self.tail_idi_frame_int_raw().bit()), + ) + .field( + "header_idi_frame_int_raw", + &format_args!("{}", self.header_idi_frame_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "raw interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/int_st.rs b/esp32p4/src/isp/int_st.rs new file mode 100644 index 0000000000..57c063fa1a --- /dev/null +++ b/esp32p4/src/isp/int_st.rs @@ -0,0 +1,347 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `ISP_DATA_TYPE_ERR_INT_ST` reader - the masked interrupt status of input data type error"] +pub type ISP_DATA_TYPE_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `ISP_ASYNC_FIFO_OVF_INT_ST` reader - the masked interrupt status of isp input fifo overflow"] +pub type ISP_ASYNC_FIFO_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `ISP_BUF_FULL_INT_ST` reader - the masked interrupt status of isp input buffer full"] +pub type ISP_BUF_FULL_INT_ST_R = crate::BitReader; +#[doc = "Field `ISP_HVNUM_SETTING_ERR_INT_ST` reader - the masked interrupt status of hnum and vnum setting format error"] +pub type ISP_HVNUM_SETTING_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `ISP_DATA_TYPE_SETTING_ERR_INT_ST` reader - the masked interrupt status of setting invalid reg_data_type"] +pub type ISP_DATA_TYPE_SETTING_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `ISP_MIPI_HNUM_UNMATCH_INT_ST` reader - the masked interrupt status of hnum setting unmatch with mipi input"] +pub type ISP_MIPI_HNUM_UNMATCH_INT_ST_R = crate::BitReader; +#[doc = "Field `DPC_CHECK_DONE_INT_ST` reader - the masked interrupt status of dpc check done"] +pub type DPC_CHECK_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `GAMMA_XCOORD_ERR_INT_ST` reader - the masked interrupt status of gamma setting error"] +pub type GAMMA_XCOORD_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `AE_MONITOR_INT_ST` reader - the masked interrupt status of ae monitor"] +pub type AE_MONITOR_INT_ST_R = crate::BitReader; +#[doc = "Field `AE_FRAME_DONE_INT_ST` reader - the masked interrupt status of ae"] +pub type AE_FRAME_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `AF_FDONE_INT_ST` reader - the masked interrupt status of af statistic"] +pub type AF_FDONE_INT_ST_R = crate::BitReader; +#[doc = "Field `AF_ENV_INT_ST` reader - the masked interrupt status of af monitor"] +pub type AF_ENV_INT_ST_R = crate::BitReader; +#[doc = "Field `AWB_FDONE_INT_ST` reader - the masked interrupt status of awb"] +pub type AWB_FDONE_INT_ST_R = crate::BitReader; +#[doc = "Field `HIST_FDONE_INT_ST` reader - the masked interrupt status of histogram"] +pub type HIST_FDONE_INT_ST_R = crate::BitReader; +#[doc = "Field `FRAME_INT_ST` reader - the masked interrupt status of isp frame end"] +pub type FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `BLC_FRAME_INT_ST` reader - the masked interrupt status of blc frame done"] +pub type BLC_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `LSC_FRAME_INT_ST` reader - the masked interrupt status of lsc frame done"] +pub type LSC_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `DPC_FRAME_INT_ST` reader - the masked interrupt status of dpc frame done"] +pub type DPC_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `BF_FRAME_INT_ST` reader - the masked interrupt status of bf frame done"] +pub type BF_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `DEMOSAIC_FRAME_INT_ST` reader - the masked interrupt status of demosaic frame done"] +pub type DEMOSAIC_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `MEDIAN_FRAME_INT_ST` reader - the masked interrupt status of median frame done"] +pub type MEDIAN_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `CCM_FRAME_INT_ST` reader - the masked interrupt status of ccm frame done"] +pub type CCM_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `GAMMA_FRAME_INT_ST` reader - the masked interrupt status of gamma frame done"] +pub type GAMMA_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `RGB2YUV_FRAME_INT_ST` reader - the masked interrupt status of rgb2yuv frame done"] +pub type RGB2YUV_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `SHARP_FRAME_INT_ST` reader - the masked interrupt status of sharp frame done"] +pub type SHARP_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `COLOR_FRAME_INT_ST` reader - the masked interrupt status of color frame done"] +pub type COLOR_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `YUV2RGB_FRAME_INT_ST` reader - the masked interrupt status of yuv2rgb frame done"] +pub type YUV2RGB_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `TAIL_IDI_FRAME_INT_ST` reader - the masked interrupt status of isp_tail idi frame_end"] +pub type TAIL_IDI_FRAME_INT_ST_R = crate::BitReader; +#[doc = "Field `HEADER_IDI_FRAME_INT_ST` reader - the masked interrupt status of real input frame end of isp_input"] +pub type HEADER_IDI_FRAME_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - the masked interrupt status of input data type error"] + #[inline(always)] + pub fn isp_data_type_err_int_st(&self) -> ISP_DATA_TYPE_ERR_INT_ST_R { + ISP_DATA_TYPE_ERR_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - the masked interrupt status of isp input fifo overflow"] + #[inline(always)] + pub fn isp_async_fifo_ovf_int_st(&self) -> ISP_ASYNC_FIFO_OVF_INT_ST_R { + ISP_ASYNC_FIFO_OVF_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - the masked interrupt status of isp input buffer full"] + #[inline(always)] + pub fn isp_buf_full_int_st(&self) -> ISP_BUF_FULL_INT_ST_R { + ISP_BUF_FULL_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - the masked interrupt status of hnum and vnum setting format error"] + #[inline(always)] + pub fn isp_hvnum_setting_err_int_st(&self) -> ISP_HVNUM_SETTING_ERR_INT_ST_R { + ISP_HVNUM_SETTING_ERR_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the masked interrupt status of setting invalid reg_data_type"] + #[inline(always)] + pub fn isp_data_type_setting_err_int_st(&self) -> ISP_DATA_TYPE_SETTING_ERR_INT_ST_R { + ISP_DATA_TYPE_SETTING_ERR_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - the masked interrupt status of hnum setting unmatch with mipi input"] + #[inline(always)] + pub fn isp_mipi_hnum_unmatch_int_st(&self) -> ISP_MIPI_HNUM_UNMATCH_INT_ST_R { + ISP_MIPI_HNUM_UNMATCH_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - the masked interrupt status of dpc check done"] + #[inline(always)] + pub fn dpc_check_done_int_st(&self) -> DPC_CHECK_DONE_INT_ST_R { + DPC_CHECK_DONE_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - the masked interrupt status of gamma setting error"] + #[inline(always)] + pub fn gamma_xcoord_err_int_st(&self) -> GAMMA_XCOORD_ERR_INT_ST_R { + GAMMA_XCOORD_ERR_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - the masked interrupt status of ae monitor"] + #[inline(always)] + pub fn ae_monitor_int_st(&self) -> AE_MONITOR_INT_ST_R { + AE_MONITOR_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - the masked interrupt status of ae"] + #[inline(always)] + pub fn ae_frame_done_int_st(&self) -> AE_FRAME_DONE_INT_ST_R { + AE_FRAME_DONE_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - the masked interrupt status of af statistic"] + #[inline(always)] + pub fn af_fdone_int_st(&self) -> AF_FDONE_INT_ST_R { + AF_FDONE_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - the masked interrupt status of af monitor"] + #[inline(always)] + pub fn af_env_int_st(&self) -> AF_ENV_INT_ST_R { + AF_ENV_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - the masked interrupt status of awb"] + #[inline(always)] + pub fn awb_fdone_int_st(&self) -> AWB_FDONE_INT_ST_R { + AWB_FDONE_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - the masked interrupt status of histogram"] + #[inline(always)] + pub fn hist_fdone_int_st(&self) -> HIST_FDONE_INT_ST_R { + HIST_FDONE_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - the masked interrupt status of isp frame end"] + #[inline(always)] + pub fn frame_int_st(&self) -> FRAME_INT_ST_R { + FRAME_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - the masked interrupt status of blc frame done"] + #[inline(always)] + pub fn blc_frame_int_st(&self) -> BLC_FRAME_INT_ST_R { + BLC_FRAME_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - the masked interrupt status of lsc frame done"] + #[inline(always)] + pub fn lsc_frame_int_st(&self) -> LSC_FRAME_INT_ST_R { + LSC_FRAME_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - the masked interrupt status of dpc frame done"] + #[inline(always)] + pub fn dpc_frame_int_st(&self) -> DPC_FRAME_INT_ST_R { + DPC_FRAME_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - the masked interrupt status of bf frame done"] + #[inline(always)] + pub fn bf_frame_int_st(&self) -> BF_FRAME_INT_ST_R { + BF_FRAME_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - the masked interrupt status of demosaic frame done"] + #[inline(always)] + pub fn demosaic_frame_int_st(&self) -> DEMOSAIC_FRAME_INT_ST_R { + DEMOSAIC_FRAME_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - the masked interrupt status of median frame done"] + #[inline(always)] + pub fn median_frame_int_st(&self) -> MEDIAN_FRAME_INT_ST_R { + MEDIAN_FRAME_INT_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - the masked interrupt status of ccm frame done"] + #[inline(always)] + pub fn ccm_frame_int_st(&self) -> CCM_FRAME_INT_ST_R { + CCM_FRAME_INT_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - the masked interrupt status of gamma frame done"] + #[inline(always)] + pub fn gamma_frame_int_st(&self) -> GAMMA_FRAME_INT_ST_R { + GAMMA_FRAME_INT_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - the masked interrupt status of rgb2yuv frame done"] + #[inline(always)] + pub fn rgb2yuv_frame_int_st(&self) -> RGB2YUV_FRAME_INT_ST_R { + RGB2YUV_FRAME_INT_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - the masked interrupt status of sharp frame done"] + #[inline(always)] + pub fn sharp_frame_int_st(&self) -> SHARP_FRAME_INT_ST_R { + SHARP_FRAME_INT_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - the masked interrupt status of color frame done"] + #[inline(always)] + pub fn color_frame_int_st(&self) -> COLOR_FRAME_INT_ST_R { + COLOR_FRAME_INT_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - the masked interrupt status of yuv2rgb frame done"] + #[inline(always)] + pub fn yuv2rgb_frame_int_st(&self) -> YUV2RGB_FRAME_INT_ST_R { + YUV2RGB_FRAME_INT_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - the masked interrupt status of isp_tail idi frame_end"] + #[inline(always)] + pub fn tail_idi_frame_int_st(&self) -> TAIL_IDI_FRAME_INT_ST_R { + TAIL_IDI_FRAME_INT_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - the masked interrupt status of real input frame end of isp_input"] + #[inline(always)] + pub fn header_idi_frame_int_st(&self) -> HEADER_IDI_FRAME_INT_ST_R { + HEADER_IDI_FRAME_INT_ST_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "isp_data_type_err_int_st", + &format_args!("{}", self.isp_data_type_err_int_st().bit()), + ) + .field( + "isp_async_fifo_ovf_int_st", + &format_args!("{}", self.isp_async_fifo_ovf_int_st().bit()), + ) + .field( + "isp_buf_full_int_st", + &format_args!("{}", self.isp_buf_full_int_st().bit()), + ) + .field( + "isp_hvnum_setting_err_int_st", + &format_args!("{}", self.isp_hvnum_setting_err_int_st().bit()), + ) + .field( + "isp_data_type_setting_err_int_st", + &format_args!("{}", self.isp_data_type_setting_err_int_st().bit()), + ) + .field( + "isp_mipi_hnum_unmatch_int_st", + &format_args!("{}", self.isp_mipi_hnum_unmatch_int_st().bit()), + ) + .field( + "dpc_check_done_int_st", + &format_args!("{}", self.dpc_check_done_int_st().bit()), + ) + .field( + "gamma_xcoord_err_int_st", + &format_args!("{}", self.gamma_xcoord_err_int_st().bit()), + ) + .field( + "ae_monitor_int_st", + &format_args!("{}", self.ae_monitor_int_st().bit()), + ) + .field( + "ae_frame_done_int_st", + &format_args!("{}", self.ae_frame_done_int_st().bit()), + ) + .field( + "af_fdone_int_st", + &format_args!("{}", self.af_fdone_int_st().bit()), + ) + .field( + "af_env_int_st", + &format_args!("{}", self.af_env_int_st().bit()), + ) + .field( + "awb_fdone_int_st", + &format_args!("{}", self.awb_fdone_int_st().bit()), + ) + .field( + "hist_fdone_int_st", + &format_args!("{}", self.hist_fdone_int_st().bit()), + ) + .field( + "frame_int_st", + &format_args!("{}", self.frame_int_st().bit()), + ) + .field( + "blc_frame_int_st", + &format_args!("{}", self.blc_frame_int_st().bit()), + ) + .field( + "lsc_frame_int_st", + &format_args!("{}", self.lsc_frame_int_st().bit()), + ) + .field( + "dpc_frame_int_st", + &format_args!("{}", self.dpc_frame_int_st().bit()), + ) + .field( + "bf_frame_int_st", + &format_args!("{}", self.bf_frame_int_st().bit()), + ) + .field( + "demosaic_frame_int_st", + &format_args!("{}", self.demosaic_frame_int_st().bit()), + ) + .field( + "median_frame_int_st", + &format_args!("{}", self.median_frame_int_st().bit()), + ) + .field( + "ccm_frame_int_st", + &format_args!("{}", self.ccm_frame_int_st().bit()), + ) + .field( + "gamma_frame_int_st", + &format_args!("{}", self.gamma_frame_int_st().bit()), + ) + .field( + "rgb2yuv_frame_int_st", + &format_args!("{}", self.rgb2yuv_frame_int_st().bit()), + ) + .field( + "sharp_frame_int_st", + &format_args!("{}", self.sharp_frame_int_st().bit()), + ) + .field( + "color_frame_int_st", + &format_args!("{}", self.color_frame_int_st().bit()), + ) + .field( + "yuv2rgb_frame_int_st", + &format_args!("{}", self.yuv2rgb_frame_int_st().bit()), + ) + .field( + "tail_idi_frame_int_st", + &format_args!("{}", self.tail_idi_frame_int_st().bit()), + ) + .field( + "header_idi_frame_int_st", + &format_args!("{}", self.header_idi_frame_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/lsc_tablesize.rs b/esp32p4/src/isp/lsc_tablesize.rs new file mode 100644 index 0000000000..30260a6821 --- /dev/null +++ b/esp32p4/src/isp/lsc_tablesize.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LSC_TABLESIZE` reader"] +pub type R = crate::R; +#[doc = "Register `LSC_TABLESIZE` writer"] +pub type W = crate::W; +#[doc = "Field `LSC_XTABLESIZE` reader - this field configures lsc table size in x-direction"] +pub type LSC_XTABLESIZE_R = crate::FieldReader; +#[doc = "Field `LSC_XTABLESIZE` writer - this field configures lsc table size in x-direction"] +pub type LSC_XTABLESIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - this field configures lsc table size in x-direction"] + #[inline(always)] + pub fn lsc_xtablesize(&self) -> LSC_XTABLESIZE_R { + LSC_XTABLESIZE_R::new((self.bits & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LSC_TABLESIZE") + .field( + "lsc_xtablesize", + &format_args!("{}", self.lsc_xtablesize().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - this field configures lsc table size in x-direction"] + #[inline(always)] + #[must_use] + pub fn lsc_xtablesize(&mut self) -> LSC_XTABLESIZE_W { + LSC_XTABLESIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LSC point in x-direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsc_tablesize::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsc_tablesize::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LSC_TABLESIZE_SPEC; +impl crate::RegisterSpec for LSC_TABLESIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lsc_tablesize::R`](R) reader structure"] +impl crate::Readable for LSC_TABLESIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lsc_tablesize::W`](W) writer structure"] +impl crate::Writable for LSC_TABLESIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LSC_TABLESIZE to value 0x1f"] +impl crate::Resettable for LSC_TABLESIZE_SPEC { + const RESET_VALUE: Self::Ux = 0x1f; +} diff --git a/esp32p4/src/isp/lut_cmd.rs b/esp32p4/src/isp/lut_cmd.rs new file mode 100644 index 0000000000..d700c0d1ba --- /dev/null +++ b/esp32p4/src/isp/lut_cmd.rs @@ -0,0 +1,58 @@ +#[doc = "Register `LUT_CMD` writer"] +pub type W = crate::W; +#[doc = "Field `LUT_ADDR` writer - this field configures the lut access addr, when select lsc lut, \\[11:10\\]:00 sel gb_b lut, 01 sel r_gr lut"] +pub type LUT_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `LUT_NUM` writer - this field configures the lut selection. 0000:LSC LUT 0001:DPC LUT"] +pub type LUT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LUT_CMD` writer - this bit configures the access event of lut. 0:rd 1: wr"] +pub type LUT_CMD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:11 - this field configures the lut access addr, when select lsc lut, \\[11:10\\]:00 sel gb_b lut, 01 sel r_gr lut"] + #[inline(always)] + #[must_use] + pub fn lut_addr(&mut self) -> LUT_ADDR_W { + LUT_ADDR_W::new(self, 0) + } + #[doc = "Bits 12:15 - this field configures the lut selection. 0000:LSC LUT 0001:DPC LUT"] + #[inline(always)] + #[must_use] + pub fn lut_num(&mut self) -> LUT_NUM_W { + LUT_NUM_W::new(self, 12) + } + #[doc = "Bit 16 - this bit configures the access event of lut. 0:rd 1: wr"] + #[inline(always)] + #[must_use] + pub fn lut_cmd(&mut self) -> LUT_CMD_W { + LUT_CMD_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LUT command register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lut_cmd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LUT_CMD_SPEC; +impl crate::RegisterSpec for LUT_CMD_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`lut_cmd::W`](W) writer structure"] +impl crate::Writable for LUT_CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LUT_CMD to value 0"] +impl crate::Resettable for LUT_CMD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/lut_rdata.rs b/esp32p4/src/isp/lut_rdata.rs new file mode 100644 index 0000000000..eb7ac0623c --- /dev/null +++ b/esp32p4/src/isp/lut_rdata.rs @@ -0,0 +1,36 @@ +#[doc = "Register `LUT_RDATA` reader"] +pub type R = crate::R; +#[doc = "Field `LUT_RDATA` reader - this field represents the read data of lut. read ISP_LUT_RDATA after write ISP_LUT_CMD register"] +pub type LUT_RDATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - this field represents the read data of lut. read ISP_LUT_RDATA after write ISP_LUT_CMD register"] + #[inline(always)] + pub fn lut_rdata(&self) -> LUT_RDATA_R { + LUT_RDATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LUT_RDATA") + .field("lut_rdata", &format_args!("{}", self.lut_rdata().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "LUT read data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lut_rdata::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LUT_RDATA_SPEC; +impl crate::RegisterSpec for LUT_RDATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lut_rdata::R`](R) reader structure"] +impl crate::Readable for LUT_RDATA_SPEC {} +#[doc = "`reset()` method sets LUT_RDATA to value 0"] +impl crate::Resettable for LUT_RDATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/lut_wdata.rs b/esp32p4/src/isp/lut_wdata.rs new file mode 100644 index 0000000000..16e385f24d --- /dev/null +++ b/esp32p4/src/isp/lut_wdata.rs @@ -0,0 +1,63 @@ +#[doc = "Register `LUT_WDATA` reader"] +pub type R = crate::R; +#[doc = "Register `LUT_WDATA` writer"] +pub type W = crate::W; +#[doc = "Field `LUT_WDATA` reader - this field configures the write data of lut. please initial ISP_LUT_WDATA before write ISP_LUT_CMD register"] +pub type LUT_WDATA_R = crate::FieldReader; +#[doc = "Field `LUT_WDATA` writer - this field configures the write data of lut. please initial ISP_LUT_WDATA before write ISP_LUT_CMD register"] +pub type LUT_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - this field configures the write data of lut. please initial ISP_LUT_WDATA before write ISP_LUT_CMD register"] + #[inline(always)] + pub fn lut_wdata(&self) -> LUT_WDATA_R { + LUT_WDATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LUT_WDATA") + .field("lut_wdata", &format_args!("{}", self.lut_wdata().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - this field configures the write data of lut. please initial ISP_LUT_WDATA before write ISP_LUT_CMD register"] + #[inline(always)] + #[must_use] + pub fn lut_wdata(&mut self) -> LUT_WDATA_W { + LUT_WDATA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LUT write data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lut_wdata::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lut_wdata::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LUT_WDATA_SPEC; +impl crate::RegisterSpec for LUT_WDATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lut_wdata::R`](R) reader structure"] +impl crate::Readable for LUT_WDATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lut_wdata::W`](W) writer structure"] +impl crate::Writable for LUT_WDATA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LUT_WDATA to value 0"] +impl crate::Resettable for LUT_WDATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/median_matrix_ctrl.rs b/esp32p4/src/isp/median_matrix_ctrl.rs new file mode 100644 index 0000000000..46f63b484a --- /dev/null +++ b/esp32p4/src/isp/median_matrix_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `MEDIAN_MATRIX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MEDIAN_MATRIX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `MEDIAN_PADDING_DATA` reader - this field configures median matrix padding data"] +pub type MEDIAN_PADDING_DATA_R = crate::FieldReader; +#[doc = "Field `MEDIAN_PADDING_DATA` writer - this field configures median matrix padding data"] +pub type MEDIAN_PADDING_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `MEDIAN_PADDING_MODE` reader - this bit configures the padding mode of median matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] +pub type MEDIAN_PADDING_MODE_R = crate::BitReader; +#[doc = "Field `MEDIAN_PADDING_MODE` writer - this bit configures the padding mode of median matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] +pub type MEDIAN_PADDING_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - this field configures median matrix padding data"] + #[inline(always)] + pub fn median_padding_data(&self) -> MEDIAN_PADDING_DATA_R { + MEDIAN_PADDING_DATA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - this bit configures the padding mode of median matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] + #[inline(always)] + pub fn median_padding_mode(&self) -> MEDIAN_PADDING_MODE_R { + MEDIAN_PADDING_MODE_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEDIAN_MATRIX_CTRL") + .field( + "median_padding_data", + &format_args!("{}", self.median_padding_data().bits()), + ) + .field( + "median_padding_mode", + &format_args!("{}", self.median_padding_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures median matrix padding data"] + #[inline(always)] + #[must_use] + pub fn median_padding_data(&mut self) -> MEDIAN_PADDING_DATA_W { + MEDIAN_PADDING_DATA_W::new(self, 0) + } + #[doc = "Bit 8 - this bit configures the padding mode of median matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding"] + #[inline(always)] + #[must_use] + pub fn median_padding_mode(&mut self) -> MEDIAN_PADDING_MODE_W { + MEDIAN_PADDING_MODE_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "median pix2matrix ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`median_matrix_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`median_matrix_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEDIAN_MATRIX_CTRL_SPEC; +impl crate::RegisterSpec for MEDIAN_MATRIX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`median_matrix_ctrl::R`](R) reader structure"] +impl crate::Readable for MEDIAN_MATRIX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`median_matrix_ctrl::W`](W) writer structure"] +impl crate::Writable for MEDIAN_MATRIX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEDIAN_MATRIX_CTRL to value 0"] +impl crate::Resettable for MEDIAN_MATRIX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/mem_aux_ctrl_0.rs b/esp32p4/src/isp/mem_aux_ctrl_0.rs new file mode 100644 index 0000000000..b375e2d3b4 --- /dev/null +++ b/esp32p4/src/isp/mem_aux_ctrl_0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `MEM_AUX_CTRL_0` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_AUX_CTRL_0` writer"] +pub type W = crate::W; +#[doc = "Field `HEADER_MEM_AUX_CTRL` reader - this field configures the mem_aux of isp input buffer memory"] +pub type HEADER_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `HEADER_MEM_AUX_CTRL` writer - this field configures the mem_aux of isp input buffer memory"] +pub type HEADER_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `DPC_LUT_MEM_AUX_CTRL` reader - this field represents this field configures the mem_aux of dpc lut memory"] +pub type DPC_LUT_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `DPC_LUT_MEM_AUX_CTRL` writer - this field represents this field configures the mem_aux of dpc lut memory"] +pub type DPC_LUT_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - this field configures the mem_aux of isp input buffer memory"] + #[inline(always)] + pub fn header_mem_aux_ctrl(&self) -> HEADER_MEM_AUX_CTRL_R { + HEADER_MEM_AUX_CTRL_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - this field represents this field configures the mem_aux of dpc lut memory"] + #[inline(always)] + pub fn dpc_lut_mem_aux_ctrl(&self) -> DPC_LUT_MEM_AUX_CTRL_R { + DPC_LUT_MEM_AUX_CTRL_R::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_AUX_CTRL_0") + .field( + "header_mem_aux_ctrl", + &format_args!("{}", self.header_mem_aux_ctrl().bits()), + ) + .field( + "dpc_lut_mem_aux_ctrl", + &format_args!("{}", self.dpc_lut_mem_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - this field configures the mem_aux of isp input buffer memory"] + #[inline(always)] + #[must_use] + pub fn header_mem_aux_ctrl(&mut self) -> HEADER_MEM_AUX_CTRL_W { + HEADER_MEM_AUX_CTRL_W::new(self, 0) + } + #[doc = "Bits 16:29 - this field represents this field configures the mem_aux of dpc lut memory"] + #[inline(always)] + #[must_use] + pub fn dpc_lut_mem_aux_ctrl(&mut self) -> DPC_LUT_MEM_AUX_CTRL_W { + DPC_LUT_MEM_AUX_CTRL_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "mem aux control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_AUX_CTRL_0_SPEC; +impl crate::RegisterSpec for MEM_AUX_CTRL_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_aux_ctrl_0::R`](R) reader structure"] +impl crate::Readable for MEM_AUX_CTRL_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_aux_ctrl_0::W`](W) writer structure"] +impl crate::Writable for MEM_AUX_CTRL_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_AUX_CTRL_0 to value 0x1320_1320"] +impl crate::Resettable for MEM_AUX_CTRL_0_SPEC { + const RESET_VALUE: Self::Ux = 0x1320_1320; +} diff --git a/esp32p4/src/isp/mem_aux_ctrl_1.rs b/esp32p4/src/isp/mem_aux_ctrl_1.rs new file mode 100644 index 0000000000..a9d274b025 --- /dev/null +++ b/esp32p4/src/isp/mem_aux_ctrl_1.rs @@ -0,0 +1,89 @@ +#[doc = "Register `MEM_AUX_CTRL_1` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_AUX_CTRL_1` writer"] +pub type W = crate::W; +#[doc = "Field `LSC_LUT_R_GR_MEM_AUX_CTRL` reader - this field configures the mem_aux of lsc r gr lut memory"] +pub type LSC_LUT_R_GR_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `LSC_LUT_R_GR_MEM_AUX_CTRL` writer - this field configures the mem_aux of lsc r gr lut memory"] +pub type LSC_LUT_R_GR_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `LSC_LUT_GB_B_MEM_AUX_CTRL` reader - this field configures the mem_aux of lsc gb b lut memory"] +pub type LSC_LUT_GB_B_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `LSC_LUT_GB_B_MEM_AUX_CTRL` writer - this field configures the mem_aux of lsc gb b lut memory"] +pub type LSC_LUT_GB_B_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - this field configures the mem_aux of lsc r gr lut memory"] + #[inline(always)] + pub fn lsc_lut_r_gr_mem_aux_ctrl(&self) -> LSC_LUT_R_GR_MEM_AUX_CTRL_R { + LSC_LUT_R_GR_MEM_AUX_CTRL_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - this field configures the mem_aux of lsc gb b lut memory"] + #[inline(always)] + pub fn lsc_lut_gb_b_mem_aux_ctrl(&self) -> LSC_LUT_GB_B_MEM_AUX_CTRL_R { + LSC_LUT_GB_B_MEM_AUX_CTRL_R::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_AUX_CTRL_1") + .field( + "lsc_lut_r_gr_mem_aux_ctrl", + &format_args!("{}", self.lsc_lut_r_gr_mem_aux_ctrl().bits()), + ) + .field( + "lsc_lut_gb_b_mem_aux_ctrl", + &format_args!("{}", self.lsc_lut_gb_b_mem_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - this field configures the mem_aux of lsc r gr lut memory"] + #[inline(always)] + #[must_use] + pub fn lsc_lut_r_gr_mem_aux_ctrl( + &mut self, + ) -> LSC_LUT_R_GR_MEM_AUX_CTRL_W { + LSC_LUT_R_GR_MEM_AUX_CTRL_W::new(self, 0) + } + #[doc = "Bits 16:29 - this field configures the mem_aux of lsc gb b lut memory"] + #[inline(always)] + #[must_use] + pub fn lsc_lut_gb_b_mem_aux_ctrl( + &mut self, + ) -> LSC_LUT_GB_B_MEM_AUX_CTRL_W { + LSC_LUT_GB_B_MEM_AUX_CTRL_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "mem aux control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_AUX_CTRL_1_SPEC; +impl crate::RegisterSpec for MEM_AUX_CTRL_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_aux_ctrl_1::R`](R) reader structure"] +impl crate::Readable for MEM_AUX_CTRL_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_aux_ctrl_1::W`](W) writer structure"] +impl crate::Writable for MEM_AUX_CTRL_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_AUX_CTRL_1 to value 0x1320_1320"] +impl crate::Resettable for MEM_AUX_CTRL_1_SPEC { + const RESET_VALUE: Self::Ux = 0x1320_1320; +} diff --git a/esp32p4/src/isp/mem_aux_ctrl_2.rs b/esp32p4/src/isp/mem_aux_ctrl_2.rs new file mode 100644 index 0000000000..554c6cb368 --- /dev/null +++ b/esp32p4/src/isp/mem_aux_ctrl_2.rs @@ -0,0 +1,85 @@ +#[doc = "Register `MEM_AUX_CTRL_2` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_AUX_CTRL_2` writer"] +pub type W = crate::W; +#[doc = "Field `BF_MATRIX_MEM_AUX_CTRL` reader - this field configures the mem_aux of bf line buffer memory"] +pub type BF_MATRIX_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `BF_MATRIX_MEM_AUX_CTRL` writer - this field configures the mem_aux of bf line buffer memory"] +pub type BF_MATRIX_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `DPC_MATRIX_MEM_AUX_CTRL` reader - this field configures the mem_aux of dpc line buffer memory"] +pub type DPC_MATRIX_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `DPC_MATRIX_MEM_AUX_CTRL` writer - this field configures the mem_aux of dpc line buffer memory"] +pub type DPC_MATRIX_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - this field configures the mem_aux of bf line buffer memory"] + #[inline(always)] + pub fn bf_matrix_mem_aux_ctrl(&self) -> BF_MATRIX_MEM_AUX_CTRL_R { + BF_MATRIX_MEM_AUX_CTRL_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - this field configures the mem_aux of dpc line buffer memory"] + #[inline(always)] + pub fn dpc_matrix_mem_aux_ctrl(&self) -> DPC_MATRIX_MEM_AUX_CTRL_R { + DPC_MATRIX_MEM_AUX_CTRL_R::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_AUX_CTRL_2") + .field( + "bf_matrix_mem_aux_ctrl", + &format_args!("{}", self.bf_matrix_mem_aux_ctrl().bits()), + ) + .field( + "dpc_matrix_mem_aux_ctrl", + &format_args!("{}", self.dpc_matrix_mem_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - this field configures the mem_aux of bf line buffer memory"] + #[inline(always)] + #[must_use] + pub fn bf_matrix_mem_aux_ctrl(&mut self) -> BF_MATRIX_MEM_AUX_CTRL_W { + BF_MATRIX_MEM_AUX_CTRL_W::new(self, 0) + } + #[doc = "Bits 16:29 - this field configures the mem_aux of dpc line buffer memory"] + #[inline(always)] + #[must_use] + pub fn dpc_matrix_mem_aux_ctrl(&mut self) -> DPC_MATRIX_MEM_AUX_CTRL_W { + DPC_MATRIX_MEM_AUX_CTRL_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "mem aux control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_AUX_CTRL_2_SPEC; +impl crate::RegisterSpec for MEM_AUX_CTRL_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_aux_ctrl_2::R`](R) reader structure"] +impl crate::Readable for MEM_AUX_CTRL_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_aux_ctrl_2::W`](W) writer structure"] +impl crate::Writable for MEM_AUX_CTRL_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_AUX_CTRL_2 to value 0x1320_1320"] +impl crate::Resettable for MEM_AUX_CTRL_2_SPEC { + const RESET_VALUE: Self::Ux = 0x1320_1320; +} diff --git a/esp32p4/src/isp/mem_aux_ctrl_3.rs b/esp32p4/src/isp/mem_aux_ctrl_3.rs new file mode 100644 index 0000000000..c15eead014 --- /dev/null +++ b/esp32p4/src/isp/mem_aux_ctrl_3.rs @@ -0,0 +1,89 @@ +#[doc = "Register `MEM_AUX_CTRL_3` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_AUX_CTRL_3` writer"] +pub type W = crate::W; +#[doc = "Field `SHARP_MATRIX_Y_MEM_AUX_CTRL` reader - this field configures the mem_aux of sharp y line buffer memory"] +pub type SHARP_MATRIX_Y_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `SHARP_MATRIX_Y_MEM_AUX_CTRL` writer - this field configures the mem_aux of sharp y line buffer memory"] +pub type SHARP_MATRIX_Y_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `DEMOSAIC_MATRIX_MEM_AUX_CTRL` reader - this field configures the mem_aux of demosaic line buffer memory"] +pub type DEMOSAIC_MATRIX_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `DEMOSAIC_MATRIX_MEM_AUX_CTRL` writer - this field configures the mem_aux of demosaic line buffer memory"] +pub type DEMOSAIC_MATRIX_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - this field configures the mem_aux of sharp y line buffer memory"] + #[inline(always)] + pub fn sharp_matrix_y_mem_aux_ctrl(&self) -> SHARP_MATRIX_Y_MEM_AUX_CTRL_R { + SHARP_MATRIX_Y_MEM_AUX_CTRL_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - this field configures the mem_aux of demosaic line buffer memory"] + #[inline(always)] + pub fn demosaic_matrix_mem_aux_ctrl(&self) -> DEMOSAIC_MATRIX_MEM_AUX_CTRL_R { + DEMOSAIC_MATRIX_MEM_AUX_CTRL_R::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_AUX_CTRL_3") + .field( + "sharp_matrix_y_mem_aux_ctrl", + &format_args!("{}", self.sharp_matrix_y_mem_aux_ctrl().bits()), + ) + .field( + "demosaic_matrix_mem_aux_ctrl", + &format_args!("{}", self.demosaic_matrix_mem_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - this field configures the mem_aux of sharp y line buffer memory"] + #[inline(always)] + #[must_use] + pub fn sharp_matrix_y_mem_aux_ctrl( + &mut self, + ) -> SHARP_MATRIX_Y_MEM_AUX_CTRL_W { + SHARP_MATRIX_Y_MEM_AUX_CTRL_W::new(self, 0) + } + #[doc = "Bits 16:29 - this field configures the mem_aux of demosaic line buffer memory"] + #[inline(always)] + #[must_use] + pub fn demosaic_matrix_mem_aux_ctrl( + &mut self, + ) -> DEMOSAIC_MATRIX_MEM_AUX_CTRL_W { + DEMOSAIC_MATRIX_MEM_AUX_CTRL_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "mem aux control register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_AUX_CTRL_3_SPEC; +impl crate::RegisterSpec for MEM_AUX_CTRL_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_aux_ctrl_3::R`](R) reader structure"] +impl crate::Readable for MEM_AUX_CTRL_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_aux_ctrl_3::W`](W) writer structure"] +impl crate::Writable for MEM_AUX_CTRL_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_AUX_CTRL_3 to value 0x1320_1320"] +impl crate::Resettable for MEM_AUX_CTRL_3_SPEC { + const RESET_VALUE: Self::Ux = 0x1320_1320; +} diff --git a/esp32p4/src/isp/mem_aux_ctrl_4.rs b/esp32p4/src/isp/mem_aux_ctrl_4.rs new file mode 100644 index 0000000000..c5936584c3 --- /dev/null +++ b/esp32p4/src/isp/mem_aux_ctrl_4.rs @@ -0,0 +1,68 @@ +#[doc = "Register `MEM_AUX_CTRL_4` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_AUX_CTRL_4` writer"] +pub type W = crate::W; +#[doc = "Field `SHARP_MATRIX_UV_MEM_AUX_CTRL` reader - this field configures the mem_aux of sharp uv line buffer memory"] +pub type SHARP_MATRIX_UV_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `SHARP_MATRIX_UV_MEM_AUX_CTRL` writer - this field configures the mem_aux of sharp uv line buffer memory"] +pub type SHARP_MATRIX_UV_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - this field configures the mem_aux of sharp uv line buffer memory"] + #[inline(always)] + pub fn sharp_matrix_uv_mem_aux_ctrl(&self) -> SHARP_MATRIX_UV_MEM_AUX_CTRL_R { + SHARP_MATRIX_UV_MEM_AUX_CTRL_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_AUX_CTRL_4") + .field( + "sharp_matrix_uv_mem_aux_ctrl", + &format_args!("{}", self.sharp_matrix_uv_mem_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - this field configures the mem_aux of sharp uv line buffer memory"] + #[inline(always)] + #[must_use] + pub fn sharp_matrix_uv_mem_aux_ctrl( + &mut self, + ) -> SHARP_MATRIX_UV_MEM_AUX_CTRL_W { + SHARP_MATRIX_UV_MEM_AUX_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "mem aux control register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_AUX_CTRL_4_SPEC; +impl crate::RegisterSpec for MEM_AUX_CTRL_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_aux_ctrl_4::R`](R) reader structure"] +impl crate::Readable for MEM_AUX_CTRL_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_aux_ctrl_4::W`](W) writer structure"] +impl crate::Writable for MEM_AUX_CTRL_4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_AUX_CTRL_4 to value 0x1320"] +impl crate::Resettable for MEM_AUX_CTRL_4_SPEC { + const RESET_VALUE: Self::Ux = 0x1320; +} diff --git a/esp32p4/src/isp/rdn_eco_cs.rs b/esp32p4/src/isp/rdn_eco_cs.rs new file mode 100644 index 0000000000..8553d8237f --- /dev/null +++ b/esp32p4/src/isp/rdn_eco_cs.rs @@ -0,0 +1,74 @@ +#[doc = "Register `RDN_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_EN` reader - rdn_eco_en"] +pub type RDN_ECO_EN_R = crate::BitReader; +#[doc = "Field `RDN_ECO_EN` writer - rdn_eco_en"] +pub type RDN_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RDN_ECO_RESULT` reader - rdn_eco_result"] +pub type RDN_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - rdn_eco_en"] + #[inline(always)] + pub fn rdn_eco_en(&self) -> RDN_ECO_EN_R { + RDN_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - rdn_eco_result"] + #[inline(always)] + pub fn rdn_eco_result(&self) -> RDN_ECO_RESULT_R { + RDN_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_CS") + .field("rdn_eco_en", &format_args!("{}", self.rdn_eco_en().bit())) + .field( + "rdn_eco_result", + &format_args!("{}", self.rdn_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - rdn_eco_en"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_en(&mut self) -> RDN_ECO_EN_W { + RDN_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "rdn eco cs register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_CS_SPEC; +impl crate::RegisterSpec for RDN_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_cs::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_cs::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_CS to value 0"] +impl crate::Resettable for RDN_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/rdn_eco_high.rs b/esp32p4/src/isp/rdn_eco_high.rs new file mode 100644 index 0000000000..00ccc1b0a4 --- /dev/null +++ b/esp32p4/src/isp/rdn_eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RDN_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_HIGH` reader - rdn_eco_high"] +pub type RDN_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_HIGH` writer - rdn_eco_high"] +pub type RDN_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - rdn_eco_high"] + #[inline(always)] + pub fn rdn_eco_high(&self) -> RDN_ECO_HIGH_R { + RDN_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_HIGH") + .field( + "rdn_eco_high", + &format_args!("{}", self.rdn_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - rdn_eco_high"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_high(&mut self) -> RDN_ECO_HIGH_W { + RDN_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "rdn eco all high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_HIGH_SPEC; +impl crate::RegisterSpec for RDN_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_high::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_high::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for RDN_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/isp/rdn_eco_low.rs b/esp32p4/src/isp/rdn_eco_low.rs new file mode 100644 index 0000000000..7aa151d1e8 --- /dev/null +++ b/esp32p4/src/isp/rdn_eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RDN_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_LOW` reader - rdn_eco_low"] +pub type RDN_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_LOW` writer - rdn_eco_low"] +pub type RDN_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - rdn_eco_low"] + #[inline(always)] + pub fn rdn_eco_low(&self) -> RDN_ECO_LOW_R { + RDN_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_LOW") + .field( + "rdn_eco_low", + &format_args!("{}", self.rdn_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - rdn_eco_low"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_low(&mut self) -> RDN_ECO_LOW_W { + RDN_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "rdn eco all low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_LOW_SPEC; +impl crate::RegisterSpec for RDN_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_low::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_low::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_LOW to value 0"] +impl crate::Resettable for RDN_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/sharp_ctrl0.rs b/esp32p4/src/isp/sharp_ctrl0.rs new file mode 100644 index 0000000000..1847699f7e --- /dev/null +++ b/esp32p4/src/isp/sharp_ctrl0.rs @@ -0,0 +1,123 @@ +#[doc = "Register `SHARP_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `SHARP_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `SHARP_THRESHOLD_LOW` reader - this field configures sharpen threshold for detail"] +pub type SHARP_THRESHOLD_LOW_R = crate::FieldReader; +#[doc = "Field `SHARP_THRESHOLD_LOW` writer - this field configures sharpen threshold for detail"] +pub type SHARP_THRESHOLD_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SHARP_THRESHOLD_HIGH` reader - this field configures sharpen threshold for edge"] +pub type SHARP_THRESHOLD_HIGH_R = crate::FieldReader; +#[doc = "Field `SHARP_THRESHOLD_HIGH` writer - this field configures sharpen threshold for edge"] +pub type SHARP_THRESHOLD_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SHARP_AMOUNT_LOW` reader - this field configures sharpen amount for detail"] +pub type SHARP_AMOUNT_LOW_R = crate::FieldReader; +#[doc = "Field `SHARP_AMOUNT_LOW` writer - this field configures sharpen amount for detail"] +pub type SHARP_AMOUNT_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SHARP_AMOUNT_HIGH` reader - this field configures sharpen amount for edge"] +pub type SHARP_AMOUNT_HIGH_R = crate::FieldReader; +#[doc = "Field `SHARP_AMOUNT_HIGH` writer - this field configures sharpen amount for edge"] +pub type SHARP_AMOUNT_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - this field configures sharpen threshold for detail"] + #[inline(always)] + pub fn sharp_threshold_low(&self) -> SHARP_THRESHOLD_LOW_R { + SHARP_THRESHOLD_LOW_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - this field configures sharpen threshold for edge"] + #[inline(always)] + pub fn sharp_threshold_high(&self) -> SHARP_THRESHOLD_HIGH_R { + SHARP_THRESHOLD_HIGH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures sharpen amount for detail"] + #[inline(always)] + pub fn sharp_amount_low(&self) -> SHARP_AMOUNT_LOW_R { + SHARP_AMOUNT_LOW_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - this field configures sharpen amount for edge"] + #[inline(always)] + pub fn sharp_amount_high(&self) -> SHARP_AMOUNT_HIGH_R { + SHARP_AMOUNT_HIGH_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHARP_CTRL0") + .field( + "sharp_threshold_low", + &format_args!("{}", self.sharp_threshold_low().bits()), + ) + .field( + "sharp_threshold_high", + &format_args!("{}", self.sharp_threshold_high().bits()), + ) + .field( + "sharp_amount_low", + &format_args!("{}", self.sharp_amount_low().bits()), + ) + .field( + "sharp_amount_high", + &format_args!("{}", self.sharp_amount_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - this field configures sharpen threshold for detail"] + #[inline(always)] + #[must_use] + pub fn sharp_threshold_low(&mut self) -> SHARP_THRESHOLD_LOW_W { + SHARP_THRESHOLD_LOW_W::new(self, 0) + } + #[doc = "Bits 8:15 - this field configures sharpen threshold for edge"] + #[inline(always)] + #[must_use] + pub fn sharp_threshold_high(&mut self) -> SHARP_THRESHOLD_HIGH_W { + SHARP_THRESHOLD_HIGH_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures sharpen amount for detail"] + #[inline(always)] + #[must_use] + pub fn sharp_amount_low(&mut self) -> SHARP_AMOUNT_LOW_W { + SHARP_AMOUNT_LOW_W::new(self, 16) + } + #[doc = "Bits 24:31 - this field configures sharpen amount for edge"] + #[inline(always)] + #[must_use] + pub fn sharp_amount_high(&mut self) -> SHARP_AMOUNT_HIGH_W { + SHARP_AMOUNT_HIGH_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "sharp control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sharp_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHARP_CTRL0_SPEC; +impl crate::RegisterSpec for SHARP_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sharp_ctrl0::R`](R) reader structure"] +impl crate::Readable for SHARP_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sharp_ctrl0::W`](W) writer structure"] +impl crate::Writable for SHARP_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SHARP_CTRL0 to value 0"] +impl crate::Resettable for SHARP_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/sharp_ctrl1.rs b/esp32p4/src/isp/sharp_ctrl1.rs new file mode 100644 index 0000000000..9572b17b09 --- /dev/null +++ b/esp32p4/src/isp/sharp_ctrl1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SHARP_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Field `SHARP_GRADIENT_MAX` reader - this field configures sharp max gradient, refresh at the end of each frame end"] +pub type SHARP_GRADIENT_MAX_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - this field configures sharp max gradient, refresh at the end of each frame end"] + #[inline(always)] + pub fn sharp_gradient_max(&self) -> SHARP_GRADIENT_MAX_R { + SHARP_GRADIENT_MAX_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHARP_CTRL1") + .field( + "sharp_gradient_max", + &format_args!("{}", self.sharp_gradient_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "sharp control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_ctrl1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHARP_CTRL1_SPEC; +impl crate::RegisterSpec for SHARP_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sharp_ctrl1::R`](R) reader structure"] +impl crate::Readable for SHARP_CTRL1_SPEC {} +#[doc = "`reset()` method sets SHARP_CTRL1 to value 0"] +impl crate::Resettable for SHARP_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/sharp_filter0.rs b/esp32p4/src/isp/sharp_filter0.rs new file mode 100644 index 0000000000..14a5d9fafa --- /dev/null +++ b/esp32p4/src/isp/sharp_filter0.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SHARP_FILTER0` reader"] +pub type R = crate::R; +#[doc = "Register `SHARP_FILTER0` writer"] +pub type W = crate::W; +#[doc = "Field `SHARP_FILTER_COE00` reader - this field configures unsharp masking(usm) filter coefficient"] +pub type SHARP_FILTER_COE00_R = crate::FieldReader; +#[doc = "Field `SHARP_FILTER_COE00` writer - this field configures unsharp masking(usm) filter coefficient"] +pub type SHARP_FILTER_COE00_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SHARP_FILTER_COE01` reader - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE01_R = crate::FieldReader; +#[doc = "Field `SHARP_FILTER_COE01` writer - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE01_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SHARP_FILTER_COE02` reader - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE02_R = crate::FieldReader; +#[doc = "Field `SHARP_FILTER_COE02` writer - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE02_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - this field configures unsharp masking(usm) filter coefficient"] + #[inline(always)] + pub fn sharp_filter_coe00(&self) -> SHARP_FILTER_COE00_R { + SHARP_FILTER_COE00_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - this field configures usm filter coefficient"] + #[inline(always)] + pub fn sharp_filter_coe01(&self) -> SHARP_FILTER_COE01_R { + SHARP_FILTER_COE01_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - this field configures usm filter coefficient"] + #[inline(always)] + pub fn sharp_filter_coe02(&self) -> SHARP_FILTER_COE02_R { + SHARP_FILTER_COE02_R::new(((self.bits >> 10) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHARP_FILTER0") + .field( + "sharp_filter_coe00", + &format_args!("{}", self.sharp_filter_coe00().bits()), + ) + .field( + "sharp_filter_coe01", + &format_args!("{}", self.sharp_filter_coe01().bits()), + ) + .field( + "sharp_filter_coe02", + &format_args!("{}", self.sharp_filter_coe02().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - this field configures unsharp masking(usm) filter coefficient"] + #[inline(always)] + #[must_use] + pub fn sharp_filter_coe00(&mut self) -> SHARP_FILTER_COE00_W { + SHARP_FILTER_COE00_W::new(self, 0) + } + #[doc = "Bits 5:9 - this field configures usm filter coefficient"] + #[inline(always)] + #[must_use] + pub fn sharp_filter_coe01(&mut self) -> SHARP_FILTER_COE01_W { + SHARP_FILTER_COE01_W::new(self, 5) + } + #[doc = "Bits 10:14 - this field configures usm filter coefficient"] + #[inline(always)] + #[must_use] + pub fn sharp_filter_coe02(&mut self) -> SHARP_FILTER_COE02_W { + SHARP_FILTER_COE02_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "sharp usm config register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_filter0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sharp_filter0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHARP_FILTER0_SPEC; +impl crate::RegisterSpec for SHARP_FILTER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sharp_filter0::R`](R) reader structure"] +impl crate::Readable for SHARP_FILTER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sharp_filter0::W`](W) writer structure"] +impl crate::Writable for SHARP_FILTER0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SHARP_FILTER0 to value 0x0441"] +impl crate::Resettable for SHARP_FILTER0_SPEC { + const RESET_VALUE: Self::Ux = 0x0441; +} diff --git a/esp32p4/src/isp/sharp_filter1.rs b/esp32p4/src/isp/sharp_filter1.rs new file mode 100644 index 0000000000..9b7ca45fe1 --- /dev/null +++ b/esp32p4/src/isp/sharp_filter1.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SHARP_FILTER1` reader"] +pub type R = crate::R; +#[doc = "Register `SHARP_FILTER1` writer"] +pub type W = crate::W; +#[doc = "Field `SHARP_FILTER_COE10` reader - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE10_R = crate::FieldReader; +#[doc = "Field `SHARP_FILTER_COE10` writer - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE10_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SHARP_FILTER_COE11` reader - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE11_R = crate::FieldReader; +#[doc = "Field `SHARP_FILTER_COE11` writer - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE11_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SHARP_FILTER_COE12` reader - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE12_R = crate::FieldReader; +#[doc = "Field `SHARP_FILTER_COE12` writer - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE12_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - this field configures usm filter coefficient"] + #[inline(always)] + pub fn sharp_filter_coe10(&self) -> SHARP_FILTER_COE10_R { + SHARP_FILTER_COE10_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - this field configures usm filter coefficient"] + #[inline(always)] + pub fn sharp_filter_coe11(&self) -> SHARP_FILTER_COE11_R { + SHARP_FILTER_COE11_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - this field configures usm filter coefficient"] + #[inline(always)] + pub fn sharp_filter_coe12(&self) -> SHARP_FILTER_COE12_R { + SHARP_FILTER_COE12_R::new(((self.bits >> 10) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHARP_FILTER1") + .field( + "sharp_filter_coe10", + &format_args!("{}", self.sharp_filter_coe10().bits()), + ) + .field( + "sharp_filter_coe11", + &format_args!("{}", self.sharp_filter_coe11().bits()), + ) + .field( + "sharp_filter_coe12", + &format_args!("{}", self.sharp_filter_coe12().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - this field configures usm filter coefficient"] + #[inline(always)] + #[must_use] + pub fn sharp_filter_coe10(&mut self) -> SHARP_FILTER_COE10_W { + SHARP_FILTER_COE10_W::new(self, 0) + } + #[doc = "Bits 5:9 - this field configures usm filter coefficient"] + #[inline(always)] + #[must_use] + pub fn sharp_filter_coe11(&mut self) -> SHARP_FILTER_COE11_W { + SHARP_FILTER_COE11_W::new(self, 5) + } + #[doc = "Bits 10:14 - this field configures usm filter coefficient"] + #[inline(always)] + #[must_use] + pub fn sharp_filter_coe12(&mut self) -> SHARP_FILTER_COE12_W { + SHARP_FILTER_COE12_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "sharp usm config register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_filter1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sharp_filter1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHARP_FILTER1_SPEC; +impl crate::RegisterSpec for SHARP_FILTER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sharp_filter1::R`](R) reader structure"] +impl crate::Readable for SHARP_FILTER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sharp_filter1::W`](W) writer structure"] +impl crate::Writable for SHARP_FILTER1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SHARP_FILTER1 to value 0x0882"] +impl crate::Resettable for SHARP_FILTER1_SPEC { + const RESET_VALUE: Self::Ux = 0x0882; +} diff --git a/esp32p4/src/isp/sharp_filter2.rs b/esp32p4/src/isp/sharp_filter2.rs new file mode 100644 index 0000000000..1fd7044b9e --- /dev/null +++ b/esp32p4/src/isp/sharp_filter2.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SHARP_FILTER2` reader"] +pub type R = crate::R; +#[doc = "Register `SHARP_FILTER2` writer"] +pub type W = crate::W; +#[doc = "Field `SHARP_FILTER_COE20` reader - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE20_R = crate::FieldReader; +#[doc = "Field `SHARP_FILTER_COE20` writer - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE20_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SHARP_FILTER_COE21` reader - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE21_R = crate::FieldReader; +#[doc = "Field `SHARP_FILTER_COE21` writer - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE21_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SHARP_FILTER_COE22` reader - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE22_R = crate::FieldReader; +#[doc = "Field `SHARP_FILTER_COE22` writer - this field configures usm filter coefficient"] +pub type SHARP_FILTER_COE22_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - this field configures usm filter coefficient"] + #[inline(always)] + pub fn sharp_filter_coe20(&self) -> SHARP_FILTER_COE20_R { + SHARP_FILTER_COE20_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - this field configures usm filter coefficient"] + #[inline(always)] + pub fn sharp_filter_coe21(&self) -> SHARP_FILTER_COE21_R { + SHARP_FILTER_COE21_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - this field configures usm filter coefficient"] + #[inline(always)] + pub fn sharp_filter_coe22(&self) -> SHARP_FILTER_COE22_R { + SHARP_FILTER_COE22_R::new(((self.bits >> 10) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHARP_FILTER2") + .field( + "sharp_filter_coe20", + &format_args!("{}", self.sharp_filter_coe20().bits()), + ) + .field( + "sharp_filter_coe21", + &format_args!("{}", self.sharp_filter_coe21().bits()), + ) + .field( + "sharp_filter_coe22", + &format_args!("{}", self.sharp_filter_coe22().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - this field configures usm filter coefficient"] + #[inline(always)] + #[must_use] + pub fn sharp_filter_coe20(&mut self) -> SHARP_FILTER_COE20_W { + SHARP_FILTER_COE20_W::new(self, 0) + } + #[doc = "Bits 5:9 - this field configures usm filter coefficient"] + #[inline(always)] + #[must_use] + pub fn sharp_filter_coe21(&mut self) -> SHARP_FILTER_COE21_W { + SHARP_FILTER_COE21_W::new(self, 5) + } + #[doc = "Bits 10:14 - this field configures usm filter coefficient"] + #[inline(always)] + #[must_use] + pub fn sharp_filter_coe22(&mut self) -> SHARP_FILTER_COE22_W { + SHARP_FILTER_COE22_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "sharp usm config register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_filter2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sharp_filter2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHARP_FILTER2_SPEC; +impl crate::RegisterSpec for SHARP_FILTER2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sharp_filter2::R`](R) reader structure"] +impl crate::Readable for SHARP_FILTER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sharp_filter2::W`](W) writer structure"] +impl crate::Writable for SHARP_FILTER2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SHARP_FILTER2 to value 0x0441"] +impl crate::Resettable for SHARP_FILTER2_SPEC { + const RESET_VALUE: Self::Ux = 0x0441; +} diff --git a/esp32p4/src/isp/sharp_matrix_ctrl.rs b/esp32p4/src/isp/sharp_matrix_ctrl.rs new file mode 100644 index 0000000000..2843890dda --- /dev/null +++ b/esp32p4/src/isp/sharp_matrix_ctrl.rs @@ -0,0 +1,127 @@ +#[doc = "Register `SHARP_MATRIX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SHARP_MATRIX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SHARP_TAIL_PIXEN_PULSE_TL` reader - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] +pub type SHARP_TAIL_PIXEN_PULSE_TL_R = crate::FieldReader; +#[doc = "Field `SHARP_TAIL_PIXEN_PULSE_TL` writer - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] +pub type SHARP_TAIL_PIXEN_PULSE_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SHARP_TAIL_PIXEN_PULSE_TH` reader - matrix tail pixen high level threshold, must < hnum-1, only reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail pulse function"] +pub type SHARP_TAIL_PIXEN_PULSE_TH_R = crate::FieldReader; +#[doc = "Field `SHARP_TAIL_PIXEN_PULSE_TH` writer - matrix tail pixen high level threshold, must < hnum-1, only reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail pulse function"] +pub type SHARP_TAIL_PIXEN_PULSE_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SHARP_PADDING_DATA` reader - this field configures sharp padding data"] +pub type SHARP_PADDING_DATA_R = crate::FieldReader; +#[doc = "Field `SHARP_PADDING_DATA` writer - this field configures sharp padding data"] +pub type SHARP_PADDING_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SHARP_PADDING_MODE` reader - this field configures sharp padding mode"] +pub type SHARP_PADDING_MODE_R = crate::BitReader; +#[doc = "Field `SHARP_PADDING_MODE` writer - this field configures sharp padding mode"] +pub type SHARP_PADDING_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + pub fn sharp_tail_pixen_pulse_tl(&self) -> SHARP_TAIL_PIXEN_PULSE_TL_R { + SHARP_TAIL_PIXEN_PULSE_TL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - matrix tail pixen high level threshold, must < hnum-1, only reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + pub fn sharp_tail_pixen_pulse_th(&self) -> SHARP_TAIL_PIXEN_PULSE_TH_R { + SHARP_TAIL_PIXEN_PULSE_TH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - this field configures sharp padding data"] + #[inline(always)] + pub fn sharp_padding_data(&self) -> SHARP_PADDING_DATA_R { + SHARP_PADDING_DATA_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - this field configures sharp padding mode"] + #[inline(always)] + pub fn sharp_padding_mode(&self) -> SHARP_PADDING_MODE_R { + SHARP_PADDING_MODE_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHARP_MATRIX_CTRL") + .field( + "sharp_tail_pixen_pulse_tl", + &format_args!("{}", self.sharp_tail_pixen_pulse_tl().bits()), + ) + .field( + "sharp_tail_pixen_pulse_th", + &format_args!("{}", self.sharp_tail_pixen_pulse_th().bits()), + ) + .field( + "sharp_padding_data", + &format_args!("{}", self.sharp_padding_data().bits()), + ) + .field( + "sharp_padding_mode", + &format_args!("{}", self.sharp_padding_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + #[must_use] + pub fn sharp_tail_pixen_pulse_tl( + &mut self, + ) -> SHARP_TAIL_PIXEN_PULSE_TL_W { + SHARP_TAIL_PIXEN_PULSE_TL_W::new(self, 0) + } + #[doc = "Bits 8:15 - matrix tail pixen high level threshold, must < hnum-1, only reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail pulse function"] + #[inline(always)] + #[must_use] + pub fn sharp_tail_pixen_pulse_th( + &mut self, + ) -> SHARP_TAIL_PIXEN_PULSE_TH_W { + SHARP_TAIL_PIXEN_PULSE_TH_W::new(self, 8) + } + #[doc = "Bits 16:23 - this field configures sharp padding data"] + #[inline(always)] + #[must_use] + pub fn sharp_padding_data(&mut self) -> SHARP_PADDING_DATA_W { + SHARP_PADDING_DATA_W::new(self, 16) + } + #[doc = "Bit 24 - this field configures sharp padding mode"] + #[inline(always)] + #[must_use] + pub fn sharp_padding_mode(&mut self) -> SHARP_PADDING_MODE_W { + SHARP_PADDING_MODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "sharp pix2matrix ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_matrix_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sharp_matrix_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHARP_MATRIX_CTRL_SPEC; +impl crate::RegisterSpec for SHARP_MATRIX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sharp_matrix_ctrl::R`](R) reader structure"] +impl crate::Readable for SHARP_MATRIX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sharp_matrix_ctrl::W`](W) writer structure"] +impl crate::Writable for SHARP_MATRIX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SHARP_MATRIX_CTRL to value 0"] +impl crate::Resettable for SHARP_MATRIX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/isp/ver_date.rs b/esp32p4/src/isp/ver_date.rs new file mode 100644 index 0000000000..8213f81b07 --- /dev/null +++ b/esp32p4/src/isp/ver_date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `VER_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `VER_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `VER_DATA` reader - csv version"] +pub type VER_DATA_R = crate::FieldReader; +#[doc = "Field `VER_DATA` writer - csv version"] +pub type VER_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - csv version"] + #[inline(always)] + pub fn ver_data(&self) -> VER_DATA_R { + VER_DATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VER_DATE") + .field("ver_data", &format_args!("{}", self.ver_data().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - csv version"] + #[inline(always)] + #[must_use] + pub fn ver_data(&mut self) -> VER_DATA_W { + VER_DATA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VER_DATE_SPEC; +impl crate::RegisterSpec for VER_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ver_date::R`](R) reader structure"] +impl crate::Readable for VER_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ver_date::W`](W) writer structure"] +impl crate::Writable for VER_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VER_DATE to value 0x2021_0608"] +impl crate::Resettable for VER_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2021_0608; +} diff --git a/esp32p4/src/isp/yuv_format.rs b/esp32p4/src/isp/yuv_format.rs new file mode 100644 index 0000000000..9c4b379bad --- /dev/null +++ b/esp32p4/src/isp/yuv_format.rs @@ -0,0 +1,79 @@ +#[doc = "Register `YUV_FORMAT` reader"] +pub type R = crate::R; +#[doc = "Register `YUV_FORMAT` writer"] +pub type W = crate::W; +#[doc = "Field `YUV_MODE` reader - this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709"] +pub type YUV_MODE_R = crate::BitReader; +#[doc = "Field `YUV_MODE` writer - this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709"] +pub type YUV_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `YUV_RANGE` reader - this bit configures the yuv range. 0: full range, 1: limit range"] +pub type YUV_RANGE_R = crate::BitReader; +#[doc = "Field `YUV_RANGE` writer - this bit configures the yuv range. 0: full range, 1: limit range"] +pub type YUV_RANGE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709"] + #[inline(always)] + pub fn yuv_mode(&self) -> YUV_MODE_R { + YUV_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - this bit configures the yuv range. 0: full range, 1: limit range"] + #[inline(always)] + pub fn yuv_range(&self) -> YUV_RANGE_R { + YUV_RANGE_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("YUV_FORMAT") + .field("yuv_mode", &format_args!("{}", self.yuv_mode().bit())) + .field("yuv_range", &format_args!("{}", self.yuv_range().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709"] + #[inline(always)] + #[must_use] + pub fn yuv_mode(&mut self) -> YUV_MODE_W { + YUV_MODE_W::new(self, 0) + } + #[doc = "Bit 1 - this bit configures the yuv range. 0: full range, 1: limit range"] + #[inline(always)] + #[must_use] + pub fn yuv_range(&mut self) -> YUV_RANGE_W { + YUV_RANGE_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "yuv format control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`yuv_format::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`yuv_format::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct YUV_FORMAT_SPEC; +impl crate::RegisterSpec for YUV_FORMAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`yuv_format::R`](R) reader structure"] +impl crate::Readable for YUV_FORMAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`yuv_format::W`](W) writer structure"] +impl crate::Writable for YUV_FORMAT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets YUV_FORMAT to value 0"] +impl crate::Resettable for YUV_FORMAT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg.rs b/esp32p4/src/jpeg.rs new file mode 100644 index 0000000000..236e807cbf --- /dev/null +++ b/esp32p4/src/jpeg.rs @@ -0,0 +1,449 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + config: CONFIG, + dqt_info: DQT_INFO, + pic_size: PIC_SIZE, + _reserved3: [u8; 0x04], + t0qnr: T0QNR, + t1qnr: T1QNR, + t2qnr: T2QNR, + t3qnr: T3QNR, + decode_conf: DECODE_CONF, + c0: C0, + c1: C1, + c2: C2, + c3: C3, + dht_info: DHT_INFO, + int_raw: INT_RAW, + int_ena: INT_ENA, + int_st: INT_ST, + int_clr: INT_CLR, + status0: STATUS0, + status2: STATUS2, + status3: STATUS3, + status4: STATUS4, + dht_totlen_dc0: DHT_TOTLEN_DC0, + dht_val_dc0: DHT_VAL_DC0, + dht_totlen_ac0: DHT_TOTLEN_AC0, + dht_val_ac0: DHT_VAL_AC0, + dht_totlen_dc1: DHT_TOTLEN_DC1, + dht_val_dc1: DHT_VAL_DC1, + dht_totlen_ac1: DHT_TOTLEN_AC1, + dht_val_ac1: DHT_VAL_AC1, + dht_codemin_dc0: DHT_CODEMIN_DC0, + dht_codemin_ac0: DHT_CODEMIN_AC0, + dht_codemin_dc1: DHT_CODEMIN_DC1, + dht_codemin_ac1: DHT_CODEMIN_AC1, + decoder_status0: DECODER_STATUS0, + decoder_status1: DECODER_STATUS1, + decoder_status2: DECODER_STATUS2, + decoder_status3: DECODER_STATUS3, + decoder_status4: DECODER_STATUS4, + decoder_status5: DECODER_STATUS5, + status5: STATUS5, + eco_low: ECO_LOW, + eco_high: ECO_HIGH, + _reserved42: [u8; 0x4c], + sys: SYS, + version: VERSION, +} +impl RegisterBlock { + #[doc = "0x00 - Control and configuration registers"] + #[inline(always)] + pub const fn config(&self) -> &CONFIG { + &self.config + } + #[doc = "0x04 - Control and configuration registers"] + #[inline(always)] + pub const fn dqt_info(&self) -> &DQT_INFO { + &self.dqt_info + } + #[doc = "0x08 - Control and configuration registers"] + #[inline(always)] + pub const fn pic_size(&self) -> &PIC_SIZE { + &self.pic_size + } + #[doc = "0x10 - Control and configuration registers"] + #[inline(always)] + pub const fn t0qnr(&self) -> &T0QNR { + &self.t0qnr + } + #[doc = "0x14 - Control and configuration registers"] + #[inline(always)] + pub const fn t1qnr(&self) -> &T1QNR { + &self.t1qnr + } + #[doc = "0x18 - Control and configuration registers"] + #[inline(always)] + pub const fn t2qnr(&self) -> &T2QNR { + &self.t2qnr + } + #[doc = "0x1c - Control and configuration registers"] + #[inline(always)] + pub const fn t3qnr(&self) -> &T3QNR { + &self.t3qnr + } + #[doc = "0x20 - Control and configuration registers"] + #[inline(always)] + pub const fn decode_conf(&self) -> &DECODE_CONF { + &self.decode_conf + } + #[doc = "0x24 - Control and configuration registers"] + #[inline(always)] + pub const fn c0(&self) -> &C0 { + &self.c0 + } + #[doc = "0x28 - Control and configuration registers"] + #[inline(always)] + pub const fn c1(&self) -> &C1 { + &self.c1 + } + #[doc = "0x2c - Control and configuration registers"] + #[inline(always)] + pub const fn c2(&self) -> &C2 { + &self.c2 + } + #[doc = "0x30 - Control and configuration registers"] + #[inline(always)] + pub const fn c3(&self) -> &C3 { + &self.c3 + } + #[doc = "0x34 - Control and configuration registers"] + #[inline(always)] + pub const fn dht_info(&self) -> &DHT_INFO { + &self.dht_info + } + #[doc = "0x38 - Interrupt raw registers"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x3c - Interrupt enable registers"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x40 - Interrupt status registers"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x44 - Interrupt clear registers"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x48 - Trace and Debug registers"] + #[inline(always)] + pub const fn status0(&self) -> &STATUS0 { + &self.status0 + } + #[doc = "0x4c - Trace and Debug registers"] + #[inline(always)] + pub const fn status2(&self) -> &STATUS2 { + &self.status2 + } + #[doc = "0x50 - Trace and Debug registers"] + #[inline(always)] + pub const fn status3(&self) -> &STATUS3 { + &self.status3 + } + #[doc = "0x54 - Trace and Debug registers"] + #[inline(always)] + pub const fn status4(&self) -> &STATUS4 { + &self.status4 + } + #[doc = "0x58 - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_totlen_dc0(&self) -> &DHT_TOTLEN_DC0 { + &self.dht_totlen_dc0 + } + #[doc = "0x5c - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_val_dc0(&self) -> &DHT_VAL_DC0 { + &self.dht_val_dc0 + } + #[doc = "0x60 - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_totlen_ac0(&self) -> &DHT_TOTLEN_AC0 { + &self.dht_totlen_ac0 + } + #[doc = "0x64 - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_val_ac0(&self) -> &DHT_VAL_AC0 { + &self.dht_val_ac0 + } + #[doc = "0x68 - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_totlen_dc1(&self) -> &DHT_TOTLEN_DC1 { + &self.dht_totlen_dc1 + } + #[doc = "0x6c - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_val_dc1(&self) -> &DHT_VAL_DC1 { + &self.dht_val_dc1 + } + #[doc = "0x70 - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_totlen_ac1(&self) -> &DHT_TOTLEN_AC1 { + &self.dht_totlen_ac1 + } + #[doc = "0x74 - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_val_ac1(&self) -> &DHT_VAL_AC1 { + &self.dht_val_ac1 + } + #[doc = "0x78 - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_codemin_dc0(&self) -> &DHT_CODEMIN_DC0 { + &self.dht_codemin_dc0 + } + #[doc = "0x7c - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_codemin_ac0(&self) -> &DHT_CODEMIN_AC0 { + &self.dht_codemin_ac0 + } + #[doc = "0x80 - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_codemin_dc1(&self) -> &DHT_CODEMIN_DC1 { + &self.dht_codemin_dc1 + } + #[doc = "0x84 - Trace and Debug registers"] + #[inline(always)] + pub const fn dht_codemin_ac1(&self) -> &DHT_CODEMIN_AC1 { + &self.dht_codemin_ac1 + } + #[doc = "0x88 - Trace and Debug registers"] + #[inline(always)] + pub const fn decoder_status0(&self) -> &DECODER_STATUS0 { + &self.decoder_status0 + } + #[doc = "0x8c - Trace and Debug registers"] + #[inline(always)] + pub const fn decoder_status1(&self) -> &DECODER_STATUS1 { + &self.decoder_status1 + } + #[doc = "0x90 - Trace and Debug registers"] + #[inline(always)] + pub const fn decoder_status2(&self) -> &DECODER_STATUS2 { + &self.decoder_status2 + } + #[doc = "0x94 - Trace and Debug registers"] + #[inline(always)] + pub const fn decoder_status3(&self) -> &DECODER_STATUS3 { + &self.decoder_status3 + } + #[doc = "0x98 - Trace and Debug registers"] + #[inline(always)] + pub const fn decoder_status4(&self) -> &DECODER_STATUS4 { + &self.decoder_status4 + } + #[doc = "0x9c - Trace and Debug registers"] + #[inline(always)] + pub const fn decoder_status5(&self) -> &DECODER_STATUS5 { + &self.decoder_status5 + } + #[doc = "0xa0 - Trace and Debug registers"] + #[inline(always)] + pub const fn status5(&self) -> &STATUS5 { + &self.status5 + } + #[doc = "0xa4 - Trace and Debug registers"] + #[inline(always)] + pub const fn eco_low(&self) -> &ECO_LOW { + &self.eco_low + } + #[doc = "0xa8 - Trace and Debug registers"] + #[inline(always)] + pub const fn eco_high(&self) -> &ECO_HIGH { + &self.eco_high + } + #[doc = "0xf8 - Trace and Debug registers"] + #[inline(always)] + pub const fn sys(&self) -> &SYS { + &self.sys + } + #[doc = "0xfc - Trace and Debug registers"] + #[inline(always)] + pub const fn version(&self) -> &VERSION { + &self.version + } +} +#[doc = "CONFIG (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] +pub type CONFIG = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod config; +#[doc = "DQT_INFO (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dqt_info::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dqt_info::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dqt_info`] module"] +pub type DQT_INFO = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod dqt_info; +#[doc = "PIC_SIZE (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pic_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pic_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pic_size`] module"] +pub type PIC_SIZE = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod pic_size; +#[doc = "T0QNR (r) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0qnr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0qnr`] module"] +pub type T0QNR = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod t0qnr; +#[doc = "T1QNR (r) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t1qnr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t1qnr`] module"] +pub type T1QNR = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod t1qnr; +#[doc = "T2QNR (r) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t2qnr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t2qnr`] module"] +pub type T2QNR = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod t2qnr; +#[doc = "T3QNR (r) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t3qnr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t3qnr`] module"] +pub type T3QNR = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod t3qnr; +#[doc = "DECODE_CONF (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decode_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`decode_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@decode_conf`] module"] +pub type DECODE_CONF = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod decode_conf; +#[doc = "C0 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c0`] module"] +pub type C0 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod c0; +#[doc = "C1 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c1`] module"] +pub type C1 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod c1; +#[doc = "C2 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c2`] module"] +pub type C2 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod c2; +#[doc = "C3 (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c3`] module"] +pub type C3 = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod c3; +#[doc = "DHT_INFO (rw) register accessor: Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_info::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dht_info::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_info`] module"] +pub type DHT_INFO = crate::Reg; +#[doc = "Control and configuration registers"] +pub mod dht_info; +#[doc = "INT_RAW (rw) register accessor: Interrupt raw registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Interrupt raw registers"] +pub mod int_raw; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable registers"] +pub mod int_ena; +#[doc = "INT_ST (r) register accessor: Interrupt status registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Interrupt status registers"] +pub mod int_st; +#[doc = "INT_CLR (w) register accessor: Interrupt clear registers\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear registers"] +pub mod int_clr; +#[doc = "STATUS0 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status0`] module"] +pub type STATUS0 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod status0; +#[doc = "STATUS2 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status2`] module"] +pub type STATUS2 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod status2; +#[doc = "STATUS3 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status3`] module"] +pub type STATUS3 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod status3; +#[doc = "STATUS4 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status4`] module"] +pub type STATUS4 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod status4; +#[doc = "DHT_TOTLEN_DC0 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_dc0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_totlen_dc0`] module"] +pub type DHT_TOTLEN_DC0 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_totlen_dc0; +#[doc = "DHT_VAl_DC0 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_dc0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_val_dc0`] module"] +pub type DHT_VAL_DC0 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_val_dc0; +#[doc = "DHT_TOTLEN_AC0 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_ac0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_totlen_ac0`] module"] +pub type DHT_TOTLEN_AC0 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_totlen_ac0; +#[doc = "DHT_VAl_AC0 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_ac0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_val_ac0`] module"] +pub type DHT_VAL_AC0 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_val_ac0; +#[doc = "DHT_TOTLEN_DC1 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_dc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_totlen_dc1`] module"] +pub type DHT_TOTLEN_DC1 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_totlen_dc1; +#[doc = "DHT_VAl_DC1 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_dc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_val_dc1`] module"] +pub type DHT_VAL_DC1 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_val_dc1; +#[doc = "DHT_TOTLEN_AC1 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_ac1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_totlen_ac1`] module"] +pub type DHT_TOTLEN_AC1 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_totlen_ac1; +#[doc = "DHT_VAl_AC1 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_ac1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_val_ac1`] module"] +pub type DHT_VAL_AC1 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_val_ac1; +#[doc = "DHT_CODEMIN_DC0 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_dc0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_codemin_dc0`] module"] +pub type DHT_CODEMIN_DC0 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_codemin_dc0; +#[doc = "DHT_CODEMIN_AC0 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_ac0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_codemin_ac0`] module"] +pub type DHT_CODEMIN_AC0 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_codemin_ac0; +#[doc = "DHT_CODEMIN_DC1 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_dc1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_codemin_dc1`] module"] +pub type DHT_CODEMIN_DC1 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_codemin_dc1; +#[doc = "DHT_CODEMIN_AC1 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_ac1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dht_codemin_ac1`] module"] +pub type DHT_CODEMIN_AC1 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod dht_codemin_ac1; +#[doc = "DECODER_STATUS0 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@decoder_status0`] module"] +pub type DECODER_STATUS0 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod decoder_status0; +#[doc = "DECODER_STATUS1 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@decoder_status1`] module"] +pub type DECODER_STATUS1 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod decoder_status1; +#[doc = "DECODER_STATUS2 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@decoder_status2`] module"] +pub type DECODER_STATUS2 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod decoder_status2; +#[doc = "DECODER_STATUS3 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@decoder_status3`] module"] +pub type DECODER_STATUS3 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod decoder_status3; +#[doc = "DECODER_STATUS4 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@decoder_status4`] module"] +pub type DECODER_STATUS4 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod decoder_status4; +#[doc = "DECODER_STATUS5 (rw) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`decoder_status5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@decoder_status5`] module"] +pub type DECODER_STATUS5 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod decoder_status5; +#[doc = "STATUS5 (r) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status5`] module"] +pub type STATUS5 = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod status5; +#[doc = "ECO_LOW (rw) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_low`] module"] +pub type ECO_LOW = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod eco_low; +#[doc = "ECO_HIGH (rw) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_high`] module"] +pub type ECO_HIGH = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod eco_high; +#[doc = "SYS (rw) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys`] module"] +pub type SYS = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod sys; +#[doc = "VERSION (rw) register accessor: Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"] +pub type VERSION = crate::Reg; +#[doc = "Trace and Debug registers"] +pub mod version; diff --git a/esp32p4/src/jpeg/c0.rs b/esp32p4/src/jpeg/c0.rs new file mode 100644 index 0000000000..9b2ac4fe68 --- /dev/null +++ b/esp32p4/src/jpeg/c0.rs @@ -0,0 +1,114 @@ +#[doc = "Register `C0` reader"] +pub type R = crate::R; +#[doc = "Register `C0` writer"] +pub type W = crate::W; +#[doc = "Field `DQT_TBL_SEL` reader - choose c0 quntization table id (TBD)"] +pub type DQT_TBL_SEL_R = crate::FieldReader; +#[doc = "Field `DQT_TBL_SEL` writer - choose c0 quntization table id (TBD)"] +pub type DQT_TBL_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Y_FACTOR` reader - vertical sampling factor of c0"] +pub type Y_FACTOR_R = crate::FieldReader; +#[doc = "Field `Y_FACTOR` writer - vertical sampling factor of c0"] +pub type Y_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `X_FACTOR` reader - horizontal sampling factor of c0"] +pub type X_FACTOR_R = crate::FieldReader; +#[doc = "Field `X_FACTOR` writer - horizontal sampling factor of c0"] +pub type X_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ID` reader - the identifier of c0"] +pub type ID_R = crate::FieldReader; +#[doc = "Field `ID` writer - the identifier of c0"] +pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - choose c0 quntization table id (TBD)"] + #[inline(always)] + pub fn dqt_tbl_sel(&self) -> DQT_TBL_SEL_R { + DQT_TBL_SEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - vertical sampling factor of c0"] + #[inline(always)] + pub fn y_factor(&self) -> Y_FACTOR_R { + Y_FACTOR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - horizontal sampling factor of c0"] + #[inline(always)] + pub fn x_factor(&self) -> X_FACTOR_R { + X_FACTOR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:23 - the identifier of c0"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("C0") + .field( + "dqt_tbl_sel", + &format_args!("{}", self.dqt_tbl_sel().bits()), + ) + .field("y_factor", &format_args!("{}", self.y_factor().bits())) + .field("x_factor", &format_args!("{}", self.x_factor().bits())) + .field("id", &format_args!("{}", self.id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - choose c0 quntization table id (TBD)"] + #[inline(always)] + #[must_use] + pub fn dqt_tbl_sel(&mut self) -> DQT_TBL_SEL_W { + DQT_TBL_SEL_W::new(self, 0) + } + #[doc = "Bits 8:11 - vertical sampling factor of c0"] + #[inline(always)] + #[must_use] + pub fn y_factor(&mut self) -> Y_FACTOR_W { + Y_FACTOR_W::new(self, 8) + } + #[doc = "Bits 12:15 - horizontal sampling factor of c0"] + #[inline(always)] + #[must_use] + pub fn x_factor(&mut self) -> X_FACTOR_W { + X_FACTOR_W::new(self, 12) + } + #[doc = "Bits 16:23 - the identifier of c0"] + #[inline(always)] + #[must_use] + pub fn id(&mut self) -> ID_W { + ID_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct C0_SPEC; +impl crate::RegisterSpec for C0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`c0::R`](R) reader structure"] +impl crate::Readable for C0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c0::W`](W) writer structure"] +impl crate::Writable for C0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C0 to value 0x1100"] +impl crate::Resettable for C0_SPEC { + const RESET_VALUE: Self::Ux = 0x1100; +} diff --git a/esp32p4/src/jpeg/c1.rs b/esp32p4/src/jpeg/c1.rs new file mode 100644 index 0000000000..68762f5a2f --- /dev/null +++ b/esp32p4/src/jpeg/c1.rs @@ -0,0 +1,114 @@ +#[doc = "Register `C1` reader"] +pub type R = crate::R; +#[doc = "Register `C1` writer"] +pub type W = crate::W; +#[doc = "Field `DQT_TBL_SEL` reader - choose c1 quntization table id (TBD)"] +pub type DQT_TBL_SEL_R = crate::FieldReader; +#[doc = "Field `DQT_TBL_SEL` writer - choose c1 quntization table id (TBD)"] +pub type DQT_TBL_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Y_FACTOR` reader - vertical sampling factor of c1"] +pub type Y_FACTOR_R = crate::FieldReader; +#[doc = "Field `Y_FACTOR` writer - vertical sampling factor of c1"] +pub type Y_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `X_FACTOR` reader - horizontal sampling factor of c1"] +pub type X_FACTOR_R = crate::FieldReader; +#[doc = "Field `X_FACTOR` writer - horizontal sampling factor of c1"] +pub type X_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ID` reader - the identifier of c1"] +pub type ID_R = crate::FieldReader; +#[doc = "Field `ID` writer - the identifier of c1"] +pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - choose c1 quntization table id (TBD)"] + #[inline(always)] + pub fn dqt_tbl_sel(&self) -> DQT_TBL_SEL_R { + DQT_TBL_SEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - vertical sampling factor of c1"] + #[inline(always)] + pub fn y_factor(&self) -> Y_FACTOR_R { + Y_FACTOR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - horizontal sampling factor of c1"] + #[inline(always)] + pub fn x_factor(&self) -> X_FACTOR_R { + X_FACTOR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:23 - the identifier of c1"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("C1") + .field( + "dqt_tbl_sel", + &format_args!("{}", self.dqt_tbl_sel().bits()), + ) + .field("y_factor", &format_args!("{}", self.y_factor().bits())) + .field("x_factor", &format_args!("{}", self.x_factor().bits())) + .field("id", &format_args!("{}", self.id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - choose c1 quntization table id (TBD)"] + #[inline(always)] + #[must_use] + pub fn dqt_tbl_sel(&mut self) -> DQT_TBL_SEL_W { + DQT_TBL_SEL_W::new(self, 0) + } + #[doc = "Bits 8:11 - vertical sampling factor of c1"] + #[inline(always)] + #[must_use] + pub fn y_factor(&mut self) -> Y_FACTOR_W { + Y_FACTOR_W::new(self, 8) + } + #[doc = "Bits 12:15 - horizontal sampling factor of c1"] + #[inline(always)] + #[must_use] + pub fn x_factor(&mut self) -> X_FACTOR_W { + X_FACTOR_W::new(self, 12) + } + #[doc = "Bits 16:23 - the identifier of c1"] + #[inline(always)] + #[must_use] + pub fn id(&mut self) -> ID_W { + ID_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct C1_SPEC; +impl crate::RegisterSpec for C1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`c1::R`](R) reader structure"] +impl crate::Readable for C1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c1::W`](W) writer structure"] +impl crate::Writable for C1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C1 to value 0x1100"] +impl crate::Resettable for C1_SPEC { + const RESET_VALUE: Self::Ux = 0x1100; +} diff --git a/esp32p4/src/jpeg/c2.rs b/esp32p4/src/jpeg/c2.rs new file mode 100644 index 0000000000..b7123e2699 --- /dev/null +++ b/esp32p4/src/jpeg/c2.rs @@ -0,0 +1,114 @@ +#[doc = "Register `C2` reader"] +pub type R = crate::R; +#[doc = "Register `C2` writer"] +pub type W = crate::W; +#[doc = "Field `DQT_TBL_SEL` reader - choose c2 quntization table id (TBD)"] +pub type DQT_TBL_SEL_R = crate::FieldReader; +#[doc = "Field `DQT_TBL_SEL` writer - choose c2 quntization table id (TBD)"] +pub type DQT_TBL_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Y_FACTOR` reader - vertical sampling factor of c2"] +pub type Y_FACTOR_R = crate::FieldReader; +#[doc = "Field `Y_FACTOR` writer - vertical sampling factor of c2"] +pub type Y_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `X_FACTOR` reader - horizontal sampling factor of c2"] +pub type X_FACTOR_R = crate::FieldReader; +#[doc = "Field `X_FACTOR` writer - horizontal sampling factor of c2"] +pub type X_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ID` reader - the identifier of c2"] +pub type ID_R = crate::FieldReader; +#[doc = "Field `ID` writer - the identifier of c2"] +pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - choose c2 quntization table id (TBD)"] + #[inline(always)] + pub fn dqt_tbl_sel(&self) -> DQT_TBL_SEL_R { + DQT_TBL_SEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - vertical sampling factor of c2"] + #[inline(always)] + pub fn y_factor(&self) -> Y_FACTOR_R { + Y_FACTOR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - horizontal sampling factor of c2"] + #[inline(always)] + pub fn x_factor(&self) -> X_FACTOR_R { + X_FACTOR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:23 - the identifier of c2"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("C2") + .field( + "dqt_tbl_sel", + &format_args!("{}", self.dqt_tbl_sel().bits()), + ) + .field("y_factor", &format_args!("{}", self.y_factor().bits())) + .field("x_factor", &format_args!("{}", self.x_factor().bits())) + .field("id", &format_args!("{}", self.id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - choose c2 quntization table id (TBD)"] + #[inline(always)] + #[must_use] + pub fn dqt_tbl_sel(&mut self) -> DQT_TBL_SEL_W { + DQT_TBL_SEL_W::new(self, 0) + } + #[doc = "Bits 8:11 - vertical sampling factor of c2"] + #[inline(always)] + #[must_use] + pub fn y_factor(&mut self) -> Y_FACTOR_W { + Y_FACTOR_W::new(self, 8) + } + #[doc = "Bits 12:15 - horizontal sampling factor of c2"] + #[inline(always)] + #[must_use] + pub fn x_factor(&mut self) -> X_FACTOR_W { + X_FACTOR_W::new(self, 12) + } + #[doc = "Bits 16:23 - the identifier of c2"] + #[inline(always)] + #[must_use] + pub fn id(&mut self) -> ID_W { + ID_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct C2_SPEC; +impl crate::RegisterSpec for C2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`c2::R`](R) reader structure"] +impl crate::Readable for C2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c2::W`](W) writer structure"] +impl crate::Writable for C2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C2 to value 0x1100"] +impl crate::Resettable for C2_SPEC { + const RESET_VALUE: Self::Ux = 0x1100; +} diff --git a/esp32p4/src/jpeg/c3.rs b/esp32p4/src/jpeg/c3.rs new file mode 100644 index 0000000000..07e9a80568 --- /dev/null +++ b/esp32p4/src/jpeg/c3.rs @@ -0,0 +1,114 @@ +#[doc = "Register `C3` reader"] +pub type R = crate::R; +#[doc = "Register `C3` writer"] +pub type W = crate::W; +#[doc = "Field `DQT_TBL_SEL` reader - choose c3 quntization table id (TBD)"] +pub type DQT_TBL_SEL_R = crate::FieldReader; +#[doc = "Field `DQT_TBL_SEL` writer - choose c3 quntization table id (TBD)"] +pub type DQT_TBL_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `Y_FACTOR` reader - vertical sampling factor of c3"] +pub type Y_FACTOR_R = crate::FieldReader; +#[doc = "Field `Y_FACTOR` writer - vertical sampling factor of c3"] +pub type Y_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `X_FACTOR` reader - horizontal sampling factor of c3"] +pub type X_FACTOR_R = crate::FieldReader; +#[doc = "Field `X_FACTOR` writer - horizontal sampling factor of c3"] +pub type X_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ID` reader - the identifier of c3"] +pub type ID_R = crate::FieldReader; +#[doc = "Field `ID` writer - the identifier of c3"] +pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - choose c3 quntization table id (TBD)"] + #[inline(always)] + pub fn dqt_tbl_sel(&self) -> DQT_TBL_SEL_R { + DQT_TBL_SEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - vertical sampling factor of c3"] + #[inline(always)] + pub fn y_factor(&self) -> Y_FACTOR_R { + Y_FACTOR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - horizontal sampling factor of c3"] + #[inline(always)] + pub fn x_factor(&self) -> X_FACTOR_R { + X_FACTOR_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:23 - the identifier of c3"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("C3") + .field( + "dqt_tbl_sel", + &format_args!("{}", self.dqt_tbl_sel().bits()), + ) + .field("y_factor", &format_args!("{}", self.y_factor().bits())) + .field("x_factor", &format_args!("{}", self.x_factor().bits())) + .field("id", &format_args!("{}", self.id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - choose c3 quntization table id (TBD)"] + #[inline(always)] + #[must_use] + pub fn dqt_tbl_sel(&mut self) -> DQT_TBL_SEL_W { + DQT_TBL_SEL_W::new(self, 0) + } + #[doc = "Bits 8:11 - vertical sampling factor of c3"] + #[inline(always)] + #[must_use] + pub fn y_factor(&mut self) -> Y_FACTOR_W { + Y_FACTOR_W::new(self, 8) + } + #[doc = "Bits 12:15 - horizontal sampling factor of c3"] + #[inline(always)] + #[must_use] + pub fn x_factor(&mut self) -> X_FACTOR_W { + X_FACTOR_W::new(self, 12) + } + #[doc = "Bits 16:23 - the identifier of c3"] + #[inline(always)] + #[must_use] + pub fn id(&mut self) -> ID_W { + ID_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct C3_SPEC; +impl crate::RegisterSpec for C3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`c3::R`](R) reader structure"] +impl crate::Readable for C3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`c3::W`](W) writer structure"] +impl crate::Writable for C3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets C3 to value 0x1100"] +impl crate::Resettable for C3_SPEC { + const RESET_VALUE: Self::Ux = 0x1100; +} diff --git a/esp32p4/src/jpeg/config.rs b/esp32p4/src/jpeg/config.rs new file mode 100644 index 0000000000..3b5490e009 --- /dev/null +++ b/esp32p4/src/jpeg/config.rs @@ -0,0 +1,421 @@ +#[doc = "Register `CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `FSM_RST` writer - fsm reset"] +pub type FSM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JPEG_START` writer - start to compress a new pic(in dma reg mode)"] +pub type JPEG_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QNR_PRESITION` reader - 0:8bit qnr,1:12bit qnr(TBD)"] +pub type QNR_PRESITION_R = crate::BitReader; +#[doc = "Field `QNR_PRESITION` writer - 0:8bit qnr,1:12bit qnr(TBD)"] +pub type QNR_PRESITION_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FF_CHECK_EN` reader - enable whether to add \"00\" after \"ff\""] +pub type FF_CHECK_EN_R = crate::BitReader; +#[doc = "Field `FF_CHECK_EN` writer - enable whether to add \"00\" after \"ff\""] +pub type FF_CHECK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAMPLE_SEL` reader - 0:yuv444,1:yuv422, 2:yuv420"] +pub type SAMPLE_SEL_R = crate::FieldReader; +#[doc = "Field `SAMPLE_SEL` writer - 0:yuv444,1:yuv422, 2:yuv420"] +pub type SAMPLE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DMA_LINKLIST_MODE` reader - 1:use linklist to configure dma"] +pub type DMA_LINKLIST_MODE_R = crate::BitReader; +#[doc = "Field `DEBUG_DIRECT_OUT_EN` reader - 0:normal mode,1:debug mode for direct output from input"] +pub type DEBUG_DIRECT_OUT_EN_R = crate::BitReader; +#[doc = "Field `DEBUG_DIRECT_OUT_EN` writer - 0:normal mode,1:debug mode for direct output from input"] +pub type DEBUG_DIRECT_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GRAY_SEL` reader - 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram"] +pub type GRAY_SEL_R = crate::BitReader; +#[doc = "Field `GRAY_SEL` writer - 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram"] +pub type GRAY_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LQNR_TBL_SEL` reader - choose luminance quntization table id(TBD)"] +pub type LQNR_TBL_SEL_R = crate::FieldReader; +#[doc = "Field `LQNR_TBL_SEL` writer - choose luminance quntization table id(TBD)"] +pub type LQNR_TBL_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CQNR_TBL_SEL` reader - choose chrominance quntization table id (TBD)"] +pub type CQNR_TBL_SEL_R = crate::FieldReader; +#[doc = "Field `CQNR_TBL_SEL` writer - choose chrominance quntization table id (TBD)"] +pub type CQNR_TBL_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `COLOR_SPACE` reader - configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray"] +pub type COLOR_SPACE_R = crate::FieldReader; +#[doc = "Field `COLOR_SPACE` writer - configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray"] +pub type COLOR_SPACE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DHT_FIFO_EN` reader - 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to write dht len_total/codemin/value table. Reading dht len_total/codemin/value table only has nonfifo way"] +pub type DHT_FIFO_EN_R = crate::BitReader; +#[doc = "Field `DHT_FIFO_EN` writer - 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to write dht len_total/codemin/value table. Reading dht len_total/codemin/value table only has nonfifo way"] +pub type DHT_FIFO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_CLK_FORCE_ON` reader - force memory's clock enabled"] +pub type MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `MEM_CLK_FORCE_ON` writer - force memory's clock enabled"] +pub type MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JFIF_VER` reader - decode pause period to trigger decode_timeout int, the timeout periods =2 power (reg_decode_timeout_thres) -1"] +pub type JFIF_VER_R = crate::FieldReader; +#[doc = "Field `JFIF_VER` writer - decode pause period to trigger decode_timeout int, the timeout periods =2 power (reg_decode_timeout_thres) -1"] +pub type JFIF_VER_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `DECODE_TIMEOUT_TASK_SEL` reader - 0: software use reset to abort decode process ,1: decoder abort decode process by itself"] +pub type DECODE_TIMEOUT_TASK_SEL_R = crate::BitReader; +#[doc = "Field `DECODE_TIMEOUT_TASK_SEL` writer - 0: software use reset to abort decode process ,1: decoder abort decode process by itself"] +pub type DECODE_TIMEOUT_TASK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOFT_RST` reader - when set to 1, soft reset JPEG module except jpeg_reg module"] +pub type SOFT_RST_R = crate::BitReader; +#[doc = "Field `SOFT_RST` writer - when set to 1, soft reset JPEG module except jpeg_reg module"] +pub type SOFT_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_RST` reader - fifo reset"] +pub type FIFO_RST_R = crate::BitReader; +#[doc = "Field `FIFO_RST` writer - fifo reset"] +pub type FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PIXEL_REV` reader - reverse the source color pixel"] +pub type PIXEL_REV_R = crate::BitReader; +#[doc = "Field `PIXEL_REV` writer - reverse the source color pixel"] +pub type PIXEL_REV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TAILER_EN` reader - set this bit to add EOI of \"0xffd9\" at the end of bitstream"] +pub type TAILER_EN_R = crate::BitReader; +#[doc = "Field `TAILER_EN` writer - set this bit to add EOI of \"0xffd9\" at the end of bitstream"] +pub type TAILER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PAUSE_EN` reader - set this bit to pause jpeg encoding"] +pub type PAUSE_EN_R = crate::BitReader; +#[doc = "Field `PAUSE_EN` writer - set this bit to pause jpeg encoding"] +pub type PAUSE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_FORCE_PD` reader - 0: no operation,1:force jpeg memory to power down"] +pub type MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PD` writer - 0: no operation,1:force jpeg memory to power down"] +pub type MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_FORCE_PU` reader - 0: no operation,1:force jpeg memory to power up"] +pub type MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PU` writer - 0: no operation,1:force jpeg memory to power up"] +pub type MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MODE` reader - 0:encoder mode, 1: decoder mode"] +pub type MODE_R = crate::BitReader; +#[doc = "Field `MODE` writer - 0:encoder mode, 1: decoder mode"] +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - 0:8bit qnr,1:12bit qnr(TBD)"] + #[inline(always)] + pub fn qnr_presition(&self) -> QNR_PRESITION_R { + QNR_PRESITION_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - enable whether to add \"00\" after \"ff\""] + #[inline(always)] + pub fn ff_check_en(&self) -> FF_CHECK_EN_R { + FF_CHECK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - 0:yuv444,1:yuv422, 2:yuv420"] + #[inline(always)] + pub fn sample_sel(&self) -> SAMPLE_SEL_R { + SAMPLE_SEL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - 1:use linklist to configure dma"] + #[inline(always)] + pub fn dma_linklist_mode(&self) -> DMA_LINKLIST_MODE_R { + DMA_LINKLIST_MODE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 0:normal mode,1:debug mode for direct output from input"] + #[inline(always)] + pub fn debug_direct_out_en(&self) -> DEBUG_DIRECT_OUT_EN_R { + DEBUG_DIRECT_OUT_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram"] + #[inline(always)] + pub fn gray_sel(&self) -> GRAY_SEL_R { + GRAY_SEL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:10 - choose luminance quntization table id(TBD)"] + #[inline(always)] + pub fn lqnr_tbl_sel(&self) -> LQNR_TBL_SEL_R { + LQNR_TBL_SEL_R::new(((self.bits >> 9) & 3) as u8) + } + #[doc = "Bits 11:12 - choose chrominance quntization table id (TBD)"] + #[inline(always)] + pub fn cqnr_tbl_sel(&self) -> CQNR_TBL_SEL_R { + CQNR_TBL_SEL_R::new(((self.bits >> 11) & 3) as u8) + } + #[doc = "Bits 13:14 - configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray"] + #[inline(always)] + pub fn color_space(&self) -> COLOR_SPACE_R { + COLOR_SPACE_R::new(((self.bits >> 13) & 3) as u8) + } + #[doc = "Bit 15 - 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to write dht len_total/codemin/value table. Reading dht len_total/codemin/value table only has nonfifo way"] + #[inline(always)] + pub fn dht_fifo_en(&self) -> DHT_FIFO_EN_R { + DHT_FIFO_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - force memory's clock enabled"] + #[inline(always)] + pub fn mem_clk_force_on(&self) -> MEM_CLK_FORCE_ON_R { + MEM_CLK_FORCE_ON_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:22 - decode pause period to trigger decode_timeout int, the timeout periods =2 power (reg_decode_timeout_thres) -1"] + #[inline(always)] + pub fn jfif_ver(&self) -> JFIF_VER_R { + JFIF_VER_R::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bit 23 - 0: software use reset to abort decode process ,1: decoder abort decode process by itself"] + #[inline(always)] + pub fn decode_timeout_task_sel(&self) -> DECODE_TIMEOUT_TASK_SEL_R { + DECODE_TIMEOUT_TASK_SEL_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - when set to 1, soft reset JPEG module except jpeg_reg module"] + #[inline(always)] + pub fn soft_rst(&self) -> SOFT_RST_R { + SOFT_RST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - fifo reset"] + #[inline(always)] + pub fn fifo_rst(&self) -> FIFO_RST_R { + FIFO_RST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - reverse the source color pixel"] + #[inline(always)] + pub fn pixel_rev(&self) -> PIXEL_REV_R { + PIXEL_REV_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - set this bit to add EOI of \"0xffd9\" at the end of bitstream"] + #[inline(always)] + pub fn tailer_en(&self) -> TAILER_EN_R { + TAILER_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - set this bit to pause jpeg encoding"] + #[inline(always)] + pub fn pause_en(&self) -> PAUSE_EN_R { + PAUSE_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - 0: no operation,1:force jpeg memory to power down"] + #[inline(always)] + pub fn mem_force_pd(&self) -> MEM_FORCE_PD_R { + MEM_FORCE_PD_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - 0: no operation,1:force jpeg memory to power up"] + #[inline(always)] + pub fn mem_force_pu(&self) -> MEM_FORCE_PU_R { + MEM_FORCE_PU_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 0:encoder mode, 1: decoder mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG") + .field( + "qnr_presition", + &format_args!("{}", self.qnr_presition().bit()), + ) + .field("ff_check_en", &format_args!("{}", self.ff_check_en().bit())) + .field("sample_sel", &format_args!("{}", self.sample_sel().bits())) + .field( + "dma_linklist_mode", + &format_args!("{}", self.dma_linklist_mode().bit()), + ) + .field( + "debug_direct_out_en", + &format_args!("{}", self.debug_direct_out_en().bit()), + ) + .field("gray_sel", &format_args!("{}", self.gray_sel().bit())) + .field( + "lqnr_tbl_sel", + &format_args!("{}", self.lqnr_tbl_sel().bits()), + ) + .field( + "cqnr_tbl_sel", + &format_args!("{}", self.cqnr_tbl_sel().bits()), + ) + .field( + "color_space", + &format_args!("{}", self.color_space().bits()), + ) + .field("dht_fifo_en", &format_args!("{}", self.dht_fifo_en().bit())) + .field( + "mem_clk_force_on", + &format_args!("{}", self.mem_clk_force_on().bit()), + ) + .field("jfif_ver", &format_args!("{}", self.jfif_ver().bits())) + .field( + "decode_timeout_task_sel", + &format_args!("{}", self.decode_timeout_task_sel().bit()), + ) + .field("soft_rst", &format_args!("{}", self.soft_rst().bit())) + .field("fifo_rst", &format_args!("{}", self.fifo_rst().bit())) + .field("pixel_rev", &format_args!("{}", self.pixel_rev().bit())) + .field("tailer_en", &format_args!("{}", self.tailer_en().bit())) + .field("pause_en", &format_args!("{}", self.pause_en().bit())) + .field( + "mem_force_pd", + &format_args!("{}", self.mem_force_pd().bit()), + ) + .field( + "mem_force_pu", + &format_args!("{}", self.mem_force_pu().bit()), + ) + .field("mode", &format_args!("{}", self.mode().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - fsm reset"] + #[inline(always)] + #[must_use] + pub fn fsm_rst(&mut self) -> FSM_RST_W { + FSM_RST_W::new(self, 0) + } + #[doc = "Bit 1 - start to compress a new pic(in dma reg mode)"] + #[inline(always)] + #[must_use] + pub fn jpeg_start(&mut self) -> JPEG_START_W { + JPEG_START_W::new(self, 1) + } + #[doc = "Bit 2 - 0:8bit qnr,1:12bit qnr(TBD)"] + #[inline(always)] + #[must_use] + pub fn qnr_presition(&mut self) -> QNR_PRESITION_W { + QNR_PRESITION_W::new(self, 2) + } + #[doc = "Bit 3 - enable whether to add \"00\" after \"ff\""] + #[inline(always)] + #[must_use] + pub fn ff_check_en(&mut self) -> FF_CHECK_EN_W { + FF_CHECK_EN_W::new(self, 3) + } + #[doc = "Bits 4:5 - 0:yuv444,1:yuv422, 2:yuv420"] + #[inline(always)] + #[must_use] + pub fn sample_sel(&mut self) -> SAMPLE_SEL_W { + SAMPLE_SEL_W::new(self, 4) + } + #[doc = "Bit 7 - 0:normal mode,1:debug mode for direct output from input"] + #[inline(always)] + #[must_use] + pub fn debug_direct_out_en(&mut self) -> DEBUG_DIRECT_OUT_EN_W { + DEBUG_DIRECT_OUT_EN_W::new(self, 7) + } + #[doc = "Bit 8 - 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram"] + #[inline(always)] + #[must_use] + pub fn gray_sel(&mut self) -> GRAY_SEL_W { + GRAY_SEL_W::new(self, 8) + } + #[doc = "Bits 9:10 - choose luminance quntization table id(TBD)"] + #[inline(always)] + #[must_use] + pub fn lqnr_tbl_sel(&mut self) -> LQNR_TBL_SEL_W { + LQNR_TBL_SEL_W::new(self, 9) + } + #[doc = "Bits 11:12 - choose chrominance quntization table id (TBD)"] + #[inline(always)] + #[must_use] + pub fn cqnr_tbl_sel(&mut self) -> CQNR_TBL_SEL_W { + CQNR_TBL_SEL_W::new(self, 11) + } + #[doc = "Bits 13:14 - configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray"] + #[inline(always)] + #[must_use] + pub fn color_space(&mut self) -> COLOR_SPACE_W { + COLOR_SPACE_W::new(self, 13) + } + #[doc = "Bit 15 - 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to write dht len_total/codemin/value table. Reading dht len_total/codemin/value table only has nonfifo way"] + #[inline(always)] + #[must_use] + pub fn dht_fifo_en(&mut self) -> DHT_FIFO_EN_W { + DHT_FIFO_EN_W::new(self, 15) + } + #[doc = "Bit 16 - force memory's clock enabled"] + #[inline(always)] + #[must_use] + pub fn mem_clk_force_on(&mut self) -> MEM_CLK_FORCE_ON_W { + MEM_CLK_FORCE_ON_W::new(self, 16) + } + #[doc = "Bits 17:22 - decode pause period to trigger decode_timeout int, the timeout periods =2 power (reg_decode_timeout_thres) -1"] + #[inline(always)] + #[must_use] + pub fn jfif_ver(&mut self) -> JFIF_VER_W { + JFIF_VER_W::new(self, 17) + } + #[doc = "Bit 23 - 0: software use reset to abort decode process ,1: decoder abort decode process by itself"] + #[inline(always)] + #[must_use] + pub fn decode_timeout_task_sel(&mut self) -> DECODE_TIMEOUT_TASK_SEL_W { + DECODE_TIMEOUT_TASK_SEL_W::new(self, 23) + } + #[doc = "Bit 24 - when set to 1, soft reset JPEG module except jpeg_reg module"] + #[inline(always)] + #[must_use] + pub fn soft_rst(&mut self) -> SOFT_RST_W { + SOFT_RST_W::new(self, 24) + } + #[doc = "Bit 25 - fifo reset"] + #[inline(always)] + #[must_use] + pub fn fifo_rst(&mut self) -> FIFO_RST_W { + FIFO_RST_W::new(self, 25) + } + #[doc = "Bit 26 - reverse the source color pixel"] + #[inline(always)] + #[must_use] + pub fn pixel_rev(&mut self) -> PIXEL_REV_W { + PIXEL_REV_W::new(self, 26) + } + #[doc = "Bit 27 - set this bit to add EOI of \"0xffd9\" at the end of bitstream"] + #[inline(always)] + #[must_use] + pub fn tailer_en(&mut self) -> TAILER_EN_W { + TAILER_EN_W::new(self, 27) + } + #[doc = "Bit 28 - set this bit to pause jpeg encoding"] + #[inline(always)] + #[must_use] + pub fn pause_en(&mut self) -> PAUSE_EN_W { + PAUSE_EN_W::new(self, 28) + } + #[doc = "Bit 29 - 0: no operation,1:force jpeg memory to power down"] + #[inline(always)] + #[must_use] + pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W { + MEM_FORCE_PD_W::new(self, 29) + } + #[doc = "Bit 30 - 0: no operation,1:force jpeg memory to power up"] + #[inline(always)] + #[must_use] + pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W { + MEM_FORCE_PU_W::new(self, 30) + } + #[doc = "Bit 31 - 0:encoder mode, 1: decoder mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`config::R`](R) reader structure"] +impl crate::Readable for CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONFIG to value 0x0040_8958"] +impl crate::Resettable for CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0x0040_8958; +} diff --git a/esp32p4/src/jpeg/decode_conf.rs b/esp32p4/src/jpeg/decode_conf.rs new file mode 100644 index 0000000000..9b62f7473a --- /dev/null +++ b/esp32p4/src/jpeg/decode_conf.rs @@ -0,0 +1,169 @@ +#[doc = "Register `DECODE_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `DECODE_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `RESTART_INTERVAL` reader - configure restart interval in DRI marker when decode"] +pub type RESTART_INTERVAL_R = crate::FieldReader; +#[doc = "Field `RESTART_INTERVAL` writer - configure restart interval in DRI marker when decode"] +pub type RESTART_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `COMPONENT_NUM` reader - configure number of components in frame when decode"] +pub type COMPONENT_NUM_R = crate::FieldReader; +#[doc = "Field `COMPONENT_NUM` writer - configure number of components in frame when decode"] +pub type COMPONENT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SW_DHT_EN` reader - software decode dht table enable"] +pub type SW_DHT_EN_R = crate::BitReader; +#[doc = "Field `SOS_CHECK_BYTE_NUM` reader - Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1"] +pub type SOS_CHECK_BYTE_NUM_R = crate::FieldReader; +#[doc = "Field `SOS_CHECK_BYTE_NUM` writer - Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1"] +pub type SOS_CHECK_BYTE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RST_CHECK_BYTE_NUM` reader - Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1"] +pub type RST_CHECK_BYTE_NUM_R = crate::FieldReader; +#[doc = "Field `RST_CHECK_BYTE_NUM` writer - Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1"] +pub type RST_CHECK_BYTE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `MULTI_SCAN_ERR_CHECK` reader - reserved for decoder"] +pub type MULTI_SCAN_ERR_CHECK_R = crate::BitReader; +#[doc = "Field `MULTI_SCAN_ERR_CHECK` writer - reserved for decoder"] +pub type MULTI_SCAN_ERR_CHECK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEZIGZAG_READY_CTL` reader - reserved for decoder"] +pub type DEZIGZAG_READY_CTL_R = crate::BitReader; +#[doc = "Field `DEZIGZAG_READY_CTL` writer - reserved for decoder"] +pub type DEZIGZAG_READY_CTL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - configure restart interval in DRI marker when decode"] + #[inline(always)] + pub fn restart_interval(&self) -> RESTART_INTERVAL_R { + RESTART_INTERVAL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - configure number of components in frame when decode"] + #[inline(always)] + pub fn component_num(&self) -> COMPONENT_NUM_R { + COMPONENT_NUM_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - software decode dht table enable"] + #[inline(always)] + pub fn sw_dht_en(&self) -> SW_DHT_EN_R { + SW_DHT_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:26 - Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1"] + #[inline(always)] + pub fn sos_check_byte_num(&self) -> SOS_CHECK_BYTE_NUM_R { + SOS_CHECK_BYTE_NUM_R::new(((self.bits >> 25) & 3) as u8) + } + #[doc = "Bits 27:28 - Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1"] + #[inline(always)] + pub fn rst_check_byte_num(&self) -> RST_CHECK_BYTE_NUM_R { + RST_CHECK_BYTE_NUM_R::new(((self.bits >> 27) & 3) as u8) + } + #[doc = "Bit 29 - reserved for decoder"] + #[inline(always)] + pub fn multi_scan_err_check(&self) -> MULTI_SCAN_ERR_CHECK_R { + MULTI_SCAN_ERR_CHECK_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - reserved for decoder"] + #[inline(always)] + pub fn dezigzag_ready_ctl(&self) -> DEZIGZAG_READY_CTL_R { + DEZIGZAG_READY_CTL_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DECODE_CONF") + .field( + "restart_interval", + &format_args!("{}", self.restart_interval().bits()), + ) + .field( + "component_num", + &format_args!("{}", self.component_num().bits()), + ) + .field("sw_dht_en", &format_args!("{}", self.sw_dht_en().bit())) + .field( + "sos_check_byte_num", + &format_args!("{}", self.sos_check_byte_num().bits()), + ) + .field( + "rst_check_byte_num", + &format_args!("{}", self.rst_check_byte_num().bits()), + ) + .field( + "multi_scan_err_check", + &format_args!("{}", self.multi_scan_err_check().bit()), + ) + .field( + "dezigzag_ready_ctl", + &format_args!("{}", self.dezigzag_ready_ctl().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - configure restart interval in DRI marker when decode"] + #[inline(always)] + #[must_use] + pub fn restart_interval(&mut self) -> RESTART_INTERVAL_W { + RESTART_INTERVAL_W::new(self, 0) + } + #[doc = "Bits 16:23 - configure number of components in frame when decode"] + #[inline(always)] + #[must_use] + pub fn component_num(&mut self) -> COMPONENT_NUM_W { + COMPONENT_NUM_W::new(self, 16) + } + #[doc = "Bits 25:26 - Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1"] + #[inline(always)] + #[must_use] + pub fn sos_check_byte_num(&mut self) -> SOS_CHECK_BYTE_NUM_W { + SOS_CHECK_BYTE_NUM_W::new(self, 25) + } + #[doc = "Bits 27:28 - Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1"] + #[inline(always)] + #[must_use] + pub fn rst_check_byte_num(&mut self) -> RST_CHECK_BYTE_NUM_W { + RST_CHECK_BYTE_NUM_W::new(self, 27) + } + #[doc = "Bit 29 - reserved for decoder"] + #[inline(always)] + #[must_use] + pub fn multi_scan_err_check(&mut self) -> MULTI_SCAN_ERR_CHECK_W { + MULTI_SCAN_ERR_CHECK_W::new(self, 29) + } + #[doc = "Bit 30 - reserved for decoder"] + #[inline(always)] + #[must_use] + pub fn dezigzag_ready_ctl(&mut self) -> DEZIGZAG_READY_CTL_W { + DEZIGZAG_READY_CTL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decode_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`decode_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DECODE_CONF_SPEC; +impl crate::RegisterSpec for DECODE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`decode_conf::R`](R) reader structure"] +impl crate::Readable for DECODE_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`decode_conf::W`](W) writer structure"] +impl crate::Writable for DECODE_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DECODE_CONF to value 0x5f03_0000"] +impl crate::Resettable for DECODE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x5f03_0000; +} diff --git a/esp32p4/src/jpeg/decoder_status0.rs b/esp32p4/src/jpeg/decoder_status0.rs new file mode 100644 index 0000000000..50b0b1bc33 --- /dev/null +++ b/esp32p4/src/jpeg/decoder_status0.rs @@ -0,0 +1,61 @@ +#[doc = "Register `DECODER_STATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `DECODE_BYTE_CNT` reader - Reserved"] +pub type DECODE_BYTE_CNT_R = crate::FieldReader; +#[doc = "Field `HEADER_DEC_ST` reader - Reserved"] +pub type HEADER_DEC_ST_R = crate::FieldReader; +#[doc = "Field `DECODE_SAMPLE_SEL` reader - Reserved"] +pub type DECODE_SAMPLE_SEL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:25 - Reserved"] + #[inline(always)] + pub fn decode_byte_cnt(&self) -> DECODE_BYTE_CNT_R { + DECODE_BYTE_CNT_R::new(self.bits & 0x03ff_ffff) + } + #[doc = "Bits 26:29 - Reserved"] + #[inline(always)] + pub fn header_dec_st(&self) -> HEADER_DEC_ST_R { + HEADER_DEC_ST_R::new(((self.bits >> 26) & 0x0f) as u8) + } + #[doc = "Bits 30:31 - Reserved"] + #[inline(always)] + pub fn decode_sample_sel(&self) -> DECODE_SAMPLE_SEL_R { + DECODE_SAMPLE_SEL_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DECODER_STATUS0") + .field( + "decode_byte_cnt", + &format_args!("{}", self.decode_byte_cnt().bits()), + ) + .field( + "header_dec_st", + &format_args!("{}", self.header_dec_st().bits()), + ) + .field( + "decode_sample_sel", + &format_args!("{}", self.decode_sample_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DECODER_STATUS0_SPEC; +impl crate::RegisterSpec for DECODER_STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`decoder_status0::R`](R) reader structure"] +impl crate::Readable for DECODER_STATUS0_SPEC {} +#[doc = "`reset()` method sets DECODER_STATUS0 to value 0"] +impl crate::Resettable for DECODER_STATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/decoder_status1.rs b/esp32p4/src/jpeg/decoder_status1.rs new file mode 100644 index 0000000000..085581ce59 --- /dev/null +++ b/esp32p4/src/jpeg/decoder_status1.rs @@ -0,0 +1,69 @@ +#[doc = "Register `DECODER_STATUS1` reader"] +pub type R = crate::R; +#[doc = "Field `ENCODE_DATA` reader - Reserved"] +pub type ENCODE_DATA_R = crate::FieldReader; +#[doc = "Field `COUNT_Q` reader - Reserved"] +pub type COUNT_Q_R = crate::FieldReader; +#[doc = "Field `MCU_FSM_READY` reader - Reserved"] +pub type MCU_FSM_READY_R = crate::BitReader; +#[doc = "Field `DECODE_DATA` reader - Reserved"] +pub type DECODE_DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + pub fn encode_data(&self) -> ENCODE_DATA_R { + ENCODE_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:22 - Reserved"] + #[inline(always)] + pub fn count_q(&self) -> COUNT_Q_R { + COUNT_Q_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + pub fn mcu_fsm_ready(&self) -> MCU_FSM_READY_R { + MCU_FSM_READY_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:31 - Reserved"] + #[inline(always)] + pub fn decode_data(&self) -> DECODE_DATA_R { + DECODE_DATA_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DECODER_STATUS1") + .field( + "encode_data", + &format_args!("{}", self.encode_data().bits()), + ) + .field("count_q", &format_args!("{}", self.count_q().bits())) + .field( + "mcu_fsm_ready", + &format_args!("{}", self.mcu_fsm_ready().bit()), + ) + .field( + "decode_data", + &format_args!("{}", self.decode_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DECODER_STATUS1_SPEC; +impl crate::RegisterSpec for DECODER_STATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`decoder_status1::R`](R) reader structure"] +impl crate::Readable for DECODER_STATUS1_SPEC {} +#[doc = "`reset()` method sets DECODER_STATUS1 to value 0"] +impl crate::Resettable for DECODER_STATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/decoder_status2.rs b/esp32p4/src/jpeg/decoder_status2.rs new file mode 100644 index 0000000000..d1f3314054 --- /dev/null +++ b/esp32p4/src/jpeg/decoder_status2.rs @@ -0,0 +1,77 @@ +#[doc = "Register `DECODER_STATUS2` reader"] +pub type R = crate::R; +#[doc = "Field `COMP_BLOCK_NUM` reader - Reserved"] +pub type COMP_BLOCK_NUM_R = crate::FieldReader; +#[doc = "Field `SCAN_NUM` reader - Reserved"] +pub type SCAN_NUM_R = crate::FieldReader; +#[doc = "Field `RST_CHECK_WAIT` reader - Reserved"] +pub type RST_CHECK_WAIT_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_WAIT` reader - Reserved"] +pub type SCAN_CHECK_WAIT_R = crate::BitReader; +#[doc = "Field `MCU_IN_PROC` reader - Reserved"] +pub type MCU_IN_PROC_R = crate::BitReader; +impl R { + #[doc = "Bits 0:25 - Reserved"] + #[inline(always)] + pub fn comp_block_num(&self) -> COMP_BLOCK_NUM_R { + COMP_BLOCK_NUM_R::new(self.bits & 0x03ff_ffff) + } + #[doc = "Bits 26:28 - Reserved"] + #[inline(always)] + pub fn scan_num(&self) -> SCAN_NUM_R { + SCAN_NUM_R::new(((self.bits >> 26) & 7) as u8) + } + #[doc = "Bit 29 - Reserved"] + #[inline(always)] + pub fn rst_check_wait(&self) -> RST_CHECK_WAIT_R { + RST_CHECK_WAIT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Reserved"] + #[inline(always)] + pub fn scan_check_wait(&self) -> SCAN_CHECK_WAIT_R { + SCAN_CHECK_WAIT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn mcu_in_proc(&self) -> MCU_IN_PROC_R { + MCU_IN_PROC_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DECODER_STATUS2") + .field( + "comp_block_num", + &format_args!("{}", self.comp_block_num().bits()), + ) + .field("scan_num", &format_args!("{}", self.scan_num().bits())) + .field( + "rst_check_wait", + &format_args!("{}", self.rst_check_wait().bit()), + ) + .field( + "scan_check_wait", + &format_args!("{}", self.scan_check_wait().bit()), + ) + .field("mcu_in_proc", &format_args!("{}", self.mcu_in_proc().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DECODER_STATUS2_SPEC; +impl crate::RegisterSpec for DECODER_STATUS2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`decoder_status2::R`](R) reader structure"] +impl crate::Readable for DECODER_STATUS2_SPEC {} +#[doc = "`reset()` method sets DECODER_STATUS2 to value 0"] +impl crate::Resettable for DECODER_STATUS2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/decoder_status3.rs b/esp32p4/src/jpeg/decoder_status3.rs new file mode 100644 index 0000000000..47922653a7 --- /dev/null +++ b/esp32p4/src/jpeg/decoder_status3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DECODER_STATUS3` reader"] +pub type R = crate::R; +#[doc = "Field `LOOKUP_DATA` reader - Reserved"] +pub type LOOKUP_DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Reserved"] + #[inline(always)] + pub fn lookup_data(&self) -> LOOKUP_DATA_R { + LOOKUP_DATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DECODER_STATUS3") + .field( + "lookup_data", + &format_args!("{}", self.lookup_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DECODER_STATUS3_SPEC; +impl crate::RegisterSpec for DECODER_STATUS3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`decoder_status3::R`](R) reader structure"] +impl crate::Readable for DECODER_STATUS3_SPEC {} +#[doc = "`reset()` method sets DECODER_STATUS3 to value 0"] +impl crate::Resettable for DECODER_STATUS3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/decoder_status4.rs b/esp32p4/src/jpeg/decoder_status4.rs new file mode 100644 index 0000000000..2da71f42c7 --- /dev/null +++ b/esp32p4/src/jpeg/decoder_status4.rs @@ -0,0 +1,72 @@ +#[doc = "Register `DECODER_STATUS4` reader"] +pub type R = crate::R; +#[doc = "Field `BLOCK_EOF_CNT` reader - Reserved"] +pub type BLOCK_EOF_CNT_R = crate::FieldReader; +#[doc = "Field `DEZIGZAG_READY` reader - Reserved"] +pub type DEZIGZAG_READY_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_CHECK` reader - Reserved"] +pub type DE_FRAME_EOF_CHECK_R = crate::BitReader; +#[doc = "Field `DE_DMA2D_IN_PUSH` reader - Reserved"] +pub type DE_DMA2D_IN_PUSH_R = crate::BitReader; +impl R { + #[doc = "Bits 0:25 - Reserved"] + #[inline(always)] + pub fn block_eof_cnt(&self) -> BLOCK_EOF_CNT_R { + BLOCK_EOF_CNT_R::new(self.bits & 0x03ff_ffff) + } + #[doc = "Bit 26 - Reserved"] + #[inline(always)] + pub fn dezigzag_ready(&self) -> DEZIGZAG_READY_R { + DEZIGZAG_READY_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Reserved"] + #[inline(always)] + pub fn de_frame_eof_check(&self) -> DE_FRAME_EOF_CHECK_R { + DE_FRAME_EOF_CHECK_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn de_dma2d_in_push(&self) -> DE_DMA2D_IN_PUSH_R { + DE_DMA2D_IN_PUSH_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DECODER_STATUS4") + .field( + "block_eof_cnt", + &format_args!("{}", self.block_eof_cnt().bits()), + ) + .field( + "dezigzag_ready", + &format_args!("{}", self.dezigzag_ready().bit()), + ) + .field( + "de_frame_eof_check", + &format_args!("{}", self.de_frame_eof_check().bit()), + ) + .field( + "de_dma2d_in_push", + &format_args!("{}", self.de_dma2d_in_push().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DECODER_STATUS4_SPEC; +impl crate::RegisterSpec for DECODER_STATUS4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`decoder_status4::R`](R) reader structure"] +impl crate::Readable for DECODER_STATUS4_SPEC {} +#[doc = "`reset()` method sets DECODER_STATUS4 to value 0"] +impl crate::Resettable for DECODER_STATUS4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/decoder_status5.rs b/esp32p4/src/jpeg/decoder_status5.rs new file mode 100644 index 0000000000..4245eb3b89 --- /dev/null +++ b/esp32p4/src/jpeg/decoder_status5.rs @@ -0,0 +1,122 @@ +#[doc = "Register `DECODER_STATUS5` reader"] +pub type R = crate::R; +#[doc = "Register `DECODER_STATUS5` writer"] +pub type W = crate::W; +#[doc = "Field `IDCT_HFM_DATA` reader - Reserved"] +pub type IDCT_HFM_DATA_R = crate::FieldReader; +#[doc = "Field `NS0` reader - Reserved"] +pub type NS0_R = crate::FieldReader; +#[doc = "Field `NS1` reader - Reserved"] +pub type NS1_R = crate::FieldReader; +#[doc = "Field `NS2` reader - Reserved"] +pub type NS2_R = crate::FieldReader; +#[doc = "Field `NS3` reader - Reserved"] +pub type NS3_R = crate::FieldReader; +#[doc = "Field `DATA_LAST_O` reader - Reserved"] +pub type DATA_LAST_O_R = crate::BitReader; +#[doc = "Field `RDN_RESULT` reader - redundant registers for jpeg"] +pub type RDN_RESULT_R = crate::BitReader; +#[doc = "Field `RDN_ENA` reader - redundant control registers for jpeg"] +pub type RDN_ENA_R = crate::BitReader; +#[doc = "Field `RDN_ENA` writer - redundant control registers for jpeg"] +pub type RDN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + pub fn idct_hfm_data(&self) -> IDCT_HFM_DATA_R { + IDCT_HFM_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Reserved"] + #[inline(always)] + pub fn ns0(&self) -> NS0_R { + NS0_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:21 - Reserved"] + #[inline(always)] + pub fn ns1(&self) -> NS1_R { + NS1_R::new(((self.bits >> 19) & 7) as u8) + } + #[doc = "Bits 22:24 - Reserved"] + #[inline(always)] + pub fn ns2(&self) -> NS2_R { + NS2_R::new(((self.bits >> 22) & 7) as u8) + } + #[doc = "Bits 25:27 - Reserved"] + #[inline(always)] + pub fn ns3(&self) -> NS3_R { + NS3_R::new(((self.bits >> 25) & 7) as u8) + } + #[doc = "Bit 28 - Reserved"] + #[inline(always)] + pub fn data_last_o(&self) -> DATA_LAST_O_R { + DATA_LAST_O_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - redundant registers for jpeg"] + #[inline(always)] + pub fn rdn_result(&self) -> RDN_RESULT_R { + RDN_RESULT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - redundant control registers for jpeg"] + #[inline(always)] + pub fn rdn_ena(&self) -> RDN_ENA_R { + RDN_ENA_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DECODER_STATUS5") + .field( + "idct_hfm_data", + &format_args!("{}", self.idct_hfm_data().bits()), + ) + .field("ns0", &format_args!("{}", self.ns0().bits())) + .field("ns1", &format_args!("{}", self.ns1().bits())) + .field("ns2", &format_args!("{}", self.ns2().bits())) + .field("ns3", &format_args!("{}", self.ns3().bits())) + .field("data_last_o", &format_args!("{}", self.data_last_o().bit())) + .field("rdn_result", &format_args!("{}", self.rdn_result().bit())) + .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - redundant control registers for jpeg"] + #[inline(always)] + #[must_use] + pub fn rdn_ena(&mut self) -> RDN_ENA_W { + RDN_ENA_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`decoder_status5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DECODER_STATUS5_SPEC; +impl crate::RegisterSpec for DECODER_STATUS5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`decoder_status5::R`](R) reader structure"] +impl crate::Readable for DECODER_STATUS5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`decoder_status5::W`](W) writer structure"] +impl crate::Writable for DECODER_STATUS5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DECODER_STATUS5 to value 0"] +impl crate::Resettable for DECODER_STATUS5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_codemin_ac0.rs b/esp32p4/src/jpeg/dht_codemin_ac0.rs new file mode 100644 index 0000000000..bb4abe992f --- /dev/null +++ b/esp32p4/src/jpeg/dht_codemin_ac0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_CODEMIN_AC0` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_CODEMIN_AC0` reader - write the minimum codeword of code length from 1~16 of ac0 table. The codeword is left shifted to the MSB position of a 16bit word"] +pub type DHT_CODEMIN_AC0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write the minimum codeword of code length from 1~16 of ac0 table. The codeword is left shifted to the MSB position of a 16bit word"] + #[inline(always)] + pub fn dht_codemin_ac0(&self) -> DHT_CODEMIN_AC0_R { + DHT_CODEMIN_AC0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_CODEMIN_AC0") + .field( + "dht_codemin_ac0", + &format_args!("{}", self.dht_codemin_ac0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_ac0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_CODEMIN_AC0_SPEC; +impl crate::RegisterSpec for DHT_CODEMIN_AC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_codemin_ac0::R`](R) reader structure"] +impl crate::Readable for DHT_CODEMIN_AC0_SPEC {} +#[doc = "`reset()` method sets DHT_CODEMIN_AC0 to value 0"] +impl crate::Resettable for DHT_CODEMIN_AC0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_codemin_ac1.rs b/esp32p4/src/jpeg/dht_codemin_ac1.rs new file mode 100644 index 0000000000..3766bc2054 --- /dev/null +++ b/esp32p4/src/jpeg/dht_codemin_ac1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_CODEMIN_AC1` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_CODEMIN_AC1` reader - write the minimum codeword of code length from 1~16 of ac1 table. The codeword is left shifted to the MSB position of a 16bit word"] +pub type DHT_CODEMIN_AC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write the minimum codeword of code length from 1~16 of ac1 table. The codeword is left shifted to the MSB position of a 16bit word"] + #[inline(always)] + pub fn dht_codemin_ac1(&self) -> DHT_CODEMIN_AC1_R { + DHT_CODEMIN_AC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_CODEMIN_AC1") + .field( + "dht_codemin_ac1", + &format_args!("{}", self.dht_codemin_ac1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_ac1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_CODEMIN_AC1_SPEC; +impl crate::RegisterSpec for DHT_CODEMIN_AC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_codemin_ac1::R`](R) reader structure"] +impl crate::Readable for DHT_CODEMIN_AC1_SPEC {} +#[doc = "`reset()` method sets DHT_CODEMIN_AC1 to value 0"] +impl crate::Resettable for DHT_CODEMIN_AC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_codemin_dc0.rs b/esp32p4/src/jpeg/dht_codemin_dc0.rs new file mode 100644 index 0000000000..7f7a1855ba --- /dev/null +++ b/esp32p4/src/jpeg/dht_codemin_dc0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_CODEMIN_DC0` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_CODEMIN_DC0` reader - write the minimum codeword of code length from 1~16 of dc0 table. The codeword is left shifted to the MSB position of a 16bit word"] +pub type DHT_CODEMIN_DC0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write the minimum codeword of code length from 1~16 of dc0 table. The codeword is left shifted to the MSB position of a 16bit word"] + #[inline(always)] + pub fn dht_codemin_dc0(&self) -> DHT_CODEMIN_DC0_R { + DHT_CODEMIN_DC0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_CODEMIN_DC0") + .field( + "dht_codemin_dc0", + &format_args!("{}", self.dht_codemin_dc0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_dc0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_CODEMIN_DC0_SPEC; +impl crate::RegisterSpec for DHT_CODEMIN_DC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_codemin_dc0::R`](R) reader structure"] +impl crate::Readable for DHT_CODEMIN_DC0_SPEC {} +#[doc = "`reset()` method sets DHT_CODEMIN_DC0 to value 0"] +impl crate::Resettable for DHT_CODEMIN_DC0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_codemin_dc1.rs b/esp32p4/src/jpeg/dht_codemin_dc1.rs new file mode 100644 index 0000000000..72d5183164 --- /dev/null +++ b/esp32p4/src/jpeg/dht_codemin_dc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_CODEMIN_DC1` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_CODEMIN_DC1` reader - write the minimum codeword of code length from 1~16 of dc1 table. The codeword is left shifted to the MSB position of a 16bit word"] +pub type DHT_CODEMIN_DC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write the minimum codeword of code length from 1~16 of dc1 table. The codeword is left shifted to the MSB position of a 16bit word"] + #[inline(always)] + pub fn dht_codemin_dc1(&self) -> DHT_CODEMIN_DC1_R { + DHT_CODEMIN_DC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_CODEMIN_DC1") + .field( + "dht_codemin_dc1", + &format_args!("{}", self.dht_codemin_dc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_dc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_CODEMIN_DC1_SPEC; +impl crate::RegisterSpec for DHT_CODEMIN_DC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_codemin_dc1::R`](R) reader structure"] +impl crate::Readable for DHT_CODEMIN_DC1_SPEC {} +#[doc = "`reset()` method sets DHT_CODEMIN_DC1 to value 0"] +impl crate::Resettable for DHT_CODEMIN_DC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_info.rs b/esp32p4/src/jpeg/dht_info.rs new file mode 100644 index 0000000000..66b2056ebe --- /dev/null +++ b/esp32p4/src/jpeg/dht_info.rs @@ -0,0 +1,111 @@ +#[doc = "Register `DHT_INFO` reader"] +pub type R = crate::R; +#[doc = "Register `DHT_INFO` writer"] +pub type W = crate::W; +#[doc = "Field `DC0_DHT_ID` reader - configure dht dc table 0 id"] +pub type DC0_DHT_ID_R = crate::FieldReader; +#[doc = "Field `DC0_DHT_ID` writer - configure dht dc table 0 id"] +pub type DC0_DHT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DC1_DHT_ID` reader - configure dht dc table 1 id"] +pub type DC1_DHT_ID_R = crate::FieldReader; +#[doc = "Field `DC1_DHT_ID` writer - configure dht dc table 1 id"] +pub type DC1_DHT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `AC0_DHT_ID` reader - configure dht ac table 0 id"] +pub type AC0_DHT_ID_R = crate::FieldReader; +#[doc = "Field `AC0_DHT_ID` writer - configure dht ac table 0 id"] +pub type AC0_DHT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `AC1_DHT_ID` reader - configure dht ac table 1 id"] +pub type AC1_DHT_ID_R = crate::FieldReader; +#[doc = "Field `AC1_DHT_ID` writer - configure dht ac table 1 id"] +pub type AC1_DHT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - configure dht dc table 0 id"] + #[inline(always)] + pub fn dc0_dht_id(&self) -> DC0_DHT_ID_R { + DC0_DHT_ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - configure dht dc table 1 id"] + #[inline(always)] + pub fn dc1_dht_id(&self) -> DC1_DHT_ID_R { + DC1_DHT_ID_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - configure dht ac table 0 id"] + #[inline(always)] + pub fn ac0_dht_id(&self) -> AC0_DHT_ID_R { + AC0_DHT_ID_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - configure dht ac table 1 id"] + #[inline(always)] + pub fn ac1_dht_id(&self) -> AC1_DHT_ID_R { + AC1_DHT_ID_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_INFO") + .field("dc0_dht_id", &format_args!("{}", self.dc0_dht_id().bits())) + .field("dc1_dht_id", &format_args!("{}", self.dc1_dht_id().bits())) + .field("ac0_dht_id", &format_args!("{}", self.ac0_dht_id().bits())) + .field("ac1_dht_id", &format_args!("{}", self.ac1_dht_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - configure dht dc table 0 id"] + #[inline(always)] + #[must_use] + pub fn dc0_dht_id(&mut self) -> DC0_DHT_ID_W { + DC0_DHT_ID_W::new(self, 0) + } + #[doc = "Bits 4:7 - configure dht dc table 1 id"] + #[inline(always)] + #[must_use] + pub fn dc1_dht_id(&mut self) -> DC1_DHT_ID_W { + DC1_DHT_ID_W::new(self, 4) + } + #[doc = "Bits 8:11 - configure dht ac table 0 id"] + #[inline(always)] + #[must_use] + pub fn ac0_dht_id(&mut self) -> AC0_DHT_ID_W { + AC0_DHT_ID_W::new(self, 8) + } + #[doc = "Bits 12:15 - configure dht ac table 1 id"] + #[inline(always)] + #[must_use] + pub fn ac1_dht_id(&mut self) -> AC1_DHT_ID_W { + AC1_DHT_ID_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_info::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dht_info::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_INFO_SPEC; +impl crate::RegisterSpec for DHT_INFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_info::R`](R) reader structure"] +impl crate::Readable for DHT_INFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dht_info::W`](W) writer structure"] +impl crate::Writable for DHT_INFO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DHT_INFO to value 0x1010"] +impl crate::Resettable for DHT_INFO_SPEC { + const RESET_VALUE: Self::Ux = 0x1010; +} diff --git a/esp32p4/src/jpeg/dht_totlen_ac0.rs b/esp32p4/src/jpeg/dht_totlen_ac0.rs new file mode 100644 index 0000000000..97fcdc55d7 --- /dev/null +++ b/esp32p4/src/jpeg/dht_totlen_ac0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_TOTLEN_AC0` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_TOTLEN_AC0` reader - write the numbers of 1~n codeword length sum from 1~16 of ac0 table"] +pub type DHT_TOTLEN_AC0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write the numbers of 1~n codeword length sum from 1~16 of ac0 table"] + #[inline(always)] + pub fn dht_totlen_ac0(&self) -> DHT_TOTLEN_AC0_R { + DHT_TOTLEN_AC0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_TOTLEN_AC0") + .field( + "dht_totlen_ac0", + &format_args!("{}", self.dht_totlen_ac0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_ac0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_TOTLEN_AC0_SPEC; +impl crate::RegisterSpec for DHT_TOTLEN_AC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_totlen_ac0::R`](R) reader structure"] +impl crate::Readable for DHT_TOTLEN_AC0_SPEC {} +#[doc = "`reset()` method sets DHT_TOTLEN_AC0 to value 0"] +impl crate::Resettable for DHT_TOTLEN_AC0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_totlen_ac1.rs b/esp32p4/src/jpeg/dht_totlen_ac1.rs new file mode 100644 index 0000000000..21e98eabe5 --- /dev/null +++ b/esp32p4/src/jpeg/dht_totlen_ac1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_TOTLEN_AC1` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_TOTLEN_AC1` reader - write the numbers of 1~n codeword length sum from 1~16 of ac1 table"] +pub type DHT_TOTLEN_AC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write the numbers of 1~n codeword length sum from 1~16 of ac1 table"] + #[inline(always)] + pub fn dht_totlen_ac1(&self) -> DHT_TOTLEN_AC1_R { + DHT_TOTLEN_AC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_TOTLEN_AC1") + .field( + "dht_totlen_ac1", + &format_args!("{}", self.dht_totlen_ac1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_ac1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_TOTLEN_AC1_SPEC; +impl crate::RegisterSpec for DHT_TOTLEN_AC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_totlen_ac1::R`](R) reader structure"] +impl crate::Readable for DHT_TOTLEN_AC1_SPEC {} +#[doc = "`reset()` method sets DHT_TOTLEN_AC1 to value 0"] +impl crate::Resettable for DHT_TOTLEN_AC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_totlen_dc0.rs b/esp32p4/src/jpeg/dht_totlen_dc0.rs new file mode 100644 index 0000000000..fbd569ddde --- /dev/null +++ b/esp32p4/src/jpeg/dht_totlen_dc0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_TOTLEN_DC0` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_TOTLEN_DC0` reader - write the numbers of 1~n codeword length sum from 1~16 of dc0 table"] +pub type DHT_TOTLEN_DC0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write the numbers of 1~n codeword length sum from 1~16 of dc0 table"] + #[inline(always)] + pub fn dht_totlen_dc0(&self) -> DHT_TOTLEN_DC0_R { + DHT_TOTLEN_DC0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_TOTLEN_DC0") + .field( + "dht_totlen_dc0", + &format_args!("{}", self.dht_totlen_dc0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_dc0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_TOTLEN_DC0_SPEC; +impl crate::RegisterSpec for DHT_TOTLEN_DC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_totlen_dc0::R`](R) reader structure"] +impl crate::Readable for DHT_TOTLEN_DC0_SPEC {} +#[doc = "`reset()` method sets DHT_TOTLEN_DC0 to value 0"] +impl crate::Resettable for DHT_TOTLEN_DC0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_totlen_dc1.rs b/esp32p4/src/jpeg/dht_totlen_dc1.rs new file mode 100644 index 0000000000..3a83b3d505 --- /dev/null +++ b/esp32p4/src/jpeg/dht_totlen_dc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_TOTLEN_DC1` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_TOTLEN_DC1` reader - write the numbers of 1~n codeword length sum from 1~16 of dc1 table"] +pub type DHT_TOTLEN_DC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write the numbers of 1~n codeword length sum from 1~16 of dc1 table"] + #[inline(always)] + pub fn dht_totlen_dc1(&self) -> DHT_TOTLEN_DC1_R { + DHT_TOTLEN_DC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_TOTLEN_DC1") + .field( + "dht_totlen_dc1", + &format_args!("{}", self.dht_totlen_dc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_dc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_TOTLEN_DC1_SPEC; +impl crate::RegisterSpec for DHT_TOTLEN_DC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_totlen_dc1::R`](R) reader structure"] +impl crate::Readable for DHT_TOTLEN_DC1_SPEC {} +#[doc = "`reset()` method sets DHT_TOTLEN_DC1 to value 0"] +impl crate::Resettable for DHT_TOTLEN_DC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_val_ac0.rs b/esp32p4/src/jpeg/dht_val_ac0.rs new file mode 100644 index 0000000000..dc9f5c49d7 --- /dev/null +++ b/esp32p4/src/jpeg/dht_val_ac0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_VAl_AC0` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_VAL_AC0` reader - write codeword corresponding huffman values of ac0 table"] +pub type DHT_VAL_AC0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write codeword corresponding huffman values of ac0 table"] + #[inline(always)] + pub fn dht_val_ac0(&self) -> DHT_VAL_AC0_R { + DHT_VAL_AC0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_VAl_AC0") + .field( + "dht_val_ac0", + &format_args!("{}", self.dht_val_ac0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_ac0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_VAL_AC0_SPEC; +impl crate::RegisterSpec for DHT_VAL_AC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_val_ac0::R`](R) reader structure"] +impl crate::Readable for DHT_VAL_AC0_SPEC {} +#[doc = "`reset()` method sets DHT_VAl_AC0 to value 0"] +impl crate::Resettable for DHT_VAL_AC0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_val_ac1.rs b/esp32p4/src/jpeg/dht_val_ac1.rs new file mode 100644 index 0000000000..a8df2bbea3 --- /dev/null +++ b/esp32p4/src/jpeg/dht_val_ac1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_VAl_AC1` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_VAL_AC1` reader - write codeword corresponding huffman values of ac1 table"] +pub type DHT_VAL_AC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write codeword corresponding huffman values of ac1 table"] + #[inline(always)] + pub fn dht_val_ac1(&self) -> DHT_VAL_AC1_R { + DHT_VAL_AC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_VAl_AC1") + .field( + "dht_val_ac1", + &format_args!("{}", self.dht_val_ac1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_ac1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_VAL_AC1_SPEC; +impl crate::RegisterSpec for DHT_VAL_AC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_val_ac1::R`](R) reader structure"] +impl crate::Readable for DHT_VAL_AC1_SPEC {} +#[doc = "`reset()` method sets DHT_VAl_AC1 to value 0"] +impl crate::Resettable for DHT_VAL_AC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_val_dc0.rs b/esp32p4/src/jpeg/dht_val_dc0.rs new file mode 100644 index 0000000000..d58aff3d31 --- /dev/null +++ b/esp32p4/src/jpeg/dht_val_dc0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_VAl_DC0` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_VAL_DC0` reader - write codeword corresponding huffman values of dc0 table"] +pub type DHT_VAL_DC0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write codeword corresponding huffman values of dc0 table"] + #[inline(always)] + pub fn dht_val_dc0(&self) -> DHT_VAL_DC0_R { + DHT_VAL_DC0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_VAl_DC0") + .field( + "dht_val_dc0", + &format_args!("{}", self.dht_val_dc0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_dc0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_VAL_DC0_SPEC; +impl crate::RegisterSpec for DHT_VAL_DC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_val_dc0::R`](R) reader structure"] +impl crate::Readable for DHT_VAL_DC0_SPEC {} +#[doc = "`reset()` method sets DHT_VAl_DC0 to value 0"] +impl crate::Resettable for DHT_VAL_DC0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dht_val_dc1.rs b/esp32p4/src/jpeg/dht_val_dc1.rs new file mode 100644 index 0000000000..4916b418ef --- /dev/null +++ b/esp32p4/src/jpeg/dht_val_dc1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DHT_VAl_DC1` reader"] +pub type R = crate::R; +#[doc = "Field `DHT_VAL_DC1` reader - write codeword corresponding huffman values of dc1 table"] +pub type DHT_VAL_DC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write codeword corresponding huffman values of dc1 table"] + #[inline(always)] + pub fn dht_val_dc1(&self) -> DHT_VAL_DC1_R { + DHT_VAL_DC1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DHT_VAl_DC1") + .field( + "dht_val_dc1", + &format_args!("{}", self.dht_val_dc1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_dc1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHT_VAL_DC1_SPEC; +impl crate::RegisterSpec for DHT_VAL_DC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dht_val_dc1::R`](R) reader structure"] +impl crate::Readable for DHT_VAL_DC1_SPEC {} +#[doc = "`reset()` method sets DHT_VAl_DC1 to value 0"] +impl crate::Resettable for DHT_VAL_DC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/dqt_info.rs b/esp32p4/src/jpeg/dqt_info.rs new file mode 100644 index 0000000000..838ae6eb12 --- /dev/null +++ b/esp32p4/src/jpeg/dqt_info.rs @@ -0,0 +1,123 @@ +#[doc = "Register `DQT_INFO` reader"] +pub type R = crate::R; +#[doc = "Register `DQT_INFO` writer"] +pub type W = crate::W; +#[doc = "Field `T0_DQT_INFO` reader - Configure dqt table0's quantization coefficient precision in bit\\[7:4\\], configure dqt table0's table id in bit\\[3:0\\]"] +pub type T0_DQT_INFO_R = crate::FieldReader; +#[doc = "Field `T0_DQT_INFO` writer - Configure dqt table0's quantization coefficient precision in bit\\[7:4\\], configure dqt table0's table id in bit\\[3:0\\]"] +pub type T0_DQT_INFO_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `T1_DQT_INFO` reader - Configure dqt table1's quantization coefficient precision in bit\\[7:4\\], configure dqt table1's table id in bit\\[3:0\\]"] +pub type T1_DQT_INFO_R = crate::FieldReader; +#[doc = "Field `T1_DQT_INFO` writer - Configure dqt table1's quantization coefficient precision in bit\\[7:4\\], configure dqt table1's table id in bit\\[3:0\\]"] +pub type T1_DQT_INFO_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `T2_DQT_INFO` reader - Configure dqt table2's quantization coefficient precision in bit\\[7:4\\], configure dqt table2's table id in bit\\[3:0\\]"] +pub type T2_DQT_INFO_R = crate::FieldReader; +#[doc = "Field `T2_DQT_INFO` writer - Configure dqt table2's quantization coefficient precision in bit\\[7:4\\], configure dqt table2's table id in bit\\[3:0\\]"] +pub type T2_DQT_INFO_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `T3_DQT_INFO` reader - Configure dqt table3's quantization coefficient precision in bit\\[7:4\\], configure dqt table3's table id in bit\\[3:0\\]"] +pub type T3_DQT_INFO_R = crate::FieldReader; +#[doc = "Field `T3_DQT_INFO` writer - Configure dqt table3's quantization coefficient precision in bit\\[7:4\\], configure dqt table3's table id in bit\\[3:0\\]"] +pub type T3_DQT_INFO_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configure dqt table0's quantization coefficient precision in bit\\[7:4\\], configure dqt table0's table id in bit\\[3:0\\]"] + #[inline(always)] + pub fn t0_dqt_info(&self) -> T0_DQT_INFO_R { + T0_DQT_INFO_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Configure dqt table1's quantization coefficient precision in bit\\[7:4\\], configure dqt table1's table id in bit\\[3:0\\]"] + #[inline(always)] + pub fn t1_dqt_info(&self) -> T1_DQT_INFO_R { + T1_DQT_INFO_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Configure dqt table2's quantization coefficient precision in bit\\[7:4\\], configure dqt table2's table id in bit\\[3:0\\]"] + #[inline(always)] + pub fn t2_dqt_info(&self) -> T2_DQT_INFO_R { + T2_DQT_INFO_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Configure dqt table3's quantization coefficient precision in bit\\[7:4\\], configure dqt table3's table id in bit\\[3:0\\]"] + #[inline(always)] + pub fn t3_dqt_info(&self) -> T3_DQT_INFO_R { + T3_DQT_INFO_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DQT_INFO") + .field( + "t0_dqt_info", + &format_args!("{}", self.t0_dqt_info().bits()), + ) + .field( + "t1_dqt_info", + &format_args!("{}", self.t1_dqt_info().bits()), + ) + .field( + "t2_dqt_info", + &format_args!("{}", self.t2_dqt_info().bits()), + ) + .field( + "t3_dqt_info", + &format_args!("{}", self.t3_dqt_info().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configure dqt table0's quantization coefficient precision in bit\\[7:4\\], configure dqt table0's table id in bit\\[3:0\\]"] + #[inline(always)] + #[must_use] + pub fn t0_dqt_info(&mut self) -> T0_DQT_INFO_W { + T0_DQT_INFO_W::new(self, 0) + } + #[doc = "Bits 8:15 - Configure dqt table1's quantization coefficient precision in bit\\[7:4\\], configure dqt table1's table id in bit\\[3:0\\]"] + #[inline(always)] + #[must_use] + pub fn t1_dqt_info(&mut self) -> T1_DQT_INFO_W { + T1_DQT_INFO_W::new(self, 8) + } + #[doc = "Bits 16:23 - Configure dqt table2's quantization coefficient precision in bit\\[7:4\\], configure dqt table2's table id in bit\\[3:0\\]"] + #[inline(always)] + #[must_use] + pub fn t2_dqt_info(&mut self) -> T2_DQT_INFO_W { + T2_DQT_INFO_W::new(self, 16) + } + #[doc = "Bits 24:31 - Configure dqt table3's quantization coefficient precision in bit\\[7:4\\], configure dqt table3's table id in bit\\[3:0\\]"] + #[inline(always)] + #[must_use] + pub fn t3_dqt_info(&mut self) -> T3_DQT_INFO_W { + T3_DQT_INFO_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dqt_info::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dqt_info::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DQT_INFO_SPEC; +impl crate::RegisterSpec for DQT_INFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dqt_info::R`](R) reader structure"] +impl crate::Readable for DQT_INFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dqt_info::W`](W) writer structure"] +impl crate::Writable for DQT_INFO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DQT_INFO to value 0x0302_0100"] +impl crate::Resettable for DQT_INFO_SPEC { + const RESET_VALUE: Self::Ux = 0x0302_0100; +} diff --git a/esp32p4/src/jpeg/eco_high.rs b/esp32p4/src/jpeg/eco_high.rs new file mode 100644 index 0000000000..9cc8125c47 --- /dev/null +++ b/esp32p4/src/jpeg/eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_HIGH` reader - redundant registers for jpeg"] +pub type RDN_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_HIGH` writer - redundant registers for jpeg"] +pub type RDN_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - redundant registers for jpeg"] + #[inline(always)] + pub fn rdn_eco_high(&self) -> RDN_ECO_HIGH_R { + RDN_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_HIGH") + .field( + "rdn_eco_high", + &format_args!("{}", self.rdn_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - redundant registers for jpeg"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_high(&mut self) -> RDN_ECO_HIGH_W { + RDN_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_HIGH_SPEC; +impl crate::RegisterSpec for ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_high::R`](R) reader structure"] +impl crate::Readable for ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_high::W`](W) writer structure"] +impl crate::Writable for ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/jpeg/eco_low.rs b/esp32p4/src/jpeg/eco_low.rs new file mode 100644 index 0000000000..5a90c9ae43 --- /dev/null +++ b/esp32p4/src/jpeg/eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_LOW` reader - redundant registers for jpeg"] +pub type RDN_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_LOW` writer - redundant registers for jpeg"] +pub type RDN_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - redundant registers for jpeg"] + #[inline(always)] + pub fn rdn_eco_low(&self) -> RDN_ECO_LOW_R { + RDN_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_LOW") + .field( + "rdn_eco_low", + &format_args!("{}", self.rdn_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - redundant registers for jpeg"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_low(&mut self) -> RDN_ECO_LOW_W { + RDN_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_LOW_SPEC; +impl crate::RegisterSpec for ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_low::R`](R) reader structure"] +impl crate::Readable for ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_low::W`](W) writer structure"] +impl crate::Writable for ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_LOW to value 0"] +impl crate::Resettable for ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/int_clr.rs b/esp32p4/src/jpeg/int_clr.rs new file mode 100644 index 0000000000..5f1eddd50e --- /dev/null +++ b/esp32p4/src/jpeg/int_clr.rs @@ -0,0 +1,236 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DONE_INT_CLR` writer - This clear interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RLE_PARALLEL_ERR_INT_CLR` writer - The clear interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CID_ERR_INT_CLR` writer - The clear interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DHT_DC_ID_ERR_INT_CLR` writer - The clear interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DHT_AC_ID_ERR_INT_CLR` writer - The clear interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DQT_ID_ERR_INT_CLR` writer - The clear interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_UXP_ERR_INT_CLR` writer - The clear interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_CHECK_NONE_ERR_INT_CLR` writer - The clear interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_CHECK_POS_ERR_INT_CLR` writer - The clear interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_INT_CLR` writer - The clear interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_COLOR_MODE_ERR_INT_CLR` writer - The clear interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCT_DONE_INT_CLR` writer - The clear interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BS_LAST_BLOCK_EOF_INT_CLR` writer - The clear interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_CLR` writer - The clear interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_CHECK_POS_ERR_INT_CLR` writer - The clear interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UXP_DET_INT_CLR` writer - The clear interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_ERR_INT_CLR` writer - The clear interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_LACK_INT_CLR` writer - The clear interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_ERR_INT_CLR` writer - The clear interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_LACK_INT_CLR` writer - The clear interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOS_UNMATCH_ERR_INT_CLR` writer - The clear interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MARKER_ERR_FST_SCAN_INT_CLR` writer - The clear interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_CLR` writer - The clear interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UNDET_INT_CLR` writer - The clear interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DECODE_TIMEOUT_INT_CLR` writer - The clear interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - This clear interrupt bit turns to high level when JPEG finishes encoding a picture.."] + #[inline(always)] + #[must_use] + pub fn done_int_clr(&mut self) -> DONE_INT_CLR_W { + DONE_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - The clear interrupt bit to sign that rle parallel error when decoding."] + #[inline(always)] + #[must_use] + pub fn rle_parallel_err_int_clr(&mut self) -> RLE_PARALLEL_ERR_INT_CLR_W { + RLE_PARALLEL_ERR_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - The clear interrupt bit to sign that scan id check with component fails when decoding."] + #[inline(always)] + #[must_use] + pub fn cid_err_int_clr(&mut self) -> CID_ERR_INT_CLR_W { + CID_ERR_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - The clear interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] + #[inline(always)] + #[must_use] + pub fn c_dht_dc_id_err_int_clr(&mut self) -> C_DHT_DC_ID_ERR_INT_CLR_W { + C_DHT_DC_ID_ERR_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - The clear interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] + #[inline(always)] + #[must_use] + pub fn c_dht_ac_id_err_int_clr(&mut self) -> C_DHT_AC_ID_ERR_INT_CLR_W { + C_DHT_AC_ID_ERR_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - The clear interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] + #[inline(always)] + #[must_use] + pub fn c_dqt_id_err_int_clr(&mut self) -> C_DQT_ID_ERR_INT_CLR_W { + C_DQT_ID_ERR_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - The clear interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] + #[inline(always)] + #[must_use] + pub fn rst_uxp_err_int_clr(&mut self) -> RST_UXP_ERR_INT_CLR_W { + RST_UXP_ERR_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - The clear interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] + #[inline(always)] + #[must_use] + pub fn rst_check_none_err_int_clr(&mut self) -> RST_CHECK_NONE_ERR_INT_CLR_W { + RST_CHECK_NONE_ERR_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - The clear interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] + #[inline(always)] + #[must_use] + pub fn rst_check_pos_err_int_clr(&mut self) -> RST_CHECK_POS_ERR_INT_CLR_W { + RST_CHECK_POS_ERR_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - The clear interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] + #[inline(always)] + #[must_use] + pub fn out_eof_int_clr(&mut self) -> OUT_EOF_INT_CLR_W { + OUT_EOF_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - The clear interrupt bit to sign that the selected source color mode is not supported."] + #[inline(always)] + #[must_use] + pub fn sr_color_mode_err_int_clr(&mut self) -> SR_COLOR_MODE_ERR_INT_CLR_W { + SR_COLOR_MODE_ERR_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - The clear interrupt bit to sign that one dct calculation is finished."] + #[inline(always)] + #[must_use] + pub fn dct_done_int_clr(&mut self) -> DCT_DONE_INT_CLR_W { + DCT_DONE_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - The clear interrupt bit to sign that the coding process for last block is finished."] + #[inline(always)] + #[must_use] + pub fn bs_last_block_eof_int_clr(&mut self) -> BS_LAST_BLOCK_EOF_INT_CLR_W { + BS_LAST_BLOCK_EOF_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - The clear interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] + #[inline(always)] + #[must_use] + pub fn scan_check_none_err_int_clr(&mut self) -> SCAN_CHECK_NONE_ERR_INT_CLR_W { + SCAN_CHECK_NONE_ERR_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - The clear interrupt bit to sign that SOS header marker position wrong when decoding."] + #[inline(always)] + #[must_use] + pub fn scan_check_pos_err_int_clr(&mut self) -> SCAN_CHECK_POS_ERR_INT_CLR_W { + SCAN_CHECK_POS_ERR_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - The clear interrupt bit to sign that unsupported header marker is detected when decoding."] + #[inline(always)] + #[must_use] + pub fn uxp_det_int_clr(&mut self) -> UXP_DET_INT_CLR_W { + UXP_DET_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - The clear interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] + #[inline(always)] + #[must_use] + pub fn en_frame_eof_err_int_clr(&mut self) -> EN_FRAME_EOF_ERR_INT_CLR_W { + EN_FRAME_EOF_ERR_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - The clear interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] + #[inline(always)] + #[must_use] + pub fn en_frame_eof_lack_int_clr(&mut self) -> EN_FRAME_EOF_LACK_INT_CLR_W { + EN_FRAME_EOF_LACK_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - The clear interrupt bit to sign that decoded blocks are smaller than expected when decoding."] + #[inline(always)] + #[must_use] + pub fn de_frame_eof_err_int_clr(&mut self) -> DE_FRAME_EOF_ERR_INT_CLR_W { + DE_FRAME_EOF_ERR_INT_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - The clear interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] + #[inline(always)] + #[must_use] + pub fn de_frame_eof_lack_int_clr(&mut self) -> DE_FRAME_EOF_LACK_INT_CLR_W { + DE_FRAME_EOF_LACK_INT_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - The clear interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] + #[inline(always)] + #[must_use] + pub fn sos_unmatch_err_int_clr(&mut self) -> SOS_UNMATCH_ERR_INT_CLR_W { + SOS_UNMATCH_ERR_INT_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - The clear interrupt bit to sign that the first scan has header marker error when decoding."] + #[inline(always)] + #[must_use] + pub fn marker_err_fst_scan_int_clr(&mut self) -> MARKER_ERR_FST_SCAN_INT_CLR_W { + MARKER_ERR_FST_SCAN_INT_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - The clear interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] + #[inline(always)] + #[must_use] + pub fn marker_err_other_scan_int_clr( + &mut self, + ) -> MARKER_ERR_OTHER_SCAN_INT_CLR_W { + MARKER_ERR_OTHER_SCAN_INT_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - The clear interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] + #[inline(always)] + #[must_use] + pub fn undet_int_clr(&mut self) -> UNDET_INT_CLR_W { + UNDET_INT_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - The clear interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] + #[inline(always)] + #[must_use] + pub fn decode_timeout_int_clr(&mut self) -> DECODE_TIMEOUT_INT_CLR_W { + DECODE_TIMEOUT_INT_CLR_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear registers\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/int_ena.rs b/esp32p4/src/jpeg/int_ena.rs new file mode 100644 index 0000000000..1fc4903136 --- /dev/null +++ b/esp32p4/src/jpeg/int_ena.rs @@ -0,0 +1,524 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `DONE_INT_ENA` reader - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `DONE_INT_ENA` writer - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RLE_PARALLEL_ERR_INT_ENA` reader - The enable interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `RLE_PARALLEL_ERR_INT_ENA` writer - The enable interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CID_ERR_INT_ENA` reader - The enable interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `CID_ERR_INT_ENA` writer - The enable interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DHT_DC_ID_ERR_INT_ENA` reader - The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `C_DHT_DC_ID_ERR_INT_ENA` writer - The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DHT_AC_ID_ERR_INT_ENA` reader - The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `C_DHT_AC_ID_ERR_INT_ENA` writer - The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DQT_ID_ERR_INT_ENA` reader - The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `C_DQT_ID_ERR_INT_ENA` writer - The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_UXP_ERR_INT_ENA` reader - The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `RST_UXP_ERR_INT_ENA` writer - The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_CHECK_NONE_ERR_INT_ENA` reader - The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `RST_CHECK_NONE_ERR_INT_ENA` writer - The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_CHECK_POS_ERR_INT_ENA` reader - The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `RST_CHECK_POS_ERR_INT_ENA` writer - The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_INT_ENA` reader - The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUT_EOF_INT_ENA` writer - The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_COLOR_MODE_ERR_INT_ENA` reader - The enable interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SR_COLOR_MODE_ERR_INT_ENA` writer - The enable interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCT_DONE_INT_ENA` reader - The enable interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `DCT_DONE_INT_ENA` writer - The enable interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BS_LAST_BLOCK_EOF_INT_ENA` reader - The enable interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_INT_ENA_R = crate::BitReader; +#[doc = "Field `BS_LAST_BLOCK_EOF_INT_ENA` writer - The enable interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_ENA` reader - The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_ENA` writer - The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_CHECK_POS_ERR_INT_ENA` reader - The enable interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_POS_ERR_INT_ENA` writer - The enable interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UXP_DET_INT_ENA` reader - The enable interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_INT_ENA_R = crate::BitReader; +#[doc = "Field `UXP_DET_INT_ENA` writer - The enable interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_ERR_INT_ENA` reader - The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_ERR_INT_ENA` writer - The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_LACK_INT_ENA` reader - The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_INT_ENA_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_LACK_INT_ENA` writer - The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_ERR_INT_ENA` reader - The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_ERR_INT_ENA` writer - The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_LACK_INT_ENA` reader - The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_INT_ENA_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_LACK_INT_ENA` writer - The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOS_UNMATCH_ERR_INT_ENA` reader - The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SOS_UNMATCH_ERR_INT_ENA` writer - The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MARKER_ERR_FST_SCAN_INT_ENA` reader - The enable interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_INT_ENA_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_FST_SCAN_INT_ENA` writer - The enable interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_ENA` reader - The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_INT_ENA_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_ENA` writer - The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UNDET_INT_ENA` reader - The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_INT_ENA_R = crate::BitReader; +#[doc = "Field `UNDET_INT_ENA` writer - The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DECODE_TIMEOUT_INT_ENA` reader - The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `DECODE_TIMEOUT_INT_ENA` writer - The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.."] + #[inline(always)] + pub fn done_int_ena(&self) -> DONE_INT_ENA_R { + DONE_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The enable interrupt bit to sign that rle parallel error when decoding."] + #[inline(always)] + pub fn rle_parallel_err_int_ena(&self) -> RLE_PARALLEL_ERR_INT_ENA_R { + RLE_PARALLEL_ERR_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The enable interrupt bit to sign that scan id check with component fails when decoding."] + #[inline(always)] + pub fn cid_err_int_ena(&self) -> CID_ERR_INT_ENA_R { + CID_ERR_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] + #[inline(always)] + pub fn c_dht_dc_id_err_int_ena(&self) -> C_DHT_DC_ID_ERR_INT_ENA_R { + C_DHT_DC_ID_ERR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] + #[inline(always)] + pub fn c_dht_ac_id_err_int_ena(&self) -> C_DHT_AC_ID_ERR_INT_ENA_R { + C_DHT_AC_ID_ERR_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] + #[inline(always)] + pub fn c_dqt_id_err_int_ena(&self) -> C_DQT_ID_ERR_INT_ENA_R { + C_DQT_ID_ERR_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] + #[inline(always)] + pub fn rst_uxp_err_int_ena(&self) -> RST_UXP_ERR_INT_ENA_R { + RST_UXP_ERR_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] + #[inline(always)] + pub fn rst_check_none_err_int_ena(&self) -> RST_CHECK_NONE_ERR_INT_ENA_R { + RST_CHECK_NONE_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] + #[inline(always)] + pub fn rst_check_pos_err_int_ena(&self) -> RST_CHECK_POS_ERR_INT_ENA_R { + RST_CHECK_POS_ERR_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] + #[inline(always)] + pub fn out_eof_int_ena(&self) -> OUT_EOF_INT_ENA_R { + OUT_EOF_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The enable interrupt bit to sign that the selected source color mode is not supported."] + #[inline(always)] + pub fn sr_color_mode_err_int_ena(&self) -> SR_COLOR_MODE_ERR_INT_ENA_R { + SR_COLOR_MODE_ERR_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The enable interrupt bit to sign that one dct calculation is finished."] + #[inline(always)] + pub fn dct_done_int_ena(&self) -> DCT_DONE_INT_ENA_R { + DCT_DONE_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The enable interrupt bit to sign that the coding process for last block is finished."] + #[inline(always)] + pub fn bs_last_block_eof_int_ena(&self) -> BS_LAST_BLOCK_EOF_INT_ENA_R { + BS_LAST_BLOCK_EOF_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] + #[inline(always)] + pub fn scan_check_none_err_int_ena(&self) -> SCAN_CHECK_NONE_ERR_INT_ENA_R { + SCAN_CHECK_NONE_ERR_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The enable interrupt bit to sign that SOS header marker position wrong when decoding."] + #[inline(always)] + pub fn scan_check_pos_err_int_ena(&self) -> SCAN_CHECK_POS_ERR_INT_ENA_R { + SCAN_CHECK_POS_ERR_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The enable interrupt bit to sign that unsupported header marker is detected when decoding."] + #[inline(always)] + pub fn uxp_det_int_ena(&self) -> UXP_DET_INT_ENA_R { + UXP_DET_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] + #[inline(always)] + pub fn en_frame_eof_err_int_ena(&self) -> EN_FRAME_EOF_ERR_INT_ENA_R { + EN_FRAME_EOF_ERR_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] + #[inline(always)] + pub fn en_frame_eof_lack_int_ena(&self) -> EN_FRAME_EOF_LACK_INT_ENA_R { + EN_FRAME_EOF_LACK_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding."] + #[inline(always)] + pub fn de_frame_eof_err_int_ena(&self) -> DE_FRAME_EOF_ERR_INT_ENA_R { + DE_FRAME_EOF_ERR_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] + #[inline(always)] + pub fn de_frame_eof_lack_int_ena(&self) -> DE_FRAME_EOF_LACK_INT_ENA_R { + DE_FRAME_EOF_LACK_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] + #[inline(always)] + pub fn sos_unmatch_err_int_ena(&self) -> SOS_UNMATCH_ERR_INT_ENA_R { + SOS_UNMATCH_ERR_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The enable interrupt bit to sign that the first scan has header marker error when decoding."] + #[inline(always)] + pub fn marker_err_fst_scan_int_ena(&self) -> MARKER_ERR_FST_SCAN_INT_ENA_R { + MARKER_ERR_FST_SCAN_INT_ENA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] + #[inline(always)] + pub fn marker_err_other_scan_int_ena(&self) -> MARKER_ERR_OTHER_SCAN_INT_ENA_R { + MARKER_ERR_OTHER_SCAN_INT_ENA_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] + #[inline(always)] + pub fn undet_int_ena(&self) -> UNDET_INT_ENA_R { + UNDET_INT_ENA_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] + #[inline(always)] + pub fn decode_timeout_int_ena(&self) -> DECODE_TIMEOUT_INT_ENA_R { + DECODE_TIMEOUT_INT_ENA_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "done_int_ena", + &format_args!("{}", self.done_int_ena().bit()), + ) + .field( + "rle_parallel_err_int_ena", + &format_args!("{}", self.rle_parallel_err_int_ena().bit()), + ) + .field( + "cid_err_int_ena", + &format_args!("{}", self.cid_err_int_ena().bit()), + ) + .field( + "c_dht_dc_id_err_int_ena", + &format_args!("{}", self.c_dht_dc_id_err_int_ena().bit()), + ) + .field( + "c_dht_ac_id_err_int_ena", + &format_args!("{}", self.c_dht_ac_id_err_int_ena().bit()), + ) + .field( + "c_dqt_id_err_int_ena", + &format_args!("{}", self.c_dqt_id_err_int_ena().bit()), + ) + .field( + "rst_uxp_err_int_ena", + &format_args!("{}", self.rst_uxp_err_int_ena().bit()), + ) + .field( + "rst_check_none_err_int_ena", + &format_args!("{}", self.rst_check_none_err_int_ena().bit()), + ) + .field( + "rst_check_pos_err_int_ena", + &format_args!("{}", self.rst_check_pos_err_int_ena().bit()), + ) + .field( + "out_eof_int_ena", + &format_args!("{}", self.out_eof_int_ena().bit()), + ) + .field( + "sr_color_mode_err_int_ena", + &format_args!("{}", self.sr_color_mode_err_int_ena().bit()), + ) + .field( + "dct_done_int_ena", + &format_args!("{}", self.dct_done_int_ena().bit()), + ) + .field( + "bs_last_block_eof_int_ena", + &format_args!("{}", self.bs_last_block_eof_int_ena().bit()), + ) + .field( + "scan_check_none_err_int_ena", + &format_args!("{}", self.scan_check_none_err_int_ena().bit()), + ) + .field( + "scan_check_pos_err_int_ena", + &format_args!("{}", self.scan_check_pos_err_int_ena().bit()), + ) + .field( + "uxp_det_int_ena", + &format_args!("{}", self.uxp_det_int_ena().bit()), + ) + .field( + "en_frame_eof_err_int_ena", + &format_args!("{}", self.en_frame_eof_err_int_ena().bit()), + ) + .field( + "en_frame_eof_lack_int_ena", + &format_args!("{}", self.en_frame_eof_lack_int_ena().bit()), + ) + .field( + "de_frame_eof_err_int_ena", + &format_args!("{}", self.de_frame_eof_err_int_ena().bit()), + ) + .field( + "de_frame_eof_lack_int_ena", + &format_args!("{}", self.de_frame_eof_lack_int_ena().bit()), + ) + .field( + "sos_unmatch_err_int_ena", + &format_args!("{}", self.sos_unmatch_err_int_ena().bit()), + ) + .field( + "marker_err_fst_scan_int_ena", + &format_args!("{}", self.marker_err_fst_scan_int_ena().bit()), + ) + .field( + "marker_err_other_scan_int_ena", + &format_args!("{}", self.marker_err_other_scan_int_ena().bit()), + ) + .field( + "undet_int_ena", + &format_args!("{}", self.undet_int_ena().bit()), + ) + .field( + "decode_timeout_int_ena", + &format_args!("{}", self.decode_timeout_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.."] + #[inline(always)] + #[must_use] + pub fn done_int_ena(&mut self) -> DONE_INT_ENA_W { + DONE_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The enable interrupt bit to sign that rle parallel error when decoding."] + #[inline(always)] + #[must_use] + pub fn rle_parallel_err_int_ena(&mut self) -> RLE_PARALLEL_ERR_INT_ENA_W { + RLE_PARALLEL_ERR_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The enable interrupt bit to sign that scan id check with component fails when decoding."] + #[inline(always)] + #[must_use] + pub fn cid_err_int_ena(&mut self) -> CID_ERR_INT_ENA_W { + CID_ERR_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] + #[inline(always)] + #[must_use] + pub fn c_dht_dc_id_err_int_ena(&mut self) -> C_DHT_DC_ID_ERR_INT_ENA_W { + C_DHT_DC_ID_ERR_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] + #[inline(always)] + #[must_use] + pub fn c_dht_ac_id_err_int_ena(&mut self) -> C_DHT_AC_ID_ERR_INT_ENA_W { + C_DHT_AC_ID_ERR_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] + #[inline(always)] + #[must_use] + pub fn c_dqt_id_err_int_ena(&mut self) -> C_DQT_ID_ERR_INT_ENA_W { + C_DQT_ID_ERR_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] + #[inline(always)] + #[must_use] + pub fn rst_uxp_err_int_ena(&mut self) -> RST_UXP_ERR_INT_ENA_W { + RST_UXP_ERR_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] + #[inline(always)] + #[must_use] + pub fn rst_check_none_err_int_ena(&mut self) -> RST_CHECK_NONE_ERR_INT_ENA_W { + RST_CHECK_NONE_ERR_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] + #[inline(always)] + #[must_use] + pub fn rst_check_pos_err_int_ena(&mut self) -> RST_CHECK_POS_ERR_INT_ENA_W { + RST_CHECK_POS_ERR_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] + #[inline(always)] + #[must_use] + pub fn out_eof_int_ena(&mut self) -> OUT_EOF_INT_ENA_W { + OUT_EOF_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - The enable interrupt bit to sign that the selected source color mode is not supported."] + #[inline(always)] + #[must_use] + pub fn sr_color_mode_err_int_ena(&mut self) -> SR_COLOR_MODE_ERR_INT_ENA_W { + SR_COLOR_MODE_ERR_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - The enable interrupt bit to sign that one dct calculation is finished."] + #[inline(always)] + #[must_use] + pub fn dct_done_int_ena(&mut self) -> DCT_DONE_INT_ENA_W { + DCT_DONE_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - The enable interrupt bit to sign that the coding process for last block is finished."] + #[inline(always)] + #[must_use] + pub fn bs_last_block_eof_int_ena(&mut self) -> BS_LAST_BLOCK_EOF_INT_ENA_W { + BS_LAST_BLOCK_EOF_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] + #[inline(always)] + #[must_use] + pub fn scan_check_none_err_int_ena(&mut self) -> SCAN_CHECK_NONE_ERR_INT_ENA_W { + SCAN_CHECK_NONE_ERR_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - The enable interrupt bit to sign that SOS header marker position wrong when decoding."] + #[inline(always)] + #[must_use] + pub fn scan_check_pos_err_int_ena(&mut self) -> SCAN_CHECK_POS_ERR_INT_ENA_W { + SCAN_CHECK_POS_ERR_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - The enable interrupt bit to sign that unsupported header marker is detected when decoding."] + #[inline(always)] + #[must_use] + pub fn uxp_det_int_ena(&mut self) -> UXP_DET_INT_ENA_W { + UXP_DET_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] + #[inline(always)] + #[must_use] + pub fn en_frame_eof_err_int_ena(&mut self) -> EN_FRAME_EOF_ERR_INT_ENA_W { + EN_FRAME_EOF_ERR_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] + #[inline(always)] + #[must_use] + pub fn en_frame_eof_lack_int_ena(&mut self) -> EN_FRAME_EOF_LACK_INT_ENA_W { + EN_FRAME_EOF_LACK_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 18 - The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding."] + #[inline(always)] + #[must_use] + pub fn de_frame_eof_err_int_ena(&mut self) -> DE_FRAME_EOF_ERR_INT_ENA_W { + DE_FRAME_EOF_ERR_INT_ENA_W::new(self, 18) + } + #[doc = "Bit 19 - The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] + #[inline(always)] + #[must_use] + pub fn de_frame_eof_lack_int_ena(&mut self) -> DE_FRAME_EOF_LACK_INT_ENA_W { + DE_FRAME_EOF_LACK_INT_ENA_W::new(self, 19) + } + #[doc = "Bit 20 - The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] + #[inline(always)] + #[must_use] + pub fn sos_unmatch_err_int_ena(&mut self) -> SOS_UNMATCH_ERR_INT_ENA_W { + SOS_UNMATCH_ERR_INT_ENA_W::new(self, 20) + } + #[doc = "Bit 21 - The enable interrupt bit to sign that the first scan has header marker error when decoding."] + #[inline(always)] + #[must_use] + pub fn marker_err_fst_scan_int_ena(&mut self) -> MARKER_ERR_FST_SCAN_INT_ENA_W { + MARKER_ERR_FST_SCAN_INT_ENA_W::new(self, 21) + } + #[doc = "Bit 22 - The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] + #[inline(always)] + #[must_use] + pub fn marker_err_other_scan_int_ena( + &mut self, + ) -> MARKER_ERR_OTHER_SCAN_INT_ENA_W { + MARKER_ERR_OTHER_SCAN_INT_ENA_W::new(self, 22) + } + #[doc = "Bit 23 - The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] + #[inline(always)] + #[must_use] + pub fn undet_int_ena(&mut self) -> UNDET_INT_ENA_W { + UNDET_INT_ENA_W::new(self, 23) + } + #[doc = "Bit 24 - The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] + #[inline(always)] + #[must_use] + pub fn decode_timeout_int_ena(&mut self) -> DECODE_TIMEOUT_INT_ENA_W { + DECODE_TIMEOUT_INT_ENA_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/int_raw.rs b/esp32p4/src/jpeg/int_raw.rs new file mode 100644 index 0000000000..05cff74e98 --- /dev/null +++ b/esp32p4/src/jpeg/int_raw.rs @@ -0,0 +1,524 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `DONE_INT_RAW` reader - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `DONE_INT_RAW` writer - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RLE_PARALLEL_ERR_INT_RAW` reader - The raw interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `RLE_PARALLEL_ERR_INT_RAW` writer - The raw interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CID_ERR_INT_RAW` reader - The raw interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `CID_ERR_INT_RAW` writer - The raw interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DHT_DC_ID_ERR_INT_RAW` reader - The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `C_DHT_DC_ID_ERR_INT_RAW` writer - The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DHT_AC_ID_ERR_INT_RAW` reader - The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `C_DHT_AC_ID_ERR_INT_RAW` writer - The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_DQT_ID_ERR_INT_RAW` reader - The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `C_DQT_ID_ERR_INT_RAW` writer - The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_UXP_ERR_INT_RAW` reader - The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `RST_UXP_ERR_INT_RAW` writer - The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_CHECK_NONE_ERR_INT_RAW` reader - The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `RST_CHECK_NONE_ERR_INT_RAW` writer - The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_CHECK_POS_ERR_INT_RAW` reader - The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `RST_CHECK_POS_ERR_INT_RAW` writer - The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_INT_RAW` reader - The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_EOF_INT_RAW` writer - The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_COLOR_MODE_ERR_INT_RAW` reader - The raw interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SR_COLOR_MODE_ERR_INT_RAW` writer - The raw interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCT_DONE_INT_RAW` reader - The raw interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `DCT_DONE_INT_RAW` writer - The raw interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BS_LAST_BLOCK_EOF_INT_RAW` reader - The raw interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_INT_RAW_R = crate::BitReader; +#[doc = "Field `BS_LAST_BLOCK_EOF_INT_RAW` writer - The raw interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_RAW` reader - The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_RAW` writer - The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_CHECK_POS_ERR_INT_RAW` reader - The raw interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_POS_ERR_INT_RAW` writer - The raw interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UXP_DET_INT_RAW` reader - The raw interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_INT_RAW_R = crate::BitReader; +#[doc = "Field `UXP_DET_INT_RAW` writer - The raw interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_ERR_INT_RAW` reader - The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_ERR_INT_RAW` writer - The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN_FRAME_EOF_LACK_INT_RAW` reader - The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_INT_RAW_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_LACK_INT_RAW` writer - The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_ERR_INT_RAW` reader - The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_ERR_INT_RAW` writer - The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE_FRAME_EOF_LACK_INT_RAW` reader - The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_INT_RAW_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_LACK_INT_RAW` writer - The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOS_UNMATCH_ERR_INT_RAW` reader - The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SOS_UNMATCH_ERR_INT_RAW` writer - The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MARKER_ERR_FST_SCAN_INT_RAW` reader - The raw interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_INT_RAW_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_FST_SCAN_INT_RAW` writer - The raw interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_RAW` reader - The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_INT_RAW_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_RAW` writer - The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UNDET_INT_RAW` reader - The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_INT_RAW_R = crate::BitReader; +#[doc = "Field `UNDET_INT_RAW` writer - The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DECODE_TIMEOUT_INT_RAW` reader - The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `DECODE_TIMEOUT_INT_RAW` writer - The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.."] + #[inline(always)] + pub fn done_int_raw(&self) -> DONE_INT_RAW_R { + DONE_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit to sign that rle parallel error when decoding."] + #[inline(always)] + pub fn rle_parallel_err_int_raw(&self) -> RLE_PARALLEL_ERR_INT_RAW_R { + RLE_PARALLEL_ERR_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit to sign that scan id check with component fails when decoding."] + #[inline(always)] + pub fn cid_err_int_raw(&self) -> CID_ERR_INT_RAW_R { + CID_ERR_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] + #[inline(always)] + pub fn c_dht_dc_id_err_int_raw(&self) -> C_DHT_DC_ID_ERR_INT_RAW_R { + C_DHT_DC_ID_ERR_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] + #[inline(always)] + pub fn c_dht_ac_id_err_int_raw(&self) -> C_DHT_AC_ID_ERR_INT_RAW_R { + C_DHT_AC_ID_ERR_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] + #[inline(always)] + pub fn c_dqt_id_err_int_raw(&self) -> C_DQT_ID_ERR_INT_RAW_R { + C_DQT_ID_ERR_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] + #[inline(always)] + pub fn rst_uxp_err_int_raw(&self) -> RST_UXP_ERR_INT_RAW_R { + RST_UXP_ERR_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] + #[inline(always)] + pub fn rst_check_none_err_int_raw(&self) -> RST_CHECK_NONE_ERR_INT_RAW_R { + RST_CHECK_NONE_ERR_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] + #[inline(always)] + pub fn rst_check_pos_err_int_raw(&self) -> RST_CHECK_POS_ERR_INT_RAW_R { + RST_CHECK_POS_ERR_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] + #[inline(always)] + pub fn out_eof_int_raw(&self) -> OUT_EOF_INT_RAW_R { + OUT_EOF_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw interrupt bit to sign that the selected source color mode is not supported."] + #[inline(always)] + pub fn sr_color_mode_err_int_raw(&self) -> SR_COLOR_MODE_ERR_INT_RAW_R { + SR_COLOR_MODE_ERR_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw interrupt bit to sign that one dct calculation is finished."] + #[inline(always)] + pub fn dct_done_int_raw(&self) -> DCT_DONE_INT_RAW_R { + DCT_DONE_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The raw interrupt bit to sign that the coding process for last block is finished."] + #[inline(always)] + pub fn bs_last_block_eof_int_raw(&self) -> BS_LAST_BLOCK_EOF_INT_RAW_R { + BS_LAST_BLOCK_EOF_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] + #[inline(always)] + pub fn scan_check_none_err_int_raw(&self) -> SCAN_CHECK_NONE_ERR_INT_RAW_R { + SCAN_CHECK_NONE_ERR_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The raw interrupt bit to sign that SOS header marker position wrong when decoding."] + #[inline(always)] + pub fn scan_check_pos_err_int_raw(&self) -> SCAN_CHECK_POS_ERR_INT_RAW_R { + SCAN_CHECK_POS_ERR_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The raw interrupt bit to sign that unsupported header marker is detected when decoding."] + #[inline(always)] + pub fn uxp_det_int_raw(&self) -> UXP_DET_INT_RAW_R { + UXP_DET_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] + #[inline(always)] + pub fn en_frame_eof_err_int_raw(&self) -> EN_FRAME_EOF_ERR_INT_RAW_R { + EN_FRAME_EOF_ERR_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] + #[inline(always)] + pub fn en_frame_eof_lack_int_raw(&self) -> EN_FRAME_EOF_LACK_INT_RAW_R { + EN_FRAME_EOF_LACK_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding."] + #[inline(always)] + pub fn de_frame_eof_err_int_raw(&self) -> DE_FRAME_EOF_ERR_INT_RAW_R { + DE_FRAME_EOF_ERR_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] + #[inline(always)] + pub fn de_frame_eof_lack_int_raw(&self) -> DE_FRAME_EOF_LACK_INT_RAW_R { + DE_FRAME_EOF_LACK_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] + #[inline(always)] + pub fn sos_unmatch_err_int_raw(&self) -> SOS_UNMATCH_ERR_INT_RAW_R { + SOS_UNMATCH_ERR_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The raw interrupt bit to sign that the first scan has header marker error when decoding."] + #[inline(always)] + pub fn marker_err_fst_scan_int_raw(&self) -> MARKER_ERR_FST_SCAN_INT_RAW_R { + MARKER_ERR_FST_SCAN_INT_RAW_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] + #[inline(always)] + pub fn marker_err_other_scan_int_raw(&self) -> MARKER_ERR_OTHER_SCAN_INT_RAW_R { + MARKER_ERR_OTHER_SCAN_INT_RAW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] + #[inline(always)] + pub fn undet_int_raw(&self) -> UNDET_INT_RAW_R { + UNDET_INT_RAW_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] + #[inline(always)] + pub fn decode_timeout_int_raw(&self) -> DECODE_TIMEOUT_INT_RAW_R { + DECODE_TIMEOUT_INT_RAW_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "done_int_raw", + &format_args!("{}", self.done_int_raw().bit()), + ) + .field( + "rle_parallel_err_int_raw", + &format_args!("{}", self.rle_parallel_err_int_raw().bit()), + ) + .field( + "cid_err_int_raw", + &format_args!("{}", self.cid_err_int_raw().bit()), + ) + .field( + "c_dht_dc_id_err_int_raw", + &format_args!("{}", self.c_dht_dc_id_err_int_raw().bit()), + ) + .field( + "c_dht_ac_id_err_int_raw", + &format_args!("{}", self.c_dht_ac_id_err_int_raw().bit()), + ) + .field( + "c_dqt_id_err_int_raw", + &format_args!("{}", self.c_dqt_id_err_int_raw().bit()), + ) + .field( + "rst_uxp_err_int_raw", + &format_args!("{}", self.rst_uxp_err_int_raw().bit()), + ) + .field( + "rst_check_none_err_int_raw", + &format_args!("{}", self.rst_check_none_err_int_raw().bit()), + ) + .field( + "rst_check_pos_err_int_raw", + &format_args!("{}", self.rst_check_pos_err_int_raw().bit()), + ) + .field( + "out_eof_int_raw", + &format_args!("{}", self.out_eof_int_raw().bit()), + ) + .field( + "sr_color_mode_err_int_raw", + &format_args!("{}", self.sr_color_mode_err_int_raw().bit()), + ) + .field( + "dct_done_int_raw", + &format_args!("{}", self.dct_done_int_raw().bit()), + ) + .field( + "bs_last_block_eof_int_raw", + &format_args!("{}", self.bs_last_block_eof_int_raw().bit()), + ) + .field( + "scan_check_none_err_int_raw", + &format_args!("{}", self.scan_check_none_err_int_raw().bit()), + ) + .field( + "scan_check_pos_err_int_raw", + &format_args!("{}", self.scan_check_pos_err_int_raw().bit()), + ) + .field( + "uxp_det_int_raw", + &format_args!("{}", self.uxp_det_int_raw().bit()), + ) + .field( + "en_frame_eof_err_int_raw", + &format_args!("{}", self.en_frame_eof_err_int_raw().bit()), + ) + .field( + "en_frame_eof_lack_int_raw", + &format_args!("{}", self.en_frame_eof_lack_int_raw().bit()), + ) + .field( + "de_frame_eof_err_int_raw", + &format_args!("{}", self.de_frame_eof_err_int_raw().bit()), + ) + .field( + "de_frame_eof_lack_int_raw", + &format_args!("{}", self.de_frame_eof_lack_int_raw().bit()), + ) + .field( + "sos_unmatch_err_int_raw", + &format_args!("{}", self.sos_unmatch_err_int_raw().bit()), + ) + .field( + "marker_err_fst_scan_int_raw", + &format_args!("{}", self.marker_err_fst_scan_int_raw().bit()), + ) + .field( + "marker_err_other_scan_int_raw", + &format_args!("{}", self.marker_err_other_scan_int_raw().bit()), + ) + .field( + "undet_int_raw", + &format_args!("{}", self.undet_int_raw().bit()), + ) + .field( + "decode_timeout_int_raw", + &format_args!("{}", self.decode_timeout_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.."] + #[inline(always)] + #[must_use] + pub fn done_int_raw(&mut self) -> DONE_INT_RAW_W { + DONE_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit to sign that rle parallel error when decoding."] + #[inline(always)] + #[must_use] + pub fn rle_parallel_err_int_raw(&mut self) -> RLE_PARALLEL_ERR_INT_RAW_W { + RLE_PARALLEL_ERR_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit to sign that scan id check with component fails when decoding."] + #[inline(always)] + #[must_use] + pub fn cid_err_int_raw(&mut self) -> CID_ERR_INT_RAW_W { + CID_ERR_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] + #[inline(always)] + #[must_use] + pub fn c_dht_dc_id_err_int_raw(&mut self) -> C_DHT_DC_ID_ERR_INT_RAW_W { + C_DHT_DC_ID_ERR_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] + #[inline(always)] + #[must_use] + pub fn c_dht_ac_id_err_int_raw(&mut self) -> C_DHT_AC_ID_ERR_INT_RAW_W { + C_DHT_AC_ID_ERR_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] + #[inline(always)] + #[must_use] + pub fn c_dqt_id_err_int_raw(&mut self) -> C_DQT_ID_ERR_INT_RAW_W { + C_DQT_ID_ERR_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] + #[inline(always)] + #[must_use] + pub fn rst_uxp_err_int_raw(&mut self) -> RST_UXP_ERR_INT_RAW_W { + RST_UXP_ERR_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] + #[inline(always)] + #[must_use] + pub fn rst_check_none_err_int_raw(&mut self) -> RST_CHECK_NONE_ERR_INT_RAW_W { + RST_CHECK_NONE_ERR_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] + #[inline(always)] + #[must_use] + pub fn rst_check_pos_err_int_raw(&mut self) -> RST_CHECK_POS_ERR_INT_RAW_W { + RST_CHECK_POS_ERR_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] + #[inline(always)] + #[must_use] + pub fn out_eof_int_raw(&mut self) -> OUT_EOF_INT_RAW_W { + OUT_EOF_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - The raw interrupt bit to sign that the selected source color mode is not supported."] + #[inline(always)] + #[must_use] + pub fn sr_color_mode_err_int_raw(&mut self) -> SR_COLOR_MODE_ERR_INT_RAW_W { + SR_COLOR_MODE_ERR_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - The raw interrupt bit to sign that one dct calculation is finished."] + #[inline(always)] + #[must_use] + pub fn dct_done_int_raw(&mut self) -> DCT_DONE_INT_RAW_W { + DCT_DONE_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 12 - The raw interrupt bit to sign that the coding process for last block is finished."] + #[inline(always)] + #[must_use] + pub fn bs_last_block_eof_int_raw(&mut self) -> BS_LAST_BLOCK_EOF_INT_RAW_W { + BS_LAST_BLOCK_EOF_INT_RAW_W::new(self, 12) + } + #[doc = "Bit 13 - The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] + #[inline(always)] + #[must_use] + pub fn scan_check_none_err_int_raw(&mut self) -> SCAN_CHECK_NONE_ERR_INT_RAW_W { + SCAN_CHECK_NONE_ERR_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 14 - The raw interrupt bit to sign that SOS header marker position wrong when decoding."] + #[inline(always)] + #[must_use] + pub fn scan_check_pos_err_int_raw(&mut self) -> SCAN_CHECK_POS_ERR_INT_RAW_W { + SCAN_CHECK_POS_ERR_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - The raw interrupt bit to sign that unsupported header marker is detected when decoding."] + #[inline(always)] + #[must_use] + pub fn uxp_det_int_raw(&mut self) -> UXP_DET_INT_RAW_W { + UXP_DET_INT_RAW_W::new(self, 15) + } + #[doc = "Bit 16 - The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] + #[inline(always)] + #[must_use] + pub fn en_frame_eof_err_int_raw(&mut self) -> EN_FRAME_EOF_ERR_INT_RAW_W { + EN_FRAME_EOF_ERR_INT_RAW_W::new(self, 16) + } + #[doc = "Bit 17 - The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] + #[inline(always)] + #[must_use] + pub fn en_frame_eof_lack_int_raw(&mut self) -> EN_FRAME_EOF_LACK_INT_RAW_W { + EN_FRAME_EOF_LACK_INT_RAW_W::new(self, 17) + } + #[doc = "Bit 18 - The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding."] + #[inline(always)] + #[must_use] + pub fn de_frame_eof_err_int_raw(&mut self) -> DE_FRAME_EOF_ERR_INT_RAW_W { + DE_FRAME_EOF_ERR_INT_RAW_W::new(self, 18) + } + #[doc = "Bit 19 - The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] + #[inline(always)] + #[must_use] + pub fn de_frame_eof_lack_int_raw(&mut self) -> DE_FRAME_EOF_LACK_INT_RAW_W { + DE_FRAME_EOF_LACK_INT_RAW_W::new(self, 19) + } + #[doc = "Bit 20 - The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] + #[inline(always)] + #[must_use] + pub fn sos_unmatch_err_int_raw(&mut self) -> SOS_UNMATCH_ERR_INT_RAW_W { + SOS_UNMATCH_ERR_INT_RAW_W::new(self, 20) + } + #[doc = "Bit 21 - The raw interrupt bit to sign that the first scan has header marker error when decoding."] + #[inline(always)] + #[must_use] + pub fn marker_err_fst_scan_int_raw(&mut self) -> MARKER_ERR_FST_SCAN_INT_RAW_W { + MARKER_ERR_FST_SCAN_INT_RAW_W::new(self, 21) + } + #[doc = "Bit 22 - The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] + #[inline(always)] + #[must_use] + pub fn marker_err_other_scan_int_raw( + &mut self, + ) -> MARKER_ERR_OTHER_SCAN_INT_RAW_W { + MARKER_ERR_OTHER_SCAN_INT_RAW_W::new(self, 22) + } + #[doc = "Bit 23 - The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] + #[inline(always)] + #[must_use] + pub fn undet_int_raw(&mut self) -> UNDET_INT_RAW_W { + UNDET_INT_RAW_W::new(self, 23) + } + #[doc = "Bit 24 - The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] + #[inline(always)] + #[must_use] + pub fn decode_timeout_int_raw(&mut self) -> DECODE_TIMEOUT_INT_RAW_W { + DECODE_TIMEOUT_INT_RAW_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt raw registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/int_st.rs b/esp32p4/src/jpeg/int_st.rs new file mode 100644 index 0000000000..d53b9393e3 --- /dev/null +++ b/esp32p4/src/jpeg/int_st.rs @@ -0,0 +1,300 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `DONE_INT_ST` reader - This status interrupt bit turns to high level when JPEG finishes encoding a picture.."] +pub type DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `RLE_PARALLEL_ERR_INT_ST` reader - The status interrupt bit to sign that rle parallel error when decoding."] +pub type RLE_PARALLEL_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `CID_ERR_INT_ST` reader - The status interrupt bit to sign that scan id check with component fails when decoding."] +pub type CID_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `C_DHT_DC_ID_ERR_INT_ST` reader - The status interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] +pub type C_DHT_DC_ID_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `C_DHT_AC_ID_ERR_INT_ST` reader - The status interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] +pub type C_DHT_AC_ID_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `C_DQT_ID_ERR_INT_ST` reader - The status interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] +pub type C_DQT_ID_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `RST_UXP_ERR_INT_ST` reader - The status interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] +pub type RST_UXP_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `RST_CHECK_NONE_ERR_INT_ST` reader - The status interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] +pub type RST_CHECK_NONE_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `RST_CHECK_POS_ERR_INT_ST` reader - The status interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] +pub type RST_CHECK_POS_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `OUT_EOF_INT_ST` reader - The status interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] +pub type OUT_EOF_INT_ST_R = crate::BitReader; +#[doc = "Field `SR_COLOR_MODE_ERR_INT_ST` reader - The status interrupt bit to sign that the selected source color mode is not supported."] +pub type SR_COLOR_MODE_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `DCT_DONE_INT_ST` reader - The status interrupt bit to sign that one dct calculation is finished."] +pub type DCT_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `BS_LAST_BLOCK_EOF_INT_ST` reader - The status interrupt bit to sign that the coding process for last block is finished."] +pub type BS_LAST_BLOCK_EOF_INT_ST_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_NONE_ERR_INT_ST` reader - The status interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] +pub type SCAN_CHECK_NONE_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SCAN_CHECK_POS_ERR_INT_ST` reader - The status interrupt bit to sign that SOS header marker position wrong when decoding."] +pub type SCAN_CHECK_POS_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `UXP_DET_INT_ST` reader - The status interrupt bit to sign that unsupported header marker is detected when decoding."] +pub type UXP_DET_INT_ST_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_ERR_INT_ST` reader - The status interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] +pub type EN_FRAME_EOF_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `EN_FRAME_EOF_LACK_INT_ST` reader - The status interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] +pub type EN_FRAME_EOF_LACK_INT_ST_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_ERR_INT_ST` reader - The status interrupt bit to sign that decoded blocks are smaller than expected when decoding."] +pub type DE_FRAME_EOF_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `DE_FRAME_EOF_LACK_INT_ST` reader - The status interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] +pub type DE_FRAME_EOF_LACK_INT_ST_R = crate::BitReader; +#[doc = "Field `SOS_UNMATCH_ERR_INT_ST` reader - The status interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] +pub type SOS_UNMATCH_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_FST_SCAN_INT_ST` reader - The status interrupt bit to sign that the first scan has header marker error when decoding."] +pub type MARKER_ERR_FST_SCAN_INT_ST_R = crate::BitReader; +#[doc = "Field `MARKER_ERR_OTHER_SCAN_INT_ST` reader - The status interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] +pub type MARKER_ERR_OTHER_SCAN_INT_ST_R = crate::BitReader; +#[doc = "Field `UNDET_INT_ST` reader - The status interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] +pub type UNDET_INT_ST_R = crate::BitReader; +#[doc = "Field `DECODE_TIMEOUT_INT_ST` reader - The status interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] +pub type DECODE_TIMEOUT_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This status interrupt bit turns to high level when JPEG finishes encoding a picture.."] + #[inline(always)] + pub fn done_int_st(&self) -> DONE_INT_ST_R { + DONE_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The status interrupt bit to sign that rle parallel error when decoding."] + #[inline(always)] + pub fn rle_parallel_err_int_st(&self) -> RLE_PARALLEL_ERR_INT_ST_R { + RLE_PARALLEL_ERR_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The status interrupt bit to sign that scan id check with component fails when decoding."] + #[inline(always)] + pub fn cid_err_int_st(&self) -> CID_ERR_INT_ST_R { + CID_ERR_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The status interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding."] + #[inline(always)] + pub fn c_dht_dc_id_err_int_st(&self) -> C_DHT_DC_ID_ERR_INT_ST_R { + C_DHT_DC_ID_ERR_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The status interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding."] + #[inline(always)] + pub fn c_dht_ac_id_err_int_st(&self) -> C_DHT_AC_ID_ERR_INT_ST_R { + C_DHT_AC_ID_ERR_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The status interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding."] + #[inline(always)] + pub fn c_dqt_id_err_int_st(&self) -> C_DQT_ID_ERR_INT_ST_R { + C_DQT_ID_ERR_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The status interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding."] + #[inline(always)] + pub fn rst_uxp_err_int_st(&self) -> RST_UXP_ERR_INT_ST_R { + RST_UXP_ERR_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The status interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding."] + #[inline(always)] + pub fn rst_check_none_err_int_st(&self) -> RST_CHECK_NONE_ERR_INT_ST_R { + RST_CHECK_NONE_ERR_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The status interrupt bit to sign that RST header marker position mismatches with restart interval when decoding."] + #[inline(always)] + pub fn rst_check_pos_err_int_st(&self) -> RST_CHECK_POS_ERR_INT_ST_R { + RST_CHECK_POS_ERR_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The status interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel."] + #[inline(always)] + pub fn out_eof_int_st(&self) -> OUT_EOF_INT_ST_R { + OUT_EOF_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The status interrupt bit to sign that the selected source color mode is not supported."] + #[inline(always)] + pub fn sr_color_mode_err_int_st(&self) -> SR_COLOR_MODE_ERR_INT_ST_R { + SR_COLOR_MODE_ERR_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The status interrupt bit to sign that one dct calculation is finished."] + #[inline(always)] + pub fn dct_done_int_st(&self) -> DCT_DONE_INT_ST_R { + DCT_DONE_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The status interrupt bit to sign that the coding process for last block is finished."] + #[inline(always)] + pub fn bs_last_block_eof_int_st(&self) -> BS_LAST_BLOCK_EOF_INT_ST_R { + BS_LAST_BLOCK_EOF_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The status interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded."] + #[inline(always)] + pub fn scan_check_none_err_int_st(&self) -> SCAN_CHECK_NONE_ERR_INT_ST_R { + SCAN_CHECK_NONE_ERR_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The status interrupt bit to sign that SOS header marker position wrong when decoding."] + #[inline(always)] + pub fn scan_check_pos_err_int_st(&self) -> SCAN_CHECK_POS_ERR_INT_ST_R { + SCAN_CHECK_POS_ERR_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The status interrupt bit to sign that unsupported header marker is detected when decoding."] + #[inline(always)] + pub fn uxp_det_int_st(&self) -> UXP_DET_INT_ST_R { + UXP_DET_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The status interrupt bit to sign that received pixel blocks are smaller than expected when encoding."] + #[inline(always)] + pub fn en_frame_eof_err_int_st(&self) -> EN_FRAME_EOF_ERR_INT_ST_R { + EN_FRAME_EOF_ERR_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The status interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough."] + #[inline(always)] + pub fn en_frame_eof_lack_int_st(&self) -> EN_FRAME_EOF_LACK_INT_ST_R { + EN_FRAME_EOF_LACK_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The status interrupt bit to sign that decoded blocks are smaller than expected when decoding."] + #[inline(always)] + pub fn de_frame_eof_err_int_st(&self) -> DE_FRAME_EOF_ERR_INT_ST_R { + DE_FRAME_EOF_ERR_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The status interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough."] + #[inline(always)] + pub fn de_frame_eof_lack_int_st(&self) -> DE_FRAME_EOF_LACK_INT_ST_R { + DE_FRAME_EOF_LACK_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The status interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding."] + #[inline(always)] + pub fn sos_unmatch_err_int_st(&self) -> SOS_UNMATCH_ERR_INT_ST_R { + SOS_UNMATCH_ERR_INT_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The status interrupt bit to sign that the first scan has header marker error when decoding."] + #[inline(always)] + pub fn marker_err_fst_scan_int_st(&self) -> MARKER_ERR_FST_SCAN_INT_ST_R { + MARKER_ERR_FST_SCAN_INT_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - The status interrupt bit to sign that the following scans but not the first scan have header marker error when decoding."] + #[inline(always)] + pub fn marker_err_other_scan_int_st(&self) -> MARKER_ERR_OTHER_SCAN_INT_ST_R { + MARKER_ERR_OTHER_SCAN_INT_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - The status interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding."] + #[inline(always)] + pub fn undet_int_st(&self) -> UNDET_INT_ST_R { + UNDET_INT_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - The status interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding."] + #[inline(always)] + pub fn decode_timeout_int_st(&self) -> DECODE_TIMEOUT_INT_ST_R { + DECODE_TIMEOUT_INT_ST_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field("done_int_st", &format_args!("{}", self.done_int_st().bit())) + .field( + "rle_parallel_err_int_st", + &format_args!("{}", self.rle_parallel_err_int_st().bit()), + ) + .field( + "cid_err_int_st", + &format_args!("{}", self.cid_err_int_st().bit()), + ) + .field( + "c_dht_dc_id_err_int_st", + &format_args!("{}", self.c_dht_dc_id_err_int_st().bit()), + ) + .field( + "c_dht_ac_id_err_int_st", + &format_args!("{}", self.c_dht_ac_id_err_int_st().bit()), + ) + .field( + "c_dqt_id_err_int_st", + &format_args!("{}", self.c_dqt_id_err_int_st().bit()), + ) + .field( + "rst_uxp_err_int_st", + &format_args!("{}", self.rst_uxp_err_int_st().bit()), + ) + .field( + "rst_check_none_err_int_st", + &format_args!("{}", self.rst_check_none_err_int_st().bit()), + ) + .field( + "rst_check_pos_err_int_st", + &format_args!("{}", self.rst_check_pos_err_int_st().bit()), + ) + .field( + "out_eof_int_st", + &format_args!("{}", self.out_eof_int_st().bit()), + ) + .field( + "sr_color_mode_err_int_st", + &format_args!("{}", self.sr_color_mode_err_int_st().bit()), + ) + .field( + "dct_done_int_st", + &format_args!("{}", self.dct_done_int_st().bit()), + ) + .field( + "bs_last_block_eof_int_st", + &format_args!("{}", self.bs_last_block_eof_int_st().bit()), + ) + .field( + "scan_check_none_err_int_st", + &format_args!("{}", self.scan_check_none_err_int_st().bit()), + ) + .field( + "scan_check_pos_err_int_st", + &format_args!("{}", self.scan_check_pos_err_int_st().bit()), + ) + .field( + "uxp_det_int_st", + &format_args!("{}", self.uxp_det_int_st().bit()), + ) + .field( + "en_frame_eof_err_int_st", + &format_args!("{}", self.en_frame_eof_err_int_st().bit()), + ) + .field( + "en_frame_eof_lack_int_st", + &format_args!("{}", self.en_frame_eof_lack_int_st().bit()), + ) + .field( + "de_frame_eof_err_int_st", + &format_args!("{}", self.de_frame_eof_err_int_st().bit()), + ) + .field( + "de_frame_eof_lack_int_st", + &format_args!("{}", self.de_frame_eof_lack_int_st().bit()), + ) + .field( + "sos_unmatch_err_int_st", + &format_args!("{}", self.sos_unmatch_err_int_st().bit()), + ) + .field( + "marker_err_fst_scan_int_st", + &format_args!("{}", self.marker_err_fst_scan_int_st().bit()), + ) + .field( + "marker_err_other_scan_int_st", + &format_args!("{}", self.marker_err_other_scan_int_st().bit()), + ) + .field( + "undet_int_st", + &format_args!("{}", self.undet_int_st().bit()), + ) + .field( + "decode_timeout_int_st", + &format_args!("{}", self.decode_timeout_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Interrupt status registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/pic_size.rs b/esp32p4/src/jpeg/pic_size.rs new file mode 100644 index 0000000000..137d3f0011 --- /dev/null +++ b/esp32p4/src/jpeg/pic_size.rs @@ -0,0 +1,79 @@ +#[doc = "Register `PIC_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `PIC_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `VA` reader - configure picture's height. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16"] +pub type VA_R = crate::FieldReader; +#[doc = "Field `VA` writer - configure picture's height. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16"] +pub type VA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `HA` reader - configure picture's width. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16"] +pub type HA_R = crate::FieldReader; +#[doc = "Field `HA` writer - configure picture's width. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16"] +pub type HA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - configure picture's height. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16"] + #[inline(always)] + pub fn va(&self) -> VA_R { + VA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - configure picture's width. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16"] + #[inline(always)] + pub fn ha(&self) -> HA_R { + HA_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIC_SIZE") + .field("va", &format_args!("{}", self.va().bits())) + .field("ha", &format_args!("{}", self.ha().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - configure picture's height. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16"] + #[inline(always)] + #[must_use] + pub fn va(&mut self) -> VA_W { + VA_W::new(self, 0) + } + #[doc = "Bits 16:31 - configure picture's width. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16"] + #[inline(always)] + #[must_use] + pub fn ha(&mut self) -> HA_W { + HA_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pic_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pic_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIC_SIZE_SPEC; +impl crate::RegisterSpec for PIC_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pic_size::R`](R) reader structure"] +impl crate::Readable for PIC_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pic_size::W`](W) writer structure"] +impl crate::Writable for PIC_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIC_SIZE to value 0x0280_01e0"] +impl crate::Resettable for PIC_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0x0280_01e0; +} diff --git a/esp32p4/src/jpeg/status0.rs b/esp32p4/src/jpeg/status0.rs new file mode 100644 index 0000000000..6416ab9d23 --- /dev/null +++ b/esp32p4/src/jpeg/status0.rs @@ -0,0 +1,72 @@ +#[doc = "Register `STATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `BITSTREAM_EOF_VLD_CNT` reader - the valid bit count for last bitstream"] +pub type BITSTREAM_EOF_VLD_CNT_R = crate::FieldReader; +#[doc = "Field `DCTOUT_ZZSCAN_ADDR` reader - the zig-zag read addr from dctout_ram"] +pub type DCTOUT_ZZSCAN_ADDR_R = crate::FieldReader; +#[doc = "Field `QNRVAL_ZZSCAN_ADDR` reader - the zig-zag read addr from qnrval_ram"] +pub type QNRVAL_ZZSCAN_ADDR_R = crate::FieldReader; +#[doc = "Field `REG_STATE_YUV` reader - the state of jpeg fsm"] +pub type REG_STATE_YUV_R = crate::FieldReader; +impl R { + #[doc = "Bits 11:16 - the valid bit count for last bitstream"] + #[inline(always)] + pub fn bitstream_eof_vld_cnt(&self) -> BITSTREAM_EOF_VLD_CNT_R { + BITSTREAM_EOF_VLD_CNT_R::new(((self.bits >> 11) & 0x3f) as u8) + } + #[doc = "Bits 17:22 - the zig-zag read addr from dctout_ram"] + #[inline(always)] + pub fn dctout_zzscan_addr(&self) -> DCTOUT_ZZSCAN_ADDR_R { + DCTOUT_ZZSCAN_ADDR_R::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bits 23:28 - the zig-zag read addr from qnrval_ram"] + #[inline(always)] + pub fn qnrval_zzscan_addr(&self) -> QNRVAL_ZZSCAN_ADDR_R { + QNRVAL_ZZSCAN_ADDR_R::new(((self.bits >> 23) & 0x3f) as u8) + } + #[doc = "Bits 29:31 - the state of jpeg fsm"] + #[inline(always)] + pub fn reg_state_yuv(&self) -> REG_STATE_YUV_R { + REG_STATE_YUV_R::new(((self.bits >> 29) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS0") + .field( + "bitstream_eof_vld_cnt", + &format_args!("{}", self.bitstream_eof_vld_cnt().bits()), + ) + .field( + "dctout_zzscan_addr", + &format_args!("{}", self.dctout_zzscan_addr().bits()), + ) + .field( + "qnrval_zzscan_addr", + &format_args!("{}", self.qnrval_zzscan_addr().bits()), + ) + .field( + "reg_state_yuv", + &format_args!("{}", self.reg_state_yuv().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS0_SPEC; +impl crate::RegisterSpec for STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status0::R`](R) reader structure"] +impl crate::Readable for STATUS0_SPEC {} +#[doc = "`reset()` method sets STATUS0 to value 0"] +impl crate::Resettable for STATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/status2.rs b/esp32p4/src/jpeg/status2.rs new file mode 100644 index 0000000000..34c1cf373e --- /dev/null +++ b/esp32p4/src/jpeg/status2.rs @@ -0,0 +1,74 @@ +#[doc = "Register `STATUS2` reader"] +pub type R = crate::R; +#[doc = "Field `SOURCE_PIXEL` reader - source pixels fetched from dma"] +pub type SOURCE_PIXEL_R = crate::FieldReader; +#[doc = "Field `LAST_BLOCK` reader - indicate the encoding process for the last mcu of the picture"] +pub type LAST_BLOCK_R = crate::BitReader; +#[doc = "Field `LAST_MCU` reader - indicate the encoding process for the last block of the picture"] +pub type LAST_MCU_R = crate::BitReader; +#[doc = "Field `LAST_DC` reader - indicate the encoding process is at the header of the last block of the picture"] +pub type LAST_DC_R = crate::BitReader; +#[doc = "Field `PACKFIFO_READY` reader - the jpeg pack_fifo ready signal, high active"] +pub type PACKFIFO_READY_R = crate::BitReader; +impl R { + #[doc = "Bits 0:23 - source pixels fetched from dma"] + #[inline(always)] + pub fn source_pixel(&self) -> SOURCE_PIXEL_R { + SOURCE_PIXEL_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bit 24 - indicate the encoding process for the last mcu of the picture"] + #[inline(always)] + pub fn last_block(&self) -> LAST_BLOCK_R { + LAST_BLOCK_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - indicate the encoding process for the last block of the picture"] + #[inline(always)] + pub fn last_mcu(&self) -> LAST_MCU_R { + LAST_MCU_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - indicate the encoding process is at the header of the last block of the picture"] + #[inline(always)] + pub fn last_dc(&self) -> LAST_DC_R { + LAST_DC_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - the jpeg pack_fifo ready signal, high active"] + #[inline(always)] + pub fn packfifo_ready(&self) -> PACKFIFO_READY_R { + PACKFIFO_READY_R::new(((self.bits >> 27) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS2") + .field( + "source_pixel", + &format_args!("{}", self.source_pixel().bits()), + ) + .field("last_block", &format_args!("{}", self.last_block().bit())) + .field("last_mcu", &format_args!("{}", self.last_mcu().bit())) + .field("last_dc", &format_args!("{}", self.last_dc().bit())) + .field( + "packfifo_ready", + &format_args!("{}", self.packfifo_ready().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS2_SPEC; +impl crate::RegisterSpec for STATUS2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status2::R`](R) reader structure"] +impl crate::Readable for STATUS2_SPEC {} +#[doc = "`reset()` method sets STATUS2 to value 0x0800_0000"] +impl crate::Resettable for STATUS2_SPEC { + const RESET_VALUE: Self::Ux = 0x0800_0000; +} diff --git a/esp32p4/src/jpeg/status3.rs b/esp32p4/src/jpeg/status3.rs new file mode 100644 index 0000000000..145e778395 --- /dev/null +++ b/esp32p4/src/jpeg/status3.rs @@ -0,0 +1,76 @@ +#[doc = "Register `STATUS3` reader"] +pub type R = crate::R; +#[doc = "Field `YO` reader - component y transferred from rgb input"] +pub type YO_R = crate::FieldReader; +#[doc = "Field `Y_READY` reader - component y valid signal, high active"] +pub type Y_READY_R = crate::BitReader; +#[doc = "Field `CBO` reader - component cb transferred from rgb input"] +pub type CBO_R = crate::FieldReader; +#[doc = "Field `CB_READY` reader - component cb valid signal, high active"] +pub type CB_READY_R = crate::BitReader; +#[doc = "Field `CRO` reader - component cr transferred from rgb input"] +pub type CRO_R = crate::FieldReader; +#[doc = "Field `CR_READY` reader - component cr valid signal, high active"] +pub type CR_READY_R = crate::BitReader; +impl R { + #[doc = "Bits 0:8 - component y transferred from rgb input"] + #[inline(always)] + pub fn yo(&self) -> YO_R { + YO_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bit 9 - component y valid signal, high active"] + #[inline(always)] + pub fn y_ready(&self) -> Y_READY_R { + Y_READY_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:18 - component cb transferred from rgb input"] + #[inline(always)] + pub fn cbo(&self) -> CBO_R { + CBO_R::new(((self.bits >> 10) & 0x01ff) as u16) + } + #[doc = "Bit 19 - component cb valid signal, high active"] + #[inline(always)] + pub fn cb_ready(&self) -> CB_READY_R { + CB_READY_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:28 - component cr transferred from rgb input"] + #[inline(always)] + pub fn cro(&self) -> CRO_R { + CRO_R::new(((self.bits >> 20) & 0x01ff) as u16) + } + #[doc = "Bit 29 - component cr valid signal, high active"] + #[inline(always)] + pub fn cr_ready(&self) -> CR_READY_R { + CR_READY_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS3") + .field("yo", &format_args!("{}", self.yo().bits())) + .field("y_ready", &format_args!("{}", self.y_ready().bit())) + .field("cbo", &format_args!("{}", self.cbo().bits())) + .field("cb_ready", &format_args!("{}", self.cb_ready().bit())) + .field("cro", &format_args!("{}", self.cro().bits())) + .field("cr_ready", &format_args!("{}", self.cr_ready().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS3_SPEC; +impl crate::RegisterSpec for STATUS3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status3::R`](R) reader structure"] +impl crate::Readable for STATUS3_SPEC {} +#[doc = "`reset()` method sets STATUS3 to value 0"] +impl crate::Resettable for STATUS3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/status4.rs b/esp32p4/src/jpeg/status4.rs new file mode 100644 index 0000000000..3d4413fbd7 --- /dev/null +++ b/esp32p4/src/jpeg/status4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `STATUS4` reader"] +pub type R = crate::R; +#[doc = "Field `HFM_BITSTREAM` reader - the hufman bitstream during encoding process"] +pub type HFM_BITSTREAM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - the hufman bitstream during encoding process"] + #[inline(always)] + pub fn hfm_bitstream(&self) -> HFM_BITSTREAM_R { + HFM_BITSTREAM_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS4") + .field( + "hfm_bitstream", + &format_args!("{}", self.hfm_bitstream().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS4_SPEC; +impl crate::RegisterSpec for STATUS4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status4::R`](R) reader structure"] +impl crate::Readable for STATUS4_SPEC {} +#[doc = "`reset()` method sets STATUS4 to value 0"] +impl crate::Resettable for STATUS4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/status5.rs b/esp32p4/src/jpeg/status5.rs new file mode 100644 index 0000000000..6414bb3f52 --- /dev/null +++ b/esp32p4/src/jpeg/status5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `STATUS5` reader"] +pub type R = crate::R; +#[doc = "Field `PIC_BLOCK_NUM` reader - Reserved"] +pub type PIC_BLOCK_NUM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - Reserved"] + #[inline(always)] + pub fn pic_block_num(&self) -> PIC_BLOCK_NUM_R { + PIC_BLOCK_NUM_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS5") + .field( + "pic_block_num", + &format_args!("{}", self.pic_block_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS5_SPEC; +impl crate::RegisterSpec for STATUS5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status5::R`](R) reader structure"] +impl crate::Readable for STATUS5_SPEC {} +#[doc = "`reset()` method sets STATUS5 to value 0"] +impl crate::Resettable for STATUS5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/sys.rs b/esp32p4/src/jpeg/sys.rs new file mode 100644 index 0000000000..edd053edbf --- /dev/null +++ b/esp32p4/src/jpeg/sys.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SYS` reader"] +pub type R = crate::R; +#[doc = "Register `SYS` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - Reserved"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Reserved"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYS") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYS_SPEC; +impl crate::RegisterSpec for SYS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sys::R`](R) reader structure"] +impl crate::Readable for SYS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sys::W`](W) writer structure"] +impl crate::Writable for SYS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYS to value 0"] +impl crate::Resettable for SYS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/t0qnr.rs b/esp32p4/src/jpeg/t0qnr.rs new file mode 100644 index 0000000000..33aa939a6a --- /dev/null +++ b/esp32p4/src/jpeg/t0qnr.rs @@ -0,0 +1,36 @@ +#[doc = "Register `T0QNR` reader"] +pub type R = crate::R; +#[doc = "Field `T0_QNR_VAL` reader - write this reg to configure 64 quantization coefficient in t0 table"] +pub type T0_QNR_VAL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write this reg to configure 64 quantization coefficient in t0 table"] + #[inline(always)] + pub fn t0_qnr_val(&self) -> T0_QNR_VAL_R { + T0_QNR_VAL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T0QNR") + .field("t0_qnr_val", &format_args!("{}", self.t0_qnr_val().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0qnr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T0QNR_SPEC; +impl crate::RegisterSpec for T0QNR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t0qnr::R`](R) reader structure"] +impl crate::Readable for T0QNR_SPEC {} +#[doc = "`reset()` method sets T0QNR to value 0"] +impl crate::Resettable for T0QNR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/t1qnr.rs b/esp32p4/src/jpeg/t1qnr.rs new file mode 100644 index 0000000000..a63a0c7228 --- /dev/null +++ b/esp32p4/src/jpeg/t1qnr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `T1QNR` reader"] +pub type R = crate::R; +#[doc = "Field `CHROMINANCE_QNR_VAL` reader - write this reg to configure 64 quantization coefficient in t1 table"] +pub type CHROMINANCE_QNR_VAL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write this reg to configure 64 quantization coefficient in t1 table"] + #[inline(always)] + pub fn chrominance_qnr_val(&self) -> CHROMINANCE_QNR_VAL_R { + CHROMINANCE_QNR_VAL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T1QNR") + .field( + "chrominance_qnr_val", + &format_args!("{}", self.chrominance_qnr_val().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t1qnr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T1QNR_SPEC; +impl crate::RegisterSpec for T1QNR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t1qnr::R`](R) reader structure"] +impl crate::Readable for T1QNR_SPEC {} +#[doc = "`reset()` method sets T1QNR to value 0"] +impl crate::Resettable for T1QNR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/t2qnr.rs b/esp32p4/src/jpeg/t2qnr.rs new file mode 100644 index 0000000000..2983349245 --- /dev/null +++ b/esp32p4/src/jpeg/t2qnr.rs @@ -0,0 +1,36 @@ +#[doc = "Register `T2QNR` reader"] +pub type R = crate::R; +#[doc = "Field `T2_QNR_VAL` reader - write this reg to configure 64 quantization coefficient in t2 table"] +pub type T2_QNR_VAL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write this reg to configure 64 quantization coefficient in t2 table"] + #[inline(always)] + pub fn t2_qnr_val(&self) -> T2_QNR_VAL_R { + T2_QNR_VAL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T2QNR") + .field("t2_qnr_val", &format_args!("{}", self.t2_qnr_val().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t2qnr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T2QNR_SPEC; +impl crate::RegisterSpec for T2QNR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t2qnr::R`](R) reader structure"] +impl crate::Readable for T2QNR_SPEC {} +#[doc = "`reset()` method sets T2QNR to value 0"] +impl crate::Resettable for T2QNR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/t3qnr.rs b/esp32p4/src/jpeg/t3qnr.rs new file mode 100644 index 0000000000..29c2db506b --- /dev/null +++ b/esp32p4/src/jpeg/t3qnr.rs @@ -0,0 +1,36 @@ +#[doc = "Register `T3QNR` reader"] +pub type R = crate::R; +#[doc = "Field `T3_QNR_VAL` reader - write this reg to configure 64 quantization coefficient in t3 table"] +pub type T3_QNR_VAL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - write this reg to configure 64 quantization coefficient in t3 table"] + #[inline(always)] + pub fn t3_qnr_val(&self) -> T3_QNR_VAL_R { + T3_QNR_VAL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T3QNR") + .field("t3_qnr_val", &format_args!("{}", self.t3_qnr_val().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t3qnr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T3QNR_SPEC; +impl crate::RegisterSpec for T3QNR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t3qnr::R`](R) reader structure"] +impl crate::Readable for T3QNR_SPEC {} +#[doc = "`reset()` method sets T3QNR to value 0"] +impl crate::Resettable for T3QNR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/jpeg/version.rs b/esp32p4/src/jpeg/version.rs new file mode 100644 index 0000000000..55abfbee9c --- /dev/null +++ b/esp32p4/src/jpeg/version.rs @@ -0,0 +1,63 @@ +#[doc = "Register `VERSION` reader"] +pub type R = crate::R; +#[doc = "Register `VERSION` writer"] +pub type W = crate::W; +#[doc = "Field `JPEG_VER` reader - Reserved"] +pub type JPEG_VER_R = crate::FieldReader; +#[doc = "Field `JPEG_VER` writer - Reserved"] +pub type JPEG_VER_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Reserved"] + #[inline(always)] + pub fn jpeg_ver(&self) -> JPEG_VER_R { + JPEG_VER_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VERSION") + .field("jpeg_ver", &format_args!("{}", self.jpeg_ver().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn jpeg_ver(&mut self) -> JPEG_VER_W { + JPEG_VER_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VERSION_SPEC; +impl crate::RegisterSpec for VERSION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`version::R`](R) reader structure"] +impl crate::Readable for VERSION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"] +impl crate::Writable for VERSION_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VERSION to value 0x0211_1190"] +impl crate::Resettable for VERSION_SPEC { + const RESET_VALUE: Self::Ux = 0x0211_1190; +} diff --git a/esp32p4/src/lcd_cam.rs b/esp32p4/src/lcd_cam.rs new file mode 100644 index 0000000000..8be31403ba --- /dev/null +++ b/esp32p4/src/lcd_cam.rs @@ -0,0 +1,200 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + lcd_clock: LCD_CLOCK, + cam_ctrl: CAM_CTRL, + cam_ctrl1: CAM_CTRL1, + cam_rgb_yuv: CAM_RGB_YUV, + lcd_rgb_yuv: LCD_RGB_YUV, + lcd_user: LCD_USER, + lcd_misc: LCD_MISC, + lcd_ctrl: LCD_CTRL, + lcd_ctrl1: LCD_CTRL1, + lcd_ctrl2: LCD_CTRL2, + lcd_first_cmd_val: LCD_FIRST_CMD_VAL, + lcd_latter_cmd_val: LCD_LATTER_CMD_VAL, + lcd_dly_mode_cfg1: LCD_DLY_MODE_CFG1, + _reserved13: [u8; 0x04], + lcd_dly_mode_cfg2: LCD_DLY_MODE_CFG2, + _reserved14: [u8; 0x28], + lc_dma_int_ena: LC_DMA_INT_ENA, + lc_dma_int_raw: LC_DMA_INT_RAW, + lc_dma_int_st: LC_DMA_INT_ST, + lc_dma_int_clr: LC_DMA_INT_CLR, + _reserved18: [u8; 0x88], + lc_reg_date: LC_REG_DATE, +} +impl RegisterBlock { + #[doc = "0x00 - LCD clock config register."] + #[inline(always)] + pub const fn lcd_clock(&self) -> &LCD_CLOCK { + &self.lcd_clock + } + #[doc = "0x04 - CAM config register."] + #[inline(always)] + pub const fn cam_ctrl(&self) -> &CAM_CTRL { + &self.cam_ctrl + } + #[doc = "0x08 - CAM config register."] + #[inline(always)] + pub const fn cam_ctrl1(&self) -> &CAM_CTRL1 { + &self.cam_ctrl1 + } + #[doc = "0x0c - CAM YUV/RGB converter configuration register."] + #[inline(always)] + pub const fn cam_rgb_yuv(&self) -> &CAM_RGB_YUV { + &self.cam_rgb_yuv + } + #[doc = "0x10 - LCD YUV/RGB converter configuration register."] + #[inline(always)] + pub const fn lcd_rgb_yuv(&self) -> &LCD_RGB_YUV { + &self.lcd_rgb_yuv + } + #[doc = "0x14 - LCD config register."] + #[inline(always)] + pub const fn lcd_user(&self) -> &LCD_USER { + &self.lcd_user + } + #[doc = "0x18 - LCD config register."] + #[inline(always)] + pub const fn lcd_misc(&self) -> &LCD_MISC { + &self.lcd_misc + } + #[doc = "0x1c - LCD config register."] + #[inline(always)] + pub const fn lcd_ctrl(&self) -> &LCD_CTRL { + &self.lcd_ctrl + } + #[doc = "0x20 - LCD config register."] + #[inline(always)] + pub const fn lcd_ctrl1(&self) -> &LCD_CTRL1 { + &self.lcd_ctrl1 + } + #[doc = "0x24 - LCD config register."] + #[inline(always)] + pub const fn lcd_ctrl2(&self) -> &LCD_CTRL2 { + &self.lcd_ctrl2 + } + #[doc = "0x28 - LCD config register."] + #[inline(always)] + pub const fn lcd_first_cmd_val(&self) -> &LCD_FIRST_CMD_VAL { + &self.lcd_first_cmd_val + } + #[doc = "0x2c - LCD config register."] + #[inline(always)] + pub const fn lcd_latter_cmd_val(&self) -> &LCD_LATTER_CMD_VAL { + &self.lcd_latter_cmd_val + } + #[doc = "0x30 - LCD config register."] + #[inline(always)] + pub const fn lcd_dly_mode_cfg1(&self) -> &LCD_DLY_MODE_CFG1 { + &self.lcd_dly_mode_cfg1 + } + #[doc = "0x38 - LCD config register."] + #[inline(always)] + pub const fn lcd_dly_mode_cfg2(&self) -> &LCD_DLY_MODE_CFG2 { + &self.lcd_dly_mode_cfg2 + } + #[doc = "0x64 - LCDCAM interrupt enable register."] + #[inline(always)] + pub const fn lc_dma_int_ena(&self) -> &LC_DMA_INT_ENA { + &self.lc_dma_int_ena + } + #[doc = "0x68 - LCDCAM interrupt raw register, valid in level."] + #[inline(always)] + pub const fn lc_dma_int_raw(&self) -> &LC_DMA_INT_RAW { + &self.lc_dma_int_raw + } + #[doc = "0x6c - LCDCAM interrupt status register."] + #[inline(always)] + pub const fn lc_dma_int_st(&self) -> &LC_DMA_INT_ST { + &self.lc_dma_int_st + } + #[doc = "0x70 - LCDCAM interrupt clear register."] + #[inline(always)] + pub const fn lc_dma_int_clr(&self) -> &LC_DMA_INT_CLR { + &self.lc_dma_int_clr + } + #[doc = "0xfc - Version register"] + #[inline(always)] + pub const fn lc_reg_date(&self) -> &LC_REG_DATE { + &self.lc_reg_date + } +} +#[doc = "LCD_CLOCK (rw) register accessor: LCD clock config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_clock::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_clock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_clock`] module"] +pub type LCD_CLOCK = crate::Reg; +#[doc = "LCD clock config register."] +pub mod lcd_clock; +#[doc = "CAM_CTRL (rw) register accessor: CAM config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cam_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cam_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cam_ctrl`] module"] +pub type CAM_CTRL = crate::Reg; +#[doc = "CAM config register."] +pub mod cam_ctrl; +#[doc = "CAM_CTRL1 (rw) register accessor: CAM config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cam_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cam_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cam_ctrl1`] module"] +pub type CAM_CTRL1 = crate::Reg; +#[doc = "CAM config register."] +pub mod cam_ctrl1; +#[doc = "CAM_RGB_YUV (rw) register accessor: CAM YUV/RGB converter configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cam_rgb_yuv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cam_rgb_yuv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cam_rgb_yuv`] module"] +pub type CAM_RGB_YUV = crate::Reg; +#[doc = "CAM YUV/RGB converter configuration register."] +pub mod cam_rgb_yuv; +#[doc = "LCD_RGB_YUV (rw) register accessor: LCD YUV/RGB converter configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_rgb_yuv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_rgb_yuv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_rgb_yuv`] module"] +pub type LCD_RGB_YUV = crate::Reg; +#[doc = "LCD YUV/RGB converter configuration register."] +pub mod lcd_rgb_yuv; +#[doc = "LCD_USER (rw) register accessor: LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_user::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_user::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_user`] module"] +pub type LCD_USER = crate::Reg; +#[doc = "LCD config register."] +pub mod lcd_user; +#[doc = "LCD_MISC (rw) register accessor: LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_misc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_misc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_misc`] module"] +pub type LCD_MISC = crate::Reg; +#[doc = "LCD config register."] +pub mod lcd_misc; +#[doc = "LCD_CTRL (rw) register accessor: LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_ctrl`] module"] +pub type LCD_CTRL = crate::Reg; +#[doc = "LCD config register."] +pub mod lcd_ctrl; +#[doc = "LCD_CTRL1 (rw) register accessor: LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_ctrl1`] module"] +pub type LCD_CTRL1 = crate::Reg; +#[doc = "LCD config register."] +pub mod lcd_ctrl1; +#[doc = "LCD_CTRL2 (rw) register accessor: LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_ctrl2`] module"] +pub type LCD_CTRL2 = crate::Reg; +#[doc = "LCD config register."] +pub mod lcd_ctrl2; +#[doc = "LCD_FIRST_CMD_VAL (rw) register accessor: LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_first_cmd_val::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_first_cmd_val::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_first_cmd_val`] module"] +pub type LCD_FIRST_CMD_VAL = crate::Reg; +#[doc = "LCD config register."] +pub mod lcd_first_cmd_val; +#[doc = "LCD_LATTER_CMD_VAL (rw) register accessor: LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_latter_cmd_val::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_latter_cmd_val::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_latter_cmd_val`] module"] +pub type LCD_LATTER_CMD_VAL = crate::Reg; +#[doc = "LCD config register."] +pub mod lcd_latter_cmd_val; +#[doc = "LCD_DLY_MODE_CFG1 (rw) register accessor: LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_dly_mode_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_dly_mode_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_dly_mode_cfg1`] module"] +pub type LCD_DLY_MODE_CFG1 = crate::Reg; +#[doc = "LCD config register."] +pub mod lcd_dly_mode_cfg1; +#[doc = "LCD_DLY_MODE_CFG2 (rw) register accessor: LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_dly_mode_cfg2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_dly_mode_cfg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcd_dly_mode_cfg2`] module"] +pub type LCD_DLY_MODE_CFG2 = crate::Reg; +#[doc = "LCD config register."] +pub mod lcd_dly_mode_cfg2; +#[doc = "LC_DMA_INT_ENA (rw) register accessor: LCDCAM interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_dma_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lc_dma_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lc_dma_int_ena`] module"] +pub type LC_DMA_INT_ENA = crate::Reg; +#[doc = "LCDCAM interrupt enable register."] +pub mod lc_dma_int_ena; +#[doc = "LC_DMA_INT_RAW (r) register accessor: LCDCAM interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_dma_int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lc_dma_int_raw`] module"] +pub type LC_DMA_INT_RAW = crate::Reg; +#[doc = "LCDCAM interrupt raw register, valid in level."] +pub mod lc_dma_int_raw; +#[doc = "LC_DMA_INT_ST (r) register accessor: LCDCAM interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_dma_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lc_dma_int_st`] module"] +pub type LC_DMA_INT_ST = crate::Reg; +#[doc = "LCDCAM interrupt status register."] +pub mod lc_dma_int_st; +#[doc = "LC_DMA_INT_CLR (w) register accessor: LCDCAM interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lc_dma_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lc_dma_int_clr`] module"] +pub type LC_DMA_INT_CLR = crate::Reg; +#[doc = "LCDCAM interrupt clear register."] +pub mod lc_dma_int_clr; +#[doc = "LC_REG_DATE (rw) register accessor: Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_reg_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lc_reg_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lc_reg_date`] module"] +pub type LC_REG_DATE = crate::Reg; +#[doc = "Version register"] +pub mod lc_reg_date; diff --git a/esp32p4/src/lcd_cam/cam_ctrl.rs b/esp32p4/src/lcd_cam/cam_ctrl.rs new file mode 100644 index 0000000000..c9512a8740 --- /dev/null +++ b/esp32p4/src/lcd_cam/cam_ctrl.rs @@ -0,0 +1,250 @@ +#[doc = "Register `CAM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CAM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CAM_STOP_EN` reader - Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop."] +pub type CAM_STOP_EN_R = crate::BitReader; +#[doc = "Field `CAM_STOP_EN` writer - Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop."] +pub type CAM_STOP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_VSYNC_FILTER_THRES` reader - Filter threshold value for CAM_VSYNC signal."] +pub type CAM_VSYNC_FILTER_THRES_R = crate::FieldReader; +#[doc = "Field `CAM_VSYNC_FILTER_THRES` writer - Filter threshold value for CAM_VSYNC signal."] +pub type CAM_VSYNC_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CAM_UPDATE` reader - 1: Update Camera registers, will be cleared by hardware. 0 : Not care."] +pub type CAM_UPDATE_R = crate::BitReader; +#[doc = "Field `CAM_UPDATE` writer - 1: Update Camera registers, will be cleared by hardware. 0 : Not care."] +pub type CAM_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_BYTE_ORDER` reader - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] +pub type CAM_BYTE_ORDER_R = crate::BitReader; +#[doc = "Field `CAM_BYTE_ORDER` writer - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] +pub type CAM_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_BIT_ORDER` reader - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] +pub type CAM_BIT_ORDER_R = crate::BitReader; +#[doc = "Field `CAM_BIT_ORDER` writer - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] +pub type CAM_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_LINE_INT_EN` reader - 1: Enable to generate CAM_HS_INT. 0: Disable."] +pub type CAM_LINE_INT_EN_R = crate::BitReader; +#[doc = "Field `CAM_LINE_INT_EN` writer - 1: Enable to generate CAM_HS_INT. 0: Disable."] +pub type CAM_LINE_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_VS_EOF_EN` reader - 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen."] +pub type CAM_VS_EOF_EN_R = crate::BitReader; +#[doc = "Field `CAM_VS_EOF_EN` writer - 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen."] +pub type CAM_VS_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_CLKM_DIV_NUM` reader - Integral Camera clock divider value"] +pub type CAM_CLKM_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `CAM_CLKM_DIV_NUM` writer - Integral Camera clock divider value"] +pub type CAM_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CAM_CLKM_DIV_B` reader - Fractional clock divider numerator value"] +pub type CAM_CLKM_DIV_B_R = crate::FieldReader; +#[doc = "Field `CAM_CLKM_DIV_B` writer - Fractional clock divider numerator value"] +pub type CAM_CLKM_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `CAM_CLKM_DIV_A` reader - Fractional clock divider denominator value"] +pub type CAM_CLKM_DIV_A_R = crate::FieldReader; +#[doc = "Field `CAM_CLKM_DIV_A` writer - Fractional clock divider denominator value"] +pub type CAM_CLKM_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `CAM_CLK_SEL` reader - Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock."] +pub type CAM_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `CAM_CLK_SEL` writer - Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock."] +pub type CAM_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop."] + #[inline(always)] + pub fn cam_stop_en(&self) -> CAM_STOP_EN_R { + CAM_STOP_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Filter threshold value for CAM_VSYNC signal."] + #[inline(always)] + pub fn cam_vsync_filter_thres(&self) -> CAM_VSYNC_FILTER_THRES_R { + CAM_VSYNC_FILTER_THRES_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - 1: Update Camera registers, will be cleared by hardware. 0 : Not care."] + #[inline(always)] + pub fn cam_update(&self) -> CAM_UPDATE_R { + CAM_UPDATE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] + #[inline(always)] + pub fn cam_byte_order(&self) -> CAM_BYTE_ORDER_R { + CAM_BYTE_ORDER_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] + #[inline(always)] + pub fn cam_bit_order(&self) -> CAM_BIT_ORDER_R { + CAM_BIT_ORDER_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 1: Enable to generate CAM_HS_INT. 0: Disable."] + #[inline(always)] + pub fn cam_line_int_en(&self) -> CAM_LINE_INT_EN_R { + CAM_LINE_INT_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen."] + #[inline(always)] + pub fn cam_vs_eof_en(&self) -> CAM_VS_EOF_EN_R { + CAM_VS_EOF_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:16 - Integral Camera clock divider value"] + #[inline(always)] + pub fn cam_clkm_div_num(&self) -> CAM_CLKM_DIV_NUM_R { + CAM_CLKM_DIV_NUM_R::new(((self.bits >> 9) & 0xff) as u8) + } + #[doc = "Bits 17:22 - Fractional clock divider numerator value"] + #[inline(always)] + pub fn cam_clkm_div_b(&self) -> CAM_CLKM_DIV_B_R { + CAM_CLKM_DIV_B_R::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bits 23:28 - Fractional clock divider denominator value"] + #[inline(always)] + pub fn cam_clkm_div_a(&self) -> CAM_CLKM_DIV_A_R { + CAM_CLKM_DIV_A_R::new(((self.bits >> 23) & 0x3f) as u8) + } + #[doc = "Bits 29:30 - Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock."] + #[inline(always)] + pub fn cam_clk_sel(&self) -> CAM_CLK_SEL_R { + CAM_CLK_SEL_R::new(((self.bits >> 29) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAM_CTRL") + .field("cam_stop_en", &format_args!("{}", self.cam_stop_en().bit())) + .field( + "cam_vsync_filter_thres", + &format_args!("{}", self.cam_vsync_filter_thres().bits()), + ) + .field("cam_update", &format_args!("{}", self.cam_update().bit())) + .field( + "cam_byte_order", + &format_args!("{}", self.cam_byte_order().bit()), + ) + .field( + "cam_bit_order", + &format_args!("{}", self.cam_bit_order().bit()), + ) + .field( + "cam_line_int_en", + &format_args!("{}", self.cam_line_int_en().bit()), + ) + .field( + "cam_vs_eof_en", + &format_args!("{}", self.cam_vs_eof_en().bit()), + ) + .field( + "cam_clkm_div_num", + &format_args!("{}", self.cam_clkm_div_num().bits()), + ) + .field( + "cam_clkm_div_b", + &format_args!("{}", self.cam_clkm_div_b().bits()), + ) + .field( + "cam_clkm_div_a", + &format_args!("{}", self.cam_clkm_div_a().bits()), + ) + .field( + "cam_clk_sel", + &format_args!("{}", self.cam_clk_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop."] + #[inline(always)] + #[must_use] + pub fn cam_stop_en(&mut self) -> CAM_STOP_EN_W { + CAM_STOP_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - Filter threshold value for CAM_VSYNC signal."] + #[inline(always)] + #[must_use] + pub fn cam_vsync_filter_thres(&mut self) -> CAM_VSYNC_FILTER_THRES_W { + CAM_VSYNC_FILTER_THRES_W::new(self, 1) + } + #[doc = "Bit 4 - 1: Update Camera registers, will be cleared by hardware. 0 : Not care."] + #[inline(always)] + #[must_use] + pub fn cam_update(&mut self) -> CAM_UPDATE_W { + CAM_UPDATE_W::new(self, 4) + } + #[doc = "Bit 5 - 1: Change data bit order, change CAM_DATA_in\\[7:0\\] to CAM_DATA_in\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] + #[inline(always)] + #[must_use] + pub fn cam_byte_order(&mut self) -> CAM_BYTE_ORDER_W { + CAM_BYTE_ORDER_W::new(self, 5) + } + #[doc = "Bit 6 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] + #[inline(always)] + #[must_use] + pub fn cam_bit_order(&mut self) -> CAM_BIT_ORDER_W { + CAM_BIT_ORDER_W::new(self, 6) + } + #[doc = "Bit 7 - 1: Enable to generate CAM_HS_INT. 0: Disable."] + #[inline(always)] + #[must_use] + pub fn cam_line_int_en(&mut self) -> CAM_LINE_INT_EN_W { + CAM_LINE_INT_EN_W::new(self, 7) + } + #[doc = "Bit 8 - 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen."] + #[inline(always)] + #[must_use] + pub fn cam_vs_eof_en(&mut self) -> CAM_VS_EOF_EN_W { + CAM_VS_EOF_EN_W::new(self, 8) + } + #[doc = "Bits 9:16 - Integral Camera clock divider value"] + #[inline(always)] + #[must_use] + pub fn cam_clkm_div_num(&mut self) -> CAM_CLKM_DIV_NUM_W { + CAM_CLKM_DIV_NUM_W::new(self, 9) + } + #[doc = "Bits 17:22 - Fractional clock divider numerator value"] + #[inline(always)] + #[must_use] + pub fn cam_clkm_div_b(&mut self) -> CAM_CLKM_DIV_B_W { + CAM_CLKM_DIV_B_W::new(self, 17) + } + #[doc = "Bits 23:28 - Fractional clock divider denominator value"] + #[inline(always)] + #[must_use] + pub fn cam_clkm_div_a(&mut self) -> CAM_CLKM_DIV_A_W { + CAM_CLKM_DIV_A_W::new(self, 23) + } + #[doc = "Bits 29:30 - Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock."] + #[inline(always)] + #[must_use] + pub fn cam_clk_sel(&mut self) -> CAM_CLK_SEL_W { + CAM_CLK_SEL_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "CAM config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cam_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cam_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAM_CTRL_SPEC; +impl crate::RegisterSpec for CAM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cam_ctrl::R`](R) reader structure"] +impl crate::Readable for CAM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cam_ctrl::W`](W) writer structure"] +impl crate::Writable for CAM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAM_CTRL to value 0x0800"] +impl crate::Resettable for CAM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0800; +} diff --git a/esp32p4/src/lcd_cam/cam_ctrl1.rs b/esp32p4/src/lcd_cam/cam_ctrl1.rs new file mode 100644 index 0000000000..b5bf160df1 --- /dev/null +++ b/esp32p4/src/lcd_cam/cam_ctrl1.rs @@ -0,0 +1,244 @@ +#[doc = "Register `CAM_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `CAM_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `CAM_REC_DATA_BYTELEN` reader - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."] +pub type CAM_REC_DATA_BYTELEN_R = crate::FieldReader; +#[doc = "Field `CAM_REC_DATA_BYTELEN` writer - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."] +pub type CAM_REC_DATA_BYTELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CAM_LINE_INT_NUM` reader - The line number minus 1 to generate cam_hs_int."] +pub type CAM_LINE_INT_NUM_R = crate::FieldReader; +#[doc = "Field `CAM_LINE_INT_NUM` writer - The line number minus 1 to generate cam_hs_int."] +pub type CAM_LINE_INT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `CAM_CLK_INV` reader - 1: Invert the input signal CAM_PCLK. 0: Not invert."] +pub type CAM_CLK_INV_R = crate::BitReader; +#[doc = "Field `CAM_CLK_INV` writer - 1: Invert the input signal CAM_PCLK. 0: Not invert."] +pub type CAM_CLK_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_VSYNC_FILTER_EN` reader - 1: Enable CAM_VSYNC filter function. 0: bypass."] +pub type CAM_VSYNC_FILTER_EN_R = crate::BitReader; +#[doc = "Field `CAM_VSYNC_FILTER_EN` writer - 1: Enable CAM_VSYNC filter function. 0: bypass."] +pub type CAM_VSYNC_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_2BYTE_EN` reader - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."] +pub type CAM_2BYTE_EN_R = crate::BitReader; +#[doc = "Field `CAM_2BYTE_EN` writer - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."] +pub type CAM_2BYTE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_DE_INV` reader - CAM_DE invert enable signal, valid in high level."] +pub type CAM_DE_INV_R = crate::BitReader; +#[doc = "Field `CAM_DE_INV` writer - CAM_DE invert enable signal, valid in high level."] +pub type CAM_DE_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_HSYNC_INV` reader - CAM_HSYNC invert enable signal, valid in high level."] +pub type CAM_HSYNC_INV_R = crate::BitReader; +#[doc = "Field `CAM_HSYNC_INV` writer - CAM_HSYNC invert enable signal, valid in high level."] +pub type CAM_HSYNC_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_VSYNC_INV` reader - CAM_VSYNC invert enable signal, valid in high level."] +pub type CAM_VSYNC_INV_R = crate::BitReader; +#[doc = "Field `CAM_VSYNC_INV` writer - CAM_VSYNC invert enable signal, valid in high level."] +pub type CAM_VSYNC_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_VH_DE_MODE_EN` reader - 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC."] +pub type CAM_VH_DE_MODE_EN_R = crate::BitReader; +#[doc = "Field `CAM_VH_DE_MODE_EN` writer - 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC."] +pub type CAM_VH_DE_MODE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_START` reader - Camera module start signal."] +pub type CAM_START_R = crate::BitReader; +#[doc = "Field `CAM_START` writer - Camera module start signal."] +pub type CAM_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_RESET` writer - Camera module reset signal."] +pub type CAM_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_AFIFO_RESET` writer - Camera AFIFO reset signal."] +pub type CAM_AFIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."] + #[inline(always)] + pub fn cam_rec_data_bytelen(&self) -> CAM_REC_DATA_BYTELEN_R { + CAM_REC_DATA_BYTELEN_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:21 - The line number minus 1 to generate cam_hs_int."] + #[inline(always)] + pub fn cam_line_int_num(&self) -> CAM_LINE_INT_NUM_R { + CAM_LINE_INT_NUM_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bit 22 - 1: Invert the input signal CAM_PCLK. 0: Not invert."] + #[inline(always)] + pub fn cam_clk_inv(&self) -> CAM_CLK_INV_R { + CAM_CLK_INV_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - 1: Enable CAM_VSYNC filter function. 0: bypass."] + #[inline(always)] + pub fn cam_vsync_filter_en(&self) -> CAM_VSYNC_FILTER_EN_R { + CAM_VSYNC_FILTER_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."] + #[inline(always)] + pub fn cam_2byte_en(&self) -> CAM_2BYTE_EN_R { + CAM_2BYTE_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - CAM_DE invert enable signal, valid in high level."] + #[inline(always)] + pub fn cam_de_inv(&self) -> CAM_DE_INV_R { + CAM_DE_INV_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - CAM_HSYNC invert enable signal, valid in high level."] + #[inline(always)] + pub fn cam_hsync_inv(&self) -> CAM_HSYNC_INV_R { + CAM_HSYNC_INV_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - CAM_VSYNC invert enable signal, valid in high level."] + #[inline(always)] + pub fn cam_vsync_inv(&self) -> CAM_VSYNC_INV_R { + CAM_VSYNC_INV_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC."] + #[inline(always)] + pub fn cam_vh_de_mode_en(&self) -> CAM_VH_DE_MODE_EN_R { + CAM_VH_DE_MODE_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Camera module start signal."] + #[inline(always)] + pub fn cam_start(&self) -> CAM_START_R { + CAM_START_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAM_CTRL1") + .field( + "cam_rec_data_bytelen", + &format_args!("{}", self.cam_rec_data_bytelen().bits()), + ) + .field( + "cam_line_int_num", + &format_args!("{}", self.cam_line_int_num().bits()), + ) + .field("cam_clk_inv", &format_args!("{}", self.cam_clk_inv().bit())) + .field( + "cam_vsync_filter_en", + &format_args!("{}", self.cam_vsync_filter_en().bit()), + ) + .field( + "cam_2byte_en", + &format_args!("{}", self.cam_2byte_en().bit()), + ) + .field("cam_de_inv", &format_args!("{}", self.cam_de_inv().bit())) + .field( + "cam_hsync_inv", + &format_args!("{}", self.cam_hsync_inv().bit()), + ) + .field( + "cam_vsync_inv", + &format_args!("{}", self.cam_vsync_inv().bit()), + ) + .field( + "cam_vh_de_mode_en", + &format_args!("{}", self.cam_vh_de_mode_en().bit()), + ) + .field("cam_start", &format_args!("{}", self.cam_start().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."] + #[inline(always)] + #[must_use] + pub fn cam_rec_data_bytelen(&mut self) -> CAM_REC_DATA_BYTELEN_W { + CAM_REC_DATA_BYTELEN_W::new(self, 0) + } + #[doc = "Bits 16:21 - The line number minus 1 to generate cam_hs_int."] + #[inline(always)] + #[must_use] + pub fn cam_line_int_num(&mut self) -> CAM_LINE_INT_NUM_W { + CAM_LINE_INT_NUM_W::new(self, 16) + } + #[doc = "Bit 22 - 1: Invert the input signal CAM_PCLK. 0: Not invert."] + #[inline(always)] + #[must_use] + pub fn cam_clk_inv(&mut self) -> CAM_CLK_INV_W { + CAM_CLK_INV_W::new(self, 22) + } + #[doc = "Bit 23 - 1: Enable CAM_VSYNC filter function. 0: bypass."] + #[inline(always)] + #[must_use] + pub fn cam_vsync_filter_en(&mut self) -> CAM_VSYNC_FILTER_EN_W { + CAM_VSYNC_FILTER_EN_W::new(self, 23) + } + #[doc = "Bit 24 - 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8."] + #[inline(always)] + #[must_use] + pub fn cam_2byte_en(&mut self) -> CAM_2BYTE_EN_W { + CAM_2BYTE_EN_W::new(self, 24) + } + #[doc = "Bit 25 - CAM_DE invert enable signal, valid in high level."] + #[inline(always)] + #[must_use] + pub fn cam_de_inv(&mut self) -> CAM_DE_INV_W { + CAM_DE_INV_W::new(self, 25) + } + #[doc = "Bit 26 - CAM_HSYNC invert enable signal, valid in high level."] + #[inline(always)] + #[must_use] + pub fn cam_hsync_inv(&mut self) -> CAM_HSYNC_INV_W { + CAM_HSYNC_INV_W::new(self, 26) + } + #[doc = "Bit 27 - CAM_VSYNC invert enable signal, valid in high level."] + #[inline(always)] + #[must_use] + pub fn cam_vsync_inv(&mut self) -> CAM_VSYNC_INV_W { + CAM_VSYNC_INV_W::new(self, 27) + } + #[doc = "Bit 28 - 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC."] + #[inline(always)] + #[must_use] + pub fn cam_vh_de_mode_en(&mut self) -> CAM_VH_DE_MODE_EN_W { + CAM_VH_DE_MODE_EN_W::new(self, 28) + } + #[doc = "Bit 29 - Camera module start signal."] + #[inline(always)] + #[must_use] + pub fn cam_start(&mut self) -> CAM_START_W { + CAM_START_W::new(self, 29) + } + #[doc = "Bit 30 - Camera module reset signal."] + #[inline(always)] + #[must_use] + pub fn cam_reset(&mut self) -> CAM_RESET_W { + CAM_RESET_W::new(self, 30) + } + #[doc = "Bit 31 - Camera AFIFO reset signal."] + #[inline(always)] + #[must_use] + pub fn cam_afifo_reset(&mut self) -> CAM_AFIFO_RESET_W { + CAM_AFIFO_RESET_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "CAM config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cam_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cam_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAM_CTRL1_SPEC; +impl crate::RegisterSpec for CAM_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cam_ctrl1::R`](R) reader structure"] +impl crate::Readable for CAM_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cam_ctrl1::W`](W) writer structure"] +impl crate::Writable for CAM_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAM_CTRL1 to value 0"] +impl crate::Resettable for CAM_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lcd_cam/cam_rgb_yuv.rs b/esp32p4/src/lcd_cam/cam_rgb_yuv.rs new file mode 100644 index 0000000000..b7639c1896 --- /dev/null +++ b/esp32p4/src/lcd_cam/cam_rgb_yuv.rs @@ -0,0 +1,218 @@ +#[doc = "Register `CAM_RGB_YUV` reader"] +pub type R = crate::R; +#[doc = "Register `CAM_RGB_YUV` writer"] +pub type W = crate::W; +#[doc = "Field `CAM_CONV_8BITS_DATA_INV` reader - 1:invert every two 8bits input data. 2. disabled."] +pub type CAM_CONV_8BITS_DATA_INV_R = crate::BitReader; +#[doc = "Field `CAM_CONV_8BITS_DATA_INV` writer - 1:invert every two 8bits input data. 2. disabled."] +pub type CAM_CONV_8BITS_DATA_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_CONV_YUV2YUV_MODE` reader - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1."] +pub type CAM_CONV_YUV2YUV_MODE_R = crate::FieldReader; +#[doc = "Field `CAM_CONV_YUV2YUV_MODE` writer - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1."] +pub type CAM_CONV_YUV2YUV_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CAM_CONV_YUV_MODE` reader - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in"] +pub type CAM_CONV_YUV_MODE_R = crate::FieldReader; +#[doc = "Field `CAM_CONV_YUV_MODE` writer - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in"] +pub type CAM_CONV_YUV_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CAM_CONV_PROTOCOL_MODE` reader - 0:BT601. 1:BT709."] +pub type CAM_CONV_PROTOCOL_MODE_R = crate::BitReader; +#[doc = "Field `CAM_CONV_PROTOCOL_MODE` writer - 0:BT601. 1:BT709."] +pub type CAM_CONV_PROTOCOL_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_CONV_DATA_OUT_MODE` reader - LIMIT or FULL mode of Data out. 0: limit. 1: full"] +pub type CAM_CONV_DATA_OUT_MODE_R = crate::BitReader; +#[doc = "Field `CAM_CONV_DATA_OUT_MODE` writer - LIMIT or FULL mode of Data out. 0: limit. 1: full"] +pub type CAM_CONV_DATA_OUT_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_CONV_DATA_IN_MODE` reader - LIMIT or FULL mode of Data in. 0: limit. 1: full"] +pub type CAM_CONV_DATA_IN_MODE_R = crate::BitReader; +#[doc = "Field `CAM_CONV_DATA_IN_MODE` writer - LIMIT or FULL mode of Data in. 0: limit. 1: full"] +pub type CAM_CONV_DATA_IN_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_CONV_MODE_8BITS_ON` reader - 0: 16bits mode. 1: 8bits mode."] +pub type CAM_CONV_MODE_8BITS_ON_R = crate::BitReader; +#[doc = "Field `CAM_CONV_MODE_8BITS_ON` writer - 0: 16bits mode. 1: 8bits mode."] +pub type CAM_CONV_MODE_8BITS_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_CONV_TRANS_MODE` reader - 0: YUV to RGB. 1: RGB to YUV."] +pub type CAM_CONV_TRANS_MODE_R = crate::BitReader; +#[doc = "Field `CAM_CONV_TRANS_MODE` writer - 0: YUV to RGB. 1: RGB to YUV."] +pub type CAM_CONV_TRANS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_CONV_ENABLE` reader - 0: Bypass converter. 1: Enable converter."] +pub type CAM_CONV_ENABLE_R = crate::BitReader; +#[doc = "Field `CAM_CONV_ENABLE` writer - 0: Bypass converter. 1: Enable converter."] +pub type CAM_CONV_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 21 - 1:invert every two 8bits input data. 2. disabled."] + #[inline(always)] + pub fn cam_conv_8bits_data_inv(&self) -> CAM_CONV_8BITS_DATA_INV_R { + CAM_CONV_8BITS_DATA_INV_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 22:23 - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1."] + #[inline(always)] + pub fn cam_conv_yuv2yuv_mode(&self) -> CAM_CONV_YUV2YUV_MODE_R { + CAM_CONV_YUV2YUV_MODE_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in"] + #[inline(always)] + pub fn cam_conv_yuv_mode(&self) -> CAM_CONV_YUV_MODE_R { + CAM_CONV_YUV_MODE_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - 0:BT601. 1:BT709."] + #[inline(always)] + pub fn cam_conv_protocol_mode(&self) -> CAM_CONV_PROTOCOL_MODE_R { + CAM_CONV_PROTOCOL_MODE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - LIMIT or FULL mode of Data out. 0: limit. 1: full"] + #[inline(always)] + pub fn cam_conv_data_out_mode(&self) -> CAM_CONV_DATA_OUT_MODE_R { + CAM_CONV_DATA_OUT_MODE_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - LIMIT or FULL mode of Data in. 0: limit. 1: full"] + #[inline(always)] + pub fn cam_conv_data_in_mode(&self) -> CAM_CONV_DATA_IN_MODE_R { + CAM_CONV_DATA_IN_MODE_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - 0: 16bits mode. 1: 8bits mode."] + #[inline(always)] + pub fn cam_conv_mode_8bits_on(&self) -> CAM_CONV_MODE_8BITS_ON_R { + CAM_CONV_MODE_8BITS_ON_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - 0: YUV to RGB. 1: RGB to YUV."] + #[inline(always)] + pub fn cam_conv_trans_mode(&self) -> CAM_CONV_TRANS_MODE_R { + CAM_CONV_TRANS_MODE_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 0: Bypass converter. 1: Enable converter."] + #[inline(always)] + pub fn cam_conv_enable(&self) -> CAM_CONV_ENABLE_R { + CAM_CONV_ENABLE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAM_RGB_YUV") + .field( + "cam_conv_8bits_data_inv", + &format_args!("{}", self.cam_conv_8bits_data_inv().bit()), + ) + .field( + "cam_conv_yuv2yuv_mode", + &format_args!("{}", self.cam_conv_yuv2yuv_mode().bits()), + ) + .field( + "cam_conv_yuv_mode", + &format_args!("{}", self.cam_conv_yuv_mode().bits()), + ) + .field( + "cam_conv_protocol_mode", + &format_args!("{}", self.cam_conv_protocol_mode().bit()), + ) + .field( + "cam_conv_data_out_mode", + &format_args!("{}", self.cam_conv_data_out_mode().bit()), + ) + .field( + "cam_conv_data_in_mode", + &format_args!("{}", self.cam_conv_data_in_mode().bit()), + ) + .field( + "cam_conv_mode_8bits_on", + &format_args!("{}", self.cam_conv_mode_8bits_on().bit()), + ) + .field( + "cam_conv_trans_mode", + &format_args!("{}", self.cam_conv_trans_mode().bit()), + ) + .field( + "cam_conv_enable", + &format_args!("{}", self.cam_conv_enable().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 21 - 1:invert every two 8bits input data. 2. disabled."] + #[inline(always)] + #[must_use] + pub fn cam_conv_8bits_data_inv(&mut self) -> CAM_CONV_8BITS_DATA_INV_W { + CAM_CONV_8BITS_DATA_INV_W::new(self, 21) + } + #[doc = "Bits 22:23 - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1."] + #[inline(always)] + #[must_use] + pub fn cam_conv_yuv2yuv_mode(&mut self) -> CAM_CONV_YUV2YUV_MODE_W { + CAM_CONV_YUV2YUV_MODE_W::new(self, 22) + } + #[doc = "Bits 24:25 - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in"] + #[inline(always)] + #[must_use] + pub fn cam_conv_yuv_mode(&mut self) -> CAM_CONV_YUV_MODE_W { + CAM_CONV_YUV_MODE_W::new(self, 24) + } + #[doc = "Bit 26 - 0:BT601. 1:BT709."] + #[inline(always)] + #[must_use] + pub fn cam_conv_protocol_mode(&mut self) -> CAM_CONV_PROTOCOL_MODE_W { + CAM_CONV_PROTOCOL_MODE_W::new(self, 26) + } + #[doc = "Bit 27 - LIMIT or FULL mode of Data out. 0: limit. 1: full"] + #[inline(always)] + #[must_use] + pub fn cam_conv_data_out_mode(&mut self) -> CAM_CONV_DATA_OUT_MODE_W { + CAM_CONV_DATA_OUT_MODE_W::new(self, 27) + } + #[doc = "Bit 28 - LIMIT or FULL mode of Data in. 0: limit. 1: full"] + #[inline(always)] + #[must_use] + pub fn cam_conv_data_in_mode(&mut self) -> CAM_CONV_DATA_IN_MODE_W { + CAM_CONV_DATA_IN_MODE_W::new(self, 28) + } + #[doc = "Bit 29 - 0: 16bits mode. 1: 8bits mode."] + #[inline(always)] + #[must_use] + pub fn cam_conv_mode_8bits_on(&mut self) -> CAM_CONV_MODE_8BITS_ON_W { + CAM_CONV_MODE_8BITS_ON_W::new(self, 29) + } + #[doc = "Bit 30 - 0: YUV to RGB. 1: RGB to YUV."] + #[inline(always)] + #[must_use] + pub fn cam_conv_trans_mode(&mut self) -> CAM_CONV_TRANS_MODE_W { + CAM_CONV_TRANS_MODE_W::new(self, 30) + } + #[doc = "Bit 31 - 0: Bypass converter. 1: Enable converter."] + #[inline(always)] + #[must_use] + pub fn cam_conv_enable(&mut self) -> CAM_CONV_ENABLE_W { + CAM_CONV_ENABLE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "CAM YUV/RGB converter configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cam_rgb_yuv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cam_rgb_yuv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAM_RGB_YUV_SPEC; +impl crate::RegisterSpec for CAM_RGB_YUV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cam_rgb_yuv::R`](R) reader structure"] +impl crate::Readable for CAM_RGB_YUV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cam_rgb_yuv::W`](W) writer structure"] +impl crate::Writable for CAM_RGB_YUV_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAM_RGB_YUV to value 0x00c0_0000"] +impl crate::Resettable for CAM_RGB_YUV_SPEC { + const RESET_VALUE: Self::Ux = 0x00c0_0000; +} diff --git a/esp32p4/src/lcd_cam/lc_dma_int_clr.rs b/esp32p4/src/lcd_cam/lc_dma_int_clr.rs new file mode 100644 index 0000000000..530d714d88 --- /dev/null +++ b/esp32p4/src/lcd_cam/lc_dma_int_clr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LC_DMA_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `LCD_VSYNC_INT_CLR` writer - The clear bit for LCD frame end interrupt."] +pub type LCD_VSYNC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_TRANS_DONE_INT_CLR` writer - The clear bit for lcd transfer end interrupt."] +pub type LCD_TRANS_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_VSYNC_INT_CLR` writer - The clear bit for Camera frame end interrupt."] +pub type CAM_VSYNC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_HS_INT_CLR` writer - The clear bit for Camera line interrupt."] +pub type CAM_HS_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - The clear bit for LCD frame end interrupt."] + #[inline(always)] + #[must_use] + pub fn lcd_vsync_int_clr(&mut self) -> LCD_VSYNC_INT_CLR_W { + LCD_VSYNC_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - The clear bit for lcd transfer end interrupt."] + #[inline(always)] + #[must_use] + pub fn lcd_trans_done_int_clr(&mut self) -> LCD_TRANS_DONE_INT_CLR_W { + LCD_TRANS_DONE_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - The clear bit for Camera frame end interrupt."] + #[inline(always)] + #[must_use] + pub fn cam_vsync_int_clr(&mut self) -> CAM_VSYNC_INT_CLR_W { + CAM_VSYNC_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - The clear bit for Camera line interrupt."] + #[inline(always)] + #[must_use] + pub fn cam_hs_int_clr(&mut self) -> CAM_HS_INT_CLR_W { + CAM_HS_INT_CLR_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCDCAM interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lc_dma_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LC_DMA_INT_CLR_SPEC; +impl crate::RegisterSpec for LC_DMA_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`lc_dma_int_clr::W`](W) writer structure"] +impl crate::Writable for LC_DMA_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LC_DMA_INT_CLR to value 0"] +impl crate::Resettable for LC_DMA_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lcd_cam/lc_dma_int_ena.rs b/esp32p4/src/lcd_cam/lc_dma_int_ena.rs new file mode 100644 index 0000000000..b5a1505a01 --- /dev/null +++ b/esp32p4/src/lcd_cam/lc_dma_int_ena.rs @@ -0,0 +1,123 @@ +#[doc = "Register `LC_DMA_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `LC_DMA_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `LCD_VSYNC_INT_ENA` reader - The enable bit for LCD frame end interrupt."] +pub type LCD_VSYNC_INT_ENA_R = crate::BitReader; +#[doc = "Field `LCD_VSYNC_INT_ENA` writer - The enable bit for LCD frame end interrupt."] +pub type LCD_VSYNC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_TRANS_DONE_INT_ENA` reader - The enable bit for lcd transfer end interrupt."] +pub type LCD_TRANS_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `LCD_TRANS_DONE_INT_ENA` writer - The enable bit for lcd transfer end interrupt."] +pub type LCD_TRANS_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_VSYNC_INT_ENA` reader - The enable bit for Camera frame end interrupt."] +pub type CAM_VSYNC_INT_ENA_R = crate::BitReader; +#[doc = "Field `CAM_VSYNC_INT_ENA` writer - The enable bit for Camera frame end interrupt."] +pub type CAM_VSYNC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAM_HS_INT_ENA` reader - The enable bit for Camera line interrupt."] +pub type CAM_HS_INT_ENA_R = crate::BitReader; +#[doc = "Field `CAM_HS_INT_ENA` writer - The enable bit for Camera line interrupt."] +pub type CAM_HS_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The enable bit for LCD frame end interrupt."] + #[inline(always)] + pub fn lcd_vsync_int_ena(&self) -> LCD_VSYNC_INT_ENA_R { + LCD_VSYNC_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The enable bit for lcd transfer end interrupt."] + #[inline(always)] + pub fn lcd_trans_done_int_ena(&self) -> LCD_TRANS_DONE_INT_ENA_R { + LCD_TRANS_DONE_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The enable bit for Camera frame end interrupt."] + #[inline(always)] + pub fn cam_vsync_int_ena(&self) -> CAM_VSYNC_INT_ENA_R { + CAM_VSYNC_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The enable bit for Camera line interrupt."] + #[inline(always)] + pub fn cam_hs_int_ena(&self) -> CAM_HS_INT_ENA_R { + CAM_HS_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LC_DMA_INT_ENA") + .field( + "lcd_vsync_int_ena", + &format_args!("{}", self.lcd_vsync_int_ena().bit()), + ) + .field( + "lcd_trans_done_int_ena", + &format_args!("{}", self.lcd_trans_done_int_ena().bit()), + ) + .field( + "cam_vsync_int_ena", + &format_args!("{}", self.cam_vsync_int_ena().bit()), + ) + .field( + "cam_hs_int_ena", + &format_args!("{}", self.cam_hs_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The enable bit for LCD frame end interrupt."] + #[inline(always)] + #[must_use] + pub fn lcd_vsync_int_ena(&mut self) -> LCD_VSYNC_INT_ENA_W { + LCD_VSYNC_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The enable bit for lcd transfer end interrupt."] + #[inline(always)] + #[must_use] + pub fn lcd_trans_done_int_ena(&mut self) -> LCD_TRANS_DONE_INT_ENA_W { + LCD_TRANS_DONE_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The enable bit for Camera frame end interrupt."] + #[inline(always)] + #[must_use] + pub fn cam_vsync_int_ena(&mut self) -> CAM_VSYNC_INT_ENA_W { + CAM_VSYNC_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The enable bit for Camera line interrupt."] + #[inline(always)] + #[must_use] + pub fn cam_hs_int_ena(&mut self) -> CAM_HS_INT_ENA_W { + CAM_HS_INT_ENA_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCDCAM interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_dma_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lc_dma_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LC_DMA_INT_ENA_SPEC; +impl crate::RegisterSpec for LC_DMA_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lc_dma_int_ena::R`](R) reader structure"] +impl crate::Readable for LC_DMA_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lc_dma_int_ena::W`](W) writer structure"] +impl crate::Writable for LC_DMA_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LC_DMA_INT_ENA to value 0"] +impl crate::Resettable for LC_DMA_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lcd_cam/lc_dma_int_raw.rs b/esp32p4/src/lcd_cam/lc_dma_int_raw.rs new file mode 100644 index 0000000000..89eb1c6371 --- /dev/null +++ b/esp32p4/src/lcd_cam/lc_dma_int_raw.rs @@ -0,0 +1,72 @@ +#[doc = "Register `LC_DMA_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `LCD_VSYNC_INT_RAW` reader - The raw bit for LCD frame end interrupt."] +pub type LCD_VSYNC_INT_RAW_R = crate::BitReader; +#[doc = "Field `LCD_TRANS_DONE_INT_RAW` reader - The raw bit for lcd transfer end interrupt."] +pub type LCD_TRANS_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `CAM_VSYNC_INT_RAW` reader - The raw bit for Camera frame end interrupt."] +pub type CAM_VSYNC_INT_RAW_R = crate::BitReader; +#[doc = "Field `CAM_HS_INT_RAW` reader - The raw bit for Camera line interrupt."] +pub type CAM_HS_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw bit for LCD frame end interrupt."] + #[inline(always)] + pub fn lcd_vsync_int_raw(&self) -> LCD_VSYNC_INT_RAW_R { + LCD_VSYNC_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw bit for lcd transfer end interrupt."] + #[inline(always)] + pub fn lcd_trans_done_int_raw(&self) -> LCD_TRANS_DONE_INT_RAW_R { + LCD_TRANS_DONE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw bit for Camera frame end interrupt."] + #[inline(always)] + pub fn cam_vsync_int_raw(&self) -> CAM_VSYNC_INT_RAW_R { + CAM_VSYNC_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw bit for Camera line interrupt."] + #[inline(always)] + pub fn cam_hs_int_raw(&self) -> CAM_HS_INT_RAW_R { + CAM_HS_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LC_DMA_INT_RAW") + .field( + "lcd_vsync_int_raw", + &format_args!("{}", self.lcd_vsync_int_raw().bit()), + ) + .field( + "lcd_trans_done_int_raw", + &format_args!("{}", self.lcd_trans_done_int_raw().bit()), + ) + .field( + "cam_vsync_int_raw", + &format_args!("{}", self.cam_vsync_int_raw().bit()), + ) + .field( + "cam_hs_int_raw", + &format_args!("{}", self.cam_hs_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "LCDCAM interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_dma_int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LC_DMA_INT_RAW_SPEC; +impl crate::RegisterSpec for LC_DMA_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lc_dma_int_raw::R`](R) reader structure"] +impl crate::Readable for LC_DMA_INT_RAW_SPEC {} +#[doc = "`reset()` method sets LC_DMA_INT_RAW to value 0"] +impl crate::Resettable for LC_DMA_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lcd_cam/lc_dma_int_st.rs b/esp32p4/src/lcd_cam/lc_dma_int_st.rs new file mode 100644 index 0000000000..b4f27484cb --- /dev/null +++ b/esp32p4/src/lcd_cam/lc_dma_int_st.rs @@ -0,0 +1,72 @@ +#[doc = "Register `LC_DMA_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `LCD_VSYNC_INT_ST` reader - The status bit for LCD frame end interrupt."] +pub type LCD_VSYNC_INT_ST_R = crate::BitReader; +#[doc = "Field `LCD_TRANS_DONE_INT_ST` reader - The status bit for lcd transfer end interrupt."] +pub type LCD_TRANS_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `CAM_VSYNC_INT_ST` reader - The status bit for Camera frame end interrupt."] +pub type CAM_VSYNC_INT_ST_R = crate::BitReader; +#[doc = "Field `CAM_HS_INT_ST` reader - The status bit for Camera transfer end interrupt."] +pub type CAM_HS_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The status bit for LCD frame end interrupt."] + #[inline(always)] + pub fn lcd_vsync_int_st(&self) -> LCD_VSYNC_INT_ST_R { + LCD_VSYNC_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The status bit for lcd transfer end interrupt."] + #[inline(always)] + pub fn lcd_trans_done_int_st(&self) -> LCD_TRANS_DONE_INT_ST_R { + LCD_TRANS_DONE_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The status bit for Camera frame end interrupt."] + #[inline(always)] + pub fn cam_vsync_int_st(&self) -> CAM_VSYNC_INT_ST_R { + CAM_VSYNC_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The status bit for Camera transfer end interrupt."] + #[inline(always)] + pub fn cam_hs_int_st(&self) -> CAM_HS_INT_ST_R { + CAM_HS_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LC_DMA_INT_ST") + .field( + "lcd_vsync_int_st", + &format_args!("{}", self.lcd_vsync_int_st().bit()), + ) + .field( + "lcd_trans_done_int_st", + &format_args!("{}", self.lcd_trans_done_int_st().bit()), + ) + .field( + "cam_vsync_int_st", + &format_args!("{}", self.cam_vsync_int_st().bit()), + ) + .field( + "cam_hs_int_st", + &format_args!("{}", self.cam_hs_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "LCDCAM interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_dma_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LC_DMA_INT_ST_SPEC; +impl crate::RegisterSpec for LC_DMA_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lc_dma_int_st::R`](R) reader structure"] +impl crate::Readable for LC_DMA_INT_ST_SPEC {} +#[doc = "`reset()` method sets LC_DMA_INT_ST to value 0"] +impl crate::Resettable for LC_DMA_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lcd_cam/lc_reg_date.rs b/esp32p4/src/lcd_cam/lc_reg_date.rs new file mode 100644 index 0000000000..93d89408bb --- /dev/null +++ b/esp32p4/src/lcd_cam/lc_reg_date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `LC_REG_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `LC_REG_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `LC_DATE` reader - LCD_CAM version control register"] +pub type LC_DATE_R = crate::FieldReader; +#[doc = "Field `LC_DATE` writer - LCD_CAM version control register"] +pub type LC_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - LCD_CAM version control register"] + #[inline(always)] + pub fn lc_date(&self) -> LC_DATE_R { + LC_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LC_REG_DATE") + .field("lc_date", &format_args!("{}", self.lc_date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - LCD_CAM version control register"] + #[inline(always)] + #[must_use] + pub fn lc_date(&mut self) -> LC_DATE_W { + LC_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_reg_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lc_reg_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LC_REG_DATE_SPEC; +impl crate::RegisterSpec for LC_REG_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lc_reg_date::R`](R) reader structure"] +impl crate::Readable for LC_REG_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lc_reg_date::W`](W) writer structure"] +impl crate::Writable for LC_REG_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LC_REG_DATE to value 0x0230_3090"] +impl crate::Resettable for LC_REG_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_3090; +} diff --git a/esp32p4/src/lcd_cam/lcd_clock.rs b/esp32p4/src/lcd_cam/lcd_clock.rs new file mode 100644 index 0000000000..aac6c13422 --- /dev/null +++ b/esp32p4/src/lcd_cam/lcd_clock.rs @@ -0,0 +1,215 @@ +#[doc = "Register `LCD_CLOCK` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_CLOCK` writer"] +pub type W = crate::W; +#[doc = "Field `LCD_CLKCNT_N` reader - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0."] +pub type LCD_CLKCNT_N_R = crate::FieldReader; +#[doc = "Field `LCD_CLKCNT_N` writer - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0."] +pub type LCD_CLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `LCD_CLK_EQU_SYSCLK` reader - 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1)."] +pub type LCD_CLK_EQU_SYSCLK_R = crate::BitReader; +#[doc = "Field `LCD_CLK_EQU_SYSCLK` writer - 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1)."] +pub type LCD_CLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CK_IDLE_EDGE` reader - 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle."] +pub type LCD_CK_IDLE_EDGE_R = crate::BitReader; +#[doc = "Field `LCD_CK_IDLE_EDGE` writer - 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle."] +pub type LCD_CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CK_OUT_EDGE` reader - 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low in the second half data cycle."] +pub type LCD_CK_OUT_EDGE_R = crate::BitReader; +#[doc = "Field `LCD_CK_OUT_EDGE` writer - 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low in the second half data cycle."] +pub type LCD_CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CLKM_DIV_NUM` reader - Integral LCD clock divider value"] +pub type LCD_CLKM_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `LCD_CLKM_DIV_NUM` writer - Integral LCD clock divider value"] +pub type LCD_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LCD_CLKM_DIV_B` reader - Fractional clock divider numerator value"] +pub type LCD_CLKM_DIV_B_R = crate::FieldReader; +#[doc = "Field `LCD_CLKM_DIV_B` writer - Fractional clock divider numerator value"] +pub type LCD_CLKM_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `LCD_CLKM_DIV_A` reader - Fractional clock divider denominator value"] +pub type LCD_CLKM_DIV_A_R = crate::FieldReader; +#[doc = "Field `LCD_CLKM_DIV_A` writer - Fractional clock divider denominator value"] +pub type LCD_CLKM_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `LCD_CLK_SEL` reader - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock."] +pub type LCD_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `LCD_CLK_SEL` writer - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock."] +pub type LCD_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CLK_EN` reader - Set this bit to enable clk gate"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Set this bit to enable clk gate"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0."] + #[inline(always)] + pub fn lcd_clkcnt_n(&self) -> LCD_CLKCNT_N_R { + LCD_CLKCNT_N_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1)."] + #[inline(always)] + pub fn lcd_clk_equ_sysclk(&self) -> LCD_CLK_EQU_SYSCLK_R { + LCD_CLK_EQU_SYSCLK_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle."] + #[inline(always)] + pub fn lcd_ck_idle_edge(&self) -> LCD_CK_IDLE_EDGE_R { + LCD_CK_IDLE_EDGE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low in the second half data cycle."] + #[inline(always)] + pub fn lcd_ck_out_edge(&self) -> LCD_CK_OUT_EDGE_R { + LCD_CK_OUT_EDGE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:16 - Integral LCD clock divider value"] + #[inline(always)] + pub fn lcd_clkm_div_num(&self) -> LCD_CLKM_DIV_NUM_R { + LCD_CLKM_DIV_NUM_R::new(((self.bits >> 9) & 0xff) as u8) + } + #[doc = "Bits 17:22 - Fractional clock divider numerator value"] + #[inline(always)] + pub fn lcd_clkm_div_b(&self) -> LCD_CLKM_DIV_B_R { + LCD_CLKM_DIV_B_R::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bits 23:28 - Fractional clock divider denominator value"] + #[inline(always)] + pub fn lcd_clkm_div_a(&self) -> LCD_CLKM_DIV_A_R { + LCD_CLKM_DIV_A_R::new(((self.bits >> 23) & 0x3f) as u8) + } + #[doc = "Bits 29:30 - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock."] + #[inline(always)] + pub fn lcd_clk_sel(&self) -> LCD_CLK_SEL_R { + LCD_CLK_SEL_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Set this bit to enable clk gate"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_CLOCK") + .field( + "lcd_clkcnt_n", + &format_args!("{}", self.lcd_clkcnt_n().bits()), + ) + .field( + "lcd_clk_equ_sysclk", + &format_args!("{}", self.lcd_clk_equ_sysclk().bit()), + ) + .field( + "lcd_ck_idle_edge", + &format_args!("{}", self.lcd_ck_idle_edge().bit()), + ) + .field( + "lcd_ck_out_edge", + &format_args!("{}", self.lcd_ck_out_edge().bit()), + ) + .field( + "lcd_clkm_div_num", + &format_args!("{}", self.lcd_clkm_div_num().bits()), + ) + .field( + "lcd_clkm_div_b", + &format_args!("{}", self.lcd_clkm_div_b().bits()), + ) + .field( + "lcd_clkm_div_a", + &format_args!("{}", self.lcd_clkm_div_a().bits()), + ) + .field( + "lcd_clk_sel", + &format_args!("{}", self.lcd_clk_sel().bits()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0."] + #[inline(always)] + #[must_use] + pub fn lcd_clkcnt_n(&mut self) -> LCD_CLKCNT_N_W { + LCD_CLKCNT_N_W::new(self, 0) + } + #[doc = "Bit 6 - 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1)."] + #[inline(always)] + #[must_use] + pub fn lcd_clk_equ_sysclk(&mut self) -> LCD_CLK_EQU_SYSCLK_W { + LCD_CLK_EQU_SYSCLK_W::new(self, 6) + } + #[doc = "Bit 7 - 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle."] + #[inline(always)] + #[must_use] + pub fn lcd_ck_idle_edge(&mut self) -> LCD_CK_IDLE_EDGE_W { + LCD_CK_IDLE_EDGE_W::new(self, 7) + } + #[doc = "Bit 8 - 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low in the second half data cycle."] + #[inline(always)] + #[must_use] + pub fn lcd_ck_out_edge(&mut self) -> LCD_CK_OUT_EDGE_W { + LCD_CK_OUT_EDGE_W::new(self, 8) + } + #[doc = "Bits 9:16 - Integral LCD clock divider value"] + #[inline(always)] + #[must_use] + pub fn lcd_clkm_div_num(&mut self) -> LCD_CLKM_DIV_NUM_W { + LCD_CLKM_DIV_NUM_W::new(self, 9) + } + #[doc = "Bits 17:22 - Fractional clock divider numerator value"] + #[inline(always)] + #[must_use] + pub fn lcd_clkm_div_b(&mut self) -> LCD_CLKM_DIV_B_W { + LCD_CLKM_DIV_B_W::new(self, 17) + } + #[doc = "Bits 23:28 - Fractional clock divider denominator value"] + #[inline(always)] + #[must_use] + pub fn lcd_clkm_div_a(&mut self) -> LCD_CLKM_DIV_A_W { + LCD_CLKM_DIV_A_W::new(self, 23) + } + #[doc = "Bits 29:30 - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock."] + #[inline(always)] + #[must_use] + pub fn lcd_clk_sel(&mut self) -> LCD_CLK_SEL_W { + LCD_CLK_SEL_W::new(self, 29) + } + #[doc = "Bit 31 - Set this bit to enable clk gate"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCD clock config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_clock::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_clock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_CLOCK_SPEC; +impl crate::RegisterSpec for LCD_CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_clock::R`](R) reader structure"] +impl crate::Readable for LCD_CLOCK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_clock::W`](W) writer structure"] +impl crate::Writable for LCD_CLOCK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_CLOCK to value 0x0843"] +impl crate::Resettable for LCD_CLOCK_SPEC { + const RESET_VALUE: Self::Ux = 0x0843; +} diff --git a/esp32p4/src/lcd_cam/lcd_ctrl.rs b/esp32p4/src/lcd_cam/lcd_ctrl.rs new file mode 100644 index 0000000000..b450aba5fa --- /dev/null +++ b/esp32p4/src/lcd_cam/lcd_ctrl.rs @@ -0,0 +1,123 @@ +#[doc = "Register `LCD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LCD_HB_FRONT` reader - It is the horizontal blank front porch of a frame."] +pub type LCD_HB_FRONT_R = crate::FieldReader; +#[doc = "Field `LCD_HB_FRONT` writer - It is the horizontal blank front porch of a frame."] +pub type LCD_HB_FRONT_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `LCD_VA_HEIGHT` reader - It is the vertical active height of a frame."] +pub type LCD_VA_HEIGHT_R = crate::FieldReader; +#[doc = "Field `LCD_VA_HEIGHT` writer - It is the vertical active height of a frame."] +pub type LCD_VA_HEIGHT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `LCD_VT_HEIGHT` reader - It is the vertical total height of a frame."] +pub type LCD_VT_HEIGHT_R = crate::FieldReader; +#[doc = "Field `LCD_VT_HEIGHT` writer - It is the vertical total height of a frame."] +pub type LCD_VT_HEIGHT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `LCD_RGB_MODE_EN` reader - 1: Enable LCD RGB mode. 0: Disable LCD RGB mode."] +pub type LCD_RGB_MODE_EN_R = crate::BitReader; +#[doc = "Field `LCD_RGB_MODE_EN` writer - 1: Enable LCD RGB mode. 0: Disable LCD RGB mode."] +pub type LCD_RGB_MODE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:10 - It is the horizontal blank front porch of a frame."] + #[inline(always)] + pub fn lcd_hb_front(&self) -> LCD_HB_FRONT_R { + LCD_HB_FRONT_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bits 11:20 - It is the vertical active height of a frame."] + #[inline(always)] + pub fn lcd_va_height(&self) -> LCD_VA_HEIGHT_R { + LCD_VA_HEIGHT_R::new(((self.bits >> 11) & 0x03ff) as u16) + } + #[doc = "Bits 21:30 - It is the vertical total height of a frame."] + #[inline(always)] + pub fn lcd_vt_height(&self) -> LCD_VT_HEIGHT_R { + LCD_VT_HEIGHT_R::new(((self.bits >> 21) & 0x03ff) as u16) + } + #[doc = "Bit 31 - 1: Enable LCD RGB mode. 0: Disable LCD RGB mode."] + #[inline(always)] + pub fn lcd_rgb_mode_en(&self) -> LCD_RGB_MODE_EN_R { + LCD_RGB_MODE_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_CTRL") + .field( + "lcd_hb_front", + &format_args!("{}", self.lcd_hb_front().bits()), + ) + .field( + "lcd_va_height", + &format_args!("{}", self.lcd_va_height().bits()), + ) + .field( + "lcd_vt_height", + &format_args!("{}", self.lcd_vt_height().bits()), + ) + .field( + "lcd_rgb_mode_en", + &format_args!("{}", self.lcd_rgb_mode_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:10 - It is the horizontal blank front porch of a frame."] + #[inline(always)] + #[must_use] + pub fn lcd_hb_front(&mut self) -> LCD_HB_FRONT_W { + LCD_HB_FRONT_W::new(self, 0) + } + #[doc = "Bits 11:20 - It is the vertical active height of a frame."] + #[inline(always)] + #[must_use] + pub fn lcd_va_height(&mut self) -> LCD_VA_HEIGHT_W { + LCD_VA_HEIGHT_W::new(self, 11) + } + #[doc = "Bits 21:30 - It is the vertical total height of a frame."] + #[inline(always)] + #[must_use] + pub fn lcd_vt_height(&mut self) -> LCD_VT_HEIGHT_W { + LCD_VT_HEIGHT_W::new(self, 21) + } + #[doc = "Bit 31 - 1: Enable LCD RGB mode. 0: Disable LCD RGB mode."] + #[inline(always)] + #[must_use] + pub fn lcd_rgb_mode_en(&mut self) -> LCD_RGB_MODE_EN_W { + LCD_RGB_MODE_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_CTRL_SPEC; +impl crate::RegisterSpec for LCD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_ctrl::R`](R) reader structure"] +impl crate::Readable for LCD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_ctrl::W`](W) writer structure"] +impl crate::Writable for LCD_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_CTRL to value 0"] +impl crate::Resettable for LCD_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lcd_cam/lcd_ctrl1.rs b/esp32p4/src/lcd_cam/lcd_ctrl1.rs new file mode 100644 index 0000000000..f60aed4ef8 --- /dev/null +++ b/esp32p4/src/lcd_cam/lcd_ctrl1.rs @@ -0,0 +1,104 @@ +#[doc = "Register `LCD_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `LCD_VB_FRONT` reader - It is the vertical blank front porch of a frame."] +pub type LCD_VB_FRONT_R = crate::FieldReader; +#[doc = "Field `LCD_VB_FRONT` writer - It is the vertical blank front porch of a frame."] +pub type LCD_VB_FRONT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LCD_HA_WIDTH` reader - It is the horizontal active width of a frame."] +pub type LCD_HA_WIDTH_R = crate::FieldReader; +#[doc = "Field `LCD_HA_WIDTH` writer - It is the horizontal active width of a frame."] +pub type LCD_HA_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `LCD_HT_WIDTH` reader - It is the horizontal total width of a frame."] +pub type LCD_HT_WIDTH_R = crate::FieldReader; +#[doc = "Field `LCD_HT_WIDTH` writer - It is the horizontal total width of a frame."] +pub type LCD_HT_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:7 - It is the vertical blank front porch of a frame."] + #[inline(always)] + pub fn lcd_vb_front(&self) -> LCD_VB_FRONT_R { + LCD_VB_FRONT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:19 - It is the horizontal active width of a frame."] + #[inline(always)] + pub fn lcd_ha_width(&self) -> LCD_HA_WIDTH_R { + LCD_HA_WIDTH_R::new(((self.bits >> 8) & 0x0fff) as u16) + } + #[doc = "Bits 20:31 - It is the horizontal total width of a frame."] + #[inline(always)] + pub fn lcd_ht_width(&self) -> LCD_HT_WIDTH_R { + LCD_HT_WIDTH_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_CTRL1") + .field( + "lcd_vb_front", + &format_args!("{}", self.lcd_vb_front().bits()), + ) + .field( + "lcd_ha_width", + &format_args!("{}", self.lcd_ha_width().bits()), + ) + .field( + "lcd_ht_width", + &format_args!("{}", self.lcd_ht_width().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - It is the vertical blank front porch of a frame."] + #[inline(always)] + #[must_use] + pub fn lcd_vb_front(&mut self) -> LCD_VB_FRONT_W { + LCD_VB_FRONT_W::new(self, 0) + } + #[doc = "Bits 8:19 - It is the horizontal active width of a frame."] + #[inline(always)] + #[must_use] + pub fn lcd_ha_width(&mut self) -> LCD_HA_WIDTH_W { + LCD_HA_WIDTH_W::new(self, 8) + } + #[doc = "Bits 20:31 - It is the horizontal total width of a frame."] + #[inline(always)] + #[must_use] + pub fn lcd_ht_width(&mut self) -> LCD_HT_WIDTH_W { + LCD_HT_WIDTH_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_CTRL1_SPEC; +impl crate::RegisterSpec for LCD_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_ctrl1::R`](R) reader structure"] +impl crate::Readable for LCD_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_ctrl1::W`](W) writer structure"] +impl crate::Writable for LCD_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_CTRL1 to value 0"] +impl crate::Resettable for LCD_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lcd_cam/lcd_ctrl2.rs b/esp32p4/src/lcd_cam/lcd_ctrl2.rs new file mode 100644 index 0000000000..b85d2cadab --- /dev/null +++ b/esp32p4/src/lcd_cam/lcd_ctrl2.rs @@ -0,0 +1,180 @@ +#[doc = "Register `LCD_CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `LCD_VSYNC_WIDTH` reader - It is the position of LCD_VSYNC active pulse in a line."] +pub type LCD_VSYNC_WIDTH_R = crate::FieldReader; +#[doc = "Field `LCD_VSYNC_WIDTH` writer - It is the position of LCD_VSYNC active pulse in a line."] +pub type LCD_VSYNC_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `LCD_VSYNC_IDLE_POL` reader - It is the idle value of LCD_VSYNC."] +pub type LCD_VSYNC_IDLE_POL_R = crate::BitReader; +#[doc = "Field `LCD_VSYNC_IDLE_POL` writer - It is the idle value of LCD_VSYNC."] +pub type LCD_VSYNC_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_DE_IDLE_POL` reader - It is the idle value of LCD_DE."] +pub type LCD_DE_IDLE_POL_R = crate::BitReader; +#[doc = "Field `LCD_DE_IDLE_POL` writer - It is the idle value of LCD_DE."] +pub type LCD_DE_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_HS_BLANK_EN` reader - 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode."] +pub type LCD_HS_BLANK_EN_R = crate::BitReader; +#[doc = "Field `LCD_HS_BLANK_EN` writer - 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode."] +pub type LCD_HS_BLANK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_HSYNC_WIDTH` reader - It is the position of LCD_HSYNC active pulse in a line."] +pub type LCD_HSYNC_WIDTH_R = crate::FieldReader; +#[doc = "Field `LCD_HSYNC_WIDTH` writer - It is the position of LCD_HSYNC active pulse in a line."] +pub type LCD_HSYNC_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `LCD_HSYNC_IDLE_POL` reader - It is the idle value of LCD_HSYNC."] +pub type LCD_HSYNC_IDLE_POL_R = crate::BitReader; +#[doc = "Field `LCD_HSYNC_IDLE_POL` writer - It is the idle value of LCD_HSYNC."] +pub type LCD_HSYNC_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_HSYNC_POSITION` reader - It is the position of LCD_HSYNC active pulse in a line."] +pub type LCD_HSYNC_POSITION_R = crate::FieldReader; +#[doc = "Field `LCD_HSYNC_POSITION` writer - It is the position of LCD_HSYNC active pulse in a line."] +pub type LCD_HSYNC_POSITION_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:6 - It is the position of LCD_VSYNC active pulse in a line."] + #[inline(always)] + pub fn lcd_vsync_width(&self) -> LCD_VSYNC_WIDTH_R { + LCD_VSYNC_WIDTH_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 7 - It is the idle value of LCD_VSYNC."] + #[inline(always)] + pub fn lcd_vsync_idle_pol(&self) -> LCD_VSYNC_IDLE_POL_R { + LCD_VSYNC_IDLE_POL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - It is the idle value of LCD_DE."] + #[inline(always)] + pub fn lcd_de_idle_pol(&self) -> LCD_DE_IDLE_POL_R { + LCD_DE_IDLE_POL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode."] + #[inline(always)] + pub fn lcd_hs_blank_en(&self) -> LCD_HS_BLANK_EN_R { + LCD_HS_BLANK_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 16:22 - It is the position of LCD_HSYNC active pulse in a line."] + #[inline(always)] + pub fn lcd_hsync_width(&self) -> LCD_HSYNC_WIDTH_R { + LCD_HSYNC_WIDTH_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bit 23 - It is the idle value of LCD_HSYNC."] + #[inline(always)] + pub fn lcd_hsync_idle_pol(&self) -> LCD_HSYNC_IDLE_POL_R { + LCD_HSYNC_IDLE_POL_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:31 - It is the position of LCD_HSYNC active pulse in a line."] + #[inline(always)] + pub fn lcd_hsync_position(&self) -> LCD_HSYNC_POSITION_R { + LCD_HSYNC_POSITION_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_CTRL2") + .field( + "lcd_vsync_width", + &format_args!("{}", self.lcd_vsync_width().bits()), + ) + .field( + "lcd_vsync_idle_pol", + &format_args!("{}", self.lcd_vsync_idle_pol().bit()), + ) + .field( + "lcd_de_idle_pol", + &format_args!("{}", self.lcd_de_idle_pol().bit()), + ) + .field( + "lcd_hs_blank_en", + &format_args!("{}", self.lcd_hs_blank_en().bit()), + ) + .field( + "lcd_hsync_width", + &format_args!("{}", self.lcd_hsync_width().bits()), + ) + .field( + "lcd_hsync_idle_pol", + &format_args!("{}", self.lcd_hsync_idle_pol().bit()), + ) + .field( + "lcd_hsync_position", + &format_args!("{}", self.lcd_hsync_position().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - It is the position of LCD_VSYNC active pulse in a line."] + #[inline(always)] + #[must_use] + pub fn lcd_vsync_width(&mut self) -> LCD_VSYNC_WIDTH_W { + LCD_VSYNC_WIDTH_W::new(self, 0) + } + #[doc = "Bit 7 - It is the idle value of LCD_VSYNC."] + #[inline(always)] + #[must_use] + pub fn lcd_vsync_idle_pol(&mut self) -> LCD_VSYNC_IDLE_POL_W { + LCD_VSYNC_IDLE_POL_W::new(self, 7) + } + #[doc = "Bit 8 - It is the idle value of LCD_DE."] + #[inline(always)] + #[must_use] + pub fn lcd_de_idle_pol(&mut self) -> LCD_DE_IDLE_POL_W { + LCD_DE_IDLE_POL_W::new(self, 8) + } + #[doc = "Bit 9 - 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode."] + #[inline(always)] + #[must_use] + pub fn lcd_hs_blank_en(&mut self) -> LCD_HS_BLANK_EN_W { + LCD_HS_BLANK_EN_W::new(self, 9) + } + #[doc = "Bits 16:22 - It is the position of LCD_HSYNC active pulse in a line."] + #[inline(always)] + #[must_use] + pub fn lcd_hsync_width(&mut self) -> LCD_HSYNC_WIDTH_W { + LCD_HSYNC_WIDTH_W::new(self, 16) + } + #[doc = "Bit 23 - It is the idle value of LCD_HSYNC."] + #[inline(always)] + #[must_use] + pub fn lcd_hsync_idle_pol(&mut self) -> LCD_HSYNC_IDLE_POL_W { + LCD_HSYNC_IDLE_POL_W::new(self, 23) + } + #[doc = "Bits 24:31 - It is the position of LCD_HSYNC active pulse in a line."] + #[inline(always)] + #[must_use] + pub fn lcd_hsync_position(&mut self) -> LCD_HSYNC_POSITION_W { + LCD_HSYNC_POSITION_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_CTRL2_SPEC; +impl crate::RegisterSpec for LCD_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_ctrl2::R`](R) reader structure"] +impl crate::Readable for LCD_CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_ctrl2::W`](W) writer structure"] +impl crate::Writable for LCD_CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_CTRL2 to value 0x0001_0001"] +impl crate::Resettable for LCD_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0001; +} diff --git a/esp32p4/src/lcd_cam/lcd_dly_mode_cfg1.rs b/esp32p4/src/lcd_cam/lcd_dly_mode_cfg1.rs new file mode 100644 index 0000000000..5a7f1d48c4 --- /dev/null +++ b/esp32p4/src/lcd_cam/lcd_dly_mode_cfg1.rs @@ -0,0 +1,275 @@ +#[doc = "Register `LCD_DLY_MODE_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_DLY_MODE_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `DOUT16_MODE` reader - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT16_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT16_MODE` writer - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT16_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT17_MODE` reader - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT17_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT17_MODE` writer - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT17_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT18_MODE` reader - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT18_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT18_MODE` writer - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT18_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT19_MODE` reader - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT19_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT19_MODE` writer - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT19_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT20_MODE` reader - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT20_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT20_MODE` writer - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT20_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT21_MODE` reader - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT21_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT21_MODE` writer - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT21_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT22_MODE` reader - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT22_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT22_MODE` writer - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT22_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT23_MODE` reader - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT23_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT23_MODE` writer - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT23_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LCD_CD_MODE` reader - The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type LCD_CD_MODE_R = crate::FieldReader; +#[doc = "Field `LCD_CD_MODE` writer - The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type LCD_CD_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LCD_DE_MODE` reader - The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type LCD_DE_MODE_R = crate::FieldReader; +#[doc = "Field `LCD_DE_MODE` writer - The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type LCD_DE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LCD_HSYNC_MODE` reader - The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type LCD_HSYNC_MODE_R = crate::FieldReader; +#[doc = "Field `LCD_HSYNC_MODE` writer - The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type LCD_HSYNC_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LCD_VSYNC_MODE` reader - The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type LCD_VSYNC_MODE_R = crate::FieldReader; +#[doc = "Field `LCD_VSYNC_MODE` writer - The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type LCD_VSYNC_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout16_mode(&self) -> DOUT16_MODE_R { + DOUT16_MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout17_mode(&self) -> DOUT17_MODE_R { + DOUT17_MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout18_mode(&self) -> DOUT18_MODE_R { + DOUT18_MODE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout19_mode(&self) -> DOUT19_MODE_R { + DOUT19_MODE_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout20_mode(&self) -> DOUT20_MODE_R { + DOUT20_MODE_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout21_mode(&self) -> DOUT21_MODE_R { + DOUT21_MODE_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout22_mode(&self) -> DOUT22_MODE_R { + DOUT22_MODE_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout23_mode(&self) -> DOUT23_MODE_R { + DOUT23_MODE_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn lcd_cd_mode(&self) -> LCD_CD_MODE_R { + LCD_CD_MODE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn lcd_de_mode(&self) -> LCD_DE_MODE_R { + LCD_DE_MODE_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn lcd_hsync_mode(&self) -> LCD_HSYNC_MODE_R { + LCD_HSYNC_MODE_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn lcd_vsync_mode(&self) -> LCD_VSYNC_MODE_R { + LCD_VSYNC_MODE_R::new(((self.bits >> 22) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_DLY_MODE_CFG1") + .field( + "dout16_mode", + &format_args!("{}", self.dout16_mode().bits()), + ) + .field( + "dout17_mode", + &format_args!("{}", self.dout17_mode().bits()), + ) + .field( + "dout18_mode", + &format_args!("{}", self.dout18_mode().bits()), + ) + .field( + "dout19_mode", + &format_args!("{}", self.dout19_mode().bits()), + ) + .field( + "dout20_mode", + &format_args!("{}", self.dout20_mode().bits()), + ) + .field( + "dout21_mode", + &format_args!("{}", self.dout21_mode().bits()), + ) + .field( + "dout22_mode", + &format_args!("{}", self.dout22_mode().bits()), + ) + .field( + "dout23_mode", + &format_args!("{}", self.dout23_mode().bits()), + ) + .field( + "lcd_cd_mode", + &format_args!("{}", self.lcd_cd_mode().bits()), + ) + .field( + "lcd_de_mode", + &format_args!("{}", self.lcd_de_mode().bits()), + ) + .field( + "lcd_hsync_mode", + &format_args!("{}", self.lcd_hsync_mode().bits()), + ) + .field( + "lcd_vsync_mode", + &format_args!("{}", self.lcd_vsync_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout16_mode(&mut self) -> DOUT16_MODE_W { + DOUT16_MODE_W::new(self, 0) + } + #[doc = "Bits 2:3 - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout17_mode(&mut self) -> DOUT17_MODE_W { + DOUT17_MODE_W::new(self, 2) + } + #[doc = "Bits 4:5 - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout18_mode(&mut self) -> DOUT18_MODE_W { + DOUT18_MODE_W::new(self, 4) + } + #[doc = "Bits 6:7 - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout19_mode(&mut self) -> DOUT19_MODE_W { + DOUT19_MODE_W::new(self, 6) + } + #[doc = "Bits 8:9 - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout20_mode(&mut self) -> DOUT20_MODE_W { + DOUT20_MODE_W::new(self, 8) + } + #[doc = "Bits 10:11 - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout21_mode(&mut self) -> DOUT21_MODE_W { + DOUT21_MODE_W::new(self, 10) + } + #[doc = "Bits 12:13 - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout22_mode(&mut self) -> DOUT22_MODE_W { + DOUT22_MODE_W::new(self, 12) + } + #[doc = "Bits 14:15 - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout23_mode(&mut self) -> DOUT23_MODE_W { + DOUT23_MODE_W::new(self, 14) + } + #[doc = "Bits 16:17 - The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn lcd_cd_mode(&mut self) -> LCD_CD_MODE_W { + LCD_CD_MODE_W::new(self, 16) + } + #[doc = "Bits 18:19 - The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn lcd_de_mode(&mut self) -> LCD_DE_MODE_W { + LCD_DE_MODE_W::new(self, 18) + } + #[doc = "Bits 20:21 - The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn lcd_hsync_mode(&mut self) -> LCD_HSYNC_MODE_W { + LCD_HSYNC_MODE_W::new(self, 20) + } + #[doc = "Bits 22:23 - The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn lcd_vsync_mode(&mut self) -> LCD_VSYNC_MODE_W { + LCD_VSYNC_MODE_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_dly_mode_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_dly_mode_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_DLY_MODE_CFG1_SPEC; +impl crate::RegisterSpec for LCD_DLY_MODE_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_dly_mode_cfg1::R`](R) reader structure"] +impl crate::Readable for LCD_DLY_MODE_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_dly_mode_cfg1::W`](W) writer structure"] +impl crate::Writable for LCD_DLY_MODE_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_DLY_MODE_CFG1 to value 0"] +impl crate::Resettable for LCD_DLY_MODE_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lcd_cam/lcd_dly_mode_cfg2.rs b/esp32p4/src/lcd_cam/lcd_dly_mode_cfg2.rs new file mode 100644 index 0000000000..289f300e3e --- /dev/null +++ b/esp32p4/src/lcd_cam/lcd_dly_mode_cfg2.rs @@ -0,0 +1,321 @@ +#[doc = "Register `LCD_DLY_MODE_CFG2` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_DLY_MODE_CFG2` writer"] +pub type W = crate::W; +#[doc = "Field `DOUT0_MODE` reader - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT0_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT0_MODE` writer - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT0_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT1_MODE` reader - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT1_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT1_MODE` writer - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT1_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT2_MODE` reader - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT2_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT2_MODE` writer - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT2_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT3_MODE` reader - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT3_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT3_MODE` writer - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT3_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT4_MODE` reader - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT4_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT4_MODE` writer - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT4_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT5_MODE` reader - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT5_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT5_MODE` writer - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT5_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT6_MODE` reader - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT6_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT6_MODE` writer - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT6_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT7_MODE` reader - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT7_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT7_MODE` writer - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT7_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT8_MODE` reader - The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT8_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT8_MODE` writer - The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT8_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT9_MODE` reader - The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT9_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT9_MODE` writer - The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT9_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT10_MODE` reader - The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT10_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT10_MODE` writer - The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT10_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT11_MODE` reader - The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT11_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT11_MODE` writer - The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT11_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT12_MODE` reader - The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT12_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT12_MODE` writer - The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT12_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT13_MODE` reader - The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT13_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT13_MODE` writer - The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT13_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT14_MODE` reader - The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT14_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT14_MODE` writer - The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT14_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DOUT15_MODE` reader - The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT15_MODE_R = crate::FieldReader; +#[doc = "Field `DOUT15_MODE` writer - The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] +pub type DOUT15_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout0_mode(&self) -> DOUT0_MODE_R { + DOUT0_MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout1_mode(&self) -> DOUT1_MODE_R { + DOUT1_MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout2_mode(&self) -> DOUT2_MODE_R { + DOUT2_MODE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout3_mode(&self) -> DOUT3_MODE_R { + DOUT3_MODE_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout4_mode(&self) -> DOUT4_MODE_R { + DOUT4_MODE_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout5_mode(&self) -> DOUT5_MODE_R { + DOUT5_MODE_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout6_mode(&self) -> DOUT6_MODE_R { + DOUT6_MODE_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout7_mode(&self) -> DOUT7_MODE_R { + DOUT7_MODE_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout8_mode(&self) -> DOUT8_MODE_R { + DOUT8_MODE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout9_mode(&self) -> DOUT9_MODE_R { + DOUT9_MODE_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout10_mode(&self) -> DOUT10_MODE_R { + DOUT10_MODE_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout11_mode(&self) -> DOUT11_MODE_R { + DOUT11_MODE_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout12_mode(&self) -> DOUT12_MODE_R { + DOUT12_MODE_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout13_mode(&self) -> DOUT13_MODE_R { + DOUT13_MODE_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout14_mode(&self) -> DOUT14_MODE_R { + DOUT14_MODE_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + pub fn dout15_mode(&self) -> DOUT15_MODE_R { + DOUT15_MODE_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_DLY_MODE_CFG2") + .field("dout0_mode", &format_args!("{}", self.dout0_mode().bits())) + .field("dout1_mode", &format_args!("{}", self.dout1_mode().bits())) + .field("dout2_mode", &format_args!("{}", self.dout2_mode().bits())) + .field("dout3_mode", &format_args!("{}", self.dout3_mode().bits())) + .field("dout4_mode", &format_args!("{}", self.dout4_mode().bits())) + .field("dout5_mode", &format_args!("{}", self.dout5_mode().bits())) + .field("dout6_mode", &format_args!("{}", self.dout6_mode().bits())) + .field("dout7_mode", &format_args!("{}", self.dout7_mode().bits())) + .field("dout8_mode", &format_args!("{}", self.dout8_mode().bits())) + .field("dout9_mode", &format_args!("{}", self.dout9_mode().bits())) + .field( + "dout10_mode", + &format_args!("{}", self.dout10_mode().bits()), + ) + .field( + "dout11_mode", + &format_args!("{}", self.dout11_mode().bits()), + ) + .field( + "dout12_mode", + &format_args!("{}", self.dout12_mode().bits()), + ) + .field( + "dout13_mode", + &format_args!("{}", self.dout13_mode().bits()), + ) + .field( + "dout14_mode", + &format_args!("{}", self.dout14_mode().bits()), + ) + .field( + "dout15_mode", + &format_args!("{}", self.dout15_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout0_mode(&mut self) -> DOUT0_MODE_W { + DOUT0_MODE_W::new(self, 0) + } + #[doc = "Bits 2:3 - The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout1_mode(&mut self) -> DOUT1_MODE_W { + DOUT1_MODE_W::new(self, 2) + } + #[doc = "Bits 4:5 - The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout2_mode(&mut self) -> DOUT2_MODE_W { + DOUT2_MODE_W::new(self, 4) + } + #[doc = "Bits 6:7 - The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout3_mode(&mut self) -> DOUT3_MODE_W { + DOUT3_MODE_W::new(self, 6) + } + #[doc = "Bits 8:9 - The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout4_mode(&mut self) -> DOUT4_MODE_W { + DOUT4_MODE_W::new(self, 8) + } + #[doc = "Bits 10:11 - The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout5_mode(&mut self) -> DOUT5_MODE_W { + DOUT5_MODE_W::new(self, 10) + } + #[doc = "Bits 12:13 - The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout6_mode(&mut self) -> DOUT6_MODE_W { + DOUT6_MODE_W::new(self, 12) + } + #[doc = "Bits 14:15 - The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout7_mode(&mut self) -> DOUT7_MODE_W { + DOUT7_MODE_W::new(self, 14) + } + #[doc = "Bits 16:17 - The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout8_mode(&mut self) -> DOUT8_MODE_W { + DOUT8_MODE_W::new(self, 16) + } + #[doc = "Bits 18:19 - The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout9_mode(&mut self) -> DOUT9_MODE_W { + DOUT9_MODE_W::new(self, 18) + } + #[doc = "Bits 20:21 - The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout10_mode(&mut self) -> DOUT10_MODE_W { + DOUT10_MODE_W::new(self, 20) + } + #[doc = "Bits 22:23 - The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout11_mode(&mut self) -> DOUT11_MODE_W { + DOUT11_MODE_W::new(self, 22) + } + #[doc = "Bits 24:25 - The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout12_mode(&mut self) -> DOUT12_MODE_W { + DOUT12_MODE_W::new(self, 24) + } + #[doc = "Bits 26:27 - The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout13_mode(&mut self) -> DOUT13_MODE_W { + DOUT13_MODE_W::new(self, 26) + } + #[doc = "Bits 28:29 - The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout14_mode(&mut self) -> DOUT14_MODE_W { + DOUT14_MODE_W::new(self, 28) + } + #[doc = "Bits 30:31 - The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK."] + #[inline(always)] + #[must_use] + pub fn dout15_mode(&mut self) -> DOUT15_MODE_W { + DOUT15_MODE_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_dly_mode_cfg2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_dly_mode_cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_DLY_MODE_CFG2_SPEC; +impl crate::RegisterSpec for LCD_DLY_MODE_CFG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_dly_mode_cfg2::R`](R) reader structure"] +impl crate::Readable for LCD_DLY_MODE_CFG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_dly_mode_cfg2::W`](W) writer structure"] +impl crate::Writable for LCD_DLY_MODE_CFG2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_DLY_MODE_CFG2 to value 0"] +impl crate::Resettable for LCD_DLY_MODE_CFG2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lcd_cam/lcd_first_cmd_val.rs b/esp32p4/src/lcd_cam/lcd_first_cmd_val.rs new file mode 100644 index 0000000000..49f88f0772 --- /dev/null +++ b/esp32p4/src/lcd_cam/lcd_first_cmd_val.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LCD_FIRST_CMD_VAL` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_FIRST_CMD_VAL` writer"] +pub type W = crate::W; +#[doc = "Field `LCD_FIRST_CMD_VALUE` reader - The LCD write command value of first cmd cycle."] +pub type LCD_FIRST_CMD_VALUE_R = crate::FieldReader; +#[doc = "Field `LCD_FIRST_CMD_VALUE` writer - The LCD write command value of first cmd cycle."] +pub type LCD_FIRST_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The LCD write command value of first cmd cycle."] + #[inline(always)] + pub fn lcd_first_cmd_value(&self) -> LCD_FIRST_CMD_VALUE_R { + LCD_FIRST_CMD_VALUE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_FIRST_CMD_VAL") + .field( + "lcd_first_cmd_value", + &format_args!("{}", self.lcd_first_cmd_value().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The LCD write command value of first cmd cycle."] + #[inline(always)] + #[must_use] + pub fn lcd_first_cmd_value(&mut self) -> LCD_FIRST_CMD_VALUE_W { + LCD_FIRST_CMD_VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_first_cmd_val::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_first_cmd_val::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_FIRST_CMD_VAL_SPEC; +impl crate::RegisterSpec for LCD_FIRST_CMD_VAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_first_cmd_val::R`](R) reader structure"] +impl crate::Readable for LCD_FIRST_CMD_VAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_first_cmd_val::W`](W) writer structure"] +impl crate::Writable for LCD_FIRST_CMD_VAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_FIRST_CMD_VAL to value 0"] +impl crate::Resettable for LCD_FIRST_CMD_VAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lcd_cam/lcd_latter_cmd_val.rs b/esp32p4/src/lcd_cam/lcd_latter_cmd_val.rs new file mode 100644 index 0000000000..33e3eb9240 --- /dev/null +++ b/esp32p4/src/lcd_cam/lcd_latter_cmd_val.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LCD_LATTER_CMD_VAL` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_LATTER_CMD_VAL` writer"] +pub type W = crate::W; +#[doc = "Field `LCD_LATTER_CMD_VALUE` reader - The LCD write command value of latter cmd cycle."] +pub type LCD_LATTER_CMD_VALUE_R = crate::FieldReader; +#[doc = "Field `LCD_LATTER_CMD_VALUE` writer - The LCD write command value of latter cmd cycle."] +pub type LCD_LATTER_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The LCD write command value of latter cmd cycle."] + #[inline(always)] + pub fn lcd_latter_cmd_value(&self) -> LCD_LATTER_CMD_VALUE_R { + LCD_LATTER_CMD_VALUE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_LATTER_CMD_VAL") + .field( + "lcd_latter_cmd_value", + &format_args!("{}", self.lcd_latter_cmd_value().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The LCD write command value of latter cmd cycle."] + #[inline(always)] + #[must_use] + pub fn lcd_latter_cmd_value(&mut self) -> LCD_LATTER_CMD_VALUE_W { + LCD_LATTER_CMD_VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_latter_cmd_val::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_latter_cmd_val::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_LATTER_CMD_VAL_SPEC; +impl crate::RegisterSpec for LCD_LATTER_CMD_VAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_latter_cmd_val::R`](R) reader structure"] +impl crate::Readable for LCD_LATTER_CMD_VAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_latter_cmd_val::W`](W) writer structure"] +impl crate::Writable for LCD_LATTER_CMD_VAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_LATTER_CMD_VAL to value 0"] +impl crate::Resettable for LCD_LATTER_CMD_VAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lcd_cam/lcd_misc.rs b/esp32p4/src/lcd_cam/lcd_misc.rs new file mode 100644 index 0000000000..97c5f6bff1 --- /dev/null +++ b/esp32p4/src/lcd_cam/lcd_misc.rs @@ -0,0 +1,223 @@ +#[doc = "Register `LCD_MISC` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_MISC` writer"] +pub type W = crate::W; +#[doc = "Field `LCD_WIRE_MODE` reader - The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit"] +pub type LCD_WIRE_MODE_R = crate::FieldReader; +#[doc = "Field `LCD_WIRE_MODE` writer - The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit"] +pub type LCD_WIRE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LCD_VFK_CYCLELEN` reader - The setup cycle length minus 1 in LCD non-RGB mode."] +pub type LCD_VFK_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `LCD_VFK_CYCLELEN` writer - The setup cycle length minus 1 in LCD non-RGB mode."] +pub type LCD_VFK_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `LCD_VBK_CYCLELEN` reader - The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode."] +pub type LCD_VBK_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `LCD_VBK_CYCLELEN` writer - The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode."] +pub type LCD_VBK_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +#[doc = "Field `LCD_NEXT_FRAME_EN` reader - 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out."] +pub type LCD_NEXT_FRAME_EN_R = crate::BitReader; +#[doc = "Field `LCD_NEXT_FRAME_EN` writer - 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out."] +pub type LCD_NEXT_FRAME_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_BK_EN` reader - 1: Enable blank region when LCD sends data out. 0: No blank region."] +pub type LCD_BK_EN_R = crate::BitReader; +#[doc = "Field `LCD_BK_EN` writer - 1: Enable blank region when LCD sends data out. 0: No blank region."] +pub type LCD_BK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_AFIFO_RESET` writer - LCD AFIFO reset signal."] +pub type LCD_AFIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CD_DATA_SET` reader - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge."] +pub type LCD_CD_DATA_SET_R = crate::BitReader; +#[doc = "Field `LCD_CD_DATA_SET` writer - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge."] +pub type LCD_CD_DATA_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CD_DUMMY_SET` reader - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge."] +pub type LCD_CD_DUMMY_SET_R = crate::BitReader; +#[doc = "Field `LCD_CD_DUMMY_SET` writer - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge."] +pub type LCD_CD_DUMMY_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CD_CMD_SET` reader - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge."] +pub type LCD_CD_CMD_SET_R = crate::BitReader; +#[doc = "Field `LCD_CD_CMD_SET` writer - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge."] +pub type LCD_CD_CMD_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CD_IDLE_EDGE` reader - The default value of LCD_CD."] +pub type LCD_CD_IDLE_EDGE_R = crate::BitReader; +#[doc = "Field `LCD_CD_IDLE_EDGE` writer - The default value of LCD_CD."] +pub type LCD_CD_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 4:5 - The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit"] + #[inline(always)] + pub fn lcd_wire_mode(&self) -> LCD_WIRE_MODE_R { + LCD_WIRE_MODE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:11 - The setup cycle length minus 1 in LCD non-RGB mode."] + #[inline(always)] + pub fn lcd_vfk_cyclelen(&self) -> LCD_VFK_CYCLELEN_R { + LCD_VFK_CYCLELEN_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:24 - The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode."] + #[inline(always)] + pub fn lcd_vbk_cyclelen(&self) -> LCD_VBK_CYCLELEN_R { + LCD_VBK_CYCLELEN_R::new(((self.bits >> 12) & 0x1fff) as u16) + } + #[doc = "Bit 25 - 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out."] + #[inline(always)] + pub fn lcd_next_frame_en(&self) -> LCD_NEXT_FRAME_EN_R { + LCD_NEXT_FRAME_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - 1: Enable blank region when LCD sends data out. 0: No blank region."] + #[inline(always)] + pub fn lcd_bk_en(&self) -> LCD_BK_EN_R { + LCD_BK_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 28 - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge."] + #[inline(always)] + pub fn lcd_cd_data_set(&self) -> LCD_CD_DATA_SET_R { + LCD_CD_DATA_SET_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge."] + #[inline(always)] + pub fn lcd_cd_dummy_set(&self) -> LCD_CD_DUMMY_SET_R { + LCD_CD_DUMMY_SET_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge."] + #[inline(always)] + pub fn lcd_cd_cmd_set(&self) -> LCD_CD_CMD_SET_R { + LCD_CD_CMD_SET_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - The default value of LCD_CD."] + #[inline(always)] + pub fn lcd_cd_idle_edge(&self) -> LCD_CD_IDLE_EDGE_R { + LCD_CD_IDLE_EDGE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_MISC") + .field( + "lcd_wire_mode", + &format_args!("{}", self.lcd_wire_mode().bits()), + ) + .field( + "lcd_vfk_cyclelen", + &format_args!("{}", self.lcd_vfk_cyclelen().bits()), + ) + .field( + "lcd_vbk_cyclelen", + &format_args!("{}", self.lcd_vbk_cyclelen().bits()), + ) + .field( + "lcd_next_frame_en", + &format_args!("{}", self.lcd_next_frame_en().bit()), + ) + .field("lcd_bk_en", &format_args!("{}", self.lcd_bk_en().bit())) + .field( + "lcd_cd_data_set", + &format_args!("{}", self.lcd_cd_data_set().bit()), + ) + .field( + "lcd_cd_dummy_set", + &format_args!("{}", self.lcd_cd_dummy_set().bit()), + ) + .field( + "lcd_cd_cmd_set", + &format_args!("{}", self.lcd_cd_cmd_set().bit()), + ) + .field( + "lcd_cd_idle_edge", + &format_args!("{}", self.lcd_cd_idle_edge().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 4:5 - The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit"] + #[inline(always)] + #[must_use] + pub fn lcd_wire_mode(&mut self) -> LCD_WIRE_MODE_W { + LCD_WIRE_MODE_W::new(self, 4) + } + #[doc = "Bits 6:11 - The setup cycle length minus 1 in LCD non-RGB mode."] + #[inline(always)] + #[must_use] + pub fn lcd_vfk_cyclelen(&mut self) -> LCD_VFK_CYCLELEN_W { + LCD_VFK_CYCLELEN_W::new(self, 6) + } + #[doc = "Bits 12:24 - The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode."] + #[inline(always)] + #[must_use] + pub fn lcd_vbk_cyclelen(&mut self) -> LCD_VBK_CYCLELEN_W { + LCD_VBK_CYCLELEN_W::new(self, 12) + } + #[doc = "Bit 25 - 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out."] + #[inline(always)] + #[must_use] + pub fn lcd_next_frame_en(&mut self) -> LCD_NEXT_FRAME_EN_W { + LCD_NEXT_FRAME_EN_W::new(self, 25) + } + #[doc = "Bit 26 - 1: Enable blank region when LCD sends data out. 0: No blank region."] + #[inline(always)] + #[must_use] + pub fn lcd_bk_en(&mut self) -> LCD_BK_EN_W { + LCD_BK_EN_W::new(self, 26) + } + #[doc = "Bit 27 - LCD AFIFO reset signal."] + #[inline(always)] + #[must_use] + pub fn lcd_afifo_reset(&mut self) -> LCD_AFIFO_RESET_W { + LCD_AFIFO_RESET_W::new(self, 27) + } + #[doc = "Bit 28 - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge."] + #[inline(always)] + #[must_use] + pub fn lcd_cd_data_set(&mut self) -> LCD_CD_DATA_SET_W { + LCD_CD_DATA_SET_W::new(self, 28) + } + #[doc = "Bit 29 - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge."] + #[inline(always)] + #[must_use] + pub fn lcd_cd_dummy_set(&mut self) -> LCD_CD_DUMMY_SET_W { + LCD_CD_DUMMY_SET_W::new(self, 29) + } + #[doc = "Bit 30 - 1: LCD_CD = !reg_cd_idle_edge when lcd_st\\[2:0\\] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge."] + #[inline(always)] + #[must_use] + pub fn lcd_cd_cmd_set(&mut self) -> LCD_CD_CMD_SET_W { + LCD_CD_CMD_SET_W::new(self, 30) + } + #[doc = "Bit 31 - The default value of LCD_CD."] + #[inline(always)] + #[must_use] + pub fn lcd_cd_idle_edge(&mut self) -> LCD_CD_IDLE_EDGE_W { + LCD_CD_IDLE_EDGE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_misc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_misc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_MISC_SPEC; +impl crate::RegisterSpec for LCD_MISC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_misc::R`](R) reader structure"] +impl crate::Readable for LCD_MISC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_misc::W`](W) writer structure"] +impl crate::Writable for LCD_MISC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_MISC to value 0xc0"] +impl crate::Resettable for LCD_MISC_SPEC { + const RESET_VALUE: Self::Ux = 0xc0; +} diff --git a/esp32p4/src/lcd_cam/lcd_rgb_yuv.rs b/esp32p4/src/lcd_cam/lcd_rgb_yuv.rs new file mode 100644 index 0000000000..3dceade4e1 --- /dev/null +++ b/esp32p4/src/lcd_cam/lcd_rgb_yuv.rs @@ -0,0 +1,237 @@ +#[doc = "Register `LCD_RGB_YUV` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_RGB_YUV` writer"] +pub type W = crate::W; +#[doc = "Field `LCD_CONV_8BITS_DATA_INV` reader - 1:invert every two 8bits input data. 2. disabled."] +pub type LCD_CONV_8BITS_DATA_INV_R = crate::BitReader; +#[doc = "Field `LCD_CONV_8BITS_DATA_INV` writer - 1:invert every two 8bits input data. 2. disabled."] +pub type LCD_CONV_8BITS_DATA_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CONV_TXTORX` reader - 0: txtorx mode off. 1: txtorx mode on."] +pub type LCD_CONV_TXTORX_R = crate::BitReader; +#[doc = "Field `LCD_CONV_TXTORX` writer - 0: txtorx mode off. 1: txtorx mode on."] +pub type LCD_CONV_TXTORX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CONV_YUV2YUV_MODE` reader - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1."] +pub type LCD_CONV_YUV2YUV_MODE_R = crate::FieldReader; +#[doc = "Field `LCD_CONV_YUV2YUV_MODE` writer - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1."] +pub type LCD_CONV_YUV2YUV_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LCD_CONV_YUV_MODE` reader - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in"] +pub type LCD_CONV_YUV_MODE_R = crate::FieldReader; +#[doc = "Field `LCD_CONV_YUV_MODE` writer - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in"] +pub type LCD_CONV_YUV_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LCD_CONV_PROTOCOL_MODE` reader - 0:BT601. 1:BT709."] +pub type LCD_CONV_PROTOCOL_MODE_R = crate::BitReader; +#[doc = "Field `LCD_CONV_PROTOCOL_MODE` writer - 0:BT601. 1:BT709."] +pub type LCD_CONV_PROTOCOL_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CONV_DATA_OUT_MODE` reader - LIMIT or FULL mode of Data out. 0: limit. 1: full"] +pub type LCD_CONV_DATA_OUT_MODE_R = crate::BitReader; +#[doc = "Field `LCD_CONV_DATA_OUT_MODE` writer - LIMIT or FULL mode of Data out. 0: limit. 1: full"] +pub type LCD_CONV_DATA_OUT_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CONV_DATA_IN_MODE` reader - LIMIT or FULL mode of Data in. 0: limit. 1: full"] +pub type LCD_CONV_DATA_IN_MODE_R = crate::BitReader; +#[doc = "Field `LCD_CONV_DATA_IN_MODE` writer - LIMIT or FULL mode of Data in. 0: limit. 1: full"] +pub type LCD_CONV_DATA_IN_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CONV_MODE_8BITS_ON` reader - 0: 16bits mode. 1: 8bits mode."] +pub type LCD_CONV_MODE_8BITS_ON_R = crate::BitReader; +#[doc = "Field `LCD_CONV_MODE_8BITS_ON` writer - 0: 16bits mode. 1: 8bits mode."] +pub type LCD_CONV_MODE_8BITS_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CONV_TRANS_MODE` reader - 0: YUV to RGB. 1: RGB to YUV."] +pub type LCD_CONV_TRANS_MODE_R = crate::BitReader; +#[doc = "Field `LCD_CONV_TRANS_MODE` writer - 0: YUV to RGB. 1: RGB to YUV."] +pub type LCD_CONV_TRANS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CONV_ENABLE` reader - 0: Bypass converter. 1: Enable converter."] +pub type LCD_CONV_ENABLE_R = crate::BitReader; +#[doc = "Field `LCD_CONV_ENABLE` writer - 0: Bypass converter. 1: Enable converter."] +pub type LCD_CONV_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 20 - 1:invert every two 8bits input data. 2. disabled."] + #[inline(always)] + pub fn lcd_conv_8bits_data_inv(&self) -> LCD_CONV_8BITS_DATA_INV_R { + LCD_CONV_8BITS_DATA_INV_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - 0: txtorx mode off. 1: txtorx mode on."] + #[inline(always)] + pub fn lcd_conv_txtorx(&self) -> LCD_CONV_TXTORX_R { + LCD_CONV_TXTORX_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 22:23 - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1."] + #[inline(always)] + pub fn lcd_conv_yuv2yuv_mode(&self) -> LCD_CONV_YUV2YUV_MODE_R { + LCD_CONV_YUV2YUV_MODE_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in"] + #[inline(always)] + pub fn lcd_conv_yuv_mode(&self) -> LCD_CONV_YUV_MODE_R { + LCD_CONV_YUV_MODE_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - 0:BT601. 1:BT709."] + #[inline(always)] + pub fn lcd_conv_protocol_mode(&self) -> LCD_CONV_PROTOCOL_MODE_R { + LCD_CONV_PROTOCOL_MODE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - LIMIT or FULL mode of Data out. 0: limit. 1: full"] + #[inline(always)] + pub fn lcd_conv_data_out_mode(&self) -> LCD_CONV_DATA_OUT_MODE_R { + LCD_CONV_DATA_OUT_MODE_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - LIMIT or FULL mode of Data in. 0: limit. 1: full"] + #[inline(always)] + pub fn lcd_conv_data_in_mode(&self) -> LCD_CONV_DATA_IN_MODE_R { + LCD_CONV_DATA_IN_MODE_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - 0: 16bits mode. 1: 8bits mode."] + #[inline(always)] + pub fn lcd_conv_mode_8bits_on(&self) -> LCD_CONV_MODE_8BITS_ON_R { + LCD_CONV_MODE_8BITS_ON_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - 0: YUV to RGB. 1: RGB to YUV."] + #[inline(always)] + pub fn lcd_conv_trans_mode(&self) -> LCD_CONV_TRANS_MODE_R { + LCD_CONV_TRANS_MODE_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 0: Bypass converter. 1: Enable converter."] + #[inline(always)] + pub fn lcd_conv_enable(&self) -> LCD_CONV_ENABLE_R { + LCD_CONV_ENABLE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_RGB_YUV") + .field( + "lcd_conv_8bits_data_inv", + &format_args!("{}", self.lcd_conv_8bits_data_inv().bit()), + ) + .field( + "lcd_conv_txtorx", + &format_args!("{}", self.lcd_conv_txtorx().bit()), + ) + .field( + "lcd_conv_yuv2yuv_mode", + &format_args!("{}", self.lcd_conv_yuv2yuv_mode().bits()), + ) + .field( + "lcd_conv_yuv_mode", + &format_args!("{}", self.lcd_conv_yuv_mode().bits()), + ) + .field( + "lcd_conv_protocol_mode", + &format_args!("{}", self.lcd_conv_protocol_mode().bit()), + ) + .field( + "lcd_conv_data_out_mode", + &format_args!("{}", self.lcd_conv_data_out_mode().bit()), + ) + .field( + "lcd_conv_data_in_mode", + &format_args!("{}", self.lcd_conv_data_in_mode().bit()), + ) + .field( + "lcd_conv_mode_8bits_on", + &format_args!("{}", self.lcd_conv_mode_8bits_on().bit()), + ) + .field( + "lcd_conv_trans_mode", + &format_args!("{}", self.lcd_conv_trans_mode().bit()), + ) + .field( + "lcd_conv_enable", + &format_args!("{}", self.lcd_conv_enable().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 20 - 1:invert every two 8bits input data. 2. disabled."] + #[inline(always)] + #[must_use] + pub fn lcd_conv_8bits_data_inv(&mut self) -> LCD_CONV_8BITS_DATA_INV_W { + LCD_CONV_8BITS_DATA_INV_W::new(self, 20) + } + #[doc = "Bit 21 - 0: txtorx mode off. 1: txtorx mode on."] + #[inline(always)] + #[must_use] + pub fn lcd_conv_txtorx(&mut self) -> LCD_CONV_TXTORX_W { + LCD_CONV_TXTORX_W::new(self, 21) + } + #[doc = "Bits 22:23 - 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1."] + #[inline(always)] + #[must_use] + pub fn lcd_conv_yuv2yuv_mode(&mut self) -> LCD_CONV_YUV2YUV_MODE_W { + LCD_CONV_YUV2YUV_MODE_W::new(self, 22) + } + #[doc = "Bits 24:25 - 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in"] + #[inline(always)] + #[must_use] + pub fn lcd_conv_yuv_mode(&mut self) -> LCD_CONV_YUV_MODE_W { + LCD_CONV_YUV_MODE_W::new(self, 24) + } + #[doc = "Bit 26 - 0:BT601. 1:BT709."] + #[inline(always)] + #[must_use] + pub fn lcd_conv_protocol_mode(&mut self) -> LCD_CONV_PROTOCOL_MODE_W { + LCD_CONV_PROTOCOL_MODE_W::new(self, 26) + } + #[doc = "Bit 27 - LIMIT or FULL mode of Data out. 0: limit. 1: full"] + #[inline(always)] + #[must_use] + pub fn lcd_conv_data_out_mode(&mut self) -> LCD_CONV_DATA_OUT_MODE_W { + LCD_CONV_DATA_OUT_MODE_W::new(self, 27) + } + #[doc = "Bit 28 - LIMIT or FULL mode of Data in. 0: limit. 1: full"] + #[inline(always)] + #[must_use] + pub fn lcd_conv_data_in_mode(&mut self) -> LCD_CONV_DATA_IN_MODE_W { + LCD_CONV_DATA_IN_MODE_W::new(self, 28) + } + #[doc = "Bit 29 - 0: 16bits mode. 1: 8bits mode."] + #[inline(always)] + #[must_use] + pub fn lcd_conv_mode_8bits_on(&mut self) -> LCD_CONV_MODE_8BITS_ON_W { + LCD_CONV_MODE_8BITS_ON_W::new(self, 29) + } + #[doc = "Bit 30 - 0: YUV to RGB. 1: RGB to YUV."] + #[inline(always)] + #[must_use] + pub fn lcd_conv_trans_mode(&mut self) -> LCD_CONV_TRANS_MODE_W { + LCD_CONV_TRANS_MODE_W::new(self, 30) + } + #[doc = "Bit 31 - 0: Bypass converter. 1: Enable converter."] + #[inline(always)] + #[must_use] + pub fn lcd_conv_enable(&mut self) -> LCD_CONV_ENABLE_W { + LCD_CONV_ENABLE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCD YUV/RGB converter configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_rgb_yuv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_rgb_yuv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_RGB_YUV_SPEC; +impl crate::RegisterSpec for LCD_RGB_YUV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_rgb_yuv::R`](R) reader structure"] +impl crate::Readable for LCD_RGB_YUV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_rgb_yuv::W`](W) writer structure"] +impl crate::Writable for LCD_RGB_YUV_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_RGB_YUV to value 0x00c0_0000"] +impl crate::Resettable for LCD_RGB_YUV_SPEC { + const RESET_VALUE: Self::Ux = 0x00c0_0000; +} diff --git a/esp32p4/src/lcd_cam/lcd_user.rs b/esp32p4/src/lcd_cam/lcd_user.rs new file mode 100644 index 0000000000..26d5183d2a --- /dev/null +++ b/esp32p4/src/lcd_cam/lcd_user.rs @@ -0,0 +1,327 @@ +#[doc = "Register `LCD_USER` reader"] +pub type R = crate::R; +#[doc = "Register `LCD_USER` writer"] +pub type W = crate::W; +#[doc = "Field `LCD_DOUT_CYCLELEN` reader - The output data cycles minus 1 of LCD module."] +pub type LCD_DOUT_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `LCD_DOUT_CYCLELEN` writer - The output data cycles minus 1 of LCD module."] +pub type LCD_DOUT_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +#[doc = "Field `LCD_ALWAYS_OUT_EN` reader - LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set."] +pub type LCD_ALWAYS_OUT_EN_R = crate::BitReader; +#[doc = "Field `LCD_ALWAYS_OUT_EN` writer - LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set."] +pub type LCD_ALWAYS_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_DOUT_BYTE_SWIZZLE_MODE` reader - 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA"] +pub type LCD_DOUT_BYTE_SWIZZLE_MODE_R = crate::FieldReader; +#[doc = "Field `LCD_DOUT_BYTE_SWIZZLE_MODE` writer - 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA"] +pub type LCD_DOUT_BYTE_SWIZZLE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LCD_DOUT_BYTE_SWIZZLE_ENABLE` reader - 1: enable byte swizzle 0: disable"] +pub type LCD_DOUT_BYTE_SWIZZLE_ENABLE_R = crate::BitReader; +#[doc = "Field `LCD_DOUT_BYTE_SWIZZLE_ENABLE` writer - 1: enable byte swizzle 0: disable"] +pub type LCD_DOUT_BYTE_SWIZZLE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_DOUT_BIT_ORDER` reader - 1: change bit order in every byte. 0: Not change."] +pub type LCD_DOUT_BIT_ORDER_R = crate::BitReader; +#[doc = "Field `LCD_DOUT_BIT_ORDER` writer - 1: change bit order in every byte. 0: Not change."] +pub type LCD_DOUT_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_BYTE_MODE` reader - 2: 24bit mode. 1: 16bit mode. 0: 8bit mode"] +pub type LCD_BYTE_MODE_R = crate::FieldReader; +#[doc = "Field `LCD_BYTE_MODE` writer - 2: 24bit mode. 1: 16bit mode. 0: 8bit mode"] +pub type LCD_BYTE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LCD_UPDATE` reader - 1: Update LCD registers, will be cleared by hardware. 0 : Not care."] +pub type LCD_UPDATE_R = crate::BitReader; +#[doc = "Field `LCD_UPDATE` writer - 1: Update LCD registers, will be cleared by hardware. 0 : Not care."] +pub type LCD_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_BIT_ORDER` reader - 1: Change data bit order, change LCD_DATA_out\\[7:0\\] to LCD_DATA_out\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] +pub type LCD_BIT_ORDER_R = crate::BitReader; +#[doc = "Field `LCD_BIT_ORDER` writer - 1: Change data bit order, change LCD_DATA_out\\[7:0\\] to LCD_DATA_out\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] +pub type LCD_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_BYTE_ORDER` reader - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] +pub type LCD_BYTE_ORDER_R = crate::BitReader; +#[doc = "Field `LCD_BYTE_ORDER` writer - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] +pub type LCD_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_DOUT` reader - 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable."] +pub type LCD_DOUT_R = crate::BitReader; +#[doc = "Field `LCD_DOUT` writer - 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable."] +pub type LCD_DOUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_DUMMY` reader - 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable."] +pub type LCD_DUMMY_R = crate::BitReader; +#[doc = "Field `LCD_DUMMY` writer - 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable."] +pub type LCD_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_CMD` reader - 1: Be able to send command in LCD sequence when LCD starts. 0: Disable."] +pub type LCD_CMD_R = crate::BitReader; +#[doc = "Field `LCD_CMD` writer - 1: Be able to send command in LCD sequence when LCD starts. 0: Disable."] +pub type LCD_CMD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_START` reader - LCD start sending data enable signal, valid in high level."] +pub type LCD_START_R = crate::BitReader; +#[doc = "Field `LCD_START` writer - LCD start sending data enable signal, valid in high level."] +pub type LCD_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_RESET` writer - The value of command."] +pub type LCD_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LCD_DUMMY_CYCLELEN` reader - The dummy cycle length minus 1."] +pub type LCD_DUMMY_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `LCD_DUMMY_CYCLELEN` writer - The dummy cycle length minus 1."] +pub type LCD_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LCD_CMD_2_CYCLE_EN` reader - The cycle length of command phase. 1: 2 cycles. 0: 1 cycle."] +pub type LCD_CMD_2_CYCLE_EN_R = crate::BitReader; +#[doc = "Field `LCD_CMD_2_CYCLE_EN` writer - The cycle length of command phase. 1: 2 cycles. 0: 1 cycle."] +pub type LCD_CMD_2_CYCLE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:12 - The output data cycles minus 1 of LCD module."] + #[inline(always)] + pub fn lcd_dout_cyclelen(&self) -> LCD_DOUT_CYCLELEN_R { + LCD_DOUT_CYCLELEN_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bit 13 - LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set."] + #[inline(always)] + pub fn lcd_always_out_en(&self) -> LCD_ALWAYS_OUT_EN_R { + LCD_ALWAYS_OUT_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:16 - 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA"] + #[inline(always)] + pub fn lcd_dout_byte_swizzle_mode(&self) -> LCD_DOUT_BYTE_SWIZZLE_MODE_R { + LCD_DOUT_BYTE_SWIZZLE_MODE_R::new(((self.bits >> 14) & 7) as u8) + } + #[doc = "Bit 17 - 1: enable byte swizzle 0: disable"] + #[inline(always)] + pub fn lcd_dout_byte_swizzle_enable(&self) -> LCD_DOUT_BYTE_SWIZZLE_ENABLE_R { + LCD_DOUT_BYTE_SWIZZLE_ENABLE_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - 1: change bit order in every byte. 0: Not change."] + #[inline(always)] + pub fn lcd_dout_bit_order(&self) -> LCD_DOUT_BIT_ORDER_R { + LCD_DOUT_BIT_ORDER_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:20 - 2: 24bit mode. 1: 16bit mode. 0: 8bit mode"] + #[inline(always)] + pub fn lcd_byte_mode(&self) -> LCD_BYTE_MODE_R { + LCD_BYTE_MODE_R::new(((self.bits >> 19) & 3) as u8) + } + #[doc = "Bit 21 - 1: Update LCD registers, will be cleared by hardware. 0 : Not care."] + #[inline(always)] + pub fn lcd_update(&self) -> LCD_UPDATE_R { + LCD_UPDATE_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - 1: Change data bit order, change LCD_DATA_out\\[7:0\\] to LCD_DATA_out\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] + #[inline(always)] + pub fn lcd_bit_order(&self) -> LCD_BIT_ORDER_R { + LCD_BIT_ORDER_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] + #[inline(always)] + pub fn lcd_byte_order(&self) -> LCD_BYTE_ORDER_R { + LCD_BYTE_ORDER_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable."] + #[inline(always)] + pub fn lcd_dout(&self) -> LCD_DOUT_R { + LCD_DOUT_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable."] + #[inline(always)] + pub fn lcd_dummy(&self) -> LCD_DUMMY_R { + LCD_DUMMY_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - 1: Be able to send command in LCD sequence when LCD starts. 0: Disable."] + #[inline(always)] + pub fn lcd_cmd(&self) -> LCD_CMD_R { + LCD_CMD_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - LCD start sending data enable signal, valid in high level."] + #[inline(always)] + pub fn lcd_start(&self) -> LCD_START_R { + LCD_START_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 29:30 - The dummy cycle length minus 1."] + #[inline(always)] + pub fn lcd_dummy_cyclelen(&self) -> LCD_DUMMY_CYCLELEN_R { + LCD_DUMMY_CYCLELEN_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - The cycle length of command phase. 1: 2 cycles. 0: 1 cycle."] + #[inline(always)] + pub fn lcd_cmd_2_cycle_en(&self) -> LCD_CMD_2_CYCLE_EN_R { + LCD_CMD_2_CYCLE_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_USER") + .field( + "lcd_dout_cyclelen", + &format_args!("{}", self.lcd_dout_cyclelen().bits()), + ) + .field( + "lcd_always_out_en", + &format_args!("{}", self.lcd_always_out_en().bit()), + ) + .field( + "lcd_dout_byte_swizzle_mode", + &format_args!("{}", self.lcd_dout_byte_swizzle_mode().bits()), + ) + .field( + "lcd_dout_byte_swizzle_enable", + &format_args!("{}", self.lcd_dout_byte_swizzle_enable().bit()), + ) + .field( + "lcd_dout_bit_order", + &format_args!("{}", self.lcd_dout_bit_order().bit()), + ) + .field( + "lcd_byte_mode", + &format_args!("{}", self.lcd_byte_mode().bits()), + ) + .field("lcd_update", &format_args!("{}", self.lcd_update().bit())) + .field( + "lcd_bit_order", + &format_args!("{}", self.lcd_bit_order().bit()), + ) + .field( + "lcd_byte_order", + &format_args!("{}", self.lcd_byte_order().bit()), + ) + .field("lcd_dout", &format_args!("{}", self.lcd_dout().bit())) + .field("lcd_dummy", &format_args!("{}", self.lcd_dummy().bit())) + .field("lcd_cmd", &format_args!("{}", self.lcd_cmd().bit())) + .field("lcd_start", &format_args!("{}", self.lcd_start().bit())) + .field( + "lcd_dummy_cyclelen", + &format_args!("{}", self.lcd_dummy_cyclelen().bits()), + ) + .field( + "lcd_cmd_2_cycle_en", + &format_args!("{}", self.lcd_cmd_2_cycle_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:12 - The output data cycles minus 1 of LCD module."] + #[inline(always)] + #[must_use] + pub fn lcd_dout_cyclelen(&mut self) -> LCD_DOUT_CYCLELEN_W { + LCD_DOUT_CYCLELEN_W::new(self, 0) + } + #[doc = "Bit 13 - LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set."] + #[inline(always)] + #[must_use] + pub fn lcd_always_out_en(&mut self) -> LCD_ALWAYS_OUT_EN_W { + LCD_ALWAYS_OUT_EN_W::new(self, 13) + } + #[doc = "Bits 14:16 - 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA"] + #[inline(always)] + #[must_use] + pub fn lcd_dout_byte_swizzle_mode(&mut self) -> LCD_DOUT_BYTE_SWIZZLE_MODE_W { + LCD_DOUT_BYTE_SWIZZLE_MODE_W::new(self, 14) + } + #[doc = "Bit 17 - 1: enable byte swizzle 0: disable"] + #[inline(always)] + #[must_use] + pub fn lcd_dout_byte_swizzle_enable( + &mut self, + ) -> LCD_DOUT_BYTE_SWIZZLE_ENABLE_W { + LCD_DOUT_BYTE_SWIZZLE_ENABLE_W::new(self, 17) + } + #[doc = "Bit 18 - 1: change bit order in every byte. 0: Not change."] + #[inline(always)] + #[must_use] + pub fn lcd_dout_bit_order(&mut self) -> LCD_DOUT_BIT_ORDER_W { + LCD_DOUT_BIT_ORDER_W::new(self, 18) + } + #[doc = "Bits 19:20 - 2: 24bit mode. 1: 16bit mode. 0: 8bit mode"] + #[inline(always)] + #[must_use] + pub fn lcd_byte_mode(&mut self) -> LCD_BYTE_MODE_W { + LCD_BYTE_MODE_W::new(self, 19) + } + #[doc = "Bit 21 - 1: Update LCD registers, will be cleared by hardware. 0 : Not care."] + #[inline(always)] + #[must_use] + pub fn lcd_update(&mut self) -> LCD_UPDATE_W { + LCD_UPDATE_W::new(self, 21) + } + #[doc = "Bit 22 - 1: Change data bit order, change LCD_DATA_out\\[7:0\\] to LCD_DATA_out\\[0:7\\] in one byte mode, and bits\\[15:0\\] to bits\\[0:15\\] in two byte mode. 0: Not change."] + #[inline(always)] + #[must_use] + pub fn lcd_bit_order(&mut self) -> LCD_BIT_ORDER_W { + LCD_BIT_ORDER_W::new(self, 22) + } + #[doc = "Bit 23 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change."] + #[inline(always)] + #[must_use] + pub fn lcd_byte_order(&mut self) -> LCD_BYTE_ORDER_W { + LCD_BYTE_ORDER_W::new(self, 23) + } + #[doc = "Bit 24 - 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable."] + #[inline(always)] + #[must_use] + pub fn lcd_dout(&mut self) -> LCD_DOUT_W { + LCD_DOUT_W::new(self, 24) + } + #[doc = "Bit 25 - 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable."] + #[inline(always)] + #[must_use] + pub fn lcd_dummy(&mut self) -> LCD_DUMMY_W { + LCD_DUMMY_W::new(self, 25) + } + #[doc = "Bit 26 - 1: Be able to send command in LCD sequence when LCD starts. 0: Disable."] + #[inline(always)] + #[must_use] + pub fn lcd_cmd(&mut self) -> LCD_CMD_W { + LCD_CMD_W::new(self, 26) + } + #[doc = "Bit 27 - LCD start sending data enable signal, valid in high level."] + #[inline(always)] + #[must_use] + pub fn lcd_start(&mut self) -> LCD_START_W { + LCD_START_W::new(self, 27) + } + #[doc = "Bit 28 - The value of command."] + #[inline(always)] + #[must_use] + pub fn lcd_reset(&mut self) -> LCD_RESET_W { + LCD_RESET_W::new(self, 28) + } + #[doc = "Bits 29:30 - The dummy cycle length minus 1."] + #[inline(always)] + #[must_use] + pub fn lcd_dummy_cyclelen(&mut self) -> LCD_DUMMY_CYCLELEN_W { + LCD_DUMMY_CYCLELEN_W::new(self, 29) + } + #[doc = "Bit 31 - The cycle length of command phase. 1: 2 cycles. 0: 1 cycle."] + #[inline(always)] + #[must_use] + pub fn lcd_cmd_2_cycle_en(&mut self) -> LCD_CMD_2_CYCLE_EN_W { + LCD_CMD_2_CYCLE_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LCD config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcd_user::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcd_user::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LCD_USER_SPEC; +impl crate::RegisterSpec for LCD_USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcd_user::R`](R) reader structure"] +impl crate::Readable for LCD_USER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lcd_user::W`](W) writer structure"] +impl crate::Writable for LCD_USER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LCD_USER to value 0x01"] +impl crate::Resettable for LCD_USER_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/ledc.rs b/esp32p4/src/ledc.rs new file mode 100644 index 0000000000..7a8c5fa997 --- /dev/null +++ b/esp32p4/src/ledc.rs @@ -0,0 +1,565 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + ch_conf0: (), + _reserved1: [u8; 0x04], + ch_hpoint: (), + _reserved2: [u8; 0x04], + ch_duty: (), + _reserved3: [u8; 0x04], + ch_conf1: (), + _reserved4: [u8; 0x04], + ch_duty_r: (), + _reserved5: [u8; 0x90], + timer_conf: (), + _reserved6: [u8; 0x04], + timer_value: (), + _reserved7: [u8; 0x1c], + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + _reserved11: [u8; 0x30], + ch_gamma_conf: [CH_GAMMA_CONF; 8], + evt_task_en0: EVT_TASK_EN0, + evt_task_en1: EVT_TASK_EN1, + evt_task_en2: EVT_TASK_EN2, + _reserved15: [u8; 0x14], + timer_cmp: [TIMER_CMP; 4], + timer_cnt_cap: [TIMER_CNT_CAP; 4], + _reserved17: [u8; 0x10], + conf: CONF, + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00..0x20 - Configuration register 0 for channel %s"] + #[inline(always)] + pub const fn ch_conf0(&self, n: usize) -> &CH_CONF0 { + #[allow(clippy::no_effect)] + [(); 8][n]; + unsafe { &*(self as *const Self).cast::().add(0).add(20 * n).cast() } + } + #[doc = "0x00 - Configuration register 0 for channel 0"] + #[inline(always)] + pub const fn ch0_conf0(&self) -> &CH_CONF0 { + &self.ch_conf0(0) + } + #[doc = "0x14 - Configuration register 0 for channel 1"] + #[inline(always)] + pub const fn ch1_conf0(&self) -> &CH_CONF0 { + &self.ch_conf0(1) + } + #[doc = "0x28 - Configuration register 0 for channel 2"] + #[inline(always)] + pub const fn ch2_conf0(&self) -> &CH_CONF0 { + &self.ch_conf0(2) + } + #[doc = "0x3c - Configuration register 0 for channel 3"] + #[inline(always)] + pub const fn ch3_conf0(&self) -> &CH_CONF0 { + &self.ch_conf0(3) + } + #[doc = "0x50 - Configuration register 0 for channel 4"] + #[inline(always)] + pub const fn ch4_conf0(&self) -> &CH_CONF0 { + &self.ch_conf0(4) + } + #[doc = "0x64 - Configuration register 0 for channel 5"] + #[inline(always)] + pub const fn ch5_conf0(&self) -> &CH_CONF0 { + &self.ch_conf0(5) + } + #[doc = "0x78 - Configuration register 0 for channel 6"] + #[inline(always)] + pub const fn ch6_conf0(&self) -> &CH_CONF0 { + &self.ch_conf0(6) + } + #[doc = "0x8c - Configuration register 0 for channel 7"] + #[inline(always)] + pub const fn ch7_conf0(&self) -> &CH_CONF0 { + &self.ch_conf0(7) + } + #[doc = "0x04..0x24 - High point register for channel %s"] + #[inline(always)] + pub const fn ch_hpoint(&self, n: usize) -> &CH_HPOINT { + #[allow(clippy::no_effect)] + [(); 8][n]; + unsafe { &*(self as *const Self).cast::().add(4).add(20 * n).cast() } + } + #[doc = "0x04 - High point register for channel 0"] + #[inline(always)] + pub const fn ch0_hpoint(&self) -> &CH_HPOINT { + &self.ch_hpoint(0) + } + #[doc = "0x18 - High point register for channel 1"] + #[inline(always)] + pub const fn ch1_hpoint(&self) -> &CH_HPOINT { + &self.ch_hpoint(1) + } + #[doc = "0x2c - High point register for channel 2"] + #[inline(always)] + pub const fn ch2_hpoint(&self) -> &CH_HPOINT { + &self.ch_hpoint(2) + } + #[doc = "0x40 - High point register for channel 3"] + #[inline(always)] + pub const fn ch3_hpoint(&self) -> &CH_HPOINT { + &self.ch_hpoint(3) + } + #[doc = "0x54 - High point register for channel 4"] + #[inline(always)] + pub const fn ch4_hpoint(&self) -> &CH_HPOINT { + &self.ch_hpoint(4) + } + #[doc = "0x68 - High point register for channel 5"] + #[inline(always)] + pub const fn ch5_hpoint(&self) -> &CH_HPOINT { + &self.ch_hpoint(5) + } + #[doc = "0x7c - High point register for channel 6"] + #[inline(always)] + pub const fn ch6_hpoint(&self) -> &CH_HPOINT { + &self.ch_hpoint(6) + } + #[doc = "0x90 - High point register for channel 7"] + #[inline(always)] + pub const fn ch7_hpoint(&self) -> &CH_HPOINT { + &self.ch_hpoint(7) + } + #[doc = "0x08..0x28 - Initial duty cycle register for channel %s"] + #[inline(always)] + pub const fn ch_duty(&self, n: usize) -> &CH_DUTY { + #[allow(clippy::no_effect)] + [(); 8][n]; + unsafe { &*(self as *const Self).cast::().add(8).add(20 * n).cast() } + } + #[doc = "0x08 - Initial duty cycle register for channel 0"] + #[inline(always)] + pub const fn ch0_duty(&self) -> &CH_DUTY { + &self.ch_duty(0) + } + #[doc = "0x1c - Initial duty cycle register for channel 1"] + #[inline(always)] + pub const fn ch1_duty(&self) -> &CH_DUTY { + &self.ch_duty(1) + } + #[doc = "0x30 - Initial duty cycle register for channel 2"] + #[inline(always)] + pub const fn ch2_duty(&self) -> &CH_DUTY { + &self.ch_duty(2) + } + #[doc = "0x44 - Initial duty cycle register for channel 3"] + #[inline(always)] + pub const fn ch3_duty(&self) -> &CH_DUTY { + &self.ch_duty(3) + } + #[doc = "0x58 - Initial duty cycle register for channel 4"] + #[inline(always)] + pub const fn ch4_duty(&self) -> &CH_DUTY { + &self.ch_duty(4) + } + #[doc = "0x6c - Initial duty cycle register for channel 5"] + #[inline(always)] + pub const fn ch5_duty(&self) -> &CH_DUTY { + &self.ch_duty(5) + } + #[doc = "0x80 - Initial duty cycle register for channel 6"] + #[inline(always)] + pub const fn ch6_duty(&self) -> &CH_DUTY { + &self.ch_duty(6) + } + #[doc = "0x94 - Initial duty cycle register for channel 7"] + #[inline(always)] + pub const fn ch7_duty(&self) -> &CH_DUTY { + &self.ch_duty(7) + } + #[doc = "0x0c..0x2c - Configuration register 1 for channel %s"] + #[inline(always)] + pub const fn ch_conf1(&self, n: usize) -> &CH_CONF1 { + #[allow(clippy::no_effect)] + [(); 8][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(12) + .add(20 * n) + .cast() + } + } + #[doc = "0x0c - Configuration register 1 for channel 0"] + #[inline(always)] + pub const fn ch0_conf1(&self) -> &CH_CONF1 { + &self.ch_conf1(0) + } + #[doc = "0x20 - Configuration register 1 for channel 1"] + #[inline(always)] + pub const fn ch1_conf1(&self) -> &CH_CONF1 { + &self.ch_conf1(1) + } + #[doc = "0x34 - Configuration register 1 for channel 2"] + #[inline(always)] + pub const fn ch2_conf1(&self) -> &CH_CONF1 { + &self.ch_conf1(2) + } + #[doc = "0x48 - Configuration register 1 for channel 3"] + #[inline(always)] + pub const fn ch3_conf1(&self) -> &CH_CONF1 { + &self.ch_conf1(3) + } + #[doc = "0x5c - Configuration register 1 for channel 4"] + #[inline(always)] + pub const fn ch4_conf1(&self) -> &CH_CONF1 { + &self.ch_conf1(4) + } + #[doc = "0x70 - Configuration register 1 for channel 5"] + #[inline(always)] + pub const fn ch5_conf1(&self) -> &CH_CONF1 { + &self.ch_conf1(5) + } + #[doc = "0x84 - Configuration register 1 for channel 6"] + #[inline(always)] + pub const fn ch6_conf1(&self) -> &CH_CONF1 { + &self.ch_conf1(6) + } + #[doc = "0x98 - Configuration register 1 for channel 7"] + #[inline(always)] + pub const fn ch7_conf1(&self) -> &CH_CONF1 { + &self.ch_conf1(7) + } + #[doc = "0x10..0x30 - Current duty cycle register for channel %s"] + #[inline(always)] + pub const fn ch_duty_r(&self, n: usize) -> &CH_DUTY_R { + #[allow(clippy::no_effect)] + [(); 8][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(16) + .add(20 * n) + .cast() + } + } + #[doc = "0x10 - Current duty cycle register for channel 0"] + #[inline(always)] + pub const fn ch0_duty_r(&self) -> &CH_DUTY_R { + &self.ch_duty_r(0) + } + #[doc = "0x24 - Current duty cycle register for channel 1"] + #[inline(always)] + pub const fn ch1_duty_r(&self) -> &CH_DUTY_R { + &self.ch_duty_r(1) + } + #[doc = "0x38 - Current duty cycle register for channel 2"] + #[inline(always)] + pub const fn ch2_duty_r(&self) -> &CH_DUTY_R { + &self.ch_duty_r(2) + } + #[doc = "0x4c - Current duty cycle register for channel 3"] + #[inline(always)] + pub const fn ch3_duty_r(&self) -> &CH_DUTY_R { + &self.ch_duty_r(3) + } + #[doc = "0x60 - Current duty cycle register for channel 4"] + #[inline(always)] + pub const fn ch4_duty_r(&self) -> &CH_DUTY_R { + &self.ch_duty_r(4) + } + #[doc = "0x74 - Current duty cycle register for channel 5"] + #[inline(always)] + pub const fn ch5_duty_r(&self) -> &CH_DUTY_R { + &self.ch_duty_r(5) + } + #[doc = "0x88 - Current duty cycle register for channel 6"] + #[inline(always)] + pub const fn ch6_duty_r(&self) -> &CH_DUTY_R { + &self.ch_duty_r(6) + } + #[doc = "0x9c - Current duty cycle register for channel 7"] + #[inline(always)] + pub const fn ch7_duty_r(&self) -> &CH_DUTY_R { + &self.ch_duty_r(7) + } + #[doc = "0xa0..0xb0 - Timer %s configuration register"] + #[inline(always)] + pub const fn timer_conf(&self, n: usize) -> &TIMER_CONF { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(160) + .add(8 * n) + .cast() + } + } + #[doc = "0xa0 - Timer 0 configuration register"] + #[inline(always)] + pub const fn timer0_conf(&self) -> &TIMER_CONF { + &self.timer_conf(0) + } + #[doc = "0xa8 - Timer 1 configuration register"] + #[inline(always)] + pub const fn timer1_conf(&self) -> &TIMER_CONF { + &self.timer_conf(1) + } + #[doc = "0xb0 - Timer 2 configuration register"] + #[inline(always)] + pub const fn timer2_conf(&self) -> &TIMER_CONF { + &self.timer_conf(2) + } + #[doc = "0xb8 - Timer 3 configuration register"] + #[inline(always)] + pub const fn timer3_conf(&self) -> &TIMER_CONF { + &self.timer_conf(3) + } + #[doc = "0xa4..0xb4 - Timer %s current counter value register"] + #[inline(always)] + pub const fn timer_value(&self, n: usize) -> &TIMER_VALUE { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(164) + .add(8 * n) + .cast() + } + } + #[doc = "0xa4 - Timer 0 current counter value register"] + #[inline(always)] + pub const fn timer0_value(&self) -> &TIMER_VALUE { + &self.timer_value(0) + } + #[doc = "0xac - Timer 1 current counter value register"] + #[inline(always)] + pub const fn timer1_value(&self) -> &TIMER_VALUE { + &self.timer_value(1) + } + #[doc = "0xb4 - Timer 2 current counter value register"] + #[inline(always)] + pub const fn timer2_value(&self) -> &TIMER_VALUE { + &self.timer_value(2) + } + #[doc = "0xbc - Timer 3 current counter value register"] + #[inline(always)] + pub const fn timer3_value(&self) -> &TIMER_VALUE { + &self.timer_value(3) + } + #[doc = "0xc0 - Interrupt raw status register"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0xc4 - Interrupt masked status register"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0xc8 - Interrupt enable register"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0xcc - Interrupt clear register"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x100..0x120 - Ledc ch%s gamma config register."] + #[inline(always)] + pub const fn ch_gamma_conf(&self, n: usize) -> &CH_GAMMA_CONF { + &self.ch_gamma_conf[n] + } + #[doc = "0x100 - Ledc ch0 gamma config register."] + #[inline(always)] + pub const fn ch0_gamma_conf(&self) -> &CH_GAMMA_CONF { + &self.ch_gamma_conf(0) + } + #[doc = "0x104 - Ledc ch1 gamma config register."] + #[inline(always)] + pub const fn ch1_gamma_conf(&self) -> &CH_GAMMA_CONF { + &self.ch_gamma_conf(1) + } + #[doc = "0x108 - Ledc ch2 gamma config register."] + #[inline(always)] + pub const fn ch2_gamma_conf(&self) -> &CH_GAMMA_CONF { + &self.ch_gamma_conf(2) + } + #[doc = "0x10c - Ledc ch3 gamma config register."] + #[inline(always)] + pub const fn ch3_gamma_conf(&self) -> &CH_GAMMA_CONF { + &self.ch_gamma_conf(3) + } + #[doc = "0x110 - Ledc ch4 gamma config register."] + #[inline(always)] + pub const fn ch4_gamma_conf(&self) -> &CH_GAMMA_CONF { + &self.ch_gamma_conf(4) + } + #[doc = "0x114 - Ledc ch5 gamma config register."] + #[inline(always)] + pub const fn ch5_gamma_conf(&self) -> &CH_GAMMA_CONF { + &self.ch_gamma_conf(5) + } + #[doc = "0x118 - Ledc ch6 gamma config register."] + #[inline(always)] + pub const fn ch6_gamma_conf(&self) -> &CH_GAMMA_CONF { + &self.ch_gamma_conf(6) + } + #[doc = "0x11c - Ledc ch7 gamma config register."] + #[inline(always)] + pub const fn ch7_gamma_conf(&self) -> &CH_GAMMA_CONF { + &self.ch_gamma_conf(7) + } + #[doc = "0x120 - Ledc event task enable bit register0."] + #[inline(always)] + pub const fn evt_task_en0(&self) -> &EVT_TASK_EN0 { + &self.evt_task_en0 + } + #[doc = "0x124 - Ledc event task enable bit register1."] + #[inline(always)] + pub const fn evt_task_en1(&self) -> &EVT_TASK_EN1 { + &self.evt_task_en1 + } + #[doc = "0x128 - Ledc event task enable bit register2."] + #[inline(always)] + pub const fn evt_task_en2(&self) -> &EVT_TASK_EN2 { + &self.evt_task_en2 + } + #[doc = "0x140..0x150 - Ledc timer%s compare value register."] + #[inline(always)] + pub const fn timer_cmp(&self, n: usize) -> &TIMER_CMP { + &self.timer_cmp[n] + } + #[doc = "0x140 - Ledc timer0 compare value register."] + #[inline(always)] + pub const fn timer0_cmp(&self) -> &TIMER_CMP { + &self.timer_cmp(0) + } + #[doc = "0x144 - Ledc timer1 compare value register."] + #[inline(always)] + pub const fn timer1_cmp(&self) -> &TIMER_CMP { + &self.timer_cmp(1) + } + #[doc = "0x148 - Ledc timer2 compare value register."] + #[inline(always)] + pub const fn timer2_cmp(&self) -> &TIMER_CMP { + &self.timer_cmp(2) + } + #[doc = "0x14c - Ledc timer3 compare value register."] + #[inline(always)] + pub const fn timer3_cmp(&self) -> &TIMER_CMP { + &self.timer_cmp(3) + } + #[doc = "0x150..0x160 - Ledc timer%s captured count value register."] + #[inline(always)] + pub const fn timer_cnt_cap(&self, n: usize) -> &TIMER_CNT_CAP { + &self.timer_cnt_cap[n] + } + #[doc = "0x150 - Ledc timer0 captured count value register."] + #[inline(always)] + pub const fn timer0_cnt_cap(&self) -> &TIMER_CNT_CAP { + &self.timer_cnt_cap(0) + } + #[doc = "0x154 - Ledc timer1 captured count value register."] + #[inline(always)] + pub const fn timer1_cnt_cap(&self) -> &TIMER_CNT_CAP { + &self.timer_cnt_cap(1) + } + #[doc = "0x158 - Ledc timer2 captured count value register."] + #[inline(always)] + pub const fn timer2_cnt_cap(&self) -> &TIMER_CNT_CAP { + &self.timer_cnt_cap(2) + } + #[doc = "0x15c - Ledc timer3 captured count value register."] + #[inline(always)] + pub const fn timer3_cnt_cap(&self) -> &TIMER_CNT_CAP { + &self.timer_cnt_cap(3) + } + #[doc = "0x170 - LEDC global configuration register"] + #[inline(always)] + pub const fn conf(&self) -> &CONF { + &self.conf + } + #[doc = "0x174 - Version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "CH_CONF0 (rw) register accessor: Configuration register 0 for channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_conf0`] module"] +pub type CH_CONF0 = crate::Reg; +#[doc = "Configuration register 0 for channel %s"] +pub mod ch_conf0; +#[doc = "CH_HPOINT (rw) register accessor: High point register for channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_hpoint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_hpoint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_hpoint`] module"] +pub type CH_HPOINT = crate::Reg; +#[doc = "High point register for channel %s"] +pub mod ch_hpoint; +#[doc = "CH_DUTY (rw) register accessor: Initial duty cycle register for channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_duty::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_duty::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_duty`] module"] +pub type CH_DUTY = crate::Reg; +#[doc = "Initial duty cycle register for channel %s"] +pub mod ch_duty; +#[doc = "CH_CONF1 (rw) register accessor: Configuration register 1 for channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_conf1`] module"] +pub type CH_CONF1 = crate::Reg; +#[doc = "Configuration register 1 for channel %s"] +pub mod ch_conf1; +#[doc = "CH_DUTY_R (r) register accessor: Current duty cycle register for channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_duty_r::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_duty_r`] module"] +pub type CH_DUTY_R = crate::Reg; +#[doc = "Current duty cycle register for channel %s"] +pub mod ch_duty_r; +#[doc = "TIMER_CONF (rw) register accessor: Timer %s configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_conf`] module"] +pub type TIMER_CONF = crate::Reg; +#[doc = "Timer %s configuration register"] +pub mod timer_conf; +#[doc = "TIMER_VALUE (r) register accessor: Timer %s current counter value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_value::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_value`] module"] +pub type TIMER_VALUE = crate::Reg; +#[doc = "Timer %s current counter value register"] +pub mod timer_value; +#[doc = "INT_RAW (rw) register accessor: Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Interrupt raw status register"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Interrupt masked status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Interrupt masked status register"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable register"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear register"] +pub mod int_clr; +#[doc = "CH_GAMMA_CONF (rw) register accessor: Ledc ch%s gamma config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_gamma_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_gamma_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_gamma_conf`] module"] +pub type CH_GAMMA_CONF = crate::Reg; +#[doc = "Ledc ch%s gamma config register."] +pub mod ch_gamma_conf; +#[doc = "EVT_TASK_EN0 (rw) register accessor: Ledc event task enable bit register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_task_en0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_task_en0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_task_en0`] module"] +pub type EVT_TASK_EN0 = crate::Reg; +#[doc = "Ledc event task enable bit register0."] +pub mod evt_task_en0; +#[doc = "EVT_TASK_EN1 (rw) register accessor: Ledc event task enable bit register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_task_en1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_task_en1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_task_en1`] module"] +pub type EVT_TASK_EN1 = crate::Reg; +#[doc = "Ledc event task enable bit register1."] +pub mod evt_task_en1; +#[doc = "EVT_TASK_EN2 (rw) register accessor: Ledc event task enable bit register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_task_en2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_task_en2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_task_en2`] module"] +pub type EVT_TASK_EN2 = crate::Reg; +#[doc = "Ledc event task enable bit register2."] +pub mod evt_task_en2; +#[doc = "TIMER_CMP (rw) register accessor: Ledc timer%s compare value register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_cmp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_cmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_cmp`] module"] +pub type TIMER_CMP = crate::Reg; +#[doc = "Ledc timer%s compare value register."] +pub mod timer_cmp; +#[doc = "TIMER_CNT_CAP (r) register accessor: Ledc timer%s captured count value register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_cnt_cap::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_cnt_cap`] module"] +pub type TIMER_CNT_CAP = crate::Reg; +#[doc = "Ledc timer%s captured count value register."] +pub mod timer_cnt_cap; +#[doc = "CONF (rw) register accessor: LEDC global configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"] +pub type CONF = crate::Reg; +#[doc = "LEDC global configuration register"] +pub mod conf; +#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version control register"] +pub mod date; diff --git a/esp32p4/src/ledc/ch_conf0.rs b/esp32p4/src/ledc/ch_conf0.rs new file mode 100644 index 0000000000..0fcd1bb1f9 --- /dev/null +++ b/esp32p4/src/ledc/ch_conf0.rs @@ -0,0 +1,152 @@ +#[doc = "Register `CH%s_CONF0` reader"] +pub type R = crate::R; +#[doc = "Register `CH%s_CONF0` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_SEL_CH` reader - Configures which timer is channel %s selected.\\\\0: Select timer0\\\\1: Select timer1\\\\2: Select timer2\\\\3: Select timer3"] +pub type TIMER_SEL_CH_R = crate::FieldReader; +#[doc = "Field `TIMER_SEL_CH` writer - Configures which timer is channel %s selected.\\\\0: Select timer0\\\\1: Select timer1\\\\2: Select timer2\\\\3: Select timer3"] +pub type TIMER_SEL_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SIG_OUT_EN_CH` reader - Configures whether or not to enable signal output on channel %s.\\\\0: Signal output disable\\\\1: Signal output enable"] +pub type SIG_OUT_EN_CH_R = crate::BitReader; +#[doc = "Field `SIG_OUT_EN_CH` writer - Configures whether or not to enable signal output on channel %s.\\\\0: Signal output disable\\\\1: Signal output enable"] +pub type SIG_OUT_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE_LV_CH` reader - Configures the output value when channel %s is inactive. Valid only when LEDC_SIG_OUT_EN_CH%s is 0.\\\\0: Output level is low\\\\1: Output level is high"] +pub type IDLE_LV_CH_R = crate::BitReader; +#[doc = "Field `IDLE_LV_CH` writer - Configures the output value when channel %s is inactive. Valid only when LEDC_SIG_OUT_EN_CH%s is 0.\\\\0: Output level is low\\\\1: Output level is high"] +pub type IDLE_LV_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARA_UP_CH` writer - Configures whether or not to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.\\\\0: Invalid. No effect\\\\1: Update"] +pub type PARA_UP_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_NUM_CH` reader - Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."] +pub type OVF_NUM_CH_R = crate::FieldReader; +#[doc = "Field `OVF_NUM_CH` writer - Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."] +pub type OVF_NUM_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `OVF_CNT_EN_CH` reader - Configures whether or not to enable the ovf_cnt of channel %s.\\\\0: Disable\\\\1: Enable"] +pub type OVF_CNT_EN_CH_R = crate::BitReader; +#[doc = "Field `OVF_CNT_EN_CH` writer - Configures whether or not to enable the ovf_cnt of channel %s.\\\\0: Disable\\\\1: Enable"] +pub type OVF_CNT_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_RESET_CH` writer - Configures whether or not to reset the ovf_cnt of channel %s.\\\\0: Invalid. No effect\\\\1: Reset the ovf_cnt"] +pub type OVF_CNT_RESET_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Configures which timer is channel %s selected.\\\\0: Select timer0\\\\1: Select timer1\\\\2: Select timer2\\\\3: Select timer3"] + #[inline(always)] + pub fn timer_sel_ch(&self) -> TIMER_SEL_CH_R { + TIMER_SEL_CH_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Configures whether or not to enable signal output on channel %s.\\\\0: Signal output disable\\\\1: Signal output enable"] + #[inline(always)] + pub fn sig_out_en_ch(&self) -> SIG_OUT_EN_CH_R { + SIG_OUT_EN_CH_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures the output value when channel %s is inactive. Valid only when LEDC_SIG_OUT_EN_CH%s is 0.\\\\0: Output level is low\\\\1: Output level is high"] + #[inline(always)] + pub fn idle_lv_ch(&self) -> IDLE_LV_CH_R { + IDLE_LV_CH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 5:14 - Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."] + #[inline(always)] + pub fn ovf_num_ch(&self) -> OVF_NUM_CH_R { + OVF_NUM_CH_R::new(((self.bits >> 5) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Configures whether or not to enable the ovf_cnt of channel %s.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ovf_cnt_en_ch(&self) -> OVF_CNT_EN_CH_R { + OVF_CNT_EN_CH_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH_CONF0") + .field( + "timer_sel_ch", + &format_args!("{}", self.timer_sel_ch().bits()), + ) + .field( + "sig_out_en_ch", + &format_args!("{}", self.sig_out_en_ch().bit()), + ) + .field("idle_lv_ch", &format_args!("{}", self.idle_lv_ch().bit())) + .field("ovf_num_ch", &format_args!("{}", self.ovf_num_ch().bits())) + .field( + "ovf_cnt_en_ch", + &format_args!("{}", self.ovf_cnt_en_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Configures which timer is channel %s selected.\\\\0: Select timer0\\\\1: Select timer1\\\\2: Select timer2\\\\3: Select timer3"] + #[inline(always)] + #[must_use] + pub fn timer_sel_ch(&mut self) -> TIMER_SEL_CH_W { + TIMER_SEL_CH_W::new(self, 0) + } + #[doc = "Bit 2 - Configures whether or not to enable signal output on channel %s.\\\\0: Signal output disable\\\\1: Signal output enable"] + #[inline(always)] + #[must_use] + pub fn sig_out_en_ch(&mut self) -> SIG_OUT_EN_CH_W { + SIG_OUT_EN_CH_W::new(self, 2) + } + #[doc = "Bit 3 - Configures the output value when channel %s is inactive. Valid only when LEDC_SIG_OUT_EN_CH%s is 0.\\\\0: Output level is low\\\\1: Output level is high"] + #[inline(always)] + #[must_use] + pub fn idle_lv_ch(&mut self) -> IDLE_LV_CH_W { + IDLE_LV_CH_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.\\\\0: Invalid. No effect\\\\1: Update"] + #[inline(always)] + #[must_use] + pub fn para_up_ch(&mut self) -> PARA_UP_CH_W { + PARA_UP_CH_W::new(self, 4) + } + #[doc = "Bits 5:14 - Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."] + #[inline(always)] + #[must_use] + pub fn ovf_num_ch(&mut self) -> OVF_NUM_CH_W { + OVF_NUM_CH_W::new(self, 5) + } + #[doc = "Bit 15 - Configures whether or not to enable the ovf_cnt of channel %s.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_en_ch(&mut self) -> OVF_CNT_EN_CH_W { + OVF_CNT_EN_CH_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to reset the ovf_cnt of channel %s.\\\\0: Invalid. No effect\\\\1: Reset the ovf_cnt"] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_reset_ch(&mut self) -> OVF_CNT_RESET_CH_W { + OVF_CNT_RESET_CH_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register 0 for channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_CONF0_SPEC; +impl crate::RegisterSpec for CH_CONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_conf0::R`](R) reader structure"] +impl crate::Readable for CH_CONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_conf0::W`](W) writer structure"] +impl crate::Writable for CH_CONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH%s_CONF0 to value 0"] +impl crate::Resettable for CH_CONF0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/ch_conf1.rs b/esp32p4/src/ledc/ch_conf1.rs new file mode 100644 index 0000000000..89ca0212a1 --- /dev/null +++ b/esp32p4/src/ledc/ch_conf1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH%s_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `CH%s_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `DUTY_START_CH` reader - Configures whether the duty cycle fading configurations take effect.\\\\0: Not take effect\\\\1: Take effect"] +pub type DUTY_START_CH_R = crate::BitReader; +#[doc = "Field `DUTY_START_CH` writer - Configures whether the duty cycle fading configurations take effect.\\\\0: Not take effect\\\\1: Take effect"] +pub type DUTY_START_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - Configures whether the duty cycle fading configurations take effect.\\\\0: Not take effect\\\\1: Take effect"] + #[inline(always)] + pub fn duty_start_ch(&self) -> DUTY_START_CH_R { + DUTY_START_CH_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH_CONF1") + .field( + "duty_start_ch", + &format_args!("{}", self.duty_start_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - Configures whether the duty cycle fading configurations take effect.\\\\0: Not take effect\\\\1: Take effect"] + #[inline(always)] + #[must_use] + pub fn duty_start_ch(&mut self) -> DUTY_START_CH_W { + DUTY_START_CH_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register 1 for channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_CONF1_SPEC; +impl crate::RegisterSpec for CH_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_conf1::R`](R) reader structure"] +impl crate::Readable for CH_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_conf1::W`](W) writer structure"] +impl crate::Writable for CH_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH%s_CONF1 to value 0"] +impl crate::Resettable for CH_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/ch_duty.rs b/esp32p4/src/ledc/ch_duty.rs new file mode 100644 index 0000000000..ececc0ccf8 --- /dev/null +++ b/esp32p4/src/ledc/ch_duty.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH%s_DUTY` reader"] +pub type R = crate::R; +#[doc = "Register `CH%s_DUTY` writer"] +pub type W = crate::W; +#[doc = "Field `DUTY_CH` reader - Configures the duty of signal output on channel %s."] +pub type DUTY_CH_R = crate::FieldReader; +#[doc = "Field `DUTY_CH` writer - Configures the duty of signal output on channel %s."] +pub type DUTY_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +impl R { + #[doc = "Bits 0:24 - Configures the duty of signal output on channel %s."] + #[inline(always)] + pub fn duty_ch(&self) -> DUTY_CH_R { + DUTY_CH_R::new(self.bits & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH_DUTY") + .field("duty_ch", &format_args!("{}", self.duty_ch().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:24 - Configures the duty of signal output on channel %s."] + #[inline(always)] + #[must_use] + pub fn duty_ch(&mut self) -> DUTY_CH_W { + DUTY_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Initial duty cycle register for channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_duty::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_duty::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_DUTY_SPEC; +impl crate::RegisterSpec for CH_DUTY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_duty::R`](R) reader structure"] +impl crate::Readable for CH_DUTY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_duty::W`](W) writer structure"] +impl crate::Writable for CH_DUTY_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH%s_DUTY to value 0"] +impl crate::Resettable for CH_DUTY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/ch_duty_r.rs b/esp32p4/src/ledc/ch_duty_r.rs new file mode 100644 index 0000000000..64da9831b3 --- /dev/null +++ b/esp32p4/src/ledc/ch_duty_r.rs @@ -0,0 +1,36 @@ +#[doc = "Register `CH%s_DUTY_R` reader"] +pub type R = crate::R; +#[doc = "Field `DUTY_CH_R` reader - Represents the current duty of output signal on channel %s."] +pub type DUTY_CH_R_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:24 - Represents the current duty of output signal on channel %s."] + #[inline(always)] + pub fn duty_ch_r(&self) -> DUTY_CH_R_R { + DUTY_CH_R_R::new(self.bits & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH_DUTY_R") + .field("duty_ch_r", &format_args!("{}", self.duty_ch_r().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Current duty cycle register for channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_duty_r::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_DUTY_R_SPEC; +impl crate::RegisterSpec for CH_DUTY_R_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_duty_r::R`](R) reader structure"] +impl crate::Readable for CH_DUTY_R_SPEC {} +#[doc = "`reset()` method sets CH%s_DUTY_R to value 0"] +impl crate::Resettable for CH_DUTY_R_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/ch_gamma_conf.rs b/esp32p4/src/ledc/ch_gamma_conf.rs new file mode 100644 index 0000000000..40b6bde25e --- /dev/null +++ b/esp32p4/src/ledc/ch_gamma_conf.rs @@ -0,0 +1,82 @@ +#[doc = "Register `CH%s_GAMMA_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CH%s_GAMMA_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CH_GAMMA_ENTRY_NUM` reader - Configures the number of duty cycle fading rages for LEDC ch%s."] +pub type CH_GAMMA_ENTRY_NUM_R = crate::FieldReader; +#[doc = "Field `CH_GAMMA_ENTRY_NUM` writer - Configures the number of duty cycle fading rages for LEDC ch%s."] +pub type CH_GAMMA_ENTRY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `CH_GAMMA_PAUSE` writer - Configures whether or not to pause duty cycle fading of LEDC ch%s.\\\\0: Invalid. No effect\\\\1: Pause"] +pub type CH_GAMMA_PAUSE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_GAMMA_RESUME` writer - Configures whether or nor to resume duty cycle fading of LEDC ch%s.\\\\0: Invalid. No effect\\\\1: Resume"] +pub type CH_GAMMA_RESUME_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Configures the number of duty cycle fading rages for LEDC ch%s."] + #[inline(always)] + pub fn ch_gamma_entry_num(&self) -> CH_GAMMA_ENTRY_NUM_R { + CH_GAMMA_ENTRY_NUM_R::new((self.bits & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH_GAMMA_CONF") + .field( + "ch_gamma_entry_num", + &format_args!("{}", self.ch_gamma_entry_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - Configures the number of duty cycle fading rages for LEDC ch%s."] + #[inline(always)] + #[must_use] + pub fn ch_gamma_entry_num(&mut self) -> CH_GAMMA_ENTRY_NUM_W { + CH_GAMMA_ENTRY_NUM_W::new(self, 0) + } + #[doc = "Bit 5 - Configures whether or not to pause duty cycle fading of LEDC ch%s.\\\\0: Invalid. No effect\\\\1: Pause"] + #[inline(always)] + #[must_use] + pub fn ch_gamma_pause(&mut self) -> CH_GAMMA_PAUSE_W { + CH_GAMMA_PAUSE_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or nor to resume duty cycle fading of LEDC ch%s.\\\\0: Invalid. No effect\\\\1: Resume"] + #[inline(always)] + #[must_use] + pub fn ch_gamma_resume(&mut self) -> CH_GAMMA_RESUME_W { + CH_GAMMA_RESUME_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Ledc ch%s gamma config register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_gamma_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_gamma_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_GAMMA_CONF_SPEC; +impl crate::RegisterSpec for CH_GAMMA_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_gamma_conf::R`](R) reader structure"] +impl crate::Readable for CH_GAMMA_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_gamma_conf::W`](W) writer structure"] +impl crate::Writable for CH_GAMMA_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH%s_GAMMA_CONF to value 0"] +impl crate::Resettable for CH_GAMMA_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/ch_hpoint.rs b/esp32p4/src/ledc/ch_hpoint.rs new file mode 100644 index 0000000000..c41f31c103 --- /dev/null +++ b/esp32p4/src/ledc/ch_hpoint.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH%s_HPOINT` reader"] +pub type R = crate::R; +#[doc = "Register `CH%s_HPOINT` writer"] +pub type W = crate::W; +#[doc = "Field `HPOINT_CH` reader - Configures high point of signal output on channel %s. The output value changes to high when the selected timers has reached the value specified by this register."] +pub type HPOINT_CH_R = crate::FieldReader; +#[doc = "Field `HPOINT_CH` writer - Configures high point of signal output on channel %s. The output value changes to high when the selected timers has reached the value specified by this register."] +pub type HPOINT_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - Configures high point of signal output on channel %s. The output value changes to high when the selected timers has reached the value specified by this register."] + #[inline(always)] + pub fn hpoint_ch(&self) -> HPOINT_CH_R { + HPOINT_CH_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH_HPOINT") + .field("hpoint_ch", &format_args!("{}", self.hpoint_ch().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - Configures high point of signal output on channel %s. The output value changes to high when the selected timers has reached the value specified by this register."] + #[inline(always)] + #[must_use] + pub fn hpoint_ch(&mut self) -> HPOINT_CH_W { + HPOINT_CH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "High point register for channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_hpoint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_hpoint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_HPOINT_SPEC; +impl crate::RegisterSpec for CH_HPOINT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_hpoint::R`](R) reader structure"] +impl crate::Readable for CH_HPOINT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_hpoint::W`](W) writer structure"] +impl crate::Writable for CH_HPOINT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH%s_HPOINT to value 0"] +impl crate::Resettable for CH_HPOINT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/conf.rs b/esp32p4/src/ledc/conf.rs new file mode 100644 index 0000000000..777f8c64cb --- /dev/null +++ b/esp32p4/src/ledc/conf.rs @@ -0,0 +1,234 @@ +#[doc = "Register `CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CONF` writer"] +pub type W = crate::W; +#[doc = "Field `APB_CLK_SEL` reader - Configures the clock source for the four timers.\\\\0: APB_CLK\\\\1: RC_FAST_CLK\\\\2: XTAL_CLK\\\\3: Invalid. No clock"] +pub type APB_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `APB_CLK_SEL` writer - Configures the clock source for the four timers.\\\\0: APB_CLK\\\\1: RC_FAST_CLK\\\\2: XTAL_CLK\\\\3: Invalid. No clock"] +pub type APB_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH0` reader - Configures whether or not to open LEDC ch0 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram\\\\1: Force open the clock gate for LEDC ch0 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH0_R = crate::BitReader; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH0` writer - Configures whether or not to open LEDC ch0 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram\\\\1: Force open the clock gate for LEDC ch0 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH1` reader - Configures whether or not to open LEDC ch1 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram\\\\1: Force open the clock gate for LEDC ch1 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH1_R = crate::BitReader; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH1` writer - Configures whether or not to open LEDC ch1 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram\\\\1: Force open the clock gate for LEDC ch1 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH2` reader - Configures whether or not to open LEDC ch2 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram\\\\1: Force open the clock gate for LEDC ch2 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH2_R = crate::BitReader; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH2` writer - Configures whether or not to open LEDC ch2 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram\\\\1: Force open the clock gate for LEDC ch2 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH3` reader - Configures whether or not to open LEDC ch3 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram\\\\1: Force open the clock gate for LEDC ch3 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH3_R = crate::BitReader; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH3` writer - Configures whether or not to open LEDC ch3 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram\\\\1: Force open the clock gate for LEDC ch3 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH4` reader - Configures whether or not to open LEDC ch4 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram\\\\1: Force open the clock gate for LEDC ch4 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH4_R = crate::BitReader; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH4` writer - Configures whether or not to open LEDC ch4 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram\\\\1: Force open the clock gate for LEDC ch4 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH5` reader - Configures whether or not to open LEDC ch5 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram\\\\1: Force open the clock gate for LEDC ch5 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH5_R = crate::BitReader; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH5` writer - Configures whether or not to open LEDC ch5 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram\\\\1: Force open the clock gate for LEDC ch5 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH6` reader - Configures whether or not to open LEDC ch6 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram\\\\1: Force open the clock gate for LEDC ch6 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH6_R = crate::BitReader; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH6` writer - Configures whether or not to open LEDC ch6 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram\\\\1: Force open the clock gate for LEDC ch6 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH7` reader - Configures whether or not to open LEDC ch7 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram\\\\1: Force open the clock gate for LEDC ch7 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH7_R = crate::BitReader; +#[doc = "Field `GAMMA_RAM_CLK_EN_CH7` writer - Configures whether or not to open LEDC ch7 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram\\\\1: Force open the clock gate for LEDC ch7 gamma ram"] +pub type GAMMA_RAM_CLK_EN_CH7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Configures the clock source for the four timers.\\\\0: APB_CLK\\\\1: RC_FAST_CLK\\\\2: XTAL_CLK\\\\3: Invalid. No clock"] + #[inline(always)] + pub fn apb_clk_sel(&self) -> APB_CLK_SEL_R { + APB_CLK_SEL_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Configures whether or not to open LEDC ch0 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram\\\\1: Force open the clock gate for LEDC ch0 gamma ram"] + #[inline(always)] + pub fn gamma_ram_clk_en_ch0(&self) -> GAMMA_RAM_CLK_EN_CH0_R { + GAMMA_RAM_CLK_EN_CH0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures whether or not to open LEDC ch1 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram\\\\1: Force open the clock gate for LEDC ch1 gamma ram"] + #[inline(always)] + pub fn gamma_ram_clk_en_ch1(&self) -> GAMMA_RAM_CLK_EN_CH1_R { + GAMMA_RAM_CLK_EN_CH1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures whether or not to open LEDC ch2 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram\\\\1: Force open the clock gate for LEDC ch2 gamma ram"] + #[inline(always)] + pub fn gamma_ram_clk_en_ch2(&self) -> GAMMA_RAM_CLK_EN_CH2_R { + GAMMA_RAM_CLK_EN_CH2_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures whether or not to open LEDC ch3 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram\\\\1: Force open the clock gate for LEDC ch3 gamma ram"] + #[inline(always)] + pub fn gamma_ram_clk_en_ch3(&self) -> GAMMA_RAM_CLK_EN_CH3_R { + GAMMA_RAM_CLK_EN_CH3_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Configures whether or not to open LEDC ch4 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram\\\\1: Force open the clock gate for LEDC ch4 gamma ram"] + #[inline(always)] + pub fn gamma_ram_clk_en_ch4(&self) -> GAMMA_RAM_CLK_EN_CH4_R { + GAMMA_RAM_CLK_EN_CH4_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures whether or not to open LEDC ch5 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram\\\\1: Force open the clock gate for LEDC ch5 gamma ram"] + #[inline(always)] + pub fn gamma_ram_clk_en_ch5(&self) -> GAMMA_RAM_CLK_EN_CH5_R { + GAMMA_RAM_CLK_EN_CH5_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configures whether or not to open LEDC ch6 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram\\\\1: Force open the clock gate for LEDC ch6 gamma ram"] + #[inline(always)] + pub fn gamma_ram_clk_en_ch6(&self) -> GAMMA_RAM_CLK_EN_CH6_R { + GAMMA_RAM_CLK_EN_CH6_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures whether or not to open LEDC ch7 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram\\\\1: Force open the clock gate for LEDC ch7 gamma ram"] + #[inline(always)] + pub fn gamma_ram_clk_en_ch7(&self) -> GAMMA_RAM_CLK_EN_CH7_R { + GAMMA_RAM_CLK_EN_CH7_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 31 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF") + .field( + "apb_clk_sel", + &format_args!("{}", self.apb_clk_sel().bits()), + ) + .field( + "gamma_ram_clk_en_ch0", + &format_args!("{}", self.gamma_ram_clk_en_ch0().bit()), + ) + .field( + "gamma_ram_clk_en_ch1", + &format_args!("{}", self.gamma_ram_clk_en_ch1().bit()), + ) + .field( + "gamma_ram_clk_en_ch2", + &format_args!("{}", self.gamma_ram_clk_en_ch2().bit()), + ) + .field( + "gamma_ram_clk_en_ch3", + &format_args!("{}", self.gamma_ram_clk_en_ch3().bit()), + ) + .field( + "gamma_ram_clk_en_ch4", + &format_args!("{}", self.gamma_ram_clk_en_ch4().bit()), + ) + .field( + "gamma_ram_clk_en_ch5", + &format_args!("{}", self.gamma_ram_clk_en_ch5().bit()), + ) + .field( + "gamma_ram_clk_en_ch6", + &format_args!("{}", self.gamma_ram_clk_en_ch6().bit()), + ) + .field( + "gamma_ram_clk_en_ch7", + &format_args!("{}", self.gamma_ram_clk_en_ch7().bit()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Configures the clock source for the four timers.\\\\0: APB_CLK\\\\1: RC_FAST_CLK\\\\2: XTAL_CLK\\\\3: Invalid. No clock"] + #[inline(always)] + #[must_use] + pub fn apb_clk_sel(&mut self) -> APB_CLK_SEL_W { + APB_CLK_SEL_W::new(self, 0) + } + #[doc = "Bit 2 - Configures whether or not to open LEDC ch0 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram\\\\1: Force open the clock gate for LEDC ch0 gamma ram"] + #[inline(always)] + #[must_use] + pub fn gamma_ram_clk_en_ch0(&mut self) -> GAMMA_RAM_CLK_EN_CH0_W { + GAMMA_RAM_CLK_EN_CH0_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to open LEDC ch1 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram\\\\1: Force open the clock gate for LEDC ch1 gamma ram"] + #[inline(always)] + #[must_use] + pub fn gamma_ram_clk_en_ch1(&mut self) -> GAMMA_RAM_CLK_EN_CH1_W { + GAMMA_RAM_CLK_EN_CH1_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to open LEDC ch2 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram\\\\1: Force open the clock gate for LEDC ch2 gamma ram"] + #[inline(always)] + #[must_use] + pub fn gamma_ram_clk_en_ch2(&mut self) -> GAMMA_RAM_CLK_EN_CH2_W { + GAMMA_RAM_CLK_EN_CH2_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to open LEDC ch3 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram\\\\1: Force open the clock gate for LEDC ch3 gamma ram"] + #[inline(always)] + #[must_use] + pub fn gamma_ram_clk_en_ch3(&mut self) -> GAMMA_RAM_CLK_EN_CH3_W { + GAMMA_RAM_CLK_EN_CH3_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to open LEDC ch4 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram\\\\1: Force open the clock gate for LEDC ch4 gamma ram"] + #[inline(always)] + #[must_use] + pub fn gamma_ram_clk_en_ch4(&mut self) -> GAMMA_RAM_CLK_EN_CH4_W { + GAMMA_RAM_CLK_EN_CH4_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to open LEDC ch5 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram\\\\1: Force open the clock gate for LEDC ch5 gamma ram"] + #[inline(always)] + #[must_use] + pub fn gamma_ram_clk_en_ch5(&mut self) -> GAMMA_RAM_CLK_EN_CH5_W { + GAMMA_RAM_CLK_EN_CH5_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to open LEDC ch6 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram\\\\1: Force open the clock gate for LEDC ch6 gamma ram"] + #[inline(always)] + #[must_use] + pub fn gamma_ram_clk_en_ch6(&mut self) -> GAMMA_RAM_CLK_EN_CH6_W { + GAMMA_RAM_CLK_EN_CH6_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to open LEDC ch7 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram\\\\1: Force open the clock gate for LEDC ch7 gamma ram"] + #[inline(always)] + #[must_use] + pub fn gamma_ram_clk_en_ch7(&mut self) -> GAMMA_RAM_CLK_EN_CH7_W { + GAMMA_RAM_CLK_EN_CH7_W::new(self, 9) + } + #[doc = "Bit 31 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "LEDC global configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SPEC; +impl crate::RegisterSpec for CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf::R`](R) reader structure"] +impl crate::Readable for CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"] +impl crate::Writable for CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF to value 0"] +impl crate::Resettable for CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/date.rs b/esp32p4/src/ledc/date.rs new file mode 100644 index 0000000000..c7398d3718 --- /dev/null +++ b/esp32p4/src/ledc/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `LEDC_DATE` reader - Configures the version."] +pub type LEDC_DATE_R = crate::FieldReader; +#[doc = "Field `LEDC_DATE` writer - Configures the version."] +pub type LEDC_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Configures the version."] + #[inline(always)] + pub fn ledc_date(&self) -> LEDC_DATE_R { + LEDC_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("ledc_date", &format_args!("{}", self.ledc_date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Configures the version."] + #[inline(always)] + #[must_use] + pub fn ledc_date(&mut self) -> LEDC_DATE_W { + LEDC_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_3070"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_3070; +} diff --git a/esp32p4/src/ledc/evt_task_en0.rs b/esp32p4/src/ledc/evt_task_en0.rs new file mode 100644 index 0000000000..0e6fe29fd5 --- /dev/null +++ b/esp32p4/src/ledc/evt_task_en0.rs @@ -0,0 +1,671 @@ +#[doc = "Register `EVT_TASK_EN0` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_TASK_EN0` writer"] +pub type W = crate::W; +#[doc = "Field `EVT_DUTY_CHNG_END_CH0_EN` reader - Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH0_EN_R = crate::BitReader; +#[doc = "Field `EVT_DUTY_CHNG_END_CH0_EN` writer - Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_DUTY_CHNG_END_CH1_EN` reader - Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH1_EN_R = crate::BitReader; +#[doc = "Field `EVT_DUTY_CHNG_END_CH1_EN` writer - Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_DUTY_CHNG_END_CH2_EN` reader - Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH2_EN_R = crate::BitReader; +#[doc = "Field `EVT_DUTY_CHNG_END_CH2_EN` writer - Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_DUTY_CHNG_END_CH3_EN` reader - Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH3_EN_R = crate::BitReader; +#[doc = "Field `EVT_DUTY_CHNG_END_CH3_EN` writer - Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_DUTY_CHNG_END_CH4_EN` reader - Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH4_EN_R = crate::BitReader; +#[doc = "Field `EVT_DUTY_CHNG_END_CH4_EN` writer - Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_DUTY_CHNG_END_CH5_EN` reader - Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH5_EN_R = crate::BitReader; +#[doc = "Field `EVT_DUTY_CHNG_END_CH5_EN` writer - Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH5_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_DUTY_CHNG_END_CH6_EN` reader - Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH6_EN_R = crate::BitReader; +#[doc = "Field `EVT_DUTY_CHNG_END_CH6_EN` writer - Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH6_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_DUTY_CHNG_END_CH7_EN` reader - Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH7_EN_R = crate::BitReader; +#[doc = "Field `EVT_DUTY_CHNG_END_CH7_EN` writer - Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_DUTY_CHNG_END_CH7_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OVF_CNT_PLS_CH0_EN` reader - Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH0_EN_R = crate::BitReader; +#[doc = "Field `EVT_OVF_CNT_PLS_CH0_EN` writer - Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OVF_CNT_PLS_CH1_EN` reader - Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH1_EN_R = crate::BitReader; +#[doc = "Field `EVT_OVF_CNT_PLS_CH1_EN` writer - Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OVF_CNT_PLS_CH2_EN` reader - Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH2_EN_R = crate::BitReader; +#[doc = "Field `EVT_OVF_CNT_PLS_CH2_EN` writer - Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OVF_CNT_PLS_CH3_EN` reader - Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH3_EN_R = crate::BitReader; +#[doc = "Field `EVT_OVF_CNT_PLS_CH3_EN` writer - Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OVF_CNT_PLS_CH4_EN` reader - Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH4_EN_R = crate::BitReader; +#[doc = "Field `EVT_OVF_CNT_PLS_CH4_EN` writer - Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OVF_CNT_PLS_CH5_EN` reader - Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH5_EN_R = crate::BitReader; +#[doc = "Field `EVT_OVF_CNT_PLS_CH5_EN` writer - Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH5_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OVF_CNT_PLS_CH6_EN` reader - Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH6_EN_R = crate::BitReader; +#[doc = "Field `EVT_OVF_CNT_PLS_CH6_EN` writer - Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH6_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OVF_CNT_PLS_CH7_EN` reader - Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH7_EN_R = crate::BitReader; +#[doc = "Field `EVT_OVF_CNT_PLS_CH7_EN` writer - Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OVF_CNT_PLS_CH7_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIME_OVF_TIMER0_EN` reader - Configures whether or not to enable the ledc_timer0_ovf event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME_OVF_TIMER0_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIME_OVF_TIMER0_EN` writer - Configures whether or not to enable the ledc_timer0_ovf event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME_OVF_TIMER0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIME_OVF_TIMER1_EN` reader - Configures whether or not to enable the ledc_timer1_ovf event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME_OVF_TIMER1_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIME_OVF_TIMER1_EN` writer - Configures whether or not to enable the ledc_timer1_ovf event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME_OVF_TIMER1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIME_OVF_TIMER2_EN` reader - Configures whether or not to enable the ledc_timer2_ovf event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME_OVF_TIMER2_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIME_OVF_TIMER2_EN` writer - Configures whether or not to enable the ledc_timer2_ovf event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME_OVF_TIMER2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIME_OVF_TIMER3_EN` reader - Configures whether or not to enable the ledc_timer3_ovf event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME_OVF_TIMER3_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIME_OVF_TIMER3_EN` writer - Configures whether or not to enable the ledc_timer3_ovf event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME_OVF_TIMER3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIME0_CMP_EN` reader - Configures whether or not to enable the ledc_timer0_cmp event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME0_CMP_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIME0_CMP_EN` writer - Configures whether or not to enable the ledc_timer0_cmp event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME0_CMP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIME1_CMP_EN` reader - Configures whether or not to enable the ledc_timer1_cmp event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME1_CMP_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIME1_CMP_EN` writer - Configures whether or not to enable the ledc_timer1_cmp event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME1_CMP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIME2_CMP_EN` reader - Configures whether or not to enable the ledc_timer2_cmp event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME2_CMP_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIME2_CMP_EN` writer - Configures whether or not to enable the ledc_timer2_cmp event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME2_CMP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIME3_CMP_EN` reader - Configures whether or not to enable the ledc_timer3_cmp event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME3_CMP_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIME3_CMP_EN` writer - Configures whether or not to enable the ledc_timer3_cmp event.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIME3_CMP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH0_EN` reader - Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH0_EN_R = crate::BitReader; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH0_EN` writer - Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH1_EN` reader - Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH1_EN_R = crate::BitReader; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH1_EN` writer - Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH2_EN` reader - Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH2_EN_R = crate::BitReader; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH2_EN` writer - Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH3_EN` reader - Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH3_EN_R = crate::BitReader; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH3_EN` writer - Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH4_EN` reader - Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH4_EN_R = crate::BitReader; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH4_EN` writer - Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH5_EN` reader - Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH5_EN_R = crate::BitReader; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH5_EN` writer - Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH5_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH6_EN` reader - Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH6_EN_R = crate::BitReader; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH6_EN` writer - Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH6_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH7_EN` reader - Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH7_EN_R = crate::BitReader; +#[doc = "Field `TASK_DUTY_SCALE_UPDATE_CH7_EN` writer - Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_DUTY_SCALE_UPDATE_CH7_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_duty_chng_end_ch0_en(&self) -> EVT_DUTY_CHNG_END_CH0_EN_R { + EVT_DUTY_CHNG_END_CH0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_duty_chng_end_ch1_en(&self) -> EVT_DUTY_CHNG_END_CH1_EN_R { + EVT_DUTY_CHNG_END_CH1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_duty_chng_end_ch2_en(&self) -> EVT_DUTY_CHNG_END_CH2_EN_R { + EVT_DUTY_CHNG_END_CH2_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_duty_chng_end_ch3_en(&self) -> EVT_DUTY_CHNG_END_CH3_EN_R { + EVT_DUTY_CHNG_END_CH3_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_duty_chng_end_ch4_en(&self) -> EVT_DUTY_CHNG_END_CH4_EN_R { + EVT_DUTY_CHNG_END_CH4_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_duty_chng_end_ch5_en(&self) -> EVT_DUTY_CHNG_END_CH5_EN_R { + EVT_DUTY_CHNG_END_CH5_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_duty_chng_end_ch6_en(&self) -> EVT_DUTY_CHNG_END_CH6_EN_R { + EVT_DUTY_CHNG_END_CH6_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_duty_chng_end_ch7_en(&self) -> EVT_DUTY_CHNG_END_CH7_EN_R { + EVT_DUTY_CHNG_END_CH7_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_ovf_cnt_pls_ch0_en(&self) -> EVT_OVF_CNT_PLS_CH0_EN_R { + EVT_OVF_CNT_PLS_CH0_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_ovf_cnt_pls_ch1_en(&self) -> EVT_OVF_CNT_PLS_CH1_EN_R { + EVT_OVF_CNT_PLS_CH1_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_ovf_cnt_pls_ch2_en(&self) -> EVT_OVF_CNT_PLS_CH2_EN_R { + EVT_OVF_CNT_PLS_CH2_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_ovf_cnt_pls_ch3_en(&self) -> EVT_OVF_CNT_PLS_CH3_EN_R { + EVT_OVF_CNT_PLS_CH3_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_ovf_cnt_pls_ch4_en(&self) -> EVT_OVF_CNT_PLS_CH4_EN_R { + EVT_OVF_CNT_PLS_CH4_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_ovf_cnt_pls_ch5_en(&self) -> EVT_OVF_CNT_PLS_CH5_EN_R { + EVT_OVF_CNT_PLS_CH5_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_ovf_cnt_pls_ch6_en(&self) -> EVT_OVF_CNT_PLS_CH6_EN_R { + EVT_OVF_CNT_PLS_CH6_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_ovf_cnt_pls_ch7_en(&self) -> EVT_OVF_CNT_PLS_CH7_EN_R { + EVT_OVF_CNT_PLS_CH7_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Configures whether or not to enable the ledc_timer0_ovf event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_time_ovf_timer0_en(&self) -> EVT_TIME_OVF_TIMER0_EN_R { + EVT_TIME_OVF_TIMER0_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Configures whether or not to enable the ledc_timer1_ovf event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_time_ovf_timer1_en(&self) -> EVT_TIME_OVF_TIMER1_EN_R { + EVT_TIME_OVF_TIMER1_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Configures whether or not to enable the ledc_timer2_ovf event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_time_ovf_timer2_en(&self) -> EVT_TIME_OVF_TIMER2_EN_R { + EVT_TIME_OVF_TIMER2_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Configures whether or not to enable the ledc_timer3_ovf event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_time_ovf_timer3_en(&self) -> EVT_TIME_OVF_TIMER3_EN_R { + EVT_TIME_OVF_TIMER3_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Configures whether or not to enable the ledc_timer0_cmp event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_time0_cmp_en(&self) -> EVT_TIME0_CMP_EN_R { + EVT_TIME0_CMP_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Configures whether or not to enable the ledc_timer1_cmp event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_time1_cmp_en(&self) -> EVT_TIME1_CMP_EN_R { + EVT_TIME1_CMP_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Configures whether or not to enable the ledc_timer2_cmp event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_time2_cmp_en(&self) -> EVT_TIME2_CMP_EN_R { + EVT_TIME2_CMP_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Configures whether or not to enable the ledc_timer3_cmp event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_time3_cmp_en(&self) -> EVT_TIME3_CMP_EN_R { + EVT_TIME3_CMP_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_duty_scale_update_ch0_en(&self) -> TASK_DUTY_SCALE_UPDATE_CH0_EN_R { + TASK_DUTY_SCALE_UPDATE_CH0_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_duty_scale_update_ch1_en(&self) -> TASK_DUTY_SCALE_UPDATE_CH1_EN_R { + TASK_DUTY_SCALE_UPDATE_CH1_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_duty_scale_update_ch2_en(&self) -> TASK_DUTY_SCALE_UPDATE_CH2_EN_R { + TASK_DUTY_SCALE_UPDATE_CH2_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_duty_scale_update_ch3_en(&self) -> TASK_DUTY_SCALE_UPDATE_CH3_EN_R { + TASK_DUTY_SCALE_UPDATE_CH3_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_duty_scale_update_ch4_en(&self) -> TASK_DUTY_SCALE_UPDATE_CH4_EN_R { + TASK_DUTY_SCALE_UPDATE_CH4_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_duty_scale_update_ch5_en(&self) -> TASK_DUTY_SCALE_UPDATE_CH5_EN_R { + TASK_DUTY_SCALE_UPDATE_CH5_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_duty_scale_update_ch6_en(&self) -> TASK_DUTY_SCALE_UPDATE_CH6_EN_R { + TASK_DUTY_SCALE_UPDATE_CH6_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_duty_scale_update_ch7_en(&self) -> TASK_DUTY_SCALE_UPDATE_CH7_EN_R { + TASK_DUTY_SCALE_UPDATE_CH7_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_TASK_EN0") + .field( + "evt_duty_chng_end_ch0_en", + &format_args!("{}", self.evt_duty_chng_end_ch0_en().bit()), + ) + .field( + "evt_duty_chng_end_ch1_en", + &format_args!("{}", self.evt_duty_chng_end_ch1_en().bit()), + ) + .field( + "evt_duty_chng_end_ch2_en", + &format_args!("{}", self.evt_duty_chng_end_ch2_en().bit()), + ) + .field( + "evt_duty_chng_end_ch3_en", + &format_args!("{}", self.evt_duty_chng_end_ch3_en().bit()), + ) + .field( + "evt_duty_chng_end_ch4_en", + &format_args!("{}", self.evt_duty_chng_end_ch4_en().bit()), + ) + .field( + "evt_duty_chng_end_ch5_en", + &format_args!("{}", self.evt_duty_chng_end_ch5_en().bit()), + ) + .field( + "evt_duty_chng_end_ch6_en", + &format_args!("{}", self.evt_duty_chng_end_ch6_en().bit()), + ) + .field( + "evt_duty_chng_end_ch7_en", + &format_args!("{}", self.evt_duty_chng_end_ch7_en().bit()), + ) + .field( + "evt_ovf_cnt_pls_ch0_en", + &format_args!("{}", self.evt_ovf_cnt_pls_ch0_en().bit()), + ) + .field( + "evt_ovf_cnt_pls_ch1_en", + &format_args!("{}", self.evt_ovf_cnt_pls_ch1_en().bit()), + ) + .field( + "evt_ovf_cnt_pls_ch2_en", + &format_args!("{}", self.evt_ovf_cnt_pls_ch2_en().bit()), + ) + .field( + "evt_ovf_cnt_pls_ch3_en", + &format_args!("{}", self.evt_ovf_cnt_pls_ch3_en().bit()), + ) + .field( + "evt_ovf_cnt_pls_ch4_en", + &format_args!("{}", self.evt_ovf_cnt_pls_ch4_en().bit()), + ) + .field( + "evt_ovf_cnt_pls_ch5_en", + &format_args!("{}", self.evt_ovf_cnt_pls_ch5_en().bit()), + ) + .field( + "evt_ovf_cnt_pls_ch6_en", + &format_args!("{}", self.evt_ovf_cnt_pls_ch6_en().bit()), + ) + .field( + "evt_ovf_cnt_pls_ch7_en", + &format_args!("{}", self.evt_ovf_cnt_pls_ch7_en().bit()), + ) + .field( + "evt_time_ovf_timer0_en", + &format_args!("{}", self.evt_time_ovf_timer0_en().bit()), + ) + .field( + "evt_time_ovf_timer1_en", + &format_args!("{}", self.evt_time_ovf_timer1_en().bit()), + ) + .field( + "evt_time_ovf_timer2_en", + &format_args!("{}", self.evt_time_ovf_timer2_en().bit()), + ) + .field( + "evt_time_ovf_timer3_en", + &format_args!("{}", self.evt_time_ovf_timer3_en().bit()), + ) + .field( + "evt_time0_cmp_en", + &format_args!("{}", self.evt_time0_cmp_en().bit()), + ) + .field( + "evt_time1_cmp_en", + &format_args!("{}", self.evt_time1_cmp_en().bit()), + ) + .field( + "evt_time2_cmp_en", + &format_args!("{}", self.evt_time2_cmp_en().bit()), + ) + .field( + "evt_time3_cmp_en", + &format_args!("{}", self.evt_time3_cmp_en().bit()), + ) + .field( + "task_duty_scale_update_ch0_en", + &format_args!("{}", self.task_duty_scale_update_ch0_en().bit()), + ) + .field( + "task_duty_scale_update_ch1_en", + &format_args!("{}", self.task_duty_scale_update_ch1_en().bit()), + ) + .field( + "task_duty_scale_update_ch2_en", + &format_args!("{}", self.task_duty_scale_update_ch2_en().bit()), + ) + .field( + "task_duty_scale_update_ch3_en", + &format_args!("{}", self.task_duty_scale_update_ch3_en().bit()), + ) + .field( + "task_duty_scale_update_ch4_en", + &format_args!("{}", self.task_duty_scale_update_ch4_en().bit()), + ) + .field( + "task_duty_scale_update_ch5_en", + &format_args!("{}", self.task_duty_scale_update_ch5_en().bit()), + ) + .field( + "task_duty_scale_update_ch6_en", + &format_args!("{}", self.task_duty_scale_update_ch6_en().bit()), + ) + .field( + "task_duty_scale_update_ch7_en", + &format_args!("{}", self.task_duty_scale_update_ch7_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_duty_chng_end_ch0_en(&mut self) -> EVT_DUTY_CHNG_END_CH0_EN_W { + EVT_DUTY_CHNG_END_CH0_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_duty_chng_end_ch1_en(&mut self) -> EVT_DUTY_CHNG_END_CH1_EN_W { + EVT_DUTY_CHNG_END_CH1_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_duty_chng_end_ch2_en(&mut self) -> EVT_DUTY_CHNG_END_CH2_EN_W { + EVT_DUTY_CHNG_END_CH2_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_duty_chng_end_ch3_en(&mut self) -> EVT_DUTY_CHNG_END_CH3_EN_W { + EVT_DUTY_CHNG_END_CH3_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_duty_chng_end_ch4_en(&mut self) -> EVT_DUTY_CHNG_END_CH4_EN_W { + EVT_DUTY_CHNG_END_CH4_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_duty_chng_end_ch5_en(&mut self) -> EVT_DUTY_CHNG_END_CH5_EN_W { + EVT_DUTY_CHNG_END_CH5_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_duty_chng_end_ch6_en(&mut self) -> EVT_DUTY_CHNG_END_CH6_EN_W { + EVT_DUTY_CHNG_END_CH6_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_duty_chng_end_ch7_en(&mut self) -> EVT_DUTY_CHNG_END_CH7_EN_W { + EVT_DUTY_CHNG_END_CH7_EN_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_ovf_cnt_pls_ch0_en(&mut self) -> EVT_OVF_CNT_PLS_CH0_EN_W { + EVT_OVF_CNT_PLS_CH0_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_ovf_cnt_pls_ch1_en(&mut self) -> EVT_OVF_CNT_PLS_CH1_EN_W { + EVT_OVF_CNT_PLS_CH1_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_ovf_cnt_pls_ch2_en(&mut self) -> EVT_OVF_CNT_PLS_CH2_EN_W { + EVT_OVF_CNT_PLS_CH2_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_ovf_cnt_pls_ch3_en(&mut self) -> EVT_OVF_CNT_PLS_CH3_EN_W { + EVT_OVF_CNT_PLS_CH3_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_ovf_cnt_pls_ch4_en(&mut self) -> EVT_OVF_CNT_PLS_CH4_EN_W { + EVT_OVF_CNT_PLS_CH4_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_ovf_cnt_pls_ch5_en(&mut self) -> EVT_OVF_CNT_PLS_CH5_EN_W { + EVT_OVF_CNT_PLS_CH5_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_ovf_cnt_pls_ch6_en(&mut self) -> EVT_OVF_CNT_PLS_CH6_EN_W { + EVT_OVF_CNT_PLS_CH6_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_ovf_cnt_pls_ch7_en(&mut self) -> EVT_OVF_CNT_PLS_CH7_EN_W { + EVT_OVF_CNT_PLS_CH7_EN_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to enable the ledc_timer0_ovf event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_time_ovf_timer0_en(&mut self) -> EVT_TIME_OVF_TIMER0_EN_W { + EVT_TIME_OVF_TIMER0_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to enable the ledc_timer1_ovf event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_time_ovf_timer1_en(&mut self) -> EVT_TIME_OVF_TIMER1_EN_W { + EVT_TIME_OVF_TIMER1_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to enable the ledc_timer2_ovf event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_time_ovf_timer2_en(&mut self) -> EVT_TIME_OVF_TIMER2_EN_W { + EVT_TIME_OVF_TIMER2_EN_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to enable the ledc_timer3_ovf event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_time_ovf_timer3_en(&mut self) -> EVT_TIME_OVF_TIMER3_EN_W { + EVT_TIME_OVF_TIMER3_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to enable the ledc_timer0_cmp event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_time0_cmp_en(&mut self) -> EVT_TIME0_CMP_EN_W { + EVT_TIME0_CMP_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to enable the ledc_timer1_cmp event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_time1_cmp_en(&mut self) -> EVT_TIME1_CMP_EN_W { + EVT_TIME1_CMP_EN_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to enable the ledc_timer2_cmp event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_time2_cmp_en(&mut self) -> EVT_TIME2_CMP_EN_W { + EVT_TIME2_CMP_EN_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to enable the ledc_timer3_cmp event.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_time3_cmp_en(&mut self) -> EVT_TIME3_CMP_EN_W { + EVT_TIME3_CMP_EN_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_duty_scale_update_ch0_en( + &mut self, + ) -> TASK_DUTY_SCALE_UPDATE_CH0_EN_W { + TASK_DUTY_SCALE_UPDATE_CH0_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_duty_scale_update_ch1_en( + &mut self, + ) -> TASK_DUTY_SCALE_UPDATE_CH1_EN_W { + TASK_DUTY_SCALE_UPDATE_CH1_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_duty_scale_update_ch2_en( + &mut self, + ) -> TASK_DUTY_SCALE_UPDATE_CH2_EN_W { + TASK_DUTY_SCALE_UPDATE_CH2_EN_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_duty_scale_update_ch3_en( + &mut self, + ) -> TASK_DUTY_SCALE_UPDATE_CH3_EN_W { + TASK_DUTY_SCALE_UPDATE_CH3_EN_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_duty_scale_update_ch4_en( + &mut self, + ) -> TASK_DUTY_SCALE_UPDATE_CH4_EN_W { + TASK_DUTY_SCALE_UPDATE_CH4_EN_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_duty_scale_update_ch5_en( + &mut self, + ) -> TASK_DUTY_SCALE_UPDATE_CH5_EN_W { + TASK_DUTY_SCALE_UPDATE_CH5_EN_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_duty_scale_update_ch6_en( + &mut self, + ) -> TASK_DUTY_SCALE_UPDATE_CH6_EN_W { + TASK_DUTY_SCALE_UPDATE_CH6_EN_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_duty_scale_update_ch7_en( + &mut self, + ) -> TASK_DUTY_SCALE_UPDATE_CH7_EN_W { + TASK_DUTY_SCALE_UPDATE_CH7_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Ledc event task enable bit register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_task_en0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_task_en0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_TASK_EN0_SPEC; +impl crate::RegisterSpec for EVT_TASK_EN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_task_en0::R`](R) reader structure"] +impl crate::Readable for EVT_TASK_EN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_task_en0::W`](W) writer structure"] +impl crate::Writable for EVT_TASK_EN0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_TASK_EN0 to value 0"] +impl crate::Resettable for EVT_TASK_EN0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/evt_task_en1.rs b/esp32p4/src/ledc/evt_task_en1.rs new file mode 100644 index 0000000000..685152b128 --- /dev/null +++ b/esp32p4/src/ledc/evt_task_en1.rs @@ -0,0 +1,663 @@ +#[doc = "Register `EVT_TASK_EN1` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_TASK_EN1` writer"] +pub type W = crate::W; +#[doc = "Field `TASK_TIMER0_RES_UPDATE_EN` reader - Configures whether or not to enable ledc_timer0_res_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_RES_UPDATE_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER0_RES_UPDATE_EN` writer - Configures whether or not to enable ledc_timer0_res_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_RES_UPDATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER1_RES_UPDATE_EN` reader - Configures whether or not to enable ledc_timer1_res_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_RES_UPDATE_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER1_RES_UPDATE_EN` writer - Configures whether or not to enable ledc_timer1_res_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_RES_UPDATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER2_RES_UPDATE_EN` reader - Configures whether or not to enable ledc_timer2_res_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_RES_UPDATE_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER2_RES_UPDATE_EN` writer - Configures whether or not to enable ledc_timer2_res_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_RES_UPDATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER3_RES_UPDATE_EN` reader - Configures whether or not to enable ledc_timer3_res_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER3_RES_UPDATE_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER3_RES_UPDATE_EN` writer - Configures whether or not to enable ledc_timer3_res_update task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER3_RES_UPDATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER0_CAP_EN` reader - Configures whether or not to enable ledc_timer0_cap task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_CAP_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER0_CAP_EN` writer - Configures whether or not to enable ledc_timer0_cap task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_CAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER1_CAP_EN` reader - Configures whether or not to enable ledc_timer1_cap task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_CAP_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER1_CAP_EN` writer - Configures whether or not to enable ledc_timer1_cap task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_CAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER2_CAP_EN` reader - Configures whether or not to enable ledc_timer2_cap task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_CAP_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER2_CAP_EN` writer - Configures whether or not to enable ledc_timer2_cap task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_CAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER3_CAP_EN` reader - Configures whether or not to enable ledc_timer3_cap task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER3_CAP_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER3_CAP_EN` writer - Configures whether or not to enable ledc_timer3_cap task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER3_CAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_SIG_OUT_DIS_CH0_EN` reader - Configures whether or not to enable ledc_ch0_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH0_EN_R = crate::BitReader; +#[doc = "Field `TASK_SIG_OUT_DIS_CH0_EN` writer - Configures whether or not to enable ledc_ch0_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_SIG_OUT_DIS_CH1_EN` reader - Configures whether or not to enable ledc_ch1_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH1_EN_R = crate::BitReader; +#[doc = "Field `TASK_SIG_OUT_DIS_CH1_EN` writer - Configures whether or not to enable ledc_ch1_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_SIG_OUT_DIS_CH2_EN` reader - Configures whether or not to enable ledc_ch2_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH2_EN_R = crate::BitReader; +#[doc = "Field `TASK_SIG_OUT_DIS_CH2_EN` writer - Configures whether or not to enable ledc_ch2_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_SIG_OUT_DIS_CH3_EN` reader - Configures whether or not to enable ledc_ch3_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH3_EN_R = crate::BitReader; +#[doc = "Field `TASK_SIG_OUT_DIS_CH3_EN` writer - Configures whether or not to enable ledc_ch3_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_SIG_OUT_DIS_CH4_EN` reader - Configures whether or not to enable ledc_ch4_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH4_EN_R = crate::BitReader; +#[doc = "Field `TASK_SIG_OUT_DIS_CH4_EN` writer - Configures whether or not to enable ledc_ch4_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_SIG_OUT_DIS_CH5_EN` reader - Configures whether or not to enable ledc_ch5_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH5_EN_R = crate::BitReader; +#[doc = "Field `TASK_SIG_OUT_DIS_CH5_EN` writer - Configures whether or not to enable ledc_ch5_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH5_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_SIG_OUT_DIS_CH6_EN` reader - Configures whether or not to enable ledc_ch6_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH6_EN_R = crate::BitReader; +#[doc = "Field `TASK_SIG_OUT_DIS_CH6_EN` writer - Configures whether or not to enable ledc_ch6_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH6_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_SIG_OUT_DIS_CH7_EN` reader - Configures whether or not to enable ledc_ch7_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH7_EN_R = crate::BitReader; +#[doc = "Field `TASK_SIG_OUT_DIS_CH7_EN` writer - Configures whether or not to enable ledc_ch7_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_SIG_OUT_DIS_CH7_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_OVF_CNT_RST_CH0_EN` reader - Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH0_EN_R = crate::BitReader; +#[doc = "Field `TASK_OVF_CNT_RST_CH0_EN` writer - Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_OVF_CNT_RST_CH1_EN` reader - Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH1_EN_R = crate::BitReader; +#[doc = "Field `TASK_OVF_CNT_RST_CH1_EN` writer - Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_OVF_CNT_RST_CH2_EN` reader - Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH2_EN_R = crate::BitReader; +#[doc = "Field `TASK_OVF_CNT_RST_CH2_EN` writer - Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_OVF_CNT_RST_CH3_EN` reader - Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH3_EN_R = crate::BitReader; +#[doc = "Field `TASK_OVF_CNT_RST_CH3_EN` writer - Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_OVF_CNT_RST_CH4_EN` reader - Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH4_EN_R = crate::BitReader; +#[doc = "Field `TASK_OVF_CNT_RST_CH4_EN` writer - Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_OVF_CNT_RST_CH5_EN` reader - Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH5_EN_R = crate::BitReader; +#[doc = "Field `TASK_OVF_CNT_RST_CH5_EN` writer - Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH5_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_OVF_CNT_RST_CH6_EN` reader - Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH6_EN_R = crate::BitReader; +#[doc = "Field `TASK_OVF_CNT_RST_CH6_EN` writer - Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH6_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_OVF_CNT_RST_CH7_EN` reader - Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH7_EN_R = crate::BitReader; +#[doc = "Field `TASK_OVF_CNT_RST_CH7_EN` writer - Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_OVF_CNT_RST_CH7_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER0_RST_EN` reader - Configures whether or not to enable ledc_timer0_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_RST_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER0_RST_EN` writer - Configures whether or not to enable ledc_timer0_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER1_RST_EN` reader - Configures whether or not to enable ledc_timer1_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_RST_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER1_RST_EN` writer - Configures whether or not to enable ledc_timer1_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER2_RST_EN` reader - Configures whether or not to enable ledc_timer2_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_RST_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER2_RST_EN` writer - Configures whether or not to enable ledc_timer2_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER3_RST_EN` reader - Configures whether or not to enable ledc_timer3_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER3_RST_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER3_RST_EN` writer - Configures whether or not to enable ledc_timer3_rst task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER3_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER0_PAUSE_RESUME_EN` reader - Configures whether or not to enable ledc_timer0_pause_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_PAUSE_RESUME_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER0_PAUSE_RESUME_EN` writer - Configures whether or not to enable ledc_timer0_pause_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_PAUSE_RESUME_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER1_PAUSE_RESUME_EN` reader - Configures whether or not to enable ledc_timer1_pause_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_PAUSE_RESUME_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER1_PAUSE_RESUME_EN` writer - Configures whether or not to enable ledc_timer1_pause_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_PAUSE_RESUME_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER2_PAUSE_RESUME_EN` reader - Configures whether or not to enable ledc_timer2_pause_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_PAUSE_RESUME_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER2_PAUSE_RESUME_EN` writer - Configures whether or not to enable ledc_timer2_pause_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_PAUSE_RESUME_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER3_PAUSE_RESUME_EN` reader - Configures whether or not to enable ledc_timer3_pause_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER3_PAUSE_RESUME_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER3_PAUSE_RESUME_EN` writer - Configures whether or not to enable ledc_timer3_pause_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER3_PAUSE_RESUME_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable ledc_timer0_res_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer0_res_update_en(&self) -> TASK_TIMER0_RES_UPDATE_EN_R { + TASK_TIMER0_RES_UPDATE_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures whether or not to enable ledc_timer1_res_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer1_res_update_en(&self) -> TASK_TIMER1_RES_UPDATE_EN_R { + TASK_TIMER1_RES_UPDATE_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures whether or not to enable ledc_timer2_res_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer2_res_update_en(&self) -> TASK_TIMER2_RES_UPDATE_EN_R { + TASK_TIMER2_RES_UPDATE_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures whether or not to enable ledc_timer3_res_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer3_res_update_en(&self) -> TASK_TIMER3_RES_UPDATE_EN_R { + TASK_TIMER3_RES_UPDATE_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures whether or not to enable ledc_timer0_cap task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer0_cap_en(&self) -> TASK_TIMER0_CAP_EN_R { + TASK_TIMER0_CAP_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures whether or not to enable ledc_timer1_cap task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer1_cap_en(&self) -> TASK_TIMER1_CAP_EN_R { + TASK_TIMER1_CAP_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Configures whether or not to enable ledc_timer2_cap task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer2_cap_en(&self) -> TASK_TIMER2_CAP_EN_R { + TASK_TIMER2_CAP_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures whether or not to enable ledc_timer3_cap task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer3_cap_en(&self) -> TASK_TIMER3_CAP_EN_R { + TASK_TIMER3_CAP_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configures whether or not to enable ledc_ch0_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_sig_out_dis_ch0_en(&self) -> TASK_SIG_OUT_DIS_CH0_EN_R { + TASK_SIG_OUT_DIS_CH0_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures whether or not to enable ledc_ch1_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_sig_out_dis_ch1_en(&self) -> TASK_SIG_OUT_DIS_CH1_EN_R { + TASK_SIG_OUT_DIS_CH1_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Configures whether or not to enable ledc_ch2_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_sig_out_dis_ch2_en(&self) -> TASK_SIG_OUT_DIS_CH2_EN_R { + TASK_SIG_OUT_DIS_CH2_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Configures whether or not to enable ledc_ch3_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_sig_out_dis_ch3_en(&self) -> TASK_SIG_OUT_DIS_CH3_EN_R { + TASK_SIG_OUT_DIS_CH3_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Configures whether or not to enable ledc_ch4_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_sig_out_dis_ch4_en(&self) -> TASK_SIG_OUT_DIS_CH4_EN_R { + TASK_SIG_OUT_DIS_CH4_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures whether or not to enable ledc_ch5_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_sig_out_dis_ch5_en(&self) -> TASK_SIG_OUT_DIS_CH5_EN_R { + TASK_SIG_OUT_DIS_CH5_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Configures whether or not to enable ledc_ch6_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_sig_out_dis_ch6_en(&self) -> TASK_SIG_OUT_DIS_CH6_EN_R { + TASK_SIG_OUT_DIS_CH6_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Configures whether or not to enable ledc_ch7_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_sig_out_dis_ch7_en(&self) -> TASK_SIG_OUT_DIS_CH7_EN_R { + TASK_SIG_OUT_DIS_CH7_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_ovf_cnt_rst_ch0_en(&self) -> TASK_OVF_CNT_RST_CH0_EN_R { + TASK_OVF_CNT_RST_CH0_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_ovf_cnt_rst_ch1_en(&self) -> TASK_OVF_CNT_RST_CH1_EN_R { + TASK_OVF_CNT_RST_CH1_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_ovf_cnt_rst_ch2_en(&self) -> TASK_OVF_CNT_RST_CH2_EN_R { + TASK_OVF_CNT_RST_CH2_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_ovf_cnt_rst_ch3_en(&self) -> TASK_OVF_CNT_RST_CH3_EN_R { + TASK_OVF_CNT_RST_CH3_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_ovf_cnt_rst_ch4_en(&self) -> TASK_OVF_CNT_RST_CH4_EN_R { + TASK_OVF_CNT_RST_CH4_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_ovf_cnt_rst_ch5_en(&self) -> TASK_OVF_CNT_RST_CH5_EN_R { + TASK_OVF_CNT_RST_CH5_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_ovf_cnt_rst_ch6_en(&self) -> TASK_OVF_CNT_RST_CH6_EN_R { + TASK_OVF_CNT_RST_CH6_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_ovf_cnt_rst_ch7_en(&self) -> TASK_OVF_CNT_RST_CH7_EN_R { + TASK_OVF_CNT_RST_CH7_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Configures whether or not to enable ledc_timer0_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer0_rst_en(&self) -> TASK_TIMER0_RST_EN_R { + TASK_TIMER0_RST_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Configures whether or not to enable ledc_timer1_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer1_rst_en(&self) -> TASK_TIMER1_RST_EN_R { + TASK_TIMER1_RST_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Configures whether or not to enable ledc_timer2_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer2_rst_en(&self) -> TASK_TIMER2_RST_EN_R { + TASK_TIMER2_RST_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Configures whether or not to enable ledc_timer3_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer3_rst_en(&self) -> TASK_TIMER3_RST_EN_R { + TASK_TIMER3_RST_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Configures whether or not to enable ledc_timer0_pause_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer0_pause_resume_en(&self) -> TASK_TIMER0_PAUSE_RESUME_EN_R { + TASK_TIMER0_PAUSE_RESUME_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Configures whether or not to enable ledc_timer1_pause_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer1_pause_resume_en(&self) -> TASK_TIMER1_PAUSE_RESUME_EN_R { + TASK_TIMER1_PAUSE_RESUME_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Configures whether or not to enable ledc_timer2_pause_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer2_pause_resume_en(&self) -> TASK_TIMER2_PAUSE_RESUME_EN_R { + TASK_TIMER2_PAUSE_RESUME_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Configures whether or not to enable ledc_timer3_pause_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer3_pause_resume_en(&self) -> TASK_TIMER3_PAUSE_RESUME_EN_R { + TASK_TIMER3_PAUSE_RESUME_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_TASK_EN1") + .field( + "task_timer0_res_update_en", + &format_args!("{}", self.task_timer0_res_update_en().bit()), + ) + .field( + "task_timer1_res_update_en", + &format_args!("{}", self.task_timer1_res_update_en().bit()), + ) + .field( + "task_timer2_res_update_en", + &format_args!("{}", self.task_timer2_res_update_en().bit()), + ) + .field( + "task_timer3_res_update_en", + &format_args!("{}", self.task_timer3_res_update_en().bit()), + ) + .field( + "task_timer0_cap_en", + &format_args!("{}", self.task_timer0_cap_en().bit()), + ) + .field( + "task_timer1_cap_en", + &format_args!("{}", self.task_timer1_cap_en().bit()), + ) + .field( + "task_timer2_cap_en", + &format_args!("{}", self.task_timer2_cap_en().bit()), + ) + .field( + "task_timer3_cap_en", + &format_args!("{}", self.task_timer3_cap_en().bit()), + ) + .field( + "task_sig_out_dis_ch0_en", + &format_args!("{}", self.task_sig_out_dis_ch0_en().bit()), + ) + .field( + "task_sig_out_dis_ch1_en", + &format_args!("{}", self.task_sig_out_dis_ch1_en().bit()), + ) + .field( + "task_sig_out_dis_ch2_en", + &format_args!("{}", self.task_sig_out_dis_ch2_en().bit()), + ) + .field( + "task_sig_out_dis_ch3_en", + &format_args!("{}", self.task_sig_out_dis_ch3_en().bit()), + ) + .field( + "task_sig_out_dis_ch4_en", + &format_args!("{}", self.task_sig_out_dis_ch4_en().bit()), + ) + .field( + "task_sig_out_dis_ch5_en", + &format_args!("{}", self.task_sig_out_dis_ch5_en().bit()), + ) + .field( + "task_sig_out_dis_ch6_en", + &format_args!("{}", self.task_sig_out_dis_ch6_en().bit()), + ) + .field( + "task_sig_out_dis_ch7_en", + &format_args!("{}", self.task_sig_out_dis_ch7_en().bit()), + ) + .field( + "task_ovf_cnt_rst_ch0_en", + &format_args!("{}", self.task_ovf_cnt_rst_ch0_en().bit()), + ) + .field( + "task_ovf_cnt_rst_ch1_en", + &format_args!("{}", self.task_ovf_cnt_rst_ch1_en().bit()), + ) + .field( + "task_ovf_cnt_rst_ch2_en", + &format_args!("{}", self.task_ovf_cnt_rst_ch2_en().bit()), + ) + .field( + "task_ovf_cnt_rst_ch3_en", + &format_args!("{}", self.task_ovf_cnt_rst_ch3_en().bit()), + ) + .field( + "task_ovf_cnt_rst_ch4_en", + &format_args!("{}", self.task_ovf_cnt_rst_ch4_en().bit()), + ) + .field( + "task_ovf_cnt_rst_ch5_en", + &format_args!("{}", self.task_ovf_cnt_rst_ch5_en().bit()), + ) + .field( + "task_ovf_cnt_rst_ch6_en", + &format_args!("{}", self.task_ovf_cnt_rst_ch6_en().bit()), + ) + .field( + "task_ovf_cnt_rst_ch7_en", + &format_args!("{}", self.task_ovf_cnt_rst_ch7_en().bit()), + ) + .field( + "task_timer0_rst_en", + &format_args!("{}", self.task_timer0_rst_en().bit()), + ) + .field( + "task_timer1_rst_en", + &format_args!("{}", self.task_timer1_rst_en().bit()), + ) + .field( + "task_timer2_rst_en", + &format_args!("{}", self.task_timer2_rst_en().bit()), + ) + .field( + "task_timer3_rst_en", + &format_args!("{}", self.task_timer3_rst_en().bit()), + ) + .field( + "task_timer0_pause_resume_en", + &format_args!("{}", self.task_timer0_pause_resume_en().bit()), + ) + .field( + "task_timer1_pause_resume_en", + &format_args!("{}", self.task_timer1_pause_resume_en().bit()), + ) + .field( + "task_timer2_pause_resume_en", + &format_args!("{}", self.task_timer2_pause_resume_en().bit()), + ) + .field( + "task_timer3_pause_resume_en", + &format_args!("{}", self.task_timer3_pause_resume_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable ledc_timer0_res_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer0_res_update_en(&mut self) -> TASK_TIMER0_RES_UPDATE_EN_W { + TASK_TIMER0_RES_UPDATE_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to enable ledc_timer1_res_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer1_res_update_en(&mut self) -> TASK_TIMER1_RES_UPDATE_EN_W { + TASK_TIMER1_RES_UPDATE_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to enable ledc_timer2_res_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer2_res_update_en(&mut self) -> TASK_TIMER2_RES_UPDATE_EN_W { + TASK_TIMER2_RES_UPDATE_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to enable ledc_timer3_res_update task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer3_res_update_en(&mut self) -> TASK_TIMER3_RES_UPDATE_EN_W { + TASK_TIMER3_RES_UPDATE_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to enable ledc_timer0_cap task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer0_cap_en(&mut self) -> TASK_TIMER0_CAP_EN_W { + TASK_TIMER0_CAP_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to enable ledc_timer1_cap task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer1_cap_en(&mut self) -> TASK_TIMER1_CAP_EN_W { + TASK_TIMER1_CAP_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to enable ledc_timer2_cap task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer2_cap_en(&mut self) -> TASK_TIMER2_CAP_EN_W { + TASK_TIMER2_CAP_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to enable ledc_timer3_cap task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer3_cap_en(&mut self) -> TASK_TIMER3_CAP_EN_W { + TASK_TIMER3_CAP_EN_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to enable ledc_ch0_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_sig_out_dis_ch0_en(&mut self) -> TASK_SIG_OUT_DIS_CH0_EN_W { + TASK_SIG_OUT_DIS_CH0_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to enable ledc_ch1_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_sig_out_dis_ch1_en(&mut self) -> TASK_SIG_OUT_DIS_CH1_EN_W { + TASK_SIG_OUT_DIS_CH1_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to enable ledc_ch2_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_sig_out_dis_ch2_en(&mut self) -> TASK_SIG_OUT_DIS_CH2_EN_W { + TASK_SIG_OUT_DIS_CH2_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to enable ledc_ch3_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_sig_out_dis_ch3_en(&mut self) -> TASK_SIG_OUT_DIS_CH3_EN_W { + TASK_SIG_OUT_DIS_CH3_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to enable ledc_ch4_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_sig_out_dis_ch4_en(&mut self) -> TASK_SIG_OUT_DIS_CH4_EN_W { + TASK_SIG_OUT_DIS_CH4_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to enable ledc_ch5_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_sig_out_dis_ch5_en(&mut self) -> TASK_SIG_OUT_DIS_CH5_EN_W { + TASK_SIG_OUT_DIS_CH5_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to enable ledc_ch6_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_sig_out_dis_ch6_en(&mut self) -> TASK_SIG_OUT_DIS_CH6_EN_W { + TASK_SIG_OUT_DIS_CH6_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to enable ledc_ch7_sig_out_dis task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_sig_out_dis_ch7_en(&mut self) -> TASK_SIG_OUT_DIS_CH7_EN_W { + TASK_SIG_OUT_DIS_CH7_EN_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_ovf_cnt_rst_ch0_en(&mut self) -> TASK_OVF_CNT_RST_CH0_EN_W { + TASK_OVF_CNT_RST_CH0_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_ovf_cnt_rst_ch1_en(&mut self) -> TASK_OVF_CNT_RST_CH1_EN_W { + TASK_OVF_CNT_RST_CH1_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_ovf_cnt_rst_ch2_en(&mut self) -> TASK_OVF_CNT_RST_CH2_EN_W { + TASK_OVF_CNT_RST_CH2_EN_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_ovf_cnt_rst_ch3_en(&mut self) -> TASK_OVF_CNT_RST_CH3_EN_W { + TASK_OVF_CNT_RST_CH3_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_ovf_cnt_rst_ch4_en(&mut self) -> TASK_OVF_CNT_RST_CH4_EN_W { + TASK_OVF_CNT_RST_CH4_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_ovf_cnt_rst_ch5_en(&mut self) -> TASK_OVF_CNT_RST_CH5_EN_W { + TASK_OVF_CNT_RST_CH5_EN_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_ovf_cnt_rst_ch6_en(&mut self) -> TASK_OVF_CNT_RST_CH6_EN_W { + TASK_OVF_CNT_RST_CH6_EN_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_ovf_cnt_rst_ch7_en(&mut self) -> TASK_OVF_CNT_RST_CH7_EN_W { + TASK_OVF_CNT_RST_CH7_EN_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to enable ledc_timer0_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer0_rst_en(&mut self) -> TASK_TIMER0_RST_EN_W { + TASK_TIMER0_RST_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to enable ledc_timer1_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer1_rst_en(&mut self) -> TASK_TIMER1_RST_EN_W { + TASK_TIMER1_RST_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to enable ledc_timer2_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer2_rst_en(&mut self) -> TASK_TIMER2_RST_EN_W { + TASK_TIMER2_RST_EN_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to enable ledc_timer3_rst task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer3_rst_en(&mut self) -> TASK_TIMER3_RST_EN_W { + TASK_TIMER3_RST_EN_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to enable ledc_timer0_pause_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer0_pause_resume_en( + &mut self, + ) -> TASK_TIMER0_PAUSE_RESUME_EN_W { + TASK_TIMER0_PAUSE_RESUME_EN_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to enable ledc_timer1_pause_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer1_pause_resume_en( + &mut self, + ) -> TASK_TIMER1_PAUSE_RESUME_EN_W { + TASK_TIMER1_PAUSE_RESUME_EN_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to enable ledc_timer2_pause_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer2_pause_resume_en( + &mut self, + ) -> TASK_TIMER2_PAUSE_RESUME_EN_W { + TASK_TIMER2_PAUSE_RESUME_EN_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to enable ledc_timer3_pause_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer3_pause_resume_en( + &mut self, + ) -> TASK_TIMER3_PAUSE_RESUME_EN_W { + TASK_TIMER3_PAUSE_RESUME_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Ledc event task enable bit register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_task_en1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_task_en1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_TASK_EN1_SPEC; +impl crate::RegisterSpec for EVT_TASK_EN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_task_en1::R`](R) reader structure"] +impl crate::Readable for EVT_TASK_EN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_task_en1::W`](W) writer structure"] +impl crate::Writable for EVT_TASK_EN1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_TASK_EN1 to value 0"] +impl crate::Resettable for EVT_TASK_EN1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/evt_task_en2.rs b/esp32p4/src/ledc/evt_task_en2.rs new file mode 100644 index 0000000000..97fb9ca2c6 --- /dev/null +++ b/esp32p4/src/ledc/evt_task_en2.rs @@ -0,0 +1,503 @@ +#[doc = "Register `EVT_TASK_EN2` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_TASK_EN2` writer"] +pub type W = crate::W; +#[doc = "Field `TASK_GAMMA_RESTART_CH0_EN` reader - Configures whether or not to enable ledc_ch0_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH0_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESTART_CH0_EN` writer - Configures whether or not to enable ledc_ch0_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESTART_CH1_EN` reader - Configures whether or not to enable ledc_ch1_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH1_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESTART_CH1_EN` writer - Configures whether or not to enable ledc_ch1_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESTART_CH2_EN` reader - Configures whether or not to enable ledc_ch2_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH2_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESTART_CH2_EN` writer - Configures whether or not to enable ledc_ch2_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESTART_CH3_EN` reader - Configures whether or not to enable ledc_ch3_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH3_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESTART_CH3_EN` writer - Configures whether or not to enable ledc_ch3_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESTART_CH4_EN` reader - Configures whether or not to enable ledc_ch4_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH4_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESTART_CH4_EN` writer - Configures whether or not to enable ledc_ch4_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESTART_CH5_EN` reader - Configures whether or not to enable ledc_ch5_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH5_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESTART_CH5_EN` writer - Configures whether or not to enable ledc_ch5_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH5_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESTART_CH6_EN` reader - Configures whether or not to enable ledc_ch6_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH6_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESTART_CH6_EN` writer - Configures whether or not to enable ledc_ch6_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH6_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESTART_CH7_EN` reader - Configures whether or not to enable ledc_ch7_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH7_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESTART_CH7_EN` writer - Configures whether or not to enable ledc_ch7_gamma_restart task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESTART_CH7_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_PAUSE_CH0_EN` reader - Configures whether or not to enable ledc_ch0_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH0_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_PAUSE_CH0_EN` writer - Configures whether or not to enable ledc_ch0_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_PAUSE_CH1_EN` reader - Configures whether or not to enable ledc_ch1_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH1_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_PAUSE_CH1_EN` writer - Configures whether or not to enable ledc_ch1_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_PAUSE_CH2_EN` reader - Configures whether or not to enable ledc_ch2_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH2_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_PAUSE_CH2_EN` writer - Configures whether or not to enable ledc_ch2_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_PAUSE_CH3_EN` reader - Configures whether or not to enable ledc_ch3_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH3_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_PAUSE_CH3_EN` writer - Configures whether or not to enable ledc_ch3_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_PAUSE_CH4_EN` reader - Configures whether or not to enable ledc_ch4_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH4_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_PAUSE_CH4_EN` writer - Configures whether or not to enable ledc_ch4_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_PAUSE_CH5_EN` reader - Configures whether or not to enable ledc_ch5_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH5_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_PAUSE_CH5_EN` writer - Configures whether or not to enable ledc_ch5_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH5_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_PAUSE_CH6_EN` reader - Configures whether or not to enable ledc_ch6_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH6_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_PAUSE_CH6_EN` writer - Configures whether or not to enable ledc_ch6_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH6_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_PAUSE_CH7_EN` reader - Configures whether or not to enable ledc_ch7_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH7_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_PAUSE_CH7_EN` writer - Configures whether or not to enable ledc_ch7_gamma_pause task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_PAUSE_CH7_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESUME_CH0_EN` reader - Configures whether or not to enable ledc_ch0_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH0_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESUME_CH0_EN` writer - Configures whether or not to enable ledc_ch0_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESUME_CH1_EN` reader - Configures whether or not to enable ledc_ch1_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH1_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESUME_CH1_EN` writer - Configures whether or not to enable ledc_ch1_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESUME_CH2_EN` reader - Configures whether or not to enable ledc_ch2_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH2_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESUME_CH2_EN` writer - Configures whether or not to enable ledc_ch2_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESUME_CH3_EN` reader - Configures whether or not to enable ledc_ch3_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH3_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESUME_CH3_EN` writer - Configures whether or not to enable ledc_ch3_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH3_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESUME_CH4_EN` reader - Configures whether or not to enable ledc_ch4_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH4_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESUME_CH4_EN` writer - Configures whether or not to enable ledc_ch4_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH4_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESUME_CH5_EN` reader - Configures whether or not to enable ledc_ch5_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH5_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESUME_CH5_EN` writer - Configures whether or not to enable ledc_ch5_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH5_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESUME_CH6_EN` reader - Configures whether or not to enable ledc_ch6_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH6_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESUME_CH6_EN` writer - Configures whether or not to enable ledc_ch6_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH6_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GAMMA_RESUME_CH7_EN` reader - Configures whether or not to enable ledc_ch7_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH7_EN_R = crate::BitReader; +#[doc = "Field `TASK_GAMMA_RESUME_CH7_EN` writer - Configures whether or not to enable ledc_ch7_gamma_resume task.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GAMMA_RESUME_CH7_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable ledc_ch0_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_restart_ch0_en(&self) -> TASK_GAMMA_RESTART_CH0_EN_R { + TASK_GAMMA_RESTART_CH0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures whether or not to enable ledc_ch1_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_restart_ch1_en(&self) -> TASK_GAMMA_RESTART_CH1_EN_R { + TASK_GAMMA_RESTART_CH1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures whether or not to enable ledc_ch2_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_restart_ch2_en(&self) -> TASK_GAMMA_RESTART_CH2_EN_R { + TASK_GAMMA_RESTART_CH2_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures whether or not to enable ledc_ch3_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_restart_ch3_en(&self) -> TASK_GAMMA_RESTART_CH3_EN_R { + TASK_GAMMA_RESTART_CH3_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures whether or not to enable ledc_ch4_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_restart_ch4_en(&self) -> TASK_GAMMA_RESTART_CH4_EN_R { + TASK_GAMMA_RESTART_CH4_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures whether or not to enable ledc_ch5_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_restart_ch5_en(&self) -> TASK_GAMMA_RESTART_CH5_EN_R { + TASK_GAMMA_RESTART_CH5_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Configures whether or not to enable ledc_ch6_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_restart_ch6_en(&self) -> TASK_GAMMA_RESTART_CH6_EN_R { + TASK_GAMMA_RESTART_CH6_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures whether or not to enable ledc_ch7_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_restart_ch7_en(&self) -> TASK_GAMMA_RESTART_CH7_EN_R { + TASK_GAMMA_RESTART_CH7_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configures whether or not to enable ledc_ch0_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_pause_ch0_en(&self) -> TASK_GAMMA_PAUSE_CH0_EN_R { + TASK_GAMMA_PAUSE_CH0_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures whether or not to enable ledc_ch1_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_pause_ch1_en(&self) -> TASK_GAMMA_PAUSE_CH1_EN_R { + TASK_GAMMA_PAUSE_CH1_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Configures whether or not to enable ledc_ch2_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_pause_ch2_en(&self) -> TASK_GAMMA_PAUSE_CH2_EN_R { + TASK_GAMMA_PAUSE_CH2_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Configures whether or not to enable ledc_ch3_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_pause_ch3_en(&self) -> TASK_GAMMA_PAUSE_CH3_EN_R { + TASK_GAMMA_PAUSE_CH3_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Configures whether or not to enable ledc_ch4_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_pause_ch4_en(&self) -> TASK_GAMMA_PAUSE_CH4_EN_R { + TASK_GAMMA_PAUSE_CH4_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures whether or not to enable ledc_ch5_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_pause_ch5_en(&self) -> TASK_GAMMA_PAUSE_CH5_EN_R { + TASK_GAMMA_PAUSE_CH5_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Configures whether or not to enable ledc_ch6_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_pause_ch6_en(&self) -> TASK_GAMMA_PAUSE_CH6_EN_R { + TASK_GAMMA_PAUSE_CH6_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Configures whether or not to enable ledc_ch7_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_pause_ch7_en(&self) -> TASK_GAMMA_PAUSE_CH7_EN_R { + TASK_GAMMA_PAUSE_CH7_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Configures whether or not to enable ledc_ch0_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_resume_ch0_en(&self) -> TASK_GAMMA_RESUME_CH0_EN_R { + TASK_GAMMA_RESUME_CH0_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Configures whether or not to enable ledc_ch1_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_resume_ch1_en(&self) -> TASK_GAMMA_RESUME_CH1_EN_R { + TASK_GAMMA_RESUME_CH1_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Configures whether or not to enable ledc_ch2_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_resume_ch2_en(&self) -> TASK_GAMMA_RESUME_CH2_EN_R { + TASK_GAMMA_RESUME_CH2_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Configures whether or not to enable ledc_ch3_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_resume_ch3_en(&self) -> TASK_GAMMA_RESUME_CH3_EN_R { + TASK_GAMMA_RESUME_CH3_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Configures whether or not to enable ledc_ch4_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_resume_ch4_en(&self) -> TASK_GAMMA_RESUME_CH4_EN_R { + TASK_GAMMA_RESUME_CH4_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Configures whether or not to enable ledc_ch5_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_resume_ch5_en(&self) -> TASK_GAMMA_RESUME_CH5_EN_R { + TASK_GAMMA_RESUME_CH5_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Configures whether or not to enable ledc_ch6_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_resume_ch6_en(&self) -> TASK_GAMMA_RESUME_CH6_EN_R { + TASK_GAMMA_RESUME_CH6_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Configures whether or not to enable ledc_ch7_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gamma_resume_ch7_en(&self) -> TASK_GAMMA_RESUME_CH7_EN_R { + TASK_GAMMA_RESUME_CH7_EN_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_TASK_EN2") + .field( + "task_gamma_restart_ch0_en", + &format_args!("{}", self.task_gamma_restart_ch0_en().bit()), + ) + .field( + "task_gamma_restart_ch1_en", + &format_args!("{}", self.task_gamma_restart_ch1_en().bit()), + ) + .field( + "task_gamma_restart_ch2_en", + &format_args!("{}", self.task_gamma_restart_ch2_en().bit()), + ) + .field( + "task_gamma_restart_ch3_en", + &format_args!("{}", self.task_gamma_restart_ch3_en().bit()), + ) + .field( + "task_gamma_restart_ch4_en", + &format_args!("{}", self.task_gamma_restart_ch4_en().bit()), + ) + .field( + "task_gamma_restart_ch5_en", + &format_args!("{}", self.task_gamma_restart_ch5_en().bit()), + ) + .field( + "task_gamma_restart_ch6_en", + &format_args!("{}", self.task_gamma_restart_ch6_en().bit()), + ) + .field( + "task_gamma_restart_ch7_en", + &format_args!("{}", self.task_gamma_restart_ch7_en().bit()), + ) + .field( + "task_gamma_pause_ch0_en", + &format_args!("{}", self.task_gamma_pause_ch0_en().bit()), + ) + .field( + "task_gamma_pause_ch1_en", + &format_args!("{}", self.task_gamma_pause_ch1_en().bit()), + ) + .field( + "task_gamma_pause_ch2_en", + &format_args!("{}", self.task_gamma_pause_ch2_en().bit()), + ) + .field( + "task_gamma_pause_ch3_en", + &format_args!("{}", self.task_gamma_pause_ch3_en().bit()), + ) + .field( + "task_gamma_pause_ch4_en", + &format_args!("{}", self.task_gamma_pause_ch4_en().bit()), + ) + .field( + "task_gamma_pause_ch5_en", + &format_args!("{}", self.task_gamma_pause_ch5_en().bit()), + ) + .field( + "task_gamma_pause_ch6_en", + &format_args!("{}", self.task_gamma_pause_ch6_en().bit()), + ) + .field( + "task_gamma_pause_ch7_en", + &format_args!("{}", self.task_gamma_pause_ch7_en().bit()), + ) + .field( + "task_gamma_resume_ch0_en", + &format_args!("{}", self.task_gamma_resume_ch0_en().bit()), + ) + .field( + "task_gamma_resume_ch1_en", + &format_args!("{}", self.task_gamma_resume_ch1_en().bit()), + ) + .field( + "task_gamma_resume_ch2_en", + &format_args!("{}", self.task_gamma_resume_ch2_en().bit()), + ) + .field( + "task_gamma_resume_ch3_en", + &format_args!("{}", self.task_gamma_resume_ch3_en().bit()), + ) + .field( + "task_gamma_resume_ch4_en", + &format_args!("{}", self.task_gamma_resume_ch4_en().bit()), + ) + .field( + "task_gamma_resume_ch5_en", + &format_args!("{}", self.task_gamma_resume_ch5_en().bit()), + ) + .field( + "task_gamma_resume_ch6_en", + &format_args!("{}", self.task_gamma_resume_ch6_en().bit()), + ) + .field( + "task_gamma_resume_ch7_en", + &format_args!("{}", self.task_gamma_resume_ch7_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable ledc_ch0_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_restart_ch0_en(&mut self) -> TASK_GAMMA_RESTART_CH0_EN_W { + TASK_GAMMA_RESTART_CH0_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to enable ledc_ch1_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_restart_ch1_en(&mut self) -> TASK_GAMMA_RESTART_CH1_EN_W { + TASK_GAMMA_RESTART_CH1_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to enable ledc_ch2_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_restart_ch2_en(&mut self) -> TASK_GAMMA_RESTART_CH2_EN_W { + TASK_GAMMA_RESTART_CH2_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to enable ledc_ch3_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_restart_ch3_en(&mut self) -> TASK_GAMMA_RESTART_CH3_EN_W { + TASK_GAMMA_RESTART_CH3_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to enable ledc_ch4_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_restart_ch4_en(&mut self) -> TASK_GAMMA_RESTART_CH4_EN_W { + TASK_GAMMA_RESTART_CH4_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to enable ledc_ch5_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_restart_ch5_en(&mut self) -> TASK_GAMMA_RESTART_CH5_EN_W { + TASK_GAMMA_RESTART_CH5_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to enable ledc_ch6_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_restart_ch6_en(&mut self) -> TASK_GAMMA_RESTART_CH6_EN_W { + TASK_GAMMA_RESTART_CH6_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to enable ledc_ch7_gamma_restart task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_restart_ch7_en(&mut self) -> TASK_GAMMA_RESTART_CH7_EN_W { + TASK_GAMMA_RESTART_CH7_EN_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to enable ledc_ch0_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_pause_ch0_en(&mut self) -> TASK_GAMMA_PAUSE_CH0_EN_W { + TASK_GAMMA_PAUSE_CH0_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to enable ledc_ch1_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_pause_ch1_en(&mut self) -> TASK_GAMMA_PAUSE_CH1_EN_W { + TASK_GAMMA_PAUSE_CH1_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to enable ledc_ch2_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_pause_ch2_en(&mut self) -> TASK_GAMMA_PAUSE_CH2_EN_W { + TASK_GAMMA_PAUSE_CH2_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to enable ledc_ch3_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_pause_ch3_en(&mut self) -> TASK_GAMMA_PAUSE_CH3_EN_W { + TASK_GAMMA_PAUSE_CH3_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to enable ledc_ch4_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_pause_ch4_en(&mut self) -> TASK_GAMMA_PAUSE_CH4_EN_W { + TASK_GAMMA_PAUSE_CH4_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to enable ledc_ch5_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_pause_ch5_en(&mut self) -> TASK_GAMMA_PAUSE_CH5_EN_W { + TASK_GAMMA_PAUSE_CH5_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to enable ledc_ch6_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_pause_ch6_en(&mut self) -> TASK_GAMMA_PAUSE_CH6_EN_W { + TASK_GAMMA_PAUSE_CH6_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to enable ledc_ch7_gamma_pause task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_pause_ch7_en(&mut self) -> TASK_GAMMA_PAUSE_CH7_EN_W { + TASK_GAMMA_PAUSE_CH7_EN_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to enable ledc_ch0_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_resume_ch0_en(&mut self) -> TASK_GAMMA_RESUME_CH0_EN_W { + TASK_GAMMA_RESUME_CH0_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to enable ledc_ch1_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_resume_ch1_en(&mut self) -> TASK_GAMMA_RESUME_CH1_EN_W { + TASK_GAMMA_RESUME_CH1_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to enable ledc_ch2_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_resume_ch2_en(&mut self) -> TASK_GAMMA_RESUME_CH2_EN_W { + TASK_GAMMA_RESUME_CH2_EN_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to enable ledc_ch3_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_resume_ch3_en(&mut self) -> TASK_GAMMA_RESUME_CH3_EN_W { + TASK_GAMMA_RESUME_CH3_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to enable ledc_ch4_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_resume_ch4_en(&mut self) -> TASK_GAMMA_RESUME_CH4_EN_W { + TASK_GAMMA_RESUME_CH4_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to enable ledc_ch5_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_resume_ch5_en(&mut self) -> TASK_GAMMA_RESUME_CH5_EN_W { + TASK_GAMMA_RESUME_CH5_EN_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to enable ledc_ch6_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_resume_ch6_en(&mut self) -> TASK_GAMMA_RESUME_CH6_EN_W { + TASK_GAMMA_RESUME_CH6_EN_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to enable ledc_ch7_gamma_resume task.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gamma_resume_ch7_en(&mut self) -> TASK_GAMMA_RESUME_CH7_EN_W { + TASK_GAMMA_RESUME_CH7_EN_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Ledc event task enable bit register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_task_en2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_task_en2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_TASK_EN2_SPEC; +impl crate::RegisterSpec for EVT_TASK_EN2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_task_en2::R`](R) reader structure"] +impl crate::Readable for EVT_TASK_EN2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_task_en2::W`](W) writer structure"] +impl crate::Writable for EVT_TASK_EN2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_TASK_EN2 to value 0"] +impl crate::Resettable for EVT_TASK_EN2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/int_clr.rs b/esp32p4/src/ledc/int_clr.rs new file mode 100644 index 0000000000..be19534349 --- /dev/null +++ b/esp32p4/src/ledc/int_clr.rs @@ -0,0 +1,194 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER0_OVF_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT."] +pub type TIMER0_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_OVF_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT."] +pub type TIMER1_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_OVF_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT."] +pub type TIMER2_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER3_OVF_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT."] +pub type TIMER3_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH0_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT."] +pub type DUTY_CHNG_END_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH1_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT."] +pub type DUTY_CHNG_END_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH2_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT."] +pub type DUTY_CHNG_END_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH3_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT."] +pub type DUTY_CHNG_END_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH4_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT."] +pub type DUTY_CHNG_END_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH5_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT."] +pub type DUTY_CHNG_END_CH5_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH6_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT."] +pub type DUTY_CHNG_END_CH6_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH7_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT."] +pub type DUTY_CHNG_END_CH7_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH0_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT."] +pub type OVF_CNT_CH0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH1_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT."] +pub type OVF_CNT_CH1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH2_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT."] +pub type OVF_CNT_CH2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH3_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT."] +pub type OVF_CNT_CH3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH4_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT."] +pub type OVF_CNT_CH4_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH5_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT."] +pub type OVF_CNT_CH5_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH6_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT."] +pub type OVF_CNT_CH6_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH7_INT_CLR` writer - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT."] +pub type OVF_CNT_CH7_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT."] + #[inline(always)] + #[must_use] + pub fn timer0_ovf_int_clr(&mut self) -> TIMER0_OVF_INT_CLR_W { + TIMER0_OVF_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT."] + #[inline(always)] + #[must_use] + pub fn timer1_ovf_int_clr(&mut self) -> TIMER1_OVF_INT_CLR_W { + TIMER1_OVF_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT."] + #[inline(always)] + #[must_use] + pub fn timer2_ovf_int_clr(&mut self) -> TIMER2_OVF_INT_CLR_W { + TIMER2_OVF_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT."] + #[inline(always)] + #[must_use] + pub fn timer3_ovf_int_clr(&mut self) -> TIMER3_OVF_INT_CLR_W { + TIMER3_OVF_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch0_int_clr(&mut self) -> DUTY_CHNG_END_CH0_INT_CLR_W { + DUTY_CHNG_END_CH0_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch1_int_clr(&mut self) -> DUTY_CHNG_END_CH1_INT_CLR_W { + DUTY_CHNG_END_CH1_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch2_int_clr(&mut self) -> DUTY_CHNG_END_CH2_INT_CLR_W { + DUTY_CHNG_END_CH2_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch3_int_clr(&mut self) -> DUTY_CHNG_END_CH3_INT_CLR_W { + DUTY_CHNG_END_CH3_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch4_int_clr(&mut self) -> DUTY_CHNG_END_CH4_INT_CLR_W { + DUTY_CHNG_END_CH4_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch5_int_clr(&mut self) -> DUTY_CHNG_END_CH5_INT_CLR_W { + DUTY_CHNG_END_CH5_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch6_int_clr(&mut self) -> DUTY_CHNG_END_CH6_INT_CLR_W { + DUTY_CHNG_END_CH6_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch7_int_clr(&mut self) -> DUTY_CHNG_END_CH7_INT_CLR_W { + DUTY_CHNG_END_CH7_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch0_int_clr(&mut self) -> OVF_CNT_CH0_INT_CLR_W { + OVF_CNT_CH0_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch1_int_clr(&mut self) -> OVF_CNT_CH1_INT_CLR_W { + OVF_CNT_CH1_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch2_int_clr(&mut self) -> OVF_CNT_CH2_INT_CLR_W { + OVF_CNT_CH2_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch3_int_clr(&mut self) -> OVF_CNT_CH3_INT_CLR_W { + OVF_CNT_CH3_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch4_int_clr(&mut self) -> OVF_CNT_CH4_INT_CLR_W { + OVF_CNT_CH4_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch5_int_clr(&mut self) -> OVF_CNT_CH5_INT_CLR_W { + OVF_CNT_CH5_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch6_int_clr(&mut self) -> OVF_CNT_CH6_INT_CLR_W { + OVF_CNT_CH6_INT_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch7_int_clr(&mut self) -> OVF_CNT_CH7_INT_CLR_W { + OVF_CNT_CH7_INT_CLR_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/int_ena.rs b/esp32p4/src/ledc/int_ena.rs new file mode 100644 index 0000000000..ab2b1f9368 --- /dev/null +++ b/esp32p4/src/ledc/int_ena.rs @@ -0,0 +1,427 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER0_OVF_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT."] +pub type TIMER0_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER0_OVF_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT."] +pub type TIMER0_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_OVF_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT."] +pub type TIMER1_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER1_OVF_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT."] +pub type TIMER1_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_OVF_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT."] +pub type TIMER2_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER2_OVF_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT."] +pub type TIMER2_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER3_OVF_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT."] +pub type TIMER3_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER3_OVF_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT."] +pub type TIMER3_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH0_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT."] +pub type DUTY_CHNG_END_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH0_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT."] +pub type DUTY_CHNG_END_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH1_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT."] +pub type DUTY_CHNG_END_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH1_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT."] +pub type DUTY_CHNG_END_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH2_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT."] +pub type DUTY_CHNG_END_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH2_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT."] +pub type DUTY_CHNG_END_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH3_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT."] +pub type DUTY_CHNG_END_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH3_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT."] +pub type DUTY_CHNG_END_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH4_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT."] +pub type DUTY_CHNG_END_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH4_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT."] +pub type DUTY_CHNG_END_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH5_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT."] +pub type DUTY_CHNG_END_CH5_INT_ENA_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH5_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT."] +pub type DUTY_CHNG_END_CH5_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH6_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT."] +pub type DUTY_CHNG_END_CH6_INT_ENA_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH6_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT."] +pub type DUTY_CHNG_END_CH6_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH7_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT."] +pub type DUTY_CHNG_END_CH7_INT_ENA_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH7_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT."] +pub type DUTY_CHNG_END_CH7_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH0_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT."] +pub type OVF_CNT_CH0_INT_ENA_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH0_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT."] +pub type OVF_CNT_CH0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH1_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT."] +pub type OVF_CNT_CH1_INT_ENA_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH1_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT."] +pub type OVF_CNT_CH1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH2_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT."] +pub type OVF_CNT_CH2_INT_ENA_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH2_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT."] +pub type OVF_CNT_CH2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH3_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT."] +pub type OVF_CNT_CH3_INT_ENA_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH3_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT."] +pub type OVF_CNT_CH3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH4_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT."] +pub type OVF_CNT_CH4_INT_ENA_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH4_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT."] +pub type OVF_CNT_CH4_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH5_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT."] +pub type OVF_CNT_CH5_INT_ENA_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH5_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT."] +pub type OVF_CNT_CH5_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH6_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT."] +pub type OVF_CNT_CH6_INT_ENA_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH6_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT."] +pub type OVF_CNT_CH6_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH7_INT_ENA` reader - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT."] +pub type OVF_CNT_CH7_INT_ENA_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH7_INT_ENA` writer - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT."] +pub type OVF_CNT_CH7_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT."] + #[inline(always)] + pub fn timer0_ovf_int_ena(&self) -> TIMER0_OVF_INT_ENA_R { + TIMER0_OVF_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT."] + #[inline(always)] + pub fn timer1_ovf_int_ena(&self) -> TIMER1_OVF_INT_ENA_R { + TIMER1_OVF_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT."] + #[inline(always)] + pub fn timer2_ovf_int_ena(&self) -> TIMER2_OVF_INT_ENA_R { + TIMER2_OVF_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT."] + #[inline(always)] + pub fn timer3_ovf_int_ena(&self) -> TIMER3_OVF_INT_ENA_R { + TIMER3_OVF_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT."] + #[inline(always)] + pub fn duty_chng_end_ch0_int_ena(&self) -> DUTY_CHNG_END_CH0_INT_ENA_R { + DUTY_CHNG_END_CH0_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT."] + #[inline(always)] + pub fn duty_chng_end_ch1_int_ena(&self) -> DUTY_CHNG_END_CH1_INT_ENA_R { + DUTY_CHNG_END_CH1_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT."] + #[inline(always)] + pub fn duty_chng_end_ch2_int_ena(&self) -> DUTY_CHNG_END_CH2_INT_ENA_R { + DUTY_CHNG_END_CH2_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT."] + #[inline(always)] + pub fn duty_chng_end_ch3_int_ena(&self) -> DUTY_CHNG_END_CH3_INT_ENA_R { + DUTY_CHNG_END_CH3_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT."] + #[inline(always)] + pub fn duty_chng_end_ch4_int_ena(&self) -> DUTY_CHNG_END_CH4_INT_ENA_R { + DUTY_CHNG_END_CH4_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT."] + #[inline(always)] + pub fn duty_chng_end_ch5_int_ena(&self) -> DUTY_CHNG_END_CH5_INT_ENA_R { + DUTY_CHNG_END_CH5_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT."] + #[inline(always)] + pub fn duty_chng_end_ch6_int_ena(&self) -> DUTY_CHNG_END_CH6_INT_ENA_R { + DUTY_CHNG_END_CH6_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT."] + #[inline(always)] + pub fn duty_chng_end_ch7_int_ena(&self) -> DUTY_CHNG_END_CH7_INT_ENA_R { + DUTY_CHNG_END_CH7_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT."] + #[inline(always)] + pub fn ovf_cnt_ch0_int_ena(&self) -> OVF_CNT_CH0_INT_ENA_R { + OVF_CNT_CH0_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT."] + #[inline(always)] + pub fn ovf_cnt_ch1_int_ena(&self) -> OVF_CNT_CH1_INT_ENA_R { + OVF_CNT_CH1_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT."] + #[inline(always)] + pub fn ovf_cnt_ch2_int_ena(&self) -> OVF_CNT_CH2_INT_ENA_R { + OVF_CNT_CH2_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT."] + #[inline(always)] + pub fn ovf_cnt_ch3_int_ena(&self) -> OVF_CNT_CH3_INT_ENA_R { + OVF_CNT_CH3_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT."] + #[inline(always)] + pub fn ovf_cnt_ch4_int_ena(&self) -> OVF_CNT_CH4_INT_ENA_R { + OVF_CNT_CH4_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT."] + #[inline(always)] + pub fn ovf_cnt_ch5_int_ena(&self) -> OVF_CNT_CH5_INT_ENA_R { + OVF_CNT_CH5_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT."] + #[inline(always)] + pub fn ovf_cnt_ch6_int_ena(&self) -> OVF_CNT_CH6_INT_ENA_R { + OVF_CNT_CH6_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT."] + #[inline(always)] + pub fn ovf_cnt_ch7_int_ena(&self) -> OVF_CNT_CH7_INT_ENA_R { + OVF_CNT_CH7_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "timer0_ovf_int_ena", + &format_args!("{}", self.timer0_ovf_int_ena().bit()), + ) + .field( + "timer1_ovf_int_ena", + &format_args!("{}", self.timer1_ovf_int_ena().bit()), + ) + .field( + "timer2_ovf_int_ena", + &format_args!("{}", self.timer2_ovf_int_ena().bit()), + ) + .field( + "timer3_ovf_int_ena", + &format_args!("{}", self.timer3_ovf_int_ena().bit()), + ) + .field( + "duty_chng_end_ch0_int_ena", + &format_args!("{}", self.duty_chng_end_ch0_int_ena().bit()), + ) + .field( + "duty_chng_end_ch1_int_ena", + &format_args!("{}", self.duty_chng_end_ch1_int_ena().bit()), + ) + .field( + "duty_chng_end_ch2_int_ena", + &format_args!("{}", self.duty_chng_end_ch2_int_ena().bit()), + ) + .field( + "duty_chng_end_ch3_int_ena", + &format_args!("{}", self.duty_chng_end_ch3_int_ena().bit()), + ) + .field( + "duty_chng_end_ch4_int_ena", + &format_args!("{}", self.duty_chng_end_ch4_int_ena().bit()), + ) + .field( + "duty_chng_end_ch5_int_ena", + &format_args!("{}", self.duty_chng_end_ch5_int_ena().bit()), + ) + .field( + "duty_chng_end_ch6_int_ena", + &format_args!("{}", self.duty_chng_end_ch6_int_ena().bit()), + ) + .field( + "duty_chng_end_ch7_int_ena", + &format_args!("{}", self.duty_chng_end_ch7_int_ena().bit()), + ) + .field( + "ovf_cnt_ch0_int_ena", + &format_args!("{}", self.ovf_cnt_ch0_int_ena().bit()), + ) + .field( + "ovf_cnt_ch1_int_ena", + &format_args!("{}", self.ovf_cnt_ch1_int_ena().bit()), + ) + .field( + "ovf_cnt_ch2_int_ena", + &format_args!("{}", self.ovf_cnt_ch2_int_ena().bit()), + ) + .field( + "ovf_cnt_ch3_int_ena", + &format_args!("{}", self.ovf_cnt_ch3_int_ena().bit()), + ) + .field( + "ovf_cnt_ch4_int_ena", + &format_args!("{}", self.ovf_cnt_ch4_int_ena().bit()), + ) + .field( + "ovf_cnt_ch5_int_ena", + &format_args!("{}", self.ovf_cnt_ch5_int_ena().bit()), + ) + .field( + "ovf_cnt_ch6_int_ena", + &format_args!("{}", self.ovf_cnt_ch6_int_ena().bit()), + ) + .field( + "ovf_cnt_ch7_int_ena", + &format_args!("{}", self.ovf_cnt_ch7_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT."] + #[inline(always)] + #[must_use] + pub fn timer0_ovf_int_ena(&mut self) -> TIMER0_OVF_INT_ENA_W { + TIMER0_OVF_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT."] + #[inline(always)] + #[must_use] + pub fn timer1_ovf_int_ena(&mut self) -> TIMER1_OVF_INT_ENA_W { + TIMER1_OVF_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT."] + #[inline(always)] + #[must_use] + pub fn timer2_ovf_int_ena(&mut self) -> TIMER2_OVF_INT_ENA_W { + TIMER2_OVF_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT."] + #[inline(always)] + #[must_use] + pub fn timer3_ovf_int_ena(&mut self) -> TIMER3_OVF_INT_ENA_W { + TIMER3_OVF_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch0_int_ena(&mut self) -> DUTY_CHNG_END_CH0_INT_ENA_W { + DUTY_CHNG_END_CH0_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch1_int_ena(&mut self) -> DUTY_CHNG_END_CH1_INT_ENA_W { + DUTY_CHNG_END_CH1_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch2_int_ena(&mut self) -> DUTY_CHNG_END_CH2_INT_ENA_W { + DUTY_CHNG_END_CH2_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch3_int_ena(&mut self) -> DUTY_CHNG_END_CH3_INT_ENA_W { + DUTY_CHNG_END_CH3_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch4_int_ena(&mut self) -> DUTY_CHNG_END_CH4_INT_ENA_W { + DUTY_CHNG_END_CH4_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch5_int_ena(&mut self) -> DUTY_CHNG_END_CH5_INT_ENA_W { + DUTY_CHNG_END_CH5_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch6_int_ena(&mut self) -> DUTY_CHNG_END_CH6_INT_ENA_W { + DUTY_CHNG_END_CH6_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch7_int_ena(&mut self) -> DUTY_CHNG_END_CH7_INT_ENA_W { + DUTY_CHNG_END_CH7_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch0_int_ena(&mut self) -> OVF_CNT_CH0_INT_ENA_W { + OVF_CNT_CH0_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch1_int_ena(&mut self) -> OVF_CNT_CH1_INT_ENA_W { + OVF_CNT_CH1_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch2_int_ena(&mut self) -> OVF_CNT_CH2_INT_ENA_W { + OVF_CNT_CH2_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch3_int_ena(&mut self) -> OVF_CNT_CH3_INT_ENA_W { + OVF_CNT_CH3_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch4_int_ena(&mut self) -> OVF_CNT_CH4_INT_ENA_W { + OVF_CNT_CH4_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch5_int_ena(&mut self) -> OVF_CNT_CH5_INT_ENA_W { + OVF_CNT_CH5_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 18 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch6_int_ena(&mut self) -> OVF_CNT_CH6_INT_ENA_W { + OVF_CNT_CH6_INT_ENA_W::new(self, 18) + } + #[doc = "Bit 19 - Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch7_int_ena(&mut self) -> OVF_CNT_CH7_INT_ENA_W { + OVF_CNT_CH7_INT_ENA_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/int_raw.rs b/esp32p4/src/ledc/int_raw.rs new file mode 100644 index 0000000000..6d32303a1c --- /dev/null +++ b/esp32p4/src/ledc/int_raw.rs @@ -0,0 +1,427 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER0_OVF_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the timer0 has reached its maximum counter value."] +pub type TIMER0_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER0_OVF_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the timer0 has reached its maximum counter value."] +pub type TIMER0_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_OVF_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the timer1 has reached its maximum counter value."] +pub type TIMER1_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER1_OVF_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the timer1 has reached its maximum counter value."] +pub type TIMER1_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_OVF_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the timer2 has reached its maximum counter value."] +pub type TIMER2_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER2_OVF_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the timer2 has reached its maximum counter value."] +pub type TIMER2_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER3_OVF_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the timer3 has reached its maximum counter value."] +pub type TIMER3_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER3_OVF_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the timer3 has reached its maximum counter value."] +pub type TIMER3_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH0_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH0_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH1_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH1_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH2_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH2_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH3_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH3_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH4_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH4_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH5_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH5_INT_RAW_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH5_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH5_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH6_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH6_INT_RAW_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH6_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH6_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DUTY_CHNG_END_CH7_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH7_INT_RAW_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH7_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered when the fading of duty has finished."] +pub type DUTY_CHNG_END_CH7_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH0_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0."] +pub type OVF_CNT_CH0_INT_RAW_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH0_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0."] +pub type OVF_CNT_CH0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH1_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1."] +pub type OVF_CNT_CH1_INT_RAW_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH1_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1."] +pub type OVF_CNT_CH1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH2_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2."] +pub type OVF_CNT_CH2_INT_RAW_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH2_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2."] +pub type OVF_CNT_CH2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH3_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3."] +pub type OVF_CNT_CH3_INT_RAW_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH3_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3."] +pub type OVF_CNT_CH3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH4_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4."] +pub type OVF_CNT_CH4_INT_RAW_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH4_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4."] +pub type OVF_CNT_CH4_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH5_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5."] +pub type OVF_CNT_CH5_INT_RAW_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH5_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5."] +pub type OVF_CNT_CH5_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH6_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6."] +pub type OVF_CNT_CH6_INT_RAW_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH6_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6."] +pub type OVF_CNT_CH6_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVF_CNT_CH7_INT_RAW` reader - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7."] +pub type OVF_CNT_CH7_INT_RAW_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH7_INT_RAW` writer - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7."] +pub type OVF_CNT_CH7_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the timer0 has reached its maximum counter value."] + #[inline(always)] + pub fn timer0_ovf_int_raw(&self) -> TIMER0_OVF_INT_RAW_R { + TIMER0_OVF_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the timer1 has reached its maximum counter value."] + #[inline(always)] + pub fn timer1_ovf_int_raw(&self) -> TIMER1_OVF_INT_RAW_R { + TIMER1_OVF_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the timer2 has reached its maximum counter value."] + #[inline(always)] + pub fn timer2_ovf_int_raw(&self) -> TIMER2_OVF_INT_RAW_R { + TIMER2_OVF_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the timer3 has reached its maximum counter value."] + #[inline(always)] + pub fn timer3_ovf_int_raw(&self) -> TIMER3_OVF_INT_RAW_R { + TIMER3_OVF_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + pub fn duty_chng_end_ch0_int_raw(&self) -> DUTY_CHNG_END_CH0_INT_RAW_R { + DUTY_CHNG_END_CH0_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + pub fn duty_chng_end_ch1_int_raw(&self) -> DUTY_CHNG_END_CH1_INT_RAW_R { + DUTY_CHNG_END_CH1_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + pub fn duty_chng_end_ch2_int_raw(&self) -> DUTY_CHNG_END_CH2_INT_RAW_R { + DUTY_CHNG_END_CH2_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + pub fn duty_chng_end_ch3_int_raw(&self) -> DUTY_CHNG_END_CH3_INT_RAW_R { + DUTY_CHNG_END_CH3_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + pub fn duty_chng_end_ch4_int_raw(&self) -> DUTY_CHNG_END_CH4_INT_RAW_R { + DUTY_CHNG_END_CH4_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + pub fn duty_chng_end_ch5_int_raw(&self) -> DUTY_CHNG_END_CH5_INT_RAW_R { + DUTY_CHNG_END_CH5_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + pub fn duty_chng_end_ch6_int_raw(&self) -> DUTY_CHNG_END_CH6_INT_RAW_R { + DUTY_CHNG_END_CH6_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + pub fn duty_chng_end_ch7_int_raw(&self) -> DUTY_CHNG_END_CH7_INT_RAW_R { + DUTY_CHNG_END_CH7_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0."] + #[inline(always)] + pub fn ovf_cnt_ch0_int_raw(&self) -> OVF_CNT_CH0_INT_RAW_R { + OVF_CNT_CH0_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1."] + #[inline(always)] + pub fn ovf_cnt_ch1_int_raw(&self) -> OVF_CNT_CH1_INT_RAW_R { + OVF_CNT_CH1_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2."] + #[inline(always)] + pub fn ovf_cnt_ch2_int_raw(&self) -> OVF_CNT_CH2_INT_RAW_R { + OVF_CNT_CH2_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3."] + #[inline(always)] + pub fn ovf_cnt_ch3_int_raw(&self) -> OVF_CNT_CH3_INT_RAW_R { + OVF_CNT_CH3_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4."] + #[inline(always)] + pub fn ovf_cnt_ch4_int_raw(&self) -> OVF_CNT_CH4_INT_RAW_R { + OVF_CNT_CH4_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5."] + #[inline(always)] + pub fn ovf_cnt_ch5_int_raw(&self) -> OVF_CNT_CH5_INT_RAW_R { + OVF_CNT_CH5_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6."] + #[inline(always)] + pub fn ovf_cnt_ch6_int_raw(&self) -> OVF_CNT_CH6_INT_RAW_R { + OVF_CNT_CH6_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7."] + #[inline(always)] + pub fn ovf_cnt_ch7_int_raw(&self) -> OVF_CNT_CH7_INT_RAW_R { + OVF_CNT_CH7_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "timer0_ovf_int_raw", + &format_args!("{}", self.timer0_ovf_int_raw().bit()), + ) + .field( + "timer1_ovf_int_raw", + &format_args!("{}", self.timer1_ovf_int_raw().bit()), + ) + .field( + "timer2_ovf_int_raw", + &format_args!("{}", self.timer2_ovf_int_raw().bit()), + ) + .field( + "timer3_ovf_int_raw", + &format_args!("{}", self.timer3_ovf_int_raw().bit()), + ) + .field( + "duty_chng_end_ch0_int_raw", + &format_args!("{}", self.duty_chng_end_ch0_int_raw().bit()), + ) + .field( + "duty_chng_end_ch1_int_raw", + &format_args!("{}", self.duty_chng_end_ch1_int_raw().bit()), + ) + .field( + "duty_chng_end_ch2_int_raw", + &format_args!("{}", self.duty_chng_end_ch2_int_raw().bit()), + ) + .field( + "duty_chng_end_ch3_int_raw", + &format_args!("{}", self.duty_chng_end_ch3_int_raw().bit()), + ) + .field( + "duty_chng_end_ch4_int_raw", + &format_args!("{}", self.duty_chng_end_ch4_int_raw().bit()), + ) + .field( + "duty_chng_end_ch5_int_raw", + &format_args!("{}", self.duty_chng_end_ch5_int_raw().bit()), + ) + .field( + "duty_chng_end_ch6_int_raw", + &format_args!("{}", self.duty_chng_end_ch6_int_raw().bit()), + ) + .field( + "duty_chng_end_ch7_int_raw", + &format_args!("{}", self.duty_chng_end_ch7_int_raw().bit()), + ) + .field( + "ovf_cnt_ch0_int_raw", + &format_args!("{}", self.ovf_cnt_ch0_int_raw().bit()), + ) + .field( + "ovf_cnt_ch1_int_raw", + &format_args!("{}", self.ovf_cnt_ch1_int_raw().bit()), + ) + .field( + "ovf_cnt_ch2_int_raw", + &format_args!("{}", self.ovf_cnt_ch2_int_raw().bit()), + ) + .field( + "ovf_cnt_ch3_int_raw", + &format_args!("{}", self.ovf_cnt_ch3_int_raw().bit()), + ) + .field( + "ovf_cnt_ch4_int_raw", + &format_args!("{}", self.ovf_cnt_ch4_int_raw().bit()), + ) + .field( + "ovf_cnt_ch5_int_raw", + &format_args!("{}", self.ovf_cnt_ch5_int_raw().bit()), + ) + .field( + "ovf_cnt_ch6_int_raw", + &format_args!("{}", self.ovf_cnt_ch6_int_raw().bit()), + ) + .field( + "ovf_cnt_ch7_int_raw", + &format_args!("{}", self.ovf_cnt_ch7_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the timer0 has reached its maximum counter value."] + #[inline(always)] + #[must_use] + pub fn timer0_ovf_int_raw(&mut self) -> TIMER0_OVF_INT_RAW_W { + TIMER0_OVF_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the timer1 has reached its maximum counter value."] + #[inline(always)] + #[must_use] + pub fn timer1_ovf_int_raw(&mut self) -> TIMER1_OVF_INT_RAW_W { + TIMER1_OVF_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the timer2 has reached its maximum counter value."] + #[inline(always)] + #[must_use] + pub fn timer2_ovf_int_raw(&mut self) -> TIMER2_OVF_INT_RAW_W { + TIMER2_OVF_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the timer3 has reached its maximum counter value."] + #[inline(always)] + #[must_use] + pub fn timer3_ovf_int_raw(&mut self) -> TIMER3_OVF_INT_RAW_W { + TIMER3_OVF_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch0_int_raw(&mut self) -> DUTY_CHNG_END_CH0_INT_RAW_W { + DUTY_CHNG_END_CH0_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch1_int_raw(&mut self) -> DUTY_CHNG_END_CH1_INT_RAW_W { + DUTY_CHNG_END_CH1_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch2_int_raw(&mut self) -> DUTY_CHNG_END_CH2_INT_RAW_W { + DUTY_CHNG_END_CH2_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch3_int_raw(&mut self) -> DUTY_CHNG_END_CH3_INT_RAW_W { + DUTY_CHNG_END_CH3_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch4_int_raw(&mut self) -> DUTY_CHNG_END_CH4_INT_RAW_W { + DUTY_CHNG_END_CH4_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch5_int_raw(&mut self) -> DUTY_CHNG_END_CH5_INT_RAW_W { + DUTY_CHNG_END_CH5_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch6_int_raw(&mut self) -> DUTY_CHNG_END_CH6_INT_RAW_W { + DUTY_CHNG_END_CH6_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered when the fading of duty has finished."] + #[inline(always)] + #[must_use] + pub fn duty_chng_end_ch7_int_raw(&mut self) -> DUTY_CHNG_END_CH7_INT_RAW_W { + DUTY_CHNG_END_CH7_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 12 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch0_int_raw(&mut self) -> OVF_CNT_CH0_INT_RAW_W { + OVF_CNT_CH0_INT_RAW_W::new(self, 12) + } + #[doc = "Bit 13 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch1_int_raw(&mut self) -> OVF_CNT_CH1_INT_RAW_W { + OVF_CNT_CH1_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 14 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch2_int_raw(&mut self) -> OVF_CNT_CH2_INT_RAW_W { + OVF_CNT_CH2_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch3_int_raw(&mut self) -> OVF_CNT_CH3_INT_RAW_W { + OVF_CNT_CH3_INT_RAW_W::new(self, 15) + } + #[doc = "Bit 16 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch4_int_raw(&mut self) -> OVF_CNT_CH4_INT_RAW_W { + OVF_CNT_CH4_INT_RAW_W::new(self, 16) + } + #[doc = "Bit 17 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch5_int_raw(&mut self) -> OVF_CNT_CH5_INT_RAW_W { + OVF_CNT_CH5_INT_RAW_W::new(self, 17) + } + #[doc = "Bit 18 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch6_int_raw(&mut self) -> OVF_CNT_CH6_INT_RAW_W { + OVF_CNT_CH6_INT_RAW_W::new(self, 18) + } + #[doc = "Bit 19 - Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7."] + #[inline(always)] + #[must_use] + pub fn ovf_cnt_ch7_int_raw(&mut self) -> OVF_CNT_CH7_INT_RAW_W { + OVF_CNT_CH7_INT_RAW_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/int_st.rs b/esp32p4/src/ledc/int_st.rs new file mode 100644 index 0000000000..984a146bdc --- /dev/null +++ b/esp32p4/src/ledc/int_st.rs @@ -0,0 +1,248 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `TIMER0_OVF_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only when LEDC_TIMER0_OVF_INT_ENA is set to 1."] +pub type TIMER0_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMER1_OVF_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only when LEDC_TIMER1_OVF_INT_ENA is set to 1."] +pub type TIMER1_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMER2_OVF_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only when LEDC_TIMER2_OVF_INT_ENA is set to 1."] +pub type TIMER2_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMER3_OVF_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only when LEDC_TIMER3_OVF_INT_ENA is set to 1."] +pub type TIMER3_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH0_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1."] +pub type DUTY_CHNG_END_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH1_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1."] +pub type DUTY_CHNG_END_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH2_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1."] +pub type DUTY_CHNG_END_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH3_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1."] +pub type DUTY_CHNG_END_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH4_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1."] +pub type DUTY_CHNG_END_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH5_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1."] +pub type DUTY_CHNG_END_CH5_INT_ST_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH6_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1."] +pub type DUTY_CHNG_END_CH6_INT_ST_R = crate::BitReader; +#[doc = "Field `DUTY_CHNG_END_CH7_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1."] +pub type DUTY_CHNG_END_CH7_INT_ST_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH0_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only when LEDC_OVF_CNT_CH0_INT_ENA is set to 1."] +pub type OVF_CNT_CH0_INT_ST_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH1_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only when LEDC_OVF_CNT_CH1_INT_ENA is set to 1."] +pub type OVF_CNT_CH1_INT_ST_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH2_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only when LEDC_OVF_CNT_CH2_INT_ENA is set to 1."] +pub type OVF_CNT_CH2_INT_ST_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH3_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only when LEDC_OVF_CNT_CH3_INT_ENA is set to 1."] +pub type OVF_CNT_CH3_INT_ST_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH4_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only when LEDC_OVF_CNT_CH4_INT_ENA is set to 1."] +pub type OVF_CNT_CH4_INT_ST_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH5_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only when LEDC_OVF_CNT_CH5_INT_ENA is set to 1."] +pub type OVF_CNT_CH5_INT_ST_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH6_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only when LEDC_OVF_CNT_CH6_INT_ENA is set to 1."] +pub type OVF_CNT_CH6_INT_ST_R = crate::BitReader; +#[doc = "Field `OVF_CNT_CH7_INT_ST` reader - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only when LEDC_OVF_CNT_CH7_INT_ENA is set to 1."] +pub type OVF_CNT_CH7_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only when LEDC_TIMER0_OVF_INT_ENA is set to 1."] + #[inline(always)] + pub fn timer0_ovf_int_st(&self) -> TIMER0_OVF_INT_ST_R { + TIMER0_OVF_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only when LEDC_TIMER1_OVF_INT_ENA is set to 1."] + #[inline(always)] + pub fn timer1_ovf_int_st(&self) -> TIMER1_OVF_INT_ST_R { + TIMER1_OVF_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only when LEDC_TIMER2_OVF_INT_ENA is set to 1."] + #[inline(always)] + pub fn timer2_ovf_int_st(&self) -> TIMER2_OVF_INT_ST_R { + TIMER2_OVF_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only when LEDC_TIMER3_OVF_INT_ENA is set to 1."] + #[inline(always)] + pub fn timer3_ovf_int_st(&self) -> TIMER3_OVF_INT_ST_R { + TIMER3_OVF_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1."] + #[inline(always)] + pub fn duty_chng_end_ch0_int_st(&self) -> DUTY_CHNG_END_CH0_INT_ST_R { + DUTY_CHNG_END_CH0_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1."] + #[inline(always)] + pub fn duty_chng_end_ch1_int_st(&self) -> DUTY_CHNG_END_CH1_INT_ST_R { + DUTY_CHNG_END_CH1_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1."] + #[inline(always)] + pub fn duty_chng_end_ch2_int_st(&self) -> DUTY_CHNG_END_CH2_INT_ST_R { + DUTY_CHNG_END_CH2_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1."] + #[inline(always)] + pub fn duty_chng_end_ch3_int_st(&self) -> DUTY_CHNG_END_CH3_INT_ST_R { + DUTY_CHNG_END_CH3_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1."] + #[inline(always)] + pub fn duty_chng_end_ch4_int_st(&self) -> DUTY_CHNG_END_CH4_INT_ST_R { + DUTY_CHNG_END_CH4_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1."] + #[inline(always)] + pub fn duty_chng_end_ch5_int_st(&self) -> DUTY_CHNG_END_CH5_INT_ST_R { + DUTY_CHNG_END_CH5_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1."] + #[inline(always)] + pub fn duty_chng_end_ch6_int_st(&self) -> DUTY_CHNG_END_CH6_INT_ST_R { + DUTY_CHNG_END_CH6_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1."] + #[inline(always)] + pub fn duty_chng_end_ch7_int_st(&self) -> DUTY_CHNG_END_CH7_INT_ST_R { + DUTY_CHNG_END_CH7_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only when LEDC_OVF_CNT_CH0_INT_ENA is set to 1."] + #[inline(always)] + pub fn ovf_cnt_ch0_int_st(&self) -> OVF_CNT_CH0_INT_ST_R { + OVF_CNT_CH0_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only when LEDC_OVF_CNT_CH1_INT_ENA is set to 1."] + #[inline(always)] + pub fn ovf_cnt_ch1_int_st(&self) -> OVF_CNT_CH1_INT_ST_R { + OVF_CNT_CH1_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only when LEDC_OVF_CNT_CH2_INT_ENA is set to 1."] + #[inline(always)] + pub fn ovf_cnt_ch2_int_st(&self) -> OVF_CNT_CH2_INT_ST_R { + OVF_CNT_CH2_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only when LEDC_OVF_CNT_CH3_INT_ENA is set to 1."] + #[inline(always)] + pub fn ovf_cnt_ch3_int_st(&self) -> OVF_CNT_CH3_INT_ST_R { + OVF_CNT_CH3_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only when LEDC_OVF_CNT_CH4_INT_ENA is set to 1."] + #[inline(always)] + pub fn ovf_cnt_ch4_int_st(&self) -> OVF_CNT_CH4_INT_ST_R { + OVF_CNT_CH4_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only when LEDC_OVF_CNT_CH5_INT_ENA is set to 1."] + #[inline(always)] + pub fn ovf_cnt_ch5_int_st(&self) -> OVF_CNT_CH5_INT_ST_R { + OVF_CNT_CH5_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only when LEDC_OVF_CNT_CH6_INT_ENA is set to 1."] + #[inline(always)] + pub fn ovf_cnt_ch6_int_st(&self) -> OVF_CNT_CH6_INT_ST_R { + OVF_CNT_CH6_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only when LEDC_OVF_CNT_CH7_INT_ENA is set to 1."] + #[inline(always)] + pub fn ovf_cnt_ch7_int_st(&self) -> OVF_CNT_CH7_INT_ST_R { + OVF_CNT_CH7_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "timer0_ovf_int_st", + &format_args!("{}", self.timer0_ovf_int_st().bit()), + ) + .field( + "timer1_ovf_int_st", + &format_args!("{}", self.timer1_ovf_int_st().bit()), + ) + .field( + "timer2_ovf_int_st", + &format_args!("{}", self.timer2_ovf_int_st().bit()), + ) + .field( + "timer3_ovf_int_st", + &format_args!("{}", self.timer3_ovf_int_st().bit()), + ) + .field( + "duty_chng_end_ch0_int_st", + &format_args!("{}", self.duty_chng_end_ch0_int_st().bit()), + ) + .field( + "duty_chng_end_ch1_int_st", + &format_args!("{}", self.duty_chng_end_ch1_int_st().bit()), + ) + .field( + "duty_chng_end_ch2_int_st", + &format_args!("{}", self.duty_chng_end_ch2_int_st().bit()), + ) + .field( + "duty_chng_end_ch3_int_st", + &format_args!("{}", self.duty_chng_end_ch3_int_st().bit()), + ) + .field( + "duty_chng_end_ch4_int_st", + &format_args!("{}", self.duty_chng_end_ch4_int_st().bit()), + ) + .field( + "duty_chng_end_ch5_int_st", + &format_args!("{}", self.duty_chng_end_ch5_int_st().bit()), + ) + .field( + "duty_chng_end_ch6_int_st", + &format_args!("{}", self.duty_chng_end_ch6_int_st().bit()), + ) + .field( + "duty_chng_end_ch7_int_st", + &format_args!("{}", self.duty_chng_end_ch7_int_st().bit()), + ) + .field( + "ovf_cnt_ch0_int_st", + &format_args!("{}", self.ovf_cnt_ch0_int_st().bit()), + ) + .field( + "ovf_cnt_ch1_int_st", + &format_args!("{}", self.ovf_cnt_ch1_int_st().bit()), + ) + .field( + "ovf_cnt_ch2_int_st", + &format_args!("{}", self.ovf_cnt_ch2_int_st().bit()), + ) + .field( + "ovf_cnt_ch3_int_st", + &format_args!("{}", self.ovf_cnt_ch3_int_st().bit()), + ) + .field( + "ovf_cnt_ch4_int_st", + &format_args!("{}", self.ovf_cnt_ch4_int_st().bit()), + ) + .field( + "ovf_cnt_ch5_int_st", + &format_args!("{}", self.ovf_cnt_ch5_int_st().bit()), + ) + .field( + "ovf_cnt_ch6_int_st", + &format_args!("{}", self.ovf_cnt_ch6_int_st().bit()), + ) + .field( + "ovf_cnt_ch7_int_st", + &format_args!("{}", self.ovf_cnt_ch7_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Interrupt masked status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/timer_cmp.rs b/esp32p4/src/ledc/timer_cmp.rs new file mode 100644 index 0000000000..e5e8955dc9 --- /dev/null +++ b/esp32p4/src/ledc/timer_cmp.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TIMER%s_CMP` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER%s_CMP` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_CMP` reader - Configures the comparison value for LEDC timer%s."] +pub type TIMER_CMP_R = crate::FieldReader; +#[doc = "Field `TIMER_CMP` writer - Configures the comparison value for LEDC timer%s."] +pub type TIMER_CMP_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - Configures the comparison value for LEDC timer%s."] + #[inline(always)] + pub fn timer_cmp(&self) -> TIMER_CMP_R { + TIMER_CMP_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER_CMP") + .field("timer_cmp", &format_args!("{}", self.timer_cmp().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - Configures the comparison value for LEDC timer%s."] + #[inline(always)] + #[must_use] + pub fn timer_cmp(&mut self) -> TIMER_CMP_W { + TIMER_CMP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Ledc timer%s compare value register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_cmp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_cmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER_CMP_SPEC; +impl crate::RegisterSpec for TIMER_CMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer_cmp::R`](R) reader structure"] +impl crate::Readable for TIMER_CMP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer_cmp::W`](W) writer structure"] +impl crate::Writable for TIMER_CMP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMER%s_CMP to value 0"] +impl crate::Resettable for TIMER_CMP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/timer_cnt_cap.rs b/esp32p4/src/ledc/timer_cnt_cap.rs new file mode 100644 index 0000000000..c9d225dfd7 --- /dev/null +++ b/esp32p4/src/ledc/timer_cnt_cap.rs @@ -0,0 +1,39 @@ +#[doc = "Register `TIMER%s_CNT_CAP` reader"] +pub type R = crate::R; +#[doc = "Field `TIMER_CNT_CAP` reader - Represents the captured LEDC timer%s count value."] +pub type TIMER_CNT_CAP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - Represents the captured LEDC timer%s count value."] + #[inline(always)] + pub fn timer_cnt_cap(&self) -> TIMER_CNT_CAP_R { + TIMER_CNT_CAP_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER_CNT_CAP") + .field( + "timer_cnt_cap", + &format_args!("{}", self.timer_cnt_cap().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Ledc timer%s captured count value register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_cnt_cap::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER_CNT_CAP_SPEC; +impl crate::RegisterSpec for TIMER_CNT_CAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer_cnt_cap::R`](R) reader structure"] +impl crate::Readable for TIMER_CNT_CAP_SPEC {} +#[doc = "`reset()` method sets TIMER%s_CNT_CAP to value 0"] +impl crate::Resettable for TIMER_CNT_CAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ledc/timer_conf.rs b/esp32p4/src/ledc/timer_conf.rs new file mode 100644 index 0000000000..89cebd4ddd --- /dev/null +++ b/esp32p4/src/ledc/timer_conf.rs @@ -0,0 +1,144 @@ +#[doc = "Register `TIMER%s_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER%s_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_DUTY_RES` reader - Configures the range of the counter in timer %s."] +pub type TIMER_DUTY_RES_R = crate::FieldReader; +#[doc = "Field `TIMER_DUTY_RES` writer - Configures the range of the counter in timer %s."] +pub type TIMER_DUTY_RES_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `CLK_DIV_TIMER` reader - Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part."] +pub type CLK_DIV_TIMER_R = crate::FieldReader; +#[doc = "Field `CLK_DIV_TIMER` writer - Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part."] +pub type CLK_DIV_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `TIMER_PAUSE` reader - Configures whether or not to pause the counter in timer %s.\\\\0: Normal\\\\1: Pause"] +pub type TIMER_PAUSE_R = crate::BitReader; +#[doc = "Field `TIMER_PAUSE` writer - Configures whether or not to pause the counter in timer %s.\\\\0: Normal\\\\1: Pause"] +pub type TIMER_PAUSE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_RST` reader - Configures whether or not to reset timer %s. The counter will show 0 after reset.\\\\0: Not reset\\\\1: Reset"] +pub type TIMER_RST_R = crate::BitReader; +#[doc = "Field `TIMER_RST` writer - Configures whether or not to reset timer %s. The counter will show 0 after reset.\\\\0: Not reset\\\\1: Reset"] +pub type TIMER_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TICK_SEL_TIMER` reader - Configures which clock is timer %s selected. Unused."] +pub type TICK_SEL_TIMER_R = crate::BitReader; +#[doc = "Field `TICK_SEL_TIMER` writer - Configures which clock is timer %s selected. Unused."] +pub type TICK_SEL_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_PARA_UP` writer - Configures whether or not to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.\\\\0: Invalid. No effect\\\\1: Update"] +pub type TIMER_PARA_UP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Configures the range of the counter in timer %s."] + #[inline(always)] + pub fn timer_duty_res(&self) -> TIMER_DUTY_RES_R { + TIMER_DUTY_RES_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:22 - Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part."] + #[inline(always)] + pub fn clk_div_timer(&self) -> CLK_DIV_TIMER_R { + CLK_DIV_TIMER_R::new((self.bits >> 5) & 0x0003_ffff) + } + #[doc = "Bit 23 - Configures whether or not to pause the counter in timer %s.\\\\0: Normal\\\\1: Pause"] + #[inline(always)] + pub fn timer_pause(&self) -> TIMER_PAUSE_R { + TIMER_PAUSE_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Configures whether or not to reset timer %s. The counter will show 0 after reset.\\\\0: Not reset\\\\1: Reset"] + #[inline(always)] + pub fn timer_rst(&self) -> TIMER_RST_R { + TIMER_RST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Configures which clock is timer %s selected. Unused."] + #[inline(always)] + pub fn tick_sel_timer(&self) -> TICK_SEL_TIMER_R { + TICK_SEL_TIMER_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER_CONF") + .field( + "timer_duty_res", + &format_args!("{}", self.timer_duty_res().bits()), + ) + .field( + "clk_div_timer", + &format_args!("{}", self.clk_div_timer().bits()), + ) + .field("timer_pause", &format_args!("{}", self.timer_pause().bit())) + .field("timer_rst", &format_args!("{}", self.timer_rst().bit())) + .field( + "tick_sel_timer", + &format_args!("{}", self.tick_sel_timer().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - Configures the range of the counter in timer %s."] + #[inline(always)] + #[must_use] + pub fn timer_duty_res(&mut self) -> TIMER_DUTY_RES_W { + TIMER_DUTY_RES_W::new(self, 0) + } + #[doc = "Bits 5:22 - Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part."] + #[inline(always)] + #[must_use] + pub fn clk_div_timer(&mut self) -> CLK_DIV_TIMER_W { + CLK_DIV_TIMER_W::new(self, 5) + } + #[doc = "Bit 23 - Configures whether or not to pause the counter in timer %s.\\\\0: Normal\\\\1: Pause"] + #[inline(always)] + #[must_use] + pub fn timer_pause(&mut self) -> TIMER_PAUSE_W { + TIMER_PAUSE_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to reset timer %s. The counter will show 0 after reset.\\\\0: Not reset\\\\1: Reset"] + #[inline(always)] + #[must_use] + pub fn timer_rst(&mut self) -> TIMER_RST_W { + TIMER_RST_W::new(self, 24) + } + #[doc = "Bit 25 - Configures which clock is timer %s selected. Unused."] + #[inline(always)] + #[must_use] + pub fn tick_sel_timer(&mut self) -> TICK_SEL_TIMER_W { + TICK_SEL_TIMER_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.\\\\0: Invalid. No effect\\\\1: Update"] + #[inline(always)] + #[must_use] + pub fn timer_para_up(&mut self) -> TIMER_PARA_UP_W { + TIMER_PARA_UP_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timer %s configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER_CONF_SPEC; +impl crate::RegisterSpec for TIMER_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer_conf::R`](R) reader structure"] +impl crate::Readable for TIMER_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer_conf::W`](W) writer structure"] +impl crate::Writable for TIMER_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMER%s_CONF to value 0x0100_0000"] +impl crate::Resettable for TIMER_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0100_0000; +} diff --git a/esp32p4/src/ledc/timer_value.rs b/esp32p4/src/ledc/timer_value.rs new file mode 100644 index 0000000000..61a0e6f302 --- /dev/null +++ b/esp32p4/src/ledc/timer_value.rs @@ -0,0 +1,36 @@ +#[doc = "Register `TIMER%s_VALUE` reader"] +pub type R = crate::R; +#[doc = "Field `TIMER_CNT` reader - Represents the current counter value of timer %s."] +pub type TIMER_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - Represents the current counter value of timer %s."] + #[inline(always)] + pub fn timer_cnt(&self) -> TIMER_CNT_R { + TIMER_CNT_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER_VALUE") + .field("timer_cnt", &format_args!("{}", self.timer_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Timer %s current counter value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_value::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER_VALUE_SPEC; +impl crate::RegisterSpec for TIMER_VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer_value::R`](R) reader structure"] +impl crate::Readable for TIMER_VALUE_SPEC {} +#[doc = "`reset()` method sets TIMER%s_VALUE to value 0"] +impl crate::Resettable for TIMER_VALUE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lib.rs b/esp32p4/src/lib.rs new file mode 100644 index 0000000000..e23a9be842 --- /dev/null +++ b/esp32p4/src/lib.rs @@ -0,0 +1,4606 @@ +#![doc = "Peripheral access API for ESP32-P4 microcontrollers (generated using svd2rust v0.31.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.31.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 0; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn LP_WDT(); + fn LP_TIMER0(); + fn LP_TIMER1(); + fn PMU0(); + fn PMU1(); + fn LP_ANA(); + fn LP_ADC(); + fn LP_GPIO(); + fn LP_I2C0(); + fn LP_I2S0(); + fn LP_TOUCH(); + fn LP_TSENS(); + fn LP_UART(); + fn LP_SYS(); + fn LP_HUK(); + fn USB_DEVICE(); + fn DMA(); + fn SPI2(); + fn SPI3(); + fn I2S0(); + fn I2S1(); + fn I2S2(); + fn UHCI0(); + fn UART0(); + fn PWM0(); + fn PWM1(); + fn TWAI0(); + fn TWAI1(); + fn TWAI2(); + fn RMT(); + fn I2C0(); + fn I2C1(); + fn TG0_T0(); + fn TG0_T1(); + fn TG0_WDT(); + fn TG1_T0(); + fn TG1_T1(); + fn TG1_WDT(); + fn LEDC(); + fn SYSTIMER_TARGET0(); + fn SYSTIMER_TARGET1(); + fn SYSTIMER_TARGET2(); + fn RSA(); + fn AES(); + fn SHA(); + fn ECC(); + fn GPIO_INT0(); + fn GPIO_INT1(); + fn GPIO_INT2(); + fn GPIO_INT3(); + fn GPIO_PAD_COMP(); + fn CACHE(); + fn CSI_BRIDGE(); + fn DSI_BRIDGE(); + fn CSI(); + fn DSI(); + fn JPEG(); + fn PPA(); + fn ISP(); + fn I3C(); + fn I3C_SLV(); + fn HP_SYS(); + fn PCNT(); + fn PAU(); + fn PARLIO_RX(); + fn PARLIO_TX(); + fn H264_DMA2D_OUT_CH0(); + fn H264_DMA2D_OUT_CH1(); + fn H264_DMA2D_OUT_CH2(); + fn H264_DMA2D_OUT_CH3(); + fn H264_DMA2D_OUT_CH4(); + fn H264_DMA2D_IN_CH0(); + fn H264_DMA2D_IN_CH1(); + fn H264_DMA2D_IN_CH2(); + fn H264_DMA2D_IN_CH3(); + fn H264_DMA2D_IN_CH4(); + fn H264_DMA2D_IN_CH5(); + fn H264_REG(); + fn ASSIST_DEBUG(); +} +#[doc(hidden)] +#[repr(C)] +pub union Vector { + pub _handler: unsafe extern "C" fn(), + pub _reserved: usize, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".trap.rodata"] +#[no_mangle] +pub static __EXTERNAL_INTERRUPTS: [Vector; 128] = [ + Vector { _reserved: 0 }, + Vector { _handler: LP_WDT }, + Vector { + _handler: LP_TIMER0, + }, + Vector { + _handler: LP_TIMER1, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: PMU0 }, + Vector { _handler: PMU1 }, + Vector { _handler: LP_ANA }, + Vector { _handler: LP_ADC }, + Vector { _handler: LP_GPIO }, + Vector { _handler: LP_I2C0 }, + Vector { _handler: LP_I2S0 }, + Vector { _reserved: 0 }, + Vector { _handler: LP_TOUCH }, + Vector { _handler: LP_TSENS }, + Vector { _handler: LP_UART }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: LP_SYS }, + Vector { _handler: LP_HUK }, + Vector { _reserved: 0 }, + Vector { + _handler: USB_DEVICE, + }, + Vector { _reserved: 0 }, + Vector { _handler: DMA }, + Vector { _handler: SPI2 }, + Vector { _handler: SPI3 }, + Vector { _handler: I2S0 }, + Vector { _handler: I2S1 }, + Vector { _handler: I2S2 }, + Vector { _handler: UHCI0 }, + Vector { _handler: UART0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: PWM0 }, + Vector { _handler: PWM1 }, + Vector { _handler: TWAI0 }, + Vector { _handler: TWAI1 }, + Vector { _handler: TWAI2 }, + Vector { _handler: RMT }, + Vector { _handler: I2C0 }, + Vector { _handler: I2C1 }, + Vector { _handler: TG0_T0 }, + Vector { _handler: TG0_T1 }, + Vector { _handler: TG0_WDT }, + Vector { _handler: TG1_T0 }, + Vector { _handler: TG1_T1 }, + Vector { _handler: TG1_WDT }, + Vector { _handler: LEDC }, + Vector { + _handler: SYSTIMER_TARGET0, + }, + Vector { + _handler: SYSTIMER_TARGET1, + }, + Vector { + _handler: SYSTIMER_TARGET2, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RSA }, + Vector { _handler: AES }, + Vector { _handler: SHA }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: GPIO_INT0, + }, + Vector { + _handler: GPIO_INT1, + }, + Vector { + _handler: GPIO_INT2, + }, + Vector { + _handler: GPIO_INT3, + }, + Vector { + _handler: GPIO_PAD_COMP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CACHE }, + Vector { _reserved: 0 }, + Vector { + _handler: CSI_BRIDGE, + }, + Vector { + _handler: DSI_BRIDGE, + }, + Vector { _handler: CSI }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: JPEG }, + Vector { _handler: PPA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: ISP }, + Vector { _handler: I3C }, + Vector { _handler: I3C_SLV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: HP_SYS }, + Vector { _handler: PCNT }, + Vector { _handler: PAU }, + Vector { + _handler: PARLIO_RX, + }, + Vector { + _handler: PARLIO_TX, + }, + Vector { + _handler: H264_DMA2D_OUT_CH0, + }, + Vector { + _handler: H264_DMA2D_OUT_CH1, + }, + Vector { + _handler: H264_DMA2D_OUT_CH2, + }, + Vector { + _handler: H264_DMA2D_OUT_CH3, + }, + Vector { + _handler: H264_DMA2D_OUT_CH4, + }, + Vector { + _handler: H264_DMA2D_IN_CH0, + }, + Vector { + _handler: H264_DMA2D_IN_CH1, + }, + Vector { + _handler: H264_DMA2D_IN_CH2, + }, + Vector { + _handler: H264_DMA2D_IN_CH3, + }, + Vector { + _handler: H264_DMA2D_IN_CH4, + }, + Vector { + _handler: H264_DMA2D_IN_CH5, + }, + Vector { _handler: H264_REG }, + Vector { + _handler: ASSIST_DEBUG, + }, +]; +#[doc(hidden)] +pub mod interrupt; +pub use self::interrupt::Interrupt; +#[doc = "ADC (Analog to Digital Converter)"] +pub struct ADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC {} +impl ADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc::RegisterBlock = 0x500d_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ADC { + type Target = adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC").finish() + } +} +#[doc = "ADC (Analog to Digital Converter)"] +pub mod adc; +#[doc = "AES (Advanced Encryption Standard) Accelerator"] +pub struct AES { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AES {} +impl AES { + #[doc = r"Pointer to the register block"] + pub const PTR: *const aes::RegisterBlock = 0x5009_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const aes::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for AES { + type Target = aes::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AES { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AES").finish() + } +} +#[doc = "AES (Advanced Encryption Standard) Accelerator"] +pub mod aes; +#[doc = "LP_I2C_ANA_MST Peripheral"] +pub struct LP_I2C_ANA_MST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_I2C_ANA_MST {} +impl LP_I2C_ANA_MST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_i2c_ana_mst::RegisterBlock = 0x5012_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_i2c_ana_mst::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_I2C_ANA_MST { + type Target = lp_i2c_ana_mst::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_I2C_ANA_MST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2C_ANA_MST").finish() + } +} +#[doc = "LP_I2C_ANA_MST Peripheral"] +pub mod lp_i2c_ana_mst; +#[doc = "Debug Assist"] +pub struct ASSIST_DEBUG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ASSIST_DEBUG {} +impl ASSIST_DEBUG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const assist_debug::RegisterBlock = 0x3ff0_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const assist_debug::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ASSIST_DEBUG { + type Target = assist_debug::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ASSIST_DEBUG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ASSIST_DEBUG").finish() + } +} +#[doc = "Debug Assist"] +pub mod assist_debug; +#[doc = "AXI_DMA Peripheral"] +pub struct AXI_DMA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AXI_DMA {} +impl AXI_DMA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const axi_dma::RegisterBlock = 0x5008_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const axi_dma::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for AXI_DMA { + type Target = axi_dma::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AXI_DMA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_DMA").finish() + } +} +#[doc = "AXI_DMA Peripheral"] +pub mod axi_dma; +#[doc = "BITSCRAMBLER Peripheral"] +pub struct BITSCRAMBLER { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BITSCRAMBLER {} +impl BITSCRAMBLER { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bitscrambler::RegisterBlock = 0x500a_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bitscrambler::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for BITSCRAMBLER { + type Target = bitscrambler::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BITSCRAMBLER { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BITSCRAMBLER").finish() + } +} +#[doc = "BITSCRAMBLER Peripheral"] +pub mod bitscrambler; +#[doc = "CACHE Peripheral"] +pub struct CACHE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CACHE {} +impl CACHE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const cache::RegisterBlock = 0x3ff1_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const cache::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for CACHE { + type Target = cache::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CACHE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CACHE").finish() + } +} +#[doc = "CACHE Peripheral"] +pub mod cache; +#[doc = "Interrupt Controller (Core 0)"] +pub struct INTERRUPT_CORE0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for INTERRUPT_CORE0 {} +impl INTERRUPT_CORE0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const interrupt_core0::RegisterBlock = 0x500d_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const interrupt_core0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for INTERRUPT_CORE0 { + type Target = interrupt_core0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for INTERRUPT_CORE0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTERRUPT_CORE0").finish() + } +} +#[doc = "Interrupt Controller (Core 0)"] +pub mod interrupt_core0; +#[doc = "Interrupt Controller (Core 1)"] +pub struct INTERRUPT_CORE1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for INTERRUPT_CORE1 {} +impl INTERRUPT_CORE1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const interrupt_core1::RegisterBlock = 0x500d_6800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const interrupt_core1::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for INTERRUPT_CORE1 { + type Target = interrupt_core1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for INTERRUPT_CORE1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTERRUPT_CORE1").finish() + } +} +#[doc = "Interrupt Controller (Core 1)"] +pub mod interrupt_core1; +#[doc = "MIPI Camera Interface Bridge"] +pub struct MIPI_CSI_BRIDGE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MIPI_CSI_BRIDGE {} +impl MIPI_CSI_BRIDGE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mipi_csi_bridge::RegisterBlock = 0x5009_f800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mipi_csi_bridge::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for MIPI_CSI_BRIDGE { + type Target = mipi_csi_bridge::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MIPI_CSI_BRIDGE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MIPI_CSI_BRIDGE").finish() + } +} +#[doc = "MIPI Camera Interface Bridge"] +pub mod mipi_csi_bridge; +#[doc = "MIPI Camera Interface Host"] +pub struct MIPI_CSI_HOST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MIPI_CSI_HOST {} +impl MIPI_CSI_HOST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mipi_csi_host::RegisterBlock = 0x5009_f000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mipi_csi_host::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for MIPI_CSI_HOST { + type Target = mipi_csi_host::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MIPI_CSI_HOST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MIPI_CSI_HOST").finish() + } +} +#[doc = "MIPI Camera Interface Host"] +pub mod mipi_csi_host; +#[doc = "DMA (Direct Memory Access) Controller"] +pub struct DMA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMA {} +impl DMA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dma::RegisterBlock = 0x5008_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dma::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for DMA { + type Target = dma::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA").finish() + } +} +#[doc = "DMA (Direct Memory Access) Controller"] +pub mod dma; +#[doc = "Digital Signature"] +pub struct DS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DS {} +impl DS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ds::RegisterBlock = 0x5009_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ds::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for DS { + type Target = ds::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DS").finish() + } +} +#[doc = "Digital Signature"] +pub mod ds; +#[doc = "MIPI Camera Interface Bridge"] +pub struct MIPI_DSI_BRIDGE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MIPI_DSI_BRIDGE {} +impl MIPI_DSI_BRIDGE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mipi_dsi_bridge::RegisterBlock = 0x500a_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mipi_dsi_bridge::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for MIPI_DSI_BRIDGE { + type Target = mipi_dsi_bridge::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MIPI_DSI_BRIDGE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MIPI_DSI_BRIDGE").finish() + } +} +#[doc = "MIPI Camera Interface Bridge"] +pub mod mipi_dsi_bridge; +#[doc = "MIPI Display Interface Host"] +pub struct MIPI_DSI_HOST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MIPI_DSI_HOST {} +impl MIPI_DSI_HOST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mipi_dsi_host::RegisterBlock = 0x500a_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mipi_dsi_host::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for MIPI_DSI_HOST { + type Target = mipi_dsi_host::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MIPI_DSI_HOST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MIPI_DSI_HOST").finish() + } +} +#[doc = "MIPI Display Interface Host"] +pub mod mipi_dsi_host; +#[doc = "ECC (ECC Hardware Accelerator)"] +pub struct ECC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ECC {} +impl ECC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ecc::RegisterBlock = 0x5009_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ecc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ECC { + type Target = ecc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ECC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECC").finish() + } +} +#[doc = "ECC (ECC Hardware Accelerator)"] +pub mod ecc; +#[doc = "ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator"] +pub struct ECDSA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ECDSA {} +impl ECDSA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ecdsa::RegisterBlock = 0x5009_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ecdsa::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ECDSA { + type Target = ecdsa::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ECDSA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECDSA").finish() + } +} +#[doc = "ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator"] +pub mod ecdsa; +#[doc = "eFuse Controller"] +pub struct EFUSE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EFUSE {} +impl EFUSE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const efuse::RegisterBlock = 0x5012_d000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const efuse::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for EFUSE { + type Target = efuse::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EFUSE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EFUSE").finish() + } +} +#[doc = "eFuse Controller"] +pub mod efuse; +#[doc = "General Purpose Input/Output"] +pub struct GPIO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIO {} +impl GPIO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpio::RegisterBlock = 0x500e_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for GPIO { + type Target = gpio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GPIO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO").finish() + } +} +#[doc = "General Purpose Input/Output"] +pub mod gpio; +#[doc = "Sigma-Delta Modulation"] +pub struct GPIO_SD { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GPIO_SD {} +impl GPIO_SD { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpio_sd::RegisterBlock = 0x500e_0f00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio_sd::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for GPIO_SD { + type Target = gpio_sd::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GPIO_SD { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GPIO_SD").finish() + } +} +#[doc = "Sigma-Delta Modulation"] +pub mod gpio_sd; +#[doc = "H264 Encoder (Core)"] +pub struct H264 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for H264 {} +impl H264 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const h264::RegisterBlock = 0x5008_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const h264::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for H264 { + type Target = h264::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for H264 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264").finish() + } +} +#[doc = "H264 Encoder (Core)"] +pub mod h264; +#[doc = "H264 Encoder (DMA)"] +pub struct H264_DMA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for H264_DMA {} +impl H264_DMA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const h264_dma::RegisterBlock = 0x500a_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const h264_dma::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for H264_DMA { + type Target = h264_dma::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for H264_DMA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("H264_DMA").finish() + } +} +#[doc = "H264 Encoder (DMA)"] +pub mod h264_dma; +#[doc = "HMAC (Hash-based Message Authentication Code) Accelerator"] +pub struct HMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HMAC {} +impl HMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hmac::RegisterBlock = 0x5009_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hmac::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for HMAC { + type Target = hmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HMAC").finish() + } +} +#[doc = "HMAC (Hash-based Message Authentication Code) Accelerator"] +pub mod hmac; +#[doc = "High-Power System"] +pub struct HP_SYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HP_SYS {} +impl HP_SYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hp_sys::RegisterBlock = 0x500e_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hp_sys::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for HP_SYS { + type Target = hp_sys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HP_SYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SYS").finish() + } +} +#[doc = "High-Power System"] +pub mod hp_sys; +#[doc = "HP_SYS_CLKRST Peripheral"] +pub struct HP_SYS_CLKRST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HP_SYS_CLKRST {} +impl HP_SYS_CLKRST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hp_sys_clkrst::RegisterBlock = 0x500e_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hp_sys_clkrst::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for HP_SYS_CLKRST { + type Target = hp_sys_clkrst::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HP_SYS_CLKRST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SYS_CLKRST").finish() + } +} +#[doc = "HP_SYS_CLKRST Peripheral"] +pub mod hp_sys_clkrst; +#[doc = "LP_HUK Peripheral"] +pub struct LP_HUK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_HUK {} +impl LP_HUK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_huk::RegisterBlock = 0x5011_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_huk::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_HUK { + type Target = lp_huk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_HUK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_HUK").finish() + } +} +#[doc = "LP_HUK Peripheral"] +pub mod lp_huk; +#[doc = "I2C (Inter-Integrated Circuit) Controller 0"] +pub struct I2C0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C0 {} +impl I2C0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x500c_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2C0 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2C0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0").finish() + } +} +#[doc = "I2C (Inter-Integrated Circuit) Controller 0"] +pub mod i2c0; +#[doc = "I2C (Inter-Integrated Circuit) Controller 1"] +pub struct I2C1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C1 {} +impl I2C1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x500c_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2C1 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2C1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1").finish() + } +} +#[doc = "I2C (Inter-Integrated Circuit) Controller 1"] +pub use self::i2c0 as i2c1; +#[doc = "I2S (Inter-IC Sound) Controller 0"] +pub struct I2S0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S0 {} +impl I2S0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2s0::RegisterBlock = 0x500c_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2S0 { + type Target = i2s0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2S0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S0").finish() + } +} +#[doc = "I2S (Inter-IC Sound) Controller 0"] +pub mod i2s0; +#[doc = "I2S (Inter-IC Sound) Controller 1"] +pub struct I2S1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S1 {} +impl I2S1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2s0::RegisterBlock = 0x500c_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2S1 { + type Target = i2s0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2S1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S1").finish() + } +} +#[doc = "I2S (Inter-IC Sound) Controller 1"] +pub use self::i2s0 as i2s1; +#[doc = "I2S (Inter-IC Sound) Controller 2"] +pub struct I2S2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2S2 {} +impl I2S2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2s0::RegisterBlock = 0x500c_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2s0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2S2 { + type Target = i2s0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2S2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2S2").finish() + } +} +#[doc = "I2S (Inter-IC Sound) Controller 2"] +pub use self::i2s0 as i2s2; +#[doc = "I3C Controller (Master)"] +pub struct I3C_MST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I3C_MST {} +impl I3C_MST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i3c_mst::RegisterBlock = 0x500d_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i3c_mst::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I3C_MST { + type Target = i3c_mst::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I3C_MST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I3C_MST").finish() + } +} +#[doc = "I3C Controller (Master)"] +pub mod i3c_mst; +#[doc = "I3C_MST_MEM Peripheral"] +pub struct I3C_MST_MEM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I3C_MST_MEM {} +impl I3C_MST_MEM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i3c_mst_mem::RegisterBlock = 0x500d_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i3c_mst_mem::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I3C_MST_MEM { + type Target = i3c_mst_mem::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I3C_MST_MEM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I3C_MST_MEM").finish() + } +} +#[doc = "I3C_MST_MEM Peripheral"] +pub mod i3c_mst_mem; +#[doc = "I3C Controller (Slave)"] +pub struct I3C_SLV { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I3C_SLV {} +impl I3C_SLV { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i3c_slv::RegisterBlock = 0x500d_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i3c_slv::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I3C_SLV { + type Target = i3c_slv::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I3C_SLV { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I3C_SLV").finish() + } +} +#[doc = "I3C Controller (Slave)"] +pub mod i3c_slv; +#[doc = "AXI_ICM Peripheral"] +pub struct AXI_ICM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AXI_ICM {} +impl AXI_ICM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const axi_icm::RegisterBlock = 0x500a_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const axi_icm::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for AXI_ICM { + type Target = axi_icm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AXI_ICM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AXI_ICM").finish() + } +} +#[doc = "AXI_ICM Peripheral"] +pub mod axi_icm; +#[doc = "Input/Output Multiplexer"] +pub struct IO_MUX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IO_MUX {} +impl IO_MUX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const io_mux::RegisterBlock = 0x500e_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const io_mux::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for IO_MUX { + type Target = io_mux::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IO_MUX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO_MUX").finish() + } +} +#[doc = "Input/Output Multiplexer"] +pub mod io_mux; +#[doc = "ISP Peripheral"] +pub struct ISP { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ISP {} +impl ISP { + #[doc = r"Pointer to the register block"] + pub const PTR: *const isp::RegisterBlock = 0x500a_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const isp::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ISP { + type Target = isp::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ISP { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ISP").finish() + } +} +#[doc = "ISP Peripheral"] +pub mod isp; +#[doc = "JPEG Codec"] +pub struct JPEG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for JPEG {} +impl JPEG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const jpeg::RegisterBlock = 0x5008_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const jpeg::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for JPEG { + type Target = jpeg::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for JPEG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("JPEG").finish() + } +} +#[doc = "JPEG Codec"] +pub mod jpeg; +#[doc = "Camera/LCD Controller"] +pub struct LCD_CAM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LCD_CAM {} +impl LCD_CAM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lcd_cam::RegisterBlock = 0x500d_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lcd_cam::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LCD_CAM { + type Target = lcd_cam::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LCD_CAM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LCD_CAM").finish() + } +} +#[doc = "Camera/LCD Controller"] +pub mod lcd_cam; +#[doc = "LED Control PWM (Pulse Width Modulation)"] +pub struct LEDC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LEDC {} +impl LEDC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ledc::RegisterBlock = 0x500d_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ledc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LEDC { + type Target = ledc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LEDC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LEDC").finish() + } +} +#[doc = "LED Control PWM (Pulse Width Modulation)"] +pub mod ledc; +#[doc = "Low-power Interrupt Controller"] +pub struct LP_INTR { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_INTR {} +impl LP_INTR { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_intr::RegisterBlock = 0x5012_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_intr::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_INTR { + type Target = lp_intr::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_INTR { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_INTR").finish() + } +} +#[doc = "Low-power Interrupt Controller"] +pub mod lp_intr; +#[doc = "LP_PERI Peripheral"] +pub struct LP_PERI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_PERI {} +impl LP_PERI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_peri::RegisterBlock = 0x5012_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_peri::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_PERI { + type Target = lp_peri::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_PERI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_PERI").finish() + } +} +#[doc = "LP_PERI Peripheral"] +pub mod lp_peri; +#[doc = "LP_SYS Peripheral"] +pub struct LP_SYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_SYS {} +impl LP_SYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_sys::RegisterBlock = 0x5011_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_sys::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_SYS { + type Target = lp_sys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_SYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SYS").finish() + } +} +#[doc = "LP_SYS Peripheral"] +pub mod lp_sys; +#[doc = "LP_ANA_PERI Peripheral"] +pub struct LP_ANA_PERI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_ANA_PERI {} +impl LP_ANA_PERI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_ana_peri::RegisterBlock = 0x5011_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_ana_peri::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_ANA_PERI { + type Target = lp_ana_peri::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_ANA_PERI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_PERI").finish() + } +} +#[doc = "LP_ANA_PERI Peripheral"] +pub mod lp_ana_peri; +#[doc = "LP_AON_CLKRST Peripheral"] +pub struct LP_AON_CLKRST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_AON_CLKRST {} +impl LP_AON_CLKRST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_aon_clkrst::RegisterBlock = 0x5011_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_aon_clkrst::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_AON_CLKRST { + type Target = lp_aon_clkrst::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_AON_CLKRST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AON_CLKRST").finish() + } +} +#[doc = "LP_AON_CLKRST Peripheral"] +pub mod lp_aon_clkrst; +#[doc = "Low-power General Purpose Input/Output"] +pub struct LP_GPIO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_GPIO {} +impl LP_GPIO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_gpio::RegisterBlock = 0x5012_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_gpio::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_GPIO { + type Target = lp_gpio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_GPIO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_GPIO").finish() + } +} +#[doc = "Low-power General Purpose Input/Output"] +pub mod lp_gpio; +#[doc = "Low-power I2C (Inter-Integrated Circuit) Controller 0"] +pub struct LP_I2C0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_I2C0 {} +impl LP_I2C0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_i2c0::RegisterBlock = 0x5012_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_I2C0 { + type Target = lp_i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_I2C0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2C0").finish() + } +} +#[doc = "Low-power I2C (Inter-Integrated Circuit) Controller 0"] +pub mod lp_i2c0; +#[doc = "Low-power I2S (Inter-IC Sound) Controller 0"] +pub struct LP_I2S0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_I2S0 {} +impl LP_I2S0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_i2s0::RegisterBlock = 0x5012_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_i2s0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_I2S0 { + type Target = lp_i2s0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_I2S0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2S0").finish() + } +} +#[doc = "Low-power I2S (Inter-IC Sound) Controller 0"] +pub mod lp_i2s0; +#[doc = "Low-power Input/Output Multiplexer"] +pub struct LP_IO_MUX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_IO_MUX {} +impl LP_IO_MUX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_io_mux::RegisterBlock = 0x5012_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_io_mux::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_IO_MUX { + type Target = lp_io_mux::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_IO_MUX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_IO_MUX").finish() + } +} +#[doc = "Low-power Input/Output Multiplexer"] +pub mod lp_io_mux; +#[doc = "Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller"] +pub struct LP_UART { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_UART {} +impl LP_UART { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_uart::RegisterBlock = 0x5012_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_uart::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_UART { + type Target = lp_uart::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_UART { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_UART").finish() + } +} +#[doc = "Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller"] +pub mod lp_uart; +#[doc = "Motor Control Pulse-Width Modulation 0"] +pub struct MCPWM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MCPWM0 {} +impl MCPWM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mcpwm0::RegisterBlock = 0x500c_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mcpwm0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for MCPWM0 { + type Target = mcpwm0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MCPWM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCPWM0").finish() + } +} +#[doc = "Motor Control Pulse-Width Modulation 0"] +pub mod mcpwm0; +#[doc = "Motor Control Pulse-Width Modulation 1"] +pub struct MCPWM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MCPWM1 {} +impl MCPWM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mcpwm0::RegisterBlock = 0x500c_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mcpwm0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for MCPWM1 { + type Target = mcpwm0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MCPWM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCPWM1").finish() + } +} +#[doc = "Motor Control Pulse-Width Modulation 1"] +pub use self::mcpwm0 as mcpwm1; +#[doc = "Parallel IO Controller"] +pub struct PARL_IO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PARL_IO {} +impl PARL_IO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const parl_io::RegisterBlock = 0x500c_f000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const parl_io::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PARL_IO { + type Target = parl_io::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PARL_IO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PARL_IO").finish() + } +} +#[doc = "Parallel IO Controller"] +pub mod parl_io; +#[doc = "PAU Peripheral"] +pub struct PAU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAU {} +impl PAU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pau::RegisterBlock = 0x6009_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pau::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PAU { + type Target = pau::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAU").finish() + } +} +#[doc = "PAU Peripheral"] +pub mod pau; +#[doc = "Pulse Count Controller"] +pub struct PCNT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PCNT {} +impl PCNT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pcnt::RegisterBlock = 0x500c_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pcnt::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PCNT { + type Target = pcnt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PCNT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PCNT").finish() + } +} +#[doc = "Pulse Count Controller"] +pub mod pcnt; +#[doc = "PMU Peripheral"] +pub struct PMU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PMU {} +impl PMU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pmu::RegisterBlock = 0x5011_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pmu::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PMU { + type Target = pmu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PMU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMU").finish() + } +} +#[doc = "PMU Peripheral"] +pub mod pmu; +#[doc = "PPA Peripheral"] +pub struct PPA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PPA {} +impl PPA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ppa::RegisterBlock = 0x5008_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ppa::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PPA { + type Target = ppa::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PPA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PPA").finish() + } +} +#[doc = "PPA Peripheral"] +pub mod ppa; +#[doc = "PVT Peripheral"] +pub struct PVT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PVT {} +impl PVT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pvt::RegisterBlock = 0x5009_e000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pvt::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PVT { + type Target = pvt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PVT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PVT").finish() + } +} +#[doc = "PVT Peripheral"] +pub mod pvt; +#[doc = "Remote Control"] +pub struct RMT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RMT {} +impl RMT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rmt::RegisterBlock = 0x500d_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rmt::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for RMT { + type Target = rmt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RMT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RMT").finish() + } +} +#[doc = "Remote Control"] +pub mod rmt; +#[doc = "RSA (Rivest Shamir Adleman) Accelerator"] +pub struct RSA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RSA {} +impl RSA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rsa::RegisterBlock = 0x5009_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rsa::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for RSA { + type Target = rsa::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RSA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSA").finish() + } +} +#[doc = "RSA (Rivest Shamir Adleman) Accelerator"] +pub mod rsa; +#[doc = "Low-power Analog to Digital Converter"] +pub struct LP_ADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_ADC {} +impl LP_ADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_adc::RegisterBlock = 0x5012_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_adc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_ADC { + type Target = lp_adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_ADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ADC").finish() + } +} +#[doc = "Low-power Analog to Digital Converter"] +pub mod lp_adc; +#[doc = "Low-power Timer"] +pub struct LP_TIMER { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_TIMER {} +impl LP_TIMER { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_timer::RegisterBlock = 0x5011_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_timer::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_TIMER { + type Target = lp_timer::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_TIMER { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TIMER").finish() + } +} +#[doc = "Low-power Timer"] +pub mod lp_timer; +#[doc = "LP_TOUCH Peripheral"] +pub struct LP_TOUCH { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_TOUCH {} +impl LP_TOUCH { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_touch::RegisterBlock = 0x5012_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_touch::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_TOUCH { + type Target = lp_touch::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_TOUCH { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TOUCH").finish() + } +} +#[doc = "LP_TOUCH Peripheral"] +pub mod lp_touch; +#[doc = "Low-power Watchdog Timer"] +pub struct LP_WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_WDT {} +impl LP_WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_wdt::RegisterBlock = 0x5011_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_wdt::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_WDT { + type Target = lp_wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_WDT").finish() + } +} +#[doc = "Low-power Watchdog Timer"] +pub mod lp_wdt; +#[doc = "SD/MMC Host Controller"] +pub struct SDHOST { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SDHOST {} +impl SDHOST { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sdhost::RegisterBlock = 0x5008_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sdhost::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SDHOST { + type Target = sdhost::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SDHOST { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDHOST").finish() + } +} +#[doc = "SD/MMC Host Controller"] +pub mod sdhost; +#[doc = "SHA (Secure Hash Algorithm) Accelerator"] +pub struct SHA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SHA {} +impl SHA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sha::RegisterBlock = 0x5009_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sha::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SHA { + type Target = sha::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SHA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHA").finish() + } +} +#[doc = "SHA (Secure Hash Algorithm) Accelerator"] +pub mod sha; +#[doc = "Event Task Matrix"] +pub struct SOC_ETM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SOC_ETM {} +impl SOC_ETM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const soc_etm::RegisterBlock = 0x500d_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const soc_etm::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SOC_ETM { + type Target = soc_etm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SOC_ETM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SOC_ETM").finish() + } +} +#[doc = "Event Task Matrix"] +pub mod soc_etm; +#[doc = "SPI (Serial Peripheral Interface) Controller 0"] +pub struct SPI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI0 {} +impl SPI0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x5008_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SPI0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI0").finish() + } +} +#[doc = "SPI (Serial Peripheral Interface) Controller 0"] +pub mod spi0; +#[doc = "SPI (Serial Peripheral Interface) Controller 1"] +pub struct SPI1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI1 {} +impl SPI1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi1::RegisterBlock = 0x5008_d000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi1::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SPI1 { + type Target = spi1::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI1").finish() + } +} +#[doc = "SPI (Serial Peripheral Interface) Controller 1"] +pub mod spi1; +#[doc = "SPI (Serial Peripheral Interface) Controller 2"] +pub struct SPI2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI2 {} +impl SPI2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi2::RegisterBlock = 0x500d_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi2::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SPI2 { + type Target = spi2::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI2").finish() + } +} +#[doc = "SPI (Serial Peripheral Interface) Controller 2"] +pub mod spi2; +#[doc = "SPI (Serial Peripheral Interface) Controller 3"] +pub struct SPI3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI3 {} +impl SPI3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi3::RegisterBlock = 0x500d_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi3::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SPI3 { + type Target = spi3::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI3").finish() + } +} +#[doc = "SPI (Serial Peripheral Interface) Controller 3"] +pub mod spi3; +#[doc = "System Timer"] +pub struct SYSTIMER { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSTIMER {} +impl SYSTIMER { + #[doc = r"Pointer to the register block"] + pub const PTR: *const systimer::RegisterBlock = 0x500e_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const systimer::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SYSTIMER { + type Target = systimer::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSTIMER { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSTIMER").finish() + } +} +#[doc = "System Timer"] +pub mod systimer; +#[doc = "Timer Group 0"] +pub struct TIMG0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMG0 {} +impl TIMG0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timg0::RegisterBlock = 0x500c_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timg0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TIMG0 { + type Target = timg0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMG0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMG0").finish() + } +} +#[doc = "Timer Group 0"] +pub mod timg0; +#[doc = "Timer Group 1"] +pub struct TIMG1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMG1 {} +impl TIMG1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timg0::RegisterBlock = 0x500c_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timg0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TIMG1 { + type Target = timg0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMG1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMG1").finish() + } +} +#[doc = "Timer Group 1"] +pub use self::timg0 as timg1; +#[doc = "TRACE0 Peripheral"] +pub struct TRACE0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TRACE0 {} +impl TRACE0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const trace0::RegisterBlock = 0x3ff0_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const trace0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TRACE0 { + type Target = trace0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TRACE0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TRACE0").finish() + } +} +#[doc = "TRACE0 Peripheral"] +pub mod trace0; +#[doc = "TRACE1 Peripheral"] +pub struct TRACE1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TRACE1 {} +impl TRACE1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const trace0::RegisterBlock = 0x3ff0_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const trace0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TRACE1 { + type Target = trace0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TRACE1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TRACE1").finish() + } +} +#[doc = "TRACE1 Peripheral"] +pub use self::trace0 as trace1; +#[doc = "Low-power Temperature Sensor"] +pub struct LP_TSENS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for LP_TSENS {} +impl LP_TSENS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const lp_tsens::RegisterBlock = 0x5012_f000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const lp_tsens::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for LP_TSENS { + type Target = lp_tsens::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for LP_TSENS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TSENS").finish() + } +} +#[doc = "Low-power Temperature Sensor"] +pub mod lp_tsens; +#[doc = "Two-Wire Automotive Interface"] +pub struct TWAI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWAI0 {} +impl TWAI0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twai0::RegisterBlock = 0x500d_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twai0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TWAI0 { + type Target = twai0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWAI0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWAI0").finish() + } +} +#[doc = "Two-Wire Automotive Interface"] +pub mod twai0; +#[doc = "Two-Wire Automotive Interface"] +pub struct TWAI1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWAI1 {} +impl TWAI1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twai0::RegisterBlock = 0x500d_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twai0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TWAI1 { + type Target = twai0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWAI1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWAI1").finish() + } +} +#[doc = "Two-Wire Automotive Interface"] +pub use self::twai0 as twai1; +#[doc = "Two-Wire Automotive Interface"] +pub struct TWAI2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TWAI2 {} +impl TWAI2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const twai0::RegisterBlock = 0x500d_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const twai0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TWAI2 { + type Target = twai0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TWAI2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TWAI2").finish() + } +} +#[doc = "Two-Wire Automotive Interface"] +pub use self::twai0 as twai2; +#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"] +pub struct UART0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART0 {} +impl UART0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x500c_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UART0 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART0").finish() + } +} +#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"] +pub mod uart0; +#[doc = "Universal Host Controller Interface 0"] +pub struct UHCI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UHCI0 {} +impl UHCI0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uhci0::RegisterBlock = 0x500d_f000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uhci0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UHCI0 { + type Target = uhci0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UHCI0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UHCI0").finish() + } +} +#[doc = "Universal Host Controller Interface 0"] +pub mod uhci0; +#[doc = "Full-speed USB Serial/JTAG Controller"] +pub struct USB_DEVICE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_DEVICE {} +impl USB_DEVICE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_device::RegisterBlock = 0x500d_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_device::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for USB_DEVICE { + type Target = usb_device::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_DEVICE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_DEVICE").finish() + } +} +#[doc = "Full-speed USB Serial/JTAG Controller"] +pub mod usb_device; +#[doc = "USB_WRAP Peripheral"] +pub struct USB_WRAP { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_WRAP {} +impl USB_WRAP { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_wrap::RegisterBlock = 0x5008_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_wrap::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for USB_WRAP { + type Target = usb_wrap::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_WRAP { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_WRAP").finish() + } +} +#[doc = "USB_WRAP Peripheral"] +pub mod usb_wrap; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "ADC"] + pub ADC: ADC, + #[doc = "AES"] + pub AES: AES, + #[doc = "LP_I2C_ANA_MST"] + pub LP_I2C_ANA_MST: LP_I2C_ANA_MST, + #[doc = "ASSIST_DEBUG"] + pub ASSIST_DEBUG: ASSIST_DEBUG, + #[doc = "AXI_DMA"] + pub AXI_DMA: AXI_DMA, + #[doc = "BITSCRAMBLER"] + pub BITSCRAMBLER: BITSCRAMBLER, + #[doc = "CACHE"] + pub CACHE: CACHE, + #[doc = "INTERRUPT_CORE0"] + pub INTERRUPT_CORE0: INTERRUPT_CORE0, + #[doc = "INTERRUPT_CORE1"] + pub INTERRUPT_CORE1: INTERRUPT_CORE1, + #[doc = "MIPI_CSI_BRIDGE"] + pub MIPI_CSI_BRIDGE: MIPI_CSI_BRIDGE, + #[doc = "MIPI_CSI_HOST"] + pub MIPI_CSI_HOST: MIPI_CSI_HOST, + #[doc = "DMA"] + pub DMA: DMA, + #[doc = "DS"] + pub DS: DS, + #[doc = "MIPI_DSI_BRIDGE"] + pub MIPI_DSI_BRIDGE: MIPI_DSI_BRIDGE, + #[doc = "MIPI_DSI_HOST"] + pub MIPI_DSI_HOST: MIPI_DSI_HOST, + #[doc = "ECC"] + pub ECC: ECC, + #[doc = "ECDSA"] + pub ECDSA: ECDSA, + #[doc = "EFUSE"] + pub EFUSE: EFUSE, + #[doc = "GPIO"] + pub GPIO: GPIO, + #[doc = "GPIO_SD"] + pub GPIO_SD: GPIO_SD, + #[doc = "H264"] + pub H264: H264, + #[doc = "H264_DMA"] + pub H264_DMA: H264_DMA, + #[doc = "HMAC"] + pub HMAC: HMAC, + #[doc = "HP_SYS"] + pub HP_SYS: HP_SYS, + #[doc = "HP_SYS_CLKRST"] + pub HP_SYS_CLKRST: HP_SYS_CLKRST, + #[doc = "LP_HUK"] + pub LP_HUK: LP_HUK, + #[doc = "I2C0"] + pub I2C0: I2C0, + #[doc = "I2C1"] + pub I2C1: I2C1, + #[doc = "I2S0"] + pub I2S0: I2S0, + #[doc = "I2S1"] + pub I2S1: I2S1, + #[doc = "I2S2"] + pub I2S2: I2S2, + #[doc = "I3C_MST"] + pub I3C_MST: I3C_MST, + #[doc = "I3C_MST_MEM"] + pub I3C_MST_MEM: I3C_MST_MEM, + #[doc = "I3C_SLV"] + pub I3C_SLV: I3C_SLV, + #[doc = "AXI_ICM"] + pub AXI_ICM: AXI_ICM, + #[doc = "IO_MUX"] + pub IO_MUX: IO_MUX, + #[doc = "ISP"] + pub ISP: ISP, + #[doc = "JPEG"] + pub JPEG: JPEG, + #[doc = "LCD_CAM"] + pub LCD_CAM: LCD_CAM, + #[doc = "LEDC"] + pub LEDC: LEDC, + #[doc = "LP_INTR"] + pub LP_INTR: LP_INTR, + #[doc = "LP_PERI"] + pub LP_PERI: LP_PERI, + #[doc = "LP_SYS"] + pub LP_SYS: LP_SYS, + #[doc = "LP_ANA_PERI"] + pub LP_ANA_PERI: LP_ANA_PERI, + #[doc = "LP_AON_CLKRST"] + pub LP_AON_CLKRST: LP_AON_CLKRST, + #[doc = "LP_GPIO"] + pub LP_GPIO: LP_GPIO, + #[doc = "LP_I2C0"] + pub LP_I2C0: LP_I2C0, + #[doc = "LP_I2S0"] + pub LP_I2S0: LP_I2S0, + #[doc = "LP_IO_MUX"] + pub LP_IO_MUX: LP_IO_MUX, + #[doc = "LP_UART"] + pub LP_UART: LP_UART, + #[doc = "MCPWM0"] + pub MCPWM0: MCPWM0, + #[doc = "MCPWM1"] + pub MCPWM1: MCPWM1, + #[doc = "PARL_IO"] + pub PARL_IO: PARL_IO, + #[doc = "PAU"] + pub PAU: PAU, + #[doc = "PCNT"] + pub PCNT: PCNT, + #[doc = "PMU"] + pub PMU: PMU, + #[doc = "PPA"] + pub PPA: PPA, + #[doc = "PVT"] + pub PVT: PVT, + #[doc = "RMT"] + pub RMT: RMT, + #[doc = "RSA"] + pub RSA: RSA, + #[doc = "LP_ADC"] + pub LP_ADC: LP_ADC, + #[doc = "LP_TIMER"] + pub LP_TIMER: LP_TIMER, + #[doc = "LP_TOUCH"] + pub LP_TOUCH: LP_TOUCH, + #[doc = "LP_WDT"] + pub LP_WDT: LP_WDT, + #[doc = "SDHOST"] + pub SDHOST: SDHOST, + #[doc = "SHA"] + pub SHA: SHA, + #[doc = "SOC_ETM"] + pub SOC_ETM: SOC_ETM, + #[doc = "SPI0"] + pub SPI0: SPI0, + #[doc = "SPI1"] + pub SPI1: SPI1, + #[doc = "SPI2"] + pub SPI2: SPI2, + #[doc = "SPI3"] + pub SPI3: SPI3, + #[doc = "SYSTIMER"] + pub SYSTIMER: SYSTIMER, + #[doc = "TIMG0"] + pub TIMG0: TIMG0, + #[doc = "TIMG1"] + pub TIMG1: TIMG1, + #[doc = "TRACE0"] + pub TRACE0: TRACE0, + #[doc = "TRACE1"] + pub TRACE1: TRACE1, + #[doc = "LP_TSENS"] + pub LP_TSENS: LP_TSENS, + #[doc = "TWAI0"] + pub TWAI0: TWAI0, + #[doc = "TWAI1"] + pub TWAI1: TWAI1, + #[doc = "TWAI2"] + pub TWAI2: TWAI2, + #[doc = "UART0"] + pub UART0: UART0, + #[doc = "UHCI0"] + pub UHCI0: UHCI0, + #[doc = "USB_DEVICE"] + pub USB_DEVICE: USB_DEVICE, + #[doc = "USB_WRAP"] + pub USB_WRAP: USB_WRAP, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + ADC: ADC { + _marker: PhantomData, + }, + AES: AES { + _marker: PhantomData, + }, + LP_I2C_ANA_MST: LP_I2C_ANA_MST { + _marker: PhantomData, + }, + ASSIST_DEBUG: ASSIST_DEBUG { + _marker: PhantomData, + }, + AXI_DMA: AXI_DMA { + _marker: PhantomData, + }, + BITSCRAMBLER: BITSCRAMBLER { + _marker: PhantomData, + }, + CACHE: CACHE { + _marker: PhantomData, + }, + INTERRUPT_CORE0: INTERRUPT_CORE0 { + _marker: PhantomData, + }, + INTERRUPT_CORE1: INTERRUPT_CORE1 { + _marker: PhantomData, + }, + MIPI_CSI_BRIDGE: MIPI_CSI_BRIDGE { + _marker: PhantomData, + }, + MIPI_CSI_HOST: MIPI_CSI_HOST { + _marker: PhantomData, + }, + DMA: DMA { + _marker: PhantomData, + }, + DS: DS { + _marker: PhantomData, + }, + MIPI_DSI_BRIDGE: MIPI_DSI_BRIDGE { + _marker: PhantomData, + }, + MIPI_DSI_HOST: MIPI_DSI_HOST { + _marker: PhantomData, + }, + ECC: ECC { + _marker: PhantomData, + }, + ECDSA: ECDSA { + _marker: PhantomData, + }, + EFUSE: EFUSE { + _marker: PhantomData, + }, + GPIO: GPIO { + _marker: PhantomData, + }, + GPIO_SD: GPIO_SD { + _marker: PhantomData, + }, + H264: H264 { + _marker: PhantomData, + }, + H264_DMA: H264_DMA { + _marker: PhantomData, + }, + HMAC: HMAC { + _marker: PhantomData, + }, + HP_SYS: HP_SYS { + _marker: PhantomData, + }, + HP_SYS_CLKRST: HP_SYS_CLKRST { + _marker: PhantomData, + }, + LP_HUK: LP_HUK { + _marker: PhantomData, + }, + I2C0: I2C0 { + _marker: PhantomData, + }, + I2C1: I2C1 { + _marker: PhantomData, + }, + I2S0: I2S0 { + _marker: PhantomData, + }, + I2S1: I2S1 { + _marker: PhantomData, + }, + I2S2: I2S2 { + _marker: PhantomData, + }, + I3C_MST: I3C_MST { + _marker: PhantomData, + }, + I3C_MST_MEM: I3C_MST_MEM { + _marker: PhantomData, + }, + I3C_SLV: I3C_SLV { + _marker: PhantomData, + }, + AXI_ICM: AXI_ICM { + _marker: PhantomData, + }, + IO_MUX: IO_MUX { + _marker: PhantomData, + }, + ISP: ISP { + _marker: PhantomData, + }, + JPEG: JPEG { + _marker: PhantomData, + }, + LCD_CAM: LCD_CAM { + _marker: PhantomData, + }, + LEDC: LEDC { + _marker: PhantomData, + }, + LP_INTR: LP_INTR { + _marker: PhantomData, + }, + LP_PERI: LP_PERI { + _marker: PhantomData, + }, + LP_SYS: LP_SYS { + _marker: PhantomData, + }, + LP_ANA_PERI: LP_ANA_PERI { + _marker: PhantomData, + }, + LP_AON_CLKRST: LP_AON_CLKRST { + _marker: PhantomData, + }, + LP_GPIO: LP_GPIO { + _marker: PhantomData, + }, + LP_I2C0: LP_I2C0 { + _marker: PhantomData, + }, + LP_I2S0: LP_I2S0 { + _marker: PhantomData, + }, + LP_IO_MUX: LP_IO_MUX { + _marker: PhantomData, + }, + LP_UART: LP_UART { + _marker: PhantomData, + }, + MCPWM0: MCPWM0 { + _marker: PhantomData, + }, + MCPWM1: MCPWM1 { + _marker: PhantomData, + }, + PARL_IO: PARL_IO { + _marker: PhantomData, + }, + PAU: PAU { + _marker: PhantomData, + }, + PCNT: PCNT { + _marker: PhantomData, + }, + PMU: PMU { + _marker: PhantomData, + }, + PPA: PPA { + _marker: PhantomData, + }, + PVT: PVT { + _marker: PhantomData, + }, + RMT: RMT { + _marker: PhantomData, + }, + RSA: RSA { + _marker: PhantomData, + }, + LP_ADC: LP_ADC { + _marker: PhantomData, + }, + LP_TIMER: LP_TIMER { + _marker: PhantomData, + }, + LP_TOUCH: LP_TOUCH { + _marker: PhantomData, + }, + LP_WDT: LP_WDT { + _marker: PhantomData, + }, + SDHOST: SDHOST { + _marker: PhantomData, + }, + SHA: SHA { + _marker: PhantomData, + }, + SOC_ETM: SOC_ETM { + _marker: PhantomData, + }, + SPI0: SPI0 { + _marker: PhantomData, + }, + SPI1: SPI1 { + _marker: PhantomData, + }, + SPI2: SPI2 { + _marker: PhantomData, + }, + SPI3: SPI3 { + _marker: PhantomData, + }, + SYSTIMER: SYSTIMER { + _marker: PhantomData, + }, + TIMG0: TIMG0 { + _marker: PhantomData, + }, + TIMG1: TIMG1 { + _marker: PhantomData, + }, + TRACE0: TRACE0 { + _marker: PhantomData, + }, + TRACE1: TRACE1 { + _marker: PhantomData, + }, + LP_TSENS: LP_TSENS { + _marker: PhantomData, + }, + TWAI0: TWAI0 { + _marker: PhantomData, + }, + TWAI1: TWAI1 { + _marker: PhantomData, + }, + TWAI2: TWAI2 { + _marker: PhantomData, + }, + UART0: UART0 { + _marker: PhantomData, + }, + UHCI0: UHCI0 { + _marker: PhantomData, + }, + USB_DEVICE: USB_DEVICE { + _marker: PhantomData, + }, + USB_WRAP: USB_WRAP { + _marker: PhantomData, + }, + } + } +} diff --git a/esp32p4/src/lp_adc.rs b/esp32p4/src/lp_adc.rs new file mode 100644 index 0000000000..8e65626e93 --- /dev/null +++ b/esp32p4/src/lp_adc.rs @@ -0,0 +1,327 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + reader1_ctrl: READER1_CTRL, + reader1_status: READER1_STATUS, + meas1_ctrl1: MEAS1_CTRL1, + meas1_ctrl2: MEAS1_CTRL2, + meas1_mux: MEAS1_MUX, + atten1: ATTEN1, + amp_ctrl1: AMP_CTRL1, + amp_ctrl2: AMP_CTRL2, + amp_ctrl3: AMP_CTRL3, + reader2_ctrl: READER2_CTRL, + reader2_status: READER2_STATUS, + meas2_ctrl1: MEAS2_CTRL1, + meas2_ctrl2: MEAS2_CTRL2, + meas2_mux: MEAS2_MUX, + atten2: ATTEN2, + force_wpd_sar: FORCE_WPD_SAR, + meas_status: MEAS_STATUS, + reg_clken: REG_CLKEN, + cocpu_int_raw: COCPU_INT_RAW, + int_ena: INT_ENA, + int_st: INT_ST, + int_clr: INT_CLR, + int_ena_w1ts: INT_ENA_W1TS, + int_ena_w1tc: INT_ENA_W1TC, + wakeup1: WAKEUP1, + wakeup2: WAKEUP2, + wakeup_sel: WAKEUP_SEL, + sar1_hw_wakeup: SAR1_HW_WAKEUP, + sar2_hw_wakeup: SAR2_HW_WAKEUP, + rnd_eco_low: RND_ECO_LOW, + rnd_eco_high: RND_ECO_HIGH, + rnd_eco_cs: RND_ECO_CS, +} +impl RegisterBlock { + #[doc = "0x00 - Control the read operation of ADC1."] + #[inline(always)] + pub const fn reader1_ctrl(&self) -> &READER1_CTRL { + &self.reader1_ctrl + } + #[doc = "0x04 - N/A"] + #[inline(always)] + pub const fn reader1_status(&self) -> &READER1_STATUS { + &self.reader1_status + } + #[doc = "0x08 - N/A"] + #[inline(always)] + pub const fn meas1_ctrl1(&self) -> &MEAS1_CTRL1 { + &self.meas1_ctrl1 + } + #[doc = "0x0c - ADC1 configuration registers."] + #[inline(always)] + pub const fn meas1_ctrl2(&self) -> &MEAS1_CTRL2 { + &self.meas1_ctrl2 + } + #[doc = "0x10 - SAR ADC1 MUX register."] + #[inline(always)] + pub const fn meas1_mux(&self) -> &MEAS1_MUX { + &self.meas1_mux + } + #[doc = "0x14 - ADC1 attenuation registers."] + #[inline(always)] + pub const fn atten1(&self) -> &ATTEN1 { + &self.atten1 + } + #[doc = "0x18 - N/A"] + #[inline(always)] + pub const fn amp_ctrl1(&self) -> &_CTRL1 { + &self.amp_ctrl1 + } + #[doc = "0x1c - N/A"] + #[inline(always)] + pub const fn amp_ctrl2(&self) -> &_CTRL2 { + &self.amp_ctrl2 + } + #[doc = "0x20 - N/A"] + #[inline(always)] + pub const fn amp_ctrl3(&self) -> &_CTRL3 { + &self.amp_ctrl3 + } + #[doc = "0x24 - Control the read operation of ADC2."] + #[inline(always)] + pub const fn reader2_ctrl(&self) -> &READER2_CTRL { + &self.reader2_ctrl + } + #[doc = "0x28 - N/A"] + #[inline(always)] + pub const fn reader2_status(&self) -> &READER2_STATUS { + &self.reader2_status + } + #[doc = "0x2c - ADC2 configuration registers."] + #[inline(always)] + pub const fn meas2_ctrl1(&self) -> &MEAS2_CTRL1 { + &self.meas2_ctrl1 + } + #[doc = "0x30 - ADC2 configuration registers."] + #[inline(always)] + pub const fn meas2_ctrl2(&self) -> &MEAS2_CTRL2 { + &self.meas2_ctrl2 + } + #[doc = "0x34 - SAR ADC2 MUX register."] + #[inline(always)] + pub const fn meas2_mux(&self) -> &MEAS2_MUX { + &self.meas2_mux + } + #[doc = "0x38 - ADC1 attenuation registers."] + #[inline(always)] + pub const fn atten2(&self) -> &ATTEN2 { + &self.atten2 + } + #[doc = "0x3c - In sleep, force to use rtc to control ADC"] + #[inline(always)] + pub const fn force_wpd_sar(&self) -> &FORCE_WPD_SAR { + &self.force_wpd_sar + } + #[doc = "0x40 - N/A"] + #[inline(always)] + pub const fn meas_status(&self) -> &MEAS_STATUS { + &self.meas_status + } + #[doc = "0x44 - N/A"] + #[inline(always)] + pub const fn reg_clken(&self) -> ®_CLKEN { + &self.reg_clken + } + #[doc = "0x48 - Interrupt raw registers."] + #[inline(always)] + pub const fn cocpu_int_raw(&self) -> &COCPU_INT_RAW { + &self.cocpu_int_raw + } + #[doc = "0x4c - Interrupt enable registers."] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x50 - Interrupt status registers."] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x54 - Interrupt clear registers."] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x58 - Interrupt enable assert registers."] + #[inline(always)] + pub const fn int_ena_w1ts(&self) -> &INT_ENA_W1TS { + &self.int_ena_w1ts + } + #[doc = "0x5c - Interrupt enable deassert registers."] + #[inline(always)] + pub const fn int_ena_w1tc(&self) -> &INT_ENA_W1TC { + &self.int_ena_w1tc + } + #[doc = "0x60 - ADC1 wakeup configuration registers."] + #[inline(always)] + pub const fn wakeup1(&self) -> &WAKEUP1 { + &self.wakeup1 + } + #[doc = "0x64 - ADC2 wakeup configuration registers."] + #[inline(always)] + pub const fn wakeup2(&self) -> &WAKEUP2 { + &self.wakeup2 + } + #[doc = "0x68 - Wakeup source select register."] + #[inline(always)] + pub const fn wakeup_sel(&self) -> &WAKEUP_SEL { + &self.wakeup_sel + } + #[doc = "0x6c - Hardware automatic sampling registers for wakeup function."] + #[inline(always)] + pub const fn sar1_hw_wakeup(&self) -> &SAR1_HW_WAKEUP { + &self.sar1_hw_wakeup + } + #[doc = "0x70 - Hardware automatic sampling registers for wakeup function."] + #[inline(always)] + pub const fn sar2_hw_wakeup(&self) -> &SAR2_HW_WAKEUP { + &self.sar2_hw_wakeup + } + #[doc = "0x74 - N/A"] + #[inline(always)] + pub const fn rnd_eco_low(&self) -> &RND_ECO_LOW { + &self.rnd_eco_low + } + #[doc = "0x78 - N/A"] + #[inline(always)] + pub const fn rnd_eco_high(&self) -> &RND_ECO_HIGH { + &self.rnd_eco_high + } + #[doc = "0x7c - N/A"] + #[inline(always)] + pub const fn rnd_eco_cs(&self) -> &RND_ECO_CS { + &self.rnd_eco_cs + } +} +#[doc = "READER1_CTRL (rw) register accessor: Control the read operation of ADC1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reader1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reader1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reader1_ctrl`] module"] +pub type READER1_CTRL = crate::Reg; +#[doc = "Control the read operation of ADC1."] +pub mod reader1_ctrl; +#[doc = "READER1_STATUS (r) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reader1_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reader1_status`] module"] +pub type READER1_STATUS = crate::Reg; +#[doc = "N/A"] +pub mod reader1_status; +#[doc = "MEAS1_CTRL1 (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas1_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas1_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@meas1_ctrl1`] module"] +pub type MEAS1_CTRL1 = crate::Reg; +#[doc = "N/A"] +pub mod meas1_ctrl1; +#[doc = "MEAS1_CTRL2 (rw) register accessor: ADC1 configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas1_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas1_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@meas1_ctrl2`] module"] +pub type MEAS1_CTRL2 = crate::Reg; +#[doc = "ADC1 configuration registers."] +pub mod meas1_ctrl2; +#[doc = "MEAS1_MUX (rw) register accessor: SAR ADC1 MUX register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas1_mux::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas1_mux::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@meas1_mux`] module"] +pub type MEAS1_MUX = crate::Reg; +#[doc = "SAR ADC1 MUX register."] +pub mod meas1_mux; +#[doc = "ATTEN1 (rw) register accessor: ADC1 attenuation registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atten1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atten1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@atten1`] module"] +pub type ATTEN1 = crate::Reg; +#[doc = "ADC1 attenuation registers."] +pub mod atten1; +#[doc = "AMP_CTRL1 (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amp_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amp_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amp_ctrl1`] module"] +pub type AMP_CTRL1 = crate::Reg; +#[doc = "N/A"] +pub mod amp_ctrl1; +#[doc = "AMP_CTRL2 (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amp_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amp_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amp_ctrl2`] module"] +pub type AMP_CTRL2 = crate::Reg; +#[doc = "N/A"] +pub mod amp_ctrl2; +#[doc = "AMP_CTRL3 (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amp_ctrl3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amp_ctrl3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amp_ctrl3`] module"] +pub type AMP_CTRL3 = crate::Reg; +#[doc = "N/A"] +pub mod amp_ctrl3; +#[doc = "READER2_CTRL (rw) register accessor: Control the read operation of ADC2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reader2_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reader2_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reader2_ctrl`] module"] +pub type READER2_CTRL = crate::Reg; +#[doc = "Control the read operation of ADC2."] +pub mod reader2_ctrl; +#[doc = "READER2_STATUS (r) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reader2_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reader2_status`] module"] +pub type READER2_STATUS = crate::Reg; +#[doc = "N/A"] +pub mod reader2_status; +#[doc = "MEAS2_CTRL1 (rw) register accessor: ADC2 configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas2_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas2_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@meas2_ctrl1`] module"] +pub type MEAS2_CTRL1 = crate::Reg; +#[doc = "ADC2 configuration registers."] +pub mod meas2_ctrl1; +#[doc = "MEAS2_CTRL2 (rw) register accessor: ADC2 configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas2_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas2_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@meas2_ctrl2`] module"] +pub type MEAS2_CTRL2 = crate::Reg; +#[doc = "ADC2 configuration registers."] +pub mod meas2_ctrl2; +#[doc = "MEAS2_MUX (rw) register accessor: SAR ADC2 MUX register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas2_mux::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas2_mux::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@meas2_mux`] module"] +pub type MEAS2_MUX = crate::Reg; +#[doc = "SAR ADC2 MUX register."] +pub mod meas2_mux; +#[doc = "ATTEN2 (rw) register accessor: ADC1 attenuation registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atten2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atten2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@atten2`] module"] +pub type ATTEN2 = crate::Reg; +#[doc = "ADC1 attenuation registers."] +pub mod atten2; +#[doc = "FORCE_WPD_SAR (rw) register accessor: In sleep, force to use rtc to control ADC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`force_wpd_sar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`force_wpd_sar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@force_wpd_sar`] module"] +pub type FORCE_WPD_SAR = crate::Reg; +#[doc = "In sleep, force to use rtc to control ADC"] +pub mod force_wpd_sar; +#[doc = "MEAS_STATUS (r) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@meas_status`] module"] +pub type MEAS_STATUS = crate::Reg; +#[doc = "N/A"] +pub mod meas_status; +#[doc = "REG_CLKEN (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_clken::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_clken::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_clken`] module"] +pub type REG_CLKEN = crate::Reg; +#[doc = "N/A"] +pub mod reg_clken; +#[doc = "COCPU_INT_RAW (rw) register accessor: Interrupt raw registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cocpu_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cocpu_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cocpu_int_raw`] module"] +pub type COCPU_INT_RAW = crate::Reg; +#[doc = "Interrupt raw registers."] +pub mod cocpu_int_raw; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable registers."] +pub mod int_ena; +#[doc = "INT_ST (r) register accessor: Interrupt status registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Interrupt status registers."] +pub mod int_st; +#[doc = "INT_CLR (w) register accessor: Interrupt clear registers.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear registers."] +pub mod int_clr; +#[doc = "INT_ENA_W1TS (w) register accessor: Interrupt enable assert registers.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena_w1ts`] module"] +pub type INT_ENA_W1TS = crate::Reg; +#[doc = "Interrupt enable assert registers."] +pub mod int_ena_w1ts; +#[doc = "INT_ENA_W1TC (w) register accessor: Interrupt enable deassert registers.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena_w1tc`] module"] +pub type INT_ENA_W1TC = crate::Reg; +#[doc = "Interrupt enable deassert registers."] +pub mod int_ena_w1tc; +#[doc = "WAKEUP1 (rw) register accessor: ADC1 wakeup configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeup1`] module"] +pub type WAKEUP1 = crate::Reg; +#[doc = "ADC1 wakeup configuration registers."] +pub mod wakeup1; +#[doc = "WAKEUP2 (rw) register accessor: ADC2 wakeup configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeup2`] module"] +pub type WAKEUP2 = crate::Reg; +#[doc = "ADC2 wakeup configuration registers."] +pub mod wakeup2; +#[doc = "WAKEUP_SEL (rw) register accessor: Wakeup source select register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeup_sel`] module"] +pub type WAKEUP_SEL = crate::Reg; +#[doc = "Wakeup source select register."] +pub mod wakeup_sel; +#[doc = "SAR1_HW_WAKEUP (rw) register accessor: Hardware automatic sampling registers for wakeup function.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_hw_wakeup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar1_hw_wakeup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar1_hw_wakeup`] module"] +pub type SAR1_HW_WAKEUP = crate::Reg; +#[doc = "Hardware automatic sampling registers for wakeup function."] +pub mod sar1_hw_wakeup; +#[doc = "SAR2_HW_WAKEUP (rw) register accessor: Hardware automatic sampling registers for wakeup function.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_hw_wakeup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar2_hw_wakeup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar2_hw_wakeup`] module"] +pub type SAR2_HW_WAKEUP = crate::Reg; +#[doc = "Hardware automatic sampling registers for wakeup function."] +pub mod sar2_hw_wakeup; +#[doc = "RND_ECO_LOW (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_low`] module"] +pub type RND_ECO_LOW = crate::Reg; +#[doc = "N/A"] +pub mod rnd_eco_low; +#[doc = "RND_ECO_HIGH (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_high`] module"] +pub type RND_ECO_HIGH = crate::Reg; +#[doc = "N/A"] +pub mod rnd_eco_high; +#[doc = "RND_ECO_CS (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_cs`] module"] +pub type RND_ECO_CS = crate::Reg; +#[doc = "N/A"] +pub mod rnd_eco_cs; diff --git a/esp32p4/src/lp_adc/amp_ctrl1.rs b/esp32p4/src/lp_adc/amp_ctrl1.rs new file mode 100644 index 0000000000..b5fd3da5de --- /dev/null +++ b/esp32p4/src/lp_adc/amp_ctrl1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `AMP_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `AMP_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `SAR_AMP_WAIT1` reader - N/A"] +pub type SAR_AMP_WAIT1_R = crate::FieldReader; +#[doc = "Field `SAR_AMP_WAIT1` writer - N/A"] +pub type SAR_AMP_WAIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SAR_AMP_WAIT2` reader - N/A"] +pub type SAR_AMP_WAIT2_R = crate::FieldReader; +#[doc = "Field `SAR_AMP_WAIT2` writer - N/A"] +pub type SAR_AMP_WAIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - N/A"] + #[inline(always)] + pub fn sar_amp_wait1(&self) -> SAR_AMP_WAIT1_R { + SAR_AMP_WAIT1_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - N/A"] + #[inline(always)] + pub fn sar_amp_wait2(&self) -> SAR_AMP_WAIT2_R { + SAR_AMP_WAIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AMP_CTRL1") + .field( + "sar_amp_wait1", + &format_args!("{}", self.sar_amp_wait1().bits()), + ) + .field( + "sar_amp_wait2", + &format_args!("{}", self.sar_amp_wait2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar_amp_wait1(&mut self) -> SAR_AMP_WAIT1_W { + SAR_AMP_WAIT1_W::new(self, 0) + } + #[doc = "Bits 16:31 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar_amp_wait2(&mut self) -> SAR_AMP_WAIT2_W { + SAR_AMP_WAIT2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amp_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amp_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AMP_CTRL1_SPEC; +impl crate::RegisterSpec for AMP_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`amp_ctrl1::R`](R) reader structure"] +impl crate::Readable for AMP_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`amp_ctrl1::W`](W) writer structure"] +impl crate::Writable for AMP_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AMP_CTRL1 to value 0x000a_000a"] +impl crate::Resettable for AMP_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0x000a_000a; +} diff --git a/esp32p4/src/lp_adc/amp_ctrl2.rs b/esp32p4/src/lp_adc/amp_ctrl2.rs new file mode 100644 index 0000000000..3621f73491 --- /dev/null +++ b/esp32p4/src/lp_adc/amp_ctrl2.rs @@ -0,0 +1,199 @@ +#[doc = "Register `AMP_CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `AMP_CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `SAR1_DAC_XPD_FSM_IDLE` reader - N/A"] +pub type SAR1_DAC_XPD_FSM_IDLE_R = crate::BitReader; +#[doc = "Field `SAR1_DAC_XPD_FSM_IDLE` writer - N/A"] +pub type SAR1_DAC_XPD_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XPD_SAR_AMP_FSM_IDLE` reader - N/A"] +pub type XPD_SAR_AMP_FSM_IDLE_R = crate::BitReader; +#[doc = "Field `XPD_SAR_AMP_FSM_IDLE` writer - N/A"] +pub type XPD_SAR_AMP_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AMP_RST_FB_FSM_IDLE` reader - N/A"] +pub type AMP_RST_FB_FSM_IDLE_R = crate::BitReader; +#[doc = "Field `AMP_RST_FB_FSM_IDLE` writer - N/A"] +pub type AMP_RST_FB_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AMP_SHORT_REF_FSM_IDLE` reader - N/A"] +pub type AMP_SHORT_REF_FSM_IDLE_R = crate::BitReader; +#[doc = "Field `AMP_SHORT_REF_FSM_IDLE` writer - N/A"] +pub type AMP_SHORT_REF_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AMP_SHORT_REF_GND_FSM_IDLE` reader - N/A"] +pub type AMP_SHORT_REF_GND_FSM_IDLE_R = crate::BitReader; +#[doc = "Field `AMP_SHORT_REF_GND_FSM_IDLE` writer - N/A"] +pub type AMP_SHORT_REF_GND_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XPD_SAR_FSM_IDLE` reader - N/A"] +pub type XPD_SAR_FSM_IDLE_R = crate::BitReader; +#[doc = "Field `XPD_SAR_FSM_IDLE` writer - N/A"] +pub type XPD_SAR_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_RSTB_FSM_IDLE` reader - N/A"] +pub type SAR_RSTB_FSM_IDLE_R = crate::BitReader; +#[doc = "Field `SAR_RSTB_FSM_IDLE` writer - N/A"] +pub type SAR_RSTB_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR_AMP_WAIT3` reader - N/A"] +pub type SAR_AMP_WAIT3_R = crate::FieldReader; +#[doc = "Field `SAR_AMP_WAIT3` writer - N/A"] +pub type SAR_AMP_WAIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + pub fn sar1_dac_xpd_fsm_idle(&self) -> SAR1_DAC_XPD_FSM_IDLE_R { + SAR1_DAC_XPD_FSM_IDLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + pub fn xpd_sar_amp_fsm_idle(&self) -> XPD_SAR_AMP_FSM_IDLE_R { + XPD_SAR_AMP_FSM_IDLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - N/A"] + #[inline(always)] + pub fn amp_rst_fb_fsm_idle(&self) -> AMP_RST_FB_FSM_IDLE_R { + AMP_RST_FB_FSM_IDLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - N/A"] + #[inline(always)] + pub fn amp_short_ref_fsm_idle(&self) -> AMP_SHORT_REF_FSM_IDLE_R { + AMP_SHORT_REF_FSM_IDLE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - N/A"] + #[inline(always)] + pub fn amp_short_ref_gnd_fsm_idle(&self) -> AMP_SHORT_REF_GND_FSM_IDLE_R { + AMP_SHORT_REF_GND_FSM_IDLE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - N/A"] + #[inline(always)] + pub fn xpd_sar_fsm_idle(&self) -> XPD_SAR_FSM_IDLE_R { + XPD_SAR_FSM_IDLE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - N/A"] + #[inline(always)] + pub fn sar_rstb_fsm_idle(&self) -> SAR_RSTB_FSM_IDLE_R { + SAR_RSTB_FSM_IDLE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 16:31 - N/A"] + #[inline(always)] + pub fn sar_amp_wait3(&self) -> SAR_AMP_WAIT3_R { + SAR_AMP_WAIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AMP_CTRL2") + .field( + "sar1_dac_xpd_fsm_idle", + &format_args!("{}", self.sar1_dac_xpd_fsm_idle().bit()), + ) + .field( + "xpd_sar_amp_fsm_idle", + &format_args!("{}", self.xpd_sar_amp_fsm_idle().bit()), + ) + .field( + "amp_rst_fb_fsm_idle", + &format_args!("{}", self.amp_rst_fb_fsm_idle().bit()), + ) + .field( + "amp_short_ref_fsm_idle", + &format_args!("{}", self.amp_short_ref_fsm_idle().bit()), + ) + .field( + "amp_short_ref_gnd_fsm_idle", + &format_args!("{}", self.amp_short_ref_gnd_fsm_idle().bit()), + ) + .field( + "xpd_sar_fsm_idle", + &format_args!("{}", self.xpd_sar_fsm_idle().bit()), + ) + .field( + "sar_rstb_fsm_idle", + &format_args!("{}", self.sar_rstb_fsm_idle().bit()), + ) + .field( + "sar_amp_wait3", + &format_args!("{}", self.sar_amp_wait3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar1_dac_xpd_fsm_idle(&mut self) -> SAR1_DAC_XPD_FSM_IDLE_W { + SAR1_DAC_XPD_FSM_IDLE_W::new(self, 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + #[must_use] + pub fn xpd_sar_amp_fsm_idle(&mut self) -> XPD_SAR_AMP_FSM_IDLE_W { + XPD_SAR_AMP_FSM_IDLE_W::new(self, 1) + } + #[doc = "Bit 2 - N/A"] + #[inline(always)] + #[must_use] + pub fn amp_rst_fb_fsm_idle(&mut self) -> AMP_RST_FB_FSM_IDLE_W { + AMP_RST_FB_FSM_IDLE_W::new(self, 2) + } + #[doc = "Bit 3 - N/A"] + #[inline(always)] + #[must_use] + pub fn amp_short_ref_fsm_idle(&mut self) -> AMP_SHORT_REF_FSM_IDLE_W { + AMP_SHORT_REF_FSM_IDLE_W::new(self, 3) + } + #[doc = "Bit 4 - N/A"] + #[inline(always)] + #[must_use] + pub fn amp_short_ref_gnd_fsm_idle(&mut self) -> AMP_SHORT_REF_GND_FSM_IDLE_W { + AMP_SHORT_REF_GND_FSM_IDLE_W::new(self, 4) + } + #[doc = "Bit 5 - N/A"] + #[inline(always)] + #[must_use] + pub fn xpd_sar_fsm_idle(&mut self) -> XPD_SAR_FSM_IDLE_W { + XPD_SAR_FSM_IDLE_W::new(self, 5) + } + #[doc = "Bit 6 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar_rstb_fsm_idle(&mut self) -> SAR_RSTB_FSM_IDLE_W { + SAR_RSTB_FSM_IDLE_W::new(self, 6) + } + #[doc = "Bits 16:31 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar_amp_wait3(&mut self) -> SAR_AMP_WAIT3_W { + SAR_AMP_WAIT3_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amp_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amp_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AMP_CTRL2_SPEC; +impl crate::RegisterSpec for AMP_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`amp_ctrl2::R`](R) reader structure"] +impl crate::Readable for AMP_CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`amp_ctrl2::W`](W) writer structure"] +impl crate::Writable for AMP_CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AMP_CTRL2 to value 0x000a_0000"] +impl crate::Resettable for AMP_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0x000a_0000; +} diff --git a/esp32p4/src/lp_adc/amp_ctrl3.rs b/esp32p4/src/lp_adc/amp_ctrl3.rs new file mode 100644 index 0000000000..b372305f1e --- /dev/null +++ b/esp32p4/src/lp_adc/amp_ctrl3.rs @@ -0,0 +1,180 @@ +#[doc = "Register `AMP_CTRL3` reader"] +pub type R = crate::R; +#[doc = "Register `AMP_CTRL3` writer"] +pub type W = crate::W; +#[doc = "Field `SAR1_DAC_XPD_FSM` reader - N/A"] +pub type SAR1_DAC_XPD_FSM_R = crate::FieldReader; +#[doc = "Field `SAR1_DAC_XPD_FSM` writer - N/A"] +pub type SAR1_DAC_XPD_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `XPD_SAR_AMP_FSM` reader - N/A"] +pub type XPD_SAR_AMP_FSM_R = crate::FieldReader; +#[doc = "Field `XPD_SAR_AMP_FSM` writer - N/A"] +pub type XPD_SAR_AMP_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `AMP_RST_FB_FSM` reader - N/A"] +pub type AMP_RST_FB_FSM_R = crate::FieldReader; +#[doc = "Field `AMP_RST_FB_FSM` writer - N/A"] +pub type AMP_RST_FB_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `AMP_SHORT_REF_FSM` reader - N/A"] +pub type AMP_SHORT_REF_FSM_R = crate::FieldReader; +#[doc = "Field `AMP_SHORT_REF_FSM` writer - N/A"] +pub type AMP_SHORT_REF_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `AMP_SHORT_REF_GND_FSM` reader - N/A"] +pub type AMP_SHORT_REF_GND_FSM_R = crate::FieldReader; +#[doc = "Field `AMP_SHORT_REF_GND_FSM` writer - N/A"] +pub type AMP_SHORT_REF_GND_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `XPD_SAR_FSM` reader - N/A"] +pub type XPD_SAR_FSM_R = crate::FieldReader; +#[doc = "Field `XPD_SAR_FSM` writer - N/A"] +pub type XPD_SAR_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SAR_RSTB_FSM` reader - N/A"] +pub type SAR_RSTB_FSM_R = crate::FieldReader; +#[doc = "Field `SAR_RSTB_FSM` writer - N/A"] +pub type SAR_RSTB_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - N/A"] + #[inline(always)] + pub fn sar1_dac_xpd_fsm(&self) -> SAR1_DAC_XPD_FSM_R { + SAR1_DAC_XPD_FSM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - N/A"] + #[inline(always)] + pub fn xpd_sar_amp_fsm(&self) -> XPD_SAR_AMP_FSM_R { + XPD_SAR_AMP_FSM_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - N/A"] + #[inline(always)] + pub fn amp_rst_fb_fsm(&self) -> AMP_RST_FB_FSM_R { + AMP_RST_FB_FSM_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - N/A"] + #[inline(always)] + pub fn amp_short_ref_fsm(&self) -> AMP_SHORT_REF_FSM_R { + AMP_SHORT_REF_FSM_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - N/A"] + #[inline(always)] + pub fn amp_short_ref_gnd_fsm(&self) -> AMP_SHORT_REF_GND_FSM_R { + AMP_SHORT_REF_GND_FSM_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - N/A"] + #[inline(always)] + pub fn xpd_sar_fsm(&self) -> XPD_SAR_FSM_R { + XPD_SAR_FSM_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - N/A"] + #[inline(always)] + pub fn sar_rstb_fsm(&self) -> SAR_RSTB_FSM_R { + SAR_RSTB_FSM_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AMP_CTRL3") + .field( + "sar1_dac_xpd_fsm", + &format_args!("{}", self.sar1_dac_xpd_fsm().bits()), + ) + .field( + "xpd_sar_amp_fsm", + &format_args!("{}", self.xpd_sar_amp_fsm().bits()), + ) + .field( + "amp_rst_fb_fsm", + &format_args!("{}", self.amp_rst_fb_fsm().bits()), + ) + .field( + "amp_short_ref_fsm", + &format_args!("{}", self.amp_short_ref_fsm().bits()), + ) + .field( + "amp_short_ref_gnd_fsm", + &format_args!("{}", self.amp_short_ref_gnd_fsm().bits()), + ) + .field( + "xpd_sar_fsm", + &format_args!("{}", self.xpd_sar_fsm().bits()), + ) + .field( + "sar_rstb_fsm", + &format_args!("{}", self.sar_rstb_fsm().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar1_dac_xpd_fsm(&mut self) -> SAR1_DAC_XPD_FSM_W { + SAR1_DAC_XPD_FSM_W::new(self, 0) + } + #[doc = "Bits 4:7 - N/A"] + #[inline(always)] + #[must_use] + pub fn xpd_sar_amp_fsm(&mut self) -> XPD_SAR_AMP_FSM_W { + XPD_SAR_AMP_FSM_W::new(self, 4) + } + #[doc = "Bits 8:11 - N/A"] + #[inline(always)] + #[must_use] + pub fn amp_rst_fb_fsm(&mut self) -> AMP_RST_FB_FSM_W { + AMP_RST_FB_FSM_W::new(self, 8) + } + #[doc = "Bits 12:15 - N/A"] + #[inline(always)] + #[must_use] + pub fn amp_short_ref_fsm(&mut self) -> AMP_SHORT_REF_FSM_W { + AMP_SHORT_REF_FSM_W::new(self, 12) + } + #[doc = "Bits 16:19 - N/A"] + #[inline(always)] + #[must_use] + pub fn amp_short_ref_gnd_fsm(&mut self) -> AMP_SHORT_REF_GND_FSM_W { + AMP_SHORT_REF_GND_FSM_W::new(self, 16) + } + #[doc = "Bits 20:23 - N/A"] + #[inline(always)] + #[must_use] + pub fn xpd_sar_fsm(&mut self) -> XPD_SAR_FSM_W { + XPD_SAR_FSM_W::new(self, 20) + } + #[doc = "Bits 24:27 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar_rstb_fsm(&mut self) -> SAR_RSTB_FSM_W { + SAR_RSTB_FSM_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amp_ctrl3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amp_ctrl3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AMP_CTRL3_SPEC; +impl crate::RegisterSpec for AMP_CTRL3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`amp_ctrl3::R`](R) reader structure"] +impl crate::Readable for AMP_CTRL3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`amp_ctrl3::W`](W) writer structure"] +impl crate::Writable for AMP_CTRL3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AMP_CTRL3 to value 0x0073_38f3"] +impl crate::Resettable for AMP_CTRL3_SPEC { + const RESET_VALUE: Self::Ux = 0x0073_38f3; +} diff --git a/esp32p4/src/lp_adc/atten1.rs b/esp32p4/src/lp_adc/atten1.rs new file mode 100644 index 0000000000..a9625fdf92 --- /dev/null +++ b/esp32p4/src/lp_adc/atten1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ATTEN1` reader"] +pub type R = crate::R; +#[doc = "Register `ATTEN1` writer"] +pub type W = crate::W; +#[doc = "Field `SAR1_ATTEN` reader - 2-bit attenuation for each pad."] +pub type SAR1_ATTEN_R = crate::FieldReader; +#[doc = "Field `SAR1_ATTEN` writer - 2-bit attenuation for each pad."] +pub type SAR1_ATTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - 2-bit attenuation for each pad."] + #[inline(always)] + pub fn sar1_atten(&self) -> SAR1_ATTEN_R { + SAR1_ATTEN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ATTEN1") + .field("sar1_atten", &format_args!("{}", self.sar1_atten().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - 2-bit attenuation for each pad."] + #[inline(always)] + #[must_use] + pub fn sar1_atten(&mut self) -> SAR1_ATTEN_W { + SAR1_ATTEN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ADC1 attenuation registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atten1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atten1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ATTEN1_SPEC; +impl crate::RegisterSpec for ATTEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`atten1::R`](R) reader structure"] +impl crate::Readable for ATTEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`atten1::W`](W) writer structure"] +impl crate::Writable for ATTEN1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ATTEN1 to value 0xffff_ffff"] +impl crate::Resettable for ATTEN1_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_adc/atten2.rs b/esp32p4/src/lp_adc/atten2.rs new file mode 100644 index 0000000000..a85beb1ea8 --- /dev/null +++ b/esp32p4/src/lp_adc/atten2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ATTEN2` reader"] +pub type R = crate::R; +#[doc = "Register `ATTEN2` writer"] +pub type W = crate::W; +#[doc = "Field `SAR2_ATTEN` reader - 2-bit attenuation for each pad."] +pub type SAR2_ATTEN_R = crate::FieldReader; +#[doc = "Field `SAR2_ATTEN` writer - 2-bit attenuation for each pad."] +pub type SAR2_ATTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - 2-bit attenuation for each pad."] + #[inline(always)] + pub fn sar2_atten(&self) -> SAR2_ATTEN_R { + SAR2_ATTEN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ATTEN2") + .field("sar2_atten", &format_args!("{}", self.sar2_atten().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - 2-bit attenuation for each pad."] + #[inline(always)] + #[must_use] + pub fn sar2_atten(&mut self) -> SAR2_ATTEN_W { + SAR2_ATTEN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ADC1 attenuation registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atten2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atten2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ATTEN2_SPEC; +impl crate::RegisterSpec for ATTEN2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`atten2::R`](R) reader structure"] +impl crate::Readable for ATTEN2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`atten2::W`](W) writer structure"] +impl crate::Writable for ATTEN2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ATTEN2 to value 0xffff_ffff"] +impl crate::Resettable for ATTEN2_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_adc/cocpu_int_raw.rs b/esp32p4/src/lp_adc/cocpu_int_raw.rs new file mode 100644 index 0000000000..edbe81c35b --- /dev/null +++ b/esp32p4/src/lp_adc/cocpu_int_raw.rs @@ -0,0 +1,169 @@ +#[doc = "Register `COCPU_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `COCPU_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `COCPU_SARADC1_INT_RAW` reader - ADC1 Conversion is done, int raw."] +pub type COCPU_SARADC1_INT_RAW_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC1_INT_RAW` writer - ADC1 Conversion is done, int raw."] +pub type COCPU_SARADC1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_INT_RAW` reader - ADC2 Conversion is done, int raw."] +pub type COCPU_SARADC2_INT_RAW_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC2_INT_RAW` writer - ADC2 Conversion is done, int raw."] +pub type COCPU_SARADC2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC1_ERROR_INT_RAW` reader - An errro occurs from ADC1, int raw."] +pub type COCPU_SARADC1_ERROR_INT_RAW_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC1_ERROR_INT_RAW` writer - An errro occurs from ADC1, int raw."] +pub type COCPU_SARADC1_ERROR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_ERROR_INT_RAW` reader - An errro occurs from ADC2, int raw."] +pub type COCPU_SARADC2_ERROR_INT_RAW_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC2_ERROR_INT_RAW` writer - An errro occurs from ADC2, int raw."] +pub type COCPU_SARADC2_ERROR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC1_WAKE_INT_RAW` reader - A wakeup event is triggered from ADC1, int raw."] +pub type COCPU_SARADC1_WAKE_INT_RAW_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC1_WAKE_INT_RAW` writer - A wakeup event is triggered from ADC1, int raw."] +pub type COCPU_SARADC1_WAKE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_WAKE_INT_RAW` reader - A wakeup event is triggered from ADC2, int raw."] +pub type COCPU_SARADC2_WAKE_INT_RAW_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC2_WAKE_INT_RAW` writer - A wakeup event is triggered from ADC2, int raw."] +pub type COCPU_SARADC2_WAKE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - ADC1 Conversion is done, int raw."] + #[inline(always)] + pub fn cocpu_saradc1_int_raw(&self) -> COCPU_SARADC1_INT_RAW_R { + COCPU_SARADC1_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ADC2 Conversion is done, int raw."] + #[inline(always)] + pub fn cocpu_saradc2_int_raw(&self) -> COCPU_SARADC2_INT_RAW_R { + COCPU_SARADC2_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - An errro occurs from ADC1, int raw."] + #[inline(always)] + pub fn cocpu_saradc1_error_int_raw(&self) -> COCPU_SARADC1_ERROR_INT_RAW_R { + COCPU_SARADC1_ERROR_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - An errro occurs from ADC2, int raw."] + #[inline(always)] + pub fn cocpu_saradc2_error_int_raw(&self) -> COCPU_SARADC2_ERROR_INT_RAW_R { + COCPU_SARADC2_ERROR_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - A wakeup event is triggered from ADC1, int raw."] + #[inline(always)] + pub fn cocpu_saradc1_wake_int_raw(&self) -> COCPU_SARADC1_WAKE_INT_RAW_R { + COCPU_SARADC1_WAKE_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - A wakeup event is triggered from ADC2, int raw."] + #[inline(always)] + pub fn cocpu_saradc2_wake_int_raw(&self) -> COCPU_SARADC2_WAKE_INT_RAW_R { + COCPU_SARADC2_WAKE_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COCPU_INT_RAW") + .field( + "cocpu_saradc1_int_raw", + &format_args!("{}", self.cocpu_saradc1_int_raw().bit()), + ) + .field( + "cocpu_saradc2_int_raw", + &format_args!("{}", self.cocpu_saradc2_int_raw().bit()), + ) + .field( + "cocpu_saradc1_error_int_raw", + &format_args!("{}", self.cocpu_saradc1_error_int_raw().bit()), + ) + .field( + "cocpu_saradc2_error_int_raw", + &format_args!("{}", self.cocpu_saradc2_error_int_raw().bit()), + ) + .field( + "cocpu_saradc1_wake_int_raw", + &format_args!("{}", self.cocpu_saradc1_wake_int_raw().bit()), + ) + .field( + "cocpu_saradc2_wake_int_raw", + &format_args!("{}", self.cocpu_saradc2_wake_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - ADC1 Conversion is done, int raw."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_int_raw(&mut self) -> COCPU_SARADC1_INT_RAW_W { + COCPU_SARADC1_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - ADC2 Conversion is done, int raw."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_int_raw(&mut self) -> COCPU_SARADC2_INT_RAW_W { + COCPU_SARADC2_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - An errro occurs from ADC1, int raw."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_error_int_raw( + &mut self, + ) -> COCPU_SARADC1_ERROR_INT_RAW_W { + COCPU_SARADC1_ERROR_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - An errro occurs from ADC2, int raw."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_error_int_raw( + &mut self, + ) -> COCPU_SARADC2_ERROR_INT_RAW_W { + COCPU_SARADC2_ERROR_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - A wakeup event is triggered from ADC1, int raw."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_wake_int_raw( + &mut self, + ) -> COCPU_SARADC1_WAKE_INT_RAW_W { + COCPU_SARADC1_WAKE_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - A wakeup event is triggered from ADC2, int raw."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_wake_int_raw( + &mut self, + ) -> COCPU_SARADC2_WAKE_INT_RAW_W { + COCPU_SARADC2_WAKE_INT_RAW_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt raw registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cocpu_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cocpu_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COCPU_INT_RAW_SPEC; +impl crate::RegisterSpec for COCPU_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cocpu_int_raw::R`](R) reader structure"] +impl crate::Readable for COCPU_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cocpu_int_raw::W`](W) writer structure"] +impl crate::Writable for COCPU_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COCPU_INT_RAW to value 0"] +impl crate::Resettable for COCPU_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/force_wpd_sar.rs b/esp32p4/src/lp_adc/force_wpd_sar.rs new file mode 100644 index 0000000000..4ee464eda0 --- /dev/null +++ b/esp32p4/src/lp_adc/force_wpd_sar.rs @@ -0,0 +1,85 @@ +#[doc = "Register `FORCE_WPD_SAR` reader"] +pub type R = crate::R; +#[doc = "Register `FORCE_WPD_SAR` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_XPD_SAR1` reader - 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control."] +pub type FORCE_XPD_SAR1_R = crate::FieldReader; +#[doc = "Field `FORCE_XPD_SAR1` writer - 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control."] +pub type FORCE_XPD_SAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `FORCE_XPD_SAR2` reader - 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control."] +pub type FORCE_XPD_SAR2_R = crate::FieldReader; +#[doc = "Field `FORCE_XPD_SAR2` writer - 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control."] +pub type FORCE_XPD_SAR2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control."] + #[inline(always)] + pub fn force_xpd_sar1(&self) -> FORCE_XPD_SAR1_R { + FORCE_XPD_SAR1_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control."] + #[inline(always)] + pub fn force_xpd_sar2(&self) -> FORCE_XPD_SAR2_R { + FORCE_XPD_SAR2_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FORCE_WPD_SAR") + .field( + "force_xpd_sar1", + &format_args!("{}", self.force_xpd_sar1().bits()), + ) + .field( + "force_xpd_sar2", + &format_args!("{}", self.force_xpd_sar2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control."] + #[inline(always)] + #[must_use] + pub fn force_xpd_sar1(&mut self) -> FORCE_XPD_SAR1_W { + FORCE_XPD_SAR1_W::new(self, 0) + } + #[doc = "Bits 2:3 - 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control."] + #[inline(always)] + #[must_use] + pub fn force_xpd_sar2(&mut self) -> FORCE_XPD_SAR2_W { + FORCE_XPD_SAR2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "In sleep, force to use rtc to control ADC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`force_wpd_sar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`force_wpd_sar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FORCE_WPD_SAR_SPEC; +impl crate::RegisterSpec for FORCE_WPD_SAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`force_wpd_sar::R`](R) reader structure"] +impl crate::Readable for FORCE_WPD_SAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`force_wpd_sar::W`](W) writer structure"] +impl crate::Writable for FORCE_WPD_SAR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FORCE_WPD_SAR to value 0"] +impl crate::Resettable for FORCE_WPD_SAR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/int_clr.rs b/esp32p4/src/lp_adc/int_clr.rs new file mode 100644 index 0000000000..5370d2718d --- /dev/null +++ b/esp32p4/src/lp_adc/int_clr.rs @@ -0,0 +1,82 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `COCPU_SARADC1_INT_CLR` writer - ADC1 Conversion is done, int clear."] +pub type COCPU_SARADC1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_INT_CLR` writer - ADC2 Conversion is done, int clear."] +pub type COCPU_SARADC2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC1_ERROR_INT_CLR` writer - An errro occurs from ADC1, int clear."] +pub type COCPU_SARADC1_ERROR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_ERROR_INT_CLR` writer - An errro occurs from ADC2, int clear."] +pub type COCPU_SARADC2_ERROR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC1_WAKE_INT_CLR` writer - A wakeup event is triggered from ADC1, int clear."] +pub type COCPU_SARADC1_WAKE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_WAKE_INT_CLR` writer - A wakeup event is triggered from ADC2, int clear."] +pub type COCPU_SARADC2_WAKE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - ADC1 Conversion is done, int clear."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_int_clr(&mut self) -> COCPU_SARADC1_INT_CLR_W { + COCPU_SARADC1_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - ADC2 Conversion is done, int clear."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_int_clr(&mut self) -> COCPU_SARADC2_INT_CLR_W { + COCPU_SARADC2_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - An errro occurs from ADC1, int clear."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_error_int_clr(&mut self) -> COCPU_SARADC1_ERROR_INT_CLR_W { + COCPU_SARADC1_ERROR_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - An errro occurs from ADC2, int clear."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_error_int_clr(&mut self) -> COCPU_SARADC2_ERROR_INT_CLR_W { + COCPU_SARADC2_ERROR_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - A wakeup event is triggered from ADC1, int clear."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_wake_int_clr(&mut self) -> COCPU_SARADC1_WAKE_INT_CLR_W { + COCPU_SARADC1_WAKE_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - A wakeup event is triggered from ADC2, int clear."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_wake_int_clr(&mut self) -> COCPU_SARADC2_WAKE_INT_CLR_W { + COCPU_SARADC2_WAKE_INT_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear registers.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/int_ena.rs b/esp32p4/src/lp_adc/int_ena.rs new file mode 100644 index 0000000000..cfd38892a7 --- /dev/null +++ b/esp32p4/src/lp_adc/int_ena.rs @@ -0,0 +1,161 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `COCPU_SARADC1_INT_ENA` reader - ADC1 Conversion is done, int enable."] +pub type COCPU_SARADC1_INT_ENA_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC1_INT_ENA` writer - ADC1 Conversion is done, int enable."] +pub type COCPU_SARADC1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_INT_ENA` reader - ADC2 Conversion is done, int enable."] +pub type COCPU_SARADC2_INT_ENA_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC2_INT_ENA` writer - ADC2 Conversion is done, int enable."] +pub type COCPU_SARADC2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC1_ERROR_INT_ENA` reader - An errro occurs from ADC1, int enable."] +pub type COCPU_SARADC1_ERROR_INT_ENA_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC1_ERROR_INT_ENA` writer - An errro occurs from ADC1, int enable."] +pub type COCPU_SARADC1_ERROR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_ERROR_INT_ENA` reader - An errro occurs from ADC2, int enable."] +pub type COCPU_SARADC2_ERROR_INT_ENA_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC2_ERROR_INT_ENA` writer - An errro occurs from ADC2, int enable."] +pub type COCPU_SARADC2_ERROR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC1_WAKE_INT_ENA` reader - A wakeup event is triggered from ADC1, int enable."] +pub type COCPU_SARADC1_WAKE_INT_ENA_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC1_WAKE_INT_ENA` writer - A wakeup event is triggered from ADC1, int enable."] +pub type COCPU_SARADC1_WAKE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_WAKE_INT_ENA` reader - A wakeup event is triggered from ADC2, int enable."] +pub type COCPU_SARADC2_WAKE_INT_ENA_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC2_WAKE_INT_ENA` writer - A wakeup event is triggered from ADC2, int enable."] +pub type COCPU_SARADC2_WAKE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - ADC1 Conversion is done, int enable."] + #[inline(always)] + pub fn cocpu_saradc1_int_ena(&self) -> COCPU_SARADC1_INT_ENA_R { + COCPU_SARADC1_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ADC2 Conversion is done, int enable."] + #[inline(always)] + pub fn cocpu_saradc2_int_ena(&self) -> COCPU_SARADC2_INT_ENA_R { + COCPU_SARADC2_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - An errro occurs from ADC1, int enable."] + #[inline(always)] + pub fn cocpu_saradc1_error_int_ena(&self) -> COCPU_SARADC1_ERROR_INT_ENA_R { + COCPU_SARADC1_ERROR_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - An errro occurs from ADC2, int enable."] + #[inline(always)] + pub fn cocpu_saradc2_error_int_ena(&self) -> COCPU_SARADC2_ERROR_INT_ENA_R { + COCPU_SARADC2_ERROR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - A wakeup event is triggered from ADC1, int enable."] + #[inline(always)] + pub fn cocpu_saradc1_wake_int_ena(&self) -> COCPU_SARADC1_WAKE_INT_ENA_R { + COCPU_SARADC1_WAKE_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - A wakeup event is triggered from ADC2, int enable."] + #[inline(always)] + pub fn cocpu_saradc2_wake_int_ena(&self) -> COCPU_SARADC2_WAKE_INT_ENA_R { + COCPU_SARADC2_WAKE_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "cocpu_saradc1_int_ena", + &format_args!("{}", self.cocpu_saradc1_int_ena().bit()), + ) + .field( + "cocpu_saradc2_int_ena", + &format_args!("{}", self.cocpu_saradc2_int_ena().bit()), + ) + .field( + "cocpu_saradc1_error_int_ena", + &format_args!("{}", self.cocpu_saradc1_error_int_ena().bit()), + ) + .field( + "cocpu_saradc2_error_int_ena", + &format_args!("{}", self.cocpu_saradc2_error_int_ena().bit()), + ) + .field( + "cocpu_saradc1_wake_int_ena", + &format_args!("{}", self.cocpu_saradc1_wake_int_ena().bit()), + ) + .field( + "cocpu_saradc2_wake_int_ena", + &format_args!("{}", self.cocpu_saradc2_wake_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - ADC1 Conversion is done, int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_int_ena(&mut self) -> COCPU_SARADC1_INT_ENA_W { + COCPU_SARADC1_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - ADC2 Conversion is done, int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_int_ena(&mut self) -> COCPU_SARADC2_INT_ENA_W { + COCPU_SARADC2_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - An errro occurs from ADC1, int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_error_int_ena(&mut self) -> COCPU_SARADC1_ERROR_INT_ENA_W { + COCPU_SARADC1_ERROR_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - An errro occurs from ADC2, int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_error_int_ena(&mut self) -> COCPU_SARADC2_ERROR_INT_ENA_W { + COCPU_SARADC2_ERROR_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - A wakeup event is triggered from ADC1, int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_wake_int_ena(&mut self) -> COCPU_SARADC1_WAKE_INT_ENA_W { + COCPU_SARADC1_WAKE_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - A wakeup event is triggered from ADC2, int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_wake_int_ena(&mut self) -> COCPU_SARADC2_WAKE_INT_ENA_W { + COCPU_SARADC2_WAKE_INT_ENA_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/int_ena_w1tc.rs b/esp32p4/src/lp_adc/int_ena_w1tc.rs new file mode 100644 index 0000000000..d5c4291a4b --- /dev/null +++ b/esp32p4/src/lp_adc/int_ena_w1tc.rs @@ -0,0 +1,94 @@ +#[doc = "Register `INT_ENA_W1TC` writer"] +pub type W = crate::W; +#[doc = "Field `COCPU_SARADC1_INT_ENA_W1TC` writer - ADC1 Conversion is done, write 1 to deassert int enable."] +pub type COCPU_SARADC1_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_INT_ENA_W1TC` writer - ADC2 Conversion is done, write 1 to deassert int enable."] +pub type COCPU_SARADC2_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC1_ERROR_INT_ENA_W1TC` writer - An errro occurs from ADC1, write 1 to deassert int enable."] +pub type COCPU_SARADC1_ERROR_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_ERROR_INT_ENA_W1TC` writer - An errro occurs from ADC2, write 1 to deassert int enable."] +pub type COCPU_SARADC2_ERROR_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC1_WAKE_INT_ENA_W1TC` writer - A wakeup event is triggered from ADC1, write 1 to deassert int enable."] +pub type COCPU_SARADC1_WAKE_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_WAKE_INT_ENA_W1TC` writer - A wakeup event is triggered from ADC2, write 1 to deassert int enable."] +pub type COCPU_SARADC2_WAKE_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - ADC1 Conversion is done, write 1 to deassert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_int_ena_w1tc( + &mut self, + ) -> COCPU_SARADC1_INT_ENA_W1TC_W { + COCPU_SARADC1_INT_ENA_W1TC_W::new(self, 0) + } + #[doc = "Bit 1 - ADC2 Conversion is done, write 1 to deassert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_int_ena_w1tc( + &mut self, + ) -> COCPU_SARADC2_INT_ENA_W1TC_W { + COCPU_SARADC2_INT_ENA_W1TC_W::new(self, 1) + } + #[doc = "Bit 2 - An errro occurs from ADC1, write 1 to deassert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_error_int_ena_w1tc( + &mut self, + ) -> COCPU_SARADC1_ERROR_INT_ENA_W1TC_W { + COCPU_SARADC1_ERROR_INT_ENA_W1TC_W::new(self, 2) + } + #[doc = "Bit 3 - An errro occurs from ADC2, write 1 to deassert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_error_int_ena_w1tc( + &mut self, + ) -> COCPU_SARADC2_ERROR_INT_ENA_W1TC_W { + COCPU_SARADC2_ERROR_INT_ENA_W1TC_W::new(self, 3) + } + #[doc = "Bit 4 - A wakeup event is triggered from ADC1, write 1 to deassert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_wake_int_ena_w1tc( + &mut self, + ) -> COCPU_SARADC1_WAKE_INT_ENA_W1TC_W { + COCPU_SARADC1_WAKE_INT_ENA_W1TC_W::new(self, 4) + } + #[doc = "Bit 5 - A wakeup event is triggered from ADC2, write 1 to deassert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_wake_int_ena_w1tc( + &mut self, + ) -> COCPU_SARADC2_WAKE_INT_ENA_W1TC_W { + COCPU_SARADC2_WAKE_INT_ENA_W1TC_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable deassert registers.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_W1TC_SPEC; +impl crate::RegisterSpec for INT_ENA_W1TC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_ena_w1tc::W`](W) writer structure"] +impl crate::Writable for INT_ENA_W1TC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA_W1TC to value 0"] +impl crate::Resettable for INT_ENA_W1TC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/int_ena_w1ts.rs b/esp32p4/src/lp_adc/int_ena_w1ts.rs new file mode 100644 index 0000000000..56c53cf7a0 --- /dev/null +++ b/esp32p4/src/lp_adc/int_ena_w1ts.rs @@ -0,0 +1,94 @@ +#[doc = "Register `INT_ENA_W1TS` writer"] +pub type W = crate::W; +#[doc = "Field `COCPU_SARADC1_INT_ENA_W1TS` writer - ADC1 Conversion is done, write 1 to assert int enable."] +pub type COCPU_SARADC1_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_INT_ENA_W1TS` writer - ADC2 Conversion is done, write 1 to assert int enable."] +pub type COCPU_SARADC2_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC1_ERROR_INT_ENA_W1TS` writer - An errro occurs from ADC1, write 1 to assert int enable."] +pub type COCPU_SARADC1_ERROR_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_ERROR_INT_ENA_W1TS` writer - An errro occurs from ADC2, write 1 to assert int enable."] +pub type COCPU_SARADC2_ERROR_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC1_WAKE_INT_ENA_W1TS` writer - A wakeup event is triggered from ADC1, write 1 to assert int enable."] +pub type COCPU_SARADC1_WAKE_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COCPU_SARADC2_WAKE_INT_ENA_W1TS` writer - A wakeup event is triggered from ADC2, write 1 to assert int enable."] +pub type COCPU_SARADC2_WAKE_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - ADC1 Conversion is done, write 1 to assert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_int_ena_w1ts( + &mut self, + ) -> COCPU_SARADC1_INT_ENA_W1TS_W { + COCPU_SARADC1_INT_ENA_W1TS_W::new(self, 0) + } + #[doc = "Bit 1 - ADC2 Conversion is done, write 1 to assert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_int_ena_w1ts( + &mut self, + ) -> COCPU_SARADC2_INT_ENA_W1TS_W { + COCPU_SARADC2_INT_ENA_W1TS_W::new(self, 1) + } + #[doc = "Bit 2 - An errro occurs from ADC1, write 1 to assert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_error_int_ena_w1ts( + &mut self, + ) -> COCPU_SARADC1_ERROR_INT_ENA_W1TS_W { + COCPU_SARADC1_ERROR_INT_ENA_W1TS_W::new(self, 2) + } + #[doc = "Bit 3 - An errro occurs from ADC2, write 1 to assert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_error_int_ena_w1ts( + &mut self, + ) -> COCPU_SARADC2_ERROR_INT_ENA_W1TS_W { + COCPU_SARADC2_ERROR_INT_ENA_W1TS_W::new(self, 3) + } + #[doc = "Bit 4 - A wakeup event is triggered from ADC1, write 1 to assert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc1_wake_int_ena_w1ts( + &mut self, + ) -> COCPU_SARADC1_WAKE_INT_ENA_W1TS_W { + COCPU_SARADC1_WAKE_INT_ENA_W1TS_W::new(self, 4) + } + #[doc = "Bit 5 - A wakeup event is triggered from ADC2, write 1 to assert int enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_saradc2_wake_int_ena_w1ts( + &mut self, + ) -> COCPU_SARADC2_WAKE_INT_ENA_W1TS_W { + COCPU_SARADC2_WAKE_INT_ENA_W1TS_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable assert registers.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_W1TS_SPEC; +impl crate::RegisterSpec for INT_ENA_W1TS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_ena_w1ts::W`](W) writer structure"] +impl crate::Writable for INT_ENA_W1TS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA_W1TS to value 0"] +impl crate::Resettable for INT_ENA_W1TS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/int_st.rs b/esp32p4/src/lp_adc/int_st.rs new file mode 100644 index 0000000000..0ad595e4d2 --- /dev/null +++ b/esp32p4/src/lp_adc/int_st.rs @@ -0,0 +1,94 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `COCPU_SARADC1_INT_ST` reader - ADC1 Conversion is done, int status."] +pub type COCPU_SARADC1_INT_ST_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC2_INT_ST` reader - ADC2 Conversion is done, int status."] +pub type COCPU_SARADC2_INT_ST_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC1_ERROR_INT_ST` reader - An errro occurs from ADC1, int status."] +pub type COCPU_SARADC1_ERROR_INT_ST_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC2_ERROR_INT_ST` reader - An errro occurs from ADC2, int status."] +pub type COCPU_SARADC2_ERROR_INT_ST_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC1_WAKE_INT_ST` reader - A wakeup event is triggered from ADC1, int status."] +pub type COCPU_SARADC1_WAKE_INT_ST_R = crate::BitReader; +#[doc = "Field `COCPU_SARADC2_WAKE_INT_ST` reader - A wakeup event is triggered from ADC2, int status."] +pub type COCPU_SARADC2_WAKE_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - ADC1 Conversion is done, int status."] + #[inline(always)] + pub fn cocpu_saradc1_int_st(&self) -> COCPU_SARADC1_INT_ST_R { + COCPU_SARADC1_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ADC2 Conversion is done, int status."] + #[inline(always)] + pub fn cocpu_saradc2_int_st(&self) -> COCPU_SARADC2_INT_ST_R { + COCPU_SARADC2_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - An errro occurs from ADC1, int status."] + #[inline(always)] + pub fn cocpu_saradc1_error_int_st(&self) -> COCPU_SARADC1_ERROR_INT_ST_R { + COCPU_SARADC1_ERROR_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - An errro occurs from ADC2, int status."] + #[inline(always)] + pub fn cocpu_saradc2_error_int_st(&self) -> COCPU_SARADC2_ERROR_INT_ST_R { + COCPU_SARADC2_ERROR_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - A wakeup event is triggered from ADC1, int status."] + #[inline(always)] + pub fn cocpu_saradc1_wake_int_st(&self) -> COCPU_SARADC1_WAKE_INT_ST_R { + COCPU_SARADC1_WAKE_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - A wakeup event is triggered from ADC2, int status."] + #[inline(always)] + pub fn cocpu_saradc2_wake_int_st(&self) -> COCPU_SARADC2_WAKE_INT_ST_R { + COCPU_SARADC2_WAKE_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "cocpu_saradc1_int_st", + &format_args!("{}", self.cocpu_saradc1_int_st().bit()), + ) + .field( + "cocpu_saradc2_int_st", + &format_args!("{}", self.cocpu_saradc2_int_st().bit()), + ) + .field( + "cocpu_saradc1_error_int_st", + &format_args!("{}", self.cocpu_saradc1_error_int_st().bit()), + ) + .field( + "cocpu_saradc2_error_int_st", + &format_args!("{}", self.cocpu_saradc2_error_int_st().bit()), + ) + .field( + "cocpu_saradc1_wake_int_st", + &format_args!("{}", self.cocpu_saradc1_wake_int_st().bit()), + ) + .field( + "cocpu_saradc2_wake_int_st", + &format_args!("{}", self.cocpu_saradc2_wake_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Interrupt status registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/meas1_ctrl1.rs b/esp32p4/src/lp_adc/meas1_ctrl1.rs new file mode 100644 index 0000000000..c63acecadf --- /dev/null +++ b/esp32p4/src/lp_adc/meas1_ctrl1.rs @@ -0,0 +1,123 @@ +#[doc = "Register `MEAS1_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `MEAS1_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_XPD_AMP` reader - N/A"] +pub type FORCE_XPD_AMP_R = crate::FieldReader; +#[doc = "Field `FORCE_XPD_AMP` writer - N/A"] +pub type FORCE_XPD_AMP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `AMP_RST_FB_FORCE` reader - N/A"] +pub type AMP_RST_FB_FORCE_R = crate::FieldReader; +#[doc = "Field `AMP_RST_FB_FORCE` writer - N/A"] +pub type AMP_RST_FB_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `AMP_SHORT_REF_FORCE` reader - N/A"] +pub type AMP_SHORT_REF_FORCE_R = crate::FieldReader; +#[doc = "Field `AMP_SHORT_REF_FORCE` writer - N/A"] +pub type AMP_SHORT_REF_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `AMP_SHORT_REF_GND_FORCE` reader - N/A"] +pub type AMP_SHORT_REF_GND_FORCE_R = crate::FieldReader; +#[doc = "Field `AMP_SHORT_REF_GND_FORCE` writer - N/A"] +pub type AMP_SHORT_REF_GND_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 24:25 - N/A"] + #[inline(always)] + pub fn force_xpd_amp(&self) -> FORCE_XPD_AMP_R { + FORCE_XPD_AMP_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - N/A"] + #[inline(always)] + pub fn amp_rst_fb_force(&self) -> AMP_RST_FB_FORCE_R { + AMP_RST_FB_FORCE_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - N/A"] + #[inline(always)] + pub fn amp_short_ref_force(&self) -> AMP_SHORT_REF_FORCE_R { + AMP_SHORT_REF_FORCE_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - N/A"] + #[inline(always)] + pub fn amp_short_ref_gnd_force(&self) -> AMP_SHORT_REF_GND_FORCE_R { + AMP_SHORT_REF_GND_FORCE_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEAS1_CTRL1") + .field( + "force_xpd_amp", + &format_args!("{}", self.force_xpd_amp().bits()), + ) + .field( + "amp_rst_fb_force", + &format_args!("{}", self.amp_rst_fb_force().bits()), + ) + .field( + "amp_short_ref_force", + &format_args!("{}", self.amp_short_ref_force().bits()), + ) + .field( + "amp_short_ref_gnd_force", + &format_args!("{}", self.amp_short_ref_gnd_force().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 24:25 - N/A"] + #[inline(always)] + #[must_use] + pub fn force_xpd_amp(&mut self) -> FORCE_XPD_AMP_W { + FORCE_XPD_AMP_W::new(self, 24) + } + #[doc = "Bits 26:27 - N/A"] + #[inline(always)] + #[must_use] + pub fn amp_rst_fb_force(&mut self) -> AMP_RST_FB_FORCE_W { + AMP_RST_FB_FORCE_W::new(self, 26) + } + #[doc = "Bits 28:29 - N/A"] + #[inline(always)] + #[must_use] + pub fn amp_short_ref_force(&mut self) -> AMP_SHORT_REF_FORCE_W { + AMP_SHORT_REF_FORCE_W::new(self, 28) + } + #[doc = "Bits 30:31 - N/A"] + #[inline(always)] + #[must_use] + pub fn amp_short_ref_gnd_force(&mut self) -> AMP_SHORT_REF_GND_FORCE_W { + AMP_SHORT_REF_GND_FORCE_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas1_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas1_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEAS1_CTRL1_SPEC; +impl crate::RegisterSpec for MEAS1_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`meas1_ctrl1::R`](R) reader structure"] +impl crate::Readable for MEAS1_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`meas1_ctrl1::W`](W) writer structure"] +impl crate::Writable for MEAS1_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEAS1_CTRL1 to value 0"] +impl crate::Resettable for MEAS1_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/meas1_ctrl2.rs b/esp32p4/src/lp_adc/meas1_ctrl2.rs new file mode 100644 index 0000000000..e467a90765 --- /dev/null +++ b/esp32p4/src/lp_adc/meas1_ctrl2.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MEAS1_CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `MEAS1_CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `MEAS1_DATA_SAR` reader - SAR ADC1 data."] +pub type MEAS1_DATA_SAR_R = crate::FieldReader; +#[doc = "Field `MEAS1_DONE_SAR` reader - SAR ADC1 conversion done indication."] +pub type MEAS1_DONE_SAR_R = crate::BitReader; +#[doc = "Field `MEAS1_START_SAR` reader - SAR ADC1 controller (in RTC) starts conversion."] +pub type MEAS1_START_SAR_R = crate::BitReader; +#[doc = "Field `MEAS1_START_SAR` writer - SAR ADC1 controller (in RTC) starts conversion."] +pub type MEAS1_START_SAR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEAS1_START_FORCE` reader - 1: SAR ADC1 controller (in RTC) is started by SW."] +pub type MEAS1_START_FORCE_R = crate::BitReader; +#[doc = "Field `MEAS1_START_FORCE` writer - 1: SAR ADC1 controller (in RTC) is started by SW."] +pub type MEAS1_START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR1_EN_PAD` reader - SAR ADC1 pad enable bitmap."] +pub type SAR1_EN_PAD_R = crate::FieldReader; +#[doc = "Field `SAR1_EN_PAD` writer - SAR ADC1 pad enable bitmap."] +pub type SAR1_EN_PAD_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SAR1_EN_PAD_FORCE` reader - 1: SAR ADC1 pad enable bitmap is controlled by SW."] +pub type SAR1_EN_PAD_FORCE_R = crate::BitReader; +#[doc = "Field `SAR1_EN_PAD_FORCE` writer - 1: SAR ADC1 pad enable bitmap is controlled by SW."] +pub type SAR1_EN_PAD_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - SAR ADC1 data."] + #[inline(always)] + pub fn meas1_data_sar(&self) -> MEAS1_DATA_SAR_R { + MEAS1_DATA_SAR_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - SAR ADC1 conversion done indication."] + #[inline(always)] + pub fn meas1_done_sar(&self) -> MEAS1_DONE_SAR_R { + MEAS1_DONE_SAR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - SAR ADC1 controller (in RTC) starts conversion."] + #[inline(always)] + pub fn meas1_start_sar(&self) -> MEAS1_START_SAR_R { + MEAS1_START_SAR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - 1: SAR ADC1 controller (in RTC) is started by SW."] + #[inline(always)] + pub fn meas1_start_force(&self) -> MEAS1_START_FORCE_R { + MEAS1_START_FORCE_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:30 - SAR ADC1 pad enable bitmap."] + #[inline(always)] + pub fn sar1_en_pad(&self) -> SAR1_EN_PAD_R { + SAR1_EN_PAD_R::new(((self.bits >> 19) & 0x0fff) as u16) + } + #[doc = "Bit 31 - 1: SAR ADC1 pad enable bitmap is controlled by SW."] + #[inline(always)] + pub fn sar1_en_pad_force(&self) -> SAR1_EN_PAD_FORCE_R { + SAR1_EN_PAD_FORCE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEAS1_CTRL2") + .field( + "meas1_data_sar", + &format_args!("{}", self.meas1_data_sar().bits()), + ) + .field( + "meas1_done_sar", + &format_args!("{}", self.meas1_done_sar().bit()), + ) + .field( + "meas1_start_sar", + &format_args!("{}", self.meas1_start_sar().bit()), + ) + .field( + "meas1_start_force", + &format_args!("{}", self.meas1_start_force().bit()), + ) + .field( + "sar1_en_pad", + &format_args!("{}", self.sar1_en_pad().bits()), + ) + .field( + "sar1_en_pad_force", + &format_args!("{}", self.sar1_en_pad_force().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 17 - SAR ADC1 controller (in RTC) starts conversion."] + #[inline(always)] + #[must_use] + pub fn meas1_start_sar(&mut self) -> MEAS1_START_SAR_W { + MEAS1_START_SAR_W::new(self, 17) + } + #[doc = "Bit 18 - 1: SAR ADC1 controller (in RTC) is started by SW."] + #[inline(always)] + #[must_use] + pub fn meas1_start_force(&mut self) -> MEAS1_START_FORCE_W { + MEAS1_START_FORCE_W::new(self, 18) + } + #[doc = "Bits 19:30 - SAR ADC1 pad enable bitmap."] + #[inline(always)] + #[must_use] + pub fn sar1_en_pad(&mut self) -> SAR1_EN_PAD_W { + SAR1_EN_PAD_W::new(self, 19) + } + #[doc = "Bit 31 - 1: SAR ADC1 pad enable bitmap is controlled by SW."] + #[inline(always)] + #[must_use] + pub fn sar1_en_pad_force(&mut self) -> SAR1_EN_PAD_FORCE_W { + SAR1_EN_PAD_FORCE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ADC1 configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas1_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas1_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEAS1_CTRL2_SPEC; +impl crate::RegisterSpec for MEAS1_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`meas1_ctrl2::R`](R) reader structure"] +impl crate::Readable for MEAS1_CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`meas1_ctrl2::W`](W) writer structure"] +impl crate::Writable for MEAS1_CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEAS1_CTRL2 to value 0"] +impl crate::Resettable for MEAS1_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/meas1_mux.rs b/esp32p4/src/lp_adc/meas1_mux.rs new file mode 100644 index 0000000000..e7f5232c91 --- /dev/null +++ b/esp32p4/src/lp_adc/meas1_mux.rs @@ -0,0 +1,66 @@ +#[doc = "Register `MEAS1_MUX` reader"] +pub type R = crate::R; +#[doc = "Register `MEAS1_MUX` writer"] +pub type W = crate::W; +#[doc = "Field `SAR1_DIG_FORCE` reader - 1: SAR ADC1 controlled by DIG ADC1 CTRL."] +pub type SAR1_DIG_FORCE_R = crate::BitReader; +#[doc = "Field `SAR1_DIG_FORCE` writer - 1: SAR ADC1 controlled by DIG ADC1 CTRL."] +pub type SAR1_DIG_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - 1: SAR ADC1 controlled by DIG ADC1 CTRL."] + #[inline(always)] + pub fn sar1_dig_force(&self) -> SAR1_DIG_FORCE_R { + SAR1_DIG_FORCE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEAS1_MUX") + .field( + "sar1_dig_force", + &format_args!("{}", self.sar1_dig_force().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - 1: SAR ADC1 controlled by DIG ADC1 CTRL."] + #[inline(always)] + #[must_use] + pub fn sar1_dig_force(&mut self) -> SAR1_DIG_FORCE_W { + SAR1_DIG_FORCE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SAR ADC1 MUX register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas1_mux::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas1_mux::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEAS1_MUX_SPEC; +impl crate::RegisterSpec for MEAS1_MUX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`meas1_mux::R`](R) reader structure"] +impl crate::Readable for MEAS1_MUX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`meas1_mux::W`](W) writer structure"] +impl crate::Writable for MEAS1_MUX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEAS1_MUX to value 0"] +impl crate::Resettable for MEAS1_MUX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/meas2_ctrl1.rs b/esp32p4/src/lp_adc/meas2_ctrl1.rs new file mode 100644 index 0000000000..8fcf92f61e --- /dev/null +++ b/esp32p4/src/lp_adc/meas2_ctrl1.rs @@ -0,0 +1,191 @@ +#[doc = "Register `MEAS2_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `MEAS2_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `SAR2_CNTL_STATE` reader - saradc2_cntl_fsm."] +pub type SAR2_CNTL_STATE_R = crate::FieldReader; +#[doc = "Field `SAR2_PWDET_CAL_EN` reader - RTC control pwdet enable."] +pub type SAR2_PWDET_CAL_EN_R = crate::BitReader; +#[doc = "Field `SAR2_PWDET_CAL_EN` writer - RTC control pwdet enable."] +pub type SAR2_PWDET_CAL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR2_PKDET_CAL_EN` reader - RTC control pkdet enable."] +pub type SAR2_PKDET_CAL_EN_R = crate::BitReader; +#[doc = "Field `SAR2_PKDET_CAL_EN` writer - RTC control pkdet enable."] +pub type SAR2_PKDET_CAL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR2_EN_TEST` reader - SAR2_EN_TEST."] +pub type SAR2_EN_TEST_R = crate::BitReader; +#[doc = "Field `SAR2_EN_TEST` writer - SAR2_EN_TEST."] +pub type SAR2_EN_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR2_RSTB_FORCE` reader - N/A"] +pub type SAR2_RSTB_FORCE_R = crate::FieldReader; +#[doc = "Field `SAR2_RSTB_FORCE` writer - N/A"] +pub type SAR2_RSTB_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SAR2_STANDBY_WAIT` reader - N/A"] +pub type SAR2_STANDBY_WAIT_R = crate::FieldReader; +#[doc = "Field `SAR2_STANDBY_WAIT` writer - N/A"] +pub type SAR2_STANDBY_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SAR2_RSTB_WAIT` reader - N/A"] +pub type SAR2_RSTB_WAIT_R = crate::FieldReader; +#[doc = "Field `SAR2_RSTB_WAIT` writer - N/A"] +pub type SAR2_RSTB_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SAR2_XPD_WAIT` reader - N/A"] +pub type SAR2_XPD_WAIT_R = crate::FieldReader; +#[doc = "Field `SAR2_XPD_WAIT` writer - N/A"] +pub type SAR2_XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:2 - saradc2_cntl_fsm."] + #[inline(always)] + pub fn sar2_cntl_state(&self) -> SAR2_CNTL_STATE_R { + SAR2_CNTL_STATE_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - RTC control pwdet enable."] + #[inline(always)] + pub fn sar2_pwdet_cal_en(&self) -> SAR2_PWDET_CAL_EN_R { + SAR2_PWDET_CAL_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RTC control pkdet enable."] + #[inline(always)] + pub fn sar2_pkdet_cal_en(&self) -> SAR2_PKDET_CAL_EN_R { + SAR2_PKDET_CAL_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - SAR2_EN_TEST."] + #[inline(always)] + pub fn sar2_en_test(&self) -> SAR2_EN_TEST_R { + SAR2_EN_TEST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - N/A"] + #[inline(always)] + pub fn sar2_rstb_force(&self) -> SAR2_RSTB_FORCE_R { + SAR2_RSTB_FORCE_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:15 - N/A"] + #[inline(always)] + pub fn sar2_standby_wait(&self) -> SAR2_STANDBY_WAIT_R { + SAR2_STANDBY_WAIT_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - N/A"] + #[inline(always)] + pub fn sar2_rstb_wait(&self) -> SAR2_RSTB_WAIT_R { + SAR2_RSTB_WAIT_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - N/A"] + #[inline(always)] + pub fn sar2_xpd_wait(&self) -> SAR2_XPD_WAIT_R { + SAR2_XPD_WAIT_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEAS2_CTRL1") + .field( + "sar2_cntl_state", + &format_args!("{}", self.sar2_cntl_state().bits()), + ) + .field( + "sar2_pwdet_cal_en", + &format_args!("{}", self.sar2_pwdet_cal_en().bit()), + ) + .field( + "sar2_pkdet_cal_en", + &format_args!("{}", self.sar2_pkdet_cal_en().bit()), + ) + .field( + "sar2_en_test", + &format_args!("{}", self.sar2_en_test().bit()), + ) + .field( + "sar2_rstb_force", + &format_args!("{}", self.sar2_rstb_force().bits()), + ) + .field( + "sar2_standby_wait", + &format_args!("{}", self.sar2_standby_wait().bits()), + ) + .field( + "sar2_rstb_wait", + &format_args!("{}", self.sar2_rstb_wait().bits()), + ) + .field( + "sar2_xpd_wait", + &format_args!("{}", self.sar2_xpd_wait().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 3 - RTC control pwdet enable."] + #[inline(always)] + #[must_use] + pub fn sar2_pwdet_cal_en(&mut self) -> SAR2_PWDET_CAL_EN_W { + SAR2_PWDET_CAL_EN_W::new(self, 3) + } + #[doc = "Bit 4 - RTC control pkdet enable."] + #[inline(always)] + #[must_use] + pub fn sar2_pkdet_cal_en(&mut self) -> SAR2_PKDET_CAL_EN_W { + SAR2_PKDET_CAL_EN_W::new(self, 4) + } + #[doc = "Bit 5 - SAR2_EN_TEST."] + #[inline(always)] + #[must_use] + pub fn sar2_en_test(&mut self) -> SAR2_EN_TEST_W { + SAR2_EN_TEST_W::new(self, 5) + } + #[doc = "Bits 6:7 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar2_rstb_force(&mut self) -> SAR2_RSTB_FORCE_W { + SAR2_RSTB_FORCE_W::new(self, 6) + } + #[doc = "Bits 8:15 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar2_standby_wait(&mut self) -> SAR2_STANDBY_WAIT_W { + SAR2_STANDBY_WAIT_W::new(self, 8) + } + #[doc = "Bits 16:23 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar2_rstb_wait(&mut self) -> SAR2_RSTB_WAIT_W { + SAR2_RSTB_WAIT_W::new(self, 16) + } + #[doc = "Bits 24:31 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar2_xpd_wait(&mut self) -> SAR2_XPD_WAIT_W { + SAR2_XPD_WAIT_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ADC2 configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas2_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas2_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEAS2_CTRL1_SPEC; +impl crate::RegisterSpec for MEAS2_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`meas2_ctrl1::R`](R) reader structure"] +impl crate::Readable for MEAS2_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`meas2_ctrl1::W`](W) writer structure"] +impl crate::Writable for MEAS2_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEAS2_CTRL1 to value 0x0702_0200"] +impl crate::Resettable for MEAS2_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0x0702_0200; +} diff --git a/esp32p4/src/lp_adc/meas2_ctrl2.rs b/esp32p4/src/lp_adc/meas2_ctrl2.rs new file mode 100644 index 0000000000..899a31d44e --- /dev/null +++ b/esp32p4/src/lp_adc/meas2_ctrl2.rs @@ -0,0 +1,145 @@ +#[doc = "Register `MEAS2_CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `MEAS2_CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `MEAS2_DATA_SAR` reader - SAR ADC2 data."] +pub type MEAS2_DATA_SAR_R = crate::FieldReader; +#[doc = "Field `MEAS2_DONE_SAR` reader - SAR ADC2 conversion done indication."] +pub type MEAS2_DONE_SAR_R = crate::BitReader; +#[doc = "Field `MEAS2_START_SAR` reader - SAR ADC2 controller (in RTC) starts conversion."] +pub type MEAS2_START_SAR_R = crate::BitReader; +#[doc = "Field `MEAS2_START_SAR` writer - SAR ADC2 controller (in RTC) starts conversion."] +pub type MEAS2_START_SAR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEAS2_START_FORCE` reader - 1: SAR ADC2 controller (in RTC) is started by SW."] +pub type MEAS2_START_FORCE_R = crate::BitReader; +#[doc = "Field `MEAS2_START_FORCE` writer - 1: SAR ADC2 controller (in RTC) is started by SW."] +pub type MEAS2_START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR2_EN_PAD` reader - SAR ADC2 pad enable bitmap."] +pub type SAR2_EN_PAD_R = crate::FieldReader; +#[doc = "Field `SAR2_EN_PAD` writer - SAR ADC2 pad enable bitmap."] +pub type SAR2_EN_PAD_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SAR2_EN_PAD_FORCE` reader - 1: SAR ADC2 pad enable bitmap is controlled by SW."] +pub type SAR2_EN_PAD_FORCE_R = crate::BitReader; +#[doc = "Field `SAR2_EN_PAD_FORCE` writer - 1: SAR ADC2 pad enable bitmap is controlled by SW."] +pub type SAR2_EN_PAD_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - SAR ADC2 data."] + #[inline(always)] + pub fn meas2_data_sar(&self) -> MEAS2_DATA_SAR_R { + MEAS2_DATA_SAR_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - SAR ADC2 conversion done indication."] + #[inline(always)] + pub fn meas2_done_sar(&self) -> MEAS2_DONE_SAR_R { + MEAS2_DONE_SAR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - SAR ADC2 controller (in RTC) starts conversion."] + #[inline(always)] + pub fn meas2_start_sar(&self) -> MEAS2_START_SAR_R { + MEAS2_START_SAR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - 1: SAR ADC2 controller (in RTC) is started by SW."] + #[inline(always)] + pub fn meas2_start_force(&self) -> MEAS2_START_FORCE_R { + MEAS2_START_FORCE_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:30 - SAR ADC2 pad enable bitmap."] + #[inline(always)] + pub fn sar2_en_pad(&self) -> SAR2_EN_PAD_R { + SAR2_EN_PAD_R::new(((self.bits >> 19) & 0x0fff) as u16) + } + #[doc = "Bit 31 - 1: SAR ADC2 pad enable bitmap is controlled by SW."] + #[inline(always)] + pub fn sar2_en_pad_force(&self) -> SAR2_EN_PAD_FORCE_R { + SAR2_EN_PAD_FORCE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEAS2_CTRL2") + .field( + "meas2_data_sar", + &format_args!("{}", self.meas2_data_sar().bits()), + ) + .field( + "meas2_done_sar", + &format_args!("{}", self.meas2_done_sar().bit()), + ) + .field( + "meas2_start_sar", + &format_args!("{}", self.meas2_start_sar().bit()), + ) + .field( + "meas2_start_force", + &format_args!("{}", self.meas2_start_force().bit()), + ) + .field( + "sar2_en_pad", + &format_args!("{}", self.sar2_en_pad().bits()), + ) + .field( + "sar2_en_pad_force", + &format_args!("{}", self.sar2_en_pad_force().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 17 - SAR ADC2 controller (in RTC) starts conversion."] + #[inline(always)] + #[must_use] + pub fn meas2_start_sar(&mut self) -> MEAS2_START_SAR_W { + MEAS2_START_SAR_W::new(self, 17) + } + #[doc = "Bit 18 - 1: SAR ADC2 controller (in RTC) is started by SW."] + #[inline(always)] + #[must_use] + pub fn meas2_start_force(&mut self) -> MEAS2_START_FORCE_W { + MEAS2_START_FORCE_W::new(self, 18) + } + #[doc = "Bits 19:30 - SAR ADC2 pad enable bitmap."] + #[inline(always)] + #[must_use] + pub fn sar2_en_pad(&mut self) -> SAR2_EN_PAD_W { + SAR2_EN_PAD_W::new(self, 19) + } + #[doc = "Bit 31 - 1: SAR ADC2 pad enable bitmap is controlled by SW."] + #[inline(always)] + #[must_use] + pub fn sar2_en_pad_force(&mut self) -> SAR2_EN_PAD_FORCE_W { + SAR2_EN_PAD_FORCE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ADC2 configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas2_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas2_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEAS2_CTRL2_SPEC; +impl crate::RegisterSpec for MEAS2_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`meas2_ctrl2::R`](R) reader structure"] +impl crate::Readable for MEAS2_CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`meas2_ctrl2::W`](W) writer structure"] +impl crate::Writable for MEAS2_CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEAS2_CTRL2 to value 0"] +impl crate::Resettable for MEAS2_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/meas2_mux.rs b/esp32p4/src/lp_adc/meas2_mux.rs new file mode 100644 index 0000000000..52784f1308 --- /dev/null +++ b/esp32p4/src/lp_adc/meas2_mux.rs @@ -0,0 +1,85 @@ +#[doc = "Register `MEAS2_MUX` reader"] +pub type R = crate::R; +#[doc = "Register `MEAS2_MUX` writer"] +pub type W = crate::W; +#[doc = "Field `SAR2_PWDET_CCT` reader - SAR2_PWDET_CCT."] +pub type SAR2_PWDET_CCT_R = crate::FieldReader; +#[doc = "Field `SAR2_PWDET_CCT` writer - SAR2_PWDET_CCT."] +pub type SAR2_PWDET_CCT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SAR2_RTC_FORCE` reader - In sleep, force to use rtc to control ADC."] +pub type SAR2_RTC_FORCE_R = crate::BitReader; +#[doc = "Field `SAR2_RTC_FORCE` writer - In sleep, force to use rtc to control ADC."] +pub type SAR2_RTC_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 28:30 - SAR2_PWDET_CCT."] + #[inline(always)] + pub fn sar2_pwdet_cct(&self) -> SAR2_PWDET_CCT_R { + SAR2_PWDET_CCT_R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - In sleep, force to use rtc to control ADC."] + #[inline(always)] + pub fn sar2_rtc_force(&self) -> SAR2_RTC_FORCE_R { + SAR2_RTC_FORCE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEAS2_MUX") + .field( + "sar2_pwdet_cct", + &format_args!("{}", self.sar2_pwdet_cct().bits()), + ) + .field( + "sar2_rtc_force", + &format_args!("{}", self.sar2_rtc_force().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 28:30 - SAR2_PWDET_CCT."] + #[inline(always)] + #[must_use] + pub fn sar2_pwdet_cct(&mut self) -> SAR2_PWDET_CCT_W { + SAR2_PWDET_CCT_W::new(self, 28) + } + #[doc = "Bit 31 - In sleep, force to use rtc to control ADC."] + #[inline(always)] + #[must_use] + pub fn sar2_rtc_force(&mut self) -> SAR2_RTC_FORCE_W { + SAR2_RTC_FORCE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SAR ADC2 MUX register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas2_mux::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`meas2_mux::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEAS2_MUX_SPEC; +impl crate::RegisterSpec for MEAS2_MUX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`meas2_mux::R`](R) reader structure"] +impl crate::Readable for MEAS2_MUX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`meas2_mux::W`](W) writer structure"] +impl crate::Writable for MEAS2_MUX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEAS2_MUX to value 0"] +impl crate::Resettable for MEAS2_MUX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/meas_status.rs b/esp32p4/src/lp_adc/meas_status.rs new file mode 100644 index 0000000000..4ba175e53c --- /dev/null +++ b/esp32p4/src/lp_adc/meas_status.rs @@ -0,0 +1,39 @@ +#[doc = "Register `MEAS_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `SARADC_MEAS_STATUS` reader - N/A"] +pub type SARADC_MEAS_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - N/A"] + #[inline(always)] + pub fn saradc_meas_status(&self) -> SARADC_MEAS_STATUS_R { + SARADC_MEAS_STATUS_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEAS_STATUS") + .field( + "saradc_meas_status", + &format_args!("{}", self.saradc_meas_status().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEAS_STATUS_SPEC; +impl crate::RegisterSpec for MEAS_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`meas_status::R`](R) reader structure"] +impl crate::Readable for MEAS_STATUS_SPEC {} +#[doc = "`reset()` method sets MEAS_STATUS to value 0"] +impl crate::Resettable for MEAS_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/reader1_ctrl.rs b/esp32p4/src/lp_adc/reader1_ctrl.rs new file mode 100644 index 0000000000..764739f3d1 --- /dev/null +++ b/esp32p4/src/lp_adc/reader1_ctrl.rs @@ -0,0 +1,158 @@ +#[doc = "Register `READER1_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `READER1_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SAR1_CLK_DIV` reader - Clock divider."] +pub type SAR1_CLK_DIV_R = crate::FieldReader; +#[doc = "Field `SAR1_CLK_DIV` writer - Clock divider."] +pub type SAR1_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SAR1_CLK_GATED` reader - N/A"] +pub type SAR1_CLK_GATED_R = crate::BitReader; +#[doc = "Field `SAR1_CLK_GATED` writer - N/A"] +pub type SAR1_CLK_GATED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR1_SAMPLE_NUM` reader - N/A"] +pub type SAR1_SAMPLE_NUM_R = crate::FieldReader; +#[doc = "Field `SAR1_SAMPLE_NUM` writer - N/A"] +pub type SAR1_SAMPLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SAR1_DATA_INV` reader - Invert SAR ADC1 data."] +pub type SAR1_DATA_INV_R = crate::BitReader; +#[doc = "Field `SAR1_DATA_INV` writer - Invert SAR ADC1 data."] +pub type SAR1_DATA_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR1_INT_EN` reader - Enable saradc1 to send out interrupt."] +pub type SAR1_INT_EN_R = crate::BitReader; +#[doc = "Field `SAR1_INT_EN` writer - Enable saradc1 to send out interrupt."] +pub type SAR1_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR1_EN_PAD_FORCE_ENABLE` reader - Force enable adc en_pad to analog circuit 2'b11: force enable ."] +pub type SAR1_EN_PAD_FORCE_ENABLE_R = crate::FieldReader; +#[doc = "Field `SAR1_EN_PAD_FORCE_ENABLE` writer - Force enable adc en_pad to analog circuit 2'b11: force enable ."] +pub type SAR1_EN_PAD_FORCE_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:7 - Clock divider."] + #[inline(always)] + pub fn sar1_clk_div(&self) -> SAR1_CLK_DIV_R { + SAR1_CLK_DIV_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 18 - N/A"] + #[inline(always)] + pub fn sar1_clk_gated(&self) -> SAR1_CLK_GATED_R { + SAR1_CLK_GATED_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:26 - N/A"] + #[inline(always)] + pub fn sar1_sample_num(&self) -> SAR1_SAMPLE_NUM_R { + SAR1_SAMPLE_NUM_R::new(((self.bits >> 19) & 0xff) as u8) + } + #[doc = "Bit 28 - Invert SAR ADC1 data."] + #[inline(always)] + pub fn sar1_data_inv(&self) -> SAR1_DATA_INV_R { + SAR1_DATA_INV_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Enable saradc1 to send out interrupt."] + #[inline(always)] + pub fn sar1_int_en(&self) -> SAR1_INT_EN_R { + SAR1_INT_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bits 30:31 - Force enable adc en_pad to analog circuit 2'b11: force enable ."] + #[inline(always)] + pub fn sar1_en_pad_force_enable(&self) -> SAR1_EN_PAD_FORCE_ENABLE_R { + SAR1_EN_PAD_FORCE_ENABLE_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("READER1_CTRL") + .field( + "sar1_clk_div", + &format_args!("{}", self.sar1_clk_div().bits()), + ) + .field( + "sar1_clk_gated", + &format_args!("{}", self.sar1_clk_gated().bit()), + ) + .field( + "sar1_sample_num", + &format_args!("{}", self.sar1_sample_num().bits()), + ) + .field( + "sar1_data_inv", + &format_args!("{}", self.sar1_data_inv().bit()), + ) + .field("sar1_int_en", &format_args!("{}", self.sar1_int_en().bit())) + .field( + "sar1_en_pad_force_enable", + &format_args!("{}", self.sar1_en_pad_force_enable().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Clock divider."] + #[inline(always)] + #[must_use] + pub fn sar1_clk_div(&mut self) -> SAR1_CLK_DIV_W { + SAR1_CLK_DIV_W::new(self, 0) + } + #[doc = "Bit 18 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar1_clk_gated(&mut self) -> SAR1_CLK_GATED_W { + SAR1_CLK_GATED_W::new(self, 18) + } + #[doc = "Bits 19:26 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar1_sample_num(&mut self) -> SAR1_SAMPLE_NUM_W { + SAR1_SAMPLE_NUM_W::new(self, 19) + } + #[doc = "Bit 28 - Invert SAR ADC1 data."] + #[inline(always)] + #[must_use] + pub fn sar1_data_inv(&mut self) -> SAR1_DATA_INV_W { + SAR1_DATA_INV_W::new(self, 28) + } + #[doc = "Bit 29 - Enable saradc1 to send out interrupt."] + #[inline(always)] + #[must_use] + pub fn sar1_int_en(&mut self) -> SAR1_INT_EN_W { + SAR1_INT_EN_W::new(self, 29) + } + #[doc = "Bits 30:31 - Force enable adc en_pad to analog circuit 2'b11: force enable ."] + #[inline(always)] + #[must_use] + pub fn sar1_en_pad_force_enable(&mut self) -> SAR1_EN_PAD_FORCE_ENABLE_W { + SAR1_EN_PAD_FORCE_ENABLE_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control the read operation of ADC1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reader1_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reader1_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct READER1_CTRL_SPEC; +impl crate::RegisterSpec for READER1_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reader1_ctrl::R`](R) reader structure"] +impl crate::Readable for READER1_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reader1_ctrl::W`](W) writer structure"] +impl crate::Writable for READER1_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets READER1_CTRL to value 0x2004_0002"] +impl crate::Resettable for READER1_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x2004_0002; +} diff --git a/esp32p4/src/lp_adc/reader1_status.rs b/esp32p4/src/lp_adc/reader1_status.rs new file mode 100644 index 0000000000..30da7b283d --- /dev/null +++ b/esp32p4/src/lp_adc/reader1_status.rs @@ -0,0 +1,39 @@ +#[doc = "Register `READER1_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `SAR1_READER_STATUS` reader - N/A"] +pub type SAR1_READER_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + pub fn sar1_reader_status(&self) -> SAR1_READER_STATUS_R { + SAR1_READER_STATUS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("READER1_STATUS") + .field( + "sar1_reader_status", + &format_args!("{}", self.sar1_reader_status().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reader1_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct READER1_STATUS_SPEC; +impl crate::RegisterSpec for READER1_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reader1_status::R`](R) reader structure"] +impl crate::Readable for READER1_STATUS_SPEC {} +#[doc = "`reset()` method sets READER1_STATUS to value 0x2000_0000"] +impl crate::Resettable for READER1_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x2000_0000; +} diff --git a/esp32p4/src/lp_adc/reader2_ctrl.rs b/esp32p4/src/lp_adc/reader2_ctrl.rs new file mode 100644 index 0000000000..db7e70fbb3 --- /dev/null +++ b/esp32p4/src/lp_adc/reader2_ctrl.rs @@ -0,0 +1,177 @@ +#[doc = "Register `READER2_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `READER2_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SAR2_CLK_DIV` reader - Clock divider."] +pub type SAR2_CLK_DIV_R = crate::FieldReader; +#[doc = "Field `SAR2_CLK_DIV` writer - Clock divider."] +pub type SAR2_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SAR2_WAIT_ARB_CYCLE` reader - Wait arbit stable after sar_done."] +pub type SAR2_WAIT_ARB_CYCLE_R = crate::FieldReader; +#[doc = "Field `SAR2_WAIT_ARB_CYCLE` writer - Wait arbit stable after sar_done."] +pub type SAR2_WAIT_ARB_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SAR2_CLK_GATED` reader - N/A"] +pub type SAR2_CLK_GATED_R = crate::BitReader; +#[doc = "Field `SAR2_CLK_GATED` writer - N/A"] +pub type SAR2_CLK_GATED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR2_SAMPLE_NUM` reader - N/A"] +pub type SAR2_SAMPLE_NUM_R = crate::FieldReader; +#[doc = "Field `SAR2_SAMPLE_NUM` writer - N/A"] +pub type SAR2_SAMPLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SAR2_EN_PAD_FORCE_ENABLE` reader - Force enable adc en_pad to analog circuit 2'b11: force enable ."] +pub type SAR2_EN_PAD_FORCE_ENABLE_R = crate::FieldReader; +#[doc = "Field `SAR2_EN_PAD_FORCE_ENABLE` writer - Force enable adc en_pad to analog circuit 2'b11: force enable ."] +pub type SAR2_EN_PAD_FORCE_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SAR2_DATA_INV` reader - Invert SAR ADC2 data."] +pub type SAR2_DATA_INV_R = crate::BitReader; +#[doc = "Field `SAR2_DATA_INV` writer - Invert SAR ADC2 data."] +pub type SAR2_DATA_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR2_INT_EN` reader - Enable saradc2 to send out interrupt."] +pub type SAR2_INT_EN_R = crate::BitReader; +#[doc = "Field `SAR2_INT_EN` writer - Enable saradc2 to send out interrupt."] +pub type SAR2_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Clock divider."] + #[inline(always)] + pub fn sar2_clk_div(&self) -> SAR2_CLK_DIV_R { + SAR2_CLK_DIV_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:17 - Wait arbit stable after sar_done."] + #[inline(always)] + pub fn sar2_wait_arb_cycle(&self) -> SAR2_WAIT_ARB_CYCLE_R { + SAR2_WAIT_ARB_CYCLE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - N/A"] + #[inline(always)] + pub fn sar2_clk_gated(&self) -> SAR2_CLK_GATED_R { + SAR2_CLK_GATED_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:26 - N/A"] + #[inline(always)] + pub fn sar2_sample_num(&self) -> SAR2_SAMPLE_NUM_R { + SAR2_SAMPLE_NUM_R::new(((self.bits >> 19) & 0xff) as u8) + } + #[doc = "Bits 27:28 - Force enable adc en_pad to analog circuit 2'b11: force enable ."] + #[inline(always)] + pub fn sar2_en_pad_force_enable(&self) -> SAR2_EN_PAD_FORCE_ENABLE_R { + SAR2_EN_PAD_FORCE_ENABLE_R::new(((self.bits >> 27) & 3) as u8) + } + #[doc = "Bit 29 - Invert SAR ADC2 data."] + #[inline(always)] + pub fn sar2_data_inv(&self) -> SAR2_DATA_INV_R { + SAR2_DATA_INV_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Enable saradc2 to send out interrupt."] + #[inline(always)] + pub fn sar2_int_en(&self) -> SAR2_INT_EN_R { + SAR2_INT_EN_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("READER2_CTRL") + .field( + "sar2_clk_div", + &format_args!("{}", self.sar2_clk_div().bits()), + ) + .field( + "sar2_wait_arb_cycle", + &format_args!("{}", self.sar2_wait_arb_cycle().bits()), + ) + .field( + "sar2_clk_gated", + &format_args!("{}", self.sar2_clk_gated().bit()), + ) + .field( + "sar2_sample_num", + &format_args!("{}", self.sar2_sample_num().bits()), + ) + .field( + "sar2_en_pad_force_enable", + &format_args!("{}", self.sar2_en_pad_force_enable().bits()), + ) + .field( + "sar2_data_inv", + &format_args!("{}", self.sar2_data_inv().bit()), + ) + .field("sar2_int_en", &format_args!("{}", self.sar2_int_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Clock divider."] + #[inline(always)] + #[must_use] + pub fn sar2_clk_div(&mut self) -> SAR2_CLK_DIV_W { + SAR2_CLK_DIV_W::new(self, 0) + } + #[doc = "Bits 16:17 - Wait arbit stable after sar_done."] + #[inline(always)] + #[must_use] + pub fn sar2_wait_arb_cycle(&mut self) -> SAR2_WAIT_ARB_CYCLE_W { + SAR2_WAIT_ARB_CYCLE_W::new(self, 16) + } + #[doc = "Bit 18 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar2_clk_gated(&mut self) -> SAR2_CLK_GATED_W { + SAR2_CLK_GATED_W::new(self, 18) + } + #[doc = "Bits 19:26 - N/A"] + #[inline(always)] + #[must_use] + pub fn sar2_sample_num(&mut self) -> SAR2_SAMPLE_NUM_W { + SAR2_SAMPLE_NUM_W::new(self, 19) + } + #[doc = "Bits 27:28 - Force enable adc en_pad to analog circuit 2'b11: force enable ."] + #[inline(always)] + #[must_use] + pub fn sar2_en_pad_force_enable(&mut self) -> SAR2_EN_PAD_FORCE_ENABLE_W { + SAR2_EN_PAD_FORCE_ENABLE_W::new(self, 27) + } + #[doc = "Bit 29 - Invert SAR ADC2 data."] + #[inline(always)] + #[must_use] + pub fn sar2_data_inv(&mut self) -> SAR2_DATA_INV_W { + SAR2_DATA_INV_W::new(self, 29) + } + #[doc = "Bit 30 - Enable saradc2 to send out interrupt."] + #[inline(always)] + #[must_use] + pub fn sar2_int_en(&mut self) -> SAR2_INT_EN_W { + SAR2_INT_EN_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control the read operation of ADC2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reader2_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reader2_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct READER2_CTRL_SPEC; +impl crate::RegisterSpec for READER2_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reader2_ctrl::R`](R) reader structure"] +impl crate::Readable for READER2_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reader2_ctrl::W`](W) writer structure"] +impl crate::Writable for READER2_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets READER2_CTRL to value 0x4005_0002"] +impl crate::Resettable for READER2_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x4005_0002; +} diff --git a/esp32p4/src/lp_adc/reader2_status.rs b/esp32p4/src/lp_adc/reader2_status.rs new file mode 100644 index 0000000000..44ed7c1fca --- /dev/null +++ b/esp32p4/src/lp_adc/reader2_status.rs @@ -0,0 +1,39 @@ +#[doc = "Register `READER2_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `SAR2_READER_STATUS` reader - N/A"] +pub type SAR2_READER_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + pub fn sar2_reader_status(&self) -> SAR2_READER_STATUS_R { + SAR2_READER_STATUS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("READER2_STATUS") + .field( + "sar2_reader_status", + &format_args!("{}", self.sar2_reader_status().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reader2_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct READER2_STATUS_SPEC; +impl crate::RegisterSpec for READER2_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reader2_status::R`](R) reader structure"] +impl crate::Readable for READER2_STATUS_SPEC {} +#[doc = "`reset()` method sets READER2_STATUS to value 0"] +impl crate::Resettable for READER2_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/reg_clken.rs b/esp32p4/src/lp_adc/reg_clken.rs new file mode 100644 index 0000000000..384b32d76e --- /dev/null +++ b/esp32p4/src/lp_adc/reg_clken.rs @@ -0,0 +1,63 @@ +#[doc = "Register `REG_CLKEN` reader"] +pub type R = crate::R; +#[doc = "Register `REG_CLKEN` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - N/A"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - N/A"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_CLKEN") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_clken::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_clken::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_CLKEN_SPEC; +impl crate::RegisterSpec for REG_CLKEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_clken::R`](R) reader structure"] +impl crate::Readable for REG_CLKEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_clken::W`](W) writer structure"] +impl crate::Writable for REG_CLKEN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_CLKEN to value 0"] +impl crate::Resettable for REG_CLKEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/rnd_eco_cs.rs b/esp32p4/src/lp_adc/rnd_eco_cs.rs new file mode 100644 index 0000000000..50d64f15d3 --- /dev/null +++ b/esp32p4/src/lp_adc/rnd_eco_cs.rs @@ -0,0 +1,74 @@ +#[doc = "Register `RND_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `RND_ECO_EN` reader - N/A"] +pub type RND_ECO_EN_R = crate::BitReader; +#[doc = "Field `RND_ECO_EN` writer - N/A"] +pub type RND_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RND_ECO_RESULT` reader - N/A"] +pub type RND_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + pub fn rnd_eco_en(&self) -> RND_ECO_EN_R { + RND_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + pub fn rnd_eco_result(&self) -> RND_ECO_RESULT_R { + RND_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_CS") + .field("rnd_eco_en", &format_args!("{}", self.rnd_eco_en().bit())) + .field( + "rnd_eco_result", + &format_args!("{}", self.rnd_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + #[must_use] + pub fn rnd_eco_en(&mut self) -> RND_ECO_EN_W { + RND_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_CS_SPEC; +impl crate::RegisterSpec for RND_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_cs::R`](R) reader structure"] +impl crate::Readable for RND_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_cs::W`](W) writer structure"] +impl crate::Writable for RND_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_CS to value 0"] +impl crate::Resettable for RND_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/rnd_eco_high.rs b/esp32p4/src/lp_adc/rnd_eco_high.rs new file mode 100644 index 0000000000..81d831c24f --- /dev/null +++ b/esp32p4/src/lp_adc/rnd_eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RND_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `RND_ECO_HIGH` reader - N/A"] +pub type RND_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `RND_ECO_HIGH` writer - N/A"] +pub type RND_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + pub fn rnd_eco_high(&self) -> RND_ECO_HIGH_R { + RND_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_HIGH") + .field( + "rnd_eco_high", + &format_args!("{}", self.rnd_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + #[must_use] + pub fn rnd_eco_high(&mut self) -> RND_ECO_HIGH_W { + RND_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_HIGH_SPEC; +impl crate::RegisterSpec for RND_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_high::R`](R) reader structure"] +impl crate::Readable for RND_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_high::W`](W) writer structure"] +impl crate::Writable for RND_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for RND_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_adc/rnd_eco_low.rs b/esp32p4/src/lp_adc/rnd_eco_low.rs new file mode 100644 index 0000000000..8d51754156 --- /dev/null +++ b/esp32p4/src/lp_adc/rnd_eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RND_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `RND_ECO_LOW` reader - N/A"] +pub type RND_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `RND_ECO_LOW` writer - N/A"] +pub type RND_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + pub fn rnd_eco_low(&self) -> RND_ECO_LOW_R { + RND_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_LOW") + .field( + "rnd_eco_low", + &format_args!("{}", self.rnd_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + #[must_use] + pub fn rnd_eco_low(&mut self) -> RND_ECO_LOW_W { + RND_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_LOW_SPEC; +impl crate::RegisterSpec for RND_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_low::R`](R) reader structure"] +impl crate::Readable for RND_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_low::W`](W) writer structure"] +impl crate::Writable for RND_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_LOW to value 0"] +impl crate::Resettable for RND_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_adc/sar1_hw_wakeup.rs b/esp32p4/src/lp_adc/sar1_hw_wakeup.rs new file mode 100644 index 0000000000..8137940e88 --- /dev/null +++ b/esp32p4/src/lp_adc/sar1_hw_wakeup.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SAR1_HW_WAKEUP` reader"] +pub type R = crate::R; +#[doc = "Register `SAR1_HW_WAKEUP` writer"] +pub type W = crate::W; +#[doc = "Field `ADC1_HW_READ_EN_I` reader - Enable hardware automatic sampling."] +pub type ADC1_HW_READ_EN_I_R = crate::BitReader; +#[doc = "Field `ADC1_HW_READ_EN_I` writer - Enable hardware automatic sampling."] +pub type ADC1_HW_READ_EN_I_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC1_HW_READ_RATE_I` reader - Hardware automatic sampling rate."] +pub type ADC1_HW_READ_RATE_I_R = crate::FieldReader; +#[doc = "Field `ADC1_HW_READ_RATE_I` writer - Hardware automatic sampling rate."] +pub type ADC1_HW_READ_RATE_I_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - Enable hardware automatic sampling."] + #[inline(always)] + pub fn adc1_hw_read_en_i(&self) -> ADC1_HW_READ_EN_I_R { + ADC1_HW_READ_EN_I_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - Hardware automatic sampling rate."] + #[inline(always)] + pub fn adc1_hw_read_rate_i(&self) -> ADC1_HW_READ_RATE_I_R { + ADC1_HW_READ_RATE_I_R::new(((self.bits >> 1) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR1_HW_WAKEUP") + .field( + "adc1_hw_read_en_i", + &format_args!("{}", self.adc1_hw_read_en_i().bit()), + ) + .field( + "adc1_hw_read_rate_i", + &format_args!("{}", self.adc1_hw_read_rate_i().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable hardware automatic sampling."] + #[inline(always)] + #[must_use] + pub fn adc1_hw_read_en_i(&mut self) -> ADC1_HW_READ_EN_I_W { + ADC1_HW_READ_EN_I_W::new(self, 0) + } + #[doc = "Bits 1:16 - Hardware automatic sampling rate."] + #[inline(always)] + #[must_use] + pub fn adc1_hw_read_rate_i(&mut self) -> ADC1_HW_READ_RATE_I_W { + ADC1_HW_READ_RATE_I_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Hardware automatic sampling registers for wakeup function.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_hw_wakeup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar1_hw_wakeup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR1_HW_WAKEUP_SPEC; +impl crate::RegisterSpec for SAR1_HW_WAKEUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar1_hw_wakeup::R`](R) reader structure"] +impl crate::Readable for SAR1_HW_WAKEUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sar1_hw_wakeup::W`](W) writer structure"] +impl crate::Writable for SAR1_HW_WAKEUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAR1_HW_WAKEUP to value 0xc8"] +impl crate::Resettable for SAR1_HW_WAKEUP_SPEC { + const RESET_VALUE: Self::Ux = 0xc8; +} diff --git a/esp32p4/src/lp_adc/sar2_hw_wakeup.rs b/esp32p4/src/lp_adc/sar2_hw_wakeup.rs new file mode 100644 index 0000000000..2f580b7175 --- /dev/null +++ b/esp32p4/src/lp_adc/sar2_hw_wakeup.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SAR2_HW_WAKEUP` reader"] +pub type R = crate::R; +#[doc = "Register `SAR2_HW_WAKEUP` writer"] +pub type W = crate::W; +#[doc = "Field `ADC2_HW_READ_EN_I` reader - Enable hardware automatic sampling."] +pub type ADC2_HW_READ_EN_I_R = crate::BitReader; +#[doc = "Field `ADC2_HW_READ_EN_I` writer - Enable hardware automatic sampling."] +pub type ADC2_HW_READ_EN_I_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC2_HW_READ_RATE_I` reader - Hardware automatic sampling rate."] +pub type ADC2_HW_READ_RATE_I_R = crate::FieldReader; +#[doc = "Field `ADC2_HW_READ_RATE_I` writer - Hardware automatic sampling rate."] +pub type ADC2_HW_READ_RATE_I_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - Enable hardware automatic sampling."] + #[inline(always)] + pub fn adc2_hw_read_en_i(&self) -> ADC2_HW_READ_EN_I_R { + ADC2_HW_READ_EN_I_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - Hardware automatic sampling rate."] + #[inline(always)] + pub fn adc2_hw_read_rate_i(&self) -> ADC2_HW_READ_RATE_I_R { + ADC2_HW_READ_RATE_I_R::new(((self.bits >> 1) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAR2_HW_WAKEUP") + .field( + "adc2_hw_read_en_i", + &format_args!("{}", self.adc2_hw_read_en_i().bit()), + ) + .field( + "adc2_hw_read_rate_i", + &format_args!("{}", self.adc2_hw_read_rate_i().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable hardware automatic sampling."] + #[inline(always)] + #[must_use] + pub fn adc2_hw_read_en_i(&mut self) -> ADC2_HW_READ_EN_I_W { + ADC2_HW_READ_EN_I_W::new(self, 0) + } + #[doc = "Bits 1:16 - Hardware automatic sampling rate."] + #[inline(always)] + #[must_use] + pub fn adc2_hw_read_rate_i(&mut self) -> ADC2_HW_READ_RATE_I_W { + ADC2_HW_READ_RATE_I_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Hardware automatic sampling registers for wakeup function.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_hw_wakeup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sar2_hw_wakeup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAR2_HW_WAKEUP_SPEC; +impl crate::RegisterSpec for SAR2_HW_WAKEUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sar2_hw_wakeup::R`](R) reader structure"] +impl crate::Readable for SAR2_HW_WAKEUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sar2_hw_wakeup::W`](W) writer structure"] +impl crate::Writable for SAR2_HW_WAKEUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAR2_HW_WAKEUP to value 0xc8"] +impl crate::Resettable for SAR2_HW_WAKEUP_SPEC { + const RESET_VALUE: Self::Ux = 0xc8; +} diff --git a/esp32p4/src/lp_adc/wakeup1.rs b/esp32p4/src/lp_adc/wakeup1.rs new file mode 100644 index 0000000000..79d732b076 --- /dev/null +++ b/esp32p4/src/lp_adc/wakeup1.rs @@ -0,0 +1,134 @@ +#[doc = "Register `WAKEUP1` reader"] +pub type R = crate::R; +#[doc = "Register `WAKEUP1` writer"] +pub type W = crate::W; +#[doc = "Field `SAR1_WAKEUP_TH_LOW` reader - Lower threshold."] +pub type SAR1_WAKEUP_TH_LOW_R = crate::FieldReader; +#[doc = "Field `SAR1_WAKEUP_TH_LOW` writer - Lower threshold."] +pub type SAR1_WAKEUP_TH_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SAR1_WAKEUP_TH_HIGH` reader - Upper threshold."] +pub type SAR1_WAKEUP_TH_HIGH_R = crate::FieldReader; +#[doc = "Field `SAR1_WAKEUP_TH_HIGH` writer - Upper threshold."] +pub type SAR1_WAKEUP_TH_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SAR1_WAKEUP_OVER_UPPER_TH` reader - Indicates that this wakeup event arose from exceeding upper threshold."] +pub type SAR1_WAKEUP_OVER_UPPER_TH_R = crate::BitReader; +#[doc = "Field `SAR1_WAKEUP_EN` reader - Wakeup function enable."] +pub type SAR1_WAKEUP_EN_R = crate::BitReader; +#[doc = "Field `SAR1_WAKEUP_EN` writer - Wakeup function enable."] +pub type SAR1_WAKEUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR1_WAKEUP_MODE` reader - 0:absolute value comparison mode. 1: relative value comparison mode."] +pub type SAR1_WAKEUP_MODE_R = crate::BitReader; +#[doc = "Field `SAR1_WAKEUP_MODE` writer - 0:absolute value comparison mode. 1: relative value comparison mode."] +pub type SAR1_WAKEUP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:11 - Lower threshold."] + #[inline(always)] + pub fn sar1_wakeup_th_low(&self) -> SAR1_WAKEUP_TH_LOW_R { + SAR1_WAKEUP_TH_LOW_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 14:25 - Upper threshold."] + #[inline(always)] + pub fn sar1_wakeup_th_high(&self) -> SAR1_WAKEUP_TH_HIGH_R { + SAR1_WAKEUP_TH_HIGH_R::new(((self.bits >> 14) & 0x0fff) as u16) + } + #[doc = "Bit 29 - Indicates that this wakeup event arose from exceeding upper threshold."] + #[inline(always)] + pub fn sar1_wakeup_over_upper_th(&self) -> SAR1_WAKEUP_OVER_UPPER_TH_R { + SAR1_WAKEUP_OVER_UPPER_TH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Wakeup function enable."] + #[inline(always)] + pub fn sar1_wakeup_en(&self) -> SAR1_WAKEUP_EN_R { + SAR1_WAKEUP_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 0:absolute value comparison mode. 1: relative value comparison mode."] + #[inline(always)] + pub fn sar1_wakeup_mode(&self) -> SAR1_WAKEUP_MODE_R { + SAR1_WAKEUP_MODE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WAKEUP1") + .field( + "sar1_wakeup_th_low", + &format_args!("{}", self.sar1_wakeup_th_low().bits()), + ) + .field( + "sar1_wakeup_th_high", + &format_args!("{}", self.sar1_wakeup_th_high().bits()), + ) + .field( + "sar1_wakeup_over_upper_th", + &format_args!("{}", self.sar1_wakeup_over_upper_th().bit()), + ) + .field( + "sar1_wakeup_en", + &format_args!("{}", self.sar1_wakeup_en().bit()), + ) + .field( + "sar1_wakeup_mode", + &format_args!("{}", self.sar1_wakeup_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - Lower threshold."] + #[inline(always)] + #[must_use] + pub fn sar1_wakeup_th_low(&mut self) -> SAR1_WAKEUP_TH_LOW_W { + SAR1_WAKEUP_TH_LOW_W::new(self, 0) + } + #[doc = "Bits 14:25 - Upper threshold."] + #[inline(always)] + #[must_use] + pub fn sar1_wakeup_th_high(&mut self) -> SAR1_WAKEUP_TH_HIGH_W { + SAR1_WAKEUP_TH_HIGH_W::new(self, 14) + } + #[doc = "Bit 30 - Wakeup function enable."] + #[inline(always)] + #[must_use] + pub fn sar1_wakeup_en(&mut self) -> SAR1_WAKEUP_EN_W { + SAR1_WAKEUP_EN_W::new(self, 30) + } + #[doc = "Bit 31 - 0:absolute value comparison mode. 1: relative value comparison mode."] + #[inline(always)] + #[must_use] + pub fn sar1_wakeup_mode(&mut self) -> SAR1_WAKEUP_MODE_W { + SAR1_WAKEUP_MODE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ADC1 wakeup configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WAKEUP1_SPEC; +impl crate::RegisterSpec for WAKEUP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wakeup1::R`](R) reader structure"] +impl crate::Readable for WAKEUP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wakeup1::W`](W) writer structure"] +impl crate::Writable for WAKEUP1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WAKEUP1 to value 0x03ff_c000"] +impl crate::Resettable for WAKEUP1_SPEC { + const RESET_VALUE: Self::Ux = 0x03ff_c000; +} diff --git a/esp32p4/src/lp_adc/wakeup2.rs b/esp32p4/src/lp_adc/wakeup2.rs new file mode 100644 index 0000000000..64e6ba95c6 --- /dev/null +++ b/esp32p4/src/lp_adc/wakeup2.rs @@ -0,0 +1,134 @@ +#[doc = "Register `WAKEUP2` reader"] +pub type R = crate::R; +#[doc = "Register `WAKEUP2` writer"] +pub type W = crate::W; +#[doc = "Field `SAR2_WAKEUP_TH_LOW` reader - Lower threshold."] +pub type SAR2_WAKEUP_TH_LOW_R = crate::FieldReader; +#[doc = "Field `SAR2_WAKEUP_TH_LOW` writer - Lower threshold."] +pub type SAR2_WAKEUP_TH_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SAR2_WAKEUP_TH_HIGH` reader - Upper threshold."] +pub type SAR2_WAKEUP_TH_HIGH_R = crate::FieldReader; +#[doc = "Field `SAR2_WAKEUP_TH_HIGH` writer - Upper threshold."] +pub type SAR2_WAKEUP_TH_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SAR2_WAKEUP_OVER_UPPER_TH` reader - Indicates that this wakeup event arose from exceeding upper threshold."] +pub type SAR2_WAKEUP_OVER_UPPER_TH_R = crate::BitReader; +#[doc = "Field `SAR2_WAKEUP_EN` reader - Wakeup function enable."] +pub type SAR2_WAKEUP_EN_R = crate::BitReader; +#[doc = "Field `SAR2_WAKEUP_EN` writer - Wakeup function enable."] +pub type SAR2_WAKEUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR2_WAKEUP_MODE` reader - 0:absolute value comparison mode. 1: relative value comparison mode."] +pub type SAR2_WAKEUP_MODE_R = crate::BitReader; +#[doc = "Field `SAR2_WAKEUP_MODE` writer - 0:absolute value comparison mode. 1: relative value comparison mode."] +pub type SAR2_WAKEUP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:11 - Lower threshold."] + #[inline(always)] + pub fn sar2_wakeup_th_low(&self) -> SAR2_WAKEUP_TH_LOW_R { + SAR2_WAKEUP_TH_LOW_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 14:25 - Upper threshold."] + #[inline(always)] + pub fn sar2_wakeup_th_high(&self) -> SAR2_WAKEUP_TH_HIGH_R { + SAR2_WAKEUP_TH_HIGH_R::new(((self.bits >> 14) & 0x0fff) as u16) + } + #[doc = "Bit 29 - Indicates that this wakeup event arose from exceeding upper threshold."] + #[inline(always)] + pub fn sar2_wakeup_over_upper_th(&self) -> SAR2_WAKEUP_OVER_UPPER_TH_R { + SAR2_WAKEUP_OVER_UPPER_TH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Wakeup function enable."] + #[inline(always)] + pub fn sar2_wakeup_en(&self) -> SAR2_WAKEUP_EN_R { + SAR2_WAKEUP_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 0:absolute value comparison mode. 1: relative value comparison mode."] + #[inline(always)] + pub fn sar2_wakeup_mode(&self) -> SAR2_WAKEUP_MODE_R { + SAR2_WAKEUP_MODE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WAKEUP2") + .field( + "sar2_wakeup_th_low", + &format_args!("{}", self.sar2_wakeup_th_low().bits()), + ) + .field( + "sar2_wakeup_th_high", + &format_args!("{}", self.sar2_wakeup_th_high().bits()), + ) + .field( + "sar2_wakeup_over_upper_th", + &format_args!("{}", self.sar2_wakeup_over_upper_th().bit()), + ) + .field( + "sar2_wakeup_en", + &format_args!("{}", self.sar2_wakeup_en().bit()), + ) + .field( + "sar2_wakeup_mode", + &format_args!("{}", self.sar2_wakeup_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - Lower threshold."] + #[inline(always)] + #[must_use] + pub fn sar2_wakeup_th_low(&mut self) -> SAR2_WAKEUP_TH_LOW_W { + SAR2_WAKEUP_TH_LOW_W::new(self, 0) + } + #[doc = "Bits 14:25 - Upper threshold."] + #[inline(always)] + #[must_use] + pub fn sar2_wakeup_th_high(&mut self) -> SAR2_WAKEUP_TH_HIGH_W { + SAR2_WAKEUP_TH_HIGH_W::new(self, 14) + } + #[doc = "Bit 30 - Wakeup function enable."] + #[inline(always)] + #[must_use] + pub fn sar2_wakeup_en(&mut self) -> SAR2_WAKEUP_EN_W { + SAR2_WAKEUP_EN_W::new(self, 30) + } + #[doc = "Bit 31 - 0:absolute value comparison mode. 1: relative value comparison mode."] + #[inline(always)] + #[must_use] + pub fn sar2_wakeup_mode(&mut self) -> SAR2_WAKEUP_MODE_W { + SAR2_WAKEUP_MODE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ADC2 wakeup configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WAKEUP2_SPEC; +impl crate::RegisterSpec for WAKEUP2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wakeup2::R`](R) reader structure"] +impl crate::Readable for WAKEUP2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wakeup2::W`](W) writer structure"] +impl crate::Writable for WAKEUP2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WAKEUP2 to value 0x03ff_c000"] +impl crate::Resettable for WAKEUP2_SPEC { + const RESET_VALUE: Self::Ux = 0x03ff_c000; +} diff --git a/esp32p4/src/lp_adc/wakeup_sel.rs b/esp32p4/src/lp_adc/wakeup_sel.rs new file mode 100644 index 0000000000..c89449ac7a --- /dev/null +++ b/esp32p4/src/lp_adc/wakeup_sel.rs @@ -0,0 +1,66 @@ +#[doc = "Register `WAKEUP_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `WAKEUP_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `SAR_WAKEUP_SEL` reader - 0: ADC1. 1: ADC2."] +pub type SAR_WAKEUP_SEL_R = crate::BitReader; +#[doc = "Field `SAR_WAKEUP_SEL` writer - 0: ADC1. 1: ADC2."] +pub type SAR_WAKEUP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 0: ADC1. 1: ADC2."] + #[inline(always)] + pub fn sar_wakeup_sel(&self) -> SAR_WAKEUP_SEL_R { + SAR_WAKEUP_SEL_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WAKEUP_SEL") + .field( + "sar_wakeup_sel", + &format_args!("{}", self.sar_wakeup_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 0: ADC1. 1: ADC2."] + #[inline(always)] + #[must_use] + pub fn sar_wakeup_sel(&mut self) -> SAR_WAKEUP_SEL_W { + SAR_WAKEUP_SEL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Wakeup source select register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WAKEUP_SEL_SPEC; +impl crate::RegisterSpec for WAKEUP_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wakeup_sel::R`](R) reader structure"] +impl crate::Readable for WAKEUP_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wakeup_sel::W`](W) writer structure"] +impl crate::Writable for WAKEUP_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WAKEUP_SEL to value 0"] +impl crate::Resettable for WAKEUP_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri.rs b/esp32p4/src/lp_ana_peri.rs new file mode 100644 index 0000000000..fbb1cf11a0 --- /dev/null +++ b/esp32p4/src/lp_ana_peri.rs @@ -0,0 +1,819 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + lp_ana_bod_mode0_cntl: LP_ANA_BOD_MODE0_CNTL, + lp_ana_bod_mode1_cntl: LP_ANA_BOD_MODE1_CNTL, + lp_ana_vdd_source_cntl: LP_ANA_VDD_SOURCE_CNTL, + lp_ana_vddbat_bod_cntl: LP_ANA_VDDBAT_BOD_CNTL, + lp_ana_vddbat_charge_cntl: LP_ANA_VDDBAT_CHARGE_CNTL, + lp_ana_ck_glitch_cntl: LP_ANA_CK_GLITCH_CNTL, + lp_ana_pg_glitch_cntl: LP_ANA_PG_GLITCH_CNTL, + lp_ana_fib_enable: LP_ANA_FIB_ENABLE, + lp_ana_int_raw: LP_ANA_INT_RAW, + lp_ana_int_st: LP_ANA_INT_ST, + lp_ana_int_ena: LP_ANA_INT_ENA, + lp_ana_int_clr: LP_ANA_INT_CLR, + lp_ana_lp_int_raw: LP_ANA_LP_INT_RAW, + lp_ana_lp_int_st: LP_ANA_LP_INT_ST, + lp_ana_lp_int_ena: LP_ANA_LP_INT_ENA, + lp_ana_lp_int_clr: LP_ANA_LP_INT_CLR, + _reserved16: [u8; 0xbc], + lp_ana_touch_approach_work_meas_num: LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM, + lp_ana_touch_scan_ctrl1: LP_ANA_TOUCH_SCAN_CTRL1, + lp_ana_touch_scan_ctrl2: LP_ANA_TOUCH_SCAN_CTRL2, + lp_ana_touch_work: LP_ANA_TOUCH_WORK, + lp_ana_touch_work_meas_num: LP_ANA_TOUCH_WORK_MEAS_NUM, + lp_ana_touch_filter1: LP_ANA_TOUCH_FILTER1, + lp_ana_touch_filter2: LP_ANA_TOUCH_FILTER2, + lp_ana_touch_filter3: LP_ANA_TOUCH_FILTER3, + lp_ana_touch_slp0: LP_ANA_TOUCH_SLP0, + lp_ana_touch_slp1: LP_ANA_TOUCH_SLP1, + lp_ana_touch_clr: LP_ANA_TOUCH_CLR, + lp_ana_touch_approach: LP_ANA_TOUCH_APPROACH, + lp_ana_touch_freq0_scan_para: LP_ANA_TOUCH_FREQ0_SCAN_PARA, + lp_ana_touch_freq1_scan_para: LP_ANA_TOUCH_FREQ1_SCAN_PARA, + lp_ana_touch_freq2_scan_para: LP_ANA_TOUCH_FREQ2_SCAN_PARA, + lp_ana_touch_ana_para: LP_ANA_TOUCH_ANA_PARA, + lp_ana_touch_mux0: LP_ANA_TOUCH_MUX0, + lp_ana_touch_mux1: LP_ANA_TOUCH_MUX1, + lp_ana_touch_pad0_th0: LP_ANA_TOUCH_PAD0_TH0, + lp_ana_touch_pad0_th1: LP_ANA_TOUCH_PAD0_TH1, + lp_ana_touch_pad0_th2: LP_ANA_TOUCH_PAD0_TH2, + lp_ana_touch_pad1_th0: LP_ANA_TOUCH_PAD1_TH0, + lp_ana_touch_pad1_th1: LP_ANA_TOUCH_PAD1_TH1, + lp_ana_touch_pad1_th2: LP_ANA_TOUCH_PAD1_TH2, + lp_ana_touch_pad2_th0: LP_ANA_TOUCH_PAD2_TH0, + lp_ana_touch_pad2_th1: LP_ANA_TOUCH_PAD2_TH1, + lp_ana_touch_pad2_th2: LP_ANA_TOUCH_PAD2_TH2, + lp_ana_touch_pad3_th0: LP_ANA_TOUCH_PAD3_TH0, + lp_ana_touch_pad3_th1: LP_ANA_TOUCH_PAD3_TH1, + lp_ana_touch_pad3_th2: LP_ANA_TOUCH_PAD3_TH2, + lp_ana_touch_pad4_th0: LP_ANA_TOUCH_PAD4_TH0, + lp_ana_touch_pad4_th1: LP_ANA_TOUCH_PAD4_TH1, + lp_ana_touch_pad4_th2: LP_ANA_TOUCH_PAD4_TH2, + lp_ana_touch_pad5_th0: LP_ANA_TOUCH_PAD5_TH0, + lp_ana_touch_pad5_th1: LP_ANA_TOUCH_PAD5_TH1, + lp_ana_touch_pad5_th2: LP_ANA_TOUCH_PAD5_TH2, + lp_ana_touch_pad6_th0: LP_ANA_TOUCH_PAD6_TH0, + lp_ana_touch_pad6_th1: LP_ANA_TOUCH_PAD6_TH1, + lp_ana_touch_pad6_th2: LP_ANA_TOUCH_PAD6_TH2, + lp_ana_touch_pad7_th0: LP_ANA_TOUCH_PAD7_TH0, + lp_ana_touch_pad7_th1: LP_ANA_TOUCH_PAD7_TH1, + lp_ana_touch_pad7_th2: LP_ANA_TOUCH_PAD7_TH2, + lp_ana_touch_pad8_th0: LP_ANA_TOUCH_PAD8_TH0, + lp_ana_touch_pad8_th1: LP_ANA_TOUCH_PAD8_TH1, + lp_ana_touch_pad8_th2: LP_ANA_TOUCH_PAD8_TH2, + lp_ana_touch_pad9_th0: LP_ANA_TOUCH_PAD9_TH0, + lp_ana_touch_pad9_th1: LP_ANA_TOUCH_PAD9_TH1, + lp_ana_touch_pad9_th2: LP_ANA_TOUCH_PAD9_TH2, + lp_ana_touch_pad10_th0: LP_ANA_TOUCH_PAD10_TH0, + lp_ana_touch_pad10_th1: LP_ANA_TOUCH_PAD10_TH1, + lp_ana_touch_pad10_th2: LP_ANA_TOUCH_PAD10_TH2, + lp_ana_touch_pad11_th0: LP_ANA_TOUCH_PAD11_TH0, + lp_ana_touch_pad11_th1: LP_ANA_TOUCH_PAD11_TH1, + lp_ana_touch_pad11_th2: LP_ANA_TOUCH_PAD11_TH2, + lp_ana_touch_pad12_th0: LP_ANA_TOUCH_PAD12_TH0, + lp_ana_touch_pad12_th1: LP_ANA_TOUCH_PAD12_TH1, + lp_ana_touch_pad12_th2: LP_ANA_TOUCH_PAD12_TH2, + lp_ana_touch_pad13_th0: LP_ANA_TOUCH_PAD13_TH0, + lp_ana_touch_pad13_th1: LP_ANA_TOUCH_PAD13_TH1, + lp_ana_touch_pad13_th2: LP_ANA_TOUCH_PAD13_TH2, + lp_ana_touch_pad14_th0: LP_ANA_TOUCH_PAD14_TH0, + lp_ana_touch_pad14_th1: LP_ANA_TOUCH_PAD14_TH1, + lp_ana_touch_pad14_th2: LP_ANA_TOUCH_PAD14_TH2, + _reserved79: [u8; 0x0204], + lp_ana_date: LP_ANA_DATE, +} +impl RegisterBlock { + #[doc = "0x00 - need_des"] + #[inline(always)] + pub const fn lp_ana_bod_mode0_cntl(&self) -> &LP_ANA_BOD_MODE0_CNTL { + &self.lp_ana_bod_mode0_cntl + } + #[doc = "0x04 - need_des"] + #[inline(always)] + pub const fn lp_ana_bod_mode1_cntl(&self) -> &LP_ANA_BOD_MODE1_CNTL { + &self.lp_ana_bod_mode1_cntl + } + #[doc = "0x08 - need_des"] + #[inline(always)] + pub const fn lp_ana_vdd_source_cntl(&self) -> &LP_ANA_VDD_SOURCE_CNTL { + &self.lp_ana_vdd_source_cntl + } + #[doc = "0x0c - need_des"] + #[inline(always)] + pub const fn lp_ana_vddbat_bod_cntl(&self) -> &LP_ANA_VDDBAT_BOD_CNTL { + &self.lp_ana_vddbat_bod_cntl + } + #[doc = "0x10 - need_des"] + #[inline(always)] + pub const fn lp_ana_vddbat_charge_cntl(&self) -> &LP_ANA_VDDBAT_CHARGE_CNTL { + &self.lp_ana_vddbat_charge_cntl + } + #[doc = "0x14 - need_des"] + #[inline(always)] + pub const fn lp_ana_ck_glitch_cntl(&self) -> &LP_ANA_CK_GLITCH_CNTL { + &self.lp_ana_ck_glitch_cntl + } + #[doc = "0x18 - need_des"] + #[inline(always)] + pub const fn lp_ana_pg_glitch_cntl(&self) -> &LP_ANA_PG_GLITCH_CNTL { + &self.lp_ana_pg_glitch_cntl + } + #[doc = "0x1c - need_des"] + #[inline(always)] + pub const fn lp_ana_fib_enable(&self) -> &LP_ANA_FIB_ENABLE { + &self.lp_ana_fib_enable + } + #[doc = "0x20 - need_des"] + #[inline(always)] + pub const fn lp_ana_int_raw(&self) -> &LP_ANA_INT_RAW { + &self.lp_ana_int_raw + } + #[doc = "0x24 - need_des"] + #[inline(always)] + pub const fn lp_ana_int_st(&self) -> &LP_ANA_INT_ST { + &self.lp_ana_int_st + } + #[doc = "0x28 - need_des"] + #[inline(always)] + pub const fn lp_ana_int_ena(&self) -> &LP_ANA_INT_ENA { + &self.lp_ana_int_ena + } + #[doc = "0x2c - need_des"] + #[inline(always)] + pub const fn lp_ana_int_clr(&self) -> &LP_ANA_INT_CLR { + &self.lp_ana_int_clr + } + #[doc = "0x30 - need_des"] + #[inline(always)] + pub const fn lp_ana_lp_int_raw(&self) -> &LP_ANA_LP_INT_RAW { + &self.lp_ana_lp_int_raw + } + #[doc = "0x34 - need_des"] + #[inline(always)] + pub const fn lp_ana_lp_int_st(&self) -> &LP_ANA_LP_INT_ST { + &self.lp_ana_lp_int_st + } + #[doc = "0x38 - need_des"] + #[inline(always)] + pub const fn lp_ana_lp_int_ena(&self) -> &LP_ANA_LP_INT_ENA { + &self.lp_ana_lp_int_ena + } + #[doc = "0x3c - need_des"] + #[inline(always)] + pub const fn lp_ana_lp_int_clr(&self) -> &LP_ANA_LP_INT_CLR { + &self.lp_ana_lp_int_clr + } + #[doc = "0xfc - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_approach_work_meas_num( + &self, + ) -> &LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM { + &self.lp_ana_touch_approach_work_meas_num + } + #[doc = "0x100 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_scan_ctrl1(&self) -> &LP_ANA_TOUCH_SCAN_CTRL1 { + &self.lp_ana_touch_scan_ctrl1 + } + #[doc = "0x104 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_scan_ctrl2(&self) -> &LP_ANA_TOUCH_SCAN_CTRL2 { + &self.lp_ana_touch_scan_ctrl2 + } + #[doc = "0x108 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_work(&self) -> &LP_ANA_TOUCH_WORK { + &self.lp_ana_touch_work + } + #[doc = "0x10c - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_work_meas_num(&self) -> &LP_ANA_TOUCH_WORK_MEAS_NUM { + &self.lp_ana_touch_work_meas_num + } + #[doc = "0x110 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_filter1(&self) -> &LP_ANA_TOUCH_FILTER1 { + &self.lp_ana_touch_filter1 + } + #[doc = "0x114 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_filter2(&self) -> &LP_ANA_TOUCH_FILTER2 { + &self.lp_ana_touch_filter2 + } + #[doc = "0x118 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_filter3(&self) -> &LP_ANA_TOUCH_FILTER3 { + &self.lp_ana_touch_filter3 + } + #[doc = "0x11c - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_slp0(&self) -> &LP_ANA_TOUCH_SLP0 { + &self.lp_ana_touch_slp0 + } + #[doc = "0x120 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_slp1(&self) -> &LP_ANA_TOUCH_SLP1 { + &self.lp_ana_touch_slp1 + } + #[doc = "0x124 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_clr(&self) -> &LP_ANA_TOUCH_CLR { + &self.lp_ana_touch_clr + } + #[doc = "0x128 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_approach(&self) -> &LP_ANA_TOUCH_APPROACH { + &self.lp_ana_touch_approach + } + #[doc = "0x12c - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_freq0_scan_para(&self) -> &LP_ANA_TOUCH_FREQ0_SCAN_PARA { + &self.lp_ana_touch_freq0_scan_para + } + #[doc = "0x130 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_freq1_scan_para(&self) -> &LP_ANA_TOUCH_FREQ1_SCAN_PARA { + &self.lp_ana_touch_freq1_scan_para + } + #[doc = "0x134 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_freq2_scan_para(&self) -> &LP_ANA_TOUCH_FREQ2_SCAN_PARA { + &self.lp_ana_touch_freq2_scan_para + } + #[doc = "0x138 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_ana_para(&self) -> &LP_ANA_TOUCH_ANA_PARA { + &self.lp_ana_touch_ana_para + } + #[doc = "0x13c - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_mux0(&self) -> &LP_ANA_TOUCH_MUX0 { + &self.lp_ana_touch_mux0 + } + #[doc = "0x140 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_mux1(&self) -> &LP_ANA_TOUCH_MUX1 { + &self.lp_ana_touch_mux1 + } + #[doc = "0x144 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad0_th0(&self) -> &LP_ANA_TOUCH_PAD0_TH0 { + &self.lp_ana_touch_pad0_th0 + } + #[doc = "0x148 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad0_th1(&self) -> &LP_ANA_TOUCH_PAD0_TH1 { + &self.lp_ana_touch_pad0_th1 + } + #[doc = "0x14c - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad0_th2(&self) -> &LP_ANA_TOUCH_PAD0_TH2 { + &self.lp_ana_touch_pad0_th2 + } + #[doc = "0x150 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad1_th0(&self) -> &LP_ANA_TOUCH_PAD1_TH0 { + &self.lp_ana_touch_pad1_th0 + } + #[doc = "0x154 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad1_th1(&self) -> &LP_ANA_TOUCH_PAD1_TH1 { + &self.lp_ana_touch_pad1_th1 + } + #[doc = "0x158 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad1_th2(&self) -> &LP_ANA_TOUCH_PAD1_TH2 { + &self.lp_ana_touch_pad1_th2 + } + #[doc = "0x15c - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad2_th0(&self) -> &LP_ANA_TOUCH_PAD2_TH0 { + &self.lp_ana_touch_pad2_th0 + } + #[doc = "0x160 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad2_th1(&self) -> &LP_ANA_TOUCH_PAD2_TH1 { + &self.lp_ana_touch_pad2_th1 + } + #[doc = "0x164 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad2_th2(&self) -> &LP_ANA_TOUCH_PAD2_TH2 { + &self.lp_ana_touch_pad2_th2 + } + #[doc = "0x168 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad3_th0(&self) -> &LP_ANA_TOUCH_PAD3_TH0 { + &self.lp_ana_touch_pad3_th0 + } + #[doc = "0x16c - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad3_th1(&self) -> &LP_ANA_TOUCH_PAD3_TH1 { + &self.lp_ana_touch_pad3_th1 + } + #[doc = "0x170 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad3_th2(&self) -> &LP_ANA_TOUCH_PAD3_TH2 { + &self.lp_ana_touch_pad3_th2 + } + #[doc = "0x174 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad4_th0(&self) -> &LP_ANA_TOUCH_PAD4_TH0 { + &self.lp_ana_touch_pad4_th0 + } + #[doc = "0x178 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad4_th1(&self) -> &LP_ANA_TOUCH_PAD4_TH1 { + &self.lp_ana_touch_pad4_th1 + } + #[doc = "0x17c - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad4_th2(&self) -> &LP_ANA_TOUCH_PAD4_TH2 { + &self.lp_ana_touch_pad4_th2 + } + #[doc = "0x180 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad5_th0(&self) -> &LP_ANA_TOUCH_PAD5_TH0 { + &self.lp_ana_touch_pad5_th0 + } + #[doc = "0x184 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad5_th1(&self) -> &LP_ANA_TOUCH_PAD5_TH1 { + &self.lp_ana_touch_pad5_th1 + } + #[doc = "0x188 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad5_th2(&self) -> &LP_ANA_TOUCH_PAD5_TH2 { + &self.lp_ana_touch_pad5_th2 + } + #[doc = "0x18c - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad6_th0(&self) -> &LP_ANA_TOUCH_PAD6_TH0 { + &self.lp_ana_touch_pad6_th0 + } + #[doc = "0x190 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad6_th1(&self) -> &LP_ANA_TOUCH_PAD6_TH1 { + &self.lp_ana_touch_pad6_th1 + } + #[doc = "0x194 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad6_th2(&self) -> &LP_ANA_TOUCH_PAD6_TH2 { + &self.lp_ana_touch_pad6_th2 + } + #[doc = "0x198 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad7_th0(&self) -> &LP_ANA_TOUCH_PAD7_TH0 { + &self.lp_ana_touch_pad7_th0 + } + #[doc = "0x19c - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad7_th1(&self) -> &LP_ANA_TOUCH_PAD7_TH1 { + &self.lp_ana_touch_pad7_th1 + } + #[doc = "0x1a0 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad7_th2(&self) -> &LP_ANA_TOUCH_PAD7_TH2 { + &self.lp_ana_touch_pad7_th2 + } + #[doc = "0x1a4 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad8_th0(&self) -> &LP_ANA_TOUCH_PAD8_TH0 { + &self.lp_ana_touch_pad8_th0 + } + #[doc = "0x1a8 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad8_th1(&self) -> &LP_ANA_TOUCH_PAD8_TH1 { + &self.lp_ana_touch_pad8_th1 + } + #[doc = "0x1ac - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad8_th2(&self) -> &LP_ANA_TOUCH_PAD8_TH2 { + &self.lp_ana_touch_pad8_th2 + } + #[doc = "0x1b0 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad9_th0(&self) -> &LP_ANA_TOUCH_PAD9_TH0 { + &self.lp_ana_touch_pad9_th0 + } + #[doc = "0x1b4 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad9_th1(&self) -> &LP_ANA_TOUCH_PAD9_TH1 { + &self.lp_ana_touch_pad9_th1 + } + #[doc = "0x1b8 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad9_th2(&self) -> &LP_ANA_TOUCH_PAD9_TH2 { + &self.lp_ana_touch_pad9_th2 + } + #[doc = "0x1bc - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad10_th0(&self) -> &LP_ANA_TOUCH_PAD10_TH0 { + &self.lp_ana_touch_pad10_th0 + } + #[doc = "0x1c0 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad10_th1(&self) -> &LP_ANA_TOUCH_PAD10_TH1 { + &self.lp_ana_touch_pad10_th1 + } + #[doc = "0x1c4 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad10_th2(&self) -> &LP_ANA_TOUCH_PAD10_TH2 { + &self.lp_ana_touch_pad10_th2 + } + #[doc = "0x1c8 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad11_th0(&self) -> &LP_ANA_TOUCH_PAD11_TH0 { + &self.lp_ana_touch_pad11_th0 + } + #[doc = "0x1cc - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad11_th1(&self) -> &LP_ANA_TOUCH_PAD11_TH1 { + &self.lp_ana_touch_pad11_th1 + } + #[doc = "0x1d0 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad11_th2(&self) -> &LP_ANA_TOUCH_PAD11_TH2 { + &self.lp_ana_touch_pad11_th2 + } + #[doc = "0x1d4 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad12_th0(&self) -> &LP_ANA_TOUCH_PAD12_TH0 { + &self.lp_ana_touch_pad12_th0 + } + #[doc = "0x1d8 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad12_th1(&self) -> &LP_ANA_TOUCH_PAD12_TH1 { + &self.lp_ana_touch_pad12_th1 + } + #[doc = "0x1dc - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad12_th2(&self) -> &LP_ANA_TOUCH_PAD12_TH2 { + &self.lp_ana_touch_pad12_th2 + } + #[doc = "0x1e0 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad13_th0(&self) -> &LP_ANA_TOUCH_PAD13_TH0 { + &self.lp_ana_touch_pad13_th0 + } + #[doc = "0x1e4 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad13_th1(&self) -> &LP_ANA_TOUCH_PAD13_TH1 { + &self.lp_ana_touch_pad13_th1 + } + #[doc = "0x1e8 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad13_th2(&self) -> &LP_ANA_TOUCH_PAD13_TH2 { + &self.lp_ana_touch_pad13_th2 + } + #[doc = "0x1ec - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad14_th0(&self) -> &LP_ANA_TOUCH_PAD14_TH0 { + &self.lp_ana_touch_pad14_th0 + } + #[doc = "0x1f0 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad14_th1(&self) -> &LP_ANA_TOUCH_PAD14_TH1 { + &self.lp_ana_touch_pad14_th1 + } + #[doc = "0x1f4 - need_des"] + #[inline(always)] + pub const fn lp_ana_touch_pad14_th2(&self) -> &LP_ANA_TOUCH_PAD14_TH2 { + &self.lp_ana_touch_pad14_th2 + } + #[doc = "0x3fc - need_des"] + #[inline(always)] + pub const fn lp_ana_date(&self) -> &LP_ANA_DATE { + &self.lp_ana_date + } +} +#[doc = "LP_ANA_BOD_MODE0_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_bod_mode0_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_bod_mode0_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_bod_mode0_cntl`] module"] +pub type LP_ANA_BOD_MODE0_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_bod_mode0_cntl; +#[doc = "LP_ANA_BOD_MODE1_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_bod_mode1_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_bod_mode1_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_bod_mode1_cntl`] module"] +pub type LP_ANA_BOD_MODE1_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_bod_mode1_cntl; +#[doc = "LP_ANA_VDD_SOURCE_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_vdd_source_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_vdd_source_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_vdd_source_cntl`] module"] +pub type LP_ANA_VDD_SOURCE_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_vdd_source_cntl; +#[doc = "LP_ANA_VDDBAT_BOD_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_vddbat_bod_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_vddbat_bod_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_vddbat_bod_cntl`] module"] +pub type LP_ANA_VDDBAT_BOD_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_vddbat_bod_cntl; +#[doc = "LP_ANA_VDDBAT_CHARGE_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_vddbat_charge_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_vddbat_charge_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_vddbat_charge_cntl`] module"] +pub type LP_ANA_VDDBAT_CHARGE_CNTL = + crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_vddbat_charge_cntl; +#[doc = "LP_ANA_CK_GLITCH_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_ck_glitch_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_ck_glitch_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_ck_glitch_cntl`] module"] +pub type LP_ANA_CK_GLITCH_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_ck_glitch_cntl; +#[doc = "LP_ANA_PG_GLITCH_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_pg_glitch_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_pg_glitch_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_pg_glitch_cntl`] module"] +pub type LP_ANA_PG_GLITCH_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_pg_glitch_cntl; +#[doc = "LP_ANA_FIB_ENABLE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_fib_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_fib_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_fib_enable`] module"] +pub type LP_ANA_FIB_ENABLE = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_fib_enable; +#[doc = "LP_ANA_INT_RAW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_int_raw`] module"] +pub type LP_ANA_INT_RAW = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_int_raw; +#[doc = "LP_ANA_INT_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_int_st`] module"] +pub type LP_ANA_INT_ST = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_int_st; +#[doc = "LP_ANA_INT_ENA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_int_ena`] module"] +pub type LP_ANA_INT_ENA = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_int_ena; +#[doc = "LP_ANA_INT_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_int_clr`] module"] +pub type LP_ANA_INT_CLR = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_int_clr; +#[doc = "LP_ANA_LP_INT_RAW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_lp_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_lp_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_lp_int_raw`] module"] +pub type LP_ANA_LP_INT_RAW = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_lp_int_raw; +#[doc = "LP_ANA_LP_INT_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_lp_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_lp_int_st`] module"] +pub type LP_ANA_LP_INT_ST = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_lp_int_st; +#[doc = "LP_ANA_LP_INT_ENA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_lp_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_lp_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_lp_int_ena`] module"] +pub type LP_ANA_LP_INT_ENA = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_lp_int_ena; +#[doc = "LP_ANA_LP_INT_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_lp_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_lp_int_clr`] module"] +pub type LP_ANA_LP_INT_CLR = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_lp_int_clr; +#[doc = "LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_approach_work_meas_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_approach_work_meas_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_approach_work_meas_num`] module"] +pub type LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM = + crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_approach_work_meas_num; +#[doc = "LP_ANA_TOUCH_SCAN_CTRL1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_scan_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_scan_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_scan_ctrl1`] module"] +pub type LP_ANA_TOUCH_SCAN_CTRL1 = + crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_scan_ctrl1; +#[doc = "LP_ANA_TOUCH_SCAN_CTRL2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_scan_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_scan_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_scan_ctrl2`] module"] +pub type LP_ANA_TOUCH_SCAN_CTRL2 = + crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_scan_ctrl2; +#[doc = "LP_ANA_TOUCH_WORK (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_work::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_work::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_work`] module"] +pub type LP_ANA_TOUCH_WORK = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_work; +#[doc = "LP_ANA_TOUCH_WORK_MEAS_NUM (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_work_meas_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_work_meas_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_work_meas_num`] module"] +pub type LP_ANA_TOUCH_WORK_MEAS_NUM = + crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_work_meas_num; +#[doc = "LP_ANA_TOUCH_FILTER1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_filter1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_filter1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_filter1`] module"] +pub type LP_ANA_TOUCH_FILTER1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_filter1; +#[doc = "LP_ANA_TOUCH_FILTER2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_filter2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_filter2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_filter2`] module"] +pub type LP_ANA_TOUCH_FILTER2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_filter2; +#[doc = "LP_ANA_TOUCH_FILTER3 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_filter3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_filter3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_filter3`] module"] +pub type LP_ANA_TOUCH_FILTER3 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_filter3; +#[doc = "LP_ANA_TOUCH_SLP0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_slp0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_slp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_slp0`] module"] +pub type LP_ANA_TOUCH_SLP0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_slp0; +#[doc = "LP_ANA_TOUCH_SLP1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_slp1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_slp1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_slp1`] module"] +pub type LP_ANA_TOUCH_SLP1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_slp1; +#[doc = "LP_ANA_TOUCH_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_clr`] module"] +pub type LP_ANA_TOUCH_CLR = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_clr; +#[doc = "LP_ANA_TOUCH_APPROACH (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_approach::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_approach::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_approach`] module"] +pub type LP_ANA_TOUCH_APPROACH = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_approach; +#[doc = "LP_ANA_TOUCH_FREQ0_SCAN_PARA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_freq0_scan_para::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_freq0_scan_para::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_freq0_scan_para`] module"] +pub type LP_ANA_TOUCH_FREQ0_SCAN_PARA = + crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_freq0_scan_para; +#[doc = "LP_ANA_TOUCH_FREQ1_SCAN_PARA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_freq1_scan_para::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_freq1_scan_para::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_freq1_scan_para`] module"] +pub type LP_ANA_TOUCH_FREQ1_SCAN_PARA = + crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_freq1_scan_para; +#[doc = "LP_ANA_TOUCH_FREQ2_SCAN_PARA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_freq2_scan_para::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_freq2_scan_para::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_freq2_scan_para`] module"] +pub type LP_ANA_TOUCH_FREQ2_SCAN_PARA = + crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_freq2_scan_para; +#[doc = "LP_ANA_TOUCH_ANA_PARA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_ana_para::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_ana_para::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_ana_para`] module"] +pub type LP_ANA_TOUCH_ANA_PARA = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_ana_para; +#[doc = "LP_ANA_TOUCH_MUX0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_mux0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_mux0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_mux0`] module"] +pub type LP_ANA_TOUCH_MUX0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_mux0; +#[doc = "LP_ANA_TOUCH_MUX1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_mux1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_mux1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_mux1`] module"] +pub type LP_ANA_TOUCH_MUX1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_mux1; +#[doc = "LP_ANA_TOUCH_PAD0_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad0_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad0_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad0_th0`] module"] +pub type LP_ANA_TOUCH_PAD0_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad0_th0; +#[doc = "LP_ANA_TOUCH_PAD0_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad0_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad0_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad0_th1`] module"] +pub type LP_ANA_TOUCH_PAD0_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad0_th1; +#[doc = "LP_ANA_TOUCH_PAD0_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad0_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad0_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad0_th2`] module"] +pub type LP_ANA_TOUCH_PAD0_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad0_th2; +#[doc = "LP_ANA_TOUCH_PAD1_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad1_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad1_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad1_th0`] module"] +pub type LP_ANA_TOUCH_PAD1_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad1_th0; +#[doc = "LP_ANA_TOUCH_PAD1_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad1_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad1_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad1_th1`] module"] +pub type LP_ANA_TOUCH_PAD1_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad1_th1; +#[doc = "LP_ANA_TOUCH_PAD1_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad1_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad1_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad1_th2`] module"] +pub type LP_ANA_TOUCH_PAD1_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad1_th2; +#[doc = "LP_ANA_TOUCH_PAD2_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad2_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad2_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad2_th0`] module"] +pub type LP_ANA_TOUCH_PAD2_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad2_th0; +#[doc = "LP_ANA_TOUCH_PAD2_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad2_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad2_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad2_th1`] module"] +pub type LP_ANA_TOUCH_PAD2_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad2_th1; +#[doc = "LP_ANA_TOUCH_PAD2_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad2_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad2_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad2_th2`] module"] +pub type LP_ANA_TOUCH_PAD2_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad2_th2; +#[doc = "LP_ANA_TOUCH_PAD3_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad3_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad3_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad3_th0`] module"] +pub type LP_ANA_TOUCH_PAD3_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad3_th0; +#[doc = "LP_ANA_TOUCH_PAD3_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad3_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad3_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad3_th1`] module"] +pub type LP_ANA_TOUCH_PAD3_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad3_th1; +#[doc = "LP_ANA_TOUCH_PAD3_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad3_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad3_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad3_th2`] module"] +pub type LP_ANA_TOUCH_PAD3_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad3_th2; +#[doc = "LP_ANA_TOUCH_PAD4_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad4_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad4_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad4_th0`] module"] +pub type LP_ANA_TOUCH_PAD4_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad4_th0; +#[doc = "LP_ANA_TOUCH_PAD4_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad4_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad4_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad4_th1`] module"] +pub type LP_ANA_TOUCH_PAD4_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad4_th1; +#[doc = "LP_ANA_TOUCH_PAD4_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad4_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad4_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad4_th2`] module"] +pub type LP_ANA_TOUCH_PAD4_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad4_th2; +#[doc = "LP_ANA_TOUCH_PAD5_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad5_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad5_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad5_th0`] module"] +pub type LP_ANA_TOUCH_PAD5_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad5_th0; +#[doc = "LP_ANA_TOUCH_PAD5_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad5_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad5_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad5_th1`] module"] +pub type LP_ANA_TOUCH_PAD5_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad5_th1; +#[doc = "LP_ANA_TOUCH_PAD5_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad5_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad5_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad5_th2`] module"] +pub type LP_ANA_TOUCH_PAD5_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad5_th2; +#[doc = "LP_ANA_TOUCH_PAD6_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad6_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad6_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad6_th0`] module"] +pub type LP_ANA_TOUCH_PAD6_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad6_th0; +#[doc = "LP_ANA_TOUCH_PAD6_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad6_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad6_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad6_th1`] module"] +pub type LP_ANA_TOUCH_PAD6_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad6_th1; +#[doc = "LP_ANA_TOUCH_PAD6_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad6_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad6_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad6_th2`] module"] +pub type LP_ANA_TOUCH_PAD6_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad6_th2; +#[doc = "LP_ANA_TOUCH_PAD7_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad7_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad7_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad7_th0`] module"] +pub type LP_ANA_TOUCH_PAD7_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad7_th0; +#[doc = "LP_ANA_TOUCH_PAD7_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad7_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad7_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad7_th1`] module"] +pub type LP_ANA_TOUCH_PAD7_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad7_th1; +#[doc = "LP_ANA_TOUCH_PAD7_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad7_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad7_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad7_th2`] module"] +pub type LP_ANA_TOUCH_PAD7_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad7_th2; +#[doc = "LP_ANA_TOUCH_PAD8_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad8_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad8_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad8_th0`] module"] +pub type LP_ANA_TOUCH_PAD8_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad8_th0; +#[doc = "LP_ANA_TOUCH_PAD8_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad8_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad8_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad8_th1`] module"] +pub type LP_ANA_TOUCH_PAD8_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad8_th1; +#[doc = "LP_ANA_TOUCH_PAD8_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad8_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad8_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad8_th2`] module"] +pub type LP_ANA_TOUCH_PAD8_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad8_th2; +#[doc = "LP_ANA_TOUCH_PAD9_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad9_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad9_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad9_th0`] module"] +pub type LP_ANA_TOUCH_PAD9_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad9_th0; +#[doc = "LP_ANA_TOUCH_PAD9_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad9_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad9_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad9_th1`] module"] +pub type LP_ANA_TOUCH_PAD9_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad9_th1; +#[doc = "LP_ANA_TOUCH_PAD9_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad9_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad9_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad9_th2`] module"] +pub type LP_ANA_TOUCH_PAD9_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad9_th2; +#[doc = "LP_ANA_TOUCH_PAD10_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad10_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad10_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad10_th0`] module"] +pub type LP_ANA_TOUCH_PAD10_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad10_th0; +#[doc = "LP_ANA_TOUCH_PAD10_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad10_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad10_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad10_th1`] module"] +pub type LP_ANA_TOUCH_PAD10_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad10_th1; +#[doc = "LP_ANA_TOUCH_PAD10_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad10_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad10_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad10_th2`] module"] +pub type LP_ANA_TOUCH_PAD10_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad10_th2; +#[doc = "LP_ANA_TOUCH_PAD11_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad11_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad11_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad11_th0`] module"] +pub type LP_ANA_TOUCH_PAD11_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad11_th0; +#[doc = "LP_ANA_TOUCH_PAD11_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad11_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad11_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad11_th1`] module"] +pub type LP_ANA_TOUCH_PAD11_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad11_th1; +#[doc = "LP_ANA_TOUCH_PAD11_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad11_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad11_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad11_th2`] module"] +pub type LP_ANA_TOUCH_PAD11_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad11_th2; +#[doc = "LP_ANA_TOUCH_PAD12_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad12_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad12_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad12_th0`] module"] +pub type LP_ANA_TOUCH_PAD12_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad12_th0; +#[doc = "LP_ANA_TOUCH_PAD12_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad12_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad12_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad12_th1`] module"] +pub type LP_ANA_TOUCH_PAD12_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad12_th1; +#[doc = "LP_ANA_TOUCH_PAD12_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad12_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad12_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad12_th2`] module"] +pub type LP_ANA_TOUCH_PAD12_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad12_th2; +#[doc = "LP_ANA_TOUCH_PAD13_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad13_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad13_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad13_th0`] module"] +pub type LP_ANA_TOUCH_PAD13_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad13_th0; +#[doc = "LP_ANA_TOUCH_PAD13_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad13_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad13_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad13_th1`] module"] +pub type LP_ANA_TOUCH_PAD13_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad13_th1; +#[doc = "LP_ANA_TOUCH_PAD13_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad13_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad13_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad13_th2`] module"] +pub type LP_ANA_TOUCH_PAD13_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad13_th2; +#[doc = "LP_ANA_TOUCH_PAD14_TH0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad14_th0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad14_th0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad14_th0`] module"] +pub type LP_ANA_TOUCH_PAD14_TH0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad14_th0; +#[doc = "LP_ANA_TOUCH_PAD14_TH1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad14_th1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad14_th1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad14_th1`] module"] +pub type LP_ANA_TOUCH_PAD14_TH1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad14_th1; +#[doc = "LP_ANA_TOUCH_PAD14_TH2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad14_th2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad14_th2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_touch_pad14_th2`] module"] +pub type LP_ANA_TOUCH_PAD14_TH2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_touch_pad14_th2; +#[doc = "LP_ANA_DATE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_ana_date`] module"] +pub type LP_ANA_DATE = crate::Reg; +#[doc = "need_des"] +pub mod lp_ana_date; diff --git a/esp32p4/src/lp_ana_peri/lp_ana_bod_mode0_cntl.rs b/esp32p4/src/lp_ana_peri/lp_ana_bod_mode0_cntl.rs new file mode 100644 index 0000000000..3c417ddcb1 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_bod_mode0_cntl.rs @@ -0,0 +1,215 @@ +#[doc = "Register `LP_ANA_BOD_MODE0_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_BOD_MODE0_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA` reader - need_des"] +pub type LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA` writer - need_des"] +pub type LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_BOD_MODE0_PD_RF_ENA` reader - need_des"] +pub type LP_ANA_BOD_MODE0_PD_RF_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE0_PD_RF_ENA` writer - need_des"] +pub type LP_ANA_BOD_MODE0_PD_RF_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_BOD_MODE0_INTR_WAIT` reader - need_des"] +pub type LP_ANA_BOD_MODE0_INTR_WAIT_R = crate::FieldReader; +#[doc = "Field `LP_ANA_BOD_MODE0_INTR_WAIT` writer - need_des"] +pub type LP_ANA_BOD_MODE0_INTR_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `LP_ANA_BOD_MODE0_RESET_WAIT` reader - need_des"] +pub type LP_ANA_BOD_MODE0_RESET_WAIT_R = crate::FieldReader; +#[doc = "Field `LP_ANA_BOD_MODE0_RESET_WAIT` writer - need_des"] +pub type LP_ANA_BOD_MODE0_RESET_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `LP_ANA_BOD_MODE0_CNT_CLR` reader - need_des"] +pub type LP_ANA_BOD_MODE0_CNT_CLR_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE0_CNT_CLR` writer - need_des"] +pub type LP_ANA_BOD_MODE0_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_BOD_MODE0_INTR_ENA` reader - need_des"] +pub type LP_ANA_BOD_MODE0_INTR_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE0_INTR_ENA` writer - need_des"] +pub type LP_ANA_BOD_MODE0_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_BOD_MODE0_RESET_SEL` reader - need_des"] +pub type LP_ANA_BOD_MODE0_RESET_SEL_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE0_RESET_SEL` writer - need_des"] +pub type LP_ANA_BOD_MODE0_RESET_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_BOD_MODE0_RESET_ENA` reader - need_des"] +pub type LP_ANA_BOD_MODE0_RESET_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE0_RESET_ENA` writer - need_des"] +pub type LP_ANA_BOD_MODE0_RESET_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 6 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_close_flash_ena(&self) -> LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_R { + LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_pd_rf_ena(&self) -> LP_ANA_BOD_MODE0_PD_RF_ENA_R { + LP_ANA_BOD_MODE0_PD_RF_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:17 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_intr_wait(&self) -> LP_ANA_BOD_MODE0_INTR_WAIT_R { + LP_ANA_BOD_MODE0_INTR_WAIT_R::new(((self.bits >> 8) & 0x03ff) as u16) + } + #[doc = "Bits 18:27 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_reset_wait(&self) -> LP_ANA_BOD_MODE0_RESET_WAIT_R { + LP_ANA_BOD_MODE0_RESET_WAIT_R::new(((self.bits >> 18) & 0x03ff) as u16) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_cnt_clr(&self) -> LP_ANA_BOD_MODE0_CNT_CLR_R { + LP_ANA_BOD_MODE0_CNT_CLR_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_intr_ena(&self) -> LP_ANA_BOD_MODE0_INTR_ENA_R { + LP_ANA_BOD_MODE0_INTR_ENA_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_reset_sel(&self) -> LP_ANA_BOD_MODE0_RESET_SEL_R { + LP_ANA_BOD_MODE0_RESET_SEL_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_reset_ena(&self) -> LP_ANA_BOD_MODE0_RESET_ENA_R { + LP_ANA_BOD_MODE0_RESET_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_BOD_MODE0_CNTL") + .field( + "lp_ana_bod_mode0_close_flash_ena", + &format_args!("{}", self.lp_ana_bod_mode0_close_flash_ena().bit()), + ) + .field( + "lp_ana_bod_mode0_pd_rf_ena", + &format_args!("{}", self.lp_ana_bod_mode0_pd_rf_ena().bit()), + ) + .field( + "lp_ana_bod_mode0_intr_wait", + &format_args!("{}", self.lp_ana_bod_mode0_intr_wait().bits()), + ) + .field( + "lp_ana_bod_mode0_reset_wait", + &format_args!("{}", self.lp_ana_bod_mode0_reset_wait().bits()), + ) + .field( + "lp_ana_bod_mode0_cnt_clr", + &format_args!("{}", self.lp_ana_bod_mode0_cnt_clr().bit()), + ) + .field( + "lp_ana_bod_mode0_intr_ena", + &format_args!("{}", self.lp_ana_bod_mode0_intr_ena().bit()), + ) + .field( + "lp_ana_bod_mode0_reset_sel", + &format_args!("{}", self.lp_ana_bod_mode0_reset_sel().bit()), + ) + .field( + "lp_ana_bod_mode0_reset_ena", + &format_args!("{}", self.lp_ana_bod_mode0_reset_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 6 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_close_flash_ena( + &mut self, + ) -> LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_W { + LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_pd_rf_ena( + &mut self, + ) -> LP_ANA_BOD_MODE0_PD_RF_ENA_W { + LP_ANA_BOD_MODE0_PD_RF_ENA_W::new(self, 7) + } + #[doc = "Bits 8:17 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_intr_wait( + &mut self, + ) -> LP_ANA_BOD_MODE0_INTR_WAIT_W { + LP_ANA_BOD_MODE0_INTR_WAIT_W::new(self, 8) + } + #[doc = "Bits 18:27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_reset_wait( + &mut self, + ) -> LP_ANA_BOD_MODE0_RESET_WAIT_W { + LP_ANA_BOD_MODE0_RESET_WAIT_W::new(self, 18) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_cnt_clr( + &mut self, + ) -> LP_ANA_BOD_MODE0_CNT_CLR_W { + LP_ANA_BOD_MODE0_CNT_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_intr_ena( + &mut self, + ) -> LP_ANA_BOD_MODE0_INTR_ENA_W { + LP_ANA_BOD_MODE0_INTR_ENA_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_reset_sel( + &mut self, + ) -> LP_ANA_BOD_MODE0_RESET_SEL_W { + LP_ANA_BOD_MODE0_RESET_SEL_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_reset_ena( + &mut self, + ) -> LP_ANA_BOD_MODE0_RESET_ENA_W { + LP_ANA_BOD_MODE0_RESET_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_bod_mode0_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_bod_mode0_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_BOD_MODE0_CNTL_SPEC; +impl crate::RegisterSpec for LP_ANA_BOD_MODE0_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_bod_mode0_cntl::R`](R) reader structure"] +impl crate::Readable for LP_ANA_BOD_MODE0_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_bod_mode0_cntl::W`](W) writer structure"] +impl crate::Writable for LP_ANA_BOD_MODE0_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_BOD_MODE0_CNTL to value 0x0ffc_0100"] +impl crate::Resettable for LP_ANA_BOD_MODE0_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x0ffc_0100; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_bod_mode1_cntl.rs b/esp32p4/src/lp_ana_peri/lp_ana_bod_mode1_cntl.rs new file mode 100644 index 0000000000..f11bdfba2c --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_bod_mode1_cntl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_BOD_MODE1_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_BOD_MODE1_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_BOD_MODE1_RESET_ENA` reader - need_des"] +pub type LP_ANA_BOD_MODE1_RESET_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE1_RESET_ENA` writer - need_des"] +pub type LP_ANA_BOD_MODE1_RESET_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode1_reset_ena(&self) -> LP_ANA_BOD_MODE1_RESET_ENA_R { + LP_ANA_BOD_MODE1_RESET_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_BOD_MODE1_CNTL") + .field( + "lp_ana_bod_mode1_reset_ena", + &format_args!("{}", self.lp_ana_bod_mode1_reset_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode1_reset_ena( + &mut self, + ) -> LP_ANA_BOD_MODE1_RESET_ENA_W { + LP_ANA_BOD_MODE1_RESET_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_bod_mode1_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_bod_mode1_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_BOD_MODE1_CNTL_SPEC; +impl crate::RegisterSpec for LP_ANA_BOD_MODE1_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_bod_mode1_cntl::R`](R) reader structure"] +impl crate::Readable for LP_ANA_BOD_MODE1_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_bod_mode1_cntl::W`](W) writer structure"] +impl crate::Writable for LP_ANA_BOD_MODE1_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_BOD_MODE1_CNTL to value 0"] +impl crate::Resettable for LP_ANA_BOD_MODE1_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_ck_glitch_cntl.rs b/esp32p4/src/lp_ana_peri/lp_ana_ck_glitch_cntl.rs new file mode 100644 index 0000000000..7dab846d36 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_ck_glitch_cntl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_CK_GLITCH_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_CK_GLITCH_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_CK_GLITCH_RESET_ENA` reader - need_des"] +pub type LP_ANA_CK_GLITCH_RESET_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_CK_GLITCH_RESET_ENA` writer - need_des"] +pub type LP_ANA_CK_GLITCH_RESET_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_ck_glitch_reset_ena(&self) -> LP_ANA_CK_GLITCH_RESET_ENA_R { + LP_ANA_CK_GLITCH_RESET_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_CK_GLITCH_CNTL") + .field( + "lp_ana_ck_glitch_reset_ena", + &format_args!("{}", self.lp_ana_ck_glitch_reset_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_ck_glitch_reset_ena( + &mut self, + ) -> LP_ANA_CK_GLITCH_RESET_ENA_W { + LP_ANA_CK_GLITCH_RESET_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_ck_glitch_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_ck_glitch_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_CK_GLITCH_CNTL_SPEC; +impl crate::RegisterSpec for LP_ANA_CK_GLITCH_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_ck_glitch_cntl::R`](R) reader structure"] +impl crate::Readable for LP_ANA_CK_GLITCH_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_ck_glitch_cntl::W`](W) writer structure"] +impl crate::Writable for LP_ANA_CK_GLITCH_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_CK_GLITCH_CNTL to value 0"] +impl crate::Resettable for LP_ANA_CK_GLITCH_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_date.rs b/esp32p4/src/lp_ana_peri/lp_ana_date.rs new file mode 100644 index 0000000000..f4654308e0 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_date.rs @@ -0,0 +1,85 @@ +#[doc = "Register `LP_ANA_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_LP_ANA_DATE` reader - need_des"] +pub type LP_ANA_LP_ANA_DATE_R = crate::FieldReader; +#[doc = "Field `LP_ANA_LP_ANA_DATE` writer - need_des"] +pub type LP_ANA_LP_ANA_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `LP_ANA_CLK_EN` reader - need_des"] +pub type LP_ANA_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_ANA_CLK_EN` writer - need_des"] +pub type LP_ANA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn lp_ana_lp_ana_date(&self) -> LP_ANA_LP_ANA_DATE_R { + LP_ANA_LP_ANA_DATE_R::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_clk_en(&self) -> LP_ANA_CLK_EN_R { + LP_ANA_CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_DATE") + .field( + "lp_ana_lp_ana_date", + &format_args!("{}", self.lp_ana_lp_ana_date().bits()), + ) + .field( + "lp_ana_clk_en", + &format_args!("{}", self.lp_ana_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_lp_ana_date(&mut self) -> LP_ANA_LP_ANA_DATE_W { + LP_ANA_LP_ANA_DATE_W::new(self, 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_clk_en(&mut self) -> LP_ANA_CLK_EN_W { + LP_ANA_CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_DATE_SPEC; +impl crate::RegisterSpec for LP_ANA_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_date::R`](R) reader structure"] +impl crate::Readable for LP_ANA_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_date::W`](W) writer structure"] +impl crate::Writable for LP_ANA_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_DATE to value 0x0023_0420"] +impl crate::Resettable for LP_ANA_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0023_0420; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_fib_enable.rs b/esp32p4/src/lp_ana_peri/lp_ana_fib_enable.rs new file mode 100644 index 0000000000..2ec1a4cebf --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_fib_enable.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_FIB_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_FIB_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_ANA_FIB_ENA` reader - need_des"] +pub type LP_ANA_ANA_FIB_ENA_R = crate::FieldReader; +#[doc = "Field `LP_ANA_ANA_FIB_ENA` writer - need_des"] +pub type LP_ANA_ANA_FIB_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_ana_ana_fib_ena(&self) -> LP_ANA_ANA_FIB_ENA_R { + LP_ANA_ANA_FIB_ENA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_FIB_ENABLE") + .field( + "lp_ana_ana_fib_ena", + &format_args!("{}", self.lp_ana_ana_fib_ena().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_ana_fib_ena(&mut self) -> LP_ANA_ANA_FIB_ENA_W { + LP_ANA_ANA_FIB_ENA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_fib_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_fib_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_FIB_ENABLE_SPEC; +impl crate::RegisterSpec for LP_ANA_FIB_ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_fib_enable::R`](R) reader structure"] +impl crate::Readable for LP_ANA_FIB_ENABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_fib_enable::W`](W) writer structure"] +impl crate::Writable for LP_ANA_FIB_ENABLE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_FIB_ENABLE to value 0xffff_ffff"] +impl crate::Resettable for LP_ANA_FIB_ENABLE_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_int_clr.rs b/esp32p4/src/lp_ana_peri/lp_ana_int_clr.rs new file mode 100644 index 0000000000..02ec6a3730 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_int_clr.rs @@ -0,0 +1,82 @@ +#[doc = "Register `LP_ANA_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR` writer - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR` writer - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR` writer - need_des"] +pub type LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR` writer - need_des"] +pub type LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_BOD_MODE0_INT_CLR` writer - need_des"] +pub type LP_ANA_BOD_MODE0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_charge_upvoltage_int_clr( + &mut self, + ) -> LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_W { + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_charge_undervoltage_int_clr( + &mut self, + ) -> LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_W { + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_upvoltage_int_clr( + &mut self, + ) -> LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_W { + LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_undervoltage_int_clr( + &mut self, + ) -> LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_W { + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_int_clr(&mut self) -> LP_ANA_BOD_MODE0_INT_CLR_W { + LP_ANA_BOD_MODE0_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_INT_CLR_SPEC; +impl crate::RegisterSpec for LP_ANA_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`lp_ana_int_clr::W`](W) writer structure"] +impl crate::Writable for LP_ANA_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_INT_CLR to value 0"] +impl crate::Resettable for LP_ANA_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_int_ena.rs b/esp32p4/src/lp_ana_peri/lp_ana_int_ena.rs new file mode 100644 index 0000000000..49e52da30a --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_int_ena.rs @@ -0,0 +1,154 @@ +#[doc = "Register `LP_ANA_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA` writer - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA` writer - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA` reader - need_des"] +pub type LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA` writer - need_des"] +pub type LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA` reader - need_des"] +pub type LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA` writer - need_des"] +pub type LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_BOD_MODE0_INT_ENA` reader - need_des"] +pub type LP_ANA_BOD_MODE0_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE0_INT_ENA` writer - need_des"] +pub type LP_ANA_BOD_MODE0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charge_upvoltage_int_ena( + &self, + ) -> LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_R { + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charge_undervoltage_int_ena( + &self, + ) -> LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_R { + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_upvoltage_int_ena(&self) -> LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_R { + LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_undervoltage_int_ena(&self) -> LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_R { + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_int_ena(&self) -> LP_ANA_BOD_MODE0_INT_ENA_R { + LP_ANA_BOD_MODE0_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_INT_ENA") + .field( + "lp_ana_vddbat_charge_upvoltage_int_ena", + &format_args!("{}", self.lp_ana_vddbat_charge_upvoltage_int_ena().bit()), + ) + .field( + "lp_ana_vddbat_charge_undervoltage_int_ena", + &format_args!("{}", self.lp_ana_vddbat_charge_undervoltage_int_ena().bit()), + ) + .field( + "lp_ana_vddbat_upvoltage_int_ena", + &format_args!("{}", self.lp_ana_vddbat_upvoltage_int_ena().bit()), + ) + .field( + "lp_ana_vddbat_undervoltage_int_ena", + &format_args!("{}", self.lp_ana_vddbat_undervoltage_int_ena().bit()), + ) + .field( + "lp_ana_bod_mode0_int_ena", + &format_args!("{}", self.lp_ana_bod_mode0_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_charge_upvoltage_int_ena( + &mut self, + ) -> LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_W { + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_charge_undervoltage_int_ena( + &mut self, + ) -> LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_W { + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_upvoltage_int_ena( + &mut self, + ) -> LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_W { + LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_undervoltage_int_ena( + &mut self, + ) -> LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_W { + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_int_ena(&mut self) -> LP_ANA_BOD_MODE0_INT_ENA_W { + LP_ANA_BOD_MODE0_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_INT_ENA_SPEC; +impl crate::RegisterSpec for LP_ANA_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_int_ena::R`](R) reader structure"] +impl crate::Readable for LP_ANA_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_int_ena::W`](W) writer structure"] +impl crate::Writable for LP_ANA_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_INT_ENA to value 0"] +impl crate::Resettable for LP_ANA_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_int_raw.rs b/esp32p4/src/lp_ana_peri/lp_ana_int_raw.rs new file mode 100644 index 0000000000..269c95db3c --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_int_raw.rs @@ -0,0 +1,154 @@ +#[doc = "Register `LP_ANA_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW` writer - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW` writer - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW` reader - need_des"] +pub type LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW` writer - need_des"] +pub type LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW` reader - need_des"] +pub type LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW` writer - need_des"] +pub type LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_BOD_MODE0_INT_RAW` reader - need_des"] +pub type LP_ANA_BOD_MODE0_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE0_INT_RAW` writer - need_des"] +pub type LP_ANA_BOD_MODE0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charge_upvoltage_int_raw( + &self, + ) -> LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_R { + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charge_undervoltage_int_raw( + &self, + ) -> LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_R { + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_upvoltage_int_raw(&self) -> LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_R { + LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_undervoltage_int_raw(&self) -> LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_R { + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_int_raw(&self) -> LP_ANA_BOD_MODE0_INT_RAW_R { + LP_ANA_BOD_MODE0_INT_RAW_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_INT_RAW") + .field( + "lp_ana_vddbat_charge_upvoltage_int_raw", + &format_args!("{}", self.lp_ana_vddbat_charge_upvoltage_int_raw().bit()), + ) + .field( + "lp_ana_vddbat_charge_undervoltage_int_raw", + &format_args!("{}", self.lp_ana_vddbat_charge_undervoltage_int_raw().bit()), + ) + .field( + "lp_ana_vddbat_upvoltage_int_raw", + &format_args!("{}", self.lp_ana_vddbat_upvoltage_int_raw().bit()), + ) + .field( + "lp_ana_vddbat_undervoltage_int_raw", + &format_args!("{}", self.lp_ana_vddbat_undervoltage_int_raw().bit()), + ) + .field( + "lp_ana_bod_mode0_int_raw", + &format_args!("{}", self.lp_ana_bod_mode0_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_charge_upvoltage_int_raw( + &mut self, + ) -> LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_W { + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_charge_undervoltage_int_raw( + &mut self, + ) -> LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_W { + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_upvoltage_int_raw( + &mut self, + ) -> LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_W { + LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_undervoltage_int_raw( + &mut self, + ) -> LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_W { + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_int_raw(&mut self) -> LP_ANA_BOD_MODE0_INT_RAW_W { + LP_ANA_BOD_MODE0_INT_RAW_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_INT_RAW_SPEC; +impl crate::RegisterSpec for LP_ANA_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_int_raw::R`](R) reader structure"] +impl crate::Readable for LP_ANA_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_int_raw::W`](W) writer structure"] +impl crate::Writable for LP_ANA_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_INT_RAW to value 0"] +impl crate::Resettable for LP_ANA_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_int_st.rs b/esp32p4/src/lp_ana_peri/lp_ana_int_st.rs new file mode 100644 index 0000000000..c3b43dfc94 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_int_st.rs @@ -0,0 +1,85 @@ +#[doc = "Register `LP_ANA_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_UPVOLTAGE_INT_ST` reader - need_des"] +pub type LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST` reader - need_des"] +pub type LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE0_INT_ST` reader - need_des"] +pub type LP_ANA_BOD_MODE0_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charge_upvoltage_int_st(&self) -> LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_R { + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charge_undervoltage_int_st( + &self, + ) -> LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_R { + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_upvoltage_int_st(&self) -> LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_R { + LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_undervoltage_int_st(&self) -> LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_R { + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_int_st(&self) -> LP_ANA_BOD_MODE0_INT_ST_R { + LP_ANA_BOD_MODE0_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_INT_ST") + .field( + "lp_ana_vddbat_charge_upvoltage_int_st", + &format_args!("{}", self.lp_ana_vddbat_charge_upvoltage_int_st().bit()), + ) + .field( + "lp_ana_vddbat_charge_undervoltage_int_st", + &format_args!("{}", self.lp_ana_vddbat_charge_undervoltage_int_st().bit()), + ) + .field( + "lp_ana_vddbat_upvoltage_int_st", + &format_args!("{}", self.lp_ana_vddbat_upvoltage_int_st().bit()), + ) + .field( + "lp_ana_vddbat_undervoltage_int_st", + &format_args!("{}", self.lp_ana_vddbat_undervoltage_int_st().bit()), + ) + .field( + "lp_ana_bod_mode0_int_st", + &format_args!("{}", self.lp_ana_bod_mode0_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_INT_ST_SPEC; +impl crate::RegisterSpec for LP_ANA_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_int_st::R`](R) reader structure"] +impl crate::Readable for LP_ANA_INT_ST_SPEC {} +#[doc = "`reset()` method sets LP_ANA_INT_ST to value 0"] +impl crate::Resettable for LP_ANA_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_lp_int_clr.rs b/esp32p4/src/lp_ana_peri/lp_ana_lp_int_clr.rs new file mode 100644 index 0000000000..49fce67af8 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_lp_int_clr.rs @@ -0,0 +1,44 @@ +#[doc = "Register `LP_ANA_LP_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_BOD_MODE0_LP_INT_CLR` writer - need_des"] +pub type LP_ANA_BOD_MODE0_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_lp_int_clr( + &mut self, + ) -> LP_ANA_BOD_MODE0_LP_INT_CLR_W { + LP_ANA_BOD_MODE0_LP_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_lp_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_LP_INT_CLR_SPEC; +impl crate::RegisterSpec for LP_ANA_LP_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`lp_ana_lp_int_clr::W`](W) writer structure"] +impl crate::Writable for LP_ANA_LP_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_LP_INT_CLR to value 0"] +impl crate::Resettable for LP_ANA_LP_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_lp_int_ena.rs b/esp32p4/src/lp_ana_peri/lp_ana_lp_int_ena.rs new file mode 100644 index 0000000000..19583d690b --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_lp_int_ena.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_LP_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_LP_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_BOD_MODE0_LP_INT_ENA` reader - need_des"] +pub type LP_ANA_BOD_MODE0_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE0_LP_INT_ENA` writer - need_des"] +pub type LP_ANA_BOD_MODE0_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_lp_int_ena(&self) -> LP_ANA_BOD_MODE0_LP_INT_ENA_R { + LP_ANA_BOD_MODE0_LP_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_LP_INT_ENA") + .field( + "lp_ana_bod_mode0_lp_int_ena", + &format_args!("{}", self.lp_ana_bod_mode0_lp_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_lp_int_ena( + &mut self, + ) -> LP_ANA_BOD_MODE0_LP_INT_ENA_W { + LP_ANA_BOD_MODE0_LP_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_lp_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_lp_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_LP_INT_ENA_SPEC; +impl crate::RegisterSpec for LP_ANA_LP_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_lp_int_ena::R`](R) reader structure"] +impl crate::Readable for LP_ANA_LP_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_lp_int_ena::W`](W) writer structure"] +impl crate::Writable for LP_ANA_LP_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_LP_INT_ENA to value 0"] +impl crate::Resettable for LP_ANA_LP_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_lp_int_raw.rs b/esp32p4/src/lp_ana_peri/lp_ana_lp_int_raw.rs new file mode 100644 index 0000000000..0a28303f28 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_lp_int_raw.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_LP_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_LP_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_BOD_MODE0_LP_INT_RAW` reader - need_des"] +pub type LP_ANA_BOD_MODE0_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_ANA_BOD_MODE0_LP_INT_RAW` writer - need_des"] +pub type LP_ANA_BOD_MODE0_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_lp_int_raw(&self) -> LP_ANA_BOD_MODE0_LP_INT_RAW_R { + LP_ANA_BOD_MODE0_LP_INT_RAW_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_LP_INT_RAW") + .field( + "lp_ana_bod_mode0_lp_int_raw", + &format_args!("{}", self.lp_ana_bod_mode0_lp_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_mode0_lp_int_raw( + &mut self, + ) -> LP_ANA_BOD_MODE0_LP_INT_RAW_W { + LP_ANA_BOD_MODE0_LP_INT_RAW_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_lp_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_lp_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_LP_INT_RAW_SPEC; +impl crate::RegisterSpec for LP_ANA_LP_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_lp_int_raw::R`](R) reader structure"] +impl crate::Readable for LP_ANA_LP_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_lp_int_raw::W`](W) writer structure"] +impl crate::Writable for LP_ANA_LP_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_LP_INT_RAW to value 0"] +impl crate::Resettable for LP_ANA_LP_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_lp_int_st.rs b/esp32p4/src/lp_ana_peri/lp_ana_lp_int_st.rs new file mode 100644 index 0000000000..e363a92c53 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_lp_int_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `LP_ANA_LP_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `LP_ANA_BOD_MODE0_LP_INT_ST` reader - need_des"] +pub type LP_ANA_BOD_MODE0_LP_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_mode0_lp_int_st(&self) -> LP_ANA_BOD_MODE0_LP_INT_ST_R { + LP_ANA_BOD_MODE0_LP_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_LP_INT_ST") + .field( + "lp_ana_bod_mode0_lp_int_st", + &format_args!("{}", self.lp_ana_bod_mode0_lp_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_lp_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_LP_INT_ST_SPEC; +impl crate::RegisterSpec for LP_ANA_LP_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_lp_int_st::R`](R) reader structure"] +impl crate::Readable for LP_ANA_LP_INT_ST_SPEC {} +#[doc = "`reset()` method sets LP_ANA_LP_INT_ST to value 0"] +impl crate::Resettable for LP_ANA_LP_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_pg_glitch_cntl.rs b/esp32p4/src/lp_ana_peri/lp_ana_pg_glitch_cntl.rs new file mode 100644 index 0000000000..4901653b54 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_pg_glitch_cntl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_PG_GLITCH_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_PG_GLITCH_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_POWER_GLITCH_RESET_ENA` reader - need_des"] +pub type LP_ANA_POWER_GLITCH_RESET_ENA_R = crate::BitReader; +#[doc = "Field `LP_ANA_POWER_GLITCH_RESET_ENA` writer - need_des"] +pub type LP_ANA_POWER_GLITCH_RESET_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_power_glitch_reset_ena(&self) -> LP_ANA_POWER_GLITCH_RESET_ENA_R { + LP_ANA_POWER_GLITCH_RESET_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_PG_GLITCH_CNTL") + .field( + "lp_ana_power_glitch_reset_ena", + &format_args!("{}", self.lp_ana_power_glitch_reset_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_power_glitch_reset_ena( + &mut self, + ) -> LP_ANA_POWER_GLITCH_RESET_ENA_W { + LP_ANA_POWER_GLITCH_RESET_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_pg_glitch_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_pg_glitch_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_PG_GLITCH_CNTL_SPEC; +impl crate::RegisterSpec for LP_ANA_PG_GLITCH_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_pg_glitch_cntl::R`](R) reader structure"] +impl crate::Readable for LP_ANA_PG_GLITCH_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_pg_glitch_cntl::W`](W) writer structure"] +impl crate::Writable for LP_ANA_PG_GLITCH_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_PG_GLITCH_CNTL to value 0"] +impl crate::Resettable for LP_ANA_PG_GLITCH_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_ana_para.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_ana_para.rs new file mode 100644 index 0000000000..5fad0e5507 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_ana_para.rs @@ -0,0 +1,110 @@ +#[doc = "Register `LP_ANA_TOUCH_ANA_PARA` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_ANA_PARA` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_TOUCH_BUF_DRV` reader - need_des"] +pub type LP_ANA_TOUCH_TOUCH_BUF_DRV_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_TOUCH_BUF_DRV` writer - need_des"] +pub type LP_ANA_TOUCH_TOUCH_BUF_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LP_ANA_TOUCH_TOUCH_EN_CAL` reader - need_des"] +pub type LP_ANA_TOUCH_TOUCH_EN_CAL_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_TOUCH_EN_CAL` writer - need_des"] +pub type LP_ANA_TOUCH_TOUCH_EN_CAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_TOUCH_DCAP_CAL` reader - need_des"] +pub type LP_ANA_TOUCH_TOUCH_DCAP_CAL_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_TOUCH_DCAP_CAL` writer - need_des"] +pub type LP_ANA_TOUCH_TOUCH_DCAP_CAL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:2 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_touch_buf_drv(&self) -> LP_ANA_TOUCH_TOUCH_BUF_DRV_R { + LP_ANA_TOUCH_TOUCH_BUF_DRV_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_touch_en_cal(&self) -> LP_ANA_TOUCH_TOUCH_EN_CAL_R { + LP_ANA_TOUCH_TOUCH_EN_CAL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:10 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_touch_dcap_cal(&self) -> LP_ANA_TOUCH_TOUCH_DCAP_CAL_R { + LP_ANA_TOUCH_TOUCH_DCAP_CAL_R::new(((self.bits >> 4) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_ANA_PARA") + .field( + "lp_ana_touch_touch_buf_drv", + &format_args!("{}", self.lp_ana_touch_touch_buf_drv().bits()), + ) + .field( + "lp_ana_touch_touch_en_cal", + &format_args!("{}", self.lp_ana_touch_touch_en_cal().bit()), + ) + .field( + "lp_ana_touch_touch_dcap_cal", + &format_args!("{}", self.lp_ana_touch_touch_dcap_cal().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_touch_buf_drv( + &mut self, + ) -> LP_ANA_TOUCH_TOUCH_BUF_DRV_W { + LP_ANA_TOUCH_TOUCH_BUF_DRV_W::new(self, 0) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_touch_en_cal( + &mut self, + ) -> LP_ANA_TOUCH_TOUCH_EN_CAL_W { + LP_ANA_TOUCH_TOUCH_EN_CAL_W::new(self, 3) + } + #[doc = "Bits 4:10 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_touch_dcap_cal( + &mut self, + ) -> LP_ANA_TOUCH_TOUCH_DCAP_CAL_W { + LP_ANA_TOUCH_TOUCH_DCAP_CAL_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_ana_para::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_ana_para::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_ANA_PARA_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_ANA_PARA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_ana_para::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_ANA_PARA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_ana_para::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_ANA_PARA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_ANA_PARA to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_ANA_PARA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_approach.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_approach.rs new file mode 100644 index 0000000000..72a93e6ce4 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_approach.rs @@ -0,0 +1,116 @@ +#[doc = "Register `LP_ANA_TOUCH_APPROACH` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_APPROACH` writer"] +pub type W = crate::W; +#[doc = "Field `PAD0` reader - need_des"] +pub type PAD0_R = crate::FieldReader; +#[doc = "Field `PAD0` writer - need_des"] +pub type PAD0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PAD1` reader - need_des"] +pub type PAD1_R = crate::FieldReader; +#[doc = "Field `PAD1` writer - need_des"] +pub type PAD1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PAD2` reader - need_des"] +pub type PAD2_R = crate::FieldReader; +#[doc = "Field `PAD2` writer - need_des"] +pub type PAD2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LP_ANA_TOUCH_SLP_APPROACH_EN` reader - need_des"] +pub type LP_ANA_TOUCH_SLP_APPROACH_EN_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_SLP_APPROACH_EN` writer - need_des"] +pub type LP_ANA_TOUCH_SLP_APPROACH_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - need_des"] + #[inline(always)] + pub fn pad0(&self) -> PAD0_R { + PAD0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - need_des"] + #[inline(always)] + pub fn pad1(&self) -> PAD1_R { + PAD1_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - need_des"] + #[inline(always)] + pub fn pad2(&self) -> PAD2_R { + PAD2_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_slp_approach_en(&self) -> LP_ANA_TOUCH_SLP_APPROACH_EN_R { + LP_ANA_TOUCH_SLP_APPROACH_EN_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_APPROACH") + .field("pad0", &format_args!("{}", self.pad0().bits())) + .field("pad1", &format_args!("{}", self.pad1().bits())) + .field("pad2", &format_args!("{}", self.pad2().bits())) + .field( + "lp_ana_touch_slp_approach_en", + &format_args!("{}", self.lp_ana_touch_slp_approach_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - need_des"] + #[inline(always)] + #[must_use] + pub fn pad0(&mut self) -> PAD0_W { + PAD0_W::new(self, 0) + } + #[doc = "Bits 4:7 - need_des"] + #[inline(always)] + #[must_use] + pub fn pad1(&mut self) -> PAD1_W { + PAD1_W::new(self, 4) + } + #[doc = "Bits 8:11 - need_des"] + #[inline(always)] + #[must_use] + pub fn pad2(&mut self) -> PAD2_W { + PAD2_W::new(self, 8) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_slp_approach_en( + &mut self, + ) -> LP_ANA_TOUCH_SLP_APPROACH_EN_W { + LP_ANA_TOUCH_SLP_APPROACH_EN_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_approach::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_approach::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_APPROACH_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_APPROACH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_approach::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_APPROACH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_approach::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_APPROACH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_APPROACH to value 0x0fff"] +impl crate::Resettable for LP_ANA_TOUCH_APPROACH_SPEC { + const RESET_VALUE: Self::Ux = 0x0fff; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_approach_work_meas_num.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_approach_work_meas_num.rs new file mode 100644 index 0000000000..d1b85dcb9c --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_approach_work_meas_num.rs @@ -0,0 +1,110 @@ +#[doc = "Register `LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_APPROACH_MEAS_NUM2` reader - need_des"] +pub type LP_ANA_TOUCH_APPROACH_MEAS_NUM2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_APPROACH_MEAS_NUM2` writer - need_des"] +pub type LP_ANA_TOUCH_APPROACH_MEAS_NUM2_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `LP_ANA_TOUCH_APPROACH_MEAS_NUM1` reader - need_des"] +pub type LP_ANA_TOUCH_APPROACH_MEAS_NUM1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_APPROACH_MEAS_NUM1` writer - need_des"] +pub type LP_ANA_TOUCH_APPROACH_MEAS_NUM1_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `LP_ANA_TOUCH_APPROACH_MEAS_NUM0` reader - need_des"] +pub type LP_ANA_TOUCH_APPROACH_MEAS_NUM0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_APPROACH_MEAS_NUM0` writer - need_des"] +pub type LP_ANA_TOUCH_APPROACH_MEAS_NUM0_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_approach_meas_num2(&self) -> LP_ANA_TOUCH_APPROACH_MEAS_NUM2_R { + LP_ANA_TOUCH_APPROACH_MEAS_NUM2_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:19 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_approach_meas_num1(&self) -> LP_ANA_TOUCH_APPROACH_MEAS_NUM1_R { + LP_ANA_TOUCH_APPROACH_MEAS_NUM1_R::new(((self.bits >> 10) & 0x03ff) as u16) + } + #[doc = "Bits 20:29 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_approach_meas_num0(&self) -> LP_ANA_TOUCH_APPROACH_MEAS_NUM0_R { + LP_ANA_TOUCH_APPROACH_MEAS_NUM0_R::new(((self.bits >> 20) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM") + .field( + "lp_ana_touch_approach_meas_num2", + &format_args!("{}", self.lp_ana_touch_approach_meas_num2().bits()), + ) + .field( + "lp_ana_touch_approach_meas_num1", + &format_args!("{}", self.lp_ana_touch_approach_meas_num1().bits()), + ) + .field( + "lp_ana_touch_approach_meas_num0", + &format_args!("{}", self.lp_ana_touch_approach_meas_num0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_approach_meas_num2( + &mut self, + ) -> LP_ANA_TOUCH_APPROACH_MEAS_NUM2_W { + LP_ANA_TOUCH_APPROACH_MEAS_NUM2_W::new(self, 0) + } + #[doc = "Bits 10:19 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_approach_meas_num1( + &mut self, + ) -> LP_ANA_TOUCH_APPROACH_MEAS_NUM1_W { + LP_ANA_TOUCH_APPROACH_MEAS_NUM1_W::new(self, 10) + } + #[doc = "Bits 20:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_approach_meas_num0( + &mut self, + ) -> LP_ANA_TOUCH_APPROACH_MEAS_NUM0_W { + LP_ANA_TOUCH_APPROACH_MEAS_NUM0_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_approach_work_meas_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_approach_work_meas_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_approach_work_meas_num::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_approach_work_meas_num::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM to value 0x0641_9064"] +impl crate::Resettable for LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0x0641_9064; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_clr.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_clr.rs new file mode 100644 index 0000000000..26cf940b6e --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_clr.rs @@ -0,0 +1,52 @@ +#[doc = "Register `LP_ANA_TOUCH_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_CHANNEL_CLR` writer - need_des"] +pub type LP_ANA_TOUCH_CHANNEL_CLR_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `LP_ANA_TOUCH_STATUS_CLR` writer - need_des"] +pub type LP_ANA_TOUCH_STATUS_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:14 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_channel_clr( + &mut self, + ) -> LP_ANA_TOUCH_CHANNEL_CLR_W { + LP_ANA_TOUCH_CHANNEL_CLR_W::new(self, 0) + } + #[doc = "Bit 15 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_status_clr(&mut self) -> LP_ANA_TOUCH_STATUS_CLR_W { + LP_ANA_TOUCH_STATUS_CLR_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_CLR_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_clr::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_CLR to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_filter1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_filter1.rs new file mode 100644 index 0000000000..9dd532731b --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_filter1.rs @@ -0,0 +1,283 @@ +#[doc = "Register `LP_ANA_TOUCH_FILTER1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_FILTER1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN` reader - Reserved"] +pub type LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN` writer - Reserved"] +pub type LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_HYSTERESIS` reader - need_des"] +pub type LP_ANA_TOUCH_HYSTERESIS_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_HYSTERESIS` writer - need_des"] +pub type LP_ANA_TOUCH_HYSTERESIS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_ANA_TOUCH_NEG_NOISE_THRES` reader - need_des"] +pub type LP_ANA_TOUCH_NEG_NOISE_THRES_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_NEG_NOISE_THRES` writer - need_des"] +pub type LP_ANA_TOUCH_NEG_NOISE_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_ANA_TOUCH_NOISE_THRES` reader - need_des"] +pub type LP_ANA_TOUCH_NOISE_THRES_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_NOISE_THRES` writer - need_des"] +pub type LP_ANA_TOUCH_NOISE_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_ANA_TOUCH_SMOOTH_LVL` reader - need_des"] +pub type LP_ANA_TOUCH_SMOOTH_LVL_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_SMOOTH_LVL` writer - need_des"] +pub type LP_ANA_TOUCH_SMOOTH_LVL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_ANA_TOUCH_JITTER_STEP` reader - need_des"] +pub type LP_ANA_TOUCH_JITTER_STEP_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_JITTER_STEP` writer - need_des"] +pub type LP_ANA_TOUCH_JITTER_STEP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LP_ANA_TOUCH_FILTER_MODE` reader - need_des"] +pub type LP_ANA_TOUCH_FILTER_MODE_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FILTER_MODE` writer - need_des"] +pub type LP_ANA_TOUCH_FILTER_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LP_ANA_TOUCH_FILTER_EN` reader - need_des"] +pub type LP_ANA_TOUCH_FILTER_EN_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_FILTER_EN` writer - need_des"] +pub type LP_ANA_TOUCH_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_NEG_NOISE_LIMIT` reader - need_des"] +pub type LP_ANA_TOUCH_NEG_NOISE_LIMIT_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_NEG_NOISE_LIMIT` writer - need_des"] +pub type LP_ANA_TOUCH_NEG_NOISE_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LP_ANA_TOUCH_APPROACH_LIMIT` reader - need_des"] +pub type LP_ANA_TOUCH_APPROACH_LIMIT_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_APPROACH_LIMIT` writer - need_des"] +pub type LP_ANA_TOUCH_APPROACH_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LP_ANA_TOUCH_DEBOUNCE_LIMIT` reader - need_des"] +pub type LP_ANA_TOUCH_DEBOUNCE_LIMIT_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_DEBOUNCE_LIMIT` writer - need_des"] +pub type LP_ANA_TOUCH_DEBOUNCE_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_neg_noise_disupdate_baseline_en( + &self, + ) -> LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_R { + LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_hysteresis(&self) -> LP_ANA_TOUCH_HYSTERESIS_R { + LP_ANA_TOUCH_HYSTERESIS_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bits 3:4 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_neg_noise_thres(&self) -> LP_ANA_TOUCH_NEG_NOISE_THRES_R { + LP_ANA_TOUCH_NEG_NOISE_THRES_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bits 5:6 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_noise_thres(&self) -> LP_ANA_TOUCH_NOISE_THRES_R { + LP_ANA_TOUCH_NOISE_THRES_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bits 7:8 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_smooth_lvl(&self) -> LP_ANA_TOUCH_SMOOTH_LVL_R { + LP_ANA_TOUCH_SMOOTH_LVL_R::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 9:12 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_jitter_step(&self) -> LP_ANA_TOUCH_JITTER_STEP_R { + LP_ANA_TOUCH_JITTER_STEP_R::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bits 13:15 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_filter_mode(&self) -> LP_ANA_TOUCH_FILTER_MODE_R { + LP_ANA_TOUCH_FILTER_MODE_R::new(((self.bits >> 13) & 7) as u8) + } + #[doc = "Bit 16 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_filter_en(&self) -> LP_ANA_TOUCH_FILTER_EN_R { + LP_ANA_TOUCH_FILTER_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:20 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_neg_noise_limit(&self) -> LP_ANA_TOUCH_NEG_NOISE_LIMIT_R { + LP_ANA_TOUCH_NEG_NOISE_LIMIT_R::new(((self.bits >> 17) & 0x0f) as u8) + } + #[doc = "Bits 21:28 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_approach_limit(&self) -> LP_ANA_TOUCH_APPROACH_LIMIT_R { + LP_ANA_TOUCH_APPROACH_LIMIT_R::new(((self.bits >> 21) & 0xff) as u8) + } + #[doc = "Bits 29:31 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_debounce_limit(&self) -> LP_ANA_TOUCH_DEBOUNCE_LIMIT_R { + LP_ANA_TOUCH_DEBOUNCE_LIMIT_R::new(((self.bits >> 29) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_FILTER1") + .field( + "lp_ana_touch_neg_noise_disupdate_baseline_en", + &format_args!( + "{}", + self.lp_ana_touch_neg_noise_disupdate_baseline_en().bit() + ), + ) + .field( + "lp_ana_touch_hysteresis", + &format_args!("{}", self.lp_ana_touch_hysteresis().bits()), + ) + .field( + "lp_ana_touch_neg_noise_thres", + &format_args!("{}", self.lp_ana_touch_neg_noise_thres().bits()), + ) + .field( + "lp_ana_touch_noise_thres", + &format_args!("{}", self.lp_ana_touch_noise_thres().bits()), + ) + .field( + "lp_ana_touch_smooth_lvl", + &format_args!("{}", self.lp_ana_touch_smooth_lvl().bits()), + ) + .field( + "lp_ana_touch_jitter_step", + &format_args!("{}", self.lp_ana_touch_jitter_step().bits()), + ) + .field( + "lp_ana_touch_filter_mode", + &format_args!("{}", self.lp_ana_touch_filter_mode().bits()), + ) + .field( + "lp_ana_touch_filter_en", + &format_args!("{}", self.lp_ana_touch_filter_en().bit()), + ) + .field( + "lp_ana_touch_neg_noise_limit", + &format_args!("{}", self.lp_ana_touch_neg_noise_limit().bits()), + ) + .field( + "lp_ana_touch_approach_limit", + &format_args!("{}", self.lp_ana_touch_approach_limit().bits()), + ) + .field( + "lp_ana_touch_debounce_limit", + &format_args!("{}", self.lp_ana_touch_debounce_limit().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_neg_noise_disupdate_baseline_en( + &mut self, + ) -> LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_W { + LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_W::new(self, 0) + } + #[doc = "Bits 1:2 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_hysteresis( + &mut self, + ) -> LP_ANA_TOUCH_HYSTERESIS_W { + LP_ANA_TOUCH_HYSTERESIS_W::new(self, 1) + } + #[doc = "Bits 3:4 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_neg_noise_thres( + &mut self, + ) -> LP_ANA_TOUCH_NEG_NOISE_THRES_W { + LP_ANA_TOUCH_NEG_NOISE_THRES_W::new(self, 3) + } + #[doc = "Bits 5:6 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_noise_thres( + &mut self, + ) -> LP_ANA_TOUCH_NOISE_THRES_W { + LP_ANA_TOUCH_NOISE_THRES_W::new(self, 5) + } + #[doc = "Bits 7:8 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_smooth_lvl( + &mut self, + ) -> LP_ANA_TOUCH_SMOOTH_LVL_W { + LP_ANA_TOUCH_SMOOTH_LVL_W::new(self, 7) + } + #[doc = "Bits 9:12 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_jitter_step( + &mut self, + ) -> LP_ANA_TOUCH_JITTER_STEP_W { + LP_ANA_TOUCH_JITTER_STEP_W::new(self, 9) + } + #[doc = "Bits 13:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_filter_mode( + &mut self, + ) -> LP_ANA_TOUCH_FILTER_MODE_W { + LP_ANA_TOUCH_FILTER_MODE_W::new(self, 13) + } + #[doc = "Bit 16 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_filter_en( + &mut self, + ) -> LP_ANA_TOUCH_FILTER_EN_W { + LP_ANA_TOUCH_FILTER_EN_W::new(self, 16) + } + #[doc = "Bits 17:20 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_neg_noise_limit( + &mut self, + ) -> LP_ANA_TOUCH_NEG_NOISE_LIMIT_W { + LP_ANA_TOUCH_NEG_NOISE_LIMIT_W::new(self, 17) + } + #[doc = "Bits 21:28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_approach_limit( + &mut self, + ) -> LP_ANA_TOUCH_APPROACH_LIMIT_W { + LP_ANA_TOUCH_APPROACH_LIMIT_W::new(self, 21) + } + #[doc = "Bits 29:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_debounce_limit( + &mut self, + ) -> LP_ANA_TOUCH_DEBOUNCE_LIMIT_W { + LP_ANA_TOUCH_DEBOUNCE_LIMIT_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_filter1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_filter1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_FILTER1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_FILTER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_filter1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_FILTER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_filter1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_FILTER1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_FILTER1 to value 0x6a0a_0200"] +impl crate::Resettable for LP_ANA_TOUCH_FILTER1_SPEC { + const RESET_VALUE: Self::Ux = 0x6a0a_0200; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_filter2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_filter2.rs new file mode 100644 index 0000000000..1274a1f07a --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_filter2.rs @@ -0,0 +1,108 @@ +#[doc = "Register `LP_ANA_TOUCH_FILTER2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_FILTER2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_OUTEN` reader - need_des"] +pub type LP_ANA_TOUCH_OUTEN_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_OUTEN` writer - need_des"] +pub type LP_ANA_TOUCH_OUTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `LP_ANA_TOUCH_BYPASS_NOISE_THRES` reader - need_des"] +pub type LP_ANA_TOUCH_BYPASS_NOISE_THRES_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_BYPASS_NOISE_THRES` writer - need_des"] +pub type LP_ANA_TOUCH_BYPASS_NOISE_THRES_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES` reader - need_des"] +pub type LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES` writer - need_des"] +pub type LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 15:29 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_outen(&self) -> LP_ANA_TOUCH_OUTEN_R { + LP_ANA_TOUCH_OUTEN_R::new(((self.bits >> 15) & 0x7fff) as u16) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_bypass_noise_thres(&self) -> LP_ANA_TOUCH_BYPASS_NOISE_THRES_R { + LP_ANA_TOUCH_BYPASS_NOISE_THRES_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_bypass_neg_noise_thres(&self) -> LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_R { + LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_FILTER2") + .field( + "lp_ana_touch_outen", + &format_args!("{}", self.lp_ana_touch_outen().bits()), + ) + .field( + "lp_ana_touch_bypass_noise_thres", + &format_args!("{}", self.lp_ana_touch_bypass_noise_thres().bit()), + ) + .field( + "lp_ana_touch_bypass_neg_noise_thres", + &format_args!("{}", self.lp_ana_touch_bypass_neg_noise_thres().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 15:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_outen(&mut self) -> LP_ANA_TOUCH_OUTEN_W { + LP_ANA_TOUCH_OUTEN_W::new(self, 15) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_bypass_noise_thres( + &mut self, + ) -> LP_ANA_TOUCH_BYPASS_NOISE_THRES_W { + LP_ANA_TOUCH_BYPASS_NOISE_THRES_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_bypass_neg_noise_thres( + &mut self, + ) -> LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_W { + LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_filter2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_filter2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_FILTER2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_FILTER2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_filter2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_FILTER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_filter2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_FILTER2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_FILTER2 to value 0x1fff_8000"] +impl crate::Resettable for LP_ANA_TOUCH_FILTER2_SPEC { + const RESET_VALUE: Self::Ux = 0x1fff_8000; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_filter3.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_filter3.rs new file mode 100644 index 0000000000..5be4a867d6 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_filter3.rs @@ -0,0 +1,78 @@ +#[doc = "Register `LP_ANA_TOUCH_FILTER3` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_FILTER3` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_BASELINE_SW` reader - need_des"] +pub type LP_ANA_TOUCH_BASELINE_SW_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_BASELINE_SW` writer - need_des"] +pub type LP_ANA_TOUCH_BASELINE_SW_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `LP_ANA_TOUCH_UPDATE_BASELINE_SW` writer - need_des"] +pub type LP_ANA_TOUCH_UPDATE_BASELINE_SW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_baseline_sw(&self) -> LP_ANA_TOUCH_BASELINE_SW_R { + LP_ANA_TOUCH_BASELINE_SW_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_FILTER3") + .field( + "lp_ana_touch_baseline_sw", + &format_args!("{}", self.lp_ana_touch_baseline_sw().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_baseline_sw( + &mut self, + ) -> LP_ANA_TOUCH_BASELINE_SW_W { + LP_ANA_TOUCH_BASELINE_SW_W::new(self, 0) + } + #[doc = "Bit 16 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_update_baseline_sw( + &mut self, + ) -> LP_ANA_TOUCH_UPDATE_BASELINE_SW_W { + LP_ANA_TOUCH_UPDATE_BASELINE_SW_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_filter3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_filter3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_FILTER3_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_FILTER3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_filter3::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_FILTER3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_filter3::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_FILTER3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_FILTER3 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_FILTER3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_freq0_scan_para.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_freq0_scan_para.rs new file mode 100644 index 0000000000..6afd6745e9 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_freq0_scan_para.rs @@ -0,0 +1,152 @@ +#[doc = "Register `LP_ANA_TOUCH_FREQ0_SCAN_PARA` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_FREQ0_SCAN_PARA` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_FREQ0_DCAP_LPF` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ0_DCAP_LPF_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ0_DCAP_LPF` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ0_DCAP_LPF_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `LP_ANA_TOUCH_FREQ0_DRES_LPF` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ0_DRES_LPF_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ0_DRES_LPF` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ0_DRES_LPF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_ANA_TOUCH_FREQ0_DRV_LS` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ0_DRV_LS_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ0_DRV_LS` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ0_DRV_LS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LP_ANA_TOUCH_FREQ0_DRV_HS` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ0_DRV_HS_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ0_DRV_HS` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ0_DRV_HS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `LP_ANA_TOUCH_FREQ0_DBIAS` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ0_DBIAS_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ0_DBIAS` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ0_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:6 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq0_dcap_lpf(&self) -> LP_ANA_TOUCH_FREQ0_DCAP_LPF_R { + LP_ANA_TOUCH_FREQ0_DCAP_LPF_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:8 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq0_dres_lpf(&self) -> LP_ANA_TOUCH_FREQ0_DRES_LPF_R { + LP_ANA_TOUCH_FREQ0_DRES_LPF_R::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 9:12 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq0_drv_ls(&self) -> LP_ANA_TOUCH_FREQ0_DRV_LS_R { + LP_ANA_TOUCH_FREQ0_DRV_LS_R::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bits 13:17 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq0_drv_hs(&self) -> LP_ANA_TOUCH_FREQ0_DRV_HS_R { + LP_ANA_TOUCH_FREQ0_DRV_HS_R::new(((self.bits >> 13) & 0x1f) as u8) + } + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq0_dbias(&self) -> LP_ANA_TOUCH_FREQ0_DBIAS_R { + LP_ANA_TOUCH_FREQ0_DBIAS_R::new(((self.bits >> 18) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_FREQ0_SCAN_PARA") + .field( + "lp_ana_touch_freq0_dcap_lpf", + &format_args!("{}", self.lp_ana_touch_freq0_dcap_lpf().bits()), + ) + .field( + "lp_ana_touch_freq0_dres_lpf", + &format_args!("{}", self.lp_ana_touch_freq0_dres_lpf().bits()), + ) + .field( + "lp_ana_touch_freq0_drv_ls", + &format_args!("{}", self.lp_ana_touch_freq0_drv_ls().bits()), + ) + .field( + "lp_ana_touch_freq0_drv_hs", + &format_args!("{}", self.lp_ana_touch_freq0_drv_hs().bits()), + ) + .field( + "lp_ana_touch_freq0_dbias", + &format_args!("{}", self.lp_ana_touch_freq0_dbias().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq0_dcap_lpf( + &mut self, + ) -> LP_ANA_TOUCH_FREQ0_DCAP_LPF_W { + LP_ANA_TOUCH_FREQ0_DCAP_LPF_W::new(self, 0) + } + #[doc = "Bits 7:8 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq0_dres_lpf( + &mut self, + ) -> LP_ANA_TOUCH_FREQ0_DRES_LPF_W { + LP_ANA_TOUCH_FREQ0_DRES_LPF_W::new(self, 7) + } + #[doc = "Bits 9:12 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq0_drv_ls( + &mut self, + ) -> LP_ANA_TOUCH_FREQ0_DRV_LS_W { + LP_ANA_TOUCH_FREQ0_DRV_LS_W::new(self, 9) + } + #[doc = "Bits 13:17 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq0_drv_hs( + &mut self, + ) -> LP_ANA_TOUCH_FREQ0_DRV_HS_W { + LP_ANA_TOUCH_FREQ0_DRV_HS_W::new(self, 13) + } + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq0_dbias( + &mut self, + ) -> LP_ANA_TOUCH_FREQ0_DBIAS_W { + LP_ANA_TOUCH_FREQ0_DBIAS_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_freq0_scan_para::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_freq0_scan_para::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_FREQ0_SCAN_PARA_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_FREQ0_SCAN_PARA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_freq0_scan_para::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_FREQ0_SCAN_PARA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_freq0_scan_para::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_FREQ0_SCAN_PARA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_FREQ0_SCAN_PARA to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_FREQ0_SCAN_PARA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_freq1_scan_para.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_freq1_scan_para.rs new file mode 100644 index 0000000000..c0020547f1 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_freq1_scan_para.rs @@ -0,0 +1,152 @@ +#[doc = "Register `LP_ANA_TOUCH_FREQ1_SCAN_PARA` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_FREQ1_SCAN_PARA` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_FREQ1_DCAP_LPF` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ1_DCAP_LPF_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ1_DCAP_LPF` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ1_DCAP_LPF_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `LP_ANA_TOUCH_FREQ1_DRES_LPF` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ1_DRES_LPF_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ1_DRES_LPF` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ1_DRES_LPF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_ANA_TOUCH_FREQ1_DRV_LS` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ1_DRV_LS_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ1_DRV_LS` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ1_DRV_LS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LP_ANA_TOUCH_FREQ1_DRV_HS` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ1_DRV_HS_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ1_DRV_HS` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ1_DRV_HS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `LP_ANA_TOUCH_FREQ1_DBIAS` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ1_DBIAS_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ1_DBIAS` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ1_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:6 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq1_dcap_lpf(&self) -> LP_ANA_TOUCH_FREQ1_DCAP_LPF_R { + LP_ANA_TOUCH_FREQ1_DCAP_LPF_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:8 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq1_dres_lpf(&self) -> LP_ANA_TOUCH_FREQ1_DRES_LPF_R { + LP_ANA_TOUCH_FREQ1_DRES_LPF_R::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 9:12 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq1_drv_ls(&self) -> LP_ANA_TOUCH_FREQ1_DRV_LS_R { + LP_ANA_TOUCH_FREQ1_DRV_LS_R::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bits 13:17 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq1_drv_hs(&self) -> LP_ANA_TOUCH_FREQ1_DRV_HS_R { + LP_ANA_TOUCH_FREQ1_DRV_HS_R::new(((self.bits >> 13) & 0x1f) as u8) + } + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq1_dbias(&self) -> LP_ANA_TOUCH_FREQ1_DBIAS_R { + LP_ANA_TOUCH_FREQ1_DBIAS_R::new(((self.bits >> 18) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_FREQ1_SCAN_PARA") + .field( + "lp_ana_touch_freq1_dcap_lpf", + &format_args!("{}", self.lp_ana_touch_freq1_dcap_lpf().bits()), + ) + .field( + "lp_ana_touch_freq1_dres_lpf", + &format_args!("{}", self.lp_ana_touch_freq1_dres_lpf().bits()), + ) + .field( + "lp_ana_touch_freq1_drv_ls", + &format_args!("{}", self.lp_ana_touch_freq1_drv_ls().bits()), + ) + .field( + "lp_ana_touch_freq1_drv_hs", + &format_args!("{}", self.lp_ana_touch_freq1_drv_hs().bits()), + ) + .field( + "lp_ana_touch_freq1_dbias", + &format_args!("{}", self.lp_ana_touch_freq1_dbias().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq1_dcap_lpf( + &mut self, + ) -> LP_ANA_TOUCH_FREQ1_DCAP_LPF_W { + LP_ANA_TOUCH_FREQ1_DCAP_LPF_W::new(self, 0) + } + #[doc = "Bits 7:8 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq1_dres_lpf( + &mut self, + ) -> LP_ANA_TOUCH_FREQ1_DRES_LPF_W { + LP_ANA_TOUCH_FREQ1_DRES_LPF_W::new(self, 7) + } + #[doc = "Bits 9:12 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq1_drv_ls( + &mut self, + ) -> LP_ANA_TOUCH_FREQ1_DRV_LS_W { + LP_ANA_TOUCH_FREQ1_DRV_LS_W::new(self, 9) + } + #[doc = "Bits 13:17 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq1_drv_hs( + &mut self, + ) -> LP_ANA_TOUCH_FREQ1_DRV_HS_W { + LP_ANA_TOUCH_FREQ1_DRV_HS_W::new(self, 13) + } + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq1_dbias( + &mut self, + ) -> LP_ANA_TOUCH_FREQ1_DBIAS_W { + LP_ANA_TOUCH_FREQ1_DBIAS_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_freq1_scan_para::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_freq1_scan_para::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_FREQ1_SCAN_PARA_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_FREQ1_SCAN_PARA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_freq1_scan_para::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_FREQ1_SCAN_PARA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_freq1_scan_para::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_FREQ1_SCAN_PARA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_FREQ1_SCAN_PARA to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_FREQ1_SCAN_PARA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_freq2_scan_para.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_freq2_scan_para.rs new file mode 100644 index 0000000000..89f0b6e0d6 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_freq2_scan_para.rs @@ -0,0 +1,152 @@ +#[doc = "Register `LP_ANA_TOUCH_FREQ2_SCAN_PARA` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_FREQ2_SCAN_PARA` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_FREQ2_DCAP_LPF` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ2_DCAP_LPF_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ2_DCAP_LPF` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ2_DCAP_LPF_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `LP_ANA_TOUCH_FREQ2_DRES_LPF` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ2_DRES_LPF_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ2_DRES_LPF` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ2_DRES_LPF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_ANA_TOUCH_FREQ2_DRV_LS` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ2_DRV_LS_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ2_DRV_LS` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ2_DRV_LS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LP_ANA_TOUCH_FREQ2_DRV_HS` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ2_DRV_HS_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ2_DRV_HS` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ2_DRV_HS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `LP_ANA_TOUCH_FREQ2_DBIAS` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ2_DBIAS_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ2_DBIAS` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ2_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:6 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq2_dcap_lpf(&self) -> LP_ANA_TOUCH_FREQ2_DCAP_LPF_R { + LP_ANA_TOUCH_FREQ2_DCAP_LPF_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:8 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq2_dres_lpf(&self) -> LP_ANA_TOUCH_FREQ2_DRES_LPF_R { + LP_ANA_TOUCH_FREQ2_DRES_LPF_R::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 9:12 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq2_drv_ls(&self) -> LP_ANA_TOUCH_FREQ2_DRV_LS_R { + LP_ANA_TOUCH_FREQ2_DRV_LS_R::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bits 13:17 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq2_drv_hs(&self) -> LP_ANA_TOUCH_FREQ2_DRV_HS_R { + LP_ANA_TOUCH_FREQ2_DRV_HS_R::new(((self.bits >> 13) & 0x1f) as u8) + } + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq2_dbias(&self) -> LP_ANA_TOUCH_FREQ2_DBIAS_R { + LP_ANA_TOUCH_FREQ2_DBIAS_R::new(((self.bits >> 18) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_FREQ2_SCAN_PARA") + .field( + "lp_ana_touch_freq2_dcap_lpf", + &format_args!("{}", self.lp_ana_touch_freq2_dcap_lpf().bits()), + ) + .field( + "lp_ana_touch_freq2_dres_lpf", + &format_args!("{}", self.lp_ana_touch_freq2_dres_lpf().bits()), + ) + .field( + "lp_ana_touch_freq2_drv_ls", + &format_args!("{}", self.lp_ana_touch_freq2_drv_ls().bits()), + ) + .field( + "lp_ana_touch_freq2_drv_hs", + &format_args!("{}", self.lp_ana_touch_freq2_drv_hs().bits()), + ) + .field( + "lp_ana_touch_freq2_dbias", + &format_args!("{}", self.lp_ana_touch_freq2_dbias().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq2_dcap_lpf( + &mut self, + ) -> LP_ANA_TOUCH_FREQ2_DCAP_LPF_W { + LP_ANA_TOUCH_FREQ2_DCAP_LPF_W::new(self, 0) + } + #[doc = "Bits 7:8 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq2_dres_lpf( + &mut self, + ) -> LP_ANA_TOUCH_FREQ2_DRES_LPF_W { + LP_ANA_TOUCH_FREQ2_DRES_LPF_W::new(self, 7) + } + #[doc = "Bits 9:12 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq2_drv_ls( + &mut self, + ) -> LP_ANA_TOUCH_FREQ2_DRV_LS_W { + LP_ANA_TOUCH_FREQ2_DRV_LS_W::new(self, 9) + } + #[doc = "Bits 13:17 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq2_drv_hs( + &mut self, + ) -> LP_ANA_TOUCH_FREQ2_DRV_HS_W { + LP_ANA_TOUCH_FREQ2_DRV_HS_W::new(self, 13) + } + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq2_dbias( + &mut self, + ) -> LP_ANA_TOUCH_FREQ2_DBIAS_W { + LP_ANA_TOUCH_FREQ2_DBIAS_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_freq2_scan_para::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_freq2_scan_para::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_FREQ2_SCAN_PARA_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_FREQ2_SCAN_PARA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_freq2_scan_para::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_FREQ2_SCAN_PARA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_freq2_scan_para::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_FREQ2_SCAN_PARA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_FREQ2_SCAN_PARA to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_FREQ2_SCAN_PARA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_mux0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_mux0.rs new file mode 100644 index 0000000000..4a375a61eb --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_mux0.rs @@ -0,0 +1,201 @@ +#[doc = "Register `LP_ANA_TOUCH_MUX0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_MUX0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_DATA_SEL` reader - need_des"] +pub type LP_ANA_TOUCH_DATA_SEL_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_DATA_SEL` writer - need_des"] +pub type LP_ANA_TOUCH_DATA_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_ANA_TOUCH_FREQ_SEL` reader - need_des"] +pub type LP_ANA_TOUCH_FREQ_SEL_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_FREQ_SEL` writer - need_des"] +pub type LP_ANA_TOUCH_FREQ_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_ANA_TOUCH_BUFSEL` reader - need_des"] +pub type LP_ANA_TOUCH_BUFSEL_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_BUFSEL` writer - need_des"] +pub type LP_ANA_TOUCH_BUFSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `LP_ANA_TOUCH_DONE_EN` reader - need_des"] +pub type LP_ANA_TOUCH_DONE_EN_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_DONE_EN` writer - need_des"] +pub type LP_ANA_TOUCH_DONE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_DONE_FORCE` reader - need_des"] +pub type LP_ANA_TOUCH_DONE_FORCE_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_DONE_FORCE` writer - need_des"] +pub type LP_ANA_TOUCH_DONE_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_FSM_EN` reader - need_des"] +pub type LP_ANA_TOUCH_FSM_EN_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_FSM_EN` writer - need_des"] +pub type LP_ANA_TOUCH_FSM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_START_EN` reader - need_des"] +pub type LP_ANA_TOUCH_START_EN_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_START_EN` writer - need_des"] +pub type LP_ANA_TOUCH_START_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_START_FORCE` reader - need_des"] +pub type LP_ANA_TOUCH_START_FORCE_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_START_FORCE` writer - need_des"] +pub type LP_ANA_TOUCH_START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 8:9 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_data_sel(&self) -> LP_ANA_TOUCH_DATA_SEL_R { + LP_ANA_TOUCH_DATA_SEL_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_freq_sel(&self) -> LP_ANA_TOUCH_FREQ_SEL_R { + LP_ANA_TOUCH_FREQ_SEL_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:26 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_bufsel(&self) -> LP_ANA_TOUCH_BUFSEL_R { + LP_ANA_TOUCH_BUFSEL_R::new(((self.bits >> 12) & 0x7fff) as u16) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_done_en(&self) -> LP_ANA_TOUCH_DONE_EN_R { + LP_ANA_TOUCH_DONE_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_done_force(&self) -> LP_ANA_TOUCH_DONE_FORCE_R { + LP_ANA_TOUCH_DONE_FORCE_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_fsm_en(&self) -> LP_ANA_TOUCH_FSM_EN_R { + LP_ANA_TOUCH_FSM_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_start_en(&self) -> LP_ANA_TOUCH_START_EN_R { + LP_ANA_TOUCH_START_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_start_force(&self) -> LP_ANA_TOUCH_START_FORCE_R { + LP_ANA_TOUCH_START_FORCE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_MUX0") + .field( + "lp_ana_touch_data_sel", + &format_args!("{}", self.lp_ana_touch_data_sel().bits()), + ) + .field( + "lp_ana_touch_freq_sel", + &format_args!("{}", self.lp_ana_touch_freq_sel().bits()), + ) + .field( + "lp_ana_touch_bufsel", + &format_args!("{}", self.lp_ana_touch_bufsel().bits()), + ) + .field( + "lp_ana_touch_done_en", + &format_args!("{}", self.lp_ana_touch_done_en().bit()), + ) + .field( + "lp_ana_touch_done_force", + &format_args!("{}", self.lp_ana_touch_done_force().bit()), + ) + .field( + "lp_ana_touch_fsm_en", + &format_args!("{}", self.lp_ana_touch_fsm_en().bit()), + ) + .field( + "lp_ana_touch_start_en", + &format_args!("{}", self.lp_ana_touch_start_en().bit()), + ) + .field( + "lp_ana_touch_start_force", + &format_args!("{}", self.lp_ana_touch_start_force().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 8:9 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_data_sel(&mut self) -> LP_ANA_TOUCH_DATA_SEL_W { + LP_ANA_TOUCH_DATA_SEL_W::new(self, 8) + } + #[doc = "Bits 10:11 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_freq_sel(&mut self) -> LP_ANA_TOUCH_FREQ_SEL_W { + LP_ANA_TOUCH_FREQ_SEL_W::new(self, 10) + } + #[doc = "Bits 12:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_bufsel(&mut self) -> LP_ANA_TOUCH_BUFSEL_W { + LP_ANA_TOUCH_BUFSEL_W::new(self, 12) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_done_en(&mut self) -> LP_ANA_TOUCH_DONE_EN_W { + LP_ANA_TOUCH_DONE_EN_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_done_force(&mut self) -> LP_ANA_TOUCH_DONE_FORCE_W { + LP_ANA_TOUCH_DONE_FORCE_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_fsm_en(&mut self) -> LP_ANA_TOUCH_FSM_EN_W { + LP_ANA_TOUCH_FSM_EN_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_start_en(&mut self) -> LP_ANA_TOUCH_START_EN_W { + LP_ANA_TOUCH_START_EN_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_start_force( + &mut self, + ) -> LP_ANA_TOUCH_START_FORCE_W { + LP_ANA_TOUCH_START_FORCE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_mux0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_mux0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_MUX0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_MUX0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_mux0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_MUX0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_mux0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_MUX0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_MUX0 to value 0x2000_0000"] +impl crate::Resettable for LP_ANA_TOUCH_MUX0_SPEC { + const RESET_VALUE: Self::Ux = 0x2000_0000; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_mux1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_mux1.rs new file mode 100644 index 0000000000..e4b49773d8 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_mux1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `LP_ANA_TOUCH_MUX1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_MUX1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_START` reader - need_des"] +pub type LP_ANA_TOUCH_START_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_START` writer - need_des"] +pub type LP_ANA_TOUCH_START_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `LP_ANA_TOUCH_XPD` reader - need_des"] +pub type LP_ANA_TOUCH_XPD_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_XPD` writer - need_des"] +pub type LP_ANA_TOUCH_XPD_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bits 0:14 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_start(&self) -> LP_ANA_TOUCH_START_R { + LP_ANA_TOUCH_START_R::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bits 15:29 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_xpd(&self) -> LP_ANA_TOUCH_XPD_R { + LP_ANA_TOUCH_XPD_R::new(((self.bits >> 15) & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_MUX1") + .field( + "lp_ana_touch_start", + &format_args!("{}", self.lp_ana_touch_start().bits()), + ) + .field( + "lp_ana_touch_xpd", + &format_args!("{}", self.lp_ana_touch_xpd().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:14 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_start(&mut self) -> LP_ANA_TOUCH_START_W { + LP_ANA_TOUCH_START_W::new(self, 0) + } + #[doc = "Bits 15:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_xpd(&mut self) -> LP_ANA_TOUCH_XPD_W { + LP_ANA_TOUCH_XPD_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_mux1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_mux1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_MUX1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_MUX1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_mux1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_MUX1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_mux1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_MUX1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_MUX1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_MUX1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad0_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad0_th0.rs new file mode 100644 index 0000000000..61e85d0c8c --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad0_th0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD0_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD0_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD0_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD0_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD0_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD0_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad0_th0(&self) -> LP_ANA_TOUCH_PAD0_TH0_R { + LP_ANA_TOUCH_PAD0_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD0_TH0") + .field( + "lp_ana_touch_pad0_th0", + &format_args!("{}", self.lp_ana_touch_pad0_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad0_th0(&mut self) -> LP_ANA_TOUCH_PAD0_TH0_W { + LP_ANA_TOUCH_PAD0_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad0_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad0_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD0_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD0_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad0_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD0_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad0_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD0_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD0_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD0_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad0_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad0_th1.rs new file mode 100644 index 0000000000..932f52c9ef --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad0_th1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD0_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD0_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD0_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD0_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD0_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD0_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad0_th1(&self) -> LP_ANA_TOUCH_PAD0_TH1_R { + LP_ANA_TOUCH_PAD0_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD0_TH1") + .field( + "lp_ana_touch_pad0_th1", + &format_args!("{}", self.lp_ana_touch_pad0_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad0_th1(&mut self) -> LP_ANA_TOUCH_PAD0_TH1_W { + LP_ANA_TOUCH_PAD0_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad0_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad0_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD0_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD0_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad0_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD0_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad0_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD0_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD0_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD0_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad0_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad0_th2.rs new file mode 100644 index 0000000000..da080ebee8 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad0_th2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD0_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD0_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD0_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD0_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD0_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD0_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad0_th2(&self) -> LP_ANA_TOUCH_PAD0_TH2_R { + LP_ANA_TOUCH_PAD0_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD0_TH2") + .field( + "lp_ana_touch_pad0_th2", + &format_args!("{}", self.lp_ana_touch_pad0_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad0_th2(&mut self) -> LP_ANA_TOUCH_PAD0_TH2_W { + LP_ANA_TOUCH_PAD0_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad0_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad0_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD0_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD0_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad0_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD0_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad0_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD0_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD0_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD0_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad10_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad10_th0.rs new file mode 100644 index 0000000000..b5f9a9dbbb --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad10_th0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD10_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD10_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD10_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD10_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD10_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD10_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad10_th0(&self) -> LP_ANA_TOUCH_PAD10_TH0_R { + LP_ANA_TOUCH_PAD10_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD10_TH0") + .field( + "lp_ana_touch_pad10_th0", + &format_args!("{}", self.lp_ana_touch_pad10_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad10_th0( + &mut self, + ) -> LP_ANA_TOUCH_PAD10_TH0_W { + LP_ANA_TOUCH_PAD10_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad10_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad10_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD10_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD10_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad10_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD10_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad10_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD10_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD10_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD10_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad10_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad10_th1.rs new file mode 100644 index 0000000000..c251dd44c6 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad10_th1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD10_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD10_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD10_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD10_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD10_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD10_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad10_th1(&self) -> LP_ANA_TOUCH_PAD10_TH1_R { + LP_ANA_TOUCH_PAD10_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD10_TH1") + .field( + "lp_ana_touch_pad10_th1", + &format_args!("{}", self.lp_ana_touch_pad10_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad10_th1( + &mut self, + ) -> LP_ANA_TOUCH_PAD10_TH1_W { + LP_ANA_TOUCH_PAD10_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad10_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad10_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD10_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD10_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad10_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD10_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad10_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD10_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD10_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD10_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad10_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad10_th2.rs new file mode 100644 index 0000000000..b695c83911 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad10_th2.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD10_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD10_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD10_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD10_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD10_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD10_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad10_th2(&self) -> LP_ANA_TOUCH_PAD10_TH2_R { + LP_ANA_TOUCH_PAD10_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD10_TH2") + .field( + "lp_ana_touch_pad10_th2", + &format_args!("{}", self.lp_ana_touch_pad10_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad10_th2( + &mut self, + ) -> LP_ANA_TOUCH_PAD10_TH2_W { + LP_ANA_TOUCH_PAD10_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad10_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad10_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD10_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD10_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad10_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD10_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad10_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD10_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD10_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD10_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad11_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad11_th0.rs new file mode 100644 index 0000000000..4bd4879910 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad11_th0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD11_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD11_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD11_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD11_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD11_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD11_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad11_th0(&self) -> LP_ANA_TOUCH_PAD11_TH0_R { + LP_ANA_TOUCH_PAD11_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD11_TH0") + .field( + "lp_ana_touch_pad11_th0", + &format_args!("{}", self.lp_ana_touch_pad11_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad11_th0( + &mut self, + ) -> LP_ANA_TOUCH_PAD11_TH0_W { + LP_ANA_TOUCH_PAD11_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad11_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad11_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD11_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD11_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad11_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD11_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad11_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD11_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD11_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD11_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad11_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad11_th1.rs new file mode 100644 index 0000000000..6e6f1b293a --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad11_th1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD11_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD11_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD11_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD11_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD11_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD11_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad11_th1(&self) -> LP_ANA_TOUCH_PAD11_TH1_R { + LP_ANA_TOUCH_PAD11_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD11_TH1") + .field( + "lp_ana_touch_pad11_th1", + &format_args!("{}", self.lp_ana_touch_pad11_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad11_th1( + &mut self, + ) -> LP_ANA_TOUCH_PAD11_TH1_W { + LP_ANA_TOUCH_PAD11_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad11_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad11_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD11_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD11_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad11_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD11_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad11_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD11_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD11_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD11_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad11_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad11_th2.rs new file mode 100644 index 0000000000..5d5770674b --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad11_th2.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD11_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD11_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD11_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD11_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD11_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD11_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad11_th2(&self) -> LP_ANA_TOUCH_PAD11_TH2_R { + LP_ANA_TOUCH_PAD11_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD11_TH2") + .field( + "lp_ana_touch_pad11_th2", + &format_args!("{}", self.lp_ana_touch_pad11_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad11_th2( + &mut self, + ) -> LP_ANA_TOUCH_PAD11_TH2_W { + LP_ANA_TOUCH_PAD11_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad11_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad11_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD11_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD11_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad11_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD11_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad11_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD11_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD11_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD11_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad12_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad12_th0.rs new file mode 100644 index 0000000000..a63122eacf --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad12_th0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD12_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD12_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD12_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD12_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD12_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD12_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad12_th0(&self) -> LP_ANA_TOUCH_PAD12_TH0_R { + LP_ANA_TOUCH_PAD12_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD12_TH0") + .field( + "lp_ana_touch_pad12_th0", + &format_args!("{}", self.lp_ana_touch_pad12_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad12_th0( + &mut self, + ) -> LP_ANA_TOUCH_PAD12_TH0_W { + LP_ANA_TOUCH_PAD12_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad12_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad12_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD12_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD12_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad12_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD12_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad12_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD12_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD12_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD12_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad12_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad12_th1.rs new file mode 100644 index 0000000000..dd234efb10 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad12_th1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD12_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD12_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD12_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD12_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD12_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD12_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad12_th1(&self) -> LP_ANA_TOUCH_PAD12_TH1_R { + LP_ANA_TOUCH_PAD12_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD12_TH1") + .field( + "lp_ana_touch_pad12_th1", + &format_args!("{}", self.lp_ana_touch_pad12_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad12_th1( + &mut self, + ) -> LP_ANA_TOUCH_PAD12_TH1_W { + LP_ANA_TOUCH_PAD12_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad12_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad12_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD12_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD12_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad12_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD12_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad12_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD12_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD12_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD12_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad12_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad12_th2.rs new file mode 100644 index 0000000000..35eaf96c55 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad12_th2.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD12_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD12_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD12_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD12_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD12_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD12_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad12_th2(&self) -> LP_ANA_TOUCH_PAD12_TH2_R { + LP_ANA_TOUCH_PAD12_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD12_TH2") + .field( + "lp_ana_touch_pad12_th2", + &format_args!("{}", self.lp_ana_touch_pad12_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad12_th2( + &mut self, + ) -> LP_ANA_TOUCH_PAD12_TH2_W { + LP_ANA_TOUCH_PAD12_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad12_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad12_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD12_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD12_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad12_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD12_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad12_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD12_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD12_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD12_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad13_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad13_th0.rs new file mode 100644 index 0000000000..7836f35aab --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad13_th0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD13_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD13_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD13_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD13_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD13_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD13_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad13_th0(&self) -> LP_ANA_TOUCH_PAD13_TH0_R { + LP_ANA_TOUCH_PAD13_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD13_TH0") + .field( + "lp_ana_touch_pad13_th0", + &format_args!("{}", self.lp_ana_touch_pad13_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad13_th0( + &mut self, + ) -> LP_ANA_TOUCH_PAD13_TH0_W { + LP_ANA_TOUCH_PAD13_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad13_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad13_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD13_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD13_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad13_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD13_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad13_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD13_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD13_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD13_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad13_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad13_th1.rs new file mode 100644 index 0000000000..0e250a6526 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad13_th1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD13_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD13_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD13_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD13_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD13_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD13_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad13_th1(&self) -> LP_ANA_TOUCH_PAD13_TH1_R { + LP_ANA_TOUCH_PAD13_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD13_TH1") + .field( + "lp_ana_touch_pad13_th1", + &format_args!("{}", self.lp_ana_touch_pad13_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad13_th1( + &mut self, + ) -> LP_ANA_TOUCH_PAD13_TH1_W { + LP_ANA_TOUCH_PAD13_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad13_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad13_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD13_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD13_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad13_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD13_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad13_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD13_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD13_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD13_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad13_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad13_th2.rs new file mode 100644 index 0000000000..be3377c08c --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad13_th2.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD13_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD13_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD13_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD13_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD13_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD13_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad13_th2(&self) -> LP_ANA_TOUCH_PAD13_TH2_R { + LP_ANA_TOUCH_PAD13_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD13_TH2") + .field( + "lp_ana_touch_pad13_th2", + &format_args!("{}", self.lp_ana_touch_pad13_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad13_th2( + &mut self, + ) -> LP_ANA_TOUCH_PAD13_TH2_W { + LP_ANA_TOUCH_PAD13_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad13_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad13_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD13_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD13_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad13_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD13_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad13_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD13_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD13_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD13_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad14_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad14_th0.rs new file mode 100644 index 0000000000..841ba2a964 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad14_th0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD14_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD14_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD14_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD14_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD14_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD14_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad14_th0(&self) -> LP_ANA_TOUCH_PAD14_TH0_R { + LP_ANA_TOUCH_PAD14_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD14_TH0") + .field( + "lp_ana_touch_pad14_th0", + &format_args!("{}", self.lp_ana_touch_pad14_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad14_th0( + &mut self, + ) -> LP_ANA_TOUCH_PAD14_TH0_W { + LP_ANA_TOUCH_PAD14_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad14_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad14_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD14_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD14_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad14_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD14_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad14_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD14_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD14_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD14_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad14_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad14_th1.rs new file mode 100644 index 0000000000..2be89b7deb --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad14_th1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD14_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD14_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD14_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD14_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD14_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD14_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad14_th1(&self) -> LP_ANA_TOUCH_PAD14_TH1_R { + LP_ANA_TOUCH_PAD14_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD14_TH1") + .field( + "lp_ana_touch_pad14_th1", + &format_args!("{}", self.lp_ana_touch_pad14_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad14_th1( + &mut self, + ) -> LP_ANA_TOUCH_PAD14_TH1_W { + LP_ANA_TOUCH_PAD14_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad14_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad14_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD14_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD14_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad14_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD14_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad14_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD14_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD14_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD14_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad14_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad14_th2.rs new file mode 100644 index 0000000000..19245f17f4 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad14_th2.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD14_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD14_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD14_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD14_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD14_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD14_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad14_th2(&self) -> LP_ANA_TOUCH_PAD14_TH2_R { + LP_ANA_TOUCH_PAD14_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD14_TH2") + .field( + "lp_ana_touch_pad14_th2", + &format_args!("{}", self.lp_ana_touch_pad14_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad14_th2( + &mut self, + ) -> LP_ANA_TOUCH_PAD14_TH2_W { + LP_ANA_TOUCH_PAD14_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad14_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad14_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD14_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD14_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad14_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD14_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad14_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD14_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD14_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD14_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad1_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad1_th0.rs new file mode 100644 index 0000000000..a698388cec --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad1_th0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD1_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD1_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD1_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD1_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD1_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD1_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad1_th0(&self) -> LP_ANA_TOUCH_PAD1_TH0_R { + LP_ANA_TOUCH_PAD1_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD1_TH0") + .field( + "lp_ana_touch_pad1_th0", + &format_args!("{}", self.lp_ana_touch_pad1_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad1_th0(&mut self) -> LP_ANA_TOUCH_PAD1_TH0_W { + LP_ANA_TOUCH_PAD1_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad1_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad1_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD1_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD1_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad1_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD1_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad1_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD1_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD1_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD1_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad1_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad1_th1.rs new file mode 100644 index 0000000000..3d28af0d9b --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad1_th1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD1_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD1_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD1_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD1_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD1_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD1_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad1_th1(&self) -> LP_ANA_TOUCH_PAD1_TH1_R { + LP_ANA_TOUCH_PAD1_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD1_TH1") + .field( + "lp_ana_touch_pad1_th1", + &format_args!("{}", self.lp_ana_touch_pad1_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad1_th1(&mut self) -> LP_ANA_TOUCH_PAD1_TH1_W { + LP_ANA_TOUCH_PAD1_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad1_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad1_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD1_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD1_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad1_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD1_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad1_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD1_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD1_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD1_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad1_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad1_th2.rs new file mode 100644 index 0000000000..35a90ca983 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad1_th2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD1_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD1_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD1_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD1_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD1_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD1_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad1_th2(&self) -> LP_ANA_TOUCH_PAD1_TH2_R { + LP_ANA_TOUCH_PAD1_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD1_TH2") + .field( + "lp_ana_touch_pad1_th2", + &format_args!("{}", self.lp_ana_touch_pad1_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad1_th2(&mut self) -> LP_ANA_TOUCH_PAD1_TH2_W { + LP_ANA_TOUCH_PAD1_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad1_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad1_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD1_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD1_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad1_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD1_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad1_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD1_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD1_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD1_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad2_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad2_th0.rs new file mode 100644 index 0000000000..95b224c7b6 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad2_th0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD2_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD2_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD2_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD2_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD2_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD2_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad2_th0(&self) -> LP_ANA_TOUCH_PAD2_TH0_R { + LP_ANA_TOUCH_PAD2_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD2_TH0") + .field( + "lp_ana_touch_pad2_th0", + &format_args!("{}", self.lp_ana_touch_pad2_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad2_th0(&mut self) -> LP_ANA_TOUCH_PAD2_TH0_W { + LP_ANA_TOUCH_PAD2_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad2_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad2_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD2_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD2_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad2_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD2_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad2_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD2_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD2_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD2_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad2_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad2_th1.rs new file mode 100644 index 0000000000..f8a493b7b4 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad2_th1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD2_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD2_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD2_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD2_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD2_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD2_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad2_th1(&self) -> LP_ANA_TOUCH_PAD2_TH1_R { + LP_ANA_TOUCH_PAD2_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD2_TH1") + .field( + "lp_ana_touch_pad2_th1", + &format_args!("{}", self.lp_ana_touch_pad2_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad2_th1(&mut self) -> LP_ANA_TOUCH_PAD2_TH1_W { + LP_ANA_TOUCH_PAD2_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad2_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad2_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD2_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD2_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad2_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD2_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad2_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD2_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD2_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD2_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad2_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad2_th2.rs new file mode 100644 index 0000000000..cbc352a69d --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad2_th2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD2_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD2_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD2_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD2_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD2_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD2_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad2_th2(&self) -> LP_ANA_TOUCH_PAD2_TH2_R { + LP_ANA_TOUCH_PAD2_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD2_TH2") + .field( + "lp_ana_touch_pad2_th2", + &format_args!("{}", self.lp_ana_touch_pad2_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad2_th2(&mut self) -> LP_ANA_TOUCH_PAD2_TH2_W { + LP_ANA_TOUCH_PAD2_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad2_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad2_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD2_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD2_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad2_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD2_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad2_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD2_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD2_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD2_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad3_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad3_th0.rs new file mode 100644 index 0000000000..2e768aa7de --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad3_th0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD3_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD3_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD3_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD3_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD3_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD3_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad3_th0(&self) -> LP_ANA_TOUCH_PAD3_TH0_R { + LP_ANA_TOUCH_PAD3_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD3_TH0") + .field( + "lp_ana_touch_pad3_th0", + &format_args!("{}", self.lp_ana_touch_pad3_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad3_th0(&mut self) -> LP_ANA_TOUCH_PAD3_TH0_W { + LP_ANA_TOUCH_PAD3_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad3_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad3_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD3_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD3_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad3_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD3_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad3_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD3_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD3_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD3_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad3_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad3_th1.rs new file mode 100644 index 0000000000..0fa7ad82ae --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad3_th1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD3_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD3_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD3_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD3_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD3_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD3_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad3_th1(&self) -> LP_ANA_TOUCH_PAD3_TH1_R { + LP_ANA_TOUCH_PAD3_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD3_TH1") + .field( + "lp_ana_touch_pad3_th1", + &format_args!("{}", self.lp_ana_touch_pad3_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad3_th1(&mut self) -> LP_ANA_TOUCH_PAD3_TH1_W { + LP_ANA_TOUCH_PAD3_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad3_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad3_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD3_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD3_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad3_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD3_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad3_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD3_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD3_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD3_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad3_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad3_th2.rs new file mode 100644 index 0000000000..e4290ac9d9 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad3_th2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD3_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD3_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD3_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD3_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD3_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD3_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad3_th2(&self) -> LP_ANA_TOUCH_PAD3_TH2_R { + LP_ANA_TOUCH_PAD3_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD3_TH2") + .field( + "lp_ana_touch_pad3_th2", + &format_args!("{}", self.lp_ana_touch_pad3_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad3_th2(&mut self) -> LP_ANA_TOUCH_PAD3_TH2_W { + LP_ANA_TOUCH_PAD3_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad3_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad3_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD3_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD3_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad3_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD3_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad3_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD3_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD3_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD3_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad4_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad4_th0.rs new file mode 100644 index 0000000000..5b80fe3b00 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad4_th0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD4_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD4_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD4_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD4_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD4_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD4_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad4_th0(&self) -> LP_ANA_TOUCH_PAD4_TH0_R { + LP_ANA_TOUCH_PAD4_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD4_TH0") + .field( + "lp_ana_touch_pad4_th0", + &format_args!("{}", self.lp_ana_touch_pad4_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad4_th0(&mut self) -> LP_ANA_TOUCH_PAD4_TH0_W { + LP_ANA_TOUCH_PAD4_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad4_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad4_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD4_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD4_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad4_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD4_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad4_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD4_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD4_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD4_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad4_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad4_th1.rs new file mode 100644 index 0000000000..0472b51f3c --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad4_th1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD4_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD4_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD4_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD4_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD4_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD4_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad4_th1(&self) -> LP_ANA_TOUCH_PAD4_TH1_R { + LP_ANA_TOUCH_PAD4_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD4_TH1") + .field( + "lp_ana_touch_pad4_th1", + &format_args!("{}", self.lp_ana_touch_pad4_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad4_th1(&mut self) -> LP_ANA_TOUCH_PAD4_TH1_W { + LP_ANA_TOUCH_PAD4_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad4_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad4_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD4_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD4_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad4_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD4_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad4_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD4_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD4_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD4_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad4_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad4_th2.rs new file mode 100644 index 0000000000..64a0b4a020 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad4_th2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD4_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD4_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD4_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD4_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD4_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD4_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad4_th2(&self) -> LP_ANA_TOUCH_PAD4_TH2_R { + LP_ANA_TOUCH_PAD4_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD4_TH2") + .field( + "lp_ana_touch_pad4_th2", + &format_args!("{}", self.lp_ana_touch_pad4_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad4_th2(&mut self) -> LP_ANA_TOUCH_PAD4_TH2_W { + LP_ANA_TOUCH_PAD4_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad4_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad4_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD4_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD4_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad4_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD4_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad4_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD4_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD4_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD4_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad5_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad5_th0.rs new file mode 100644 index 0000000000..20b1baef41 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad5_th0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD5_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD5_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD5_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD5_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD5_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD5_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad5_th0(&self) -> LP_ANA_TOUCH_PAD5_TH0_R { + LP_ANA_TOUCH_PAD5_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD5_TH0") + .field( + "lp_ana_touch_pad5_th0", + &format_args!("{}", self.lp_ana_touch_pad5_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad5_th0(&mut self) -> LP_ANA_TOUCH_PAD5_TH0_W { + LP_ANA_TOUCH_PAD5_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad5_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad5_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD5_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD5_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad5_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD5_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad5_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD5_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD5_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD5_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad5_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad5_th1.rs new file mode 100644 index 0000000000..41b5eef496 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad5_th1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD5_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD5_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD5_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD5_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD5_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD5_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad5_th1(&self) -> LP_ANA_TOUCH_PAD5_TH1_R { + LP_ANA_TOUCH_PAD5_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD5_TH1") + .field( + "lp_ana_touch_pad5_th1", + &format_args!("{}", self.lp_ana_touch_pad5_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad5_th1(&mut self) -> LP_ANA_TOUCH_PAD5_TH1_W { + LP_ANA_TOUCH_PAD5_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad5_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad5_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD5_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD5_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad5_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD5_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad5_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD5_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD5_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD5_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad5_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad5_th2.rs new file mode 100644 index 0000000000..0bf6a7659d --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad5_th2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD5_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD5_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD5_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD5_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD5_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD5_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad5_th2(&self) -> LP_ANA_TOUCH_PAD5_TH2_R { + LP_ANA_TOUCH_PAD5_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD5_TH2") + .field( + "lp_ana_touch_pad5_th2", + &format_args!("{}", self.lp_ana_touch_pad5_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad5_th2(&mut self) -> LP_ANA_TOUCH_PAD5_TH2_W { + LP_ANA_TOUCH_PAD5_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad5_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad5_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD5_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD5_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad5_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD5_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad5_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD5_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD5_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD5_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad6_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad6_th0.rs new file mode 100644 index 0000000000..dea08288be --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad6_th0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD6_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD6_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD6_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD6_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD6_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD6_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad6_th0(&self) -> LP_ANA_TOUCH_PAD6_TH0_R { + LP_ANA_TOUCH_PAD6_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD6_TH0") + .field( + "lp_ana_touch_pad6_th0", + &format_args!("{}", self.lp_ana_touch_pad6_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad6_th0(&mut self) -> LP_ANA_TOUCH_PAD6_TH0_W { + LP_ANA_TOUCH_PAD6_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad6_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad6_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD6_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD6_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad6_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD6_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad6_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD6_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD6_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD6_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad6_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad6_th1.rs new file mode 100644 index 0000000000..ce207f516a --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad6_th1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD6_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD6_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD6_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD6_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD6_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD6_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad6_th1(&self) -> LP_ANA_TOUCH_PAD6_TH1_R { + LP_ANA_TOUCH_PAD6_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD6_TH1") + .field( + "lp_ana_touch_pad6_th1", + &format_args!("{}", self.lp_ana_touch_pad6_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad6_th1(&mut self) -> LP_ANA_TOUCH_PAD6_TH1_W { + LP_ANA_TOUCH_PAD6_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad6_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad6_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD6_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD6_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad6_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD6_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad6_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD6_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD6_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD6_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad6_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad6_th2.rs new file mode 100644 index 0000000000..5d9f206821 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad6_th2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD6_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD6_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD6_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD6_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD6_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD6_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad6_th2(&self) -> LP_ANA_TOUCH_PAD6_TH2_R { + LP_ANA_TOUCH_PAD6_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD6_TH2") + .field( + "lp_ana_touch_pad6_th2", + &format_args!("{}", self.lp_ana_touch_pad6_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad6_th2(&mut self) -> LP_ANA_TOUCH_PAD6_TH2_W { + LP_ANA_TOUCH_PAD6_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad6_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad6_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD6_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD6_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad6_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD6_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad6_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD6_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD6_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD6_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad7_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad7_th0.rs new file mode 100644 index 0000000000..db1832d6ee --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad7_th0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD7_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD7_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD7_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD7_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD7_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD7_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad7_th0(&self) -> LP_ANA_TOUCH_PAD7_TH0_R { + LP_ANA_TOUCH_PAD7_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD7_TH0") + .field( + "lp_ana_touch_pad7_th0", + &format_args!("{}", self.lp_ana_touch_pad7_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad7_th0(&mut self) -> LP_ANA_TOUCH_PAD7_TH0_W { + LP_ANA_TOUCH_PAD7_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad7_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad7_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD7_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD7_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad7_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD7_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad7_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD7_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD7_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD7_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad7_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad7_th1.rs new file mode 100644 index 0000000000..0dac3aca2d --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad7_th1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD7_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD7_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD7_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD7_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD7_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD7_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad7_th1(&self) -> LP_ANA_TOUCH_PAD7_TH1_R { + LP_ANA_TOUCH_PAD7_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD7_TH1") + .field( + "lp_ana_touch_pad7_th1", + &format_args!("{}", self.lp_ana_touch_pad7_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad7_th1(&mut self) -> LP_ANA_TOUCH_PAD7_TH1_W { + LP_ANA_TOUCH_PAD7_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad7_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad7_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD7_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD7_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad7_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD7_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad7_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD7_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD7_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD7_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad7_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad7_th2.rs new file mode 100644 index 0000000000..b4def51852 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad7_th2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD7_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD7_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD7_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD7_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD7_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD7_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad7_th2(&self) -> LP_ANA_TOUCH_PAD7_TH2_R { + LP_ANA_TOUCH_PAD7_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD7_TH2") + .field( + "lp_ana_touch_pad7_th2", + &format_args!("{}", self.lp_ana_touch_pad7_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad7_th2(&mut self) -> LP_ANA_TOUCH_PAD7_TH2_W { + LP_ANA_TOUCH_PAD7_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad7_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad7_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD7_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD7_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad7_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD7_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad7_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD7_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD7_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD7_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad8_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad8_th0.rs new file mode 100644 index 0000000000..1300e33e8e --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad8_th0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD8_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD8_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD8_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD8_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD8_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD8_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad8_th0(&self) -> LP_ANA_TOUCH_PAD8_TH0_R { + LP_ANA_TOUCH_PAD8_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD8_TH0") + .field( + "lp_ana_touch_pad8_th0", + &format_args!("{}", self.lp_ana_touch_pad8_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad8_th0(&mut self) -> LP_ANA_TOUCH_PAD8_TH0_W { + LP_ANA_TOUCH_PAD8_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad8_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad8_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD8_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD8_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad8_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD8_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad8_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD8_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD8_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD8_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad8_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad8_th1.rs new file mode 100644 index 0000000000..019554f25a --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad8_th1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD8_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD8_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD8_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD8_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD8_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD8_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad8_th1(&self) -> LP_ANA_TOUCH_PAD8_TH1_R { + LP_ANA_TOUCH_PAD8_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD8_TH1") + .field( + "lp_ana_touch_pad8_th1", + &format_args!("{}", self.lp_ana_touch_pad8_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad8_th1(&mut self) -> LP_ANA_TOUCH_PAD8_TH1_W { + LP_ANA_TOUCH_PAD8_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad8_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad8_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD8_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD8_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad8_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD8_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad8_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD8_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD8_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD8_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad8_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad8_th2.rs new file mode 100644 index 0000000000..73f15fb7a5 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad8_th2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD8_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD8_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD8_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD8_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD8_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD8_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad8_th2(&self) -> LP_ANA_TOUCH_PAD8_TH2_R { + LP_ANA_TOUCH_PAD8_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD8_TH2") + .field( + "lp_ana_touch_pad8_th2", + &format_args!("{}", self.lp_ana_touch_pad8_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad8_th2(&mut self) -> LP_ANA_TOUCH_PAD8_TH2_W { + LP_ANA_TOUCH_PAD8_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad8_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad8_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD8_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD8_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad8_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD8_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad8_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD8_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD8_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD8_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad9_th0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad9_th0.rs new file mode 100644 index 0000000000..9b06e7212e --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad9_th0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD9_TH0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD9_TH0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD9_TH0` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD9_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD9_TH0` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD9_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad9_th0(&self) -> LP_ANA_TOUCH_PAD9_TH0_R { + LP_ANA_TOUCH_PAD9_TH0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD9_TH0") + .field( + "lp_ana_touch_pad9_th0", + &format_args!("{}", self.lp_ana_touch_pad9_th0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad9_th0(&mut self) -> LP_ANA_TOUCH_PAD9_TH0_W { + LP_ANA_TOUCH_PAD9_TH0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad9_th0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad9_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD9_TH0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD9_TH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad9_th0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD9_TH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad9_th0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD9_TH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD9_TH0 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD9_TH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad9_th1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad9_th1.rs new file mode 100644 index 0000000000..ee241a4c47 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad9_th1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD9_TH1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD9_TH1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD9_TH1` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD9_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD9_TH1` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD9_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad9_th1(&self) -> LP_ANA_TOUCH_PAD9_TH1_R { + LP_ANA_TOUCH_PAD9_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD9_TH1") + .field( + "lp_ana_touch_pad9_th1", + &format_args!("{}", self.lp_ana_touch_pad9_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad9_th1(&mut self) -> LP_ANA_TOUCH_PAD9_TH1_W { + LP_ANA_TOUCH_PAD9_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad9_th1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad9_th1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD9_TH1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD9_TH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad9_th1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD9_TH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad9_th1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD9_TH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD9_TH1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD9_TH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_pad9_th2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad9_th2.rs new file mode 100644 index 0000000000..82d86f1dac --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_pad9_th2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ANA_TOUCH_PAD9_TH2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_PAD9_TH2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_PAD9_TH2` reader - Reserved"] +pub type LP_ANA_TOUCH_PAD9_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_PAD9_TH2` writer - Reserved"] +pub type LP_ANA_TOUCH_PAD9_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + pub fn lp_ana_touch_pad9_th2(&self) -> LP_ANA_TOUCH_PAD9_TH2_R { + LP_ANA_TOUCH_PAD9_TH2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_PAD9_TH2") + .field( + "lp_ana_touch_pad9_th2", + &format_args!("{}", self.lp_ana_touch_pad9_th2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - Reserved"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_pad9_th2(&mut self) -> LP_ANA_TOUCH_PAD9_TH2_W { + LP_ANA_TOUCH_PAD9_TH2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_pad9_th2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_pad9_th2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_PAD9_TH2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_PAD9_TH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_pad9_th2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_PAD9_TH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_pad9_th2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_PAD9_TH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_PAD9_TH2 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_PAD9_TH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_scan_ctrl1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_scan_ctrl1.rs new file mode 100644 index 0000000000..aaefbefbb6 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_scan_ctrl1.rs @@ -0,0 +1,131 @@ +#[doc = "Register `LP_ANA_TOUCH_SCAN_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_SCAN_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_SHIELD_PAD_EN` reader - need_des"] +pub type LP_ANA_TOUCH_SHIELD_PAD_EN_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_SHIELD_PAD_EN` writer - need_des"] +pub type LP_ANA_TOUCH_SHIELD_PAD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_INACTIVE_CONNECTION` reader - need_des"] +pub type LP_ANA_TOUCH_INACTIVE_CONNECTION_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_INACTIVE_CONNECTION` writer - need_des"] +pub type LP_ANA_TOUCH_INACTIVE_CONNECTION_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_SCAN_PAD_MAP` reader - need_des"] +pub type LP_ANA_TOUCH_SCAN_PAD_MAP_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_SCAN_PAD_MAP` writer - need_des"] +pub type LP_ANA_TOUCH_SCAN_PAD_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `LP_ANA_TOUCH_XPD_WAIT` reader - need_des"] +pub type LP_ANA_TOUCH_XPD_WAIT_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_XPD_WAIT` writer - need_des"] +pub type LP_ANA_TOUCH_XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_shield_pad_en(&self) -> LP_ANA_TOUCH_SHIELD_PAD_EN_R { + LP_ANA_TOUCH_SHIELD_PAD_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_inactive_connection(&self) -> LP_ANA_TOUCH_INACTIVE_CONNECTION_R { + LP_ANA_TOUCH_INACTIVE_CONNECTION_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:16 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_scan_pad_map(&self) -> LP_ANA_TOUCH_SCAN_PAD_MAP_R { + LP_ANA_TOUCH_SCAN_PAD_MAP_R::new(((self.bits >> 2) & 0x7fff) as u16) + } + #[doc = "Bits 17:31 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_xpd_wait(&self) -> LP_ANA_TOUCH_XPD_WAIT_R { + LP_ANA_TOUCH_XPD_WAIT_R::new(((self.bits >> 17) & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_SCAN_CTRL1") + .field( + "lp_ana_touch_shield_pad_en", + &format_args!("{}", self.lp_ana_touch_shield_pad_en().bit()), + ) + .field( + "lp_ana_touch_inactive_connection", + &format_args!("{}", self.lp_ana_touch_inactive_connection().bit()), + ) + .field( + "lp_ana_touch_scan_pad_map", + &format_args!("{}", self.lp_ana_touch_scan_pad_map().bits()), + ) + .field( + "lp_ana_touch_xpd_wait", + &format_args!("{}", self.lp_ana_touch_xpd_wait().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_shield_pad_en( + &mut self, + ) -> LP_ANA_TOUCH_SHIELD_PAD_EN_W { + LP_ANA_TOUCH_SHIELD_PAD_EN_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_inactive_connection( + &mut self, + ) -> LP_ANA_TOUCH_INACTIVE_CONNECTION_W { + LP_ANA_TOUCH_INACTIVE_CONNECTION_W::new(self, 1) + } + #[doc = "Bits 2:16 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_scan_pad_map( + &mut self, + ) -> LP_ANA_TOUCH_SCAN_PAD_MAP_W { + LP_ANA_TOUCH_SCAN_PAD_MAP_W::new(self, 2) + } + #[doc = "Bits 17:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_xpd_wait( + &mut self, + ) -> LP_ANA_TOUCH_XPD_WAIT_W { + LP_ANA_TOUCH_XPD_WAIT_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_scan_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_scan_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_SCAN_CTRL1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_SCAN_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_scan_ctrl1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_SCAN_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_scan_ctrl1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_SCAN_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_SCAN_CTRL1 to value 0x0008_0000"] +impl crate::Resettable for LP_ANA_TOUCH_SCAN_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0x0008_0000; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_scan_ctrl2.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_scan_ctrl2.rs new file mode 100644 index 0000000000..64dafa9b20 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_scan_ctrl2.rs @@ -0,0 +1,150 @@ +#[doc = "Register `LP_ANA_TOUCH_SCAN_CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_SCAN_CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_TIMEOUT_NUM` reader - need_des"] +pub type LP_ANA_TOUCH_TIMEOUT_NUM_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_TIMEOUT_NUM` writer - need_des"] +pub type LP_ANA_TOUCH_TIMEOUT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `LP_ANA_TOUCH_TIMEOUT_EN` reader - need_des"] +pub type LP_ANA_TOUCH_TIMEOUT_EN_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_TIMEOUT_EN` writer - need_des"] +pub type LP_ANA_TOUCH_TIMEOUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_OUT_RING` reader - need_des"] +pub type LP_ANA_TOUCH_OUT_RING_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_OUT_RING` writer - need_des"] +pub type LP_ANA_TOUCH_OUT_RING_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LP_ANA_FREQ_SCAN_EN` reader - need_des"] +pub type LP_ANA_FREQ_SCAN_EN_R = crate::BitReader; +#[doc = "Field `LP_ANA_FREQ_SCAN_EN` writer - need_des"] +pub type LP_ANA_FREQ_SCAN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_FREQ_SCAN_CNT_LIMIT` reader - need_des"] +pub type LP_ANA_FREQ_SCAN_CNT_LIMIT_R = crate::FieldReader; +#[doc = "Field `LP_ANA_FREQ_SCAN_CNT_LIMIT` writer - need_des"] +pub type LP_ANA_FREQ_SCAN_CNT_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 6:21 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_timeout_num(&self) -> LP_ANA_TOUCH_TIMEOUT_NUM_R { + LP_ANA_TOUCH_TIMEOUT_NUM_R::new(((self.bits >> 6) & 0xffff) as u16) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_timeout_en(&self) -> LP_ANA_TOUCH_TIMEOUT_EN_R { + LP_ANA_TOUCH_TIMEOUT_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_out_ring(&self) -> LP_ANA_TOUCH_OUT_RING_R { + LP_ANA_TOUCH_OUT_RING_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_ana_freq_scan_en(&self) -> LP_ANA_FREQ_SCAN_EN_R { + LP_ANA_FREQ_SCAN_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:29 - need_des"] + #[inline(always)] + pub fn lp_ana_freq_scan_cnt_limit(&self) -> LP_ANA_FREQ_SCAN_CNT_LIMIT_R { + LP_ANA_FREQ_SCAN_CNT_LIMIT_R::new(((self.bits >> 28) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_SCAN_CTRL2") + .field( + "lp_ana_touch_timeout_num", + &format_args!("{}", self.lp_ana_touch_timeout_num().bits()), + ) + .field( + "lp_ana_touch_timeout_en", + &format_args!("{}", self.lp_ana_touch_timeout_en().bit()), + ) + .field( + "lp_ana_touch_out_ring", + &format_args!("{}", self.lp_ana_touch_out_ring().bits()), + ) + .field( + "lp_ana_freq_scan_en", + &format_args!("{}", self.lp_ana_freq_scan_en().bit()), + ) + .field( + "lp_ana_freq_scan_cnt_limit", + &format_args!("{}", self.lp_ana_freq_scan_cnt_limit().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 6:21 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_timeout_num( + &mut self, + ) -> LP_ANA_TOUCH_TIMEOUT_NUM_W { + LP_ANA_TOUCH_TIMEOUT_NUM_W::new(self, 6) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_timeout_en( + &mut self, + ) -> LP_ANA_TOUCH_TIMEOUT_EN_W { + LP_ANA_TOUCH_TIMEOUT_EN_W::new(self, 22) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_out_ring( + &mut self, + ) -> LP_ANA_TOUCH_OUT_RING_W { + LP_ANA_TOUCH_OUT_RING_W::new(self, 23) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_freq_scan_en(&mut self) -> LP_ANA_FREQ_SCAN_EN_W { + LP_ANA_FREQ_SCAN_EN_W::new(self, 27) + } + #[doc = "Bits 28:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_freq_scan_cnt_limit( + &mut self, + ) -> LP_ANA_FREQ_SCAN_CNT_LIMIT_W { + LP_ANA_FREQ_SCAN_CNT_LIMIT_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_scan_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_scan_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_SCAN_CTRL2_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_SCAN_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_scan_ctrl2::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_SCAN_CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_scan_ctrl2::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_SCAN_CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_SCAN_CTRL2 to value 0x37bf_ffc0"] +impl crate::Resettable for LP_ANA_TOUCH_SCAN_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0x37bf_ffc0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_slp0.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_slp0.rs new file mode 100644 index 0000000000..c6a682c81d --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_slp0.rs @@ -0,0 +1,95 @@ +#[doc = "Register `LP_ANA_TOUCH_SLP0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_SLP0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_SLP_TH0` reader - need_des"] +pub type LP_ANA_TOUCH_SLP_TH0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_SLP_TH0` writer - need_des"] +pub type LP_ANA_TOUCH_SLP_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `LP_ANA_TOUCH_SLP_CHANNEL_CLR` writer - need_des"] +pub type LP_ANA_TOUCH_SLP_CHANNEL_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_SLP_PAD` reader - need_des"] +pub type LP_ANA_TOUCH_SLP_PAD_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_SLP_PAD` writer - need_des"] +pub type LP_ANA_TOUCH_SLP_PAD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_slp_th0(&self) -> LP_ANA_TOUCH_SLP_TH0_R { + LP_ANA_TOUCH_SLP_TH0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 17:20 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_slp_pad(&self) -> LP_ANA_TOUCH_SLP_PAD_R { + LP_ANA_TOUCH_SLP_PAD_R::new(((self.bits >> 17) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_SLP0") + .field( + "lp_ana_touch_slp_th0", + &format_args!("{}", self.lp_ana_touch_slp_th0().bits()), + ) + .field( + "lp_ana_touch_slp_pad", + &format_args!("{}", self.lp_ana_touch_slp_pad().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_slp_th0(&mut self) -> LP_ANA_TOUCH_SLP_TH0_W { + LP_ANA_TOUCH_SLP_TH0_W::new(self, 0) + } + #[doc = "Bit 16 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_slp_channel_clr( + &mut self, + ) -> LP_ANA_TOUCH_SLP_CHANNEL_CLR_W { + LP_ANA_TOUCH_SLP_CHANNEL_CLR_W::new(self, 16) + } + #[doc = "Bits 17:20 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_slp_pad(&mut self) -> LP_ANA_TOUCH_SLP_PAD_W { + LP_ANA_TOUCH_SLP_PAD_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_slp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_slp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_SLP0_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_SLP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_slp0::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_SLP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_slp0::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_SLP0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_SLP0 to value 0x001e_0000"] +impl crate::Resettable for LP_ANA_TOUCH_SLP0_SPEC { + const RESET_VALUE: Self::Ux = 0x001e_0000; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_slp1.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_slp1.rs new file mode 100644 index 0000000000..e2f7cc3ad5 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_slp1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `LP_ANA_TOUCH_SLP1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_SLP1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_SLP_TH2` reader - need_des"] +pub type LP_ANA_TOUCH_SLP_TH2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_SLP_TH2` writer - need_des"] +pub type LP_ANA_TOUCH_SLP_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `LP_ANA_TOUCH_SLP_TH1` reader - need_des"] +pub type LP_ANA_TOUCH_SLP_TH1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_SLP_TH1` writer - need_des"] +pub type LP_ANA_TOUCH_SLP_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_slp_th2(&self) -> LP_ANA_TOUCH_SLP_TH2_R { + LP_ANA_TOUCH_SLP_TH2_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_slp_th1(&self) -> LP_ANA_TOUCH_SLP_TH1_R { + LP_ANA_TOUCH_SLP_TH1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_SLP1") + .field( + "lp_ana_touch_slp_th2", + &format_args!("{}", self.lp_ana_touch_slp_th2().bits()), + ) + .field( + "lp_ana_touch_slp_th1", + &format_args!("{}", self.lp_ana_touch_slp_th1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_slp_th2(&mut self) -> LP_ANA_TOUCH_SLP_TH2_W { + LP_ANA_TOUCH_SLP_TH2_W::new(self, 0) + } + #[doc = "Bits 16:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_slp_th1(&mut self) -> LP_ANA_TOUCH_SLP_TH1_W { + LP_ANA_TOUCH_SLP_TH1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_slp1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_slp1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_SLP1_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_SLP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_slp1::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_SLP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_slp1::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_SLP1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_SLP1 to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_SLP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_work.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_work.rs new file mode 100644 index 0000000000..3f53798b9d --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_work.rs @@ -0,0 +1,150 @@ +#[doc = "Register `LP_ANA_TOUCH_WORK` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_WORK` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_DIV_NUM2` reader - need_des"] +pub type LP_ANA_DIV_NUM2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_DIV_NUM2` writer - need_des"] +pub type LP_ANA_DIV_NUM2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LP_ANA_DIV_NUM1` reader - need_des"] +pub type LP_ANA_DIV_NUM1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_DIV_NUM1` writer - need_des"] +pub type LP_ANA_DIV_NUM1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LP_ANA_DIV_NUM0` reader - need_des"] +pub type LP_ANA_DIV_NUM0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_DIV_NUM0` writer - need_des"] +pub type LP_ANA_DIV_NUM0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LP_ANA_TOUCH_OUT_SEL` reader - need_des"] +pub type LP_ANA_TOUCH_OUT_SEL_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_OUT_SEL` writer - need_des"] +pub type LP_ANA_TOUCH_OUT_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_OUT_RESET` writer - need_des"] +pub type LP_ANA_TOUCH_OUT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_TOUCH_OUT_GATE` reader - need_des"] +pub type LP_ANA_TOUCH_OUT_GATE_R = crate::BitReader; +#[doc = "Field `LP_ANA_TOUCH_OUT_GATE` writer - need_des"] +pub type LP_ANA_TOUCH_OUT_GATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn lp_ana_div_num2(&self) -> LP_ANA_DIV_NUM2_R { + LP_ANA_DIV_NUM2_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:21 - need_des"] + #[inline(always)] + pub fn lp_ana_div_num1(&self) -> LP_ANA_DIV_NUM1_R { + LP_ANA_DIV_NUM1_R::new(((self.bits >> 19) & 7) as u8) + } + #[doc = "Bits 22:24 - need_des"] + #[inline(always)] + pub fn lp_ana_div_num0(&self) -> LP_ANA_DIV_NUM0_R { + LP_ANA_DIV_NUM0_R::new(((self.bits >> 22) & 7) as u8) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_out_sel(&self) -> LP_ANA_TOUCH_OUT_SEL_R { + LP_ANA_TOUCH_OUT_SEL_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_out_gate(&self) -> LP_ANA_TOUCH_OUT_GATE_R { + LP_ANA_TOUCH_OUT_GATE_R::new(((self.bits >> 27) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_WORK") + .field( + "lp_ana_div_num2", + &format_args!("{}", self.lp_ana_div_num2().bits()), + ) + .field( + "lp_ana_div_num1", + &format_args!("{}", self.lp_ana_div_num1().bits()), + ) + .field( + "lp_ana_div_num0", + &format_args!("{}", self.lp_ana_div_num0().bits()), + ) + .field( + "lp_ana_touch_out_sel", + &format_args!("{}", self.lp_ana_touch_out_sel().bit()), + ) + .field( + "lp_ana_touch_out_gate", + &format_args!("{}", self.lp_ana_touch_out_gate().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_div_num2(&mut self) -> LP_ANA_DIV_NUM2_W { + LP_ANA_DIV_NUM2_W::new(self, 16) + } + #[doc = "Bits 19:21 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_div_num1(&mut self) -> LP_ANA_DIV_NUM1_W { + LP_ANA_DIV_NUM1_W::new(self, 19) + } + #[doc = "Bits 22:24 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_div_num0(&mut self) -> LP_ANA_DIV_NUM0_W { + LP_ANA_DIV_NUM0_W::new(self, 22) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_out_sel(&mut self) -> LP_ANA_TOUCH_OUT_SEL_W { + LP_ANA_TOUCH_OUT_SEL_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_out_reset(&mut self) -> LP_ANA_TOUCH_OUT_RESET_W { + LP_ANA_TOUCH_OUT_RESET_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_out_gate(&mut self) -> LP_ANA_TOUCH_OUT_GATE_W { + LP_ANA_TOUCH_OUT_GATE_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_work::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_work::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_WORK_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_WORK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_work::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_WORK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_work::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_WORK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_WORK to value 0"] +impl crate::Resettable for LP_ANA_TOUCH_WORK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_touch_work_meas_num.rs b/esp32p4/src/lp_ana_peri/lp_ana_touch_work_meas_num.rs new file mode 100644 index 0000000000..954656de60 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_touch_work_meas_num.rs @@ -0,0 +1,110 @@ +#[doc = "Register `LP_ANA_TOUCH_WORK_MEAS_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_TOUCH_WORK_MEAS_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_TOUCH_MEAS_NUM2` reader - need_des"] +pub type LP_ANA_TOUCH_MEAS_NUM2_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_MEAS_NUM2` writer - need_des"] +pub type LP_ANA_TOUCH_MEAS_NUM2_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `LP_ANA_TOUCH_MEAS_NUM1` reader - need_des"] +pub type LP_ANA_TOUCH_MEAS_NUM1_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_MEAS_NUM1` writer - need_des"] +pub type LP_ANA_TOUCH_MEAS_NUM1_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `LP_ANA_TOUCH_MEAS_NUM0` reader - need_des"] +pub type LP_ANA_TOUCH_MEAS_NUM0_R = crate::FieldReader; +#[doc = "Field `LP_ANA_TOUCH_MEAS_NUM0` writer - need_des"] +pub type LP_ANA_TOUCH_MEAS_NUM0_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_meas_num2(&self) -> LP_ANA_TOUCH_MEAS_NUM2_R { + LP_ANA_TOUCH_MEAS_NUM2_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:19 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_meas_num1(&self) -> LP_ANA_TOUCH_MEAS_NUM1_R { + LP_ANA_TOUCH_MEAS_NUM1_R::new(((self.bits >> 10) & 0x03ff) as u16) + } + #[doc = "Bits 20:29 - need_des"] + #[inline(always)] + pub fn lp_ana_touch_meas_num0(&self) -> LP_ANA_TOUCH_MEAS_NUM0_R { + LP_ANA_TOUCH_MEAS_NUM0_R::new(((self.bits >> 20) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_TOUCH_WORK_MEAS_NUM") + .field( + "lp_ana_touch_meas_num2", + &format_args!("{}", self.lp_ana_touch_meas_num2().bits()), + ) + .field( + "lp_ana_touch_meas_num1", + &format_args!("{}", self.lp_ana_touch_meas_num1().bits()), + ) + .field( + "lp_ana_touch_meas_num0", + &format_args!("{}", self.lp_ana_touch_meas_num0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_meas_num2( + &mut self, + ) -> LP_ANA_TOUCH_MEAS_NUM2_W { + LP_ANA_TOUCH_MEAS_NUM2_W::new(self, 0) + } + #[doc = "Bits 10:19 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_meas_num1( + &mut self, + ) -> LP_ANA_TOUCH_MEAS_NUM1_W { + LP_ANA_TOUCH_MEAS_NUM1_W::new(self, 10) + } + #[doc = "Bits 20:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_touch_meas_num0( + &mut self, + ) -> LP_ANA_TOUCH_MEAS_NUM0_W { + LP_ANA_TOUCH_MEAS_NUM0_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_touch_work_meas_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_touch_work_meas_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_TOUCH_WORK_MEAS_NUM_SPEC; +impl crate::RegisterSpec for LP_ANA_TOUCH_WORK_MEAS_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_touch_work_meas_num::R`](R) reader structure"] +impl crate::Readable for LP_ANA_TOUCH_WORK_MEAS_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_touch_work_meas_num::W`](W) writer structure"] +impl crate::Writable for LP_ANA_TOUCH_WORK_MEAS_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_TOUCH_WORK_MEAS_NUM to value 0x0641_9064"] +impl crate::Resettable for LP_ANA_TOUCH_WORK_MEAS_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0x0641_9064; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_vdd_source_cntl.rs b/esp32p4/src/lp_ana_peri/lp_ana_vdd_source_cntl.rs new file mode 100644 index 0000000000..15aedd791e --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_vdd_source_cntl.rs @@ -0,0 +1,108 @@ +#[doc = "Register `LP_ANA_VDD_SOURCE_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_VDD_SOURCE_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_DETMODE_SEL` reader - need_des"] +pub type LP_ANA_DETMODE_SEL_R = crate::FieldReader; +#[doc = "Field `LP_ANA_DETMODE_SEL` writer - need_des"] +pub type LP_ANA_DETMODE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LP_ANA_VGOOD_EVENT_RECORD` reader - need_des"] +pub type LP_ANA_VGOOD_EVENT_RECORD_R = crate::FieldReader; +#[doc = "Field `LP_ANA_VBAT_EVENT_RECORD_CLR` writer - need_des"] +pub type LP_ANA_VBAT_EVENT_RECORD_CLR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LP_ANA_BOD_SOURCE_ENA` reader - need_des"] +pub type LP_ANA_BOD_SOURCE_ENA_R = crate::FieldReader; +#[doc = "Field `LP_ANA_BOD_SOURCE_ENA` writer - need_des"] +pub type LP_ANA_BOD_SOURCE_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + pub fn lp_ana_detmode_sel(&self) -> LP_ANA_DETMODE_SEL_R { + LP_ANA_DETMODE_SEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - need_des"] + #[inline(always)] + pub fn lp_ana_vgood_event_record(&self) -> LP_ANA_VGOOD_EVENT_RECORD_R { + LP_ANA_VGOOD_EVENT_RECORD_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + pub fn lp_ana_bod_source_ena(&self) -> LP_ANA_BOD_SOURCE_ENA_R { + LP_ANA_BOD_SOURCE_ENA_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_VDD_SOURCE_CNTL") + .field( + "lp_ana_detmode_sel", + &format_args!("{}", self.lp_ana_detmode_sel().bits()), + ) + .field( + "lp_ana_vgood_event_record", + &format_args!("{}", self.lp_ana_vgood_event_record().bits()), + ) + .field( + "lp_ana_bod_source_ena", + &format_args!("{}", self.lp_ana_bod_source_ena().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_detmode_sel(&mut self) -> LP_ANA_DETMODE_SEL_W { + LP_ANA_DETMODE_SEL_W::new(self, 0) + } + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vbat_event_record_clr( + &mut self, + ) -> LP_ANA_VBAT_EVENT_RECORD_CLR_W { + LP_ANA_VBAT_EVENT_RECORD_CLR_W::new(self, 16) + } + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_bod_source_ena( + &mut self, + ) -> LP_ANA_BOD_SOURCE_ENA_W { + LP_ANA_BOD_SOURCE_ENA_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_vdd_source_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_vdd_source_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_VDD_SOURCE_CNTL_SPEC; +impl crate::RegisterSpec for LP_ANA_VDD_SOURCE_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_vdd_source_cntl::R`](R) reader structure"] +impl crate::Readable for LP_ANA_VDD_SOURCE_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_vdd_source_cntl::W`](W) writer structure"] +impl crate::Writable for LP_ANA_VDD_SOURCE_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_VDD_SOURCE_CNTL to value 0x0400_00ff"] +impl crate::Resettable for LP_ANA_VDD_SOURCE_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x0400_00ff; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_vddbat_bod_cntl.rs b/esp32p4/src/lp_ana_peri/lp_ana_vddbat_bod_cntl.rs new file mode 100644 index 0000000000..1da9671680 --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_vddbat_bod_cntl.rs @@ -0,0 +1,142 @@ +#[doc = "Register `LP_ANA_VDDBAT_BOD_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_VDDBAT_BOD_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG` reader - need_des"] +pub type LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGER` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGER_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGER` writer - need_des"] +pub type LP_ANA_VDDBAT_CHARGER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_CNT_CLR` reader - need_des"] +pub type LP_ANA_VDDBAT_CNT_CLR_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_CNT_CLR` writer - need_des"] +pub type LP_ANA_VDDBAT_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_UPVOLTAGE_TARGET` reader - need_des"] +pub type LP_ANA_VDDBAT_UPVOLTAGE_TARGET_R = crate::FieldReader; +#[doc = "Field `LP_ANA_VDDBAT_UPVOLTAGE_TARGET` writer - need_des"] +pub type LP_ANA_VDDBAT_UPVOLTAGE_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET` reader - need_des"] +pub type LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_R = crate::FieldReader; +#[doc = "Field `LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET` writer - need_des"] +pub type LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_undervoltage_flag(&self) -> LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_R { + LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charger(&self) -> LP_ANA_VDDBAT_CHARGER_R { + LP_ANA_VDDBAT_CHARGER_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_cnt_clr(&self) -> LP_ANA_VDDBAT_CNT_CLR_R { + LP_ANA_VDDBAT_CNT_CLR_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:21 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_upvoltage_target(&self) -> LP_ANA_VDDBAT_UPVOLTAGE_TARGET_R { + LP_ANA_VDDBAT_UPVOLTAGE_TARGET_R::new(((self.bits >> 12) & 0x03ff) as u16) + } + #[doc = "Bits 22:31 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_undervoltage_target(&self) -> LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_R { + LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_R::new(((self.bits >> 22) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_VDDBAT_BOD_CNTL") + .field( + "lp_ana_vddbat_undervoltage_flag", + &format_args!("{}", self.lp_ana_vddbat_undervoltage_flag().bit()), + ) + .field( + "lp_ana_vddbat_charger", + &format_args!("{}", self.lp_ana_vddbat_charger().bit()), + ) + .field( + "lp_ana_vddbat_cnt_clr", + &format_args!("{}", self.lp_ana_vddbat_cnt_clr().bit()), + ) + .field( + "lp_ana_vddbat_upvoltage_target", + &format_args!("{}", self.lp_ana_vddbat_upvoltage_target().bits()), + ) + .field( + "lp_ana_vddbat_undervoltage_target", + &format_args!("{}", self.lp_ana_vddbat_undervoltage_target().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 10 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_charger( + &mut self, + ) -> LP_ANA_VDDBAT_CHARGER_W { + LP_ANA_VDDBAT_CHARGER_W::new(self, 10) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_cnt_clr( + &mut self, + ) -> LP_ANA_VDDBAT_CNT_CLR_W { + LP_ANA_VDDBAT_CNT_CLR_W::new(self, 11) + } + #[doc = "Bits 12:21 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_upvoltage_target( + &mut self, + ) -> LP_ANA_VDDBAT_UPVOLTAGE_TARGET_W { + LP_ANA_VDDBAT_UPVOLTAGE_TARGET_W::new(self, 12) + } + #[doc = "Bits 22:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_undervoltage_target( + &mut self, + ) -> LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_W { + LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_vddbat_bod_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_vddbat_bod_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_VDDBAT_BOD_CNTL_SPEC; +impl crate::RegisterSpec for LP_ANA_VDDBAT_BOD_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_vddbat_bod_cntl::R`](R) reader structure"] +impl crate::Readable for LP_ANA_VDDBAT_BOD_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_vddbat_bod_cntl::W`](W) writer structure"] +impl crate::Writable for LP_ANA_VDDBAT_BOD_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_VDDBAT_BOD_CNTL to value 0xffc0_0000"] +impl crate::Resettable for LP_ANA_VDDBAT_BOD_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0xffc0_0000; +} diff --git a/esp32p4/src/lp_ana_peri/lp_ana_vddbat_charge_cntl.rs b/esp32p4/src/lp_ana_peri/lp_ana_vddbat_charge_cntl.rs new file mode 100644 index 0000000000..9d9492221b --- /dev/null +++ b/esp32p4/src/lp_ana_peri/lp_ana_vddbat_charge_cntl.rs @@ -0,0 +1,146 @@ +#[doc = "Register `LP_ANA_VDDBAT_CHARGE_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ANA_VDDBAT_CHARGE_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_CHARGER` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_CHARGER_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_CHARGER` writer - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_CHARGER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_CNT_CLR` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_CNT_CLR_R = crate::BitReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_CNT_CLR` writer - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_R = crate::FieldReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET` writer - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET` reader - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_R = crate::FieldReader; +#[doc = "Field `LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET` writer - need_des"] +pub type LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charge_undervoltage_flag( + &self, + ) -> LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_R { + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charge_charger(&self) -> LP_ANA_VDDBAT_CHARGE_CHARGER_R { + LP_ANA_VDDBAT_CHARGE_CHARGER_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charge_cnt_clr(&self) -> LP_ANA_VDDBAT_CHARGE_CNT_CLR_R { + LP_ANA_VDDBAT_CHARGE_CNT_CLR_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:21 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charge_upvoltage_target(&self) -> LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_R { + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_R::new(((self.bits >> 12) & 0x03ff) as u16) + } + #[doc = "Bits 22:31 - need_des"] + #[inline(always)] + pub fn lp_ana_vddbat_charge_undervoltage_target( + &self, + ) -> LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_R { + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_R::new(((self.bits >> 22) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ANA_VDDBAT_CHARGE_CNTL") + .field( + "lp_ana_vddbat_charge_undervoltage_flag", + &format_args!("{}", self.lp_ana_vddbat_charge_undervoltage_flag().bit()), + ) + .field( + "lp_ana_vddbat_charge_charger", + &format_args!("{}", self.lp_ana_vddbat_charge_charger().bit()), + ) + .field( + "lp_ana_vddbat_charge_cnt_clr", + &format_args!("{}", self.lp_ana_vddbat_charge_cnt_clr().bit()), + ) + .field( + "lp_ana_vddbat_charge_upvoltage_target", + &format_args!("{}", self.lp_ana_vddbat_charge_upvoltage_target().bits()), + ) + .field( + "lp_ana_vddbat_charge_undervoltage_target", + &format_args!("{}", self.lp_ana_vddbat_charge_undervoltage_target().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 10 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_charge_charger( + &mut self, + ) -> LP_ANA_VDDBAT_CHARGE_CHARGER_W { + LP_ANA_VDDBAT_CHARGE_CHARGER_W::new(self, 10) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_charge_cnt_clr( + &mut self, + ) -> LP_ANA_VDDBAT_CHARGE_CNT_CLR_W { + LP_ANA_VDDBAT_CHARGE_CNT_CLR_W::new(self, 11) + } + #[doc = "Bits 12:21 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_charge_upvoltage_target( + &mut self, + ) -> LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_W { + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_W::new(self, 12) + } + #[doc = "Bits 22:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_vddbat_charge_undervoltage_target( + &mut self, + ) -> LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_W { + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_ana_vddbat_charge_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_ana_vddbat_charge_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ANA_VDDBAT_CHARGE_CNTL_SPEC; +impl crate::RegisterSpec for LP_ANA_VDDBAT_CHARGE_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_ana_vddbat_charge_cntl::R`](R) reader structure"] +impl crate::Readable for LP_ANA_VDDBAT_CHARGE_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_ana_vddbat_charge_cntl::W`](W) writer structure"] +impl crate::Writable for LP_ANA_VDDBAT_CHARGE_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ANA_VDDBAT_CHARGE_CNTL to value 0xffc0_0000"] +impl crate::Resettable for LP_ANA_VDDBAT_CHARGE_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0xffc0_0000; +} diff --git a/esp32p4/src/lp_aon_clkrst.rs b/esp32p4/src/lp_aon_clkrst.rs new file mode 100644 index 0000000000..7acf463c20 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst.rs @@ -0,0 +1,238 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + lp_aonclkrst_lp_clk_conf: LP_AONCLKRST_LP_CLK_CONF, + lp_aonclkrst_lp_clk_po_en: LP_AONCLKRST_LP_CLK_PO_EN, + lp_aonclkrst_lp_clk_en: LP_AONCLKRST_LP_CLK_EN, + lp_aonclkrst_lp_rst_en: LP_AONCLKRST_LP_RST_EN, + lp_aonclkrst_reset_cause: LP_AONCLKRST_RESET_CAUSE, + lp_aonclkrst_hpcpu_reset_ctrl0: LP_AONCLKRST_HPCPU_RESET_CTRL0, + lp_aonclkrst_hpcpu_reset_ctrl1: LP_AONCLKRST_HPCPU_RESET_CTRL1, + lp_aonclkrst_fosc_cntl: LP_AONCLKRST_FOSC_CNTL, + lp_aonclkrst_rc32k_cntl: LP_AONCLKRST_RC32K_CNTL, + lp_aonclkrst_sosc_cntl: LP_AONCLKRST_SOSC_CNTL, + lp_aonclkrst_clk_to_hp: LP_AONCLKRST_CLK_TO_HP, + lp_aonclkrst_lpmem_force: LP_AONCLKRST_LPMEM_FORCE, + lp_aonclkrst_xtal32k: LP_AONCLKRST_XTAL32K, + lp_aonclkrst_mux_hpsys_reset_bypass: LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS, + lp_aonclkrst_hpsys_0_reset_bypass: LP_AONCLKRST_HPSYS_0_RESET_BYPASS, + lp_aonclkrst_hpsys_apm_reset_bypass: LP_AONCLKRST_HPSYS_APM_RESET_BYPASS, + lp_aonclkrst_hp_clk_ctrl: LP_AONCLKRST_HP_CLK_CTRL, + lp_aonclkrst_hp_usb_clkrst_ctrl0: LP_AONCLKRST_HP_USB_CLKRST_CTRL0, + lp_aonclkrst_hp_usb_clkrst_ctrl1: LP_AONCLKRST_HP_USB_CLKRST_CTRL1, + lp_aonclkrst_hp_sdmmc_emac_rst_ctrl: LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL, + _reserved20: [u8; 0x03ac], + lp_aonclkrst_date: LP_AONCLKRST_DATE, +} +impl RegisterBlock { + #[doc = "0x00 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_lp_clk_conf(&self) -> &LP_AONCLKRST_LP_CLK_CONF { + &self.lp_aonclkrst_lp_clk_conf + } + #[doc = "0x04 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_lp_clk_po_en(&self) -> &LP_AONCLKRST_LP_CLK_PO_EN { + &self.lp_aonclkrst_lp_clk_po_en + } + #[doc = "0x08 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_lp_clk_en(&self) -> &LP_AONCLKRST_LP_CLK_EN { + &self.lp_aonclkrst_lp_clk_en + } + #[doc = "0x0c - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_lp_rst_en(&self) -> &LP_AONCLKRST_LP_RST_EN { + &self.lp_aonclkrst_lp_rst_en + } + #[doc = "0x10 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_reset_cause(&self) -> &LP_AONCLKRST_RESET_CAUSE { + &self.lp_aonclkrst_reset_cause + } + #[doc = "0x14 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_hpcpu_reset_ctrl0(&self) -> &LP_AONCLKRST_HPCPU_RESET_CTRL0 { + &self.lp_aonclkrst_hpcpu_reset_ctrl0 + } + #[doc = "0x18 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_hpcpu_reset_ctrl1(&self) -> &LP_AONCLKRST_HPCPU_RESET_CTRL1 { + &self.lp_aonclkrst_hpcpu_reset_ctrl1 + } + #[doc = "0x1c - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_fosc_cntl(&self) -> &LP_AONCLKRST_FOSC_CNTL { + &self.lp_aonclkrst_fosc_cntl + } + #[doc = "0x20 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_rc32k_cntl(&self) -> &LP_AONCLKRST_RC32K_CNTL { + &self.lp_aonclkrst_rc32k_cntl + } + #[doc = "0x24 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_sosc_cntl(&self) -> &LP_AONCLKRST_SOSC_CNTL { + &self.lp_aonclkrst_sosc_cntl + } + #[doc = "0x28 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_clk_to_hp(&self) -> &LP_AONCLKRST_CLK_TO_HP { + &self.lp_aonclkrst_clk_to_hp + } + #[doc = "0x2c - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_lpmem_force(&self) -> &LP_AONCLKRST_LPMEM_FORCE { + &self.lp_aonclkrst_lpmem_force + } + #[doc = "0x30 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_xtal32k(&self) -> &LP_AONCLKRST_XTAL32K { + &self.lp_aonclkrst_xtal32k + } + #[doc = "0x34 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_mux_hpsys_reset_bypass( + &self, + ) -> &LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS { + &self.lp_aonclkrst_mux_hpsys_reset_bypass + } + #[doc = "0x38 - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_hpsys_0_reset_bypass(&self) -> &LP_AONCLKRST_HPSYS_0_RESET_BYPASS { + &self.lp_aonclkrst_hpsys_0_reset_bypass + } + #[doc = "0x3c - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_hpsys_apm_reset_bypass( + &self, + ) -> &LP_AONCLKRST_HPSYS_APM_RESET_BYPASS { + &self.lp_aonclkrst_hpsys_apm_reset_bypass + } + #[doc = "0x40 - HP Clock Control Register."] + #[inline(always)] + pub const fn lp_aonclkrst_hp_clk_ctrl(&self) -> &LP_AONCLKRST_HP_CLK_CTRL { + &self.lp_aonclkrst_hp_clk_ctrl + } + #[doc = "0x44 - HP USB Clock Reset Control Register."] + #[inline(always)] + pub const fn lp_aonclkrst_hp_usb_clkrst_ctrl0(&self) -> &LP_AONCLKRST_HP_USB_CLKRST_CTRL0 { + &self.lp_aonclkrst_hp_usb_clkrst_ctrl0 + } + #[doc = "0x48 - HP USB Clock Reset Control Register."] + #[inline(always)] + pub const fn lp_aonclkrst_hp_usb_clkrst_ctrl1(&self) -> &LP_AONCLKRST_HP_USB_CLKRST_CTRL1 { + &self.lp_aonclkrst_hp_usb_clkrst_ctrl1 + } + #[doc = "0x4c - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_hp_sdmmc_emac_rst_ctrl( + &self, + ) -> &LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL { + &self.lp_aonclkrst_hp_sdmmc_emac_rst_ctrl + } + #[doc = "0x3fc - need_des"] + #[inline(always)] + pub const fn lp_aonclkrst_date(&self) -> &LP_AONCLKRST_DATE { + &self.lp_aonclkrst_date + } +} +#[doc = "LP_AONCLKRST_LP_CLK_CONF (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_lp_clk_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_lp_clk_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_lp_clk_conf`] module"] +pub type LP_AONCLKRST_LP_CLK_CONF = + crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_lp_clk_conf; +#[doc = "LP_AONCLKRST_LP_CLK_PO_EN (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_lp_clk_po_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_lp_clk_po_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_lp_clk_po_en`] module"] +pub type LP_AONCLKRST_LP_CLK_PO_EN = + crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_lp_clk_po_en; +#[doc = "LP_AONCLKRST_LP_CLK_EN (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_lp_clk_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_lp_clk_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_lp_clk_en`] module"] +pub type LP_AONCLKRST_LP_CLK_EN = crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_lp_clk_en; +#[doc = "LP_AONCLKRST_LP_RST_EN (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_lp_rst_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_lp_rst_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_lp_rst_en`] module"] +pub type LP_AONCLKRST_LP_RST_EN = crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_lp_rst_en; +#[doc = "LP_AONCLKRST_RESET_CAUSE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_reset_cause::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_reset_cause::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_reset_cause`] module"] +pub type LP_AONCLKRST_RESET_CAUSE = + crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_reset_cause; +#[doc = "LP_AONCLKRST_HPCPU_RESET_CTRL0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hpcpu_reset_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hpcpu_reset_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_hpcpu_reset_ctrl0`] module"] +pub type LP_AONCLKRST_HPCPU_RESET_CTRL0 = + crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_hpcpu_reset_ctrl0; +#[doc = "LP_AONCLKRST_HPCPU_RESET_CTRL1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hpcpu_reset_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hpcpu_reset_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_hpcpu_reset_ctrl1`] module"] +pub type LP_AONCLKRST_HPCPU_RESET_CTRL1 = + crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_hpcpu_reset_ctrl1; +#[doc = "LP_AONCLKRST_FOSC_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_fosc_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_fosc_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_fosc_cntl`] module"] +pub type LP_AONCLKRST_FOSC_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_fosc_cntl; +#[doc = "LP_AONCLKRST_RC32K_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_rc32k_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_rc32k_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_rc32k_cntl`] module"] +pub type LP_AONCLKRST_RC32K_CNTL = + crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_rc32k_cntl; +#[doc = "LP_AONCLKRST_SOSC_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_sosc_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_sosc_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_sosc_cntl`] module"] +pub type LP_AONCLKRST_SOSC_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_sosc_cntl; +#[doc = "LP_AONCLKRST_CLK_TO_HP (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_clk_to_hp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_clk_to_hp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_clk_to_hp`] module"] +pub type LP_AONCLKRST_CLK_TO_HP = crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_clk_to_hp; +#[doc = "LP_AONCLKRST_LPMEM_FORCE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_lpmem_force::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_lpmem_force::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_lpmem_force`] module"] +pub type LP_AONCLKRST_LPMEM_FORCE = + crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_lpmem_force; +#[doc = "LP_AONCLKRST_XTAL32K (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_xtal32k::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_xtal32k::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_xtal32k`] module"] +pub type LP_AONCLKRST_XTAL32K = crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_xtal32k; +#[doc = "LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_mux_hpsys_reset_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_mux_hpsys_reset_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_mux_hpsys_reset_bypass`] module"] +pub type LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS = + crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_mux_hpsys_reset_bypass; +#[doc = "LP_AONCLKRST_HPSYS_0_RESET_BYPASS (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hpsys_0_reset_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hpsys_0_reset_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_hpsys_0_reset_bypass`] module"] +pub type LP_AONCLKRST_HPSYS_0_RESET_BYPASS = + crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_hpsys_0_reset_bypass; +#[doc = "LP_AONCLKRST_HPSYS_APM_RESET_BYPASS (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hpsys_apm_reset_bypass::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hpsys_apm_reset_bypass::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_hpsys_apm_reset_bypass`] module"] +pub type LP_AONCLKRST_HPSYS_APM_RESET_BYPASS = + crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_hpsys_apm_reset_bypass; +#[doc = "LP_AONCLKRST_HP_CLK_CTRL (rw) register accessor: HP Clock Control Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hp_clk_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hp_clk_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_hp_clk_ctrl`] module"] +pub type LP_AONCLKRST_HP_CLK_CTRL = + crate::Reg; +#[doc = "HP Clock Control Register."] +pub mod lp_aonclkrst_hp_clk_ctrl; +#[doc = "LP_AONCLKRST_HP_USB_CLKRST_CTRL0 (rw) register accessor: HP USB Clock Reset Control Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hp_usb_clkrst_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hp_usb_clkrst_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_hp_usb_clkrst_ctrl0`] module"] +pub type LP_AONCLKRST_HP_USB_CLKRST_CTRL0 = + crate::Reg; +#[doc = "HP USB Clock Reset Control Register."] +pub mod lp_aonclkrst_hp_usb_clkrst_ctrl0; +#[doc = "LP_AONCLKRST_HP_USB_CLKRST_CTRL1 (rw) register accessor: HP USB Clock Reset Control Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hp_usb_clkrst_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hp_usb_clkrst_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_hp_usb_clkrst_ctrl1`] module"] +pub type LP_AONCLKRST_HP_USB_CLKRST_CTRL1 = + crate::Reg; +#[doc = "HP USB Clock Reset Control Register."] +pub mod lp_aonclkrst_hp_usb_clkrst_ctrl1; +#[doc = "LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hp_sdmmc_emac_rst_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hp_sdmmc_emac_rst_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_hp_sdmmc_emac_rst_ctrl`] module"] +pub type LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL = + crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_hp_sdmmc_emac_rst_ctrl; +#[doc = "LP_AONCLKRST_DATE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_aonclkrst_date`] module"] +pub type LP_AONCLKRST_DATE = crate::Reg; +#[doc = "need_des"] +pub mod lp_aonclkrst_date; diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_clk_to_hp.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_clk_to_hp.rs new file mode 100644 index 0000000000..3e1151c598 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_clk_to_hp.rs @@ -0,0 +1,131 @@ +#[doc = "Register `LP_AONCLKRST_CLK_TO_HP` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_CLK_TO_HP` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_ICG_HP_XTAL32K` reader - reserved"] +pub type LP_AONCLKRST_ICG_HP_XTAL32K_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_ICG_HP_XTAL32K` writer - reserved"] +pub type LP_AONCLKRST_ICG_HP_XTAL32K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_ICG_HP_SOSC` reader - reserved"] +pub type LP_AONCLKRST_ICG_HP_SOSC_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_ICG_HP_SOSC` writer - reserved"] +pub type LP_AONCLKRST_ICG_HP_SOSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_ICG_HP_OSC32K` reader - reserved"] +pub type LP_AONCLKRST_ICG_HP_OSC32K_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_ICG_HP_OSC32K` writer - reserved"] +pub type LP_AONCLKRST_ICG_HP_OSC32K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_ICG_HP_FOSC` reader - reserved"] +pub type LP_AONCLKRST_ICG_HP_FOSC_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_ICG_HP_FOSC` writer - reserved"] +pub type LP_AONCLKRST_ICG_HP_FOSC_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 28 - reserved"] + #[inline(always)] + pub fn lp_aonclkrst_icg_hp_xtal32k(&self) -> LP_AONCLKRST_ICG_HP_XTAL32K_R { + LP_AONCLKRST_ICG_HP_XTAL32K_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - reserved"] + #[inline(always)] + pub fn lp_aonclkrst_icg_hp_sosc(&self) -> LP_AONCLKRST_ICG_HP_SOSC_R { + LP_AONCLKRST_ICG_HP_SOSC_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - reserved"] + #[inline(always)] + pub fn lp_aonclkrst_icg_hp_osc32k(&self) -> LP_AONCLKRST_ICG_HP_OSC32K_R { + LP_AONCLKRST_ICG_HP_OSC32K_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - reserved"] + #[inline(always)] + pub fn lp_aonclkrst_icg_hp_fosc(&self) -> LP_AONCLKRST_ICG_HP_FOSC_R { + LP_AONCLKRST_ICG_HP_FOSC_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_CLK_TO_HP") + .field( + "lp_aonclkrst_icg_hp_xtal32k", + &format_args!("{}", self.lp_aonclkrst_icg_hp_xtal32k().bit()), + ) + .field( + "lp_aonclkrst_icg_hp_sosc", + &format_args!("{}", self.lp_aonclkrst_icg_hp_sosc().bit()), + ) + .field( + "lp_aonclkrst_icg_hp_osc32k", + &format_args!("{}", self.lp_aonclkrst_icg_hp_osc32k().bit()), + ) + .field( + "lp_aonclkrst_icg_hp_fosc", + &format_args!("{}", self.lp_aonclkrst_icg_hp_fosc().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 28 - reserved"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_icg_hp_xtal32k( + &mut self, + ) -> LP_AONCLKRST_ICG_HP_XTAL32K_W { + LP_AONCLKRST_ICG_HP_XTAL32K_W::new(self, 28) + } + #[doc = "Bit 29 - reserved"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_icg_hp_sosc( + &mut self, + ) -> LP_AONCLKRST_ICG_HP_SOSC_W { + LP_AONCLKRST_ICG_HP_SOSC_W::new(self, 29) + } + #[doc = "Bit 30 - reserved"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_icg_hp_osc32k( + &mut self, + ) -> LP_AONCLKRST_ICG_HP_OSC32K_W { + LP_AONCLKRST_ICG_HP_OSC32K_W::new(self, 30) + } + #[doc = "Bit 31 - reserved"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_icg_hp_fosc( + &mut self, + ) -> LP_AONCLKRST_ICG_HP_FOSC_W { + LP_AONCLKRST_ICG_HP_FOSC_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_clk_to_hp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_clk_to_hp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_CLK_TO_HP_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_CLK_TO_HP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_clk_to_hp::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_CLK_TO_HP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_clk_to_hp::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_CLK_TO_HP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_CLK_TO_HP to value 0xf000_0000"] +impl crate::Resettable for LP_AONCLKRST_CLK_TO_HP_SPEC { + const RESET_VALUE: Self::Ux = 0xf000_0000; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_date.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_date.rs new file mode 100644 index 0000000000..332f502966 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_date.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_AONCLKRST_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_CLK_EN` reader - need_des"] +pub type LP_AONCLKRST_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CLK_EN` writer - need_des"] +pub type LP_AONCLKRST_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_clk_en(&self) -> LP_AONCLKRST_CLK_EN_R { + LP_AONCLKRST_CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_DATE") + .field( + "lp_aonclkrst_clk_en", + &format_args!("{}", self.lp_aonclkrst_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_clk_en(&mut self) -> LP_AONCLKRST_CLK_EN_W { + LP_AONCLKRST_CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_DATE_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_date::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_date::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_DATE to value 0"] +impl crate::Resettable for LP_AONCLKRST_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_fosc_cntl.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_fosc_cntl.rs new file mode 100644 index 0000000000..894a44eb9e --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_fosc_cntl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_AONCLKRST_FOSC_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_FOSC_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_FOSC_DFREQ` reader - need_des"] +pub type LP_AONCLKRST_FOSC_DFREQ_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_FOSC_DFREQ` writer - need_des"] +pub type LP_AONCLKRST_FOSC_DFREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 22:31 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_fosc_dfreq(&self) -> LP_AONCLKRST_FOSC_DFREQ_R { + LP_AONCLKRST_FOSC_DFREQ_R::new(((self.bits >> 22) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_FOSC_CNTL") + .field( + "lp_aonclkrst_fosc_dfreq", + &format_args!("{}", self.lp_aonclkrst_fosc_dfreq().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 22:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_fosc_dfreq( + &mut self, + ) -> LP_AONCLKRST_FOSC_DFREQ_W { + LP_AONCLKRST_FOSC_DFREQ_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_fosc_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_fosc_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_FOSC_CNTL_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_FOSC_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_fosc_cntl::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_FOSC_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_fosc_cntl::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_FOSC_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_FOSC_CNTL to value 0x6400_0000"] +impl crate::Resettable for LP_AONCLKRST_FOSC_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x6400_0000; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_clk_ctrl.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_clk_ctrl.rs new file mode 100644 index 0000000000..c437f9cdb4 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_clk_ctrl.rs @@ -0,0 +1,635 @@ +#[doc = "Register `LP_AONCLKRST_HP_CLK_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_HP_CLK_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL` reader - HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m."] +pub type LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL` writer - HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m."] +pub type LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_AONCLKRST_HP_ROOT_CLK_EN` reader - HP SoC Root Clock Enable."] +pub type LP_AONCLKRST_HP_ROOT_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_ROOT_CLK_EN` writer - HP SoC Root Clock Enable."] +pub type LP_AONCLKRST_HP_ROOT_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN` reader - PARLIO TX Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN` writer - PARLIO TX Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN` reader - PARLIO RX Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN` writer - PARLIO RX Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN` reader - UART4 SLP Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN` writer - UART4 SLP Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN` reader - UART3 SLP Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN` writer - UART3 SLP Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN` reader - UART2 SLP Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN` writer - UART2 SLP Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN` reader - UART1 SLP Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN` writer - UART1 SLP Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN` reader - UART0 SLP Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN` writer - UART0 SLP Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN` reader - I2S2 MCLK Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN` writer - I2S2 MCLK Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN` reader - I2S1 MCLK Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN` writer - I2S1 MCLK Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN` reader - I2S0 MCLK Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN` writer - I2S0 MCLK Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN` reader - EMAC RX Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN` writer - EMAC RX Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN` reader - EMAC TX Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN` writer - EMAC TX Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN` reader - EMAC TXRX Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN` writer - EMAC TXRX Clock From Pad Enable."] +pub type LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_XTAL_32K_CLK_EN` reader - XTAL 32K Clock Enable."] +pub type LP_AONCLKRST_HP_XTAL_32K_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_XTAL_32K_CLK_EN` writer - XTAL 32K Clock Enable."] +pub type LP_AONCLKRST_HP_XTAL_32K_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_RC_32K_CLK_EN` reader - RC 32K Clock Enable."] +pub type LP_AONCLKRST_HP_RC_32K_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_RC_32K_CLK_EN` writer - RC 32K Clock Enable."] +pub type LP_AONCLKRST_HP_RC_32K_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_SOSC_150K_CLK_EN` reader - SOSC 150K Clock Enable."] +pub type LP_AONCLKRST_HP_SOSC_150K_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_SOSC_150K_CLK_EN` writer - SOSC 150K Clock Enable."] +pub type LP_AONCLKRST_HP_SOSC_150K_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_PLL_8M_CLK_EN` reader - PLL 8M Clock Enable."] +pub type LP_AONCLKRST_HP_PLL_8M_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_PLL_8M_CLK_EN` writer - PLL 8M Clock Enable."] +pub type LP_AONCLKRST_HP_PLL_8M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN` reader - AUDIO PLL Clock Enable."] +pub type LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN` writer - AUDIO PLL Clock Enable."] +pub type LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN` reader - SDIO PLL2 Clock Enable."] +pub type LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN` writer - SDIO PLL2 Clock Enable."] +pub type LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN` reader - SDIO PLL1 Clock Enable."] +pub type LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN` writer - SDIO PLL1 Clock Enable."] +pub type LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN` reader - SDIO PLL0 Clock Enable."] +pub type LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN` writer - SDIO PLL0 Clock Enable."] +pub type LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_FOSC_20M_CLK_EN` reader - FOSC 20M Clock Enable."] +pub type LP_AONCLKRST_HP_FOSC_20M_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_FOSC_20M_CLK_EN` writer - FOSC 20M Clock Enable."] +pub type LP_AONCLKRST_HP_FOSC_20M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_XTAL_40M_CLK_EN` reader - XTAL 40M Clock Enalbe."] +pub type LP_AONCLKRST_HP_XTAL_40M_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_XTAL_40M_CLK_EN` writer - XTAL 40M Clock Enalbe."] +pub type LP_AONCLKRST_HP_XTAL_40M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_CPLL_400M_CLK_EN` reader - CPLL 400M Clock Enable."] +pub type LP_AONCLKRST_HP_CPLL_400M_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_CPLL_400M_CLK_EN` writer - CPLL 400M Clock Enable."] +pub type LP_AONCLKRST_HP_CPLL_400M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_SPLL_480M_CLK_EN` reader - SPLL 480M Clock Enable."] +pub type LP_AONCLKRST_HP_SPLL_480M_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_SPLL_480M_CLK_EN` writer - SPLL 480M Clock Enable."] +pub type LP_AONCLKRST_HP_SPLL_480M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HP_MPLL_500M_CLK_EN` reader - MPLL 500M Clock Enable."] +pub type LP_AONCLKRST_HP_MPLL_500M_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HP_MPLL_500M_CLK_EN` writer - MPLL 500M Clock Enable."] +pub type LP_AONCLKRST_HP_MPLL_500M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m."] + #[inline(always)] + pub fn lp_aonclkrst_hp_root_clk_src_sel(&self) -> LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_R { + LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - HP SoC Root Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_root_clk_en(&self) -> LP_AONCLKRST_HP_ROOT_CLK_EN_R { + LP_AONCLKRST_HP_ROOT_CLK_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - PARLIO TX Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_parlio_tx_clk_en(&self) -> LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_R { + LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PARLIO RX Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_parlio_rx_clk_en(&self) -> LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_R { + LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - UART4 SLP Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_uart4_slp_clk_en(&self) -> LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_R { + LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - UART3 SLP Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_uart3_slp_clk_en(&self) -> LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_R { + LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - UART2 SLP Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_uart2_slp_clk_en(&self) -> LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_R { + LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - UART1 SLP Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_uart1_slp_clk_en(&self) -> LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_R { + LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - UART0 SLP Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_uart0_slp_clk_en(&self) -> LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_R { + LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - I2S2 MCLK Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_i2s2_mclk_en(&self) -> LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_R { + LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - I2S1 MCLK Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_i2s1_mclk_en(&self) -> LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_R { + LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - I2S0 MCLK Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_i2s0_mclk_en(&self) -> LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_R { + LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - EMAC RX Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_emac_tx_clk_en(&self) -> LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_R { + LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - EMAC TX Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_emac_rx_clk_en(&self) -> LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_R { + LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - EMAC TXRX Clock From Pad Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pad_emac_txrx_clk_en(&self) -> LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_R { + LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - XTAL 32K Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_xtal_32k_clk_en(&self) -> LP_AONCLKRST_HP_XTAL_32K_CLK_EN_R { + LP_AONCLKRST_HP_XTAL_32K_CLK_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - RC 32K Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_rc_32k_clk_en(&self) -> LP_AONCLKRST_HP_RC_32K_CLK_EN_R { + LP_AONCLKRST_HP_RC_32K_CLK_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - SOSC 150K Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_sosc_150k_clk_en(&self) -> LP_AONCLKRST_HP_SOSC_150K_CLK_EN_R { + LP_AONCLKRST_HP_SOSC_150K_CLK_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - PLL 8M Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_pll_8m_clk_en(&self) -> LP_AONCLKRST_HP_PLL_8M_CLK_EN_R { + LP_AONCLKRST_HP_PLL_8M_CLK_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - AUDIO PLL Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_audio_pll_clk_en(&self) -> LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_R { + LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - SDIO PLL2 Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_sdio_pll2_clk_en(&self) -> LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_R { + LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - SDIO PLL1 Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_sdio_pll1_clk_en(&self) -> LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_R { + LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - SDIO PLL0 Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_sdio_pll0_clk_en(&self) -> LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_R { + LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - FOSC 20M Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_fosc_20m_clk_en(&self) -> LP_AONCLKRST_HP_FOSC_20M_CLK_EN_R { + LP_AONCLKRST_HP_FOSC_20M_CLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - XTAL 40M Clock Enalbe."] + #[inline(always)] + pub fn lp_aonclkrst_hp_xtal_40m_clk_en(&self) -> LP_AONCLKRST_HP_XTAL_40M_CLK_EN_R { + LP_AONCLKRST_HP_XTAL_40M_CLK_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - CPLL 400M Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_cpll_400m_clk_en(&self) -> LP_AONCLKRST_HP_CPLL_400M_CLK_EN_R { + LP_AONCLKRST_HP_CPLL_400M_CLK_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - SPLL 480M Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_spll_480m_clk_en(&self) -> LP_AONCLKRST_HP_SPLL_480M_CLK_EN_R { + LP_AONCLKRST_HP_SPLL_480M_CLK_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - MPLL 500M Clock Enable."] + #[inline(always)] + pub fn lp_aonclkrst_hp_mpll_500m_clk_en(&self) -> LP_AONCLKRST_HP_MPLL_500M_CLK_EN_R { + LP_AONCLKRST_HP_MPLL_500M_CLK_EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_HP_CLK_CTRL") + .field( + "lp_aonclkrst_hp_root_clk_src_sel", + &format_args!("{}", self.lp_aonclkrst_hp_root_clk_src_sel().bits()), + ) + .field( + "lp_aonclkrst_hp_root_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_root_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_parlio_tx_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_parlio_tx_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_parlio_rx_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_parlio_rx_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_uart4_slp_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_uart4_slp_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_uart3_slp_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_uart3_slp_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_uart2_slp_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_uart2_slp_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_uart1_slp_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_uart1_slp_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_uart0_slp_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_uart0_slp_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_i2s2_mclk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_i2s2_mclk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_i2s1_mclk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_i2s1_mclk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_i2s0_mclk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_i2s0_mclk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_emac_tx_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_emac_tx_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_emac_rx_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_emac_rx_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pad_emac_txrx_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pad_emac_txrx_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_xtal_32k_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_xtal_32k_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_rc_32k_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_rc_32k_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_sosc_150k_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_sosc_150k_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_pll_8m_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_pll_8m_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_audio_pll_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_audio_pll_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_sdio_pll2_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_sdio_pll2_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_sdio_pll1_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_sdio_pll1_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_sdio_pll0_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_sdio_pll0_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_fosc_20m_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_fosc_20m_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_xtal_40m_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_xtal_40m_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_cpll_400m_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_cpll_400m_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_spll_480m_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_spll_480m_clk_en().bit()), + ) + .field( + "lp_aonclkrst_hp_mpll_500m_clk_en", + &format_args!("{}", self.lp_aonclkrst_hp_mpll_500m_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_root_clk_src_sel( + &mut self, + ) -> LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_W { + LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL_W::new(self, 0) + } + #[doc = "Bit 2 - HP SoC Root Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_root_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_ROOT_CLK_EN_W { + LP_AONCLKRST_HP_ROOT_CLK_EN_W::new(self, 2) + } + #[doc = "Bit 3 - PARLIO TX Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_parlio_tx_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_W { + LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN_W::new(self, 3) + } + #[doc = "Bit 4 - PARLIO RX Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_parlio_rx_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_W { + LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN_W::new(self, 4) + } + #[doc = "Bit 5 - UART4 SLP Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_uart4_slp_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_W { + LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN_W::new(self, 5) + } + #[doc = "Bit 6 - UART3 SLP Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_uart3_slp_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_W { + LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN_W::new(self, 6) + } + #[doc = "Bit 7 - UART2 SLP Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_uart2_slp_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_W { + LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN_W::new(self, 7) + } + #[doc = "Bit 8 - UART1 SLP Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_uart1_slp_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_W { + LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN_W::new(self, 8) + } + #[doc = "Bit 9 - UART0 SLP Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_uart0_slp_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_W { + LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN_W::new(self, 9) + } + #[doc = "Bit 10 - I2S2 MCLK Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_i2s2_mclk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_W { + LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN_W::new(self, 10) + } + #[doc = "Bit 11 - I2S1 MCLK Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_i2s1_mclk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_W { + LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN_W::new(self, 11) + } + #[doc = "Bit 12 - I2S0 MCLK Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_i2s0_mclk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_W { + LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN_W::new(self, 12) + } + #[doc = "Bit 13 - EMAC RX Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_emac_tx_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_W { + LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN_W::new(self, 13) + } + #[doc = "Bit 14 - EMAC TX Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_emac_rx_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_W { + LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN_W::new(self, 14) + } + #[doc = "Bit 15 - EMAC TXRX Clock From Pad Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pad_emac_txrx_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_W { + LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN_W::new(self, 15) + } + #[doc = "Bit 16 - XTAL 32K Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_xtal_32k_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_XTAL_32K_CLK_EN_W { + LP_AONCLKRST_HP_XTAL_32K_CLK_EN_W::new(self, 16) + } + #[doc = "Bit 17 - RC 32K Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_rc_32k_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_RC_32K_CLK_EN_W { + LP_AONCLKRST_HP_RC_32K_CLK_EN_W::new(self, 17) + } + #[doc = "Bit 18 - SOSC 150K Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_sosc_150k_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_SOSC_150K_CLK_EN_W { + LP_AONCLKRST_HP_SOSC_150K_CLK_EN_W::new(self, 18) + } + #[doc = "Bit 19 - PLL 8M Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_pll_8m_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_PLL_8M_CLK_EN_W { + LP_AONCLKRST_HP_PLL_8M_CLK_EN_W::new(self, 19) + } + #[doc = "Bit 20 - AUDIO PLL Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_audio_pll_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_W { + LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN_W::new(self, 20) + } + #[doc = "Bit 21 - SDIO PLL2 Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_sdio_pll2_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_W { + LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN_W::new(self, 21) + } + #[doc = "Bit 22 - SDIO PLL1 Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_sdio_pll1_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_W { + LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN_W::new(self, 22) + } + #[doc = "Bit 23 - SDIO PLL0 Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_sdio_pll0_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_W { + LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN_W::new(self, 23) + } + #[doc = "Bit 24 - FOSC 20M Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_fosc_20m_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_FOSC_20M_CLK_EN_W { + LP_AONCLKRST_HP_FOSC_20M_CLK_EN_W::new(self, 24) + } + #[doc = "Bit 25 - XTAL 40M Clock Enalbe."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_xtal_40m_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_XTAL_40M_CLK_EN_W { + LP_AONCLKRST_HP_XTAL_40M_CLK_EN_W::new(self, 25) + } + #[doc = "Bit 26 - CPLL 400M Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_cpll_400m_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_CPLL_400M_CLK_EN_W { + LP_AONCLKRST_HP_CPLL_400M_CLK_EN_W::new(self, 26) + } + #[doc = "Bit 27 - SPLL 480M Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_spll_480m_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_SPLL_480M_CLK_EN_W { + LP_AONCLKRST_HP_SPLL_480M_CLK_EN_W::new(self, 27) + } + #[doc = "Bit 28 - MPLL 500M Clock Enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hp_mpll_500m_clk_en( + &mut self, + ) -> LP_AONCLKRST_HP_MPLL_500M_CLK_EN_W { + LP_AONCLKRST_HP_MPLL_500M_CLK_EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "HP Clock Control Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hp_clk_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hp_clk_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_HP_CLK_CTRL_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_HP_CLK_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_hp_clk_ctrl::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_HP_CLK_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_hp_clk_ctrl::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_HP_CLK_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_HP_CLK_CTRL to value 0x1fff_fffc"] +impl crate::Resettable for LP_AONCLKRST_HP_CLK_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x1fff_fffc; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_sdmmc_emac_rst_ctrl.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_sdmmc_emac_rst_ctrl.rs new file mode 100644 index 0000000000..c26c88794c --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_sdmmc_emac_rst_ctrl.rs @@ -0,0 +1,131 @@ +#[doc = "Register `LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_RST_EN_SDMMC` reader - hp sdmmc reset en"] +pub type LP_AONCLKRST_RST_EN_SDMMC_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_SDMMC` writer - hp sdmmc reset en"] +pub type LP_AONCLKRST_RST_EN_SDMMC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_FORCE_NORST_SDMMC` reader - hp sdmmc force norst"] +pub type LP_AONCLKRST_FORCE_NORST_SDMMC_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_FORCE_NORST_SDMMC` writer - hp sdmmc force norst"] +pub type LP_AONCLKRST_FORCE_NORST_SDMMC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_EMAC` reader - hp emac reset en"] +pub type LP_AONCLKRST_RST_EN_EMAC_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_EMAC` writer - hp emac reset en"] +pub type LP_AONCLKRST_RST_EN_EMAC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_FORCE_NORST_EMAC` reader - hp emac force norst"] +pub type LP_AONCLKRST_FORCE_NORST_EMAC_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_FORCE_NORST_EMAC` writer - hp emac force norst"] +pub type LP_AONCLKRST_FORCE_NORST_EMAC_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 28 - hp sdmmc reset en"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_sdmmc(&self) -> LP_AONCLKRST_RST_EN_SDMMC_R { + LP_AONCLKRST_RST_EN_SDMMC_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - hp sdmmc force norst"] + #[inline(always)] + pub fn lp_aonclkrst_force_norst_sdmmc(&self) -> LP_AONCLKRST_FORCE_NORST_SDMMC_R { + LP_AONCLKRST_FORCE_NORST_SDMMC_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - hp emac reset en"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_emac(&self) -> LP_AONCLKRST_RST_EN_EMAC_R { + LP_AONCLKRST_RST_EN_EMAC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - hp emac force norst"] + #[inline(always)] + pub fn lp_aonclkrst_force_norst_emac(&self) -> LP_AONCLKRST_FORCE_NORST_EMAC_R { + LP_AONCLKRST_FORCE_NORST_EMAC_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL") + .field( + "lp_aonclkrst_rst_en_sdmmc", + &format_args!("{}", self.lp_aonclkrst_rst_en_sdmmc().bit()), + ) + .field( + "lp_aonclkrst_force_norst_sdmmc", + &format_args!("{}", self.lp_aonclkrst_force_norst_sdmmc().bit()), + ) + .field( + "lp_aonclkrst_rst_en_emac", + &format_args!("{}", self.lp_aonclkrst_rst_en_emac().bit()), + ) + .field( + "lp_aonclkrst_force_norst_emac", + &format_args!("{}", self.lp_aonclkrst_force_norst_emac().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 28 - hp sdmmc reset en"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_sdmmc( + &mut self, + ) -> LP_AONCLKRST_RST_EN_SDMMC_W { + LP_AONCLKRST_RST_EN_SDMMC_W::new(self, 28) + } + #[doc = "Bit 29 - hp sdmmc force norst"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_force_norst_sdmmc( + &mut self, + ) -> LP_AONCLKRST_FORCE_NORST_SDMMC_W { + LP_AONCLKRST_FORCE_NORST_SDMMC_W::new(self, 29) + } + #[doc = "Bit 30 - hp emac reset en"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_emac( + &mut self, + ) -> LP_AONCLKRST_RST_EN_EMAC_W { + LP_AONCLKRST_RST_EN_EMAC_W::new(self, 30) + } + #[doc = "Bit 31 - hp emac force norst"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_force_norst_emac( + &mut self, + ) -> LP_AONCLKRST_FORCE_NORST_EMAC_W { + LP_AONCLKRST_FORCE_NORST_EMAC_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hp_sdmmc_emac_rst_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hp_sdmmc_emac_rst_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_hp_sdmmc_emac_rst_ctrl::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_hp_sdmmc_emac_rst_ctrl::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL to value 0"] +impl crate::Resettable for LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl0.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl0.rs new file mode 100644 index 0000000000..1a7f0a4def --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl0.rs @@ -0,0 +1,236 @@ +#[doc = "Register `LP_AONCLKRST_HP_USB_CLKRST_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_HP_USB_CLKRST_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_USB_OTG20_SLEEP_MODE` reader - unused."] +pub type LP_AONCLKRST_USB_OTG20_SLEEP_MODE_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_USB_OTG20_SLEEP_MODE` writer - unused."] +pub type LP_AONCLKRST_USB_OTG20_SLEEP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN` reader - unused."] +pub type LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN` writer - unused."] +pub type LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_USB_OTG11_SLEEP_MODE` reader - unused."] +pub type LP_AONCLKRST_USB_OTG11_SLEEP_MODE_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_USB_OTG11_SLEEP_MODE` writer - unused."] +pub type LP_AONCLKRST_USB_OTG11_SLEEP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN` reader - unused."] +pub type LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN` writer - unused."] +pub type LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_USB_OTG11_48M_CLK_EN` reader - usb otg11 fs phy clock enable."] +pub type LP_AONCLKRST_USB_OTG11_48M_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_USB_OTG11_48M_CLK_EN` writer - usb otg11 fs phy clock enable."] +pub type LP_AONCLKRST_USB_OTG11_48M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_USB_DEVICE_48M_CLK_EN` reader - usb device fs phy clock enable."] +pub type LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_USB_DEVICE_48M_CLK_EN` writer - usb device fs phy clock enable."] +pub type LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_USB_48M_DIV_NUM` reader - usb 480m to 25m divide number."] +pub type LP_AONCLKRST_USB_48M_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_USB_48M_DIV_NUM` writer - usb 480m to 25m divide number."] +pub type LP_AONCLKRST_USB_48M_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LP_AONCLKRST_USB_25M_DIV_NUM` reader - usb 500m to 25m divide number."] +pub type LP_AONCLKRST_USB_25M_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_USB_25M_DIV_NUM` writer - usb 500m to 25m divide number."] +pub type LP_AONCLKRST_USB_25M_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LP_AONCLKRST_USB_12M_DIV_NUM` reader - usb 480m to 12m divide number."] +pub type LP_AONCLKRST_USB_12M_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_USB_12M_DIV_NUM` writer - usb 480m to 12m divide number."] +pub type LP_AONCLKRST_USB_12M_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 0 - unused."] + #[inline(always)] + pub fn lp_aonclkrst_usb_otg20_sleep_mode(&self) -> LP_AONCLKRST_USB_OTG20_SLEEP_MODE_R { + LP_AONCLKRST_USB_OTG20_SLEEP_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - unused."] + #[inline(always)] + pub fn lp_aonclkrst_usb_otg20_bk_sys_clk_en(&self) -> LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_R { + LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - unused."] + #[inline(always)] + pub fn lp_aonclkrst_usb_otg11_sleep_mode(&self) -> LP_AONCLKRST_USB_OTG11_SLEEP_MODE_R { + LP_AONCLKRST_USB_OTG11_SLEEP_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - unused."] + #[inline(always)] + pub fn lp_aonclkrst_usb_otg11_bk_sys_clk_en(&self) -> LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_R { + LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - usb otg11 fs phy clock enable."] + #[inline(always)] + pub fn lp_aonclkrst_usb_otg11_48m_clk_en(&self) -> LP_AONCLKRST_USB_OTG11_48M_CLK_EN_R { + LP_AONCLKRST_USB_OTG11_48M_CLK_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - usb device fs phy clock enable."] + #[inline(always)] + pub fn lp_aonclkrst_usb_device_48m_clk_en(&self) -> LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_R { + LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:13 - usb 480m to 25m divide number."] + #[inline(always)] + pub fn lp_aonclkrst_usb_48m_div_num(&self) -> LP_AONCLKRST_USB_48M_DIV_NUM_R { + LP_AONCLKRST_USB_48M_DIV_NUM_R::new(((self.bits >> 6) & 0xff) as u8) + } + #[doc = "Bits 14:21 - usb 500m to 25m divide number."] + #[inline(always)] + pub fn lp_aonclkrst_usb_25m_div_num(&self) -> LP_AONCLKRST_USB_25M_DIV_NUM_R { + LP_AONCLKRST_USB_25M_DIV_NUM_R::new(((self.bits >> 14) & 0xff) as u8) + } + #[doc = "Bits 22:29 - usb 480m to 12m divide number."] + #[inline(always)] + pub fn lp_aonclkrst_usb_12m_div_num(&self) -> LP_AONCLKRST_USB_12M_DIV_NUM_R { + LP_AONCLKRST_USB_12M_DIV_NUM_R::new(((self.bits >> 22) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_HP_USB_CLKRST_CTRL0") + .field( + "lp_aonclkrst_usb_otg20_sleep_mode", + &format_args!("{}", self.lp_aonclkrst_usb_otg20_sleep_mode().bit()), + ) + .field( + "lp_aonclkrst_usb_otg20_bk_sys_clk_en", + &format_args!("{}", self.lp_aonclkrst_usb_otg20_bk_sys_clk_en().bit()), + ) + .field( + "lp_aonclkrst_usb_otg11_sleep_mode", + &format_args!("{}", self.lp_aonclkrst_usb_otg11_sleep_mode().bit()), + ) + .field( + "lp_aonclkrst_usb_otg11_bk_sys_clk_en", + &format_args!("{}", self.lp_aonclkrst_usb_otg11_bk_sys_clk_en().bit()), + ) + .field( + "lp_aonclkrst_usb_otg11_48m_clk_en", + &format_args!("{}", self.lp_aonclkrst_usb_otg11_48m_clk_en().bit()), + ) + .field( + "lp_aonclkrst_usb_device_48m_clk_en", + &format_args!("{}", self.lp_aonclkrst_usb_device_48m_clk_en().bit()), + ) + .field( + "lp_aonclkrst_usb_48m_div_num", + &format_args!("{}", self.lp_aonclkrst_usb_48m_div_num().bits()), + ) + .field( + "lp_aonclkrst_usb_25m_div_num", + &format_args!("{}", self.lp_aonclkrst_usb_25m_div_num().bits()), + ) + .field( + "lp_aonclkrst_usb_12m_div_num", + &format_args!("{}", self.lp_aonclkrst_usb_12m_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - unused."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_otg20_sleep_mode( + &mut self, + ) -> LP_AONCLKRST_USB_OTG20_SLEEP_MODE_W { + LP_AONCLKRST_USB_OTG20_SLEEP_MODE_W::new(self, 0) + } + #[doc = "Bit 1 - unused."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_otg20_bk_sys_clk_en( + &mut self, + ) -> LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_W { + LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN_W::new(self, 1) + } + #[doc = "Bit 2 - unused."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_otg11_sleep_mode( + &mut self, + ) -> LP_AONCLKRST_USB_OTG11_SLEEP_MODE_W { + LP_AONCLKRST_USB_OTG11_SLEEP_MODE_W::new(self, 2) + } + #[doc = "Bit 3 - unused."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_otg11_bk_sys_clk_en( + &mut self, + ) -> LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_W { + LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN_W::new(self, 3) + } + #[doc = "Bit 4 - usb otg11 fs phy clock enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_otg11_48m_clk_en( + &mut self, + ) -> LP_AONCLKRST_USB_OTG11_48M_CLK_EN_W { + LP_AONCLKRST_USB_OTG11_48M_CLK_EN_W::new(self, 4) + } + #[doc = "Bit 5 - usb device fs phy clock enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_device_48m_clk_en( + &mut self, + ) -> LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_W { + LP_AONCLKRST_USB_DEVICE_48M_CLK_EN_W::new(self, 5) + } + #[doc = "Bits 6:13 - usb 480m to 25m divide number."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_48m_div_num( + &mut self, + ) -> LP_AONCLKRST_USB_48M_DIV_NUM_W { + LP_AONCLKRST_USB_48M_DIV_NUM_W::new(self, 6) + } + #[doc = "Bits 14:21 - usb 500m to 25m divide number."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_25m_div_num( + &mut self, + ) -> LP_AONCLKRST_USB_25M_DIV_NUM_W { + LP_AONCLKRST_USB_25M_DIV_NUM_W::new(self, 14) + } + #[doc = "Bits 22:29 - usb 480m to 12m divide number."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_12m_div_num( + &mut self, + ) -> LP_AONCLKRST_USB_12M_DIV_NUM_W { + LP_AONCLKRST_USB_12M_DIV_NUM_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "HP USB Clock Reset Control Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hp_usb_clkrst_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hp_usb_clkrst_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_HP_USB_CLKRST_CTRL0_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_HP_USB_CLKRST_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_hp_usb_clkrst_ctrl0::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_HP_USB_CLKRST_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_hp_usb_clkrst_ctrl0::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_HP_USB_CLKRST_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_HP_USB_CLKRST_CTRL0 to value 0x09c4_c27a"] +impl crate::Resettable for LP_AONCLKRST_HP_USB_CLKRST_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0x09c4_c27a; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl1.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl1.rs new file mode 100644 index 0000000000..2a48f78dbb --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl1.rs @@ -0,0 +1,220 @@ +#[doc = "Register `LP_AONCLKRST_HP_USB_CLKRST_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_HP_USB_CLKRST_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_RST_EN_USB_OTG20_ADP` reader - usb otg20 adp reset en"] +pub type LP_AONCLKRST_RST_EN_USB_OTG20_ADP_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_USB_OTG20_ADP` writer - usb otg20 adp reset en"] +pub type LP_AONCLKRST_RST_EN_USB_OTG20_ADP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_USB_OTG20_PHY` reader - usb otg20 phy reset en"] +pub type LP_AONCLKRST_RST_EN_USB_OTG20_PHY_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_USB_OTG20_PHY` writer - usb otg20 phy reset en"] +pub type LP_AONCLKRST_RST_EN_USB_OTG20_PHY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_USB_OTG20` reader - usb otg20 reset en"] +pub type LP_AONCLKRST_RST_EN_USB_OTG20_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_USB_OTG20` writer - usb otg20 reset en"] +pub type LP_AONCLKRST_RST_EN_USB_OTG20_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_USB_OTG11` reader - usb org11 reset en"] +pub type LP_AONCLKRST_RST_EN_USB_OTG11_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_USB_OTG11` writer - usb org11 reset en"] +pub type LP_AONCLKRST_RST_EN_USB_OTG11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_USB_DEVICE` reader - usb device reset en"] +pub type LP_AONCLKRST_RST_EN_USB_DEVICE_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_USB_DEVICE` writer - usb device reset en"] +pub type LP_AONCLKRST_RST_EN_USB_DEVICE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL` reader - usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk."] +pub type LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL` writer - usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk."] +pub type LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN` reader - usb otg20 hs phy refclk enable."] +pub type LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN` writer - usb otg20 hs phy refclk enable."] +pub type LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN` reader - usb otg20 ulpi clock enable."] +pub type LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN` writer - usb otg20 ulpi clock enable."] +pub type LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - usb otg20 adp reset en"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_usb_otg20_adp(&self) -> LP_AONCLKRST_RST_EN_USB_OTG20_ADP_R { + LP_AONCLKRST_RST_EN_USB_OTG20_ADP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - usb otg20 phy reset en"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_usb_otg20_phy(&self) -> LP_AONCLKRST_RST_EN_USB_OTG20_PHY_R { + LP_AONCLKRST_RST_EN_USB_OTG20_PHY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - usb otg20 reset en"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_usb_otg20(&self) -> LP_AONCLKRST_RST_EN_USB_OTG20_R { + LP_AONCLKRST_RST_EN_USB_OTG20_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - usb org11 reset en"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_usb_otg11(&self) -> LP_AONCLKRST_RST_EN_USB_OTG11_R { + LP_AONCLKRST_RST_EN_USB_OTG11_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - usb device reset en"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_usb_device(&self) -> LP_AONCLKRST_RST_EN_USB_DEVICE_R { + LP_AONCLKRST_RST_EN_USB_DEVICE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 28:29 - usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk."] + #[inline(always)] + pub fn lp_aonclkrst_usb_otg20_phyref_clk_src_sel( + &self, + ) -> LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_R { + LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bit 30 - usb otg20 hs phy refclk enable."] + #[inline(always)] + pub fn lp_aonclkrst_usb_otg20_phyref_clk_en(&self) -> LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_R { + LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - usb otg20 ulpi clock enable."] + #[inline(always)] + pub fn lp_aonclkrst_usb_otg20_ulpi_clk_en(&self) -> LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_R { + LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_HP_USB_CLKRST_CTRL1") + .field( + "lp_aonclkrst_rst_en_usb_otg20_adp", + &format_args!("{}", self.lp_aonclkrst_rst_en_usb_otg20_adp().bit()), + ) + .field( + "lp_aonclkrst_rst_en_usb_otg20_phy", + &format_args!("{}", self.lp_aonclkrst_rst_en_usb_otg20_phy().bit()), + ) + .field( + "lp_aonclkrst_rst_en_usb_otg20", + &format_args!("{}", self.lp_aonclkrst_rst_en_usb_otg20().bit()), + ) + .field( + "lp_aonclkrst_rst_en_usb_otg11", + &format_args!("{}", self.lp_aonclkrst_rst_en_usb_otg11().bit()), + ) + .field( + "lp_aonclkrst_rst_en_usb_device", + &format_args!("{}", self.lp_aonclkrst_rst_en_usb_device().bit()), + ) + .field( + "lp_aonclkrst_usb_otg20_phyref_clk_src_sel", + &format_args!( + "{}", + self.lp_aonclkrst_usb_otg20_phyref_clk_src_sel().bits() + ), + ) + .field( + "lp_aonclkrst_usb_otg20_phyref_clk_en", + &format_args!("{}", self.lp_aonclkrst_usb_otg20_phyref_clk_en().bit()), + ) + .field( + "lp_aonclkrst_usb_otg20_ulpi_clk_en", + &format_args!("{}", self.lp_aonclkrst_usb_otg20_ulpi_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - usb otg20 adp reset en"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_usb_otg20_adp( + &mut self, + ) -> LP_AONCLKRST_RST_EN_USB_OTG20_ADP_W { + LP_AONCLKRST_RST_EN_USB_OTG20_ADP_W::new(self, 0) + } + #[doc = "Bit 1 - usb otg20 phy reset en"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_usb_otg20_phy( + &mut self, + ) -> LP_AONCLKRST_RST_EN_USB_OTG20_PHY_W { + LP_AONCLKRST_RST_EN_USB_OTG20_PHY_W::new(self, 1) + } + #[doc = "Bit 2 - usb otg20 reset en"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_usb_otg20( + &mut self, + ) -> LP_AONCLKRST_RST_EN_USB_OTG20_W { + LP_AONCLKRST_RST_EN_USB_OTG20_W::new(self, 2) + } + #[doc = "Bit 3 - usb org11 reset en"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_usb_otg11( + &mut self, + ) -> LP_AONCLKRST_RST_EN_USB_OTG11_W { + LP_AONCLKRST_RST_EN_USB_OTG11_W::new(self, 3) + } + #[doc = "Bit 4 - usb device reset en"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_usb_device( + &mut self, + ) -> LP_AONCLKRST_RST_EN_USB_DEVICE_W { + LP_AONCLKRST_RST_EN_USB_DEVICE_W::new(self, 4) + } + #[doc = "Bits 28:29 - usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_otg20_phyref_clk_src_sel( + &mut self, + ) -> LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_W { + LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_W::new(self, 28) + } + #[doc = "Bit 30 - usb otg20 hs phy refclk enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_otg20_phyref_clk_en( + &mut self, + ) -> LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_W { + LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN_W::new(self, 30) + } + #[doc = "Bit 31 - usb otg20 ulpi clock enable."] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_usb_otg20_ulpi_clk_en( + &mut self, + ) -> LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_W { + LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "HP USB Clock Reset Control Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hp_usb_clkrst_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hp_usb_clkrst_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_HP_USB_CLKRST_CTRL1_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_HP_USB_CLKRST_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_hp_usb_clkrst_ctrl1::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_HP_USB_CLKRST_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_hp_usb_clkrst_ctrl1::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_HP_USB_CLKRST_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_HP_USB_CLKRST_CTRL1 to value 0xc000_0000"] +impl crate::Resettable for LP_AONCLKRST_HP_USB_CLKRST_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0xc000_0000; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl0.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl0.rs new file mode 100644 index 0000000000..9dfe43e832 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl0.rs @@ -0,0 +1,369 @@ +#[doc = "Register `LP_AONCLKRST_HPCPU_RESET_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_HPCPU_RESET_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN` reader - write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature"] +pub type LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN` writer - write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature"] +pub type LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH` reader - need_des"] +pub type LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH` writer - need_des"] +pub type LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN` reader - write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature"] +pub type LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN` writer - write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature"] +pub type LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE0_STALL_WAIT` reader - need_des"] +pub type LP_AONCLKRST_HPCORE0_STALL_WAIT_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_HPCORE0_STALL_WAIT` writer - need_des"] +pub type LP_AONCLKRST_HPCORE0_STALL_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `LP_AONCLKRST_HPCORE0_STALL_EN` reader - need_des"] +pub type LP_AONCLKRST_HPCORE0_STALL_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HPCORE0_STALL_EN` writer - need_des"] +pub type LP_AONCLKRST_HPCORE0_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE0_SW_RESET` writer - need_des"] +pub type LP_AONCLKRST_HPCORE0_SW_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET` reader - need_des"] +pub type LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET` writer - need_des"] +pub type LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL` reader - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"] +pub type LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL` writer - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"] +pub type LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN` reader - write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature"] +pub type LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN` writer - write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature"] +pub type LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH` reader - need_des"] +pub type LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH` writer - need_des"] +pub type LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN` reader - write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature"] +pub type LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN` writer - write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature"] +pub type LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE1_STALL_WAIT` reader - need_des"] +pub type LP_AONCLKRST_HPCORE1_STALL_WAIT_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_HPCORE1_STALL_WAIT` writer - need_des"] +pub type LP_AONCLKRST_HPCORE1_STALL_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `LP_AONCLKRST_HPCORE1_STALL_EN` reader - need_des"] +pub type LP_AONCLKRST_HPCORE1_STALL_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HPCORE1_STALL_EN` writer - need_des"] +pub type LP_AONCLKRST_HPCORE1_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE1_SW_RESET` writer - need_des"] +pub type LP_AONCLKRST_HPCORE1_SW_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET` reader - need_des"] +pub type LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET` writer - need_des"] +pub type LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL` reader - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"] +pub type LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL` writer - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"] +pub type LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore0_lockup_reset_en(&self) -> LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_R { + LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_lp_wdt_hpcore0_reset_length( + &self, + ) -> LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_R { + LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature"] + #[inline(always)] + pub fn lp_aonclkrst_lp_wdt_hpcore0_reset_en(&self) -> LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_R { + LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:11 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore0_stall_wait(&self) -> LP_AONCLKRST_HPCORE0_STALL_WAIT_R { + LP_AONCLKRST_HPCORE0_STALL_WAIT_R::new(((self.bits >> 5) & 0x7f) as u8) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore0_stall_en(&self) -> LP_AONCLKRST_HPCORE0_STALL_EN_R { + LP_AONCLKRST_HPCORE0_STALL_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore0_ocd_halt_on_reset( + &self, + ) -> LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_R { + LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore0_stat_vector_sel(&self) -> LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_R { + LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore1_lockup_reset_en(&self) -> LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_R { + LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_lp_wdt_hpcore1_reset_length( + &self, + ) -> LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_R { + LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_R::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 20 - write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature"] + #[inline(always)] + pub fn lp_aonclkrst_lp_wdt_hpcore1_reset_en(&self) -> LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_R { + LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:27 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore1_stall_wait(&self) -> LP_AONCLKRST_HPCORE1_STALL_WAIT_R { + LP_AONCLKRST_HPCORE1_STALL_WAIT_R::new(((self.bits >> 21) & 0x7f) as u8) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore1_stall_en(&self) -> LP_AONCLKRST_HPCORE1_STALL_EN_R { + LP_AONCLKRST_HPCORE1_STALL_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore1_ocd_halt_on_reset( + &self, + ) -> LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_R { + LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore1_stat_vector_sel(&self) -> LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_R { + LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_HPCPU_RESET_CTRL0") + .field( + "lp_aonclkrst_hpcore0_lockup_reset_en", + &format_args!("{}", self.lp_aonclkrst_hpcore0_lockup_reset_en().bit()), + ) + .field( + "lp_aonclkrst_lp_wdt_hpcore0_reset_length", + &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore0_reset_length().bits()), + ) + .field( + "lp_aonclkrst_lp_wdt_hpcore0_reset_en", + &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore0_reset_en().bit()), + ) + .field( + "lp_aonclkrst_hpcore0_stall_wait", + &format_args!("{}", self.lp_aonclkrst_hpcore0_stall_wait().bits()), + ) + .field( + "lp_aonclkrst_hpcore0_stall_en", + &format_args!("{}", self.lp_aonclkrst_hpcore0_stall_en().bit()), + ) + .field( + "lp_aonclkrst_hpcore0_ocd_halt_on_reset", + &format_args!("{}", self.lp_aonclkrst_hpcore0_ocd_halt_on_reset().bit()), + ) + .field( + "lp_aonclkrst_hpcore0_stat_vector_sel", + &format_args!("{}", self.lp_aonclkrst_hpcore0_stat_vector_sel().bit()), + ) + .field( + "lp_aonclkrst_hpcore1_lockup_reset_en", + &format_args!("{}", self.lp_aonclkrst_hpcore1_lockup_reset_en().bit()), + ) + .field( + "lp_aonclkrst_lp_wdt_hpcore1_reset_length", + &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore1_reset_length().bits()), + ) + .field( + "lp_aonclkrst_lp_wdt_hpcore1_reset_en", + &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore1_reset_en().bit()), + ) + .field( + "lp_aonclkrst_hpcore1_stall_wait", + &format_args!("{}", self.lp_aonclkrst_hpcore1_stall_wait().bits()), + ) + .field( + "lp_aonclkrst_hpcore1_stall_en", + &format_args!("{}", self.lp_aonclkrst_hpcore1_stall_en().bit()), + ) + .field( + "lp_aonclkrst_hpcore1_ocd_halt_on_reset", + &format_args!("{}", self.lp_aonclkrst_hpcore1_ocd_halt_on_reset().bit()), + ) + .field( + "lp_aonclkrst_hpcore1_stat_vector_sel", + &format_args!("{}", self.lp_aonclkrst_hpcore1_stat_vector_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore0_lockup_reset_en( + &mut self, + ) -> LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_W { + LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_lp_wdt_hpcore0_reset_length( + &mut self, + ) -> LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_W { + LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_W::new(self, 1) + } + #[doc = "Bit 4 - write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_lp_wdt_hpcore0_reset_en( + &mut self, + ) -> LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_W { + LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_W::new(self, 4) + } + #[doc = "Bits 5:11 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore0_stall_wait( + &mut self, + ) -> LP_AONCLKRST_HPCORE0_STALL_WAIT_W { + LP_AONCLKRST_HPCORE0_STALL_WAIT_W::new(self, 5) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore0_stall_en( + &mut self, + ) -> LP_AONCLKRST_HPCORE0_STALL_EN_W { + LP_AONCLKRST_HPCORE0_STALL_EN_W::new(self, 12) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore0_sw_reset( + &mut self, + ) -> LP_AONCLKRST_HPCORE0_SW_RESET_W { + LP_AONCLKRST_HPCORE0_SW_RESET_W::new(self, 13) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore0_ocd_halt_on_reset( + &mut self, + ) -> LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_W { + LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_W::new(self, 14) + } + #[doc = "Bit 15 - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore0_stat_vector_sel( + &mut self, + ) -> LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_W { + LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_W::new(self, 15) + } + #[doc = "Bit 16 - write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore1_lockup_reset_en( + &mut self, + ) -> LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_W { + LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_W::new(self, 16) + } + #[doc = "Bits 17:19 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_lp_wdt_hpcore1_reset_length( + &mut self, + ) -> LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_W { + LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_W::new(self, 17) + } + #[doc = "Bit 20 - write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_lp_wdt_hpcore1_reset_en( + &mut self, + ) -> LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_W { + LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_W::new(self, 20) + } + #[doc = "Bits 21:27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore1_stall_wait( + &mut self, + ) -> LP_AONCLKRST_HPCORE1_STALL_WAIT_W { + LP_AONCLKRST_HPCORE1_STALL_WAIT_W::new(self, 21) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore1_stall_en( + &mut self, + ) -> LP_AONCLKRST_HPCORE1_STALL_EN_W { + LP_AONCLKRST_HPCORE1_STALL_EN_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore1_sw_reset( + &mut self, + ) -> LP_AONCLKRST_HPCORE1_SW_RESET_W { + LP_AONCLKRST_HPCORE1_SW_RESET_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore1_ocd_halt_on_reset( + &mut self, + ) -> LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_W { + LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_W::new(self, 30) + } + #[doc = "Bit 31 - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore1_stat_vector_sel( + &mut self, + ) -> LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_W { + LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hpcpu_reset_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hpcpu_reset_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_hpcpu_reset_ctrl0::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_hpcpu_reset_ctrl0::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_HPCPU_RESET_CTRL0 to value 0x8002_8002"] +impl crate::Resettable for LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0x8002_8002; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl1.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl1.rs new file mode 100644 index 0000000000..3ef3b174c7 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl1.rs @@ -0,0 +1,89 @@ +#[doc = "Register `LP_AONCLKRST_HPCPU_RESET_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_HPCPU_RESET_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_HPCORE0_SW_STALL_CODE` reader - HP core0 software stall when set to 8'h86"] +pub type LP_AONCLKRST_HPCORE0_SW_STALL_CODE_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_HPCORE0_SW_STALL_CODE` writer - HP core0 software stall when set to 8'h86"] +pub type LP_AONCLKRST_HPCORE0_SW_STALL_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LP_AONCLKRST_HPCORE1_SW_STALL_CODE` reader - HP core1 software stall when set to 8'h86"] +pub type LP_AONCLKRST_HPCORE1_SW_STALL_CODE_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_HPCORE1_SW_STALL_CODE` writer - HP core1 software stall when set to 8'h86"] +pub type LP_AONCLKRST_HPCORE1_SW_STALL_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 16:23 - HP core0 software stall when set to 8'h86"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore0_sw_stall_code(&self) -> LP_AONCLKRST_HPCORE0_SW_STALL_CODE_R { + LP_AONCLKRST_HPCORE0_SW_STALL_CODE_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - HP core1 software stall when set to 8'h86"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore1_sw_stall_code(&self) -> LP_AONCLKRST_HPCORE1_SW_STALL_CODE_R { + LP_AONCLKRST_HPCORE1_SW_STALL_CODE_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_HPCPU_RESET_CTRL1") + .field( + "lp_aonclkrst_hpcore0_sw_stall_code", + &format_args!("{}", self.lp_aonclkrst_hpcore0_sw_stall_code().bits()), + ) + .field( + "lp_aonclkrst_hpcore1_sw_stall_code", + &format_args!("{}", self.lp_aonclkrst_hpcore1_sw_stall_code().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:23 - HP core0 software stall when set to 8'h86"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore0_sw_stall_code( + &mut self, + ) -> LP_AONCLKRST_HPCORE0_SW_STALL_CODE_W { + LP_AONCLKRST_HPCORE0_SW_STALL_CODE_W::new(self, 16) + } + #[doc = "Bits 24:31 - HP core1 software stall when set to 8'h86"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore1_sw_stall_code( + &mut self, + ) -> LP_AONCLKRST_HPCORE1_SW_STALL_CODE_W { + LP_AONCLKRST_HPCORE1_SW_STALL_CODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hpcpu_reset_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hpcpu_reset_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_HPCPU_RESET_CTRL1_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_HPCPU_RESET_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_hpcpu_reset_ctrl1::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_HPCPU_RESET_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_hpcpu_reset_ctrl1::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_HPCPU_RESET_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_HPCPU_RESET_CTRL1 to value 0"] +impl crate::Resettable for LP_AONCLKRST_HPCPU_RESET_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_0_reset_bypass.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_0_reset_bypass.rs new file mode 100644 index 0000000000..1b21d9ed27 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_0_reset_bypass.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_AONCLKRST_HPSYS_0_RESET_BYPASS` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_HPSYS_0_RESET_BYPASS` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_HPSYS_0_RESET_BYPASS` reader - reserved"] +pub type LP_AONCLKRST_HPSYS_0_RESET_BYPASS_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_HPSYS_0_RESET_BYPASS` writer - reserved"] +pub type LP_AONCLKRST_HPSYS_0_RESET_BYPASS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + pub fn lp_aonclkrst_hpsys_0_reset_bypass(&self) -> LP_AONCLKRST_HPSYS_0_RESET_BYPASS_R { + LP_AONCLKRST_HPSYS_0_RESET_BYPASS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_HPSYS_0_RESET_BYPASS") + .field( + "lp_aonclkrst_hpsys_0_reset_bypass", + &format_args!("{}", self.lp_aonclkrst_hpsys_0_reset_bypass().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpsys_0_reset_bypass( + &mut self, + ) -> LP_AONCLKRST_HPSYS_0_RESET_BYPASS_W { + LP_AONCLKRST_HPSYS_0_RESET_BYPASS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hpsys_0_reset_bypass::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hpsys_0_reset_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_HPSYS_0_RESET_BYPASS_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_HPSYS_0_RESET_BYPASS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_hpsys_0_reset_bypass::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_HPSYS_0_RESET_BYPASS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_hpsys_0_reset_bypass::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_HPSYS_0_RESET_BYPASS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_HPSYS_0_RESET_BYPASS to value 0xffff_ffff"] +impl crate::Resettable for LP_AONCLKRST_HPSYS_0_RESET_BYPASS_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_apm_reset_bypass.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_apm_reset_bypass.rs new file mode 100644 index 0000000000..af6ca7b573 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_apm_reset_bypass.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_AONCLKRST_HPSYS_APM_RESET_BYPASS` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_HPSYS_APM_RESET_BYPASS` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_HPSYS_APM_RESET_BYPASS` reader - reserved"] +pub type LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_HPSYS_APM_RESET_BYPASS` writer - reserved"] +pub type LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + pub fn lp_aonclkrst_hpsys_apm_reset_bypass(&self) -> LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_R { + LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_HPSYS_APM_RESET_BYPASS") + .field( + "lp_aonclkrst_hpsys_apm_reset_bypass", + &format_args!("{}", self.lp_aonclkrst_hpsys_apm_reset_bypass().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpsys_apm_reset_bypass( + &mut self, + ) -> LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_W { + LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hpsys_apm_reset_bypass::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hpsys_apm_reset_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_hpsys_apm_reset_bypass::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_hpsys_apm_reset_bypass::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_HPSYS_APM_RESET_BYPASS to value 0xffff_ffff"] +impl crate::Resettable for LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_conf.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_conf.rs new file mode 100644 index 0000000000..00593e9ee7 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_conf.rs @@ -0,0 +1,131 @@ +#[doc = "Register `LP_AONCLKRST_LP_CLK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_LP_CLK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_SLOW_CLK_SEL` reader - need_des"] +pub type LP_AONCLKRST_SLOW_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_SLOW_CLK_SEL` writer - need_des"] +pub type LP_AONCLKRST_SLOW_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_AONCLKRST_FAST_CLK_SEL` reader - need_des"] +pub type LP_AONCLKRST_FAST_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_FAST_CLK_SEL` writer - need_des"] +pub type LP_AONCLKRST_FAST_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_AONCLKRST_LP_PERI_DIV_NUM` reader - need_des"] +pub type LP_AONCLKRST_LP_PERI_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_LP_PERI_DIV_NUM` writer - need_des"] +pub type LP_AONCLKRST_LP_PERI_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `LP_AONCLKRST_ANA_SEL_REF_PLL8M` reader - need_des"] +pub type LP_AONCLKRST_ANA_SEL_REF_PLL8M_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_ANA_SEL_REF_PLL8M` writer - need_des"] +pub type LP_AONCLKRST_ANA_SEL_REF_PLL8M_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_slow_clk_sel(&self) -> LP_AONCLKRST_SLOW_CLK_SEL_R { + LP_AONCLKRST_SLOW_CLK_SEL_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_fast_clk_sel(&self) -> LP_AONCLKRST_FAST_CLK_SEL_R { + LP_AONCLKRST_FAST_CLK_SEL_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:9 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_lp_peri_div_num(&self) -> LP_AONCLKRST_LP_PERI_DIV_NUM_R { + LP_AONCLKRST_LP_PERI_DIV_NUM_R::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_ana_sel_ref_pll8m(&self) -> LP_AONCLKRST_ANA_SEL_REF_PLL8M_R { + LP_AONCLKRST_ANA_SEL_REF_PLL8M_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_LP_CLK_CONF") + .field( + "lp_aonclkrst_slow_clk_sel", + &format_args!("{}", self.lp_aonclkrst_slow_clk_sel().bits()), + ) + .field( + "lp_aonclkrst_fast_clk_sel", + &format_args!("{}", self.lp_aonclkrst_fast_clk_sel().bits()), + ) + .field( + "lp_aonclkrst_lp_peri_div_num", + &format_args!("{}", self.lp_aonclkrst_lp_peri_div_num().bits()), + ) + .field( + "lp_aonclkrst_ana_sel_ref_pll8m", + &format_args!("{}", self.lp_aonclkrst_ana_sel_ref_pll8m().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_slow_clk_sel( + &mut self, + ) -> LP_AONCLKRST_SLOW_CLK_SEL_W { + LP_AONCLKRST_SLOW_CLK_SEL_W::new(self, 0) + } + #[doc = "Bits 2:3 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_fast_clk_sel( + &mut self, + ) -> LP_AONCLKRST_FAST_CLK_SEL_W { + LP_AONCLKRST_FAST_CLK_SEL_W::new(self, 2) + } + #[doc = "Bits 4:9 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_lp_peri_div_num( + &mut self, + ) -> LP_AONCLKRST_LP_PERI_DIV_NUM_W { + LP_AONCLKRST_LP_PERI_DIV_NUM_W::new(self, 4) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_ana_sel_ref_pll8m( + &mut self, + ) -> LP_AONCLKRST_ANA_SEL_REF_PLL8M_W { + LP_AONCLKRST_ANA_SEL_REF_PLL8M_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_lp_clk_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_lp_clk_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_LP_CLK_CONF_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_LP_CLK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_lp_clk_conf::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_LP_CLK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_lp_clk_conf::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_LP_CLK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_LP_CLK_CONF to value 0x04"] +impl crate::Resettable for LP_AONCLKRST_LP_CLK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x04; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_en.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_en.rs new file mode 100644 index 0000000000..c0a0d6d318 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_en.rs @@ -0,0 +1,173 @@ +#[doc = "Register `LP_AONCLKRST_LP_CLK_EN` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_LP_CLK_EN` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON` reader - need_des"] +pub type LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON` writer - need_des"] +pub type LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_CK_EN_LP_RAM` reader - need_des"] +pub type LP_AONCLKRST_CK_EN_LP_RAM_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CK_EN_LP_RAM` writer - need_des"] +pub type LP_AONCLKRST_CK_EN_LP_RAM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_ETM_EVENT_TICK_EN` reader - need_des"] +pub type LP_AONCLKRST_ETM_EVENT_TICK_EN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_ETM_EVENT_TICK_EN` writer - need_des"] +pub type LP_AONCLKRST_ETM_EVENT_TICK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_PLL8M_CLK_FORCE_ON` reader - need_des"] +pub type LP_AONCLKRST_PLL8M_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_PLL8M_CLK_FORCE_ON` writer - need_des"] +pub type LP_AONCLKRST_PLL8M_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_XTAL_CLK_FORCE_ON` reader - need_des"] +pub type LP_AONCLKRST_XTAL_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_XTAL_CLK_FORCE_ON` writer - need_des"] +pub type LP_AONCLKRST_XTAL_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_FOSC_CLK_FORCE_ON` reader - need_des"] +pub type LP_AONCLKRST_FOSC_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_FOSC_CLK_FORCE_ON` writer - need_des"] +pub type LP_AONCLKRST_FOSC_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_lp_rtc_xtal_force_on(&self) -> LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_R { + LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_ck_en_lp_ram(&self) -> LP_AONCLKRST_CK_EN_LP_RAM_R { + LP_AONCLKRST_CK_EN_LP_RAM_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_etm_event_tick_en(&self) -> LP_AONCLKRST_ETM_EVENT_TICK_EN_R { + LP_AONCLKRST_ETM_EVENT_TICK_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_pll8m_clk_force_on(&self) -> LP_AONCLKRST_PLL8M_CLK_FORCE_ON_R { + LP_AONCLKRST_PLL8M_CLK_FORCE_ON_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_xtal_clk_force_on(&self) -> LP_AONCLKRST_XTAL_CLK_FORCE_ON_R { + LP_AONCLKRST_XTAL_CLK_FORCE_ON_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_fosc_clk_force_on(&self) -> LP_AONCLKRST_FOSC_CLK_FORCE_ON_R { + LP_AONCLKRST_FOSC_CLK_FORCE_ON_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_LP_CLK_EN") + .field( + "lp_aonclkrst_lp_rtc_xtal_force_on", + &format_args!("{}", self.lp_aonclkrst_lp_rtc_xtal_force_on().bit()), + ) + .field( + "lp_aonclkrst_ck_en_lp_ram", + &format_args!("{}", self.lp_aonclkrst_ck_en_lp_ram().bit()), + ) + .field( + "lp_aonclkrst_etm_event_tick_en", + &format_args!("{}", self.lp_aonclkrst_etm_event_tick_en().bit()), + ) + .field( + "lp_aonclkrst_pll8m_clk_force_on", + &format_args!("{}", self.lp_aonclkrst_pll8m_clk_force_on().bit()), + ) + .field( + "lp_aonclkrst_xtal_clk_force_on", + &format_args!("{}", self.lp_aonclkrst_xtal_clk_force_on().bit()), + ) + .field( + "lp_aonclkrst_fosc_clk_force_on", + &format_args!("{}", self.lp_aonclkrst_fosc_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_lp_rtc_xtal_force_on( + &mut self, + ) -> LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_W { + LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_ck_en_lp_ram( + &mut self, + ) -> LP_AONCLKRST_CK_EN_LP_RAM_W { + LP_AONCLKRST_CK_EN_LP_RAM_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_etm_event_tick_en( + &mut self, + ) -> LP_AONCLKRST_ETM_EVENT_TICK_EN_W { + LP_AONCLKRST_ETM_EVENT_TICK_EN_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_pll8m_clk_force_on( + &mut self, + ) -> LP_AONCLKRST_PLL8M_CLK_FORCE_ON_W { + LP_AONCLKRST_PLL8M_CLK_FORCE_ON_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_xtal_clk_force_on( + &mut self, + ) -> LP_AONCLKRST_XTAL_CLK_FORCE_ON_W { + LP_AONCLKRST_XTAL_CLK_FORCE_ON_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_fosc_clk_force_on( + &mut self, + ) -> LP_AONCLKRST_FOSC_CLK_FORCE_ON_W { + LP_AONCLKRST_FOSC_CLK_FORCE_ON_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_lp_clk_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_lp_clk_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_LP_CLK_EN_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_LP_CLK_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_lp_clk_en::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_LP_CLK_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_lp_clk_en::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_LP_CLK_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_LP_CLK_EN to value 0x0800_0000"] +impl crate::Resettable for LP_AONCLKRST_LP_CLK_EN_SPEC { + const RESET_VALUE: Self::Ux = 0x0800_0000; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_po_en.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_po_en.rs new file mode 100644 index 0000000000..77b26e9386 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_po_en.rs @@ -0,0 +1,257 @@ +#[doc = "Register `LP_AONCLKRST_LP_CLK_PO_EN` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_LP_CLK_PO_EN` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_CLK_CORE_EFUSE_OEN` reader - need_des"] +pub type LP_AONCLKRST_CLK_CORE_EFUSE_OEN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CLK_CORE_EFUSE_OEN` writer - need_des"] +pub type LP_AONCLKRST_CLK_CORE_EFUSE_OEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_CLK_LP_BUS_OEN` reader - need_des"] +pub type LP_AONCLKRST_CLK_LP_BUS_OEN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CLK_LP_BUS_OEN` writer - need_des"] +pub type LP_AONCLKRST_CLK_LP_BUS_OEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_CLK_AON_SLOW_OEN` reader - need_des"] +pub type LP_AONCLKRST_CLK_AON_SLOW_OEN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CLK_AON_SLOW_OEN` writer - need_des"] +pub type LP_AONCLKRST_CLK_AON_SLOW_OEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_CLK_AON_FAST_OEN` reader - need_des"] +pub type LP_AONCLKRST_CLK_AON_FAST_OEN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CLK_AON_FAST_OEN` writer - need_des"] +pub type LP_AONCLKRST_CLK_AON_FAST_OEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_CLK_SLOW_OEN` reader - need_des"] +pub type LP_AONCLKRST_CLK_SLOW_OEN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CLK_SLOW_OEN` writer - need_des"] +pub type LP_AONCLKRST_CLK_SLOW_OEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_CLK_FAST_OEN` reader - need_des"] +pub type LP_AONCLKRST_CLK_FAST_OEN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CLK_FAST_OEN` writer - need_des"] +pub type LP_AONCLKRST_CLK_FAST_OEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_CLK_FOSC_OEN` reader - need_des"] +pub type LP_AONCLKRST_CLK_FOSC_OEN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CLK_FOSC_OEN` writer - need_des"] +pub type LP_AONCLKRST_CLK_FOSC_OEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_CLK_RC32K_OEN` reader - need_des"] +pub type LP_AONCLKRST_CLK_RC32K_OEN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CLK_RC32K_OEN` writer - need_des"] +pub type LP_AONCLKRST_CLK_RC32K_OEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_CLK_SXTAL_OEN` reader - need_des"] +pub type LP_AONCLKRST_CLK_SXTAL_OEN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CLK_SXTAL_OEN` writer - need_des"] +pub type LP_AONCLKRST_CLK_SXTAL_OEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_CLK_SOSC_OEN` reader - 1'b1: probe sosc clk on 1'b0: probe sosc clk off"] +pub type LP_AONCLKRST_CLK_SOSC_OEN_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_CLK_SOSC_OEN` writer - 1'b1: probe sosc clk on 1'b0: probe sosc clk off"] +pub type LP_AONCLKRST_CLK_SOSC_OEN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_clk_core_efuse_oen(&self) -> LP_AONCLKRST_CLK_CORE_EFUSE_OEN_R { + LP_AONCLKRST_CLK_CORE_EFUSE_OEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_clk_lp_bus_oen(&self) -> LP_AONCLKRST_CLK_LP_BUS_OEN_R { + LP_AONCLKRST_CLK_LP_BUS_OEN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_clk_aon_slow_oen(&self) -> LP_AONCLKRST_CLK_AON_SLOW_OEN_R { + LP_AONCLKRST_CLK_AON_SLOW_OEN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_clk_aon_fast_oen(&self) -> LP_AONCLKRST_CLK_AON_FAST_OEN_R { + LP_AONCLKRST_CLK_AON_FAST_OEN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_clk_slow_oen(&self) -> LP_AONCLKRST_CLK_SLOW_OEN_R { + LP_AONCLKRST_CLK_SLOW_OEN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_clk_fast_oen(&self) -> LP_AONCLKRST_CLK_FAST_OEN_R { + LP_AONCLKRST_CLK_FAST_OEN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_clk_fosc_oen(&self) -> LP_AONCLKRST_CLK_FOSC_OEN_R { + LP_AONCLKRST_CLK_FOSC_OEN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_clk_rc32k_oen(&self) -> LP_AONCLKRST_CLK_RC32K_OEN_R { + LP_AONCLKRST_CLK_RC32K_OEN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_clk_sxtal_oen(&self) -> LP_AONCLKRST_CLK_SXTAL_OEN_R { + LP_AONCLKRST_CLK_SXTAL_OEN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1'b1: probe sosc clk on 1'b0: probe sosc clk off"] + #[inline(always)] + pub fn lp_aonclkrst_clk_sosc_oen(&self) -> LP_AONCLKRST_CLK_SOSC_OEN_R { + LP_AONCLKRST_CLK_SOSC_OEN_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_LP_CLK_PO_EN") + .field( + "lp_aonclkrst_clk_core_efuse_oen", + &format_args!("{}", self.lp_aonclkrst_clk_core_efuse_oen().bit()), + ) + .field( + "lp_aonclkrst_clk_lp_bus_oen", + &format_args!("{}", self.lp_aonclkrst_clk_lp_bus_oen().bit()), + ) + .field( + "lp_aonclkrst_clk_aon_slow_oen", + &format_args!("{}", self.lp_aonclkrst_clk_aon_slow_oen().bit()), + ) + .field( + "lp_aonclkrst_clk_aon_fast_oen", + &format_args!("{}", self.lp_aonclkrst_clk_aon_fast_oen().bit()), + ) + .field( + "lp_aonclkrst_clk_slow_oen", + &format_args!("{}", self.lp_aonclkrst_clk_slow_oen().bit()), + ) + .field( + "lp_aonclkrst_clk_fast_oen", + &format_args!("{}", self.lp_aonclkrst_clk_fast_oen().bit()), + ) + .field( + "lp_aonclkrst_clk_fosc_oen", + &format_args!("{}", self.lp_aonclkrst_clk_fosc_oen().bit()), + ) + .field( + "lp_aonclkrst_clk_rc32k_oen", + &format_args!("{}", self.lp_aonclkrst_clk_rc32k_oen().bit()), + ) + .field( + "lp_aonclkrst_clk_sxtal_oen", + &format_args!("{}", self.lp_aonclkrst_clk_sxtal_oen().bit()), + ) + .field( + "lp_aonclkrst_clk_sosc_oen", + &format_args!("{}", self.lp_aonclkrst_clk_sosc_oen().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_clk_core_efuse_oen( + &mut self, + ) -> LP_AONCLKRST_CLK_CORE_EFUSE_OEN_W { + LP_AONCLKRST_CLK_CORE_EFUSE_OEN_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_clk_lp_bus_oen( + &mut self, + ) -> LP_AONCLKRST_CLK_LP_BUS_OEN_W { + LP_AONCLKRST_CLK_LP_BUS_OEN_W::new(self, 1) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_clk_aon_slow_oen( + &mut self, + ) -> LP_AONCLKRST_CLK_AON_SLOW_OEN_W { + LP_AONCLKRST_CLK_AON_SLOW_OEN_W::new(self, 2) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_clk_aon_fast_oen( + &mut self, + ) -> LP_AONCLKRST_CLK_AON_FAST_OEN_W { + LP_AONCLKRST_CLK_AON_FAST_OEN_W::new(self, 3) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_clk_slow_oen( + &mut self, + ) -> LP_AONCLKRST_CLK_SLOW_OEN_W { + LP_AONCLKRST_CLK_SLOW_OEN_W::new(self, 4) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_clk_fast_oen( + &mut self, + ) -> LP_AONCLKRST_CLK_FAST_OEN_W { + LP_AONCLKRST_CLK_FAST_OEN_W::new(self, 5) + } + #[doc = "Bit 6 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_clk_fosc_oen( + &mut self, + ) -> LP_AONCLKRST_CLK_FOSC_OEN_W { + LP_AONCLKRST_CLK_FOSC_OEN_W::new(self, 6) + } + #[doc = "Bit 7 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_clk_rc32k_oen( + &mut self, + ) -> LP_AONCLKRST_CLK_RC32K_OEN_W { + LP_AONCLKRST_CLK_RC32K_OEN_W::new(self, 7) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_clk_sxtal_oen( + &mut self, + ) -> LP_AONCLKRST_CLK_SXTAL_OEN_W { + LP_AONCLKRST_CLK_SXTAL_OEN_W::new(self, 8) + } + #[doc = "Bit 9 - 1'b1: probe sosc clk on 1'b0: probe sosc clk off"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_clk_sosc_oen( + &mut self, + ) -> LP_AONCLKRST_CLK_SOSC_OEN_W { + LP_AONCLKRST_CLK_SOSC_OEN_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_lp_clk_po_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_lp_clk_po_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_LP_CLK_PO_EN_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_LP_CLK_PO_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_lp_clk_po_en::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_LP_CLK_PO_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_lp_clk_po_en::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_LP_CLK_PO_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_LP_CLK_PO_EN to value 0"] +impl crate::Resettable for LP_AONCLKRST_LP_CLK_PO_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_rst_en.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_rst_en.rs new file mode 100644 index 0000000000..030d7de758 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_rst_en.rs @@ -0,0 +1,215 @@ +#[doc = "Register `LP_AONCLKRST_LP_RST_EN` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_LP_RST_EN` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_HUK` reader - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_HUK_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_HUK` writer - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_HUK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_ANAPERI` reader - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_ANAPERI_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_ANAPERI` writer - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_ANAPERI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_WDT` reader - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_WDT_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_WDT` writer - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_WDT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_TIMER` reader - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_TIMER_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_TIMER` writer - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_RTC` reader - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_RTC_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_RTC` writer - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_RTC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_MAILBOX` reader - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_MAILBOX_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_MAILBOX` writer - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_MAILBOX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_AONEFUSEREG` reader - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_AONEFUSEREG` writer - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_RAM` reader - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_RAM_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_RST_EN_LP_RAM` writer - need_des"] +pub type LP_AONCLKRST_RST_EN_LP_RAM_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 24 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_lp_huk(&self) -> LP_AONCLKRST_RST_EN_LP_HUK_R { + LP_AONCLKRST_RST_EN_LP_HUK_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_lp_anaperi(&self) -> LP_AONCLKRST_RST_EN_LP_ANAPERI_R { + LP_AONCLKRST_RST_EN_LP_ANAPERI_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_lp_wdt(&self) -> LP_AONCLKRST_RST_EN_LP_WDT_R { + LP_AONCLKRST_RST_EN_LP_WDT_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_lp_timer(&self) -> LP_AONCLKRST_RST_EN_LP_TIMER_R { + LP_AONCLKRST_RST_EN_LP_TIMER_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_lp_rtc(&self) -> LP_AONCLKRST_RST_EN_LP_RTC_R { + LP_AONCLKRST_RST_EN_LP_RTC_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_lp_mailbox(&self) -> LP_AONCLKRST_RST_EN_LP_MAILBOX_R { + LP_AONCLKRST_RST_EN_LP_MAILBOX_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_lp_aonefusereg(&self) -> LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_R { + LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_rst_en_lp_ram(&self) -> LP_AONCLKRST_RST_EN_LP_RAM_R { + LP_AONCLKRST_RST_EN_LP_RAM_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_LP_RST_EN") + .field( + "lp_aonclkrst_rst_en_lp_huk", + &format_args!("{}", self.lp_aonclkrst_rst_en_lp_huk().bit()), + ) + .field( + "lp_aonclkrst_rst_en_lp_anaperi", + &format_args!("{}", self.lp_aonclkrst_rst_en_lp_anaperi().bit()), + ) + .field( + "lp_aonclkrst_rst_en_lp_wdt", + &format_args!("{}", self.lp_aonclkrst_rst_en_lp_wdt().bit()), + ) + .field( + "lp_aonclkrst_rst_en_lp_timer", + &format_args!("{}", self.lp_aonclkrst_rst_en_lp_timer().bit()), + ) + .field( + "lp_aonclkrst_rst_en_lp_rtc", + &format_args!("{}", self.lp_aonclkrst_rst_en_lp_rtc().bit()), + ) + .field( + "lp_aonclkrst_rst_en_lp_mailbox", + &format_args!("{}", self.lp_aonclkrst_rst_en_lp_mailbox().bit()), + ) + .field( + "lp_aonclkrst_rst_en_lp_aonefusereg", + &format_args!("{}", self.lp_aonclkrst_rst_en_lp_aonefusereg().bit()), + ) + .field( + "lp_aonclkrst_rst_en_lp_ram", + &format_args!("{}", self.lp_aonclkrst_rst_en_lp_ram().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 24 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_lp_huk( + &mut self, + ) -> LP_AONCLKRST_RST_EN_LP_HUK_W { + LP_AONCLKRST_RST_EN_LP_HUK_W::new(self, 24) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_lp_anaperi( + &mut self, + ) -> LP_AONCLKRST_RST_EN_LP_ANAPERI_W { + LP_AONCLKRST_RST_EN_LP_ANAPERI_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_lp_wdt( + &mut self, + ) -> LP_AONCLKRST_RST_EN_LP_WDT_W { + LP_AONCLKRST_RST_EN_LP_WDT_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_lp_timer( + &mut self, + ) -> LP_AONCLKRST_RST_EN_LP_TIMER_W { + LP_AONCLKRST_RST_EN_LP_TIMER_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_lp_rtc( + &mut self, + ) -> LP_AONCLKRST_RST_EN_LP_RTC_W { + LP_AONCLKRST_RST_EN_LP_RTC_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_lp_mailbox( + &mut self, + ) -> LP_AONCLKRST_RST_EN_LP_MAILBOX_W { + LP_AONCLKRST_RST_EN_LP_MAILBOX_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_lp_aonefusereg( + &mut self, + ) -> LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_W { + LP_AONCLKRST_RST_EN_LP_AONEFUSEREG_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rst_en_lp_ram( + &mut self, + ) -> LP_AONCLKRST_RST_EN_LP_RAM_W { + LP_AONCLKRST_RST_EN_LP_RAM_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_lp_rst_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_lp_rst_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_LP_RST_EN_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_LP_RST_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_lp_rst_en::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_LP_RST_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_lp_rst_en::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_LP_RST_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_LP_RST_EN to value 0"] +impl crate::Resettable for LP_AONCLKRST_LP_RST_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lpmem_force.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lpmem_force.rs new file mode 100644 index 0000000000..aaef6535f3 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lpmem_force.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_AONCLKRST_LPMEM_FORCE` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_LPMEM_FORCE` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_LPMEM_CLK_FORCE_ON` reader - reserved"] +pub type LP_AONCLKRST_LPMEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_LPMEM_CLK_FORCE_ON` writer - reserved"] +pub type LP_AONCLKRST_LPMEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - reserved"] + #[inline(always)] + pub fn lp_aonclkrst_lpmem_clk_force_on(&self) -> LP_AONCLKRST_LPMEM_CLK_FORCE_ON_R { + LP_AONCLKRST_LPMEM_CLK_FORCE_ON_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_LPMEM_FORCE") + .field( + "lp_aonclkrst_lpmem_clk_force_on", + &format_args!("{}", self.lp_aonclkrst_lpmem_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - reserved"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_lpmem_clk_force_on( + &mut self, + ) -> LP_AONCLKRST_LPMEM_CLK_FORCE_ON_W { + LP_AONCLKRST_LPMEM_CLK_FORCE_ON_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_lpmem_force::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_lpmem_force::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_LPMEM_FORCE_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_LPMEM_FORCE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_lpmem_force::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_LPMEM_FORCE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_lpmem_force::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_LPMEM_FORCE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_LPMEM_FORCE to value 0"] +impl crate::Resettable for LP_AONCLKRST_LPMEM_FORCE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_mux_hpsys_reset_bypass.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_mux_hpsys_reset_bypass.rs new file mode 100644 index 0000000000..b6d57fbb7c --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_mux_hpsys_reset_bypass.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS` reader - reserved"] +pub type LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS` writer - reserved"] +pub type LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + pub fn lp_aonclkrst_mux_hpsys_reset_bypass(&self) -> LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_R { + LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS") + .field( + "lp_aonclkrst_mux_hpsys_reset_bypass", + &format_args!("{}", self.lp_aonclkrst_mux_hpsys_reset_bypass().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - reserved"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_mux_hpsys_reset_bypass( + &mut self, + ) -> LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_W { + LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_mux_hpsys_reset_bypass::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_mux_hpsys_reset_bypass::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_mux_hpsys_reset_bypass::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_mux_hpsys_reset_bypass::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS to value 0xffff_ffff"] +impl crate::Resettable for LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_rc32k_cntl.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_rc32k_cntl.rs new file mode 100644 index 0000000000..40da227add --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_rc32k_cntl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_AONCLKRST_RC32K_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_RC32K_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_RC32K_DFREQ` reader - need_des"] +pub type LP_AONCLKRST_RC32K_DFREQ_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_RC32K_DFREQ` writer - need_des"] +pub type LP_AONCLKRST_RC32K_DFREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_rc32k_dfreq(&self) -> LP_AONCLKRST_RC32K_DFREQ_R { + LP_AONCLKRST_RC32K_DFREQ_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_RC32K_CNTL") + .field( + "lp_aonclkrst_rc32k_dfreq", + &format_args!("{}", self.lp_aonclkrst_rc32k_dfreq().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_rc32k_dfreq( + &mut self, + ) -> LP_AONCLKRST_RC32K_DFREQ_W { + LP_AONCLKRST_RC32K_DFREQ_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_rc32k_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_rc32k_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_RC32K_CNTL_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_RC32K_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_rc32k_cntl::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_RC32K_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_rc32k_cntl::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_RC32K_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_RC32K_CNTL to value 0x028a"] +impl crate::Resettable for LP_AONCLKRST_RC32K_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x028a; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_reset_cause.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_reset_cause.rs new file mode 100644 index 0000000000..7387ae85e6 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_reset_cause.rs @@ -0,0 +1,199 @@ +#[doc = "Register `LP_AONCLKRST_RESET_CAUSE` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_RESET_CAUSE` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_LPCORE_RESET_CAUSE` reader - 6'h1: POR reset 6'h9: PMU LP PERI power down reset 6'ha: PMU LP CPU reset 6'hf: brown out reset 6'h10: LP watchdog chip reset 6'h12: super watch dog reset 6'h13: glitch reset 6'h14: software reset"] +pub type LP_AONCLKRST_LPCORE_RESET_CAUSE_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_LPCORE_RESET_FLAG` reader - need_des"] +pub type LP_AONCLKRST_LPCORE_RESET_FLAG_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HPCORE0_RESET_CAUSE` reader - 6'h1: POR reset 6'h3: digital system software reset 6'h5: PMU HP system power down reset 6'h7: HP system reset from HP watchdog 6'h9: HP system reset from LP watchdog 6'hb: HP core reset from HP watchdog 6'hc: HP core software reset 6'hd: HP core reset from LP watchdog 6'hf: brown out reset 6'h10: LP watchdog chip reset 6'h12: super watch dog reset 6'h13: glitch reset 6'h14: efuse crc error reset 6'h16: HP usb jtag chip reset 6'h17: HP usb uart chip reset 6'h18: HP jtag reset 6'h1a: HP core lockup"] +pub type LP_AONCLKRST_HPCORE0_RESET_CAUSE_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_HPCORE0_RESET_FLAG` reader - need_des"] +pub type LP_AONCLKRST_HPCORE0_RESET_FLAG_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_HPCORE1_RESET_CAUSE` reader - 6'h1: POR reset 6'h3: digital system software reset 6'h5: PMU HP system power down reset 6'h7: HP system reset from HP watchdog 6'h9: HP system reset from LP watchdog 6'hb: HP core reset from HP watchdog 6'hc: HP core software reset 6'hd: HP core reset from LP watchdog 6'hf: brown out reset 6'h10: LP watchdog chip reset 6'h12: super watch dog reset 6'h13: glitch reset 6'h14: efuse crc error reset 6'h16: HP usb jtag chip reset 6'h17: HP usb uart chip reset 6'h18: HP jtag reset 6'h1a: HP core lockup"] +pub type LP_AONCLKRST_HPCORE1_RESET_CAUSE_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_HPCORE1_RESET_FLAG` reader - need_des"] +pub type LP_AONCLKRST_HPCORE1_RESET_FLAG_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK` reader - 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore pmu_lp_cpu_reset reset_cause"] +pub type LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK` writer - 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore pmu_lp_cpu_reset reset_cause"] +pub type LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR` writer - need_des"] +pub type LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_LPCORE_RESET_FLAG_CLR` writer - need_des"] +pub type LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR` writer - need_des"] +pub type LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR` writer - need_des"] +pub type LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR` writer - need_des"] +pub type LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR` writer - need_des"] +pub type LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - 6'h1: POR reset 6'h9: PMU LP PERI power down reset 6'ha: PMU LP CPU reset 6'hf: brown out reset 6'h10: LP watchdog chip reset 6'h12: super watch dog reset 6'h13: glitch reset 6'h14: software reset"] + #[inline(always)] + pub fn lp_aonclkrst_lpcore_reset_cause(&self) -> LP_AONCLKRST_LPCORE_RESET_CAUSE_R { + LP_AONCLKRST_LPCORE_RESET_CAUSE_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_lpcore_reset_flag(&self) -> LP_AONCLKRST_LPCORE_RESET_FLAG_R { + LP_AONCLKRST_LPCORE_RESET_FLAG_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:12 - 6'h1: POR reset 6'h3: digital system software reset 6'h5: PMU HP system power down reset 6'h7: HP system reset from HP watchdog 6'h9: HP system reset from LP watchdog 6'hb: HP core reset from HP watchdog 6'hc: HP core software reset 6'hd: HP core reset from LP watchdog 6'hf: brown out reset 6'h10: LP watchdog chip reset 6'h12: super watch dog reset 6'h13: glitch reset 6'h14: efuse crc error reset 6'h16: HP usb jtag chip reset 6'h17: HP usb uart chip reset 6'h18: HP jtag reset 6'h1a: HP core lockup"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore0_reset_cause(&self) -> LP_AONCLKRST_HPCORE0_RESET_CAUSE_R { + LP_AONCLKRST_HPCORE0_RESET_CAUSE_R::new(((self.bits >> 7) & 0x3f) as u8) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore0_reset_flag(&self) -> LP_AONCLKRST_HPCORE0_RESET_FLAG_R { + LP_AONCLKRST_HPCORE0_RESET_FLAG_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:19 - 6'h1: POR reset 6'h3: digital system software reset 6'h5: PMU HP system power down reset 6'h7: HP system reset from HP watchdog 6'h9: HP system reset from LP watchdog 6'hb: HP core reset from HP watchdog 6'hc: HP core software reset 6'hd: HP core reset from LP watchdog 6'hf: brown out reset 6'h10: LP watchdog chip reset 6'h12: super watch dog reset 6'h13: glitch reset 6'h14: efuse crc error reset 6'h16: HP usb jtag chip reset 6'h17: HP usb uart chip reset 6'h18: HP jtag reset 6'h1a: HP core lockup"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore1_reset_cause(&self) -> LP_AONCLKRST_HPCORE1_RESET_CAUSE_R { + LP_AONCLKRST_HPCORE1_RESET_CAUSE_R::new(((self.bits >> 14) & 0x3f) as u8) + } + #[doc = "Bit 20 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_hpcore1_reset_flag(&self) -> LP_AONCLKRST_HPCORE1_RESET_FLAG_R { + LP_AONCLKRST_HPCORE1_RESET_FLAG_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 25 - 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore pmu_lp_cpu_reset reset_cause"] + #[inline(always)] + pub fn lp_aonclkrst_lpcore_reset_cause_pmu_lp_cpu_mask( + &self, + ) -> LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_R { + LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_RESET_CAUSE") + .field( + "lp_aonclkrst_lpcore_reset_cause", + &format_args!("{}", self.lp_aonclkrst_lpcore_reset_cause().bits()), + ) + .field( + "lp_aonclkrst_lpcore_reset_flag", + &format_args!("{}", self.lp_aonclkrst_lpcore_reset_flag().bit()), + ) + .field( + "lp_aonclkrst_hpcore0_reset_cause", + &format_args!("{}", self.lp_aonclkrst_hpcore0_reset_cause().bits()), + ) + .field( + "lp_aonclkrst_hpcore0_reset_flag", + &format_args!("{}", self.lp_aonclkrst_hpcore0_reset_flag().bit()), + ) + .field( + "lp_aonclkrst_hpcore1_reset_cause", + &format_args!("{}", self.lp_aonclkrst_hpcore1_reset_cause().bits()), + ) + .field( + "lp_aonclkrst_hpcore1_reset_flag", + &format_args!("{}", self.lp_aonclkrst_hpcore1_reset_flag().bit()), + ) + .field( + "lp_aonclkrst_lpcore_reset_cause_pmu_lp_cpu_mask", + &format_args!( + "{}", + self.lp_aonclkrst_lpcore_reset_cause_pmu_lp_cpu_mask().bit() + ), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 25 - 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore pmu_lp_cpu_reset reset_cause"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_lpcore_reset_cause_pmu_lp_cpu_mask( + &mut self, + ) -> LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_W { + LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_lpcore_reset_cause_clr( + &mut self, + ) -> LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_W { + LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_lpcore_reset_flag_clr( + &mut self, + ) -> LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_W { + LP_AONCLKRST_LPCORE_RESET_FLAG_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore0_reset_cause_clr( + &mut self, + ) -> LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_W { + LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore0_reset_flag_clr( + &mut self, + ) -> LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_W { + LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore1_reset_cause_clr( + &mut self, + ) -> LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_W { + LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_hpcore1_reset_flag_clr( + &mut self, + ) -> LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_W { + LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_reset_cause::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_reset_cause::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_RESET_CAUSE_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_RESET_CAUSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_reset_cause::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_RESET_CAUSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_reset_cause::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_RESET_CAUSE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_RESET_CAUSE to value 0x0200_0000"] +impl crate::Resettable for LP_AONCLKRST_RESET_CAUSE_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0000; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_sosc_cntl.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_sosc_cntl.rs new file mode 100644 index 0000000000..9ab9a017f3 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_sosc_cntl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_AONCLKRST_SOSC_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_SOSC_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_SOSC_DFREQ` reader - need_des"] +pub type LP_AONCLKRST_SOSC_DFREQ_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_SOSC_DFREQ` writer - need_des"] +pub type LP_AONCLKRST_SOSC_DFREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 22:31 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_sosc_dfreq(&self) -> LP_AONCLKRST_SOSC_DFREQ_R { + LP_AONCLKRST_SOSC_DFREQ_R::new(((self.bits >> 22) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_SOSC_CNTL") + .field( + "lp_aonclkrst_sosc_dfreq", + &format_args!("{}", self.lp_aonclkrst_sosc_dfreq().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 22:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_sosc_dfreq( + &mut self, + ) -> LP_AONCLKRST_SOSC_DFREQ_W { + LP_AONCLKRST_SOSC_DFREQ_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_sosc_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_sosc_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_SOSC_CNTL_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_SOSC_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_sosc_cntl::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_SOSC_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_sosc_cntl::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_SOSC_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_SOSC_CNTL to value 0x2b00_0000"] +impl crate::Resettable for LP_AONCLKRST_SOSC_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x2b00_0000; +} diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_xtal32k.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_xtal32k.rs new file mode 100644 index 0000000000..ab7f896de1 --- /dev/null +++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_xtal32k.rs @@ -0,0 +1,131 @@ +#[doc = "Register `LP_AONCLKRST_XTAL32K` reader"] +pub type R = crate::R; +#[doc = "Register `LP_AONCLKRST_XTAL32K` writer"] +pub type W = crate::W; +#[doc = "Field `LP_AONCLKRST_DRES_XTAL32K` reader - need_des"] +pub type LP_AONCLKRST_DRES_XTAL32K_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_DRES_XTAL32K` writer - need_des"] +pub type LP_AONCLKRST_DRES_XTAL32K_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LP_AONCLKRST_DGM_XTAL32K` reader - need_des"] +pub type LP_AONCLKRST_DGM_XTAL32K_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_DGM_XTAL32K` writer - need_des"] +pub type LP_AONCLKRST_DGM_XTAL32K_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LP_AONCLKRST_DBUF_XTAL32K` reader - need_des"] +pub type LP_AONCLKRST_DBUF_XTAL32K_R = crate::BitReader; +#[doc = "Field `LP_AONCLKRST_DBUF_XTAL32K` writer - need_des"] +pub type LP_AONCLKRST_DBUF_XTAL32K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_AONCLKRST_DAC_XTAL32K` reader - need_des"] +pub type LP_AONCLKRST_DAC_XTAL32K_R = crate::FieldReader; +#[doc = "Field `LP_AONCLKRST_DAC_XTAL32K` writer - need_des"] +pub type LP_AONCLKRST_DAC_XTAL32K_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 22:24 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_dres_xtal32k(&self) -> LP_AONCLKRST_DRES_XTAL32K_R { + LP_AONCLKRST_DRES_XTAL32K_R::new(((self.bits >> 22) & 7) as u8) + } + #[doc = "Bits 25:27 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_dgm_xtal32k(&self) -> LP_AONCLKRST_DGM_XTAL32K_R { + LP_AONCLKRST_DGM_XTAL32K_R::new(((self.bits >> 25) & 7) as u8) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_dbuf_xtal32k(&self) -> LP_AONCLKRST_DBUF_XTAL32K_R { + LP_AONCLKRST_DBUF_XTAL32K_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bits 29:31 - need_des"] + #[inline(always)] + pub fn lp_aonclkrst_dac_xtal32k(&self) -> LP_AONCLKRST_DAC_XTAL32K_R { + LP_AONCLKRST_DAC_XTAL32K_R::new(((self.bits >> 29) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_AONCLKRST_XTAL32K") + .field( + "lp_aonclkrst_dres_xtal32k", + &format_args!("{}", self.lp_aonclkrst_dres_xtal32k().bits()), + ) + .field( + "lp_aonclkrst_dgm_xtal32k", + &format_args!("{}", self.lp_aonclkrst_dgm_xtal32k().bits()), + ) + .field( + "lp_aonclkrst_dbuf_xtal32k", + &format_args!("{}", self.lp_aonclkrst_dbuf_xtal32k().bit()), + ) + .field( + "lp_aonclkrst_dac_xtal32k", + &format_args!("{}", self.lp_aonclkrst_dac_xtal32k().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 22:24 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_dres_xtal32k( + &mut self, + ) -> LP_AONCLKRST_DRES_XTAL32K_W { + LP_AONCLKRST_DRES_XTAL32K_W::new(self, 22) + } + #[doc = "Bits 25:27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_dgm_xtal32k( + &mut self, + ) -> LP_AONCLKRST_DGM_XTAL32K_W { + LP_AONCLKRST_DGM_XTAL32K_W::new(self, 25) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_dbuf_xtal32k( + &mut self, + ) -> LP_AONCLKRST_DBUF_XTAL32K_W { + LP_AONCLKRST_DBUF_XTAL32K_W::new(self, 28) + } + #[doc = "Bits 29:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_aonclkrst_dac_xtal32k( + &mut self, + ) -> LP_AONCLKRST_DAC_XTAL32K_W { + LP_AONCLKRST_DAC_XTAL32K_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_xtal32k::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_xtal32k::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_AONCLKRST_XTAL32K_SPEC; +impl crate::RegisterSpec for LP_AONCLKRST_XTAL32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_aonclkrst_xtal32k::R`](R) reader structure"] +impl crate::Readable for LP_AONCLKRST_XTAL32K_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_xtal32k::W`](W) writer structure"] +impl crate::Writable for LP_AONCLKRST_XTAL32K_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_AONCLKRST_XTAL32K to value 0x66c0_0000"] +impl crate::Resettable for LP_AONCLKRST_XTAL32K_SPEC { + const RESET_VALUE: Self::Ux = 0x66c0_0000; +} diff --git a/esp32p4/src/lp_gpio.rs b/esp32p4/src/lp_gpio.rs new file mode 100644 index 0000000000..8a15ad7ef3 --- /dev/null +++ b/esp32p4/src/lp_gpio.rs @@ -0,0 +1,598 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + clk_en: CLK_EN, + ver_date: VER_DATE, + out: OUT, + out_w1ts: OUT_W1TS, + out_w1tc: OUT_W1TC, + enable: ENABLE, + enable_w1ts: ENABLE_W1TS, + enable_w1tc: ENABLE_W1TC, + status: STATUS, + status_w1ts: STATUS_W1TS, + status_w1tc: STATUS_W1TC, + status_next: STATUS_NEXT, + in_: IN, + pin0: PIN0, + pin1: PIN1, + pin2: PIN2, + pin3: PIN3, + pin4: PIN4, + pin5: PIN5, + pin6: PIN6, + pin7: PIN7, + pin8: PIN8, + pin9: PIN9, + pin10: PIN10, + pin11: PIN11, + pin12: PIN12, + pin13: PIN13, + pin14: PIN14, + pin15: PIN15, + func0_in_sel_cfg: FUNC0_IN_SEL_CFG, + func1_in_sel_cfg: FUNC1_IN_SEL_CFG, + func2_in_sel_cfg: FUNC2_IN_SEL_CFG, + func3_in_sel_cfg: FUNC3_IN_SEL_CFG, + func4_in_sel_cfg: FUNC4_IN_SEL_CFG, + func5_in_sel_cfg: FUNC5_IN_SEL_CFG, + func6_in_sel_cfg: FUNC6_IN_SEL_CFG, + func7_in_sel_cfg: FUNC7_IN_SEL_CFG, + func8_in_sel_cfg: FUNC8_IN_SEL_CFG, + func9_in_sel_cfg: FUNC9_IN_SEL_CFG, + func10_in_sel_cfg: FUNC10_IN_SEL_CFG, + func11_in_sel_cfg: FUNC11_IN_SEL_CFG, + func12_in_sel_cfg: FUNC12_IN_SEL_CFG, + func13_in_sel_cfg: FUNC13_IN_SEL_CFG, + _reserved43: [u8; 0x48], + func0_out_sel_cfg: FUNC0_OUT_SEL_CFG, + func1_out_sel_cfg: FUNC1_OUT_SEL_CFG, + func2_out_sel_cfg: FUNC2_OUT_SEL_CFG, + func3_out_sel_cfg: FUNC3_OUT_SEL_CFG, + func4_out_sel_cfg: FUNC4_OUT_SEL_CFG, + func5_out_sel_cfg: FUNC5_OUT_SEL_CFG, + func6_out_sel_cfg: FUNC6_OUT_SEL_CFG, + func7_out_sel_cfg: FUNC7_OUT_SEL_CFG, + func8_out_sel_cfg: FUNC8_OUT_SEL_CFG, + func9_out_sel_cfg: FUNC9_OUT_SEL_CFG, + func10_out_sel_cfg: FUNC10_OUT_SEL_CFG, + func11_out_sel_cfg: FUNC11_OUT_SEL_CFG, + func12_out_sel_cfg: FUNC12_OUT_SEL_CFG, + func13_out_sel_cfg: FUNC13_OUT_SEL_CFG, + func14_out_sel_cfg: FUNC14_OUT_SEL_CFG, + func15_out_sel_cfg: FUNC15_OUT_SEL_CFG, +} +impl RegisterBlock { + #[doc = "0x00 - Reserved"] + #[inline(always)] + pub const fn clk_en(&self) -> &CLK_EN { + &self.clk_en + } + #[doc = "0x04 - Reserved"] + #[inline(always)] + pub const fn ver_date(&self) -> &VER_DATE { + &self.ver_date + } + #[doc = "0x08 - Reserved"] + #[inline(always)] + pub const fn out(&self) -> &OUT { + &self.out + } + #[doc = "0x0c - Reserved"] + #[inline(always)] + pub const fn out_w1ts(&self) -> &OUT_W1TS { + &self.out_w1ts + } + #[doc = "0x10 - Reserved"] + #[inline(always)] + pub const fn out_w1tc(&self) -> &OUT_W1TC { + &self.out_w1tc + } + #[doc = "0x14 - Reserved"] + #[inline(always)] + pub const fn enable(&self) -> &ENABLE { + &self.enable + } + #[doc = "0x18 - Reserved"] + #[inline(always)] + pub const fn enable_w1ts(&self) -> &ENABLE_W1TS { + &self.enable_w1ts + } + #[doc = "0x1c - Reserved"] + #[inline(always)] + pub const fn enable_w1tc(&self) -> &ENABLE_W1TC { + &self.enable_w1tc + } + #[doc = "0x20 - Reserved"] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0x24 - Reserved"] + #[inline(always)] + pub const fn status_w1ts(&self) -> &STATUS_W1TS { + &self.status_w1ts + } + #[doc = "0x28 - Reserved"] + #[inline(always)] + pub const fn status_w1tc(&self) -> &STATUS_W1TC { + &self.status_w1tc + } + #[doc = "0x2c - Reserved"] + #[inline(always)] + pub const fn status_next(&self) -> &STATUS_NEXT { + &self.status_next + } + #[doc = "0x30 - Reserved"] + #[inline(always)] + pub const fn in_(&self) -> &IN { + &self.in_ + } + #[doc = "0x34 - Reserved"] + #[inline(always)] + pub const fn pin0(&self) -> &PIN0 { + &self.pin0 + } + #[doc = "0x38 - Reserved"] + #[inline(always)] + pub const fn pin1(&self) -> &PIN1 { + &self.pin1 + } + #[doc = "0x3c - Reserved"] + #[inline(always)] + pub const fn pin2(&self) -> &PIN2 { + &self.pin2 + } + #[doc = "0x40 - Reserved"] + #[inline(always)] + pub const fn pin3(&self) -> &PIN3 { + &self.pin3 + } + #[doc = "0x44 - Reserved"] + #[inline(always)] + pub const fn pin4(&self) -> &PIN4 { + &self.pin4 + } + #[doc = "0x48 - Reserved"] + #[inline(always)] + pub const fn pin5(&self) -> &PIN5 { + &self.pin5 + } + #[doc = "0x4c - Reserved"] + #[inline(always)] + pub const fn pin6(&self) -> &PIN6 { + &self.pin6 + } + #[doc = "0x50 - Reserved"] + #[inline(always)] + pub const fn pin7(&self) -> &PIN7 { + &self.pin7 + } + #[doc = "0x54 - Reserved"] + #[inline(always)] + pub const fn pin8(&self) -> &PIN8 { + &self.pin8 + } + #[doc = "0x58 - Reserved"] + #[inline(always)] + pub const fn pin9(&self) -> &PIN9 { + &self.pin9 + } + #[doc = "0x5c - Reserved"] + #[inline(always)] + pub const fn pin10(&self) -> &PIN10 { + &self.pin10 + } + #[doc = "0x60 - Reserved"] + #[inline(always)] + pub const fn pin11(&self) -> &PIN11 { + &self.pin11 + } + #[doc = "0x64 - Reserved"] + #[inline(always)] + pub const fn pin12(&self) -> &PIN12 { + &self.pin12 + } + #[doc = "0x68 - Reserved"] + #[inline(always)] + pub const fn pin13(&self) -> &PIN13 { + &self.pin13 + } + #[doc = "0x6c - Reserved"] + #[inline(always)] + pub const fn pin14(&self) -> &PIN14 { + &self.pin14 + } + #[doc = "0x70 - Reserved"] + #[inline(always)] + pub const fn pin15(&self) -> &PIN15 { + &self.pin15 + } + #[doc = "0x74 - Reserved"] + #[inline(always)] + pub const fn func0_in_sel_cfg(&self) -> &FUNC0_IN_SEL_CFG { + &self.func0_in_sel_cfg + } + #[doc = "0x78 - Reserved"] + #[inline(always)] + pub const fn func1_in_sel_cfg(&self) -> &FUNC1_IN_SEL_CFG { + &self.func1_in_sel_cfg + } + #[doc = "0x7c - Reserved"] + #[inline(always)] + pub const fn func2_in_sel_cfg(&self) -> &FUNC2_IN_SEL_CFG { + &self.func2_in_sel_cfg + } + #[doc = "0x80 - Reserved"] + #[inline(always)] + pub const fn func3_in_sel_cfg(&self) -> &FUNC3_IN_SEL_CFG { + &self.func3_in_sel_cfg + } + #[doc = "0x84 - Reserved"] + #[inline(always)] + pub const fn func4_in_sel_cfg(&self) -> &FUNC4_IN_SEL_CFG { + &self.func4_in_sel_cfg + } + #[doc = "0x88 - Reserved"] + #[inline(always)] + pub const fn func5_in_sel_cfg(&self) -> &FUNC5_IN_SEL_CFG { + &self.func5_in_sel_cfg + } + #[doc = "0x8c - Reserved"] + #[inline(always)] + pub const fn func6_in_sel_cfg(&self) -> &FUNC6_IN_SEL_CFG { + &self.func6_in_sel_cfg + } + #[doc = "0x90 - Reserved"] + #[inline(always)] + pub const fn func7_in_sel_cfg(&self) -> &FUNC7_IN_SEL_CFG { + &self.func7_in_sel_cfg + } + #[doc = "0x94 - Reserved"] + #[inline(always)] + pub const fn func8_in_sel_cfg(&self) -> &FUNC8_IN_SEL_CFG { + &self.func8_in_sel_cfg + } + #[doc = "0x98 - Reserved"] + #[inline(always)] + pub const fn func9_in_sel_cfg(&self) -> &FUNC9_IN_SEL_CFG { + &self.func9_in_sel_cfg + } + #[doc = "0x9c - Reserved"] + #[inline(always)] + pub const fn func10_in_sel_cfg(&self) -> &FUNC10_IN_SEL_CFG { + &self.func10_in_sel_cfg + } + #[doc = "0xa0 - Reserved"] + #[inline(always)] + pub const fn func11_in_sel_cfg(&self) -> &FUNC11_IN_SEL_CFG { + &self.func11_in_sel_cfg + } + #[doc = "0xa4 - Reserved"] + #[inline(always)] + pub const fn func12_in_sel_cfg(&self) -> &FUNC12_IN_SEL_CFG { + &self.func12_in_sel_cfg + } + #[doc = "0xa8 - Reserved"] + #[inline(always)] + pub const fn func13_in_sel_cfg(&self) -> &FUNC13_IN_SEL_CFG { + &self.func13_in_sel_cfg + } + #[doc = "0xf4 - Reserved"] + #[inline(always)] + pub const fn func0_out_sel_cfg(&self) -> &FUNC0_OUT_SEL_CFG { + &self.func0_out_sel_cfg + } + #[doc = "0xf8 - Reserved"] + #[inline(always)] + pub const fn func1_out_sel_cfg(&self) -> &FUNC1_OUT_SEL_CFG { + &self.func1_out_sel_cfg + } + #[doc = "0xfc - Reserved"] + #[inline(always)] + pub const fn func2_out_sel_cfg(&self) -> &FUNC2_OUT_SEL_CFG { + &self.func2_out_sel_cfg + } + #[doc = "0x100 - Reserved"] + #[inline(always)] + pub const fn func3_out_sel_cfg(&self) -> &FUNC3_OUT_SEL_CFG { + &self.func3_out_sel_cfg + } + #[doc = "0x104 - Reserved"] + #[inline(always)] + pub const fn func4_out_sel_cfg(&self) -> &FUNC4_OUT_SEL_CFG { + &self.func4_out_sel_cfg + } + #[doc = "0x108 - Reserved"] + #[inline(always)] + pub const fn func5_out_sel_cfg(&self) -> &FUNC5_OUT_SEL_CFG { + &self.func5_out_sel_cfg + } + #[doc = "0x10c - Reserved"] + #[inline(always)] + pub const fn func6_out_sel_cfg(&self) -> &FUNC6_OUT_SEL_CFG { + &self.func6_out_sel_cfg + } + #[doc = "0x110 - Reserved"] + #[inline(always)] + pub const fn func7_out_sel_cfg(&self) -> &FUNC7_OUT_SEL_CFG { + &self.func7_out_sel_cfg + } + #[doc = "0x114 - Reserved"] + #[inline(always)] + pub const fn func8_out_sel_cfg(&self) -> &FUNC8_OUT_SEL_CFG { + &self.func8_out_sel_cfg + } + #[doc = "0x118 - Reserved"] + #[inline(always)] + pub const fn func9_out_sel_cfg(&self) -> &FUNC9_OUT_SEL_CFG { + &self.func9_out_sel_cfg + } + #[doc = "0x11c - Reserved"] + #[inline(always)] + pub const fn func10_out_sel_cfg(&self) -> &FUNC10_OUT_SEL_CFG { + &self.func10_out_sel_cfg + } + #[doc = "0x120 - Reserved"] + #[inline(always)] + pub const fn func11_out_sel_cfg(&self) -> &FUNC11_OUT_SEL_CFG { + &self.func11_out_sel_cfg + } + #[doc = "0x124 - Reserved"] + #[inline(always)] + pub const fn func12_out_sel_cfg(&self) -> &FUNC12_OUT_SEL_CFG { + &self.func12_out_sel_cfg + } + #[doc = "0x128 - Reserved"] + #[inline(always)] + pub const fn func13_out_sel_cfg(&self) -> &FUNC13_OUT_SEL_CFG { + &self.func13_out_sel_cfg + } + #[doc = "0x12c - Reserved"] + #[inline(always)] + pub const fn func14_out_sel_cfg(&self) -> &FUNC14_OUT_SEL_CFG { + &self.func14_out_sel_cfg + } + #[doc = "0x130 - Reserved"] + #[inline(always)] + pub const fn func15_out_sel_cfg(&self) -> &FUNC15_OUT_SEL_CFG { + &self.func15_out_sel_cfg + } +} +#[doc = "CLK_EN (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_en`] module"] +pub type CLK_EN = crate::Reg; +#[doc = "Reserved"] +pub mod clk_en; +#[doc = "VER_DATE (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ver_date`] module"] +pub type VER_DATE = crate::Reg; +#[doc = "Reserved"] +pub mod ver_date; +#[doc = "OUT (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out`] module"] +pub type OUT = crate::Reg; +#[doc = "Reserved"] +pub mod out; +#[doc = "OUT_W1TS (w) register accessor: Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_w1ts`] module"] +pub type OUT_W1TS = crate::Reg; +#[doc = "Reserved"] +pub mod out_w1ts; +#[doc = "OUT_W1TC (w) register accessor: Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_w1tc`] module"] +pub type OUT_W1TC = crate::Reg; +#[doc = "Reserved"] +pub mod out_w1tc; +#[doc = "ENABLE (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"] +pub type ENABLE = crate::Reg; +#[doc = "Reserved"] +pub mod enable; +#[doc = "ENABLE_W1TS (w) register accessor: Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_w1ts`] module"] +pub type ENABLE_W1TS = crate::Reg; +#[doc = "Reserved"] +pub mod enable_w1ts; +#[doc = "ENABLE_W1TC (w) register accessor: Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_w1tc`] module"] +pub type ENABLE_W1TC = crate::Reg; +#[doc = "Reserved"] +pub mod enable_w1tc; +#[doc = "STATUS (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +pub type STATUS = crate::Reg; +#[doc = "Reserved"] +pub mod status; +#[doc = "STATUS_W1TS (w) register accessor: Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_w1ts`] module"] +pub type STATUS_W1TS = crate::Reg; +#[doc = "Reserved"] +pub mod status_w1ts; +#[doc = "STATUS_W1TC (w) register accessor: Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_w1tc`] module"] +pub type STATUS_W1TC = crate::Reg; +#[doc = "Reserved"] +pub mod status_w1tc; +#[doc = "STATUS_NEXT (r) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_next`] module"] +pub type STATUS_NEXT = crate::Reg; +#[doc = "Reserved"] +pub mod status_next; +#[doc = "IN (r) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_`] module"] +pub type IN = crate::Reg; +#[doc = "Reserved"] +pub mod in_; +#[doc = "PIN0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin0`] module"] +pub type PIN0 = crate::Reg; +#[doc = "Reserved"] +pub mod pin0; +#[doc = "PIN1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin1`] module"] +pub type PIN1 = crate::Reg; +#[doc = "Reserved"] +pub mod pin1; +#[doc = "PIN2 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin2`] module"] +pub type PIN2 = crate::Reg; +#[doc = "Reserved"] +pub mod pin2; +#[doc = "PIN3 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin3`] module"] +pub type PIN3 = crate::Reg; +#[doc = "Reserved"] +pub mod pin3; +#[doc = "PIN4 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin4`] module"] +pub type PIN4 = crate::Reg; +#[doc = "Reserved"] +pub mod pin4; +#[doc = "PIN5 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin5`] module"] +pub type PIN5 = crate::Reg; +#[doc = "Reserved"] +pub mod pin5; +#[doc = "PIN6 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin6`] module"] +pub type PIN6 = crate::Reg; +#[doc = "Reserved"] +pub mod pin6; +#[doc = "PIN7 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin7`] module"] +pub type PIN7 = crate::Reg; +#[doc = "Reserved"] +pub mod pin7; +#[doc = "PIN8 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin8`] module"] +pub type PIN8 = crate::Reg; +#[doc = "Reserved"] +pub mod pin8; +#[doc = "PIN9 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin9`] module"] +pub type PIN9 = crate::Reg; +#[doc = "Reserved"] +pub mod pin9; +#[doc = "PIN10 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin10`] module"] +pub type PIN10 = crate::Reg; +#[doc = "Reserved"] +pub mod pin10; +#[doc = "PIN11 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin11`] module"] +pub type PIN11 = crate::Reg; +#[doc = "Reserved"] +pub mod pin11; +#[doc = "PIN12 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin12`] module"] +pub type PIN12 = crate::Reg; +#[doc = "Reserved"] +pub mod pin12; +#[doc = "PIN13 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin13`] module"] +pub type PIN13 = crate::Reg; +#[doc = "Reserved"] +pub mod pin13; +#[doc = "PIN14 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin14`] module"] +pub type PIN14 = crate::Reg; +#[doc = "Reserved"] +pub mod pin14; +#[doc = "PIN15 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin15`] module"] +pub type PIN15 = crate::Reg; +#[doc = "Reserved"] +pub mod pin15; +#[doc = "FUNC0_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func0_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func0_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func0_in_sel_cfg`] module"] +pub type FUNC0_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func0_in_sel_cfg; +#[doc = "FUNC1_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func1_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func1_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func1_in_sel_cfg`] module"] +pub type FUNC1_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func1_in_sel_cfg; +#[doc = "FUNC2_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func2_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func2_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func2_in_sel_cfg`] module"] +pub type FUNC2_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func2_in_sel_cfg; +#[doc = "FUNC3_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func3_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func3_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func3_in_sel_cfg`] module"] +pub type FUNC3_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func3_in_sel_cfg; +#[doc = "FUNC4_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func4_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func4_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func4_in_sel_cfg`] module"] +pub type FUNC4_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func4_in_sel_cfg; +#[doc = "FUNC5_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func5_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func5_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func5_in_sel_cfg`] module"] +pub type FUNC5_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func5_in_sel_cfg; +#[doc = "FUNC6_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func6_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func6_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func6_in_sel_cfg`] module"] +pub type FUNC6_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func6_in_sel_cfg; +#[doc = "FUNC7_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func7_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func7_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func7_in_sel_cfg`] module"] +pub type FUNC7_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func7_in_sel_cfg; +#[doc = "FUNC8_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func8_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func8_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func8_in_sel_cfg`] module"] +pub type FUNC8_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func8_in_sel_cfg; +#[doc = "FUNC9_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func9_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func9_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func9_in_sel_cfg`] module"] +pub type FUNC9_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func9_in_sel_cfg; +#[doc = "FUNC10_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func10_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func10_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func10_in_sel_cfg`] module"] +pub type FUNC10_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func10_in_sel_cfg; +#[doc = "FUNC11_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func11_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func11_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func11_in_sel_cfg`] module"] +pub type FUNC11_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func11_in_sel_cfg; +#[doc = "FUNC12_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func12_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func12_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func12_in_sel_cfg`] module"] +pub type FUNC12_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func12_in_sel_cfg; +#[doc = "FUNC13_IN_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func13_in_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func13_in_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func13_in_sel_cfg`] module"] +pub type FUNC13_IN_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func13_in_sel_cfg; +#[doc = "FUNC0_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func0_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func0_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func0_out_sel_cfg`] module"] +pub type FUNC0_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func0_out_sel_cfg; +#[doc = "FUNC1_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func1_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func1_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func1_out_sel_cfg`] module"] +pub type FUNC1_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func1_out_sel_cfg; +#[doc = "FUNC2_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func2_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func2_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func2_out_sel_cfg`] module"] +pub type FUNC2_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func2_out_sel_cfg; +#[doc = "FUNC3_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func3_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func3_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func3_out_sel_cfg`] module"] +pub type FUNC3_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func3_out_sel_cfg; +#[doc = "FUNC4_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func4_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func4_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func4_out_sel_cfg`] module"] +pub type FUNC4_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func4_out_sel_cfg; +#[doc = "FUNC5_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func5_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func5_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func5_out_sel_cfg`] module"] +pub type FUNC5_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func5_out_sel_cfg; +#[doc = "FUNC6_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func6_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func6_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func6_out_sel_cfg`] module"] +pub type FUNC6_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func6_out_sel_cfg; +#[doc = "FUNC7_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func7_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func7_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func7_out_sel_cfg`] module"] +pub type FUNC7_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func7_out_sel_cfg; +#[doc = "FUNC8_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func8_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func8_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func8_out_sel_cfg`] module"] +pub type FUNC8_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func8_out_sel_cfg; +#[doc = "FUNC9_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func9_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func9_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func9_out_sel_cfg`] module"] +pub type FUNC9_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func9_out_sel_cfg; +#[doc = "FUNC10_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func10_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func10_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func10_out_sel_cfg`] module"] +pub type FUNC10_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func10_out_sel_cfg; +#[doc = "FUNC11_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func11_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func11_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func11_out_sel_cfg`] module"] +pub type FUNC11_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func11_out_sel_cfg; +#[doc = "FUNC12_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func12_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func12_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func12_out_sel_cfg`] module"] +pub type FUNC12_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func12_out_sel_cfg; +#[doc = "FUNC13_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func13_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func13_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func13_out_sel_cfg`] module"] +pub type FUNC13_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func13_out_sel_cfg; +#[doc = "FUNC14_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func14_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func14_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func14_out_sel_cfg`] module"] +pub type FUNC14_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func14_out_sel_cfg; +#[doc = "FUNC15_OUT_SEL_CFG (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func15_out_sel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func15_out_sel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func15_out_sel_cfg`] module"] +pub type FUNC15_OUT_SEL_CFG = crate::Reg; +#[doc = "Reserved"] +pub mod func15_out_sel_cfg; diff --git a/esp32p4/src/lp_gpio/clk_en.rs b/esp32p4/src/lp_gpio/clk_en.rs new file mode 100644 index 0000000000..985706e75b --- /dev/null +++ b/esp32p4/src/lp_gpio/clk_en.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLK_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_EN` writer"] +pub type W = crate::W; +#[doc = "Field `REG_CLK_EN` reader - Reserved"] +pub type REG_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CLK_EN` writer - Reserved"] +pub type REG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_clk_en(&self) -> REG_CLK_EN_R { + REG_CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_EN") + .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_clk_en(&mut self) -> REG_CLK_EN_W { + REG_CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_EN_SPEC; +impl crate::RegisterSpec for CLK_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_en::R`](R) reader structure"] +impl crate::Readable for CLK_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_en::W`](W) writer structure"] +impl crate::Writable for CLK_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_EN to value 0x01"] +impl crate::Resettable for CLK_EN_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/lp_gpio/enable.rs b/esp32p4/src/lp_gpio/enable.rs new file mode 100644 index 0000000000..a46d0d9caa --- /dev/null +++ b/esp32p4/src/lp_gpio/enable.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_ENABLE_DATA` reader - Reserved"] +pub type REG_GPIO_ENABLE_DATA_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_ENABLE_DATA` writer - Reserved"] +pub type REG_GPIO_ENABLE_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + pub fn reg_gpio_enable_data(&self) -> REG_GPIO_ENABLE_DATA_R { + REG_GPIO_ENABLE_DATA_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENABLE") + .field( + "reg_gpio_enable_data", + &format_args!("{}", self.reg_gpio_enable_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_enable_data(&mut self) -> REG_GPIO_ENABLE_DATA_W { + REG_GPIO_ENABLE_DATA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENABLE_SPEC; +impl crate::RegisterSpec for ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`enable::R`](R) reader structure"] +impl crate::Readable for ENABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"] +impl crate::Writable for ENABLE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for ENABLE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/enable_w1tc.rs b/esp32p4/src/lp_gpio/enable_w1tc.rs new file mode 100644 index 0000000000..fe69dfa305 --- /dev/null +++ b/esp32p4/src/lp_gpio/enable_w1tc.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ENABLE_W1TC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_ENABLE_DATA_W1TC` writer - Reserved"] +pub type REG_GPIO_ENABLE_DATA_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_enable_data_w1tc(&mut self) -> REG_GPIO_ENABLE_DATA_W1TC_W { + REG_GPIO_ENABLE_DATA_W1TC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENABLE_W1TC_SPEC; +impl crate::RegisterSpec for ENABLE_W1TC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`enable_w1tc::W`](W) writer structure"] +impl crate::Writable for ENABLE_W1TC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLE_W1TC to value 0"] +impl crate::Resettable for ENABLE_W1TC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/enable_w1ts.rs b/esp32p4/src/lp_gpio/enable_w1ts.rs new file mode 100644 index 0000000000..2566f94f8f --- /dev/null +++ b/esp32p4/src/lp_gpio/enable_w1ts.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ENABLE_W1TS` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_ENABLE_DATA_W1TS` writer - Reserved"] +pub type REG_GPIO_ENABLE_DATA_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_enable_data_w1ts(&mut self) -> REG_GPIO_ENABLE_DATA_W1TS_W { + REG_GPIO_ENABLE_DATA_W1TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENABLE_W1TS_SPEC; +impl crate::RegisterSpec for ENABLE_W1TS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`enable_w1ts::W`](W) writer structure"] +impl crate::Writable for ENABLE_W1TS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENABLE_W1TS to value 0"] +impl crate::Resettable for ENABLE_W1TS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/func0_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func0_in_sel_cfg.rs new file mode 100644 index 0000000000..a4a6ce9c70 --- /dev/null +++ b/esp32p4/src/lp_gpio/func0_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC0_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC0_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC0_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC0_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC0_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC0_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG0_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG0_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG0_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG0_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC0_IN_SEL` reader - reg_gpio_func0_in_sel\\[5:4\\]==2'b11->constant 1,reg_gpio_func0_in_sel\\[5:4\\]==2'b10->constant 0"] +pub type REG_GPIO_FUNC0_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC0_IN_SEL` writer - reg_gpio_func0_in_sel\\[5:4\\]==2'b11->constant 1,reg_gpio_func0_in_sel\\[5:4\\]==2'b10->constant 0"] +pub type REG_GPIO_FUNC0_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func0_in_inv_sel(&self) -> REG_GPIO_FUNC0_IN_INV_SEL_R { + REG_GPIO_FUNC0_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig0_in_sel(&self) -> REG_GPIO_SIG0_IN_SEL_R { + REG_GPIO_SIG0_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - reg_gpio_func0_in_sel\\[5:4\\]==2'b11->constant 1,reg_gpio_func0_in_sel\\[5:4\\]==2'b10->constant 0"] + #[inline(always)] + pub fn reg_gpio_func0_in_sel(&self) -> REG_GPIO_FUNC0_IN_SEL_R { + REG_GPIO_FUNC0_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC0_IN_SEL_CFG") + .field( + "reg_gpio_func0_in_inv_sel", + &format_args!("{}", self.reg_gpio_func0_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig0_in_sel", + &format_args!("{}", self.reg_gpio_sig0_in_sel().bit()), + ) + .field( + "reg_gpio_func0_in_sel", + &format_args!("{}", self.reg_gpio_func0_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func0_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC0_IN_INV_SEL_W { + REG_GPIO_FUNC0_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig0_in_sel(&mut self) -> REG_GPIO_SIG0_IN_SEL_W { + REG_GPIO_SIG0_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - reg_gpio_func0_in_sel\\[5:4\\]==2'b11->constant 1,reg_gpio_func0_in_sel\\[5:4\\]==2'b10->constant 0"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func0_in_sel(&mut self) -> REG_GPIO_FUNC0_IN_SEL_W { + REG_GPIO_FUNC0_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func0_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func0_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC0_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC0_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func0_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC0_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func0_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC0_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC0_IN_SEL_CFG to value 0xc0"] +impl crate::Resettable for FUNC0_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0xc0; +} diff --git a/esp32p4/src/lp_gpio/func0_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func0_out_sel_cfg.rs new file mode 100644 index 0000000000..c896063bb4 --- /dev/null +++ b/esp32p4/src/lp_gpio/func0_out_sel_cfg.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FUNC0_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC0_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC0_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC0_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC0_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC0_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC0_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC0_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC0_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC0_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC0_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC0_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC0_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC0_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC0_OUT_SEL` reader - reg_gpio_func0_out_sel\\[5:1\\]==16 -> output gpio register value to pad"] +pub type REG_GPIO_FUNC0_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC0_OUT_SEL` writer - reg_gpio_func0_out_sel\\[5:1\\]==16 -> output gpio register value to pad"] +pub type REG_GPIO_FUNC0_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func0_oe_inv_sel(&self) -> REG_GPIO_FUNC0_OE_INV_SEL_R { + REG_GPIO_FUNC0_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func0_oe_sel(&self) -> REG_GPIO_FUNC0_OE_SEL_R { + REG_GPIO_FUNC0_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func0_out_inv_sel(&self) -> REG_GPIO_FUNC0_OUT_INV_SEL_R { + REG_GPIO_FUNC0_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - reg_gpio_func0_out_sel\\[5:1\\]==16 -> output gpio register value to pad"] + #[inline(always)] + pub fn reg_gpio_func0_out_sel(&self) -> REG_GPIO_FUNC0_OUT_SEL_R { + REG_GPIO_FUNC0_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC0_OUT_SEL_CFG") + .field( + "reg_gpio_func0_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func0_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func0_oe_sel", + &format_args!("{}", self.reg_gpio_func0_oe_sel().bit()), + ) + .field( + "reg_gpio_func0_out_inv_sel", + &format_args!("{}", self.reg_gpio_func0_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func0_out_sel", + &format_args!("{}", self.reg_gpio_func0_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func0_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC0_OE_INV_SEL_W { + REG_GPIO_FUNC0_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func0_oe_sel(&mut self) -> REG_GPIO_FUNC0_OE_SEL_W { + REG_GPIO_FUNC0_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func0_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC0_OUT_INV_SEL_W { + REG_GPIO_FUNC0_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - reg_gpio_func0_out_sel\\[5:1\\]==16 -> output gpio register value to pad"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func0_out_sel(&mut self) -> REG_GPIO_FUNC0_OUT_SEL_W { + REG_GPIO_FUNC0_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func0_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func0_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC0_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC0_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func0_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC0_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func0_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC0_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC0_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC0_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func10_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func10_in_sel_cfg.rs new file mode 100644 index 0000000000..9fb3377510 --- /dev/null +++ b/esp32p4/src/lp_gpio/func10_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC10_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC10_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC10_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC10_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC10_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC10_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG10_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG10_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG10_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG10_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC10_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC10_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC10_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC10_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func10_in_inv_sel(&self) -> REG_GPIO_FUNC10_IN_INV_SEL_R { + REG_GPIO_FUNC10_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig10_in_sel(&self) -> REG_GPIO_SIG10_IN_SEL_R { + REG_GPIO_SIG10_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func10_in_sel(&self) -> REG_GPIO_FUNC10_IN_SEL_R { + REG_GPIO_FUNC10_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC10_IN_SEL_CFG") + .field( + "reg_gpio_func10_in_inv_sel", + &format_args!("{}", self.reg_gpio_func10_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig10_in_sel", + &format_args!("{}", self.reg_gpio_sig10_in_sel().bit()), + ) + .field( + "reg_gpio_func10_in_sel", + &format_args!("{}", self.reg_gpio_func10_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func10_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC10_IN_INV_SEL_W { + REG_GPIO_FUNC10_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig10_in_sel(&mut self) -> REG_GPIO_SIG10_IN_SEL_W { + REG_GPIO_SIG10_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func10_in_sel(&mut self) -> REG_GPIO_FUNC10_IN_SEL_W { + REG_GPIO_FUNC10_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func10_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func10_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC10_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC10_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func10_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC10_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func10_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC10_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC10_IN_SEL_CFG to value 0x80"] +impl crate::Resettable for FUNC10_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/lp_gpio/func10_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func10_out_sel_cfg.rs new file mode 100644 index 0000000000..04c7ca9ce6 --- /dev/null +++ b/esp32p4/src/lp_gpio/func10_out_sel_cfg.rs @@ -0,0 +1,129 @@ +#[doc = "Register `FUNC10_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC10_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC10_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC10_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC10_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC10_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC10_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC10_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC10_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC10_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC10_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC10_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC10_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC10_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC10_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC10_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC10_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC10_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func10_oe_inv_sel(&self) -> REG_GPIO_FUNC10_OE_INV_SEL_R { + REG_GPIO_FUNC10_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func10_oe_sel(&self) -> REG_GPIO_FUNC10_OE_SEL_R { + REG_GPIO_FUNC10_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func10_out_inv_sel(&self) -> REG_GPIO_FUNC10_OUT_INV_SEL_R { + REG_GPIO_FUNC10_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func10_out_sel(&self) -> REG_GPIO_FUNC10_OUT_SEL_R { + REG_GPIO_FUNC10_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC10_OUT_SEL_CFG") + .field( + "reg_gpio_func10_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func10_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func10_oe_sel", + &format_args!("{}", self.reg_gpio_func10_oe_sel().bit()), + ) + .field( + "reg_gpio_func10_out_inv_sel", + &format_args!("{}", self.reg_gpio_func10_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func10_out_sel", + &format_args!("{}", self.reg_gpio_func10_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func10_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC10_OE_INV_SEL_W { + REG_GPIO_FUNC10_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func10_oe_sel(&mut self) -> REG_GPIO_FUNC10_OE_SEL_W { + REG_GPIO_FUNC10_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func10_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC10_OUT_INV_SEL_W { + REG_GPIO_FUNC10_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func10_out_sel( + &mut self, + ) -> REG_GPIO_FUNC10_OUT_SEL_W { + REG_GPIO_FUNC10_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func10_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func10_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC10_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC10_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func10_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC10_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func10_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC10_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC10_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC10_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func11_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func11_in_sel_cfg.rs new file mode 100644 index 0000000000..681133bc47 --- /dev/null +++ b/esp32p4/src/lp_gpio/func11_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC11_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC11_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC11_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC11_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC11_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC11_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG11_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG11_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG11_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG11_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC11_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC11_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC11_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC11_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func11_in_inv_sel(&self) -> REG_GPIO_FUNC11_IN_INV_SEL_R { + REG_GPIO_FUNC11_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig11_in_sel(&self) -> REG_GPIO_SIG11_IN_SEL_R { + REG_GPIO_SIG11_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func11_in_sel(&self) -> REG_GPIO_FUNC11_IN_SEL_R { + REG_GPIO_FUNC11_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC11_IN_SEL_CFG") + .field( + "reg_gpio_func11_in_inv_sel", + &format_args!("{}", self.reg_gpio_func11_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig11_in_sel", + &format_args!("{}", self.reg_gpio_sig11_in_sel().bit()), + ) + .field( + "reg_gpio_func11_in_sel", + &format_args!("{}", self.reg_gpio_func11_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func11_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC11_IN_INV_SEL_W { + REG_GPIO_FUNC11_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig11_in_sel(&mut self) -> REG_GPIO_SIG11_IN_SEL_W { + REG_GPIO_SIG11_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func11_in_sel(&mut self) -> REG_GPIO_FUNC11_IN_SEL_W { + REG_GPIO_FUNC11_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func11_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func11_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC11_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC11_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func11_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC11_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func11_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC11_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC11_IN_SEL_CFG to value 0x80"] +impl crate::Resettable for FUNC11_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/lp_gpio/func11_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func11_out_sel_cfg.rs new file mode 100644 index 0000000000..630d72e57f --- /dev/null +++ b/esp32p4/src/lp_gpio/func11_out_sel_cfg.rs @@ -0,0 +1,129 @@ +#[doc = "Register `FUNC11_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC11_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC11_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC11_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC11_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC11_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC11_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC11_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC11_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC11_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC11_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC11_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC11_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC11_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC11_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC11_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC11_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC11_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func11_oe_inv_sel(&self) -> REG_GPIO_FUNC11_OE_INV_SEL_R { + REG_GPIO_FUNC11_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func11_oe_sel(&self) -> REG_GPIO_FUNC11_OE_SEL_R { + REG_GPIO_FUNC11_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func11_out_inv_sel(&self) -> REG_GPIO_FUNC11_OUT_INV_SEL_R { + REG_GPIO_FUNC11_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func11_out_sel(&self) -> REG_GPIO_FUNC11_OUT_SEL_R { + REG_GPIO_FUNC11_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC11_OUT_SEL_CFG") + .field( + "reg_gpio_func11_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func11_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func11_oe_sel", + &format_args!("{}", self.reg_gpio_func11_oe_sel().bit()), + ) + .field( + "reg_gpio_func11_out_inv_sel", + &format_args!("{}", self.reg_gpio_func11_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func11_out_sel", + &format_args!("{}", self.reg_gpio_func11_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func11_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC11_OE_INV_SEL_W { + REG_GPIO_FUNC11_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func11_oe_sel(&mut self) -> REG_GPIO_FUNC11_OE_SEL_W { + REG_GPIO_FUNC11_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func11_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC11_OUT_INV_SEL_W { + REG_GPIO_FUNC11_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func11_out_sel( + &mut self, + ) -> REG_GPIO_FUNC11_OUT_SEL_W { + REG_GPIO_FUNC11_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func11_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func11_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC11_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC11_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func11_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC11_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func11_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC11_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC11_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC11_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func12_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func12_in_sel_cfg.rs new file mode 100644 index 0000000000..5c8f3bdf3f --- /dev/null +++ b/esp32p4/src/lp_gpio/func12_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC12_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC12_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC12_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC12_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC12_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC12_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG12_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG12_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG12_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG12_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC12_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC12_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC12_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC12_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func12_in_inv_sel(&self) -> REG_GPIO_FUNC12_IN_INV_SEL_R { + REG_GPIO_FUNC12_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig12_in_sel(&self) -> REG_GPIO_SIG12_IN_SEL_R { + REG_GPIO_SIG12_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func12_in_sel(&self) -> REG_GPIO_FUNC12_IN_SEL_R { + REG_GPIO_FUNC12_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC12_IN_SEL_CFG") + .field( + "reg_gpio_func12_in_inv_sel", + &format_args!("{}", self.reg_gpio_func12_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig12_in_sel", + &format_args!("{}", self.reg_gpio_sig12_in_sel().bit()), + ) + .field( + "reg_gpio_func12_in_sel", + &format_args!("{}", self.reg_gpio_func12_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func12_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC12_IN_INV_SEL_W { + REG_GPIO_FUNC12_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig12_in_sel(&mut self) -> REG_GPIO_SIG12_IN_SEL_W { + REG_GPIO_SIG12_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func12_in_sel(&mut self) -> REG_GPIO_FUNC12_IN_SEL_W { + REG_GPIO_FUNC12_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func12_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func12_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC12_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC12_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func12_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC12_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func12_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC12_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC12_IN_SEL_CFG to value 0x80"] +impl crate::Resettable for FUNC12_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/lp_gpio/func12_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func12_out_sel_cfg.rs new file mode 100644 index 0000000000..262902592e --- /dev/null +++ b/esp32p4/src/lp_gpio/func12_out_sel_cfg.rs @@ -0,0 +1,129 @@ +#[doc = "Register `FUNC12_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC12_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC12_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC12_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC12_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC12_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC12_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC12_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC12_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC12_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC12_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC12_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC12_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC12_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC12_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC12_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC12_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC12_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func12_oe_inv_sel(&self) -> REG_GPIO_FUNC12_OE_INV_SEL_R { + REG_GPIO_FUNC12_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func12_oe_sel(&self) -> REG_GPIO_FUNC12_OE_SEL_R { + REG_GPIO_FUNC12_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func12_out_inv_sel(&self) -> REG_GPIO_FUNC12_OUT_INV_SEL_R { + REG_GPIO_FUNC12_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func12_out_sel(&self) -> REG_GPIO_FUNC12_OUT_SEL_R { + REG_GPIO_FUNC12_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC12_OUT_SEL_CFG") + .field( + "reg_gpio_func12_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func12_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func12_oe_sel", + &format_args!("{}", self.reg_gpio_func12_oe_sel().bit()), + ) + .field( + "reg_gpio_func12_out_inv_sel", + &format_args!("{}", self.reg_gpio_func12_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func12_out_sel", + &format_args!("{}", self.reg_gpio_func12_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func12_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC12_OE_INV_SEL_W { + REG_GPIO_FUNC12_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func12_oe_sel(&mut self) -> REG_GPIO_FUNC12_OE_SEL_W { + REG_GPIO_FUNC12_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func12_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC12_OUT_INV_SEL_W { + REG_GPIO_FUNC12_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func12_out_sel( + &mut self, + ) -> REG_GPIO_FUNC12_OUT_SEL_W { + REG_GPIO_FUNC12_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func12_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func12_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC12_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC12_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func12_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC12_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func12_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC12_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC12_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC12_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func13_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func13_in_sel_cfg.rs new file mode 100644 index 0000000000..38b459dcc5 --- /dev/null +++ b/esp32p4/src/lp_gpio/func13_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC13_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC13_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC13_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC13_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC13_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC13_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG13_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG13_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG13_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG13_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC13_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC13_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC13_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC13_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func13_in_inv_sel(&self) -> REG_GPIO_FUNC13_IN_INV_SEL_R { + REG_GPIO_FUNC13_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig13_in_sel(&self) -> REG_GPIO_SIG13_IN_SEL_R { + REG_GPIO_SIG13_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func13_in_sel(&self) -> REG_GPIO_FUNC13_IN_SEL_R { + REG_GPIO_FUNC13_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC13_IN_SEL_CFG") + .field( + "reg_gpio_func13_in_inv_sel", + &format_args!("{}", self.reg_gpio_func13_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig13_in_sel", + &format_args!("{}", self.reg_gpio_sig13_in_sel().bit()), + ) + .field( + "reg_gpio_func13_in_sel", + &format_args!("{}", self.reg_gpio_func13_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func13_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC13_IN_INV_SEL_W { + REG_GPIO_FUNC13_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig13_in_sel(&mut self) -> REG_GPIO_SIG13_IN_SEL_W { + REG_GPIO_SIG13_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func13_in_sel(&mut self) -> REG_GPIO_FUNC13_IN_SEL_W { + REG_GPIO_FUNC13_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func13_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func13_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC13_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC13_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func13_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC13_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func13_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC13_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC13_IN_SEL_CFG to value 0x80"] +impl crate::Resettable for FUNC13_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/lp_gpio/func13_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func13_out_sel_cfg.rs new file mode 100644 index 0000000000..ab0adf351a --- /dev/null +++ b/esp32p4/src/lp_gpio/func13_out_sel_cfg.rs @@ -0,0 +1,129 @@ +#[doc = "Register `FUNC13_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC13_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC13_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC13_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC13_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC13_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC13_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC13_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC13_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC13_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC13_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC13_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC13_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC13_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC13_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC13_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC13_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC13_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func13_oe_inv_sel(&self) -> REG_GPIO_FUNC13_OE_INV_SEL_R { + REG_GPIO_FUNC13_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func13_oe_sel(&self) -> REG_GPIO_FUNC13_OE_SEL_R { + REG_GPIO_FUNC13_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func13_out_inv_sel(&self) -> REG_GPIO_FUNC13_OUT_INV_SEL_R { + REG_GPIO_FUNC13_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func13_out_sel(&self) -> REG_GPIO_FUNC13_OUT_SEL_R { + REG_GPIO_FUNC13_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC13_OUT_SEL_CFG") + .field( + "reg_gpio_func13_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func13_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func13_oe_sel", + &format_args!("{}", self.reg_gpio_func13_oe_sel().bit()), + ) + .field( + "reg_gpio_func13_out_inv_sel", + &format_args!("{}", self.reg_gpio_func13_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func13_out_sel", + &format_args!("{}", self.reg_gpio_func13_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func13_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC13_OE_INV_SEL_W { + REG_GPIO_FUNC13_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func13_oe_sel(&mut self) -> REG_GPIO_FUNC13_OE_SEL_W { + REG_GPIO_FUNC13_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func13_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC13_OUT_INV_SEL_W { + REG_GPIO_FUNC13_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func13_out_sel( + &mut self, + ) -> REG_GPIO_FUNC13_OUT_SEL_W { + REG_GPIO_FUNC13_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func13_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func13_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC13_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC13_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func13_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC13_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func13_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC13_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC13_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC13_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func14_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func14_out_sel_cfg.rs new file mode 100644 index 0000000000..e9a6885bed --- /dev/null +++ b/esp32p4/src/lp_gpio/func14_out_sel_cfg.rs @@ -0,0 +1,129 @@ +#[doc = "Register `FUNC14_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC14_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC14_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC14_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC14_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC14_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC14_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC14_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC14_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC14_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC14_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC14_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC14_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC14_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC14_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC14_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC14_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC14_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func14_oe_inv_sel(&self) -> REG_GPIO_FUNC14_OE_INV_SEL_R { + REG_GPIO_FUNC14_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func14_oe_sel(&self) -> REG_GPIO_FUNC14_OE_SEL_R { + REG_GPIO_FUNC14_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func14_out_inv_sel(&self) -> REG_GPIO_FUNC14_OUT_INV_SEL_R { + REG_GPIO_FUNC14_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func14_out_sel(&self) -> REG_GPIO_FUNC14_OUT_SEL_R { + REG_GPIO_FUNC14_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC14_OUT_SEL_CFG") + .field( + "reg_gpio_func14_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func14_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func14_oe_sel", + &format_args!("{}", self.reg_gpio_func14_oe_sel().bit()), + ) + .field( + "reg_gpio_func14_out_inv_sel", + &format_args!("{}", self.reg_gpio_func14_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func14_out_sel", + &format_args!("{}", self.reg_gpio_func14_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func14_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC14_OE_INV_SEL_W { + REG_GPIO_FUNC14_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func14_oe_sel(&mut self) -> REG_GPIO_FUNC14_OE_SEL_W { + REG_GPIO_FUNC14_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func14_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC14_OUT_INV_SEL_W { + REG_GPIO_FUNC14_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func14_out_sel( + &mut self, + ) -> REG_GPIO_FUNC14_OUT_SEL_W { + REG_GPIO_FUNC14_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func14_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func14_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC14_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC14_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func14_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC14_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func14_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC14_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC14_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC14_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func15_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func15_out_sel_cfg.rs new file mode 100644 index 0000000000..9b7154236e --- /dev/null +++ b/esp32p4/src/lp_gpio/func15_out_sel_cfg.rs @@ -0,0 +1,129 @@ +#[doc = "Register `FUNC15_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC15_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC15_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC15_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC15_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC15_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC15_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC15_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC15_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC15_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC15_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC15_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC15_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC15_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC15_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC15_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC15_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC15_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func15_oe_inv_sel(&self) -> REG_GPIO_FUNC15_OE_INV_SEL_R { + REG_GPIO_FUNC15_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func15_oe_sel(&self) -> REG_GPIO_FUNC15_OE_SEL_R { + REG_GPIO_FUNC15_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func15_out_inv_sel(&self) -> REG_GPIO_FUNC15_OUT_INV_SEL_R { + REG_GPIO_FUNC15_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func15_out_sel(&self) -> REG_GPIO_FUNC15_OUT_SEL_R { + REG_GPIO_FUNC15_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC15_OUT_SEL_CFG") + .field( + "reg_gpio_func15_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func15_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func15_oe_sel", + &format_args!("{}", self.reg_gpio_func15_oe_sel().bit()), + ) + .field( + "reg_gpio_func15_out_inv_sel", + &format_args!("{}", self.reg_gpio_func15_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func15_out_sel", + &format_args!("{}", self.reg_gpio_func15_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func15_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC15_OE_INV_SEL_W { + REG_GPIO_FUNC15_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func15_oe_sel(&mut self) -> REG_GPIO_FUNC15_OE_SEL_W { + REG_GPIO_FUNC15_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func15_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC15_OUT_INV_SEL_W { + REG_GPIO_FUNC15_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func15_out_sel( + &mut self, + ) -> REG_GPIO_FUNC15_OUT_SEL_W { + REG_GPIO_FUNC15_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func15_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func15_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC15_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC15_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func15_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC15_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func15_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC15_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC15_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC15_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func1_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func1_in_sel_cfg.rs new file mode 100644 index 0000000000..8b463165ad --- /dev/null +++ b/esp32p4/src/lp_gpio/func1_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC1_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC1_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC1_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC1_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC1_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC1_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG1_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG1_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG1_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG1_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC1_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC1_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC1_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC1_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func1_in_inv_sel(&self) -> REG_GPIO_FUNC1_IN_INV_SEL_R { + REG_GPIO_FUNC1_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig1_in_sel(&self) -> REG_GPIO_SIG1_IN_SEL_R { + REG_GPIO_SIG1_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func1_in_sel(&self) -> REG_GPIO_FUNC1_IN_SEL_R { + REG_GPIO_FUNC1_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC1_IN_SEL_CFG") + .field( + "reg_gpio_func1_in_inv_sel", + &format_args!("{}", self.reg_gpio_func1_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig1_in_sel", + &format_args!("{}", self.reg_gpio_sig1_in_sel().bit()), + ) + .field( + "reg_gpio_func1_in_sel", + &format_args!("{}", self.reg_gpio_func1_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func1_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC1_IN_INV_SEL_W { + REG_GPIO_FUNC1_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig1_in_sel(&mut self) -> REG_GPIO_SIG1_IN_SEL_W { + REG_GPIO_SIG1_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func1_in_sel(&mut self) -> REG_GPIO_FUNC1_IN_SEL_W { + REG_GPIO_FUNC1_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func1_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func1_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC1_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC1_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func1_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC1_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func1_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC1_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC1_IN_SEL_CFG to value 0xc0"] +impl crate::Resettable for FUNC1_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0xc0; +} diff --git a/esp32p4/src/lp_gpio/func1_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func1_out_sel_cfg.rs new file mode 100644 index 0000000000..7bd7781e04 --- /dev/null +++ b/esp32p4/src/lp_gpio/func1_out_sel_cfg.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FUNC1_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC1_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC1_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC1_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC1_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC1_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC1_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC1_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC1_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC1_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC1_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC1_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC1_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC1_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC1_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC1_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC1_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC1_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func1_oe_inv_sel(&self) -> REG_GPIO_FUNC1_OE_INV_SEL_R { + REG_GPIO_FUNC1_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func1_oe_sel(&self) -> REG_GPIO_FUNC1_OE_SEL_R { + REG_GPIO_FUNC1_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func1_out_inv_sel(&self) -> REG_GPIO_FUNC1_OUT_INV_SEL_R { + REG_GPIO_FUNC1_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func1_out_sel(&self) -> REG_GPIO_FUNC1_OUT_SEL_R { + REG_GPIO_FUNC1_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC1_OUT_SEL_CFG") + .field( + "reg_gpio_func1_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func1_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func1_oe_sel", + &format_args!("{}", self.reg_gpio_func1_oe_sel().bit()), + ) + .field( + "reg_gpio_func1_out_inv_sel", + &format_args!("{}", self.reg_gpio_func1_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func1_out_sel", + &format_args!("{}", self.reg_gpio_func1_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func1_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC1_OE_INV_SEL_W { + REG_GPIO_FUNC1_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func1_oe_sel(&mut self) -> REG_GPIO_FUNC1_OE_SEL_W { + REG_GPIO_FUNC1_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func1_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC1_OUT_INV_SEL_W { + REG_GPIO_FUNC1_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func1_out_sel(&mut self) -> REG_GPIO_FUNC1_OUT_SEL_W { + REG_GPIO_FUNC1_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func1_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func1_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC1_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC1_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func1_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC1_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func1_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC1_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC1_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC1_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func2_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func2_in_sel_cfg.rs new file mode 100644 index 0000000000..e5ac671193 --- /dev/null +++ b/esp32p4/src/lp_gpio/func2_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC2_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC2_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC2_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC2_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC2_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC2_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG2_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG2_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG2_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG2_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC2_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC2_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC2_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC2_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func2_in_inv_sel(&self) -> REG_GPIO_FUNC2_IN_INV_SEL_R { + REG_GPIO_FUNC2_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig2_in_sel(&self) -> REG_GPIO_SIG2_IN_SEL_R { + REG_GPIO_SIG2_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func2_in_sel(&self) -> REG_GPIO_FUNC2_IN_SEL_R { + REG_GPIO_FUNC2_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC2_IN_SEL_CFG") + .field( + "reg_gpio_func2_in_inv_sel", + &format_args!("{}", self.reg_gpio_func2_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig2_in_sel", + &format_args!("{}", self.reg_gpio_sig2_in_sel().bit()), + ) + .field( + "reg_gpio_func2_in_sel", + &format_args!("{}", self.reg_gpio_func2_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func2_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC2_IN_INV_SEL_W { + REG_GPIO_FUNC2_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig2_in_sel(&mut self) -> REG_GPIO_SIG2_IN_SEL_W { + REG_GPIO_SIG2_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func2_in_sel(&mut self) -> REG_GPIO_FUNC2_IN_SEL_W { + REG_GPIO_FUNC2_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func2_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func2_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC2_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC2_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func2_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC2_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func2_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC2_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC2_IN_SEL_CFG to value 0x80"] +impl crate::Resettable for FUNC2_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/lp_gpio/func2_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func2_out_sel_cfg.rs new file mode 100644 index 0000000000..cc9e404199 --- /dev/null +++ b/esp32p4/src/lp_gpio/func2_out_sel_cfg.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FUNC2_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC2_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC2_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC2_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC2_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC2_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC2_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC2_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC2_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC2_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC2_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC2_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC2_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC2_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC2_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC2_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC2_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC2_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func2_oe_inv_sel(&self) -> REG_GPIO_FUNC2_OE_INV_SEL_R { + REG_GPIO_FUNC2_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func2_oe_sel(&self) -> REG_GPIO_FUNC2_OE_SEL_R { + REG_GPIO_FUNC2_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func2_out_inv_sel(&self) -> REG_GPIO_FUNC2_OUT_INV_SEL_R { + REG_GPIO_FUNC2_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func2_out_sel(&self) -> REG_GPIO_FUNC2_OUT_SEL_R { + REG_GPIO_FUNC2_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC2_OUT_SEL_CFG") + .field( + "reg_gpio_func2_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func2_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func2_oe_sel", + &format_args!("{}", self.reg_gpio_func2_oe_sel().bit()), + ) + .field( + "reg_gpio_func2_out_inv_sel", + &format_args!("{}", self.reg_gpio_func2_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func2_out_sel", + &format_args!("{}", self.reg_gpio_func2_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func2_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC2_OE_INV_SEL_W { + REG_GPIO_FUNC2_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func2_oe_sel(&mut self) -> REG_GPIO_FUNC2_OE_SEL_W { + REG_GPIO_FUNC2_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func2_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC2_OUT_INV_SEL_W { + REG_GPIO_FUNC2_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func2_out_sel(&mut self) -> REG_GPIO_FUNC2_OUT_SEL_W { + REG_GPIO_FUNC2_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func2_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func2_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC2_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC2_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func2_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC2_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func2_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC2_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC2_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC2_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func3_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func3_in_sel_cfg.rs new file mode 100644 index 0000000000..81b8d3407d --- /dev/null +++ b/esp32p4/src/lp_gpio/func3_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC3_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC3_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC3_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC3_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC3_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC3_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG3_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG3_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG3_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG3_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC3_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC3_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC3_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC3_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func3_in_inv_sel(&self) -> REG_GPIO_FUNC3_IN_INV_SEL_R { + REG_GPIO_FUNC3_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig3_in_sel(&self) -> REG_GPIO_SIG3_IN_SEL_R { + REG_GPIO_SIG3_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func3_in_sel(&self) -> REG_GPIO_FUNC3_IN_SEL_R { + REG_GPIO_FUNC3_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC3_IN_SEL_CFG") + .field( + "reg_gpio_func3_in_inv_sel", + &format_args!("{}", self.reg_gpio_func3_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig3_in_sel", + &format_args!("{}", self.reg_gpio_sig3_in_sel().bit()), + ) + .field( + "reg_gpio_func3_in_sel", + &format_args!("{}", self.reg_gpio_func3_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func3_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC3_IN_INV_SEL_W { + REG_GPIO_FUNC3_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig3_in_sel(&mut self) -> REG_GPIO_SIG3_IN_SEL_W { + REG_GPIO_SIG3_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func3_in_sel(&mut self) -> REG_GPIO_FUNC3_IN_SEL_W { + REG_GPIO_FUNC3_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func3_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func3_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC3_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC3_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func3_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC3_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func3_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC3_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC3_IN_SEL_CFG to value 0xc0"] +impl crate::Resettable for FUNC3_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0xc0; +} diff --git a/esp32p4/src/lp_gpio/func3_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func3_out_sel_cfg.rs new file mode 100644 index 0000000000..4326805852 --- /dev/null +++ b/esp32p4/src/lp_gpio/func3_out_sel_cfg.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FUNC3_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC3_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC3_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC3_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC3_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC3_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC3_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC3_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC3_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC3_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC3_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC3_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC3_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC3_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC3_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC3_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC3_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC3_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func3_oe_inv_sel(&self) -> REG_GPIO_FUNC3_OE_INV_SEL_R { + REG_GPIO_FUNC3_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func3_oe_sel(&self) -> REG_GPIO_FUNC3_OE_SEL_R { + REG_GPIO_FUNC3_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func3_out_inv_sel(&self) -> REG_GPIO_FUNC3_OUT_INV_SEL_R { + REG_GPIO_FUNC3_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func3_out_sel(&self) -> REG_GPIO_FUNC3_OUT_SEL_R { + REG_GPIO_FUNC3_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC3_OUT_SEL_CFG") + .field( + "reg_gpio_func3_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func3_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func3_oe_sel", + &format_args!("{}", self.reg_gpio_func3_oe_sel().bit()), + ) + .field( + "reg_gpio_func3_out_inv_sel", + &format_args!("{}", self.reg_gpio_func3_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func3_out_sel", + &format_args!("{}", self.reg_gpio_func3_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func3_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC3_OE_INV_SEL_W { + REG_GPIO_FUNC3_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func3_oe_sel(&mut self) -> REG_GPIO_FUNC3_OE_SEL_W { + REG_GPIO_FUNC3_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func3_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC3_OUT_INV_SEL_W { + REG_GPIO_FUNC3_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func3_out_sel(&mut self) -> REG_GPIO_FUNC3_OUT_SEL_W { + REG_GPIO_FUNC3_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func3_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func3_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC3_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC3_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func3_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC3_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func3_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC3_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC3_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC3_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func4_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func4_in_sel_cfg.rs new file mode 100644 index 0000000000..7289881aef --- /dev/null +++ b/esp32p4/src/lp_gpio/func4_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC4_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC4_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC4_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC4_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC4_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC4_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG4_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG4_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG4_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG4_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC4_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC4_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC4_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC4_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func4_in_inv_sel(&self) -> REG_GPIO_FUNC4_IN_INV_SEL_R { + REG_GPIO_FUNC4_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig4_in_sel(&self) -> REG_GPIO_SIG4_IN_SEL_R { + REG_GPIO_SIG4_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func4_in_sel(&self) -> REG_GPIO_FUNC4_IN_SEL_R { + REG_GPIO_FUNC4_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC4_IN_SEL_CFG") + .field( + "reg_gpio_func4_in_inv_sel", + &format_args!("{}", self.reg_gpio_func4_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig4_in_sel", + &format_args!("{}", self.reg_gpio_sig4_in_sel().bit()), + ) + .field( + "reg_gpio_func4_in_sel", + &format_args!("{}", self.reg_gpio_func4_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func4_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC4_IN_INV_SEL_W { + REG_GPIO_FUNC4_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig4_in_sel(&mut self) -> REG_GPIO_SIG4_IN_SEL_W { + REG_GPIO_SIG4_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func4_in_sel(&mut self) -> REG_GPIO_FUNC4_IN_SEL_W { + REG_GPIO_FUNC4_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func4_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func4_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC4_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC4_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func4_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC4_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func4_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC4_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC4_IN_SEL_CFG to value 0xc0"] +impl crate::Resettable for FUNC4_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0xc0; +} diff --git a/esp32p4/src/lp_gpio/func4_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func4_out_sel_cfg.rs new file mode 100644 index 0000000000..206bf70694 --- /dev/null +++ b/esp32p4/src/lp_gpio/func4_out_sel_cfg.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FUNC4_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC4_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC4_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC4_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC4_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC4_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC4_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC4_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC4_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC4_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC4_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC4_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC4_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC4_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC4_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC4_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC4_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC4_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func4_oe_inv_sel(&self) -> REG_GPIO_FUNC4_OE_INV_SEL_R { + REG_GPIO_FUNC4_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func4_oe_sel(&self) -> REG_GPIO_FUNC4_OE_SEL_R { + REG_GPIO_FUNC4_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func4_out_inv_sel(&self) -> REG_GPIO_FUNC4_OUT_INV_SEL_R { + REG_GPIO_FUNC4_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func4_out_sel(&self) -> REG_GPIO_FUNC4_OUT_SEL_R { + REG_GPIO_FUNC4_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC4_OUT_SEL_CFG") + .field( + "reg_gpio_func4_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func4_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func4_oe_sel", + &format_args!("{}", self.reg_gpio_func4_oe_sel().bit()), + ) + .field( + "reg_gpio_func4_out_inv_sel", + &format_args!("{}", self.reg_gpio_func4_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func4_out_sel", + &format_args!("{}", self.reg_gpio_func4_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func4_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC4_OE_INV_SEL_W { + REG_GPIO_FUNC4_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func4_oe_sel(&mut self) -> REG_GPIO_FUNC4_OE_SEL_W { + REG_GPIO_FUNC4_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func4_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC4_OUT_INV_SEL_W { + REG_GPIO_FUNC4_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func4_out_sel(&mut self) -> REG_GPIO_FUNC4_OUT_SEL_W { + REG_GPIO_FUNC4_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func4_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func4_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC4_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC4_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func4_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC4_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func4_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC4_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC4_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC4_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func5_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func5_in_sel_cfg.rs new file mode 100644 index 0000000000..2282d24e58 --- /dev/null +++ b/esp32p4/src/lp_gpio/func5_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC5_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC5_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC5_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC5_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC5_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC5_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG5_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG5_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG5_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG5_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC5_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC5_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC5_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC5_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func5_in_inv_sel(&self) -> REG_GPIO_FUNC5_IN_INV_SEL_R { + REG_GPIO_FUNC5_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig5_in_sel(&self) -> REG_GPIO_SIG5_IN_SEL_R { + REG_GPIO_SIG5_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func5_in_sel(&self) -> REG_GPIO_FUNC5_IN_SEL_R { + REG_GPIO_FUNC5_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC5_IN_SEL_CFG") + .field( + "reg_gpio_func5_in_inv_sel", + &format_args!("{}", self.reg_gpio_func5_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig5_in_sel", + &format_args!("{}", self.reg_gpio_sig5_in_sel().bit()), + ) + .field( + "reg_gpio_func5_in_sel", + &format_args!("{}", self.reg_gpio_func5_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func5_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC5_IN_INV_SEL_W { + REG_GPIO_FUNC5_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig5_in_sel(&mut self) -> REG_GPIO_SIG5_IN_SEL_W { + REG_GPIO_SIG5_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func5_in_sel(&mut self) -> REG_GPIO_FUNC5_IN_SEL_W { + REG_GPIO_FUNC5_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func5_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func5_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC5_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC5_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func5_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC5_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func5_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC5_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC5_IN_SEL_CFG to value 0x80"] +impl crate::Resettable for FUNC5_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/lp_gpio/func5_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func5_out_sel_cfg.rs new file mode 100644 index 0000000000..e5b002ed93 --- /dev/null +++ b/esp32p4/src/lp_gpio/func5_out_sel_cfg.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FUNC5_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC5_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC5_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC5_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC5_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC5_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC5_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC5_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC5_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC5_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC5_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC5_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC5_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC5_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC5_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC5_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC5_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC5_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func5_oe_inv_sel(&self) -> REG_GPIO_FUNC5_OE_INV_SEL_R { + REG_GPIO_FUNC5_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func5_oe_sel(&self) -> REG_GPIO_FUNC5_OE_SEL_R { + REG_GPIO_FUNC5_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func5_out_inv_sel(&self) -> REG_GPIO_FUNC5_OUT_INV_SEL_R { + REG_GPIO_FUNC5_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func5_out_sel(&self) -> REG_GPIO_FUNC5_OUT_SEL_R { + REG_GPIO_FUNC5_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC5_OUT_SEL_CFG") + .field( + "reg_gpio_func5_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func5_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func5_oe_sel", + &format_args!("{}", self.reg_gpio_func5_oe_sel().bit()), + ) + .field( + "reg_gpio_func5_out_inv_sel", + &format_args!("{}", self.reg_gpio_func5_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func5_out_sel", + &format_args!("{}", self.reg_gpio_func5_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func5_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC5_OE_INV_SEL_W { + REG_GPIO_FUNC5_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func5_oe_sel(&mut self) -> REG_GPIO_FUNC5_OE_SEL_W { + REG_GPIO_FUNC5_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func5_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC5_OUT_INV_SEL_W { + REG_GPIO_FUNC5_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func5_out_sel(&mut self) -> REG_GPIO_FUNC5_OUT_SEL_W { + REG_GPIO_FUNC5_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func5_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func5_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC5_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC5_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func5_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC5_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func5_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC5_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC5_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC5_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func6_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func6_in_sel_cfg.rs new file mode 100644 index 0000000000..8708424f05 --- /dev/null +++ b/esp32p4/src/lp_gpio/func6_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC6_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC6_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC6_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC6_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC6_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC6_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG6_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG6_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG6_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG6_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC6_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC6_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC6_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC6_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func6_in_inv_sel(&self) -> REG_GPIO_FUNC6_IN_INV_SEL_R { + REG_GPIO_FUNC6_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig6_in_sel(&self) -> REG_GPIO_SIG6_IN_SEL_R { + REG_GPIO_SIG6_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func6_in_sel(&self) -> REG_GPIO_FUNC6_IN_SEL_R { + REG_GPIO_FUNC6_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC6_IN_SEL_CFG") + .field( + "reg_gpio_func6_in_inv_sel", + &format_args!("{}", self.reg_gpio_func6_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig6_in_sel", + &format_args!("{}", self.reg_gpio_sig6_in_sel().bit()), + ) + .field( + "reg_gpio_func6_in_sel", + &format_args!("{}", self.reg_gpio_func6_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func6_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC6_IN_INV_SEL_W { + REG_GPIO_FUNC6_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig6_in_sel(&mut self) -> REG_GPIO_SIG6_IN_SEL_W { + REG_GPIO_SIG6_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func6_in_sel(&mut self) -> REG_GPIO_FUNC6_IN_SEL_W { + REG_GPIO_FUNC6_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func6_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func6_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC6_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC6_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func6_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC6_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func6_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC6_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC6_IN_SEL_CFG to value 0x80"] +impl crate::Resettable for FUNC6_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/lp_gpio/func6_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func6_out_sel_cfg.rs new file mode 100644 index 0000000000..305af69560 --- /dev/null +++ b/esp32p4/src/lp_gpio/func6_out_sel_cfg.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FUNC6_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC6_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC6_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC6_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC6_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC6_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC6_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC6_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC6_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC6_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC6_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC6_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC6_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC6_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC6_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC6_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC6_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC6_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func6_oe_inv_sel(&self) -> REG_GPIO_FUNC6_OE_INV_SEL_R { + REG_GPIO_FUNC6_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func6_oe_sel(&self) -> REG_GPIO_FUNC6_OE_SEL_R { + REG_GPIO_FUNC6_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func6_out_inv_sel(&self) -> REG_GPIO_FUNC6_OUT_INV_SEL_R { + REG_GPIO_FUNC6_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func6_out_sel(&self) -> REG_GPIO_FUNC6_OUT_SEL_R { + REG_GPIO_FUNC6_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC6_OUT_SEL_CFG") + .field( + "reg_gpio_func6_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func6_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func6_oe_sel", + &format_args!("{}", self.reg_gpio_func6_oe_sel().bit()), + ) + .field( + "reg_gpio_func6_out_inv_sel", + &format_args!("{}", self.reg_gpio_func6_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func6_out_sel", + &format_args!("{}", self.reg_gpio_func6_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func6_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC6_OE_INV_SEL_W { + REG_GPIO_FUNC6_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func6_oe_sel(&mut self) -> REG_GPIO_FUNC6_OE_SEL_W { + REG_GPIO_FUNC6_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func6_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC6_OUT_INV_SEL_W { + REG_GPIO_FUNC6_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func6_out_sel(&mut self) -> REG_GPIO_FUNC6_OUT_SEL_W { + REG_GPIO_FUNC6_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func6_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func6_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC6_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC6_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func6_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC6_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func6_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC6_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC6_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC6_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func7_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func7_in_sel_cfg.rs new file mode 100644 index 0000000000..ec14425a1d --- /dev/null +++ b/esp32p4/src/lp_gpio/func7_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC7_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC7_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC7_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC7_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC7_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC7_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG7_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG7_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG7_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG7_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC7_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC7_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC7_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC7_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func7_in_inv_sel(&self) -> REG_GPIO_FUNC7_IN_INV_SEL_R { + REG_GPIO_FUNC7_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig7_in_sel(&self) -> REG_GPIO_SIG7_IN_SEL_R { + REG_GPIO_SIG7_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func7_in_sel(&self) -> REG_GPIO_FUNC7_IN_SEL_R { + REG_GPIO_FUNC7_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC7_IN_SEL_CFG") + .field( + "reg_gpio_func7_in_inv_sel", + &format_args!("{}", self.reg_gpio_func7_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig7_in_sel", + &format_args!("{}", self.reg_gpio_sig7_in_sel().bit()), + ) + .field( + "reg_gpio_func7_in_sel", + &format_args!("{}", self.reg_gpio_func7_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func7_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC7_IN_INV_SEL_W { + REG_GPIO_FUNC7_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig7_in_sel(&mut self) -> REG_GPIO_SIG7_IN_SEL_W { + REG_GPIO_SIG7_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func7_in_sel(&mut self) -> REG_GPIO_FUNC7_IN_SEL_W { + REG_GPIO_FUNC7_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func7_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func7_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC7_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC7_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func7_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC7_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func7_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC7_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC7_IN_SEL_CFG to value 0x80"] +impl crate::Resettable for FUNC7_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/lp_gpio/func7_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func7_out_sel_cfg.rs new file mode 100644 index 0000000000..40524e70a1 --- /dev/null +++ b/esp32p4/src/lp_gpio/func7_out_sel_cfg.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FUNC7_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC7_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC7_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC7_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC7_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC7_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC7_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC7_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC7_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC7_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC7_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC7_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC7_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC7_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC7_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC7_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC7_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC7_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func7_oe_inv_sel(&self) -> REG_GPIO_FUNC7_OE_INV_SEL_R { + REG_GPIO_FUNC7_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func7_oe_sel(&self) -> REG_GPIO_FUNC7_OE_SEL_R { + REG_GPIO_FUNC7_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func7_out_inv_sel(&self) -> REG_GPIO_FUNC7_OUT_INV_SEL_R { + REG_GPIO_FUNC7_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func7_out_sel(&self) -> REG_GPIO_FUNC7_OUT_SEL_R { + REG_GPIO_FUNC7_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC7_OUT_SEL_CFG") + .field( + "reg_gpio_func7_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func7_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func7_oe_sel", + &format_args!("{}", self.reg_gpio_func7_oe_sel().bit()), + ) + .field( + "reg_gpio_func7_out_inv_sel", + &format_args!("{}", self.reg_gpio_func7_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func7_out_sel", + &format_args!("{}", self.reg_gpio_func7_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func7_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC7_OE_INV_SEL_W { + REG_GPIO_FUNC7_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func7_oe_sel(&mut self) -> REG_GPIO_FUNC7_OE_SEL_W { + REG_GPIO_FUNC7_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func7_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC7_OUT_INV_SEL_W { + REG_GPIO_FUNC7_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func7_out_sel(&mut self) -> REG_GPIO_FUNC7_OUT_SEL_W { + REG_GPIO_FUNC7_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func7_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func7_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC7_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC7_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func7_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC7_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func7_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC7_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC7_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC7_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func8_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func8_in_sel_cfg.rs new file mode 100644 index 0000000000..1c4c152765 --- /dev/null +++ b/esp32p4/src/lp_gpio/func8_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC8_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC8_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC8_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC8_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC8_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC8_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG8_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG8_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG8_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG8_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC8_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC8_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC8_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC8_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func8_in_inv_sel(&self) -> REG_GPIO_FUNC8_IN_INV_SEL_R { + REG_GPIO_FUNC8_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig8_in_sel(&self) -> REG_GPIO_SIG8_IN_SEL_R { + REG_GPIO_SIG8_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func8_in_sel(&self) -> REG_GPIO_FUNC8_IN_SEL_R { + REG_GPIO_FUNC8_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC8_IN_SEL_CFG") + .field( + "reg_gpio_func8_in_inv_sel", + &format_args!("{}", self.reg_gpio_func8_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig8_in_sel", + &format_args!("{}", self.reg_gpio_sig8_in_sel().bit()), + ) + .field( + "reg_gpio_func8_in_sel", + &format_args!("{}", self.reg_gpio_func8_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func8_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC8_IN_INV_SEL_W { + REG_GPIO_FUNC8_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig8_in_sel(&mut self) -> REG_GPIO_SIG8_IN_SEL_W { + REG_GPIO_SIG8_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func8_in_sel(&mut self) -> REG_GPIO_FUNC8_IN_SEL_W { + REG_GPIO_FUNC8_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func8_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func8_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC8_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC8_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func8_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC8_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func8_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC8_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC8_IN_SEL_CFG to value 0x80"] +impl crate::Resettable for FUNC8_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/lp_gpio/func8_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func8_out_sel_cfg.rs new file mode 100644 index 0000000000..6d16068eaa --- /dev/null +++ b/esp32p4/src/lp_gpio/func8_out_sel_cfg.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FUNC8_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC8_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC8_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC8_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC8_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC8_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC8_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC8_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC8_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC8_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC8_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC8_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC8_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC8_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC8_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC8_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC8_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC8_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func8_oe_inv_sel(&self) -> REG_GPIO_FUNC8_OE_INV_SEL_R { + REG_GPIO_FUNC8_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func8_oe_sel(&self) -> REG_GPIO_FUNC8_OE_SEL_R { + REG_GPIO_FUNC8_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func8_out_inv_sel(&self) -> REG_GPIO_FUNC8_OUT_INV_SEL_R { + REG_GPIO_FUNC8_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func8_out_sel(&self) -> REG_GPIO_FUNC8_OUT_SEL_R { + REG_GPIO_FUNC8_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC8_OUT_SEL_CFG") + .field( + "reg_gpio_func8_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func8_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func8_oe_sel", + &format_args!("{}", self.reg_gpio_func8_oe_sel().bit()), + ) + .field( + "reg_gpio_func8_out_inv_sel", + &format_args!("{}", self.reg_gpio_func8_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func8_out_sel", + &format_args!("{}", self.reg_gpio_func8_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func8_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC8_OE_INV_SEL_W { + REG_GPIO_FUNC8_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func8_oe_sel(&mut self) -> REG_GPIO_FUNC8_OE_SEL_W { + REG_GPIO_FUNC8_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func8_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC8_OUT_INV_SEL_W { + REG_GPIO_FUNC8_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func8_out_sel(&mut self) -> REG_GPIO_FUNC8_OUT_SEL_W { + REG_GPIO_FUNC8_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func8_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func8_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC8_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC8_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func8_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC8_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func8_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC8_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC8_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC8_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/func9_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func9_in_sel_cfg.rs new file mode 100644 index 0000000000..dcf1d9b871 --- /dev/null +++ b/esp32p4/src/lp_gpio/func9_in_sel_cfg.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FUNC9_IN_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC9_IN_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC9_IN_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC9_IN_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC9_IN_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC9_IN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_SIG9_IN_SEL` reader - Reserved"] +pub type REG_GPIO_SIG9_IN_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_SIG9_IN_SEL` writer - Reserved"] +pub type REG_GPIO_SIG9_IN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC9_IN_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC9_IN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC9_IN_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC9_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func9_in_inv_sel(&self) -> REG_GPIO_FUNC9_IN_INV_SEL_R { + REG_GPIO_FUNC9_IN_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_sig9_in_sel(&self) -> REG_GPIO_SIG9_IN_SEL_R { + REG_GPIO_SIG9_IN_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func9_in_sel(&self) -> REG_GPIO_FUNC9_IN_SEL_R { + REG_GPIO_FUNC9_IN_SEL_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC9_IN_SEL_CFG") + .field( + "reg_gpio_func9_in_inv_sel", + &format_args!("{}", self.reg_gpio_func9_in_inv_sel().bit()), + ) + .field( + "reg_gpio_sig9_in_sel", + &format_args!("{}", self.reg_gpio_sig9_in_sel().bit()), + ) + .field( + "reg_gpio_func9_in_sel", + &format_args!("{}", self.reg_gpio_func9_in_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func9_in_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC9_IN_INV_SEL_W { + REG_GPIO_FUNC9_IN_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_sig9_in_sel(&mut self) -> REG_GPIO_SIG9_IN_SEL_W { + REG_GPIO_SIG9_IN_SEL_W::new(self, 1) + } + #[doc = "Bits 2:7 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func9_in_sel(&mut self) -> REG_GPIO_FUNC9_IN_SEL_W { + REG_GPIO_FUNC9_IN_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func9_in_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func9_in_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC9_IN_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC9_IN_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func9_in_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC9_IN_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func9_in_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC9_IN_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC9_IN_SEL_CFG to value 0x80"] +impl crate::Resettable for FUNC9_IN_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/lp_gpio/func9_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func9_out_sel_cfg.rs new file mode 100644 index 0000000000..9856c72e39 --- /dev/null +++ b/esp32p4/src/lp_gpio/func9_out_sel_cfg.rs @@ -0,0 +1,127 @@ +#[doc = "Register `FUNC9_OUT_SEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FUNC9_OUT_SEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_FUNC9_OE_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC9_OE_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC9_OE_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC9_OE_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC9_OE_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC9_OE_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC9_OE_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC9_OE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC9_OUT_INV_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC9_OUT_INV_SEL_R = crate::BitReader; +#[doc = "Field `REG_GPIO_FUNC9_OUT_INV_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC9_OUT_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_FUNC9_OUT_SEL` reader - Reserved"] +pub type REG_GPIO_FUNC9_OUT_SEL_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_FUNC9_OUT_SEL` writer - Reserved"] +pub type REG_GPIO_FUNC9_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func9_oe_inv_sel(&self) -> REG_GPIO_FUNC9_OE_INV_SEL_R { + REG_GPIO_FUNC9_OE_INV_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func9_oe_sel(&self) -> REG_GPIO_FUNC9_OE_SEL_R { + REG_GPIO_FUNC9_OE_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func9_out_inv_sel(&self) -> REG_GPIO_FUNC9_OUT_INV_SEL_R { + REG_GPIO_FUNC9_OUT_INV_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + pub fn reg_gpio_func9_out_sel(&self) -> REG_GPIO_FUNC9_OUT_SEL_R { + REG_GPIO_FUNC9_OUT_SEL_R::new(((self.bits >> 3) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FUNC9_OUT_SEL_CFG") + .field( + "reg_gpio_func9_oe_inv_sel", + &format_args!("{}", self.reg_gpio_func9_oe_inv_sel().bit()), + ) + .field( + "reg_gpio_func9_oe_sel", + &format_args!("{}", self.reg_gpio_func9_oe_sel().bit()), + ) + .field( + "reg_gpio_func9_out_inv_sel", + &format_args!("{}", self.reg_gpio_func9_out_inv_sel().bit()), + ) + .field( + "reg_gpio_func9_out_sel", + &format_args!("{}", self.reg_gpio_func9_out_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func9_oe_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC9_OE_INV_SEL_W { + REG_GPIO_FUNC9_OE_INV_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func9_oe_sel(&mut self) -> REG_GPIO_FUNC9_OE_SEL_W { + REG_GPIO_FUNC9_OE_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func9_out_inv_sel( + &mut self, + ) -> REG_GPIO_FUNC9_OUT_INV_SEL_W { + REG_GPIO_FUNC9_OUT_INV_SEL_W::new(self, 2) + } + #[doc = "Bits 3:8 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_func9_out_sel(&mut self) -> REG_GPIO_FUNC9_OUT_SEL_W { + REG_GPIO_FUNC9_OUT_SEL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func9_out_sel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func9_out_sel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FUNC9_OUT_SEL_CFG_SPEC; +impl crate::RegisterSpec for FUNC9_OUT_SEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`func9_out_sel_cfg::R`](R) reader structure"] +impl crate::Readable for FUNC9_OUT_SEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`func9_out_sel_cfg::W`](W) writer structure"] +impl crate::Writable for FUNC9_OUT_SEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FUNC9_OUT_SEL_CFG to value 0x0100"] +impl crate::Resettable for FUNC9_OUT_SEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0100; +} diff --git a/esp32p4/src/lp_gpio/in_.rs b/esp32p4/src/lp_gpio/in_.rs new file mode 100644 index 0000000000..c692fedeb2 --- /dev/null +++ b/esp32p4/src/lp_gpio/in_.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IN` reader"] +pub type R = crate::R; +#[doc = "Field `REG_GPIO_IN_DATA_NEXT` reader - Reserved"] +pub type REG_GPIO_IN_DATA_NEXT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + pub fn reg_gpio_in_data_next(&self) -> REG_GPIO_IN_DATA_NEXT_R { + REG_GPIO_IN_DATA_NEXT_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN") + .field( + "reg_gpio_in_data_next", + &format_args!("{}", self.reg_gpio_in_data_next().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_::R`](R) reader structure"] +impl crate::Readable for IN_SPEC {} +#[doc = "`reset()` method sets IN to value 0"] +impl crate::Resettable for IN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/out.rs b/esp32p4/src/lp_gpio/out.rs new file mode 100644 index 0000000000..f4d2d0db15 --- /dev/null +++ b/esp32p4/src/lp_gpio/out.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OUT` reader"] +pub type R = crate::R; +#[doc = "Register `OUT` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_OUT_DATA` reader - Reserved"] +pub type REG_GPIO_OUT_DATA_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_OUT_DATA` writer - Reserved"] +pub type REG_GPIO_OUT_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + pub fn reg_gpio_out_data(&self) -> REG_GPIO_OUT_DATA_R { + REG_GPIO_OUT_DATA_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT") + .field( + "reg_gpio_out_data", + &format_args!("{}", self.reg_gpio_out_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_out_data(&mut self) -> REG_GPIO_OUT_DATA_W { + REG_GPIO_OUT_DATA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out::R`](R) reader structure"] +impl crate::Readable for OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`out::W`](W) writer structure"] +impl crate::Writable for OUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT to value 0"] +impl crate::Resettable for OUT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/out_w1tc.rs b/esp32p4/src/lp_gpio/out_w1tc.rs new file mode 100644 index 0000000000..1cc952a576 --- /dev/null +++ b/esp32p4/src/lp_gpio/out_w1tc.rs @@ -0,0 +1,42 @@ +#[doc = "Register `OUT_W1TC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_OUT_DATA_W1TC` writer - Reserved"] +pub type REG_GPIO_OUT_DATA_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_out_data_w1tc(&mut self) -> REG_GPIO_OUT_DATA_W1TC_W { + REG_GPIO_OUT_DATA_W1TC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_W1TC_SPEC; +impl crate::RegisterSpec for OUT_W1TC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out_w1tc::W`](W) writer structure"] +impl crate::Writable for OUT_W1TC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_W1TC to value 0"] +impl crate::Resettable for OUT_W1TC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/out_w1ts.rs b/esp32p4/src/lp_gpio/out_w1ts.rs new file mode 100644 index 0000000000..3e74616675 --- /dev/null +++ b/esp32p4/src/lp_gpio/out_w1ts.rs @@ -0,0 +1,42 @@ +#[doc = "Register `OUT_W1TS` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_OUT_DATA_W1TS` writer - Reserved"] +pub type REG_GPIO_OUT_DATA_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_out_data_w1ts(&mut self) -> REG_GPIO_OUT_DATA_W1TS_W { + REG_GPIO_OUT_DATA_W1TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_W1TS_SPEC; +impl crate::RegisterSpec for OUT_W1TS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`out_w1ts::W`](W) writer structure"] +impl crate::Writable for OUT_W1TS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT_W1TS to value 0"] +impl crate::Resettable for OUT_W1TS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin0.rs b/esp32p4/src/lp_gpio/pin0.rs new file mode 100644 index 0000000000..010ba7c8d7 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin0.rs @@ -0,0 +1,112 @@ +#[doc = "Register `PIN0` reader"] +pub type R = crate::R; +#[doc = "Register `PIN0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN0_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN0_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN0_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN0_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN0_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN0_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN0_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN0_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN0_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN0_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN0_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN0_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPIO_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin0_wakeup_enable(&self) -> REG_GPIO_PIN0_WAKEUP_ENABLE_R { + REG_GPIO_PIN0_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin0_int_type(&self) -> REG_GPIO_PIN0_INT_TYPE_R { + REG_GPIO_PIN0_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin0_pad_driver(&self) -> REG_GPIO_PIN0_PAD_DRIVER_R { + REG_GPIO_PIN0_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN0") + .field( + "reg_gpio_pin0_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin0_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin0_int_type", + &format_args!("{}", self.reg_gpio_pin0_int_type().bits()), + ) + .field( + "reg_gpio_pin0_pad_driver", + &format_args!("{}", self.reg_gpio_pin0_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin0_wakeup_enable(&mut self) -> REG_GPIO_PIN0_WAKEUP_ENABLE_W { + REG_GPIO_PIN0_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin0_int_type(&mut self) -> REG_GPIO_PIN0_INT_TYPE_W { + REG_GPIO_PIN0_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin0_pad_driver(&mut self) -> REG_GPIO_PIN0_PAD_DRIVER_W { + REG_GPIO_PIN0_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin0_edge_wakeup_clr(&mut self) -> REG_GPIO_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPIO_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN0_SPEC; +impl crate::RegisterSpec for PIN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin0::R`](R) reader structure"] +impl crate::Readable for PIN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin0::W`](W) writer structure"] +impl crate::Writable for PIN0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN0 to value 0"] +impl crate::Resettable for PIN0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin1.rs b/esp32p4/src/lp_gpio/pin1.rs new file mode 100644 index 0000000000..348d321d8a --- /dev/null +++ b/esp32p4/src/lp_gpio/pin1.rs @@ -0,0 +1,112 @@ +#[doc = "Register `PIN1` reader"] +pub type R = crate::R; +#[doc = "Register `PIN1` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN1_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN1_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN1_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN1_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN1_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN1_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN1_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN1_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN1_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN1_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN1_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN1_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI1_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI1_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin1_wakeup_enable(&self) -> REG_GPIO_PIN1_WAKEUP_ENABLE_R { + REG_GPIO_PIN1_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin1_int_type(&self) -> REG_GPIO_PIN1_INT_TYPE_R { + REG_GPIO_PIN1_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin1_pad_driver(&self) -> REG_GPIO_PIN1_PAD_DRIVER_R { + REG_GPIO_PIN1_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN1") + .field( + "reg_gpio_pin1_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin1_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin1_int_type", + &format_args!("{}", self.reg_gpio_pin1_int_type().bits()), + ) + .field( + "reg_gpio_pin1_pad_driver", + &format_args!("{}", self.reg_gpio_pin1_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin1_wakeup_enable(&mut self) -> REG_GPIO_PIN1_WAKEUP_ENABLE_W { + REG_GPIO_PIN1_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin1_int_type(&mut self) -> REG_GPIO_PIN1_INT_TYPE_W { + REG_GPIO_PIN1_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin1_pad_driver(&mut self) -> REG_GPIO_PIN1_PAD_DRIVER_W { + REG_GPIO_PIN1_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi1_pin0_edge_wakeup_clr(&mut self) -> REG_GPI1_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI1_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN1_SPEC; +impl crate::RegisterSpec for PIN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin1::R`](R) reader structure"] +impl crate::Readable for PIN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin1::W`](W) writer structure"] +impl crate::Writable for PIN1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN1 to value 0"] +impl crate::Resettable for PIN1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin10.rs b/esp32p4/src/lp_gpio/pin10.rs new file mode 100644 index 0000000000..96ab381741 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin10.rs @@ -0,0 +1,114 @@ +#[doc = "Register `PIN10` reader"] +pub type R = crate::R; +#[doc = "Register `PIN10` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN10_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN10_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN10_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN10_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN10_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN10_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN10_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN10_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN10_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN10_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN10_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN10_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI10_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI10_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin10_wakeup_enable(&self) -> REG_GPIO_PIN10_WAKEUP_ENABLE_R { + REG_GPIO_PIN10_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin10_int_type(&self) -> REG_GPIO_PIN10_INT_TYPE_R { + REG_GPIO_PIN10_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin10_pad_driver(&self) -> REG_GPIO_PIN10_PAD_DRIVER_R { + REG_GPIO_PIN10_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN10") + .field( + "reg_gpio_pin10_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin10_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin10_int_type", + &format_args!("{}", self.reg_gpio_pin10_int_type().bits()), + ) + .field( + "reg_gpio_pin10_pad_driver", + &format_args!("{}", self.reg_gpio_pin10_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin10_wakeup_enable(&mut self) -> REG_GPIO_PIN10_WAKEUP_ENABLE_W { + REG_GPIO_PIN10_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin10_int_type(&mut self) -> REG_GPIO_PIN10_INT_TYPE_W { + REG_GPIO_PIN10_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin10_pad_driver(&mut self) -> REG_GPIO_PIN10_PAD_DRIVER_W { + REG_GPIO_PIN10_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi10_pin0_edge_wakeup_clr( + &mut self, + ) -> REG_GPI10_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI10_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN10_SPEC; +impl crate::RegisterSpec for PIN10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin10::R`](R) reader structure"] +impl crate::Readable for PIN10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin10::W`](W) writer structure"] +impl crate::Writable for PIN10_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN10 to value 0"] +impl crate::Resettable for PIN10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin11.rs b/esp32p4/src/lp_gpio/pin11.rs new file mode 100644 index 0000000000..07b24dd7c2 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin11.rs @@ -0,0 +1,114 @@ +#[doc = "Register `PIN11` reader"] +pub type R = crate::R; +#[doc = "Register `PIN11` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN11_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN11_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN11_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN11_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN11_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN11_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN11_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN11_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN11_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN11_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN11_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN11_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI11_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI11_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin11_wakeup_enable(&self) -> REG_GPIO_PIN11_WAKEUP_ENABLE_R { + REG_GPIO_PIN11_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin11_int_type(&self) -> REG_GPIO_PIN11_INT_TYPE_R { + REG_GPIO_PIN11_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin11_pad_driver(&self) -> REG_GPIO_PIN11_PAD_DRIVER_R { + REG_GPIO_PIN11_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN11") + .field( + "reg_gpio_pin11_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin11_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin11_int_type", + &format_args!("{}", self.reg_gpio_pin11_int_type().bits()), + ) + .field( + "reg_gpio_pin11_pad_driver", + &format_args!("{}", self.reg_gpio_pin11_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin11_wakeup_enable(&mut self) -> REG_GPIO_PIN11_WAKEUP_ENABLE_W { + REG_GPIO_PIN11_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin11_int_type(&mut self) -> REG_GPIO_PIN11_INT_TYPE_W { + REG_GPIO_PIN11_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin11_pad_driver(&mut self) -> REG_GPIO_PIN11_PAD_DRIVER_W { + REG_GPIO_PIN11_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi11_pin0_edge_wakeup_clr( + &mut self, + ) -> REG_GPI11_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI11_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN11_SPEC; +impl crate::RegisterSpec for PIN11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin11::R`](R) reader structure"] +impl crate::Readable for PIN11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin11::W`](W) writer structure"] +impl crate::Writable for PIN11_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN11 to value 0"] +impl crate::Resettable for PIN11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin12.rs b/esp32p4/src/lp_gpio/pin12.rs new file mode 100644 index 0000000000..2db55a54c8 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin12.rs @@ -0,0 +1,114 @@ +#[doc = "Register `PIN12` reader"] +pub type R = crate::R; +#[doc = "Register `PIN12` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN12_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN12_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN12_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN12_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN12_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN12_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN12_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN12_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN12_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN12_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN12_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN12_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI12_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI12_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin12_wakeup_enable(&self) -> REG_GPIO_PIN12_WAKEUP_ENABLE_R { + REG_GPIO_PIN12_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin12_int_type(&self) -> REG_GPIO_PIN12_INT_TYPE_R { + REG_GPIO_PIN12_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin12_pad_driver(&self) -> REG_GPIO_PIN12_PAD_DRIVER_R { + REG_GPIO_PIN12_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN12") + .field( + "reg_gpio_pin12_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin12_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin12_int_type", + &format_args!("{}", self.reg_gpio_pin12_int_type().bits()), + ) + .field( + "reg_gpio_pin12_pad_driver", + &format_args!("{}", self.reg_gpio_pin12_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin12_wakeup_enable(&mut self) -> REG_GPIO_PIN12_WAKEUP_ENABLE_W { + REG_GPIO_PIN12_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin12_int_type(&mut self) -> REG_GPIO_PIN12_INT_TYPE_W { + REG_GPIO_PIN12_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin12_pad_driver(&mut self) -> REG_GPIO_PIN12_PAD_DRIVER_W { + REG_GPIO_PIN12_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi12_pin0_edge_wakeup_clr( + &mut self, + ) -> REG_GPI12_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI12_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN12_SPEC; +impl crate::RegisterSpec for PIN12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin12::R`](R) reader structure"] +impl crate::Readable for PIN12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin12::W`](W) writer structure"] +impl crate::Writable for PIN12_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN12 to value 0"] +impl crate::Resettable for PIN12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin13.rs b/esp32p4/src/lp_gpio/pin13.rs new file mode 100644 index 0000000000..9c443ad63a --- /dev/null +++ b/esp32p4/src/lp_gpio/pin13.rs @@ -0,0 +1,114 @@ +#[doc = "Register `PIN13` reader"] +pub type R = crate::R; +#[doc = "Register `PIN13` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN13_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN13_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN13_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN13_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN13_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN13_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN13_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN13_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN13_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN13_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN13_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN13_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI13_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI13_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin13_wakeup_enable(&self) -> REG_GPIO_PIN13_WAKEUP_ENABLE_R { + REG_GPIO_PIN13_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin13_int_type(&self) -> REG_GPIO_PIN13_INT_TYPE_R { + REG_GPIO_PIN13_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin13_pad_driver(&self) -> REG_GPIO_PIN13_PAD_DRIVER_R { + REG_GPIO_PIN13_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN13") + .field( + "reg_gpio_pin13_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin13_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin13_int_type", + &format_args!("{}", self.reg_gpio_pin13_int_type().bits()), + ) + .field( + "reg_gpio_pin13_pad_driver", + &format_args!("{}", self.reg_gpio_pin13_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin13_wakeup_enable(&mut self) -> REG_GPIO_PIN13_WAKEUP_ENABLE_W { + REG_GPIO_PIN13_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin13_int_type(&mut self) -> REG_GPIO_PIN13_INT_TYPE_W { + REG_GPIO_PIN13_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin13_pad_driver(&mut self) -> REG_GPIO_PIN13_PAD_DRIVER_W { + REG_GPIO_PIN13_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi13_pin0_edge_wakeup_clr( + &mut self, + ) -> REG_GPI13_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI13_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN13_SPEC; +impl crate::RegisterSpec for PIN13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin13::R`](R) reader structure"] +impl crate::Readable for PIN13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin13::W`](W) writer structure"] +impl crate::Writable for PIN13_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN13 to value 0"] +impl crate::Resettable for PIN13_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin14.rs b/esp32p4/src/lp_gpio/pin14.rs new file mode 100644 index 0000000000..631ba56d86 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin14.rs @@ -0,0 +1,114 @@ +#[doc = "Register `PIN14` reader"] +pub type R = crate::R; +#[doc = "Register `PIN14` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN14_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN14_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN14_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN14_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN14_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN14_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN14_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN14_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN14_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN14_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN14_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN14_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI14_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI14_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin14_wakeup_enable(&self) -> REG_GPIO_PIN14_WAKEUP_ENABLE_R { + REG_GPIO_PIN14_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin14_int_type(&self) -> REG_GPIO_PIN14_INT_TYPE_R { + REG_GPIO_PIN14_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin14_pad_driver(&self) -> REG_GPIO_PIN14_PAD_DRIVER_R { + REG_GPIO_PIN14_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN14") + .field( + "reg_gpio_pin14_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin14_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin14_int_type", + &format_args!("{}", self.reg_gpio_pin14_int_type().bits()), + ) + .field( + "reg_gpio_pin14_pad_driver", + &format_args!("{}", self.reg_gpio_pin14_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin14_wakeup_enable(&mut self) -> REG_GPIO_PIN14_WAKEUP_ENABLE_W { + REG_GPIO_PIN14_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin14_int_type(&mut self) -> REG_GPIO_PIN14_INT_TYPE_W { + REG_GPIO_PIN14_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin14_pad_driver(&mut self) -> REG_GPIO_PIN14_PAD_DRIVER_W { + REG_GPIO_PIN14_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi14_pin0_edge_wakeup_clr( + &mut self, + ) -> REG_GPI14_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI14_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN14_SPEC; +impl crate::RegisterSpec for PIN14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin14::R`](R) reader structure"] +impl crate::Readable for PIN14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin14::W`](W) writer structure"] +impl crate::Writable for PIN14_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN14 to value 0"] +impl crate::Resettable for PIN14_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin15.rs b/esp32p4/src/lp_gpio/pin15.rs new file mode 100644 index 0000000000..a933274cdc --- /dev/null +++ b/esp32p4/src/lp_gpio/pin15.rs @@ -0,0 +1,114 @@ +#[doc = "Register `PIN15` reader"] +pub type R = crate::R; +#[doc = "Register `PIN15` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN15_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN15_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN15_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN15_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN15_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN15_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN15_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN15_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN15_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN15_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN15_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN15_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI15_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI15_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin15_wakeup_enable(&self) -> REG_GPIO_PIN15_WAKEUP_ENABLE_R { + REG_GPIO_PIN15_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin15_int_type(&self) -> REG_GPIO_PIN15_INT_TYPE_R { + REG_GPIO_PIN15_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin15_pad_driver(&self) -> REG_GPIO_PIN15_PAD_DRIVER_R { + REG_GPIO_PIN15_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN15") + .field( + "reg_gpio_pin15_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin15_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin15_int_type", + &format_args!("{}", self.reg_gpio_pin15_int_type().bits()), + ) + .field( + "reg_gpio_pin15_pad_driver", + &format_args!("{}", self.reg_gpio_pin15_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin15_wakeup_enable(&mut self) -> REG_GPIO_PIN15_WAKEUP_ENABLE_W { + REG_GPIO_PIN15_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin15_int_type(&mut self) -> REG_GPIO_PIN15_INT_TYPE_W { + REG_GPIO_PIN15_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin15_pad_driver(&mut self) -> REG_GPIO_PIN15_PAD_DRIVER_W { + REG_GPIO_PIN15_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi15_pin0_edge_wakeup_clr( + &mut self, + ) -> REG_GPI15_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI15_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN15_SPEC; +impl crate::RegisterSpec for PIN15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin15::R`](R) reader structure"] +impl crate::Readable for PIN15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin15::W`](W) writer structure"] +impl crate::Writable for PIN15_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN15 to value 0"] +impl crate::Resettable for PIN15_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin2.rs b/esp32p4/src/lp_gpio/pin2.rs new file mode 100644 index 0000000000..2813f8a972 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin2.rs @@ -0,0 +1,112 @@ +#[doc = "Register `PIN2` reader"] +pub type R = crate::R; +#[doc = "Register `PIN2` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN2_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN2_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN2_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN2_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN2_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN2_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN2_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN2_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN2_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN2_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN2_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN2_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI2_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI2_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin2_wakeup_enable(&self) -> REG_GPIO_PIN2_WAKEUP_ENABLE_R { + REG_GPIO_PIN2_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin2_int_type(&self) -> REG_GPIO_PIN2_INT_TYPE_R { + REG_GPIO_PIN2_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin2_pad_driver(&self) -> REG_GPIO_PIN2_PAD_DRIVER_R { + REG_GPIO_PIN2_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN2") + .field( + "reg_gpio_pin2_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin2_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin2_int_type", + &format_args!("{}", self.reg_gpio_pin2_int_type().bits()), + ) + .field( + "reg_gpio_pin2_pad_driver", + &format_args!("{}", self.reg_gpio_pin2_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin2_wakeup_enable(&mut self) -> REG_GPIO_PIN2_WAKEUP_ENABLE_W { + REG_GPIO_PIN2_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin2_int_type(&mut self) -> REG_GPIO_PIN2_INT_TYPE_W { + REG_GPIO_PIN2_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin2_pad_driver(&mut self) -> REG_GPIO_PIN2_PAD_DRIVER_W { + REG_GPIO_PIN2_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi2_pin0_edge_wakeup_clr(&mut self) -> REG_GPI2_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI2_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN2_SPEC; +impl crate::RegisterSpec for PIN2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin2::R`](R) reader structure"] +impl crate::Readable for PIN2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin2::W`](W) writer structure"] +impl crate::Writable for PIN2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN2 to value 0"] +impl crate::Resettable for PIN2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin3.rs b/esp32p4/src/lp_gpio/pin3.rs new file mode 100644 index 0000000000..54c9c17625 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin3.rs @@ -0,0 +1,112 @@ +#[doc = "Register `PIN3` reader"] +pub type R = crate::R; +#[doc = "Register `PIN3` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN3_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN3_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN3_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN3_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN3_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN3_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN3_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN3_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN3_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN3_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN3_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN3_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI3_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI3_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin3_wakeup_enable(&self) -> REG_GPIO_PIN3_WAKEUP_ENABLE_R { + REG_GPIO_PIN3_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin3_int_type(&self) -> REG_GPIO_PIN3_INT_TYPE_R { + REG_GPIO_PIN3_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin3_pad_driver(&self) -> REG_GPIO_PIN3_PAD_DRIVER_R { + REG_GPIO_PIN3_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN3") + .field( + "reg_gpio_pin3_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin3_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin3_int_type", + &format_args!("{}", self.reg_gpio_pin3_int_type().bits()), + ) + .field( + "reg_gpio_pin3_pad_driver", + &format_args!("{}", self.reg_gpio_pin3_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin3_wakeup_enable(&mut self) -> REG_GPIO_PIN3_WAKEUP_ENABLE_W { + REG_GPIO_PIN3_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin3_int_type(&mut self) -> REG_GPIO_PIN3_INT_TYPE_W { + REG_GPIO_PIN3_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin3_pad_driver(&mut self) -> REG_GPIO_PIN3_PAD_DRIVER_W { + REG_GPIO_PIN3_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi3_pin0_edge_wakeup_clr(&mut self) -> REG_GPI3_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI3_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN3_SPEC; +impl crate::RegisterSpec for PIN3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin3::R`](R) reader structure"] +impl crate::Readable for PIN3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin3::W`](W) writer structure"] +impl crate::Writable for PIN3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN3 to value 0"] +impl crate::Resettable for PIN3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin4.rs b/esp32p4/src/lp_gpio/pin4.rs new file mode 100644 index 0000000000..eefb3ebc12 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin4.rs @@ -0,0 +1,112 @@ +#[doc = "Register `PIN4` reader"] +pub type R = crate::R; +#[doc = "Register `PIN4` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN4_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN4_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN4_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN4_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN4_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN4_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN4_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN4_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN4_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN4_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN4_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN4_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI4_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI4_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin4_wakeup_enable(&self) -> REG_GPIO_PIN4_WAKEUP_ENABLE_R { + REG_GPIO_PIN4_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin4_int_type(&self) -> REG_GPIO_PIN4_INT_TYPE_R { + REG_GPIO_PIN4_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin4_pad_driver(&self) -> REG_GPIO_PIN4_PAD_DRIVER_R { + REG_GPIO_PIN4_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN4") + .field( + "reg_gpio_pin4_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin4_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin4_int_type", + &format_args!("{}", self.reg_gpio_pin4_int_type().bits()), + ) + .field( + "reg_gpio_pin4_pad_driver", + &format_args!("{}", self.reg_gpio_pin4_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin4_wakeup_enable(&mut self) -> REG_GPIO_PIN4_WAKEUP_ENABLE_W { + REG_GPIO_PIN4_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin4_int_type(&mut self) -> REG_GPIO_PIN4_INT_TYPE_W { + REG_GPIO_PIN4_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin4_pad_driver(&mut self) -> REG_GPIO_PIN4_PAD_DRIVER_W { + REG_GPIO_PIN4_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi4_pin0_edge_wakeup_clr(&mut self) -> REG_GPI4_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI4_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN4_SPEC; +impl crate::RegisterSpec for PIN4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin4::R`](R) reader structure"] +impl crate::Readable for PIN4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin4::W`](W) writer structure"] +impl crate::Writable for PIN4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN4 to value 0"] +impl crate::Resettable for PIN4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin5.rs b/esp32p4/src/lp_gpio/pin5.rs new file mode 100644 index 0000000000..9d7f5edaa2 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin5.rs @@ -0,0 +1,112 @@ +#[doc = "Register `PIN5` reader"] +pub type R = crate::R; +#[doc = "Register `PIN5` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN5_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN5_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN5_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN5_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN5_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN5_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN5_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN5_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN5_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN5_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN5_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN5_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI5_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI5_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin5_wakeup_enable(&self) -> REG_GPIO_PIN5_WAKEUP_ENABLE_R { + REG_GPIO_PIN5_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin5_int_type(&self) -> REG_GPIO_PIN5_INT_TYPE_R { + REG_GPIO_PIN5_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin5_pad_driver(&self) -> REG_GPIO_PIN5_PAD_DRIVER_R { + REG_GPIO_PIN5_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN5") + .field( + "reg_gpio_pin5_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin5_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin5_int_type", + &format_args!("{}", self.reg_gpio_pin5_int_type().bits()), + ) + .field( + "reg_gpio_pin5_pad_driver", + &format_args!("{}", self.reg_gpio_pin5_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin5_wakeup_enable(&mut self) -> REG_GPIO_PIN5_WAKEUP_ENABLE_W { + REG_GPIO_PIN5_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin5_int_type(&mut self) -> REG_GPIO_PIN5_INT_TYPE_W { + REG_GPIO_PIN5_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin5_pad_driver(&mut self) -> REG_GPIO_PIN5_PAD_DRIVER_W { + REG_GPIO_PIN5_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi5_pin0_edge_wakeup_clr(&mut self) -> REG_GPI5_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI5_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN5_SPEC; +impl crate::RegisterSpec for PIN5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin5::R`](R) reader structure"] +impl crate::Readable for PIN5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin5::W`](W) writer structure"] +impl crate::Writable for PIN5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN5 to value 0"] +impl crate::Resettable for PIN5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin6.rs b/esp32p4/src/lp_gpio/pin6.rs new file mode 100644 index 0000000000..58fdf3acb9 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin6.rs @@ -0,0 +1,112 @@ +#[doc = "Register `PIN6` reader"] +pub type R = crate::R; +#[doc = "Register `PIN6` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN6_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN6_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN6_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN6_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN6_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN6_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN6_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN6_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN6_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN6_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN6_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN6_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI6_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI6_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin6_wakeup_enable(&self) -> REG_GPIO_PIN6_WAKEUP_ENABLE_R { + REG_GPIO_PIN6_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin6_int_type(&self) -> REG_GPIO_PIN6_INT_TYPE_R { + REG_GPIO_PIN6_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin6_pad_driver(&self) -> REG_GPIO_PIN6_PAD_DRIVER_R { + REG_GPIO_PIN6_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN6") + .field( + "reg_gpio_pin6_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin6_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin6_int_type", + &format_args!("{}", self.reg_gpio_pin6_int_type().bits()), + ) + .field( + "reg_gpio_pin6_pad_driver", + &format_args!("{}", self.reg_gpio_pin6_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin6_wakeup_enable(&mut self) -> REG_GPIO_PIN6_WAKEUP_ENABLE_W { + REG_GPIO_PIN6_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin6_int_type(&mut self) -> REG_GPIO_PIN6_INT_TYPE_W { + REG_GPIO_PIN6_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin6_pad_driver(&mut self) -> REG_GPIO_PIN6_PAD_DRIVER_W { + REG_GPIO_PIN6_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi6_pin0_edge_wakeup_clr(&mut self) -> REG_GPI6_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI6_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN6_SPEC; +impl crate::RegisterSpec for PIN6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin6::R`](R) reader structure"] +impl crate::Readable for PIN6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin6::W`](W) writer structure"] +impl crate::Writable for PIN6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN6 to value 0"] +impl crate::Resettable for PIN6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin7.rs b/esp32p4/src/lp_gpio/pin7.rs new file mode 100644 index 0000000000..bdff659972 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin7.rs @@ -0,0 +1,112 @@ +#[doc = "Register `PIN7` reader"] +pub type R = crate::R; +#[doc = "Register `PIN7` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN7_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN7_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN7_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN7_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN7_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN7_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN7_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN7_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN7_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN7_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN7_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN7_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI7_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI7_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin7_wakeup_enable(&self) -> REG_GPIO_PIN7_WAKEUP_ENABLE_R { + REG_GPIO_PIN7_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin7_int_type(&self) -> REG_GPIO_PIN7_INT_TYPE_R { + REG_GPIO_PIN7_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin7_pad_driver(&self) -> REG_GPIO_PIN7_PAD_DRIVER_R { + REG_GPIO_PIN7_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN7") + .field( + "reg_gpio_pin7_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin7_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin7_int_type", + &format_args!("{}", self.reg_gpio_pin7_int_type().bits()), + ) + .field( + "reg_gpio_pin7_pad_driver", + &format_args!("{}", self.reg_gpio_pin7_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin7_wakeup_enable(&mut self) -> REG_GPIO_PIN7_WAKEUP_ENABLE_W { + REG_GPIO_PIN7_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin7_int_type(&mut self) -> REG_GPIO_PIN7_INT_TYPE_W { + REG_GPIO_PIN7_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin7_pad_driver(&mut self) -> REG_GPIO_PIN7_PAD_DRIVER_W { + REG_GPIO_PIN7_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi7_pin0_edge_wakeup_clr(&mut self) -> REG_GPI7_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI7_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN7_SPEC; +impl crate::RegisterSpec for PIN7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin7::R`](R) reader structure"] +impl crate::Readable for PIN7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin7::W`](W) writer structure"] +impl crate::Writable for PIN7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN7 to value 0"] +impl crate::Resettable for PIN7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin8.rs b/esp32p4/src/lp_gpio/pin8.rs new file mode 100644 index 0000000000..16e28b4ef8 --- /dev/null +++ b/esp32p4/src/lp_gpio/pin8.rs @@ -0,0 +1,112 @@ +#[doc = "Register `PIN8` reader"] +pub type R = crate::R; +#[doc = "Register `PIN8` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN8_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN8_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN8_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN8_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN8_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN8_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN8_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN8_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN8_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN8_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN8_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN8_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI8_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI8_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin8_wakeup_enable(&self) -> REG_GPIO_PIN8_WAKEUP_ENABLE_R { + REG_GPIO_PIN8_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin8_int_type(&self) -> REG_GPIO_PIN8_INT_TYPE_R { + REG_GPIO_PIN8_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin8_pad_driver(&self) -> REG_GPIO_PIN8_PAD_DRIVER_R { + REG_GPIO_PIN8_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN8") + .field( + "reg_gpio_pin8_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin8_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin8_int_type", + &format_args!("{}", self.reg_gpio_pin8_int_type().bits()), + ) + .field( + "reg_gpio_pin8_pad_driver", + &format_args!("{}", self.reg_gpio_pin8_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin8_wakeup_enable(&mut self) -> REG_GPIO_PIN8_WAKEUP_ENABLE_W { + REG_GPIO_PIN8_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin8_int_type(&mut self) -> REG_GPIO_PIN8_INT_TYPE_W { + REG_GPIO_PIN8_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin8_pad_driver(&mut self) -> REG_GPIO_PIN8_PAD_DRIVER_W { + REG_GPIO_PIN8_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi8_pin0_edge_wakeup_clr(&mut self) -> REG_GPI8_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI8_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN8_SPEC; +impl crate::RegisterSpec for PIN8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin8::R`](R) reader structure"] +impl crate::Readable for PIN8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin8::W`](W) writer structure"] +impl crate::Writable for PIN8_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN8 to value 0"] +impl crate::Resettable for PIN8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/pin9.rs b/esp32p4/src/lp_gpio/pin9.rs new file mode 100644 index 0000000000..a629d1a8ef --- /dev/null +++ b/esp32p4/src/lp_gpio/pin9.rs @@ -0,0 +1,112 @@ +#[doc = "Register `PIN9` reader"] +pub type R = crate::R; +#[doc = "Register `PIN9` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_PIN9_WAKEUP_ENABLE` reader - Reserved"] +pub type REG_GPIO_PIN9_WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN9_WAKEUP_ENABLE` writer - Reserved"] +pub type REG_GPIO_PIN9_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPIO_PIN9_INT_TYPE` reader - Reserved"] +pub type REG_GPIO_PIN9_INT_TYPE_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_PIN9_INT_TYPE` writer - Reserved"] +pub type REG_GPIO_PIN9_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `REG_GPIO_PIN9_PAD_DRIVER` reader - Reserved"] +pub type REG_GPIO_PIN9_PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `REG_GPIO_PIN9_PAD_DRIVER` writer - Reserved"] +pub type REG_GPIO_PIN9_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_GPI9_PIN0_EDGE_WAKEUP_CLR` writer - need des"] +pub type REG_GPI9_PIN0_EDGE_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin9_wakeup_enable(&self) -> REG_GPIO_PIN9_WAKEUP_ENABLE_R { + REG_GPIO_PIN9_WAKEUP_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin9_int_type(&self) -> REG_GPIO_PIN9_INT_TYPE_R { + REG_GPIO_PIN9_INT_TYPE_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + pub fn reg_gpio_pin9_pad_driver(&self) -> REG_GPIO_PIN9_PAD_DRIVER_R { + REG_GPIO_PIN9_PAD_DRIVER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIN9") + .field( + "reg_gpio_pin9_wakeup_enable", + &format_args!("{}", self.reg_gpio_pin9_wakeup_enable().bit()), + ) + .field( + "reg_gpio_pin9_int_type", + &format_args!("{}", self.reg_gpio_pin9_int_type().bits()), + ) + .field( + "reg_gpio_pin9_pad_driver", + &format_args!("{}", self.reg_gpio_pin9_pad_driver().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin9_wakeup_enable(&mut self) -> REG_GPIO_PIN9_WAKEUP_ENABLE_W { + REG_GPIO_PIN9_WAKEUP_ENABLE_W::new(self, 0) + } + #[doc = "Bits 1:3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin9_int_type(&mut self) -> REG_GPIO_PIN9_INT_TYPE_W { + REG_GPIO_PIN9_INT_TYPE_W::new(self, 1) + } + #[doc = "Bit 4 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_pin9_pad_driver(&mut self) -> REG_GPIO_PIN9_PAD_DRIVER_W { + REG_GPIO_PIN9_PAD_DRIVER_W::new(self, 4) + } + #[doc = "Bit 5 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_gpi9_pin0_edge_wakeup_clr(&mut self) -> REG_GPI9_PIN0_EDGE_WAKEUP_CLR_W { + REG_GPI9_PIN0_EDGE_WAKEUP_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN9_SPEC; +impl crate::RegisterSpec for PIN9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pin9::R`](R) reader structure"] +impl crate::Readable for PIN9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin9::W`](W) writer structure"] +impl crate::Writable for PIN9_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIN9 to value 0"] +impl crate::Resettable for PIN9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/status.rs b/esp32p4/src/lp_gpio/status.rs new file mode 100644 index 0000000000..8b754e7492 --- /dev/null +++ b/esp32p4/src/lp_gpio/status.rs @@ -0,0 +1,66 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_STATUS_DATA` reader - Reserved"] +pub type REG_GPIO_STATUS_DATA_R = crate::FieldReader; +#[doc = "Field `REG_GPIO_STATUS_DATA` writer - Reserved"] +pub type REG_GPIO_STATUS_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + pub fn reg_gpio_status_data(&self) -> REG_GPIO_STATUS_DATA_R { + REG_GPIO_STATUS_DATA_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field( + "reg_gpio_status_data", + &format_args!("{}", self.reg_gpio_status_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_status_data(&mut self) -> REG_GPIO_STATUS_DATA_W { + REG_GPIO_STATUS_DATA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/status_next.rs b/esp32p4/src/lp_gpio/status_next.rs new file mode 100644 index 0000000000..9164a84907 --- /dev/null +++ b/esp32p4/src/lp_gpio/status_next.rs @@ -0,0 +1,39 @@ +#[doc = "Register `STATUS_NEXT` reader"] +pub type R = crate::R; +#[doc = "Field `REG_GPIO_STATUS_INTERRUPT_NEXT` reader - Reserved"] +pub type REG_GPIO_STATUS_INTERRUPT_NEXT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + pub fn reg_gpio_status_interrupt_next(&self) -> REG_GPIO_STATUS_INTERRUPT_NEXT_R { + REG_GPIO_STATUS_INTERRUPT_NEXT_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_NEXT") + .field( + "reg_gpio_status_interrupt_next", + &format_args!("{}", self.reg_gpio_status_interrupt_next().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_NEXT_SPEC; +impl crate::RegisterSpec for STATUS_NEXT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_next::R`](R) reader structure"] +impl crate::Readable for STATUS_NEXT_SPEC {} +#[doc = "`reset()` method sets STATUS_NEXT to value 0"] +impl crate::Resettable for STATUS_NEXT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/status_w1tc.rs b/esp32p4/src/lp_gpio/status_w1tc.rs new file mode 100644 index 0000000000..aea6fcbc57 --- /dev/null +++ b/esp32p4/src/lp_gpio/status_w1tc.rs @@ -0,0 +1,42 @@ +#[doc = "Register `STATUS_W1TC` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_STATUS_DATA_W1TC` writer - Reserved"] +pub type REG_GPIO_STATUS_DATA_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_status_data_w1tc(&mut self) -> REG_GPIO_STATUS_DATA_W1TC_W { + REG_GPIO_STATUS_DATA_W1TC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_W1TC_SPEC; +impl crate::RegisterSpec for STATUS_W1TC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`status_w1tc::W`](W) writer structure"] +impl crate::Writable for STATUS_W1TC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS_W1TC to value 0"] +impl crate::Resettable for STATUS_W1TC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/status_w1ts.rs b/esp32p4/src/lp_gpio/status_w1ts.rs new file mode 100644 index 0000000000..5126a3d0ab --- /dev/null +++ b/esp32p4/src/lp_gpio/status_w1ts.rs @@ -0,0 +1,42 @@ +#[doc = "Register `STATUS_W1TS` writer"] +pub type W = crate::W; +#[doc = "Field `REG_GPIO_STATUS_DATA_W1TS` writer - Reserved"] +pub type REG_GPIO_STATUS_DATA_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_gpio_status_data_w1ts(&mut self) -> REG_GPIO_STATUS_DATA_W1TS_W { + REG_GPIO_STATUS_DATA_W1TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_W1TS_SPEC; +impl crate::RegisterSpec for STATUS_W1TS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`status_w1ts::W`](W) writer structure"] +impl crate::Writable for STATUS_W1TS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS_W1TS to value 0"] +impl crate::Resettable for STATUS_W1TS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_gpio/ver_date.rs b/esp32p4/src/lp_gpio/ver_date.rs new file mode 100644 index 0000000000..863f4973bf --- /dev/null +++ b/esp32p4/src/lp_gpio/ver_date.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VER_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `VER_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `REG_VER_DATE` reader - Reserved"] +pub type REG_VER_DATE_R = crate::FieldReader; +#[doc = "Field `REG_VER_DATE` writer - Reserved"] +pub type REG_VER_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Reserved"] + #[inline(always)] + pub fn reg_ver_date(&self) -> REG_VER_DATE_R { + REG_VER_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VER_DATE") + .field( + "reg_ver_date", + &format_args!("{}", self.reg_ver_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ver_date(&mut self) -> REG_VER_DATE_W { + REG_VER_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VER_DATE_SPEC; +impl crate::RegisterSpec for VER_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ver_date::R`](R) reader structure"] +impl crate::Readable for VER_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ver_date::W`](W) writer structure"] +impl crate::Writable for VER_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VER_DATE to value 0x0023_0323"] +impl crate::Resettable for VER_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0023_0323; +} diff --git a/esp32p4/src/lp_huk.rs b/esp32p4/src/lp_huk.rs new file mode 100644 index 0000000000..32452831c3 --- /dev/null +++ b/esp32p4/src/lp_huk.rs @@ -0,0 +1,121 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + _reserved0: [u8; 0x04], + clk: CLK, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + _reserved5: [u8; 0x08], + conf: CONF, + start: START, + state: STATE, + _reserved8: [u8; 0x08], + status: STATUS, + _reserved9: [u8; 0xc4], + date: DATE, + info_mem: [INFO_MEM; 384], +} +impl RegisterBlock { + #[doc = "0x04 - HUK Generator clock gate control register"] + #[inline(always)] + pub const fn clk(&self) -> &CLK { + &self.clk + } + #[doc = "0x08 - HUK Generator interrupt raw register, valid in level."] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x0c - HUK Generator interrupt status register."] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x10 - HUK Generator interrupt enable register."] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x14 - HUK Generator interrupt clear register."] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x20 - HUK Generator configuration register"] + #[inline(always)] + pub const fn conf(&self) -> &CONF { + &self.conf + } + #[doc = "0x24 - HUK Generator control register"] + #[inline(always)] + pub const fn start(&self) -> &START { + &self.start + } + #[doc = "0x28 - HUK Generator state register"] + #[inline(always)] + pub const fn state(&self) -> &STATE { + &self.state + } + #[doc = "0x34 - HUK Generator HUK status register"] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0xfc - Version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } + #[doc = "0x100..0x280 - The memory that stores HUK info."] + #[inline(always)] + pub const fn info_mem(&self, n: usize) -> &INFO_MEM { + &self.info_mem[n] + } +} +#[doc = "CLK (rw) register accessor: HUK Generator clock gate control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk`] module"] +pub type CLK = crate::Reg; +#[doc = "HUK Generator clock gate control register"] +pub mod clk; +#[doc = "INT_RAW (r) register accessor: HUK Generator interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "HUK Generator interrupt raw register, valid in level."] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: HUK Generator interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "HUK Generator interrupt status register."] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: HUK Generator interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "HUK Generator interrupt enable register."] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: HUK Generator interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "HUK Generator interrupt clear register."] +pub mod int_clr; +#[doc = "CONF (rw) register accessor: HUK Generator configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"] +pub type CONF = crate::Reg; +#[doc = "HUK Generator configuration register"] +pub mod conf; +#[doc = "START (w) register accessor: HUK Generator control register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`start::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@start`] module"] +pub type START = crate::Reg; +#[doc = "HUK Generator control register"] +pub mod start; +#[doc = "STATE (r) register accessor: HUK Generator state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"] +pub type STATE = crate::Reg; +#[doc = "HUK Generator state register"] +pub mod state; +#[doc = "STATUS (r) register accessor: HUK Generator HUK status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +pub type STATUS = crate::Reg; +#[doc = "HUK Generator HUK status register"] +pub mod status; +#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version control register"] +pub mod date; +#[doc = "INFO_MEM (rw) register accessor: The memory that stores HUK info.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`info_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`info_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@info_mem`] module"] +pub type INFO_MEM = crate::Reg; +#[doc = "The memory that stores HUK info."] +pub mod info_mem; diff --git a/esp32p4/src/lp_huk/clk.rs b/esp32p4/src/lp_huk/clk.rs new file mode 100644 index 0000000000..ce99ce015f --- /dev/null +++ b/esp32p4/src/lp_huk/clk.rs @@ -0,0 +1,82 @@ +#[doc = "Register `CLK` reader"] +pub type R = crate::R; +#[doc = "Register `CLK` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Write 1 to force on register clock gate."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Write 1 to force on register clock gate."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_CG_FORCE_ON` reader - Write 1 to force on memory clock gate."] +pub type MEM_CG_FORCE_ON_R = crate::BitReader; +#[doc = "Field `MEM_CG_FORCE_ON` writer - Write 1 to force on memory clock gate."] +pub type MEM_CG_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 to force on register clock gate."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to force on memory clock gate."] + #[inline(always)] + pub fn mem_cg_force_on(&self) -> MEM_CG_FORCE_ON_R { + MEM_CG_FORCE_ON_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK") + .field("en", &format_args!("{}", self.en().bit())) + .field( + "mem_cg_force_on", + &format_args!("{}", self.mem_cg_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to force on register clock gate."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to force on memory clock gate."] + #[inline(always)] + #[must_use] + pub fn mem_cg_force_on(&mut self) -> MEM_CG_FORCE_ON_W { + MEM_CG_FORCE_ON_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "HUK Generator clock gate control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_SPEC; +impl crate::RegisterSpec for CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk::R`](R) reader structure"] +impl crate::Readable for CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"] +impl crate::Writable for CLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK to value 0x01"] +impl crate::Resettable for CLK_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/lp_huk/conf.rs b/esp32p4/src/lp_huk/conf.rs new file mode 100644 index 0000000000..d5a4fe0b16 --- /dev/null +++ b/esp32p4/src/lp_huk/conf.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CONF` writer"] +pub type W = crate::W; +#[doc = "Field `MODE` reader - Set this field to choose the huk process. 1: process huk generate mode. 0: process huk recovery mode."] +pub type MODE_R = crate::BitReader; +#[doc = "Field `MODE` writer - Set this field to choose the huk process. 1: process huk generate mode. 0: process huk recovery mode."] +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this field to choose the huk process. 1: process huk generate mode. 0: process huk recovery mode."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF") + .field("mode", &format_args!("{}", self.mode().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this field to choose the huk process. 1: process huk generate mode. 0: process huk recovery mode."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "HUK Generator configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SPEC; +impl crate::RegisterSpec for CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf::R`](R) reader structure"] +impl crate::Readable for CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"] +impl crate::Writable for CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF to value 0"] +impl crate::Resettable for CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_huk/date.rs b/esp32p4/src/lp_huk/date.rs new file mode 100644 index 0000000000..fa0b4ae94b --- /dev/null +++ b/esp32p4/src/lp_huk/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - HUK Generator version control register."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - HUK Generator version control register."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - HUK Generator version control register."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - HUK Generator version control register."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_5040"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_5040; +} diff --git a/esp32p4/src/lp_huk/info_mem.rs b/esp32p4/src/lp_huk/info_mem.rs new file mode 100644 index 0000000000..13904747a3 --- /dev/null +++ b/esp32p4/src/lp_huk/info_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `INFO_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `INFO_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The memory that stores HUK info.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`info_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`info_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFO_MEM_SPEC; +impl crate::RegisterSpec for INFO_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`info_mem::R`](R) reader structure"] +impl crate::Readable for INFO_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`info_mem::W`](W) writer structure"] +impl crate::Writable for INFO_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INFO_MEM[%s] to value 0"] +impl crate::Resettable for INFO_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_huk/int_clr.rs b/esp32p4/src/lp_huk/int_clr.rs new file mode 100644 index 0000000000..1e182b7035 --- /dev/null +++ b/esp32p4/src/lp_huk/int_clr.rs @@ -0,0 +1,58 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `PREP_DONE_INT_CLR` writer - Set this bit to clear the huk_prep_done_int interrupt"] +pub type PREP_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC_DONE_INT_CLR` writer - Set this bit to clear the huk_proc_done_int interrupt"] +pub type PROC_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `POST_DONE_INT_CLR` writer - Set this bit to clear the huk_post_done_int interrupt"] +pub type POST_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the huk_prep_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn prep_done_int_clr(&mut self) -> PREP_DONE_INT_CLR_W { + PREP_DONE_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the huk_proc_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn proc_done_int_clr(&mut self) -> PROC_DONE_INT_CLR_W { + PROC_DONE_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the huk_post_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn post_done_int_clr(&mut self) -> POST_DONE_INT_CLR_W { + POST_DONE_INT_CLR_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "HUK Generator interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_huk/int_ena.rs b/esp32p4/src/lp_huk/int_ena.rs new file mode 100644 index 0000000000..afc3f36035 --- /dev/null +++ b/esp32p4/src/lp_huk/int_ena.rs @@ -0,0 +1,104 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `PREP_DONE_INT_ENA` reader - The interrupt enable bit for the huk_prep_done_int interrupt"] +pub type PREP_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `PREP_DONE_INT_ENA` writer - The interrupt enable bit for the huk_prep_done_int interrupt"] +pub type PREP_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC_DONE_INT_ENA` reader - The interrupt enable bit for the huk_proc_done_int interrupt"] +pub type PROC_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `PROC_DONE_INT_ENA` writer - The interrupt enable bit for the huk_proc_done_int interrupt"] +pub type PROC_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `POST_DONE_INT_ENA` reader - The interrupt enable bit for the huk_post_done_int interrupt"] +pub type POST_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `POST_DONE_INT_ENA` writer - The interrupt enable bit for the huk_post_done_int interrupt"] +pub type POST_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the huk_prep_done_int interrupt"] + #[inline(always)] + pub fn prep_done_int_ena(&self) -> PREP_DONE_INT_ENA_R { + PREP_DONE_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the huk_proc_done_int interrupt"] + #[inline(always)] + pub fn proc_done_int_ena(&self) -> PROC_DONE_INT_ENA_R { + PROC_DONE_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the huk_post_done_int interrupt"] + #[inline(always)] + pub fn post_done_int_ena(&self) -> POST_DONE_INT_ENA_R { + POST_DONE_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "prep_done_int_ena", + &format_args!("{}", self.prep_done_int_ena().bit()), + ) + .field( + "proc_done_int_ena", + &format_args!("{}", self.proc_done_int_ena().bit()), + ) + .field( + "post_done_int_ena", + &format_args!("{}", self.post_done_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the huk_prep_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn prep_done_int_ena(&mut self) -> PREP_DONE_INT_ENA_W { + PREP_DONE_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the huk_proc_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn proc_done_int_ena(&mut self) -> PROC_DONE_INT_ENA_W { + PROC_DONE_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the huk_post_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn post_done_int_ena(&mut self) -> POST_DONE_INT_ENA_W { + POST_DONE_INT_ENA_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "HUK Generator interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_huk/int_raw.rs b/esp32p4/src/lp_huk/int_raw.rs new file mode 100644 index 0000000000..39714bd90f --- /dev/null +++ b/esp32p4/src/lp_huk/int_raw.rs @@ -0,0 +1,61 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `PREP_DONE_INT_RAW` reader - The raw interrupt status bit for the huk_prep_done_int interrupt"] +pub type PREP_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `PROC_DONE_INT_RAW` reader - The raw interrupt status bit for the huk_proc_done_int interrupt"] +pub type PROC_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `POST_DONE_INT_RAW` reader - The raw interrupt status bit for the huk_post_done_int interrupt"] +pub type POST_DONE_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the huk_prep_done_int interrupt"] + #[inline(always)] + pub fn prep_done_int_raw(&self) -> PREP_DONE_INT_RAW_R { + PREP_DONE_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the huk_proc_done_int interrupt"] + #[inline(always)] + pub fn proc_done_int_raw(&self) -> PROC_DONE_INT_RAW_R { + PROC_DONE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the huk_post_done_int interrupt"] + #[inline(always)] + pub fn post_done_int_raw(&self) -> POST_DONE_INT_RAW_R { + POST_DONE_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "prep_done_int_raw", + &format_args!("{}", self.prep_done_int_raw().bit()), + ) + .field( + "proc_done_int_raw", + &format_args!("{}", self.proc_done_int_raw().bit()), + ) + .field( + "post_done_int_raw", + &format_args!("{}", self.post_done_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "HUK Generator interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_huk/int_st.rs b/esp32p4/src/lp_huk/int_st.rs new file mode 100644 index 0000000000..f3f406fca7 --- /dev/null +++ b/esp32p4/src/lp_huk/int_st.rs @@ -0,0 +1,61 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `PREP_DONE_INT_ST` reader - The masked interrupt status bit for the huk_prep_done_int interrupt"] +pub type PREP_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `PROC_DONE_INT_ST` reader - The masked interrupt status bit for the huk_proc_done_int interrupt"] +pub type PROC_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `POST_DONE_INT_ST` reader - The masked interrupt status bit for the huk_post_done_int interrupt"] +pub type POST_DONE_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status bit for the huk_prep_done_int interrupt"] + #[inline(always)] + pub fn prep_done_int_st(&self) -> PREP_DONE_INT_ST_R { + PREP_DONE_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status bit for the huk_proc_done_int interrupt"] + #[inline(always)] + pub fn proc_done_int_st(&self) -> PROC_DONE_INT_ST_R { + PROC_DONE_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status bit for the huk_post_done_int interrupt"] + #[inline(always)] + pub fn post_done_int_st(&self) -> POST_DONE_INT_ST_R { + POST_DONE_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "prep_done_int_st", + &format_args!("{}", self.prep_done_int_st().bit()), + ) + .field( + "proc_done_int_st", + &format_args!("{}", self.proc_done_int_st().bit()), + ) + .field( + "post_done_int_st", + &format_args!("{}", self.post_done_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "HUK Generator interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_huk/start.rs b/esp32p4/src/lp_huk/start.rs new file mode 100644 index 0000000000..c1e6f4b8a3 --- /dev/null +++ b/esp32p4/src/lp_huk/start.rs @@ -0,0 +1,50 @@ +#[doc = "Register `START` writer"] +pub type W = crate::W; +#[doc = "Field `START` writer - Write 1 to continue HUK Generator operation at LOAD/GAIN state."] +pub type START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CONTINUE` writer - Write 1 to start HUK Generator at IDLE state."] +pub type CONTINUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to continue HUK Generator operation at LOAD/GAIN state."] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> START_W { + START_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to start HUK Generator at IDLE state."] + #[inline(always)] + #[must_use] + pub fn continue_(&mut self) -> CONTINUE_W { + CONTINUE_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "HUK Generator control register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`start::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct START_SPEC; +impl crate::RegisterSpec for START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`start::W`](W) writer structure"] +impl crate::Writable for START_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets START to value 0"] +impl crate::Resettable for START_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_huk/state.rs b/esp32p4/src/lp_huk/state.rs new file mode 100644 index 0000000000..a72f1fff0d --- /dev/null +++ b/esp32p4/src/lp_huk/state.rs @@ -0,0 +1,36 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +#[doc = "Field `STATE` reader - The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY."] +pub type STATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY."] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATE") + .field("state", &format_args!("{}", self.state().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "HUK Generator state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATE_SPEC; +impl crate::RegisterSpec for STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for STATE_SPEC {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for STATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_huk/status.rs b/esp32p4/src/lp_huk/status.rs new file mode 100644 index 0000000000..4810318105 --- /dev/null +++ b/esp32p4/src/lp_huk/status.rs @@ -0,0 +1,44 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `STATUS` reader - The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. 2: HUK is generated but invalid. 3: reserved."] +pub type STATUS_R = crate::FieldReader; +#[doc = "Field `RISK_LEVEL` reader - The risk level of HUK. 0-6: the higher the risk level is, the more error bits there are in the PUF SRAM. 7: Error Level, HUK is invalid."] +pub type RISK_LEVEL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. 2: HUK is generated but invalid. 3: reserved."] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:4 - The risk level of HUK. 0-6: the higher the risk level is, the more error bits there are in the PUF SRAM. 7: Error Level, HUK is invalid."] + #[inline(always)] + pub fn risk_level(&self) -> RISK_LEVEL_R { + RISK_LEVEL_R::new(((self.bits >> 2) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field("status", &format_args!("{}", self.status().bits())) + .field("risk_level", &format_args!("{}", self.risk_level().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "HUK Generator HUK status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0.rs b/esp32p4/src/lp_i2c0.rs new file mode 100644 index 0000000000..8e122e755a --- /dev/null +++ b/esp32p4/src/lp_i2c0.rs @@ -0,0 +1,352 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + scl_low_period: SCL_LOW_PERIOD, + ctr: CTR, + sr: SR, + to: TO, + _reserved4: [u8; 0x04], + fifo_st: FIFO_ST, + fifo_conf: FIFO_CONF, + data: DATA, + int_raw: INT_RAW, + int_clr: INT_CLR, + int_ena: INT_ENA, + int_status: INT_STATUS, + sda_hold: SDA_HOLD, + sda_sample: SDA_SAMPLE, + scl_high_period: SCL_HIGH_PERIOD, + _reserved14: [u8; 0x04], + scl_start_hold: SCL_START_HOLD, + scl_rstart_setup: SCL_RSTART_SETUP, + scl_stop_hold: SCL_STOP_HOLD, + scl_stop_setup: SCL_STOP_SETUP, + filter_cfg: FILTER_CFG, + clk_conf: CLK_CONF, + comd0: COMD0, + comd1: COMD1, + comd2: COMD2, + comd3: COMD3, + comd4: COMD4, + comd5: COMD5, + comd6: COMD6, + comd7: COMD7, + scl_st_time_out: SCL_ST_TIME_OUT, + scl_main_st_time_out: SCL_MAIN_ST_TIME_OUT, + scl_sp_conf: SCL_SP_CONF, + _reserved31: [u8; 0x74], + date: DATE, + _reserved32: [u8; 0x04], + txfifo_start_addr: TXFIFO_START_ADDR, + _reserved33: [u8; 0x7c], + rxfifo_start_addr: RXFIFO_START_ADDR, +} +impl RegisterBlock { + #[doc = "0x00 - Configures the low level width of the SCL Clock"] + #[inline(always)] + pub const fn scl_low_period(&self) -> &SCL_LOW_PERIOD { + &self.scl_low_period + } + #[doc = "0x04 - Transmission setting"] + #[inline(always)] + pub const fn ctr(&self) -> &CTR { + &self.ctr + } + #[doc = "0x08 - Describe I2C work status."] + #[inline(always)] + pub const fn sr(&self) -> &SR { + &self.sr + } + #[doc = "0x0c - Setting time out control for receiving data."] + #[inline(always)] + pub const fn to(&self) -> &TO { + &self.to + } + #[doc = "0x14 - FIFO status register."] + #[inline(always)] + pub const fn fifo_st(&self) -> &FIFO_ST { + &self.fifo_st + } + #[doc = "0x18 - FIFO configuration register."] + #[inline(always)] + pub const fn fifo_conf(&self) -> &FIFO_CONF { + &self.fifo_conf + } + #[doc = "0x1c - Rx FIFO read data."] + #[inline(always)] + pub const fn data(&self) -> &DATA { + &self.data + } + #[doc = "0x20 - Raw interrupt status"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x24 - Interrupt clear bits"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x28 - Interrupt enable bits"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x2c - Status of captured I2C communication events"] + #[inline(always)] + pub const fn int_status(&self) -> &INT_STATUS { + &self.int_status + } + #[doc = "0x30 - Configures the hold time after a negative SCL edge."] + #[inline(always)] + pub const fn sda_hold(&self) -> &SDA_HOLD { + &self.sda_hold + } + #[doc = "0x34 - Configures the sample time after a positive SCL edge."] + #[inline(always)] + pub const fn sda_sample(&self) -> &SDA_SAMPLE { + &self.sda_sample + } + #[doc = "0x38 - Configures the high level width of SCL"] + #[inline(always)] + pub const fn scl_high_period(&self) -> &SCL_HIGH_PERIOD { + &self.scl_high_period + } + #[doc = "0x40 - Configures the delay between the SDA and SCL negative edge for a start condition"] + #[inline(always)] + pub const fn scl_start_hold(&self) -> &SCL_START_HOLD { + &self.scl_start_hold + } + #[doc = "0x44 - Configures the delay between the positive edge of SCL and the negative edge of SDA"] + #[inline(always)] + pub const fn scl_rstart_setup(&self) -> &SCL_RSTART_SETUP { + &self.scl_rstart_setup + } + #[doc = "0x48 - Configures the delay after the SCL clock edge for a stop condition"] + #[inline(always)] + pub const fn scl_stop_hold(&self) -> &SCL_STOP_HOLD { + &self.scl_stop_hold + } + #[doc = "0x4c - Configures the delay between the SDA and SCL positive edge for a stop condition"] + #[inline(always)] + pub const fn scl_stop_setup(&self) -> &SCL_STOP_SETUP { + &self.scl_stop_setup + } + #[doc = "0x50 - SCL and SDA filter configuration register"] + #[inline(always)] + pub const fn filter_cfg(&self) -> &FILTER_CFG { + &self.filter_cfg + } + #[doc = "0x54 - I2C CLK configuration register"] + #[inline(always)] + pub const fn clk_conf(&self) -> &CLK_CONF { + &self.clk_conf + } + #[doc = "0x58 - I2C command register 0"] + #[inline(always)] + pub const fn comd0(&self) -> &COMD0 { + &self.comd0 + } + #[doc = "0x5c - I2C command register 1"] + #[inline(always)] + pub const fn comd1(&self) -> &COMD1 { + &self.comd1 + } + #[doc = "0x60 - I2C command register 2"] + #[inline(always)] + pub const fn comd2(&self) -> &COMD2 { + &self.comd2 + } + #[doc = "0x64 - I2C command register 3"] + #[inline(always)] + pub const fn comd3(&self) -> &COMD3 { + &self.comd3 + } + #[doc = "0x68 - I2C command register 4"] + #[inline(always)] + pub const fn comd4(&self) -> &COMD4 { + &self.comd4 + } + #[doc = "0x6c - I2C command register 5"] + #[inline(always)] + pub const fn comd5(&self) -> &COMD5 { + &self.comd5 + } + #[doc = "0x70 - I2C command register 6"] + #[inline(always)] + pub const fn comd6(&self) -> &COMD6 { + &self.comd6 + } + #[doc = "0x74 - I2C command register 7"] + #[inline(always)] + pub const fn comd7(&self) -> &COMD7 { + &self.comd7 + } + #[doc = "0x78 - SCL status time out register"] + #[inline(always)] + pub const fn scl_st_time_out(&self) -> &SCL_ST_TIME_OUT { + &self.scl_st_time_out + } + #[doc = "0x7c - SCL main status time out register"] + #[inline(always)] + pub const fn scl_main_st_time_out(&self) -> &SCL_MAIN_ST_TIME_OUT { + &self.scl_main_st_time_out + } + #[doc = "0x80 - Power configuration register"] + #[inline(always)] + pub const fn scl_sp_conf(&self) -> &SCL_SP_CONF { + &self.scl_sp_conf + } + #[doc = "0xf8 - Version register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } + #[doc = "0x100 - I2C TXFIFO base address register"] + #[inline(always)] + pub const fn txfifo_start_addr(&self) -> &TXFIFO_START_ADDR { + &self.txfifo_start_addr + } + #[doc = "0x180 - I2C RXFIFO base address register"] + #[inline(always)] + pub const fn rxfifo_start_addr(&self) -> &RXFIFO_START_ADDR { + &self.rxfifo_start_addr + } +} +#[doc = "SCL_LOW_PERIOD (rw) register accessor: Configures the low level width of the SCL Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_low_period::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_low_period::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_low_period`] module"] +pub type SCL_LOW_PERIOD = crate::Reg; +#[doc = "Configures the low level width of the SCL Clock"] +pub mod scl_low_period; +#[doc = "CTR (rw) register accessor: Transmission setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"] +pub type CTR = crate::Reg; +#[doc = "Transmission setting"] +pub mod ctr; +#[doc = "SR (r) register accessor: Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"] +pub type SR = crate::Reg; +#[doc = "Describe I2C work status."] +pub mod sr; +#[doc = "TO (rw) register accessor: Setting time out control for receiving data.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`to::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`to::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@to`] module"] +pub type TO = crate::Reg; +#[doc = "Setting time out control for receiving data."] +pub mod to; +#[doc = "FIFO_ST (r) register accessor: FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_st`] module"] +pub type FIFO_ST = crate::Reg; +#[doc = "FIFO status register."] +pub mod fifo_st; +#[doc = "FIFO_CONF (rw) register accessor: FIFO configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_conf`] module"] +pub type FIFO_CONF = crate::Reg; +#[doc = "FIFO configuration register."] +pub mod fifo_conf; +#[doc = "DATA (r) register accessor: Rx FIFO read data.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"] +pub type DATA = crate::Reg; +#[doc = "Rx FIFO read data."] +pub mod data; +#[doc = "INT_RAW (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Raw interrupt status"] +pub mod int_raw; +#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear bits"] +pub mod int_clr; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable bits"] +pub mod int_ena; +#[doc = "INT_STATUS (r) register accessor: Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_status`] module"] +pub type INT_STATUS = crate::Reg; +#[doc = "Status of captured I2C communication events"] +pub mod int_status; +#[doc = "SDA_HOLD (rw) register accessor: Configures the hold time after a negative SCL edge.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_hold`] module"] +pub type SDA_HOLD = crate::Reg; +#[doc = "Configures the hold time after a negative SCL edge."] +pub mod sda_hold; +#[doc = "SDA_SAMPLE (rw) register accessor: Configures the sample time after a positive SCL edge.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_sample::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_sample::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sda_sample`] module"] +pub type SDA_SAMPLE = crate::Reg; +#[doc = "Configures the sample time after a positive SCL edge."] +pub mod sda_sample; +#[doc = "SCL_HIGH_PERIOD (rw) register accessor: Configures the high level width of SCL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_high_period::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_high_period::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_high_period`] module"] +pub type SCL_HIGH_PERIOD = crate::Reg; +#[doc = "Configures the high level width of SCL"] +pub mod scl_high_period; +#[doc = "SCL_START_HOLD (rw) register accessor: Configures the delay between the SDA and SCL negative edge for a start condition\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_start_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_start_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_start_hold`] module"] +pub type SCL_START_HOLD = crate::Reg; +#[doc = "Configures the delay between the SDA and SCL negative edge for a start condition"] +pub mod scl_start_hold; +#[doc = "SCL_RSTART_SETUP (rw) register accessor: Configures the delay between the positive edge of SCL and the negative edge of SDA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_rstart_setup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_rstart_setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_rstart_setup`] module"] +pub type SCL_RSTART_SETUP = crate::Reg; +#[doc = "Configures the delay between the positive edge of SCL and the negative edge of SDA"] +pub mod scl_rstart_setup; +#[doc = "SCL_STOP_HOLD (rw) register accessor: Configures the delay after the SCL clock edge for a stop condition\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stop_hold`] module"] +pub type SCL_STOP_HOLD = crate::Reg; +#[doc = "Configures the delay after the SCL clock edge for a stop condition"] +pub mod scl_stop_hold; +#[doc = "SCL_STOP_SETUP (rw) register accessor: Configures the delay between the SDA and SCL positive edge for a stop condition\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_setup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_stop_setup`] module"] +pub type SCL_STOP_SETUP = crate::Reg; +#[doc = "Configures the delay between the SDA and SCL positive edge for a stop condition"] +pub mod scl_stop_setup; +#[doc = "FILTER_CFG (rw) register accessor: SCL and SDA filter configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_cfg`] module"] +pub type FILTER_CFG = crate::Reg; +#[doc = "SCL and SDA filter configuration register"] +pub mod filter_cfg; +#[doc = "CLK_CONF (rw) register accessor: I2C CLK configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"] +pub type CLK_CONF = crate::Reg; +#[doc = "I2C CLK configuration register"] +pub mod clk_conf; +#[doc = "COMD0 (rw) register accessor: I2C command register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd0`] module"] +pub type COMD0 = crate::Reg; +#[doc = "I2C command register 0"] +pub mod comd0; +#[doc = "COMD1 (rw) register accessor: I2C command register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd1`] module"] +pub type COMD1 = crate::Reg; +#[doc = "I2C command register 1"] +pub mod comd1; +#[doc = "COMD2 (rw) register accessor: I2C command register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd2`] module"] +pub type COMD2 = crate::Reg; +#[doc = "I2C command register 2"] +pub mod comd2; +#[doc = "COMD3 (rw) register accessor: I2C command register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd3`] module"] +pub type COMD3 = crate::Reg; +#[doc = "I2C command register 3"] +pub mod comd3; +#[doc = "COMD4 (rw) register accessor: I2C command register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd4`] module"] +pub type COMD4 = crate::Reg; +#[doc = "I2C command register 4"] +pub mod comd4; +#[doc = "COMD5 (rw) register accessor: I2C command register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd5`] module"] +pub type COMD5 = crate::Reg; +#[doc = "I2C command register 5"] +pub mod comd5; +#[doc = "COMD6 (rw) register accessor: I2C command register 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd6`] module"] +pub type COMD6 = crate::Reg; +#[doc = "I2C command register 6"] +pub mod comd6; +#[doc = "COMD7 (rw) register accessor: I2C command register 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comd7`] module"] +pub type COMD7 = crate::Reg; +#[doc = "I2C command register 7"] +pub mod comd7; +#[doc = "SCL_ST_TIME_OUT (rw) register accessor: SCL status time out register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_st_time_out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_st_time_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_st_time_out`] module"] +pub type SCL_ST_TIME_OUT = crate::Reg; +#[doc = "SCL status time out register"] +pub mod scl_st_time_out; +#[doc = "SCL_MAIN_ST_TIME_OUT (rw) register accessor: SCL main status time out register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_main_st_time_out::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_main_st_time_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_main_st_time_out`] module"] +pub type SCL_MAIN_ST_TIME_OUT = crate::Reg; +#[doc = "SCL main status time out register"] +pub mod scl_main_st_time_out; +#[doc = "SCL_SP_CONF (rw) register accessor: Power configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_sp_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_sp_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scl_sp_conf`] module"] +pub type SCL_SP_CONF = crate::Reg; +#[doc = "Power configuration register"] +pub mod scl_sp_conf; +#[doc = "DATE (rw) register accessor: Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version register"] +pub mod date; +#[doc = "TXFIFO_START_ADDR (r) register accessor: I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifo_start_addr`] module"] +pub type TXFIFO_START_ADDR = crate::Reg; +#[doc = "I2C TXFIFO base address register"] +pub mod txfifo_start_addr; +#[doc = "RXFIFO_START_ADDR (r) register accessor: I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifo_start_addr`] module"] +pub type RXFIFO_START_ADDR = crate::Reg; +#[doc = "I2C RXFIFO base address register"] +pub mod rxfifo_start_addr; diff --git a/esp32p4/src/lp_i2c0/clk_conf.rs b/esp32p4/src/lp_i2c0/clk_conf.rs new file mode 100644 index 0000000000..3fdd0f77db --- /dev/null +++ b/esp32p4/src/lp_i2c0/clk_conf.rs @@ -0,0 +1,130 @@ +#[doc = "Register `CLK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SCLK_DIV_NUM` reader - the integral part of the fractional divisor for i2c module"] +pub type SCLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_NUM` writer - the integral part of the fractional divisor for i2c module"] +pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SCLK_DIV_A` reader - the numerator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_A_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_A` writer - the numerator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_DIV_B` reader - the denominator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_B_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_B` writer - the denominator of the fractional part of the fractional divisor for i2c module"] +pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_SEL` reader - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] +pub type SCLK_SEL_R = crate::BitReader; +#[doc = "Field `SCLK_SEL` writer - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] +pub type SCLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCLK_ACTIVE` reader - The clock switch for i2c module"] +pub type SCLK_ACTIVE_R = crate::BitReader; +#[doc = "Field `SCLK_ACTIVE` writer - The clock switch for i2c module"] +pub type SCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R { + SCLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_a(&self) -> SCLK_DIV_A_R { + SCLK_DIV_A_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + pub fn sclk_div_b(&self) -> SCLK_DIV_B_R { + SCLK_DIV_B_R::new(((self.bits >> 14) & 0x3f) as u8) + } + #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] + #[inline(always)] + pub fn sclk_sel(&self) -> SCLK_SEL_R { + SCLK_SEL_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The clock switch for i2c module"] + #[inline(always)] + pub fn sclk_active(&self) -> SCLK_ACTIVE_R { + SCLK_ACTIVE_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_CONF") + .field( + "sclk_div_num", + &format_args!("{}", self.sclk_div_num().bits()), + ) + .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits())) + .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits())) + .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit())) + .field("sclk_active", &format_args!("{}", self.sclk_active().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"] + #[inline(always)] + #[must_use] + pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W { + SCLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bits 8:13 - the numerator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + #[must_use] + pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W { + SCLK_DIV_A_W::new(self, 8) + } + #[doc = "Bits 14:19 - the denominator of the fractional part of the fractional divisor for i2c module"] + #[inline(always)] + #[must_use] + pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W { + SCLK_DIV_B_W::new(self, 14) + } + #[doc = "Bit 20 - The clock selection for i2c module:0-XTAL,1-CLK_8MHz."] + #[inline(always)] + #[must_use] + pub fn sclk_sel(&mut self) -> SCLK_SEL_W { + SCLK_SEL_W::new(self, 20) + } + #[doc = "Bit 21 - The clock switch for i2c module"] + #[inline(always)] + #[must_use] + pub fn sclk_active(&mut self) -> SCLK_ACTIVE_W { + SCLK_ACTIVE_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C CLK configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_CONF_SPEC; +impl crate::RegisterSpec for CLK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"] +impl crate::Readable for CLK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"] +impl crate::Writable for CLK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_CONF to value 0x0020_0000"] +impl crate::Resettable for CLK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0020_0000; +} diff --git a/esp32p4/src/lp_i2c0/comd0.rs b/esp32p4/src/lp_i2c0/comd0.rs new file mode 100644 index 0000000000..3946fa9327 --- /dev/null +++ b/esp32p4/src/lp_i2c0/comd0.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD0` reader"] +pub type R = crate::R; +#[doc = "Register `COMD0` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND0` reader - Configures command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information."] +pub type COMMAND0_R = crate::FieldReader; +#[doc = "Field `COMMAND0` writer - Configures command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information."] +pub type COMMAND0_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND0_DONE` reader - Represents whether command 0 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND0_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND0_DONE` writer - Represents whether command 0 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND0_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information."] + #[inline(always)] + pub fn command0(&self) -> COMMAND0_R { + COMMAND0_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 0 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command0_done(&self) -> COMMAND0_DONE_R { + COMMAND0_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD0") + .field("command0", &format_args!("{}", self.command0().bits())) + .field( + "command0_done", + &format_args!("{}", self.command0_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information."] + #[inline(always)] + #[must_use] + pub fn command0(&mut self) -> COMMAND0_W { + COMMAND0_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 0 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command0_done(&mut self) -> COMMAND0_DONE_W { + COMMAND0_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD0_SPEC; +impl crate::RegisterSpec for COMD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd0::R`](R) reader structure"] +impl crate::Readable for COMD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd0::W`](W) writer structure"] +impl crate::Writable for COMD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD0 to value 0"] +impl crate::Resettable for COMD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/comd1.rs b/esp32p4/src/lp_i2c0/comd1.rs new file mode 100644 index 0000000000..043bb212fc --- /dev/null +++ b/esp32p4/src/lp_i2c0/comd1.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD1` reader"] +pub type R = crate::R; +#[doc = "Register `COMD1` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND1` reader - Configures command 1. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND1_R = crate::FieldReader; +#[doc = "Field `COMMAND1` writer - Configures command 1. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND1_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND1_DONE` reader - Represents whether command 1 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND1_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND1_DONE` writer - Represents whether command 1 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND1_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 1. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command1(&self) -> COMMAND1_R { + COMMAND1_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 1 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command1_done(&self) -> COMMAND1_DONE_R { + COMMAND1_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD1") + .field("command1", &format_args!("{}", self.command1().bits())) + .field( + "command1_done", + &format_args!("{}", self.command1_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 1. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command1(&mut self) -> COMMAND1_W { + COMMAND1_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 1 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command1_done(&mut self) -> COMMAND1_DONE_W { + COMMAND1_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD1_SPEC; +impl crate::RegisterSpec for COMD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd1::R`](R) reader structure"] +impl crate::Readable for COMD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd1::W`](W) writer structure"] +impl crate::Writable for COMD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD1 to value 0"] +impl crate::Resettable for COMD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/comd2.rs b/esp32p4/src/lp_i2c0/comd2.rs new file mode 100644 index 0000000000..eac951a0aa --- /dev/null +++ b/esp32p4/src/lp_i2c0/comd2.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD2` reader"] +pub type R = crate::R; +#[doc = "Register `COMD2` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND2` reader - Configures command 2. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND2_R = crate::FieldReader; +#[doc = "Field `COMMAND2` writer - Configures command 2. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND2_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND2_DONE` reader - Represents whether command 2 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND2_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND2_DONE` writer - Represents whether command 2 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND2_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 2. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command2(&self) -> COMMAND2_R { + COMMAND2_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 2 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command2_done(&self) -> COMMAND2_DONE_R { + COMMAND2_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD2") + .field("command2", &format_args!("{}", self.command2().bits())) + .field( + "command2_done", + &format_args!("{}", self.command2_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 2. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command2(&mut self) -> COMMAND2_W { + COMMAND2_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 2 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command2_done(&mut self) -> COMMAND2_DONE_W { + COMMAND2_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD2_SPEC; +impl crate::RegisterSpec for COMD2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd2::R`](R) reader structure"] +impl crate::Readable for COMD2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd2::W`](W) writer structure"] +impl crate::Writable for COMD2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD2 to value 0"] +impl crate::Resettable for COMD2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/comd3.rs b/esp32p4/src/lp_i2c0/comd3.rs new file mode 100644 index 0000000000..067c57abc0 --- /dev/null +++ b/esp32p4/src/lp_i2c0/comd3.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD3` reader"] +pub type R = crate::R; +#[doc = "Register `COMD3` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND3` reader - Configures command 3. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND3_R = crate::FieldReader; +#[doc = "Field `COMMAND3` writer - Configures command 3. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND3_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND3_DONE` reader - Represents whether command 3 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND3_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND3_DONE` writer - Represents whether command 3 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND3_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 3. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command3(&self) -> COMMAND3_R { + COMMAND3_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 3 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command3_done(&self) -> COMMAND3_DONE_R { + COMMAND3_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD3") + .field("command3", &format_args!("{}", self.command3().bits())) + .field( + "command3_done", + &format_args!("{}", self.command3_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 3. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command3(&mut self) -> COMMAND3_W { + COMMAND3_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 3 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command3_done(&mut self) -> COMMAND3_DONE_W { + COMMAND3_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD3_SPEC; +impl crate::RegisterSpec for COMD3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd3::R`](R) reader structure"] +impl crate::Readable for COMD3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd3::W`](W) writer structure"] +impl crate::Writable for COMD3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD3 to value 0"] +impl crate::Resettable for COMD3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/comd4.rs b/esp32p4/src/lp_i2c0/comd4.rs new file mode 100644 index 0000000000..1a095d781d --- /dev/null +++ b/esp32p4/src/lp_i2c0/comd4.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD4` reader"] +pub type R = crate::R; +#[doc = "Register `COMD4` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND4` reader - Configures command 4. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND4_R = crate::FieldReader; +#[doc = "Field `COMMAND4` writer - Configures command 4. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND4_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND4_DONE` reader - Represents whether command 4 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND4_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND4_DONE` writer - Represents whether command 4 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND4_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 4. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command4(&self) -> COMMAND4_R { + COMMAND4_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 4 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command4_done(&self) -> COMMAND4_DONE_R { + COMMAND4_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD4") + .field("command4", &format_args!("{}", self.command4().bits())) + .field( + "command4_done", + &format_args!("{}", self.command4_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 4. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command4(&mut self) -> COMMAND4_W { + COMMAND4_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 4 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command4_done(&mut self) -> COMMAND4_DONE_W { + COMMAND4_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD4_SPEC; +impl crate::RegisterSpec for COMD4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd4::R`](R) reader structure"] +impl crate::Readable for COMD4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd4::W`](W) writer structure"] +impl crate::Writable for COMD4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD4 to value 0"] +impl crate::Resettable for COMD4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/comd5.rs b/esp32p4/src/lp_i2c0/comd5.rs new file mode 100644 index 0000000000..62e79ca266 --- /dev/null +++ b/esp32p4/src/lp_i2c0/comd5.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD5` reader"] +pub type R = crate::R; +#[doc = "Register `COMD5` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND5` reader - Configures command 5. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND5_R = crate::FieldReader; +#[doc = "Field `COMMAND5` writer - Configures command 5. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND5_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND5_DONE` reader - Represents whether command 5 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND5_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND5_DONE` writer - Represents whether command 5 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND5_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 5. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command5(&self) -> COMMAND5_R { + COMMAND5_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 5 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command5_done(&self) -> COMMAND5_DONE_R { + COMMAND5_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD5") + .field("command5", &format_args!("{}", self.command5().bits())) + .field( + "command5_done", + &format_args!("{}", self.command5_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 5. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command5(&mut self) -> COMMAND5_W { + COMMAND5_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 5 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command5_done(&mut self) -> COMMAND5_DONE_W { + COMMAND5_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD5_SPEC; +impl crate::RegisterSpec for COMD5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd5::R`](R) reader structure"] +impl crate::Readable for COMD5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd5::W`](W) writer structure"] +impl crate::Writable for COMD5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD5 to value 0"] +impl crate::Resettable for COMD5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/comd6.rs b/esp32p4/src/lp_i2c0/comd6.rs new file mode 100644 index 0000000000..d9cd7d39ab --- /dev/null +++ b/esp32p4/src/lp_i2c0/comd6.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD6` reader"] +pub type R = crate::R; +#[doc = "Register `COMD6` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND6` reader - Configures command 6. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND6_R = crate::FieldReader; +#[doc = "Field `COMMAND6` writer - Configures command 6. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND6_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND6_DONE` reader - Represents whether command 6 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND6_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND6_DONE` writer - Represents whether command 6 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND6_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 6. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command6(&self) -> COMMAND6_R { + COMMAND6_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 6 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command6_done(&self) -> COMMAND6_DONE_R { + COMMAND6_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD6") + .field("command6", &format_args!("{}", self.command6().bits())) + .field( + "command6_done", + &format_args!("{}", self.command6_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 6. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command6(&mut self) -> COMMAND6_W { + COMMAND6_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 6 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command6_done(&mut self) -> COMMAND6_DONE_W { + COMMAND6_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD6_SPEC; +impl crate::RegisterSpec for COMD6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd6::R`](R) reader structure"] +impl crate::Readable for COMD6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd6::W`](W) writer structure"] +impl crate::Writable for COMD6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD6 to value 0"] +impl crate::Resettable for COMD6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/comd7.rs b/esp32p4/src/lp_i2c0/comd7.rs new file mode 100644 index 0000000000..5f80ce68c2 --- /dev/null +++ b/esp32p4/src/lp_i2c0/comd7.rs @@ -0,0 +1,82 @@ +#[doc = "Register `COMD7` reader"] +pub type R = crate::R; +#[doc = "Register `COMD7` writer"] +pub type W = crate::W; +#[doc = "Field `COMMAND7` reader - Configures command 7. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND7_R = crate::FieldReader; +#[doc = "Field `COMMAND7` writer - Configures command 7. See details in I2C_CMD0_REG\\[13:0\\]."] +pub type COMMAND7_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `COMMAND7_DONE` reader - Represents whether command 7 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND7_DONE_R = crate::BitReader; +#[doc = "Field `COMMAND7_DONE` writer - Represents whether command 7 is done in I2C Master mode. 0: Not done 1: Done"] +pub type COMMAND7_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Configures command 7. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + pub fn command7(&self) -> COMMAND7_R { + COMMAND7_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 31 - Represents whether command 7 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + pub fn command7_done(&self) -> COMMAND7_DONE_R { + COMMAND7_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMD7") + .field("command7", &format_args!("{}", self.command7().bits())) + .field( + "command7_done", + &format_args!("{}", self.command7_done().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Configures command 7. See details in I2C_CMD0_REG\\[13:0\\]."] + #[inline(always)] + #[must_use] + pub fn command7(&mut self) -> COMMAND7_W { + COMMAND7_W::new(self, 0) + } + #[doc = "Bit 31 - Represents whether command 7 is done in I2C Master mode. 0: Not done 1: Done"] + #[inline(always)] + #[must_use] + pub fn command7_done(&mut self) -> COMMAND7_DONE_W { + COMMAND7_DONE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2C command register 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comd7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comd7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMD7_SPEC; +impl crate::RegisterSpec for COMD7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comd7::R`](R) reader structure"] +impl crate::Readable for COMD7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comd7::W`](W) writer structure"] +impl crate::Writable for COMD7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMD7 to value 0"] +impl crate::Resettable for COMD7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/ctr.rs b/esp32p4/src/lp_i2c0/ctr.rs new file mode 100644 index 0000000000..2ef7ecf8fa --- /dev/null +++ b/esp32p4/src/lp_i2c0/ctr.rs @@ -0,0 +1,220 @@ +#[doc = "Register `CTR` reader"] +pub type R = crate::R; +#[doc = "Register `CTR` writer"] +pub type W = crate::W; +#[doc = "Field `SDA_FORCE_OUT` reader - Configures the SDA output mode 1: Direct output, 0: Open drain output."] +pub type SDA_FORCE_OUT_R = crate::BitReader; +#[doc = "Field `SDA_FORCE_OUT` writer - Configures the SDA output mode 1: Direct output, 0: Open drain output."] +pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_FORCE_OUT` reader - Configures the SCL output mode 1: Direct output, 0: Open drain output."] +pub type SCL_FORCE_OUT_R = crate::BitReader; +#[doc = "Field `SCL_FORCE_OUT` writer - Configures the SCL output mode 1: Direct output, 0: Open drain output."] +pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAMPLE_SCL_LEVEL` reader - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."] +pub type SAMPLE_SCL_LEVEL_R = crate::BitReader; +#[doc = "Field `SAMPLE_SCL_LEVEL` writer - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."] +pub type SAMPLE_SCL_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FULL_ACK_LEVEL` reader - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."] +pub type RX_FULL_ACK_LEVEL_R = crate::BitReader; +#[doc = "Field `RX_FULL_ACK_LEVEL` writer - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."] +pub type RX_FULL_ACK_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_START` writer - Configures to start sending the data in txfifo for slave. 0: No effect 1: Start"] +pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_LSB_FIRST` reader - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."] +pub type TX_LSB_FIRST_R = crate::BitReader; +#[doc = "Field `TX_LSB_FIRST` writer - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."] +pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_LSB_FIRST` reader - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."] +pub type RX_LSB_FIRST_R = crate::BitReader; +#[doc = "Field `RX_LSB_FIRST` writer - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."] +pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBITRATION_EN` reader - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"] +pub type ARBITRATION_EN_R = crate::BitReader; +#[doc = "Field `ARBITRATION_EN` writer - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"] +pub type ARBITRATION_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FSM_RST` writer - Configures to reset the SCL_FSM. 0: No effect 1: Reset"] +pub type FSM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CONF_UPGATE` writer - Configures this bit for synchronization 0: No effect 1: Synchronize"] +pub type CONF_UPGATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures the SDA output mode 1: Direct output, 0: Open drain output."] + #[inline(always)] + pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R { + SDA_FORCE_OUT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures the SCL output mode 1: Direct output, 0: Open drain output."] + #[inline(always)] + pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R { + SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."] + #[inline(always)] + pub fn sample_scl_level(&self) -> SAMPLE_SCL_LEVEL_R { + SAMPLE_SCL_LEVEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."] + #[inline(always)] + pub fn rx_full_ack_level(&self) -> RX_FULL_ACK_LEVEL_R { + RX_FULL_ACK_LEVEL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 6 - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."] + #[inline(always)] + pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R { + TX_LSB_FIRST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."] + #[inline(always)] + pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R { + RX_LSB_FIRST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"] + #[inline(always)] + pub fn arbitration_en(&self) -> ARBITRATION_EN_R { + ARBITRATION_EN_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTR") + .field( + "sda_force_out", + &format_args!("{}", self.sda_force_out().bit()), + ) + .field( + "scl_force_out", + &format_args!("{}", self.scl_force_out().bit()), + ) + .field( + "sample_scl_level", + &format_args!("{}", self.sample_scl_level().bit()), + ) + .field( + "rx_full_ack_level", + &format_args!("{}", self.rx_full_ack_level().bit()), + ) + .field( + "tx_lsb_first", + &format_args!("{}", self.tx_lsb_first().bit()), + ) + .field( + "rx_lsb_first", + &format_args!("{}", self.rx_lsb_first().bit()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field( + "arbitration_en", + &format_args!("{}", self.arbitration_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures the SDA output mode 1: Direct output, 0: Open drain output."] + #[inline(always)] + #[must_use] + pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W { + SDA_FORCE_OUT_W::new(self, 0) + } + #[doc = "Bit 1 - Configures the SCL output mode 1: Direct output, 0: Open drain output."] + #[inline(always)] + #[must_use] + pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W { + SCL_FORCE_OUT_W::new(self, 1) + } + #[doc = "Bit 2 - Configures the sample mode for SDA. 1: Sample SDA data on the SCL low level. 0: Sample SDA data on the SCL high level."] + #[inline(always)] + #[must_use] + pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W { + SAMPLE_SCL_LEVEL_W::new(self, 2) + } + #[doc = "Bit 3 - Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold."] + #[inline(always)] + #[must_use] + pub fn rx_full_ack_level(&mut self) -> RX_FULL_ACK_LEVEL_W { + RX_FULL_ACK_LEVEL_W::new(self, 3) + } + #[doc = "Bit 5 - Configures to start sending the data in txfifo for slave. 0: No effect 1: Start"] + #[inline(always)] + #[must_use] + pub fn trans_start(&mut self) -> TRANS_START_W { + TRANS_START_W::new(self, 5) + } + #[doc = "Bit 6 - Configures to control the sending order for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."] + #[inline(always)] + #[must_use] + pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W { + TX_LSB_FIRST_W::new(self, 6) + } + #[doc = "Bit 7 - Configures to control the storage order for received data. 1: receive data from the least significant bit 0: receive data from the most significant bit."] + #[inline(always)] + #[must_use] + pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W { + RX_LSB_FIRST_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether to gate clock signal for registers. 0: Force clock on for registers 1: Support clock only when registers are read or written to by software."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Configures to enable I2C bus arbitration detection. 0: No effect 1: Enable"] + #[inline(always)] + #[must_use] + pub fn arbitration_en(&mut self) -> ARBITRATION_EN_W { + ARBITRATION_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Configures to reset the SCL_FSM. 0: No effect 1: Reset"] + #[inline(always)] + #[must_use] + pub fn fsm_rst(&mut self) -> FSM_RST_W { + FSM_RST_W::new(self, 10) + } + #[doc = "Bit 11 - Configures this bit for synchronization 0: No effect 1: Synchronize"] + #[inline(always)] + #[must_use] + pub fn conf_upgate(&mut self) -> CONF_UPGATE_W { + CONF_UPGATE_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Transmission setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTR_SPEC; +impl crate::RegisterSpec for CTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctr::R`](R) reader structure"] +impl crate::Readable for CTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"] +impl crate::Writable for CTR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTR to value 0x0208"] +impl crate::Resettable for CTR_SPEC { + const RESET_VALUE: Self::Ux = 0x0208; +} diff --git a/esp32p4/src/lp_i2c0/data.rs b/esp32p4/src/lp_i2c0/data.rs new file mode 100644 index 0000000000..f3bab00b70 --- /dev/null +++ b/esp32p4/src/lp_i2c0/data.rs @@ -0,0 +1,36 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_RDATA` reader - Represents the value of RXFIFO read data."] +pub type FIFO_RDATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Represents the value of RXFIFO read data."] + #[inline(always)] + pub fn fifo_rdata(&self) -> FIFO_RDATA_R { + FIFO_RDATA_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA") + .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Rx FIFO read data.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DATA_SPEC {} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/date.rs b/esp32p4/src/lp_i2c0/date.rs new file mode 100644 index 0000000000..b99a6fc80d --- /dev/null +++ b/esp32p4/src/lp_i2c0/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - Version control register."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - Version control register."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Version control register."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Version control register."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0220_1143"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_1143; +} diff --git a/esp32p4/src/lp_i2c0/fifo_conf.rs b/esp32p4/src/lp_i2c0/fifo_conf.rs new file mode 100644 index 0000000000..9c6711711e --- /dev/null +++ b/esp32p4/src/lp_i2c0/fifo_conf.rs @@ -0,0 +1,149 @@ +#[doc = "Register `FIFO_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_WM_THRHD` reader - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."] +pub type RXFIFO_WM_THRHD_R = crate::FieldReader; +#[doc = "Field `RXFIFO_WM_THRHD` writer - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."] +pub type RXFIFO_WM_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TXFIFO_WM_THRHD` reader - Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[3:0\\], reg_txfifo_wm_int_raw bit will be valid."] +pub type TXFIFO_WM_THRHD_R = crate::FieldReader; +#[doc = "Field `TXFIFO_WM_THRHD` writer - Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[3:0\\], reg_txfifo_wm_int_raw bit will be valid."] +pub type TXFIFO_WM_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `NONFIFO_EN` reader - Configures to enable APB nonfifo access."] +pub type NONFIFO_EN_R = crate::BitReader; +#[doc = "Field `NONFIFO_EN` writer - Configures to enable APB nonfifo access."] +pub type NONFIFO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFO_RST` reader - Configures to reset RXFIFO. 0: No effect 1: Reset"] +pub type RX_FIFO_RST_R = crate::BitReader; +#[doc = "Field `RX_FIFO_RST` writer - Configures to reset RXFIFO. 0: No effect 1: Reset"] +pub type RX_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_FIFO_RST` reader - Configures to reset TXFIFO. 0: No effect 1: Reset"] +pub type TX_FIFO_RST_R = crate::BitReader; +#[doc = "Field `TX_FIFO_RST` writer - Configures to reset TXFIFO. 0: No effect 1: Reset"] +pub type TX_FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_PRT_EN` reader - Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. 0: No effect 1: Enable"] +pub type FIFO_PRT_EN_R = crate::BitReader; +#[doc = "Field `FIFO_PRT_EN` writer - Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. 0: No effect 1: Enable"] +pub type FIFO_PRT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."] + #[inline(always)] + pub fn rxfifo_wm_thrhd(&self) -> RXFIFO_WM_THRHD_R { + RXFIFO_WM_THRHD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 5:8 - Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[3:0\\], reg_txfifo_wm_int_raw bit will be valid."] + #[inline(always)] + pub fn txfifo_wm_thrhd(&self) -> TXFIFO_WM_THRHD_R { + TXFIFO_WM_THRHD_R::new(((self.bits >> 5) & 0x0f) as u8) + } + #[doc = "Bit 10 - Configures to enable APB nonfifo access."] + #[inline(always)] + pub fn nonfifo_en(&self) -> NONFIFO_EN_R { + NONFIFO_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - Configures to reset RXFIFO. 0: No effect 1: Reset"] + #[inline(always)] + pub fn rx_fifo_rst(&self) -> RX_FIFO_RST_R { + RX_FIFO_RST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures to reset TXFIFO. 0: No effect 1: Reset"] + #[inline(always)] + pub fn tx_fifo_rst(&self) -> TX_FIFO_RST_R { + TX_FIFO_RST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. 0: No effect 1: Enable"] + #[inline(always)] + pub fn fifo_prt_en(&self) -> FIFO_PRT_EN_R { + FIFO_PRT_EN_R::new(((self.bits >> 14) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO_CONF") + .field( + "rxfifo_wm_thrhd", + &format_args!("{}", self.rxfifo_wm_thrhd().bits()), + ) + .field( + "txfifo_wm_thrhd", + &format_args!("{}", self.txfifo_wm_thrhd().bits()), + ) + .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit())) + .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit())) + .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit())) + .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."] + #[inline(always)] + #[must_use] + pub fn rxfifo_wm_thrhd(&mut self) -> RXFIFO_WM_THRHD_W { + RXFIFO_WM_THRHD_W::new(self, 0) + } + #[doc = "Bits 5:8 - Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd\\[3:0\\], reg_txfifo_wm_int_raw bit will be valid."] + #[inline(always)] + #[must_use] + pub fn txfifo_wm_thrhd(&mut self) -> TXFIFO_WM_THRHD_W { + TXFIFO_WM_THRHD_W::new(self, 5) + } + #[doc = "Bit 10 - Configures to enable APB nonfifo access."] + #[inline(always)] + #[must_use] + pub fn nonfifo_en(&mut self) -> NONFIFO_EN_W { + NONFIFO_EN_W::new(self, 10) + } + #[doc = "Bit 12 - Configures to reset RXFIFO. 0: No effect 1: Reset"] + #[inline(always)] + #[must_use] + pub fn rx_fifo_rst(&mut self) -> RX_FIFO_RST_W { + RX_FIFO_RST_W::new(self, 12) + } + #[doc = "Bit 13 - Configures to reset TXFIFO. 0: No effect 1: Reset"] + #[inline(always)] + #[must_use] + pub fn tx_fifo_rst(&mut self) -> TX_FIFO_RST_W { + TX_FIFO_RST_W::new(self, 13) + } + #[doc = "Bit 14 - Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. 0: No effect 1: Enable"] + #[inline(always)] + #[must_use] + pub fn fifo_prt_en(&mut self) -> FIFO_PRT_EN_W { + FIFO_PRT_EN_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "FIFO configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_CONF_SPEC; +impl crate::RegisterSpec for FIFO_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_conf::R`](R) reader structure"] +impl crate::Readable for FIFO_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo_conf::W`](W) writer structure"] +impl crate::Writable for FIFO_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIFO_CONF to value 0x4046"] +impl crate::Resettable for FIFO_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x4046; +} diff --git a/esp32p4/src/lp_i2c0/fifo_st.rs b/esp32p4/src/lp_i2c0/fifo_st.rs new file mode 100644 index 0000000000..c55c988073 --- /dev/null +++ b/esp32p4/src/lp_i2c0/fifo_st.rs @@ -0,0 +1,72 @@ +#[doc = "Register `FIFO_ST` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_RADDR` reader - Represents the offset address of the APB reading from RXFIFO"] +pub type RXFIFO_RADDR_R = crate::FieldReader; +#[doc = "Field `RXFIFO_WADDR` reader - Represents the offset address of i2c module receiving data and writing to RXFIFO."] +pub type RXFIFO_WADDR_R = crate::FieldReader; +#[doc = "Field `TXFIFO_RADDR` reader - Represents the offset address of i2c module reading from TXFIFO."] +pub type TXFIFO_RADDR_R = crate::FieldReader; +#[doc = "Field `TXFIFO_WADDR` reader - Represents the offset address of APB bus writing to TXFIFO."] +pub type TXFIFO_WADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Represents the offset address of the APB reading from RXFIFO"] + #[inline(always)] + pub fn rxfifo_raddr(&self) -> RXFIFO_RADDR_R { + RXFIFO_RADDR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 5:8 - Represents the offset address of i2c module receiving data and writing to RXFIFO."] + #[inline(always)] + pub fn rxfifo_waddr(&self) -> RXFIFO_WADDR_R { + RXFIFO_WADDR_R::new(((self.bits >> 5) & 0x0f) as u8) + } + #[doc = "Bits 10:13 - Represents the offset address of i2c module reading from TXFIFO."] + #[inline(always)] + pub fn txfifo_raddr(&self) -> TXFIFO_RADDR_R { + TXFIFO_RADDR_R::new(((self.bits >> 10) & 0x0f) as u8) + } + #[doc = "Bits 15:18 - Represents the offset address of APB bus writing to TXFIFO."] + #[inline(always)] + pub fn txfifo_waddr(&self) -> TXFIFO_WADDR_R { + TXFIFO_WADDR_R::new(((self.bits >> 15) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO_ST") + .field( + "rxfifo_raddr", + &format_args!("{}", self.rxfifo_raddr().bits()), + ) + .field( + "rxfifo_waddr", + &format_args!("{}", self.rxfifo_waddr().bits()), + ) + .field( + "txfifo_raddr", + &format_args!("{}", self.txfifo_raddr().bits()), + ) + .field( + "txfifo_waddr", + &format_args!("{}", self.txfifo_waddr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_ST_SPEC; +impl crate::RegisterSpec for FIFO_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_st::R`](R) reader structure"] +impl crate::Readable for FIFO_ST_SPEC {} +#[doc = "`reset()` method sets FIFO_ST to value 0"] +impl crate::Resettable for FIFO_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/filter_cfg.rs b/esp32p4/src/lp_i2c0/filter_cfg.rs new file mode 100644 index 0000000000..6a9d0e9d0d --- /dev/null +++ b/esp32p4/src/lp_i2c0/filter_cfg.rs @@ -0,0 +1,123 @@ +#[doc = "Register `FILTER_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FILTER_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_FILTER_THRES` reader - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] +pub type SCL_FILTER_THRES_R = crate::FieldReader; +#[doc = "Field `SCL_FILTER_THRES` writer - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] +pub type SCL_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SDA_FILTER_THRES` reader - Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] +pub type SDA_FILTER_THRES_R = crate::FieldReader; +#[doc = "Field `SDA_FILTER_THRES` writer - Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] +pub type SDA_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SCL_FILTER_EN` reader - Configures to enable the filter function for SCL."] +pub type SCL_FILTER_EN_R = crate::BitReader; +#[doc = "Field `SCL_FILTER_EN` writer - Configures to enable the filter function for SCL."] +pub type SCL_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDA_FILTER_EN` reader - Configures to enable the filter function for SDA."] +pub type SDA_FILTER_EN_R = crate::BitReader; +#[doc = "Field `SDA_FILTER_EN` writer - Configures to enable the filter function for SDA."] +pub type SDA_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_filter_thres(&self) -> SCL_FILTER_THRES_R { + SCL_FILTER_THRES_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn sda_filter_thres(&self) -> SDA_FILTER_THRES_R { + SDA_FILTER_THRES_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8 - Configures to enable the filter function for SCL."] + #[inline(always)] + pub fn scl_filter_en(&self) -> SCL_FILTER_EN_R { + SCL_FILTER_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures to enable the filter function for SDA."] + #[inline(always)] + pub fn sda_filter_en(&self) -> SDA_FILTER_EN_R { + SDA_FILTER_EN_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FILTER_CFG") + .field( + "scl_filter_thres", + &format_args!("{}", self.scl_filter_thres().bits()), + ) + .field( + "sda_filter_thres", + &format_args!("{}", self.sda_filter_thres().bits()), + ) + .field( + "scl_filter_en", + &format_args!("{}", self.scl_filter_en().bit()), + ) + .field( + "sda_filter_en", + &format_args!("{}", self.sda_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_filter_thres(&mut self) -> SCL_FILTER_THRES_W { + SCL_FILTER_THRES_W::new(self, 0) + } + #[doc = "Bits 4:7 - Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn sda_filter_thres(&mut self) -> SDA_FILTER_THRES_W { + SDA_FILTER_THRES_W::new(self, 4) + } + #[doc = "Bit 8 - Configures to enable the filter function for SCL."] + #[inline(always)] + #[must_use] + pub fn scl_filter_en(&mut self) -> SCL_FILTER_EN_W { + SCL_FILTER_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Configures to enable the filter function for SDA."] + #[inline(always)] + #[must_use] + pub fn sda_filter_en(&mut self) -> SDA_FILTER_EN_W { + SDA_FILTER_EN_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SCL and SDA filter configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FILTER_CFG_SPEC; +impl crate::RegisterSpec for FILTER_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`filter_cfg::R`](R) reader structure"] +impl crate::Readable for FILTER_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`filter_cfg::W`](W) writer structure"] +impl crate::Writable for FILTER_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FILTER_CFG to value 0x0300"] +impl crate::Resettable for FILTER_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0300; +} diff --git a/esp32p4/src/lp_i2c0/int_clr.rs b/esp32p4/src/lp_i2c0/int_clr.rs new file mode 100644 index 0000000000..665e8505ff --- /dev/null +++ b/esp32p4/src/lp_i2c0/int_clr.rs @@ -0,0 +1,162 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_WM_INT_CLR` writer - Write 1 to clear I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_WM_INT_CLR` writer - Write 1 to clear I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF_INT_CLR` writer - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `END_DETECT_INT_CLR` writer - Write 1 to clear the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BYTE_TRANS_DONE_INT_CLR` writer - Write 1 to clear the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBITRATION_LOST_INT_CLR` writer - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MST_TXFIFO_UDF_INT_CLR` writer - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_COMPLETE_INT_CLR` writer - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIME_OUT_INT_CLR` writer - Write 1 to clear the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_START_INT_CLR` writer - Write 1 to clear the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACK_INT_CLR` writer - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_OVF_INT_CLR` writer - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_UDF_INT_CLR` writer - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_ST_TO_INT_CLR` writer - Write 1 to clear I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_MAIN_ST_TO_INT_CLR` writer - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DET_START_INT_CLR` writer - Write 1 to clear I2C_DET_START_INT interrupt."] +pub type DET_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to clear I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_wm_int_clr(&mut self) -> RXFIFO_WM_INT_CLR_W { + RXFIFO_WM_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to clear I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn txfifo_wm_int_clr(&mut self) -> TXFIFO_WM_INT_CLR_W { + TXFIFO_WM_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to clear I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_ovf_int_clr(&mut self) -> RXFIFO_OVF_INT_CLR_W { + RXFIFO_OVF_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to clear the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn end_detect_int_clr(&mut self) -> END_DETECT_INT_CLR_W { + END_DETECT_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to clear the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn byte_trans_done_int_clr(&mut self) -> BYTE_TRANS_DONE_INT_CLR_W { + BYTE_TRANS_DONE_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn arbitration_lost_int_clr(&mut self) -> ARBITRATION_LOST_INT_CLR_W { + ARBITRATION_LOST_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn mst_txfifo_udf_int_clr(&mut self) -> MST_TXFIFO_UDF_INT_CLR_W { + MST_TXFIFO_UDF_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn trans_complete_int_clr(&mut self) -> TRANS_COMPLETE_INT_CLR_W { + TRANS_COMPLETE_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Write 1 to clear the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn time_out_int_clr(&mut self) -> TIME_OUT_INT_CLR_W { + TIME_OUT_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Write 1 to clear the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn trans_start_int_clr(&mut self) -> TRANS_START_INT_CLR_W { + TRANS_START_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn nack_int_clr(&mut self) -> NACK_INT_CLR_W { + NACK_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Write 1 to clear I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn txfifo_ovf_int_clr(&mut self) -> TXFIFO_OVF_INT_CLR_W { + TXFIFO_OVF_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Write 1 to clear I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_udf_int_clr(&mut self) -> RXFIFO_UDF_INT_CLR_W { + RXFIFO_UDF_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Write 1 to clear I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn scl_st_to_int_clr(&mut self) -> SCL_ST_TO_INT_CLR_W { + SCL_ST_TO_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn scl_main_st_to_int_clr(&mut self) -> SCL_MAIN_ST_TO_INT_CLR_W { + SCL_MAIN_ST_TO_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Write 1 to clear I2C_DET_START_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn det_start_int_clr(&mut self) -> DET_START_INT_CLR_W { + DET_START_INT_CLR_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/int_ena.rs b/esp32p4/src/lp_i2c0/int_ena.rs new file mode 100644 index 0000000000..a8fbdd6f51 --- /dev/null +++ b/esp32p4/src/lp_i2c0/int_ena.rs @@ -0,0 +1,351 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_WM_INT_ENA` reader - Write 1 to anable I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_WM_INT_ENA` writer - Write 1 to anable I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_WM_INT_ENA` reader - Write 1 to anable I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_INT_ENA_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM_INT_ENA` writer - Write 1 to anable I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF_INT_ENA` reader - Write 1 to anable I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_ENA` writer - Write 1 to anable I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `END_DETECT_INT_ENA` reader - Write 1 to anable the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_INT_ENA_R = crate::BitReader; +#[doc = "Field `END_DETECT_INT_ENA` writer - Write 1 to anable the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BYTE_TRANS_DONE_INT_ENA` reader - Write 1 to anable the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE_INT_ENA` writer - Write 1 to anable the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBITRATION_LOST_INT_ENA` reader - Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_INT_ENA_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST_INT_ENA` writer - Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MST_TXFIFO_UDF_INT_ENA` reader - Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_INT_ENA_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF_INT_ENA` writer - Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_COMPLETE_INT_ENA` reader - Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_INT_ENA_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE_INT_ENA` writer - Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIME_OUT_INT_ENA` reader - Write 1 to anable the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIME_OUT_INT_ENA` writer - Write 1 to anable the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_START_INT_ENA` reader - Write 1 to anable the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_INT_ENA_R = crate::BitReader; +#[doc = "Field `TRANS_START_INT_ENA` writer - Write 1 to anable the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACK_INT_ENA` reader - Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_INT_ENA_R = crate::BitReader; +#[doc = "Field `NACK_INT_ENA` writer - Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_OVF_INT_ENA` reader - Write 1 to anable I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF_INT_ENA` writer - Write 1 to anable I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_UDF_INT_ENA` reader - Write 1 to anable I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF_INT_ENA` writer - Write 1 to anable I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_ST_TO_INT_ENA` reader - Write 1 to anable I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_INT_ENA_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO_INT_ENA` writer - Write 1 to anable I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_MAIN_ST_TO_INT_ENA` reader - Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_INT_ENA_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO_INT_ENA` writer - Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DET_START_INT_ENA` reader - Write 1 to anable I2C_DET_START_INT interrupt."] +pub type DET_START_INT_ENA_R = crate::BitReader; +#[doc = "Field `DET_START_INT_ENA` writer - Write 1 to anable I2C_DET_START_INT interrupt."] +pub type DET_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 to anable I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn rxfifo_wm_int_ena(&self) -> RXFIFO_WM_INT_ENA_R { + RXFIFO_WM_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to anable I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn txfifo_wm_int_ena(&self) -> TXFIFO_WM_INT_ENA_R { + TXFIFO_WM_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 to anable I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R { + RXFIFO_OVF_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1 to anable the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn end_detect_int_ena(&self) -> END_DETECT_INT_ENA_R { + END_DETECT_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write 1 to anable the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn byte_trans_done_int_ena(&self) -> BYTE_TRANS_DONE_INT_ENA_R { + BYTE_TRANS_DONE_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + pub fn arbitration_lost_int_ena(&self) -> ARBITRATION_LOST_INT_ENA_R { + ARBITRATION_LOST_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn mst_txfifo_udf_int_ena(&self) -> MST_TXFIFO_UDF_INT_ENA_R { + MST_TXFIFO_UDF_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn trans_complete_int_ena(&self) -> TRANS_COMPLETE_INT_ENA_R { + TRANS_COMPLETE_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Write 1 to anable the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + pub fn time_out_int_ena(&self) -> TIME_OUT_INT_ENA_R { + TIME_OUT_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write 1 to anable the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + pub fn trans_start_int_ena(&self) -> TRANS_START_INT_ENA_R { + TRANS_START_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn nack_int_ena(&self) -> NACK_INT_ENA_R { + NACK_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Write 1 to anable I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn txfifo_ovf_int_ena(&self) -> TXFIFO_OVF_INT_ENA_R { + TXFIFO_OVF_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Write 1 to anable I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_udf_int_ena(&self) -> RXFIFO_UDF_INT_ENA_R { + RXFIFO_UDF_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Write 1 to anable I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_st_to_int_ena(&self) -> SCL_ST_TO_INT_ENA_R { + SCL_ST_TO_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_main_st_to_int_ena(&self) -> SCL_MAIN_ST_TO_INT_ENA_R { + SCL_MAIN_ST_TO_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Write 1 to anable I2C_DET_START_INT interrupt."] + #[inline(always)] + pub fn det_start_int_ena(&self) -> DET_START_INT_ENA_R { + DET_START_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "rxfifo_wm_int_ena", + &format_args!("{}", self.rxfifo_wm_int_ena().bit()), + ) + .field( + "txfifo_wm_int_ena", + &format_args!("{}", self.txfifo_wm_int_ena().bit()), + ) + .field( + "rxfifo_ovf_int_ena", + &format_args!("{}", self.rxfifo_ovf_int_ena().bit()), + ) + .field( + "end_detect_int_ena", + &format_args!("{}", self.end_detect_int_ena().bit()), + ) + .field( + "byte_trans_done_int_ena", + &format_args!("{}", self.byte_trans_done_int_ena().bit()), + ) + .field( + "arbitration_lost_int_ena", + &format_args!("{}", self.arbitration_lost_int_ena().bit()), + ) + .field( + "mst_txfifo_udf_int_ena", + &format_args!("{}", self.mst_txfifo_udf_int_ena().bit()), + ) + .field( + "trans_complete_int_ena", + &format_args!("{}", self.trans_complete_int_ena().bit()), + ) + .field( + "time_out_int_ena", + &format_args!("{}", self.time_out_int_ena().bit()), + ) + .field( + "trans_start_int_ena", + &format_args!("{}", self.trans_start_int_ena().bit()), + ) + .field( + "nack_int_ena", + &format_args!("{}", self.nack_int_ena().bit()), + ) + .field( + "txfifo_ovf_int_ena", + &format_args!("{}", self.txfifo_ovf_int_ena().bit()), + ) + .field( + "rxfifo_udf_int_ena", + &format_args!("{}", self.rxfifo_udf_int_ena().bit()), + ) + .field( + "scl_st_to_int_ena", + &format_args!("{}", self.scl_st_to_int_ena().bit()), + ) + .field( + "scl_main_st_to_int_ena", + &format_args!("{}", self.scl_main_st_to_int_ena().bit()), + ) + .field( + "det_start_int_ena", + &format_args!("{}", self.det_start_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to anable I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_wm_int_ena(&mut self) -> RXFIFO_WM_INT_ENA_W { + RXFIFO_WM_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to anable I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn txfifo_wm_int_ena(&mut self) -> TXFIFO_WM_INT_ENA_W { + TXFIFO_WM_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to anable I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_ovf_int_ena(&mut self) -> RXFIFO_OVF_INT_ENA_W { + RXFIFO_OVF_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to anable the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn end_detect_int_ena(&mut self) -> END_DETECT_INT_ENA_W { + END_DETECT_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to anable the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn byte_trans_done_int_ena(&mut self) -> BYTE_TRANS_DONE_INT_ENA_W { + BYTE_TRANS_DONE_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn arbitration_lost_int_ena(&mut self) -> ARBITRATION_LOST_INT_ENA_W { + ARBITRATION_LOST_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn mst_txfifo_udf_int_ena(&mut self) -> MST_TXFIFO_UDF_INT_ENA_W { + MST_TXFIFO_UDF_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn trans_complete_int_ena(&mut self) -> TRANS_COMPLETE_INT_ENA_W { + TRANS_COMPLETE_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - Write 1 to anable the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn time_out_int_ena(&mut self) -> TIME_OUT_INT_ENA_W { + TIME_OUT_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - Write 1 to anable the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn trans_start_int_ena(&mut self) -> TRANS_START_INT_ENA_W { + TRANS_START_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn nack_int_ena(&mut self) -> NACK_INT_ENA_W { + NACK_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - Write 1 to anable I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn txfifo_ovf_int_ena(&mut self) -> TXFIFO_OVF_INT_ENA_W { + TXFIFO_OVF_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - Write 1 to anable I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_udf_int_ena(&mut self) -> RXFIFO_UDF_INT_ENA_W { + RXFIFO_UDF_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - Write 1 to anable I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn scl_st_to_int_ena(&mut self) -> SCL_ST_TO_INT_ENA_W { + SCL_ST_TO_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn scl_main_st_to_int_ena(&mut self) -> SCL_MAIN_ST_TO_INT_ENA_W { + SCL_MAIN_ST_TO_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - Write 1 to anable I2C_DET_START_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn det_start_int_ena(&mut self) -> DET_START_INT_ENA_W { + DET_START_INT_ENA_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/int_raw.rs b/esp32p4/src/lp_i2c0/int_raw.rs new file mode 100644 index 0000000000..180622df2e --- /dev/null +++ b/esp32p4/src/lp_i2c0/int_raw.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_WM_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_INT_RAW_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM_INT_RAW` reader - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_INT_RAW_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `END_DETECT_INT_RAW` reader - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_INT_RAW_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE_INT_RAW` reader - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST_INT_RAW` reader - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_INT_RAW_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF_INT_RAW` reader - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_INT_RAW_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE_INT_RAW` reader - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIME_OUT_INT_RAW` reader - The raw interrupt status of the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `TRANS_START_INT_RAW` reader - The raw interrupt status of the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `NACK_INT_RAW` reader - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_INT_RAW_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF_INT_RAW` reader - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO_INT_RAW` reader - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_INT_RAW_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO_INT_RAW` reader - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_INT_RAW_R = crate::BitReader; +#[doc = "Field `DET_START_INT_RAW` reader - The raw interrupt status of I2C_DET_START_INT interrupt."] +pub type DET_START_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn rxfifo_wm_int_raw(&self) -> RXFIFO_WM_INT_RAW_R { + RXFIFO_WM_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn txfifo_wm_int_raw(&self) -> TXFIFO_WM_INT_RAW_R { + TXFIFO_WM_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R { + RXFIFO_OVF_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn end_detect_int_raw(&self) -> END_DETECT_INT_RAW_R { + END_DETECT_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status of the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn byte_trans_done_int_raw(&self) -> BYTE_TRANS_DONE_INT_RAW_R { + BYTE_TRANS_DONE_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + pub fn arbitration_lost_int_raw(&self) -> ARBITRATION_LOST_INT_RAW_R { + ARBITRATION_LOST_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn mst_txfifo_udf_int_raw(&self) -> MST_TXFIFO_UDF_INT_RAW_R { + MST_TXFIFO_UDF_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn trans_complete_int_raw(&self) -> TRANS_COMPLETE_INT_RAW_R { + TRANS_COMPLETE_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status of the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + pub fn time_out_int_raw(&self) -> TIME_OUT_INT_RAW_R { + TIME_OUT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status of the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + pub fn trans_start_int_raw(&self) -> TRANS_START_INT_RAW_R { + TRANS_START_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn nack_int_raw(&self) -> NACK_INT_RAW_R { + NACK_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn txfifo_ovf_int_raw(&self) -> TXFIFO_OVF_INT_RAW_R { + TXFIFO_OVF_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_udf_int_raw(&self) -> RXFIFO_UDF_INT_RAW_R { + RXFIFO_UDF_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_st_to_int_raw(&self) -> SCL_ST_TO_INT_RAW_R { + SCL_ST_TO_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_main_st_to_int_raw(&self) -> SCL_MAIN_ST_TO_INT_RAW_R { + SCL_MAIN_ST_TO_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The raw interrupt status of I2C_DET_START_INT interrupt."] + #[inline(always)] + pub fn det_start_int_raw(&self) -> DET_START_INT_RAW_R { + DET_START_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "rxfifo_wm_int_raw", + &format_args!("{}", self.rxfifo_wm_int_raw().bit()), + ) + .field( + "txfifo_wm_int_raw", + &format_args!("{}", self.txfifo_wm_int_raw().bit()), + ) + .field( + "rxfifo_ovf_int_raw", + &format_args!("{}", self.rxfifo_ovf_int_raw().bit()), + ) + .field( + "end_detect_int_raw", + &format_args!("{}", self.end_detect_int_raw().bit()), + ) + .field( + "byte_trans_done_int_raw", + &format_args!("{}", self.byte_trans_done_int_raw().bit()), + ) + .field( + "arbitration_lost_int_raw", + &format_args!("{}", self.arbitration_lost_int_raw().bit()), + ) + .field( + "mst_txfifo_udf_int_raw", + &format_args!("{}", self.mst_txfifo_udf_int_raw().bit()), + ) + .field( + "trans_complete_int_raw", + &format_args!("{}", self.trans_complete_int_raw().bit()), + ) + .field( + "time_out_int_raw", + &format_args!("{}", self.time_out_int_raw().bit()), + ) + .field( + "trans_start_int_raw", + &format_args!("{}", self.trans_start_int_raw().bit()), + ) + .field( + "nack_int_raw", + &format_args!("{}", self.nack_int_raw().bit()), + ) + .field( + "txfifo_ovf_int_raw", + &format_args!("{}", self.txfifo_ovf_int_raw().bit()), + ) + .field( + "rxfifo_udf_int_raw", + &format_args!("{}", self.rxfifo_udf_int_raw().bit()), + ) + .field( + "scl_st_to_int_raw", + &format_args!("{}", self.scl_st_to_int_raw().bit()), + ) + .field( + "scl_main_st_to_int_raw", + &format_args!("{}", self.scl_main_st_to_int_raw().bit()), + ) + .field( + "det_start_int_raw", + &format_args!("{}", self.det_start_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0x02"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_i2c0/int_status.rs b/esp32p4/src/lp_i2c0/int_status.rs new file mode 100644 index 0000000000..f6ae86ff39 --- /dev/null +++ b/esp32p4/src/lp_i2c0/int_status.rs @@ -0,0 +1,201 @@ +#[doc = "Register `INT_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_WM_INT_ST` reader - The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt."] +pub type RXFIFO_WM_INT_ST_R = crate::BitReader; +#[doc = "Field `TXFIFO_WM_INT_ST` reader - The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt."] +pub type TXFIFO_WM_INT_ST_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_ST` reader - The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt."] +pub type RXFIFO_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `END_DETECT_INT_ST` reader - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] +pub type END_DETECT_INT_ST_R = crate::BitReader; +#[doc = "Field `BYTE_TRANS_DONE_INT_ST` reader - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] +pub type BYTE_TRANS_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST_INT_ST` reader - The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt."] +pub type ARBITRATION_LOST_INT_ST_R = crate::BitReader; +#[doc = "Field `MST_TXFIFO_UDF_INT_ST` reader - The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt."] +pub type MST_TXFIFO_UDF_INT_ST_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE_INT_ST` reader - The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt."] +pub type TRANS_COMPLETE_INT_ST_R = crate::BitReader; +#[doc = "Field `TIME_OUT_INT_ST` reader - The masked interrupt status status of the I2C_TIME_OUT_INT interrupt."] +pub type TIME_OUT_INT_ST_R = crate::BitReader; +#[doc = "Field `TRANS_START_INT_ST` reader - The masked interrupt status status of the I2C_TRANS_START_INT interrupt."] +pub type TRANS_START_INT_ST_R = crate::BitReader; +#[doc = "Field `NACK_INT_ST` reader - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt."] +pub type NACK_INT_ST_R = crate::BitReader; +#[doc = "Field `TXFIFO_OVF_INT_ST` reader - The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt."] +pub type TXFIFO_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `RXFIFO_UDF_INT_ST` reader - The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt."] +pub type RXFIFO_UDF_INT_ST_R = crate::BitReader; +#[doc = "Field `SCL_ST_TO_INT_ST` reader - The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt."] +pub type SCL_ST_TO_INT_ST_R = crate::BitReader; +#[doc = "Field `SCL_MAIN_ST_TO_INT_ST` reader - The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt."] +pub type SCL_MAIN_ST_TO_INT_ST_R = crate::BitReader; +#[doc = "Field `DET_START_INT_ST` reader - The masked interrupt status status of I2C_DET_START_INT interrupt."] +pub type DET_START_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn rxfifo_wm_int_st(&self) -> RXFIFO_WM_INT_ST_R { + RXFIFO_WM_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt."] + #[inline(always)] + pub fn txfifo_wm_int_st(&self) -> TXFIFO_WM_INT_ST_R { + TXFIFO_WM_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_ovf_int_st(&self) -> RXFIFO_OVF_INT_ST_R { + RXFIFO_OVF_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn end_detect_int_st(&self) -> END_DETECT_INT_ST_R { + END_DETECT_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The masked interrupt status status of the I2C_END_DETECT_INT interrupt."] + #[inline(always)] + pub fn byte_trans_done_int_st(&self) -> BYTE_TRANS_DONE_INT_ST_R { + BYTE_TRANS_DONE_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt."] + #[inline(always)] + pub fn arbitration_lost_int_st(&self) -> ARBITRATION_LOST_INT_ST_R { + ARBITRATION_LOST_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn mst_txfifo_udf_int_st(&self) -> MST_TXFIFO_UDF_INT_ST_R { + MST_TXFIFO_UDF_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt."] + #[inline(always)] + pub fn trans_complete_int_st(&self) -> TRANS_COMPLETE_INT_ST_R { + TRANS_COMPLETE_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The masked interrupt status status of the I2C_TIME_OUT_INT interrupt."] + #[inline(always)] + pub fn time_out_int_st(&self) -> TIME_OUT_INT_ST_R { + TIME_OUT_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The masked interrupt status status of the I2C_TRANS_START_INT interrupt."] + #[inline(always)] + pub fn trans_start_int_st(&self) -> TRANS_START_INT_ST_R { + TRANS_START_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt."] + #[inline(always)] + pub fn nack_int_st(&self) -> NACK_INT_ST_R { + NACK_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn txfifo_ovf_int_st(&self) -> TXFIFO_OVF_INT_ST_R { + TXFIFO_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt."] + #[inline(always)] + pub fn rxfifo_udf_int_st(&self) -> RXFIFO_UDF_INT_ST_R { + RXFIFO_UDF_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_st_to_int_st(&self) -> SCL_ST_TO_INT_ST_R { + SCL_ST_TO_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt."] + #[inline(always)] + pub fn scl_main_st_to_int_st(&self) -> SCL_MAIN_ST_TO_INT_ST_R { + SCL_MAIN_ST_TO_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The masked interrupt status status of I2C_DET_START_INT interrupt."] + #[inline(always)] + pub fn det_start_int_st(&self) -> DET_START_INT_ST_R { + DET_START_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_STATUS") + .field( + "rxfifo_wm_int_st", + &format_args!("{}", self.rxfifo_wm_int_st().bit()), + ) + .field( + "txfifo_wm_int_st", + &format_args!("{}", self.txfifo_wm_int_st().bit()), + ) + .field( + "rxfifo_ovf_int_st", + &format_args!("{}", self.rxfifo_ovf_int_st().bit()), + ) + .field( + "end_detect_int_st", + &format_args!("{}", self.end_detect_int_st().bit()), + ) + .field( + "byte_trans_done_int_st", + &format_args!("{}", self.byte_trans_done_int_st().bit()), + ) + .field( + "arbitration_lost_int_st", + &format_args!("{}", self.arbitration_lost_int_st().bit()), + ) + .field( + "mst_txfifo_udf_int_st", + &format_args!("{}", self.mst_txfifo_udf_int_st().bit()), + ) + .field( + "trans_complete_int_st", + &format_args!("{}", self.trans_complete_int_st().bit()), + ) + .field( + "time_out_int_st", + &format_args!("{}", self.time_out_int_st().bit()), + ) + .field( + "trans_start_int_st", + &format_args!("{}", self.trans_start_int_st().bit()), + ) + .field("nack_int_st", &format_args!("{}", self.nack_int_st().bit())) + .field( + "txfifo_ovf_int_st", + &format_args!("{}", self.txfifo_ovf_int_st().bit()), + ) + .field( + "rxfifo_udf_int_st", + &format_args!("{}", self.rxfifo_udf_int_st().bit()), + ) + .field( + "scl_st_to_int_st", + &format_args!("{}", self.scl_st_to_int_st().bit()), + ) + .field( + "scl_main_st_to_int_st", + &format_args!("{}", self.scl_main_st_to_int_st().bit()), + ) + .field( + "det_start_int_st", + &format_args!("{}", self.det_start_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_STATUS_SPEC; +impl crate::RegisterSpec for INT_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_status::R`](R) reader structure"] +impl crate::Readable for INT_STATUS_SPEC {} +#[doc = "`reset()` method sets INT_STATUS to value 0"] +impl crate::Resettable for INT_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/rxfifo_start_addr.rs b/esp32p4/src/lp_i2c0/rxfifo_start_addr.rs new file mode 100644 index 0000000000..fe33026457 --- /dev/null +++ b/esp32p4/src/lp_i2c0/rxfifo_start_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RXFIFO_START_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_START_ADDR` reader - Represents the I2C rxfifo first address."] +pub type RXFIFO_START_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Represents the I2C rxfifo first address."] + #[inline(always)] + pub fn rxfifo_start_addr(&self) -> RXFIFO_START_ADDR_R { + RXFIFO_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RXFIFO_START_ADDR") + .field( + "rxfifo_start_addr", + &format_args!("{}", self.rxfifo_start_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RXFIFO_START_ADDR_SPEC; +impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifo_start_addr::R`](R) reader structure"] +impl crate::Readable for RXFIFO_START_ADDR_SPEC {} +#[doc = "`reset()` method sets RXFIFO_START_ADDR to value 0"] +impl crate::Resettable for RXFIFO_START_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/scl_high_period.rs b/esp32p4/src/lp_i2c0/scl_high_period.rs new file mode 100644 index 0000000000..af1fade8cf --- /dev/null +++ b/esp32p4/src/lp_i2c0/scl_high_period.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SCL_HIGH_PERIOD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_HIGH_PERIOD` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_HIGH_PERIOD` reader - Configures for how long SCL remains high in master mode. Measurement unit: i2c_sclk"] +pub type SCL_HIGH_PERIOD_R = crate::FieldReader; +#[doc = "Field `SCL_HIGH_PERIOD` writer - Configures for how long SCL remains high in master mode. Measurement unit: i2c_sclk"] +pub type SCL_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `SCL_WAIT_HIGH_PERIOD` reader - Configures the SCL_FSM's waiting period for SCL high level in master mode. Measurement unit: i2c_sclk"] +pub type SCL_WAIT_HIGH_PERIOD_R = crate::FieldReader; +#[doc = "Field `SCL_WAIT_HIGH_PERIOD` writer - Configures the SCL_FSM's waiting period for SCL high level in master mode. Measurement unit: i2c_sclk"] +pub type SCL_WAIT_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:8 - Configures for how long SCL remains high in master mode. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_high_period(&self) -> SCL_HIGH_PERIOD_R { + SCL_HIGH_PERIOD_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:15 - Configures the SCL_FSM's waiting period for SCL high level in master mode. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_wait_high_period(&self) -> SCL_WAIT_HIGH_PERIOD_R { + SCL_WAIT_HIGH_PERIOD_R::new(((self.bits >> 9) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_HIGH_PERIOD") + .field( + "scl_high_period", + &format_args!("{}", self.scl_high_period().bits()), + ) + .field( + "scl_wait_high_period", + &format_args!("{}", self.scl_wait_high_period().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures for how long SCL remains high in master mode. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_high_period(&mut self) -> SCL_HIGH_PERIOD_W { + SCL_HIGH_PERIOD_W::new(self, 0) + } + #[doc = "Bits 9:15 - Configures the SCL_FSM's waiting period for SCL high level in master mode. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_wait_high_period(&mut self) -> SCL_WAIT_HIGH_PERIOD_W { + SCL_WAIT_HIGH_PERIOD_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the high level width of SCL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_high_period::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_high_period::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_HIGH_PERIOD_SPEC; +impl crate::RegisterSpec for SCL_HIGH_PERIOD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_high_period::R`](R) reader structure"] +impl crate::Readable for SCL_HIGH_PERIOD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_high_period::W`](W) writer structure"] +impl crate::Writable for SCL_HIGH_PERIOD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_HIGH_PERIOD to value 0"] +impl crate::Resettable for SCL_HIGH_PERIOD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/scl_low_period.rs b/esp32p4/src/lp_i2c0/scl_low_period.rs new file mode 100644 index 0000000000..bb7f161cc4 --- /dev/null +++ b/esp32p4/src/lp_i2c0/scl_low_period.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SCL_LOW_PERIOD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_LOW_PERIOD` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_LOW_PERIOD` reader - Configures the low level width of the SCL Clock. Measurement unit: i2c_sclk."] +pub type SCL_LOW_PERIOD_R = crate::FieldReader; +#[doc = "Field `SCL_LOW_PERIOD` writer - Configures the low level width of the SCL Clock. Measurement unit: i2c_sclk."] +pub type SCL_LOW_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the low level width of the SCL Clock. Measurement unit: i2c_sclk."] + #[inline(always)] + pub fn scl_low_period(&self) -> SCL_LOW_PERIOD_R { + SCL_LOW_PERIOD_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_LOW_PERIOD") + .field( + "scl_low_period", + &format_args!("{}", self.scl_low_period().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the low level width of the SCL Clock. Measurement unit: i2c_sclk."] + #[inline(always)] + #[must_use] + pub fn scl_low_period(&mut self) -> SCL_LOW_PERIOD_W { + SCL_LOW_PERIOD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the low level width of the SCL Clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_low_period::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_low_period::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_LOW_PERIOD_SPEC; +impl crate::RegisterSpec for SCL_LOW_PERIOD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_low_period::R`](R) reader structure"] +impl crate::Readable for SCL_LOW_PERIOD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_low_period::W`](W) writer structure"] +impl crate::Writable for SCL_LOW_PERIOD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_LOW_PERIOD to value 0"] +impl crate::Resettable for SCL_LOW_PERIOD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/scl_main_st_time_out.rs b/esp32p4/src/lp_i2c0/scl_main_st_time_out.rs new file mode 100644 index 0000000000..23d278a5f5 --- /dev/null +++ b/esp32p4/src/lp_i2c0/scl_main_st_time_out.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SCL_MAIN_ST_TIME_OUT` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_MAIN_ST_TIME_OUT` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_MAIN_ST_TO_I2C` reader - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. Measurement unit: i2c_sclk"] +pub type SCL_MAIN_ST_TO_I2C_R = crate::FieldReader; +#[doc = "Field `SCL_MAIN_ST_TO_I2C` writer - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. Measurement unit: i2c_sclk"] +pub type SCL_MAIN_ST_TO_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_main_st_to_i2c(&self) -> SCL_MAIN_ST_TO_I2C_R { + SCL_MAIN_ST_TO_I2C_R::new((self.bits & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_MAIN_ST_TIME_OUT") + .field( + "scl_main_st_to_i2c", + &format_args!("{}", self.scl_main_st_to_i2c().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_main_st_to_i2c(&mut self) -> SCL_MAIN_ST_TO_I2C_W { + SCL_MAIN_ST_TO_I2C_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SCL main status time out register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_main_st_time_out::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_main_st_time_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_MAIN_ST_TIME_OUT_SPEC; +impl crate::RegisterSpec for SCL_MAIN_ST_TIME_OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_main_st_time_out::R`](R) reader structure"] +impl crate::Readable for SCL_MAIN_ST_TIME_OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_main_st_time_out::W`](W) writer structure"] +impl crate::Writable for SCL_MAIN_ST_TIME_OUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_MAIN_ST_TIME_OUT to value 0x10"] +impl crate::Resettable for SCL_MAIN_ST_TIME_OUT_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/esp32p4/src/lp_i2c0/scl_rstart_setup.rs b/esp32p4/src/lp_i2c0/scl_rstart_setup.rs new file mode 100644 index 0000000000..81b2c9d683 --- /dev/null +++ b/esp32p4/src/lp_i2c0/scl_rstart_setup.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SCL_RSTART_SETUP` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_RSTART_SETUP` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. Measurement unit: i2c_sclk"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. Measurement unit: i2c_sclk"] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_RSTART_SETUP") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the delay between the positive edge of SCL and the negative edge of SDA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_rstart_setup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_rstart_setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_RSTART_SETUP_SPEC; +impl crate::RegisterSpec for SCL_RSTART_SETUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_rstart_setup::R`](R) reader structure"] +impl crate::Readable for SCL_RSTART_SETUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_rstart_setup::W`](W) writer structure"] +impl crate::Writable for SCL_RSTART_SETUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_RSTART_SETUP to value 0x08"] +impl crate::Resettable for SCL_RSTART_SETUP_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/lp_i2c0/scl_sp_conf.rs b/esp32p4/src/lp_i2c0/scl_sp_conf.rs new file mode 100644 index 0000000000..9a97c35167 --- /dev/null +++ b/esp32p4/src/lp_i2c0/scl_sp_conf.rs @@ -0,0 +1,117 @@ +#[doc = "Register `SCL_SP_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_SP_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_RST_SLV_EN` reader - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] +pub type SCL_RST_SLV_EN_R = crate::BitReader; +#[doc = "Field `SCL_RST_SLV_EN` writer - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] +pub type SCL_RST_SLV_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCL_RST_SLV_NUM` reader - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] +pub type SCL_RST_SLV_NUM_R = crate::FieldReader; +#[doc = "Field `SCL_RST_SLV_NUM` writer - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] +pub type SCL_RST_SLV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SCL_PD_EN` reader - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. Measurement unit: i2c_sclk"] +pub type SCL_PD_EN_R = crate::BitReader; +#[doc = "Field `SCL_PD_EN` writer - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. Measurement unit: i2c_sclk"] +pub type SCL_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDA_PD_EN` reader - Configures to power down the I2C output SCL line. 0: Not power down. 1: Power down. Valid only when reg_scl_force_out is 1."] +pub type SDA_PD_EN_R = crate::BitReader; +#[doc = "Field `SDA_PD_EN` writer - Configures to power down the I2C output SCL line. 0: Not power down. 1: Power down. Valid only when reg_scl_force_out is 1."] +pub type SDA_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] + #[inline(always)] + pub fn scl_rst_slv_en(&self) -> SCL_RST_SLV_EN_R { + SCL_RST_SLV_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:5 - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] + #[inline(always)] + pub fn scl_rst_slv_num(&self) -> SCL_RST_SLV_NUM_R { + SCL_RST_SLV_NUM_R::new(((self.bits >> 1) & 0x1f) as u8) + } + #[doc = "Bit 6 - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_pd_en(&self) -> SCL_PD_EN_R { + SCL_PD_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures to power down the I2C output SCL line. 0: Not power down. 1: Power down. Valid only when reg_scl_force_out is 1."] + #[inline(always)] + pub fn sda_pd_en(&self) -> SDA_PD_EN_R { + SDA_PD_EN_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_SP_CONF") + .field( + "scl_rst_slv_en", + &format_args!("{}", self.scl_rst_slv_en().bit()), + ) + .field( + "scl_rst_slv_num", + &format_args!("{}", self.scl_rst_slv_num().bits()), + ) + .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit())) + .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] + #[inline(always)] + #[must_use] + pub fn scl_rst_slv_en(&mut self) -> SCL_RST_SLV_EN_W { + SCL_RST_SLV_EN_W::new(self, 0) + } + #[doc = "Bits 1:5 - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."] + #[inline(always)] + #[must_use] + pub fn scl_rst_slv_num(&mut self) -> SCL_RST_SLV_NUM_W { + SCL_RST_SLV_NUM_W::new(self, 1) + } + #[doc = "Bit 6 - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_pd_en(&mut self) -> SCL_PD_EN_W { + SCL_PD_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Configures to power down the I2C output SCL line. 0: Not power down. 1: Power down. Valid only when reg_scl_force_out is 1."] + #[inline(always)] + #[must_use] + pub fn sda_pd_en(&mut self) -> SDA_PD_EN_W { + SDA_PD_EN_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Power configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_sp_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_sp_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_SP_CONF_SPEC; +impl crate::RegisterSpec for SCL_SP_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_sp_conf::R`](R) reader structure"] +impl crate::Readable for SCL_SP_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_sp_conf::W`](W) writer structure"] +impl crate::Writable for SCL_SP_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_SP_CONF to value 0"] +impl crate::Resettable for SCL_SP_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/scl_st_time_out.rs b/esp32p4/src/lp_i2c0/scl_st_time_out.rs new file mode 100644 index 0000000000..3811a9e1fb --- /dev/null +++ b/esp32p4/src/lp_i2c0/scl_st_time_out.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SCL_ST_TIME_OUT` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_ST_TIME_OUT` writer"] +pub type W = crate::W; +#[doc = "Field `SCL_ST_TO_I2C` reader - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. Measurement unit: i2c_sclk"] +pub type SCL_ST_TO_I2C_R = crate::FieldReader; +#[doc = "Field `SCL_ST_TO_I2C` writer - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. Measurement unit: i2c_sclk"] +pub type SCL_ST_TO_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn scl_st_to_i2c(&self) -> SCL_ST_TO_I2C_R { + SCL_ST_TO_I2C_R::new((self.bits & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_ST_TIME_OUT") + .field( + "scl_st_to_i2c", + &format_args!("{}", self.scl_st_to_i2c().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn scl_st_to_i2c(&mut self) -> SCL_ST_TO_I2C_W { + SCL_ST_TO_I2C_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SCL status time out register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_st_time_out::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_st_time_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_ST_TIME_OUT_SPEC; +impl crate::RegisterSpec for SCL_ST_TIME_OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_st_time_out::R`](R) reader structure"] +impl crate::Readable for SCL_ST_TIME_OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_st_time_out::W`](W) writer structure"] +impl crate::Writable for SCL_ST_TIME_OUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_ST_TIME_OUT to value 0x10"] +impl crate::Resettable for SCL_ST_TIME_OUT_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/esp32p4/src/lp_i2c0/scl_start_hold.rs b/esp32p4/src/lp_i2c0/scl_start_hold.rs new file mode 100644 index 0000000000..a1a367768c --- /dev/null +++ b/esp32p4/src/lp_i2c0/scl_start_hold.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SCL_START_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_START_HOLD` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: i2c_sclk."] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: i2c_sclk."] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: i2c_sclk."] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_START_HOLD") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: i2c_sclk."] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the delay between the SDA and SCL negative edge for a start condition\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_start_hold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_start_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_START_HOLD_SPEC; +impl crate::RegisterSpec for SCL_START_HOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_start_hold::R`](R) reader structure"] +impl crate::Readable for SCL_START_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_start_hold::W`](W) writer structure"] +impl crate::Writable for SCL_START_HOLD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_START_HOLD to value 0x08"] +impl crate::Resettable for SCL_START_HOLD_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/lp_i2c0/scl_stop_hold.rs b/esp32p4/src/lp_i2c0/scl_stop_hold.rs new file mode 100644 index 0000000000..866c4b67bc --- /dev/null +++ b/esp32p4/src/lp_i2c0/scl_stop_hold.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SCL_STOP_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_STOP_HOLD` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the delay after the STOP condition. Measurement unit: i2c_sclk"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the delay after the STOP condition. Measurement unit: i2c_sclk"] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the delay after the STOP condition. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_STOP_HOLD") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the delay after the STOP condition. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the delay after the SCL clock edge for a stop condition\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_hold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_STOP_HOLD_SPEC; +impl crate::RegisterSpec for SCL_STOP_HOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_stop_hold::R`](R) reader structure"] +impl crate::Readable for SCL_STOP_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_stop_hold::W`](W) writer structure"] +impl crate::Writable for SCL_STOP_HOLD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_STOP_HOLD to value 0x08"] +impl crate::Resettable for SCL_STOP_HOLD_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/lp_i2c0/scl_stop_setup.rs b/esp32p4/src/lp_i2c0/scl_stop_setup.rs new file mode 100644 index 0000000000..37bdf6b0e3 --- /dev/null +++ b/esp32p4/src/lp_i2c0/scl_stop_setup.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SCL_STOP_SETUP` reader"] +pub type R = crate::R; +#[doc = "Register `SCL_STOP_SETUP` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the time between the rising edge of SCL and the rising edge of SDA. Measurement unit: i2c_sclk"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the time between the rising edge of SCL and the rising edge of SDA. Measurement unit: i2c_sclk"] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the time between the rising edge of SCL and the rising edge of SDA. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCL_STOP_SETUP") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the time between the rising edge of SCL and the rising edge of SDA. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the delay between the SDA and SCL positive edge for a stop condition\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl_stop_setup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl_stop_setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCL_STOP_SETUP_SPEC; +impl crate::RegisterSpec for SCL_STOP_SETUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scl_stop_setup::R`](R) reader structure"] +impl crate::Readable for SCL_STOP_SETUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl_stop_setup::W`](W) writer structure"] +impl crate::Writable for SCL_STOP_SETUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCL_STOP_SETUP to value 0x08"] +impl crate::Resettable for SCL_STOP_SETUP_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/lp_i2c0/sda_hold.rs b/esp32p4/src/lp_i2c0/sda_hold.rs new file mode 100644 index 0000000000..4cba5c0c26 --- /dev/null +++ b/esp32p4/src/lp_i2c0/sda_hold.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SDA_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `SDA_HOLD` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the time to hold the data after the falling edge of SCL. Measurement unit: i2c_sclk"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the time to hold the data after the falling edge of SCL. Measurement unit: i2c_sclk"] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the time to hold the data after the falling edge of SCL. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDA_HOLD") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the time to hold the data after the falling edge of SCL. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the hold time after a negative SCL edge.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_hold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDA_HOLD_SPEC; +impl crate::RegisterSpec for SDA_HOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sda_hold::R`](R) reader structure"] +impl crate::Readable for SDA_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sda_hold::W`](W) writer structure"] +impl crate::Writable for SDA_HOLD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDA_HOLD to value 0"] +impl crate::Resettable for SDA_HOLD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/sda_sample.rs b/esp32p4/src/lp_i2c0/sda_sample.rs new file mode 100644 index 0000000000..f733b428d5 --- /dev/null +++ b/esp32p4/src/lp_i2c0/sda_sample.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SDA_SAMPLE` reader"] +pub type R = crate::R; +#[doc = "Register `SDA_SAMPLE` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Configures the sample time after a positive SCL edge. Measurement unit: i2c_sclk"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `TIME` writer - Configures the sample time after a positive SCL edge. Measurement unit: i2c_sclk"] +pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Configures the sample time after a positive SCL edge. Measurement unit: i2c_sclk"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDA_SAMPLE") + .field("time", &format_args!("{}", self.time().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - Configures the sample time after a positive SCL edge. Measurement unit: i2c_sclk"] + #[inline(always)] + #[must_use] + pub fn time(&mut self) -> TIME_W { + TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the sample time after a positive SCL edge.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sda_sample::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sda_sample::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDA_SAMPLE_SPEC; +impl crate::RegisterSpec for SDA_SAMPLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sda_sample::R`](R) reader structure"] +impl crate::Readable for SDA_SAMPLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sda_sample::W`](W) writer structure"] +impl crate::Writable for SDA_SAMPLE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDA_SAMPLE to value 0"] +impl crate::Resettable for SDA_SAMPLE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/sr.rs b/esp32p4/src/lp_i2c0/sr.rs new file mode 100644 index 0000000000..4f0cd143a0 --- /dev/null +++ b/esp32p4/src/lp_i2c0/sr.rs @@ -0,0 +1,90 @@ +#[doc = "Register `SR` reader"] +pub type R = crate::R; +#[doc = "Field `RESP_REC` reader - Represents the received ACK value in master mode or slave mode. 0: ACK, 1: NACK."] +pub type RESP_REC_R = crate::BitReader; +#[doc = "Field `ARB_LOST` reader - Represents whether the I2C controller loses control of SCL line. 0: No arbitration lost 1: Arbitration lost"] +pub type ARB_LOST_R = crate::BitReader; +#[doc = "Field `BUS_BUSY` reader - Represents the I2C bus state. 1: The I2C bus is busy transferring data, 0: The I2C bus is in idle state."] +pub type BUS_BUSY_R = crate::BitReader; +#[doc = "Field `RXFIFO_CNT` reader - Represents the number of data bytes to be sent."] +pub type RXFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `TXFIFO_CNT` reader - Represents the number of data bytes received in RAM."] +pub type TXFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `SCL_MAIN_STATE_LAST` reader - Represents the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"] +pub type SCL_MAIN_STATE_LAST_R = crate::FieldReader; +#[doc = "Field `SCL_STATE_LAST` reader - Represents the states of the state machine used to produce SCL. 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"] +pub type SCL_STATE_LAST_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Represents the received ACK value in master mode or slave mode. 0: ACK, 1: NACK."] + #[inline(always)] + pub fn resp_rec(&self) -> RESP_REC_R { + RESP_REC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 3 - Represents whether the I2C controller loses control of SCL line. 0: No arbitration lost 1: Arbitration lost"] + #[inline(always)] + pub fn arb_lost(&self) -> ARB_LOST_R { + ARB_LOST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents the I2C bus state. 1: The I2C bus is busy transferring data, 0: The I2C bus is in idle state."] + #[inline(always)] + pub fn bus_busy(&self) -> BUS_BUSY_R { + BUS_BUSY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 8:12 - Represents the number of data bytes to be sent."] + #[inline(always)] + pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R { + RXFIFO_CNT_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 18:22 - Represents the number of data bytes received in RAM."] + #[inline(always)] + pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R { + TXFIFO_CNT_R::new(((self.bits >> 18) & 0x1f) as u8) + } + #[doc = "Bits 24:26 - Represents the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"] + #[inline(always)] + pub fn scl_main_state_last(&self) -> SCL_MAIN_STATE_LAST_R { + SCL_MAIN_STATE_LAST_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 28:30 - Represents the states of the state machine used to produce SCL. 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"] + #[inline(always)] + pub fn scl_state_last(&self) -> SCL_STATE_LAST_R { + SCL_STATE_LAST_R::new(((self.bits >> 28) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SR") + .field("resp_rec", &format_args!("{}", self.resp_rec().bit())) + .field("arb_lost", &format_args!("{}", self.arb_lost().bit())) + .field("bus_busy", &format_args!("{}", self.bus_busy().bit())) + .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits())) + .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits())) + .field( + "scl_main_state_last", + &format_args!("{}", self.scl_main_state_last().bits()), + ) + .field( + "scl_state_last", + &format_args!("{}", self.scl_state_last().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SR_SPEC; +impl crate::RegisterSpec for SR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} +#[doc = "`reset()` method sets SR to value 0"] +impl crate::Resettable for SR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c0/to.rs b/esp32p4/src/lp_i2c0/to.rs new file mode 100644 index 0000000000..d6ee8f5140 --- /dev/null +++ b/esp32p4/src/lp_i2c0/to.rs @@ -0,0 +1,82 @@ +#[doc = "Register `TO` reader"] +pub type R = crate::R; +#[doc = "Register `TO` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_OUT_VALUE` reader - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). Measurement unit: i2c_sclk."] +pub type TIME_OUT_VALUE_R = crate::FieldReader; +#[doc = "Field `TIME_OUT_VALUE` writer - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). Measurement unit: i2c_sclk."] +pub type TIME_OUT_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `TIME_OUT_EN` reader - Configures to enable time out control. 0: No effect 1: Enable"] +pub type TIME_OUT_EN_R = crate::BitReader; +#[doc = "Field `TIME_OUT_EN` writer - Configures to enable time out control. 0: No effect 1: Enable"] +pub type TIME_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). Measurement unit: i2c_sclk."] + #[inline(always)] + pub fn time_out_value(&self) -> TIME_OUT_VALUE_R { + TIME_OUT_VALUE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Configures to enable time out control. 0: No effect 1: Enable"] + #[inline(always)] + pub fn time_out_en(&self) -> TIME_OUT_EN_R { + TIME_OUT_EN_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TO") + .field( + "time_out_value", + &format_args!("{}", self.time_out_value().bits()), + ) + .field("time_out_en", &format_args!("{}", self.time_out_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). Measurement unit: i2c_sclk."] + #[inline(always)] + #[must_use] + pub fn time_out_value(&mut self) -> TIME_OUT_VALUE_W { + TIME_OUT_VALUE_W::new(self, 0) + } + #[doc = "Bit 5 - Configures to enable time out control. 0: No effect 1: Enable"] + #[inline(always)] + #[must_use] + pub fn time_out_en(&mut self) -> TIME_OUT_EN_W { + TIME_OUT_EN_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Setting time out control for receiving data.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`to::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`to::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TO_SPEC; +impl crate::RegisterSpec for TO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`to::R`](R) reader structure"] +impl crate::Readable for TO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`to::W`](W) writer structure"] +impl crate::Writable for TO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TO to value 0x10"] +impl crate::Resettable for TO_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/esp32p4/src/lp_i2c0/txfifo_start_addr.rs b/esp32p4/src/lp_i2c0/txfifo_start_addr.rs new file mode 100644 index 0000000000..6fa651b202 --- /dev/null +++ b/esp32p4/src/lp_i2c0/txfifo_start_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `TXFIFO_START_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `TXFIFO_START_ADDR` reader - Represents the I2C txfifo first address."] +pub type TXFIFO_START_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Represents the I2C txfifo first address."] + #[inline(always)] + pub fn txfifo_start_addr(&self) -> TXFIFO_START_ADDR_R { + TXFIFO_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TXFIFO_START_ADDR") + .field( + "txfifo_start_addr", + &format_args!("{}", self.txfifo_start_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TXFIFO_START_ADDR_SPEC; +impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifo_start_addr::R`](R) reader structure"] +impl crate::Readable for TXFIFO_START_ADDR_SPEC {} +#[doc = "`reset()` method sets TXFIFO_START_ADDR to value 0"] +impl crate::Resettable for TXFIFO_START_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c_ana_mst.rs b/esp32p4/src/lp_i2c_ana_mst.rs new file mode 100644 index 0000000000..b13cb2eff4 --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst.rs @@ -0,0 +1,157 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + i2c0_ctrl: I2C0_CTRL, + i2c1_ctrl: I2C1_CTRL, + i2c0_conf: I2C0_CONF, + i2c1_conf: I2C1_CONF, + i2c_burst_conf: I2C_BURST_CONF, + i2c_burst_status: I2C_BURST_STATUS, + ana_conf0: ANA_CONF0, + ana_conf1: ANA_CONF1, + ana_conf2: ANA_CONF2, + i2c0_ctrl1: I2C0_CTRL1, + i2c1_ctrl1: I2C1_CTRL1, + hw_i2c_ctrl: HW_I2C_CTRL, + nouse: NOUSE, + clk160m: CLK160M, + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - need des"] + #[inline(always)] + pub const fn i2c0_ctrl(&self) -> &I2C0_CTRL { + &self.i2c0_ctrl + } + #[doc = "0x04 - need des"] + #[inline(always)] + pub const fn i2c1_ctrl(&self) -> &I2C1_CTRL { + &self.i2c1_ctrl + } + #[doc = "0x08 - need des"] + #[inline(always)] + pub const fn i2c0_conf(&self) -> &I2C0_CONF { + &self.i2c0_conf + } + #[doc = "0x0c - need des"] + #[inline(always)] + pub const fn i2c1_conf(&self) -> &I2C1_CONF { + &self.i2c1_conf + } + #[doc = "0x10 - need des"] + #[inline(always)] + pub const fn i2c_burst_conf(&self) -> &I2C_BURST_CONF { + &self.i2c_burst_conf + } + #[doc = "0x14 - need des"] + #[inline(always)] + pub const fn i2c_burst_status(&self) -> &I2C_BURST_STATUS { + &self.i2c_burst_status + } + #[doc = "0x18 - need des"] + #[inline(always)] + pub const fn ana_conf0(&self) -> &ANA_CONF0 { + &self.ana_conf0 + } + #[doc = "0x1c - need des"] + #[inline(always)] + pub const fn ana_conf1(&self) -> &ANA_CONF1 { + &self.ana_conf1 + } + #[doc = "0x20 - need des"] + #[inline(always)] + pub const fn ana_conf2(&self) -> &ANA_CONF2 { + &self.ana_conf2 + } + #[doc = "0x24 - need des"] + #[inline(always)] + pub const fn i2c0_ctrl1(&self) -> &I2C0_CTRL1 { + &self.i2c0_ctrl1 + } + #[doc = "0x28 - need des"] + #[inline(always)] + pub const fn i2c1_ctrl1(&self) -> &I2C1_CTRL1 { + &self.i2c1_ctrl1 + } + #[doc = "0x2c - need des"] + #[inline(always)] + pub const fn hw_i2c_ctrl(&self) -> &HW_I2C_CTRL { + &self.hw_i2c_ctrl + } + #[doc = "0x30 - need des"] + #[inline(always)] + pub const fn nouse(&self) -> &NOUSE { + &self.nouse + } + #[doc = "0x34 - need des"] + #[inline(always)] + pub const fn clk160m(&self) -> &CLK160M { + &self.clk160m + } + #[doc = "0x38 - need des"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "I2C0_CTRL (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c0_ctrl`] module"] +pub type I2C0_CTRL = crate::Reg; +#[doc = "need des"] +pub mod i2c0_ctrl; +#[doc = "I2C1_CTRL (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c1_ctrl`] module"] +pub type I2C1_CTRL = crate::Reg; +#[doc = "need des"] +pub mod i2c1_ctrl; +#[doc = "I2C0_CONF (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c0_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c0_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c0_conf`] module"] +pub type I2C0_CONF = crate::Reg; +#[doc = "need des"] +pub mod i2c0_conf; +#[doc = "I2C1_CONF (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c1_conf`] module"] +pub type I2C1_CONF = crate::Reg; +#[doc = "need des"] +pub mod i2c1_conf; +#[doc = "I2C_BURST_CONF (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c_burst_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c_burst_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_burst_conf`] module"] +pub type I2C_BURST_CONF = crate::Reg; +#[doc = "need des"] +pub mod i2c_burst_conf; +#[doc = "I2C_BURST_STATUS (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c_burst_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c_burst_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c_burst_status`] module"] +pub type I2C_BURST_STATUS = crate::Reg; +#[doc = "need des"] +pub mod i2c_burst_status; +#[doc = "ANA_CONF0 (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_conf0`] module"] +pub type ANA_CONF0 = crate::Reg; +#[doc = "need des"] +pub mod ana_conf0; +#[doc = "ANA_CONF1 (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_conf1`] module"] +pub type ANA_CONF1 = crate::Reg; +#[doc = "need des"] +pub mod ana_conf1; +#[doc = "ANA_CONF2 (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_conf2`] module"] +pub type ANA_CONF2 = crate::Reg; +#[doc = "need des"] +pub mod ana_conf2; +#[doc = "I2C0_CTRL1 (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c0_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c0_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c0_ctrl1`] module"] +pub type I2C0_CTRL1 = crate::Reg; +#[doc = "need des"] +pub mod i2c0_ctrl1; +#[doc = "I2C1_CTRL1 (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c1_ctrl1`] module"] +pub type I2C1_CTRL1 = crate::Reg; +#[doc = "need des"] +pub mod i2c1_ctrl1; +#[doc = "HW_I2C_CTRL (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_i2c_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_i2c_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_i2c_ctrl`] module"] +pub type HW_I2C_CTRL = crate::Reg; +#[doc = "need des"] +pub mod hw_i2c_ctrl; +#[doc = "NOUSE (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nouse::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nouse::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nouse`] module"] +pub type NOUSE = crate::Reg; +#[doc = "need des"] +pub mod nouse; +#[doc = "CLK160M (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk160m::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk160m::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk160m`] module"] +pub type CLK160M = crate::Reg; +#[doc = "need des"] +pub mod clk160m; +#[doc = "DATE (rw) register accessor: need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "need des"] +pub mod date; diff --git a/esp32p4/src/lp_i2c_ana_mst/ana_conf0.rs b/esp32p4/src/lp_i2c_ana_mst/ana_conf0.rs new file mode 100644 index 0000000000..f9cbd83b44 --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/ana_conf0.rs @@ -0,0 +1,74 @@ +#[doc = "Register `ANA_CONF0` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_CONF0` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_CONF0` reader - need des"] +pub type ANA_CONF0_R = crate::FieldReader; +#[doc = "Field `ANA_CONF0` writer - need des"] +pub type ANA_CONF0_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Field `ANA_STATUS0` reader - need des"] +pub type ANA_STATUS0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - need des"] + #[inline(always)] + pub fn ana_conf0(&self) -> ANA_CONF0_R { + ANA_CONF0_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bits 24:31 - need des"] + #[inline(always)] + pub fn ana_status0(&self) -> ANA_STATUS0_R { + ANA_STATUS0_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_CONF0") + .field("ana_conf0", &format_args!("{}", self.ana_conf0().bits())) + .field( + "ana_status0", + &format_args!("{}", self.ana_status0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - need des"] + #[inline(always)] + #[must_use] + pub fn ana_conf0(&mut self) -> ANA_CONF0_W { + ANA_CONF0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_CONF0_SPEC; +impl crate::RegisterSpec for ANA_CONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_conf0::R`](R) reader structure"] +impl crate::Readable for ANA_CONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_conf0::W`](W) writer structure"] +impl crate::Writable for ANA_CONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ANA_CONF0 to value 0"] +impl crate::Resettable for ANA_CONF0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/ana_conf1.rs b/esp32p4/src/lp_i2c_ana_mst/ana_conf1.rs new file mode 100644 index 0000000000..1f3bf2b63b --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/ana_conf1.rs @@ -0,0 +1,74 @@ +#[doc = "Register `ANA_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_CONF1` reader - need des"] +pub type ANA_CONF1_R = crate::FieldReader; +#[doc = "Field `ANA_CONF1` writer - need des"] +pub type ANA_CONF1_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Field `ANA_STATUS1` reader - need des"] +pub type ANA_STATUS1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - need des"] + #[inline(always)] + pub fn ana_conf1(&self) -> ANA_CONF1_R { + ANA_CONF1_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bits 24:31 - need des"] + #[inline(always)] + pub fn ana_status1(&self) -> ANA_STATUS1_R { + ANA_STATUS1_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_CONF1") + .field("ana_conf1", &format_args!("{}", self.ana_conf1().bits())) + .field( + "ana_status1", + &format_args!("{}", self.ana_status1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - need des"] + #[inline(always)] + #[must_use] + pub fn ana_conf1(&mut self) -> ANA_CONF1_W { + ANA_CONF1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_CONF1_SPEC; +impl crate::RegisterSpec for ANA_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_conf1::R`](R) reader structure"] +impl crate::Readable for ANA_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_conf1::W`](W) writer structure"] +impl crate::Writable for ANA_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ANA_CONF1 to value 0"] +impl crate::Resettable for ANA_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/ana_conf2.rs b/esp32p4/src/lp_i2c_ana_mst/ana_conf2.rs new file mode 100644 index 0000000000..75b6a1dbc5 --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/ana_conf2.rs @@ -0,0 +1,74 @@ +#[doc = "Register `ANA_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_CONF2` reader - need des"] +pub type ANA_CONF2_R = crate::FieldReader; +#[doc = "Field `ANA_CONF2` writer - need des"] +pub type ANA_CONF2_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Field `ANA_STATUS2` reader - need des"] +pub type ANA_STATUS2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - need des"] + #[inline(always)] + pub fn ana_conf2(&self) -> ANA_CONF2_R { + ANA_CONF2_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bits 24:31 - need des"] + #[inline(always)] + pub fn ana_status2(&self) -> ANA_STATUS2_R { + ANA_STATUS2_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_CONF2") + .field("ana_conf2", &format_args!("{}", self.ana_conf2().bits())) + .field( + "ana_status2", + &format_args!("{}", self.ana_status2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - need des"] + #[inline(always)] + #[must_use] + pub fn ana_conf2(&mut self) -> ANA_CONF2_W { + ANA_CONF2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_CONF2_SPEC; +impl crate::RegisterSpec for ANA_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_conf2::R`](R) reader structure"] +impl crate::Readable for ANA_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_conf2::W`](W) writer structure"] +impl crate::Writable for ANA_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ANA_CONF2 to value 0"] +impl crate::Resettable for ANA_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/clk160m.rs b/esp32p4/src/lp_i2c_ana_mst/clk160m.rs new file mode 100644 index 0000000000..ead49ee5e2 --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/clk160m.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CLK160M` reader"] +pub type R = crate::R; +#[doc = "Register `CLK160M` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_I2C_MST_SEL_160M` reader - need des"] +pub type CLK_I2C_MST_SEL_160M_R = crate::BitReader; +#[doc = "Field `CLK_I2C_MST_SEL_160M` writer - need des"] +pub type CLK_I2C_MST_SEL_160M_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need des"] + #[inline(always)] + pub fn clk_i2c_mst_sel_160m(&self) -> CLK_I2C_MST_SEL_160M_R { + CLK_I2C_MST_SEL_160M_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK160M") + .field( + "clk_i2c_mst_sel_160m", + &format_args!("{}", self.clk_i2c_mst_sel_160m().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need des"] + #[inline(always)] + #[must_use] + pub fn clk_i2c_mst_sel_160m(&mut self) -> CLK_I2C_MST_SEL_160M_W { + CLK_I2C_MST_SEL_160M_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk160m::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk160m::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK160M_SPEC; +impl crate::RegisterSpec for CLK160M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk160m::R`](R) reader structure"] +impl crate::Readable for CLK160M_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk160m::W`](W) writer structure"] +impl crate::Writable for CLK160M_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK160M to value 0"] +impl crate::Resettable for CLK160M_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/date.rs b/esp32p4/src/lp_i2c_ana_mst/date.rs new file mode 100644 index 0000000000..6cbb7ed4d4 --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/date.rs @@ -0,0 +1,82 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - need des"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - need des"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +#[doc = "Field `I2C_MST_CLK_EN` reader - need des"] +pub type I2C_MST_CLK_EN_R = crate::BitReader; +#[doc = "Field `I2C_MST_CLK_EN` writer - need des"] +pub type I2C_MST_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:27 - need des"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } + #[doc = "Bit 28 - need des"] + #[inline(always)] + pub fn i2c_mst_clk_en(&self) -> I2C_MST_CLK_EN_R { + I2C_MST_CLK_EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .field( + "i2c_mst_clk_en", + &format_args!("{}", self.i2c_mst_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - need des"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = "Bit 28 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c_mst_clk_en(&mut self) -> I2C_MST_CLK_EN_W { + I2C_MST_CLK_EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0220_1300"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_1300; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/hw_i2c_ctrl.rs b/esp32p4/src/lp_i2c_ana_mst/hw_i2c_ctrl.rs new file mode 100644 index 0000000000..7fd74144d2 --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/hw_i2c_ctrl.rs @@ -0,0 +1,101 @@ +#[doc = "Register `HW_I2C_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HW_I2C_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HW_I2C_SCL_PULSE_DUR` reader - need des"] +pub type HW_I2C_SCL_PULSE_DUR_R = crate::FieldReader; +#[doc = "Field `HW_I2C_SCL_PULSE_DUR` writer - need des"] +pub type HW_I2C_SCL_PULSE_DUR_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `HW_I2C_SDA_SIDE_GUARD` reader - need des"] +pub type HW_I2C_SDA_SIDE_GUARD_R = crate::FieldReader; +#[doc = "Field `HW_I2C_SDA_SIDE_GUARD` writer - need des"] +pub type HW_I2C_SDA_SIDE_GUARD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `ARBITER_DIS` reader - need des"] +pub type ARBITER_DIS_R = crate::BitReader; +#[doc = "Field `ARBITER_DIS` writer - need des"] +pub type ARBITER_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - need des"] + #[inline(always)] + pub fn hw_i2c_scl_pulse_dur(&self) -> HW_I2C_SCL_PULSE_DUR_R { + HW_I2C_SCL_PULSE_DUR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:10 - need des"] + #[inline(always)] + pub fn hw_i2c_sda_side_guard(&self) -> HW_I2C_SDA_SIDE_GUARD_R { + HW_I2C_SDA_SIDE_GUARD_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn arbiter_dis(&self) -> ARBITER_DIS_R { + ARBITER_DIS_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HW_I2C_CTRL") + .field( + "hw_i2c_scl_pulse_dur", + &format_args!("{}", self.hw_i2c_scl_pulse_dur().bits()), + ) + .field( + "hw_i2c_sda_side_guard", + &format_args!("{}", self.hw_i2c_sda_side_guard().bits()), + ) + .field("arbiter_dis", &format_args!("{}", self.arbiter_dis().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - need des"] + #[inline(always)] + #[must_use] + pub fn hw_i2c_scl_pulse_dur(&mut self) -> HW_I2C_SCL_PULSE_DUR_W { + HW_I2C_SCL_PULSE_DUR_W::new(self, 0) + } + #[doc = "Bits 6:10 - need des"] + #[inline(always)] + #[must_use] + pub fn hw_i2c_sda_side_guard(&mut self) -> HW_I2C_SDA_SIDE_GUARD_W { + HW_I2C_SDA_SIDE_GUARD_W::new(self, 6) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn arbiter_dis(&mut self) -> ARBITER_DIS_W { + ARBITER_DIS_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_i2c_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_i2c_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HW_I2C_CTRL_SPEC; +impl crate::RegisterSpec for HW_I2C_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hw_i2c_ctrl::R`](R) reader structure"] +impl crate::Readable for HW_I2C_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hw_i2c_ctrl::W`](W) writer structure"] +impl crate::Writable for HW_I2C_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HW_I2C_CTRL to value 0x42"] +impl crate::Resettable for HW_I2C_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x42; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c0_conf.rs b/esp32p4/src/lp_i2c_ana_mst/i2c0_conf.rs new file mode 100644 index 0000000000..4407e3f4ab --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/i2c0_conf.rs @@ -0,0 +1,74 @@ +#[doc = "Register `I2C0_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `I2C0_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `I2C0_CONF` reader - need des"] +pub type I2C0_CONF_R = crate::FieldReader; +#[doc = "Field `I2C0_CONF` writer - need des"] +pub type I2C0_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Field `I2C0_STATUS` reader - need des"] +pub type I2C0_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - need des"] + #[inline(always)] + pub fn i2c0_conf(&self) -> I2C0_CONF_R { + I2C0_CONF_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bits 24:31 - need des"] + #[inline(always)] + pub fn i2c0_status(&self) -> I2C0_STATUS_R { + I2C0_STATUS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0_CONF") + .field("i2c0_conf", &format_args!("{}", self.i2c0_conf().bits())) + .field( + "i2c0_status", + &format_args!("{}", self.i2c0_status().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c0_conf(&mut self) -> I2C0_CONF_W { + I2C0_CONF_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c0_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c0_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C0_CONF_SPEC; +impl crate::RegisterSpec for I2C0_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c0_conf::R`](R) reader structure"] +impl crate::Readable for I2C0_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c0_conf::W`](W) writer structure"] +impl crate::Writable for I2C0_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C0_CONF to value 0"] +impl crate::Resettable for I2C0_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl.rs b/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl.rs new file mode 100644 index 0000000000..afb87c5a23 --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl.rs @@ -0,0 +1,71 @@ +#[doc = "Register `I2C0_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `I2C0_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `I2C0_CTRL` reader - need des"] +pub type I2C0_CTRL_R = crate::FieldReader; +#[doc = "Field `I2C0_CTRL` writer - need des"] +pub type I2C0_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +#[doc = "Field `I2C0_BUSY` reader - need des"] +pub type I2C0_BUSY_R = crate::BitReader; +impl R { + #[doc = "Bits 0:24 - need des"] + #[inline(always)] + pub fn i2c0_ctrl(&self) -> I2C0_CTRL_R { + I2C0_CTRL_R::new(self.bits & 0x01ff_ffff) + } + #[doc = "Bit 25 - need des"] + #[inline(always)] + pub fn i2c0_busy(&self) -> I2C0_BUSY_R { + I2C0_BUSY_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0_CTRL") + .field("i2c0_ctrl", &format_args!("{}", self.i2c0_ctrl().bits())) + .field("i2c0_busy", &format_args!("{}", self.i2c0_busy().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:24 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c0_ctrl(&mut self) -> I2C0_CTRL_W { + I2C0_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c0_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C0_CTRL_SPEC; +impl crate::RegisterSpec for I2C0_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c0_ctrl::R`](R) reader structure"] +impl crate::Readable for I2C0_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c0_ctrl::W`](W) writer structure"] +impl crate::Writable for I2C0_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C0_CTRL to value 0"] +impl crate::Resettable for I2C0_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl1.rs b/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl1.rs new file mode 100644 index 0000000000..324bc91c24 --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `I2C0_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `I2C0_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `I2C0_SCL_PULSE_DUR` reader - need des"] +pub type I2C0_SCL_PULSE_DUR_R = crate::FieldReader; +#[doc = "Field `I2C0_SCL_PULSE_DUR` writer - need des"] +pub type I2C0_SCL_PULSE_DUR_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `I2C0_SDA_SIDE_GUARD` reader - need des"] +pub type I2C0_SDA_SIDE_GUARD_R = crate::FieldReader; +#[doc = "Field `I2C0_SDA_SIDE_GUARD` writer - need des"] +pub type I2C0_SDA_SIDE_GUARD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:5 - need des"] + #[inline(always)] + pub fn i2c0_scl_pulse_dur(&self) -> I2C0_SCL_PULSE_DUR_R { + I2C0_SCL_PULSE_DUR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:10 - need des"] + #[inline(always)] + pub fn i2c0_sda_side_guard(&self) -> I2C0_SDA_SIDE_GUARD_R { + I2C0_SDA_SIDE_GUARD_R::new(((self.bits >> 6) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0_CTRL1") + .field( + "i2c0_scl_pulse_dur", + &format_args!("{}", self.i2c0_scl_pulse_dur().bits()), + ) + .field( + "i2c0_sda_side_guard", + &format_args!("{}", self.i2c0_sda_side_guard().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c0_scl_pulse_dur(&mut self) -> I2C0_SCL_PULSE_DUR_W { + I2C0_SCL_PULSE_DUR_W::new(self, 0) + } + #[doc = "Bits 6:10 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c0_sda_side_guard(&mut self) -> I2C0_SDA_SIDE_GUARD_W { + I2C0_SDA_SIDE_GUARD_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c0_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c0_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C0_CTRL1_SPEC; +impl crate::RegisterSpec for I2C0_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c0_ctrl1::R`](R) reader structure"] +impl crate::Readable for I2C0_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c0_ctrl1::W`](W) writer structure"] +impl crate::Writable for I2C0_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C0_CTRL1 to value 0x42"] +impl crate::Resettable for I2C0_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0x42; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c1_conf.rs b/esp32p4/src/lp_i2c_ana_mst/i2c1_conf.rs new file mode 100644 index 0000000000..a15c49177a --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/i2c1_conf.rs @@ -0,0 +1,74 @@ +#[doc = "Register `I2C1_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `I2C1_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `I2C1_CONF` reader - need des"] +pub type I2C1_CONF_R = crate::FieldReader; +#[doc = "Field `I2C1_CONF` writer - need des"] +pub type I2C1_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Field `I2C1_STATUS` reader - need des"] +pub type I2C1_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - need des"] + #[inline(always)] + pub fn i2c1_conf(&self) -> I2C1_CONF_R { + I2C1_CONF_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bits 24:31 - need des"] + #[inline(always)] + pub fn i2c1_status(&self) -> I2C1_STATUS_R { + I2C1_STATUS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1_CONF") + .field("i2c1_conf", &format_args!("{}", self.i2c1_conf().bits())) + .field( + "i2c1_status", + &format_args!("{}", self.i2c1_status().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c1_conf(&mut self) -> I2C1_CONF_W { + I2C1_CONF_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C1_CONF_SPEC; +impl crate::RegisterSpec for I2C1_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c1_conf::R`](R) reader structure"] +impl crate::Readable for I2C1_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c1_conf::W`](W) writer structure"] +impl crate::Writable for I2C1_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C1_CONF to value 0"] +impl crate::Resettable for I2C1_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl.rs b/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl.rs new file mode 100644 index 0000000000..81a6475c62 --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl.rs @@ -0,0 +1,71 @@ +#[doc = "Register `I2C1_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `I2C1_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `I2C1_CTRL` reader - need des"] +pub type I2C1_CTRL_R = crate::FieldReader; +#[doc = "Field `I2C1_CTRL` writer - need des"] +pub type I2C1_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +#[doc = "Field `I2C1_BUSY` reader - need des"] +pub type I2C1_BUSY_R = crate::BitReader; +impl R { + #[doc = "Bits 0:24 - need des"] + #[inline(always)] + pub fn i2c1_ctrl(&self) -> I2C1_CTRL_R { + I2C1_CTRL_R::new(self.bits & 0x01ff_ffff) + } + #[doc = "Bit 25 - need des"] + #[inline(always)] + pub fn i2c1_busy(&self) -> I2C1_BUSY_R { + I2C1_BUSY_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1_CTRL") + .field("i2c1_ctrl", &format_args!("{}", self.i2c1_ctrl().bits())) + .field("i2c1_busy", &format_args!("{}", self.i2c1_busy().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:24 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c1_ctrl(&mut self) -> I2C1_CTRL_W { + I2C1_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C1_CTRL_SPEC; +impl crate::RegisterSpec for I2C1_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c1_ctrl::R`](R) reader structure"] +impl crate::Readable for I2C1_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c1_ctrl::W`](W) writer structure"] +impl crate::Writable for I2C1_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C1_CTRL to value 0"] +impl crate::Resettable for I2C1_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl1.rs b/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl1.rs new file mode 100644 index 0000000000..d3d71abbf2 --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `I2C1_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `I2C1_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `I2C1_SCL_PULSE_DUR` reader - need des"] +pub type I2C1_SCL_PULSE_DUR_R = crate::FieldReader; +#[doc = "Field `I2C1_SCL_PULSE_DUR` writer - need des"] +pub type I2C1_SCL_PULSE_DUR_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `I2C1_SDA_SIDE_GUARD` reader - need des"] +pub type I2C1_SDA_SIDE_GUARD_R = crate::FieldReader; +#[doc = "Field `I2C1_SDA_SIDE_GUARD` writer - need des"] +pub type I2C1_SDA_SIDE_GUARD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:5 - need des"] + #[inline(always)] + pub fn i2c1_scl_pulse_dur(&self) -> I2C1_SCL_PULSE_DUR_R { + I2C1_SCL_PULSE_DUR_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:10 - need des"] + #[inline(always)] + pub fn i2c1_sda_side_guard(&self) -> I2C1_SDA_SIDE_GUARD_R { + I2C1_SDA_SIDE_GUARD_R::new(((self.bits >> 6) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1_CTRL1") + .field( + "i2c1_scl_pulse_dur", + &format_args!("{}", self.i2c1_scl_pulse_dur().bits()), + ) + .field( + "i2c1_sda_side_guard", + &format_args!("{}", self.i2c1_sda_side_guard().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c1_scl_pulse_dur(&mut self) -> I2C1_SCL_PULSE_DUR_W { + I2C1_SCL_PULSE_DUR_W::new(self, 0) + } + #[doc = "Bits 6:10 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c1_sda_side_guard(&mut self) -> I2C1_SDA_SIDE_GUARD_W { + I2C1_SDA_SIDE_GUARD_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c1_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c1_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C1_CTRL1_SPEC; +impl crate::RegisterSpec for I2C1_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c1_ctrl1::R`](R) reader structure"] +impl crate::Readable for I2C1_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c1_ctrl1::W`](W) writer structure"] +impl crate::Writable for I2C1_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C1_CTRL1 to value 0x42"] +impl crate::Resettable for I2C1_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0x42; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c_burst_conf.rs b/esp32p4/src/lp_i2c_ana_mst/i2c_burst_conf.rs new file mode 100644 index 0000000000..19aeb6ce4e --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/i2c_burst_conf.rs @@ -0,0 +1,66 @@ +#[doc = "Register `I2C_BURST_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `I2C_BURST_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `I2C_MST_BURST_CTRL` reader - need des"] +pub type I2C_MST_BURST_CTRL_R = crate::FieldReader; +#[doc = "Field `I2C_MST_BURST_CTRL` writer - need des"] +pub type I2C_MST_BURST_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need des"] + #[inline(always)] + pub fn i2c_mst_burst_ctrl(&self) -> I2C_MST_BURST_CTRL_R { + I2C_MST_BURST_CTRL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C_BURST_CONF") + .field( + "i2c_mst_burst_ctrl", + &format_args!("{}", self.i2c_mst_burst_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c_mst_burst_ctrl(&mut self) -> I2C_MST_BURST_CTRL_W { + I2C_MST_BURST_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c_burst_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c_burst_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C_BURST_CONF_SPEC; +impl crate::RegisterSpec for I2C_BURST_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c_burst_conf::R`](R) reader structure"] +impl crate::Readable for I2C_BURST_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c_burst_conf::W`](W) writer structure"] +impl crate::Writable for I2C_BURST_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C_BURST_CONF to value 0"] +impl crate::Resettable for I2C_BURST_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c_burst_status.rs b/esp32p4/src/lp_i2c_ana_mst/i2c_burst_status.rs new file mode 100644 index 0000000000..962872f5b0 --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/i2c_burst_status.rs @@ -0,0 +1,101 @@ +#[doc = "Register `I2C_BURST_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `I2C_BURST_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `I2C_MST_BURST_DONE` reader - need des"] +pub type I2C_MST_BURST_DONE_R = crate::BitReader; +#[doc = "Field `I2C_MST0_BURST_ERR_FLAG` reader - need des"] +pub type I2C_MST0_BURST_ERR_FLAG_R = crate::BitReader; +#[doc = "Field `I2C_MST1_BURST_ERR_FLAG` reader - need des"] +pub type I2C_MST1_BURST_ERR_FLAG_R = crate::BitReader; +#[doc = "Field `I2C_MST_BURST_TIMEOUT_CNT` reader - need des"] +pub type I2C_MST_BURST_TIMEOUT_CNT_R = crate::FieldReader; +#[doc = "Field `I2C_MST_BURST_TIMEOUT_CNT` writer - need des"] +pub type I2C_MST_BURST_TIMEOUT_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bit 0 - need des"] + #[inline(always)] + pub fn i2c_mst_burst_done(&self) -> I2C_MST_BURST_DONE_R { + I2C_MST_BURST_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need des"] + #[inline(always)] + pub fn i2c_mst0_burst_err_flag(&self) -> I2C_MST0_BURST_ERR_FLAG_R { + I2C_MST0_BURST_ERR_FLAG_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - need des"] + #[inline(always)] + pub fn i2c_mst1_burst_err_flag(&self) -> I2C_MST1_BURST_ERR_FLAG_R { + I2C_MST1_BURST_ERR_FLAG_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 20:31 - need des"] + #[inline(always)] + pub fn i2c_mst_burst_timeout_cnt(&self) -> I2C_MST_BURST_TIMEOUT_CNT_R { + I2C_MST_BURST_TIMEOUT_CNT_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C_BURST_STATUS") + .field( + "i2c_mst_burst_done", + &format_args!("{}", self.i2c_mst_burst_done().bit()), + ) + .field( + "i2c_mst0_burst_err_flag", + &format_args!("{}", self.i2c_mst0_burst_err_flag().bit()), + ) + .field( + "i2c_mst1_burst_err_flag", + &format_args!("{}", self.i2c_mst1_burst_err_flag().bit()), + ) + .field( + "i2c_mst_burst_timeout_cnt", + &format_args!("{}", self.i2c_mst_burst_timeout_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 20:31 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c_mst_burst_timeout_cnt( + &mut self, + ) -> I2C_MST_BURST_TIMEOUT_CNT_W { + I2C_MST_BURST_TIMEOUT_CNT_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2c_burst_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2c_burst_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C_BURST_STATUS_SPEC; +impl crate::RegisterSpec for I2C_BURST_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c_burst_status::R`](R) reader structure"] +impl crate::Readable for I2C_BURST_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c_burst_status::W`](W) writer structure"] +impl crate::Writable for I2C_BURST_STATUS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets I2C_BURST_STATUS to value 0x4000_0000"] +impl crate::Resettable for I2C_BURST_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x4000_0000; +} diff --git a/esp32p4/src/lp_i2c_ana_mst/nouse.rs b/esp32p4/src/lp_i2c_ana_mst/nouse.rs new file mode 100644 index 0000000000..db9e5684cd --- /dev/null +++ b/esp32p4/src/lp_i2c_ana_mst/nouse.rs @@ -0,0 +1,66 @@ +#[doc = "Register `NOUSE` reader"] +pub type R = crate::R; +#[doc = "Register `NOUSE` writer"] +pub type W = crate::W; +#[doc = "Field `I2C_MST_NOUSE` reader - need des"] +pub type I2C_MST_NOUSE_R = crate::FieldReader; +#[doc = "Field `I2C_MST_NOUSE` writer - need des"] +pub type I2C_MST_NOUSE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need des"] + #[inline(always)] + pub fn i2c_mst_nouse(&self) -> I2C_MST_NOUSE_R { + I2C_MST_NOUSE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NOUSE") + .field( + "i2c_mst_nouse", + &format_args!("{}", self.i2c_mst_nouse().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need des"] + #[inline(always)] + #[must_use] + pub fn i2c_mst_nouse(&mut self) -> I2C_MST_NOUSE_W { + I2C_MST_NOUSE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nouse::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nouse::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NOUSE_SPEC; +impl crate::RegisterSpec for NOUSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nouse::R`](R) reader structure"] +impl crate::Readable for NOUSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nouse::W`](W) writer structure"] +impl crate::Writable for NOUSE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets NOUSE to value 0"] +impl crate::Resettable for NOUSE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0.rs b/esp32p4/src/lp_i2s0.rs new file mode 100644 index 0000000000..10e6e44841 --- /dev/null +++ b/esp32p4/src/lp_i2s0.rs @@ -0,0 +1,395 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + vad_conf: VAD_CONF, + vad_result: VAD_RESULT, + rx_mem_conf: RX_MEM_CONF, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + _reserved7: [u8; 0x04], + rx_conf: RX_CONF, + _reserved8: [u8; 0x04], + rx_conf1: RX_CONF1, + _reserved9: [u8; 0x24], + rx_tdm_ctrl: RX_TDM_CTRL, + _reserved10: [u8; 0x04], + rx_timing: RX_TIMING, + _reserved11: [u8; 0x04], + lc_hung_conf: LC_HUNG_CONF, + rxeof_num: RXEOF_NUM, + conf_sigle_data: CONF_SIGLE_DATA, + _reserved14: [u8; 0x04], + rx_pdm_conf: RX_PDM_CONF, + eco_low: ECO_LOW, + eco_high: ECO_HIGH, + eco_conf: ECO_CONF, + vad_param0: VAD_PARAM0, + vad_param1: VAD_PARAM1, + vad_param2: VAD_PARAM2, + vad_param3: VAD_PARAM3, + vad_param4: VAD_PARAM4, + vad_param5: VAD_PARAM5, + vad_param6: VAD_PARAM6, + vad_param7: VAD_PARAM7, + vad_param8: VAD_PARAM8, + _reserved27: [u8; 0x0c], + vad_ob0: VAD_OB0, + vad_ob1: VAD_OB1, + vad_ob2: VAD_OB2, + vad_ob3: VAD_OB3, + vad_ob4: VAD_OB4, + vad_ob5: VAD_OB5, + vad_ob6: VAD_OB6, + vad_ob7: VAD_OB7, + vad_ob8: VAD_OB8, + _reserved36: [u8; 0x24], + clk_gate: CLK_GATE, + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - I2S VAD Configure register"] + #[inline(always)] + pub const fn vad_conf(&self) -> &VAD_CONF { + &self.vad_conf + } + #[doc = "0x04 - I2S VAD Result register"] + #[inline(always)] + pub const fn vad_result(&self) -> &VAD_RESULT { + &self.vad_result + } + #[doc = "0x08 - I2S VAD Observe register"] + #[inline(always)] + pub const fn rx_mem_conf(&self) -> &RX_MEM_CONF { + &self.rx_mem_conf + } + #[doc = "0x0c - I2S interrupt raw register, valid in level."] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x10 - I2S interrupt status register."] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x14 - I2S interrupt enable register."] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x18 - I2S interrupt clear register."] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x20 - I2S RX configure register"] + #[inline(always)] + pub const fn rx_conf(&self) -> &RX_CONF { + &self.rx_conf + } + #[doc = "0x28 - I2S RX configure register 1"] + #[inline(always)] + pub const fn rx_conf1(&self) -> &RX_CONF1 { + &self.rx_conf1 + } + #[doc = "0x50 - I2S TX TDM mode control register"] + #[inline(always)] + pub const fn rx_tdm_ctrl(&self) -> &RX_TDM_CTRL { + &self.rx_tdm_ctrl + } + #[doc = "0x58 - I2S RX timing control register"] + #[inline(always)] + pub const fn rx_timing(&self) -> &RX_TIMING { + &self.rx_timing + } + #[doc = "0x60 - I2S HUNG configure register."] + #[inline(always)] + pub const fn lc_hung_conf(&self) -> &LC_HUNG_CONF { + &self.lc_hung_conf + } + #[doc = "0x64 - I2S RX data number control register."] + #[inline(always)] + pub const fn rxeof_num(&self) -> &RXEOF_NUM { + &self.rxeof_num + } + #[doc = "0x68 - I2S signal data register"] + #[inline(always)] + pub const fn conf_sigle_data(&self) -> &CONF_SIGLE_DATA { + &self.conf_sigle_data + } + #[doc = "0x70 - I2S RX configure register"] + #[inline(always)] + pub const fn rx_pdm_conf(&self) -> &RX_PDM_CONF { + &self.rx_pdm_conf + } + #[doc = "0x74 - I2S ECO register"] + #[inline(always)] + pub const fn eco_low(&self) -> &ECO_LOW { + &self.eco_low + } + #[doc = "0x78 - I2S ECO register"] + #[inline(always)] + pub const fn eco_high(&self) -> &ECO_HIGH { + &self.eco_high + } + #[doc = "0x7c - I2S ECO register"] + #[inline(always)] + pub const fn eco_conf(&self) -> &ECO_CONF { + &self.eco_conf + } + #[doc = "0x80 - I2S VAD Parameter register"] + #[inline(always)] + pub const fn vad_param0(&self) -> &VAD_PARAM0 { + &self.vad_param0 + } + #[doc = "0x84 - I2S VAD Parameter register"] + #[inline(always)] + pub const fn vad_param1(&self) -> &VAD_PARAM1 { + &self.vad_param1 + } + #[doc = "0x88 - I2S VAD Parameter register"] + #[inline(always)] + pub const fn vad_param2(&self) -> &VAD_PARAM2 { + &self.vad_param2 + } + #[doc = "0x8c - I2S VAD Parameter register"] + #[inline(always)] + pub const fn vad_param3(&self) -> &VAD_PARAM3 { + &self.vad_param3 + } + #[doc = "0x90 - I2S VAD Parameter register"] + #[inline(always)] + pub const fn vad_param4(&self) -> &VAD_PARAM4 { + &self.vad_param4 + } + #[doc = "0x94 - I2S VAD Parameter register"] + #[inline(always)] + pub const fn vad_param5(&self) -> &VAD_PARAM5 { + &self.vad_param5 + } + #[doc = "0x98 - I2S VAD Parameter register"] + #[inline(always)] + pub const fn vad_param6(&self) -> &VAD_PARAM6 { + &self.vad_param6 + } + #[doc = "0x9c - I2S VAD Parameter register"] + #[inline(always)] + pub const fn vad_param7(&self) -> &VAD_PARAM7 { + &self.vad_param7 + } + #[doc = "0xa0 - I2S VAD Parameter register"] + #[inline(always)] + pub const fn vad_param8(&self) -> &VAD_PARAM8 { + &self.vad_param8 + } + #[doc = "0xb0 - I2S VAD Observe register"] + #[inline(always)] + pub const fn vad_ob0(&self) -> &VAD_OB0 { + &self.vad_ob0 + } + #[doc = "0xb4 - I2S VAD Observe register"] + #[inline(always)] + pub const fn vad_ob1(&self) -> &VAD_OB1 { + &self.vad_ob1 + } + #[doc = "0xb8 - I2S VAD Observe register"] + #[inline(always)] + pub const fn vad_ob2(&self) -> &VAD_OB2 { + &self.vad_ob2 + } + #[doc = "0xbc - I2S VAD Observe register"] + #[inline(always)] + pub const fn vad_ob3(&self) -> &VAD_OB3 { + &self.vad_ob3 + } + #[doc = "0xc0 - I2S VAD Observe register"] + #[inline(always)] + pub const fn vad_ob4(&self) -> &VAD_OB4 { + &self.vad_ob4 + } + #[doc = "0xc4 - I2S VAD Observe register"] + #[inline(always)] + pub const fn vad_ob5(&self) -> &VAD_OB5 { + &self.vad_ob5 + } + #[doc = "0xc8 - I2S VAD Observe register"] + #[inline(always)] + pub const fn vad_ob6(&self) -> &VAD_OB6 { + &self.vad_ob6 + } + #[doc = "0xcc - I2S VAD Observe register"] + #[inline(always)] + pub const fn vad_ob7(&self) -> &VAD_OB7 { + &self.vad_ob7 + } + #[doc = "0xd0 - I2S VAD Observe register"] + #[inline(always)] + pub const fn vad_ob8(&self) -> &VAD_OB8 { + &self.vad_ob8 + } + #[doc = "0xf8 - Clock gate register"] + #[inline(always)] + pub const fn clk_gate(&self) -> &CLK_GATE { + &self.clk_gate + } + #[doc = "0xfc - Version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "VAD_CONF (rw) register accessor: I2S VAD Configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_conf`] module"] +pub type VAD_CONF = crate::Reg; +#[doc = "I2S VAD Configure register"] +pub mod vad_conf; +#[doc = "VAD_RESULT (r) register accessor: I2S VAD Result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_result::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_result`] module"] +pub type VAD_RESULT = crate::Reg; +#[doc = "I2S VAD Result register"] +pub mod vad_result; +#[doc = "RX_MEM_CONF (rw) register accessor: I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_mem_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_mem_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_mem_conf`] module"] +pub type RX_MEM_CONF = crate::Reg; +#[doc = "I2S VAD Observe register"] +pub mod rx_mem_conf; +#[doc = "INT_RAW (r) register accessor: I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "I2S interrupt raw register, valid in level."] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "I2S interrupt status register."] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: I2S interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "I2S interrupt enable register."] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: I2S interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "I2S interrupt clear register."] +pub mod int_clr; +#[doc = "RX_CONF (rw) register accessor: I2S RX configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_conf`] module"] +pub type RX_CONF = crate::Reg; +#[doc = "I2S RX configure register"] +pub mod rx_conf; +#[doc = "RX_CONF1 (rw) register accessor: I2S RX configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_conf1`] module"] +pub type RX_CONF1 = crate::Reg; +#[doc = "I2S RX configure register 1"] +pub mod rx_conf1; +#[doc = "RX_TDM_CTRL (rw) register accessor: I2S TX TDM mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tdm_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tdm_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_tdm_ctrl`] module"] +pub type RX_TDM_CTRL = crate::Reg; +#[doc = "I2S TX TDM mode control register"] +pub mod rx_tdm_ctrl; +#[doc = "RX_TIMING (rw) register accessor: I2S RX timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_timing::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_timing::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_timing`] module"] +pub type RX_TIMING = crate::Reg; +#[doc = "I2S RX timing control register"] +pub mod rx_timing; +#[doc = "LC_HUNG_CONF (rw) register accessor: I2S HUNG configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_hung_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lc_hung_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lc_hung_conf`] module"] +pub type LC_HUNG_CONF = crate::Reg; +#[doc = "I2S HUNG configure register."] +pub mod lc_hung_conf; +#[doc = "RXEOF_NUM (rw) register accessor: I2S RX data number control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxeof_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxeof_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxeof_num`] module"] +pub type RXEOF_NUM = crate::Reg; +#[doc = "I2S RX data number control register."] +pub mod rxeof_num; +#[doc = "CONF_SIGLE_DATA (rw) register accessor: I2S signal data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf_sigle_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf_sigle_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf_sigle_data`] module"] +pub type CONF_SIGLE_DATA = crate::Reg; +#[doc = "I2S signal data register"] +pub mod conf_sigle_data; +#[doc = "RX_PDM_CONF (rw) register accessor: I2S RX configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_pdm_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_pdm_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_pdm_conf`] module"] +pub type RX_PDM_CONF = crate::Reg; +#[doc = "I2S RX configure register"] +pub mod rx_pdm_conf; +#[doc = "ECO_LOW (rw) register accessor: I2S ECO register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_low`] module"] +pub type ECO_LOW = crate::Reg; +#[doc = "I2S ECO register"] +pub mod eco_low; +#[doc = "ECO_HIGH (rw) register accessor: I2S ECO register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_high`] module"] +pub type ECO_HIGH = crate::Reg; +#[doc = "I2S ECO register"] +pub mod eco_high; +#[doc = "ECO_CONF (rw) register accessor: I2S ECO register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_conf`] module"] +pub type ECO_CONF = crate::Reg; +#[doc = "I2S ECO register"] +pub mod eco_conf; +#[doc = "VAD_PARAM0 (rw) register accessor: I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_param0`] module"] +pub type VAD_PARAM0 = crate::Reg; +#[doc = "I2S VAD Parameter register"] +pub mod vad_param0; +#[doc = "VAD_PARAM1 (rw) register accessor: I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_param1`] module"] +pub type VAD_PARAM1 = crate::Reg; +#[doc = "I2S VAD Parameter register"] +pub mod vad_param1; +#[doc = "VAD_PARAM2 (rw) register accessor: I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_param2`] module"] +pub type VAD_PARAM2 = crate::Reg; +#[doc = "I2S VAD Parameter register"] +pub mod vad_param2; +#[doc = "VAD_PARAM3 (rw) register accessor: I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_param3`] module"] +pub type VAD_PARAM3 = crate::Reg; +#[doc = "I2S VAD Parameter register"] +pub mod vad_param3; +#[doc = "VAD_PARAM4 (rw) register accessor: I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_param4`] module"] +pub type VAD_PARAM4 = crate::Reg; +#[doc = "I2S VAD Parameter register"] +pub mod vad_param4; +#[doc = "VAD_PARAM5 (rw) register accessor: I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_param5`] module"] +pub type VAD_PARAM5 = crate::Reg; +#[doc = "I2S VAD Parameter register"] +pub mod vad_param5; +#[doc = "VAD_PARAM6 (rw) register accessor: I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_param6`] module"] +pub type VAD_PARAM6 = crate::Reg; +#[doc = "I2S VAD Parameter register"] +pub mod vad_param6; +#[doc = "VAD_PARAM7 (rw) register accessor: I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_param7`] module"] +pub type VAD_PARAM7 = crate::Reg; +#[doc = "I2S VAD Parameter register"] +pub mod vad_param7; +#[doc = "VAD_PARAM8 (rw) register accessor: I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_param8`] module"] +pub type VAD_PARAM8 = crate::Reg; +#[doc = "I2S VAD Parameter register"] +pub mod vad_param8; +#[doc = "VAD_OB0 (r) register accessor: I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_ob0`] module"] +pub type VAD_OB0 = crate::Reg; +#[doc = "I2S VAD Observe register"] +pub mod vad_ob0; +#[doc = "VAD_OB1 (r) register accessor: I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_ob1`] module"] +pub type VAD_OB1 = crate::Reg; +#[doc = "I2S VAD Observe register"] +pub mod vad_ob1; +#[doc = "VAD_OB2 (r) register accessor: I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_ob2`] module"] +pub type VAD_OB2 = crate::Reg; +#[doc = "I2S VAD Observe register"] +pub mod vad_ob2; +#[doc = "VAD_OB3 (r) register accessor: I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_ob3`] module"] +pub type VAD_OB3 = crate::Reg; +#[doc = "I2S VAD Observe register"] +pub mod vad_ob3; +#[doc = "VAD_OB4 (r) register accessor: I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_ob4`] module"] +pub type VAD_OB4 = crate::Reg; +#[doc = "I2S VAD Observe register"] +pub mod vad_ob4; +#[doc = "VAD_OB5 (r) register accessor: I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_ob5`] module"] +pub type VAD_OB5 = crate::Reg; +#[doc = "I2S VAD Observe register"] +pub mod vad_ob5; +#[doc = "VAD_OB6 (r) register accessor: I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_ob6`] module"] +pub type VAD_OB6 = crate::Reg; +#[doc = "I2S VAD Observe register"] +pub mod vad_ob6; +#[doc = "VAD_OB7 (r) register accessor: I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_ob7`] module"] +pub type VAD_OB7 = crate::Reg; +#[doc = "I2S VAD Observe register"] +pub mod vad_ob7; +#[doc = "VAD_OB8 (r) register accessor: I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vad_ob8`] module"] +pub type VAD_OB8 = crate::Reg; +#[doc = "I2S VAD Observe register"] +pub mod vad_ob8; +#[doc = "CLK_GATE (rw) register accessor: Clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_gate`] module"] +pub type CLK_GATE = crate::Reg; +#[doc = "Clock gate register"] +pub mod clk_gate; +#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version control register"] +pub mod date; diff --git a/esp32p4/src/lp_i2s0/clk_gate.rs b/esp32p4/src/lp_i2s0/clk_gate.rs new file mode 100644 index 0000000000..20d009d31d --- /dev/null +++ b/esp32p4/src/lp_i2s0/clk_gate.rs @@ -0,0 +1,120 @@ +#[doc = "Register `CLK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - set this bit to enable clock gate"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - set this bit to enable clock gate"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VAD_CG_FORCE_ON` reader - VAD clock gate force on register"] +pub type VAD_CG_FORCE_ON_R = crate::BitReader; +#[doc = "Field `VAD_CG_FORCE_ON` writer - VAD clock gate force on register"] +pub type VAD_CG_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_MEM_CG_FORCE_ON` reader - I2S rx mem clock gate force on register"] +pub type RX_MEM_CG_FORCE_ON_R = crate::BitReader; +#[doc = "Field `RX_MEM_CG_FORCE_ON` writer - I2S rx mem clock gate force on register"] +pub type RX_MEM_CG_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_REG_CG_FORCE_ON` reader - I2S rx reg clock gate force on register"] +pub type RX_REG_CG_FORCE_ON_R = crate::BitReader; +#[doc = "Field `RX_REG_CG_FORCE_ON` writer - I2S rx reg clock gate force on register"] +pub type RX_REG_CG_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - set this bit to enable clock gate"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - VAD clock gate force on register"] + #[inline(always)] + pub fn vad_cg_force_on(&self) -> VAD_CG_FORCE_ON_R { + VAD_CG_FORCE_ON_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - I2S rx mem clock gate force on register"] + #[inline(always)] + pub fn rx_mem_cg_force_on(&self) -> RX_MEM_CG_FORCE_ON_R { + RX_MEM_CG_FORCE_ON_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - I2S rx reg clock gate force on register"] + #[inline(always)] + pub fn rx_reg_cg_force_on(&self) -> RX_REG_CG_FORCE_ON_R { + RX_REG_CG_FORCE_ON_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_GATE") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field( + "vad_cg_force_on", + &format_args!("{}", self.vad_cg_force_on().bit()), + ) + .field( + "rx_mem_cg_force_on", + &format_args!("{}", self.rx_mem_cg_force_on().bit()), + ) + .field( + "rx_reg_cg_force_on", + &format_args!("{}", self.rx_reg_cg_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this bit to enable clock gate"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - VAD clock gate force on register"] + #[inline(always)] + #[must_use] + pub fn vad_cg_force_on(&mut self) -> VAD_CG_FORCE_ON_W { + VAD_CG_FORCE_ON_W::new(self, 1) + } + #[doc = "Bit 2 - I2S rx mem clock gate force on register"] + #[inline(always)] + #[must_use] + pub fn rx_mem_cg_force_on(&mut self) -> RX_MEM_CG_FORCE_ON_W { + RX_MEM_CG_FORCE_ON_W::new(self, 2) + } + #[doc = "Bit 3 - I2S rx reg clock gate force on register"] + #[inline(always)] + #[must_use] + pub fn rx_reg_cg_force_on(&mut self) -> RX_REG_CG_FORCE_ON_W { + RX_REG_CG_FORCE_ON_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GATE_SPEC; +impl crate::RegisterSpec for CLK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gate::R`](R) reader structure"] +impl crate::Readable for CLK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gate::W`](W) writer structure"] +impl crate::Writable for CLK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_GATE to value 0x0a"] +impl crate::Resettable for CLK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0a; +} diff --git a/esp32p4/src/lp_i2s0/conf_sigle_data.rs b/esp32p4/src/lp_i2s0/conf_sigle_data.rs new file mode 100644 index 0000000000..4dced54c8d --- /dev/null +++ b/esp32p4/src/lp_i2s0/conf_sigle_data.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CONF_SIGLE_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `CONF_SIGLE_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `SINGLE_DATA` reader - The configured constant channel data to be sent out."] +pub type SINGLE_DATA_R = crate::FieldReader; +#[doc = "Field `SINGLE_DATA` writer - The configured constant channel data to be sent out."] +pub type SINGLE_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The configured constant channel data to be sent out."] + #[inline(always)] + pub fn single_data(&self) -> SINGLE_DATA_R { + SINGLE_DATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF_SIGLE_DATA") + .field( + "single_data", + &format_args!("{}", self.single_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The configured constant channel data to be sent out."] + #[inline(always)] + #[must_use] + pub fn single_data(&mut self) -> SINGLE_DATA_W { + SINGLE_DATA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S signal data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf_sigle_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf_sigle_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SIGLE_DATA_SPEC; +impl crate::RegisterSpec for CONF_SIGLE_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf_sigle_data::R`](R) reader structure"] +impl crate::Readable for CONF_SIGLE_DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf_sigle_data::W`](W) writer structure"] +impl crate::Writable for CONF_SIGLE_DATA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF_SIGLE_DATA to value 0"] +impl crate::Resettable for CONF_SIGLE_DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/date.rs b/esp32p4/src/lp_i2s0/date.rs new file mode 100644 index 0000000000..e04c07fe94 --- /dev/null +++ b/esp32p4/src/lp_i2s0/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - I2S version control register"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - I2S version control register"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - I2S version control register"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - I2S version control register"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_5040"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_5040; +} diff --git a/esp32p4/src/lp_i2s0/eco_conf.rs b/esp32p4/src/lp_i2s0/eco_conf.rs new file mode 100644 index 0000000000..717fb2b963 --- /dev/null +++ b/esp32p4/src/lp_i2s0/eco_conf.rs @@ -0,0 +1,71 @@ +#[doc = "Register `ECO_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ENA` reader - enable rdn counter bit"] +pub type RDN_ENA_R = crate::BitReader; +#[doc = "Field `RDN_ENA` writer - enable rdn counter bit"] +pub type RDN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RDN_RESULT` reader - rdn result"] +pub type RDN_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - enable rdn counter bit"] + #[inline(always)] + pub fn rdn_ena(&self) -> RDN_ENA_R { + RDN_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - rdn result"] + #[inline(always)] + pub fn rdn_result(&self) -> RDN_RESULT_R { + RDN_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_CONF") + .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit())) + .field("rdn_result", &format_args!("{}", self.rdn_result().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - enable rdn counter bit"] + #[inline(always)] + #[must_use] + pub fn rdn_ena(&mut self) -> RDN_ENA_W { + RDN_ENA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S ECO register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_CONF_SPEC; +impl crate::RegisterSpec for ECO_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_conf::R`](R) reader structure"] +impl crate::Readable for ECO_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_conf::W`](W) writer structure"] +impl crate::Writable for ECO_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_CONF to value 0"] +impl crate::Resettable for ECO_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/eco_high.rs b/esp32p4/src/lp_i2s0/eco_high.rs new file mode 100644 index 0000000000..e52f30d95c --- /dev/null +++ b/esp32p4/src/lp_i2s0/eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_HIGH` reader - logic high eco registers"] +pub type RDN_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_HIGH` writer - logic high eco registers"] +pub type RDN_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - logic high eco registers"] + #[inline(always)] + pub fn rdn_eco_high(&self) -> RDN_ECO_HIGH_R { + RDN_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_HIGH") + .field( + "rdn_eco_high", + &format_args!("{}", self.rdn_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - logic high eco registers"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_high(&mut self) -> RDN_ECO_HIGH_W { + RDN_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S ECO register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_HIGH_SPEC; +impl crate::RegisterSpec for ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_high::R`](R) reader structure"] +impl crate::Readable for ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_high::W`](W) writer structure"] +impl crate::Writable for ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_i2s0/eco_low.rs b/esp32p4/src/lp_i2s0/eco_low.rs new file mode 100644 index 0000000000..6b4d4020d8 --- /dev/null +++ b/esp32p4/src/lp_i2s0/eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_LOW` reader - logic low eco registers"] +pub type RDN_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_LOW` writer - logic low eco registers"] +pub type RDN_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - logic low eco registers"] + #[inline(always)] + pub fn rdn_eco_low(&self) -> RDN_ECO_LOW_R { + RDN_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_LOW") + .field( + "rdn_eco_low", + &format_args!("{}", self.rdn_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - logic low eco registers"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_low(&mut self) -> RDN_ECO_LOW_W { + RDN_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S ECO register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_LOW_SPEC; +impl crate::RegisterSpec for ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_low::R`](R) reader structure"] +impl crate::Readable for ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_low::W`](W) writer structure"] +impl crate::Writable for ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_LOW to value 0"] +impl crate::Resettable for ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/int_clr.rs b/esp32p4/src/lp_i2s0/int_clr.rs new file mode 100644 index 0000000000..3b40bcbb1e --- /dev/null +++ b/esp32p4/src/lp_i2s0/int_clr.rs @@ -0,0 +1,82 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RX_DONE_INT_CLR` writer - Set this bit to clear the i2s_rx_done_int interrupt"] +pub type RX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_HUNG_INT_CLR` writer - Set this bit to clear the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFOMEM_UDF_INT_CLR` writer - Set this bit to clear the i2s_rx_fifomem_udf_int interrupt"] +pub type RX_FIFOMEM_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_VAD_DONE_INT_CLR` writer - Set this bit to clear the vad_done_int interrupt"] +pub type LP_VAD_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_VAD_RESET_DONE_INT_CLR` writer - Set this bit to clear the vad_reset_done_int interrupt"] +pub type LP_VAD_RESET_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_MEM_THRESHOLD_INT_CLR` writer - Set this bit to clear the rx_mem_threshold_int interrupt"] +pub type RX_MEM_THRESHOLD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the i2s_rx_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_done_int_clr(&mut self) -> RX_DONE_INT_CLR_W { + RX_DONE_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the i2s_rx_hung_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_hung_int_clr(&mut self) -> RX_HUNG_INT_CLR_W { + RX_HUNG_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the i2s_rx_fifomem_udf_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_fifomem_udf_int_clr(&mut self) -> RX_FIFOMEM_UDF_INT_CLR_W { + RX_FIFOMEM_UDF_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the vad_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn lp_vad_done_int_clr(&mut self) -> LP_VAD_DONE_INT_CLR_W { + LP_VAD_DONE_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the vad_reset_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn lp_vad_reset_done_int_clr(&mut self) -> LP_VAD_RESET_DONE_INT_CLR_W { + LP_VAD_RESET_DONE_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the rx_mem_threshold_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_mem_threshold_int_clr(&mut self) -> RX_MEM_THRESHOLD_INT_CLR_W { + RX_MEM_THRESHOLD_INT_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/int_ena.rs b/esp32p4/src/lp_i2s0/int_ena.rs new file mode 100644 index 0000000000..da41c02ea7 --- /dev/null +++ b/esp32p4/src/lp_i2s0/int_ena.rs @@ -0,0 +1,161 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `RX_DONE_INT_ENA` reader - The interrupt enable bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `RX_DONE_INT_ENA` writer - The interrupt enable bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_HUNG_INT_ENA` reader - The interrupt enable bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_INT_ENA_R = crate::BitReader; +#[doc = "Field `RX_HUNG_INT_ENA` writer - The interrupt enable bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFOMEM_UDF_INT_ENA` reader - The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt"] +pub type RX_FIFOMEM_UDF_INT_ENA_R = crate::BitReader; +#[doc = "Field `RX_FIFOMEM_UDF_INT_ENA` writer - The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt"] +pub type RX_FIFOMEM_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_VAD_DONE_INT_ENA` reader - The interrupt enable bit for the vad_done_int interrupt"] +pub type LP_VAD_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_VAD_DONE_INT_ENA` writer - The interrupt enable bit for the vad_done_int interrupt"] +pub type LP_VAD_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_VAD_RESET_DONE_INT_ENA` reader - The interrupt enable bit for the vad_reset_done_int interrupt"] +pub type LP_VAD_RESET_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_VAD_RESET_DONE_INT_ENA` writer - The interrupt enable bit for the vad_reset_done_int interrupt"] +pub type LP_VAD_RESET_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_MEM_THRESHOLD_INT_ENA` reader - The interrupt enable bit for the rx_mem_threshold_int interrupt"] +pub type RX_MEM_THRESHOLD_INT_ENA_R = crate::BitReader; +#[doc = "Field `RX_MEM_THRESHOLD_INT_ENA` writer - The interrupt enable bit for the rx_mem_threshold_int interrupt"] +pub type RX_MEM_THRESHOLD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"] + #[inline(always)] + pub fn rx_done_int_ena(&self) -> RX_DONE_INT_ENA_R { + RX_DONE_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the i2s_rx_hung_int interrupt"] + #[inline(always)] + pub fn rx_hung_int_ena(&self) -> RX_HUNG_INT_ENA_R { + RX_HUNG_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt"] + #[inline(always)] + pub fn rx_fifomem_udf_int_ena(&self) -> RX_FIFOMEM_UDF_INT_ENA_R { + RX_FIFOMEM_UDF_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the vad_done_int interrupt"] + #[inline(always)] + pub fn lp_vad_done_int_ena(&self) -> LP_VAD_DONE_INT_ENA_R { + LP_VAD_DONE_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the vad_reset_done_int interrupt"] + #[inline(always)] + pub fn lp_vad_reset_done_int_ena(&self) -> LP_VAD_RESET_DONE_INT_ENA_R { + LP_VAD_RESET_DONE_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the rx_mem_threshold_int interrupt"] + #[inline(always)] + pub fn rx_mem_threshold_int_ena(&self) -> RX_MEM_THRESHOLD_INT_ENA_R { + RX_MEM_THRESHOLD_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "rx_done_int_ena", + &format_args!("{}", self.rx_done_int_ena().bit()), + ) + .field( + "rx_hung_int_ena", + &format_args!("{}", self.rx_hung_int_ena().bit()), + ) + .field( + "rx_fifomem_udf_int_ena", + &format_args!("{}", self.rx_fifomem_udf_int_ena().bit()), + ) + .field( + "lp_vad_done_int_ena", + &format_args!("{}", self.lp_vad_done_int_ena().bit()), + ) + .field( + "lp_vad_reset_done_int_ena", + &format_args!("{}", self.lp_vad_reset_done_int_ena().bit()), + ) + .field( + "rx_mem_threshold_int_ena", + &format_args!("{}", self.rx_mem_threshold_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_done_int_ena(&mut self) -> RX_DONE_INT_ENA_W { + RX_DONE_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the i2s_rx_hung_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_hung_int_ena(&mut self) -> RX_HUNG_INT_ENA_W { + RX_HUNG_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_fifomem_udf_int_ena(&mut self) -> RX_FIFOMEM_UDF_INT_ENA_W { + RX_FIFOMEM_UDF_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the vad_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn lp_vad_done_int_ena(&mut self) -> LP_VAD_DONE_INT_ENA_W { + LP_VAD_DONE_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the vad_reset_done_int interrupt"] + #[inline(always)] + #[must_use] + pub fn lp_vad_reset_done_int_ena(&mut self) -> LP_VAD_RESET_DONE_INT_ENA_W { + LP_VAD_RESET_DONE_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the rx_mem_threshold_int interrupt"] + #[inline(always)] + #[must_use] + pub fn rx_mem_threshold_int_ena(&mut self) -> RX_MEM_THRESHOLD_INT_ENA_W { + RX_MEM_THRESHOLD_INT_ENA_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/int_raw.rs b/esp32p4/src/lp_i2s0/int_raw.rs new file mode 100644 index 0000000000..1c0157ef22 --- /dev/null +++ b/esp32p4/src/lp_i2s0/int_raw.rs @@ -0,0 +1,94 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `RX_DONE_INT_RAW` reader - The raw interrupt status bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_HUNG_INT_RAW` reader - The raw interrupt status bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_FIFOMEM_UDF_INT_RAW` reader - The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt"] +pub type RX_FIFOMEM_UDF_INT_RAW_R = crate::BitReader; +#[doc = "Field `VAD_DONE_INT_RAW` reader - The raw interrupt status bit for the vad_done_int interrupt"] +pub type VAD_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `VAD_RESET_DONE_INT_RAW` reader - The raw interrupt status bit for the vad_reset_done_int interrupt"] +pub type VAD_RESET_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_MEM_THRESHOLD_INT_RAW` reader - The raw interrupt status bit for the rx_mem_threshold_int interrupt"] +pub type RX_MEM_THRESHOLD_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the i2s_rx_done_int interrupt"] + #[inline(always)] + pub fn rx_done_int_raw(&self) -> RX_DONE_INT_RAW_R { + RX_DONE_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the i2s_rx_hung_int interrupt"] + #[inline(always)] + pub fn rx_hung_int_raw(&self) -> RX_HUNG_INT_RAW_R { + RX_HUNG_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt"] + #[inline(always)] + pub fn rx_fifomem_udf_int_raw(&self) -> RX_FIFOMEM_UDF_INT_RAW_R { + RX_FIFOMEM_UDF_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the vad_done_int interrupt"] + #[inline(always)] + pub fn vad_done_int_raw(&self) -> VAD_DONE_INT_RAW_R { + VAD_DONE_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the vad_reset_done_int interrupt"] + #[inline(always)] + pub fn vad_reset_done_int_raw(&self) -> VAD_RESET_DONE_INT_RAW_R { + VAD_RESET_DONE_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the rx_mem_threshold_int interrupt"] + #[inline(always)] + pub fn rx_mem_threshold_int_raw(&self) -> RX_MEM_THRESHOLD_INT_RAW_R { + RX_MEM_THRESHOLD_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "rx_done_int_raw", + &format_args!("{}", self.rx_done_int_raw().bit()), + ) + .field( + "rx_hung_int_raw", + &format_args!("{}", self.rx_hung_int_raw().bit()), + ) + .field( + "rx_fifomem_udf_int_raw", + &format_args!("{}", self.rx_fifomem_udf_int_raw().bit()), + ) + .field( + "vad_done_int_raw", + &format_args!("{}", self.vad_done_int_raw().bit()), + ) + .field( + "vad_reset_done_int_raw", + &format_args!("{}", self.vad_reset_done_int_raw().bit()), + ) + .field( + "rx_mem_threshold_int_raw", + &format_args!("{}", self.rx_mem_threshold_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/int_st.rs b/esp32p4/src/lp_i2s0/int_st.rs new file mode 100644 index 0000000000..bbfbfab74a --- /dev/null +++ b/esp32p4/src/lp_i2s0/int_st.rs @@ -0,0 +1,94 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `RX_DONE_INT_ST` reader - The masked interrupt status bit for the i2s_rx_done_int interrupt"] +pub type RX_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_HUNG_INT_ST` reader - The masked interrupt status bit for the i2s_rx_hung_int interrupt"] +pub type RX_HUNG_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_FIFOMEM_UDF_INT_ST` reader - The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt"] +pub type RX_FIFOMEM_UDF_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_VAD_DONE_INT_ST` reader - The masked interrupt status bit for the vad_done_int interrupt"] +pub type LP_VAD_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_VAD_RESET_DONE_INT_ST` reader - The masked interrupt status bit for the vad_reset_done_int interrupt"] +pub type LP_VAD_RESET_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_MEM_THRESHOLD_INT_ST` reader - The masked interrupt status bit for the rx_mem_threshold_int interrupt"] +pub type RX_MEM_THRESHOLD_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status bit for the i2s_rx_done_int interrupt"] + #[inline(always)] + pub fn rx_done_int_st(&self) -> RX_DONE_INT_ST_R { + RX_DONE_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status bit for the i2s_rx_hung_int interrupt"] + #[inline(always)] + pub fn rx_hung_int_st(&self) -> RX_HUNG_INT_ST_R { + RX_HUNG_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt"] + #[inline(always)] + pub fn rx_fifomem_udf_int_st(&self) -> RX_FIFOMEM_UDF_INT_ST_R { + RX_FIFOMEM_UDF_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The masked interrupt status bit for the vad_done_int interrupt"] + #[inline(always)] + pub fn lp_vad_done_int_st(&self) -> LP_VAD_DONE_INT_ST_R { + LP_VAD_DONE_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The masked interrupt status bit for the vad_reset_done_int interrupt"] + #[inline(always)] + pub fn lp_vad_reset_done_int_st(&self) -> LP_VAD_RESET_DONE_INT_ST_R { + LP_VAD_RESET_DONE_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The masked interrupt status bit for the rx_mem_threshold_int interrupt"] + #[inline(always)] + pub fn rx_mem_threshold_int_st(&self) -> RX_MEM_THRESHOLD_INT_ST_R { + RX_MEM_THRESHOLD_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "rx_done_int_st", + &format_args!("{}", self.rx_done_int_st().bit()), + ) + .field( + "rx_hung_int_st", + &format_args!("{}", self.rx_hung_int_st().bit()), + ) + .field( + "rx_fifomem_udf_int_st", + &format_args!("{}", self.rx_fifomem_udf_int_st().bit()), + ) + .field( + "lp_vad_done_int_st", + &format_args!("{}", self.lp_vad_done_int_st().bit()), + ) + .field( + "lp_vad_reset_done_int_st", + &format_args!("{}", self.lp_vad_reset_done_int_st().bit()), + ) + .field( + "rx_mem_threshold_int_st", + &format_args!("{}", self.rx_mem_threshold_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/lc_hung_conf.rs b/esp32p4/src/lp_i2s0/lc_hung_conf.rs new file mode 100644 index 0000000000..b10dfd36c9 --- /dev/null +++ b/esp32p4/src/lp_i2s0/lc_hung_conf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `LC_HUNG_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `LC_HUNG_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `LC_FIFO_TIMEOUT` reader - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"] +pub type LC_FIFO_TIMEOUT_R = crate::FieldReader; +#[doc = "Field `LC_FIFO_TIMEOUT` writer - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"] +pub type LC_FIFO_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LC_FIFO_TIMEOUT_SHIFT` reader - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"] +pub type LC_FIFO_TIMEOUT_SHIFT_R = crate::FieldReader; +#[doc = "Field `LC_FIFO_TIMEOUT_SHIFT` writer - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"] +pub type LC_FIFO_TIMEOUT_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LC_FIFO_TIMEOUT_ENA` reader - The enable bit for FIFO timeout"] +pub type LC_FIFO_TIMEOUT_ENA_R = crate::BitReader; +#[doc = "Field `LC_FIFO_TIMEOUT_ENA` writer - The enable bit for FIFO timeout"] +pub type LC_FIFO_TIMEOUT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"] + #[inline(always)] + pub fn lc_fifo_timeout(&self) -> LC_FIFO_TIMEOUT_R { + LC_FIFO_TIMEOUT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"] + #[inline(always)] + pub fn lc_fifo_timeout_shift(&self) -> LC_FIFO_TIMEOUT_SHIFT_R { + LC_FIFO_TIMEOUT_SHIFT_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - The enable bit for FIFO timeout"] + #[inline(always)] + pub fn lc_fifo_timeout_ena(&self) -> LC_FIFO_TIMEOUT_ENA_R { + LC_FIFO_TIMEOUT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LC_HUNG_CONF") + .field( + "lc_fifo_timeout", + &format_args!("{}", self.lc_fifo_timeout().bits()), + ) + .field( + "lc_fifo_timeout_shift", + &format_args!("{}", self.lc_fifo_timeout_shift().bits()), + ) + .field( + "lc_fifo_timeout_ena", + &format_args!("{}", self.lc_fifo_timeout_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"] + #[inline(always)] + #[must_use] + pub fn lc_fifo_timeout(&mut self) -> LC_FIFO_TIMEOUT_W { + LC_FIFO_TIMEOUT_W::new(self, 0) + } + #[doc = "Bits 8:10 - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"] + #[inline(always)] + #[must_use] + pub fn lc_fifo_timeout_shift(&mut self) -> LC_FIFO_TIMEOUT_SHIFT_W { + LC_FIFO_TIMEOUT_SHIFT_W::new(self, 8) + } + #[doc = "Bit 11 - The enable bit for FIFO timeout"] + #[inline(always)] + #[must_use] + pub fn lc_fifo_timeout_ena(&mut self) -> LC_FIFO_TIMEOUT_ENA_W { + LC_FIFO_TIMEOUT_ENA_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S HUNG configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_hung_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lc_hung_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LC_HUNG_CONF_SPEC; +impl crate::RegisterSpec for LC_HUNG_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lc_hung_conf::R`](R) reader structure"] +impl crate::Readable for LC_HUNG_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lc_hung_conf::W`](W) writer structure"] +impl crate::Writable for LC_HUNG_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LC_HUNG_CONF to value 0x0810"] +impl crate::Resettable for LC_HUNG_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0810; +} diff --git a/esp32p4/src/lp_i2s0/rx_conf.rs b/esp32p4/src/lp_i2s0/rx_conf.rs new file mode 100644 index 0000000000..97f62e8781 --- /dev/null +++ b/esp32p4/src/lp_i2s0/rx_conf.rs @@ -0,0 +1,341 @@ +#[doc = "Register `RX_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `RX_RESET` writer - Set this bit to reset receiver"] +pub type RX_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFO_RESET` writer - Set this bit to reset Rx AFIFO"] +pub type RX_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_START` reader - Set this bit to start receiving data"] +pub type RX_START_R = crate::BitReader; +#[doc = "Field `RX_START` writer - Set this bit to start receiving data"] +pub type RX_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_SLAVE_MOD` reader - Set this bit to enable slave receiver mode"] +pub type RX_SLAVE_MOD_R = crate::BitReader; +#[doc = "Field `RX_SLAVE_MOD` writer - Set this bit to enable slave receiver mode"] +pub type RX_SLAVE_MOD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFOMEM_RESET` writer - Set this bit to reset Rx Syncfifomem"] +pub type RX_FIFOMEM_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_MONO` reader - Set this bit to enable receiver in mono mode"] +pub type RX_MONO_R = crate::BitReader; +#[doc = "Field `RX_MONO` writer - Set this bit to enable receiver in mono mode"] +pub type RX_MONO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_BIG_ENDIAN` reader - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] +pub type RX_BIG_ENDIAN_R = crate::BitReader; +#[doc = "Field `RX_BIG_ENDIAN` writer - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] +pub type RX_BIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_UPDATE` reader - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."] +pub type RX_UPDATE_R = crate::BitReader; +#[doc = "Field `RX_UPDATE` writer - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."] +pub type RX_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_MONO_FST_VLD` reader - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."] +pub type RX_MONO_FST_VLD_R = crate::BitReader; +#[doc = "Field `RX_MONO_FST_VLD` writer - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."] +pub type RX_MONO_FST_VLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PCM_CONF` reader - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] +pub type RX_PCM_CONF_R = crate::FieldReader; +#[doc = "Field `RX_PCM_CONF` writer - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] +pub type RX_PCM_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_PCM_BYPASS` reader - Set this bit to bypass Compress/Decompress module for received data."] +pub type RX_PCM_BYPASS_R = crate::BitReader; +#[doc = "Field `RX_PCM_BYPASS` writer - Set this bit to bypass Compress/Decompress module for received data."] +pub type RX_PCM_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_STOP_MODE` reader - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."] +pub type RX_STOP_MODE_R = crate::FieldReader; +#[doc = "Field `RX_STOP_MODE` writer - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."] +pub type RX_STOP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_LEFT_ALIGN` reader - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."] +pub type RX_LEFT_ALIGN_R = crate::BitReader; +#[doc = "Field `RX_LEFT_ALIGN` writer - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."] +pub type RX_LEFT_ALIGN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_24_FILL_EN` reader - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."] +pub type RX_24_FILL_EN_R = crate::BitReader; +#[doc = "Field `RX_24_FILL_EN` writer - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."] +pub type RX_24_FILL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_WS_IDLE_POL` reader - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."] +pub type RX_WS_IDLE_POL_R = crate::BitReader; +#[doc = "Field `RX_WS_IDLE_POL` writer - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."] +pub type RX_WS_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_BIT_ORDER` reader - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."] +pub type RX_BIT_ORDER_R = crate::BitReader; +#[doc = "Field `RX_BIT_ORDER` writer - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."] +pub type RX_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_EN` reader - 1: Enable I2S TDM Rx mode . 0: Disable."] +pub type RX_TDM_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_EN` writer - 1: Enable I2S TDM Rx mode . 0: Disable."] +pub type RX_TDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PDM_EN` reader - 1: Enable I2S PDM Rx mode . 0: Disable."] +pub type RX_PDM_EN_R = crate::BitReader; +#[doc = "Field `RX_PDM_EN` writer - 1: Enable I2S PDM Rx mode . 0: Disable."] +pub type RX_PDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Set this bit to start receiving data"] + #[inline(always)] + pub fn rx_start(&self) -> RX_START_R { + RX_START_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to enable slave receiver mode"] + #[inline(always)] + pub fn rx_slave_mod(&self) -> RX_SLAVE_MOD_R { + RX_SLAVE_MOD_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Set this bit to enable receiver in mono mode"] + #[inline(always)] + pub fn rx_mono(&self) -> RX_MONO_R { + RX_MONO_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] + #[inline(always)] + pub fn rx_big_endian(&self) -> RX_BIG_ENDIAN_R { + RX_BIG_ENDIAN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."] + #[inline(always)] + pub fn rx_update(&self) -> RX_UPDATE_R { + RX_UPDATE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."] + #[inline(always)] + pub fn rx_mono_fst_vld(&self) -> RX_MONO_FST_VLD_R { + RX_MONO_FST_VLD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] + #[inline(always)] + pub fn rx_pcm_conf(&self) -> RX_PCM_CONF_R { + RX_PCM_CONF_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for received data."] + #[inline(always)] + pub fn rx_pcm_bypass(&self) -> RX_PCM_BYPASS_R { + RX_PCM_BYPASS_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:14 - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."] + #[inline(always)] + pub fn rx_stop_mode(&self) -> RX_STOP_MODE_R { + RX_STOP_MODE_R::new(((self.bits >> 13) & 3) as u8) + } + #[doc = "Bit 15 - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."] + #[inline(always)] + pub fn rx_left_align(&self) -> RX_LEFT_ALIGN_R { + RX_LEFT_ALIGN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."] + #[inline(always)] + pub fn rx_24_fill_en(&self) -> RX_24_FILL_EN_R { + RX_24_FILL_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."] + #[inline(always)] + pub fn rx_ws_idle_pol(&self) -> RX_WS_IDLE_POL_R { + RX_WS_IDLE_POL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."] + #[inline(always)] + pub fn rx_bit_order(&self) -> RX_BIT_ORDER_R { + RX_BIT_ORDER_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - 1: Enable I2S TDM Rx mode . 0: Disable."] + #[inline(always)] + pub fn rx_tdm_en(&self) -> RX_TDM_EN_R { + RX_TDM_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - 1: Enable I2S PDM Rx mode . 0: Disable."] + #[inline(always)] + pub fn rx_pdm_en(&self) -> RX_PDM_EN_R { + RX_PDM_EN_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CONF") + .field("rx_start", &format_args!("{}", self.rx_start().bit())) + .field( + "rx_slave_mod", + &format_args!("{}", self.rx_slave_mod().bit()), + ) + .field("rx_mono", &format_args!("{}", self.rx_mono().bit())) + .field( + "rx_big_endian", + &format_args!("{}", self.rx_big_endian().bit()), + ) + .field("rx_update", &format_args!("{}", self.rx_update().bit())) + .field( + "rx_mono_fst_vld", + &format_args!("{}", self.rx_mono_fst_vld().bit()), + ) + .field( + "rx_pcm_conf", + &format_args!("{}", self.rx_pcm_conf().bits()), + ) + .field( + "rx_pcm_bypass", + &format_args!("{}", self.rx_pcm_bypass().bit()), + ) + .field( + "rx_stop_mode", + &format_args!("{}", self.rx_stop_mode().bits()), + ) + .field( + "rx_left_align", + &format_args!("{}", self.rx_left_align().bit()), + ) + .field( + "rx_24_fill_en", + &format_args!("{}", self.rx_24_fill_en().bit()), + ) + .field( + "rx_ws_idle_pol", + &format_args!("{}", self.rx_ws_idle_pol().bit()), + ) + .field( + "rx_bit_order", + &format_args!("{}", self.rx_bit_order().bit()), + ) + .field("rx_tdm_en", &format_args!("{}", self.rx_tdm_en().bit())) + .field("rx_pdm_en", &format_args!("{}", self.rx_pdm_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to reset receiver"] + #[inline(always)] + #[must_use] + pub fn rx_reset(&mut self) -> RX_RESET_W { + RX_RESET_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to reset Rx AFIFO"] + #[inline(always)] + #[must_use] + pub fn rx_fifo_reset(&mut self) -> RX_FIFO_RESET_W { + RX_FIFO_RESET_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to start receiving data"] + #[inline(always)] + #[must_use] + pub fn rx_start(&mut self) -> RX_START_W { + RX_START_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to enable slave receiver mode"] + #[inline(always)] + #[must_use] + pub fn rx_slave_mod(&mut self) -> RX_SLAVE_MOD_W { + RX_SLAVE_MOD_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to reset Rx Syncfifomem"] + #[inline(always)] + #[must_use] + pub fn rx_fifomem_reset(&mut self) -> RX_FIFOMEM_RESET_W { + RX_FIFOMEM_RESET_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to enable receiver in mono mode"] + #[inline(always)] + #[must_use] + pub fn rx_mono(&mut self) -> RX_MONO_W { + RX_MONO_W::new(self, 5) + } + #[doc = "Bit 7 - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."] + #[inline(always)] + #[must_use] + pub fn rx_big_endian(&mut self) -> RX_BIG_ENDIAN_W { + RX_BIG_ENDIAN_W::new(self, 7) + } + #[doc = "Bit 8 - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."] + #[inline(always)] + #[must_use] + pub fn rx_update(&mut self) -> RX_UPDATE_W { + RX_UPDATE_W::new(self, 8) + } + #[doc = "Bit 9 - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."] + #[inline(always)] + #[must_use] + pub fn rx_mono_fst_vld(&mut self) -> RX_MONO_FST_VLD_W { + RX_MONO_FST_VLD_W::new(self, 9) + } + #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"] + #[inline(always)] + #[must_use] + pub fn rx_pcm_conf(&mut self) -> RX_PCM_CONF_W { + RX_PCM_CONF_W::new(self, 10) + } + #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for received data."] + #[inline(always)] + #[must_use] + pub fn rx_pcm_bypass(&mut self) -> RX_PCM_BYPASS_W { + RX_PCM_BYPASS_W::new(self, 12) + } + #[doc = "Bits 13:14 - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."] + #[inline(always)] + #[must_use] + pub fn rx_stop_mode(&mut self) -> RX_STOP_MODE_W { + RX_STOP_MODE_W::new(self, 13) + } + #[doc = "Bit 15 - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."] + #[inline(always)] + #[must_use] + pub fn rx_left_align(&mut self) -> RX_LEFT_ALIGN_W { + RX_LEFT_ALIGN_W::new(self, 15) + } + #[doc = "Bit 16 - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."] + #[inline(always)] + #[must_use] + pub fn rx_24_fill_en(&mut self) -> RX_24_FILL_EN_W { + RX_24_FILL_EN_W::new(self, 16) + } + #[doc = "Bit 17 - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."] + #[inline(always)] + #[must_use] + pub fn rx_ws_idle_pol(&mut self) -> RX_WS_IDLE_POL_W { + RX_WS_IDLE_POL_W::new(self, 17) + } + #[doc = "Bit 18 - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."] + #[inline(always)] + #[must_use] + pub fn rx_bit_order(&mut self) -> RX_BIT_ORDER_W { + RX_BIT_ORDER_W::new(self, 18) + } + #[doc = "Bit 19 - 1: Enable I2S TDM Rx mode . 0: Disable."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_en(&mut self) -> RX_TDM_EN_W { + RX_TDM_EN_W::new(self, 19) + } + #[doc = "Bit 20 - 1: Enable I2S PDM Rx mode . 0: Disable."] + #[inline(always)] + #[must_use] + pub fn rx_pdm_en(&mut self) -> RX_PDM_EN_W { + RX_PDM_EN_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S RX configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CONF_SPEC; +impl crate::RegisterSpec for RX_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_conf::R`](R) reader structure"] +impl crate::Readable for RX_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_conf::W`](W) writer structure"] +impl crate::Writable for RX_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CONF to value 0x9600"] +impl crate::Resettable for RX_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x9600; +} diff --git a/esp32p4/src/lp_i2s0/rx_conf1.rs b/esp32p4/src/lp_i2s0/rx_conf1.rs new file mode 100644 index 0000000000..6a50670a51 --- /dev/null +++ b/esp32p4/src/lp_i2s0/rx_conf1.rs @@ -0,0 +1,161 @@ +#[doc = "Register `RX_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `RX_TDM_WS_WIDTH` reader - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"] +pub type RX_TDM_WS_WIDTH_R = crate::FieldReader; +#[doc = "Field `RX_TDM_WS_WIDTH` writer - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"] +pub type RX_TDM_WS_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `RX_BCK_DIV_NUM` reader - Bit clock configuration bits in receiver mode."] +pub type RX_BCK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `RX_BCK_DIV_NUM` writer - Bit clock configuration bits in receiver mode."] +pub type RX_BCK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `RX_BITS_MOD` reader - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] +pub type RX_BITS_MOD_R = crate::FieldReader; +#[doc = "Field `RX_BITS_MOD` writer - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] +pub type RX_BITS_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `RX_HALF_SAMPLE_BITS` reader - I2S Rx half sample bits -1."] +pub type RX_HALF_SAMPLE_BITS_R = crate::FieldReader; +#[doc = "Field `RX_HALF_SAMPLE_BITS` writer - I2S Rx half sample bits -1."] +pub type RX_HALF_SAMPLE_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `RX_TDM_CHAN_BITS` reader - The Rx bit number for each channel minus 1in TDM mode."] +pub type RX_TDM_CHAN_BITS_R = crate::FieldReader; +#[doc = "Field `RX_TDM_CHAN_BITS` writer - The Rx bit number for each channel minus 1in TDM mode."] +pub type RX_TDM_CHAN_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `RX_MSB_SHIFT` reader - Set this bit to enable receiver in Phillips standard mode"] +pub type RX_MSB_SHIFT_R = crate::BitReader; +#[doc = "Field `RX_MSB_SHIFT` writer - Set this bit to enable receiver in Phillips standard mode"] +pub type RX_MSB_SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"] + #[inline(always)] + pub fn rx_tdm_ws_width(&self) -> RX_TDM_WS_WIDTH_R { + RX_TDM_WS_WIDTH_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:12 - Bit clock configuration bits in receiver mode."] + #[inline(always)] + pub fn rx_bck_div_num(&self) -> RX_BCK_DIV_NUM_R { + RX_BCK_DIV_NUM_R::new(((self.bits >> 7) & 0x3f) as u8) + } + #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] + #[inline(always)] + pub fn rx_bits_mod(&self) -> RX_BITS_MOD_R { + RX_BITS_MOD_R::new(((self.bits >> 13) & 0x1f) as u8) + } + #[doc = "Bits 18:23 - I2S Rx half sample bits -1."] + #[inline(always)] + pub fn rx_half_sample_bits(&self) -> RX_HALF_SAMPLE_BITS_R { + RX_HALF_SAMPLE_BITS_R::new(((self.bits >> 18) & 0x3f) as u8) + } + #[doc = "Bits 24:28 - The Rx bit number for each channel minus 1in TDM mode."] + #[inline(always)] + pub fn rx_tdm_chan_bits(&self) -> RX_TDM_CHAN_BITS_R { + RX_TDM_CHAN_BITS_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bit 29 - Set this bit to enable receiver in Phillips standard mode"] + #[inline(always)] + pub fn rx_msb_shift(&self) -> RX_MSB_SHIFT_R { + RX_MSB_SHIFT_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CONF1") + .field( + "rx_tdm_ws_width", + &format_args!("{}", self.rx_tdm_ws_width().bits()), + ) + .field( + "rx_bck_div_num", + &format_args!("{}", self.rx_bck_div_num().bits()), + ) + .field( + "rx_bits_mod", + &format_args!("{}", self.rx_bits_mod().bits()), + ) + .field( + "rx_half_sample_bits", + &format_args!("{}", self.rx_half_sample_bits().bits()), + ) + .field( + "rx_tdm_chan_bits", + &format_args!("{}", self.rx_tdm_chan_bits().bits()), + ) + .field( + "rx_msb_shift", + &format_args!("{}", self.rx_msb_shift().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"] + #[inline(always)] + #[must_use] + pub fn rx_tdm_ws_width(&mut self) -> RX_TDM_WS_WIDTH_W { + RX_TDM_WS_WIDTH_W::new(self, 0) + } + #[doc = "Bits 7:12 - Bit clock configuration bits in receiver mode."] + #[inline(always)] + #[must_use] + pub fn rx_bck_div_num(&mut self) -> RX_BCK_DIV_NUM_W { + RX_BCK_DIV_NUM_W::new(self, 7) + } + #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."] + #[inline(always)] + #[must_use] + pub fn rx_bits_mod(&mut self) -> RX_BITS_MOD_W { + RX_BITS_MOD_W::new(self, 13) + } + #[doc = "Bits 18:23 - I2S Rx half sample bits -1."] + #[inline(always)] + #[must_use] + pub fn rx_half_sample_bits(&mut self) -> RX_HALF_SAMPLE_BITS_W { + RX_HALF_SAMPLE_BITS_W::new(self, 18) + } + #[doc = "Bits 24:28 - The Rx bit number for each channel minus 1in TDM mode."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_chan_bits(&mut self) -> RX_TDM_CHAN_BITS_W { + RX_TDM_CHAN_BITS_W::new(self, 24) + } + #[doc = "Bit 29 - Set this bit to enable receiver in Phillips standard mode"] + #[inline(always)] + #[must_use] + pub fn rx_msb_shift(&mut self) -> RX_MSB_SHIFT_W { + RX_MSB_SHIFT_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S RX configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CONF1_SPEC; +impl crate::RegisterSpec for RX_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_conf1::R`](R) reader structure"] +impl crate::Readable for RX_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_conf1::W`](W) writer structure"] +impl crate::Writable for RX_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CONF1 to value 0x2f3d_e300"] +impl crate::Resettable for RX_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x2f3d_e300; +} diff --git a/esp32p4/src/lp_i2s0/rx_mem_conf.rs b/esp32p4/src/lp_i2s0/rx_mem_conf.rs new file mode 100644 index 0000000000..ebf07f4974 --- /dev/null +++ b/esp32p4/src/lp_i2s0/rx_mem_conf.rs @@ -0,0 +1,77 @@ +#[doc = "Register `RX_MEM_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `RX_MEM_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `RX_MEM_FIFO_CNT` reader - The number of data in the rx mem"] +pub type RX_MEM_FIFO_CNT_R = crate::FieldReader; +#[doc = "Field `RX_MEM_THRESHOLD` reader - I2S rx mem will trigger an interrupt when the data in the mem is over(not including equal) reg_rx_mem_threshold"] +pub type RX_MEM_THRESHOLD_R = crate::FieldReader; +#[doc = "Field `RX_MEM_THRESHOLD` writer - I2S rx mem will trigger an interrupt when the data in the mem is over(not including equal) reg_rx_mem_threshold"] +pub type RX_MEM_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:8 - The number of data in the rx mem"] + #[inline(always)] + pub fn rx_mem_fifo_cnt(&self) -> RX_MEM_FIFO_CNT_R { + RX_MEM_FIFO_CNT_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:16 - I2S rx mem will trigger an interrupt when the data in the mem is over(not including equal) reg_rx_mem_threshold"] + #[inline(always)] + pub fn rx_mem_threshold(&self) -> RX_MEM_THRESHOLD_R { + RX_MEM_THRESHOLD_R::new(((self.bits >> 9) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_MEM_CONF") + .field( + "rx_mem_fifo_cnt", + &format_args!("{}", self.rx_mem_fifo_cnt().bits()), + ) + .field( + "rx_mem_threshold", + &format_args!("{}", self.rx_mem_threshold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 9:16 - I2S rx mem will trigger an interrupt when the data in the mem is over(not including equal) reg_rx_mem_threshold"] + #[inline(always)] + #[must_use] + pub fn rx_mem_threshold(&mut self) -> RX_MEM_THRESHOLD_W { + RX_MEM_THRESHOLD_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_mem_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_mem_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_MEM_CONF_SPEC; +impl crate::RegisterSpec for RX_MEM_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_mem_conf::R`](R) reader structure"] +impl crate::Readable for RX_MEM_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_mem_conf::W`](W) writer structure"] +impl crate::Writable for RX_MEM_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_MEM_CONF to value 0x7e00"] +impl crate::Resettable for RX_MEM_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x7e00; +} diff --git a/esp32p4/src/lp_i2s0/rx_pdm_conf.rs b/esp32p4/src/lp_i2s0/rx_pdm_conf.rs new file mode 100644 index 0000000000..f7b8fa06fb --- /dev/null +++ b/esp32p4/src/lp_i2s0/rx_pdm_conf.rs @@ -0,0 +1,161 @@ +#[doc = "Register `RX_PDM_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `RX_PDM_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `RX_PDM2PCM_EN` reader - 1: Enable PDM2PCM RX mode. 0: DIsable."] +pub type RX_PDM2PCM_EN_R = crate::BitReader; +#[doc = "Field `RX_PDM2PCM_EN` writer - 1: Enable PDM2PCM RX mode. 0: DIsable."] +pub type RX_PDM2PCM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PDM_SINC_DSR_16_EN` reader - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."] +pub type RX_PDM_SINC_DSR_16_EN_R = crate::BitReader; +#[doc = "Field `RX_PDM_SINC_DSR_16_EN` writer - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."] +pub type RX_PDM_SINC_DSR_16_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PDM2PCM_AMPLIFY_NUM` reader - Configure PDM RX amplify number."] +pub type RX_PDM2PCM_AMPLIFY_NUM_R = crate::FieldReader; +#[doc = "Field `RX_PDM2PCM_AMPLIFY_NUM` writer - Configure PDM RX amplify number."] +pub type RX_PDM2PCM_AMPLIFY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RX_PDM_HP_BYPASS` reader - I2S PDM RX bypass hp filter or not."] +pub type RX_PDM_HP_BYPASS_R = crate::BitReader; +#[doc = "Field `RX_PDM_HP_BYPASS` writer - I2S PDM RX bypass hp filter or not."] +pub type RX_PDM_HP_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_IIR_HP_MULT12_5` reader - The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5\\[2:0\\])"] +pub type RX_IIR_HP_MULT12_5_R = crate::FieldReader; +#[doc = "Field `RX_IIR_HP_MULT12_5` writer - The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5\\[2:0\\])"] +pub type RX_IIR_HP_MULT12_5_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `RX_IIR_HP_MULT12_0` reader - The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0\\[2:0\\])"] +pub type RX_IIR_HP_MULT12_0_R = crate::FieldReader; +#[doc = "Field `RX_IIR_HP_MULT12_0` writer - The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0\\[2:0\\])"] +pub type RX_IIR_HP_MULT12_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 19 - 1: Enable PDM2PCM RX mode. 0: DIsable."] + #[inline(always)] + pub fn rx_pdm2pcm_en(&self) -> RX_PDM2PCM_EN_R { + RX_PDM2PCM_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."] + #[inline(always)] + pub fn rx_pdm_sinc_dsr_16_en(&self) -> RX_PDM_SINC_DSR_16_EN_R { + RX_PDM_SINC_DSR_16_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:24 - Configure PDM RX amplify number."] + #[inline(always)] + pub fn rx_pdm2pcm_amplify_num(&self) -> RX_PDM2PCM_AMPLIFY_NUM_R { + RX_PDM2PCM_AMPLIFY_NUM_R::new(((self.bits >> 21) & 0x0f) as u8) + } + #[doc = "Bit 25 - I2S PDM RX bypass hp filter or not."] + #[inline(always)] + pub fn rx_pdm_hp_bypass(&self) -> RX_PDM_HP_BYPASS_R { + RX_PDM_HP_BYPASS_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 26:28 - The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5\\[2:0\\])"] + #[inline(always)] + pub fn rx_iir_hp_mult12_5(&self) -> RX_IIR_HP_MULT12_5_R { + RX_IIR_HP_MULT12_5_R::new(((self.bits >> 26) & 7) as u8) + } + #[doc = "Bits 29:31 - The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0\\[2:0\\])"] + #[inline(always)] + pub fn rx_iir_hp_mult12_0(&self) -> RX_IIR_HP_MULT12_0_R { + RX_IIR_HP_MULT12_0_R::new(((self.bits >> 29) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_PDM_CONF") + .field( + "rx_pdm2pcm_en", + &format_args!("{}", self.rx_pdm2pcm_en().bit()), + ) + .field( + "rx_pdm_sinc_dsr_16_en", + &format_args!("{}", self.rx_pdm_sinc_dsr_16_en().bit()), + ) + .field( + "rx_pdm2pcm_amplify_num", + &format_args!("{}", self.rx_pdm2pcm_amplify_num().bits()), + ) + .field( + "rx_pdm_hp_bypass", + &format_args!("{}", self.rx_pdm_hp_bypass().bit()), + ) + .field( + "rx_iir_hp_mult12_5", + &format_args!("{}", self.rx_iir_hp_mult12_5().bits()), + ) + .field( + "rx_iir_hp_mult12_0", + &format_args!("{}", self.rx_iir_hp_mult12_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 19 - 1: Enable PDM2PCM RX mode. 0: DIsable."] + #[inline(always)] + #[must_use] + pub fn rx_pdm2pcm_en(&mut self) -> RX_PDM2PCM_EN_W { + RX_PDM2PCM_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."] + #[inline(always)] + #[must_use] + pub fn rx_pdm_sinc_dsr_16_en(&mut self) -> RX_PDM_SINC_DSR_16_EN_W { + RX_PDM_SINC_DSR_16_EN_W::new(self, 20) + } + #[doc = "Bits 21:24 - Configure PDM RX amplify number."] + #[inline(always)] + #[must_use] + pub fn rx_pdm2pcm_amplify_num(&mut self) -> RX_PDM2PCM_AMPLIFY_NUM_W { + RX_PDM2PCM_AMPLIFY_NUM_W::new(self, 21) + } + #[doc = "Bit 25 - I2S PDM RX bypass hp filter or not."] + #[inline(always)] + #[must_use] + pub fn rx_pdm_hp_bypass(&mut self) -> RX_PDM_HP_BYPASS_W { + RX_PDM_HP_BYPASS_W::new(self, 25) + } + #[doc = "Bits 26:28 - The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5\\[2:0\\])"] + #[inline(always)] + #[must_use] + pub fn rx_iir_hp_mult12_5(&mut self) -> RX_IIR_HP_MULT12_5_W { + RX_IIR_HP_MULT12_5_W::new(self, 26) + } + #[doc = "Bits 29:31 - The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0\\[2:0\\])"] + #[inline(always)] + #[must_use] + pub fn rx_iir_hp_mult12_0(&mut self) -> RX_IIR_HP_MULT12_0_W { + RX_IIR_HP_MULT12_0_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S RX configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_pdm_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_pdm_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_PDM_CONF_SPEC; +impl crate::RegisterSpec for RX_PDM_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_pdm_conf::R`](R) reader structure"] +impl crate::Readable for RX_PDM_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_pdm_conf::W`](W) writer structure"] +impl crate::Writable for RX_PDM_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_PDM_CONF to value 0xf820_0000"] +impl crate::Resettable for RX_PDM_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0xf820_0000; +} diff --git a/esp32p4/src/lp_i2s0/rx_tdm_ctrl.rs b/esp32p4/src/lp_i2s0/rx_tdm_ctrl.rs new file mode 100644 index 0000000000..ea8ca2eb17 --- /dev/null +++ b/esp32p4/src/lp_i2s0/rx_tdm_ctrl.rs @@ -0,0 +1,104 @@ +#[doc = "Register `RX_TDM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `RX_TDM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `RX_TDM_PDM_CHAN0_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN0_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_PDM_CHAN0_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_PDM_CHAN1_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN1_EN_R = crate::BitReader; +#[doc = "Field `RX_TDM_PDM_CHAN1_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."] +pub type RX_TDM_PDM_CHAN1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TDM_TOT_CHAN_NUM` reader - The total channel number of I2S TX TDM mode."] +pub type RX_TDM_TOT_CHAN_NUM_R = crate::FieldReader; +#[doc = "Field `RX_TDM_TOT_CHAN_NUM` writer - The total channel number of I2S TX TDM mode."] +pub type RX_TDM_TOT_CHAN_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_pdm_chan0_en(&self) -> RX_TDM_PDM_CHAN0_EN_R { + RX_TDM_PDM_CHAN0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."] + #[inline(always)] + pub fn rx_tdm_pdm_chan1_en(&self) -> RX_TDM_PDM_CHAN1_EN_R { + RX_TDM_PDM_CHAN1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."] + #[inline(always)] + pub fn rx_tdm_tot_chan_num(&self) -> RX_TDM_TOT_CHAN_NUM_R { + RX_TDM_TOT_CHAN_NUM_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_TDM_CTRL") + .field( + "rx_tdm_pdm_chan0_en", + &format_args!("{}", self.rx_tdm_pdm_chan0_en().bit()), + ) + .field( + "rx_tdm_pdm_chan1_en", + &format_args!("{}", self.rx_tdm_pdm_chan1_en().bit()), + ) + .field( + "rx_tdm_tot_chan_num", + &format_args!("{}", self.rx_tdm_tot_chan_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_pdm_chan0_en(&mut self) -> RX_TDM_PDM_CHAN0_EN_W { + RX_TDM_PDM_CHAN0_EN_W::new(self, 0) + } + #[doc = "Bit 1 - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_pdm_chan1_en(&mut self) -> RX_TDM_PDM_CHAN1_EN_W { + RX_TDM_PDM_CHAN1_EN_W::new(self, 1) + } + #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."] + #[inline(always)] + #[must_use] + pub fn rx_tdm_tot_chan_num(&mut self) -> RX_TDM_TOT_CHAN_NUM_W { + RX_TDM_TOT_CHAN_NUM_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S TX TDM mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_tdm_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_tdm_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_TDM_CTRL_SPEC; +impl crate::RegisterSpec for RX_TDM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_tdm_ctrl::R`](R) reader structure"] +impl crate::Readable for RX_TDM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_tdm_ctrl::W`](W) writer structure"] +impl crate::Writable for RX_TDM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_TDM_CTRL to value 0x03"] +impl crate::Resettable for RX_TDM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/lp_i2s0/rx_timing.rs b/esp32p4/src/lp_i2s0/rx_timing.rs new file mode 100644 index 0000000000..f887032a7e --- /dev/null +++ b/esp32p4/src/lp_i2s0/rx_timing.rs @@ -0,0 +1,142 @@ +#[doc = "Register `RX_TIMING` reader"] +pub type R = crate::R; +#[doc = "Register `RX_TIMING` writer"] +pub type W = crate::W; +#[doc = "Field `RX_SD_IN_DM` reader - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_SD_IN_DM_R = crate::FieldReader; +#[doc = "Field `RX_SD_IN_DM` writer - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_SD_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_WS_OUT_DM` reader - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_WS_OUT_DM_R = crate::FieldReader; +#[doc = "Field `RX_WS_OUT_DM` writer - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_WS_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_BCK_OUT_DM` reader - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_BCK_OUT_DM_R = crate::FieldReader; +#[doc = "Field `RX_BCK_OUT_DM` writer - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_BCK_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_WS_IN_DM` reader - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_WS_IN_DM_R = crate::FieldReader; +#[doc = "Field `RX_WS_IN_DM` writer - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_WS_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RX_BCK_IN_DM` reader - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_BCK_IN_DM_R = crate::FieldReader; +#[doc = "Field `RX_BCK_IN_DM` writer - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] +pub type RX_BCK_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_sd_in_dm(&self) -> RX_SD_IN_DM_R { + RX_SD_IN_DM_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_ws_out_dm(&self) -> RX_WS_OUT_DM_R { + RX_WS_OUT_DM_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_bck_out_dm(&self) -> RX_BCK_OUT_DM_R { + RX_BCK_OUT_DM_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_ws_in_dm(&self) -> RX_WS_IN_DM_R { + RX_WS_IN_DM_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + pub fn rx_bck_in_dm(&self) -> RX_BCK_IN_DM_R { + RX_BCK_IN_DM_R::new(((self.bits >> 28) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_TIMING") + .field( + "rx_sd_in_dm", + &format_args!("{}", self.rx_sd_in_dm().bits()), + ) + .field( + "rx_ws_out_dm", + &format_args!("{}", self.rx_ws_out_dm().bits()), + ) + .field( + "rx_bck_out_dm", + &format_args!("{}", self.rx_bck_out_dm().bits()), + ) + .field( + "rx_ws_in_dm", + &format_args!("{}", self.rx_ws_in_dm().bits()), + ) + .field( + "rx_bck_in_dm", + &format_args!("{}", self.rx_bck_in_dm().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_sd_in_dm(&mut self) -> RX_SD_IN_DM_W { + RX_SD_IN_DM_W::new(self, 0) + } + #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_ws_out_dm(&mut self) -> RX_WS_OUT_DM_W { + RX_WS_OUT_DM_W::new(self, 16) + } + #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_bck_out_dm(&mut self) -> RX_BCK_OUT_DM_W { + RX_BCK_OUT_DM_W::new(self, 20) + } + #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_ws_in_dm(&mut self) -> RX_WS_IN_DM_W { + RX_WS_IN_DM_W::new(self, 24) + } + #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."] + #[inline(always)] + #[must_use] + pub fn rx_bck_in_dm(&mut self) -> RX_BCK_IN_DM_W { + RX_BCK_IN_DM_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S RX timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_timing::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_timing::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_TIMING_SPEC; +impl crate::RegisterSpec for RX_TIMING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_timing::R`](R) reader structure"] +impl crate::Readable for RX_TIMING_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_timing::W`](W) writer structure"] +impl crate::Writable for RX_TIMING_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_TIMING to value 0"] +impl crate::Resettable for RX_TIMING_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/rxeof_num.rs b/esp32p4/src/lp_i2s0/rxeof_num.rs new file mode 100644 index 0000000000..61325d1eb6 --- /dev/null +++ b/esp32p4/src/lp_i2s0/rxeof_num.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RXEOF_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `RXEOF_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `RX_EOF_NUM` reader - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."] +pub type RX_EOF_NUM_R = crate::FieldReader; +#[doc = "Field `RX_EOF_NUM` writer - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."] +pub type RX_EOF_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."] + #[inline(always)] + pub fn rx_eof_num(&self) -> RX_EOF_NUM_R { + RX_EOF_NUM_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RXEOF_NUM") + .field("rx_eof_num", &format_args!("{}", self.rx_eof_num().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."] + #[inline(always)] + #[must_use] + pub fn rx_eof_num(&mut self) -> RX_EOF_NUM_W { + RX_EOF_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S RX data number control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxeof_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxeof_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RXEOF_NUM_SPEC; +impl crate::RegisterSpec for RXEOF_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxeof_num::R`](R) reader structure"] +impl crate::Readable for RXEOF_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxeof_num::W`](W) writer structure"] +impl crate::Writable for RXEOF_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RXEOF_NUM to value 0x40"] +impl crate::Resettable for RXEOF_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0x40; +} diff --git a/esp32p4/src/lp_i2s0/vad_conf.rs b/esp32p4/src/lp_i2s0/vad_conf.rs new file mode 100644 index 0000000000..8671e3a251 --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_conf.rs @@ -0,0 +1,79 @@ +#[doc = "Register `VAD_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `VAD_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `VAD_EN` reader - VAD enable register"] +pub type VAD_EN_R = crate::BitReader; +#[doc = "Field `VAD_EN` writer - VAD enable register"] +pub type VAD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VAD_RESET` writer - VAD reset register"] +pub type VAD_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VAD_FORCE_START` writer - VAD force start register."] +pub type VAD_FORCE_START_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - VAD enable register"] + #[inline(always)] + pub fn vad_en(&self) -> VAD_EN_R { + VAD_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_CONF") + .field("vad_en", &format_args!("{}", self.vad_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - VAD enable register"] + #[inline(always)] + #[must_use] + pub fn vad_en(&mut self) -> VAD_EN_W { + VAD_EN_W::new(self, 0) + } + #[doc = "Bit 1 - VAD reset register"] + #[inline(always)] + #[must_use] + pub fn vad_reset(&mut self) -> VAD_RESET_W { + VAD_RESET_W::new(self, 1) + } + #[doc = "Bit 2 - VAD force start register."] + #[inline(always)] + #[must_use] + pub fn vad_force_start(&mut self) -> VAD_FORCE_START_W { + VAD_FORCE_START_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S VAD Configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_CONF_SPEC; +impl crate::RegisterSpec for VAD_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_conf::R`](R) reader structure"] +impl crate::Readable for VAD_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vad_conf::W`](W) writer structure"] +impl crate::Writable for VAD_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VAD_CONF to value 0"] +impl crate::Resettable for VAD_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/vad_ob0.rs b/esp32p4/src/lp_i2s0/vad_ob0.rs new file mode 100644 index 0000000000..4bfb89a462 --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_ob0.rs @@ -0,0 +1,61 @@ +#[doc = "Register `VAD_OB0` reader"] +pub type R = crate::R; +#[doc = "Field `SPEECH_COUNT_OB` reader - Reg silent count observe"] +pub type SPEECH_COUNT_OB_R = crate::FieldReader; +#[doc = "Field `SILENT_COUNT_OB` reader - Reg speech count observe"] +pub type SILENT_COUNT_OB_R = crate::FieldReader; +#[doc = "Field `MAX_SIGNAL0_OB` reader - Reg max signal0 observe"] +pub type MAX_SIGNAL0_OB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Reg silent count observe"] + #[inline(always)] + pub fn speech_count_ob(&self) -> SPEECH_COUNT_OB_R { + SPEECH_COUNT_OB_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reg speech count observe"] + #[inline(always)] + pub fn silent_count_ob(&self) -> SILENT_COUNT_OB_R { + SILENT_COUNT_OB_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:31 - Reg max signal0 observe"] + #[inline(always)] + pub fn max_signal0_ob(&self) -> MAX_SIGNAL0_OB_R { + MAX_SIGNAL0_OB_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_OB0") + .field( + "speech_count_ob", + &format_args!("{}", self.speech_count_ob().bits()), + ) + .field( + "silent_count_ob", + &format_args!("{}", self.silent_count_ob().bits()), + ) + .field( + "max_signal0_ob", + &format_args!("{}", self.max_signal0_ob().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_OB0_SPEC; +impl crate::RegisterSpec for VAD_OB0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_ob0::R`](R) reader structure"] +impl crate::Readable for VAD_OB0_SPEC {} +#[doc = "`reset()` method sets VAD_OB0 to value 0"] +impl crate::Resettable for VAD_OB0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/vad_ob1.rs b/esp32p4/src/lp_i2s0/vad_ob1.rs new file mode 100644 index 0000000000..df26293a42 --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_ob1.rs @@ -0,0 +1,50 @@ +#[doc = "Register `VAD_OB1` reader"] +pub type R = crate::R; +#[doc = "Field `MAX_SIGNAL1_OB` reader - Reg max signal1 observe"] +pub type MAX_SIGNAL1_OB_R = crate::FieldReader; +#[doc = "Field `MAX_SIGNAL2_OB` reader - Reg max signal2 observe"] +pub type MAX_SIGNAL2_OB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Reg max signal1 observe"] + #[inline(always)] + pub fn max_signal1_ob(&self) -> MAX_SIGNAL1_OB_R { + MAX_SIGNAL1_OB_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Reg max signal2 observe"] + #[inline(always)] + pub fn max_signal2_ob(&self) -> MAX_SIGNAL2_OB_R { + MAX_SIGNAL2_OB_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_OB1") + .field( + "max_signal1_ob", + &format_args!("{}", self.max_signal1_ob().bits()), + ) + .field( + "max_signal2_ob", + &format_args!("{}", self.max_signal2_ob().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_OB1_SPEC; +impl crate::RegisterSpec for VAD_OB1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_ob1::R`](R) reader structure"] +impl crate::Readable for VAD_OB1_SPEC {} +#[doc = "`reset()` method sets VAD_OB1 to value 0"] +impl crate::Resettable for VAD_OB1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/vad_ob2.rs b/esp32p4/src/lp_i2s0/vad_ob2.rs new file mode 100644 index 0000000000..bc58efc96f --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_ob2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VAD_OB2` reader"] +pub type R = crate::R; +#[doc = "Field `NOISE_AMP_OB` reader - Reg noise_amp observe signal"] +pub type NOISE_AMP_OB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Reg noise_amp observe signal"] + #[inline(always)] + pub fn noise_amp_ob(&self) -> NOISE_AMP_OB_R { + NOISE_AMP_OB_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_OB2") + .field( + "noise_amp_ob", + &format_args!("{}", self.noise_amp_ob().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_OB2_SPEC; +impl crate::RegisterSpec for VAD_OB2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_ob2::R`](R) reader structure"] +impl crate::Readable for VAD_OB2_SPEC {} +#[doc = "`reset()` method sets VAD_OB2 to value 0"] +impl crate::Resettable for VAD_OB2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/vad_ob3.rs b/esp32p4/src/lp_i2s0/vad_ob3.rs new file mode 100644 index 0000000000..ca3eca0ab6 --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_ob3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VAD_OB3` reader"] +pub type R = crate::R; +#[doc = "Field `NOISE_MEAN_OB` reader - Reg noise_mean observe signal"] +pub type NOISE_MEAN_OB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Reg noise_mean observe signal"] + #[inline(always)] + pub fn noise_mean_ob(&self) -> NOISE_MEAN_OB_R { + NOISE_MEAN_OB_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_OB3") + .field( + "noise_mean_ob", + &format_args!("{}", self.noise_mean_ob().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_OB3_SPEC; +impl crate::RegisterSpec for VAD_OB3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_ob3::R`](R) reader structure"] +impl crate::Readable for VAD_OB3_SPEC {} +#[doc = "`reset()` method sets VAD_OB3 to value 0"] +impl crate::Resettable for VAD_OB3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/vad_ob4.rs b/esp32p4/src/lp_i2s0/vad_ob4.rs new file mode 100644 index 0000000000..81a7e4c45e --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_ob4.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VAD_OB4` reader"] +pub type R = crate::R; +#[doc = "Field `NOISE_STD_OB` reader - Reg noise_std observe signal"] +pub type NOISE_STD_OB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Reg noise_std observe signal"] + #[inline(always)] + pub fn noise_std_ob(&self) -> NOISE_STD_OB_R { + NOISE_STD_OB_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_OB4") + .field( + "noise_std_ob", + &format_args!("{}", self.noise_std_ob().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_OB4_SPEC; +impl crate::RegisterSpec for VAD_OB4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_ob4::R`](R) reader structure"] +impl crate::Readable for VAD_OB4_SPEC {} +#[doc = "`reset()` method sets VAD_OB4 to value 0"] +impl crate::Resettable for VAD_OB4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/vad_ob5.rs b/esp32p4/src/lp_i2s0/vad_ob5.rs new file mode 100644 index 0000000000..e1befdb48c --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_ob5.rs @@ -0,0 +1,36 @@ +#[doc = "Register `VAD_OB5` reader"] +pub type R = crate::R; +#[doc = "Field `OFFSET_OB` reader - Reg offset observe signal"] +pub type OFFSET_OB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Reg offset observe signal"] + #[inline(always)] + pub fn offset_ob(&self) -> OFFSET_OB_R { + OFFSET_OB_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_OB5") + .field("offset_ob", &format_args!("{}", self.offset_ob().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_OB5_SPEC; +impl crate::RegisterSpec for VAD_OB5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_ob5::R`](R) reader structure"] +impl crate::Readable for VAD_OB5_SPEC {} +#[doc = "`reset()` method sets VAD_OB5 to value 0"] +impl crate::Resettable for VAD_OB5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/vad_ob6.rs b/esp32p4/src/lp_i2s0/vad_ob6.rs new file mode 100644 index 0000000000..63c45f362e --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_ob6.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VAD_OB6` reader"] +pub type R = crate::R; +#[doc = "Field `THRESHOLD_OB` reader - Reg threshold observe signal"] +pub type THRESHOLD_OB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Reg threshold observe signal"] + #[inline(always)] + pub fn threshold_ob(&self) -> THRESHOLD_OB_R { + THRESHOLD_OB_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_OB6") + .field( + "threshold_ob", + &format_args!("{}", self.threshold_ob().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_OB6_SPEC; +impl crate::RegisterSpec for VAD_OB6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_ob6::R`](R) reader structure"] +impl crate::Readable for VAD_OB6_SPEC {} +#[doc = "`reset()` method sets VAD_OB6 to value 0"] +impl crate::Resettable for VAD_OB6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/vad_ob7.rs b/esp32p4/src/lp_i2s0/vad_ob7.rs new file mode 100644 index 0000000000..d8029c347e --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_ob7.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VAD_OB7` reader"] +pub type R = crate::R; +#[doc = "Field `ENERGY_LOW_OB` reader - Reg energy bit 31~0 observe signal"] +pub type ENERGY_LOW_OB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Reg energy bit 31~0 observe signal"] + #[inline(always)] + pub fn energy_low_ob(&self) -> ENERGY_LOW_OB_R { + ENERGY_LOW_OB_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_OB7") + .field( + "energy_low_ob", + &format_args!("{}", self.energy_low_ob().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_OB7_SPEC; +impl crate::RegisterSpec for VAD_OB7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_ob7::R`](R) reader structure"] +impl crate::Readable for VAD_OB7_SPEC {} +#[doc = "`reset()` method sets VAD_OB7 to value 0"] +impl crate::Resettable for VAD_OB7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/vad_ob8.rs b/esp32p4/src/lp_i2s0/vad_ob8.rs new file mode 100644 index 0000000000..389bff3cf8 --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_ob8.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VAD_OB8` reader"] +pub type R = crate::R; +#[doc = "Field `ENERGY_HIGH_OB` reader - Reg energy bit 63~32 observe signal"] +pub type ENERGY_HIGH_OB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Reg energy bit 63~32 observe signal"] + #[inline(always)] + pub fn energy_high_ob(&self) -> ENERGY_HIGH_OB_R { + ENERGY_HIGH_OB_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_OB8") + .field( + "energy_high_ob", + &format_args!("{}", self.energy_high_ob().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_OB8_SPEC; +impl crate::RegisterSpec for VAD_OB8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_ob8::R`](R) reader structure"] +impl crate::Readable for VAD_OB8_SPEC {} +#[doc = "`reset()` method sets VAD_OB8 to value 0"] +impl crate::Resettable for VAD_OB8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_i2s0/vad_param0.rs b/esp32p4/src/lp_i2s0/vad_param0.rs new file mode 100644 index 0000000000..c30b1659d3 --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_param0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `VAD_PARAM0` reader"] +pub type R = crate::R; +#[doc = "Register `VAD_PARAM0` writer"] +pub type W = crate::W; +#[doc = "Field `PARAM_MIN_ENERGY` reader - VAD parameter"] +pub type PARAM_MIN_ENERGY_R = crate::FieldReader; +#[doc = "Field `PARAM_MIN_ENERGY` writer - VAD parameter"] +pub type PARAM_MIN_ENERGY_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `PARAM_INIT_FRAME_NUM` reader - VAD parameter"] +pub type PARAM_INIT_FRAME_NUM_R = crate::FieldReader; +#[doc = "Field `PARAM_INIT_FRAME_NUM` writer - VAD parameter"] +pub type PARAM_INIT_FRAME_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + pub fn param_min_energy(&self) -> PARAM_MIN_ENERGY_R { + PARAM_MIN_ENERGY_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:24 - VAD parameter"] + #[inline(always)] + pub fn param_init_frame_num(&self) -> PARAM_INIT_FRAME_NUM_R { + PARAM_INIT_FRAME_NUM_R::new(((self.bits >> 16) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_PARAM0") + .field( + "param_min_energy", + &format_args!("{}", self.param_min_energy().bits()), + ) + .field( + "param_init_frame_num", + &format_args!("{}", self.param_init_frame_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_min_energy(&mut self) -> PARAM_MIN_ENERGY_W { + PARAM_MIN_ENERGY_W::new(self, 0) + } + #[doc = "Bits 16:24 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_init_frame_num(&mut self) -> PARAM_INIT_FRAME_NUM_W { + PARAM_INIT_FRAME_NUM_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_PARAM0_SPEC; +impl crate::RegisterSpec for VAD_PARAM0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_param0::R`](R) reader structure"] +impl crate::Readable for VAD_PARAM0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vad_param0::W`](W) writer structure"] +impl crate::Writable for VAD_PARAM0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VAD_PARAM0 to value 0x00c8_1388"] +impl crate::Resettable for VAD_PARAM0_SPEC { + const RESET_VALUE: Self::Ux = 0x00c8_1388; +} diff --git a/esp32p4/src/lp_i2s0/vad_param1.rs b/esp32p4/src/lp_i2s0/vad_param1.rs new file mode 100644 index 0000000000..51dcb7aefa --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_param1.rs @@ -0,0 +1,161 @@ +#[doc = "Register `VAD_PARAM1` reader"] +pub type R = crate::R; +#[doc = "Register `VAD_PARAM1` writer"] +pub type W = crate::W; +#[doc = "Field `PARAM_MIN_SPEECH_COUNT` reader - VAD parameter"] +pub type PARAM_MIN_SPEECH_COUNT_R = crate::FieldReader; +#[doc = "Field `PARAM_MIN_SPEECH_COUNT` writer - VAD parameter"] +pub type PARAM_MIN_SPEECH_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PARAM_MAX_SPEECH_COUNT` reader - VAD parameter"] +pub type PARAM_MAX_SPEECH_COUNT_R = crate::FieldReader; +#[doc = "Field `PARAM_MAX_SPEECH_COUNT` writer - VAD parameter"] +pub type PARAM_MAX_SPEECH_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `PARAM_HANGOVER_SPEECH` reader - VAD parameter"] +pub type PARAM_HANGOVER_SPEECH_R = crate::FieldReader; +#[doc = "Field `PARAM_HANGOVER_SPEECH` writer - VAD parameter"] +pub type PARAM_HANGOVER_SPEECH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PARAM_HANGOVER_SILENT` reader - VAD parameter"] +pub type PARAM_HANGOVER_SILENT_R = crate::FieldReader; +#[doc = "Field `PARAM_HANGOVER_SILENT` writer - VAD parameter"] +pub type PARAM_HANGOVER_SILENT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PARAM_MAX_OFFSET` reader - VAD parameter"] +pub type PARAM_MAX_OFFSET_R = crate::FieldReader; +#[doc = "Field `PARAM_MAX_OFFSET` writer - VAD parameter"] +pub type PARAM_MAX_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `PARAM_SKIP_BAND_ENERGY` reader - Set 1 to skip band energy check."] +pub type PARAM_SKIP_BAND_ENERGY_R = crate::BitReader; +#[doc = "Field `PARAM_SKIP_BAND_ENERGY` writer - Set 1 to skip band energy check."] +pub type PARAM_SKIP_BAND_ENERGY_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - VAD parameter"] + #[inline(always)] + pub fn param_min_speech_count(&self) -> PARAM_MIN_SPEECH_COUNT_R { + PARAM_MIN_SPEECH_COUNT_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:10 - VAD parameter"] + #[inline(always)] + pub fn param_max_speech_count(&self) -> PARAM_MAX_SPEECH_COUNT_R { + PARAM_MAX_SPEECH_COUNT_R::new(((self.bits >> 4) & 0x7f) as u8) + } + #[doc = "Bits 11:15 - VAD parameter"] + #[inline(always)] + pub fn param_hangover_speech(&self) -> PARAM_HANGOVER_SPEECH_R { + PARAM_HANGOVER_SPEECH_R::new(((self.bits >> 11) & 0x1f) as u8) + } + #[doc = "Bits 16:23 - VAD parameter"] + #[inline(always)] + pub fn param_hangover_silent(&self) -> PARAM_HANGOVER_SILENT_R { + PARAM_HANGOVER_SILENT_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:30 - VAD parameter"] + #[inline(always)] + pub fn param_max_offset(&self) -> PARAM_MAX_OFFSET_R { + PARAM_MAX_OFFSET_R::new(((self.bits >> 24) & 0x7f) as u8) + } + #[doc = "Bit 31 - Set 1 to skip band energy check."] + #[inline(always)] + pub fn param_skip_band_energy(&self) -> PARAM_SKIP_BAND_ENERGY_R { + PARAM_SKIP_BAND_ENERGY_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_PARAM1") + .field( + "param_min_speech_count", + &format_args!("{}", self.param_min_speech_count().bits()), + ) + .field( + "param_max_speech_count", + &format_args!("{}", self.param_max_speech_count().bits()), + ) + .field( + "param_hangover_speech", + &format_args!("{}", self.param_hangover_speech().bits()), + ) + .field( + "param_hangover_silent", + &format_args!("{}", self.param_hangover_silent().bits()), + ) + .field( + "param_max_offset", + &format_args!("{}", self.param_max_offset().bits()), + ) + .field( + "param_skip_band_energy", + &format_args!("{}", self.param_skip_band_energy().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_min_speech_count(&mut self) -> PARAM_MIN_SPEECH_COUNT_W { + PARAM_MIN_SPEECH_COUNT_W::new(self, 0) + } + #[doc = "Bits 4:10 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_max_speech_count(&mut self) -> PARAM_MAX_SPEECH_COUNT_W { + PARAM_MAX_SPEECH_COUNT_W::new(self, 4) + } + #[doc = "Bits 11:15 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_hangover_speech(&mut self) -> PARAM_HANGOVER_SPEECH_W { + PARAM_HANGOVER_SPEECH_W::new(self, 11) + } + #[doc = "Bits 16:23 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_hangover_silent(&mut self) -> PARAM_HANGOVER_SILENT_W { + PARAM_HANGOVER_SILENT_W::new(self, 16) + } + #[doc = "Bits 24:30 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_max_offset(&mut self) -> PARAM_MAX_OFFSET_W { + PARAM_MAX_OFFSET_W::new(self, 24) + } + #[doc = "Bit 31 - Set 1 to skip band energy check."] + #[inline(always)] + #[must_use] + pub fn param_skip_band_energy(&mut self) -> PARAM_SKIP_BAND_ENERGY_W { + PARAM_SKIP_BAND_ENERGY_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_PARAM1_SPEC; +impl crate::RegisterSpec for VAD_PARAM1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_param1::R`](R) reader structure"] +impl crate::Readable for VAD_PARAM1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vad_param1::W`](W) writer structure"] +impl crate::Writable for VAD_PARAM1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VAD_PARAM1 to value 0x281e_1e43"] +impl crate::Resettable for VAD_PARAM1_SPEC { + const RESET_VALUE: Self::Ux = 0x281e_1e43; +} diff --git a/esp32p4/src/lp_i2s0/vad_param2.rs b/esp32p4/src/lp_i2s0/vad_param2.rs new file mode 100644 index 0000000000..eb92fc31ce --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_param2.rs @@ -0,0 +1,85 @@ +#[doc = "Register `VAD_PARAM2` reader"] +pub type R = crate::R; +#[doc = "Register `VAD_PARAM2` writer"] +pub type W = crate::W; +#[doc = "Field `PARAM_NOISE_AMP_DOWN` reader - VAD parameter"] +pub type PARAM_NOISE_AMP_DOWN_R = crate::FieldReader; +#[doc = "Field `PARAM_NOISE_AMP_DOWN` writer - VAD parameter"] +pub type PARAM_NOISE_AMP_DOWN_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `PARAM_NOISE_AMP_UP` reader - VAD parameter"] +pub type PARAM_NOISE_AMP_UP_R = crate::FieldReader; +#[doc = "Field `PARAM_NOISE_AMP_UP` writer - VAD parameter"] +pub type PARAM_NOISE_AMP_UP_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + pub fn param_noise_amp_down(&self) -> PARAM_NOISE_AMP_DOWN_R { + PARAM_NOISE_AMP_DOWN_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + pub fn param_noise_amp_up(&self) -> PARAM_NOISE_AMP_UP_R { + PARAM_NOISE_AMP_UP_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_PARAM2") + .field( + "param_noise_amp_down", + &format_args!("{}", self.param_noise_amp_down().bits()), + ) + .field( + "param_noise_amp_up", + &format_args!("{}", self.param_noise_amp_up().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_noise_amp_down(&mut self) -> PARAM_NOISE_AMP_DOWN_W { + PARAM_NOISE_AMP_DOWN_W::new(self, 0) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_noise_amp_up(&mut self) -> PARAM_NOISE_AMP_UP_W { + PARAM_NOISE_AMP_UP_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_PARAM2_SPEC; +impl crate::RegisterSpec for VAD_PARAM2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_param2::R`](R) reader structure"] +impl crate::Readable for VAD_PARAM2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vad_param2::W`](W) writer structure"] +impl crate::Writable for VAD_PARAM2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VAD_PARAM2 to value 0x7eb8_6666"] +impl crate::Resettable for VAD_PARAM2_SPEC { + const RESET_VALUE: Self::Ux = 0x7eb8_6666; +} diff --git a/esp32p4/src/lp_i2s0/vad_param3.rs b/esp32p4/src/lp_i2s0/vad_param3.rs new file mode 100644 index 0000000000..1c60a63790 --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_param3.rs @@ -0,0 +1,85 @@ +#[doc = "Register `VAD_PARAM3` reader"] +pub type R = crate::R; +#[doc = "Register `VAD_PARAM3` writer"] +pub type W = crate::W; +#[doc = "Field `PARAM_NOISE_SPE_UP0` reader - VAD parameter"] +pub type PARAM_NOISE_SPE_UP0_R = crate::FieldReader; +#[doc = "Field `PARAM_NOISE_SPE_UP0` writer - VAD parameter"] +pub type PARAM_NOISE_SPE_UP0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `PARAM_NOISE_SPE_UP1` reader - VAD parameter"] +pub type PARAM_NOISE_SPE_UP1_R = crate::FieldReader; +#[doc = "Field `PARAM_NOISE_SPE_UP1` writer - VAD parameter"] +pub type PARAM_NOISE_SPE_UP1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + pub fn param_noise_spe_up0(&self) -> PARAM_NOISE_SPE_UP0_R { + PARAM_NOISE_SPE_UP0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + pub fn param_noise_spe_up1(&self) -> PARAM_NOISE_SPE_UP1_R { + PARAM_NOISE_SPE_UP1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_PARAM3") + .field( + "param_noise_spe_up0", + &format_args!("{}", self.param_noise_spe_up0().bits()), + ) + .field( + "param_noise_spe_up1", + &format_args!("{}", self.param_noise_spe_up1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_noise_spe_up0(&mut self) -> PARAM_NOISE_SPE_UP0_W { + PARAM_NOISE_SPE_UP0_W::new(self, 0) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_noise_spe_up1(&mut self) -> PARAM_NOISE_SPE_UP1_W { + PARAM_NOISE_SPE_UP1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_PARAM3_SPEC; +impl crate::RegisterSpec for VAD_PARAM3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_param3::R`](R) reader structure"] +impl crate::Readable for VAD_PARAM3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vad_param3::W`](W) writer structure"] +impl crate::Writable for VAD_PARAM3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VAD_PARAM3 to value 0x7d71_7fdf"] +impl crate::Resettable for VAD_PARAM3_SPEC { + const RESET_VALUE: Self::Ux = 0x7d71_7fdf; +} diff --git a/esp32p4/src/lp_i2s0/vad_param4.rs b/esp32p4/src/lp_i2s0/vad_param4.rs new file mode 100644 index 0000000000..eb337906cf --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_param4.rs @@ -0,0 +1,85 @@ +#[doc = "Register `VAD_PARAM4` reader"] +pub type R = crate::R; +#[doc = "Register `VAD_PARAM4` writer"] +pub type W = crate::W; +#[doc = "Field `PARAM_NOISE_SPE_DOWN` reader - VAD parameter"] +pub type PARAM_NOISE_SPE_DOWN_R = crate::FieldReader; +#[doc = "Field `PARAM_NOISE_SPE_DOWN` writer - VAD parameter"] +pub type PARAM_NOISE_SPE_DOWN_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `PARAM_NOISE_MEAN_DOWN` reader - VAD parameter"] +pub type PARAM_NOISE_MEAN_DOWN_R = crate::FieldReader; +#[doc = "Field `PARAM_NOISE_MEAN_DOWN` writer - VAD parameter"] +pub type PARAM_NOISE_MEAN_DOWN_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + pub fn param_noise_spe_down(&self) -> PARAM_NOISE_SPE_DOWN_R { + PARAM_NOISE_SPE_DOWN_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + pub fn param_noise_mean_down(&self) -> PARAM_NOISE_MEAN_DOWN_R { + PARAM_NOISE_MEAN_DOWN_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_PARAM4") + .field( + "param_noise_spe_down", + &format_args!("{}", self.param_noise_spe_down().bits()), + ) + .field( + "param_noise_mean_down", + &format_args!("{}", self.param_noise_mean_down().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_noise_spe_down(&mut self) -> PARAM_NOISE_SPE_DOWN_W { + PARAM_NOISE_SPE_DOWN_W::new(self, 0) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_noise_mean_down(&mut self) -> PARAM_NOISE_MEAN_DOWN_W { + PARAM_NOISE_MEAN_DOWN_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_PARAM4_SPEC; +impl crate::RegisterSpec for VAD_PARAM4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_param4::R`](R) reader structure"] +impl crate::Readable for VAD_PARAM4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vad_param4::W`](W) writer structure"] +impl crate::Writable for VAD_PARAM4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VAD_PARAM4 to value 0x799a_6666"] +impl crate::Resettable for VAD_PARAM4_SPEC { + const RESET_VALUE: Self::Ux = 0x799a_6666; +} diff --git a/esp32p4/src/lp_i2s0/vad_param5.rs b/esp32p4/src/lp_i2s0/vad_param5.rs new file mode 100644 index 0000000000..410d2c0bdd --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_param5.rs @@ -0,0 +1,85 @@ +#[doc = "Register `VAD_PARAM5` reader"] +pub type R = crate::R; +#[doc = "Register `VAD_PARAM5` writer"] +pub type W = crate::W; +#[doc = "Field `PARAM_NOISE_MEAN_UP0` reader - VAD parameter"] +pub type PARAM_NOISE_MEAN_UP0_R = crate::FieldReader; +#[doc = "Field `PARAM_NOISE_MEAN_UP0` writer - VAD parameter"] +pub type PARAM_NOISE_MEAN_UP0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `PARAM_NOISE_MEAN_UP1` reader - VAD parameter"] +pub type PARAM_NOISE_MEAN_UP1_R = crate::FieldReader; +#[doc = "Field `PARAM_NOISE_MEAN_UP1` writer - VAD parameter"] +pub type PARAM_NOISE_MEAN_UP1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + pub fn param_noise_mean_up0(&self) -> PARAM_NOISE_MEAN_UP0_R { + PARAM_NOISE_MEAN_UP0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + pub fn param_noise_mean_up1(&self) -> PARAM_NOISE_MEAN_UP1_R { + PARAM_NOISE_MEAN_UP1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_PARAM5") + .field( + "param_noise_mean_up0", + &format_args!("{}", self.param_noise_mean_up0().bits()), + ) + .field( + "param_noise_mean_up1", + &format_args!("{}", self.param_noise_mean_up1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_noise_mean_up0(&mut self) -> PARAM_NOISE_MEAN_UP0_W { + PARAM_NOISE_MEAN_UP0_W::new(self, 0) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_noise_mean_up1(&mut self) -> PARAM_NOISE_MEAN_UP1_W { + PARAM_NOISE_MEAN_UP1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_PARAM5_SPEC; +impl crate::RegisterSpec for VAD_PARAM5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_param5::R`](R) reader structure"] +impl crate::Readable for VAD_PARAM5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vad_param5::W`](W) writer structure"] +impl crate::Writable for VAD_PARAM5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VAD_PARAM5 to value 0x7c28_7d71"] +impl crate::Resettable for VAD_PARAM5_SPEC { + const RESET_VALUE: Self::Ux = 0x7c28_7d71; +} diff --git a/esp32p4/src/lp_i2s0/vad_param6.rs b/esp32p4/src/lp_i2s0/vad_param6.rs new file mode 100644 index 0000000000..65d3150f41 --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_param6.rs @@ -0,0 +1,85 @@ +#[doc = "Register `VAD_PARAM6` reader"] +pub type R = crate::R; +#[doc = "Register `VAD_PARAM6` writer"] +pub type W = crate::W; +#[doc = "Field `PARAM_NOISE_STD_FS_THSL` reader - Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to ((noise_std_max)>>11)^2*5"] +pub type PARAM_NOISE_STD_FS_THSL_R = crate::FieldReader; +#[doc = "Field `PARAM_NOISE_STD_FS_THSL` writer - Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to ((noise_std_max)>>11)^2*5"] +pub type PARAM_NOISE_STD_FS_THSL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `PARAM_NOISE_STD_FS_THSH` reader - Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to ((noise_std_max)>>11)^2*5"] +pub type PARAM_NOISE_STD_FS_THSH_R = crate::FieldReader; +#[doc = "Field `PARAM_NOISE_STD_FS_THSH` writer - Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to ((noise_std_max)>>11)^2*5"] +pub type PARAM_NOISE_STD_FS_THSH_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to ((noise_std_max)>>11)^2*5"] + #[inline(always)] + pub fn param_noise_std_fs_thsl(&self) -> PARAM_NOISE_STD_FS_THSL_R { + PARAM_NOISE_STD_FS_THSL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to ((noise_std_max)>>11)^2*5"] + #[inline(always)] + pub fn param_noise_std_fs_thsh(&self) -> PARAM_NOISE_STD_FS_THSH_R { + PARAM_NOISE_STD_FS_THSH_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_PARAM6") + .field( + "param_noise_std_fs_thsl", + &format_args!("{}", self.param_noise_std_fs_thsl().bits()), + ) + .field( + "param_noise_std_fs_thsh", + &format_args!("{}", self.param_noise_std_fs_thsh().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to ((noise_std_max)>>11)^2*5"] + #[inline(always)] + #[must_use] + pub fn param_noise_std_fs_thsl(&mut self) -> PARAM_NOISE_STD_FS_THSL_W { + PARAM_NOISE_STD_FS_THSL_W::new(self, 0) + } + #[doc = "Bits 16:31 - Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to ((noise_std_max)>>11)^2*5"] + #[inline(always)] + #[must_use] + pub fn param_noise_std_fs_thsh(&mut self) -> PARAM_NOISE_STD_FS_THSH_W { + PARAM_NOISE_STD_FS_THSH_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_PARAM6_SPEC; +impl crate::RegisterSpec for VAD_PARAM6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_param6::R`](R) reader structure"] +impl crate::Readable for VAD_PARAM6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vad_param6::W`](W) writer structure"] +impl crate::Writable for VAD_PARAM6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VAD_PARAM6 to value 0xb400_7d00"] +impl crate::Resettable for VAD_PARAM6_SPEC { + const RESET_VALUE: Self::Ux = 0xb400_7d00; +} diff --git a/esp32p4/src/lp_i2s0/vad_param7.rs b/esp32p4/src/lp_i2s0/vad_param7.rs new file mode 100644 index 0000000000..7a9e01d1d1 --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_param7.rs @@ -0,0 +1,85 @@ +#[doc = "Register `VAD_PARAM7` reader"] +pub type R = crate::R; +#[doc = "Register `VAD_PARAM7` writer"] +pub type W = crate::W; +#[doc = "Field `PARAM_THRES_UPD_BASE` reader - VAD parameter"] +pub type PARAM_THRES_UPD_BASE_R = crate::FieldReader; +#[doc = "Field `PARAM_THRES_UPD_BASE` writer - VAD parameter"] +pub type PARAM_THRES_UPD_BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `PARAM_THRES_UPD_VARY` reader - VAD parameter"] +pub type PARAM_THRES_UPD_VARY_R = crate::FieldReader; +#[doc = "Field `PARAM_THRES_UPD_VARY` writer - VAD parameter"] +pub type PARAM_THRES_UPD_VARY_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + pub fn param_thres_upd_base(&self) -> PARAM_THRES_UPD_BASE_R { + PARAM_THRES_UPD_BASE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + pub fn param_thres_upd_vary(&self) -> PARAM_THRES_UPD_VARY_R { + PARAM_THRES_UPD_VARY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_PARAM7") + .field( + "param_thres_upd_base", + &format_args!("{}", self.param_thres_upd_base().bits()), + ) + .field( + "param_thres_upd_vary", + &format_args!("{}", self.param_thres_upd_vary().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_thres_upd_base(&mut self) -> PARAM_THRES_UPD_BASE_W { + PARAM_THRES_UPD_BASE_W::new(self, 0) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_thres_upd_vary(&mut self) -> PARAM_THRES_UPD_VARY_W { + PARAM_THRES_UPD_VARY_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_PARAM7_SPEC; +impl crate::RegisterSpec for VAD_PARAM7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_param7::R`](R) reader structure"] +impl crate::Readable for VAD_PARAM7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vad_param7::W`](W) writer structure"] +impl crate::Writable for VAD_PARAM7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VAD_PARAM7 to value 0x0148_7eb8"] +impl crate::Resettable for VAD_PARAM7_SPEC { + const RESET_VALUE: Self::Ux = 0x0148_7eb8; +} diff --git a/esp32p4/src/lp_i2s0/vad_param8.rs b/esp32p4/src/lp_i2s0/vad_param8.rs new file mode 100644 index 0000000000..3599fe89e5 --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_param8.rs @@ -0,0 +1,104 @@ +#[doc = "Register `VAD_PARAM8` reader"] +pub type R = crate::R; +#[doc = "Register `VAD_PARAM8` writer"] +pub type W = crate::W; +#[doc = "Field `PARAM_THRES_UPD_BDL` reader - Noise_std boundary low when updating threshold."] +pub type PARAM_THRES_UPD_BDL_R = crate::FieldReader; +#[doc = "Field `PARAM_THRES_UPD_BDL` writer - Noise_std boundary low when updating threshold."] +pub type PARAM_THRES_UPD_BDL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PARAM_THRES_UPD_BDH` reader - Noise_std boundary high when updating threshold."] +pub type PARAM_THRES_UPD_BDH_R = crate::FieldReader; +#[doc = "Field `PARAM_THRES_UPD_BDH` writer - Noise_std boundary high when updating threshold."] +pub type PARAM_THRES_UPD_BDH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PARAM_FEATURE_BURST` reader - VAD parameter"] +pub type PARAM_FEATURE_BURST_R = crate::FieldReader; +#[doc = "Field `PARAM_FEATURE_BURST` writer - VAD parameter"] +pub type PARAM_FEATURE_BURST_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:7 - Noise_std boundary low when updating threshold."] + #[inline(always)] + pub fn param_thres_upd_bdl(&self) -> PARAM_THRES_UPD_BDL_R { + PARAM_THRES_UPD_BDL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Noise_std boundary high when updating threshold."] + #[inline(always)] + pub fn param_thres_upd_bdh(&self) -> PARAM_THRES_UPD_BDH_R { + PARAM_THRES_UPD_BDH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + pub fn param_feature_burst(&self) -> PARAM_FEATURE_BURST_R { + PARAM_FEATURE_BURST_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_PARAM8") + .field( + "param_thres_upd_bdl", + &format_args!("{}", self.param_thres_upd_bdl().bits()), + ) + .field( + "param_thres_upd_bdh", + &format_args!("{}", self.param_thres_upd_bdh().bits()), + ) + .field( + "param_feature_burst", + &format_args!("{}", self.param_feature_burst().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Noise_std boundary low when updating threshold."] + #[inline(always)] + #[must_use] + pub fn param_thres_upd_bdl(&mut self) -> PARAM_THRES_UPD_BDL_W { + PARAM_THRES_UPD_BDL_W::new(self, 0) + } + #[doc = "Bits 8:15 - Noise_std boundary high when updating threshold."] + #[inline(always)] + #[must_use] + pub fn param_thres_upd_bdh(&mut self) -> PARAM_THRES_UPD_BDH_W { + PARAM_THRES_UPD_BDH_W::new(self, 8) + } + #[doc = "Bits 16:31 - VAD parameter"] + #[inline(always)] + #[must_use] + pub fn param_feature_burst(&mut self) -> PARAM_FEATURE_BURST_W { + PARAM_FEATURE_BURST_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "I2S VAD Parameter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_param8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vad_param8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_PARAM8_SPEC; +impl crate::RegisterSpec for VAD_PARAM8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_param8::R`](R) reader structure"] +impl crate::Readable for VAD_PARAM8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vad_param8::W`](W) writer structure"] +impl crate::Writable for VAD_PARAM8_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VAD_PARAM8 to value 0x2000_5040"] +impl crate::Resettable for VAD_PARAM8_SPEC { + const RESET_VALUE: Self::Ux = 0x2000_5040; +} diff --git a/esp32p4/src/lp_i2s0/vad_result.rs b/esp32p4/src/lp_i2s0/vad_result.rs new file mode 100644 index 0000000000..fb295f4948 --- /dev/null +++ b/esp32p4/src/lp_i2s0/vad_result.rs @@ -0,0 +1,47 @@ +#[doc = "Register `VAD_RESULT` reader"] +pub type R = crate::R; +#[doc = "Field `VAD_FLAG` reader - Reg vad flag observe signal"] +pub type VAD_FLAG_R = crate::BitReader; +#[doc = "Field `ENERGY_ENOUGH` reader - Reg energy enough observe signal"] +pub type ENERGY_ENOUGH_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Reg vad flag observe signal"] + #[inline(always)] + pub fn vad_flag(&self) -> VAD_FLAG_R { + VAD_FLAG_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reg energy enough observe signal"] + #[inline(always)] + pub fn energy_enough(&self) -> ENERGY_ENOUGH_R { + ENERGY_ENOUGH_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VAD_RESULT") + .field("vad_flag", &format_args!("{}", self.vad_flag().bit())) + .field( + "energy_enough", + &format_args!("{}", self.energy_enough().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "I2S VAD Result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_result::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VAD_RESULT_SPEC; +impl crate::RegisterSpec for VAD_RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vad_result::R`](R) reader structure"] +impl crate::Readable for VAD_RESULT_SPEC {} +#[doc = "`reset()` method sets VAD_RESULT to value 0"] +impl crate::Resettable for VAD_RESULT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_intr.rs b/esp32p4/src/lp_intr.rs new file mode 100644 index 0000000000..369123614a --- /dev/null +++ b/esp32p4/src/lp_intr.rs @@ -0,0 +1,68 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + sw_int_raw: SW_INT_RAW, + sw_int_st: SW_INT_ST, + sw_int_ena: SW_INT_ENA, + sw_int_clr: SW_INT_CLR, + status: STATUS, + _reserved5: [u8; 0x03e8], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - need_des"] + #[inline(always)] + pub const fn sw_int_raw(&self) -> &SW_INT_RAW { + &self.sw_int_raw + } + #[doc = "0x04 - need_des"] + #[inline(always)] + pub const fn sw_int_st(&self) -> &SW_INT_ST { + &self.sw_int_st + } + #[doc = "0x08 - need_des"] + #[inline(always)] + pub const fn sw_int_ena(&self) -> &SW_INT_ENA { + &self.sw_int_ena + } + #[doc = "0x0c - need_des"] + #[inline(always)] + pub const fn sw_int_clr(&self) -> &SW_INT_CLR { + &self.sw_int_clr + } + #[doc = "0x10 - need_des"] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0x3fc - need_des"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "SW_INT_RAW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_int_raw`] module"] +pub type SW_INT_RAW = crate::Reg; +#[doc = "need_des"] +pub mod sw_int_raw; +#[doc = "SW_INT_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_int_st`] module"] +pub type SW_INT_ST = crate::Reg; +#[doc = "need_des"] +pub mod sw_int_st; +#[doc = "SW_INT_ENA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_int_ena`] module"] +pub type SW_INT_ENA = crate::Reg; +#[doc = "need_des"] +pub mod sw_int_ena; +#[doc = "SW_INT_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_int_clr`] module"] +pub type SW_INT_CLR = crate::Reg; +#[doc = "need_des"] +pub mod sw_int_clr; +#[doc = "STATUS (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +pub type STATUS = crate::Reg; +#[doc = "need_des"] +pub mod status; +#[doc = "DATE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "need_des"] +pub mod date; diff --git a/esp32p4/src/lp_intr/date.rs b/esp32p4/src/lp_intr/date.rs new file mode 100644 index 0000000000..d0cb7beb4f --- /dev/null +++ b/esp32p4/src/lp_intr/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - need_des"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - need_des"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_intr/status.rs b/esp32p4/src/lp_intr/status.rs new file mode 100644 index 0000000000..d9105532e2 --- /dev/null +++ b/esp32p4/src/lp_intr/status.rs @@ -0,0 +1,267 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `LP_HUK_INTR_ST` reader - need_des"] +pub type LP_HUK_INTR_ST_R = crate::BitReader; +#[doc = "Field `SYSREG_INTR_ST` reader - need_des"] +pub type SYSREG_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_SW_INTR_ST` reader - need_des"] +pub type LP_SW_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_EFUSE_INTR_ST` reader - need_des"] +pub type LP_EFUSE_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_UART_INTR_ST` reader - need_des"] +pub type LP_UART_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_TSENS_INTR_ST` reader - need_des"] +pub type LP_TSENS_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_TOUCH_INTR_ST` reader - need_des"] +pub type LP_TOUCH_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_SPI_INTR_ST` reader - need_des"] +pub type LP_SPI_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_I2S_INTR_ST` reader - need_des"] +pub type LP_I2S_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_I2C_INTR_ST` reader - need_des"] +pub type LP_I2C_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_GPIO_INTR_ST` reader - need_des"] +pub type LP_GPIO_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_ADC_INTR_ST` reader - need_des"] +pub type LP_ADC_INTR_ST_R = crate::BitReader; +#[doc = "Field `ANAPERI_INTR_ST` reader - need_des"] +pub type ANAPERI_INTR_ST_R = crate::BitReader; +#[doc = "Field `PMU_REG_1_INTR_ST` reader - need_des"] +pub type PMU_REG_1_INTR_ST_R = crate::BitReader; +#[doc = "Field `PMU_REG_0_INTR_ST` reader - need_des"] +pub type PMU_REG_0_INTR_ST_R = crate::BitReader; +#[doc = "Field `MB_LP_INTR_ST` reader - need_des"] +pub type MB_LP_INTR_ST_R = crate::BitReader; +#[doc = "Field `MB_HP_INTR_ST` reader - need_des"] +pub type MB_HP_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_TIMER_REG_1_INTR_ST` reader - need_des"] +pub type LP_TIMER_REG_1_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_TIMER_REG_0_INTR_ST` reader - need_des"] +pub type LP_TIMER_REG_0_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_WDT_INTR_ST` reader - need_des"] +pub type LP_WDT_INTR_ST_R = crate::BitReader; +#[doc = "Field `LP_RTC_INTR_ST` reader - need_des"] +pub type LP_RTC_INTR_ST_R = crate::BitReader; +#[doc = "Field `HP_INTR_ST` reader - need_des"] +pub type HP_INTR_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 10 - need_des"] + #[inline(always)] + pub fn lp_huk_intr_st(&self) -> LP_HUK_INTR_ST_R { + LP_HUK_INTR_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + pub fn sysreg_intr_st(&self) -> SYSREG_INTR_ST_R { + SYSREG_INTR_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn lp_sw_intr_st(&self) -> LP_SW_INTR_ST_R { + LP_SW_INTR_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn lp_efuse_intr_st(&self) -> LP_EFUSE_INTR_ST_R { + LP_EFUSE_INTR_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + pub fn lp_uart_intr_st(&self) -> LP_UART_INTR_ST_R { + LP_UART_INTR_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - need_des"] + #[inline(always)] + pub fn lp_tsens_intr_st(&self) -> LP_TSENS_INTR_ST_R { + LP_TSENS_INTR_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - need_des"] + #[inline(always)] + pub fn lp_touch_intr_st(&self) -> LP_TOUCH_INTR_ST_R { + LP_TOUCH_INTR_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - need_des"] + #[inline(always)] + pub fn lp_spi_intr_st(&self) -> LP_SPI_INTR_ST_R { + LP_SPI_INTR_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - need_des"] + #[inline(always)] + pub fn lp_i2s_intr_st(&self) -> LP_I2S_INTR_ST_R { + LP_I2S_INTR_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - need_des"] + #[inline(always)] + pub fn lp_i2c_intr_st(&self) -> LP_I2C_INTR_ST_R { + LP_I2C_INTR_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - need_des"] + #[inline(always)] + pub fn lp_gpio_intr_st(&self) -> LP_GPIO_INTR_ST_R { + LP_GPIO_INTR_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - need_des"] + #[inline(always)] + pub fn lp_adc_intr_st(&self) -> LP_ADC_INTR_ST_R { + LP_ADC_INTR_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + pub fn anaperi_intr_st(&self) -> ANAPERI_INTR_ST_R { + ANAPERI_INTR_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - need_des"] + #[inline(always)] + pub fn pmu_reg_1_intr_st(&self) -> PMU_REG_1_INTR_ST_R { + PMU_REG_1_INTR_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + pub fn pmu_reg_0_intr_st(&self) -> PMU_REG_0_INTR_ST_R { + PMU_REG_0_INTR_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn mb_lp_intr_st(&self) -> MB_LP_INTR_ST_R { + MB_LP_INTR_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn mb_hp_intr_st(&self) -> MB_HP_INTR_ST_R { + MB_HP_INTR_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_timer_reg_1_intr_st(&self) -> LP_TIMER_REG_1_INTR_ST_R { + LP_TIMER_REG_1_INTR_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn lp_timer_reg_0_intr_st(&self) -> LP_TIMER_REG_0_INTR_ST_R { + LP_TIMER_REG_0_INTR_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn lp_wdt_intr_st(&self) -> LP_WDT_INTR_ST_R { + LP_WDT_INTR_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_rtc_intr_st(&self) -> LP_RTC_INTR_ST_R { + LP_RTC_INTR_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_intr_st(&self) -> HP_INTR_ST_R { + HP_INTR_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field( + "lp_huk_intr_st", + &format_args!("{}", self.lp_huk_intr_st().bit()), + ) + .field( + "sysreg_intr_st", + &format_args!("{}", self.sysreg_intr_st().bit()), + ) + .field( + "lp_sw_intr_st", + &format_args!("{}", self.lp_sw_intr_st().bit()), + ) + .field( + "lp_efuse_intr_st", + &format_args!("{}", self.lp_efuse_intr_st().bit()), + ) + .field( + "lp_uart_intr_st", + &format_args!("{}", self.lp_uart_intr_st().bit()), + ) + .field( + "lp_tsens_intr_st", + &format_args!("{}", self.lp_tsens_intr_st().bit()), + ) + .field( + "lp_touch_intr_st", + &format_args!("{}", self.lp_touch_intr_st().bit()), + ) + .field( + "lp_spi_intr_st", + &format_args!("{}", self.lp_spi_intr_st().bit()), + ) + .field( + "lp_i2s_intr_st", + &format_args!("{}", self.lp_i2s_intr_st().bit()), + ) + .field( + "lp_i2c_intr_st", + &format_args!("{}", self.lp_i2c_intr_st().bit()), + ) + .field( + "lp_gpio_intr_st", + &format_args!("{}", self.lp_gpio_intr_st().bit()), + ) + .field( + "lp_adc_intr_st", + &format_args!("{}", self.lp_adc_intr_st().bit()), + ) + .field( + "anaperi_intr_st", + &format_args!("{}", self.anaperi_intr_st().bit()), + ) + .field( + "pmu_reg_1_intr_st", + &format_args!("{}", self.pmu_reg_1_intr_st().bit()), + ) + .field( + "pmu_reg_0_intr_st", + &format_args!("{}", self.pmu_reg_0_intr_st().bit()), + ) + .field( + "mb_lp_intr_st", + &format_args!("{}", self.mb_lp_intr_st().bit()), + ) + .field( + "mb_hp_intr_st", + &format_args!("{}", self.mb_hp_intr_st().bit()), + ) + .field( + "lp_timer_reg_1_intr_st", + &format_args!("{}", self.lp_timer_reg_1_intr_st().bit()), + ) + .field( + "lp_timer_reg_0_intr_st", + &format_args!("{}", self.lp_timer_reg_0_intr_st().bit()), + ) + .field( + "lp_wdt_intr_st", + &format_args!("{}", self.lp_wdt_intr_st().bit()), + ) + .field( + "lp_rtc_intr_st", + &format_args!("{}", self.lp_rtc_intr_st().bit()), + ) + .field("hp_intr_st", &format_args!("{}", self.hp_intr_st().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_intr/sw_int_clr.rs b/esp32p4/src/lp_intr/sw_int_clr.rs new file mode 100644 index 0000000000..3d58618e1a --- /dev/null +++ b/esp32p4/src/lp_intr/sw_int_clr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SW_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SW_INT_CLR` writer - need_des"] +pub type LP_SW_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sw_int_clr(&mut self) -> LP_SW_INT_CLR_W { + LP_SW_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_INT_CLR_SPEC; +impl crate::RegisterSpec for SW_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`sw_int_clr::W`](W) writer structure"] +impl crate::Writable for SW_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SW_INT_CLR to value 0"] +impl crate::Resettable for SW_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_intr/sw_int_ena.rs b/esp32p4/src/lp_intr/sw_int_ena.rs new file mode 100644 index 0000000000..877f2c3727 --- /dev/null +++ b/esp32p4/src/lp_intr/sw_int_ena.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SW_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `SW_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SW_INT_ENA` reader - need_des"] +pub type LP_SW_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_SW_INT_ENA` writer - need_des"] +pub type LP_SW_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_sw_int_ena(&self) -> LP_SW_INT_ENA_R { + LP_SW_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SW_INT_ENA") + .field( + "lp_sw_int_ena", + &format_args!("{}", self.lp_sw_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sw_int_ena(&mut self) -> LP_SW_INT_ENA_W { + LP_SW_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_INT_ENA_SPEC; +impl crate::RegisterSpec for SW_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_int_ena::R`](R) reader structure"] +impl crate::Readable for SW_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_int_ena::W`](W) writer structure"] +impl crate::Writable for SW_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SW_INT_ENA to value 0"] +impl crate::Resettable for SW_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_intr/sw_int_raw.rs b/esp32p4/src/lp_intr/sw_int_raw.rs new file mode 100644 index 0000000000..52b7ec0f6f --- /dev/null +++ b/esp32p4/src/lp_intr/sw_int_raw.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SW_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `SW_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SW_INT_RAW` reader - need_des"] +pub type LP_SW_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_SW_INT_RAW` writer - need_des"] +pub type LP_SW_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_sw_int_raw(&self) -> LP_SW_INT_RAW_R { + LP_SW_INT_RAW_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SW_INT_RAW") + .field( + "lp_sw_int_raw", + &format_args!("{}", self.lp_sw_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sw_int_raw(&mut self) -> LP_SW_INT_RAW_W { + LP_SW_INT_RAW_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_INT_RAW_SPEC; +impl crate::RegisterSpec for SW_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_int_raw::R`](R) reader structure"] +impl crate::Readable for SW_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_int_raw::W`](W) writer structure"] +impl crate::Writable for SW_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SW_INT_RAW to value 0"] +impl crate::Resettable for SW_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_intr/sw_int_st.rs b/esp32p4/src/lp_intr/sw_int_st.rs new file mode 100644 index 0000000000..a8271fea31 --- /dev/null +++ b/esp32p4/src/lp_intr/sw_int_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SW_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `LP_SW_INT_ST` reader - need_des"] +pub type LP_SW_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_sw_int_st(&self) -> LP_SW_INT_ST_R { + LP_SW_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SW_INT_ST") + .field( + "lp_sw_int_st", + &format_args!("{}", self.lp_sw_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_INT_ST_SPEC; +impl crate::RegisterSpec for SW_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_int_st::R`](R) reader structure"] +impl crate::Readable for SW_INT_ST_SPEC {} +#[doc = "`reset()` method sets SW_INT_ST to value 0"] +impl crate::Resettable for SW_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_io_mux.rs b/esp32p4/src/lp_io_mux.rs new file mode 100644 index 0000000000..1cde6251e2 --- /dev/null +++ b/esp32p4/src/lp_io_mux.rs @@ -0,0 +1,217 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + clk_en: CLK_EN, + ver_date: VER_DATE, + pad0: PAD0, + pad1: PAD1, + pad2: PAD2, + pad3: PAD3, + pad4: PAD4, + pad5: PAD5, + pad6: PAD6, + pad7: PAD7, + pad8: PAD8, + pad9: PAD9, + pad10: PAD10, + pad11: PAD11, + pad120: PAD120, + pad13: PAD13, + pad14: PAD14, + pad15: PAD15, + ext_wakeup0_sel: EXT_WAKEUP0_SEL, + lp_pad_hold: LP_PAD_HOLD, + lp_pad_hys: LP_PAD_HYS, +} +impl RegisterBlock { + #[doc = "0x00 - Reserved"] + #[inline(always)] + pub const fn clk_en(&self) -> &CLK_EN { + &self.clk_en + } + #[doc = "0x04 - Reserved"] + #[inline(always)] + pub const fn ver_date(&self) -> &VER_DATE { + &self.ver_date + } + #[doc = "0x08 - Reserved"] + #[inline(always)] + pub const fn pad0(&self) -> &PAD0 { + &self.pad0 + } + #[doc = "0x0c - Reserved"] + #[inline(always)] + pub const fn pad1(&self) -> &PAD1 { + &self.pad1 + } + #[doc = "0x10 - Reserved"] + #[inline(always)] + pub const fn pad2(&self) -> &PAD2 { + &self.pad2 + } + #[doc = "0x14 - Reserved"] + #[inline(always)] + pub const fn pad3(&self) -> &PAD3 { + &self.pad3 + } + #[doc = "0x18 - Reserved"] + #[inline(always)] + pub const fn pad4(&self) -> &PAD4 { + &self.pad4 + } + #[doc = "0x1c - Reserved"] + #[inline(always)] + pub const fn pad5(&self) -> &PAD5 { + &self.pad5 + } + #[doc = "0x20 - Reserved"] + #[inline(always)] + pub const fn pad6(&self) -> &PAD6 { + &self.pad6 + } + #[doc = "0x24 - Reserved"] + #[inline(always)] + pub const fn pad7(&self) -> &PAD7 { + &self.pad7 + } + #[doc = "0x28 - Reserved"] + #[inline(always)] + pub const fn pad8(&self) -> &PAD8 { + &self.pad8 + } + #[doc = "0x2c - Reserved"] + #[inline(always)] + pub const fn pad9(&self) -> &PAD9 { + &self.pad9 + } + #[doc = "0x30 - Reserved"] + #[inline(always)] + pub const fn pad10(&self) -> &PAD10 { + &self.pad10 + } + #[doc = "0x34 - Reserved"] + #[inline(always)] + pub const fn pad11(&self) -> &PAD11 { + &self.pad11 + } + #[doc = "0x38 - Reserved"] + #[inline(always)] + pub const fn pad120(&self) -> &PAD120 { + &self.pad120 + } + #[doc = "0x3c - Reserved"] + #[inline(always)] + pub const fn pad13(&self) -> &PAD13 { + &self.pad13 + } + #[doc = "0x40 - Reserved"] + #[inline(always)] + pub const fn pad14(&self) -> &PAD14 { + &self.pad14 + } + #[doc = "0x44 - Reserved"] + #[inline(always)] + pub const fn pad15(&self) -> &PAD15 { + &self.pad15 + } + #[doc = "0x48 - Reserved"] + #[inline(always)] + pub const fn ext_wakeup0_sel(&self) -> &EXT_WAKEUP0_SEL { + &self.ext_wakeup0_sel + } + #[doc = "0x4c - Reserved"] + #[inline(always)] + pub const fn lp_pad_hold(&self) -> &LP_PAD_HOLD { + &self.lp_pad_hold + } + #[doc = "0x50 - Reserved"] + #[inline(always)] + pub const fn lp_pad_hys(&self) -> &LP_PAD_HYS { + &self.lp_pad_hys + } +} +#[doc = "CLK_EN (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_en`] module"] +pub type CLK_EN = crate::Reg; +#[doc = "Reserved"] +pub mod clk_en; +#[doc = "VER_DATE (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ver_date`] module"] +pub type VER_DATE = crate::Reg; +#[doc = "Reserved"] +pub mod ver_date; +#[doc = "PAD0 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad0`] module"] +pub type PAD0 = crate::Reg; +#[doc = "Reserved"] +pub mod pad0; +#[doc = "PAD1 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad1`] module"] +pub type PAD1 = crate::Reg; +#[doc = "Reserved"] +pub mod pad1; +#[doc = "PAD2 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad2`] module"] +pub type PAD2 = crate::Reg; +#[doc = "Reserved"] +pub mod pad2; +#[doc = "PAD3 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad3`] module"] +pub type PAD3 = crate::Reg; +#[doc = "Reserved"] +pub mod pad3; +#[doc = "PAD4 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad4`] module"] +pub type PAD4 = crate::Reg; +#[doc = "Reserved"] +pub mod pad4; +#[doc = "PAD5 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad5`] module"] +pub type PAD5 = crate::Reg; +#[doc = "Reserved"] +pub mod pad5; +#[doc = "PAD6 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad6`] module"] +pub type PAD6 = crate::Reg; +#[doc = "Reserved"] +pub mod pad6; +#[doc = "PAD7 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad7`] module"] +pub type PAD7 = crate::Reg; +#[doc = "Reserved"] +pub mod pad7; +#[doc = "PAD8 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad8`] module"] +pub type PAD8 = crate::Reg; +#[doc = "Reserved"] +pub mod pad8; +#[doc = "PAD9 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad9`] module"] +pub type PAD9 = crate::Reg; +#[doc = "Reserved"] +pub mod pad9; +#[doc = "PAD10 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad10`] module"] +pub type PAD10 = crate::Reg; +#[doc = "Reserved"] +pub mod pad10; +#[doc = "PAD11 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad11`] module"] +pub type PAD11 = crate::Reg; +#[doc = "Reserved"] +pub mod pad11; +#[doc = "PAD120 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad120::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad120::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad120`] module"] +pub type PAD120 = crate::Reg; +#[doc = "Reserved"] +pub mod pad120; +#[doc = "PAD13 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad13`] module"] +pub type PAD13 = crate::Reg; +#[doc = "Reserved"] +pub mod pad13; +#[doc = "PAD14 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad14`] module"] +pub type PAD14 = crate::Reg; +#[doc = "Reserved"] +pub mod pad14; +#[doc = "PAD15 (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad15`] module"] +pub type PAD15 = crate::Reg; +#[doc = "Reserved"] +pub mod pad15; +#[doc = "EXT_WAKEUP0_SEL (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup0_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_wakeup0_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_wakeup0_sel`] module"] +pub type EXT_WAKEUP0_SEL = crate::Reg; +#[doc = "Reserved"] +pub mod ext_wakeup0_sel; +#[doc = "LP_PAD_HOLD (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_pad_hold::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_pad_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_pad_hold`] module"] +pub type LP_PAD_HOLD = crate::Reg; +#[doc = "Reserved"] +pub mod lp_pad_hold; +#[doc = "LP_PAD_HYS (rw) register accessor: Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_pad_hys::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_pad_hys::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_pad_hys`] module"] +pub type LP_PAD_HYS = crate::Reg; +#[doc = "Reserved"] +pub mod lp_pad_hys; diff --git a/esp32p4/src/lp_io_mux/clk_en.rs b/esp32p4/src/lp_io_mux/clk_en.rs new file mode 100644 index 0000000000..985706e75b --- /dev/null +++ b/esp32p4/src/lp_io_mux/clk_en.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLK_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_EN` writer"] +pub type W = crate::W; +#[doc = "Field `REG_CLK_EN` reader - Reserved"] +pub type REG_CLK_EN_R = crate::BitReader; +#[doc = "Field `REG_CLK_EN` writer - Reserved"] +pub type REG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + pub fn reg_clk_en(&self) -> REG_CLK_EN_R { + REG_CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_EN") + .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_clk_en(&mut self) -> REG_CLK_EN_W { + REG_CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_EN_SPEC; +impl crate::RegisterSpec for CLK_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_en::R`](R) reader structure"] +impl crate::Readable for CLK_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_en::W`](W) writer structure"] +impl crate::Writable for CLK_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_EN to value 0x01"] +impl crate::Resettable for CLK_EN_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/lp_io_mux/ext_wakeup0_sel.rs b/esp32p4/src/lp_io_mux/ext_wakeup0_sel.rs new file mode 100644 index 0000000000..d931c2f60c --- /dev/null +++ b/esp32p4/src/lp_io_mux/ext_wakeup0_sel.rs @@ -0,0 +1,85 @@ +#[doc = "Register `EXT_WAKEUP0_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_WAKEUP0_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `REG_XTL_EXT_CTR_SEL` reader - select LP GPIO 0 ~ 15 to control XTAL"] +pub type REG_XTL_EXT_CTR_SEL_R = crate::FieldReader; +#[doc = "Field `REG_XTL_EXT_CTR_SEL` writer - select LP GPIO 0 ~ 15 to control XTAL"] +pub type REG_XTL_EXT_CTR_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `REG_EXT_WAKEUP0_SEL` reader - Reserved"] +pub type REG_EXT_WAKEUP0_SEL_R = crate::FieldReader; +#[doc = "Field `REG_EXT_WAKEUP0_SEL` writer - Reserved"] +pub type REG_EXT_WAKEUP0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - select LP GPIO 0 ~ 15 to control XTAL"] + #[inline(always)] + pub fn reg_xtl_ext_ctr_sel(&self) -> REG_XTL_EXT_CTR_SEL_R { + REG_XTL_EXT_CTR_SEL_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - Reserved"] + #[inline(always)] + pub fn reg_ext_wakeup0_sel(&self) -> REG_EXT_WAKEUP0_SEL_R { + REG_EXT_WAKEUP0_SEL_R::new(((self.bits >> 5) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_WAKEUP0_SEL") + .field( + "reg_xtl_ext_ctr_sel", + &format_args!("{}", self.reg_xtl_ext_ctr_sel().bits()), + ) + .field( + "reg_ext_wakeup0_sel", + &format_args!("{}", self.reg_ext_wakeup0_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - select LP GPIO 0 ~ 15 to control XTAL"] + #[inline(always)] + #[must_use] + pub fn reg_xtl_ext_ctr_sel(&mut self) -> REG_XTL_EXT_CTR_SEL_W { + REG_XTL_EXT_CTR_SEL_W::new(self, 0) + } + #[doc = "Bits 5:9 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ext_wakeup0_sel(&mut self) -> REG_EXT_WAKEUP0_SEL_W { + REG_EXT_WAKEUP0_SEL_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup0_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_wakeup0_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_WAKEUP0_SEL_SPEC; +impl crate::RegisterSpec for EXT_WAKEUP0_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_wakeup0_sel::R`](R) reader structure"] +impl crate::Readable for EXT_WAKEUP0_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_wakeup0_sel::W`](W) writer structure"] +impl crate::Writable for EXT_WAKEUP0_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_WAKEUP0_SEL to value 0"] +impl crate::Resettable for EXT_WAKEUP0_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_io_mux/lp_pad_hold.rs b/esp32p4/src/lp_io_mux/lp_pad_hold.rs new file mode 100644 index 0000000000..5f91837604 --- /dev/null +++ b/esp32p4/src/lp_io_mux/lp_pad_hold.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_PAD_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `LP_PAD_HOLD` writer"] +pub type W = crate::W; +#[doc = "Field `REG_LP_GPIO_HOLD` reader - Reserved"] +pub type REG_LP_GPIO_HOLD_R = crate::FieldReader; +#[doc = "Field `REG_LP_GPIO_HOLD` writer - Reserved"] +pub type REG_LP_GPIO_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + pub fn reg_lp_gpio_hold(&self) -> REG_LP_GPIO_HOLD_R { + REG_LP_GPIO_HOLD_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_PAD_HOLD") + .field( + "reg_lp_gpio_hold", + &format_args!("{}", self.reg_lp_gpio_hold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_lp_gpio_hold(&mut self) -> REG_LP_GPIO_HOLD_W { + REG_LP_GPIO_HOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_pad_hold::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_pad_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_PAD_HOLD_SPEC; +impl crate::RegisterSpec for LP_PAD_HOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_pad_hold::R`](R) reader structure"] +impl crate::Readable for LP_PAD_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_pad_hold::W`](W) writer structure"] +impl crate::Writable for LP_PAD_HOLD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_PAD_HOLD to value 0"] +impl crate::Resettable for LP_PAD_HOLD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_io_mux/lp_pad_hys.rs b/esp32p4/src/lp_io_mux/lp_pad_hys.rs new file mode 100644 index 0000000000..2091c2d944 --- /dev/null +++ b/esp32p4/src/lp_io_mux/lp_pad_hys.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_PAD_HYS` reader"] +pub type R = crate::R; +#[doc = "Register `LP_PAD_HYS` writer"] +pub type W = crate::W; +#[doc = "Field `REG_LP_GPIO_HYS` reader - Reserved"] +pub type REG_LP_GPIO_HYS_R = crate::FieldReader; +#[doc = "Field `REG_LP_GPIO_HYS` writer - Reserved"] +pub type REG_LP_GPIO_HYS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + pub fn reg_lp_gpio_hys(&self) -> REG_LP_GPIO_HYS_R { + REG_LP_GPIO_HYS_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_PAD_HYS") + .field( + "reg_lp_gpio_hys", + &format_args!("{}", self.reg_lp_gpio_hys().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_lp_gpio_hys(&mut self) -> REG_LP_GPIO_HYS_W { + REG_LP_GPIO_HYS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_pad_hys::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_pad_hys::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_PAD_HYS_SPEC; +impl crate::RegisterSpec for LP_PAD_HYS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_pad_hys::R`](R) reader structure"] +impl crate::Readable for LP_PAD_HYS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_pad_hys::W`](W) writer structure"] +impl crate::Writable for LP_PAD_HYS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_PAD_HYS to value 0"] +impl crate::Resettable for LP_PAD_HYS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_io_mux/pad0.rs b/esp32p4/src/lp_io_mux/pad0.rs new file mode 100644 index 0000000000..f21dfff355 --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad0.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD0` reader"] +pub type R = crate::R; +#[doc = "Register `PAD0` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD0_DRV` reader - Reserved"] +pub type REG_PAD0_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD0_DRV` writer - Reserved"] +pub type REG_PAD0_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD0_RDE` reader - Reserved"] +pub type REG_PAD0_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD0_RDE` writer - Reserved"] +pub type REG_PAD0_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD0_RUE` reader - Reserved"] +pub type REG_PAD0_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD0_RUE` writer - Reserved"] +pub type REG_PAD0_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD0_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD0_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD0_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD0_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD0_FUN_SEL` reader - function sel"] +pub type REG_PAD0_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD0_FUN_SEL` writer - function sel"] +pub type REG_PAD0_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD0_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD0_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD0_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD0_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD0_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD0_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD0_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD0_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD0_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD0_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD0_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD0_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD0_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD0_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD0_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD0_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD0_FILTER_EN` reader - need des"] +pub type REG_PAD0_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD0_FILTER_EN` writer - need des"] +pub type REG_PAD0_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad0_drv(&self) -> REG_PAD0_DRV_R { + REG_PAD0_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad0_rde(&self) -> REG_PAD0_RDE_R { + REG_PAD0_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad0_rue(&self) -> REG_PAD0_RUE_R { + REG_PAD0_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad0_mux_sel(&self) -> REG_PAD0_MUX_SEL_R { + REG_PAD0_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad0_fun_sel(&self) -> REG_PAD0_FUN_SEL_R { + REG_PAD0_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad0_slp_sel(&self) -> REG_PAD0_SLP_SEL_R { + REG_PAD0_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad0_slp_ie(&self) -> REG_PAD0_SLP_IE_R { + REG_PAD0_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad0_slp_oe(&self) -> REG_PAD0_SLP_OE_R { + REG_PAD0_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad0_fun_ie(&self) -> REG_PAD0_FUN_IE_R { + REG_PAD0_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad0_filter_en(&self) -> REG_PAD0_FILTER_EN_R { + REG_PAD0_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD0") + .field( + "reg_pad0_drv", + &format_args!("{}", self.reg_pad0_drv().bits()), + ) + .field( + "reg_pad0_rde", + &format_args!("{}", self.reg_pad0_rde().bit()), + ) + .field( + "reg_pad0_rue", + &format_args!("{}", self.reg_pad0_rue().bit()), + ) + .field( + "reg_pad0_mux_sel", + &format_args!("{}", self.reg_pad0_mux_sel().bit()), + ) + .field( + "reg_pad0_fun_sel", + &format_args!("{}", self.reg_pad0_fun_sel().bits()), + ) + .field( + "reg_pad0_slp_sel", + &format_args!("{}", self.reg_pad0_slp_sel().bit()), + ) + .field( + "reg_pad0_slp_ie", + &format_args!("{}", self.reg_pad0_slp_ie().bit()), + ) + .field( + "reg_pad0_slp_oe", + &format_args!("{}", self.reg_pad0_slp_oe().bit()), + ) + .field( + "reg_pad0_fun_ie", + &format_args!("{}", self.reg_pad0_fun_ie().bit()), + ) + .field( + "reg_pad0_filter_en", + &format_args!("{}", self.reg_pad0_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad0_drv(&mut self) -> REG_PAD0_DRV_W { + REG_PAD0_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad0_rde(&mut self) -> REG_PAD0_RDE_W { + REG_PAD0_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad0_rue(&mut self) -> REG_PAD0_RUE_W { + REG_PAD0_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad0_mux_sel(&mut self) -> REG_PAD0_MUX_SEL_W { + REG_PAD0_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad0_fun_sel(&mut self) -> REG_PAD0_FUN_SEL_W { + REG_PAD0_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad0_slp_sel(&mut self) -> REG_PAD0_SLP_SEL_W { + REG_PAD0_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad0_slp_ie(&mut self) -> REG_PAD0_SLP_IE_W { + REG_PAD0_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad0_slp_oe(&mut self) -> REG_PAD0_SLP_OE_W { + REG_PAD0_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad0_fun_ie(&mut self) -> REG_PAD0_FUN_IE_W { + REG_PAD0_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad0_filter_en(&mut self) -> REG_PAD0_FILTER_EN_W { + REG_PAD0_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD0_SPEC; +impl crate::RegisterSpec for PAD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad0::R`](R) reader structure"] +impl crate::Readable for PAD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad0::W`](W) writer structure"] +impl crate::Writable for PAD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD0 to value 0x02"] +impl crate::Resettable for PAD0_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad1.rs b/esp32p4/src/lp_io_mux/pad1.rs new file mode 100644 index 0000000000..0eca413a3d --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad1.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD1` reader"] +pub type R = crate::R; +#[doc = "Register `PAD1` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD1_DRV` reader - Reserved"] +pub type REG_PAD1_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD1_DRV` writer - Reserved"] +pub type REG_PAD1_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD1_RDE` reader - Reserved"] +pub type REG_PAD1_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD1_RDE` writer - Reserved"] +pub type REG_PAD1_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD1_RUE` reader - Reserved"] +pub type REG_PAD1_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD1_RUE` writer - Reserved"] +pub type REG_PAD1_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD1_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD1_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD1_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD1_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD1_FUN_SEL` reader - function sel"] +pub type REG_PAD1_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD1_FUN_SEL` writer - function sel"] +pub type REG_PAD1_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD1_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD1_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD1_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD1_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD1_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD1_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD1_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD1_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD1_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD1_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD1_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD1_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD1_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD1_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD1_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD1_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD1_FILTER_EN` reader - need des"] +pub type REG_PAD1_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD1_FILTER_EN` writer - need des"] +pub type REG_PAD1_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad1_drv(&self) -> REG_PAD1_DRV_R { + REG_PAD1_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad1_rde(&self) -> REG_PAD1_RDE_R { + REG_PAD1_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad1_rue(&self) -> REG_PAD1_RUE_R { + REG_PAD1_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad1_mux_sel(&self) -> REG_PAD1_MUX_SEL_R { + REG_PAD1_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad1_fun_sel(&self) -> REG_PAD1_FUN_SEL_R { + REG_PAD1_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad1_slp_sel(&self) -> REG_PAD1_SLP_SEL_R { + REG_PAD1_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad1_slp_ie(&self) -> REG_PAD1_SLP_IE_R { + REG_PAD1_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad1_slp_oe(&self) -> REG_PAD1_SLP_OE_R { + REG_PAD1_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad1_fun_ie(&self) -> REG_PAD1_FUN_IE_R { + REG_PAD1_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad1_filter_en(&self) -> REG_PAD1_FILTER_EN_R { + REG_PAD1_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD1") + .field( + "reg_pad1_drv", + &format_args!("{}", self.reg_pad1_drv().bits()), + ) + .field( + "reg_pad1_rde", + &format_args!("{}", self.reg_pad1_rde().bit()), + ) + .field( + "reg_pad1_rue", + &format_args!("{}", self.reg_pad1_rue().bit()), + ) + .field( + "reg_pad1_mux_sel", + &format_args!("{}", self.reg_pad1_mux_sel().bit()), + ) + .field( + "reg_pad1_fun_sel", + &format_args!("{}", self.reg_pad1_fun_sel().bits()), + ) + .field( + "reg_pad1_slp_sel", + &format_args!("{}", self.reg_pad1_slp_sel().bit()), + ) + .field( + "reg_pad1_slp_ie", + &format_args!("{}", self.reg_pad1_slp_ie().bit()), + ) + .field( + "reg_pad1_slp_oe", + &format_args!("{}", self.reg_pad1_slp_oe().bit()), + ) + .field( + "reg_pad1_fun_ie", + &format_args!("{}", self.reg_pad1_fun_ie().bit()), + ) + .field( + "reg_pad1_filter_en", + &format_args!("{}", self.reg_pad1_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad1_drv(&mut self) -> REG_PAD1_DRV_W { + REG_PAD1_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad1_rde(&mut self) -> REG_PAD1_RDE_W { + REG_PAD1_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad1_rue(&mut self) -> REG_PAD1_RUE_W { + REG_PAD1_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad1_mux_sel(&mut self) -> REG_PAD1_MUX_SEL_W { + REG_PAD1_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad1_fun_sel(&mut self) -> REG_PAD1_FUN_SEL_W { + REG_PAD1_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad1_slp_sel(&mut self) -> REG_PAD1_SLP_SEL_W { + REG_PAD1_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad1_slp_ie(&mut self) -> REG_PAD1_SLP_IE_W { + REG_PAD1_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad1_slp_oe(&mut self) -> REG_PAD1_SLP_OE_W { + REG_PAD1_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad1_fun_ie(&mut self) -> REG_PAD1_FUN_IE_W { + REG_PAD1_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad1_filter_en(&mut self) -> REG_PAD1_FILTER_EN_W { + REG_PAD1_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD1_SPEC; +impl crate::RegisterSpec for PAD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad1::R`](R) reader structure"] +impl crate::Readable for PAD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad1::W`](W) writer structure"] +impl crate::Writable for PAD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD1 to value 0x02"] +impl crate::Resettable for PAD1_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad10.rs b/esp32p4/src/lp_io_mux/pad10.rs new file mode 100644 index 0000000000..e13e52f6f2 --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad10.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD10` reader"] +pub type R = crate::R; +#[doc = "Register `PAD10` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD10_DRV` reader - Reserved"] +pub type REG_PAD10_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD10_DRV` writer - Reserved"] +pub type REG_PAD10_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD10_RDE` reader - Reserved"] +pub type REG_PAD10_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD10_RDE` writer - Reserved"] +pub type REG_PAD10_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD10_RUE` reader - Reserved"] +pub type REG_PAD10_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD10_RUE` writer - Reserved"] +pub type REG_PAD10_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD10_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD10_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD10_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD10_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD10_FUN_SEL` reader - function sel"] +pub type REG_PAD10_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD10_FUN_SEL` writer - function sel"] +pub type REG_PAD10_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD10_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD10_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD10_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD10_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD10_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD10_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD10_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD10_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD10_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD10_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD10_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD10_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD10_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD10_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD10_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD10_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD10_FILTER_EN` reader - need des"] +pub type REG_PAD10_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD10_FILTER_EN` writer - need des"] +pub type REG_PAD10_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad10_drv(&self) -> REG_PAD10_DRV_R { + REG_PAD10_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad10_rde(&self) -> REG_PAD10_RDE_R { + REG_PAD10_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad10_rue(&self) -> REG_PAD10_RUE_R { + REG_PAD10_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad10_mux_sel(&self) -> REG_PAD10_MUX_SEL_R { + REG_PAD10_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad10_fun_sel(&self) -> REG_PAD10_FUN_SEL_R { + REG_PAD10_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad10_slp_sel(&self) -> REG_PAD10_SLP_SEL_R { + REG_PAD10_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad10_slp_ie(&self) -> REG_PAD10_SLP_IE_R { + REG_PAD10_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad10_slp_oe(&self) -> REG_PAD10_SLP_OE_R { + REG_PAD10_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad10_fun_ie(&self) -> REG_PAD10_FUN_IE_R { + REG_PAD10_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad10_filter_en(&self) -> REG_PAD10_FILTER_EN_R { + REG_PAD10_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD10") + .field( + "reg_pad10_drv", + &format_args!("{}", self.reg_pad10_drv().bits()), + ) + .field( + "reg_pad10_rde", + &format_args!("{}", self.reg_pad10_rde().bit()), + ) + .field( + "reg_pad10_rue", + &format_args!("{}", self.reg_pad10_rue().bit()), + ) + .field( + "reg_pad10_mux_sel", + &format_args!("{}", self.reg_pad10_mux_sel().bit()), + ) + .field( + "reg_pad10_fun_sel", + &format_args!("{}", self.reg_pad10_fun_sel().bits()), + ) + .field( + "reg_pad10_slp_sel", + &format_args!("{}", self.reg_pad10_slp_sel().bit()), + ) + .field( + "reg_pad10_slp_ie", + &format_args!("{}", self.reg_pad10_slp_ie().bit()), + ) + .field( + "reg_pad10_slp_oe", + &format_args!("{}", self.reg_pad10_slp_oe().bit()), + ) + .field( + "reg_pad10_fun_ie", + &format_args!("{}", self.reg_pad10_fun_ie().bit()), + ) + .field( + "reg_pad10_filter_en", + &format_args!("{}", self.reg_pad10_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad10_drv(&mut self) -> REG_PAD10_DRV_W { + REG_PAD10_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad10_rde(&mut self) -> REG_PAD10_RDE_W { + REG_PAD10_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad10_rue(&mut self) -> REG_PAD10_RUE_W { + REG_PAD10_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad10_mux_sel(&mut self) -> REG_PAD10_MUX_SEL_W { + REG_PAD10_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad10_fun_sel(&mut self) -> REG_PAD10_FUN_SEL_W { + REG_PAD10_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad10_slp_sel(&mut self) -> REG_PAD10_SLP_SEL_W { + REG_PAD10_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad10_slp_ie(&mut self) -> REG_PAD10_SLP_IE_W { + REG_PAD10_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad10_slp_oe(&mut self) -> REG_PAD10_SLP_OE_W { + REG_PAD10_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad10_fun_ie(&mut self) -> REG_PAD10_FUN_IE_W { + REG_PAD10_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad10_filter_en(&mut self) -> REG_PAD10_FILTER_EN_W { + REG_PAD10_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD10_SPEC; +impl crate::RegisterSpec for PAD10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad10::R`](R) reader structure"] +impl crate::Readable for PAD10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad10::W`](W) writer structure"] +impl crate::Writable for PAD10_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD10 to value 0x02"] +impl crate::Resettable for PAD10_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad11.rs b/esp32p4/src/lp_io_mux/pad11.rs new file mode 100644 index 0000000000..456491a03a --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad11.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD11` reader"] +pub type R = crate::R; +#[doc = "Register `PAD11` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD11_DRV` reader - Reserved"] +pub type REG_PAD11_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD11_DRV` writer - Reserved"] +pub type REG_PAD11_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD11_RDE` reader - Reserved"] +pub type REG_PAD11_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD11_RDE` writer - Reserved"] +pub type REG_PAD11_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD11_RUE` reader - Reserved"] +pub type REG_PAD11_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD11_RUE` writer - Reserved"] +pub type REG_PAD11_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD11_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD11_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD11_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD11_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD11_FUN_SEL` reader - function sel"] +pub type REG_PAD11_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD11_FUN_SEL` writer - function sel"] +pub type REG_PAD11_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD11_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD11_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD11_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD11_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD11_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD11_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD11_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD11_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD11_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD11_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD11_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD11_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD11_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD11_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD11_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD11_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD11_FILTER_EN` reader - need des"] +pub type REG_PAD11_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD11_FILTER_EN` writer - need des"] +pub type REG_PAD11_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad11_drv(&self) -> REG_PAD11_DRV_R { + REG_PAD11_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad11_rde(&self) -> REG_PAD11_RDE_R { + REG_PAD11_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad11_rue(&self) -> REG_PAD11_RUE_R { + REG_PAD11_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad11_mux_sel(&self) -> REG_PAD11_MUX_SEL_R { + REG_PAD11_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad11_fun_sel(&self) -> REG_PAD11_FUN_SEL_R { + REG_PAD11_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad11_slp_sel(&self) -> REG_PAD11_SLP_SEL_R { + REG_PAD11_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad11_slp_ie(&self) -> REG_PAD11_SLP_IE_R { + REG_PAD11_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad11_slp_oe(&self) -> REG_PAD11_SLP_OE_R { + REG_PAD11_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad11_fun_ie(&self) -> REG_PAD11_FUN_IE_R { + REG_PAD11_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad11_filter_en(&self) -> REG_PAD11_FILTER_EN_R { + REG_PAD11_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD11") + .field( + "reg_pad11_drv", + &format_args!("{}", self.reg_pad11_drv().bits()), + ) + .field( + "reg_pad11_rde", + &format_args!("{}", self.reg_pad11_rde().bit()), + ) + .field( + "reg_pad11_rue", + &format_args!("{}", self.reg_pad11_rue().bit()), + ) + .field( + "reg_pad11_mux_sel", + &format_args!("{}", self.reg_pad11_mux_sel().bit()), + ) + .field( + "reg_pad11_fun_sel", + &format_args!("{}", self.reg_pad11_fun_sel().bits()), + ) + .field( + "reg_pad11_slp_sel", + &format_args!("{}", self.reg_pad11_slp_sel().bit()), + ) + .field( + "reg_pad11_slp_ie", + &format_args!("{}", self.reg_pad11_slp_ie().bit()), + ) + .field( + "reg_pad11_slp_oe", + &format_args!("{}", self.reg_pad11_slp_oe().bit()), + ) + .field( + "reg_pad11_fun_ie", + &format_args!("{}", self.reg_pad11_fun_ie().bit()), + ) + .field( + "reg_pad11_filter_en", + &format_args!("{}", self.reg_pad11_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad11_drv(&mut self) -> REG_PAD11_DRV_W { + REG_PAD11_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad11_rde(&mut self) -> REG_PAD11_RDE_W { + REG_PAD11_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad11_rue(&mut self) -> REG_PAD11_RUE_W { + REG_PAD11_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad11_mux_sel(&mut self) -> REG_PAD11_MUX_SEL_W { + REG_PAD11_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad11_fun_sel(&mut self) -> REG_PAD11_FUN_SEL_W { + REG_PAD11_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad11_slp_sel(&mut self) -> REG_PAD11_SLP_SEL_W { + REG_PAD11_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad11_slp_ie(&mut self) -> REG_PAD11_SLP_IE_W { + REG_PAD11_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad11_slp_oe(&mut self) -> REG_PAD11_SLP_OE_W { + REG_PAD11_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad11_fun_ie(&mut self) -> REG_PAD11_FUN_IE_W { + REG_PAD11_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad11_filter_en(&mut self) -> REG_PAD11_FILTER_EN_W { + REG_PAD11_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD11_SPEC; +impl crate::RegisterSpec for PAD11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad11::R`](R) reader structure"] +impl crate::Readable for PAD11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad11::W`](W) writer structure"] +impl crate::Writable for PAD11_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD11 to value 0x02"] +impl crate::Resettable for PAD11_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad120.rs b/esp32p4/src/lp_io_mux/pad120.rs new file mode 100644 index 0000000000..773d4aaa26 --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad120.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD120` reader"] +pub type R = crate::R; +#[doc = "Register `PAD120` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD12_DRV` reader - Reserved"] +pub type REG_PAD12_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD12_DRV` writer - Reserved"] +pub type REG_PAD12_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD12_RDE` reader - Reserved"] +pub type REG_PAD12_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD12_RDE` writer - Reserved"] +pub type REG_PAD12_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD12_RUE` reader - Reserved"] +pub type REG_PAD12_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD12_RUE` writer - Reserved"] +pub type REG_PAD12_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD12_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD12_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD12_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD12_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD12_FUN_SEL` reader - function sel"] +pub type REG_PAD12_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD12_FUN_SEL` writer - function sel"] +pub type REG_PAD12_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD12_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD12_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD12_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD12_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD12_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD12_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD12_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD12_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD12_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD12_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD12_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD12_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD12_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD12_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD12_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD12_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD12_FILTER_EN` reader - need des"] +pub type REG_PAD12_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD12_FILTER_EN` writer - need des"] +pub type REG_PAD12_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad12_drv(&self) -> REG_PAD12_DRV_R { + REG_PAD12_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad12_rde(&self) -> REG_PAD12_RDE_R { + REG_PAD12_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad12_rue(&self) -> REG_PAD12_RUE_R { + REG_PAD12_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad12_mux_sel(&self) -> REG_PAD12_MUX_SEL_R { + REG_PAD12_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad12_fun_sel(&self) -> REG_PAD12_FUN_SEL_R { + REG_PAD12_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad12_slp_sel(&self) -> REG_PAD12_SLP_SEL_R { + REG_PAD12_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad12_slp_ie(&self) -> REG_PAD12_SLP_IE_R { + REG_PAD12_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad12_slp_oe(&self) -> REG_PAD12_SLP_OE_R { + REG_PAD12_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad12_fun_ie(&self) -> REG_PAD12_FUN_IE_R { + REG_PAD12_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad12_filter_en(&self) -> REG_PAD12_FILTER_EN_R { + REG_PAD12_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD120") + .field( + "reg_pad12_drv", + &format_args!("{}", self.reg_pad12_drv().bits()), + ) + .field( + "reg_pad12_rde", + &format_args!("{}", self.reg_pad12_rde().bit()), + ) + .field( + "reg_pad12_rue", + &format_args!("{}", self.reg_pad12_rue().bit()), + ) + .field( + "reg_pad12_mux_sel", + &format_args!("{}", self.reg_pad12_mux_sel().bit()), + ) + .field( + "reg_pad12_fun_sel", + &format_args!("{}", self.reg_pad12_fun_sel().bits()), + ) + .field( + "reg_pad12_slp_sel", + &format_args!("{}", self.reg_pad12_slp_sel().bit()), + ) + .field( + "reg_pad12_slp_ie", + &format_args!("{}", self.reg_pad12_slp_ie().bit()), + ) + .field( + "reg_pad12_slp_oe", + &format_args!("{}", self.reg_pad12_slp_oe().bit()), + ) + .field( + "reg_pad12_fun_ie", + &format_args!("{}", self.reg_pad12_fun_ie().bit()), + ) + .field( + "reg_pad12_filter_en", + &format_args!("{}", self.reg_pad12_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad12_drv(&mut self) -> REG_PAD12_DRV_W { + REG_PAD12_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad12_rde(&mut self) -> REG_PAD12_RDE_W { + REG_PAD12_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad12_rue(&mut self) -> REG_PAD12_RUE_W { + REG_PAD12_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad12_mux_sel(&mut self) -> REG_PAD12_MUX_SEL_W { + REG_PAD12_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad12_fun_sel(&mut self) -> REG_PAD12_FUN_SEL_W { + REG_PAD12_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad12_slp_sel(&mut self) -> REG_PAD12_SLP_SEL_W { + REG_PAD12_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad12_slp_ie(&mut self) -> REG_PAD12_SLP_IE_W { + REG_PAD12_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad12_slp_oe(&mut self) -> REG_PAD12_SLP_OE_W { + REG_PAD12_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad12_fun_ie(&mut self) -> REG_PAD12_FUN_IE_W { + REG_PAD12_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad12_filter_en(&mut self) -> REG_PAD12_FILTER_EN_W { + REG_PAD12_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad120::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad120::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD120_SPEC; +impl crate::RegisterSpec for PAD120_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad120::R`](R) reader structure"] +impl crate::Readable for PAD120_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad120::W`](W) writer structure"] +impl crate::Writable for PAD120_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD120 to value 0x02"] +impl crate::Resettable for PAD120_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad13.rs b/esp32p4/src/lp_io_mux/pad13.rs new file mode 100644 index 0000000000..a200e7bd17 --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad13.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD13` reader"] +pub type R = crate::R; +#[doc = "Register `PAD13` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD13_DRV` reader - Reserved"] +pub type REG_PAD13_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD13_DRV` writer - Reserved"] +pub type REG_PAD13_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD13_RDE` reader - Reserved"] +pub type REG_PAD13_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD13_RDE` writer - Reserved"] +pub type REG_PAD13_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD13_RUE` reader - Reserved"] +pub type REG_PAD13_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD13_RUE` writer - Reserved"] +pub type REG_PAD13_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD13_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD13_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD13_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD13_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD13_FUN_SEL` reader - function sel"] +pub type REG_PAD13_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD13_FUN_SEL` writer - function sel"] +pub type REG_PAD13_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD13_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD13_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD13_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD13_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD13_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD13_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD13_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD13_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD13_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD13_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD13_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD13_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD13_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD13_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD13_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD13_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD13_FILTER_EN` reader - need des"] +pub type REG_PAD13_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD13_FILTER_EN` writer - need des"] +pub type REG_PAD13_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad13_drv(&self) -> REG_PAD13_DRV_R { + REG_PAD13_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad13_rde(&self) -> REG_PAD13_RDE_R { + REG_PAD13_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad13_rue(&self) -> REG_PAD13_RUE_R { + REG_PAD13_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad13_mux_sel(&self) -> REG_PAD13_MUX_SEL_R { + REG_PAD13_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad13_fun_sel(&self) -> REG_PAD13_FUN_SEL_R { + REG_PAD13_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad13_slp_sel(&self) -> REG_PAD13_SLP_SEL_R { + REG_PAD13_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad13_slp_ie(&self) -> REG_PAD13_SLP_IE_R { + REG_PAD13_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad13_slp_oe(&self) -> REG_PAD13_SLP_OE_R { + REG_PAD13_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad13_fun_ie(&self) -> REG_PAD13_FUN_IE_R { + REG_PAD13_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad13_filter_en(&self) -> REG_PAD13_FILTER_EN_R { + REG_PAD13_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD13") + .field( + "reg_pad13_drv", + &format_args!("{}", self.reg_pad13_drv().bits()), + ) + .field( + "reg_pad13_rde", + &format_args!("{}", self.reg_pad13_rde().bit()), + ) + .field( + "reg_pad13_rue", + &format_args!("{}", self.reg_pad13_rue().bit()), + ) + .field( + "reg_pad13_mux_sel", + &format_args!("{}", self.reg_pad13_mux_sel().bit()), + ) + .field( + "reg_pad13_fun_sel", + &format_args!("{}", self.reg_pad13_fun_sel().bits()), + ) + .field( + "reg_pad13_slp_sel", + &format_args!("{}", self.reg_pad13_slp_sel().bit()), + ) + .field( + "reg_pad13_slp_ie", + &format_args!("{}", self.reg_pad13_slp_ie().bit()), + ) + .field( + "reg_pad13_slp_oe", + &format_args!("{}", self.reg_pad13_slp_oe().bit()), + ) + .field( + "reg_pad13_fun_ie", + &format_args!("{}", self.reg_pad13_fun_ie().bit()), + ) + .field( + "reg_pad13_filter_en", + &format_args!("{}", self.reg_pad13_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad13_drv(&mut self) -> REG_PAD13_DRV_W { + REG_PAD13_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad13_rde(&mut self) -> REG_PAD13_RDE_W { + REG_PAD13_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad13_rue(&mut self) -> REG_PAD13_RUE_W { + REG_PAD13_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad13_mux_sel(&mut self) -> REG_PAD13_MUX_SEL_W { + REG_PAD13_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad13_fun_sel(&mut self) -> REG_PAD13_FUN_SEL_W { + REG_PAD13_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad13_slp_sel(&mut self) -> REG_PAD13_SLP_SEL_W { + REG_PAD13_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad13_slp_ie(&mut self) -> REG_PAD13_SLP_IE_W { + REG_PAD13_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad13_slp_oe(&mut self) -> REG_PAD13_SLP_OE_W { + REG_PAD13_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad13_fun_ie(&mut self) -> REG_PAD13_FUN_IE_W { + REG_PAD13_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad13_filter_en(&mut self) -> REG_PAD13_FILTER_EN_W { + REG_PAD13_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD13_SPEC; +impl crate::RegisterSpec for PAD13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad13::R`](R) reader structure"] +impl crate::Readable for PAD13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad13::W`](W) writer structure"] +impl crate::Writable for PAD13_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD13 to value 0x02"] +impl crate::Resettable for PAD13_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad14.rs b/esp32p4/src/lp_io_mux/pad14.rs new file mode 100644 index 0000000000..c6edb7ab7c --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad14.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD14` reader"] +pub type R = crate::R; +#[doc = "Register `PAD14` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD14_DRV` reader - Reserved"] +pub type REG_PAD14_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD14_DRV` writer - Reserved"] +pub type REG_PAD14_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD14_RDE` reader - Reserved"] +pub type REG_PAD14_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD14_RDE` writer - Reserved"] +pub type REG_PAD14_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD14_RUE` reader - Reserved"] +pub type REG_PAD14_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD14_RUE` writer - Reserved"] +pub type REG_PAD14_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD14_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD14_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD14_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD14_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD14_FUN_SEL` reader - function sel"] +pub type REG_PAD14_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD14_FUN_SEL` writer - function sel"] +pub type REG_PAD14_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD14_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD14_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD14_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD14_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD14_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD14_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD14_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD14_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD14_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD14_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD14_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD14_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD14_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD14_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD14_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD14_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD14_FILTER_EN` reader - need des"] +pub type REG_PAD14_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD14_FILTER_EN` writer - need des"] +pub type REG_PAD14_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad14_drv(&self) -> REG_PAD14_DRV_R { + REG_PAD14_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad14_rde(&self) -> REG_PAD14_RDE_R { + REG_PAD14_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad14_rue(&self) -> REG_PAD14_RUE_R { + REG_PAD14_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad14_mux_sel(&self) -> REG_PAD14_MUX_SEL_R { + REG_PAD14_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad14_fun_sel(&self) -> REG_PAD14_FUN_SEL_R { + REG_PAD14_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad14_slp_sel(&self) -> REG_PAD14_SLP_SEL_R { + REG_PAD14_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad14_slp_ie(&self) -> REG_PAD14_SLP_IE_R { + REG_PAD14_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad14_slp_oe(&self) -> REG_PAD14_SLP_OE_R { + REG_PAD14_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad14_fun_ie(&self) -> REG_PAD14_FUN_IE_R { + REG_PAD14_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad14_filter_en(&self) -> REG_PAD14_FILTER_EN_R { + REG_PAD14_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD14") + .field( + "reg_pad14_drv", + &format_args!("{}", self.reg_pad14_drv().bits()), + ) + .field( + "reg_pad14_rde", + &format_args!("{}", self.reg_pad14_rde().bit()), + ) + .field( + "reg_pad14_rue", + &format_args!("{}", self.reg_pad14_rue().bit()), + ) + .field( + "reg_pad14_mux_sel", + &format_args!("{}", self.reg_pad14_mux_sel().bit()), + ) + .field( + "reg_pad14_fun_sel", + &format_args!("{}", self.reg_pad14_fun_sel().bits()), + ) + .field( + "reg_pad14_slp_sel", + &format_args!("{}", self.reg_pad14_slp_sel().bit()), + ) + .field( + "reg_pad14_slp_ie", + &format_args!("{}", self.reg_pad14_slp_ie().bit()), + ) + .field( + "reg_pad14_slp_oe", + &format_args!("{}", self.reg_pad14_slp_oe().bit()), + ) + .field( + "reg_pad14_fun_ie", + &format_args!("{}", self.reg_pad14_fun_ie().bit()), + ) + .field( + "reg_pad14_filter_en", + &format_args!("{}", self.reg_pad14_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad14_drv(&mut self) -> REG_PAD14_DRV_W { + REG_PAD14_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad14_rde(&mut self) -> REG_PAD14_RDE_W { + REG_PAD14_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad14_rue(&mut self) -> REG_PAD14_RUE_W { + REG_PAD14_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad14_mux_sel(&mut self) -> REG_PAD14_MUX_SEL_W { + REG_PAD14_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad14_fun_sel(&mut self) -> REG_PAD14_FUN_SEL_W { + REG_PAD14_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad14_slp_sel(&mut self) -> REG_PAD14_SLP_SEL_W { + REG_PAD14_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad14_slp_ie(&mut self) -> REG_PAD14_SLP_IE_W { + REG_PAD14_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad14_slp_oe(&mut self) -> REG_PAD14_SLP_OE_W { + REG_PAD14_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad14_fun_ie(&mut self) -> REG_PAD14_FUN_IE_W { + REG_PAD14_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad14_filter_en(&mut self) -> REG_PAD14_FILTER_EN_W { + REG_PAD14_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD14_SPEC; +impl crate::RegisterSpec for PAD14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad14::R`](R) reader structure"] +impl crate::Readable for PAD14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad14::W`](W) writer structure"] +impl crate::Writable for PAD14_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD14 to value 0x02"] +impl crate::Resettable for PAD14_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad15.rs b/esp32p4/src/lp_io_mux/pad15.rs new file mode 100644 index 0000000000..5c04299501 --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad15.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD15` reader"] +pub type R = crate::R; +#[doc = "Register `PAD15` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD15_DRV` reader - Reserved"] +pub type REG_PAD15_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD15_DRV` writer - Reserved"] +pub type REG_PAD15_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD15_RDE` reader - Reserved"] +pub type REG_PAD15_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD15_RDE` writer - Reserved"] +pub type REG_PAD15_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD15_RUE` reader - Reserved"] +pub type REG_PAD15_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD15_RUE` writer - Reserved"] +pub type REG_PAD15_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD15_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD15_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD15_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD15_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD15_FUN_SEL` reader - function sel"] +pub type REG_PAD15_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD15_FUN_SEL` writer - function sel"] +pub type REG_PAD15_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD15_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD15_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD15_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD15_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD15_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD15_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD15_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD15_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD15_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD15_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD15_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD15_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD15_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD15_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD15_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD15_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD15_FILTER_EN` reader - need des"] +pub type REG_PAD15_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD15_FILTER_EN` writer - need des"] +pub type REG_PAD15_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad15_drv(&self) -> REG_PAD15_DRV_R { + REG_PAD15_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad15_rde(&self) -> REG_PAD15_RDE_R { + REG_PAD15_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad15_rue(&self) -> REG_PAD15_RUE_R { + REG_PAD15_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad15_mux_sel(&self) -> REG_PAD15_MUX_SEL_R { + REG_PAD15_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad15_fun_sel(&self) -> REG_PAD15_FUN_SEL_R { + REG_PAD15_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad15_slp_sel(&self) -> REG_PAD15_SLP_SEL_R { + REG_PAD15_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad15_slp_ie(&self) -> REG_PAD15_SLP_IE_R { + REG_PAD15_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad15_slp_oe(&self) -> REG_PAD15_SLP_OE_R { + REG_PAD15_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad15_fun_ie(&self) -> REG_PAD15_FUN_IE_R { + REG_PAD15_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad15_filter_en(&self) -> REG_PAD15_FILTER_EN_R { + REG_PAD15_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD15") + .field( + "reg_pad15_drv", + &format_args!("{}", self.reg_pad15_drv().bits()), + ) + .field( + "reg_pad15_rde", + &format_args!("{}", self.reg_pad15_rde().bit()), + ) + .field( + "reg_pad15_rue", + &format_args!("{}", self.reg_pad15_rue().bit()), + ) + .field( + "reg_pad15_mux_sel", + &format_args!("{}", self.reg_pad15_mux_sel().bit()), + ) + .field( + "reg_pad15_fun_sel", + &format_args!("{}", self.reg_pad15_fun_sel().bits()), + ) + .field( + "reg_pad15_slp_sel", + &format_args!("{}", self.reg_pad15_slp_sel().bit()), + ) + .field( + "reg_pad15_slp_ie", + &format_args!("{}", self.reg_pad15_slp_ie().bit()), + ) + .field( + "reg_pad15_slp_oe", + &format_args!("{}", self.reg_pad15_slp_oe().bit()), + ) + .field( + "reg_pad15_fun_ie", + &format_args!("{}", self.reg_pad15_fun_ie().bit()), + ) + .field( + "reg_pad15_filter_en", + &format_args!("{}", self.reg_pad15_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad15_drv(&mut self) -> REG_PAD15_DRV_W { + REG_PAD15_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad15_rde(&mut self) -> REG_PAD15_RDE_W { + REG_PAD15_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad15_rue(&mut self) -> REG_PAD15_RUE_W { + REG_PAD15_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad15_mux_sel(&mut self) -> REG_PAD15_MUX_SEL_W { + REG_PAD15_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad15_fun_sel(&mut self) -> REG_PAD15_FUN_SEL_W { + REG_PAD15_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad15_slp_sel(&mut self) -> REG_PAD15_SLP_SEL_W { + REG_PAD15_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad15_slp_ie(&mut self) -> REG_PAD15_SLP_IE_W { + REG_PAD15_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad15_slp_oe(&mut self) -> REG_PAD15_SLP_OE_W { + REG_PAD15_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad15_fun_ie(&mut self) -> REG_PAD15_FUN_IE_W { + REG_PAD15_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad15_filter_en(&mut self) -> REG_PAD15_FILTER_EN_W { + REG_PAD15_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD15_SPEC; +impl crate::RegisterSpec for PAD15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad15::R`](R) reader structure"] +impl crate::Readable for PAD15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad15::W`](W) writer structure"] +impl crate::Writable for PAD15_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD15 to value 0x02"] +impl crate::Resettable for PAD15_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad2.rs b/esp32p4/src/lp_io_mux/pad2.rs new file mode 100644 index 0000000000..91542388f6 --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad2.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD2` reader"] +pub type R = crate::R; +#[doc = "Register `PAD2` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD2_DRV` reader - Reserved"] +pub type REG_PAD2_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD2_DRV` writer - Reserved"] +pub type REG_PAD2_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD2_RDE` reader - Reserved"] +pub type REG_PAD2_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD2_RDE` writer - Reserved"] +pub type REG_PAD2_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD2_RUE` reader - Reserved"] +pub type REG_PAD2_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD2_RUE` writer - Reserved"] +pub type REG_PAD2_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD2_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD2_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD2_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD2_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD2_FUN_SEL` reader - function sel"] +pub type REG_PAD2_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD2_FUN_SEL` writer - function sel"] +pub type REG_PAD2_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD2_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD2_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD2_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD2_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD2_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD2_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD2_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD2_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD2_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD2_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD2_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD2_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD2_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD2_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD2_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD2_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD2_FILTER_EN` reader - need des"] +pub type REG_PAD2_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD2_FILTER_EN` writer - need des"] +pub type REG_PAD2_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad2_drv(&self) -> REG_PAD2_DRV_R { + REG_PAD2_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad2_rde(&self) -> REG_PAD2_RDE_R { + REG_PAD2_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad2_rue(&self) -> REG_PAD2_RUE_R { + REG_PAD2_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad2_mux_sel(&self) -> REG_PAD2_MUX_SEL_R { + REG_PAD2_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad2_fun_sel(&self) -> REG_PAD2_FUN_SEL_R { + REG_PAD2_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad2_slp_sel(&self) -> REG_PAD2_SLP_SEL_R { + REG_PAD2_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad2_slp_ie(&self) -> REG_PAD2_SLP_IE_R { + REG_PAD2_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad2_slp_oe(&self) -> REG_PAD2_SLP_OE_R { + REG_PAD2_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad2_fun_ie(&self) -> REG_PAD2_FUN_IE_R { + REG_PAD2_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad2_filter_en(&self) -> REG_PAD2_FILTER_EN_R { + REG_PAD2_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD2") + .field( + "reg_pad2_drv", + &format_args!("{}", self.reg_pad2_drv().bits()), + ) + .field( + "reg_pad2_rde", + &format_args!("{}", self.reg_pad2_rde().bit()), + ) + .field( + "reg_pad2_rue", + &format_args!("{}", self.reg_pad2_rue().bit()), + ) + .field( + "reg_pad2_mux_sel", + &format_args!("{}", self.reg_pad2_mux_sel().bit()), + ) + .field( + "reg_pad2_fun_sel", + &format_args!("{}", self.reg_pad2_fun_sel().bits()), + ) + .field( + "reg_pad2_slp_sel", + &format_args!("{}", self.reg_pad2_slp_sel().bit()), + ) + .field( + "reg_pad2_slp_ie", + &format_args!("{}", self.reg_pad2_slp_ie().bit()), + ) + .field( + "reg_pad2_slp_oe", + &format_args!("{}", self.reg_pad2_slp_oe().bit()), + ) + .field( + "reg_pad2_fun_ie", + &format_args!("{}", self.reg_pad2_fun_ie().bit()), + ) + .field( + "reg_pad2_filter_en", + &format_args!("{}", self.reg_pad2_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad2_drv(&mut self) -> REG_PAD2_DRV_W { + REG_PAD2_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad2_rde(&mut self) -> REG_PAD2_RDE_W { + REG_PAD2_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad2_rue(&mut self) -> REG_PAD2_RUE_W { + REG_PAD2_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad2_mux_sel(&mut self) -> REG_PAD2_MUX_SEL_W { + REG_PAD2_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad2_fun_sel(&mut self) -> REG_PAD2_FUN_SEL_W { + REG_PAD2_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad2_slp_sel(&mut self) -> REG_PAD2_SLP_SEL_W { + REG_PAD2_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad2_slp_ie(&mut self) -> REG_PAD2_SLP_IE_W { + REG_PAD2_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad2_slp_oe(&mut self) -> REG_PAD2_SLP_OE_W { + REG_PAD2_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad2_fun_ie(&mut self) -> REG_PAD2_FUN_IE_W { + REG_PAD2_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad2_filter_en(&mut self) -> REG_PAD2_FILTER_EN_W { + REG_PAD2_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD2_SPEC; +impl crate::RegisterSpec for PAD2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad2::R`](R) reader structure"] +impl crate::Readable for PAD2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad2::W`](W) writer structure"] +impl crate::Writable for PAD2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD2 to value 0x02"] +impl crate::Resettable for PAD2_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad3.rs b/esp32p4/src/lp_io_mux/pad3.rs new file mode 100644 index 0000000000..5d5dad1fbd --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad3.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD3` reader"] +pub type R = crate::R; +#[doc = "Register `PAD3` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD3_DRV` reader - Reserved"] +pub type REG_PAD3_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD3_DRV` writer - Reserved"] +pub type REG_PAD3_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD3_RDE` reader - Reserved"] +pub type REG_PAD3_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD3_RDE` writer - Reserved"] +pub type REG_PAD3_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD3_RUE` reader - Reserved"] +pub type REG_PAD3_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD3_RUE` writer - Reserved"] +pub type REG_PAD3_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD3_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD3_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD3_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD3_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD3_FUN_SEL` reader - function sel"] +pub type REG_PAD3_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD3_FUN_SEL` writer - function sel"] +pub type REG_PAD3_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD3_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD3_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD3_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD3_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD3_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD3_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD3_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD3_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD3_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD3_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD3_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD3_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD3_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD3_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD3_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD3_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD3_FILTER_EN` reader - need des"] +pub type REG_PAD3_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD3_FILTER_EN` writer - need des"] +pub type REG_PAD3_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad3_drv(&self) -> REG_PAD3_DRV_R { + REG_PAD3_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad3_rde(&self) -> REG_PAD3_RDE_R { + REG_PAD3_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad3_rue(&self) -> REG_PAD3_RUE_R { + REG_PAD3_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad3_mux_sel(&self) -> REG_PAD3_MUX_SEL_R { + REG_PAD3_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad3_fun_sel(&self) -> REG_PAD3_FUN_SEL_R { + REG_PAD3_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad3_slp_sel(&self) -> REG_PAD3_SLP_SEL_R { + REG_PAD3_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad3_slp_ie(&self) -> REG_PAD3_SLP_IE_R { + REG_PAD3_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad3_slp_oe(&self) -> REG_PAD3_SLP_OE_R { + REG_PAD3_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad3_fun_ie(&self) -> REG_PAD3_FUN_IE_R { + REG_PAD3_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad3_filter_en(&self) -> REG_PAD3_FILTER_EN_R { + REG_PAD3_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD3") + .field( + "reg_pad3_drv", + &format_args!("{}", self.reg_pad3_drv().bits()), + ) + .field( + "reg_pad3_rde", + &format_args!("{}", self.reg_pad3_rde().bit()), + ) + .field( + "reg_pad3_rue", + &format_args!("{}", self.reg_pad3_rue().bit()), + ) + .field( + "reg_pad3_mux_sel", + &format_args!("{}", self.reg_pad3_mux_sel().bit()), + ) + .field( + "reg_pad3_fun_sel", + &format_args!("{}", self.reg_pad3_fun_sel().bits()), + ) + .field( + "reg_pad3_slp_sel", + &format_args!("{}", self.reg_pad3_slp_sel().bit()), + ) + .field( + "reg_pad3_slp_ie", + &format_args!("{}", self.reg_pad3_slp_ie().bit()), + ) + .field( + "reg_pad3_slp_oe", + &format_args!("{}", self.reg_pad3_slp_oe().bit()), + ) + .field( + "reg_pad3_fun_ie", + &format_args!("{}", self.reg_pad3_fun_ie().bit()), + ) + .field( + "reg_pad3_filter_en", + &format_args!("{}", self.reg_pad3_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad3_drv(&mut self) -> REG_PAD3_DRV_W { + REG_PAD3_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad3_rde(&mut self) -> REG_PAD3_RDE_W { + REG_PAD3_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad3_rue(&mut self) -> REG_PAD3_RUE_W { + REG_PAD3_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad3_mux_sel(&mut self) -> REG_PAD3_MUX_SEL_W { + REG_PAD3_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad3_fun_sel(&mut self) -> REG_PAD3_FUN_SEL_W { + REG_PAD3_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad3_slp_sel(&mut self) -> REG_PAD3_SLP_SEL_W { + REG_PAD3_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad3_slp_ie(&mut self) -> REG_PAD3_SLP_IE_W { + REG_PAD3_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad3_slp_oe(&mut self) -> REG_PAD3_SLP_OE_W { + REG_PAD3_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad3_fun_ie(&mut self) -> REG_PAD3_FUN_IE_W { + REG_PAD3_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad3_filter_en(&mut self) -> REG_PAD3_FILTER_EN_W { + REG_PAD3_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD3_SPEC; +impl crate::RegisterSpec for PAD3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad3::R`](R) reader structure"] +impl crate::Readable for PAD3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad3::W`](W) writer structure"] +impl crate::Writable for PAD3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD3 to value 0x02"] +impl crate::Resettable for PAD3_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad4.rs b/esp32p4/src/lp_io_mux/pad4.rs new file mode 100644 index 0000000000..7a19539c5c --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad4.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD4` reader"] +pub type R = crate::R; +#[doc = "Register `PAD4` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD4_DRV` reader - Reserved"] +pub type REG_PAD4_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD4_DRV` writer - Reserved"] +pub type REG_PAD4_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD4_RDE` reader - Reserved"] +pub type REG_PAD4_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD4_RDE` writer - Reserved"] +pub type REG_PAD4_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD4_RUE` reader - Reserved"] +pub type REG_PAD4_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD4_RUE` writer - Reserved"] +pub type REG_PAD4_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD4_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD4_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD4_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD4_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD4_FUN_SEL` reader - function sel"] +pub type REG_PAD4_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD4_FUN_SEL` writer - function sel"] +pub type REG_PAD4_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD4_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD4_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD4_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD4_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD4_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD4_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD4_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD4_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD4_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD4_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD4_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD4_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD4_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD4_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD4_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD4_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD4_FILTER_EN` reader - need des"] +pub type REG_PAD4_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD4_FILTER_EN` writer - need des"] +pub type REG_PAD4_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad4_drv(&self) -> REG_PAD4_DRV_R { + REG_PAD4_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad4_rde(&self) -> REG_PAD4_RDE_R { + REG_PAD4_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad4_rue(&self) -> REG_PAD4_RUE_R { + REG_PAD4_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad4_mux_sel(&self) -> REG_PAD4_MUX_SEL_R { + REG_PAD4_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad4_fun_sel(&self) -> REG_PAD4_FUN_SEL_R { + REG_PAD4_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad4_slp_sel(&self) -> REG_PAD4_SLP_SEL_R { + REG_PAD4_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad4_slp_ie(&self) -> REG_PAD4_SLP_IE_R { + REG_PAD4_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad4_slp_oe(&self) -> REG_PAD4_SLP_OE_R { + REG_PAD4_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad4_fun_ie(&self) -> REG_PAD4_FUN_IE_R { + REG_PAD4_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad4_filter_en(&self) -> REG_PAD4_FILTER_EN_R { + REG_PAD4_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD4") + .field( + "reg_pad4_drv", + &format_args!("{}", self.reg_pad4_drv().bits()), + ) + .field( + "reg_pad4_rde", + &format_args!("{}", self.reg_pad4_rde().bit()), + ) + .field( + "reg_pad4_rue", + &format_args!("{}", self.reg_pad4_rue().bit()), + ) + .field( + "reg_pad4_mux_sel", + &format_args!("{}", self.reg_pad4_mux_sel().bit()), + ) + .field( + "reg_pad4_fun_sel", + &format_args!("{}", self.reg_pad4_fun_sel().bits()), + ) + .field( + "reg_pad4_slp_sel", + &format_args!("{}", self.reg_pad4_slp_sel().bit()), + ) + .field( + "reg_pad4_slp_ie", + &format_args!("{}", self.reg_pad4_slp_ie().bit()), + ) + .field( + "reg_pad4_slp_oe", + &format_args!("{}", self.reg_pad4_slp_oe().bit()), + ) + .field( + "reg_pad4_fun_ie", + &format_args!("{}", self.reg_pad4_fun_ie().bit()), + ) + .field( + "reg_pad4_filter_en", + &format_args!("{}", self.reg_pad4_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad4_drv(&mut self) -> REG_PAD4_DRV_W { + REG_PAD4_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad4_rde(&mut self) -> REG_PAD4_RDE_W { + REG_PAD4_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad4_rue(&mut self) -> REG_PAD4_RUE_W { + REG_PAD4_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad4_mux_sel(&mut self) -> REG_PAD4_MUX_SEL_W { + REG_PAD4_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad4_fun_sel(&mut self) -> REG_PAD4_FUN_SEL_W { + REG_PAD4_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad4_slp_sel(&mut self) -> REG_PAD4_SLP_SEL_W { + REG_PAD4_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad4_slp_ie(&mut self) -> REG_PAD4_SLP_IE_W { + REG_PAD4_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad4_slp_oe(&mut self) -> REG_PAD4_SLP_OE_W { + REG_PAD4_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad4_fun_ie(&mut self) -> REG_PAD4_FUN_IE_W { + REG_PAD4_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad4_filter_en(&mut self) -> REG_PAD4_FILTER_EN_W { + REG_PAD4_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD4_SPEC; +impl crate::RegisterSpec for PAD4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad4::R`](R) reader structure"] +impl crate::Readable for PAD4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad4::W`](W) writer structure"] +impl crate::Writable for PAD4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD4 to value 0x02"] +impl crate::Resettable for PAD4_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad5.rs b/esp32p4/src/lp_io_mux/pad5.rs new file mode 100644 index 0000000000..a6846b6cea --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad5.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD5` reader"] +pub type R = crate::R; +#[doc = "Register `PAD5` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD5_DRV` reader - Reserved"] +pub type REG_PAD5_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD5_DRV` writer - Reserved"] +pub type REG_PAD5_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD5_RDE` reader - Reserved"] +pub type REG_PAD5_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD5_RDE` writer - Reserved"] +pub type REG_PAD5_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD5_RUE` reader - Reserved"] +pub type REG_PAD5_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD5_RUE` writer - Reserved"] +pub type REG_PAD5_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD5_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD5_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD5_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD5_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD5_FUN_SEL` reader - function sel"] +pub type REG_PAD5_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD5_FUN_SEL` writer - function sel"] +pub type REG_PAD5_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD5_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD5_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD5_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD5_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD5_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD5_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD5_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD5_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD5_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD5_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD5_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD5_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD5_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD5_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD5_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD5_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD5_FILTER_EN` reader - need des"] +pub type REG_PAD5_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD5_FILTER_EN` writer - need des"] +pub type REG_PAD5_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad5_drv(&self) -> REG_PAD5_DRV_R { + REG_PAD5_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad5_rde(&self) -> REG_PAD5_RDE_R { + REG_PAD5_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad5_rue(&self) -> REG_PAD5_RUE_R { + REG_PAD5_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad5_mux_sel(&self) -> REG_PAD5_MUX_SEL_R { + REG_PAD5_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad5_fun_sel(&self) -> REG_PAD5_FUN_SEL_R { + REG_PAD5_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad5_slp_sel(&self) -> REG_PAD5_SLP_SEL_R { + REG_PAD5_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad5_slp_ie(&self) -> REG_PAD5_SLP_IE_R { + REG_PAD5_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad5_slp_oe(&self) -> REG_PAD5_SLP_OE_R { + REG_PAD5_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad5_fun_ie(&self) -> REG_PAD5_FUN_IE_R { + REG_PAD5_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad5_filter_en(&self) -> REG_PAD5_FILTER_EN_R { + REG_PAD5_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD5") + .field( + "reg_pad5_drv", + &format_args!("{}", self.reg_pad5_drv().bits()), + ) + .field( + "reg_pad5_rde", + &format_args!("{}", self.reg_pad5_rde().bit()), + ) + .field( + "reg_pad5_rue", + &format_args!("{}", self.reg_pad5_rue().bit()), + ) + .field( + "reg_pad5_mux_sel", + &format_args!("{}", self.reg_pad5_mux_sel().bit()), + ) + .field( + "reg_pad5_fun_sel", + &format_args!("{}", self.reg_pad5_fun_sel().bits()), + ) + .field( + "reg_pad5_slp_sel", + &format_args!("{}", self.reg_pad5_slp_sel().bit()), + ) + .field( + "reg_pad5_slp_ie", + &format_args!("{}", self.reg_pad5_slp_ie().bit()), + ) + .field( + "reg_pad5_slp_oe", + &format_args!("{}", self.reg_pad5_slp_oe().bit()), + ) + .field( + "reg_pad5_fun_ie", + &format_args!("{}", self.reg_pad5_fun_ie().bit()), + ) + .field( + "reg_pad5_filter_en", + &format_args!("{}", self.reg_pad5_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad5_drv(&mut self) -> REG_PAD5_DRV_W { + REG_PAD5_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad5_rde(&mut self) -> REG_PAD5_RDE_W { + REG_PAD5_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad5_rue(&mut self) -> REG_PAD5_RUE_W { + REG_PAD5_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad5_mux_sel(&mut self) -> REG_PAD5_MUX_SEL_W { + REG_PAD5_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad5_fun_sel(&mut self) -> REG_PAD5_FUN_SEL_W { + REG_PAD5_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad5_slp_sel(&mut self) -> REG_PAD5_SLP_SEL_W { + REG_PAD5_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad5_slp_ie(&mut self) -> REG_PAD5_SLP_IE_W { + REG_PAD5_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad5_slp_oe(&mut self) -> REG_PAD5_SLP_OE_W { + REG_PAD5_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad5_fun_ie(&mut self) -> REG_PAD5_FUN_IE_W { + REG_PAD5_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad5_filter_en(&mut self) -> REG_PAD5_FILTER_EN_W { + REG_PAD5_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD5_SPEC; +impl crate::RegisterSpec for PAD5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad5::R`](R) reader structure"] +impl crate::Readable for PAD5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad5::W`](W) writer structure"] +impl crate::Writable for PAD5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD5 to value 0x02"] +impl crate::Resettable for PAD5_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad6.rs b/esp32p4/src/lp_io_mux/pad6.rs new file mode 100644 index 0000000000..b38ff640b0 --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad6.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD6` reader"] +pub type R = crate::R; +#[doc = "Register `PAD6` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD6_DRV` reader - Reserved"] +pub type REG_PAD6_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD6_DRV` writer - Reserved"] +pub type REG_PAD6_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD6_RDE` reader - Reserved"] +pub type REG_PAD6_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD6_RDE` writer - Reserved"] +pub type REG_PAD6_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD6_RUE` reader - Reserved"] +pub type REG_PAD6_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD6_RUE` writer - Reserved"] +pub type REG_PAD6_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD6_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD6_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD6_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD6_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD6_FUN_SEL` reader - function sel"] +pub type REG_PAD6_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD6_FUN_SEL` writer - function sel"] +pub type REG_PAD6_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD6_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD6_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD6_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD6_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD6_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD6_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD6_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD6_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD6_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD6_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD6_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD6_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD6_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD6_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD6_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD6_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD6_FILTER_EN` reader - need des"] +pub type REG_PAD6_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD6_FILTER_EN` writer - need des"] +pub type REG_PAD6_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad6_drv(&self) -> REG_PAD6_DRV_R { + REG_PAD6_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad6_rde(&self) -> REG_PAD6_RDE_R { + REG_PAD6_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad6_rue(&self) -> REG_PAD6_RUE_R { + REG_PAD6_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad6_mux_sel(&self) -> REG_PAD6_MUX_SEL_R { + REG_PAD6_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad6_fun_sel(&self) -> REG_PAD6_FUN_SEL_R { + REG_PAD6_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad6_slp_sel(&self) -> REG_PAD6_SLP_SEL_R { + REG_PAD6_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad6_slp_ie(&self) -> REG_PAD6_SLP_IE_R { + REG_PAD6_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad6_slp_oe(&self) -> REG_PAD6_SLP_OE_R { + REG_PAD6_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad6_fun_ie(&self) -> REG_PAD6_FUN_IE_R { + REG_PAD6_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad6_filter_en(&self) -> REG_PAD6_FILTER_EN_R { + REG_PAD6_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD6") + .field( + "reg_pad6_drv", + &format_args!("{}", self.reg_pad6_drv().bits()), + ) + .field( + "reg_pad6_rde", + &format_args!("{}", self.reg_pad6_rde().bit()), + ) + .field( + "reg_pad6_rue", + &format_args!("{}", self.reg_pad6_rue().bit()), + ) + .field( + "reg_pad6_mux_sel", + &format_args!("{}", self.reg_pad6_mux_sel().bit()), + ) + .field( + "reg_pad6_fun_sel", + &format_args!("{}", self.reg_pad6_fun_sel().bits()), + ) + .field( + "reg_pad6_slp_sel", + &format_args!("{}", self.reg_pad6_slp_sel().bit()), + ) + .field( + "reg_pad6_slp_ie", + &format_args!("{}", self.reg_pad6_slp_ie().bit()), + ) + .field( + "reg_pad6_slp_oe", + &format_args!("{}", self.reg_pad6_slp_oe().bit()), + ) + .field( + "reg_pad6_fun_ie", + &format_args!("{}", self.reg_pad6_fun_ie().bit()), + ) + .field( + "reg_pad6_filter_en", + &format_args!("{}", self.reg_pad6_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad6_drv(&mut self) -> REG_PAD6_DRV_W { + REG_PAD6_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad6_rde(&mut self) -> REG_PAD6_RDE_W { + REG_PAD6_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad6_rue(&mut self) -> REG_PAD6_RUE_W { + REG_PAD6_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad6_mux_sel(&mut self) -> REG_PAD6_MUX_SEL_W { + REG_PAD6_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad6_fun_sel(&mut self) -> REG_PAD6_FUN_SEL_W { + REG_PAD6_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad6_slp_sel(&mut self) -> REG_PAD6_SLP_SEL_W { + REG_PAD6_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad6_slp_ie(&mut self) -> REG_PAD6_SLP_IE_W { + REG_PAD6_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad6_slp_oe(&mut self) -> REG_PAD6_SLP_OE_W { + REG_PAD6_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad6_fun_ie(&mut self) -> REG_PAD6_FUN_IE_W { + REG_PAD6_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad6_filter_en(&mut self) -> REG_PAD6_FILTER_EN_W { + REG_PAD6_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD6_SPEC; +impl crate::RegisterSpec for PAD6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad6::R`](R) reader structure"] +impl crate::Readable for PAD6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad6::W`](W) writer structure"] +impl crate::Writable for PAD6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD6 to value 0x02"] +impl crate::Resettable for PAD6_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad7.rs b/esp32p4/src/lp_io_mux/pad7.rs new file mode 100644 index 0000000000..2c516f38c3 --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad7.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD7` reader"] +pub type R = crate::R; +#[doc = "Register `PAD7` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD7_DRV` reader - Reserved"] +pub type REG_PAD7_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD7_DRV` writer - Reserved"] +pub type REG_PAD7_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD7_RDE` reader - Reserved"] +pub type REG_PAD7_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD7_RDE` writer - Reserved"] +pub type REG_PAD7_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD7_RUE` reader - Reserved"] +pub type REG_PAD7_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD7_RUE` writer - Reserved"] +pub type REG_PAD7_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD7_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD7_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD7_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD7_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD7_FUN_SEL` reader - function sel"] +pub type REG_PAD7_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD7_FUN_SEL` writer - function sel"] +pub type REG_PAD7_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD7_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD7_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD7_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD7_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD7_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD7_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD7_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD7_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD7_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD7_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD7_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD7_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD7_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD7_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD7_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD7_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD7_FILTER_EN` reader - need des"] +pub type REG_PAD7_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD7_FILTER_EN` writer - need des"] +pub type REG_PAD7_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad7_drv(&self) -> REG_PAD7_DRV_R { + REG_PAD7_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad7_rde(&self) -> REG_PAD7_RDE_R { + REG_PAD7_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad7_rue(&self) -> REG_PAD7_RUE_R { + REG_PAD7_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad7_mux_sel(&self) -> REG_PAD7_MUX_SEL_R { + REG_PAD7_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad7_fun_sel(&self) -> REG_PAD7_FUN_SEL_R { + REG_PAD7_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad7_slp_sel(&self) -> REG_PAD7_SLP_SEL_R { + REG_PAD7_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad7_slp_ie(&self) -> REG_PAD7_SLP_IE_R { + REG_PAD7_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad7_slp_oe(&self) -> REG_PAD7_SLP_OE_R { + REG_PAD7_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad7_fun_ie(&self) -> REG_PAD7_FUN_IE_R { + REG_PAD7_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad7_filter_en(&self) -> REG_PAD7_FILTER_EN_R { + REG_PAD7_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD7") + .field( + "reg_pad7_drv", + &format_args!("{}", self.reg_pad7_drv().bits()), + ) + .field( + "reg_pad7_rde", + &format_args!("{}", self.reg_pad7_rde().bit()), + ) + .field( + "reg_pad7_rue", + &format_args!("{}", self.reg_pad7_rue().bit()), + ) + .field( + "reg_pad7_mux_sel", + &format_args!("{}", self.reg_pad7_mux_sel().bit()), + ) + .field( + "reg_pad7_fun_sel", + &format_args!("{}", self.reg_pad7_fun_sel().bits()), + ) + .field( + "reg_pad7_slp_sel", + &format_args!("{}", self.reg_pad7_slp_sel().bit()), + ) + .field( + "reg_pad7_slp_ie", + &format_args!("{}", self.reg_pad7_slp_ie().bit()), + ) + .field( + "reg_pad7_slp_oe", + &format_args!("{}", self.reg_pad7_slp_oe().bit()), + ) + .field( + "reg_pad7_fun_ie", + &format_args!("{}", self.reg_pad7_fun_ie().bit()), + ) + .field( + "reg_pad7_filter_en", + &format_args!("{}", self.reg_pad7_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad7_drv(&mut self) -> REG_PAD7_DRV_W { + REG_PAD7_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad7_rde(&mut self) -> REG_PAD7_RDE_W { + REG_PAD7_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad7_rue(&mut self) -> REG_PAD7_RUE_W { + REG_PAD7_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad7_mux_sel(&mut self) -> REG_PAD7_MUX_SEL_W { + REG_PAD7_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad7_fun_sel(&mut self) -> REG_PAD7_FUN_SEL_W { + REG_PAD7_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad7_slp_sel(&mut self) -> REG_PAD7_SLP_SEL_W { + REG_PAD7_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad7_slp_ie(&mut self) -> REG_PAD7_SLP_IE_W { + REG_PAD7_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad7_slp_oe(&mut self) -> REG_PAD7_SLP_OE_W { + REG_PAD7_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad7_fun_ie(&mut self) -> REG_PAD7_FUN_IE_W { + REG_PAD7_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad7_filter_en(&mut self) -> REG_PAD7_FILTER_EN_W { + REG_PAD7_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD7_SPEC; +impl crate::RegisterSpec for PAD7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad7::R`](R) reader structure"] +impl crate::Readable for PAD7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad7::W`](W) writer structure"] +impl crate::Writable for PAD7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD7 to value 0x02"] +impl crate::Resettable for PAD7_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad8.rs b/esp32p4/src/lp_io_mux/pad8.rs new file mode 100644 index 0000000000..88e22eaed2 --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad8.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD8` reader"] +pub type R = crate::R; +#[doc = "Register `PAD8` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD8_DRV` reader - Reserved"] +pub type REG_PAD8_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD8_DRV` writer - Reserved"] +pub type REG_PAD8_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD8_RDE` reader - Reserved"] +pub type REG_PAD8_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD8_RDE` writer - Reserved"] +pub type REG_PAD8_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD8_RUE` reader - Reserved"] +pub type REG_PAD8_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD8_RUE` writer - Reserved"] +pub type REG_PAD8_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD8_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD8_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD8_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD8_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD8_FUN_SEL` reader - function sel"] +pub type REG_PAD8_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD8_FUN_SEL` writer - function sel"] +pub type REG_PAD8_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD8_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD8_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD8_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD8_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD8_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD8_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD8_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD8_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD8_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD8_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD8_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD8_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD8_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD8_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD8_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD8_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD8_FILTER_EN` reader - need des"] +pub type REG_PAD8_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD8_FILTER_EN` writer - need des"] +pub type REG_PAD8_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad8_drv(&self) -> REG_PAD8_DRV_R { + REG_PAD8_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad8_rde(&self) -> REG_PAD8_RDE_R { + REG_PAD8_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad8_rue(&self) -> REG_PAD8_RUE_R { + REG_PAD8_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad8_mux_sel(&self) -> REG_PAD8_MUX_SEL_R { + REG_PAD8_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad8_fun_sel(&self) -> REG_PAD8_FUN_SEL_R { + REG_PAD8_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad8_slp_sel(&self) -> REG_PAD8_SLP_SEL_R { + REG_PAD8_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad8_slp_ie(&self) -> REG_PAD8_SLP_IE_R { + REG_PAD8_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad8_slp_oe(&self) -> REG_PAD8_SLP_OE_R { + REG_PAD8_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad8_fun_ie(&self) -> REG_PAD8_FUN_IE_R { + REG_PAD8_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad8_filter_en(&self) -> REG_PAD8_FILTER_EN_R { + REG_PAD8_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD8") + .field( + "reg_pad8_drv", + &format_args!("{}", self.reg_pad8_drv().bits()), + ) + .field( + "reg_pad8_rde", + &format_args!("{}", self.reg_pad8_rde().bit()), + ) + .field( + "reg_pad8_rue", + &format_args!("{}", self.reg_pad8_rue().bit()), + ) + .field( + "reg_pad8_mux_sel", + &format_args!("{}", self.reg_pad8_mux_sel().bit()), + ) + .field( + "reg_pad8_fun_sel", + &format_args!("{}", self.reg_pad8_fun_sel().bits()), + ) + .field( + "reg_pad8_slp_sel", + &format_args!("{}", self.reg_pad8_slp_sel().bit()), + ) + .field( + "reg_pad8_slp_ie", + &format_args!("{}", self.reg_pad8_slp_ie().bit()), + ) + .field( + "reg_pad8_slp_oe", + &format_args!("{}", self.reg_pad8_slp_oe().bit()), + ) + .field( + "reg_pad8_fun_ie", + &format_args!("{}", self.reg_pad8_fun_ie().bit()), + ) + .field( + "reg_pad8_filter_en", + &format_args!("{}", self.reg_pad8_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad8_drv(&mut self) -> REG_PAD8_DRV_W { + REG_PAD8_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad8_rde(&mut self) -> REG_PAD8_RDE_W { + REG_PAD8_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad8_rue(&mut self) -> REG_PAD8_RUE_W { + REG_PAD8_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad8_mux_sel(&mut self) -> REG_PAD8_MUX_SEL_W { + REG_PAD8_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad8_fun_sel(&mut self) -> REG_PAD8_FUN_SEL_W { + REG_PAD8_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad8_slp_sel(&mut self) -> REG_PAD8_SLP_SEL_W { + REG_PAD8_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad8_slp_ie(&mut self) -> REG_PAD8_SLP_IE_W { + REG_PAD8_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad8_slp_oe(&mut self) -> REG_PAD8_SLP_OE_W { + REG_PAD8_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad8_fun_ie(&mut self) -> REG_PAD8_FUN_IE_W { + REG_PAD8_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad8_filter_en(&mut self) -> REG_PAD8_FILTER_EN_W { + REG_PAD8_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD8_SPEC; +impl crate::RegisterSpec for PAD8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad8::R`](R) reader structure"] +impl crate::Readable for PAD8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad8::W`](W) writer structure"] +impl crate::Writable for PAD8_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD8 to value 0x02"] +impl crate::Resettable for PAD8_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/pad9.rs b/esp32p4/src/lp_io_mux/pad9.rs new file mode 100644 index 0000000000..b9d24094a5 --- /dev/null +++ b/esp32p4/src/lp_io_mux/pad9.rs @@ -0,0 +1,237 @@ +#[doc = "Register `PAD9` reader"] +pub type R = crate::R; +#[doc = "Register `PAD9` writer"] +pub type W = crate::W; +#[doc = "Field `REG_PAD9_DRV` reader - Reserved"] +pub type REG_PAD9_DRV_R = crate::FieldReader; +#[doc = "Field `REG_PAD9_DRV` writer - Reserved"] +pub type REG_PAD9_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD9_RDE` reader - Reserved"] +pub type REG_PAD9_RDE_R = crate::BitReader; +#[doc = "Field `REG_PAD9_RDE` writer - Reserved"] +pub type REG_PAD9_RDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD9_RUE` reader - Reserved"] +pub type REG_PAD9_RUE_R = crate::BitReader; +#[doc = "Field `REG_PAD9_RUE` writer - Reserved"] +pub type REG_PAD9_RUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD9_MUX_SEL` reader - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD9_MUX_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD9_MUX_SEL` writer - 1:use LP GPIO,0: use digital GPIO"] +pub type REG_PAD9_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD9_FUN_SEL` reader - function sel"] +pub type REG_PAD9_FUN_SEL_R = crate::FieldReader; +#[doc = "Field `REG_PAD9_FUN_SEL` writer - function sel"] +pub type REG_PAD9_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `REG_PAD9_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD9_SLP_SEL_R = crate::BitReader; +#[doc = "Field `REG_PAD9_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"] +pub type REG_PAD9_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD9_SLP_IE` reader - input enable in sleep mode"] +pub type REG_PAD9_SLP_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD9_SLP_IE` writer - input enable in sleep mode"] +pub type REG_PAD9_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD9_SLP_OE` reader - output enable in sleep mode"] +pub type REG_PAD9_SLP_OE_R = crate::BitReader; +#[doc = "Field `REG_PAD9_SLP_OE` writer - output enable in sleep mode"] +pub type REG_PAD9_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD9_FUN_IE` reader - input enable in work mode"] +pub type REG_PAD9_FUN_IE_R = crate::BitReader; +#[doc = "Field `REG_PAD9_FUN_IE` writer - input enable in work mode"] +pub type REG_PAD9_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REG_PAD9_FILTER_EN` reader - need des"] +pub type REG_PAD9_FILTER_EN_R = crate::BitReader; +#[doc = "Field `REG_PAD9_FILTER_EN` writer - need des"] +pub type REG_PAD9_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + pub fn reg_pad9_drv(&self) -> REG_PAD9_DRV_R { + REG_PAD9_DRV_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + pub fn reg_pad9_rde(&self) -> REG_PAD9_RDE_R { + REG_PAD9_RDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + pub fn reg_pad9_rue(&self) -> REG_PAD9_RUE_R { + REG_PAD9_RUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + pub fn reg_pad9_mux_sel(&self) -> REG_PAD9_MUX_SEL_R { + REG_PAD9_MUX_SEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + pub fn reg_pad9_fun_sel(&self) -> REG_PAD9_FUN_SEL_R { + REG_PAD9_FUN_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + pub fn reg_pad9_slp_sel(&self) -> REG_PAD9_SLP_SEL_R { + REG_PAD9_SLP_SEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + pub fn reg_pad9_slp_ie(&self) -> REG_PAD9_SLP_IE_R { + REG_PAD9_SLP_IE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + pub fn reg_pad9_slp_oe(&self) -> REG_PAD9_SLP_OE_R { + REG_PAD9_SLP_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + pub fn reg_pad9_fun_ie(&self) -> REG_PAD9_FUN_IE_R { + REG_PAD9_FUN_IE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + pub fn reg_pad9_filter_en(&self) -> REG_PAD9_FILTER_EN_R { + REG_PAD9_FILTER_EN_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD9") + .field( + "reg_pad9_drv", + &format_args!("{}", self.reg_pad9_drv().bits()), + ) + .field( + "reg_pad9_rde", + &format_args!("{}", self.reg_pad9_rde().bit()), + ) + .field( + "reg_pad9_rue", + &format_args!("{}", self.reg_pad9_rue().bit()), + ) + .field( + "reg_pad9_mux_sel", + &format_args!("{}", self.reg_pad9_mux_sel().bit()), + ) + .field( + "reg_pad9_fun_sel", + &format_args!("{}", self.reg_pad9_fun_sel().bits()), + ) + .field( + "reg_pad9_slp_sel", + &format_args!("{}", self.reg_pad9_slp_sel().bit()), + ) + .field( + "reg_pad9_slp_ie", + &format_args!("{}", self.reg_pad9_slp_ie().bit()), + ) + .field( + "reg_pad9_slp_oe", + &format_args!("{}", self.reg_pad9_slp_oe().bit()), + ) + .field( + "reg_pad9_fun_ie", + &format_args!("{}", self.reg_pad9_fun_ie().bit()), + ) + .field( + "reg_pad9_filter_en", + &format_args!("{}", self.reg_pad9_filter_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad9_drv(&mut self) -> REG_PAD9_DRV_W { + REG_PAD9_DRV_W::new(self, 0) + } + #[doc = "Bit 2 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad9_rde(&mut self) -> REG_PAD9_RDE_W { + REG_PAD9_RDE_W::new(self, 2) + } + #[doc = "Bit 3 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_pad9_rue(&mut self) -> REG_PAD9_RUE_W { + REG_PAD9_RUE_W::new(self, 3) + } + #[doc = "Bit 4 - 1:use LP GPIO,0: use digital GPIO"] + #[inline(always)] + #[must_use] + pub fn reg_pad9_mux_sel(&mut self) -> REG_PAD9_MUX_SEL_W { + REG_PAD9_MUX_SEL_W::new(self, 4) + } + #[doc = "Bits 5:6 - function sel"] + #[inline(always)] + #[must_use] + pub fn reg_pad9_fun_sel(&mut self) -> REG_PAD9_FUN_SEL_W { + REG_PAD9_FUN_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - 1: enable sleep mode during sleep,0: no sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad9_slp_sel(&mut self) -> REG_PAD9_SLP_SEL_W { + REG_PAD9_SLP_SEL_W::new(self, 7) + } + #[doc = "Bit 8 - input enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad9_slp_ie(&mut self) -> REG_PAD9_SLP_IE_W { + REG_PAD9_SLP_IE_W::new(self, 8) + } + #[doc = "Bit 9 - output enable in sleep mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad9_slp_oe(&mut self) -> REG_PAD9_SLP_OE_W { + REG_PAD9_SLP_OE_W::new(self, 9) + } + #[doc = "Bit 10 - input enable in work mode"] + #[inline(always)] + #[must_use] + pub fn reg_pad9_fun_ie(&mut self) -> REG_PAD9_FUN_IE_W { + REG_PAD9_FUN_IE_W::new(self, 10) + } + #[doc = "Bit 11 - need des"] + #[inline(always)] + #[must_use] + pub fn reg_pad9_filter_en(&mut self) -> REG_PAD9_FILTER_EN_W { + REG_PAD9_FILTER_EN_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD9_SPEC; +impl crate::RegisterSpec for PAD9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad9::R`](R) reader structure"] +impl crate::Readable for PAD9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad9::W`](W) writer structure"] +impl crate::Writable for PAD9_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD9 to value 0x02"] +impl crate::Resettable for PAD9_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_io_mux/ver_date.rs b/esp32p4/src/lp_io_mux/ver_date.rs new file mode 100644 index 0000000000..f0adf47fb7 --- /dev/null +++ b/esp32p4/src/lp_io_mux/ver_date.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VER_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `VER_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `REG_VER_DATE` reader - Reserved"] +pub type REG_VER_DATE_R = crate::FieldReader; +#[doc = "Field `REG_VER_DATE` writer - Reserved"] +pub type REG_VER_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Reserved"] + #[inline(always)] + pub fn reg_ver_date(&self) -> REG_VER_DATE_R { + REG_VER_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VER_DATE") + .field( + "reg_ver_date", + &format_args!("{}", self.reg_ver_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Reserved"] + #[inline(always)] + #[must_use] + pub fn reg_ver_date(&mut self) -> REG_VER_DATE_W { + REG_VER_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ver_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VER_DATE_SPEC; +impl crate::RegisterSpec for VER_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ver_date::R`](R) reader structure"] +impl crate::Readable for VER_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ver_date::W`](W) writer structure"] +impl crate::Writable for VER_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VER_DATE to value 0x0023_0313"] +impl crate::Resettable for VER_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0023_0313; +} diff --git a/esp32p4/src/lp_peri.rs b/esp32p4/src/lp_peri.rs new file mode 100644 index 0000000000..6d567d4a0f --- /dev/null +++ b/esp32p4/src/lp_peri.rs @@ -0,0 +1,119 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + clk_en: CLK_EN, + core_clk_sel: CORE_CLK_SEL, + reset_en: RESET_EN, + cpu: CPU, + _reserved4: [u8; 0x18], + mem_ctrl: MEM_CTRL, + adc_ctrl: ADC_CTRL, + lp_i2s_rxclk_div_num: LP_I2S_RXCLK_DIV_NUM, + lp_i2s_rxclk_div_xyz: LP_I2S_RXCLK_DIV_XYZ, + lp_i2s_txclk_div_num: LP_I2S_TXCLK_DIV_NUM, + lp_i2s_txclk_div_xyz: LP_I2S_TXCLK_DIV_XYZ, + _reserved10: [u8; 0x03bc], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - need_des"] + #[inline(always)] + pub const fn clk_en(&self) -> &CLK_EN { + &self.clk_en + } + #[doc = "0x04 - need_des"] + #[inline(always)] + pub const fn core_clk_sel(&self) -> &CORE_CLK_SEL { + &self.core_clk_sel + } + #[doc = "0x08 - need_des"] + #[inline(always)] + pub const fn reset_en(&self) -> &RESET_EN { + &self.reset_en + } + #[doc = "0x0c - need_des"] + #[inline(always)] + pub const fn cpu(&self) -> &CPU { + &self.cpu + } + #[doc = "0x28 - need_des"] + #[inline(always)] + pub const fn mem_ctrl(&self) -> &MEM_CTRL { + &self.mem_ctrl + } + #[doc = "0x2c - need_des"] + #[inline(always)] + pub const fn adc_ctrl(&self) -> &ADC_CTRL { + &self.adc_ctrl + } + #[doc = "0x30 - need_des"] + #[inline(always)] + pub const fn lp_i2s_rxclk_div_num(&self) -> &LP_I2S_RXCLK_DIV_NUM { + &self.lp_i2s_rxclk_div_num + } + #[doc = "0x34 - need_des"] + #[inline(always)] + pub const fn lp_i2s_rxclk_div_xyz(&self) -> &LP_I2S_RXCLK_DIV_XYZ { + &self.lp_i2s_rxclk_div_xyz + } + #[doc = "0x38 - need_des"] + #[inline(always)] + pub const fn lp_i2s_txclk_div_num(&self) -> &LP_I2S_TXCLK_DIV_NUM { + &self.lp_i2s_txclk_div_num + } + #[doc = "0x3c - need_des"] + #[inline(always)] + pub const fn lp_i2s_txclk_div_xyz(&self) -> &LP_I2S_TXCLK_DIV_XYZ { + &self.lp_i2s_txclk_div_xyz + } + #[doc = "0x3fc - need_des"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "CLK_EN (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_en`] module"] +pub type CLK_EN = crate::Reg; +#[doc = "need_des"] +pub mod clk_en; +#[doc = "CORE_CLK_SEL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_clk_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_clk_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_clk_sel`] module"] +pub type CORE_CLK_SEL = crate::Reg; +#[doc = "need_des"] +pub mod core_clk_sel; +#[doc = "RESET_EN (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_en`] module"] +pub type RESET_EN = crate::Reg; +#[doc = "need_des"] +pub mod reset_en; +#[doc = "CPU (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu`] module"] +pub type CPU = crate::Reg; +#[doc = "need_des"] +pub mod cpu; +#[doc = "MEM_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_ctrl`] module"] +pub type MEM_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod mem_ctrl; +#[doc = "ADC_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc_ctrl`] module"] +pub type ADC_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod adc_ctrl; +#[doc = "LP_I2S_RXCLK_DIV_NUM (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_rxclk_div_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_rxclk_div_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_i2s_rxclk_div_num`] module"] +pub type LP_I2S_RXCLK_DIV_NUM = crate::Reg; +#[doc = "need_des"] +pub mod lp_i2s_rxclk_div_num; +#[doc = "LP_I2S_RXCLK_DIV_XYZ (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_rxclk_div_xyz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_rxclk_div_xyz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_i2s_rxclk_div_xyz`] module"] +pub type LP_I2S_RXCLK_DIV_XYZ = crate::Reg; +#[doc = "need_des"] +pub mod lp_i2s_rxclk_div_xyz; +#[doc = "LP_I2S_TXCLK_DIV_NUM (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_txclk_div_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_txclk_div_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_i2s_txclk_div_num`] module"] +pub type LP_I2S_TXCLK_DIV_NUM = crate::Reg; +#[doc = "need_des"] +pub mod lp_i2s_txclk_div_num; +#[doc = "LP_I2S_TXCLK_DIV_XYZ (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_txclk_div_xyz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_txclk_div_xyz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_i2s_txclk_div_xyz`] module"] +pub type LP_I2S_TXCLK_DIV_XYZ = crate::Reg; +#[doc = "need_des"] +pub mod lp_i2s_txclk_div_xyz; +#[doc = "DATE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "need_des"] +pub mod date; diff --git a/esp32p4/src/lp_peri/adc_ctrl.rs b/esp32p4/src/lp_peri/adc_ctrl.rs new file mode 100644 index 0000000000..247dafb984 --- /dev/null +++ b/esp32p4/src/lp_peri/adc_ctrl.rs @@ -0,0 +1,142 @@ +#[doc = "Register `ADC_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `ADC_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SAR2_CLK_FORCE_ON` reader - need_des"] +pub type SAR2_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `SAR2_CLK_FORCE_ON` writer - need_des"] +pub type SAR2_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAR1_CLK_FORCE_ON` reader - need_des"] +pub type SAR1_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `SAR1_CLK_FORCE_ON` writer - need_des"] +pub type SAR1_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LPADC_FUNC_DIV_NUM` reader - need_des"] +pub type LPADC_FUNC_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `LPADC_FUNC_DIV_NUM` writer - need_des"] +pub type LPADC_FUNC_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LPADC_SAR2_DIV_NUM` reader - need_des"] +pub type LPADC_SAR2_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `LPADC_SAR2_DIV_NUM` writer - need_des"] +pub type LPADC_SAR2_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LPADC_SAR1_DIV_NUM` reader - need_des"] +pub type LPADC_SAR1_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `LPADC_SAR1_DIV_NUM` writer - need_des"] +pub type LPADC_SAR1_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bit 6 - need_des"] + #[inline(always)] + pub fn sar2_clk_force_on(&self) -> SAR2_CLK_FORCE_ON_R { + SAR2_CLK_FORCE_ON_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - need_des"] + #[inline(always)] + pub fn sar1_clk_force_on(&self) -> SAR1_CLK_FORCE_ON_R { + SAR1_CLK_FORCE_ON_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:15 - need_des"] + #[inline(always)] + pub fn lpadc_func_div_num(&self) -> LPADC_FUNC_DIV_NUM_R { + LPADC_FUNC_DIV_NUM_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + pub fn lpadc_sar2_div_num(&self) -> LPADC_SAR2_DIV_NUM_R { + LPADC_SAR2_DIV_NUM_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + pub fn lpadc_sar1_div_num(&self) -> LPADC_SAR1_DIV_NUM_R { + LPADC_SAR1_DIV_NUM_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC_CTRL") + .field( + "sar2_clk_force_on", + &format_args!("{}", self.sar2_clk_force_on().bit()), + ) + .field( + "sar1_clk_force_on", + &format_args!("{}", self.sar1_clk_force_on().bit()), + ) + .field( + "lpadc_func_div_num", + &format_args!("{}", self.lpadc_func_div_num().bits()), + ) + .field( + "lpadc_sar2_div_num", + &format_args!("{}", self.lpadc_sar2_div_num().bits()), + ) + .field( + "lpadc_sar1_div_num", + &format_args!("{}", self.lpadc_sar1_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 6 - need_des"] + #[inline(always)] + #[must_use] + pub fn sar2_clk_force_on(&mut self) -> SAR2_CLK_FORCE_ON_W { + SAR2_CLK_FORCE_ON_W::new(self, 6) + } + #[doc = "Bit 7 - need_des"] + #[inline(always)] + #[must_use] + pub fn sar1_clk_force_on(&mut self) -> SAR1_CLK_FORCE_ON_W { + SAR1_CLK_FORCE_ON_W::new(self, 7) + } + #[doc = "Bits 8:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn lpadc_func_div_num(&mut self) -> LPADC_FUNC_DIV_NUM_W { + LPADC_FUNC_DIV_NUM_W::new(self, 8) + } + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + #[must_use] + pub fn lpadc_sar2_div_num(&mut self) -> LPADC_SAR2_DIV_NUM_W { + LPADC_SAR2_DIV_NUM_W::new(self, 16) + } + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lpadc_sar1_div_num(&mut self) -> LPADC_SAR1_DIV_NUM_W { + LPADC_SAR1_DIV_NUM_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ADC_CTRL_SPEC; +impl crate::RegisterSpec for ADC_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`adc_ctrl::R`](R) reader structure"] +impl crate::Readable for ADC_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`adc_ctrl::W`](W) writer structure"] +impl crate::Writable for ADC_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ADC_CTRL to value 0x0404_0400"] +impl crate::Resettable for ADC_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0404_0400; +} diff --git a/esp32p4/src/lp_peri/clk_en.rs b/esp32p4/src/lp_peri/clk_en.rs new file mode 100644 index 0000000000..196cb2bf36 --- /dev/null +++ b/esp32p4/src/lp_peri/clk_en.rs @@ -0,0 +1,348 @@ +#[doc = "Register `CLK_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_EN` writer"] +pub type W = crate::W; +#[doc = "Field `CK_EN_RNG` reader - need_des"] +pub type CK_EN_RNG_R = crate::BitReader; +#[doc = "Field `CK_EN_RNG` writer - need_des"] +pub type CK_EN_RNG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_TSENS` reader - need_des"] +pub type CK_EN_LP_TSENS_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_TSENS` writer - need_des"] +pub type CK_EN_LP_TSENS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_PMS` reader - need_des"] +pub type CK_EN_LP_PMS_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_PMS` writer - need_des"] +pub type CK_EN_LP_PMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_EFUSE` reader - need_des"] +pub type CK_EN_LP_EFUSE_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_EFUSE` writer - need_des"] +pub type CK_EN_LP_EFUSE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_IOMUX` reader - need_des"] +pub type CK_EN_LP_IOMUX_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_IOMUX` writer - need_des"] +pub type CK_EN_LP_IOMUX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_TOUCH` reader - need_des"] +pub type CK_EN_LP_TOUCH_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_TOUCH` writer - need_des"] +pub type CK_EN_LP_TOUCH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_SPI` reader - need_des"] +pub type CK_EN_LP_SPI_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_SPI` writer - need_des"] +pub type CK_EN_LP_SPI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_ADC` reader - need_des"] +pub type CK_EN_LP_ADC_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_ADC` writer - need_des"] +pub type CK_EN_LP_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_I2S_TX` reader - need_des"] +pub type CK_EN_LP_I2S_TX_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_I2S_TX` writer - need_des"] +pub type CK_EN_LP_I2S_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_I2S_RX` reader - need_des"] +pub type CK_EN_LP_I2S_RX_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_I2S_RX` writer - need_des"] +pub type CK_EN_LP_I2S_RX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_I2S` reader - need_des"] +pub type CK_EN_LP_I2S_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_I2S` writer - need_des"] +pub type CK_EN_LP_I2S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_I2CMST` reader - need_des"] +pub type CK_EN_LP_I2CMST_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_I2CMST` writer - need_des"] +pub type CK_EN_LP_I2CMST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_I2C` reader - need_des"] +pub type CK_EN_LP_I2C_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_I2C` writer - need_des"] +pub type CK_EN_LP_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_UART` reader - need_des"] +pub type CK_EN_LP_UART_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_UART` writer - need_des"] +pub type CK_EN_LP_UART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_INTR` reader - need_des"] +pub type CK_EN_LP_INTR_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_INTR` writer - need_des"] +pub type CK_EN_LP_INTR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CK_EN_LP_CORE` reader - write 1 to force on lp_core clk"] +pub type CK_EN_LP_CORE_R = crate::BitReader; +#[doc = "Field `CK_EN_LP_CORE` writer - write 1 to force on lp_core clk"] +pub type CK_EN_LP_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 16 - need_des"] + #[inline(always)] + pub fn ck_en_rng(&self) -> CK_EN_RNG_R { + CK_EN_RNG_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - need_des"] + #[inline(always)] + pub fn ck_en_lp_tsens(&self) -> CK_EN_LP_TSENS_R { + CK_EN_LP_TSENS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - need_des"] + #[inline(always)] + pub fn ck_en_lp_pms(&self) -> CK_EN_LP_PMS_R { + CK_EN_LP_PMS_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - need_des"] + #[inline(always)] + pub fn ck_en_lp_efuse(&self) -> CK_EN_LP_EFUSE_R { + CK_EN_LP_EFUSE_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - need_des"] + #[inline(always)] + pub fn ck_en_lp_iomux(&self) -> CK_EN_LP_IOMUX_R { + CK_EN_LP_IOMUX_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - need_des"] + #[inline(always)] + pub fn ck_en_lp_touch(&self) -> CK_EN_LP_TOUCH_R { + CK_EN_LP_TOUCH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + pub fn ck_en_lp_spi(&self) -> CK_EN_LP_SPI_R { + CK_EN_LP_SPI_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - need_des"] + #[inline(always)] + pub fn ck_en_lp_adc(&self) -> CK_EN_LP_ADC_R { + CK_EN_LP_ADC_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + pub fn ck_en_lp_i2s_tx(&self) -> CK_EN_LP_I2S_TX_R { + CK_EN_LP_I2S_TX_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn ck_en_lp_i2s_rx(&self) -> CK_EN_LP_I2S_RX_R { + CK_EN_LP_I2S_RX_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn ck_en_lp_i2s(&self) -> CK_EN_LP_I2S_R { + CK_EN_LP_I2S_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn ck_en_lp_i2cmst(&self) -> CK_EN_LP_I2CMST_R { + CK_EN_LP_I2CMST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn ck_en_lp_i2c(&self) -> CK_EN_LP_I2C_R { + CK_EN_LP_I2C_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn ck_en_lp_uart(&self) -> CK_EN_LP_UART_R { + CK_EN_LP_UART_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn ck_en_lp_intr(&self) -> CK_EN_LP_INTR_R { + CK_EN_LP_INTR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - write 1 to force on lp_core clk"] + #[inline(always)] + pub fn ck_en_lp_core(&self) -> CK_EN_LP_CORE_R { + CK_EN_LP_CORE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_EN") + .field("ck_en_rng", &format_args!("{}", self.ck_en_rng().bit())) + .field( + "ck_en_lp_tsens", + &format_args!("{}", self.ck_en_lp_tsens().bit()), + ) + .field( + "ck_en_lp_pms", + &format_args!("{}", self.ck_en_lp_pms().bit()), + ) + .field( + "ck_en_lp_efuse", + &format_args!("{}", self.ck_en_lp_efuse().bit()), + ) + .field( + "ck_en_lp_iomux", + &format_args!("{}", self.ck_en_lp_iomux().bit()), + ) + .field( + "ck_en_lp_touch", + &format_args!("{}", self.ck_en_lp_touch().bit()), + ) + .field( + "ck_en_lp_spi", + &format_args!("{}", self.ck_en_lp_spi().bit()), + ) + .field( + "ck_en_lp_adc", + &format_args!("{}", self.ck_en_lp_adc().bit()), + ) + .field( + "ck_en_lp_i2s_tx", + &format_args!("{}", self.ck_en_lp_i2s_tx().bit()), + ) + .field( + "ck_en_lp_i2s_rx", + &format_args!("{}", self.ck_en_lp_i2s_rx().bit()), + ) + .field( + "ck_en_lp_i2s", + &format_args!("{}", self.ck_en_lp_i2s().bit()), + ) + .field( + "ck_en_lp_i2cmst", + &format_args!("{}", self.ck_en_lp_i2cmst().bit()), + ) + .field( + "ck_en_lp_i2c", + &format_args!("{}", self.ck_en_lp_i2c().bit()), + ) + .field( + "ck_en_lp_uart", + &format_args!("{}", self.ck_en_lp_uart().bit()), + ) + .field( + "ck_en_lp_intr", + &format_args!("{}", self.ck_en_lp_intr().bit()), + ) + .field( + "ck_en_lp_core", + &format_args!("{}", self.ck_en_lp_core().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 16 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_rng(&mut self) -> CK_EN_RNG_W { + CK_EN_RNG_W::new(self, 16) + } + #[doc = "Bit 17 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_tsens(&mut self) -> CK_EN_LP_TSENS_W { + CK_EN_LP_TSENS_W::new(self, 17) + } + #[doc = "Bit 18 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_pms(&mut self) -> CK_EN_LP_PMS_W { + CK_EN_LP_PMS_W::new(self, 18) + } + #[doc = "Bit 19 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_efuse(&mut self) -> CK_EN_LP_EFUSE_W { + CK_EN_LP_EFUSE_W::new(self, 19) + } + #[doc = "Bit 20 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_iomux(&mut self) -> CK_EN_LP_IOMUX_W { + CK_EN_LP_IOMUX_W::new(self, 20) + } + #[doc = "Bit 21 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_touch(&mut self) -> CK_EN_LP_TOUCH_W { + CK_EN_LP_TOUCH_W::new(self, 21) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_spi(&mut self) -> CK_EN_LP_SPI_W { + CK_EN_LP_SPI_W::new(self, 22) + } + #[doc = "Bit 23 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_adc(&mut self) -> CK_EN_LP_ADC_W { + CK_EN_LP_ADC_W::new(self, 23) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_i2s_tx(&mut self) -> CK_EN_LP_I2S_TX_W { + CK_EN_LP_I2S_TX_W::new(self, 24) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_i2s_rx(&mut self) -> CK_EN_LP_I2S_RX_W { + CK_EN_LP_I2S_RX_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_i2s(&mut self) -> CK_EN_LP_I2S_W { + CK_EN_LP_I2S_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_i2cmst(&mut self) -> CK_EN_LP_I2CMST_W { + CK_EN_LP_I2CMST_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_i2c(&mut self) -> CK_EN_LP_I2C_W { + CK_EN_LP_I2C_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_uart(&mut self) -> CK_EN_LP_UART_W { + CK_EN_LP_UART_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_intr(&mut self) -> CK_EN_LP_INTR_W { + CK_EN_LP_INTR_W::new(self, 30) + } + #[doc = "Bit 31 - write 1 to force on lp_core clk"] + #[inline(always)] + #[must_use] + pub fn ck_en_lp_core(&mut self) -> CK_EN_LP_CORE_W { + CK_EN_LP_CORE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_EN_SPEC; +impl crate::RegisterSpec for CLK_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_en::R`](R) reader structure"] +impl crate::Readable for CLK_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_en::W`](W) writer structure"] +impl crate::Writable for CLK_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_EN to value 0x7fff_0000"] +impl crate::Resettable for CLK_EN_SPEC { + const RESET_VALUE: Self::Ux = 0x7fff_0000; +} diff --git a/esp32p4/src/lp_peri/core_clk_sel.rs b/esp32p4/src/lp_peri/core_clk_sel.rs new file mode 100644 index 0000000000..a6c7f804a0 --- /dev/null +++ b/esp32p4/src/lp_peri/core_clk_sel.rs @@ -0,0 +1,123 @@ +#[doc = "Register `CORE_CLK_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `CORE_CLK_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_I2S_TX_CLK_SEL` reader - need_des"] +pub type LP_I2S_TX_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `LP_I2S_TX_CLK_SEL` writer - need_des"] +pub type LP_I2S_TX_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_I2S_RX_CLK_SEL` reader - need_des"] +pub type LP_I2S_RX_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `LP_I2S_RX_CLK_SEL` writer - need_des"] +pub type LP_I2S_RX_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_I2C_CLK_SEL` reader - need_des"] +pub type LP_I2C_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `LP_I2C_CLK_SEL` writer - need_des"] +pub type LP_I2C_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_UART_CLK_SEL` reader - need_des"] +pub type LP_UART_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `LP_UART_CLK_SEL` writer - need_des"] +pub type LP_UART_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 24:25 - need_des"] + #[inline(always)] + pub fn lp_i2s_tx_clk_sel(&self) -> LP_I2S_TX_CLK_SEL_R { + LP_I2S_TX_CLK_SEL_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - need_des"] + #[inline(always)] + pub fn lp_i2s_rx_clk_sel(&self) -> LP_I2S_RX_CLK_SEL_R { + LP_I2S_RX_CLK_SEL_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - need_des"] + #[inline(always)] + pub fn lp_i2c_clk_sel(&self) -> LP_I2C_CLK_SEL_R { + LP_I2C_CLK_SEL_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + pub fn lp_uart_clk_sel(&self) -> LP_UART_CLK_SEL_R { + LP_UART_CLK_SEL_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORE_CLK_SEL") + .field( + "lp_i2s_tx_clk_sel", + &format_args!("{}", self.lp_i2s_tx_clk_sel().bits()), + ) + .field( + "lp_i2s_rx_clk_sel", + &format_args!("{}", self.lp_i2s_rx_clk_sel().bits()), + ) + .field( + "lp_i2c_clk_sel", + &format_args!("{}", self.lp_i2c_clk_sel().bits()), + ) + .field( + "lp_uart_clk_sel", + &format_args!("{}", self.lp_uart_clk_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 24:25 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_tx_clk_sel(&mut self) -> LP_I2S_TX_CLK_SEL_W { + LP_I2S_TX_CLK_SEL_W::new(self, 24) + } + #[doc = "Bits 26:27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_rx_clk_sel(&mut self) -> LP_I2S_RX_CLK_SEL_W { + LP_I2S_RX_CLK_SEL_W::new(self, 26) + } + #[doc = "Bits 28:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2c_clk_sel(&mut self) -> LP_I2C_CLK_SEL_W { + LP_I2C_CLK_SEL_W::new(self, 28) + } + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_uart_clk_sel(&mut self) -> LP_UART_CLK_SEL_W { + LP_UART_CLK_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_clk_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_clk_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORE_CLK_SEL_SPEC; +impl crate::RegisterSpec for CORE_CLK_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`core_clk_sel::R`](R) reader structure"] +impl crate::Readable for CORE_CLK_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`core_clk_sel::W`](W) writer structure"] +impl crate::Writable for CORE_CLK_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CORE_CLK_SEL to value 0"] +impl crate::Resettable for CORE_CLK_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_peri/cpu.rs b/esp32p4/src/lp_peri/cpu.rs new file mode 100644 index 0000000000..0efce1d48c --- /dev/null +++ b/esp32p4/src/lp_peri/cpu.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CPU` reader"] +pub type R = crate::R; +#[doc = "Register `CPU` writer"] +pub type W = crate::W; +#[doc = "Field `LPCORE_DBGM_UNAVAILABLE` reader - need_des"] +pub type LPCORE_DBGM_UNAVAILABLE_R = crate::BitReader; +#[doc = "Field `LPCORE_DBGM_UNAVAILABLE` writer - need_des"] +pub type LPCORE_DBGM_UNAVAILABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lpcore_dbgm_unavailable(&self) -> LPCORE_DBGM_UNAVAILABLE_R { + LPCORE_DBGM_UNAVAILABLE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU") + .field( + "lpcore_dbgm_unavailable", + &format_args!("{}", self.lpcore_dbgm_unavailable().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lpcore_dbgm_unavailable(&mut self) -> LPCORE_DBGM_UNAVAILABLE_W { + LPCORE_DBGM_UNAVAILABLE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_SPEC; +impl crate::RegisterSpec for CPU_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu::R`](R) reader structure"] +impl crate::Readable for CPU_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpu::W`](W) writer structure"] +impl crate::Writable for CPU_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CPU to value 0x8000_0000"] +impl crate::Resettable for CPU_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_0000; +} diff --git a/esp32p4/src/lp_peri/date.rs b/esp32p4/src/lp_peri/date.rs new file mode 100644 index 0000000000..d0cb7beb4f --- /dev/null +++ b/esp32p4/src/lp_peri/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - need_des"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - need_des"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_peri/lp_i2s_rxclk_div_num.rs b/esp32p4/src/lp_peri/lp_i2s_rxclk_div_num.rs new file mode 100644 index 0000000000..a211e56d7d --- /dev/null +++ b/esp32p4/src/lp_peri/lp_i2s_rxclk_div_num.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_I2S_RXCLK_DIV_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `LP_I2S_RXCLK_DIV_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `LP_I2S_RX_CLKM_DIV_NUM` reader - need_des"] +pub type LP_I2S_RX_CLKM_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `LP_I2S_RX_CLKM_DIV_NUM` writer - need_des"] +pub type LP_I2S_RX_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + pub fn lp_i2s_rx_clkm_div_num(&self) -> LP_I2S_RX_CLKM_DIV_NUM_R { + LP_I2S_RX_CLKM_DIV_NUM_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2S_RXCLK_DIV_NUM") + .field( + "lp_i2s_rx_clkm_div_num", + &format_args!("{}", self.lp_i2s_rx_clkm_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_rx_clkm_div_num( + &mut self, + ) -> LP_I2S_RX_CLKM_DIV_NUM_W { + LP_I2S_RX_CLKM_DIV_NUM_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_rxclk_div_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_rxclk_div_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_I2S_RXCLK_DIV_NUM_SPEC; +impl crate::RegisterSpec for LP_I2S_RXCLK_DIV_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_i2s_rxclk_div_num::R`](R) reader structure"] +impl crate::Readable for LP_I2S_RXCLK_DIV_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_i2s_rxclk_div_num::W`](W) writer structure"] +impl crate::Writable for LP_I2S_RXCLK_DIV_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_I2S_RXCLK_DIV_NUM to value 0x0200_0000"] +impl crate::Resettable for LP_I2S_RXCLK_DIV_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0000; +} diff --git a/esp32p4/src/lp_peri/lp_i2s_rxclk_div_xyz.rs b/esp32p4/src/lp_peri/lp_i2s_rxclk_div_xyz.rs new file mode 100644 index 0000000000..ee11701fa8 --- /dev/null +++ b/esp32p4/src/lp_peri/lp_i2s_rxclk_div_xyz.rs @@ -0,0 +1,125 @@ +#[doc = "Register `LP_I2S_RXCLK_DIV_XYZ` reader"] +pub type R = crate::R; +#[doc = "Register `LP_I2S_RXCLK_DIV_XYZ` writer"] +pub type W = crate::W; +#[doc = "Field `LP_I2S_RX_CLKM_DIV_YN1` reader - need_des"] +pub type LP_I2S_RX_CLKM_DIV_YN1_R = crate::BitReader; +#[doc = "Field `LP_I2S_RX_CLKM_DIV_YN1` writer - need_des"] +pub type LP_I2S_RX_CLKM_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_I2S_RX_CLKM_DIV_Z` reader - need_des"] +pub type LP_I2S_RX_CLKM_DIV_Z_R = crate::FieldReader; +#[doc = "Field `LP_I2S_RX_CLKM_DIV_Z` writer - need_des"] +pub type LP_I2S_RX_CLKM_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `LP_I2S_RX_CLKM_DIV_Y` reader - need_des"] +pub type LP_I2S_RX_CLKM_DIV_Y_R = crate::FieldReader; +#[doc = "Field `LP_I2S_RX_CLKM_DIV_Y` writer - need_des"] +pub type LP_I2S_RX_CLKM_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `LP_I2S_RX_CLKM_DIV_X` reader - need_des"] +pub type LP_I2S_RX_CLKM_DIV_X_R = crate::FieldReader; +#[doc = "Field `LP_I2S_RX_CLKM_DIV_X` writer - need_des"] +pub type LP_I2S_RX_CLKM_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bit 4 - need_des"] + #[inline(always)] + pub fn lp_i2s_rx_clkm_div_yn1(&self) -> LP_I2S_RX_CLKM_DIV_YN1_R { + LP_I2S_RX_CLKM_DIV_YN1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:13 - need_des"] + #[inline(always)] + pub fn lp_i2s_rx_clkm_div_z(&self) -> LP_I2S_RX_CLKM_DIV_Z_R { + LP_I2S_RX_CLKM_DIV_Z_R::new(((self.bits >> 5) & 0x01ff) as u16) + } + #[doc = "Bits 14:22 - need_des"] + #[inline(always)] + pub fn lp_i2s_rx_clkm_div_y(&self) -> LP_I2S_RX_CLKM_DIV_Y_R { + LP_I2S_RX_CLKM_DIV_Y_R::new(((self.bits >> 14) & 0x01ff) as u16) + } + #[doc = "Bits 23:31 - need_des"] + #[inline(always)] + pub fn lp_i2s_rx_clkm_div_x(&self) -> LP_I2S_RX_CLKM_DIV_X_R { + LP_I2S_RX_CLKM_DIV_X_R::new(((self.bits >> 23) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2S_RXCLK_DIV_XYZ") + .field( + "lp_i2s_rx_clkm_div_yn1", + &format_args!("{}", self.lp_i2s_rx_clkm_div_yn1().bit()), + ) + .field( + "lp_i2s_rx_clkm_div_z", + &format_args!("{}", self.lp_i2s_rx_clkm_div_z().bits()), + ) + .field( + "lp_i2s_rx_clkm_div_y", + &format_args!("{}", self.lp_i2s_rx_clkm_div_y().bits()), + ) + .field( + "lp_i2s_rx_clkm_div_x", + &format_args!("{}", self.lp_i2s_rx_clkm_div_x().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 4 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_rx_clkm_div_yn1( + &mut self, + ) -> LP_I2S_RX_CLKM_DIV_YN1_W { + LP_I2S_RX_CLKM_DIV_YN1_W::new(self, 4) + } + #[doc = "Bits 5:13 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_rx_clkm_div_z(&mut self) -> LP_I2S_RX_CLKM_DIV_Z_W { + LP_I2S_RX_CLKM_DIV_Z_W::new(self, 5) + } + #[doc = "Bits 14:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_rx_clkm_div_y(&mut self) -> LP_I2S_RX_CLKM_DIV_Y_W { + LP_I2S_RX_CLKM_DIV_Y_W::new(self, 14) + } + #[doc = "Bits 23:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_rx_clkm_div_x(&mut self) -> LP_I2S_RX_CLKM_DIV_X_W { + LP_I2S_RX_CLKM_DIV_X_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_rxclk_div_xyz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_rxclk_div_xyz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_I2S_RXCLK_DIV_XYZ_SPEC; +impl crate::RegisterSpec for LP_I2S_RXCLK_DIV_XYZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_i2s_rxclk_div_xyz::R`](R) reader structure"] +impl crate::Readable for LP_I2S_RXCLK_DIV_XYZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_i2s_rxclk_div_xyz::W`](W) writer structure"] +impl crate::Writable for LP_I2S_RXCLK_DIV_XYZ_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_I2S_RXCLK_DIV_XYZ to value 0x4000"] +impl crate::Resettable for LP_I2S_RXCLK_DIV_XYZ_SPEC { + const RESET_VALUE: Self::Ux = 0x4000; +} diff --git a/esp32p4/src/lp_peri/lp_i2s_txclk_div_num.rs b/esp32p4/src/lp_peri/lp_i2s_txclk_div_num.rs new file mode 100644 index 0000000000..80ca49b4cb --- /dev/null +++ b/esp32p4/src/lp_peri/lp_i2s_txclk_div_num.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_I2S_TXCLK_DIV_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `LP_I2S_TXCLK_DIV_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `LP_I2S_TX_CLKM_DIV_NUM` reader - need_des"] +pub type LP_I2S_TX_CLKM_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `LP_I2S_TX_CLKM_DIV_NUM` writer - need_des"] +pub type LP_I2S_TX_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + pub fn lp_i2s_tx_clkm_div_num(&self) -> LP_I2S_TX_CLKM_DIV_NUM_R { + LP_I2S_TX_CLKM_DIV_NUM_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2S_TXCLK_DIV_NUM") + .field( + "lp_i2s_tx_clkm_div_num", + &format_args!("{}", self.lp_i2s_tx_clkm_div_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_tx_clkm_div_num( + &mut self, + ) -> LP_I2S_TX_CLKM_DIV_NUM_W { + LP_I2S_TX_CLKM_DIV_NUM_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_txclk_div_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_txclk_div_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_I2S_TXCLK_DIV_NUM_SPEC; +impl crate::RegisterSpec for LP_I2S_TXCLK_DIV_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_i2s_txclk_div_num::R`](R) reader structure"] +impl crate::Readable for LP_I2S_TXCLK_DIV_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_i2s_txclk_div_num::W`](W) writer structure"] +impl crate::Writable for LP_I2S_TXCLK_DIV_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_I2S_TXCLK_DIV_NUM to value 0x0200_0000"] +impl crate::Resettable for LP_I2S_TXCLK_DIV_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0x0200_0000; +} diff --git a/esp32p4/src/lp_peri/lp_i2s_txclk_div_xyz.rs b/esp32p4/src/lp_peri/lp_i2s_txclk_div_xyz.rs new file mode 100644 index 0000000000..b26e521d9e --- /dev/null +++ b/esp32p4/src/lp_peri/lp_i2s_txclk_div_xyz.rs @@ -0,0 +1,125 @@ +#[doc = "Register `LP_I2S_TXCLK_DIV_XYZ` reader"] +pub type R = crate::R; +#[doc = "Register `LP_I2S_TXCLK_DIV_XYZ` writer"] +pub type W = crate::W; +#[doc = "Field `LP_I2S_TX_CLKM_DIV_YN1` reader - need_des"] +pub type LP_I2S_TX_CLKM_DIV_YN1_R = crate::BitReader; +#[doc = "Field `LP_I2S_TX_CLKM_DIV_YN1` writer - need_des"] +pub type LP_I2S_TX_CLKM_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_I2S_TX_CLKM_DIV_Z` reader - need_des"] +pub type LP_I2S_TX_CLKM_DIV_Z_R = crate::FieldReader; +#[doc = "Field `LP_I2S_TX_CLKM_DIV_Z` writer - need_des"] +pub type LP_I2S_TX_CLKM_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `LP_I2S_TX_CLKM_DIV_Y` reader - need_des"] +pub type LP_I2S_TX_CLKM_DIV_Y_R = crate::FieldReader; +#[doc = "Field `LP_I2S_TX_CLKM_DIV_Y` writer - need_des"] +pub type LP_I2S_TX_CLKM_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `LP_I2S_TX_CLKM_DIV_X` reader - need_des"] +pub type LP_I2S_TX_CLKM_DIV_X_R = crate::FieldReader; +#[doc = "Field `LP_I2S_TX_CLKM_DIV_X` writer - need_des"] +pub type LP_I2S_TX_CLKM_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bit 4 - need_des"] + #[inline(always)] + pub fn lp_i2s_tx_clkm_div_yn1(&self) -> LP_I2S_TX_CLKM_DIV_YN1_R { + LP_I2S_TX_CLKM_DIV_YN1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:13 - need_des"] + #[inline(always)] + pub fn lp_i2s_tx_clkm_div_z(&self) -> LP_I2S_TX_CLKM_DIV_Z_R { + LP_I2S_TX_CLKM_DIV_Z_R::new(((self.bits >> 5) & 0x01ff) as u16) + } + #[doc = "Bits 14:22 - need_des"] + #[inline(always)] + pub fn lp_i2s_tx_clkm_div_y(&self) -> LP_I2S_TX_CLKM_DIV_Y_R { + LP_I2S_TX_CLKM_DIV_Y_R::new(((self.bits >> 14) & 0x01ff) as u16) + } + #[doc = "Bits 23:31 - need_des"] + #[inline(always)] + pub fn lp_i2s_tx_clkm_div_x(&self) -> LP_I2S_TX_CLKM_DIV_X_R { + LP_I2S_TX_CLKM_DIV_X_R::new(((self.bits >> 23) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_I2S_TXCLK_DIV_XYZ") + .field( + "lp_i2s_tx_clkm_div_yn1", + &format_args!("{}", self.lp_i2s_tx_clkm_div_yn1().bit()), + ) + .field( + "lp_i2s_tx_clkm_div_z", + &format_args!("{}", self.lp_i2s_tx_clkm_div_z().bits()), + ) + .field( + "lp_i2s_tx_clkm_div_y", + &format_args!("{}", self.lp_i2s_tx_clkm_div_y().bits()), + ) + .field( + "lp_i2s_tx_clkm_div_x", + &format_args!("{}", self.lp_i2s_tx_clkm_div_x().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 4 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_tx_clkm_div_yn1( + &mut self, + ) -> LP_I2S_TX_CLKM_DIV_YN1_W { + LP_I2S_TX_CLKM_DIV_YN1_W::new(self, 4) + } + #[doc = "Bits 5:13 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_tx_clkm_div_z(&mut self) -> LP_I2S_TX_CLKM_DIV_Z_W { + LP_I2S_TX_CLKM_DIV_Z_W::new(self, 5) + } + #[doc = "Bits 14:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_tx_clkm_div_y(&mut self) -> LP_I2S_TX_CLKM_DIV_Y_W { + LP_I2S_TX_CLKM_DIV_Y_W::new(self, 14) + } + #[doc = "Bits 23:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_i2s_tx_clkm_div_x(&mut self) -> LP_I2S_TX_CLKM_DIV_X_W { + LP_I2S_TX_CLKM_DIV_X_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_i2s_txclk_div_xyz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_i2s_txclk_div_xyz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_I2S_TXCLK_DIV_XYZ_SPEC; +impl crate::RegisterSpec for LP_I2S_TXCLK_DIV_XYZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_i2s_txclk_div_xyz::R`](R) reader structure"] +impl crate::Readable for LP_I2S_TXCLK_DIV_XYZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_i2s_txclk_div_xyz::W`](W) writer structure"] +impl crate::Writable for LP_I2S_TXCLK_DIV_XYZ_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_I2S_TXCLK_DIV_XYZ to value 0x4000"] +impl crate::Resettable for LP_I2S_TXCLK_DIV_XYZ_SPEC { + const RESET_VALUE: Self::Ux = 0x4000; +} diff --git a/esp32p4/src/lp_peri/mem_ctrl.rs b/esp32p4/src/lp_peri/mem_ctrl.rs new file mode 100644 index 0000000000..bc240c972e --- /dev/null +++ b/esp32p4/src/lp_peri/mem_ctrl.rs @@ -0,0 +1,131 @@ +#[doc = "Register `MEM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_UART_WAKEUP_FLAG_CLR` writer - need_des"] +pub type LP_UART_WAKEUP_FLAG_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_UART_WAKEUP_FLAG` reader - need_des"] +pub type LP_UART_WAKEUP_FLAG_R = crate::BitReader; +#[doc = "Field `LP_UART_WAKEUP_FLAG` writer - need_des"] +pub type LP_UART_WAKEUP_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_UART_WAKEUP_EN` reader - need_des"] +pub type LP_UART_WAKEUP_EN_R = crate::BitReader; +#[doc = "Field `LP_UART_WAKEUP_EN` writer - need_des"] +pub type LP_UART_WAKEUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_UART_MEM_FORCE_PD` reader - need_des"] +pub type LP_UART_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `LP_UART_MEM_FORCE_PD` writer - need_des"] +pub type LP_UART_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_UART_MEM_FORCE_PU` reader - need_des"] +pub type LP_UART_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `LP_UART_MEM_FORCE_PU` writer - need_des"] +pub type LP_UART_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn lp_uart_wakeup_flag(&self) -> LP_UART_WAKEUP_FLAG_R { + LP_UART_WAKEUP_FLAG_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn lp_uart_wakeup_en(&self) -> LP_UART_WAKEUP_EN_R { + LP_UART_WAKEUP_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_uart_mem_force_pd(&self) -> LP_UART_MEM_FORCE_PD_R { + LP_UART_MEM_FORCE_PD_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_uart_mem_force_pu(&self) -> LP_UART_MEM_FORCE_PU_R { + LP_UART_MEM_FORCE_PU_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_CTRL") + .field( + "lp_uart_wakeup_flag", + &format_args!("{}", self.lp_uart_wakeup_flag().bit()), + ) + .field( + "lp_uart_wakeup_en", + &format_args!("{}", self.lp_uart_wakeup_en().bit()), + ) + .field( + "lp_uart_mem_force_pd", + &format_args!("{}", self.lp_uart_mem_force_pd().bit()), + ) + .field( + "lp_uart_mem_force_pu", + &format_args!("{}", self.lp_uart_mem_force_pu().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_uart_wakeup_flag_clr(&mut self) -> LP_UART_WAKEUP_FLAG_CLR_W { + LP_UART_WAKEUP_FLAG_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_uart_wakeup_flag(&mut self) -> LP_UART_WAKEUP_FLAG_W { + LP_UART_WAKEUP_FLAG_W::new(self, 1) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_uart_wakeup_en(&mut self) -> LP_UART_WAKEUP_EN_W { + LP_UART_WAKEUP_EN_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_uart_mem_force_pd(&mut self) -> LP_UART_MEM_FORCE_PD_W { + LP_UART_MEM_FORCE_PD_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_uart_mem_force_pu(&mut self) -> LP_UART_MEM_FORCE_PU_W { + LP_UART_MEM_FORCE_PU_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_CTRL_SPEC; +impl crate::RegisterSpec for MEM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_ctrl::R`](R) reader structure"] +impl crate::Readable for MEM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_ctrl::W`](W) writer structure"] +impl crate::Writable for MEM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_CTRL to value 0x8000_0000"] +impl crate::Resettable for MEM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_0000; +} diff --git a/esp32p4/src/lp_peri/reset_en.rs b/esp32p4/src/lp_peri/reset_en.rs new file mode 100644 index 0000000000..8f85297d9d --- /dev/null +++ b/esp32p4/src/lp_peri/reset_en.rs @@ -0,0 +1,302 @@ +#[doc = "Register `RESET_EN` reader"] +pub type R = crate::R; +#[doc = "Register `RESET_EN` writer"] +pub type W = crate::W; +#[doc = "Field `RST_EN_LP_TSENS` reader - need_des"] +pub type RST_EN_LP_TSENS_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_TSENS` writer - need_des"] +pub type RST_EN_LP_TSENS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_PMS` reader - need_des"] +pub type RST_EN_LP_PMS_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_PMS` writer - need_des"] +pub type RST_EN_LP_PMS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_EFUSE` reader - need_des"] +pub type RST_EN_LP_EFUSE_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_EFUSE` writer - need_des"] +pub type RST_EN_LP_EFUSE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_IOMUX` reader - need_des"] +pub type RST_EN_LP_IOMUX_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_IOMUX` writer - need_des"] +pub type RST_EN_LP_IOMUX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_TOUCH` reader - need_des"] +pub type RST_EN_LP_TOUCH_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_TOUCH` writer - need_des"] +pub type RST_EN_LP_TOUCH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_SPI` reader - need_des"] +pub type RST_EN_LP_SPI_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_SPI` writer - need_des"] +pub type RST_EN_LP_SPI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_ADC` reader - need_des"] +pub type RST_EN_LP_ADC_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_ADC` writer - need_des"] +pub type RST_EN_LP_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_I2S` reader - need_des"] +pub type RST_EN_LP_I2S_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_I2S` writer - need_des"] +pub type RST_EN_LP_I2S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_I2CMST` reader - need_des"] +pub type RST_EN_LP_I2CMST_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_I2CMST` writer - need_des"] +pub type RST_EN_LP_I2CMST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_I2C` reader - need_des"] +pub type RST_EN_LP_I2C_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_I2C` writer - need_des"] +pub type RST_EN_LP_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_UART` reader - need_des"] +pub type RST_EN_LP_UART_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_UART` writer - need_des"] +pub type RST_EN_LP_UART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_INTR` reader - need_des"] +pub type RST_EN_LP_INTR_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_INTR` writer - need_des"] +pub type RST_EN_LP_INTR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_ROM` reader - need_des"] +pub type RST_EN_LP_ROM_R = crate::BitReader; +#[doc = "Field `RST_EN_LP_ROM` writer - need_des"] +pub type RST_EN_LP_ROM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_EN_LP_CORE` writer - need_des"] +pub type RST_EN_LP_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 18 - need_des"] + #[inline(always)] + pub fn rst_en_lp_tsens(&self) -> RST_EN_LP_TSENS_R { + RST_EN_LP_TSENS_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - need_des"] + #[inline(always)] + pub fn rst_en_lp_pms(&self) -> RST_EN_LP_PMS_R { + RST_EN_LP_PMS_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - need_des"] + #[inline(always)] + pub fn rst_en_lp_efuse(&self) -> RST_EN_LP_EFUSE_R { + RST_EN_LP_EFUSE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - need_des"] + #[inline(always)] + pub fn rst_en_lp_iomux(&self) -> RST_EN_LP_IOMUX_R { + RST_EN_LP_IOMUX_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + pub fn rst_en_lp_touch(&self) -> RST_EN_LP_TOUCH_R { + RST_EN_LP_TOUCH_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - need_des"] + #[inline(always)] + pub fn rst_en_lp_spi(&self) -> RST_EN_LP_SPI_R { + RST_EN_LP_SPI_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + pub fn rst_en_lp_adc(&self) -> RST_EN_LP_ADC_R { + RST_EN_LP_ADC_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn rst_en_lp_i2s(&self) -> RST_EN_LP_I2S_R { + RST_EN_LP_I2S_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn rst_en_lp_i2cmst(&self) -> RST_EN_LP_I2CMST_R { + RST_EN_LP_I2CMST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn rst_en_lp_i2c(&self) -> RST_EN_LP_I2C_R { + RST_EN_LP_I2C_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn rst_en_lp_uart(&self) -> RST_EN_LP_UART_R { + RST_EN_LP_UART_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn rst_en_lp_intr(&self) -> RST_EN_LP_INTR_R { + RST_EN_LP_INTR_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn rst_en_lp_rom(&self) -> RST_EN_LP_ROM_R { + RST_EN_LP_ROM_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESET_EN") + .field( + "rst_en_lp_tsens", + &format_args!("{}", self.rst_en_lp_tsens().bit()), + ) + .field( + "rst_en_lp_pms", + &format_args!("{}", self.rst_en_lp_pms().bit()), + ) + .field( + "rst_en_lp_efuse", + &format_args!("{}", self.rst_en_lp_efuse().bit()), + ) + .field( + "rst_en_lp_iomux", + &format_args!("{}", self.rst_en_lp_iomux().bit()), + ) + .field( + "rst_en_lp_touch", + &format_args!("{}", self.rst_en_lp_touch().bit()), + ) + .field( + "rst_en_lp_spi", + &format_args!("{}", self.rst_en_lp_spi().bit()), + ) + .field( + "rst_en_lp_adc", + &format_args!("{}", self.rst_en_lp_adc().bit()), + ) + .field( + "rst_en_lp_i2s", + &format_args!("{}", self.rst_en_lp_i2s().bit()), + ) + .field( + "rst_en_lp_i2cmst", + &format_args!("{}", self.rst_en_lp_i2cmst().bit()), + ) + .field( + "rst_en_lp_i2c", + &format_args!("{}", self.rst_en_lp_i2c().bit()), + ) + .field( + "rst_en_lp_uart", + &format_args!("{}", self.rst_en_lp_uart().bit()), + ) + .field( + "rst_en_lp_intr", + &format_args!("{}", self.rst_en_lp_intr().bit()), + ) + .field( + "rst_en_lp_rom", + &format_args!("{}", self.rst_en_lp_rom().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 18 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_tsens(&mut self) -> RST_EN_LP_TSENS_W { + RST_EN_LP_TSENS_W::new(self, 18) + } + #[doc = "Bit 19 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_pms(&mut self) -> RST_EN_LP_PMS_W { + RST_EN_LP_PMS_W::new(self, 19) + } + #[doc = "Bit 20 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_efuse(&mut self) -> RST_EN_LP_EFUSE_W { + RST_EN_LP_EFUSE_W::new(self, 20) + } + #[doc = "Bit 21 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_iomux(&mut self) -> RST_EN_LP_IOMUX_W { + RST_EN_LP_IOMUX_W::new(self, 21) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_touch(&mut self) -> RST_EN_LP_TOUCH_W { + RST_EN_LP_TOUCH_W::new(self, 22) + } + #[doc = "Bit 23 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_spi(&mut self) -> RST_EN_LP_SPI_W { + RST_EN_LP_SPI_W::new(self, 23) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_adc(&mut self) -> RST_EN_LP_ADC_W { + RST_EN_LP_ADC_W::new(self, 24) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_i2s(&mut self) -> RST_EN_LP_I2S_W { + RST_EN_LP_I2S_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_i2cmst(&mut self) -> RST_EN_LP_I2CMST_W { + RST_EN_LP_I2CMST_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_i2c(&mut self) -> RST_EN_LP_I2C_W { + RST_EN_LP_I2C_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_uart(&mut self) -> RST_EN_LP_UART_W { + RST_EN_LP_UART_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_intr(&mut self) -> RST_EN_LP_INTR_W { + RST_EN_LP_INTR_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_rom(&mut self) -> RST_EN_LP_ROM_W { + RST_EN_LP_ROM_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn rst_en_lp_core(&mut self) -> RST_EN_LP_CORE_W { + RST_EN_LP_CORE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESET_EN_SPEC; +impl crate::RegisterSpec for RESET_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reset_en::R`](R) reader structure"] +impl crate::Readable for RESET_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reset_en::W`](W) writer structure"] +impl crate::Writable for RESET_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESET_EN to value 0"] +impl crate::Resettable for RESET_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys.rs b/esp32p4/src/lp_sys.rs new file mode 100644 index 0000000000..abab78463d --- /dev/null +++ b/esp32p4/src/lp_sys.rs @@ -0,0 +1,699 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + lp_sys_ver_date: LP_SYS_VER_DATE, + clk_sel_ctrl: CLK_SEL_CTRL, + sys_ctrl: SYS_CTRL, + lp_clk_ctrl: LP_CLK_CTRL, + lp_rst_ctrl: LP_RST_CTRL, + _reserved5: [u8; 0x04], + lp_core_boot_addr: LP_CORE_BOOT_ADDR, + ext_wakeup1: EXT_WAKEUP1, + ext_wakeup1_status: EXT_WAKEUP1_STATUS, + lp_tcm_pwr_ctrl: LP_TCM_PWR_CTRL, + boot_addr_hp_lp: BOOT_ADDR_HP_LP, + lp_store0: LP_STORE0, + lp_store1: LP_STORE1, + lp_store2: LP_STORE2, + lp_store3: LP_STORE3, + lp_store4: LP_STORE4, + lp_store5: LP_STORE5, + lp_store6: LP_STORE6, + lp_store7: LP_STORE7, + lp_store8: LP_STORE8, + lp_store9: LP_STORE9, + lp_store10: LP_STORE10, + lp_store11: LP_STORE11, + lp_store12: LP_STORE12, + lp_store13: LP_STORE13, + lp_store14: LP_STORE14, + lp_store15: LP_STORE15, + lp_probea_ctrl: LP_PROBEA_CTRL, + lp_probeb_ctrl: LP_PROBEB_CTRL, + lp_probe_out: LP_PROBE_OUT, + _reserved29: [u8; 0x24], + f2s_apb_brg_cntl: F2S_APB_BRG_CNTL, + _reserved30: [u8; 0x60], + usb_ctrl: USB_CTRL, + _reserved31: [u8; 0x08], + ana_xpd_pad_group: ANA_XPD_PAD_GROUP, + lp_tcm_ram_rdn_eco_cs: LP_TCM_RAM_RDN_ECO_CS, + lp_tcm_ram_rdn_eco_low: LP_TCM_RAM_RDN_ECO_LOW, + lp_tcm_ram_rdn_eco_high: LP_TCM_RAM_RDN_ECO_HIGH, + lp_tcm_rom_rdn_eco_cs: LP_TCM_ROM_RDN_ECO_CS, + lp_tcm_rom_rdn_eco_low: LP_TCM_ROM_RDN_ECO_LOW, + lp_tcm_rom_rdn_eco_high: LP_TCM_ROM_RDN_ECO_HIGH, + _reserved38: [u8; 0x08], + hp_root_clk_ctrl: HP_ROOT_CLK_CTRL, + _reserved39: [u8; 0x04], + lp_pmu_rdn_eco_low: LP_PMU_RDN_ECO_LOW, + lp_pmu_rdn_eco_high: LP_PMU_RDN_ECO_HIGH, + _reserved41: [u8; 0x08], + pad_comp0: PAD_COMP0, + pad_comp1: PAD_COMP1, + _reserved43: [u8; 0x04], + backup_dma_cfg0: BACKUP_DMA_CFG0, + backup_dma_cfg1: BACKUP_DMA_CFG1, + backup_dma_cfg2: BACKUP_DMA_CFG2, + _reserved46: [u8; 0x04], + boot_addr_hp_core1: BOOT_ADDR_HP_CORE1, + lp_addrhole_addr: LP_ADDRHOLE_ADDR, + lp_addrhole_info: LP_ADDRHOLE_INFO, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + hp_mem_aux_ctrl: HP_MEM_AUX_CTRL, + lp_mem_aux_ctrl: LP_MEM_AUX_CTRL, + hp_rom_aux_ctrl: HP_ROM_AUX_CTRL, + lp_rom_aux_ctrl: LP_ROM_AUX_CTRL, + lp_cpu_dbg_pc: LP_CPU_DBG_PC, + lp_cpu_exc_pc: LP_CPU_EXC_PC, + idbus_addrhole_addr: IDBUS_ADDRHOLE_ADDR, + idbus_addrhole_info: IDBUS_ADDRHOLE_INFO, + hp_por_rst_bypass_ctrl: HP_POR_RST_BYPASS_CTRL, + rng_data: RNG_DATA, + _reserved63: [u8; 0x08], + lp_core_ahb_timeout: LP_CORE_AHB_TIMEOUT, + lp_core_ibus_timeout: LP_CORE_IBUS_TIMEOUT, + lp_core_dbus_timeout: LP_CORE_DBUS_TIMEOUT, + lp_core_err_resp_dis: LP_CORE_ERR_RESP_DIS, + rng_cfg: RNG_CFG, +} +impl RegisterBlock { + #[doc = "0x00 - need_des"] + #[inline(always)] + pub const fn lp_sys_ver_date(&self) -> &LP_SYS_VER_DATE { + &self.lp_sys_ver_date + } + #[doc = "0x04 - need_des"] + #[inline(always)] + pub const fn clk_sel_ctrl(&self) -> &CLK_SEL_CTRL { + &self.clk_sel_ctrl + } + #[doc = "0x08 - need_des"] + #[inline(always)] + pub const fn sys_ctrl(&self) -> &SYS_CTRL { + &self.sys_ctrl + } + #[doc = "0x0c - need_des"] + #[inline(always)] + pub const fn lp_clk_ctrl(&self) -> &LP_CLK_CTRL { + &self.lp_clk_ctrl + } + #[doc = "0x10 - need_des"] + #[inline(always)] + pub const fn lp_rst_ctrl(&self) -> &LP_RST_CTRL { + &self.lp_rst_ctrl + } + #[doc = "0x18 - need_des"] + #[inline(always)] + pub const fn lp_core_boot_addr(&self) -> &LP_CORE_BOOT_ADDR { + &self.lp_core_boot_addr + } + #[doc = "0x1c - need_des"] + #[inline(always)] + pub const fn ext_wakeup1(&self) -> &EXT_WAKEUP1 { + &self.ext_wakeup1 + } + #[doc = "0x20 - need_des"] + #[inline(always)] + pub const fn ext_wakeup1_status(&self) -> &EXT_WAKEUP1_STATUS { + &self.ext_wakeup1_status + } + #[doc = "0x24 - need_des"] + #[inline(always)] + pub const fn lp_tcm_pwr_ctrl(&self) -> &LP_TCM_PWR_CTRL { + &self.lp_tcm_pwr_ctrl + } + #[doc = "0x28 - need_des"] + #[inline(always)] + pub const fn boot_addr_hp_lp(&self) -> &BOOT_ADDR_HP_LP { + &self.boot_addr_hp_lp + } + #[doc = "0x2c - need_des"] + #[inline(always)] + pub const fn lp_store0(&self) -> &LP_STORE0 { + &self.lp_store0 + } + #[doc = "0x30 - need_des"] + #[inline(always)] + pub const fn lp_store1(&self) -> &LP_STORE1 { + &self.lp_store1 + } + #[doc = "0x34 - need_des"] + #[inline(always)] + pub const fn lp_store2(&self) -> &LP_STORE2 { + &self.lp_store2 + } + #[doc = "0x38 - need_des"] + #[inline(always)] + pub const fn lp_store3(&self) -> &LP_STORE3 { + &self.lp_store3 + } + #[doc = "0x3c - need_des"] + #[inline(always)] + pub const fn lp_store4(&self) -> &LP_STORE4 { + &self.lp_store4 + } + #[doc = "0x40 - need_des"] + #[inline(always)] + pub const fn lp_store5(&self) -> &LP_STORE5 { + &self.lp_store5 + } + #[doc = "0x44 - need_des"] + #[inline(always)] + pub const fn lp_store6(&self) -> &LP_STORE6 { + &self.lp_store6 + } + #[doc = "0x48 - need_des"] + #[inline(always)] + pub const fn lp_store7(&self) -> &LP_STORE7 { + &self.lp_store7 + } + #[doc = "0x4c - need_des"] + #[inline(always)] + pub const fn lp_store8(&self) -> &LP_STORE8 { + &self.lp_store8 + } + #[doc = "0x50 - need_des"] + #[inline(always)] + pub const fn lp_store9(&self) -> &LP_STORE9 { + &self.lp_store9 + } + #[doc = "0x54 - need_des"] + #[inline(always)] + pub const fn lp_store10(&self) -> &LP_STORE10 { + &self.lp_store10 + } + #[doc = "0x58 - need_des"] + #[inline(always)] + pub const fn lp_store11(&self) -> &LP_STORE11 { + &self.lp_store11 + } + #[doc = "0x5c - need_des"] + #[inline(always)] + pub const fn lp_store12(&self) -> &LP_STORE12 { + &self.lp_store12 + } + #[doc = "0x60 - need_des"] + #[inline(always)] + pub const fn lp_store13(&self) -> &LP_STORE13 { + &self.lp_store13 + } + #[doc = "0x64 - need_des"] + #[inline(always)] + pub const fn lp_store14(&self) -> &LP_STORE14 { + &self.lp_store14 + } + #[doc = "0x68 - need_des"] + #[inline(always)] + pub const fn lp_store15(&self) -> &LP_STORE15 { + &self.lp_store15 + } + #[doc = "0x6c - need_des"] + #[inline(always)] + pub const fn lp_probea_ctrl(&self) -> &LP_PROBEA_CTRL { + &self.lp_probea_ctrl + } + #[doc = "0x70 - need_des"] + #[inline(always)] + pub const fn lp_probeb_ctrl(&self) -> &LP_PROBEB_CTRL { + &self.lp_probeb_ctrl + } + #[doc = "0x74 - need_des"] + #[inline(always)] + pub const fn lp_probe_out(&self) -> &LP_PROBE_OUT { + &self.lp_probe_out + } + #[doc = "0x9c - need_des"] + #[inline(always)] + pub const fn f2s_apb_brg_cntl(&self) -> &F2S_APB_BRG_CNTL { + &self.f2s_apb_brg_cntl + } + #[doc = "0x100 - need_des"] + #[inline(always)] + pub const fn usb_ctrl(&self) -> &USB_CTRL { + &self.usb_ctrl + } + #[doc = "0x10c - need_des"] + #[inline(always)] + pub const fn ana_xpd_pad_group(&self) -> &ANA_XPD_PAD_GROUP { + &self.ana_xpd_pad_group + } + #[doc = "0x110 - need_des"] + #[inline(always)] + pub const fn lp_tcm_ram_rdn_eco_cs(&self) -> &LP_TCM_RAM_RDN_ECO_CS { + &self.lp_tcm_ram_rdn_eco_cs + } + #[doc = "0x114 - need_des"] + #[inline(always)] + pub const fn lp_tcm_ram_rdn_eco_low(&self) -> &LP_TCM_RAM_RDN_ECO_LOW { + &self.lp_tcm_ram_rdn_eco_low + } + #[doc = "0x118 - need_des"] + #[inline(always)] + pub const fn lp_tcm_ram_rdn_eco_high(&self) -> &LP_TCM_RAM_RDN_ECO_HIGH { + &self.lp_tcm_ram_rdn_eco_high + } + #[doc = "0x11c - need_des"] + #[inline(always)] + pub const fn lp_tcm_rom_rdn_eco_cs(&self) -> &LP_TCM_ROM_RDN_ECO_CS { + &self.lp_tcm_rom_rdn_eco_cs + } + #[doc = "0x120 - need_des"] + #[inline(always)] + pub const fn lp_tcm_rom_rdn_eco_low(&self) -> &LP_TCM_ROM_RDN_ECO_LOW { + &self.lp_tcm_rom_rdn_eco_low + } + #[doc = "0x124 - need_des"] + #[inline(always)] + pub const fn lp_tcm_rom_rdn_eco_high(&self) -> &LP_TCM_ROM_RDN_ECO_HIGH { + &self.lp_tcm_rom_rdn_eco_high + } + #[doc = "0x130 - need_des"] + #[inline(always)] + pub const fn hp_root_clk_ctrl(&self) -> &HP_ROOT_CLK_CTRL { + &self.hp_root_clk_ctrl + } + #[doc = "0x138 - need_des"] + #[inline(always)] + pub const fn lp_pmu_rdn_eco_low(&self) -> &LP_PMU_RDN_ECO_LOW { + &self.lp_pmu_rdn_eco_low + } + #[doc = "0x13c - need_des"] + #[inline(always)] + pub const fn lp_pmu_rdn_eco_high(&self) -> &LP_PMU_RDN_ECO_HIGH { + &self.lp_pmu_rdn_eco_high + } + #[doc = "0x148 - need_des"] + #[inline(always)] + pub const fn pad_comp0(&self) -> &PAD_COMP0 { + &self.pad_comp0 + } + #[doc = "0x14c - need_des"] + #[inline(always)] + pub const fn pad_comp1(&self) -> &PAD_COMP1 { + &self.pad_comp1 + } + #[doc = "0x154 - need_des"] + #[inline(always)] + pub const fn backup_dma_cfg0(&self) -> &BACKUP_DMA_CFG0 { + &self.backup_dma_cfg0 + } + #[doc = "0x158 - need_des"] + #[inline(always)] + pub const fn backup_dma_cfg1(&self) -> &BACKUP_DMA_CFG1 { + &self.backup_dma_cfg1 + } + #[doc = "0x15c - need_des"] + #[inline(always)] + pub const fn backup_dma_cfg2(&self) -> &BACKUP_DMA_CFG2 { + &self.backup_dma_cfg2 + } + #[doc = "0x164 - need_des"] + #[inline(always)] + pub const fn boot_addr_hp_core1(&self) -> &BOOT_ADDR_HP_CORE1 { + &self.boot_addr_hp_core1 + } + #[doc = "0x168 - need_des"] + #[inline(always)] + pub const fn lp_addrhole_addr(&self) -> &LP_ADDRHOLE_ADDR { + &self.lp_addrhole_addr + } + #[doc = "0x16c - need_des"] + #[inline(always)] + pub const fn lp_addrhole_info(&self) -> &LP_ADDRHOLE_INFO { + &self.lp_addrhole_info + } + #[doc = "0x170 - raw interrupt register"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x174 - masked interrupt register"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x178 - masked interrupt register"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x17c - interrupt clear register"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x180 - need_des"] + #[inline(always)] + pub const fn hp_mem_aux_ctrl(&self) -> &HP_MEM_AUX_CTRL { + &self.hp_mem_aux_ctrl + } + #[doc = "0x184 - need_des"] + #[inline(always)] + pub const fn lp_mem_aux_ctrl(&self) -> &LP_MEM_AUX_CTRL { + &self.lp_mem_aux_ctrl + } + #[doc = "0x188 - need_des"] + #[inline(always)] + pub const fn hp_rom_aux_ctrl(&self) -> &HP_ROM_AUX_CTRL { + &self.hp_rom_aux_ctrl + } + #[doc = "0x18c - need_des"] + #[inline(always)] + pub const fn lp_rom_aux_ctrl(&self) -> &LP_ROM_AUX_CTRL { + &self.lp_rom_aux_ctrl + } + #[doc = "0x190 - need_des"] + #[inline(always)] + pub const fn lp_cpu_dbg_pc(&self) -> &LP_CPU_DBG_PC { + &self.lp_cpu_dbg_pc + } + #[doc = "0x194 - need_des"] + #[inline(always)] + pub const fn lp_cpu_exc_pc(&self) -> &LP_CPU_EXC_PC { + &self.lp_cpu_exc_pc + } + #[doc = "0x198 - need_des"] + #[inline(always)] + pub const fn idbus_addrhole_addr(&self) -> &IDBUS_ADDRHOLE_ADDR { + &self.idbus_addrhole_addr + } + #[doc = "0x19c - need_des"] + #[inline(always)] + pub const fn idbus_addrhole_info(&self) -> &IDBUS_ADDRHOLE_INFO { + &self.idbus_addrhole_info + } + #[doc = "0x1a0 - need_des"] + #[inline(always)] + pub const fn hp_por_rst_bypass_ctrl(&self) -> &HP_POR_RST_BYPASS_CTRL { + &self.hp_por_rst_bypass_ctrl + } + #[doc = "0x1a4 - rng data register"] + #[inline(always)] + pub const fn rng_data(&self) -> &RNG_DATA { + &self.rng_data + } + #[doc = "0x1b0 - need_des"] + #[inline(always)] + pub const fn lp_core_ahb_timeout(&self) -> &LP_CORE_AHB_TIMEOUT { + &self.lp_core_ahb_timeout + } + #[doc = "0x1b4 - need_des"] + #[inline(always)] + pub const fn lp_core_ibus_timeout(&self) -> &LP_CORE_IBUS_TIMEOUT { + &self.lp_core_ibus_timeout + } + #[doc = "0x1b8 - need_des"] + #[inline(always)] + pub const fn lp_core_dbus_timeout(&self) -> &LP_CORE_DBUS_TIMEOUT { + &self.lp_core_dbus_timeout + } + #[doc = "0x1bc - need_des"] + #[inline(always)] + pub const fn lp_core_err_resp_dis(&self) -> &LP_CORE_ERR_RESP_DIS { + &self.lp_core_err_resp_dis + } + #[doc = "0x1c0 - rng cfg register"] + #[inline(always)] + pub const fn rng_cfg(&self) -> &RNG_CFG { + &self.rng_cfg + } +} +#[doc = "LP_SYS_VER_DATE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sys_ver_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sys_ver_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sys_ver_date`] module"] +pub type LP_SYS_VER_DATE = crate::Reg; +#[doc = "need_des"] +pub mod lp_sys_ver_date; +#[doc = "CLK_SEL_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sel_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sel_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_sel_ctrl`] module"] +pub type CLK_SEL_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod clk_sel_ctrl; +#[doc = "SYS_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_ctrl`] module"] +pub type SYS_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod sys_ctrl; +#[doc = "LP_CLK_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_clk_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_clk_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_clk_ctrl`] module"] +pub type LP_CLK_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod lp_clk_ctrl; +#[doc = "LP_RST_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_rst_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_rst_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_rst_ctrl`] module"] +pub type LP_RST_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod lp_rst_ctrl; +#[doc = "LP_CORE_BOOT_ADDR (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_core_boot_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_core_boot_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_core_boot_addr`] module"] +pub type LP_CORE_BOOT_ADDR = crate::Reg; +#[doc = "need_des"] +pub mod lp_core_boot_addr; +#[doc = "EXT_WAKEUP1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_wakeup1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_wakeup1`] module"] +pub type EXT_WAKEUP1 = crate::Reg; +#[doc = "need_des"] +pub mod ext_wakeup1; +#[doc = "EXT_WAKEUP1_STATUS (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup1_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_wakeup1_status`] module"] +pub type EXT_WAKEUP1_STATUS = crate::Reg; +#[doc = "need_des"] +pub mod ext_wakeup1_status; +#[doc = "LP_TCM_PWR_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_pwr_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_pwr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_tcm_pwr_ctrl`] module"] +pub type LP_TCM_PWR_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod lp_tcm_pwr_ctrl; +#[doc = "BOOT_ADDR_HP_LP (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`boot_addr_hp_lp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`boot_addr_hp_lp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@boot_addr_hp_lp`] module"] +pub type BOOT_ADDR_HP_LP = crate::Reg; +#[doc = "need_des"] +pub mod boot_addr_hp_lp; +#[doc = "LP_STORE0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store0`] module"] +pub type LP_STORE0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store0; +#[doc = "LP_STORE1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store1`] module"] +pub type LP_STORE1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store1; +#[doc = "LP_STORE2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store2`] module"] +pub type LP_STORE2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store2; +#[doc = "LP_STORE3 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store3`] module"] +pub type LP_STORE3 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store3; +#[doc = "LP_STORE4 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store4`] module"] +pub type LP_STORE4 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store4; +#[doc = "LP_STORE5 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store5`] module"] +pub type LP_STORE5 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store5; +#[doc = "LP_STORE6 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store6`] module"] +pub type LP_STORE6 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store6; +#[doc = "LP_STORE7 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store7`] module"] +pub type LP_STORE7 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store7; +#[doc = "LP_STORE8 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store8`] module"] +pub type LP_STORE8 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store8; +#[doc = "LP_STORE9 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store9`] module"] +pub type LP_STORE9 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store9; +#[doc = "LP_STORE10 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store10`] module"] +pub type LP_STORE10 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store10; +#[doc = "LP_STORE11 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store11`] module"] +pub type LP_STORE11 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store11; +#[doc = "LP_STORE12 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store12`] module"] +pub type LP_STORE12 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store12; +#[doc = "LP_STORE13 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store13`] module"] +pub type LP_STORE13 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store13; +#[doc = "LP_STORE14 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store14`] module"] +pub type LP_STORE14 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store14; +#[doc = "LP_STORE15 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_store15`] module"] +pub type LP_STORE15 = crate::Reg; +#[doc = "need_des"] +pub mod lp_store15; +#[doc = "LP_PROBEA_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_probea_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_probea_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_probea_ctrl`] module"] +pub type LP_PROBEA_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod lp_probea_ctrl; +#[doc = "LP_PROBEB_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_probeb_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_probeb_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_probeb_ctrl`] module"] +pub type LP_PROBEB_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod lp_probeb_ctrl; +#[doc = "LP_PROBE_OUT (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_probe_out::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_probe_out`] module"] +pub type LP_PROBE_OUT = crate::Reg; +#[doc = "need_des"] +pub mod lp_probe_out; +#[doc = "F2S_APB_BRG_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`f2s_apb_brg_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`f2s_apb_brg_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@f2s_apb_brg_cntl`] module"] +pub type F2S_APB_BRG_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod f2s_apb_brg_cntl; +#[doc = "USB_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb_ctrl`] module"] +pub type USB_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod usb_ctrl; +#[doc = "ANA_XPD_PAD_GROUP (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_xpd_pad_group::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_xpd_pad_group::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_xpd_pad_group`] module"] +pub type ANA_XPD_PAD_GROUP = crate::Reg; +#[doc = "need_des"] +pub mod ana_xpd_pad_group; +#[doc = "LP_TCM_RAM_RDN_ECO_CS (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_ram_rdn_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_ram_rdn_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_tcm_ram_rdn_eco_cs`] module"] +pub type LP_TCM_RAM_RDN_ECO_CS = crate::Reg; +#[doc = "need_des"] +pub mod lp_tcm_ram_rdn_eco_cs; +#[doc = "LP_TCM_RAM_RDN_ECO_LOW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_ram_rdn_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_ram_rdn_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_tcm_ram_rdn_eco_low`] module"] +pub type LP_TCM_RAM_RDN_ECO_LOW = crate::Reg; +#[doc = "need_des"] +pub mod lp_tcm_ram_rdn_eco_low; +#[doc = "LP_TCM_RAM_RDN_ECO_HIGH (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_ram_rdn_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_ram_rdn_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_tcm_ram_rdn_eco_high`] module"] +pub type LP_TCM_RAM_RDN_ECO_HIGH = + crate::Reg; +#[doc = "need_des"] +pub mod lp_tcm_ram_rdn_eco_high; +#[doc = "LP_TCM_ROM_RDN_ECO_CS (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_rom_rdn_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_rom_rdn_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_tcm_rom_rdn_eco_cs`] module"] +pub type LP_TCM_ROM_RDN_ECO_CS = crate::Reg; +#[doc = "need_des"] +pub mod lp_tcm_rom_rdn_eco_cs; +#[doc = "LP_TCM_ROM_RDN_ECO_LOW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_rom_rdn_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_rom_rdn_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_tcm_rom_rdn_eco_low`] module"] +pub type LP_TCM_ROM_RDN_ECO_LOW = crate::Reg; +#[doc = "need_des"] +pub mod lp_tcm_rom_rdn_eco_low; +#[doc = "LP_TCM_ROM_RDN_ECO_HIGH (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_rom_rdn_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_rom_rdn_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_tcm_rom_rdn_eco_high`] module"] +pub type LP_TCM_ROM_RDN_ECO_HIGH = + crate::Reg; +#[doc = "need_des"] +pub mod lp_tcm_rom_rdn_eco_high; +#[doc = "HP_ROOT_CLK_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_root_clk_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_root_clk_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_root_clk_ctrl`] module"] +pub type HP_ROOT_CLK_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod hp_root_clk_ctrl; +#[doc = "LP_PMU_RDN_ECO_LOW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_pmu_rdn_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_pmu_rdn_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_pmu_rdn_eco_low`] module"] +pub type LP_PMU_RDN_ECO_LOW = crate::Reg; +#[doc = "need_des"] +pub mod lp_pmu_rdn_eco_low; +#[doc = "LP_PMU_RDN_ECO_HIGH (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_pmu_rdn_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_pmu_rdn_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_pmu_rdn_eco_high`] module"] +pub type LP_PMU_RDN_ECO_HIGH = crate::Reg; +#[doc = "need_des"] +pub mod lp_pmu_rdn_eco_high; +#[doc = "PAD_COMP0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_comp0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_comp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_comp0`] module"] +pub type PAD_COMP0 = crate::Reg; +#[doc = "need_des"] +pub mod pad_comp0; +#[doc = "PAD_COMP1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_comp1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_comp1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_comp1`] module"] +pub type PAD_COMP1 = crate::Reg; +#[doc = "need_des"] +pub mod pad_comp1; +#[doc = "BACKUP_DMA_CFG0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_dma_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`backup_dma_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@backup_dma_cfg0`] module"] +pub type BACKUP_DMA_CFG0 = crate::Reg; +#[doc = "need_des"] +pub mod backup_dma_cfg0; +#[doc = "BACKUP_DMA_CFG1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_dma_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`backup_dma_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@backup_dma_cfg1`] module"] +pub type BACKUP_DMA_CFG1 = crate::Reg; +#[doc = "need_des"] +pub mod backup_dma_cfg1; +#[doc = "BACKUP_DMA_CFG2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_dma_cfg2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`backup_dma_cfg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@backup_dma_cfg2`] module"] +pub type BACKUP_DMA_CFG2 = crate::Reg; +#[doc = "need_des"] +pub mod backup_dma_cfg2; +#[doc = "BOOT_ADDR_HP_CORE1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`boot_addr_hp_core1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`boot_addr_hp_core1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@boot_addr_hp_core1`] module"] +pub type BOOT_ADDR_HP_CORE1 = crate::Reg; +#[doc = "need_des"] +pub mod boot_addr_hp_core1; +#[doc = "LP_ADDRHOLE_ADDR (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_addrhole_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_addrhole_addr`] module"] +pub type LP_ADDRHOLE_ADDR = crate::Reg; +#[doc = "need_des"] +pub mod lp_addrhole_addr; +#[doc = "LP_ADDRHOLE_INFO (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_addrhole_info::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_addrhole_info`] module"] +pub type LP_ADDRHOLE_INFO = crate::Reg; +#[doc = "need_des"] +pub mod lp_addrhole_info; +#[doc = "INT_RAW (r) register accessor: raw interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "raw interrupt register"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "masked interrupt register"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "masked interrupt register"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "interrupt clear register"] +pub mod int_clr; +#[doc = "HP_MEM_AUX_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_mem_aux_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_mem_aux_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_mem_aux_ctrl`] module"] +pub type HP_MEM_AUX_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod hp_mem_aux_ctrl; +#[doc = "LP_MEM_AUX_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_mem_aux_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_mem_aux_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_mem_aux_ctrl`] module"] +pub type LP_MEM_AUX_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod lp_mem_aux_ctrl; +#[doc = "HP_ROM_AUX_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rom_aux_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rom_aux_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_rom_aux_ctrl`] module"] +pub type HP_ROM_AUX_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod hp_rom_aux_ctrl; +#[doc = "LP_ROM_AUX_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_rom_aux_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_rom_aux_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_rom_aux_ctrl`] module"] +pub type LP_ROM_AUX_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod lp_rom_aux_ctrl; +#[doc = "LP_CPU_DBG_PC (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_dbg_pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cpu_dbg_pc`] module"] +pub type LP_CPU_DBG_PC = crate::Reg; +#[doc = "need_des"] +pub mod lp_cpu_dbg_pc; +#[doc = "LP_CPU_EXC_PC (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_exc_pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cpu_exc_pc`] module"] +pub type LP_CPU_EXC_PC = crate::Reg; +#[doc = "need_des"] +pub mod lp_cpu_exc_pc; +#[doc = "IDBUS_ADDRHOLE_ADDR (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idbus_addrhole_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idbus_addrhole_addr`] module"] +pub type IDBUS_ADDRHOLE_ADDR = crate::Reg; +#[doc = "need_des"] +pub mod idbus_addrhole_addr; +#[doc = "IDBUS_ADDRHOLE_INFO (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idbus_addrhole_info::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idbus_addrhole_info`] module"] +pub type IDBUS_ADDRHOLE_INFO = crate::Reg; +#[doc = "need_des"] +pub mod idbus_addrhole_info; +#[doc = "HP_POR_RST_BYPASS_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_por_rst_bypass_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_por_rst_bypass_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_por_rst_bypass_ctrl`] module"] +pub type HP_POR_RST_BYPASS_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod hp_por_rst_bypass_ctrl; +#[doc = "RNG_DATA (r) register accessor: rng data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rng_data`] module"] +pub type RNG_DATA = crate::Reg; +#[doc = "rng data register"] +pub mod rng_data; +#[doc = "LP_CORE_AHB_TIMEOUT (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_core_ahb_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_core_ahb_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_core_ahb_timeout`] module"] +pub type LP_CORE_AHB_TIMEOUT = crate::Reg; +#[doc = "need_des"] +pub mod lp_core_ahb_timeout; +#[doc = "LP_CORE_IBUS_TIMEOUT (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_core_ibus_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_core_ibus_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_core_ibus_timeout`] module"] +pub type LP_CORE_IBUS_TIMEOUT = crate::Reg; +#[doc = "need_des"] +pub mod lp_core_ibus_timeout; +#[doc = "LP_CORE_DBUS_TIMEOUT (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_core_dbus_timeout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_core_dbus_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_core_dbus_timeout`] module"] +pub type LP_CORE_DBUS_TIMEOUT = crate::Reg; +#[doc = "need_des"] +pub mod lp_core_dbus_timeout; +#[doc = "LP_CORE_ERR_RESP_DIS (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_core_err_resp_dis::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_core_err_resp_dis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_core_err_resp_dis`] module"] +pub type LP_CORE_ERR_RESP_DIS = crate::Reg; +#[doc = "need_des"] +pub mod lp_core_err_resp_dis; +#[doc = "RNG_CFG (rw) register accessor: rng cfg register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rng_cfg`] module"] +pub type RNG_CFG = crate::Reg; +#[doc = "rng cfg register"] +pub mod rng_cfg; diff --git a/esp32p4/src/lp_sys/ana_xpd_pad_group.rs b/esp32p4/src/lp_sys/ana_xpd_pad_group.rs new file mode 100644 index 0000000000..a6dd39f039 --- /dev/null +++ b/esp32p4/src/lp_sys/ana_xpd_pad_group.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ANA_XPD_PAD_GROUP` reader"] +pub type R = crate::R; +#[doc = "Register `ANA_XPD_PAD_GROUP` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_REG_XPD_PAD_GROUP` reader - Set 1 to power up pad group"] +pub type ANA_REG_XPD_PAD_GROUP_R = crate::FieldReader; +#[doc = "Field `ANA_REG_XPD_PAD_GROUP` writer - Set 1 to power up pad group"] +pub type ANA_REG_XPD_PAD_GROUP_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Set 1 to power up pad group"] + #[inline(always)] + pub fn ana_reg_xpd_pad_group(&self) -> ANA_REG_XPD_PAD_GROUP_R { + ANA_REG_XPD_PAD_GROUP_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ANA_XPD_PAD_GROUP") + .field( + "ana_reg_xpd_pad_group", + &format_args!("{}", self.ana_reg_xpd_pad_group().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Set 1 to power up pad group"] + #[inline(always)] + #[must_use] + pub fn ana_reg_xpd_pad_group(&mut self) -> ANA_REG_XPD_PAD_GROUP_W { + ANA_REG_XPD_PAD_GROUP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_xpd_pad_group::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_xpd_pad_group::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ANA_XPD_PAD_GROUP_SPEC; +impl crate::RegisterSpec for ANA_XPD_PAD_GROUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ana_xpd_pad_group::R`](R) reader structure"] +impl crate::Readable for ANA_XPD_PAD_GROUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ana_xpd_pad_group::W`](W) writer structure"] +impl crate::Writable for ANA_XPD_PAD_GROUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ANA_XPD_PAD_GROUP to value 0xff"] +impl crate::Resettable for ANA_XPD_PAD_GROUP_SPEC { + const RESET_VALUE: Self::Ux = 0xff; +} diff --git a/esp32p4/src/lp_sys/backup_dma_cfg0.rs b/esp32p4/src/lp_sys/backup_dma_cfg0.rs new file mode 100644 index 0000000000..dcce2bcf2c --- /dev/null +++ b/esp32p4/src/lp_sys/backup_dma_cfg0.rs @@ -0,0 +1,125 @@ +#[doc = "Register `BACKUP_DMA_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `BACKUP_DMA_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `BURST_LIMIT_AON` reader - need_des"] +pub type BURST_LIMIT_AON_R = crate::FieldReader; +#[doc = "Field `BURST_LIMIT_AON` writer - need_des"] +pub type BURST_LIMIT_AON_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `READ_INTERVAL_AON` reader - need_des"] +pub type READ_INTERVAL_AON_R = crate::FieldReader; +#[doc = "Field `READ_INTERVAL_AON` writer - need_des"] +pub type READ_INTERVAL_AON_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `LINK_BACKUP_TOUT_THRES_AON` reader - need_des"] +pub type LINK_BACKUP_TOUT_THRES_AON_R = crate::FieldReader; +#[doc = "Field `LINK_BACKUP_TOUT_THRES_AON` writer - need_des"] +pub type LINK_BACKUP_TOUT_THRES_AON_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `LINK_TOUT_THRES_AON` reader - need_des"] +pub type LINK_TOUT_THRES_AON_R = crate::FieldReader; +#[doc = "Field `LINK_TOUT_THRES_AON` writer - need_des"] +pub type LINK_TOUT_THRES_AON_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + pub fn burst_limit_aon(&self) -> BURST_LIMIT_AON_R { + BURST_LIMIT_AON_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:11 - need_des"] + #[inline(always)] + pub fn read_interval_aon(&self) -> READ_INTERVAL_AON_R { + READ_INTERVAL_AON_R::new(((self.bits >> 5) & 0x7f) as u8) + } + #[doc = "Bits 12:21 - need_des"] + #[inline(always)] + pub fn link_backup_tout_thres_aon(&self) -> LINK_BACKUP_TOUT_THRES_AON_R { + LINK_BACKUP_TOUT_THRES_AON_R::new(((self.bits >> 12) & 0x03ff) as u16) + } + #[doc = "Bits 22:31 - need_des"] + #[inline(always)] + pub fn link_tout_thres_aon(&self) -> LINK_TOUT_THRES_AON_R { + LINK_TOUT_THRES_AON_R::new(((self.bits >> 22) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BACKUP_DMA_CFG0") + .field( + "burst_limit_aon", + &format_args!("{}", self.burst_limit_aon().bits()), + ) + .field( + "read_interval_aon", + &format_args!("{}", self.read_interval_aon().bits()), + ) + .field( + "link_backup_tout_thres_aon", + &format_args!("{}", self.link_backup_tout_thres_aon().bits()), + ) + .field( + "link_tout_thres_aon", + &format_args!("{}", self.link_tout_thres_aon().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + #[must_use] + pub fn burst_limit_aon(&mut self) -> BURST_LIMIT_AON_W { + BURST_LIMIT_AON_W::new(self, 0) + } + #[doc = "Bits 5:11 - need_des"] + #[inline(always)] + #[must_use] + pub fn read_interval_aon(&mut self) -> READ_INTERVAL_AON_W { + READ_INTERVAL_AON_W::new(self, 5) + } + #[doc = "Bits 12:21 - need_des"] + #[inline(always)] + #[must_use] + pub fn link_backup_tout_thres_aon( + &mut self, + ) -> LINK_BACKUP_TOUT_THRES_AON_W { + LINK_BACKUP_TOUT_THRES_AON_W::new(self, 12) + } + #[doc = "Bits 22:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn link_tout_thres_aon(&mut self) -> LINK_TOUT_THRES_AON_W { + LINK_TOUT_THRES_AON_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_dma_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`backup_dma_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BACKUP_DMA_CFG0_SPEC; +impl crate::RegisterSpec for BACKUP_DMA_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`backup_dma_cfg0::R`](R) reader structure"] +impl crate::Readable for BACKUP_DMA_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`backup_dma_cfg0::W`](W) writer structure"] +impl crate::Writable for BACKUP_DMA_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BACKUP_DMA_CFG0 to value 0x1906_414a"] +impl crate::Resettable for BACKUP_DMA_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0x1906_414a; +} diff --git a/esp32p4/src/lp_sys/backup_dma_cfg1.rs b/esp32p4/src/lp_sys/backup_dma_cfg1.rs new file mode 100644 index 0000000000..a28041561a --- /dev/null +++ b/esp32p4/src/lp_sys/backup_dma_cfg1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BACKUP_DMA_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `BACKUP_DMA_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `AON_BYPASS` reader - need_des"] +pub type AON_BYPASS_R = crate::BitReader; +#[doc = "Field `AON_BYPASS` writer - need_des"] +pub type AON_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn aon_bypass(&self) -> AON_BYPASS_R { + AON_BYPASS_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BACKUP_DMA_CFG1") + .field("aon_bypass", &format_args!("{}", self.aon_bypass().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn aon_bypass(&mut self) -> AON_BYPASS_W { + AON_BYPASS_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_dma_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`backup_dma_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BACKUP_DMA_CFG1_SPEC; +impl crate::RegisterSpec for BACKUP_DMA_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`backup_dma_cfg1::R`](R) reader structure"] +impl crate::Readable for BACKUP_DMA_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`backup_dma_cfg1::W`](W) writer structure"] +impl crate::Writable for BACKUP_DMA_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BACKUP_DMA_CFG1 to value 0"] +impl crate::Resettable for BACKUP_DMA_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/backup_dma_cfg2.rs b/esp32p4/src/lp_sys/backup_dma_cfg2.rs new file mode 100644 index 0000000000..5f0e1cce4f --- /dev/null +++ b/esp32p4/src/lp_sys/backup_dma_cfg2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `BACKUP_DMA_CFG2` reader"] +pub type R = crate::R; +#[doc = "Register `BACKUP_DMA_CFG2` writer"] +pub type W = crate::W; +#[doc = "Field `LINK_ADDR_AON` reader - need_des"] +pub type LINK_ADDR_AON_R = crate::FieldReader; +#[doc = "Field `LINK_ADDR_AON` writer - need_des"] +pub type LINK_ADDR_AON_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn link_addr_aon(&self) -> LINK_ADDR_AON_R { + LINK_ADDR_AON_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BACKUP_DMA_CFG2") + .field( + "link_addr_aon", + &format_args!("{}", self.link_addr_aon().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn link_addr_aon(&mut self) -> LINK_ADDR_AON_W { + LINK_ADDR_AON_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_dma_cfg2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`backup_dma_cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BACKUP_DMA_CFG2_SPEC; +impl crate::RegisterSpec for BACKUP_DMA_CFG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`backup_dma_cfg2::R`](R) reader structure"] +impl crate::Readable for BACKUP_DMA_CFG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`backup_dma_cfg2::W`](W) writer structure"] +impl crate::Writable for BACKUP_DMA_CFG2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BACKUP_DMA_CFG2 to value 0"] +impl crate::Resettable for BACKUP_DMA_CFG2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/boot_addr_hp_core1.rs b/esp32p4/src/lp_sys/boot_addr_hp_core1.rs new file mode 100644 index 0000000000..72320a0f81 --- /dev/null +++ b/esp32p4/src/lp_sys/boot_addr_hp_core1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `BOOT_ADDR_HP_CORE1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT_ADDR_HP_CORE1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOT_ADDR_HP_CORE1` reader - need_des"] +pub type BOOT_ADDR_HP_CORE1_R = crate::FieldReader; +#[doc = "Field `BOOT_ADDR_HP_CORE1` writer - need_des"] +pub type BOOT_ADDR_HP_CORE1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn boot_addr_hp_core1(&self) -> BOOT_ADDR_HP_CORE1_R { + BOOT_ADDR_HP_CORE1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BOOT_ADDR_HP_CORE1") + .field( + "boot_addr_hp_core1", + &format_args!("{}", self.boot_addr_hp_core1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn boot_addr_hp_core1(&mut self) -> BOOT_ADDR_HP_CORE1_W { + BOOT_ADDR_HP_CORE1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`boot_addr_hp_core1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`boot_addr_hp_core1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT_ADDR_HP_CORE1_SPEC; +impl crate::RegisterSpec for BOOT_ADDR_HP_CORE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot_addr_hp_core1::R`](R) reader structure"] +impl crate::Readable for BOOT_ADDR_HP_CORE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot_addr_hp_core1::W`](W) writer structure"] +impl crate::Writable for BOOT_ADDR_HP_CORE1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BOOT_ADDR_HP_CORE1 to value 0"] +impl crate::Resettable for BOOT_ADDR_HP_CORE1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/boot_addr_hp_lp.rs b/esp32p4/src/lp_sys/boot_addr_hp_lp.rs new file mode 100644 index 0000000000..50b690b229 --- /dev/null +++ b/esp32p4/src/lp_sys/boot_addr_hp_lp.rs @@ -0,0 +1,66 @@ +#[doc = "Register `BOOT_ADDR_HP_LP` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT_ADDR_HP_LP` writer"] +pub type W = crate::W; +#[doc = "Field `BOOT_ADDR_HP_LP` reader - need_des"] +pub type BOOT_ADDR_HP_LP_R = crate::FieldReader; +#[doc = "Field `BOOT_ADDR_HP_LP` writer - need_des"] +pub type BOOT_ADDR_HP_LP_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn boot_addr_hp_lp(&self) -> BOOT_ADDR_HP_LP_R { + BOOT_ADDR_HP_LP_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BOOT_ADDR_HP_LP") + .field( + "boot_addr_hp_lp", + &format_args!("{}", self.boot_addr_hp_lp().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn boot_addr_hp_lp(&mut self) -> BOOT_ADDR_HP_LP_W { + BOOT_ADDR_HP_LP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`boot_addr_hp_lp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`boot_addr_hp_lp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT_ADDR_HP_LP_SPEC; +impl crate::RegisterSpec for BOOT_ADDR_HP_LP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot_addr_hp_lp::R`](R) reader structure"] +impl crate::Readable for BOOT_ADDR_HP_LP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot_addr_hp_lp::W`](W) writer structure"] +impl crate::Writable for BOOT_ADDR_HP_LP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BOOT_ADDR_HP_LP to value 0"] +impl crate::Resettable for BOOT_ADDR_HP_LP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/clk_sel_ctrl.rs b/esp32p4/src/lp_sys/clk_sel_ctrl.rs new file mode 100644 index 0000000000..e2a65faeda --- /dev/null +++ b/esp32p4/src/lp_sys/clk_sel_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLK_SEL_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_SEL_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ENA_SW_SEL_SYS_CLK` reader - reserved"] +pub type ENA_SW_SEL_SYS_CLK_R = crate::BitReader; +#[doc = "Field `ENA_SW_SEL_SYS_CLK` writer - reserved"] +pub type ENA_SW_SEL_SYS_CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_SYS_CLK_SRC_SEL` reader - reserved"] +pub type SW_SYS_CLK_SRC_SEL_R = crate::BitReader; +#[doc = "Field `SW_SYS_CLK_SRC_SEL` writer - reserved"] +pub type SW_SYS_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 16 - reserved"] + #[inline(always)] + pub fn ena_sw_sel_sys_clk(&self) -> ENA_SW_SEL_SYS_CLK_R { + ENA_SW_SEL_SYS_CLK_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - reserved"] + #[inline(always)] + pub fn sw_sys_clk_src_sel(&self) -> SW_SYS_CLK_SRC_SEL_R { + SW_SYS_CLK_SRC_SEL_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_SEL_CTRL") + .field( + "ena_sw_sel_sys_clk", + &format_args!("{}", self.ena_sw_sel_sys_clk().bit()), + ) + .field( + "sw_sys_clk_src_sel", + &format_args!("{}", self.sw_sys_clk_src_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 16 - reserved"] + #[inline(always)] + #[must_use] + pub fn ena_sw_sel_sys_clk(&mut self) -> ENA_SW_SEL_SYS_CLK_W { + ENA_SW_SEL_SYS_CLK_W::new(self, 16) + } + #[doc = "Bit 17 - reserved"] + #[inline(always)] + #[must_use] + pub fn sw_sys_clk_src_sel(&mut self) -> SW_SYS_CLK_SRC_SEL_W { + SW_SYS_CLK_SRC_SEL_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_sel_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_sel_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_SEL_CTRL_SPEC; +impl crate::RegisterSpec for CLK_SEL_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_sel_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_SEL_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_sel_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_SEL_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_SEL_CTRL to value 0"] +impl crate::Resettable for CLK_SEL_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/ext_wakeup1.rs b/esp32p4/src/lp_sys/ext_wakeup1.rs new file mode 100644 index 0000000000..d9a73e05dd --- /dev/null +++ b/esp32p4/src/lp_sys/ext_wakeup1.rs @@ -0,0 +1,71 @@ +#[doc = "Register `EXT_WAKEUP1` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_WAKEUP1` writer"] +pub type W = crate::W; +#[doc = "Field `SEL` reader - Bitmap to select RTC pads for ext wakeup1"] +pub type SEL_R = crate::FieldReader; +#[doc = "Field `SEL` writer - Bitmap to select RTC pads for ext wakeup1"] +pub type SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `STATUS_CLR` writer - clear ext wakeup1 status"] +pub type STATUS_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Bitmap to select RTC pads for ext wakeup1"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_WAKEUP1") + .field("sel", &format_args!("{}", self.sel().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Bitmap to select RTC pads for ext wakeup1"] + #[inline(always)] + #[must_use] + pub fn sel(&mut self) -> SEL_W { + SEL_W::new(self, 0) + } + #[doc = "Bit 16 - clear ext wakeup1 status"] + #[inline(always)] + #[must_use] + pub fn status_clr(&mut self) -> STATUS_CLR_W { + STATUS_CLR_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_wakeup1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_WAKEUP1_SPEC; +impl crate::RegisterSpec for EXT_WAKEUP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_wakeup1::R`](R) reader structure"] +impl crate::Readable for EXT_WAKEUP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_wakeup1::W`](W) writer structure"] +impl crate::Writable for EXT_WAKEUP1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_WAKEUP1 to value 0"] +impl crate::Resettable for EXT_WAKEUP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/ext_wakeup1_status.rs b/esp32p4/src/lp_sys/ext_wakeup1_status.rs new file mode 100644 index 0000000000..92abbb680e --- /dev/null +++ b/esp32p4/src/lp_sys/ext_wakeup1_status.rs @@ -0,0 +1,39 @@ +#[doc = "Register `EXT_WAKEUP1_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `EXT_WAKEUP1_STATUS` reader - ext wakeup1 status"] +pub type EXT_WAKEUP1_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - ext wakeup1 status"] + #[inline(always)] + pub fn ext_wakeup1_status(&self) -> EXT_WAKEUP1_STATUS_R { + EXT_WAKEUP1_STATUS_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_WAKEUP1_STATUS") + .field( + "ext_wakeup1_status", + &format_args!("{}", self.ext_wakeup1_status().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup1_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_WAKEUP1_STATUS_SPEC; +impl crate::RegisterSpec for EXT_WAKEUP1_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_wakeup1_status::R`](R) reader structure"] +impl crate::Readable for EXT_WAKEUP1_STATUS_SPEC {} +#[doc = "`reset()` method sets EXT_WAKEUP1_STATUS to value 0"] +impl crate::Resettable for EXT_WAKEUP1_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/f2s_apb_brg_cntl.rs b/esp32p4/src/lp_sys/f2s_apb_brg_cntl.rs new file mode 100644 index 0000000000..303d30fcf0 --- /dev/null +++ b/esp32p4/src/lp_sys/f2s_apb_brg_cntl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `F2S_APB_BRG_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `F2S_APB_BRG_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `F2S_APB_POSTW_EN` reader - reserved"] +pub type F2S_APB_POSTW_EN_R = crate::BitReader; +#[doc = "Field `F2S_APB_POSTW_EN` writer - reserved"] +pub type F2S_APB_POSTW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - reserved"] + #[inline(always)] + pub fn f2s_apb_postw_en(&self) -> F2S_APB_POSTW_EN_R { + F2S_APB_POSTW_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("F2S_APB_BRG_CNTL") + .field( + "f2s_apb_postw_en", + &format_args!("{}", self.f2s_apb_postw_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - reserved"] + #[inline(always)] + #[must_use] + pub fn f2s_apb_postw_en(&mut self) -> F2S_APB_POSTW_EN_W { + F2S_APB_POSTW_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`f2s_apb_brg_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`f2s_apb_brg_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct F2S_APB_BRG_CNTL_SPEC; +impl crate::RegisterSpec for F2S_APB_BRG_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`f2s_apb_brg_cntl::R`](R) reader structure"] +impl crate::Readable for F2S_APB_BRG_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`f2s_apb_brg_cntl::W`](W) writer structure"] +impl crate::Writable for F2S_APB_BRG_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets F2S_APB_BRG_CNTL to value 0"] +impl crate::Resettable for F2S_APB_BRG_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/hp_mem_aux_ctrl.rs b/esp32p4/src/lp_sys/hp_mem_aux_ctrl.rs new file mode 100644 index 0000000000..6e11f414a6 --- /dev/null +++ b/esp32p4/src/lp_sys/hp_mem_aux_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_MEM_AUX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_MEM_AUX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MEM_AUX_CTRL` reader - need_des"] +pub type HP_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `HP_MEM_AUX_CTRL` writer - need_des"] +pub type HP_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn hp_mem_aux_ctrl(&self) -> HP_MEM_AUX_CTRL_R { + HP_MEM_AUX_CTRL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_MEM_AUX_CTRL") + .field( + "hp_mem_aux_ctrl", + &format_args!("{}", self.hp_mem_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_mem_aux_ctrl(&mut self) -> HP_MEM_AUX_CTRL_W { + HP_MEM_AUX_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_mem_aux_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_mem_aux_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MEM_AUX_CTRL_SPEC; +impl crate::RegisterSpec for HP_MEM_AUX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_mem_aux_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_MEM_AUX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_mem_aux_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_MEM_AUX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MEM_AUX_CTRL to value 0x2070"] +impl crate::Resettable for HP_MEM_AUX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x2070; +} diff --git a/esp32p4/src/lp_sys/hp_por_rst_bypass_ctrl.rs b/esp32p4/src/lp_sys/hp_por_rst_bypass_ctrl.rs new file mode 100644 index 0000000000..16ba76b593 --- /dev/null +++ b/esp32p4/src/lp_sys/hp_por_rst_bypass_ctrl.rs @@ -0,0 +1,89 @@ +#[doc = "Register `HP_POR_RST_BYPASS_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_POR_RST_BYPASS_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_PO_CNNT_RSTN_BYPASS_CTRL` reader - 15\\] 1'b1: po_cnnt_rstn bypass sys_sw_rstn \\[14\\] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn \\[13\\] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn \\[12\\] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn \\[11\\] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst \\[10\\] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst \\[9\\] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn \\[8\\] 1'b1: po_cnnt_rstn bypass efuse_err_rstn"] +pub type HP_PO_CNNT_RSTN_BYPASS_CTRL_R = crate::FieldReader; +#[doc = "Field `HP_PO_CNNT_RSTN_BYPASS_CTRL` writer - 15\\] 1'b1: po_cnnt_rstn bypass sys_sw_rstn \\[14\\] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn \\[13\\] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn \\[12\\] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn \\[11\\] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst \\[10\\] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst \\[9\\] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn \\[8\\] 1'b1: po_cnnt_rstn bypass efuse_err_rstn"] +pub type HP_PO_CNNT_RSTN_BYPASS_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HP_PO_RSTN_BYPASS_CTRL` reader - 31\\] 1'b1: po_rstn bypass sys_sw_rstn \\[30\\] 1'b1: po_rstn bypass hp_wdt_sys_rstn \\[29\\] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn \\[28\\] 1'b1: po_rstn bypass hp_sdio_sys_rstn \\[27\\] 1'b1: po_rstn bypass usb_jtag_chip_rst \\[26\\] 1'b1: po_rstn bypass usb_uart_chip_rst \\[25\\] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn \\[24\\] 1'b1: po_rstn bypass efuse_err_rstn"] +pub type HP_PO_RSTN_BYPASS_CTRL_R = crate::FieldReader; +#[doc = "Field `HP_PO_RSTN_BYPASS_CTRL` writer - 31\\] 1'b1: po_rstn bypass sys_sw_rstn \\[30\\] 1'b1: po_rstn bypass hp_wdt_sys_rstn \\[29\\] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn \\[28\\] 1'b1: po_rstn bypass hp_sdio_sys_rstn \\[27\\] 1'b1: po_rstn bypass usb_jtag_chip_rst \\[26\\] 1'b1: po_rstn bypass usb_uart_chip_rst \\[25\\] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn \\[24\\] 1'b1: po_rstn bypass efuse_err_rstn"] +pub type HP_PO_RSTN_BYPASS_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 8:15 - 15\\] 1'b1: po_cnnt_rstn bypass sys_sw_rstn \\[14\\] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn \\[13\\] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn \\[12\\] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn \\[11\\] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst \\[10\\] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst \\[9\\] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn \\[8\\] 1'b1: po_cnnt_rstn bypass efuse_err_rstn"] + #[inline(always)] + pub fn hp_po_cnnt_rstn_bypass_ctrl(&self) -> HP_PO_CNNT_RSTN_BYPASS_CTRL_R { + HP_PO_CNNT_RSTN_BYPASS_CTRL_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 24:31 - 31\\] 1'b1: po_rstn bypass sys_sw_rstn \\[30\\] 1'b1: po_rstn bypass hp_wdt_sys_rstn \\[29\\] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn \\[28\\] 1'b1: po_rstn bypass hp_sdio_sys_rstn \\[27\\] 1'b1: po_rstn bypass usb_jtag_chip_rst \\[26\\] 1'b1: po_rstn bypass usb_uart_chip_rst \\[25\\] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn \\[24\\] 1'b1: po_rstn bypass efuse_err_rstn"] + #[inline(always)] + pub fn hp_po_rstn_bypass_ctrl(&self) -> HP_PO_RSTN_BYPASS_CTRL_R { + HP_PO_RSTN_BYPASS_CTRL_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_POR_RST_BYPASS_CTRL") + .field( + "hp_po_cnnt_rstn_bypass_ctrl", + &format_args!("{}", self.hp_po_cnnt_rstn_bypass_ctrl().bits()), + ) + .field( + "hp_po_rstn_bypass_ctrl", + &format_args!("{}", self.hp_po_rstn_bypass_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 8:15 - 15\\] 1'b1: po_cnnt_rstn bypass sys_sw_rstn \\[14\\] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn \\[13\\] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn \\[12\\] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn \\[11\\] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst \\[10\\] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst \\[9\\] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn \\[8\\] 1'b1: po_cnnt_rstn bypass efuse_err_rstn"] + #[inline(always)] + #[must_use] + pub fn hp_po_cnnt_rstn_bypass_ctrl( + &mut self, + ) -> HP_PO_CNNT_RSTN_BYPASS_CTRL_W { + HP_PO_CNNT_RSTN_BYPASS_CTRL_W::new(self, 8) + } + #[doc = "Bits 24:31 - 31\\] 1'b1: po_rstn bypass sys_sw_rstn \\[30\\] 1'b1: po_rstn bypass hp_wdt_sys_rstn \\[29\\] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn \\[28\\] 1'b1: po_rstn bypass hp_sdio_sys_rstn \\[27\\] 1'b1: po_rstn bypass usb_jtag_chip_rst \\[26\\] 1'b1: po_rstn bypass usb_uart_chip_rst \\[25\\] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn \\[24\\] 1'b1: po_rstn bypass efuse_err_rstn"] + #[inline(always)] + #[must_use] + pub fn hp_po_rstn_bypass_ctrl( + &mut self, + ) -> HP_PO_RSTN_BYPASS_CTRL_W { + HP_PO_RSTN_BYPASS_CTRL_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_por_rst_bypass_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_por_rst_bypass_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_POR_RST_BYPASS_CTRL_SPEC; +impl crate::RegisterSpec for HP_POR_RST_BYPASS_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_por_rst_bypass_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_POR_RST_BYPASS_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_por_rst_bypass_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_POR_RST_BYPASS_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_POR_RST_BYPASS_CTRL to value 0xff00_ff00"] +impl crate::Resettable for HP_POR_RST_BYPASS_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0xff00_ff00; +} diff --git a/esp32p4/src/lp_sys/hp_rom_aux_ctrl.rs b/esp32p4/src/lp_sys/hp_rom_aux_ctrl.rs new file mode 100644 index 0000000000..f373b9bfc5 --- /dev/null +++ b/esp32p4/src/lp_sys/hp_rom_aux_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_ROM_AUX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ROM_AUX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ROM_AUX_CTRL` reader - need_des"] +pub type HP_ROM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `HP_ROM_AUX_CTRL` writer - need_des"] +pub type HP_ROM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn hp_rom_aux_ctrl(&self) -> HP_ROM_AUX_CTRL_R { + HP_ROM_AUX_CTRL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ROM_AUX_CTRL") + .field( + "hp_rom_aux_ctrl", + &format_args!("{}", self.hp_rom_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_rom_aux_ctrl(&mut self) -> HP_ROM_AUX_CTRL_W { + HP_ROM_AUX_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_rom_aux_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_rom_aux_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ROM_AUX_CTRL_SPEC; +impl crate::RegisterSpec for HP_ROM_AUX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_rom_aux_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_ROM_AUX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_rom_aux_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_ROM_AUX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ROM_AUX_CTRL to value 0x70"] +impl crate::Resettable for HP_ROM_AUX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x70; +} diff --git a/esp32p4/src/lp_sys/hp_root_clk_ctrl.rs b/esp32p4/src/lp_sys/hp_root_clk_ctrl.rs new file mode 100644 index 0000000000..7cdbaea6bd --- /dev/null +++ b/esp32p4/src/lp_sys/hp_root_clk_ctrl.rs @@ -0,0 +1,79 @@ +#[doc = "Register `HP_ROOT_CLK_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ROOT_CLK_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CPU_CLK_EN` reader - clock gate enable for hp cpu root 400M clk"] +pub type CPU_CLK_EN_R = crate::BitReader; +#[doc = "Field `CPU_CLK_EN` writer - clock gate enable for hp cpu root 400M clk"] +pub type CPU_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYS_CLK_EN` reader - clock gate enable for hp sys root 480M clk"] +pub type SYS_CLK_EN_R = crate::BitReader; +#[doc = "Field `SYS_CLK_EN` writer - clock gate enable for hp sys root 480M clk"] +pub type SYS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - clock gate enable for hp cpu root 400M clk"] + #[inline(always)] + pub fn cpu_clk_en(&self) -> CPU_CLK_EN_R { + CPU_CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - clock gate enable for hp sys root 480M clk"] + #[inline(always)] + pub fn sys_clk_en(&self) -> SYS_CLK_EN_R { + SYS_CLK_EN_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ROOT_CLK_CTRL") + .field("cpu_clk_en", &format_args!("{}", self.cpu_clk_en().bit())) + .field("sys_clk_en", &format_args!("{}", self.sys_clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - clock gate enable for hp cpu root 400M clk"] + #[inline(always)] + #[must_use] + pub fn cpu_clk_en(&mut self) -> CPU_CLK_EN_W { + CPU_CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - clock gate enable for hp sys root 480M clk"] + #[inline(always)] + #[must_use] + pub fn sys_clk_en(&mut self) -> SYS_CLK_EN_W { + SYS_CLK_EN_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_root_clk_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_root_clk_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ROOT_CLK_CTRL_SPEC; +impl crate::RegisterSpec for HP_ROOT_CLK_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_root_clk_ctrl::R`](R) reader structure"] +impl crate::Readable for HP_ROOT_CLK_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_root_clk_ctrl::W`](W) writer structure"] +impl crate::Writable for HP_ROOT_CLK_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ROOT_CLK_CTRL to value 0x03"] +impl crate::Resettable for HP_ROOT_CLK_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/lp_sys/idbus_addrhole_addr.rs b/esp32p4/src/lp_sys/idbus_addrhole_addr.rs new file mode 100644 index 0000000000..bbaa64b7eb --- /dev/null +++ b/esp32p4/src/lp_sys/idbus_addrhole_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `IDBUS_ADDRHOLE_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `IDBUS_ADDRHOLE_ADDR` reader - need_des"] +pub type IDBUS_ADDRHOLE_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn idbus_addrhole_addr(&self) -> IDBUS_ADDRHOLE_ADDR_R { + IDBUS_ADDRHOLE_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IDBUS_ADDRHOLE_ADDR") + .field( + "idbus_addrhole_addr", + &format_args!("{}", self.idbus_addrhole_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idbus_addrhole_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IDBUS_ADDRHOLE_ADDR_SPEC; +impl crate::RegisterSpec for IDBUS_ADDRHOLE_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`idbus_addrhole_addr::R`](R) reader structure"] +impl crate::Readable for IDBUS_ADDRHOLE_ADDR_SPEC {} +#[doc = "`reset()` method sets IDBUS_ADDRHOLE_ADDR to value 0"] +impl crate::Resettable for IDBUS_ADDRHOLE_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/idbus_addrhole_info.rs b/esp32p4/src/lp_sys/idbus_addrhole_info.rs new file mode 100644 index 0000000000..3fe4b894c5 --- /dev/null +++ b/esp32p4/src/lp_sys/idbus_addrhole_info.rs @@ -0,0 +1,61 @@ +#[doc = "Register `IDBUS_ADDRHOLE_INFO` reader"] +pub type R = crate::R; +#[doc = "Field `IDBUS_ADDRHOLE_ID` reader - need_des"] +pub type IDBUS_ADDRHOLE_ID_R = crate::FieldReader; +#[doc = "Field `IDBUS_ADDRHOLE_WR` reader - need_des"] +pub type IDBUS_ADDRHOLE_WR_R = crate::BitReader; +#[doc = "Field `IDBUS_ADDRHOLE_SECURE` reader - need_des"] +pub type IDBUS_ADDRHOLE_SECURE_R = crate::BitReader; +impl R { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + pub fn idbus_addrhole_id(&self) -> IDBUS_ADDRHOLE_ID_R { + IDBUS_ADDRHOLE_ID_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + pub fn idbus_addrhole_wr(&self) -> IDBUS_ADDRHOLE_WR_R { + IDBUS_ADDRHOLE_WR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - need_des"] + #[inline(always)] + pub fn idbus_addrhole_secure(&self) -> IDBUS_ADDRHOLE_SECURE_R { + IDBUS_ADDRHOLE_SECURE_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IDBUS_ADDRHOLE_INFO") + .field( + "idbus_addrhole_id", + &format_args!("{}", self.idbus_addrhole_id().bits()), + ) + .field( + "idbus_addrhole_wr", + &format_args!("{}", self.idbus_addrhole_wr().bit()), + ) + .field( + "idbus_addrhole_secure", + &format_args!("{}", self.idbus_addrhole_secure().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idbus_addrhole_info::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IDBUS_ADDRHOLE_INFO_SPEC; +impl crate::RegisterSpec for IDBUS_ADDRHOLE_INFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`idbus_addrhole_info::R`](R) reader structure"] +impl crate::Readable for IDBUS_ADDRHOLE_INFO_SPEC {} +#[doc = "`reset()` method sets IDBUS_ADDRHOLE_INFO to value 0"] +impl crate::Resettable for IDBUS_ADDRHOLE_INFO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/int_clr.rs b/esp32p4/src/lp_sys/int_clr.rs new file mode 100644 index 0000000000..e86e3d9341 --- /dev/null +++ b/esp32p4/src/lp_sys/int_clr.rs @@ -0,0 +1,90 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ADDRHOLE_INT_CLR` writer - write 1 to clear lp addrhole int"] +pub type LP_ADDRHOLE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDBUS_ADDRHOLE_INT_CLR` writer - write 1 to clear idbus addrhole int"] +pub type IDBUS_ADDRHOLE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CORE_AHB_TIMEOUT_INT_CLR` writer - Write 1 to clear lp_core_ahb_timeout int"] +pub type LP_CORE_AHB_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CORE_IBUS_TIMEOUT_INT_CLR` writer - Write 1 to clear lp_core_ibus_timeout int"] +pub type LP_CORE_IBUS_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CORE_DBUS_TIMEOUT_INT_CLR` writer - Write 1 to clear lp_core_dbus_timeout int"] +pub type LP_CORE_DBUS_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_ULP_INT_CLR` writer - Write 1 to clear etm tasl ulp int"] +pub type ETM_TASK_ULP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLOW_CLK_TICK_INT_CLR` writer - Write 1 to clear slow_clk_tick int"] +pub type SLOW_CLK_TICK_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - write 1 to clear lp addrhole int"] + #[inline(always)] + #[must_use] + pub fn lp_addrhole_int_clr(&mut self) -> LP_ADDRHOLE_INT_CLR_W { + LP_ADDRHOLE_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - write 1 to clear idbus addrhole int"] + #[inline(always)] + #[must_use] + pub fn idbus_addrhole_int_clr(&mut self) -> IDBUS_ADDRHOLE_INT_CLR_W { + IDBUS_ADDRHOLE_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to clear lp_core_ahb_timeout int"] + #[inline(always)] + #[must_use] + pub fn lp_core_ahb_timeout_int_clr(&mut self) -> LP_CORE_AHB_TIMEOUT_INT_CLR_W { + LP_CORE_AHB_TIMEOUT_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to clear lp_core_ibus_timeout int"] + #[inline(always)] + #[must_use] + pub fn lp_core_ibus_timeout_int_clr(&mut self) -> LP_CORE_IBUS_TIMEOUT_INT_CLR_W { + LP_CORE_IBUS_TIMEOUT_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to clear lp_core_dbus_timeout int"] + #[inline(always)] + #[must_use] + pub fn lp_core_dbus_timeout_int_clr(&mut self) -> LP_CORE_DBUS_TIMEOUT_INT_CLR_W { + LP_CORE_DBUS_TIMEOUT_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to clear etm tasl ulp int"] + #[inline(always)] + #[must_use] + pub fn etm_task_ulp_int_clr(&mut self) -> ETM_TASK_ULP_INT_CLR_W { + ETM_TASK_ULP_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Write 1 to clear slow_clk_tick int"] + #[inline(always)] + #[must_use] + pub fn slow_clk_tick_int_clr(&mut self) -> SLOW_CLK_TICK_INT_CLR_W { + SLOW_CLK_TICK_INT_CLR_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/int_ena.rs b/esp32p4/src/lp_sys/int_ena.rs new file mode 100644 index 0000000000..fff0e69078 --- /dev/null +++ b/esp32p4/src/lp_sys/int_ena.rs @@ -0,0 +1,180 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ADDRHOLE_INT_ENA` reader - Write 1 to enable lp addrhole int"] +pub type LP_ADDRHOLE_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_ADDRHOLE_INT_ENA` writer - Write 1 to enable lp addrhole int"] +pub type LP_ADDRHOLE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDBUS_ADDRHOLE_INT_ENA` reader - Write 1 to enable idbus addrhole int"] +pub type IDBUS_ADDRHOLE_INT_ENA_R = crate::BitReader; +#[doc = "Field `IDBUS_ADDRHOLE_INT_ENA` writer - Write 1 to enable idbus addrhole int"] +pub type IDBUS_ADDRHOLE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CORE_AHB_TIMEOUT_INT_ENA` reader - Write 1 to enable lp_core_ahb_timeout int"] +pub type LP_CORE_AHB_TIMEOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_CORE_AHB_TIMEOUT_INT_ENA` writer - Write 1 to enable lp_core_ahb_timeout int"] +pub type LP_CORE_AHB_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CORE_IBUS_TIMEOUT_INT_ENA` reader - Write 1 to enable lp_core_ibus_timeout int"] +pub type LP_CORE_IBUS_TIMEOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_CORE_IBUS_TIMEOUT_INT_ENA` writer - Write 1 to enable lp_core_ibus_timeout int"] +pub type LP_CORE_IBUS_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CORE_DBUS_TIMEOUT_INT_ENA` reader - Write 1 to enable lp_core_dbus_timeout int"] +pub type LP_CORE_DBUS_TIMEOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_CORE_DBUS_TIMEOUT_INT_ENA` writer - Write 1 to enable lp_core_dbus_timeout int"] +pub type LP_CORE_DBUS_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_TASK_ULP_INT_ENA` reader - Write 1 to enable etm task ulp int"] +pub type ETM_TASK_ULP_INT_ENA_R = crate::BitReader; +#[doc = "Field `ETM_TASK_ULP_INT_ENA` writer - Write 1 to enable etm task ulp int"] +pub type ETM_TASK_ULP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLOW_CLK_TICK_INT_ENA` reader - Write 1 to enable slow_clk_tick int"] +pub type SLOW_CLK_TICK_INT_ENA_R = crate::BitReader; +#[doc = "Field `SLOW_CLK_TICK_INT_ENA` writer - Write 1 to enable slow_clk_tick int"] +pub type SLOW_CLK_TICK_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 to enable lp addrhole int"] + #[inline(always)] + pub fn lp_addrhole_int_ena(&self) -> LP_ADDRHOLE_INT_ENA_R { + LP_ADDRHOLE_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to enable idbus addrhole int"] + #[inline(always)] + pub fn idbus_addrhole_int_ena(&self) -> IDBUS_ADDRHOLE_INT_ENA_R { + IDBUS_ADDRHOLE_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 to enable lp_core_ahb_timeout int"] + #[inline(always)] + pub fn lp_core_ahb_timeout_int_ena(&self) -> LP_CORE_AHB_TIMEOUT_INT_ENA_R { + LP_CORE_AHB_TIMEOUT_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1 to enable lp_core_ibus_timeout int"] + #[inline(always)] + pub fn lp_core_ibus_timeout_int_ena(&self) -> LP_CORE_IBUS_TIMEOUT_INT_ENA_R { + LP_CORE_IBUS_TIMEOUT_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write 1 to enable lp_core_dbus_timeout int"] + #[inline(always)] + pub fn lp_core_dbus_timeout_int_ena(&self) -> LP_CORE_DBUS_TIMEOUT_INT_ENA_R { + LP_CORE_DBUS_TIMEOUT_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Write 1 to enable etm task ulp int"] + #[inline(always)] + pub fn etm_task_ulp_int_ena(&self) -> ETM_TASK_ULP_INT_ENA_R { + ETM_TASK_ULP_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Write 1 to enable slow_clk_tick int"] + #[inline(always)] + pub fn slow_clk_tick_int_ena(&self) -> SLOW_CLK_TICK_INT_ENA_R { + SLOW_CLK_TICK_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "lp_addrhole_int_ena", + &format_args!("{}", self.lp_addrhole_int_ena().bit()), + ) + .field( + "idbus_addrhole_int_ena", + &format_args!("{}", self.idbus_addrhole_int_ena().bit()), + ) + .field( + "lp_core_ahb_timeout_int_ena", + &format_args!("{}", self.lp_core_ahb_timeout_int_ena().bit()), + ) + .field( + "lp_core_ibus_timeout_int_ena", + &format_args!("{}", self.lp_core_ibus_timeout_int_ena().bit()), + ) + .field( + "lp_core_dbus_timeout_int_ena", + &format_args!("{}", self.lp_core_dbus_timeout_int_ena().bit()), + ) + .field( + "etm_task_ulp_int_ena", + &format_args!("{}", self.etm_task_ulp_int_ena().bit()), + ) + .field( + "slow_clk_tick_int_ena", + &format_args!("{}", self.slow_clk_tick_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to enable lp addrhole int"] + #[inline(always)] + #[must_use] + pub fn lp_addrhole_int_ena(&mut self) -> LP_ADDRHOLE_INT_ENA_W { + LP_ADDRHOLE_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to enable idbus addrhole int"] + #[inline(always)] + #[must_use] + pub fn idbus_addrhole_int_ena(&mut self) -> IDBUS_ADDRHOLE_INT_ENA_W { + IDBUS_ADDRHOLE_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to enable lp_core_ahb_timeout int"] + #[inline(always)] + #[must_use] + pub fn lp_core_ahb_timeout_int_ena(&mut self) -> LP_CORE_AHB_TIMEOUT_INT_ENA_W { + LP_CORE_AHB_TIMEOUT_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to enable lp_core_ibus_timeout int"] + #[inline(always)] + #[must_use] + pub fn lp_core_ibus_timeout_int_ena(&mut self) -> LP_CORE_IBUS_TIMEOUT_INT_ENA_W { + LP_CORE_IBUS_TIMEOUT_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 to enable lp_core_dbus_timeout int"] + #[inline(always)] + #[must_use] + pub fn lp_core_dbus_timeout_int_ena(&mut self) -> LP_CORE_DBUS_TIMEOUT_INT_ENA_W { + LP_CORE_DBUS_TIMEOUT_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - Write 1 to enable etm task ulp int"] + #[inline(always)] + #[must_use] + pub fn etm_task_ulp_int_ena(&mut self) -> ETM_TASK_ULP_INT_ENA_W { + ETM_TASK_ULP_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - Write 1 to enable slow_clk_tick int"] + #[inline(always)] + #[must_use] + pub fn slow_clk_tick_int_ena(&mut self) -> SLOW_CLK_TICK_INT_ENA_W { + SLOW_CLK_TICK_INT_ENA_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/int_raw.rs b/esp32p4/src/lp_sys/int_raw.rs new file mode 100644 index 0000000000..9d29af221f --- /dev/null +++ b/esp32p4/src/lp_sys/int_raw.rs @@ -0,0 +1,105 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `LP_ADDRHOLE_INT_RAW` reader - the raw interrupt status of lp addrhole(for lp peri and lp ram tee apm, and lp matrix default slave)"] +pub type LP_ADDRHOLE_INT_RAW_R = crate::BitReader; +#[doc = "Field `IDBUS_ADDRHOLE_INT_RAW` reader - the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus)"] +pub type IDBUS_ADDRHOLE_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_CORE_AHB_TIMEOUT_INT_RAW` reader - the raw interrupt status of lp core ahb bus timeout"] +pub type LP_CORE_AHB_TIMEOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_CORE_IBUS_TIMEOUT_INT_RAW` reader - the raw interrupt status of lp core ibus timeout"] +pub type LP_CORE_IBUS_TIMEOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_CORE_DBUS_TIMEOUT_INT_RAW` reader - the raw interrupt status of lp core dbus timeout"] +pub type LP_CORE_DBUS_TIMEOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `ETM_TASK_ULP_INT_RAW` reader - the raw interrupt status of etm task ulp"] +pub type ETM_TASK_ULP_INT_RAW_R = crate::BitReader; +#[doc = "Field `SLOW_CLK_TICK_INT_RAW` reader - the raw interrupt status of slow_clk_tick"] +pub type SLOW_CLK_TICK_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - the raw interrupt status of lp addrhole(for lp peri and lp ram tee apm, and lp matrix default slave)"] + #[inline(always)] + pub fn lp_addrhole_int_raw(&self) -> LP_ADDRHOLE_INT_RAW_R { + LP_ADDRHOLE_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus)"] + #[inline(always)] + pub fn idbus_addrhole_int_raw(&self) -> IDBUS_ADDRHOLE_INT_RAW_R { + IDBUS_ADDRHOLE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - the raw interrupt status of lp core ahb bus timeout"] + #[inline(always)] + pub fn lp_core_ahb_timeout_int_raw(&self) -> LP_CORE_AHB_TIMEOUT_INT_RAW_R { + LP_CORE_AHB_TIMEOUT_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - the raw interrupt status of lp core ibus timeout"] + #[inline(always)] + pub fn lp_core_ibus_timeout_int_raw(&self) -> LP_CORE_IBUS_TIMEOUT_INT_RAW_R { + LP_CORE_IBUS_TIMEOUT_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the raw interrupt status of lp core dbus timeout"] + #[inline(always)] + pub fn lp_core_dbus_timeout_int_raw(&self) -> LP_CORE_DBUS_TIMEOUT_INT_RAW_R { + LP_CORE_DBUS_TIMEOUT_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - the raw interrupt status of etm task ulp"] + #[inline(always)] + pub fn etm_task_ulp_int_raw(&self) -> ETM_TASK_ULP_INT_RAW_R { + ETM_TASK_ULP_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - the raw interrupt status of slow_clk_tick"] + #[inline(always)] + pub fn slow_clk_tick_int_raw(&self) -> SLOW_CLK_TICK_INT_RAW_R { + SLOW_CLK_TICK_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "lp_addrhole_int_raw", + &format_args!("{}", self.lp_addrhole_int_raw().bit()), + ) + .field( + "idbus_addrhole_int_raw", + &format_args!("{}", self.idbus_addrhole_int_raw().bit()), + ) + .field( + "lp_core_ahb_timeout_int_raw", + &format_args!("{}", self.lp_core_ahb_timeout_int_raw().bit()), + ) + .field( + "lp_core_ibus_timeout_int_raw", + &format_args!("{}", self.lp_core_ibus_timeout_int_raw().bit()), + ) + .field( + "lp_core_dbus_timeout_int_raw", + &format_args!("{}", self.lp_core_dbus_timeout_int_raw().bit()), + ) + .field( + "etm_task_ulp_int_raw", + &format_args!("{}", self.etm_task_ulp_int_raw().bit()), + ) + .field( + "slow_clk_tick_int_raw", + &format_args!("{}", self.slow_clk_tick_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "raw interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/int_st.rs b/esp32p4/src/lp_sys/int_st.rs new file mode 100644 index 0000000000..1d363e62d3 --- /dev/null +++ b/esp32p4/src/lp_sys/int_st.rs @@ -0,0 +1,105 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `LP_ADDRHOLE_INT_ST` reader - the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp matrix default slave)"] +pub type LP_ADDRHOLE_INT_ST_R = crate::BitReader; +#[doc = "Field `IDBUS_ADDRHOLE_INT_ST` reader - the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus)"] +pub type IDBUS_ADDRHOLE_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_CORE_AHB_TIMEOUT_INT_ST` reader - the masked interrupt status of lp core ahb bus timeout"] +pub type LP_CORE_AHB_TIMEOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_CORE_IBUS_TIMEOUT_INT_ST` reader - the masked interrupt status of lp core ibus timeout"] +pub type LP_CORE_IBUS_TIMEOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_CORE_DBUS_TIMEOUT_INT_ST` reader - the masked interrupt status of lp core dbus timeout"] +pub type LP_CORE_DBUS_TIMEOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `ETM_TASK_ULP_INT_ST` reader - the masked interrupt status of etm task ulp"] +pub type ETM_TASK_ULP_INT_ST_R = crate::BitReader; +#[doc = "Field `SLOW_CLK_TICK_INT_ST` reader - the masked interrupt status of slow_clk_tick"] +pub type SLOW_CLK_TICK_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp matrix default slave)"] + #[inline(always)] + pub fn lp_addrhole_int_st(&self) -> LP_ADDRHOLE_INT_ST_R { + LP_ADDRHOLE_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus)"] + #[inline(always)] + pub fn idbus_addrhole_int_st(&self) -> IDBUS_ADDRHOLE_INT_ST_R { + IDBUS_ADDRHOLE_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - the masked interrupt status of lp core ahb bus timeout"] + #[inline(always)] + pub fn lp_core_ahb_timeout_int_st(&self) -> LP_CORE_AHB_TIMEOUT_INT_ST_R { + LP_CORE_AHB_TIMEOUT_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - the masked interrupt status of lp core ibus timeout"] + #[inline(always)] + pub fn lp_core_ibus_timeout_int_st(&self) -> LP_CORE_IBUS_TIMEOUT_INT_ST_R { + LP_CORE_IBUS_TIMEOUT_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the masked interrupt status of lp core dbus timeout"] + #[inline(always)] + pub fn lp_core_dbus_timeout_int_st(&self) -> LP_CORE_DBUS_TIMEOUT_INT_ST_R { + LP_CORE_DBUS_TIMEOUT_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - the masked interrupt status of etm task ulp"] + #[inline(always)] + pub fn etm_task_ulp_int_st(&self) -> ETM_TASK_ULP_INT_ST_R { + ETM_TASK_ULP_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - the masked interrupt status of slow_clk_tick"] + #[inline(always)] + pub fn slow_clk_tick_int_st(&self) -> SLOW_CLK_TICK_INT_ST_R { + SLOW_CLK_TICK_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "lp_addrhole_int_st", + &format_args!("{}", self.lp_addrhole_int_st().bit()), + ) + .field( + "idbus_addrhole_int_st", + &format_args!("{}", self.idbus_addrhole_int_st().bit()), + ) + .field( + "lp_core_ahb_timeout_int_st", + &format_args!("{}", self.lp_core_ahb_timeout_int_st().bit()), + ) + .field( + "lp_core_ibus_timeout_int_st", + &format_args!("{}", self.lp_core_ibus_timeout_int_st().bit()), + ) + .field( + "lp_core_dbus_timeout_int_st", + &format_args!("{}", self.lp_core_dbus_timeout_int_st().bit()), + ) + .field( + "etm_task_ulp_int_st", + &format_args!("{}", self.etm_task_ulp_int_st().bit()), + ) + .field( + "slow_clk_tick_int_st", + &format_args!("{}", self.slow_clk_tick_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_addrhole_addr.rs b/esp32p4/src/lp_sys/lp_addrhole_addr.rs new file mode 100644 index 0000000000..15235ffce8 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_addrhole_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `LP_ADDRHOLE_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `LP_ADDRHOLE_ADDR` reader - need_des"] +pub type LP_ADDRHOLE_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_addrhole_addr(&self) -> LP_ADDRHOLE_ADDR_R { + LP_ADDRHOLE_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ADDRHOLE_ADDR") + .field( + "lp_addrhole_addr", + &format_args!("{}", self.lp_addrhole_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_addrhole_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ADDRHOLE_ADDR_SPEC; +impl crate::RegisterSpec for LP_ADDRHOLE_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_addrhole_addr::R`](R) reader structure"] +impl crate::Readable for LP_ADDRHOLE_ADDR_SPEC {} +#[doc = "`reset()` method sets LP_ADDRHOLE_ADDR to value 0"] +impl crate::Resettable for LP_ADDRHOLE_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_addrhole_info.rs b/esp32p4/src/lp_sys/lp_addrhole_info.rs new file mode 100644 index 0000000000..121176aea6 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_addrhole_info.rs @@ -0,0 +1,61 @@ +#[doc = "Register `LP_ADDRHOLE_INFO` reader"] +pub type R = crate::R; +#[doc = "Field `LP_ADDRHOLE_ID` reader - master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma."] +pub type LP_ADDRHOLE_ID_R = crate::FieldReader; +#[doc = "Field `LP_ADDRHOLE_WR` reader - 1:write trans, 0: read trans."] +pub type LP_ADDRHOLE_WR_R = crate::BitReader; +#[doc = "Field `LP_ADDRHOLE_SECURE` reader - 1: illegal address access, 0: access without permission"] +pub type LP_ADDRHOLE_SECURE_R = crate::BitReader; +impl R { + #[doc = "Bits 0:4 - master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma."] + #[inline(always)] + pub fn lp_addrhole_id(&self) -> LP_ADDRHOLE_ID_R { + LP_ADDRHOLE_ID_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - 1:write trans, 0: read trans."] + #[inline(always)] + pub fn lp_addrhole_wr(&self) -> LP_ADDRHOLE_WR_R { + LP_ADDRHOLE_WR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1: illegal address access, 0: access without permission"] + #[inline(always)] + pub fn lp_addrhole_secure(&self) -> LP_ADDRHOLE_SECURE_R { + LP_ADDRHOLE_SECURE_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ADDRHOLE_INFO") + .field( + "lp_addrhole_id", + &format_args!("{}", self.lp_addrhole_id().bits()), + ) + .field( + "lp_addrhole_wr", + &format_args!("{}", self.lp_addrhole_wr().bit()), + ) + .field( + "lp_addrhole_secure", + &format_args!("{}", self.lp_addrhole_secure().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_addrhole_info::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ADDRHOLE_INFO_SPEC; +impl crate::RegisterSpec for LP_ADDRHOLE_INFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_addrhole_info::R`](R) reader structure"] +impl crate::Readable for LP_ADDRHOLE_INFO_SPEC {} +#[doc = "`reset()` method sets LP_ADDRHOLE_INFO to value 0"] +impl crate::Resettable for LP_ADDRHOLE_INFO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_clk_ctrl.rs b/esp32p4/src/lp_sys/lp_clk_ctrl.rs new file mode 100644 index 0000000000..f42fd0020c --- /dev/null +++ b/esp32p4/src/lp_sys/lp_clk_ctrl.rs @@ -0,0 +1,82 @@ +#[doc = "Register `LP_CLK_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_CLK_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - need_des"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - need_des"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_FOSC_HP_CKEN` reader - reserved"] +pub type LP_FOSC_HP_CKEN_R = crate::BitReader; +#[doc = "Field `LP_FOSC_HP_CKEN` writer - reserved"] +pub type LP_FOSC_HP_CKEN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 14 - reserved"] + #[inline(always)] + pub fn lp_fosc_hp_cken(&self) -> LP_FOSC_HP_CKEN_R { + LP_FOSC_HP_CKEN_R::new(((self.bits >> 14) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CLK_CTRL") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field( + "lp_fosc_hp_cken", + &format_args!("{}", self.lp_fosc_hp_cken().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = "Bit 14 - reserved"] + #[inline(always)] + #[must_use] + pub fn lp_fosc_hp_cken(&mut self) -> LP_FOSC_HP_CKEN_W { + LP_FOSC_HP_CKEN_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_clk_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_clk_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CLK_CTRL_SPEC; +impl crate::RegisterSpec for LP_CLK_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_clk_ctrl::R`](R) reader structure"] +impl crate::Readable for LP_CLK_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_clk_ctrl::W`](W) writer structure"] +impl crate::Writable for LP_CLK_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_CLK_CTRL to value 0x4001"] +impl crate::Resettable for LP_CLK_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x4001; +} diff --git a/esp32p4/src/lp_sys/lp_core_ahb_timeout.rs b/esp32p4/src/lp_sys/lp_core_ahb_timeout.rs new file mode 100644 index 0000000000..363e79eb91 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_core_ahb_timeout.rs @@ -0,0 +1,119 @@ +#[doc = "Register `LP_CORE_AHB_TIMEOUT` reader"] +pub type R = crate::R; +#[doc = "Register `LP_CORE_AHB_TIMEOUT` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - set this field to 1 to enable lp core ahb timeout handle"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - set this field to 1 to enable lp core ahb timeout handle"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES` reader - This field used to set lp core ahb bus timeout threshold"] +pub type THRES_R = crate::FieldReader; +#[doc = "Field `THRES` writer - This field used to set lp core ahb bus timeout threshold"] +pub type THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `LP2HP_AHB_TIMEOUT_EN` reader - set this field to 1 to enable lp2hp ahb timeout handle"] +pub type LP2HP_AHB_TIMEOUT_EN_R = crate::BitReader; +#[doc = "Field `LP2HP_AHB_TIMEOUT_EN` writer - set this field to 1 to enable lp2hp ahb timeout handle"] +pub type LP2HP_AHB_TIMEOUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP2HP_AHB_TIMEOUT_THRES` reader - This field used to set lp2hp ahb bus timeout threshold"] +pub type LP2HP_AHB_TIMEOUT_THRES_R = crate::FieldReader; +#[doc = "Field `LP2HP_AHB_TIMEOUT_THRES` writer - This field used to set lp2hp ahb bus timeout threshold"] +pub type LP2HP_AHB_TIMEOUT_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bit 0 - set this field to 1 to enable lp core ahb timeout handle"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - This field used to set lp core ahb bus timeout threshold"] + #[inline(always)] + pub fn thres(&self) -> THRES_R { + THRES_R::new(((self.bits >> 1) & 0xffff) as u16) + } + #[doc = "Bit 17 - set this field to 1 to enable lp2hp ahb timeout handle"] + #[inline(always)] + pub fn lp2hp_ahb_timeout_en(&self) -> LP2HP_AHB_TIMEOUT_EN_R { + LP2HP_AHB_TIMEOUT_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:22 - This field used to set lp2hp ahb bus timeout threshold"] + #[inline(always)] + pub fn lp2hp_ahb_timeout_thres(&self) -> LP2HP_AHB_TIMEOUT_THRES_R { + LP2HP_AHB_TIMEOUT_THRES_R::new(((self.bits >> 18) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CORE_AHB_TIMEOUT") + .field("en", &format_args!("{}", self.en().bit())) + .field("thres", &format_args!("{}", self.thres().bits())) + .field( + "lp2hp_ahb_timeout_en", + &format_args!("{}", self.lp2hp_ahb_timeout_en().bit()), + ) + .field( + "lp2hp_ahb_timeout_thres", + &format_args!("{}", self.lp2hp_ahb_timeout_thres().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this field to 1 to enable lp core ahb timeout handle"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 1:16 - This field used to set lp core ahb bus timeout threshold"] + #[inline(always)] + #[must_use] + pub fn thres(&mut self) -> THRES_W { + THRES_W::new(self, 1) + } + #[doc = "Bit 17 - set this field to 1 to enable lp2hp ahb timeout handle"] + #[inline(always)] + #[must_use] + pub fn lp2hp_ahb_timeout_en(&mut self) -> LP2HP_AHB_TIMEOUT_EN_W { + LP2HP_AHB_TIMEOUT_EN_W::new(self, 17) + } + #[doc = "Bits 18:22 - This field used to set lp2hp ahb bus timeout threshold"] + #[inline(always)] + #[must_use] + pub fn lp2hp_ahb_timeout_thres( + &mut self, + ) -> LP2HP_AHB_TIMEOUT_THRES_W { + LP2HP_AHB_TIMEOUT_THRES_W::new(self, 18) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_core_ahb_timeout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_core_ahb_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CORE_AHB_TIMEOUT_SPEC; +impl crate::RegisterSpec for LP_CORE_AHB_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_core_ahb_timeout::R`](R) reader structure"] +impl crate::Readable for LP_CORE_AHB_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_core_ahb_timeout::W`](W) writer structure"] +impl crate::Writable for LP_CORE_AHB_TIMEOUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_CORE_AHB_TIMEOUT to value 0x007f_ffff"] +impl crate::Resettable for LP_CORE_AHB_TIMEOUT_SPEC { + const RESET_VALUE: Self::Ux = 0x007f_ffff; +} diff --git a/esp32p4/src/lp_sys/lp_core_boot_addr.rs b/esp32p4/src/lp_sys/lp_core_boot_addr.rs new file mode 100644 index 0000000000..01b46c4ac6 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_core_boot_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_CORE_BOOT_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `LP_CORE_BOOT_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `LP_CPU_BOOT_ADDR` reader - need_des"] +pub type LP_CPU_BOOT_ADDR_R = crate::FieldReader; +#[doc = "Field `LP_CPU_BOOT_ADDR` writer - need_des"] +pub type LP_CPU_BOOT_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_cpu_boot_addr(&self) -> LP_CPU_BOOT_ADDR_R { + LP_CPU_BOOT_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CORE_BOOT_ADDR") + .field( + "lp_cpu_boot_addr", + &format_args!("{}", self.lp_cpu_boot_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_boot_addr(&mut self) -> LP_CPU_BOOT_ADDR_W { + LP_CPU_BOOT_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_core_boot_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_core_boot_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CORE_BOOT_ADDR_SPEC; +impl crate::RegisterSpec for LP_CORE_BOOT_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_core_boot_addr::R`](R) reader structure"] +impl crate::Readable for LP_CORE_BOOT_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_core_boot_addr::W`](W) writer structure"] +impl crate::Writable for LP_CORE_BOOT_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_CORE_BOOT_ADDR to value 0x5010_0000"] +impl crate::Resettable for LP_CORE_BOOT_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0x5010_0000; +} diff --git a/esp32p4/src/lp_sys/lp_core_dbus_timeout.rs b/esp32p4/src/lp_sys/lp_core_dbus_timeout.rs new file mode 100644 index 0000000000..b50ab007bd --- /dev/null +++ b/esp32p4/src/lp_sys/lp_core_dbus_timeout.rs @@ -0,0 +1,79 @@ +#[doc = "Register `LP_CORE_DBUS_TIMEOUT` reader"] +pub type R = crate::R; +#[doc = "Register `LP_CORE_DBUS_TIMEOUT` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - set this field to 1 to enable lp core dbus timeout handle"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - set this field to 1 to enable lp core dbus timeout handle"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES` reader - This field used to set lp core dbus timeout threshold"] +pub type THRES_R = crate::FieldReader; +#[doc = "Field `THRES` writer - This field used to set lp core dbus timeout threshold"] +pub type THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - set this field to 1 to enable lp core dbus timeout handle"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - This field used to set lp core dbus timeout threshold"] + #[inline(always)] + pub fn thres(&self) -> THRES_R { + THRES_R::new(((self.bits >> 1) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CORE_DBUS_TIMEOUT") + .field("en", &format_args!("{}", self.en().bit())) + .field("thres", &format_args!("{}", self.thres().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this field to 1 to enable lp core dbus timeout handle"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 1:16 - This field used to set lp core dbus timeout threshold"] + #[inline(always)] + #[must_use] + pub fn thres(&mut self) -> THRES_W { + THRES_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_core_dbus_timeout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_core_dbus_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CORE_DBUS_TIMEOUT_SPEC; +impl crate::RegisterSpec for LP_CORE_DBUS_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_core_dbus_timeout::R`](R) reader structure"] +impl crate::Readable for LP_CORE_DBUS_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_core_dbus_timeout::W`](W) writer structure"] +impl crate::Writable for LP_CORE_DBUS_TIMEOUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_CORE_DBUS_TIMEOUT to value 0x0001_ffff"] +impl crate::Resettable for LP_CORE_DBUS_TIMEOUT_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_ffff; +} diff --git a/esp32p4/src/lp_sys/lp_core_err_resp_dis.rs b/esp32p4/src/lp_sys/lp_core_err_resp_dis.rs new file mode 100644 index 0000000000..db020aee3a --- /dev/null +++ b/esp32p4/src/lp_sys/lp_core_err_resp_dis.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_CORE_ERR_RESP_DIS` reader"] +pub type R = crate::R; +#[doc = "Register `LP_CORE_ERR_RESP_DIS` writer"] +pub type W = crate::W; +#[doc = "Field `LP_CORE_ERR_RESP_DIS` reader - Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to disable ahb err resp."] +pub type LP_CORE_ERR_RESP_DIS_R = crate::FieldReader; +#[doc = "Field `LP_CORE_ERR_RESP_DIS` writer - Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to disable ahb err resp."] +pub type LP_CORE_ERR_RESP_DIS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to disable ahb err resp."] + #[inline(always)] + pub fn lp_core_err_resp_dis(&self) -> LP_CORE_ERR_RESP_DIS_R { + LP_CORE_ERR_RESP_DIS_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CORE_ERR_RESP_DIS") + .field( + "lp_core_err_resp_dis", + &format_args!("{}", self.lp_core_err_resp_dis().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to disable ahb err resp."] + #[inline(always)] + #[must_use] + pub fn lp_core_err_resp_dis(&mut self) -> LP_CORE_ERR_RESP_DIS_W { + LP_CORE_ERR_RESP_DIS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_core_err_resp_dis::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_core_err_resp_dis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CORE_ERR_RESP_DIS_SPEC; +impl crate::RegisterSpec for LP_CORE_ERR_RESP_DIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_core_err_resp_dis::R`](R) reader structure"] +impl crate::Readable for LP_CORE_ERR_RESP_DIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_core_err_resp_dis::W`](W) writer structure"] +impl crate::Writable for LP_CORE_ERR_RESP_DIS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_CORE_ERR_RESP_DIS to value 0"] +impl crate::Resettable for LP_CORE_ERR_RESP_DIS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_core_ibus_timeout.rs b/esp32p4/src/lp_sys/lp_core_ibus_timeout.rs new file mode 100644 index 0000000000..e2eda90399 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_core_ibus_timeout.rs @@ -0,0 +1,79 @@ +#[doc = "Register `LP_CORE_IBUS_TIMEOUT` reader"] +pub type R = crate::R; +#[doc = "Register `LP_CORE_IBUS_TIMEOUT` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - set this field to 1 to enable lp core ibus timeout handle"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - set this field to 1 to enable lp core ibus timeout handle"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THRES` reader - This field used to set lp core ibus timeout threshold"] +pub type THRES_R = crate::FieldReader; +#[doc = "Field `THRES` writer - This field used to set lp core ibus timeout threshold"] +pub type THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - set this field to 1 to enable lp core ibus timeout handle"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:16 - This field used to set lp core ibus timeout threshold"] + #[inline(always)] + pub fn thres(&self) -> THRES_R { + THRES_R::new(((self.bits >> 1) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CORE_IBUS_TIMEOUT") + .field("en", &format_args!("{}", self.en().bit())) + .field("thres", &format_args!("{}", self.thres().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - set this field to 1 to enable lp core ibus timeout handle"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 1:16 - This field used to set lp core ibus timeout threshold"] + #[inline(always)] + #[must_use] + pub fn thres(&mut self) -> THRES_W { + THRES_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_core_ibus_timeout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_core_ibus_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CORE_IBUS_TIMEOUT_SPEC; +impl crate::RegisterSpec for LP_CORE_IBUS_TIMEOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_core_ibus_timeout::R`](R) reader structure"] +impl crate::Readable for LP_CORE_IBUS_TIMEOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_core_ibus_timeout::W`](W) writer structure"] +impl crate::Writable for LP_CORE_IBUS_TIMEOUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_CORE_IBUS_TIMEOUT to value 0x0001_ffff"] +impl crate::Resettable for LP_CORE_IBUS_TIMEOUT_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_ffff; +} diff --git a/esp32p4/src/lp_sys/lp_cpu_dbg_pc.rs b/esp32p4/src/lp_sys/lp_cpu_dbg_pc.rs new file mode 100644 index 0000000000..f1b20b308d --- /dev/null +++ b/esp32p4/src/lp_sys/lp_cpu_dbg_pc.rs @@ -0,0 +1,39 @@ +#[doc = "Register `LP_CPU_DBG_PC` reader"] +pub type R = crate::R; +#[doc = "Field `LP_CPU_DBG_PC` reader - need_des"] +pub type LP_CPU_DBG_PC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_cpu_dbg_pc(&self) -> LP_CPU_DBG_PC_R { + LP_CPU_DBG_PC_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CPU_DBG_PC") + .field( + "lp_cpu_dbg_pc", + &format_args!("{}", self.lp_cpu_dbg_pc().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_dbg_pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CPU_DBG_PC_SPEC; +impl crate::RegisterSpec for LP_CPU_DBG_PC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_cpu_dbg_pc::R`](R) reader structure"] +impl crate::Readable for LP_CPU_DBG_PC_SPEC {} +#[doc = "`reset()` method sets LP_CPU_DBG_PC to value 0"] +impl crate::Resettable for LP_CPU_DBG_PC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_cpu_exc_pc.rs b/esp32p4/src/lp_sys/lp_cpu_exc_pc.rs new file mode 100644 index 0000000000..a8776d0236 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_cpu_exc_pc.rs @@ -0,0 +1,39 @@ +#[doc = "Register `LP_CPU_EXC_PC` reader"] +pub type R = crate::R; +#[doc = "Field `LP_CPU_EXC_PC` reader - need_des"] +pub type LP_CPU_EXC_PC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_cpu_exc_pc(&self) -> LP_CPU_EXC_PC_R { + LP_CPU_EXC_PC_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CPU_EXC_PC") + .field( + "lp_cpu_exc_pc", + &format_args!("{}", self.lp_cpu_exc_pc().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_exc_pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CPU_EXC_PC_SPEC; +impl crate::RegisterSpec for LP_CPU_EXC_PC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_cpu_exc_pc::R`](R) reader structure"] +impl crate::Readable for LP_CPU_EXC_PC_SPEC {} +#[doc = "`reset()` method sets LP_CPU_EXC_PC to value 0"] +impl crate::Resettable for LP_CPU_EXC_PC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_mem_aux_ctrl.rs b/esp32p4/src/lp_sys/lp_mem_aux_ctrl.rs new file mode 100644 index 0000000000..27cef339b3 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_mem_aux_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_MEM_AUX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_MEM_AUX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_MEM_AUX_CTRL` reader - need_des"] +pub type LP_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `LP_MEM_AUX_CTRL` writer - need_des"] +pub type LP_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_mem_aux_ctrl(&self) -> LP_MEM_AUX_CTRL_R { + LP_MEM_AUX_CTRL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_MEM_AUX_CTRL") + .field( + "lp_mem_aux_ctrl", + &format_args!("{}", self.lp_mem_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_mem_aux_ctrl(&mut self) -> LP_MEM_AUX_CTRL_W { + LP_MEM_AUX_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_mem_aux_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_mem_aux_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_MEM_AUX_CTRL_SPEC; +impl crate::RegisterSpec for LP_MEM_AUX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_mem_aux_ctrl::R`](R) reader structure"] +impl crate::Readable for LP_MEM_AUX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_mem_aux_ctrl::W`](W) writer structure"] +impl crate::Writable for LP_MEM_AUX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_MEM_AUX_CTRL to value 0x2070"] +impl crate::Resettable for LP_MEM_AUX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x2070; +} diff --git a/esp32p4/src/lp_sys/lp_pmu_rdn_eco_high.rs b/esp32p4/src/lp_sys/lp_pmu_rdn_eco_high.rs new file mode 100644 index 0000000000..374e155a78 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_pmu_rdn_eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_PMU_RDN_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `LP_PMU_RDN_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `PMU_RDN_ECO_HIGH` reader - need_des"] +pub type PMU_RDN_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `PMU_RDN_ECO_HIGH` writer - need_des"] +pub type PMU_RDN_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn pmu_rdn_eco_high(&self) -> PMU_RDN_ECO_HIGH_R { + PMU_RDN_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_PMU_RDN_ECO_HIGH") + .field( + "pmu_rdn_eco_high", + &format_args!("{}", self.pmu_rdn_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn pmu_rdn_eco_high(&mut self) -> PMU_RDN_ECO_HIGH_W { + PMU_RDN_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_pmu_rdn_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_pmu_rdn_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_PMU_RDN_ECO_HIGH_SPEC; +impl crate::RegisterSpec for LP_PMU_RDN_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_pmu_rdn_eco_high::R`](R) reader structure"] +impl crate::Readable for LP_PMU_RDN_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_pmu_rdn_eco_high::W`](W) writer structure"] +impl crate::Writable for LP_PMU_RDN_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_PMU_RDN_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for LP_PMU_RDN_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_sys/lp_pmu_rdn_eco_low.rs b/esp32p4/src/lp_sys/lp_pmu_rdn_eco_low.rs new file mode 100644 index 0000000000..194b8c6dd9 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_pmu_rdn_eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_PMU_RDN_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `LP_PMU_RDN_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `PMU_RDN_ECO_LOW` reader - need_des"] +pub type PMU_RDN_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `PMU_RDN_ECO_LOW` writer - need_des"] +pub type PMU_RDN_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn pmu_rdn_eco_low(&self) -> PMU_RDN_ECO_LOW_R { + PMU_RDN_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_PMU_RDN_ECO_LOW") + .field( + "pmu_rdn_eco_low", + &format_args!("{}", self.pmu_rdn_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn pmu_rdn_eco_low(&mut self) -> PMU_RDN_ECO_LOW_W { + PMU_RDN_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_pmu_rdn_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_pmu_rdn_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_PMU_RDN_ECO_LOW_SPEC; +impl crate::RegisterSpec for LP_PMU_RDN_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_pmu_rdn_eco_low::R`](R) reader structure"] +impl crate::Readable for LP_PMU_RDN_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_pmu_rdn_eco_low::W`](W) writer structure"] +impl crate::Writable for LP_PMU_RDN_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_PMU_RDN_ECO_LOW to value 0"] +impl crate::Resettable for LP_PMU_RDN_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_probe_out.rs b/esp32p4/src/lp_sys/lp_probe_out.rs new file mode 100644 index 0000000000..e2e7e37225 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_probe_out.rs @@ -0,0 +1,39 @@ +#[doc = "Register `LP_PROBE_OUT` reader"] +pub type R = crate::R; +#[doc = "Field `PROBE_TOP_OUT` reader - need_des"] +pub type PROBE_TOP_OUT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn probe_top_out(&self) -> PROBE_TOP_OUT_R { + PROBE_TOP_OUT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_PROBE_OUT") + .field( + "probe_top_out", + &format_args!("{}", self.probe_top_out().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_probe_out::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_PROBE_OUT_SPEC; +impl crate::RegisterSpec for LP_PROBE_OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_probe_out::R`](R) reader structure"] +impl crate::Readable for LP_PROBE_OUT_SPEC {} +#[doc = "`reset()` method sets LP_PROBE_OUT to value 0"] +impl crate::Resettable for LP_PROBE_OUT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_probea_ctrl.rs b/esp32p4/src/lp_sys/lp_probea_ctrl.rs new file mode 100644 index 0000000000..7f2ec6306b --- /dev/null +++ b/esp32p4/src/lp_sys/lp_probea_ctrl.rs @@ -0,0 +1,142 @@ +#[doc = "Register `LP_PROBEA_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_PROBEA_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `PROBE_A_MOD_SEL` reader - need_des"] +pub type PROBE_A_MOD_SEL_R = crate::FieldReader; +#[doc = "Field `PROBE_A_MOD_SEL` writer - need_des"] +pub type PROBE_A_MOD_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `PROBE_A_TOP_SEL` reader - need_des"] +pub type PROBE_A_TOP_SEL_R = crate::FieldReader; +#[doc = "Field `PROBE_A_TOP_SEL` writer - need_des"] +pub type PROBE_A_TOP_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PROBE_L_SEL` reader - need_des"] +pub type PROBE_L_SEL_R = crate::FieldReader; +#[doc = "Field `PROBE_L_SEL` writer - need_des"] +pub type PROBE_L_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PROBE_H_SEL` reader - need_des"] +pub type PROBE_H_SEL_R = crate::FieldReader; +#[doc = "Field `PROBE_H_SEL` writer - need_des"] +pub type PROBE_H_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PROBE_GLOBAL_EN` reader - need_des"] +pub type PROBE_GLOBAL_EN_R = crate::BitReader; +#[doc = "Field `PROBE_GLOBAL_EN` writer - need_des"] +pub type PROBE_GLOBAL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn probe_a_mod_sel(&self) -> PROBE_A_MOD_SEL_R { + PROBE_A_MOD_SEL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + pub fn probe_a_top_sel(&self) -> PROBE_A_TOP_SEL_R { + PROBE_A_TOP_SEL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:25 - need_des"] + #[inline(always)] + pub fn probe_l_sel(&self) -> PROBE_L_SEL_R { + PROBE_L_SEL_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - need_des"] + #[inline(always)] + pub fn probe_h_sel(&self) -> PROBE_H_SEL_R { + PROBE_H_SEL_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn probe_global_en(&self) -> PROBE_GLOBAL_EN_R { + PROBE_GLOBAL_EN_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_PROBEA_CTRL") + .field( + "probe_a_mod_sel", + &format_args!("{}", self.probe_a_mod_sel().bits()), + ) + .field( + "probe_a_top_sel", + &format_args!("{}", self.probe_a_top_sel().bits()), + ) + .field( + "probe_l_sel", + &format_args!("{}", self.probe_l_sel().bits()), + ) + .field( + "probe_h_sel", + &format_args!("{}", self.probe_h_sel().bits()), + ) + .field( + "probe_global_en", + &format_args!("{}", self.probe_global_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn probe_a_mod_sel(&mut self) -> PROBE_A_MOD_SEL_W { + PROBE_A_MOD_SEL_W::new(self, 0) + } + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + #[must_use] + pub fn probe_a_top_sel(&mut self) -> PROBE_A_TOP_SEL_W { + PROBE_A_TOP_SEL_W::new(self, 16) + } + #[doc = "Bits 24:25 - need_des"] + #[inline(always)] + #[must_use] + pub fn probe_l_sel(&mut self) -> PROBE_L_SEL_W { + PROBE_L_SEL_W::new(self, 24) + } + #[doc = "Bits 26:27 - need_des"] + #[inline(always)] + #[must_use] + pub fn probe_h_sel(&mut self) -> PROBE_H_SEL_W { + PROBE_H_SEL_W::new(self, 26) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn probe_global_en(&mut self) -> PROBE_GLOBAL_EN_W { + PROBE_GLOBAL_EN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_probea_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_probea_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_PROBEA_CTRL_SPEC; +impl crate::RegisterSpec for LP_PROBEA_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_probea_ctrl::R`](R) reader structure"] +impl crate::Readable for LP_PROBEA_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_probea_ctrl::W`](W) writer structure"] +impl crate::Writable for LP_PROBEA_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_PROBEA_CTRL to value 0"] +impl crate::Resettable for LP_PROBEA_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_probeb_ctrl.rs b/esp32p4/src/lp_sys/lp_probeb_ctrl.rs new file mode 100644 index 0000000000..a211f56429 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_probeb_ctrl.rs @@ -0,0 +1,101 @@ +#[doc = "Register `LP_PROBEB_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_PROBEB_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `PROBE_B_MOD_SEL` reader - need_des"] +pub type PROBE_B_MOD_SEL_R = crate::FieldReader; +#[doc = "Field `PROBE_B_MOD_SEL` writer - need_des"] +pub type PROBE_B_MOD_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `PROBE_B_TOP_SEL` reader - need_des"] +pub type PROBE_B_TOP_SEL_R = crate::FieldReader; +#[doc = "Field `PROBE_B_TOP_SEL` writer - need_des"] +pub type PROBE_B_TOP_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PROBE_B_EN` reader - need_des"] +pub type PROBE_B_EN_R = crate::BitReader; +#[doc = "Field `PROBE_B_EN` writer - need_des"] +pub type PROBE_B_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn probe_b_mod_sel(&self) -> PROBE_B_MOD_SEL_R { + PROBE_B_MOD_SEL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + pub fn probe_b_top_sel(&self) -> PROBE_B_TOP_SEL_R { + PROBE_B_TOP_SEL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + pub fn probe_b_en(&self) -> PROBE_B_EN_R { + PROBE_B_EN_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_PROBEB_CTRL") + .field( + "probe_b_mod_sel", + &format_args!("{}", self.probe_b_mod_sel().bits()), + ) + .field( + "probe_b_top_sel", + &format_args!("{}", self.probe_b_top_sel().bits()), + ) + .field("probe_b_en", &format_args!("{}", self.probe_b_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn probe_b_mod_sel(&mut self) -> PROBE_B_MOD_SEL_W { + PROBE_B_MOD_SEL_W::new(self, 0) + } + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + #[must_use] + pub fn probe_b_top_sel(&mut self) -> PROBE_B_TOP_SEL_W { + PROBE_B_TOP_SEL_W::new(self, 16) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + #[must_use] + pub fn probe_b_en(&mut self) -> PROBE_B_EN_W { + PROBE_B_EN_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_probeb_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_probeb_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_PROBEB_CTRL_SPEC; +impl crate::RegisterSpec for LP_PROBEB_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_probeb_ctrl::R`](R) reader structure"] +impl crate::Readable for LP_PROBEB_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_probeb_ctrl::W`](W) writer structure"] +impl crate::Writable for LP_PROBEB_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_PROBEB_CTRL to value 0"] +impl crate::Resettable for LP_PROBEB_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_rom_aux_ctrl.rs b/esp32p4/src/lp_sys/lp_rom_aux_ctrl.rs new file mode 100644 index 0000000000..474257e037 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_rom_aux_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_ROM_AUX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_ROM_AUX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_ROM_AUX_CTRL` reader - need_des"] +pub type LP_ROM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `LP_ROM_AUX_CTRL` writer - need_des"] +pub type LP_ROM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_rom_aux_ctrl(&self) -> LP_ROM_AUX_CTRL_R { + LP_ROM_AUX_CTRL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_ROM_AUX_CTRL") + .field( + "lp_rom_aux_ctrl", + &format_args!("{}", self.lp_rom_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_rom_aux_ctrl(&mut self) -> LP_ROM_AUX_CTRL_W { + LP_ROM_AUX_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_rom_aux_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_rom_aux_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_ROM_AUX_CTRL_SPEC; +impl crate::RegisterSpec for LP_ROM_AUX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_rom_aux_ctrl::R`](R) reader structure"] +impl crate::Readable for LP_ROM_AUX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_rom_aux_ctrl::W`](W) writer structure"] +impl crate::Writable for LP_ROM_AUX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_ROM_AUX_CTRL to value 0x70"] +impl crate::Resettable for LP_ROM_AUX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x70; +} diff --git a/esp32p4/src/lp_sys/lp_rst_ctrl.rs b/esp32p4/src/lp_sys/lp_rst_ctrl.rs new file mode 100644 index 0000000000..9f8cfe5f74 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_rst_ctrl.rs @@ -0,0 +1,104 @@ +#[doc = "Register `LP_RST_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_RST_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_RST_BYPASS` reader - analog source reset bypass : wdt,brown out,super wdt,glitch"] +pub type ANA_RST_BYPASS_R = crate::BitReader; +#[doc = "Field `ANA_RST_BYPASS` writer - analog source reset bypass : wdt,brown out,super wdt,glitch"] +pub type ANA_RST_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYS_RST_BYPASS` reader - system source reset bypass : software reset,hp wdt,lp wdt,efuse"] +pub type SYS_RST_BYPASS_R = crate::BitReader; +#[doc = "Field `SYS_RST_BYPASS` writer - system source reset bypass : software reset,hp wdt,lp wdt,efuse"] +pub type SYS_RST_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EFUSE_FORCE_NORST` reader - efuse force no reset control"] +pub type EFUSE_FORCE_NORST_R = crate::BitReader; +#[doc = "Field `EFUSE_FORCE_NORST` writer - efuse force no reset control"] +pub type EFUSE_FORCE_NORST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - analog source reset bypass : wdt,brown out,super wdt,glitch"] + #[inline(always)] + pub fn ana_rst_bypass(&self) -> ANA_RST_BYPASS_R { + ANA_RST_BYPASS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - system source reset bypass : software reset,hp wdt,lp wdt,efuse"] + #[inline(always)] + pub fn sys_rst_bypass(&self) -> SYS_RST_BYPASS_R { + SYS_RST_BYPASS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - efuse force no reset control"] + #[inline(always)] + pub fn efuse_force_norst(&self) -> EFUSE_FORCE_NORST_R { + EFUSE_FORCE_NORST_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_RST_CTRL") + .field( + "ana_rst_bypass", + &format_args!("{}", self.ana_rst_bypass().bit()), + ) + .field( + "sys_rst_bypass", + &format_args!("{}", self.sys_rst_bypass().bit()), + ) + .field( + "efuse_force_norst", + &format_args!("{}", self.efuse_force_norst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - analog source reset bypass : wdt,brown out,super wdt,glitch"] + #[inline(always)] + #[must_use] + pub fn ana_rst_bypass(&mut self) -> ANA_RST_BYPASS_W { + ANA_RST_BYPASS_W::new(self, 0) + } + #[doc = "Bit 1 - system source reset bypass : software reset,hp wdt,lp wdt,efuse"] + #[inline(always)] + #[must_use] + pub fn sys_rst_bypass(&mut self) -> SYS_RST_BYPASS_W { + SYS_RST_BYPASS_W::new(self, 1) + } + #[doc = "Bit 2 - efuse force no reset control"] + #[inline(always)] + #[must_use] + pub fn efuse_force_norst(&mut self) -> EFUSE_FORCE_NORST_W { + EFUSE_FORCE_NORST_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_rst_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_rst_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_RST_CTRL_SPEC; +impl crate::RegisterSpec for LP_RST_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_rst_ctrl::R`](R) reader structure"] +impl crate::Readable for LP_RST_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_rst_ctrl::W`](W) writer structure"] +impl crate::Writable for LP_RST_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_RST_CTRL to value 0x03"] +impl crate::Resettable for LP_RST_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/lp_sys/lp_store0.rs b/esp32p4/src/lp_sys/lp_store0.rs new file mode 100644 index 0000000000..dbae9bc01c --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH0` reader - need_des"] +pub type LP_SCRATCH0_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH0` writer - need_des"] +pub type LP_SCRATCH0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch0(&self) -> LP_SCRATCH0_R { + LP_SCRATCH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE0") + .field( + "lp_scratch0", + &format_args!("{}", self.lp_scratch0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch0(&mut self) -> LP_SCRATCH0_W { + LP_SCRATCH0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE0_SPEC; +impl crate::RegisterSpec for LP_STORE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store0::R`](R) reader structure"] +impl crate::Readable for LP_STORE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store0::W`](W) writer structure"] +impl crate::Writable for LP_STORE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE0 to value 0"] +impl crate::Resettable for LP_STORE0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store1.rs b/esp32p4/src/lp_sys/lp_store1.rs new file mode 100644 index 0000000000..236f3dcf75 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH1` reader - need_des"] +pub type LP_SCRATCH1_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH1` writer - need_des"] +pub type LP_SCRATCH1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch1(&self) -> LP_SCRATCH1_R { + LP_SCRATCH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE1") + .field( + "lp_scratch1", + &format_args!("{}", self.lp_scratch1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch1(&mut self) -> LP_SCRATCH1_W { + LP_SCRATCH1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE1_SPEC; +impl crate::RegisterSpec for LP_STORE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store1::R`](R) reader structure"] +impl crate::Readable for LP_STORE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store1::W`](W) writer structure"] +impl crate::Writable for LP_STORE1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE1 to value 0"] +impl crate::Resettable for LP_STORE1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store10.rs b/esp32p4/src/lp_sys/lp_store10.rs new file mode 100644 index 0000000000..271b995241 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store10.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE10` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE10` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH10` reader - need_des"] +pub type LP_SCRATCH10_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH10` writer - need_des"] +pub type LP_SCRATCH10_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch10(&self) -> LP_SCRATCH10_R { + LP_SCRATCH10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE10") + .field( + "lp_scratch10", + &format_args!("{}", self.lp_scratch10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch10(&mut self) -> LP_SCRATCH10_W { + LP_SCRATCH10_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE10_SPEC; +impl crate::RegisterSpec for LP_STORE10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store10::R`](R) reader structure"] +impl crate::Readable for LP_STORE10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store10::W`](W) writer structure"] +impl crate::Writable for LP_STORE10_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE10 to value 0"] +impl crate::Resettable for LP_STORE10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store11.rs b/esp32p4/src/lp_sys/lp_store11.rs new file mode 100644 index 0000000000..267e8234d1 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store11.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE11` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE11` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH11` reader - need_des"] +pub type LP_SCRATCH11_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH11` writer - need_des"] +pub type LP_SCRATCH11_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch11(&self) -> LP_SCRATCH11_R { + LP_SCRATCH11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE11") + .field( + "lp_scratch11", + &format_args!("{}", self.lp_scratch11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch11(&mut self) -> LP_SCRATCH11_W { + LP_SCRATCH11_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE11_SPEC; +impl crate::RegisterSpec for LP_STORE11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store11::R`](R) reader structure"] +impl crate::Readable for LP_STORE11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store11::W`](W) writer structure"] +impl crate::Writable for LP_STORE11_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE11 to value 0"] +impl crate::Resettable for LP_STORE11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store12.rs b/esp32p4/src/lp_sys/lp_store12.rs new file mode 100644 index 0000000000..1714794c52 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store12.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE12` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE12` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH12` reader - need_des"] +pub type LP_SCRATCH12_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH12` writer - need_des"] +pub type LP_SCRATCH12_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch12(&self) -> LP_SCRATCH12_R { + LP_SCRATCH12_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE12") + .field( + "lp_scratch12", + &format_args!("{}", self.lp_scratch12().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch12(&mut self) -> LP_SCRATCH12_W { + LP_SCRATCH12_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE12_SPEC; +impl crate::RegisterSpec for LP_STORE12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store12::R`](R) reader structure"] +impl crate::Readable for LP_STORE12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store12::W`](W) writer structure"] +impl crate::Writable for LP_STORE12_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE12 to value 0"] +impl crate::Resettable for LP_STORE12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store13.rs b/esp32p4/src/lp_sys/lp_store13.rs new file mode 100644 index 0000000000..33a1246bb1 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store13.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE13` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE13` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH13` reader - need_des"] +pub type LP_SCRATCH13_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH13` writer - need_des"] +pub type LP_SCRATCH13_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch13(&self) -> LP_SCRATCH13_R { + LP_SCRATCH13_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE13") + .field( + "lp_scratch13", + &format_args!("{}", self.lp_scratch13().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch13(&mut self) -> LP_SCRATCH13_W { + LP_SCRATCH13_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE13_SPEC; +impl crate::RegisterSpec for LP_STORE13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store13::R`](R) reader structure"] +impl crate::Readable for LP_STORE13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store13::W`](W) writer structure"] +impl crate::Writable for LP_STORE13_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE13 to value 0"] +impl crate::Resettable for LP_STORE13_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store14.rs b/esp32p4/src/lp_sys/lp_store14.rs new file mode 100644 index 0000000000..6176203257 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store14.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE14` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE14` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH14` reader - need_des"] +pub type LP_SCRATCH14_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH14` writer - need_des"] +pub type LP_SCRATCH14_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch14(&self) -> LP_SCRATCH14_R { + LP_SCRATCH14_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE14") + .field( + "lp_scratch14", + &format_args!("{}", self.lp_scratch14().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch14(&mut self) -> LP_SCRATCH14_W { + LP_SCRATCH14_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE14_SPEC; +impl crate::RegisterSpec for LP_STORE14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store14::R`](R) reader structure"] +impl crate::Readable for LP_STORE14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store14::W`](W) writer structure"] +impl crate::Writable for LP_STORE14_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE14 to value 0"] +impl crate::Resettable for LP_STORE14_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store15.rs b/esp32p4/src/lp_sys/lp_store15.rs new file mode 100644 index 0000000000..8adfb4a60b --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store15.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE15` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE15` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH15` reader - need_des"] +pub type LP_SCRATCH15_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH15` writer - need_des"] +pub type LP_SCRATCH15_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch15(&self) -> LP_SCRATCH15_R { + LP_SCRATCH15_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE15") + .field( + "lp_scratch15", + &format_args!("{}", self.lp_scratch15().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch15(&mut self) -> LP_SCRATCH15_W { + LP_SCRATCH15_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE15_SPEC; +impl crate::RegisterSpec for LP_STORE15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store15::R`](R) reader structure"] +impl crate::Readable for LP_STORE15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store15::W`](W) writer structure"] +impl crate::Writable for LP_STORE15_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE15 to value 0"] +impl crate::Resettable for LP_STORE15_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store2.rs b/esp32p4/src/lp_sys/lp_store2.rs new file mode 100644 index 0000000000..002066d686 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH2` reader - need_des"] +pub type LP_SCRATCH2_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH2` writer - need_des"] +pub type LP_SCRATCH2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch2(&self) -> LP_SCRATCH2_R { + LP_SCRATCH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE2") + .field( + "lp_scratch2", + &format_args!("{}", self.lp_scratch2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch2(&mut self) -> LP_SCRATCH2_W { + LP_SCRATCH2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE2_SPEC; +impl crate::RegisterSpec for LP_STORE2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store2::R`](R) reader structure"] +impl crate::Readable for LP_STORE2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store2::W`](W) writer structure"] +impl crate::Writable for LP_STORE2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE2 to value 0"] +impl crate::Resettable for LP_STORE2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store3.rs b/esp32p4/src/lp_sys/lp_store3.rs new file mode 100644 index 0000000000..af7dfcfc64 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store3.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE3` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE3` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH3` reader - need_des"] +pub type LP_SCRATCH3_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH3` writer - need_des"] +pub type LP_SCRATCH3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch3(&self) -> LP_SCRATCH3_R { + LP_SCRATCH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE3") + .field( + "lp_scratch3", + &format_args!("{}", self.lp_scratch3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch3(&mut self) -> LP_SCRATCH3_W { + LP_SCRATCH3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE3_SPEC; +impl crate::RegisterSpec for LP_STORE3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store3::R`](R) reader structure"] +impl crate::Readable for LP_STORE3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store3::W`](W) writer structure"] +impl crate::Writable for LP_STORE3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE3 to value 0"] +impl crate::Resettable for LP_STORE3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store4.rs b/esp32p4/src/lp_sys/lp_store4.rs new file mode 100644 index 0000000000..64903e6f25 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store4.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE4` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE4` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH4` reader - need_des"] +pub type LP_SCRATCH4_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH4` writer - need_des"] +pub type LP_SCRATCH4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch4(&self) -> LP_SCRATCH4_R { + LP_SCRATCH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE4") + .field( + "lp_scratch4", + &format_args!("{}", self.lp_scratch4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch4(&mut self) -> LP_SCRATCH4_W { + LP_SCRATCH4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE4_SPEC; +impl crate::RegisterSpec for LP_STORE4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store4::R`](R) reader structure"] +impl crate::Readable for LP_STORE4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store4::W`](W) writer structure"] +impl crate::Writable for LP_STORE4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE4 to value 0"] +impl crate::Resettable for LP_STORE4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store5.rs b/esp32p4/src/lp_sys/lp_store5.rs new file mode 100644 index 0000000000..f64b3efe8f --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store5.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE5` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE5` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH5` reader - need_des"] +pub type LP_SCRATCH5_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH5` writer - need_des"] +pub type LP_SCRATCH5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch5(&self) -> LP_SCRATCH5_R { + LP_SCRATCH5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE5") + .field( + "lp_scratch5", + &format_args!("{}", self.lp_scratch5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch5(&mut self) -> LP_SCRATCH5_W { + LP_SCRATCH5_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE5_SPEC; +impl crate::RegisterSpec for LP_STORE5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store5::R`](R) reader structure"] +impl crate::Readable for LP_STORE5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store5::W`](W) writer structure"] +impl crate::Writable for LP_STORE5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE5 to value 0"] +impl crate::Resettable for LP_STORE5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store6.rs b/esp32p4/src/lp_sys/lp_store6.rs new file mode 100644 index 0000000000..cd21129419 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store6.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE6` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE6` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH6` reader - need_des"] +pub type LP_SCRATCH6_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH6` writer - need_des"] +pub type LP_SCRATCH6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch6(&self) -> LP_SCRATCH6_R { + LP_SCRATCH6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE6") + .field( + "lp_scratch6", + &format_args!("{}", self.lp_scratch6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch6(&mut self) -> LP_SCRATCH6_W { + LP_SCRATCH6_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE6_SPEC; +impl crate::RegisterSpec for LP_STORE6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store6::R`](R) reader structure"] +impl crate::Readable for LP_STORE6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store6::W`](W) writer structure"] +impl crate::Writable for LP_STORE6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE6 to value 0"] +impl crate::Resettable for LP_STORE6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store7.rs b/esp32p4/src/lp_sys/lp_store7.rs new file mode 100644 index 0000000000..5d536d37d6 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store7.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE7` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE7` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH7` reader - need_des"] +pub type LP_SCRATCH7_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH7` writer - need_des"] +pub type LP_SCRATCH7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch7(&self) -> LP_SCRATCH7_R { + LP_SCRATCH7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE7") + .field( + "lp_scratch7", + &format_args!("{}", self.lp_scratch7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch7(&mut self) -> LP_SCRATCH7_W { + LP_SCRATCH7_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE7_SPEC; +impl crate::RegisterSpec for LP_STORE7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store7::R`](R) reader structure"] +impl crate::Readable for LP_STORE7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store7::W`](W) writer structure"] +impl crate::Writable for LP_STORE7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE7 to value 0"] +impl crate::Resettable for LP_STORE7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store8.rs b/esp32p4/src/lp_sys/lp_store8.rs new file mode 100644 index 0000000000..fc3f00adbb --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store8.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE8` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE8` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH8` reader - need_des"] +pub type LP_SCRATCH8_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH8` writer - need_des"] +pub type LP_SCRATCH8_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch8(&self) -> LP_SCRATCH8_R { + LP_SCRATCH8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE8") + .field( + "lp_scratch8", + &format_args!("{}", self.lp_scratch8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch8(&mut self) -> LP_SCRATCH8_W { + LP_SCRATCH8_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE8_SPEC; +impl crate::RegisterSpec for LP_STORE8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store8::R`](R) reader structure"] +impl crate::Readable for LP_STORE8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store8::W`](W) writer structure"] +impl crate::Writable for LP_STORE8_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE8 to value 0"] +impl crate::Resettable for LP_STORE8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_store9.rs b/esp32p4/src/lp_sys/lp_store9.rs new file mode 100644 index 0000000000..c9cfe8d487 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_store9.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_STORE9` reader"] +pub type R = crate::R; +#[doc = "Register `LP_STORE9` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SCRATCH9` reader - need_des"] +pub type LP_SCRATCH9_R = crate::FieldReader; +#[doc = "Field `LP_SCRATCH9` writer - need_des"] +pub type LP_SCRATCH9_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_scratch9(&self) -> LP_SCRATCH9_R { + LP_SCRATCH9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_STORE9") + .field( + "lp_scratch9", + &format_args!("{}", self.lp_scratch9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_scratch9(&mut self) -> LP_SCRATCH9_W { + LP_SCRATCH9_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_store9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_store9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_STORE9_SPEC; +impl crate::RegisterSpec for LP_STORE9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_store9::R`](R) reader structure"] +impl crate::Readable for LP_STORE9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_store9::W`](W) writer structure"] +impl crate::Writable for LP_STORE9_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_STORE9 to value 0"] +impl crate::Resettable for LP_STORE9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_sys_ver_date.rs b/esp32p4/src/lp_sys/lp_sys_ver_date.rs new file mode 100644 index 0000000000..4274d8bda5 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_sys_ver_date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `LP_SYS_VER_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SYS_VER_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `VER_DATE` reader - need_des"] +pub type VER_DATE_R = crate::FieldReader; +#[doc = "Field `VER_DATE` writer - need_des"] +pub type VER_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn ver_date(&self) -> VER_DATE_R { + VER_DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SYS_VER_DATE") + .field("ver_date", &format_args!("{}", self.ver_date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn ver_date(&mut self) -> VER_DATE_W { + VER_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sys_ver_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sys_ver_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SYS_VER_DATE_SPEC; +impl crate::RegisterSpec for LP_SYS_VER_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_sys_ver_date::R`](R) reader structure"] +impl crate::Readable for LP_SYS_VER_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_sys_ver_date::W`](W) writer structure"] +impl crate::Writable for LP_SYS_VER_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SYS_VER_DATE to value 0x2023_0509"] +impl crate::Resettable for LP_SYS_VER_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2023_0509; +} diff --git a/esp32p4/src/lp_sys/lp_tcm_pwr_ctrl.rs b/esp32p4/src/lp_sys/lp_tcm_pwr_ctrl.rs new file mode 100644 index 0000000000..3db6b356bc --- /dev/null +++ b/esp32p4/src/lp_sys/lp_tcm_pwr_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `LP_TCM_PWR_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TCM_PWR_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_TCM_ROM_CLK_FORCE_ON` reader - need_des"] +pub type LP_TCM_ROM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `LP_TCM_ROM_CLK_FORCE_ON` writer - need_des"] +pub type LP_TCM_ROM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_TCM_RAM_CLK_FORCE_ON` reader - need_des"] +pub type LP_TCM_RAM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `LP_TCM_RAM_CLK_FORCE_ON` writer - need_des"] +pub type LP_TCM_RAM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 5 - need_des"] + #[inline(always)] + pub fn lp_tcm_rom_clk_force_on(&self) -> LP_TCM_ROM_CLK_FORCE_ON_R { + LP_TCM_ROM_CLK_FORCE_ON_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - need_des"] + #[inline(always)] + pub fn lp_tcm_ram_clk_force_on(&self) -> LP_TCM_RAM_CLK_FORCE_ON_R { + LP_TCM_RAM_CLK_FORCE_ON_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TCM_PWR_CTRL") + .field( + "lp_tcm_rom_clk_force_on", + &format_args!("{}", self.lp_tcm_rom_clk_force_on().bit()), + ) + .field( + "lp_tcm_ram_clk_force_on", + &format_args!("{}", self.lp_tcm_ram_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 5 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_tcm_rom_clk_force_on(&mut self) -> LP_TCM_ROM_CLK_FORCE_ON_W { + LP_TCM_ROM_CLK_FORCE_ON_W::new(self, 5) + } + #[doc = "Bit 7 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_tcm_ram_clk_force_on(&mut self) -> LP_TCM_RAM_CLK_FORCE_ON_W { + LP_TCM_RAM_CLK_FORCE_ON_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_pwr_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_pwr_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TCM_PWR_CTRL_SPEC; +impl crate::RegisterSpec for LP_TCM_PWR_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_tcm_pwr_ctrl::R`](R) reader structure"] +impl crate::Readable for LP_TCM_PWR_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_tcm_pwr_ctrl::W`](W) writer structure"] +impl crate::Writable for LP_TCM_PWR_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TCM_PWR_CTRL to value 0"] +impl crate::Resettable for LP_TCM_PWR_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_cs.rs b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_cs.rs new file mode 100644 index 0000000000..d6158adfba --- /dev/null +++ b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_cs.rs @@ -0,0 +1,77 @@ +#[doc = "Register `LP_TCM_RAM_RDN_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TCM_RAM_RDN_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `LP_TCM_RAM_RDN_ECO_EN` reader - need_des"] +pub type LP_TCM_RAM_RDN_ECO_EN_R = crate::BitReader; +#[doc = "Field `LP_TCM_RAM_RDN_ECO_EN` writer - need_des"] +pub type LP_TCM_RAM_RDN_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_TCM_RAM_RDN_ECO_RESULT` reader - need_des"] +pub type LP_TCM_RAM_RDN_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn lp_tcm_ram_rdn_eco_en(&self) -> LP_TCM_RAM_RDN_ECO_EN_R { + LP_TCM_RAM_RDN_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn lp_tcm_ram_rdn_eco_result(&self) -> LP_TCM_RAM_RDN_ECO_RESULT_R { + LP_TCM_RAM_RDN_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TCM_RAM_RDN_ECO_CS") + .field( + "lp_tcm_ram_rdn_eco_en", + &format_args!("{}", self.lp_tcm_ram_rdn_eco_en().bit()), + ) + .field( + "lp_tcm_ram_rdn_eco_result", + &format_args!("{}", self.lp_tcm_ram_rdn_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_tcm_ram_rdn_eco_en(&mut self) -> LP_TCM_RAM_RDN_ECO_EN_W { + LP_TCM_RAM_RDN_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_ram_rdn_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_ram_rdn_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TCM_RAM_RDN_ECO_CS_SPEC; +impl crate::RegisterSpec for LP_TCM_RAM_RDN_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_tcm_ram_rdn_eco_cs::R`](R) reader structure"] +impl crate::Readable for LP_TCM_RAM_RDN_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_tcm_ram_rdn_eco_cs::W`](W) writer structure"] +impl crate::Writable for LP_TCM_RAM_RDN_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TCM_RAM_RDN_ECO_CS to value 0"] +impl crate::Resettable for LP_TCM_RAM_RDN_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_high.rs b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_high.rs new file mode 100644 index 0000000000..4ae0ee5fe8 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_high.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_TCM_RAM_RDN_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TCM_RAM_RDN_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `LP_TCM_RAM_RDN_ECO_HIGH` reader - need_des"] +pub type LP_TCM_RAM_RDN_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `LP_TCM_RAM_RDN_ECO_HIGH` writer - need_des"] +pub type LP_TCM_RAM_RDN_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_tcm_ram_rdn_eco_high(&self) -> LP_TCM_RAM_RDN_ECO_HIGH_R { + LP_TCM_RAM_RDN_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TCM_RAM_RDN_ECO_HIGH") + .field( + "lp_tcm_ram_rdn_eco_high", + &format_args!("{}", self.lp_tcm_ram_rdn_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_tcm_ram_rdn_eco_high( + &mut self, + ) -> LP_TCM_RAM_RDN_ECO_HIGH_W { + LP_TCM_RAM_RDN_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_ram_rdn_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_ram_rdn_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TCM_RAM_RDN_ECO_HIGH_SPEC; +impl crate::RegisterSpec for LP_TCM_RAM_RDN_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_tcm_ram_rdn_eco_high::R`](R) reader structure"] +impl crate::Readable for LP_TCM_RAM_RDN_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_tcm_ram_rdn_eco_high::W`](W) writer structure"] +impl crate::Writable for LP_TCM_RAM_RDN_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TCM_RAM_RDN_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for LP_TCM_RAM_RDN_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_low.rs b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_low.rs new file mode 100644 index 0000000000..9649f922a0 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_low.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_TCM_RAM_RDN_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TCM_RAM_RDN_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `LP_TCM_RAM_RDN_ECO_LOW` reader - need_des"] +pub type LP_TCM_RAM_RDN_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `LP_TCM_RAM_RDN_ECO_LOW` writer - need_des"] +pub type LP_TCM_RAM_RDN_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_tcm_ram_rdn_eco_low(&self) -> LP_TCM_RAM_RDN_ECO_LOW_R { + LP_TCM_RAM_RDN_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TCM_RAM_RDN_ECO_LOW") + .field( + "lp_tcm_ram_rdn_eco_low", + &format_args!("{}", self.lp_tcm_ram_rdn_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_tcm_ram_rdn_eco_low( + &mut self, + ) -> LP_TCM_RAM_RDN_ECO_LOW_W { + LP_TCM_RAM_RDN_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_ram_rdn_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_ram_rdn_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TCM_RAM_RDN_ECO_LOW_SPEC; +impl crate::RegisterSpec for LP_TCM_RAM_RDN_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_tcm_ram_rdn_eco_low::R`](R) reader structure"] +impl crate::Readable for LP_TCM_RAM_RDN_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_tcm_ram_rdn_eco_low::W`](W) writer structure"] +impl crate::Writable for LP_TCM_RAM_RDN_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TCM_RAM_RDN_ECO_LOW to value 0"] +impl crate::Resettable for LP_TCM_RAM_RDN_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_cs.rs b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_cs.rs new file mode 100644 index 0000000000..81c23b540b --- /dev/null +++ b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_cs.rs @@ -0,0 +1,77 @@ +#[doc = "Register `LP_TCM_ROM_RDN_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TCM_ROM_RDN_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `LP_TCM_ROM_RDN_ECO_EN` reader - need_des"] +pub type LP_TCM_ROM_RDN_ECO_EN_R = crate::BitReader; +#[doc = "Field `LP_TCM_ROM_RDN_ECO_EN` writer - need_des"] +pub type LP_TCM_ROM_RDN_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_TCM_ROM_RDN_ECO_RESULT` reader - need_des"] +pub type LP_TCM_ROM_RDN_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn lp_tcm_rom_rdn_eco_en(&self) -> LP_TCM_ROM_RDN_ECO_EN_R { + LP_TCM_ROM_RDN_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn lp_tcm_rom_rdn_eco_result(&self) -> LP_TCM_ROM_RDN_ECO_RESULT_R { + LP_TCM_ROM_RDN_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TCM_ROM_RDN_ECO_CS") + .field( + "lp_tcm_rom_rdn_eco_en", + &format_args!("{}", self.lp_tcm_rom_rdn_eco_en().bit()), + ) + .field( + "lp_tcm_rom_rdn_eco_result", + &format_args!("{}", self.lp_tcm_rom_rdn_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_tcm_rom_rdn_eco_en(&mut self) -> LP_TCM_ROM_RDN_ECO_EN_W { + LP_TCM_ROM_RDN_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_rom_rdn_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_rom_rdn_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TCM_ROM_RDN_ECO_CS_SPEC; +impl crate::RegisterSpec for LP_TCM_ROM_RDN_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_tcm_rom_rdn_eco_cs::R`](R) reader structure"] +impl crate::Readable for LP_TCM_ROM_RDN_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_tcm_rom_rdn_eco_cs::W`](W) writer structure"] +impl crate::Writable for LP_TCM_ROM_RDN_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TCM_ROM_RDN_ECO_CS to value 0"] +impl crate::Resettable for LP_TCM_ROM_RDN_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_high.rs b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_high.rs new file mode 100644 index 0000000000..5430665d53 --- /dev/null +++ b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_high.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_TCM_ROM_RDN_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TCM_ROM_RDN_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `LP_TCM_ROM_RDN_ECO_HIGH` reader - need_des"] +pub type LP_TCM_ROM_RDN_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `LP_TCM_ROM_RDN_ECO_HIGH` writer - need_des"] +pub type LP_TCM_ROM_RDN_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_tcm_rom_rdn_eco_high(&self) -> LP_TCM_ROM_RDN_ECO_HIGH_R { + LP_TCM_ROM_RDN_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TCM_ROM_RDN_ECO_HIGH") + .field( + "lp_tcm_rom_rdn_eco_high", + &format_args!("{}", self.lp_tcm_rom_rdn_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_tcm_rom_rdn_eco_high( + &mut self, + ) -> LP_TCM_ROM_RDN_ECO_HIGH_W { + LP_TCM_ROM_RDN_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_rom_rdn_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_rom_rdn_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TCM_ROM_RDN_ECO_HIGH_SPEC; +impl crate::RegisterSpec for LP_TCM_ROM_RDN_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_tcm_rom_rdn_eco_high::R`](R) reader structure"] +impl crate::Readable for LP_TCM_ROM_RDN_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_tcm_rom_rdn_eco_high::W`](W) writer structure"] +impl crate::Writable for LP_TCM_ROM_RDN_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TCM_ROM_RDN_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for LP_TCM_ROM_RDN_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_low.rs b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_low.rs new file mode 100644 index 0000000000..44fd3ba1ab --- /dev/null +++ b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_low.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_TCM_ROM_RDN_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `LP_TCM_ROM_RDN_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `LP_TCM_ROM_RDN_ECO_LOW` reader - need_des"] +pub type LP_TCM_ROM_RDN_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `LP_TCM_ROM_RDN_ECO_LOW` writer - need_des"] +pub type LP_TCM_ROM_RDN_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn lp_tcm_rom_rdn_eco_low(&self) -> LP_TCM_ROM_RDN_ECO_LOW_R { + LP_TCM_ROM_RDN_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_TCM_ROM_RDN_ECO_LOW") + .field( + "lp_tcm_rom_rdn_eco_low", + &format_args!("{}", self.lp_tcm_rom_rdn_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_tcm_rom_rdn_eco_low( + &mut self, + ) -> LP_TCM_ROM_RDN_ECO_LOW_W { + LP_TCM_ROM_RDN_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_tcm_rom_rdn_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_tcm_rom_rdn_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_TCM_ROM_RDN_ECO_LOW_SPEC; +impl crate::RegisterSpec for LP_TCM_ROM_RDN_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_tcm_rom_rdn_eco_low::R`](R) reader structure"] +impl crate::Readable for LP_TCM_ROM_RDN_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_tcm_rom_rdn_eco_low::W`](W) writer structure"] +impl crate::Writable for LP_TCM_ROM_RDN_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_TCM_ROM_RDN_ECO_LOW to value 0"] +impl crate::Resettable for LP_TCM_ROM_RDN_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/pad_comp0.rs b/esp32p4/src/lp_sys/pad_comp0.rs new file mode 100644 index 0000000000..97d857e63a --- /dev/null +++ b/esp32p4/src/lp_sys/pad_comp0.rs @@ -0,0 +1,95 @@ +#[doc = "Register `PAD_COMP0` reader"] +pub type R = crate::R; +#[doc = "Register `PAD_COMP0` writer"] +pub type W = crate::W; +#[doc = "Field `DREF_COMP0` reader - pad comp dref"] +pub type DREF_COMP0_R = crate::FieldReader; +#[doc = "Field `DREF_COMP0` writer - pad comp dref"] +pub type DREF_COMP0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `MODE_COMP0` reader - pad comp mode"] +pub type MODE_COMP0_R = crate::BitReader; +#[doc = "Field `MODE_COMP0` writer - pad comp mode"] +pub type MODE_COMP0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XPD_COMP0` reader - pad comp xpd"] +pub type XPD_COMP0_R = crate::BitReader; +#[doc = "Field `XPD_COMP0` writer - pad comp xpd"] +pub type XPD_COMP0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - pad comp dref"] + #[inline(always)] + pub fn dref_comp0(&self) -> DREF_COMP0_R { + DREF_COMP0_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - pad comp mode"] + #[inline(always)] + pub fn mode_comp0(&self) -> MODE_COMP0_R { + MODE_COMP0_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - pad comp xpd"] + #[inline(always)] + pub fn xpd_comp0(&self) -> XPD_COMP0_R { + XPD_COMP0_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD_COMP0") + .field("dref_comp0", &format_args!("{}", self.dref_comp0().bits())) + .field("mode_comp0", &format_args!("{}", self.mode_comp0().bit())) + .field("xpd_comp0", &format_args!("{}", self.xpd_comp0().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - pad comp dref"] + #[inline(always)] + #[must_use] + pub fn dref_comp0(&mut self) -> DREF_COMP0_W { + DREF_COMP0_W::new(self, 0) + } + #[doc = "Bit 3 - pad comp mode"] + #[inline(always)] + #[must_use] + pub fn mode_comp0(&mut self) -> MODE_COMP0_W { + MODE_COMP0_W::new(self, 3) + } + #[doc = "Bit 4 - pad comp xpd"] + #[inline(always)] + #[must_use] + pub fn xpd_comp0(&mut self) -> XPD_COMP0_W { + XPD_COMP0_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_comp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_comp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD_COMP0_SPEC; +impl crate::RegisterSpec for PAD_COMP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad_comp0::R`](R) reader structure"] +impl crate::Readable for PAD_COMP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad_comp0::W`](W) writer structure"] +impl crate::Writable for PAD_COMP0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD_COMP0 to value 0"] +impl crate::Resettable for PAD_COMP0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/pad_comp1.rs b/esp32p4/src/lp_sys/pad_comp1.rs new file mode 100644 index 0000000000..9d1582c1f4 --- /dev/null +++ b/esp32p4/src/lp_sys/pad_comp1.rs @@ -0,0 +1,95 @@ +#[doc = "Register `PAD_COMP1` reader"] +pub type R = crate::R; +#[doc = "Register `PAD_COMP1` writer"] +pub type W = crate::W; +#[doc = "Field `DREF_COMP1` reader - pad comp dref"] +pub type DREF_COMP1_R = crate::FieldReader; +#[doc = "Field `DREF_COMP1` writer - pad comp dref"] +pub type DREF_COMP1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `MODE_COMP1` reader - pad comp mode"] +pub type MODE_COMP1_R = crate::BitReader; +#[doc = "Field `MODE_COMP1` writer - pad comp mode"] +pub type MODE_COMP1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XPD_COMP1` reader - pad comp xpd"] +pub type XPD_COMP1_R = crate::BitReader; +#[doc = "Field `XPD_COMP1` writer - pad comp xpd"] +pub type XPD_COMP1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - pad comp dref"] + #[inline(always)] + pub fn dref_comp1(&self) -> DREF_COMP1_R { + DREF_COMP1_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - pad comp mode"] + #[inline(always)] + pub fn mode_comp1(&self) -> MODE_COMP1_R { + MODE_COMP1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - pad comp xpd"] + #[inline(always)] + pub fn xpd_comp1(&self) -> XPD_COMP1_R { + XPD_COMP1_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAD_COMP1") + .field("dref_comp1", &format_args!("{}", self.dref_comp1().bits())) + .field("mode_comp1", &format_args!("{}", self.mode_comp1().bit())) + .field("xpd_comp1", &format_args!("{}", self.xpd_comp1().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - pad comp dref"] + #[inline(always)] + #[must_use] + pub fn dref_comp1(&mut self) -> DREF_COMP1_W { + DREF_COMP1_W::new(self, 0) + } + #[doc = "Bit 3 - pad comp mode"] + #[inline(always)] + #[must_use] + pub fn mode_comp1(&mut self) -> MODE_COMP1_W { + MODE_COMP1_W::new(self, 3) + } + #[doc = "Bit 4 - pad comp xpd"] + #[inline(always)] + #[must_use] + pub fn xpd_comp1(&mut self) -> XPD_COMP1_W { + XPD_COMP1_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_comp1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_comp1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAD_COMP1_SPEC; +impl crate::RegisterSpec for PAD_COMP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pad_comp1::R`](R) reader structure"] +impl crate::Readable for PAD_COMP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pad_comp1::W`](W) writer structure"] +impl crate::Writable for PAD_COMP1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PAD_COMP1 to value 0"] +impl crate::Resettable for PAD_COMP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/rng_cfg.rs b/esp32p4/src/lp_sys/rng_cfg.rs new file mode 100644 index 0000000000..b7045260f0 --- /dev/null +++ b/esp32p4/src/lp_sys/rng_cfg.rs @@ -0,0 +1,115 @@ +#[doc = "Register `RNG_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `RNG_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `RNG_TIMER_EN` reader - enable rng timer"] +pub type RNG_TIMER_EN_R = crate::BitReader; +#[doc = "Field `RNG_TIMER_EN` writer - enable rng timer"] +pub type RNG_TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RNG_TIMER_PSCALE` reader - configure ng timer pscale"] +pub type RNG_TIMER_PSCALE_R = crate::FieldReader; +#[doc = "Field `RNG_TIMER_PSCALE` writer - configure ng timer pscale"] +pub type RNG_TIMER_PSCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RNG_SAR_ENABLE` reader - enable rng_saradc"] +pub type RNG_SAR_ENABLE_R = crate::BitReader; +#[doc = "Field `RNG_SAR_ENABLE` writer - enable rng_saradc"] +pub type RNG_SAR_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RNG_SAR_DATA` reader - debug rng sar sample cnt"] +pub type RNG_SAR_DATA_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - enable rng timer"] + #[inline(always)] + pub fn rng_timer_en(&self) -> RNG_TIMER_EN_R { + RNG_TIMER_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:8 - configure ng timer pscale"] + #[inline(always)] + pub fn rng_timer_pscale(&self) -> RNG_TIMER_PSCALE_R { + RNG_TIMER_PSCALE_R::new(((self.bits >> 1) & 0xff) as u8) + } + #[doc = "Bit 9 - enable rng_saradc"] + #[inline(always)] + pub fn rng_sar_enable(&self) -> RNG_SAR_ENABLE_R { + RNG_SAR_ENABLE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 16:28 - debug rng sar sample cnt"] + #[inline(always)] + pub fn rng_sar_data(&self) -> RNG_SAR_DATA_R { + RNG_SAR_DATA_R::new(((self.bits >> 16) & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RNG_CFG") + .field( + "rng_timer_en", + &format_args!("{}", self.rng_timer_en().bit()), + ) + .field( + "rng_timer_pscale", + &format_args!("{}", self.rng_timer_pscale().bits()), + ) + .field( + "rng_sar_enable", + &format_args!("{}", self.rng_sar_enable().bit()), + ) + .field( + "rng_sar_data", + &format_args!("{}", self.rng_sar_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - enable rng timer"] + #[inline(always)] + #[must_use] + pub fn rng_timer_en(&mut self) -> RNG_TIMER_EN_W { + RNG_TIMER_EN_W::new(self, 0) + } + #[doc = "Bits 1:8 - configure ng timer pscale"] + #[inline(always)] + #[must_use] + pub fn rng_timer_pscale(&mut self) -> RNG_TIMER_PSCALE_W { + RNG_TIMER_PSCALE_W::new(self, 1) + } + #[doc = "Bit 9 - enable rng_saradc"] + #[inline(always)] + #[must_use] + pub fn rng_sar_enable(&mut self) -> RNG_SAR_ENABLE_W { + RNG_SAR_ENABLE_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "rng cfg register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RNG_CFG_SPEC; +impl crate::RegisterSpec for RNG_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rng_cfg::R`](R) reader structure"] +impl crate::Readable for RNG_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng_cfg::W`](W) writer structure"] +impl crate::Writable for RNG_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RNG_CFG to value 0x03"] +impl crate::Resettable for RNG_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/lp_sys/rng_data.rs b/esp32p4/src/lp_sys/rng_data.rs new file mode 100644 index 0000000000..4a1e115753 --- /dev/null +++ b/esp32p4/src/lp_sys/rng_data.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RNG_DATA` reader"] +pub type R = crate::R; +#[doc = "Field `RND_DATA` reader - result of rng output"] +pub type RND_DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - result of rng output"] + #[inline(always)] + pub fn rnd_data(&self) -> RND_DATA_R { + RND_DATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RNG_DATA") + .field("rnd_data", &format_args!("{}", self.rnd_data().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "rng data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RNG_DATA_SPEC; +impl crate::RegisterSpec for RNG_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rng_data::R`](R) reader structure"] +impl crate::Readable for RNG_DATA_SPEC {} +#[doc = "`reset()` method sets RNG_DATA to value 0"] +impl crate::Resettable for RNG_DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_sys/sys_ctrl.rs b/esp32p4/src/lp_sys/sys_ctrl.rs new file mode 100644 index 0000000000..90123d6914 --- /dev/null +++ b/esp32p4/src/lp_sys/sys_ctrl.rs @@ -0,0 +1,198 @@ +#[doc = "Register `SYS_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SYS_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_CORE_DISABLE` reader - lp cpu disable"] +pub type LP_CORE_DISABLE_R = crate::BitReader; +#[doc = "Field `LP_CORE_DISABLE` writer - lp cpu disable"] +pub type LP_CORE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYS_SW_RST` writer - digital system software reset bit"] +pub type SYS_SW_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_DOWNLOAD_BOOT` reader - need_des"] +pub type FORCE_DOWNLOAD_BOOT_R = crate::BitReader; +#[doc = "Field `FORCE_DOWNLOAD_BOOT` writer - need_des"] +pub type FORCE_DOWNLOAD_BOOT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIG_FIB` reader - need_des"] +pub type DIG_FIB_R = crate::FieldReader; +#[doc = "Field `DIG_FIB` writer - need_des"] +pub type DIG_FIB_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `IO_MUX_RESET_DISABLE` reader - reset disable bit for LP IOMUX"] +pub type IO_MUX_RESET_DISABLE_R = crate::BitReader; +#[doc = "Field `IO_MUX_RESET_DISABLE` writer - reset disable bit for LP IOMUX"] +pub type IO_MUX_RESET_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_FIB` reader - need_des"] +pub type ANA_FIB_R = crate::FieldReader; +#[doc = "Field `LP_FIB_SEL` reader - need_des"] +pub type LP_FIB_SEL_R = crate::FieldReader; +#[doc = "Field `LP_FIB_SEL` writer - need_des"] +pub type LP_FIB_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LP_CORE_ETM_WAKEUP_FLAG_CLR` writer - need_des"] +pub type LP_CORE_ETM_WAKEUP_FLAG_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CORE_ETM_WAKEUP_FLAG` reader - need_des"] +pub type LP_CORE_ETM_WAKEUP_FLAG_R = crate::BitReader; +#[doc = "Field `LP_CORE_ETM_WAKEUP_FLAG` writer - need_des"] +pub type LP_CORE_ETM_WAKEUP_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSTIMER_STALL_SEL` reader - 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from hp_core1"] +pub type SYSTIMER_STALL_SEL_R = crate::BitReader; +#[doc = "Field `SYSTIMER_STALL_SEL` writer - 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from hp_core1"] +pub type SYSTIMER_STALL_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - lp cpu disable"] + #[inline(always)] + pub fn lp_core_disable(&self) -> LP_CORE_DISABLE_R { + LP_CORE_DISABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + pub fn force_download_boot(&self) -> FORCE_DOWNLOAD_BOOT_R { + FORCE_DOWNLOAD_BOOT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:10 - need_des"] + #[inline(always)] + pub fn dig_fib(&self) -> DIG_FIB_R { + DIG_FIB_R::new(((self.bits >> 3) & 0xff) as u8) + } + #[doc = "Bit 11 - reset disable bit for LP IOMUX"] + #[inline(always)] + pub fn io_mux_reset_disable(&self) -> IO_MUX_RESET_DISABLE_R { + IO_MUX_RESET_DISABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 14:20 - need_des"] + #[inline(always)] + pub fn ana_fib(&self) -> ANA_FIB_R { + ANA_FIB_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bits 21:28 - need_des"] + #[inline(always)] + pub fn lp_fib_sel(&self) -> LP_FIB_SEL_R { + LP_FIB_SEL_R::new(((self.bits >> 21) & 0xff) as u8) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_core_etm_wakeup_flag(&self) -> LP_CORE_ETM_WAKEUP_FLAG_R { + LP_CORE_ETM_WAKEUP_FLAG_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from hp_core1"] + #[inline(always)] + pub fn systimer_stall_sel(&self) -> SYSTIMER_STALL_SEL_R { + SYSTIMER_STALL_SEL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYS_CTRL") + .field( + "lp_core_disable", + &format_args!("{}", self.lp_core_disable().bit()), + ) + .field( + "force_download_boot", + &format_args!("{}", self.force_download_boot().bit()), + ) + .field("dig_fib", &format_args!("{}", self.dig_fib().bits())) + .field( + "io_mux_reset_disable", + &format_args!("{}", self.io_mux_reset_disable().bit()), + ) + .field("ana_fib", &format_args!("{}", self.ana_fib().bits())) + .field("lp_fib_sel", &format_args!("{}", self.lp_fib_sel().bits())) + .field( + "lp_core_etm_wakeup_flag", + &format_args!("{}", self.lp_core_etm_wakeup_flag().bit()), + ) + .field( + "systimer_stall_sel", + &format_args!("{}", self.systimer_stall_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - lp cpu disable"] + #[inline(always)] + #[must_use] + pub fn lp_core_disable(&mut self) -> LP_CORE_DISABLE_W { + LP_CORE_DISABLE_W::new(self, 0) + } + #[doc = "Bit 1 - digital system software reset bit"] + #[inline(always)] + #[must_use] + pub fn sys_sw_rst(&mut self) -> SYS_SW_RST_W { + SYS_SW_RST_W::new(self, 1) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_download_boot(&mut self) -> FORCE_DOWNLOAD_BOOT_W { + FORCE_DOWNLOAD_BOOT_W::new(self, 2) + } + #[doc = "Bits 3:10 - need_des"] + #[inline(always)] + #[must_use] + pub fn dig_fib(&mut self) -> DIG_FIB_W { + DIG_FIB_W::new(self, 3) + } + #[doc = "Bit 11 - reset disable bit for LP IOMUX"] + #[inline(always)] + #[must_use] + pub fn io_mux_reset_disable(&mut self) -> IO_MUX_RESET_DISABLE_W { + IO_MUX_RESET_DISABLE_W::new(self, 11) + } + #[doc = "Bits 21:28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_fib_sel(&mut self) -> LP_FIB_SEL_W { + LP_FIB_SEL_W::new(self, 21) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_core_etm_wakeup_flag_clr(&mut self) -> LP_CORE_ETM_WAKEUP_FLAG_CLR_W { + LP_CORE_ETM_WAKEUP_FLAG_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_core_etm_wakeup_flag(&mut self) -> LP_CORE_ETM_WAKEUP_FLAG_W { + LP_CORE_ETM_WAKEUP_FLAG_W::new(self, 30) + } + #[doc = "Bit 31 - 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from hp_core1"] + #[inline(always)] + #[must_use] + pub fn systimer_stall_sel(&mut self) -> SYSTIMER_STALL_SEL_W { + SYSTIMER_STALL_SEL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYS_CTRL_SPEC; +impl crate::RegisterSpec for SYS_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sys_ctrl::R`](R) reader structure"] +impl crate::Readable for SYS_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sys_ctrl::W`](W) writer structure"] +impl crate::Writable for SYS_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYS_CTRL to value 0x1fff_c7f8"] +impl crate::Resettable for SYS_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x1fff_c7f8; +} diff --git a/esp32p4/src/lp_sys/usb_ctrl.rs b/esp32p4/src/lp_sys/usb_ctrl.rs new file mode 100644 index 0000000000..4fc87a6a0c --- /dev/null +++ b/esp32p4/src/lp_sys/usb_ctrl.rs @@ -0,0 +1,112 @@ +#[doc = "Register `USB_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `USB_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SW_HW_USB_PHY_SEL` reader - need_des"] +pub type SW_HW_USB_PHY_SEL_R = crate::BitReader; +#[doc = "Field `SW_HW_USB_PHY_SEL` writer - need_des"] +pub type SW_HW_USB_PHY_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_USB_PHY_SEL` reader - need_des"] +pub type SW_USB_PHY_SEL_R = crate::BitReader; +#[doc = "Field `SW_USB_PHY_SEL` writer - need_des"] +pub type SW_USB_PHY_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBOTG20_WAKEUP_CLR` writer - clear usb wakeup to PMU."] +pub type USBOTG20_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBOTG20_IN_SUSPEND` reader - indicate usb otg2.0 is in suspend state."] +pub type USBOTG20_IN_SUSPEND_R = crate::BitReader; +#[doc = "Field `USBOTG20_IN_SUSPEND` writer - indicate usb otg2.0 is in suspend state."] +pub type USBOTG20_IN_SUSPEND_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn sw_hw_usb_phy_sel(&self) -> SW_HW_USB_PHY_SEL_R { + SW_HW_USB_PHY_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn sw_usb_phy_sel(&self) -> SW_USB_PHY_SEL_R { + SW_USB_PHY_SEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - indicate usb otg2.0 is in suspend state."] + #[inline(always)] + pub fn usbotg20_in_suspend(&self) -> USBOTG20_IN_SUSPEND_R { + USBOTG20_IN_SUSPEND_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_CTRL") + .field( + "sw_hw_usb_phy_sel", + &format_args!("{}", self.sw_hw_usb_phy_sel().bit()), + ) + .field( + "sw_usb_phy_sel", + &format_args!("{}", self.sw_usb_phy_sel().bit()), + ) + .field( + "usbotg20_in_suspend", + &format_args!("{}", self.usbotg20_in_suspend().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn sw_hw_usb_phy_sel(&mut self) -> SW_HW_USB_PHY_SEL_W { + SW_HW_USB_PHY_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn sw_usb_phy_sel(&mut self) -> SW_USB_PHY_SEL_W { + SW_USB_PHY_SEL_W::new(self, 1) + } + #[doc = "Bit 2 - clear usb wakeup to PMU."] + #[inline(always)] + #[must_use] + pub fn usbotg20_wakeup_clr(&mut self) -> USBOTG20_WAKEUP_CLR_W { + USBOTG20_WAKEUP_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - indicate usb otg2.0 is in suspend state."] + #[inline(always)] + #[must_use] + pub fn usbotg20_in_suspend(&mut self) -> USBOTG20_IN_SUSPEND_W { + USBOTG20_IN_SUSPEND_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_CTRL_SPEC; +impl crate::RegisterSpec for USB_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_ctrl::R`](R) reader structure"] +impl crate::Readable for USB_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_ctrl::W`](W) writer structure"] +impl crate::Writable for USB_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USB_CTRL to value 0"] +impl crate::Resettable for USB_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer.rs b/esp32p4/src/lp_timer.rs new file mode 100644 index 0000000000..6fbd003e5a --- /dev/null +++ b/esp32p4/src/lp_timer.rs @@ -0,0 +1,198 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + tar0_low: TAR0_LOW, + tar0_high: TAR0_HIGH, + tar1_low: TAR1_LOW, + tar1_high: TAR1_HIGH, + update: UPDATE, + main_buf0_low: MAIN_BUF0_LOW, + main_buf0_high: MAIN_BUF0_HIGH, + main_buf1_low: MAIN_BUF1_LOW, + main_buf1_high: MAIN_BUF1_HIGH, + main_overflow: MAIN_OVERFLOW, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + lp_int_raw: LP_INT_RAW, + lp_int_st: LP_INT_ST, + lp_int_ena: LP_INT_ENA, + lp_int_clr: LP_INT_CLR, + _reserved18: [u8; 0x03b4], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - need_des"] + #[inline(always)] + pub const fn tar0_low(&self) -> &TAR0_LOW { + &self.tar0_low + } + #[doc = "0x04 - need_des"] + #[inline(always)] + pub const fn tar0_high(&self) -> &TAR0_HIGH { + &self.tar0_high + } + #[doc = "0x08 - need_des"] + #[inline(always)] + pub const fn tar1_low(&self) -> &TAR1_LOW { + &self.tar1_low + } + #[doc = "0x0c - need_des"] + #[inline(always)] + pub const fn tar1_high(&self) -> &TAR1_HIGH { + &self.tar1_high + } + #[doc = "0x10 - need_des"] + #[inline(always)] + pub const fn update(&self) -> &UPDATE { + &self.update + } + #[doc = "0x14 - need_des"] + #[inline(always)] + pub const fn main_buf0_low(&self) -> &MAIN_BUF0_LOW { + &self.main_buf0_low + } + #[doc = "0x18 - need_des"] + #[inline(always)] + pub const fn main_buf0_high(&self) -> &MAIN_BUF0_HIGH { + &self.main_buf0_high + } + #[doc = "0x1c - need_des"] + #[inline(always)] + pub const fn main_buf1_low(&self) -> &MAIN_BUF1_LOW { + &self.main_buf1_low + } + #[doc = "0x20 - need_des"] + #[inline(always)] + pub const fn main_buf1_high(&self) -> &MAIN_BUF1_HIGH { + &self.main_buf1_high + } + #[doc = "0x24 - need_des"] + #[inline(always)] + pub const fn main_overflow(&self) -> &MAIN_OVERFLOW { + &self.main_overflow + } + #[doc = "0x28 - need_des"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x2c - need_des"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x30 - need_des"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x34 - need_des"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x38 - need_des"] + #[inline(always)] + pub const fn lp_int_raw(&self) -> &LP_INT_RAW { + &self.lp_int_raw + } + #[doc = "0x3c - need_des"] + #[inline(always)] + pub const fn lp_int_st(&self) -> &LP_INT_ST { + &self.lp_int_st + } + #[doc = "0x40 - need_des"] + #[inline(always)] + pub const fn lp_int_ena(&self) -> &LP_INT_ENA { + &self.lp_int_ena + } + #[doc = "0x44 - need_des"] + #[inline(always)] + pub const fn lp_int_clr(&self) -> &LP_INT_CLR { + &self.lp_int_clr + } + #[doc = "0x3fc - need_des"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "TAR0_LOW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar0_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar0_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar0_low`] module"] +pub type TAR0_LOW = crate::Reg; +#[doc = "need_des"] +pub mod tar0_low; +#[doc = "TAR0_HIGH (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar0_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar0_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar0_high`] module"] +pub type TAR0_HIGH = crate::Reg; +#[doc = "need_des"] +pub mod tar0_high; +#[doc = "TAR1_LOW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar1_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar1_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar1_low`] module"] +pub type TAR1_LOW = crate::Reg; +#[doc = "need_des"] +pub mod tar1_low; +#[doc = "TAR1_HIGH (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar1_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar1_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tar1_high`] module"] +pub type TAR1_HIGH = crate::Reg; +#[doc = "need_des"] +pub mod tar1_high; +#[doc = "UPDATE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`update::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`update::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@update`] module"] +pub type UPDATE = crate::Reg; +#[doc = "need_des"] +pub mod update; +#[doc = "MAIN_BUF0_LOW (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_low::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@main_buf0_low`] module"] +pub type MAIN_BUF0_LOW = crate::Reg; +#[doc = "need_des"] +pub mod main_buf0_low; +#[doc = "MAIN_BUF0_HIGH (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_high::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@main_buf0_high`] module"] +pub type MAIN_BUF0_HIGH = crate::Reg; +#[doc = "need_des"] +pub mod main_buf0_high; +#[doc = "MAIN_BUF1_LOW (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_low::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@main_buf1_low`] module"] +pub type MAIN_BUF1_LOW = crate::Reg; +#[doc = "need_des"] +pub mod main_buf1_low; +#[doc = "MAIN_BUF1_HIGH (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_high::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@main_buf1_high`] module"] +pub type MAIN_BUF1_HIGH = crate::Reg; +#[doc = "need_des"] +pub mod main_buf1_high; +#[doc = "MAIN_OVERFLOW (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`main_overflow::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@main_overflow`] module"] +pub type MAIN_OVERFLOW = crate::Reg; +#[doc = "need_des"] +pub mod main_overflow; +#[doc = "INT_RAW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "need_des"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "need_des"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "need_des"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "need_des"] +pub mod int_clr; +#[doc = "LP_INT_RAW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_raw`] module"] +pub type LP_INT_RAW = crate::Reg; +#[doc = "need_des"] +pub mod lp_int_raw; +#[doc = "LP_INT_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_st`] module"] +pub type LP_INT_ST = crate::Reg; +#[doc = "need_des"] +pub mod lp_int_st; +#[doc = "LP_INT_ENA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_ena`] module"] +pub type LP_INT_ENA = crate::Reg; +#[doc = "need_des"] +pub mod lp_int_ena; +#[doc = "LP_INT_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_clr`] module"] +pub type LP_INT_CLR = crate::Reg; +#[doc = "need_des"] +pub mod lp_int_clr; +#[doc = "DATE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "need_des"] +pub mod date; diff --git a/esp32p4/src/lp_timer/date.rs b/esp32p4/src/lp_timer/date.rs new file mode 100644 index 0000000000..f8691cd3a8 --- /dev/null +++ b/esp32p4/src/lp_timer/date.rs @@ -0,0 +1,79 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - need_des"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - need_des"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `CLK_EN` reader - need_des"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - need_des"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0211_1150"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0211_1150; +} diff --git a/esp32p4/src/lp_timer/int_clr.rs b/esp32p4/src/lp_timer/int_clr.rs new file mode 100644 index 0000000000..bbb356e21f --- /dev/null +++ b/esp32p4/src/lp_timer/int_clr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `OVERFLOW_CLR` writer - need_des"] +pub type OVERFLOW_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOC_WAKEUP_INT_CLR` writer - need_des"] +pub type SOC_WAKEUP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn overflow_clr(&mut self) -> OVERFLOW_CLR_W { + OVERFLOW_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn soc_wakeup_int_clr(&mut self) -> SOC_WAKEUP_INT_CLR_W { + SOC_WAKEUP_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/int_ena.rs b/esp32p4/src/lp_timer/int_ena.rs new file mode 100644 index 0000000000..e2d285a46f --- /dev/null +++ b/esp32p4/src/lp_timer/int_ena.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `OVERFLOW_ENA` reader - need_des"] +pub type OVERFLOW_ENA_R = crate::BitReader; +#[doc = "Field `OVERFLOW_ENA` writer - need_des"] +pub type OVERFLOW_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOC_WAKEUP_INT_ENA` reader - need_des"] +pub type SOC_WAKEUP_INT_ENA_R = crate::BitReader; +#[doc = "Field `SOC_WAKEUP_INT_ENA` writer - need_des"] +pub type SOC_WAKEUP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn overflow_ena(&self) -> OVERFLOW_ENA_R { + OVERFLOW_ENA_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn soc_wakeup_int_ena(&self) -> SOC_WAKEUP_INT_ENA_R { + SOC_WAKEUP_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "overflow_ena", + &format_args!("{}", self.overflow_ena().bit()), + ) + .field( + "soc_wakeup_int_ena", + &format_args!("{}", self.soc_wakeup_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn overflow_ena(&mut self) -> OVERFLOW_ENA_W { + OVERFLOW_ENA_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn soc_wakeup_int_ena(&mut self) -> SOC_WAKEUP_INT_ENA_W { + SOC_WAKEUP_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/int_raw.rs b/esp32p4/src/lp_timer/int_raw.rs new file mode 100644 index 0000000000..630ac9f8a0 --- /dev/null +++ b/esp32p4/src/lp_timer/int_raw.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `OVERFLOW_RAW` reader - need_des"] +pub type OVERFLOW_RAW_R = crate::BitReader; +#[doc = "Field `OVERFLOW_RAW` writer - need_des"] +pub type OVERFLOW_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOC_WAKEUP_INT_RAW` reader - need_des"] +pub type SOC_WAKEUP_INT_RAW_R = crate::BitReader; +#[doc = "Field `SOC_WAKEUP_INT_RAW` writer - need_des"] +pub type SOC_WAKEUP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn overflow_raw(&self) -> OVERFLOW_RAW_R { + OVERFLOW_RAW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn soc_wakeup_int_raw(&self) -> SOC_WAKEUP_INT_RAW_R { + SOC_WAKEUP_INT_RAW_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "overflow_raw", + &format_args!("{}", self.overflow_raw().bit()), + ) + .field( + "soc_wakeup_int_raw", + &format_args!("{}", self.soc_wakeup_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn overflow_raw(&mut self) -> OVERFLOW_RAW_W { + OVERFLOW_RAW_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn soc_wakeup_int_raw(&mut self) -> SOC_WAKEUP_INT_RAW_W { + SOC_WAKEUP_INT_RAW_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/int_st.rs b/esp32p4/src/lp_timer/int_st.rs new file mode 100644 index 0000000000..f8fd817739 --- /dev/null +++ b/esp32p4/src/lp_timer/int_st.rs @@ -0,0 +1,47 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `OVERFLOW_ST` reader - need_des"] +pub type OVERFLOW_ST_R = crate::BitReader; +#[doc = "Field `SOC_WAKEUP_INT_ST` reader - need_des"] +pub type SOC_WAKEUP_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn overflow_st(&self) -> OVERFLOW_ST_R { + OVERFLOW_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn soc_wakeup_int_st(&self) -> SOC_WAKEUP_INT_ST_R { + SOC_WAKEUP_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field("overflow_st", &format_args!("{}", self.overflow_st().bit())) + .field( + "soc_wakeup_int_st", + &format_args!("{}", self.soc_wakeup_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/lp_int_clr.rs b/esp32p4/src/lp_timer/lp_int_clr.rs new file mode 100644 index 0000000000..62b438bbdc --- /dev/null +++ b/esp32p4/src/lp_timer/lp_int_clr.rs @@ -0,0 +1,52 @@ +#[doc = "Register `LP_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `MAIN_TIMER_OVERFLOW_LP_INT_CLR` writer - need_des"] +pub type MAIN_TIMER_OVERFLOW_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAIN_TIMER_LP_INT_CLR` writer - need_des"] +pub type MAIN_TIMER_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_overflow_lp_int_clr( + &mut self, + ) -> MAIN_TIMER_OVERFLOW_LP_INT_CLR_W { + MAIN_TIMER_OVERFLOW_LP_INT_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_lp_int_clr(&mut self) -> MAIN_TIMER_LP_INT_CLR_W { + MAIN_TIMER_LP_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_INT_CLR_SPEC; +impl crate::RegisterSpec for LP_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`lp_int_clr::W`](W) writer structure"] +impl crate::Writable for LP_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_INT_CLR to value 0"] +impl crate::Resettable for LP_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/lp_int_ena.rs b/esp32p4/src/lp_timer/lp_int_ena.rs new file mode 100644 index 0000000000..98b11fe4b8 --- /dev/null +++ b/esp32p4/src/lp_timer/lp_int_ena.rs @@ -0,0 +1,87 @@ +#[doc = "Register `LP_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `LP_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `MAIN_TIMER_OVERFLOW_LP_INT_ENA` reader - need_des"] +pub type MAIN_TIMER_OVERFLOW_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `MAIN_TIMER_OVERFLOW_LP_INT_ENA` writer - need_des"] +pub type MAIN_TIMER_OVERFLOW_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAIN_TIMER_LP_INT_ENA` reader - need_des"] +pub type MAIN_TIMER_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `MAIN_TIMER_LP_INT_ENA` writer - need_des"] +pub type MAIN_TIMER_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn main_timer_overflow_lp_int_ena(&self) -> MAIN_TIMER_OVERFLOW_LP_INT_ENA_R { + MAIN_TIMER_OVERFLOW_LP_INT_ENA_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn main_timer_lp_int_ena(&self) -> MAIN_TIMER_LP_INT_ENA_R { + MAIN_TIMER_LP_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_INT_ENA") + .field( + "main_timer_overflow_lp_int_ena", + &format_args!("{}", self.main_timer_overflow_lp_int_ena().bit()), + ) + .field( + "main_timer_lp_int_ena", + &format_args!("{}", self.main_timer_lp_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_overflow_lp_int_ena( + &mut self, + ) -> MAIN_TIMER_OVERFLOW_LP_INT_ENA_W { + MAIN_TIMER_OVERFLOW_LP_INT_ENA_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_lp_int_ena(&mut self) -> MAIN_TIMER_LP_INT_ENA_W { + MAIN_TIMER_LP_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_INT_ENA_SPEC; +impl crate::RegisterSpec for LP_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_int_ena::R`](R) reader structure"] +impl crate::Readable for LP_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_int_ena::W`](W) writer structure"] +impl crate::Writable for LP_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_INT_ENA to value 0"] +impl crate::Resettable for LP_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/lp_int_raw.rs b/esp32p4/src/lp_timer/lp_int_raw.rs new file mode 100644 index 0000000000..5febf25ccb --- /dev/null +++ b/esp32p4/src/lp_timer/lp_int_raw.rs @@ -0,0 +1,87 @@ +#[doc = "Register `LP_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `LP_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `MAIN_TIMER_OVERFLOW_LP_INT_RAW` reader - need_des"] +pub type MAIN_TIMER_OVERFLOW_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `MAIN_TIMER_OVERFLOW_LP_INT_RAW` writer - need_des"] +pub type MAIN_TIMER_OVERFLOW_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAIN_TIMER_LP_INT_RAW` reader - need_des"] +pub type MAIN_TIMER_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `MAIN_TIMER_LP_INT_RAW` writer - need_des"] +pub type MAIN_TIMER_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn main_timer_overflow_lp_int_raw(&self) -> MAIN_TIMER_OVERFLOW_LP_INT_RAW_R { + MAIN_TIMER_OVERFLOW_LP_INT_RAW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn main_timer_lp_int_raw(&self) -> MAIN_TIMER_LP_INT_RAW_R { + MAIN_TIMER_LP_INT_RAW_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_INT_RAW") + .field( + "main_timer_overflow_lp_int_raw", + &format_args!("{}", self.main_timer_overflow_lp_int_raw().bit()), + ) + .field( + "main_timer_lp_int_raw", + &format_args!("{}", self.main_timer_lp_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_overflow_lp_int_raw( + &mut self, + ) -> MAIN_TIMER_OVERFLOW_LP_INT_RAW_W { + MAIN_TIMER_OVERFLOW_LP_INT_RAW_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_lp_int_raw(&mut self) -> MAIN_TIMER_LP_INT_RAW_W { + MAIN_TIMER_LP_INT_RAW_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_INT_RAW_SPEC; +impl crate::RegisterSpec for LP_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_int_raw::R`](R) reader structure"] +impl crate::Readable for LP_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_int_raw::W`](W) writer structure"] +impl crate::Writable for LP_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_INT_RAW to value 0"] +impl crate::Resettable for LP_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/lp_int_st.rs b/esp32p4/src/lp_timer/lp_int_st.rs new file mode 100644 index 0000000000..92c3825dbe --- /dev/null +++ b/esp32p4/src/lp_timer/lp_int_st.rs @@ -0,0 +1,50 @@ +#[doc = "Register `LP_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `MAIN_TIMER_OVERFLOW_LP_INT_ST` reader - need_des"] +pub type MAIN_TIMER_OVERFLOW_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `MAIN_TIMER_LP_INT_ST` reader - need_des"] +pub type MAIN_TIMER_LP_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn main_timer_overflow_lp_int_st(&self) -> MAIN_TIMER_OVERFLOW_LP_INT_ST_R { + MAIN_TIMER_OVERFLOW_LP_INT_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn main_timer_lp_int_st(&self) -> MAIN_TIMER_LP_INT_ST_R { + MAIN_TIMER_LP_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_INT_ST") + .field( + "main_timer_overflow_lp_int_st", + &format_args!("{}", self.main_timer_overflow_lp_int_st().bit()), + ) + .field( + "main_timer_lp_int_st", + &format_args!("{}", self.main_timer_lp_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_INT_ST_SPEC; +impl crate::RegisterSpec for LP_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_int_st::R`](R) reader structure"] +impl crate::Readable for LP_INT_ST_SPEC {} +#[doc = "`reset()` method sets LP_INT_ST to value 0"] +impl crate::Resettable for LP_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/main_buf0_high.rs b/esp32p4/src/lp_timer/main_buf0_high.rs new file mode 100644 index 0000000000..82af878b1d --- /dev/null +++ b/esp32p4/src/lp_timer/main_buf0_high.rs @@ -0,0 +1,39 @@ +#[doc = "Register `MAIN_BUF0_HIGH` reader"] +pub type R = crate::R; +#[doc = "Field `MAIN_TIMER_BUF0_HIGH` reader - need_des"] +pub type MAIN_TIMER_BUF0_HIGH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn main_timer_buf0_high(&self) -> MAIN_TIMER_BUF0_HIGH_R { + MAIN_TIMER_BUF0_HIGH_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MAIN_BUF0_HIGH") + .field( + "main_timer_buf0_high", + &format_args!("{}", self.main_timer_buf0_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_high::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MAIN_BUF0_HIGH_SPEC; +impl crate::RegisterSpec for MAIN_BUF0_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`main_buf0_high::R`](R) reader structure"] +impl crate::Readable for MAIN_BUF0_HIGH_SPEC {} +#[doc = "`reset()` method sets MAIN_BUF0_HIGH to value 0"] +impl crate::Resettable for MAIN_BUF0_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/main_buf0_low.rs b/esp32p4/src/lp_timer/main_buf0_low.rs new file mode 100644 index 0000000000..34fd0a6698 --- /dev/null +++ b/esp32p4/src/lp_timer/main_buf0_low.rs @@ -0,0 +1,39 @@ +#[doc = "Register `MAIN_BUF0_LOW` reader"] +pub type R = crate::R; +#[doc = "Field `MAIN_TIMER_BUF0_LOW` reader - need_des"] +pub type MAIN_TIMER_BUF0_LOW_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn main_timer_buf0_low(&self) -> MAIN_TIMER_BUF0_LOW_R { + MAIN_TIMER_BUF0_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MAIN_BUF0_LOW") + .field( + "main_timer_buf0_low", + &format_args!("{}", self.main_timer_buf0_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_low::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MAIN_BUF0_LOW_SPEC; +impl crate::RegisterSpec for MAIN_BUF0_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`main_buf0_low::R`](R) reader structure"] +impl crate::Readable for MAIN_BUF0_LOW_SPEC {} +#[doc = "`reset()` method sets MAIN_BUF0_LOW to value 0"] +impl crate::Resettable for MAIN_BUF0_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/main_buf1_high.rs b/esp32p4/src/lp_timer/main_buf1_high.rs new file mode 100644 index 0000000000..7698563211 --- /dev/null +++ b/esp32p4/src/lp_timer/main_buf1_high.rs @@ -0,0 +1,39 @@ +#[doc = "Register `MAIN_BUF1_HIGH` reader"] +pub type R = crate::R; +#[doc = "Field `MAIN_TIMER_BUF1_HIGH` reader - need_des"] +pub type MAIN_TIMER_BUF1_HIGH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn main_timer_buf1_high(&self) -> MAIN_TIMER_BUF1_HIGH_R { + MAIN_TIMER_BUF1_HIGH_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MAIN_BUF1_HIGH") + .field( + "main_timer_buf1_high", + &format_args!("{}", self.main_timer_buf1_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_high::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MAIN_BUF1_HIGH_SPEC; +impl crate::RegisterSpec for MAIN_BUF1_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`main_buf1_high::R`](R) reader structure"] +impl crate::Readable for MAIN_BUF1_HIGH_SPEC {} +#[doc = "`reset()` method sets MAIN_BUF1_HIGH to value 0"] +impl crate::Resettable for MAIN_BUF1_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/main_buf1_low.rs b/esp32p4/src/lp_timer/main_buf1_low.rs new file mode 100644 index 0000000000..fec67aee31 --- /dev/null +++ b/esp32p4/src/lp_timer/main_buf1_low.rs @@ -0,0 +1,39 @@ +#[doc = "Register `MAIN_BUF1_LOW` reader"] +pub type R = crate::R; +#[doc = "Field `MAIN_TIMER_BUF1_LOW` reader - need_des"] +pub type MAIN_TIMER_BUF1_LOW_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn main_timer_buf1_low(&self) -> MAIN_TIMER_BUF1_LOW_R { + MAIN_TIMER_BUF1_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MAIN_BUF1_LOW") + .field( + "main_timer_buf1_low", + &format_args!("{}", self.main_timer_buf1_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_low::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MAIN_BUF1_LOW_SPEC; +impl crate::RegisterSpec for MAIN_BUF1_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`main_buf1_low::R`](R) reader structure"] +impl crate::Readable for MAIN_BUF1_LOW_SPEC {} +#[doc = "`reset()` method sets MAIN_BUF1_LOW to value 0"] +impl crate::Resettable for MAIN_BUF1_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/main_overflow.rs b/esp32p4/src/lp_timer/main_overflow.rs new file mode 100644 index 0000000000..073985b784 --- /dev/null +++ b/esp32p4/src/lp_timer/main_overflow.rs @@ -0,0 +1,42 @@ +#[doc = "Register `MAIN_OVERFLOW` writer"] +pub type W = crate::W; +#[doc = "Field `MAIN_TIMER_ALARM_LOAD` writer - need_des"] +pub type MAIN_TIMER_ALARM_LOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_alarm_load(&mut self) -> MAIN_TIMER_ALARM_LOAD_W { + MAIN_TIMER_ALARM_LOAD_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`main_overflow::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MAIN_OVERFLOW_SPEC; +impl crate::RegisterSpec for MAIN_OVERFLOW_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`main_overflow::W`](W) writer structure"] +impl crate::Writable for MAIN_OVERFLOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MAIN_OVERFLOW to value 0"] +impl crate::Resettable for MAIN_OVERFLOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/tar0_high.rs b/esp32p4/src/lp_timer/tar0_high.rs new file mode 100644 index 0000000000..c4f062faeb --- /dev/null +++ b/esp32p4/src/lp_timer/tar0_high.rs @@ -0,0 +1,74 @@ +#[doc = "Register `TAR0_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `TAR0_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `MAIN_TIMER_TAR_HIGH0` reader - need_des"] +pub type MAIN_TIMER_TAR_HIGH0_R = crate::FieldReader; +#[doc = "Field `MAIN_TIMER_TAR_HIGH0` writer - need_des"] +pub type MAIN_TIMER_TAR_HIGH0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `MAIN_TIMER_TAR_EN0` writer - need_des"] +pub type MAIN_TIMER_TAR_EN0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn main_timer_tar_high0(&self) -> MAIN_TIMER_TAR_HIGH0_R { + MAIN_TIMER_TAR_HIGH0_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TAR0_HIGH") + .field( + "main_timer_tar_high0", + &format_args!("{}", self.main_timer_tar_high0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_tar_high0(&mut self) -> MAIN_TIMER_TAR_HIGH0_W { + MAIN_TIMER_TAR_HIGH0_W::new(self, 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_tar_en0(&mut self) -> MAIN_TIMER_TAR_EN0_W { + MAIN_TIMER_TAR_EN0_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar0_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar0_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TAR0_HIGH_SPEC; +impl crate::RegisterSpec for TAR0_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tar0_high::R`](R) reader structure"] +impl crate::Readable for TAR0_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tar0_high::W`](W) writer structure"] +impl crate::Writable for TAR0_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TAR0_HIGH to value 0"] +impl crate::Resettable for TAR0_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/tar0_low.rs b/esp32p4/src/lp_timer/tar0_low.rs new file mode 100644 index 0000000000..f80b439264 --- /dev/null +++ b/esp32p4/src/lp_timer/tar0_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TAR0_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `TAR0_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `MAIN_TIMER_TAR_LOW0` reader - need_des"] +pub type MAIN_TIMER_TAR_LOW0_R = crate::FieldReader; +#[doc = "Field `MAIN_TIMER_TAR_LOW0` writer - need_des"] +pub type MAIN_TIMER_TAR_LOW0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn main_timer_tar_low0(&self) -> MAIN_TIMER_TAR_LOW0_R { + MAIN_TIMER_TAR_LOW0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TAR0_LOW") + .field( + "main_timer_tar_low0", + &format_args!("{}", self.main_timer_tar_low0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_tar_low0(&mut self) -> MAIN_TIMER_TAR_LOW0_W { + MAIN_TIMER_TAR_LOW0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar0_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar0_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TAR0_LOW_SPEC; +impl crate::RegisterSpec for TAR0_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tar0_low::R`](R) reader structure"] +impl crate::Readable for TAR0_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tar0_low::W`](W) writer structure"] +impl crate::Writable for TAR0_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TAR0_LOW to value 0"] +impl crate::Resettable for TAR0_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/tar1_high.rs b/esp32p4/src/lp_timer/tar1_high.rs new file mode 100644 index 0000000000..8c6a367fee --- /dev/null +++ b/esp32p4/src/lp_timer/tar1_high.rs @@ -0,0 +1,74 @@ +#[doc = "Register `TAR1_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `TAR1_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `MAIN_TIMER_TAR_HIGH1` reader - need_des"] +pub type MAIN_TIMER_TAR_HIGH1_R = crate::FieldReader; +#[doc = "Field `MAIN_TIMER_TAR_HIGH1` writer - need_des"] +pub type MAIN_TIMER_TAR_HIGH1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `MAIN_TIMER_TAR_EN1` writer - need_des"] +pub type MAIN_TIMER_TAR_EN1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn main_timer_tar_high1(&self) -> MAIN_TIMER_TAR_HIGH1_R { + MAIN_TIMER_TAR_HIGH1_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TAR1_HIGH") + .field( + "main_timer_tar_high1", + &format_args!("{}", self.main_timer_tar_high1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_tar_high1(&mut self) -> MAIN_TIMER_TAR_HIGH1_W { + MAIN_TIMER_TAR_HIGH1_W::new(self, 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_tar_en1(&mut self) -> MAIN_TIMER_TAR_EN1_W { + MAIN_TIMER_TAR_EN1_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar1_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar1_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TAR1_HIGH_SPEC; +impl crate::RegisterSpec for TAR1_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tar1_high::R`](R) reader structure"] +impl crate::Readable for TAR1_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tar1_high::W`](W) writer structure"] +impl crate::Writable for TAR1_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TAR1_HIGH to value 0"] +impl crate::Resettable for TAR1_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/tar1_low.rs b/esp32p4/src/lp_timer/tar1_low.rs new file mode 100644 index 0000000000..27b1beaf2c --- /dev/null +++ b/esp32p4/src/lp_timer/tar1_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TAR1_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `TAR1_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `MAIN_TIMER_TAR_LOW1` reader - need_des"] +pub type MAIN_TIMER_TAR_LOW1_R = crate::FieldReader; +#[doc = "Field `MAIN_TIMER_TAR_LOW1` writer - need_des"] +pub type MAIN_TIMER_TAR_LOW1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn main_timer_tar_low1(&self) -> MAIN_TIMER_TAR_LOW1_R { + MAIN_TIMER_TAR_LOW1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TAR1_LOW") + .field( + "main_timer_tar_low1", + &format_args!("{}", self.main_timer_tar_low1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_tar_low1(&mut self) -> MAIN_TIMER_TAR_LOW1_W { + MAIN_TIMER_TAR_LOW1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tar1_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tar1_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TAR1_LOW_SPEC; +impl crate::RegisterSpec for TAR1_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tar1_low::R`](R) reader structure"] +impl crate::Readable for TAR1_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tar1_low::W`](W) writer structure"] +impl crate::Writable for TAR1_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TAR1_LOW to value 0"] +impl crate::Resettable for TAR1_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_timer/update.rs b/esp32p4/src/lp_timer/update.rs new file mode 100644 index 0000000000..e517f7df7c --- /dev/null +++ b/esp32p4/src/lp_timer/update.rs @@ -0,0 +1,112 @@ +#[doc = "Register `UPDATE` reader"] +pub type R = crate::R; +#[doc = "Register `UPDATE` writer"] +pub type W = crate::W; +#[doc = "Field `MAIN_TIMER_UPDATE` writer - need_des"] +pub type MAIN_TIMER_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAIN_TIMER_XTAL_OFF` reader - need_des"] +pub type MAIN_TIMER_XTAL_OFF_R = crate::BitReader; +#[doc = "Field `MAIN_TIMER_XTAL_OFF` writer - need_des"] +pub type MAIN_TIMER_XTAL_OFF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAIN_TIMER_SYS_STALL` reader - need_des"] +pub type MAIN_TIMER_SYS_STALL_R = crate::BitReader; +#[doc = "Field `MAIN_TIMER_SYS_STALL` writer - need_des"] +pub type MAIN_TIMER_SYS_STALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAIN_TIMER_SYS_RST` reader - need_des"] +pub type MAIN_TIMER_SYS_RST_R = crate::BitReader; +#[doc = "Field `MAIN_TIMER_SYS_RST` writer - need_des"] +pub type MAIN_TIMER_SYS_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn main_timer_xtal_off(&self) -> MAIN_TIMER_XTAL_OFF_R { + MAIN_TIMER_XTAL_OFF_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn main_timer_sys_stall(&self) -> MAIN_TIMER_SYS_STALL_R { + MAIN_TIMER_SYS_STALL_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn main_timer_sys_rst(&self) -> MAIN_TIMER_SYS_RST_R { + MAIN_TIMER_SYS_RST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UPDATE") + .field( + "main_timer_xtal_off", + &format_args!("{}", self.main_timer_xtal_off().bit()), + ) + .field( + "main_timer_sys_stall", + &format_args!("{}", self.main_timer_sys_stall().bit()), + ) + .field( + "main_timer_sys_rst", + &format_args!("{}", self.main_timer_sys_rst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_update(&mut self) -> MAIN_TIMER_UPDATE_W { + MAIN_TIMER_UPDATE_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_xtal_off(&mut self) -> MAIN_TIMER_XTAL_OFF_W { + MAIN_TIMER_XTAL_OFF_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_sys_stall(&mut self) -> MAIN_TIMER_SYS_STALL_W { + MAIN_TIMER_SYS_STALL_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn main_timer_sys_rst(&mut self) -> MAIN_TIMER_SYS_RST_W { + MAIN_TIMER_SYS_RST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`update::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`update::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UPDATE_SPEC; +impl crate::RegisterSpec for UPDATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`update::R`](R) reader structure"] +impl crate::Readable for UPDATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`update::W`](W) writer structure"] +impl crate::Writable for UPDATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UPDATE to value 0"] +impl crate::Resettable for UPDATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch.rs b/esp32p4/src/lp_touch.rs new file mode 100644 index 0000000000..184a8b4752 --- /dev/null +++ b/esp32p4/src/lp_touch.rs @@ -0,0 +1,258 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + chn_status: CHN_STATUS, + status_0: STATUS_0, + status_1: STATUS_1, + status_2: STATUS_2, + status_3: STATUS_3, + status_4: STATUS_4, + status_5: STATUS_5, + status_6: STATUS_6, + status_7: STATUS_7, + status_8: STATUS_8, + status_9: STATUS_9, + status_10: STATUS_10, + status_11: STATUS_11, + status_12: STATUS_12, + status_13: STATUS_13, + status_14: STATUS_14, + status_15: STATUS_15, + status_16: STATUS_16, + status_17: STATUS_17, + chn_tmp_status: CHN_TMP_STATUS, + _reserved24: [u8; 0xa0], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - need_des"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x04 - need_des"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x08 - need_des"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x0c - need_des"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x10 - need_des"] + #[inline(always)] + pub const fn chn_status(&self) -> &CHN_STATUS { + &self.chn_status + } + #[doc = "0x14 - need_des"] + #[inline(always)] + pub const fn status_0(&self) -> &STATUS_0 { + &self.status_0 + } + #[doc = "0x18 - need_des"] + #[inline(always)] + pub const fn status_1(&self) -> &STATUS_1 { + &self.status_1 + } + #[doc = "0x1c - need_des"] + #[inline(always)] + pub const fn status_2(&self) -> &STATUS_2 { + &self.status_2 + } + #[doc = "0x20 - need_des"] + #[inline(always)] + pub const fn status_3(&self) -> &STATUS_3 { + &self.status_3 + } + #[doc = "0x24 - need_des"] + #[inline(always)] + pub const fn status_4(&self) -> &STATUS_4 { + &self.status_4 + } + #[doc = "0x28 - need_des"] + #[inline(always)] + pub const fn status_5(&self) -> &STATUS_5 { + &self.status_5 + } + #[doc = "0x2c - need_des"] + #[inline(always)] + pub const fn status_6(&self) -> &STATUS_6 { + &self.status_6 + } + #[doc = "0x30 - need_des"] + #[inline(always)] + pub const fn status_7(&self) -> &STATUS_7 { + &self.status_7 + } + #[doc = "0x34 - need_des"] + #[inline(always)] + pub const fn status_8(&self) -> &STATUS_8 { + &self.status_8 + } + #[doc = "0x38 - need_des"] + #[inline(always)] + pub const fn status_9(&self) -> &STATUS_9 { + &self.status_9 + } + #[doc = "0x3c - need_des"] + #[inline(always)] + pub const fn status_10(&self) -> &STATUS_10 { + &self.status_10 + } + #[doc = "0x40 - need_des"] + #[inline(always)] + pub const fn status_11(&self) -> &STATUS_11 { + &self.status_11 + } + #[doc = "0x44 - need_des"] + #[inline(always)] + pub const fn status_12(&self) -> &STATUS_12 { + &self.status_12 + } + #[doc = "0x48 - need_des"] + #[inline(always)] + pub const fn status_13(&self) -> &STATUS_13 { + &self.status_13 + } + #[doc = "0x4c - need_des"] + #[inline(always)] + pub const fn status_14(&self) -> &STATUS_14 { + &self.status_14 + } + #[doc = "0x50 - need_des"] + #[inline(always)] + pub const fn status_15(&self) -> &STATUS_15 { + &self.status_15 + } + #[doc = "0x54 - need_des"] + #[inline(always)] + pub const fn status_16(&self) -> &STATUS_16 { + &self.status_16 + } + #[doc = "0x58 - need_des"] + #[inline(always)] + pub const fn status_17(&self) -> &STATUS_17 { + &self.status_17 + } + #[doc = "0x5c - need_des"] + #[inline(always)] + pub const fn chn_tmp_status(&self) -> &CHN_TMP_STATUS { + &self.chn_tmp_status + } + #[doc = "0x100 - need_des"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "INT_RAW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "need_des"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "need_des"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "need_des"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "need_des"] +pub mod int_clr; +#[doc = "CHN_STATUS (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chn_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chn_status`] module"] +pub type CHN_STATUS = crate::Reg; +#[doc = "need_des"] +pub mod chn_status; +#[doc = "STATUS_0 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_0`] module"] +pub type STATUS_0 = crate::Reg; +#[doc = "need_des"] +pub mod status_0; +#[doc = "STATUS_1 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_1`] module"] +pub type STATUS_1 = crate::Reg; +#[doc = "need_des"] +pub mod status_1; +#[doc = "STATUS_2 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_2`] module"] +pub type STATUS_2 = crate::Reg; +#[doc = "need_des"] +pub mod status_2; +#[doc = "STATUS_3 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_3`] module"] +pub type STATUS_3 = crate::Reg; +#[doc = "need_des"] +pub mod status_3; +#[doc = "STATUS_4 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_4`] module"] +pub type STATUS_4 = crate::Reg; +#[doc = "need_des"] +pub mod status_4; +#[doc = "STATUS_5 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_5`] module"] +pub type STATUS_5 = crate::Reg; +#[doc = "need_des"] +pub mod status_5; +#[doc = "STATUS_6 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_6`] module"] +pub type STATUS_6 = crate::Reg; +#[doc = "need_des"] +pub mod status_6; +#[doc = "STATUS_7 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_7`] module"] +pub type STATUS_7 = crate::Reg; +#[doc = "need_des"] +pub mod status_7; +#[doc = "STATUS_8 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_8`] module"] +pub type STATUS_8 = crate::Reg; +#[doc = "need_des"] +pub mod status_8; +#[doc = "STATUS_9 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_9`] module"] +pub type STATUS_9 = crate::Reg; +#[doc = "need_des"] +pub mod status_9; +#[doc = "STATUS_10 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_10`] module"] +pub type STATUS_10 = crate::Reg; +#[doc = "need_des"] +pub mod status_10; +#[doc = "STATUS_11 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_11`] module"] +pub type STATUS_11 = crate::Reg; +#[doc = "need_des"] +pub mod status_11; +#[doc = "STATUS_12 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_12::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_12`] module"] +pub type STATUS_12 = crate::Reg; +#[doc = "need_des"] +pub mod status_12; +#[doc = "STATUS_13 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_13::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_13`] module"] +pub type STATUS_13 = crate::Reg; +#[doc = "need_des"] +pub mod status_13; +#[doc = "STATUS_14 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_14::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_14`] module"] +pub type STATUS_14 = crate::Reg; +#[doc = "need_des"] +pub mod status_14; +#[doc = "STATUS_15 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_15::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_15`] module"] +pub type STATUS_15 = crate::Reg; +#[doc = "need_des"] +pub mod status_15; +#[doc = "STATUS_16 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_16::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_16`] module"] +pub type STATUS_16 = crate::Reg; +#[doc = "need_des"] +pub mod status_16; +#[doc = "STATUS_17 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_17::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status_17`] module"] +pub type STATUS_17 = crate::Reg; +#[doc = "need_des"] +pub mod status_17; +#[doc = "CHN_TMP_STATUS (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chn_tmp_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chn_tmp_status`] module"] +pub type CHN_TMP_STATUS = crate::Reg; +#[doc = "need_des"] +pub mod chn_tmp_status; +#[doc = "DATE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "need_des"] +pub mod date; diff --git a/esp32p4/src/lp_touch/chn_status.rs b/esp32p4/src/lp_touch/chn_status.rs new file mode 100644 index 0000000000..46335a83e6 --- /dev/null +++ b/esp32p4/src/lp_touch/chn_status.rs @@ -0,0 +1,52 @@ +#[doc = "Register `CHN_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `PAD_ACTIVE` reader - need_des"] +pub type PAD_ACTIVE_R = crate::FieldReader; +#[doc = "Field `MEAS_DONE` reader - need_des"] +pub type MEAS_DONE_R = crate::BitReader; +#[doc = "Field `SCAN_CURR` reader - need_des"] +pub type SCAN_CURR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:14 - need_des"] + #[inline(always)] + pub fn pad_active(&self) -> PAD_ACTIVE_R { + PAD_ACTIVE_R::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bit 15 - need_des"] + #[inline(always)] + pub fn meas_done(&self) -> MEAS_DONE_R { + MEAS_DONE_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:19 - need_des"] + #[inline(always)] + pub fn scan_curr(&self) -> SCAN_CURR_R { + SCAN_CURR_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CHN_STATUS") + .field("pad_active", &format_args!("{}", self.pad_active().bits())) + .field("meas_done", &format_args!("{}", self.meas_done().bit())) + .field("scan_curr", &format_args!("{}", self.scan_curr().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chn_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHN_STATUS_SPEC; +impl crate::RegisterSpec for CHN_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chn_status::R`](R) reader structure"] +impl crate::Readable for CHN_STATUS_SPEC {} +#[doc = "`reset()` method sets CHN_STATUS to value 0"] +impl crate::Resettable for CHN_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/chn_tmp_status.rs b/esp32p4/src/lp_touch/chn_tmp_status.rs new file mode 100644 index 0000000000..ff26bbefea --- /dev/null +++ b/esp32p4/src/lp_touch/chn_tmp_status.rs @@ -0,0 +1,50 @@ +#[doc = "Register `CHN_TMP_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `PAD_INACTIVE_STATUS` reader - need_des"] +pub type PAD_INACTIVE_STATUS_R = crate::FieldReader; +#[doc = "Field `PAD_ACTIVE_STATUS` reader - need_des"] +pub type PAD_ACTIVE_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:14 - need_des"] + #[inline(always)] + pub fn pad_inactive_status(&self) -> PAD_INACTIVE_STATUS_R { + PAD_INACTIVE_STATUS_R::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bits 15:29 - need_des"] + #[inline(always)] + pub fn pad_active_status(&self) -> PAD_ACTIVE_STATUS_R { + PAD_ACTIVE_STATUS_R::new(((self.bits >> 15) & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CHN_TMP_STATUS") + .field( + "pad_inactive_status", + &format_args!("{}", self.pad_inactive_status().bits()), + ) + .field( + "pad_active_status", + &format_args!("{}", self.pad_active_status().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chn_tmp_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHN_TMP_STATUS_SPEC; +impl crate::RegisterSpec for CHN_TMP_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chn_tmp_status::R`](R) reader structure"] +impl crate::Readable for CHN_TMP_STATUS_SPEC {} +#[doc = "`reset()` method sets CHN_TMP_STATUS to value 0"] +impl crate::Resettable for CHN_TMP_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/date.rs b/esp32p4/src/lp_touch/date.rs new file mode 100644 index 0000000000..afcfd8004f --- /dev/null +++ b/esp32p4/src/lp_touch/date.rs @@ -0,0 +1,79 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `RTC_DATE` reader - need_des"] +pub type RTC_DATE_R = crate::FieldReader; +#[doc = "Field `RTC_DATE` writer - need_des"] +pub type RTC_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +#[doc = "Field `RTC_CLK_EN` reader - need_des"] +pub type RTC_CLK_EN_R = crate::BitReader; +#[doc = "Field `RTC_CLK_EN` writer - need_des"] +pub type RTC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:27 - need_des"] + #[inline(always)] + pub fn rtc_date(&self) -> RTC_DATE_R { + RTC_DATE_R::new(self.bits & 0x0fff_ffff) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn rtc_clk_en(&self) -> RTC_CLK_EN_R { + RTC_CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("rtc_date", &format_args!("{}", self.rtc_date().bits())) + .field("rtc_clk_en", &format_args!("{}", self.rtc_clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - need_des"] + #[inline(always)] + #[must_use] + pub fn rtc_date(&mut self) -> RTC_DATE_W { + RTC_DATE_W::new(self, 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn rtc_clk_en(&mut self) -> RTC_CLK_EN_W { + RTC_CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0023_0314"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0023_0314; +} diff --git a/esp32p4/src/lp_touch/int_clr.rs b/esp32p4/src/lp_touch/int_clr.rs new file mode 100644 index 0000000000..6113c08f79 --- /dev/null +++ b/esp32p4/src/lp_touch/int_clr.rs @@ -0,0 +1,82 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `SCAN_DONE_INT_CLR` writer - need_des"] +pub type SCAN_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DONE_INT_CLR` writer - need_des"] +pub type DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE_INT_CLR` writer - need_des"] +pub type ACTIVE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INACTIVE_INT_CLR` writer - need_des"] +pub type INACTIVE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMEOUT_INT_CLR` writer - need_des"] +pub type TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APPROACH_LOOP_DONE_INT_CLR` writer - need_des"] +pub type APPROACH_LOOP_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn scan_done_int_clr(&mut self) -> SCAN_DONE_INT_CLR_W { + SCAN_DONE_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn done_int_clr(&mut self) -> DONE_INT_CLR_W { + DONE_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + #[must_use] + pub fn active_int_clr(&mut self) -> ACTIVE_INT_CLR_W { + ACTIVE_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + #[must_use] + pub fn inactive_int_clr(&mut self) -> INACTIVE_INT_CLR_W { + INACTIVE_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + #[must_use] + pub fn timeout_int_clr(&mut self) -> TIMEOUT_INT_CLR_W { + TIMEOUT_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + #[must_use] + pub fn approach_loop_done_int_clr(&mut self) -> APPROACH_LOOP_DONE_INT_CLR_W { + APPROACH_LOOP_DONE_INT_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/int_ena.rs b/esp32p4/src/lp_touch/int_ena.rs new file mode 100644 index 0000000000..d4dedb20de --- /dev/null +++ b/esp32p4/src/lp_touch/int_ena.rs @@ -0,0 +1,161 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `SCAN_DONE_INT_ENA` reader - need_des"] +pub type SCAN_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SCAN_DONE_INT_ENA` writer - need_des"] +pub type SCAN_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DONE_INT_ENA` reader - need_des"] +pub type DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `DONE_INT_ENA` writer - need_des"] +pub type DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE_INT_ENA` reader - need_des"] +pub type ACTIVE_INT_ENA_R = crate::BitReader; +#[doc = "Field `ACTIVE_INT_ENA` writer - need_des"] +pub type ACTIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INACTIVE_INT_ENA` reader - need_des"] +pub type INACTIVE_INT_ENA_R = crate::BitReader; +#[doc = "Field `INACTIVE_INT_ENA` writer - need_des"] +pub type INACTIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMEOUT_INT_ENA` reader - need_des"] +pub type TIMEOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMEOUT_INT_ENA` writer - need_des"] +pub type TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APPROACH_LOOP_DONE_INT_ENA` reader - need_des"] +pub type APPROACH_LOOP_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `APPROACH_LOOP_DONE_INT_ENA` writer - need_des"] +pub type APPROACH_LOOP_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn scan_done_int_ena(&self) -> SCAN_DONE_INT_ENA_R { + SCAN_DONE_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn done_int_ena(&self) -> DONE_INT_ENA_R { + DONE_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + pub fn active_int_ena(&self) -> ACTIVE_INT_ENA_R { + ACTIVE_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + pub fn inactive_int_ena(&self) -> INACTIVE_INT_ENA_R { + INACTIVE_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + pub fn timeout_int_ena(&self) -> TIMEOUT_INT_ENA_R { + TIMEOUT_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + pub fn approach_loop_done_int_ena(&self) -> APPROACH_LOOP_DONE_INT_ENA_R { + APPROACH_LOOP_DONE_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "scan_done_int_ena", + &format_args!("{}", self.scan_done_int_ena().bit()), + ) + .field( + "done_int_ena", + &format_args!("{}", self.done_int_ena().bit()), + ) + .field( + "active_int_ena", + &format_args!("{}", self.active_int_ena().bit()), + ) + .field( + "inactive_int_ena", + &format_args!("{}", self.inactive_int_ena().bit()), + ) + .field( + "timeout_int_ena", + &format_args!("{}", self.timeout_int_ena().bit()), + ) + .field( + "approach_loop_done_int_ena", + &format_args!("{}", self.approach_loop_done_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn scan_done_int_ena(&mut self) -> SCAN_DONE_INT_ENA_W { + SCAN_DONE_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn done_int_ena(&mut self) -> DONE_INT_ENA_W { + DONE_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + #[must_use] + pub fn active_int_ena(&mut self) -> ACTIVE_INT_ENA_W { + ACTIVE_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + #[must_use] + pub fn inactive_int_ena(&mut self) -> INACTIVE_INT_ENA_W { + INACTIVE_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + #[must_use] + pub fn timeout_int_ena(&mut self) -> TIMEOUT_INT_ENA_W { + TIMEOUT_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + #[must_use] + pub fn approach_loop_done_int_ena(&mut self) -> APPROACH_LOOP_DONE_INT_ENA_W { + APPROACH_LOOP_DONE_INT_ENA_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/int_raw.rs b/esp32p4/src/lp_touch/int_raw.rs new file mode 100644 index 0000000000..cdc3a862e7 --- /dev/null +++ b/esp32p4/src/lp_touch/int_raw.rs @@ -0,0 +1,161 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `SCAN_DONE_INT_RAW` reader - need_des"] +pub type SCAN_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SCAN_DONE_INT_RAW` writer - need_des"] +pub type SCAN_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DONE_INT_RAW` reader - need_des"] +pub type DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `DONE_INT_RAW` writer - need_des"] +pub type DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE_INT_RAW` reader - need_des"] +pub type ACTIVE_INT_RAW_R = crate::BitReader; +#[doc = "Field `ACTIVE_INT_RAW` writer - need_des"] +pub type ACTIVE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INACTIVE_INT_RAW` reader - need_des"] +pub type INACTIVE_INT_RAW_R = crate::BitReader; +#[doc = "Field `INACTIVE_INT_RAW` writer - need_des"] +pub type INACTIVE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMEOUT_INT_RAW` reader - need_des"] +pub type TIMEOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMEOUT_INT_RAW` writer - need_des"] +pub type TIMEOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APPROACH_LOOP_DONE_INT_RAW` reader - need_des"] +pub type APPROACH_LOOP_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `APPROACH_LOOP_DONE_INT_RAW` writer - need_des"] +pub type APPROACH_LOOP_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn scan_done_int_raw(&self) -> SCAN_DONE_INT_RAW_R { + SCAN_DONE_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn done_int_raw(&self) -> DONE_INT_RAW_R { + DONE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + pub fn active_int_raw(&self) -> ACTIVE_INT_RAW_R { + ACTIVE_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + pub fn inactive_int_raw(&self) -> INACTIVE_INT_RAW_R { + INACTIVE_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + pub fn timeout_int_raw(&self) -> TIMEOUT_INT_RAW_R { + TIMEOUT_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + pub fn approach_loop_done_int_raw(&self) -> APPROACH_LOOP_DONE_INT_RAW_R { + APPROACH_LOOP_DONE_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "scan_done_int_raw", + &format_args!("{}", self.scan_done_int_raw().bit()), + ) + .field( + "done_int_raw", + &format_args!("{}", self.done_int_raw().bit()), + ) + .field( + "active_int_raw", + &format_args!("{}", self.active_int_raw().bit()), + ) + .field( + "inactive_int_raw", + &format_args!("{}", self.inactive_int_raw().bit()), + ) + .field( + "timeout_int_raw", + &format_args!("{}", self.timeout_int_raw().bit()), + ) + .field( + "approach_loop_done_int_raw", + &format_args!("{}", self.approach_loop_done_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn scan_done_int_raw(&mut self) -> SCAN_DONE_INT_RAW_W { + SCAN_DONE_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn done_int_raw(&mut self) -> DONE_INT_RAW_W { + DONE_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + #[must_use] + pub fn active_int_raw(&mut self) -> ACTIVE_INT_RAW_W { + ACTIVE_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + #[must_use] + pub fn inactive_int_raw(&mut self) -> INACTIVE_INT_RAW_W { + INACTIVE_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + #[must_use] + pub fn timeout_int_raw(&mut self) -> TIMEOUT_INT_RAW_W { + TIMEOUT_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + #[must_use] + pub fn approach_loop_done_int_raw(&mut self) -> APPROACH_LOOP_DONE_INT_RAW_W { + APPROACH_LOOP_DONE_INT_RAW_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/int_st.rs b/esp32p4/src/lp_touch/int_st.rs new file mode 100644 index 0000000000..f4c9ba5e95 --- /dev/null +++ b/esp32p4/src/lp_touch/int_st.rs @@ -0,0 +1,91 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `SCAN_DONE_INT_ST` reader - need_des"] +pub type SCAN_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `DONE_INT_ST` reader - need_des"] +pub type DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `ACTIVE_INT_ST` reader - need_des"] +pub type ACTIVE_INT_ST_R = crate::BitReader; +#[doc = "Field `INACTIVE_INT_ST` reader - need_des"] +pub type INACTIVE_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMEOUT_INT_ST` reader - need_des"] +pub type TIMEOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `APPROACH_LOOP_DONE_INT_ST` reader - need_des"] +pub type APPROACH_LOOP_DONE_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn scan_done_int_st(&self) -> SCAN_DONE_INT_ST_R { + SCAN_DONE_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn done_int_st(&self) -> DONE_INT_ST_R { + DONE_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + pub fn active_int_st(&self) -> ACTIVE_INT_ST_R { + ACTIVE_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + pub fn inactive_int_st(&self) -> INACTIVE_INT_ST_R { + INACTIVE_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + pub fn timeout_int_st(&self) -> TIMEOUT_INT_ST_R { + TIMEOUT_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + pub fn approach_loop_done_int_st(&self) -> APPROACH_LOOP_DONE_INT_ST_R { + APPROACH_LOOP_DONE_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "scan_done_int_st", + &format_args!("{}", self.scan_done_int_st().bit()), + ) + .field("done_int_st", &format_args!("{}", self.done_int_st().bit())) + .field( + "active_int_st", + &format_args!("{}", self.active_int_st().bit()), + ) + .field( + "inactive_int_st", + &format_args!("{}", self.inactive_int_st().bit()), + ) + .field( + "timeout_int_st", + &format_args!("{}", self.timeout_int_st().bit()), + ) + .field( + "approach_loop_done_int_st", + &format_args!("{}", self.approach_loop_done_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_0.rs b/esp32p4/src/lp_touch/status_0.rs new file mode 100644 index 0000000000..99a4c014d3 --- /dev/null +++ b/esp32p4/src/lp_touch/status_0.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_0` reader"] +pub type R = crate::R; +#[doc = "Field `PAD0_DATA` reader - need_des"] +pub type PAD0_DATA_R = crate::FieldReader; +#[doc = "Field `PAD0_DEBOUNCE_CNT` reader - need_des"] +pub type PAD0_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD0_NEG_NOISE_CNT` reader - need_des"] +pub type PAD0_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad0_data(&self) -> PAD0_DATA_R { + PAD0_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad0_debounce_cnt(&self) -> PAD0_DEBOUNCE_CNT_R { + PAD0_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad0_neg_noise_cnt(&self) -> PAD0_NEG_NOISE_CNT_R { + PAD0_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_0") + .field("pad0_data", &format_args!("{}", self.pad0_data().bits())) + .field( + "pad0_debounce_cnt", + &format_args!("{}", self.pad0_debounce_cnt().bits()), + ) + .field( + "pad0_neg_noise_cnt", + &format_args!("{}", self.pad0_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_0_SPEC; +impl crate::RegisterSpec for STATUS_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_0::R`](R) reader structure"] +impl crate::Readable for STATUS_0_SPEC {} +#[doc = "`reset()` method sets STATUS_0 to value 0"] +impl crate::Resettable for STATUS_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_1.rs b/esp32p4/src/lp_touch/status_1.rs new file mode 100644 index 0000000000..8381ac3c73 --- /dev/null +++ b/esp32p4/src/lp_touch/status_1.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_1` reader"] +pub type R = crate::R; +#[doc = "Field `PAD1_DATA` reader - need_des"] +pub type PAD1_DATA_R = crate::FieldReader; +#[doc = "Field `PAD1_DEBOUNCE_CNT` reader - need_des"] +pub type PAD1_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD1_NEG_NOISE_CNT` reader - need_des"] +pub type PAD1_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad1_data(&self) -> PAD1_DATA_R { + PAD1_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad1_debounce_cnt(&self) -> PAD1_DEBOUNCE_CNT_R { + PAD1_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad1_neg_noise_cnt(&self) -> PAD1_NEG_NOISE_CNT_R { + PAD1_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_1") + .field("pad1_data", &format_args!("{}", self.pad1_data().bits())) + .field( + "pad1_debounce_cnt", + &format_args!("{}", self.pad1_debounce_cnt().bits()), + ) + .field( + "pad1_neg_noise_cnt", + &format_args!("{}", self.pad1_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_1_SPEC; +impl crate::RegisterSpec for STATUS_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_1::R`](R) reader structure"] +impl crate::Readable for STATUS_1_SPEC {} +#[doc = "`reset()` method sets STATUS_1 to value 0"] +impl crate::Resettable for STATUS_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_10.rs b/esp32p4/src/lp_touch/status_10.rs new file mode 100644 index 0000000000..0fb9334912 --- /dev/null +++ b/esp32p4/src/lp_touch/status_10.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_10` reader"] +pub type R = crate::R; +#[doc = "Field `PAD10_DATA` reader - need_des"] +pub type PAD10_DATA_R = crate::FieldReader; +#[doc = "Field `PAD10_DEBOUNCE_CNT` reader - need_des"] +pub type PAD10_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD10_NEG_NOISE_CNT` reader - need_des"] +pub type PAD10_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad10_data(&self) -> PAD10_DATA_R { + PAD10_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad10_debounce_cnt(&self) -> PAD10_DEBOUNCE_CNT_R { + PAD10_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad10_neg_noise_cnt(&self) -> PAD10_NEG_NOISE_CNT_R { + PAD10_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_10") + .field("pad10_data", &format_args!("{}", self.pad10_data().bits())) + .field( + "pad10_debounce_cnt", + &format_args!("{}", self.pad10_debounce_cnt().bits()), + ) + .field( + "pad10_neg_noise_cnt", + &format_args!("{}", self.pad10_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_10_SPEC; +impl crate::RegisterSpec for STATUS_10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_10::R`](R) reader structure"] +impl crate::Readable for STATUS_10_SPEC {} +#[doc = "`reset()` method sets STATUS_10 to value 0"] +impl crate::Resettable for STATUS_10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_11.rs b/esp32p4/src/lp_touch/status_11.rs new file mode 100644 index 0000000000..fe9ee08680 --- /dev/null +++ b/esp32p4/src/lp_touch/status_11.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_11` reader"] +pub type R = crate::R; +#[doc = "Field `PAD11_DATA` reader - need_des"] +pub type PAD11_DATA_R = crate::FieldReader; +#[doc = "Field `PAD11_DEBOUNCE_CNT` reader - need_des"] +pub type PAD11_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD11_NEG_NOISE_CNT` reader - need_des"] +pub type PAD11_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad11_data(&self) -> PAD11_DATA_R { + PAD11_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad11_debounce_cnt(&self) -> PAD11_DEBOUNCE_CNT_R { + PAD11_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad11_neg_noise_cnt(&self) -> PAD11_NEG_NOISE_CNT_R { + PAD11_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_11") + .field("pad11_data", &format_args!("{}", self.pad11_data().bits())) + .field( + "pad11_debounce_cnt", + &format_args!("{}", self.pad11_debounce_cnt().bits()), + ) + .field( + "pad11_neg_noise_cnt", + &format_args!("{}", self.pad11_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_11_SPEC; +impl crate::RegisterSpec for STATUS_11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_11::R`](R) reader structure"] +impl crate::Readable for STATUS_11_SPEC {} +#[doc = "`reset()` method sets STATUS_11 to value 0"] +impl crate::Resettable for STATUS_11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_12.rs b/esp32p4/src/lp_touch/status_12.rs new file mode 100644 index 0000000000..9026813fcf --- /dev/null +++ b/esp32p4/src/lp_touch/status_12.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_12` reader"] +pub type R = crate::R; +#[doc = "Field `PAD12_DATA` reader - need_des"] +pub type PAD12_DATA_R = crate::FieldReader; +#[doc = "Field `PAD12_DEBOUNCE_CNT` reader - need_des"] +pub type PAD12_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD12_NEG_NOISE_CNT` reader - need_des"] +pub type PAD12_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad12_data(&self) -> PAD12_DATA_R { + PAD12_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad12_debounce_cnt(&self) -> PAD12_DEBOUNCE_CNT_R { + PAD12_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad12_neg_noise_cnt(&self) -> PAD12_NEG_NOISE_CNT_R { + PAD12_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_12") + .field("pad12_data", &format_args!("{}", self.pad12_data().bits())) + .field( + "pad12_debounce_cnt", + &format_args!("{}", self.pad12_debounce_cnt().bits()), + ) + .field( + "pad12_neg_noise_cnt", + &format_args!("{}", self.pad12_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_12::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_12_SPEC; +impl crate::RegisterSpec for STATUS_12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_12::R`](R) reader structure"] +impl crate::Readable for STATUS_12_SPEC {} +#[doc = "`reset()` method sets STATUS_12 to value 0"] +impl crate::Resettable for STATUS_12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_13.rs b/esp32p4/src/lp_touch/status_13.rs new file mode 100644 index 0000000000..cb955e5e86 --- /dev/null +++ b/esp32p4/src/lp_touch/status_13.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_13` reader"] +pub type R = crate::R; +#[doc = "Field `PAD13_DATA` reader - need_des"] +pub type PAD13_DATA_R = crate::FieldReader; +#[doc = "Field `PAD13_DEBOUNCE_CNT` reader - need_des"] +pub type PAD13_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD13_NEG_NOISE_CNT` reader - need_des"] +pub type PAD13_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad13_data(&self) -> PAD13_DATA_R { + PAD13_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad13_debounce_cnt(&self) -> PAD13_DEBOUNCE_CNT_R { + PAD13_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad13_neg_noise_cnt(&self) -> PAD13_NEG_NOISE_CNT_R { + PAD13_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_13") + .field("pad13_data", &format_args!("{}", self.pad13_data().bits())) + .field( + "pad13_debounce_cnt", + &format_args!("{}", self.pad13_debounce_cnt().bits()), + ) + .field( + "pad13_neg_noise_cnt", + &format_args!("{}", self.pad13_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_13::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_13_SPEC; +impl crate::RegisterSpec for STATUS_13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_13::R`](R) reader structure"] +impl crate::Readable for STATUS_13_SPEC {} +#[doc = "`reset()` method sets STATUS_13 to value 0"] +impl crate::Resettable for STATUS_13_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_14.rs b/esp32p4/src/lp_touch/status_14.rs new file mode 100644 index 0000000000..971fee9b06 --- /dev/null +++ b/esp32p4/src/lp_touch/status_14.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_14` reader"] +pub type R = crate::R; +#[doc = "Field `PAD14_DATA` reader - need_des"] +pub type PAD14_DATA_R = crate::FieldReader; +#[doc = "Field `PAD14_DEBOUNCE_CNT` reader - need_des"] +pub type PAD14_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD14_NEG_NOISE_CNT` reader - need_des"] +pub type PAD14_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad14_data(&self) -> PAD14_DATA_R { + PAD14_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad14_debounce_cnt(&self) -> PAD14_DEBOUNCE_CNT_R { + PAD14_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad14_neg_noise_cnt(&self) -> PAD14_NEG_NOISE_CNT_R { + PAD14_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_14") + .field("pad14_data", &format_args!("{}", self.pad14_data().bits())) + .field( + "pad14_debounce_cnt", + &format_args!("{}", self.pad14_debounce_cnt().bits()), + ) + .field( + "pad14_neg_noise_cnt", + &format_args!("{}", self.pad14_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_14::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_14_SPEC; +impl crate::RegisterSpec for STATUS_14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_14::R`](R) reader structure"] +impl crate::Readable for STATUS_14_SPEC {} +#[doc = "`reset()` method sets STATUS_14 to value 0"] +impl crate::Resettable for STATUS_14_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_15.rs b/esp32p4/src/lp_touch/status_15.rs new file mode 100644 index 0000000000..d697031c8a --- /dev/null +++ b/esp32p4/src/lp_touch/status_15.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_15` reader"] +pub type R = crate::R; +#[doc = "Field `SLP_DATA` reader - need_des"] +pub type SLP_DATA_R = crate::FieldReader; +#[doc = "Field `SLP_DEBOUNCE_CNT` reader - need_des"] +pub type SLP_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `SLP_NEG_NOISE_CNT` reader - need_des"] +pub type SLP_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn slp_data(&self) -> SLP_DATA_R { + SLP_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn slp_debounce_cnt(&self) -> SLP_DEBOUNCE_CNT_R { + SLP_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn slp_neg_noise_cnt(&self) -> SLP_NEG_NOISE_CNT_R { + SLP_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_15") + .field("slp_data", &format_args!("{}", self.slp_data().bits())) + .field( + "slp_debounce_cnt", + &format_args!("{}", self.slp_debounce_cnt().bits()), + ) + .field( + "slp_neg_noise_cnt", + &format_args!("{}", self.slp_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_15::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_15_SPEC; +impl crate::RegisterSpec for STATUS_15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_15::R`](R) reader structure"] +impl crate::Readable for STATUS_15_SPEC {} +#[doc = "`reset()` method sets STATUS_15 to value 0"] +impl crate::Resettable for STATUS_15_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_16.rs b/esp32p4/src/lp_touch/status_16.rs new file mode 100644 index 0000000000..13748a7612 --- /dev/null +++ b/esp32p4/src/lp_touch/status_16.rs @@ -0,0 +1,72 @@ +#[doc = "Register `STATUS_16` reader"] +pub type R = crate::R; +#[doc = "Field `APPROACH_PAD2_CNT` reader - need_des"] +pub type APPROACH_PAD2_CNT_R = crate::FieldReader; +#[doc = "Field `APPROACH_PAD1_CNT` reader - need_des"] +pub type APPROACH_PAD1_CNT_R = crate::FieldReader; +#[doc = "Field `APPROACH_PAD0_CNT` reader - need_des"] +pub type APPROACH_PAD0_CNT_R = crate::FieldReader; +#[doc = "Field `SLP_APPROACH_CNT` reader - need_des"] +pub type SLP_APPROACH_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + pub fn approach_pad2_cnt(&self) -> APPROACH_PAD2_CNT_R { + APPROACH_PAD2_CNT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - need_des"] + #[inline(always)] + pub fn approach_pad1_cnt(&self) -> APPROACH_PAD1_CNT_R { + APPROACH_PAD1_CNT_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + pub fn approach_pad0_cnt(&self) -> APPROACH_PAD0_CNT_R { + APPROACH_PAD0_CNT_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + pub fn slp_approach_cnt(&self) -> SLP_APPROACH_CNT_R { + SLP_APPROACH_CNT_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_16") + .field( + "approach_pad2_cnt", + &format_args!("{}", self.approach_pad2_cnt().bits()), + ) + .field( + "approach_pad1_cnt", + &format_args!("{}", self.approach_pad1_cnt().bits()), + ) + .field( + "approach_pad0_cnt", + &format_args!("{}", self.approach_pad0_cnt().bits()), + ) + .field( + "slp_approach_cnt", + &format_args!("{}", self.slp_approach_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_16::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_16_SPEC; +impl crate::RegisterSpec for STATUS_16_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_16::R`](R) reader structure"] +impl crate::Readable for STATUS_16_SPEC {} +#[doc = "`reset()` method sets STATUS_16 to value 0"] +impl crate::Resettable for STATUS_16_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_17.rs b/esp32p4/src/lp_touch/status_17.rs new file mode 100644 index 0000000000..62c452fbbc --- /dev/null +++ b/esp32p4/src/lp_touch/status_17.rs @@ -0,0 +1,79 @@ +#[doc = "Register `STATUS_17` reader"] +pub type R = crate::R; +#[doc = "Field `DCAP_LPF` reader - Reserved"] +pub type DCAP_LPF_R = crate::FieldReader; +#[doc = "Field `DRES_LPF` reader - need_des"] +pub type DRES_LPF_R = crate::FieldReader; +#[doc = "Field `DRV_LS` reader - need_des"] +pub type DRV_LS_R = crate::FieldReader; +#[doc = "Field `DRV_HS` reader - need_des"] +pub type DRV_HS_R = crate::FieldReader; +#[doc = "Field `DBIAS` reader - need_des"] +pub type DBIAS_R = crate::FieldReader; +#[doc = "Field `RTC_FREQ_SCAN_CNT` reader - need_des"] +pub type RTC_FREQ_SCAN_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:6 - Reserved"] + #[inline(always)] + pub fn dcap_lpf(&self) -> DCAP_LPF_R { + DCAP_LPF_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:8 - need_des"] + #[inline(always)] + pub fn dres_lpf(&self) -> DRES_LPF_R { + DRES_LPF_R::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 9:12 - need_des"] + #[inline(always)] + pub fn drv_ls(&self) -> DRV_LS_R { + DRV_LS_R::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bits 13:17 - need_des"] + #[inline(always)] + pub fn drv_hs(&self) -> DRV_HS_R { + DRV_HS_R::new(((self.bits >> 13) & 0x1f) as u8) + } + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + pub fn dbias(&self) -> DBIAS_R { + DBIAS_R::new(((self.bits >> 18) & 0x1f) as u8) + } + #[doc = "Bits 23:24 - need_des"] + #[inline(always)] + pub fn rtc_freq_scan_cnt(&self) -> RTC_FREQ_SCAN_CNT_R { + RTC_FREQ_SCAN_CNT_R::new(((self.bits >> 23) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_17") + .field("dcap_lpf", &format_args!("{}", self.dcap_lpf().bits())) + .field("dres_lpf", &format_args!("{}", self.dres_lpf().bits())) + .field("drv_ls", &format_args!("{}", self.drv_ls().bits())) + .field("drv_hs", &format_args!("{}", self.drv_hs().bits())) + .field("dbias", &format_args!("{}", self.dbias().bits())) + .field( + "rtc_freq_scan_cnt", + &format_args!("{}", self.rtc_freq_scan_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_17::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_17_SPEC; +impl crate::RegisterSpec for STATUS_17_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_17::R`](R) reader structure"] +impl crate::Readable for STATUS_17_SPEC {} +#[doc = "`reset()` method sets STATUS_17 to value 0"] +impl crate::Resettable for STATUS_17_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_2.rs b/esp32p4/src/lp_touch/status_2.rs new file mode 100644 index 0000000000..3c8c63f930 --- /dev/null +++ b/esp32p4/src/lp_touch/status_2.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_2` reader"] +pub type R = crate::R; +#[doc = "Field `PAD2_DATA` reader - need_des"] +pub type PAD2_DATA_R = crate::FieldReader; +#[doc = "Field `PAD2_DEBOUNCE_CNT` reader - need_des"] +pub type PAD2_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD2_NEG_NOISE_CNT` reader - need_des"] +pub type PAD2_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad2_data(&self) -> PAD2_DATA_R { + PAD2_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad2_debounce_cnt(&self) -> PAD2_DEBOUNCE_CNT_R { + PAD2_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad2_neg_noise_cnt(&self) -> PAD2_NEG_NOISE_CNT_R { + PAD2_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_2") + .field("pad2_data", &format_args!("{}", self.pad2_data().bits())) + .field( + "pad2_debounce_cnt", + &format_args!("{}", self.pad2_debounce_cnt().bits()), + ) + .field( + "pad2_neg_noise_cnt", + &format_args!("{}", self.pad2_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_2_SPEC; +impl crate::RegisterSpec for STATUS_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_2::R`](R) reader structure"] +impl crate::Readable for STATUS_2_SPEC {} +#[doc = "`reset()` method sets STATUS_2 to value 0"] +impl crate::Resettable for STATUS_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_3.rs b/esp32p4/src/lp_touch/status_3.rs new file mode 100644 index 0000000000..3e728d314f --- /dev/null +++ b/esp32p4/src/lp_touch/status_3.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_3` reader"] +pub type R = crate::R; +#[doc = "Field `PAD3_DATA` reader - need_des"] +pub type PAD3_DATA_R = crate::FieldReader; +#[doc = "Field `PAD3_DEBOUNCE_CNT` reader - need_des"] +pub type PAD3_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD3_NEG_NOISE_CNT` reader - need_des"] +pub type PAD3_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad3_data(&self) -> PAD3_DATA_R { + PAD3_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad3_debounce_cnt(&self) -> PAD3_DEBOUNCE_CNT_R { + PAD3_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad3_neg_noise_cnt(&self) -> PAD3_NEG_NOISE_CNT_R { + PAD3_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_3") + .field("pad3_data", &format_args!("{}", self.pad3_data().bits())) + .field( + "pad3_debounce_cnt", + &format_args!("{}", self.pad3_debounce_cnt().bits()), + ) + .field( + "pad3_neg_noise_cnt", + &format_args!("{}", self.pad3_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_3_SPEC; +impl crate::RegisterSpec for STATUS_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_3::R`](R) reader structure"] +impl crate::Readable for STATUS_3_SPEC {} +#[doc = "`reset()` method sets STATUS_3 to value 0"] +impl crate::Resettable for STATUS_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_4.rs b/esp32p4/src/lp_touch/status_4.rs new file mode 100644 index 0000000000..25db62caff --- /dev/null +++ b/esp32p4/src/lp_touch/status_4.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_4` reader"] +pub type R = crate::R; +#[doc = "Field `PAD4_DATA` reader - need_des"] +pub type PAD4_DATA_R = crate::FieldReader; +#[doc = "Field `PAD4_DEBOUNCE_CNT` reader - need_des"] +pub type PAD4_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD4_NEG_NOISE_CNT` reader - need_des"] +pub type PAD4_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad4_data(&self) -> PAD4_DATA_R { + PAD4_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad4_debounce_cnt(&self) -> PAD4_DEBOUNCE_CNT_R { + PAD4_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad4_neg_noise_cnt(&self) -> PAD4_NEG_NOISE_CNT_R { + PAD4_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_4") + .field("pad4_data", &format_args!("{}", self.pad4_data().bits())) + .field( + "pad4_debounce_cnt", + &format_args!("{}", self.pad4_debounce_cnt().bits()), + ) + .field( + "pad4_neg_noise_cnt", + &format_args!("{}", self.pad4_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_4_SPEC; +impl crate::RegisterSpec for STATUS_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_4::R`](R) reader structure"] +impl crate::Readable for STATUS_4_SPEC {} +#[doc = "`reset()` method sets STATUS_4 to value 0"] +impl crate::Resettable for STATUS_4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_5.rs b/esp32p4/src/lp_touch/status_5.rs new file mode 100644 index 0000000000..c641d5422e --- /dev/null +++ b/esp32p4/src/lp_touch/status_5.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_5` reader"] +pub type R = crate::R; +#[doc = "Field `PAD5_DATA` reader - need_des"] +pub type PAD5_DATA_R = crate::FieldReader; +#[doc = "Field `PAD5_DEBOUNCE_CNT` reader - need_des"] +pub type PAD5_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD5_NEG_NOISE_CNT` reader - need_des"] +pub type PAD5_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad5_data(&self) -> PAD5_DATA_R { + PAD5_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad5_debounce_cnt(&self) -> PAD5_DEBOUNCE_CNT_R { + PAD5_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad5_neg_noise_cnt(&self) -> PAD5_NEG_NOISE_CNT_R { + PAD5_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_5") + .field("pad5_data", &format_args!("{}", self.pad5_data().bits())) + .field( + "pad5_debounce_cnt", + &format_args!("{}", self.pad5_debounce_cnt().bits()), + ) + .field( + "pad5_neg_noise_cnt", + &format_args!("{}", self.pad5_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_5_SPEC; +impl crate::RegisterSpec for STATUS_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_5::R`](R) reader structure"] +impl crate::Readable for STATUS_5_SPEC {} +#[doc = "`reset()` method sets STATUS_5 to value 0"] +impl crate::Resettable for STATUS_5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_6.rs b/esp32p4/src/lp_touch/status_6.rs new file mode 100644 index 0000000000..e8001ce070 --- /dev/null +++ b/esp32p4/src/lp_touch/status_6.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_6` reader"] +pub type R = crate::R; +#[doc = "Field `PAD6_DATA` reader - need_des"] +pub type PAD6_DATA_R = crate::FieldReader; +#[doc = "Field `PAD6_DEBOUNCE_CNT` reader - need_des"] +pub type PAD6_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD6_NEG_NOISE_CNT` reader - need_des"] +pub type PAD6_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad6_data(&self) -> PAD6_DATA_R { + PAD6_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad6_debounce_cnt(&self) -> PAD6_DEBOUNCE_CNT_R { + PAD6_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad6_neg_noise_cnt(&self) -> PAD6_NEG_NOISE_CNT_R { + PAD6_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_6") + .field("pad6_data", &format_args!("{}", self.pad6_data().bits())) + .field( + "pad6_debounce_cnt", + &format_args!("{}", self.pad6_debounce_cnt().bits()), + ) + .field( + "pad6_neg_noise_cnt", + &format_args!("{}", self.pad6_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_6_SPEC; +impl crate::RegisterSpec for STATUS_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_6::R`](R) reader structure"] +impl crate::Readable for STATUS_6_SPEC {} +#[doc = "`reset()` method sets STATUS_6 to value 0"] +impl crate::Resettable for STATUS_6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_7.rs b/esp32p4/src/lp_touch/status_7.rs new file mode 100644 index 0000000000..869563e62c --- /dev/null +++ b/esp32p4/src/lp_touch/status_7.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_7` reader"] +pub type R = crate::R; +#[doc = "Field `PAD7_DATA` reader - need_des"] +pub type PAD7_DATA_R = crate::FieldReader; +#[doc = "Field `PAD7_DEBOUNCE_CNT` reader - need_des"] +pub type PAD7_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD7_NEG_NOISE_CNT` reader - need_des"] +pub type PAD7_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad7_data(&self) -> PAD7_DATA_R { + PAD7_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad7_debounce_cnt(&self) -> PAD7_DEBOUNCE_CNT_R { + PAD7_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad7_neg_noise_cnt(&self) -> PAD7_NEG_NOISE_CNT_R { + PAD7_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_7") + .field("pad7_data", &format_args!("{}", self.pad7_data().bits())) + .field( + "pad7_debounce_cnt", + &format_args!("{}", self.pad7_debounce_cnt().bits()), + ) + .field( + "pad7_neg_noise_cnt", + &format_args!("{}", self.pad7_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_7_SPEC; +impl crate::RegisterSpec for STATUS_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_7::R`](R) reader structure"] +impl crate::Readable for STATUS_7_SPEC {} +#[doc = "`reset()` method sets STATUS_7 to value 0"] +impl crate::Resettable for STATUS_7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_8.rs b/esp32p4/src/lp_touch/status_8.rs new file mode 100644 index 0000000000..4bdb871c1f --- /dev/null +++ b/esp32p4/src/lp_touch/status_8.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_8` reader"] +pub type R = crate::R; +#[doc = "Field `PAD8_DATA` reader - need_des"] +pub type PAD8_DATA_R = crate::FieldReader; +#[doc = "Field `PAD8_DEBOUNCE_CNT` reader - need_des"] +pub type PAD8_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD8_NEG_NOISE_CNT` reader - need_des"] +pub type PAD8_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad8_data(&self) -> PAD8_DATA_R { + PAD8_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad8_debounce_cnt(&self) -> PAD8_DEBOUNCE_CNT_R { + PAD8_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad8_neg_noise_cnt(&self) -> PAD8_NEG_NOISE_CNT_R { + PAD8_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_8") + .field("pad8_data", &format_args!("{}", self.pad8_data().bits())) + .field( + "pad8_debounce_cnt", + &format_args!("{}", self.pad8_debounce_cnt().bits()), + ) + .field( + "pad8_neg_noise_cnt", + &format_args!("{}", self.pad8_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_8_SPEC; +impl crate::RegisterSpec for STATUS_8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_8::R`](R) reader structure"] +impl crate::Readable for STATUS_8_SPEC {} +#[doc = "`reset()` method sets STATUS_8 to value 0"] +impl crate::Resettable for STATUS_8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_touch/status_9.rs b/esp32p4/src/lp_touch/status_9.rs new file mode 100644 index 0000000000..05665238e3 --- /dev/null +++ b/esp32p4/src/lp_touch/status_9.rs @@ -0,0 +1,58 @@ +#[doc = "Register `STATUS_9` reader"] +pub type R = crate::R; +#[doc = "Field `PAD9_DATA` reader - need_des"] +pub type PAD9_DATA_R = crate::FieldReader; +#[doc = "Field `PAD9_DEBOUNCE_CNT` reader - need_des"] +pub type PAD9_DEBOUNCE_CNT_R = crate::FieldReader; +#[doc = "Field `PAD9_NEG_NOISE_CNT` reader - need_des"] +pub type PAD9_NEG_NOISE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pad9_data(&self) -> PAD9_DATA_R { + PAD9_DATA_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn pad9_debounce_cnt(&self) -> PAD9_DEBOUNCE_CNT_R { + PAD9_DEBOUNCE_CNT_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn pad9_neg_noise_cnt(&self) -> PAD9_NEG_NOISE_CNT_R { + PAD9_NEG_NOISE_CNT_R::new(((self.bits >> 19) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS_9") + .field("pad9_data", &format_args!("{}", self.pad9_data().bits())) + .field( + "pad9_debounce_cnt", + &format_args!("{}", self.pad9_debounce_cnt().bits()), + ) + .field( + "pad9_neg_noise_cnt", + &format_args!("{}", self.pad9_neg_noise_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_9_SPEC; +impl crate::RegisterSpec for STATUS_9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status_9::R`](R) reader structure"] +impl crate::Readable for STATUS_9_SPEC {} +#[doc = "`reset()` method sets STATUS_9 to value 0"] +impl crate::Resettable for STATUS_9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_tsens.rs b/esp32p4/src/lp_tsens.rs new file mode 100644 index 0000000000..9f399c8cf4 --- /dev/null +++ b/esp32p4/src/lp_tsens.rs @@ -0,0 +1,147 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + ctrl: CTRL, + ctrl2: CTRL2, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + clk_conf: CLK_CONF, + int_ena_w1ts: INT_ENA_W1TS, + int_ena_w1tc: INT_ENA_W1TC, + wakeup_ctrl: WAKEUP_CTRL, + sample_rate: SAMPLE_RATE, + rnd_eco_low: RND_ECO_LOW, + rnd_eco_high: RND_ECO_HIGH, + rnd_eco_cs: RND_ECO_CS, +} +impl RegisterBlock { + #[doc = "0x00 - Tsens configuration."] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0x04 - Tsens configuration."] + #[inline(always)] + pub const fn ctrl2(&self) -> &CTRL2 { + &self.ctrl2 + } + #[doc = "0x08 - Tsens interrupt raw registers."] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x0c - Tsens interrupt status registers."] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x10 - Tsens interrupt enable registers."] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x14 - Tsens interrupt clear registers."] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x18 - Tsens regbank configuration registers."] + #[inline(always)] + pub const fn clk_conf(&self) -> &CLK_CONF { + &self.clk_conf + } + #[doc = "0x1c - Tsens wakeup interrupt enable assert."] + #[inline(always)] + pub const fn int_ena_w1ts(&self) -> &INT_ENA_W1TS { + &self.int_ena_w1ts + } + #[doc = "0x20 - Tsens wakeup interrupt enable deassert."] + #[inline(always)] + pub const fn int_ena_w1tc(&self) -> &INT_ENA_W1TC { + &self.int_ena_w1tc + } + #[doc = "0x24 - Tsens wakeup control registers."] + #[inline(always)] + pub const fn wakeup_ctrl(&self) -> &WAKEUP_CTRL { + &self.wakeup_ctrl + } + #[doc = "0x28 - Hardware automatic sampling control registers."] + #[inline(always)] + pub const fn sample_rate(&self) -> &SAMPLE_RATE { + &self.sample_rate + } + #[doc = "0x2c - N/A"] + #[inline(always)] + pub const fn rnd_eco_low(&self) -> &RND_ECO_LOW { + &self.rnd_eco_low + } + #[doc = "0x30 - N/A"] + #[inline(always)] + pub const fn rnd_eco_high(&self) -> &RND_ECO_HIGH { + &self.rnd_eco_high + } + #[doc = "0x34 - N/A"] + #[inline(always)] + pub const fn rnd_eco_cs(&self) -> &RND_ECO_CS { + &self.rnd_eco_cs + } +} +#[doc = "CTRL (rw) register accessor: Tsens configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +pub type CTRL = crate::Reg; +#[doc = "Tsens configuration."] +pub mod ctrl; +#[doc = "CTRL2 (rw) register accessor: Tsens configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2`] module"] +pub type CTRL2 = crate::Reg; +#[doc = "Tsens configuration."] +pub mod ctrl2; +#[doc = "INT_RAW (rw) register accessor: Tsens interrupt raw registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Tsens interrupt raw registers."] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Tsens interrupt status registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Tsens interrupt status registers."] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: Tsens interrupt enable registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Tsens interrupt enable registers."] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: Tsens interrupt clear registers.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Tsens interrupt clear registers."] +pub mod int_clr; +#[doc = "CLK_CONF (rw) register accessor: Tsens regbank configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"] +pub type CLK_CONF = crate::Reg; +#[doc = "Tsens regbank configuration registers."] +pub mod clk_conf; +#[doc = "INT_ENA_W1TS (w) register accessor: Tsens wakeup interrupt enable assert.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena_w1ts::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena_w1ts`] module"] +pub type INT_ENA_W1TS = crate::Reg; +#[doc = "Tsens wakeup interrupt enable assert."] +pub mod int_ena_w1ts; +#[doc = "INT_ENA_W1TC (w) register accessor: Tsens wakeup interrupt enable deassert.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena_w1tc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena_w1tc`] module"] +pub type INT_ENA_W1TC = crate::Reg; +#[doc = "Tsens wakeup interrupt enable deassert."] +pub mod int_ena_w1tc; +#[doc = "WAKEUP_CTRL (rw) register accessor: Tsens wakeup control registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeup_ctrl`] module"] +pub type WAKEUP_CTRL = crate::Reg; +#[doc = "Tsens wakeup control registers."] +pub mod wakeup_ctrl; +#[doc = "SAMPLE_RATE (rw) register accessor: Hardware automatic sampling control registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_rate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_rate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sample_rate`] module"] +pub type SAMPLE_RATE = crate::Reg; +#[doc = "Hardware automatic sampling control registers."] +pub mod sample_rate; +#[doc = "RND_ECO_LOW (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_low`] module"] +pub type RND_ECO_LOW = crate::Reg; +#[doc = "N/A"] +pub mod rnd_eco_low; +#[doc = "RND_ECO_HIGH (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_high`] module"] +pub type RND_ECO_HIGH = crate::Reg; +#[doc = "N/A"] +pub mod rnd_eco_high; +#[doc = "RND_ECO_CS (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_eco_cs`] module"] +pub type RND_ECO_CS = crate::Reg; +#[doc = "N/A"] +pub mod rnd_eco_cs; diff --git a/esp32p4/src/lp_tsens/clk_conf.rs b/esp32p4/src/lp_tsens/clk_conf.rs new file mode 100644 index 0000000000..457ef15dc7 --- /dev/null +++ b/esp32p4/src/lp_tsens/clk_conf.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - Tsens regbank clock gating enable."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Tsens regbank clock gating enable."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Tsens regbank clock gating enable."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_CONF") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Tsens regbank clock gating enable."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tsens regbank configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_CONF_SPEC; +impl crate::RegisterSpec for CLK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"] +impl crate::Readable for CLK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"] +impl crate::Writable for CLK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_CONF to value 0"] +impl crate::Resettable for CLK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_tsens/ctrl.rs b/esp32p4/src/lp_tsens/ctrl.rs new file mode 100644 index 0000000000..7ad2a63e6f --- /dev/null +++ b/esp32p4/src/lp_tsens/ctrl.rs @@ -0,0 +1,178 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `OUT` reader - Temperature sensor data out."] +pub type OUT_R = crate::FieldReader; +#[doc = "Field `READY` reader - Indicate temperature sensor out ready."] +pub type READY_R = crate::BitReader; +#[doc = "Field `SAMPLE_EN` reader - Enable sample signal for wakeup module."] +pub type SAMPLE_EN_R = crate::BitReader; +#[doc = "Field `SAMPLE_EN` writer - Enable sample signal for wakeup module."] +pub type SAMPLE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAKEUP_MASK` reader - Wake up signal mask."] +pub type WAKEUP_MASK_R = crate::BitReader; +#[doc = "Field `WAKEUP_MASK` writer - Wake up signal mask."] +pub type WAKEUP_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INT_EN` reader - Enable temperature sensor to send out interrupt."] +pub type INT_EN_R = crate::BitReader; +#[doc = "Field `INT_EN` writer - Enable temperature sensor to send out interrupt."] +pub type INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_INV` reader - Invert temperature sensor data."] +pub type IN_INV_R = crate::BitReader; +#[doc = "Field `IN_INV` writer - Invert temperature sensor data."] +pub type IN_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_DIV` reader - Temperature sensor clock divider."] +pub type CLK_DIV_R = crate::FieldReader; +#[doc = "Field `CLK_DIV` writer - Temperature sensor clock divider."] +pub type CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `POWER_UP` reader - Temperature sensor power up."] +pub type POWER_UP_R = crate::BitReader; +#[doc = "Field `POWER_UP` writer - Temperature sensor power up."] +pub type POWER_UP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `POWER_UP_FORCE` reader - 1: dump out & power up controlled by SW, 0: by FSM."] +pub type POWER_UP_FORCE_R = crate::BitReader; +#[doc = "Field `POWER_UP_FORCE` writer - 1: dump out & power up controlled by SW, 0: by FSM."] +pub type POWER_UP_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Temperature sensor data out."] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - Indicate temperature sensor out ready."] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable sample signal for wakeup module."] + #[inline(always)] + pub fn sample_en(&self) -> SAMPLE_EN_R { + SAMPLE_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Wake up signal mask."] + #[inline(always)] + pub fn wakeup_mask(&self) -> WAKEUP_MASK_R { + WAKEUP_MASK_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - Enable temperature sensor to send out interrupt."] + #[inline(always)] + pub fn int_en(&self) -> INT_EN_R { + INT_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Invert temperature sensor data."] + #[inline(always)] + pub fn in_inv(&self) -> IN_INV_R { + IN_INV_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:21 - Temperature sensor clock divider."] + #[inline(always)] + pub fn clk_div(&self) -> CLK_DIV_R { + CLK_DIV_R::new(((self.bits >> 14) & 0xff) as u8) + } + #[doc = "Bit 22 - Temperature sensor power up."] + #[inline(always)] + pub fn power_up(&self) -> POWER_UP_R { + POWER_UP_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - 1: dump out & power up controlled by SW, 0: by FSM."] + #[inline(always)] + pub fn power_up_force(&self) -> POWER_UP_FORCE_R { + POWER_UP_FORCE_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTRL") + .field("out", &format_args!("{}", self.out().bits())) + .field("ready", &format_args!("{}", self.ready().bit())) + .field("sample_en", &format_args!("{}", self.sample_en().bit())) + .field("wakeup_mask", &format_args!("{}", self.wakeup_mask().bit())) + .field("int_en", &format_args!("{}", self.int_en().bit())) + .field("in_inv", &format_args!("{}", self.in_inv().bit())) + .field("clk_div", &format_args!("{}", self.clk_div().bits())) + .field("power_up", &format_args!("{}", self.power_up().bit())) + .field( + "power_up_force", + &format_args!("{}", self.power_up_force().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 9 - Enable sample signal for wakeup module."] + #[inline(always)] + #[must_use] + pub fn sample_en(&mut self) -> SAMPLE_EN_W { + SAMPLE_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Wake up signal mask."] + #[inline(always)] + #[must_use] + pub fn wakeup_mask(&mut self) -> WAKEUP_MASK_W { + WAKEUP_MASK_W::new(self, 10) + } + #[doc = "Bit 12 - Enable temperature sensor to send out interrupt."] + #[inline(always)] + #[must_use] + pub fn int_en(&mut self) -> INT_EN_W { + INT_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Invert temperature sensor data."] + #[inline(always)] + #[must_use] + pub fn in_inv(&mut self) -> IN_INV_W { + IN_INV_W::new(self, 13) + } + #[doc = "Bits 14:21 - Temperature sensor clock divider."] + #[inline(always)] + #[must_use] + pub fn clk_div(&mut self) -> CLK_DIV_W { + CLK_DIV_W::new(self, 14) + } + #[doc = "Bit 22 - Temperature sensor power up."] + #[inline(always)] + #[must_use] + pub fn power_up(&mut self) -> POWER_UP_W { + POWER_UP_W::new(self, 22) + } + #[doc = "Bit 23 - 1: dump out & power up controlled by SW, 0: by FSM."] + #[inline(always)] + #[must_use] + pub fn power_up_force(&mut self) -> POWER_UP_FORCE_W { + POWER_UP_FORCE_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tsens configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL to value 0x0001_9400"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_9400; +} diff --git a/esp32p4/src/lp_tsens/ctrl2.rs b/esp32p4/src/lp_tsens/ctrl2.rs new file mode 100644 index 0000000000..4bf0e04987 --- /dev/null +++ b/esp32p4/src/lp_tsens/ctrl2.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `XPD_WAIT` reader - N/A"] +pub type XPD_WAIT_R = crate::FieldReader; +#[doc = "Field `XPD_WAIT` writer - N/A"] +pub type XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `XPD_FORCE` reader - N/A"] +pub type XPD_FORCE_R = crate::FieldReader; +#[doc = "Field `XPD_FORCE` writer - N/A"] +pub type XPD_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CLK_INV` reader - N/A"] +pub type CLK_INV_R = crate::BitReader; +#[doc = "Field `CLK_INV` writer - N/A"] +pub type CLK_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:11 - N/A"] + #[inline(always)] + pub fn xpd_wait(&self) -> XPD_WAIT_R { + XPD_WAIT_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:13 - N/A"] + #[inline(always)] + pub fn xpd_force(&self) -> XPD_FORCE_R { + XPD_FORCE_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bit 14 - N/A"] + #[inline(always)] + pub fn clk_inv(&self) -> CLK_INV_R { + CLK_INV_R::new(((self.bits >> 14) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTRL2") + .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits())) + .field("xpd_force", &format_args!("{}", self.xpd_force().bits())) + .field("clk_inv", &format_args!("{}", self.clk_inv().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - N/A"] + #[inline(always)] + #[must_use] + pub fn xpd_wait(&mut self) -> XPD_WAIT_W { + XPD_WAIT_W::new(self, 0) + } + #[doc = "Bits 12:13 - N/A"] + #[inline(always)] + #[must_use] + pub fn xpd_force(&mut self) -> XPD_FORCE_W { + XPD_FORCE_W::new(self, 12) + } + #[doc = "Bit 14 - N/A"] + #[inline(always)] + #[must_use] + pub fn clk_inv(&mut self) -> CLK_INV_W { + CLK_INV_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tsens configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL2_SPEC; +impl crate::RegisterSpec for CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"] +impl crate::Readable for CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"] +impl crate::Writable for CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL2 to value 0x4002"] +impl crate::Resettable for CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0x4002; +} diff --git a/esp32p4/src/lp_tsens/int_clr.rs b/esp32p4/src/lp_tsens/int_clr.rs new file mode 100644 index 0000000000..44ca4416d3 --- /dev/null +++ b/esp32p4/src/lp_tsens/int_clr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `COCPU_TSENS_WAKE_INT_CLR` writer - Tsens wakeup interrupt clear."] +pub type COCPU_TSENS_WAKE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Tsens wakeup interrupt clear."] + #[inline(always)] + #[must_use] + pub fn cocpu_tsens_wake_int_clr(&mut self) -> COCPU_TSENS_WAKE_INT_CLR_W { + COCPU_TSENS_WAKE_INT_CLR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tsens interrupt clear registers.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_tsens/int_ena.rs b/esp32p4/src/lp_tsens/int_ena.rs new file mode 100644 index 0000000000..3db12d09c7 --- /dev/null +++ b/esp32p4/src/lp_tsens/int_ena.rs @@ -0,0 +1,66 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `COCPU_TSENS_WAKE_INT_ENA` reader - Tsens wakeup interrupt enable."] +pub type COCPU_TSENS_WAKE_INT_ENA_R = crate::BitReader; +#[doc = "Field `COCPU_TSENS_WAKE_INT_ENA` writer - Tsens wakeup interrupt enable."] +pub type COCPU_TSENS_WAKE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Tsens wakeup interrupt enable."] + #[inline(always)] + pub fn cocpu_tsens_wake_int_ena(&self) -> COCPU_TSENS_WAKE_INT_ENA_R { + COCPU_TSENS_WAKE_INT_ENA_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "cocpu_tsens_wake_int_ena", + &format_args!("{}", self.cocpu_tsens_wake_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Tsens wakeup interrupt enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_tsens_wake_int_ena(&mut self) -> COCPU_TSENS_WAKE_INT_ENA_W { + COCPU_TSENS_WAKE_INT_ENA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tsens interrupt enable registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_tsens/int_ena_w1tc.rs b/esp32p4/src/lp_tsens/int_ena_w1tc.rs new file mode 100644 index 0000000000..53bad29bd1 --- /dev/null +++ b/esp32p4/src/lp_tsens/int_ena_w1tc.rs @@ -0,0 +1,44 @@ +#[doc = "Register `INT_ENA_W1TC` writer"] +pub type W = crate::W; +#[doc = "Field `COCPU_TSENS_WAKE_INT_ENA_W1TC` writer - Write 1 to this field to deassert interrupt enable."] +pub type COCPU_TSENS_WAKE_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to this field to deassert interrupt enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_tsens_wake_int_ena_w1tc( + &mut self, + ) -> COCPU_TSENS_WAKE_INT_ENA_W1TC_W { + COCPU_TSENS_WAKE_INT_ENA_W1TC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tsens wakeup interrupt enable deassert.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_W1TC_SPEC; +impl crate::RegisterSpec for INT_ENA_W1TC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_ena_w1tc::W`](W) writer structure"] +impl crate::Writable for INT_ENA_W1TC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA_W1TC to value 0"] +impl crate::Resettable for INT_ENA_W1TC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_tsens/int_ena_w1ts.rs b/esp32p4/src/lp_tsens/int_ena_w1ts.rs new file mode 100644 index 0000000000..c51a67dada --- /dev/null +++ b/esp32p4/src/lp_tsens/int_ena_w1ts.rs @@ -0,0 +1,44 @@ +#[doc = "Register `INT_ENA_W1TS` writer"] +pub type W = crate::W; +#[doc = "Field `COCPU_TSENS_WAKE_INT_ENA_W1TS` writer - Write 1 to this field to assert interrupt enable."] +pub type COCPU_TSENS_WAKE_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to this field to assert interrupt enable."] + #[inline(always)] + #[must_use] + pub fn cocpu_tsens_wake_int_ena_w1ts( + &mut self, + ) -> COCPU_TSENS_WAKE_INT_ENA_W1TS_W { + COCPU_TSENS_WAKE_INT_ENA_W1TS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tsens wakeup interrupt enable assert.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_W1TS_SPEC; +impl crate::RegisterSpec for INT_ENA_W1TS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_ena_w1ts::W`](W) writer structure"] +impl crate::Writable for INT_ENA_W1TS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA_W1TS to value 0"] +impl crate::Resettable for INT_ENA_W1TS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_tsens/int_raw.rs b/esp32p4/src/lp_tsens/int_raw.rs new file mode 100644 index 0000000000..71a6046f41 --- /dev/null +++ b/esp32p4/src/lp_tsens/int_raw.rs @@ -0,0 +1,66 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `COCPU_TSENS_WAKE_INT_RAW` reader - Tsens wakeup interrupt raw."] +pub type COCPU_TSENS_WAKE_INT_RAW_R = crate::BitReader; +#[doc = "Field `COCPU_TSENS_WAKE_INT_RAW` writer - Tsens wakeup interrupt raw."] +pub type COCPU_TSENS_WAKE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Tsens wakeup interrupt raw."] + #[inline(always)] + pub fn cocpu_tsens_wake_int_raw(&self) -> COCPU_TSENS_WAKE_INT_RAW_R { + COCPU_TSENS_WAKE_INT_RAW_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "cocpu_tsens_wake_int_raw", + &format_args!("{}", self.cocpu_tsens_wake_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Tsens wakeup interrupt raw."] + #[inline(always)] + #[must_use] + pub fn cocpu_tsens_wake_int_raw(&mut self) -> COCPU_TSENS_WAKE_INT_RAW_W { + COCPU_TSENS_WAKE_INT_RAW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tsens interrupt raw registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_tsens/int_st.rs b/esp32p4/src/lp_tsens/int_st.rs new file mode 100644 index 0000000000..e51dbc701c --- /dev/null +++ b/esp32p4/src/lp_tsens/int_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `COCPU_TSENS_WAKE_INT_ST` reader - Tsens wakeup interrupt status."] +pub type COCPU_TSENS_WAKE_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Tsens wakeup interrupt status."] + #[inline(always)] + pub fn cocpu_tsens_wake_int_st(&self) -> COCPU_TSENS_WAKE_INT_ST_R { + COCPU_TSENS_WAKE_INT_ST_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "cocpu_tsens_wake_int_st", + &format_args!("{}", self.cocpu_tsens_wake_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Tsens interrupt status registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_tsens/rnd_eco_cs.rs b/esp32p4/src/lp_tsens/rnd_eco_cs.rs new file mode 100644 index 0000000000..50d64f15d3 --- /dev/null +++ b/esp32p4/src/lp_tsens/rnd_eco_cs.rs @@ -0,0 +1,74 @@ +#[doc = "Register `RND_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `RND_ECO_EN` reader - N/A"] +pub type RND_ECO_EN_R = crate::BitReader; +#[doc = "Field `RND_ECO_EN` writer - N/A"] +pub type RND_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RND_ECO_RESULT` reader - N/A"] +pub type RND_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + pub fn rnd_eco_en(&self) -> RND_ECO_EN_R { + RND_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + pub fn rnd_eco_result(&self) -> RND_ECO_RESULT_R { + RND_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_CS") + .field("rnd_eco_en", &format_args!("{}", self.rnd_eco_en().bit())) + .field( + "rnd_eco_result", + &format_args!("{}", self.rnd_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + #[must_use] + pub fn rnd_eco_en(&mut self) -> RND_ECO_EN_W { + RND_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_CS_SPEC; +impl crate::RegisterSpec for RND_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_cs::R`](R) reader structure"] +impl crate::Readable for RND_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_cs::W`](W) writer structure"] +impl crate::Writable for RND_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_CS to value 0"] +impl crate::Resettable for RND_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_tsens/rnd_eco_high.rs b/esp32p4/src/lp_tsens/rnd_eco_high.rs new file mode 100644 index 0000000000..81d831c24f --- /dev/null +++ b/esp32p4/src/lp_tsens/rnd_eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RND_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `RND_ECO_HIGH` reader - N/A"] +pub type RND_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `RND_ECO_HIGH` writer - N/A"] +pub type RND_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + pub fn rnd_eco_high(&self) -> RND_ECO_HIGH_R { + RND_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_HIGH") + .field( + "rnd_eco_high", + &format_args!("{}", self.rnd_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + #[must_use] + pub fn rnd_eco_high(&mut self) -> RND_ECO_HIGH_W { + RND_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_HIGH_SPEC; +impl crate::RegisterSpec for RND_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_high::R`](R) reader structure"] +impl crate::Readable for RND_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_high::W`](W) writer structure"] +impl crate::Writable for RND_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for RND_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/lp_tsens/rnd_eco_low.rs b/esp32p4/src/lp_tsens/rnd_eco_low.rs new file mode 100644 index 0000000000..8d51754156 --- /dev/null +++ b/esp32p4/src/lp_tsens/rnd_eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RND_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `RND_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `RND_ECO_LOW` reader - N/A"] +pub type RND_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `RND_ECO_LOW` writer - N/A"] +pub type RND_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + pub fn rnd_eco_low(&self) -> RND_ECO_LOW_R { + RND_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RND_ECO_LOW") + .field( + "rnd_eco_low", + &format_args!("{}", self.rnd_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + #[must_use] + pub fn rnd_eco_low(&mut self) -> RND_ECO_LOW_W { + RND_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_ECO_LOW_SPEC; +impl crate::RegisterSpec for RND_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_eco_low::R`](R) reader structure"] +impl crate::Readable for RND_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_eco_low::W`](W) writer structure"] +impl crate::Writable for RND_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RND_ECO_LOW to value 0"] +impl crate::Resettable for RND_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_tsens/sample_rate.rs b/esp32p4/src/lp_tsens/sample_rate.rs new file mode 100644 index 0000000000..1b9c6acd58 --- /dev/null +++ b/esp32p4/src/lp_tsens/sample_rate.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SAMPLE_RATE` reader"] +pub type R = crate::R; +#[doc = "Register `SAMPLE_RATE` writer"] +pub type W = crate::W; +#[doc = "Field `SAMPLE_RATE` reader - Hardware automatic sampling rate."] +pub type SAMPLE_RATE_R = crate::FieldReader; +#[doc = "Field `SAMPLE_RATE` writer - Hardware automatic sampling rate."] +pub type SAMPLE_RATE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Hardware automatic sampling rate."] + #[inline(always)] + pub fn sample_rate(&self) -> SAMPLE_RATE_R { + SAMPLE_RATE_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SAMPLE_RATE") + .field( + "sample_rate", + &format_args!("{}", self.sample_rate().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Hardware automatic sampling rate."] + #[inline(always)] + #[must_use] + pub fn sample_rate(&mut self) -> SAMPLE_RATE_W { + SAMPLE_RATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Hardware automatic sampling control registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_rate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_rate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAMPLE_RATE_SPEC; +impl crate::RegisterSpec for SAMPLE_RATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sample_rate::R`](R) reader structure"] +impl crate::Readable for SAMPLE_RATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sample_rate::W`](W) writer structure"] +impl crate::Writable for SAMPLE_RATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAMPLE_RATE to value 0x14"] +impl crate::Resettable for SAMPLE_RATE_SPEC { + const RESET_VALUE: Self::Ux = 0x14; +} diff --git a/esp32p4/src/lp_tsens/wakeup_ctrl.rs b/esp32p4/src/lp_tsens/wakeup_ctrl.rs new file mode 100644 index 0000000000..408b4ea701 --- /dev/null +++ b/esp32p4/src/lp_tsens/wakeup_ctrl.rs @@ -0,0 +1,128 @@ +#[doc = "Register `WAKEUP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `WAKEUP_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `WAKEUP_TH_LOW` reader - Lower threshold."] +pub type WAKEUP_TH_LOW_R = crate::FieldReader; +#[doc = "Field `WAKEUP_TH_LOW` writer - Lower threshold."] +pub type WAKEUP_TH_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WAKEUP_TH_HIGH` reader - Upper threshold."] +pub type WAKEUP_TH_HIGH_R = crate::FieldReader; +#[doc = "Field `WAKEUP_TH_HIGH` writer - Upper threshold."] +pub type WAKEUP_TH_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WAKEUP_OVER_UPPER_TH` reader - Indicates that this wakeup event arose from exceeding upper threshold."] +pub type WAKEUP_OVER_UPPER_TH_R = crate::BitReader; +#[doc = "Field `WAKEUP_EN` reader - Tsens wakeup enable."] +pub type WAKEUP_EN_R = crate::BitReader; +#[doc = "Field `WAKEUP_EN` writer - Tsens wakeup enable."] +pub type WAKEUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAKEUP_MODE` reader - 0:absolute value comparison mode. 1: relative value comparison mode."] +pub type WAKEUP_MODE_R = crate::BitReader; +#[doc = "Field `WAKEUP_MODE` writer - 0:absolute value comparison mode. 1: relative value comparison mode."] +pub type WAKEUP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Lower threshold."] + #[inline(always)] + pub fn wakeup_th_low(&self) -> WAKEUP_TH_LOW_R { + WAKEUP_TH_LOW_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 14:21 - Upper threshold."] + #[inline(always)] + pub fn wakeup_th_high(&self) -> WAKEUP_TH_HIGH_R { + WAKEUP_TH_HIGH_R::new(((self.bits >> 14) & 0xff) as u8) + } + #[doc = "Bit 29 - Indicates that this wakeup event arose from exceeding upper threshold."] + #[inline(always)] + pub fn wakeup_over_upper_th(&self) -> WAKEUP_OVER_UPPER_TH_R { + WAKEUP_OVER_UPPER_TH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Tsens wakeup enable."] + #[inline(always)] + pub fn wakeup_en(&self) -> WAKEUP_EN_R { + WAKEUP_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 0:absolute value comparison mode. 1: relative value comparison mode."] + #[inline(always)] + pub fn wakeup_mode(&self) -> WAKEUP_MODE_R { + WAKEUP_MODE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WAKEUP_CTRL") + .field( + "wakeup_th_low", + &format_args!("{}", self.wakeup_th_low().bits()), + ) + .field( + "wakeup_th_high", + &format_args!("{}", self.wakeup_th_high().bits()), + ) + .field( + "wakeup_over_upper_th", + &format_args!("{}", self.wakeup_over_upper_th().bit()), + ) + .field("wakeup_en", &format_args!("{}", self.wakeup_en().bit())) + .field("wakeup_mode", &format_args!("{}", self.wakeup_mode().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Lower threshold."] + #[inline(always)] + #[must_use] + pub fn wakeup_th_low(&mut self) -> WAKEUP_TH_LOW_W { + WAKEUP_TH_LOW_W::new(self, 0) + } + #[doc = "Bits 14:21 - Upper threshold."] + #[inline(always)] + #[must_use] + pub fn wakeup_th_high(&mut self) -> WAKEUP_TH_HIGH_W { + WAKEUP_TH_HIGH_W::new(self, 14) + } + #[doc = "Bit 30 - Tsens wakeup enable."] + #[inline(always)] + #[must_use] + pub fn wakeup_en(&mut self) -> WAKEUP_EN_W { + WAKEUP_EN_W::new(self, 30) + } + #[doc = "Bit 31 - 0:absolute value comparison mode. 1: relative value comparison mode."] + #[inline(always)] + #[must_use] + pub fn wakeup_mode(&mut self) -> WAKEUP_MODE_W { + WAKEUP_MODE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tsens wakeup control registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WAKEUP_CTRL_SPEC; +impl crate::RegisterSpec for WAKEUP_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wakeup_ctrl::R`](R) reader structure"] +impl crate::Readable for WAKEUP_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wakeup_ctrl::W`](W) writer structure"] +impl crate::Writable for WAKEUP_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WAKEUP_CTRL to value 0x003f_c000"] +impl crate::Resettable for WAKEUP_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x003f_c000; +} diff --git a/esp32p4/src/lp_uart.rs b/esp32p4/src/lp_uart.rs new file mode 100644 index 0000000000..cb22b1e6d6 --- /dev/null +++ b/esp32p4/src/lp_uart.rs @@ -0,0 +1,340 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + fifo: FIFO, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + clkdiv_sync: CLKDIV_SYNC, + rx_filt: RX_FILT, + status: STATUS, + conf0_sync: CONF0_SYNC, + conf1: CONF1, + _reserved10: [u8; 0x04], + hwfc_conf_sync: HWFC_CONF_SYNC, + sleep_conf0: SLEEP_CONF0, + sleep_conf1: SLEEP_CONF1, + sleep_conf2: SLEEP_CONF2, + swfc_conf0_sync: SWFC_CONF0_SYNC, + swfc_conf1: SWFC_CONF1, + txbrk_conf_sync: TXBRK_CONF_SYNC, + idle_conf_sync: IDLE_CONF_SYNC, + rs485_conf_sync: RS485_CONF_SYNC, + at_cmd_precnt_sync: AT_CMD_PRECNT_SYNC, + at_cmd_postcnt_sync: AT_CMD_POSTCNT_SYNC, + at_cmd_gaptout_sync: AT_CMD_GAPTOUT_SYNC, + at_cmd_char_sync: AT_CMD_CHAR_SYNC, + mem_conf: MEM_CONF, + tout_conf_sync: TOUT_CONF_SYNC, + mem_tx_status: MEM_TX_STATUS, + mem_rx_status: MEM_RX_STATUS, + fsm_status: FSM_STATUS, + _reserved28: [u8; 0x14], + clk_conf: CLK_CONF, + date: DATE, + afifo_status: AFIFO_STATUS, + _reserved31: [u8; 0x04], + reg_update: REG_UPDATE, + id: ID, +} +impl RegisterBlock { + #[doc = "0x00 - FIFO data register"] + #[inline(always)] + pub const fn fifo(&self) -> &FIFO { + &self.fifo + } + #[doc = "0x04 - Raw interrupt status"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x08 - Masked interrupt status"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x0c - Interrupt enable bits"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x10 - Interrupt clear bits"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x14 - Clock divider configuration"] + #[inline(always)] + pub const fn clkdiv_sync(&self) -> &CLKDIV_SYNC { + &self.clkdiv_sync + } + #[doc = "0x18 - Rx Filter configuration"] + #[inline(always)] + pub const fn rx_filt(&self) -> &RX_FILT { + &self.rx_filt + } + #[doc = "0x1c - UART status register"] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0x20 - Configuration register 0"] + #[inline(always)] + pub const fn conf0_sync(&self) -> &CONF0_SYNC { + &self.conf0_sync + } + #[doc = "0x24 - Configuration register 1"] + #[inline(always)] + pub const fn conf1(&self) -> &CONF1 { + &self.conf1 + } + #[doc = "0x2c - Hardware flow-control configuration"] + #[inline(always)] + pub const fn hwfc_conf_sync(&self) -> &HWFC_CONF_SYNC { + &self.hwfc_conf_sync + } + #[doc = "0x30 - UART sleep configure register 0"] + #[inline(always)] + pub const fn sleep_conf0(&self) -> &SLEEP_CONF0 { + &self.sleep_conf0 + } + #[doc = "0x34 - UART sleep configure register 1"] + #[inline(always)] + pub const fn sleep_conf1(&self) -> &SLEEP_CONF1 { + &self.sleep_conf1 + } + #[doc = "0x38 - UART sleep configure register 2"] + #[inline(always)] + pub const fn sleep_conf2(&self) -> &SLEEP_CONF2 { + &self.sleep_conf2 + } + #[doc = "0x3c - Software flow-control character configuration"] + #[inline(always)] + pub const fn swfc_conf0_sync(&self) -> &SWFC_CONF0_SYNC { + &self.swfc_conf0_sync + } + #[doc = "0x40 - Software flow-control character configuration"] + #[inline(always)] + pub const fn swfc_conf1(&self) -> &SWFC_CONF1 { + &self.swfc_conf1 + } + #[doc = "0x44 - Tx Break character configuration"] + #[inline(always)] + pub const fn txbrk_conf_sync(&self) -> &TXBRK_CONF_SYNC { + &self.txbrk_conf_sync + } + #[doc = "0x48 - Frame-end idle configuration"] + #[inline(always)] + pub const fn idle_conf_sync(&self) -> &IDLE_CONF_SYNC { + &self.idle_conf_sync + } + #[doc = "0x4c - RS485 mode configuration"] + #[inline(always)] + pub const fn rs485_conf_sync(&self) -> &RS485_CONF_SYNC { + &self.rs485_conf_sync + } + #[doc = "0x50 - Pre-sequence timing configuration"] + #[inline(always)] + pub const fn at_cmd_precnt_sync(&self) -> &AT_CMD_PRECNT_SYNC { + &self.at_cmd_precnt_sync + } + #[doc = "0x54 - Post-sequence timing configuration"] + #[inline(always)] + pub const fn at_cmd_postcnt_sync(&self) -> &AT_CMD_POSTCNT_SYNC { + &self.at_cmd_postcnt_sync + } + #[doc = "0x58 - Timeout configuration"] + #[inline(always)] + pub const fn at_cmd_gaptout_sync(&self) -> &AT_CMD_GAPTOUT_SYNC { + &self.at_cmd_gaptout_sync + } + #[doc = "0x5c - AT escape sequence detection configuration"] + #[inline(always)] + pub const fn at_cmd_char_sync(&self) -> &AT_CMD_CHAR_SYNC { + &self.at_cmd_char_sync + } + #[doc = "0x60 - UART memory power configuration"] + #[inline(always)] + pub const fn mem_conf(&self) -> &MEM_CONF { + &self.mem_conf + } + #[doc = "0x64 - UART threshold and allocation configuration"] + #[inline(always)] + pub const fn tout_conf_sync(&self) -> &TOUT_CONF_SYNC { + &self.tout_conf_sync + } + #[doc = "0x68 - Tx-SRAM write and read offset address."] + #[inline(always)] + pub const fn mem_tx_status(&self) -> &MEM_TX_STATUS { + &self.mem_tx_status + } + #[doc = "0x6c - Rx-SRAM write and read offset address."] + #[inline(always)] + pub const fn mem_rx_status(&self) -> &MEM_RX_STATUS { + &self.mem_rx_status + } + #[doc = "0x70 - UART transmit and receive status."] + #[inline(always)] + pub const fn fsm_status(&self) -> &FSM_STATUS { + &self.fsm_status + } + #[doc = "0x88 - UART core clock configuration"] + #[inline(always)] + pub const fn clk_conf(&self) -> &CLK_CONF { + &self.clk_conf + } + #[doc = "0x8c - UART Version register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } + #[doc = "0x90 - UART AFIFO Status"] + #[inline(always)] + pub const fn afifo_status(&self) -> &AFIFO_STATUS { + &self.afifo_status + } + #[doc = "0x98 - UART Registers Configuration Update register"] + #[inline(always)] + pub const fn reg_update(&self) -> ®_UPDATE { + &self.reg_update + } + #[doc = "0x9c - UART ID register"] + #[inline(always)] + pub const fn id(&self) -> &ID { + &self.id + } +} +#[doc = "FIFO (r) register accessor: FIFO data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] module"] +pub type FIFO = crate::Reg; +#[doc = "FIFO data register"] +pub mod fifo; +#[doc = "INT_RAW (rw) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Raw interrupt status"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Masked interrupt status"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable bits"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear bits"] +pub mod int_clr; +#[doc = "CLKDIV_SYNC (rw) register accessor: Clock divider configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv_sync`] module"] +pub type CLKDIV_SYNC = crate::Reg; +#[doc = "Clock divider configuration"] +pub mod clkdiv_sync; +#[doc = "RX_FILT (rw) register accessor: Rx Filter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_filt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_filt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_filt`] module"] +pub type RX_FILT = crate::Reg; +#[doc = "Rx Filter configuration"] +pub mod rx_filt; +#[doc = "STATUS (r) register accessor: UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +pub type STATUS = crate::Reg; +#[doc = "UART status register"] +pub mod status; +#[doc = "CONF0_SYNC (rw) register accessor: Configuration register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf0_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf0_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf0_sync`] module"] +pub type CONF0_SYNC = crate::Reg; +#[doc = "Configuration register 0"] +pub mod conf0_sync; +#[doc = "CONF1 (rw) register accessor: Configuration register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf1`] module"] +pub type CONF1 = crate::Reg; +#[doc = "Configuration register 1"] +pub mod conf1; +#[doc = "HWFC_CONF_SYNC (rw) register accessor: Hardware flow-control configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwfc_conf_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwfc_conf_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwfc_conf_sync`] module"] +pub type HWFC_CONF_SYNC = crate::Reg; +#[doc = "Hardware flow-control configuration"] +pub mod hwfc_conf_sync; +#[doc = "SLEEP_CONF0 (rw) register accessor: UART sleep configure register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf0`] module"] +pub type SLEEP_CONF0 = crate::Reg; +#[doc = "UART sleep configure register 0"] +pub mod sleep_conf0; +#[doc = "SLEEP_CONF1 (rw) register accessor: UART sleep configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf1`] module"] +pub type SLEEP_CONF1 = crate::Reg; +#[doc = "UART sleep configure register 1"] +pub mod sleep_conf1; +#[doc = "SLEEP_CONF2 (rw) register accessor: UART sleep configure register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf2`] module"] +pub type SLEEP_CONF2 = crate::Reg; +#[doc = "UART sleep configure register 2"] +pub mod sleep_conf2; +#[doc = "SWFC_CONF0_SYNC (rw) register accessor: Software flow-control character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swfc_conf0_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swfc_conf0_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swfc_conf0_sync`] module"] +pub type SWFC_CONF0_SYNC = crate::Reg; +#[doc = "Software flow-control character configuration"] +pub mod swfc_conf0_sync; +#[doc = "SWFC_CONF1 (rw) register accessor: Software flow-control character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swfc_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swfc_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swfc_conf1`] module"] +pub type SWFC_CONF1 = crate::Reg; +#[doc = "Software flow-control character configuration"] +pub mod swfc_conf1; +#[doc = "TXBRK_CONF_SYNC (rw) register accessor: Tx Break character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbrk_conf_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbrk_conf_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbrk_conf_sync`] module"] +pub type TXBRK_CONF_SYNC = crate::Reg; +#[doc = "Tx Break character configuration"] +pub mod txbrk_conf_sync; +#[doc = "IDLE_CONF_SYNC (rw) register accessor: Frame-end idle configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle_conf_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idle_conf_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idle_conf_sync`] module"] +pub type IDLE_CONF_SYNC = crate::Reg; +#[doc = "Frame-end idle configuration"] +pub mod idle_conf_sync; +#[doc = "RS485_CONF_SYNC (rw) register accessor: RS485 mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rs485_conf_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rs485_conf_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rs485_conf_sync`] module"] +pub type RS485_CONF_SYNC = crate::Reg; +#[doc = "RS485 mode configuration"] +pub mod rs485_conf_sync; +#[doc = "AT_CMD_PRECNT_SYNC (rw) register accessor: Pre-sequence timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_precnt_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_precnt_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_precnt_sync`] module"] +pub type AT_CMD_PRECNT_SYNC = crate::Reg; +#[doc = "Pre-sequence timing configuration"] +pub mod at_cmd_precnt_sync; +#[doc = "AT_CMD_POSTCNT_SYNC (rw) register accessor: Post-sequence timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_postcnt_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_postcnt_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_postcnt_sync`] module"] +pub type AT_CMD_POSTCNT_SYNC = crate::Reg; +#[doc = "Post-sequence timing configuration"] +pub mod at_cmd_postcnt_sync; +#[doc = "AT_CMD_GAPTOUT_SYNC (rw) register accessor: Timeout configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_gaptout_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_gaptout_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_gaptout_sync`] module"] +pub type AT_CMD_GAPTOUT_SYNC = crate::Reg; +#[doc = "Timeout configuration"] +pub mod at_cmd_gaptout_sync; +#[doc = "AT_CMD_CHAR_SYNC (rw) register accessor: AT escape sequence detection configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_char_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_char_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_char_sync`] module"] +pub type AT_CMD_CHAR_SYNC = crate::Reg; +#[doc = "AT escape sequence detection configuration"] +pub mod at_cmd_char_sync; +#[doc = "MEM_CONF (rw) register accessor: UART memory power configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_conf`] module"] +pub type MEM_CONF = crate::Reg; +#[doc = "UART memory power configuration"] +pub mod mem_conf; +#[doc = "TOUT_CONF_SYNC (rw) register accessor: UART threshold and allocation configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tout_conf_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tout_conf_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tout_conf_sync`] module"] +pub type TOUT_CONF_SYNC = crate::Reg; +#[doc = "UART threshold and allocation configuration"] +pub mod tout_conf_sync; +#[doc = "MEM_TX_STATUS (r) register accessor: Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_tx_status`] module"] +pub type MEM_TX_STATUS = crate::Reg; +#[doc = "Tx-SRAM write and read offset address."] +pub mod mem_tx_status; +#[doc = "MEM_RX_STATUS (r) register accessor: Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_rx_status`] module"] +pub type MEM_RX_STATUS = crate::Reg; +#[doc = "Rx-SRAM write and read offset address."] +pub mod mem_rx_status; +#[doc = "FSM_STATUS (r) register accessor: UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsm_status`] module"] +pub type FSM_STATUS = crate::Reg; +#[doc = "UART transmit and receive status."] +pub mod fsm_status; +#[doc = "CLK_CONF (rw) register accessor: UART core clock configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"] +pub type CLK_CONF = crate::Reg; +#[doc = "UART core clock configuration"] +pub mod clk_conf; +#[doc = "DATE (rw) register accessor: UART Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "UART Version register"] +pub mod date; +#[doc = "AFIFO_STATUS (r) register accessor: UART AFIFO Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`afifo_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@afifo_status`] module"] +pub type AFIFO_STATUS = crate::Reg; +#[doc = "UART AFIFO Status"] +pub mod afifo_status; +#[doc = "REG_UPDATE (rw) register accessor: UART Registers Configuration Update register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_update::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_update::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_update`] module"] +pub type REG_UPDATE = crate::Reg; +#[doc = "UART Registers Configuration Update register"] +pub mod reg_update; +#[doc = "ID (rw) register accessor: UART ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`] module"] +pub type ID = crate::Reg; +#[doc = "UART ID register"] +pub mod id; diff --git a/esp32p4/src/lp_uart/afifo_status.rs b/esp32p4/src/lp_uart/afifo_status.rs new file mode 100644 index 0000000000..fe85b494e8 --- /dev/null +++ b/esp32p4/src/lp_uart/afifo_status.rs @@ -0,0 +1,72 @@ +#[doc = "Register `AFIFO_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `TX_AFIFO_FULL` reader - Full signal of APB TX AFIFO."] +pub type TX_AFIFO_FULL_R = crate::BitReader; +#[doc = "Field `TX_AFIFO_EMPTY` reader - Empty signal of APB TX AFIFO."] +pub type TX_AFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `RX_AFIFO_FULL` reader - Full signal of APB RX AFIFO."] +pub type RX_AFIFO_FULL_R = crate::BitReader; +#[doc = "Field `RX_AFIFO_EMPTY` reader - Empty signal of APB RX AFIFO."] +pub type RX_AFIFO_EMPTY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Full signal of APB TX AFIFO."] + #[inline(always)] + pub fn tx_afifo_full(&self) -> TX_AFIFO_FULL_R { + TX_AFIFO_FULL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Empty signal of APB TX AFIFO."] + #[inline(always)] + pub fn tx_afifo_empty(&self) -> TX_AFIFO_EMPTY_R { + TX_AFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Full signal of APB RX AFIFO."] + #[inline(always)] + pub fn rx_afifo_full(&self) -> RX_AFIFO_FULL_R { + RX_AFIFO_FULL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Empty signal of APB RX AFIFO."] + #[inline(always)] + pub fn rx_afifo_empty(&self) -> RX_AFIFO_EMPTY_R { + RX_AFIFO_EMPTY_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AFIFO_STATUS") + .field( + "tx_afifo_full", + &format_args!("{}", self.tx_afifo_full().bit()), + ) + .field( + "tx_afifo_empty", + &format_args!("{}", self.tx_afifo_empty().bit()), + ) + .field( + "rx_afifo_full", + &format_args!("{}", self.rx_afifo_full().bit()), + ) + .field( + "rx_afifo_empty", + &format_args!("{}", self.rx_afifo_empty().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "UART AFIFO Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`afifo_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AFIFO_STATUS_SPEC; +impl crate::RegisterSpec for AFIFO_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`afifo_status::R`](R) reader structure"] +impl crate::Readable for AFIFO_STATUS_SPEC {} +#[doc = "`reset()` method sets AFIFO_STATUS to value 0x0a"] +impl crate::Resettable for AFIFO_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x0a; +} diff --git a/esp32p4/src/lp_uart/at_cmd_char_sync.rs b/esp32p4/src/lp_uart/at_cmd_char_sync.rs new file mode 100644 index 0000000000..cd1d506e27 --- /dev/null +++ b/esp32p4/src/lp_uart/at_cmd_char_sync.rs @@ -0,0 +1,82 @@ +#[doc = "Register `AT_CMD_CHAR_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `AT_CMD_CHAR_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `AT_CMD_CHAR` reader - This register is used to configure the content of at_cmd char."] +pub type AT_CMD_CHAR_R = crate::FieldReader; +#[doc = "Field `AT_CMD_CHAR` writer - This register is used to configure the content of at_cmd char."] +pub type AT_CMD_CHAR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CHAR_NUM` reader - This register is used to configure the num of continuous at_cmd chars received by receiver."] +pub type CHAR_NUM_R = crate::FieldReader; +#[doc = "Field `CHAR_NUM` writer - This register is used to configure the num of continuous at_cmd chars received by receiver."] +pub type CHAR_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."] + #[inline(always)] + pub fn at_cmd_char(&self) -> AT_CMD_CHAR_R { + AT_CMD_CHAR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - This register is used to configure the num of continuous at_cmd chars received by receiver."] + #[inline(always)] + pub fn char_num(&self) -> CHAR_NUM_R { + CHAR_NUM_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AT_CMD_CHAR_SYNC") + .field( + "at_cmd_char", + &format_args!("{}", self.at_cmd_char().bits()), + ) + .field("char_num", &format_args!("{}", self.char_num().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."] + #[inline(always)] + #[must_use] + pub fn at_cmd_char(&mut self) -> AT_CMD_CHAR_W { + AT_CMD_CHAR_W::new(self, 0) + } + #[doc = "Bits 8:15 - This register is used to configure the num of continuous at_cmd chars received by receiver."] + #[inline(always)] + #[must_use] + pub fn char_num(&mut self) -> CHAR_NUM_W { + CHAR_NUM_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AT escape sequence detection configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_char_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_char_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AT_CMD_CHAR_SYNC_SPEC; +impl crate::RegisterSpec for AT_CMD_CHAR_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`at_cmd_char_sync::R`](R) reader structure"] +impl crate::Readable for AT_CMD_CHAR_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`at_cmd_char_sync::W`](W) writer structure"] +impl crate::Writable for AT_CMD_CHAR_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AT_CMD_CHAR_SYNC to value 0x032b"] +impl crate::Resettable for AT_CMD_CHAR_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x032b; +} diff --git a/esp32p4/src/lp_uart/at_cmd_gaptout_sync.rs b/esp32p4/src/lp_uart/at_cmd_gaptout_sync.rs new file mode 100644 index 0000000000..6bc46424d1 --- /dev/null +++ b/esp32p4/src/lp_uart/at_cmd_gaptout_sync.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AT_CMD_GAPTOUT_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `AT_CMD_GAPTOUT_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `RX_GAP_TOUT` reader - This register is used to configure the duration time between the at_cmd chars."] +pub type RX_GAP_TOUT_R = crate::FieldReader; +#[doc = "Field `RX_GAP_TOUT` writer - This register is used to configure the duration time between the at_cmd chars."] +pub type RX_GAP_TOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."] + #[inline(always)] + pub fn rx_gap_tout(&self) -> RX_GAP_TOUT_R { + RX_GAP_TOUT_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AT_CMD_GAPTOUT_SYNC") + .field( + "rx_gap_tout", + &format_args!("{}", self.rx_gap_tout().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."] + #[inline(always)] + #[must_use] + pub fn rx_gap_tout(&mut self) -> RX_GAP_TOUT_W { + RX_GAP_TOUT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timeout configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_gaptout_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_gaptout_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AT_CMD_GAPTOUT_SYNC_SPEC; +impl crate::RegisterSpec for AT_CMD_GAPTOUT_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`at_cmd_gaptout_sync::R`](R) reader structure"] +impl crate::Readable for AT_CMD_GAPTOUT_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`at_cmd_gaptout_sync::W`](W) writer structure"] +impl crate::Writable for AT_CMD_GAPTOUT_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AT_CMD_GAPTOUT_SYNC to value 0x0b"] +impl crate::Resettable for AT_CMD_GAPTOUT_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x0b; +} diff --git a/esp32p4/src/lp_uart/at_cmd_postcnt_sync.rs b/esp32p4/src/lp_uart/at_cmd_postcnt_sync.rs new file mode 100644 index 0000000000..37b284b295 --- /dev/null +++ b/esp32p4/src/lp_uart/at_cmd_postcnt_sync.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AT_CMD_POSTCNT_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `AT_CMD_POSTCNT_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `POST_IDLE_NUM` reader - This register is used to configure the duration time between the last at_cmd and the next data."] +pub type POST_IDLE_NUM_R = crate::FieldReader; +#[doc = "Field `POST_IDLE_NUM` writer - This register is used to configure the duration time between the last at_cmd and the next data."] +pub type POST_IDLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."] + #[inline(always)] + pub fn post_idle_num(&self) -> POST_IDLE_NUM_R { + POST_IDLE_NUM_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AT_CMD_POSTCNT_SYNC") + .field( + "post_idle_num", + &format_args!("{}", self.post_idle_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."] + #[inline(always)] + #[must_use] + pub fn post_idle_num(&mut self) -> POST_IDLE_NUM_W { + POST_IDLE_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Post-sequence timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_postcnt_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_postcnt_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AT_CMD_POSTCNT_SYNC_SPEC; +impl crate::RegisterSpec for AT_CMD_POSTCNT_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`at_cmd_postcnt_sync::R`](R) reader structure"] +impl crate::Readable for AT_CMD_POSTCNT_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`at_cmd_postcnt_sync::W`](W) writer structure"] +impl crate::Writable for AT_CMD_POSTCNT_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AT_CMD_POSTCNT_SYNC to value 0x0901"] +impl crate::Resettable for AT_CMD_POSTCNT_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x0901; +} diff --git a/esp32p4/src/lp_uart/at_cmd_precnt_sync.rs b/esp32p4/src/lp_uart/at_cmd_precnt_sync.rs new file mode 100644 index 0000000000..847e9c7053 --- /dev/null +++ b/esp32p4/src/lp_uart/at_cmd_precnt_sync.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AT_CMD_PRECNT_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `AT_CMD_PRECNT_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `PRE_IDLE_NUM` reader - This register is used to configure the idle duration time before the first at_cmd is received by receiver."] +pub type PRE_IDLE_NUM_R = crate::FieldReader; +#[doc = "Field `PRE_IDLE_NUM` writer - This register is used to configure the idle duration time before the first at_cmd is received by receiver."] +pub type PRE_IDLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."] + #[inline(always)] + pub fn pre_idle_num(&self) -> PRE_IDLE_NUM_R { + PRE_IDLE_NUM_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AT_CMD_PRECNT_SYNC") + .field( + "pre_idle_num", + &format_args!("{}", self.pre_idle_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."] + #[inline(always)] + #[must_use] + pub fn pre_idle_num(&mut self) -> PRE_IDLE_NUM_W { + PRE_IDLE_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Pre-sequence timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_precnt_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_precnt_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AT_CMD_PRECNT_SYNC_SPEC; +impl crate::RegisterSpec for AT_CMD_PRECNT_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`at_cmd_precnt_sync::R`](R) reader structure"] +impl crate::Readable for AT_CMD_PRECNT_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`at_cmd_precnt_sync::W`](W) writer structure"] +impl crate::Writable for AT_CMD_PRECNT_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AT_CMD_PRECNT_SYNC to value 0x0901"] +impl crate::Resettable for AT_CMD_PRECNT_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x0901; +} diff --git a/esp32p4/src/lp_uart/clk_conf.rs b/esp32p4/src/lp_uart/clk_conf.rs new file mode 100644 index 0000000000..414dc359bf --- /dev/null +++ b/esp32p4/src/lp_uart/clk_conf.rs @@ -0,0 +1,111 @@ +#[doc = "Register `CLK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `TX_SCLK_EN` reader - Set this bit to enable UART Tx clock."] +pub type TX_SCLK_EN_R = crate::BitReader; +#[doc = "Field `TX_SCLK_EN` writer - Set this bit to enable UART Tx clock."] +pub type TX_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_SCLK_EN` reader - Set this bit to enable UART Rx clock."] +pub type RX_SCLK_EN_R = crate::BitReader; +#[doc = "Field `RX_SCLK_EN` writer - Set this bit to enable UART Rx clock."] +pub type RX_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_RST_CORE` reader - Write 1 then write 0 to this bit to reset UART Tx."] +pub type TX_RST_CORE_R = crate::BitReader; +#[doc = "Field `TX_RST_CORE` writer - Write 1 then write 0 to this bit to reset UART Tx."] +pub type TX_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_RST_CORE` reader - Write 1 then write 0 to this bit to reset UART Rx."] +pub type RX_RST_CORE_R = crate::BitReader; +#[doc = "Field `RX_RST_CORE` writer - Write 1 then write 0 to this bit to reset UART Rx."] +pub type RX_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 24 - Set this bit to enable UART Tx clock."] + #[inline(always)] + pub fn tx_sclk_en(&self) -> TX_SCLK_EN_R { + TX_SCLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Set this bit to enable UART Rx clock."] + #[inline(always)] + pub fn rx_sclk_en(&self) -> RX_SCLK_EN_R { + RX_SCLK_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Write 1 then write 0 to this bit to reset UART Tx."] + #[inline(always)] + pub fn tx_rst_core(&self) -> TX_RST_CORE_R { + TX_RST_CORE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Write 1 then write 0 to this bit to reset UART Rx."] + #[inline(always)] + pub fn rx_rst_core(&self) -> RX_RST_CORE_R { + RX_RST_CORE_R::new(((self.bits >> 27) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_CONF") + .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit())) + .field("rx_sclk_en", &format_args!("{}", self.rx_sclk_en().bit())) + .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit())) + .field("rx_rst_core", &format_args!("{}", self.rx_rst_core().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 24 - Set this bit to enable UART Tx clock."] + #[inline(always)] + #[must_use] + pub fn tx_sclk_en(&mut self) -> TX_SCLK_EN_W { + TX_SCLK_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Set this bit to enable UART Rx clock."] + #[inline(always)] + #[must_use] + pub fn rx_sclk_en(&mut self) -> RX_SCLK_EN_W { + RX_SCLK_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Write 1 then write 0 to this bit to reset UART Tx."] + #[inline(always)] + #[must_use] + pub fn tx_rst_core(&mut self) -> TX_RST_CORE_W { + TX_RST_CORE_W::new(self, 26) + } + #[doc = "Bit 27 - Write 1 then write 0 to this bit to reset UART Rx."] + #[inline(always)] + #[must_use] + pub fn rx_rst_core(&mut self) -> RX_RST_CORE_W { + RX_RST_CORE_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART core clock configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_CONF_SPEC; +impl crate::RegisterSpec for CLK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"] +impl crate::Readable for CLK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"] +impl crate::Writable for CLK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_CONF to value 0x0300_0000"] +impl crate::Resettable for CLK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0300_0000; +} diff --git a/esp32p4/src/lp_uart/clkdiv_sync.rs b/esp32p4/src/lp_uart/clkdiv_sync.rs new file mode 100644 index 0000000000..54ea1b108b --- /dev/null +++ b/esp32p4/src/lp_uart/clkdiv_sync.rs @@ -0,0 +1,82 @@ +#[doc = "Register `CLKDIV_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `CLKDIV` reader - The integral part of the frequency divider factor."] +pub type CLKDIV_R = crate::FieldReader; +#[doc = "Field `CLKDIV` writer - The integral part of the frequency divider factor."] +pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `CLKDIV_FRAG` reader - The decimal part of the frequency divider factor."] +pub type CLKDIV_FRAG_R = crate::FieldReader; +#[doc = "Field `CLKDIV_FRAG` writer - The decimal part of the frequency divider factor."] +pub type CLKDIV_FRAG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:11 - The integral part of the frequency divider factor."] + #[inline(always)] + pub fn clkdiv(&self) -> CLKDIV_R { + CLKDIV_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 20:23 - The decimal part of the frequency divider factor."] + #[inline(always)] + pub fn clkdiv_frag(&self) -> CLKDIV_FRAG_R { + CLKDIV_FRAG_R::new(((self.bits >> 20) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLKDIV_SYNC") + .field("clkdiv", &format_args!("{}", self.clkdiv().bits())) + .field( + "clkdiv_frag", + &format_args!("{}", self.clkdiv_frag().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - The integral part of the frequency divider factor."] + #[inline(always)] + #[must_use] + pub fn clkdiv(&mut self) -> CLKDIV_W { + CLKDIV_W::new(self, 0) + } + #[doc = "Bits 20:23 - The decimal part of the frequency divider factor."] + #[inline(always)] + #[must_use] + pub fn clkdiv_frag(&mut self) -> CLKDIV_FRAG_W { + CLKDIV_FRAG_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock divider configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLKDIV_SYNC_SPEC; +impl crate::RegisterSpec for CLKDIV_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv_sync::R`](R) reader structure"] +impl crate::Readable for CLKDIV_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clkdiv_sync::W`](W) writer structure"] +impl crate::Writable for CLKDIV_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLKDIV_SYNC to value 0x02b6"] +impl crate::Resettable for CLKDIV_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x02b6; +} diff --git a/esp32p4/src/lp_uart/conf0_sync.rs b/esp32p4/src/lp_uart/conf0_sync.rs new file mode 100644 index 0000000000..d441efa575 --- /dev/null +++ b/esp32p4/src/lp_uart/conf0_sync.rs @@ -0,0 +1,293 @@ +#[doc = "Register `CONF0_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `CONF0_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `PARITY` reader - This register is used to configure the parity check mode."] +pub type PARITY_R = crate::BitReader; +#[doc = "Field `PARITY` writer - This register is used to configure the parity check mode."] +pub type PARITY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARITY_EN` reader - Set this bit to enable uart parity check."] +pub type PARITY_EN_R = crate::BitReader; +#[doc = "Field `PARITY_EN` writer - Set this bit to enable uart parity check."] +pub type PARITY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BIT_NUM` reader - This register is used to set the length of data."] +pub type BIT_NUM_R = crate::FieldReader; +#[doc = "Field `BIT_NUM` writer - This register is used to set the length of data."] +pub type BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `STOP_BIT_NUM` reader - This register is used to set the length of stop bit."] +pub type STOP_BIT_NUM_R = crate::FieldReader; +#[doc = "Field `STOP_BIT_NUM` writer - This register is used to set the length of stop bit."] +pub type STOP_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TXD_BRK` reader - Set this bit to enbale transmitter to send NULL when the process of sending data is done."] +pub type TXD_BRK_R = crate::BitReader; +#[doc = "Field `TXD_BRK` writer - Set this bit to enbale transmitter to send NULL when the process of sending data is done."] +pub type TXD_BRK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOPBACK` reader - Set this bit to enable uart loopback test mode."] +pub type LOOPBACK_R = crate::BitReader; +#[doc = "Field `LOOPBACK` writer - Set this bit to enable uart loopback test mode."] +pub type LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_FLOW_EN` reader - Set this bit to enable flow control function for transmitter."] +pub type TX_FLOW_EN_R = crate::BitReader; +#[doc = "Field `TX_FLOW_EN` writer - Set this bit to enable flow control function for transmitter."] +pub type TX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXD_INV` reader - Set this bit to inverse the level value of uart rxd signal."] +pub type RXD_INV_R = crate::BitReader; +#[doc = "Field `RXD_INV` writer - Set this bit to inverse the level value of uart rxd signal."] +pub type RXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXD_INV` reader - Set this bit to inverse the level value of uart txd signal."] +pub type TXD_INV_R = crate::BitReader; +#[doc = "Field `TXD_INV` writer - Set this bit to inverse the level value of uart txd signal."] +pub type TXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIS_RX_DAT_OVF` reader - Disable UART Rx data overflow detect."] +pub type DIS_RX_DAT_OVF_R = crate::BitReader; +#[doc = "Field `DIS_RX_DAT_OVF` writer - Disable UART Rx data overflow detect."] +pub type DIS_RX_DAT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERR_WR_MASK` reader - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."] +pub type ERR_WR_MASK_R = crate::BitReader; +#[doc = "Field `ERR_WR_MASK` writer - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."] +pub type ERR_WR_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_CLK_EN` reader - UART memory clock gate enable signal."] +pub type MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `MEM_CLK_EN` writer - UART memory clock gate enable signal."] +pub type MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_RTS` reader - This register is used to configure the software rts signal which is used in software flow control."] +pub type SW_RTS_R = crate::BitReader; +#[doc = "Field `SW_RTS` writer - This register is used to configure the software rts signal which is used in software flow control."] +pub type SW_RTS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_RST` reader - Set this bit to reset the uart receive-FIFO."] +pub type RXFIFO_RST_R = crate::BitReader; +#[doc = "Field `RXFIFO_RST` writer - Set this bit to reset the uart receive-FIFO."] +pub type RXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_RST` reader - Set this bit to reset the uart transmit-FIFO."] +pub type TXFIFO_RST_R = crate::BitReader; +#[doc = "Field `TXFIFO_RST` writer - Set this bit to reset the uart transmit-FIFO."] +pub type TXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This register is used to configure the parity check mode."] + #[inline(always)] + pub fn parity(&self) -> PARITY_R { + PARITY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to enable uart parity check."] + #[inline(always)] + pub fn parity_en(&self) -> PARITY_EN_R { + PARITY_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - This register is used to set the length of data."] + #[inline(always)] + pub fn bit_num(&self) -> BIT_NUM_R { + BIT_NUM_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - This register is used to set the length of stop bit."] + #[inline(always)] + pub fn stop_bit_num(&self) -> STOP_BIT_NUM_R { + STOP_BIT_NUM_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."] + #[inline(always)] + pub fn txd_brk(&self) -> TXD_BRK_R { + TXD_BRK_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 12 - Set this bit to enable uart loopback test mode."] + #[inline(always)] + pub fn loopback(&self) -> LOOPBACK_R { + LOOPBACK_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set this bit to enable flow control function for transmitter."] + #[inline(always)] + pub fn tx_flow_en(&self) -> TX_FLOW_EN_R { + TX_FLOW_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Set this bit to inverse the level value of uart rxd signal."] + #[inline(always)] + pub fn rxd_inv(&self) -> RXD_INV_R { + RXD_INV_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Set this bit to inverse the level value of uart txd signal."] + #[inline(always)] + pub fn txd_inv(&self) -> TXD_INV_R { + TXD_INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Disable UART Rx data overflow detect."] + #[inline(always)] + pub fn dis_rx_dat_ovf(&self) -> DIS_RX_DAT_OVF_R { + DIS_RX_DAT_OVF_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."] + #[inline(always)] + pub fn err_wr_mask(&self) -> ERR_WR_MASK_R { + ERR_WR_MASK_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 20 - UART memory clock gate enable signal."] + #[inline(always)] + pub fn mem_clk_en(&self) -> MEM_CLK_EN_R { + MEM_CLK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - This register is used to configure the software rts signal which is used in software flow control."] + #[inline(always)] + pub fn sw_rts(&self) -> SW_RTS_R { + SW_RTS_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to reset the uart receive-FIFO."] + #[inline(always)] + pub fn rxfifo_rst(&self) -> RXFIFO_RST_R { + RXFIFO_RST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Set this bit to reset the uart transmit-FIFO."] + #[inline(always)] + pub fn txfifo_rst(&self) -> TXFIFO_RST_R { + TXFIFO_RST_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF0_SYNC") + .field("parity", &format_args!("{}", self.parity().bit())) + .field("parity_en", &format_args!("{}", self.parity_en().bit())) + .field("bit_num", &format_args!("{}", self.bit_num().bits())) + .field( + "stop_bit_num", + &format_args!("{}", self.stop_bit_num().bits()), + ) + .field("txd_brk", &format_args!("{}", self.txd_brk().bit())) + .field("loopback", &format_args!("{}", self.loopback().bit())) + .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit())) + .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit())) + .field("txd_inv", &format_args!("{}", self.txd_inv().bit())) + .field( + "dis_rx_dat_ovf", + &format_args!("{}", self.dis_rx_dat_ovf().bit()), + ) + .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit())) + .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit())) + .field("sw_rts", &format_args!("{}", self.sw_rts().bit())) + .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit())) + .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This register is used to configure the parity check mode."] + #[inline(always)] + #[must_use] + pub fn parity(&mut self) -> PARITY_W { + PARITY_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to enable uart parity check."] + #[inline(always)] + #[must_use] + pub fn parity_en(&mut self) -> PARITY_EN_W { + PARITY_EN_W::new(self, 1) + } + #[doc = "Bits 2:3 - This register is used to set the length of data."] + #[inline(always)] + #[must_use] + pub fn bit_num(&mut self) -> BIT_NUM_W { + BIT_NUM_W::new(self, 2) + } + #[doc = "Bits 4:5 - This register is used to set the length of stop bit."] + #[inline(always)] + #[must_use] + pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W { + STOP_BIT_NUM_W::new(self, 4) + } + #[doc = "Bit 6 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."] + #[inline(always)] + #[must_use] + pub fn txd_brk(&mut self) -> TXD_BRK_W { + TXD_BRK_W::new(self, 6) + } + #[doc = "Bit 12 - Set this bit to enable uart loopback test mode."] + #[inline(always)] + #[must_use] + pub fn loopback(&mut self) -> LOOPBACK_W { + LOOPBACK_W::new(self, 12) + } + #[doc = "Bit 13 - Set this bit to enable flow control function for transmitter."] + #[inline(always)] + #[must_use] + pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W { + TX_FLOW_EN_W::new(self, 13) + } + #[doc = "Bit 15 - Set this bit to inverse the level value of uart rxd signal."] + #[inline(always)] + #[must_use] + pub fn rxd_inv(&mut self) -> RXD_INV_W { + RXD_INV_W::new(self, 15) + } + #[doc = "Bit 16 - Set this bit to inverse the level value of uart txd signal."] + #[inline(always)] + #[must_use] + pub fn txd_inv(&mut self) -> TXD_INV_W { + TXD_INV_W::new(self, 16) + } + #[doc = "Bit 17 - Disable UART Rx data overflow detect."] + #[inline(always)] + #[must_use] + pub fn dis_rx_dat_ovf(&mut self) -> DIS_RX_DAT_OVF_W { + DIS_RX_DAT_OVF_W::new(self, 17) + } + #[doc = "Bit 18 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."] + #[inline(always)] + #[must_use] + pub fn err_wr_mask(&mut self) -> ERR_WR_MASK_W { + ERR_WR_MASK_W::new(self, 18) + } + #[doc = "Bit 20 - UART memory clock gate enable signal."] + #[inline(always)] + #[must_use] + pub fn mem_clk_en(&mut self) -> MEM_CLK_EN_W { + MEM_CLK_EN_W::new(self, 20) + } + #[doc = "Bit 21 - This register is used to configure the software rts signal which is used in software flow control."] + #[inline(always)] + #[must_use] + pub fn sw_rts(&mut self) -> SW_RTS_W { + SW_RTS_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to reset the uart receive-FIFO."] + #[inline(always)] + #[must_use] + pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W { + RXFIFO_RST_W::new(self, 22) + } + #[doc = "Bit 23 - Set this bit to reset the uart transmit-FIFO."] + #[inline(always)] + #[must_use] + pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W { + TXFIFO_RST_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf0_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf0_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF0_SYNC_SPEC; +impl crate::RegisterSpec for CONF0_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf0_sync::R`](R) reader structure"] +impl crate::Readable for CONF0_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf0_sync::W`](W) writer structure"] +impl crate::Writable for CONF0_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF0_SYNC to value 0x1c"] +impl crate::Resettable for CONF0_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x1c; +} diff --git a/esp32p4/src/lp_uart/conf1.rs b/esp32p4/src/lp_uart/conf1.rs new file mode 100644 index 0000000000..0c58d7063a --- /dev/null +++ b/esp32p4/src/lp_uart/conf1.rs @@ -0,0 +1,181 @@ +#[doc = "Register `CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_FULL_THRHD` reader - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."] +pub type RXFIFO_FULL_THRHD_R = crate::FieldReader; +#[doc = "Field `RXFIFO_FULL_THRHD` writer - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."] +pub type RXFIFO_FULL_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `TXFIFO_EMPTY_THRHD` reader - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."] +pub type TXFIFO_EMPTY_THRHD_R = crate::FieldReader; +#[doc = "Field `TXFIFO_EMPTY_THRHD` writer - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."] +pub type TXFIFO_EMPTY_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `CTS_INV` reader - Set this bit to inverse the level value of uart cts signal."] +pub type CTS_INV_R = crate::BitReader; +#[doc = "Field `CTS_INV` writer - Set this bit to inverse the level value of uart cts signal."] +pub type CTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSR_INV` reader - Set this bit to inverse the level value of uart dsr signal."] +pub type DSR_INV_R = crate::BitReader; +#[doc = "Field `DSR_INV` writer - Set this bit to inverse the level value of uart dsr signal."] +pub type DSR_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTS_INV` reader - Set this bit to inverse the level value of uart rts signal."] +pub type RTS_INV_R = crate::BitReader; +#[doc = "Field `RTS_INV` writer - Set this bit to inverse the level value of uart rts signal."] +pub type RTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DTR_INV` reader - Set this bit to inverse the level value of uart dtr signal."] +pub type DTR_INV_R = crate::BitReader; +#[doc = "Field `DTR_INV` writer - Set this bit to inverse the level value of uart dtr signal."] +pub type DTR_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_DTR` reader - This register is used to configure the software dtr signal which is used in software flow control."] +pub type SW_DTR_R = crate::BitReader; +#[doc = "Field `SW_DTR` writer - This register is used to configure the software dtr signal which is used in software flow control."] +pub type SW_DTR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 3:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."] + #[inline(always)] + pub fn rxfifo_full_thrhd(&self) -> RXFIFO_FULL_THRHD_R { + RXFIFO_FULL_THRHD_R::new(((self.bits >> 3) & 0x1f) as u8) + } + #[doc = "Bits 11:15 - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."] + #[inline(always)] + pub fn txfifo_empty_thrhd(&self) -> TXFIFO_EMPTY_THRHD_R { + TXFIFO_EMPTY_THRHD_R::new(((self.bits >> 11) & 0x1f) as u8) + } + #[doc = "Bit 16 - Set this bit to inverse the level value of uart cts signal."] + #[inline(always)] + pub fn cts_inv(&self) -> CTS_INV_R { + CTS_INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Set this bit to inverse the level value of uart dsr signal."] + #[inline(always)] + pub fn dsr_inv(&self) -> DSR_INV_R { + DSR_INV_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Set this bit to inverse the level value of uart rts signal."] + #[inline(always)] + pub fn rts_inv(&self) -> RTS_INV_R { + RTS_INV_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Set this bit to inverse the level value of uart dtr signal."] + #[inline(always)] + pub fn dtr_inv(&self) -> DTR_INV_R { + DTR_INV_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - This register is used to configure the software dtr signal which is used in software flow control."] + #[inline(always)] + pub fn sw_dtr(&self) -> SW_DTR_R { + SW_DTR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF1") + .field( + "rxfifo_full_thrhd", + &format_args!("{}", self.rxfifo_full_thrhd().bits()), + ) + .field( + "txfifo_empty_thrhd", + &format_args!("{}", self.txfifo_empty_thrhd().bits()), + ) + .field("cts_inv", &format_args!("{}", self.cts_inv().bit())) + .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit())) + .field("rts_inv", &format_args!("{}", self.rts_inv().bit())) + .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit())) + .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 3:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."] + #[inline(always)] + #[must_use] + pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W { + RXFIFO_FULL_THRHD_W::new(self, 3) + } + #[doc = "Bits 11:15 - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."] + #[inline(always)] + #[must_use] + pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W { + TXFIFO_EMPTY_THRHD_W::new(self, 11) + } + #[doc = "Bit 16 - Set this bit to inverse the level value of uart cts signal."] + #[inline(always)] + #[must_use] + pub fn cts_inv(&mut self) -> CTS_INV_W { + CTS_INV_W::new(self, 16) + } + #[doc = "Bit 17 - Set this bit to inverse the level value of uart dsr signal."] + #[inline(always)] + #[must_use] + pub fn dsr_inv(&mut self) -> DSR_INV_W { + DSR_INV_W::new(self, 17) + } + #[doc = "Bit 18 - Set this bit to inverse the level value of uart rts signal."] + #[inline(always)] + #[must_use] + pub fn rts_inv(&mut self) -> RTS_INV_W { + RTS_INV_W::new(self, 18) + } + #[doc = "Bit 19 - Set this bit to inverse the level value of uart dtr signal."] + #[inline(always)] + #[must_use] + pub fn dtr_inv(&mut self) -> DTR_INV_W { + DTR_INV_W::new(self, 19) + } + #[doc = "Bit 20 - This register is used to configure the software dtr signal which is used in software flow control."] + #[inline(always)] + #[must_use] + pub fn sw_dtr(&mut self) -> SW_DTR_W { + SW_DTR_W::new(self, 20) + } + #[doc = "Bit 21 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF1_SPEC; +impl crate::RegisterSpec for CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf1::R`](R) reader structure"] +impl crate::Readable for CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf1::W`](W) writer structure"] +impl crate::Writable for CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF1 to value 0x6060"] +impl crate::Resettable for CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x6060; +} diff --git a/esp32p4/src/lp_uart/date.rs b/esp32p4/src/lp_uart/date.rs new file mode 100644 index 0000000000..0322224da8 --- /dev/null +++ b/esp32p4/src/lp_uart/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - This is the version register."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - This is the version register."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This is the version register."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This is the version register."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_5050"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_5050; +} diff --git a/esp32p4/src/lp_uart/fifo.rs b/esp32p4/src/lp_uart/fifo.rs new file mode 100644 index 0000000000..5670061c44 --- /dev/null +++ b/esp32p4/src/lp_uart/fifo.rs @@ -0,0 +1,39 @@ +#[doc = "Register `FIFO` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_RD_BYTE` reader - UART 0 accesses FIFO via this register."] +pub type RXFIFO_RD_BYTE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."] + #[inline(always)] + pub fn rxfifo_rd_byte(&self) -> RXFIFO_RD_BYTE_R { + RXFIFO_RD_BYTE_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO") + .field( + "rxfifo_rd_byte", + &format_args!("{}", self.rxfifo_rd_byte().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "FIFO data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_SPEC; +impl crate::RegisterSpec for FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} +#[doc = "`reset()` method sets FIFO to value 0"] +impl crate::Resettable for FIFO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/fsm_status.rs b/esp32p4/src/lp_uart/fsm_status.rs new file mode 100644 index 0000000000..8a34e7ab1e --- /dev/null +++ b/esp32p4/src/lp_uart/fsm_status.rs @@ -0,0 +1,44 @@ +#[doc = "Register `FSM_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `ST_URX_OUT` reader - This is the status register of receiver."] +pub type ST_URX_OUT_R = crate::FieldReader; +#[doc = "Field `ST_UTX_OUT` reader - This is the status register of transmitter."] +pub type ST_UTX_OUT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - This is the status register of receiver."] + #[inline(always)] + pub fn st_urx_out(&self) -> ST_URX_OUT_R { + ST_URX_OUT_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - This is the status register of transmitter."] + #[inline(always)] + pub fn st_utx_out(&self) -> ST_UTX_OUT_R { + ST_UTX_OUT_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FSM_STATUS") + .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits())) + .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FSM_STATUS_SPEC; +impl crate::RegisterSpec for FSM_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fsm_status::R`](R) reader structure"] +impl crate::Readable for FSM_STATUS_SPEC {} +#[doc = "`reset()` method sets FSM_STATUS to value 0"] +impl crate::Resettable for FSM_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/hwfc_conf_sync.rs b/esp32p4/src/lp_uart/hwfc_conf_sync.rs new file mode 100644 index 0000000000..713951c138 --- /dev/null +++ b/esp32p4/src/lp_uart/hwfc_conf_sync.rs @@ -0,0 +1,82 @@ +#[doc = "Register `HWFC_CONF_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `HWFC_CONF_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `RX_FLOW_THRHD` reader - This register is used to configure the maximum amount of data that can be received when hardware flow control works."] +pub type RX_FLOW_THRHD_R = crate::FieldReader; +#[doc = "Field `RX_FLOW_THRHD` writer - This register is used to configure the maximum amount of data that can be received when hardware flow control works."] +pub type RX_FLOW_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `RX_FLOW_EN` reader - This is the flow enable bit for UART receiver."] +pub type RX_FLOW_EN_R = crate::BitReader; +#[doc = "Field `RX_FLOW_EN` writer - This is the flow enable bit for UART receiver."] +pub type RX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 3:7 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."] + #[inline(always)] + pub fn rx_flow_thrhd(&self) -> RX_FLOW_THRHD_R { + RX_FLOW_THRHD_R::new(((self.bits >> 3) & 0x1f) as u8) + } + #[doc = "Bit 8 - This is the flow enable bit for UART receiver."] + #[inline(always)] + pub fn rx_flow_en(&self) -> RX_FLOW_EN_R { + RX_FLOW_EN_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HWFC_CONF_SYNC") + .field( + "rx_flow_thrhd", + &format_args!("{}", self.rx_flow_thrhd().bits()), + ) + .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 3:7 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."] + #[inline(always)] + #[must_use] + pub fn rx_flow_thrhd(&mut self) -> RX_FLOW_THRHD_W { + RX_FLOW_THRHD_W::new(self, 3) + } + #[doc = "Bit 8 - This is the flow enable bit for UART receiver."] + #[inline(always)] + #[must_use] + pub fn rx_flow_en(&mut self) -> RX_FLOW_EN_W { + RX_FLOW_EN_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Hardware flow-control configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwfc_conf_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwfc_conf_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HWFC_CONF_SYNC_SPEC; +impl crate::RegisterSpec for HWFC_CONF_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hwfc_conf_sync::R`](R) reader structure"] +impl crate::Readable for HWFC_CONF_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hwfc_conf_sync::W`](W) writer structure"] +impl crate::Writable for HWFC_CONF_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HWFC_CONF_SYNC to value 0"] +impl crate::Resettable for HWFC_CONF_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/id.rs b/esp32p4/src/lp_uart/id.rs new file mode 100644 index 0000000000..20d5d54393 --- /dev/null +++ b/esp32p4/src/lp_uart/id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID` reader"] +pub type R = crate::R; +#[doc = "Register `ID` writer"] +pub type W = crate::W; +#[doc = "Field `ID` reader - This register is used to configure the uart_id."] +pub type ID_R = crate::FieldReader; +#[doc = "Field `ID` writer - This register is used to configure the uart_id."] +pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is used to configure the uart_id."] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ID") + .field("id", &format_args!("{}", self.id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register is used to configure the uart_id."] + #[inline(always)] + #[must_use] + pub fn id(&mut self) -> ID_W { + ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_SPEC; +impl crate::RegisterSpec for ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id::R`](R) reader structure"] +impl crate::Readable for ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id::W`](W) writer structure"] +impl crate::Writable for ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ID to value 0x0500"] +impl crate::Resettable for ID_SPEC { + const RESET_VALUE: Self::Ux = 0x0500; +} diff --git a/esp32p4/src/lp_uart/idle_conf_sync.rs b/esp32p4/src/lp_uart/idle_conf_sync.rs new file mode 100644 index 0000000000..99ae7c7b5b --- /dev/null +++ b/esp32p4/src/lp_uart/idle_conf_sync.rs @@ -0,0 +1,85 @@ +#[doc = "Register `IDLE_CONF_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `IDLE_CONF_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `RX_IDLE_THRHD` reader - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."] +pub type RX_IDLE_THRHD_R = crate::FieldReader; +#[doc = "Field `RX_IDLE_THRHD` writer - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."] +pub type RX_IDLE_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `TX_IDLE_NUM` reader - This register is used to configure the duration time between transfers."] +pub type TX_IDLE_NUM_R = crate::FieldReader; +#[doc = "Field `TX_IDLE_NUM` writer - This register is used to configure the duration time between transfers."] +pub type TX_IDLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."] + #[inline(always)] + pub fn rx_idle_thrhd(&self) -> RX_IDLE_THRHD_R { + RX_IDLE_THRHD_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:19 - This register is used to configure the duration time between transfers."] + #[inline(always)] + pub fn tx_idle_num(&self) -> TX_IDLE_NUM_R { + TX_IDLE_NUM_R::new(((self.bits >> 10) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IDLE_CONF_SYNC") + .field( + "rx_idle_thrhd", + &format_args!("{}", self.rx_idle_thrhd().bits()), + ) + .field( + "tx_idle_num", + &format_args!("{}", self.tx_idle_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."] + #[inline(always)] + #[must_use] + pub fn rx_idle_thrhd(&mut self) -> RX_IDLE_THRHD_W { + RX_IDLE_THRHD_W::new(self, 0) + } + #[doc = "Bits 10:19 - This register is used to configure the duration time between transfers."] + #[inline(always)] + #[must_use] + pub fn tx_idle_num(&mut self) -> TX_IDLE_NUM_W { + TX_IDLE_NUM_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Frame-end idle configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle_conf_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idle_conf_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IDLE_CONF_SYNC_SPEC; +impl crate::RegisterSpec for IDLE_CONF_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`idle_conf_sync::R`](R) reader structure"] +impl crate::Readable for IDLE_CONF_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`idle_conf_sync::W`](W) writer structure"] +impl crate::Writable for IDLE_CONF_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IDLE_CONF_SYNC to value 0x0004_0100"] +impl crate::Resettable for IDLE_CONF_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x0004_0100; +} diff --git a/esp32p4/src/lp_uart/int_clr.rs b/esp32p4/src/lp_uart/int_clr.rs new file mode 100644 index 0000000000..b41350dc93 --- /dev/null +++ b/esp32p4/src/lp_uart/int_clr.rs @@ -0,0 +1,170 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_FULL_INT_CLR` writer - Set this bit to clear the rxfifo_full_int_raw interrupt."] +pub type RXFIFO_FULL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_EMPTY_INT_CLR` writer - Set this bit to clear txfifo_empty_int_raw interrupt."] +pub type TXFIFO_EMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARITY_ERR_INT_CLR` writer - Set this bit to clear parity_err_int_raw interrupt."] +pub type PARITY_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRM_ERR_INT_CLR` writer - Set this bit to clear frm_err_int_raw interrupt."] +pub type FRM_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF_INT_CLR` writer - Set this bit to clear rxfifo_ovf_int_raw interrupt."] +pub type RXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSR_CHG_INT_CLR` writer - Set this bit to clear the dsr_chg_int_raw interrupt."] +pub type DSR_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTS_CHG_INT_CLR` writer - Set this bit to clear the cts_chg_int_raw interrupt."] +pub type CTS_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRK_DET_INT_CLR` writer - Set this bit to clear the brk_det_int_raw interrupt."] +pub type BRK_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_TOUT_INT_CLR` writer - Set this bit to clear the rxfifo_tout_int_raw interrupt."] +pub type RXFIFO_TOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XON_INT_CLR` writer - Set this bit to clear the sw_xon_int_raw interrupt."] +pub type SW_XON_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XOFF_INT_CLR` writer - Set this bit to clear the sw_xoff_int_raw interrupt."] +pub type SW_XOFF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GLITCH_DET_INT_CLR` writer - Set this bit to clear the glitch_det_int_raw interrupt."] +pub type GLITCH_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_DONE_INT_CLR` writer - Set this bit to clear the tx_brk_done_int_raw interrupt.."] +pub type TX_BRK_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_CLR` writer - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."] +pub type TX_BRK_IDLE_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DONE_INT_CLR` writer - Set this bit to clear the tx_done_int_raw interrupt."] +pub type TX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AT_CMD_CHAR_DET_INT_CLR` writer - Set this bit to clear the at_cmd_char_det_int_raw interrupt."] +pub type AT_CMD_CHAR_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAKEUP_INT_CLR` writer - Set this bit to clear the uart_wakeup_int_raw interrupt."] +pub type WAKEUP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the rxfifo_full_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_full_int_clr(&mut self) -> RXFIFO_FULL_INT_CLR_W { + RXFIFO_FULL_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear txfifo_empty_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn txfifo_empty_int_clr(&mut self) -> TXFIFO_EMPTY_INT_CLR_W { + TXFIFO_EMPTY_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear parity_err_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn parity_err_int_clr(&mut self) -> PARITY_ERR_INT_CLR_W { + PARITY_ERR_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear frm_err_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn frm_err_int_clr(&mut self) -> FRM_ERR_INT_CLR_W { + FRM_ERR_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear rxfifo_ovf_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_ovf_int_clr(&mut self) -> RXFIFO_OVF_INT_CLR_W { + RXFIFO_OVF_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the dsr_chg_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn dsr_chg_int_clr(&mut self) -> DSR_CHG_INT_CLR_W { + DSR_CHG_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the cts_chg_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn cts_chg_int_clr(&mut self) -> CTS_CHG_INT_CLR_W { + CTS_CHG_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the brk_det_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn brk_det_int_clr(&mut self) -> BRK_DET_INT_CLR_W { + BRK_DET_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the rxfifo_tout_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_tout_int_clr(&mut self) -> RXFIFO_TOUT_INT_CLR_W { + RXFIFO_TOUT_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the sw_xon_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn sw_xon_int_clr(&mut self) -> SW_XON_INT_CLR_W { + SW_XON_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to clear the sw_xoff_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn sw_xoff_int_clr(&mut self) -> SW_XOFF_INT_CLR_W { + SW_XOFF_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Set this bit to clear the glitch_det_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn glitch_det_int_clr(&mut self) -> GLITCH_DET_INT_CLR_W { + GLITCH_DET_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Set this bit to clear the tx_brk_done_int_raw interrupt.."] + #[inline(always)] + #[must_use] + pub fn tx_brk_done_int_clr(&mut self) -> TX_BRK_DONE_INT_CLR_W { + TX_BRK_DONE_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn tx_brk_idle_done_int_clr(&mut self) -> TX_BRK_IDLE_DONE_INT_CLR_W { + TX_BRK_IDLE_DONE_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Set this bit to clear the tx_done_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn tx_done_int_clr(&mut self) -> TX_DONE_INT_CLR_W { + TX_DONE_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 18 - Set this bit to clear the at_cmd_char_det_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn at_cmd_char_det_int_clr(&mut self) -> AT_CMD_CHAR_DET_INT_CLR_W { + AT_CMD_CHAR_DET_INT_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Set this bit to clear the uart_wakeup_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn wakeup_int_clr(&mut self) -> WAKEUP_INT_CLR_W { + WAKEUP_INT_CLR_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/int_ena.rs b/esp32p4/src/lp_uart/int_ena.rs new file mode 100644 index 0000000000..ee6d3adebc --- /dev/null +++ b/esp32p4/src/lp_uart/int_ena.rs @@ -0,0 +1,370 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_FULL_INT_ENA` reader - This is the enable bit for rxfifo_full_int_st register."] +pub type RXFIFO_FULL_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_FULL_INT_ENA` writer - This is the enable bit for rxfifo_full_int_st register."] +pub type RXFIFO_FULL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_EMPTY_INT_ENA` reader - This is the enable bit for txfifo_empty_int_st register."] +pub type TXFIFO_EMPTY_INT_ENA_R = crate::BitReader; +#[doc = "Field `TXFIFO_EMPTY_INT_ENA` writer - This is the enable bit for txfifo_empty_int_st register."] +pub type TXFIFO_EMPTY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARITY_ERR_INT_ENA` reader - This is the enable bit for parity_err_int_st register."] +pub type PARITY_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `PARITY_ERR_INT_ENA` writer - This is the enable bit for parity_err_int_st register."] +pub type PARITY_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRM_ERR_INT_ENA` reader - This is the enable bit for frm_err_int_st register."] +pub type FRM_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `FRM_ERR_INT_ENA` writer - This is the enable bit for frm_err_int_st register."] +pub type FRM_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF_INT_ENA` reader - This is the enable bit for rxfifo_ovf_int_st register."] +pub type RXFIFO_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_ENA` writer - This is the enable bit for rxfifo_ovf_int_st register."] +pub type RXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSR_CHG_INT_ENA` reader - This is the enable bit for dsr_chg_int_st register."] +pub type DSR_CHG_INT_ENA_R = crate::BitReader; +#[doc = "Field `DSR_CHG_INT_ENA` writer - This is the enable bit for dsr_chg_int_st register."] +pub type DSR_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTS_CHG_INT_ENA` reader - This is the enable bit for cts_chg_int_st register."] +pub type CTS_CHG_INT_ENA_R = crate::BitReader; +#[doc = "Field `CTS_CHG_INT_ENA` writer - This is the enable bit for cts_chg_int_st register."] +pub type CTS_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRK_DET_INT_ENA` reader - This is the enable bit for brk_det_int_st register."] +pub type BRK_DET_INT_ENA_R = crate::BitReader; +#[doc = "Field `BRK_DET_INT_ENA` writer - This is the enable bit for brk_det_int_st register."] +pub type BRK_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_TOUT_INT_ENA` reader - This is the enable bit for rxfifo_tout_int_st register."] +pub type RXFIFO_TOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_TOUT_INT_ENA` writer - This is the enable bit for rxfifo_tout_int_st register."] +pub type RXFIFO_TOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XON_INT_ENA` reader - This is the enable bit for sw_xon_int_st register."] +pub type SW_XON_INT_ENA_R = crate::BitReader; +#[doc = "Field `SW_XON_INT_ENA` writer - This is the enable bit for sw_xon_int_st register."] +pub type SW_XON_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XOFF_INT_ENA` reader - This is the enable bit for sw_xoff_int_st register."] +pub type SW_XOFF_INT_ENA_R = crate::BitReader; +#[doc = "Field `SW_XOFF_INT_ENA` writer - This is the enable bit for sw_xoff_int_st register."] +pub type SW_XOFF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GLITCH_DET_INT_ENA` reader - This is the enable bit for glitch_det_int_st register."] +pub type GLITCH_DET_INT_ENA_R = crate::BitReader; +#[doc = "Field `GLITCH_DET_INT_ENA` writer - This is the enable bit for glitch_det_int_st register."] +pub type GLITCH_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_DONE_INT_ENA` reader - This is the enable bit for tx_brk_done_int_st register."] +pub type TX_BRK_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_BRK_DONE_INT_ENA` writer - This is the enable bit for tx_brk_done_int_st register."] +pub type TX_BRK_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_ENA` reader - This is the enable bit for tx_brk_idle_done_int_st register."] +pub type TX_BRK_IDLE_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_ENA` writer - This is the enable bit for tx_brk_idle_done_int_st register."] +pub type TX_BRK_IDLE_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DONE_INT_ENA` reader - This is the enable bit for tx_done_int_st register."] +pub type TX_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_DONE_INT_ENA` writer - This is the enable bit for tx_done_int_st register."] +pub type TX_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AT_CMD_CHAR_DET_INT_ENA` reader - This is the enable bit for at_cmd_char_det_int_st register."] +pub type AT_CMD_CHAR_DET_INT_ENA_R = crate::BitReader; +#[doc = "Field `AT_CMD_CHAR_DET_INT_ENA` writer - This is the enable bit for at_cmd_char_det_int_st register."] +pub type AT_CMD_CHAR_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAKEUP_INT_ENA` reader - This is the enable bit for uart_wakeup_int_st register."] +pub type WAKEUP_INT_ENA_R = crate::BitReader; +#[doc = "Field `WAKEUP_INT_ENA` writer - This is the enable bit for uart_wakeup_int_st register."] +pub type WAKEUP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."] + #[inline(always)] + pub fn rxfifo_full_int_ena(&self) -> RXFIFO_FULL_INT_ENA_R { + RXFIFO_FULL_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This is the enable bit for txfifo_empty_int_st register."] + #[inline(always)] + pub fn txfifo_empty_int_ena(&self) -> TXFIFO_EMPTY_INT_ENA_R { + TXFIFO_EMPTY_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."] + #[inline(always)] + pub fn parity_err_int_ena(&self) -> PARITY_ERR_INT_ENA_R { + PARITY_ERR_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."] + #[inline(always)] + pub fn frm_err_int_ena(&self) -> FRM_ERR_INT_ENA_R { + FRM_ERR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."] + #[inline(always)] + pub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R { + RXFIFO_OVF_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."] + #[inline(always)] + pub fn dsr_chg_int_ena(&self) -> DSR_CHG_INT_ENA_R { + DSR_CHG_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."] + #[inline(always)] + pub fn cts_chg_int_ena(&self) -> CTS_CHG_INT_ENA_R { + CTS_CHG_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."] + #[inline(always)] + pub fn brk_det_int_ena(&self) -> BRK_DET_INT_ENA_R { + BRK_DET_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."] + #[inline(always)] + pub fn rxfifo_tout_int_ena(&self) -> RXFIFO_TOUT_INT_ENA_R { + RXFIFO_TOUT_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."] + #[inline(always)] + pub fn sw_xon_int_ena(&self) -> SW_XON_INT_ENA_R { + SW_XON_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."] + #[inline(always)] + pub fn sw_xoff_int_ena(&self) -> SW_XOFF_INT_ENA_R { + SW_XOFF_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."] + #[inline(always)] + pub fn glitch_det_int_ena(&self) -> GLITCH_DET_INT_ENA_R { + GLITCH_DET_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."] + #[inline(always)] + pub fn tx_brk_done_int_ena(&self) -> TX_BRK_DONE_INT_ENA_R { + TX_BRK_DONE_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."] + #[inline(always)] + pub fn tx_brk_idle_done_int_ena(&self) -> TX_BRK_IDLE_DONE_INT_ENA_R { + TX_BRK_IDLE_DONE_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."] + #[inline(always)] + pub fn tx_done_int_ena(&self) -> TX_DONE_INT_ENA_R { + TX_DONE_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."] + #[inline(always)] + pub fn at_cmd_char_det_int_ena(&self) -> AT_CMD_CHAR_DET_INT_ENA_R { + AT_CMD_CHAR_DET_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - This is the enable bit for uart_wakeup_int_st register."] + #[inline(always)] + pub fn wakeup_int_ena(&self) -> WAKEUP_INT_ENA_R { + WAKEUP_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "rxfifo_full_int_ena", + &format_args!("{}", self.rxfifo_full_int_ena().bit()), + ) + .field( + "txfifo_empty_int_ena", + &format_args!("{}", self.txfifo_empty_int_ena().bit()), + ) + .field( + "parity_err_int_ena", + &format_args!("{}", self.parity_err_int_ena().bit()), + ) + .field( + "frm_err_int_ena", + &format_args!("{}", self.frm_err_int_ena().bit()), + ) + .field( + "rxfifo_ovf_int_ena", + &format_args!("{}", self.rxfifo_ovf_int_ena().bit()), + ) + .field( + "dsr_chg_int_ena", + &format_args!("{}", self.dsr_chg_int_ena().bit()), + ) + .field( + "cts_chg_int_ena", + &format_args!("{}", self.cts_chg_int_ena().bit()), + ) + .field( + "brk_det_int_ena", + &format_args!("{}", self.brk_det_int_ena().bit()), + ) + .field( + "rxfifo_tout_int_ena", + &format_args!("{}", self.rxfifo_tout_int_ena().bit()), + ) + .field( + "sw_xon_int_ena", + &format_args!("{}", self.sw_xon_int_ena().bit()), + ) + .field( + "sw_xoff_int_ena", + &format_args!("{}", self.sw_xoff_int_ena().bit()), + ) + .field( + "glitch_det_int_ena", + &format_args!("{}", self.glitch_det_int_ena().bit()), + ) + .field( + "tx_brk_done_int_ena", + &format_args!("{}", self.tx_brk_done_int_ena().bit()), + ) + .field( + "tx_brk_idle_done_int_ena", + &format_args!("{}", self.tx_brk_idle_done_int_ena().bit()), + ) + .field( + "tx_done_int_ena", + &format_args!("{}", self.tx_done_int_ena().bit()), + ) + .field( + "at_cmd_char_det_int_ena", + &format_args!("{}", self.at_cmd_char_det_int_ena().bit()), + ) + .field( + "wakeup_int_ena", + &format_args!("{}", self.wakeup_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."] + #[inline(always)] + #[must_use] + pub fn rxfifo_full_int_ena(&mut self) -> RXFIFO_FULL_INT_ENA_W { + RXFIFO_FULL_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - This is the enable bit for txfifo_empty_int_st register."] + #[inline(always)] + #[must_use] + pub fn txfifo_empty_int_ena(&mut self) -> TXFIFO_EMPTY_INT_ENA_W { + TXFIFO_EMPTY_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."] + #[inline(always)] + #[must_use] + pub fn parity_err_int_ena(&mut self) -> PARITY_ERR_INT_ENA_W { + PARITY_ERR_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."] + #[inline(always)] + #[must_use] + pub fn frm_err_int_ena(&mut self) -> FRM_ERR_INT_ENA_W { + FRM_ERR_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."] + #[inline(always)] + #[must_use] + pub fn rxfifo_ovf_int_ena(&mut self) -> RXFIFO_OVF_INT_ENA_W { + RXFIFO_OVF_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."] + #[inline(always)] + #[must_use] + pub fn dsr_chg_int_ena(&mut self) -> DSR_CHG_INT_ENA_W { + DSR_CHG_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."] + #[inline(always)] + #[must_use] + pub fn cts_chg_int_ena(&mut self) -> CTS_CHG_INT_ENA_W { + CTS_CHG_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."] + #[inline(always)] + #[must_use] + pub fn brk_det_int_ena(&mut self) -> BRK_DET_INT_ENA_W { + BRK_DET_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."] + #[inline(always)] + #[must_use] + pub fn rxfifo_tout_int_ena(&mut self) -> RXFIFO_TOUT_INT_ENA_W { + RXFIFO_TOUT_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."] + #[inline(always)] + #[must_use] + pub fn sw_xon_int_ena(&mut self) -> SW_XON_INT_ENA_W { + SW_XON_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."] + #[inline(always)] + #[must_use] + pub fn sw_xoff_int_ena(&mut self) -> SW_XOFF_INT_ENA_W { + SW_XOFF_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."] + #[inline(always)] + #[must_use] + pub fn glitch_det_int_ena(&mut self) -> GLITCH_DET_INT_ENA_W { + GLITCH_DET_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."] + #[inline(always)] + #[must_use] + pub fn tx_brk_done_int_ena(&mut self) -> TX_BRK_DONE_INT_ENA_W { + TX_BRK_DONE_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."] + #[inline(always)] + #[must_use] + pub fn tx_brk_idle_done_int_ena(&mut self) -> TX_BRK_IDLE_DONE_INT_ENA_W { + TX_BRK_IDLE_DONE_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."] + #[inline(always)] + #[must_use] + pub fn tx_done_int_ena(&mut self) -> TX_DONE_INT_ENA_W { + TX_DONE_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."] + #[inline(always)] + #[must_use] + pub fn at_cmd_char_det_int_ena(&mut self) -> AT_CMD_CHAR_DET_INT_ENA_W { + AT_CMD_CHAR_DET_INT_ENA_W::new(self, 18) + } + #[doc = "Bit 19 - This is the enable bit for uart_wakeup_int_st register."] + #[inline(always)] + #[must_use] + pub fn wakeup_int_ena(&mut self) -> WAKEUP_INT_ENA_W { + WAKEUP_INT_ENA_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/int_raw.rs b/esp32p4/src/lp_uart/int_raw.rs new file mode 100644 index 0000000000..48d0c1727c --- /dev/null +++ b/esp32p4/src/lp_uart/int_raw.rs @@ -0,0 +1,370 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_FULL_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] +pub type RXFIFO_FULL_INT_RAW_R = crate::BitReader; +#[doc = "Field `RXFIFO_FULL_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] +pub type RXFIFO_FULL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_EMPTY_INT_RAW` reader - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] +pub type TXFIFO_EMPTY_INT_RAW_R = crate::BitReader; +#[doc = "Field `TXFIFO_EMPTY_INT_RAW` writer - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] +pub type TXFIFO_EMPTY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARITY_ERR_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] +pub type PARITY_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `PARITY_ERR_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] +pub type PARITY_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRM_ERR_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a data frame error ."] +pub type FRM_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `FRM_ERR_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a data frame error ."] +pub type FRM_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] +pub type RXFIFO_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] +pub type RXFIFO_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSR_CHG_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] +pub type DSR_CHG_INT_RAW_R = crate::BitReader; +#[doc = "Field `DSR_CHG_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] +pub type DSR_CHG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTS_CHG_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] +pub type CTS_CHG_INT_RAW_R = crate::BitReader; +#[doc = "Field `CTS_CHG_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] +pub type CTS_CHG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRK_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] +pub type BRK_DET_INT_RAW_R = crate::BitReader; +#[doc = "Field `BRK_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] +pub type BRK_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_TOUT_INT_RAW` reader - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] +pub type RXFIFO_TOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `RXFIFO_TOUT_INT_RAW` writer - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] +pub type RXFIFO_TOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XON_INT_RAW` reader - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] +pub type SW_XON_INT_RAW_R = crate::BitReader; +#[doc = "Field `SW_XON_INT_RAW` writer - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] +pub type SW_XON_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XOFF_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] +pub type SW_XOFF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SW_XOFF_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] +pub type SW_XOFF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GLITCH_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] +pub type GLITCH_DET_INT_RAW_R = crate::BitReader; +#[doc = "Field `GLITCH_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] +pub type GLITCH_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] +pub type TX_BRK_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_BRK_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] +pub type TX_BRK_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] +pub type TX_BRK_IDLE_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] +pub type TX_BRK_IDLE_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] +pub type TX_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] +pub type TX_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AT_CMD_CHAR_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] +pub type AT_CMD_CHAR_DET_INT_RAW_R = crate::BitReader; +#[doc = "Field `AT_CMD_CHAR_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] +pub type AT_CMD_CHAR_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAKEUP_INT_RAW` reader - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] +pub type WAKEUP_INT_RAW_R = crate::BitReader; +#[doc = "Field `WAKEUP_INT_RAW` writer - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] +pub type WAKEUP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] + #[inline(always)] + pub fn rxfifo_full_int_raw(&self) -> RXFIFO_FULL_INT_RAW_R { + RXFIFO_FULL_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] + #[inline(always)] + pub fn txfifo_empty_int_raw(&self) -> TXFIFO_EMPTY_INT_RAW_R { + TXFIFO_EMPTY_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] + #[inline(always)] + pub fn parity_err_int_raw(&self) -> PARITY_ERR_INT_RAW_R { + PARITY_ERR_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This interrupt raw bit turns to high level when receiver detects a data frame error ."] + #[inline(always)] + pub fn frm_err_int_raw(&self) -> FRM_ERR_INT_RAW_R { + FRM_ERR_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] + #[inline(always)] + pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R { + RXFIFO_OVF_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] + #[inline(always)] + pub fn dsr_chg_int_raw(&self) -> DSR_CHG_INT_RAW_R { + DSR_CHG_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] + #[inline(always)] + pub fn cts_chg_int_raw(&self) -> CTS_CHG_INT_RAW_R { + CTS_CHG_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] + #[inline(always)] + pub fn brk_det_int_raw(&self) -> BRK_DET_INT_RAW_R { + BRK_DET_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] + #[inline(always)] + pub fn rxfifo_tout_int_raw(&self) -> RXFIFO_TOUT_INT_RAW_R { + RXFIFO_TOUT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] + #[inline(always)] + pub fn sw_xon_int_raw(&self) -> SW_XON_INT_RAW_R { + SW_XON_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] + #[inline(always)] + pub fn sw_xoff_int_raw(&self) -> SW_XOFF_INT_RAW_R { + SW_XOFF_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] + #[inline(always)] + pub fn glitch_det_int_raw(&self) -> GLITCH_DET_INT_RAW_R { + GLITCH_DET_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] + #[inline(always)] + pub fn tx_brk_done_int_raw(&self) -> TX_BRK_DONE_INT_RAW_R { + TX_BRK_DONE_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] + #[inline(always)] + pub fn tx_brk_idle_done_int_raw(&self) -> TX_BRK_IDLE_DONE_INT_RAW_R { + TX_BRK_IDLE_DONE_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] + #[inline(always)] + pub fn tx_done_int_raw(&self) -> TX_DONE_INT_RAW_R { + TX_DONE_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 18 - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] + #[inline(always)] + pub fn at_cmd_char_det_int_raw(&self) -> AT_CMD_CHAR_DET_INT_RAW_R { + AT_CMD_CHAR_DET_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] + #[inline(always)] + pub fn wakeup_int_raw(&self) -> WAKEUP_INT_RAW_R { + WAKEUP_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "rxfifo_full_int_raw", + &format_args!("{}", self.rxfifo_full_int_raw().bit()), + ) + .field( + "txfifo_empty_int_raw", + &format_args!("{}", self.txfifo_empty_int_raw().bit()), + ) + .field( + "parity_err_int_raw", + &format_args!("{}", self.parity_err_int_raw().bit()), + ) + .field( + "frm_err_int_raw", + &format_args!("{}", self.frm_err_int_raw().bit()), + ) + .field( + "rxfifo_ovf_int_raw", + &format_args!("{}", self.rxfifo_ovf_int_raw().bit()), + ) + .field( + "dsr_chg_int_raw", + &format_args!("{}", self.dsr_chg_int_raw().bit()), + ) + .field( + "cts_chg_int_raw", + &format_args!("{}", self.cts_chg_int_raw().bit()), + ) + .field( + "brk_det_int_raw", + &format_args!("{}", self.brk_det_int_raw().bit()), + ) + .field( + "rxfifo_tout_int_raw", + &format_args!("{}", self.rxfifo_tout_int_raw().bit()), + ) + .field( + "sw_xon_int_raw", + &format_args!("{}", self.sw_xon_int_raw().bit()), + ) + .field( + "sw_xoff_int_raw", + &format_args!("{}", self.sw_xoff_int_raw().bit()), + ) + .field( + "glitch_det_int_raw", + &format_args!("{}", self.glitch_det_int_raw().bit()), + ) + .field( + "tx_brk_done_int_raw", + &format_args!("{}", self.tx_brk_done_int_raw().bit()), + ) + .field( + "tx_brk_idle_done_int_raw", + &format_args!("{}", self.tx_brk_idle_done_int_raw().bit()), + ) + .field( + "tx_done_int_raw", + &format_args!("{}", self.tx_done_int_raw().bit()), + ) + .field( + "at_cmd_char_det_int_raw", + &format_args!("{}", self.at_cmd_char_det_int_raw().bit()), + ) + .field( + "wakeup_int_raw", + &format_args!("{}", self.wakeup_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] + #[inline(always)] + #[must_use] + pub fn rxfifo_full_int_raw(&mut self) -> RXFIFO_FULL_INT_RAW_W { + RXFIFO_FULL_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] + #[inline(always)] + #[must_use] + pub fn txfifo_empty_int_raw(&mut self) -> TXFIFO_EMPTY_INT_RAW_W { + TXFIFO_EMPTY_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] + #[inline(always)] + #[must_use] + pub fn parity_err_int_raw(&mut self) -> PARITY_ERR_INT_RAW_W { + PARITY_ERR_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - This interrupt raw bit turns to high level when receiver detects a data frame error ."] + #[inline(always)] + #[must_use] + pub fn frm_err_int_raw(&mut self) -> FRM_ERR_INT_RAW_W { + FRM_ERR_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] + #[inline(always)] + #[must_use] + pub fn rxfifo_ovf_int_raw(&mut self) -> RXFIFO_OVF_INT_RAW_W { + RXFIFO_OVF_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] + #[inline(always)] + #[must_use] + pub fn dsr_chg_int_raw(&mut self) -> DSR_CHG_INT_RAW_W { + DSR_CHG_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] + #[inline(always)] + #[must_use] + pub fn cts_chg_int_raw(&mut self) -> CTS_CHG_INT_RAW_W { + CTS_CHG_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] + #[inline(always)] + #[must_use] + pub fn brk_det_int_raw(&mut self) -> BRK_DET_INT_RAW_W { + BRK_DET_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] + #[inline(always)] + #[must_use] + pub fn rxfifo_tout_int_raw(&mut self) -> RXFIFO_TOUT_INT_RAW_W { + RXFIFO_TOUT_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] + #[inline(always)] + #[must_use] + pub fn sw_xon_int_raw(&mut self) -> SW_XON_INT_RAW_W { + SW_XON_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] + #[inline(always)] + #[must_use] + pub fn sw_xoff_int_raw(&mut self) -> SW_XOFF_INT_RAW_W { + SW_XOFF_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] + #[inline(always)] + #[must_use] + pub fn glitch_det_int_raw(&mut self) -> GLITCH_DET_INT_RAW_W { + GLITCH_DET_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 12 - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] + #[inline(always)] + #[must_use] + pub fn tx_brk_done_int_raw(&mut self) -> TX_BRK_DONE_INT_RAW_W { + TX_BRK_DONE_INT_RAW_W::new(self, 12) + } + #[doc = "Bit 13 - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] + #[inline(always)] + #[must_use] + pub fn tx_brk_idle_done_int_raw(&mut self) -> TX_BRK_IDLE_DONE_INT_RAW_W { + TX_BRK_IDLE_DONE_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 14 - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] + #[inline(always)] + #[must_use] + pub fn tx_done_int_raw(&mut self) -> TX_DONE_INT_RAW_W { + TX_DONE_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 18 - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] + #[inline(always)] + #[must_use] + pub fn at_cmd_char_det_int_raw(&mut self) -> AT_CMD_CHAR_DET_INT_RAW_W { + AT_CMD_CHAR_DET_INT_RAW_W::new(self, 18) + } + #[doc = "Bit 19 - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] + #[inline(always)] + #[must_use] + pub fn wakeup_int_raw(&mut self) -> WAKEUP_INT_RAW_W { + WAKEUP_INT_RAW_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0x02"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/lp_uart/int_st.rs b/esp32p4/src/lp_uart/int_st.rs new file mode 100644 index 0000000000..2cb8730f11 --- /dev/null +++ b/esp32p4/src/lp_uart/int_st.rs @@ -0,0 +1,215 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_FULL_INT_ST` reader - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."] +pub type RXFIFO_FULL_INT_ST_R = crate::BitReader; +#[doc = "Field `TXFIFO_EMPTY_INT_ST` reader - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."] +pub type TXFIFO_EMPTY_INT_ST_R = crate::BitReader; +#[doc = "Field `PARITY_ERR_INT_ST` reader - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."] +pub type PARITY_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `FRM_ERR_INT_ST` reader - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."] +pub type FRM_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_ST` reader - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."] +pub type RXFIFO_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `DSR_CHG_INT_ST` reader - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."] +pub type DSR_CHG_INT_ST_R = crate::BitReader; +#[doc = "Field `CTS_CHG_INT_ST` reader - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."] +pub type CTS_CHG_INT_ST_R = crate::BitReader; +#[doc = "Field `BRK_DET_INT_ST` reader - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."] +pub type BRK_DET_INT_ST_R = crate::BitReader; +#[doc = "Field `RXFIFO_TOUT_INT_ST` reader - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."] +pub type RXFIFO_TOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `SW_XON_INT_ST` reader - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."] +pub type SW_XON_INT_ST_R = crate::BitReader; +#[doc = "Field `SW_XOFF_INT_ST` reader - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."] +pub type SW_XOFF_INT_ST_R = crate::BitReader; +#[doc = "Field `GLITCH_DET_INT_ST` reader - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."] +pub type GLITCH_DET_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_BRK_DONE_INT_ST` reader - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."] +pub type TX_BRK_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_ST` reader - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."] +pub type TX_BRK_IDLE_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_DONE_INT_ST` reader - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."] +pub type TX_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `AT_CMD_CHAR_DET_INT_ST` reader - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."] +pub type AT_CMD_CHAR_DET_INT_ST_R = crate::BitReader; +#[doc = "Field `WAKEUP_INT_ST` reader - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."] +pub type WAKEUP_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."] + #[inline(always)] + pub fn rxfifo_full_int_st(&self) -> RXFIFO_FULL_INT_ST_R { + RXFIFO_FULL_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."] + #[inline(always)] + pub fn txfifo_empty_int_st(&self) -> TXFIFO_EMPTY_INT_ST_R { + TXFIFO_EMPTY_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."] + #[inline(always)] + pub fn parity_err_int_st(&self) -> PARITY_ERR_INT_ST_R { + PARITY_ERR_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."] + #[inline(always)] + pub fn frm_err_int_st(&self) -> FRM_ERR_INT_ST_R { + FRM_ERR_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."] + #[inline(always)] + pub fn rxfifo_ovf_int_st(&self) -> RXFIFO_OVF_INT_ST_R { + RXFIFO_OVF_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."] + #[inline(always)] + pub fn dsr_chg_int_st(&self) -> DSR_CHG_INT_ST_R { + DSR_CHG_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."] + #[inline(always)] + pub fn cts_chg_int_st(&self) -> CTS_CHG_INT_ST_R { + CTS_CHG_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."] + #[inline(always)] + pub fn brk_det_int_st(&self) -> BRK_DET_INT_ST_R { + BRK_DET_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."] + #[inline(always)] + pub fn rxfifo_tout_int_st(&self) -> RXFIFO_TOUT_INT_ST_R { + RXFIFO_TOUT_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."] + #[inline(always)] + pub fn sw_xon_int_st(&self) -> SW_XON_INT_ST_R { + SW_XON_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."] + #[inline(always)] + pub fn sw_xoff_int_st(&self) -> SW_XOFF_INT_ST_R { + SW_XOFF_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."] + #[inline(always)] + pub fn glitch_det_int_st(&self) -> GLITCH_DET_INT_ST_R { + GLITCH_DET_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."] + #[inline(always)] + pub fn tx_brk_done_int_st(&self) -> TX_BRK_DONE_INT_ST_R { + TX_BRK_DONE_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."] + #[inline(always)] + pub fn tx_brk_idle_done_int_st(&self) -> TX_BRK_IDLE_DONE_INT_ST_R { + TX_BRK_IDLE_DONE_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."] + #[inline(always)] + pub fn tx_done_int_st(&self) -> TX_DONE_INT_ST_R { + TX_DONE_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 18 - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."] + #[inline(always)] + pub fn at_cmd_char_det_int_st(&self) -> AT_CMD_CHAR_DET_INT_ST_R { + AT_CMD_CHAR_DET_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."] + #[inline(always)] + pub fn wakeup_int_st(&self) -> WAKEUP_INT_ST_R { + WAKEUP_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "rxfifo_full_int_st", + &format_args!("{}", self.rxfifo_full_int_st().bit()), + ) + .field( + "txfifo_empty_int_st", + &format_args!("{}", self.txfifo_empty_int_st().bit()), + ) + .field( + "parity_err_int_st", + &format_args!("{}", self.parity_err_int_st().bit()), + ) + .field( + "frm_err_int_st", + &format_args!("{}", self.frm_err_int_st().bit()), + ) + .field( + "rxfifo_ovf_int_st", + &format_args!("{}", self.rxfifo_ovf_int_st().bit()), + ) + .field( + "dsr_chg_int_st", + &format_args!("{}", self.dsr_chg_int_st().bit()), + ) + .field( + "cts_chg_int_st", + &format_args!("{}", self.cts_chg_int_st().bit()), + ) + .field( + "brk_det_int_st", + &format_args!("{}", self.brk_det_int_st().bit()), + ) + .field( + "rxfifo_tout_int_st", + &format_args!("{}", self.rxfifo_tout_int_st().bit()), + ) + .field( + "sw_xon_int_st", + &format_args!("{}", self.sw_xon_int_st().bit()), + ) + .field( + "sw_xoff_int_st", + &format_args!("{}", self.sw_xoff_int_st().bit()), + ) + .field( + "glitch_det_int_st", + &format_args!("{}", self.glitch_det_int_st().bit()), + ) + .field( + "tx_brk_done_int_st", + &format_args!("{}", self.tx_brk_done_int_st().bit()), + ) + .field( + "tx_brk_idle_done_int_st", + &format_args!("{}", self.tx_brk_idle_done_int_st().bit()), + ) + .field( + "tx_done_int_st", + &format_args!("{}", self.tx_done_int_st().bit()), + ) + .field( + "at_cmd_char_det_int_st", + &format_args!("{}", self.at_cmd_char_det_int_st().bit()), + ) + .field( + "wakeup_int_st", + &format_args!("{}", self.wakeup_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/mem_conf.rs b/esp32p4/src/lp_uart/mem_conf.rs new file mode 100644 index 0000000000..8982b26108 --- /dev/null +++ b/esp32p4/src/lp_uart/mem_conf.rs @@ -0,0 +1,85 @@ +#[doc = "Register `MEM_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `MEM_FORCE_PD` reader - Set this bit to force power down UART memory."] +pub type MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PD` writer - Set this bit to force power down UART memory."] +pub type MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_FORCE_PU` reader - Set this bit to force power up UART memory."] +pub type MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PU` writer - Set this bit to force power up UART memory."] +pub type MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 25 - Set this bit to force power down UART memory."] + #[inline(always)] + pub fn mem_force_pd(&self) -> MEM_FORCE_PD_R { + MEM_FORCE_PD_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to force power up UART memory."] + #[inline(always)] + pub fn mem_force_pu(&self) -> MEM_FORCE_PU_R { + MEM_FORCE_PU_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_CONF") + .field( + "mem_force_pd", + &format_args!("{}", self.mem_force_pd().bit()), + ) + .field( + "mem_force_pu", + &format_args!("{}", self.mem_force_pu().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 25 - Set this bit to force power down UART memory."] + #[inline(always)] + #[must_use] + pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W { + MEM_FORCE_PD_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to force power up UART memory."] + #[inline(always)] + #[must_use] + pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W { + MEM_FORCE_PU_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART memory power configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_CONF_SPEC; +impl crate::RegisterSpec for MEM_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_conf::R`](R) reader structure"] +impl crate::Readable for MEM_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_conf::W`](W) writer structure"] +impl crate::Writable for MEM_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_CONF to value 0"] +impl crate::Resettable for MEM_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/mem_rx_status.rs b/esp32p4/src/lp_uart/mem_rx_status.rs new file mode 100644 index 0000000000..983d36364e --- /dev/null +++ b/esp32p4/src/lp_uart/mem_rx_status.rs @@ -0,0 +1,50 @@ +#[doc = "Register `MEM_RX_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `RX_SRAM_RADDR` reader - This register stores the offset read address in RX-SRAM."] +pub type RX_SRAM_RADDR_R = crate::FieldReader; +#[doc = "Field `RX_SRAM_WADDR` reader - This register stores the offset write address in Rx-SRAM."] +pub type RX_SRAM_WADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 3:7 - This register stores the offset read address in RX-SRAM."] + #[inline(always)] + pub fn rx_sram_raddr(&self) -> RX_SRAM_RADDR_R { + RX_SRAM_RADDR_R::new(((self.bits >> 3) & 0x1f) as u8) + } + #[doc = "Bits 12:16 - This register stores the offset write address in Rx-SRAM."] + #[inline(always)] + pub fn rx_sram_waddr(&self) -> RX_SRAM_WADDR_R { + RX_SRAM_WADDR_R::new(((self.bits >> 12) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_RX_STATUS") + .field( + "rx_sram_raddr", + &format_args!("{}", self.rx_sram_raddr().bits()), + ) + .field( + "rx_sram_waddr", + &format_args!("{}", self.rx_sram_waddr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_RX_STATUS_SPEC; +impl crate::RegisterSpec for MEM_RX_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_rx_status::R`](R) reader structure"] +impl crate::Readable for MEM_RX_STATUS_SPEC {} +#[doc = "`reset()` method sets MEM_RX_STATUS to value 0x0001_0080"] +impl crate::Resettable for MEM_RX_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0080; +} diff --git a/esp32p4/src/lp_uart/mem_tx_status.rs b/esp32p4/src/lp_uart/mem_tx_status.rs new file mode 100644 index 0000000000..69a148eae9 --- /dev/null +++ b/esp32p4/src/lp_uart/mem_tx_status.rs @@ -0,0 +1,50 @@ +#[doc = "Register `MEM_TX_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `TX_SRAM_WADDR` reader - This register stores the offset write address in Tx-SRAM."] +pub type TX_SRAM_WADDR_R = crate::FieldReader; +#[doc = "Field `TX_SRAM_RADDR` reader - This register stores the offset read address in Tx-SRAM."] +pub type TX_SRAM_RADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 3:7 - This register stores the offset write address in Tx-SRAM."] + #[inline(always)] + pub fn tx_sram_waddr(&self) -> TX_SRAM_WADDR_R { + TX_SRAM_WADDR_R::new(((self.bits >> 3) & 0x1f) as u8) + } + #[doc = "Bits 12:16 - This register stores the offset read address in Tx-SRAM."] + #[inline(always)] + pub fn tx_sram_raddr(&self) -> TX_SRAM_RADDR_R { + TX_SRAM_RADDR_R::new(((self.bits >> 12) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_TX_STATUS") + .field( + "tx_sram_waddr", + &format_args!("{}", self.tx_sram_waddr().bits()), + ) + .field( + "tx_sram_raddr", + &format_args!("{}", self.tx_sram_raddr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_TX_STATUS_SPEC; +impl crate::RegisterSpec for MEM_TX_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_tx_status::R`](R) reader structure"] +impl crate::Readable for MEM_TX_STATUS_SPEC {} +#[doc = "`reset()` method sets MEM_TX_STATUS to value 0"] +impl crate::Resettable for MEM_TX_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/reg_update.rs b/esp32p4/src/lp_uart/reg_update.rs new file mode 100644 index 0000000000..c74dde8a5f --- /dev/null +++ b/esp32p4/src/lp_uart/reg_update.rs @@ -0,0 +1,63 @@ +#[doc = "Register `REG_UPDATE` reader"] +pub type R = crate::R; +#[doc = "Register `REG_UPDATE` writer"] +pub type W = crate::W; +#[doc = "Field `REG_UPDATE` reader - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."] +pub type REG_UPDATE_R = crate::BitReader; +#[doc = "Field `REG_UPDATE` writer - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."] +pub type REG_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."] + #[inline(always)] + pub fn reg_update(&self) -> REG_UPDATE_R { + REG_UPDATE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_UPDATE") + .field("reg_update", &format_args!("{}", self.reg_update().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."] + #[inline(always)] + #[must_use] + pub fn reg_update(&mut self) -> REG_UPDATE_W { + REG_UPDATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART Registers Configuration Update register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_update::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_update::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_UPDATE_SPEC; +impl crate::RegisterSpec for REG_UPDATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_update::R`](R) reader structure"] +impl crate::Readable for REG_UPDATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_update::W`](W) writer structure"] +impl crate::Writable for REG_UPDATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_UPDATE to value 0"] +impl crate::Resettable for REG_UPDATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/rs485_conf_sync.rs b/esp32p4/src/lp_uart/rs485_conf_sync.rs new file mode 100644 index 0000000000..68ffb745b8 --- /dev/null +++ b/esp32p4/src/lp_uart/rs485_conf_sync.rs @@ -0,0 +1,79 @@ +#[doc = "Register `RS485_CONF_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `RS485_CONF_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `DL0_EN` reader - Set this bit to delay the stop bit by 1 bit."] +pub type DL0_EN_R = crate::BitReader; +#[doc = "Field `DL0_EN` writer - Set this bit to delay the stop bit by 1 bit."] +pub type DL0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DL1_EN` reader - Set this bit to delay the stop bit by 1 bit."] +pub type DL1_EN_R = crate::BitReader; +#[doc = "Field `DL1_EN` writer - Set this bit to delay the stop bit by 1 bit."] +pub type DL1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Set this bit to delay the stop bit by 1 bit."] + #[inline(always)] + pub fn dl0_en(&self) -> DL0_EN_R { + DL0_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to delay the stop bit by 1 bit."] + #[inline(always)] + pub fn dl1_en(&self) -> DL1_EN_R { + DL1_EN_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RS485_CONF_SYNC") + .field("dl0_en", &format_args!("{}", self.dl0_en().bit())) + .field("dl1_en", &format_args!("{}", self.dl1_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 1 - Set this bit to delay the stop bit by 1 bit."] + #[inline(always)] + #[must_use] + pub fn dl0_en(&mut self) -> DL0_EN_W { + DL0_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to delay the stop bit by 1 bit."] + #[inline(always)] + #[must_use] + pub fn dl1_en(&mut self) -> DL1_EN_W { + DL1_EN_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RS485 mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rs485_conf_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rs485_conf_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RS485_CONF_SYNC_SPEC; +impl crate::RegisterSpec for RS485_CONF_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rs485_conf_sync::R`](R) reader structure"] +impl crate::Readable for RS485_CONF_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rs485_conf_sync::W`](W) writer structure"] +impl crate::Writable for RS485_CONF_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RS485_CONF_SYNC to value 0"] +impl crate::Resettable for RS485_CONF_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/rx_filt.rs b/esp32p4/src/lp_uart/rx_filt.rs new file mode 100644 index 0000000000..ec984971fc --- /dev/null +++ b/esp32p4/src/lp_uart/rx_filt.rs @@ -0,0 +1,85 @@ +#[doc = "Register `RX_FILT` reader"] +pub type R = crate::R; +#[doc = "Register `RX_FILT` writer"] +pub type W = crate::W; +#[doc = "Field `GLITCH_FILT` reader - when input pulse width is lower than this value the pulse is ignored."] +pub type GLITCH_FILT_R = crate::FieldReader; +#[doc = "Field `GLITCH_FILT` writer - when input pulse width is lower than this value the pulse is ignored."] +pub type GLITCH_FILT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GLITCH_FILT_EN` reader - Set this bit to enable Rx signal filter."] +pub type GLITCH_FILT_EN_R = crate::BitReader; +#[doc = "Field `GLITCH_FILT_EN` writer - Set this bit to enable Rx signal filter."] +pub type GLITCH_FILT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."] + #[inline(always)] + pub fn glitch_filt(&self) -> GLITCH_FILT_R { + GLITCH_FILT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - Set this bit to enable Rx signal filter."] + #[inline(always)] + pub fn glitch_filt_en(&self) -> GLITCH_FILT_EN_R { + GLITCH_FILT_EN_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_FILT") + .field( + "glitch_filt", + &format_args!("{}", self.glitch_filt().bits()), + ) + .field( + "glitch_filt_en", + &format_args!("{}", self.glitch_filt_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."] + #[inline(always)] + #[must_use] + pub fn glitch_filt(&mut self) -> GLITCH_FILT_W { + GLITCH_FILT_W::new(self, 0) + } + #[doc = "Bit 8 - Set this bit to enable Rx signal filter."] + #[inline(always)] + #[must_use] + pub fn glitch_filt_en(&mut self) -> GLITCH_FILT_EN_W { + GLITCH_FILT_EN_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Rx Filter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_filt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_filt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_FILT_SPEC; +impl crate::RegisterSpec for RX_FILT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_filt::R`](R) reader structure"] +impl crate::Readable for RX_FILT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_filt::W`](W) writer structure"] +impl crate::Writable for RX_FILT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_FILT to value 0x08"] +impl crate::Resettable for RX_FILT_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/lp_uart/sleep_conf0.rs b/esp32p4/src/lp_uart/sleep_conf0.rs new file mode 100644 index 0000000000..e867f2b351 --- /dev/null +++ b/esp32p4/src/lp_uart/sleep_conf0.rs @@ -0,0 +1,111 @@ +#[doc = "Register `SLEEP_CONF0` reader"] +pub type R = crate::R; +#[doc = "Register `SLEEP_CONF0` writer"] +pub type W = crate::W; +#[doc = "Field `WK_CHAR1` reader - This register restores the specified wake up char1 to wake up"] +pub type WK_CHAR1_R = crate::FieldReader; +#[doc = "Field `WK_CHAR1` writer - This register restores the specified wake up char1 to wake up"] +pub type WK_CHAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WK_CHAR2` reader - This register restores the specified wake up char2 to wake up"] +pub type WK_CHAR2_R = crate::FieldReader; +#[doc = "Field `WK_CHAR2` writer - This register restores the specified wake up char2 to wake up"] +pub type WK_CHAR2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WK_CHAR3` reader - This register restores the specified wake up char3 to wake up"] +pub type WK_CHAR3_R = crate::FieldReader; +#[doc = "Field `WK_CHAR3` writer - This register restores the specified wake up char3 to wake up"] +pub type WK_CHAR3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WK_CHAR4` reader - This register restores the specified wake up char4 to wake up"] +pub type WK_CHAR4_R = crate::FieldReader; +#[doc = "Field `WK_CHAR4` writer - This register restores the specified wake up char4 to wake up"] +pub type WK_CHAR4_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This register restores the specified wake up char1 to wake up"] + #[inline(always)] + pub fn wk_char1(&self) -> WK_CHAR1_R { + WK_CHAR1_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - This register restores the specified wake up char2 to wake up"] + #[inline(always)] + pub fn wk_char2(&self) -> WK_CHAR2_R { + WK_CHAR2_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - This register restores the specified wake up char3 to wake up"] + #[inline(always)] + pub fn wk_char3(&self) -> WK_CHAR3_R { + WK_CHAR3_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - This register restores the specified wake up char4 to wake up"] + #[inline(always)] + pub fn wk_char4(&self) -> WK_CHAR4_R { + WK_CHAR4_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLEEP_CONF0") + .field("wk_char1", &format_args!("{}", self.wk_char1().bits())) + .field("wk_char2", &format_args!("{}", self.wk_char2().bits())) + .field("wk_char3", &format_args!("{}", self.wk_char3().bits())) + .field("wk_char4", &format_args!("{}", self.wk_char4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register restores the specified wake up char1 to wake up"] + #[inline(always)] + #[must_use] + pub fn wk_char1(&mut self) -> WK_CHAR1_W { + WK_CHAR1_W::new(self, 0) + } + #[doc = "Bits 8:15 - This register restores the specified wake up char2 to wake up"] + #[inline(always)] + #[must_use] + pub fn wk_char2(&mut self) -> WK_CHAR2_W { + WK_CHAR2_W::new(self, 8) + } + #[doc = "Bits 16:23 - This register restores the specified wake up char3 to wake up"] + #[inline(always)] + #[must_use] + pub fn wk_char3(&mut self) -> WK_CHAR3_W { + WK_CHAR3_W::new(self, 16) + } + #[doc = "Bits 24:31 - This register restores the specified wake up char4 to wake up"] + #[inline(always)] + #[must_use] + pub fn wk_char4(&mut self) -> WK_CHAR4_W { + WK_CHAR4_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART sleep configure register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLEEP_CONF0_SPEC; +impl crate::RegisterSpec for SLEEP_CONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sleep_conf0::R`](R) reader structure"] +impl crate::Readable for SLEEP_CONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sleep_conf0::W`](W) writer structure"] +impl crate::Writable for SLEEP_CONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLEEP_CONF0 to value 0"] +impl crate::Resettable for SLEEP_CONF0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/sleep_conf1.rs b/esp32p4/src/lp_uart/sleep_conf1.rs new file mode 100644 index 0000000000..27d56da2c5 --- /dev/null +++ b/esp32p4/src/lp_uart/sleep_conf1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SLEEP_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `SLEEP_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `WK_CHAR0` reader - This register restores the specified char0 to wake up"] +pub type WK_CHAR0_R = crate::FieldReader; +#[doc = "Field `WK_CHAR0` writer - This register restores the specified char0 to wake up"] +pub type WK_CHAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This register restores the specified char0 to wake up"] + #[inline(always)] + pub fn wk_char0(&self) -> WK_CHAR0_R { + WK_CHAR0_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLEEP_CONF1") + .field("wk_char0", &format_args!("{}", self.wk_char0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register restores the specified char0 to wake up"] + #[inline(always)] + #[must_use] + pub fn wk_char0(&mut self) -> WK_CHAR0_W { + WK_CHAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART sleep configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLEEP_CONF1_SPEC; +impl crate::RegisterSpec for SLEEP_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sleep_conf1::R`](R) reader structure"] +impl crate::Readable for SLEEP_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sleep_conf1::W`](W) writer structure"] +impl crate::Writable for SLEEP_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLEEP_CONF1 to value 0"] +impl crate::Resettable for SLEEP_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_uart/sleep_conf2.rs b/esp32p4/src/lp_uart/sleep_conf2.rs new file mode 100644 index 0000000000..854088c068 --- /dev/null +++ b/esp32p4/src/lp_uart/sleep_conf2.rs @@ -0,0 +1,142 @@ +#[doc = "Register `SLEEP_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `SLEEP_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `ACTIVE_THRESHOLD` reader - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."] +pub type ACTIVE_THRESHOLD_R = crate::FieldReader; +#[doc = "Field `ACTIVE_THRESHOLD` writer - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."] +pub type ACTIVE_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `RX_WAKE_UP_THRHD` reader - In wake up mode 1 this field is used to set the received data number threshold to wake up chip."] +pub type RX_WAKE_UP_THRHD_R = crate::FieldReader; +#[doc = "Field `RX_WAKE_UP_THRHD` writer - In wake up mode 1 this field is used to set the received data number threshold to wake up chip."] +pub type RX_WAKE_UP_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `WK_CHAR_NUM` reader - This register is used to select number of wake up char."] +pub type WK_CHAR_NUM_R = crate::FieldReader; +#[doc = "Field `WK_CHAR_NUM` writer - This register is used to select number of wake up char."] +pub type WK_CHAR_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WK_CHAR_MASK` reader - This register is used to mask wake up char."] +pub type WK_CHAR_MASK_R = crate::FieldReader; +#[doc = "Field `WK_CHAR_MASK` writer - This register is used to mask wake up char."] +pub type WK_CHAR_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `WK_MODE_SEL` reader - This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than"] +pub type WK_MODE_SEL_R = crate::FieldReader; +#[doc = "Field `WK_MODE_SEL` writer - This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than"] +pub type WK_MODE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."] + #[inline(always)] + pub fn active_threshold(&self) -> ACTIVE_THRESHOLD_R { + ACTIVE_THRESHOLD_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 13:17 - In wake up mode 1 this field is used to set the received data number threshold to wake up chip."] + #[inline(always)] + pub fn rx_wake_up_thrhd(&self) -> RX_WAKE_UP_THRHD_R { + RX_WAKE_UP_THRHD_R::new(((self.bits >> 13) & 0x1f) as u8) + } + #[doc = "Bits 18:20 - This register is used to select number of wake up char."] + #[inline(always)] + pub fn wk_char_num(&self) -> WK_CHAR_NUM_R { + WK_CHAR_NUM_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:25 - This register is used to mask wake up char."] + #[inline(always)] + pub fn wk_char_mask(&self) -> WK_CHAR_MASK_R { + WK_CHAR_MASK_R::new(((self.bits >> 21) & 0x1f) as u8) + } + #[doc = "Bits 26:27 - This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than"] + #[inline(always)] + pub fn wk_mode_sel(&self) -> WK_MODE_SEL_R { + WK_MODE_SEL_R::new(((self.bits >> 26) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLEEP_CONF2") + .field( + "active_threshold", + &format_args!("{}", self.active_threshold().bits()), + ) + .field( + "rx_wake_up_thrhd", + &format_args!("{}", self.rx_wake_up_thrhd().bits()), + ) + .field( + "wk_char_num", + &format_args!("{}", self.wk_char_num().bits()), + ) + .field( + "wk_char_mask", + &format_args!("{}", self.wk_char_mask().bits()), + ) + .field( + "wk_mode_sel", + &format_args!("{}", self.wk_mode_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."] + #[inline(always)] + #[must_use] + pub fn active_threshold(&mut self) -> ACTIVE_THRESHOLD_W { + ACTIVE_THRESHOLD_W::new(self, 0) + } + #[doc = "Bits 13:17 - In wake up mode 1 this field is used to set the received data number threshold to wake up chip."] + #[inline(always)] + #[must_use] + pub fn rx_wake_up_thrhd(&mut self) -> RX_WAKE_UP_THRHD_W { + RX_WAKE_UP_THRHD_W::new(self, 13) + } + #[doc = "Bits 18:20 - This register is used to select number of wake up char."] + #[inline(always)] + #[must_use] + pub fn wk_char_num(&mut self) -> WK_CHAR_NUM_W { + WK_CHAR_NUM_W::new(self, 18) + } + #[doc = "Bits 21:25 - This register is used to mask wake up char."] + #[inline(always)] + #[must_use] + pub fn wk_char_mask(&mut self) -> WK_CHAR_MASK_W { + WK_CHAR_MASK_W::new(self, 21) + } + #[doc = "Bits 26:27 - This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than"] + #[inline(always)] + #[must_use] + pub fn wk_mode_sel(&mut self) -> WK_MODE_SEL_W { + WK_MODE_SEL_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART sleep configure register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLEEP_CONF2_SPEC; +impl crate::RegisterSpec for SLEEP_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sleep_conf2::R`](R) reader structure"] +impl crate::Readable for SLEEP_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sleep_conf2::W`](W) writer structure"] +impl crate::Writable for SLEEP_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLEEP_CONF2 to value 0x0014_20f0"] +impl crate::Resettable for SLEEP_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0x0014_20f0; +} diff --git a/esp32p4/src/lp_uart/status.rs b/esp32p4/src/lp_uart/status.rs new file mode 100644 index 0000000000..3529393c5e --- /dev/null +++ b/esp32p4/src/lp_uart/status.rs @@ -0,0 +1,92 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_CNT` reader - Stores the byte number of valid data in Rx-FIFO."] +pub type RXFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `DSRN` reader - The register represent the level value of the internal uart dsr signal."] +pub type DSRN_R = crate::BitReader; +#[doc = "Field `CTSN` reader - This register represent the level value of the internal uart cts signal."] +pub type CTSN_R = crate::BitReader; +#[doc = "Field `RXD` reader - This register represent the level value of the internal uart rxd signal."] +pub type RXD_R = crate::BitReader; +#[doc = "Field `TXFIFO_CNT` reader - Stores the byte number of data in Tx-FIFO."] +pub type TXFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `DTRN` reader - This bit represents the level of the internal uart dtr signal."] +pub type DTRN_R = crate::BitReader; +#[doc = "Field `RTSN` reader - This bit represents the level of the internal uart rts signal."] +pub type RTSN_R = crate::BitReader; +#[doc = "Field `TXD` reader - This bit represents the level of the internal uart txd signal."] +pub type TXD_R = crate::BitReader; +impl R { + #[doc = "Bits 3:7 - Stores the byte number of valid data in Rx-FIFO."] + #[inline(always)] + pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R { + RXFIFO_CNT_R::new(((self.bits >> 3) & 0x1f) as u8) + } + #[doc = "Bit 13 - The register represent the level value of the internal uart dsr signal."] + #[inline(always)] + pub fn dsrn(&self) -> DSRN_R { + DSRN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - This register represent the level value of the internal uart cts signal."] + #[inline(always)] + pub fn ctsn(&self) -> CTSN_R { + CTSN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - This register represent the level value of the internal uart rxd signal."] + #[inline(always)] + pub fn rxd(&self) -> RXD_R { + RXD_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 19:23 - Stores the byte number of data in Tx-FIFO."] + #[inline(always)] + pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R { + TXFIFO_CNT_R::new(((self.bits >> 19) & 0x1f) as u8) + } + #[doc = "Bit 29 - This bit represents the level of the internal uart dtr signal."] + #[inline(always)] + pub fn dtrn(&self) -> DTRN_R { + DTRN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - This bit represents the level of the internal uart rts signal."] + #[inline(always)] + pub fn rtsn(&self) -> RTSN_R { + RTSN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - This bit represents the level of the internal uart txd signal."] + #[inline(always)] + pub fn txd(&self) -> TXD_R { + TXD_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits())) + .field("dsrn", &format_args!("{}", self.dsrn().bit())) + .field("ctsn", &format_args!("{}", self.ctsn().bit())) + .field("rxd", &format_args!("{}", self.rxd().bit())) + .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits())) + .field("dtrn", &format_args!("{}", self.dtrn().bit())) + .field("rtsn", &format_args!("{}", self.rtsn().bit())) + .field("txd", &format_args!("{}", self.txd().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`reset()` method sets STATUS to value 0xe000_c000"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0xe000_c000; +} diff --git a/esp32p4/src/lp_uart/swfc_conf0_sync.rs b/esp32p4/src/lp_uart/swfc_conf0_sync.rs new file mode 100644 index 0000000000..60cada4167 --- /dev/null +++ b/esp32p4/src/lp_uart/swfc_conf0_sync.rs @@ -0,0 +1,197 @@ +#[doc = "Register `SWFC_CONF0_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `SWFC_CONF0_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `XON_CHAR` reader - This register stores the Xon flow control char."] +pub type XON_CHAR_R = crate::FieldReader; +#[doc = "Field `XON_CHAR` writer - This register stores the Xon flow control char."] +pub type XON_CHAR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `XOFF_CHAR` reader - This register stores the Xoff flow control char."] +pub type XOFF_CHAR_R = crate::FieldReader; +#[doc = "Field `XOFF_CHAR` writer - This register stores the Xoff flow control char."] +pub type XOFF_CHAR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `XON_XOFF_STILL_SEND` reader - In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled."] +pub type XON_XOFF_STILL_SEND_R = crate::BitReader; +#[doc = "Field `XON_XOFF_STILL_SEND` writer - In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled."] +pub type XON_XOFF_STILL_SEND_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_FLOW_CON_EN` reader - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."] +pub type SW_FLOW_CON_EN_R = crate::BitReader; +#[doc = "Field `SW_FLOW_CON_EN` writer - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."] +pub type SW_FLOW_CON_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XONOFF_DEL` reader - Set this bit to remove flow control char from the received data."] +pub type XONOFF_DEL_R = crate::BitReader; +#[doc = "Field `XONOFF_DEL` writer - Set this bit to remove flow control char from the received data."] +pub type XONOFF_DEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_XON` reader - Set this bit to enable the transmitter to go on sending data."] +pub type FORCE_XON_R = crate::BitReader; +#[doc = "Field `FORCE_XON` writer - Set this bit to enable the transmitter to go on sending data."] +pub type FORCE_XON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_XOFF` reader - Set this bit to stop the transmitter from sending data."] +pub type FORCE_XOFF_R = crate::BitReader; +#[doc = "Field `FORCE_XOFF` writer - Set this bit to stop the transmitter from sending data."] +pub type FORCE_XOFF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_XON` reader - Set this bit to send Xon char. It is cleared by hardware automatically."] +pub type SEND_XON_R = crate::BitReader; +#[doc = "Field `SEND_XON` writer - Set this bit to send Xon char. It is cleared by hardware automatically."] +pub type SEND_XON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_XOFF` reader - Set this bit to send Xoff char. It is cleared by hardware automatically."] +pub type SEND_XOFF_R = crate::BitReader; +#[doc = "Field `SEND_XOFF` writer - Set this bit to send Xoff char. It is cleared by hardware automatically."] +pub type SEND_XOFF_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - This register stores the Xon flow control char."] + #[inline(always)] + pub fn xon_char(&self) -> XON_CHAR_R { + XON_CHAR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - This register stores the Xoff flow control char."] + #[inline(always)] + pub fn xoff_char(&self) -> XOFF_CHAR_R { + XOFF_CHAR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 16 - In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled."] + #[inline(always)] + pub fn xon_xoff_still_send(&self) -> XON_XOFF_STILL_SEND_R { + XON_XOFF_STILL_SEND_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."] + #[inline(always)] + pub fn sw_flow_con_en(&self) -> SW_FLOW_CON_EN_R { + SW_FLOW_CON_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Set this bit to remove flow control char from the received data."] + #[inline(always)] + pub fn xonoff_del(&self) -> XONOFF_DEL_R { + XONOFF_DEL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Set this bit to enable the transmitter to go on sending data."] + #[inline(always)] + pub fn force_xon(&self) -> FORCE_XON_R { + FORCE_XON_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Set this bit to stop the transmitter from sending data."] + #[inline(always)] + pub fn force_xoff(&self) -> FORCE_XOFF_R { + FORCE_XOFF_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to send Xon char. It is cleared by hardware automatically."] + #[inline(always)] + pub fn send_xon(&self) -> SEND_XON_R { + SEND_XON_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to send Xoff char. It is cleared by hardware automatically."] + #[inline(always)] + pub fn send_xoff(&self) -> SEND_XOFF_R { + SEND_XOFF_R::new(((self.bits >> 22) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SWFC_CONF0_SYNC") + .field("xon_char", &format_args!("{}", self.xon_char().bits())) + .field("xoff_char", &format_args!("{}", self.xoff_char().bits())) + .field( + "xon_xoff_still_send", + &format_args!("{}", self.xon_xoff_still_send().bit()), + ) + .field( + "sw_flow_con_en", + &format_args!("{}", self.sw_flow_con_en().bit()), + ) + .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit())) + .field("force_xon", &format_args!("{}", self.force_xon().bit())) + .field("force_xoff", &format_args!("{}", self.force_xoff().bit())) + .field("send_xon", &format_args!("{}", self.send_xon().bit())) + .field("send_xoff", &format_args!("{}", self.send_xoff().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register stores the Xon flow control char."] + #[inline(always)] + #[must_use] + pub fn xon_char(&mut self) -> XON_CHAR_W { + XON_CHAR_W::new(self, 0) + } + #[doc = "Bits 8:15 - This register stores the Xoff flow control char."] + #[inline(always)] + #[must_use] + pub fn xoff_char(&mut self) -> XOFF_CHAR_W { + XOFF_CHAR_W::new(self, 8) + } + #[doc = "Bit 16 - In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled."] + #[inline(always)] + #[must_use] + pub fn xon_xoff_still_send(&mut self) -> XON_XOFF_STILL_SEND_W { + XON_XOFF_STILL_SEND_W::new(self, 16) + } + #[doc = "Bit 17 - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."] + #[inline(always)] + #[must_use] + pub fn sw_flow_con_en(&mut self) -> SW_FLOW_CON_EN_W { + SW_FLOW_CON_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Set this bit to remove flow control char from the received data."] + #[inline(always)] + #[must_use] + pub fn xonoff_del(&mut self) -> XONOFF_DEL_W { + XONOFF_DEL_W::new(self, 18) + } + #[doc = "Bit 19 - Set this bit to enable the transmitter to go on sending data."] + #[inline(always)] + #[must_use] + pub fn force_xon(&mut self) -> FORCE_XON_W { + FORCE_XON_W::new(self, 19) + } + #[doc = "Bit 20 - Set this bit to stop the transmitter from sending data."] + #[inline(always)] + #[must_use] + pub fn force_xoff(&mut self) -> FORCE_XOFF_W { + FORCE_XOFF_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to send Xon char. It is cleared by hardware automatically."] + #[inline(always)] + #[must_use] + pub fn send_xon(&mut self) -> SEND_XON_W { + SEND_XON_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to send Xoff char. It is cleared by hardware automatically."] + #[inline(always)] + #[must_use] + pub fn send_xoff(&mut self) -> SEND_XOFF_W { + SEND_XOFF_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Software flow-control character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swfc_conf0_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swfc_conf0_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SWFC_CONF0_SYNC_SPEC; +impl crate::RegisterSpec for SWFC_CONF0_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`swfc_conf0_sync::R`](R) reader structure"] +impl crate::Readable for SWFC_CONF0_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`swfc_conf0_sync::W`](W) writer structure"] +impl crate::Writable for SWFC_CONF0_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SWFC_CONF0_SYNC to value 0x1311"] +impl crate::Resettable for SWFC_CONF0_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x1311; +} diff --git a/esp32p4/src/lp_uart/swfc_conf1.rs b/esp32p4/src/lp_uart/swfc_conf1.rs new file mode 100644 index 0000000000..addd9ab57c --- /dev/null +++ b/esp32p4/src/lp_uart/swfc_conf1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SWFC_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `SWFC_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `XON_THRESHOLD` reader - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."] +pub type XON_THRESHOLD_R = crate::FieldReader; +#[doc = "Field `XON_THRESHOLD` writer - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."] +pub type XON_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `XOFF_THRESHOLD` reader - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char."] +pub type XOFF_THRESHOLD_R = crate::FieldReader; +#[doc = "Field `XOFF_THRESHOLD` writer - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char."] +pub type XOFF_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 3:7 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."] + #[inline(always)] + pub fn xon_threshold(&self) -> XON_THRESHOLD_R { + XON_THRESHOLD_R::new(((self.bits >> 3) & 0x1f) as u8) + } + #[doc = "Bits 11:15 - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char."] + #[inline(always)] + pub fn xoff_threshold(&self) -> XOFF_THRESHOLD_R { + XOFF_THRESHOLD_R::new(((self.bits >> 11) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SWFC_CONF1") + .field( + "xon_threshold", + &format_args!("{}", self.xon_threshold().bits()), + ) + .field( + "xoff_threshold", + &format_args!("{}", self.xoff_threshold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 3:7 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."] + #[inline(always)] + #[must_use] + pub fn xon_threshold(&mut self) -> XON_THRESHOLD_W { + XON_THRESHOLD_W::new(self, 3) + } + #[doc = "Bits 11:15 - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char."] + #[inline(always)] + #[must_use] + pub fn xoff_threshold(&mut self) -> XOFF_THRESHOLD_W { + XOFF_THRESHOLD_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Software flow-control character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swfc_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swfc_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SWFC_CONF1_SPEC; +impl crate::RegisterSpec for SWFC_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`swfc_conf1::R`](R) reader structure"] +impl crate::Readable for SWFC_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`swfc_conf1::W`](W) writer structure"] +impl crate::Writable for SWFC_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SWFC_CONF1 to value 0x6000"] +impl crate::Resettable for SWFC_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x6000; +} diff --git a/esp32p4/src/lp_uart/tout_conf_sync.rs b/esp32p4/src/lp_uart/tout_conf_sync.rs new file mode 100644 index 0000000000..f182983145 --- /dev/null +++ b/esp32p4/src/lp_uart/tout_conf_sync.rs @@ -0,0 +1,101 @@ +#[doc = "Register `TOUT_CONF_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `TOUT_CONF_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `RX_TOUT_EN` reader - This is the enble bit for uart receiver's timeout function."] +pub type RX_TOUT_EN_R = crate::BitReader; +#[doc = "Field `RX_TOUT_EN` writer - This is the enble bit for uart receiver's timeout function."] +pub type RX_TOUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TOUT_FLOW_DIS` reader - Set this bit to stop accumulating idle_cnt when hardware flow control works."] +pub type RX_TOUT_FLOW_DIS_R = crate::BitReader; +#[doc = "Field `RX_TOUT_FLOW_DIS` writer - Set this bit to stop accumulating idle_cnt when hardware flow control works."] +pub type RX_TOUT_FLOW_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TOUT_THRHD` reader - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."] +pub type RX_TOUT_THRHD_R = crate::FieldReader; +#[doc = "Field `RX_TOUT_THRHD` writer - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."] +pub type RX_TOUT_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bit 0 - This is the enble bit for uart receiver's timeout function."] + #[inline(always)] + pub fn rx_tout_en(&self) -> RX_TOUT_EN_R { + RX_TOUT_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to stop accumulating idle_cnt when hardware flow control works."] + #[inline(always)] + pub fn rx_tout_flow_dis(&self) -> RX_TOUT_FLOW_DIS_R { + RX_TOUT_FLOW_DIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:11 - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."] + #[inline(always)] + pub fn rx_tout_thrhd(&self) -> RX_TOUT_THRHD_R { + RX_TOUT_THRHD_R::new(((self.bits >> 2) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TOUT_CONF_SYNC") + .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit())) + .field( + "rx_tout_flow_dis", + &format_args!("{}", self.rx_tout_flow_dis().bit()), + ) + .field( + "rx_tout_thrhd", + &format_args!("{}", self.rx_tout_thrhd().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This is the enble bit for uart receiver's timeout function."] + #[inline(always)] + #[must_use] + pub fn rx_tout_en(&mut self) -> RX_TOUT_EN_W { + RX_TOUT_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to stop accumulating idle_cnt when hardware flow control works."] + #[inline(always)] + #[must_use] + pub fn rx_tout_flow_dis(&mut self) -> RX_TOUT_FLOW_DIS_W { + RX_TOUT_FLOW_DIS_W::new(self, 1) + } + #[doc = "Bits 2:11 - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."] + #[inline(always)] + #[must_use] + pub fn rx_tout_thrhd(&mut self) -> RX_TOUT_THRHD_W { + RX_TOUT_THRHD_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART threshold and allocation configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tout_conf_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tout_conf_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TOUT_CONF_SYNC_SPEC; +impl crate::RegisterSpec for TOUT_CONF_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tout_conf_sync::R`](R) reader structure"] +impl crate::Readable for TOUT_CONF_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tout_conf_sync::W`](W) writer structure"] +impl crate::Writable for TOUT_CONF_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TOUT_CONF_SYNC to value 0x28"] +impl crate::Resettable for TOUT_CONF_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x28; +} diff --git a/esp32p4/src/lp_uart/txbrk_conf_sync.rs b/esp32p4/src/lp_uart/txbrk_conf_sync.rs new file mode 100644 index 0000000000..8589787271 --- /dev/null +++ b/esp32p4/src/lp_uart/txbrk_conf_sync.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TXBRK_CONF_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `TXBRK_CONF_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `TX_BRK_NUM` reader - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."] +pub type TX_BRK_NUM_R = crate::FieldReader; +#[doc = "Field `TX_BRK_NUM` writer - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."] +pub type TX_BRK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."] + #[inline(always)] + pub fn tx_brk_num(&self) -> TX_BRK_NUM_R { + TX_BRK_NUM_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TXBRK_CONF_SYNC") + .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."] + #[inline(always)] + #[must_use] + pub fn tx_brk_num(&mut self) -> TX_BRK_NUM_W { + TX_BRK_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tx Break character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbrk_conf_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbrk_conf_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TXBRK_CONF_SYNC_SPEC; +impl crate::RegisterSpec for TXBRK_CONF_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`txbrk_conf_sync::R`](R) reader structure"] +impl crate::Readable for TXBRK_CONF_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txbrk_conf_sync::W`](W) writer structure"] +impl crate::Writable for TXBRK_CONF_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TXBRK_CONF_SYNC to value 0x0a"] +impl crate::Resettable for TXBRK_CONF_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x0a; +} diff --git a/esp32p4/src/lp_wdt.rs b/esp32p4/src/lp_wdt.rs new file mode 100644 index 0000000000..ee0067b7f5 --- /dev/null +++ b/esp32p4/src/lp_wdt.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + config0: CONFIG0, + config1: CONFIG1, + config2: CONFIG2, + config3: CONFIG3, + config4: CONFIG4, + feed: FEED, + wprotect: WPROTECT, + swd_config: SWD_CONFIG, + swd_wprotect: SWD_WPROTECT, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + _reserved13: [u8; 0x03c8], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - need_des"] + #[inline(always)] + pub const fn config0(&self) -> &CONFIG0 { + &self.config0 + } + #[doc = "0x04 - need_des"] + #[inline(always)] + pub const fn config1(&self) -> &CONFIG1 { + &self.config1 + } + #[doc = "0x08 - need_des"] + #[inline(always)] + pub const fn config2(&self) -> &CONFIG2 { + &self.config2 + } + #[doc = "0x0c - need_des"] + #[inline(always)] + pub const fn config3(&self) -> &CONFIG3 { + &self.config3 + } + #[doc = "0x10 - need_des"] + #[inline(always)] + pub const fn config4(&self) -> &CONFIG4 { + &self.config4 + } + #[doc = "0x14 - need_des"] + #[inline(always)] + pub const fn feed(&self) -> &FEED { + &self.feed + } + #[doc = "0x18 - need_des"] + #[inline(always)] + pub const fn wprotect(&self) -> &WPROTECT { + &self.wprotect + } + #[doc = "0x1c - need_des"] + #[inline(always)] + pub const fn swd_config(&self) -> &SWD_CONFIG { + &self.swd_config + } + #[doc = "0x20 - need_des"] + #[inline(always)] + pub const fn swd_wprotect(&self) -> &SWD_WPROTECT { + &self.swd_wprotect + } + #[doc = "0x24 - need_des"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x28 - need_des"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x2c - need_des"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x30 - need_des"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x3fc - need_des"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "CONFIG0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config0`] module"] +pub type CONFIG0 = crate::Reg; +#[doc = "need_des"] +pub mod config0; +#[doc = "CONFIG1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config1`] module"] +pub type CONFIG1 = crate::Reg; +#[doc = "need_des"] +pub mod config1; +#[doc = "CONFIG2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config2`] module"] +pub type CONFIG2 = crate::Reg; +#[doc = "need_des"] +pub mod config2; +#[doc = "CONFIG3 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config3`] module"] +pub type CONFIG3 = crate::Reg; +#[doc = "need_des"] +pub mod config3; +#[doc = "CONFIG4 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config4`] module"] +pub type CONFIG4 = crate::Reg; +#[doc = "need_des"] +pub mod config4; +#[doc = "FEED (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`feed::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@feed`] module"] +pub type FEED = crate::Reg; +#[doc = "need_des"] +pub mod feed; +#[doc = "WPROTECT (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wprotect::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wprotect::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wprotect`] module"] +pub type WPROTECT = crate::Reg; +#[doc = "need_des"] +pub mod wprotect; +#[doc = "SWD_CONFIG (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swd_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swd_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swd_config`] module"] +pub type SWD_CONFIG = crate::Reg; +#[doc = "need_des"] +pub mod swd_config; +#[doc = "SWD_WPROTECT (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swd_wprotect::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swd_wprotect::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swd_wprotect`] module"] +pub type SWD_WPROTECT = crate::Reg; +#[doc = "need_des"] +pub mod swd_wprotect; +#[doc = "INT_RAW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "need_des"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "need_des"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "need_des"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "need_des"] +pub mod int_clr; +#[doc = "DATE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "need_des"] +pub mod date; diff --git a/esp32p4/src/lp_wdt/config0.rs b/esp32p4/src/lp_wdt/config0.rs new file mode 100644 index 0000000000..9588a55a00 --- /dev/null +++ b/esp32p4/src/lp_wdt/config0.rs @@ -0,0 +1,279 @@ +#[doc = "Register `CONFIG0` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG0` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_CHIP_RESET_WIDTH` reader - need_des"] +pub type WDT_CHIP_RESET_WIDTH_R = crate::FieldReader; +#[doc = "Field `WDT_CHIP_RESET_WIDTH` writer - need_des"] +pub type WDT_CHIP_RESET_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WDT_CHIP_RESET_EN` reader - need_des"] +pub type WDT_CHIP_RESET_EN_R = crate::BitReader; +#[doc = "Field `WDT_CHIP_RESET_EN` writer - need_des"] +pub type WDT_CHIP_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_PAUSE_IN_SLP` reader - need_des"] +pub type WDT_PAUSE_IN_SLP_R = crate::BitReader; +#[doc = "Field `WDT_PAUSE_IN_SLP` writer - need_des"] +pub type WDT_PAUSE_IN_SLP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_APPCPU_RESET_EN` reader - need_des"] +pub type WDT_APPCPU_RESET_EN_R = crate::BitReader; +#[doc = "Field `WDT_APPCPU_RESET_EN` writer - need_des"] +pub type WDT_APPCPU_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_PROCPU_RESET_EN` reader - need_des"] +pub type WDT_PROCPU_RESET_EN_R = crate::BitReader; +#[doc = "Field `WDT_PROCPU_RESET_EN` writer - need_des"] +pub type WDT_PROCPU_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_FLASHBOOT_MOD_EN` reader - need_des"] +pub type WDT_FLASHBOOT_MOD_EN_R = crate::BitReader; +#[doc = "Field `WDT_FLASHBOOT_MOD_EN` writer - need_des"] +pub type WDT_FLASHBOOT_MOD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_SYS_RESET_LENGTH` reader - need_des"] +pub type WDT_SYS_RESET_LENGTH_R = crate::FieldReader; +#[doc = "Field `WDT_SYS_RESET_LENGTH` writer - need_des"] +pub type WDT_SYS_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WDT_CPU_RESET_LENGTH` reader - need_des"] +pub type WDT_CPU_RESET_LENGTH_R = crate::FieldReader; +#[doc = "Field `WDT_CPU_RESET_LENGTH` writer - need_des"] +pub type WDT_CPU_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WDT_STG3` reader - need_des"] +pub type WDT_STG3_R = crate::FieldReader; +#[doc = "Field `WDT_STG3` writer - need_des"] +pub type WDT_STG3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WDT_STG2` reader - need_des"] +pub type WDT_STG2_R = crate::FieldReader; +#[doc = "Field `WDT_STG2` writer - need_des"] +pub type WDT_STG2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WDT_STG1` reader - need_des"] +pub type WDT_STG1_R = crate::FieldReader; +#[doc = "Field `WDT_STG1` writer - need_des"] +pub type WDT_STG1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WDT_STG0` reader - need_des"] +pub type WDT_STG0_R = crate::FieldReader; +#[doc = "Field `WDT_STG0` writer - need_des"] +pub type WDT_STG0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WDT_EN` reader - need_des"] +pub type WDT_EN_R = crate::BitReader; +#[doc = "Field `WDT_EN` writer - need_des"] +pub type WDT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + pub fn wdt_chip_reset_width(&self) -> WDT_CHIP_RESET_WIDTH_R { + WDT_CHIP_RESET_WIDTH_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + pub fn wdt_chip_reset_en(&self) -> WDT_CHIP_RESET_EN_R { + WDT_CHIP_RESET_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - need_des"] + #[inline(always)] + pub fn wdt_pause_in_slp(&self) -> WDT_PAUSE_IN_SLP_R { + WDT_PAUSE_IN_SLP_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + pub fn wdt_appcpu_reset_en(&self) -> WDT_APPCPU_RESET_EN_R { + WDT_APPCPU_RESET_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + pub fn wdt_procpu_reset_en(&self) -> WDT_PROCPU_RESET_EN_R { + WDT_PROCPU_RESET_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn wdt_flashboot_mod_en(&self) -> WDT_FLASHBOOT_MOD_EN_R { + WDT_FLASHBOOT_MOD_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:15 - need_des"] + #[inline(always)] + pub fn wdt_sys_reset_length(&self) -> WDT_SYS_RESET_LENGTH_R { + WDT_SYS_RESET_LENGTH_R::new(((self.bits >> 13) & 7) as u8) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + pub fn wdt_cpu_reset_length(&self) -> WDT_CPU_RESET_LENGTH_R { + WDT_CPU_RESET_LENGTH_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:21 - need_des"] + #[inline(always)] + pub fn wdt_stg3(&self) -> WDT_STG3_R { + WDT_STG3_R::new(((self.bits >> 19) & 7) as u8) + } + #[doc = "Bits 22:24 - need_des"] + #[inline(always)] + pub fn wdt_stg2(&self) -> WDT_STG2_R { + WDT_STG2_R::new(((self.bits >> 22) & 7) as u8) + } + #[doc = "Bits 25:27 - need_des"] + #[inline(always)] + pub fn wdt_stg1(&self) -> WDT_STG1_R { + WDT_STG1_R::new(((self.bits >> 25) & 7) as u8) + } + #[doc = "Bits 28:30 - need_des"] + #[inline(always)] + pub fn wdt_stg0(&self) -> WDT_STG0_R { + WDT_STG0_R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn wdt_en(&self) -> WDT_EN_R { + WDT_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG0") + .field( + "wdt_chip_reset_width", + &format_args!("{}", self.wdt_chip_reset_width().bits()), + ) + .field( + "wdt_chip_reset_en", + &format_args!("{}", self.wdt_chip_reset_en().bit()), + ) + .field( + "wdt_pause_in_slp", + &format_args!("{}", self.wdt_pause_in_slp().bit()), + ) + .field( + "wdt_appcpu_reset_en", + &format_args!("{}", self.wdt_appcpu_reset_en().bit()), + ) + .field( + "wdt_procpu_reset_en", + &format_args!("{}", self.wdt_procpu_reset_en().bit()), + ) + .field( + "wdt_flashboot_mod_en", + &format_args!("{}", self.wdt_flashboot_mod_en().bit()), + ) + .field( + "wdt_sys_reset_length", + &format_args!("{}", self.wdt_sys_reset_length().bits()), + ) + .field( + "wdt_cpu_reset_length", + &format_args!("{}", self.wdt_cpu_reset_length().bits()), + ) + .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits())) + .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits())) + .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits())) + .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits())) + .field("wdt_en", &format_args!("{}", self.wdt_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_chip_reset_width(&mut self) -> WDT_CHIP_RESET_WIDTH_W { + WDT_CHIP_RESET_WIDTH_W::new(self, 0) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_chip_reset_en(&mut self) -> WDT_CHIP_RESET_EN_W { + WDT_CHIP_RESET_EN_W::new(self, 8) + } + #[doc = "Bit 9 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_pause_in_slp(&mut self) -> WDT_PAUSE_IN_SLP_W { + WDT_PAUSE_IN_SLP_W::new(self, 9) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W { + WDT_APPCPU_RESET_EN_W::new(self, 10) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W { + WDT_PROCPU_RESET_EN_W::new(self, 11) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W { + WDT_FLASHBOOT_MOD_EN_W::new(self, 12) + } + #[doc = "Bits 13:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W { + WDT_SYS_RESET_LENGTH_W::new(self, 13) + } + #[doc = "Bits 16:18 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W { + WDT_CPU_RESET_LENGTH_W::new(self, 16) + } + #[doc = "Bits 19:21 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_stg3(&mut self) -> WDT_STG3_W { + WDT_STG3_W::new(self, 19) + } + #[doc = "Bits 22:24 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_stg2(&mut self) -> WDT_STG2_W { + WDT_STG2_W::new(self, 22) + } + #[doc = "Bits 25:27 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_stg1(&mut self) -> WDT_STG1_W { + WDT_STG1_W::new(self, 25) + } + #[doc = "Bits 28:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_stg0(&mut self) -> WDT_STG0_W { + WDT_STG0_W::new(self, 28) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_en(&mut self) -> WDT_EN_W { + WDT_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONFIG0_SPEC; +impl crate::RegisterSpec for CONFIG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`config0::R`](R) reader structure"] +impl crate::Readable for CONFIG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config0::W`](W) writer structure"] +impl crate::Writable for CONFIG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONFIG0 to value 0x0001_3214"] +impl crate::Resettable for CONFIG0_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_3214; +} diff --git a/esp32p4/src/lp_wdt/config1.rs b/esp32p4/src/lp_wdt/config1.rs new file mode 100644 index 0000000000..13644bae1b --- /dev/null +++ b/esp32p4/src/lp_wdt/config1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CONFIG1` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG1` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_STG0_HOLD` reader - need_des"] +pub type WDT_STG0_HOLD_R = crate::FieldReader; +#[doc = "Field `WDT_STG0_HOLD` writer - need_des"] +pub type WDT_STG0_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn wdt_stg0_hold(&self) -> WDT_STG0_HOLD_R { + WDT_STG0_HOLD_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG1") + .field( + "wdt_stg0_hold", + &format_args!("{}", self.wdt_stg0_hold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_stg0_hold(&mut self) -> WDT_STG0_HOLD_W { + WDT_STG0_HOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONFIG1_SPEC; +impl crate::RegisterSpec for CONFIG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`config1::R`](R) reader structure"] +impl crate::Readable for CONFIG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config1::W`](W) writer structure"] +impl crate::Writable for CONFIG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONFIG1 to value 0x0003_0d40"] +impl crate::Resettable for CONFIG1_SPEC { + const RESET_VALUE: Self::Ux = 0x0003_0d40; +} diff --git a/esp32p4/src/lp_wdt/config2.rs b/esp32p4/src/lp_wdt/config2.rs new file mode 100644 index 0000000000..d220e1673b --- /dev/null +++ b/esp32p4/src/lp_wdt/config2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CONFIG2` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG2` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_STG1_HOLD` reader - need_des"] +pub type WDT_STG1_HOLD_R = crate::FieldReader; +#[doc = "Field `WDT_STG1_HOLD` writer - need_des"] +pub type WDT_STG1_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn wdt_stg1_hold(&self) -> WDT_STG1_HOLD_R { + WDT_STG1_HOLD_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG2") + .field( + "wdt_stg1_hold", + &format_args!("{}", self.wdt_stg1_hold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_stg1_hold(&mut self) -> WDT_STG1_HOLD_W { + WDT_STG1_HOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONFIG2_SPEC; +impl crate::RegisterSpec for CONFIG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`config2::R`](R) reader structure"] +impl crate::Readable for CONFIG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config2::W`](W) writer structure"] +impl crate::Writable for CONFIG2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONFIG2 to value 0x0001_3880"] +impl crate::Resettable for CONFIG2_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_3880; +} diff --git a/esp32p4/src/lp_wdt/config3.rs b/esp32p4/src/lp_wdt/config3.rs new file mode 100644 index 0000000000..7d3878d7b1 --- /dev/null +++ b/esp32p4/src/lp_wdt/config3.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CONFIG3` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG3` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_STG2_HOLD` reader - need_des"] +pub type WDT_STG2_HOLD_R = crate::FieldReader; +#[doc = "Field `WDT_STG2_HOLD` writer - need_des"] +pub type WDT_STG2_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn wdt_stg2_hold(&self) -> WDT_STG2_HOLD_R { + WDT_STG2_HOLD_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG3") + .field( + "wdt_stg2_hold", + &format_args!("{}", self.wdt_stg2_hold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_stg2_hold(&mut self) -> WDT_STG2_HOLD_W { + WDT_STG2_HOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONFIG3_SPEC; +impl crate::RegisterSpec for CONFIG3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`config3::R`](R) reader structure"] +impl crate::Readable for CONFIG3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config3::W`](W) writer structure"] +impl crate::Writable for CONFIG3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONFIG3 to value 0x0fff"] +impl crate::Resettable for CONFIG3_SPEC { + const RESET_VALUE: Self::Ux = 0x0fff; +} diff --git a/esp32p4/src/lp_wdt/config4.rs b/esp32p4/src/lp_wdt/config4.rs new file mode 100644 index 0000000000..ff2a0801e8 --- /dev/null +++ b/esp32p4/src/lp_wdt/config4.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CONFIG4` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG4` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_STG3_HOLD` reader - need_des"] +pub type WDT_STG3_HOLD_R = crate::FieldReader; +#[doc = "Field `WDT_STG3_HOLD` writer - need_des"] +pub type WDT_STG3_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn wdt_stg3_hold(&self) -> WDT_STG3_HOLD_R { + WDT_STG3_HOLD_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG4") + .field( + "wdt_stg3_hold", + &format_args!("{}", self.wdt_stg3_hold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_stg3_hold(&mut self) -> WDT_STG3_HOLD_W { + WDT_STG3_HOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONFIG4_SPEC; +impl crate::RegisterSpec for CONFIG4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`config4::R`](R) reader structure"] +impl crate::Readable for CONFIG4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config4::W`](W) writer structure"] +impl crate::Writable for CONFIG4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONFIG4 to value 0x0fff"] +impl crate::Resettable for CONFIG4_SPEC { + const RESET_VALUE: Self::Ux = 0x0fff; +} diff --git a/esp32p4/src/lp_wdt/date.rs b/esp32p4/src/lp_wdt/date.rs new file mode 100644 index 0000000000..3f6d07bcd7 --- /dev/null +++ b/esp32p4/src/lp_wdt/date.rs @@ -0,0 +1,82 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `LP_WDT_DATE` reader - need_des"] +pub type LP_WDT_DATE_R = crate::FieldReader; +#[doc = "Field `LP_WDT_DATE` writer - need_des"] +pub type LP_WDT_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `CLK_EN` reader - need_des"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - need_des"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn lp_wdt_date(&self) -> LP_WDT_DATE_R { + LP_WDT_DATE_R::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field( + "lp_wdt_date", + &format_args!("{}", self.lp_wdt_date().bits()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_wdt_date(&mut self) -> LP_WDT_DATE_W { + LP_WDT_DATE_W::new(self, 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0211_2080"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0211_2080; +} diff --git a/esp32p4/src/lp_wdt/feed.rs b/esp32p4/src/lp_wdt/feed.rs new file mode 100644 index 0000000000..3801905370 --- /dev/null +++ b/esp32p4/src/lp_wdt/feed.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FEED` writer"] +pub type W = crate::W; +#[doc = "Field `FEED` writer - need_des"] +pub type FEED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn feed(&mut self) -> FEED_W { + FEED_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`feed::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FEED_SPEC; +impl crate::RegisterSpec for FEED_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`feed::W`](W) writer structure"] +impl crate::Writable for FEED_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FEED to value 0"] +impl crate::Resettable for FEED_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_wdt/int_clr.rs b/esp32p4/src/lp_wdt/int_clr.rs new file mode 100644 index 0000000000..f041b7e2c7 --- /dev/null +++ b/esp32p4/src/lp_wdt/int_clr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `SUPER_WDT_INT_CLR` writer - need_des"] +pub type SUPER_WDT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_WDT_INT_CLR` writer - need_des"] +pub type LP_WDT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn super_wdt_int_clr(&mut self) -> SUPER_WDT_INT_CLR_W { + SUPER_WDT_INT_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_wdt_int_clr(&mut self) -> LP_WDT_INT_CLR_W { + LP_WDT_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_wdt/int_ena.rs b/esp32p4/src/lp_wdt/int_ena.rs new file mode 100644 index 0000000000..29b814e95f --- /dev/null +++ b/esp32p4/src/lp_wdt/int_ena.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `SUPER_WDT_INT_ENA` reader - need_des"] +pub type SUPER_WDT_INT_ENA_R = crate::BitReader; +#[doc = "Field `SUPER_WDT_INT_ENA` writer - need_des"] +pub type SUPER_WDT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_WDT_INT_ENA` reader - need_des"] +pub type LP_WDT_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_WDT_INT_ENA` writer - need_des"] +pub type LP_WDT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn super_wdt_int_ena(&self) -> SUPER_WDT_INT_ENA_R { + SUPER_WDT_INT_ENA_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_wdt_int_ena(&self) -> LP_WDT_INT_ENA_R { + LP_WDT_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "super_wdt_int_ena", + &format_args!("{}", self.super_wdt_int_ena().bit()), + ) + .field( + "lp_wdt_int_ena", + &format_args!("{}", self.lp_wdt_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn super_wdt_int_ena(&mut self) -> SUPER_WDT_INT_ENA_W { + SUPER_WDT_INT_ENA_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_wdt_int_ena(&mut self) -> LP_WDT_INT_ENA_W { + LP_WDT_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_wdt/int_raw.rs b/esp32p4/src/lp_wdt/int_raw.rs new file mode 100644 index 0000000000..3bc3b94a2b --- /dev/null +++ b/esp32p4/src/lp_wdt/int_raw.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `SUPER_WDT_INT_RAW` reader - need_des"] +pub type SUPER_WDT_INT_RAW_R = crate::BitReader; +#[doc = "Field `SUPER_WDT_INT_RAW` writer - need_des"] +pub type SUPER_WDT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_WDT_INT_RAW` reader - need_des"] +pub type LP_WDT_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_WDT_INT_RAW` writer - need_des"] +pub type LP_WDT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn super_wdt_int_raw(&self) -> SUPER_WDT_INT_RAW_R { + SUPER_WDT_INT_RAW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_wdt_int_raw(&self) -> LP_WDT_INT_RAW_R { + LP_WDT_INT_RAW_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "super_wdt_int_raw", + &format_args!("{}", self.super_wdt_int_raw().bit()), + ) + .field( + "lp_wdt_int_raw", + &format_args!("{}", self.lp_wdt_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn super_wdt_int_raw(&mut self) -> SUPER_WDT_INT_RAW_W { + SUPER_WDT_INT_RAW_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_wdt_int_raw(&mut self) -> LP_WDT_INT_RAW_W { + LP_WDT_INT_RAW_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_wdt/int_st.rs b/esp32p4/src/lp_wdt/int_st.rs new file mode 100644 index 0000000000..8d4f3a9e2a --- /dev/null +++ b/esp32p4/src/lp_wdt/int_st.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `SUPER_WDT_INT_ST` reader - need_des"] +pub type SUPER_WDT_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_WDT_INT_ST` reader - need_des"] +pub type LP_WDT_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn super_wdt_int_st(&self) -> SUPER_WDT_INT_ST_R { + SUPER_WDT_INT_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_wdt_int_st(&self) -> LP_WDT_INT_ST_R { + LP_WDT_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "super_wdt_int_st", + &format_args!("{}", self.super_wdt_int_st().bit()), + ) + .field( + "lp_wdt_int_st", + &format_args!("{}", self.lp_wdt_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_wdt/swd_config.rs b/esp32p4/src/lp_wdt/swd_config.rs new file mode 100644 index 0000000000..a167066eb2 --- /dev/null +++ b/esp32p4/src/lp_wdt/swd_config.rs @@ -0,0 +1,128 @@ +#[doc = "Register `SWD_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `SWD_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `SWD_RESET_FLAG` reader - need_des"] +pub type SWD_RESET_FLAG_R = crate::BitReader; +#[doc = "Field `SWD_AUTO_FEED_EN` reader - need_des"] +pub type SWD_AUTO_FEED_EN_R = crate::BitReader; +#[doc = "Field `SWD_AUTO_FEED_EN` writer - need_des"] +pub type SWD_AUTO_FEED_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SWD_RST_FLAG_CLR` writer - need_des"] +pub type SWD_RST_FLAG_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SWD_SIGNAL_WIDTH` reader - need_des"] +pub type SWD_SIGNAL_WIDTH_R = crate::FieldReader; +#[doc = "Field `SWD_SIGNAL_WIDTH` writer - need_des"] +pub type SWD_SIGNAL_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `SWD_DISABLE` reader - need_des"] +pub type SWD_DISABLE_R = crate::BitReader; +#[doc = "Field `SWD_DISABLE` writer - need_des"] +pub type SWD_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SWD_FEED` writer - need_des"] +pub type SWD_FEED_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn swd_reset_flag(&self) -> SWD_RESET_FLAG_R { + SWD_RESET_FLAG_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 18 - need_des"] + #[inline(always)] + pub fn swd_auto_feed_en(&self) -> SWD_AUTO_FEED_EN_R { + SWD_AUTO_FEED_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 20:29 - need_des"] + #[inline(always)] + pub fn swd_signal_width(&self) -> SWD_SIGNAL_WIDTH_R { + SWD_SIGNAL_WIDTH_R::new(((self.bits >> 20) & 0x03ff) as u16) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn swd_disable(&self) -> SWD_DISABLE_R { + SWD_DISABLE_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SWD_CONFIG") + .field( + "swd_reset_flag", + &format_args!("{}", self.swd_reset_flag().bit()), + ) + .field( + "swd_auto_feed_en", + &format_args!("{}", self.swd_auto_feed_en().bit()), + ) + .field( + "swd_signal_width", + &format_args!("{}", self.swd_signal_width().bits()), + ) + .field("swd_disable", &format_args!("{}", self.swd_disable().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 18 - need_des"] + #[inline(always)] + #[must_use] + pub fn swd_auto_feed_en(&mut self) -> SWD_AUTO_FEED_EN_W { + SWD_AUTO_FEED_EN_W::new(self, 18) + } + #[doc = "Bit 19 - need_des"] + #[inline(always)] + #[must_use] + pub fn swd_rst_flag_clr(&mut self) -> SWD_RST_FLAG_CLR_W { + SWD_RST_FLAG_CLR_W::new(self, 19) + } + #[doc = "Bits 20:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn swd_signal_width(&mut self) -> SWD_SIGNAL_WIDTH_W { + SWD_SIGNAL_WIDTH_W::new(self, 20) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn swd_disable(&mut self) -> SWD_DISABLE_W { + SWD_DISABLE_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn swd_feed(&mut self) -> SWD_FEED_W { + SWD_FEED_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swd_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swd_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SWD_CONFIG_SPEC; +impl crate::RegisterSpec for SWD_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`swd_config::R`](R) reader structure"] +impl crate::Readable for SWD_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`swd_config::W`](W) writer structure"] +impl crate::Writable for SWD_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SWD_CONFIG to value 0x12c0_0000"] +impl crate::Resettable for SWD_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0x12c0_0000; +} diff --git a/esp32p4/src/lp_wdt/swd_wprotect.rs b/esp32p4/src/lp_wdt/swd_wprotect.rs new file mode 100644 index 0000000000..b1f97166e7 --- /dev/null +++ b/esp32p4/src/lp_wdt/swd_wprotect.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SWD_WPROTECT` reader"] +pub type R = crate::R; +#[doc = "Register `SWD_WPROTECT` writer"] +pub type W = crate::W; +#[doc = "Field `SWD_WKEY` reader - need_des"] +pub type SWD_WKEY_R = crate::FieldReader; +#[doc = "Field `SWD_WKEY` writer - need_des"] +pub type SWD_WKEY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn swd_wkey(&self) -> SWD_WKEY_R { + SWD_WKEY_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SWD_WPROTECT") + .field("swd_wkey", &format_args!("{}", self.swd_wkey().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn swd_wkey(&mut self) -> SWD_WKEY_W { + SWD_WKEY_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swd_wprotect::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swd_wprotect::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SWD_WPROTECT_SPEC; +impl crate::RegisterSpec for SWD_WPROTECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`swd_wprotect::R`](R) reader structure"] +impl crate::Readable for SWD_WPROTECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`swd_wprotect::W`](W) writer structure"] +impl crate::Writable for SWD_WPROTECT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SWD_WPROTECT to value 0"] +impl crate::Resettable for SWD_WPROTECT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/lp_wdt/wprotect.rs b/esp32p4/src/lp_wdt/wprotect.rs new file mode 100644 index 0000000000..68c16fd96d --- /dev/null +++ b/esp32p4/src/lp_wdt/wprotect.rs @@ -0,0 +1,63 @@ +#[doc = "Register `WPROTECT` reader"] +pub type R = crate::R; +#[doc = "Register `WPROTECT` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_WKEY` reader - need_des"] +pub type WDT_WKEY_R = crate::FieldReader; +#[doc = "Field `WDT_WKEY` writer - need_des"] +pub type WDT_WKEY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn wdt_wkey(&self) -> WDT_WKEY_R { + WDT_WKEY_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WPROTECT") + .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn wdt_wkey(&mut self) -> WDT_WKEY_W { + WDT_WKEY_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wprotect::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wprotect::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WPROTECT_SPEC; +impl crate::RegisterSpec for WPROTECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wprotect::R`](R) reader structure"] +impl crate::Readable for WPROTECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wprotect::W`](W) writer structure"] +impl crate::Writable for WPROTECT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WPROTECT to value 0"] +impl crate::Resettable for WPROTECT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0.rs b/esp32p4/src/mcpwm0.rs new file mode 100644 index 0000000000..3b2b037ec9 --- /dev/null +++ b/esp32p4/src/mcpwm0.rs @@ -0,0 +1,880 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + clk_cfg: CLK_CFG, + timer_cfg0: (), + _reserved2: [u8; 0x04], + timer_cfg1: (), + _reserved3: [u8; 0x04], + timer_sync: (), + _reserved4: [u8; 0x04], + timer_status: (), + _reserved5: [u8; 0x24], + timer_synci_cfg: TIMER_SYNCI_CFG, + operator_timersel: OPERATOR_TIMERSEL, + gen_stmp_cfg: (), + _reserved8: [u8; 0x04], + gen_tstmp_a: (), + _reserved9: [u8; 0x04], + gen_tstmp_b: (), + _reserved10: [u8; 0x04], + gen_cfg0: (), + _reserved11: [u8; 0x04], + gen_force: (), + _reserved12: [u8; 0x04], + gen_a: (), + _reserved13: [u8; 0x04], + gen_b: (), + _reserved14: [u8; 0x04], + dt_cfg: (), + _reserved15: [u8; 0x04], + dt_fed_cfg: (), + _reserved16: [u8; 0x04], + dt_red_cfg: (), + _reserved17: [u8; 0x04], + carrier_cfg: (), + _reserved18: [u8; 0x04], + fh_cfg0: (), + _reserved19: [u8; 0x04], + fh_cfg1: (), + _reserved20: [u8; 0x04], + fh_status: (), + _reserved21: [u8; 0x74], + fault_detect: FAULT_DETECT, + cap_timer_cfg: CAP_TIMER_CFG, + cap_timer_phase: CAP_TIMER_PHASE, + cap_ch_cfg: [CAP_CH_CFG; 3], + cap_ch: [CAP_CH; 3], + cap_status: CAP_STATUS, + update_cfg: UPDATE_CFG, + int_ena: INT_ENA, + int_raw: INT_RAW, + int_st: INT_ST, + int_clr: INT_CLR, + evt_en: EVT_EN, + task_en: TASK_EN, + evt_en2: EVT_EN2, + op_tstmp_e1: (), + _reserved36: [u8; 0x04], + op_tstmp_e2: (), + _reserved37: [u8; 0x14], + clk: CLK, + version: VERSION, +} +impl RegisterBlock { + #[doc = "0x00 - PWM clock prescaler register."] + #[inline(always)] + pub const fn clk_cfg(&self) -> &CLK_CFG { + &self.clk_cfg + } + #[doc = "0x04..0x10 - PWM timer%s period and update method configuration register."] + #[inline(always)] + pub const fn timer_cfg0(&self, n: usize) -> &TIMER_CFG0 { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { &*(self as *const Self).cast::().add(4).add(16 * n).cast() } + } + #[doc = "0x04 - PWM timer0 period and update method configuration register."] + #[inline(always)] + pub const fn timer0_cfg0(&self) -> &TIMER_CFG0 { + &self.timer_cfg0(0) + } + #[doc = "0x14 - PWM timer1 period and update method configuration register."] + #[inline(always)] + pub const fn timer1_cfg0(&self) -> &TIMER_CFG0 { + &self.timer_cfg0(1) + } + #[doc = "0x24 - PWM timer2 period and update method configuration register."] + #[inline(always)] + pub const fn timer2_cfg0(&self) -> &TIMER_CFG0 { + &self.timer_cfg0(2) + } + #[doc = "0x08..0x14 - PWM timer%s working mode and start/stop control register."] + #[inline(always)] + pub const fn timer_cfg1(&self, n: usize) -> &TIMER_CFG1 { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { &*(self as *const Self).cast::().add(8).add(16 * n).cast() } + } + #[doc = "0x08 - PWM timer0 working mode and start/stop control register."] + #[inline(always)] + pub const fn timer0_cfg1(&self) -> &TIMER_CFG1 { + &self.timer_cfg1(0) + } + #[doc = "0x18 - PWM timer1 working mode and start/stop control register."] + #[inline(always)] + pub const fn timer1_cfg1(&self) -> &TIMER_CFG1 { + &self.timer_cfg1(1) + } + #[doc = "0x28 - PWM timer2 working mode and start/stop control register."] + #[inline(always)] + pub const fn timer2_cfg1(&self) -> &TIMER_CFG1 { + &self.timer_cfg1(2) + } + #[doc = "0x0c..0x18 - PWM timer%s sync function configuration register."] + #[inline(always)] + pub const fn timer_sync(&self, n: usize) -> &TIMER_SYNC { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(12) + .add(16 * n) + .cast() + } + } + #[doc = "0x0c - PWM timer0 sync function configuration register."] + #[inline(always)] + pub const fn timer0_sync(&self) -> &TIMER_SYNC { + &self.timer_sync(0) + } + #[doc = "0x1c - PWM timer1 sync function configuration register."] + #[inline(always)] + pub const fn timer1_sync(&self) -> &TIMER_SYNC { + &self.timer_sync(1) + } + #[doc = "0x2c - PWM timer2 sync function configuration register."] + #[inline(always)] + pub const fn timer2_sync(&self) -> &TIMER_SYNC { + &self.timer_sync(2) + } + #[doc = "0x10..0x1c - PWM timer%s status register."] + #[inline(always)] + pub const fn timer_status(&self, n: usize) -> &TIMER_STATUS { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(16) + .add(16 * n) + .cast() + } + } + #[doc = "0x10 - PWM timer0 status register."] + #[inline(always)] + pub const fn timer0_status(&self) -> &TIMER_STATUS { + &self.timer_status(0) + } + #[doc = "0x20 - PWM timer1 status register."] + #[inline(always)] + pub const fn timer1_status(&self) -> &TIMER_STATUS { + &self.timer_status(1) + } + #[doc = "0x30 - PWM timer2 status register."] + #[inline(always)] + pub const fn timer2_status(&self) -> &TIMER_STATUS { + &self.timer_status(2) + } + #[doc = "0x34 - Synchronization input selection register for PWM timers."] + #[inline(always)] + pub const fn timer_synci_cfg(&self) -> &TIMER_SYNCI_CFG { + &self.timer_synci_cfg + } + #[doc = "0x38 - PWM operator's timer select register"] + #[inline(always)] + pub const fn operator_timersel(&self) -> &OPERATOR_TIMERSEL { + &self.operator_timersel + } + #[doc = "0x3c..0x48 - Generator%s time stamp registers A and B transfer status and update method register"] + #[inline(always)] + pub const fn gen_stmp_cfg(&self, n: usize) -> &GEN_STMP_CFG { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(60) + .add(56 * n) + .cast() + } + } + #[doc = "0x3c - Generator0 time stamp registers A and B transfer status and update method register"] + #[inline(always)] + pub const fn gen0_stmp_cfg(&self) -> &GEN_STMP_CFG { + &self.gen_stmp_cfg(0) + } + #[doc = "0x74 - Generator1 time stamp registers A and B transfer status and update method register"] + #[inline(always)] + pub const fn gen1_stmp_cfg(&self) -> &GEN_STMP_CFG { + &self.gen_stmp_cfg(1) + } + #[doc = "0xac - Generator2 time stamp registers A and B transfer status and update method register"] + #[inline(always)] + pub const fn gen2_stmp_cfg(&self) -> &GEN_STMP_CFG { + &self.gen_stmp_cfg(2) + } + #[doc = "0x40..0x4c - Generator%s time stamp A's shadow register"] + #[inline(always)] + pub const fn gen_tstmp_a(&self, n: usize) -> &GEN_TSTMP_A { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(64) + .add(56 * n) + .cast() + } + } + #[doc = "0x40 - Generator0 time stamp A's shadow register"] + #[inline(always)] + pub const fn gen0_tstmp_a(&self) -> &GEN_TSTMP_A { + &self.gen_tstmp_a(0) + } + #[doc = "0x78 - Generator1 time stamp A's shadow register"] + #[inline(always)] + pub const fn gen1_tstmp_a(&self) -> &GEN_TSTMP_A { + &self.gen_tstmp_a(1) + } + #[doc = "0xb0 - Generator2 time stamp A's shadow register"] + #[inline(always)] + pub const fn gen2_tstmp_a(&self) -> &GEN_TSTMP_A { + &self.gen_tstmp_a(2) + } + #[doc = "0x44..0x50 - Generator%s time stamp B's shadow register"] + #[inline(always)] + pub const fn gen_tstmp_b(&self, n: usize) -> &GEN_TSTMP_B { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(68) + .add(56 * n) + .cast() + } + } + #[doc = "0x44 - Generator0 time stamp B's shadow register"] + #[inline(always)] + pub const fn gen0_tstmp_b(&self) -> &GEN_TSTMP_B { + &self.gen_tstmp_b(0) + } + #[doc = "0x7c - Generator1 time stamp B's shadow register"] + #[inline(always)] + pub const fn gen1_tstmp_b(&self) -> &GEN_TSTMP_B { + &self.gen_tstmp_b(1) + } + #[doc = "0xb4 - Generator2 time stamp B's shadow register"] + #[inline(always)] + pub const fn gen2_tstmp_b(&self) -> &GEN_TSTMP_B { + &self.gen_tstmp_b(2) + } + #[doc = "0x48..0x54 - Generator%s fault event T0 and T1 configuration register"] + #[inline(always)] + pub const fn gen_cfg0(&self, n: usize) -> &GEN_CFG0 { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(72) + .add(56 * n) + .cast() + } + } + #[doc = "0x48 - Generator0 fault event T0 and T1 configuration register"] + #[inline(always)] + pub const fn gen0_cfg0(&self) -> &GEN_CFG0 { + &self.gen_cfg0(0) + } + #[doc = "0x80 - Generator1 fault event T0 and T1 configuration register"] + #[inline(always)] + pub const fn gen1_cfg0(&self) -> &GEN_CFG0 { + &self.gen_cfg0(1) + } + #[doc = "0xb8 - Generator2 fault event T0 and T1 configuration register"] + #[inline(always)] + pub const fn gen2_cfg0(&self) -> &GEN_CFG0 { + &self.gen_cfg0(2) + } + #[doc = "0x4c..0x58 - Generator%s output signal force mode register."] + #[inline(always)] + pub const fn gen_force(&self, n: usize) -> &GEN_FORCE { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(76) + .add(56 * n) + .cast() + } + } + #[doc = "0x4c - Generator0 output signal force mode register."] + #[inline(always)] + pub const fn gen0_force(&self) -> &GEN_FORCE { + &self.gen_force(0) + } + #[doc = "0x84 - Generator1 output signal force mode register."] + #[inline(always)] + pub const fn gen1_force(&self) -> &GEN_FORCE { + &self.gen_force(1) + } + #[doc = "0xbc - Generator2 output signal force mode register."] + #[inline(always)] + pub const fn gen2_force(&self) -> &GEN_FORCE { + &self.gen_force(2) + } + #[doc = "0x50..0x5c - PWM%s output signal A actions configuration register"] + #[inline(always)] + pub const fn gen_a(&self, n: usize) -> &GEN_A { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(80) + .add(56 * n) + .cast() + } + } + #[doc = "0x50 - PWM0 output signal A actions configuration register"] + #[inline(always)] + pub const fn gen0_a(&self) -> &GEN_A { + &self.gen_a(0) + } + #[doc = "0x88 - PWM1 output signal A actions configuration register"] + #[inline(always)] + pub const fn gen1_a(&self) -> &GEN_A { + &self.gen_a(1) + } + #[doc = "0xc0 - PWM2 output signal A actions configuration register"] + #[inline(always)] + pub const fn gen2_a(&self) -> &GEN_A { + &self.gen_a(2) + } + #[doc = "0x54..0x60 - PWM%s output signal B actions configuration register"] + #[inline(always)] + pub const fn gen_b(&self, n: usize) -> &GEN_B { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(84) + .add(56 * n) + .cast() + } + } + #[doc = "0x54 - PWM0 output signal B actions configuration register"] + #[inline(always)] + pub const fn gen0_b(&self) -> &GEN_B { + &self.gen_b(0) + } + #[doc = "0x8c - PWM1 output signal B actions configuration register"] + #[inline(always)] + pub const fn gen1_b(&self) -> &GEN_B { + &self.gen_b(1) + } + #[doc = "0xc4 - PWM2 output signal B actions configuration register"] + #[inline(always)] + pub const fn gen2_b(&self) -> &GEN_B { + &self.gen_b(2) + } + #[doc = "0x58..0x64 - Dead time configuration register"] + #[inline(always)] + pub const fn dt_cfg(&self, n: usize) -> &DT_CFG { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(88) + .add(56 * n) + .cast() + } + } + #[doc = "0x58 - Dead time configuration register"] + #[inline(always)] + pub const fn dt0_cfg(&self) -> &DT_CFG { + &self.dt_cfg(0) + } + #[doc = "0x90 - Dead time configuration register"] + #[inline(always)] + pub const fn dt1_cfg(&self) -> &DT_CFG { + &self.dt_cfg(1) + } + #[doc = "0xc8 - Dead time configuration register"] + #[inline(always)] + pub const fn dt2_cfg(&self) -> &DT_CFG { + &self.dt_cfg(2) + } + #[doc = "0x5c..0x68 - Falling edge delay (FED) shadow register"] + #[inline(always)] + pub const fn dt_fed_cfg(&self, n: usize) -> &DT_FED_CFG { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(92) + .add(56 * n) + .cast() + } + } + #[doc = "0x5c - Falling edge delay (FED) shadow register"] + #[inline(always)] + pub const fn dt0_fed_cfg(&self) -> &DT_FED_CFG { + &self.dt_fed_cfg(0) + } + #[doc = "0x94 - Falling edge delay (FED) shadow register"] + #[inline(always)] + pub const fn dt1_fed_cfg(&self) -> &DT_FED_CFG { + &self.dt_fed_cfg(1) + } + #[doc = "0xcc - Falling edge delay (FED) shadow register"] + #[inline(always)] + pub const fn dt2_fed_cfg(&self) -> &DT_FED_CFG { + &self.dt_fed_cfg(2) + } + #[doc = "0x60..0x6c - Rising edge delay (RED) shadow register"] + #[inline(always)] + pub const fn dt_red_cfg(&self, n: usize) -> &DT_RED_CFG { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(96) + .add(56 * n) + .cast() + } + } + #[doc = "0x60 - Rising edge delay (RED) shadow register"] + #[inline(always)] + pub const fn dt0_red_cfg(&self) -> &DT_RED_CFG { + &self.dt_red_cfg(0) + } + #[doc = "0x98 - Rising edge delay (RED) shadow register"] + #[inline(always)] + pub const fn dt1_red_cfg(&self) -> &DT_RED_CFG { + &self.dt_red_cfg(1) + } + #[doc = "0xd0 - Rising edge delay (RED) shadow register"] + #[inline(always)] + pub const fn dt2_red_cfg(&self) -> &DT_RED_CFG { + &self.dt_red_cfg(2) + } + #[doc = "0x64..0x70 - Carrier%s configuration register"] + #[inline(always)] + pub const fn carrier_cfg(&self, n: usize) -> &CARRIER_CFG { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(100) + .add(56 * n) + .cast() + } + } + #[doc = "0x64 - Carrier0 configuration register"] + #[inline(always)] + pub const fn carrier0_cfg(&self) -> &CARRIER_CFG { + &self.carrier_cfg(0) + } + #[doc = "0x9c - Carrier1 configuration register"] + #[inline(always)] + pub const fn carrier1_cfg(&self) -> &CARRIER_CFG { + &self.carrier_cfg(1) + } + #[doc = "0xd4 - Carrier2 configuration register"] + #[inline(always)] + pub const fn carrier2_cfg(&self) -> &CARRIER_CFG { + &self.carrier_cfg(2) + } + #[doc = "0x68..0x74 - PWM%s A and PWM%s B trip events actions configuration register"] + #[inline(always)] + pub const fn fh_cfg0(&self, n: usize) -> &FH_CFG0 { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(104) + .add(56 * n) + .cast() + } + } + #[doc = "0x68 - PWM0 A and PWM0 B trip events actions configuration register"] + #[inline(always)] + pub const fn fh0_cfg0(&self) -> &FH_CFG0 { + &self.fh_cfg0(0) + } + #[doc = "0xa0 - PWM1 A and PWM1 B trip events actions configuration register"] + #[inline(always)] + pub const fn fh1_cfg0(&self) -> &FH_CFG0 { + &self.fh_cfg0(1) + } + #[doc = "0xd8 - PWM2 A and PWM2 B trip events actions configuration register"] + #[inline(always)] + pub const fn fh2_cfg0(&self) -> &FH_CFG0 { + &self.fh_cfg0(2) + } + #[doc = "0x6c..0x78 - Software triggers for fault handler actions configuration register"] + #[inline(always)] + pub const fn fh_cfg1(&self, n: usize) -> &FH_CFG1 { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(108) + .add(56 * n) + .cast() + } + } + #[doc = "0x6c - Software triggers for fault handler actions configuration register"] + #[inline(always)] + pub const fn fh0_cfg1(&self) -> &FH_CFG1 { + &self.fh_cfg1(0) + } + #[doc = "0xa4 - Software triggers for fault handler actions configuration register"] + #[inline(always)] + pub const fn fh1_cfg1(&self) -> &FH_CFG1 { + &self.fh_cfg1(1) + } + #[doc = "0xdc - Software triggers for fault handler actions configuration register"] + #[inline(always)] + pub const fn fh2_cfg1(&self) -> &FH_CFG1 { + &self.fh_cfg1(2) + } + #[doc = "0x70..0x7c - Fault events status register"] + #[inline(always)] + pub const fn fh_status(&self, n: usize) -> &FH_STATUS { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(112) + .add(56 * n) + .cast() + } + } + #[doc = "0x70 - Fault events status register"] + #[inline(always)] + pub const fn fh0_status(&self) -> &FH_STATUS { + &self.fh_status(0) + } + #[doc = "0xa8 - Fault events status register"] + #[inline(always)] + pub const fn fh1_status(&self) -> &FH_STATUS { + &self.fh_status(1) + } + #[doc = "0xe0 - Fault events status register"] + #[inline(always)] + pub const fn fh2_status(&self) -> &FH_STATUS { + &self.fh_status(2) + } + #[doc = "0xe4 - Fault detection configuration and status register"] + #[inline(always)] + pub const fn fault_detect(&self) -> &FAULT_DETECT { + &self.fault_detect + } + #[doc = "0xe8 - Capture timer configuration register"] + #[inline(always)] + pub const fn cap_timer_cfg(&self) -> &CAP_TIMER_CFG { + &self.cap_timer_cfg + } + #[doc = "0xec - Capture timer sync phase register"] + #[inline(always)] + pub const fn cap_timer_phase(&self) -> &CAP_TIMER_PHASE { + &self.cap_timer_phase + } + #[doc = "0xf0..0xfc - Capture channel %s configuration register"] + #[inline(always)] + pub const fn cap_ch_cfg(&self, n: usize) -> &CAP_CH_CFG { + &self.cap_ch_cfg[n] + } + #[doc = "0xf0 - Capture channel 0 configuration register"] + #[inline(always)] + pub const fn cap_ch0_cfg(&self) -> &CAP_CH_CFG { + &self.cap_ch_cfg(0) + } + #[doc = "0xf4 - Capture channel 1 configuration register"] + #[inline(always)] + pub const fn cap_ch1_cfg(&self) -> &CAP_CH_CFG { + &self.cap_ch_cfg(1) + } + #[doc = "0xf8 - Capture channel 2 configuration register"] + #[inline(always)] + pub const fn cap_ch2_cfg(&self) -> &CAP_CH_CFG { + &self.cap_ch_cfg(2) + } + #[doc = "0xfc..0x108 - CAP%s capture value register"] + #[inline(always)] + pub const fn cap_ch(&self, n: usize) -> &CAP_CH { + &self.cap_ch[n] + } + #[doc = "0x108 - Last capture trigger edge information register"] + #[inline(always)] + pub const fn cap_status(&self) -> &CAP_STATUS { + &self.cap_status + } + #[doc = "0x10c - Generator Update configuration register"] + #[inline(always)] + pub const fn update_cfg(&self) -> &UPDATE_CFG { + &self.update_cfg + } + #[doc = "0x110 - Interrupt enable register"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x114 - Interrupt raw status register"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x118 - Interrupt masked status register"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x11c - Interrupt clear register"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x120 - Event enable register"] + #[inline(always)] + pub const fn evt_en(&self) -> &EVT_EN { + &self.evt_en + } + #[doc = "0x124 - Task enable register"] + #[inline(always)] + pub const fn task_en(&self) -> &TASK_EN { + &self.task_en + } + #[doc = "0x128 - Event enable register2"] + #[inline(always)] + pub const fn evt_en2(&self) -> &EVT_EN2 { + &self.evt_en2 + } + #[doc = "0x12c..0x138 - Generator%s timer stamp E1 value register"] + #[inline(always)] + pub const fn op_tstmp_e1(&self, n: usize) -> &OP_TSTMP_E1 { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(300) + .add(8 * n) + .cast() + } + } + #[doc = "0x12c - Generator0 timer stamp E1 value register"] + #[inline(always)] + pub const fn op0_tstmp_e1(&self) -> &OP_TSTMP_E1 { + &self.op_tstmp_e1(0) + } + #[doc = "0x134 - Generator1 timer stamp E1 value register"] + #[inline(always)] + pub const fn op1_tstmp_e1(&self) -> &OP_TSTMP_E1 { + &self.op_tstmp_e1(1) + } + #[doc = "0x13c - Generator2 timer stamp E1 value register"] + #[inline(always)] + pub const fn op2_tstmp_e1(&self) -> &OP_TSTMP_E1 { + &self.op_tstmp_e1(2) + } + #[doc = "0x130..0x13c - Generator%s timer stamp E2 value register"] + #[inline(always)] + pub const fn op_tstmp_e2(&self, n: usize) -> &OP_TSTMP_E2 { + #[allow(clippy::no_effect)] + [(); 3][n]; + unsafe { + &*(self as *const Self) + .cast::() + .add(304) + .add(8 * n) + .cast() + } + } + #[doc = "0x130 - Generator0 timer stamp E2 value register"] + #[inline(always)] + pub const fn op0_tstmp_e2(&self) -> &OP_TSTMP_E2 { + &self.op_tstmp_e2(0) + } + #[doc = "0x138 - Generator1 timer stamp E2 value register"] + #[inline(always)] + pub const fn op1_tstmp_e2(&self) -> &OP_TSTMP_E2 { + &self.op_tstmp_e2(1) + } + #[doc = "0x140 - Generator2 timer stamp E2 value register"] + #[inline(always)] + pub const fn op2_tstmp_e2(&self) -> &OP_TSTMP_E2 { + &self.op_tstmp_e2(2) + } + #[doc = "0x144 - Global configuration register"] + #[inline(always)] + pub const fn clk(&self) -> &CLK { + &self.clk + } + #[doc = "0x148 - Version register."] + #[inline(always)] + pub const fn version(&self) -> &VERSION { + &self.version + } +} +#[doc = "CLK_CFG (rw) register accessor: PWM clock prescaler register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_cfg`] module"] +pub type CLK_CFG = crate::Reg; +#[doc = "PWM clock prescaler register."] +pub mod clk_cfg; +#[doc = "TIMER_CFG0 (rw) register accessor: PWM timer%s period and update method configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_cfg0`] module"] +pub type TIMER_CFG0 = crate::Reg; +#[doc = "PWM timer%s period and update method configuration register."] +pub mod timer_cfg0; +#[doc = "TIMER_CFG1 (rw) register accessor: PWM timer%s working mode and start/stop control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_cfg1`] module"] +pub type TIMER_CFG1 = crate::Reg; +#[doc = "PWM timer%s working mode and start/stop control register."] +pub mod timer_cfg1; +#[doc = "TIMER_SYNC (rw) register accessor: PWM timer%s sync function configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_sync`] module"] +pub type TIMER_SYNC = crate::Reg; +#[doc = "PWM timer%s sync function configuration register."] +pub mod timer_sync; +#[doc = "TIMER_STATUS (r) register accessor: PWM timer%s status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_status`] module"] +pub type TIMER_STATUS = crate::Reg; +#[doc = "PWM timer%s status register."] +pub mod timer_status; +#[doc = "TIMER_SYNCI_CFG (rw) register accessor: Synchronization input selection register for PWM timers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_synci_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_synci_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer_synci_cfg`] module"] +pub type TIMER_SYNCI_CFG = crate::Reg; +#[doc = "Synchronization input selection register for PWM timers."] +pub mod timer_synci_cfg; +#[doc = "OPERATOR_TIMERSEL (rw) register accessor: PWM operator's timer select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`operator_timersel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`operator_timersel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@operator_timersel`] module"] +pub type OPERATOR_TIMERSEL = crate::Reg; +#[doc = "PWM operator's timer select register"] +pub mod operator_timersel; +#[doc = "GEN_STMP_CFG (rw) register accessor: Generator%s time stamp registers A and B transfer status and update method register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_stmp_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_stmp_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_stmp_cfg`] module"] +pub type GEN_STMP_CFG = crate::Reg; +#[doc = "Generator%s time stamp registers A and B transfer status and update method register"] +pub mod gen_stmp_cfg; +#[doc = "GEN_TSTMP_A (rw) register accessor: Generator%s time stamp A's shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_tstmp_a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_tstmp_a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_tstmp_a`] module"] +pub type GEN_TSTMP_A = crate::Reg; +#[doc = "Generator%s time stamp A's shadow register"] +pub mod gen_tstmp_a; +#[doc = "GEN_TSTMP_B (rw) register accessor: Generator%s time stamp B's shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_tstmp_b::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_tstmp_b::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_tstmp_b`] module"] +pub type GEN_TSTMP_B = crate::Reg; +#[doc = "Generator%s time stamp B's shadow register"] +pub mod gen_tstmp_b; +#[doc = "GEN_CFG0 (rw) register accessor: Generator%s fault event T0 and T1 configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_cfg0`] module"] +pub type GEN_CFG0 = crate::Reg; +#[doc = "Generator%s fault event T0 and T1 configuration register"] +pub mod gen_cfg0; +#[doc = "GEN_FORCE (rw) register accessor: Generator%s output signal force mode register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_force::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_force::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_force`] module"] +pub type GEN_FORCE = crate::Reg; +#[doc = "Generator%s output signal force mode register."] +pub mod gen_force; +#[doc = "GEN_A (rw) register accessor: PWM%s output signal A actions configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_a`] module"] +pub type GEN_A = crate::Reg; +#[doc = "PWM%s output signal A actions configuration register"] +pub mod gen_a; +#[doc = "GEN_B (rw) register accessor: PWM%s output signal B actions configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_b::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_b::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_b`] module"] +pub type GEN_B = crate::Reg; +#[doc = "PWM%s output signal B actions configuration register"] +pub mod gen_b; +#[doc = "DT_CFG (rw) register accessor: Dead time configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dt_cfg`] module"] +pub type DT_CFG = crate::Reg; +#[doc = "Dead time configuration register"] +pub mod dt_cfg; +#[doc = "DT_FED_CFG (rw) register accessor: Falling edge delay (FED) shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_fed_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_fed_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dt_fed_cfg`] module"] +pub type DT_FED_CFG = crate::Reg; +#[doc = "Falling edge delay (FED) shadow register"] +pub mod dt_fed_cfg; +#[doc = "DT_RED_CFG (rw) register accessor: Rising edge delay (RED) shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_red_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_red_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dt_red_cfg`] module"] +pub type DT_RED_CFG = crate::Reg; +#[doc = "Rising edge delay (RED) shadow register"] +pub mod dt_red_cfg; +#[doc = "CARRIER_CFG (rw) register accessor: Carrier%s configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`carrier_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`carrier_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@carrier_cfg`] module"] +pub type CARRIER_CFG = crate::Reg; +#[doc = "Carrier%s configuration register"] +pub mod carrier_cfg; +#[doc = "FH_CFG0 (rw) register accessor: PWM%s A and PWM%s B trip events actions configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fh_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fh_cfg0`] module"] +pub type FH_CFG0 = crate::Reg; +#[doc = "PWM%s A and PWM%s B trip events actions configuration register"] +pub mod fh_cfg0; +#[doc = "FH_CFG1 (rw) register accessor: Software triggers for fault handler actions configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fh_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fh_cfg1`] module"] +pub type FH_CFG1 = crate::Reg; +#[doc = "Software triggers for fault handler actions configuration register"] +pub mod fh_cfg1; +#[doc = "FH_STATUS (r) register accessor: Fault events status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fh_status`] module"] +pub type FH_STATUS = crate::Reg; +#[doc = "Fault events status register"] +pub mod fh_status; +#[doc = "FAULT_DETECT (rw) register accessor: Fault detection configuration and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fault_detect::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fault_detect::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fault_detect`] module"] +pub type FAULT_DETECT = crate::Reg; +#[doc = "Fault detection configuration and status register"] +pub mod fault_detect; +#[doc = "CAP_TIMER_CFG (rw) register accessor: Capture timer configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_timer_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cap_timer_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap_timer_cfg`] module"] +pub type CAP_TIMER_CFG = crate::Reg; +#[doc = "Capture timer configuration register"] +pub mod cap_timer_cfg; +#[doc = "CAP_TIMER_PHASE (rw) register accessor: Capture timer sync phase register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_timer_phase::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cap_timer_phase::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap_timer_phase`] module"] +pub type CAP_TIMER_PHASE = crate::Reg; +#[doc = "Capture timer sync phase register"] +pub mod cap_timer_phase; +#[doc = "CAP_CH_CFG (rw) register accessor: Capture channel %s configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_ch_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cap_ch_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap_ch_cfg`] module"] +pub type CAP_CH_CFG = crate::Reg; +#[doc = "Capture channel %s configuration register"] +pub mod cap_ch_cfg; +#[doc = "CAP_CH (r) register accessor: CAP%s capture value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_ch::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap_ch`] module"] +pub type CAP_CH = crate::Reg; +#[doc = "CAP%s capture value register"] +pub mod cap_ch; +#[doc = "CAP_STATUS (r) register accessor: Last capture trigger edge information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cap_status`] module"] +pub type CAP_STATUS = crate::Reg; +#[doc = "Last capture trigger edge information register"] +pub mod cap_status; +#[doc = "UPDATE_CFG (rw) register accessor: Generator Update configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`update_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`update_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@update_cfg`] module"] +pub type UPDATE_CFG = crate::Reg; +#[doc = "Generator Update configuration register"] +pub mod update_cfg; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable register"] +pub mod int_ena; +#[doc = "INT_RAW (rw) register accessor: Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Interrupt raw status register"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Interrupt masked status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Interrupt masked status register"] +pub mod int_st; +#[doc = "INT_CLR (w) register accessor: Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear register"] +pub mod int_clr; +#[doc = "EVT_EN (rw) register accessor: Event enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_en`] module"] +pub type EVT_EN = crate::Reg; +#[doc = "Event enable register"] +pub mod evt_en; +#[doc = "TASK_EN (rw) register accessor: Task enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_en`] module"] +pub type TASK_EN = crate::Reg; +#[doc = "Task enable register"] +pub mod task_en; +#[doc = "EVT_EN2 (rw) register accessor: Event enable register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_en2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_en2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_en2`] module"] +pub type EVT_EN2 = crate::Reg; +#[doc = "Event enable register2"] +pub mod evt_en2; +#[doc = "OP_TSTMP_E1 (rw) register accessor: Generator%s timer stamp E1 value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`op_tstmp_e1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`op_tstmp_e1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@op_tstmp_e1`] module"] +pub type OP_TSTMP_E1 = crate::Reg; +#[doc = "Generator%s timer stamp E1 value register"] +pub mod op_tstmp_e1; +#[doc = "OP_TSTMP_E2 (rw) register accessor: Generator%s timer stamp E2 value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`op_tstmp_e2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`op_tstmp_e2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@op_tstmp_e2`] module"] +pub type OP_TSTMP_E2 = crate::Reg; +#[doc = "Generator%s timer stamp E2 value register"] +pub mod op_tstmp_e2; +#[doc = "CLK (rw) register accessor: Global configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk`] module"] +pub type CLK = crate::Reg; +#[doc = "Global configuration register"] +pub mod clk; +#[doc = "VERSION (rw) register accessor: Version register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"] +pub type VERSION = crate::Reg; +#[doc = "Version register."] +pub mod version; diff --git a/esp32p4/src/mcpwm0/cap_ch.rs b/esp32p4/src/mcpwm0/cap_ch.rs new file mode 100644 index 0000000000..c572d48f41 --- /dev/null +++ b/esp32p4/src/mcpwm0/cap_ch.rs @@ -0,0 +1,36 @@ +#[doc = "Register `CAP_CH%s` reader"] +pub type R = crate::R; +#[doc = "Field `CAP_VALUE` reader - Represents value of last capture on CAP%s"] +pub type CAP_VALUE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Represents value of last capture on CAP%s"] + #[inline(always)] + pub fn cap_value(&self) -> CAP_VALUE_R { + CAP_VALUE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAP_CH") + .field("cap_value", &format_args!("{}", self.cap_value().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "CAP%s capture value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAP_CH_SPEC; +impl crate::RegisterSpec for CAP_CH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cap_ch::R`](R) reader structure"] +impl crate::Readable for CAP_CH_SPEC {} +#[doc = "`reset()` method sets CAP_CH%s to value 0"] +impl crate::Resettable for CAP_CH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/cap_ch_cfg.rs b/esp32p4/src/mcpwm0/cap_ch_cfg.rs new file mode 100644 index 0000000000..0f0db4afd5 --- /dev/null +++ b/esp32p4/src/mcpwm0/cap_ch_cfg.rs @@ -0,0 +1,125 @@ +#[doc = "Register `CAP_CH%s_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `CAP_CH%s_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `CAP_EN` reader - Configures whether or not to enable capture on channel %s.\\\\0: Disable\\\\1: Enable"] +pub type CAP_EN_R = crate::BitReader; +#[doc = "Field `CAP_EN` writer - Configures whether or not to enable capture on channel %s.\\\\0: Disable\\\\1: Enable"] +pub type CAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP_MODE` reader - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"] +pub type CAP_MODE_R = crate::FieldReader; +#[doc = "Field `CAP_MODE` writer - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"] +pub type CAP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CAP_PRESCALE` reader - Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1"] +pub type CAP_PRESCALE_R = crate::FieldReader; +#[doc = "Field `CAP_PRESCALE` writer - Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1"] +pub type CAP_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CAP_IN_INVERT` reader - Configures whether or not to invert CAP%s from GPIO matrix before prescale.\\\\0: Normal\\\\1: Invert"] +pub type CAP_IN_INVERT_R = crate::BitReader; +#[doc = "Field `CAP_IN_INVERT` writer - Configures whether or not to invert CAP%s from GPIO matrix before prescale.\\\\0: Normal\\\\1: Invert"] +pub type CAP_IN_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP_SW` writer - Configures the generation of software capture.\\\\0: Invalid, No effect\\\\1: Trigger a software forced capture on channel %s"] +pub type CAP_SW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable capture on channel %s.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn cap_en(&self) -> CAP_EN_R { + CAP_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"] + #[inline(always)] + pub fn cap_mode(&self) -> CAP_MODE_R { + CAP_MODE_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bits 3:10 - Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1"] + #[inline(always)] + pub fn cap_prescale(&self) -> CAP_PRESCALE_R { + CAP_PRESCALE_R::new(((self.bits >> 3) & 0xff) as u8) + } + #[doc = "Bit 11 - Configures whether or not to invert CAP%s from GPIO matrix before prescale.\\\\0: Normal\\\\1: Invert"] + #[inline(always)] + pub fn cap_in_invert(&self) -> CAP_IN_INVERT_R { + CAP_IN_INVERT_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAP_CH_CFG") + .field("cap_en", &format_args!("{}", self.cap_en().bit())) + .field("cap_mode", &format_args!("{}", self.cap_mode().bits())) + .field( + "cap_prescale", + &format_args!("{}", self.cap_prescale().bits()), + ) + .field( + "cap_in_invert", + &format_args!("{}", self.cap_in_invert().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable capture on channel %s.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn cap_en(&mut self) -> CAP_EN_W { + CAP_EN_W::new(self, 0) + } + #[doc = "Bits 1:2 - Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge"] + #[inline(always)] + #[must_use] + pub fn cap_mode(&mut self) -> CAP_MODE_W { + CAP_MODE_W::new(self, 1) + } + #[doc = "Bits 3:10 - Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1"] + #[inline(always)] + #[must_use] + pub fn cap_prescale(&mut self) -> CAP_PRESCALE_W { + CAP_PRESCALE_W::new(self, 3) + } + #[doc = "Bit 11 - Configures whether or not to invert CAP%s from GPIO matrix before prescale.\\\\0: Normal\\\\1: Invert"] + #[inline(always)] + #[must_use] + pub fn cap_in_invert(&mut self) -> CAP_IN_INVERT_W { + CAP_IN_INVERT_W::new(self, 11) + } + #[doc = "Bit 12 - Configures the generation of software capture.\\\\0: Invalid, No effect\\\\1: Trigger a software forced capture on channel %s"] + #[inline(always)] + #[must_use] + pub fn cap_sw(&mut self) -> CAP_SW_W { + CAP_SW_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Capture channel %s configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_ch_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cap_ch_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAP_CH_CFG_SPEC; +impl crate::RegisterSpec for CAP_CH_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cap_ch_cfg::R`](R) reader structure"] +impl crate::Readable for CAP_CH_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cap_ch_cfg::W`](W) writer structure"] +impl crate::Writable for CAP_CH_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAP_CH%s_CFG to value 0"] +impl crate::Resettable for CAP_CH_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/cap_status.rs b/esp32p4/src/mcpwm0/cap_status.rs new file mode 100644 index 0000000000..180e421528 --- /dev/null +++ b/esp32p4/src/mcpwm0/cap_status.rs @@ -0,0 +1,52 @@ +#[doc = "Register `CAP_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `CAP0_EDGE` reader - Represents edge of last capture trigger on channel0.\\\\0: Posedge\\\\1: Negedge"] +pub type CAP0_EDGE_R = crate::BitReader; +#[doc = "Field `CAP1_EDGE` reader - Represents edge of last capture trigger on channel1.\\\\0: Posedge\\\\1: Negedge"] +pub type CAP1_EDGE_R = crate::BitReader; +#[doc = "Field `CAP2_EDGE` reader - Represents edge of last capture trigger on channel2.\\\\0: Posedge\\\\1: Negedge"] +pub type CAP2_EDGE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Represents edge of last capture trigger on channel0.\\\\0: Posedge\\\\1: Negedge"] + #[inline(always)] + pub fn cap0_edge(&self) -> CAP0_EDGE_R { + CAP0_EDGE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents edge of last capture trigger on channel1.\\\\0: Posedge\\\\1: Negedge"] + #[inline(always)] + pub fn cap1_edge(&self) -> CAP1_EDGE_R { + CAP1_EDGE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents edge of last capture trigger on channel2.\\\\0: Posedge\\\\1: Negedge"] + #[inline(always)] + pub fn cap2_edge(&self) -> CAP2_EDGE_R { + CAP2_EDGE_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAP_STATUS") + .field("cap0_edge", &format_args!("{}", self.cap0_edge().bit())) + .field("cap1_edge", &format_args!("{}", self.cap1_edge().bit())) + .field("cap2_edge", &format_args!("{}", self.cap2_edge().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Last capture trigger edge information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAP_STATUS_SPEC; +impl crate::RegisterSpec for CAP_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cap_status::R`](R) reader structure"] +impl crate::Readable for CAP_STATUS_SPEC {} +#[doc = "`reset()` method sets CAP_STATUS to value 0"] +impl crate::Resettable for CAP_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/cap_timer_cfg.rs b/esp32p4/src/mcpwm0/cap_timer_cfg.rs new file mode 100644 index 0000000000..4695f98c52 --- /dev/null +++ b/esp32p4/src/mcpwm0/cap_timer_cfg.rs @@ -0,0 +1,112 @@ +#[doc = "Register `CAP_TIMER_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `CAP_TIMER_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `CAP_TIMER_EN` reader - Configures whether or not to enable capture timer increment.\\\\0: Disable\\\\1: Enable"] +pub type CAP_TIMER_EN_R = crate::BitReader; +#[doc = "Field `CAP_TIMER_EN` writer - Configures whether or not to enable capture timer increment.\\\\0: Disable\\\\1: Enable"] +pub type CAP_TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP_SYNCI_EN` reader - Configures whether or not to enable capture timer sync.\\\\0: Disable\\\\1: Enable"] +pub type CAP_SYNCI_EN_R = crate::BitReader; +#[doc = "Field `CAP_SYNCI_EN` writer - Configures whether or not to enable capture timer sync.\\\\0: Disable\\\\1: Enable"] +pub type CAP_SYNCI_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP_SYNCI_SEL` reader - Configures the selection of capture module sync input.\\\\0: None\\\\1: Timer0 sync_out\\\\2: Timer1 sync_out\\\\3: Timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\7: None"] +pub type CAP_SYNCI_SEL_R = crate::FieldReader; +#[doc = "Field `CAP_SYNCI_SEL` writer - Configures the selection of capture module sync input.\\\\0: None\\\\1: Timer0 sync_out\\\\2: Timer1 sync_out\\\\3: Timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\7: None"] +pub type CAP_SYNCI_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CAP_SYNC_SW` writer - Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\\\0: Invalid, No effect\\\\1: Trigger a capture timer sync, capture timer is loaded with value in phase register"] +pub type CAP_SYNC_SW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable capture timer increment.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn cap_timer_en(&self) -> CAP_TIMER_EN_R { + CAP_TIMER_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures whether or not to enable capture timer sync.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn cap_synci_en(&self) -> CAP_SYNCI_EN_R { + CAP_SYNCI_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - Configures the selection of capture module sync input.\\\\0: None\\\\1: Timer0 sync_out\\\\2: Timer1 sync_out\\\\3: Timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\7: None"] + #[inline(always)] + pub fn cap_synci_sel(&self) -> CAP_SYNCI_SEL_R { + CAP_SYNCI_SEL_R::new(((self.bits >> 2) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAP_TIMER_CFG") + .field( + "cap_timer_en", + &format_args!("{}", self.cap_timer_en().bit()), + ) + .field( + "cap_synci_en", + &format_args!("{}", self.cap_synci_en().bit()), + ) + .field( + "cap_synci_sel", + &format_args!("{}", self.cap_synci_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable capture timer increment.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn cap_timer_en(&mut self) -> CAP_TIMER_EN_W { + CAP_TIMER_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to enable capture timer sync.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn cap_synci_en(&mut self) -> CAP_SYNCI_EN_W { + CAP_SYNCI_EN_W::new(self, 1) + } + #[doc = "Bits 2:4 - Configures the selection of capture module sync input.\\\\0: None\\\\1: Timer0 sync_out\\\\2: Timer1 sync_out\\\\3: Timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\7: None"] + #[inline(always)] + #[must_use] + pub fn cap_synci_sel(&mut self) -> CAP_SYNCI_SEL_W { + CAP_SYNCI_SEL_W::new(self, 2) + } + #[doc = "Bit 5 - Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\\\0: Invalid, No effect\\\\1: Trigger a capture timer sync, capture timer is loaded with value in phase register"] + #[inline(always)] + #[must_use] + pub fn cap_sync_sw(&mut self) -> CAP_SYNC_SW_W { + CAP_SYNC_SW_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Capture timer configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_timer_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cap_timer_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAP_TIMER_CFG_SPEC; +impl crate::RegisterSpec for CAP_TIMER_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cap_timer_cfg::R`](R) reader structure"] +impl crate::Readable for CAP_TIMER_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cap_timer_cfg::W`](W) writer structure"] +impl crate::Writable for CAP_TIMER_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAP_TIMER_CFG to value 0"] +impl crate::Resettable for CAP_TIMER_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/cap_timer_phase.rs b/esp32p4/src/mcpwm0/cap_timer_phase.rs new file mode 100644 index 0000000000..4421fdd3cb --- /dev/null +++ b/esp32p4/src/mcpwm0/cap_timer_phase.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CAP_TIMER_PHASE` reader"] +pub type R = crate::R; +#[doc = "Register `CAP_TIMER_PHASE` writer"] +pub type W = crate::W; +#[doc = "Field `CAP_PHASE` reader - Configures phase value for capture timer sync operation."] +pub type CAP_PHASE_R = crate::FieldReader; +#[doc = "Field `CAP_PHASE` writer - Configures phase value for capture timer sync operation."] +pub type CAP_PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures phase value for capture timer sync operation."] + #[inline(always)] + pub fn cap_phase(&self) -> CAP_PHASE_R { + CAP_PHASE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CAP_TIMER_PHASE") + .field("cap_phase", &format_args!("{}", self.cap_phase().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures phase value for capture timer sync operation."] + #[inline(always)] + #[must_use] + pub fn cap_phase(&mut self) -> CAP_PHASE_W { + CAP_PHASE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Capture timer sync phase register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_timer_phase::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cap_timer_phase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CAP_TIMER_PHASE_SPEC; +impl crate::RegisterSpec for CAP_TIMER_PHASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cap_timer_phase::R`](R) reader structure"] +impl crate::Readable for CAP_TIMER_PHASE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cap_timer_phase::W`](W) writer structure"] +impl crate::Writable for CAP_TIMER_PHASE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CAP_TIMER_PHASE to value 0"] +impl crate::Resettable for CAP_TIMER_PHASE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/carrier_cfg.rs b/esp32p4/src/mcpwm0/carrier_cfg.rs new file mode 100644 index 0000000000..2adbe1c0f9 --- /dev/null +++ b/esp32p4/src/mcpwm0/carrier_cfg.rs @@ -0,0 +1,158 @@ +#[doc = "Register `CARRIER%s_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `CARRIER%s_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `CHOPPER_EN` reader - Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled"] +pub type CHOPPER_EN_R = crate::BitReader; +#[doc = "Field `CHOPPER_EN` writer - Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled"] +pub type CHOPPER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHOPPER_PRESCALE` reader - Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1)"] +pub type CHOPPER_PRESCALE_R = crate::FieldReader; +#[doc = "Field `CHOPPER_PRESCALE` writer - Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1)"] +pub type CHOPPER_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CHOPPER_DUTY` reader - Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8"] +pub type CHOPPER_DUTY_R = crate::FieldReader; +#[doc = "Field `CHOPPER_DUTY` writer - Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8"] +pub type CHOPPER_DUTY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CHOPPER_OSHTWTH` reader - Configures width of the first pulse. Measurement unit: Periods of the carrier."] +pub type CHOPPER_OSHTWTH_R = crate::FieldReader; +#[doc = "Field `CHOPPER_OSHTWTH` writer - Configures width of the first pulse. Measurement unit: Periods of the carrier."] +pub type CHOPPER_OSHTWTH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CHOPPER_OUT_INVERT` reader - Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] +pub type CHOPPER_OUT_INVERT_R = crate::BitReader; +#[doc = "Field `CHOPPER_OUT_INVERT` writer - Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] +pub type CHOPPER_OUT_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHOPPER_IN_INVERT` reader - Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] +pub type CHOPPER_IN_INVERT_R = crate::BitReader; +#[doc = "Field `CHOPPER_IN_INVERT` writer - Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] +pub type CHOPPER_IN_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled"] + #[inline(always)] + pub fn chopper_en(&self) -> CHOPPER_EN_R { + CHOPPER_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:4 - Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1)"] + #[inline(always)] + pub fn chopper_prescale(&self) -> CHOPPER_PRESCALE_R { + CHOPPER_PRESCALE_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bits 5:7 - Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8"] + #[inline(always)] + pub fn chopper_duty(&self) -> CHOPPER_DUTY_R { + CHOPPER_DUTY_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bits 8:11 - Configures width of the first pulse. Measurement unit: Periods of the carrier."] + #[inline(always)] + pub fn chopper_oshtwth(&self) -> CHOPPER_OSHTWTH_R { + CHOPPER_OSHTWTH_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] + #[inline(always)] + pub fn chopper_out_invert(&self) -> CHOPPER_OUT_INVERT_R { + CHOPPER_OUT_INVERT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] + #[inline(always)] + pub fn chopper_in_invert(&self) -> CHOPPER_IN_INVERT_R { + CHOPPER_IN_INVERT_R::new(((self.bits >> 13) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CARRIER_CFG") + .field("chopper_en", &format_args!("{}", self.chopper_en().bit())) + .field( + "chopper_prescale", + &format_args!("{}", self.chopper_prescale().bits()), + ) + .field( + "chopper_duty", + &format_args!("{}", self.chopper_duty().bits()), + ) + .field( + "chopper_oshtwth", + &format_args!("{}", self.chopper_oshtwth().bits()), + ) + .field( + "chopper_out_invert", + &format_args!("{}", self.chopper_out_invert().bit()), + ) + .field( + "chopper_in_invert", + &format_args!("{}", self.chopper_in_invert().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled"] + #[inline(always)] + #[must_use] + pub fn chopper_en(&mut self) -> CHOPPER_EN_W { + CHOPPER_EN_W::new(self, 0) + } + #[doc = "Bits 1:4 - Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1)"] + #[inline(always)] + #[must_use] + pub fn chopper_prescale(&mut self) -> CHOPPER_PRESCALE_W { + CHOPPER_PRESCALE_W::new(self, 1) + } + #[doc = "Bits 5:7 - Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8"] + #[inline(always)] + #[must_use] + pub fn chopper_duty(&mut self) -> CHOPPER_DUTY_W { + CHOPPER_DUTY_W::new(self, 5) + } + #[doc = "Bits 8:11 - Configures width of the first pulse. Measurement unit: Periods of the carrier."] + #[inline(always)] + #[must_use] + pub fn chopper_oshtwth(&mut self) -> CHOPPER_OSHTWTH_W { + CHOPPER_OSHTWTH_W::new(self, 8) + } + #[doc = "Bit 12 - Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] + #[inline(always)] + #[must_use] + pub fn chopper_out_invert(&mut self) -> CHOPPER_OUT_INVERT_W { + CHOPPER_OUT_INVERT_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert"] + #[inline(always)] + #[must_use] + pub fn chopper_in_invert(&mut self) -> CHOPPER_IN_INVERT_W { + CHOPPER_IN_INVERT_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Carrier%s configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`carrier_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`carrier_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CARRIER_CFG_SPEC; +impl crate::RegisterSpec for CARRIER_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`carrier_cfg::R`](R) reader structure"] +impl crate::Readable for CARRIER_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`carrier_cfg::W`](W) writer structure"] +impl crate::Writable for CARRIER_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CARRIER%s_CFG to value 0"] +impl crate::Resettable for CARRIER_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/clk.rs b/esp32p4/src/mcpwm0/clk.rs new file mode 100644 index 0000000000..4975217e72 --- /dev/null +++ b/esp32p4/src/mcpwm0/clk.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLK` reader"] +pub type R = crate::R; +#[doc = "Register `CLK` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK") + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Global configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_SPEC; +impl crate::RegisterSpec for CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk::R`](R) reader structure"] +impl crate::Readable for CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"] +impl crate::Writable for CLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK to value 0"] +impl crate::Resettable for CLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/clk_cfg.rs b/esp32p4/src/mcpwm0/clk_cfg.rs new file mode 100644 index 0000000000..9be27ec2f8 --- /dev/null +++ b/esp32p4/src/mcpwm0/clk_cfg.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CLK_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_PRESCALE` reader - Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)."] +pub type CLK_PRESCALE_R = crate::FieldReader; +#[doc = "Field `CLK_PRESCALE` writer - Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)."] +pub type CLK_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)."] + #[inline(always)] + pub fn clk_prescale(&self) -> CLK_PRESCALE_R { + CLK_PRESCALE_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_CFG") + .field( + "clk_prescale", + &format_args!("{}", self.clk_prescale().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)."] + #[inline(always)] + #[must_use] + pub fn clk_prescale(&mut self) -> CLK_PRESCALE_W { + CLK_PRESCALE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PWM clock prescaler register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_CFG_SPEC; +impl crate::RegisterSpec for CLK_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_cfg::R`](R) reader structure"] +impl crate::Readable for CLK_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_cfg::W`](W) writer structure"] +impl crate::Writable for CLK_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_CFG to value 0"] +impl crate::Resettable for CLK_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/dt_cfg.rs b/esp32p4/src/mcpwm0/dt_cfg.rs new file mode 100644 index 0000000000..abe19f62c8 --- /dev/null +++ b/esp32p4/src/mcpwm0/dt_cfg.rs @@ -0,0 +1,269 @@ +#[doc = "Register `DT%s_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `DT%s_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `DB_FED_UPMETHOD` reader - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type DB_FED_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `DB_FED_UPMETHOD` writer - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type DB_FED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DB_RED_UPMETHOD` reader - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type DB_RED_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `DB_RED_UPMETHOD` writer - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type DB_RED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DB_DEB_MODE` reader - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"] +pub type DB_DEB_MODE_R = crate::BitReader; +#[doc = "Field `DB_DEB_MODE` writer - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"] +pub type DB_DEB_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DB_A_OUTSWAP` reader - Configures S6 in table."] +pub type DB_A_OUTSWAP_R = crate::BitReader; +#[doc = "Field `DB_A_OUTSWAP` writer - Configures S6 in table."] +pub type DB_A_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DB_B_OUTSWAP` reader - Configures S7 in table."] +pub type DB_B_OUTSWAP_R = crate::BitReader; +#[doc = "Field `DB_B_OUTSWAP` writer - Configures S7 in table."] +pub type DB_B_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DB_RED_INSEL` reader - Configures S4 in table."] +pub type DB_RED_INSEL_R = crate::BitReader; +#[doc = "Field `DB_RED_INSEL` writer - Configures S4 in table."] +pub type DB_RED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DB_FED_INSEL` reader - Configures S5 in table."] +pub type DB_FED_INSEL_R = crate::BitReader; +#[doc = "Field `DB_FED_INSEL` writer - Configures S5 in table."] +pub type DB_FED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DB_RED_OUTINVERT` reader - Configures S2 in table."] +pub type DB_RED_OUTINVERT_R = crate::BitReader; +#[doc = "Field `DB_RED_OUTINVERT` writer - Configures S2 in table."] +pub type DB_RED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DB_FED_OUTINVERT` reader - Configures S3 in table."] +pub type DB_FED_OUTINVERT_R = crate::BitReader; +#[doc = "Field `DB_FED_OUTINVERT` writer - Configures S3 in table."] +pub type DB_FED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DB_A_OUTBYPASS` reader - Configures S1 in table."] +pub type DB_A_OUTBYPASS_R = crate::BitReader; +#[doc = "Field `DB_A_OUTBYPASS` writer - Configures S1 in table."] +pub type DB_A_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DB_B_OUTBYPASS` reader - Configures S0 in table."] +pub type DB_B_OUTBYPASS_R = crate::BitReader; +#[doc = "Field `DB_B_OUTBYPASS` writer - Configures S0 in table."] +pub type DB_B_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DB_CLK_SEL` reader - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"] +pub type DB_CLK_SEL_R = crate::BitReader; +#[doc = "Field `DB_CLK_SEL` writer - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"] +pub type DB_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] + #[inline(always)] + pub fn db_fed_upmethod(&self) -> DB_FED_UPMETHOD_R { + DB_FED_UPMETHOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] + #[inline(always)] + pub fn db_red_upmethod(&self) -> DB_RED_UPMETHOD_R { + DB_RED_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8 - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"] + #[inline(always)] + pub fn db_deb_mode(&self) -> DB_DEB_MODE_R { + DB_DEB_MODE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures S6 in table."] + #[inline(always)] + pub fn db_a_outswap(&self) -> DB_A_OUTSWAP_R { + DB_A_OUTSWAP_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Configures S7 in table."] + #[inline(always)] + pub fn db_b_outswap(&self) -> DB_B_OUTSWAP_R { + DB_B_OUTSWAP_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Configures S4 in table."] + #[inline(always)] + pub fn db_red_insel(&self) -> DB_RED_INSEL_R { + DB_RED_INSEL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Configures S5 in table."] + #[inline(always)] + pub fn db_fed_insel(&self) -> DB_FED_INSEL_R { + DB_FED_INSEL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures S2 in table."] + #[inline(always)] + pub fn db_red_outinvert(&self) -> DB_RED_OUTINVERT_R { + DB_RED_OUTINVERT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Configures S3 in table."] + #[inline(always)] + pub fn db_fed_outinvert(&self) -> DB_FED_OUTINVERT_R { + DB_FED_OUTINVERT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Configures S1 in table."] + #[inline(always)] + pub fn db_a_outbypass(&self) -> DB_A_OUTBYPASS_R { + DB_A_OUTBYPASS_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Configures S0 in table."] + #[inline(always)] + pub fn db_b_outbypass(&self) -> DB_B_OUTBYPASS_R { + DB_B_OUTBYPASS_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"] + #[inline(always)] + pub fn db_clk_sel(&self) -> DB_CLK_SEL_R { + DB_CLK_SEL_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DT_CFG") + .field( + "db_fed_upmethod", + &format_args!("{}", self.db_fed_upmethod().bits()), + ) + .field( + "db_red_upmethod", + &format_args!("{}", self.db_red_upmethod().bits()), + ) + .field("db_deb_mode", &format_args!("{}", self.db_deb_mode().bit())) + .field( + "db_a_outswap", + &format_args!("{}", self.db_a_outswap().bit()), + ) + .field( + "db_b_outswap", + &format_args!("{}", self.db_b_outswap().bit()), + ) + .field( + "db_red_insel", + &format_args!("{}", self.db_red_insel().bit()), + ) + .field( + "db_fed_insel", + &format_args!("{}", self.db_fed_insel().bit()), + ) + .field( + "db_red_outinvert", + &format_args!("{}", self.db_red_outinvert().bit()), + ) + .field( + "db_fed_outinvert", + &format_args!("{}", self.db_fed_outinvert().bit()), + ) + .field( + "db_a_outbypass", + &format_args!("{}", self.db_a_outbypass().bit()), + ) + .field( + "db_b_outbypass", + &format_args!("{}", self.db_b_outbypass().bit()), + ) + .field("db_clk_sel", &format_args!("{}", self.db_clk_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] + #[inline(always)] + #[must_use] + pub fn db_fed_upmethod(&mut self) -> DB_FED_UPMETHOD_W { + DB_FED_UPMETHOD_W::new(self, 0) + } + #[doc = "Bits 4:7 - Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] + #[inline(always)] + #[must_use] + pub fn db_red_upmethod(&mut self) -> DB_RED_UPMETHOD_W { + DB_RED_UPMETHOD_W::new(self, 4) + } + #[doc = "Bit 8 - Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode"] + #[inline(always)] + #[must_use] + pub fn db_deb_mode(&mut self) -> DB_DEB_MODE_W { + DB_DEB_MODE_W::new(self, 8) + } + #[doc = "Bit 9 - Configures S6 in table."] + #[inline(always)] + #[must_use] + pub fn db_a_outswap(&mut self) -> DB_A_OUTSWAP_W { + DB_A_OUTSWAP_W::new(self, 9) + } + #[doc = "Bit 10 - Configures S7 in table."] + #[inline(always)] + #[must_use] + pub fn db_b_outswap(&mut self) -> DB_B_OUTSWAP_W { + DB_B_OUTSWAP_W::new(self, 10) + } + #[doc = "Bit 11 - Configures S4 in table."] + #[inline(always)] + #[must_use] + pub fn db_red_insel(&mut self) -> DB_RED_INSEL_W { + DB_RED_INSEL_W::new(self, 11) + } + #[doc = "Bit 12 - Configures S5 in table."] + #[inline(always)] + #[must_use] + pub fn db_fed_insel(&mut self) -> DB_FED_INSEL_W { + DB_FED_INSEL_W::new(self, 12) + } + #[doc = "Bit 13 - Configures S2 in table."] + #[inline(always)] + #[must_use] + pub fn db_red_outinvert(&mut self) -> DB_RED_OUTINVERT_W { + DB_RED_OUTINVERT_W::new(self, 13) + } + #[doc = "Bit 14 - Configures S3 in table."] + #[inline(always)] + #[must_use] + pub fn db_fed_outinvert(&mut self) -> DB_FED_OUTINVERT_W { + DB_FED_OUTINVERT_W::new(self, 14) + } + #[doc = "Bit 15 - Configures S1 in table."] + #[inline(always)] + #[must_use] + pub fn db_a_outbypass(&mut self) -> DB_A_OUTBYPASS_W { + DB_A_OUTBYPASS_W::new(self, 15) + } + #[doc = "Bit 16 - Configures S0 in table."] + #[inline(always)] + #[must_use] + pub fn db_b_outbypass(&mut self) -> DB_B_OUTBYPASS_W { + DB_B_OUTBYPASS_W::new(self, 16) + } + #[doc = "Bit 17 - Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk"] + #[inline(always)] + #[must_use] + pub fn db_clk_sel(&mut self) -> DB_CLK_SEL_W { + DB_CLK_SEL_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Dead time configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DT_CFG_SPEC; +impl crate::RegisterSpec for DT_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dt_cfg::R`](R) reader structure"] +impl crate::Readable for DT_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dt_cfg::W`](W) writer structure"] +impl crate::Writable for DT_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DT%s_CFG to value 0x0001_8000"] +impl crate::Resettable for DT_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_8000; +} diff --git a/esp32p4/src/mcpwm0/dt_fed_cfg.rs b/esp32p4/src/mcpwm0/dt_fed_cfg.rs new file mode 100644 index 0000000000..b343684d73 --- /dev/null +++ b/esp32p4/src/mcpwm0/dt_fed_cfg.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DT%s_FED_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `DT%s_FED_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `DB_FED` reader - Configures shadow register for FED."] +pub type DB_FED_R = crate::FieldReader; +#[doc = "Field `DB_FED` writer - Configures shadow register for FED."] +pub type DB_FED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures shadow register for FED."] + #[inline(always)] + pub fn db_fed(&self) -> DB_FED_R { + DB_FED_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DT_FED_CFG") + .field("db_fed", &format_args!("{}", self.db_fed().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures shadow register for FED."] + #[inline(always)] + #[must_use] + pub fn db_fed(&mut self) -> DB_FED_W { + DB_FED_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Falling edge delay (FED) shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_fed_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_fed_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DT_FED_CFG_SPEC; +impl crate::RegisterSpec for DT_FED_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dt_fed_cfg::R`](R) reader structure"] +impl crate::Readable for DT_FED_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dt_fed_cfg::W`](W) writer structure"] +impl crate::Writable for DT_FED_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DT%s_FED_CFG to value 0"] +impl crate::Resettable for DT_FED_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/dt_red_cfg.rs b/esp32p4/src/mcpwm0/dt_red_cfg.rs new file mode 100644 index 0000000000..114a7f7e30 --- /dev/null +++ b/esp32p4/src/mcpwm0/dt_red_cfg.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DT%s_RED_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `DT%s_RED_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `DB_RED` reader - Configures shadow register for RED."] +pub type DB_RED_R = crate::FieldReader; +#[doc = "Field `DB_RED` writer - Configures shadow register for RED."] +pub type DB_RED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures shadow register for RED."] + #[inline(always)] + pub fn db_red(&self) -> DB_RED_R { + DB_RED_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DT_RED_CFG") + .field("db_red", &format_args!("{}", self.db_red().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures shadow register for RED."] + #[inline(always)] + #[must_use] + pub fn db_red(&mut self) -> DB_RED_W { + DB_RED_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Rising edge delay (RED) shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt_red_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt_red_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DT_RED_CFG_SPEC; +impl crate::RegisterSpec for DT_RED_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dt_red_cfg::R`](R) reader structure"] +impl crate::Readable for DT_RED_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dt_red_cfg::W`](W) writer structure"] +impl crate::Writable for DT_RED_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DT%s_RED_CFG to value 0"] +impl crate::Resettable for DT_RED_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/evt_en.rs b/esp32p4/src/mcpwm0/evt_en.rs new file mode 100644 index 0000000000..5a865f1518 --- /dev/null +++ b/esp32p4/src/mcpwm0/evt_en.rs @@ -0,0 +1,599 @@ +#[doc = "Register `EVT_EN` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_EN` writer"] +pub type W = crate::W; +#[doc = "Field `EVT_TIMER0_STOP_EN` reader - Configures whether or not to enable timer0 stop event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER0_STOP_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIMER0_STOP_EN` writer - Configures whether or not to enable timer0 stop event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER0_STOP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIMER1_STOP_EN` reader - Configures whether or not to enable timer1 stop event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER1_STOP_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIMER1_STOP_EN` writer - Configures whether or not to enable timer1 stop event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER1_STOP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIMER2_STOP_EN` reader - Configures whether or not to enable timer2 stop event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER2_STOP_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIMER2_STOP_EN` writer - Configures whether or not to enable timer2 stop event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER2_STOP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIMER0_TEZ_EN` reader - Configures whether or not to enable timer0 equal zero event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER0_TEZ_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIMER0_TEZ_EN` writer - Configures whether or not to enable timer0 equal zero event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER0_TEZ_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIMER1_TEZ_EN` reader - Configures whether or not to enable timer1 equal zero event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER1_TEZ_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIMER1_TEZ_EN` writer - Configures whether or not to enable timer1 equal zero event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER1_TEZ_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIMER2_TEZ_EN` reader - Configures whether or not to enable timer2 equal zero event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER2_TEZ_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIMER2_TEZ_EN` writer - Configures whether or not to enable timer2 equal zero event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER2_TEZ_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIMER0_TEP_EN` reader - Configures whether or not to enable timer0 equal period event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER0_TEP_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIMER0_TEP_EN` writer - Configures whether or not to enable timer0 equal period event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER0_TEP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIMER1_TEP_EN` reader - Configures whether or not to enable timer1 equal period event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER1_TEP_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIMER1_TEP_EN` writer - Configures whether or not to enable timer1 equal period event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER1_TEP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TIMER2_TEP_EN` reader - Configures whether or not to enable timer2 equal period event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER2_TEP_EN_R = crate::BitReader; +#[doc = "Field `EVT_TIMER2_TEP_EN` writer - Configures whether or not to enable timer2 equal period event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TIMER2_TEP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OP0_TEA_EN` reader - Configures whether or not to enable PWM generator0 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP0_TEA_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP0_TEA_EN` writer - Configures whether or not to enable PWM generator0 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP0_TEA_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OP1_TEA_EN` reader - Configures whether or not to enable PWM generator1 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP1_TEA_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP1_TEA_EN` writer - Configures whether or not to enable PWM generator1 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP1_TEA_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OP2_TEA_EN` reader - Configures whether or not to enable PWM generator2 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP2_TEA_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP2_TEA_EN` writer - Configures whether or not to enable PWM generator2 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP2_TEA_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OP0_TEB_EN` reader - Configures whether or not to enable PWM generator0 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP0_TEB_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP0_TEB_EN` writer - Configures whether or not to enable PWM generator0 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP0_TEB_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OP1_TEB_EN` reader - Configures whether or not to enable PWM generator1 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP1_TEB_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP1_TEB_EN` writer - Configures whether or not to enable PWM generator1 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP1_TEB_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OP2_TEB_EN` reader - Configures whether or not to enable PWM generator2 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP2_TEB_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP2_TEB_EN` writer - Configures whether or not to enable PWM generator2 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP2_TEB_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_F0_EN` reader - Configures whether or not to enable fault0 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F0_EN_R = crate::BitReader; +#[doc = "Field `EVT_F0_EN` writer - Configures whether or not to enable fault0 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_F1_EN` reader - Configures whether or not to enable fault1 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F1_EN_R = crate::BitReader; +#[doc = "Field `EVT_F1_EN` writer - Configures whether or not to enable fault1 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_F2_EN` reader - Configures whether or not to enable fault2 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F2_EN_R = crate::BitReader; +#[doc = "Field `EVT_F2_EN` writer - Configures whether or not to enable fault2 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_F0_CLR_EN` reader - Configures whether or not to enable fault0 clear event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F0_CLR_EN_R = crate::BitReader; +#[doc = "Field `EVT_F0_CLR_EN` writer - Configures whether or not to enable fault0 clear event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F0_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_F1_CLR_EN` reader - Configures whether or not to enable fault1 clear event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F1_CLR_EN_R = crate::BitReader; +#[doc = "Field `EVT_F1_CLR_EN` writer - Configures whether or not to enable fault1 clear event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F1_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_F2_CLR_EN` reader - Configures whether or not to enable fault2 clear event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F2_CLR_EN_R = crate::BitReader; +#[doc = "Field `EVT_F2_CLR_EN` writer - Configures whether or not to enable fault2 clear event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_F2_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TZ0_CBC_EN` reader - Configures whether or not to enable cycle-by-cycle trip0 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ0_CBC_EN_R = crate::BitReader; +#[doc = "Field `EVT_TZ0_CBC_EN` writer - Configures whether or not to enable cycle-by-cycle trip0 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ0_CBC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TZ1_CBC_EN` reader - Configures whether or not to enable cycle-by-cycle trip1 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ1_CBC_EN_R = crate::BitReader; +#[doc = "Field `EVT_TZ1_CBC_EN` writer - Configures whether or not to enable cycle-by-cycle trip1 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ1_CBC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TZ2_CBC_EN` reader - Configures whether or not to enable cycle-by-cycle trip2 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ2_CBC_EN_R = crate::BitReader; +#[doc = "Field `EVT_TZ2_CBC_EN` writer - Configures whether or not to enable cycle-by-cycle trip2 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ2_CBC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TZ0_OST_EN` reader - Configures whether or not to enable one-shot trip0 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ0_OST_EN_R = crate::BitReader; +#[doc = "Field `EVT_TZ0_OST_EN` writer - Configures whether or not to enable one-shot trip0 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ0_OST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TZ1_OST_EN` reader - Configures whether or not to enable one-shot trip1 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ1_OST_EN_R = crate::BitReader; +#[doc = "Field `EVT_TZ1_OST_EN` writer - Configures whether or not to enable one-shot trip1 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ1_OST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_TZ2_OST_EN` reader - Configures whether or not to enable one-shot trip2 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ2_OST_EN_R = crate::BitReader; +#[doc = "Field `EVT_TZ2_OST_EN` writer - Configures whether or not to enable one-shot trip2 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_TZ2_OST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_CAP0_EN` reader - Configures whether or not to enable capture0 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_CAP0_EN_R = crate::BitReader; +#[doc = "Field `EVT_CAP0_EN` writer - Configures whether or not to enable capture0 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_CAP0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_CAP1_EN` reader - Configures whether or not to enable capture1 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_CAP1_EN_R = crate::BitReader; +#[doc = "Field `EVT_CAP1_EN` writer - Configures whether or not to enable capture1 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_CAP1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_CAP2_EN` reader - Configures whether or not to enable capture2 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_CAP2_EN_R = crate::BitReader; +#[doc = "Field `EVT_CAP2_EN` writer - Configures whether or not to enable capture2 event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_CAP2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable timer0 stop event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_timer0_stop_en(&self) -> EVT_TIMER0_STOP_EN_R { + EVT_TIMER0_STOP_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures whether or not to enable timer1 stop event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_timer1_stop_en(&self) -> EVT_TIMER1_STOP_EN_R { + EVT_TIMER1_STOP_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures whether or not to enable timer2 stop event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_timer2_stop_en(&self) -> EVT_TIMER2_STOP_EN_R { + EVT_TIMER2_STOP_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures whether or not to enable timer0 equal zero event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_timer0_tez_en(&self) -> EVT_TIMER0_TEZ_EN_R { + EVT_TIMER0_TEZ_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures whether or not to enable timer1 equal zero event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_timer1_tez_en(&self) -> EVT_TIMER1_TEZ_EN_R { + EVT_TIMER1_TEZ_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures whether or not to enable timer2 equal zero event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_timer2_tez_en(&self) -> EVT_TIMER2_TEZ_EN_R { + EVT_TIMER2_TEZ_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Configures whether or not to enable timer0 equal period event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_timer0_tep_en(&self) -> EVT_TIMER0_TEP_EN_R { + EVT_TIMER0_TEP_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures whether or not to enable timer1 equal period event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_timer1_tep_en(&self) -> EVT_TIMER1_TEP_EN_R { + EVT_TIMER1_TEP_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configures whether or not to enable timer2 equal period event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_timer2_tep_en(&self) -> EVT_TIMER2_TEP_EN_R { + EVT_TIMER2_TEP_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures whether or not to enable PWM generator0 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op0_tea_en(&self) -> EVT_OP0_TEA_EN_R { + EVT_OP0_TEA_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Configures whether or not to enable PWM generator1 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op1_tea_en(&self) -> EVT_OP1_TEA_EN_R { + EVT_OP1_TEA_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Configures whether or not to enable PWM generator2 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op2_tea_en(&self) -> EVT_OP2_TEA_EN_R { + EVT_OP2_TEA_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Configures whether or not to enable PWM generator0 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op0_teb_en(&self) -> EVT_OP0_TEB_EN_R { + EVT_OP0_TEB_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures whether or not to enable PWM generator1 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op1_teb_en(&self) -> EVT_OP1_TEB_EN_R { + EVT_OP1_TEB_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Configures whether or not to enable PWM generator2 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op2_teb_en(&self) -> EVT_OP2_TEB_EN_R { + EVT_OP2_TEB_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Configures whether or not to enable fault0 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_f0_en(&self) -> EVT_F0_EN_R { + EVT_F0_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Configures whether or not to enable fault1 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_f1_en(&self) -> EVT_F1_EN_R { + EVT_F1_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Configures whether or not to enable fault2 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_f2_en(&self) -> EVT_F2_EN_R { + EVT_F2_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Configures whether or not to enable fault0 clear event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_f0_clr_en(&self) -> EVT_F0_CLR_EN_R { + EVT_F0_CLR_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Configures whether or not to enable fault1 clear event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_f1_clr_en(&self) -> EVT_F1_CLR_EN_R { + EVT_F1_CLR_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Configures whether or not to enable fault2 clear event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_f2_clr_en(&self) -> EVT_F2_CLR_EN_R { + EVT_F2_CLR_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Configures whether or not to enable cycle-by-cycle trip0 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_tz0_cbc_en(&self) -> EVT_TZ0_CBC_EN_R { + EVT_TZ0_CBC_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Configures whether or not to enable cycle-by-cycle trip1 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_tz1_cbc_en(&self) -> EVT_TZ1_CBC_EN_R { + EVT_TZ1_CBC_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Configures whether or not to enable cycle-by-cycle trip2 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_tz2_cbc_en(&self) -> EVT_TZ2_CBC_EN_R { + EVT_TZ2_CBC_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Configures whether or not to enable one-shot trip0 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_tz0_ost_en(&self) -> EVT_TZ0_OST_EN_R { + EVT_TZ0_OST_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Configures whether or not to enable one-shot trip1 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_tz1_ost_en(&self) -> EVT_TZ1_OST_EN_R { + EVT_TZ1_OST_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Configures whether or not to enable one-shot trip2 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_tz2_ost_en(&self) -> EVT_TZ2_OST_EN_R { + EVT_TZ2_OST_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Configures whether or not to enable capture0 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_cap0_en(&self) -> EVT_CAP0_EN_R { + EVT_CAP0_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Configures whether or not to enable capture1 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_cap1_en(&self) -> EVT_CAP1_EN_R { + EVT_CAP1_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Configures whether or not to enable capture2 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_cap2_en(&self) -> EVT_CAP2_EN_R { + EVT_CAP2_EN_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_EN") + .field( + "evt_timer0_stop_en", + &format_args!("{}", self.evt_timer0_stop_en().bit()), + ) + .field( + "evt_timer1_stop_en", + &format_args!("{}", self.evt_timer1_stop_en().bit()), + ) + .field( + "evt_timer2_stop_en", + &format_args!("{}", self.evt_timer2_stop_en().bit()), + ) + .field( + "evt_timer0_tez_en", + &format_args!("{}", self.evt_timer0_tez_en().bit()), + ) + .field( + "evt_timer1_tez_en", + &format_args!("{}", self.evt_timer1_tez_en().bit()), + ) + .field( + "evt_timer2_tez_en", + &format_args!("{}", self.evt_timer2_tez_en().bit()), + ) + .field( + "evt_timer0_tep_en", + &format_args!("{}", self.evt_timer0_tep_en().bit()), + ) + .field( + "evt_timer1_tep_en", + &format_args!("{}", self.evt_timer1_tep_en().bit()), + ) + .field( + "evt_timer2_tep_en", + &format_args!("{}", self.evt_timer2_tep_en().bit()), + ) + .field( + "evt_op0_tea_en", + &format_args!("{}", self.evt_op0_tea_en().bit()), + ) + .field( + "evt_op1_tea_en", + &format_args!("{}", self.evt_op1_tea_en().bit()), + ) + .field( + "evt_op2_tea_en", + &format_args!("{}", self.evt_op2_tea_en().bit()), + ) + .field( + "evt_op0_teb_en", + &format_args!("{}", self.evt_op0_teb_en().bit()), + ) + .field( + "evt_op1_teb_en", + &format_args!("{}", self.evt_op1_teb_en().bit()), + ) + .field( + "evt_op2_teb_en", + &format_args!("{}", self.evt_op2_teb_en().bit()), + ) + .field("evt_f0_en", &format_args!("{}", self.evt_f0_en().bit())) + .field("evt_f1_en", &format_args!("{}", self.evt_f1_en().bit())) + .field("evt_f2_en", &format_args!("{}", self.evt_f2_en().bit())) + .field( + "evt_f0_clr_en", + &format_args!("{}", self.evt_f0_clr_en().bit()), + ) + .field( + "evt_f1_clr_en", + &format_args!("{}", self.evt_f1_clr_en().bit()), + ) + .field( + "evt_f2_clr_en", + &format_args!("{}", self.evt_f2_clr_en().bit()), + ) + .field( + "evt_tz0_cbc_en", + &format_args!("{}", self.evt_tz0_cbc_en().bit()), + ) + .field( + "evt_tz1_cbc_en", + &format_args!("{}", self.evt_tz1_cbc_en().bit()), + ) + .field( + "evt_tz2_cbc_en", + &format_args!("{}", self.evt_tz2_cbc_en().bit()), + ) + .field( + "evt_tz0_ost_en", + &format_args!("{}", self.evt_tz0_ost_en().bit()), + ) + .field( + "evt_tz1_ost_en", + &format_args!("{}", self.evt_tz1_ost_en().bit()), + ) + .field( + "evt_tz2_ost_en", + &format_args!("{}", self.evt_tz2_ost_en().bit()), + ) + .field("evt_cap0_en", &format_args!("{}", self.evt_cap0_en().bit())) + .field("evt_cap1_en", &format_args!("{}", self.evt_cap1_en().bit())) + .field("evt_cap2_en", &format_args!("{}", self.evt_cap2_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable timer0 stop event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_timer0_stop_en(&mut self) -> EVT_TIMER0_STOP_EN_W { + EVT_TIMER0_STOP_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to enable timer1 stop event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_timer1_stop_en(&mut self) -> EVT_TIMER1_STOP_EN_W { + EVT_TIMER1_STOP_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to enable timer2 stop event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_timer2_stop_en(&mut self) -> EVT_TIMER2_STOP_EN_W { + EVT_TIMER2_STOP_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to enable timer0 equal zero event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_timer0_tez_en(&mut self) -> EVT_TIMER0_TEZ_EN_W { + EVT_TIMER0_TEZ_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to enable timer1 equal zero event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_timer1_tez_en(&mut self) -> EVT_TIMER1_TEZ_EN_W { + EVT_TIMER1_TEZ_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to enable timer2 equal zero event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_timer2_tez_en(&mut self) -> EVT_TIMER2_TEZ_EN_W { + EVT_TIMER2_TEZ_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to enable timer0 equal period event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_timer0_tep_en(&mut self) -> EVT_TIMER0_TEP_EN_W { + EVT_TIMER0_TEP_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to enable timer1 equal period event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_timer1_tep_en(&mut self) -> EVT_TIMER1_TEP_EN_W { + EVT_TIMER1_TEP_EN_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to enable timer2 equal period event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_timer2_tep_en(&mut self) -> EVT_TIMER2_TEP_EN_W { + EVT_TIMER2_TEP_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to enable PWM generator0 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op0_tea_en(&mut self) -> EVT_OP0_TEA_EN_W { + EVT_OP0_TEA_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to enable PWM generator1 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op1_tea_en(&mut self) -> EVT_OP1_TEA_EN_W { + EVT_OP1_TEA_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to enable PWM generator2 timer equal a event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op2_tea_en(&mut self) -> EVT_OP2_TEA_EN_W { + EVT_OP2_TEA_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to enable PWM generator0 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op0_teb_en(&mut self) -> EVT_OP0_TEB_EN_W { + EVT_OP0_TEB_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to enable PWM generator1 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op1_teb_en(&mut self) -> EVT_OP1_TEB_EN_W { + EVT_OP1_TEB_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to enable PWM generator2 timer equal b event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op2_teb_en(&mut self) -> EVT_OP2_TEB_EN_W { + EVT_OP2_TEB_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to enable fault0 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_f0_en(&mut self) -> EVT_F0_EN_W { + EVT_F0_EN_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to enable fault1 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_f1_en(&mut self) -> EVT_F1_EN_W { + EVT_F1_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to enable fault2 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_f2_en(&mut self) -> EVT_F2_EN_W { + EVT_F2_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to enable fault0 clear event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_f0_clr_en(&mut self) -> EVT_F0_CLR_EN_W { + EVT_F0_CLR_EN_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to enable fault1 clear event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_f1_clr_en(&mut self) -> EVT_F1_CLR_EN_W { + EVT_F1_CLR_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to enable fault2 clear event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_f2_clr_en(&mut self) -> EVT_F2_CLR_EN_W { + EVT_F2_CLR_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to enable cycle-by-cycle trip0 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_tz0_cbc_en(&mut self) -> EVT_TZ0_CBC_EN_W { + EVT_TZ0_CBC_EN_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to enable cycle-by-cycle trip1 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_tz1_cbc_en(&mut self) -> EVT_TZ1_CBC_EN_W { + EVT_TZ1_CBC_EN_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to enable cycle-by-cycle trip2 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_tz2_cbc_en(&mut self) -> EVT_TZ2_CBC_EN_W { + EVT_TZ2_CBC_EN_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to enable one-shot trip0 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_tz0_ost_en(&mut self) -> EVT_TZ0_OST_EN_W { + EVT_TZ0_OST_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to enable one-shot trip1 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_tz1_ost_en(&mut self) -> EVT_TZ1_OST_EN_W { + EVT_TZ1_OST_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to enable one-shot trip2 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_tz2_ost_en(&mut self) -> EVT_TZ2_OST_EN_W { + EVT_TZ2_OST_EN_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to enable capture0 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_cap0_en(&mut self) -> EVT_CAP0_EN_W { + EVT_CAP0_EN_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to enable capture1 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_cap1_en(&mut self) -> EVT_CAP1_EN_W { + EVT_CAP1_EN_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to enable capture2 event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_cap2_en(&mut self) -> EVT_CAP2_EN_W { + EVT_CAP2_EN_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Event enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_EN_SPEC; +impl crate::RegisterSpec for EVT_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_en::R`](R) reader structure"] +impl crate::Readable for EVT_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_en::W`](W) writer structure"] +impl crate::Writable for EVT_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_EN to value 0"] +impl crate::Resettable for EVT_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/evt_en2.rs b/esp32p4/src/mcpwm0/evt_en2.rs new file mode 100644 index 0000000000..91e558cb37 --- /dev/null +++ b/esp32p4/src/mcpwm0/evt_en2.rs @@ -0,0 +1,161 @@ +#[doc = "Register `EVT_EN2` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_EN2` writer"] +pub type W = crate::W; +#[doc = "Field `EVT_OP0_TEE1_EN` reader - Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP0_TEE1_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP0_TEE1_EN` writer - Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP0_TEE1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OP1_TEE1_EN` reader - Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP1_TEE1_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP1_TEE1_EN` writer - Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP1_TEE1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OP2_TEE1_EN` reader - Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP2_TEE1_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP2_TEE1_EN` writer - Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP2_TEE1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OP0_TEE2_EN` reader - Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP0_TEE2_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP0_TEE2_EN` writer - Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP0_TEE2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OP1_TEE2_EN` reader - Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP1_TEE2_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP1_TEE2_EN` writer - Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP1_TEE2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVT_OP2_TEE2_EN` reader - Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP2_TEE2_EN_R = crate::BitReader; +#[doc = "Field `EVT_OP2_TEE2_EN` writer - Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] +pub type EVT_OP2_TEE2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op0_tee1_en(&self) -> EVT_OP0_TEE1_EN_R { + EVT_OP0_TEE1_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op1_tee1_en(&self) -> EVT_OP1_TEE1_EN_R { + EVT_OP1_TEE1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op2_tee1_en(&self) -> EVT_OP2_TEE1_EN_R { + EVT_OP2_TEE1_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op0_tee2_en(&self) -> EVT_OP0_TEE2_EN_R { + EVT_OP0_TEE2_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op1_tee2_en(&self) -> EVT_OP1_TEE2_EN_R { + EVT_OP1_TEE2_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn evt_op2_tee2_en(&self) -> EVT_OP2_TEE2_EN_R { + EVT_OP2_TEE2_EN_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_EN2") + .field( + "evt_op0_tee1_en", + &format_args!("{}", self.evt_op0_tee1_en().bit()), + ) + .field( + "evt_op1_tee1_en", + &format_args!("{}", self.evt_op1_tee1_en().bit()), + ) + .field( + "evt_op2_tee1_en", + &format_args!("{}", self.evt_op2_tee1_en().bit()), + ) + .field( + "evt_op0_tee2_en", + &format_args!("{}", self.evt_op0_tee2_en().bit()), + ) + .field( + "evt_op1_tee2_en", + &format_args!("{}", self.evt_op1_tee2_en().bit()), + ) + .field( + "evt_op2_tee2_en", + &format_args!("{}", self.evt_op2_tee2_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op0_tee1_en(&mut self) -> EVT_OP0_TEE1_EN_W { + EVT_OP0_TEE1_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op1_tee1_en(&mut self) -> EVT_OP1_TEE1_EN_W { + EVT_OP1_TEE1_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op2_tee1_en(&mut self) -> EVT_OP2_TEE1_EN_W { + EVT_OP2_TEE1_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op0_tee2_en(&mut self) -> EVT_OP0_TEE2_EN_W { + EVT_OP0_TEE2_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op1_tee2_en(&mut self) -> EVT_OP1_TEE2_EN_W { + EVT_OP1_TEE2_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn evt_op2_tee2_en(&mut self) -> EVT_OP2_TEE2_EN_W { + EVT_OP2_TEE2_EN_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Event enable register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_en2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_en2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_EN2_SPEC; +impl crate::RegisterSpec for EVT_EN2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_en2::R`](R) reader structure"] +impl crate::Readable for EVT_EN2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_en2::W`](W) writer structure"] +impl crate::Writable for EVT_EN2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_EN2 to value 0"] +impl crate::Resettable for EVT_EN2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/fault_detect.rs b/esp32p4/src/mcpwm0/fault_detect.rs new file mode 100644 index 0000000000..f970e300fe --- /dev/null +++ b/esp32p4/src/mcpwm0/fault_detect.rs @@ -0,0 +1,167 @@ +#[doc = "Register `FAULT_DETECT` reader"] +pub type R = crate::R; +#[doc = "Register `FAULT_DETECT` writer"] +pub type W = crate::W; +#[doc = "Field `F0_EN` reader - Configures whether or not to enable event_f0 generation.\\\\0: Disable\\\\1: Enable"] +pub type F0_EN_R = crate::BitReader; +#[doc = "Field `F0_EN` writer - Configures whether or not to enable event_f0 generation.\\\\0: Disable\\\\1: Enable"] +pub type F0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F1_EN` reader - Configures whether or not to enable event_f1 generation.\\\\0: Disable\\\\1: Enable"] +pub type F1_EN_R = crate::BitReader; +#[doc = "Field `F1_EN` writer - Configures whether or not to enable event_f1 generation.\\\\0: Disable\\\\1: Enable"] +pub type F1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F2_EN` reader - Configures whether or not to enable event_f2 generation.\\\\0: Disable\\\\1: Enable"] +pub type F2_EN_R = crate::BitReader; +#[doc = "Field `F2_EN` writer - Configures whether or not to enable event_f2 generation.\\\\0: Disable\\\\1: Enable"] +pub type F2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F0_POLE` reader - Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] +pub type F0_POLE_R = crate::BitReader; +#[doc = "Field `F0_POLE` writer - Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] +pub type F0_POLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F1_POLE` reader - Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] +pub type F1_POLE_R = crate::BitReader; +#[doc = "Field `F1_POLE` writer - Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] +pub type F1_POLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `F2_POLE` reader - Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] +pub type F2_POLE_R = crate::BitReader; +#[doc = "Field `F2_POLE` writer - Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] +pub type F2_POLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EVENT_F0` reader - Represents whether or not an event_f0 is on going.\\\\0: No action\\\\1: On going"] +pub type EVENT_F0_R = crate::BitReader; +#[doc = "Field `EVENT_F1` reader - Represents whether or not an event_f1 is on going.\\\\0: No action\\\\1: On going"] +pub type EVENT_F1_R = crate::BitReader; +#[doc = "Field `EVENT_F2` reader - Represents whether or not an event_f2 is on going.\\\\0: No action\\\\1: On going"] +pub type EVENT_F2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable event_f0 generation.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn f0_en(&self) -> F0_EN_R { + F0_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures whether or not to enable event_f1 generation.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn f1_en(&self) -> F1_EN_R { + F1_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures whether or not to enable event_f2 generation.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn f2_en(&self) -> F2_EN_R { + F2_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] + #[inline(always)] + pub fn f0_pole(&self) -> F0_POLE_R { + F0_POLE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] + #[inline(always)] + pub fn f1_pole(&self) -> F1_POLE_R { + F1_POLE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] + #[inline(always)] + pub fn f2_pole(&self) -> F2_POLE_R { + F2_POLE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents whether or not an event_f0 is on going.\\\\0: No action\\\\1: On going"] + #[inline(always)] + pub fn event_f0(&self) -> EVENT_F0_R { + EVENT_F0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents whether or not an event_f1 is on going.\\\\0: No action\\\\1: On going"] + #[inline(always)] + pub fn event_f1(&self) -> EVENT_F1_R { + EVENT_F1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents whether or not an event_f2 is on going.\\\\0: No action\\\\1: On going"] + #[inline(always)] + pub fn event_f2(&self) -> EVENT_F2_R { + EVENT_F2_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FAULT_DETECT") + .field("f0_en", &format_args!("{}", self.f0_en().bit())) + .field("f1_en", &format_args!("{}", self.f1_en().bit())) + .field("f2_en", &format_args!("{}", self.f2_en().bit())) + .field("f0_pole", &format_args!("{}", self.f0_pole().bit())) + .field("f1_pole", &format_args!("{}", self.f1_pole().bit())) + .field("f2_pole", &format_args!("{}", self.f2_pole().bit())) + .field("event_f0", &format_args!("{}", self.event_f0().bit())) + .field("event_f1", &format_args!("{}", self.event_f1().bit())) + .field("event_f2", &format_args!("{}", self.event_f2().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable event_f0 generation.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn f0_en(&mut self) -> F0_EN_W { + F0_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to enable event_f1 generation.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn f1_en(&mut self) -> F1_EN_W { + F1_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to enable event_f2 generation.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn f2_en(&mut self) -> F2_EN_W { + F2_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] + #[inline(always)] + #[must_use] + pub fn f0_pole(&mut self) -> F0_POLE_W { + F0_POLE_W::new(self, 3) + } + #[doc = "Bit 4 - Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] + #[inline(always)] + #[must_use] + pub fn f1_pole(&mut self) -> F1_POLE_W { + F1_POLE_W::new(self, 4) + } + #[doc = "Bit 5 - Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\\\0: Level low\\\\1: Level high"] + #[inline(always)] + #[must_use] + pub fn f2_pole(&mut self) -> F2_POLE_W { + F2_POLE_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Fault detection configuration and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fault_detect::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fault_detect::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FAULT_DETECT_SPEC; +impl crate::RegisterSpec for FAULT_DETECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fault_detect::R`](R) reader structure"] +impl crate::Readable for FAULT_DETECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fault_detect::W`](W) writer structure"] +impl crate::Writable for FAULT_DETECT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FAULT_DETECT to value 0"] +impl crate::Resettable for FAULT_DETECT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/fh_cfg0.rs b/esp32p4/src/mcpwm0/fh_cfg0.rs new file mode 100644 index 0000000000..85266e6c85 --- /dev/null +++ b/esp32p4/src/mcpwm0/fh_cfg0.rs @@ -0,0 +1,303 @@ +#[doc = "Register `FH%s_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `FH%s_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `TZ_SW_CBC` reader - Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_SW_CBC_R = crate::BitReader; +#[doc = "Field `TZ_SW_CBC` writer - Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_SW_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ_F2_CBC` reader - Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F2_CBC_R = crate::BitReader; +#[doc = "Field `TZ_F2_CBC` writer - Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ_F1_CBC` reader - Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F1_CBC_R = crate::BitReader; +#[doc = "Field `TZ_F1_CBC` writer - Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ_F0_CBC` reader - Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F0_CBC_R = crate::BitReader; +#[doc = "Field `TZ_F0_CBC` writer - Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ_SW_OST` reader - Configures whether or not to enable software force one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_SW_OST_R = crate::BitReader; +#[doc = "Field `TZ_SW_OST` writer - Configures whether or not to enable software force one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_SW_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ_F2_OST` reader - Configures whether or not event_f2 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F2_OST_R = crate::BitReader; +#[doc = "Field `TZ_F2_OST` writer - Configures whether or not event_f2 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F2_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ_F1_OST` reader - Configures whether or not event_f1 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F1_OST_R = crate::BitReader; +#[doc = "Field `TZ_F1_OST` writer - Configures whether or not event_f1 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F1_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ_F0_OST` reader - Configures whether or not event_f0 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F0_OST_R = crate::BitReader; +#[doc = "Field `TZ_F0_OST` writer - Configures whether or not event_f0 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] +pub type TZ_F0_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ_A_CBC_D` reader - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_A_CBC_D_R = crate::FieldReader; +#[doc = "Field `TZ_A_CBC_D` writer - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_A_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TZ_A_CBC_U` reader - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_A_CBC_U_R = crate::FieldReader; +#[doc = "Field `TZ_A_CBC_U` writer - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_A_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TZ_A_OST_D` reader - Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_A_OST_D_R = crate::FieldReader; +#[doc = "Field `TZ_A_OST_D` writer - Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_A_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TZ_A_OST_U` reader - Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_A_OST_U_R = crate::FieldReader; +#[doc = "Field `TZ_A_OST_U` writer - Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_A_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TZ_B_CBC_D` reader - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_B_CBC_D_R = crate::FieldReader; +#[doc = "Field `TZ_B_CBC_D` writer - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_B_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TZ_B_CBC_U` reader - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_B_CBC_U_R = crate::FieldReader; +#[doc = "Field `TZ_B_CBC_U` writer - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_B_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TZ_B_OST_D` reader - Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_B_OST_D_R = crate::FieldReader; +#[doc = "Field `TZ_B_OST_D` writer - Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_B_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TZ_B_OST_U` reader - Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_B_OST_U_R = crate::FieldReader; +#[doc = "Field `TZ_B_OST_U` writer - Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] +pub type TZ_B_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn tz_sw_cbc(&self) -> TZ_SW_CBC_R { + TZ_SW_CBC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn tz_f2_cbc(&self) -> TZ_F2_CBC_R { + TZ_F2_CBC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn tz_f1_cbc(&self) -> TZ_F1_CBC_R { + TZ_F1_CBC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn tz_f0_cbc(&self) -> TZ_F0_CBC_R { + TZ_F0_CBC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures whether or not to enable software force one-shot mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn tz_sw_ost(&self) -> TZ_SW_OST_R { + TZ_SW_OST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures whether or not event_f2 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn tz_f2_ost(&self) -> TZ_F2_OST_R { + TZ_F2_OST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Configures whether or not event_f1 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn tz_f1_ost(&self) -> TZ_F1_OST_R { + TZ_F1_OST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures whether or not event_f0 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn tz_f0_ost(&self) -> TZ_F0_OST_R { + TZ_F0_OST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + pub fn tz_a_cbc_d(&self) -> TZ_A_CBC_D_R { + TZ_A_CBC_D_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + pub fn tz_a_cbc_u(&self) -> TZ_A_CBC_U_R { + TZ_A_CBC_U_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + pub fn tz_a_ost_d(&self) -> TZ_A_OST_D_R { + TZ_A_OST_D_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + pub fn tz_a_ost_u(&self) -> TZ_A_OST_U_R { + TZ_A_OST_U_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + pub fn tz_b_cbc_d(&self) -> TZ_B_CBC_D_R { + TZ_B_CBC_D_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + pub fn tz_b_cbc_u(&self) -> TZ_B_CBC_U_R { + TZ_B_CBC_U_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + pub fn tz_b_ost_d(&self) -> TZ_B_OST_D_R { + TZ_B_OST_D_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + pub fn tz_b_ost_u(&self) -> TZ_B_OST_U_R { + TZ_B_OST_U_R::new(((self.bits >> 22) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FH_CFG0") + .field("tz_sw_cbc", &format_args!("{}", self.tz_sw_cbc().bit())) + .field("tz_f2_cbc", &format_args!("{}", self.tz_f2_cbc().bit())) + .field("tz_f1_cbc", &format_args!("{}", self.tz_f1_cbc().bit())) + .field("tz_f0_cbc", &format_args!("{}", self.tz_f0_cbc().bit())) + .field("tz_sw_ost", &format_args!("{}", self.tz_sw_ost().bit())) + .field("tz_f2_ost", &format_args!("{}", self.tz_f2_ost().bit())) + .field("tz_f1_ost", &format_args!("{}", self.tz_f1_ost().bit())) + .field("tz_f0_ost", &format_args!("{}", self.tz_f0_ost().bit())) + .field("tz_a_cbc_d", &format_args!("{}", self.tz_a_cbc_d().bits())) + .field("tz_a_cbc_u", &format_args!("{}", self.tz_a_cbc_u().bits())) + .field("tz_a_ost_d", &format_args!("{}", self.tz_a_ost_d().bits())) + .field("tz_a_ost_u", &format_args!("{}", self.tz_a_ost_u().bits())) + .field("tz_b_cbc_d", &format_args!("{}", self.tz_b_cbc_d().bits())) + .field("tz_b_cbc_u", &format_args!("{}", self.tz_b_cbc_u().bits())) + .field("tz_b_ost_d", &format_args!("{}", self.tz_b_ost_d().bits())) + .field("tz_b_ost_u", &format_args!("{}", self.tz_b_ost_u().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn tz_sw_cbc(&mut self) -> TZ_SW_CBC_W { + TZ_SW_CBC_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn tz_f2_cbc(&mut self) -> TZ_F2_CBC_W { + TZ_F2_CBC_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn tz_f1_cbc(&mut self) -> TZ_F1_CBC_W { + TZ_F1_CBC_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn tz_f0_cbc(&mut self) -> TZ_F0_CBC_W { + TZ_F0_CBC_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to enable software force one-shot mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn tz_sw_ost(&mut self) -> TZ_SW_OST_W { + TZ_SW_OST_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not event_f2 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn tz_f2_ost(&mut self) -> TZ_F2_OST_W { + TZ_F2_OST_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not event_f1 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn tz_f1_ost(&mut self) -> TZ_F1_OST_W { + TZ_F1_OST_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not event_f0 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn tz_f0_ost(&mut self) -> TZ_F0_OST_W { + TZ_F0_OST_W::new(self, 7) + } + #[doc = "Bits 8:9 - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn tz_a_cbc_d(&mut self) -> TZ_A_CBC_D_W { + TZ_A_CBC_D_W::new(self, 8) + } + #[doc = "Bits 10:11 - Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn tz_a_cbc_u(&mut self) -> TZ_A_CBC_U_W { + TZ_A_CBC_U_W::new(self, 10) + } + #[doc = "Bits 12:13 - Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn tz_a_ost_d(&mut self) -> TZ_A_OST_D_W { + TZ_A_OST_D_W::new(self, 12) + } + #[doc = "Bits 14:15 - Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn tz_a_ost_u(&mut self) -> TZ_A_OST_U_W { + TZ_A_OST_U_W::new(self, 14) + } + #[doc = "Bits 16:17 - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn tz_b_cbc_d(&mut self) -> TZ_B_CBC_D_W { + TZ_B_CBC_D_W::new(self, 16) + } + #[doc = "Bits 18:19 - Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn tz_b_cbc_u(&mut self) -> TZ_B_CBC_U_W { + TZ_B_CBC_U_W::new(self, 18) + } + #[doc = "Bits 20:21 - Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn tz_b_ost_d(&mut self) -> TZ_B_OST_D_W { + TZ_B_OST_D_W::new(self, 20) + } + #[doc = "Bits 22:23 - Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn tz_b_ost_u(&mut self) -> TZ_B_OST_U_W { + TZ_B_OST_U_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PWM%s A and PWM%s B trip events actions configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fh_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FH_CFG0_SPEC; +impl crate::RegisterSpec for FH_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fh_cfg0::R`](R) reader structure"] +impl crate::Readable for FH_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fh_cfg0::W`](W) writer structure"] +impl crate::Writable for FH_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FH%s_CFG0 to value 0"] +impl crate::Resettable for FH_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/fh_cfg1.rs b/esp32p4/src/mcpwm0/fh_cfg1.rs new file mode 100644 index 0000000000..2d3b483ddd --- /dev/null +++ b/esp32p4/src/mcpwm0/fh_cfg1.rs @@ -0,0 +1,120 @@ +#[doc = "Register `FH%s_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `FH%s_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `TZ_CLR_OST` reader - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."] +pub type TZ_CLR_OST_R = crate::BitReader; +#[doc = "Field `TZ_CLR_OST` writer - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."] +pub type TZ_CLR_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ_CBCPULSE` reader - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"] +pub type TZ_CBCPULSE_R = crate::FieldReader; +#[doc = "Field `TZ_CBCPULSE` writer - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"] +pub type TZ_CBCPULSE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TZ_FORCE_CBC` reader - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."] +pub type TZ_FORCE_CBC_R = crate::BitReader; +#[doc = "Field `TZ_FORCE_CBC` writer - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."] +pub type TZ_FORCE_CBC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ_FORCE_OST` reader - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."] +pub type TZ_FORCE_OST_R = crate::BitReader; +#[doc = "Field `TZ_FORCE_OST` writer - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."] +pub type TZ_FORCE_OST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."] + #[inline(always)] + pub fn tz_clr_ost(&self) -> TZ_CLR_OST_R { + TZ_CLR_OST_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"] + #[inline(always)] + pub fn tz_cbcpulse(&self) -> TZ_CBCPULSE_R { + TZ_CBCPULSE_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."] + #[inline(always)] + pub fn tz_force_cbc(&self) -> TZ_FORCE_CBC_R { + TZ_FORCE_CBC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."] + #[inline(always)] + pub fn tz_force_ost(&self) -> TZ_FORCE_OST_R { + TZ_FORCE_OST_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FH_CFG1") + .field("tz_clr_ost", &format_args!("{}", self.tz_clr_ost().bit())) + .field( + "tz_cbcpulse", + &format_args!("{}", self.tz_cbcpulse().bits()), + ) + .field( + "tz_force_cbc", + &format_args!("{}", self.tz_force_cbc().bit()), + ) + .field( + "tz_force_ost", + &format_args!("{}", self.tz_force_ost().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."] + #[inline(always)] + #[must_use] + pub fn tz_clr_ost(&mut self) -> TZ_CLR_OST_W { + TZ_CLR_OST_W::new(self, 0) + } + #[doc = "Bits 1:2 - Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP"] + #[inline(always)] + #[must_use] + pub fn tz_cbcpulse(&mut self) -> TZ_CBCPULSE_W { + TZ_CBCPULSE_W::new(self, 1) + } + #[doc = "Bit 3 - Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action."] + #[inline(always)] + #[must_use] + pub fn tz_force_cbc(&mut self) -> TZ_FORCE_CBC_W { + TZ_FORCE_CBC_W::new(self, 3) + } + #[doc = "Bit 4 - Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action."] + #[inline(always)] + #[must_use] + pub fn tz_force_ost(&mut self) -> TZ_FORCE_OST_W { + TZ_FORCE_OST_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Software triggers for fault handler actions configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fh_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FH_CFG1_SPEC; +impl crate::RegisterSpec for FH_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fh_cfg1::R`](R) reader structure"] +impl crate::Readable for FH_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fh_cfg1::W`](W) writer structure"] +impl crate::Writable for FH_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FH%s_CFG1 to value 0"] +impl crate::Resettable for FH_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/fh_status.rs b/esp32p4/src/mcpwm0/fh_status.rs new file mode 100644 index 0000000000..2f79a15f14 --- /dev/null +++ b/esp32p4/src/mcpwm0/fh_status.rs @@ -0,0 +1,44 @@ +#[doc = "Register `FH%s_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `TZ_CBC_ON` reader - Represents whether or not an cycle-by-cycle mode action is on going.\\\\0:No action\\\\1: On going"] +pub type TZ_CBC_ON_R = crate::BitReader; +#[doc = "Field `TZ_OST_ON` reader - Represents whether or not an one-shot mode action is on going.\\\\0:No action\\\\1: On going"] +pub type TZ_OST_ON_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Represents whether or not an cycle-by-cycle mode action is on going.\\\\0:No action\\\\1: On going"] + #[inline(always)] + pub fn tz_cbc_on(&self) -> TZ_CBC_ON_R { + TZ_CBC_ON_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents whether or not an one-shot mode action is on going.\\\\0:No action\\\\1: On going"] + #[inline(always)] + pub fn tz_ost_on(&self) -> TZ_OST_ON_R { + TZ_OST_ON_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FH_STATUS") + .field("tz_cbc_on", &format_args!("{}", self.tz_cbc_on().bit())) + .field("tz_ost_on", &format_args!("{}", self.tz_ost_on().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Fault events status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FH_STATUS_SPEC; +impl crate::RegisterSpec for FH_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fh_status::R`](R) reader structure"] +impl crate::Readable for FH_STATUS_SPEC {} +#[doc = "`reset()` method sets FH%s_STATUS to value 0"] +impl crate::Resettable for FH_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/gen_a.rs b/esp32p4/src/mcpwm0/gen_a.rs new file mode 100644 index 0000000000..06d8e7347c --- /dev/null +++ b/esp32p4/src/mcpwm0/gen_a.rs @@ -0,0 +1,239 @@ +#[doc = "Register `GEN%s_A` reader"] +pub type R = crate::R; +#[doc = "Register `GEN%s_A` writer"] +pub type W = crate::W; +#[doc = "Field `UTEZ` reader - Configures action on PWM%s A triggered by event TEZ when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEZ_R = crate::FieldReader; +#[doc = "Field `UTEZ` writer - Configures action on PWM%s A triggered by event TEZ when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEZ_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `UTEP` reader - Configures action on PWM%s A triggered by event TEP when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEP_R = crate::FieldReader; +#[doc = "Field `UTEP` writer - Configures action on PWM%s A triggered by event TEP when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `UTEA` reader - Configures action on PWM%s A triggered by event TEA when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEA_R = crate::FieldReader; +#[doc = "Field `UTEA` writer - Configures action on PWM%s A triggered by event TEA when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `UTEB` reader - Configures action on PWM%s A triggered by event TEB when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEB_R = crate::FieldReader; +#[doc = "Field `UTEB` writer - Configures action on PWM%s A triggered by event TEB when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `UT0` reader - Configures action on PWM%s A triggered by event_t0 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UT0_R = crate::FieldReader; +#[doc = "Field `UT0` writer - Configures action on PWM%s A triggered by event_t0 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `UT1` reader - Configures action on PWM%s A triggered by event_t1 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UT1_R = crate::FieldReader; +#[doc = "Field `UT1` writer - Configures action on PWM%s A triggered by event_t1 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DTEZ` reader - Configures action on PWM%s A triggered by event TEZ when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEZ_R = crate::FieldReader; +#[doc = "Field `DTEZ` writer - Configures action on PWM%s A triggered by event TEZ when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEZ_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DTEP` reader - Configures action on PWM%s A triggered by event TEP when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEP_R = crate::FieldReader; +#[doc = "Field `DTEP` writer - Configures action on PWM%s A triggered by event TEP when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DTEA` reader - Configures action on PWM%s A triggered by event TEA when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEA_R = crate::FieldReader; +#[doc = "Field `DTEA` writer - Configures action on PWM%s A triggered by event TEA when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DTEB` reader - Configures action on PWM%s A triggered by event TEB when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEB_R = crate::FieldReader; +#[doc = "Field `DTEB` writer - Configures action on PWM%s A triggered by event TEB when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DT0` reader - Configures action on PWM%s A triggered by event_t0 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DT0_R = crate::FieldReader; +#[doc = "Field `DT0` writer - Configures action on PWM%s A triggered by event_t0 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DT1` reader - Configures action on PWM%s A triggered by event_t1 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DT1_R = crate::FieldReader; +#[doc = "Field `DT1` writer - Configures action on PWM%s A triggered by event_t1 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Configures action on PWM%s A triggered by event TEZ when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn utez(&self) -> UTEZ_R { + UTEZ_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Configures action on PWM%s A triggered by event TEP when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn utep(&self) -> UTEP_R { + UTEP_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Configures action on PWM%s A triggered by event TEA when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn utea(&self) -> UTEA_R { + UTEA_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Configures action on PWM%s A triggered by event TEB when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn uteb(&self) -> UTEB_R { + UTEB_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Configures action on PWM%s A triggered by event_t0 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn ut0(&self) -> UT0_R { + UT0_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Configures action on PWM%s A triggered by event_t1 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn ut1(&self) -> UT1_R { + UT1_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Configures action on PWM%s A triggered by event TEZ when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dtez(&self) -> DTEZ_R { + DTEZ_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Configures action on PWM%s A triggered by event TEP when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dtep(&self) -> DTEP_R { + DTEP_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Configures action on PWM%s A triggered by event TEA when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dtea(&self) -> DTEA_R { + DTEA_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Configures action on PWM%s A triggered by event TEB when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dteb(&self) -> DTEB_R { + DTEB_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Configures action on PWM%s A triggered by event_t0 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dt0(&self) -> DT0_R { + DT0_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Configures action on PWM%s A triggered by event_t1 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dt1(&self) -> DT1_R { + DT1_R::new(((self.bits >> 22) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_A") + .field("utez", &format_args!("{}", self.utez().bits())) + .field("utep", &format_args!("{}", self.utep().bits())) + .field("utea", &format_args!("{}", self.utea().bits())) + .field("uteb", &format_args!("{}", self.uteb().bits())) + .field("ut0", &format_args!("{}", self.ut0().bits())) + .field("ut1", &format_args!("{}", self.ut1().bits())) + .field("dtez", &format_args!("{}", self.dtez().bits())) + .field("dtep", &format_args!("{}", self.dtep().bits())) + .field("dtea", &format_args!("{}", self.dtea().bits())) + .field("dteb", &format_args!("{}", self.dteb().bits())) + .field("dt0", &format_args!("{}", self.dt0().bits())) + .field("dt1", &format_args!("{}", self.dt1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Configures action on PWM%s A triggered by event TEZ when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn utez(&mut self) -> UTEZ_W { + UTEZ_W::new(self, 0) + } + #[doc = "Bits 2:3 - Configures action on PWM%s A triggered by event TEP when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn utep(&mut self) -> UTEP_W { + UTEP_W::new(self, 2) + } + #[doc = "Bits 4:5 - Configures action on PWM%s A triggered by event TEA when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn utea(&mut self) -> UTEA_W { + UTEA_W::new(self, 4) + } + #[doc = "Bits 6:7 - Configures action on PWM%s A triggered by event TEB when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn uteb(&mut self) -> UTEB_W { + UTEB_W::new(self, 6) + } + #[doc = "Bits 8:9 - Configures action on PWM%s A triggered by event_t0 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn ut0(&mut self) -> UT0_W { + UT0_W::new(self, 8) + } + #[doc = "Bits 10:11 - Configures action on PWM%s A triggered by event_t1 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn ut1(&mut self) -> UT1_W { + UT1_W::new(self, 10) + } + #[doc = "Bits 12:13 - Configures action on PWM%s A triggered by event TEZ when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dtez(&mut self) -> DTEZ_W { + DTEZ_W::new(self, 12) + } + #[doc = "Bits 14:15 - Configures action on PWM%s A triggered by event TEP when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dtep(&mut self) -> DTEP_W { + DTEP_W::new(self, 14) + } + #[doc = "Bits 16:17 - Configures action on PWM%s A triggered by event TEA when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dtea(&mut self) -> DTEA_W { + DTEA_W::new(self, 16) + } + #[doc = "Bits 18:19 - Configures action on PWM%s A triggered by event TEB when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dteb(&mut self) -> DTEB_W { + DTEB_W::new(self, 18) + } + #[doc = "Bits 20:21 - Configures action on PWM%s A triggered by event_t0 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dt0(&mut self) -> DT0_W { + DT0_W::new(self, 20) + } + #[doc = "Bits 22:23 - Configures action on PWM%s A triggered by event_t1 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dt1(&mut self) -> DT1_W { + DT1_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PWM%s output signal A actions configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_A_SPEC; +impl crate::RegisterSpec for GEN_A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gen_a::R`](R) reader structure"] +impl crate::Readable for GEN_A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_a::W`](W) writer structure"] +impl crate::Writable for GEN_A_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GEN%s_A to value 0"] +impl crate::Resettable for GEN_A_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/gen_b.rs b/esp32p4/src/mcpwm0/gen_b.rs new file mode 100644 index 0000000000..1922461071 --- /dev/null +++ b/esp32p4/src/mcpwm0/gen_b.rs @@ -0,0 +1,239 @@ +#[doc = "Register `GEN%s_B` reader"] +pub type R = crate::R; +#[doc = "Register `GEN%s_B` writer"] +pub type W = crate::W; +#[doc = "Field `UTEZ` reader - Configures action on PWM%s B triggered by event TEZ when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEZ_R = crate::FieldReader; +#[doc = "Field `UTEZ` writer - Configures action on PWM%s B triggered by event TEZ when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEZ_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `UTEP` reader - Configures action on PWM%s B triggered by event TEP when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEP_R = crate::FieldReader; +#[doc = "Field `UTEP` writer - Configures action on PWM%s B triggered by event TEP when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `UTEA` reader - Configures action on PWM%s B triggered by event TEA when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEA_R = crate::FieldReader; +#[doc = "Field `UTEA` writer - Configures action on PWM%s B triggered by event TEA when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `UTEB` reader - Configures action on PWM%s B triggered by event TEB when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEB_R = crate::FieldReader; +#[doc = "Field `UTEB` writer - Configures action on PWM%s B triggered by event TEB when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UTEB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `UT0` reader - Configures action on PWM%s B triggered by event_t0 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UT0_R = crate::FieldReader; +#[doc = "Field `UT0` writer - Configures action on PWM%s B triggered by event_t0 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `UT1` reader - Configures action on PWM%s B triggered by event_t1 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UT1_R = crate::FieldReader; +#[doc = "Field `UT1` writer - Configures action on PWM%s B triggered by event_t1 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type UT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DTEZ` reader - Configures action on PWM%s B triggered by event TEZ when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEZ_R = crate::FieldReader; +#[doc = "Field `DTEZ` writer - Configures action on PWM%s B triggered by event TEZ when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEZ_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DTEP` reader - Configures action on PWM%s B triggered by event TEP when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEP_R = crate::FieldReader; +#[doc = "Field `DTEP` writer - Configures action on PWM%s B triggered by event TEP when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DTEA` reader - Configures action on PWM%s B triggered by event TEA when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEA_R = crate::FieldReader; +#[doc = "Field `DTEA` writer - Configures action on PWM%s B triggered by event TEA when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DTEB` reader - Configures action on PWM%s B triggered by event TEB when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEB_R = crate::FieldReader; +#[doc = "Field `DTEB` writer - Configures action on PWM%s B triggered by event TEB when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DTEB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DT0` reader - Configures action on PWM%s B triggered by event_t0 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DT0_R = crate::FieldReader; +#[doc = "Field `DT0` writer - Configures action on PWM%s B triggered by event_t0 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DT1` reader - Configures action on PWM%s B triggered by event_t1 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DT1_R = crate::FieldReader; +#[doc = "Field `DT1` writer - Configures action on PWM%s B triggered by event_t1 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] +pub type DT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Configures action on PWM%s B triggered by event TEZ when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn utez(&self) -> UTEZ_R { + UTEZ_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Configures action on PWM%s B triggered by event TEP when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn utep(&self) -> UTEP_R { + UTEP_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Configures action on PWM%s B triggered by event TEA when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn utea(&self) -> UTEA_R { + UTEA_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Configures action on PWM%s B triggered by event TEB when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn uteb(&self) -> UTEB_R { + UTEB_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Configures action on PWM%s B triggered by event_t0 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn ut0(&self) -> UT0_R { + UT0_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Configures action on PWM%s B triggered by event_t1 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn ut1(&self) -> UT1_R { + UT1_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Configures action on PWM%s B triggered by event TEZ when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dtez(&self) -> DTEZ_R { + DTEZ_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Configures action on PWM%s B triggered by event TEP when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dtep(&self) -> DTEP_R { + DTEP_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - Configures action on PWM%s B triggered by event TEA when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dtea(&self) -> DTEA_R { + DTEA_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Configures action on PWM%s B triggered by event TEB when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dteb(&self) -> DTEB_R { + DTEB_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - Configures action on PWM%s B triggered by event_t0 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dt0(&self) -> DT0_R { + DT0_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Configures action on PWM%s B triggered by event_t1 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + pub fn dt1(&self) -> DT1_R { + DT1_R::new(((self.bits >> 22) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_B") + .field("utez", &format_args!("{}", self.utez().bits())) + .field("utep", &format_args!("{}", self.utep().bits())) + .field("utea", &format_args!("{}", self.utea().bits())) + .field("uteb", &format_args!("{}", self.uteb().bits())) + .field("ut0", &format_args!("{}", self.ut0().bits())) + .field("ut1", &format_args!("{}", self.ut1().bits())) + .field("dtez", &format_args!("{}", self.dtez().bits())) + .field("dtep", &format_args!("{}", self.dtep().bits())) + .field("dtea", &format_args!("{}", self.dtea().bits())) + .field("dteb", &format_args!("{}", self.dteb().bits())) + .field("dt0", &format_args!("{}", self.dt0().bits())) + .field("dt1", &format_args!("{}", self.dt1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Configures action on PWM%s B triggered by event TEZ when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn utez(&mut self) -> UTEZ_W { + UTEZ_W::new(self, 0) + } + #[doc = "Bits 2:3 - Configures action on PWM%s B triggered by event TEP when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn utep(&mut self) -> UTEP_W { + UTEP_W::new(self, 2) + } + #[doc = "Bits 4:5 - Configures action on PWM%s B triggered by event TEA when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn utea(&mut self) -> UTEA_W { + UTEA_W::new(self, 4) + } + #[doc = "Bits 6:7 - Configures action on PWM%s B triggered by event TEB when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn uteb(&mut self) -> UTEB_W { + UTEB_W::new(self, 6) + } + #[doc = "Bits 8:9 - Configures action on PWM%s B triggered by event_t0 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn ut0(&mut self) -> UT0_W { + UT0_W::new(self, 8) + } + #[doc = "Bits 10:11 - Configures action on PWM%s B triggered by event_t1 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn ut1(&mut self) -> UT1_W { + UT1_W::new(self, 10) + } + #[doc = "Bits 12:13 - Configures action on PWM%s B triggered by event TEZ when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dtez(&mut self) -> DTEZ_W { + DTEZ_W::new(self, 12) + } + #[doc = "Bits 14:15 - Configures action on PWM%s B triggered by event TEP when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dtep(&mut self) -> DTEP_W { + DTEP_W::new(self, 14) + } + #[doc = "Bits 16:17 - Configures action on PWM%s B triggered by event TEA when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dtea(&mut self) -> DTEA_W { + DTEA_W::new(self, 16) + } + #[doc = "Bits 18:19 - Configures action on PWM%s B triggered by event TEB when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dteb(&mut self) -> DTEB_W { + DTEB_W::new(self, 18) + } + #[doc = "Bits 20:21 - Configures action on PWM%s B triggered by event_t0 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dt0(&mut self) -> DT0_W { + DT0_W::new(self, 20) + } + #[doc = "Bits 22:23 - Configures action on PWM%s B triggered by event_t1 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"] + #[inline(always)] + #[must_use] + pub fn dt1(&mut self) -> DT1_W { + DT1_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PWM%s output signal B actions configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_b::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_b::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_B_SPEC; +impl crate::RegisterSpec for GEN_B_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gen_b::R`](R) reader structure"] +impl crate::Readable for GEN_B_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_b::W`](W) writer structure"] +impl crate::Writable for GEN_B_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GEN%s_B to value 0"] +impl crate::Resettable for GEN_B_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/gen_cfg0.rs b/esp32p4/src/mcpwm0/gen_cfg0.rs new file mode 100644 index 0000000000..d3d37bb76e --- /dev/null +++ b/esp32p4/src/mcpwm0/gen_cfg0.rs @@ -0,0 +1,98 @@ +#[doc = "Register `GEN%s_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `GEN%s_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `GEN_CFG_UPMETHOD` reader - Configures update method for PWM generator %s's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type GEN_CFG_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `GEN_CFG_UPMETHOD` writer - Configures update method for PWM generator %s's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type GEN_CFG_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `GEN_T0_SEL` reader - Configures source selection for PWM generator %s event_t0, take effect immediately.\\\\0: fault_event0\\\\1: fault_event1\\\\2: fault_event2\\\\3: sync_taken\\\\4: Invalid, Select nothing"] +pub type GEN_T0_SEL_R = crate::FieldReader; +#[doc = "Field `GEN_T0_SEL` writer - Configures source selection for PWM generator %s event_t0, take effect immediately.\\\\0: fault_event0\\\\1: fault_event1\\\\2: fault_event2\\\\3: sync_taken\\\\4: Invalid, Select nothing"] +pub type GEN_T0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `GEN_T1_SEL` reader - Configures source selection for PWM generator %s event_t1, take effect immediately.\\\\0: fault_event0\\\\1: fault_event1\\\\2: fault_event2\\\\3: sync_taken\\\\4: Invalid, Select nothing"] +pub type GEN_T1_SEL_R = crate::FieldReader; +#[doc = "Field `GEN_T1_SEL` writer - Configures source selection for PWM generator %s event_t1, take effect immediately.\\\\0: fault_event0\\\\1: fault_event1\\\\2: fault_event2\\\\3: sync_taken\\\\4: Invalid, Select nothing"] +pub type GEN_T1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:3 - Configures update method for PWM generator %s's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] + #[inline(always)] + pub fn gen_cfg_upmethod(&self) -> GEN_CFG_UPMETHOD_R { + GEN_CFG_UPMETHOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - Configures source selection for PWM generator %s event_t0, take effect immediately.\\\\0: fault_event0\\\\1: fault_event1\\\\2: fault_event2\\\\3: sync_taken\\\\4: Invalid, Select nothing"] + #[inline(always)] + pub fn gen_t0_sel(&self) -> GEN_T0_SEL_R { + GEN_T0_SEL_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bits 7:9 - Configures source selection for PWM generator %s event_t1, take effect immediately.\\\\0: fault_event0\\\\1: fault_event1\\\\2: fault_event2\\\\3: sync_taken\\\\4: Invalid, Select nothing"] + #[inline(always)] + pub fn gen_t1_sel(&self) -> GEN_T1_SEL_R { + GEN_T1_SEL_R::new(((self.bits >> 7) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_CFG0") + .field( + "gen_cfg_upmethod", + &format_args!("{}", self.gen_cfg_upmethod().bits()), + ) + .field("gen_t0_sel", &format_args!("{}", self.gen_t0_sel().bits())) + .field("gen_t1_sel", &format_args!("{}", self.gen_t1_sel().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Configures update method for PWM generator %s's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] + #[inline(always)] + #[must_use] + pub fn gen_cfg_upmethod(&mut self) -> GEN_CFG_UPMETHOD_W { + GEN_CFG_UPMETHOD_W::new(self, 0) + } + #[doc = "Bits 4:6 - Configures source selection for PWM generator %s event_t0, take effect immediately.\\\\0: fault_event0\\\\1: fault_event1\\\\2: fault_event2\\\\3: sync_taken\\\\4: Invalid, Select nothing"] + #[inline(always)] + #[must_use] + pub fn gen_t0_sel(&mut self) -> GEN_T0_SEL_W { + GEN_T0_SEL_W::new(self, 4) + } + #[doc = "Bits 7:9 - Configures source selection for PWM generator %s event_t1, take effect immediately.\\\\0: fault_event0\\\\1: fault_event1\\\\2: fault_event2\\\\3: sync_taken\\\\4: Invalid, Select nothing"] + #[inline(always)] + #[must_use] + pub fn gen_t1_sel(&mut self) -> GEN_T1_SEL_W { + GEN_T1_SEL_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Generator%s fault event T0 and T1 configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_CFG0_SPEC; +impl crate::RegisterSpec for GEN_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gen_cfg0::R`](R) reader structure"] +impl crate::Readable for GEN_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_cfg0::W`](W) writer structure"] +impl crate::Writable for GEN_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GEN%s_CFG0 to value 0"] +impl crate::Resettable for GEN_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/gen_force.rs b/esp32p4/src/mcpwm0/gen_force.rs new file mode 100644 index 0000000000..f1428acca8 --- /dev/null +++ b/esp32p4/src/mcpwm0/gen_force.rs @@ -0,0 +1,180 @@ +#[doc = "Register `GEN%s_FORCE` reader"] +pub type R = crate::R; +#[doc = "Register `GEN%s_FORCE` writer"] +pub type W = crate::W; +#[doc = "Field `GEN_CNTUFORCE_UPMETHOD` reader - Configures update method for continuous software force of PWM generator%s.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: TEA\\\\Bit3 is set to 1: TEB\\\\Bit4 is set to 1: Sync\\\\Bit5 is set to 1: Disable update. TEA/B here and below means an event generated when the timer's value equals to that of register A/B."] +pub type GEN_CNTUFORCE_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `GEN_CNTUFORCE_UPMETHOD` writer - Configures update method for continuous software force of PWM generator%s.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: TEA\\\\Bit3 is set to 1: TEB\\\\Bit4 is set to 1: Sync\\\\Bit5 is set to 1: Disable update. TEA/B here and below means an event generated when the timer's value equals to that of register A/B."] +pub type GEN_CNTUFORCE_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `GEN_A_CNTUFORCE_MODE` reader - Configures continuous software force mode for PWM%s A.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] +pub type GEN_A_CNTUFORCE_MODE_R = crate::FieldReader; +#[doc = "Field `GEN_A_CNTUFORCE_MODE` writer - Configures continuous software force mode for PWM%s A.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] +pub type GEN_A_CNTUFORCE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GEN_B_CNTUFORCE_MODE` reader - Configures continuous software force mode for PWM%s B.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] +pub type GEN_B_CNTUFORCE_MODE_R = crate::FieldReader; +#[doc = "Field `GEN_B_CNTUFORCE_MODE` writer - Configures continuous software force mode for PWM%s B.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] +pub type GEN_B_CNTUFORCE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GEN_A_NCIFORCE` reader - Configures the generation of non-continuous immediate software-force event for PWM%s A, a toggle will trigger a force event."] +pub type GEN_A_NCIFORCE_R = crate::BitReader; +#[doc = "Field `GEN_A_NCIFORCE` writer - Configures the generation of non-continuous immediate software-force event for PWM%s A, a toggle will trigger a force event."] +pub type GEN_A_NCIFORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GEN_A_NCIFORCE_MODE` reader - Configures non-continuous immediate software force mode for PWM%s A.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] +pub type GEN_A_NCIFORCE_MODE_R = crate::FieldReader; +#[doc = "Field `GEN_A_NCIFORCE_MODE` writer - Configures non-continuous immediate software force mode for PWM%s A.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] +pub type GEN_A_NCIFORCE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GEN_B_NCIFORCE` reader - Configures the generation of non-continuous immediate software-force event for PWM%s B, a toggle will trigger a force event."] +pub type GEN_B_NCIFORCE_R = crate::BitReader; +#[doc = "Field `GEN_B_NCIFORCE` writer - Configures the generation of non-continuous immediate software-force event for PWM%s B, a toggle will trigger a force event."] +pub type GEN_B_NCIFORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GEN_B_NCIFORCE_MODE` reader - Configures non-continuous immediate software force mode for PWM%s B.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] +pub type GEN_B_NCIFORCE_MODE_R = crate::FieldReader; +#[doc = "Field `GEN_B_NCIFORCE_MODE` writer - Configures non-continuous immediate software force mode for PWM%s B.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] +pub type GEN_B_NCIFORCE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:5 - Configures update method for continuous software force of PWM generator%s.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: TEA\\\\Bit3 is set to 1: TEB\\\\Bit4 is set to 1: Sync\\\\Bit5 is set to 1: Disable update. TEA/B here and below means an event generated when the timer's value equals to that of register A/B."] + #[inline(always)] + pub fn gen_cntuforce_upmethod(&self) -> GEN_CNTUFORCE_UPMETHOD_R { + GEN_CNTUFORCE_UPMETHOD_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:7 - Configures continuous software force mode for PWM%s A.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] + #[inline(always)] + pub fn gen_a_cntuforce_mode(&self) -> GEN_A_CNTUFORCE_MODE_R { + GEN_A_CNTUFORCE_MODE_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Configures continuous software force mode for PWM%s B.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] + #[inline(always)] + pub fn gen_b_cntuforce_mode(&self) -> GEN_B_CNTUFORCE_MODE_R { + GEN_B_CNTUFORCE_MODE_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - Configures the generation of non-continuous immediate software-force event for PWM%s A, a toggle will trigger a force event."] + #[inline(always)] + pub fn gen_a_nciforce(&self) -> GEN_A_NCIFORCE_R { + GEN_A_NCIFORCE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 11:12 - Configures non-continuous immediate software force mode for PWM%s A.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] + #[inline(always)] + pub fn gen_a_nciforce_mode(&self) -> GEN_A_NCIFORCE_MODE_R { + GEN_A_NCIFORCE_MODE_R::new(((self.bits >> 11) & 3) as u8) + } + #[doc = "Bit 13 - Configures the generation of non-continuous immediate software-force event for PWM%s B, a toggle will trigger a force event."] + #[inline(always)] + pub fn gen_b_nciforce(&self) -> GEN_B_NCIFORCE_R { + GEN_B_NCIFORCE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:15 - Configures non-continuous immediate software force mode for PWM%s B.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] + #[inline(always)] + pub fn gen_b_nciforce_mode(&self) -> GEN_B_NCIFORCE_MODE_R { + GEN_B_NCIFORCE_MODE_R::new(((self.bits >> 14) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_FORCE") + .field( + "gen_cntuforce_upmethod", + &format_args!("{}", self.gen_cntuforce_upmethod().bits()), + ) + .field( + "gen_a_cntuforce_mode", + &format_args!("{}", self.gen_a_cntuforce_mode().bits()), + ) + .field( + "gen_b_cntuforce_mode", + &format_args!("{}", self.gen_b_cntuforce_mode().bits()), + ) + .field( + "gen_a_nciforce", + &format_args!("{}", self.gen_a_nciforce().bit()), + ) + .field( + "gen_a_nciforce_mode", + &format_args!("{}", self.gen_a_nciforce_mode().bits()), + ) + .field( + "gen_b_nciforce", + &format_args!("{}", self.gen_b_nciforce().bit()), + ) + .field( + "gen_b_nciforce_mode", + &format_args!("{}", self.gen_b_nciforce_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - Configures update method for continuous software force of PWM generator%s.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: TEA\\\\Bit3 is set to 1: TEB\\\\Bit4 is set to 1: Sync\\\\Bit5 is set to 1: Disable update. TEA/B here and below means an event generated when the timer's value equals to that of register A/B."] + #[inline(always)] + #[must_use] + pub fn gen_cntuforce_upmethod(&mut self) -> GEN_CNTUFORCE_UPMETHOD_W { + GEN_CNTUFORCE_UPMETHOD_W::new(self, 0) + } + #[doc = "Bits 6:7 - Configures continuous software force mode for PWM%s A.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] + #[inline(always)] + #[must_use] + pub fn gen_a_cntuforce_mode(&mut self) -> GEN_A_CNTUFORCE_MODE_W { + GEN_A_CNTUFORCE_MODE_W::new(self, 6) + } + #[doc = "Bits 8:9 - Configures continuous software force mode for PWM%s B.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] + #[inline(always)] + #[must_use] + pub fn gen_b_cntuforce_mode(&mut self) -> GEN_B_CNTUFORCE_MODE_W { + GEN_B_CNTUFORCE_MODE_W::new(self, 8) + } + #[doc = "Bit 10 - Configures the generation of non-continuous immediate software-force event for PWM%s A, a toggle will trigger a force event."] + #[inline(always)] + #[must_use] + pub fn gen_a_nciforce(&mut self) -> GEN_A_NCIFORCE_W { + GEN_A_NCIFORCE_W::new(self, 10) + } + #[doc = "Bits 11:12 - Configures non-continuous immediate software force mode for PWM%s A.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] + #[inline(always)] + #[must_use] + pub fn gen_a_nciforce_mode(&mut self) -> GEN_A_NCIFORCE_MODE_W { + GEN_A_NCIFORCE_MODE_W::new(self, 11) + } + #[doc = "Bit 13 - Configures the generation of non-continuous immediate software-force event for PWM%s B, a toggle will trigger a force event."] + #[inline(always)] + #[must_use] + pub fn gen_b_nciforce(&mut self) -> GEN_B_NCIFORCE_W { + GEN_B_NCIFORCE_W::new(self, 13) + } + #[doc = "Bits 14:15 - Configures non-continuous immediate software force mode for PWM%s B.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled"] + #[inline(always)] + #[must_use] + pub fn gen_b_nciforce_mode(&mut self) -> GEN_B_NCIFORCE_MODE_W { + GEN_B_NCIFORCE_MODE_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Generator%s output signal force mode register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_force::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_force::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_FORCE_SPEC; +impl crate::RegisterSpec for GEN_FORCE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gen_force::R`](R) reader structure"] +impl crate::Readable for GEN_FORCE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_force::W`](W) writer structure"] +impl crate::Writable for GEN_FORCE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GEN%s_FORCE to value 0x20"] +impl crate::Resettable for GEN_FORCE_SPEC { + const RESET_VALUE: Self::Ux = 0x20; +} diff --git a/esp32p4/src/mcpwm0/gen_stmp_cfg.rs b/esp32p4/src/mcpwm0/gen_stmp_cfg.rs new file mode 100644 index 0000000000..8ae2341ca6 --- /dev/null +++ b/esp32p4/src/mcpwm0/gen_stmp_cfg.rs @@ -0,0 +1,123 @@ +#[doc = "Register `GEN%s_STMP_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `GEN%s_STMP_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `CMPR_A_UPMETHOD` reader - Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type CMPR_A_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `CMPR_A_UPMETHOD` writer - Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type CMPR_A_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CMPR_B_UPMETHOD` reader - Configures the update method for PWM generator %s time stamp B's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type CMPR_B_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `CMPR_B_UPMETHOD` writer - Configures the update method for PWM generator %s time stamp B's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] +pub type CMPR_B_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CMPR_A_SHDW_FULL` reader - Represents whether or not generator%s time stamp A's shadow reg is transferred.\\\\0: A's active reg has been updated with shadow register latest value.\\\\1: A's shadow reg is filled and waiting to be transferred to A's active reg"] +pub type CMPR_A_SHDW_FULL_R = crate::BitReader; +#[doc = "Field `CMPR_A_SHDW_FULL` writer - Represents whether or not generator%s time stamp A's shadow reg is transferred.\\\\0: A's active reg has been updated with shadow register latest value.\\\\1: A's shadow reg is filled and waiting to be transferred to A's active reg"] +pub type CMPR_A_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR_B_SHDW_FULL` reader - Represents whether or not generator%s time stamp B's shadow reg is transferred.\\\\0: B's active reg has been updated with shadow register latest value.\\\\1: B's shadow reg is filled and waiting to be transferred to B's active reg"] +pub type CMPR_B_SHDW_FULL_R = crate::BitReader; +#[doc = "Field `CMPR_B_SHDW_FULL` writer - Represents whether or not generator%s time stamp B's shadow reg is transferred.\\\\0: B's active reg has been updated with shadow register latest value.\\\\1: B's shadow reg is filled and waiting to be transferred to B's active reg"] +pub type CMPR_B_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] + #[inline(always)] + pub fn cmpr_a_upmethod(&self) -> CMPR_A_UPMETHOD_R { + CMPR_A_UPMETHOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Configures the update method for PWM generator %s time stamp B's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] + #[inline(always)] + pub fn cmpr_b_upmethod(&self) -> CMPR_B_UPMETHOD_R { + CMPR_B_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8 - Represents whether or not generator%s time stamp A's shadow reg is transferred.\\\\0: A's active reg has been updated with shadow register latest value.\\\\1: A's shadow reg is filled and waiting to be transferred to A's active reg"] + #[inline(always)] + pub fn cmpr_a_shdw_full(&self) -> CMPR_A_SHDW_FULL_R { + CMPR_A_SHDW_FULL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents whether or not generator%s time stamp B's shadow reg is transferred.\\\\0: B's active reg has been updated with shadow register latest value.\\\\1: B's shadow reg is filled and waiting to be transferred to B's active reg"] + #[inline(always)] + pub fn cmpr_b_shdw_full(&self) -> CMPR_B_SHDW_FULL_R { + CMPR_B_SHDW_FULL_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_STMP_CFG") + .field( + "cmpr_a_upmethod", + &format_args!("{}", self.cmpr_a_upmethod().bits()), + ) + .field( + "cmpr_b_upmethod", + &format_args!("{}", self.cmpr_b_upmethod().bits()), + ) + .field( + "cmpr_a_shdw_full", + &format_args!("{}", self.cmpr_a_shdw_full().bit()), + ) + .field( + "cmpr_b_shdw_full", + &format_args!("{}", self.cmpr_b_shdw_full().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] + #[inline(always)] + #[must_use] + pub fn cmpr_a_upmethod(&mut self) -> CMPR_A_UPMETHOD_W { + CMPR_A_UPMETHOD_W::new(self, 0) + } + #[doc = "Bits 4:7 - Configures the update method for PWM generator %s time stamp B's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"] + #[inline(always)] + #[must_use] + pub fn cmpr_b_upmethod(&mut self) -> CMPR_B_UPMETHOD_W { + CMPR_B_UPMETHOD_W::new(self, 4) + } + #[doc = "Bit 8 - Represents whether or not generator%s time stamp A's shadow reg is transferred.\\\\0: A's active reg has been updated with shadow register latest value.\\\\1: A's shadow reg is filled and waiting to be transferred to A's active reg"] + #[inline(always)] + #[must_use] + pub fn cmpr_a_shdw_full(&mut self) -> CMPR_A_SHDW_FULL_W { + CMPR_A_SHDW_FULL_W::new(self, 8) + } + #[doc = "Bit 9 - Represents whether or not generator%s time stamp B's shadow reg is transferred.\\\\0: B's active reg has been updated with shadow register latest value.\\\\1: B's shadow reg is filled and waiting to be transferred to B's active reg"] + #[inline(always)] + #[must_use] + pub fn cmpr_b_shdw_full(&mut self) -> CMPR_B_SHDW_FULL_W { + CMPR_B_SHDW_FULL_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Generator%s time stamp registers A and B transfer status and update method register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_stmp_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_stmp_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_STMP_CFG_SPEC; +impl crate::RegisterSpec for GEN_STMP_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gen_stmp_cfg::R`](R) reader structure"] +impl crate::Readable for GEN_STMP_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_stmp_cfg::W`](W) writer structure"] +impl crate::Writable for GEN_STMP_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GEN%s_STMP_CFG to value 0"] +impl crate::Resettable for GEN_STMP_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/gen_tstmp_a.rs b/esp32p4/src/mcpwm0/gen_tstmp_a.rs new file mode 100644 index 0000000000..09c230fbe5 --- /dev/null +++ b/esp32p4/src/mcpwm0/gen_tstmp_a.rs @@ -0,0 +1,63 @@ +#[doc = "Register `GEN%s_TSTMP_A` reader"] +pub type R = crate::R; +#[doc = "Register `GEN%s_TSTMP_A` writer"] +pub type W = crate::W; +#[doc = "Field `CMPR_A` reader - Configures the value of PWM generator %s time stamp A's shadow register."] +pub type CMPR_A_R = crate::FieldReader; +#[doc = "Field `CMPR_A` writer - Configures the value of PWM generator %s time stamp A's shadow register."] +pub type CMPR_A_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures the value of PWM generator %s time stamp A's shadow register."] + #[inline(always)] + pub fn cmpr_a(&self) -> CMPR_A_R { + CMPR_A_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_TSTMP_A") + .field("cmpr_a", &format_args!("{}", self.cmpr_a().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures the value of PWM generator %s time stamp A's shadow register."] + #[inline(always)] + #[must_use] + pub fn cmpr_a(&mut self) -> CMPR_A_W { + CMPR_A_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Generator%s time stamp A's shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_tstmp_a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_tstmp_a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_TSTMP_A_SPEC; +impl crate::RegisterSpec for GEN_TSTMP_A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gen_tstmp_a::R`](R) reader structure"] +impl crate::Readable for GEN_TSTMP_A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_tstmp_a::W`](W) writer structure"] +impl crate::Writable for GEN_TSTMP_A_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GEN%s_TSTMP_A to value 0"] +impl crate::Resettable for GEN_TSTMP_A_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/gen_tstmp_b.rs b/esp32p4/src/mcpwm0/gen_tstmp_b.rs new file mode 100644 index 0000000000..6a3aca0d02 --- /dev/null +++ b/esp32p4/src/mcpwm0/gen_tstmp_b.rs @@ -0,0 +1,63 @@ +#[doc = "Register `GEN%s_TSTMP_B` reader"] +pub type R = crate::R; +#[doc = "Register `GEN%s_TSTMP_B` writer"] +pub type W = crate::W; +#[doc = "Field `CMPR_B` reader - Configures the value of PWM generator %s time stamp B's shadow register."] +pub type CMPR_B_R = crate::FieldReader; +#[doc = "Field `CMPR_B` writer - Configures the value of PWM generator %s time stamp B's shadow register."] +pub type CMPR_B_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures the value of PWM generator %s time stamp B's shadow register."] + #[inline(always)] + pub fn cmpr_b(&self) -> CMPR_B_R { + CMPR_B_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_TSTMP_B") + .field("cmpr_b", &format_args!("{}", self.cmpr_b().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures the value of PWM generator %s time stamp B's shadow register."] + #[inline(always)] + #[must_use] + pub fn cmpr_b(&mut self) -> CMPR_B_W { + CMPR_B_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Generator%s time stamp B's shadow register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_tstmp_b::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_tstmp_b::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_TSTMP_B_SPEC; +impl crate::RegisterSpec for GEN_TSTMP_B_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gen_tstmp_b::R`](R) reader structure"] +impl crate::Readable for GEN_TSTMP_B_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_tstmp_b::W`](W) writer structure"] +impl crate::Writable for GEN_TSTMP_B_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GEN%s_TSTMP_B to value 0"] +impl crate::Resettable for GEN_TSTMP_B_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/int_clr.rs b/esp32p4/src/mcpwm0/int_clr.rs new file mode 100644 index 0000000000..9a91dc61d0 --- /dev/null +++ b/esp32p4/src/mcpwm0/int_clr.rs @@ -0,0 +1,274 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER0_STOP_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops."] +pub type TIMER0_STOP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_STOP_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops."] +pub type TIMER1_STOP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_STOP_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops."] +pub type TIMER2_STOP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER0_TEZ_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event."] +pub type TIMER0_TEZ_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_TEZ_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event."] +pub type TIMER1_TEZ_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_TEZ_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event."] +pub type TIMER2_TEZ_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER0_TEP_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event."] +pub type TIMER0_TEP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_TEP_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event."] +pub type TIMER1_TEP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_TEP_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event."] +pub type TIMER2_TEP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT0_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts."] +pub type FAULT0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT1_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts."] +pub type FAULT1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT2_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts."] +pub type FAULT2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT0_CLR_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears."] +pub type FAULT0_CLR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT1_CLR_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears."] +pub type FAULT1_CLR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT2_CLR_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears."] +pub type FAULT2_CLR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR0_TEA_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event"] +pub type CMPR0_TEA_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR1_TEA_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event"] +pub type CMPR1_TEA_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR2_TEA_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event"] +pub type CMPR2_TEA_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR0_TEB_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event"] +pub type CMPR0_TEB_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR1_TEB_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event"] +pub type CMPR1_TEB_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR2_TEB_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event"] +pub type CMPR2_TEB_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ0_CBC_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."] +pub type TZ0_CBC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ1_CBC_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."] +pub type TZ1_CBC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ2_CBC_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."] +pub type TZ2_CBC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ0_OST_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM0."] +pub type TZ0_OST_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ1_OST_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM1."] +pub type TZ1_OST_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ2_OST_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM2."] +pub type TZ2_OST_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP0_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0."] +pub type CAP0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP1_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1."] +pub type CAP1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP2_INT_CLR` writer - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2."] +pub type CAP2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops."] + #[inline(always)] + #[must_use] + pub fn timer0_stop_int_clr(&mut self) -> TIMER0_STOP_INT_CLR_W { + TIMER0_STOP_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops."] + #[inline(always)] + #[must_use] + pub fn timer1_stop_int_clr(&mut self) -> TIMER1_STOP_INT_CLR_W { + TIMER1_STOP_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops."] + #[inline(always)] + #[must_use] + pub fn timer2_stop_int_clr(&mut self) -> TIMER2_STOP_INT_CLR_W { + TIMER2_STOP_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event."] + #[inline(always)] + #[must_use] + pub fn timer0_tez_int_clr(&mut self) -> TIMER0_TEZ_INT_CLR_W { + TIMER0_TEZ_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event."] + #[inline(always)] + #[must_use] + pub fn timer1_tez_int_clr(&mut self) -> TIMER1_TEZ_INT_CLR_W { + TIMER1_TEZ_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event."] + #[inline(always)] + #[must_use] + pub fn timer2_tez_int_clr(&mut self) -> TIMER2_TEZ_INT_CLR_W { + TIMER2_TEZ_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event."] + #[inline(always)] + #[must_use] + pub fn timer0_tep_int_clr(&mut self) -> TIMER0_TEP_INT_CLR_W { + TIMER0_TEP_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event."] + #[inline(always)] + #[must_use] + pub fn timer1_tep_int_clr(&mut self) -> TIMER1_TEP_INT_CLR_W { + TIMER1_TEP_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event."] + #[inline(always)] + #[must_use] + pub fn timer2_tep_int_clr(&mut self) -> TIMER2_TEP_INT_CLR_W { + TIMER2_TEP_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts."] + #[inline(always)] + #[must_use] + pub fn fault0_int_clr(&mut self) -> FAULT0_INT_CLR_W { + FAULT0_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts."] + #[inline(always)] + #[must_use] + pub fn fault1_int_clr(&mut self) -> FAULT1_INT_CLR_W { + FAULT1_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts."] + #[inline(always)] + #[must_use] + pub fn fault2_int_clr(&mut self) -> FAULT2_INT_CLR_W { + FAULT2_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears."] + #[inline(always)] + #[must_use] + pub fn fault0_clr_int_clr(&mut self) -> FAULT0_CLR_INT_CLR_W { + FAULT0_CLR_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears."] + #[inline(always)] + #[must_use] + pub fn fault1_clr_int_clr(&mut self) -> FAULT1_CLR_INT_CLR_W { + FAULT1_CLR_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears."] + #[inline(always)] + #[must_use] + pub fn fault2_clr_int_clr(&mut self) -> FAULT2_CLR_INT_CLR_W { + FAULT2_CLR_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event"] + #[inline(always)] + #[must_use] + pub fn cmpr0_tea_int_clr(&mut self) -> CMPR0_TEA_INT_CLR_W { + CMPR0_TEA_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event"] + #[inline(always)] + #[must_use] + pub fn cmpr1_tea_int_clr(&mut self) -> CMPR1_TEA_INT_CLR_W { + CMPR1_TEA_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event"] + #[inline(always)] + #[must_use] + pub fn cmpr2_tea_int_clr(&mut self) -> CMPR2_TEA_INT_CLR_W { + CMPR2_TEA_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event"] + #[inline(always)] + #[must_use] + pub fn cmpr0_teb_int_clr(&mut self) -> CMPR0_TEB_INT_CLR_W { + CMPR0_TEB_INT_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event"] + #[inline(always)] + #[must_use] + pub fn cmpr1_teb_int_clr(&mut self) -> CMPR1_TEB_INT_CLR_W { + CMPR1_TEB_INT_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event"] + #[inline(always)] + #[must_use] + pub fn cmpr2_teb_int_clr(&mut self) -> CMPR2_TEB_INT_CLR_W { + CMPR2_TEB_INT_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."] + #[inline(always)] + #[must_use] + pub fn tz0_cbc_int_clr(&mut self) -> TZ0_CBC_INT_CLR_W { + TZ0_CBC_INT_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."] + #[inline(always)] + #[must_use] + pub fn tz1_cbc_int_clr(&mut self) -> TZ1_CBC_INT_CLR_W { + TZ1_CBC_INT_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."] + #[inline(always)] + #[must_use] + pub fn tz2_cbc_int_clr(&mut self) -> TZ2_CBC_INT_CLR_W { + TZ2_CBC_INT_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM0."] + #[inline(always)] + #[must_use] + pub fn tz0_ost_int_clr(&mut self) -> TZ0_OST_INT_CLR_W { + TZ0_OST_INT_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM1."] + #[inline(always)] + #[must_use] + pub fn tz1_ost_int_clr(&mut self) -> TZ1_OST_INT_CLR_W { + TZ1_OST_INT_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM2."] + #[inline(always)] + #[must_use] + pub fn tz2_ost_int_clr(&mut self) -> TZ2_OST_INT_CLR_W { + TZ2_OST_INT_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0."] + #[inline(always)] + #[must_use] + pub fn cap0_int_clr(&mut self) -> CAP0_INT_CLR_W { + CAP0_INT_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1."] + #[inline(always)] + #[must_use] + pub fn cap1_int_clr(&mut self) -> CAP1_INT_CLR_W { + CAP1_INT_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2."] + #[inline(always)] + #[must_use] + pub fn cap2_int_clr(&mut self) -> CAP2_INT_CLR_W { + CAP2_INT_CLR_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/int_ena.rs b/esp32p4/src/mcpwm0/int_ena.rs new file mode 100644 index 0000000000..03cd4f9b43 --- /dev/null +++ b/esp32p4/src/mcpwm0/int_ena.rs @@ -0,0 +1,617 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER0_STOP_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."] +pub type TIMER0_STOP_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER0_STOP_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."] +pub type TIMER0_STOP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_STOP_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."] +pub type TIMER1_STOP_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER1_STOP_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."] +pub type TIMER1_STOP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_STOP_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."] +pub type TIMER2_STOP_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER2_STOP_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."] +pub type TIMER2_STOP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER0_TEZ_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."] +pub type TIMER0_TEZ_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER0_TEZ_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."] +pub type TIMER0_TEZ_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_TEZ_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."] +pub type TIMER1_TEZ_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER1_TEZ_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."] +pub type TIMER1_TEZ_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_TEZ_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."] +pub type TIMER2_TEZ_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER2_TEZ_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."] +pub type TIMER2_TEZ_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER0_TEP_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."] +pub type TIMER0_TEP_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER0_TEP_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."] +pub type TIMER0_TEP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_TEP_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."] +pub type TIMER1_TEP_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER1_TEP_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."] +pub type TIMER1_TEP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_TEP_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."] +pub type TIMER2_TEP_INT_ENA_R = crate::BitReader; +#[doc = "Field `TIMER2_TEP_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."] +pub type TIMER2_TEP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT0_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."] +pub type FAULT0_INT_ENA_R = crate::BitReader; +#[doc = "Field `FAULT0_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."] +pub type FAULT0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT1_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."] +pub type FAULT1_INT_ENA_R = crate::BitReader; +#[doc = "Field `FAULT1_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."] +pub type FAULT1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT2_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."] +pub type FAULT2_INT_ENA_R = crate::BitReader; +#[doc = "Field `FAULT2_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."] +pub type FAULT2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT0_CLR_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."] +pub type FAULT0_CLR_INT_ENA_R = crate::BitReader; +#[doc = "Field `FAULT0_CLR_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."] +pub type FAULT0_CLR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT1_CLR_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."] +pub type FAULT1_CLR_INT_ENA_R = crate::BitReader; +#[doc = "Field `FAULT1_CLR_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."] +pub type FAULT1_CLR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT2_CLR_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."] +pub type FAULT2_CLR_INT_ENA_R = crate::BitReader; +#[doc = "Field `FAULT2_CLR_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."] +pub type FAULT2_CLR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR0_TEA_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."] +pub type CMPR0_TEA_INT_ENA_R = crate::BitReader; +#[doc = "Field `CMPR0_TEA_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."] +pub type CMPR0_TEA_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR1_TEA_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."] +pub type CMPR1_TEA_INT_ENA_R = crate::BitReader; +#[doc = "Field `CMPR1_TEA_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."] +pub type CMPR1_TEA_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR2_TEA_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."] +pub type CMPR2_TEA_INT_ENA_R = crate::BitReader; +#[doc = "Field `CMPR2_TEA_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."] +pub type CMPR2_TEA_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR0_TEB_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."] +pub type CMPR0_TEB_INT_ENA_R = crate::BitReader; +#[doc = "Field `CMPR0_TEB_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."] +pub type CMPR0_TEB_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR1_TEB_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."] +pub type CMPR1_TEB_INT_ENA_R = crate::BitReader; +#[doc = "Field `CMPR1_TEB_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."] +pub type CMPR1_TEB_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR2_TEB_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."] +pub type CMPR2_TEB_INT_ENA_R = crate::BitReader; +#[doc = "Field `CMPR2_TEB_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."] +pub type CMPR2_TEB_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ0_CBC_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."] +pub type TZ0_CBC_INT_ENA_R = crate::BitReader; +#[doc = "Field `TZ0_CBC_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."] +pub type TZ0_CBC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ1_CBC_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."] +pub type TZ1_CBC_INT_ENA_R = crate::BitReader; +#[doc = "Field `TZ1_CBC_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."] +pub type TZ1_CBC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ2_CBC_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."] +pub type TZ2_CBC_INT_ENA_R = crate::BitReader; +#[doc = "Field `TZ2_CBC_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."] +pub type TZ2_CBC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ0_OST_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."] +pub type TZ0_OST_INT_ENA_R = crate::BitReader; +#[doc = "Field `TZ0_OST_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."] +pub type TZ0_OST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ1_OST_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."] +pub type TZ1_OST_INT_ENA_R = crate::BitReader; +#[doc = "Field `TZ1_OST_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."] +pub type TZ1_OST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ2_OST_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."] +pub type TZ2_OST_INT_ENA_R = crate::BitReader; +#[doc = "Field `TZ2_OST_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."] +pub type TZ2_OST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP0_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."] +pub type CAP0_INT_ENA_R = crate::BitReader; +#[doc = "Field `CAP0_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."] +pub type CAP0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP1_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."] +pub type CAP1_INT_ENA_R = crate::BitReader; +#[doc = "Field `CAP1_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."] +pub type CAP1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP2_INT_ENA` reader - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."] +pub type CAP2_INT_ENA_R = crate::BitReader; +#[doc = "Field `CAP2_INT_ENA` writer - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."] +pub type CAP2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."] + #[inline(always)] + pub fn timer0_stop_int_ena(&self) -> TIMER0_STOP_INT_ENA_R { + TIMER0_STOP_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."] + #[inline(always)] + pub fn timer1_stop_int_ena(&self) -> TIMER1_STOP_INT_ENA_R { + TIMER1_STOP_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."] + #[inline(always)] + pub fn timer2_stop_int_ena(&self) -> TIMER2_STOP_INT_ENA_R { + TIMER2_STOP_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."] + #[inline(always)] + pub fn timer0_tez_int_ena(&self) -> TIMER0_TEZ_INT_ENA_R { + TIMER0_TEZ_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."] + #[inline(always)] + pub fn timer1_tez_int_ena(&self) -> TIMER1_TEZ_INT_ENA_R { + TIMER1_TEZ_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."] + #[inline(always)] + pub fn timer2_tez_int_ena(&self) -> TIMER2_TEZ_INT_ENA_R { + TIMER2_TEZ_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."] + #[inline(always)] + pub fn timer0_tep_int_ena(&self) -> TIMER0_TEP_INT_ENA_R { + TIMER0_TEP_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."] + #[inline(always)] + pub fn timer1_tep_int_ena(&self) -> TIMER1_TEP_INT_ENA_R { + TIMER1_TEP_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."] + #[inline(always)] + pub fn timer2_tep_int_ena(&self) -> TIMER2_TEP_INT_ENA_R { + TIMER2_TEP_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."] + #[inline(always)] + pub fn fault0_int_ena(&self) -> FAULT0_INT_ENA_R { + FAULT0_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."] + #[inline(always)] + pub fn fault1_int_ena(&self) -> FAULT1_INT_ENA_R { + FAULT1_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."] + #[inline(always)] + pub fn fault2_int_ena(&self) -> FAULT2_INT_ENA_R { + FAULT2_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."] + #[inline(always)] + pub fn fault0_clr_int_ena(&self) -> FAULT0_CLR_INT_ENA_R { + FAULT0_CLR_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."] + #[inline(always)] + pub fn fault1_clr_int_ena(&self) -> FAULT1_CLR_INT_ENA_R { + FAULT1_CLR_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."] + #[inline(always)] + pub fn fault2_clr_int_ena(&self) -> FAULT2_CLR_INT_ENA_R { + FAULT2_CLR_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."] + #[inline(always)] + pub fn cmpr0_tea_int_ena(&self) -> CMPR0_TEA_INT_ENA_R { + CMPR0_TEA_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."] + #[inline(always)] + pub fn cmpr1_tea_int_ena(&self) -> CMPR1_TEA_INT_ENA_R { + CMPR1_TEA_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."] + #[inline(always)] + pub fn cmpr2_tea_int_ena(&self) -> CMPR2_TEA_INT_ENA_R { + CMPR2_TEA_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."] + #[inline(always)] + pub fn cmpr0_teb_int_ena(&self) -> CMPR0_TEB_INT_ENA_R { + CMPR0_TEB_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."] + #[inline(always)] + pub fn cmpr1_teb_int_ena(&self) -> CMPR1_TEB_INT_ENA_R { + CMPR1_TEB_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."] + #[inline(always)] + pub fn cmpr2_teb_int_ena(&self) -> CMPR2_TEB_INT_ENA_R { + CMPR2_TEB_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."] + #[inline(always)] + pub fn tz0_cbc_int_ena(&self) -> TZ0_CBC_INT_ENA_R { + TZ0_CBC_INT_ENA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."] + #[inline(always)] + pub fn tz1_cbc_int_ena(&self) -> TZ1_CBC_INT_ENA_R { + TZ1_CBC_INT_ENA_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."] + #[inline(always)] + pub fn tz2_cbc_int_ena(&self) -> TZ2_CBC_INT_ENA_R { + TZ2_CBC_INT_ENA_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."] + #[inline(always)] + pub fn tz0_ost_int_ena(&self) -> TZ0_OST_INT_ENA_R { + TZ0_OST_INT_ENA_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."] + #[inline(always)] + pub fn tz1_ost_int_ena(&self) -> TZ1_OST_INT_ENA_R { + TZ1_OST_INT_ENA_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."] + #[inline(always)] + pub fn tz2_ost_int_ena(&self) -> TZ2_OST_INT_ENA_R { + TZ2_OST_INT_ENA_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."] + #[inline(always)] + pub fn cap0_int_ena(&self) -> CAP0_INT_ENA_R { + CAP0_INT_ENA_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."] + #[inline(always)] + pub fn cap1_int_ena(&self) -> CAP1_INT_ENA_R { + CAP1_INT_ENA_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."] + #[inline(always)] + pub fn cap2_int_ena(&self) -> CAP2_INT_ENA_R { + CAP2_INT_ENA_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "timer0_stop_int_ena", + &format_args!("{}", self.timer0_stop_int_ena().bit()), + ) + .field( + "timer1_stop_int_ena", + &format_args!("{}", self.timer1_stop_int_ena().bit()), + ) + .field( + "timer2_stop_int_ena", + &format_args!("{}", self.timer2_stop_int_ena().bit()), + ) + .field( + "timer0_tez_int_ena", + &format_args!("{}", self.timer0_tez_int_ena().bit()), + ) + .field( + "timer1_tez_int_ena", + &format_args!("{}", self.timer1_tez_int_ena().bit()), + ) + .field( + "timer2_tez_int_ena", + &format_args!("{}", self.timer2_tez_int_ena().bit()), + ) + .field( + "timer0_tep_int_ena", + &format_args!("{}", self.timer0_tep_int_ena().bit()), + ) + .field( + "timer1_tep_int_ena", + &format_args!("{}", self.timer1_tep_int_ena().bit()), + ) + .field( + "timer2_tep_int_ena", + &format_args!("{}", self.timer2_tep_int_ena().bit()), + ) + .field( + "fault0_int_ena", + &format_args!("{}", self.fault0_int_ena().bit()), + ) + .field( + "fault1_int_ena", + &format_args!("{}", self.fault1_int_ena().bit()), + ) + .field( + "fault2_int_ena", + &format_args!("{}", self.fault2_int_ena().bit()), + ) + .field( + "fault0_clr_int_ena", + &format_args!("{}", self.fault0_clr_int_ena().bit()), + ) + .field( + "fault1_clr_int_ena", + &format_args!("{}", self.fault1_clr_int_ena().bit()), + ) + .field( + "fault2_clr_int_ena", + &format_args!("{}", self.fault2_clr_int_ena().bit()), + ) + .field( + "cmpr0_tea_int_ena", + &format_args!("{}", self.cmpr0_tea_int_ena().bit()), + ) + .field( + "cmpr1_tea_int_ena", + &format_args!("{}", self.cmpr1_tea_int_ena().bit()), + ) + .field( + "cmpr2_tea_int_ena", + &format_args!("{}", self.cmpr2_tea_int_ena().bit()), + ) + .field( + "cmpr0_teb_int_ena", + &format_args!("{}", self.cmpr0_teb_int_ena().bit()), + ) + .field( + "cmpr1_teb_int_ena", + &format_args!("{}", self.cmpr1_teb_int_ena().bit()), + ) + .field( + "cmpr2_teb_int_ena", + &format_args!("{}", self.cmpr2_teb_int_ena().bit()), + ) + .field( + "tz0_cbc_int_ena", + &format_args!("{}", self.tz0_cbc_int_ena().bit()), + ) + .field( + "tz1_cbc_int_ena", + &format_args!("{}", self.tz1_cbc_int_ena().bit()), + ) + .field( + "tz2_cbc_int_ena", + &format_args!("{}", self.tz2_cbc_int_ena().bit()), + ) + .field( + "tz0_ost_int_ena", + &format_args!("{}", self.tz0_ost_int_ena().bit()), + ) + .field( + "tz1_ost_int_ena", + &format_args!("{}", self.tz1_ost_int_ena().bit()), + ) + .field( + "tz2_ost_int_ena", + &format_args!("{}", self.tz2_ost_int_ena().bit()), + ) + .field( + "cap0_int_ena", + &format_args!("{}", self.cap0_int_ena().bit()), + ) + .field( + "cap1_int_ena", + &format_args!("{}", self.cap1_int_ena().bit()), + ) + .field( + "cap2_int_ena", + &format_args!("{}", self.cap2_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."] + #[inline(always)] + #[must_use] + pub fn timer0_stop_int_ena(&mut self) -> TIMER0_STOP_INT_ENA_W { + TIMER0_STOP_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops."] + #[inline(always)] + #[must_use] + pub fn timer1_stop_int_ena(&mut self) -> TIMER1_STOP_INT_ENA_W { + TIMER1_STOP_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops."] + #[inline(always)] + #[must_use] + pub fn timer2_stop_int_ena(&mut self) -> TIMER2_STOP_INT_ENA_W { + TIMER2_STOP_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event."] + #[inline(always)] + #[must_use] + pub fn timer0_tez_int_ena(&mut self) -> TIMER0_TEZ_INT_ENA_W { + TIMER0_TEZ_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event."] + #[inline(always)] + #[must_use] + pub fn timer1_tez_int_ena(&mut self) -> TIMER1_TEZ_INT_ENA_W { + TIMER1_TEZ_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event."] + #[inline(always)] + #[must_use] + pub fn timer2_tez_int_ena(&mut self) -> TIMER2_TEZ_INT_ENA_W { + TIMER2_TEZ_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event."] + #[inline(always)] + #[must_use] + pub fn timer0_tep_int_ena(&mut self) -> TIMER0_TEP_INT_ENA_W { + TIMER0_TEP_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event."] + #[inline(always)] + #[must_use] + pub fn timer1_tep_int_ena(&mut self) -> TIMER1_TEP_INT_ENA_W { + TIMER1_TEP_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event."] + #[inline(always)] + #[must_use] + pub fn timer2_tep_int_ena(&mut self) -> TIMER2_TEP_INT_ENA_W { + TIMER2_TEP_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts."] + #[inline(always)] + #[must_use] + pub fn fault0_int_ena(&mut self) -> FAULT0_INT_ENA_W { + FAULT0_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts."] + #[inline(always)] + #[must_use] + pub fn fault1_int_ena(&mut self) -> FAULT1_INT_ENA_W { + FAULT1_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts."] + #[inline(always)] + #[must_use] + pub fn fault2_int_ena(&mut self) -> FAULT2_INT_ENA_W { + FAULT2_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears."] + #[inline(always)] + #[must_use] + pub fn fault0_clr_int_ena(&mut self) -> FAULT0_CLR_INT_ENA_W { + FAULT0_CLR_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears."] + #[inline(always)] + #[must_use] + pub fn fault1_clr_int_ena(&mut self) -> FAULT1_CLR_INT_ENA_W { + FAULT1_CLR_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears."] + #[inline(always)] + #[must_use] + pub fn fault2_clr_int_ena(&mut self) -> FAULT2_CLR_INT_ENA_W { + FAULT2_CLR_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event."] + #[inline(always)] + #[must_use] + pub fn cmpr0_tea_int_ena(&mut self) -> CMPR0_TEA_INT_ENA_W { + CMPR0_TEA_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event."] + #[inline(always)] + #[must_use] + pub fn cmpr1_tea_int_ena(&mut self) -> CMPR1_TEA_INT_ENA_W { + CMPR1_TEA_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event."] + #[inline(always)] + #[must_use] + pub fn cmpr2_tea_int_ena(&mut self) -> CMPR2_TEA_INT_ENA_W { + CMPR2_TEA_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 18 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event."] + #[inline(always)] + #[must_use] + pub fn cmpr0_teb_int_ena(&mut self) -> CMPR0_TEB_INT_ENA_W { + CMPR0_TEB_INT_ENA_W::new(self, 18) + } + #[doc = "Bit 19 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event."] + #[inline(always)] + #[must_use] + pub fn cmpr1_teb_int_ena(&mut self) -> CMPR1_TEB_INT_ENA_W { + CMPR1_TEB_INT_ENA_W::new(self, 19) + } + #[doc = "Bit 20 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event."] + #[inline(always)] + #[must_use] + pub fn cmpr2_teb_int_ena(&mut self) -> CMPR2_TEB_INT_ENA_W { + CMPR2_TEB_INT_ENA_W::new(self, 20) + } + #[doc = "Bit 21 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0."] + #[inline(always)] + #[must_use] + pub fn tz0_cbc_int_ena(&mut self) -> TZ0_CBC_INT_ENA_W { + TZ0_CBC_INT_ENA_W::new(self, 21) + } + #[doc = "Bit 22 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1."] + #[inline(always)] + #[must_use] + pub fn tz1_cbc_int_ena(&mut self) -> TZ1_CBC_INT_ENA_W { + TZ1_CBC_INT_ENA_W::new(self, 22) + } + #[doc = "Bit 23 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2."] + #[inline(always)] + #[must_use] + pub fn tz2_cbc_int_ena(&mut self) -> TZ2_CBC_INT_ENA_W { + TZ2_CBC_INT_ENA_W::new(self, 23) + } + #[doc = "Bit 24 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0."] + #[inline(always)] + #[must_use] + pub fn tz0_ost_int_ena(&mut self) -> TZ0_OST_INT_ENA_W { + TZ0_OST_INT_ENA_W::new(self, 24) + } + #[doc = "Bit 25 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1."] + #[inline(always)] + #[must_use] + pub fn tz1_ost_int_ena(&mut self) -> TZ1_OST_INT_ENA_W { + TZ1_OST_INT_ENA_W::new(self, 25) + } + #[doc = "Bit 26 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2."] + #[inline(always)] + #[must_use] + pub fn tz2_ost_int_ena(&mut self) -> TZ2_OST_INT_ENA_W { + TZ2_OST_INT_ENA_W::new(self, 26) + } + #[doc = "Bit 27 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0."] + #[inline(always)] + #[must_use] + pub fn cap0_int_ena(&mut self) -> CAP0_INT_ENA_W { + CAP0_INT_ENA_W::new(self, 27) + } + #[doc = "Bit 28 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1."] + #[inline(always)] + #[must_use] + pub fn cap1_int_ena(&mut self) -> CAP1_INT_ENA_W { + CAP1_INT_ENA_W::new(self, 28) + } + #[doc = "Bit 29 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2."] + #[inline(always)] + #[must_use] + pub fn cap2_int_ena(&mut self) -> CAP2_INT_ENA_W { + CAP2_INT_ENA_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/int_raw.rs b/esp32p4/src/mcpwm0/int_raw.rs new file mode 100644 index 0000000000..f3f9f4aea3 --- /dev/null +++ b/esp32p4/src/mcpwm0/int_raw.rs @@ -0,0 +1,617 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER0_STOP_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."] +pub type TIMER0_STOP_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER0_STOP_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."] +pub type TIMER0_STOP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_STOP_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."] +pub type TIMER1_STOP_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER1_STOP_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."] +pub type TIMER1_STOP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_STOP_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."] +pub type TIMER2_STOP_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER2_STOP_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."] +pub type TIMER2_STOP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER0_TEZ_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."] +pub type TIMER0_TEZ_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER0_TEZ_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."] +pub type TIMER0_TEZ_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_TEZ_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."] +pub type TIMER1_TEZ_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER1_TEZ_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."] +pub type TIMER1_TEZ_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_TEZ_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."] +pub type TIMER2_TEZ_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER2_TEZ_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."] +pub type TIMER2_TEZ_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER0_TEP_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."] +pub type TIMER0_TEP_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER0_TEP_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."] +pub type TIMER0_TEP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_TEP_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."] +pub type TIMER1_TEP_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER1_TEP_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."] +pub type TIMER1_TEP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_TEP_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."] +pub type TIMER2_TEP_INT_RAW_R = crate::BitReader; +#[doc = "Field `TIMER2_TEP_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."] +pub type TIMER2_TEP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT0_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."] +pub type FAULT0_INT_RAW_R = crate::BitReader; +#[doc = "Field `FAULT0_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."] +pub type FAULT0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT1_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."] +pub type FAULT1_INT_RAW_R = crate::BitReader; +#[doc = "Field `FAULT1_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."] +pub type FAULT1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT2_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."] +pub type FAULT2_INT_RAW_R = crate::BitReader; +#[doc = "Field `FAULT2_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."] +pub type FAULT2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT0_CLR_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."] +pub type FAULT0_CLR_INT_RAW_R = crate::BitReader; +#[doc = "Field `FAULT0_CLR_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."] +pub type FAULT0_CLR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT1_CLR_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."] +pub type FAULT1_CLR_INT_RAW_R = crate::BitReader; +#[doc = "Field `FAULT1_CLR_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."] +pub type FAULT1_CLR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FAULT2_CLR_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."] +pub type FAULT2_CLR_INT_RAW_R = crate::BitReader; +#[doc = "Field `FAULT2_CLR_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."] +pub type FAULT2_CLR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR0_TEA_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"] +pub type CMPR0_TEA_INT_RAW_R = crate::BitReader; +#[doc = "Field `CMPR0_TEA_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"] +pub type CMPR0_TEA_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR1_TEA_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"] +pub type CMPR1_TEA_INT_RAW_R = crate::BitReader; +#[doc = "Field `CMPR1_TEA_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"] +pub type CMPR1_TEA_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR2_TEA_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"] +pub type CMPR2_TEA_INT_RAW_R = crate::BitReader; +#[doc = "Field `CMPR2_TEA_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"] +pub type CMPR2_TEA_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR0_TEB_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"] +pub type CMPR0_TEB_INT_RAW_R = crate::BitReader; +#[doc = "Field `CMPR0_TEB_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"] +pub type CMPR0_TEB_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR1_TEB_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"] +pub type CMPR1_TEB_INT_RAW_R = crate::BitReader; +#[doc = "Field `CMPR1_TEB_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"] +pub type CMPR1_TEB_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMPR2_TEB_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"] +pub type CMPR2_TEB_INT_RAW_R = crate::BitReader; +#[doc = "Field `CMPR2_TEB_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"] +pub type CMPR2_TEB_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ0_CBC_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."] +pub type TZ0_CBC_INT_RAW_R = crate::BitReader; +#[doc = "Field `TZ0_CBC_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."] +pub type TZ0_CBC_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ1_CBC_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."] +pub type TZ1_CBC_INT_RAW_R = crate::BitReader; +#[doc = "Field `TZ1_CBC_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."] +pub type TZ1_CBC_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ2_CBC_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."] +pub type TZ2_CBC_INT_RAW_R = crate::BitReader; +#[doc = "Field `TZ2_CBC_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."] +pub type TZ2_CBC_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ0_OST_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."] +pub type TZ0_OST_INT_RAW_R = crate::BitReader; +#[doc = "Field `TZ0_OST_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."] +pub type TZ0_OST_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ1_OST_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."] +pub type TZ1_OST_INT_RAW_R = crate::BitReader; +#[doc = "Field `TZ1_OST_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."] +pub type TZ1_OST_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TZ2_OST_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."] +pub type TZ2_OST_INT_RAW_R = crate::BitReader; +#[doc = "Field `TZ2_OST_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."] +pub type TZ2_OST_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP0_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."] +pub type CAP0_INT_RAW_R = crate::BitReader; +#[doc = "Field `CAP0_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."] +pub type CAP0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP1_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."] +pub type CAP1_INT_RAW_R = crate::BitReader; +#[doc = "Field `CAP1_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."] +pub type CAP1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAP2_INT_RAW` reader - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."] +pub type CAP2_INT_RAW_R = crate::BitReader; +#[doc = "Field `CAP2_INT_RAW` writer - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."] +pub type CAP2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."] + #[inline(always)] + pub fn timer0_stop_int_raw(&self) -> TIMER0_STOP_INT_RAW_R { + TIMER0_STOP_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."] + #[inline(always)] + pub fn timer1_stop_int_raw(&self) -> TIMER1_STOP_INT_RAW_R { + TIMER1_STOP_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."] + #[inline(always)] + pub fn timer2_stop_int_raw(&self) -> TIMER2_STOP_INT_RAW_R { + TIMER2_STOP_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."] + #[inline(always)] + pub fn timer0_tez_int_raw(&self) -> TIMER0_TEZ_INT_RAW_R { + TIMER0_TEZ_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."] + #[inline(always)] + pub fn timer1_tez_int_raw(&self) -> TIMER1_TEZ_INT_RAW_R { + TIMER1_TEZ_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."] + #[inline(always)] + pub fn timer2_tez_int_raw(&self) -> TIMER2_TEZ_INT_RAW_R { + TIMER2_TEZ_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."] + #[inline(always)] + pub fn timer0_tep_int_raw(&self) -> TIMER0_TEP_INT_RAW_R { + TIMER0_TEP_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."] + #[inline(always)] + pub fn timer1_tep_int_raw(&self) -> TIMER1_TEP_INT_RAW_R { + TIMER1_TEP_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."] + #[inline(always)] + pub fn timer2_tep_int_raw(&self) -> TIMER2_TEP_INT_RAW_R { + TIMER2_TEP_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."] + #[inline(always)] + pub fn fault0_int_raw(&self) -> FAULT0_INT_RAW_R { + FAULT0_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."] + #[inline(always)] + pub fn fault1_int_raw(&self) -> FAULT1_INT_RAW_R { + FAULT1_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."] + #[inline(always)] + pub fn fault2_int_raw(&self) -> FAULT2_INT_RAW_R { + FAULT2_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."] + #[inline(always)] + pub fn fault0_clr_int_raw(&self) -> FAULT0_CLR_INT_RAW_R { + FAULT0_CLR_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."] + #[inline(always)] + pub fn fault1_clr_int_raw(&self) -> FAULT1_CLR_INT_RAW_R { + FAULT1_CLR_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."] + #[inline(always)] + pub fn fault2_clr_int_raw(&self) -> FAULT2_CLR_INT_RAW_R { + FAULT2_CLR_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"] + #[inline(always)] + pub fn cmpr0_tea_int_raw(&self) -> CMPR0_TEA_INT_RAW_R { + CMPR0_TEA_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"] + #[inline(always)] + pub fn cmpr1_tea_int_raw(&self) -> CMPR1_TEA_INT_RAW_R { + CMPR1_TEA_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"] + #[inline(always)] + pub fn cmpr2_tea_int_raw(&self) -> CMPR2_TEA_INT_RAW_R { + CMPR2_TEA_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"] + #[inline(always)] + pub fn cmpr0_teb_int_raw(&self) -> CMPR0_TEB_INT_RAW_R { + CMPR0_TEB_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"] + #[inline(always)] + pub fn cmpr1_teb_int_raw(&self) -> CMPR1_TEB_INT_RAW_R { + CMPR1_TEB_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"] + #[inline(always)] + pub fn cmpr2_teb_int_raw(&self) -> CMPR2_TEB_INT_RAW_R { + CMPR2_TEB_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."] + #[inline(always)] + pub fn tz0_cbc_int_raw(&self) -> TZ0_CBC_INT_RAW_R { + TZ0_CBC_INT_RAW_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."] + #[inline(always)] + pub fn tz1_cbc_int_raw(&self) -> TZ1_CBC_INT_RAW_R { + TZ1_CBC_INT_RAW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."] + #[inline(always)] + pub fn tz2_cbc_int_raw(&self) -> TZ2_CBC_INT_RAW_R { + TZ2_CBC_INT_RAW_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."] + #[inline(always)] + pub fn tz0_ost_int_raw(&self) -> TZ0_OST_INT_RAW_R { + TZ0_OST_INT_RAW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."] + #[inline(always)] + pub fn tz1_ost_int_raw(&self) -> TZ1_OST_INT_RAW_R { + TZ1_OST_INT_RAW_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."] + #[inline(always)] + pub fn tz2_ost_int_raw(&self) -> TZ2_OST_INT_RAW_R { + TZ2_OST_INT_RAW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."] + #[inline(always)] + pub fn cap0_int_raw(&self) -> CAP0_INT_RAW_R { + CAP0_INT_RAW_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."] + #[inline(always)] + pub fn cap1_int_raw(&self) -> CAP1_INT_RAW_R { + CAP1_INT_RAW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."] + #[inline(always)] + pub fn cap2_int_raw(&self) -> CAP2_INT_RAW_R { + CAP2_INT_RAW_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "timer0_stop_int_raw", + &format_args!("{}", self.timer0_stop_int_raw().bit()), + ) + .field( + "timer1_stop_int_raw", + &format_args!("{}", self.timer1_stop_int_raw().bit()), + ) + .field( + "timer2_stop_int_raw", + &format_args!("{}", self.timer2_stop_int_raw().bit()), + ) + .field( + "timer0_tez_int_raw", + &format_args!("{}", self.timer0_tez_int_raw().bit()), + ) + .field( + "timer1_tez_int_raw", + &format_args!("{}", self.timer1_tez_int_raw().bit()), + ) + .field( + "timer2_tez_int_raw", + &format_args!("{}", self.timer2_tez_int_raw().bit()), + ) + .field( + "timer0_tep_int_raw", + &format_args!("{}", self.timer0_tep_int_raw().bit()), + ) + .field( + "timer1_tep_int_raw", + &format_args!("{}", self.timer1_tep_int_raw().bit()), + ) + .field( + "timer2_tep_int_raw", + &format_args!("{}", self.timer2_tep_int_raw().bit()), + ) + .field( + "fault0_int_raw", + &format_args!("{}", self.fault0_int_raw().bit()), + ) + .field( + "fault1_int_raw", + &format_args!("{}", self.fault1_int_raw().bit()), + ) + .field( + "fault2_int_raw", + &format_args!("{}", self.fault2_int_raw().bit()), + ) + .field( + "fault0_clr_int_raw", + &format_args!("{}", self.fault0_clr_int_raw().bit()), + ) + .field( + "fault1_clr_int_raw", + &format_args!("{}", self.fault1_clr_int_raw().bit()), + ) + .field( + "fault2_clr_int_raw", + &format_args!("{}", self.fault2_clr_int_raw().bit()), + ) + .field( + "cmpr0_tea_int_raw", + &format_args!("{}", self.cmpr0_tea_int_raw().bit()), + ) + .field( + "cmpr1_tea_int_raw", + &format_args!("{}", self.cmpr1_tea_int_raw().bit()), + ) + .field( + "cmpr2_tea_int_raw", + &format_args!("{}", self.cmpr2_tea_int_raw().bit()), + ) + .field( + "cmpr0_teb_int_raw", + &format_args!("{}", self.cmpr0_teb_int_raw().bit()), + ) + .field( + "cmpr1_teb_int_raw", + &format_args!("{}", self.cmpr1_teb_int_raw().bit()), + ) + .field( + "cmpr2_teb_int_raw", + &format_args!("{}", self.cmpr2_teb_int_raw().bit()), + ) + .field( + "tz0_cbc_int_raw", + &format_args!("{}", self.tz0_cbc_int_raw().bit()), + ) + .field( + "tz1_cbc_int_raw", + &format_args!("{}", self.tz1_cbc_int_raw().bit()), + ) + .field( + "tz2_cbc_int_raw", + &format_args!("{}", self.tz2_cbc_int_raw().bit()), + ) + .field( + "tz0_ost_int_raw", + &format_args!("{}", self.tz0_ost_int_raw().bit()), + ) + .field( + "tz1_ost_int_raw", + &format_args!("{}", self.tz1_ost_int_raw().bit()), + ) + .field( + "tz2_ost_int_raw", + &format_args!("{}", self.tz2_ost_int_raw().bit()), + ) + .field( + "cap0_int_raw", + &format_args!("{}", self.cap0_int_raw().bit()), + ) + .field( + "cap1_int_raw", + &format_args!("{}", self.cap1_int_raw().bit()), + ) + .field( + "cap2_int_raw", + &format_args!("{}", self.cap2_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."] + #[inline(always)] + #[must_use] + pub fn timer0_stop_int_raw(&mut self) -> TIMER0_STOP_INT_RAW_W { + TIMER0_STOP_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops."] + #[inline(always)] + #[must_use] + pub fn timer1_stop_int_raw(&mut self) -> TIMER1_STOP_INT_RAW_W { + TIMER1_STOP_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops."] + #[inline(always)] + #[must_use] + pub fn timer2_stop_int_raw(&mut self) -> TIMER2_STOP_INT_RAW_W { + TIMER2_STOP_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."] + #[inline(always)] + #[must_use] + pub fn timer0_tez_int_raw(&mut self) -> TIMER0_TEZ_INT_RAW_W { + TIMER0_TEZ_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."] + #[inline(always)] + #[must_use] + pub fn timer1_tez_int_raw(&mut self) -> TIMER1_TEZ_INT_RAW_W { + TIMER1_TEZ_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."] + #[inline(always)] + #[must_use] + pub fn timer2_tez_int_raw(&mut self) -> TIMER2_TEZ_INT_RAW_W { + TIMER2_TEZ_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event."] + #[inline(always)] + #[must_use] + pub fn timer0_tep_int_raw(&mut self) -> TIMER0_TEP_INT_RAW_W { + TIMER0_TEP_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event."] + #[inline(always)] + #[must_use] + pub fn timer1_tep_int_raw(&mut self) -> TIMER1_TEP_INT_RAW_W { + TIMER1_TEP_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event."] + #[inline(always)] + #[must_use] + pub fn timer2_tep_int_raw(&mut self) -> TIMER2_TEP_INT_RAW_W { + TIMER2_TEP_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts."] + #[inline(always)] + #[must_use] + pub fn fault0_int_raw(&mut self) -> FAULT0_INT_RAW_W { + FAULT0_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts."] + #[inline(always)] + #[must_use] + pub fn fault1_int_raw(&mut self) -> FAULT1_INT_RAW_W { + FAULT1_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts."] + #[inline(always)] + #[must_use] + pub fn fault2_int_raw(&mut self) -> FAULT2_INT_RAW_W { + FAULT2_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 12 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears."] + #[inline(always)] + #[must_use] + pub fn fault0_clr_int_raw(&mut self) -> FAULT0_CLR_INT_RAW_W { + FAULT0_CLR_INT_RAW_W::new(self, 12) + } + #[doc = "Bit 13 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears."] + #[inline(always)] + #[must_use] + pub fn fault1_clr_int_raw(&mut self) -> FAULT1_CLR_INT_RAW_W { + FAULT1_CLR_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 14 - Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears."] + #[inline(always)] + #[must_use] + pub fn fault2_clr_int_raw(&mut self) -> FAULT2_CLR_INT_RAW_W { + FAULT2_CLR_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event"] + #[inline(always)] + #[must_use] + pub fn cmpr0_tea_int_raw(&mut self) -> CMPR0_TEA_INT_RAW_W { + CMPR0_TEA_INT_RAW_W::new(self, 15) + } + #[doc = "Bit 16 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event"] + #[inline(always)] + #[must_use] + pub fn cmpr1_tea_int_raw(&mut self) -> CMPR1_TEA_INT_RAW_W { + CMPR1_TEA_INT_RAW_W::new(self, 16) + } + #[doc = "Bit 17 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event"] + #[inline(always)] + #[must_use] + pub fn cmpr2_tea_int_raw(&mut self) -> CMPR2_TEA_INT_RAW_W { + CMPR2_TEA_INT_RAW_W::new(self, 17) + } + #[doc = "Bit 18 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event"] + #[inline(always)] + #[must_use] + pub fn cmpr0_teb_int_raw(&mut self) -> CMPR0_TEB_INT_RAW_W { + CMPR0_TEB_INT_RAW_W::new(self, 18) + } + #[doc = "Bit 19 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event"] + #[inline(always)] + #[must_use] + pub fn cmpr1_teb_int_raw(&mut self) -> CMPR1_TEB_INT_RAW_W { + CMPR1_TEB_INT_RAW_W::new(self, 19) + } + #[doc = "Bit 20 - Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event"] + #[inline(always)] + #[must_use] + pub fn cmpr2_teb_int_raw(&mut self) -> CMPR2_TEB_INT_RAW_W { + CMPR2_TEB_INT_RAW_W::new(self, 20) + } + #[doc = "Bit 21 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."] + #[inline(always)] + #[must_use] + pub fn tz0_cbc_int_raw(&mut self) -> TZ0_CBC_INT_RAW_W { + TZ0_CBC_INT_RAW_W::new(self, 21) + } + #[doc = "Bit 22 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."] + #[inline(always)] + #[must_use] + pub fn tz1_cbc_int_raw(&mut self) -> TZ1_CBC_INT_RAW_W { + TZ1_CBC_INT_RAW_W::new(self, 22) + } + #[doc = "Bit 23 - Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."] + #[inline(always)] + #[must_use] + pub fn tz2_cbc_int_raw(&mut self) -> TZ2_CBC_INT_RAW_W { + TZ2_CBC_INT_RAW_W::new(self, 23) + } + #[doc = "Bit 24 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0."] + #[inline(always)] + #[must_use] + pub fn tz0_ost_int_raw(&mut self) -> TZ0_OST_INT_RAW_W { + TZ0_OST_INT_RAW_W::new(self, 24) + } + #[doc = "Bit 25 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1."] + #[inline(always)] + #[must_use] + pub fn tz1_ost_int_raw(&mut self) -> TZ1_OST_INT_RAW_W { + TZ1_OST_INT_RAW_W::new(self, 25) + } + #[doc = "Bit 26 - Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2."] + #[inline(always)] + #[must_use] + pub fn tz2_ost_int_raw(&mut self) -> TZ2_OST_INT_RAW_W { + TZ2_OST_INT_RAW_W::new(self, 26) + } + #[doc = "Bit 27 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0."] + #[inline(always)] + #[must_use] + pub fn cap0_int_raw(&mut self) -> CAP0_INT_RAW_W { + CAP0_INT_RAW_W::new(self, 27) + } + #[doc = "Bit 28 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1."] + #[inline(always)] + #[must_use] + pub fn cap1_int_raw(&mut self) -> CAP1_INT_RAW_W { + CAP1_INT_RAW_W::new(self, 28) + } + #[doc = "Bit 29 - Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2."] + #[inline(always)] + #[must_use] + pub fn cap2_int_raw(&mut self) -> CAP2_INT_RAW_W { + CAP2_INT_RAW_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/int_st.rs b/esp32p4/src/mcpwm0/int_st.rs new file mode 100644 index 0000000000..ae8fba5b2e --- /dev/null +++ b/esp32p4/src/mcpwm0/int_st.rs @@ -0,0 +1,349 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `TIMER0_STOP_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 0 stops."] +pub type TIMER0_STOP_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMER1_STOP_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 1 stops."] +pub type TIMER1_STOP_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMER2_STOP_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 2 stops."] +pub type TIMER2_STOP_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMER0_TEZ_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."] +pub type TIMER0_TEZ_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMER1_TEZ_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."] +pub type TIMER1_TEZ_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMER2_TEZ_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."] +pub type TIMER2_TEZ_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMER0_TEP_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEP event."] +pub type TIMER0_TEP_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMER1_TEP_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEP event."] +pub type TIMER1_TEP_INT_ST_R = crate::BitReader; +#[doc = "Field `TIMER2_TEP_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEP event."] +pub type TIMER2_TEP_INT_ST_R = crate::BitReader; +#[doc = "Field `FAULT0_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 starts."] +pub type FAULT0_INT_ST_R = crate::BitReader; +#[doc = "Field `FAULT1_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 starts."] +pub type FAULT1_INT_ST_R = crate::BitReader; +#[doc = "Field `FAULT2_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 starts."] +pub type FAULT2_INT_ST_R = crate::BitReader; +#[doc = "Field `FAULT0_CLR_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 clears."] +pub type FAULT0_CLR_INT_ST_R = crate::BitReader; +#[doc = "Field `FAULT1_CLR_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 clears."] +pub type FAULT1_CLR_INT_ST_R = crate::BitReader; +#[doc = "Field `FAULT2_CLR_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 clears."] +pub type FAULT2_CLR_INT_ST_R = crate::BitReader; +#[doc = "Field `CMPR0_TEA_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEA event"] +pub type CMPR0_TEA_INT_ST_R = crate::BitReader; +#[doc = "Field `CMPR1_TEA_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEA event"] +pub type CMPR1_TEA_INT_ST_R = crate::BitReader; +#[doc = "Field `CMPR2_TEA_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEA event"] +pub type CMPR2_TEA_INT_ST_R = crate::BitReader; +#[doc = "Field `CMPR0_TEB_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEB event"] +pub type CMPR0_TEB_INT_ST_R = crate::BitReader; +#[doc = "Field `CMPR1_TEB_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEB event"] +pub type CMPR1_TEB_INT_ST_R = crate::BitReader; +#[doc = "Field `CMPR2_TEB_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEB event"] +pub type CMPR2_TEB_INT_ST_R = crate::BitReader; +#[doc = "Field `TZ0_CBC_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."] +pub type TZ0_CBC_INT_ST_R = crate::BitReader; +#[doc = "Field `TZ1_CBC_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."] +pub type TZ1_CBC_INT_ST_R = crate::BitReader; +#[doc = "Field `TZ2_CBC_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."] +pub type TZ2_CBC_INT_ST_R = crate::BitReader; +#[doc = "Field `TZ0_OST_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM0."] +pub type TZ0_OST_INT_ST_R = crate::BitReader; +#[doc = "Field `TZ1_OST_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM1."] +pub type TZ1_OST_INT_ST_R = crate::BitReader; +#[doc = "Field `TZ2_OST_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM2."] +pub type TZ2_OST_INT_ST_R = crate::BitReader; +#[doc = "Field `CAP0_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP0."] +pub type CAP0_INT_ST_R = crate::BitReader; +#[doc = "Field `CAP1_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP1."] +pub type CAP1_INT_ST_R = crate::BitReader; +#[doc = "Field `CAP2_INT_ST` reader - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP2."] +pub type CAP2_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 0 stops."] + #[inline(always)] + pub fn timer0_stop_int_st(&self) -> TIMER0_STOP_INT_ST_R { + TIMER0_STOP_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 1 stops."] + #[inline(always)] + pub fn timer1_stop_int_st(&self) -> TIMER1_STOP_INT_ST_R { + TIMER1_STOP_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Masked status bit: The masked interrupt status of the interrupt triggered when the timer 2 stops."] + #[inline(always)] + pub fn timer2_stop_int_st(&self) -> TIMER2_STOP_INT_ST_R { + TIMER2_STOP_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEZ event."] + #[inline(always)] + pub fn timer0_tez_int_st(&self) -> TIMER0_TEZ_INT_ST_R { + TIMER0_TEZ_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEZ event."] + #[inline(always)] + pub fn timer1_tez_int_st(&self) -> TIMER1_TEZ_INT_ST_R { + TIMER1_TEZ_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEZ event."] + #[inline(always)] + pub fn timer2_tez_int_st(&self) -> TIMER2_TEZ_INT_ST_R { + TIMER2_TEZ_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEP event."] + #[inline(always)] + pub fn timer0_tep_int_st(&self) -> TIMER0_TEP_INT_ST_R { + TIMER0_TEP_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEP event."] + #[inline(always)] + pub fn timer1_tep_int_st(&self) -> TIMER1_TEP_INT_ST_R { + TIMER1_TEP_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEP event."] + #[inline(always)] + pub fn timer2_tep_int_st(&self) -> TIMER2_TEP_INT_ST_R { + TIMER2_TEP_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 starts."] + #[inline(always)] + pub fn fault0_int_st(&self) -> FAULT0_INT_ST_R { + FAULT0_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 starts."] + #[inline(always)] + pub fn fault1_int_st(&self) -> FAULT1_INT_ST_R { + FAULT1_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 starts."] + #[inline(always)] + pub fn fault2_int_st(&self) -> FAULT2_INT_ST_R { + FAULT2_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 clears."] + #[inline(always)] + pub fn fault0_clr_int_st(&self) -> FAULT0_CLR_INT_ST_R { + FAULT0_CLR_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 clears."] + #[inline(always)] + pub fn fault1_clr_int_st(&self) -> FAULT1_CLR_INT_ST_R { + FAULT1_CLR_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 clears."] + #[inline(always)] + pub fn fault2_clr_int_st(&self) -> FAULT2_CLR_INT_ST_R { + FAULT2_CLR_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEA event"] + #[inline(always)] + pub fn cmpr0_tea_int_st(&self) -> CMPR0_TEA_INT_ST_R { + CMPR0_TEA_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEA event"] + #[inline(always)] + pub fn cmpr1_tea_int_st(&self) -> CMPR1_TEA_INT_ST_R { + CMPR1_TEA_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEA event"] + #[inline(always)] + pub fn cmpr2_tea_int_st(&self) -> CMPR2_TEA_INT_ST_R { + CMPR2_TEA_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEB event"] + #[inline(always)] + pub fn cmpr0_teb_int_st(&self) -> CMPR0_TEB_INT_ST_R { + CMPR0_TEB_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEB event"] + #[inline(always)] + pub fn cmpr1_teb_int_st(&self) -> CMPR1_TEB_INT_ST_R { + CMPR1_TEB_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEB event"] + #[inline(always)] + pub fn cmpr2_teb_int_st(&self) -> CMPR2_TEB_INT_ST_R { + CMPR2_TEB_INT_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0."] + #[inline(always)] + pub fn tz0_cbc_int_st(&self) -> TZ0_CBC_INT_ST_R { + TZ0_CBC_INT_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1."] + #[inline(always)] + pub fn tz1_cbc_int_st(&self) -> TZ1_CBC_INT_ST_R { + TZ1_CBC_INT_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2."] + #[inline(always)] + pub fn tz2_cbc_int_st(&self) -> TZ2_CBC_INT_ST_R { + TZ2_CBC_INT_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM0."] + #[inline(always)] + pub fn tz0_ost_int_st(&self) -> TZ0_OST_INT_ST_R { + TZ0_OST_INT_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM1."] + #[inline(always)] + pub fn tz1_ost_int_st(&self) -> TZ1_OST_INT_ST_R { + TZ1_OST_INT_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM2."] + #[inline(always)] + pub fn tz2_ost_int_st(&self) -> TZ2_OST_INT_ST_R { + TZ2_OST_INT_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP0."] + #[inline(always)] + pub fn cap0_int_st(&self) -> CAP0_INT_ST_R { + CAP0_INT_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP1."] + #[inline(always)] + pub fn cap1_int_st(&self) -> CAP1_INT_ST_R { + CAP1_INT_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP2."] + #[inline(always)] + pub fn cap2_int_st(&self) -> CAP2_INT_ST_R { + CAP2_INT_ST_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "timer0_stop_int_st", + &format_args!("{}", self.timer0_stop_int_st().bit()), + ) + .field( + "timer1_stop_int_st", + &format_args!("{}", self.timer1_stop_int_st().bit()), + ) + .field( + "timer2_stop_int_st", + &format_args!("{}", self.timer2_stop_int_st().bit()), + ) + .field( + "timer0_tez_int_st", + &format_args!("{}", self.timer0_tez_int_st().bit()), + ) + .field( + "timer1_tez_int_st", + &format_args!("{}", self.timer1_tez_int_st().bit()), + ) + .field( + "timer2_tez_int_st", + &format_args!("{}", self.timer2_tez_int_st().bit()), + ) + .field( + "timer0_tep_int_st", + &format_args!("{}", self.timer0_tep_int_st().bit()), + ) + .field( + "timer1_tep_int_st", + &format_args!("{}", self.timer1_tep_int_st().bit()), + ) + .field( + "timer2_tep_int_st", + &format_args!("{}", self.timer2_tep_int_st().bit()), + ) + .field( + "fault0_int_st", + &format_args!("{}", self.fault0_int_st().bit()), + ) + .field( + "fault1_int_st", + &format_args!("{}", self.fault1_int_st().bit()), + ) + .field( + "fault2_int_st", + &format_args!("{}", self.fault2_int_st().bit()), + ) + .field( + "fault0_clr_int_st", + &format_args!("{}", self.fault0_clr_int_st().bit()), + ) + .field( + "fault1_clr_int_st", + &format_args!("{}", self.fault1_clr_int_st().bit()), + ) + .field( + "fault2_clr_int_st", + &format_args!("{}", self.fault2_clr_int_st().bit()), + ) + .field( + "cmpr0_tea_int_st", + &format_args!("{}", self.cmpr0_tea_int_st().bit()), + ) + .field( + "cmpr1_tea_int_st", + &format_args!("{}", self.cmpr1_tea_int_st().bit()), + ) + .field( + "cmpr2_tea_int_st", + &format_args!("{}", self.cmpr2_tea_int_st().bit()), + ) + .field( + "cmpr0_teb_int_st", + &format_args!("{}", self.cmpr0_teb_int_st().bit()), + ) + .field( + "cmpr1_teb_int_st", + &format_args!("{}", self.cmpr1_teb_int_st().bit()), + ) + .field( + "cmpr2_teb_int_st", + &format_args!("{}", self.cmpr2_teb_int_st().bit()), + ) + .field( + "tz0_cbc_int_st", + &format_args!("{}", self.tz0_cbc_int_st().bit()), + ) + .field( + "tz1_cbc_int_st", + &format_args!("{}", self.tz1_cbc_int_st().bit()), + ) + .field( + "tz2_cbc_int_st", + &format_args!("{}", self.tz2_cbc_int_st().bit()), + ) + .field( + "tz0_ost_int_st", + &format_args!("{}", self.tz0_ost_int_st().bit()), + ) + .field( + "tz1_ost_int_st", + &format_args!("{}", self.tz1_ost_int_st().bit()), + ) + .field( + "tz2_ost_int_st", + &format_args!("{}", self.tz2_ost_int_st().bit()), + ) + .field("cap0_int_st", &format_args!("{}", self.cap0_int_st().bit())) + .field("cap1_int_st", &format_args!("{}", self.cap1_int_st().bit())) + .field("cap2_int_st", &format_args!("{}", self.cap2_int_st().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Interrupt masked status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/op_tstmp_e1.rs b/esp32p4/src/mcpwm0/op_tstmp_e1.rs new file mode 100644 index 0000000000..433fc95375 --- /dev/null +++ b/esp32p4/src/mcpwm0/op_tstmp_e1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OP%s_TSTMP_E1` reader"] +pub type R = crate::R; +#[doc = "Register `OP%s_TSTMP_E1` writer"] +pub type W = crate::W; +#[doc = "Field `OP_TSTMP_E1` reader - Configures generator%s timer stamp E1 value register"] +pub type OP_TSTMP_E1_R = crate::FieldReader; +#[doc = "Field `OP_TSTMP_E1` writer - Configures generator%s timer stamp E1 value register"] +pub type OP_TSTMP_E1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures generator%s timer stamp E1 value register"] + #[inline(always)] + pub fn op_tstmp_e1(&self) -> OP_TSTMP_E1_R { + OP_TSTMP_E1_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OP_TSTMP_E1") + .field( + "op_tstmp_e1", + &format_args!("{}", self.op_tstmp_e1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures generator%s timer stamp E1 value register"] + #[inline(always)] + #[must_use] + pub fn op_tstmp_e1(&mut self) -> OP_TSTMP_E1_W { + OP_TSTMP_E1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Generator%s timer stamp E1 value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`op_tstmp_e1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`op_tstmp_e1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OP_TSTMP_E1_SPEC; +impl crate::RegisterSpec for OP_TSTMP_E1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`op_tstmp_e1::R`](R) reader structure"] +impl crate::Readable for OP_TSTMP_E1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`op_tstmp_e1::W`](W) writer structure"] +impl crate::Writable for OP_TSTMP_E1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OP%s_TSTMP_E1 to value 0"] +impl crate::Resettable for OP_TSTMP_E1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/op_tstmp_e2.rs b/esp32p4/src/mcpwm0/op_tstmp_e2.rs new file mode 100644 index 0000000000..17ec6bad9e --- /dev/null +++ b/esp32p4/src/mcpwm0/op_tstmp_e2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `OP%s_TSTMP_E2` reader"] +pub type R = crate::R; +#[doc = "Register `OP%s_TSTMP_E2` writer"] +pub type W = crate::W; +#[doc = "Field `OP_TSTMP_E2` reader - Configures generator%s timer stamp E2 value register"] +pub type OP_TSTMP_E2_R = crate::FieldReader; +#[doc = "Field `OP_TSTMP_E2` writer - Configures generator%s timer stamp E2 value register"] +pub type OP_TSTMP_E2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures generator%s timer stamp E2 value register"] + #[inline(always)] + pub fn op_tstmp_e2(&self) -> OP_TSTMP_E2_R { + OP_TSTMP_E2_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OP_TSTMP_E2") + .field( + "op_tstmp_e2", + &format_args!("{}", self.op_tstmp_e2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures generator%s timer stamp E2 value register"] + #[inline(always)] + #[must_use] + pub fn op_tstmp_e2(&mut self) -> OP_TSTMP_E2_W { + OP_TSTMP_E2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Generator%s timer stamp E2 value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`op_tstmp_e2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`op_tstmp_e2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OP_TSTMP_E2_SPEC; +impl crate::RegisterSpec for OP_TSTMP_E2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`op_tstmp_e2::R`](R) reader structure"] +impl crate::Readable for OP_TSTMP_E2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`op_tstmp_e2::W`](W) writer structure"] +impl crate::Writable for OP_TSTMP_E2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OP%s_TSTMP_E2 to value 0"] +impl crate::Resettable for OP_TSTMP_E2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/operator_timersel.rs b/esp32p4/src/mcpwm0/operator_timersel.rs new file mode 100644 index 0000000000..2f431c9b8c --- /dev/null +++ b/esp32p4/src/mcpwm0/operator_timersel.rs @@ -0,0 +1,104 @@ +#[doc = "Register `OPERATOR_TIMERSEL` reader"] +pub type R = crate::R; +#[doc = "Register `OPERATOR_TIMERSEL` writer"] +pub type W = crate::W; +#[doc = "Field `OPERATOR0_TIMERSEL` reader - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] +pub type OPERATOR0_TIMERSEL_R = crate::FieldReader; +#[doc = "Field `OPERATOR0_TIMERSEL` writer - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] +pub type OPERATOR0_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `OPERATOR1_TIMERSEL` reader - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] +pub type OPERATOR1_TIMERSEL_R = crate::FieldReader; +#[doc = "Field `OPERATOR1_TIMERSEL` writer - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] +pub type OPERATOR1_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `OPERATOR2_TIMERSEL` reader - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] +pub type OPERATOR2_TIMERSEL_R = crate::FieldReader; +#[doc = "Field `OPERATOR2_TIMERSEL` writer - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] +pub type OPERATOR2_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] + #[inline(always)] + pub fn operator0_timersel(&self) -> OPERATOR0_TIMERSEL_R { + OPERATOR0_TIMERSEL_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] + #[inline(always)] + pub fn operator1_timersel(&self) -> OPERATOR1_TIMERSEL_R { + OPERATOR1_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] + #[inline(always)] + pub fn operator2_timersel(&self) -> OPERATOR2_TIMERSEL_R { + OPERATOR2_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OPERATOR_TIMERSEL") + .field( + "operator0_timersel", + &format_args!("{}", self.operator0_timersel().bits()), + ) + .field( + "operator1_timersel", + &format_args!("{}", self.operator1_timersel().bits()), + ) + .field( + "operator2_timersel", + &format_args!("{}", self.operator2_timersel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] + #[inline(always)] + #[must_use] + pub fn operator0_timersel(&mut self) -> OPERATOR0_TIMERSEL_W { + OPERATOR0_TIMERSEL_W::new(self, 0) + } + #[doc = "Bits 2:3 - Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] + #[inline(always)] + #[must_use] + pub fn operator1_timersel(&mut self) -> OPERATOR1_TIMERSEL_W { + OPERATOR1_TIMERSEL_W::new(self, 2) + } + #[doc = "Bits 4:5 - Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"] + #[inline(always)] + #[must_use] + pub fn operator2_timersel(&mut self) -> OPERATOR2_TIMERSEL_W { + OPERATOR2_TIMERSEL_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PWM operator's timer select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`operator_timersel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`operator_timersel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OPERATOR_TIMERSEL_SPEC; +impl crate::RegisterSpec for OPERATOR_TIMERSEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`operator_timersel::R`](R) reader structure"] +impl crate::Readable for OPERATOR_TIMERSEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`operator_timersel::W`](W) writer structure"] +impl crate::Writable for OPERATOR_TIMERSEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OPERATOR_TIMERSEL to value 0"] +impl crate::Resettable for OPERATOR_TIMERSEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/task_en.rs b/esp32p4/src/mcpwm0/task_en.rs new file mode 100644 index 0000000000..bc30b875be --- /dev/null +++ b/esp32p4/src/mcpwm0/task_en.rs @@ -0,0 +1,465 @@ +#[doc = "Register `TASK_EN` reader"] +pub type R = crate::R; +#[doc = "Register `TASK_EN` writer"] +pub type W = crate::W; +#[doc = "Field `TASK_CMPR0_A_UP_EN` reader - Configures whether or not to enable PWM generator0 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR0_A_UP_EN_R = crate::BitReader; +#[doc = "Field `TASK_CMPR0_A_UP_EN` writer - Configures whether or not to enable PWM generator0 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR0_A_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_CMPR1_A_UP_EN` reader - Configures whether or not to enable PWM generator1 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR1_A_UP_EN_R = crate::BitReader; +#[doc = "Field `TASK_CMPR1_A_UP_EN` writer - Configures whether or not to enable PWM generator1 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR1_A_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_CMPR2_A_UP_EN` reader - Configures whether or not to enable PWM generator2 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR2_A_UP_EN_R = crate::BitReader; +#[doc = "Field `TASK_CMPR2_A_UP_EN` writer - Configures whether or not to enable PWM generator2 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR2_A_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_CMPR0_B_UP_EN` reader - Configures whether or not to enable PWM generator0 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR0_B_UP_EN_R = crate::BitReader; +#[doc = "Field `TASK_CMPR0_B_UP_EN` writer - Configures whether or not to enable PWM generator0 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR0_B_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_CMPR1_B_UP_EN` reader - Configures whether or not to enable PWM generator1 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR1_B_UP_EN_R = crate::BitReader; +#[doc = "Field `TASK_CMPR1_B_UP_EN` writer - Configures whether or not to enable PWM generator1 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR1_B_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_CMPR2_B_UP_EN` reader - Configures whether or not to enable PWM generator2 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR2_B_UP_EN_R = crate::BitReader; +#[doc = "Field `TASK_CMPR2_B_UP_EN` writer - Configures whether or not to enable PWM generator2 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CMPR2_B_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_GEN_STOP_EN` reader - Configures whether or not to enable all PWM generate stop task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GEN_STOP_EN_R = crate::BitReader; +#[doc = "Field `TASK_GEN_STOP_EN` writer - Configures whether or not to enable all PWM generate stop task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_GEN_STOP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER0_SYNC_EN` reader - Configures whether or not to enable timer0 sync task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_SYNC_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER0_SYNC_EN` writer - Configures whether or not to enable timer0 sync task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_SYNC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER1_SYNC_EN` reader - Configures whether or not to enable timer1 sync task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_SYNC_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER1_SYNC_EN` writer - Configures whether or not to enable timer1 sync task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_SYNC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER2_SYNC_EN` reader - Configures whether or not to enable timer2 sync task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_SYNC_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER2_SYNC_EN` writer - Configures whether or not to enable timer2 sync task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_SYNC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER0_PERIOD_UP_EN` reader - Configures whether or not to enable timer0 period update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_PERIOD_UP_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER0_PERIOD_UP_EN` writer - Configures whether or not to enable timer0 period update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER0_PERIOD_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER1_PERIOD_UP_EN` reader - Configures whether or not to enable timer1 period update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_PERIOD_UP_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER1_PERIOD_UP_EN` writer - Configures whether or not to enable timer1 period update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER1_PERIOD_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TIMER2_PERIOD_UP_EN` reader - Configures whether or not to enable timer2 period update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_PERIOD_UP_EN_R = crate::BitReader; +#[doc = "Field `TASK_TIMER2_PERIOD_UP_EN` writer - Configures whether or not to enable timer2 period update task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TIMER2_PERIOD_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TZ0_OST_EN` reader - Configures whether or not to enable one shot trip0 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TZ0_OST_EN_R = crate::BitReader; +#[doc = "Field `TASK_TZ0_OST_EN` writer - Configures whether or not to enable one shot trip0 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TZ0_OST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TZ1_OST_EN` reader - Configures whether or not to enable one shot trip1 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TZ1_OST_EN_R = crate::BitReader; +#[doc = "Field `TASK_TZ1_OST_EN` writer - Configures whether or not to enable one shot trip1 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TZ1_OST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_TZ2_OST_EN` reader - Configures whether or not to enable one shot trip2 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TZ2_OST_EN_R = crate::BitReader; +#[doc = "Field `TASK_TZ2_OST_EN` writer - Configures whether or not to enable one shot trip2 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_TZ2_OST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_CLR0_OST_EN` reader - Configures whether or not to enable one shot trip0 clear task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CLR0_OST_EN_R = crate::BitReader; +#[doc = "Field `TASK_CLR0_OST_EN` writer - Configures whether or not to enable one shot trip0 clear task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CLR0_OST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_CLR1_OST_EN` reader - Configures whether or not to enable one shot trip1 clear task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CLR1_OST_EN_R = crate::BitReader; +#[doc = "Field `TASK_CLR1_OST_EN` writer - Configures whether or not to enable one shot trip1 clear task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CLR1_OST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_CLR2_OST_EN` reader - Configures whether or not to enable one shot trip2 clear task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CLR2_OST_EN_R = crate::BitReader; +#[doc = "Field `TASK_CLR2_OST_EN` writer - Configures whether or not to enable one shot trip2 clear task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CLR2_OST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_CAP0_EN` reader - Configures whether or not to enable capture0 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CAP0_EN_R = crate::BitReader; +#[doc = "Field `TASK_CAP0_EN` writer - Configures whether or not to enable capture0 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CAP0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_CAP1_EN` reader - Configures whether or not to enable capture1 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CAP1_EN_R = crate::BitReader; +#[doc = "Field `TASK_CAP1_EN` writer - Configures whether or not to enable capture1 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CAP1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TASK_CAP2_EN` reader - Configures whether or not to enable capture2 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CAP2_EN_R = crate::BitReader; +#[doc = "Field `TASK_CAP2_EN` writer - Configures whether or not to enable capture2 task receive.\\\\0: Disable\\\\1: Enable"] +pub type TASK_CAP2_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable PWM generator0 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_cmpr0_a_up_en(&self) -> TASK_CMPR0_A_UP_EN_R { + TASK_CMPR0_A_UP_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures whether or not to enable PWM generator1 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_cmpr1_a_up_en(&self) -> TASK_CMPR1_A_UP_EN_R { + TASK_CMPR1_A_UP_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures whether or not to enable PWM generator2 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_cmpr2_a_up_en(&self) -> TASK_CMPR2_A_UP_EN_R { + TASK_CMPR2_A_UP_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures whether or not to enable PWM generator0 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_cmpr0_b_up_en(&self) -> TASK_CMPR0_B_UP_EN_R { + TASK_CMPR0_B_UP_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures whether or not to enable PWM generator1 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_cmpr1_b_up_en(&self) -> TASK_CMPR1_B_UP_EN_R { + TASK_CMPR1_B_UP_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures whether or not to enable PWM generator2 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_cmpr2_b_up_en(&self) -> TASK_CMPR2_B_UP_EN_R { + TASK_CMPR2_B_UP_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Configures whether or not to enable all PWM generate stop task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_gen_stop_en(&self) -> TASK_GEN_STOP_EN_R { + TASK_GEN_STOP_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures whether or not to enable timer0 sync task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer0_sync_en(&self) -> TASK_TIMER0_SYNC_EN_R { + TASK_TIMER0_SYNC_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configures whether or not to enable timer1 sync task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer1_sync_en(&self) -> TASK_TIMER1_SYNC_EN_R { + TASK_TIMER1_SYNC_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures whether or not to enable timer2 sync task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer2_sync_en(&self) -> TASK_TIMER2_SYNC_EN_R { + TASK_TIMER2_SYNC_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Configures whether or not to enable timer0 period update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer0_period_up_en(&self) -> TASK_TIMER0_PERIOD_UP_EN_R { + TASK_TIMER0_PERIOD_UP_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Configures whether or not to enable timer1 period update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer1_period_up_en(&self) -> TASK_TIMER1_PERIOD_UP_EN_R { + TASK_TIMER1_PERIOD_UP_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Configures whether or not to enable timer2 period update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_timer2_period_up_en(&self) -> TASK_TIMER2_PERIOD_UP_EN_R { + TASK_TIMER2_PERIOD_UP_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Configures whether or not to enable one shot trip0 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_tz0_ost_en(&self) -> TASK_TZ0_OST_EN_R { + TASK_TZ0_OST_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Configures whether or not to enable one shot trip1 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_tz1_ost_en(&self) -> TASK_TZ1_OST_EN_R { + TASK_TZ1_OST_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Configures whether or not to enable one shot trip2 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_tz2_ost_en(&self) -> TASK_TZ2_OST_EN_R { + TASK_TZ2_OST_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Configures whether or not to enable one shot trip0 clear task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_clr0_ost_en(&self) -> TASK_CLR0_OST_EN_R { + TASK_CLR0_OST_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Configures whether or not to enable one shot trip1 clear task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_clr1_ost_en(&self) -> TASK_CLR1_OST_EN_R { + TASK_CLR1_OST_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Configures whether or not to enable one shot trip2 clear task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_clr2_ost_en(&self) -> TASK_CLR2_OST_EN_R { + TASK_CLR2_OST_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Configures whether or not to enable capture0 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_cap0_en(&self) -> TASK_CAP0_EN_R { + TASK_CAP0_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Configures whether or not to enable capture1 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_cap1_en(&self) -> TASK_CAP1_EN_R { + TASK_CAP1_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Configures whether or not to enable capture2 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn task_cap2_en(&self) -> TASK_CAP2_EN_R { + TASK_CAP2_EN_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TASK_EN") + .field( + "task_cmpr0_a_up_en", + &format_args!("{}", self.task_cmpr0_a_up_en().bit()), + ) + .field( + "task_cmpr1_a_up_en", + &format_args!("{}", self.task_cmpr1_a_up_en().bit()), + ) + .field( + "task_cmpr2_a_up_en", + &format_args!("{}", self.task_cmpr2_a_up_en().bit()), + ) + .field( + "task_cmpr0_b_up_en", + &format_args!("{}", self.task_cmpr0_b_up_en().bit()), + ) + .field( + "task_cmpr1_b_up_en", + &format_args!("{}", self.task_cmpr1_b_up_en().bit()), + ) + .field( + "task_cmpr2_b_up_en", + &format_args!("{}", self.task_cmpr2_b_up_en().bit()), + ) + .field( + "task_gen_stop_en", + &format_args!("{}", self.task_gen_stop_en().bit()), + ) + .field( + "task_timer0_sync_en", + &format_args!("{}", self.task_timer0_sync_en().bit()), + ) + .field( + "task_timer1_sync_en", + &format_args!("{}", self.task_timer1_sync_en().bit()), + ) + .field( + "task_timer2_sync_en", + &format_args!("{}", self.task_timer2_sync_en().bit()), + ) + .field( + "task_timer0_period_up_en", + &format_args!("{}", self.task_timer0_period_up_en().bit()), + ) + .field( + "task_timer1_period_up_en", + &format_args!("{}", self.task_timer1_period_up_en().bit()), + ) + .field( + "task_timer2_period_up_en", + &format_args!("{}", self.task_timer2_period_up_en().bit()), + ) + .field( + "task_tz0_ost_en", + &format_args!("{}", self.task_tz0_ost_en().bit()), + ) + .field( + "task_tz1_ost_en", + &format_args!("{}", self.task_tz1_ost_en().bit()), + ) + .field( + "task_tz2_ost_en", + &format_args!("{}", self.task_tz2_ost_en().bit()), + ) + .field( + "task_clr0_ost_en", + &format_args!("{}", self.task_clr0_ost_en().bit()), + ) + .field( + "task_clr1_ost_en", + &format_args!("{}", self.task_clr1_ost_en().bit()), + ) + .field( + "task_clr2_ost_en", + &format_args!("{}", self.task_clr2_ost_en().bit()), + ) + .field( + "task_cap0_en", + &format_args!("{}", self.task_cap0_en().bit()), + ) + .field( + "task_cap1_en", + &format_args!("{}", self.task_cap1_en().bit()), + ) + .field( + "task_cap2_en", + &format_args!("{}", self.task_cap2_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable PWM generator0 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_cmpr0_a_up_en(&mut self) -> TASK_CMPR0_A_UP_EN_W { + TASK_CMPR0_A_UP_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to enable PWM generator1 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_cmpr1_a_up_en(&mut self) -> TASK_CMPR1_A_UP_EN_W { + TASK_CMPR1_A_UP_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to enable PWM generator2 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_cmpr2_a_up_en(&mut self) -> TASK_CMPR2_A_UP_EN_W { + TASK_CMPR2_A_UP_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to enable PWM generator0 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_cmpr0_b_up_en(&mut self) -> TASK_CMPR0_B_UP_EN_W { + TASK_CMPR0_B_UP_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to enable PWM generator1 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_cmpr1_b_up_en(&mut self) -> TASK_CMPR1_B_UP_EN_W { + TASK_CMPR1_B_UP_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to enable PWM generator2 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_cmpr2_b_up_en(&mut self) -> TASK_CMPR2_B_UP_EN_W { + TASK_CMPR2_B_UP_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to enable all PWM generate stop task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_gen_stop_en(&mut self) -> TASK_GEN_STOP_EN_W { + TASK_GEN_STOP_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to enable timer0 sync task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer0_sync_en(&mut self) -> TASK_TIMER0_SYNC_EN_W { + TASK_TIMER0_SYNC_EN_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to enable timer1 sync task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer1_sync_en(&mut self) -> TASK_TIMER1_SYNC_EN_W { + TASK_TIMER1_SYNC_EN_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to enable timer2 sync task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer2_sync_en(&mut self) -> TASK_TIMER2_SYNC_EN_W { + TASK_TIMER2_SYNC_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to enable timer0 period update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer0_period_up_en(&mut self) -> TASK_TIMER0_PERIOD_UP_EN_W { + TASK_TIMER0_PERIOD_UP_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to enable timer1 period update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer1_period_up_en(&mut self) -> TASK_TIMER1_PERIOD_UP_EN_W { + TASK_TIMER1_PERIOD_UP_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to enable timer2 period update task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_timer2_period_up_en(&mut self) -> TASK_TIMER2_PERIOD_UP_EN_W { + TASK_TIMER2_PERIOD_UP_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to enable one shot trip0 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_tz0_ost_en(&mut self) -> TASK_TZ0_OST_EN_W { + TASK_TZ0_OST_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to enable one shot trip1 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_tz1_ost_en(&mut self) -> TASK_TZ1_OST_EN_W { + TASK_TZ1_OST_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to enable one shot trip2 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_tz2_ost_en(&mut self) -> TASK_TZ2_OST_EN_W { + TASK_TZ2_OST_EN_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to enable one shot trip0 clear task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_clr0_ost_en(&mut self) -> TASK_CLR0_OST_EN_W { + TASK_CLR0_OST_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to enable one shot trip1 clear task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_clr1_ost_en(&mut self) -> TASK_CLR1_OST_EN_W { + TASK_CLR1_OST_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to enable one shot trip2 clear task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_clr2_ost_en(&mut self) -> TASK_CLR2_OST_EN_W { + TASK_CLR2_OST_EN_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to enable capture0 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_cap0_en(&mut self) -> TASK_CAP0_EN_W { + TASK_CAP0_EN_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to enable capture1 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_cap1_en(&mut self) -> TASK_CAP1_EN_W { + TASK_CAP1_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to enable capture2 task receive.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn task_cap2_en(&mut self) -> TASK_CAP2_EN_W { + TASK_CAP2_EN_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Task enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_EN_SPEC; +impl crate::RegisterSpec for TASK_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`task_en::R`](R) reader structure"] +impl crate::Readable for TASK_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`task_en::W`](W) writer structure"] +impl crate::Writable for TASK_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_EN to value 0"] +impl crate::Resettable for TASK_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/timer_cfg0.rs b/esp32p4/src/mcpwm0/timer_cfg0.rs new file mode 100644 index 0000000000..0d0846a6cd --- /dev/null +++ b/esp32p4/src/mcpwm0/timer_cfg0.rs @@ -0,0 +1,104 @@ +#[doc = "Register `TIMER%s_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER%s_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_PRESCALE` reader - Configures the prescaler value of timer%s, so that the period of PT0_clk = Period of PWM_clk * (PWM_TIMER%s_PRESCALE + 1)"] +pub type TIMER_PRESCALE_R = crate::FieldReader; +#[doc = "Field `TIMER_PRESCALE` writer - Configures the prescaler value of timer%s, so that the period of PT0_clk = Period of PWM_clk * (PWM_TIMER%s_PRESCALE + 1)"] +pub type TIMER_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TIMER_PERIOD` reader - Configures the period shadow of PWM timer%s"] +pub type TIMER_PERIOD_R = crate::FieldReader; +#[doc = "Field `TIMER_PERIOD` writer - Configures the period shadow of PWM timer%s"] +pub type TIMER_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `TIMER_PERIOD_UPMETHOD` reader - Configures the update method for active register of PWM timer%s period.\\\\0: Immediate\\\\1: TEZ\\\\2: Sync\\\\3: TEZ or sync\\\\TEZ here and below means timer equal zero event"] +pub type TIMER_PERIOD_UPMETHOD_R = crate::FieldReader; +#[doc = "Field `TIMER_PERIOD_UPMETHOD` writer - Configures the update method for active register of PWM timer%s period.\\\\0: Immediate\\\\1: TEZ\\\\2: Sync\\\\3: TEZ or sync\\\\TEZ here and below means timer equal zero event"] +pub type TIMER_PERIOD_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:7 - Configures the prescaler value of timer%s, so that the period of PT0_clk = Period of PWM_clk * (PWM_TIMER%s_PRESCALE + 1)"] + #[inline(always)] + pub fn timer_prescale(&self) -> TIMER_PRESCALE_R { + TIMER_PRESCALE_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:23 - Configures the period shadow of PWM timer%s"] + #[inline(always)] + pub fn timer_period(&self) -> TIMER_PERIOD_R { + TIMER_PERIOD_R::new(((self.bits >> 8) & 0xffff) as u16) + } + #[doc = "Bits 24:25 - Configures the update method for active register of PWM timer%s period.\\\\0: Immediate\\\\1: TEZ\\\\2: Sync\\\\3: TEZ or sync\\\\TEZ here and below means timer equal zero event"] + #[inline(always)] + pub fn timer_period_upmethod(&self) -> TIMER_PERIOD_UPMETHOD_R { + TIMER_PERIOD_UPMETHOD_R::new(((self.bits >> 24) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER_CFG0") + .field( + "timer_prescale", + &format_args!("{}", self.timer_prescale().bits()), + ) + .field( + "timer_period", + &format_args!("{}", self.timer_period().bits()), + ) + .field( + "timer_period_upmethod", + &format_args!("{}", self.timer_period_upmethod().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures the prescaler value of timer%s, so that the period of PT0_clk = Period of PWM_clk * (PWM_TIMER%s_PRESCALE + 1)"] + #[inline(always)] + #[must_use] + pub fn timer_prescale(&mut self) -> TIMER_PRESCALE_W { + TIMER_PRESCALE_W::new(self, 0) + } + #[doc = "Bits 8:23 - Configures the period shadow of PWM timer%s"] + #[inline(always)] + #[must_use] + pub fn timer_period(&mut self) -> TIMER_PERIOD_W { + TIMER_PERIOD_W::new(self, 8) + } + #[doc = "Bits 24:25 - Configures the update method for active register of PWM timer%s period.\\\\0: Immediate\\\\1: TEZ\\\\2: Sync\\\\3: TEZ or sync\\\\TEZ here and below means timer equal zero event"] + #[inline(always)] + #[must_use] + pub fn timer_period_upmethod(&mut self) -> TIMER_PERIOD_UPMETHOD_W { + TIMER_PERIOD_UPMETHOD_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PWM timer%s period and update method configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER_CFG0_SPEC; +impl crate::RegisterSpec for TIMER_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer_cfg0::R`](R) reader structure"] +impl crate::Readable for TIMER_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer_cfg0::W`](W) writer structure"] +impl crate::Writable for TIMER_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMER%s_CFG0 to value 0xff00"] +impl crate::Resettable for TIMER_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0xff00; +} diff --git a/esp32p4/src/mcpwm0/timer_cfg1.rs b/esp32p4/src/mcpwm0/timer_cfg1.rs new file mode 100644 index 0000000000..9907f96a36 --- /dev/null +++ b/esp32p4/src/mcpwm0/timer_cfg1.rs @@ -0,0 +1,82 @@ +#[doc = "Register `TIMER%s_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER%s_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_START` reader - Configures whether or not to start/stop PWM timer%s.\\\\0: If PWM timer%s starts, then stops at TEZ\\\\1: If timer%s starts, then stops at TEP\\\\2: PWM timer%s starts and runs on\\\\3: Timer%s starts and stops at the next TEZ\\\\4: Timer0 starts and stops at the next TEP.\\\\TEP here and below means the event that happens when the timer equals to period"] +pub type TIMER_START_R = crate::FieldReader; +#[doc = "Field `TIMER_START` writer - Configures whether or not to start/stop PWM timer%s.\\\\0: If PWM timer%s starts, then stops at TEZ\\\\1: If timer%s starts, then stops at TEP\\\\2: PWM timer%s starts and runs on\\\\3: Timer%s starts and stops at the next TEZ\\\\4: Timer0 starts and stops at the next TEP.\\\\TEP here and below means the event that happens when the timer equals to period"] +pub type TIMER_START_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `TIMER_MOD` reader - Configures the working mode of PWM timer%s.\\\\0: Freeze\\\\1: Increase mode\\\\2: Decrease mode\\\\3: Up-down mode"] +pub type TIMER_MOD_R = crate::FieldReader; +#[doc = "Field `TIMER_MOD` writer - Configures the working mode of PWM timer%s.\\\\0: Freeze\\\\1: Increase mode\\\\2: Decrease mode\\\\3: Up-down mode"] +pub type TIMER_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:2 - Configures whether or not to start/stop PWM timer%s.\\\\0: If PWM timer%s starts, then stops at TEZ\\\\1: If timer%s starts, then stops at TEP\\\\2: PWM timer%s starts and runs on\\\\3: Timer%s starts and stops at the next TEZ\\\\4: Timer0 starts and stops at the next TEP.\\\\TEP here and below means the event that happens when the timer equals to period"] + #[inline(always)] + pub fn timer_start(&self) -> TIMER_START_R { + TIMER_START_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Configures the working mode of PWM timer%s.\\\\0: Freeze\\\\1: Increase mode\\\\2: Decrease mode\\\\3: Up-down mode"] + #[inline(always)] + pub fn timer_mod(&self) -> TIMER_MOD_R { + TIMER_MOD_R::new(((self.bits >> 3) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER_CFG1") + .field( + "timer_start", + &format_args!("{}", self.timer_start().bits()), + ) + .field("timer_mod", &format_args!("{}", self.timer_mod().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Configures whether or not to start/stop PWM timer%s.\\\\0: If PWM timer%s starts, then stops at TEZ\\\\1: If timer%s starts, then stops at TEP\\\\2: PWM timer%s starts and runs on\\\\3: Timer%s starts and stops at the next TEZ\\\\4: Timer0 starts and stops at the next TEP.\\\\TEP here and below means the event that happens when the timer equals to period"] + #[inline(always)] + #[must_use] + pub fn timer_start(&mut self) -> TIMER_START_W { + TIMER_START_W::new(self, 0) + } + #[doc = "Bits 3:4 - Configures the working mode of PWM timer%s.\\\\0: Freeze\\\\1: Increase mode\\\\2: Decrease mode\\\\3: Up-down mode"] + #[inline(always)] + #[must_use] + pub fn timer_mod(&mut self) -> TIMER_MOD_W { + TIMER_MOD_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PWM timer%s working mode and start/stop control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER_CFG1_SPEC; +impl crate::RegisterSpec for TIMER_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer_cfg1::R`](R) reader structure"] +impl crate::Readable for TIMER_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer_cfg1::W`](W) writer structure"] +impl crate::Writable for TIMER_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMER%s_CFG1 to value 0"] +impl crate::Resettable for TIMER_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/timer_status.rs b/esp32p4/src/mcpwm0/timer_status.rs new file mode 100644 index 0000000000..3a6233aa8d --- /dev/null +++ b/esp32p4/src/mcpwm0/timer_status.rs @@ -0,0 +1,50 @@ +#[doc = "Register `TIMER%s_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `TIMER_VALUE` reader - Represents current PWM timer%s counter value."] +pub type TIMER_VALUE_R = crate::FieldReader; +#[doc = "Field `TIMER_DIRECTION` reader - Represents current PWM timer%s counter direction.\\\\0: Increment\\\\1: Decrement"] +pub type TIMER_DIRECTION_R = crate::BitReader; +impl R { + #[doc = "Bits 0:15 - Represents current PWM timer%s counter value."] + #[inline(always)] + pub fn timer_value(&self) -> TIMER_VALUE_R { + TIMER_VALUE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Represents current PWM timer%s counter direction.\\\\0: Increment\\\\1: Decrement"] + #[inline(always)] + pub fn timer_direction(&self) -> TIMER_DIRECTION_R { + TIMER_DIRECTION_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER_STATUS") + .field( + "timer_value", + &format_args!("{}", self.timer_value().bits()), + ) + .field( + "timer_direction", + &format_args!("{}", self.timer_direction().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "PWM timer%s status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER_STATUS_SPEC; +impl crate::RegisterSpec for TIMER_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer_status::R`](R) reader structure"] +impl crate::Readable for TIMER_STATUS_SPEC {} +#[doc = "`reset()` method sets TIMER%s_STATUS to value 0"] +impl crate::Resettable for TIMER_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/timer_sync.rs b/esp32p4/src/mcpwm0/timer_sync.rs new file mode 100644 index 0000000000..8fc4eb5002 --- /dev/null +++ b/esp32p4/src/mcpwm0/timer_sync.rs @@ -0,0 +1,139 @@ +#[doc = "Register `TIMER%s_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER%s_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_SYNCI_EN` reader - Configures whether or not to enable timer%s reloading with phase on sync input event is enabled.\\\\0: Disable\\\\1: Enable"] +pub type TIMER_SYNCI_EN_R = crate::BitReader; +#[doc = "Field `TIMER_SYNCI_EN` writer - Configures whether or not to enable timer%s reloading with phase on sync input event is enabled.\\\\0: Disable\\\\1: Enable"] +pub type TIMER_SYNCI_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW` reader - Configures the generation of software sync. Toggling this bit will trigger a software sync."] +pub type SW_R = crate::BitReader; +#[doc = "Field `SW` writer - Configures the generation of software sync. Toggling this bit will trigger a software sync."] +pub type SW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_SYNCO_SEL` reader - Configures the selection of PWM timer%s sync_out.\\\\0: Sync_in\\\\1: TEZ\\\\2: TEP\\\\3: Invalid, sync_out selects noting"] +pub type TIMER_SYNCO_SEL_R = crate::FieldReader; +#[doc = "Field `TIMER_SYNCO_SEL` writer - Configures the selection of PWM timer%s sync_out.\\\\0: Sync_in\\\\1: TEZ\\\\2: TEP\\\\3: Invalid, sync_out selects noting"] +pub type TIMER_SYNCO_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TIMER_PHASE` reader - Configures the phase for timer%s reload on sync event."] +pub type TIMER_PHASE_R = crate::FieldReader; +#[doc = "Field `TIMER_PHASE` writer - Configures the phase for timer%s reload on sync event."] +pub type TIMER_PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `TIMER_PHASE_DIRECTION` reader - Configures the PWM timer%s's direction when timer%s mode is up-down mode.\\\\0: Increase\\\\1: Decrease"] +pub type TIMER_PHASE_DIRECTION_R = crate::BitReader; +#[doc = "Field `TIMER_PHASE_DIRECTION` writer - Configures the PWM timer%s's direction when timer%s mode is up-down mode.\\\\0: Increase\\\\1: Decrease"] +pub type TIMER_PHASE_DIRECTION_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable timer%s reloading with phase on sync input event is enabled.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn timer_synci_en(&self) -> TIMER_SYNCI_EN_R { + TIMER_SYNCI_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures the generation of software sync. Toggling this bit will trigger a software sync."] + #[inline(always)] + pub fn sw(&self) -> SW_R { + SW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Configures the selection of PWM timer%s sync_out.\\\\0: Sync_in\\\\1: TEZ\\\\2: TEP\\\\3: Invalid, sync_out selects noting"] + #[inline(always)] + pub fn timer_synco_sel(&self) -> TIMER_SYNCO_SEL_R { + TIMER_SYNCO_SEL_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:19 - Configures the phase for timer%s reload on sync event."] + #[inline(always)] + pub fn timer_phase(&self) -> TIMER_PHASE_R { + TIMER_PHASE_R::new(((self.bits >> 4) & 0xffff) as u16) + } + #[doc = "Bit 20 - Configures the PWM timer%s's direction when timer%s mode is up-down mode.\\\\0: Increase\\\\1: Decrease"] + #[inline(always)] + pub fn timer_phase_direction(&self) -> TIMER_PHASE_DIRECTION_R { + TIMER_PHASE_DIRECTION_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER_SYNC") + .field( + "timer_synci_en", + &format_args!("{}", self.timer_synci_en().bit()), + ) + .field("sw", &format_args!("{}", self.sw().bit())) + .field( + "timer_synco_sel", + &format_args!("{}", self.timer_synco_sel().bits()), + ) + .field( + "timer_phase", + &format_args!("{}", self.timer_phase().bits()), + ) + .field( + "timer_phase_direction", + &format_args!("{}", self.timer_phase_direction().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable timer%s reloading with phase on sync input event is enabled.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn timer_synci_en(&mut self) -> TIMER_SYNCI_EN_W { + TIMER_SYNCI_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures the generation of software sync. Toggling this bit will trigger a software sync."] + #[inline(always)] + #[must_use] + pub fn sw(&mut self) -> SW_W { + SW_W::new(self, 1) + } + #[doc = "Bits 2:3 - Configures the selection of PWM timer%s sync_out.\\\\0: Sync_in\\\\1: TEZ\\\\2: TEP\\\\3: Invalid, sync_out selects noting"] + #[inline(always)] + #[must_use] + pub fn timer_synco_sel(&mut self) -> TIMER_SYNCO_SEL_W { + TIMER_SYNCO_SEL_W::new(self, 2) + } + #[doc = "Bits 4:19 - Configures the phase for timer%s reload on sync event."] + #[inline(always)] + #[must_use] + pub fn timer_phase(&mut self) -> TIMER_PHASE_W { + TIMER_PHASE_W::new(self, 4) + } + #[doc = "Bit 20 - Configures the PWM timer%s's direction when timer%s mode is up-down mode.\\\\0: Increase\\\\1: Decrease"] + #[inline(always)] + #[must_use] + pub fn timer_phase_direction(&mut self) -> TIMER_PHASE_DIRECTION_W { + TIMER_PHASE_DIRECTION_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PWM timer%s sync function configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER_SYNC_SPEC; +impl crate::RegisterSpec for TIMER_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer_sync::R`](R) reader structure"] +impl crate::Readable for TIMER_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer_sync::W`](W) writer structure"] +impl crate::Writable for TIMER_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMER%s_SYNC to value 0"] +impl crate::Resettable for TIMER_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/timer_synci_cfg.rs b/esp32p4/src/mcpwm0/timer_synci_cfg.rs new file mode 100644 index 0000000000..884ccbc266 --- /dev/null +++ b/esp32p4/src/mcpwm0/timer_synci_cfg.rs @@ -0,0 +1,161 @@ +#[doc = "Register `TIMER_SYNCI_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER_SYNCI_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER0_SYNCISEL` reader - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] +pub type TIMER0_SYNCISEL_R = crate::FieldReader; +#[doc = "Field `TIMER0_SYNCISEL` writer - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] +pub type TIMER0_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `TIMER1_SYNCISEL` reader - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] +pub type TIMER1_SYNCISEL_R = crate::FieldReader; +#[doc = "Field `TIMER1_SYNCISEL` writer - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] +pub type TIMER1_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `TIMER2_SYNCISEL` reader - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] +pub type TIMER2_SYNCISEL_R = crate::FieldReader; +#[doc = "Field `TIMER2_SYNCISEL` writer - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] +pub type TIMER2_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `EXTERNAL_SYNCI0_INVERT` reader - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] +pub type EXTERNAL_SYNCI0_INVERT_R = crate::BitReader; +#[doc = "Field `EXTERNAL_SYNCI0_INVERT` writer - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] +pub type EXTERNAL_SYNCI0_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXTERNAL_SYNCI1_INVERT` reader - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] +pub type EXTERNAL_SYNCI1_INVERT_R = crate::BitReader; +#[doc = "Field `EXTERNAL_SYNCI1_INVERT` writer - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] +pub type EXTERNAL_SYNCI1_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXTERNAL_SYNCI2_INVERT` reader - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] +pub type EXTERNAL_SYNCI2_INVERT_R = crate::BitReader; +#[doc = "Field `EXTERNAL_SYNCI2_INVERT` writer - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] +pub type EXTERNAL_SYNCI2_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] + #[inline(always)] + pub fn timer0_syncisel(&self) -> TIMER0_SYNCISEL_R { + TIMER0_SYNCISEL_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] + #[inline(always)] + pub fn timer1_syncisel(&self) -> TIMER1_SYNCISEL_R { + TIMER1_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] + #[inline(always)] + pub fn timer2_syncisel(&self) -> TIMER2_SYNCISEL_R { + TIMER2_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bit 9 - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] + #[inline(always)] + pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI0_INVERT_R { + EXTERNAL_SYNCI0_INVERT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] + #[inline(always)] + pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI1_INVERT_R { + EXTERNAL_SYNCI1_INVERT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] + #[inline(always)] + pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI2_INVERT_R { + EXTERNAL_SYNCI2_INVERT_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER_SYNCI_CFG") + .field( + "timer0_syncisel", + &format_args!("{}", self.timer0_syncisel().bits()), + ) + .field( + "timer1_syncisel", + &format_args!("{}", self.timer1_syncisel().bits()), + ) + .field( + "timer2_syncisel", + &format_args!("{}", self.timer2_syncisel().bits()), + ) + .field( + "external_synci0_invert", + &format_args!("{}", self.external_synci0_invert().bit()), + ) + .field( + "external_synci1_invert", + &format_args!("{}", self.external_synci1_invert().bit()), + ) + .field( + "external_synci2_invert", + &format_args!("{}", self.external_synci2_invert().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] + #[inline(always)] + #[must_use] + pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W { + TIMER0_SYNCISEL_W::new(self, 0) + } + #[doc = "Bits 3:5 - Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] + #[inline(always)] + #[must_use] + pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W { + TIMER1_SYNCISEL_W::new(self, 3) + } + #[doc = "Bits 6:8 - Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"] + #[inline(always)] + #[must_use] + pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W { + TIMER2_SYNCISEL_W::new(self, 6) + } + #[doc = "Bit 9 - Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] + #[inline(always)] + #[must_use] + pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W { + EXTERNAL_SYNCI0_INVERT_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] + #[inline(always)] + #[must_use] + pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W { + EXTERNAL_SYNCI1_INVERT_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert"] + #[inline(always)] + #[must_use] + pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W { + EXTERNAL_SYNCI2_INVERT_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Synchronization input selection register for PWM timers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_synci_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timer_synci_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER_SYNCI_CFG_SPEC; +impl crate::RegisterSpec for TIMER_SYNCI_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer_synci_cfg::R`](R) reader structure"] +impl crate::Readable for TIMER_SYNCI_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer_synci_cfg::W`](W) writer structure"] +impl crate::Writable for TIMER_SYNCI_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMER_SYNCI_CFG to value 0"] +impl crate::Resettable for TIMER_SYNCI_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mcpwm0/update_cfg.rs b/esp32p4/src/mcpwm0/update_cfg.rs new file mode 100644 index 0000000000..4b30a3837e --- /dev/null +++ b/esp32p4/src/mcpwm0/update_cfg.rs @@ -0,0 +1,190 @@ +#[doc = "Register `UPDATE_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `UPDATE_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `GLOBAL_UP_EN` reader - Configures whether or not to enable global update for all active registers in MCPWM module.\\\\0: Disable\\\\1: Enable"] +pub type GLOBAL_UP_EN_R = crate::BitReader; +#[doc = "Field `GLOBAL_UP_EN` writer - Configures whether or not to enable global update for all active registers in MCPWM module.\\\\0: Disable\\\\1: Enable"] +pub type GLOBAL_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GLOBAL_FORCE_UP` reader - Configures the generation of global forced update for all active registers in MCPWM module. A toggle (software invert its value) will trigger a global forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1."] +pub type GLOBAL_FORCE_UP_R = crate::BitReader; +#[doc = "Field `GLOBAL_FORCE_UP` writer - Configures the generation of global forced update for all active registers in MCPWM module. A toggle (software invert its value) will trigger a global forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1."] +pub type GLOBAL_FORCE_UP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OP0_UP_EN` reader - Configures whether or not to enable update of active registers in PWM operator0. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] +pub type OP0_UP_EN_R = crate::BitReader; +#[doc = "Field `OP0_UP_EN` writer - Configures whether or not to enable update of active registers in PWM operator0. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] +pub type OP0_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OP0_FORCE_UP` reader - Configures the generation of forced update for active registers in PWM operator0. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1."] +pub type OP0_FORCE_UP_R = crate::BitReader; +#[doc = "Field `OP0_FORCE_UP` writer - Configures the generation of forced update for active registers in PWM operator0. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1."] +pub type OP0_FORCE_UP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OP1_UP_EN` reader - Configures whether or not to enable update of active registers in PWM operator1. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] +pub type OP1_UP_EN_R = crate::BitReader; +#[doc = "Field `OP1_UP_EN` writer - Configures whether or not to enable update of active registers in PWM operator1. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] +pub type OP1_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OP1_FORCE_UP` reader - Configures the generation of forced update for active registers in PWM operator1. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1."] +pub type OP1_FORCE_UP_R = crate::BitReader; +#[doc = "Field `OP1_FORCE_UP` writer - Configures the generation of forced update for active registers in PWM operator1. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1."] +pub type OP1_FORCE_UP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OP2_UP_EN` reader - Configures whether or not to enable update of active registers in PWM operator2. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] +pub type OP2_UP_EN_R = crate::BitReader; +#[doc = "Field `OP2_UP_EN` writer - Configures whether or not to enable update of active registers in PWM operator2. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] +pub type OP2_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OP2_FORCE_UP` reader - Configures the generation of forced update for active registers in PWM operator2. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1."] +pub type OP2_FORCE_UP_R = crate::BitReader; +#[doc = "Field `OP2_FORCE_UP` writer - Configures the generation of forced update for active registers in PWM operator2. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1."] +pub type OP2_FORCE_UP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to enable global update for all active registers in MCPWM module.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn global_up_en(&self) -> GLOBAL_UP_EN_R { + GLOBAL_UP_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configures the generation of global forced update for all active registers in MCPWM module. A toggle (software invert its value) will trigger a global forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1."] + #[inline(always)] + pub fn global_force_up(&self) -> GLOBAL_FORCE_UP_R { + GLOBAL_FORCE_UP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configures whether or not to enable update of active registers in PWM operator0. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn op0_up_en(&self) -> OP0_UP_EN_R { + OP0_UP_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configures the generation of forced update for active registers in PWM operator0. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1."] + #[inline(always)] + pub fn op0_force_up(&self) -> OP0_FORCE_UP_R { + OP0_FORCE_UP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configures whether or not to enable update of active registers in PWM operator1. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn op1_up_en(&self) -> OP1_UP_EN_R { + OP1_UP_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configures the generation of forced update for active registers in PWM operator1. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1."] + #[inline(always)] + pub fn op1_force_up(&self) -> OP1_FORCE_UP_R { + OP1_FORCE_UP_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Configures whether or not to enable update of active registers in PWM operator2. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn op2_up_en(&self) -> OP2_UP_EN_R { + OP2_UP_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configures the generation of forced update for active registers in PWM operator2. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1."] + #[inline(always)] + pub fn op2_force_up(&self) -> OP2_FORCE_UP_R { + OP2_FORCE_UP_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UPDATE_CFG") + .field( + "global_up_en", + &format_args!("{}", self.global_up_en().bit()), + ) + .field( + "global_force_up", + &format_args!("{}", self.global_force_up().bit()), + ) + .field("op0_up_en", &format_args!("{}", self.op0_up_en().bit())) + .field( + "op0_force_up", + &format_args!("{}", self.op0_force_up().bit()), + ) + .field("op1_up_en", &format_args!("{}", self.op1_up_en().bit())) + .field( + "op1_force_up", + &format_args!("{}", self.op1_force_up().bit()), + ) + .field("op2_up_en", &format_args!("{}", self.op2_up_en().bit())) + .field( + "op2_force_up", + &format_args!("{}", self.op2_force_up().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable global update for all active registers in MCPWM module.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn global_up_en(&mut self) -> GLOBAL_UP_EN_W { + GLOBAL_UP_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Configures the generation of global forced update for all active registers in MCPWM module. A toggle (software invert its value) will trigger a global forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1."] + #[inline(always)] + #[must_use] + pub fn global_force_up(&mut self) -> GLOBAL_FORCE_UP_W { + GLOBAL_FORCE_UP_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to enable update of active registers in PWM operator0. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn op0_up_en(&mut self) -> OP0_UP_EN_W { + OP0_UP_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Configures the generation of forced update for active registers in PWM operator0. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1."] + #[inline(always)] + #[must_use] + pub fn op0_force_up(&mut self) -> OP0_FORCE_UP_W { + OP0_FORCE_UP_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to enable update of active registers in PWM operator1. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn op1_up_en(&mut self) -> OP1_UP_EN_W { + OP1_UP_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Configures the generation of forced update for active registers in PWM operator1. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1."] + #[inline(always)] + #[must_use] + pub fn op1_force_up(&mut self) -> OP1_FORCE_UP_W { + OP1_FORCE_UP_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to enable update of active registers in PWM operator2. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn op2_up_en(&mut self) -> OP2_UP_EN_W { + OP2_UP_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Configures the generation of forced update for active registers in PWM operator2. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1."] + #[inline(always)] + #[must_use] + pub fn op2_force_up(&mut self) -> OP2_FORCE_UP_W { + OP2_FORCE_UP_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Generator Update configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`update_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`update_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UPDATE_CFG_SPEC; +impl crate::RegisterSpec for UPDATE_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`update_cfg::R`](R) reader structure"] +impl crate::Readable for UPDATE_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`update_cfg::W`](W) writer structure"] +impl crate::Writable for UPDATE_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UPDATE_CFG to value 0x05"] +impl crate::Resettable for UPDATE_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x05; +} diff --git a/esp32p4/src/mcpwm0/version.rs b/esp32p4/src/mcpwm0/version.rs new file mode 100644 index 0000000000..b5a11b0f0a --- /dev/null +++ b/esp32p4/src/mcpwm0/version.rs @@ -0,0 +1,63 @@ +#[doc = "Register `VERSION` reader"] +pub type R = crate::R; +#[doc = "Register `VERSION` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - Configures the version."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - Configures the version."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Configures the version."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VERSION") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Configures the version."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VERSION_SPEC; +impl crate::RegisterSpec for VERSION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`version::R`](R) reader structure"] +impl crate::Readable for VERSION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"] +impl crate::Writable for VERSION_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VERSION to value 0x0221_2290"] +impl crate::Resettable for VERSION_SPEC { + const RESET_VALUE: Self::Ux = 0x0221_2290; +} diff --git a/esp32p4/src/mipi_csi_bridge.rs b/esp32p4/src/mipi_csi_bridge.rs new file mode 100644 index 0000000000..ada14925ec --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge.rs @@ -0,0 +1,187 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + clk_en: CLK_EN, + csi_en: CSI_EN, + dma_req_cfg: DMA_REQ_CFG, + buf_flow_ctl: BUF_FLOW_CTL, + data_type_cfg: DATA_TYPE_CFG, + frame_cfg: FRAME_CFG, + endian_mode: ENDIAN_MODE, + int_raw: INT_RAW, + int_clr: INT_CLR, + int_st: INT_ST, + int_ena: INT_ENA, + dma_req_interval: DMA_REQ_INTERVAL, + dmablk_size: DMABLK_SIZE, + rdn_eco_cs: RDN_ECO_CS, + rdn_eco_low: RDN_ECO_LOW, + rdn_eco_high: RDN_ECO_HIGH, + host_ctrl: HOST_CTRL, + mem_ctrl: MEM_CTRL, +} +impl RegisterBlock { + #[doc = "0x00 - csi bridge register mapping unit clock gating."] + #[inline(always)] + pub const fn clk_en(&self) -> &CLK_EN { + &self.clk_en + } + #[doc = "0x04 - csi bridge enable."] + #[inline(always)] + pub const fn csi_en(&self) -> &CSI_EN { + &self.csi_en + } + #[doc = "0x08 - dma request configuration."] + #[inline(always)] + pub const fn dma_req_cfg(&self) -> &DMA_REQ_CFG { + &self.dma_req_cfg + } + #[doc = "0x0c - csi bridge buffer control."] + #[inline(always)] + pub const fn buf_flow_ctl(&self) -> &BUF_FLOW_CTL { + &self.buf_flow_ctl + } + #[doc = "0x10 - pixel data type configuration."] + #[inline(always)] + pub const fn data_type_cfg(&self) -> &DATA_TYPE_CFG { + &self.data_type_cfg + } + #[doc = "0x14 - frame configuration."] + #[inline(always)] + pub const fn frame_cfg(&self) -> &FRAME_CFG { + &self.frame_cfg + } + #[doc = "0x18 - data endianness order configuration."] + #[inline(always)] + pub const fn endian_mode(&self) -> &ENDIAN_MODE { + &self.endian_mode + } + #[doc = "0x1c - csi bridge interrupt raw."] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x20 - csi bridge interrupt clr."] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x24 - csi bridge interrupt st."] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x28 - csi bridge interrupt enable."] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x2c - DMA interval configuration."] + #[inline(always)] + pub const fn dma_req_interval(&self) -> &DMA_REQ_INTERVAL { + &self.dma_req_interval + } + #[doc = "0x30 - DMA block size configuration."] + #[inline(always)] + pub const fn dmablk_size(&self) -> &DMABLK_SIZE { + &self.dmablk_size + } + #[doc = "0x34 - N/A"] + #[inline(always)] + pub const fn rdn_eco_cs(&self) -> &RDN_ECO_CS { + &self.rdn_eco_cs + } + #[doc = "0x38 - N/A"] + #[inline(always)] + pub const fn rdn_eco_low(&self) -> &RDN_ECO_LOW { + &self.rdn_eco_low + } + #[doc = "0x3c - N/A"] + #[inline(always)] + pub const fn rdn_eco_high(&self) -> &RDN_ECO_HIGH { + &self.rdn_eco_high + } + #[doc = "0x40 - csi host control by csi bridge."] + #[inline(always)] + pub const fn host_ctrl(&self) -> &HOST_CTRL { + &self.host_ctrl + } + #[doc = "0x44 - csi bridge buffer control."] + #[inline(always)] + pub const fn mem_ctrl(&self) -> &MEM_CTRL { + &self.mem_ctrl + } +} +#[doc = "CLK_EN (rw) register accessor: csi bridge register mapping unit clock gating.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_en`] module"] +pub type CLK_EN = crate::Reg; +#[doc = "csi bridge register mapping unit clock gating."] +pub mod clk_en; +#[doc = "CSI_EN (rw) register accessor: csi bridge enable.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csi_en`] module"] +pub type CSI_EN = crate::Reg; +#[doc = "csi bridge enable."] +pub mod csi_en; +#[doc = "DMA_REQ_CFG (rw) register accessor: dma request configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_req_cfg`] module"] +pub type DMA_REQ_CFG = crate::Reg; +#[doc = "dma request configuration."] +pub mod dma_req_cfg; +#[doc = "BUF_FLOW_CTL (rw) register accessor: csi bridge buffer control.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buf_flow_ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buf_flow_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@buf_flow_ctl`] module"] +pub type BUF_FLOW_CTL = crate::Reg; +#[doc = "csi bridge buffer control."] +pub mod buf_flow_ctl; +#[doc = "DATA_TYPE_CFG (rw) register accessor: pixel data type configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_type_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_type_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_type_cfg`] module"] +pub type DATA_TYPE_CFG = crate::Reg; +#[doc = "pixel data type configuration."] +pub mod data_type_cfg; +#[doc = "FRAME_CFG (rw) register accessor: frame configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frame_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frame_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frame_cfg`] module"] +pub type FRAME_CFG = crate::Reg; +#[doc = "frame configuration."] +pub mod frame_cfg; +#[doc = "ENDIAN_MODE (rw) register accessor: data endianness order configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endian_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endian_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endian_mode`] module"] +pub type ENDIAN_MODE = crate::Reg; +#[doc = "data endianness order configuration."] +pub mod endian_mode; +#[doc = "INT_RAW (rw) register accessor: csi bridge interrupt raw.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "csi bridge interrupt raw."] +pub mod int_raw; +#[doc = "INT_CLR (w) register accessor: csi bridge interrupt clr.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "csi bridge interrupt clr."] +pub mod int_clr; +#[doc = "INT_ST (r) register accessor: csi bridge interrupt st.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "csi bridge interrupt st."] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: csi bridge interrupt enable.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "csi bridge interrupt enable."] +pub mod int_ena; +#[doc = "DMA_REQ_INTERVAL (rw) register accessor: DMA interval configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_interval::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_interval::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_req_interval`] module"] +pub type DMA_REQ_INTERVAL = crate::Reg; +#[doc = "DMA interval configuration."] +pub mod dma_req_interval; +#[doc = "DMABLK_SIZE (rw) register accessor: DMA block size configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmablk_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmablk_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmablk_size`] module"] +pub type DMABLK_SIZE = crate::Reg; +#[doc = "DMA block size configuration."] +pub mod dmablk_size; +#[doc = "RDN_ECO_CS (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_cs`] module"] +pub type RDN_ECO_CS = crate::Reg; +#[doc = "N/A"] +pub mod rdn_eco_cs; +#[doc = "RDN_ECO_LOW (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_low`] module"] +pub type RDN_ECO_LOW = crate::Reg; +#[doc = "N/A"] +pub mod rdn_eco_low; +#[doc = "RDN_ECO_HIGH (rw) register accessor: N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_high`] module"] +pub type RDN_ECO_HIGH = crate::Reg; +#[doc = "N/A"] +pub mod rdn_eco_high; +#[doc = "HOST_CTRL (rw) register accessor: csi host control by csi bridge.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@host_ctrl`] module"] +pub type HOST_CTRL = crate::Reg; +#[doc = "csi host control by csi bridge."] +pub mod host_ctrl; +#[doc = "MEM_CTRL (rw) register accessor: csi bridge buffer control.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_ctrl`] module"] +pub type MEM_CTRL = crate::Reg; +#[doc = "csi bridge buffer control."] +pub mod mem_ctrl; diff --git a/esp32p4/src/mipi_csi_bridge/buf_flow_ctl.rs b/esp32p4/src/mipi_csi_bridge/buf_flow_ctl.rs new file mode 100644 index 0000000000..c1a0178735 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/buf_flow_ctl.rs @@ -0,0 +1,77 @@ +#[doc = "Register `BUF_FLOW_CTL` reader"] +pub type R = crate::R; +#[doc = "Register `BUF_FLOW_CTL` writer"] +pub type W = crate::W; +#[doc = "Field `CSI_BUF_AFULL_THRD` reader - buffer almost full threshold."] +pub type CSI_BUF_AFULL_THRD_R = crate::FieldReader; +#[doc = "Field `CSI_BUF_AFULL_THRD` writer - buffer almost full threshold."] +pub type CSI_BUF_AFULL_THRD_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `CSI_BUF_DEPTH` reader - buffer data count."] +pub type CSI_BUF_DEPTH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:13 - buffer almost full threshold."] + #[inline(always)] + pub fn csi_buf_afull_thrd(&self) -> CSI_BUF_AFULL_THRD_R { + CSI_BUF_AFULL_THRD_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 16:29 - buffer data count."] + #[inline(always)] + pub fn csi_buf_depth(&self) -> CSI_BUF_DEPTH_R { + CSI_BUF_DEPTH_R::new(((self.bits >> 16) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUF_FLOW_CTL") + .field( + "csi_buf_afull_thrd", + &format_args!("{}", self.csi_buf_afull_thrd().bits()), + ) + .field( + "csi_buf_depth", + &format_args!("{}", self.csi_buf_depth().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - buffer almost full threshold."] + #[inline(always)] + #[must_use] + pub fn csi_buf_afull_thrd(&mut self) -> CSI_BUF_AFULL_THRD_W { + CSI_BUF_AFULL_THRD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "csi bridge buffer control.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buf_flow_ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buf_flow_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUF_FLOW_CTL_SPEC; +impl crate::RegisterSpec for BUF_FLOW_CTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`buf_flow_ctl::R`](R) reader structure"] +impl crate::Readable for BUF_FLOW_CTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`buf_flow_ctl::W`](W) writer structure"] +impl crate::Writable for BUF_FLOW_CTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BUF_FLOW_CTL to value 0x07f8"] +impl crate::Resettable for BUF_FLOW_CTL_SPEC { + const RESET_VALUE: Self::Ux = 0x07f8; +} diff --git a/esp32p4/src/mipi_csi_bridge/clk_en.rs b/esp32p4/src/mipi_csi_bridge/clk_en.rs new file mode 100644 index 0000000000..d201d9c619 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/clk_en.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLK_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_EN` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - 0: enable clock gating. 1: disable clock gating, clock always on."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - 0: enable clock gating. 1: disable clock gating, clock always on."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 0: enable clock gating. 1: disable clock gating, clock always on."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_EN") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 0: enable clock gating. 1: disable clock gating, clock always on."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "csi bridge register mapping unit clock gating.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_EN_SPEC; +impl crate::RegisterSpec for CLK_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_en::R`](R) reader structure"] +impl crate::Readable for CLK_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_en::W`](W) writer structure"] +impl crate::Writable for CLK_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_EN to value 0"] +impl crate::Resettable for CLK_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_bridge/csi_en.rs b/esp32p4/src/mipi_csi_bridge/csi_en.rs new file mode 100644 index 0000000000..47983a02d5 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/csi_en.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CSI_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CSI_EN` writer"] +pub type W = crate::W; +#[doc = "Field `CSI_BRIG_EN` reader - 0: disable csi bridge. 1: enable csi bridge."] +pub type CSI_BRIG_EN_R = crate::BitReader; +#[doc = "Field `CSI_BRIG_EN` writer - 0: disable csi bridge. 1: enable csi bridge."] +pub type CSI_BRIG_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 0: disable csi bridge. 1: enable csi bridge."] + #[inline(always)] + pub fn csi_brig_en(&self) -> CSI_BRIG_EN_R { + CSI_BRIG_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CSI_EN") + .field("csi_brig_en", &format_args!("{}", self.csi_brig_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 0: disable csi bridge. 1: enable csi bridge."] + #[inline(always)] + #[must_use] + pub fn csi_brig_en(&mut self) -> CSI_BRIG_EN_W { + CSI_BRIG_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "csi bridge enable.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CSI_EN_SPEC; +impl crate::RegisterSpec for CSI_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`csi_en::R`](R) reader structure"] +impl crate::Readable for CSI_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csi_en::W`](W) writer structure"] +impl crate::Writable for CSI_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CSI_EN to value 0"] +impl crate::Resettable for CSI_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_bridge/data_type_cfg.rs b/esp32p4/src/mipi_csi_bridge/data_type_cfg.rs new file mode 100644 index 0000000000..64e2d3c80c --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/data_type_cfg.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DATA_TYPE_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_TYPE_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_TYPE_MIN` reader - the min value of data type used for pixel filter."] +pub type DATA_TYPE_MIN_R = crate::FieldReader; +#[doc = "Field `DATA_TYPE_MIN` writer - the min value of data type used for pixel filter."] +pub type DATA_TYPE_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `DATA_TYPE_MAX` reader - the max value of data type used for pixel filter."] +pub type DATA_TYPE_MAX_R = crate::FieldReader; +#[doc = "Field `DATA_TYPE_MAX` writer - the max value of data type used for pixel filter."] +pub type DATA_TYPE_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - the min value of data type used for pixel filter."] + #[inline(always)] + pub fn data_type_min(&self) -> DATA_TYPE_MIN_R { + DATA_TYPE_MIN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:13 - the max value of data type used for pixel filter."] + #[inline(always)] + pub fn data_type_max(&self) -> DATA_TYPE_MAX_R { + DATA_TYPE_MAX_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_TYPE_CFG") + .field( + "data_type_min", + &format_args!("{}", self.data_type_min().bits()), + ) + .field( + "data_type_max", + &format_args!("{}", self.data_type_max().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - the min value of data type used for pixel filter."] + #[inline(always)] + #[must_use] + pub fn data_type_min(&mut self) -> DATA_TYPE_MIN_W { + DATA_TYPE_MIN_W::new(self, 0) + } + #[doc = "Bits 8:13 - the max value of data type used for pixel filter."] + #[inline(always)] + #[must_use] + pub fn data_type_max(&mut self) -> DATA_TYPE_MAX_W { + DATA_TYPE_MAX_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "pixel data type configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_type_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_type_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_TYPE_CFG_SPEC; +impl crate::RegisterSpec for DATA_TYPE_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_type_cfg::R`](R) reader structure"] +impl crate::Readable for DATA_TYPE_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_type_cfg::W`](W) writer structure"] +impl crate::Writable for DATA_TYPE_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_TYPE_CFG to value 0x2f18"] +impl crate::Resettable for DATA_TYPE_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x2f18; +} diff --git a/esp32p4/src/mipi_csi_bridge/dma_req_cfg.rs b/esp32p4/src/mipi_csi_bridge/dma_req_cfg.rs new file mode 100644 index 0000000000..a9723d37c3 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/dma_req_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DMA_REQ_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_REQ_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_BURST_LEN` reader - DMA burst length."] +pub type DMA_BURST_LEN_R = crate::FieldReader; +#[doc = "Field `DMA_BURST_LEN` writer - DMA burst length."] +pub type DMA_BURST_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `DMA_CFG_UPD_BY_BLK` reader - 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: updated by frame."] +pub type DMA_CFG_UPD_BY_BLK_R = crate::BitReader; +#[doc = "Field `DMA_CFG_UPD_BY_BLK` writer - 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: updated by frame."] +pub type DMA_CFG_UPD_BY_BLK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_FORCE_RD_STATUS` reader - 1: mask dma request when reading frame info. 0: disable mask."] +pub type DMA_FORCE_RD_STATUS_R = crate::BitReader; +#[doc = "Field `DMA_FORCE_RD_STATUS` writer - 1: mask dma request when reading frame info. 0: disable mask."] +pub type DMA_FORCE_RD_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:11 - DMA burst length."] + #[inline(always)] + pub fn dma_burst_len(&self) -> DMA_BURST_LEN_R { + DMA_BURST_LEN_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bit 12 - 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: updated by frame."] + #[inline(always)] + pub fn dma_cfg_upd_by_blk(&self) -> DMA_CFG_UPD_BY_BLK_R { + DMA_CFG_UPD_BY_BLK_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - 1: mask dma request when reading frame info. 0: disable mask."] + #[inline(always)] + pub fn dma_force_rd_status(&self) -> DMA_FORCE_RD_STATUS_R { + DMA_FORCE_RD_STATUS_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_REQ_CFG") + .field( + "dma_burst_len", + &format_args!("{}", self.dma_burst_len().bits()), + ) + .field( + "dma_cfg_upd_by_blk", + &format_args!("{}", self.dma_cfg_upd_by_blk().bit()), + ) + .field( + "dma_force_rd_status", + &format_args!("{}", self.dma_force_rd_status().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - DMA burst length."] + #[inline(always)] + #[must_use] + pub fn dma_burst_len(&mut self) -> DMA_BURST_LEN_W { + DMA_BURST_LEN_W::new(self, 0) + } + #[doc = "Bit 12 - 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: updated by frame."] + #[inline(always)] + #[must_use] + pub fn dma_cfg_upd_by_blk(&mut self) -> DMA_CFG_UPD_BY_BLK_W { + DMA_CFG_UPD_BY_BLK_W::new(self, 12) + } + #[doc = "Bit 16 - 1: mask dma request when reading frame info. 0: disable mask."] + #[inline(always)] + #[must_use] + pub fn dma_force_rd_status(&mut self) -> DMA_FORCE_RD_STATUS_W { + DMA_FORCE_RD_STATUS_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dma request configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_REQ_CFG_SPEC; +impl crate::RegisterSpec for DMA_REQ_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_req_cfg::R`](R) reader structure"] +impl crate::Readable for DMA_REQ_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_req_cfg::W`](W) writer structure"] +impl crate::Writable for DMA_REQ_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_REQ_CFG to value 0x80"] +impl crate::Resettable for DMA_REQ_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/mipi_csi_bridge/dma_req_interval.rs b/esp32p4/src/mipi_csi_bridge/dma_req_interval.rs new file mode 100644 index 0000000000..a22d45b827 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/dma_req_interval.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DMA_REQ_INTERVAL` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_REQ_INTERVAL` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_REQ_INTERVAL` reader - 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle."] +pub type DMA_REQ_INTERVAL_R = crate::FieldReader; +#[doc = "Field `DMA_REQ_INTERVAL` writer - 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle."] +pub type DMA_REQ_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle."] + #[inline(always)] + pub fn dma_req_interval(&self) -> DMA_REQ_INTERVAL_R { + DMA_REQ_INTERVAL_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_REQ_INTERVAL") + .field( + "dma_req_interval", + &format_args!("{}", self.dma_req_interval().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle."] + #[inline(always)] + #[must_use] + pub fn dma_req_interval(&mut self) -> DMA_REQ_INTERVAL_W { + DMA_REQ_INTERVAL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DMA interval configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_interval::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_interval::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_REQ_INTERVAL_SPEC; +impl crate::RegisterSpec for DMA_REQ_INTERVAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_req_interval::R`](R) reader structure"] +impl crate::Readable for DMA_REQ_INTERVAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_req_interval::W`](W) writer structure"] +impl crate::Writable for DMA_REQ_INTERVAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_REQ_INTERVAL to value 0x01"] +impl crate::Resettable for DMA_REQ_INTERVAL_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/mipi_csi_bridge/dmablk_size.rs b/esp32p4/src/mipi_csi_bridge/dmablk_size.rs new file mode 100644 index 0000000000..73c78851a5 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/dmablk_size.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DMABLK_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `DMABLK_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `DMABLK_SIZE` reader - the number of reg_dma_burst_len in a block"] +pub type DMABLK_SIZE_R = crate::FieldReader; +#[doc = "Field `DMABLK_SIZE` writer - the number of reg_dma_burst_len in a block"] +pub type DMABLK_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:12 - the number of reg_dma_burst_len in a block"] + #[inline(always)] + pub fn dmablk_size(&self) -> DMABLK_SIZE_R { + DMABLK_SIZE_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMABLK_SIZE") + .field( + "dmablk_size", + &format_args!("{}", self.dmablk_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:12 - the number of reg_dma_burst_len in a block"] + #[inline(always)] + #[must_use] + pub fn dmablk_size(&mut self) -> DMABLK_SIZE_W { + DMABLK_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DMA block size configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmablk_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmablk_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMABLK_SIZE_SPEC; +impl crate::RegisterSpec for DMABLK_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmablk_size::R`](R) reader structure"] +impl crate::Readable for DMABLK_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dmablk_size::W`](W) writer structure"] +impl crate::Writable for DMABLK_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMABLK_SIZE to value 0x1fff"] +impl crate::Resettable for DMABLK_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0x1fff; +} diff --git a/esp32p4/src/mipi_csi_bridge/endian_mode.rs b/esp32p4/src/mipi_csi_bridge/endian_mode.rs new file mode 100644 index 0000000000..148fa19963 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/endian_mode.rs @@ -0,0 +1,85 @@ +#[doc = "Register `ENDIAN_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `ENDIAN_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE_ENDIAN_ORDER` reader - endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) when isp is bapassed."] +pub type BYTE_ENDIAN_ORDER_R = crate::BitReader; +#[doc = "Field `BYTE_ENDIAN_ORDER` writer - endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) when isp is bapassed."] +pub type BYTE_ENDIAN_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BIT_ENDIAN_ORDER` reader - N/A"] +pub type BIT_ENDIAN_ORDER_R = crate::BitReader; +#[doc = "Field `BIT_ENDIAN_ORDER` writer - N/A"] +pub type BIT_ENDIAN_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) when isp is bapassed."] + #[inline(always)] + pub fn byte_endian_order(&self) -> BYTE_ENDIAN_ORDER_R { + BYTE_ENDIAN_ORDER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + pub fn bit_endian_order(&self) -> BIT_ENDIAN_ORDER_R { + BIT_ENDIAN_ORDER_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENDIAN_MODE") + .field( + "byte_endian_order", + &format_args!("{}", self.byte_endian_order().bit()), + ) + .field( + "bit_endian_order", + &format_args!("{}", self.bit_endian_order().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) when isp is bapassed."] + #[inline(always)] + #[must_use] + pub fn byte_endian_order(&mut self) -> BYTE_ENDIAN_ORDER_W { + BYTE_ENDIAN_ORDER_W::new(self, 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + #[must_use] + pub fn bit_endian_order(&mut self) -> BIT_ENDIAN_ORDER_W { + BIT_ENDIAN_ORDER_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "data endianness order configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endian_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endian_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENDIAN_MODE_SPEC; +impl crate::RegisterSpec for ENDIAN_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`endian_mode::R`](R) reader structure"] +impl crate::Readable for ENDIAN_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`endian_mode::W`](W) writer structure"] +impl crate::Writable for ENDIAN_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENDIAN_MODE to value 0"] +impl crate::Resettable for ENDIAN_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_bridge/frame_cfg.rs b/esp32p4/src/mipi_csi_bridge/frame_cfg.rs new file mode 100644 index 0000000000..457b1f7820 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/frame_cfg.rs @@ -0,0 +1,114 @@ +#[doc = "Register `FRAME_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FRAME_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `VADR_NUM` reader - vadr of frame data."] +pub type VADR_NUM_R = crate::FieldReader; +#[doc = "Field `VADR_NUM` writer - vadr of frame data."] +pub type VADR_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `HADR_NUM` reader - hadr of frame data."] +pub type HADR_NUM_R = crate::FieldReader; +#[doc = "Field `HADR_NUM` writer - hadr of frame data."] +pub type HADR_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `HAS_HSYNC_E` reader - 0: frame data doesn't contain hsync. 1: frame data contains hsync."] +pub type HAS_HSYNC_E_R = crate::BitReader; +#[doc = "Field `HAS_HSYNC_E` writer - 0: frame data doesn't contain hsync. 1: frame data contains hsync."] +pub type HAS_HSYNC_E_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VADR_NUM_CHECK` reader - 0: disable vadr check. 1: enable vadr check."] +pub type VADR_NUM_CHECK_R = crate::BitReader; +#[doc = "Field `VADR_NUM_CHECK` writer - 0: disable vadr check. 1: enable vadr check."] +pub type VADR_NUM_CHECK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:11 - vadr of frame data."] + #[inline(always)] + pub fn vadr_num(&self) -> VADR_NUM_R { + VADR_NUM_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:23 - hadr of frame data."] + #[inline(always)] + pub fn hadr_num(&self) -> HADR_NUM_R { + HADR_NUM_R::new(((self.bits >> 12) & 0x0fff) as u16) + } + #[doc = "Bit 24 - 0: frame data doesn't contain hsync. 1: frame data contains hsync."] + #[inline(always)] + pub fn has_hsync_e(&self) -> HAS_HSYNC_E_R { + HAS_HSYNC_E_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - 0: disable vadr check. 1: enable vadr check."] + #[inline(always)] + pub fn vadr_num_check(&self) -> VADR_NUM_CHECK_R { + VADR_NUM_CHECK_R::new(((self.bits >> 25) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FRAME_CFG") + .field("vadr_num", &format_args!("{}", self.vadr_num().bits())) + .field("hadr_num", &format_args!("{}", self.hadr_num().bits())) + .field("has_hsync_e", &format_args!("{}", self.has_hsync_e().bit())) + .field( + "vadr_num_check", + &format_args!("{}", self.vadr_num_check().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - vadr of frame data."] + #[inline(always)] + #[must_use] + pub fn vadr_num(&mut self) -> VADR_NUM_W { + VADR_NUM_W::new(self, 0) + } + #[doc = "Bits 12:23 - hadr of frame data."] + #[inline(always)] + #[must_use] + pub fn hadr_num(&mut self) -> HADR_NUM_W { + HADR_NUM_W::new(self, 12) + } + #[doc = "Bit 24 - 0: frame data doesn't contain hsync. 1: frame data contains hsync."] + #[inline(always)] + #[must_use] + pub fn has_hsync_e(&mut self) -> HAS_HSYNC_E_W { + HAS_HSYNC_E_W::new(self, 24) + } + #[doc = "Bit 25 - 0: disable vadr check. 1: enable vadr check."] + #[inline(always)] + #[must_use] + pub fn vadr_num_check(&mut self) -> VADR_NUM_CHECK_W { + VADR_NUM_CHECK_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "frame configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frame_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frame_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FRAME_CFG_SPEC; +impl crate::RegisterSpec for FRAME_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`frame_cfg::R`](R) reader structure"] +impl crate::Readable for FRAME_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`frame_cfg::W`](W) writer structure"] +impl crate::Writable for FRAME_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FRAME_CFG to value 0x011e_01e0"] +impl crate::Resettable for FRAME_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x011e_01e0; +} diff --git a/esp32p4/src/mipi_csi_bridge/host_ctrl.rs b/esp32p4/src/mipi_csi_bridge/host_ctrl.rs new file mode 100644 index 0000000000..29ca1e7147 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/host_ctrl.rs @@ -0,0 +1,104 @@ +#[doc = "Register `HOST_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HOST_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CSI_ENABLECLK` reader - enable clock lane module of csi phy."] +pub type CSI_ENABLECLK_R = crate::BitReader; +#[doc = "Field `CSI_ENABLECLK` writer - enable clock lane module of csi phy."] +pub type CSI_ENABLECLK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSI_CFG_CLK_EN` reader - enable cfg_clk of csi host module."] +pub type CSI_CFG_CLK_EN_R = crate::BitReader; +#[doc = "Field `CSI_CFG_CLK_EN` writer - enable cfg_clk of csi host module."] +pub type CSI_CFG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOPBK_TEST_EN` reader - for phy test by loopback dsi phy to csi phy."] +pub type LOOPBK_TEST_EN_R = crate::BitReader; +#[doc = "Field `LOOPBK_TEST_EN` writer - for phy test by loopback dsi phy to csi phy."] +pub type LOOPBK_TEST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - enable clock lane module of csi phy."] + #[inline(always)] + pub fn csi_enableclk(&self) -> CSI_ENABLECLK_R { + CSI_ENABLECLK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - enable cfg_clk of csi host module."] + #[inline(always)] + pub fn csi_cfg_clk_en(&self) -> CSI_CFG_CLK_EN_R { + CSI_CFG_CLK_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - for phy test by loopback dsi phy to csi phy."] + #[inline(always)] + pub fn loopbk_test_en(&self) -> LOOPBK_TEST_EN_R { + LOOPBK_TEST_EN_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HOST_CTRL") + .field( + "csi_enableclk", + &format_args!("{}", self.csi_enableclk().bit()), + ) + .field( + "csi_cfg_clk_en", + &format_args!("{}", self.csi_cfg_clk_en().bit()), + ) + .field( + "loopbk_test_en", + &format_args!("{}", self.loopbk_test_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - enable clock lane module of csi phy."] + #[inline(always)] + #[must_use] + pub fn csi_enableclk(&mut self) -> CSI_ENABLECLK_W { + CSI_ENABLECLK_W::new(self, 0) + } + #[doc = "Bit 1 - enable cfg_clk of csi host module."] + #[inline(always)] + #[must_use] + pub fn csi_cfg_clk_en(&mut self) -> CSI_CFG_CLK_EN_W { + CSI_CFG_CLK_EN_W::new(self, 1) + } + #[doc = "Bit 2 - for phy test by loopback dsi phy to csi phy."] + #[inline(always)] + #[must_use] + pub fn loopbk_test_en(&mut self) -> LOOPBK_TEST_EN_W { + LOOPBK_TEST_EN_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "csi host control by csi bridge.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HOST_CTRL_SPEC; +impl crate::RegisterSpec for HOST_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`host_ctrl::R`](R) reader structure"] +impl crate::Readable for HOST_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`host_ctrl::W`](W) writer structure"] +impl crate::Writable for HOST_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HOST_CTRL to value 0x03"] +impl crate::Resettable for HOST_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/mipi_csi_bridge/int_clr.rs b/esp32p4/src/mipi_csi_bridge/int_clr.rs new file mode 100644 index 0000000000..f280476687 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/int_clr.rs @@ -0,0 +1,82 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `VADR_NUM_GT_REAL_INT_CLR` writer - reg_vadr_num is greater than real interrupt clr."] +pub type VADR_NUM_GT_REAL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VADR_NUM_LT_REAL_INT_CLR` writer - reg_vadr_num is less than real interrupt clr."] +pub type VADR_NUM_LT_REAL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DISCARD_INT_CLR` writer - an incomplete frame of data was sent interrupt clr."] +pub type DISCARD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSI_BUF_OVERRUN_INT_CLR` writer - buffer overrun interrupt clr."] +pub type CSI_BUF_OVERRUN_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSI_ASYNC_FIFO_OVF_INT_CLR` writer - buffer overflow interrupt clr."] +pub type CSI_ASYNC_FIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_CFG_HAS_UPDATED_INT_CLR` writer - dma configuration update complete interrupt clr."] +pub type DMA_CFG_HAS_UPDATED_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - reg_vadr_num is greater than real interrupt clr."] + #[inline(always)] + #[must_use] + pub fn vadr_num_gt_real_int_clr(&mut self) -> VADR_NUM_GT_REAL_INT_CLR_W { + VADR_NUM_GT_REAL_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - reg_vadr_num is less than real interrupt clr."] + #[inline(always)] + #[must_use] + pub fn vadr_num_lt_real_int_clr(&mut self) -> VADR_NUM_LT_REAL_INT_CLR_W { + VADR_NUM_LT_REAL_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - an incomplete frame of data was sent interrupt clr."] + #[inline(always)] + #[must_use] + pub fn discard_int_clr(&mut self) -> DISCARD_INT_CLR_W { + DISCARD_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - buffer overrun interrupt clr."] + #[inline(always)] + #[must_use] + pub fn csi_buf_overrun_int_clr(&mut self) -> CSI_BUF_OVERRUN_INT_CLR_W { + CSI_BUF_OVERRUN_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - buffer overflow interrupt clr."] + #[inline(always)] + #[must_use] + pub fn csi_async_fifo_ovf_int_clr(&mut self) -> CSI_ASYNC_FIFO_OVF_INT_CLR_W { + CSI_ASYNC_FIFO_OVF_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - dma configuration update complete interrupt clr."] + #[inline(always)] + #[must_use] + pub fn dma_cfg_has_updated_int_clr(&mut self) -> DMA_CFG_HAS_UPDATED_INT_CLR_W { + DMA_CFG_HAS_UPDATED_INT_CLR_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "csi bridge interrupt clr.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_bridge/int_ena.rs b/esp32p4/src/mipi_csi_bridge/int_ena.rs new file mode 100644 index 0000000000..693fba1f6c --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/int_ena.rs @@ -0,0 +1,161 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `VADR_NUM_GT_INT_ENA` reader - reg_vadr_num is greater than real interrupt enable."] +pub type VADR_NUM_GT_INT_ENA_R = crate::BitReader; +#[doc = "Field `VADR_NUM_GT_INT_ENA` writer - reg_vadr_num is greater than real interrupt enable."] +pub type VADR_NUM_GT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VADR_NUM_LT_INT_ENA` reader - reg_vadr_num is less than real interrupt enable."] +pub type VADR_NUM_LT_INT_ENA_R = crate::BitReader; +#[doc = "Field `VADR_NUM_LT_INT_ENA` writer - reg_vadr_num is less than real interrupt enable."] +pub type VADR_NUM_LT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DISCARD_INT_ENA` reader - an incomplete frame of data was sent interrupt enable."] +pub type DISCARD_INT_ENA_R = crate::BitReader; +#[doc = "Field `DISCARD_INT_ENA` writer - an incomplete frame of data was sent interrupt enable."] +pub type DISCARD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSI_BUF_OVERRUN_INT_ENA` reader - buffer overrun interrupt enable."] +pub type CSI_BUF_OVERRUN_INT_ENA_R = crate::BitReader; +#[doc = "Field `CSI_BUF_OVERRUN_INT_ENA` writer - buffer overrun interrupt enable."] +pub type CSI_BUF_OVERRUN_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSI_ASYNC_FIFO_OVF_INT_ENA` reader - buffer overflow interrupt enable."] +pub type CSI_ASYNC_FIFO_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `CSI_ASYNC_FIFO_OVF_INT_ENA` writer - buffer overflow interrupt enable."] +pub type CSI_ASYNC_FIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_CFG_HAS_UPDATED_INT_ENA` reader - dma configuration update complete interrupt enable."] +pub type DMA_CFG_HAS_UPDATED_INT_ENA_R = crate::BitReader; +#[doc = "Field `DMA_CFG_HAS_UPDATED_INT_ENA` writer - dma configuration update complete interrupt enable."] +pub type DMA_CFG_HAS_UPDATED_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - reg_vadr_num is greater than real interrupt enable."] + #[inline(always)] + pub fn vadr_num_gt_int_ena(&self) -> VADR_NUM_GT_INT_ENA_R { + VADR_NUM_GT_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - reg_vadr_num is less than real interrupt enable."] + #[inline(always)] + pub fn vadr_num_lt_int_ena(&self) -> VADR_NUM_LT_INT_ENA_R { + VADR_NUM_LT_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - an incomplete frame of data was sent interrupt enable."] + #[inline(always)] + pub fn discard_int_ena(&self) -> DISCARD_INT_ENA_R { + DISCARD_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - buffer overrun interrupt enable."] + #[inline(always)] + pub fn csi_buf_overrun_int_ena(&self) -> CSI_BUF_OVERRUN_INT_ENA_R { + CSI_BUF_OVERRUN_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - buffer overflow interrupt enable."] + #[inline(always)] + pub fn csi_async_fifo_ovf_int_ena(&self) -> CSI_ASYNC_FIFO_OVF_INT_ENA_R { + CSI_ASYNC_FIFO_OVF_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - dma configuration update complete interrupt enable."] + #[inline(always)] + pub fn dma_cfg_has_updated_int_ena(&self) -> DMA_CFG_HAS_UPDATED_INT_ENA_R { + DMA_CFG_HAS_UPDATED_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "vadr_num_gt_int_ena", + &format_args!("{}", self.vadr_num_gt_int_ena().bit()), + ) + .field( + "vadr_num_lt_int_ena", + &format_args!("{}", self.vadr_num_lt_int_ena().bit()), + ) + .field( + "discard_int_ena", + &format_args!("{}", self.discard_int_ena().bit()), + ) + .field( + "csi_buf_overrun_int_ena", + &format_args!("{}", self.csi_buf_overrun_int_ena().bit()), + ) + .field( + "csi_async_fifo_ovf_int_ena", + &format_args!("{}", self.csi_async_fifo_ovf_int_ena().bit()), + ) + .field( + "dma_cfg_has_updated_int_ena", + &format_args!("{}", self.dma_cfg_has_updated_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - reg_vadr_num is greater than real interrupt enable."] + #[inline(always)] + #[must_use] + pub fn vadr_num_gt_int_ena(&mut self) -> VADR_NUM_GT_INT_ENA_W { + VADR_NUM_GT_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - reg_vadr_num is less than real interrupt enable."] + #[inline(always)] + #[must_use] + pub fn vadr_num_lt_int_ena(&mut self) -> VADR_NUM_LT_INT_ENA_W { + VADR_NUM_LT_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - an incomplete frame of data was sent interrupt enable."] + #[inline(always)] + #[must_use] + pub fn discard_int_ena(&mut self) -> DISCARD_INT_ENA_W { + DISCARD_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - buffer overrun interrupt enable."] + #[inline(always)] + #[must_use] + pub fn csi_buf_overrun_int_ena(&mut self) -> CSI_BUF_OVERRUN_INT_ENA_W { + CSI_BUF_OVERRUN_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - buffer overflow interrupt enable."] + #[inline(always)] + #[must_use] + pub fn csi_async_fifo_ovf_int_ena(&mut self) -> CSI_ASYNC_FIFO_OVF_INT_ENA_W { + CSI_ASYNC_FIFO_OVF_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - dma configuration update complete interrupt enable."] + #[inline(always)] + #[must_use] + pub fn dma_cfg_has_updated_int_ena(&mut self) -> DMA_CFG_HAS_UPDATED_INT_ENA_W { + DMA_CFG_HAS_UPDATED_INT_ENA_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "csi bridge interrupt enable.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_bridge/int_raw.rs b/esp32p4/src/mipi_csi_bridge/int_raw.rs new file mode 100644 index 0000000000..af1e1e66fa --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/int_raw.rs @@ -0,0 +1,161 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `VADR_NUM_GT_INT_RAW` reader - reg_vadr_num is greater than real interrupt raw."] +pub type VADR_NUM_GT_INT_RAW_R = crate::BitReader; +#[doc = "Field `VADR_NUM_GT_INT_RAW` writer - reg_vadr_num is greater than real interrupt raw."] +pub type VADR_NUM_GT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VADR_NUM_LT_INT_RAW` reader - reg_vadr_num is less than real interrupt raw."] +pub type VADR_NUM_LT_INT_RAW_R = crate::BitReader; +#[doc = "Field `VADR_NUM_LT_INT_RAW` writer - reg_vadr_num is less than real interrupt raw."] +pub type VADR_NUM_LT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DISCARD_INT_RAW` reader - an incomplete frame of data was sent interrupt raw."] +pub type DISCARD_INT_RAW_R = crate::BitReader; +#[doc = "Field `DISCARD_INT_RAW` writer - an incomplete frame of data was sent interrupt raw."] +pub type DISCARD_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSI_BUF_OVERRUN_INT_RAW` reader - buffer overrun interrupt raw."] +pub type CSI_BUF_OVERRUN_INT_RAW_R = crate::BitReader; +#[doc = "Field `CSI_BUF_OVERRUN_INT_RAW` writer - buffer overrun interrupt raw."] +pub type CSI_BUF_OVERRUN_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSI_ASYNC_FIFO_OVF_INT_RAW` reader - buffer overflow interrupt raw."] +pub type CSI_ASYNC_FIFO_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `CSI_ASYNC_FIFO_OVF_INT_RAW` writer - buffer overflow interrupt raw."] +pub type CSI_ASYNC_FIFO_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_CFG_HAS_UPDATED_INT_RAW` reader - dma configuration update complete interrupt raw."] +pub type DMA_CFG_HAS_UPDATED_INT_RAW_R = crate::BitReader; +#[doc = "Field `DMA_CFG_HAS_UPDATED_INT_RAW` writer - dma configuration update complete interrupt raw."] +pub type DMA_CFG_HAS_UPDATED_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - reg_vadr_num is greater than real interrupt raw."] + #[inline(always)] + pub fn vadr_num_gt_int_raw(&self) -> VADR_NUM_GT_INT_RAW_R { + VADR_NUM_GT_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - reg_vadr_num is less than real interrupt raw."] + #[inline(always)] + pub fn vadr_num_lt_int_raw(&self) -> VADR_NUM_LT_INT_RAW_R { + VADR_NUM_LT_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - an incomplete frame of data was sent interrupt raw."] + #[inline(always)] + pub fn discard_int_raw(&self) -> DISCARD_INT_RAW_R { + DISCARD_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - buffer overrun interrupt raw."] + #[inline(always)] + pub fn csi_buf_overrun_int_raw(&self) -> CSI_BUF_OVERRUN_INT_RAW_R { + CSI_BUF_OVERRUN_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - buffer overflow interrupt raw."] + #[inline(always)] + pub fn csi_async_fifo_ovf_int_raw(&self) -> CSI_ASYNC_FIFO_OVF_INT_RAW_R { + CSI_ASYNC_FIFO_OVF_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - dma configuration update complete interrupt raw."] + #[inline(always)] + pub fn dma_cfg_has_updated_int_raw(&self) -> DMA_CFG_HAS_UPDATED_INT_RAW_R { + DMA_CFG_HAS_UPDATED_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "vadr_num_gt_int_raw", + &format_args!("{}", self.vadr_num_gt_int_raw().bit()), + ) + .field( + "vadr_num_lt_int_raw", + &format_args!("{}", self.vadr_num_lt_int_raw().bit()), + ) + .field( + "discard_int_raw", + &format_args!("{}", self.discard_int_raw().bit()), + ) + .field( + "csi_buf_overrun_int_raw", + &format_args!("{}", self.csi_buf_overrun_int_raw().bit()), + ) + .field( + "csi_async_fifo_ovf_int_raw", + &format_args!("{}", self.csi_async_fifo_ovf_int_raw().bit()), + ) + .field( + "dma_cfg_has_updated_int_raw", + &format_args!("{}", self.dma_cfg_has_updated_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - reg_vadr_num is greater than real interrupt raw."] + #[inline(always)] + #[must_use] + pub fn vadr_num_gt_int_raw(&mut self) -> VADR_NUM_GT_INT_RAW_W { + VADR_NUM_GT_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - reg_vadr_num is less than real interrupt raw."] + #[inline(always)] + #[must_use] + pub fn vadr_num_lt_int_raw(&mut self) -> VADR_NUM_LT_INT_RAW_W { + VADR_NUM_LT_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - an incomplete frame of data was sent interrupt raw."] + #[inline(always)] + #[must_use] + pub fn discard_int_raw(&mut self) -> DISCARD_INT_RAW_W { + DISCARD_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - buffer overrun interrupt raw."] + #[inline(always)] + #[must_use] + pub fn csi_buf_overrun_int_raw(&mut self) -> CSI_BUF_OVERRUN_INT_RAW_W { + CSI_BUF_OVERRUN_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - buffer overflow interrupt raw."] + #[inline(always)] + #[must_use] + pub fn csi_async_fifo_ovf_int_raw(&mut self) -> CSI_ASYNC_FIFO_OVF_INT_RAW_W { + CSI_ASYNC_FIFO_OVF_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - dma configuration update complete interrupt raw."] + #[inline(always)] + #[must_use] + pub fn dma_cfg_has_updated_int_raw(&mut self) -> DMA_CFG_HAS_UPDATED_INT_RAW_W { + DMA_CFG_HAS_UPDATED_INT_RAW_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "csi bridge interrupt raw.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_bridge/int_st.rs b/esp32p4/src/mipi_csi_bridge/int_st.rs new file mode 100644 index 0000000000..1fac743926 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/int_st.rs @@ -0,0 +1,94 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `VADR_NUM_GT_INT_ST` reader - reg_vadr_num is greater than real interrupt st."] +pub type VADR_NUM_GT_INT_ST_R = crate::BitReader; +#[doc = "Field `VADR_NUM_LT_INT_ST` reader - reg_vadr_num is less than real interrupt st."] +pub type VADR_NUM_LT_INT_ST_R = crate::BitReader; +#[doc = "Field `DISCARD_INT_ST` reader - an incomplete frame of data was sent interrupt st."] +pub type DISCARD_INT_ST_R = crate::BitReader; +#[doc = "Field `CSI_BUF_OVERRUN_INT_ST` reader - buffer overrun interrupt st."] +pub type CSI_BUF_OVERRUN_INT_ST_R = crate::BitReader; +#[doc = "Field `CSI_ASYNC_FIFO_OVF_INT_ST` reader - buffer overflow interrupt st."] +pub type CSI_ASYNC_FIFO_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `DMA_CFG_HAS_UPDATED_INT_ST` reader - dma configuration update complete interrupt st."] +pub type DMA_CFG_HAS_UPDATED_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - reg_vadr_num is greater than real interrupt st."] + #[inline(always)] + pub fn vadr_num_gt_int_st(&self) -> VADR_NUM_GT_INT_ST_R { + VADR_NUM_GT_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - reg_vadr_num is less than real interrupt st."] + #[inline(always)] + pub fn vadr_num_lt_int_st(&self) -> VADR_NUM_LT_INT_ST_R { + VADR_NUM_LT_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - an incomplete frame of data was sent interrupt st."] + #[inline(always)] + pub fn discard_int_st(&self) -> DISCARD_INT_ST_R { + DISCARD_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - buffer overrun interrupt st."] + #[inline(always)] + pub fn csi_buf_overrun_int_st(&self) -> CSI_BUF_OVERRUN_INT_ST_R { + CSI_BUF_OVERRUN_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - buffer overflow interrupt st."] + #[inline(always)] + pub fn csi_async_fifo_ovf_int_st(&self) -> CSI_ASYNC_FIFO_OVF_INT_ST_R { + CSI_ASYNC_FIFO_OVF_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - dma configuration update complete interrupt st."] + #[inline(always)] + pub fn dma_cfg_has_updated_int_st(&self) -> DMA_CFG_HAS_UPDATED_INT_ST_R { + DMA_CFG_HAS_UPDATED_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "vadr_num_gt_int_st", + &format_args!("{}", self.vadr_num_gt_int_st().bit()), + ) + .field( + "vadr_num_lt_int_st", + &format_args!("{}", self.vadr_num_lt_int_st().bit()), + ) + .field( + "discard_int_st", + &format_args!("{}", self.discard_int_st().bit()), + ) + .field( + "csi_buf_overrun_int_st", + &format_args!("{}", self.csi_buf_overrun_int_st().bit()), + ) + .field( + "csi_async_fifo_ovf_int_st", + &format_args!("{}", self.csi_async_fifo_ovf_int_st().bit()), + ) + .field( + "dma_cfg_has_updated_int_st", + &format_args!("{}", self.dma_cfg_has_updated_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "csi bridge interrupt st.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_bridge/mem_ctrl.rs b/esp32p4/src/mipi_csi_bridge/mem_ctrl.rs new file mode 100644 index 0000000000..b602846498 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/mem_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `MEM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CSI_BRIDGE_MEM_CLK_FORCE_ON` reader - csi bridge memory clock gating force on."] +pub type CSI_BRIDGE_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `CSI_BRIDGE_MEM_CLK_FORCE_ON` writer - csi bridge memory clock gating force on."] +pub type CSI_BRIDGE_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSI_MEM_AUX_CTRL` reader - N/A"] +pub type CSI_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `CSI_MEM_AUX_CTRL` writer - N/A"] +pub type CSI_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bit 0 - csi bridge memory clock gating force on."] + #[inline(always)] + pub fn csi_bridge_mem_clk_force_on(&self) -> CSI_BRIDGE_MEM_CLK_FORCE_ON_R { + CSI_BRIDGE_MEM_CLK_FORCE_ON_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:14 - N/A"] + #[inline(always)] + pub fn csi_mem_aux_ctrl(&self) -> CSI_MEM_AUX_CTRL_R { + CSI_MEM_AUX_CTRL_R::new(((self.bits >> 1) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_CTRL") + .field( + "csi_bridge_mem_clk_force_on", + &format_args!("{}", self.csi_bridge_mem_clk_force_on().bit()), + ) + .field( + "csi_mem_aux_ctrl", + &format_args!("{}", self.csi_mem_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - csi bridge memory clock gating force on."] + #[inline(always)] + #[must_use] + pub fn csi_bridge_mem_clk_force_on(&mut self) -> CSI_BRIDGE_MEM_CLK_FORCE_ON_W { + CSI_BRIDGE_MEM_CLK_FORCE_ON_W::new(self, 0) + } + #[doc = "Bits 1:14 - N/A"] + #[inline(always)] + #[must_use] + pub fn csi_mem_aux_ctrl(&mut self) -> CSI_MEM_AUX_CTRL_W { + CSI_MEM_AUX_CTRL_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "csi bridge buffer control.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_CTRL_SPEC; +impl crate::RegisterSpec for MEM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_ctrl::R`](R) reader structure"] +impl crate::Readable for MEM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_ctrl::W`](W) writer structure"] +impl crate::Writable for MEM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_CTRL to value 0x2640"] +impl crate::Resettable for MEM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x2640; +} diff --git a/esp32p4/src/mipi_csi_bridge/rdn_eco_cs.rs b/esp32p4/src/mipi_csi_bridge/rdn_eco_cs.rs new file mode 100644 index 0000000000..3ffd83c956 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/rdn_eco_cs.rs @@ -0,0 +1,74 @@ +#[doc = "Register `RDN_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_EN` reader - N/A"] +pub type RDN_ECO_EN_R = crate::BitReader; +#[doc = "Field `RDN_ECO_EN` writer - N/A"] +pub type RDN_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RDN_ECO_RESULT` reader - N/A"] +pub type RDN_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + pub fn rdn_eco_en(&self) -> RDN_ECO_EN_R { + RDN_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - N/A"] + #[inline(always)] + pub fn rdn_eco_result(&self) -> RDN_ECO_RESULT_R { + RDN_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_CS") + .field("rdn_eco_en", &format_args!("{}", self.rdn_eco_en().bit())) + .field( + "rdn_eco_result", + &format_args!("{}", self.rdn_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - N/A"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_en(&mut self) -> RDN_ECO_EN_W { + RDN_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_CS_SPEC; +impl crate::RegisterSpec for RDN_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_cs::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_cs::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_CS to value 0"] +impl crate::Resettable for RDN_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_bridge/rdn_eco_high.rs b/esp32p4/src/mipi_csi_bridge/rdn_eco_high.rs new file mode 100644 index 0000000000..6865d9ec71 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/rdn_eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RDN_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_HIGH` reader - N/A"] +pub type RDN_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_HIGH` writer - N/A"] +pub type RDN_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + pub fn rdn_eco_high(&self) -> RDN_ECO_HIGH_R { + RDN_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_HIGH") + .field( + "rdn_eco_high", + &format_args!("{}", self.rdn_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_high(&mut self) -> RDN_ECO_HIGH_W { + RDN_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_HIGH_SPEC; +impl crate::RegisterSpec for RDN_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_high::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_high::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for RDN_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/mipi_csi_bridge/rdn_eco_low.rs b/esp32p4/src/mipi_csi_bridge/rdn_eco_low.rs new file mode 100644 index 0000000000..c15a498116 --- /dev/null +++ b/esp32p4/src/mipi_csi_bridge/rdn_eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RDN_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_LOW` reader - N/A"] +pub type RDN_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_LOW` writer - N/A"] +pub type RDN_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + pub fn rdn_eco_low(&self) -> RDN_ECO_LOW_R { + RDN_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_LOW") + .field( + "rdn_eco_low", + &format_args!("{}", self.rdn_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - N/A"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_low(&mut self) -> RDN_ECO_LOW_W { + RDN_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_LOW_SPEC; +impl crate::RegisterSpec for RDN_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_low::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_low::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_LOW to value 0"] +impl crate::Resettable for RDN_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host.rs b/esp32p4/src/mipi_csi_host.rs new file mode 100644 index 0000000000..ba1898359a --- /dev/null +++ b/esp32p4/src/mipi_csi_host.rs @@ -0,0 +1,448 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + version: VERSION, + n_lanes: N_LANES, + csi2_resetn: CSI2_RESETN, + int_st_main: INT_ST_MAIN, + _reserved4: [u8; 0x30], + phy_shutdownz: PHY_SHUTDOWNZ, + dphy_rstz: DPHY_RSTZ, + phy_rx: PHY_RX, + phy_stopstate: PHY_STOPSTATE, + phy_test_ctrl0: PHY_TEST_CTRL0, + phy_test_ctrl1: PHY_TEST_CTRL1, + _reserved10: [u8; 0x70], + vc_extension: VC_EXTENSION, + phy_cal: PHY_CAL, + _reserved12: [u8; 0x10], + int_st_phy_fatal: INT_ST_PHY_FATAL, + int_msk_phy_fatal: INT_MSK_PHY_FATAL, + int_force_phy_fatal: INT_FORCE_PHY_FATAL, + _reserved15: [u8; 0x04], + int_st_pkt_fatal: INT_ST_PKT_FATAL, + int_msk_pkt_fatal: INT_MSK_PKT_FATAL, + int_force_pkt_fatal: INT_FORCE_PKT_FATAL, + _reserved18: [u8; 0x14], + int_st_phy: INT_ST_PHY, + int_msk_phy: INT_MSK_PHY, + int_force_phy: INT_FORCE_PHY, + _reserved21: [u8; 0x0164], + int_st_bndry_frame_fatal: INT_ST_BNDRY_FRAME_FATAL, + int_msk_bndry_frame_fatal: INT_MSK_BNDRY_FRAME_FATAL, + int_force_bndry_frame_fatal: INT_FORCE_BNDRY_FRAME_FATAL, + _reserved24: [u8; 0x04], + int_st_seq_frame_fatal: INT_ST_SEQ_FRAME_FATAL, + int_msk_seq_frame_fatal: INT_MSK_SEQ_FRAME_FATAL, + int_force_seq_frame_fatal: INT_FORCE_SEQ_FRAME_FATAL, + _reserved27: [u8; 0x04], + int_st_crc_frame_fatal: INT_ST_CRC_FRAME_FATAL, + int_msk_crc_frame_fatal: INT_MSK_CRC_FRAME_FATAL, + int_force_crc_frame_fatal: INT_FORCE_CRC_FRAME_FATAL, + _reserved30: [u8; 0x04], + int_st_pld_crc_fatal: INT_ST_PLD_CRC_FATAL, + int_msk_pld_crc_fatal: INT_MSK_PLD_CRC_FATAL, + int_force_pld_crc_fatal: INT_FORCE_PLD_CRC_FATAL, + _reserved33: [u8; 0x04], + int_st_data_id: INT_ST_DATA_ID, + int_msk_data_id: INT_MSK_DATA_ID, + int_force_data_id: INT_FORCE_DATA_ID, + _reserved36: [u8; 0x04], + int_st_ecc_corrected: INT_ST_ECC_CORRECTED, + int_msk_ecc_corrected: INT_MSK_ECC_CORRECTED, + int_force_ecc_corrected: INT_FORCE_ECC_CORRECTED, + _reserved39: [u8; 0x24], + scrambling: SCRAMBLING, + scrambling_seed1: SCRAMBLING_SEED1, + scrambling_seed2: SCRAMBLING_SEED2, +} +impl RegisterBlock { + #[doc = "0x00 - NA"] + #[inline(always)] + pub const fn version(&self) -> &VERSION { + &self.version + } + #[doc = "0x04 - NA"] + #[inline(always)] + pub const fn n_lanes(&self) -> &N_LANES { + &self.n_lanes + } + #[doc = "0x08 - NA"] + #[inline(always)] + pub const fn csi2_resetn(&self) -> &CSI2_RESETN { + &self.csi2_resetn + } + #[doc = "0x0c - NA"] + #[inline(always)] + pub const fn int_st_main(&self) -> &INT_ST_MAIN { + &self.int_st_main + } + #[doc = "0x40 - NA"] + #[inline(always)] + pub const fn phy_shutdownz(&self) -> &PHY_SHUTDOWNZ { + &self.phy_shutdownz + } + #[doc = "0x44 - NA"] + #[inline(always)] + pub const fn dphy_rstz(&self) -> &DPHY_RSTZ { + &self.dphy_rstz + } + #[doc = "0x48 - NA"] + #[inline(always)] + pub const fn phy_rx(&self) -> &PHY_RX { + &self.phy_rx + } + #[doc = "0x4c - NA"] + #[inline(always)] + pub const fn phy_stopstate(&self) -> &PHY_STOPSTATE { + &self.phy_stopstate + } + #[doc = "0x50 - NA"] + #[inline(always)] + pub const fn phy_test_ctrl0(&self) -> &PHY_TEST_CTRL0 { + &self.phy_test_ctrl0 + } + #[doc = "0x54 - NA"] + #[inline(always)] + pub const fn phy_test_ctrl1(&self) -> &PHY_TEST_CTRL1 { + &self.phy_test_ctrl1 + } + #[doc = "0xc8 - NA"] + #[inline(always)] + pub const fn vc_extension(&self) -> &VC_EXTENSION { + &self.vc_extension + } + #[doc = "0xcc - NA"] + #[inline(always)] + pub const fn phy_cal(&self) -> &PHY_CAL { + &self.phy_cal + } + #[doc = "0xe0 - NA"] + #[inline(always)] + pub const fn int_st_phy_fatal(&self) -> &INT_ST_PHY_FATAL { + &self.int_st_phy_fatal + } + #[doc = "0xe4 - NA"] + #[inline(always)] + pub const fn int_msk_phy_fatal(&self) -> &INT_MSK_PHY_FATAL { + &self.int_msk_phy_fatal + } + #[doc = "0xe8 - NA"] + #[inline(always)] + pub const fn int_force_phy_fatal(&self) -> &INT_FORCE_PHY_FATAL { + &self.int_force_phy_fatal + } + #[doc = "0xf0 - NA"] + #[inline(always)] + pub const fn int_st_pkt_fatal(&self) -> &INT_ST_PKT_FATAL { + &self.int_st_pkt_fatal + } + #[doc = "0xf4 - NA"] + #[inline(always)] + pub const fn int_msk_pkt_fatal(&self) -> &INT_MSK_PKT_FATAL { + &self.int_msk_pkt_fatal + } + #[doc = "0xf8 - NA"] + #[inline(always)] + pub const fn int_force_pkt_fatal(&self) -> &INT_FORCE_PKT_FATAL { + &self.int_force_pkt_fatal + } + #[doc = "0x110 - NA"] + #[inline(always)] + pub const fn int_st_phy(&self) -> &INT_ST_PHY { + &self.int_st_phy + } + #[doc = "0x114 - NA"] + #[inline(always)] + pub const fn int_msk_phy(&self) -> &INT_MSK_PHY { + &self.int_msk_phy + } + #[doc = "0x118 - NA"] + #[inline(always)] + pub const fn int_force_phy(&self) -> &INT_FORCE_PHY { + &self.int_force_phy + } + #[doc = "0x280 - NA"] + #[inline(always)] + pub const fn int_st_bndry_frame_fatal(&self) -> &INT_ST_BNDRY_FRAME_FATAL { + &self.int_st_bndry_frame_fatal + } + #[doc = "0x284 - NA"] + #[inline(always)] + pub const fn int_msk_bndry_frame_fatal(&self) -> &INT_MSK_BNDRY_FRAME_FATAL { + &self.int_msk_bndry_frame_fatal + } + #[doc = "0x288 - NA"] + #[inline(always)] + pub const fn int_force_bndry_frame_fatal(&self) -> &INT_FORCE_BNDRY_FRAME_FATAL { + &self.int_force_bndry_frame_fatal + } + #[doc = "0x290 - NA"] + #[inline(always)] + pub const fn int_st_seq_frame_fatal(&self) -> &INT_ST_SEQ_FRAME_FATAL { + &self.int_st_seq_frame_fatal + } + #[doc = "0x294 - NA"] + #[inline(always)] + pub const fn int_msk_seq_frame_fatal(&self) -> &INT_MSK_SEQ_FRAME_FATAL { + &self.int_msk_seq_frame_fatal + } + #[doc = "0x298 - NA"] + #[inline(always)] + pub const fn int_force_seq_frame_fatal(&self) -> &INT_FORCE_SEQ_FRAME_FATAL { + &self.int_force_seq_frame_fatal + } + #[doc = "0x2a0 - NA"] + #[inline(always)] + pub const fn int_st_crc_frame_fatal(&self) -> &INT_ST_CRC_FRAME_FATAL { + &self.int_st_crc_frame_fatal + } + #[doc = "0x2a4 - NA"] + #[inline(always)] + pub const fn int_msk_crc_frame_fatal(&self) -> &INT_MSK_CRC_FRAME_FATAL { + &self.int_msk_crc_frame_fatal + } + #[doc = "0x2a8 - NA"] + #[inline(always)] + pub const fn int_force_crc_frame_fatal(&self) -> &INT_FORCE_CRC_FRAME_FATAL { + &self.int_force_crc_frame_fatal + } + #[doc = "0x2b0 - NA"] + #[inline(always)] + pub const fn int_st_pld_crc_fatal(&self) -> &INT_ST_PLD_CRC_FATAL { + &self.int_st_pld_crc_fatal + } + #[doc = "0x2b4 - NA"] + #[inline(always)] + pub const fn int_msk_pld_crc_fatal(&self) -> &INT_MSK_PLD_CRC_FATAL { + &self.int_msk_pld_crc_fatal + } + #[doc = "0x2b8 - NA"] + #[inline(always)] + pub const fn int_force_pld_crc_fatal(&self) -> &INT_FORCE_PLD_CRC_FATAL { + &self.int_force_pld_crc_fatal + } + #[doc = "0x2c0 - NA"] + #[inline(always)] + pub const fn int_st_data_id(&self) -> &INT_ST_DATA_ID { + &self.int_st_data_id + } + #[doc = "0x2c4 - NA"] + #[inline(always)] + pub const fn int_msk_data_id(&self) -> &INT_MSK_DATA_ID { + &self.int_msk_data_id + } + #[doc = "0x2c8 - NA"] + #[inline(always)] + pub const fn int_force_data_id(&self) -> &INT_FORCE_DATA_ID { + &self.int_force_data_id + } + #[doc = "0x2d0 - NA"] + #[inline(always)] + pub const fn int_st_ecc_corrected(&self) -> &INT_ST_ECC_CORRECTED { + &self.int_st_ecc_corrected + } + #[doc = "0x2d4 - NA"] + #[inline(always)] + pub const fn int_msk_ecc_corrected(&self) -> &INT_MSK_ECC_CORRECTED { + &self.int_msk_ecc_corrected + } + #[doc = "0x2d8 - NA"] + #[inline(always)] + pub const fn int_force_ecc_corrected(&self) -> &INT_FORCE_ECC_CORRECTED { + &self.int_force_ecc_corrected + } + #[doc = "0x300 - NA"] + #[inline(always)] + pub const fn scrambling(&self) -> &SCRAMBLING { + &self.scrambling + } + #[doc = "0x304 - NA"] + #[inline(always)] + pub const fn scrambling_seed1(&self) -> &SCRAMBLING_SEED1 { + &self.scrambling_seed1 + } + #[doc = "0x308 - NA"] + #[inline(always)] + pub const fn scrambling_seed2(&self) -> &SCRAMBLING_SEED2 { + &self.scrambling_seed2 + } +} +#[doc = "VERSION (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"] +pub type VERSION = crate::Reg; +#[doc = "NA"] +pub mod version; +#[doc = "N_LANES (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`n_lanes::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`n_lanes::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@n_lanes`] module"] +pub type N_LANES = crate::Reg; +#[doc = "NA"] +pub mod n_lanes; +#[doc = "CSI2_RESETN (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi2_resetn::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi2_resetn::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csi2_resetn`] module"] +pub type CSI2_RESETN = crate::Reg; +#[doc = "NA"] +pub mod csi2_resetn; +#[doc = "INT_ST_MAIN (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_main::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_main`] module"] +pub type INT_ST_MAIN = crate::Reg; +#[doc = "NA"] +pub mod int_st_main; +#[doc = "PHY_SHUTDOWNZ (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_shutdownz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_shutdownz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_shutdownz`] module"] +pub type PHY_SHUTDOWNZ = crate::Reg; +#[doc = "NA"] +pub mod phy_shutdownz; +#[doc = "DPHY_RSTZ (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dphy_rstz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dphy_rstz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dphy_rstz`] module"] +pub type DPHY_RSTZ = crate::Reg; +#[doc = "NA"] +pub mod dphy_rstz; +#[doc = "PHY_RX (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_rx::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_rx`] module"] +pub type PHY_RX = crate::Reg; +#[doc = "NA"] +pub mod phy_rx; +#[doc = "PHY_STOPSTATE (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_stopstate::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_stopstate`] module"] +pub type PHY_STOPSTATE = crate::Reg; +#[doc = "NA"] +pub mod phy_stopstate; +#[doc = "PHY_TEST_CTRL0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_test_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_test_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_test_ctrl0`] module"] +pub type PHY_TEST_CTRL0 = crate::Reg; +#[doc = "NA"] +pub mod phy_test_ctrl0; +#[doc = "PHY_TEST_CTRL1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_test_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_test_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_test_ctrl1`] module"] +pub type PHY_TEST_CTRL1 = crate::Reg; +#[doc = "NA"] +pub mod phy_test_ctrl1; +#[doc = "VC_EXTENSION (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vc_extension::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vc_extension::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vc_extension`] module"] +pub type VC_EXTENSION = crate::Reg; +#[doc = "NA"] +pub mod vc_extension; +#[doc = "PHY_CAL (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_cal`] module"] +pub type PHY_CAL = crate::Reg; +#[doc = "NA"] +pub mod phy_cal; +#[doc = "INT_ST_PHY_FATAL (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_phy_fatal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_phy_fatal`] module"] +pub type INT_ST_PHY_FATAL = crate::Reg; +#[doc = "NA"] +pub mod int_st_phy_fatal; +#[doc = "INT_MSK_PHY_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_phy_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_phy_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk_phy_fatal`] module"] +pub type INT_MSK_PHY_FATAL = crate::Reg; +#[doc = "NA"] +pub mod int_msk_phy_fatal; +#[doc = "INT_FORCE_PHY_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_phy_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_phy_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_force_phy_fatal`] module"] +pub type INT_FORCE_PHY_FATAL = crate::Reg; +#[doc = "NA"] +pub mod int_force_phy_fatal; +#[doc = "INT_ST_PKT_FATAL (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_pkt_fatal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_pkt_fatal`] module"] +pub type INT_ST_PKT_FATAL = crate::Reg; +#[doc = "NA"] +pub mod int_st_pkt_fatal; +#[doc = "INT_MSK_PKT_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_pkt_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_pkt_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk_pkt_fatal`] module"] +pub type INT_MSK_PKT_FATAL = crate::Reg; +#[doc = "NA"] +pub mod int_msk_pkt_fatal; +#[doc = "INT_FORCE_PKT_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_pkt_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_pkt_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_force_pkt_fatal`] module"] +pub type INT_FORCE_PKT_FATAL = crate::Reg; +#[doc = "NA"] +pub mod int_force_pkt_fatal; +#[doc = "INT_ST_PHY (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_phy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_phy`] module"] +pub type INT_ST_PHY = crate::Reg; +#[doc = "NA"] +pub mod int_st_phy; +#[doc = "INT_MSK_PHY (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_phy::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_phy::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk_phy`] module"] +pub type INT_MSK_PHY = crate::Reg; +#[doc = "NA"] +pub mod int_msk_phy; +#[doc = "INT_FORCE_PHY (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_phy::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_phy::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_force_phy`] module"] +pub type INT_FORCE_PHY = crate::Reg; +#[doc = "NA"] +pub mod int_force_phy; +#[doc = "INT_ST_BNDRY_FRAME_FATAL (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_bndry_frame_fatal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_bndry_frame_fatal`] module"] +pub type INT_ST_BNDRY_FRAME_FATAL = + crate::Reg; +#[doc = "NA"] +pub mod int_st_bndry_frame_fatal; +#[doc = "INT_MSK_BNDRY_FRAME_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_bndry_frame_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_bndry_frame_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk_bndry_frame_fatal`] module"] +pub type INT_MSK_BNDRY_FRAME_FATAL = + crate::Reg; +#[doc = "NA"] +pub mod int_msk_bndry_frame_fatal; +#[doc = "INT_FORCE_BNDRY_FRAME_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_bndry_frame_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_bndry_frame_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_force_bndry_frame_fatal`] module"] +pub type INT_FORCE_BNDRY_FRAME_FATAL = + crate::Reg; +#[doc = "NA"] +pub mod int_force_bndry_frame_fatal; +#[doc = "INT_ST_SEQ_FRAME_FATAL (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_seq_frame_fatal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_seq_frame_fatal`] module"] +pub type INT_ST_SEQ_FRAME_FATAL = crate::Reg; +#[doc = "NA"] +pub mod int_st_seq_frame_fatal; +#[doc = "INT_MSK_SEQ_FRAME_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_seq_frame_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_seq_frame_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk_seq_frame_fatal`] module"] +pub type INT_MSK_SEQ_FRAME_FATAL = + crate::Reg; +#[doc = "NA"] +pub mod int_msk_seq_frame_fatal; +#[doc = "INT_FORCE_SEQ_FRAME_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_seq_frame_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_seq_frame_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_force_seq_frame_fatal`] module"] +pub type INT_FORCE_SEQ_FRAME_FATAL = + crate::Reg; +#[doc = "NA"] +pub mod int_force_seq_frame_fatal; +#[doc = "INT_ST_CRC_FRAME_FATAL (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_crc_frame_fatal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_crc_frame_fatal`] module"] +pub type INT_ST_CRC_FRAME_FATAL = crate::Reg; +#[doc = "NA"] +pub mod int_st_crc_frame_fatal; +#[doc = "INT_MSK_CRC_FRAME_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_crc_frame_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_crc_frame_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk_crc_frame_fatal`] module"] +pub type INT_MSK_CRC_FRAME_FATAL = + crate::Reg; +#[doc = "NA"] +pub mod int_msk_crc_frame_fatal; +#[doc = "INT_FORCE_CRC_FRAME_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_crc_frame_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_crc_frame_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_force_crc_frame_fatal`] module"] +pub type INT_FORCE_CRC_FRAME_FATAL = + crate::Reg; +#[doc = "NA"] +pub mod int_force_crc_frame_fatal; +#[doc = "INT_ST_PLD_CRC_FATAL (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_pld_crc_fatal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_pld_crc_fatal`] module"] +pub type INT_ST_PLD_CRC_FATAL = crate::Reg; +#[doc = "NA"] +pub mod int_st_pld_crc_fatal; +#[doc = "INT_MSK_PLD_CRC_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_pld_crc_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_pld_crc_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk_pld_crc_fatal`] module"] +pub type INT_MSK_PLD_CRC_FATAL = crate::Reg; +#[doc = "NA"] +pub mod int_msk_pld_crc_fatal; +#[doc = "INT_FORCE_PLD_CRC_FATAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_pld_crc_fatal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_pld_crc_fatal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_force_pld_crc_fatal`] module"] +pub type INT_FORCE_PLD_CRC_FATAL = + crate::Reg; +#[doc = "NA"] +pub mod int_force_pld_crc_fatal; +#[doc = "INT_ST_DATA_ID (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_data_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_data_id`] module"] +pub type INT_ST_DATA_ID = crate::Reg; +#[doc = "NA"] +pub mod int_st_data_id; +#[doc = "INT_MSK_DATA_ID (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_data_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_data_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk_data_id`] module"] +pub type INT_MSK_DATA_ID = crate::Reg; +#[doc = "NA"] +pub mod int_msk_data_id; +#[doc = "INT_FORCE_DATA_ID (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_data_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_data_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_force_data_id`] module"] +pub type INT_FORCE_DATA_ID = crate::Reg; +#[doc = "NA"] +pub mod int_force_data_id; +#[doc = "INT_ST_ECC_CORRECTED (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_ecc_corrected::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_ecc_corrected`] module"] +pub type INT_ST_ECC_CORRECTED = crate::Reg; +#[doc = "NA"] +pub mod int_st_ecc_corrected; +#[doc = "INT_MSK_ECC_CORRECTED (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_ecc_corrected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_ecc_corrected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk_ecc_corrected`] module"] +pub type INT_MSK_ECC_CORRECTED = crate::Reg; +#[doc = "NA"] +pub mod int_msk_ecc_corrected; +#[doc = "INT_FORCE_ECC_CORRECTED (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_ecc_corrected::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_ecc_corrected::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_force_ecc_corrected`] module"] +pub type INT_FORCE_ECC_CORRECTED = + crate::Reg; +#[doc = "NA"] +pub mod int_force_ecc_corrected; +#[doc = "SCRAMBLING (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scrambling::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scrambling::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scrambling`] module"] +pub type SCRAMBLING = crate::Reg; +#[doc = "NA"] +pub mod scrambling; +#[doc = "SCRAMBLING_SEED1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scrambling_seed1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scrambling_seed1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scrambling_seed1`] module"] +pub type SCRAMBLING_SEED1 = crate::Reg; +#[doc = "NA"] +pub mod scrambling_seed1; +#[doc = "SCRAMBLING_SEED2 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scrambling_seed2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scrambling_seed2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scrambling_seed2`] module"] +pub type SCRAMBLING_SEED2 = crate::Reg; +#[doc = "NA"] +pub mod scrambling_seed2; diff --git a/esp32p4/src/mipi_csi_host/csi2_resetn.rs b/esp32p4/src/mipi_csi_host/csi2_resetn.rs new file mode 100644 index 0000000000..c314f7ebf4 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/csi2_resetn.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CSI2_RESETN` reader"] +pub type R = crate::R; +#[doc = "Register `CSI2_RESETN` writer"] +pub type W = crate::W; +#[doc = "Field `CSI2_RESETN` reader - NA"] +pub type CSI2_RESETN_R = crate::BitReader; +#[doc = "Field `CSI2_RESETN` writer - NA"] +pub type CSI2_RESETN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn csi2_resetn(&self) -> CSI2_RESETN_R { + CSI2_RESETN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CSI2_RESETN") + .field("csi2_resetn", &format_args!("{}", self.csi2_resetn().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn csi2_resetn(&mut self) -> CSI2_RESETN_W { + CSI2_RESETN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi2_resetn::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi2_resetn::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CSI2_RESETN_SPEC; +impl crate::RegisterSpec for CSI2_RESETN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`csi2_resetn::R`](R) reader structure"] +impl crate::Readable for CSI2_RESETN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csi2_resetn::W`](W) writer structure"] +impl crate::Writable for CSI2_RESETN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CSI2_RESETN to value 0"] +impl crate::Resettable for CSI2_RESETN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/dphy_rstz.rs b/esp32p4/src/mipi_csi_host/dphy_rstz.rs new file mode 100644 index 0000000000..588ab6f396 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/dphy_rstz.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DPHY_RSTZ` reader"] +pub type R = crate::R; +#[doc = "Register `DPHY_RSTZ` writer"] +pub type W = crate::W; +#[doc = "Field `DPHY_RSTZ` reader - NA"] +pub type DPHY_RSTZ_R = crate::BitReader; +#[doc = "Field `DPHY_RSTZ` writer - NA"] +pub type DPHY_RSTZ_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn dphy_rstz(&self) -> DPHY_RSTZ_R { + DPHY_RSTZ_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPHY_RSTZ") + .field("dphy_rstz", &format_args!("{}", self.dphy_rstz().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn dphy_rstz(&mut self) -> DPHY_RSTZ_W { + DPHY_RSTZ_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dphy_rstz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dphy_rstz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPHY_RSTZ_SPEC; +impl crate::RegisterSpec for DPHY_RSTZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dphy_rstz::R`](R) reader structure"] +impl crate::Readable for DPHY_RSTZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dphy_rstz::W`](W) writer structure"] +impl crate::Writable for DPHY_RSTZ_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPHY_RSTZ to value 0"] +impl crate::Resettable for DPHY_RSTZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_force_bndry_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_bndry_frame_fatal.rs new file mode 100644 index 0000000000..22e1b1714c --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_force_bndry_frame_fatal.rs @@ -0,0 +1,383 @@ +#[doc = "Register `INT_FORCE_BNDRY_FRAME_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_FORCE_BNDRY_FRAME_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC0` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC0_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC0` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC1` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC1_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC1` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC2` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC2_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC2` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC3` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC3_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC3` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC4` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC4_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC4` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC5` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC5_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC5` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC6` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC6_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC6` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC7` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC7_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC7` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC8` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC8_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC8` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC9` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC9_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC9` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC10` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC10_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC10` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC11` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC11_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC11` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC12` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC12_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC12` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC13` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC13_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC13` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC14` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC14_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC14` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC15` reader - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC15_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_BNDRY_MATCH_VC15` writer - NA"] +pub type FORCE_ERR_F_BNDRY_MATCH_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc0(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC0_R { + FORCE_ERR_F_BNDRY_MATCH_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc1(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC1_R { + FORCE_ERR_F_BNDRY_MATCH_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc2(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC2_R { + FORCE_ERR_F_BNDRY_MATCH_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc3(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC3_R { + FORCE_ERR_F_BNDRY_MATCH_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc4(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC4_R { + FORCE_ERR_F_BNDRY_MATCH_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc5(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC5_R { + FORCE_ERR_F_BNDRY_MATCH_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc6(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC6_R { + FORCE_ERR_F_BNDRY_MATCH_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc7(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC7_R { + FORCE_ERR_F_BNDRY_MATCH_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc8(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC8_R { + FORCE_ERR_F_BNDRY_MATCH_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc9(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC9_R { + FORCE_ERR_F_BNDRY_MATCH_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc10(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC10_R { + FORCE_ERR_F_BNDRY_MATCH_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc11(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC11_R { + FORCE_ERR_F_BNDRY_MATCH_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc12(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC12_R { + FORCE_ERR_F_BNDRY_MATCH_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc13(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC13_R { + FORCE_ERR_F_BNDRY_MATCH_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc14(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC14_R { + FORCE_ERR_F_BNDRY_MATCH_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn force_err_f_bndry_match_vc15(&self) -> FORCE_ERR_F_BNDRY_MATCH_VC15_R { + FORCE_ERR_F_BNDRY_MATCH_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_FORCE_BNDRY_FRAME_FATAL") + .field( + "force_err_f_bndry_match_vc0", + &format_args!("{}", self.force_err_f_bndry_match_vc0().bit()), + ) + .field( + "force_err_f_bndry_match_vc1", + &format_args!("{}", self.force_err_f_bndry_match_vc1().bit()), + ) + .field( + "force_err_f_bndry_match_vc2", + &format_args!("{}", self.force_err_f_bndry_match_vc2().bit()), + ) + .field( + "force_err_f_bndry_match_vc3", + &format_args!("{}", self.force_err_f_bndry_match_vc3().bit()), + ) + .field( + "force_err_f_bndry_match_vc4", + &format_args!("{}", self.force_err_f_bndry_match_vc4().bit()), + ) + .field( + "force_err_f_bndry_match_vc5", + &format_args!("{}", self.force_err_f_bndry_match_vc5().bit()), + ) + .field( + "force_err_f_bndry_match_vc6", + &format_args!("{}", self.force_err_f_bndry_match_vc6().bit()), + ) + .field( + "force_err_f_bndry_match_vc7", + &format_args!("{}", self.force_err_f_bndry_match_vc7().bit()), + ) + .field( + "force_err_f_bndry_match_vc8", + &format_args!("{}", self.force_err_f_bndry_match_vc8().bit()), + ) + .field( + "force_err_f_bndry_match_vc9", + &format_args!("{}", self.force_err_f_bndry_match_vc9().bit()), + ) + .field( + "force_err_f_bndry_match_vc10", + &format_args!("{}", self.force_err_f_bndry_match_vc10().bit()), + ) + .field( + "force_err_f_bndry_match_vc11", + &format_args!("{}", self.force_err_f_bndry_match_vc11().bit()), + ) + .field( + "force_err_f_bndry_match_vc12", + &format_args!("{}", self.force_err_f_bndry_match_vc12().bit()), + ) + .field( + "force_err_f_bndry_match_vc13", + &format_args!("{}", self.force_err_f_bndry_match_vc13().bit()), + ) + .field( + "force_err_f_bndry_match_vc14", + &format_args!("{}", self.force_err_f_bndry_match_vc14().bit()), + ) + .field( + "force_err_f_bndry_match_vc15", + &format_args!("{}", self.force_err_f_bndry_match_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc0( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC0_W { + FORCE_ERR_F_BNDRY_MATCH_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc1( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC1_W { + FORCE_ERR_F_BNDRY_MATCH_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc2( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC2_W { + FORCE_ERR_F_BNDRY_MATCH_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc3( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC3_W { + FORCE_ERR_F_BNDRY_MATCH_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc4( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC4_W { + FORCE_ERR_F_BNDRY_MATCH_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc5( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC5_W { + FORCE_ERR_F_BNDRY_MATCH_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc6( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC6_W { + FORCE_ERR_F_BNDRY_MATCH_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc7( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC7_W { + FORCE_ERR_F_BNDRY_MATCH_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc8( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC8_W { + FORCE_ERR_F_BNDRY_MATCH_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc9( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC9_W { + FORCE_ERR_F_BNDRY_MATCH_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc10( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC10_W { + FORCE_ERR_F_BNDRY_MATCH_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc11( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC11_W { + FORCE_ERR_F_BNDRY_MATCH_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc12( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC12_W { + FORCE_ERR_F_BNDRY_MATCH_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc13( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC13_W { + FORCE_ERR_F_BNDRY_MATCH_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc14( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC14_W { + FORCE_ERR_F_BNDRY_MATCH_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_bndry_match_vc15( + &mut self, + ) -> FORCE_ERR_F_BNDRY_MATCH_VC15_W { + FORCE_ERR_F_BNDRY_MATCH_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_bndry_frame_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_bndry_frame_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_FORCE_BNDRY_FRAME_FATAL_SPEC; +impl crate::RegisterSpec for INT_FORCE_BNDRY_FRAME_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_force_bndry_frame_fatal::R`](R) reader structure"] +impl crate::Readable for INT_FORCE_BNDRY_FRAME_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_force_bndry_frame_fatal::W`](W) writer structure"] +impl crate::Writable for INT_FORCE_BNDRY_FRAME_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_FORCE_BNDRY_FRAME_FATAL to value 0"] +impl crate::Resettable for INT_FORCE_BNDRY_FRAME_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_force_crc_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_crc_frame_fatal.rs new file mode 100644 index 0000000000..818cfe8345 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_force_crc_frame_fatal.rs @@ -0,0 +1,383 @@ +#[doc = "Register `INT_FORCE_CRC_FRAME_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_FORCE_CRC_FRAME_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC0` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC0_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC0` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC1` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC1_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC1` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC2` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC2_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC2` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC3` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC3_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC3` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC4` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC4_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC4` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC5` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC5_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC5` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC6` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC6_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC6` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC7` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC7_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC7` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC8` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC8_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC8` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC9` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC9_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC9` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC10` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC10_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC10` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC11` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC11_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC11` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC12` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC12_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC12` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC13` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC13_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC13` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC14` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC14_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC14` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC15` reader - NA"] +pub type FORCE_ERR_FRAME_DATA_VC15_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_FRAME_DATA_VC15` writer - NA"] +pub type FORCE_ERR_FRAME_DATA_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc0(&self) -> FORCE_ERR_FRAME_DATA_VC0_R { + FORCE_ERR_FRAME_DATA_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc1(&self) -> FORCE_ERR_FRAME_DATA_VC1_R { + FORCE_ERR_FRAME_DATA_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc2(&self) -> FORCE_ERR_FRAME_DATA_VC2_R { + FORCE_ERR_FRAME_DATA_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc3(&self) -> FORCE_ERR_FRAME_DATA_VC3_R { + FORCE_ERR_FRAME_DATA_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc4(&self) -> FORCE_ERR_FRAME_DATA_VC4_R { + FORCE_ERR_FRAME_DATA_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc5(&self) -> FORCE_ERR_FRAME_DATA_VC5_R { + FORCE_ERR_FRAME_DATA_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc6(&self) -> FORCE_ERR_FRAME_DATA_VC6_R { + FORCE_ERR_FRAME_DATA_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc7(&self) -> FORCE_ERR_FRAME_DATA_VC7_R { + FORCE_ERR_FRAME_DATA_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc8(&self) -> FORCE_ERR_FRAME_DATA_VC8_R { + FORCE_ERR_FRAME_DATA_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc9(&self) -> FORCE_ERR_FRAME_DATA_VC9_R { + FORCE_ERR_FRAME_DATA_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc10(&self) -> FORCE_ERR_FRAME_DATA_VC10_R { + FORCE_ERR_FRAME_DATA_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc11(&self) -> FORCE_ERR_FRAME_DATA_VC11_R { + FORCE_ERR_FRAME_DATA_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc12(&self) -> FORCE_ERR_FRAME_DATA_VC12_R { + FORCE_ERR_FRAME_DATA_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc13(&self) -> FORCE_ERR_FRAME_DATA_VC13_R { + FORCE_ERR_FRAME_DATA_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc14(&self) -> FORCE_ERR_FRAME_DATA_VC14_R { + FORCE_ERR_FRAME_DATA_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn force_err_frame_data_vc15(&self) -> FORCE_ERR_FRAME_DATA_VC15_R { + FORCE_ERR_FRAME_DATA_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_FORCE_CRC_FRAME_FATAL") + .field( + "force_err_frame_data_vc0", + &format_args!("{}", self.force_err_frame_data_vc0().bit()), + ) + .field( + "force_err_frame_data_vc1", + &format_args!("{}", self.force_err_frame_data_vc1().bit()), + ) + .field( + "force_err_frame_data_vc2", + &format_args!("{}", self.force_err_frame_data_vc2().bit()), + ) + .field( + "force_err_frame_data_vc3", + &format_args!("{}", self.force_err_frame_data_vc3().bit()), + ) + .field( + "force_err_frame_data_vc4", + &format_args!("{}", self.force_err_frame_data_vc4().bit()), + ) + .field( + "force_err_frame_data_vc5", + &format_args!("{}", self.force_err_frame_data_vc5().bit()), + ) + .field( + "force_err_frame_data_vc6", + &format_args!("{}", self.force_err_frame_data_vc6().bit()), + ) + .field( + "force_err_frame_data_vc7", + &format_args!("{}", self.force_err_frame_data_vc7().bit()), + ) + .field( + "force_err_frame_data_vc8", + &format_args!("{}", self.force_err_frame_data_vc8().bit()), + ) + .field( + "force_err_frame_data_vc9", + &format_args!("{}", self.force_err_frame_data_vc9().bit()), + ) + .field( + "force_err_frame_data_vc10", + &format_args!("{}", self.force_err_frame_data_vc10().bit()), + ) + .field( + "force_err_frame_data_vc11", + &format_args!("{}", self.force_err_frame_data_vc11().bit()), + ) + .field( + "force_err_frame_data_vc12", + &format_args!("{}", self.force_err_frame_data_vc12().bit()), + ) + .field( + "force_err_frame_data_vc13", + &format_args!("{}", self.force_err_frame_data_vc13().bit()), + ) + .field( + "force_err_frame_data_vc14", + &format_args!("{}", self.force_err_frame_data_vc14().bit()), + ) + .field( + "force_err_frame_data_vc15", + &format_args!("{}", self.force_err_frame_data_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc0( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC0_W { + FORCE_ERR_FRAME_DATA_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc1( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC1_W { + FORCE_ERR_FRAME_DATA_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc2( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC2_W { + FORCE_ERR_FRAME_DATA_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc3( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC3_W { + FORCE_ERR_FRAME_DATA_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc4( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC4_W { + FORCE_ERR_FRAME_DATA_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc5( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC5_W { + FORCE_ERR_FRAME_DATA_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc6( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC6_W { + FORCE_ERR_FRAME_DATA_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc7( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC7_W { + FORCE_ERR_FRAME_DATA_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc8( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC8_W { + FORCE_ERR_FRAME_DATA_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc9( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC9_W { + FORCE_ERR_FRAME_DATA_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc10( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC10_W { + FORCE_ERR_FRAME_DATA_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc11( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC11_W { + FORCE_ERR_FRAME_DATA_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc12( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC12_W { + FORCE_ERR_FRAME_DATA_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc13( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC13_W { + FORCE_ERR_FRAME_DATA_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc14( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC14_W { + FORCE_ERR_FRAME_DATA_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_frame_data_vc15( + &mut self, + ) -> FORCE_ERR_FRAME_DATA_VC15_W { + FORCE_ERR_FRAME_DATA_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_crc_frame_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_crc_frame_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_FORCE_CRC_FRAME_FATAL_SPEC; +impl crate::RegisterSpec for INT_FORCE_CRC_FRAME_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_force_crc_frame_fatal::R`](R) reader structure"] +impl crate::Readable for INT_FORCE_CRC_FRAME_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_force_crc_frame_fatal::W`](W) writer structure"] +impl crate::Writable for INT_FORCE_CRC_FRAME_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_FORCE_CRC_FRAME_FATAL to value 0"] +impl crate::Resettable for INT_FORCE_CRC_FRAME_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_force_data_id.rs b/esp32p4/src/mipi_csi_host/int_force_data_id.rs new file mode 100644 index 0000000000..daa5f30f8c --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_force_data_id.rs @@ -0,0 +1,351 @@ +#[doc = "Register `INT_FORCE_DATA_ID` reader"] +pub type R = crate::R; +#[doc = "Register `INT_FORCE_DATA_ID` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_ERR_ID_VC0` reader - NA"] +pub type FORCE_ERR_ID_VC0_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC0` writer - NA"] +pub type FORCE_ERR_ID_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC1` reader - NA"] +pub type FORCE_ERR_ID_VC1_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC1` writer - NA"] +pub type FORCE_ERR_ID_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC2` reader - NA"] +pub type FORCE_ERR_ID_VC2_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC2` writer - NA"] +pub type FORCE_ERR_ID_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC3` reader - NA"] +pub type FORCE_ERR_ID_VC3_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC3` writer - NA"] +pub type FORCE_ERR_ID_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC4` reader - NA"] +pub type FORCE_ERR_ID_VC4_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC4` writer - NA"] +pub type FORCE_ERR_ID_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC5` reader - NA"] +pub type FORCE_ERR_ID_VC5_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC5` writer - NA"] +pub type FORCE_ERR_ID_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC6` reader - NA"] +pub type FORCE_ERR_ID_VC6_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC6` writer - NA"] +pub type FORCE_ERR_ID_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC7` reader - NA"] +pub type FORCE_ERR_ID_VC7_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC7` writer - NA"] +pub type FORCE_ERR_ID_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC8` reader - NA"] +pub type FORCE_ERR_ID_VC8_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC8` writer - NA"] +pub type FORCE_ERR_ID_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC9` reader - NA"] +pub type FORCE_ERR_ID_VC9_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC9` writer - NA"] +pub type FORCE_ERR_ID_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC10` reader - NA"] +pub type FORCE_ERR_ID_VC10_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC10` writer - NA"] +pub type FORCE_ERR_ID_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC11` reader - NA"] +pub type FORCE_ERR_ID_VC11_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC11` writer - NA"] +pub type FORCE_ERR_ID_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC12` reader - NA"] +pub type FORCE_ERR_ID_VC12_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC12` writer - NA"] +pub type FORCE_ERR_ID_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC13` reader - NA"] +pub type FORCE_ERR_ID_VC13_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC13` writer - NA"] +pub type FORCE_ERR_ID_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC14` reader - NA"] +pub type FORCE_ERR_ID_VC14_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC14` writer - NA"] +pub type FORCE_ERR_ID_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ID_VC15` reader - NA"] +pub type FORCE_ERR_ID_VC15_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ID_VC15` writer - NA"] +pub type FORCE_ERR_ID_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn force_err_id_vc0(&self) -> FORCE_ERR_ID_VC0_R { + FORCE_ERR_ID_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn force_err_id_vc1(&self) -> FORCE_ERR_ID_VC1_R { + FORCE_ERR_ID_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn force_err_id_vc2(&self) -> FORCE_ERR_ID_VC2_R { + FORCE_ERR_ID_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn force_err_id_vc3(&self) -> FORCE_ERR_ID_VC3_R { + FORCE_ERR_ID_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn force_err_id_vc4(&self) -> FORCE_ERR_ID_VC4_R { + FORCE_ERR_ID_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn force_err_id_vc5(&self) -> FORCE_ERR_ID_VC5_R { + FORCE_ERR_ID_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn force_err_id_vc6(&self) -> FORCE_ERR_ID_VC6_R { + FORCE_ERR_ID_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn force_err_id_vc7(&self) -> FORCE_ERR_ID_VC7_R { + FORCE_ERR_ID_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn force_err_id_vc8(&self) -> FORCE_ERR_ID_VC8_R { + FORCE_ERR_ID_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn force_err_id_vc9(&self) -> FORCE_ERR_ID_VC9_R { + FORCE_ERR_ID_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn force_err_id_vc10(&self) -> FORCE_ERR_ID_VC10_R { + FORCE_ERR_ID_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn force_err_id_vc11(&self) -> FORCE_ERR_ID_VC11_R { + FORCE_ERR_ID_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn force_err_id_vc12(&self) -> FORCE_ERR_ID_VC12_R { + FORCE_ERR_ID_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn force_err_id_vc13(&self) -> FORCE_ERR_ID_VC13_R { + FORCE_ERR_ID_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn force_err_id_vc14(&self) -> FORCE_ERR_ID_VC14_R { + FORCE_ERR_ID_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn force_err_id_vc15(&self) -> FORCE_ERR_ID_VC15_R { + FORCE_ERR_ID_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_FORCE_DATA_ID") + .field( + "force_err_id_vc0", + &format_args!("{}", self.force_err_id_vc0().bit()), + ) + .field( + "force_err_id_vc1", + &format_args!("{}", self.force_err_id_vc1().bit()), + ) + .field( + "force_err_id_vc2", + &format_args!("{}", self.force_err_id_vc2().bit()), + ) + .field( + "force_err_id_vc3", + &format_args!("{}", self.force_err_id_vc3().bit()), + ) + .field( + "force_err_id_vc4", + &format_args!("{}", self.force_err_id_vc4().bit()), + ) + .field( + "force_err_id_vc5", + &format_args!("{}", self.force_err_id_vc5().bit()), + ) + .field( + "force_err_id_vc6", + &format_args!("{}", self.force_err_id_vc6().bit()), + ) + .field( + "force_err_id_vc7", + &format_args!("{}", self.force_err_id_vc7().bit()), + ) + .field( + "force_err_id_vc8", + &format_args!("{}", self.force_err_id_vc8().bit()), + ) + .field( + "force_err_id_vc9", + &format_args!("{}", self.force_err_id_vc9().bit()), + ) + .field( + "force_err_id_vc10", + &format_args!("{}", self.force_err_id_vc10().bit()), + ) + .field( + "force_err_id_vc11", + &format_args!("{}", self.force_err_id_vc11().bit()), + ) + .field( + "force_err_id_vc12", + &format_args!("{}", self.force_err_id_vc12().bit()), + ) + .field( + "force_err_id_vc13", + &format_args!("{}", self.force_err_id_vc13().bit()), + ) + .field( + "force_err_id_vc14", + &format_args!("{}", self.force_err_id_vc14().bit()), + ) + .field( + "force_err_id_vc15", + &format_args!("{}", self.force_err_id_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc0(&mut self) -> FORCE_ERR_ID_VC0_W { + FORCE_ERR_ID_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc1(&mut self) -> FORCE_ERR_ID_VC1_W { + FORCE_ERR_ID_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc2(&mut self) -> FORCE_ERR_ID_VC2_W { + FORCE_ERR_ID_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc3(&mut self) -> FORCE_ERR_ID_VC3_W { + FORCE_ERR_ID_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc4(&mut self) -> FORCE_ERR_ID_VC4_W { + FORCE_ERR_ID_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc5(&mut self) -> FORCE_ERR_ID_VC5_W { + FORCE_ERR_ID_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc6(&mut self) -> FORCE_ERR_ID_VC6_W { + FORCE_ERR_ID_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc7(&mut self) -> FORCE_ERR_ID_VC7_W { + FORCE_ERR_ID_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc8(&mut self) -> FORCE_ERR_ID_VC8_W { + FORCE_ERR_ID_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc9(&mut self) -> FORCE_ERR_ID_VC9_W { + FORCE_ERR_ID_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc10(&mut self) -> FORCE_ERR_ID_VC10_W { + FORCE_ERR_ID_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc11(&mut self) -> FORCE_ERR_ID_VC11_W { + FORCE_ERR_ID_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc12(&mut self) -> FORCE_ERR_ID_VC12_W { + FORCE_ERR_ID_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc13(&mut self) -> FORCE_ERR_ID_VC13_W { + FORCE_ERR_ID_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc14(&mut self) -> FORCE_ERR_ID_VC14_W { + FORCE_ERR_ID_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_id_vc15(&mut self) -> FORCE_ERR_ID_VC15_W { + FORCE_ERR_ID_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_data_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_data_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_FORCE_DATA_ID_SPEC; +impl crate::RegisterSpec for INT_FORCE_DATA_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_force_data_id::R`](R) reader structure"] +impl crate::Readable for INT_FORCE_DATA_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_force_data_id::W`](W) writer structure"] +impl crate::Writable for INT_FORCE_DATA_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_FORCE_DATA_ID to value 0"] +impl crate::Resettable for INT_FORCE_DATA_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_force_ecc_corrected.rs b/esp32p4/src/mipi_csi_host/int_force_ecc_corrected.rs new file mode 100644 index 0000000000..0b9c1ba16e --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_force_ecc_corrected.rs @@ -0,0 +1,383 @@ +#[doc = "Register `INT_FORCE_ECC_CORRECTED` reader"] +pub type R = crate::R; +#[doc = "Register `INT_FORCE_ECC_CORRECTED` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC0` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC0_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC0` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC1` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC1_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC1` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC2` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC2_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC2` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC3` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC3_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC3` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC4` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC4_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC4` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC5` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC5_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC5` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC6` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC6_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC6` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC7` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC7_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC7` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC8` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC8_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC8` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC9` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC9_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC9` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC10` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC10_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC10` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC11` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC11_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC11` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC12` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC12_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC12` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC13` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC13_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC13` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC14` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC14_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC14` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC15` reader - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC15_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_CORRECTED_VC15` writer - NA"] +pub type FORCE_ERR_ECC_CORRECTED_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc0(&self) -> FORCE_ERR_ECC_CORRECTED_VC0_R { + FORCE_ERR_ECC_CORRECTED_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc1(&self) -> FORCE_ERR_ECC_CORRECTED_VC1_R { + FORCE_ERR_ECC_CORRECTED_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc2(&self) -> FORCE_ERR_ECC_CORRECTED_VC2_R { + FORCE_ERR_ECC_CORRECTED_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc3(&self) -> FORCE_ERR_ECC_CORRECTED_VC3_R { + FORCE_ERR_ECC_CORRECTED_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc4(&self) -> FORCE_ERR_ECC_CORRECTED_VC4_R { + FORCE_ERR_ECC_CORRECTED_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc5(&self) -> FORCE_ERR_ECC_CORRECTED_VC5_R { + FORCE_ERR_ECC_CORRECTED_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc6(&self) -> FORCE_ERR_ECC_CORRECTED_VC6_R { + FORCE_ERR_ECC_CORRECTED_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc7(&self) -> FORCE_ERR_ECC_CORRECTED_VC7_R { + FORCE_ERR_ECC_CORRECTED_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc8(&self) -> FORCE_ERR_ECC_CORRECTED_VC8_R { + FORCE_ERR_ECC_CORRECTED_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc9(&self) -> FORCE_ERR_ECC_CORRECTED_VC9_R { + FORCE_ERR_ECC_CORRECTED_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc10(&self) -> FORCE_ERR_ECC_CORRECTED_VC10_R { + FORCE_ERR_ECC_CORRECTED_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc11(&self) -> FORCE_ERR_ECC_CORRECTED_VC11_R { + FORCE_ERR_ECC_CORRECTED_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc12(&self) -> FORCE_ERR_ECC_CORRECTED_VC12_R { + FORCE_ERR_ECC_CORRECTED_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc13(&self) -> FORCE_ERR_ECC_CORRECTED_VC13_R { + FORCE_ERR_ECC_CORRECTED_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc14(&self) -> FORCE_ERR_ECC_CORRECTED_VC14_R { + FORCE_ERR_ECC_CORRECTED_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn force_err_ecc_corrected_vc15(&self) -> FORCE_ERR_ECC_CORRECTED_VC15_R { + FORCE_ERR_ECC_CORRECTED_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_FORCE_ECC_CORRECTED") + .field( + "force_err_ecc_corrected_vc0", + &format_args!("{}", self.force_err_ecc_corrected_vc0().bit()), + ) + .field( + "force_err_ecc_corrected_vc1", + &format_args!("{}", self.force_err_ecc_corrected_vc1().bit()), + ) + .field( + "force_err_ecc_corrected_vc2", + &format_args!("{}", self.force_err_ecc_corrected_vc2().bit()), + ) + .field( + "force_err_ecc_corrected_vc3", + &format_args!("{}", self.force_err_ecc_corrected_vc3().bit()), + ) + .field( + "force_err_ecc_corrected_vc4", + &format_args!("{}", self.force_err_ecc_corrected_vc4().bit()), + ) + .field( + "force_err_ecc_corrected_vc5", + &format_args!("{}", self.force_err_ecc_corrected_vc5().bit()), + ) + .field( + "force_err_ecc_corrected_vc6", + &format_args!("{}", self.force_err_ecc_corrected_vc6().bit()), + ) + .field( + "force_err_ecc_corrected_vc7", + &format_args!("{}", self.force_err_ecc_corrected_vc7().bit()), + ) + .field( + "force_err_ecc_corrected_vc8", + &format_args!("{}", self.force_err_ecc_corrected_vc8().bit()), + ) + .field( + "force_err_ecc_corrected_vc9", + &format_args!("{}", self.force_err_ecc_corrected_vc9().bit()), + ) + .field( + "force_err_ecc_corrected_vc10", + &format_args!("{}", self.force_err_ecc_corrected_vc10().bit()), + ) + .field( + "force_err_ecc_corrected_vc11", + &format_args!("{}", self.force_err_ecc_corrected_vc11().bit()), + ) + .field( + "force_err_ecc_corrected_vc12", + &format_args!("{}", self.force_err_ecc_corrected_vc12().bit()), + ) + .field( + "force_err_ecc_corrected_vc13", + &format_args!("{}", self.force_err_ecc_corrected_vc13().bit()), + ) + .field( + "force_err_ecc_corrected_vc14", + &format_args!("{}", self.force_err_ecc_corrected_vc14().bit()), + ) + .field( + "force_err_ecc_corrected_vc15", + &format_args!("{}", self.force_err_ecc_corrected_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc0( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC0_W { + FORCE_ERR_ECC_CORRECTED_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc1( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC1_W { + FORCE_ERR_ECC_CORRECTED_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc2( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC2_W { + FORCE_ERR_ECC_CORRECTED_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc3( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC3_W { + FORCE_ERR_ECC_CORRECTED_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc4( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC4_W { + FORCE_ERR_ECC_CORRECTED_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc5( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC5_W { + FORCE_ERR_ECC_CORRECTED_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc6( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC6_W { + FORCE_ERR_ECC_CORRECTED_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc7( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC7_W { + FORCE_ERR_ECC_CORRECTED_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc8( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC8_W { + FORCE_ERR_ECC_CORRECTED_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc9( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC9_W { + FORCE_ERR_ECC_CORRECTED_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc10( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC10_W { + FORCE_ERR_ECC_CORRECTED_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc11( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC11_W { + FORCE_ERR_ECC_CORRECTED_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc12( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC12_W { + FORCE_ERR_ECC_CORRECTED_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc13( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC13_W { + FORCE_ERR_ECC_CORRECTED_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc14( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC14_W { + FORCE_ERR_ECC_CORRECTED_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_corrected_vc15( + &mut self, + ) -> FORCE_ERR_ECC_CORRECTED_VC15_W { + FORCE_ERR_ECC_CORRECTED_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_ecc_corrected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_ecc_corrected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_FORCE_ECC_CORRECTED_SPEC; +impl crate::RegisterSpec for INT_FORCE_ECC_CORRECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_force_ecc_corrected::R`](R) reader structure"] +impl crate::Readable for INT_FORCE_ECC_CORRECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_force_ecc_corrected::W`](W) writer structure"] +impl crate::Writable for INT_FORCE_ECC_CORRECTED_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_FORCE_ECC_CORRECTED to value 0"] +impl crate::Resettable for INT_FORCE_ECC_CORRECTED_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_force_phy.rs b/esp32p4/src/mipi_csi_host/int_force_phy.rs new file mode 100644 index 0000000000..1c9da04c9a --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_force_phy.rs @@ -0,0 +1,123 @@ +#[doc = "Register `INT_FORCE_PHY` reader"] +pub type R = crate::R; +#[doc = "Register `INT_FORCE_PHY` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_PHY_ERRSOTHS_0` reader - NA"] +pub type FORCE_PHY_ERRSOTHS_0_R = crate::BitReader; +#[doc = "Field `FORCE_PHY_ERRSOTHS_0` writer - NA"] +pub type FORCE_PHY_ERRSOTHS_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_PHY_ERRSOTHS_1` reader - NA"] +pub type FORCE_PHY_ERRSOTHS_1_R = crate::BitReader; +#[doc = "Field `FORCE_PHY_ERRSOTHS_1` writer - NA"] +pub type FORCE_PHY_ERRSOTHS_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_PHY_ERRESC_0` reader - NA"] +pub type FORCE_PHY_ERRESC_0_R = crate::BitReader; +#[doc = "Field `FORCE_PHY_ERRESC_0` writer - NA"] +pub type FORCE_PHY_ERRESC_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_PHY_ERRESC_1` reader - NA"] +pub type FORCE_PHY_ERRESC_1_R = crate::BitReader; +#[doc = "Field `FORCE_PHY_ERRESC_1` writer - NA"] +pub type FORCE_PHY_ERRESC_1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn force_phy_errsoths_0(&self) -> FORCE_PHY_ERRSOTHS_0_R { + FORCE_PHY_ERRSOTHS_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn force_phy_errsoths_1(&self) -> FORCE_PHY_ERRSOTHS_1_R { + FORCE_PHY_ERRSOTHS_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn force_phy_erresc_0(&self) -> FORCE_PHY_ERRESC_0_R { + FORCE_PHY_ERRESC_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn force_phy_erresc_1(&self) -> FORCE_PHY_ERRESC_1_R { + FORCE_PHY_ERRESC_1_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_FORCE_PHY") + .field( + "force_phy_errsoths_0", + &format_args!("{}", self.force_phy_errsoths_0().bit()), + ) + .field( + "force_phy_errsoths_1", + &format_args!("{}", self.force_phy_errsoths_1().bit()), + ) + .field( + "force_phy_erresc_0", + &format_args!("{}", self.force_phy_erresc_0().bit()), + ) + .field( + "force_phy_erresc_1", + &format_args!("{}", self.force_phy_erresc_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn force_phy_errsoths_0(&mut self) -> FORCE_PHY_ERRSOTHS_0_W { + FORCE_PHY_ERRSOTHS_0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn force_phy_errsoths_1(&mut self) -> FORCE_PHY_ERRSOTHS_1_W { + FORCE_PHY_ERRSOTHS_1_W::new(self, 1) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn force_phy_erresc_0(&mut self) -> FORCE_PHY_ERRESC_0_W { + FORCE_PHY_ERRESC_0_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn force_phy_erresc_1(&mut self) -> FORCE_PHY_ERRESC_1_W { + FORCE_PHY_ERRESC_1_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_phy::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_phy::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_FORCE_PHY_SPEC; +impl crate::RegisterSpec for INT_FORCE_PHY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_force_phy::R`](R) reader structure"] +impl crate::Readable for INT_FORCE_PHY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_force_phy::W`](W) writer structure"] +impl crate::Writable for INT_FORCE_PHY_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_FORCE_PHY to value 0"] +impl crate::Resettable for INT_FORCE_PHY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_force_phy_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_phy_fatal.rs new file mode 100644 index 0000000000..502852eb1f --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_force_phy_fatal.rs @@ -0,0 +1,89 @@ +#[doc = "Register `INT_FORCE_PHY_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_FORCE_PHY_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_PHY_ERRSOTSYNCHS_0` reader - NA"] +pub type FORCE_PHY_ERRSOTSYNCHS_0_R = crate::BitReader; +#[doc = "Field `FORCE_PHY_ERRSOTSYNCHS_0` writer - NA"] +pub type FORCE_PHY_ERRSOTSYNCHS_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_PHY_ERRSOTSYNCHS_1` reader - NA"] +pub type FORCE_PHY_ERRSOTSYNCHS_1_R = crate::BitReader; +#[doc = "Field `FORCE_PHY_ERRSOTSYNCHS_1` writer - NA"] +pub type FORCE_PHY_ERRSOTSYNCHS_1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn force_phy_errsotsynchs_0(&self) -> FORCE_PHY_ERRSOTSYNCHS_0_R { + FORCE_PHY_ERRSOTSYNCHS_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn force_phy_errsotsynchs_1(&self) -> FORCE_PHY_ERRSOTSYNCHS_1_R { + FORCE_PHY_ERRSOTSYNCHS_1_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_FORCE_PHY_FATAL") + .field( + "force_phy_errsotsynchs_0", + &format_args!("{}", self.force_phy_errsotsynchs_0().bit()), + ) + .field( + "force_phy_errsotsynchs_1", + &format_args!("{}", self.force_phy_errsotsynchs_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn force_phy_errsotsynchs_0( + &mut self, + ) -> FORCE_PHY_ERRSOTSYNCHS_0_W { + FORCE_PHY_ERRSOTSYNCHS_0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn force_phy_errsotsynchs_1( + &mut self, + ) -> FORCE_PHY_ERRSOTSYNCHS_1_W { + FORCE_PHY_ERRSOTSYNCHS_1_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_phy_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_phy_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_FORCE_PHY_FATAL_SPEC; +impl crate::RegisterSpec for INT_FORCE_PHY_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_force_phy_fatal::R`](R) reader structure"] +impl crate::Readable for INT_FORCE_PHY_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_force_phy_fatal::W`](W) writer structure"] +impl crate::Writable for INT_FORCE_PHY_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_FORCE_PHY_FATAL to value 0"] +impl crate::Resettable for INT_FORCE_PHY_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_force_pkt_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_pkt_fatal.rs new file mode 100644 index 0000000000..ba9028cd89 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_force_pkt_fatal.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INT_FORCE_PKT_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_FORCE_PKT_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_ERR_ECC_DOUBLE` reader - NA"] +pub type FORCE_ERR_ECC_DOUBLE_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_ECC_DOUBLE` writer - NA"] +pub type FORCE_ERR_ECC_DOUBLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_SHORTER_PAYLOAD` reader - NA"] +pub type FORCE_SHORTER_PAYLOAD_R = crate::BitReader; +#[doc = "Field `FORCE_SHORTER_PAYLOAD` writer - NA"] +pub type FORCE_SHORTER_PAYLOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn force_err_ecc_double(&self) -> FORCE_ERR_ECC_DOUBLE_R { + FORCE_ERR_ECC_DOUBLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn force_shorter_payload(&self) -> FORCE_SHORTER_PAYLOAD_R { + FORCE_SHORTER_PAYLOAD_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_FORCE_PKT_FATAL") + .field( + "force_err_ecc_double", + &format_args!("{}", self.force_err_ecc_double().bit()), + ) + .field( + "force_shorter_payload", + &format_args!("{}", self.force_shorter_payload().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_ecc_double(&mut self) -> FORCE_ERR_ECC_DOUBLE_W { + FORCE_ERR_ECC_DOUBLE_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn force_shorter_payload(&mut self) -> FORCE_SHORTER_PAYLOAD_W { + FORCE_SHORTER_PAYLOAD_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_pkt_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_pkt_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_FORCE_PKT_FATAL_SPEC; +impl crate::RegisterSpec for INT_FORCE_PKT_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_force_pkt_fatal::R`](R) reader structure"] +impl crate::Readable for INT_FORCE_PKT_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_force_pkt_fatal::W`](W) writer structure"] +impl crate::Writable for INT_FORCE_PKT_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_FORCE_PKT_FATAL to value 0"] +impl crate::Resettable for INT_FORCE_PKT_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_force_pld_crc_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_pld_crc_fatal.rs new file mode 100644 index 0000000000..e0b694ee9f --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_force_pld_crc_fatal.rs @@ -0,0 +1,351 @@ +#[doc = "Register `INT_FORCE_PLD_CRC_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_FORCE_PLD_CRC_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_ERR_CRC_VC0` reader - NA"] +pub type FORCE_ERR_CRC_VC0_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC0` writer - NA"] +pub type FORCE_ERR_CRC_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC1` reader - NA"] +pub type FORCE_ERR_CRC_VC1_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC1` writer - NA"] +pub type FORCE_ERR_CRC_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC2` reader - NA"] +pub type FORCE_ERR_CRC_VC2_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC2` writer - NA"] +pub type FORCE_ERR_CRC_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC3` reader - NA"] +pub type FORCE_ERR_CRC_VC3_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC3` writer - NA"] +pub type FORCE_ERR_CRC_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC4` reader - NA"] +pub type FORCE_ERR_CRC_VC4_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC4` writer - NA"] +pub type FORCE_ERR_CRC_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC5` reader - NA"] +pub type FORCE_ERR_CRC_VC5_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC5` writer - NA"] +pub type FORCE_ERR_CRC_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC6` reader - NA"] +pub type FORCE_ERR_CRC_VC6_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC6` writer - NA"] +pub type FORCE_ERR_CRC_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC7` reader - NA"] +pub type FORCE_ERR_CRC_VC7_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC7` writer - NA"] +pub type FORCE_ERR_CRC_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC8` reader - NA"] +pub type FORCE_ERR_CRC_VC8_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC8` writer - NA"] +pub type FORCE_ERR_CRC_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC9` reader - NA"] +pub type FORCE_ERR_CRC_VC9_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC9` writer - NA"] +pub type FORCE_ERR_CRC_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC10` reader - NA"] +pub type FORCE_ERR_CRC_VC10_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC10` writer - NA"] +pub type FORCE_ERR_CRC_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC11` reader - NA"] +pub type FORCE_ERR_CRC_VC11_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC11` writer - NA"] +pub type FORCE_ERR_CRC_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC12` reader - NA"] +pub type FORCE_ERR_CRC_VC12_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC12` writer - NA"] +pub type FORCE_ERR_CRC_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC13` reader - NA"] +pub type FORCE_ERR_CRC_VC13_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC13` writer - NA"] +pub type FORCE_ERR_CRC_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC14` reader - NA"] +pub type FORCE_ERR_CRC_VC14_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC14` writer - NA"] +pub type FORCE_ERR_CRC_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_CRC_VC15` reader - NA"] +pub type FORCE_ERR_CRC_VC15_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_CRC_VC15` writer - NA"] +pub type FORCE_ERR_CRC_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn force_err_crc_vc0(&self) -> FORCE_ERR_CRC_VC0_R { + FORCE_ERR_CRC_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn force_err_crc_vc1(&self) -> FORCE_ERR_CRC_VC1_R { + FORCE_ERR_CRC_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn force_err_crc_vc2(&self) -> FORCE_ERR_CRC_VC2_R { + FORCE_ERR_CRC_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn force_err_crc_vc3(&self) -> FORCE_ERR_CRC_VC3_R { + FORCE_ERR_CRC_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn force_err_crc_vc4(&self) -> FORCE_ERR_CRC_VC4_R { + FORCE_ERR_CRC_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn force_err_crc_vc5(&self) -> FORCE_ERR_CRC_VC5_R { + FORCE_ERR_CRC_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn force_err_crc_vc6(&self) -> FORCE_ERR_CRC_VC6_R { + FORCE_ERR_CRC_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn force_err_crc_vc7(&self) -> FORCE_ERR_CRC_VC7_R { + FORCE_ERR_CRC_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn force_err_crc_vc8(&self) -> FORCE_ERR_CRC_VC8_R { + FORCE_ERR_CRC_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn force_err_crc_vc9(&self) -> FORCE_ERR_CRC_VC9_R { + FORCE_ERR_CRC_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn force_err_crc_vc10(&self) -> FORCE_ERR_CRC_VC10_R { + FORCE_ERR_CRC_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn force_err_crc_vc11(&self) -> FORCE_ERR_CRC_VC11_R { + FORCE_ERR_CRC_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn force_err_crc_vc12(&self) -> FORCE_ERR_CRC_VC12_R { + FORCE_ERR_CRC_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn force_err_crc_vc13(&self) -> FORCE_ERR_CRC_VC13_R { + FORCE_ERR_CRC_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn force_err_crc_vc14(&self) -> FORCE_ERR_CRC_VC14_R { + FORCE_ERR_CRC_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn force_err_crc_vc15(&self) -> FORCE_ERR_CRC_VC15_R { + FORCE_ERR_CRC_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_FORCE_PLD_CRC_FATAL") + .field( + "force_err_crc_vc0", + &format_args!("{}", self.force_err_crc_vc0().bit()), + ) + .field( + "force_err_crc_vc1", + &format_args!("{}", self.force_err_crc_vc1().bit()), + ) + .field( + "force_err_crc_vc2", + &format_args!("{}", self.force_err_crc_vc2().bit()), + ) + .field( + "force_err_crc_vc3", + &format_args!("{}", self.force_err_crc_vc3().bit()), + ) + .field( + "force_err_crc_vc4", + &format_args!("{}", self.force_err_crc_vc4().bit()), + ) + .field( + "force_err_crc_vc5", + &format_args!("{}", self.force_err_crc_vc5().bit()), + ) + .field( + "force_err_crc_vc6", + &format_args!("{}", self.force_err_crc_vc6().bit()), + ) + .field( + "force_err_crc_vc7", + &format_args!("{}", self.force_err_crc_vc7().bit()), + ) + .field( + "force_err_crc_vc8", + &format_args!("{}", self.force_err_crc_vc8().bit()), + ) + .field( + "force_err_crc_vc9", + &format_args!("{}", self.force_err_crc_vc9().bit()), + ) + .field( + "force_err_crc_vc10", + &format_args!("{}", self.force_err_crc_vc10().bit()), + ) + .field( + "force_err_crc_vc11", + &format_args!("{}", self.force_err_crc_vc11().bit()), + ) + .field( + "force_err_crc_vc12", + &format_args!("{}", self.force_err_crc_vc12().bit()), + ) + .field( + "force_err_crc_vc13", + &format_args!("{}", self.force_err_crc_vc13().bit()), + ) + .field( + "force_err_crc_vc14", + &format_args!("{}", self.force_err_crc_vc14().bit()), + ) + .field( + "force_err_crc_vc15", + &format_args!("{}", self.force_err_crc_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc0(&mut self) -> FORCE_ERR_CRC_VC0_W { + FORCE_ERR_CRC_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc1(&mut self) -> FORCE_ERR_CRC_VC1_W { + FORCE_ERR_CRC_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc2(&mut self) -> FORCE_ERR_CRC_VC2_W { + FORCE_ERR_CRC_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc3(&mut self) -> FORCE_ERR_CRC_VC3_W { + FORCE_ERR_CRC_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc4(&mut self) -> FORCE_ERR_CRC_VC4_W { + FORCE_ERR_CRC_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc5(&mut self) -> FORCE_ERR_CRC_VC5_W { + FORCE_ERR_CRC_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc6(&mut self) -> FORCE_ERR_CRC_VC6_W { + FORCE_ERR_CRC_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc7(&mut self) -> FORCE_ERR_CRC_VC7_W { + FORCE_ERR_CRC_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc8(&mut self) -> FORCE_ERR_CRC_VC8_W { + FORCE_ERR_CRC_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc9(&mut self) -> FORCE_ERR_CRC_VC9_W { + FORCE_ERR_CRC_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc10(&mut self) -> FORCE_ERR_CRC_VC10_W { + FORCE_ERR_CRC_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc11(&mut self) -> FORCE_ERR_CRC_VC11_W { + FORCE_ERR_CRC_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc12(&mut self) -> FORCE_ERR_CRC_VC12_W { + FORCE_ERR_CRC_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc13(&mut self) -> FORCE_ERR_CRC_VC13_W { + FORCE_ERR_CRC_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc14(&mut self) -> FORCE_ERR_CRC_VC14_W { + FORCE_ERR_CRC_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_crc_vc15(&mut self) -> FORCE_ERR_CRC_VC15_W { + FORCE_ERR_CRC_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_pld_crc_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_pld_crc_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_FORCE_PLD_CRC_FATAL_SPEC; +impl crate::RegisterSpec for INT_FORCE_PLD_CRC_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_force_pld_crc_fatal::R`](R) reader structure"] +impl crate::Readable for INT_FORCE_PLD_CRC_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_force_pld_crc_fatal::W`](W) writer structure"] +impl crate::Writable for INT_FORCE_PLD_CRC_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_FORCE_PLD_CRC_FATAL to value 0"] +impl crate::Resettable for INT_FORCE_PLD_CRC_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_force_seq_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_seq_frame_fatal.rs new file mode 100644 index 0000000000..a979b33930 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_force_seq_frame_fatal.rs @@ -0,0 +1,363 @@ +#[doc = "Register `INT_FORCE_SEQ_FRAME_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_FORCE_SEQ_FRAME_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_ERR_F_SEQ_VC0` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC0_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC0` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC1` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC1_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC1` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC2` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC2_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC2` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC3` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC3_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC3` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC4` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC4_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC4` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC5` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC5_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC5` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC6` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC6_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC6` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC7` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC7_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC7` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC8` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC8_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC8` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC9` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC9_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC9` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC10` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC10_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC10` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC11` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC11_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC11` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC12` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC12_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC12` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC13` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC13_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC13` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC14` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC14_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC14` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ERR_F_SEQ_VC15` reader - NA"] +pub type FORCE_ERR_F_SEQ_VC15_R = crate::BitReader; +#[doc = "Field `FORCE_ERR_F_SEQ_VC15` writer - NA"] +pub type FORCE_ERR_F_SEQ_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc0(&self) -> FORCE_ERR_F_SEQ_VC0_R { + FORCE_ERR_F_SEQ_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc1(&self) -> FORCE_ERR_F_SEQ_VC1_R { + FORCE_ERR_F_SEQ_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc2(&self) -> FORCE_ERR_F_SEQ_VC2_R { + FORCE_ERR_F_SEQ_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc3(&self) -> FORCE_ERR_F_SEQ_VC3_R { + FORCE_ERR_F_SEQ_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc4(&self) -> FORCE_ERR_F_SEQ_VC4_R { + FORCE_ERR_F_SEQ_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc5(&self) -> FORCE_ERR_F_SEQ_VC5_R { + FORCE_ERR_F_SEQ_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc6(&self) -> FORCE_ERR_F_SEQ_VC6_R { + FORCE_ERR_F_SEQ_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc7(&self) -> FORCE_ERR_F_SEQ_VC7_R { + FORCE_ERR_F_SEQ_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc8(&self) -> FORCE_ERR_F_SEQ_VC8_R { + FORCE_ERR_F_SEQ_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc9(&self) -> FORCE_ERR_F_SEQ_VC9_R { + FORCE_ERR_F_SEQ_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc10(&self) -> FORCE_ERR_F_SEQ_VC10_R { + FORCE_ERR_F_SEQ_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc11(&self) -> FORCE_ERR_F_SEQ_VC11_R { + FORCE_ERR_F_SEQ_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc12(&self) -> FORCE_ERR_F_SEQ_VC12_R { + FORCE_ERR_F_SEQ_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc13(&self) -> FORCE_ERR_F_SEQ_VC13_R { + FORCE_ERR_F_SEQ_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc14(&self) -> FORCE_ERR_F_SEQ_VC14_R { + FORCE_ERR_F_SEQ_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn force_err_f_seq_vc15(&self) -> FORCE_ERR_F_SEQ_VC15_R { + FORCE_ERR_F_SEQ_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_FORCE_SEQ_FRAME_FATAL") + .field( + "force_err_f_seq_vc0", + &format_args!("{}", self.force_err_f_seq_vc0().bit()), + ) + .field( + "force_err_f_seq_vc1", + &format_args!("{}", self.force_err_f_seq_vc1().bit()), + ) + .field( + "force_err_f_seq_vc2", + &format_args!("{}", self.force_err_f_seq_vc2().bit()), + ) + .field( + "force_err_f_seq_vc3", + &format_args!("{}", self.force_err_f_seq_vc3().bit()), + ) + .field( + "force_err_f_seq_vc4", + &format_args!("{}", self.force_err_f_seq_vc4().bit()), + ) + .field( + "force_err_f_seq_vc5", + &format_args!("{}", self.force_err_f_seq_vc5().bit()), + ) + .field( + "force_err_f_seq_vc6", + &format_args!("{}", self.force_err_f_seq_vc6().bit()), + ) + .field( + "force_err_f_seq_vc7", + &format_args!("{}", self.force_err_f_seq_vc7().bit()), + ) + .field( + "force_err_f_seq_vc8", + &format_args!("{}", self.force_err_f_seq_vc8().bit()), + ) + .field( + "force_err_f_seq_vc9", + &format_args!("{}", self.force_err_f_seq_vc9().bit()), + ) + .field( + "force_err_f_seq_vc10", + &format_args!("{}", self.force_err_f_seq_vc10().bit()), + ) + .field( + "force_err_f_seq_vc11", + &format_args!("{}", self.force_err_f_seq_vc11().bit()), + ) + .field( + "force_err_f_seq_vc12", + &format_args!("{}", self.force_err_f_seq_vc12().bit()), + ) + .field( + "force_err_f_seq_vc13", + &format_args!("{}", self.force_err_f_seq_vc13().bit()), + ) + .field( + "force_err_f_seq_vc14", + &format_args!("{}", self.force_err_f_seq_vc14().bit()), + ) + .field( + "force_err_f_seq_vc15", + &format_args!("{}", self.force_err_f_seq_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc0(&mut self) -> FORCE_ERR_F_SEQ_VC0_W { + FORCE_ERR_F_SEQ_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc1(&mut self) -> FORCE_ERR_F_SEQ_VC1_W { + FORCE_ERR_F_SEQ_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc2(&mut self) -> FORCE_ERR_F_SEQ_VC2_W { + FORCE_ERR_F_SEQ_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc3(&mut self) -> FORCE_ERR_F_SEQ_VC3_W { + FORCE_ERR_F_SEQ_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc4(&mut self) -> FORCE_ERR_F_SEQ_VC4_W { + FORCE_ERR_F_SEQ_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc5(&mut self) -> FORCE_ERR_F_SEQ_VC5_W { + FORCE_ERR_F_SEQ_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc6(&mut self) -> FORCE_ERR_F_SEQ_VC6_W { + FORCE_ERR_F_SEQ_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc7(&mut self) -> FORCE_ERR_F_SEQ_VC7_W { + FORCE_ERR_F_SEQ_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc8(&mut self) -> FORCE_ERR_F_SEQ_VC8_W { + FORCE_ERR_F_SEQ_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc9(&mut self) -> FORCE_ERR_F_SEQ_VC9_W { + FORCE_ERR_F_SEQ_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc10( + &mut self, + ) -> FORCE_ERR_F_SEQ_VC10_W { + FORCE_ERR_F_SEQ_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc11( + &mut self, + ) -> FORCE_ERR_F_SEQ_VC11_W { + FORCE_ERR_F_SEQ_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc12( + &mut self, + ) -> FORCE_ERR_F_SEQ_VC12_W { + FORCE_ERR_F_SEQ_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc13( + &mut self, + ) -> FORCE_ERR_F_SEQ_VC13_W { + FORCE_ERR_F_SEQ_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc14( + &mut self, + ) -> FORCE_ERR_F_SEQ_VC14_W { + FORCE_ERR_F_SEQ_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn force_err_f_seq_vc15( + &mut self, + ) -> FORCE_ERR_F_SEQ_VC15_W { + FORCE_ERR_F_SEQ_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force_seq_frame_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force_seq_frame_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_FORCE_SEQ_FRAME_FATAL_SPEC; +impl crate::RegisterSpec for INT_FORCE_SEQ_FRAME_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_force_seq_frame_fatal::R`](R) reader structure"] +impl crate::Readable for INT_FORCE_SEQ_FRAME_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_force_seq_frame_fatal::W`](W) writer structure"] +impl crate::Writable for INT_FORCE_SEQ_FRAME_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_FORCE_SEQ_FRAME_FATAL to value 0"] +impl crate::Resettable for INT_FORCE_SEQ_FRAME_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_msk_bndry_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_bndry_frame_fatal.rs new file mode 100644 index 0000000000..67b24e3158 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_msk_bndry_frame_fatal.rs @@ -0,0 +1,383 @@ +#[doc = "Register `INT_MSK_BNDRY_FRAME_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MSK_BNDRY_FRAME_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC0` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC0_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC0` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC1` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC1_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC1` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC2` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC2_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC2` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC3` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC3_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC3` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC4` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC4_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC4` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC5` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC5_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC5` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC6` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC6_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC6` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC7` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC7_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC7` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC8` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC8_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC8` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC9` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC9_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC9` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC10` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC10_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC10` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC11` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC11_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC11` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC12` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC12_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC12` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC13` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC13_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC13` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC14` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC14_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC14` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC15` reader - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC15_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_BNDRY_MATCH_VC15` writer - NA"] +pub type MASK_ERR_F_BNDRY_MATCH_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc0(&self) -> MASK_ERR_F_BNDRY_MATCH_VC0_R { + MASK_ERR_F_BNDRY_MATCH_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc1(&self) -> MASK_ERR_F_BNDRY_MATCH_VC1_R { + MASK_ERR_F_BNDRY_MATCH_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc2(&self) -> MASK_ERR_F_BNDRY_MATCH_VC2_R { + MASK_ERR_F_BNDRY_MATCH_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc3(&self) -> MASK_ERR_F_BNDRY_MATCH_VC3_R { + MASK_ERR_F_BNDRY_MATCH_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc4(&self) -> MASK_ERR_F_BNDRY_MATCH_VC4_R { + MASK_ERR_F_BNDRY_MATCH_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc5(&self) -> MASK_ERR_F_BNDRY_MATCH_VC5_R { + MASK_ERR_F_BNDRY_MATCH_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc6(&self) -> MASK_ERR_F_BNDRY_MATCH_VC6_R { + MASK_ERR_F_BNDRY_MATCH_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc7(&self) -> MASK_ERR_F_BNDRY_MATCH_VC7_R { + MASK_ERR_F_BNDRY_MATCH_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc8(&self) -> MASK_ERR_F_BNDRY_MATCH_VC8_R { + MASK_ERR_F_BNDRY_MATCH_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc9(&self) -> MASK_ERR_F_BNDRY_MATCH_VC9_R { + MASK_ERR_F_BNDRY_MATCH_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc10(&self) -> MASK_ERR_F_BNDRY_MATCH_VC10_R { + MASK_ERR_F_BNDRY_MATCH_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc11(&self) -> MASK_ERR_F_BNDRY_MATCH_VC11_R { + MASK_ERR_F_BNDRY_MATCH_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc12(&self) -> MASK_ERR_F_BNDRY_MATCH_VC12_R { + MASK_ERR_F_BNDRY_MATCH_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc13(&self) -> MASK_ERR_F_BNDRY_MATCH_VC13_R { + MASK_ERR_F_BNDRY_MATCH_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc14(&self) -> MASK_ERR_F_BNDRY_MATCH_VC14_R { + MASK_ERR_F_BNDRY_MATCH_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn mask_err_f_bndry_match_vc15(&self) -> MASK_ERR_F_BNDRY_MATCH_VC15_R { + MASK_ERR_F_BNDRY_MATCH_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_MSK_BNDRY_FRAME_FATAL") + .field( + "mask_err_f_bndry_match_vc0", + &format_args!("{}", self.mask_err_f_bndry_match_vc0().bit()), + ) + .field( + "mask_err_f_bndry_match_vc1", + &format_args!("{}", self.mask_err_f_bndry_match_vc1().bit()), + ) + .field( + "mask_err_f_bndry_match_vc2", + &format_args!("{}", self.mask_err_f_bndry_match_vc2().bit()), + ) + .field( + "mask_err_f_bndry_match_vc3", + &format_args!("{}", self.mask_err_f_bndry_match_vc3().bit()), + ) + .field( + "mask_err_f_bndry_match_vc4", + &format_args!("{}", self.mask_err_f_bndry_match_vc4().bit()), + ) + .field( + "mask_err_f_bndry_match_vc5", + &format_args!("{}", self.mask_err_f_bndry_match_vc5().bit()), + ) + .field( + "mask_err_f_bndry_match_vc6", + &format_args!("{}", self.mask_err_f_bndry_match_vc6().bit()), + ) + .field( + "mask_err_f_bndry_match_vc7", + &format_args!("{}", self.mask_err_f_bndry_match_vc7().bit()), + ) + .field( + "mask_err_f_bndry_match_vc8", + &format_args!("{}", self.mask_err_f_bndry_match_vc8().bit()), + ) + .field( + "mask_err_f_bndry_match_vc9", + &format_args!("{}", self.mask_err_f_bndry_match_vc9().bit()), + ) + .field( + "mask_err_f_bndry_match_vc10", + &format_args!("{}", self.mask_err_f_bndry_match_vc10().bit()), + ) + .field( + "mask_err_f_bndry_match_vc11", + &format_args!("{}", self.mask_err_f_bndry_match_vc11().bit()), + ) + .field( + "mask_err_f_bndry_match_vc12", + &format_args!("{}", self.mask_err_f_bndry_match_vc12().bit()), + ) + .field( + "mask_err_f_bndry_match_vc13", + &format_args!("{}", self.mask_err_f_bndry_match_vc13().bit()), + ) + .field( + "mask_err_f_bndry_match_vc14", + &format_args!("{}", self.mask_err_f_bndry_match_vc14().bit()), + ) + .field( + "mask_err_f_bndry_match_vc15", + &format_args!("{}", self.mask_err_f_bndry_match_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc0( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC0_W { + MASK_ERR_F_BNDRY_MATCH_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc1( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC1_W { + MASK_ERR_F_BNDRY_MATCH_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc2( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC2_W { + MASK_ERR_F_BNDRY_MATCH_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc3( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC3_W { + MASK_ERR_F_BNDRY_MATCH_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc4( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC4_W { + MASK_ERR_F_BNDRY_MATCH_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc5( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC5_W { + MASK_ERR_F_BNDRY_MATCH_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc6( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC6_W { + MASK_ERR_F_BNDRY_MATCH_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc7( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC7_W { + MASK_ERR_F_BNDRY_MATCH_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc8( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC8_W { + MASK_ERR_F_BNDRY_MATCH_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc9( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC9_W { + MASK_ERR_F_BNDRY_MATCH_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc10( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC10_W { + MASK_ERR_F_BNDRY_MATCH_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc11( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC11_W { + MASK_ERR_F_BNDRY_MATCH_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc12( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC12_W { + MASK_ERR_F_BNDRY_MATCH_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc13( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC13_W { + MASK_ERR_F_BNDRY_MATCH_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc14( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC14_W { + MASK_ERR_F_BNDRY_MATCH_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_bndry_match_vc15( + &mut self, + ) -> MASK_ERR_F_BNDRY_MATCH_VC15_W { + MASK_ERR_F_BNDRY_MATCH_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_bndry_frame_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_bndry_frame_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_MSK_BNDRY_FRAME_FATAL_SPEC; +impl crate::RegisterSpec for INT_MSK_BNDRY_FRAME_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_msk_bndry_frame_fatal::R`](R) reader structure"] +impl crate::Readable for INT_MSK_BNDRY_FRAME_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_msk_bndry_frame_fatal::W`](W) writer structure"] +impl crate::Writable for INT_MSK_BNDRY_FRAME_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_MSK_BNDRY_FRAME_FATAL to value 0"] +impl crate::Resettable for INT_MSK_BNDRY_FRAME_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_msk_crc_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_crc_frame_fatal.rs new file mode 100644 index 0000000000..44f1b62272 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_msk_crc_frame_fatal.rs @@ -0,0 +1,383 @@ +#[doc = "Register `INT_MSK_CRC_FRAME_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MSK_CRC_FRAME_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC0` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC0_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC0` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC1` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC1_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC1` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC2` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC2_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC2` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC3` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC3_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC3` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC4` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC4_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC4` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC5` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC5_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC5` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC6` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC6_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC6` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC7` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC7_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC7` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC8` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC8_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC8` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC9` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC9_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC9` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC10` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC10_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC10` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC11` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC11_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC11` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC12` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC12_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC12` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC13` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC13_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC13` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC14` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC14_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC14` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC15` reader - NA"] +pub type MASK_ERR_FRAME_DATA_VC15_R = crate::BitReader; +#[doc = "Field `MASK_ERR_FRAME_DATA_VC15` writer - NA"] +pub type MASK_ERR_FRAME_DATA_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc0(&self) -> MASK_ERR_FRAME_DATA_VC0_R { + MASK_ERR_FRAME_DATA_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc1(&self) -> MASK_ERR_FRAME_DATA_VC1_R { + MASK_ERR_FRAME_DATA_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc2(&self) -> MASK_ERR_FRAME_DATA_VC2_R { + MASK_ERR_FRAME_DATA_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc3(&self) -> MASK_ERR_FRAME_DATA_VC3_R { + MASK_ERR_FRAME_DATA_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc4(&self) -> MASK_ERR_FRAME_DATA_VC4_R { + MASK_ERR_FRAME_DATA_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc5(&self) -> MASK_ERR_FRAME_DATA_VC5_R { + MASK_ERR_FRAME_DATA_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc6(&self) -> MASK_ERR_FRAME_DATA_VC6_R { + MASK_ERR_FRAME_DATA_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc7(&self) -> MASK_ERR_FRAME_DATA_VC7_R { + MASK_ERR_FRAME_DATA_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc8(&self) -> MASK_ERR_FRAME_DATA_VC8_R { + MASK_ERR_FRAME_DATA_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc9(&self) -> MASK_ERR_FRAME_DATA_VC9_R { + MASK_ERR_FRAME_DATA_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc10(&self) -> MASK_ERR_FRAME_DATA_VC10_R { + MASK_ERR_FRAME_DATA_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc11(&self) -> MASK_ERR_FRAME_DATA_VC11_R { + MASK_ERR_FRAME_DATA_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc12(&self) -> MASK_ERR_FRAME_DATA_VC12_R { + MASK_ERR_FRAME_DATA_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc13(&self) -> MASK_ERR_FRAME_DATA_VC13_R { + MASK_ERR_FRAME_DATA_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc14(&self) -> MASK_ERR_FRAME_DATA_VC14_R { + MASK_ERR_FRAME_DATA_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn mask_err_frame_data_vc15(&self) -> MASK_ERR_FRAME_DATA_VC15_R { + MASK_ERR_FRAME_DATA_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_MSK_CRC_FRAME_FATAL") + .field( + "mask_err_frame_data_vc0", + &format_args!("{}", self.mask_err_frame_data_vc0().bit()), + ) + .field( + "mask_err_frame_data_vc1", + &format_args!("{}", self.mask_err_frame_data_vc1().bit()), + ) + .field( + "mask_err_frame_data_vc2", + &format_args!("{}", self.mask_err_frame_data_vc2().bit()), + ) + .field( + "mask_err_frame_data_vc3", + &format_args!("{}", self.mask_err_frame_data_vc3().bit()), + ) + .field( + "mask_err_frame_data_vc4", + &format_args!("{}", self.mask_err_frame_data_vc4().bit()), + ) + .field( + "mask_err_frame_data_vc5", + &format_args!("{}", self.mask_err_frame_data_vc5().bit()), + ) + .field( + "mask_err_frame_data_vc6", + &format_args!("{}", self.mask_err_frame_data_vc6().bit()), + ) + .field( + "mask_err_frame_data_vc7", + &format_args!("{}", self.mask_err_frame_data_vc7().bit()), + ) + .field( + "mask_err_frame_data_vc8", + &format_args!("{}", self.mask_err_frame_data_vc8().bit()), + ) + .field( + "mask_err_frame_data_vc9", + &format_args!("{}", self.mask_err_frame_data_vc9().bit()), + ) + .field( + "mask_err_frame_data_vc10", + &format_args!("{}", self.mask_err_frame_data_vc10().bit()), + ) + .field( + "mask_err_frame_data_vc11", + &format_args!("{}", self.mask_err_frame_data_vc11().bit()), + ) + .field( + "mask_err_frame_data_vc12", + &format_args!("{}", self.mask_err_frame_data_vc12().bit()), + ) + .field( + "mask_err_frame_data_vc13", + &format_args!("{}", self.mask_err_frame_data_vc13().bit()), + ) + .field( + "mask_err_frame_data_vc14", + &format_args!("{}", self.mask_err_frame_data_vc14().bit()), + ) + .field( + "mask_err_frame_data_vc15", + &format_args!("{}", self.mask_err_frame_data_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc0( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC0_W { + MASK_ERR_FRAME_DATA_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc1( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC1_W { + MASK_ERR_FRAME_DATA_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc2( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC2_W { + MASK_ERR_FRAME_DATA_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc3( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC3_W { + MASK_ERR_FRAME_DATA_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc4( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC4_W { + MASK_ERR_FRAME_DATA_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc5( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC5_W { + MASK_ERR_FRAME_DATA_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc6( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC6_W { + MASK_ERR_FRAME_DATA_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc7( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC7_W { + MASK_ERR_FRAME_DATA_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc8( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC8_W { + MASK_ERR_FRAME_DATA_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc9( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC9_W { + MASK_ERR_FRAME_DATA_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc10( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC10_W { + MASK_ERR_FRAME_DATA_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc11( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC11_W { + MASK_ERR_FRAME_DATA_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc12( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC12_W { + MASK_ERR_FRAME_DATA_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc13( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC13_W { + MASK_ERR_FRAME_DATA_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc14( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC14_W { + MASK_ERR_FRAME_DATA_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_frame_data_vc15( + &mut self, + ) -> MASK_ERR_FRAME_DATA_VC15_W { + MASK_ERR_FRAME_DATA_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_crc_frame_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_crc_frame_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_MSK_CRC_FRAME_FATAL_SPEC; +impl crate::RegisterSpec for INT_MSK_CRC_FRAME_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_msk_crc_frame_fatal::R`](R) reader structure"] +impl crate::Readable for INT_MSK_CRC_FRAME_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_msk_crc_frame_fatal::W`](W) writer structure"] +impl crate::Writable for INT_MSK_CRC_FRAME_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_MSK_CRC_FRAME_FATAL to value 0"] +impl crate::Resettable for INT_MSK_CRC_FRAME_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_msk_data_id.rs b/esp32p4/src/mipi_csi_host/int_msk_data_id.rs new file mode 100644 index 0000000000..c53da61a34 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_msk_data_id.rs @@ -0,0 +1,351 @@ +#[doc = "Register `INT_MSK_DATA_ID` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MSK_DATA_ID` writer"] +pub type W = crate::W; +#[doc = "Field `MASK_ERR_ID_VC0` reader - NA"] +pub type MASK_ERR_ID_VC0_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC0` writer - NA"] +pub type MASK_ERR_ID_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC1` reader - NA"] +pub type MASK_ERR_ID_VC1_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC1` writer - NA"] +pub type MASK_ERR_ID_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC2` reader - NA"] +pub type MASK_ERR_ID_VC2_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC2` writer - NA"] +pub type MASK_ERR_ID_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC3` reader - NA"] +pub type MASK_ERR_ID_VC3_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC3` writer - NA"] +pub type MASK_ERR_ID_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC4` reader - NA"] +pub type MASK_ERR_ID_VC4_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC4` writer - NA"] +pub type MASK_ERR_ID_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC5` reader - NA"] +pub type MASK_ERR_ID_VC5_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC5` writer - NA"] +pub type MASK_ERR_ID_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC6` reader - NA"] +pub type MASK_ERR_ID_VC6_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC6` writer - NA"] +pub type MASK_ERR_ID_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC7` reader - NA"] +pub type MASK_ERR_ID_VC7_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC7` writer - NA"] +pub type MASK_ERR_ID_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC8` reader - NA"] +pub type MASK_ERR_ID_VC8_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC8` writer - NA"] +pub type MASK_ERR_ID_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC9` reader - NA"] +pub type MASK_ERR_ID_VC9_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC9` writer - NA"] +pub type MASK_ERR_ID_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC10` reader - NA"] +pub type MASK_ERR_ID_VC10_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC10` writer - NA"] +pub type MASK_ERR_ID_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC11` reader - NA"] +pub type MASK_ERR_ID_VC11_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC11` writer - NA"] +pub type MASK_ERR_ID_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC12` reader - NA"] +pub type MASK_ERR_ID_VC12_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC12` writer - NA"] +pub type MASK_ERR_ID_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC13` reader - NA"] +pub type MASK_ERR_ID_VC13_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC13` writer - NA"] +pub type MASK_ERR_ID_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC14` reader - NA"] +pub type MASK_ERR_ID_VC14_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC14` writer - NA"] +pub type MASK_ERR_ID_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ID_VC15` reader - NA"] +pub type MASK_ERR_ID_VC15_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ID_VC15` writer - NA"] +pub type MASK_ERR_ID_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn mask_err_id_vc0(&self) -> MASK_ERR_ID_VC0_R { + MASK_ERR_ID_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn mask_err_id_vc1(&self) -> MASK_ERR_ID_VC1_R { + MASK_ERR_ID_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn mask_err_id_vc2(&self) -> MASK_ERR_ID_VC2_R { + MASK_ERR_ID_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn mask_err_id_vc3(&self) -> MASK_ERR_ID_VC3_R { + MASK_ERR_ID_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn mask_err_id_vc4(&self) -> MASK_ERR_ID_VC4_R { + MASK_ERR_ID_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn mask_err_id_vc5(&self) -> MASK_ERR_ID_VC5_R { + MASK_ERR_ID_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn mask_err_id_vc6(&self) -> MASK_ERR_ID_VC6_R { + MASK_ERR_ID_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn mask_err_id_vc7(&self) -> MASK_ERR_ID_VC7_R { + MASK_ERR_ID_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn mask_err_id_vc8(&self) -> MASK_ERR_ID_VC8_R { + MASK_ERR_ID_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn mask_err_id_vc9(&self) -> MASK_ERR_ID_VC9_R { + MASK_ERR_ID_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn mask_err_id_vc10(&self) -> MASK_ERR_ID_VC10_R { + MASK_ERR_ID_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn mask_err_id_vc11(&self) -> MASK_ERR_ID_VC11_R { + MASK_ERR_ID_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn mask_err_id_vc12(&self) -> MASK_ERR_ID_VC12_R { + MASK_ERR_ID_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn mask_err_id_vc13(&self) -> MASK_ERR_ID_VC13_R { + MASK_ERR_ID_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn mask_err_id_vc14(&self) -> MASK_ERR_ID_VC14_R { + MASK_ERR_ID_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn mask_err_id_vc15(&self) -> MASK_ERR_ID_VC15_R { + MASK_ERR_ID_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_MSK_DATA_ID") + .field( + "mask_err_id_vc0", + &format_args!("{}", self.mask_err_id_vc0().bit()), + ) + .field( + "mask_err_id_vc1", + &format_args!("{}", self.mask_err_id_vc1().bit()), + ) + .field( + "mask_err_id_vc2", + &format_args!("{}", self.mask_err_id_vc2().bit()), + ) + .field( + "mask_err_id_vc3", + &format_args!("{}", self.mask_err_id_vc3().bit()), + ) + .field( + "mask_err_id_vc4", + &format_args!("{}", self.mask_err_id_vc4().bit()), + ) + .field( + "mask_err_id_vc5", + &format_args!("{}", self.mask_err_id_vc5().bit()), + ) + .field( + "mask_err_id_vc6", + &format_args!("{}", self.mask_err_id_vc6().bit()), + ) + .field( + "mask_err_id_vc7", + &format_args!("{}", self.mask_err_id_vc7().bit()), + ) + .field( + "mask_err_id_vc8", + &format_args!("{}", self.mask_err_id_vc8().bit()), + ) + .field( + "mask_err_id_vc9", + &format_args!("{}", self.mask_err_id_vc9().bit()), + ) + .field( + "mask_err_id_vc10", + &format_args!("{}", self.mask_err_id_vc10().bit()), + ) + .field( + "mask_err_id_vc11", + &format_args!("{}", self.mask_err_id_vc11().bit()), + ) + .field( + "mask_err_id_vc12", + &format_args!("{}", self.mask_err_id_vc12().bit()), + ) + .field( + "mask_err_id_vc13", + &format_args!("{}", self.mask_err_id_vc13().bit()), + ) + .field( + "mask_err_id_vc14", + &format_args!("{}", self.mask_err_id_vc14().bit()), + ) + .field( + "mask_err_id_vc15", + &format_args!("{}", self.mask_err_id_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc0(&mut self) -> MASK_ERR_ID_VC0_W { + MASK_ERR_ID_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc1(&mut self) -> MASK_ERR_ID_VC1_W { + MASK_ERR_ID_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc2(&mut self) -> MASK_ERR_ID_VC2_W { + MASK_ERR_ID_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc3(&mut self) -> MASK_ERR_ID_VC3_W { + MASK_ERR_ID_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc4(&mut self) -> MASK_ERR_ID_VC4_W { + MASK_ERR_ID_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc5(&mut self) -> MASK_ERR_ID_VC5_W { + MASK_ERR_ID_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc6(&mut self) -> MASK_ERR_ID_VC6_W { + MASK_ERR_ID_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc7(&mut self) -> MASK_ERR_ID_VC7_W { + MASK_ERR_ID_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc8(&mut self) -> MASK_ERR_ID_VC8_W { + MASK_ERR_ID_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc9(&mut self) -> MASK_ERR_ID_VC9_W { + MASK_ERR_ID_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc10(&mut self) -> MASK_ERR_ID_VC10_W { + MASK_ERR_ID_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc11(&mut self) -> MASK_ERR_ID_VC11_W { + MASK_ERR_ID_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc12(&mut self) -> MASK_ERR_ID_VC12_W { + MASK_ERR_ID_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc13(&mut self) -> MASK_ERR_ID_VC13_W { + MASK_ERR_ID_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc14(&mut self) -> MASK_ERR_ID_VC14_W { + MASK_ERR_ID_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_id_vc15(&mut self) -> MASK_ERR_ID_VC15_W { + MASK_ERR_ID_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_data_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_data_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_MSK_DATA_ID_SPEC; +impl crate::RegisterSpec for INT_MSK_DATA_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_msk_data_id::R`](R) reader structure"] +impl crate::Readable for INT_MSK_DATA_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_msk_data_id::W`](W) writer structure"] +impl crate::Writable for INT_MSK_DATA_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_MSK_DATA_ID to value 0"] +impl crate::Resettable for INT_MSK_DATA_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_msk_ecc_corrected.rs b/esp32p4/src/mipi_csi_host/int_msk_ecc_corrected.rs new file mode 100644 index 0000000000..e5976e2303 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_msk_ecc_corrected.rs @@ -0,0 +1,383 @@ +#[doc = "Register `INT_MSK_ECC_CORRECTED` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MSK_ECC_CORRECTED` writer"] +pub type W = crate::W; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC0` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC0_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC0` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC1` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC1_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC1` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC2` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC2_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC2` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC3` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC3_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC3` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC4` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC4_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC4` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC5` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC5_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC5` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC6` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC6_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC6` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC7` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC7_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC7` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC8` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC8_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC8` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC9` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC9_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC9` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC10` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC10_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC10` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC11` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC11_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC11` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC12` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC12_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC12` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC13` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC13_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC13` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC14` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC14_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC14` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC15` reader - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC15_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_CORRECTED_VC15` writer - NA"] +pub type MASK_ERR_ECC_CORRECTED_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc0(&self) -> MASK_ERR_ECC_CORRECTED_VC0_R { + MASK_ERR_ECC_CORRECTED_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc1(&self) -> MASK_ERR_ECC_CORRECTED_VC1_R { + MASK_ERR_ECC_CORRECTED_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc2(&self) -> MASK_ERR_ECC_CORRECTED_VC2_R { + MASK_ERR_ECC_CORRECTED_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc3(&self) -> MASK_ERR_ECC_CORRECTED_VC3_R { + MASK_ERR_ECC_CORRECTED_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc4(&self) -> MASK_ERR_ECC_CORRECTED_VC4_R { + MASK_ERR_ECC_CORRECTED_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc5(&self) -> MASK_ERR_ECC_CORRECTED_VC5_R { + MASK_ERR_ECC_CORRECTED_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc6(&self) -> MASK_ERR_ECC_CORRECTED_VC6_R { + MASK_ERR_ECC_CORRECTED_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc7(&self) -> MASK_ERR_ECC_CORRECTED_VC7_R { + MASK_ERR_ECC_CORRECTED_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc8(&self) -> MASK_ERR_ECC_CORRECTED_VC8_R { + MASK_ERR_ECC_CORRECTED_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc9(&self) -> MASK_ERR_ECC_CORRECTED_VC9_R { + MASK_ERR_ECC_CORRECTED_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc10(&self) -> MASK_ERR_ECC_CORRECTED_VC10_R { + MASK_ERR_ECC_CORRECTED_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc11(&self) -> MASK_ERR_ECC_CORRECTED_VC11_R { + MASK_ERR_ECC_CORRECTED_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc12(&self) -> MASK_ERR_ECC_CORRECTED_VC12_R { + MASK_ERR_ECC_CORRECTED_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc13(&self) -> MASK_ERR_ECC_CORRECTED_VC13_R { + MASK_ERR_ECC_CORRECTED_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc14(&self) -> MASK_ERR_ECC_CORRECTED_VC14_R { + MASK_ERR_ECC_CORRECTED_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn mask_err_ecc_corrected_vc15(&self) -> MASK_ERR_ECC_CORRECTED_VC15_R { + MASK_ERR_ECC_CORRECTED_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_MSK_ECC_CORRECTED") + .field( + "mask_err_ecc_corrected_vc0", + &format_args!("{}", self.mask_err_ecc_corrected_vc0().bit()), + ) + .field( + "mask_err_ecc_corrected_vc1", + &format_args!("{}", self.mask_err_ecc_corrected_vc1().bit()), + ) + .field( + "mask_err_ecc_corrected_vc2", + &format_args!("{}", self.mask_err_ecc_corrected_vc2().bit()), + ) + .field( + "mask_err_ecc_corrected_vc3", + &format_args!("{}", self.mask_err_ecc_corrected_vc3().bit()), + ) + .field( + "mask_err_ecc_corrected_vc4", + &format_args!("{}", self.mask_err_ecc_corrected_vc4().bit()), + ) + .field( + "mask_err_ecc_corrected_vc5", + &format_args!("{}", self.mask_err_ecc_corrected_vc5().bit()), + ) + .field( + "mask_err_ecc_corrected_vc6", + &format_args!("{}", self.mask_err_ecc_corrected_vc6().bit()), + ) + .field( + "mask_err_ecc_corrected_vc7", + &format_args!("{}", self.mask_err_ecc_corrected_vc7().bit()), + ) + .field( + "mask_err_ecc_corrected_vc8", + &format_args!("{}", self.mask_err_ecc_corrected_vc8().bit()), + ) + .field( + "mask_err_ecc_corrected_vc9", + &format_args!("{}", self.mask_err_ecc_corrected_vc9().bit()), + ) + .field( + "mask_err_ecc_corrected_vc10", + &format_args!("{}", self.mask_err_ecc_corrected_vc10().bit()), + ) + .field( + "mask_err_ecc_corrected_vc11", + &format_args!("{}", self.mask_err_ecc_corrected_vc11().bit()), + ) + .field( + "mask_err_ecc_corrected_vc12", + &format_args!("{}", self.mask_err_ecc_corrected_vc12().bit()), + ) + .field( + "mask_err_ecc_corrected_vc13", + &format_args!("{}", self.mask_err_ecc_corrected_vc13().bit()), + ) + .field( + "mask_err_ecc_corrected_vc14", + &format_args!("{}", self.mask_err_ecc_corrected_vc14().bit()), + ) + .field( + "mask_err_ecc_corrected_vc15", + &format_args!("{}", self.mask_err_ecc_corrected_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc0( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC0_W { + MASK_ERR_ECC_CORRECTED_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc1( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC1_W { + MASK_ERR_ECC_CORRECTED_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc2( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC2_W { + MASK_ERR_ECC_CORRECTED_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc3( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC3_W { + MASK_ERR_ECC_CORRECTED_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc4( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC4_W { + MASK_ERR_ECC_CORRECTED_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc5( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC5_W { + MASK_ERR_ECC_CORRECTED_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc6( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC6_W { + MASK_ERR_ECC_CORRECTED_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc7( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC7_W { + MASK_ERR_ECC_CORRECTED_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc8( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC8_W { + MASK_ERR_ECC_CORRECTED_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc9( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC9_W { + MASK_ERR_ECC_CORRECTED_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc10( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC10_W { + MASK_ERR_ECC_CORRECTED_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc11( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC11_W { + MASK_ERR_ECC_CORRECTED_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc12( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC12_W { + MASK_ERR_ECC_CORRECTED_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc13( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC13_W { + MASK_ERR_ECC_CORRECTED_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc14( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC14_W { + MASK_ERR_ECC_CORRECTED_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_corrected_vc15( + &mut self, + ) -> MASK_ERR_ECC_CORRECTED_VC15_W { + MASK_ERR_ECC_CORRECTED_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_ecc_corrected::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_ecc_corrected::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_MSK_ECC_CORRECTED_SPEC; +impl crate::RegisterSpec for INT_MSK_ECC_CORRECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_msk_ecc_corrected::R`](R) reader structure"] +impl crate::Readable for INT_MSK_ECC_CORRECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_msk_ecc_corrected::W`](W) writer structure"] +impl crate::Writable for INT_MSK_ECC_CORRECTED_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_MSK_ECC_CORRECTED to value 0"] +impl crate::Resettable for INT_MSK_ECC_CORRECTED_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_msk_phy.rs b/esp32p4/src/mipi_csi_host/int_msk_phy.rs new file mode 100644 index 0000000000..dc62938d8f --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_msk_phy.rs @@ -0,0 +1,123 @@ +#[doc = "Register `INT_MSK_PHY` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MSK_PHY` writer"] +pub type W = crate::W; +#[doc = "Field `MASK_PHY_ERRSOTHS_0` reader - NA"] +pub type MASK_PHY_ERRSOTHS_0_R = crate::BitReader; +#[doc = "Field `MASK_PHY_ERRSOTHS_0` writer - NA"] +pub type MASK_PHY_ERRSOTHS_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_PHY_ERRSOTHS_1` reader - NA"] +pub type MASK_PHY_ERRSOTHS_1_R = crate::BitReader; +#[doc = "Field `MASK_PHY_ERRSOTHS_1` writer - NA"] +pub type MASK_PHY_ERRSOTHS_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_PHY_ERRESC_0` reader - NA"] +pub type MASK_PHY_ERRESC_0_R = crate::BitReader; +#[doc = "Field `MASK_PHY_ERRESC_0` writer - NA"] +pub type MASK_PHY_ERRESC_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_PHY_ERRESC_1` reader - NA"] +pub type MASK_PHY_ERRESC_1_R = crate::BitReader; +#[doc = "Field `MASK_PHY_ERRESC_1` writer - NA"] +pub type MASK_PHY_ERRESC_1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn mask_phy_errsoths_0(&self) -> MASK_PHY_ERRSOTHS_0_R { + MASK_PHY_ERRSOTHS_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn mask_phy_errsoths_1(&self) -> MASK_PHY_ERRSOTHS_1_R { + MASK_PHY_ERRSOTHS_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn mask_phy_erresc_0(&self) -> MASK_PHY_ERRESC_0_R { + MASK_PHY_ERRESC_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn mask_phy_erresc_1(&self) -> MASK_PHY_ERRESC_1_R { + MASK_PHY_ERRESC_1_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_MSK_PHY") + .field( + "mask_phy_errsoths_0", + &format_args!("{}", self.mask_phy_errsoths_0().bit()), + ) + .field( + "mask_phy_errsoths_1", + &format_args!("{}", self.mask_phy_errsoths_1().bit()), + ) + .field( + "mask_phy_erresc_0", + &format_args!("{}", self.mask_phy_erresc_0().bit()), + ) + .field( + "mask_phy_erresc_1", + &format_args!("{}", self.mask_phy_erresc_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_phy_errsoths_0(&mut self) -> MASK_PHY_ERRSOTHS_0_W { + MASK_PHY_ERRSOTHS_0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_phy_errsoths_1(&mut self) -> MASK_PHY_ERRSOTHS_1_W { + MASK_PHY_ERRSOTHS_1_W::new(self, 1) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_phy_erresc_0(&mut self) -> MASK_PHY_ERRESC_0_W { + MASK_PHY_ERRESC_0_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_phy_erresc_1(&mut self) -> MASK_PHY_ERRESC_1_W { + MASK_PHY_ERRESC_1_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_phy::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_phy::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_MSK_PHY_SPEC; +impl crate::RegisterSpec for INT_MSK_PHY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_msk_phy::R`](R) reader structure"] +impl crate::Readable for INT_MSK_PHY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_msk_phy::W`](W) writer structure"] +impl crate::Writable for INT_MSK_PHY_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_MSK_PHY to value 0"] +impl crate::Resettable for INT_MSK_PHY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_msk_phy_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_phy_fatal.rs new file mode 100644 index 0000000000..35f312e13a --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_msk_phy_fatal.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INT_MSK_PHY_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MSK_PHY_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `MASK_PHY_ERRSOTSYNCHS_0` reader - NA"] +pub type MASK_PHY_ERRSOTSYNCHS_0_R = crate::BitReader; +#[doc = "Field `MASK_PHY_ERRSOTSYNCHS_0` writer - NA"] +pub type MASK_PHY_ERRSOTSYNCHS_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_PHY_ERRSOTSYNCHS_1` reader - NA"] +pub type MASK_PHY_ERRSOTSYNCHS_1_R = crate::BitReader; +#[doc = "Field `MASK_PHY_ERRSOTSYNCHS_1` writer - NA"] +pub type MASK_PHY_ERRSOTSYNCHS_1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn mask_phy_errsotsynchs_0(&self) -> MASK_PHY_ERRSOTSYNCHS_0_R { + MASK_PHY_ERRSOTSYNCHS_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn mask_phy_errsotsynchs_1(&self) -> MASK_PHY_ERRSOTSYNCHS_1_R { + MASK_PHY_ERRSOTSYNCHS_1_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_MSK_PHY_FATAL") + .field( + "mask_phy_errsotsynchs_0", + &format_args!("{}", self.mask_phy_errsotsynchs_0().bit()), + ) + .field( + "mask_phy_errsotsynchs_1", + &format_args!("{}", self.mask_phy_errsotsynchs_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_phy_errsotsynchs_0(&mut self) -> MASK_PHY_ERRSOTSYNCHS_0_W { + MASK_PHY_ERRSOTSYNCHS_0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_phy_errsotsynchs_1(&mut self) -> MASK_PHY_ERRSOTSYNCHS_1_W { + MASK_PHY_ERRSOTSYNCHS_1_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_phy_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_phy_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_MSK_PHY_FATAL_SPEC; +impl crate::RegisterSpec for INT_MSK_PHY_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_msk_phy_fatal::R`](R) reader structure"] +impl crate::Readable for INT_MSK_PHY_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_msk_phy_fatal::W`](W) writer structure"] +impl crate::Writable for INT_MSK_PHY_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_MSK_PHY_FATAL to value 0"] +impl crate::Resettable for INT_MSK_PHY_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_msk_pkt_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_pkt_fatal.rs new file mode 100644 index 0000000000..27c8e98212 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_msk_pkt_fatal.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INT_MSK_PKT_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MSK_PKT_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `MASK_ERR_ECC_DOUBLE` reader - NA"] +pub type MASK_ERR_ECC_DOUBLE_R = crate::BitReader; +#[doc = "Field `MASK_ERR_ECC_DOUBLE` writer - NA"] +pub type MASK_ERR_ECC_DOUBLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_SHORTER_PAYLOAD` reader - NA"] +pub type MASK_SHORTER_PAYLOAD_R = crate::BitReader; +#[doc = "Field `MASK_SHORTER_PAYLOAD` writer - NA"] +pub type MASK_SHORTER_PAYLOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn mask_err_ecc_double(&self) -> MASK_ERR_ECC_DOUBLE_R { + MASK_ERR_ECC_DOUBLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn mask_shorter_payload(&self) -> MASK_SHORTER_PAYLOAD_R { + MASK_SHORTER_PAYLOAD_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_MSK_PKT_FATAL") + .field( + "mask_err_ecc_double", + &format_args!("{}", self.mask_err_ecc_double().bit()), + ) + .field( + "mask_shorter_payload", + &format_args!("{}", self.mask_shorter_payload().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_ecc_double(&mut self) -> MASK_ERR_ECC_DOUBLE_W { + MASK_ERR_ECC_DOUBLE_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_shorter_payload(&mut self) -> MASK_SHORTER_PAYLOAD_W { + MASK_SHORTER_PAYLOAD_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_pkt_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_pkt_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_MSK_PKT_FATAL_SPEC; +impl crate::RegisterSpec for INT_MSK_PKT_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_msk_pkt_fatal::R`](R) reader structure"] +impl crate::Readable for INT_MSK_PKT_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_msk_pkt_fatal::W`](W) writer structure"] +impl crate::Writable for INT_MSK_PKT_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_MSK_PKT_FATAL to value 0"] +impl crate::Resettable for INT_MSK_PKT_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_msk_pld_crc_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_pld_crc_fatal.rs new file mode 100644 index 0000000000..f66aefcf2d --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_msk_pld_crc_fatal.rs @@ -0,0 +1,351 @@ +#[doc = "Register `INT_MSK_PLD_CRC_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MSK_PLD_CRC_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `MASK_ERR_CRC_VC0` reader - NA"] +pub type MASK_ERR_CRC_VC0_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC0` writer - NA"] +pub type MASK_ERR_CRC_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC1` reader - NA"] +pub type MASK_ERR_CRC_VC1_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC1` writer - NA"] +pub type MASK_ERR_CRC_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC2` reader - NA"] +pub type MASK_ERR_CRC_VC2_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC2` writer - NA"] +pub type MASK_ERR_CRC_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC3` reader - NA"] +pub type MASK_ERR_CRC_VC3_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC3` writer - NA"] +pub type MASK_ERR_CRC_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC4` reader - NA"] +pub type MASK_ERR_CRC_VC4_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC4` writer - NA"] +pub type MASK_ERR_CRC_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC5` reader - NA"] +pub type MASK_ERR_CRC_VC5_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC5` writer - NA"] +pub type MASK_ERR_CRC_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC6` reader - NA"] +pub type MASK_ERR_CRC_VC6_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC6` writer - NA"] +pub type MASK_ERR_CRC_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC7` reader - NA"] +pub type MASK_ERR_CRC_VC7_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC7` writer - NA"] +pub type MASK_ERR_CRC_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC8` reader - NA"] +pub type MASK_ERR_CRC_VC8_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC8` writer - NA"] +pub type MASK_ERR_CRC_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC9` reader - NA"] +pub type MASK_ERR_CRC_VC9_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC9` writer - NA"] +pub type MASK_ERR_CRC_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC10` reader - NA"] +pub type MASK_ERR_CRC_VC10_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC10` writer - NA"] +pub type MASK_ERR_CRC_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC11` reader - NA"] +pub type MASK_ERR_CRC_VC11_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC11` writer - NA"] +pub type MASK_ERR_CRC_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC12` reader - NA"] +pub type MASK_ERR_CRC_VC12_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC12` writer - NA"] +pub type MASK_ERR_CRC_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC13` reader - NA"] +pub type MASK_ERR_CRC_VC13_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC13` writer - NA"] +pub type MASK_ERR_CRC_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC14` reader - NA"] +pub type MASK_ERR_CRC_VC14_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC14` writer - NA"] +pub type MASK_ERR_CRC_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_CRC_VC15` reader - NA"] +pub type MASK_ERR_CRC_VC15_R = crate::BitReader; +#[doc = "Field `MASK_ERR_CRC_VC15` writer - NA"] +pub type MASK_ERR_CRC_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc0(&self) -> MASK_ERR_CRC_VC0_R { + MASK_ERR_CRC_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc1(&self) -> MASK_ERR_CRC_VC1_R { + MASK_ERR_CRC_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc2(&self) -> MASK_ERR_CRC_VC2_R { + MASK_ERR_CRC_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc3(&self) -> MASK_ERR_CRC_VC3_R { + MASK_ERR_CRC_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc4(&self) -> MASK_ERR_CRC_VC4_R { + MASK_ERR_CRC_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc5(&self) -> MASK_ERR_CRC_VC5_R { + MASK_ERR_CRC_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc6(&self) -> MASK_ERR_CRC_VC6_R { + MASK_ERR_CRC_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc7(&self) -> MASK_ERR_CRC_VC7_R { + MASK_ERR_CRC_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc8(&self) -> MASK_ERR_CRC_VC8_R { + MASK_ERR_CRC_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc9(&self) -> MASK_ERR_CRC_VC9_R { + MASK_ERR_CRC_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc10(&self) -> MASK_ERR_CRC_VC10_R { + MASK_ERR_CRC_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc11(&self) -> MASK_ERR_CRC_VC11_R { + MASK_ERR_CRC_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc12(&self) -> MASK_ERR_CRC_VC12_R { + MASK_ERR_CRC_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc13(&self) -> MASK_ERR_CRC_VC13_R { + MASK_ERR_CRC_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc14(&self) -> MASK_ERR_CRC_VC14_R { + MASK_ERR_CRC_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn mask_err_crc_vc15(&self) -> MASK_ERR_CRC_VC15_R { + MASK_ERR_CRC_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_MSK_PLD_CRC_FATAL") + .field( + "mask_err_crc_vc0", + &format_args!("{}", self.mask_err_crc_vc0().bit()), + ) + .field( + "mask_err_crc_vc1", + &format_args!("{}", self.mask_err_crc_vc1().bit()), + ) + .field( + "mask_err_crc_vc2", + &format_args!("{}", self.mask_err_crc_vc2().bit()), + ) + .field( + "mask_err_crc_vc3", + &format_args!("{}", self.mask_err_crc_vc3().bit()), + ) + .field( + "mask_err_crc_vc4", + &format_args!("{}", self.mask_err_crc_vc4().bit()), + ) + .field( + "mask_err_crc_vc5", + &format_args!("{}", self.mask_err_crc_vc5().bit()), + ) + .field( + "mask_err_crc_vc6", + &format_args!("{}", self.mask_err_crc_vc6().bit()), + ) + .field( + "mask_err_crc_vc7", + &format_args!("{}", self.mask_err_crc_vc7().bit()), + ) + .field( + "mask_err_crc_vc8", + &format_args!("{}", self.mask_err_crc_vc8().bit()), + ) + .field( + "mask_err_crc_vc9", + &format_args!("{}", self.mask_err_crc_vc9().bit()), + ) + .field( + "mask_err_crc_vc10", + &format_args!("{}", self.mask_err_crc_vc10().bit()), + ) + .field( + "mask_err_crc_vc11", + &format_args!("{}", self.mask_err_crc_vc11().bit()), + ) + .field( + "mask_err_crc_vc12", + &format_args!("{}", self.mask_err_crc_vc12().bit()), + ) + .field( + "mask_err_crc_vc13", + &format_args!("{}", self.mask_err_crc_vc13().bit()), + ) + .field( + "mask_err_crc_vc14", + &format_args!("{}", self.mask_err_crc_vc14().bit()), + ) + .field( + "mask_err_crc_vc15", + &format_args!("{}", self.mask_err_crc_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc0(&mut self) -> MASK_ERR_CRC_VC0_W { + MASK_ERR_CRC_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc1(&mut self) -> MASK_ERR_CRC_VC1_W { + MASK_ERR_CRC_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc2(&mut self) -> MASK_ERR_CRC_VC2_W { + MASK_ERR_CRC_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc3(&mut self) -> MASK_ERR_CRC_VC3_W { + MASK_ERR_CRC_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc4(&mut self) -> MASK_ERR_CRC_VC4_W { + MASK_ERR_CRC_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc5(&mut self) -> MASK_ERR_CRC_VC5_W { + MASK_ERR_CRC_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc6(&mut self) -> MASK_ERR_CRC_VC6_W { + MASK_ERR_CRC_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc7(&mut self) -> MASK_ERR_CRC_VC7_W { + MASK_ERR_CRC_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc8(&mut self) -> MASK_ERR_CRC_VC8_W { + MASK_ERR_CRC_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc9(&mut self) -> MASK_ERR_CRC_VC9_W { + MASK_ERR_CRC_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc10(&mut self) -> MASK_ERR_CRC_VC10_W { + MASK_ERR_CRC_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc11(&mut self) -> MASK_ERR_CRC_VC11_W { + MASK_ERR_CRC_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc12(&mut self) -> MASK_ERR_CRC_VC12_W { + MASK_ERR_CRC_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc13(&mut self) -> MASK_ERR_CRC_VC13_W { + MASK_ERR_CRC_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc14(&mut self) -> MASK_ERR_CRC_VC14_W { + MASK_ERR_CRC_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_crc_vc15(&mut self) -> MASK_ERR_CRC_VC15_W { + MASK_ERR_CRC_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_pld_crc_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_pld_crc_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_MSK_PLD_CRC_FATAL_SPEC; +impl crate::RegisterSpec for INT_MSK_PLD_CRC_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_msk_pld_crc_fatal::R`](R) reader structure"] +impl crate::Readable for INT_MSK_PLD_CRC_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_msk_pld_crc_fatal::W`](W) writer structure"] +impl crate::Writable for INT_MSK_PLD_CRC_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_MSK_PLD_CRC_FATAL to value 0"] +impl crate::Resettable for INT_MSK_PLD_CRC_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_msk_seq_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_seq_frame_fatal.rs new file mode 100644 index 0000000000..9548cf9a1a --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_msk_seq_frame_fatal.rs @@ -0,0 +1,351 @@ +#[doc = "Register `INT_MSK_SEQ_FRAME_FATAL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MSK_SEQ_FRAME_FATAL` writer"] +pub type W = crate::W; +#[doc = "Field `MASK_ERR_F_SEQ_VC0` reader - NA"] +pub type MASK_ERR_F_SEQ_VC0_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC0` writer - NA"] +pub type MASK_ERR_F_SEQ_VC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC1` reader - NA"] +pub type MASK_ERR_F_SEQ_VC1_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC1` writer - NA"] +pub type MASK_ERR_F_SEQ_VC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC2` reader - NA"] +pub type MASK_ERR_F_SEQ_VC2_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC2` writer - NA"] +pub type MASK_ERR_F_SEQ_VC2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC3` reader - NA"] +pub type MASK_ERR_F_SEQ_VC3_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC3` writer - NA"] +pub type MASK_ERR_F_SEQ_VC3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC4` reader - NA"] +pub type MASK_ERR_F_SEQ_VC4_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC4` writer - NA"] +pub type MASK_ERR_F_SEQ_VC4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC5` reader - NA"] +pub type MASK_ERR_F_SEQ_VC5_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC5` writer - NA"] +pub type MASK_ERR_F_SEQ_VC5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC6` reader - NA"] +pub type MASK_ERR_F_SEQ_VC6_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC6` writer - NA"] +pub type MASK_ERR_F_SEQ_VC6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC7` reader - NA"] +pub type MASK_ERR_F_SEQ_VC7_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC7` writer - NA"] +pub type MASK_ERR_F_SEQ_VC7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC8` reader - NA"] +pub type MASK_ERR_F_SEQ_VC8_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC8` writer - NA"] +pub type MASK_ERR_F_SEQ_VC8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC9` reader - NA"] +pub type MASK_ERR_F_SEQ_VC9_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC9` writer - NA"] +pub type MASK_ERR_F_SEQ_VC9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC10` reader - NA"] +pub type MASK_ERR_F_SEQ_VC10_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC10` writer - NA"] +pub type MASK_ERR_F_SEQ_VC10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC11` reader - NA"] +pub type MASK_ERR_F_SEQ_VC11_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC11` writer - NA"] +pub type MASK_ERR_F_SEQ_VC11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC12` reader - NA"] +pub type MASK_ERR_F_SEQ_VC12_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC12` writer - NA"] +pub type MASK_ERR_F_SEQ_VC12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC13` reader - NA"] +pub type MASK_ERR_F_SEQ_VC13_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC13` writer - NA"] +pub type MASK_ERR_F_SEQ_VC13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC14` reader - NA"] +pub type MASK_ERR_F_SEQ_VC14_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC14` writer - NA"] +pub type MASK_ERR_F_SEQ_VC14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ERR_F_SEQ_VC15` reader - NA"] +pub type MASK_ERR_F_SEQ_VC15_R = crate::BitReader; +#[doc = "Field `MASK_ERR_F_SEQ_VC15` writer - NA"] +pub type MASK_ERR_F_SEQ_VC15_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc0(&self) -> MASK_ERR_F_SEQ_VC0_R { + MASK_ERR_F_SEQ_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc1(&self) -> MASK_ERR_F_SEQ_VC1_R { + MASK_ERR_F_SEQ_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc2(&self) -> MASK_ERR_F_SEQ_VC2_R { + MASK_ERR_F_SEQ_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc3(&self) -> MASK_ERR_F_SEQ_VC3_R { + MASK_ERR_F_SEQ_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc4(&self) -> MASK_ERR_F_SEQ_VC4_R { + MASK_ERR_F_SEQ_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc5(&self) -> MASK_ERR_F_SEQ_VC5_R { + MASK_ERR_F_SEQ_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc6(&self) -> MASK_ERR_F_SEQ_VC6_R { + MASK_ERR_F_SEQ_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc7(&self) -> MASK_ERR_F_SEQ_VC7_R { + MASK_ERR_F_SEQ_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc8(&self) -> MASK_ERR_F_SEQ_VC8_R { + MASK_ERR_F_SEQ_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc9(&self) -> MASK_ERR_F_SEQ_VC9_R { + MASK_ERR_F_SEQ_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc10(&self) -> MASK_ERR_F_SEQ_VC10_R { + MASK_ERR_F_SEQ_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc11(&self) -> MASK_ERR_F_SEQ_VC11_R { + MASK_ERR_F_SEQ_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc12(&self) -> MASK_ERR_F_SEQ_VC12_R { + MASK_ERR_F_SEQ_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc13(&self) -> MASK_ERR_F_SEQ_VC13_R { + MASK_ERR_F_SEQ_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc14(&self) -> MASK_ERR_F_SEQ_VC14_R { + MASK_ERR_F_SEQ_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn mask_err_f_seq_vc15(&self) -> MASK_ERR_F_SEQ_VC15_R { + MASK_ERR_F_SEQ_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_MSK_SEQ_FRAME_FATAL") + .field( + "mask_err_f_seq_vc0", + &format_args!("{}", self.mask_err_f_seq_vc0().bit()), + ) + .field( + "mask_err_f_seq_vc1", + &format_args!("{}", self.mask_err_f_seq_vc1().bit()), + ) + .field( + "mask_err_f_seq_vc2", + &format_args!("{}", self.mask_err_f_seq_vc2().bit()), + ) + .field( + "mask_err_f_seq_vc3", + &format_args!("{}", self.mask_err_f_seq_vc3().bit()), + ) + .field( + "mask_err_f_seq_vc4", + &format_args!("{}", self.mask_err_f_seq_vc4().bit()), + ) + .field( + "mask_err_f_seq_vc5", + &format_args!("{}", self.mask_err_f_seq_vc5().bit()), + ) + .field( + "mask_err_f_seq_vc6", + &format_args!("{}", self.mask_err_f_seq_vc6().bit()), + ) + .field( + "mask_err_f_seq_vc7", + &format_args!("{}", self.mask_err_f_seq_vc7().bit()), + ) + .field( + "mask_err_f_seq_vc8", + &format_args!("{}", self.mask_err_f_seq_vc8().bit()), + ) + .field( + "mask_err_f_seq_vc9", + &format_args!("{}", self.mask_err_f_seq_vc9().bit()), + ) + .field( + "mask_err_f_seq_vc10", + &format_args!("{}", self.mask_err_f_seq_vc10().bit()), + ) + .field( + "mask_err_f_seq_vc11", + &format_args!("{}", self.mask_err_f_seq_vc11().bit()), + ) + .field( + "mask_err_f_seq_vc12", + &format_args!("{}", self.mask_err_f_seq_vc12().bit()), + ) + .field( + "mask_err_f_seq_vc13", + &format_args!("{}", self.mask_err_f_seq_vc13().bit()), + ) + .field( + "mask_err_f_seq_vc14", + &format_args!("{}", self.mask_err_f_seq_vc14().bit()), + ) + .field( + "mask_err_f_seq_vc15", + &format_args!("{}", self.mask_err_f_seq_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc0(&mut self) -> MASK_ERR_F_SEQ_VC0_W { + MASK_ERR_F_SEQ_VC0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc1(&mut self) -> MASK_ERR_F_SEQ_VC1_W { + MASK_ERR_F_SEQ_VC1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc2(&mut self) -> MASK_ERR_F_SEQ_VC2_W { + MASK_ERR_F_SEQ_VC2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc3(&mut self) -> MASK_ERR_F_SEQ_VC3_W { + MASK_ERR_F_SEQ_VC3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc4(&mut self) -> MASK_ERR_F_SEQ_VC4_W { + MASK_ERR_F_SEQ_VC4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc5(&mut self) -> MASK_ERR_F_SEQ_VC5_W { + MASK_ERR_F_SEQ_VC5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc6(&mut self) -> MASK_ERR_F_SEQ_VC6_W { + MASK_ERR_F_SEQ_VC6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc7(&mut self) -> MASK_ERR_F_SEQ_VC7_W { + MASK_ERR_F_SEQ_VC7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc8(&mut self) -> MASK_ERR_F_SEQ_VC8_W { + MASK_ERR_F_SEQ_VC8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc9(&mut self) -> MASK_ERR_F_SEQ_VC9_W { + MASK_ERR_F_SEQ_VC9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc10(&mut self) -> MASK_ERR_F_SEQ_VC10_W { + MASK_ERR_F_SEQ_VC10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc11(&mut self) -> MASK_ERR_F_SEQ_VC11_W { + MASK_ERR_F_SEQ_VC11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc12(&mut self) -> MASK_ERR_F_SEQ_VC12_W { + MASK_ERR_F_SEQ_VC12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc13(&mut self) -> MASK_ERR_F_SEQ_VC13_W { + MASK_ERR_F_SEQ_VC13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc14(&mut self) -> MASK_ERR_F_SEQ_VC14_W { + MASK_ERR_F_SEQ_VC14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_err_f_seq_vc15(&mut self) -> MASK_ERR_F_SEQ_VC15_W { + MASK_ERR_F_SEQ_VC15_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk_seq_frame_fatal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk_seq_frame_fatal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_MSK_SEQ_FRAME_FATAL_SPEC; +impl crate::RegisterSpec for INT_MSK_SEQ_FRAME_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_msk_seq_frame_fatal::R`](R) reader structure"] +impl crate::Readable for INT_MSK_SEQ_FRAME_FATAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_msk_seq_frame_fatal::W`](W) writer structure"] +impl crate::Writable for INT_MSK_SEQ_FRAME_FATAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_MSK_SEQ_FRAME_FATAL to value 0"] +impl crate::Resettable for INT_MSK_SEQ_FRAME_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_st_bndry_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_bndry_frame_fatal.rs new file mode 100644 index 0000000000..6dad6773a8 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_st_bndry_frame_fatal.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INT_ST_BNDRY_FRAME_FATAL` reader"] +pub type R = crate::R; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC0` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC0_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC1` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC1_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC2` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC2_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC3` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC3_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC4` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC4_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC5` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC5_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC6` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC6_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC7` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC7_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC8` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC8_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC9` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC9_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC10` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC10_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC11` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC11_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC12` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC12_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC13` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC13_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC14` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC14_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_BNDRY_MATCH_VC15` reader - NA"] +pub type ST_ERR_F_BNDRY_MATCH_VC15_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc0(&self) -> ST_ERR_F_BNDRY_MATCH_VC0_R { + ST_ERR_F_BNDRY_MATCH_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc1(&self) -> ST_ERR_F_BNDRY_MATCH_VC1_R { + ST_ERR_F_BNDRY_MATCH_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc2(&self) -> ST_ERR_F_BNDRY_MATCH_VC2_R { + ST_ERR_F_BNDRY_MATCH_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc3(&self) -> ST_ERR_F_BNDRY_MATCH_VC3_R { + ST_ERR_F_BNDRY_MATCH_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc4(&self) -> ST_ERR_F_BNDRY_MATCH_VC4_R { + ST_ERR_F_BNDRY_MATCH_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc5(&self) -> ST_ERR_F_BNDRY_MATCH_VC5_R { + ST_ERR_F_BNDRY_MATCH_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc6(&self) -> ST_ERR_F_BNDRY_MATCH_VC6_R { + ST_ERR_F_BNDRY_MATCH_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc7(&self) -> ST_ERR_F_BNDRY_MATCH_VC7_R { + ST_ERR_F_BNDRY_MATCH_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc8(&self) -> ST_ERR_F_BNDRY_MATCH_VC8_R { + ST_ERR_F_BNDRY_MATCH_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc9(&self) -> ST_ERR_F_BNDRY_MATCH_VC9_R { + ST_ERR_F_BNDRY_MATCH_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc10(&self) -> ST_ERR_F_BNDRY_MATCH_VC10_R { + ST_ERR_F_BNDRY_MATCH_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc11(&self) -> ST_ERR_F_BNDRY_MATCH_VC11_R { + ST_ERR_F_BNDRY_MATCH_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc12(&self) -> ST_ERR_F_BNDRY_MATCH_VC12_R { + ST_ERR_F_BNDRY_MATCH_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc13(&self) -> ST_ERR_F_BNDRY_MATCH_VC13_R { + ST_ERR_F_BNDRY_MATCH_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc14(&self) -> ST_ERR_F_BNDRY_MATCH_VC14_R { + ST_ERR_F_BNDRY_MATCH_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn st_err_f_bndry_match_vc15(&self) -> ST_ERR_F_BNDRY_MATCH_VC15_R { + ST_ERR_F_BNDRY_MATCH_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_BNDRY_FRAME_FATAL") + .field( + "st_err_f_bndry_match_vc0", + &format_args!("{}", self.st_err_f_bndry_match_vc0().bit()), + ) + .field( + "st_err_f_bndry_match_vc1", + &format_args!("{}", self.st_err_f_bndry_match_vc1().bit()), + ) + .field( + "st_err_f_bndry_match_vc2", + &format_args!("{}", self.st_err_f_bndry_match_vc2().bit()), + ) + .field( + "st_err_f_bndry_match_vc3", + &format_args!("{}", self.st_err_f_bndry_match_vc3().bit()), + ) + .field( + "st_err_f_bndry_match_vc4", + &format_args!("{}", self.st_err_f_bndry_match_vc4().bit()), + ) + .field( + "st_err_f_bndry_match_vc5", + &format_args!("{}", self.st_err_f_bndry_match_vc5().bit()), + ) + .field( + "st_err_f_bndry_match_vc6", + &format_args!("{}", self.st_err_f_bndry_match_vc6().bit()), + ) + .field( + "st_err_f_bndry_match_vc7", + &format_args!("{}", self.st_err_f_bndry_match_vc7().bit()), + ) + .field( + "st_err_f_bndry_match_vc8", + &format_args!("{}", self.st_err_f_bndry_match_vc8().bit()), + ) + .field( + "st_err_f_bndry_match_vc9", + &format_args!("{}", self.st_err_f_bndry_match_vc9().bit()), + ) + .field( + "st_err_f_bndry_match_vc10", + &format_args!("{}", self.st_err_f_bndry_match_vc10().bit()), + ) + .field( + "st_err_f_bndry_match_vc11", + &format_args!("{}", self.st_err_f_bndry_match_vc11().bit()), + ) + .field( + "st_err_f_bndry_match_vc12", + &format_args!("{}", self.st_err_f_bndry_match_vc12().bit()), + ) + .field( + "st_err_f_bndry_match_vc13", + &format_args!("{}", self.st_err_f_bndry_match_vc13().bit()), + ) + .field( + "st_err_f_bndry_match_vc14", + &format_args!("{}", self.st_err_f_bndry_match_vc14().bit()), + ) + .field( + "st_err_f_bndry_match_vc15", + &format_args!("{}", self.st_err_f_bndry_match_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_bndry_frame_fatal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_BNDRY_FRAME_FATAL_SPEC; +impl crate::RegisterSpec for INT_ST_BNDRY_FRAME_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_bndry_frame_fatal::R`](R) reader structure"] +impl crate::Readable for INT_ST_BNDRY_FRAME_FATAL_SPEC {} +#[doc = "`reset()` method sets INT_ST_BNDRY_FRAME_FATAL to value 0"] +impl crate::Resettable for INT_ST_BNDRY_FRAME_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_st_crc_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_crc_frame_fatal.rs new file mode 100644 index 0000000000..723b22ebb7 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_st_crc_frame_fatal.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INT_ST_CRC_FRAME_FATAL` reader"] +pub type R = crate::R; +#[doc = "Field `ST_ERR_FRAME_DATA_VC0` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC0_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC1` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC1_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC2` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC2_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC3` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC3_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC4` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC4_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC5` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC5_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC6` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC6_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC7` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC7_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC8` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC8_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC9` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC9_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC10` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC10_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC11` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC11_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC12` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC12_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC13` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC13_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC14` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC14_R = crate::BitReader; +#[doc = "Field `ST_ERR_FRAME_DATA_VC15` reader - NA"] +pub type ST_ERR_FRAME_DATA_VC15_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc0(&self) -> ST_ERR_FRAME_DATA_VC0_R { + ST_ERR_FRAME_DATA_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc1(&self) -> ST_ERR_FRAME_DATA_VC1_R { + ST_ERR_FRAME_DATA_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc2(&self) -> ST_ERR_FRAME_DATA_VC2_R { + ST_ERR_FRAME_DATA_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc3(&self) -> ST_ERR_FRAME_DATA_VC3_R { + ST_ERR_FRAME_DATA_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc4(&self) -> ST_ERR_FRAME_DATA_VC4_R { + ST_ERR_FRAME_DATA_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc5(&self) -> ST_ERR_FRAME_DATA_VC5_R { + ST_ERR_FRAME_DATA_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc6(&self) -> ST_ERR_FRAME_DATA_VC6_R { + ST_ERR_FRAME_DATA_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc7(&self) -> ST_ERR_FRAME_DATA_VC7_R { + ST_ERR_FRAME_DATA_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc8(&self) -> ST_ERR_FRAME_DATA_VC8_R { + ST_ERR_FRAME_DATA_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc9(&self) -> ST_ERR_FRAME_DATA_VC9_R { + ST_ERR_FRAME_DATA_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc10(&self) -> ST_ERR_FRAME_DATA_VC10_R { + ST_ERR_FRAME_DATA_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc11(&self) -> ST_ERR_FRAME_DATA_VC11_R { + ST_ERR_FRAME_DATA_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc12(&self) -> ST_ERR_FRAME_DATA_VC12_R { + ST_ERR_FRAME_DATA_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc13(&self) -> ST_ERR_FRAME_DATA_VC13_R { + ST_ERR_FRAME_DATA_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc14(&self) -> ST_ERR_FRAME_DATA_VC14_R { + ST_ERR_FRAME_DATA_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn st_err_frame_data_vc15(&self) -> ST_ERR_FRAME_DATA_VC15_R { + ST_ERR_FRAME_DATA_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_CRC_FRAME_FATAL") + .field( + "st_err_frame_data_vc0", + &format_args!("{}", self.st_err_frame_data_vc0().bit()), + ) + .field( + "st_err_frame_data_vc1", + &format_args!("{}", self.st_err_frame_data_vc1().bit()), + ) + .field( + "st_err_frame_data_vc2", + &format_args!("{}", self.st_err_frame_data_vc2().bit()), + ) + .field( + "st_err_frame_data_vc3", + &format_args!("{}", self.st_err_frame_data_vc3().bit()), + ) + .field( + "st_err_frame_data_vc4", + &format_args!("{}", self.st_err_frame_data_vc4().bit()), + ) + .field( + "st_err_frame_data_vc5", + &format_args!("{}", self.st_err_frame_data_vc5().bit()), + ) + .field( + "st_err_frame_data_vc6", + &format_args!("{}", self.st_err_frame_data_vc6().bit()), + ) + .field( + "st_err_frame_data_vc7", + &format_args!("{}", self.st_err_frame_data_vc7().bit()), + ) + .field( + "st_err_frame_data_vc8", + &format_args!("{}", self.st_err_frame_data_vc8().bit()), + ) + .field( + "st_err_frame_data_vc9", + &format_args!("{}", self.st_err_frame_data_vc9().bit()), + ) + .field( + "st_err_frame_data_vc10", + &format_args!("{}", self.st_err_frame_data_vc10().bit()), + ) + .field( + "st_err_frame_data_vc11", + &format_args!("{}", self.st_err_frame_data_vc11().bit()), + ) + .field( + "st_err_frame_data_vc12", + &format_args!("{}", self.st_err_frame_data_vc12().bit()), + ) + .field( + "st_err_frame_data_vc13", + &format_args!("{}", self.st_err_frame_data_vc13().bit()), + ) + .field( + "st_err_frame_data_vc14", + &format_args!("{}", self.st_err_frame_data_vc14().bit()), + ) + .field( + "st_err_frame_data_vc15", + &format_args!("{}", self.st_err_frame_data_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_crc_frame_fatal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_CRC_FRAME_FATAL_SPEC; +impl crate::RegisterSpec for INT_ST_CRC_FRAME_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_crc_frame_fatal::R`](R) reader structure"] +impl crate::Readable for INT_ST_CRC_FRAME_FATAL_SPEC {} +#[doc = "`reset()` method sets INT_ST_CRC_FRAME_FATAL to value 0"] +impl crate::Resettable for INT_ST_CRC_FRAME_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_st_data_id.rs b/esp32p4/src/mipi_csi_host/int_st_data_id.rs new file mode 100644 index 0000000000..ee02d66e00 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_st_data_id.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INT_ST_DATA_ID` reader"] +pub type R = crate::R; +#[doc = "Field `ST_ERR_ID_VC0` reader - NA"] +pub type ST_ERR_ID_VC0_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC1` reader - NA"] +pub type ST_ERR_ID_VC1_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC2` reader - NA"] +pub type ST_ERR_ID_VC2_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC3` reader - NA"] +pub type ST_ERR_ID_VC3_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC4` reader - NA"] +pub type ST_ERR_ID_VC4_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC5` reader - NA"] +pub type ST_ERR_ID_VC5_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC6` reader - NA"] +pub type ST_ERR_ID_VC6_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC7` reader - NA"] +pub type ST_ERR_ID_VC7_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC8` reader - NA"] +pub type ST_ERR_ID_VC8_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC9` reader - NA"] +pub type ST_ERR_ID_VC9_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC10` reader - NA"] +pub type ST_ERR_ID_VC10_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC11` reader - NA"] +pub type ST_ERR_ID_VC11_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC12` reader - NA"] +pub type ST_ERR_ID_VC12_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC13` reader - NA"] +pub type ST_ERR_ID_VC13_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC14` reader - NA"] +pub type ST_ERR_ID_VC14_R = crate::BitReader; +#[doc = "Field `ST_ERR_ID_VC15` reader - NA"] +pub type ST_ERR_ID_VC15_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn st_err_id_vc0(&self) -> ST_ERR_ID_VC0_R { + ST_ERR_ID_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn st_err_id_vc1(&self) -> ST_ERR_ID_VC1_R { + ST_ERR_ID_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn st_err_id_vc2(&self) -> ST_ERR_ID_VC2_R { + ST_ERR_ID_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn st_err_id_vc3(&self) -> ST_ERR_ID_VC3_R { + ST_ERR_ID_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn st_err_id_vc4(&self) -> ST_ERR_ID_VC4_R { + ST_ERR_ID_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn st_err_id_vc5(&self) -> ST_ERR_ID_VC5_R { + ST_ERR_ID_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn st_err_id_vc6(&self) -> ST_ERR_ID_VC6_R { + ST_ERR_ID_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn st_err_id_vc7(&self) -> ST_ERR_ID_VC7_R { + ST_ERR_ID_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn st_err_id_vc8(&self) -> ST_ERR_ID_VC8_R { + ST_ERR_ID_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn st_err_id_vc9(&self) -> ST_ERR_ID_VC9_R { + ST_ERR_ID_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn st_err_id_vc10(&self) -> ST_ERR_ID_VC10_R { + ST_ERR_ID_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn st_err_id_vc11(&self) -> ST_ERR_ID_VC11_R { + ST_ERR_ID_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn st_err_id_vc12(&self) -> ST_ERR_ID_VC12_R { + ST_ERR_ID_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn st_err_id_vc13(&self) -> ST_ERR_ID_VC13_R { + ST_ERR_ID_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn st_err_id_vc14(&self) -> ST_ERR_ID_VC14_R { + ST_ERR_ID_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn st_err_id_vc15(&self) -> ST_ERR_ID_VC15_R { + ST_ERR_ID_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_DATA_ID") + .field( + "st_err_id_vc0", + &format_args!("{}", self.st_err_id_vc0().bit()), + ) + .field( + "st_err_id_vc1", + &format_args!("{}", self.st_err_id_vc1().bit()), + ) + .field( + "st_err_id_vc2", + &format_args!("{}", self.st_err_id_vc2().bit()), + ) + .field( + "st_err_id_vc3", + &format_args!("{}", self.st_err_id_vc3().bit()), + ) + .field( + "st_err_id_vc4", + &format_args!("{}", self.st_err_id_vc4().bit()), + ) + .field( + "st_err_id_vc5", + &format_args!("{}", self.st_err_id_vc5().bit()), + ) + .field( + "st_err_id_vc6", + &format_args!("{}", self.st_err_id_vc6().bit()), + ) + .field( + "st_err_id_vc7", + &format_args!("{}", self.st_err_id_vc7().bit()), + ) + .field( + "st_err_id_vc8", + &format_args!("{}", self.st_err_id_vc8().bit()), + ) + .field( + "st_err_id_vc9", + &format_args!("{}", self.st_err_id_vc9().bit()), + ) + .field( + "st_err_id_vc10", + &format_args!("{}", self.st_err_id_vc10().bit()), + ) + .field( + "st_err_id_vc11", + &format_args!("{}", self.st_err_id_vc11().bit()), + ) + .field( + "st_err_id_vc12", + &format_args!("{}", self.st_err_id_vc12().bit()), + ) + .field( + "st_err_id_vc13", + &format_args!("{}", self.st_err_id_vc13().bit()), + ) + .field( + "st_err_id_vc14", + &format_args!("{}", self.st_err_id_vc14().bit()), + ) + .field( + "st_err_id_vc15", + &format_args!("{}", self.st_err_id_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_data_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_DATA_ID_SPEC; +impl crate::RegisterSpec for INT_ST_DATA_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_data_id::R`](R) reader structure"] +impl crate::Readable for INT_ST_DATA_ID_SPEC {} +#[doc = "`reset()` method sets INT_ST_DATA_ID to value 0"] +impl crate::Resettable for INT_ST_DATA_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_st_ecc_corrected.rs b/esp32p4/src/mipi_csi_host/int_st_ecc_corrected.rs new file mode 100644 index 0000000000..051d53bf36 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_st_ecc_corrected.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INT_ST_ECC_CORRECTED` reader"] +pub type R = crate::R; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC0` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC0_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC1` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC1_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC2` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC2_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC3` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC3_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC4` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC4_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC5` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC5_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC6` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC6_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC7` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC7_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC8` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC8_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC9` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC9_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC10` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC10_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC11` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC11_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC12` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC12_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC13` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC13_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC14` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC14_R = crate::BitReader; +#[doc = "Field `ST_ERR_ECC_CORRECTED_VC15` reader - NA"] +pub type ST_ERR_ECC_CORRECTED_VC15_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc0(&self) -> ST_ERR_ECC_CORRECTED_VC0_R { + ST_ERR_ECC_CORRECTED_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc1(&self) -> ST_ERR_ECC_CORRECTED_VC1_R { + ST_ERR_ECC_CORRECTED_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc2(&self) -> ST_ERR_ECC_CORRECTED_VC2_R { + ST_ERR_ECC_CORRECTED_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc3(&self) -> ST_ERR_ECC_CORRECTED_VC3_R { + ST_ERR_ECC_CORRECTED_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc4(&self) -> ST_ERR_ECC_CORRECTED_VC4_R { + ST_ERR_ECC_CORRECTED_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc5(&self) -> ST_ERR_ECC_CORRECTED_VC5_R { + ST_ERR_ECC_CORRECTED_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc6(&self) -> ST_ERR_ECC_CORRECTED_VC6_R { + ST_ERR_ECC_CORRECTED_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc7(&self) -> ST_ERR_ECC_CORRECTED_VC7_R { + ST_ERR_ECC_CORRECTED_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc8(&self) -> ST_ERR_ECC_CORRECTED_VC8_R { + ST_ERR_ECC_CORRECTED_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc9(&self) -> ST_ERR_ECC_CORRECTED_VC9_R { + ST_ERR_ECC_CORRECTED_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc10(&self) -> ST_ERR_ECC_CORRECTED_VC10_R { + ST_ERR_ECC_CORRECTED_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc11(&self) -> ST_ERR_ECC_CORRECTED_VC11_R { + ST_ERR_ECC_CORRECTED_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc12(&self) -> ST_ERR_ECC_CORRECTED_VC12_R { + ST_ERR_ECC_CORRECTED_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc13(&self) -> ST_ERR_ECC_CORRECTED_VC13_R { + ST_ERR_ECC_CORRECTED_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc14(&self) -> ST_ERR_ECC_CORRECTED_VC14_R { + ST_ERR_ECC_CORRECTED_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn st_err_ecc_corrected_vc15(&self) -> ST_ERR_ECC_CORRECTED_VC15_R { + ST_ERR_ECC_CORRECTED_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_ECC_CORRECTED") + .field( + "st_err_ecc_corrected_vc0", + &format_args!("{}", self.st_err_ecc_corrected_vc0().bit()), + ) + .field( + "st_err_ecc_corrected_vc1", + &format_args!("{}", self.st_err_ecc_corrected_vc1().bit()), + ) + .field( + "st_err_ecc_corrected_vc2", + &format_args!("{}", self.st_err_ecc_corrected_vc2().bit()), + ) + .field( + "st_err_ecc_corrected_vc3", + &format_args!("{}", self.st_err_ecc_corrected_vc3().bit()), + ) + .field( + "st_err_ecc_corrected_vc4", + &format_args!("{}", self.st_err_ecc_corrected_vc4().bit()), + ) + .field( + "st_err_ecc_corrected_vc5", + &format_args!("{}", self.st_err_ecc_corrected_vc5().bit()), + ) + .field( + "st_err_ecc_corrected_vc6", + &format_args!("{}", self.st_err_ecc_corrected_vc6().bit()), + ) + .field( + "st_err_ecc_corrected_vc7", + &format_args!("{}", self.st_err_ecc_corrected_vc7().bit()), + ) + .field( + "st_err_ecc_corrected_vc8", + &format_args!("{}", self.st_err_ecc_corrected_vc8().bit()), + ) + .field( + "st_err_ecc_corrected_vc9", + &format_args!("{}", self.st_err_ecc_corrected_vc9().bit()), + ) + .field( + "st_err_ecc_corrected_vc10", + &format_args!("{}", self.st_err_ecc_corrected_vc10().bit()), + ) + .field( + "st_err_ecc_corrected_vc11", + &format_args!("{}", self.st_err_ecc_corrected_vc11().bit()), + ) + .field( + "st_err_ecc_corrected_vc12", + &format_args!("{}", self.st_err_ecc_corrected_vc12().bit()), + ) + .field( + "st_err_ecc_corrected_vc13", + &format_args!("{}", self.st_err_ecc_corrected_vc13().bit()), + ) + .field( + "st_err_ecc_corrected_vc14", + &format_args!("{}", self.st_err_ecc_corrected_vc14().bit()), + ) + .field( + "st_err_ecc_corrected_vc15", + &format_args!("{}", self.st_err_ecc_corrected_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_ecc_corrected::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_ECC_CORRECTED_SPEC; +impl crate::RegisterSpec for INT_ST_ECC_CORRECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_ecc_corrected::R`](R) reader structure"] +impl crate::Readable for INT_ST_ECC_CORRECTED_SPEC {} +#[doc = "`reset()` method sets INT_ST_ECC_CORRECTED to value 0"] +impl crate::Resettable for INT_ST_ECC_CORRECTED_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_st_main.rs b/esp32p4/src/mipi_csi_host/int_st_main.rs new file mode 100644 index 0000000000..dcfd0919b4 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_st_main.rs @@ -0,0 +1,127 @@ +#[doc = "Register `INT_ST_MAIN` reader"] +pub type R = crate::R; +#[doc = "Field `ST_STATUS_INT_PHY_FATAL` reader - NA"] +pub type ST_STATUS_INT_PHY_FATAL_R = crate::BitReader; +#[doc = "Field `ST_STATUS_INT_PKT_FATAL` reader - NA"] +pub type ST_STATUS_INT_PKT_FATAL_R = crate::BitReader; +#[doc = "Field `ST_STATUS_INT_BNDRY_FRAME_FATAL` reader - NA"] +pub type ST_STATUS_INT_BNDRY_FRAME_FATAL_R = crate::BitReader; +#[doc = "Field `ST_STATUS_INT_SEQ_FRAME_FATAL` reader - NA"] +pub type ST_STATUS_INT_SEQ_FRAME_FATAL_R = crate::BitReader; +#[doc = "Field `ST_STATUS_INT_CRC_FRAME_FATAL` reader - NA"] +pub type ST_STATUS_INT_CRC_FRAME_FATAL_R = crate::BitReader; +#[doc = "Field `ST_STATUS_INT_PLD_CRC_FATAL` reader - NA"] +pub type ST_STATUS_INT_PLD_CRC_FATAL_R = crate::BitReader; +#[doc = "Field `ST_STATUS_INT_DATA_ID` reader - NA"] +pub type ST_STATUS_INT_DATA_ID_R = crate::BitReader; +#[doc = "Field `ST_STATUS_INT_ECC_CORRECTED` reader - NA"] +pub type ST_STATUS_INT_ECC_CORRECTED_R = crate::BitReader; +#[doc = "Field `ST_STATUS_INT_PHY` reader - NA"] +pub type ST_STATUS_INT_PHY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn st_status_int_phy_fatal(&self) -> ST_STATUS_INT_PHY_FATAL_R { + ST_STATUS_INT_PHY_FATAL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn st_status_int_pkt_fatal(&self) -> ST_STATUS_INT_PKT_FATAL_R { + ST_STATUS_INT_PKT_FATAL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn st_status_int_bndry_frame_fatal(&self) -> ST_STATUS_INT_BNDRY_FRAME_FATAL_R { + ST_STATUS_INT_BNDRY_FRAME_FATAL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn st_status_int_seq_frame_fatal(&self) -> ST_STATUS_INT_SEQ_FRAME_FATAL_R { + ST_STATUS_INT_SEQ_FRAME_FATAL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn st_status_int_crc_frame_fatal(&self) -> ST_STATUS_INT_CRC_FRAME_FATAL_R { + ST_STATUS_INT_CRC_FRAME_FATAL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn st_status_int_pld_crc_fatal(&self) -> ST_STATUS_INT_PLD_CRC_FATAL_R { + ST_STATUS_INT_PLD_CRC_FATAL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn st_status_int_data_id(&self) -> ST_STATUS_INT_DATA_ID_R { + ST_STATUS_INT_DATA_ID_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn st_status_int_ecc_corrected(&self) -> ST_STATUS_INT_ECC_CORRECTED_R { + ST_STATUS_INT_ECC_CORRECTED_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn st_status_int_phy(&self) -> ST_STATUS_INT_PHY_R { + ST_STATUS_INT_PHY_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_MAIN") + .field( + "st_status_int_phy_fatal", + &format_args!("{}", self.st_status_int_phy_fatal().bit()), + ) + .field( + "st_status_int_pkt_fatal", + &format_args!("{}", self.st_status_int_pkt_fatal().bit()), + ) + .field( + "st_status_int_bndry_frame_fatal", + &format_args!("{}", self.st_status_int_bndry_frame_fatal().bit()), + ) + .field( + "st_status_int_seq_frame_fatal", + &format_args!("{}", self.st_status_int_seq_frame_fatal().bit()), + ) + .field( + "st_status_int_crc_frame_fatal", + &format_args!("{}", self.st_status_int_crc_frame_fatal().bit()), + ) + .field( + "st_status_int_pld_crc_fatal", + &format_args!("{}", self.st_status_int_pld_crc_fatal().bit()), + ) + .field( + "st_status_int_data_id", + &format_args!("{}", self.st_status_int_data_id().bit()), + ) + .field( + "st_status_int_ecc_corrected", + &format_args!("{}", self.st_status_int_ecc_corrected().bit()), + ) + .field( + "st_status_int_phy", + &format_args!("{}", self.st_status_int_phy().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_main::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_MAIN_SPEC; +impl crate::RegisterSpec for INT_ST_MAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_main::R`](R) reader structure"] +impl crate::Readable for INT_ST_MAIN_SPEC {} +#[doc = "`reset()` method sets INT_ST_MAIN to value 0"] +impl crate::Resettable for INT_ST_MAIN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_st_phy.rs b/esp32p4/src/mipi_csi_host/int_st_phy.rs new file mode 100644 index 0000000000..1515cd6fae --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_st_phy.rs @@ -0,0 +1,72 @@ +#[doc = "Register `INT_ST_PHY` reader"] +pub type R = crate::R; +#[doc = "Field `ST_PHY_ERRSOTHS_0` reader - NA"] +pub type ST_PHY_ERRSOTHS_0_R = crate::BitReader; +#[doc = "Field `ST_PHY_ERRSOTHS_1` reader - NA"] +pub type ST_PHY_ERRSOTHS_1_R = crate::BitReader; +#[doc = "Field `ST_PHY_ERRESC_0` reader - NA"] +pub type ST_PHY_ERRESC_0_R = crate::BitReader; +#[doc = "Field `ST_PHY_ERRESC_1` reader - NA"] +pub type ST_PHY_ERRESC_1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn st_phy_errsoths_0(&self) -> ST_PHY_ERRSOTHS_0_R { + ST_PHY_ERRSOTHS_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn st_phy_errsoths_1(&self) -> ST_PHY_ERRSOTHS_1_R { + ST_PHY_ERRSOTHS_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn st_phy_erresc_0(&self) -> ST_PHY_ERRESC_0_R { + ST_PHY_ERRESC_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn st_phy_erresc_1(&self) -> ST_PHY_ERRESC_1_R { + ST_PHY_ERRESC_1_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_PHY") + .field( + "st_phy_errsoths_0", + &format_args!("{}", self.st_phy_errsoths_0().bit()), + ) + .field( + "st_phy_errsoths_1", + &format_args!("{}", self.st_phy_errsoths_1().bit()), + ) + .field( + "st_phy_erresc_0", + &format_args!("{}", self.st_phy_erresc_0().bit()), + ) + .field( + "st_phy_erresc_1", + &format_args!("{}", self.st_phy_erresc_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_phy::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_PHY_SPEC; +impl crate::RegisterSpec for INT_ST_PHY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_phy::R`](R) reader structure"] +impl crate::Readable for INT_ST_PHY_SPEC {} +#[doc = "`reset()` method sets INT_ST_PHY to value 0"] +impl crate::Resettable for INT_ST_PHY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_st_phy_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_phy_fatal.rs new file mode 100644 index 0000000000..290a555cf8 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_st_phy_fatal.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_ST_PHY_FATAL` reader"] +pub type R = crate::R; +#[doc = "Field `ST_PHY_ERRSOTSYNCHS_0` reader - NA"] +pub type ST_PHY_ERRSOTSYNCHS_0_R = crate::BitReader; +#[doc = "Field `ST_PHY_ERRSOTSYNCHS_1` reader - NA"] +pub type ST_PHY_ERRSOTSYNCHS_1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn st_phy_errsotsynchs_0(&self) -> ST_PHY_ERRSOTSYNCHS_0_R { + ST_PHY_ERRSOTSYNCHS_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn st_phy_errsotsynchs_1(&self) -> ST_PHY_ERRSOTSYNCHS_1_R { + ST_PHY_ERRSOTSYNCHS_1_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_PHY_FATAL") + .field( + "st_phy_errsotsynchs_0", + &format_args!("{}", self.st_phy_errsotsynchs_0().bit()), + ) + .field( + "st_phy_errsotsynchs_1", + &format_args!("{}", self.st_phy_errsotsynchs_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_phy_fatal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_PHY_FATAL_SPEC; +impl crate::RegisterSpec for INT_ST_PHY_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_phy_fatal::R`](R) reader structure"] +impl crate::Readable for INT_ST_PHY_FATAL_SPEC {} +#[doc = "`reset()` method sets INT_ST_PHY_FATAL to value 0"] +impl crate::Resettable for INT_ST_PHY_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_st_pkt_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_pkt_fatal.rs new file mode 100644 index 0000000000..e73751fe59 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_st_pkt_fatal.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_ST_PKT_FATAL` reader"] +pub type R = crate::R; +#[doc = "Field `ST_ERR_ECC_DOUBLE` reader - NA"] +pub type ST_ERR_ECC_DOUBLE_R = crate::BitReader; +#[doc = "Field `ST_SHORTER_PAYLOAD` reader - NA"] +pub type ST_SHORTER_PAYLOAD_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn st_err_ecc_double(&self) -> ST_ERR_ECC_DOUBLE_R { + ST_ERR_ECC_DOUBLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn st_shorter_payload(&self) -> ST_SHORTER_PAYLOAD_R { + ST_SHORTER_PAYLOAD_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_PKT_FATAL") + .field( + "st_err_ecc_double", + &format_args!("{}", self.st_err_ecc_double().bit()), + ) + .field( + "st_shorter_payload", + &format_args!("{}", self.st_shorter_payload().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_pkt_fatal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_PKT_FATAL_SPEC; +impl crate::RegisterSpec for INT_ST_PKT_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_pkt_fatal::R`](R) reader structure"] +impl crate::Readable for INT_ST_PKT_FATAL_SPEC {} +#[doc = "`reset()` method sets INT_ST_PKT_FATAL to value 0"] +impl crate::Resettable for INT_ST_PKT_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_st_pld_crc_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_pld_crc_fatal.rs new file mode 100644 index 0000000000..8f7f136e5d --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_st_pld_crc_fatal.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INT_ST_PLD_CRC_FATAL` reader"] +pub type R = crate::R; +#[doc = "Field `ST_ERR_CRC_VC0` reader - NA"] +pub type ST_ERR_CRC_VC0_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC1` reader - NA"] +pub type ST_ERR_CRC_VC1_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC2` reader - NA"] +pub type ST_ERR_CRC_VC2_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC3` reader - NA"] +pub type ST_ERR_CRC_VC3_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC4` reader - NA"] +pub type ST_ERR_CRC_VC4_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC5` reader - NA"] +pub type ST_ERR_CRC_VC5_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC6` reader - NA"] +pub type ST_ERR_CRC_VC6_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC7` reader - NA"] +pub type ST_ERR_CRC_VC7_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC8` reader - NA"] +pub type ST_ERR_CRC_VC8_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC9` reader - NA"] +pub type ST_ERR_CRC_VC9_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC10` reader - NA"] +pub type ST_ERR_CRC_VC10_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC11` reader - NA"] +pub type ST_ERR_CRC_VC11_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC12` reader - NA"] +pub type ST_ERR_CRC_VC12_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC13` reader - NA"] +pub type ST_ERR_CRC_VC13_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC14` reader - NA"] +pub type ST_ERR_CRC_VC14_R = crate::BitReader; +#[doc = "Field `ST_ERR_CRC_VC15` reader - NA"] +pub type ST_ERR_CRC_VC15_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn st_err_crc_vc0(&self) -> ST_ERR_CRC_VC0_R { + ST_ERR_CRC_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn st_err_crc_vc1(&self) -> ST_ERR_CRC_VC1_R { + ST_ERR_CRC_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn st_err_crc_vc2(&self) -> ST_ERR_CRC_VC2_R { + ST_ERR_CRC_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn st_err_crc_vc3(&self) -> ST_ERR_CRC_VC3_R { + ST_ERR_CRC_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn st_err_crc_vc4(&self) -> ST_ERR_CRC_VC4_R { + ST_ERR_CRC_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn st_err_crc_vc5(&self) -> ST_ERR_CRC_VC5_R { + ST_ERR_CRC_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn st_err_crc_vc6(&self) -> ST_ERR_CRC_VC6_R { + ST_ERR_CRC_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn st_err_crc_vc7(&self) -> ST_ERR_CRC_VC7_R { + ST_ERR_CRC_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn st_err_crc_vc8(&self) -> ST_ERR_CRC_VC8_R { + ST_ERR_CRC_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn st_err_crc_vc9(&self) -> ST_ERR_CRC_VC9_R { + ST_ERR_CRC_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn st_err_crc_vc10(&self) -> ST_ERR_CRC_VC10_R { + ST_ERR_CRC_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn st_err_crc_vc11(&self) -> ST_ERR_CRC_VC11_R { + ST_ERR_CRC_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn st_err_crc_vc12(&self) -> ST_ERR_CRC_VC12_R { + ST_ERR_CRC_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn st_err_crc_vc13(&self) -> ST_ERR_CRC_VC13_R { + ST_ERR_CRC_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn st_err_crc_vc14(&self) -> ST_ERR_CRC_VC14_R { + ST_ERR_CRC_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn st_err_crc_vc15(&self) -> ST_ERR_CRC_VC15_R { + ST_ERR_CRC_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_PLD_CRC_FATAL") + .field( + "st_err_crc_vc0", + &format_args!("{}", self.st_err_crc_vc0().bit()), + ) + .field( + "st_err_crc_vc1", + &format_args!("{}", self.st_err_crc_vc1().bit()), + ) + .field( + "st_err_crc_vc2", + &format_args!("{}", self.st_err_crc_vc2().bit()), + ) + .field( + "st_err_crc_vc3", + &format_args!("{}", self.st_err_crc_vc3().bit()), + ) + .field( + "st_err_crc_vc4", + &format_args!("{}", self.st_err_crc_vc4().bit()), + ) + .field( + "st_err_crc_vc5", + &format_args!("{}", self.st_err_crc_vc5().bit()), + ) + .field( + "st_err_crc_vc6", + &format_args!("{}", self.st_err_crc_vc6().bit()), + ) + .field( + "st_err_crc_vc7", + &format_args!("{}", self.st_err_crc_vc7().bit()), + ) + .field( + "st_err_crc_vc8", + &format_args!("{}", self.st_err_crc_vc8().bit()), + ) + .field( + "st_err_crc_vc9", + &format_args!("{}", self.st_err_crc_vc9().bit()), + ) + .field( + "st_err_crc_vc10", + &format_args!("{}", self.st_err_crc_vc10().bit()), + ) + .field( + "st_err_crc_vc11", + &format_args!("{}", self.st_err_crc_vc11().bit()), + ) + .field( + "st_err_crc_vc12", + &format_args!("{}", self.st_err_crc_vc12().bit()), + ) + .field( + "st_err_crc_vc13", + &format_args!("{}", self.st_err_crc_vc13().bit()), + ) + .field( + "st_err_crc_vc14", + &format_args!("{}", self.st_err_crc_vc14().bit()), + ) + .field( + "st_err_crc_vc15", + &format_args!("{}", self.st_err_crc_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_pld_crc_fatal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_PLD_CRC_FATAL_SPEC; +impl crate::RegisterSpec for INT_ST_PLD_CRC_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_pld_crc_fatal::R`](R) reader structure"] +impl crate::Readable for INT_ST_PLD_CRC_FATAL_SPEC {} +#[doc = "`reset()` method sets INT_ST_PLD_CRC_FATAL to value 0"] +impl crate::Resettable for INT_ST_PLD_CRC_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/int_st_seq_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_seq_frame_fatal.rs new file mode 100644 index 0000000000..debd93a47c --- /dev/null +++ b/esp32p4/src/mipi_csi_host/int_st_seq_frame_fatal.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INT_ST_SEQ_FRAME_FATAL` reader"] +pub type R = crate::R; +#[doc = "Field `ST_ERR_F_SEQ_VC0` reader - NA"] +pub type ST_ERR_F_SEQ_VC0_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC1` reader - NA"] +pub type ST_ERR_F_SEQ_VC1_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC2` reader - NA"] +pub type ST_ERR_F_SEQ_VC2_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC3` reader - NA"] +pub type ST_ERR_F_SEQ_VC3_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC4` reader - NA"] +pub type ST_ERR_F_SEQ_VC4_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC5` reader - NA"] +pub type ST_ERR_F_SEQ_VC5_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC6` reader - NA"] +pub type ST_ERR_F_SEQ_VC6_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC7` reader - NA"] +pub type ST_ERR_F_SEQ_VC7_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC8` reader - NA"] +pub type ST_ERR_F_SEQ_VC8_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC9` reader - NA"] +pub type ST_ERR_F_SEQ_VC9_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC10` reader - NA"] +pub type ST_ERR_F_SEQ_VC10_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC11` reader - NA"] +pub type ST_ERR_F_SEQ_VC11_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC12` reader - NA"] +pub type ST_ERR_F_SEQ_VC12_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC13` reader - NA"] +pub type ST_ERR_F_SEQ_VC13_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC14` reader - NA"] +pub type ST_ERR_F_SEQ_VC14_R = crate::BitReader; +#[doc = "Field `ST_ERR_F_SEQ_VC15` reader - NA"] +pub type ST_ERR_F_SEQ_VC15_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc0(&self) -> ST_ERR_F_SEQ_VC0_R { + ST_ERR_F_SEQ_VC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc1(&self) -> ST_ERR_F_SEQ_VC1_R { + ST_ERR_F_SEQ_VC1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc2(&self) -> ST_ERR_F_SEQ_VC2_R { + ST_ERR_F_SEQ_VC2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc3(&self) -> ST_ERR_F_SEQ_VC3_R { + ST_ERR_F_SEQ_VC3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc4(&self) -> ST_ERR_F_SEQ_VC4_R { + ST_ERR_F_SEQ_VC4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc5(&self) -> ST_ERR_F_SEQ_VC5_R { + ST_ERR_F_SEQ_VC5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc6(&self) -> ST_ERR_F_SEQ_VC6_R { + ST_ERR_F_SEQ_VC6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc7(&self) -> ST_ERR_F_SEQ_VC7_R { + ST_ERR_F_SEQ_VC7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc8(&self) -> ST_ERR_F_SEQ_VC8_R { + ST_ERR_F_SEQ_VC8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc9(&self) -> ST_ERR_F_SEQ_VC9_R { + ST_ERR_F_SEQ_VC9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc10(&self) -> ST_ERR_F_SEQ_VC10_R { + ST_ERR_F_SEQ_VC10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc11(&self) -> ST_ERR_F_SEQ_VC11_R { + ST_ERR_F_SEQ_VC11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc12(&self) -> ST_ERR_F_SEQ_VC12_R { + ST_ERR_F_SEQ_VC12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc13(&self) -> ST_ERR_F_SEQ_VC13_R { + ST_ERR_F_SEQ_VC13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc14(&self) -> ST_ERR_F_SEQ_VC14_R { + ST_ERR_F_SEQ_VC14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn st_err_f_seq_vc15(&self) -> ST_ERR_F_SEQ_VC15_R { + ST_ERR_F_SEQ_VC15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_SEQ_FRAME_FATAL") + .field( + "st_err_f_seq_vc0", + &format_args!("{}", self.st_err_f_seq_vc0().bit()), + ) + .field( + "st_err_f_seq_vc1", + &format_args!("{}", self.st_err_f_seq_vc1().bit()), + ) + .field( + "st_err_f_seq_vc2", + &format_args!("{}", self.st_err_f_seq_vc2().bit()), + ) + .field( + "st_err_f_seq_vc3", + &format_args!("{}", self.st_err_f_seq_vc3().bit()), + ) + .field( + "st_err_f_seq_vc4", + &format_args!("{}", self.st_err_f_seq_vc4().bit()), + ) + .field( + "st_err_f_seq_vc5", + &format_args!("{}", self.st_err_f_seq_vc5().bit()), + ) + .field( + "st_err_f_seq_vc6", + &format_args!("{}", self.st_err_f_seq_vc6().bit()), + ) + .field( + "st_err_f_seq_vc7", + &format_args!("{}", self.st_err_f_seq_vc7().bit()), + ) + .field( + "st_err_f_seq_vc8", + &format_args!("{}", self.st_err_f_seq_vc8().bit()), + ) + .field( + "st_err_f_seq_vc9", + &format_args!("{}", self.st_err_f_seq_vc9().bit()), + ) + .field( + "st_err_f_seq_vc10", + &format_args!("{}", self.st_err_f_seq_vc10().bit()), + ) + .field( + "st_err_f_seq_vc11", + &format_args!("{}", self.st_err_f_seq_vc11().bit()), + ) + .field( + "st_err_f_seq_vc12", + &format_args!("{}", self.st_err_f_seq_vc12().bit()), + ) + .field( + "st_err_f_seq_vc13", + &format_args!("{}", self.st_err_f_seq_vc13().bit()), + ) + .field( + "st_err_f_seq_vc14", + &format_args!("{}", self.st_err_f_seq_vc14().bit()), + ) + .field( + "st_err_f_seq_vc15", + &format_args!("{}", self.st_err_f_seq_vc15().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_seq_frame_fatal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SEQ_FRAME_FATAL_SPEC; +impl crate::RegisterSpec for INT_ST_SEQ_FRAME_FATAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_seq_frame_fatal::R`](R) reader structure"] +impl crate::Readable for INT_ST_SEQ_FRAME_FATAL_SPEC {} +#[doc = "`reset()` method sets INT_ST_SEQ_FRAME_FATAL to value 0"] +impl crate::Resettable for INT_ST_SEQ_FRAME_FATAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/n_lanes.rs b/esp32p4/src/mipi_csi_host/n_lanes.rs new file mode 100644 index 0000000000..7cb726b56d --- /dev/null +++ b/esp32p4/src/mipi_csi_host/n_lanes.rs @@ -0,0 +1,63 @@ +#[doc = "Register `N_LANES` reader"] +pub type R = crate::R; +#[doc = "Register `N_LANES` writer"] +pub type W = crate::W; +#[doc = "Field `N_LANES` reader - NA"] +pub type N_LANES_R = crate::FieldReader; +#[doc = "Field `N_LANES` writer - NA"] +pub type N_LANES_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + pub fn n_lanes(&self) -> N_LANES_R { + N_LANES_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("N_LANES") + .field("n_lanes", &format_args!("{}", self.n_lanes().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - NA"] + #[inline(always)] + #[must_use] + pub fn n_lanes(&mut self) -> N_LANES_W { + N_LANES_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`n_lanes::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`n_lanes::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct N_LANES_SPEC; +impl crate::RegisterSpec for N_LANES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`n_lanes::R`](R) reader structure"] +impl crate::Readable for N_LANES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`n_lanes::W`](W) writer structure"] +impl crate::Writable for N_LANES_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets N_LANES to value 0x01"] +impl crate::Resettable for N_LANES_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/mipi_csi_host/phy_cal.rs b/esp32p4/src/mipi_csi_host/phy_cal.rs new file mode 100644 index 0000000000..7d72b708f7 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/phy_cal.rs @@ -0,0 +1,36 @@ +#[doc = "Register `PHY_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `RXSKEWCALHS` reader - NA"] +pub type RXSKEWCALHS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn rxskewcalhs(&self) -> RXSKEWCALHS_R { + RXSKEWCALHS_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_CAL") + .field("rxskewcalhs", &format_args!("{}", self.rxskewcalhs().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_CAL_SPEC; +impl crate::RegisterSpec for PHY_CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_cal::R`](R) reader structure"] +impl crate::Readable for PHY_CAL_SPEC {} +#[doc = "`reset()` method sets PHY_CAL to value 0"] +impl crate::Resettable for PHY_CAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/phy_rx.rs b/esp32p4/src/mipi_csi_host/phy_rx.rs new file mode 100644 index 0000000000..37c37463a6 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/phy_rx.rs @@ -0,0 +1,72 @@ +#[doc = "Register `PHY_RX` reader"] +pub type R = crate::R; +#[doc = "Field `PHY_RXULPSESC_0` reader - NA"] +pub type PHY_RXULPSESC_0_R = crate::BitReader; +#[doc = "Field `PHY_RXULPSESC_1` reader - NA"] +pub type PHY_RXULPSESC_1_R = crate::BitReader; +#[doc = "Field `PHY_RXULPSCLKNOT` reader - NA"] +pub type PHY_RXULPSCLKNOT_R = crate::BitReader; +#[doc = "Field `PHY_RXCLKACTIVEHS` reader - NA"] +pub type PHY_RXCLKACTIVEHS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn phy_rxulpsesc_0(&self) -> PHY_RXULPSESC_0_R { + PHY_RXULPSESC_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn phy_rxulpsesc_1(&self) -> PHY_RXULPSESC_1_R { + PHY_RXULPSESC_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn phy_rxulpsclknot(&self) -> PHY_RXULPSCLKNOT_R { + PHY_RXULPSCLKNOT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn phy_rxclkactivehs(&self) -> PHY_RXCLKACTIVEHS_R { + PHY_RXCLKACTIVEHS_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_RX") + .field( + "phy_rxulpsesc_0", + &format_args!("{}", self.phy_rxulpsesc_0().bit()), + ) + .field( + "phy_rxulpsesc_1", + &format_args!("{}", self.phy_rxulpsesc_1().bit()), + ) + .field( + "phy_rxulpsclknot", + &format_args!("{}", self.phy_rxulpsclknot().bit()), + ) + .field( + "phy_rxclkactivehs", + &format_args!("{}", self.phy_rxclkactivehs().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_rx::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_RX_SPEC; +impl crate::RegisterSpec for PHY_RX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_rx::R`](R) reader structure"] +impl crate::Readable for PHY_RX_SPEC {} +#[doc = "`reset()` method sets PHY_RX to value 0x0001_0000"] +impl crate::Resettable for PHY_RX_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0000; +} diff --git a/esp32p4/src/mipi_csi_host/phy_shutdownz.rs b/esp32p4/src/mipi_csi_host/phy_shutdownz.rs new file mode 100644 index 0000000000..5e15e4b4a9 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/phy_shutdownz.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PHY_SHUTDOWNZ` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_SHUTDOWNZ` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_SHUTDOWNZ` reader - NA"] +pub type PHY_SHUTDOWNZ_R = crate::BitReader; +#[doc = "Field `PHY_SHUTDOWNZ` writer - NA"] +pub type PHY_SHUTDOWNZ_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn phy_shutdownz(&self) -> PHY_SHUTDOWNZ_R { + PHY_SHUTDOWNZ_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_SHUTDOWNZ") + .field( + "phy_shutdownz", + &format_args!("{}", self.phy_shutdownz().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_shutdownz(&mut self) -> PHY_SHUTDOWNZ_W { + PHY_SHUTDOWNZ_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_shutdownz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_shutdownz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_SHUTDOWNZ_SPEC; +impl crate::RegisterSpec for PHY_SHUTDOWNZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_shutdownz::R`](R) reader structure"] +impl crate::Readable for PHY_SHUTDOWNZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_shutdownz::W`](W) writer structure"] +impl crate::Writable for PHY_SHUTDOWNZ_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_SHUTDOWNZ to value 0"] +impl crate::Resettable for PHY_SHUTDOWNZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/phy_stopstate.rs b/esp32p4/src/mipi_csi_host/phy_stopstate.rs new file mode 100644 index 0000000000..4a0a11ee86 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/phy_stopstate.rs @@ -0,0 +1,61 @@ +#[doc = "Register `PHY_STOPSTATE` reader"] +pub type R = crate::R; +#[doc = "Field `PHY_STOPSTATEDATA_0` reader - NA"] +pub type PHY_STOPSTATEDATA_0_R = crate::BitReader; +#[doc = "Field `PHY_STOPSTATEDATA_1` reader - NA"] +pub type PHY_STOPSTATEDATA_1_R = crate::BitReader; +#[doc = "Field `PHY_STOPSTATECLK` reader - NA"] +pub type PHY_STOPSTATECLK_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn phy_stopstatedata_0(&self) -> PHY_STOPSTATEDATA_0_R { + PHY_STOPSTATEDATA_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn phy_stopstatedata_1(&self) -> PHY_STOPSTATEDATA_1_R { + PHY_STOPSTATEDATA_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn phy_stopstateclk(&self) -> PHY_STOPSTATECLK_R { + PHY_STOPSTATECLK_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_STOPSTATE") + .field( + "phy_stopstatedata_0", + &format_args!("{}", self.phy_stopstatedata_0().bit()), + ) + .field( + "phy_stopstatedata_1", + &format_args!("{}", self.phy_stopstatedata_1().bit()), + ) + .field( + "phy_stopstateclk", + &format_args!("{}", self.phy_stopstateclk().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_stopstate::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_STOPSTATE_SPEC; +impl crate::RegisterSpec for PHY_STOPSTATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_stopstate::R`](R) reader structure"] +impl crate::Readable for PHY_STOPSTATE_SPEC {} +#[doc = "`reset()` method sets PHY_STOPSTATE to value 0"] +impl crate::Resettable for PHY_STOPSTATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/phy_test_ctrl0.rs b/esp32p4/src/mipi_csi_host/phy_test_ctrl0.rs new file mode 100644 index 0000000000..db634c438f --- /dev/null +++ b/esp32p4/src/mipi_csi_host/phy_test_ctrl0.rs @@ -0,0 +1,79 @@ +#[doc = "Register `PHY_TEST_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_TEST_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_TESTCLR` reader - NA"] +pub type PHY_TESTCLR_R = crate::BitReader; +#[doc = "Field `PHY_TESTCLR` writer - NA"] +pub type PHY_TESTCLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_TESTCLK` reader - NA"] +pub type PHY_TESTCLK_R = crate::BitReader; +#[doc = "Field `PHY_TESTCLK` writer - NA"] +pub type PHY_TESTCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn phy_testclr(&self) -> PHY_TESTCLR_R { + PHY_TESTCLR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn phy_testclk(&self) -> PHY_TESTCLK_R { + PHY_TESTCLK_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_TEST_CTRL0") + .field("phy_testclr", &format_args!("{}", self.phy_testclr().bit())) + .field("phy_testclk", &format_args!("{}", self.phy_testclk().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_testclr(&mut self) -> PHY_TESTCLR_W { + PHY_TESTCLR_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_testclk(&mut self) -> PHY_TESTCLK_W { + PHY_TESTCLK_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_test_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_test_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_TEST_CTRL0_SPEC; +impl crate::RegisterSpec for PHY_TEST_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_test_ctrl0::R`](R) reader structure"] +impl crate::Readable for PHY_TEST_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_test_ctrl0::W`](W) writer structure"] +impl crate::Writable for PHY_TEST_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_TEST_CTRL0 to value 0x01"] +impl crate::Resettable for PHY_TEST_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/mipi_csi_host/phy_test_ctrl1.rs b/esp32p4/src/mipi_csi_host/phy_test_ctrl1.rs new file mode 100644 index 0000000000..b34125fe71 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/phy_test_ctrl1.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PHY_TEST_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_TEST_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_TESTDIN` reader - NA"] +pub type PHY_TESTDIN_R = crate::FieldReader; +#[doc = "Field `PHY_TESTDIN` writer - NA"] +pub type PHY_TESTDIN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PHY_TESTDOUT` reader - NA"] +pub type PHY_TESTDOUT_R = crate::FieldReader; +#[doc = "Field `PHY_TESTEN` reader - NA"] +pub type PHY_TESTEN_R = crate::BitReader; +#[doc = "Field `PHY_TESTEN` writer - NA"] +pub type PHY_TESTEN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + pub fn phy_testdin(&self) -> PHY_TESTDIN_R { + PHY_TESTDIN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + pub fn phy_testdout(&self) -> PHY_TESTDOUT_R { + PHY_TESTDOUT_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn phy_testen(&self) -> PHY_TESTEN_R { + PHY_TESTEN_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_TEST_CTRL1") + .field( + "phy_testdin", + &format_args!("{}", self.phy_testdin().bits()), + ) + .field( + "phy_testdout", + &format_args!("{}", self.phy_testdout().bits()), + ) + .field("phy_testen", &format_args!("{}", self.phy_testen().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_testdin(&mut self) -> PHY_TESTDIN_W { + PHY_TESTDIN_W::new(self, 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_testen(&mut self) -> PHY_TESTEN_W { + PHY_TESTEN_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_test_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_test_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_TEST_CTRL1_SPEC; +impl crate::RegisterSpec for PHY_TEST_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_test_ctrl1::R`](R) reader structure"] +impl crate::Readable for PHY_TEST_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_test_ctrl1::W`](W) writer structure"] +impl crate::Writable for PHY_TEST_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_TEST_CTRL1 to value 0"] +impl crate::Resettable for PHY_TEST_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/scrambling.rs b/esp32p4/src/mipi_csi_host/scrambling.rs new file mode 100644 index 0000000000..88e5ab6e72 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/scrambling.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SCRAMBLING` reader"] +pub type R = crate::R; +#[doc = "Register `SCRAMBLING` writer"] +pub type W = crate::W; +#[doc = "Field `SCRAMBLE_ENABLE` reader - NA"] +pub type SCRAMBLE_ENABLE_R = crate::BitReader; +#[doc = "Field `SCRAMBLE_ENABLE` writer - NA"] +pub type SCRAMBLE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn scramble_enable(&self) -> SCRAMBLE_ENABLE_R { + SCRAMBLE_ENABLE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCRAMBLING") + .field( + "scramble_enable", + &format_args!("{}", self.scramble_enable().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn scramble_enable(&mut self) -> SCRAMBLE_ENABLE_W { + SCRAMBLE_ENABLE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scrambling::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scrambling::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRAMBLING_SPEC; +impl crate::RegisterSpec for SCRAMBLING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scrambling::R`](R) reader structure"] +impl crate::Readable for SCRAMBLING_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scrambling::W`](W) writer structure"] +impl crate::Writable for SCRAMBLING_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCRAMBLING to value 0"] +impl crate::Resettable for SCRAMBLING_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/scrambling_seed1.rs b/esp32p4/src/mipi_csi_host/scrambling_seed1.rs new file mode 100644 index 0000000000..f85d22c233 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/scrambling_seed1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SCRAMBLING_SEED1` reader"] +pub type R = crate::R; +#[doc = "Register `SCRAMBLING_SEED1` writer"] +pub type W = crate::W; +#[doc = "Field `SCRAMBLE_SEED_LANE1` reader - NA"] +pub type SCRAMBLE_SEED_LANE1_R = crate::FieldReader; +#[doc = "Field `SCRAMBLE_SEED_LANE1` writer - NA"] +pub type SCRAMBLE_SEED_LANE1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn scramble_seed_lane1(&self) -> SCRAMBLE_SEED_LANE1_R { + SCRAMBLE_SEED_LANE1_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCRAMBLING_SEED1") + .field( + "scramble_seed_lane1", + &format_args!("{}", self.scramble_seed_lane1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn scramble_seed_lane1(&mut self) -> SCRAMBLE_SEED_LANE1_W { + SCRAMBLE_SEED_LANE1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scrambling_seed1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scrambling_seed1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRAMBLING_SEED1_SPEC; +impl crate::RegisterSpec for SCRAMBLING_SEED1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scrambling_seed1::R`](R) reader structure"] +impl crate::Readable for SCRAMBLING_SEED1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scrambling_seed1::W`](W) writer structure"] +impl crate::Writable for SCRAMBLING_SEED1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCRAMBLING_SEED1 to value 0x1008"] +impl crate::Resettable for SCRAMBLING_SEED1_SPEC { + const RESET_VALUE: Self::Ux = 0x1008; +} diff --git a/esp32p4/src/mipi_csi_host/scrambling_seed2.rs b/esp32p4/src/mipi_csi_host/scrambling_seed2.rs new file mode 100644 index 0000000000..d7e15bcde6 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/scrambling_seed2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SCRAMBLING_SEED2` reader"] +pub type R = crate::R; +#[doc = "Register `SCRAMBLING_SEED2` writer"] +pub type W = crate::W; +#[doc = "Field `SCRAMBLE_SEED_LANE2` reader - NA"] +pub type SCRAMBLE_SEED_LANE2_R = crate::FieldReader; +#[doc = "Field `SCRAMBLE_SEED_LANE2` writer - NA"] +pub type SCRAMBLE_SEED_LANE2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn scramble_seed_lane2(&self) -> SCRAMBLE_SEED_LANE2_R { + SCRAMBLE_SEED_LANE2_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SCRAMBLING_SEED2") + .field( + "scramble_seed_lane2", + &format_args!("{}", self.scramble_seed_lane2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn scramble_seed_lane2(&mut self) -> SCRAMBLE_SEED_LANE2_W { + SCRAMBLE_SEED_LANE2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scrambling_seed2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scrambling_seed2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRAMBLING_SEED2_SPEC; +impl crate::RegisterSpec for SCRAMBLING_SEED2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scrambling_seed2::R`](R) reader structure"] +impl crate::Readable for SCRAMBLING_SEED2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scrambling_seed2::W`](W) writer structure"] +impl crate::Writable for SCRAMBLING_SEED2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCRAMBLING_SEED2 to value 0x1188"] +impl crate::Resettable for SCRAMBLING_SEED2_SPEC { + const RESET_VALUE: Self::Ux = 0x1188; +} diff --git a/esp32p4/src/mipi_csi_host/vc_extension.rs b/esp32p4/src/mipi_csi_host/vc_extension.rs new file mode 100644 index 0000000000..739a0c355a --- /dev/null +++ b/esp32p4/src/mipi_csi_host/vc_extension.rs @@ -0,0 +1,63 @@ +#[doc = "Register `VC_EXTENSION` reader"] +pub type R = crate::R; +#[doc = "Register `VC_EXTENSION` writer"] +pub type W = crate::W; +#[doc = "Field `VCX` reader - NA"] +pub type VCX_R = crate::BitReader; +#[doc = "Field `VCX` writer - NA"] +pub type VCX_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn vcx(&self) -> VCX_R { + VCX_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VC_EXTENSION") + .field("vcx", &format_args!("{}", self.vcx().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn vcx(&mut self) -> VCX_W { + VCX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vc_extension::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vc_extension::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VC_EXTENSION_SPEC; +impl crate::RegisterSpec for VC_EXTENSION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vc_extension::R`](R) reader structure"] +impl crate::Readable for VC_EXTENSION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vc_extension::W`](W) writer structure"] +impl crate::Writable for VC_EXTENSION_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VC_EXTENSION to value 0"] +impl crate::Resettable for VC_EXTENSION_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_csi_host/version.rs b/esp32p4/src/mipi_csi_host/version.rs new file mode 100644 index 0000000000..7c7b5a2ab0 --- /dev/null +++ b/esp32p4/src/mipi_csi_host/version.rs @@ -0,0 +1,36 @@ +#[doc = "Register `VERSION` reader"] +pub type R = crate::R; +#[doc = "Field `VERSION` reader - NA"] +pub type VERSION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn version(&self) -> VERSION_R { + VERSION_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VERSION") + .field("version", &format_args!("{}", self.version().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VERSION_SPEC; +impl crate::RegisterSpec for VERSION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`version::R`](R) reader structure"] +impl crate::Readable for VERSION_SPEC {} +#[doc = "`reset()` method sets VERSION to value 0x3135_302a"] +impl crate::Resettable for VERSION_SPEC { + const RESET_VALUE: Self::Ux = 0x3135_302a; +} diff --git a/esp32p4/src/mipi_dsi_bridge.rs b/esp32p4/src/mipi_dsi_bridge.rs new file mode 100644 index 0000000000..d92f9d18d2 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge.rs @@ -0,0 +1,380 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + clk_en: CLK_EN, + en: EN, + dma_req_cfg: DMA_REQ_CFG, + raw_num_cfg: RAW_NUM_CFG, + raw_buf_credit_ctl: RAW_BUF_CREDIT_CTL, + fifo_flow_status: FIFO_FLOW_STATUS, + pixel_type: PIXEL_TYPE, + dma_block_interval: DMA_BLOCK_INTERVAL, + dma_req_interval: DMA_REQ_INTERVAL, + dpi_lcd_ctl: DPI_LCD_CTL, + dpi_rsv_dpi_data: DPI_RSV_DPI_DATA, + _reserved11: [u8; 0x04], + dpi_v_cfg0: DPI_V_CFG0, + dpi_v_cfg1: DPI_V_CFG1, + dpi_h_cfg0: DPI_H_CFG0, + dpi_h_cfg1: DPI_H_CFG1, + dpi_misc_config: DPI_MISC_CONFIG, + dpi_config_update: DPI_CONFIG_UPDATE, + _reserved17: [u8; 0x08], + int_ena: INT_ENA, + int_clr: INT_CLR, + int_raw: INT_RAW, + int_st: INT_ST, + host_bist_ctl: HOST_BIST_CTL, + host_trigger_rev: HOST_TRIGGER_REV, + blk_raw_num_cfg: BLK_RAW_NUM_CFG, + dma_frame_interval: DMA_FRAME_INTERVAL, + mem_aux_ctrl: MEM_AUX_CTRL, + rdn_eco_cs: RDN_ECO_CS, + rdn_eco_low: RDN_ECO_LOW, + rdn_eco_high: RDN_ECO_HIGH, + host_ctrl: HOST_CTRL, + mem_clk_ctrl: MEM_CLK_CTRL, + dma_flow_ctrl: DMA_FLOW_CTRL, + raw_buf_almost_empty_thrd: RAW_BUF_ALMOST_EMPTY_THRD, + yuv_cfg: YUV_CFG, + phy_lp_loopback_ctrl: PHY_LP_LOOPBACK_CTRL, + phy_hs_loopback_ctrl: PHY_HS_LOOPBACK_CTRL, + phy_loopback_cnt: PHY_LOOPBACK_CNT, +} +impl RegisterBlock { + #[doc = "0x00 - dsi bridge clk control register"] + #[inline(always)] + pub const fn clk_en(&self) -> &CLK_EN { + &self.clk_en + } + #[doc = "0x04 - dsi bridge en register"] + #[inline(always)] + pub const fn en(&self) -> &EN { + &self.en + } + #[doc = "0x08 - dsi bridge dma burst len register"] + #[inline(always)] + pub const fn dma_req_cfg(&self) -> &DMA_REQ_CFG { + &self.dma_req_cfg + } + #[doc = "0x0c - dsi bridge raw number control register"] + #[inline(always)] + pub const fn raw_num_cfg(&self) -> &RAW_NUM_CFG { + &self.raw_num_cfg + } + #[doc = "0x10 - dsi bridge credit register"] + #[inline(always)] + pub const fn raw_buf_credit_ctl(&self) -> &RAW_BUF_CREDIT_CTL { + &self.raw_buf_credit_ctl + } + #[doc = "0x14 - dsi bridge raw buffer depth register"] + #[inline(always)] + pub const fn fifo_flow_status(&self) -> &FIFO_FLOW_STATUS { + &self.fifo_flow_status + } + #[doc = "0x18 - dsi bridge dpi type control register"] + #[inline(always)] + pub const fn pixel_type(&self) -> &PIXEL_TYPE { + &self.pixel_type + } + #[doc = "0x1c - dsi bridge dma block interval control register"] + #[inline(always)] + pub const fn dma_block_interval(&self) -> &DMA_BLOCK_INTERVAL { + &self.dma_block_interval + } + #[doc = "0x20 - dsi bridge dma req interval control register"] + #[inline(always)] + pub const fn dma_req_interval(&self) -> &DMA_REQ_INTERVAL { + &self.dma_req_interval + } + #[doc = "0x24 - dsi bridge dpi signal control register"] + #[inline(always)] + pub const fn dpi_lcd_ctl(&self) -> &DPI_LCD_CTL { + &self.dpi_lcd_ctl + } + #[doc = "0x28 - dsi bridge dpi reserved data register"] + #[inline(always)] + pub const fn dpi_rsv_dpi_data(&self) -> &DPI_RSV_DPI_DATA { + &self.dpi_rsv_dpi_data + } + #[doc = "0x30 - dsi bridge dpi v config register 0"] + #[inline(always)] + pub const fn dpi_v_cfg0(&self) -> &DPI_V_CFG0 { + &self.dpi_v_cfg0 + } + #[doc = "0x34 - dsi bridge dpi v config register 1"] + #[inline(always)] + pub const fn dpi_v_cfg1(&self) -> &DPI_V_CFG1 { + &self.dpi_v_cfg1 + } + #[doc = "0x38 - dsi bridge dpi h config register 0"] + #[inline(always)] + pub const fn dpi_h_cfg0(&self) -> &DPI_H_CFG0 { + &self.dpi_h_cfg0 + } + #[doc = "0x3c - dsi bridge dpi h config register 1"] + #[inline(always)] + pub const fn dpi_h_cfg1(&self) -> &DPI_H_CFG1 { + &self.dpi_h_cfg1 + } + #[doc = "0x40 - dsi_bridge dpi misc config register"] + #[inline(always)] + pub const fn dpi_misc_config(&self) -> &DPI_MISC_CONFIG { + &self.dpi_misc_config + } + #[doc = "0x44 - dsi_bridge dpi config update register"] + #[inline(always)] + pub const fn dpi_config_update(&self) -> &DPI_CONFIG_UPDATE { + &self.dpi_config_update + } + #[doc = "0x50 - dsi_bridge interrupt enable register"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x54 - dsi_bridge interrupt clear register"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x58 - dsi_bridge raw interrupt register"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x5c - dsi_bridge masked interrupt register"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x60 - dsi_bridge host bist control register"] + #[inline(always)] + pub const fn host_bist_ctl(&self) -> &HOST_BIST_CTL { + &self.host_bist_ctl + } + #[doc = "0x64 - dsi_bridge host trigger reverse control register"] + #[inline(always)] + pub const fn host_trigger_rev(&self) -> &HOST_TRIGGER_REV { + &self.host_trigger_rev + } + #[doc = "0x68 - dsi_bridge block raw number control register"] + #[inline(always)] + pub const fn blk_raw_num_cfg(&self) -> &BLK_RAW_NUM_CFG { + &self.blk_raw_num_cfg + } + #[doc = "0x6c - dsi_bridge dam frame interval control register"] + #[inline(always)] + pub const fn dma_frame_interval(&self) -> &DMA_FRAME_INTERVAL { + &self.dma_frame_interval + } + #[doc = "0x70 - dsi_bridge mem aux control register"] + #[inline(always)] + pub const fn mem_aux_ctrl(&self) -> &MEM_AUX_CTRL { + &self.mem_aux_ctrl + } + #[doc = "0x74 - dsi_bridge rdn eco cs register"] + #[inline(always)] + pub const fn rdn_eco_cs(&self) -> &RDN_ECO_CS { + &self.rdn_eco_cs + } + #[doc = "0x78 - dsi_bridge rdn eco all low register"] + #[inline(always)] + pub const fn rdn_eco_low(&self) -> &RDN_ECO_LOW { + &self.rdn_eco_low + } + #[doc = "0x7c - dsi_bridge rdn eco all high register"] + #[inline(always)] + pub const fn rdn_eco_high(&self) -> &RDN_ECO_HIGH { + &self.rdn_eco_high + } + #[doc = "0x80 - dsi_bridge host control register"] + #[inline(always)] + pub const fn host_ctrl(&self) -> &HOST_CTRL { + &self.host_ctrl + } + #[doc = "0x84 - dsi_bridge mem force on control register"] + #[inline(always)] + pub const fn mem_clk_ctrl(&self) -> &MEM_CLK_CTRL { + &self.mem_clk_ctrl + } + #[doc = "0x88 - dsi_bridge dma flow controller register"] + #[inline(always)] + pub const fn dma_flow_ctrl(&self) -> &DMA_FLOW_CTRL { + &self.dma_flow_ctrl + } + #[doc = "0x8c - dsi_bridge buffer empty threshold register"] + #[inline(always)] + pub const fn raw_buf_almost_empty_thrd(&self) -> &RAW_BUF_ALMOST_EMPTY_THRD { + &self.raw_buf_almost_empty_thrd + } + #[doc = "0x90 - dsi_bridge yuv format config register"] + #[inline(always)] + pub const fn yuv_cfg(&self) -> &YUV_CFG { + &self.yuv_cfg + } + #[doc = "0x94 - dsi phy lp_loopback test ctrl"] + #[inline(always)] + pub const fn phy_lp_loopback_ctrl(&self) -> &PHY_LP_LOOPBACK_CTRL { + &self.phy_lp_loopback_ctrl + } + #[doc = "0x98 - dsi phy hp_loopback test ctrl"] + #[inline(always)] + pub const fn phy_hs_loopback_ctrl(&self) -> &PHY_HS_LOOPBACK_CTRL { + &self.phy_hs_loopback_ctrl + } + #[doc = "0x9c - loopback test cnt"] + #[inline(always)] + pub const fn phy_loopback_cnt(&self) -> &PHY_LOOPBACK_CNT { + &self.phy_loopback_cnt + } +} +#[doc = "CLK_EN (rw) register accessor: dsi bridge clk control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_en`] module"] +pub type CLK_EN = crate::Reg; +#[doc = "dsi bridge clk control register"] +pub mod clk_en; +#[doc = "EN (rw) register accessor: dsi bridge en register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@en`] module"] +pub type EN = crate::Reg; +#[doc = "dsi bridge en register"] +pub mod en; +#[doc = "DMA_REQ_CFG (rw) register accessor: dsi bridge dma burst len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_req_cfg`] module"] +pub type DMA_REQ_CFG = crate::Reg; +#[doc = "dsi bridge dma burst len register"] +pub mod dma_req_cfg; +#[doc = "RAW_NUM_CFG (rw) register accessor: dsi bridge raw number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_num_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_num_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_num_cfg`] module"] +pub type RAW_NUM_CFG = crate::Reg; +#[doc = "dsi bridge raw number control register"] +pub mod raw_num_cfg; +#[doc = "RAW_BUF_CREDIT_CTL (rw) register accessor: dsi bridge credit register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_buf_credit_ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_buf_credit_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_buf_credit_ctl`] module"] +pub type RAW_BUF_CREDIT_CTL = crate::Reg; +#[doc = "dsi bridge credit register"] +pub mod raw_buf_credit_ctl; +#[doc = "FIFO_FLOW_STATUS (r) register accessor: dsi bridge raw buffer depth register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_flow_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_flow_status`] module"] +pub type FIFO_FLOW_STATUS = crate::Reg; +#[doc = "dsi bridge raw buffer depth register"] +pub mod fifo_flow_status; +#[doc = "PIXEL_TYPE (rw) register accessor: dsi bridge dpi type control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pixel_type::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pixel_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pixel_type`] module"] +pub type PIXEL_TYPE = crate::Reg; +#[doc = "dsi bridge dpi type control register"] +pub mod pixel_type; +#[doc = "DMA_BLOCK_INTERVAL (rw) register accessor: dsi bridge dma block interval control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_block_interval::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_block_interval::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_block_interval`] module"] +pub type DMA_BLOCK_INTERVAL = crate::Reg; +#[doc = "dsi bridge dma block interval control register"] +pub mod dma_block_interval; +#[doc = "DMA_REQ_INTERVAL (rw) register accessor: dsi bridge dma req interval control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_interval::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_interval::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_req_interval`] module"] +pub type DMA_REQ_INTERVAL = crate::Reg; +#[doc = "dsi bridge dma req interval control register"] +pub mod dma_req_interval; +#[doc = "DPI_LCD_CTL (rw) register accessor: dsi bridge dpi signal control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_lcd_ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_lcd_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_lcd_ctl`] module"] +pub type DPI_LCD_CTL = crate::Reg; +#[doc = "dsi bridge dpi signal control register"] +pub mod dpi_lcd_ctl; +#[doc = "DPI_RSV_DPI_DATA (rw) register accessor: dsi bridge dpi reserved data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_rsv_dpi_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_rsv_dpi_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_rsv_dpi_data`] module"] +pub type DPI_RSV_DPI_DATA = crate::Reg; +#[doc = "dsi bridge dpi reserved data register"] +pub mod dpi_rsv_dpi_data; +#[doc = "DPI_V_CFG0 (rw) register accessor: dsi bridge dpi v config register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_v_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_v_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_v_cfg0`] module"] +pub type DPI_V_CFG0 = crate::Reg; +#[doc = "dsi bridge dpi v config register 0"] +pub mod dpi_v_cfg0; +#[doc = "DPI_V_CFG1 (rw) register accessor: dsi bridge dpi v config register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_v_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_v_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_v_cfg1`] module"] +pub type DPI_V_CFG1 = crate::Reg; +#[doc = "dsi bridge dpi v config register 1"] +pub mod dpi_v_cfg1; +#[doc = "DPI_H_CFG0 (rw) register accessor: dsi bridge dpi h config register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_h_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_h_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_h_cfg0`] module"] +pub type DPI_H_CFG0 = crate::Reg; +#[doc = "dsi bridge dpi h config register 0"] +pub mod dpi_h_cfg0; +#[doc = "DPI_H_CFG1 (rw) register accessor: dsi bridge dpi h config register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_h_cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_h_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_h_cfg1`] module"] +pub type DPI_H_CFG1 = crate::Reg; +#[doc = "dsi bridge dpi h config register 1"] +pub mod dpi_h_cfg1; +#[doc = "DPI_MISC_CONFIG (rw) register accessor: dsi_bridge dpi misc config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_misc_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_misc_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_misc_config`] module"] +pub type DPI_MISC_CONFIG = crate::Reg; +#[doc = "dsi_bridge dpi misc config register"] +pub mod dpi_misc_config; +#[doc = "DPI_CONFIG_UPDATE (w) register accessor: dsi_bridge dpi config update register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_config_update::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_config_update`] module"] +pub type DPI_CONFIG_UPDATE = crate::Reg; +#[doc = "dsi_bridge dpi config update register"] +pub mod dpi_config_update; +#[doc = "INT_ENA (rw) register accessor: dsi_bridge interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "dsi_bridge interrupt enable register"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: dsi_bridge interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "dsi_bridge interrupt clear register"] +pub mod int_clr; +#[doc = "INT_RAW (rw) register accessor: dsi_bridge raw interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "dsi_bridge raw interrupt register"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: dsi_bridge masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "dsi_bridge masked interrupt register"] +pub mod int_st; +#[doc = "HOST_BIST_CTL (rw) register accessor: dsi_bridge host bist control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_bist_ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_bist_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@host_bist_ctl`] module"] +pub type HOST_BIST_CTL = crate::Reg; +#[doc = "dsi_bridge host bist control register"] +pub mod host_bist_ctl; +#[doc = "HOST_TRIGGER_REV (rw) register accessor: dsi_bridge host trigger reverse control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_trigger_rev::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_trigger_rev::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@host_trigger_rev`] module"] +pub type HOST_TRIGGER_REV = crate::Reg; +#[doc = "dsi_bridge host trigger reverse control register"] +pub mod host_trigger_rev; +#[doc = "BLK_RAW_NUM_CFG (rw) register accessor: dsi_bridge block raw number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk_raw_num_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blk_raw_num_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blk_raw_num_cfg`] module"] +pub type BLK_RAW_NUM_CFG = crate::Reg; +#[doc = "dsi_bridge block raw number control register"] +pub mod blk_raw_num_cfg; +#[doc = "DMA_FRAME_INTERVAL (rw) register accessor: dsi_bridge dam frame interval control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_frame_interval::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_frame_interval::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_frame_interval`] module"] +pub type DMA_FRAME_INTERVAL = crate::Reg; +#[doc = "dsi_bridge dam frame interval control register"] +pub mod dma_frame_interval; +#[doc = "MEM_AUX_CTRL (rw) register accessor: dsi_bridge mem aux control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_aux_ctrl`] module"] +pub type MEM_AUX_CTRL = crate::Reg; +#[doc = "dsi_bridge mem aux control register"] +pub mod mem_aux_ctrl; +#[doc = "RDN_ECO_CS (rw) register accessor: dsi_bridge rdn eco cs register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_cs`] module"] +pub type RDN_ECO_CS = crate::Reg; +#[doc = "dsi_bridge rdn eco cs register"] +pub mod rdn_eco_cs; +#[doc = "RDN_ECO_LOW (rw) register accessor: dsi_bridge rdn eco all low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_low`] module"] +pub type RDN_ECO_LOW = crate::Reg; +#[doc = "dsi_bridge rdn eco all low register"] +pub mod rdn_eco_low; +#[doc = "RDN_ECO_HIGH (rw) register accessor: dsi_bridge rdn eco all high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco_high`] module"] +pub type RDN_ECO_HIGH = crate::Reg; +#[doc = "dsi_bridge rdn eco all high register"] +pub mod rdn_eco_high; +#[doc = "HOST_CTRL (rw) register accessor: dsi_bridge host control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@host_ctrl`] module"] +pub type HOST_CTRL = crate::Reg; +#[doc = "dsi_bridge host control register"] +pub mod host_ctrl; +#[doc = "MEM_CLK_CTRL (rw) register accessor: dsi_bridge mem force on control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_clk_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_clk_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_clk_ctrl`] module"] +pub type MEM_CLK_CTRL = crate::Reg; +#[doc = "dsi_bridge mem force on control register"] +pub mod mem_clk_ctrl; +#[doc = "DMA_FLOW_CTRL (rw) register accessor: dsi_bridge dma flow controller register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_flow_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_flow_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_flow_ctrl`] module"] +pub type DMA_FLOW_CTRL = crate::Reg; +#[doc = "dsi_bridge dma flow controller register"] +pub mod dma_flow_ctrl; +#[doc = "RAW_BUF_ALMOST_EMPTY_THRD (rw) register accessor: dsi_bridge buffer empty threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_buf_almost_empty_thrd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_buf_almost_empty_thrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_buf_almost_empty_thrd`] module"] +pub type RAW_BUF_ALMOST_EMPTY_THRD = + crate::Reg; +#[doc = "dsi_bridge buffer empty threshold register"] +pub mod raw_buf_almost_empty_thrd; +#[doc = "YUV_CFG (rw) register accessor: dsi_bridge yuv format config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`yuv_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`yuv_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@yuv_cfg`] module"] +pub type YUV_CFG = crate::Reg; +#[doc = "dsi_bridge yuv format config register"] +pub mod yuv_cfg; +#[doc = "PHY_LP_LOOPBACK_CTRL (rw) register accessor: dsi phy lp_loopback test ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_lp_loopback_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_lp_loopback_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_lp_loopback_ctrl`] module"] +pub type PHY_LP_LOOPBACK_CTRL = crate::Reg; +#[doc = "dsi phy lp_loopback test ctrl"] +pub mod phy_lp_loopback_ctrl; +#[doc = "PHY_HS_LOOPBACK_CTRL (rw) register accessor: dsi phy hp_loopback test ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_hs_loopback_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_hs_loopback_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_hs_loopback_ctrl`] module"] +pub type PHY_HS_LOOPBACK_CTRL = crate::Reg; +#[doc = "dsi phy hp_loopback test ctrl"] +pub mod phy_hs_loopback_ctrl; +#[doc = "PHY_LOOPBACK_CNT (rw) register accessor: loopback test cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_loopback_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_loopback_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_loopback_cnt`] module"] +pub type PHY_LOOPBACK_CNT = crate::Reg; +#[doc = "loopback test cnt"] +pub mod phy_loopback_cnt; diff --git a/esp32p4/src/mipi_dsi_bridge/blk_raw_num_cfg.rs b/esp32p4/src/mipi_dsi_bridge/blk_raw_num_cfg.rs new file mode 100644 index 0000000000..bb65baac78 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/blk_raw_num_cfg.rs @@ -0,0 +1,74 @@ +#[doc = "Register `BLK_RAW_NUM_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `BLK_RAW_NUM_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `BLK_RAW_NUM_TOTAL` reader - this field configures number of total block pix bits/64"] +pub type BLK_RAW_NUM_TOTAL_R = crate::FieldReader; +#[doc = "Field `BLK_RAW_NUM_TOTAL` writer - this field configures number of total block pix bits/64"] +pub type BLK_RAW_NUM_TOTAL_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +#[doc = "Field `BLK_RAW_NUM_TOTAL_SET` writer - write 1 to reload reg_blk_raw_num_total to internal cnt"] +pub type BLK_RAW_NUM_TOTAL_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:21 - this field configures number of total block pix bits/64"] + #[inline(always)] + pub fn blk_raw_num_total(&self) -> BLK_RAW_NUM_TOTAL_R { + BLK_RAW_NUM_TOTAL_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLK_RAW_NUM_CFG") + .field( + "blk_raw_num_total", + &format_args!("{}", self.blk_raw_num_total().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:21 - this field configures number of total block pix bits/64"] + #[inline(always)] + #[must_use] + pub fn blk_raw_num_total(&mut self) -> BLK_RAW_NUM_TOTAL_W { + BLK_RAW_NUM_TOTAL_W::new(self, 0) + } + #[doc = "Bit 31 - write 1 to reload reg_blk_raw_num_total to internal cnt"] + #[inline(always)] + #[must_use] + pub fn blk_raw_num_total_set(&mut self) -> BLK_RAW_NUM_TOTAL_SET_W { + BLK_RAW_NUM_TOTAL_SET_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge block raw number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk_raw_num_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blk_raw_num_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLK_RAW_NUM_CFG_SPEC; +impl crate::RegisterSpec for BLK_RAW_NUM_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blk_raw_num_cfg::R`](R) reader structure"] +impl crate::Readable for BLK_RAW_NUM_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blk_raw_num_cfg::W`](W) writer structure"] +impl crate::Writable for BLK_RAW_NUM_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLK_RAW_NUM_CFG to value 0x0003_8400"] +impl crate::Resettable for BLK_RAW_NUM_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0003_8400; +} diff --git a/esp32p4/src/mipi_dsi_bridge/clk_en.rs b/esp32p4/src/mipi_dsi_bridge/clk_en.rs new file mode 100644 index 0000000000..aae038652c --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/clk_en.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLK_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_EN` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - this bit configures force_on of dsi_bridge register clock gate"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - this bit configures force_on of dsi_bridge register clock gate"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - this bit configures force_on of dsi_bridge register clock gate"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_EN") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures force_on of dsi_bridge register clock gate"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge clk control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_EN_SPEC; +impl crate::RegisterSpec for CLK_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_en::R`](R) reader structure"] +impl crate::Readable for CLK_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_en::W`](W) writer structure"] +impl crate::Writable for CLK_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_EN to value 0"] +impl crate::Resettable for CLK_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dma_block_interval.rs b/esp32p4/src/mipi_dsi_bridge/dma_block_interval.rs new file mode 100644 index 0000000000..43f9333344 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dma_block_interval.rs @@ -0,0 +1,122 @@ +#[doc = "Register `DMA_BLOCK_INTERVAL` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_BLOCK_INTERVAL` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_BLOCK_SLOT` reader - this field configures the max block_slot_cnt"] +pub type DMA_BLOCK_SLOT_R = crate::FieldReader; +#[doc = "Field `DMA_BLOCK_SLOT` writer - this field configures the max block_slot_cnt"] +pub type DMA_BLOCK_SLOT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `DMA_BLOCK_INTERVAL` reader - this field configures the max block_interval_cnt, block_interval_cnt increased by 1 when block_slot_cnt if full"] +pub type DMA_BLOCK_INTERVAL_R = crate::FieldReader; +#[doc = "Field `DMA_BLOCK_INTERVAL` writer - this field configures the max block_interval_cnt, block_interval_cnt increased by 1 when block_slot_cnt if full"] +pub type DMA_BLOCK_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `RAW_NUM_TOTAL_AUTO_RELOAD` reader - this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable"] +pub type RAW_NUM_TOTAL_AUTO_RELOAD_R = crate::BitReader; +#[doc = "Field `RAW_NUM_TOTAL_AUTO_RELOAD` writer - this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable"] +pub type RAW_NUM_TOTAL_AUTO_RELOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN` reader - this bit configures enable of interval between dma block transfer, 0: disable, 1: enable"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - this bit configures enable of interval between dma block transfer, 0: disable, 1: enable"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:9 - this field configures the max block_slot_cnt"] + #[inline(always)] + pub fn dma_block_slot(&self) -> DMA_BLOCK_SLOT_R { + DMA_BLOCK_SLOT_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:27 - this field configures the max block_interval_cnt, block_interval_cnt increased by 1 when block_slot_cnt if full"] + #[inline(always)] + pub fn dma_block_interval(&self) -> DMA_BLOCK_INTERVAL_R { + DMA_BLOCK_INTERVAL_R::new((self.bits >> 10) & 0x0003_ffff) + } + #[doc = "Bit 28 - this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable"] + #[inline(always)] + pub fn raw_num_total_auto_reload(&self) -> RAW_NUM_TOTAL_AUTO_RELOAD_R { + RAW_NUM_TOTAL_AUTO_RELOAD_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - this bit configures enable of interval between dma block transfer, 0: disable, 1: enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_BLOCK_INTERVAL") + .field( + "dma_block_slot", + &format_args!("{}", self.dma_block_slot().bits()), + ) + .field( + "dma_block_interval", + &format_args!("{}", self.dma_block_interval().bits()), + ) + .field( + "raw_num_total_auto_reload", + &format_args!("{}", self.raw_num_total_auto_reload().bit()), + ) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - this field configures the max block_slot_cnt"] + #[inline(always)] + #[must_use] + pub fn dma_block_slot(&mut self) -> DMA_BLOCK_SLOT_W { + DMA_BLOCK_SLOT_W::new(self, 0) + } + #[doc = "Bits 10:27 - this field configures the max block_interval_cnt, block_interval_cnt increased by 1 when block_slot_cnt if full"] + #[inline(always)] + #[must_use] + pub fn dma_block_interval(&mut self) -> DMA_BLOCK_INTERVAL_W { + DMA_BLOCK_INTERVAL_W::new(self, 10) + } + #[doc = "Bit 28 - this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn raw_num_total_auto_reload( + &mut self, + ) -> RAW_NUM_TOTAL_AUTO_RELOAD_W { + RAW_NUM_TOTAL_AUTO_RELOAD_W::new(self, 28) + } + #[doc = "Bit 29 - this bit configures enable of interval between dma block transfer, 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge dma block interval control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_block_interval::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_block_interval::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_BLOCK_INTERVAL_SPEC; +impl crate::RegisterSpec for DMA_BLOCK_INTERVAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_block_interval::R`](R) reader structure"] +impl crate::Readable for DMA_BLOCK_INTERVAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_block_interval::W`](W) writer structure"] +impl crate::Writable for DMA_BLOCK_INTERVAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_BLOCK_INTERVAL to value 0x3000_2409"] +impl crate::Resettable for DMA_BLOCK_INTERVAL_SPEC { + const RESET_VALUE: Self::Ux = 0x3000_2409; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dma_flow_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/dma_flow_ctrl.rs new file mode 100644 index 0000000000..c3a769adb8 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dma_flow_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DMA_FLOW_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_FLOW_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DSI_DMA_FLOW_CONTROLLER` reader - this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller"] +pub type DSI_DMA_FLOW_CONTROLLER_R = crate::BitReader; +#[doc = "Field `DSI_DMA_FLOW_CONTROLLER` writer - this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller"] +pub type DSI_DMA_FLOW_CONTROLLER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_FLOW_MULTIBLK_NUM` reader - this field configures the num of blocks when multi-blk is enable and dmac as flow controller"] +pub type DMA_FLOW_MULTIBLK_NUM_R = crate::FieldReader; +#[doc = "Field `DMA_FLOW_MULTIBLK_NUM` writer - this field configures the num of blocks when multi-blk is enable and dmac as flow controller"] +pub type DMA_FLOW_MULTIBLK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller"] + #[inline(always)] + pub fn dsi_dma_flow_controller(&self) -> DSI_DMA_FLOW_CONTROLLER_R { + DSI_DMA_FLOW_CONTROLLER_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 4:7 - this field configures the num of blocks when multi-blk is enable and dmac as flow controller"] + #[inline(always)] + pub fn dma_flow_multiblk_num(&self) -> DMA_FLOW_MULTIBLK_NUM_R { + DMA_FLOW_MULTIBLK_NUM_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_FLOW_CTRL") + .field( + "dsi_dma_flow_controller", + &format_args!("{}", self.dsi_dma_flow_controller().bit()), + ) + .field( + "dma_flow_multiblk_num", + &format_args!("{}", self.dma_flow_multiblk_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller"] + #[inline(always)] + #[must_use] + pub fn dsi_dma_flow_controller(&mut self) -> DSI_DMA_FLOW_CONTROLLER_W { + DSI_DMA_FLOW_CONTROLLER_W::new(self, 0) + } + #[doc = "Bits 4:7 - this field configures the num of blocks when multi-blk is enable and dmac as flow controller"] + #[inline(always)] + #[must_use] + pub fn dma_flow_multiblk_num(&mut self) -> DMA_FLOW_MULTIBLK_NUM_W { + DMA_FLOW_MULTIBLK_NUM_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge dma flow controller register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_flow_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_flow_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_FLOW_CTRL_SPEC; +impl crate::RegisterSpec for DMA_FLOW_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_flow_ctrl::R`](R) reader structure"] +impl crate::Readable for DMA_FLOW_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_flow_ctrl::W`](W) writer structure"] +impl crate::Writable for DMA_FLOW_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_FLOW_CTRL to value 0x11"] +impl crate::Resettable for DMA_FLOW_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x11; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dma_frame_interval.rs b/esp32p4/src/mipi_dsi_bridge/dma_frame_interval.rs new file mode 100644 index 0000000000..27d5404fd1 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dma_frame_interval.rs @@ -0,0 +1,120 @@ +#[doc = "Register `DMA_FRAME_INTERVAL` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_FRAME_INTERVAL` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_FRAME_SLOT` reader - this field configures the max frame_slot_cnt"] +pub type DMA_FRAME_SLOT_R = crate::FieldReader; +#[doc = "Field `DMA_FRAME_SLOT` writer - this field configures the max frame_slot_cnt"] +pub type DMA_FRAME_SLOT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `DMA_FRAME_INTERVAL` reader - this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full"] +pub type DMA_FRAME_INTERVAL_R = crate::FieldReader; +#[doc = "Field `DMA_FRAME_INTERVAL` writer - this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full"] +pub type DMA_FRAME_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `DMA_MULTIBLK_EN` reader - this bit configures enable multi-blk transfer, 0: disable, 1: enable"] +pub type DMA_MULTIBLK_EN_R = crate::BitReader; +#[doc = "Field `DMA_MULTIBLK_EN` writer - this bit configures enable multi-blk transfer, 0: disable, 1: enable"] +pub type DMA_MULTIBLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN` reader - this bit configures enable interval between frame transfer, 0: disable, 1: enable"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - this bit configures enable interval between frame transfer, 0: disable, 1: enable"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:9 - this field configures the max frame_slot_cnt"] + #[inline(always)] + pub fn dma_frame_slot(&self) -> DMA_FRAME_SLOT_R { + DMA_FRAME_SLOT_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:27 - this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full"] + #[inline(always)] + pub fn dma_frame_interval(&self) -> DMA_FRAME_INTERVAL_R { + DMA_FRAME_INTERVAL_R::new((self.bits >> 10) & 0x0003_ffff) + } + #[doc = "Bit 28 - this bit configures enable multi-blk transfer, 0: disable, 1: enable"] + #[inline(always)] + pub fn dma_multiblk_en(&self) -> DMA_MULTIBLK_EN_R { + DMA_MULTIBLK_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - this bit configures enable interval between frame transfer, 0: disable, 1: enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_FRAME_INTERVAL") + .field( + "dma_frame_slot", + &format_args!("{}", self.dma_frame_slot().bits()), + ) + .field( + "dma_frame_interval", + &format_args!("{}", self.dma_frame_interval().bits()), + ) + .field( + "dma_multiblk_en", + &format_args!("{}", self.dma_multiblk_en().bit()), + ) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - this field configures the max frame_slot_cnt"] + #[inline(always)] + #[must_use] + pub fn dma_frame_slot(&mut self) -> DMA_FRAME_SLOT_W { + DMA_FRAME_SLOT_W::new(self, 0) + } + #[doc = "Bits 10:27 - this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full"] + #[inline(always)] + #[must_use] + pub fn dma_frame_interval(&mut self) -> DMA_FRAME_INTERVAL_W { + DMA_FRAME_INTERVAL_W::new(self, 10) + } + #[doc = "Bit 28 - this bit configures enable multi-blk transfer, 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn dma_multiblk_en(&mut self) -> DMA_MULTIBLK_EN_W { + DMA_MULTIBLK_EN_W::new(self, 28) + } + #[doc = "Bit 29 - this bit configures enable interval between frame transfer, 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge dam frame interval control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_frame_interval::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_frame_interval::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_FRAME_INTERVAL_SPEC; +impl crate::RegisterSpec for DMA_FRAME_INTERVAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_frame_interval::R`](R) reader structure"] +impl crate::Readable for DMA_FRAME_INTERVAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_frame_interval::W`](W) writer structure"] +impl crate::Writable for DMA_FRAME_INTERVAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_FRAME_INTERVAL to value 0x2000_2409"] +impl crate::Resettable for DMA_FRAME_INTERVAL_SPEC { + const RESET_VALUE: Self::Ux = 0x2000_2409; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dma_req_cfg.rs b/esp32p4/src/mipi_dsi_bridge/dma_req_cfg.rs new file mode 100644 index 0000000000..da544fc8e6 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dma_req_cfg.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DMA_REQ_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_REQ_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_BURST_LEN` reader - this field configures the num of 64-bit in one dma burst transfer, valid only when dsi_bridge as flow controller"] +pub type DMA_BURST_LEN_R = crate::FieldReader; +#[doc = "Field `DMA_BURST_LEN` writer - this field configures the num of 64-bit in one dma burst transfer, valid only when dsi_bridge as flow controller"] +pub type DMA_BURST_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures the num of 64-bit in one dma burst transfer, valid only when dsi_bridge as flow controller"] + #[inline(always)] + pub fn dma_burst_len(&self) -> DMA_BURST_LEN_R { + DMA_BURST_LEN_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_REQ_CFG") + .field( + "dma_burst_len", + &format_args!("{}", self.dma_burst_len().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures the num of 64-bit in one dma burst transfer, valid only when dsi_bridge as flow controller"] + #[inline(always)] + #[must_use] + pub fn dma_burst_len(&mut self) -> DMA_BURST_LEN_W { + DMA_BURST_LEN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge dma burst len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_REQ_CFG_SPEC; +impl crate::RegisterSpec for DMA_REQ_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_req_cfg::R`](R) reader structure"] +impl crate::Readable for DMA_REQ_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_req_cfg::W`](W) writer structure"] +impl crate::Writable for DMA_REQ_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_REQ_CFG to value 0x80"] +impl crate::Resettable for DMA_REQ_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dma_req_interval.rs b/esp32p4/src/mipi_dsi_bridge/dma_req_interval.rs new file mode 100644 index 0000000000..78193729a4 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dma_req_interval.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DMA_REQ_INTERVAL` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_REQ_INTERVAL` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_REQ_INTERVAL` reader - this field configures the interval between dma req events"] +pub type DMA_REQ_INTERVAL_R = crate::FieldReader; +#[doc = "Field `DMA_REQ_INTERVAL` writer - this field configures the interval between dma req events"] +pub type DMA_REQ_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - this field configures the interval between dma req events"] + #[inline(always)] + pub fn dma_req_interval(&self) -> DMA_REQ_INTERVAL_R { + DMA_REQ_INTERVAL_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_REQ_INTERVAL") + .field( + "dma_req_interval", + &format_args!("{}", self.dma_req_interval().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - this field configures the interval between dma req events"] + #[inline(always)] + #[must_use] + pub fn dma_req_interval(&mut self) -> DMA_REQ_INTERVAL_W { + DMA_REQ_INTERVAL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge dma req interval control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_interval::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_interval::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_REQ_INTERVAL_SPEC; +impl crate::RegisterSpec for DMA_REQ_INTERVAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_req_interval::R`](R) reader structure"] +impl crate::Readable for DMA_REQ_INTERVAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_req_interval::W`](W) writer structure"] +impl crate::Writable for DMA_REQ_INTERVAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_REQ_INTERVAL to value 0x01"] +impl crate::Resettable for DMA_REQ_INTERVAL_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_config_update.rs b/esp32p4/src/mipi_dsi_bridge/dpi_config_update.rs new file mode 100644 index 0000000000..24b51a2b6f --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dpi_config_update.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DPI_CONFIG_UPDATE` writer"] +pub type W = crate::W; +#[doc = "Field `DPI_CONFIG_UPDATE` writer - write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*"] +pub type DPI_CONFIG_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_*"] + #[inline(always)] + #[must_use] + pub fn dpi_config_update(&mut self) -> DPI_CONFIG_UPDATE_W { + DPI_CONFIG_UPDATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge dpi config update register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_config_update::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_CONFIG_UPDATE_SPEC; +impl crate::RegisterSpec for DPI_CONFIG_UPDATE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`dpi_config_update::W`](W) writer structure"] +impl crate::Writable for DPI_CONFIG_UPDATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_CONFIG_UPDATE to value 0"] +impl crate::Resettable for DPI_CONFIG_UPDATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg0.rs b/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg0.rs new file mode 100644 index 0000000000..c9e61d9f2a --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg0.rs @@ -0,0 +1,79 @@ +#[doc = "Register `DPI_H_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `DPI_H_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `HTOTAL` reader - this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank"] +pub type HTOTAL_R = crate::FieldReader; +#[doc = "Field `HTOTAL` writer - this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank"] +pub type HTOTAL_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `HDISP` reader - this field configures the length of valid pixel data (by pixel num) for dpi output"] +pub type HDISP_R = crate::FieldReader; +#[doc = "Field `HDISP` writer - this field configures the length of valid pixel data (by pixel num) for dpi output"] +pub type HDISP_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank"] + #[inline(always)] + pub fn htotal(&self) -> HTOTAL_R { + HTOTAL_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures the length of valid pixel data (by pixel num) for dpi output"] + #[inline(always)] + pub fn hdisp(&self) -> HDISP_R { + HDISP_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_H_CFG0") + .field("htotal", &format_args!("{}", self.htotal().bits())) + .field("hdisp", &format_args!("{}", self.hdisp().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank"] + #[inline(always)] + #[must_use] + pub fn htotal(&mut self) -> HTOTAL_W { + HTOTAL_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures the length of valid pixel data (by pixel num) for dpi output"] + #[inline(always)] + #[must_use] + pub fn hdisp(&mut self) -> HDISP_W { + HDISP_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge dpi h config register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_h_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_h_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_H_CFG0_SPEC; +impl crate::RegisterSpec for DPI_H_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_h_cfg0::R`](R) reader structure"] +impl crate::Readable for DPI_H_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpi_h_cfg0::W`](W) writer structure"] +impl crate::Writable for DPI_H_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_H_CFG0 to value 0x0280_0320"] +impl crate::Resettable for DPI_H_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0x0280_0320; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg1.rs b/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg1.rs new file mode 100644 index 0000000000..01c2b42ee8 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg1.rs @@ -0,0 +1,79 @@ +#[doc = "Register `DPI_H_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `DPI_H_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `HBANK` reader - this field configures the length between hsync and pixel data valid (by pixel num) for dpi output"] +pub type HBANK_R = crate::FieldReader; +#[doc = "Field `HBANK` writer - this field configures the length between hsync and pixel data valid (by pixel num) for dpi output"] +pub type HBANK_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `HSYNC` reader - this field configures the length of hsync (by pixel num) for dpi output"] +pub type HSYNC_R = crate::FieldReader; +#[doc = "Field `HSYNC` writer - this field configures the length of hsync (by pixel num) for dpi output"] +pub type HSYNC_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures the length between hsync and pixel data valid (by pixel num) for dpi output"] + #[inline(always)] + pub fn hbank(&self) -> HBANK_R { + HBANK_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures the length of hsync (by pixel num) for dpi output"] + #[inline(always)] + pub fn hsync(&self) -> HSYNC_R { + HSYNC_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_H_CFG1") + .field("hbank", &format_args!("{}", self.hbank().bits())) + .field("hsync", &format_args!("{}", self.hsync().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures the length between hsync and pixel data valid (by pixel num) for dpi output"] + #[inline(always)] + #[must_use] + pub fn hbank(&mut self) -> HBANK_W { + HBANK_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures the length of hsync (by pixel num) for dpi output"] + #[inline(always)] + #[must_use] + pub fn hsync(&mut self) -> HSYNC_W { + HSYNC_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge dpi h config register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_h_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_h_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_H_CFG1_SPEC; +impl crate::RegisterSpec for DPI_H_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_h_cfg1::R`](R) reader structure"] +impl crate::Readable for DPI_H_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpi_h_cfg1::W`](W) writer structure"] +impl crate::Writable for DPI_H_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_H_CFG1 to value 0x0060_0030"] +impl crate::Resettable for DPI_H_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0x0060_0030; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_lcd_ctl.rs b/esp32p4/src/mipi_dsi_bridge/dpi_lcd_ctl.rs new file mode 100644 index 0000000000..e3a5897a53 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dpi_lcd_ctl.rs @@ -0,0 +1,98 @@ +#[doc = "Register `DPI_LCD_CTL` reader"] +pub type R = crate::R; +#[doc = "Register `DPI_LCD_CTL` writer"] +pub type W = crate::W; +#[doc = "Field `DPISHUTDN` reader - this bit configures dpishutdn signal in dpi interface"] +pub type DPISHUTDN_R = crate::BitReader; +#[doc = "Field `DPISHUTDN` writer - this bit configures dpishutdn signal in dpi interface"] +pub type DPISHUTDN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPICOLORM` reader - this bit configures dpicolorm signal in dpi interface"] +pub type DPICOLORM_R = crate::BitReader; +#[doc = "Field `DPICOLORM` writer - this bit configures dpicolorm signal in dpi interface"] +pub type DPICOLORM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DPIUPDATECFG` reader - this bit configures dpiupdatecfg signal in dpi interface"] +pub type DPIUPDATECFG_R = crate::BitReader; +#[doc = "Field `DPIUPDATECFG` writer - this bit configures dpiupdatecfg signal in dpi interface"] +pub type DPIUPDATECFG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - this bit configures dpishutdn signal in dpi interface"] + #[inline(always)] + pub fn dpishutdn(&self) -> DPISHUTDN_R { + DPISHUTDN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - this bit configures dpicolorm signal in dpi interface"] + #[inline(always)] + pub fn dpicolorm(&self) -> DPICOLORM_R { + DPICOLORM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - this bit configures dpiupdatecfg signal in dpi interface"] + #[inline(always)] + pub fn dpiupdatecfg(&self) -> DPIUPDATECFG_R { + DPIUPDATECFG_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_LCD_CTL") + .field("dpishutdn", &format_args!("{}", self.dpishutdn().bit())) + .field("dpicolorm", &format_args!("{}", self.dpicolorm().bit())) + .field( + "dpiupdatecfg", + &format_args!("{}", self.dpiupdatecfg().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures dpishutdn signal in dpi interface"] + #[inline(always)] + #[must_use] + pub fn dpishutdn(&mut self) -> DPISHUTDN_W { + DPISHUTDN_W::new(self, 0) + } + #[doc = "Bit 1 - this bit configures dpicolorm signal in dpi interface"] + #[inline(always)] + #[must_use] + pub fn dpicolorm(&mut self) -> DPICOLORM_W { + DPICOLORM_W::new(self, 1) + } + #[doc = "Bit 2 - this bit configures dpiupdatecfg signal in dpi interface"] + #[inline(always)] + #[must_use] + pub fn dpiupdatecfg(&mut self) -> DPIUPDATECFG_W { + DPIUPDATECFG_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge dpi signal control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_lcd_ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_lcd_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_LCD_CTL_SPEC; +impl crate::RegisterSpec for DPI_LCD_CTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_lcd_ctl::R`](R) reader structure"] +impl crate::Readable for DPI_LCD_CTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpi_lcd_ctl::W`](W) writer structure"] +impl crate::Writable for DPI_LCD_CTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_LCD_CTL to value 0"] +impl crate::Resettable for DPI_LCD_CTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_misc_config.rs b/esp32p4/src/mipi_dsi_bridge/dpi_misc_config.rs new file mode 100644 index 0000000000..5971aa7dee --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dpi_misc_config.rs @@ -0,0 +1,84 @@ +#[doc = "Register `DPI_MISC_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `DPI_MISC_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `DPI_EN` reader - this bit configures enable of dpi output, 0: disable, 1: enable"] +pub type DPI_EN_R = crate::BitReader; +#[doc = "Field `DPI_EN` writer - this bit configures enable of dpi output, 0: disable, 1: enable"] +pub type DPI_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_UNDERRUN_DISCARD_VCNT` reader - this field configures the underrun interrupt musk, when underrun occurs and line cnt is less then this field"] +pub type FIFO_UNDERRUN_DISCARD_VCNT_R = crate::FieldReader; +#[doc = "Field `FIFO_UNDERRUN_DISCARD_VCNT` writer - this field configures the underrun interrupt musk, when underrun occurs and line cnt is less then this field"] +pub type FIFO_UNDERRUN_DISCARD_VCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bit 0 - this bit configures enable of dpi output, 0: disable, 1: enable"] + #[inline(always)] + pub fn dpi_en(&self) -> DPI_EN_R { + DPI_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 4:15 - this field configures the underrun interrupt musk, when underrun occurs and line cnt is less then this field"] + #[inline(always)] + pub fn fifo_underrun_discard_vcnt(&self) -> FIFO_UNDERRUN_DISCARD_VCNT_R { + FIFO_UNDERRUN_DISCARD_VCNT_R::new(((self.bits >> 4) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_MISC_CONFIG") + .field("dpi_en", &format_args!("{}", self.dpi_en().bit())) + .field( + "fifo_underrun_discard_vcnt", + &format_args!("{}", self.fifo_underrun_discard_vcnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures enable of dpi output, 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn dpi_en(&mut self) -> DPI_EN_W { + DPI_EN_W::new(self, 0) + } + #[doc = "Bits 4:15 - this field configures the underrun interrupt musk, when underrun occurs and line cnt is less then this field"] + #[inline(always)] + #[must_use] + pub fn fifo_underrun_discard_vcnt( + &mut self, + ) -> FIFO_UNDERRUN_DISCARD_VCNT_W { + FIFO_UNDERRUN_DISCARD_VCNT_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge dpi misc config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_misc_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_misc_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_MISC_CONFIG_SPEC; +impl crate::RegisterSpec for DPI_MISC_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_misc_config::R`](R) reader structure"] +impl crate::Readable for DPI_MISC_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpi_misc_config::W`](W) writer structure"] +impl crate::Writable for DPI_MISC_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_MISC_CONFIG to value 0x19d0"] +impl crate::Resettable for DPI_MISC_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0x19d0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_rsv_dpi_data.rs b/esp32p4/src/mipi_dsi_bridge/dpi_rsv_dpi_data.rs new file mode 100644 index 0000000000..a39818a20d --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dpi_rsv_dpi_data.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DPI_RSV_DPI_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DPI_RSV_DPI_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `DPI_RSV_DATA` reader - this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow"] +pub type DPI_RSV_DATA_R = crate::FieldReader; +#[doc = "Field `DPI_RSV_DATA` writer - this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow"] +pub type DPI_RSV_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 0:29 - this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow"] + #[inline(always)] + pub fn dpi_rsv_data(&self) -> DPI_RSV_DATA_R { + DPI_RSV_DATA_R::new(self.bits & 0x3fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_RSV_DPI_DATA") + .field( + "dpi_rsv_data", + &format_args!("{}", self.dpi_rsv_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:29 - this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow"] + #[inline(always)] + #[must_use] + pub fn dpi_rsv_data(&mut self) -> DPI_RSV_DATA_W { + DPI_RSV_DATA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge dpi reserved data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_rsv_dpi_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_rsv_dpi_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_RSV_DPI_DATA_SPEC; +impl crate::RegisterSpec for DPI_RSV_DPI_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_rsv_dpi_data::R`](R) reader structure"] +impl crate::Readable for DPI_RSV_DPI_DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpi_rsv_dpi_data::W`](W) writer structure"] +impl crate::Writable for DPI_RSV_DPI_DATA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_RSV_DPI_DATA to value 0x3fff"] +impl crate::Resettable for DPI_RSV_DPI_DATA_SPEC { + const RESET_VALUE: Self::Ux = 0x3fff; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg0.rs b/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg0.rs new file mode 100644 index 0000000000..096380279c --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg0.rs @@ -0,0 +1,79 @@ +#[doc = "Register `DPI_V_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `DPI_V_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `VTOTAL` reader - this field configures the total length of one frame (by line) for dpi output, must meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank"] +pub type VTOTAL_R = crate::FieldReader; +#[doc = "Field `VTOTAL` writer - this field configures the total length of one frame (by line) for dpi output, must meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank"] +pub type VTOTAL_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `VDISP` reader - this field configures the length of valid line (by line) for dpi output"] +pub type VDISP_R = crate::FieldReader; +#[doc = "Field `VDISP` writer - this field configures the length of valid line (by line) for dpi output"] +pub type VDISP_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures the total length of one frame (by line) for dpi output, must meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank"] + #[inline(always)] + pub fn vtotal(&self) -> VTOTAL_R { + VTOTAL_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures the length of valid line (by line) for dpi output"] + #[inline(always)] + pub fn vdisp(&self) -> VDISP_R { + VDISP_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_V_CFG0") + .field("vtotal", &format_args!("{}", self.vtotal().bits())) + .field("vdisp", &format_args!("{}", self.vdisp().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures the total length of one frame (by line) for dpi output, must meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank"] + #[inline(always)] + #[must_use] + pub fn vtotal(&mut self) -> VTOTAL_W { + VTOTAL_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures the length of valid line (by line) for dpi output"] + #[inline(always)] + #[must_use] + pub fn vdisp(&mut self) -> VDISP_W { + VDISP_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge dpi v config register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_v_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_v_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_V_CFG0_SPEC; +impl crate::RegisterSpec for DPI_V_CFG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_v_cfg0::R`](R) reader structure"] +impl crate::Readable for DPI_V_CFG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpi_v_cfg0::W`](W) writer structure"] +impl crate::Writable for DPI_V_CFG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_V_CFG0 to value 0x01e0_020d"] +impl crate::Resettable for DPI_V_CFG0_SPEC { + const RESET_VALUE: Self::Ux = 0x01e0_020d; +} diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg1.rs b/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg1.rs new file mode 100644 index 0000000000..b8894923ca --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg1.rs @@ -0,0 +1,79 @@ +#[doc = "Register `DPI_V_CFG1` reader"] +pub type R = crate::R; +#[doc = "Register `DPI_V_CFG1` writer"] +pub type W = crate::W; +#[doc = "Field `VBANK` reader - this field configures the length between vsync and valid line (by line) for dpi output"] +pub type VBANK_R = crate::FieldReader; +#[doc = "Field `VBANK` writer - this field configures the length between vsync and valid line (by line) for dpi output"] +pub type VBANK_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `VSYNC` reader - this field configures the length of vsync (by line) for dpi output"] +pub type VSYNC_R = crate::FieldReader; +#[doc = "Field `VSYNC` writer - this field configures the length of vsync (by line) for dpi output"] +pub type VSYNC_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - this field configures the length between vsync and valid line (by line) for dpi output"] + #[inline(always)] + pub fn vbank(&self) -> VBANK_R { + VBANK_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:27 - this field configures the length of vsync (by line) for dpi output"] + #[inline(always)] + pub fn vsync(&self) -> VSYNC_R { + VSYNC_R::new(((self.bits >> 16) & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_V_CFG1") + .field("vbank", &format_args!("{}", self.vbank().bits())) + .field("vsync", &format_args!("{}", self.vsync().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - this field configures the length between vsync and valid line (by line) for dpi output"] + #[inline(always)] + #[must_use] + pub fn vbank(&mut self) -> VBANK_W { + VBANK_W::new(self, 0) + } + #[doc = "Bits 16:27 - this field configures the length of vsync (by line) for dpi output"] + #[inline(always)] + #[must_use] + pub fn vsync(&mut self) -> VSYNC_W { + VSYNC_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge dpi v config register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_v_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_v_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_V_CFG1_SPEC; +impl crate::RegisterSpec for DPI_V_CFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_v_cfg1::R`](R) reader structure"] +impl crate::Readable for DPI_V_CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpi_v_cfg1::W`](W) writer structure"] +impl crate::Writable for DPI_V_CFG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_V_CFG1 to value 0x0002_0021"] +impl crate::Resettable for DPI_V_CFG1_SPEC { + const RESET_VALUE: Self::Ux = 0x0002_0021; +} diff --git a/esp32p4/src/mipi_dsi_bridge/en.rs b/esp32p4/src/mipi_dsi_bridge/en.rs new file mode 100644 index 0000000000..8665af6e77 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/en.rs @@ -0,0 +1,63 @@ +#[doc = "Register `EN` reader"] +pub type R = crate::R; +#[doc = "Register `EN` writer"] +pub type W = crate::W; +#[doc = "Field `DSI_EN` reader - this bit configures module enable of dsi_bridge. 0: disable, 1: enable"] +pub type DSI_EN_R = crate::BitReader; +#[doc = "Field `DSI_EN` writer - this bit configures module enable of dsi_bridge. 0: disable, 1: enable"] +pub type DSI_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - this bit configures module enable of dsi_bridge. 0: disable, 1: enable"] + #[inline(always)] + pub fn dsi_en(&self) -> DSI_EN_R { + DSI_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EN") + .field("dsi_en", &format_args!("{}", self.dsi_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures module enable of dsi_bridge. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn dsi_en(&mut self) -> DSI_EN_W { + DSI_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge en register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EN_SPEC; +impl crate::RegisterSpec for EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`en::R`](R) reader structure"] +impl crate::Readable for EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`en::W`](W) writer structure"] +impl crate::Writable for EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EN to value 0"] +impl crate::Resettable for EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/fifo_flow_status.rs b/esp32p4/src/mipi_dsi_bridge/fifo_flow_status.rs new file mode 100644 index 0000000000..574ff27c2b --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/fifo_flow_status.rs @@ -0,0 +1,39 @@ +#[doc = "Register `FIFO_FLOW_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `RAW_BUF_DEPTH` reader - this field configures the depth of dsi_bridge fifo depth"] +pub type RAW_BUF_DEPTH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:13 - this field configures the depth of dsi_bridge fifo depth"] + #[inline(always)] + pub fn raw_buf_depth(&self) -> RAW_BUF_DEPTH_R { + RAW_BUF_DEPTH_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO_FLOW_STATUS") + .field( + "raw_buf_depth", + &format_args!("{}", self.raw_buf_depth().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "dsi bridge raw buffer depth register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_flow_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_FLOW_STATUS_SPEC; +impl crate::RegisterSpec for FIFO_FLOW_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_flow_status::R`](R) reader structure"] +impl crate::Readable for FIFO_FLOW_STATUS_SPEC {} +#[doc = "`reset()` method sets FIFO_FLOW_STATUS to value 0"] +impl crate::Resettable for FIFO_FLOW_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/host_bist_ctl.rs b/esp32p4/src/mipi_dsi_bridge/host_bist_ctl.rs new file mode 100644 index 0000000000..ef815c5083 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/host_bist_ctl.rs @@ -0,0 +1,71 @@ +#[doc = "Register `HOST_BIST_CTL` reader"] +pub type R = crate::R; +#[doc = "Register `HOST_BIST_CTL` writer"] +pub type W = crate::W; +#[doc = "Field `BISTOK` reader - bistok"] +pub type BISTOK_R = crate::BitReader; +#[doc = "Field `BISTON` reader - biston"] +pub type BISTON_R = crate::BitReader; +#[doc = "Field `BISTON` writer - biston"] +pub type BISTON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - bistok"] + #[inline(always)] + pub fn bistok(&self) -> BISTOK_R { + BISTOK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - biston"] + #[inline(always)] + pub fn biston(&self) -> BISTON_R { + BISTON_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HOST_BIST_CTL") + .field("bistok", &format_args!("{}", self.bistok().bit())) + .field("biston", &format_args!("{}", self.biston().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 1 - biston"] + #[inline(always)] + #[must_use] + pub fn biston(&mut self) -> BISTON_W { + BISTON_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge host bist control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_bist_ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_bist_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HOST_BIST_CTL_SPEC; +impl crate::RegisterSpec for HOST_BIST_CTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`host_bist_ctl::R`](R) reader structure"] +impl crate::Readable for HOST_BIST_CTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`host_bist_ctl::W`](W) writer structure"] +impl crate::Writable for HOST_BIST_CTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HOST_BIST_CTL to value 0"] +impl crate::Resettable for HOST_BIST_CTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/host_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/host_ctrl.rs new file mode 100644 index 0000000000..bbaa340b2d --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/host_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HOST_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `HOST_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DSI_CFG_REF_CLK_EN` reader - this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable"] +pub type DSI_CFG_REF_CLK_EN_R = crate::BitReader; +#[doc = "Field `DSI_CFG_REF_CLK_EN` writer - this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable"] +pub type DSI_CFG_REF_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable"] + #[inline(always)] + pub fn dsi_cfg_ref_clk_en(&self) -> DSI_CFG_REF_CLK_EN_R { + DSI_CFG_REF_CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HOST_CTRL") + .field( + "dsi_cfg_ref_clk_en", + &format_args!("{}", self.dsi_cfg_ref_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn dsi_cfg_ref_clk_en(&mut self) -> DSI_CFG_REF_CLK_EN_W { + DSI_CFG_REF_CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge host control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HOST_CTRL_SPEC; +impl crate::RegisterSpec for HOST_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`host_ctrl::R`](R) reader structure"] +impl crate::Readable for HOST_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`host_ctrl::W`](W) writer structure"] +impl crate::Writable for HOST_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HOST_CTRL to value 0x01"] +impl crate::Resettable for HOST_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/mipi_dsi_bridge/host_trigger_rev.rs b/esp32p4/src/mipi_dsi_bridge/host_trigger_rev.rs new file mode 100644 index 0000000000..35f5254269 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/host_trigger_rev.rs @@ -0,0 +1,85 @@ +#[doc = "Register `HOST_TRIGGER_REV` reader"] +pub type R = crate::R; +#[doc = "Register `HOST_TRIGGER_REV` writer"] +pub type W = crate::W; +#[doc = "Field `TX_TRIGGER_REV_EN` reader - tx_trigger reverse. 0: disable, 1: enable"] +pub type TX_TRIGGER_REV_EN_R = crate::BitReader; +#[doc = "Field `TX_TRIGGER_REV_EN` writer - tx_trigger reverse. 0: disable, 1: enable"] +pub type TX_TRIGGER_REV_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TRIGGER_REV_EN` reader - rx_trigger reverse. 0: disable, 1: enable"] +pub type RX_TRIGGER_REV_EN_R = crate::BitReader; +#[doc = "Field `RX_TRIGGER_REV_EN` writer - rx_trigger reverse. 0: disable, 1: enable"] +pub type RX_TRIGGER_REV_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - tx_trigger reverse. 0: disable, 1: enable"] + #[inline(always)] + pub fn tx_trigger_rev_en(&self) -> TX_TRIGGER_REV_EN_R { + TX_TRIGGER_REV_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - rx_trigger reverse. 0: disable, 1: enable"] + #[inline(always)] + pub fn rx_trigger_rev_en(&self) -> RX_TRIGGER_REV_EN_R { + RX_TRIGGER_REV_EN_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HOST_TRIGGER_REV") + .field( + "tx_trigger_rev_en", + &format_args!("{}", self.tx_trigger_rev_en().bit()), + ) + .field( + "rx_trigger_rev_en", + &format_args!("{}", self.rx_trigger_rev_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - tx_trigger reverse. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn tx_trigger_rev_en(&mut self) -> TX_TRIGGER_REV_EN_W { + TX_TRIGGER_REV_EN_W::new(self, 0) + } + #[doc = "Bit 1 - rx_trigger reverse. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn rx_trigger_rev_en(&mut self) -> RX_TRIGGER_REV_EN_W { + RX_TRIGGER_REV_EN_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge host trigger reverse control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_trigger_rev::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_trigger_rev::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HOST_TRIGGER_REV_SPEC; +impl crate::RegisterSpec for HOST_TRIGGER_REV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`host_trigger_rev::R`](R) reader structure"] +impl crate::Readable for HOST_TRIGGER_REV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`host_trigger_rev::W`](W) writer structure"] +impl crate::Writable for HOST_TRIGGER_REV_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HOST_TRIGGER_REV to value 0"] +impl crate::Resettable for HOST_TRIGGER_REV_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/int_clr.rs b/esp32p4/src/mipi_dsi_bridge/int_clr.rs new file mode 100644 index 0000000000..c3543e49cb --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/int_clr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `UNDERRUN_INT_CLR` writer - write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG"] +pub type UNDERRUN_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG"] + #[inline(always)] + #[must_use] + pub fn underrun_int_clr(&mut self) -> UNDERRUN_INT_CLR_W { + UNDERRUN_INT_CLR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/int_ena.rs b/esp32p4/src/mipi_dsi_bridge/int_ena.rs new file mode 100644 index 0000000000..5997369783 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/int_ena.rs @@ -0,0 +1,66 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `UNDERRUN_INT_ENA` reader - write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal"] +pub type UNDERRUN_INT_ENA_R = crate::BitReader; +#[doc = "Field `UNDERRUN_INT_ENA` writer - write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal"] +pub type UNDERRUN_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal"] + #[inline(always)] + pub fn underrun_int_ena(&self) -> UNDERRUN_INT_ENA_R { + UNDERRUN_INT_ENA_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "underrun_int_ena", + &format_args!("{}", self.underrun_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal"] + #[inline(always)] + #[must_use] + pub fn underrun_int_ena(&mut self) -> UNDERRUN_INT_ENA_W { + UNDERRUN_INT_ENA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/int_raw.rs b/esp32p4/src/mipi_dsi_bridge/int_raw.rs new file mode 100644 index 0000000000..38d911a6e7 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/int_raw.rs @@ -0,0 +1,66 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `UNDERRUN_INT_RAW` reader - the raw interrupt status of dpi_underrun"] +pub type UNDERRUN_INT_RAW_R = crate::BitReader; +#[doc = "Field `UNDERRUN_INT_RAW` writer - the raw interrupt status of dpi_underrun"] +pub type UNDERRUN_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - the raw interrupt status of dpi_underrun"] + #[inline(always)] + pub fn underrun_int_raw(&self) -> UNDERRUN_INT_RAW_R { + UNDERRUN_INT_RAW_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "underrun_int_raw", + &format_args!("{}", self.underrun_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - the raw interrupt status of dpi_underrun"] + #[inline(always)] + #[must_use] + pub fn underrun_int_raw(&mut self) -> UNDERRUN_INT_RAW_W { + UNDERRUN_INT_RAW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge raw interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/int_st.rs b/esp32p4/src/mipi_dsi_bridge/int_st.rs new file mode 100644 index 0000000000..ee01062c48 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/int_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `UNDERRUN_INT_ST` reader - the masked interrupt status of dpi_underrun"] +pub type UNDERRUN_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - the masked interrupt status of dpi_underrun"] + #[inline(always)] + pub fn underrun_int_st(&self) -> UNDERRUN_INT_ST_R { + UNDERRUN_INT_ST_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "underrun_int_st", + &format_args!("{}", self.underrun_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "dsi_bridge masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/mem_aux_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/mem_aux_ctrl.rs new file mode 100644 index 0000000000..8840ae7fdc --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/mem_aux_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `MEM_AUX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_AUX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DSI_MEM_AUX_CTRL` reader - this field configures dsi_bridge fifo memory aux ctrl"] +pub type DSI_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `DSI_MEM_AUX_CTRL` writer - this field configures dsi_bridge fifo memory aux ctrl"] +pub type DSI_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - this field configures dsi_bridge fifo memory aux ctrl"] + #[inline(always)] + pub fn dsi_mem_aux_ctrl(&self) -> DSI_MEM_AUX_CTRL_R { + DSI_MEM_AUX_CTRL_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_AUX_CTRL") + .field( + "dsi_mem_aux_ctrl", + &format_args!("{}", self.dsi_mem_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - this field configures dsi_bridge fifo memory aux ctrl"] + #[inline(always)] + #[must_use] + pub fn dsi_mem_aux_ctrl(&mut self) -> DSI_MEM_AUX_CTRL_W { + DSI_MEM_AUX_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge mem aux control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_aux_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_aux_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_AUX_CTRL_SPEC; +impl crate::RegisterSpec for MEM_AUX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_aux_ctrl::R`](R) reader structure"] +impl crate::Readable for MEM_AUX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_aux_ctrl::W`](W) writer structure"] +impl crate::Writable for MEM_AUX_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_AUX_CTRL to value 0x1320"] +impl crate::Resettable for MEM_AUX_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x1320; +} diff --git a/esp32p4/src/mipi_dsi_bridge/mem_clk_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/mem_clk_ctrl.rs new file mode 100644 index 0000000000..a51855a88f --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/mem_clk_ctrl.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MEM_CLK_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_CLK_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DSI_BRIDGE_MEM_CLK_FORCE_ON` reader - this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on"] +pub type DSI_BRIDGE_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `DSI_BRIDGE_MEM_CLK_FORCE_ON` writer - this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on"] +pub type DSI_BRIDGE_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSI_MEM_CLK_FORCE_ON` reader - this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on"] +pub type DSI_MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `DSI_MEM_CLK_FORCE_ON` writer - this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on"] +pub type DSI_MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on"] + #[inline(always)] + pub fn dsi_bridge_mem_clk_force_on(&self) -> DSI_BRIDGE_MEM_CLK_FORCE_ON_R { + DSI_BRIDGE_MEM_CLK_FORCE_ON_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on"] + #[inline(always)] + pub fn dsi_mem_clk_force_on(&self) -> DSI_MEM_CLK_FORCE_ON_R { + DSI_MEM_CLK_FORCE_ON_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_CLK_CTRL") + .field( + "dsi_bridge_mem_clk_force_on", + &format_args!("{}", self.dsi_bridge_mem_clk_force_on().bit()), + ) + .field( + "dsi_mem_clk_force_on", + &format_args!("{}", self.dsi_mem_clk_force_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on"] + #[inline(always)] + #[must_use] + pub fn dsi_bridge_mem_clk_force_on( + &mut self, + ) -> DSI_BRIDGE_MEM_CLK_FORCE_ON_W { + DSI_BRIDGE_MEM_CLK_FORCE_ON_W::new(self, 0) + } + #[doc = "Bit 1 - this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on"] + #[inline(always)] + #[must_use] + pub fn dsi_mem_clk_force_on(&mut self) -> DSI_MEM_CLK_FORCE_ON_W { + DSI_MEM_CLK_FORCE_ON_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge mem force on control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_clk_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_clk_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_CLK_CTRL_SPEC; +impl crate::RegisterSpec for MEM_CLK_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_clk_ctrl::R`](R) reader structure"] +impl crate::Readable for MEM_CLK_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_clk_ctrl::W`](W) writer structure"] +impl crate::Writable for MEM_CLK_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_CLK_CTRL to value 0"] +impl crate::Resettable for MEM_CLK_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/phy_hs_loopback_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/phy_hs_loopback_ctrl.rs new file mode 100644 index 0000000000..33bef19a8d --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/phy_hs_loopback_ctrl.rs @@ -0,0 +1,233 @@ +#[doc = "Register `PHY_HS_LOOPBACK_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_HS_LOOPBACK_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_HS_TXDATAHS_1` reader - txdatahs_1 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_TXDATAHS_1_R = crate::FieldReader; +#[doc = "Field `PHY_HS_TXDATAHS_1` writer - txdatahs_1 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_TXDATAHS_1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PHY_HS_TXREQUESTDATAHS_1` reader - txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_TXREQUESTDATAHS_1_R = crate::BitReader; +#[doc = "Field `PHY_HS_TXREQUESTDATAHS_1` writer - txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_TXREQUESTDATAHS_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_HS_BASEDIR_1` reader - basedir_1 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_BASEDIR_1_R = crate::BitReader; +#[doc = "Field `PHY_HS_BASEDIR_1` writer - basedir_1 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_BASEDIR_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_HS_TXDATAHS_0` reader - txdatahs_0 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_TXDATAHS_0_R = crate::FieldReader; +#[doc = "Field `PHY_HS_TXDATAHS_0` writer - txdatahs_0 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_TXDATAHS_0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PHY_HS_TXREQUESTDATAHS_0` reader - txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_TXREQUESTDATAHS_0_R = crate::BitReader; +#[doc = "Field `PHY_HS_TXREQUESTDATAHS_0` writer - txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_TXREQUESTDATAHS_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_HS_BASEDIR_0` reader - basedir_0 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_BASEDIR_0_R = crate::BitReader; +#[doc = "Field `PHY_HS_BASEDIR_0` writer - basedir_0 ctrl when enable dsi phy hs_loopback_test"] +pub type PHY_HS_BASEDIR_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_HS_TXREQUESTHSCLK` reader - txrequesthsclk when enable dsi phy hs_loopback_test"] +pub type PHY_HS_TXREQUESTHSCLK_R = crate::BitReader; +#[doc = "Field `PHY_HS_TXREQUESTHSCLK` writer - txrequesthsclk when enable dsi phy hs_loopback_test"] +pub type PHY_HS_TXREQUESTHSCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_HS_LOOPBACK_CHECK` writer - dsi phy hs_loopback test start check"] +pub type PHY_HS_LOOPBACK_CHECK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_HS_LOOPBACK_CHECK_DONE` reader - dsi phy hs_loopback test check done"] +pub type PHY_HS_LOOPBACK_CHECK_DONE_R = crate::BitReader; +#[doc = "Field `PHY_HS_LOOPBACK_EN` reader - dsi phy hs_loopback ctrl en"] +pub type PHY_HS_LOOPBACK_EN_R = crate::BitReader; +#[doc = "Field `PHY_HS_LOOPBACK_EN` writer - dsi phy hs_loopback ctrl en"] +pub type PHY_HS_LOOPBACK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_HS_LOOPBACK_OK` reader - result of dsi phy hs_loopback test"] +pub type PHY_HS_LOOPBACK_OK_R = crate::BitReader; +impl R { + #[doc = "Bits 0:7 - txdatahs_1 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + pub fn phy_hs_txdatahs_1(&self) -> PHY_HS_TXDATAHS_1_R { + PHY_HS_TXDATAHS_1_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + pub fn phy_hs_txrequestdatahs_1(&self) -> PHY_HS_TXREQUESTDATAHS_1_R { + PHY_HS_TXREQUESTDATAHS_1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - basedir_1 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + pub fn phy_hs_basedir_1(&self) -> PHY_HS_BASEDIR_1_R { + PHY_HS_BASEDIR_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 16:23 - txdatahs_0 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + pub fn phy_hs_txdatahs_0(&self) -> PHY_HS_TXDATAHS_0_R { + PHY_HS_TXDATAHS_0_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + pub fn phy_hs_txrequestdatahs_0(&self) -> PHY_HS_TXREQUESTDATAHS_0_R { + PHY_HS_TXREQUESTDATAHS_0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - basedir_0 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + pub fn phy_hs_basedir_0(&self) -> PHY_HS_BASEDIR_0_R { + PHY_HS_BASEDIR_0_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - txrequesthsclk when enable dsi phy hs_loopback_test"] + #[inline(always)] + pub fn phy_hs_txrequesthsclk(&self) -> PHY_HS_TXREQUESTHSCLK_R { + PHY_HS_TXREQUESTHSCLK_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - dsi phy hs_loopback test check done"] + #[inline(always)] + pub fn phy_hs_loopback_check_done(&self) -> PHY_HS_LOOPBACK_CHECK_DONE_R { + PHY_HS_LOOPBACK_CHECK_DONE_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - dsi phy hs_loopback ctrl en"] + #[inline(always)] + pub fn phy_hs_loopback_en(&self) -> PHY_HS_LOOPBACK_EN_R { + PHY_HS_LOOPBACK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - result of dsi phy hs_loopback test"] + #[inline(always)] + pub fn phy_hs_loopback_ok(&self) -> PHY_HS_LOOPBACK_OK_R { + PHY_HS_LOOPBACK_OK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_HS_LOOPBACK_CTRL") + .field( + "phy_hs_txdatahs_1", + &format_args!("{}", self.phy_hs_txdatahs_1().bits()), + ) + .field( + "phy_hs_txrequestdatahs_1", + &format_args!("{}", self.phy_hs_txrequestdatahs_1().bit()), + ) + .field( + "phy_hs_basedir_1", + &format_args!("{}", self.phy_hs_basedir_1().bit()), + ) + .field( + "phy_hs_txdatahs_0", + &format_args!("{}", self.phy_hs_txdatahs_0().bits()), + ) + .field( + "phy_hs_txrequestdatahs_0", + &format_args!("{}", self.phy_hs_txrequestdatahs_0().bit()), + ) + .field( + "phy_hs_basedir_0", + &format_args!("{}", self.phy_hs_basedir_0().bit()), + ) + .field( + "phy_hs_txrequesthsclk", + &format_args!("{}", self.phy_hs_txrequesthsclk().bit()), + ) + .field( + "phy_hs_loopback_check_done", + &format_args!("{}", self.phy_hs_loopback_check_done().bit()), + ) + .field( + "phy_hs_loopback_en", + &format_args!("{}", self.phy_hs_loopback_en().bit()), + ) + .field( + "phy_hs_loopback_ok", + &format_args!("{}", self.phy_hs_loopback_ok().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - txdatahs_1 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_hs_txdatahs_1(&mut self) -> PHY_HS_TXDATAHS_1_W { + PHY_HS_TXDATAHS_1_W::new(self, 0) + } + #[doc = "Bit 8 - txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_hs_txrequestdatahs_1( + &mut self, + ) -> PHY_HS_TXREQUESTDATAHS_1_W { + PHY_HS_TXREQUESTDATAHS_1_W::new(self, 8) + } + #[doc = "Bit 9 - basedir_1 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_hs_basedir_1(&mut self) -> PHY_HS_BASEDIR_1_W { + PHY_HS_BASEDIR_1_W::new(self, 9) + } + #[doc = "Bits 16:23 - txdatahs_0 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_hs_txdatahs_0(&mut self) -> PHY_HS_TXDATAHS_0_W { + PHY_HS_TXDATAHS_0_W::new(self, 16) + } + #[doc = "Bit 24 - txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_hs_txrequestdatahs_0( + &mut self, + ) -> PHY_HS_TXREQUESTDATAHS_0_W { + PHY_HS_TXREQUESTDATAHS_0_W::new(self, 24) + } + #[doc = "Bit 25 - basedir_0 ctrl when enable dsi phy hs_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_hs_basedir_0(&mut self) -> PHY_HS_BASEDIR_0_W { + PHY_HS_BASEDIR_0_W::new(self, 25) + } + #[doc = "Bit 27 - txrequesthsclk when enable dsi phy hs_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_hs_txrequesthsclk(&mut self) -> PHY_HS_TXREQUESTHSCLK_W { + PHY_HS_TXREQUESTHSCLK_W::new(self, 27) + } + #[doc = "Bit 28 - dsi phy hs_loopback test start check"] + #[inline(always)] + #[must_use] + pub fn phy_hs_loopback_check(&mut self) -> PHY_HS_LOOPBACK_CHECK_W { + PHY_HS_LOOPBACK_CHECK_W::new(self, 28) + } + #[doc = "Bit 30 - dsi phy hs_loopback ctrl en"] + #[inline(always)] + #[must_use] + pub fn phy_hs_loopback_en(&mut self) -> PHY_HS_LOOPBACK_EN_W { + PHY_HS_LOOPBACK_EN_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi phy hp_loopback test ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_hs_loopback_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_hs_loopback_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_HS_LOOPBACK_CTRL_SPEC; +impl crate::RegisterSpec for PHY_HS_LOOPBACK_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_hs_loopback_ctrl::R`](R) reader structure"] +impl crate::Readable for PHY_HS_LOOPBACK_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_hs_loopback_ctrl::W`](W) writer structure"] +impl crate::Writable for PHY_HS_LOOPBACK_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_HS_LOOPBACK_CTRL to value 0x0200"] +impl crate::Resettable for PHY_HS_LOOPBACK_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/esp32p4/src/mipi_dsi_bridge/phy_loopback_cnt.rs b/esp32p4/src/mipi_dsi_bridge/phy_loopback_cnt.rs new file mode 100644 index 0000000000..a0ca5d1fc4 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/phy_loopback_cnt.rs @@ -0,0 +1,85 @@ +#[doc = "Register `PHY_LOOPBACK_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_LOOPBACK_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_HS_CHECK_CNT_TH` reader - hs_loopback test check cnt"] +pub type PHY_HS_CHECK_CNT_TH_R = crate::FieldReader; +#[doc = "Field `PHY_HS_CHECK_CNT_TH` writer - hs_loopback test check cnt"] +pub type PHY_HS_CHECK_CNT_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PHY_LP_CHECK_CNT_TH` reader - lp_loopback test check cnt"] +pub type PHY_LP_CHECK_CNT_TH_R = crate::FieldReader; +#[doc = "Field `PHY_LP_CHECK_CNT_TH` writer - lp_loopback test check cnt"] +pub type PHY_LP_CHECK_CNT_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - hs_loopback test check cnt"] + #[inline(always)] + pub fn phy_hs_check_cnt_th(&self) -> PHY_HS_CHECK_CNT_TH_R { + PHY_HS_CHECK_CNT_TH_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - lp_loopback test check cnt"] + #[inline(always)] + pub fn phy_lp_check_cnt_th(&self) -> PHY_LP_CHECK_CNT_TH_R { + PHY_LP_CHECK_CNT_TH_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_LOOPBACK_CNT") + .field( + "phy_hs_check_cnt_th", + &format_args!("{}", self.phy_hs_check_cnt_th().bits()), + ) + .field( + "phy_lp_check_cnt_th", + &format_args!("{}", self.phy_lp_check_cnt_th().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - hs_loopback test check cnt"] + #[inline(always)] + #[must_use] + pub fn phy_hs_check_cnt_th(&mut self) -> PHY_HS_CHECK_CNT_TH_W { + PHY_HS_CHECK_CNT_TH_W::new(self, 0) + } + #[doc = "Bits 16:23 - lp_loopback test check cnt"] + #[inline(always)] + #[must_use] + pub fn phy_lp_check_cnt_th(&mut self) -> PHY_LP_CHECK_CNT_TH_W { + PHY_LP_CHECK_CNT_TH_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "loopback test cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_loopback_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_loopback_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_LOOPBACK_CNT_SPEC; +impl crate::RegisterSpec for PHY_LOOPBACK_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_loopback_cnt::R`](R) reader structure"] +impl crate::Readable for PHY_LOOPBACK_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_loopback_cnt::W`](W) writer structure"] +impl crate::Writable for PHY_LOOPBACK_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_LOOPBACK_CNT to value 0x0040_0040"] +impl crate::Resettable for PHY_LOOPBACK_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0x0040_0040; +} diff --git a/esp32p4/src/mipi_dsi_bridge/phy_lp_loopback_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/phy_lp_loopback_ctrl.rs new file mode 100644 index 0000000000..821f937b27 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/phy_lp_loopback_ctrl.rs @@ -0,0 +1,286 @@ +#[doc = "Register `PHY_LP_LOOPBACK_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_LP_LOOPBACK_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_LP_TXDATAESC_1` reader - txdataesc_1 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXDATAESC_1_R = crate::FieldReader; +#[doc = "Field `PHY_LP_TXDATAESC_1` writer - txdataesc_1 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXDATAESC_1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PHY_LP_TXREQUESTESC_1` reader - txrequestesc_1 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXREQUESTESC_1_R = crate::BitReader; +#[doc = "Field `PHY_LP_TXREQUESTESC_1` writer - txrequestesc_1 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXREQUESTESC_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_LP_TXVALIDESC_1` reader - txvalidesc_1 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXVALIDESC_1_R = crate::BitReader; +#[doc = "Field `PHY_LP_TXVALIDESC_1` writer - txvalidesc_1 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXVALIDESC_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_LP_TXLPDTESC_1` reader - txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXLPDTESC_1_R = crate::BitReader; +#[doc = "Field `PHY_LP_TXLPDTESC_1` writer - txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXLPDTESC_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_LP_BASEDIR_1` reader - basedir_1 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_BASEDIR_1_R = crate::BitReader; +#[doc = "Field `PHY_LP_BASEDIR_1` writer - basedir_1 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_BASEDIR_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_LP_TXDATAESC_0` reader - txdataesc_0 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXDATAESC_0_R = crate::FieldReader; +#[doc = "Field `PHY_LP_TXDATAESC_0` writer - txdataesc_0 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXDATAESC_0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PHY_LP_TXREQUESTESC_0` reader - txrequestesc_0 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXREQUESTESC_0_R = crate::BitReader; +#[doc = "Field `PHY_LP_TXREQUESTESC_0` writer - txrequestesc_0 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXREQUESTESC_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_LP_TXVALIDESC_0` reader - txvalidesc_0 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXVALIDESC_0_R = crate::BitReader; +#[doc = "Field `PHY_LP_TXVALIDESC_0` writer - txvalidesc_0 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXVALIDESC_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_LP_TXLPDTESC_0` reader - txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXLPDTESC_0_R = crate::BitReader; +#[doc = "Field `PHY_LP_TXLPDTESC_0` writer - txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_TXLPDTESC_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_LP_BASEDIR_0` reader - basedir_0 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_BASEDIR_0_R = crate::BitReader; +#[doc = "Field `PHY_LP_BASEDIR_0` writer - basedir_0 ctrl when enable dsi phy lp_loopback_test"] +pub type PHY_LP_BASEDIR_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_LP_LOOPBACK_CHECK` writer - dsi phy lp_loopback test start check"] +pub type PHY_LP_LOOPBACK_CHECK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_LP_LOOPBACK_CHECK_DONE` reader - dsi phy lp_loopback test check done"] +pub type PHY_LP_LOOPBACK_CHECK_DONE_R = crate::BitReader; +#[doc = "Field `PHY_LP_LOOPBACK_EN` reader - dsi phy lp_loopback ctrl en"] +pub type PHY_LP_LOOPBACK_EN_R = crate::BitReader; +#[doc = "Field `PHY_LP_LOOPBACK_EN` writer - dsi phy lp_loopback ctrl en"] +pub type PHY_LP_LOOPBACK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_LP_LOOPBACK_OK` reader - result of dsi phy lp_loopback test"] +pub type PHY_LP_LOOPBACK_OK_R = crate::BitReader; +impl R { + #[doc = "Bits 0:7 - txdataesc_1 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + pub fn phy_lp_txdataesc_1(&self) -> PHY_LP_TXDATAESC_1_R { + PHY_LP_TXDATAESC_1_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - txrequestesc_1 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + pub fn phy_lp_txrequestesc_1(&self) -> PHY_LP_TXREQUESTESC_1_R { + PHY_LP_TXREQUESTESC_1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - txvalidesc_1 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + pub fn phy_lp_txvalidesc_1(&self) -> PHY_LP_TXVALIDESC_1_R { + PHY_LP_TXVALIDESC_1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + pub fn phy_lp_txlpdtesc_1(&self) -> PHY_LP_TXLPDTESC_1_R { + PHY_LP_TXLPDTESC_1_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - basedir_1 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + pub fn phy_lp_basedir_1(&self) -> PHY_LP_BASEDIR_1_R { + PHY_LP_BASEDIR_1_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 16:23 - txdataesc_0 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + pub fn phy_lp_txdataesc_0(&self) -> PHY_LP_TXDATAESC_0_R { + PHY_LP_TXDATAESC_0_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - txrequestesc_0 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + pub fn phy_lp_txrequestesc_0(&self) -> PHY_LP_TXREQUESTESC_0_R { + PHY_LP_TXREQUESTESC_0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - txvalidesc_0 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + pub fn phy_lp_txvalidesc_0(&self) -> PHY_LP_TXVALIDESC_0_R { + PHY_LP_TXVALIDESC_0_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + pub fn phy_lp_txlpdtesc_0(&self) -> PHY_LP_TXLPDTESC_0_R { + PHY_LP_TXLPDTESC_0_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - basedir_0 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + pub fn phy_lp_basedir_0(&self) -> PHY_LP_BASEDIR_0_R { + PHY_LP_BASEDIR_0_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - dsi phy lp_loopback test check done"] + #[inline(always)] + pub fn phy_lp_loopback_check_done(&self) -> PHY_LP_LOOPBACK_CHECK_DONE_R { + PHY_LP_LOOPBACK_CHECK_DONE_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - dsi phy lp_loopback ctrl en"] + #[inline(always)] + pub fn phy_lp_loopback_en(&self) -> PHY_LP_LOOPBACK_EN_R { + PHY_LP_LOOPBACK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - result of dsi phy lp_loopback test"] + #[inline(always)] + pub fn phy_lp_loopback_ok(&self) -> PHY_LP_LOOPBACK_OK_R { + PHY_LP_LOOPBACK_OK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_LP_LOOPBACK_CTRL") + .field( + "phy_lp_txdataesc_1", + &format_args!("{}", self.phy_lp_txdataesc_1().bits()), + ) + .field( + "phy_lp_txrequestesc_1", + &format_args!("{}", self.phy_lp_txrequestesc_1().bit()), + ) + .field( + "phy_lp_txvalidesc_1", + &format_args!("{}", self.phy_lp_txvalidesc_1().bit()), + ) + .field( + "phy_lp_txlpdtesc_1", + &format_args!("{}", self.phy_lp_txlpdtesc_1().bit()), + ) + .field( + "phy_lp_basedir_1", + &format_args!("{}", self.phy_lp_basedir_1().bit()), + ) + .field( + "phy_lp_txdataesc_0", + &format_args!("{}", self.phy_lp_txdataesc_0().bits()), + ) + .field( + "phy_lp_txrequestesc_0", + &format_args!("{}", self.phy_lp_txrequestesc_0().bit()), + ) + .field( + "phy_lp_txvalidesc_0", + &format_args!("{}", self.phy_lp_txvalidesc_0().bit()), + ) + .field( + "phy_lp_txlpdtesc_0", + &format_args!("{}", self.phy_lp_txlpdtesc_0().bit()), + ) + .field( + "phy_lp_basedir_0", + &format_args!("{}", self.phy_lp_basedir_0().bit()), + ) + .field( + "phy_lp_loopback_check_done", + &format_args!("{}", self.phy_lp_loopback_check_done().bit()), + ) + .field( + "phy_lp_loopback_en", + &format_args!("{}", self.phy_lp_loopback_en().bit()), + ) + .field( + "phy_lp_loopback_ok", + &format_args!("{}", self.phy_lp_loopback_ok().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - txdataesc_1 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_lp_txdataesc_1(&mut self) -> PHY_LP_TXDATAESC_1_W { + PHY_LP_TXDATAESC_1_W::new(self, 0) + } + #[doc = "Bit 8 - txrequestesc_1 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_lp_txrequestesc_1(&mut self) -> PHY_LP_TXREQUESTESC_1_W { + PHY_LP_TXREQUESTESC_1_W::new(self, 8) + } + #[doc = "Bit 9 - txvalidesc_1 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_lp_txvalidesc_1(&mut self) -> PHY_LP_TXVALIDESC_1_W { + PHY_LP_TXVALIDESC_1_W::new(self, 9) + } + #[doc = "Bit 10 - txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_lp_txlpdtesc_1(&mut self) -> PHY_LP_TXLPDTESC_1_W { + PHY_LP_TXLPDTESC_1_W::new(self, 10) + } + #[doc = "Bit 11 - basedir_1 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_lp_basedir_1(&mut self) -> PHY_LP_BASEDIR_1_W { + PHY_LP_BASEDIR_1_W::new(self, 11) + } + #[doc = "Bits 16:23 - txdataesc_0 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_lp_txdataesc_0(&mut self) -> PHY_LP_TXDATAESC_0_W { + PHY_LP_TXDATAESC_0_W::new(self, 16) + } + #[doc = "Bit 24 - txrequestesc_0 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_lp_txrequestesc_0(&mut self) -> PHY_LP_TXREQUESTESC_0_W { + PHY_LP_TXREQUESTESC_0_W::new(self, 24) + } + #[doc = "Bit 25 - txvalidesc_0 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_lp_txvalidesc_0(&mut self) -> PHY_LP_TXVALIDESC_0_W { + PHY_LP_TXVALIDESC_0_W::new(self, 25) + } + #[doc = "Bit 26 - txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_lp_txlpdtesc_0(&mut self) -> PHY_LP_TXLPDTESC_0_W { + PHY_LP_TXLPDTESC_0_W::new(self, 26) + } + #[doc = "Bit 27 - basedir_0 ctrl when enable dsi phy lp_loopback_test"] + #[inline(always)] + #[must_use] + pub fn phy_lp_basedir_0(&mut self) -> PHY_LP_BASEDIR_0_W { + PHY_LP_BASEDIR_0_W::new(self, 27) + } + #[doc = "Bit 28 - dsi phy lp_loopback test start check"] + #[inline(always)] + #[must_use] + pub fn phy_lp_loopback_check(&mut self) -> PHY_LP_LOOPBACK_CHECK_W { + PHY_LP_LOOPBACK_CHECK_W::new(self, 28) + } + #[doc = "Bit 30 - dsi phy lp_loopback ctrl en"] + #[inline(always)] + #[must_use] + pub fn phy_lp_loopback_en(&mut self) -> PHY_LP_LOOPBACK_EN_W { + PHY_LP_LOOPBACK_EN_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi phy lp_loopback test ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_lp_loopback_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_lp_loopback_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_LP_LOOPBACK_CTRL_SPEC; +impl crate::RegisterSpec for PHY_LP_LOOPBACK_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_lp_loopback_ctrl::R`](R) reader structure"] +impl crate::Readable for PHY_LP_LOOPBACK_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_lp_loopback_ctrl::W`](W) writer structure"] +impl crate::Writable for PHY_LP_LOOPBACK_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_LP_LOOPBACK_CTRL to value 0"] +impl crate::Resettable for PHY_LP_LOOPBACK_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/pixel_type.rs b/esp32p4/src/mipi_dsi_bridge/pixel_type.rs new file mode 100644 index 0000000000..0e33b89613 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/pixel_type.rs @@ -0,0 +1,98 @@ +#[doc = "Register `PIXEL_TYPE` reader"] +pub type R = crate::R; +#[doc = "Register `PIXEL_TYPE` writer"] +pub type W = crate::W; +#[doc = "Field `RAW_TYPE` reader - this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565"] +pub type RAW_TYPE_R = crate::FieldReader; +#[doc = "Field `RAW_TYPE` writer - this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565"] +pub type RAW_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DPI_CONFIG` reader - this field configures the pixel arrange type of dpi interface"] +pub type DPI_CONFIG_R = crate::FieldReader; +#[doc = "Field `DPI_CONFIG` writer - this field configures the pixel arrange type of dpi interface"] +pub type DPI_CONFIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DATA_IN_TYPE` reader - input data type, 0: rgb, 1: yuv"] +pub type DATA_IN_TYPE_R = crate::BitReader; +#[doc = "Field `DATA_IN_TYPE` writer - input data type, 0: rgb, 1: yuv"] +pub type DATA_IN_TYPE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565"] + #[inline(always)] + pub fn raw_type(&self) -> RAW_TYPE_R { + RAW_TYPE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - this field configures the pixel arrange type of dpi interface"] + #[inline(always)] + pub fn dpi_config(&self) -> DPI_CONFIG_R { + DPI_CONFIG_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - input data type, 0: rgb, 1: yuv"] + #[inline(always)] + pub fn data_in_type(&self) -> DATA_IN_TYPE_R { + DATA_IN_TYPE_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIXEL_TYPE") + .field("raw_type", &format_args!("{}", self.raw_type().bits())) + .field("dpi_config", &format_args!("{}", self.dpi_config().bits())) + .field( + "data_in_type", + &format_args!("{}", self.data_in_type().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565"] + #[inline(always)] + #[must_use] + pub fn raw_type(&mut self) -> RAW_TYPE_W { + RAW_TYPE_W::new(self, 0) + } + #[doc = "Bits 4:5 - this field configures the pixel arrange type of dpi interface"] + #[inline(always)] + #[must_use] + pub fn dpi_config(&mut self) -> DPI_CONFIG_W { + DPI_CONFIG_W::new(self, 4) + } + #[doc = "Bit 6 - input data type, 0: rgb, 1: yuv"] + #[inline(always)] + #[must_use] + pub fn data_in_type(&mut self) -> DATA_IN_TYPE_W { + DATA_IN_TYPE_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge dpi type control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pixel_type::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pixel_type::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIXEL_TYPE_SPEC; +impl crate::RegisterSpec for PIXEL_TYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pixel_type::R`](R) reader structure"] +impl crate::Readable for PIXEL_TYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pixel_type::W`](W) writer structure"] +impl crate::Writable for PIXEL_TYPE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PIXEL_TYPE to value 0"] +impl crate::Resettable for PIXEL_TYPE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/raw_buf_almost_empty_thrd.rs b/esp32p4/src/mipi_dsi_bridge/raw_buf_almost_empty_thrd.rs new file mode 100644 index 0000000000..230139926a --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/raw_buf_almost_empty_thrd.rs @@ -0,0 +1,68 @@ +#[doc = "Register `RAW_BUF_ALMOST_EMPTY_THRD` reader"] +pub type R = crate::R; +#[doc = "Register `RAW_BUF_ALMOST_EMPTY_THRD` writer"] +pub type W = crate::W; +#[doc = "Field `DSI_RAW_BUF_ALMOST_EMPTY_THRD` reader - this field configures the fifo almost empty threshold, is valid only when dmac as flow controller"] +pub type DSI_RAW_BUF_ALMOST_EMPTY_THRD_R = crate::FieldReader; +#[doc = "Field `DSI_RAW_BUF_ALMOST_EMPTY_THRD` writer - this field configures the fifo almost empty threshold, is valid only when dmac as flow controller"] +pub type DSI_RAW_BUF_ALMOST_EMPTY_THRD_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - this field configures the fifo almost empty threshold, is valid only when dmac as flow controller"] + #[inline(always)] + pub fn dsi_raw_buf_almost_empty_thrd(&self) -> DSI_RAW_BUF_ALMOST_EMPTY_THRD_R { + DSI_RAW_BUF_ALMOST_EMPTY_THRD_R::new((self.bits & 0x07ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RAW_BUF_ALMOST_EMPTY_THRD") + .field( + "dsi_raw_buf_almost_empty_thrd", + &format_args!("{}", self.dsi_raw_buf_almost_empty_thrd().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:10 - this field configures the fifo almost empty threshold, is valid only when dmac as flow controller"] + #[inline(always)] + #[must_use] + pub fn dsi_raw_buf_almost_empty_thrd( + &mut self, + ) -> DSI_RAW_BUF_ALMOST_EMPTY_THRD_W { + DSI_RAW_BUF_ALMOST_EMPTY_THRD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge buffer empty threshold register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_buf_almost_empty_thrd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_buf_almost_empty_thrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAW_BUF_ALMOST_EMPTY_THRD_SPEC; +impl crate::RegisterSpec for RAW_BUF_ALMOST_EMPTY_THRD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`raw_buf_almost_empty_thrd::R`](R) reader structure"] +impl crate::Readable for RAW_BUF_ALMOST_EMPTY_THRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`raw_buf_almost_empty_thrd::W`](W) writer structure"] +impl crate::Writable for RAW_BUF_ALMOST_EMPTY_THRD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RAW_BUF_ALMOST_EMPTY_THRD to value 0x0200"] +impl crate::Resettable for RAW_BUF_ALMOST_EMPTY_THRD_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/esp32p4/src/mipi_dsi_bridge/raw_buf_credit_ctl.rs b/esp32p4/src/mipi_dsi_bridge/raw_buf_credit_ctl.rs new file mode 100644 index 0000000000..c891a535b8 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/raw_buf_credit_ctl.rs @@ -0,0 +1,104 @@ +#[doc = "Register `RAW_BUF_CREDIT_CTL` reader"] +pub type R = crate::R; +#[doc = "Register `RAW_BUF_CREDIT_CTL` writer"] +pub type W = crate::W; +#[doc = "Field `CREDIT_THRD` reader - this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller"] +pub type CREDIT_THRD_R = crate::FieldReader; +#[doc = "Field `CREDIT_THRD` writer - this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller"] +pub type CREDIT_THRD_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `CREDIT_BURST_THRD` reader - this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller"] +pub type CREDIT_BURST_THRD_R = crate::FieldReader; +#[doc = "Field `CREDIT_BURST_THRD` writer - this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller"] +pub type CREDIT_BURST_THRD_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `CREDIT_RESET` reader - this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller"] +pub type CREDIT_RESET_R = crate::BitReader; +#[doc = "Field `CREDIT_RESET` writer - this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller"] +pub type CREDIT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:14 - this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller"] + #[inline(always)] + pub fn credit_thrd(&self) -> CREDIT_THRD_R { + CREDIT_THRD_R::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bits 16:30 - this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller"] + #[inline(always)] + pub fn credit_burst_thrd(&self) -> CREDIT_BURST_THRD_R { + CREDIT_BURST_THRD_R::new(((self.bits >> 16) & 0x7fff) as u16) + } + #[doc = "Bit 31 - this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller"] + #[inline(always)] + pub fn credit_reset(&self) -> CREDIT_RESET_R { + CREDIT_RESET_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RAW_BUF_CREDIT_CTL") + .field( + "credit_thrd", + &format_args!("{}", self.credit_thrd().bits()), + ) + .field( + "credit_burst_thrd", + &format_args!("{}", self.credit_burst_thrd().bits()), + ) + .field( + "credit_reset", + &format_args!("{}", self.credit_reset().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:14 - this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller"] + #[inline(always)] + #[must_use] + pub fn credit_thrd(&mut self) -> CREDIT_THRD_W { + CREDIT_THRD_W::new(self, 0) + } + #[doc = "Bits 16:30 - this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller"] + #[inline(always)] + #[must_use] + pub fn credit_burst_thrd(&mut self) -> CREDIT_BURST_THRD_W { + CREDIT_BURST_THRD_W::new(self, 16) + } + #[doc = "Bit 31 - this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller"] + #[inline(always)] + #[must_use] + pub fn credit_reset(&mut self) -> CREDIT_RESET_W { + CREDIT_RESET_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge credit register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_buf_credit_ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_buf_credit_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAW_BUF_CREDIT_CTL_SPEC; +impl crate::RegisterSpec for RAW_BUF_CREDIT_CTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`raw_buf_credit_ctl::R`](R) reader structure"] +impl crate::Readable for RAW_BUF_CREDIT_CTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`raw_buf_credit_ctl::W`](W) writer structure"] +impl crate::Writable for RAW_BUF_CREDIT_CTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RAW_BUF_CREDIT_CTL to value 0x0320_0400"] +impl crate::Resettable for RAW_BUF_CREDIT_CTL_SPEC { + const RESET_VALUE: Self::Ux = 0x0320_0400; +} diff --git a/esp32p4/src/mipi_dsi_bridge/raw_num_cfg.rs b/esp32p4/src/mipi_dsi_bridge/raw_num_cfg.rs new file mode 100644 index 0000000000..4e3f853007 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/raw_num_cfg.rs @@ -0,0 +1,93 @@ +#[doc = "Register `RAW_NUM_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `RAW_NUM_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `RAW_NUM_TOTAL` reader - this field configures number of total pix bits/64"] +pub type RAW_NUM_TOTAL_R = crate::FieldReader; +#[doc = "Field `RAW_NUM_TOTAL` writer - this field configures number of total pix bits/64"] +pub type RAW_NUM_TOTAL_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +#[doc = "Field `UNALIGN_64BIT_EN` reader - this field configures whether the total pix bits is a multiple of 64bits. 0: align to 64-bit, 1: unalign to 64-bit"] +pub type UNALIGN_64BIT_EN_R = crate::BitReader; +#[doc = "Field `UNALIGN_64BIT_EN` writer - this field configures whether the total pix bits is a multiple of 64bits. 0: align to 64-bit, 1: unalign to 64-bit"] +pub type UNALIGN_64BIT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAW_NUM_TOTAL_SET` writer - this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, 1: enable. valid only when dsi_bridge as flow controller"] +pub type RAW_NUM_TOTAL_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:21 - this field configures number of total pix bits/64"] + #[inline(always)] + pub fn raw_num_total(&self) -> RAW_NUM_TOTAL_R { + RAW_NUM_TOTAL_R::new(self.bits & 0x003f_ffff) + } + #[doc = "Bit 22 - this field configures whether the total pix bits is a multiple of 64bits. 0: align to 64-bit, 1: unalign to 64-bit"] + #[inline(always)] + pub fn unalign_64bit_en(&self) -> UNALIGN_64BIT_EN_R { + UNALIGN_64BIT_EN_R::new(((self.bits >> 22) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RAW_NUM_CFG") + .field( + "raw_num_total", + &format_args!("{}", self.raw_num_total().bits()), + ) + .field( + "unalign_64bit_en", + &format_args!("{}", self.unalign_64bit_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:21 - this field configures number of total pix bits/64"] + #[inline(always)] + #[must_use] + pub fn raw_num_total(&mut self) -> RAW_NUM_TOTAL_W { + RAW_NUM_TOTAL_W::new(self, 0) + } + #[doc = "Bit 22 - this field configures whether the total pix bits is a multiple of 64bits. 0: align to 64-bit, 1: unalign to 64-bit"] + #[inline(always)] + #[must_use] + pub fn unalign_64bit_en(&mut self) -> UNALIGN_64BIT_EN_W { + UNALIGN_64BIT_EN_W::new(self, 22) + } + #[doc = "Bit 31 - this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, 1: enable. valid only when dsi_bridge as flow controller"] + #[inline(always)] + #[must_use] + pub fn raw_num_total_set(&mut self) -> RAW_NUM_TOTAL_SET_W { + RAW_NUM_TOTAL_SET_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi bridge raw number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_num_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`raw_num_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAW_NUM_CFG_SPEC; +impl crate::RegisterSpec for RAW_NUM_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`raw_num_cfg::R`](R) reader structure"] +impl crate::Readable for RAW_NUM_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`raw_num_cfg::W`](W) writer structure"] +impl crate::Writable for RAW_NUM_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RAW_NUM_CFG to value 0x0003_8400"] +impl crate::Resettable for RAW_NUM_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0003_8400; +} diff --git a/esp32p4/src/mipi_dsi_bridge/rdn_eco_cs.rs b/esp32p4/src/mipi_dsi_bridge/rdn_eco_cs.rs new file mode 100644 index 0000000000..b3de245e26 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/rdn_eco_cs.rs @@ -0,0 +1,74 @@ +#[doc = "Register `RDN_ECO_CS` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_CS` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_EN` reader - rdn_eco_en"] +pub type RDN_ECO_EN_R = crate::BitReader; +#[doc = "Field `RDN_ECO_EN` writer - rdn_eco_en"] +pub type RDN_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RDN_ECO_RESULT` reader - rdn_eco_result"] +pub type RDN_ECO_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - rdn_eco_en"] + #[inline(always)] + pub fn rdn_eco_en(&self) -> RDN_ECO_EN_R { + RDN_ECO_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - rdn_eco_result"] + #[inline(always)] + pub fn rdn_eco_result(&self) -> RDN_ECO_RESULT_R { + RDN_ECO_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_CS") + .field("rdn_eco_en", &format_args!("{}", self.rdn_eco_en().bit())) + .field( + "rdn_eco_result", + &format_args!("{}", self.rdn_eco_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - rdn_eco_en"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_en(&mut self) -> RDN_ECO_EN_W { + RDN_ECO_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge rdn eco cs register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_CS_SPEC; +impl crate::RegisterSpec for RDN_ECO_CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_cs::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_cs::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_CS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_CS to value 0"] +impl crate::Resettable for RDN_ECO_CS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/rdn_eco_high.rs b/esp32p4/src/mipi_dsi_bridge/rdn_eco_high.rs new file mode 100644 index 0000000000..c5c3954c9f --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/rdn_eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RDN_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_HIGH` reader - rdn_eco_high"] +pub type RDN_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_HIGH` writer - rdn_eco_high"] +pub type RDN_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - rdn_eco_high"] + #[inline(always)] + pub fn rdn_eco_high(&self) -> RDN_ECO_HIGH_R { + RDN_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_HIGH") + .field( + "rdn_eco_high", + &format_args!("{}", self.rdn_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - rdn_eco_high"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_high(&mut self) -> RDN_ECO_HIGH_W { + RDN_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge rdn eco all high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_HIGH_SPEC; +impl crate::RegisterSpec for RDN_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_high::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_high::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for RDN_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/mipi_dsi_bridge/rdn_eco_low.rs b/esp32p4/src/mipi_dsi_bridge/rdn_eco_low.rs new file mode 100644 index 0000000000..4a29348aa2 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/rdn_eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `RDN_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ECO_LOW` reader - rdn_eco_low"] +pub type RDN_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `RDN_ECO_LOW` writer - rdn_eco_low"] +pub type RDN_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - rdn_eco_low"] + #[inline(always)] + pub fn rdn_eco_low(&self) -> RDN_ECO_LOW_R { + RDN_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO_LOW") + .field( + "rdn_eco_low", + &format_args!("{}", self.rdn_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - rdn_eco_low"] + #[inline(always)] + #[must_use] + pub fn rdn_eco_low(&mut self) -> RDN_ECO_LOW_W { + RDN_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge rdn eco all low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_LOW_SPEC; +impl crate::RegisterSpec for RDN_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco_low::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco_low::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO_LOW to value 0"] +impl crate::Resettable for RDN_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_bridge/yuv_cfg.rs b/esp32p4/src/mipi_dsi_bridge/yuv_cfg.rs new file mode 100644 index 0000000000..8ac34c4db3 --- /dev/null +++ b/esp32p4/src/mipi_dsi_bridge/yuv_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `YUV_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `YUV_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `PROTOCAL` reader - this bit configures yuv protoocl, 0: bt.601, 1: bt.709"] +pub type PROTOCAL_R = crate::BitReader; +#[doc = "Field `PROTOCAL` writer - this bit configures yuv protoocl, 0: bt.601, 1: bt.709"] +pub type PROTOCAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `YUV_PIX_ENDIAN` reader - this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0"] +pub type YUV_PIX_ENDIAN_R = crate::BitReader; +#[doc = "Field `YUV_PIX_ENDIAN` writer - this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0"] +pub type YUV_PIX_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `YUV422_FORMAT` reader - this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy"] +pub type YUV422_FORMAT_R = crate::FieldReader; +#[doc = "Field `YUV422_FORMAT` writer - this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy"] +pub type YUV422_FORMAT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - this bit configures yuv protoocl, 0: bt.601, 1: bt.709"] + #[inline(always)] + pub fn protocal(&self) -> PROTOCAL_R { + PROTOCAL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0"] + #[inline(always)] + pub fn yuv_pix_endian(&self) -> YUV_PIX_ENDIAN_R { + YUV_PIX_ENDIAN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy"] + #[inline(always)] + pub fn yuv422_format(&self) -> YUV422_FORMAT_R { + YUV422_FORMAT_R::new(((self.bits >> 2) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("YUV_CFG") + .field("protocal", &format_args!("{}", self.protocal().bit())) + .field( + "yuv_pix_endian", + &format_args!("{}", self.yuv_pix_endian().bit()), + ) + .field( + "yuv422_format", + &format_args!("{}", self.yuv422_format().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - this bit configures yuv protoocl, 0: bt.601, 1: bt.709"] + #[inline(always)] + #[must_use] + pub fn protocal(&mut self) -> PROTOCAL_W { + PROTOCAL_W::new(self, 0) + } + #[doc = "Bit 1 - this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0"] + #[inline(always)] + #[must_use] + pub fn yuv_pix_endian(&mut self) -> YUV_PIX_ENDIAN_W { + YUV_PIX_ENDIAN_W::new(self, 1) + } + #[doc = "Bits 2:3 - this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy"] + #[inline(always)] + #[must_use] + pub fn yuv422_format(&mut self) -> YUV422_FORMAT_W { + YUV422_FORMAT_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "dsi_bridge yuv format config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`yuv_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`yuv_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct YUV_CFG_SPEC; +impl crate::RegisterSpec for YUV_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`yuv_cfg::R`](R) reader structure"] +impl crate::Readable for YUV_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`yuv_cfg::W`](W) writer structure"] +impl crate::Writable for YUV_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets YUV_CFG to value 0"] +impl crate::Resettable for YUV_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host.rs b/esp32p4/src/mipi_dsi_host.rs new file mode 100644 index 0000000000..e56bb7de7b --- /dev/null +++ b/esp32p4/src/mipi_dsi_host.rs @@ -0,0 +1,755 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + version: VERSION, + pwr_up: PWR_UP, + clkmgr_cfg: CLKMGR_CFG, + dpi_vcid: DPI_VCID, + dpi_color_coding: DPI_COLOR_CODING, + dpi_cfg_pol: DPI_CFG_POL, + dpi_lp_cmd_tim: DPI_LP_CMD_TIM, + dbi_vcid: DBI_VCID, + dbi_cfg: DBI_CFG, + dbi_partitioning_en: DBI_PARTITIONING_EN, + dbi_cmdsize: DBI_CMDSIZE, + pckhdl_cfg: PCKHDL_CFG, + gen_vcid: GEN_VCID, + mode_cfg: MODE_CFG, + vid_mode_cfg: VID_MODE_CFG, + vid_pkt_size: VID_PKT_SIZE, + vid_num_chunks: VID_NUM_CHUNKS, + vid_null_size: VID_NULL_SIZE, + vid_hsa_time: VID_HSA_TIME, + vid_hbp_time: VID_HBP_TIME, + vid_hline_time: VID_HLINE_TIME, + vid_vsa_lines: VID_VSA_LINES, + vid_vbp_lines: VID_VBP_LINES, + vid_vfp_lines: VID_VFP_LINES, + vid_vactive_lines: VID_VACTIVE_LINES, + edpi_cmd_size: EDPI_CMD_SIZE, + cmd_mode_cfg: CMD_MODE_CFG, + gen_hdr: GEN_HDR, + gen_pld_data: GEN_PLD_DATA, + cmd_pkt_status: CMD_PKT_STATUS, + to_cnt_cfg: TO_CNT_CFG, + hs_rd_to_cnt: HS_RD_TO_CNT, + lp_rd_to_cnt: LP_RD_TO_CNT, + hs_wr_to_cnt: HS_WR_TO_CNT, + lp_wr_to_cnt: LP_WR_TO_CNT, + bta_to_cnt: BTA_TO_CNT, + sdf_3d: SDF_3D, + lpclk_ctrl: LPCLK_CTRL, + phy_tmr_lpclk_cfg: PHY_TMR_LPCLK_CFG, + phy_tmr_cfg: PHY_TMR_CFG, + phy_rstz: PHY_RSTZ, + phy_if_cfg: PHY_IF_CFG, + phy_ulps_ctrl: PHY_ULPS_CTRL, + phy_tx_triggers: PHY_TX_TRIGGERS, + phy_status: PHY_STATUS, + phy_tst_ctrl0: PHY_TST_CTRL0, + phy_tst_ctrl1: PHY_TST_CTRL1, + int_st0: INT_ST0, + int_st1: INT_ST1, + int_msk0: INT_MSK0, + int_msk1: INT_MSK1, + phy_cal: PHY_CAL, + _reserved52: [u8; 0x08], + int_force0: INT_FORCE0, + int_force1: INT_FORCE1, + _reserved54: [u8; 0x10], + dsc_parameter: DSC_PARAMETER, + phy_tmr_rd_cfg: PHY_TMR_RD_CFG, + _reserved56: [u8; 0x08], + vid_shadow_ctrl: VID_SHADOW_CTRL, + _reserved57: [u8; 0x08], + dpi_vcid_act: DPI_VCID_ACT, + dpi_color_coding_act: DPI_COLOR_CODING_ACT, + _reserved59: [u8; 0x04], + dpi_lp_cmd_tim_act: DPI_LP_CMD_TIM_ACT, + edpi_te_hw_cfg: EDPI_TE_HW_CFG, + _reserved61: [u8; 0x18], + vid_mode_cfg_act: VID_MODE_CFG_ACT, + vid_pkt_size_act: VID_PKT_SIZE_ACT, + vid_num_chunks_act: VID_NUM_CHUNKS_ACT, + vid_null_size_act: VID_NULL_SIZE_ACT, + vid_hsa_time_act: VID_HSA_TIME_ACT, + vid_hbp_time_act: VID_HBP_TIME_ACT, + vid_hline_time_act: VID_HLINE_TIME_ACT, + vid_vsa_lines_act: VID_VSA_LINES_ACT, + vid_vbp_lines_act: VID_VBP_LINES_ACT, + vid_vfp_lines_act: VID_VFP_LINES_ACT, + vid_vactive_lines_act: VID_VACTIVE_LINES_ACT, + _reserved72: [u8; 0x04], + vid_pkt_status: VID_PKT_STATUS, + _reserved73: [u8; 0x24], + sdf_3d_act: SDF_3D_ACT, +} +impl RegisterBlock { + #[doc = "0x00 - NA"] + #[inline(always)] + pub const fn version(&self) -> &VERSION { + &self.version + } + #[doc = "0x04 - NA"] + #[inline(always)] + pub const fn pwr_up(&self) -> &PWR_UP { + &self.pwr_up + } + #[doc = "0x08 - NA"] + #[inline(always)] + pub const fn clkmgr_cfg(&self) -> &CLKMGR_CFG { + &self.clkmgr_cfg + } + #[doc = "0x0c - NA"] + #[inline(always)] + pub const fn dpi_vcid(&self) -> &DPI_VCID { + &self.dpi_vcid + } + #[doc = "0x10 - NA"] + #[inline(always)] + pub const fn dpi_color_coding(&self) -> &DPI_COLOR_CODING { + &self.dpi_color_coding + } + #[doc = "0x14 - NA"] + #[inline(always)] + pub const fn dpi_cfg_pol(&self) -> &DPI_CFG_POL { + &self.dpi_cfg_pol + } + #[doc = "0x18 - NA"] + #[inline(always)] + pub const fn dpi_lp_cmd_tim(&self) -> &DPI_LP_CMD_TIM { + &self.dpi_lp_cmd_tim + } + #[doc = "0x1c - NA"] + #[inline(always)] + pub const fn dbi_vcid(&self) -> &DBI_VCID { + &self.dbi_vcid + } + #[doc = "0x20 - NA"] + #[inline(always)] + pub const fn dbi_cfg(&self) -> &DBI_CFG { + &self.dbi_cfg + } + #[doc = "0x24 - NA"] + #[inline(always)] + pub const fn dbi_partitioning_en(&self) -> &DBI_PARTITIONING_EN { + &self.dbi_partitioning_en + } + #[doc = "0x28 - NA"] + #[inline(always)] + pub const fn dbi_cmdsize(&self) -> &DBI_CMDSIZE { + &self.dbi_cmdsize + } + #[doc = "0x2c - NA"] + #[inline(always)] + pub const fn pckhdl_cfg(&self) -> &PCKHDL_CFG { + &self.pckhdl_cfg + } + #[doc = "0x30 - NA"] + #[inline(always)] + pub const fn gen_vcid(&self) -> &GEN_VCID { + &self.gen_vcid + } + #[doc = "0x34 - NA"] + #[inline(always)] + pub const fn mode_cfg(&self) -> &MODE_CFG { + &self.mode_cfg + } + #[doc = "0x38 - NA"] + #[inline(always)] + pub const fn vid_mode_cfg(&self) -> &VID_MODE_CFG { + &self.vid_mode_cfg + } + #[doc = "0x3c - NA"] + #[inline(always)] + pub const fn vid_pkt_size(&self) -> &VID_PKT_SIZE { + &self.vid_pkt_size + } + #[doc = "0x40 - NA"] + #[inline(always)] + pub const fn vid_num_chunks(&self) -> &VID_NUM_CHUNKS { + &self.vid_num_chunks + } + #[doc = "0x44 - NA"] + #[inline(always)] + pub const fn vid_null_size(&self) -> &VID_NULL_SIZE { + &self.vid_null_size + } + #[doc = "0x48 - NA"] + #[inline(always)] + pub const fn vid_hsa_time(&self) -> &VID_HSA_TIME { + &self.vid_hsa_time + } + #[doc = "0x4c - NA"] + #[inline(always)] + pub const fn vid_hbp_time(&self) -> &VID_HBP_TIME { + &self.vid_hbp_time + } + #[doc = "0x50 - NA"] + #[inline(always)] + pub const fn vid_hline_time(&self) -> &VID_HLINE_TIME { + &self.vid_hline_time + } + #[doc = "0x54 - NA"] + #[inline(always)] + pub const fn vid_vsa_lines(&self) -> &VID_VSA_LINES { + &self.vid_vsa_lines + } + #[doc = "0x58 - NA"] + #[inline(always)] + pub const fn vid_vbp_lines(&self) -> &VID_VBP_LINES { + &self.vid_vbp_lines + } + #[doc = "0x5c - NA"] + #[inline(always)] + pub const fn vid_vfp_lines(&self) -> &VID_VFP_LINES { + &self.vid_vfp_lines + } + #[doc = "0x60 - NA"] + #[inline(always)] + pub const fn vid_vactive_lines(&self) -> &VID_VACTIVE_LINES { + &self.vid_vactive_lines + } + #[doc = "0x64 - NA"] + #[inline(always)] + pub const fn edpi_cmd_size(&self) -> &EDPI_CMD_SIZE { + &self.edpi_cmd_size + } + #[doc = "0x68 - NA"] + #[inline(always)] + pub const fn cmd_mode_cfg(&self) -> &CMD_MODE_CFG { + &self.cmd_mode_cfg + } + #[doc = "0x6c - NA"] + #[inline(always)] + pub const fn gen_hdr(&self) -> &GEN_HDR { + &self.gen_hdr + } + #[doc = "0x70 - NA"] + #[inline(always)] + pub const fn gen_pld_data(&self) -> &GEN_PLD_DATA { + &self.gen_pld_data + } + #[doc = "0x74 - NA"] + #[inline(always)] + pub const fn cmd_pkt_status(&self) -> &CMD_PKT_STATUS { + &self.cmd_pkt_status + } + #[doc = "0x78 - NA"] + #[inline(always)] + pub const fn to_cnt_cfg(&self) -> &TO_CNT_CFG { + &self.to_cnt_cfg + } + #[doc = "0x7c - NA"] + #[inline(always)] + pub const fn hs_rd_to_cnt(&self) -> &HS_RD_TO_CNT { + &self.hs_rd_to_cnt + } + #[doc = "0x80 - NA"] + #[inline(always)] + pub const fn lp_rd_to_cnt(&self) -> &LP_RD_TO_CNT { + &self.lp_rd_to_cnt + } + #[doc = "0x84 - NA"] + #[inline(always)] + pub const fn hs_wr_to_cnt(&self) -> &HS_WR_TO_CNT { + &self.hs_wr_to_cnt + } + #[doc = "0x88 - NA"] + #[inline(always)] + pub const fn lp_wr_to_cnt(&self) -> &LP_WR_TO_CNT { + &self.lp_wr_to_cnt + } + #[doc = "0x8c - NA"] + #[inline(always)] + pub const fn bta_to_cnt(&self) -> &BTA_TO_CNT { + &self.bta_to_cnt + } + #[doc = "0x90 - NA"] + #[inline(always)] + pub const fn sdf_3d(&self) -> &SDF_3D { + &self.sdf_3d + } + #[doc = "0x94 - NA"] + #[inline(always)] + pub const fn lpclk_ctrl(&self) -> &LPCLK_CTRL { + &self.lpclk_ctrl + } + #[doc = "0x98 - NA"] + #[inline(always)] + pub const fn phy_tmr_lpclk_cfg(&self) -> &PHY_TMR_LPCLK_CFG { + &self.phy_tmr_lpclk_cfg + } + #[doc = "0x9c - NA"] + #[inline(always)] + pub const fn phy_tmr_cfg(&self) -> &PHY_TMR_CFG { + &self.phy_tmr_cfg + } + #[doc = "0xa0 - NA"] + #[inline(always)] + pub const fn phy_rstz(&self) -> &PHY_RSTZ { + &self.phy_rstz + } + #[doc = "0xa4 - NA"] + #[inline(always)] + pub const fn phy_if_cfg(&self) -> &PHY_IF_CFG { + &self.phy_if_cfg + } + #[doc = "0xa8 - NA"] + #[inline(always)] + pub const fn phy_ulps_ctrl(&self) -> &PHY_ULPS_CTRL { + &self.phy_ulps_ctrl + } + #[doc = "0xac - NA"] + #[inline(always)] + pub const fn phy_tx_triggers(&self) -> &PHY_TX_TRIGGERS { + &self.phy_tx_triggers + } + #[doc = "0xb0 - NA"] + #[inline(always)] + pub const fn phy_status(&self) -> &PHY_STATUS { + &self.phy_status + } + #[doc = "0xb4 - NA"] + #[inline(always)] + pub const fn phy_tst_ctrl0(&self) -> &PHY_TST_CTRL0 { + &self.phy_tst_ctrl0 + } + #[doc = "0xb8 - NA"] + #[inline(always)] + pub const fn phy_tst_ctrl1(&self) -> &PHY_TST_CTRL1 { + &self.phy_tst_ctrl1 + } + #[doc = "0xbc - NA"] + #[inline(always)] + pub const fn int_st0(&self) -> &INT_ST0 { + &self.int_st0 + } + #[doc = "0xc0 - NA"] + #[inline(always)] + pub const fn int_st1(&self) -> &INT_ST1 { + &self.int_st1 + } + #[doc = "0xc4 - NA"] + #[inline(always)] + pub const fn int_msk0(&self) -> &INT_MSK0 { + &self.int_msk0 + } + #[doc = "0xc8 - NA"] + #[inline(always)] + pub const fn int_msk1(&self) -> &INT_MSK1 { + &self.int_msk1 + } + #[doc = "0xcc - NA"] + #[inline(always)] + pub const fn phy_cal(&self) -> &PHY_CAL { + &self.phy_cal + } + #[doc = "0xd8 - NA"] + #[inline(always)] + pub const fn int_force0(&self) -> &INT_FORCE0 { + &self.int_force0 + } + #[doc = "0xdc - NA"] + #[inline(always)] + pub const fn int_force1(&self) -> &INT_FORCE1 { + &self.int_force1 + } + #[doc = "0xf0 - NA"] + #[inline(always)] + pub const fn dsc_parameter(&self) -> &DSC_PARAMETER { + &self.dsc_parameter + } + #[doc = "0xf4 - NA"] + #[inline(always)] + pub const fn phy_tmr_rd_cfg(&self) -> &PHY_TMR_RD_CFG { + &self.phy_tmr_rd_cfg + } + #[doc = "0x100 - NA"] + #[inline(always)] + pub const fn vid_shadow_ctrl(&self) -> &VID_SHADOW_CTRL { + &self.vid_shadow_ctrl + } + #[doc = "0x10c - NA"] + #[inline(always)] + pub const fn dpi_vcid_act(&self) -> &DPI_VCID_ACT { + &self.dpi_vcid_act + } + #[doc = "0x110 - NA"] + #[inline(always)] + pub const fn dpi_color_coding_act(&self) -> &DPI_COLOR_CODING_ACT { + &self.dpi_color_coding_act + } + #[doc = "0x118 - NA"] + #[inline(always)] + pub const fn dpi_lp_cmd_tim_act(&self) -> &DPI_LP_CMD_TIM_ACT { + &self.dpi_lp_cmd_tim_act + } + #[doc = "0x11c - NA"] + #[inline(always)] + pub const fn edpi_te_hw_cfg(&self) -> &EDPI_TE_HW_CFG { + &self.edpi_te_hw_cfg + } + #[doc = "0x138 - NA"] + #[inline(always)] + pub const fn vid_mode_cfg_act(&self) -> &VID_MODE_CFG_ACT { + &self.vid_mode_cfg_act + } + #[doc = "0x13c - NA"] + #[inline(always)] + pub const fn vid_pkt_size_act(&self) -> &VID_PKT_SIZE_ACT { + &self.vid_pkt_size_act + } + #[doc = "0x140 - NA"] + #[inline(always)] + pub const fn vid_num_chunks_act(&self) -> &VID_NUM_CHUNKS_ACT { + &self.vid_num_chunks_act + } + #[doc = "0x144 - NA"] + #[inline(always)] + pub const fn vid_null_size_act(&self) -> &VID_NULL_SIZE_ACT { + &self.vid_null_size_act + } + #[doc = "0x148 - NA"] + #[inline(always)] + pub const fn vid_hsa_time_act(&self) -> &VID_HSA_TIME_ACT { + &self.vid_hsa_time_act + } + #[doc = "0x14c - NA"] + #[inline(always)] + pub const fn vid_hbp_time_act(&self) -> &VID_HBP_TIME_ACT { + &self.vid_hbp_time_act + } + #[doc = "0x150 - NA"] + #[inline(always)] + pub const fn vid_hline_time_act(&self) -> &VID_HLINE_TIME_ACT { + &self.vid_hline_time_act + } + #[doc = "0x154 - NA"] + #[inline(always)] + pub const fn vid_vsa_lines_act(&self) -> &VID_VSA_LINES_ACT { + &self.vid_vsa_lines_act + } + #[doc = "0x158 - NA"] + #[inline(always)] + pub const fn vid_vbp_lines_act(&self) -> &VID_VBP_LINES_ACT { + &self.vid_vbp_lines_act + } + #[doc = "0x15c - NA"] + #[inline(always)] + pub const fn vid_vfp_lines_act(&self) -> &VID_VFP_LINES_ACT { + &self.vid_vfp_lines_act + } + #[doc = "0x160 - NA"] + #[inline(always)] + pub const fn vid_vactive_lines_act(&self) -> &VID_VACTIVE_LINES_ACT { + &self.vid_vactive_lines_act + } + #[doc = "0x168 - NA"] + #[inline(always)] + pub const fn vid_pkt_status(&self) -> &VID_PKT_STATUS { + &self.vid_pkt_status + } + #[doc = "0x190 - NA"] + #[inline(always)] + pub const fn sdf_3d_act(&self) -> &SDF_3D_ACT { + &self.sdf_3d_act + } +} +#[doc = "VERSION (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"] +pub type VERSION = crate::Reg; +#[doc = "NA"] +pub mod version; +#[doc = "PWR_UP (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwr_up::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwr_up::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwr_up`] module"] +pub type PWR_UP = crate::Reg; +#[doc = "NA"] +pub mod pwr_up; +#[doc = "CLKMGR_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkmgr_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkmgr_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkmgr_cfg`] module"] +pub type CLKMGR_CFG = crate::Reg; +#[doc = "NA"] +pub mod clkmgr_cfg; +#[doc = "DPI_VCID (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_vcid::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_vcid::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_vcid`] module"] +pub type DPI_VCID = crate::Reg; +#[doc = "NA"] +pub mod dpi_vcid; +#[doc = "DPI_COLOR_CODING (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_color_coding::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_color_coding::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_color_coding`] module"] +pub type DPI_COLOR_CODING = crate::Reg; +#[doc = "NA"] +pub mod dpi_color_coding; +#[doc = "DPI_CFG_POL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_cfg_pol::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_cfg_pol::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_cfg_pol`] module"] +pub type DPI_CFG_POL = crate::Reg; +#[doc = "NA"] +pub mod dpi_cfg_pol; +#[doc = "DPI_LP_CMD_TIM (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_lp_cmd_tim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_lp_cmd_tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_lp_cmd_tim`] module"] +pub type DPI_LP_CMD_TIM = crate::Reg; +#[doc = "NA"] +pub mod dpi_lp_cmd_tim; +#[doc = "DBI_VCID (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_vcid::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_vcid::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_vcid`] module"] +pub type DBI_VCID = crate::Reg; +#[doc = "NA"] +pub mod dbi_vcid; +#[doc = "DBI_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_cfg`] module"] +pub type DBI_CFG = crate::Reg; +#[doc = "NA"] +pub mod dbi_cfg; +#[doc = "DBI_PARTITIONING_EN (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_partitioning_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_partitioning_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_partitioning_en`] module"] +pub type DBI_PARTITIONING_EN = crate::Reg; +#[doc = "NA"] +pub mod dbi_partitioning_en; +#[doc = "DBI_CMDSIZE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_cmdsize::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_cmdsize::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbi_cmdsize`] module"] +pub type DBI_CMDSIZE = crate::Reg; +#[doc = "NA"] +pub mod dbi_cmdsize; +#[doc = "PCKHDL_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pckhdl_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pckhdl_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pckhdl_cfg`] module"] +pub type PCKHDL_CFG = crate::Reg; +#[doc = "NA"] +pub mod pckhdl_cfg; +#[doc = "GEN_VCID (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_vcid::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_vcid::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_vcid`] module"] +pub type GEN_VCID = crate::Reg; +#[doc = "NA"] +pub mod gen_vcid; +#[doc = "MODE_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode_cfg`] module"] +pub type MODE_CFG = crate::Reg; +#[doc = "NA"] +pub mod mode_cfg; +#[doc = "VID_MODE_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_mode_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_mode_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_mode_cfg`] module"] +pub type VID_MODE_CFG = crate::Reg; +#[doc = "NA"] +pub mod vid_mode_cfg; +#[doc = "VID_PKT_SIZE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_pkt_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_pkt_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_pkt_size`] module"] +pub type VID_PKT_SIZE = crate::Reg; +#[doc = "NA"] +pub mod vid_pkt_size; +#[doc = "VID_NUM_CHUNKS (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_num_chunks::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_num_chunks::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_num_chunks`] module"] +pub type VID_NUM_CHUNKS = crate::Reg; +#[doc = "NA"] +pub mod vid_num_chunks; +#[doc = "VID_NULL_SIZE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_null_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_null_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_null_size`] module"] +pub type VID_NULL_SIZE = crate::Reg; +#[doc = "NA"] +pub mod vid_null_size; +#[doc = "VID_HSA_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hsa_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_hsa_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_hsa_time`] module"] +pub type VID_HSA_TIME = crate::Reg; +#[doc = "NA"] +pub mod vid_hsa_time; +#[doc = "VID_HBP_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hbp_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_hbp_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_hbp_time`] module"] +pub type VID_HBP_TIME = crate::Reg; +#[doc = "NA"] +pub mod vid_hbp_time; +#[doc = "VID_HLINE_TIME (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hline_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_hline_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_hline_time`] module"] +pub type VID_HLINE_TIME = crate::Reg; +#[doc = "NA"] +pub mod vid_hline_time; +#[doc = "VID_VSA_LINES (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vsa_lines::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_vsa_lines::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_vsa_lines`] module"] +pub type VID_VSA_LINES = crate::Reg; +#[doc = "NA"] +pub mod vid_vsa_lines; +#[doc = "VID_VBP_LINES (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vbp_lines::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_vbp_lines::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_vbp_lines`] module"] +pub type VID_VBP_LINES = crate::Reg; +#[doc = "NA"] +pub mod vid_vbp_lines; +#[doc = "VID_VFP_LINES (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vfp_lines::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_vfp_lines::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_vfp_lines`] module"] +pub type VID_VFP_LINES = crate::Reg; +#[doc = "NA"] +pub mod vid_vfp_lines; +#[doc = "VID_VACTIVE_LINES (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vactive_lines::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_vactive_lines::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_vactive_lines`] module"] +pub type VID_VACTIVE_LINES = crate::Reg; +#[doc = "NA"] +pub mod vid_vactive_lines; +#[doc = "EDPI_CMD_SIZE (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edpi_cmd_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edpi_cmd_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edpi_cmd_size`] module"] +pub type EDPI_CMD_SIZE = crate::Reg; +#[doc = "NA"] +pub mod edpi_cmd_size; +#[doc = "CMD_MODE_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_mode_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_mode_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_mode_cfg`] module"] +pub type CMD_MODE_CFG = crate::Reg; +#[doc = "NA"] +pub mod cmd_mode_cfg; +#[doc = "GEN_HDR (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_hdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_hdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_hdr`] module"] +pub type GEN_HDR = crate::Reg; +#[doc = "NA"] +pub mod gen_hdr; +#[doc = "GEN_PLD_DATA (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_pld_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_pld_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_pld_data`] module"] +pub type GEN_PLD_DATA = crate::Reg; +#[doc = "NA"] +pub mod gen_pld_data; +#[doc = "CMD_PKT_STATUS (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_pkt_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd_pkt_status`] module"] +pub type CMD_PKT_STATUS = crate::Reg; +#[doc = "NA"] +pub mod cmd_pkt_status; +#[doc = "TO_CNT_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`to_cnt_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`to_cnt_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@to_cnt_cfg`] module"] +pub type TO_CNT_CFG = crate::Reg; +#[doc = "NA"] +pub mod to_cnt_cfg; +#[doc = "HS_RD_TO_CNT (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_rd_to_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_rd_to_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_rd_to_cnt`] module"] +pub type HS_RD_TO_CNT = crate::Reg; +#[doc = "NA"] +pub mod hs_rd_to_cnt; +#[doc = "LP_RD_TO_CNT (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_rd_to_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_rd_to_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_rd_to_cnt`] module"] +pub type LP_RD_TO_CNT = crate::Reg; +#[doc = "NA"] +pub mod lp_rd_to_cnt; +#[doc = "HS_WR_TO_CNT (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_wr_to_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_wr_to_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hs_wr_to_cnt`] module"] +pub type HS_WR_TO_CNT = crate::Reg; +#[doc = "NA"] +pub mod hs_wr_to_cnt; +#[doc = "LP_WR_TO_CNT (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_wr_to_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_wr_to_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_wr_to_cnt`] module"] +pub type LP_WR_TO_CNT = crate::Reg; +#[doc = "NA"] +pub mod lp_wr_to_cnt; +#[doc = "BTA_TO_CNT (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bta_to_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bta_to_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bta_to_cnt`] module"] +pub type BTA_TO_CNT = crate::Reg; +#[doc = "NA"] +pub mod bta_to_cnt; +#[doc = "SDF_3D (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdf_3d::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdf_3d::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdf_3d`] module"] +pub type SDF_3D = crate::Reg; +#[doc = "NA"] +pub mod sdf_3d; +#[doc = "LPCLK_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpclk_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpclk_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpclk_ctrl`] module"] +pub type LPCLK_CTRL = crate::Reg; +#[doc = "NA"] +pub mod lpclk_ctrl; +#[doc = "PHY_TMR_LPCLK_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tmr_lpclk_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tmr_lpclk_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_tmr_lpclk_cfg`] module"] +pub type PHY_TMR_LPCLK_CFG = crate::Reg; +#[doc = "NA"] +pub mod phy_tmr_lpclk_cfg; +#[doc = "PHY_TMR_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tmr_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tmr_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_tmr_cfg`] module"] +pub type PHY_TMR_CFG = crate::Reg; +#[doc = "NA"] +pub mod phy_tmr_cfg; +#[doc = "PHY_RSTZ (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_rstz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_rstz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_rstz`] module"] +pub type PHY_RSTZ = crate::Reg; +#[doc = "NA"] +pub mod phy_rstz; +#[doc = "PHY_IF_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_if_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_if_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_if_cfg`] module"] +pub type PHY_IF_CFG = crate::Reg; +#[doc = "NA"] +pub mod phy_if_cfg; +#[doc = "PHY_ULPS_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_ulps_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_ulps_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_ulps_ctrl`] module"] +pub type PHY_ULPS_CTRL = crate::Reg; +#[doc = "NA"] +pub mod phy_ulps_ctrl; +#[doc = "PHY_TX_TRIGGERS (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tx_triggers::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tx_triggers::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_tx_triggers`] module"] +pub type PHY_TX_TRIGGERS = crate::Reg; +#[doc = "NA"] +pub mod phy_tx_triggers; +#[doc = "PHY_STATUS (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_status`] module"] +pub type PHY_STATUS = crate::Reg; +#[doc = "NA"] +pub mod phy_status; +#[doc = "PHY_TST_CTRL0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tst_ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tst_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_tst_ctrl0`] module"] +pub type PHY_TST_CTRL0 = crate::Reg; +#[doc = "NA"] +pub mod phy_tst_ctrl0; +#[doc = "PHY_TST_CTRL1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tst_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tst_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_tst_ctrl1`] module"] +pub type PHY_TST_CTRL1 = crate::Reg; +#[doc = "NA"] +pub mod phy_tst_ctrl1; +#[doc = "INT_ST0 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st0`] module"] +pub type INT_ST0 = crate::Reg; +#[doc = "NA"] +pub mod int_st0; +#[doc = "INT_ST1 (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st1`] module"] +pub type INT_ST1 = crate::Reg; +#[doc = "NA"] +pub mod int_st1; +#[doc = "INT_MSK0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk0`] module"] +pub type INT_MSK0 = crate::Reg; +#[doc = "NA"] +pub mod int_msk0; +#[doc = "INT_MSK1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_msk1`] module"] +pub type INT_MSK1 = crate::Reg; +#[doc = "NA"] +pub mod int_msk1; +#[doc = "PHY_CAL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_cal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_cal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_cal`] module"] +pub type PHY_CAL = crate::Reg; +#[doc = "NA"] +pub mod phy_cal; +#[doc = "INT_FORCE0 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_force0`] module"] +pub type INT_FORCE0 = crate::Reg; +#[doc = "NA"] +pub mod int_force0; +#[doc = "INT_FORCE1 (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_force1`] module"] +pub type INT_FORCE1 = crate::Reg; +#[doc = "NA"] +pub mod int_force1; +#[doc = "DSC_PARAMETER (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsc_parameter::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsc_parameter::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsc_parameter`] module"] +pub type DSC_PARAMETER = crate::Reg; +#[doc = "NA"] +pub mod dsc_parameter; +#[doc = "PHY_TMR_RD_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tmr_rd_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tmr_rd_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_tmr_rd_cfg`] module"] +pub type PHY_TMR_RD_CFG = crate::Reg; +#[doc = "NA"] +pub mod phy_tmr_rd_cfg; +#[doc = "VID_SHADOW_CTRL (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_shadow_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_shadow_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_shadow_ctrl`] module"] +pub type VID_SHADOW_CTRL = crate::Reg; +#[doc = "NA"] +pub mod vid_shadow_ctrl; +#[doc = "DPI_VCID_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_vcid_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_vcid_act`] module"] +pub type DPI_VCID_ACT = crate::Reg; +#[doc = "NA"] +pub mod dpi_vcid_act; +#[doc = "DPI_COLOR_CODING_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_color_coding_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_color_coding_act`] module"] +pub type DPI_COLOR_CODING_ACT = crate::Reg; +#[doc = "NA"] +pub mod dpi_color_coding_act; +#[doc = "DPI_LP_CMD_TIM_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_lp_cmd_tim_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpi_lp_cmd_tim_act`] module"] +pub type DPI_LP_CMD_TIM_ACT = crate::Reg; +#[doc = "NA"] +pub mod dpi_lp_cmd_tim_act; +#[doc = "EDPI_TE_HW_CFG (rw) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edpi_te_hw_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edpi_te_hw_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edpi_te_hw_cfg`] module"] +pub type EDPI_TE_HW_CFG = crate::Reg; +#[doc = "NA"] +pub mod edpi_te_hw_cfg; +#[doc = "VID_MODE_CFG_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_mode_cfg_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_mode_cfg_act`] module"] +pub type VID_MODE_CFG_ACT = crate::Reg; +#[doc = "NA"] +pub mod vid_mode_cfg_act; +#[doc = "VID_PKT_SIZE_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_pkt_size_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_pkt_size_act`] module"] +pub type VID_PKT_SIZE_ACT = crate::Reg; +#[doc = "NA"] +pub mod vid_pkt_size_act; +#[doc = "VID_NUM_CHUNKS_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_num_chunks_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_num_chunks_act`] module"] +pub type VID_NUM_CHUNKS_ACT = crate::Reg; +#[doc = "NA"] +pub mod vid_num_chunks_act; +#[doc = "VID_NULL_SIZE_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_null_size_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_null_size_act`] module"] +pub type VID_NULL_SIZE_ACT = crate::Reg; +#[doc = "NA"] +pub mod vid_null_size_act; +#[doc = "VID_HSA_TIME_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hsa_time_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_hsa_time_act`] module"] +pub type VID_HSA_TIME_ACT = crate::Reg; +#[doc = "NA"] +pub mod vid_hsa_time_act; +#[doc = "VID_HBP_TIME_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hbp_time_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_hbp_time_act`] module"] +pub type VID_HBP_TIME_ACT = crate::Reg; +#[doc = "NA"] +pub mod vid_hbp_time_act; +#[doc = "VID_HLINE_TIME_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hline_time_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_hline_time_act`] module"] +pub type VID_HLINE_TIME_ACT = crate::Reg; +#[doc = "NA"] +pub mod vid_hline_time_act; +#[doc = "VID_VSA_LINES_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vsa_lines_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_vsa_lines_act`] module"] +pub type VID_VSA_LINES_ACT = crate::Reg; +#[doc = "NA"] +pub mod vid_vsa_lines_act; +#[doc = "VID_VBP_LINES_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vbp_lines_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_vbp_lines_act`] module"] +pub type VID_VBP_LINES_ACT = crate::Reg; +#[doc = "NA"] +pub mod vid_vbp_lines_act; +#[doc = "VID_VFP_LINES_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vfp_lines_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_vfp_lines_act`] module"] +pub type VID_VFP_LINES_ACT = crate::Reg; +#[doc = "NA"] +pub mod vid_vfp_lines_act; +#[doc = "VID_VACTIVE_LINES_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vactive_lines_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_vactive_lines_act`] module"] +pub type VID_VACTIVE_LINES_ACT = crate::Reg; +#[doc = "NA"] +pub mod vid_vactive_lines_act; +#[doc = "VID_PKT_STATUS (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_pkt_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vid_pkt_status`] module"] +pub type VID_PKT_STATUS = crate::Reg; +#[doc = "NA"] +pub mod vid_pkt_status; +#[doc = "SDF_3D_ACT (r) register accessor: NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdf_3d_act::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdf_3d_act`] module"] +pub type SDF_3D_ACT = crate::Reg; +#[doc = "NA"] +pub mod sdf_3d_act; diff --git a/esp32p4/src/mipi_dsi_host/bta_to_cnt.rs b/esp32p4/src/mipi_dsi_host/bta_to_cnt.rs new file mode 100644 index 0000000000..3164b38616 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/bta_to_cnt.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BTA_TO_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `BTA_TO_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `BTA_TO_CNT` reader - NA"] +pub type BTA_TO_CNT_R = crate::FieldReader; +#[doc = "Field `BTA_TO_CNT` writer - NA"] +pub type BTA_TO_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn bta_to_cnt(&self) -> BTA_TO_CNT_R { + BTA_TO_CNT_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BTA_TO_CNT") + .field("bta_to_cnt", &format_args!("{}", self.bta_to_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn bta_to_cnt(&mut self) -> BTA_TO_CNT_W { + BTA_TO_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bta_to_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bta_to_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BTA_TO_CNT_SPEC; +impl crate::RegisterSpec for BTA_TO_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bta_to_cnt::R`](R) reader structure"] +impl crate::Readable for BTA_TO_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bta_to_cnt::W`](W) writer structure"] +impl crate::Writable for BTA_TO_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BTA_TO_CNT to value 0"] +impl crate::Resettable for BTA_TO_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/clkmgr_cfg.rs b/esp32p4/src/mipi_dsi_host/clkmgr_cfg.rs new file mode 100644 index 0000000000..afab826eff --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/clkmgr_cfg.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CLKMGR_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `CLKMGR_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `TX_ESC_CLK_DIVISION` reader - NA"] +pub type TX_ESC_CLK_DIVISION_R = crate::FieldReader; +#[doc = "Field `TX_ESC_CLK_DIVISION` writer - NA"] +pub type TX_ESC_CLK_DIVISION_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TO_CLK_DIVISION` reader - NA"] +pub type TO_CLK_DIVISION_R = crate::FieldReader; +#[doc = "Field `TO_CLK_DIVISION` writer - NA"] +pub type TO_CLK_DIVISION_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + pub fn tx_esc_clk_division(&self) -> TX_ESC_CLK_DIVISION_R { + TX_ESC_CLK_DIVISION_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + pub fn to_clk_division(&self) -> TO_CLK_DIVISION_R { + TO_CLK_DIVISION_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLKMGR_CFG") + .field( + "tx_esc_clk_division", + &format_args!("{}", self.tx_esc_clk_division().bits()), + ) + .field( + "to_clk_division", + &format_args!("{}", self.to_clk_division().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + #[must_use] + pub fn tx_esc_clk_division(&mut self) -> TX_ESC_CLK_DIVISION_W { + TX_ESC_CLK_DIVISION_W::new(self, 0) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + #[must_use] + pub fn to_clk_division(&mut self) -> TO_CLK_DIVISION_W { + TO_CLK_DIVISION_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkmgr_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkmgr_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLKMGR_CFG_SPEC; +impl crate::RegisterSpec for CLKMGR_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkmgr_cfg::R`](R) reader structure"] +impl crate::Readable for CLKMGR_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clkmgr_cfg::W`](W) writer structure"] +impl crate::Writable for CLKMGR_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLKMGR_CFG to value 0"] +impl crate::Resettable for CLKMGR_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/cmd_mode_cfg.rs b/esp32p4/src/mipi_dsi_host/cmd_mode_cfg.rs new file mode 100644 index 0000000000..a09ed79d1d --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/cmd_mode_cfg.rs @@ -0,0 +1,301 @@ +#[doc = "Register `CMD_MODE_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `CMD_MODE_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `TEAR_FX_EN` reader - NA"] +pub type TEAR_FX_EN_R = crate::BitReader; +#[doc = "Field `TEAR_FX_EN` writer - NA"] +pub type TEAR_FX_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACK_RQST_EN` reader - NA"] +pub type ACK_RQST_EN_R = crate::BitReader; +#[doc = "Field `ACK_RQST_EN` writer - NA"] +pub type ACK_RQST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GEN_SW_0P_TX` reader - NA"] +pub type GEN_SW_0P_TX_R = crate::BitReader; +#[doc = "Field `GEN_SW_0P_TX` writer - NA"] +pub type GEN_SW_0P_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GEN_SW_1P_TX` reader - NA"] +pub type GEN_SW_1P_TX_R = crate::BitReader; +#[doc = "Field `GEN_SW_1P_TX` writer - NA"] +pub type GEN_SW_1P_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GEN_SW_2P_TX` reader - NA"] +pub type GEN_SW_2P_TX_R = crate::BitReader; +#[doc = "Field `GEN_SW_2P_TX` writer - NA"] +pub type GEN_SW_2P_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GEN_SR_0P_TX` reader - NA"] +pub type GEN_SR_0P_TX_R = crate::BitReader; +#[doc = "Field `GEN_SR_0P_TX` writer - NA"] +pub type GEN_SR_0P_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GEN_SR_1P_TX` reader - NA"] +pub type GEN_SR_1P_TX_R = crate::BitReader; +#[doc = "Field `GEN_SR_1P_TX` writer - NA"] +pub type GEN_SR_1P_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GEN_SR_2P_TX` reader - NA"] +pub type GEN_SR_2P_TX_R = crate::BitReader; +#[doc = "Field `GEN_SR_2P_TX` writer - NA"] +pub type GEN_SR_2P_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GEN_LW_TX` reader - NA"] +pub type GEN_LW_TX_R = crate::BitReader; +#[doc = "Field `GEN_LW_TX` writer - NA"] +pub type GEN_LW_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCS_SW_0P_TX` reader - NA"] +pub type DCS_SW_0P_TX_R = crate::BitReader; +#[doc = "Field `DCS_SW_0P_TX` writer - NA"] +pub type DCS_SW_0P_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCS_SW_1P_TX` reader - NA"] +pub type DCS_SW_1P_TX_R = crate::BitReader; +#[doc = "Field `DCS_SW_1P_TX` writer - NA"] +pub type DCS_SW_1P_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCS_SR_0P_TX` reader - NA"] +pub type DCS_SR_0P_TX_R = crate::BitReader; +#[doc = "Field `DCS_SR_0P_TX` writer - NA"] +pub type DCS_SR_0P_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCS_LW_TX` reader - NA"] +pub type DCS_LW_TX_R = crate::BitReader; +#[doc = "Field `DCS_LW_TX` writer - NA"] +pub type DCS_LW_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAX_RD_PKT_SIZE` reader - NA"] +pub type MAX_RD_PKT_SIZE_R = crate::BitReader; +#[doc = "Field `MAX_RD_PKT_SIZE` writer - NA"] +pub type MAX_RD_PKT_SIZE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn tear_fx_en(&self) -> TEAR_FX_EN_R { + TEAR_FX_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ack_rqst_en(&self) -> ACK_RQST_EN_R { + ACK_RQST_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn gen_sw_0p_tx(&self) -> GEN_SW_0P_TX_R { + GEN_SW_0P_TX_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn gen_sw_1p_tx(&self) -> GEN_SW_1P_TX_R { + GEN_SW_1P_TX_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn gen_sw_2p_tx(&self) -> GEN_SW_2P_TX_R { + GEN_SW_2P_TX_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn gen_sr_0p_tx(&self) -> GEN_SR_0P_TX_R { + GEN_SR_0P_TX_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn gen_sr_1p_tx(&self) -> GEN_SR_1P_TX_R { + GEN_SR_1P_TX_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn gen_sr_2p_tx(&self) -> GEN_SR_2P_TX_R { + GEN_SR_2P_TX_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn gen_lw_tx(&self) -> GEN_LW_TX_R { + GEN_LW_TX_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn dcs_sw_0p_tx(&self) -> DCS_SW_0P_TX_R { + DCS_SW_0P_TX_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn dcs_sw_1p_tx(&self) -> DCS_SW_1P_TX_R { + DCS_SW_1P_TX_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn dcs_sr_0p_tx(&self) -> DCS_SR_0P_TX_R { + DCS_SR_0P_TX_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn dcs_lw_tx(&self) -> DCS_LW_TX_R { + DCS_LW_TX_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + pub fn max_rd_pkt_size(&self) -> MAX_RD_PKT_SIZE_R { + MAX_RD_PKT_SIZE_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CMD_MODE_CFG") + .field("tear_fx_en", &format_args!("{}", self.tear_fx_en().bit())) + .field("ack_rqst_en", &format_args!("{}", self.ack_rqst_en().bit())) + .field( + "gen_sw_0p_tx", + &format_args!("{}", self.gen_sw_0p_tx().bit()), + ) + .field( + "gen_sw_1p_tx", + &format_args!("{}", self.gen_sw_1p_tx().bit()), + ) + .field( + "gen_sw_2p_tx", + &format_args!("{}", self.gen_sw_2p_tx().bit()), + ) + .field( + "gen_sr_0p_tx", + &format_args!("{}", self.gen_sr_0p_tx().bit()), + ) + .field( + "gen_sr_1p_tx", + &format_args!("{}", self.gen_sr_1p_tx().bit()), + ) + .field( + "gen_sr_2p_tx", + &format_args!("{}", self.gen_sr_2p_tx().bit()), + ) + .field("gen_lw_tx", &format_args!("{}", self.gen_lw_tx().bit())) + .field( + "dcs_sw_0p_tx", + &format_args!("{}", self.dcs_sw_0p_tx().bit()), + ) + .field( + "dcs_sw_1p_tx", + &format_args!("{}", self.dcs_sw_1p_tx().bit()), + ) + .field( + "dcs_sr_0p_tx", + &format_args!("{}", self.dcs_sr_0p_tx().bit()), + ) + .field("dcs_lw_tx", &format_args!("{}", self.dcs_lw_tx().bit())) + .field( + "max_rd_pkt_size", + &format_args!("{}", self.max_rd_pkt_size().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn tear_fx_en(&mut self) -> TEAR_FX_EN_W { + TEAR_FX_EN_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn ack_rqst_en(&mut self) -> ACK_RQST_EN_W { + ACK_RQST_EN_W::new(self, 1) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_sw_0p_tx(&mut self) -> GEN_SW_0P_TX_W { + GEN_SW_0P_TX_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_sw_1p_tx(&mut self) -> GEN_SW_1P_TX_W { + GEN_SW_1P_TX_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_sw_2p_tx(&mut self) -> GEN_SW_2P_TX_W { + GEN_SW_2P_TX_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_sr_0p_tx(&mut self) -> GEN_SR_0P_TX_W { + GEN_SR_0P_TX_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_sr_1p_tx(&mut self) -> GEN_SR_1P_TX_W { + GEN_SR_1P_TX_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_sr_2p_tx(&mut self) -> GEN_SR_2P_TX_W { + GEN_SR_2P_TX_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_lw_tx(&mut self) -> GEN_LW_TX_W { + GEN_LW_TX_W::new(self, 14) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn dcs_sw_0p_tx(&mut self) -> DCS_SW_0P_TX_W { + DCS_SW_0P_TX_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn dcs_sw_1p_tx(&mut self) -> DCS_SW_1P_TX_W { + DCS_SW_1P_TX_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn dcs_sr_0p_tx(&mut self) -> DCS_SR_0P_TX_W { + DCS_SR_0P_TX_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn dcs_lw_tx(&mut self) -> DCS_LW_TX_W { + DCS_LW_TX_W::new(self, 19) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + #[must_use] + pub fn max_rd_pkt_size(&mut self) -> MAX_RD_PKT_SIZE_W { + MAX_RD_PKT_SIZE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_mode_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd_mode_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CMD_MODE_CFG_SPEC; +impl crate::RegisterSpec for CMD_MODE_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmd_mode_cfg::R`](R) reader structure"] +impl crate::Readable for CMD_MODE_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmd_mode_cfg::W`](W) writer structure"] +impl crate::Writable for CMD_MODE_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMD_MODE_CFG to value 0"] +impl crate::Resettable for CMD_MODE_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/cmd_pkt_status.rs b/esp32p4/src/mipi_dsi_host/cmd_pkt_status.rs new file mode 100644 index 0000000000..f850f4bcaa --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/cmd_pkt_status.rs @@ -0,0 +1,149 @@ +#[doc = "Register `CMD_PKT_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `GEN_CMD_EMPTY` reader - NA"] +pub type GEN_CMD_EMPTY_R = crate::BitReader; +#[doc = "Field `GEN_CMD_FULL` reader - NA"] +pub type GEN_CMD_FULL_R = crate::BitReader; +#[doc = "Field `GEN_PLD_W_EMPTY` reader - NA"] +pub type GEN_PLD_W_EMPTY_R = crate::BitReader; +#[doc = "Field `GEN_PLD_W_FULL` reader - NA"] +pub type GEN_PLD_W_FULL_R = crate::BitReader; +#[doc = "Field `GEN_PLD_R_EMPTY` reader - NA"] +pub type GEN_PLD_R_EMPTY_R = crate::BitReader; +#[doc = "Field `GEN_PLD_R_FULL` reader - NA"] +pub type GEN_PLD_R_FULL_R = crate::BitReader; +#[doc = "Field `GEN_RD_CMD_BUSY` reader - NA"] +pub type GEN_RD_CMD_BUSY_R = crate::BitReader; +#[doc = "Field `GEN_BUFF_CMD_EMPTY` reader - NA"] +pub type GEN_BUFF_CMD_EMPTY_R = crate::BitReader; +#[doc = "Field `GEN_BUFF_CMD_FULL` reader - NA"] +pub type GEN_BUFF_CMD_FULL_R = crate::BitReader; +#[doc = "Field `GEN_BUFF_PLD_EMPTY` reader - NA"] +pub type GEN_BUFF_PLD_EMPTY_R = crate::BitReader; +#[doc = "Field `GEN_BUFF_PLD_FULL` reader - NA"] +pub type GEN_BUFF_PLD_FULL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn gen_cmd_empty(&self) -> GEN_CMD_EMPTY_R { + GEN_CMD_EMPTY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn gen_cmd_full(&self) -> GEN_CMD_FULL_R { + GEN_CMD_FULL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn gen_pld_w_empty(&self) -> GEN_PLD_W_EMPTY_R { + GEN_PLD_W_EMPTY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn gen_pld_w_full(&self) -> GEN_PLD_W_FULL_R { + GEN_PLD_W_FULL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn gen_pld_r_empty(&self) -> GEN_PLD_R_EMPTY_R { + GEN_PLD_R_EMPTY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn gen_pld_r_full(&self) -> GEN_PLD_R_FULL_R { + GEN_PLD_R_FULL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn gen_rd_cmd_busy(&self) -> GEN_RD_CMD_BUSY_R { + GEN_RD_CMD_BUSY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn gen_buff_cmd_empty(&self) -> GEN_BUFF_CMD_EMPTY_R { + GEN_BUFF_CMD_EMPTY_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn gen_buff_cmd_full(&self) -> GEN_BUFF_CMD_FULL_R { + GEN_BUFF_CMD_FULL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn gen_buff_pld_empty(&self) -> GEN_BUFF_PLD_EMPTY_R { + GEN_BUFF_PLD_EMPTY_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn gen_buff_pld_full(&self) -> GEN_BUFF_PLD_FULL_R { + GEN_BUFF_PLD_FULL_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CMD_PKT_STATUS") + .field( + "gen_cmd_empty", + &format_args!("{}", self.gen_cmd_empty().bit()), + ) + .field( + "gen_cmd_full", + &format_args!("{}", self.gen_cmd_full().bit()), + ) + .field( + "gen_pld_w_empty", + &format_args!("{}", self.gen_pld_w_empty().bit()), + ) + .field( + "gen_pld_w_full", + &format_args!("{}", self.gen_pld_w_full().bit()), + ) + .field( + "gen_pld_r_empty", + &format_args!("{}", self.gen_pld_r_empty().bit()), + ) + .field( + "gen_pld_r_full", + &format_args!("{}", self.gen_pld_r_full().bit()), + ) + .field( + "gen_rd_cmd_busy", + &format_args!("{}", self.gen_rd_cmd_busy().bit()), + ) + .field( + "gen_buff_cmd_empty", + &format_args!("{}", self.gen_buff_cmd_empty().bit()), + ) + .field( + "gen_buff_cmd_full", + &format_args!("{}", self.gen_buff_cmd_full().bit()), + ) + .field( + "gen_buff_pld_empty", + &format_args!("{}", self.gen_buff_pld_empty().bit()), + ) + .field( + "gen_buff_pld_full", + &format_args!("{}", self.gen_buff_pld_full().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_pkt_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CMD_PKT_STATUS_SPEC; +impl crate::RegisterSpec for CMD_PKT_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmd_pkt_status::R`](R) reader structure"] +impl crate::Readable for CMD_PKT_STATUS_SPEC {} +#[doc = "`reset()` method sets CMD_PKT_STATUS to value 0x0005_0015"] +impl crate::Resettable for CMD_PKT_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x0005_0015; +} diff --git a/esp32p4/src/mipi_dsi_host/dbi_cfg.rs b/esp32p4/src/mipi_dsi_host/dbi_cfg.rs new file mode 100644 index 0000000000..02523a1839 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dbi_cfg.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DBI_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `DBI_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `IN_DBI_CONF` reader - NA"] +pub type IN_DBI_CONF_R = crate::FieldReader; +#[doc = "Field `IN_DBI_CONF` writer - NA"] +pub type IN_DBI_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `OUT_DBI_CONF` reader - NA"] +pub type OUT_DBI_CONF_R = crate::FieldReader; +#[doc = "Field `OUT_DBI_CONF` writer - NA"] +pub type OUT_DBI_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LUT_SIZE_CONF` reader - NA"] +pub type LUT_SIZE_CONF_R = crate::FieldReader; +#[doc = "Field `LUT_SIZE_CONF` writer - NA"] +pub type LUT_SIZE_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + pub fn in_dbi_conf(&self) -> IN_DBI_CONF_R { + IN_DBI_CONF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:11 - NA"] + #[inline(always)] + pub fn out_dbi_conf(&self) -> OUT_DBI_CONF_R { + OUT_DBI_CONF_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:17 - NA"] + #[inline(always)] + pub fn lut_size_conf(&self) -> LUT_SIZE_CONF_R { + LUT_SIZE_CONF_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBI_CFG") + .field( + "in_dbi_conf", + &format_args!("{}", self.in_dbi_conf().bits()), + ) + .field( + "out_dbi_conf", + &format_args!("{}", self.out_dbi_conf().bits()), + ) + .field( + "lut_size_conf", + &format_args!("{}", self.lut_size_conf().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + #[must_use] + pub fn in_dbi_conf(&mut self) -> IN_DBI_CONF_W { + IN_DBI_CONF_W::new(self, 0) + } + #[doc = "Bits 8:11 - NA"] + #[inline(always)] + #[must_use] + pub fn out_dbi_conf(&mut self) -> OUT_DBI_CONF_W { + OUT_DBI_CONF_W::new(self, 8) + } + #[doc = "Bits 16:17 - NA"] + #[inline(always)] + #[must_use] + pub fn lut_size_conf(&mut self) -> LUT_SIZE_CONF_W { + LUT_SIZE_CONF_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBI_CFG_SPEC; +impl crate::RegisterSpec for DBI_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbi_cfg::R`](R) reader structure"] +impl crate::Readable for DBI_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbi_cfg::W`](W) writer structure"] +impl crate::Writable for DBI_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBI_CFG to value 0"] +impl crate::Resettable for DBI_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/dbi_cmdsize.rs b/esp32p4/src/mipi_dsi_host/dbi_cmdsize.rs new file mode 100644 index 0000000000..d3608d3bc6 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dbi_cmdsize.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DBI_CMDSIZE` reader"] +pub type R = crate::R; +#[doc = "Register `DBI_CMDSIZE` writer"] +pub type W = crate::W; +#[doc = "Field `WR_CMD_SIZE` reader - NA"] +pub type WR_CMD_SIZE_R = crate::FieldReader; +#[doc = "Field `WR_CMD_SIZE` writer - NA"] +pub type WR_CMD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `ALLOWED_CMD_SIZE` reader - NA"] +pub type ALLOWED_CMD_SIZE_R = crate::FieldReader; +#[doc = "Field `ALLOWED_CMD_SIZE` writer - NA"] +pub type ALLOWED_CMD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn wr_cmd_size(&self) -> WR_CMD_SIZE_R { + WR_CMD_SIZE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - NA"] + #[inline(always)] + pub fn allowed_cmd_size(&self) -> ALLOWED_CMD_SIZE_R { + ALLOWED_CMD_SIZE_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBI_CMDSIZE") + .field( + "wr_cmd_size", + &format_args!("{}", self.wr_cmd_size().bits()), + ) + .field( + "allowed_cmd_size", + &format_args!("{}", self.allowed_cmd_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn wr_cmd_size(&mut self) -> WR_CMD_SIZE_W { + WR_CMD_SIZE_W::new(self, 0) + } + #[doc = "Bits 16:31 - NA"] + #[inline(always)] + #[must_use] + pub fn allowed_cmd_size(&mut self) -> ALLOWED_CMD_SIZE_W { + ALLOWED_CMD_SIZE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_cmdsize::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_cmdsize::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBI_CMDSIZE_SPEC; +impl crate::RegisterSpec for DBI_CMDSIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbi_cmdsize::R`](R) reader structure"] +impl crate::Readable for DBI_CMDSIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbi_cmdsize::W`](W) writer structure"] +impl crate::Writable for DBI_CMDSIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBI_CMDSIZE to value 0"] +impl crate::Resettable for DBI_CMDSIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/dbi_partitioning_en.rs b/esp32p4/src/mipi_dsi_host/dbi_partitioning_en.rs new file mode 100644 index 0000000000..64cf6bafd8 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dbi_partitioning_en.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DBI_PARTITIONING_EN` reader"] +pub type R = crate::R; +#[doc = "Register `DBI_PARTITIONING_EN` writer"] +pub type W = crate::W; +#[doc = "Field `PARTITIONING_EN` reader - NA"] +pub type PARTITIONING_EN_R = crate::BitReader; +#[doc = "Field `PARTITIONING_EN` writer - NA"] +pub type PARTITIONING_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn partitioning_en(&self) -> PARTITIONING_EN_R { + PARTITIONING_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBI_PARTITIONING_EN") + .field( + "partitioning_en", + &format_args!("{}", self.partitioning_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn partitioning_en(&mut self) -> PARTITIONING_EN_W { + PARTITIONING_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_partitioning_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_partitioning_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBI_PARTITIONING_EN_SPEC; +impl crate::RegisterSpec for DBI_PARTITIONING_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbi_partitioning_en::R`](R) reader structure"] +impl crate::Readable for DBI_PARTITIONING_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbi_partitioning_en::W`](W) writer structure"] +impl crate::Writable for DBI_PARTITIONING_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBI_PARTITIONING_EN to value 0"] +impl crate::Resettable for DBI_PARTITIONING_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/dbi_vcid.rs b/esp32p4/src/mipi_dsi_host/dbi_vcid.rs new file mode 100644 index 0000000000..48362ac530 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dbi_vcid.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DBI_VCID` reader"] +pub type R = crate::R; +#[doc = "Register `DBI_VCID` writer"] +pub type W = crate::W; +#[doc = "Field `DBI_VCID` reader - NA"] +pub type DBI_VCID_R = crate::FieldReader; +#[doc = "Field `DBI_VCID` writer - NA"] +pub type DBI_VCID_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn dbi_vcid(&self) -> DBI_VCID_R { + DBI_VCID_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBI_VCID") + .field("dbi_vcid", &format_args!("{}", self.dbi_vcid().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + #[must_use] + pub fn dbi_vcid(&mut self) -> DBI_VCID_W { + DBI_VCID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_vcid::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_vcid::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBI_VCID_SPEC; +impl crate::RegisterSpec for DBI_VCID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbi_vcid::R`](R) reader structure"] +impl crate::Readable for DBI_VCID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbi_vcid::W`](W) writer structure"] +impl crate::Writable for DBI_VCID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBI_VCID to value 0"] +impl crate::Resettable for DBI_VCID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/dpi_cfg_pol.rs b/esp32p4/src/mipi_dsi_host/dpi_cfg_pol.rs new file mode 100644 index 0000000000..4906322cff --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dpi_cfg_pol.rs @@ -0,0 +1,142 @@ +#[doc = "Register `DPI_CFG_POL` reader"] +pub type R = crate::R; +#[doc = "Register `DPI_CFG_POL` writer"] +pub type W = crate::W; +#[doc = "Field `DATAEN_ACTIVE_LOW` reader - NA"] +pub type DATAEN_ACTIVE_LOW_R = crate::BitReader; +#[doc = "Field `DATAEN_ACTIVE_LOW` writer - NA"] +pub type DATAEN_ACTIVE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VSYNC_ACTIVE_LOW` reader - NA"] +pub type VSYNC_ACTIVE_LOW_R = crate::BitReader; +#[doc = "Field `VSYNC_ACTIVE_LOW` writer - NA"] +pub type VSYNC_ACTIVE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HSYNC_ACTIVE_LOW` reader - NA"] +pub type HSYNC_ACTIVE_LOW_R = crate::BitReader; +#[doc = "Field `HSYNC_ACTIVE_LOW` writer - NA"] +pub type HSYNC_ACTIVE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SHUTD_ACTIVE_LOW` reader - NA"] +pub type SHUTD_ACTIVE_LOW_R = crate::BitReader; +#[doc = "Field `SHUTD_ACTIVE_LOW` writer - NA"] +pub type SHUTD_ACTIVE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COLORM_ACTIVE_LOW` reader - NA"] +pub type COLORM_ACTIVE_LOW_R = crate::BitReader; +#[doc = "Field `COLORM_ACTIVE_LOW` writer - NA"] +pub type COLORM_ACTIVE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn dataen_active_low(&self) -> DATAEN_ACTIVE_LOW_R { + DATAEN_ACTIVE_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn vsync_active_low(&self) -> VSYNC_ACTIVE_LOW_R { + VSYNC_ACTIVE_LOW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn hsync_active_low(&self) -> HSYNC_ACTIVE_LOW_R { + HSYNC_ACTIVE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn shutd_active_low(&self) -> SHUTD_ACTIVE_LOW_R { + SHUTD_ACTIVE_LOW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn colorm_active_low(&self) -> COLORM_ACTIVE_LOW_R { + COLORM_ACTIVE_LOW_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_CFG_POL") + .field( + "dataen_active_low", + &format_args!("{}", self.dataen_active_low().bit()), + ) + .field( + "vsync_active_low", + &format_args!("{}", self.vsync_active_low().bit()), + ) + .field( + "hsync_active_low", + &format_args!("{}", self.hsync_active_low().bit()), + ) + .field( + "shutd_active_low", + &format_args!("{}", self.shutd_active_low().bit()), + ) + .field( + "colorm_active_low", + &format_args!("{}", self.colorm_active_low().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn dataen_active_low(&mut self) -> DATAEN_ACTIVE_LOW_W { + DATAEN_ACTIVE_LOW_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn vsync_active_low(&mut self) -> VSYNC_ACTIVE_LOW_W { + VSYNC_ACTIVE_LOW_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn hsync_active_low(&mut self) -> HSYNC_ACTIVE_LOW_W { + HSYNC_ACTIVE_LOW_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn shutd_active_low(&mut self) -> SHUTD_ACTIVE_LOW_W { + SHUTD_ACTIVE_LOW_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn colorm_active_low(&mut self) -> COLORM_ACTIVE_LOW_W { + COLORM_ACTIVE_LOW_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_cfg_pol::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_cfg_pol::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_CFG_POL_SPEC; +impl crate::RegisterSpec for DPI_CFG_POL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_cfg_pol::R`](R) reader structure"] +impl crate::Readable for DPI_CFG_POL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpi_cfg_pol::W`](W) writer structure"] +impl crate::Writable for DPI_CFG_POL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_CFG_POL to value 0"] +impl crate::Resettable for DPI_CFG_POL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/dpi_color_coding.rs b/esp32p4/src/mipi_dsi_host/dpi_color_coding.rs new file mode 100644 index 0000000000..6b40329dfa --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dpi_color_coding.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DPI_COLOR_CODING` reader"] +pub type R = crate::R; +#[doc = "Register `DPI_COLOR_CODING` writer"] +pub type W = crate::W; +#[doc = "Field `DPI_COLOR_CODING` reader - NA"] +pub type DPI_COLOR_CODING_R = crate::FieldReader; +#[doc = "Field `DPI_COLOR_CODING` writer - NA"] +pub type DPI_COLOR_CODING_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LOOSELY18_EN` reader - NA"] +pub type LOOSELY18_EN_R = crate::BitReader; +#[doc = "Field `LOOSELY18_EN` writer - NA"] +pub type LOOSELY18_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + pub fn dpi_color_coding(&self) -> DPI_COLOR_CODING_R { + DPI_COLOR_CODING_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn loosely18_en(&self) -> LOOSELY18_EN_R { + LOOSELY18_EN_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_COLOR_CODING") + .field( + "dpi_color_coding", + &format_args!("{}", self.dpi_color_coding().bits()), + ) + .field( + "loosely18_en", + &format_args!("{}", self.loosely18_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + #[must_use] + pub fn dpi_color_coding(&mut self) -> DPI_COLOR_CODING_W { + DPI_COLOR_CODING_W::new(self, 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn loosely18_en(&mut self) -> LOOSELY18_EN_W { + LOOSELY18_EN_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_color_coding::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_color_coding::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_COLOR_CODING_SPEC; +impl crate::RegisterSpec for DPI_COLOR_CODING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_color_coding::R`](R) reader structure"] +impl crate::Readable for DPI_COLOR_CODING_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpi_color_coding::W`](W) writer structure"] +impl crate::Writable for DPI_COLOR_CODING_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_COLOR_CODING to value 0"] +impl crate::Resettable for DPI_COLOR_CODING_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/dpi_color_coding_act.rs b/esp32p4/src/mipi_dsi_host/dpi_color_coding_act.rs new file mode 100644 index 0000000000..7e102f90b8 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dpi_color_coding_act.rs @@ -0,0 +1,50 @@ +#[doc = "Register `DPI_COLOR_CODING_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `DPI_COLOR_CODING_ACT` reader - NA"] +pub type DPI_COLOR_CODING_ACT_R = crate::FieldReader; +#[doc = "Field `LOOSELY18_EN_ACT` reader - NA"] +pub type LOOSELY18_EN_ACT_R = crate::BitReader; +impl R { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + pub fn dpi_color_coding_act(&self) -> DPI_COLOR_CODING_ACT_R { + DPI_COLOR_CODING_ACT_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn loosely18_en_act(&self) -> LOOSELY18_EN_ACT_R { + LOOSELY18_EN_ACT_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_COLOR_CODING_ACT") + .field( + "dpi_color_coding_act", + &format_args!("{}", self.dpi_color_coding_act().bits()), + ) + .field( + "loosely18_en_act", + &format_args!("{}", self.loosely18_en_act().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_color_coding_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_COLOR_CODING_ACT_SPEC; +impl crate::RegisterSpec for DPI_COLOR_CODING_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_color_coding_act::R`](R) reader structure"] +impl crate::Readable for DPI_COLOR_CODING_ACT_SPEC {} +#[doc = "`reset()` method sets DPI_COLOR_CODING_ACT to value 0"] +impl crate::Resettable for DPI_COLOR_CODING_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim.rs b/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim.rs new file mode 100644 index 0000000000..2778916528 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DPI_LP_CMD_TIM` reader"] +pub type R = crate::R; +#[doc = "Register `DPI_LP_CMD_TIM` writer"] +pub type W = crate::W; +#[doc = "Field `INVACT_LPCMD_TIME` reader - NA"] +pub type INVACT_LPCMD_TIME_R = crate::FieldReader; +#[doc = "Field `INVACT_LPCMD_TIME` writer - NA"] +pub type INVACT_LPCMD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `OUTVACT_LPCMD_TIME` reader - NA"] +pub type OUTVACT_LPCMD_TIME_R = crate::FieldReader; +#[doc = "Field `OUTVACT_LPCMD_TIME` writer - NA"] +pub type OUTVACT_LPCMD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + pub fn invact_lpcmd_time(&self) -> INVACT_LPCMD_TIME_R { + INVACT_LPCMD_TIME_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn outvact_lpcmd_time(&self) -> OUTVACT_LPCMD_TIME_R { + OUTVACT_LPCMD_TIME_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_LP_CMD_TIM") + .field( + "invact_lpcmd_time", + &format_args!("{}", self.invact_lpcmd_time().bits()), + ) + .field( + "outvact_lpcmd_time", + &format_args!("{}", self.outvact_lpcmd_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + #[must_use] + pub fn invact_lpcmd_time(&mut self) -> INVACT_LPCMD_TIME_W { + INVACT_LPCMD_TIME_W::new(self, 0) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + #[must_use] + pub fn outvact_lpcmd_time(&mut self) -> OUTVACT_LPCMD_TIME_W { + OUTVACT_LPCMD_TIME_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_lp_cmd_tim::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_lp_cmd_tim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_LP_CMD_TIM_SPEC; +impl crate::RegisterSpec for DPI_LP_CMD_TIM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_lp_cmd_tim::R`](R) reader structure"] +impl crate::Readable for DPI_LP_CMD_TIM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpi_lp_cmd_tim::W`](W) writer structure"] +impl crate::Writable for DPI_LP_CMD_TIM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_LP_CMD_TIM to value 0"] +impl crate::Resettable for DPI_LP_CMD_TIM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim_act.rs b/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim_act.rs new file mode 100644 index 0000000000..af18d68430 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim_act.rs @@ -0,0 +1,50 @@ +#[doc = "Register `DPI_LP_CMD_TIM_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `INVACT_LPCMD_TIME_ACT` reader - NA"] +pub type INVACT_LPCMD_TIME_ACT_R = crate::FieldReader; +#[doc = "Field `OUTVACT_LPCMD_TIME_ACT` reader - NA"] +pub type OUTVACT_LPCMD_TIME_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + pub fn invact_lpcmd_time_act(&self) -> INVACT_LPCMD_TIME_ACT_R { + INVACT_LPCMD_TIME_ACT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn outvact_lpcmd_time_act(&self) -> OUTVACT_LPCMD_TIME_ACT_R { + OUTVACT_LPCMD_TIME_ACT_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_LP_CMD_TIM_ACT") + .field( + "invact_lpcmd_time_act", + &format_args!("{}", self.invact_lpcmd_time_act().bits()), + ) + .field( + "outvact_lpcmd_time_act", + &format_args!("{}", self.outvact_lpcmd_time_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_lp_cmd_tim_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_LP_CMD_TIM_ACT_SPEC; +impl crate::RegisterSpec for DPI_LP_CMD_TIM_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_lp_cmd_tim_act::R`](R) reader structure"] +impl crate::Readable for DPI_LP_CMD_TIM_ACT_SPEC {} +#[doc = "`reset()` method sets DPI_LP_CMD_TIM_ACT to value 0"] +impl crate::Resettable for DPI_LP_CMD_TIM_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/dpi_vcid.rs b/esp32p4/src/mipi_dsi_host/dpi_vcid.rs new file mode 100644 index 0000000000..a287f70327 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dpi_vcid.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DPI_VCID` reader"] +pub type R = crate::R; +#[doc = "Register `DPI_VCID` writer"] +pub type W = crate::W; +#[doc = "Field `DPI_VCID` reader - NA"] +pub type DPI_VCID_R = crate::FieldReader; +#[doc = "Field `DPI_VCID` writer - NA"] +pub type DPI_VCID_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn dpi_vcid(&self) -> DPI_VCID_R { + DPI_VCID_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_VCID") + .field("dpi_vcid", &format_args!("{}", self.dpi_vcid().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + #[must_use] + pub fn dpi_vcid(&mut self) -> DPI_VCID_W { + DPI_VCID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_vcid::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpi_vcid::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_VCID_SPEC; +impl crate::RegisterSpec for DPI_VCID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_vcid::R`](R) reader structure"] +impl crate::Readable for DPI_VCID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpi_vcid::W`](W) writer structure"] +impl crate::Writable for DPI_VCID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPI_VCID to value 0"] +impl crate::Resettable for DPI_VCID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/dpi_vcid_act.rs b/esp32p4/src/mipi_dsi_host/dpi_vcid_act.rs new file mode 100644 index 0000000000..6844e4ce2c --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dpi_vcid_act.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DPI_VCID_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `DPI_VCID_ACT` reader - NA"] +pub type DPI_VCID_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn dpi_vcid_act(&self) -> DPI_VCID_ACT_R { + DPI_VCID_ACT_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DPI_VCID_ACT") + .field( + "dpi_vcid_act", + &format_args!("{}", self.dpi_vcid_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_vcid_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPI_VCID_ACT_SPEC; +impl crate::RegisterSpec for DPI_VCID_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpi_vcid_act::R`](R) reader structure"] +impl crate::Readable for DPI_VCID_ACT_SPEC {} +#[doc = "`reset()` method sets DPI_VCID_ACT to value 0"] +impl crate::Resettable for DPI_VCID_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/dsc_parameter.rs b/esp32p4/src/mipi_dsi_host/dsc_parameter.rs new file mode 100644 index 0000000000..7b44486479 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/dsc_parameter.rs @@ -0,0 +1,101 @@ +#[doc = "Register `DSC_PARAMETER` reader"] +pub type R = crate::R; +#[doc = "Register `DSC_PARAMETER` writer"] +pub type W = crate::W; +#[doc = "Field `COMPRESSION_MODE` reader - NA"] +pub type COMPRESSION_MODE_R = crate::BitReader; +#[doc = "Field `COMPRESSION_MODE` writer - NA"] +pub type COMPRESSION_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COMPRESS_ALGO` reader - NA"] +pub type COMPRESS_ALGO_R = crate::FieldReader; +#[doc = "Field `COMPRESS_ALGO` writer - NA"] +pub type COMPRESS_ALGO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PPS_SEL` reader - NA"] +pub type PPS_SEL_R = crate::FieldReader; +#[doc = "Field `PPS_SEL` writer - NA"] +pub type PPS_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn compression_mode(&self) -> COMPRESSION_MODE_R { + COMPRESSION_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 8:9 - NA"] + #[inline(always)] + pub fn compress_algo(&self) -> COMPRESS_ALGO_R { + COMPRESS_ALGO_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 16:17 - NA"] + #[inline(always)] + pub fn pps_sel(&self) -> PPS_SEL_R { + PPS_SEL_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSC_PARAMETER") + .field( + "compression_mode", + &format_args!("{}", self.compression_mode().bit()), + ) + .field( + "compress_algo", + &format_args!("{}", self.compress_algo().bits()), + ) + .field("pps_sel", &format_args!("{}", self.pps_sel().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn compression_mode(&mut self) -> COMPRESSION_MODE_W { + COMPRESSION_MODE_W::new(self, 0) + } + #[doc = "Bits 8:9 - NA"] + #[inline(always)] + #[must_use] + pub fn compress_algo(&mut self) -> COMPRESS_ALGO_W { + COMPRESS_ALGO_W::new(self, 8) + } + #[doc = "Bits 16:17 - NA"] + #[inline(always)] + #[must_use] + pub fn pps_sel(&mut self) -> PPS_SEL_W { + PPS_SEL_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsc_parameter::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsc_parameter::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DSC_PARAMETER_SPEC; +impl crate::RegisterSpec for DSC_PARAMETER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dsc_parameter::R`](R) reader structure"] +impl crate::Readable for DSC_PARAMETER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dsc_parameter::W`](W) writer structure"] +impl crate::Writable for DSC_PARAMETER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DSC_PARAMETER to value 0"] +impl crate::Resettable for DSC_PARAMETER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/edpi_cmd_size.rs b/esp32p4/src/mipi_dsi_host/edpi_cmd_size.rs new file mode 100644 index 0000000000..ce6bd0e1ae --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/edpi_cmd_size.rs @@ -0,0 +1,66 @@ +#[doc = "Register `EDPI_CMD_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `EDPI_CMD_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `EDPI_ALLOWED_CMD_SIZE` reader - NA"] +pub type EDPI_ALLOWED_CMD_SIZE_R = crate::FieldReader; +#[doc = "Field `EDPI_ALLOWED_CMD_SIZE` writer - NA"] +pub type EDPI_ALLOWED_CMD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn edpi_allowed_cmd_size(&self) -> EDPI_ALLOWED_CMD_SIZE_R { + EDPI_ALLOWED_CMD_SIZE_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EDPI_CMD_SIZE") + .field( + "edpi_allowed_cmd_size", + &format_args!("{}", self.edpi_allowed_cmd_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn edpi_allowed_cmd_size(&mut self) -> EDPI_ALLOWED_CMD_SIZE_W { + EDPI_ALLOWED_CMD_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edpi_cmd_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edpi_cmd_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EDPI_CMD_SIZE_SPEC; +impl crate::RegisterSpec for EDPI_CMD_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`edpi_cmd_size::R`](R) reader structure"] +impl crate::Readable for EDPI_CMD_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`edpi_cmd_size::W`](W) writer structure"] +impl crate::Writable for EDPI_CMD_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EDPI_CMD_SIZE to value 0"] +impl crate::Resettable for EDPI_CMD_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/edpi_te_hw_cfg.rs b/esp32p4/src/mipi_dsi_host/edpi_te_hw_cfg.rs new file mode 100644 index 0000000000..c433091d0d --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/edpi_te_hw_cfg.rs @@ -0,0 +1,123 @@ +#[doc = "Register `EDPI_TE_HW_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `EDPI_TE_HW_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `HW_TEAR_EFFECT_ON` reader - NA"] +pub type HW_TEAR_EFFECT_ON_R = crate::BitReader; +#[doc = "Field `HW_TEAR_EFFECT_ON` writer - NA"] +pub type HW_TEAR_EFFECT_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HW_TEAR_EFFECT_GEN` reader - NA"] +pub type HW_TEAR_EFFECT_GEN_R = crate::BitReader; +#[doc = "Field `HW_TEAR_EFFECT_GEN` writer - NA"] +pub type HW_TEAR_EFFECT_GEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HW_SET_SCAN_LINE` reader - NA"] +pub type HW_SET_SCAN_LINE_R = crate::BitReader; +#[doc = "Field `HW_SET_SCAN_LINE` writer - NA"] +pub type HW_SET_SCAN_LINE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAN_LINE_PARAMETER` reader - NA"] +pub type SCAN_LINE_PARAMETER_R = crate::FieldReader; +#[doc = "Field `SCAN_LINE_PARAMETER` writer - NA"] +pub type SCAN_LINE_PARAMETER_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn hw_tear_effect_on(&self) -> HW_TEAR_EFFECT_ON_R { + HW_TEAR_EFFECT_ON_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn hw_tear_effect_gen(&self) -> HW_TEAR_EFFECT_GEN_R { + HW_TEAR_EFFECT_GEN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn hw_set_scan_line(&self) -> HW_SET_SCAN_LINE_R { + HW_SET_SCAN_LINE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 16:31 - NA"] + #[inline(always)] + pub fn scan_line_parameter(&self) -> SCAN_LINE_PARAMETER_R { + SCAN_LINE_PARAMETER_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EDPI_TE_HW_CFG") + .field( + "hw_tear_effect_on", + &format_args!("{}", self.hw_tear_effect_on().bit()), + ) + .field( + "hw_tear_effect_gen", + &format_args!("{}", self.hw_tear_effect_gen().bit()), + ) + .field( + "hw_set_scan_line", + &format_args!("{}", self.hw_set_scan_line().bit()), + ) + .field( + "scan_line_parameter", + &format_args!("{}", self.scan_line_parameter().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn hw_tear_effect_on(&mut self) -> HW_TEAR_EFFECT_ON_W { + HW_TEAR_EFFECT_ON_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn hw_tear_effect_gen(&mut self) -> HW_TEAR_EFFECT_GEN_W { + HW_TEAR_EFFECT_GEN_W::new(self, 1) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn hw_set_scan_line(&mut self) -> HW_SET_SCAN_LINE_W { + HW_SET_SCAN_LINE_W::new(self, 4) + } + #[doc = "Bits 16:31 - NA"] + #[inline(always)] + #[must_use] + pub fn scan_line_parameter(&mut self) -> SCAN_LINE_PARAMETER_W { + SCAN_LINE_PARAMETER_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edpi_te_hw_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edpi_te_hw_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EDPI_TE_HW_CFG_SPEC; +impl crate::RegisterSpec for EDPI_TE_HW_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`edpi_te_hw_cfg::R`](R) reader structure"] +impl crate::Readable for EDPI_TE_HW_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`edpi_te_hw_cfg::W`](W) writer structure"] +impl crate::Writable for EDPI_TE_HW_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EDPI_TE_HW_CFG to value 0"] +impl crate::Resettable for EDPI_TE_HW_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/gen_hdr.rs b/esp32p4/src/mipi_dsi_host/gen_hdr.rs new file mode 100644 index 0000000000..179be887bb --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/gen_hdr.rs @@ -0,0 +1,117 @@ +#[doc = "Register `GEN_HDR` reader"] +pub type R = crate::R; +#[doc = "Register `GEN_HDR` writer"] +pub type W = crate::W; +#[doc = "Field `GEN_DT` reader - NA"] +pub type GEN_DT_R = crate::FieldReader; +#[doc = "Field `GEN_DT` writer - NA"] +pub type GEN_DT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `GEN_VC` reader - NA"] +pub type GEN_VC_R = crate::FieldReader; +#[doc = "Field `GEN_VC` writer - NA"] +pub type GEN_VC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GEN_WC_LSBYTE` reader - NA"] +pub type GEN_WC_LSBYTE_R = crate::FieldReader; +#[doc = "Field `GEN_WC_LSBYTE` writer - NA"] +pub type GEN_WC_LSBYTE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GEN_WC_MSBYTE` reader - NA"] +pub type GEN_WC_MSBYTE_R = crate::FieldReader; +#[doc = "Field `GEN_WC_MSBYTE` writer - NA"] +pub type GEN_WC_MSBYTE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + pub fn gen_dt(&self) -> GEN_DT_R { + GEN_DT_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:7 - NA"] + #[inline(always)] + pub fn gen_vc(&self) -> GEN_VC_R { + GEN_VC_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + pub fn gen_wc_lsbyte(&self) -> GEN_WC_LSBYTE_R { + GEN_WC_LSBYTE_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn gen_wc_msbyte(&self) -> GEN_WC_MSBYTE_R { + GEN_WC_MSBYTE_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_HDR") + .field("gen_dt", &format_args!("{}", self.gen_dt().bits())) + .field("gen_vc", &format_args!("{}", self.gen_vc().bits())) + .field( + "gen_wc_lsbyte", + &format_args!("{}", self.gen_wc_lsbyte().bits()), + ) + .field( + "gen_wc_msbyte", + &format_args!("{}", self.gen_wc_msbyte().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_dt(&mut self) -> GEN_DT_W { + GEN_DT_W::new(self, 0) + } + #[doc = "Bits 6:7 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_vc(&mut self) -> GEN_VC_W { + GEN_VC_W::new(self, 6) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_wc_lsbyte(&mut self) -> GEN_WC_LSBYTE_W { + GEN_WC_LSBYTE_W::new(self, 8) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_wc_msbyte(&mut self) -> GEN_WC_MSBYTE_W { + GEN_WC_MSBYTE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_hdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_hdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_HDR_SPEC; +impl crate::RegisterSpec for GEN_HDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gen_hdr::R`](R) reader structure"] +impl crate::Readable for GEN_HDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_hdr::W`](W) writer structure"] +impl crate::Writable for GEN_HDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GEN_HDR to value 0"] +impl crate::Resettable for GEN_HDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/gen_pld_data.rs b/esp32p4/src/mipi_dsi_host/gen_pld_data.rs new file mode 100644 index 0000000000..29831de40f --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/gen_pld_data.rs @@ -0,0 +1,111 @@ +#[doc = "Register `GEN_PLD_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `GEN_PLD_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `GEN_PLD_B1` reader - NA"] +pub type GEN_PLD_B1_R = crate::FieldReader; +#[doc = "Field `GEN_PLD_B1` writer - NA"] +pub type GEN_PLD_B1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GEN_PLD_B2` reader - NA"] +pub type GEN_PLD_B2_R = crate::FieldReader; +#[doc = "Field `GEN_PLD_B2` writer - NA"] +pub type GEN_PLD_B2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GEN_PLD_B3` reader - NA"] +pub type GEN_PLD_B3_R = crate::FieldReader; +#[doc = "Field `GEN_PLD_B3` writer - NA"] +pub type GEN_PLD_B3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GEN_PLD_B4` reader - NA"] +pub type GEN_PLD_B4_R = crate::FieldReader; +#[doc = "Field `GEN_PLD_B4` writer - NA"] +pub type GEN_PLD_B4_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + pub fn gen_pld_b1(&self) -> GEN_PLD_B1_R { + GEN_PLD_B1_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + pub fn gen_pld_b2(&self) -> GEN_PLD_B2_R { + GEN_PLD_B2_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + pub fn gen_pld_b3(&self) -> GEN_PLD_B3_R { + GEN_PLD_B3_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - NA"] + #[inline(always)] + pub fn gen_pld_b4(&self) -> GEN_PLD_B4_R { + GEN_PLD_B4_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_PLD_DATA") + .field("gen_pld_b1", &format_args!("{}", self.gen_pld_b1().bits())) + .field("gen_pld_b2", &format_args!("{}", self.gen_pld_b2().bits())) + .field("gen_pld_b3", &format_args!("{}", self.gen_pld_b3().bits())) + .field("gen_pld_b4", &format_args!("{}", self.gen_pld_b4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_pld_b1(&mut self) -> GEN_PLD_B1_W { + GEN_PLD_B1_W::new(self, 0) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_pld_b2(&mut self) -> GEN_PLD_B2_W { + GEN_PLD_B2_W::new(self, 8) + } + #[doc = "Bits 16:23 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_pld_b3(&mut self) -> GEN_PLD_B3_W { + GEN_PLD_B3_W::new(self, 16) + } + #[doc = "Bits 24:31 - NA"] + #[inline(always)] + #[must_use] + pub fn gen_pld_b4(&mut self) -> GEN_PLD_B4_W { + GEN_PLD_B4_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_pld_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_pld_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_PLD_DATA_SPEC; +impl crate::RegisterSpec for GEN_PLD_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gen_pld_data::R`](R) reader structure"] +impl crate::Readable for GEN_PLD_DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_pld_data::W`](W) writer structure"] +impl crate::Writable for GEN_PLD_DATA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GEN_PLD_DATA to value 0"] +impl crate::Resettable for GEN_PLD_DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/gen_vcid.rs b/esp32p4/src/mipi_dsi_host/gen_vcid.rs new file mode 100644 index 0000000000..22c8baa5c2 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/gen_vcid.rs @@ -0,0 +1,95 @@ +#[doc = "Register `GEN_VCID` reader"] +pub type R = crate::R; +#[doc = "Register `GEN_VCID` writer"] +pub type W = crate::W; +#[doc = "Field `RX` reader - NA"] +pub type RX_R = crate::FieldReader; +#[doc = "Field `RX` writer - NA"] +pub type RX_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TEAR_AUTO` reader - NA"] +pub type TEAR_AUTO_R = crate::FieldReader; +#[doc = "Field `TEAR_AUTO` writer - NA"] +pub type TEAR_AUTO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TX_AUTO` reader - NA"] +pub type TX_AUTO_R = crate::FieldReader; +#[doc = "Field `TX_AUTO` writer - NA"] +pub type TX_AUTO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn rx(&self) -> RX_R { + RX_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 8:9 - NA"] + #[inline(always)] + pub fn tear_auto(&self) -> TEAR_AUTO_R { + TEAR_AUTO_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 16:17 - NA"] + #[inline(always)] + pub fn tx_auto(&self) -> TX_AUTO_R { + TX_AUTO_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GEN_VCID") + .field("rx", &format_args!("{}", self.rx().bits())) + .field("tear_auto", &format_args!("{}", self.tear_auto().bits())) + .field("tx_auto", &format_args!("{}", self.tx_auto().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + #[must_use] + pub fn rx(&mut self) -> RX_W { + RX_W::new(self, 0) + } + #[doc = "Bits 8:9 - NA"] + #[inline(always)] + #[must_use] + pub fn tear_auto(&mut self) -> TEAR_AUTO_W { + TEAR_AUTO_W::new(self, 8) + } + #[doc = "Bits 16:17 - NA"] + #[inline(always)] + #[must_use] + pub fn tx_auto(&mut self) -> TX_AUTO_W { + TX_AUTO_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gen_vcid::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gen_vcid::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GEN_VCID_SPEC; +impl crate::RegisterSpec for GEN_VCID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gen_vcid::R`](R) reader structure"] +impl crate::Readable for GEN_VCID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gen_vcid::W`](W) writer structure"] +impl crate::Writable for GEN_VCID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GEN_VCID to value 0"] +impl crate::Resettable for GEN_VCID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/hs_rd_to_cnt.rs b/esp32p4/src/mipi_dsi_host/hs_rd_to_cnt.rs new file mode 100644 index 0000000000..0989c3e10c --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/hs_rd_to_cnt.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HS_RD_TO_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `HS_RD_TO_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `HS_RD_TO_CNT` reader - NA"] +pub type HS_RD_TO_CNT_R = crate::FieldReader; +#[doc = "Field `HS_RD_TO_CNT` writer - NA"] +pub type HS_RD_TO_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn hs_rd_to_cnt(&self) -> HS_RD_TO_CNT_R { + HS_RD_TO_CNT_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HS_RD_TO_CNT") + .field( + "hs_rd_to_cnt", + &format_args!("{}", self.hs_rd_to_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn hs_rd_to_cnt(&mut self) -> HS_RD_TO_CNT_W { + HS_RD_TO_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_rd_to_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_rd_to_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HS_RD_TO_CNT_SPEC; +impl crate::RegisterSpec for HS_RD_TO_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hs_rd_to_cnt::R`](R) reader structure"] +impl crate::Readable for HS_RD_TO_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hs_rd_to_cnt::W`](W) writer structure"] +impl crate::Writable for HS_RD_TO_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HS_RD_TO_CNT to value 0"] +impl crate::Resettable for HS_RD_TO_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/hs_wr_to_cnt.rs b/esp32p4/src/mipi_dsi_host/hs_wr_to_cnt.rs new file mode 100644 index 0000000000..d07aecf5da --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/hs_wr_to_cnt.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HS_WR_TO_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `HS_WR_TO_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `HS_WR_TO_CNT` reader - NA"] +pub type HS_WR_TO_CNT_R = crate::FieldReader; +#[doc = "Field `HS_WR_TO_CNT` writer - NA"] +pub type HS_WR_TO_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn hs_wr_to_cnt(&self) -> HS_WR_TO_CNT_R { + HS_WR_TO_CNT_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HS_WR_TO_CNT") + .field( + "hs_wr_to_cnt", + &format_args!("{}", self.hs_wr_to_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn hs_wr_to_cnt(&mut self) -> HS_WR_TO_CNT_W { + HS_WR_TO_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_wr_to_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_wr_to_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HS_WR_TO_CNT_SPEC; +impl crate::RegisterSpec for HS_WR_TO_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hs_wr_to_cnt::R`](R) reader structure"] +impl crate::Readable for HS_WR_TO_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hs_wr_to_cnt::W`](W) writer structure"] +impl crate::Writable for HS_WR_TO_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HS_WR_TO_CNT to value 0"] +impl crate::Resettable for HS_WR_TO_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/int_force0.rs b/esp32p4/src/mipi_dsi_host/int_force0.rs new file mode 100644 index 0000000000..a015771842 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/int_force0.rs @@ -0,0 +1,446 @@ +#[doc = "Register `INT_FORCE0` reader"] +pub type R = crate::R; +#[doc = "Register `INT_FORCE0` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_ACK_WITH_ERR_0` reader - NA"] +pub type FORCE_ACK_WITH_ERR_0_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_0` writer - NA"] +pub type FORCE_ACK_WITH_ERR_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_1` reader - NA"] +pub type FORCE_ACK_WITH_ERR_1_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_1` writer - NA"] +pub type FORCE_ACK_WITH_ERR_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_2` reader - NA"] +pub type FORCE_ACK_WITH_ERR_2_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_2` writer - NA"] +pub type FORCE_ACK_WITH_ERR_2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_3` reader - NA"] +pub type FORCE_ACK_WITH_ERR_3_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_3` writer - NA"] +pub type FORCE_ACK_WITH_ERR_3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_4` reader - NA"] +pub type FORCE_ACK_WITH_ERR_4_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_4` writer - NA"] +pub type FORCE_ACK_WITH_ERR_4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_5` reader - NA"] +pub type FORCE_ACK_WITH_ERR_5_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_5` writer - NA"] +pub type FORCE_ACK_WITH_ERR_5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_6` reader - NA"] +pub type FORCE_ACK_WITH_ERR_6_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_6` writer - NA"] +pub type FORCE_ACK_WITH_ERR_6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_7` reader - NA"] +pub type FORCE_ACK_WITH_ERR_7_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_7` writer - NA"] +pub type FORCE_ACK_WITH_ERR_7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_8` reader - NA"] +pub type FORCE_ACK_WITH_ERR_8_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_8` writer - NA"] +pub type FORCE_ACK_WITH_ERR_8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_9` reader - NA"] +pub type FORCE_ACK_WITH_ERR_9_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_9` writer - NA"] +pub type FORCE_ACK_WITH_ERR_9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_10` reader - NA"] +pub type FORCE_ACK_WITH_ERR_10_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_10` writer - NA"] +pub type FORCE_ACK_WITH_ERR_10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_11` reader - NA"] +pub type FORCE_ACK_WITH_ERR_11_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_11` writer - NA"] +pub type FORCE_ACK_WITH_ERR_11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_12` reader - NA"] +pub type FORCE_ACK_WITH_ERR_12_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_12` writer - NA"] +pub type FORCE_ACK_WITH_ERR_12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_13` reader - NA"] +pub type FORCE_ACK_WITH_ERR_13_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_13` writer - NA"] +pub type FORCE_ACK_WITH_ERR_13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_14` reader - NA"] +pub type FORCE_ACK_WITH_ERR_14_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_14` writer - NA"] +pub type FORCE_ACK_WITH_ERR_14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ACK_WITH_ERR_15` reader - NA"] +pub type FORCE_ACK_WITH_ERR_15_R = crate::BitReader; +#[doc = "Field `FORCE_ACK_WITH_ERR_15` writer - NA"] +pub type FORCE_ACK_WITH_ERR_15_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_DPHY_ERRORS_0` reader - NA"] +pub type FORCE_DPHY_ERRORS_0_R = crate::BitReader; +#[doc = "Field `FORCE_DPHY_ERRORS_0` writer - NA"] +pub type FORCE_DPHY_ERRORS_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_DPHY_ERRORS_1` reader - NA"] +pub type FORCE_DPHY_ERRORS_1_R = crate::BitReader; +#[doc = "Field `FORCE_DPHY_ERRORS_1` writer - NA"] +pub type FORCE_DPHY_ERRORS_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_DPHY_ERRORS_2` reader - NA"] +pub type FORCE_DPHY_ERRORS_2_R = crate::BitReader; +#[doc = "Field `FORCE_DPHY_ERRORS_2` writer - NA"] +pub type FORCE_DPHY_ERRORS_2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_DPHY_ERRORS_3` reader - NA"] +pub type FORCE_DPHY_ERRORS_3_R = crate::BitReader; +#[doc = "Field `FORCE_DPHY_ERRORS_3` writer - NA"] +pub type FORCE_DPHY_ERRORS_3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_DPHY_ERRORS_4` reader - NA"] +pub type FORCE_DPHY_ERRORS_4_R = crate::BitReader; +#[doc = "Field `FORCE_DPHY_ERRORS_4` writer - NA"] +pub type FORCE_DPHY_ERRORS_4_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn force_ack_with_err_0(&self) -> FORCE_ACK_WITH_ERR_0_R { + FORCE_ACK_WITH_ERR_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn force_ack_with_err_1(&self) -> FORCE_ACK_WITH_ERR_1_R { + FORCE_ACK_WITH_ERR_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn force_ack_with_err_2(&self) -> FORCE_ACK_WITH_ERR_2_R { + FORCE_ACK_WITH_ERR_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn force_ack_with_err_3(&self) -> FORCE_ACK_WITH_ERR_3_R { + FORCE_ACK_WITH_ERR_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn force_ack_with_err_4(&self) -> FORCE_ACK_WITH_ERR_4_R { + FORCE_ACK_WITH_ERR_4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn force_ack_with_err_5(&self) -> FORCE_ACK_WITH_ERR_5_R { + FORCE_ACK_WITH_ERR_5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn force_ack_with_err_6(&self) -> FORCE_ACK_WITH_ERR_6_R { + FORCE_ACK_WITH_ERR_6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn force_ack_with_err_7(&self) -> FORCE_ACK_WITH_ERR_7_R { + FORCE_ACK_WITH_ERR_7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn force_ack_with_err_8(&self) -> FORCE_ACK_WITH_ERR_8_R { + FORCE_ACK_WITH_ERR_8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn force_ack_with_err_9(&self) -> FORCE_ACK_WITH_ERR_9_R { + FORCE_ACK_WITH_ERR_9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn force_ack_with_err_10(&self) -> FORCE_ACK_WITH_ERR_10_R { + FORCE_ACK_WITH_ERR_10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn force_ack_with_err_11(&self) -> FORCE_ACK_WITH_ERR_11_R { + FORCE_ACK_WITH_ERR_11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn force_ack_with_err_12(&self) -> FORCE_ACK_WITH_ERR_12_R { + FORCE_ACK_WITH_ERR_12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn force_ack_with_err_13(&self) -> FORCE_ACK_WITH_ERR_13_R { + FORCE_ACK_WITH_ERR_13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn force_ack_with_err_14(&self) -> FORCE_ACK_WITH_ERR_14_R { + FORCE_ACK_WITH_ERR_14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn force_ack_with_err_15(&self) -> FORCE_ACK_WITH_ERR_15_R { + FORCE_ACK_WITH_ERR_15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn force_dphy_errors_0(&self) -> FORCE_DPHY_ERRORS_0_R { + FORCE_DPHY_ERRORS_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn force_dphy_errors_1(&self) -> FORCE_DPHY_ERRORS_1_R { + FORCE_DPHY_ERRORS_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn force_dphy_errors_2(&self) -> FORCE_DPHY_ERRORS_2_R { + FORCE_DPHY_ERRORS_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn force_dphy_errors_3(&self) -> FORCE_DPHY_ERRORS_3_R { + FORCE_DPHY_ERRORS_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn force_dphy_errors_4(&self) -> FORCE_DPHY_ERRORS_4_R { + FORCE_DPHY_ERRORS_4_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_FORCE0") + .field( + "force_ack_with_err_0", + &format_args!("{}", self.force_ack_with_err_0().bit()), + ) + .field( + "force_ack_with_err_1", + &format_args!("{}", self.force_ack_with_err_1().bit()), + ) + .field( + "force_ack_with_err_2", + &format_args!("{}", self.force_ack_with_err_2().bit()), + ) + .field( + "force_ack_with_err_3", + &format_args!("{}", self.force_ack_with_err_3().bit()), + ) + .field( + "force_ack_with_err_4", + &format_args!("{}", self.force_ack_with_err_4().bit()), + ) + .field( + "force_ack_with_err_5", + &format_args!("{}", self.force_ack_with_err_5().bit()), + ) + .field( + "force_ack_with_err_6", + &format_args!("{}", self.force_ack_with_err_6().bit()), + ) + .field( + "force_ack_with_err_7", + &format_args!("{}", self.force_ack_with_err_7().bit()), + ) + .field( + "force_ack_with_err_8", + &format_args!("{}", self.force_ack_with_err_8().bit()), + ) + .field( + "force_ack_with_err_9", + &format_args!("{}", self.force_ack_with_err_9().bit()), + ) + .field( + "force_ack_with_err_10", + &format_args!("{}", self.force_ack_with_err_10().bit()), + ) + .field( + "force_ack_with_err_11", + &format_args!("{}", self.force_ack_with_err_11().bit()), + ) + .field( + "force_ack_with_err_12", + &format_args!("{}", self.force_ack_with_err_12().bit()), + ) + .field( + "force_ack_with_err_13", + &format_args!("{}", self.force_ack_with_err_13().bit()), + ) + .field( + "force_ack_with_err_14", + &format_args!("{}", self.force_ack_with_err_14().bit()), + ) + .field( + "force_ack_with_err_15", + &format_args!("{}", self.force_ack_with_err_15().bit()), + ) + .field( + "force_dphy_errors_0", + &format_args!("{}", self.force_dphy_errors_0().bit()), + ) + .field( + "force_dphy_errors_1", + &format_args!("{}", self.force_dphy_errors_1().bit()), + ) + .field( + "force_dphy_errors_2", + &format_args!("{}", self.force_dphy_errors_2().bit()), + ) + .field( + "force_dphy_errors_3", + &format_args!("{}", self.force_dphy_errors_3().bit()), + ) + .field( + "force_dphy_errors_4", + &format_args!("{}", self.force_dphy_errors_4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_0(&mut self) -> FORCE_ACK_WITH_ERR_0_W { + FORCE_ACK_WITH_ERR_0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_1(&mut self) -> FORCE_ACK_WITH_ERR_1_W { + FORCE_ACK_WITH_ERR_1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_2(&mut self) -> FORCE_ACK_WITH_ERR_2_W { + FORCE_ACK_WITH_ERR_2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_3(&mut self) -> FORCE_ACK_WITH_ERR_3_W { + FORCE_ACK_WITH_ERR_3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_4(&mut self) -> FORCE_ACK_WITH_ERR_4_W { + FORCE_ACK_WITH_ERR_4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_5(&mut self) -> FORCE_ACK_WITH_ERR_5_W { + FORCE_ACK_WITH_ERR_5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_6(&mut self) -> FORCE_ACK_WITH_ERR_6_W { + FORCE_ACK_WITH_ERR_6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_7(&mut self) -> FORCE_ACK_WITH_ERR_7_W { + FORCE_ACK_WITH_ERR_7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_8(&mut self) -> FORCE_ACK_WITH_ERR_8_W { + FORCE_ACK_WITH_ERR_8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_9(&mut self) -> FORCE_ACK_WITH_ERR_9_W { + FORCE_ACK_WITH_ERR_9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_10(&mut self) -> FORCE_ACK_WITH_ERR_10_W { + FORCE_ACK_WITH_ERR_10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_11(&mut self) -> FORCE_ACK_WITH_ERR_11_W { + FORCE_ACK_WITH_ERR_11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_12(&mut self) -> FORCE_ACK_WITH_ERR_12_W { + FORCE_ACK_WITH_ERR_12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_13(&mut self) -> FORCE_ACK_WITH_ERR_13_W { + FORCE_ACK_WITH_ERR_13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_14(&mut self) -> FORCE_ACK_WITH_ERR_14_W { + FORCE_ACK_WITH_ERR_14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ack_with_err_15(&mut self) -> FORCE_ACK_WITH_ERR_15_W { + FORCE_ACK_WITH_ERR_15_W::new(self, 15) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn force_dphy_errors_0(&mut self) -> FORCE_DPHY_ERRORS_0_W { + FORCE_DPHY_ERRORS_0_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn force_dphy_errors_1(&mut self) -> FORCE_DPHY_ERRORS_1_W { + FORCE_DPHY_ERRORS_1_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn force_dphy_errors_2(&mut self) -> FORCE_DPHY_ERRORS_2_W { + FORCE_DPHY_ERRORS_2_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn force_dphy_errors_3(&mut self) -> FORCE_DPHY_ERRORS_3_W { + FORCE_DPHY_ERRORS_3_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn force_dphy_errors_4(&mut self) -> FORCE_DPHY_ERRORS_4_W { + FORCE_DPHY_ERRORS_4_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_FORCE0_SPEC; +impl crate::RegisterSpec for INT_FORCE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_force0::R`](R) reader structure"] +impl crate::Readable for INT_FORCE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_force0::W`](W) writer structure"] +impl crate::Writable for INT_FORCE0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_FORCE0 to value 0"] +impl crate::Resettable for INT_FORCE0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/int_force1.rs b/esp32p4/src/mipi_dsi_host/int_force1.rs new file mode 100644 index 0000000000..4b1a62a999 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/int_force1.rs @@ -0,0 +1,313 @@ +#[doc = "Register `INT_FORCE1` reader"] +pub type R = crate::R; +#[doc = "Register `INT_FORCE1` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_TO_HS_TX` reader - NA"] +pub type FORCE_TO_HS_TX_R = crate::BitReader; +#[doc = "Field `FORCE_TO_HS_TX` writer - NA"] +pub type FORCE_TO_HS_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_TO_LP_RX` reader - NA"] +pub type FORCE_TO_LP_RX_R = crate::BitReader; +#[doc = "Field `FORCE_TO_LP_RX` writer - NA"] +pub type FORCE_TO_LP_RX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ECC_SINGLE_ERR` reader - NA"] +pub type FORCE_ECC_SINGLE_ERR_R = crate::BitReader; +#[doc = "Field `FORCE_ECC_SINGLE_ERR` writer - NA"] +pub type FORCE_ECC_SINGLE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_ECC_MILTI_ERR` reader - NA"] +pub type FORCE_ECC_MILTI_ERR_R = crate::BitReader; +#[doc = "Field `FORCE_ECC_MILTI_ERR` writer - NA"] +pub type FORCE_ECC_MILTI_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_CRC_ERR` reader - NA"] +pub type FORCE_CRC_ERR_R = crate::BitReader; +#[doc = "Field `FORCE_CRC_ERR` writer - NA"] +pub type FORCE_CRC_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_PKT_SIZE_ERR` reader - NA"] +pub type FORCE_PKT_SIZE_ERR_R = crate::BitReader; +#[doc = "Field `FORCE_PKT_SIZE_ERR` writer - NA"] +pub type FORCE_PKT_SIZE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_EOPT_ERR` reader - NA"] +pub type FORCE_EOPT_ERR_R = crate::BitReader; +#[doc = "Field `FORCE_EOPT_ERR` writer - NA"] +pub type FORCE_EOPT_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_DPI_PLD_WR_ERR` reader - NA"] +pub type FORCE_DPI_PLD_WR_ERR_R = crate::BitReader; +#[doc = "Field `FORCE_DPI_PLD_WR_ERR` writer - NA"] +pub type FORCE_DPI_PLD_WR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_GEN_CMD_WR_ERR` reader - NA"] +pub type FORCE_GEN_CMD_WR_ERR_R = crate::BitReader; +#[doc = "Field `FORCE_GEN_CMD_WR_ERR` writer - NA"] +pub type FORCE_GEN_CMD_WR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_GEN_PLD_WR_ERR` reader - NA"] +pub type FORCE_GEN_PLD_WR_ERR_R = crate::BitReader; +#[doc = "Field `FORCE_GEN_PLD_WR_ERR` writer - NA"] +pub type FORCE_GEN_PLD_WR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_GEN_PLD_SEND_ERR` reader - NA"] +pub type FORCE_GEN_PLD_SEND_ERR_R = crate::BitReader; +#[doc = "Field `FORCE_GEN_PLD_SEND_ERR` writer - NA"] +pub type FORCE_GEN_PLD_SEND_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_GEN_PLD_RD_ERR` reader - NA"] +pub type FORCE_GEN_PLD_RD_ERR_R = crate::BitReader; +#[doc = "Field `FORCE_GEN_PLD_RD_ERR` writer - NA"] +pub type FORCE_GEN_PLD_RD_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_GEN_PLD_RECEV_ERR` reader - NA"] +pub type FORCE_GEN_PLD_RECEV_ERR_R = crate::BitReader; +#[doc = "Field `FORCE_GEN_PLD_RECEV_ERR` writer - NA"] +pub type FORCE_GEN_PLD_RECEV_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_DPI_BUFF_PLD_UNDER` reader - NA"] +pub type FORCE_DPI_BUFF_PLD_UNDER_R = crate::BitReader; +#[doc = "Field `FORCE_DPI_BUFF_PLD_UNDER` writer - NA"] +pub type FORCE_DPI_BUFF_PLD_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn force_to_hs_tx(&self) -> FORCE_TO_HS_TX_R { + FORCE_TO_HS_TX_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn force_to_lp_rx(&self) -> FORCE_TO_LP_RX_R { + FORCE_TO_LP_RX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn force_ecc_single_err(&self) -> FORCE_ECC_SINGLE_ERR_R { + FORCE_ECC_SINGLE_ERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn force_ecc_milti_err(&self) -> FORCE_ECC_MILTI_ERR_R { + FORCE_ECC_MILTI_ERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn force_crc_err(&self) -> FORCE_CRC_ERR_R { + FORCE_CRC_ERR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn force_pkt_size_err(&self) -> FORCE_PKT_SIZE_ERR_R { + FORCE_PKT_SIZE_ERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn force_eopt_err(&self) -> FORCE_EOPT_ERR_R { + FORCE_EOPT_ERR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn force_dpi_pld_wr_err(&self) -> FORCE_DPI_PLD_WR_ERR_R { + FORCE_DPI_PLD_WR_ERR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn force_gen_cmd_wr_err(&self) -> FORCE_GEN_CMD_WR_ERR_R { + FORCE_GEN_CMD_WR_ERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn force_gen_pld_wr_err(&self) -> FORCE_GEN_PLD_WR_ERR_R { + FORCE_GEN_PLD_WR_ERR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn force_gen_pld_send_err(&self) -> FORCE_GEN_PLD_SEND_ERR_R { + FORCE_GEN_PLD_SEND_ERR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn force_gen_pld_rd_err(&self) -> FORCE_GEN_PLD_RD_ERR_R { + FORCE_GEN_PLD_RD_ERR_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn force_gen_pld_recev_err(&self) -> FORCE_GEN_PLD_RECEV_ERR_R { + FORCE_GEN_PLD_RECEV_ERR_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn force_dpi_buff_pld_under(&self) -> FORCE_DPI_BUFF_PLD_UNDER_R { + FORCE_DPI_BUFF_PLD_UNDER_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_FORCE1") + .field( + "force_to_hs_tx", + &format_args!("{}", self.force_to_hs_tx().bit()), + ) + .field( + "force_to_lp_rx", + &format_args!("{}", self.force_to_lp_rx().bit()), + ) + .field( + "force_ecc_single_err", + &format_args!("{}", self.force_ecc_single_err().bit()), + ) + .field( + "force_ecc_milti_err", + &format_args!("{}", self.force_ecc_milti_err().bit()), + ) + .field( + "force_crc_err", + &format_args!("{}", self.force_crc_err().bit()), + ) + .field( + "force_pkt_size_err", + &format_args!("{}", self.force_pkt_size_err().bit()), + ) + .field( + "force_eopt_err", + &format_args!("{}", self.force_eopt_err().bit()), + ) + .field( + "force_dpi_pld_wr_err", + &format_args!("{}", self.force_dpi_pld_wr_err().bit()), + ) + .field( + "force_gen_cmd_wr_err", + &format_args!("{}", self.force_gen_cmd_wr_err().bit()), + ) + .field( + "force_gen_pld_wr_err", + &format_args!("{}", self.force_gen_pld_wr_err().bit()), + ) + .field( + "force_gen_pld_send_err", + &format_args!("{}", self.force_gen_pld_send_err().bit()), + ) + .field( + "force_gen_pld_rd_err", + &format_args!("{}", self.force_gen_pld_rd_err().bit()), + ) + .field( + "force_gen_pld_recev_err", + &format_args!("{}", self.force_gen_pld_recev_err().bit()), + ) + .field( + "force_dpi_buff_pld_under", + &format_args!("{}", self.force_dpi_buff_pld_under().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn force_to_hs_tx(&mut self) -> FORCE_TO_HS_TX_W { + FORCE_TO_HS_TX_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn force_to_lp_rx(&mut self) -> FORCE_TO_LP_RX_W { + FORCE_TO_LP_RX_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ecc_single_err(&mut self) -> FORCE_ECC_SINGLE_ERR_W { + FORCE_ECC_SINGLE_ERR_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn force_ecc_milti_err(&mut self) -> FORCE_ECC_MILTI_ERR_W { + FORCE_ECC_MILTI_ERR_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn force_crc_err(&mut self) -> FORCE_CRC_ERR_W { + FORCE_CRC_ERR_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn force_pkt_size_err(&mut self) -> FORCE_PKT_SIZE_ERR_W { + FORCE_PKT_SIZE_ERR_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn force_eopt_err(&mut self) -> FORCE_EOPT_ERR_W { + FORCE_EOPT_ERR_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn force_dpi_pld_wr_err(&mut self) -> FORCE_DPI_PLD_WR_ERR_W { + FORCE_DPI_PLD_WR_ERR_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn force_gen_cmd_wr_err(&mut self) -> FORCE_GEN_CMD_WR_ERR_W { + FORCE_GEN_CMD_WR_ERR_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn force_gen_pld_wr_err(&mut self) -> FORCE_GEN_PLD_WR_ERR_W { + FORCE_GEN_PLD_WR_ERR_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn force_gen_pld_send_err(&mut self) -> FORCE_GEN_PLD_SEND_ERR_W { + FORCE_GEN_PLD_SEND_ERR_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn force_gen_pld_rd_err(&mut self) -> FORCE_GEN_PLD_RD_ERR_W { + FORCE_GEN_PLD_RD_ERR_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn force_gen_pld_recev_err(&mut self) -> FORCE_GEN_PLD_RECEV_ERR_W { + FORCE_GEN_PLD_RECEV_ERR_W::new(self, 12) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn force_dpi_buff_pld_under(&mut self) -> FORCE_DPI_BUFF_PLD_UNDER_W { + FORCE_DPI_BUFF_PLD_UNDER_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_force1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_force1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_FORCE1_SPEC; +impl crate::RegisterSpec for INT_FORCE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_force1::R`](R) reader structure"] +impl crate::Readable for INT_FORCE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_force1::W`](W) writer structure"] +impl crate::Writable for INT_FORCE1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_FORCE1 to value 0"] +impl crate::Resettable for INT_FORCE1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/int_msk0.rs b/esp32p4/src/mipi_dsi_host/int_msk0.rs new file mode 100644 index 0000000000..fa43803ee6 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/int_msk0.rs @@ -0,0 +1,446 @@ +#[doc = "Register `INT_MSK0` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MSK0` writer"] +pub type W = crate::W; +#[doc = "Field `MASK_ACK_WITH_ERR_0` reader - NA"] +pub type MASK_ACK_WITH_ERR_0_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_0` writer - NA"] +pub type MASK_ACK_WITH_ERR_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_1` reader - NA"] +pub type MASK_ACK_WITH_ERR_1_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_1` writer - NA"] +pub type MASK_ACK_WITH_ERR_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_2` reader - NA"] +pub type MASK_ACK_WITH_ERR_2_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_2` writer - NA"] +pub type MASK_ACK_WITH_ERR_2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_3` reader - NA"] +pub type MASK_ACK_WITH_ERR_3_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_3` writer - NA"] +pub type MASK_ACK_WITH_ERR_3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_4` reader - NA"] +pub type MASK_ACK_WITH_ERR_4_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_4` writer - NA"] +pub type MASK_ACK_WITH_ERR_4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_5` reader - NA"] +pub type MASK_ACK_WITH_ERR_5_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_5` writer - NA"] +pub type MASK_ACK_WITH_ERR_5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_6` reader - NA"] +pub type MASK_ACK_WITH_ERR_6_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_6` writer - NA"] +pub type MASK_ACK_WITH_ERR_6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_7` reader - NA"] +pub type MASK_ACK_WITH_ERR_7_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_7` writer - NA"] +pub type MASK_ACK_WITH_ERR_7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_8` reader - NA"] +pub type MASK_ACK_WITH_ERR_8_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_8` writer - NA"] +pub type MASK_ACK_WITH_ERR_8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_9` reader - NA"] +pub type MASK_ACK_WITH_ERR_9_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_9` writer - NA"] +pub type MASK_ACK_WITH_ERR_9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_10` reader - NA"] +pub type MASK_ACK_WITH_ERR_10_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_10` writer - NA"] +pub type MASK_ACK_WITH_ERR_10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_11` reader - NA"] +pub type MASK_ACK_WITH_ERR_11_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_11` writer - NA"] +pub type MASK_ACK_WITH_ERR_11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_12` reader - NA"] +pub type MASK_ACK_WITH_ERR_12_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_12` writer - NA"] +pub type MASK_ACK_WITH_ERR_12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_13` reader - NA"] +pub type MASK_ACK_WITH_ERR_13_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_13` writer - NA"] +pub type MASK_ACK_WITH_ERR_13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_14` reader - NA"] +pub type MASK_ACK_WITH_ERR_14_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_14` writer - NA"] +pub type MASK_ACK_WITH_ERR_14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ACK_WITH_ERR_15` reader - NA"] +pub type MASK_ACK_WITH_ERR_15_R = crate::BitReader; +#[doc = "Field `MASK_ACK_WITH_ERR_15` writer - NA"] +pub type MASK_ACK_WITH_ERR_15_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_DPHY_ERRORS_0` reader - NA"] +pub type MASK_DPHY_ERRORS_0_R = crate::BitReader; +#[doc = "Field `MASK_DPHY_ERRORS_0` writer - NA"] +pub type MASK_DPHY_ERRORS_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_DPHY_ERRORS_1` reader - NA"] +pub type MASK_DPHY_ERRORS_1_R = crate::BitReader; +#[doc = "Field `MASK_DPHY_ERRORS_1` writer - NA"] +pub type MASK_DPHY_ERRORS_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_DPHY_ERRORS_2` reader - NA"] +pub type MASK_DPHY_ERRORS_2_R = crate::BitReader; +#[doc = "Field `MASK_DPHY_ERRORS_2` writer - NA"] +pub type MASK_DPHY_ERRORS_2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_DPHY_ERRORS_3` reader - NA"] +pub type MASK_DPHY_ERRORS_3_R = crate::BitReader; +#[doc = "Field `MASK_DPHY_ERRORS_3` writer - NA"] +pub type MASK_DPHY_ERRORS_3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_DPHY_ERRORS_4` reader - NA"] +pub type MASK_DPHY_ERRORS_4_R = crate::BitReader; +#[doc = "Field `MASK_DPHY_ERRORS_4` writer - NA"] +pub type MASK_DPHY_ERRORS_4_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_0(&self) -> MASK_ACK_WITH_ERR_0_R { + MASK_ACK_WITH_ERR_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_1(&self) -> MASK_ACK_WITH_ERR_1_R { + MASK_ACK_WITH_ERR_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_2(&self) -> MASK_ACK_WITH_ERR_2_R { + MASK_ACK_WITH_ERR_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_3(&self) -> MASK_ACK_WITH_ERR_3_R { + MASK_ACK_WITH_ERR_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_4(&self) -> MASK_ACK_WITH_ERR_4_R { + MASK_ACK_WITH_ERR_4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_5(&self) -> MASK_ACK_WITH_ERR_5_R { + MASK_ACK_WITH_ERR_5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_6(&self) -> MASK_ACK_WITH_ERR_6_R { + MASK_ACK_WITH_ERR_6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_7(&self) -> MASK_ACK_WITH_ERR_7_R { + MASK_ACK_WITH_ERR_7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_8(&self) -> MASK_ACK_WITH_ERR_8_R { + MASK_ACK_WITH_ERR_8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_9(&self) -> MASK_ACK_WITH_ERR_9_R { + MASK_ACK_WITH_ERR_9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_10(&self) -> MASK_ACK_WITH_ERR_10_R { + MASK_ACK_WITH_ERR_10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_11(&self) -> MASK_ACK_WITH_ERR_11_R { + MASK_ACK_WITH_ERR_11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_12(&self) -> MASK_ACK_WITH_ERR_12_R { + MASK_ACK_WITH_ERR_12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_13(&self) -> MASK_ACK_WITH_ERR_13_R { + MASK_ACK_WITH_ERR_13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_14(&self) -> MASK_ACK_WITH_ERR_14_R { + MASK_ACK_WITH_ERR_14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn mask_ack_with_err_15(&self) -> MASK_ACK_WITH_ERR_15_R { + MASK_ACK_WITH_ERR_15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn mask_dphy_errors_0(&self) -> MASK_DPHY_ERRORS_0_R { + MASK_DPHY_ERRORS_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn mask_dphy_errors_1(&self) -> MASK_DPHY_ERRORS_1_R { + MASK_DPHY_ERRORS_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn mask_dphy_errors_2(&self) -> MASK_DPHY_ERRORS_2_R { + MASK_DPHY_ERRORS_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn mask_dphy_errors_3(&self) -> MASK_DPHY_ERRORS_3_R { + MASK_DPHY_ERRORS_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn mask_dphy_errors_4(&self) -> MASK_DPHY_ERRORS_4_R { + MASK_DPHY_ERRORS_4_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_MSK0") + .field( + "mask_ack_with_err_0", + &format_args!("{}", self.mask_ack_with_err_0().bit()), + ) + .field( + "mask_ack_with_err_1", + &format_args!("{}", self.mask_ack_with_err_1().bit()), + ) + .field( + "mask_ack_with_err_2", + &format_args!("{}", self.mask_ack_with_err_2().bit()), + ) + .field( + "mask_ack_with_err_3", + &format_args!("{}", self.mask_ack_with_err_3().bit()), + ) + .field( + "mask_ack_with_err_4", + &format_args!("{}", self.mask_ack_with_err_4().bit()), + ) + .field( + "mask_ack_with_err_5", + &format_args!("{}", self.mask_ack_with_err_5().bit()), + ) + .field( + "mask_ack_with_err_6", + &format_args!("{}", self.mask_ack_with_err_6().bit()), + ) + .field( + "mask_ack_with_err_7", + &format_args!("{}", self.mask_ack_with_err_7().bit()), + ) + .field( + "mask_ack_with_err_8", + &format_args!("{}", self.mask_ack_with_err_8().bit()), + ) + .field( + "mask_ack_with_err_9", + &format_args!("{}", self.mask_ack_with_err_9().bit()), + ) + .field( + "mask_ack_with_err_10", + &format_args!("{}", self.mask_ack_with_err_10().bit()), + ) + .field( + "mask_ack_with_err_11", + &format_args!("{}", self.mask_ack_with_err_11().bit()), + ) + .field( + "mask_ack_with_err_12", + &format_args!("{}", self.mask_ack_with_err_12().bit()), + ) + .field( + "mask_ack_with_err_13", + &format_args!("{}", self.mask_ack_with_err_13().bit()), + ) + .field( + "mask_ack_with_err_14", + &format_args!("{}", self.mask_ack_with_err_14().bit()), + ) + .field( + "mask_ack_with_err_15", + &format_args!("{}", self.mask_ack_with_err_15().bit()), + ) + .field( + "mask_dphy_errors_0", + &format_args!("{}", self.mask_dphy_errors_0().bit()), + ) + .field( + "mask_dphy_errors_1", + &format_args!("{}", self.mask_dphy_errors_1().bit()), + ) + .field( + "mask_dphy_errors_2", + &format_args!("{}", self.mask_dphy_errors_2().bit()), + ) + .field( + "mask_dphy_errors_3", + &format_args!("{}", self.mask_dphy_errors_3().bit()), + ) + .field( + "mask_dphy_errors_4", + &format_args!("{}", self.mask_dphy_errors_4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_0(&mut self) -> MASK_ACK_WITH_ERR_0_W { + MASK_ACK_WITH_ERR_0_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_1(&mut self) -> MASK_ACK_WITH_ERR_1_W { + MASK_ACK_WITH_ERR_1_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_2(&mut self) -> MASK_ACK_WITH_ERR_2_W { + MASK_ACK_WITH_ERR_2_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_3(&mut self) -> MASK_ACK_WITH_ERR_3_W { + MASK_ACK_WITH_ERR_3_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_4(&mut self) -> MASK_ACK_WITH_ERR_4_W { + MASK_ACK_WITH_ERR_4_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_5(&mut self) -> MASK_ACK_WITH_ERR_5_W { + MASK_ACK_WITH_ERR_5_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_6(&mut self) -> MASK_ACK_WITH_ERR_6_W { + MASK_ACK_WITH_ERR_6_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_7(&mut self) -> MASK_ACK_WITH_ERR_7_W { + MASK_ACK_WITH_ERR_7_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_8(&mut self) -> MASK_ACK_WITH_ERR_8_W { + MASK_ACK_WITH_ERR_8_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_9(&mut self) -> MASK_ACK_WITH_ERR_9_W { + MASK_ACK_WITH_ERR_9_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_10(&mut self) -> MASK_ACK_WITH_ERR_10_W { + MASK_ACK_WITH_ERR_10_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_11(&mut self) -> MASK_ACK_WITH_ERR_11_W { + MASK_ACK_WITH_ERR_11_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_12(&mut self) -> MASK_ACK_WITH_ERR_12_W { + MASK_ACK_WITH_ERR_12_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_13(&mut self) -> MASK_ACK_WITH_ERR_13_W { + MASK_ACK_WITH_ERR_13_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_14(&mut self) -> MASK_ACK_WITH_ERR_14_W { + MASK_ACK_WITH_ERR_14_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ack_with_err_15(&mut self) -> MASK_ACK_WITH_ERR_15_W { + MASK_ACK_WITH_ERR_15_W::new(self, 15) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_dphy_errors_0(&mut self) -> MASK_DPHY_ERRORS_0_W { + MASK_DPHY_ERRORS_0_W::new(self, 16) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_dphy_errors_1(&mut self) -> MASK_DPHY_ERRORS_1_W { + MASK_DPHY_ERRORS_1_W::new(self, 17) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_dphy_errors_2(&mut self) -> MASK_DPHY_ERRORS_2_W { + MASK_DPHY_ERRORS_2_W::new(self, 18) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_dphy_errors_3(&mut self) -> MASK_DPHY_ERRORS_3_W { + MASK_DPHY_ERRORS_3_W::new(self, 19) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_dphy_errors_4(&mut self) -> MASK_DPHY_ERRORS_4_W { + MASK_DPHY_ERRORS_4_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_MSK0_SPEC; +impl crate::RegisterSpec for INT_MSK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_msk0::R`](R) reader structure"] +impl crate::Readable for INT_MSK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_msk0::W`](W) writer structure"] +impl crate::Writable for INT_MSK0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_MSK0 to value 0"] +impl crate::Resettable for INT_MSK0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/int_msk1.rs b/esp32p4/src/mipi_dsi_host/int_msk1.rs new file mode 100644 index 0000000000..6a18c73011 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/int_msk1.rs @@ -0,0 +1,313 @@ +#[doc = "Register `INT_MSK1` reader"] +pub type R = crate::R; +#[doc = "Register `INT_MSK1` writer"] +pub type W = crate::W; +#[doc = "Field `MASK_TO_HS_TX` reader - NA"] +pub type MASK_TO_HS_TX_R = crate::BitReader; +#[doc = "Field `MASK_TO_HS_TX` writer - NA"] +pub type MASK_TO_HS_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_TO_LP_RX` reader - NA"] +pub type MASK_TO_LP_RX_R = crate::BitReader; +#[doc = "Field `MASK_TO_LP_RX` writer - NA"] +pub type MASK_TO_LP_RX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ECC_SINGLE_ERR` reader - NA"] +pub type MASK_ECC_SINGLE_ERR_R = crate::BitReader; +#[doc = "Field `MASK_ECC_SINGLE_ERR` writer - NA"] +pub type MASK_ECC_SINGLE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_ECC_MILTI_ERR` reader - NA"] +pub type MASK_ECC_MILTI_ERR_R = crate::BitReader; +#[doc = "Field `MASK_ECC_MILTI_ERR` writer - NA"] +pub type MASK_ECC_MILTI_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_CRC_ERR` reader - NA"] +pub type MASK_CRC_ERR_R = crate::BitReader; +#[doc = "Field `MASK_CRC_ERR` writer - NA"] +pub type MASK_CRC_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_PKT_SIZE_ERR` reader - NA"] +pub type MASK_PKT_SIZE_ERR_R = crate::BitReader; +#[doc = "Field `MASK_PKT_SIZE_ERR` writer - NA"] +pub type MASK_PKT_SIZE_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_EOPT_ERR` reader - NA"] +pub type MASK_EOPT_ERR_R = crate::BitReader; +#[doc = "Field `MASK_EOPT_ERR` writer - NA"] +pub type MASK_EOPT_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_DPI_PLD_WR_ERR` reader - NA"] +pub type MASK_DPI_PLD_WR_ERR_R = crate::BitReader; +#[doc = "Field `MASK_DPI_PLD_WR_ERR` writer - NA"] +pub type MASK_DPI_PLD_WR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_GEN_CMD_WR_ERR` reader - NA"] +pub type MASK_GEN_CMD_WR_ERR_R = crate::BitReader; +#[doc = "Field `MASK_GEN_CMD_WR_ERR` writer - NA"] +pub type MASK_GEN_CMD_WR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_GEN_PLD_WR_ERR` reader - NA"] +pub type MASK_GEN_PLD_WR_ERR_R = crate::BitReader; +#[doc = "Field `MASK_GEN_PLD_WR_ERR` writer - NA"] +pub type MASK_GEN_PLD_WR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_GEN_PLD_SEND_ERR` reader - NA"] +pub type MASK_GEN_PLD_SEND_ERR_R = crate::BitReader; +#[doc = "Field `MASK_GEN_PLD_SEND_ERR` writer - NA"] +pub type MASK_GEN_PLD_SEND_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_GEN_PLD_RD_ERR` reader - NA"] +pub type MASK_GEN_PLD_RD_ERR_R = crate::BitReader; +#[doc = "Field `MASK_GEN_PLD_RD_ERR` writer - NA"] +pub type MASK_GEN_PLD_RD_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_GEN_PLD_RECEV_ERR` reader - NA"] +pub type MASK_GEN_PLD_RECEV_ERR_R = crate::BitReader; +#[doc = "Field `MASK_GEN_PLD_RECEV_ERR` writer - NA"] +pub type MASK_GEN_PLD_RECEV_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK_DPI_BUFF_PLD_UNDER` reader - NA"] +pub type MASK_DPI_BUFF_PLD_UNDER_R = crate::BitReader; +#[doc = "Field `MASK_DPI_BUFF_PLD_UNDER` writer - NA"] +pub type MASK_DPI_BUFF_PLD_UNDER_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn mask_to_hs_tx(&self) -> MASK_TO_HS_TX_R { + MASK_TO_HS_TX_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn mask_to_lp_rx(&self) -> MASK_TO_LP_RX_R { + MASK_TO_LP_RX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn mask_ecc_single_err(&self) -> MASK_ECC_SINGLE_ERR_R { + MASK_ECC_SINGLE_ERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn mask_ecc_milti_err(&self) -> MASK_ECC_MILTI_ERR_R { + MASK_ECC_MILTI_ERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn mask_crc_err(&self) -> MASK_CRC_ERR_R { + MASK_CRC_ERR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn mask_pkt_size_err(&self) -> MASK_PKT_SIZE_ERR_R { + MASK_PKT_SIZE_ERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn mask_eopt_err(&self) -> MASK_EOPT_ERR_R { + MASK_EOPT_ERR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn mask_dpi_pld_wr_err(&self) -> MASK_DPI_PLD_WR_ERR_R { + MASK_DPI_PLD_WR_ERR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn mask_gen_cmd_wr_err(&self) -> MASK_GEN_CMD_WR_ERR_R { + MASK_GEN_CMD_WR_ERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn mask_gen_pld_wr_err(&self) -> MASK_GEN_PLD_WR_ERR_R { + MASK_GEN_PLD_WR_ERR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn mask_gen_pld_send_err(&self) -> MASK_GEN_PLD_SEND_ERR_R { + MASK_GEN_PLD_SEND_ERR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn mask_gen_pld_rd_err(&self) -> MASK_GEN_PLD_RD_ERR_R { + MASK_GEN_PLD_RD_ERR_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn mask_gen_pld_recev_err(&self) -> MASK_GEN_PLD_RECEV_ERR_R { + MASK_GEN_PLD_RECEV_ERR_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn mask_dpi_buff_pld_under(&self) -> MASK_DPI_BUFF_PLD_UNDER_R { + MASK_DPI_BUFF_PLD_UNDER_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_MSK1") + .field( + "mask_to_hs_tx", + &format_args!("{}", self.mask_to_hs_tx().bit()), + ) + .field( + "mask_to_lp_rx", + &format_args!("{}", self.mask_to_lp_rx().bit()), + ) + .field( + "mask_ecc_single_err", + &format_args!("{}", self.mask_ecc_single_err().bit()), + ) + .field( + "mask_ecc_milti_err", + &format_args!("{}", self.mask_ecc_milti_err().bit()), + ) + .field( + "mask_crc_err", + &format_args!("{}", self.mask_crc_err().bit()), + ) + .field( + "mask_pkt_size_err", + &format_args!("{}", self.mask_pkt_size_err().bit()), + ) + .field( + "mask_eopt_err", + &format_args!("{}", self.mask_eopt_err().bit()), + ) + .field( + "mask_dpi_pld_wr_err", + &format_args!("{}", self.mask_dpi_pld_wr_err().bit()), + ) + .field( + "mask_gen_cmd_wr_err", + &format_args!("{}", self.mask_gen_cmd_wr_err().bit()), + ) + .field( + "mask_gen_pld_wr_err", + &format_args!("{}", self.mask_gen_pld_wr_err().bit()), + ) + .field( + "mask_gen_pld_send_err", + &format_args!("{}", self.mask_gen_pld_send_err().bit()), + ) + .field( + "mask_gen_pld_rd_err", + &format_args!("{}", self.mask_gen_pld_rd_err().bit()), + ) + .field( + "mask_gen_pld_recev_err", + &format_args!("{}", self.mask_gen_pld_recev_err().bit()), + ) + .field( + "mask_dpi_buff_pld_under", + &format_args!("{}", self.mask_dpi_buff_pld_under().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_to_hs_tx(&mut self) -> MASK_TO_HS_TX_W { + MASK_TO_HS_TX_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_to_lp_rx(&mut self) -> MASK_TO_LP_RX_W { + MASK_TO_LP_RX_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ecc_single_err(&mut self) -> MASK_ECC_SINGLE_ERR_W { + MASK_ECC_SINGLE_ERR_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_ecc_milti_err(&mut self) -> MASK_ECC_MILTI_ERR_W { + MASK_ECC_MILTI_ERR_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_crc_err(&mut self) -> MASK_CRC_ERR_W { + MASK_CRC_ERR_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_pkt_size_err(&mut self) -> MASK_PKT_SIZE_ERR_W { + MASK_PKT_SIZE_ERR_W::new(self, 5) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_eopt_err(&mut self) -> MASK_EOPT_ERR_W { + MASK_EOPT_ERR_W::new(self, 6) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_dpi_pld_wr_err(&mut self) -> MASK_DPI_PLD_WR_ERR_W { + MASK_DPI_PLD_WR_ERR_W::new(self, 7) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_gen_cmd_wr_err(&mut self) -> MASK_GEN_CMD_WR_ERR_W { + MASK_GEN_CMD_WR_ERR_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_gen_pld_wr_err(&mut self) -> MASK_GEN_PLD_WR_ERR_W { + MASK_GEN_PLD_WR_ERR_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_gen_pld_send_err(&mut self) -> MASK_GEN_PLD_SEND_ERR_W { + MASK_GEN_PLD_SEND_ERR_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_gen_pld_rd_err(&mut self) -> MASK_GEN_PLD_RD_ERR_W { + MASK_GEN_PLD_RD_ERR_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_gen_pld_recev_err(&mut self) -> MASK_GEN_PLD_RECEV_ERR_W { + MASK_GEN_PLD_RECEV_ERR_W::new(self, 12) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + #[must_use] + pub fn mask_dpi_buff_pld_under(&mut self) -> MASK_DPI_BUFF_PLD_UNDER_W { + MASK_DPI_BUFF_PLD_UNDER_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_msk1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_msk1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_MSK1_SPEC; +impl crate::RegisterSpec for INT_MSK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_msk1::R`](R) reader structure"] +impl crate::Readable for INT_MSK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_msk1::W`](W) writer structure"] +impl crate::Writable for INT_MSK1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_MSK1 to value 0"] +impl crate::Resettable for INT_MSK1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/int_st0.rs b/esp32p4/src/mipi_dsi_host/int_st0.rs new file mode 100644 index 0000000000..5635b2ba40 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/int_st0.rs @@ -0,0 +1,259 @@ +#[doc = "Register `INT_ST0` reader"] +pub type R = crate::R; +#[doc = "Field `ACK_WITH_ERR_0` reader - NA"] +pub type ACK_WITH_ERR_0_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_1` reader - NA"] +pub type ACK_WITH_ERR_1_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_2` reader - NA"] +pub type ACK_WITH_ERR_2_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_3` reader - NA"] +pub type ACK_WITH_ERR_3_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_4` reader - NA"] +pub type ACK_WITH_ERR_4_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_5` reader - NA"] +pub type ACK_WITH_ERR_5_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_6` reader - NA"] +pub type ACK_WITH_ERR_6_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_7` reader - NA"] +pub type ACK_WITH_ERR_7_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_8` reader - NA"] +pub type ACK_WITH_ERR_8_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_9` reader - NA"] +pub type ACK_WITH_ERR_9_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_10` reader - NA"] +pub type ACK_WITH_ERR_10_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_11` reader - NA"] +pub type ACK_WITH_ERR_11_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_12` reader - NA"] +pub type ACK_WITH_ERR_12_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_13` reader - NA"] +pub type ACK_WITH_ERR_13_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_14` reader - NA"] +pub type ACK_WITH_ERR_14_R = crate::BitReader; +#[doc = "Field `ACK_WITH_ERR_15` reader - NA"] +pub type ACK_WITH_ERR_15_R = crate::BitReader; +#[doc = "Field `DPHY_ERRORS_0` reader - NA"] +pub type DPHY_ERRORS_0_R = crate::BitReader; +#[doc = "Field `DPHY_ERRORS_1` reader - NA"] +pub type DPHY_ERRORS_1_R = crate::BitReader; +#[doc = "Field `DPHY_ERRORS_2` reader - NA"] +pub type DPHY_ERRORS_2_R = crate::BitReader; +#[doc = "Field `DPHY_ERRORS_3` reader - NA"] +pub type DPHY_ERRORS_3_R = crate::BitReader; +#[doc = "Field `DPHY_ERRORS_4` reader - NA"] +pub type DPHY_ERRORS_4_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn ack_with_err_0(&self) -> ACK_WITH_ERR_0_R { + ACK_WITH_ERR_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn ack_with_err_1(&self) -> ACK_WITH_ERR_1_R { + ACK_WITH_ERR_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ack_with_err_2(&self) -> ACK_WITH_ERR_2_R { + ACK_WITH_ERR_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ack_with_err_3(&self) -> ACK_WITH_ERR_3_R { + ACK_WITH_ERR_3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn ack_with_err_4(&self) -> ACK_WITH_ERR_4_R { + ACK_WITH_ERR_4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn ack_with_err_5(&self) -> ACK_WITH_ERR_5_R { + ACK_WITH_ERR_5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn ack_with_err_6(&self) -> ACK_WITH_ERR_6_R { + ACK_WITH_ERR_6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn ack_with_err_7(&self) -> ACK_WITH_ERR_7_R { + ACK_WITH_ERR_7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn ack_with_err_8(&self) -> ACK_WITH_ERR_8_R { + ACK_WITH_ERR_8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn ack_with_err_9(&self) -> ACK_WITH_ERR_9_R { + ACK_WITH_ERR_9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn ack_with_err_10(&self) -> ACK_WITH_ERR_10_R { + ACK_WITH_ERR_10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn ack_with_err_11(&self) -> ACK_WITH_ERR_11_R { + ACK_WITH_ERR_11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn ack_with_err_12(&self) -> ACK_WITH_ERR_12_R { + ACK_WITH_ERR_12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn ack_with_err_13(&self) -> ACK_WITH_ERR_13_R { + ACK_WITH_ERR_13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn ack_with_err_14(&self) -> ACK_WITH_ERR_14_R { + ACK_WITH_ERR_14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn ack_with_err_15(&self) -> ACK_WITH_ERR_15_R { + ACK_WITH_ERR_15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn dphy_errors_0(&self) -> DPHY_ERRORS_0_R { + DPHY_ERRORS_0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn dphy_errors_1(&self) -> DPHY_ERRORS_1_R { + DPHY_ERRORS_1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - NA"] + #[inline(always)] + pub fn dphy_errors_2(&self) -> DPHY_ERRORS_2_R { + DPHY_ERRORS_2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn dphy_errors_3(&self) -> DPHY_ERRORS_3_R { + DPHY_ERRORS_3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn dphy_errors_4(&self) -> DPHY_ERRORS_4_R { + DPHY_ERRORS_4_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST0") + .field( + "ack_with_err_0", + &format_args!("{}", self.ack_with_err_0().bit()), + ) + .field( + "ack_with_err_1", + &format_args!("{}", self.ack_with_err_1().bit()), + ) + .field( + "ack_with_err_2", + &format_args!("{}", self.ack_with_err_2().bit()), + ) + .field( + "ack_with_err_3", + &format_args!("{}", self.ack_with_err_3().bit()), + ) + .field( + "ack_with_err_4", + &format_args!("{}", self.ack_with_err_4().bit()), + ) + .field( + "ack_with_err_5", + &format_args!("{}", self.ack_with_err_5().bit()), + ) + .field( + "ack_with_err_6", + &format_args!("{}", self.ack_with_err_6().bit()), + ) + .field( + "ack_with_err_7", + &format_args!("{}", self.ack_with_err_7().bit()), + ) + .field( + "ack_with_err_8", + &format_args!("{}", self.ack_with_err_8().bit()), + ) + .field( + "ack_with_err_9", + &format_args!("{}", self.ack_with_err_9().bit()), + ) + .field( + "ack_with_err_10", + &format_args!("{}", self.ack_with_err_10().bit()), + ) + .field( + "ack_with_err_11", + &format_args!("{}", self.ack_with_err_11().bit()), + ) + .field( + "ack_with_err_12", + &format_args!("{}", self.ack_with_err_12().bit()), + ) + .field( + "ack_with_err_13", + &format_args!("{}", self.ack_with_err_13().bit()), + ) + .field( + "ack_with_err_14", + &format_args!("{}", self.ack_with_err_14().bit()), + ) + .field( + "ack_with_err_15", + &format_args!("{}", self.ack_with_err_15().bit()), + ) + .field( + "dphy_errors_0", + &format_args!("{}", self.dphy_errors_0().bit()), + ) + .field( + "dphy_errors_1", + &format_args!("{}", self.dphy_errors_1().bit()), + ) + .field( + "dphy_errors_2", + &format_args!("{}", self.dphy_errors_2().bit()), + ) + .field( + "dphy_errors_3", + &format_args!("{}", self.dphy_errors_3().bit()), + ) + .field( + "dphy_errors_4", + &format_args!("{}", self.dphy_errors_4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST0_SPEC; +impl crate::RegisterSpec for INT_ST0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st0::R`](R) reader structure"] +impl crate::Readable for INT_ST0_SPEC {} +#[doc = "`reset()` method sets INT_ST0 to value 0"] +impl crate::Resettable for INT_ST0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/int_st1.rs b/esp32p4/src/mipi_dsi_host/int_st1.rs new file mode 100644 index 0000000000..2cb8a67ab6 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/int_st1.rs @@ -0,0 +1,170 @@ +#[doc = "Register `INT_ST1` reader"] +pub type R = crate::R; +#[doc = "Field `TO_HS_TX` reader - NA"] +pub type TO_HS_TX_R = crate::BitReader; +#[doc = "Field `TO_LP_RX` reader - NA"] +pub type TO_LP_RX_R = crate::BitReader; +#[doc = "Field `ECC_SINGLE_ERR` reader - NA"] +pub type ECC_SINGLE_ERR_R = crate::BitReader; +#[doc = "Field `ECC_MILTI_ERR` reader - NA"] +pub type ECC_MILTI_ERR_R = crate::BitReader; +#[doc = "Field `CRC_ERR` reader - NA"] +pub type CRC_ERR_R = crate::BitReader; +#[doc = "Field `PKT_SIZE_ERR` reader - NA"] +pub type PKT_SIZE_ERR_R = crate::BitReader; +#[doc = "Field `EOPT_ERR` reader - NA"] +pub type EOPT_ERR_R = crate::BitReader; +#[doc = "Field `DPI_PLD_WR_ERR` reader - NA"] +pub type DPI_PLD_WR_ERR_R = crate::BitReader; +#[doc = "Field `GEN_CMD_WR_ERR` reader - NA"] +pub type GEN_CMD_WR_ERR_R = crate::BitReader; +#[doc = "Field `GEN_PLD_WR_ERR` reader - NA"] +pub type GEN_PLD_WR_ERR_R = crate::BitReader; +#[doc = "Field `GEN_PLD_SEND_ERR` reader - NA"] +pub type GEN_PLD_SEND_ERR_R = crate::BitReader; +#[doc = "Field `GEN_PLD_RD_ERR` reader - NA"] +pub type GEN_PLD_RD_ERR_R = crate::BitReader; +#[doc = "Field `GEN_PLD_RECEV_ERR` reader - NA"] +pub type GEN_PLD_RECEV_ERR_R = crate::BitReader; +#[doc = "Field `DPI_BUFF_PLD_UNDER` reader - NA"] +pub type DPI_BUFF_PLD_UNDER_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn to_hs_tx(&self) -> TO_HS_TX_R { + TO_HS_TX_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn to_lp_rx(&self) -> TO_LP_RX_R { + TO_LP_RX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn ecc_single_err(&self) -> ECC_SINGLE_ERR_R { + ECC_SINGLE_ERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ecc_milti_err(&self) -> ECC_MILTI_ERR_R { + ECC_MILTI_ERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn crc_err(&self) -> CRC_ERR_R { + CRC_ERR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn pkt_size_err(&self) -> PKT_SIZE_ERR_R { + PKT_SIZE_ERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn eopt_err(&self) -> EOPT_ERR_R { + EOPT_ERR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn dpi_pld_wr_err(&self) -> DPI_PLD_WR_ERR_R { + DPI_PLD_WR_ERR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn gen_cmd_wr_err(&self) -> GEN_CMD_WR_ERR_R { + GEN_CMD_WR_ERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn gen_pld_wr_err(&self) -> GEN_PLD_WR_ERR_R { + GEN_PLD_WR_ERR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn gen_pld_send_err(&self) -> GEN_PLD_SEND_ERR_R { + GEN_PLD_SEND_ERR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn gen_pld_rd_err(&self) -> GEN_PLD_RD_ERR_R { + GEN_PLD_RD_ERR_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn gen_pld_recev_err(&self) -> GEN_PLD_RECEV_ERR_R { + GEN_PLD_RECEV_ERR_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 19 - NA"] + #[inline(always)] + pub fn dpi_buff_pld_under(&self) -> DPI_BUFF_PLD_UNDER_R { + DPI_BUFF_PLD_UNDER_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST1") + .field("to_hs_tx", &format_args!("{}", self.to_hs_tx().bit())) + .field("to_lp_rx", &format_args!("{}", self.to_lp_rx().bit())) + .field( + "ecc_single_err", + &format_args!("{}", self.ecc_single_err().bit()), + ) + .field( + "ecc_milti_err", + &format_args!("{}", self.ecc_milti_err().bit()), + ) + .field("crc_err", &format_args!("{}", self.crc_err().bit())) + .field( + "pkt_size_err", + &format_args!("{}", self.pkt_size_err().bit()), + ) + .field("eopt_err", &format_args!("{}", self.eopt_err().bit())) + .field( + "dpi_pld_wr_err", + &format_args!("{}", self.dpi_pld_wr_err().bit()), + ) + .field( + "gen_cmd_wr_err", + &format_args!("{}", self.gen_cmd_wr_err().bit()), + ) + .field( + "gen_pld_wr_err", + &format_args!("{}", self.gen_pld_wr_err().bit()), + ) + .field( + "gen_pld_send_err", + &format_args!("{}", self.gen_pld_send_err().bit()), + ) + .field( + "gen_pld_rd_err", + &format_args!("{}", self.gen_pld_rd_err().bit()), + ) + .field( + "gen_pld_recev_err", + &format_args!("{}", self.gen_pld_recev_err().bit()), + ) + .field( + "dpi_buff_pld_under", + &format_args!("{}", self.dpi_buff_pld_under().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST1_SPEC; +impl crate::RegisterSpec for INT_ST1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st1::R`](R) reader structure"] +impl crate::Readable for INT_ST1_SPEC {} +#[doc = "`reset()` method sets INT_ST1 to value 0"] +impl crate::Resettable for INT_ST1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/lp_rd_to_cnt.rs b/esp32p4/src/mipi_dsi_host/lp_rd_to_cnt.rs new file mode 100644 index 0000000000..424a1a37eb --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/lp_rd_to_cnt.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_RD_TO_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `LP_RD_TO_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `LP_RD_TO_CNT` reader - NA"] +pub type LP_RD_TO_CNT_R = crate::FieldReader; +#[doc = "Field `LP_RD_TO_CNT` writer - NA"] +pub type LP_RD_TO_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn lp_rd_to_cnt(&self) -> LP_RD_TO_CNT_R { + LP_RD_TO_CNT_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_RD_TO_CNT") + .field( + "lp_rd_to_cnt", + &format_args!("{}", self.lp_rd_to_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn lp_rd_to_cnt(&mut self) -> LP_RD_TO_CNT_W { + LP_RD_TO_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_rd_to_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_rd_to_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_RD_TO_CNT_SPEC; +impl crate::RegisterSpec for LP_RD_TO_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_rd_to_cnt::R`](R) reader structure"] +impl crate::Readable for LP_RD_TO_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_rd_to_cnt::W`](W) writer structure"] +impl crate::Writable for LP_RD_TO_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_RD_TO_CNT to value 0"] +impl crate::Resettable for LP_RD_TO_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/lp_wr_to_cnt.rs b/esp32p4/src/mipi_dsi_host/lp_wr_to_cnt.rs new file mode 100644 index 0000000000..67f5fceb5f --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/lp_wr_to_cnt.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_WR_TO_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `LP_WR_TO_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `LP_WR_TO_CNT` reader - NA"] +pub type LP_WR_TO_CNT_R = crate::FieldReader; +#[doc = "Field `LP_WR_TO_CNT` writer - NA"] +pub type LP_WR_TO_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn lp_wr_to_cnt(&self) -> LP_WR_TO_CNT_R { + LP_WR_TO_CNT_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_WR_TO_CNT") + .field( + "lp_wr_to_cnt", + &format_args!("{}", self.lp_wr_to_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn lp_wr_to_cnt(&mut self) -> LP_WR_TO_CNT_W { + LP_WR_TO_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_wr_to_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_wr_to_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_WR_TO_CNT_SPEC; +impl crate::RegisterSpec for LP_WR_TO_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_wr_to_cnt::R`](R) reader structure"] +impl crate::Readable for LP_WR_TO_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_wr_to_cnt::W`](W) writer structure"] +impl crate::Writable for LP_WR_TO_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_WR_TO_CNT to value 0"] +impl crate::Resettable for LP_WR_TO_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/lpclk_ctrl.rs b/esp32p4/src/mipi_dsi_host/lpclk_ctrl.rs new file mode 100644 index 0000000000..f625636aef --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/lpclk_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `LPCLK_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `LPCLK_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_TXREQUESTCLKHS` reader - NA"] +pub type PHY_TXREQUESTCLKHS_R = crate::BitReader; +#[doc = "Field `PHY_TXREQUESTCLKHS` writer - NA"] +pub type PHY_TXREQUESTCLKHS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTO_CLKLANE_CTRL` reader - NA"] +pub type AUTO_CLKLANE_CTRL_R = crate::BitReader; +#[doc = "Field `AUTO_CLKLANE_CTRL` writer - NA"] +pub type AUTO_CLKLANE_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn phy_txrequestclkhs(&self) -> PHY_TXREQUESTCLKHS_R { + PHY_TXREQUESTCLKHS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn auto_clklane_ctrl(&self) -> AUTO_CLKLANE_CTRL_R { + AUTO_CLKLANE_CTRL_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LPCLK_CTRL") + .field( + "phy_txrequestclkhs", + &format_args!("{}", self.phy_txrequestclkhs().bit()), + ) + .field( + "auto_clklane_ctrl", + &format_args!("{}", self.auto_clklane_ctrl().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_txrequestclkhs(&mut self) -> PHY_TXREQUESTCLKHS_W { + PHY_TXREQUESTCLKHS_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn auto_clklane_ctrl(&mut self) -> AUTO_CLKLANE_CTRL_W { + AUTO_CLKLANE_CTRL_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lpclk_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lpclk_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LPCLK_CTRL_SPEC; +impl crate::RegisterSpec for LPCLK_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lpclk_ctrl::R`](R) reader structure"] +impl crate::Readable for LPCLK_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lpclk_ctrl::W`](W) writer structure"] +impl crate::Writable for LPCLK_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LPCLK_CTRL to value 0"] +impl crate::Resettable for LPCLK_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/mode_cfg.rs b/esp32p4/src/mipi_dsi_host/mode_cfg.rs new file mode 100644 index 0000000000..1dee67ec33 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/mode_cfg.rs @@ -0,0 +1,66 @@ +#[doc = "Register `MODE_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `MODE_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `CMD_VIDEO_MODE` reader - NA"] +pub type CMD_VIDEO_MODE_R = crate::BitReader; +#[doc = "Field `CMD_VIDEO_MODE` writer - NA"] +pub type CMD_VIDEO_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn cmd_video_mode(&self) -> CMD_VIDEO_MODE_R { + CMD_VIDEO_MODE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MODE_CFG") + .field( + "cmd_video_mode", + &format_args!("{}", self.cmd_video_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn cmd_video_mode(&mut self) -> CMD_VIDEO_MODE_W { + CMD_VIDEO_MODE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MODE_CFG_SPEC; +impl crate::RegisterSpec for MODE_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mode_cfg::R`](R) reader structure"] +impl crate::Readable for MODE_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mode_cfg::W`](W) writer structure"] +impl crate::Writable for MODE_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MODE_CFG to value 0x01"] +impl crate::Resettable for MODE_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/mipi_dsi_host/pckhdl_cfg.rs b/esp32p4/src/mipi_dsi_host/pckhdl_cfg.rs new file mode 100644 index 0000000000..79bdc9f003 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/pckhdl_cfg.rs @@ -0,0 +1,146 @@ +#[doc = "Register `PCKHDL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `PCKHDL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `EOTP_TX_EN` reader - NA"] +pub type EOTP_TX_EN_R = crate::BitReader; +#[doc = "Field `EOTP_TX_EN` writer - NA"] +pub type EOTP_TX_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EOTP_RX_EN` reader - NA"] +pub type EOTP_RX_EN_R = crate::BitReader; +#[doc = "Field `EOTP_RX_EN` writer - NA"] +pub type EOTP_RX_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BTA_EN` reader - NA"] +pub type BTA_EN_R = crate::BitReader; +#[doc = "Field `BTA_EN` writer - NA"] +pub type BTA_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ECC_RX_EN` reader - NA"] +pub type ECC_RX_EN_R = crate::BitReader; +#[doc = "Field `ECC_RX_EN` writer - NA"] +pub type ECC_RX_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRC_RX_EN` reader - NA"] +pub type CRC_RX_EN_R = crate::BitReader; +#[doc = "Field `CRC_RX_EN` writer - NA"] +pub type CRC_RX_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EOTP_TX_LP_EN` reader - NA"] +pub type EOTP_TX_LP_EN_R = crate::BitReader; +#[doc = "Field `EOTP_TX_LP_EN` writer - NA"] +pub type EOTP_TX_LP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn eotp_tx_en(&self) -> EOTP_TX_EN_R { + EOTP_TX_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn eotp_rx_en(&self) -> EOTP_RX_EN_R { + EOTP_RX_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn bta_en(&self) -> BTA_EN_R { + BTA_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn ecc_rx_en(&self) -> ECC_RX_EN_R { + ECC_RX_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn crc_rx_en(&self) -> CRC_RX_EN_R { + CRC_RX_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn eotp_tx_lp_en(&self) -> EOTP_TX_LP_EN_R { + EOTP_TX_LP_EN_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PCKHDL_CFG") + .field("eotp_tx_en", &format_args!("{}", self.eotp_tx_en().bit())) + .field("eotp_rx_en", &format_args!("{}", self.eotp_rx_en().bit())) + .field("bta_en", &format_args!("{}", self.bta_en().bit())) + .field("ecc_rx_en", &format_args!("{}", self.ecc_rx_en().bit())) + .field("crc_rx_en", &format_args!("{}", self.crc_rx_en().bit())) + .field( + "eotp_tx_lp_en", + &format_args!("{}", self.eotp_tx_lp_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn eotp_tx_en(&mut self) -> EOTP_TX_EN_W { + EOTP_TX_EN_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn eotp_rx_en(&mut self) -> EOTP_RX_EN_W { + EOTP_RX_EN_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn bta_en(&mut self) -> BTA_EN_W { + BTA_EN_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn ecc_rx_en(&mut self) -> ECC_RX_EN_W { + ECC_RX_EN_W::new(self, 3) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn crc_rx_en(&mut self) -> CRC_RX_EN_W { + CRC_RX_EN_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn eotp_tx_lp_en(&mut self) -> EOTP_TX_LP_EN_W { + EOTP_TX_LP_EN_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pckhdl_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pckhdl_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PCKHDL_CFG_SPEC; +impl crate::RegisterSpec for PCKHDL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pckhdl_cfg::R`](R) reader structure"] +impl crate::Readable for PCKHDL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pckhdl_cfg::W`](W) writer structure"] +impl crate::Writable for PCKHDL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PCKHDL_CFG to value 0"] +impl crate::Resettable for PCKHDL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/phy_cal.rs b/esp32p4/src/mipi_dsi_host/phy_cal.rs new file mode 100644 index 0000000000..e72fdf568b --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/phy_cal.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PHY_CAL` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_CAL` writer"] +pub type W = crate::W; +#[doc = "Field `TXSKEWCALHS` reader - NA"] +pub type TXSKEWCALHS_R = crate::BitReader; +#[doc = "Field `TXSKEWCALHS` writer - NA"] +pub type TXSKEWCALHS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn txskewcalhs(&self) -> TXSKEWCALHS_R { + TXSKEWCALHS_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_CAL") + .field("txskewcalhs", &format_args!("{}", self.txskewcalhs().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn txskewcalhs(&mut self) -> TXSKEWCALHS_W { + TXSKEWCALHS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_cal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_cal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_CAL_SPEC; +impl crate::RegisterSpec for PHY_CAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_cal::R`](R) reader structure"] +impl crate::Readable for PHY_CAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_cal::W`](W) writer structure"] +impl crate::Writable for PHY_CAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_CAL to value 0"] +impl crate::Resettable for PHY_CAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/phy_if_cfg.rs b/esp32p4/src/mipi_dsi_host/phy_if_cfg.rs new file mode 100644 index 0000000000..b40adf2fe0 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/phy_if_cfg.rs @@ -0,0 +1,82 @@ +#[doc = "Register `PHY_IF_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_IF_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `N_LANES` reader - NA"] +pub type N_LANES_R = crate::FieldReader; +#[doc = "Field `N_LANES` writer - NA"] +pub type N_LANES_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PHY_STOP_WAIT_TIME` reader - NA"] +pub type PHY_STOP_WAIT_TIME_R = crate::FieldReader; +#[doc = "Field `PHY_STOP_WAIT_TIME` writer - NA"] +pub type PHY_STOP_WAIT_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn n_lanes(&self) -> N_LANES_R { + N_LANES_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + pub fn phy_stop_wait_time(&self) -> PHY_STOP_WAIT_TIME_R { + PHY_STOP_WAIT_TIME_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_IF_CFG") + .field("n_lanes", &format_args!("{}", self.n_lanes().bits())) + .field( + "phy_stop_wait_time", + &format_args!("{}", self.phy_stop_wait_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + #[must_use] + pub fn n_lanes(&mut self) -> N_LANES_W { + N_LANES_W::new(self, 0) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_stop_wait_time(&mut self) -> PHY_STOP_WAIT_TIME_W { + PHY_STOP_WAIT_TIME_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_if_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_if_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_IF_CFG_SPEC; +impl crate::RegisterSpec for PHY_IF_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_if_cfg::R`](R) reader structure"] +impl crate::Readable for PHY_IF_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_if_cfg::W`](W) writer structure"] +impl crate::Writable for PHY_IF_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_IF_CFG to value 0x01"] +impl crate::Resettable for PHY_IF_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/mipi_dsi_host/phy_rstz.rs b/esp32p4/src/mipi_dsi_host/phy_rstz.rs new file mode 100644 index 0000000000..62a0ce3474 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/phy_rstz.rs @@ -0,0 +1,120 @@ +#[doc = "Register `PHY_RSTZ` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_RSTZ` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_SHUTDOWNZ` reader - NA"] +pub type PHY_SHUTDOWNZ_R = crate::BitReader; +#[doc = "Field `PHY_SHUTDOWNZ` writer - NA"] +pub type PHY_SHUTDOWNZ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_RSTZ` reader - NA"] +pub type PHY_RSTZ_R = crate::BitReader; +#[doc = "Field `PHY_RSTZ` writer - NA"] +pub type PHY_RSTZ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_ENABLECLK` reader - NA"] +pub type PHY_ENABLECLK_R = crate::BitReader; +#[doc = "Field `PHY_ENABLECLK` writer - NA"] +pub type PHY_ENABLECLK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_FORCEPLL` reader - NA"] +pub type PHY_FORCEPLL_R = crate::BitReader; +#[doc = "Field `PHY_FORCEPLL` writer - NA"] +pub type PHY_FORCEPLL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn phy_shutdownz(&self) -> PHY_SHUTDOWNZ_R { + PHY_SHUTDOWNZ_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn phy_rstz(&self) -> PHY_RSTZ_R { + PHY_RSTZ_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn phy_enableclk(&self) -> PHY_ENABLECLK_R { + PHY_ENABLECLK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn phy_forcepll(&self) -> PHY_FORCEPLL_R { + PHY_FORCEPLL_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_RSTZ") + .field( + "phy_shutdownz", + &format_args!("{}", self.phy_shutdownz().bit()), + ) + .field("phy_rstz", &format_args!("{}", self.phy_rstz().bit())) + .field( + "phy_enableclk", + &format_args!("{}", self.phy_enableclk().bit()), + ) + .field( + "phy_forcepll", + &format_args!("{}", self.phy_forcepll().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_shutdownz(&mut self) -> PHY_SHUTDOWNZ_W { + PHY_SHUTDOWNZ_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_rstz(&mut self) -> PHY_RSTZ_W { + PHY_RSTZ_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_enableclk(&mut self) -> PHY_ENABLECLK_W { + PHY_ENABLECLK_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_forcepll(&mut self) -> PHY_FORCEPLL_W { + PHY_FORCEPLL_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_rstz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_rstz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_RSTZ_SPEC; +impl crate::RegisterSpec for PHY_RSTZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_rstz::R`](R) reader structure"] +impl crate::Readable for PHY_RSTZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_rstz::W`](W) writer structure"] +impl crate::Writable for PHY_RSTZ_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_RSTZ to value 0"] +impl crate::Resettable for PHY_RSTZ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/phy_status.rs b/esp32p4/src/mipi_dsi_host/phy_status.rs new file mode 100644 index 0000000000..213862b877 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/phy_status.rs @@ -0,0 +1,124 @@ +#[doc = "Register `PHY_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `PHY_LOCK` reader - NA"] +pub type PHY_LOCK_R = crate::BitReader; +#[doc = "Field `PHY_DIRECTION` reader - NA"] +pub type PHY_DIRECTION_R = crate::BitReader; +#[doc = "Field `PHY_STOPSTATECLKLANE` reader - NA"] +pub type PHY_STOPSTATECLKLANE_R = crate::BitReader; +#[doc = "Field `PHY_ULPSACTIVENOTCLK` reader - NA"] +pub type PHY_ULPSACTIVENOTCLK_R = crate::BitReader; +#[doc = "Field `PHY_STOPSTATE0LANE` reader - NA"] +pub type PHY_STOPSTATE0LANE_R = crate::BitReader; +#[doc = "Field `PHY_ULPSACTIVENOT0LANE` reader - NA"] +pub type PHY_ULPSACTIVENOT0LANE_R = crate::BitReader; +#[doc = "Field `PHY_RXULPSESC0LANE` reader - NA"] +pub type PHY_RXULPSESC0LANE_R = crate::BitReader; +#[doc = "Field `PHY_STOPSTATE1LANE` reader - NA"] +pub type PHY_STOPSTATE1LANE_R = crate::BitReader; +#[doc = "Field `PHY_ULPSACTIVENOT1LANE` reader - NA"] +pub type PHY_ULPSACTIVENOT1LANE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn phy_lock(&self) -> PHY_LOCK_R { + PHY_LOCK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn phy_direction(&self) -> PHY_DIRECTION_R { + PHY_DIRECTION_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn phy_stopstateclklane(&self) -> PHY_STOPSTATECLKLANE_R { + PHY_STOPSTATECLKLANE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn phy_ulpsactivenotclk(&self) -> PHY_ULPSACTIVENOTCLK_R { + PHY_ULPSACTIVENOTCLK_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn phy_stopstate0lane(&self) -> PHY_STOPSTATE0LANE_R { + PHY_STOPSTATE0LANE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn phy_ulpsactivenot0lane(&self) -> PHY_ULPSACTIVENOT0LANE_R { + PHY_ULPSACTIVENOT0LANE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn phy_rxulpsesc0lane(&self) -> PHY_RXULPSESC0LANE_R { + PHY_RXULPSESC0LANE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn phy_stopstate1lane(&self) -> PHY_STOPSTATE1LANE_R { + PHY_STOPSTATE1LANE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn phy_ulpsactivenot1lane(&self) -> PHY_ULPSACTIVENOT1LANE_R { + PHY_ULPSACTIVENOT1LANE_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_STATUS") + .field("phy_lock", &format_args!("{}", self.phy_lock().bit())) + .field( + "phy_direction", + &format_args!("{}", self.phy_direction().bit()), + ) + .field( + "phy_stopstateclklane", + &format_args!("{}", self.phy_stopstateclklane().bit()), + ) + .field( + "phy_ulpsactivenotclk", + &format_args!("{}", self.phy_ulpsactivenotclk().bit()), + ) + .field( + "phy_stopstate0lane", + &format_args!("{}", self.phy_stopstate0lane().bit()), + ) + .field( + "phy_ulpsactivenot0lane", + &format_args!("{}", self.phy_ulpsactivenot0lane().bit()), + ) + .field( + "phy_rxulpsesc0lane", + &format_args!("{}", self.phy_rxulpsesc0lane().bit()), + ) + .field( + "phy_stopstate1lane", + &format_args!("{}", self.phy_stopstate1lane().bit()), + ) + .field( + "phy_ulpsactivenot1lane", + &format_args!("{}", self.phy_ulpsactivenot1lane().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_STATUS_SPEC; +impl crate::RegisterSpec for PHY_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_status::R`](R) reader structure"] +impl crate::Readable for PHY_STATUS_SPEC {} +#[doc = "`reset()` method sets PHY_STATUS to value 0x0140"] +impl crate::Resettable for PHY_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x0140; +} diff --git a/esp32p4/src/mipi_dsi_host/phy_tmr_cfg.rs b/esp32p4/src/mipi_dsi_host/phy_tmr_cfg.rs new file mode 100644 index 0000000000..e2a9c8fe4f --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/phy_tmr_cfg.rs @@ -0,0 +1,85 @@ +#[doc = "Register `PHY_TMR_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_TMR_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_LP2HS_TIME` reader - NA"] +pub type PHY_LP2HS_TIME_R = crate::FieldReader; +#[doc = "Field `PHY_LP2HS_TIME` writer - NA"] +pub type PHY_LP2HS_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `PHY_HS2LP_TIME` reader - NA"] +pub type PHY_HS2LP_TIME_R = crate::FieldReader; +#[doc = "Field `PHY_HS2LP_TIME` writer - NA"] +pub type PHY_HS2LP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + pub fn phy_lp2hs_time(&self) -> PHY_LP2HS_TIME_R { + PHY_LP2HS_TIME_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:25 - NA"] + #[inline(always)] + pub fn phy_hs2lp_time(&self) -> PHY_HS2LP_TIME_R { + PHY_HS2LP_TIME_R::new(((self.bits >> 16) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_TMR_CFG") + .field( + "phy_lp2hs_time", + &format_args!("{}", self.phy_lp2hs_time().bits()), + ) + .field( + "phy_hs2lp_time", + &format_args!("{}", self.phy_hs2lp_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_lp2hs_time(&mut self) -> PHY_LP2HS_TIME_W { + PHY_LP2HS_TIME_W::new(self, 0) + } + #[doc = "Bits 16:25 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_hs2lp_time(&mut self) -> PHY_HS2LP_TIME_W { + PHY_HS2LP_TIME_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tmr_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tmr_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_TMR_CFG_SPEC; +impl crate::RegisterSpec for PHY_TMR_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_tmr_cfg::R`](R) reader structure"] +impl crate::Readable for PHY_TMR_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_tmr_cfg::W`](W) writer structure"] +impl crate::Writable for PHY_TMR_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_TMR_CFG to value 0"] +impl crate::Resettable for PHY_TMR_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/phy_tmr_lpclk_cfg.rs b/esp32p4/src/mipi_dsi_host/phy_tmr_lpclk_cfg.rs new file mode 100644 index 0000000000..5a7940d8de --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/phy_tmr_lpclk_cfg.rs @@ -0,0 +1,85 @@ +#[doc = "Register `PHY_TMR_LPCLK_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_TMR_LPCLK_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_CLKLP2HS_TIME` reader - NA"] +pub type PHY_CLKLP2HS_TIME_R = crate::FieldReader; +#[doc = "Field `PHY_CLKLP2HS_TIME` writer - NA"] +pub type PHY_CLKLP2HS_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `PHY_CLKHS2LP_TIME` reader - NA"] +pub type PHY_CLKHS2LP_TIME_R = crate::FieldReader; +#[doc = "Field `PHY_CLKHS2LP_TIME` writer - NA"] +pub type PHY_CLKHS2LP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + pub fn phy_clklp2hs_time(&self) -> PHY_CLKLP2HS_TIME_R { + PHY_CLKLP2HS_TIME_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 16:25 - NA"] + #[inline(always)] + pub fn phy_clkhs2lp_time(&self) -> PHY_CLKHS2LP_TIME_R { + PHY_CLKHS2LP_TIME_R::new(((self.bits >> 16) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_TMR_LPCLK_CFG") + .field( + "phy_clklp2hs_time", + &format_args!("{}", self.phy_clklp2hs_time().bits()), + ) + .field( + "phy_clkhs2lp_time", + &format_args!("{}", self.phy_clkhs2lp_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_clklp2hs_time(&mut self) -> PHY_CLKLP2HS_TIME_W { + PHY_CLKLP2HS_TIME_W::new(self, 0) + } + #[doc = "Bits 16:25 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_clkhs2lp_time(&mut self) -> PHY_CLKHS2LP_TIME_W { + PHY_CLKHS2LP_TIME_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tmr_lpclk_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tmr_lpclk_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_TMR_LPCLK_CFG_SPEC; +impl crate::RegisterSpec for PHY_TMR_LPCLK_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_tmr_lpclk_cfg::R`](R) reader structure"] +impl crate::Readable for PHY_TMR_LPCLK_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_tmr_lpclk_cfg::W`](W) writer structure"] +impl crate::Writable for PHY_TMR_LPCLK_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_TMR_LPCLK_CFG to value 0"] +impl crate::Resettable for PHY_TMR_LPCLK_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/phy_tmr_rd_cfg.rs b/esp32p4/src/mipi_dsi_host/phy_tmr_rd_cfg.rs new file mode 100644 index 0000000000..adf4a16540 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/phy_tmr_rd_cfg.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PHY_TMR_RD_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_TMR_RD_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `MAX_RD_TIME` reader - NA"] +pub type MAX_RD_TIME_R = crate::FieldReader; +#[doc = "Field `MAX_RD_TIME` writer - NA"] +pub type MAX_RD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + pub fn max_rd_time(&self) -> MAX_RD_TIME_R { + MAX_RD_TIME_R::new((self.bits & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_TMR_RD_CFG") + .field( + "max_rd_time", + &format_args!("{}", self.max_rd_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + #[must_use] + pub fn max_rd_time(&mut self) -> MAX_RD_TIME_W { + MAX_RD_TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tmr_rd_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tmr_rd_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_TMR_RD_CFG_SPEC; +impl crate::RegisterSpec for PHY_TMR_RD_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_tmr_rd_cfg::R`](R) reader structure"] +impl crate::Readable for PHY_TMR_RD_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_tmr_rd_cfg::W`](W) writer structure"] +impl crate::Writable for PHY_TMR_RD_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_TMR_RD_CFG to value 0"] +impl crate::Resettable for PHY_TMR_RD_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/phy_tst_ctrl0.rs b/esp32p4/src/mipi_dsi_host/phy_tst_ctrl0.rs new file mode 100644 index 0000000000..4323b49c8a --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/phy_tst_ctrl0.rs @@ -0,0 +1,79 @@ +#[doc = "Register `PHY_TST_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_TST_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_TESTCLR` reader - NA"] +pub type PHY_TESTCLR_R = crate::BitReader; +#[doc = "Field `PHY_TESTCLR` writer - NA"] +pub type PHY_TESTCLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_TESTCLK` reader - NA"] +pub type PHY_TESTCLK_R = crate::BitReader; +#[doc = "Field `PHY_TESTCLK` writer - NA"] +pub type PHY_TESTCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn phy_testclr(&self) -> PHY_TESTCLR_R { + PHY_TESTCLR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn phy_testclk(&self) -> PHY_TESTCLK_R { + PHY_TESTCLK_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_TST_CTRL0") + .field("phy_testclr", &format_args!("{}", self.phy_testclr().bit())) + .field("phy_testclk", &format_args!("{}", self.phy_testclk().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_testclr(&mut self) -> PHY_TESTCLR_W { + PHY_TESTCLR_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_testclk(&mut self) -> PHY_TESTCLK_W { + PHY_TESTCLK_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tst_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tst_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_TST_CTRL0_SPEC; +impl crate::RegisterSpec for PHY_TST_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_tst_ctrl0::R`](R) reader structure"] +impl crate::Readable for PHY_TST_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_tst_ctrl0::W`](W) writer structure"] +impl crate::Writable for PHY_TST_CTRL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_TST_CTRL0 to value 0x01"] +impl crate::Resettable for PHY_TST_CTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/mipi_dsi_host/phy_tst_ctrl1.rs b/esp32p4/src/mipi_dsi_host/phy_tst_ctrl1.rs new file mode 100644 index 0000000000..0ce370a9eb --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/phy_tst_ctrl1.rs @@ -0,0 +1,93 @@ +#[doc = "Register `PHY_TST_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_TST_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_TESTDIN` reader - NA"] +pub type PHY_TESTDIN_R = crate::FieldReader; +#[doc = "Field `PHY_TESTDIN` writer - NA"] +pub type PHY_TESTDIN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PHT_TESTDOUT` reader - NA"] +pub type PHT_TESTDOUT_R = crate::FieldReader; +#[doc = "Field `PHY_TESTEN` reader - NA"] +pub type PHY_TESTEN_R = crate::BitReader; +#[doc = "Field `PHY_TESTEN` writer - NA"] +pub type PHY_TESTEN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + pub fn phy_testdin(&self) -> PHY_TESTDIN_R { + PHY_TESTDIN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - NA"] + #[inline(always)] + pub fn pht_testdout(&self) -> PHT_TESTDOUT_R { + PHT_TESTDOUT_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn phy_testen(&self) -> PHY_TESTEN_R { + PHY_TESTEN_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_TST_CTRL1") + .field( + "phy_testdin", + &format_args!("{}", self.phy_testdin().bits()), + ) + .field( + "pht_testdout", + &format_args!("{}", self.pht_testdout().bits()), + ) + .field("phy_testen", &format_args!("{}", self.phy_testen().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_testdin(&mut self) -> PHY_TESTDIN_W { + PHY_TESTDIN_W::new(self, 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_testen(&mut self) -> PHY_TESTEN_W { + PHY_TESTEN_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tst_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tst_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_TST_CTRL1_SPEC; +impl crate::RegisterSpec for PHY_TST_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_tst_ctrl1::R`](R) reader structure"] +impl crate::Readable for PHY_TST_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_tst_ctrl1::W`](W) writer structure"] +impl crate::Writable for PHY_TST_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_TST_CTRL1 to value 0"] +impl crate::Resettable for PHY_TST_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/phy_tx_triggers.rs b/esp32p4/src/mipi_dsi_host/phy_tx_triggers.rs new file mode 100644 index 0000000000..71308879a5 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/phy_tx_triggers.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PHY_TX_TRIGGERS` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_TX_TRIGGERS` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_TX_TRIGGERS` reader - NA"] +pub type PHY_TX_TRIGGERS_R = crate::FieldReader; +#[doc = "Field `PHY_TX_TRIGGERS` writer - NA"] +pub type PHY_TX_TRIGGERS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + pub fn phy_tx_triggers(&self) -> PHY_TX_TRIGGERS_R { + PHY_TX_TRIGGERS_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_TX_TRIGGERS") + .field( + "phy_tx_triggers", + &format_args!("{}", self.phy_tx_triggers().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_tx_triggers(&mut self) -> PHY_TX_TRIGGERS_W { + PHY_TX_TRIGGERS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_tx_triggers::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_tx_triggers::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_TX_TRIGGERS_SPEC; +impl crate::RegisterSpec for PHY_TX_TRIGGERS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_tx_triggers::R`](R) reader structure"] +impl crate::Readable for PHY_TX_TRIGGERS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_tx_triggers::W`](W) writer structure"] +impl crate::Writable for PHY_TX_TRIGGERS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_TX_TRIGGERS to value 0"] +impl crate::Resettable for PHY_TX_TRIGGERS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/phy_ulps_ctrl.rs b/esp32p4/src/mipi_dsi_host/phy_ulps_ctrl.rs new file mode 100644 index 0000000000..d18e58c4d5 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/phy_ulps_ctrl.rs @@ -0,0 +1,123 @@ +#[doc = "Register `PHY_ULPS_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `PHY_ULPS_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `PHY_TXREQULPSCLK` reader - NA"] +pub type PHY_TXREQULPSCLK_R = crate::BitReader; +#[doc = "Field `PHY_TXREQULPSCLK` writer - NA"] +pub type PHY_TXREQULPSCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_TXEXITULPSCLK` reader - NA"] +pub type PHY_TXEXITULPSCLK_R = crate::BitReader; +#[doc = "Field `PHY_TXEXITULPSCLK` writer - NA"] +pub type PHY_TXEXITULPSCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_TXREQULPSLAN` reader - NA"] +pub type PHY_TXREQULPSLAN_R = crate::BitReader; +#[doc = "Field `PHY_TXREQULPSLAN` writer - NA"] +pub type PHY_TXREQULPSLAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_TXEXITULPSLAN` reader - NA"] +pub type PHY_TXEXITULPSLAN_R = crate::BitReader; +#[doc = "Field `PHY_TXEXITULPSLAN` writer - NA"] +pub type PHY_TXEXITULPSLAN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn phy_txrequlpsclk(&self) -> PHY_TXREQULPSCLK_R { + PHY_TXREQULPSCLK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn phy_txexitulpsclk(&self) -> PHY_TXEXITULPSCLK_R { + PHY_TXEXITULPSCLK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn phy_txrequlpslan(&self) -> PHY_TXREQULPSLAN_R { + PHY_TXREQULPSLAN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn phy_txexitulpslan(&self) -> PHY_TXEXITULPSLAN_R { + PHY_TXEXITULPSLAN_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PHY_ULPS_CTRL") + .field( + "phy_txrequlpsclk", + &format_args!("{}", self.phy_txrequlpsclk().bit()), + ) + .field( + "phy_txexitulpsclk", + &format_args!("{}", self.phy_txexitulpsclk().bit()), + ) + .field( + "phy_txrequlpslan", + &format_args!("{}", self.phy_txrequlpslan().bit()), + ) + .field( + "phy_txexitulpslan", + &format_args!("{}", self.phy_txexitulpslan().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_txrequlpsclk(&mut self) -> PHY_TXREQULPSCLK_W { + PHY_TXREQULPSCLK_W::new(self, 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_txexitulpsclk(&mut self) -> PHY_TXEXITULPSCLK_W { + PHY_TXEXITULPSCLK_W::new(self, 1) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_txrequlpslan(&mut self) -> PHY_TXREQULPSLAN_W { + PHY_TXREQULPSLAN_W::new(self, 2) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + #[must_use] + pub fn phy_txexitulpslan(&mut self) -> PHY_TXEXITULPSLAN_W { + PHY_TXEXITULPSLAN_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_ulps_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_ulps_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHY_ULPS_CTRL_SPEC; +impl crate::RegisterSpec for PHY_ULPS_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phy_ulps_ctrl::R`](R) reader structure"] +impl crate::Readable for PHY_ULPS_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phy_ulps_ctrl::W`](W) writer structure"] +impl crate::Writable for PHY_ULPS_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PHY_ULPS_CTRL to value 0"] +impl crate::Resettable for PHY_ULPS_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/pwr_up.rs b/esp32p4/src/mipi_dsi_host/pwr_up.rs new file mode 100644 index 0000000000..1bc2fe6aa5 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/pwr_up.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PWR_UP` reader"] +pub type R = crate::R; +#[doc = "Register `PWR_UP` writer"] +pub type W = crate::W; +#[doc = "Field `SHUTDOWNZ` reader - NA"] +pub type SHUTDOWNZ_R = crate::BitReader; +#[doc = "Field `SHUTDOWNZ` writer - NA"] +pub type SHUTDOWNZ_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn shutdownz(&self) -> SHUTDOWNZ_R { + SHUTDOWNZ_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWR_UP") + .field("shutdownz", &format_args!("{}", self.shutdownz().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn shutdownz(&mut self) -> SHUTDOWNZ_W { + SHUTDOWNZ_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwr_up::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwr_up::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWR_UP_SPEC; +impl crate::RegisterSpec for PWR_UP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwr_up::R`](R) reader structure"] +impl crate::Readable for PWR_UP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwr_up::W`](W) writer structure"] +impl crate::Writable for PWR_UP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PWR_UP to value 0"] +impl crate::Resettable for PWR_UP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/sdf_3d.rs b/esp32p4/src/mipi_dsi_host/sdf_3d.rs new file mode 100644 index 0000000000..ab472d94f5 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/sdf_3d.rs @@ -0,0 +1,130 @@ +#[doc = "Register `SDF_3D` reader"] +pub type R = crate::R; +#[doc = "Register `SDF_3D` writer"] +pub type W = crate::W; +#[doc = "Field `MODE_3D` reader - NA"] +pub type MODE_3D_R = crate::FieldReader; +#[doc = "Field `MODE_3D` writer - NA"] +pub type MODE_3D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `FORMAT_3D` reader - NA"] +pub type FORMAT_3D_R = crate::FieldReader; +#[doc = "Field `FORMAT_3D` writer - NA"] +pub type FORMAT_3D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SECOND_VSYNC` reader - NA"] +pub type SECOND_VSYNC_R = crate::BitReader; +#[doc = "Field `SECOND_VSYNC` writer - NA"] +pub type SECOND_VSYNC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RIGHT_FIRST` reader - NA"] +pub type RIGHT_FIRST_R = crate::BitReader; +#[doc = "Field `RIGHT_FIRST` writer - NA"] +pub type RIGHT_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_3D_CFG` reader - NA"] +pub type SEND_3D_CFG_R = crate::BitReader; +#[doc = "Field `SEND_3D_CFG` writer - NA"] +pub type SEND_3D_CFG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn mode_3d(&self) -> MODE_3D_R { + MODE_3D_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - NA"] + #[inline(always)] + pub fn format_3d(&self) -> FORMAT_3D_R { + FORMAT_3D_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn second_vsync(&self) -> SECOND_VSYNC_R { + SECOND_VSYNC_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn right_first(&self) -> RIGHT_FIRST_R { + RIGHT_FIRST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn send_3d_cfg(&self) -> SEND_3D_CFG_R { + SEND_3D_CFG_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDF_3D") + .field("mode_3d", &format_args!("{}", self.mode_3d().bits())) + .field("format_3d", &format_args!("{}", self.format_3d().bits())) + .field( + "second_vsync", + &format_args!("{}", self.second_vsync().bit()), + ) + .field("right_first", &format_args!("{}", self.right_first().bit())) + .field("send_3d_cfg", &format_args!("{}", self.send_3d_cfg().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + #[must_use] + pub fn mode_3d(&mut self) -> MODE_3D_W { + MODE_3D_W::new(self, 0) + } + #[doc = "Bits 2:3 - NA"] + #[inline(always)] + #[must_use] + pub fn format_3d(&mut self) -> FORMAT_3D_W { + FORMAT_3D_W::new(self, 2) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + #[must_use] + pub fn second_vsync(&mut self) -> SECOND_VSYNC_W { + SECOND_VSYNC_W::new(self, 4) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + #[must_use] + pub fn right_first(&mut self) -> RIGHT_FIRST_W { + RIGHT_FIRST_W::new(self, 5) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn send_3d_cfg(&mut self) -> SEND_3D_CFG_W { + SEND_3D_CFG_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdf_3d::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdf_3d::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDF_3D_SPEC; +impl crate::RegisterSpec for SDF_3D_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sdf_3d::R`](R) reader structure"] +impl crate::Readable for SDF_3D_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sdf_3d::W`](W) writer structure"] +impl crate::Writable for SDF_3D_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDF_3D to value 0"] +impl crate::Resettable for SDF_3D_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/sdf_3d_act.rs b/esp32p4/src/mipi_dsi_host/sdf_3d_act.rs new file mode 100644 index 0000000000..70cbc991a0 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/sdf_3d_act.rs @@ -0,0 +1,83 @@ +#[doc = "Register `SDF_3D_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `MODE_3D_ACT` reader - NA"] +pub type MODE_3D_ACT_R = crate::FieldReader; +#[doc = "Field `FORMAT_3D_ACT` reader - NA"] +pub type FORMAT_3D_ACT_R = crate::FieldReader; +#[doc = "Field `SECOND_VSYNC_ACT` reader - NA"] +pub type SECOND_VSYNC_ACT_R = crate::BitReader; +#[doc = "Field `RIGHT_FIRST_ACT` reader - NA"] +pub type RIGHT_FIRST_ACT_R = crate::BitReader; +#[doc = "Field `SEND_3D_CFG_ACT` reader - NA"] +pub type SEND_3D_CFG_ACT_R = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn mode_3d_act(&self) -> MODE_3D_ACT_R { + MODE_3D_ACT_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - NA"] + #[inline(always)] + pub fn format_3d_act(&self) -> FORMAT_3D_ACT_R { + FORMAT_3D_ACT_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn second_vsync_act(&self) -> SECOND_VSYNC_ACT_R { + SECOND_VSYNC_ACT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn right_first_act(&self) -> RIGHT_FIRST_ACT_R { + RIGHT_FIRST_ACT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn send_3d_cfg_act(&self) -> SEND_3D_CFG_ACT_R { + SEND_3D_CFG_ACT_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDF_3D_ACT") + .field( + "mode_3d_act", + &format_args!("{}", self.mode_3d_act().bits()), + ) + .field( + "format_3d_act", + &format_args!("{}", self.format_3d_act().bits()), + ) + .field( + "second_vsync_act", + &format_args!("{}", self.second_vsync_act().bit()), + ) + .field( + "right_first_act", + &format_args!("{}", self.right_first_act().bit()), + ) + .field( + "send_3d_cfg_act", + &format_args!("{}", self.send_3d_cfg_act().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdf_3d_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDF_3D_ACT_SPEC; +impl crate::RegisterSpec for SDF_3D_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sdf_3d_act::R`](R) reader structure"] +impl crate::Readable for SDF_3D_ACT_SPEC {} +#[doc = "`reset()` method sets SDF_3D_ACT to value 0"] +impl crate::Resettable for SDF_3D_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/to_cnt_cfg.rs b/esp32p4/src/mipi_dsi_host/to_cnt_cfg.rs new file mode 100644 index 0000000000..464c856713 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/to_cnt_cfg.rs @@ -0,0 +1,85 @@ +#[doc = "Register `TO_CNT_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `TO_CNT_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `LPRX_TO_CNT` reader - NA"] +pub type LPRX_TO_CNT_R = crate::FieldReader; +#[doc = "Field `LPRX_TO_CNT` writer - NA"] +pub type LPRX_TO_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `HSTX_TO_CNT` reader - NA"] +pub type HSTX_TO_CNT_R = crate::FieldReader; +#[doc = "Field `HSTX_TO_CNT` writer - NA"] +pub type HSTX_TO_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + pub fn lprx_to_cnt(&self) -> LPRX_TO_CNT_R { + LPRX_TO_CNT_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - NA"] + #[inline(always)] + pub fn hstx_to_cnt(&self) -> HSTX_TO_CNT_R { + HSTX_TO_CNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TO_CNT_CFG") + .field( + "lprx_to_cnt", + &format_args!("{}", self.lprx_to_cnt().bits()), + ) + .field( + "hstx_to_cnt", + &format_args!("{}", self.hstx_to_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - NA"] + #[inline(always)] + #[must_use] + pub fn lprx_to_cnt(&mut self) -> LPRX_TO_CNT_W { + LPRX_TO_CNT_W::new(self, 0) + } + #[doc = "Bits 16:31 - NA"] + #[inline(always)] + #[must_use] + pub fn hstx_to_cnt(&mut self) -> HSTX_TO_CNT_W { + HSTX_TO_CNT_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`to_cnt_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`to_cnt_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TO_CNT_CFG_SPEC; +impl crate::RegisterSpec for TO_CNT_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`to_cnt_cfg::R`](R) reader structure"] +impl crate::Readable for TO_CNT_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`to_cnt_cfg::W`](W) writer structure"] +impl crate::Writable for TO_CNT_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TO_CNT_CFG to value 0"] +impl crate::Resettable for TO_CNT_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/version.rs b/esp32p4/src/mipi_dsi_host/version.rs new file mode 100644 index 0000000000..65719e1eaa --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/version.rs @@ -0,0 +1,36 @@ +#[doc = "Register `VERSION` reader"] +pub type R = crate::R; +#[doc = "Field `VERSION` reader - NA"] +pub type VERSION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - NA"] + #[inline(always)] + pub fn version(&self) -> VERSION_R { + VERSION_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VERSION") + .field("version", &format_args!("{}", self.version().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VERSION_SPEC; +impl crate::RegisterSpec for VERSION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`version::R`](R) reader structure"] +impl crate::Readable for VERSION_SPEC {} +#[doc = "`reset()` method sets VERSION to value 0x3134_312a"] +impl crate::Resettable for VERSION_SPEC { + const RESET_VALUE: Self::Ux = 0x3134_312a; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_hbp_time.rs b/esp32p4/src/mipi_dsi_host/vid_hbp_time.rs new file mode 100644 index 0000000000..903276deb4 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_hbp_time.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VID_HBP_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `VID_HBP_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `VID_HBP_TIME` reader - NA"] +pub type VID_HBP_TIME_R = crate::FieldReader; +#[doc = "Field `VID_HBP_TIME` writer - NA"] +pub type VID_HBP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - NA"] + #[inline(always)] + pub fn vid_hbp_time(&self) -> VID_HBP_TIME_R { + VID_HBP_TIME_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_HBP_TIME") + .field( + "vid_hbp_time", + &format_args!("{}", self.vid_hbp_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - NA"] + #[inline(always)] + #[must_use] + pub fn vid_hbp_time(&mut self) -> VID_HBP_TIME_W { + VID_HBP_TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hbp_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_hbp_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_HBP_TIME_SPEC; +impl crate::RegisterSpec for VID_HBP_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_hbp_time::R`](R) reader structure"] +impl crate::Readable for VID_HBP_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_hbp_time::W`](W) writer structure"] +impl crate::Writable for VID_HBP_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_HBP_TIME to value 0"] +impl crate::Resettable for VID_HBP_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_hbp_time_act.rs b/esp32p4/src/mipi_dsi_host/vid_hbp_time_act.rs new file mode 100644 index 0000000000..45bd35c13c --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_hbp_time_act.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VID_HBP_TIME_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `VID_HBP_TIME_ACT` reader - NA"] +pub type VID_HBP_TIME_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - NA"] + #[inline(always)] + pub fn vid_hbp_time_act(&self) -> VID_HBP_TIME_ACT_R { + VID_HBP_TIME_ACT_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_HBP_TIME_ACT") + .field( + "vid_hbp_time_act", + &format_args!("{}", self.vid_hbp_time_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hbp_time_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_HBP_TIME_ACT_SPEC; +impl crate::RegisterSpec for VID_HBP_TIME_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_hbp_time_act::R`](R) reader structure"] +impl crate::Readable for VID_HBP_TIME_ACT_SPEC {} +#[doc = "`reset()` method sets VID_HBP_TIME_ACT to value 0"] +impl crate::Resettable for VID_HBP_TIME_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_hline_time.rs b/esp32p4/src/mipi_dsi_host/vid_hline_time.rs new file mode 100644 index 0000000000..8b91eb0d0a --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_hline_time.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VID_HLINE_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `VID_HLINE_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `VID_HLINE_TIME` reader - NA"] +pub type VID_HLINE_TIME_R = crate::FieldReader; +#[doc = "Field `VID_HLINE_TIME` writer - NA"] +pub type VID_HLINE_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + pub fn vid_hline_time(&self) -> VID_HLINE_TIME_R { + VID_HLINE_TIME_R::new((self.bits & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_HLINE_TIME") + .field( + "vid_hline_time", + &format_args!("{}", self.vid_hline_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + #[must_use] + pub fn vid_hline_time(&mut self) -> VID_HLINE_TIME_W { + VID_HLINE_TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hline_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_hline_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_HLINE_TIME_SPEC; +impl crate::RegisterSpec for VID_HLINE_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_hline_time::R`](R) reader structure"] +impl crate::Readable for VID_HLINE_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_hline_time::W`](W) writer structure"] +impl crate::Writable for VID_HLINE_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_HLINE_TIME to value 0"] +impl crate::Resettable for VID_HLINE_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_hline_time_act.rs b/esp32p4/src/mipi_dsi_host/vid_hline_time_act.rs new file mode 100644 index 0000000000..86f983bb40 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_hline_time_act.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VID_HLINE_TIME_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `VID_HLINE_TIME_ACT` reader - NA"] +pub type VID_HLINE_TIME_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:14 - NA"] + #[inline(always)] + pub fn vid_hline_time_act(&self) -> VID_HLINE_TIME_ACT_R { + VID_HLINE_TIME_ACT_R::new((self.bits & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_HLINE_TIME_ACT") + .field( + "vid_hline_time_act", + &format_args!("{}", self.vid_hline_time_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hline_time_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_HLINE_TIME_ACT_SPEC; +impl crate::RegisterSpec for VID_HLINE_TIME_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_hline_time_act::R`](R) reader structure"] +impl crate::Readable for VID_HLINE_TIME_ACT_SPEC {} +#[doc = "`reset()` method sets VID_HLINE_TIME_ACT to value 0"] +impl crate::Resettable for VID_HLINE_TIME_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_hsa_time.rs b/esp32p4/src/mipi_dsi_host/vid_hsa_time.rs new file mode 100644 index 0000000000..2cebb93807 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_hsa_time.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VID_HSA_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `VID_HSA_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `VID_HSA_TIME` reader - NA"] +pub type VID_HSA_TIME_R = crate::FieldReader; +#[doc = "Field `VID_HSA_TIME` writer - NA"] +pub type VID_HSA_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - NA"] + #[inline(always)] + pub fn vid_hsa_time(&self) -> VID_HSA_TIME_R { + VID_HSA_TIME_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_HSA_TIME") + .field( + "vid_hsa_time", + &format_args!("{}", self.vid_hsa_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - NA"] + #[inline(always)] + #[must_use] + pub fn vid_hsa_time(&mut self) -> VID_HSA_TIME_W { + VID_HSA_TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hsa_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_hsa_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_HSA_TIME_SPEC; +impl crate::RegisterSpec for VID_HSA_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_hsa_time::R`](R) reader structure"] +impl crate::Readable for VID_HSA_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_hsa_time::W`](W) writer structure"] +impl crate::Writable for VID_HSA_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_HSA_TIME to value 0"] +impl crate::Resettable for VID_HSA_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_hsa_time_act.rs b/esp32p4/src/mipi_dsi_host/vid_hsa_time_act.rs new file mode 100644 index 0000000000..ad3d9637a4 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_hsa_time_act.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VID_HSA_TIME_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `VID_HSA_TIME_ACT` reader - NA"] +pub type VID_HSA_TIME_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - NA"] + #[inline(always)] + pub fn vid_hsa_time_act(&self) -> VID_HSA_TIME_ACT_R { + VID_HSA_TIME_ACT_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_HSA_TIME_ACT") + .field( + "vid_hsa_time_act", + &format_args!("{}", self.vid_hsa_time_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hsa_time_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_HSA_TIME_ACT_SPEC; +impl crate::RegisterSpec for VID_HSA_TIME_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_hsa_time_act::R`](R) reader structure"] +impl crate::Readable for VID_HSA_TIME_ACT_SPEC {} +#[doc = "`reset()` method sets VID_HSA_TIME_ACT to value 0"] +impl crate::Resettable for VID_HSA_TIME_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_mode_cfg.rs b/esp32p4/src/mipi_dsi_host/vid_mode_cfg.rs new file mode 100644 index 0000000000..bcd7690b40 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_mode_cfg.rs @@ -0,0 +1,248 @@ +#[doc = "Register `VID_MODE_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `VID_MODE_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `VID_MODE_TYPE` reader - NA"] +pub type VID_MODE_TYPE_R = crate::FieldReader; +#[doc = "Field `VID_MODE_TYPE` writer - NA"] +pub type VID_MODE_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_VSA_EN` reader - NA"] +pub type LP_VSA_EN_R = crate::BitReader; +#[doc = "Field `LP_VSA_EN` writer - NA"] +pub type LP_VSA_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_VBP_EN` reader - NA"] +pub type LP_VBP_EN_R = crate::BitReader; +#[doc = "Field `LP_VBP_EN` writer - NA"] +pub type LP_VBP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_VFP_EN` reader - NA"] +pub type LP_VFP_EN_R = crate::BitReader; +#[doc = "Field `LP_VFP_EN` writer - NA"] +pub type LP_VFP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_VACT_EN` reader - NA"] +pub type LP_VACT_EN_R = crate::BitReader; +#[doc = "Field `LP_VACT_EN` writer - NA"] +pub type LP_VACT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_HBP_EN` reader - NA"] +pub type LP_HBP_EN_R = crate::BitReader; +#[doc = "Field `LP_HBP_EN` writer - NA"] +pub type LP_HBP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_HFP_EN` reader - NA"] +pub type LP_HFP_EN_R = crate::BitReader; +#[doc = "Field `LP_HFP_EN` writer - NA"] +pub type LP_HFP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRAME_BTA_ACK_EN` reader - NA"] +pub type FRAME_BTA_ACK_EN_R = crate::BitReader; +#[doc = "Field `FRAME_BTA_ACK_EN` writer - NA"] +pub type FRAME_BTA_ACK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CMD_EN` reader - NA"] +pub type LP_CMD_EN_R = crate::BitReader; +#[doc = "Field `LP_CMD_EN` writer - NA"] +pub type LP_CMD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VPG_EN` reader - NA"] +pub type VPG_EN_R = crate::BitReader; +#[doc = "Field `VPG_EN` writer - NA"] +pub type VPG_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VPG_MODE` reader - NA"] +pub type VPG_MODE_R = crate::BitReader; +#[doc = "Field `VPG_MODE` writer - NA"] +pub type VPG_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VPG_ORIENTATION` reader - NA"] +pub type VPG_ORIENTATION_R = crate::BitReader; +#[doc = "Field `VPG_ORIENTATION` writer - NA"] +pub type VPG_ORIENTATION_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn vid_mode_type(&self) -> VID_MODE_TYPE_R { + VID_MODE_TYPE_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn lp_vsa_en(&self) -> LP_VSA_EN_R { + LP_VSA_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn lp_vbp_en(&self) -> LP_VBP_EN_R { + LP_VBP_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + pub fn lp_vfp_en(&self) -> LP_VFP_EN_R { + LP_VFP_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + pub fn lp_vact_en(&self) -> LP_VACT_EN_R { + LP_VACT_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + pub fn lp_hbp_en(&self) -> LP_HBP_EN_R { + LP_HBP_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + pub fn lp_hfp_en(&self) -> LP_HFP_EN_R { + LP_HFP_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + pub fn frame_bta_ack_en(&self) -> FRAME_BTA_ACK_EN_R { + FRAME_BTA_ACK_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + pub fn lp_cmd_en(&self) -> LP_CMD_EN_R { + LP_CMD_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn vpg_en(&self) -> VPG_EN_R { + VPG_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + pub fn vpg_mode(&self) -> VPG_MODE_R { + VPG_MODE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + pub fn vpg_orientation(&self) -> VPG_ORIENTATION_R { + VPG_ORIENTATION_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_MODE_CFG") + .field( + "vid_mode_type", + &format_args!("{}", self.vid_mode_type().bits()), + ) + .field("lp_vsa_en", &format_args!("{}", self.lp_vsa_en().bit())) + .field("lp_vbp_en", &format_args!("{}", self.lp_vbp_en().bit())) + .field("lp_vfp_en", &format_args!("{}", self.lp_vfp_en().bit())) + .field("lp_vact_en", &format_args!("{}", self.lp_vact_en().bit())) + .field("lp_hbp_en", &format_args!("{}", self.lp_hbp_en().bit())) + .field("lp_hfp_en", &format_args!("{}", self.lp_hfp_en().bit())) + .field( + "frame_bta_ack_en", + &format_args!("{}", self.frame_bta_ack_en().bit()), + ) + .field("lp_cmd_en", &format_args!("{}", self.lp_cmd_en().bit())) + .field("vpg_en", &format_args!("{}", self.vpg_en().bit())) + .field("vpg_mode", &format_args!("{}", self.vpg_mode().bit())) + .field( + "vpg_orientation", + &format_args!("{}", self.vpg_orientation().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + #[must_use] + pub fn vid_mode_type(&mut self) -> VID_MODE_TYPE_W { + VID_MODE_TYPE_W::new(self, 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn lp_vsa_en(&mut self) -> LP_VSA_EN_W { + LP_VSA_EN_W::new(self, 8) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + #[must_use] + pub fn lp_vbp_en(&mut self) -> LP_VBP_EN_W { + LP_VBP_EN_W::new(self, 9) + } + #[doc = "Bit 10 - NA"] + #[inline(always)] + #[must_use] + pub fn lp_vfp_en(&mut self) -> LP_VFP_EN_W { + LP_VFP_EN_W::new(self, 10) + } + #[doc = "Bit 11 - NA"] + #[inline(always)] + #[must_use] + pub fn lp_vact_en(&mut self) -> LP_VACT_EN_W { + LP_VACT_EN_W::new(self, 11) + } + #[doc = "Bit 12 - NA"] + #[inline(always)] + #[must_use] + pub fn lp_hbp_en(&mut self) -> LP_HBP_EN_W { + LP_HBP_EN_W::new(self, 12) + } + #[doc = "Bit 13 - NA"] + #[inline(always)] + #[must_use] + pub fn lp_hfp_en(&mut self) -> LP_HFP_EN_W { + LP_HFP_EN_W::new(self, 13) + } + #[doc = "Bit 14 - NA"] + #[inline(always)] + #[must_use] + pub fn frame_bta_ack_en(&mut self) -> FRAME_BTA_ACK_EN_W { + FRAME_BTA_ACK_EN_W::new(self, 14) + } + #[doc = "Bit 15 - NA"] + #[inline(always)] + #[must_use] + pub fn lp_cmd_en(&mut self) -> LP_CMD_EN_W { + LP_CMD_EN_W::new(self, 15) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn vpg_en(&mut self) -> VPG_EN_W { + VPG_EN_W::new(self, 16) + } + #[doc = "Bit 20 - NA"] + #[inline(always)] + #[must_use] + pub fn vpg_mode(&mut self) -> VPG_MODE_W { + VPG_MODE_W::new(self, 20) + } + #[doc = "Bit 24 - NA"] + #[inline(always)] + #[must_use] + pub fn vpg_orientation(&mut self) -> VPG_ORIENTATION_W { + VPG_ORIENTATION_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_mode_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_mode_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_MODE_CFG_SPEC; +impl crate::RegisterSpec for VID_MODE_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_mode_cfg::R`](R) reader structure"] +impl crate::Readable for VID_MODE_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_mode_cfg::W`](W) writer structure"] +impl crate::Writable for VID_MODE_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_MODE_CFG to value 0"] +impl crate::Resettable for VID_MODE_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_mode_cfg_act.rs b/esp32p4/src/mipi_dsi_host/vid_mode_cfg_act.rs new file mode 100644 index 0000000000..46f97e8bc5 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_mode_cfg_act.rs @@ -0,0 +1,127 @@ +#[doc = "Register `VID_MODE_CFG_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `VID_MODE_TYPE_ACT` reader - NA"] +pub type VID_MODE_TYPE_ACT_R = crate::FieldReader; +#[doc = "Field `LP_VSA_EN_ACT` reader - NA"] +pub type LP_VSA_EN_ACT_R = crate::BitReader; +#[doc = "Field `LP_VBP_EN_ACT` reader - NA"] +pub type LP_VBP_EN_ACT_R = crate::BitReader; +#[doc = "Field `LP_VFP_EN_ACT` reader - NA"] +pub type LP_VFP_EN_ACT_R = crate::BitReader; +#[doc = "Field `LP_VACT_EN_ACT` reader - NA"] +pub type LP_VACT_EN_ACT_R = crate::BitReader; +#[doc = "Field `LP_HBP_EN_ACT` reader - NA"] +pub type LP_HBP_EN_ACT_R = crate::BitReader; +#[doc = "Field `LP_HFP_EN_ACT` reader - NA"] +pub type LP_HFP_EN_ACT_R = crate::BitReader; +#[doc = "Field `FRAME_BTA_ACK_EN_ACT` reader - NA"] +pub type FRAME_BTA_ACK_EN_ACT_R = crate::BitReader; +#[doc = "Field `LP_CMD_EN_ACT` reader - NA"] +pub type LP_CMD_EN_ACT_R = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - NA"] + #[inline(always)] + pub fn vid_mode_type_act(&self) -> VID_MODE_TYPE_ACT_R { + VID_MODE_TYPE_ACT_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn lp_vsa_en_act(&self) -> LP_VSA_EN_ACT_R { + LP_VSA_EN_ACT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn lp_vbp_en_act(&self) -> LP_VBP_EN_ACT_R { + LP_VBP_EN_ACT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NA"] + #[inline(always)] + pub fn lp_vfp_en_act(&self) -> LP_VFP_EN_ACT_R { + LP_VFP_EN_ACT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - NA"] + #[inline(always)] + pub fn lp_vact_en_act(&self) -> LP_VACT_EN_ACT_R { + LP_VACT_EN_ACT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - NA"] + #[inline(always)] + pub fn lp_hbp_en_act(&self) -> LP_HBP_EN_ACT_R { + LP_HBP_EN_ACT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - NA"] + #[inline(always)] + pub fn lp_hfp_en_act(&self) -> LP_HFP_EN_ACT_R { + LP_HFP_EN_ACT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn frame_bta_ack_en_act(&self) -> FRAME_BTA_ACK_EN_ACT_R { + FRAME_BTA_ACK_EN_ACT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - NA"] + #[inline(always)] + pub fn lp_cmd_en_act(&self) -> LP_CMD_EN_ACT_R { + LP_CMD_EN_ACT_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_MODE_CFG_ACT") + .field( + "vid_mode_type_act", + &format_args!("{}", self.vid_mode_type_act().bits()), + ) + .field( + "lp_vsa_en_act", + &format_args!("{}", self.lp_vsa_en_act().bit()), + ) + .field( + "lp_vbp_en_act", + &format_args!("{}", self.lp_vbp_en_act().bit()), + ) + .field( + "lp_vfp_en_act", + &format_args!("{}", self.lp_vfp_en_act().bit()), + ) + .field( + "lp_vact_en_act", + &format_args!("{}", self.lp_vact_en_act().bit()), + ) + .field( + "lp_hbp_en_act", + &format_args!("{}", self.lp_hbp_en_act().bit()), + ) + .field( + "lp_hfp_en_act", + &format_args!("{}", self.lp_hfp_en_act().bit()), + ) + .field( + "frame_bta_ack_en_act", + &format_args!("{}", self.frame_bta_ack_en_act().bit()), + ) + .field( + "lp_cmd_en_act", + &format_args!("{}", self.lp_cmd_en_act().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_mode_cfg_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_MODE_CFG_ACT_SPEC; +impl crate::RegisterSpec for VID_MODE_CFG_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_mode_cfg_act::R`](R) reader structure"] +impl crate::Readable for VID_MODE_CFG_ACT_SPEC {} +#[doc = "`reset()` method sets VID_MODE_CFG_ACT to value 0"] +impl crate::Resettable for VID_MODE_CFG_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_null_size.rs b/esp32p4/src/mipi_dsi_host/vid_null_size.rs new file mode 100644 index 0000000000..892cce8b9c --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_null_size.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VID_NULL_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `VID_NULL_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `VID_NULL_SIZE` reader - NA"] +pub type VID_NULL_SIZE_R = crate::FieldReader; +#[doc = "Field `VID_NULL_SIZE` writer - NA"] +pub type VID_NULL_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:12 - NA"] + #[inline(always)] + pub fn vid_null_size(&self) -> VID_NULL_SIZE_R { + VID_NULL_SIZE_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_NULL_SIZE") + .field( + "vid_null_size", + &format_args!("{}", self.vid_null_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:12 - NA"] + #[inline(always)] + #[must_use] + pub fn vid_null_size(&mut self) -> VID_NULL_SIZE_W { + VID_NULL_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_null_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_null_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_NULL_SIZE_SPEC; +impl crate::RegisterSpec for VID_NULL_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_null_size::R`](R) reader structure"] +impl crate::Readable for VID_NULL_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_null_size::W`](W) writer structure"] +impl crate::Writable for VID_NULL_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_NULL_SIZE to value 0"] +impl crate::Resettable for VID_NULL_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_null_size_act.rs b/esp32p4/src/mipi_dsi_host/vid_null_size_act.rs new file mode 100644 index 0000000000..4d72e7406d --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_null_size_act.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VID_NULL_SIZE_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `VID_NULL_SIZE_ACT` reader - NA"] +pub type VID_NULL_SIZE_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - NA"] + #[inline(always)] + pub fn vid_null_size_act(&self) -> VID_NULL_SIZE_ACT_R { + VID_NULL_SIZE_ACT_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_NULL_SIZE_ACT") + .field( + "vid_null_size_act", + &format_args!("{}", self.vid_null_size_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_null_size_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_NULL_SIZE_ACT_SPEC; +impl crate::RegisterSpec for VID_NULL_SIZE_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_null_size_act::R`](R) reader structure"] +impl crate::Readable for VID_NULL_SIZE_ACT_SPEC {} +#[doc = "`reset()` method sets VID_NULL_SIZE_ACT to value 0"] +impl crate::Resettable for VID_NULL_SIZE_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_num_chunks.rs b/esp32p4/src/mipi_dsi_host/vid_num_chunks.rs new file mode 100644 index 0000000000..0cb2a98706 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_num_chunks.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VID_NUM_CHUNKS` reader"] +pub type R = crate::R; +#[doc = "Register `VID_NUM_CHUNKS` writer"] +pub type W = crate::W; +#[doc = "Field `VID_NUM_CHUNKS` reader - NA"] +pub type VID_NUM_CHUNKS_R = crate::FieldReader; +#[doc = "Field `VID_NUM_CHUNKS` writer - NA"] +pub type VID_NUM_CHUNKS_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:12 - NA"] + #[inline(always)] + pub fn vid_num_chunks(&self) -> VID_NUM_CHUNKS_R { + VID_NUM_CHUNKS_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_NUM_CHUNKS") + .field( + "vid_num_chunks", + &format_args!("{}", self.vid_num_chunks().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:12 - NA"] + #[inline(always)] + #[must_use] + pub fn vid_num_chunks(&mut self) -> VID_NUM_CHUNKS_W { + VID_NUM_CHUNKS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_num_chunks::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_num_chunks::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_NUM_CHUNKS_SPEC; +impl crate::RegisterSpec for VID_NUM_CHUNKS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_num_chunks::R`](R) reader structure"] +impl crate::Readable for VID_NUM_CHUNKS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_num_chunks::W`](W) writer structure"] +impl crate::Writable for VID_NUM_CHUNKS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_NUM_CHUNKS to value 0"] +impl crate::Resettable for VID_NUM_CHUNKS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_num_chunks_act.rs b/esp32p4/src/mipi_dsi_host/vid_num_chunks_act.rs new file mode 100644 index 0000000000..e4bf5642d5 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_num_chunks_act.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VID_NUM_CHUNKS_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `VID_NUM_CHUNKS_ACT` reader - NA"] +pub type VID_NUM_CHUNKS_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:12 - NA"] + #[inline(always)] + pub fn vid_num_chunks_act(&self) -> VID_NUM_CHUNKS_ACT_R { + VID_NUM_CHUNKS_ACT_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_NUM_CHUNKS_ACT") + .field( + "vid_num_chunks_act", + &format_args!("{}", self.vid_num_chunks_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_num_chunks_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_NUM_CHUNKS_ACT_SPEC; +impl crate::RegisterSpec for VID_NUM_CHUNKS_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_num_chunks_act::R`](R) reader structure"] +impl crate::Readable for VID_NUM_CHUNKS_ACT_SPEC {} +#[doc = "`reset()` method sets VID_NUM_CHUNKS_ACT to value 0"] +impl crate::Resettable for VID_NUM_CHUNKS_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_pkt_size.rs b/esp32p4/src/mipi_dsi_host/vid_pkt_size.rs new file mode 100644 index 0000000000..bc1e401e2c --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_pkt_size.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VID_PKT_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `VID_PKT_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `VID_PKT_SIZE` reader - NA"] +pub type VID_PKT_SIZE_R = crate::FieldReader; +#[doc = "Field `VID_PKT_SIZE` writer - NA"] +pub type VID_PKT_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - NA"] + #[inline(always)] + pub fn vid_pkt_size(&self) -> VID_PKT_SIZE_R { + VID_PKT_SIZE_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_PKT_SIZE") + .field( + "vid_pkt_size", + &format_args!("{}", self.vid_pkt_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - NA"] + #[inline(always)] + #[must_use] + pub fn vid_pkt_size(&mut self) -> VID_PKT_SIZE_W { + VID_PKT_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_pkt_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_pkt_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_PKT_SIZE_SPEC; +impl crate::RegisterSpec for VID_PKT_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_pkt_size::R`](R) reader structure"] +impl crate::Readable for VID_PKT_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_pkt_size::W`](W) writer structure"] +impl crate::Writable for VID_PKT_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_PKT_SIZE to value 0"] +impl crate::Resettable for VID_PKT_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_pkt_size_act.rs b/esp32p4/src/mipi_dsi_host/vid_pkt_size_act.rs new file mode 100644 index 0000000000..c6e4b27023 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_pkt_size_act.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VID_PKT_SIZE_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `VID_PKT_SIZE_ACT` reader - NA"] +pub type VID_PKT_SIZE_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:13 - NA"] + #[inline(always)] + pub fn vid_pkt_size_act(&self) -> VID_PKT_SIZE_ACT_R { + VID_PKT_SIZE_ACT_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_PKT_SIZE_ACT") + .field( + "vid_pkt_size_act", + &format_args!("{}", self.vid_pkt_size_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_pkt_size_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_PKT_SIZE_ACT_SPEC; +impl crate::RegisterSpec for VID_PKT_SIZE_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_pkt_size_act::R`](R) reader structure"] +impl crate::Readable for VID_PKT_SIZE_ACT_SPEC {} +#[doc = "`reset()` method sets VID_PKT_SIZE_ACT to value 0"] +impl crate::Resettable for VID_PKT_SIZE_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_pkt_status.rs b/esp32p4/src/mipi_dsi_host/vid_pkt_status.rs new file mode 100644 index 0000000000..5f7f62baba --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_pkt_status.rs @@ -0,0 +1,94 @@ +#[doc = "Register `VID_PKT_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `DPI_CMD_W_EMPTY` reader - NA"] +pub type DPI_CMD_W_EMPTY_R = crate::BitReader; +#[doc = "Field `DPI_CMD_W_FULL` reader - NA"] +pub type DPI_CMD_W_FULL_R = crate::BitReader; +#[doc = "Field `DPI_PLD_W_EMPTY` reader - NA"] +pub type DPI_PLD_W_EMPTY_R = crate::BitReader; +#[doc = "Field `DPI_PLD_W_FULL` reader - NA"] +pub type DPI_PLD_W_FULL_R = crate::BitReader; +#[doc = "Field `DPI_BUFF_PLD_EMPTY` reader - NA"] +pub type DPI_BUFF_PLD_EMPTY_R = crate::BitReader; +#[doc = "Field `DPI_BUFF_PLD_FULL` reader - NA"] +pub type DPI_BUFF_PLD_FULL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn dpi_cmd_w_empty(&self) -> DPI_CMD_W_EMPTY_R { + DPI_CMD_W_EMPTY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NA"] + #[inline(always)] + pub fn dpi_cmd_w_full(&self) -> DPI_CMD_W_FULL_R { + DPI_CMD_W_FULL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NA"] + #[inline(always)] + pub fn dpi_pld_w_empty(&self) -> DPI_PLD_W_EMPTY_R { + DPI_PLD_W_EMPTY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - NA"] + #[inline(always)] + pub fn dpi_pld_w_full(&self) -> DPI_PLD_W_FULL_R { + DPI_PLD_W_FULL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn dpi_buff_pld_empty(&self) -> DPI_BUFF_PLD_EMPTY_R { + DPI_BUFF_PLD_EMPTY_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - NA"] + #[inline(always)] + pub fn dpi_buff_pld_full(&self) -> DPI_BUFF_PLD_FULL_R { + DPI_BUFF_PLD_FULL_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_PKT_STATUS") + .field( + "dpi_cmd_w_empty", + &format_args!("{}", self.dpi_cmd_w_empty().bit()), + ) + .field( + "dpi_cmd_w_full", + &format_args!("{}", self.dpi_cmd_w_full().bit()), + ) + .field( + "dpi_pld_w_empty", + &format_args!("{}", self.dpi_pld_w_empty().bit()), + ) + .field( + "dpi_pld_w_full", + &format_args!("{}", self.dpi_pld_w_full().bit()), + ) + .field( + "dpi_buff_pld_empty", + &format_args!("{}", self.dpi_buff_pld_empty().bit()), + ) + .field( + "dpi_buff_pld_full", + &format_args!("{}", self.dpi_buff_pld_full().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_pkt_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_PKT_STATUS_SPEC; +impl crate::RegisterSpec for VID_PKT_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_pkt_status::R`](R) reader structure"] +impl crate::Readable for VID_PKT_STATUS_SPEC {} +#[doc = "`reset()` method sets VID_PKT_STATUS to value 0x0001_0005"] +impl crate::Resettable for VID_PKT_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0005; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_shadow_ctrl.rs b/esp32p4/src/mipi_dsi_host/vid_shadow_ctrl.rs new file mode 100644 index 0000000000..b17d671f15 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_shadow_ctrl.rs @@ -0,0 +1,104 @@ +#[doc = "Register `VID_SHADOW_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `VID_SHADOW_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `VID_SHADOW_EN` reader - NA"] +pub type VID_SHADOW_EN_R = crate::BitReader; +#[doc = "Field `VID_SHADOW_EN` writer - NA"] +pub type VID_SHADOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VID_SHADOW_REQ` reader - NA"] +pub type VID_SHADOW_REQ_R = crate::BitReader; +#[doc = "Field `VID_SHADOW_REQ` writer - NA"] +pub type VID_SHADOW_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VID_SHADOW_PIN_REQ` reader - NA"] +pub type VID_SHADOW_PIN_REQ_R = crate::BitReader; +#[doc = "Field `VID_SHADOW_PIN_REQ` writer - NA"] +pub type VID_SHADOW_PIN_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - NA"] + #[inline(always)] + pub fn vid_shadow_en(&self) -> VID_SHADOW_EN_R { + VID_SHADOW_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + pub fn vid_shadow_req(&self) -> VID_SHADOW_REQ_R { + VID_SHADOW_REQ_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + pub fn vid_shadow_pin_req(&self) -> VID_SHADOW_PIN_REQ_R { + VID_SHADOW_PIN_REQ_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_SHADOW_CTRL") + .field( + "vid_shadow_en", + &format_args!("{}", self.vid_shadow_en().bit()), + ) + .field( + "vid_shadow_req", + &format_args!("{}", self.vid_shadow_req().bit()), + ) + .field( + "vid_shadow_pin_req", + &format_args!("{}", self.vid_shadow_pin_req().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - NA"] + #[inline(always)] + #[must_use] + pub fn vid_shadow_en(&mut self) -> VID_SHADOW_EN_W { + VID_SHADOW_EN_W::new(self, 0) + } + #[doc = "Bit 8 - NA"] + #[inline(always)] + #[must_use] + pub fn vid_shadow_req(&mut self) -> VID_SHADOW_REQ_W { + VID_SHADOW_REQ_W::new(self, 8) + } + #[doc = "Bit 16 - NA"] + #[inline(always)] + #[must_use] + pub fn vid_shadow_pin_req(&mut self) -> VID_SHADOW_PIN_REQ_W { + VID_SHADOW_PIN_REQ_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_shadow_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_shadow_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_SHADOW_CTRL_SPEC; +impl crate::RegisterSpec for VID_SHADOW_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_shadow_ctrl::R`](R) reader structure"] +impl crate::Readable for VID_SHADOW_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_shadow_ctrl::W`](W) writer structure"] +impl crate::Writable for VID_SHADOW_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_SHADOW_CTRL to value 0"] +impl crate::Resettable for VID_SHADOW_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_vactive_lines.rs b/esp32p4/src/mipi_dsi_host/vid_vactive_lines.rs new file mode 100644 index 0000000000..57ad52fc3d --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_vactive_lines.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VID_VACTIVE_LINES` reader"] +pub type R = crate::R; +#[doc = "Register `VID_VACTIVE_LINES` writer"] +pub type W = crate::W; +#[doc = "Field `V_ACTIVE_LINES` reader - NA"] +pub type V_ACTIVE_LINES_R = crate::FieldReader; +#[doc = "Field `V_ACTIVE_LINES` writer - NA"] +pub type V_ACTIVE_LINES_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - NA"] + #[inline(always)] + pub fn v_active_lines(&self) -> V_ACTIVE_LINES_R { + V_ACTIVE_LINES_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_VACTIVE_LINES") + .field( + "v_active_lines", + &format_args!("{}", self.v_active_lines().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - NA"] + #[inline(always)] + #[must_use] + pub fn v_active_lines(&mut self) -> V_ACTIVE_LINES_W { + V_ACTIVE_LINES_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vactive_lines::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_vactive_lines::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_VACTIVE_LINES_SPEC; +impl crate::RegisterSpec for VID_VACTIVE_LINES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_vactive_lines::R`](R) reader structure"] +impl crate::Readable for VID_VACTIVE_LINES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_vactive_lines::W`](W) writer structure"] +impl crate::Writable for VID_VACTIVE_LINES_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_VACTIVE_LINES to value 0"] +impl crate::Resettable for VID_VACTIVE_LINES_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_vactive_lines_act.rs b/esp32p4/src/mipi_dsi_host/vid_vactive_lines_act.rs new file mode 100644 index 0000000000..037ced15e3 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_vactive_lines_act.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VID_VACTIVE_LINES_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `V_ACTIVE_LINES_ACT` reader - NA"] +pub type V_ACTIVE_LINES_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:13 - NA"] + #[inline(always)] + pub fn v_active_lines_act(&self) -> V_ACTIVE_LINES_ACT_R { + V_ACTIVE_LINES_ACT_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_VACTIVE_LINES_ACT") + .field( + "v_active_lines_act", + &format_args!("{}", self.v_active_lines_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vactive_lines_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_VACTIVE_LINES_ACT_SPEC; +impl crate::RegisterSpec for VID_VACTIVE_LINES_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_vactive_lines_act::R`](R) reader structure"] +impl crate::Readable for VID_VACTIVE_LINES_ACT_SPEC {} +#[doc = "`reset()` method sets VID_VACTIVE_LINES_ACT to value 0"] +impl crate::Resettable for VID_VACTIVE_LINES_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_vbp_lines.rs b/esp32p4/src/mipi_dsi_host/vid_vbp_lines.rs new file mode 100644 index 0000000000..02ed3c3620 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_vbp_lines.rs @@ -0,0 +1,63 @@ +#[doc = "Register `VID_VBP_LINES` reader"] +pub type R = crate::R; +#[doc = "Register `VID_VBP_LINES` writer"] +pub type W = crate::W; +#[doc = "Field `VBP_LINES` reader - NA"] +pub type VBP_LINES_R = crate::FieldReader; +#[doc = "Field `VBP_LINES` writer - NA"] +pub type VBP_LINES_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + pub fn vbp_lines(&self) -> VBP_LINES_R { + VBP_LINES_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_VBP_LINES") + .field("vbp_lines", &format_args!("{}", self.vbp_lines().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + #[must_use] + pub fn vbp_lines(&mut self) -> VBP_LINES_W { + VBP_LINES_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vbp_lines::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_vbp_lines::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_VBP_LINES_SPEC; +impl crate::RegisterSpec for VID_VBP_LINES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_vbp_lines::R`](R) reader structure"] +impl crate::Readable for VID_VBP_LINES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_vbp_lines::W`](W) writer structure"] +impl crate::Writable for VID_VBP_LINES_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_VBP_LINES to value 0"] +impl crate::Resettable for VID_VBP_LINES_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_vbp_lines_act.rs b/esp32p4/src/mipi_dsi_host/vid_vbp_lines_act.rs new file mode 100644 index 0000000000..65337acdd1 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_vbp_lines_act.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VID_VBP_LINES_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `VBP_LINES_ACT` reader - NA"] +pub type VBP_LINES_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + pub fn vbp_lines_act(&self) -> VBP_LINES_ACT_R { + VBP_LINES_ACT_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_VBP_LINES_ACT") + .field( + "vbp_lines_act", + &format_args!("{}", self.vbp_lines_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vbp_lines_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_VBP_LINES_ACT_SPEC; +impl crate::RegisterSpec for VID_VBP_LINES_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_vbp_lines_act::R`](R) reader structure"] +impl crate::Readable for VID_VBP_LINES_ACT_SPEC {} +#[doc = "`reset()` method sets VID_VBP_LINES_ACT to value 0"] +impl crate::Resettable for VID_VBP_LINES_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_vfp_lines.rs b/esp32p4/src/mipi_dsi_host/vid_vfp_lines.rs new file mode 100644 index 0000000000..3190ff0960 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_vfp_lines.rs @@ -0,0 +1,63 @@ +#[doc = "Register `VID_VFP_LINES` reader"] +pub type R = crate::R; +#[doc = "Register `VID_VFP_LINES` writer"] +pub type W = crate::W; +#[doc = "Field `VFP_LINES` reader - NA"] +pub type VFP_LINES_R = crate::FieldReader; +#[doc = "Field `VFP_LINES` writer - NA"] +pub type VFP_LINES_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + pub fn vfp_lines(&self) -> VFP_LINES_R { + VFP_LINES_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_VFP_LINES") + .field("vfp_lines", &format_args!("{}", self.vfp_lines().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + #[must_use] + pub fn vfp_lines(&mut self) -> VFP_LINES_W { + VFP_LINES_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vfp_lines::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_vfp_lines::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_VFP_LINES_SPEC; +impl crate::RegisterSpec for VID_VFP_LINES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_vfp_lines::R`](R) reader structure"] +impl crate::Readable for VID_VFP_LINES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_vfp_lines::W`](W) writer structure"] +impl crate::Writable for VID_VFP_LINES_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_VFP_LINES to value 0"] +impl crate::Resettable for VID_VFP_LINES_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_vfp_lines_act.rs b/esp32p4/src/mipi_dsi_host/vid_vfp_lines_act.rs new file mode 100644 index 0000000000..2de3ab3186 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_vfp_lines_act.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VID_VFP_LINES_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `VFP_LINES_ACT` reader - NA"] +pub type VFP_LINES_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + pub fn vfp_lines_act(&self) -> VFP_LINES_ACT_R { + VFP_LINES_ACT_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_VFP_LINES_ACT") + .field( + "vfp_lines_act", + &format_args!("{}", self.vfp_lines_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vfp_lines_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_VFP_LINES_ACT_SPEC; +impl crate::RegisterSpec for VID_VFP_LINES_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_vfp_lines_act::R`](R) reader structure"] +impl crate::Readable for VID_VFP_LINES_ACT_SPEC {} +#[doc = "`reset()` method sets VID_VFP_LINES_ACT to value 0"] +impl crate::Resettable for VID_VFP_LINES_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_vsa_lines.rs b/esp32p4/src/mipi_dsi_host/vid_vsa_lines.rs new file mode 100644 index 0000000000..618092e6f0 --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_vsa_lines.rs @@ -0,0 +1,63 @@ +#[doc = "Register `VID_VSA_LINES` reader"] +pub type R = crate::R; +#[doc = "Register `VID_VSA_LINES` writer"] +pub type W = crate::W; +#[doc = "Field `VSA_LINES` reader - NA"] +pub type VSA_LINES_R = crate::FieldReader; +#[doc = "Field `VSA_LINES` writer - NA"] +pub type VSA_LINES_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + pub fn vsa_lines(&self) -> VSA_LINES_R { + VSA_LINES_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_VSA_LINES") + .field("vsa_lines", &format_args!("{}", self.vsa_lines().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + #[must_use] + pub fn vsa_lines(&mut self) -> VSA_LINES_W { + VSA_LINES_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vsa_lines::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vid_vsa_lines::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_VSA_LINES_SPEC; +impl crate::RegisterSpec for VID_VSA_LINES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_vsa_lines::R`](R) reader structure"] +impl crate::Readable for VID_VSA_LINES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vid_vsa_lines::W`](W) writer structure"] +impl crate::Writable for VID_VSA_LINES_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VID_VSA_LINES to value 0"] +impl crate::Resettable for VID_VSA_LINES_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/mipi_dsi_host/vid_vsa_lines_act.rs b/esp32p4/src/mipi_dsi_host/vid_vsa_lines_act.rs new file mode 100644 index 0000000000..6f10a4a79e --- /dev/null +++ b/esp32p4/src/mipi_dsi_host/vid_vsa_lines_act.rs @@ -0,0 +1,39 @@ +#[doc = "Register `VID_VSA_LINES_ACT` reader"] +pub type R = crate::R; +#[doc = "Field `VSA_LINES_ACT` reader - NA"] +pub type VSA_LINES_ACT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - NA"] + #[inline(always)] + pub fn vsa_lines_act(&self) -> VSA_LINES_ACT_R { + VSA_LINES_ACT_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VID_VSA_LINES_ACT") + .field( + "vsa_lines_act", + &format_args!("{}", self.vsa_lines_act().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vsa_lines_act::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VID_VSA_LINES_ACT_SPEC; +impl crate::RegisterSpec for VID_VSA_LINES_ACT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vid_vsa_lines_act::R`](R) reader structure"] +impl crate::Readable for VID_VSA_LINES_ACT_SPEC {} +#[doc = "`reset()` method sets VID_VSA_LINES_ACT to value 0"] +impl crate::Resettable for VID_VSA_LINES_ACT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io.rs b/esp32p4/src/parl_io.rs new file mode 100644 index 0000000000..3859a17d36 --- /dev/null +++ b/esp32p4/src/parl_io.rs @@ -0,0 +1,219 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + rx_mode_cfg: RX_MODE_CFG, + rx_data_cfg: RX_DATA_CFG, + rx_genrl_cfg: RX_GENRL_CFG, + rx_start_cfg: RX_START_CFG, + tx_data_cfg: TX_DATA_CFG, + tx_start_cfg: TX_START_CFG, + tx_genrl_cfg: TX_GENRL_CFG, + fifo_cfg: FIFO_CFG, + reg_update: REG_UPDATE, + st: ST, + int_ena: INT_ENA, + int_raw: INT_RAW, + int_st: INT_ST, + int_clr: INT_CLR, + rx_st0: RX_ST0, + rx_st1: RX_ST1, + tx_st0: TX_ST0, + rx_clk_cfg: RX_CLK_CFG, + tx_clk_cfg: TX_CLK_CFG, + _reserved19: [u8; 0xd4], + clk: CLK, + _reserved20: [u8; 0x02d8], + version: VERSION, +} +impl RegisterBlock { + #[doc = "0x00 - Parallel RX Sampling mode configuration register."] + #[inline(always)] + pub const fn rx_mode_cfg(&self) -> &RX_MODE_CFG { + &self.rx_mode_cfg + } + #[doc = "0x04 - Parallel RX data configuration register."] + #[inline(always)] + pub const fn rx_data_cfg(&self) -> &RX_DATA_CFG { + &self.rx_data_cfg + } + #[doc = "0x08 - Parallel RX general configuration register."] + #[inline(always)] + pub const fn rx_genrl_cfg(&self) -> &RX_GENRL_CFG { + &self.rx_genrl_cfg + } + #[doc = "0x0c - Parallel RX Start configuration register."] + #[inline(always)] + pub const fn rx_start_cfg(&self) -> &RX_START_CFG { + &self.rx_start_cfg + } + #[doc = "0x10 - Parallel TX data configuration register."] + #[inline(always)] + pub const fn tx_data_cfg(&self) -> &TX_DATA_CFG { + &self.tx_data_cfg + } + #[doc = "0x14 - Parallel TX Start configuration register."] + #[inline(always)] + pub const fn tx_start_cfg(&self) -> &TX_START_CFG { + &self.tx_start_cfg + } + #[doc = "0x18 - Parallel TX general configuration register."] + #[inline(always)] + pub const fn tx_genrl_cfg(&self) -> &TX_GENRL_CFG { + &self.tx_genrl_cfg + } + #[doc = "0x1c - Parallel IO FIFO configuration register."] + #[inline(always)] + pub const fn fifo_cfg(&self) -> &FIFO_CFG { + &self.fifo_cfg + } + #[doc = "0x20 - Parallel IO FIFO configuration register."] + #[inline(always)] + pub const fn reg_update(&self) -> ®_UPDATE { + &self.reg_update + } + #[doc = "0x24 - Parallel IO module status register0."] + #[inline(always)] + pub const fn st(&self) -> &ST { + &self.st + } + #[doc = "0x28 - Parallel IO interrupt enable singal configuration register."] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x2c - Parallel IO interrupt raw singal status register."] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x30 - Parallel IO interrupt singal status register."] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x34 - Parallel IO interrupt clear singal configuration register."] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x38 - Parallel IO RX status register0"] + #[inline(always)] + pub const fn rx_st0(&self) -> &RX_ST0 { + &self.rx_st0 + } + #[doc = "0x3c - Parallel IO RX status register1"] + #[inline(always)] + pub const fn rx_st1(&self) -> &RX_ST1 { + &self.rx_st1 + } + #[doc = "0x40 - Parallel IO TX status register0"] + #[inline(always)] + pub const fn tx_st0(&self) -> &TX_ST0 { + &self.tx_st0 + } + #[doc = "0x44 - Parallel IO RX clk configuration register"] + #[inline(always)] + pub const fn rx_clk_cfg(&self) -> &RX_CLK_CFG { + &self.rx_clk_cfg + } + #[doc = "0x48 - Parallel IO TX clk configuration register"] + #[inline(always)] + pub const fn tx_clk_cfg(&self) -> &TX_CLK_CFG { + &self.tx_clk_cfg + } + #[doc = "0x120 - Parallel IO clk configuration register"] + #[inline(always)] + pub const fn clk(&self) -> &CLK { + &self.clk + } + #[doc = "0x3fc - Version register."] + #[inline(always)] + pub const fn version(&self) -> &VERSION { + &self.version + } +} +#[doc = "RX_MODE_CFG (rw) register accessor: Parallel RX Sampling mode configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_mode_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_mode_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_mode_cfg`] module"] +pub type RX_MODE_CFG = crate::Reg; +#[doc = "Parallel RX Sampling mode configuration register."] +pub mod rx_mode_cfg; +#[doc = "RX_DATA_CFG (rw) register accessor: Parallel RX data configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_data_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_data_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_data_cfg`] module"] +pub type RX_DATA_CFG = crate::Reg; +#[doc = "Parallel RX data configuration register."] +pub mod rx_data_cfg; +#[doc = "RX_GENRL_CFG (rw) register accessor: Parallel RX general configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_genrl_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_genrl_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_genrl_cfg`] module"] +pub type RX_GENRL_CFG = crate::Reg; +#[doc = "Parallel RX general configuration register."] +pub mod rx_genrl_cfg; +#[doc = "RX_START_CFG (rw) register accessor: Parallel RX Start configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_start_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_start_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_start_cfg`] module"] +pub type RX_START_CFG = crate::Reg; +#[doc = "Parallel RX Start configuration register."] +pub mod rx_start_cfg; +#[doc = "TX_DATA_CFG (rw) register accessor: Parallel TX data configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_data_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_data_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data_cfg`] module"] +pub type TX_DATA_CFG = crate::Reg; +#[doc = "Parallel TX data configuration register."] +pub mod tx_data_cfg; +#[doc = "TX_START_CFG (rw) register accessor: Parallel TX Start configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_start_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_start_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_start_cfg`] module"] +pub type TX_START_CFG = crate::Reg; +#[doc = "Parallel TX Start configuration register."] +pub mod tx_start_cfg; +#[doc = "TX_GENRL_CFG (rw) register accessor: Parallel TX general configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_genrl_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_genrl_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_genrl_cfg`] module"] +pub type TX_GENRL_CFG = crate::Reg; +#[doc = "Parallel TX general configuration register."] +pub mod tx_genrl_cfg; +#[doc = "FIFO_CFG (rw) register accessor: Parallel IO FIFO configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_cfg`] module"] +pub type FIFO_CFG = crate::Reg; +#[doc = "Parallel IO FIFO configuration register."] +pub mod fifo_cfg; +#[doc = "REG_UPDATE (w) register accessor: Parallel IO FIFO configuration register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_update::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_update`] module"] +pub type REG_UPDATE = crate::Reg; +#[doc = "Parallel IO FIFO configuration register."] +pub mod reg_update; +#[doc = "ST (r) register accessor: Parallel IO module status register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@st`] module"] +pub type ST = crate::Reg; +#[doc = "Parallel IO module status register0."] +pub mod st; +#[doc = "INT_ENA (rw) register accessor: Parallel IO interrupt enable singal configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Parallel IO interrupt enable singal configuration register."] +pub mod int_ena; +#[doc = "INT_RAW (rw) register accessor: Parallel IO interrupt raw singal status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Parallel IO interrupt raw singal status register."] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Parallel IO interrupt singal status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Parallel IO interrupt singal status register."] +pub mod int_st; +#[doc = "INT_CLR (w) register accessor: Parallel IO interrupt clear singal configuration register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Parallel IO interrupt clear singal configuration register."] +pub mod int_clr; +#[doc = "RX_ST0 (r) register accessor: Parallel IO RX status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_st0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_st0`] module"] +pub type RX_ST0 = crate::Reg; +#[doc = "Parallel IO RX status register0"] +pub mod rx_st0; +#[doc = "RX_ST1 (r) register accessor: Parallel IO RX status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_st1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_st1`] module"] +pub type RX_ST1 = crate::Reg; +#[doc = "Parallel IO RX status register1"] +pub mod rx_st1; +#[doc = "TX_ST0 (r) register accessor: Parallel IO TX status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_st0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_st0`] module"] +pub type TX_ST0 = crate::Reg; +#[doc = "Parallel IO TX status register0"] +pub mod tx_st0; +#[doc = "RX_CLK_CFG (rw) register accessor: Parallel IO RX clk configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_clk_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_clk_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_clk_cfg`] module"] +pub type RX_CLK_CFG = crate::Reg; +#[doc = "Parallel IO RX clk configuration register"] +pub mod rx_clk_cfg; +#[doc = "TX_CLK_CFG (rw) register accessor: Parallel IO TX clk configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_clk_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_clk_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_clk_cfg`] module"] +pub type TX_CLK_CFG = crate::Reg; +#[doc = "Parallel IO TX clk configuration register"] +pub mod tx_clk_cfg; +#[doc = "CLK (rw) register accessor: Parallel IO clk configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk`] module"] +pub type CLK = crate::Reg; +#[doc = "Parallel IO clk configuration register"] +pub mod clk; +#[doc = "VERSION (rw) register accessor: Version register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"] +pub type VERSION = crate::Reg; +#[doc = "Version register."] +pub mod version; diff --git a/esp32p4/src/parl_io/clk.rs b/esp32p4/src/parl_io/clk.rs new file mode 100644 index 0000000000..d7d0b9e9f7 --- /dev/null +++ b/esp32p4/src/parl_io/clk.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLK` reader"] +pub type R = crate::R; +#[doc = "Register `CLK` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Force clock on for this register file"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Force clock on for this register file"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - Force clock on for this register file"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK") + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - Force clock on for this register file"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel IO clk configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_SPEC; +impl crate::RegisterSpec for CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk::R`](R) reader structure"] +impl crate::Readable for CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"] +impl crate::Writable for CLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK to value 0"] +impl crate::Resettable for CLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/fifo_cfg.rs b/esp32p4/src/parl_io/fifo_cfg.rs new file mode 100644 index 0000000000..569f2e91c8 --- /dev/null +++ b/esp32p4/src/parl_io/fifo_cfg.rs @@ -0,0 +1,85 @@ +#[doc = "Register `FIFO_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `TX_FIFO_SRST` reader - Set this bit to reset async fifo in tx module."] +pub type TX_FIFO_SRST_R = crate::BitReader; +#[doc = "Field `TX_FIFO_SRST` writer - Set this bit to reset async fifo in tx module."] +pub type TX_FIFO_SRST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFO_SRST` reader - Set this bit to reset async fifo in rx module."] +pub type RX_FIFO_SRST_R = crate::BitReader; +#[doc = "Field `RX_FIFO_SRST` writer - Set this bit to reset async fifo in rx module."] +pub type RX_FIFO_SRST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 30 - Set this bit to reset async fifo in tx module."] + #[inline(always)] + pub fn tx_fifo_srst(&self) -> TX_FIFO_SRST_R { + TX_FIFO_SRST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Set this bit to reset async fifo in rx module."] + #[inline(always)] + pub fn rx_fifo_srst(&self) -> RX_FIFO_SRST_R { + RX_FIFO_SRST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO_CFG") + .field( + "tx_fifo_srst", + &format_args!("{}", self.tx_fifo_srst().bit()), + ) + .field( + "rx_fifo_srst", + &format_args!("{}", self.rx_fifo_srst().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - Set this bit to reset async fifo in tx module."] + #[inline(always)] + #[must_use] + pub fn tx_fifo_srst(&mut self) -> TX_FIFO_SRST_W { + TX_FIFO_SRST_W::new(self, 30) + } + #[doc = "Bit 31 - Set this bit to reset async fifo in rx module."] + #[inline(always)] + #[must_use] + pub fn rx_fifo_srst(&mut self) -> RX_FIFO_SRST_W { + RX_FIFO_SRST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel IO FIFO configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_CFG_SPEC; +impl crate::RegisterSpec for FIFO_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_cfg::R`](R) reader structure"] +impl crate::Readable for FIFO_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo_cfg::W`](W) writer structure"] +impl crate::Writable for FIFO_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIFO_CFG to value 0"] +impl crate::Resettable for FIFO_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/int_clr.rs b/esp32p4/src/parl_io/int_clr.rs new file mode 100644 index 0000000000..c94f5d4d0d --- /dev/null +++ b/esp32p4/src/parl_io/int_clr.rs @@ -0,0 +1,58 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `TX_FIFO_REMPTY_INT_CLR` writer - Set this bit to clear TX_FIFO_REMPTY_INT."] +pub type TX_FIFO_REMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFO_WOVF_INT_CLR` writer - Set this bit to clear RX_FIFO_WOVF_INT."] +pub type RX_FIFO_WOVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_EOF_INT_CLR` writer - Set this bit to clear TX_EOF_INT."] +pub type TX_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear TX_FIFO_REMPTY_INT."] + #[inline(always)] + #[must_use] + pub fn tx_fifo_rempty_int_clr(&mut self) -> TX_FIFO_REMPTY_INT_CLR_W { + TX_FIFO_REMPTY_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear RX_FIFO_WOVF_INT."] + #[inline(always)] + #[must_use] + pub fn rx_fifo_wovf_int_clr(&mut self) -> RX_FIFO_WOVF_INT_CLR_W { + RX_FIFO_WOVF_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear TX_EOF_INT."] + #[inline(always)] + #[must_use] + pub fn tx_eof_int_clr(&mut self) -> TX_EOF_INT_CLR_W { + TX_EOF_INT_CLR_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel IO interrupt clear singal configuration register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/int_ena.rs b/esp32p4/src/parl_io/int_ena.rs new file mode 100644 index 0000000000..74f83e6bbf --- /dev/null +++ b/esp32p4/src/parl_io/int_ena.rs @@ -0,0 +1,104 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `TX_FIFO_REMPTY_INT_ENA` reader - Set this bit to enable TX_FIFO_REMPTY_INT."] +pub type TX_FIFO_REMPTY_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_FIFO_REMPTY_INT_ENA` writer - Set this bit to enable TX_FIFO_REMPTY_INT."] +pub type TX_FIFO_REMPTY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFO_WOVF_INT_ENA` reader - Set this bit to enable RX_FIFO_WOVF_INT."] +pub type RX_FIFO_WOVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `RX_FIFO_WOVF_INT_ENA` writer - Set this bit to enable RX_FIFO_WOVF_INT."] +pub type RX_FIFO_WOVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_EOF_INT_ENA` reader - Set this bit to enable TX_EOF_INT."] +pub type TX_EOF_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_EOF_INT_ENA` writer - Set this bit to enable TX_EOF_INT."] +pub type TX_EOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable TX_FIFO_REMPTY_INT."] + #[inline(always)] + pub fn tx_fifo_rempty_int_ena(&self) -> TX_FIFO_REMPTY_INT_ENA_R { + TX_FIFO_REMPTY_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to enable RX_FIFO_WOVF_INT."] + #[inline(always)] + pub fn rx_fifo_wovf_int_ena(&self) -> RX_FIFO_WOVF_INT_ENA_R { + RX_FIFO_WOVF_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to enable TX_EOF_INT."] + #[inline(always)] + pub fn tx_eof_int_ena(&self) -> TX_EOF_INT_ENA_R { + TX_EOF_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "tx_fifo_rempty_int_ena", + &format_args!("{}", self.tx_fifo_rempty_int_ena().bit()), + ) + .field( + "rx_fifo_wovf_int_ena", + &format_args!("{}", self.rx_fifo_wovf_int_ena().bit()), + ) + .field( + "tx_eof_int_ena", + &format_args!("{}", self.tx_eof_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable TX_FIFO_REMPTY_INT."] + #[inline(always)] + #[must_use] + pub fn tx_fifo_rempty_int_ena(&mut self) -> TX_FIFO_REMPTY_INT_ENA_W { + TX_FIFO_REMPTY_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to enable RX_FIFO_WOVF_INT."] + #[inline(always)] + #[must_use] + pub fn rx_fifo_wovf_int_ena(&mut self) -> RX_FIFO_WOVF_INT_ENA_W { + RX_FIFO_WOVF_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to enable TX_EOF_INT."] + #[inline(always)] + #[must_use] + pub fn tx_eof_int_ena(&mut self) -> TX_EOF_INT_ENA_W { + TX_EOF_INT_ENA_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel IO interrupt enable singal configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/int_raw.rs b/esp32p4/src/parl_io/int_raw.rs new file mode 100644 index 0000000000..561c2a6b50 --- /dev/null +++ b/esp32p4/src/parl_io/int_raw.rs @@ -0,0 +1,104 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `TX_FIFO_REMPTY_INT_RAW` reader - The raw interrupt status of TX_FIFO_REMPTY_INT."] +pub type TX_FIFO_REMPTY_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_FIFO_REMPTY_INT_RAW` writer - The raw interrupt status of TX_FIFO_REMPTY_INT."] +pub type TX_FIFO_REMPTY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FIFO_WOVF_INT_RAW` reader - The raw interrupt status of RX_FIFO_WOVF_INT."] +pub type RX_FIFO_WOVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_FIFO_WOVF_INT_RAW` writer - The raw interrupt status of RX_FIFO_WOVF_INT."] +pub type RX_FIFO_WOVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_EOF_INT_RAW` reader - The raw interrupt status of TX_EOF_INT."] +pub type TX_EOF_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_EOF_INT_RAW` writer - The raw interrupt status of TX_EOF_INT."] +pub type TX_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt status of TX_FIFO_REMPTY_INT."] + #[inline(always)] + pub fn tx_fifo_rempty_int_raw(&self) -> TX_FIFO_REMPTY_INT_RAW_R { + TX_FIFO_REMPTY_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status of RX_FIFO_WOVF_INT."] + #[inline(always)] + pub fn rx_fifo_wovf_int_raw(&self) -> RX_FIFO_WOVF_INT_RAW_R { + RX_FIFO_WOVF_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status of TX_EOF_INT."] + #[inline(always)] + pub fn tx_eof_int_raw(&self) -> TX_EOF_INT_RAW_R { + TX_EOF_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "tx_fifo_rempty_int_raw", + &format_args!("{}", self.tx_fifo_rempty_int_raw().bit()), + ) + .field( + "rx_fifo_wovf_int_raw", + &format_args!("{}", self.rx_fifo_wovf_int_raw().bit()), + ) + .field( + "tx_eof_int_raw", + &format_args!("{}", self.tx_eof_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt status of TX_FIFO_REMPTY_INT."] + #[inline(always)] + #[must_use] + pub fn tx_fifo_rempty_int_raw(&mut self) -> TX_FIFO_REMPTY_INT_RAW_W { + TX_FIFO_REMPTY_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt status of RX_FIFO_WOVF_INT."] + #[inline(always)] + #[must_use] + pub fn rx_fifo_wovf_int_raw(&mut self) -> RX_FIFO_WOVF_INT_RAW_W { + RX_FIFO_WOVF_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt status of TX_EOF_INT."] + #[inline(always)] + #[must_use] + pub fn tx_eof_int_raw(&mut self) -> TX_EOF_INT_RAW_W { + TX_EOF_INT_RAW_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel IO interrupt raw singal status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/int_st.rs b/esp32p4/src/parl_io/int_st.rs new file mode 100644 index 0000000000..1ddcb36699 --- /dev/null +++ b/esp32p4/src/parl_io/int_st.rs @@ -0,0 +1,61 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `TX_FIFO_REMPTY_INT_ST` reader - The masked interrupt status of TX_FIFO_REMPTY_INT."] +pub type TX_FIFO_REMPTY_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_FIFO_WOVF_INT_ST` reader - The masked interrupt status of RX_FIFO_WOVF_INT."] +pub type RX_FIFO_WOVF_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_EOF_INT_ST` reader - The masked interrupt status of TX_EOF_INT."] +pub type TX_EOF_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status of TX_FIFO_REMPTY_INT."] + #[inline(always)] + pub fn tx_fifo_rempty_int_st(&self) -> TX_FIFO_REMPTY_INT_ST_R { + TX_FIFO_REMPTY_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status of RX_FIFO_WOVF_INT."] + #[inline(always)] + pub fn rx_fifo_wovf_int_st(&self) -> RX_FIFO_WOVF_INT_ST_R { + RX_FIFO_WOVF_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status of TX_EOF_INT."] + #[inline(always)] + pub fn tx_eof_int_st(&self) -> TX_EOF_INT_ST_R { + TX_EOF_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "tx_fifo_rempty_int_st", + &format_args!("{}", self.tx_fifo_rempty_int_st().bit()), + ) + .field( + "rx_fifo_wovf_int_st", + &format_args!("{}", self.rx_fifo_wovf_int_st().bit()), + ) + .field( + "tx_eof_int_st", + &format_args!("{}", self.tx_eof_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Parallel IO interrupt singal status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/reg_update.rs b/esp32p4/src/parl_io/reg_update.rs new file mode 100644 index 0000000000..c73f002d05 --- /dev/null +++ b/esp32p4/src/parl_io/reg_update.rs @@ -0,0 +1,42 @@ +#[doc = "Register `REG_UPDATE` writer"] +pub type W = crate::W; +#[doc = "Field `RX_REG_UPDATE` writer - Set this bit to update rx register configuration."] +pub type RX_REG_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - Set this bit to update rx register configuration."] + #[inline(always)] + #[must_use] + pub fn rx_reg_update(&mut self) -> RX_REG_UPDATE_W { + RX_REG_UPDATE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel IO FIFO configuration register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_update::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_UPDATE_SPEC; +impl crate::RegisterSpec for REG_UPDATE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`reg_update::W`](W) writer structure"] +impl crate::Writable for REG_UPDATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_UPDATE to value 0"] +impl crate::Resettable for REG_UPDATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/rx_clk_cfg.rs b/esp32p4/src/parl_io/rx_clk_cfg.rs new file mode 100644 index 0000000000..225ba4f381 --- /dev/null +++ b/esp32p4/src/parl_io/rx_clk_cfg.rs @@ -0,0 +1,85 @@ +#[doc = "Register `RX_CLK_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CLK_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `RX_CLK_I_INV` reader - Set this bit to invert the input Rx core clock."] +pub type RX_CLK_I_INV_R = crate::BitReader; +#[doc = "Field `RX_CLK_I_INV` writer - Set this bit to invert the input Rx core clock."] +pub type RX_CLK_I_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CLK_O_INV` reader - Set this bit to invert the output Rx core clock."] +pub type RX_CLK_O_INV_R = crate::BitReader; +#[doc = "Field `RX_CLK_O_INV` writer - Set this bit to invert the output Rx core clock."] +pub type RX_CLK_O_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 30 - Set this bit to invert the input Rx core clock."] + #[inline(always)] + pub fn rx_clk_i_inv(&self) -> RX_CLK_I_INV_R { + RX_CLK_I_INV_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Set this bit to invert the output Rx core clock."] + #[inline(always)] + pub fn rx_clk_o_inv(&self) -> RX_CLK_O_INV_R { + RX_CLK_O_INV_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CLK_CFG") + .field( + "rx_clk_i_inv", + &format_args!("{}", self.rx_clk_i_inv().bit()), + ) + .field( + "rx_clk_o_inv", + &format_args!("{}", self.rx_clk_o_inv().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - Set this bit to invert the input Rx core clock."] + #[inline(always)] + #[must_use] + pub fn rx_clk_i_inv(&mut self) -> RX_CLK_I_INV_W { + RX_CLK_I_INV_W::new(self, 30) + } + #[doc = "Bit 31 - Set this bit to invert the output Rx core clock."] + #[inline(always)] + #[must_use] + pub fn rx_clk_o_inv(&mut self) -> RX_CLK_O_INV_W { + RX_CLK_O_INV_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel IO RX clk configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_clk_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_clk_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CLK_CFG_SPEC; +impl crate::RegisterSpec for RX_CLK_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_clk_cfg::R`](R) reader structure"] +impl crate::Readable for RX_CLK_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_clk_cfg::W`](W) writer structure"] +impl crate::Writable for RX_CLK_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CLK_CFG to value 0"] +impl crate::Resettable for RX_CLK_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/rx_data_cfg.rs b/esp32p4/src/parl_io/rx_data_cfg.rs new file mode 100644 index 0000000000..f684a71119 --- /dev/null +++ b/esp32p4/src/parl_io/rx_data_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `RX_DATA_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `RX_DATA_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `RX_BITLEN` reader - Configures expected byte number of received data."] +pub type RX_BITLEN_R = crate::FieldReader; +#[doc = "Field `RX_BITLEN` writer - Configures expected byte number of received data."] +pub type RX_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>; +#[doc = "Field `RX_DATA_ORDER_INV` reader - Set this bit to invert bit order of one byte sent from RX_FIFO to DMA."] +pub type RX_DATA_ORDER_INV_R = crate::BitReader; +#[doc = "Field `RX_DATA_ORDER_INV` writer - Set this bit to invert bit order of one byte sent from RX_FIFO to DMA."] +pub type RX_DATA_ORDER_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_BUS_WID_SEL` reader - Configures the rxd bus width. 3'd0: bus width is 1. 3'd1: bus width is 2. 3'd2: bus width is 4. 3'd3: bus width is 8."] +pub type RX_BUS_WID_SEL_R = crate::FieldReader; +#[doc = "Field `RX_BUS_WID_SEL` writer - Configures the rxd bus width. 3'd0: bus width is 1. 3'd1: bus width is 2. 3'd2: bus width is 4. 3'd3: bus width is 8."] +pub type RX_BUS_WID_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 9:27 - Configures expected byte number of received data."] + #[inline(always)] + pub fn rx_bitlen(&self) -> RX_BITLEN_R { + RX_BITLEN_R::new((self.bits >> 9) & 0x0007_ffff) + } + #[doc = "Bit 28 - Set this bit to invert bit order of one byte sent from RX_FIFO to DMA."] + #[inline(always)] + pub fn rx_data_order_inv(&self) -> RX_DATA_ORDER_INV_R { + RX_DATA_ORDER_INV_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bits 29:31 - Configures the rxd bus width. 3'd0: bus width is 1. 3'd1: bus width is 2. 3'd2: bus width is 4. 3'd3: bus width is 8."] + #[inline(always)] + pub fn rx_bus_wid_sel(&self) -> RX_BUS_WID_SEL_R { + RX_BUS_WID_SEL_R::new(((self.bits >> 29) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_DATA_CFG") + .field("rx_bitlen", &format_args!("{}", self.rx_bitlen().bits())) + .field( + "rx_data_order_inv", + &format_args!("{}", self.rx_data_order_inv().bit()), + ) + .field( + "rx_bus_wid_sel", + &format_args!("{}", self.rx_bus_wid_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 9:27 - Configures expected byte number of received data."] + #[inline(always)] + #[must_use] + pub fn rx_bitlen(&mut self) -> RX_BITLEN_W { + RX_BITLEN_W::new(self, 9) + } + #[doc = "Bit 28 - Set this bit to invert bit order of one byte sent from RX_FIFO to DMA."] + #[inline(always)] + #[must_use] + pub fn rx_data_order_inv(&mut self) -> RX_DATA_ORDER_INV_W { + RX_DATA_ORDER_INV_W::new(self, 28) + } + #[doc = "Bits 29:31 - Configures the rxd bus width. 3'd0: bus width is 1. 3'd1: bus width is 2. 3'd2: bus width is 4. 3'd3: bus width is 8."] + #[inline(always)] + #[must_use] + pub fn rx_bus_wid_sel(&mut self) -> RX_BUS_WID_SEL_W { + RX_BUS_WID_SEL_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel RX data configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_data_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_data_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_DATA_CFG_SPEC; +impl crate::RegisterSpec for RX_DATA_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_data_cfg::R`](R) reader structure"] +impl crate::Readable for RX_DATA_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_data_cfg::W`](W) writer structure"] +impl crate::Writable for RX_DATA_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_DATA_CFG to value 0x6000_0000"] +impl crate::Resettable for RX_DATA_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x6000_0000; +} diff --git a/esp32p4/src/parl_io/rx_genrl_cfg.rs b/esp32p4/src/parl_io/rx_genrl_cfg.rs new file mode 100644 index 0000000000..3472026d4a --- /dev/null +++ b/esp32p4/src/parl_io/rx_genrl_cfg.rs @@ -0,0 +1,123 @@ +#[doc = "Register `RX_GENRL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `RX_GENRL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `RX_GATING_EN` reader - Set this bit to enable the clock gating of output rx clock."] +pub type RX_GATING_EN_R = crate::BitReader; +#[doc = "Field `RX_GATING_EN` writer - Set this bit to enable the clock gating of output rx clock."] +pub type RX_GATING_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TIMEOUT_THRES` reader - Configures threshold of timeout counter."] +pub type RX_TIMEOUT_THRES_R = crate::FieldReader; +#[doc = "Field `RX_TIMEOUT_THRES` writer - Configures threshold of timeout counter."] +pub type RX_TIMEOUT_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `RX_TIMEOUT_EN` reader - Set this bit to enable timeout function to generate error eof."] +pub type RX_TIMEOUT_EN_R = crate::BitReader; +#[doc = "Field `RX_TIMEOUT_EN` writer - Set this bit to enable timeout function to generate error eof."] +pub type RX_TIMEOUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_EOF_GEN_SEL` reader - Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by external enable signal."] +pub type RX_EOF_GEN_SEL_R = crate::BitReader; +#[doc = "Field `RX_EOF_GEN_SEL` writer - Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by external enable signal."] +pub type RX_EOF_GEN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 12 - Set this bit to enable the clock gating of output rx clock."] + #[inline(always)] + pub fn rx_gating_en(&self) -> RX_GATING_EN_R { + RX_GATING_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:28 - Configures threshold of timeout counter."] + #[inline(always)] + pub fn rx_timeout_thres(&self) -> RX_TIMEOUT_THRES_R { + RX_TIMEOUT_THRES_R::new(((self.bits >> 13) & 0xffff) as u16) + } + #[doc = "Bit 29 - Set this bit to enable timeout function to generate error eof."] + #[inline(always)] + pub fn rx_timeout_en(&self) -> RX_TIMEOUT_EN_R { + RX_TIMEOUT_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by external enable signal."] + #[inline(always)] + pub fn rx_eof_gen_sel(&self) -> RX_EOF_GEN_SEL_R { + RX_EOF_GEN_SEL_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_GENRL_CFG") + .field( + "rx_gating_en", + &format_args!("{}", self.rx_gating_en().bit()), + ) + .field( + "rx_timeout_thres", + &format_args!("{}", self.rx_timeout_thres().bits()), + ) + .field( + "rx_timeout_en", + &format_args!("{}", self.rx_timeout_en().bit()), + ) + .field( + "rx_eof_gen_sel", + &format_args!("{}", self.rx_eof_gen_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 12 - Set this bit to enable the clock gating of output rx clock."] + #[inline(always)] + #[must_use] + pub fn rx_gating_en(&mut self) -> RX_GATING_EN_W { + RX_GATING_EN_W::new(self, 12) + } + #[doc = "Bits 13:28 - Configures threshold of timeout counter."] + #[inline(always)] + #[must_use] + pub fn rx_timeout_thres(&mut self) -> RX_TIMEOUT_THRES_W { + RX_TIMEOUT_THRES_W::new(self, 13) + } + #[doc = "Bit 29 - Set this bit to enable timeout function to generate error eof."] + #[inline(always)] + #[must_use] + pub fn rx_timeout_en(&mut self) -> RX_TIMEOUT_EN_W { + RX_TIMEOUT_EN_W::new(self, 29) + } + #[doc = "Bit 30 - Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by external enable signal."] + #[inline(always)] + #[must_use] + pub fn rx_eof_gen_sel(&mut self) -> RX_EOF_GEN_SEL_W { + RX_EOF_GEN_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel RX general configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_genrl_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_genrl_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_GENRL_CFG_SPEC; +impl crate::RegisterSpec for RX_GENRL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_genrl_cfg::R`](R) reader structure"] +impl crate::Readable for RX_GENRL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_genrl_cfg::W`](W) writer structure"] +impl crate::Writable for RX_GENRL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_GENRL_CFG to value 0x21ff_e000"] +impl crate::Resettable for RX_GENRL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x21ff_e000; +} diff --git a/esp32p4/src/parl_io/rx_mode_cfg.rs b/esp32p4/src/parl_io/rx_mode_cfg.rs new file mode 100644 index 0000000000..540ee651d8 --- /dev/null +++ b/esp32p4/src/parl_io/rx_mode_cfg.rs @@ -0,0 +1,139 @@ +#[doc = "Register `RX_MODE_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `RX_MODE_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `RX_EXT_EN_SEL` reader - Configures rx external enable signal selection from IO PAD."] +pub type RX_EXT_EN_SEL_R = crate::FieldReader; +#[doc = "Field `RX_EXT_EN_SEL` writer - Configures rx external enable signal selection from IO PAD."] +pub type RX_EXT_EN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RX_SW_EN` reader - Set this bit to enable data sampling by software."] +pub type RX_SW_EN_R = crate::BitReader; +#[doc = "Field `RX_SW_EN` writer - Set this bit to enable data sampling by software."] +pub type RX_SW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_EXT_EN_INV` reader - Set this bit to invert the external enable signal."] +pub type RX_EXT_EN_INV_R = crate::BitReader; +#[doc = "Field `RX_EXT_EN_INV` writer - Set this bit to invert the external enable signal."] +pub type RX_EXT_EN_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PULSE_SUBMODE_SEL` reader - Configures the rxd pulse sampling submode. 4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) 4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) 4'd4: positive pulse start(data bit included) && length end 4'd5: positive pulse start(data bit excluded) && length end"] +pub type RX_PULSE_SUBMODE_SEL_R = crate::FieldReader; +#[doc = "Field `RX_PULSE_SUBMODE_SEL` writer - Configures the rxd pulse sampling submode. 4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) 4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) 4'd4: positive pulse start(data bit included) && length end 4'd5: positive pulse start(data bit excluded) && length end"] +pub type RX_PULSE_SUBMODE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `RX_SMP_MODE_SEL` reader - Configures the rxd sampling mode. 2'b00: external level enable mode 2'b01: external pulse enable mode 2'b10: internal software enable mode"] +pub type RX_SMP_MODE_SEL_R = crate::FieldReader; +#[doc = "Field `RX_SMP_MODE_SEL` writer - Configures the rxd sampling mode. 2'b00: external level enable mode 2'b01: external pulse enable mode 2'b10: internal software enable mode"] +pub type RX_SMP_MODE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 21:24 - Configures rx external enable signal selection from IO PAD."] + #[inline(always)] + pub fn rx_ext_en_sel(&self) -> RX_EXT_EN_SEL_R { + RX_EXT_EN_SEL_R::new(((self.bits >> 21) & 0x0f) as u8) + } + #[doc = "Bit 25 - Set this bit to enable data sampling by software."] + #[inline(always)] + pub fn rx_sw_en(&self) -> RX_SW_EN_R { + RX_SW_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to invert the external enable signal."] + #[inline(always)] + pub fn rx_ext_en_inv(&self) -> RX_EXT_EN_INV_R { + RX_EXT_EN_INV_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bits 27:29 - Configures the rxd pulse sampling submode. 4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) 4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) 4'd4: positive pulse start(data bit included) && length end 4'd5: positive pulse start(data bit excluded) && length end"] + #[inline(always)] + pub fn rx_pulse_submode_sel(&self) -> RX_PULSE_SUBMODE_SEL_R { + RX_PULSE_SUBMODE_SEL_R::new(((self.bits >> 27) & 7) as u8) + } + #[doc = "Bits 30:31 - Configures the rxd sampling mode. 2'b00: external level enable mode 2'b01: external pulse enable mode 2'b10: internal software enable mode"] + #[inline(always)] + pub fn rx_smp_mode_sel(&self) -> RX_SMP_MODE_SEL_R { + RX_SMP_MODE_SEL_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_MODE_CFG") + .field( + "rx_ext_en_sel", + &format_args!("{}", self.rx_ext_en_sel().bits()), + ) + .field("rx_sw_en", &format_args!("{}", self.rx_sw_en().bit())) + .field( + "rx_ext_en_inv", + &format_args!("{}", self.rx_ext_en_inv().bit()), + ) + .field( + "rx_pulse_submode_sel", + &format_args!("{}", self.rx_pulse_submode_sel().bits()), + ) + .field( + "rx_smp_mode_sel", + &format_args!("{}", self.rx_smp_mode_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 21:24 - Configures rx external enable signal selection from IO PAD."] + #[inline(always)] + #[must_use] + pub fn rx_ext_en_sel(&mut self) -> RX_EXT_EN_SEL_W { + RX_EXT_EN_SEL_W::new(self, 21) + } + #[doc = "Bit 25 - Set this bit to enable data sampling by software."] + #[inline(always)] + #[must_use] + pub fn rx_sw_en(&mut self) -> RX_SW_EN_W { + RX_SW_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to invert the external enable signal."] + #[inline(always)] + #[must_use] + pub fn rx_ext_en_inv(&mut self) -> RX_EXT_EN_INV_W { + RX_EXT_EN_INV_W::new(self, 26) + } + #[doc = "Bits 27:29 - Configures the rxd pulse sampling submode. 4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) 4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) 4'd4: positive pulse start(data bit included) && length end 4'd5: positive pulse start(data bit excluded) && length end"] + #[inline(always)] + #[must_use] + pub fn rx_pulse_submode_sel(&mut self) -> RX_PULSE_SUBMODE_SEL_W { + RX_PULSE_SUBMODE_SEL_W::new(self, 27) + } + #[doc = "Bits 30:31 - Configures the rxd sampling mode. 2'b00: external level enable mode 2'b01: external pulse enable mode 2'b10: internal software enable mode"] + #[inline(always)] + #[must_use] + pub fn rx_smp_mode_sel(&mut self) -> RX_SMP_MODE_SEL_W { + RX_SMP_MODE_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel RX Sampling mode configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_mode_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_mode_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_MODE_CFG_SPEC; +impl crate::RegisterSpec for RX_MODE_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_mode_cfg::R`](R) reader structure"] +impl crate::Readable for RX_MODE_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_mode_cfg::W`](W) writer structure"] +impl crate::Writable for RX_MODE_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_MODE_CFG to value 0x00e0_0000"] +impl crate::Resettable for RX_MODE_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x00e0_0000; +} diff --git a/esp32p4/src/parl_io/rx_st0.rs b/esp32p4/src/parl_io/rx_st0.rs new file mode 100644 index 0000000000..4e6397238c --- /dev/null +++ b/esp32p4/src/parl_io/rx_st0.rs @@ -0,0 +1,47 @@ +#[doc = "Register `RX_ST0` reader"] +pub type R = crate::R; +#[doc = "Field `RX_CNT` reader - Indicates the cycle number of reading Rx FIFO."] +pub type RX_CNT_R = crate::FieldReader; +#[doc = "Field `RX_FIFO_WR_BIT_CNT` reader - Indicates the current written bit number into Rx FIFO."] +pub type RX_FIFO_WR_BIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 8:12 - Indicates the cycle number of reading Rx FIFO."] + #[inline(always)] + pub fn rx_cnt(&self) -> RX_CNT_R { + RX_CNT_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:31 - Indicates the current written bit number into Rx FIFO."] + #[inline(always)] + pub fn rx_fifo_wr_bit_cnt(&self) -> RX_FIFO_WR_BIT_CNT_R { + RX_FIFO_WR_BIT_CNT_R::new((self.bits >> 13) & 0x0007_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_ST0") + .field("rx_cnt", &format_args!("{}", self.rx_cnt().bits())) + .field( + "rx_fifo_wr_bit_cnt", + &format_args!("{}", self.rx_fifo_wr_bit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Parallel IO RX status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_st0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_ST0_SPEC; +impl crate::RegisterSpec for RX_ST0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_st0::R`](R) reader structure"] +impl crate::Readable for RX_ST0_SPEC {} +#[doc = "`reset()` method sets RX_ST0 to value 0"] +impl crate::Resettable for RX_ST0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/rx_st1.rs b/esp32p4/src/parl_io/rx_st1.rs new file mode 100644 index 0000000000..99c60d5f5b --- /dev/null +++ b/esp32p4/src/parl_io/rx_st1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RX_ST1` reader"] +pub type R = crate::R; +#[doc = "Field `RX_FIFO_RD_BIT_CNT` reader - Indicates the current read bit number from Rx FIFO."] +pub type RX_FIFO_RD_BIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 13:31 - Indicates the current read bit number from Rx FIFO."] + #[inline(always)] + pub fn rx_fifo_rd_bit_cnt(&self) -> RX_FIFO_RD_BIT_CNT_R { + RX_FIFO_RD_BIT_CNT_R::new((self.bits >> 13) & 0x0007_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_ST1") + .field( + "rx_fifo_rd_bit_cnt", + &format_args!("{}", self.rx_fifo_rd_bit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Parallel IO RX status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_st1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_ST1_SPEC; +impl crate::RegisterSpec for RX_ST1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_st1::R`](R) reader structure"] +impl crate::Readable for RX_ST1_SPEC {} +#[doc = "`reset()` method sets RX_ST1 to value 0"] +impl crate::Resettable for RX_ST1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/rx_start_cfg.rs b/esp32p4/src/parl_io/rx_start_cfg.rs new file mode 100644 index 0000000000..34887a0548 --- /dev/null +++ b/esp32p4/src/parl_io/rx_start_cfg.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RX_START_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `RX_START_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `RX_START` reader - Set this bit to start rx data sampling."] +pub type RX_START_R = crate::BitReader; +#[doc = "Field `RX_START` writer - Set this bit to start rx data sampling."] +pub type RX_START_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - Set this bit to start rx data sampling."] + #[inline(always)] + pub fn rx_start(&self) -> RX_START_R { + RX_START_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_START_CFG") + .field("rx_start", &format_args!("{}", self.rx_start().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - Set this bit to start rx data sampling."] + #[inline(always)] + #[must_use] + pub fn rx_start(&mut self) -> RX_START_W { + RX_START_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel RX Start configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_start_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_start_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_START_CFG_SPEC; +impl crate::RegisterSpec for RX_START_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_start_cfg::R`](R) reader structure"] +impl crate::Readable for RX_START_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_start_cfg::W`](W) writer structure"] +impl crate::Writable for RX_START_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_START_CFG to value 0"] +impl crate::Resettable for RX_START_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/st.rs b/esp32p4/src/parl_io/st.rs new file mode 100644 index 0000000000..c4f952859d --- /dev/null +++ b/esp32p4/src/parl_io/st.rs @@ -0,0 +1,36 @@ +#[doc = "Register `ST` reader"] +pub type R = crate::R; +#[doc = "Field `TX_READY` reader - Represents the status that tx is ready to transmit."] +pub type TX_READY_R = crate::BitReader; +impl R { + #[doc = "Bit 31 - Represents the status that tx is ready to transmit."] + #[inline(always)] + pub fn tx_ready(&self) -> TX_READY_R { + TX_READY_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ST") + .field("tx_ready", &format_args!("{}", self.tx_ready().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Parallel IO module status register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ST_SPEC; +impl crate::RegisterSpec for ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`st::R`](R) reader structure"] +impl crate::Readable for ST_SPEC {} +#[doc = "`reset()` method sets ST to value 0"] +impl crate::Resettable for ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/tx_clk_cfg.rs b/esp32p4/src/parl_io/tx_clk_cfg.rs new file mode 100644 index 0000000000..2624b6eccb --- /dev/null +++ b/esp32p4/src/parl_io/tx_clk_cfg.rs @@ -0,0 +1,85 @@ +#[doc = "Register `TX_CLK_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CLK_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `TX_CLK_I_INV` reader - Set this bit to invert the input Tx core clock."] +pub type TX_CLK_I_INV_R = crate::BitReader; +#[doc = "Field `TX_CLK_I_INV` writer - Set this bit to invert the input Tx core clock."] +pub type TX_CLK_I_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CLK_O_INV` reader - Set this bit to invert the output Tx core clock."] +pub type TX_CLK_O_INV_R = crate::BitReader; +#[doc = "Field `TX_CLK_O_INV` writer - Set this bit to invert the output Tx core clock."] +pub type TX_CLK_O_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 30 - Set this bit to invert the input Tx core clock."] + #[inline(always)] + pub fn tx_clk_i_inv(&self) -> TX_CLK_I_INV_R { + TX_CLK_I_INV_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Set this bit to invert the output Tx core clock."] + #[inline(always)] + pub fn tx_clk_o_inv(&self) -> TX_CLK_O_INV_R { + TX_CLK_O_INV_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CLK_CFG") + .field( + "tx_clk_i_inv", + &format_args!("{}", self.tx_clk_i_inv().bit()), + ) + .field( + "tx_clk_o_inv", + &format_args!("{}", self.tx_clk_o_inv().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - Set this bit to invert the input Tx core clock."] + #[inline(always)] + #[must_use] + pub fn tx_clk_i_inv(&mut self) -> TX_CLK_I_INV_W { + TX_CLK_I_INV_W::new(self, 30) + } + #[doc = "Bit 31 - Set this bit to invert the output Tx core clock."] + #[inline(always)] + #[must_use] + pub fn tx_clk_o_inv(&mut self) -> TX_CLK_O_INV_W { + TX_CLK_O_INV_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel IO TX clk configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_clk_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_clk_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CLK_CFG_SPEC; +impl crate::RegisterSpec for TX_CLK_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_clk_cfg::R`](R) reader structure"] +impl crate::Readable for TX_CLK_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_clk_cfg::W`](W) writer structure"] +impl crate::Writable for TX_CLK_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CLK_CFG to value 0"] +impl crate::Resettable for TX_CLK_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/tx_data_cfg.rs b/esp32p4/src/parl_io/tx_data_cfg.rs new file mode 100644 index 0000000000..06d19d780c --- /dev/null +++ b/esp32p4/src/parl_io/tx_data_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `TX_DATA_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `TX_DATA_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `TX_BITLEN` reader - Configures expected byte number of sent data."] +pub type TX_BITLEN_R = crate::FieldReader; +#[doc = "Field `TX_BITLEN` writer - Configures expected byte number of sent data."] +pub type TX_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>; +#[doc = "Field `TX_DATA_ORDER_INV` reader - Set this bit to invert bit order of one byte sent from TX_FIFO to IO data."] +pub type TX_DATA_ORDER_INV_R = crate::BitReader; +#[doc = "Field `TX_DATA_ORDER_INV` writer - Set this bit to invert bit order of one byte sent from TX_FIFO to IO data."] +pub type TX_DATA_ORDER_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BUS_WID_SEL` reader - Configures the txd bus width. 3'd0: bus width is 1. 3'd1: bus width is 2. 3'd2: bus width is 4. 3'd3: bus width is 8."] +pub type TX_BUS_WID_SEL_R = crate::FieldReader; +#[doc = "Field `TX_BUS_WID_SEL` writer - Configures the txd bus width. 3'd0: bus width is 1. 3'd1: bus width is 2. 3'd2: bus width is 4. 3'd3: bus width is 8."] +pub type TX_BUS_WID_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 9:27 - Configures expected byte number of sent data."] + #[inline(always)] + pub fn tx_bitlen(&self) -> TX_BITLEN_R { + TX_BITLEN_R::new((self.bits >> 9) & 0x0007_ffff) + } + #[doc = "Bit 28 - Set this bit to invert bit order of one byte sent from TX_FIFO to IO data."] + #[inline(always)] + pub fn tx_data_order_inv(&self) -> TX_DATA_ORDER_INV_R { + TX_DATA_ORDER_INV_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bits 29:31 - Configures the txd bus width. 3'd0: bus width is 1. 3'd1: bus width is 2. 3'd2: bus width is 4. 3'd3: bus width is 8."] + #[inline(always)] + pub fn tx_bus_wid_sel(&self) -> TX_BUS_WID_SEL_R { + TX_BUS_WID_SEL_R::new(((self.bits >> 29) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_DATA_CFG") + .field("tx_bitlen", &format_args!("{}", self.tx_bitlen().bits())) + .field( + "tx_data_order_inv", + &format_args!("{}", self.tx_data_order_inv().bit()), + ) + .field( + "tx_bus_wid_sel", + &format_args!("{}", self.tx_bus_wid_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 9:27 - Configures expected byte number of sent data."] + #[inline(always)] + #[must_use] + pub fn tx_bitlen(&mut self) -> TX_BITLEN_W { + TX_BITLEN_W::new(self, 9) + } + #[doc = "Bit 28 - Set this bit to invert bit order of one byte sent from TX_FIFO to IO data."] + #[inline(always)] + #[must_use] + pub fn tx_data_order_inv(&mut self) -> TX_DATA_ORDER_INV_W { + TX_DATA_ORDER_INV_W::new(self, 28) + } + #[doc = "Bits 29:31 - Configures the txd bus width. 3'd0: bus width is 1. 3'd1: bus width is 2. 3'd2: bus width is 4. 3'd3: bus width is 8."] + #[inline(always)] + #[must_use] + pub fn tx_bus_wid_sel(&mut self) -> TX_BUS_WID_SEL_W { + TX_BUS_WID_SEL_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel TX data configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_data_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_data_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_DATA_CFG_SPEC; +impl crate::RegisterSpec for TX_DATA_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_data_cfg::R`](R) reader structure"] +impl crate::Readable for TX_DATA_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_data_cfg::W`](W) writer structure"] +impl crate::Writable for TX_DATA_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_DATA_CFG to value 0x6000_0000"] +impl crate::Resettable for TX_DATA_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x6000_0000; +} diff --git a/esp32p4/src/parl_io/tx_genrl_cfg.rs b/esp32p4/src/parl_io/tx_genrl_cfg.rs new file mode 100644 index 0000000000..32293b6744 --- /dev/null +++ b/esp32p4/src/parl_io/tx_genrl_cfg.rs @@ -0,0 +1,123 @@ +#[doc = "Register `TX_GENRL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `TX_GENRL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `TX_EOF_GEN_SEL` reader - Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by DMA eof."] +pub type TX_EOF_GEN_SEL_R = crate::BitReader; +#[doc = "Field `TX_EOF_GEN_SEL` writer - Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by DMA eof."] +pub type TX_EOF_GEN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_IDLE_VALUE` reader - Configures bus value of transmitter in IDLE state."] +pub type TX_IDLE_VALUE_R = crate::FieldReader; +#[doc = "Field `TX_IDLE_VALUE` writer - Configures bus value of transmitter in IDLE state."] +pub type TX_IDLE_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `TX_GATING_EN` reader - Set this bit to enable the clock gating of output tx clock."] +pub type TX_GATING_EN_R = crate::BitReader; +#[doc = "Field `TX_GATING_EN` writer - Set this bit to enable the clock gating of output tx clock."] +pub type TX_GATING_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_VALID_OUTPUT_EN` reader - Set this bit to enable the output of tx data valid signal."] +pub type TX_VALID_OUTPUT_EN_R = crate::BitReader; +#[doc = "Field `TX_VALID_OUTPUT_EN` writer - Set this bit to enable the output of tx data valid signal."] +pub type TX_VALID_OUTPUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 13 - Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by DMA eof."] + #[inline(always)] + pub fn tx_eof_gen_sel(&self) -> TX_EOF_GEN_SEL_R { + TX_EOF_GEN_SEL_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:29 - Configures bus value of transmitter in IDLE state."] + #[inline(always)] + pub fn tx_idle_value(&self) -> TX_IDLE_VALUE_R { + TX_IDLE_VALUE_R::new(((self.bits >> 14) & 0xffff) as u16) + } + #[doc = "Bit 30 - Set this bit to enable the clock gating of output tx clock."] + #[inline(always)] + pub fn tx_gating_en(&self) -> TX_GATING_EN_R { + TX_GATING_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Set this bit to enable the output of tx data valid signal."] + #[inline(always)] + pub fn tx_valid_output_en(&self) -> TX_VALID_OUTPUT_EN_R { + TX_VALID_OUTPUT_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_GENRL_CFG") + .field( + "tx_eof_gen_sel", + &format_args!("{}", self.tx_eof_gen_sel().bit()), + ) + .field( + "tx_idle_value", + &format_args!("{}", self.tx_idle_value().bits()), + ) + .field( + "tx_gating_en", + &format_args!("{}", self.tx_gating_en().bit()), + ) + .field( + "tx_valid_output_en", + &format_args!("{}", self.tx_valid_output_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 13 - Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by DMA eof."] + #[inline(always)] + #[must_use] + pub fn tx_eof_gen_sel(&mut self) -> TX_EOF_GEN_SEL_W { + TX_EOF_GEN_SEL_W::new(self, 13) + } + #[doc = "Bits 14:29 - Configures bus value of transmitter in IDLE state."] + #[inline(always)] + #[must_use] + pub fn tx_idle_value(&mut self) -> TX_IDLE_VALUE_W { + TX_IDLE_VALUE_W::new(self, 14) + } + #[doc = "Bit 30 - Set this bit to enable the clock gating of output tx clock."] + #[inline(always)] + #[must_use] + pub fn tx_gating_en(&mut self) -> TX_GATING_EN_W { + TX_GATING_EN_W::new(self, 30) + } + #[doc = "Bit 31 - Set this bit to enable the output of tx data valid signal."] + #[inline(always)] + #[must_use] + pub fn tx_valid_output_en(&mut self) -> TX_VALID_OUTPUT_EN_W { + TX_VALID_OUTPUT_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel TX general configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_genrl_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_genrl_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_GENRL_CFG_SPEC; +impl crate::RegisterSpec for TX_GENRL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_genrl_cfg::R`](R) reader structure"] +impl crate::Readable for TX_GENRL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_genrl_cfg::W`](W) writer structure"] +impl crate::Writable for TX_GENRL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_GENRL_CFG to value 0"] +impl crate::Resettable for TX_GENRL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/tx_st0.rs b/esp32p4/src/parl_io/tx_st0.rs new file mode 100644 index 0000000000..e6f2e5790b --- /dev/null +++ b/esp32p4/src/parl_io/tx_st0.rs @@ -0,0 +1,47 @@ +#[doc = "Register `TX_ST0` reader"] +pub type R = crate::R; +#[doc = "Field `TX_CNT` reader - Indicates the cycle number of reading Tx FIFO."] +pub type TX_CNT_R = crate::FieldReader; +#[doc = "Field `TX_FIFO_RD_BIT_CNT` reader - Indicates the current read bit number from Tx FIFO."] +pub type TX_FIFO_RD_BIT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 6:12 - Indicates the cycle number of reading Tx FIFO."] + #[inline(always)] + pub fn tx_cnt(&self) -> TX_CNT_R { + TX_CNT_R::new(((self.bits >> 6) & 0x7f) as u8) + } + #[doc = "Bits 13:31 - Indicates the current read bit number from Tx FIFO."] + #[inline(always)] + pub fn tx_fifo_rd_bit_cnt(&self) -> TX_FIFO_RD_BIT_CNT_R { + TX_FIFO_RD_BIT_CNT_R::new((self.bits >> 13) & 0x0007_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_ST0") + .field("tx_cnt", &format_args!("{}", self.tx_cnt().bits())) + .field( + "tx_fifo_rd_bit_cnt", + &format_args!("{}", self.tx_fifo_rd_bit_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Parallel IO TX status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_st0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_ST0_SPEC; +impl crate::RegisterSpec for TX_ST0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_st0::R`](R) reader structure"] +impl crate::Readable for TX_ST0_SPEC {} +#[doc = "`reset()` method sets TX_ST0 to value 0"] +impl crate::Resettable for TX_ST0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/tx_start_cfg.rs b/esp32p4/src/parl_io/tx_start_cfg.rs new file mode 100644 index 0000000000..40dcfb9394 --- /dev/null +++ b/esp32p4/src/parl_io/tx_start_cfg.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TX_START_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `TX_START_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `TX_START` reader - Set this bit to start tx data transmit."] +pub type TX_START_R = crate::BitReader; +#[doc = "Field `TX_START` writer - Set this bit to start tx data transmit."] +pub type TX_START_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - Set this bit to start tx data transmit."] + #[inline(always)] + pub fn tx_start(&self) -> TX_START_R { + TX_START_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_START_CFG") + .field("tx_start", &format_args!("{}", self.tx_start().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - Set this bit to start tx data transmit."] + #[inline(always)] + #[must_use] + pub fn tx_start(&mut self) -> TX_START_W { + TX_START_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Parallel TX Start configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_start_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_start_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_START_CFG_SPEC; +impl crate::RegisterSpec for TX_START_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_start_cfg::R`](R) reader structure"] +impl crate::Readable for TX_START_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_start_cfg::W`](W) writer structure"] +impl crate::Writable for TX_START_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_START_CFG to value 0"] +impl crate::Resettable for TX_START_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/parl_io/version.rs b/esp32p4/src/parl_io/version.rs new file mode 100644 index 0000000000..02b8acb4ad --- /dev/null +++ b/esp32p4/src/parl_io/version.rs @@ -0,0 +1,63 @@ +#[doc = "Register `VERSION` reader"] +pub type R = crate::R; +#[doc = "Register `VERSION` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - Version of this register file"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - Version of this register file"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Version of this register file"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VERSION") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Version of this register file"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VERSION_SPEC; +impl crate::RegisterSpec for VERSION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`version::R`](R) reader structure"] +impl crate::Readable for VERSION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"] +impl crate::Writable for VERSION_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VERSION to value 0x0221_2260"] +impl crate::Resettable for VERSION_SPEC { + const RESET_VALUE: Self::Ux = 0x0221_2260; +} diff --git a/esp32p4/src/pau.rs b/esp32p4/src/pau.rs new file mode 100644 index 0000000000..6e5914db3a --- /dev/null +++ b/esp32p4/src/pau.rs @@ -0,0 +1,179 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + regdma_conf: REGDMA_CONF, + regdma_clk_conf: REGDMA_CLK_CONF, + regdma_etm_ctrl: REGDMA_ETM_CTRL, + regdma_link_0_addr: REGDMA_LINK_0_ADDR, + regdma_link_1_addr: REGDMA_LINK_1_ADDR, + regdma_link_2_addr: REGDMA_LINK_2_ADDR, + regdma_link_3_addr: REGDMA_LINK_3_ADDR, + regdma_link_mac_addr: REGDMA_LINK_MAC_ADDR, + regdma_current_link_addr: REGDMA_CURRENT_LINK_ADDR, + regdma_backup_addr: REGDMA_BACKUP_ADDR, + regdma_mem_addr: REGDMA_MEM_ADDR, + regdma_bkp_conf: REGDMA_BKP_CONF, + int_ena: INT_ENA, + int_raw: INT_RAW, + int_clr: INT_CLR, + int_st: INT_ST, + _reserved16: [u8; 0x03bc], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - Peri backup control register"] + #[inline(always)] + pub const fn regdma_conf(&self) -> ®DMA_CONF { + &self.regdma_conf + } + #[doc = "0x04 - Clock control register"] + #[inline(always)] + pub const fn regdma_clk_conf(&self) -> ®DMA_CLK_CONF { + &self.regdma_clk_conf + } + #[doc = "0x08 - ETM start ctrl reg"] + #[inline(always)] + pub const fn regdma_etm_ctrl(&self) -> ®DMA_ETM_CTRL { + &self.regdma_etm_ctrl + } + #[doc = "0x0c - link_0_addr"] + #[inline(always)] + pub const fn regdma_link_0_addr(&self) -> ®DMA_LINK_0_ADDR { + &self.regdma_link_0_addr + } + #[doc = "0x10 - Link_1_addr"] + #[inline(always)] + pub const fn regdma_link_1_addr(&self) -> ®DMA_LINK_1_ADDR { + &self.regdma_link_1_addr + } + #[doc = "0x14 - Link_2_addr"] + #[inline(always)] + pub const fn regdma_link_2_addr(&self) -> ®DMA_LINK_2_ADDR { + &self.regdma_link_2_addr + } + #[doc = "0x18 - Link_3_addr"] + #[inline(always)] + pub const fn regdma_link_3_addr(&self) -> ®DMA_LINK_3_ADDR { + &self.regdma_link_3_addr + } + #[doc = "0x1c - Link_mac_addr"] + #[inline(always)] + pub const fn regdma_link_mac_addr(&self) -> ®DMA_LINK_MAC_ADDR { + &self.regdma_link_mac_addr + } + #[doc = "0x20 - current link addr"] + #[inline(always)] + pub const fn regdma_current_link_addr(&self) -> ®DMA_CURRENT_LINK_ADDR { + &self.regdma_current_link_addr + } + #[doc = "0x24 - Backup addr"] + #[inline(always)] + pub const fn regdma_backup_addr(&self) -> ®DMA_BACKUP_ADDR { + &self.regdma_backup_addr + } + #[doc = "0x28 - mem addr"] + #[inline(always)] + pub const fn regdma_mem_addr(&self) -> ®DMA_MEM_ADDR { + &self.regdma_mem_addr + } + #[doc = "0x2c - backup config"] + #[inline(always)] + pub const fn regdma_bkp_conf(&self) -> ®DMA_BKP_CONF { + &self.regdma_bkp_conf + } + #[doc = "0x30 - Read only register for error and done"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x34 - Read only register for error and done"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x38 - Read only register for error and done"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x3c - Read only register for error and done"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x3fc - Date register."] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "REGDMA_CONF (rw) register accessor: Peri backup control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_conf`] module"] +pub type REGDMA_CONF = crate::Reg; +#[doc = "Peri backup control register"] +pub mod regdma_conf; +#[doc = "REGDMA_CLK_CONF (rw) register accessor: Clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_clk_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_clk_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_clk_conf`] module"] +pub type REGDMA_CLK_CONF = crate::Reg; +#[doc = "Clock control register"] +pub mod regdma_clk_conf; +#[doc = "REGDMA_ETM_CTRL (w) register accessor: ETM start ctrl reg\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_etm_ctrl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_etm_ctrl`] module"] +pub type REGDMA_ETM_CTRL = crate::Reg; +#[doc = "ETM start ctrl reg"] +pub mod regdma_etm_ctrl; +#[doc = "REGDMA_LINK_0_ADDR (rw) register accessor: link_0_addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_link_0_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_link_0_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_link_0_addr`] module"] +pub type REGDMA_LINK_0_ADDR = crate::Reg; +#[doc = "link_0_addr"] +pub mod regdma_link_0_addr; +#[doc = "REGDMA_LINK_1_ADDR (rw) register accessor: Link_1_addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_link_1_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_link_1_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_link_1_addr`] module"] +pub type REGDMA_LINK_1_ADDR = crate::Reg; +#[doc = "Link_1_addr"] +pub mod regdma_link_1_addr; +#[doc = "REGDMA_LINK_2_ADDR (rw) register accessor: Link_2_addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_link_2_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_link_2_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_link_2_addr`] module"] +pub type REGDMA_LINK_2_ADDR = crate::Reg; +#[doc = "Link_2_addr"] +pub mod regdma_link_2_addr; +#[doc = "REGDMA_LINK_3_ADDR (rw) register accessor: Link_3_addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_link_3_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_link_3_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_link_3_addr`] module"] +pub type REGDMA_LINK_3_ADDR = crate::Reg; +#[doc = "Link_3_addr"] +pub mod regdma_link_3_addr; +#[doc = "REGDMA_LINK_MAC_ADDR (rw) register accessor: Link_mac_addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_link_mac_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_link_mac_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_link_mac_addr`] module"] +pub type REGDMA_LINK_MAC_ADDR = crate::Reg; +#[doc = "Link_mac_addr"] +pub mod regdma_link_mac_addr; +#[doc = "REGDMA_CURRENT_LINK_ADDR (r) register accessor: current link addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_current_link_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_current_link_addr`] module"] +pub type REGDMA_CURRENT_LINK_ADDR = + crate::Reg; +#[doc = "current link addr"] +pub mod regdma_current_link_addr; +#[doc = "REGDMA_BACKUP_ADDR (r) register accessor: Backup addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_backup_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_backup_addr`] module"] +pub type REGDMA_BACKUP_ADDR = crate::Reg; +#[doc = "Backup addr"] +pub mod regdma_backup_addr; +#[doc = "REGDMA_MEM_ADDR (r) register accessor: mem addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_mem_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_mem_addr`] module"] +pub type REGDMA_MEM_ADDR = crate::Reg; +#[doc = "mem addr"] +pub mod regdma_mem_addr; +#[doc = "REGDMA_BKP_CONF (rw) register accessor: backup config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_bkp_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_bkp_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regdma_bkp_conf`] module"] +pub type REGDMA_BKP_CONF = crate::Reg; +#[doc = "backup config"] +pub mod regdma_bkp_conf; +#[doc = "INT_ENA (rw) register accessor: Read only register for error and done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Read only register for error and done"] +pub mod int_ena; +#[doc = "INT_RAW (rw) register accessor: Read only register for error and done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Read only register for error and done"] +pub mod int_raw; +#[doc = "INT_CLR (w) register accessor: Read only register for error and done\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Read only register for error and done"] +pub mod int_clr; +#[doc = "INT_ST (r) register accessor: Read only register for error and done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Read only register for error and done"] +pub mod int_st; +#[doc = "DATE (rw) register accessor: Date register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Date register."] +pub mod date; diff --git a/esp32p4/src/pau/date.rs b/esp32p4/src/pau/date.rs new file mode 100644 index 0000000000..8601cb2a93 --- /dev/null +++ b/esp32p4/src/pau/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - REGDMA date information/ REGDMA version information."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - REGDMA date information/ REGDMA version information."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - REGDMA date information/ REGDMA version information."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - REGDMA date information/ REGDMA version information."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Date register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0220_3070"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_3070; +} diff --git a/esp32p4/src/pau/int_clr.rs b/esp32p4/src/pau/int_clr.rs new file mode 100644 index 0000000000..bfead19965 --- /dev/null +++ b/esp32p4/src/pau/int_clr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DONE_INT_CLR` writer - backup done flag"] +pub type DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_INT_CLR` writer - error flag"] +pub type ERROR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - backup done flag"] + #[inline(always)] + #[must_use] + pub fn done_int_clr(&mut self) -> DONE_INT_CLR_W { + DONE_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - error flag"] + #[inline(always)] + #[must_use] + pub fn error_int_clr(&mut self) -> ERROR_INT_CLR_W { + ERROR_INT_CLR_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Read only register for error and done\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/int_ena.rs b/esp32p4/src/pau/int_ena.rs new file mode 100644 index 0000000000..ba556bc472 --- /dev/null +++ b/esp32p4/src/pau/int_ena.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `DONE_INT_ENA` reader - backup done flag"] +pub type DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `DONE_INT_ENA` writer - backup done flag"] +pub type DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_INT_ENA` reader - error flag"] +pub type ERROR_INT_ENA_R = crate::BitReader; +#[doc = "Field `ERROR_INT_ENA` writer - error flag"] +pub type ERROR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - backup done flag"] + #[inline(always)] + pub fn done_int_ena(&self) -> DONE_INT_ENA_R { + DONE_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - error flag"] + #[inline(always)] + pub fn error_int_ena(&self) -> ERROR_INT_ENA_R { + ERROR_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "done_int_ena", + &format_args!("{}", self.done_int_ena().bit()), + ) + .field( + "error_int_ena", + &format_args!("{}", self.error_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - backup done flag"] + #[inline(always)] + #[must_use] + pub fn done_int_ena(&mut self) -> DONE_INT_ENA_W { + DONE_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - error flag"] + #[inline(always)] + #[must_use] + pub fn error_int_ena(&mut self) -> ERROR_INT_ENA_W { + ERROR_INT_ENA_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Read only register for error and done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/int_raw.rs b/esp32p4/src/pau/int_raw.rs new file mode 100644 index 0000000000..900d64f384 --- /dev/null +++ b/esp32p4/src/pau/int_raw.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `DONE_INT_RAW` reader - backup done flag"] +pub type DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `DONE_INT_RAW` writer - backup done flag"] +pub type DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_INT_RAW` reader - error flag"] +pub type ERROR_INT_RAW_R = crate::BitReader; +#[doc = "Field `ERROR_INT_RAW` writer - error flag"] +pub type ERROR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - backup done flag"] + #[inline(always)] + pub fn done_int_raw(&self) -> DONE_INT_RAW_R { + DONE_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - error flag"] + #[inline(always)] + pub fn error_int_raw(&self) -> ERROR_INT_RAW_R { + ERROR_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "done_int_raw", + &format_args!("{}", self.done_int_raw().bit()), + ) + .field( + "error_int_raw", + &format_args!("{}", self.error_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - backup done flag"] + #[inline(always)] + #[must_use] + pub fn done_int_raw(&mut self) -> DONE_INT_RAW_W { + DONE_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - error flag"] + #[inline(always)] + #[must_use] + pub fn error_int_raw(&mut self) -> ERROR_INT_RAW_W { + ERROR_INT_RAW_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Read only register for error and done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/int_st.rs b/esp32p4/src/pau/int_st.rs new file mode 100644 index 0000000000..b1eeae82f6 --- /dev/null +++ b/esp32p4/src/pau/int_st.rs @@ -0,0 +1,47 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `DONE_INT_ST` reader - backup done flag"] +pub type DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `ERROR_INT_ST` reader - error flag"] +pub type ERROR_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - backup done flag"] + #[inline(always)] + pub fn done_int_st(&self) -> DONE_INT_ST_R { + DONE_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - error flag"] + #[inline(always)] + pub fn error_int_st(&self) -> ERROR_INT_ST_R { + ERROR_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field("done_int_st", &format_args!("{}", self.done_int_st().bit())) + .field( + "error_int_st", + &format_args!("{}", self.error_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Read only register for error and done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/regdma_backup_addr.rs b/esp32p4/src/pau/regdma_backup_addr.rs new file mode 100644 index 0000000000..6e60ee407b --- /dev/null +++ b/esp32p4/src/pau/regdma_backup_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `REGDMA_BACKUP_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `BACKUP_ADDR` reader - backup addr reg"] +pub type BACKUP_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - backup addr reg"] + #[inline(always)] + pub fn backup_addr(&self) -> BACKUP_ADDR_R { + BACKUP_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGDMA_BACKUP_ADDR") + .field( + "backup_addr", + &format_args!("{}", self.backup_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Backup addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_backup_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_BACKUP_ADDR_SPEC; +impl crate::RegisterSpec for REGDMA_BACKUP_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regdma_backup_addr::R`](R) reader structure"] +impl crate::Readable for REGDMA_BACKUP_ADDR_SPEC {} +#[doc = "`reset()` method sets REGDMA_BACKUP_ADDR to value 0"] +impl crate::Resettable for REGDMA_BACKUP_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/regdma_bkp_conf.rs b/esp32p4/src/pau/regdma_bkp_conf.rs new file mode 100644 index 0000000000..acdf5220a1 --- /dev/null +++ b/esp32p4/src/pau/regdma_bkp_conf.rs @@ -0,0 +1,123 @@ +#[doc = "Register `REGDMA_BKP_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `REGDMA_BKP_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `READ_INTERVAL` reader - Link read_interval"] +pub type READ_INTERVAL_R = crate::FieldReader; +#[doc = "Field `READ_INTERVAL` writer - Link read_interval"] +pub type READ_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `LINK_TOUT_THRES` reader - link wait timeout threshold"] +pub type LINK_TOUT_THRES_R = crate::FieldReader; +#[doc = "Field `LINK_TOUT_THRES` writer - link wait timeout threshold"] +pub type LINK_TOUT_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `BURST_LIMIT` reader - burst limit"] +pub type BURST_LIMIT_R = crate::FieldReader; +#[doc = "Field `BURST_LIMIT` writer - burst limit"] +pub type BURST_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `BACKUP_TOUT_THRES` reader - Backup timeout threshold"] +pub type BACKUP_TOUT_THRES_R = crate::FieldReader; +#[doc = "Field `BACKUP_TOUT_THRES` writer - Backup timeout threshold"] +pub type BACKUP_TOUT_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:6 - Link read_interval"] + #[inline(always)] + pub fn read_interval(&self) -> READ_INTERVAL_R { + READ_INTERVAL_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 7:16 - link wait timeout threshold"] + #[inline(always)] + pub fn link_tout_thres(&self) -> LINK_TOUT_THRES_R { + LINK_TOUT_THRES_R::new(((self.bits >> 7) & 0x03ff) as u16) + } + #[doc = "Bits 17:21 - burst limit"] + #[inline(always)] + pub fn burst_limit(&self) -> BURST_LIMIT_R { + BURST_LIMIT_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:31 - Backup timeout threshold"] + #[inline(always)] + pub fn backup_tout_thres(&self) -> BACKUP_TOUT_THRES_R { + BACKUP_TOUT_THRES_R::new(((self.bits >> 22) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGDMA_BKP_CONF") + .field( + "read_interval", + &format_args!("{}", self.read_interval().bits()), + ) + .field( + "link_tout_thres", + &format_args!("{}", self.link_tout_thres().bits()), + ) + .field( + "burst_limit", + &format_args!("{}", self.burst_limit().bits()), + ) + .field( + "backup_tout_thres", + &format_args!("{}", self.backup_tout_thres().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Link read_interval"] + #[inline(always)] + #[must_use] + pub fn read_interval(&mut self) -> READ_INTERVAL_W { + READ_INTERVAL_W::new(self, 0) + } + #[doc = "Bits 7:16 - link wait timeout threshold"] + #[inline(always)] + #[must_use] + pub fn link_tout_thres(&mut self) -> LINK_TOUT_THRES_W { + LINK_TOUT_THRES_W::new(self, 7) + } + #[doc = "Bits 17:21 - burst limit"] + #[inline(always)] + #[must_use] + pub fn burst_limit(&mut self) -> BURST_LIMIT_W { + BURST_LIMIT_W::new(self, 17) + } + #[doc = "Bits 22:31 - Backup timeout threshold"] + #[inline(always)] + #[must_use] + pub fn backup_tout_thres(&mut self) -> BACKUP_TOUT_THRES_W { + BACKUP_TOUT_THRES_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "backup config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_bkp_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_bkp_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_BKP_CONF_SPEC; +impl crate::RegisterSpec for REGDMA_BKP_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regdma_bkp_conf::R`](R) reader structure"] +impl crate::Readable for REGDMA_BKP_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`regdma_bkp_conf::W`](W) writer structure"] +impl crate::Writable for REGDMA_BKP_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REGDMA_BKP_CONF to value 0x7d10_1920"] +impl crate::Resettable for REGDMA_BKP_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x7d10_1920; +} diff --git a/esp32p4/src/pau/regdma_clk_conf.rs b/esp32p4/src/pau/regdma_clk_conf.rs new file mode 100644 index 0000000000..72b9615274 --- /dev/null +++ b/esp32p4/src/pau/regdma_clk_conf.rs @@ -0,0 +1,63 @@ +#[doc = "Register `REGDMA_CLK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `REGDMA_CLK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - clock enable"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - clock enable"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - clock enable"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGDMA_CLK_CONF") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - clock enable"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_clk_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_clk_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_CLK_CONF_SPEC; +impl crate::RegisterSpec for REGDMA_CLK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regdma_clk_conf::R`](R) reader structure"] +impl crate::Readable for REGDMA_CLK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`regdma_clk_conf::W`](W) writer structure"] +impl crate::Writable for REGDMA_CLK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REGDMA_CLK_CONF to value 0"] +impl crate::Resettable for REGDMA_CLK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/regdma_conf.rs b/esp32p4/src/pau/regdma_conf.rs new file mode 100644 index 0000000000..5ac8812a37 --- /dev/null +++ b/esp32p4/src/pau/regdma_conf.rs @@ -0,0 +1,135 @@ +#[doc = "Register `REGDMA_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `REGDMA_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `FLOW_ERR` reader - backup error type"] +pub type FLOW_ERR_R = crate::FieldReader; +#[doc = "Field `START` writer - backup start signal"] +pub type START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TO_MEM` reader - backup direction(reg to mem / mem to reg)"] +pub type TO_MEM_R = crate::BitReader; +#[doc = "Field `TO_MEM` writer - backup direction(reg to mem / mem to reg)"] +pub type TO_MEM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LINK_SEL` reader - Link select"] +pub type LINK_SEL_R = crate::FieldReader; +#[doc = "Field `LINK_SEL` writer - Link select"] +pub type LINK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `START_MAC` writer - mac sw backup start signal"] +pub type START_MAC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TO_MEM_MAC` reader - mac sw backup direction(reg to mem / mem to reg)"] +pub type TO_MEM_MAC_R = crate::BitReader; +#[doc = "Field `TO_MEM_MAC` writer - mac sw backup direction(reg to mem / mem to reg)"] +pub type TO_MEM_MAC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEL_MAC` reader - mac hw/sw select"] +pub type SEL_MAC_R = crate::BitReader; +#[doc = "Field `SEL_MAC` writer - mac hw/sw select"] +pub type SEL_MAC_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - backup error type"] + #[inline(always)] + pub fn flow_err(&self) -> FLOW_ERR_R { + FLOW_ERR_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 4 - backup direction(reg to mem / mem to reg)"] + #[inline(always)] + pub fn to_mem(&self) -> TO_MEM_R { + TO_MEM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Link select"] + #[inline(always)] + pub fn link_sel(&self) -> LINK_SEL_R { + LINK_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 8 - mac sw backup direction(reg to mem / mem to reg)"] + #[inline(always)] + pub fn to_mem_mac(&self) -> TO_MEM_MAC_R { + TO_MEM_MAC_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - mac hw/sw select"] + #[inline(always)] + pub fn sel_mac(&self) -> SEL_MAC_R { + SEL_MAC_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGDMA_CONF") + .field("flow_err", &format_args!("{}", self.flow_err().bits())) + .field("to_mem", &format_args!("{}", self.to_mem().bit())) + .field("link_sel", &format_args!("{}", self.link_sel().bits())) + .field("to_mem_mac", &format_args!("{}", self.to_mem_mac().bit())) + .field("sel_mac", &format_args!("{}", self.sel_mac().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 3 - backup start signal"] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> START_W { + START_W::new(self, 3) + } + #[doc = "Bit 4 - backup direction(reg to mem / mem to reg)"] + #[inline(always)] + #[must_use] + pub fn to_mem(&mut self) -> TO_MEM_W { + TO_MEM_W::new(self, 4) + } + #[doc = "Bits 5:6 - Link select"] + #[inline(always)] + #[must_use] + pub fn link_sel(&mut self) -> LINK_SEL_W { + LINK_SEL_W::new(self, 5) + } + #[doc = "Bit 7 - mac sw backup start signal"] + #[inline(always)] + #[must_use] + pub fn start_mac(&mut self) -> START_MAC_W { + START_MAC_W::new(self, 7) + } + #[doc = "Bit 8 - mac sw backup direction(reg to mem / mem to reg)"] + #[inline(always)] + #[must_use] + pub fn to_mem_mac(&mut self) -> TO_MEM_MAC_W { + TO_MEM_MAC_W::new(self, 8) + } + #[doc = "Bit 9 - mac hw/sw select"] + #[inline(always)] + #[must_use] + pub fn sel_mac(&mut self) -> SEL_MAC_W { + SEL_MAC_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Peri backup control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_CONF_SPEC; +impl crate::RegisterSpec for REGDMA_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regdma_conf::R`](R) reader structure"] +impl crate::Readable for REGDMA_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`regdma_conf::W`](W) writer structure"] +impl crate::Writable for REGDMA_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REGDMA_CONF to value 0"] +impl crate::Resettable for REGDMA_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/regdma_current_link_addr.rs b/esp32p4/src/pau/regdma_current_link_addr.rs new file mode 100644 index 0000000000..bdebee6e9c --- /dev/null +++ b/esp32p4/src/pau/regdma_current_link_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `REGDMA_CURRENT_LINK_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `CURRENT_LINK_ADDR` reader - current link addr reg"] +pub type CURRENT_LINK_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - current link addr reg"] + #[inline(always)] + pub fn current_link_addr(&self) -> CURRENT_LINK_ADDR_R { + CURRENT_LINK_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGDMA_CURRENT_LINK_ADDR") + .field( + "current_link_addr", + &format_args!("{}", self.current_link_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "current link addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_current_link_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_CURRENT_LINK_ADDR_SPEC; +impl crate::RegisterSpec for REGDMA_CURRENT_LINK_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regdma_current_link_addr::R`](R) reader structure"] +impl crate::Readable for REGDMA_CURRENT_LINK_ADDR_SPEC {} +#[doc = "`reset()` method sets REGDMA_CURRENT_LINK_ADDR to value 0"] +impl crate::Resettable for REGDMA_CURRENT_LINK_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/regdma_etm_ctrl.rs b/esp32p4/src/pau/regdma_etm_ctrl.rs new file mode 100644 index 0000000000..2e72511a4c --- /dev/null +++ b/esp32p4/src/pau/regdma_etm_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REGDMA_ETM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_START_0` writer - etm_start_0 reg"] +pub type ETM_START_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_START_1` writer - etm_start_1 reg"] +pub type ETM_START_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_START_2` writer - etm_start_2 reg"] +pub type ETM_START_2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_START_3` writer - etm_start_3 reg"] +pub type ETM_START_3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - etm_start_0 reg"] + #[inline(always)] + #[must_use] + pub fn etm_start_0(&mut self) -> ETM_START_0_W { + ETM_START_0_W::new(self, 0) + } + #[doc = "Bit 1 - etm_start_1 reg"] + #[inline(always)] + #[must_use] + pub fn etm_start_1(&mut self) -> ETM_START_1_W { + ETM_START_1_W::new(self, 1) + } + #[doc = "Bit 2 - etm_start_2 reg"] + #[inline(always)] + #[must_use] + pub fn etm_start_2(&mut self) -> ETM_START_2_W { + ETM_START_2_W::new(self, 2) + } + #[doc = "Bit 3 - etm_start_3 reg"] + #[inline(always)] + #[must_use] + pub fn etm_start_3(&mut self) -> ETM_START_3_W { + ETM_START_3_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ETM start ctrl reg\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_etm_ctrl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_ETM_CTRL_SPEC; +impl crate::RegisterSpec for REGDMA_ETM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`regdma_etm_ctrl::W`](W) writer structure"] +impl crate::Writable for REGDMA_ETM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REGDMA_ETM_CTRL to value 0"] +impl crate::Resettable for REGDMA_ETM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/regdma_link_0_addr.rs b/esp32p4/src/pau/regdma_link_0_addr.rs new file mode 100644 index 0000000000..eb161a8848 --- /dev/null +++ b/esp32p4/src/pau/regdma_link_0_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REGDMA_LINK_0_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `REGDMA_LINK_0_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `LINK_ADDR_0` reader - link_0_addr reg"] +pub type LINK_ADDR_0_R = crate::FieldReader; +#[doc = "Field `LINK_ADDR_0` writer - link_0_addr reg"] +pub type LINK_ADDR_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - link_0_addr reg"] + #[inline(always)] + pub fn link_addr_0(&self) -> LINK_ADDR_0_R { + LINK_ADDR_0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGDMA_LINK_0_ADDR") + .field( + "link_addr_0", + &format_args!("{}", self.link_addr_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - link_0_addr reg"] + #[inline(always)] + #[must_use] + pub fn link_addr_0(&mut self) -> LINK_ADDR_0_W { + LINK_ADDR_0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "link_0_addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_link_0_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_link_0_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_LINK_0_ADDR_SPEC; +impl crate::RegisterSpec for REGDMA_LINK_0_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regdma_link_0_addr::R`](R) reader structure"] +impl crate::Readable for REGDMA_LINK_0_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`regdma_link_0_addr::W`](W) writer structure"] +impl crate::Writable for REGDMA_LINK_0_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REGDMA_LINK_0_ADDR to value 0"] +impl crate::Resettable for REGDMA_LINK_0_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/regdma_link_1_addr.rs b/esp32p4/src/pau/regdma_link_1_addr.rs new file mode 100644 index 0000000000..dabbdba884 --- /dev/null +++ b/esp32p4/src/pau/regdma_link_1_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REGDMA_LINK_1_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `REGDMA_LINK_1_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `LINK_ADDR_1` reader - Link_1_addr reg"] +pub type LINK_ADDR_1_R = crate::FieldReader; +#[doc = "Field `LINK_ADDR_1` writer - Link_1_addr reg"] +pub type LINK_ADDR_1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Link_1_addr reg"] + #[inline(always)] + pub fn link_addr_1(&self) -> LINK_ADDR_1_R { + LINK_ADDR_1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGDMA_LINK_1_ADDR") + .field( + "link_addr_1", + &format_args!("{}", self.link_addr_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Link_1_addr reg"] + #[inline(always)] + #[must_use] + pub fn link_addr_1(&mut self) -> LINK_ADDR_1_W { + LINK_ADDR_1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link_1_addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_link_1_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_link_1_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_LINK_1_ADDR_SPEC; +impl crate::RegisterSpec for REGDMA_LINK_1_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regdma_link_1_addr::R`](R) reader structure"] +impl crate::Readable for REGDMA_LINK_1_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`regdma_link_1_addr::W`](W) writer structure"] +impl crate::Writable for REGDMA_LINK_1_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REGDMA_LINK_1_ADDR to value 0"] +impl crate::Resettable for REGDMA_LINK_1_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/regdma_link_2_addr.rs b/esp32p4/src/pau/regdma_link_2_addr.rs new file mode 100644 index 0000000000..a671671d19 --- /dev/null +++ b/esp32p4/src/pau/regdma_link_2_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REGDMA_LINK_2_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `REGDMA_LINK_2_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `LINK_ADDR_2` reader - Link_2_addr reg"] +pub type LINK_ADDR_2_R = crate::FieldReader; +#[doc = "Field `LINK_ADDR_2` writer - Link_2_addr reg"] +pub type LINK_ADDR_2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Link_2_addr reg"] + #[inline(always)] + pub fn link_addr_2(&self) -> LINK_ADDR_2_R { + LINK_ADDR_2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGDMA_LINK_2_ADDR") + .field( + "link_addr_2", + &format_args!("{}", self.link_addr_2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Link_2_addr reg"] + #[inline(always)] + #[must_use] + pub fn link_addr_2(&mut self) -> LINK_ADDR_2_W { + LINK_ADDR_2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link_2_addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_link_2_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_link_2_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_LINK_2_ADDR_SPEC; +impl crate::RegisterSpec for REGDMA_LINK_2_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regdma_link_2_addr::R`](R) reader structure"] +impl crate::Readable for REGDMA_LINK_2_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`regdma_link_2_addr::W`](W) writer structure"] +impl crate::Writable for REGDMA_LINK_2_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REGDMA_LINK_2_ADDR to value 0"] +impl crate::Resettable for REGDMA_LINK_2_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/regdma_link_3_addr.rs b/esp32p4/src/pau/regdma_link_3_addr.rs new file mode 100644 index 0000000000..b514ee84fa --- /dev/null +++ b/esp32p4/src/pau/regdma_link_3_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REGDMA_LINK_3_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `REGDMA_LINK_3_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `LINK_ADDR_3` reader - Link_3_addr reg"] +pub type LINK_ADDR_3_R = crate::FieldReader; +#[doc = "Field `LINK_ADDR_3` writer - Link_3_addr reg"] +pub type LINK_ADDR_3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Link_3_addr reg"] + #[inline(always)] + pub fn link_addr_3(&self) -> LINK_ADDR_3_R { + LINK_ADDR_3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGDMA_LINK_3_ADDR") + .field( + "link_addr_3", + &format_args!("{}", self.link_addr_3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Link_3_addr reg"] + #[inline(always)] + #[must_use] + pub fn link_addr_3(&mut self) -> LINK_ADDR_3_W { + LINK_ADDR_3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link_3_addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_link_3_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_link_3_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_LINK_3_ADDR_SPEC; +impl crate::RegisterSpec for REGDMA_LINK_3_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regdma_link_3_addr::R`](R) reader structure"] +impl crate::Readable for REGDMA_LINK_3_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`regdma_link_3_addr::W`](W) writer structure"] +impl crate::Writable for REGDMA_LINK_3_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REGDMA_LINK_3_ADDR to value 0"] +impl crate::Resettable for REGDMA_LINK_3_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/regdma_link_mac_addr.rs b/esp32p4/src/pau/regdma_link_mac_addr.rs new file mode 100644 index 0000000000..d41b47c1f5 --- /dev/null +++ b/esp32p4/src/pau/regdma_link_mac_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REGDMA_LINK_MAC_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `REGDMA_LINK_MAC_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `LINK_ADDR_MAC` reader - Link_mac_addr reg"] +pub type LINK_ADDR_MAC_R = crate::FieldReader; +#[doc = "Field `LINK_ADDR_MAC` writer - Link_mac_addr reg"] +pub type LINK_ADDR_MAC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Link_mac_addr reg"] + #[inline(always)] + pub fn link_addr_mac(&self) -> LINK_ADDR_MAC_R { + LINK_ADDR_MAC_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGDMA_LINK_MAC_ADDR") + .field( + "link_addr_mac", + &format_args!("{}", self.link_addr_mac().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Link_mac_addr reg"] + #[inline(always)] + #[must_use] + pub fn link_addr_mac(&mut self) -> LINK_ADDR_MAC_W { + LINK_ADDR_MAC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Link_mac_addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_link_mac_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_link_mac_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_LINK_MAC_ADDR_SPEC; +impl crate::RegisterSpec for REGDMA_LINK_MAC_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regdma_link_mac_addr::R`](R) reader structure"] +impl crate::Readable for REGDMA_LINK_MAC_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`regdma_link_mac_addr::W`](W) writer structure"] +impl crate::Writable for REGDMA_LINK_MAC_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REGDMA_LINK_MAC_ADDR to value 0"] +impl crate::Resettable for REGDMA_LINK_MAC_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pau/regdma_mem_addr.rs b/esp32p4/src/pau/regdma_mem_addr.rs new file mode 100644 index 0000000000..62df10ce91 --- /dev/null +++ b/esp32p4/src/pau/regdma_mem_addr.rs @@ -0,0 +1,36 @@ +#[doc = "Register `REGDMA_MEM_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `MEM_ADDR` reader - mem addr reg"] +pub type MEM_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - mem addr reg"] + #[inline(always)] + pub fn mem_addr(&self) -> MEM_ADDR_R { + MEM_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGDMA_MEM_ADDR") + .field("mem_addr", &format_args!("{}", self.mem_addr().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "mem addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_mem_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGDMA_MEM_ADDR_SPEC; +impl crate::RegisterSpec for REGDMA_MEM_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regdma_mem_addr::R`](R) reader structure"] +impl crate::Readable for REGDMA_MEM_ADDR_SPEC {} +#[doc = "`reset()` method sets REGDMA_MEM_ADDR to value 0"] +impl crate::Resettable for REGDMA_MEM_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt.rs b/esp32p4/src/pcnt.rs new file mode 100644 index 0000000000..92a3468b8a --- /dev/null +++ b/esp32p4/src/pcnt.rs @@ -0,0 +1,267 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + u_conf0: (), + _reserved1: [u8; 0x04], + u_conf1: (), + _reserved2: [u8; 0x04], + u_conf2: (), + _reserved3: [u8; 0x28], + u_cnt: [U_CNT; 4], + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + u_status: [U_STATUS; 4], + ctrl: CTRL, + u3_change_conf: U3_CHANGE_CONF, + u2_change_conf: U2_CHANGE_CONF, + u1_change_conf: U1_CHANGE_CONF, + u0_change_conf: U0_CHANGE_CONF, + _reserved14: [u8; 0x88], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00..0x10 - Configuration register 0 for unit %s"] + #[inline(always)] + pub const fn u_conf0(&self, n: usize) -> &U_CONF0 { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(0).add(12 * n).cast() } + } + #[doc = "0x00 - Configuration register 0 for unit 0"] + #[inline(always)] + pub const fn u0_conf0(&self) -> &U_CONF0 { + &self.u_conf0(0) + } + #[doc = "0x0c - Configuration register 0 for unit 1"] + #[inline(always)] + pub const fn u1_conf0(&self) -> &U_CONF0 { + &self.u_conf0(1) + } + #[doc = "0x18 - Configuration register 0 for unit 2"] + #[inline(always)] + pub const fn u2_conf0(&self) -> &U_CONF0 { + &self.u_conf0(2) + } + #[doc = "0x24 - Configuration register 0 for unit 3"] + #[inline(always)] + pub const fn u3_conf0(&self) -> &U_CONF0 { + &self.u_conf0(3) + } + #[doc = "0x04..0x14 - Configuration register 1 for unit %s"] + #[inline(always)] + pub const fn u_conf1(&self, n: usize) -> &U_CONF1 { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(4).add(12 * n).cast() } + } + #[doc = "0x04 - Configuration register 1 for unit 0"] + #[inline(always)] + pub const fn u0_conf1(&self) -> &U_CONF1 { + &self.u_conf1(0) + } + #[doc = "0x10 - Configuration register 1 for unit 1"] + #[inline(always)] + pub const fn u1_conf1(&self) -> &U_CONF1 { + &self.u_conf1(1) + } + #[doc = "0x1c - Configuration register 1 for unit 2"] + #[inline(always)] + pub const fn u2_conf1(&self) -> &U_CONF1 { + &self.u_conf1(2) + } + #[doc = "0x28 - Configuration register 1 for unit 3"] + #[inline(always)] + pub const fn u3_conf1(&self) -> &U_CONF1 { + &self.u_conf1(3) + } + #[doc = "0x08..0x18 - Configuration register 2 for unit %s"] + #[inline(always)] + pub const fn u_conf2(&self, n: usize) -> &U_CONF2 { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(8).add(12 * n).cast() } + } + #[doc = "0x08 - Configuration register 2 for unit 0"] + #[inline(always)] + pub const fn u0_conf2(&self) -> &U_CONF2 { + &self.u_conf2(0) + } + #[doc = "0x14 - Configuration register 2 for unit 1"] + #[inline(always)] + pub const fn u1_conf2(&self) -> &U_CONF2 { + &self.u_conf2(1) + } + #[doc = "0x20 - Configuration register 2 for unit 2"] + #[inline(always)] + pub const fn u2_conf2(&self) -> &U_CONF2 { + &self.u_conf2(2) + } + #[doc = "0x2c - Configuration register 2 for unit 3"] + #[inline(always)] + pub const fn u3_conf2(&self) -> &U_CONF2 { + &self.u_conf2(3) + } + #[doc = "0x30..0x40 - Counter value for unit %s"] + #[inline(always)] + pub const fn u_cnt(&self, n: usize) -> &U_CNT { + &self.u_cnt[n] + } + #[doc = "0x30 - Counter value for unit 0"] + #[inline(always)] + pub const fn u0_cnt(&self) -> &U_CNT { + &self.u_cnt(0) + } + #[doc = "0x34 - Counter value for unit 1"] + #[inline(always)] + pub const fn u1_cnt(&self) -> &U_CNT { + &self.u_cnt(1) + } + #[doc = "0x38 - Counter value for unit 2"] + #[inline(always)] + pub const fn u2_cnt(&self) -> &U_CNT { + &self.u_cnt(2) + } + #[doc = "0x3c - Counter value for unit 3"] + #[inline(always)] + pub const fn u3_cnt(&self) -> &U_CNT { + &self.u_cnt(3) + } + #[doc = "0x40 - Interrupt raw status register"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x44 - Interrupt status register"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x48 - Interrupt enable register"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x4c - Interrupt clear register"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x50..0x60 - PNCT UNIT%s status register"] + #[inline(always)] + pub const fn u_status(&self, n: usize) -> &U_STATUS { + &self.u_status[n] + } + #[doc = "0x50 - PNCT UNIT0 status register"] + #[inline(always)] + pub const fn u0_status(&self) -> &U_STATUS { + &self.u_status(0) + } + #[doc = "0x54 - PNCT UNIT1 status register"] + #[inline(always)] + pub const fn u1_status(&self) -> &U_STATUS { + &self.u_status(1) + } + #[doc = "0x58 - PNCT UNIT2 status register"] + #[inline(always)] + pub const fn u2_status(&self) -> &U_STATUS { + &self.u_status(2) + } + #[doc = "0x5c - PNCT UNIT3 status register"] + #[inline(always)] + pub const fn u3_status(&self) -> &U_STATUS { + &self.u_status(3) + } + #[doc = "0x60 - Control register for all counters"] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0x64 - Configuration register for unit $n's step value."] + #[inline(always)] + pub const fn u3_change_conf(&self) -> &U3_CHANGE_CONF { + &self.u3_change_conf + } + #[doc = "0x68 - Configuration register for unit $n's step value."] + #[inline(always)] + pub const fn u2_change_conf(&self) -> &U2_CHANGE_CONF { + &self.u2_change_conf + } + #[doc = "0x6c - Configuration register for unit $n's step value."] + #[inline(always)] + pub const fn u1_change_conf(&self) -> &U1_CHANGE_CONF { + &self.u1_change_conf + } + #[doc = "0x70 - Configuration register for unit $n's step value."] + #[inline(always)] + pub const fn u0_change_conf(&self) -> &U0_CHANGE_CONF { + &self.u0_change_conf + } + #[doc = "0xfc - PCNT version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "U_CONF0 (rw) register accessor: Configuration register 0 for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u_conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@u_conf0`] module"] +pub type U_CONF0 = crate::Reg; +#[doc = "Configuration register 0 for unit %s"] +pub mod u_conf0; +#[doc = "U_CONF1 (rw) register accessor: Configuration register 1 for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@u_conf1`] module"] +pub type U_CONF1 = crate::Reg; +#[doc = "Configuration register 1 for unit %s"] +pub mod u_conf1; +#[doc = "U_CONF2 (rw) register accessor: Configuration register 2 for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@u_conf2`] module"] +pub type U_CONF2 = crate::Reg; +#[doc = "Configuration register 2 for unit %s"] +pub mod u_conf2; +#[doc = "U_CNT (r) register accessor: Counter value for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@u_cnt`] module"] +pub type U_CNT = crate::Reg; +#[doc = "Counter value for unit %s"] +pub mod u_cnt; +#[doc = "INT_RAW (rw) register accessor: Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Interrupt raw status register"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Interrupt status register"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable register"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear register"] +pub mod int_clr; +#[doc = "U_STATUS (r) register accessor: PNCT UNIT%s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@u_status`] module"] +pub type U_STATUS = crate::Reg; +#[doc = "PNCT UNIT%s status register"] +pub mod u_status; +#[doc = "CTRL (rw) register accessor: Control register for all counters\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +pub type CTRL = crate::Reg; +#[doc = "Control register for all counters"] +pub mod ctrl; +#[doc = "U3_CHANGE_CONF (rw) register accessor: Configuration register for unit $n's step value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u3_change_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u3_change_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@u3_change_conf`] module"] +pub type U3_CHANGE_CONF = crate::Reg; +#[doc = "Configuration register for unit $n's step value."] +pub mod u3_change_conf; +#[doc = "U2_CHANGE_CONF (rw) register accessor: Configuration register for unit $n's step value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u2_change_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u2_change_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@u2_change_conf`] module"] +pub type U2_CHANGE_CONF = crate::Reg; +#[doc = "Configuration register for unit $n's step value."] +pub mod u2_change_conf; +#[doc = "U1_CHANGE_CONF (rw) register accessor: Configuration register for unit $n's step value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u1_change_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u1_change_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@u1_change_conf`] module"] +pub type U1_CHANGE_CONF = crate::Reg; +#[doc = "Configuration register for unit $n's step value."] +pub mod u1_change_conf; +#[doc = "U0_CHANGE_CONF (rw) register accessor: Configuration register for unit $n's step value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u0_change_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u0_change_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@u0_change_conf`] module"] +pub type U0_CHANGE_CONF = crate::Reg; +#[doc = "Configuration register for unit $n's step value."] +pub mod u0_change_conf; +#[doc = "DATE (rw) register accessor: PCNT version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "PCNT version control register"] +pub mod date; diff --git a/esp32p4/src/pcnt/ctrl.rs b/esp32p4/src/pcnt/ctrl.rs new file mode 100644 index 0000000000..01f62d8b6c --- /dev/null +++ b/esp32p4/src/pcnt/ctrl.rs @@ -0,0 +1,291 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `PULSE_CNT_RST_U0` reader - Set this bit to clear unit 0's counter."] +pub type PULSE_CNT_RST_U0_R = crate::BitReader; +#[doc = "Field `PULSE_CNT_RST_U0` writer - Set this bit to clear unit 0's counter."] +pub type PULSE_CNT_RST_U0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_PAUSE_U0` reader - Set this bit to freeze unit 0's counter."] +pub type CNT_PAUSE_U0_R = crate::BitReader; +#[doc = "Field `CNT_PAUSE_U0` writer - Set this bit to freeze unit 0's counter."] +pub type CNT_PAUSE_U0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PULSE_CNT_RST_U1` reader - Set this bit to clear unit 1's counter."] +pub type PULSE_CNT_RST_U1_R = crate::BitReader; +#[doc = "Field `PULSE_CNT_RST_U1` writer - Set this bit to clear unit 1's counter."] +pub type PULSE_CNT_RST_U1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_PAUSE_U1` reader - Set this bit to freeze unit 1's counter."] +pub type CNT_PAUSE_U1_R = crate::BitReader; +#[doc = "Field `CNT_PAUSE_U1` writer - Set this bit to freeze unit 1's counter."] +pub type CNT_PAUSE_U1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PULSE_CNT_RST_U2` reader - Set this bit to clear unit 2's counter."] +pub type PULSE_CNT_RST_U2_R = crate::BitReader; +#[doc = "Field `PULSE_CNT_RST_U2` writer - Set this bit to clear unit 2's counter."] +pub type PULSE_CNT_RST_U2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_PAUSE_U2` reader - Set this bit to freeze unit 2's counter."] +pub type CNT_PAUSE_U2_R = crate::BitReader; +#[doc = "Field `CNT_PAUSE_U2` writer - Set this bit to freeze unit 2's counter."] +pub type CNT_PAUSE_U2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PULSE_CNT_RST_U3` reader - Set this bit to clear unit 3's counter."] +pub type PULSE_CNT_RST_U3_R = crate::BitReader; +#[doc = "Field `PULSE_CNT_RST_U3` writer - Set this bit to clear unit 3's counter."] +pub type PULSE_CNT_RST_U3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_PAUSE_U3` reader - Set this bit to freeze unit 3's counter."] +pub type CNT_PAUSE_U3_R = crate::BitReader; +#[doc = "Field `CNT_PAUSE_U3` writer - Set this bit to freeze unit 3's counter."] +pub type CNT_PAUSE_U3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DALTA_CHANGE_EN_U0` reader - Configures this bit to enable unit 0's step comparator."] +pub type DALTA_CHANGE_EN_U0_R = crate::BitReader; +#[doc = "Field `DALTA_CHANGE_EN_U0` writer - Configures this bit to enable unit 0's step comparator."] +pub type DALTA_CHANGE_EN_U0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DALTA_CHANGE_EN_U1` reader - Configures this bit to enable unit 1's step comparator."] +pub type DALTA_CHANGE_EN_U1_R = crate::BitReader; +#[doc = "Field `DALTA_CHANGE_EN_U1` writer - Configures this bit to enable unit 1's step comparator."] +pub type DALTA_CHANGE_EN_U1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DALTA_CHANGE_EN_U2` reader - Configures this bit to enable unit 2's step comparator."] +pub type DALTA_CHANGE_EN_U2_R = crate::BitReader; +#[doc = "Field `DALTA_CHANGE_EN_U2` writer - Configures this bit to enable unit 2's step comparator."] +pub type DALTA_CHANGE_EN_U2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DALTA_CHANGE_EN_U3` reader - Configures this bit to enable unit 3's step comparator."] +pub type DALTA_CHANGE_EN_U3_R = crate::BitReader; +#[doc = "Field `DALTA_CHANGE_EN_U3` writer - Configures this bit to enable unit 3's step comparator."] +pub type DALTA_CHANGE_EN_U3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to clear unit 0's counter."] + #[inline(always)] + pub fn pulse_cnt_rst_u0(&self) -> PULSE_CNT_RST_U0_R { + PULSE_CNT_RST_U0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to freeze unit 0's counter."] + #[inline(always)] + pub fn cnt_pause_u0(&self) -> CNT_PAUSE_U0_R { + CNT_PAUSE_U0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to clear unit 1's counter."] + #[inline(always)] + pub fn pulse_cnt_rst_u1(&self) -> PULSE_CNT_RST_U1_R { + PULSE_CNT_RST_U1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to freeze unit 1's counter."] + #[inline(always)] + pub fn cnt_pause_u1(&self) -> CNT_PAUSE_U1_R { + CNT_PAUSE_U1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to clear unit 2's counter."] + #[inline(always)] + pub fn pulse_cnt_rst_u2(&self) -> PULSE_CNT_RST_U2_R { + PULSE_CNT_RST_U2_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set this bit to freeze unit 2's counter."] + #[inline(always)] + pub fn cnt_pause_u2(&self) -> CNT_PAUSE_U2_R { + CNT_PAUSE_U2_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set this bit to clear unit 3's counter."] + #[inline(always)] + pub fn pulse_cnt_rst_u3(&self) -> PULSE_CNT_RST_U3_R { + PULSE_CNT_RST_U3_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set this bit to freeze unit 3's counter."] + #[inline(always)] + pub fn cnt_pause_u3(&self) -> CNT_PAUSE_U3_R { + CNT_PAUSE_U3_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configures this bit to enable unit 0's step comparator."] + #[inline(always)] + pub fn dalta_change_en_u0(&self) -> DALTA_CHANGE_EN_U0_R { + DALTA_CHANGE_EN_U0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Configures this bit to enable unit 1's step comparator."] + #[inline(always)] + pub fn dalta_change_en_u1(&self) -> DALTA_CHANGE_EN_U1_R { + DALTA_CHANGE_EN_U1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Configures this bit to enable unit 2's step comparator."] + #[inline(always)] + pub fn dalta_change_en_u2(&self) -> DALTA_CHANGE_EN_U2_R { + DALTA_CHANGE_EN_U2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Configures this bit to enable unit 3's step comparator."] + #[inline(always)] + pub fn dalta_change_en_u3(&self) -> DALTA_CHANGE_EN_U3_R { + DALTA_CHANGE_EN_U3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTRL") + .field( + "pulse_cnt_rst_u0", + &format_args!("{}", self.pulse_cnt_rst_u0().bit()), + ) + .field( + "cnt_pause_u0", + &format_args!("{}", self.cnt_pause_u0().bit()), + ) + .field( + "pulse_cnt_rst_u1", + &format_args!("{}", self.pulse_cnt_rst_u1().bit()), + ) + .field( + "cnt_pause_u1", + &format_args!("{}", self.cnt_pause_u1().bit()), + ) + .field( + "pulse_cnt_rst_u2", + &format_args!("{}", self.pulse_cnt_rst_u2().bit()), + ) + .field( + "cnt_pause_u2", + &format_args!("{}", self.cnt_pause_u2().bit()), + ) + .field( + "pulse_cnt_rst_u3", + &format_args!("{}", self.pulse_cnt_rst_u3().bit()), + ) + .field( + "cnt_pause_u3", + &format_args!("{}", self.cnt_pause_u3().bit()), + ) + .field( + "dalta_change_en_u0", + &format_args!("{}", self.dalta_change_en_u0().bit()), + ) + .field( + "dalta_change_en_u1", + &format_args!("{}", self.dalta_change_en_u1().bit()), + ) + .field( + "dalta_change_en_u2", + &format_args!("{}", self.dalta_change_en_u2().bit()), + ) + .field( + "dalta_change_en_u3", + &format_args!("{}", self.dalta_change_en_u3().bit()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear unit 0's counter."] + #[inline(always)] + #[must_use] + pub fn pulse_cnt_rst_u0(&mut self) -> PULSE_CNT_RST_U0_W { + PULSE_CNT_RST_U0_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to freeze unit 0's counter."] + #[inline(always)] + #[must_use] + pub fn cnt_pause_u0(&mut self) -> CNT_PAUSE_U0_W { + CNT_PAUSE_U0_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear unit 1's counter."] + #[inline(always)] + #[must_use] + pub fn pulse_cnt_rst_u1(&mut self) -> PULSE_CNT_RST_U1_W { + PULSE_CNT_RST_U1_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to freeze unit 1's counter."] + #[inline(always)] + #[must_use] + pub fn cnt_pause_u1(&mut self) -> CNT_PAUSE_U1_W { + CNT_PAUSE_U1_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear unit 2's counter."] + #[inline(always)] + #[must_use] + pub fn pulse_cnt_rst_u2(&mut self) -> PULSE_CNT_RST_U2_W { + PULSE_CNT_RST_U2_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to freeze unit 2's counter."] + #[inline(always)] + #[must_use] + pub fn cnt_pause_u2(&mut self) -> CNT_PAUSE_U2_W { + CNT_PAUSE_U2_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear unit 3's counter."] + #[inline(always)] + #[must_use] + pub fn pulse_cnt_rst_u3(&mut self) -> PULSE_CNT_RST_U3_W { + PULSE_CNT_RST_U3_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to freeze unit 3's counter."] + #[inline(always)] + #[must_use] + pub fn cnt_pause_u3(&mut self) -> CNT_PAUSE_U3_W { + CNT_PAUSE_U3_W::new(self, 7) + } + #[doc = "Bit 8 - Configures this bit to enable unit 0's step comparator."] + #[inline(always)] + #[must_use] + pub fn dalta_change_en_u0(&mut self) -> DALTA_CHANGE_EN_U0_W { + DALTA_CHANGE_EN_U0_W::new(self, 8) + } + #[doc = "Bit 9 - Configures this bit to enable unit 1's step comparator."] + #[inline(always)] + #[must_use] + pub fn dalta_change_en_u1(&mut self) -> DALTA_CHANGE_EN_U1_W { + DALTA_CHANGE_EN_U1_W::new(self, 9) + } + #[doc = "Bit 10 - Configures this bit to enable unit 2's step comparator."] + #[inline(always)] + #[must_use] + pub fn dalta_change_en_u2(&mut self) -> DALTA_CHANGE_EN_U2_W { + DALTA_CHANGE_EN_U2_W::new(self, 10) + } + #[doc = "Bit 11 - Configures this bit to enable unit 3's step comparator."] + #[inline(always)] + #[must_use] + pub fn dalta_change_en_u3(&mut self) -> DALTA_CHANGE_EN_U3_W { + DALTA_CHANGE_EN_U3_W::new(self, 11) + } + #[doc = "Bit 16 - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control register for all counters\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL to value 0x01"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/pcnt/date.rs b/esp32p4/src/pcnt/date.rs new file mode 100644 index 0000000000..e543053864 --- /dev/null +++ b/esp32p4/src/pcnt/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - This is the PCNT version control register."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - This is the PCNT version control register."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This is the PCNT version control register."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This is the PCNT version control register."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PCNT version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x2209_1900"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2209_1900; +} diff --git a/esp32p4/src/pcnt/int_clr.rs b/esp32p4/src/pcnt/int_clr.rs new file mode 100644 index 0000000000..28a085b573 --- /dev/null +++ b/esp32p4/src/pcnt/int_clr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CNT_THR_EVENT_U0_INT_CLR` writer - Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt."] +pub type CNT_THR_EVENT_U0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_THR_EVENT_U1_INT_CLR` writer - Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt."] +pub type CNT_THR_EVENT_U1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_THR_EVENT_U2_INT_CLR` writer - Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt."] +pub type CNT_THR_EVENT_U2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_THR_EVENT_U3_INT_CLR` writer - Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt."] +pub type CNT_THR_EVENT_U3_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u0_int_clr(&mut self) -> CNT_THR_EVENT_U0_INT_CLR_W { + CNT_THR_EVENT_U0_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u1_int_clr(&mut self) -> CNT_THR_EVENT_U1_INT_CLR_W { + CNT_THR_EVENT_U1_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u2_int_clr(&mut self) -> CNT_THR_EVENT_U2_INT_CLR_W { + CNT_THR_EVENT_U2_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u3_int_clr(&mut self) -> CNT_THR_EVENT_U3_INT_CLR_W { + CNT_THR_EVENT_U3_INT_CLR_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt/int_ena.rs b/esp32p4/src/pcnt/int_ena.rs new file mode 100644 index 0000000000..240f8d690a --- /dev/null +++ b/esp32p4/src/pcnt/int_ena.rs @@ -0,0 +1,123 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `CNT_THR_EVENT_U0_INT_ENA` reader - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."] +pub type CNT_THR_EVENT_U0_INT_ENA_R = crate::BitReader; +#[doc = "Field `CNT_THR_EVENT_U0_INT_ENA` writer - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."] +pub type CNT_THR_EVENT_U0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_THR_EVENT_U1_INT_ENA` reader - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."] +pub type CNT_THR_EVENT_U1_INT_ENA_R = crate::BitReader; +#[doc = "Field `CNT_THR_EVENT_U1_INT_ENA` writer - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."] +pub type CNT_THR_EVENT_U1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_THR_EVENT_U2_INT_ENA` reader - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."] +pub type CNT_THR_EVENT_U2_INT_ENA_R = crate::BitReader; +#[doc = "Field `CNT_THR_EVENT_U2_INT_ENA` writer - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."] +pub type CNT_THR_EVENT_U2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_THR_EVENT_U3_INT_ENA` reader - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."] +pub type CNT_THR_EVENT_U3_INT_ENA_R = crate::BitReader; +#[doc = "Field `CNT_THR_EVENT_U3_INT_ENA` writer - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."] +pub type CNT_THR_EVENT_U3_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u0_int_ena(&self) -> CNT_THR_EVENT_U0_INT_ENA_R { + CNT_THR_EVENT_U0_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u1_int_ena(&self) -> CNT_THR_EVENT_U1_INT_ENA_R { + CNT_THR_EVENT_U1_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u2_int_ena(&self) -> CNT_THR_EVENT_U2_INT_ENA_R { + CNT_THR_EVENT_U2_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u3_int_ena(&self) -> CNT_THR_EVENT_U3_INT_ENA_R { + CNT_THR_EVENT_U3_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "cnt_thr_event_u0_int_ena", + &format_args!("{}", self.cnt_thr_event_u0_int_ena().bit()), + ) + .field( + "cnt_thr_event_u1_int_ena", + &format_args!("{}", self.cnt_thr_event_u1_int_ena().bit()), + ) + .field( + "cnt_thr_event_u2_int_ena", + &format_args!("{}", self.cnt_thr_event_u2_int_ena().bit()), + ) + .field( + "cnt_thr_event_u3_int_ena", + &format_args!("{}", self.cnt_thr_event_u3_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u0_int_ena(&mut self) -> CNT_THR_EVENT_U0_INT_ENA_W { + CNT_THR_EVENT_U0_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u1_int_ena(&mut self) -> CNT_THR_EVENT_U1_INT_ENA_W { + CNT_THR_EVENT_U1_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u2_int_ena(&mut self) -> CNT_THR_EVENT_U2_INT_ENA_W { + CNT_THR_EVENT_U2_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u3_int_ena(&mut self) -> CNT_THR_EVENT_U3_INT_ENA_W { + CNT_THR_EVENT_U3_INT_ENA_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt/int_raw.rs b/esp32p4/src/pcnt/int_raw.rs new file mode 100644 index 0000000000..736d5a74c2 --- /dev/null +++ b/esp32p4/src/pcnt/int_raw.rs @@ -0,0 +1,123 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `CNT_THR_EVENT_U0_INT_RAW` reader - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."] +pub type CNT_THR_EVENT_U0_INT_RAW_R = crate::BitReader; +#[doc = "Field `CNT_THR_EVENT_U0_INT_RAW` writer - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."] +pub type CNT_THR_EVENT_U0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_THR_EVENT_U1_INT_RAW` reader - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."] +pub type CNT_THR_EVENT_U1_INT_RAW_R = crate::BitReader; +#[doc = "Field `CNT_THR_EVENT_U1_INT_RAW` writer - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."] +pub type CNT_THR_EVENT_U1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_THR_EVENT_U2_INT_RAW` reader - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."] +pub type CNT_THR_EVENT_U2_INT_RAW_R = crate::BitReader; +#[doc = "Field `CNT_THR_EVENT_U2_INT_RAW` writer - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."] +pub type CNT_THR_EVENT_U2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_THR_EVENT_U3_INT_RAW` reader - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."] +pub type CNT_THR_EVENT_U3_INT_RAW_R = crate::BitReader; +#[doc = "Field `CNT_THR_EVENT_U3_INT_RAW` writer - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."] +pub type CNT_THR_EVENT_U3_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u0_int_raw(&self) -> CNT_THR_EVENT_U0_INT_RAW_R { + CNT_THR_EVENT_U0_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u1_int_raw(&self) -> CNT_THR_EVENT_U1_INT_RAW_R { + CNT_THR_EVENT_U1_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u2_int_raw(&self) -> CNT_THR_EVENT_U2_INT_RAW_R { + CNT_THR_EVENT_U2_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u3_int_raw(&self) -> CNT_THR_EVENT_U3_INT_RAW_R { + CNT_THR_EVENT_U3_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "cnt_thr_event_u0_int_raw", + &format_args!("{}", self.cnt_thr_event_u0_int_raw().bit()), + ) + .field( + "cnt_thr_event_u1_int_raw", + &format_args!("{}", self.cnt_thr_event_u1_int_raw().bit()), + ) + .field( + "cnt_thr_event_u2_int_raw", + &format_args!("{}", self.cnt_thr_event_u2_int_raw().bit()), + ) + .field( + "cnt_thr_event_u3_int_raw", + &format_args!("{}", self.cnt_thr_event_u3_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u0_int_raw(&mut self) -> CNT_THR_EVENT_U0_INT_RAW_W { + CNT_THR_EVENT_U0_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u1_int_raw(&mut self) -> CNT_THR_EVENT_U1_INT_RAW_W { + CNT_THR_EVENT_U1_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u2_int_raw(&mut self) -> CNT_THR_EVENT_U2_INT_RAW_W { + CNT_THR_EVENT_U2_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn cnt_thr_event_u3_int_raw(&mut self) -> CNT_THR_EVENT_U3_INT_RAW_W { + CNT_THR_EVENT_U3_INT_RAW_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt/int_st.rs b/esp32p4/src/pcnt/int_st.rs new file mode 100644 index 0000000000..85ea3a964b --- /dev/null +++ b/esp32p4/src/pcnt/int_st.rs @@ -0,0 +1,72 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `CNT_THR_EVENT_U0_INT_ST` reader - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."] +pub type CNT_THR_EVENT_U0_INT_ST_R = crate::BitReader; +#[doc = "Field `CNT_THR_EVENT_U1_INT_ST` reader - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."] +pub type CNT_THR_EVENT_U1_INT_ST_R = crate::BitReader; +#[doc = "Field `CNT_THR_EVENT_U2_INT_ST` reader - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."] +pub type CNT_THR_EVENT_U2_INT_ST_R = crate::BitReader; +#[doc = "Field `CNT_THR_EVENT_U3_INT_ST` reader - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."] +pub type CNT_THR_EVENT_U3_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u0_int_st(&self) -> CNT_THR_EVENT_U0_INT_ST_R { + CNT_THR_EVENT_U0_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u1_int_st(&self) -> CNT_THR_EVENT_U1_INT_ST_R { + CNT_THR_EVENT_U1_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u2_int_st(&self) -> CNT_THR_EVENT_U2_INT_ST_R { + CNT_THR_EVENT_U2_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."] + #[inline(always)] + pub fn cnt_thr_event_u3_int_st(&self) -> CNT_THR_EVENT_U3_INT_ST_R { + CNT_THR_EVENT_U3_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "cnt_thr_event_u0_int_st", + &format_args!("{}", self.cnt_thr_event_u0_int_st().bit()), + ) + .field( + "cnt_thr_event_u1_int_st", + &format_args!("{}", self.cnt_thr_event_u1_int_st().bit()), + ) + .field( + "cnt_thr_event_u2_int_st", + &format_args!("{}", self.cnt_thr_event_u2_int_st().bit()), + ) + .field( + "cnt_thr_event_u3_int_st", + &format_args!("{}", self.cnt_thr_event_u3_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt/u0_change_conf.rs b/esp32p4/src/pcnt/u0_change_conf.rs new file mode 100644 index 0000000000..ddcf0d7ada --- /dev/null +++ b/esp32p4/src/pcnt/u0_change_conf.rs @@ -0,0 +1,85 @@ +#[doc = "Register `U0_CHANGE_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `U0_CHANGE_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CNT_STEP_U0` reader - Configures the step value for unit 0."] +pub type CNT_STEP_U0_R = crate::FieldReader; +#[doc = "Field `CNT_STEP_U0` writer - Configures the step value for unit 0."] +pub type CNT_STEP_U0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CNT_STEP_LIM_U0` reader - Configures the step limit value for unit 0."] +pub type CNT_STEP_LIM_U0_R = crate::FieldReader; +#[doc = "Field `CNT_STEP_LIM_U0` writer - Configures the step limit value for unit 0."] +pub type CNT_STEP_LIM_U0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures the step value for unit 0."] + #[inline(always)] + pub fn cnt_step_u0(&self) -> CNT_STEP_U0_R { + CNT_STEP_U0_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Configures the step limit value for unit 0."] + #[inline(always)] + pub fn cnt_step_lim_u0(&self) -> CNT_STEP_LIM_U0_R { + CNT_STEP_LIM_U0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("U0_CHANGE_CONF") + .field( + "cnt_step_u0", + &format_args!("{}", self.cnt_step_u0().bits()), + ) + .field( + "cnt_step_lim_u0", + &format_args!("{}", self.cnt_step_lim_u0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures the step value for unit 0."] + #[inline(always)] + #[must_use] + pub fn cnt_step_u0(&mut self) -> CNT_STEP_U0_W { + CNT_STEP_U0_W::new(self, 0) + } + #[doc = "Bits 16:31 - Configures the step limit value for unit 0."] + #[inline(always)] + #[must_use] + pub fn cnt_step_lim_u0(&mut self) -> CNT_STEP_LIM_U0_W { + CNT_STEP_LIM_U0_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register for unit $n's step value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u0_change_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u0_change_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct U0_CHANGE_CONF_SPEC; +impl crate::RegisterSpec for U0_CHANGE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`u0_change_conf::R`](R) reader structure"] +impl crate::Readable for U0_CHANGE_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`u0_change_conf::W`](W) writer structure"] +impl crate::Writable for U0_CHANGE_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets U0_CHANGE_CONF to value 0"] +impl crate::Resettable for U0_CHANGE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt/u1_change_conf.rs b/esp32p4/src/pcnt/u1_change_conf.rs new file mode 100644 index 0000000000..b5f04cc909 --- /dev/null +++ b/esp32p4/src/pcnt/u1_change_conf.rs @@ -0,0 +1,85 @@ +#[doc = "Register `U1_CHANGE_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `U1_CHANGE_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CNT_STEP_U1` reader - Configures the step value for unit 1."] +pub type CNT_STEP_U1_R = crate::FieldReader; +#[doc = "Field `CNT_STEP_U1` writer - Configures the step value for unit 1."] +pub type CNT_STEP_U1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CNT_STEP_LIM_U1` reader - Configures the step limit value for unit 1."] +pub type CNT_STEP_LIM_U1_R = crate::FieldReader; +#[doc = "Field `CNT_STEP_LIM_U1` writer - Configures the step limit value for unit 1."] +pub type CNT_STEP_LIM_U1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures the step value for unit 1."] + #[inline(always)] + pub fn cnt_step_u1(&self) -> CNT_STEP_U1_R { + CNT_STEP_U1_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Configures the step limit value for unit 1."] + #[inline(always)] + pub fn cnt_step_lim_u1(&self) -> CNT_STEP_LIM_U1_R { + CNT_STEP_LIM_U1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("U1_CHANGE_CONF") + .field( + "cnt_step_u1", + &format_args!("{}", self.cnt_step_u1().bits()), + ) + .field( + "cnt_step_lim_u1", + &format_args!("{}", self.cnt_step_lim_u1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures the step value for unit 1."] + #[inline(always)] + #[must_use] + pub fn cnt_step_u1(&mut self) -> CNT_STEP_U1_W { + CNT_STEP_U1_W::new(self, 0) + } + #[doc = "Bits 16:31 - Configures the step limit value for unit 1."] + #[inline(always)] + #[must_use] + pub fn cnt_step_lim_u1(&mut self) -> CNT_STEP_LIM_U1_W { + CNT_STEP_LIM_U1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register for unit $n's step value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u1_change_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u1_change_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct U1_CHANGE_CONF_SPEC; +impl crate::RegisterSpec for U1_CHANGE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`u1_change_conf::R`](R) reader structure"] +impl crate::Readable for U1_CHANGE_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`u1_change_conf::W`](W) writer structure"] +impl crate::Writable for U1_CHANGE_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets U1_CHANGE_CONF to value 0"] +impl crate::Resettable for U1_CHANGE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt/u2_change_conf.rs b/esp32p4/src/pcnt/u2_change_conf.rs new file mode 100644 index 0000000000..12213470f2 --- /dev/null +++ b/esp32p4/src/pcnt/u2_change_conf.rs @@ -0,0 +1,85 @@ +#[doc = "Register `U2_CHANGE_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `U2_CHANGE_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CNT_STEP_U2` reader - Configures the step value for unit 2."] +pub type CNT_STEP_U2_R = crate::FieldReader; +#[doc = "Field `CNT_STEP_U2` writer - Configures the step value for unit 2."] +pub type CNT_STEP_U2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CNT_STEP_LIM_U2` reader - Configures the step limit value for unit 2."] +pub type CNT_STEP_LIM_U2_R = crate::FieldReader; +#[doc = "Field `CNT_STEP_LIM_U2` writer - Configures the step limit value for unit 2."] +pub type CNT_STEP_LIM_U2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures the step value for unit 2."] + #[inline(always)] + pub fn cnt_step_u2(&self) -> CNT_STEP_U2_R { + CNT_STEP_U2_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Configures the step limit value for unit 2."] + #[inline(always)] + pub fn cnt_step_lim_u2(&self) -> CNT_STEP_LIM_U2_R { + CNT_STEP_LIM_U2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("U2_CHANGE_CONF") + .field( + "cnt_step_u2", + &format_args!("{}", self.cnt_step_u2().bits()), + ) + .field( + "cnt_step_lim_u2", + &format_args!("{}", self.cnt_step_lim_u2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures the step value for unit 2."] + #[inline(always)] + #[must_use] + pub fn cnt_step_u2(&mut self) -> CNT_STEP_U2_W { + CNT_STEP_U2_W::new(self, 0) + } + #[doc = "Bits 16:31 - Configures the step limit value for unit 2."] + #[inline(always)] + #[must_use] + pub fn cnt_step_lim_u2(&mut self) -> CNT_STEP_LIM_U2_W { + CNT_STEP_LIM_U2_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register for unit $n's step value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u2_change_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u2_change_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct U2_CHANGE_CONF_SPEC; +impl crate::RegisterSpec for U2_CHANGE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`u2_change_conf::R`](R) reader structure"] +impl crate::Readable for U2_CHANGE_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`u2_change_conf::W`](W) writer structure"] +impl crate::Writable for U2_CHANGE_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets U2_CHANGE_CONF to value 0"] +impl crate::Resettable for U2_CHANGE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt/u3_change_conf.rs b/esp32p4/src/pcnt/u3_change_conf.rs new file mode 100644 index 0000000000..760060d757 --- /dev/null +++ b/esp32p4/src/pcnt/u3_change_conf.rs @@ -0,0 +1,85 @@ +#[doc = "Register `U3_CHANGE_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `U3_CHANGE_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CNT_STEP_U3` reader - Configures the step value for unit 3."] +pub type CNT_STEP_U3_R = crate::FieldReader; +#[doc = "Field `CNT_STEP_U3` writer - Configures the step value for unit 3."] +pub type CNT_STEP_U3_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CNT_STEP_LIM_U3` reader - Configures the step limit value for unit 3."] +pub type CNT_STEP_LIM_U3_R = crate::FieldReader; +#[doc = "Field `CNT_STEP_LIM_U3` writer - Configures the step limit value for unit 3."] +pub type CNT_STEP_LIM_U3_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures the step value for unit 3."] + #[inline(always)] + pub fn cnt_step_u3(&self) -> CNT_STEP_U3_R { + CNT_STEP_U3_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Configures the step limit value for unit 3."] + #[inline(always)] + pub fn cnt_step_lim_u3(&self) -> CNT_STEP_LIM_U3_R { + CNT_STEP_LIM_U3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("U3_CHANGE_CONF") + .field( + "cnt_step_u3", + &format_args!("{}", self.cnt_step_u3().bits()), + ) + .field( + "cnt_step_lim_u3", + &format_args!("{}", self.cnt_step_lim_u3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures the step value for unit 3."] + #[inline(always)] + #[must_use] + pub fn cnt_step_u3(&mut self) -> CNT_STEP_U3_W { + CNT_STEP_U3_W::new(self, 0) + } + #[doc = "Bits 16:31 - Configures the step limit value for unit 3."] + #[inline(always)] + #[must_use] + pub fn cnt_step_lim_u3(&mut self) -> CNT_STEP_LIM_U3_W { + CNT_STEP_LIM_U3_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register for unit $n's step value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u3_change_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u3_change_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct U3_CHANGE_CONF_SPEC; +impl crate::RegisterSpec for U3_CHANGE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`u3_change_conf::R`](R) reader structure"] +impl crate::Readable for U3_CHANGE_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`u3_change_conf::W`](W) writer structure"] +impl crate::Writable for U3_CHANGE_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets U3_CHANGE_CONF to value 0"] +impl crate::Resettable for U3_CHANGE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt/u_cnt.rs b/esp32p4/src/pcnt/u_cnt.rs new file mode 100644 index 0000000000..fe801f1d50 --- /dev/null +++ b/esp32p4/src/pcnt/u_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `U%s_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `PULSE_CNT_U` reader - This register stores the current pulse count value for unit %s."] +pub type PULSE_CNT_U_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - This register stores the current pulse count value for unit %s."] + #[inline(always)] + pub fn pulse_cnt_u(&self) -> PULSE_CNT_U_R { + PULSE_CNT_U_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("U_CNT") + .field( + "pulse_cnt_u", + &format_args!("{}", self.pulse_cnt_u().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Counter value for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct U_CNT_SPEC; +impl crate::RegisterSpec for U_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`u_cnt::R`](R) reader structure"] +impl crate::Readable for U_CNT_SPEC {} +#[doc = "`reset()` method sets U%s_CNT to value 0"] +impl crate::Resettable for U_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt/u_conf0.rs b/esp32p4/src/pcnt/u_conf0.rs new file mode 100644 index 0000000000..f5b8ec6eed --- /dev/null +++ b/esp32p4/src/pcnt/u_conf0.rs @@ -0,0 +1,329 @@ +#[doc = "Register `U%s_CONF0` reader"] +pub type R = crate::R; +#[doc = "Register `U%s_CONF0` writer"] +pub type W = crate::W; +#[doc = "Field `FILTER_THRES_U` reader - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."] +pub type FILTER_THRES_U_R = crate::FieldReader; +#[doc = "Field `FILTER_THRES_U` writer - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."] +pub type FILTER_THRES_U_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `FILTER_EN_U` reader - This is the enable bit for unit %s's input filter."] +pub type FILTER_EN_U_R = crate::BitReader; +#[doc = "Field `FILTER_EN_U` writer - This is the enable bit for unit %s's input filter."] +pub type FILTER_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THR_ZERO_EN_U` reader - This is the enable bit for unit %s's zero comparator."] +pub type THR_ZERO_EN_U_R = crate::BitReader; +#[doc = "Field `THR_ZERO_EN_U` writer - This is the enable bit for unit %s's zero comparator."] +pub type THR_ZERO_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THR_H_LIM_EN_U` reader - This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt."] +pub type THR_H_LIM_EN_U_R = crate::BitReader; +#[doc = "Field `THR_H_LIM_EN_U` writer - This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt."] +pub type THR_H_LIM_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THR_L_LIM_EN_U` reader - This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt."] +pub type THR_L_LIM_EN_U_R = crate::BitReader; +#[doc = "Field `THR_L_LIM_EN_U` writer - This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt."] +pub type THR_L_LIM_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THR_THRES0_EN_U` reader - This is the enable bit for unit %s's thres0 comparator."] +pub type THR_THRES0_EN_U_R = crate::BitReader; +#[doc = "Field `THR_THRES0_EN_U` writer - This is the enable bit for unit %s's thres0 comparator."] +pub type THR_THRES0_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THR_THRES1_EN_U` reader - This is the enable bit for unit %s's thres1 comparator."] +pub type THR_THRES1_EN_U_R = crate::BitReader; +#[doc = "Field `THR_THRES1_EN_U` writer - This is the enable bit for unit %s's thres1 comparator."] +pub type THR_THRES1_EN_U_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH0_NEG_MODE_U` reader - This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"] +pub type CH0_NEG_MODE_U_R = crate::FieldReader; +#[doc = "Field `CH0_NEG_MODE_U` writer - This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"] +pub type CH0_NEG_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH0_POS_MODE_U` reader - This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"] +pub type CH0_POS_MODE_U_R = crate::FieldReader; +#[doc = "Field `CH0_POS_MODE_U` writer - This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"] +pub type CH0_POS_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH0_HCTRL_MODE_U` reader - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] +pub type CH0_HCTRL_MODE_U_R = crate::FieldReader; +#[doc = "Field `CH0_HCTRL_MODE_U` writer - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] +pub type CH0_HCTRL_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH0_LCTRL_MODE_U` reader - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] +pub type CH0_LCTRL_MODE_U_R = crate::FieldReader; +#[doc = "Field `CH0_LCTRL_MODE_U` writer - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] +pub type CH0_LCTRL_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH1_NEG_MODE_U` reader - This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"] +pub type CH1_NEG_MODE_U_R = crate::FieldReader; +#[doc = "Field `CH1_NEG_MODE_U` writer - This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"] +pub type CH1_NEG_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH1_POS_MODE_U` reader - This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"] +pub type CH1_POS_MODE_U_R = crate::FieldReader; +#[doc = "Field `CH1_POS_MODE_U` writer - This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"] +pub type CH1_POS_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH1_HCTRL_MODE_U` reader - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] +pub type CH1_HCTRL_MODE_U_R = crate::FieldReader; +#[doc = "Field `CH1_HCTRL_MODE_U` writer - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] +pub type CH1_HCTRL_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CH1_LCTRL_MODE_U` reader - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] +pub type CH1_LCTRL_MODE_U_R = crate::FieldReader; +#[doc = "Field `CH1_LCTRL_MODE_U` writer - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] +pub type CH1_LCTRL_MODE_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."] + #[inline(always)] + pub fn filter_thres_u(&self) -> FILTER_THRES_U_R { + FILTER_THRES_U_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bit 10 - This is the enable bit for unit %s's input filter."] + #[inline(always)] + pub fn filter_en_u(&self) -> FILTER_EN_U_R { + FILTER_EN_U_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - This is the enable bit for unit %s's zero comparator."] + #[inline(always)] + pub fn thr_zero_en_u(&self) -> THR_ZERO_EN_U_R { + THR_ZERO_EN_U_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt."] + #[inline(always)] + pub fn thr_h_lim_en_u(&self) -> THR_H_LIM_EN_U_R { + THR_H_LIM_EN_U_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt."] + #[inline(always)] + pub fn thr_l_lim_en_u(&self) -> THR_L_LIM_EN_U_R { + THR_L_LIM_EN_U_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - This is the enable bit for unit %s's thres0 comparator."] + #[inline(always)] + pub fn thr_thres0_en_u(&self) -> THR_THRES0_EN_U_R { + THR_THRES0_EN_U_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - This is the enable bit for unit %s's thres1 comparator."] + #[inline(always)] + pub fn thr_thres1_en_u(&self) -> THR_THRES1_EN_U_R { + THR_THRES1_EN_U_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:17 - This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"] + #[inline(always)] + pub fn ch0_neg_mode_u(&self) -> CH0_NEG_MODE_U_R { + CH0_NEG_MODE_U_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"] + #[inline(always)] + pub fn ch0_pos_mode_u(&self) -> CH0_POS_MODE_U_R { + CH0_POS_MODE_U_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] + #[inline(always)] + pub fn ch0_hctrl_mode_u(&self) -> CH0_HCTRL_MODE_U_R { + CH0_HCTRL_MODE_U_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] + #[inline(always)] + pub fn ch0_lctrl_mode_u(&self) -> CH0_LCTRL_MODE_U_R { + CH0_LCTRL_MODE_U_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"] + #[inline(always)] + pub fn ch1_neg_mode_u(&self) -> CH1_NEG_MODE_U_R { + CH1_NEG_MODE_U_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"] + #[inline(always)] + pub fn ch1_pos_mode_u(&self) -> CH1_POS_MODE_U_R { + CH1_POS_MODE_U_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] + #[inline(always)] + pub fn ch1_hctrl_mode_u(&self) -> CH1_HCTRL_MODE_U_R { + CH1_HCTRL_MODE_U_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] + #[inline(always)] + pub fn ch1_lctrl_mode_u(&self) -> CH1_LCTRL_MODE_U_R { + CH1_LCTRL_MODE_U_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("U_CONF0") + .field( + "filter_thres_u", + &format_args!("{}", self.filter_thres_u().bits()), + ) + .field("filter_en_u", &format_args!("{}", self.filter_en_u().bit())) + .field( + "thr_zero_en_u", + &format_args!("{}", self.thr_zero_en_u().bit()), + ) + .field( + "thr_h_lim_en_u", + &format_args!("{}", self.thr_h_lim_en_u().bit()), + ) + .field( + "thr_l_lim_en_u", + &format_args!("{}", self.thr_l_lim_en_u().bit()), + ) + .field( + "thr_thres0_en_u", + &format_args!("{}", self.thr_thres0_en_u().bit()), + ) + .field( + "thr_thres1_en_u", + &format_args!("{}", self.thr_thres1_en_u().bit()), + ) + .field( + "ch0_neg_mode_u", + &format_args!("{}", self.ch0_neg_mode_u().bits()), + ) + .field( + "ch0_pos_mode_u", + &format_args!("{}", self.ch0_pos_mode_u().bits()), + ) + .field( + "ch0_hctrl_mode_u", + &format_args!("{}", self.ch0_hctrl_mode_u().bits()), + ) + .field( + "ch0_lctrl_mode_u", + &format_args!("{}", self.ch0_lctrl_mode_u().bits()), + ) + .field( + "ch1_neg_mode_u", + &format_args!("{}", self.ch1_neg_mode_u().bits()), + ) + .field( + "ch1_pos_mode_u", + &format_args!("{}", self.ch1_pos_mode_u().bits()), + ) + .field( + "ch1_hctrl_mode_u", + &format_args!("{}", self.ch1_hctrl_mode_u().bits()), + ) + .field( + "ch1_lctrl_mode_u", + &format_args!("{}", self.ch1_lctrl_mode_u().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."] + #[inline(always)] + #[must_use] + pub fn filter_thres_u(&mut self) -> FILTER_THRES_U_W { + FILTER_THRES_U_W::new(self, 0) + } + #[doc = "Bit 10 - This is the enable bit for unit %s's input filter."] + #[inline(always)] + #[must_use] + pub fn filter_en_u(&mut self) -> FILTER_EN_U_W { + FILTER_EN_U_W::new(self, 10) + } + #[doc = "Bit 11 - This is the enable bit for unit %s's zero comparator."] + #[inline(always)] + #[must_use] + pub fn thr_zero_en_u(&mut self) -> THR_ZERO_EN_U_W { + THR_ZERO_EN_U_W::new(self, 11) + } + #[doc = "Bit 12 - This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt."] + #[inline(always)] + #[must_use] + pub fn thr_h_lim_en_u(&mut self) -> THR_H_LIM_EN_U_W { + THR_H_LIM_EN_U_W::new(self, 12) + } + #[doc = "Bit 13 - This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt."] + #[inline(always)] + #[must_use] + pub fn thr_l_lim_en_u(&mut self) -> THR_L_LIM_EN_U_W { + THR_L_LIM_EN_U_W::new(self, 13) + } + #[doc = "Bit 14 - This is the enable bit for unit %s's thres0 comparator."] + #[inline(always)] + #[must_use] + pub fn thr_thres0_en_u(&mut self) -> THR_THRES0_EN_U_W { + THR_THRES0_EN_U_W::new(self, 14) + } + #[doc = "Bit 15 - This is the enable bit for unit %s's thres1 comparator."] + #[inline(always)] + #[must_use] + pub fn thr_thres1_en_u(&mut self) -> THR_THRES1_EN_U_W { + THR_THRES1_EN_U_W::new(self, 15) + } + #[doc = "Bits 16:17 - This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"] + #[inline(always)] + #[must_use] + pub fn ch0_neg_mode_u(&mut self) -> CH0_NEG_MODE_U_W { + CH0_NEG_MODE_U_W::new(self, 16) + } + #[doc = "Bits 18:19 - This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter"] + #[inline(always)] + #[must_use] + pub fn ch0_pos_mode_u(&mut self) -> CH0_POS_MODE_U_W { + CH0_POS_MODE_U_W::new(self, 18) + } + #[doc = "Bits 20:21 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] + #[inline(always)] + #[must_use] + pub fn ch0_hctrl_mode_u(&mut self) -> CH0_HCTRL_MODE_U_W { + CH0_HCTRL_MODE_U_W::new(self, 20) + } + #[doc = "Bits 22:23 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] + #[inline(always)] + #[must_use] + pub fn ch0_lctrl_mode_u(&mut self) -> CH0_LCTRL_MODE_U_W { + CH0_LCTRL_MODE_U_W::new(self, 22) + } + #[doc = "Bits 24:25 - This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"] + #[inline(always)] + #[must_use] + pub fn ch1_neg_mode_u(&mut self) -> CH1_NEG_MODE_U_W { + CH1_NEG_MODE_U_W::new(self, 24) + } + #[doc = "Bits 26:27 - This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter"] + #[inline(always)] + #[must_use] + pub fn ch1_pos_mode_u(&mut self) -> CH1_POS_MODE_U_W { + CH1_POS_MODE_U_W::new(self, 26) + } + #[doc = "Bits 28:29 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] + #[inline(always)] + #[must_use] + pub fn ch1_hctrl_mode_u(&mut self) -> CH1_HCTRL_MODE_U_W { + CH1_HCTRL_MODE_U_W::new(self, 28) + } + #[doc = "Bits 30:31 - This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification"] + #[inline(always)] + #[must_use] + pub fn ch1_lctrl_mode_u(&mut self) -> CH1_LCTRL_MODE_U_W { + CH1_LCTRL_MODE_U_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register 0 for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct U_CONF0_SPEC; +impl crate::RegisterSpec for U_CONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`u_conf0::R`](R) reader structure"] +impl crate::Readable for U_CONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`u_conf0::W`](W) writer structure"] +impl crate::Writable for U_CONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets U%s_CONF0 to value 0x3c10"] +impl crate::Resettable for U_CONF0_SPEC { + const RESET_VALUE: Self::Ux = 0x3c10; +} diff --git a/esp32p4/src/pcnt/u_conf1.rs b/esp32p4/src/pcnt/u_conf1.rs new file mode 100644 index 0000000000..930c2893dc --- /dev/null +++ b/esp32p4/src/pcnt/u_conf1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `U%s_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `U%s_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `CNT_THRES0_U` reader - This register is used to configure the thres0 value for unit %s."] +pub type CNT_THRES0_U_R = crate::FieldReader; +#[doc = "Field `CNT_THRES0_U` writer - This register is used to configure the thres0 value for unit %s."] +pub type CNT_THRES0_U_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CNT_THRES1_U` reader - This register is used to configure the thres1 value for unit %s."] +pub type CNT_THRES1_U_R = crate::FieldReader; +#[doc = "Field `CNT_THRES1_U` writer - This register is used to configure the thres1 value for unit %s."] +pub type CNT_THRES1_U_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to configure the thres0 value for unit %s."] + #[inline(always)] + pub fn cnt_thres0_u(&self) -> CNT_THRES0_U_R { + CNT_THRES0_U_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - This register is used to configure the thres1 value for unit %s."] + #[inline(always)] + pub fn cnt_thres1_u(&self) -> CNT_THRES1_U_R { + CNT_THRES1_U_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("U_CONF1") + .field( + "cnt_thres0_u", + &format_args!("{}", self.cnt_thres0_u().bits()), + ) + .field( + "cnt_thres1_u", + &format_args!("{}", self.cnt_thres1_u().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to configure the thres0 value for unit %s."] + #[inline(always)] + #[must_use] + pub fn cnt_thres0_u(&mut self) -> CNT_THRES0_U_W { + CNT_THRES0_U_W::new(self, 0) + } + #[doc = "Bits 16:31 - This register is used to configure the thres1 value for unit %s."] + #[inline(always)] + #[must_use] + pub fn cnt_thres1_u(&mut self) -> CNT_THRES1_U_W { + CNT_THRES1_U_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register 1 for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct U_CONF1_SPEC; +impl crate::RegisterSpec for U_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`u_conf1::R`](R) reader structure"] +impl crate::Readable for U_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`u_conf1::W`](W) writer structure"] +impl crate::Writable for U_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets U%s_CONF1 to value 0"] +impl crate::Resettable for U_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt/u_conf2.rs b/esp32p4/src/pcnt/u_conf2.rs new file mode 100644 index 0000000000..7953b30cc7 --- /dev/null +++ b/esp32p4/src/pcnt/u_conf2.rs @@ -0,0 +1,85 @@ +#[doc = "Register `U%s_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `U%s_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `CNT_H_LIM_U` reader - This register is used to configure the thr_h_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0."] +pub type CNT_H_LIM_U_R = crate::FieldReader; +#[doc = "Field `CNT_H_LIM_U` writer - This register is used to configure the thr_h_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0."] +pub type CNT_H_LIM_U_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CNT_L_LIM_U` reader - This register is used to configure the thr_l_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0."] +pub type CNT_L_LIM_U_R = crate::FieldReader; +#[doc = "Field `CNT_L_LIM_U` writer - This register is used to configure the thr_l_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0."] +pub type CNT_L_LIM_U_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to configure the thr_h_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0."] + #[inline(always)] + pub fn cnt_h_lim_u(&self) -> CNT_H_LIM_U_R { + CNT_H_LIM_U_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - This register is used to configure the thr_l_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0."] + #[inline(always)] + pub fn cnt_l_lim_u(&self) -> CNT_L_LIM_U_R { + CNT_L_LIM_U_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("U_CONF2") + .field( + "cnt_h_lim_u", + &format_args!("{}", self.cnt_h_lim_u().bits()), + ) + .field( + "cnt_l_lim_u", + &format_args!("{}", self.cnt_l_lim_u().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to configure the thr_h_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0."] + #[inline(always)] + #[must_use] + pub fn cnt_h_lim_u(&mut self) -> CNT_H_LIM_U_W { + CNT_H_LIM_U_W::new(self, 0) + } + #[doc = "Bits 16:31 - This register is used to configure the thr_l_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0."] + #[inline(always)] + #[must_use] + pub fn cnt_l_lim_u(&mut self) -> CNT_L_LIM_U_W { + CNT_L_LIM_U_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register 2 for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`u_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct U_CONF2_SPEC; +impl crate::RegisterSpec for U_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`u_conf2::R`](R) reader structure"] +impl crate::Readable for U_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`u_conf2::W`](W) writer structure"] +impl crate::Writable for U_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets U%s_CONF2 to value 0"] +impl crate::Resettable for U_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pcnt/u_status.rs b/esp32p4/src/pcnt/u_status.rs new file mode 100644 index 0000000000..b9afc51de8 --- /dev/null +++ b/esp32p4/src/pcnt/u_status.rs @@ -0,0 +1,94 @@ +#[doc = "Register `U%s_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `CNT_THR_ZERO_MODE_U` reader - The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive."] +pub type CNT_THR_ZERO_MODE_U_R = crate::FieldReader; +#[doc = "Field `CNT_THR_THRES1_LAT_U` reader - The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others"] +pub type CNT_THR_THRES1_LAT_U_R = crate::BitReader; +#[doc = "Field `CNT_THR_THRES0_LAT_U` reader - The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others"] +pub type CNT_THR_THRES0_LAT_U_R = crate::BitReader; +#[doc = "Field `CNT_THR_L_LIM_LAT_U` reader - The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others"] +pub type CNT_THR_L_LIM_LAT_U_R = crate::BitReader; +#[doc = "Field `CNT_THR_H_LIM_LAT_U` reader - The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others"] +pub type CNT_THR_H_LIM_LAT_U_R = crate::BitReader; +#[doc = "Field `CNT_THR_ZERO_LAT_U` reader - The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others"] +pub type CNT_THR_ZERO_LAT_U_R = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive."] + #[inline(always)] + pub fn cnt_thr_zero_mode_u(&self) -> CNT_THR_ZERO_MODE_U_R { + CNT_THR_ZERO_MODE_U_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others"] + #[inline(always)] + pub fn cnt_thr_thres1_lat_u(&self) -> CNT_THR_THRES1_LAT_U_R { + CNT_THR_THRES1_LAT_U_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others"] + #[inline(always)] + pub fn cnt_thr_thres0_lat_u(&self) -> CNT_THR_THRES0_LAT_U_R { + CNT_THR_THRES0_LAT_U_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others"] + #[inline(always)] + pub fn cnt_thr_l_lim_lat_u(&self) -> CNT_THR_L_LIM_LAT_U_R { + CNT_THR_L_LIM_LAT_U_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others"] + #[inline(always)] + pub fn cnt_thr_h_lim_lat_u(&self) -> CNT_THR_H_LIM_LAT_U_R { + CNT_THR_H_LIM_LAT_U_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others"] + #[inline(always)] + pub fn cnt_thr_zero_lat_u(&self) -> CNT_THR_ZERO_LAT_U_R { + CNT_THR_ZERO_LAT_U_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("U_STATUS") + .field( + "cnt_thr_zero_mode_u", + &format_args!("{}", self.cnt_thr_zero_mode_u().bits()), + ) + .field( + "cnt_thr_thres1_lat_u", + &format_args!("{}", self.cnt_thr_thres1_lat_u().bit()), + ) + .field( + "cnt_thr_thres0_lat_u", + &format_args!("{}", self.cnt_thr_thres0_lat_u().bit()), + ) + .field( + "cnt_thr_l_lim_lat_u", + &format_args!("{}", self.cnt_thr_l_lim_lat_u().bit()), + ) + .field( + "cnt_thr_h_lim_lat_u", + &format_args!("{}", self.cnt_thr_h_lim_lat_u().bit()), + ) + .field( + "cnt_thr_zero_lat_u", + &format_args!("{}", self.cnt_thr_zero_lat_u().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "PNCT UNIT%s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct U_STATUS_SPEC; +impl crate::RegisterSpec for U_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`u_status::R`](R) reader structure"] +impl crate::Readable for U_STATUS_SPEC {} +#[doc = "`reset()` method sets U%s_STATUS to value 0"] +impl crate::Resettable for U_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu.rs b/esp32p4/src/pmu.rs new file mode 100644 index 0000000000..1c6e66595c --- /dev/null +++ b/esp32p4/src/pmu.rs @@ -0,0 +1,1362 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + hp_active_dig_power: HP_ACTIVE_DIG_POWER, + hp_active_icg_hp_func: HP_ACTIVE_ICG_HP_FUNC, + hp_active_icg_hp_apb: HP_ACTIVE_ICG_HP_APB, + hp_active_icg_modem: HP_ACTIVE_ICG_MODEM, + hp_active_hp_sys_cntl: HP_ACTIVE_HP_SYS_CNTL, + hp_active_hp_ck_power: HP_ACTIVE_HP_CK_POWER, + hp_active_bias: HP_ACTIVE_BIAS, + hp_active_backup: HP_ACTIVE_BACKUP, + hp_active_backup_clk: HP_ACTIVE_BACKUP_CLK, + hp_active_sysclk: HP_ACTIVE_SYSCLK, + hp_active_hp_regulator0: HP_ACTIVE_HP_REGULATOR0, + hp_active_hp_regulator1: HP_ACTIVE_HP_REGULATOR1, + hp_active_xtal: HP_ACTIVE_XTAL, + hp_modem_dig_power: HP_MODEM_DIG_POWER, + hp_modem_icg_hp_func: HP_MODEM_ICG_HP_FUNC, + hp_modem_icg_hp_apb: HP_MODEM_ICG_HP_APB, + hp_modem_icg_modem: HP_MODEM_ICG_MODEM, + hp_modem_hp_sys_cntl: HP_MODEM_HP_SYS_CNTL, + hp_modem_hp_ck_power: HP_MODEM_HP_CK_POWER, + hp_modem_bias: HP_MODEM_BIAS, + hp_modem_backup: HP_MODEM_BACKUP, + hp_modem_backup_clk: HP_MODEM_BACKUP_CLK, + hp_modem_sysclk: HP_MODEM_SYSCLK, + hp_modem_hp_regulator0: HP_MODEM_HP_REGULATOR0, + hp_modem_hp_regulator1: HP_MODEM_HP_REGULATOR1, + hp_modem_xtal: HP_MODEM_XTAL, + hp_sleep_dig_power: HP_SLEEP_DIG_POWER, + hp_sleep_icg_hp_func: HP_SLEEP_ICG_HP_FUNC, + hp_sleep_icg_hp_apb: HP_SLEEP_ICG_HP_APB, + hp_sleep_icg_modem: HP_SLEEP_ICG_MODEM, + hp_sleep_hp_sys_cntl: HP_SLEEP_HP_SYS_CNTL, + hp_sleep_hp_ck_power: HP_SLEEP_HP_CK_POWER, + hp_sleep_bias: HP_SLEEP_BIAS, + hp_sleep_backup: HP_SLEEP_BACKUP, + hp_sleep_backup_clk: HP_SLEEP_BACKUP_CLK, + hp_sleep_sysclk: HP_SLEEP_SYSCLK, + hp_sleep_hp_regulator0: HP_SLEEP_HP_REGULATOR0, + hp_sleep_hp_regulator1: HP_SLEEP_HP_REGULATOR1, + hp_sleep_xtal: HP_SLEEP_XTAL, + hp_sleep_lp_regulator0: HP_SLEEP_LP_REGULATOR0, + hp_sleep_lp_regulator1: HP_SLEEP_LP_REGULATOR1, + hp_sleep_lp_dcdc_reserve: HP_SLEEP_LP_DCDC_RESERVE, + hp_sleep_lp_dig_power: HP_SLEEP_LP_DIG_POWER, + hp_sleep_lp_ck_power: HP_SLEEP_LP_CK_POWER, + lp_sleep_lp_bias_reserve: LP_SLEEP_LP_BIAS_RESERVE, + lp_sleep_lp_regulator0: LP_SLEEP_LP_REGULATOR0, + lp_sleep_lp_regulator1: LP_SLEEP_LP_REGULATOR1, + lp_sleep_xtal: LP_SLEEP_XTAL, + lp_sleep_lp_dig_power: LP_SLEEP_LP_DIG_POWER, + lp_sleep_lp_ck_power: LP_SLEEP_LP_CK_POWER, + lp_sleep_bias: LP_SLEEP_BIAS, + imm_hp_ck_power: IMM_HP_CK_POWER, + imm_sleep_sysclk: IMM_SLEEP_SYSCLK, + imm_hp_func_icg: IMM_HP_FUNC_ICG, + imm_hp_apb_icg: IMM_HP_APB_ICG, + imm_modem_icg: IMM_MODEM_ICG, + imm_lp_icg: IMM_LP_ICG, + imm_pad_hold_all: IMM_PAD_HOLD_ALL, + imm_i2c_iso: IMM_I2C_ISO, + power_wait_timer0: POWER_WAIT_TIMER0, + power_wait_timer1: POWER_WAIT_TIMER1, + power_pd_top_cntl: POWER_PD_TOP_CNTL, + power_pd_cnnt_cntl: POWER_PD_CNNT_CNTL, + power_pd_hpmem_cntl: POWER_PD_HPMEM_CNTL, + power_pd_top_mask: POWER_PD_TOP_MASK, + power_pd_cnnt_mask: POWER_PD_CNNT_MASK, + power_pd_hpmem_mask: POWER_PD_HPMEM_MASK, + power_dcdc_switch: POWER_DCDC_SWITCH, + power_pd_lpperi_cntl: POWER_PD_LPPERI_CNTL, + power_pd_lpperi_mask: POWER_PD_LPPERI_MASK, + power_hp_pad: POWER_HP_PAD, + power_ck_wait_cntl: POWER_CK_WAIT_CNTL, + slp_wakeup_cntl0: SLP_WAKEUP_CNTL0, + slp_wakeup_cntl1: SLP_WAKEUP_CNTL1, + slp_wakeup_cntl2: SLP_WAKEUP_CNTL2, + slp_wakeup_cntl3: SLP_WAKEUP_CNTL3, + slp_wakeup_cntl4: SLP_WAKEUP_CNTL4, + slp_wakeup_cntl5: SLP_WAKEUP_CNTL5, + slp_wakeup_cntl6: SLP_WAKEUP_CNTL6, + slp_wakeup_cntl7: SLP_WAKEUP_CNTL7, + slp_wakeup_cntl8: SLP_WAKEUP_CNTL8, + slp_wakeup_status0: SLP_WAKEUP_STATUS0, + slp_wakeup_status1: SLP_WAKEUP_STATUS1, + slp_wakeup_status2: SLP_WAKEUP_STATUS2, + hp_ck_poweron: HP_CK_POWERON, + hp_ck_cntl: HP_CK_CNTL, + por_status: POR_STATUS, + rf_pwc: RF_PWC, + backup_cfg: BACKUP_CFG, + int_raw: INT_RAW, + hp_int_st: HP_INT_ST, + hp_int_ena: HP_INT_ENA, + hp_int_clr: HP_INT_CLR, + lp_int_raw: LP_INT_RAW, + lp_int_st: LP_INT_ST, + lp_int_ena: LP_INT_ENA, + lp_int_clr: LP_INT_CLR, + lp_cpu_pwr0: LP_CPU_PWR0, + lp_cpu_pwr1: LP_CPU_PWR1, + lp_cpu_pwr2: LP_CPU_PWR2, + lp_cpu_pwr3: LP_CPU_PWR3, + lp_cpu_pwr4: LP_CPU_PWR4, + lp_cpu_pwr5: LP_CPU_PWR5, + hp_lp_cpu_comm: HP_LP_CPU_COMM, + hp_regulator_cfg: HP_REGULATOR_CFG, + main_state: MAIN_STATE, + pwr_state: PWR_STATE, + clk_state0: CLK_STATE0, + clk_state1: CLK_STATE1, + clk_state2: CLK_STATE2, + ext_ldo_p0_0p1a: EXT_LDO_P0_0P1A, + ext_ldo_p0_0p1a_ana: EXT_LDO_P0_0P1A_ANA, + ext_ldo_p0_0p2a: EXT_LDO_P0_0P2A, + ext_ldo_p0_0p2a_ana: EXT_LDO_P0_0P2A_ANA, + ext_ldo_p0_0p3a: EXT_LDO_P0_0P3A, + ext_ldo_p0_0p3a_ana: EXT_LDO_P0_0P3A_ANA, + ext_ldo_p1_0p1a: EXT_LDO_P1_0P1A, + ext_ldo_p1_0p1a_ana: EXT_LDO_P1_0P1A_ANA, + ext_ldo_p1_0p2a: EXT_LDO_P1_0P2A, + ext_ldo_p1_0p2a_ana: EXT_LDO_P1_0P2A_ANA, + ext_ldo_p1_0p3a: EXT_LDO_P1_0P3A, + ext_ldo_p1_0p3a_ana: EXT_LDO_P1_0P3A_ANA, + ext_wakeup_lv: EXT_WAKEUP_LV, + ext_wakeup_sel: EXT_WAKEUP_SEL, + ext_wakeup_st: EXT_WAKEUP_ST, + ext_wakeup_cntl: EXT_WAKEUP_CNTL, + sdio_wakeup_cntl: SDIO_WAKEUP_CNTL, + xtal_slp: XTAL_SLP, + cpu_sw_stall: CPU_SW_STALL, + dcm_ctrl: DCM_CTRL, + dcm_wait_delay: DCM_WAIT_DELAY, + vddbat_cfg: VDDBAT_CFG, + touch_pwr_cntl: TOUCH_PWR_CNTL, + rdn_eco: RDN_ECO, + _reserved134: [u8; 0x01e4], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - need_des"] + #[inline(always)] + pub const fn hp_active_dig_power(&self) -> &HP_ACTIVE_DIG_POWER { + &self.hp_active_dig_power + } + #[doc = "0x04 - need_des"] + #[inline(always)] + pub const fn hp_active_icg_hp_func(&self) -> &HP_ACTIVE_ICG_HP_FUNC { + &self.hp_active_icg_hp_func + } + #[doc = "0x08 - need_des"] + #[inline(always)] + pub const fn hp_active_icg_hp_apb(&self) -> &HP_ACTIVE_ICG_HP_APB { + &self.hp_active_icg_hp_apb + } + #[doc = "0x0c - need_des"] + #[inline(always)] + pub const fn hp_active_icg_modem(&self) -> &HP_ACTIVE_ICG_MODEM { + &self.hp_active_icg_modem + } + #[doc = "0x10 - need_des"] + #[inline(always)] + pub const fn hp_active_hp_sys_cntl(&self) -> &HP_ACTIVE_HP_SYS_CNTL { + &self.hp_active_hp_sys_cntl + } + #[doc = "0x14 - need_des"] + #[inline(always)] + pub const fn hp_active_hp_ck_power(&self) -> &HP_ACTIVE_HP_CK_POWER { + &self.hp_active_hp_ck_power + } + #[doc = "0x18 - need_des"] + #[inline(always)] + pub const fn hp_active_bias(&self) -> &HP_ACTIVE_BIAS { + &self.hp_active_bias + } + #[doc = "0x1c - need_des"] + #[inline(always)] + pub const fn hp_active_backup(&self) -> &HP_ACTIVE_BACKUP { + &self.hp_active_backup + } + #[doc = "0x20 - need_des"] + #[inline(always)] + pub const fn hp_active_backup_clk(&self) -> &HP_ACTIVE_BACKUP_CLK { + &self.hp_active_backup_clk + } + #[doc = "0x24 - need_des"] + #[inline(always)] + pub const fn hp_active_sysclk(&self) -> &HP_ACTIVE_SYSCLK { + &self.hp_active_sysclk + } + #[doc = "0x28 - need_des"] + #[inline(always)] + pub const fn hp_active_hp_regulator0(&self) -> &HP_ACTIVE_HP_REGULATOR0 { + &self.hp_active_hp_regulator0 + } + #[doc = "0x2c - need_des"] + #[inline(always)] + pub const fn hp_active_hp_regulator1(&self) -> &HP_ACTIVE_HP_REGULATOR1 { + &self.hp_active_hp_regulator1 + } + #[doc = "0x30 - need_des"] + #[inline(always)] + pub const fn hp_active_xtal(&self) -> &HP_ACTIVE_XTAL { + &self.hp_active_xtal + } + #[doc = "0x34 - need_des"] + #[inline(always)] + pub const fn hp_modem_dig_power(&self) -> &HP_MODEM_DIG_POWER { + &self.hp_modem_dig_power + } + #[doc = "0x38 - need_des"] + #[inline(always)] + pub const fn hp_modem_icg_hp_func(&self) -> &HP_MODEM_ICG_HP_FUNC { + &self.hp_modem_icg_hp_func + } + #[doc = "0x3c - need_des"] + #[inline(always)] + pub const fn hp_modem_icg_hp_apb(&self) -> &HP_MODEM_ICG_HP_APB { + &self.hp_modem_icg_hp_apb + } + #[doc = "0x40 - need_des"] + #[inline(always)] + pub const fn hp_modem_icg_modem(&self) -> &HP_MODEM_ICG_MODEM { + &self.hp_modem_icg_modem + } + #[doc = "0x44 - need_des"] + #[inline(always)] + pub const fn hp_modem_hp_sys_cntl(&self) -> &HP_MODEM_HP_SYS_CNTL { + &self.hp_modem_hp_sys_cntl + } + #[doc = "0x48 - need_des"] + #[inline(always)] + pub const fn hp_modem_hp_ck_power(&self) -> &HP_MODEM_HP_CK_POWER { + &self.hp_modem_hp_ck_power + } + #[doc = "0x4c - need_des"] + #[inline(always)] + pub const fn hp_modem_bias(&self) -> &HP_MODEM_BIAS { + &self.hp_modem_bias + } + #[doc = "0x50 - need_des"] + #[inline(always)] + pub const fn hp_modem_backup(&self) -> &HP_MODEM_BACKUP { + &self.hp_modem_backup + } + #[doc = "0x54 - need_des"] + #[inline(always)] + pub const fn hp_modem_backup_clk(&self) -> &HP_MODEM_BACKUP_CLK { + &self.hp_modem_backup_clk + } + #[doc = "0x58 - need_des"] + #[inline(always)] + pub const fn hp_modem_sysclk(&self) -> &HP_MODEM_SYSCLK { + &self.hp_modem_sysclk + } + #[doc = "0x5c - need_des"] + #[inline(always)] + pub const fn hp_modem_hp_regulator0(&self) -> &HP_MODEM_HP_REGULATOR0 { + &self.hp_modem_hp_regulator0 + } + #[doc = "0x60 - need_des"] + #[inline(always)] + pub const fn hp_modem_hp_regulator1(&self) -> &HP_MODEM_HP_REGULATOR1 { + &self.hp_modem_hp_regulator1 + } + #[doc = "0x64 - need_des"] + #[inline(always)] + pub const fn hp_modem_xtal(&self) -> &HP_MODEM_XTAL { + &self.hp_modem_xtal + } + #[doc = "0x68 - need_des"] + #[inline(always)] + pub const fn hp_sleep_dig_power(&self) -> &HP_SLEEP_DIG_POWER { + &self.hp_sleep_dig_power + } + #[doc = "0x6c - need_des"] + #[inline(always)] + pub const fn hp_sleep_icg_hp_func(&self) -> &HP_SLEEP_ICG_HP_FUNC { + &self.hp_sleep_icg_hp_func + } + #[doc = "0x70 - need_des"] + #[inline(always)] + pub const fn hp_sleep_icg_hp_apb(&self) -> &HP_SLEEP_ICG_HP_APB { + &self.hp_sleep_icg_hp_apb + } + #[doc = "0x74 - need_des"] + #[inline(always)] + pub const fn hp_sleep_icg_modem(&self) -> &HP_SLEEP_ICG_MODEM { + &self.hp_sleep_icg_modem + } + #[doc = "0x78 - need_des"] + #[inline(always)] + pub const fn hp_sleep_hp_sys_cntl(&self) -> &HP_SLEEP_HP_SYS_CNTL { + &self.hp_sleep_hp_sys_cntl + } + #[doc = "0x7c - need_des"] + #[inline(always)] + pub const fn hp_sleep_hp_ck_power(&self) -> &HP_SLEEP_HP_CK_POWER { + &self.hp_sleep_hp_ck_power + } + #[doc = "0x80 - need_des"] + #[inline(always)] + pub const fn hp_sleep_bias(&self) -> &HP_SLEEP_BIAS { + &self.hp_sleep_bias + } + #[doc = "0x84 - need_des"] + #[inline(always)] + pub const fn hp_sleep_backup(&self) -> &HP_SLEEP_BACKUP { + &self.hp_sleep_backup + } + #[doc = "0x88 - need_des"] + #[inline(always)] + pub const fn hp_sleep_backup_clk(&self) -> &HP_SLEEP_BACKUP_CLK { + &self.hp_sleep_backup_clk + } + #[doc = "0x8c - need_des"] + #[inline(always)] + pub const fn hp_sleep_sysclk(&self) -> &HP_SLEEP_SYSCLK { + &self.hp_sleep_sysclk + } + #[doc = "0x90 - need_des"] + #[inline(always)] + pub const fn hp_sleep_hp_regulator0(&self) -> &HP_SLEEP_HP_REGULATOR0 { + &self.hp_sleep_hp_regulator0 + } + #[doc = "0x94 - need_des"] + #[inline(always)] + pub const fn hp_sleep_hp_regulator1(&self) -> &HP_SLEEP_HP_REGULATOR1 { + &self.hp_sleep_hp_regulator1 + } + #[doc = "0x98 - need_des"] + #[inline(always)] + pub const fn hp_sleep_xtal(&self) -> &HP_SLEEP_XTAL { + &self.hp_sleep_xtal + } + #[doc = "0x9c - need_des"] + #[inline(always)] + pub const fn hp_sleep_lp_regulator0(&self) -> &HP_SLEEP_LP_REGULATOR0 { + &self.hp_sleep_lp_regulator0 + } + #[doc = "0xa0 - need_des"] + #[inline(always)] + pub const fn hp_sleep_lp_regulator1(&self) -> &HP_SLEEP_LP_REGULATOR1 { + &self.hp_sleep_lp_regulator1 + } + #[doc = "0xa4 - need_des"] + #[inline(always)] + pub const fn hp_sleep_lp_dcdc_reserve(&self) -> &HP_SLEEP_LP_DCDC_RESERVE { + &self.hp_sleep_lp_dcdc_reserve + } + #[doc = "0xa8 - need_des"] + #[inline(always)] + pub const fn hp_sleep_lp_dig_power(&self) -> &HP_SLEEP_LP_DIG_POWER { + &self.hp_sleep_lp_dig_power + } + #[doc = "0xac - need_des"] + #[inline(always)] + pub const fn hp_sleep_lp_ck_power(&self) -> &HP_SLEEP_LP_CK_POWER { + &self.hp_sleep_lp_ck_power + } + #[doc = "0xb0 - need_des"] + #[inline(always)] + pub const fn lp_sleep_lp_bias_reserve(&self) -> &LP_SLEEP_LP_BIAS_RESERVE { + &self.lp_sleep_lp_bias_reserve + } + #[doc = "0xb4 - need_des"] + #[inline(always)] + pub const fn lp_sleep_lp_regulator0(&self) -> &LP_SLEEP_LP_REGULATOR0 { + &self.lp_sleep_lp_regulator0 + } + #[doc = "0xb8 - need_des"] + #[inline(always)] + pub const fn lp_sleep_lp_regulator1(&self) -> &LP_SLEEP_LP_REGULATOR1 { + &self.lp_sleep_lp_regulator1 + } + #[doc = "0xbc - need_des"] + #[inline(always)] + pub const fn lp_sleep_xtal(&self) -> &LP_SLEEP_XTAL { + &self.lp_sleep_xtal + } + #[doc = "0xc0 - need_des"] + #[inline(always)] + pub const fn lp_sleep_lp_dig_power(&self) -> &LP_SLEEP_LP_DIG_POWER { + &self.lp_sleep_lp_dig_power + } + #[doc = "0xc4 - need_des"] + #[inline(always)] + pub const fn lp_sleep_lp_ck_power(&self) -> &LP_SLEEP_LP_CK_POWER { + &self.lp_sleep_lp_ck_power + } + #[doc = "0xc8 - need_des"] + #[inline(always)] + pub const fn lp_sleep_bias(&self) -> &LP_SLEEP_BIAS { + &self.lp_sleep_bias + } + #[doc = "0xcc - need_des"] + #[inline(always)] + pub const fn imm_hp_ck_power(&self) -> &IMM_HP_CK_POWER { + &self.imm_hp_ck_power + } + #[doc = "0xd0 - need_des"] + #[inline(always)] + pub const fn imm_sleep_sysclk(&self) -> &IMM_SLEEP_SYSCLK { + &self.imm_sleep_sysclk + } + #[doc = "0xd4 - need_des"] + #[inline(always)] + pub const fn imm_hp_func_icg(&self) -> &IMM_HP_FUNC_ICG { + &self.imm_hp_func_icg + } + #[doc = "0xd8 - need_des"] + #[inline(always)] + pub const fn imm_hp_apb_icg(&self) -> &IMM_HP_APB_ICG { + &self.imm_hp_apb_icg + } + #[doc = "0xdc - need_des"] + #[inline(always)] + pub const fn imm_modem_icg(&self) -> &IMM_MODEM_ICG { + &self.imm_modem_icg + } + #[doc = "0xe0 - need_des"] + #[inline(always)] + pub const fn imm_lp_icg(&self) -> &IMM_LP_ICG { + &self.imm_lp_icg + } + #[doc = "0xe4 - need_des"] + #[inline(always)] + pub const fn imm_pad_hold_all(&self) -> &IMM_PAD_HOLD_ALL { + &self.imm_pad_hold_all + } + #[doc = "0xe8 - need_des"] + #[inline(always)] + pub const fn imm_i2c_iso(&self) -> &IMM_I2C_ISO { + &self.imm_i2c_iso + } + #[doc = "0xec - need_des"] + #[inline(always)] + pub const fn power_wait_timer0(&self) -> &POWER_WAIT_TIMER0 { + &self.power_wait_timer0 + } + #[doc = "0xf0 - need_des"] + #[inline(always)] + pub const fn power_wait_timer1(&self) -> &POWER_WAIT_TIMER1 { + &self.power_wait_timer1 + } + #[doc = "0xf4 - need_des"] + #[inline(always)] + pub const fn power_pd_top_cntl(&self) -> &POWER_PD_TOP_CNTL { + &self.power_pd_top_cntl + } + #[doc = "0xf8 - need_des"] + #[inline(always)] + pub const fn power_pd_cnnt_cntl(&self) -> &POWER_PD_CNNT_CNTL { + &self.power_pd_cnnt_cntl + } + #[doc = "0xfc - need_des"] + #[inline(always)] + pub const fn power_pd_hpmem_cntl(&self) -> &POWER_PD_HPMEM_CNTL { + &self.power_pd_hpmem_cntl + } + #[doc = "0x100 - need_des"] + #[inline(always)] + pub const fn power_pd_top_mask(&self) -> &POWER_PD_TOP_MASK { + &self.power_pd_top_mask + } + #[doc = "0x104 - need_des"] + #[inline(always)] + pub const fn power_pd_cnnt_mask(&self) -> &POWER_PD_CNNT_MASK { + &self.power_pd_cnnt_mask + } + #[doc = "0x108 - need_des"] + #[inline(always)] + pub const fn power_pd_hpmem_mask(&self) -> &POWER_PD_HPMEM_MASK { + &self.power_pd_hpmem_mask + } + #[doc = "0x10c - need_des"] + #[inline(always)] + pub const fn power_dcdc_switch(&self) -> &POWER_DCDC_SWITCH { + &self.power_dcdc_switch + } + #[doc = "0x110 - need_des"] + #[inline(always)] + pub const fn power_pd_lpperi_cntl(&self) -> &POWER_PD_LPPERI_CNTL { + &self.power_pd_lpperi_cntl + } + #[doc = "0x114 - need_des"] + #[inline(always)] + pub const fn power_pd_lpperi_mask(&self) -> &POWER_PD_LPPERI_MASK { + &self.power_pd_lpperi_mask + } + #[doc = "0x118 - need_des"] + #[inline(always)] + pub const fn power_hp_pad(&self) -> &POWER_HP_PAD { + &self.power_hp_pad + } + #[doc = "0x11c - need_des"] + #[inline(always)] + pub const fn power_ck_wait_cntl(&self) -> &POWER_CK_WAIT_CNTL { + &self.power_ck_wait_cntl + } + #[doc = "0x120 - need_des"] + #[inline(always)] + pub const fn slp_wakeup_cntl0(&self) -> &SLP_WAKEUP_CNTL0 { + &self.slp_wakeup_cntl0 + } + #[doc = "0x124 - need_des"] + #[inline(always)] + pub const fn slp_wakeup_cntl1(&self) -> &SLP_WAKEUP_CNTL1 { + &self.slp_wakeup_cntl1 + } + #[doc = "0x128 - need_des"] + #[inline(always)] + pub const fn slp_wakeup_cntl2(&self) -> &SLP_WAKEUP_CNTL2 { + &self.slp_wakeup_cntl2 + } + #[doc = "0x12c - need_des"] + #[inline(always)] + pub const fn slp_wakeup_cntl3(&self) -> &SLP_WAKEUP_CNTL3 { + &self.slp_wakeup_cntl3 + } + #[doc = "0x130 - need_des"] + #[inline(always)] + pub const fn slp_wakeup_cntl4(&self) -> &SLP_WAKEUP_CNTL4 { + &self.slp_wakeup_cntl4 + } + #[doc = "0x134 - need_des"] + #[inline(always)] + pub const fn slp_wakeup_cntl5(&self) -> &SLP_WAKEUP_CNTL5 { + &self.slp_wakeup_cntl5 + } + #[doc = "0x138 - need_des"] + #[inline(always)] + pub const fn slp_wakeup_cntl6(&self) -> &SLP_WAKEUP_CNTL6 { + &self.slp_wakeup_cntl6 + } + #[doc = "0x13c - need_des"] + #[inline(always)] + pub const fn slp_wakeup_cntl7(&self) -> &SLP_WAKEUP_CNTL7 { + &self.slp_wakeup_cntl7 + } + #[doc = "0x140 - need_des"] + #[inline(always)] + pub const fn slp_wakeup_cntl8(&self) -> &SLP_WAKEUP_CNTL8 { + &self.slp_wakeup_cntl8 + } + #[doc = "0x144 - need_des"] + #[inline(always)] + pub const fn slp_wakeup_status0(&self) -> &SLP_WAKEUP_STATUS0 { + &self.slp_wakeup_status0 + } + #[doc = "0x148 - need_des"] + #[inline(always)] + pub const fn slp_wakeup_status1(&self) -> &SLP_WAKEUP_STATUS1 { + &self.slp_wakeup_status1 + } + #[doc = "0x14c - need_des"] + #[inline(always)] + pub const fn slp_wakeup_status2(&self) -> &SLP_WAKEUP_STATUS2 { + &self.slp_wakeup_status2 + } + #[doc = "0x150 - need_des"] + #[inline(always)] + pub const fn hp_ck_poweron(&self) -> &HP_CK_POWERON { + &self.hp_ck_poweron + } + #[doc = "0x154 - need_des"] + #[inline(always)] + pub const fn hp_ck_cntl(&self) -> &HP_CK_CNTL { + &self.hp_ck_cntl + } + #[doc = "0x158 - need_des"] + #[inline(always)] + pub const fn por_status(&self) -> &POR_STATUS { + &self.por_status + } + #[doc = "0x15c - need_des"] + #[inline(always)] + pub const fn rf_pwc(&self) -> &RF_PWC { + &self.rf_pwc + } + #[doc = "0x160 - need_des"] + #[inline(always)] + pub const fn backup_cfg(&self) -> &BACKUP_CFG { + &self.backup_cfg + } + #[doc = "0x164 - need_des"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x168 - need_des"] + #[inline(always)] + pub const fn hp_int_st(&self) -> &HP_INT_ST { + &self.hp_int_st + } + #[doc = "0x16c - need_des"] + #[inline(always)] + pub const fn hp_int_ena(&self) -> &HP_INT_ENA { + &self.hp_int_ena + } + #[doc = "0x170 - need_des"] + #[inline(always)] + pub const fn hp_int_clr(&self) -> &HP_INT_CLR { + &self.hp_int_clr + } + #[doc = "0x174 - need_des"] + #[inline(always)] + pub const fn lp_int_raw(&self) -> &LP_INT_RAW { + &self.lp_int_raw + } + #[doc = "0x178 - need_des"] + #[inline(always)] + pub const fn lp_int_st(&self) -> &LP_INT_ST { + &self.lp_int_st + } + #[doc = "0x17c - need_des"] + #[inline(always)] + pub const fn lp_int_ena(&self) -> &LP_INT_ENA { + &self.lp_int_ena + } + #[doc = "0x180 - need_des"] + #[inline(always)] + pub const fn lp_int_clr(&self) -> &LP_INT_CLR { + &self.lp_int_clr + } + #[doc = "0x184 - need_des"] + #[inline(always)] + pub const fn lp_cpu_pwr0(&self) -> &LP_CPU_PWR0 { + &self.lp_cpu_pwr0 + } + #[doc = "0x188 - need_des"] + #[inline(always)] + pub const fn lp_cpu_pwr1(&self) -> &LP_CPU_PWR1 { + &self.lp_cpu_pwr1 + } + #[doc = "0x18c - need_des"] + #[inline(always)] + pub const fn lp_cpu_pwr2(&self) -> &LP_CPU_PWR2 { + &self.lp_cpu_pwr2 + } + #[doc = "0x190 - need_des"] + #[inline(always)] + pub const fn lp_cpu_pwr3(&self) -> &LP_CPU_PWR3 { + &self.lp_cpu_pwr3 + } + #[doc = "0x194 - need_des"] + #[inline(always)] + pub const fn lp_cpu_pwr4(&self) -> &LP_CPU_PWR4 { + &self.lp_cpu_pwr4 + } + #[doc = "0x198 - need_des"] + #[inline(always)] + pub const fn lp_cpu_pwr5(&self) -> &LP_CPU_PWR5 { + &self.lp_cpu_pwr5 + } + #[doc = "0x19c - need_des"] + #[inline(always)] + pub const fn hp_lp_cpu_comm(&self) -> &HP_LP_CPU_COMM { + &self.hp_lp_cpu_comm + } + #[doc = "0x1a0 - need_des"] + #[inline(always)] + pub const fn hp_regulator_cfg(&self) -> &HP_REGULATOR_CFG { + &self.hp_regulator_cfg + } + #[doc = "0x1a4 - need_des"] + #[inline(always)] + pub const fn main_state(&self) -> &MAIN_STATE { + &self.main_state + } + #[doc = "0x1a8 - need_des"] + #[inline(always)] + pub const fn pwr_state(&self) -> &PWR_STATE { + &self.pwr_state + } + #[doc = "0x1ac - need_des"] + #[inline(always)] + pub const fn clk_state0(&self) -> &CLK_STATE0 { + &self.clk_state0 + } + #[doc = "0x1b0 - need_des"] + #[inline(always)] + pub const fn clk_state1(&self) -> &CLK_STATE1 { + &self.clk_state1 + } + #[doc = "0x1b4 - need_des"] + #[inline(always)] + pub const fn clk_state2(&self) -> &CLK_STATE2 { + &self.clk_state2 + } + #[doc = "0x1b8 - need_des"] + #[inline(always)] + pub const fn ext_ldo_p0_0p1a(&self) -> &EXT_LDO_P0_0P1A { + &self.ext_ldo_p0_0p1a + } + #[doc = "0x1bc - need_des"] + #[inline(always)] + pub const fn ext_ldo_p0_0p1a_ana(&self) -> &EXT_LDO_P0_0P1A_ANA { + &self.ext_ldo_p0_0p1a_ana + } + #[doc = "0x1c0 - need_des"] + #[inline(always)] + pub const fn ext_ldo_p0_0p2a(&self) -> &EXT_LDO_P0_0P2A { + &self.ext_ldo_p0_0p2a + } + #[doc = "0x1c4 - need_des"] + #[inline(always)] + pub const fn ext_ldo_p0_0p2a_ana(&self) -> &EXT_LDO_P0_0P2A_ANA { + &self.ext_ldo_p0_0p2a_ana + } + #[doc = "0x1c8 - need_des"] + #[inline(always)] + pub const fn ext_ldo_p0_0p3a(&self) -> &EXT_LDO_P0_0P3A { + &self.ext_ldo_p0_0p3a + } + #[doc = "0x1cc - need_des"] + #[inline(always)] + pub const fn ext_ldo_p0_0p3a_ana(&self) -> &EXT_LDO_P0_0P3A_ANA { + &self.ext_ldo_p0_0p3a_ana + } + #[doc = "0x1d0 - need_des"] + #[inline(always)] + pub const fn ext_ldo_p1_0p1a(&self) -> &EXT_LDO_P1_0P1A { + &self.ext_ldo_p1_0p1a + } + #[doc = "0x1d4 - need_des"] + #[inline(always)] + pub const fn ext_ldo_p1_0p1a_ana(&self) -> &EXT_LDO_P1_0P1A_ANA { + &self.ext_ldo_p1_0p1a_ana + } + #[doc = "0x1d8 - need_des"] + #[inline(always)] + pub const fn ext_ldo_p1_0p2a(&self) -> &EXT_LDO_P1_0P2A { + &self.ext_ldo_p1_0p2a + } + #[doc = "0x1dc - need_des"] + #[inline(always)] + pub const fn ext_ldo_p1_0p2a_ana(&self) -> &EXT_LDO_P1_0P2A_ANA { + &self.ext_ldo_p1_0p2a_ana + } + #[doc = "0x1e0 - need_des"] + #[inline(always)] + pub const fn ext_ldo_p1_0p3a(&self) -> &EXT_LDO_P1_0P3A { + &self.ext_ldo_p1_0p3a + } + #[doc = "0x1e4 - need_des"] + #[inline(always)] + pub const fn ext_ldo_p1_0p3a_ana(&self) -> &EXT_LDO_P1_0P3A_ANA { + &self.ext_ldo_p1_0p3a_ana + } + #[doc = "0x1e8 - need_des"] + #[inline(always)] + pub const fn ext_wakeup_lv(&self) -> &EXT_WAKEUP_LV { + &self.ext_wakeup_lv + } + #[doc = "0x1ec - need_des"] + #[inline(always)] + pub const fn ext_wakeup_sel(&self) -> &EXT_WAKEUP_SEL { + &self.ext_wakeup_sel + } + #[doc = "0x1f0 - need_des"] + #[inline(always)] + pub const fn ext_wakeup_st(&self) -> &EXT_WAKEUP_ST { + &self.ext_wakeup_st + } + #[doc = "0x1f4 - need_des"] + #[inline(always)] + pub const fn ext_wakeup_cntl(&self) -> &EXT_WAKEUP_CNTL { + &self.ext_wakeup_cntl + } + #[doc = "0x1f8 - need_des"] + #[inline(always)] + pub const fn sdio_wakeup_cntl(&self) -> &SDIO_WAKEUP_CNTL { + &self.sdio_wakeup_cntl + } + #[doc = "0x1fc - need_des"] + #[inline(always)] + pub const fn xtal_slp(&self) -> &XTAL_SLP { + &self.xtal_slp + } + #[doc = "0x200 - need_des"] + #[inline(always)] + pub const fn cpu_sw_stall(&self) -> &CPU_SW_STALL { + &self.cpu_sw_stall + } + #[doc = "0x204 - need_des"] + #[inline(always)] + pub const fn dcm_ctrl(&self) -> &DCM_CTRL { + &self.dcm_ctrl + } + #[doc = "0x208 - need_des"] + #[inline(always)] + pub const fn dcm_wait_delay(&self) -> &DCM_WAIT_DELAY { + &self.dcm_wait_delay + } + #[doc = "0x20c - need_des"] + #[inline(always)] + pub const fn vddbat_cfg(&self) -> &VDDBAT_CFG { + &self.vddbat_cfg + } + #[doc = "0x210 - need_des"] + #[inline(always)] + pub const fn touch_pwr_cntl(&self) -> &TOUCH_PWR_CNTL { + &self.touch_pwr_cntl + } + #[doc = "0x214 - need_des"] + #[inline(always)] + pub const fn rdn_eco(&self) -> &RDN_ECO { + &self.rdn_eco + } + #[doc = "0x3fc - need_des"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "HP_ACTIVE_DIG_POWER (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_dig_power::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_dig_power::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_dig_power`] module"] +pub type HP_ACTIVE_DIG_POWER = crate::Reg; +#[doc = "need_des"] +pub mod hp_active_dig_power; +#[doc = "HP_ACTIVE_ICG_HP_FUNC (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_icg_hp_func::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_icg_hp_func::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_icg_hp_func`] module"] +pub type HP_ACTIVE_ICG_HP_FUNC = crate::Reg; +#[doc = "need_des"] +pub mod hp_active_icg_hp_func; +#[doc = "HP_ACTIVE_ICG_HP_APB (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_icg_hp_apb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_icg_hp_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_icg_hp_apb`] module"] +pub type HP_ACTIVE_ICG_HP_APB = crate::Reg; +#[doc = "need_des"] +pub mod hp_active_icg_hp_apb; +#[doc = "HP_ACTIVE_ICG_MODEM (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_icg_modem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_icg_modem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_icg_modem`] module"] +pub type HP_ACTIVE_ICG_MODEM = crate::Reg; +#[doc = "need_des"] +pub mod hp_active_icg_modem; +#[doc = "HP_ACTIVE_HP_SYS_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_hp_sys_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_hp_sys_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_hp_sys_cntl`] module"] +pub type HP_ACTIVE_HP_SYS_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod hp_active_hp_sys_cntl; +#[doc = "HP_ACTIVE_HP_CK_POWER (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_hp_ck_power::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_hp_ck_power::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_hp_ck_power`] module"] +pub type HP_ACTIVE_HP_CK_POWER = crate::Reg; +#[doc = "need_des"] +pub mod hp_active_hp_ck_power; +#[doc = "HP_ACTIVE_BIAS (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_bias::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_bias::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_bias`] module"] +pub type HP_ACTIVE_BIAS = crate::Reg; +#[doc = "need_des"] +pub mod hp_active_bias; +#[doc = "HP_ACTIVE_BACKUP (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_backup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_backup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_backup`] module"] +pub type HP_ACTIVE_BACKUP = crate::Reg; +#[doc = "need_des"] +pub mod hp_active_backup; +#[doc = "HP_ACTIVE_BACKUP_CLK (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_backup_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_backup_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_backup_clk`] module"] +pub type HP_ACTIVE_BACKUP_CLK = crate::Reg; +#[doc = "need_des"] +pub mod hp_active_backup_clk; +#[doc = "HP_ACTIVE_SYSCLK (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_sysclk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_sysclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_sysclk`] module"] +pub type HP_ACTIVE_SYSCLK = crate::Reg; +#[doc = "need_des"] +pub mod hp_active_sysclk; +#[doc = "HP_ACTIVE_HP_REGULATOR0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_hp_regulator0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_hp_regulator0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_hp_regulator0`] module"] +pub type HP_ACTIVE_HP_REGULATOR0 = + crate::Reg; +#[doc = "need_des"] +pub mod hp_active_hp_regulator0; +#[doc = "HP_ACTIVE_HP_REGULATOR1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_hp_regulator1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_hp_regulator1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_hp_regulator1`] module"] +pub type HP_ACTIVE_HP_REGULATOR1 = + crate::Reg; +#[doc = "need_des"] +pub mod hp_active_hp_regulator1; +#[doc = "HP_ACTIVE_XTAL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_xtal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_xtal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_active_xtal`] module"] +pub type HP_ACTIVE_XTAL = crate::Reg; +#[doc = "need_des"] +pub mod hp_active_xtal; +#[doc = "HP_MODEM_DIG_POWER (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_modem_dig_power::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_dig_power::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_dig_power`] module"] +pub type HP_MODEM_DIG_POWER = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_dig_power; +#[doc = "HP_MODEM_ICG_HP_FUNC (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_icg_hp_func::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_icg_hp_func`] module"] +pub type HP_MODEM_ICG_HP_FUNC = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_icg_hp_func; +#[doc = "HP_MODEM_ICG_HP_APB (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_icg_hp_apb::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_icg_hp_apb`] module"] +pub type HP_MODEM_ICG_HP_APB = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_icg_hp_apb; +#[doc = "HP_MODEM_ICG_MODEM (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_icg_modem::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_icg_modem`] module"] +pub type HP_MODEM_ICG_MODEM = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_icg_modem; +#[doc = "HP_MODEM_HP_SYS_CNTL (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_hp_sys_cntl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_hp_sys_cntl`] module"] +pub type HP_MODEM_HP_SYS_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_hp_sys_cntl; +#[doc = "HP_MODEM_HP_CK_POWER (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_hp_ck_power::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_hp_ck_power`] module"] +pub type HP_MODEM_HP_CK_POWER = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_hp_ck_power; +#[doc = "HP_MODEM_BIAS (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_bias::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_bias`] module"] +pub type HP_MODEM_BIAS = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_bias; +#[doc = "HP_MODEM_BACKUP (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_backup::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_backup`] module"] +pub type HP_MODEM_BACKUP = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_backup; +#[doc = "HP_MODEM_BACKUP_CLK (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_backup_clk::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_backup_clk`] module"] +pub type HP_MODEM_BACKUP_CLK = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_backup_clk; +#[doc = "HP_MODEM_SYSCLK (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_sysclk::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_sysclk`] module"] +pub type HP_MODEM_SYSCLK = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_sysclk; +#[doc = "HP_MODEM_HP_REGULATOR0 (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_hp_regulator0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_hp_regulator0`] module"] +pub type HP_MODEM_HP_REGULATOR0 = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_hp_regulator0; +#[doc = "HP_MODEM_HP_REGULATOR1 (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_hp_regulator1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_hp_regulator1`] module"] +pub type HP_MODEM_HP_REGULATOR1 = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_hp_regulator1; +#[doc = "HP_MODEM_XTAL (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_xtal::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_modem_xtal`] module"] +pub type HP_MODEM_XTAL = crate::Reg; +#[doc = "need_des"] +pub mod hp_modem_xtal; +#[doc = "HP_SLEEP_DIG_POWER (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_dig_power::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_dig_power::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_dig_power`] module"] +pub type HP_SLEEP_DIG_POWER = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_dig_power; +#[doc = "HP_SLEEP_ICG_HP_FUNC (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_icg_hp_func::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_icg_hp_func::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_icg_hp_func`] module"] +pub type HP_SLEEP_ICG_HP_FUNC = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_icg_hp_func; +#[doc = "HP_SLEEP_ICG_HP_APB (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_icg_hp_apb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_icg_hp_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_icg_hp_apb`] module"] +pub type HP_SLEEP_ICG_HP_APB = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_icg_hp_apb; +#[doc = "HP_SLEEP_ICG_MODEM (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_icg_modem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_icg_modem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_icg_modem`] module"] +pub type HP_SLEEP_ICG_MODEM = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_icg_modem; +#[doc = "HP_SLEEP_HP_SYS_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_hp_sys_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_hp_sys_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_hp_sys_cntl`] module"] +pub type HP_SLEEP_HP_SYS_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_hp_sys_cntl; +#[doc = "HP_SLEEP_HP_CK_POWER (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_hp_ck_power::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_hp_ck_power::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_hp_ck_power`] module"] +pub type HP_SLEEP_HP_CK_POWER = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_hp_ck_power; +#[doc = "HP_SLEEP_BIAS (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_bias::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_bias::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_bias`] module"] +pub type HP_SLEEP_BIAS = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_bias; +#[doc = "HP_SLEEP_BACKUP (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_backup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_backup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_backup`] module"] +pub type HP_SLEEP_BACKUP = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_backup; +#[doc = "HP_SLEEP_BACKUP_CLK (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_backup_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_backup_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_backup_clk`] module"] +pub type HP_SLEEP_BACKUP_CLK = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_backup_clk; +#[doc = "HP_SLEEP_SYSCLK (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_sysclk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_sysclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_sysclk`] module"] +pub type HP_SLEEP_SYSCLK = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_sysclk; +#[doc = "HP_SLEEP_HP_REGULATOR0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_hp_regulator0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_hp_regulator0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_hp_regulator0`] module"] +pub type HP_SLEEP_HP_REGULATOR0 = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_hp_regulator0; +#[doc = "HP_SLEEP_HP_REGULATOR1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_hp_regulator1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_hp_regulator1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_hp_regulator1`] module"] +pub type HP_SLEEP_HP_REGULATOR1 = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_hp_regulator1; +#[doc = "HP_SLEEP_XTAL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_xtal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_xtal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_xtal`] module"] +pub type HP_SLEEP_XTAL = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_xtal; +#[doc = "HP_SLEEP_LP_REGULATOR0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_lp_regulator0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_lp_regulator0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_lp_regulator0`] module"] +pub type HP_SLEEP_LP_REGULATOR0 = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_lp_regulator0; +#[doc = "HP_SLEEP_LP_REGULATOR1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_lp_regulator1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_lp_regulator1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_lp_regulator1`] module"] +pub type HP_SLEEP_LP_REGULATOR1 = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_lp_regulator1; +#[doc = "HP_SLEEP_LP_DCDC_RESERVE (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_lp_dcdc_reserve::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_lp_dcdc_reserve`] module"] +pub type HP_SLEEP_LP_DCDC_RESERVE = + crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_lp_dcdc_reserve; +#[doc = "HP_SLEEP_LP_DIG_POWER (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_lp_dig_power::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_lp_dig_power::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_lp_dig_power`] module"] +pub type HP_SLEEP_LP_DIG_POWER = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_lp_dig_power; +#[doc = "HP_SLEEP_LP_CK_POWER (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_lp_ck_power::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_lp_ck_power::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_sleep_lp_ck_power`] module"] +pub type HP_SLEEP_LP_CK_POWER = crate::Reg; +#[doc = "need_des"] +pub mod hp_sleep_lp_ck_power; +#[doc = "LP_SLEEP_LP_BIAS_RESERVE (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_lp_bias_reserve::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sleep_lp_bias_reserve`] module"] +pub type LP_SLEEP_LP_BIAS_RESERVE = + crate::Reg; +#[doc = "need_des"] +pub mod lp_sleep_lp_bias_reserve; +#[doc = "LP_SLEEP_LP_REGULATOR0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_lp_regulator0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_lp_regulator0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sleep_lp_regulator0`] module"] +pub type LP_SLEEP_LP_REGULATOR0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_sleep_lp_regulator0; +#[doc = "LP_SLEEP_LP_REGULATOR1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_lp_regulator1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_lp_regulator1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sleep_lp_regulator1`] module"] +pub type LP_SLEEP_LP_REGULATOR1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_sleep_lp_regulator1; +#[doc = "LP_SLEEP_XTAL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_xtal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_xtal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sleep_xtal`] module"] +pub type LP_SLEEP_XTAL = crate::Reg; +#[doc = "need_des"] +pub mod lp_sleep_xtal; +#[doc = "LP_SLEEP_LP_DIG_POWER (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_lp_dig_power::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_lp_dig_power::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sleep_lp_dig_power`] module"] +pub type LP_SLEEP_LP_DIG_POWER = crate::Reg; +#[doc = "need_des"] +pub mod lp_sleep_lp_dig_power; +#[doc = "LP_SLEEP_LP_CK_POWER (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_lp_ck_power::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_lp_ck_power::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sleep_lp_ck_power`] module"] +pub type LP_SLEEP_LP_CK_POWER = crate::Reg; +#[doc = "need_des"] +pub mod lp_sleep_lp_ck_power; +#[doc = "LP_SLEEP_BIAS (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_bias::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_bias::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_sleep_bias`] module"] +pub type LP_SLEEP_BIAS = crate::Reg; +#[doc = "need_des"] +pub mod lp_sleep_bias; +#[doc = "IMM_HP_CK_POWER (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imm_hp_ck_power::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_hp_ck_power::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imm_hp_ck_power`] module"] +pub type IMM_HP_CK_POWER = crate::Reg; +#[doc = "need_des"] +pub mod imm_hp_ck_power; +#[doc = "IMM_SLEEP_SYSCLK (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_sleep_sysclk::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imm_sleep_sysclk`] module"] +pub type IMM_SLEEP_SYSCLK = crate::Reg; +#[doc = "need_des"] +pub mod imm_sleep_sysclk; +#[doc = "IMM_HP_FUNC_ICG (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_hp_func_icg::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imm_hp_func_icg`] module"] +pub type IMM_HP_FUNC_ICG = crate::Reg; +#[doc = "need_des"] +pub mod imm_hp_func_icg; +#[doc = "IMM_HP_APB_ICG (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_hp_apb_icg::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imm_hp_apb_icg`] module"] +pub type IMM_HP_APB_ICG = crate::Reg; +#[doc = "need_des"] +pub mod imm_hp_apb_icg; +#[doc = "IMM_MODEM_ICG (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_modem_icg::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imm_modem_icg`] module"] +pub type IMM_MODEM_ICG = crate::Reg; +#[doc = "need_des"] +pub mod imm_modem_icg; +#[doc = "IMM_LP_ICG (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_lp_icg::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imm_lp_icg`] module"] +pub type IMM_LP_ICG = crate::Reg; +#[doc = "need_des"] +pub mod imm_lp_icg; +#[doc = "IMM_PAD_HOLD_ALL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imm_pad_hold_all::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_pad_hold_all::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imm_pad_hold_all`] module"] +pub type IMM_PAD_HOLD_ALL = crate::Reg; +#[doc = "need_des"] +pub mod imm_pad_hold_all; +#[doc = "IMM_I2C_ISO (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_i2c_iso::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imm_i2c_iso`] module"] +pub type IMM_I2C_ISO = crate::Reg; +#[doc = "need_des"] +pub mod imm_i2c_iso; +#[doc = "POWER_WAIT_TIMER0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_wait_timer0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_wait_timer0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_wait_timer0`] module"] +pub type POWER_WAIT_TIMER0 = crate::Reg; +#[doc = "need_des"] +pub mod power_wait_timer0; +#[doc = "POWER_WAIT_TIMER1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_wait_timer1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_wait_timer1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_wait_timer1`] module"] +pub type POWER_WAIT_TIMER1 = crate::Reg; +#[doc = "need_des"] +pub mod power_wait_timer1; +#[doc = "POWER_PD_TOP_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_top_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_top_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_pd_top_cntl`] module"] +pub type POWER_PD_TOP_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod power_pd_top_cntl; +#[doc = "POWER_PD_CNNT_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_cnnt_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_cnnt_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_pd_cnnt_cntl`] module"] +pub type POWER_PD_CNNT_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod power_pd_cnnt_cntl; +#[doc = "POWER_PD_HPMEM_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_hpmem_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_hpmem_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_pd_hpmem_cntl`] module"] +pub type POWER_PD_HPMEM_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod power_pd_hpmem_cntl; +#[doc = "POWER_PD_TOP_MASK (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_top_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_top_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_pd_top_mask`] module"] +pub type POWER_PD_TOP_MASK = crate::Reg; +#[doc = "need_des"] +pub mod power_pd_top_mask; +#[doc = "POWER_PD_CNNT_MASK (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_cnnt_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_cnnt_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_pd_cnnt_mask`] module"] +pub type POWER_PD_CNNT_MASK = crate::Reg; +#[doc = "need_des"] +pub mod power_pd_cnnt_mask; +#[doc = "POWER_PD_HPMEM_MASK (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_hpmem_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_hpmem_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_pd_hpmem_mask`] module"] +pub type POWER_PD_HPMEM_MASK = crate::Reg; +#[doc = "need_des"] +pub mod power_pd_hpmem_mask; +#[doc = "POWER_DCDC_SWITCH (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_dcdc_switch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_dcdc_switch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_dcdc_switch`] module"] +pub type POWER_DCDC_SWITCH = crate::Reg; +#[doc = "need_des"] +pub mod power_dcdc_switch; +#[doc = "POWER_PD_LPPERI_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_lpperi_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_lpperi_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_pd_lpperi_cntl`] module"] +pub type POWER_PD_LPPERI_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod power_pd_lpperi_cntl; +#[doc = "POWER_PD_LPPERI_MASK (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_lpperi_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_lpperi_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_pd_lpperi_mask`] module"] +pub type POWER_PD_LPPERI_MASK = crate::Reg; +#[doc = "need_des"] +pub mod power_pd_lpperi_mask; +#[doc = "POWER_HP_PAD (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_hp_pad::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_hp_pad::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_hp_pad`] module"] +pub type POWER_HP_PAD = crate::Reg; +#[doc = "need_des"] +pub mod power_hp_pad; +#[doc = "POWER_CK_WAIT_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_ck_wait_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_ck_wait_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_ck_wait_cntl`] module"] +pub type POWER_CK_WAIT_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod power_ck_wait_cntl; +#[doc = "SLP_WAKEUP_CNTL0 (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_cntl0`] module"] +pub type SLP_WAKEUP_CNTL0 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_cntl0; +#[doc = "SLP_WAKEUP_CNTL1 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_cntl1`] module"] +pub type SLP_WAKEUP_CNTL1 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_cntl1; +#[doc = "SLP_WAKEUP_CNTL2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_cntl2`] module"] +pub type SLP_WAKEUP_CNTL2 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_cntl2; +#[doc = "SLP_WAKEUP_CNTL3 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_cntl3`] module"] +pub type SLP_WAKEUP_CNTL3 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_cntl3; +#[doc = "SLP_WAKEUP_CNTL4 (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl4::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_cntl4`] module"] +pub type SLP_WAKEUP_CNTL4 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_cntl4; +#[doc = "SLP_WAKEUP_CNTL5 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_cntl5`] module"] +pub type SLP_WAKEUP_CNTL5 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_cntl5; +#[doc = "SLP_WAKEUP_CNTL6 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_cntl6`] module"] +pub type SLP_WAKEUP_CNTL6 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_cntl6; +#[doc = "SLP_WAKEUP_CNTL7 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_cntl7`] module"] +pub type SLP_WAKEUP_CNTL7 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_cntl7; +#[doc = "SLP_WAKEUP_CNTL8 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_cntl8`] module"] +pub type SLP_WAKEUP_CNTL8 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_cntl8; +#[doc = "SLP_WAKEUP_STATUS0 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_status0`] module"] +pub type SLP_WAKEUP_STATUS0 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_status0; +#[doc = "SLP_WAKEUP_STATUS1 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_status1`] module"] +pub type SLP_WAKEUP_STATUS1 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_status1; +#[doc = "SLP_WAKEUP_STATUS2 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slp_wakeup_status2`] module"] +pub type SLP_WAKEUP_STATUS2 = crate::Reg; +#[doc = "need_des"] +pub mod slp_wakeup_status2; +#[doc = "HP_CK_POWERON (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ck_poweron::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ck_poweron::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_ck_poweron`] module"] +pub type HP_CK_POWERON = crate::Reg; +#[doc = "need_des"] +pub mod hp_ck_poweron; +#[doc = "HP_CK_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ck_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ck_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_ck_cntl`] module"] +pub type HP_CK_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod hp_ck_cntl; +#[doc = "POR_STATUS (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`por_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@por_status`] module"] +pub type POR_STATUS = crate::Reg; +#[doc = "need_des"] +pub mod por_status; +#[doc = "RF_PWC (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rf_pwc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rf_pwc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rf_pwc`] module"] +pub type RF_PWC = crate::Reg; +#[doc = "need_des"] +pub mod rf_pwc; +#[doc = "BACKUP_CFG (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`backup_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@backup_cfg`] module"] +pub type BACKUP_CFG = crate::Reg; +#[doc = "need_des"] +pub mod backup_cfg; +#[doc = "INT_RAW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "need_des"] +pub mod int_raw; +#[doc = "HP_INT_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_int_st`] module"] +pub type HP_INT_ST = crate::Reg; +#[doc = "need_des"] +pub mod hp_int_st; +#[doc = "HP_INT_ENA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_int_ena`] module"] +pub type HP_INT_ENA = crate::Reg; +#[doc = "need_des"] +pub mod hp_int_ena; +#[doc = "HP_INT_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_int_clr`] module"] +pub type HP_INT_CLR = crate::Reg; +#[doc = "need_des"] +pub mod hp_int_clr; +#[doc = "LP_INT_RAW (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_raw`] module"] +pub type LP_INT_RAW = crate::Reg; +#[doc = "need_des"] +pub mod lp_int_raw; +#[doc = "LP_INT_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_st`] module"] +pub type LP_INT_ST = crate::Reg; +#[doc = "need_des"] +pub mod lp_int_st; +#[doc = "LP_INT_ENA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_ena`] module"] +pub type LP_INT_ENA = crate::Reg; +#[doc = "need_des"] +pub mod lp_int_ena; +#[doc = "LP_INT_CLR (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_int_clr`] module"] +pub type LP_INT_CLR = crate::Reg; +#[doc = "need_des"] +pub mod lp_int_clr; +#[doc = "LP_CPU_PWR0 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_cpu_pwr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cpu_pwr0`] module"] +pub type LP_CPU_PWR0 = crate::Reg; +#[doc = "need_des"] +pub mod lp_cpu_pwr0; +#[doc = "LP_CPU_PWR1 (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_cpu_pwr1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cpu_pwr1`] module"] +pub type LP_CPU_PWR1 = crate::Reg; +#[doc = "need_des"] +pub mod lp_cpu_pwr1; +#[doc = "LP_CPU_PWR2 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_cpu_pwr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cpu_pwr2`] module"] +pub type LP_CPU_PWR2 = crate::Reg; +#[doc = "need_des"] +pub mod lp_cpu_pwr2; +#[doc = "LP_CPU_PWR3 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cpu_pwr3`] module"] +pub type LP_CPU_PWR3 = crate::Reg; +#[doc = "need_des"] +pub mod lp_cpu_pwr3; +#[doc = "LP_CPU_PWR4 (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_cpu_pwr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cpu_pwr4`] module"] +pub type LP_CPU_PWR4 = crate::Reg; +#[doc = "need_des"] +pub mod lp_cpu_pwr4; +#[doc = "LP_CPU_PWR5 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp_cpu_pwr5`] module"] +pub type LP_CPU_PWR5 = crate::Reg; +#[doc = "need_des"] +pub mod lp_cpu_pwr5; +#[doc = "HP_LP_CPU_COMM (w) register accessor: need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_lp_cpu_comm::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_lp_cpu_comm`] module"] +pub type HP_LP_CPU_COMM = crate::Reg; +#[doc = "need_des"] +pub mod hp_lp_cpu_comm; +#[doc = "HP_REGULATOR_CFG (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_regulator_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_regulator_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hp_regulator_cfg`] module"] +pub type HP_REGULATOR_CFG = crate::Reg; +#[doc = "need_des"] +pub mod hp_regulator_cfg; +#[doc = "MAIN_STATE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_state::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`main_state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@main_state`] module"] +pub type MAIN_STATE = crate::Reg; +#[doc = "need_des"] +pub mod main_state; +#[doc = "PWR_STATE (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwr_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwr_state`] module"] +pub type PWR_STATE = crate::Reg; +#[doc = "need_des"] +pub mod pwr_state; +#[doc = "CLK_STATE0 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_state0`] module"] +pub type CLK_STATE0 = crate::Reg; +#[doc = "need_des"] +pub mod clk_state0; +#[doc = "CLK_STATE1 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_state1`] module"] +pub type CLK_STATE1 = crate::Reg; +#[doc = "need_des"] +pub mod clk_state1; +#[doc = "CLK_STATE2 (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_state2`] module"] +pub type CLK_STATE2 = crate::Reg; +#[doc = "need_des"] +pub mod clk_state2; +#[doc = "EXT_LDO_P0_0P1A (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p1a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p1a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p0_0p1a`] module"] +pub type EXT_LDO_P0_0P1A = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p0_0p1a; +#[doc = "EXT_LDO_P0_0P1A_ANA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p1a_ana::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p1a_ana::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p0_0p1a_ana`] module"] +pub type EXT_LDO_P0_0P1A_ANA = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p0_0p1a_ana; +#[doc = "EXT_LDO_P0_0P2A (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p2a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p2a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p0_0p2a`] module"] +pub type EXT_LDO_P0_0P2A = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p0_0p2a; +#[doc = "EXT_LDO_P0_0P2A_ANA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p2a_ana::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p2a_ana::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p0_0p2a_ana`] module"] +pub type EXT_LDO_P0_0P2A_ANA = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p0_0p2a_ana; +#[doc = "EXT_LDO_P0_0P3A (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p3a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p3a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p0_0p3a`] module"] +pub type EXT_LDO_P0_0P3A = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p0_0p3a; +#[doc = "EXT_LDO_P0_0P3A_ANA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p3a_ana::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p3a_ana::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p0_0p3a_ana`] module"] +pub type EXT_LDO_P0_0P3A_ANA = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p0_0p3a_ana; +#[doc = "EXT_LDO_P1_0P1A (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p1a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p1a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p1_0p1a`] module"] +pub type EXT_LDO_P1_0P1A = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p1_0p1a; +#[doc = "EXT_LDO_P1_0P1A_ANA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p1a_ana::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p1a_ana::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p1_0p1a_ana`] module"] +pub type EXT_LDO_P1_0P1A_ANA = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p1_0p1a_ana; +#[doc = "EXT_LDO_P1_0P2A (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p2a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p2a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p1_0p2a`] module"] +pub type EXT_LDO_P1_0P2A = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p1_0p2a; +#[doc = "EXT_LDO_P1_0P2A_ANA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p2a_ana::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p2a_ana::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p1_0p2a_ana`] module"] +pub type EXT_LDO_P1_0P2A_ANA = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p1_0p2a_ana; +#[doc = "EXT_LDO_P1_0P3A (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p3a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p3a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p1_0p3a`] module"] +pub type EXT_LDO_P1_0P3A = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p1_0p3a; +#[doc = "EXT_LDO_P1_0P3A_ANA (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p3a_ana::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p3a_ana::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_ldo_p1_0p3a_ana`] module"] +pub type EXT_LDO_P1_0P3A_ANA = crate::Reg; +#[doc = "need_des"] +pub mod ext_ldo_p1_0p3a_ana; +#[doc = "EXT_WAKEUP_LV (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup_lv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_wakeup_lv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_wakeup_lv`] module"] +pub type EXT_WAKEUP_LV = crate::Reg; +#[doc = "need_des"] +pub mod ext_wakeup_lv; +#[doc = "EXT_WAKEUP_SEL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_wakeup_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_wakeup_sel`] module"] +pub type EXT_WAKEUP_SEL = crate::Reg; +#[doc = "need_des"] +pub mod ext_wakeup_sel; +#[doc = "EXT_WAKEUP_ST (r) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_wakeup_st`] module"] +pub type EXT_WAKEUP_ST = crate::Reg; +#[doc = "need_des"] +pub mod ext_wakeup_st; +#[doc = "EXT_WAKEUP_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_wakeup_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_wakeup_cntl`] module"] +pub type EXT_WAKEUP_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod ext_wakeup_cntl; +#[doc = "SDIO_WAKEUP_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdio_wakeup_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdio_wakeup_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdio_wakeup_cntl`] module"] +pub type SDIO_WAKEUP_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod sdio_wakeup_cntl; +#[doc = "XTAL_SLP (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xtal_slp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xtal_slp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xtal_slp`] module"] +pub type XTAL_SLP = crate::Reg; +#[doc = "need_des"] +pub mod xtal_slp; +#[doc = "CPU_SW_STALL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_sw_stall::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_sw_stall::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_sw_stall`] module"] +pub type CPU_SW_STALL = crate::Reg; +#[doc = "need_des"] +pub mod cpu_sw_stall; +#[doc = "DCM_CTRL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcm_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcm_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcm_ctrl`] module"] +pub type DCM_CTRL = crate::Reg; +#[doc = "need_des"] +pub mod dcm_ctrl; +#[doc = "DCM_WAIT_DELAY (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcm_wait_delay::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcm_wait_delay::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcm_wait_delay`] module"] +pub type DCM_WAIT_DELAY = crate::Reg; +#[doc = "need_des"] +pub mod dcm_wait_delay; +#[doc = "VDDBAT_CFG (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vddbat_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vddbat_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vddbat_cfg`] module"] +pub type VDDBAT_CFG = crate::Reg; +#[doc = "need_des"] +pub mod vddbat_cfg; +#[doc = "TOUCH_PWR_CNTL (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`touch_pwr_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`touch_pwr_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@touch_pwr_cntl`] module"] +pub type TOUCH_PWR_CNTL = crate::Reg; +#[doc = "need_des"] +pub mod touch_pwr_cntl; +#[doc = "RDN_ECO (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdn_eco`] module"] +pub type RDN_ECO = crate::Reg; +#[doc = "need_des"] +pub mod rdn_eco; +#[doc = "DATE (rw) register accessor: need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "need_des"] +pub mod date; diff --git a/esp32p4/src/pmu/backup_cfg.rs b/esp32p4/src/pmu/backup_cfg.rs new file mode 100644 index 0000000000..824d500d1e --- /dev/null +++ b/esp32p4/src/pmu/backup_cfg.rs @@ -0,0 +1,66 @@ +#[doc = "Register `BACKUP_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `BACKUP_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `BACKUP_SYS_CLK_NO_DIV` reader - need_des"] +pub type BACKUP_SYS_CLK_NO_DIV_R = crate::BitReader; +#[doc = "Field `BACKUP_SYS_CLK_NO_DIV` writer - need_des"] +pub type BACKUP_SYS_CLK_NO_DIV_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn backup_sys_clk_no_div(&self) -> BACKUP_SYS_CLK_NO_DIV_R { + BACKUP_SYS_CLK_NO_DIV_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BACKUP_CFG") + .field( + "backup_sys_clk_no_div", + &format_args!("{}", self.backup_sys_clk_no_div().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn backup_sys_clk_no_div(&mut self) -> BACKUP_SYS_CLK_NO_DIV_W { + BACKUP_SYS_CLK_NO_DIV_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`backup_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BACKUP_CFG_SPEC; +impl crate::RegisterSpec for BACKUP_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`backup_cfg::R`](R) reader structure"] +impl crate::Readable for BACKUP_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`backup_cfg::W`](W) writer structure"] +impl crate::Writable for BACKUP_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BACKUP_CFG to value 0x8000_0000"] +impl crate::Resettable for BACKUP_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_0000; +} diff --git a/esp32p4/src/pmu/clk_state0.rs b/esp32p4/src/pmu/clk_state0.rs new file mode 100644 index 0000000000..82205b16a9 --- /dev/null +++ b/esp32p4/src/pmu/clk_state0.rs @@ -0,0 +1,204 @@ +#[doc = "Register `CLK_STATE0` reader"] +pub type R = crate::R; +#[doc = "Field `STABLE_XPD_PLL_STATE` reader - need_des"] +pub type STABLE_XPD_PLL_STATE_R = crate::FieldReader; +#[doc = "Field `STABLE_XPD_XTAL_STATE` reader - need_des"] +pub type STABLE_XPD_XTAL_STATE_R = crate::BitReader; +#[doc = "Field `PMU_ANA_XPD_PLL_I2C_STATE` reader - need_des"] +pub type PMU_ANA_XPD_PLL_I2C_STATE_R = crate::FieldReader; +#[doc = "Field `PMU_SYS_CLK_SLP_SEL_STATE` reader - need_des"] +pub type PMU_SYS_CLK_SLP_SEL_STATE_R = crate::BitReader; +#[doc = "Field `PMU_SYS_CLK_SEL_STATE` reader - need_des"] +pub type PMU_SYS_CLK_SEL_STATE_R = crate::FieldReader; +#[doc = "Field `PMU_SYS_CLK_NO_DIV_STATE` reader - need_des"] +pub type PMU_SYS_CLK_NO_DIV_STATE_R = crate::BitReader; +#[doc = "Field `PMU_ICG_SYS_CLK_EN_STATE` reader - need_des"] +pub type PMU_ICG_SYS_CLK_EN_STATE_R = crate::BitReader; +#[doc = "Field `PMU_ICG_MODEM_SWITCH_STATE` reader - need_des"] +pub type PMU_ICG_MODEM_SWITCH_STATE_R = crate::BitReader; +#[doc = "Field `PMU_ICG_MODEM_CODE_STATE` reader - need_des"] +pub type PMU_ICG_MODEM_CODE_STATE_R = crate::FieldReader; +#[doc = "Field `PMU_ICG_SLP_SEL_STATE` reader - need_des"] +pub type PMU_ICG_SLP_SEL_STATE_R = crate::BitReader; +#[doc = "Field `PMU_ICG_GLOBAL_XTAL_STATE` reader - need_des"] +pub type PMU_ICG_GLOBAL_XTAL_STATE_R = crate::BitReader; +#[doc = "Field `PMU_ICG_GLOBAL_PLL_STATE` reader - need_des"] +pub type PMU_ICG_GLOBAL_PLL_STATE_R = crate::FieldReader; +#[doc = "Field `PMU_ANA_I2C_ISO_EN_STATE` reader - need_des"] +pub type PMU_ANA_I2C_ISO_EN_STATE_R = crate::BitReader; +#[doc = "Field `PMU_ANA_I2C_RETENTION_STATE` reader - need_des"] +pub type PMU_ANA_I2C_RETENTION_STATE_R = crate::BitReader; +#[doc = "Field `PMU_ANA_XPD_PLL_STATE` reader - need_des"] +pub type PMU_ANA_XPD_PLL_STATE_R = crate::FieldReader; +#[doc = "Field `PMU_ANA_XPD_XTAL_STATE` reader - need_des"] +pub type PMU_ANA_XPD_XTAL_STATE_R = crate::BitReader; +impl R { + #[doc = "Bits 0:2 - need_des"] + #[inline(always)] + pub fn stable_xpd_pll_state(&self) -> STABLE_XPD_PLL_STATE_R { + STABLE_XPD_PLL_STATE_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + pub fn stable_xpd_xtal_state(&self) -> STABLE_XPD_XTAL_STATE_R { + STABLE_XPD_XTAL_STATE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - need_des"] + #[inline(always)] + pub fn pmu_ana_xpd_pll_i2c_state(&self) -> PMU_ANA_XPD_PLL_I2C_STATE_R { + PMU_ANA_XPD_PLL_I2C_STATE_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + pub fn pmu_sys_clk_slp_sel_state(&self) -> PMU_SYS_CLK_SLP_SEL_STATE_R { + PMU_SYS_CLK_SLP_SEL_STATE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 11:12 - need_des"] + #[inline(always)] + pub fn pmu_sys_clk_sel_state(&self) -> PMU_SYS_CLK_SEL_STATE_R { + PMU_SYS_CLK_SEL_STATE_R::new(((self.bits >> 11) & 3) as u8) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn pmu_sys_clk_no_div_state(&self) -> PMU_SYS_CLK_NO_DIV_STATE_R { + PMU_SYS_CLK_NO_DIV_STATE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + pub fn pmu_icg_sys_clk_en_state(&self) -> PMU_ICG_SYS_CLK_EN_STATE_R { + PMU_ICG_SYS_CLK_EN_STATE_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - need_des"] + #[inline(always)] + pub fn pmu_icg_modem_switch_state(&self) -> PMU_ICG_MODEM_SWITCH_STATE_R { + PMU_ICG_MODEM_SWITCH_STATE_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:17 - need_des"] + #[inline(always)] + pub fn pmu_icg_modem_code_state(&self) -> PMU_ICG_MODEM_CODE_STATE_R { + PMU_ICG_MODEM_CODE_STATE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - need_des"] + #[inline(always)] + pub fn pmu_icg_slp_sel_state(&self) -> PMU_ICG_SLP_SEL_STATE_R { + PMU_ICG_SLP_SEL_STATE_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - need_des"] + #[inline(always)] + pub fn pmu_icg_global_xtal_state(&self) -> PMU_ICG_GLOBAL_XTAL_STATE_R { + PMU_ICG_GLOBAL_XTAL_STATE_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:23 - need_des"] + #[inline(always)] + pub fn pmu_icg_global_pll_state(&self) -> PMU_ICG_GLOBAL_PLL_STATE_R { + PMU_ICG_GLOBAL_PLL_STATE_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + pub fn pmu_ana_i2c_iso_en_state(&self) -> PMU_ANA_I2C_ISO_EN_STATE_R { + PMU_ANA_I2C_ISO_EN_STATE_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn pmu_ana_i2c_retention_state(&self) -> PMU_ANA_I2C_RETENTION_STATE_R { + PMU_ANA_I2C_RETENTION_STATE_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 27:30 - need_des"] + #[inline(always)] + pub fn pmu_ana_xpd_pll_state(&self) -> PMU_ANA_XPD_PLL_STATE_R { + PMU_ANA_XPD_PLL_STATE_R::new(((self.bits >> 27) & 0x0f) as u8) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn pmu_ana_xpd_xtal_state(&self) -> PMU_ANA_XPD_XTAL_STATE_R { + PMU_ANA_XPD_XTAL_STATE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_STATE0") + .field( + "stable_xpd_pll_state", + &format_args!("{}", self.stable_xpd_pll_state().bits()), + ) + .field( + "stable_xpd_xtal_state", + &format_args!("{}", self.stable_xpd_xtal_state().bit()), + ) + .field( + "pmu_ana_xpd_pll_i2c_state", + &format_args!("{}", self.pmu_ana_xpd_pll_i2c_state().bits()), + ) + .field( + "pmu_sys_clk_slp_sel_state", + &format_args!("{}", self.pmu_sys_clk_slp_sel_state().bit()), + ) + .field( + "pmu_sys_clk_sel_state", + &format_args!("{}", self.pmu_sys_clk_sel_state().bits()), + ) + .field( + "pmu_sys_clk_no_div_state", + &format_args!("{}", self.pmu_sys_clk_no_div_state().bit()), + ) + .field( + "pmu_icg_sys_clk_en_state", + &format_args!("{}", self.pmu_icg_sys_clk_en_state().bit()), + ) + .field( + "pmu_icg_modem_switch_state", + &format_args!("{}", self.pmu_icg_modem_switch_state().bit()), + ) + .field( + "pmu_icg_modem_code_state", + &format_args!("{}", self.pmu_icg_modem_code_state().bits()), + ) + .field( + "pmu_icg_slp_sel_state", + &format_args!("{}", self.pmu_icg_slp_sel_state().bit()), + ) + .field( + "pmu_icg_global_xtal_state", + &format_args!("{}", self.pmu_icg_global_xtal_state().bit()), + ) + .field( + "pmu_icg_global_pll_state", + &format_args!("{}", self.pmu_icg_global_pll_state().bits()), + ) + .field( + "pmu_ana_i2c_iso_en_state", + &format_args!("{}", self.pmu_ana_i2c_iso_en_state().bit()), + ) + .field( + "pmu_ana_i2c_retention_state", + &format_args!("{}", self.pmu_ana_i2c_retention_state().bit()), + ) + .field( + "pmu_ana_xpd_pll_state", + &format_args!("{}", self.pmu_ana_xpd_pll_state().bits()), + ) + .field( + "pmu_ana_xpd_xtal_state", + &format_args!("{}", self.pmu_ana_xpd_xtal_state().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_STATE0_SPEC; +impl crate::RegisterSpec for CLK_STATE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_state0::R`](R) reader structure"] +impl crate::Readable for CLK_STATE0_SPEC {} +#[doc = "`reset()` method sets CLK_STATE0 to value 0x0f"] +impl crate::Resettable for CLK_STATE0_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/pmu/clk_state1.rs b/esp32p4/src/pmu/clk_state1.rs new file mode 100644 index 0000000000..d70b4f77bc --- /dev/null +++ b/esp32p4/src/pmu/clk_state1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CLK_STATE1` reader"] +pub type R = crate::R; +#[doc = "Field `PMU_ICG_FUNC_EN_STATE` reader - need_des"] +pub type PMU_ICG_FUNC_EN_STATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn pmu_icg_func_en_state(&self) -> PMU_ICG_FUNC_EN_STATE_R { + PMU_ICG_FUNC_EN_STATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_STATE1") + .field( + "pmu_icg_func_en_state", + &format_args!("{}", self.pmu_icg_func_en_state().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_STATE1_SPEC; +impl crate::RegisterSpec for CLK_STATE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_state1::R`](R) reader structure"] +impl crate::Readable for CLK_STATE1_SPEC {} +#[doc = "`reset()` method sets CLK_STATE1 to value 0xffff_ffff"] +impl crate::Resettable for CLK_STATE1_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/pmu/clk_state2.rs b/esp32p4/src/pmu/clk_state2.rs new file mode 100644 index 0000000000..b189b49f4f --- /dev/null +++ b/esp32p4/src/pmu/clk_state2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CLK_STATE2` reader"] +pub type R = crate::R; +#[doc = "Field `PMU_ICG_APB_EN_STATE` reader - need_des"] +pub type PMU_ICG_APB_EN_STATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn pmu_icg_apb_en_state(&self) -> PMU_ICG_APB_EN_STATE_R { + PMU_ICG_APB_EN_STATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_STATE2") + .field( + "pmu_icg_apb_en_state", + &format_args!("{}", self.pmu_icg_apb_en_state().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_STATE2_SPEC; +impl crate::RegisterSpec for CLK_STATE2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_state2::R`](R) reader structure"] +impl crate::Readable for CLK_STATE2_SPEC {} +#[doc = "`reset()` method sets CLK_STATE2 to value 0xffff_ffff"] +impl crate::Resettable for CLK_STATE2_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/pmu/cpu_sw_stall.rs b/esp32p4/src/pmu/cpu_sw_stall.rs new file mode 100644 index 0000000000..5aa5c056fd --- /dev/null +++ b/esp32p4/src/pmu/cpu_sw_stall.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CPU_SW_STALL` reader"] +pub type R = crate::R; +#[doc = "Register `CPU_SW_STALL` writer"] +pub type W = crate::W; +#[doc = "Field `HPCORE1_SW_STALL_CODE` reader - need_des"] +pub type HPCORE1_SW_STALL_CODE_R = crate::FieldReader; +#[doc = "Field `HPCORE1_SW_STALL_CODE` writer - need_des"] +pub type HPCORE1_SW_STALL_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HPCORE0_SW_STALL_CODE` reader - need_des"] +pub type HPCORE0_SW_STALL_CODE_R = crate::FieldReader; +#[doc = "Field `HPCORE0_SW_STALL_CODE` writer - need_des"] +pub type HPCORE0_SW_STALL_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + pub fn hpcore1_sw_stall_code(&self) -> HPCORE1_SW_STALL_CODE_R { + HPCORE1_SW_STALL_CODE_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + pub fn hpcore0_sw_stall_code(&self) -> HPCORE0_SW_STALL_CODE_R { + HPCORE0_SW_STALL_CODE_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CPU_SW_STALL") + .field( + "hpcore1_sw_stall_code", + &format_args!("{}", self.hpcore1_sw_stall_code().bits()), + ) + .field( + "hpcore0_sw_stall_code", + &format_args!("{}", self.hpcore0_sw_stall_code().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + #[must_use] + pub fn hpcore1_sw_stall_code(&mut self) -> HPCORE1_SW_STALL_CODE_W { + HPCORE1_SW_STALL_CODE_W::new(self, 16) + } + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hpcore0_sw_stall_code(&mut self) -> HPCORE0_SW_STALL_CODE_W { + HPCORE0_SW_STALL_CODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_sw_stall::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_sw_stall::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPU_SW_STALL_SPEC; +impl crate::RegisterSpec for CPU_SW_STALL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpu_sw_stall::R`](R) reader structure"] +impl crate::Readable for CPU_SW_STALL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpu_sw_stall::W`](W) writer structure"] +impl crate::Writable for CPU_SW_STALL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CPU_SW_STALL to value 0"] +impl crate::Resettable for CPU_SW_STALL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/date.rs b/esp32p4/src/pmu/date.rs new file mode 100644 index 0000000000..c019c8bf7d --- /dev/null +++ b/esp32p4/src/pmu/date.rs @@ -0,0 +1,79 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `PMU_DATE` reader - need_des"] +pub type PMU_DATE_R = crate::FieldReader; +#[doc = "Field `PMU_DATE` writer - need_des"] +pub type PMU_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `CLK_EN` reader - need_des"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - need_des"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn pmu_date(&self) -> PMU_DATE_R { + PMU_DATE_R::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("pmu_date", &format_args!("{}", self.pmu_date().bits())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn pmu_date(&mut self) -> PMU_DATE_W { + PMU_DATE_W::new(self, 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_3140"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_3140; +} diff --git a/esp32p4/src/pmu/dcm_ctrl.rs b/esp32p4/src/pmu/dcm_ctrl.rs new file mode 100644 index 0000000000..eb4e000871 --- /dev/null +++ b/esp32p4/src/pmu/dcm_ctrl.rs @@ -0,0 +1,277 @@ +#[doc = "Register `DCM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DCM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DCDC_ON_REQ` writer - SW trigger dcdc on"] +pub type DCDC_ON_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_OFF_REQ` writer - SW trigger dcdc off"] +pub type DCDC_OFF_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_LIGHTSLP_REQ` writer - SW trigger dcdc enter lightsleep"] +pub type DCDC_LIGHTSLP_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_DEEPSLP_REQ` writer - SW trigger dcdc enter deepsleep"] +pub type DCDC_DEEPSLP_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_DONE_FORCE` reader - need_des"] +pub type DCDC_DONE_FORCE_R = crate::BitReader; +#[doc = "Field `DCDC_DONE_FORCE` writer - need_des"] +pub type DCDC_DONE_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_ON_FORCE_PU` reader - need_des"] +pub type DCDC_ON_FORCE_PU_R = crate::BitReader; +#[doc = "Field `DCDC_ON_FORCE_PU` writer - need_des"] +pub type DCDC_ON_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_ON_FORCE_PD` reader - need_des"] +pub type DCDC_ON_FORCE_PD_R = crate::BitReader; +#[doc = "Field `DCDC_ON_FORCE_PD` writer - need_des"] +pub type DCDC_ON_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_FB_RES_FORCE_PU` reader - need_des"] +pub type DCDC_FB_RES_FORCE_PU_R = crate::BitReader; +#[doc = "Field `DCDC_FB_RES_FORCE_PU` writer - need_des"] +pub type DCDC_FB_RES_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_FB_RES_FORCE_PD` reader - need_des"] +pub type DCDC_FB_RES_FORCE_PD_R = crate::BitReader; +#[doc = "Field `DCDC_FB_RES_FORCE_PD` writer - need_des"] +pub type DCDC_FB_RES_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_LS_FORCE_PU` reader - need_des"] +pub type DCDC_LS_FORCE_PU_R = crate::BitReader; +#[doc = "Field `DCDC_LS_FORCE_PU` writer - need_des"] +pub type DCDC_LS_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_LS_FORCE_PD` reader - need_des"] +pub type DCDC_LS_FORCE_PD_R = crate::BitReader; +#[doc = "Field `DCDC_LS_FORCE_PD` writer - need_des"] +pub type DCDC_LS_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_DS_FORCE_PU` reader - need_des"] +pub type DCDC_DS_FORCE_PU_R = crate::BitReader; +#[doc = "Field `DCDC_DS_FORCE_PU` writer - need_des"] +pub type DCDC_DS_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDC_DS_FORCE_PD` reader - need_des"] +pub type DCDC_DS_FORCE_PD_R = crate::BitReader; +#[doc = "Field `DCDC_DS_FORCE_PD` writer - need_des"] +pub type DCDC_DS_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCM_CUR_ST` reader - need_des"] +pub type DCM_CUR_ST_R = crate::FieldReader; +#[doc = "Field `DCDC_EN_AMUX_TEST` reader - Enable analog mux to pull PAD TEST_DCDC voltage signal"] +pub type DCDC_EN_AMUX_TEST_R = crate::BitReader; +#[doc = "Field `DCDC_EN_AMUX_TEST` writer - Enable analog mux to pull PAD TEST_DCDC voltage signal"] +pub type DCDC_EN_AMUX_TEST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + pub fn dcdc_done_force(&self) -> DCDC_DONE_FORCE_R { + DCDC_DONE_FORCE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + pub fn dcdc_on_force_pu(&self) -> DCDC_ON_FORCE_PU_R { + DCDC_ON_FORCE_PU_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - need_des"] + #[inline(always)] + pub fn dcdc_on_force_pd(&self) -> DCDC_ON_FORCE_PD_R { + DCDC_ON_FORCE_PD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + pub fn dcdc_fb_res_force_pu(&self) -> DCDC_FB_RES_FORCE_PU_R { + DCDC_FB_RES_FORCE_PU_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + pub fn dcdc_fb_res_force_pd(&self) -> DCDC_FB_RES_FORCE_PD_R { + DCDC_FB_RES_FORCE_PD_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn dcdc_ls_force_pu(&self) -> DCDC_LS_FORCE_PU_R { + DCDC_LS_FORCE_PU_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn dcdc_ls_force_pd(&self) -> DCDC_LS_FORCE_PD_R { + DCDC_LS_FORCE_PD_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + pub fn dcdc_ds_force_pu(&self) -> DCDC_DS_FORCE_PU_R { + DCDC_DS_FORCE_PU_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - need_des"] + #[inline(always)] + pub fn dcdc_ds_force_pd(&self) -> DCDC_DS_FORCE_PD_R { + DCDC_DS_FORCE_PD_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:23 - need_des"] + #[inline(always)] + pub fn dcm_cur_st(&self) -> DCM_CUR_ST_R { + DCM_CUR_ST_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 29 - Enable analog mux to pull PAD TEST_DCDC voltage signal"] + #[inline(always)] + pub fn dcdc_en_amux_test(&self) -> DCDC_EN_AMUX_TEST_R { + DCDC_EN_AMUX_TEST_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DCM_CTRL") + .field( + "dcdc_done_force", + &format_args!("{}", self.dcdc_done_force().bit()), + ) + .field( + "dcdc_on_force_pu", + &format_args!("{}", self.dcdc_on_force_pu().bit()), + ) + .field( + "dcdc_on_force_pd", + &format_args!("{}", self.dcdc_on_force_pd().bit()), + ) + .field( + "dcdc_fb_res_force_pu", + &format_args!("{}", self.dcdc_fb_res_force_pu().bit()), + ) + .field( + "dcdc_fb_res_force_pd", + &format_args!("{}", self.dcdc_fb_res_force_pd().bit()), + ) + .field( + "dcdc_ls_force_pu", + &format_args!("{}", self.dcdc_ls_force_pu().bit()), + ) + .field( + "dcdc_ls_force_pd", + &format_args!("{}", self.dcdc_ls_force_pd().bit()), + ) + .field( + "dcdc_ds_force_pu", + &format_args!("{}", self.dcdc_ds_force_pu().bit()), + ) + .field( + "dcdc_ds_force_pd", + &format_args!("{}", self.dcdc_ds_force_pd().bit()), + ) + .field("dcm_cur_st", &format_args!("{}", self.dcm_cur_st().bits())) + .field( + "dcdc_en_amux_test", + &format_args!("{}", self.dcdc_en_amux_test().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - SW trigger dcdc on"] + #[inline(always)] + #[must_use] + pub fn dcdc_on_req(&mut self) -> DCDC_ON_REQ_W { + DCDC_ON_REQ_W::new(self, 0) + } + #[doc = "Bit 1 - SW trigger dcdc off"] + #[inline(always)] + #[must_use] + pub fn dcdc_off_req(&mut self) -> DCDC_OFF_REQ_W { + DCDC_OFF_REQ_W::new(self, 1) + } + #[doc = "Bit 2 - SW trigger dcdc enter lightsleep"] + #[inline(always)] + #[must_use] + pub fn dcdc_lightslp_req(&mut self) -> DCDC_LIGHTSLP_REQ_W { + DCDC_LIGHTSLP_REQ_W::new(self, 2) + } + #[doc = "Bit 3 - SW trigger dcdc enter deepsleep"] + #[inline(always)] + #[must_use] + pub fn dcdc_deepslp_req(&mut self) -> DCDC_DEEPSLP_REQ_W { + DCDC_DEEPSLP_REQ_W::new(self, 3) + } + #[doc = "Bit 7 - need_des"] + #[inline(always)] + #[must_use] + pub fn dcdc_done_force(&mut self) -> DCDC_DONE_FORCE_W { + DCDC_DONE_FORCE_W::new(self, 7) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + #[must_use] + pub fn dcdc_on_force_pu(&mut self) -> DCDC_ON_FORCE_PU_W { + DCDC_ON_FORCE_PU_W::new(self, 8) + } + #[doc = "Bit 9 - need_des"] + #[inline(always)] + #[must_use] + pub fn dcdc_on_force_pd(&mut self) -> DCDC_ON_FORCE_PD_W { + DCDC_ON_FORCE_PD_W::new(self, 9) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + #[must_use] + pub fn dcdc_fb_res_force_pu(&mut self) -> DCDC_FB_RES_FORCE_PU_W { + DCDC_FB_RES_FORCE_PU_W::new(self, 10) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + #[must_use] + pub fn dcdc_fb_res_force_pd(&mut self) -> DCDC_FB_RES_FORCE_PD_W { + DCDC_FB_RES_FORCE_PD_W::new(self, 11) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn dcdc_ls_force_pu(&mut self) -> DCDC_LS_FORCE_PU_W { + DCDC_LS_FORCE_PU_W::new(self, 12) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn dcdc_ls_force_pd(&mut self) -> DCDC_LS_FORCE_PD_W { + DCDC_LS_FORCE_PD_W::new(self, 13) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + #[must_use] + pub fn dcdc_ds_force_pu(&mut self) -> DCDC_DS_FORCE_PU_W { + DCDC_DS_FORCE_PU_W::new(self, 14) + } + #[doc = "Bit 15 - need_des"] + #[inline(always)] + #[must_use] + pub fn dcdc_ds_force_pd(&mut self) -> DCDC_DS_FORCE_PD_W { + DCDC_DS_FORCE_PD_W::new(self, 15) + } + #[doc = "Bit 29 - Enable analog mux to pull PAD TEST_DCDC voltage signal"] + #[inline(always)] + #[must_use] + pub fn dcdc_en_amux_test(&mut self) -> DCDC_EN_AMUX_TEST_W { + DCDC_EN_AMUX_TEST_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcm_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcm_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DCM_CTRL_SPEC; +impl crate::RegisterSpec for DCM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dcm_ctrl::R`](R) reader structure"] +impl crate::Readable for DCM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcm_ctrl::W`](W) writer structure"] +impl crate::Writable for DCM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DCM_CTRL to value 0x0001_0000"] +impl crate::Resettable for DCM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0000; +} diff --git a/esp32p4/src/pmu/dcm_wait_delay.rs b/esp32p4/src/pmu/dcm_wait_delay.rs new file mode 100644 index 0000000000..50a3c0b44e --- /dev/null +++ b/esp32p4/src/pmu/dcm_wait_delay.rs @@ -0,0 +1,104 @@ +#[doc = "Register `DCM_WAIT_DELAY` reader"] +pub type R = crate::R; +#[doc = "Register `DCM_WAIT_DELAY` writer"] +pub type W = crate::W; +#[doc = "Field `DCDC_PRE_DELAY` reader - DCDC pre-on/post off delay"] +pub type DCDC_PRE_DELAY_R = crate::FieldReader; +#[doc = "Field `DCDC_PRE_DELAY` writer - DCDC pre-on/post off delay"] +pub type DCDC_PRE_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DCDC_RES_OFF_DELAY` reader - DCDC fb res off delay"] +pub type DCDC_RES_OFF_DELAY_R = crate::FieldReader; +#[doc = "Field `DCDC_RES_OFF_DELAY` writer - DCDC fb res off delay"] +pub type DCDC_RES_OFF_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DCDC_STABLE_DELAY` reader - DCDC stable delay"] +pub type DCDC_STABLE_DELAY_R = crate::FieldReader; +#[doc = "Field `DCDC_STABLE_DELAY` writer - DCDC stable delay"] +pub type DCDC_STABLE_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:7 - DCDC pre-on/post off delay"] + #[inline(always)] + pub fn dcdc_pre_delay(&self) -> DCDC_PRE_DELAY_R { + DCDC_PRE_DELAY_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - DCDC fb res off delay"] + #[inline(always)] + pub fn dcdc_res_off_delay(&self) -> DCDC_RES_OFF_DELAY_R { + DCDC_RES_OFF_DELAY_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:25 - DCDC stable delay"] + #[inline(always)] + pub fn dcdc_stable_delay(&self) -> DCDC_STABLE_DELAY_R { + DCDC_STABLE_DELAY_R::new(((self.bits >> 16) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DCM_WAIT_DELAY") + .field( + "dcdc_pre_delay", + &format_args!("{}", self.dcdc_pre_delay().bits()), + ) + .field( + "dcdc_res_off_delay", + &format_args!("{}", self.dcdc_res_off_delay().bits()), + ) + .field( + "dcdc_stable_delay", + &format_args!("{}", self.dcdc_stable_delay().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - DCDC pre-on/post off delay"] + #[inline(always)] + #[must_use] + pub fn dcdc_pre_delay(&mut self) -> DCDC_PRE_DELAY_W { + DCDC_PRE_DELAY_W::new(self, 0) + } + #[doc = "Bits 8:15 - DCDC fb res off delay"] + #[inline(always)] + #[must_use] + pub fn dcdc_res_off_delay(&mut self) -> DCDC_RES_OFF_DELAY_W { + DCDC_RES_OFF_DELAY_W::new(self, 8) + } + #[doc = "Bits 16:25 - DCDC stable delay"] + #[inline(always)] + #[must_use] + pub fn dcdc_stable_delay(&mut self) -> DCDC_STABLE_DELAY_W { + DCDC_STABLE_DELAY_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcm_wait_delay::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcm_wait_delay::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DCM_WAIT_DELAY_SPEC; +impl crate::RegisterSpec for DCM_WAIT_DELAY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dcm_wait_delay::R`](R) reader structure"] +impl crate::Readable for DCM_WAIT_DELAY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcm_wait_delay::W`](W) writer structure"] +impl crate::Writable for DCM_WAIT_DELAY_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DCM_WAIT_DELAY to value 0x004b_0205"] +impl crate::Resettable for DCM_WAIT_DELAY_SPEC { + const RESET_VALUE: Self::Ux = 0x004b_0205; +} diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p1a.rs b/esp32p4/src/pmu/ext_ldo_p0_0p1a.rs new file mode 100644 index 0000000000..1dda335d4f --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p0_0p1a.rs @@ -0,0 +1,217 @@ +#[doc = "Register `EXT_LDO_P0_0P1A` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P0_0P1A` writer"] +pub type W = crate::W; +#[doc = "Field `_0P1A_FORCE_TIEH_SEL_0` reader - need_des"] +pub type _0P1A_FORCE_TIEH_SEL_0_R = crate::BitReader; +#[doc = "Field `_0P1A_FORCE_TIEH_SEL_0` writer - need_des"] +pub type _0P1A_FORCE_TIEH_SEL_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_XPD_0` reader - need_des"] +pub type _0P1A_XPD_0_R = crate::BitReader; +#[doc = "Field `_0P1A_XPD_0` writer - need_des"] +pub type _0P1A_XPD_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_TIEH_SEL_0` reader - need_des"] +pub type _0P1A_TIEH_SEL_0_R = crate::FieldReader; +#[doc = "Field `_0P1A_TIEH_SEL_0` writer - need_des"] +pub type _0P1A_TIEH_SEL_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `_0P1A_TIEH_POS_EN_0` reader - need_des"] +pub type _0P1A_TIEH_POS_EN_0_R = crate::BitReader; +#[doc = "Field `_0P1A_TIEH_POS_EN_0` writer - need_des"] +pub type _0P1A_TIEH_POS_EN_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_TIEH_NEG_EN_0` reader - need_des"] +pub type _0P1A_TIEH_NEG_EN_0_R = crate::BitReader; +#[doc = "Field `_0P1A_TIEH_NEG_EN_0` writer - need_des"] +pub type _0P1A_TIEH_NEG_EN_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_TIEH_0` reader - need_des"] +pub type _0P1A_TIEH_0_R = crate::BitReader; +#[doc = "Field `_0P1A_TIEH_0` writer - need_des"] +pub type _0P1A_TIEH_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_TARGET1_0` reader - need_des"] +pub type _0P1A_TARGET1_0_R = crate::FieldReader; +#[doc = "Field `_0P1A_TARGET1_0` writer - need_des"] +pub type _0P1A_TARGET1_0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P1A_TARGET0_0` reader - need_des"] +pub type _0P1A_TARGET0_0_R = crate::FieldReader; +#[doc = "Field `_0P1A_TARGET0_0` writer - need_des"] +pub type _0P1A_TARGET0_0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P1A_LDO_CNT_PRESCALER_SEL_0` reader - need_des"] +pub type _0P1A_LDO_CNT_PRESCALER_SEL_0_R = crate::BitReader; +#[doc = "Field `_0P1A_LDO_CNT_PRESCALER_SEL_0` writer - need_des"] +pub type _0P1A_LDO_CNT_PRESCALER_SEL_0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + pub fn _0p1a_force_tieh_sel_0(&self) -> _0P1A_FORCE_TIEH_SEL_0_R { + _0P1A_FORCE_TIEH_SEL_0_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + pub fn _0p1a_xpd_0(&self) -> _0P1A_XPD_0_R { + _0P1A_XPD_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + pub fn _0p1a_tieh_sel_0(&self) -> _0P1A_TIEH_SEL_0_R { + _0P1A_TIEH_SEL_0_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn _0p1a_tieh_pos_en_0(&self) -> _0P1A_TIEH_POS_EN_0_R { + _0P1A_TIEH_POS_EN_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn _0p1a_tieh_neg_en_0(&self) -> _0P1A_TIEH_NEG_EN_0_R { + _0P1A_TIEH_NEG_EN_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + pub fn _0p1a_tieh_0(&self) -> _0P1A_TIEH_0_R { + _0P1A_TIEH_0_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + pub fn _0p1a_target1_0(&self) -> _0P1A_TARGET1_0_R { + _0P1A_TARGET1_0_R::new(((self.bits >> 15) & 0xff) as u8) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + pub fn _0p1a_target0_0(&self) -> _0P1A_TARGET0_0_R { + _0P1A_TARGET0_0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn _0p1a_ldo_cnt_prescaler_sel_0(&self) -> _0P1A_LDO_CNT_PRESCALER_SEL_0_R { + _0P1A_LDO_CNT_PRESCALER_SEL_0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P0_0P1A") + .field( + "_0p1a_force_tieh_sel_0", + &format_args!("{}", self._0p1a_force_tieh_sel_0().bit()), + ) + .field("_0p1a_xpd_0", &format_args!("{}", self._0p1a_xpd_0().bit())) + .field( + "_0p1a_tieh_sel_0", + &format_args!("{}", self._0p1a_tieh_sel_0().bits()), + ) + .field( + "_0p1a_tieh_pos_en_0", + &format_args!("{}", self._0p1a_tieh_pos_en_0().bit()), + ) + .field( + "_0p1a_tieh_neg_en_0", + &format_args!("{}", self._0p1a_tieh_neg_en_0().bit()), + ) + .field( + "_0p1a_tieh_0", + &format_args!("{}", self._0p1a_tieh_0().bit()), + ) + .field( + "_0p1a_target1_0", + &format_args!("{}", self._0p1a_target1_0().bits()), + ) + .field( + "_0p1a_target0_0", + &format_args!("{}", self._0p1a_target0_0().bits()), + ) + .field( + "_0p1a_ldo_cnt_prescaler_sel_0", + &format_args!("{}", self._0p1a_ldo_cnt_prescaler_sel_0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_force_tieh_sel_0(&mut self) -> _0P1A_FORCE_TIEH_SEL_0_W { + _0P1A_FORCE_TIEH_SEL_0_W::new(self, 7) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_xpd_0(&mut self) -> _0P1A_XPD_0_W { + _0P1A_XPD_0_W::new(self, 8) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_tieh_sel_0(&mut self) -> _0P1A_TIEH_SEL_0_W { + _0P1A_TIEH_SEL_0_W::new(self, 9) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_tieh_pos_en_0(&mut self) -> _0P1A_TIEH_POS_EN_0_W { + _0P1A_TIEH_POS_EN_0_W::new(self, 12) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_tieh_neg_en_0(&mut self) -> _0P1A_TIEH_NEG_EN_0_W { + _0P1A_TIEH_NEG_EN_0_W::new(self, 13) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_tieh_0(&mut self) -> _0P1A_TIEH_0_W { + _0P1A_TIEH_0_W::new(self, 14) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_target1_0(&mut self) -> _0P1A_TARGET1_0_W { + _0P1A_TARGET1_0_W::new(self, 15) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_target0_0(&mut self) -> _0P1A_TARGET0_0_W { + _0P1A_TARGET0_0_W::new(self, 23) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_ldo_cnt_prescaler_sel_0( + &mut self, + ) -> _0P1A_LDO_CNT_PRESCALER_SEL_0_W { + _0P1A_LDO_CNT_PRESCALER_SEL_0_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p1a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p1a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P0_0P1A_SPEC; +impl crate::RegisterSpec for EXT_LDO_P0_0P1A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p0_0p1a::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P0_0P1A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p0_0p1a::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P0_0P1A_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P0_0P1A to value 0x4020_0100"] +impl crate::Resettable for EXT_LDO_P0_0P1A_SPEC { + const RESET_VALUE: Self::Ux = 0x4020_0100; +} diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p1a_ana.rs b/esp32p4/src/pmu/ext_ldo_p0_0p1a_ana.rs new file mode 100644 index 0000000000..a9f0e62819 --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p0_0p1a_ana.rs @@ -0,0 +1,123 @@ +#[doc = "Register `EXT_LDO_P0_0P1A_ANA` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P0_0P1A_ANA` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_0P1A_MUL_0` reader - need_des"] +pub type ANA_0P1A_MUL_0_R = crate::FieldReader; +#[doc = "Field `ANA_0P1A_MUL_0` writer - need_des"] +pub type ANA_0P1A_MUL_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ANA_0P1A_EN_VDET_0` reader - need_des"] +pub type ANA_0P1A_EN_VDET_0_R = crate::BitReader; +#[doc = "Field `ANA_0P1A_EN_VDET_0` writer - need_des"] +pub type ANA_0P1A_EN_VDET_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P1A_EN_CUR_LIM_0` reader - need_des"] +pub type ANA_0P1A_EN_CUR_LIM_0_R = crate::BitReader; +#[doc = "Field `ANA_0P1A_EN_CUR_LIM_0` writer - need_des"] +pub type ANA_0P1A_EN_CUR_LIM_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P1A_DREF_0` reader - need_des"] +pub type ANA_0P1A_DREF_0_R = crate::FieldReader; +#[doc = "Field `ANA_0P1A_DREF_0` writer - need_des"] +pub type ANA_0P1A_DREF_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + pub fn ana_0p1a_mul_0(&self) -> ANA_0P1A_MUL_0_R { + ANA_0P1A_MUL_0_R::new(((self.bits >> 23) & 7) as u8) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn ana_0p1a_en_vdet_0(&self) -> ANA_0P1A_EN_VDET_0_R { + ANA_0P1A_EN_VDET_0_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn ana_0p1a_en_cur_lim_0(&self) -> ANA_0P1A_EN_CUR_LIM_0_R { + ANA_0P1A_EN_CUR_LIM_0_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + pub fn ana_0p1a_dref_0(&self) -> ANA_0P1A_DREF_0_R { + ANA_0P1A_DREF_0_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P0_0P1A_ANA") + .field( + "ana_0p1a_mul_0", + &format_args!("{}", self.ana_0p1a_mul_0().bits()), + ) + .field( + "ana_0p1a_en_vdet_0", + &format_args!("{}", self.ana_0p1a_en_vdet_0().bit()), + ) + .field( + "ana_0p1a_en_cur_lim_0", + &format_args!("{}", self.ana_0p1a_en_cur_lim_0().bit()), + ) + .field( + "ana_0p1a_dref_0", + &format_args!("{}", self.ana_0p1a_dref_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p1a_mul_0(&mut self) -> ANA_0P1A_MUL_0_W { + ANA_0P1A_MUL_0_W::new(self, 23) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p1a_en_vdet_0(&mut self) -> ANA_0P1A_EN_VDET_0_W { + ANA_0P1A_EN_VDET_0_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p1a_en_cur_lim_0(&mut self) -> ANA_0P1A_EN_CUR_LIM_0_W { + ANA_0P1A_EN_CUR_LIM_0_W::new(self, 27) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p1a_dref_0(&mut self) -> ANA_0P1A_DREF_0_W { + ANA_0P1A_DREF_0_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p1a_ana::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p1a_ana::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P0_0P1A_ANA_SPEC; +impl crate::RegisterSpec for EXT_LDO_P0_0P1A_ANA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p0_0p1a_ana::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P0_0P1A_ANA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p0_0p1a_ana::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P0_0P1A_ANA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P0_0P1A_ANA to value 0xb100_0000"] +impl crate::Resettable for EXT_LDO_P0_0P1A_ANA_SPEC { + const RESET_VALUE: Self::Ux = 0xb100_0000; +} diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p2a.rs b/esp32p4/src/pmu/ext_ldo_p0_0p2a.rs new file mode 100644 index 0000000000..186acc50c0 --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p0_0p2a.rs @@ -0,0 +1,217 @@ +#[doc = "Register `EXT_LDO_P0_0P2A` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P0_0P2A` writer"] +pub type W = crate::W; +#[doc = "Field `_0P2A_FORCE_TIEH_SEL_0` reader - need_des"] +pub type _0P2A_FORCE_TIEH_SEL_0_R = crate::BitReader; +#[doc = "Field `_0P2A_FORCE_TIEH_SEL_0` writer - need_des"] +pub type _0P2A_FORCE_TIEH_SEL_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_XPD_0` reader - need_des"] +pub type _0P2A_XPD_0_R = crate::BitReader; +#[doc = "Field `_0P2A_XPD_0` writer - need_des"] +pub type _0P2A_XPD_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_TIEH_SEL_0` reader - need_des"] +pub type _0P2A_TIEH_SEL_0_R = crate::FieldReader; +#[doc = "Field `_0P2A_TIEH_SEL_0` writer - need_des"] +pub type _0P2A_TIEH_SEL_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `_0P2A_TIEH_POS_EN_0` reader - need_des"] +pub type _0P2A_TIEH_POS_EN_0_R = crate::BitReader; +#[doc = "Field `_0P2A_TIEH_POS_EN_0` writer - need_des"] +pub type _0P2A_TIEH_POS_EN_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_TIEH_NEG_EN_0` reader - need_des"] +pub type _0P2A_TIEH_NEG_EN_0_R = crate::BitReader; +#[doc = "Field `_0P2A_TIEH_NEG_EN_0` writer - need_des"] +pub type _0P2A_TIEH_NEG_EN_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_TIEH_0` reader - need_des"] +pub type _0P2A_TIEH_0_R = crate::BitReader; +#[doc = "Field `_0P2A_TIEH_0` writer - need_des"] +pub type _0P2A_TIEH_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_TARGET1_0` reader - need_des"] +pub type _0P2A_TARGET1_0_R = crate::FieldReader; +#[doc = "Field `_0P2A_TARGET1_0` writer - need_des"] +pub type _0P2A_TARGET1_0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P2A_TARGET0_0` reader - need_des"] +pub type _0P2A_TARGET0_0_R = crate::FieldReader; +#[doc = "Field `_0P2A_TARGET0_0` writer - need_des"] +pub type _0P2A_TARGET0_0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P2A_LDO_CNT_PRESCALER_SEL_0` reader - need_des"] +pub type _0P2A_LDO_CNT_PRESCALER_SEL_0_R = crate::BitReader; +#[doc = "Field `_0P2A_LDO_CNT_PRESCALER_SEL_0` writer - need_des"] +pub type _0P2A_LDO_CNT_PRESCALER_SEL_0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + pub fn _0p2a_force_tieh_sel_0(&self) -> _0P2A_FORCE_TIEH_SEL_0_R { + _0P2A_FORCE_TIEH_SEL_0_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + pub fn _0p2a_xpd_0(&self) -> _0P2A_XPD_0_R { + _0P2A_XPD_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + pub fn _0p2a_tieh_sel_0(&self) -> _0P2A_TIEH_SEL_0_R { + _0P2A_TIEH_SEL_0_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn _0p2a_tieh_pos_en_0(&self) -> _0P2A_TIEH_POS_EN_0_R { + _0P2A_TIEH_POS_EN_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn _0p2a_tieh_neg_en_0(&self) -> _0P2A_TIEH_NEG_EN_0_R { + _0P2A_TIEH_NEG_EN_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + pub fn _0p2a_tieh_0(&self) -> _0P2A_TIEH_0_R { + _0P2A_TIEH_0_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + pub fn _0p2a_target1_0(&self) -> _0P2A_TARGET1_0_R { + _0P2A_TARGET1_0_R::new(((self.bits >> 15) & 0xff) as u8) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + pub fn _0p2a_target0_0(&self) -> _0P2A_TARGET0_0_R { + _0P2A_TARGET0_0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn _0p2a_ldo_cnt_prescaler_sel_0(&self) -> _0P2A_LDO_CNT_PRESCALER_SEL_0_R { + _0P2A_LDO_CNT_PRESCALER_SEL_0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P0_0P2A") + .field( + "_0p2a_force_tieh_sel_0", + &format_args!("{}", self._0p2a_force_tieh_sel_0().bit()), + ) + .field("_0p2a_xpd_0", &format_args!("{}", self._0p2a_xpd_0().bit())) + .field( + "_0p2a_tieh_sel_0", + &format_args!("{}", self._0p2a_tieh_sel_0().bits()), + ) + .field( + "_0p2a_tieh_pos_en_0", + &format_args!("{}", self._0p2a_tieh_pos_en_0().bit()), + ) + .field( + "_0p2a_tieh_neg_en_0", + &format_args!("{}", self._0p2a_tieh_neg_en_0().bit()), + ) + .field( + "_0p2a_tieh_0", + &format_args!("{}", self._0p2a_tieh_0().bit()), + ) + .field( + "_0p2a_target1_0", + &format_args!("{}", self._0p2a_target1_0().bits()), + ) + .field( + "_0p2a_target0_0", + &format_args!("{}", self._0p2a_target0_0().bits()), + ) + .field( + "_0p2a_ldo_cnt_prescaler_sel_0", + &format_args!("{}", self._0p2a_ldo_cnt_prescaler_sel_0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_force_tieh_sel_0(&mut self) -> _0P2A_FORCE_TIEH_SEL_0_W { + _0P2A_FORCE_TIEH_SEL_0_W::new(self, 7) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_xpd_0(&mut self) -> _0P2A_XPD_0_W { + _0P2A_XPD_0_W::new(self, 8) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_tieh_sel_0(&mut self) -> _0P2A_TIEH_SEL_0_W { + _0P2A_TIEH_SEL_0_W::new(self, 9) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_tieh_pos_en_0(&mut self) -> _0P2A_TIEH_POS_EN_0_W { + _0P2A_TIEH_POS_EN_0_W::new(self, 12) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_tieh_neg_en_0(&mut self) -> _0P2A_TIEH_NEG_EN_0_W { + _0P2A_TIEH_NEG_EN_0_W::new(self, 13) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_tieh_0(&mut self) -> _0P2A_TIEH_0_W { + _0P2A_TIEH_0_W::new(self, 14) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_target1_0(&mut self) -> _0P2A_TARGET1_0_W { + _0P2A_TARGET1_0_W::new(self, 15) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_target0_0(&mut self) -> _0P2A_TARGET0_0_W { + _0P2A_TARGET0_0_W::new(self, 23) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_ldo_cnt_prescaler_sel_0( + &mut self, + ) -> _0P2A_LDO_CNT_PRESCALER_SEL_0_W { + _0P2A_LDO_CNT_PRESCALER_SEL_0_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p2a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p2a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P0_0P2A_SPEC; +impl crate::RegisterSpec for EXT_LDO_P0_0P2A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p0_0p2a::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P0_0P2A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p0_0p2a::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P0_0P2A_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P0_0P2A to value 0x4020_0000"] +impl crate::Resettable for EXT_LDO_P0_0P2A_SPEC { + const RESET_VALUE: Self::Ux = 0x4020_0000; +} diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p2a_ana.rs b/esp32p4/src/pmu/ext_ldo_p0_0p2a_ana.rs new file mode 100644 index 0000000000..fbfde91ac6 --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p0_0p2a_ana.rs @@ -0,0 +1,123 @@ +#[doc = "Register `EXT_LDO_P0_0P2A_ANA` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P0_0P2A_ANA` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_0P2A_MUL_0` reader - need_des"] +pub type ANA_0P2A_MUL_0_R = crate::FieldReader; +#[doc = "Field `ANA_0P2A_MUL_0` writer - need_des"] +pub type ANA_0P2A_MUL_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ANA_0P2A_EN_VDET_0` reader - need_des"] +pub type ANA_0P2A_EN_VDET_0_R = crate::BitReader; +#[doc = "Field `ANA_0P2A_EN_VDET_0` writer - need_des"] +pub type ANA_0P2A_EN_VDET_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P2A_EN_CUR_LIM_0` reader - need_des"] +pub type ANA_0P2A_EN_CUR_LIM_0_R = crate::BitReader; +#[doc = "Field `ANA_0P2A_EN_CUR_LIM_0` writer - need_des"] +pub type ANA_0P2A_EN_CUR_LIM_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P2A_DREF_0` reader - need_des"] +pub type ANA_0P2A_DREF_0_R = crate::FieldReader; +#[doc = "Field `ANA_0P2A_DREF_0` writer - need_des"] +pub type ANA_0P2A_DREF_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + pub fn ana_0p2a_mul_0(&self) -> ANA_0P2A_MUL_0_R { + ANA_0P2A_MUL_0_R::new(((self.bits >> 23) & 7) as u8) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn ana_0p2a_en_vdet_0(&self) -> ANA_0P2A_EN_VDET_0_R { + ANA_0P2A_EN_VDET_0_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn ana_0p2a_en_cur_lim_0(&self) -> ANA_0P2A_EN_CUR_LIM_0_R { + ANA_0P2A_EN_CUR_LIM_0_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + pub fn ana_0p2a_dref_0(&self) -> ANA_0P2A_DREF_0_R { + ANA_0P2A_DREF_0_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P0_0P2A_ANA") + .field( + "ana_0p2a_mul_0", + &format_args!("{}", self.ana_0p2a_mul_0().bits()), + ) + .field( + "ana_0p2a_en_vdet_0", + &format_args!("{}", self.ana_0p2a_en_vdet_0().bit()), + ) + .field( + "ana_0p2a_en_cur_lim_0", + &format_args!("{}", self.ana_0p2a_en_cur_lim_0().bit()), + ) + .field( + "ana_0p2a_dref_0", + &format_args!("{}", self.ana_0p2a_dref_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p2a_mul_0(&mut self) -> ANA_0P2A_MUL_0_W { + ANA_0P2A_MUL_0_W::new(self, 23) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p2a_en_vdet_0(&mut self) -> ANA_0P2A_EN_VDET_0_W { + ANA_0P2A_EN_VDET_0_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p2a_en_cur_lim_0(&mut self) -> ANA_0P2A_EN_CUR_LIM_0_W { + ANA_0P2A_EN_CUR_LIM_0_W::new(self, 27) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p2a_dref_0(&mut self) -> ANA_0P2A_DREF_0_W { + ANA_0P2A_DREF_0_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p2a_ana::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p2a_ana::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P0_0P2A_ANA_SPEC; +impl crate::RegisterSpec for EXT_LDO_P0_0P2A_ANA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p0_0p2a_ana::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P0_0P2A_ANA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p0_0p2a_ana::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P0_0P2A_ANA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P0_0P2A_ANA to value 0xa000_0000"] +impl crate::Resettable for EXT_LDO_P0_0P2A_ANA_SPEC { + const RESET_VALUE: Self::Ux = 0xa000_0000; +} diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p3a.rs b/esp32p4/src/pmu/ext_ldo_p0_0p3a.rs new file mode 100644 index 0000000000..35dbc1d37f --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p0_0p3a.rs @@ -0,0 +1,217 @@ +#[doc = "Register `EXT_LDO_P0_0P3A` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P0_0P3A` writer"] +pub type W = crate::W; +#[doc = "Field `_0P3A_FORCE_TIEH_SEL_0` reader - need_des"] +pub type _0P3A_FORCE_TIEH_SEL_0_R = crate::BitReader; +#[doc = "Field `_0P3A_FORCE_TIEH_SEL_0` writer - need_des"] +pub type _0P3A_FORCE_TIEH_SEL_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_XPD_0` reader - need_des"] +pub type _0P3A_XPD_0_R = crate::BitReader; +#[doc = "Field `_0P3A_XPD_0` writer - need_des"] +pub type _0P3A_XPD_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_TIEH_SEL_0` reader - need_des"] +pub type _0P3A_TIEH_SEL_0_R = crate::FieldReader; +#[doc = "Field `_0P3A_TIEH_SEL_0` writer - need_des"] +pub type _0P3A_TIEH_SEL_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `_0P3A_TIEH_POS_EN_0` reader - need_des"] +pub type _0P3A_TIEH_POS_EN_0_R = crate::BitReader; +#[doc = "Field `_0P3A_TIEH_POS_EN_0` writer - need_des"] +pub type _0P3A_TIEH_POS_EN_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_TIEH_NEG_EN_0` reader - need_des"] +pub type _0P3A_TIEH_NEG_EN_0_R = crate::BitReader; +#[doc = "Field `_0P3A_TIEH_NEG_EN_0` writer - need_des"] +pub type _0P3A_TIEH_NEG_EN_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_TIEH_0` reader - need_des"] +pub type _0P3A_TIEH_0_R = crate::BitReader; +#[doc = "Field `_0P3A_TIEH_0` writer - need_des"] +pub type _0P3A_TIEH_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_TARGET1_0` reader - need_des"] +pub type _0P3A_TARGET1_0_R = crate::FieldReader; +#[doc = "Field `_0P3A_TARGET1_0` writer - need_des"] +pub type _0P3A_TARGET1_0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P3A_TARGET0_0` reader - need_des"] +pub type _0P3A_TARGET0_0_R = crate::FieldReader; +#[doc = "Field `_0P3A_TARGET0_0` writer - need_des"] +pub type _0P3A_TARGET0_0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P3A_LDO_CNT_PRESCALER_SEL_0` reader - need_des"] +pub type _0P3A_LDO_CNT_PRESCALER_SEL_0_R = crate::BitReader; +#[doc = "Field `_0P3A_LDO_CNT_PRESCALER_SEL_0` writer - need_des"] +pub type _0P3A_LDO_CNT_PRESCALER_SEL_0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + pub fn _0p3a_force_tieh_sel_0(&self) -> _0P3A_FORCE_TIEH_SEL_0_R { + _0P3A_FORCE_TIEH_SEL_0_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + pub fn _0p3a_xpd_0(&self) -> _0P3A_XPD_0_R { + _0P3A_XPD_0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + pub fn _0p3a_tieh_sel_0(&self) -> _0P3A_TIEH_SEL_0_R { + _0P3A_TIEH_SEL_0_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn _0p3a_tieh_pos_en_0(&self) -> _0P3A_TIEH_POS_EN_0_R { + _0P3A_TIEH_POS_EN_0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn _0p3a_tieh_neg_en_0(&self) -> _0P3A_TIEH_NEG_EN_0_R { + _0P3A_TIEH_NEG_EN_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + pub fn _0p3a_tieh_0(&self) -> _0P3A_TIEH_0_R { + _0P3A_TIEH_0_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + pub fn _0p3a_target1_0(&self) -> _0P3A_TARGET1_0_R { + _0P3A_TARGET1_0_R::new(((self.bits >> 15) & 0xff) as u8) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + pub fn _0p3a_target0_0(&self) -> _0P3A_TARGET0_0_R { + _0P3A_TARGET0_0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn _0p3a_ldo_cnt_prescaler_sel_0(&self) -> _0P3A_LDO_CNT_PRESCALER_SEL_0_R { + _0P3A_LDO_CNT_PRESCALER_SEL_0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P0_0P3A") + .field( + "_0p3a_force_tieh_sel_0", + &format_args!("{}", self._0p3a_force_tieh_sel_0().bit()), + ) + .field("_0p3a_xpd_0", &format_args!("{}", self._0p3a_xpd_0().bit())) + .field( + "_0p3a_tieh_sel_0", + &format_args!("{}", self._0p3a_tieh_sel_0().bits()), + ) + .field( + "_0p3a_tieh_pos_en_0", + &format_args!("{}", self._0p3a_tieh_pos_en_0().bit()), + ) + .field( + "_0p3a_tieh_neg_en_0", + &format_args!("{}", self._0p3a_tieh_neg_en_0().bit()), + ) + .field( + "_0p3a_tieh_0", + &format_args!("{}", self._0p3a_tieh_0().bit()), + ) + .field( + "_0p3a_target1_0", + &format_args!("{}", self._0p3a_target1_0().bits()), + ) + .field( + "_0p3a_target0_0", + &format_args!("{}", self._0p3a_target0_0().bits()), + ) + .field( + "_0p3a_ldo_cnt_prescaler_sel_0", + &format_args!("{}", self._0p3a_ldo_cnt_prescaler_sel_0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_force_tieh_sel_0(&mut self) -> _0P3A_FORCE_TIEH_SEL_0_W { + _0P3A_FORCE_TIEH_SEL_0_W::new(self, 7) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_xpd_0(&mut self) -> _0P3A_XPD_0_W { + _0P3A_XPD_0_W::new(self, 8) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_tieh_sel_0(&mut self) -> _0P3A_TIEH_SEL_0_W { + _0P3A_TIEH_SEL_0_W::new(self, 9) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_tieh_pos_en_0(&mut self) -> _0P3A_TIEH_POS_EN_0_W { + _0P3A_TIEH_POS_EN_0_W::new(self, 12) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_tieh_neg_en_0(&mut self) -> _0P3A_TIEH_NEG_EN_0_W { + _0P3A_TIEH_NEG_EN_0_W::new(self, 13) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_tieh_0(&mut self) -> _0P3A_TIEH_0_W { + _0P3A_TIEH_0_W::new(self, 14) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_target1_0(&mut self) -> _0P3A_TARGET1_0_W { + _0P3A_TARGET1_0_W::new(self, 15) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_target0_0(&mut self) -> _0P3A_TARGET0_0_W { + _0P3A_TARGET0_0_W::new(self, 23) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_ldo_cnt_prescaler_sel_0( + &mut self, + ) -> _0P3A_LDO_CNT_PRESCALER_SEL_0_W { + _0P3A_LDO_CNT_PRESCALER_SEL_0_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p3a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p3a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P0_0P3A_SPEC; +impl crate::RegisterSpec for EXT_LDO_P0_0P3A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p0_0p3a::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P0_0P3A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p0_0p3a::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P0_0P3A_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P0_0P3A to value 0x4020_0000"] +impl crate::Resettable for EXT_LDO_P0_0P3A_SPEC { + const RESET_VALUE: Self::Ux = 0x4020_0000; +} diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p3a_ana.rs b/esp32p4/src/pmu/ext_ldo_p0_0p3a_ana.rs new file mode 100644 index 0000000000..d423b29ef7 --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p0_0p3a_ana.rs @@ -0,0 +1,123 @@ +#[doc = "Register `EXT_LDO_P0_0P3A_ANA` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P0_0P3A_ANA` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_0P3A_MUL_0` reader - need_des"] +pub type ANA_0P3A_MUL_0_R = crate::FieldReader; +#[doc = "Field `ANA_0P3A_MUL_0` writer - need_des"] +pub type ANA_0P3A_MUL_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ANA_0P3A_EN_VDET_0` reader - need_des"] +pub type ANA_0P3A_EN_VDET_0_R = crate::BitReader; +#[doc = "Field `ANA_0P3A_EN_VDET_0` writer - need_des"] +pub type ANA_0P3A_EN_VDET_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P3A_EN_CUR_LIM_0` reader - need_des"] +pub type ANA_0P3A_EN_CUR_LIM_0_R = crate::BitReader; +#[doc = "Field `ANA_0P3A_EN_CUR_LIM_0` writer - need_des"] +pub type ANA_0P3A_EN_CUR_LIM_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P3A_DREF_0` reader - need_des"] +pub type ANA_0P3A_DREF_0_R = crate::FieldReader; +#[doc = "Field `ANA_0P3A_DREF_0` writer - need_des"] +pub type ANA_0P3A_DREF_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + pub fn ana_0p3a_mul_0(&self) -> ANA_0P3A_MUL_0_R { + ANA_0P3A_MUL_0_R::new(((self.bits >> 23) & 7) as u8) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn ana_0p3a_en_vdet_0(&self) -> ANA_0P3A_EN_VDET_0_R { + ANA_0P3A_EN_VDET_0_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn ana_0p3a_en_cur_lim_0(&self) -> ANA_0P3A_EN_CUR_LIM_0_R { + ANA_0P3A_EN_CUR_LIM_0_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + pub fn ana_0p3a_dref_0(&self) -> ANA_0P3A_DREF_0_R { + ANA_0P3A_DREF_0_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P0_0P3A_ANA") + .field( + "ana_0p3a_mul_0", + &format_args!("{}", self.ana_0p3a_mul_0().bits()), + ) + .field( + "ana_0p3a_en_vdet_0", + &format_args!("{}", self.ana_0p3a_en_vdet_0().bit()), + ) + .field( + "ana_0p3a_en_cur_lim_0", + &format_args!("{}", self.ana_0p3a_en_cur_lim_0().bit()), + ) + .field( + "ana_0p3a_dref_0", + &format_args!("{}", self.ana_0p3a_dref_0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p3a_mul_0(&mut self) -> ANA_0P3A_MUL_0_W { + ANA_0P3A_MUL_0_W::new(self, 23) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p3a_en_vdet_0(&mut self) -> ANA_0P3A_EN_VDET_0_W { + ANA_0P3A_EN_VDET_0_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p3a_en_cur_lim_0(&mut self) -> ANA_0P3A_EN_CUR_LIM_0_W { + ANA_0P3A_EN_CUR_LIM_0_W::new(self, 27) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p3a_dref_0(&mut self) -> ANA_0P3A_DREF_0_W { + ANA_0P3A_DREF_0_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p0_0p3a_ana::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p0_0p3a_ana::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P0_0P3A_ANA_SPEC; +impl crate::RegisterSpec for EXT_LDO_P0_0P3A_ANA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p0_0p3a_ana::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P0_0P3A_ANA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p0_0p3a_ana::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P0_0P3A_ANA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P0_0P3A_ANA to value 0xa000_0000"] +impl crate::Resettable for EXT_LDO_P0_0P3A_ANA_SPEC { + const RESET_VALUE: Self::Ux = 0xa000_0000; +} diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p1a.rs b/esp32p4/src/pmu/ext_ldo_p1_0p1a.rs new file mode 100644 index 0000000000..8bc2a2e4a6 --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p1_0p1a.rs @@ -0,0 +1,217 @@ +#[doc = "Register `EXT_LDO_P1_0P1A` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P1_0P1A` writer"] +pub type W = crate::W; +#[doc = "Field `_0P1A_FORCE_TIEH_SEL_1` reader - need_des"] +pub type _0P1A_FORCE_TIEH_SEL_1_R = crate::BitReader; +#[doc = "Field `_0P1A_FORCE_TIEH_SEL_1` writer - need_des"] +pub type _0P1A_FORCE_TIEH_SEL_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_XPD_1` reader - need_des"] +pub type _0P1A_XPD_1_R = crate::BitReader; +#[doc = "Field `_0P1A_XPD_1` writer - need_des"] +pub type _0P1A_XPD_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_TIEH_SEL_1` reader - need_des"] +pub type _0P1A_TIEH_SEL_1_R = crate::FieldReader; +#[doc = "Field `_0P1A_TIEH_SEL_1` writer - need_des"] +pub type _0P1A_TIEH_SEL_1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `_0P1A_TIEH_POS_EN_1` reader - need_des"] +pub type _0P1A_TIEH_POS_EN_1_R = crate::BitReader; +#[doc = "Field `_0P1A_TIEH_POS_EN_1` writer - need_des"] +pub type _0P1A_TIEH_POS_EN_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_TIEH_NEG_EN_1` reader - need_des"] +pub type _0P1A_TIEH_NEG_EN_1_R = crate::BitReader; +#[doc = "Field `_0P1A_TIEH_NEG_EN_1` writer - need_des"] +pub type _0P1A_TIEH_NEG_EN_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_TIEH_1` reader - need_des"] +pub type _0P1A_TIEH_1_R = crate::BitReader; +#[doc = "Field `_0P1A_TIEH_1` writer - need_des"] +pub type _0P1A_TIEH_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_TARGET1_1` reader - need_des"] +pub type _0P1A_TARGET1_1_R = crate::FieldReader; +#[doc = "Field `_0P1A_TARGET1_1` writer - need_des"] +pub type _0P1A_TARGET1_1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P1A_TARGET0_1` reader - need_des"] +pub type _0P1A_TARGET0_1_R = crate::FieldReader; +#[doc = "Field `_0P1A_TARGET0_1` writer - need_des"] +pub type _0P1A_TARGET0_1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P1A_LDO_CNT_PRESCALER_SEL_1` reader - need_des"] +pub type _0P1A_LDO_CNT_PRESCALER_SEL_1_R = crate::BitReader; +#[doc = "Field `_0P1A_LDO_CNT_PRESCALER_SEL_1` writer - need_des"] +pub type _0P1A_LDO_CNT_PRESCALER_SEL_1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + pub fn _0p1a_force_tieh_sel_1(&self) -> _0P1A_FORCE_TIEH_SEL_1_R { + _0P1A_FORCE_TIEH_SEL_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + pub fn _0p1a_xpd_1(&self) -> _0P1A_XPD_1_R { + _0P1A_XPD_1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + pub fn _0p1a_tieh_sel_1(&self) -> _0P1A_TIEH_SEL_1_R { + _0P1A_TIEH_SEL_1_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn _0p1a_tieh_pos_en_1(&self) -> _0P1A_TIEH_POS_EN_1_R { + _0P1A_TIEH_POS_EN_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn _0p1a_tieh_neg_en_1(&self) -> _0P1A_TIEH_NEG_EN_1_R { + _0P1A_TIEH_NEG_EN_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + pub fn _0p1a_tieh_1(&self) -> _0P1A_TIEH_1_R { + _0P1A_TIEH_1_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + pub fn _0p1a_target1_1(&self) -> _0P1A_TARGET1_1_R { + _0P1A_TARGET1_1_R::new(((self.bits >> 15) & 0xff) as u8) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + pub fn _0p1a_target0_1(&self) -> _0P1A_TARGET0_1_R { + _0P1A_TARGET0_1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn _0p1a_ldo_cnt_prescaler_sel_1(&self) -> _0P1A_LDO_CNT_PRESCALER_SEL_1_R { + _0P1A_LDO_CNT_PRESCALER_SEL_1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P1_0P1A") + .field( + "_0p1a_force_tieh_sel_1", + &format_args!("{}", self._0p1a_force_tieh_sel_1().bit()), + ) + .field("_0p1a_xpd_1", &format_args!("{}", self._0p1a_xpd_1().bit())) + .field( + "_0p1a_tieh_sel_1", + &format_args!("{}", self._0p1a_tieh_sel_1().bits()), + ) + .field( + "_0p1a_tieh_pos_en_1", + &format_args!("{}", self._0p1a_tieh_pos_en_1().bit()), + ) + .field( + "_0p1a_tieh_neg_en_1", + &format_args!("{}", self._0p1a_tieh_neg_en_1().bit()), + ) + .field( + "_0p1a_tieh_1", + &format_args!("{}", self._0p1a_tieh_1().bit()), + ) + .field( + "_0p1a_target1_1", + &format_args!("{}", self._0p1a_target1_1().bits()), + ) + .field( + "_0p1a_target0_1", + &format_args!("{}", self._0p1a_target0_1().bits()), + ) + .field( + "_0p1a_ldo_cnt_prescaler_sel_1", + &format_args!("{}", self._0p1a_ldo_cnt_prescaler_sel_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_force_tieh_sel_1(&mut self) -> _0P1A_FORCE_TIEH_SEL_1_W { + _0P1A_FORCE_TIEH_SEL_1_W::new(self, 7) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_xpd_1(&mut self) -> _0P1A_XPD_1_W { + _0P1A_XPD_1_W::new(self, 8) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_tieh_sel_1(&mut self) -> _0P1A_TIEH_SEL_1_W { + _0P1A_TIEH_SEL_1_W::new(self, 9) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_tieh_pos_en_1(&mut self) -> _0P1A_TIEH_POS_EN_1_W { + _0P1A_TIEH_POS_EN_1_W::new(self, 12) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_tieh_neg_en_1(&mut self) -> _0P1A_TIEH_NEG_EN_1_W { + _0P1A_TIEH_NEG_EN_1_W::new(self, 13) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_tieh_1(&mut self) -> _0P1A_TIEH_1_W { + _0P1A_TIEH_1_W::new(self, 14) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_target1_1(&mut self) -> _0P1A_TARGET1_1_W { + _0P1A_TARGET1_1_W::new(self, 15) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_target0_1(&mut self) -> _0P1A_TARGET0_1_W { + _0P1A_TARGET0_1_W::new(self, 23) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p1a_ldo_cnt_prescaler_sel_1( + &mut self, + ) -> _0P1A_LDO_CNT_PRESCALER_SEL_1_W { + _0P1A_LDO_CNT_PRESCALER_SEL_1_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p1a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p1a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P1_0P1A_SPEC; +impl crate::RegisterSpec for EXT_LDO_P1_0P1A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p1_0p1a::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P1_0P1A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p1_0p1a::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P1_0P1A_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P1_0P1A to value 0x4020_0000"] +impl crate::Resettable for EXT_LDO_P1_0P1A_SPEC { + const RESET_VALUE: Self::Ux = 0x4020_0000; +} diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p1a_ana.rs b/esp32p4/src/pmu/ext_ldo_p1_0p1a_ana.rs new file mode 100644 index 0000000000..6fb33f77d3 --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p1_0p1a_ana.rs @@ -0,0 +1,123 @@ +#[doc = "Register `EXT_LDO_P1_0P1A_ANA` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P1_0P1A_ANA` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_0P1A_MUL_1` reader - need_des"] +pub type ANA_0P1A_MUL_1_R = crate::FieldReader; +#[doc = "Field `ANA_0P1A_MUL_1` writer - need_des"] +pub type ANA_0P1A_MUL_1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ANA_0P1A_EN_VDET_1` reader - need_des"] +pub type ANA_0P1A_EN_VDET_1_R = crate::BitReader; +#[doc = "Field `ANA_0P1A_EN_VDET_1` writer - need_des"] +pub type ANA_0P1A_EN_VDET_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P1A_EN_CUR_LIM_1` reader - need_des"] +pub type ANA_0P1A_EN_CUR_LIM_1_R = crate::BitReader; +#[doc = "Field `ANA_0P1A_EN_CUR_LIM_1` writer - need_des"] +pub type ANA_0P1A_EN_CUR_LIM_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P1A_DREF_1` reader - need_des"] +pub type ANA_0P1A_DREF_1_R = crate::FieldReader; +#[doc = "Field `ANA_0P1A_DREF_1` writer - need_des"] +pub type ANA_0P1A_DREF_1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + pub fn ana_0p1a_mul_1(&self) -> ANA_0P1A_MUL_1_R { + ANA_0P1A_MUL_1_R::new(((self.bits >> 23) & 7) as u8) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn ana_0p1a_en_vdet_1(&self) -> ANA_0P1A_EN_VDET_1_R { + ANA_0P1A_EN_VDET_1_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn ana_0p1a_en_cur_lim_1(&self) -> ANA_0P1A_EN_CUR_LIM_1_R { + ANA_0P1A_EN_CUR_LIM_1_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + pub fn ana_0p1a_dref_1(&self) -> ANA_0P1A_DREF_1_R { + ANA_0P1A_DREF_1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P1_0P1A_ANA") + .field( + "ana_0p1a_mul_1", + &format_args!("{}", self.ana_0p1a_mul_1().bits()), + ) + .field( + "ana_0p1a_en_vdet_1", + &format_args!("{}", self.ana_0p1a_en_vdet_1().bit()), + ) + .field( + "ana_0p1a_en_cur_lim_1", + &format_args!("{}", self.ana_0p1a_en_cur_lim_1().bit()), + ) + .field( + "ana_0p1a_dref_1", + &format_args!("{}", self.ana_0p1a_dref_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p1a_mul_1(&mut self) -> ANA_0P1A_MUL_1_W { + ANA_0P1A_MUL_1_W::new(self, 23) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p1a_en_vdet_1(&mut self) -> ANA_0P1A_EN_VDET_1_W { + ANA_0P1A_EN_VDET_1_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p1a_en_cur_lim_1(&mut self) -> ANA_0P1A_EN_CUR_LIM_1_W { + ANA_0P1A_EN_CUR_LIM_1_W::new(self, 27) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p1a_dref_1(&mut self) -> ANA_0P1A_DREF_1_W { + ANA_0P1A_DREF_1_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p1a_ana::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p1a_ana::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P1_0P1A_ANA_SPEC; +impl crate::RegisterSpec for EXT_LDO_P1_0P1A_ANA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p1_0p1a_ana::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P1_0P1A_ANA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p1_0p1a_ana::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P1_0P1A_ANA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P1_0P1A_ANA to value 0xa000_0000"] +impl crate::Resettable for EXT_LDO_P1_0P1A_ANA_SPEC { + const RESET_VALUE: Self::Ux = 0xa000_0000; +} diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p2a.rs b/esp32p4/src/pmu/ext_ldo_p1_0p2a.rs new file mode 100644 index 0000000000..5bf825b1bd --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p1_0p2a.rs @@ -0,0 +1,217 @@ +#[doc = "Register `EXT_LDO_P1_0P2A` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P1_0P2A` writer"] +pub type W = crate::W; +#[doc = "Field `_0P2A_FORCE_TIEH_SEL_1` reader - need_des"] +pub type _0P2A_FORCE_TIEH_SEL_1_R = crate::BitReader; +#[doc = "Field `_0P2A_FORCE_TIEH_SEL_1` writer - need_des"] +pub type _0P2A_FORCE_TIEH_SEL_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_XPD_1` reader - need_des"] +pub type _0P2A_XPD_1_R = crate::BitReader; +#[doc = "Field `_0P2A_XPD_1` writer - need_des"] +pub type _0P2A_XPD_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_TIEH_SEL_1` reader - need_des"] +pub type _0P2A_TIEH_SEL_1_R = crate::FieldReader; +#[doc = "Field `_0P2A_TIEH_SEL_1` writer - need_des"] +pub type _0P2A_TIEH_SEL_1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `_0P2A_TIEH_POS_EN_1` reader - need_des"] +pub type _0P2A_TIEH_POS_EN_1_R = crate::BitReader; +#[doc = "Field `_0P2A_TIEH_POS_EN_1` writer - need_des"] +pub type _0P2A_TIEH_POS_EN_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_TIEH_NEG_EN_1` reader - need_des"] +pub type _0P2A_TIEH_NEG_EN_1_R = crate::BitReader; +#[doc = "Field `_0P2A_TIEH_NEG_EN_1` writer - need_des"] +pub type _0P2A_TIEH_NEG_EN_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_TIEH_1` reader - need_des"] +pub type _0P2A_TIEH_1_R = crate::BitReader; +#[doc = "Field `_0P2A_TIEH_1` writer - need_des"] +pub type _0P2A_TIEH_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_TARGET1_1` reader - need_des"] +pub type _0P2A_TARGET1_1_R = crate::FieldReader; +#[doc = "Field `_0P2A_TARGET1_1` writer - need_des"] +pub type _0P2A_TARGET1_1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P2A_TARGET0_1` reader - need_des"] +pub type _0P2A_TARGET0_1_R = crate::FieldReader; +#[doc = "Field `_0P2A_TARGET0_1` writer - need_des"] +pub type _0P2A_TARGET0_1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P2A_LDO_CNT_PRESCALER_SEL_1` reader - need_des"] +pub type _0P2A_LDO_CNT_PRESCALER_SEL_1_R = crate::BitReader; +#[doc = "Field `_0P2A_LDO_CNT_PRESCALER_SEL_1` writer - need_des"] +pub type _0P2A_LDO_CNT_PRESCALER_SEL_1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + pub fn _0p2a_force_tieh_sel_1(&self) -> _0P2A_FORCE_TIEH_SEL_1_R { + _0P2A_FORCE_TIEH_SEL_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + pub fn _0p2a_xpd_1(&self) -> _0P2A_XPD_1_R { + _0P2A_XPD_1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + pub fn _0p2a_tieh_sel_1(&self) -> _0P2A_TIEH_SEL_1_R { + _0P2A_TIEH_SEL_1_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn _0p2a_tieh_pos_en_1(&self) -> _0P2A_TIEH_POS_EN_1_R { + _0P2A_TIEH_POS_EN_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn _0p2a_tieh_neg_en_1(&self) -> _0P2A_TIEH_NEG_EN_1_R { + _0P2A_TIEH_NEG_EN_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + pub fn _0p2a_tieh_1(&self) -> _0P2A_TIEH_1_R { + _0P2A_TIEH_1_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + pub fn _0p2a_target1_1(&self) -> _0P2A_TARGET1_1_R { + _0P2A_TARGET1_1_R::new(((self.bits >> 15) & 0xff) as u8) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + pub fn _0p2a_target0_1(&self) -> _0P2A_TARGET0_1_R { + _0P2A_TARGET0_1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn _0p2a_ldo_cnt_prescaler_sel_1(&self) -> _0P2A_LDO_CNT_PRESCALER_SEL_1_R { + _0P2A_LDO_CNT_PRESCALER_SEL_1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P1_0P2A") + .field( + "_0p2a_force_tieh_sel_1", + &format_args!("{}", self._0p2a_force_tieh_sel_1().bit()), + ) + .field("_0p2a_xpd_1", &format_args!("{}", self._0p2a_xpd_1().bit())) + .field( + "_0p2a_tieh_sel_1", + &format_args!("{}", self._0p2a_tieh_sel_1().bits()), + ) + .field( + "_0p2a_tieh_pos_en_1", + &format_args!("{}", self._0p2a_tieh_pos_en_1().bit()), + ) + .field( + "_0p2a_tieh_neg_en_1", + &format_args!("{}", self._0p2a_tieh_neg_en_1().bit()), + ) + .field( + "_0p2a_tieh_1", + &format_args!("{}", self._0p2a_tieh_1().bit()), + ) + .field( + "_0p2a_target1_1", + &format_args!("{}", self._0p2a_target1_1().bits()), + ) + .field( + "_0p2a_target0_1", + &format_args!("{}", self._0p2a_target0_1().bits()), + ) + .field( + "_0p2a_ldo_cnt_prescaler_sel_1", + &format_args!("{}", self._0p2a_ldo_cnt_prescaler_sel_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_force_tieh_sel_1(&mut self) -> _0P2A_FORCE_TIEH_SEL_1_W { + _0P2A_FORCE_TIEH_SEL_1_W::new(self, 7) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_xpd_1(&mut self) -> _0P2A_XPD_1_W { + _0P2A_XPD_1_W::new(self, 8) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_tieh_sel_1(&mut self) -> _0P2A_TIEH_SEL_1_W { + _0P2A_TIEH_SEL_1_W::new(self, 9) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_tieh_pos_en_1(&mut self) -> _0P2A_TIEH_POS_EN_1_W { + _0P2A_TIEH_POS_EN_1_W::new(self, 12) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_tieh_neg_en_1(&mut self) -> _0P2A_TIEH_NEG_EN_1_W { + _0P2A_TIEH_NEG_EN_1_W::new(self, 13) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_tieh_1(&mut self) -> _0P2A_TIEH_1_W { + _0P2A_TIEH_1_W::new(self, 14) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_target1_1(&mut self) -> _0P2A_TARGET1_1_W { + _0P2A_TARGET1_1_W::new(self, 15) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_target0_1(&mut self) -> _0P2A_TARGET0_1_W { + _0P2A_TARGET0_1_W::new(self, 23) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p2a_ldo_cnt_prescaler_sel_1( + &mut self, + ) -> _0P2A_LDO_CNT_PRESCALER_SEL_1_W { + _0P2A_LDO_CNT_PRESCALER_SEL_1_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p2a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p2a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P1_0P2A_SPEC; +impl crate::RegisterSpec for EXT_LDO_P1_0P2A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p1_0p2a::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P1_0P2A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p1_0p2a::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P1_0P2A_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P1_0P2A to value 0x4020_0000"] +impl crate::Resettable for EXT_LDO_P1_0P2A_SPEC { + const RESET_VALUE: Self::Ux = 0x4020_0000; +} diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p2a_ana.rs b/esp32p4/src/pmu/ext_ldo_p1_0p2a_ana.rs new file mode 100644 index 0000000000..14351c1acc --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p1_0p2a_ana.rs @@ -0,0 +1,123 @@ +#[doc = "Register `EXT_LDO_P1_0P2A_ANA` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P1_0P2A_ANA` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_0P2A_MUL_1` reader - need_des"] +pub type ANA_0P2A_MUL_1_R = crate::FieldReader; +#[doc = "Field `ANA_0P2A_MUL_1` writer - need_des"] +pub type ANA_0P2A_MUL_1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ANA_0P2A_EN_VDET_1` reader - need_des"] +pub type ANA_0P2A_EN_VDET_1_R = crate::BitReader; +#[doc = "Field `ANA_0P2A_EN_VDET_1` writer - need_des"] +pub type ANA_0P2A_EN_VDET_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P2A_EN_CUR_LIM_1` reader - need_des"] +pub type ANA_0P2A_EN_CUR_LIM_1_R = crate::BitReader; +#[doc = "Field `ANA_0P2A_EN_CUR_LIM_1` writer - need_des"] +pub type ANA_0P2A_EN_CUR_LIM_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P2A_DREF_1` reader - need_des"] +pub type ANA_0P2A_DREF_1_R = crate::FieldReader; +#[doc = "Field `ANA_0P2A_DREF_1` writer - need_des"] +pub type ANA_0P2A_DREF_1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + pub fn ana_0p2a_mul_1(&self) -> ANA_0P2A_MUL_1_R { + ANA_0P2A_MUL_1_R::new(((self.bits >> 23) & 7) as u8) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn ana_0p2a_en_vdet_1(&self) -> ANA_0P2A_EN_VDET_1_R { + ANA_0P2A_EN_VDET_1_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn ana_0p2a_en_cur_lim_1(&self) -> ANA_0P2A_EN_CUR_LIM_1_R { + ANA_0P2A_EN_CUR_LIM_1_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + pub fn ana_0p2a_dref_1(&self) -> ANA_0P2A_DREF_1_R { + ANA_0P2A_DREF_1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P1_0P2A_ANA") + .field( + "ana_0p2a_mul_1", + &format_args!("{}", self.ana_0p2a_mul_1().bits()), + ) + .field( + "ana_0p2a_en_vdet_1", + &format_args!("{}", self.ana_0p2a_en_vdet_1().bit()), + ) + .field( + "ana_0p2a_en_cur_lim_1", + &format_args!("{}", self.ana_0p2a_en_cur_lim_1().bit()), + ) + .field( + "ana_0p2a_dref_1", + &format_args!("{}", self.ana_0p2a_dref_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p2a_mul_1(&mut self) -> ANA_0P2A_MUL_1_W { + ANA_0P2A_MUL_1_W::new(self, 23) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p2a_en_vdet_1(&mut self) -> ANA_0P2A_EN_VDET_1_W { + ANA_0P2A_EN_VDET_1_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p2a_en_cur_lim_1(&mut self) -> ANA_0P2A_EN_CUR_LIM_1_W { + ANA_0P2A_EN_CUR_LIM_1_W::new(self, 27) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p2a_dref_1(&mut self) -> ANA_0P2A_DREF_1_W { + ANA_0P2A_DREF_1_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p2a_ana::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p2a_ana::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P1_0P2A_ANA_SPEC; +impl crate::RegisterSpec for EXT_LDO_P1_0P2A_ANA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p1_0p2a_ana::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P1_0P2A_ANA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p1_0p2a_ana::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P1_0P2A_ANA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P1_0P2A_ANA to value 0xa000_0000"] +impl crate::Resettable for EXT_LDO_P1_0P2A_ANA_SPEC { + const RESET_VALUE: Self::Ux = 0xa000_0000; +} diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p3a.rs b/esp32p4/src/pmu/ext_ldo_p1_0p3a.rs new file mode 100644 index 0000000000..db47b4de3f --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p1_0p3a.rs @@ -0,0 +1,217 @@ +#[doc = "Register `EXT_LDO_P1_0P3A` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P1_0P3A` writer"] +pub type W = crate::W; +#[doc = "Field `_0P3A_FORCE_TIEH_SEL_1` reader - need_des"] +pub type _0P3A_FORCE_TIEH_SEL_1_R = crate::BitReader; +#[doc = "Field `_0P3A_FORCE_TIEH_SEL_1` writer - need_des"] +pub type _0P3A_FORCE_TIEH_SEL_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_XPD_1` reader - need_des"] +pub type _0P3A_XPD_1_R = crate::BitReader; +#[doc = "Field `_0P3A_XPD_1` writer - need_des"] +pub type _0P3A_XPD_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_TIEH_SEL_1` reader - need_des"] +pub type _0P3A_TIEH_SEL_1_R = crate::FieldReader; +#[doc = "Field `_0P3A_TIEH_SEL_1` writer - need_des"] +pub type _0P3A_TIEH_SEL_1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `_0P3A_TIEH_POS_EN_1` reader - need_des"] +pub type _0P3A_TIEH_POS_EN_1_R = crate::BitReader; +#[doc = "Field `_0P3A_TIEH_POS_EN_1` writer - need_des"] +pub type _0P3A_TIEH_POS_EN_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_TIEH_NEG_EN_1` reader - need_des"] +pub type _0P3A_TIEH_NEG_EN_1_R = crate::BitReader; +#[doc = "Field `_0P3A_TIEH_NEG_EN_1` writer - need_des"] +pub type _0P3A_TIEH_NEG_EN_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_TIEH_1` reader - need_des"] +pub type _0P3A_TIEH_1_R = crate::BitReader; +#[doc = "Field `_0P3A_TIEH_1` writer - need_des"] +pub type _0P3A_TIEH_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_TARGET1_1` reader - need_des"] +pub type _0P3A_TARGET1_1_R = crate::FieldReader; +#[doc = "Field `_0P3A_TARGET1_1` writer - need_des"] +pub type _0P3A_TARGET1_1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P3A_TARGET0_1` reader - need_des"] +pub type _0P3A_TARGET0_1_R = crate::FieldReader; +#[doc = "Field `_0P3A_TARGET0_1` writer - need_des"] +pub type _0P3A_TARGET0_1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `_0P3A_LDO_CNT_PRESCALER_SEL_1` reader - need_des"] +pub type _0P3A_LDO_CNT_PRESCALER_SEL_1_R = crate::BitReader; +#[doc = "Field `_0P3A_LDO_CNT_PRESCALER_SEL_1` writer - need_des"] +pub type _0P3A_LDO_CNT_PRESCALER_SEL_1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + pub fn _0p3a_force_tieh_sel_1(&self) -> _0P3A_FORCE_TIEH_SEL_1_R { + _0P3A_FORCE_TIEH_SEL_1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + pub fn _0p3a_xpd_1(&self) -> _0P3A_XPD_1_R { + _0P3A_XPD_1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + pub fn _0p3a_tieh_sel_1(&self) -> _0P3A_TIEH_SEL_1_R { + _0P3A_TIEH_SEL_1_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn _0p3a_tieh_pos_en_1(&self) -> _0P3A_TIEH_POS_EN_1_R { + _0P3A_TIEH_POS_EN_1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn _0p3a_tieh_neg_en_1(&self) -> _0P3A_TIEH_NEG_EN_1_R { + _0P3A_TIEH_NEG_EN_1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + pub fn _0p3a_tieh_1(&self) -> _0P3A_TIEH_1_R { + _0P3A_TIEH_1_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + pub fn _0p3a_target1_1(&self) -> _0P3A_TARGET1_1_R { + _0P3A_TARGET1_1_R::new(((self.bits >> 15) & 0xff) as u8) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + pub fn _0p3a_target0_1(&self) -> _0P3A_TARGET0_1_R { + _0P3A_TARGET0_1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn _0p3a_ldo_cnt_prescaler_sel_1(&self) -> _0P3A_LDO_CNT_PRESCALER_SEL_1_R { + _0P3A_LDO_CNT_PRESCALER_SEL_1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P1_0P3A") + .field( + "_0p3a_force_tieh_sel_1", + &format_args!("{}", self._0p3a_force_tieh_sel_1().bit()), + ) + .field("_0p3a_xpd_1", &format_args!("{}", self._0p3a_xpd_1().bit())) + .field( + "_0p3a_tieh_sel_1", + &format_args!("{}", self._0p3a_tieh_sel_1().bits()), + ) + .field( + "_0p3a_tieh_pos_en_1", + &format_args!("{}", self._0p3a_tieh_pos_en_1().bit()), + ) + .field( + "_0p3a_tieh_neg_en_1", + &format_args!("{}", self._0p3a_tieh_neg_en_1().bit()), + ) + .field( + "_0p3a_tieh_1", + &format_args!("{}", self._0p3a_tieh_1().bit()), + ) + .field( + "_0p3a_target1_1", + &format_args!("{}", self._0p3a_target1_1().bits()), + ) + .field( + "_0p3a_target0_1", + &format_args!("{}", self._0p3a_target0_1().bits()), + ) + .field( + "_0p3a_ldo_cnt_prescaler_sel_1", + &format_args!("{}", self._0p3a_ldo_cnt_prescaler_sel_1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 7 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_force_tieh_sel_1(&mut self) -> _0P3A_FORCE_TIEH_SEL_1_W { + _0P3A_FORCE_TIEH_SEL_1_W::new(self, 7) + } + #[doc = "Bit 8 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_xpd_1(&mut self) -> _0P3A_XPD_1_W { + _0P3A_XPD_1_W::new(self, 8) + } + #[doc = "Bits 9:11 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_tieh_sel_1(&mut self) -> _0P3A_TIEH_SEL_1_W { + _0P3A_TIEH_SEL_1_W::new(self, 9) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_tieh_pos_en_1(&mut self) -> _0P3A_TIEH_POS_EN_1_W { + _0P3A_TIEH_POS_EN_1_W::new(self, 12) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_tieh_neg_en_1(&mut self) -> _0P3A_TIEH_NEG_EN_1_W { + _0P3A_TIEH_NEG_EN_1_W::new(self, 13) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_tieh_1(&mut self) -> _0P3A_TIEH_1_W { + _0P3A_TIEH_1_W::new(self, 14) + } + #[doc = "Bits 15:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_target1_1(&mut self) -> _0P3A_TARGET1_1_W { + _0P3A_TARGET1_1_W::new(self, 15) + } + #[doc = "Bits 23:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_target0_1(&mut self) -> _0P3A_TARGET0_1_W { + _0P3A_TARGET0_1_W::new(self, 23) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn _0p3a_ldo_cnt_prescaler_sel_1( + &mut self, + ) -> _0P3A_LDO_CNT_PRESCALER_SEL_1_W { + _0P3A_LDO_CNT_PRESCALER_SEL_1_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p3a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p3a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P1_0P3A_SPEC; +impl crate::RegisterSpec for EXT_LDO_P1_0P3A_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p1_0p3a::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P1_0P3A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p1_0p3a::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P1_0P3A_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P1_0P3A to value 0x4020_0000"] +impl crate::Resettable for EXT_LDO_P1_0P3A_SPEC { + const RESET_VALUE: Self::Ux = 0x4020_0000; +} diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p3a_ana.rs b/esp32p4/src/pmu/ext_ldo_p1_0p3a_ana.rs new file mode 100644 index 0000000000..5b4c71b39a --- /dev/null +++ b/esp32p4/src/pmu/ext_ldo_p1_0p3a_ana.rs @@ -0,0 +1,123 @@ +#[doc = "Register `EXT_LDO_P1_0P3A_ANA` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_LDO_P1_0P3A_ANA` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_0P3A_MUL_1` reader - need_des"] +pub type ANA_0P3A_MUL_1_R = crate::FieldReader; +#[doc = "Field `ANA_0P3A_MUL_1` writer - need_des"] +pub type ANA_0P3A_MUL_1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ANA_0P3A_EN_VDET_1` reader - need_des"] +pub type ANA_0P3A_EN_VDET_1_R = crate::BitReader; +#[doc = "Field `ANA_0P3A_EN_VDET_1` writer - need_des"] +pub type ANA_0P3A_EN_VDET_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P3A_EN_CUR_LIM_1` reader - need_des"] +pub type ANA_0P3A_EN_CUR_LIM_1_R = crate::BitReader; +#[doc = "Field `ANA_0P3A_EN_CUR_LIM_1` writer - need_des"] +pub type ANA_0P3A_EN_CUR_LIM_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ANA_0P3A_DREF_1` reader - need_des"] +pub type ANA_0P3A_DREF_1_R = crate::FieldReader; +#[doc = "Field `ANA_0P3A_DREF_1` writer - need_des"] +pub type ANA_0P3A_DREF_1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + pub fn ana_0p3a_mul_1(&self) -> ANA_0P3A_MUL_1_R { + ANA_0P3A_MUL_1_R::new(((self.bits >> 23) & 7) as u8) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn ana_0p3a_en_vdet_1(&self) -> ANA_0P3A_EN_VDET_1_R { + ANA_0P3A_EN_VDET_1_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn ana_0p3a_en_cur_lim_1(&self) -> ANA_0P3A_EN_CUR_LIM_1_R { + ANA_0P3A_EN_CUR_LIM_1_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + pub fn ana_0p3a_dref_1(&self) -> ANA_0P3A_DREF_1_R { + ANA_0P3A_DREF_1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_LDO_P1_0P3A_ANA") + .field( + "ana_0p3a_mul_1", + &format_args!("{}", self.ana_0p3a_mul_1().bits()), + ) + .field( + "ana_0p3a_en_vdet_1", + &format_args!("{}", self.ana_0p3a_en_vdet_1().bit()), + ) + .field( + "ana_0p3a_en_cur_lim_1", + &format_args!("{}", self.ana_0p3a_en_cur_lim_1().bit()), + ) + .field( + "ana_0p3a_dref_1", + &format_args!("{}", self.ana_0p3a_dref_1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p3a_mul_1(&mut self) -> ANA_0P3A_MUL_1_W { + ANA_0P3A_MUL_1_W::new(self, 23) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p3a_en_vdet_1(&mut self) -> ANA_0P3A_EN_VDET_1_W { + ANA_0P3A_EN_VDET_1_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p3a_en_cur_lim_1(&mut self) -> ANA_0P3A_EN_CUR_LIM_1_W { + ANA_0P3A_EN_CUR_LIM_1_W::new(self, 27) + } + #[doc = "Bits 28:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_0p3a_dref_1(&mut self) -> ANA_0P3A_DREF_1_W { + ANA_0P3A_DREF_1_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_ldo_p1_0p3a_ana::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_ldo_p1_0p3a_ana::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_LDO_P1_0P3A_ANA_SPEC; +impl crate::RegisterSpec for EXT_LDO_P1_0P3A_ANA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ldo_p1_0p3a_ana::R`](R) reader structure"] +impl crate::Readable for EXT_LDO_P1_0P3A_ANA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ldo_p1_0p3a_ana::W`](W) writer structure"] +impl crate::Writable for EXT_LDO_P1_0P3A_ANA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_LDO_P1_0P3A_ANA to value 0xa000_0000"] +impl crate::Resettable for EXT_LDO_P1_0P3A_ANA_SPEC { + const RESET_VALUE: Self::Ux = 0xa000_0000; +} diff --git a/esp32p4/src/pmu/ext_wakeup_cntl.rs b/esp32p4/src/pmu/ext_wakeup_cntl.rs new file mode 100644 index 0000000000..e9f8c71c49 --- /dev/null +++ b/esp32p4/src/pmu/ext_wakeup_cntl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `EXT_WAKEUP_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_WAKEUP_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `EXT_WAKEUP_STATUS_CLR` reader - need_des"] +pub type EXT_WAKEUP_STATUS_CLR_R = crate::BitReader; +#[doc = "Field `EXT_WAKEUP_STATUS_CLR` writer - need_des"] +pub type EXT_WAKEUP_STATUS_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXT_WAKEUP_FILTER` reader - need_des"] +pub type EXT_WAKEUP_FILTER_R = crate::BitReader; +#[doc = "Field `EXT_WAKEUP_FILTER` writer - need_des"] +pub type EXT_WAKEUP_FILTER_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn ext_wakeup_status_clr(&self) -> EXT_WAKEUP_STATUS_CLR_R { + EXT_WAKEUP_STATUS_CLR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn ext_wakeup_filter(&self) -> EXT_WAKEUP_FILTER_R { + EXT_WAKEUP_FILTER_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_WAKEUP_CNTL") + .field( + "ext_wakeup_status_clr", + &format_args!("{}", self.ext_wakeup_status_clr().bit()), + ) + .field( + "ext_wakeup_filter", + &format_args!("{}", self.ext_wakeup_filter().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn ext_wakeup_status_clr(&mut self) -> EXT_WAKEUP_STATUS_CLR_W { + EXT_WAKEUP_STATUS_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn ext_wakeup_filter(&mut self) -> EXT_WAKEUP_FILTER_W { + EXT_WAKEUP_FILTER_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_wakeup_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_WAKEUP_CNTL_SPEC; +impl crate::RegisterSpec for EXT_WAKEUP_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_wakeup_cntl::R`](R) reader structure"] +impl crate::Readable for EXT_WAKEUP_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_wakeup_cntl::W`](W) writer structure"] +impl crate::Writable for EXT_WAKEUP_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_WAKEUP_CNTL to value 0"] +impl crate::Resettable for EXT_WAKEUP_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/ext_wakeup_lv.rs b/esp32p4/src/pmu/ext_wakeup_lv.rs new file mode 100644 index 0000000000..d0d32521c1 --- /dev/null +++ b/esp32p4/src/pmu/ext_wakeup_lv.rs @@ -0,0 +1,66 @@ +#[doc = "Register `EXT_WAKEUP_LV` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_WAKEUP_LV` writer"] +pub type W = crate::W; +#[doc = "Field `EXT_WAKEUP_LV` reader - need_des"] +pub type EXT_WAKEUP_LV_R = crate::FieldReader; +#[doc = "Field `EXT_WAKEUP_LV` writer - need_des"] +pub type EXT_WAKEUP_LV_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn ext_wakeup_lv(&self) -> EXT_WAKEUP_LV_R { + EXT_WAKEUP_LV_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_WAKEUP_LV") + .field( + "ext_wakeup_lv", + &format_args!("{}", self.ext_wakeup_lv().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn ext_wakeup_lv(&mut self) -> EXT_WAKEUP_LV_W { + EXT_WAKEUP_LV_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup_lv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_wakeup_lv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_WAKEUP_LV_SPEC; +impl crate::RegisterSpec for EXT_WAKEUP_LV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_wakeup_lv::R`](R) reader structure"] +impl crate::Readable for EXT_WAKEUP_LV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_wakeup_lv::W`](W) writer structure"] +impl crate::Writable for EXT_WAKEUP_LV_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_WAKEUP_LV to value 0"] +impl crate::Resettable for EXT_WAKEUP_LV_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/ext_wakeup_sel.rs b/esp32p4/src/pmu/ext_wakeup_sel.rs new file mode 100644 index 0000000000..1d511c0df8 --- /dev/null +++ b/esp32p4/src/pmu/ext_wakeup_sel.rs @@ -0,0 +1,66 @@ +#[doc = "Register `EXT_WAKEUP_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_WAKEUP_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `EXT_WAKEUP_SEL` reader - need_des"] +pub type EXT_WAKEUP_SEL_R = crate::FieldReader; +#[doc = "Field `EXT_WAKEUP_SEL` writer - need_des"] +pub type EXT_WAKEUP_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn ext_wakeup_sel(&self) -> EXT_WAKEUP_SEL_R { + EXT_WAKEUP_SEL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_WAKEUP_SEL") + .field( + "ext_wakeup_sel", + &format_args!("{}", self.ext_wakeup_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn ext_wakeup_sel(&mut self) -> EXT_WAKEUP_SEL_W { + EXT_WAKEUP_SEL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_wakeup_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_WAKEUP_SEL_SPEC; +impl crate::RegisterSpec for EXT_WAKEUP_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_wakeup_sel::R`](R) reader structure"] +impl crate::Readable for EXT_WAKEUP_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_wakeup_sel::W`](W) writer structure"] +impl crate::Writable for EXT_WAKEUP_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EXT_WAKEUP_SEL to value 0"] +impl crate::Resettable for EXT_WAKEUP_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/ext_wakeup_st.rs b/esp32p4/src/pmu/ext_wakeup_st.rs new file mode 100644 index 0000000000..99348c50d2 --- /dev/null +++ b/esp32p4/src/pmu/ext_wakeup_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `EXT_WAKEUP_ST` reader"] +pub type R = crate::R; +#[doc = "Field `EXT_WAKEUP_STATUS` reader - need_des"] +pub type EXT_WAKEUP_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn ext_wakeup_status(&self) -> EXT_WAKEUP_STATUS_R { + EXT_WAKEUP_STATUS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EXT_WAKEUP_ST") + .field( + "ext_wakeup_status", + &format_args!("{}", self.ext_wakeup_status().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_WAKEUP_ST_SPEC; +impl crate::RegisterSpec for EXT_WAKEUP_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_wakeup_st::R`](R) reader structure"] +impl crate::Readable for EXT_WAKEUP_ST_SPEC {} +#[doc = "`reset()` method sets EXT_WAKEUP_ST to value 0"] +impl crate::Resettable for EXT_WAKEUP_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_active_backup.rs b/esp32p4/src/pmu/hp_active_backup.rs new file mode 100644 index 0000000000..2fcc66c58b --- /dev/null +++ b/esp32p4/src/pmu/hp_active_backup.rs @@ -0,0 +1,278 @@ +#[doc = "Register `HP_ACTIVE_BACKUP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_BACKUP` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE` reader - need_des"] +pub type HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE` writer - need_des"] +pub type HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE` reader - need_des"] +pub type HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_R = crate::FieldReader; +#[doc = "Field `HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE` writer - need_des"] +pub type HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_ACTIVE_RETENTION_MODE` reader - need_des"] +pub type HP_ACTIVE_RETENTION_MODE_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_RETENTION_MODE` writer - need_des"] +pub type HP_ACTIVE_RETENTION_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP2ACTIVE_RETENTION_EN` reader - need_des"] +pub type HP_SLEEP2ACTIVE_RETENTION_EN_R = crate::BitReader; +#[doc = "Field `HP_SLEEP2ACTIVE_RETENTION_EN` writer - need_des"] +pub type HP_SLEEP2ACTIVE_RETENTION_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM2ACTIVE_RETENTION_EN` reader - need_des"] +pub type HP_MODEM2ACTIVE_RETENTION_EN_R = crate::BitReader; +#[doc = "Field `HP_MODEM2ACTIVE_RETENTION_EN` writer - need_des"] +pub type HP_MODEM2ACTIVE_RETENTION_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP2ACTIVE_BACKUP_CLK_SEL` reader - need_des"] +pub type HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP2ACTIVE_BACKUP_CLK_SEL` writer - need_des"] +pub type HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_MODEM2ACTIVE_BACKUP_CLK_SEL` reader - need_des"] +pub type HP_MODEM2ACTIVE_BACKUP_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `HP_MODEM2ACTIVE_BACKUP_CLK_SEL` writer - need_des"] +pub type HP_MODEM2ACTIVE_BACKUP_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_SLEEP2ACTIVE_BACKUP_MODE` reader - need_des"] +pub type HP_SLEEP2ACTIVE_BACKUP_MODE_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP2ACTIVE_BACKUP_MODE` writer - need_des"] +pub type HP_SLEEP2ACTIVE_BACKUP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_MODEM2ACTIVE_BACKUP_MODE` reader - need_des"] +pub type HP_MODEM2ACTIVE_BACKUP_MODE_R = crate::FieldReader; +#[doc = "Field `HP_MODEM2ACTIVE_BACKUP_MODE` writer - need_des"] +pub type HP_MODEM2ACTIVE_BACKUP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_SLEEP2ACTIVE_BACKUP_EN` reader - need_des"] +pub type HP_SLEEP2ACTIVE_BACKUP_EN_R = crate::BitReader; +#[doc = "Field `HP_SLEEP2ACTIVE_BACKUP_EN` writer - need_des"] +pub type HP_SLEEP2ACTIVE_BACKUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM2ACTIVE_BACKUP_EN` reader - need_des"] +pub type HP_MODEM2ACTIVE_BACKUP_EN_R = crate::BitReader; +#[doc = "Field `HP_MODEM2ACTIVE_BACKUP_EN` writer - need_des"] +pub type HP_MODEM2ACTIVE_BACKUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 4:5 - need_des"] + #[inline(always)] + pub fn hp_sleep2active_backup_modem_clk_code(&self) -> HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_R { + HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - need_des"] + #[inline(always)] + pub fn hp_modem2active_backup_modem_clk_code(&self) -> HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_R { + HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + pub fn hp_active_retention_mode(&self) -> HP_ACTIVE_RETENTION_MODE_R { + HP_ACTIVE_RETENTION_MODE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + pub fn hp_sleep2active_retention_en(&self) -> HP_SLEEP2ACTIVE_RETENTION_EN_R { + HP_SLEEP2ACTIVE_RETENTION_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn hp_modem2active_retention_en(&self) -> HP_MODEM2ACTIVE_RETENTION_EN_R { + HP_MODEM2ACTIVE_RETENTION_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 14:15 - need_des"] + #[inline(always)] + pub fn hp_sleep2active_backup_clk_sel(&self) -> HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_R { + HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - need_des"] + #[inline(always)] + pub fn hp_modem2active_backup_clk_sel(&self) -> HP_MODEM2ACTIVE_BACKUP_CLK_SEL_R { + HP_MODEM2ACTIVE_BACKUP_CLK_SEL_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 20:22 - need_des"] + #[inline(always)] + pub fn hp_sleep2active_backup_mode(&self) -> HP_SLEEP2ACTIVE_BACKUP_MODE_R { + HP_SLEEP2ACTIVE_BACKUP_MODE_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + pub fn hp_modem2active_backup_mode(&self) -> HP_MODEM2ACTIVE_BACKUP_MODE_R { + HP_MODEM2ACTIVE_BACKUP_MODE_R::new(((self.bits >> 23) & 7) as u8) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn hp_sleep2active_backup_en(&self) -> HP_SLEEP2ACTIVE_BACKUP_EN_R { + HP_SLEEP2ACTIVE_BACKUP_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn hp_modem2active_backup_en(&self) -> HP_MODEM2ACTIVE_BACKUP_EN_R { + HP_MODEM2ACTIVE_BACKUP_EN_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_BACKUP") + .field( + "hp_sleep2active_backup_modem_clk_code", + &format_args!("{}", self.hp_sleep2active_backup_modem_clk_code().bits()), + ) + .field( + "hp_modem2active_backup_modem_clk_code", + &format_args!("{}", self.hp_modem2active_backup_modem_clk_code().bits()), + ) + .field( + "hp_active_retention_mode", + &format_args!("{}", self.hp_active_retention_mode().bit()), + ) + .field( + "hp_sleep2active_retention_en", + &format_args!("{}", self.hp_sleep2active_retention_en().bit()), + ) + .field( + "hp_modem2active_retention_en", + &format_args!("{}", self.hp_modem2active_retention_en().bit()), + ) + .field( + "hp_sleep2active_backup_clk_sel", + &format_args!("{}", self.hp_sleep2active_backup_clk_sel().bits()), + ) + .field( + "hp_modem2active_backup_clk_sel", + &format_args!("{}", self.hp_modem2active_backup_clk_sel().bits()), + ) + .field( + "hp_sleep2active_backup_mode", + &format_args!("{}", self.hp_sleep2active_backup_mode().bits()), + ) + .field( + "hp_modem2active_backup_mode", + &format_args!("{}", self.hp_modem2active_backup_mode().bits()), + ) + .field( + "hp_sleep2active_backup_en", + &format_args!("{}", self.hp_sleep2active_backup_en().bit()), + ) + .field( + "hp_modem2active_backup_en", + &format_args!("{}", self.hp_modem2active_backup_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 4:5 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep2active_backup_modem_clk_code( + &mut self, + ) -> HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_W { + HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_W::new(self, 4) + } + #[doc = "Bits 6:7 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem2active_backup_modem_clk_code( + &mut self, + ) -> HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_W { + HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_W::new(self, 6) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_retention_mode( + &mut self, + ) -> HP_ACTIVE_RETENTION_MODE_W { + HP_ACTIVE_RETENTION_MODE_W::new(self, 10) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep2active_retention_en( + &mut self, + ) -> HP_SLEEP2ACTIVE_RETENTION_EN_W { + HP_SLEEP2ACTIVE_RETENTION_EN_W::new(self, 11) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem2active_retention_en( + &mut self, + ) -> HP_MODEM2ACTIVE_RETENTION_EN_W { + HP_MODEM2ACTIVE_RETENTION_EN_W::new(self, 12) + } + #[doc = "Bits 14:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep2active_backup_clk_sel( + &mut self, + ) -> HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_W { + HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_W::new(self, 14) + } + #[doc = "Bits 16:17 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem2active_backup_clk_sel( + &mut self, + ) -> HP_MODEM2ACTIVE_BACKUP_CLK_SEL_W { + HP_MODEM2ACTIVE_BACKUP_CLK_SEL_W::new(self, 16) + } + #[doc = "Bits 20:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep2active_backup_mode( + &mut self, + ) -> HP_SLEEP2ACTIVE_BACKUP_MODE_W { + HP_SLEEP2ACTIVE_BACKUP_MODE_W::new(self, 20) + } + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem2active_backup_mode( + &mut self, + ) -> HP_MODEM2ACTIVE_BACKUP_MODE_W { + HP_MODEM2ACTIVE_BACKUP_MODE_W::new(self, 23) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep2active_backup_en( + &mut self, + ) -> HP_SLEEP2ACTIVE_BACKUP_EN_W { + HP_SLEEP2ACTIVE_BACKUP_EN_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem2active_backup_en( + &mut self, + ) -> HP_MODEM2ACTIVE_BACKUP_EN_W { + HP_MODEM2ACTIVE_BACKUP_EN_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_backup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_backup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_BACKUP_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_BACKUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_backup::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_BACKUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_backup::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_BACKUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_BACKUP to value 0"] +impl crate::Resettable for HP_ACTIVE_BACKUP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_active_backup_clk.rs b/esp32p4/src/pmu/hp_active_backup_clk.rs new file mode 100644 index 0000000000..7442b419b2 --- /dev/null +++ b/esp32p4/src/pmu/hp_active_backup_clk.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_ACTIVE_BACKUP_CLK` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_BACKUP_CLK` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ACTIVE_BACKUP_ICG_FUNC_EN` reader - need_des"] +pub type HP_ACTIVE_BACKUP_ICG_FUNC_EN_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_BACKUP_ICG_FUNC_EN` writer - need_des"] +pub type HP_ACTIVE_BACKUP_ICG_FUNC_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn hp_active_backup_icg_func_en(&self) -> HP_ACTIVE_BACKUP_ICG_FUNC_EN_R { + HP_ACTIVE_BACKUP_ICG_FUNC_EN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_BACKUP_CLK") + .field( + "hp_active_backup_icg_func_en", + &format_args!("{}", self.hp_active_backup_icg_func_en().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_backup_icg_func_en( + &mut self, + ) -> HP_ACTIVE_BACKUP_ICG_FUNC_EN_W { + HP_ACTIVE_BACKUP_ICG_FUNC_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_backup_clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_backup_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_BACKUP_CLK_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_BACKUP_CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_backup_clk::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_BACKUP_CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_backup_clk::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_BACKUP_CLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_BACKUP_CLK to value 0"] +impl crate::Resettable for HP_ACTIVE_BACKUP_CLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_active_bias.rs b/esp32p4/src/pmu/hp_active_bias.rs new file mode 100644 index 0000000000..bf91d489c5 --- /dev/null +++ b/esp32p4/src/pmu/hp_active_bias.rs @@ -0,0 +1,158 @@ +#[doc = "Register `HP_ACTIVE_BIAS` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_BIAS` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ACTIVE_DCM_VSET` reader - need_des"] +pub type HP_ACTIVE_DCM_VSET_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_DCM_VSET` writer - need_des"] +pub type HP_ACTIVE_DCM_VSET_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `HP_ACTIVE_DCM_MODE` reader - need_des"] +pub type HP_ACTIVE_DCM_MODE_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_DCM_MODE` writer - need_des"] +pub type HP_ACTIVE_DCM_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_ACTIVE_XPD_BIAS` reader - need_des"] +pub type HP_ACTIVE_XPD_BIAS_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_XPD_BIAS` writer - need_des"] +pub type HP_ACTIVE_XPD_BIAS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_DBG_ATTEN` reader - need_des"] +pub type HP_ACTIVE_DBG_ATTEN_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_DBG_ATTEN` writer - need_des"] +pub type HP_ACTIVE_DBG_ATTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_ACTIVE_PD_CUR` reader - need_des"] +pub type HP_ACTIVE_PD_CUR_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_PD_CUR` writer - need_des"] +pub type HP_ACTIVE_PD_CUR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEP` reader - need_des"] +pub type SLEEP_R = crate::BitReader; +#[doc = "Field `SLEEP` writer - need_des"] +pub type SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + pub fn hp_active_dcm_vset(&self) -> HP_ACTIVE_DCM_VSET_R { + HP_ACTIVE_DCM_VSET_R::new(((self.bits >> 18) & 0x1f) as u8) + } + #[doc = "Bits 23:24 - need_des"] + #[inline(always)] + pub fn hp_active_dcm_mode(&self) -> HP_ACTIVE_DCM_MODE_R { + HP_ACTIVE_DCM_MODE_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn hp_active_xpd_bias(&self) -> HP_ACTIVE_XPD_BIAS_R { + HP_ACTIVE_XPD_BIAS_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 26:29 - need_des"] + #[inline(always)] + pub fn hp_active_dbg_atten(&self) -> HP_ACTIVE_DBG_ATTEN_R { + HP_ACTIVE_DBG_ATTEN_R::new(((self.bits >> 26) & 0x0f) as u8) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn hp_active_pd_cur(&self) -> HP_ACTIVE_PD_CUR_R { + HP_ACTIVE_PD_CUR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn sleep(&self) -> SLEEP_R { + SLEEP_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_BIAS") + .field( + "hp_active_dcm_vset", + &format_args!("{}", self.hp_active_dcm_vset().bits()), + ) + .field( + "hp_active_dcm_mode", + &format_args!("{}", self.hp_active_dcm_mode().bits()), + ) + .field( + "hp_active_xpd_bias", + &format_args!("{}", self.hp_active_xpd_bias().bit()), + ) + .field( + "hp_active_dbg_atten", + &format_args!("{}", self.hp_active_dbg_atten().bits()), + ) + .field( + "hp_active_pd_cur", + &format_args!("{}", self.hp_active_pd_cur().bit()), + ) + .field("sleep", &format_args!("{}", self.sleep().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dcm_vset(&mut self) -> HP_ACTIVE_DCM_VSET_W { + HP_ACTIVE_DCM_VSET_W::new(self, 18) + } + #[doc = "Bits 23:24 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dcm_mode(&mut self) -> HP_ACTIVE_DCM_MODE_W { + HP_ACTIVE_DCM_MODE_W::new(self, 23) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_xpd_bias(&mut self) -> HP_ACTIVE_XPD_BIAS_W { + HP_ACTIVE_XPD_BIAS_W::new(self, 25) + } + #[doc = "Bits 26:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dbg_atten(&mut self) -> HP_ACTIVE_DBG_ATTEN_W { + HP_ACTIVE_DBG_ATTEN_W::new(self, 26) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_pd_cur(&mut self) -> HP_ACTIVE_PD_CUR_W { + HP_ACTIVE_PD_CUR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep(&mut self) -> SLEEP_W { + SLEEP_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_bias::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_bias::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_BIAS_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_BIAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_bias::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_BIAS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_bias::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_BIAS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_BIAS to value 0x0050_0000"] +impl crate::Resettable for HP_ACTIVE_BIAS_SPEC { + const RESET_VALUE: Self::Ux = 0x0050_0000; +} diff --git a/esp32p4/src/pmu/hp_active_dig_power.rs b/esp32p4/src/pmu/hp_active_dig_power.rs new file mode 100644 index 0000000000..7c058b2aa3 --- /dev/null +++ b/esp32p4/src/pmu/hp_active_dig_power.rs @@ -0,0 +1,148 @@ +#[doc = "Register `HP_ACTIVE_DIG_POWER` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_DIG_POWER` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ACTIVE_DCDC_SWITCH_PD_EN` reader - need_des"] +pub type HP_ACTIVE_DCDC_SWITCH_PD_EN_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_DCDC_SWITCH_PD_EN` writer - need_des"] +pub type HP_ACTIVE_DCDC_SWITCH_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_HP_MEM_DSLP` reader - need_des"] +pub type HP_ACTIVE_HP_MEM_DSLP_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_HP_MEM_DSLP` writer - need_des"] +pub type HP_ACTIVE_HP_MEM_DSLP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_PD_HP_MEM_PD_EN` reader - need_des"] +pub type HP_ACTIVE_PD_HP_MEM_PD_EN_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_PD_HP_MEM_PD_EN` writer - need_des"] +pub type HP_ACTIVE_PD_HP_MEM_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_PD_CNNT_PD_EN` reader - need_des"] +pub type HP_ACTIVE_PD_CNNT_PD_EN_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_PD_CNNT_PD_EN` writer - need_des"] +pub type HP_ACTIVE_PD_CNNT_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_PD_TOP_PD_EN` reader - need_des"] +pub type HP_ACTIVE_PD_TOP_PD_EN_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_PD_TOP_PD_EN` writer - need_des"] +pub type HP_ACTIVE_PD_TOP_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + pub fn hp_active_dcdc_switch_pd_en(&self) -> HP_ACTIVE_DCDC_SWITCH_PD_EN_R { + HP_ACTIVE_DCDC_SWITCH_PD_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + pub fn hp_active_hp_mem_dslp(&self) -> HP_ACTIVE_HP_MEM_DSLP_R { + HP_ACTIVE_HP_MEM_DSLP_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - need_des"] + #[inline(always)] + pub fn hp_active_pd_hp_mem_pd_en(&self) -> HP_ACTIVE_PD_HP_MEM_PD_EN_R { + HP_ACTIVE_PD_HP_MEM_PD_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn hp_active_pd_cnnt_pd_en(&self) -> HP_ACTIVE_PD_CNNT_PD_EN_R { + HP_ACTIVE_PD_CNNT_PD_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_active_pd_top_pd_en(&self) -> HP_ACTIVE_PD_TOP_PD_EN_R { + HP_ACTIVE_PD_TOP_PD_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_DIG_POWER") + .field( + "hp_active_dcdc_switch_pd_en", + &format_args!("{}", self.hp_active_dcdc_switch_pd_en().bit()), + ) + .field( + "hp_active_hp_mem_dslp", + &format_args!("{}", self.hp_active_hp_mem_dslp().bit()), + ) + .field( + "hp_active_pd_hp_mem_pd_en", + &format_args!("{}", self.hp_active_pd_hp_mem_pd_en().bit()), + ) + .field( + "hp_active_pd_cnnt_pd_en", + &format_args!("{}", self.hp_active_pd_cnnt_pd_en().bit()), + ) + .field( + "hp_active_pd_top_pd_en", + &format_args!("{}", self.hp_active_pd_top_pd_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dcdc_switch_pd_en( + &mut self, + ) -> HP_ACTIVE_DCDC_SWITCH_PD_EN_W { + HP_ACTIVE_DCDC_SWITCH_PD_EN_W::new(self, 21) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_hp_mem_dslp(&mut self) -> HP_ACTIVE_HP_MEM_DSLP_W { + HP_ACTIVE_HP_MEM_DSLP_W::new(self, 22) + } + #[doc = "Bit 23 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_pd_hp_mem_pd_en( + &mut self, + ) -> HP_ACTIVE_PD_HP_MEM_PD_EN_W { + HP_ACTIVE_PD_HP_MEM_PD_EN_W::new(self, 23) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_pd_cnnt_pd_en( + &mut self, + ) -> HP_ACTIVE_PD_CNNT_PD_EN_W { + HP_ACTIVE_PD_CNNT_PD_EN_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_pd_top_pd_en(&mut self) -> HP_ACTIVE_PD_TOP_PD_EN_W { + HP_ACTIVE_PD_TOP_PD_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_dig_power::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_dig_power::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_DIG_POWER_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_DIG_POWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_dig_power::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_DIG_POWER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_dig_power::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_DIG_POWER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_DIG_POWER to value 0"] +impl crate::Resettable for HP_ACTIVE_DIG_POWER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_active_hp_ck_power.rs b/esp32p4/src/pmu/hp_active_hp_ck_power.rs new file mode 100644 index 0000000000..bccbac389c --- /dev/null +++ b/esp32p4/src/pmu/hp_active_hp_ck_power.rs @@ -0,0 +1,125 @@ +#[doc = "Register `HP_ACTIVE_HP_CK_POWER` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_HP_CK_POWER` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ACTIVE_I2C_ISO_EN` reader - need_des"] +pub type HP_ACTIVE_I2C_ISO_EN_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_I2C_ISO_EN` writer - need_des"] +pub type HP_ACTIVE_I2C_ISO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_I2C_RETENTION` reader - need_des"] +pub type HP_ACTIVE_I2C_RETENTION_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_I2C_RETENTION` writer - need_des"] +pub type HP_ACTIVE_I2C_RETENTION_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_XPD_PLL_I2C` reader - need_des"] +pub type HP_ACTIVE_XPD_PLL_I2C_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_XPD_PLL_I2C` writer - need_des"] +pub type HP_ACTIVE_XPD_PLL_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_ACTIVE_XPD_PLL` reader - need_des"] +pub type HP_ACTIVE_XPD_PLL_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_XPD_PLL` writer - need_des"] +pub type HP_ACTIVE_XPD_PLL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + pub fn hp_active_i2c_iso_en(&self) -> HP_ACTIVE_I2C_ISO_EN_R { + HP_ACTIVE_I2C_ISO_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + pub fn hp_active_i2c_retention(&self) -> HP_ACTIVE_I2C_RETENTION_R { + HP_ACTIVE_I2C_RETENTION_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + pub fn hp_active_xpd_pll_i2c(&self) -> HP_ACTIVE_XPD_PLL_I2C_R { + HP_ACTIVE_XPD_PLL_I2C_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bits 27:30 - need_des"] + #[inline(always)] + pub fn hp_active_xpd_pll(&self) -> HP_ACTIVE_XPD_PLL_R { + HP_ACTIVE_XPD_PLL_R::new(((self.bits >> 27) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_HP_CK_POWER") + .field( + "hp_active_i2c_iso_en", + &format_args!("{}", self.hp_active_i2c_iso_en().bit()), + ) + .field( + "hp_active_i2c_retention", + &format_args!("{}", self.hp_active_i2c_retention().bit()), + ) + .field( + "hp_active_xpd_pll_i2c", + &format_args!("{}", self.hp_active_xpd_pll_i2c().bits()), + ) + .field( + "hp_active_xpd_pll", + &format_args!("{}", self.hp_active_xpd_pll().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_i2c_iso_en(&mut self) -> HP_ACTIVE_I2C_ISO_EN_W { + HP_ACTIVE_I2C_ISO_EN_W::new(self, 21) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_i2c_retention( + &mut self, + ) -> HP_ACTIVE_I2C_RETENTION_W { + HP_ACTIVE_I2C_RETENTION_W::new(self, 22) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_xpd_pll_i2c(&mut self) -> HP_ACTIVE_XPD_PLL_I2C_W { + HP_ACTIVE_XPD_PLL_I2C_W::new(self, 23) + } + #[doc = "Bits 27:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_xpd_pll(&mut self) -> HP_ACTIVE_XPD_PLL_W { + HP_ACTIVE_XPD_PLL_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_hp_ck_power::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_hp_ck_power::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_HP_CK_POWER_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_HP_CK_POWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_hp_ck_power::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_HP_CK_POWER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_hp_ck_power::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_HP_CK_POWER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_HP_CK_POWER to value 0"] +impl crate::Resettable for HP_ACTIVE_HP_CK_POWER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_active_hp_regulator0.rs b/esp32p4/src/pmu/hp_active_hp_regulator0.rs new file mode 100644 index 0000000000..a005a1e7c9 --- /dev/null +++ b/esp32p4/src/pmu/hp_active_hp_regulator0.rs @@ -0,0 +1,226 @@ +#[doc = "Register `HP_ACTIVE_HP_REGULATOR0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_HP_REGULATOR0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_DBIAS_VOL` reader - need_des"] +pub type LP_DBIAS_VOL_R = crate::FieldReader; +#[doc = "Field `HP_DBIAS_VOL` reader - need_des"] +pub type HP_DBIAS_VOL_R = crate::FieldReader; +#[doc = "Field `DIG_REGULATOR0_DBIAS_SEL` reader - need_des"] +pub type DIG_REGULATOR0_DBIAS_SEL_R = crate::BitReader; +#[doc = "Field `DIG_REGULATOR0_DBIAS_SEL` writer - need_des"] +pub type DIG_REGULATOR0_DBIAS_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIG_DBIAS_INIT` writer - need_des"] +pub type DIG_DBIAS_INIT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD` reader - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD` writer - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD` reader - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD` writer - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_XPD` reader - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_XPD_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_XPD` writer - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS` reader - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS` writer - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS` reader - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS` writer - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_DBIAS` reader - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_DBIAS_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_DBIAS` writer - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 4:8 - need_des"] + #[inline(always)] + pub fn lp_dbias_vol(&self) -> LP_DBIAS_VOL_R { + LP_DBIAS_VOL_R::new(((self.bits >> 4) & 0x1f) as u8) + } + #[doc = "Bits 9:13 - need_des"] + #[inline(always)] + pub fn hp_dbias_vol(&self) -> HP_DBIAS_VOL_R { + HP_DBIAS_VOL_R::new(((self.bits >> 9) & 0x1f) as u8) + } + #[doc = "Bit 14 - need_des"] + #[inline(always)] + pub fn dig_regulator0_dbias_sel(&self) -> DIG_REGULATOR0_DBIAS_SEL_R { + DIG_REGULATOR0_DBIAS_SEL_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 16 - need_des"] + #[inline(always)] + pub fn hp_active_hp_regulator_slp_mem_xpd(&self) -> HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_R { + HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - need_des"] + #[inline(always)] + pub fn hp_active_hp_regulator_slp_logic_xpd(&self) -> HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_R { + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - need_des"] + #[inline(always)] + pub fn hp_active_hp_regulator_xpd(&self) -> HP_ACTIVE_HP_REGULATOR_XPD_R { + HP_ACTIVE_HP_REGULATOR_XPD_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn hp_active_hp_regulator_slp_mem_dbias(&self) -> HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_R { + HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_R::new(((self.bits >> 19) & 0x0f) as u8) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + pub fn hp_active_hp_regulator_slp_logic_dbias( + &self, + ) -> HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_R { + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + pub fn hp_active_hp_regulator_dbias(&self) -> HP_ACTIVE_HP_REGULATOR_DBIAS_R { + HP_ACTIVE_HP_REGULATOR_DBIAS_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_HP_REGULATOR0") + .field( + "lp_dbias_vol", + &format_args!("{}", self.lp_dbias_vol().bits()), + ) + .field( + "hp_dbias_vol", + &format_args!("{}", self.hp_dbias_vol().bits()), + ) + .field( + "dig_regulator0_dbias_sel", + &format_args!("{}", self.dig_regulator0_dbias_sel().bit()), + ) + .field( + "hp_active_hp_regulator_slp_mem_xpd", + &format_args!("{}", self.hp_active_hp_regulator_slp_mem_xpd().bit()), + ) + .field( + "hp_active_hp_regulator_slp_logic_xpd", + &format_args!("{}", self.hp_active_hp_regulator_slp_logic_xpd().bit()), + ) + .field( + "hp_active_hp_regulator_xpd", + &format_args!("{}", self.hp_active_hp_regulator_xpd().bit()), + ) + .field( + "hp_active_hp_regulator_slp_mem_dbias", + &format_args!("{}", self.hp_active_hp_regulator_slp_mem_dbias().bits()), + ) + .field( + "hp_active_hp_regulator_slp_logic_dbias", + &format_args!("{}", self.hp_active_hp_regulator_slp_logic_dbias().bits()), + ) + .field( + "hp_active_hp_regulator_dbias", + &format_args!("{}", self.hp_active_hp_regulator_dbias().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 14 - need_des"] + #[inline(always)] + #[must_use] + pub fn dig_regulator0_dbias_sel( + &mut self, + ) -> DIG_REGULATOR0_DBIAS_SEL_W { + DIG_REGULATOR0_DBIAS_SEL_W::new(self, 14) + } + #[doc = "Bit 15 - need_des"] + #[inline(always)] + #[must_use] + pub fn dig_dbias_init(&mut self) -> DIG_DBIAS_INIT_W { + DIG_DBIAS_INIT_W::new(self, 15) + } + #[doc = "Bit 16 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_hp_regulator_slp_mem_xpd( + &mut self, + ) -> HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_W { + HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_W::new(self, 16) + } + #[doc = "Bit 17 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_hp_regulator_slp_logic_xpd( + &mut self, + ) -> HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_W { + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_W::new(self, 17) + } + #[doc = "Bit 18 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_hp_regulator_xpd( + &mut self, + ) -> HP_ACTIVE_HP_REGULATOR_XPD_W { + HP_ACTIVE_HP_REGULATOR_XPD_W::new(self, 18) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_hp_regulator_slp_mem_dbias( + &mut self, + ) -> HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_W { + HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_W::new(self, 19) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_hp_regulator_slp_logic_dbias( + &mut self, + ) -> HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_W { + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_W::new(self, 23) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_hp_regulator_dbias( + &mut self, + ) -> HP_ACTIVE_HP_REGULATOR_DBIAS_W { + HP_ACTIVE_HP_REGULATOR_DBIAS_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_hp_regulator0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_hp_regulator0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_HP_REGULATOR0_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_HP_REGULATOR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_hp_regulator0::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_HP_REGULATOR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_hp_regulator0::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_HP_REGULATOR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_HP_REGULATOR0 to value 0xc667_7180"] +impl crate::Resettable for HP_ACTIVE_HP_REGULATOR0_SPEC { + const RESET_VALUE: Self::Ux = 0xc667_7180; +} diff --git a/esp32p4/src/pmu/hp_active_hp_regulator1.rs b/esp32p4/src/pmu/hp_active_hp_regulator1.rs new file mode 100644 index 0000000000..864605b90d --- /dev/null +++ b/esp32p4/src/pmu/hp_active_hp_regulator1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_ACTIVE_HP_REGULATOR1` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_HP_REGULATOR1` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_DRV_B` reader - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_DRV_B_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_HP_REGULATOR_DRV_B` writer - need_des"] +pub type HP_ACTIVE_HP_REGULATOR_DRV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 26:31 - need_des"] + #[inline(always)] + pub fn hp_active_hp_regulator_drv_b(&self) -> HP_ACTIVE_HP_REGULATOR_DRV_B_R { + HP_ACTIVE_HP_REGULATOR_DRV_B_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_HP_REGULATOR1") + .field( + "hp_active_hp_regulator_drv_b", + &format_args!("{}", self.hp_active_hp_regulator_drv_b().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 26:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_hp_regulator_drv_b( + &mut self, + ) -> HP_ACTIVE_HP_REGULATOR_DRV_B_W { + HP_ACTIVE_HP_REGULATOR_DRV_B_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_hp_regulator1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_hp_regulator1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_HP_REGULATOR1_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_HP_REGULATOR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_hp_regulator1::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_HP_REGULATOR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_hp_regulator1::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_HP_REGULATOR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_HP_REGULATOR1 to value 0"] +impl crate::Resettable for HP_ACTIVE_HP_REGULATOR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_active_hp_sys_cntl.rs b/esp32p4/src/pmu/hp_active_hp_sys_cntl.rs new file mode 100644 index 0000000000..a14b140145 --- /dev/null +++ b/esp32p4/src/pmu/hp_active_hp_sys_cntl.rs @@ -0,0 +1,194 @@ +#[doc = "Register `HP_ACTIVE_HP_SYS_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_HP_SYS_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ACTIVE_HP_POWER_DET_BYPASS` reader - need_des"] +pub type HP_ACTIVE_HP_POWER_DET_BYPASS_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_HP_POWER_DET_BYPASS` writer - need_des"] +pub type HP_ACTIVE_HP_POWER_DET_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_UART_WAKEUP_EN` reader - need_des"] +pub type HP_ACTIVE_UART_WAKEUP_EN_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_UART_WAKEUP_EN` writer - need_des"] +pub type HP_ACTIVE_UART_WAKEUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_LP_PAD_HOLD_ALL` reader - need_des"] +pub type HP_ACTIVE_LP_PAD_HOLD_ALL_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_LP_PAD_HOLD_ALL` writer - need_des"] +pub type HP_ACTIVE_LP_PAD_HOLD_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_HP_PAD_HOLD_ALL` reader - need_des"] +pub type HP_ACTIVE_HP_PAD_HOLD_ALL_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_HP_PAD_HOLD_ALL` writer - need_des"] +pub type HP_ACTIVE_HP_PAD_HOLD_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_DIG_PAD_SLP_SEL` reader - need_des"] +pub type HP_ACTIVE_DIG_PAD_SLP_SEL_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_DIG_PAD_SLP_SEL` writer - need_des"] +pub type HP_ACTIVE_DIG_PAD_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_DIG_PAUSE_WDT` reader - need_des"] +pub type HP_ACTIVE_DIG_PAUSE_WDT_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_DIG_PAUSE_WDT` writer - need_des"] +pub type HP_ACTIVE_DIG_PAUSE_WDT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_DIG_CPU_STALL` reader - need_des"] +pub type HP_ACTIVE_DIG_CPU_STALL_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_DIG_CPU_STALL` writer - need_des"] +pub type HP_ACTIVE_DIG_CPU_STALL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 23 - need_des"] + #[inline(always)] + pub fn hp_active_hp_power_det_bypass(&self) -> HP_ACTIVE_HP_POWER_DET_BYPASS_R { + HP_ACTIVE_HP_POWER_DET_BYPASS_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + pub fn hp_active_uart_wakeup_en(&self) -> HP_ACTIVE_UART_WAKEUP_EN_R { + HP_ACTIVE_UART_WAKEUP_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn hp_active_lp_pad_hold_all(&self) -> HP_ACTIVE_LP_PAD_HOLD_ALL_R { + HP_ACTIVE_LP_PAD_HOLD_ALL_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn hp_active_hp_pad_hold_all(&self) -> HP_ACTIVE_HP_PAD_HOLD_ALL_R { + HP_ACTIVE_HP_PAD_HOLD_ALL_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn hp_active_dig_pad_slp_sel(&self) -> HP_ACTIVE_DIG_PAD_SLP_SEL_R { + HP_ACTIVE_DIG_PAD_SLP_SEL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn hp_active_dig_pause_wdt(&self) -> HP_ACTIVE_DIG_PAUSE_WDT_R { + HP_ACTIVE_DIG_PAUSE_WDT_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn hp_active_dig_cpu_stall(&self) -> HP_ACTIVE_DIG_CPU_STALL_R { + HP_ACTIVE_DIG_CPU_STALL_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_HP_SYS_CNTL") + .field( + "hp_active_hp_power_det_bypass", + &format_args!("{}", self.hp_active_hp_power_det_bypass().bit()), + ) + .field( + "hp_active_uart_wakeup_en", + &format_args!("{}", self.hp_active_uart_wakeup_en().bit()), + ) + .field( + "hp_active_lp_pad_hold_all", + &format_args!("{}", self.hp_active_lp_pad_hold_all().bit()), + ) + .field( + "hp_active_hp_pad_hold_all", + &format_args!("{}", self.hp_active_hp_pad_hold_all().bit()), + ) + .field( + "hp_active_dig_pad_slp_sel", + &format_args!("{}", self.hp_active_dig_pad_slp_sel().bit()), + ) + .field( + "hp_active_dig_pause_wdt", + &format_args!("{}", self.hp_active_dig_pause_wdt().bit()), + ) + .field( + "hp_active_dig_cpu_stall", + &format_args!("{}", self.hp_active_dig_cpu_stall().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 23 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_hp_power_det_bypass( + &mut self, + ) -> HP_ACTIVE_HP_POWER_DET_BYPASS_W { + HP_ACTIVE_HP_POWER_DET_BYPASS_W::new(self, 23) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_uart_wakeup_en( + &mut self, + ) -> HP_ACTIVE_UART_WAKEUP_EN_W { + HP_ACTIVE_UART_WAKEUP_EN_W::new(self, 24) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_lp_pad_hold_all( + &mut self, + ) -> HP_ACTIVE_LP_PAD_HOLD_ALL_W { + HP_ACTIVE_LP_PAD_HOLD_ALL_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_hp_pad_hold_all( + &mut self, + ) -> HP_ACTIVE_HP_PAD_HOLD_ALL_W { + HP_ACTIVE_HP_PAD_HOLD_ALL_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dig_pad_slp_sel( + &mut self, + ) -> HP_ACTIVE_DIG_PAD_SLP_SEL_W { + HP_ACTIVE_DIG_PAD_SLP_SEL_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dig_pause_wdt( + &mut self, + ) -> HP_ACTIVE_DIG_PAUSE_WDT_W { + HP_ACTIVE_DIG_PAUSE_WDT_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dig_cpu_stall( + &mut self, + ) -> HP_ACTIVE_DIG_CPU_STALL_W { + HP_ACTIVE_DIG_CPU_STALL_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_hp_sys_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_hp_sys_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_HP_SYS_CNTL_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_HP_SYS_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_hp_sys_cntl::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_HP_SYS_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_hp_sys_cntl::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_HP_SYS_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_HP_SYS_CNTL to value 0"] +impl crate::Resettable for HP_ACTIVE_HP_SYS_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_active_icg_hp_apb.rs b/esp32p4/src/pmu/hp_active_icg_hp_apb.rs new file mode 100644 index 0000000000..0cba3695e4 --- /dev/null +++ b/esp32p4/src/pmu/hp_active_icg_hp_apb.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_ACTIVE_ICG_HP_APB` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_ICG_HP_APB` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ACTIVE_DIG_ICG_APB_EN` reader - need_des"] +pub type HP_ACTIVE_DIG_ICG_APB_EN_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_DIG_ICG_APB_EN` writer - need_des"] +pub type HP_ACTIVE_DIG_ICG_APB_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn hp_active_dig_icg_apb_en(&self) -> HP_ACTIVE_DIG_ICG_APB_EN_R { + HP_ACTIVE_DIG_ICG_APB_EN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_ICG_HP_APB") + .field( + "hp_active_dig_icg_apb_en", + &format_args!("{}", self.hp_active_dig_icg_apb_en().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dig_icg_apb_en( + &mut self, + ) -> HP_ACTIVE_DIG_ICG_APB_EN_W { + HP_ACTIVE_DIG_ICG_APB_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_icg_hp_apb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_icg_hp_apb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_ICG_HP_APB_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_ICG_HP_APB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_icg_hp_apb::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_ICG_HP_APB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_icg_hp_apb::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_ICG_HP_APB_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_ICG_HP_APB to value 0xffff_ffff"] +impl crate::Resettable for HP_ACTIVE_ICG_HP_APB_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/pmu/hp_active_icg_hp_func.rs b/esp32p4/src/pmu/hp_active_icg_hp_func.rs new file mode 100644 index 0000000000..eaf4917af3 --- /dev/null +++ b/esp32p4/src/pmu/hp_active_icg_hp_func.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_ACTIVE_ICG_HP_FUNC` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_ICG_HP_FUNC` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ACTIVE_DIG_ICG_FUNC_EN` reader - need_des"] +pub type HP_ACTIVE_DIG_ICG_FUNC_EN_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_DIG_ICG_FUNC_EN` writer - need_des"] +pub type HP_ACTIVE_DIG_ICG_FUNC_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn hp_active_dig_icg_func_en(&self) -> HP_ACTIVE_DIG_ICG_FUNC_EN_R { + HP_ACTIVE_DIG_ICG_FUNC_EN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_ICG_HP_FUNC") + .field( + "hp_active_dig_icg_func_en", + &format_args!("{}", self.hp_active_dig_icg_func_en().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dig_icg_func_en( + &mut self, + ) -> HP_ACTIVE_DIG_ICG_FUNC_EN_W { + HP_ACTIVE_DIG_ICG_FUNC_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_icg_hp_func::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_icg_hp_func::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_ICG_HP_FUNC_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_ICG_HP_FUNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_icg_hp_func::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_ICG_HP_FUNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_icg_hp_func::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_ICG_HP_FUNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_ICG_HP_FUNC to value 0xffff_ffff"] +impl crate::Resettable for HP_ACTIVE_ICG_HP_FUNC_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/pmu/hp_active_icg_modem.rs b/esp32p4/src/pmu/hp_active_icg_modem.rs new file mode 100644 index 0000000000..54d51f6bbf --- /dev/null +++ b/esp32p4/src/pmu/hp_active_icg_modem.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_ACTIVE_ICG_MODEM` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_ICG_MODEM` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ACTIVE_DIG_ICG_MODEM_CODE` reader - need_des"] +pub type HP_ACTIVE_DIG_ICG_MODEM_CODE_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_DIG_ICG_MODEM_CODE` writer - need_des"] +pub type HP_ACTIVE_DIG_ICG_MODEM_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + pub fn hp_active_dig_icg_modem_code(&self) -> HP_ACTIVE_DIG_ICG_MODEM_CODE_R { + HP_ACTIVE_DIG_ICG_MODEM_CODE_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_ICG_MODEM") + .field( + "hp_active_dig_icg_modem_code", + &format_args!("{}", self.hp_active_dig_icg_modem_code().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dig_icg_modem_code( + &mut self, + ) -> HP_ACTIVE_DIG_ICG_MODEM_CODE_W { + HP_ACTIVE_DIG_ICG_MODEM_CODE_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_icg_modem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_icg_modem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_ICG_MODEM_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_ICG_MODEM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_icg_modem::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_ICG_MODEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_icg_modem::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_ICG_MODEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_ICG_MODEM to value 0"] +impl crate::Resettable for HP_ACTIVE_ICG_MODEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_active_sysclk.rs b/esp32p4/src/pmu/hp_active_sysclk.rs new file mode 100644 index 0000000000..154f9e9f59 --- /dev/null +++ b/esp32p4/src/pmu/hp_active_sysclk.rs @@ -0,0 +1,150 @@ +#[doc = "Register `HP_ACTIVE_SYSCLK` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_SYSCLK` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ACTIVE_DIG_SYS_CLK_NO_DIV` reader - need_des"] +pub type HP_ACTIVE_DIG_SYS_CLK_NO_DIV_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_DIG_SYS_CLK_NO_DIV` writer - need_des"] +pub type HP_ACTIVE_DIG_SYS_CLK_NO_DIV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_ICG_SYS_CLOCK_EN` reader - need_des"] +pub type HP_ACTIVE_ICG_SYS_CLOCK_EN_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_ICG_SYS_CLOCK_EN` writer - need_des"] +pub type HP_ACTIVE_ICG_SYS_CLOCK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_SYS_CLK_SLP_SEL` reader - need_des"] +pub type HP_ACTIVE_SYS_CLK_SLP_SEL_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_SYS_CLK_SLP_SEL` writer - need_des"] +pub type HP_ACTIVE_SYS_CLK_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_ICG_SLP_SEL` reader - need_des"] +pub type HP_ACTIVE_ICG_SLP_SEL_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_ICG_SLP_SEL` writer - need_des"] +pub type HP_ACTIVE_ICG_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE_DIG_SYS_CLK_SEL` reader - need_des"] +pub type HP_ACTIVE_DIG_SYS_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE_DIG_SYS_CLK_SEL` writer - need_des"] +pub type HP_ACTIVE_DIG_SYS_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn hp_active_dig_sys_clk_no_div(&self) -> HP_ACTIVE_DIG_SYS_CLK_NO_DIV_R { + HP_ACTIVE_DIG_SYS_CLK_NO_DIV_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn hp_active_icg_sys_clock_en(&self) -> HP_ACTIVE_ICG_SYS_CLOCK_EN_R { + HP_ACTIVE_ICG_SYS_CLOCK_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn hp_active_sys_clk_slp_sel(&self) -> HP_ACTIVE_SYS_CLK_SLP_SEL_R { + HP_ACTIVE_SYS_CLK_SLP_SEL_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn hp_active_icg_slp_sel(&self) -> HP_ACTIVE_ICG_SLP_SEL_R { + HP_ACTIVE_ICG_SLP_SEL_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + pub fn hp_active_dig_sys_clk_sel(&self) -> HP_ACTIVE_DIG_SYS_CLK_SEL_R { + HP_ACTIVE_DIG_SYS_CLK_SEL_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_SYSCLK") + .field( + "hp_active_dig_sys_clk_no_div", + &format_args!("{}", self.hp_active_dig_sys_clk_no_div().bit()), + ) + .field( + "hp_active_icg_sys_clock_en", + &format_args!("{}", self.hp_active_icg_sys_clock_en().bit()), + ) + .field( + "hp_active_sys_clk_slp_sel", + &format_args!("{}", self.hp_active_sys_clk_slp_sel().bit()), + ) + .field( + "hp_active_icg_slp_sel", + &format_args!("{}", self.hp_active_icg_slp_sel().bit()), + ) + .field( + "hp_active_dig_sys_clk_sel", + &format_args!("{}", self.hp_active_dig_sys_clk_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dig_sys_clk_no_div( + &mut self, + ) -> HP_ACTIVE_DIG_SYS_CLK_NO_DIV_W { + HP_ACTIVE_DIG_SYS_CLK_NO_DIV_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_icg_sys_clock_en( + &mut self, + ) -> HP_ACTIVE_ICG_SYS_CLOCK_EN_W { + HP_ACTIVE_ICG_SYS_CLOCK_EN_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_sys_clk_slp_sel( + &mut self, + ) -> HP_ACTIVE_SYS_CLK_SLP_SEL_W { + HP_ACTIVE_SYS_CLK_SLP_SEL_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_icg_slp_sel(&mut self) -> HP_ACTIVE_ICG_SLP_SEL_W { + HP_ACTIVE_ICG_SLP_SEL_W::new(self, 29) + } + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_dig_sys_clk_sel( + &mut self, + ) -> HP_ACTIVE_DIG_SYS_CLK_SEL_W { + HP_ACTIVE_DIG_SYS_CLK_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_sysclk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_sysclk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_SYSCLK_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_SYSCLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_sysclk::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_SYSCLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_sysclk::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_SYSCLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_SYSCLK to value 0"] +impl crate::Resettable for HP_ACTIVE_SYSCLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_active_xtal.rs b/esp32p4/src/pmu/hp_active_xtal.rs new file mode 100644 index 0000000000..92892bd1ce --- /dev/null +++ b/esp32p4/src/pmu/hp_active_xtal.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_ACTIVE_XTAL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_ACTIVE_XTAL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_ACTIVE_XPD_XTAL` reader - need_des"] +pub type HP_ACTIVE_XPD_XTAL_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE_XPD_XTAL` writer - need_des"] +pub type HP_ACTIVE_XPD_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_active_xpd_xtal(&self) -> HP_ACTIVE_XPD_XTAL_R { + HP_ACTIVE_XPD_XTAL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_ACTIVE_XTAL") + .field( + "hp_active_xpd_xtal", + &format_args!("{}", self.hp_active_xpd_xtal().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active_xpd_xtal(&mut self) -> HP_ACTIVE_XPD_XTAL_W { + HP_ACTIVE_XPD_XTAL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_active_xtal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_active_xtal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_ACTIVE_XTAL_SPEC; +impl crate::RegisterSpec for HP_ACTIVE_XTAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_active_xtal::R`](R) reader structure"] +impl crate::Readable for HP_ACTIVE_XTAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_active_xtal::W`](W) writer structure"] +impl crate::Writable for HP_ACTIVE_XTAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_ACTIVE_XTAL to value 0x8000_0000"] +impl crate::Resettable for HP_ACTIVE_XTAL_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_0000; +} diff --git a/esp32p4/src/pmu/hp_ck_cntl.rs b/esp32p4/src/pmu/hp_ck_cntl.rs new file mode 100644 index 0000000000..97178c91fa --- /dev/null +++ b/esp32p4/src/pmu/hp_ck_cntl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `HP_CK_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CK_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `MODIFY_ICG_CNTL_WAIT` reader - need_des"] +pub type MODIFY_ICG_CNTL_WAIT_R = crate::FieldReader; +#[doc = "Field `MODIFY_ICG_CNTL_WAIT` writer - need_des"] +pub type MODIFY_ICG_CNTL_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SWITCH_ICG_CNTL_WAIT` reader - need_des"] +pub type SWITCH_ICG_CNTL_WAIT_R = crate::FieldReader; +#[doc = "Field `SWITCH_ICG_CNTL_WAIT` writer - need_des"] +pub type SWITCH_ICG_CNTL_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + pub fn modify_icg_cntl_wait(&self) -> MODIFY_ICG_CNTL_WAIT_R { + MODIFY_ICG_CNTL_WAIT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - need_des"] + #[inline(always)] + pub fn switch_icg_cntl_wait(&self) -> SWITCH_ICG_CNTL_WAIT_R { + SWITCH_ICG_CNTL_WAIT_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CK_CNTL") + .field( + "modify_icg_cntl_wait", + &format_args!("{}", self.modify_icg_cntl_wait().bits()), + ) + .field( + "switch_icg_cntl_wait", + &format_args!("{}", self.switch_icg_cntl_wait().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + #[must_use] + pub fn modify_icg_cntl_wait(&mut self) -> MODIFY_ICG_CNTL_WAIT_W { + MODIFY_ICG_CNTL_WAIT_W::new(self, 0) + } + #[doc = "Bits 8:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn switch_icg_cntl_wait(&mut self) -> SWITCH_ICG_CNTL_WAIT_W { + SWITCH_ICG_CNTL_WAIT_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ck_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ck_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CK_CNTL_SPEC; +impl crate::RegisterSpec for HP_CK_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_ck_cntl::R`](R) reader structure"] +impl crate::Readable for HP_CK_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_ck_cntl::W`](W) writer structure"] +impl crate::Writable for HP_CK_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CK_CNTL to value 0x0a0a"] +impl crate::Resettable for HP_CK_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x0a0a; +} diff --git a/esp32p4/src/pmu/hp_ck_poweron.rs b/esp32p4/src/pmu/hp_ck_poweron.rs new file mode 100644 index 0000000000..22474da2f0 --- /dev/null +++ b/esp32p4/src/pmu/hp_ck_poweron.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_CK_POWERON` reader"] +pub type R = crate::R; +#[doc = "Register `HP_CK_POWERON` writer"] +pub type W = crate::W; +#[doc = "Field `I2C_POR_WAIT_TARGET` reader - need_des"] +pub type I2C_POR_WAIT_TARGET_R = crate::FieldReader; +#[doc = "Field `I2C_POR_WAIT_TARGET` writer - need_des"] +pub type I2C_POR_WAIT_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + pub fn i2c_por_wait_target(&self) -> I2C_POR_WAIT_TARGET_R { + I2C_POR_WAIT_TARGET_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_CK_POWERON") + .field( + "i2c_por_wait_target", + &format_args!("{}", self.i2c_por_wait_target().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + #[must_use] + pub fn i2c_por_wait_target(&mut self) -> I2C_POR_WAIT_TARGET_W { + I2C_POR_WAIT_TARGET_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_ck_poweron::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_ck_poweron::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_CK_POWERON_SPEC; +impl crate::RegisterSpec for HP_CK_POWERON_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_ck_poweron::R`](R) reader structure"] +impl crate::Readable for HP_CK_POWERON_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_ck_poweron::W`](W) writer structure"] +impl crate::Writable for HP_CK_POWERON_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_CK_POWERON to value 0x32"] +impl crate::Resettable for HP_CK_POWERON_SPEC { + const RESET_VALUE: Self::Ux = 0x32; +} diff --git a/esp32p4/src/pmu/hp_int_clr.rs b/esp32p4/src/pmu/hp_int_clr.rs new file mode 100644 index 0000000000..2ad08a8bce --- /dev/null +++ b/esp32p4/src/pmu/hp_int_clr.rs @@ -0,0 +1,194 @@ +#[doc = "Register `HP_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR` writer - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR` writer - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR` writer - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR` writer - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CPU_EXC_INT_CLR` writer - need_des"] +pub type LP_CPU_EXC_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_IDLE_INT_CLR` writer - need_des"] +pub type SDIO_IDLE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_INT_CLR` writer - need_des"] +pub type SW_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOC_SLEEP_REJECT_INT_CLR` writer - need_des"] +pub type SOC_SLEEP_REJECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOC_WAKEUP_INT_CLR` writer - need_des"] +pub type SOC_WAKEUP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_0_hp_int_clr( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_W { + _0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_0_hp_int_clr( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_W { + _0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_1_hp_int_clr( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_W { + _0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_1_hp_int_clr( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_W { + _0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_0_hp_int_clr( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_W { + _0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_0_hp_int_clr( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_W { + _0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_1_hp_int_clr( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_W { + _0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_1_hp_int_clr( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_W { + _0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_0_hp_int_clr( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_W { + _0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_0_hp_int_clr( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_W { + _0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_1_hp_int_clr( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_W { + _0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_1_hp_int_clr( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_W { + _0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR_W::new(self, 25) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_exc_int_clr(&mut self) -> LP_CPU_EXC_INT_CLR_W { + LP_CPU_EXC_INT_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn sdio_idle_int_clr(&mut self) -> SDIO_IDLE_INT_CLR_W { + SDIO_IDLE_INT_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn sw_int_clr(&mut self) -> SW_INT_CLR_W { + SW_INT_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn soc_sleep_reject_int_clr(&mut self) -> SOC_SLEEP_REJECT_INT_CLR_W { + SOC_SLEEP_REJECT_INT_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn soc_wakeup_int_clr(&mut self) -> SOC_WAKEUP_INT_CLR_W { + SOC_WAKEUP_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_INT_CLR_SPEC; +impl crate::RegisterSpec for HP_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_int_clr::W`](W) writer structure"] +impl crate::Writable for HP_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_INT_CLR to value 0"] +impl crate::Resettable for HP_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_int_ena.rs b/esp32p4/src/pmu/hp_int_ena.rs new file mode 100644 index 0000000000..4f99390e2a --- /dev/null +++ b/esp32p4/src/pmu/hp_int_ena.rs @@ -0,0 +1,391 @@ +#[doc = "Register `HP_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `HP_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA` reader - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA` writer - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA` reader - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA` writer - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA` reader - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA` writer - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA` reader - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA` writer - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CPU_EXC_INT_ENA` reader - need_des"] +pub type LP_CPU_EXC_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_CPU_EXC_INT_ENA` writer - need_des"] +pub type LP_CPU_EXC_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_IDLE_INT_ENA` reader - need_des"] +pub type SDIO_IDLE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SDIO_IDLE_INT_ENA` writer - need_des"] +pub type SDIO_IDLE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_INT_ENA` reader - need_des"] +pub type SW_INT_ENA_R = crate::BitReader; +#[doc = "Field `SW_INT_ENA` writer - need_des"] +pub type SW_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOC_SLEEP_REJECT_INT_ENA` reader - need_des"] +pub type SOC_SLEEP_REJECT_INT_ENA_R = crate::BitReader; +#[doc = "Field `SOC_SLEEP_REJECT_INT_ENA` writer - need_des"] +pub type SOC_SLEEP_REJECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOC_WAKEUP_INT_ENA` reader - need_des"] +pub type SOC_WAKEUP_INT_ENA_R = crate::BitReader; +#[doc = "Field `SOC_WAKEUP_INT_ENA` writer - need_des"] +pub type SOC_WAKEUP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_0_hp_int_ena(&self) -> _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_R { + _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_0_hp_int_ena(&self) -> _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_R { + _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_1_hp_int_ena(&self) -> _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_R { + _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_1_hp_int_ena(&self) -> _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_R { + _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_0_hp_int_ena(&self) -> _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_R { + _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_0_hp_int_ena(&self) -> _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_R { + _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_1_hp_int_ena(&self) -> _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_R { + _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_1_hp_int_ena(&self) -> _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_R { + _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_0_hp_int_ena(&self) -> _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_R { + _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_0_hp_int_ena(&self) -> _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_R { + _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_1_hp_int_ena(&self) -> _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_R { + _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_1_hp_int_ena(&self) -> _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_R { + _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_cpu_exc_int_ena(&self) -> LP_CPU_EXC_INT_ENA_R { + LP_CPU_EXC_INT_ENA_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn sdio_idle_int_ena(&self) -> SDIO_IDLE_INT_ENA_R { + SDIO_IDLE_INT_ENA_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn sw_int_ena(&self) -> SW_INT_ENA_R { + SW_INT_ENA_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn soc_sleep_reject_int_ena(&self) -> SOC_SLEEP_REJECT_INT_ENA_R { + SOC_SLEEP_REJECT_INT_ENA_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn soc_wakeup_int_ena(&self) -> SOC_WAKEUP_INT_ENA_R { + SOC_WAKEUP_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_INT_ENA") + .field( + "_0p1a_cnt_target0_reach_0_hp_int_ena", + &format_args!("{}", self._0p1a_cnt_target0_reach_0_hp_int_ena().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_0_hp_int_ena", + &format_args!("{}", self._0p1a_cnt_target1_reach_0_hp_int_ena().bit()), + ) + .field( + "_0p1a_cnt_target0_reach_1_hp_int_ena", + &format_args!("{}", self._0p1a_cnt_target0_reach_1_hp_int_ena().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_1_hp_int_ena", + &format_args!("{}", self._0p1a_cnt_target1_reach_1_hp_int_ena().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_0_hp_int_ena", + &format_args!("{}", self._0p2a_cnt_target0_reach_0_hp_int_ena().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_0_hp_int_ena", + &format_args!("{}", self._0p2a_cnt_target1_reach_0_hp_int_ena().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_1_hp_int_ena", + &format_args!("{}", self._0p2a_cnt_target0_reach_1_hp_int_ena().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_1_hp_int_ena", + &format_args!("{}", self._0p2a_cnt_target1_reach_1_hp_int_ena().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_0_hp_int_ena", + &format_args!("{}", self._0p3a_cnt_target0_reach_0_hp_int_ena().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_0_hp_int_ena", + &format_args!("{}", self._0p3a_cnt_target1_reach_0_hp_int_ena().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_1_hp_int_ena", + &format_args!("{}", self._0p3a_cnt_target0_reach_1_hp_int_ena().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_1_hp_int_ena", + &format_args!("{}", self._0p3a_cnt_target1_reach_1_hp_int_ena().bit()), + ) + .field( + "lp_cpu_exc_int_ena", + &format_args!("{}", self.lp_cpu_exc_int_ena().bit()), + ) + .field( + "sdio_idle_int_ena", + &format_args!("{}", self.sdio_idle_int_ena().bit()), + ) + .field("sw_int_ena", &format_args!("{}", self.sw_int_ena().bit())) + .field( + "soc_sleep_reject_int_ena", + &format_args!("{}", self.soc_sleep_reject_int_ena().bit()), + ) + .field( + "soc_wakeup_int_ena", + &format_args!("{}", self.soc_wakeup_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_0_hp_int_ena( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_W { + _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_0_hp_int_ena( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_W { + _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_1_hp_int_ena( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_W { + _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_1_hp_int_ena( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_W { + _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_0_hp_int_ena( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_W { + _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA_W::new(self, 18) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_0_hp_int_ena( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_W { + _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA_W::new(self, 19) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_1_hp_int_ena( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_W { + _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA_W::new(self, 20) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_1_hp_int_ena( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_W { + _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA_W::new(self, 21) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_0_hp_int_ena( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_W { + _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA_W::new(self, 22) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_0_hp_int_ena( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_W { + _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA_W::new(self, 23) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_1_hp_int_ena( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_W { + _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA_W::new(self, 24) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_1_hp_int_ena( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_W { + _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA_W::new(self, 25) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_exc_int_ena(&mut self) -> LP_CPU_EXC_INT_ENA_W { + LP_CPU_EXC_INT_ENA_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn sdio_idle_int_ena(&mut self) -> SDIO_IDLE_INT_ENA_W { + SDIO_IDLE_INT_ENA_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn sw_int_ena(&mut self) -> SW_INT_ENA_W { + SW_INT_ENA_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn soc_sleep_reject_int_ena(&mut self) -> SOC_SLEEP_REJECT_INT_ENA_W { + SOC_SLEEP_REJECT_INT_ENA_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn soc_wakeup_int_ena(&mut self) -> SOC_WAKEUP_INT_ENA_W { + SOC_WAKEUP_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_INT_ENA_SPEC; +impl crate::RegisterSpec for HP_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_int_ena::R`](R) reader structure"] +impl crate::Readable for HP_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_int_ena::W`](W) writer structure"] +impl crate::Writable for HP_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_INT_ENA to value 0"] +impl crate::Resettable for HP_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_int_st.rs b/esp32p4/src/pmu/hp_int_st.rs new file mode 100644 index 0000000000..fb3ad3b1e9 --- /dev/null +++ b/esp32p4/src/pmu/hp_int_st.rs @@ -0,0 +1,212 @@ +#[doc = "Register `HP_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_HP_INT_ST` reader - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_HP_INT_ST` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_HP_INT_ST` reader - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_HP_INT_ST` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_HP_INT_ST` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_HP_INT_ST` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_HP_INT_ST` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_HP_INT_ST` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_HP_INT_ST` reader - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_HP_INT_ST` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_HP_INT_ST` reader - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_HP_INT_ST` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_CPU_EXC_INT_ST` reader - need_des"] +pub type LP_CPU_EXC_INT_ST_R = crate::BitReader; +#[doc = "Field `SDIO_IDLE_INT_ST` reader - need_des"] +pub type SDIO_IDLE_INT_ST_R = crate::BitReader; +#[doc = "Field `SW_INT_ST` reader - need_des"] +pub type SW_INT_ST_R = crate::BitReader; +#[doc = "Field `SOC_SLEEP_REJECT_INT_ST` reader - need_des"] +pub type SOC_SLEEP_REJECT_INT_ST_R = crate::BitReader; +#[doc = "Field `SOC_WAKEUP_INT_ST` reader - need_des"] +pub type SOC_WAKEUP_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_0_hp_int_st(&self) -> _0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_R { + _0P1A_CNT_TARGET0_REACH_0_HP_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_0_hp_int_st(&self) -> _0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_R { + _0P1A_CNT_TARGET1_REACH_0_HP_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_1_hp_int_st(&self) -> _0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_R { + _0P1A_CNT_TARGET0_REACH_1_HP_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_1_hp_int_st(&self) -> _0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_R { + _0P1A_CNT_TARGET1_REACH_1_HP_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_0_hp_int_st(&self) -> _0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_R { + _0P2A_CNT_TARGET0_REACH_0_HP_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_0_hp_int_st(&self) -> _0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_R { + _0P2A_CNT_TARGET1_REACH_0_HP_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_1_hp_int_st(&self) -> _0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_R { + _0P2A_CNT_TARGET0_REACH_1_HP_INT_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_1_hp_int_st(&self) -> _0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_R { + _0P2A_CNT_TARGET1_REACH_1_HP_INT_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_0_hp_int_st(&self) -> _0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_R { + _0P3A_CNT_TARGET0_REACH_0_HP_INT_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_0_hp_int_st(&self) -> _0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_R { + _0P3A_CNT_TARGET1_REACH_0_HP_INT_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_1_hp_int_st(&self) -> _0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_R { + _0P3A_CNT_TARGET0_REACH_1_HP_INT_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_1_hp_int_st(&self) -> _0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_R { + _0P3A_CNT_TARGET1_REACH_1_HP_INT_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_cpu_exc_int_st(&self) -> LP_CPU_EXC_INT_ST_R { + LP_CPU_EXC_INT_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn sdio_idle_int_st(&self) -> SDIO_IDLE_INT_ST_R { + SDIO_IDLE_INT_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn sw_int_st(&self) -> SW_INT_ST_R { + SW_INT_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn soc_sleep_reject_int_st(&self) -> SOC_SLEEP_REJECT_INT_ST_R { + SOC_SLEEP_REJECT_INT_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn soc_wakeup_int_st(&self) -> SOC_WAKEUP_INT_ST_R { + SOC_WAKEUP_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_INT_ST") + .field( + "_0p1a_cnt_target0_reach_0_hp_int_st", + &format_args!("{}", self._0p1a_cnt_target0_reach_0_hp_int_st().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_0_hp_int_st", + &format_args!("{}", self._0p1a_cnt_target1_reach_0_hp_int_st().bit()), + ) + .field( + "_0p1a_cnt_target0_reach_1_hp_int_st", + &format_args!("{}", self._0p1a_cnt_target0_reach_1_hp_int_st().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_1_hp_int_st", + &format_args!("{}", self._0p1a_cnt_target1_reach_1_hp_int_st().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_0_hp_int_st", + &format_args!("{}", self._0p2a_cnt_target0_reach_0_hp_int_st().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_0_hp_int_st", + &format_args!("{}", self._0p2a_cnt_target1_reach_0_hp_int_st().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_1_hp_int_st", + &format_args!("{}", self._0p2a_cnt_target0_reach_1_hp_int_st().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_1_hp_int_st", + &format_args!("{}", self._0p2a_cnt_target1_reach_1_hp_int_st().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_0_hp_int_st", + &format_args!("{}", self._0p3a_cnt_target0_reach_0_hp_int_st().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_0_hp_int_st", + &format_args!("{}", self._0p3a_cnt_target1_reach_0_hp_int_st().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_1_hp_int_st", + &format_args!("{}", self._0p3a_cnt_target0_reach_1_hp_int_st().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_1_hp_int_st", + &format_args!("{}", self._0p3a_cnt_target1_reach_1_hp_int_st().bit()), + ) + .field( + "lp_cpu_exc_int_st", + &format_args!("{}", self.lp_cpu_exc_int_st().bit()), + ) + .field( + "sdio_idle_int_st", + &format_args!("{}", self.sdio_idle_int_st().bit()), + ) + .field("sw_int_st", &format_args!("{}", self.sw_int_st().bit())) + .field( + "soc_sleep_reject_int_st", + &format_args!("{}", self.soc_sleep_reject_int_st().bit()), + ) + .field( + "soc_wakeup_int_st", + &format_args!("{}", self.soc_wakeup_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_INT_ST_SPEC; +impl crate::RegisterSpec for HP_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_int_st::R`](R) reader structure"] +impl crate::Readable for HP_INT_ST_SPEC {} +#[doc = "`reset()` method sets HP_INT_ST to value 0"] +impl crate::Resettable for HP_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_lp_cpu_comm.rs b/esp32p4/src/pmu/hp_lp_cpu_comm.rs new file mode 100644 index 0000000000..b7ad236d6c --- /dev/null +++ b/esp32p4/src/pmu/hp_lp_cpu_comm.rs @@ -0,0 +1,50 @@ +#[doc = "Register `HP_LP_CPU_COMM` writer"] +pub type W = crate::W; +#[doc = "Field `LP_TRIGGER_HP` writer - need_des"] +pub type LP_TRIGGER_HP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_TRIGGER_LP` writer - need_des"] +pub type HP_TRIGGER_LP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_trigger_hp(&mut self) -> LP_TRIGGER_HP_W { + LP_TRIGGER_HP_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_trigger_lp(&mut self) -> HP_TRIGGER_LP_W { + HP_TRIGGER_LP_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_lp_cpu_comm::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_LP_CPU_COMM_SPEC; +impl crate::RegisterSpec for HP_LP_CPU_COMM_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_lp_cpu_comm::W`](W) writer structure"] +impl crate::Writable for HP_LP_CPU_COMM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_LP_CPU_COMM to value 0"] +impl crate::Resettable for HP_LP_CPU_COMM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_modem_backup.rs b/esp32p4/src/pmu/hp_modem_backup.rs new file mode 100644 index 0000000000..d1b1ee0452 --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_backup.rs @@ -0,0 +1,90 @@ +#[doc = "Register `HP_MODEM_BACKUP` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE` writer - need_des"] +pub type HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_MODEM_RETENTION_MODE` writer - need_des"] +pub type HP_MODEM_RETENTION_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP2MODEM_RETENTION_EN` writer - need_des"] +pub type HP_SLEEP2MODEM_RETENTION_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP2MODEM_BACKUP_CLK_SEL` writer - need_des"] +pub type HP_SLEEP2MODEM_BACKUP_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_SLEEP2MODEM_BACKUP_MODE` writer - need_des"] +pub type HP_SLEEP2MODEM_BACKUP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_SLEEP2MODEM_BACKUP_EN` writer - need_des"] +pub type HP_SLEEP2MODEM_BACKUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 4:5 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep2modem_backup_modem_clk_code( + &mut self, + ) -> HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_W { + HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_W::new(self, 4) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_retention_mode(&mut self) -> HP_MODEM_RETENTION_MODE_W { + HP_MODEM_RETENTION_MODE_W::new(self, 10) + } + #[doc = "Bit 11 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep2modem_retention_en( + &mut self, + ) -> HP_SLEEP2MODEM_RETENTION_EN_W { + HP_SLEEP2MODEM_RETENTION_EN_W::new(self, 11) + } + #[doc = "Bits 14:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep2modem_backup_clk_sel( + &mut self, + ) -> HP_SLEEP2MODEM_BACKUP_CLK_SEL_W { + HP_SLEEP2MODEM_BACKUP_CLK_SEL_W::new(self, 14) + } + #[doc = "Bits 20:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep2modem_backup_mode( + &mut self, + ) -> HP_SLEEP2MODEM_BACKUP_MODE_W { + HP_SLEEP2MODEM_BACKUP_MODE_W::new(self, 20) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep2modem_backup_en(&mut self) -> HP_SLEEP2MODEM_BACKUP_EN_W { + HP_SLEEP2MODEM_BACKUP_EN_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_backup::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_BACKUP_SPEC; +impl crate::RegisterSpec for HP_MODEM_BACKUP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_backup::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_BACKUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_BACKUP to value 0"] +impl crate::Resettable for HP_MODEM_BACKUP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_modem_backup_clk.rs b/esp32p4/src/pmu/hp_modem_backup_clk.rs new file mode 100644 index 0000000000..8007da2cd2 --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_backup_clk.rs @@ -0,0 +1,44 @@ +#[doc = "Register `HP_MODEM_BACKUP_CLK` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_BACKUP_ICG_FUNC_EN` writer - need_des"] +pub type HP_MODEM_BACKUP_ICG_FUNC_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_backup_icg_func_en( + &mut self, + ) -> HP_MODEM_BACKUP_ICG_FUNC_EN_W { + HP_MODEM_BACKUP_ICG_FUNC_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_backup_clk::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_BACKUP_CLK_SPEC; +impl crate::RegisterSpec for HP_MODEM_BACKUP_CLK_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_backup_clk::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_BACKUP_CLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_BACKUP_CLK to value 0"] +impl crate::Resettable for HP_MODEM_BACKUP_CLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_modem_bias.rs b/esp32p4/src/pmu/hp_modem_bias.rs new file mode 100644 index 0000000000..c8e733e7ba --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_bias.rs @@ -0,0 +1,82 @@ +#[doc = "Register `HP_MODEM_BIAS` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_DCM_VSET` writer - need_des"] +pub type HP_MODEM_DCM_VSET_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `HP_MODEM_DCM_MODE` writer - need_des"] +pub type HP_MODEM_DCM_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_MODEM_XPD_BIAS` writer - need_des"] +pub type HP_MODEM_XPD_BIAS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_DBG_ATTEN` writer - need_des"] +pub type HP_MODEM_DBG_ATTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_MODEM_PD_CUR` writer - need_des"] +pub type HP_MODEM_PD_CUR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEP` writer - need_des"] +pub type SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dcm_vset(&mut self) -> HP_MODEM_DCM_VSET_W { + HP_MODEM_DCM_VSET_W::new(self, 18) + } + #[doc = "Bits 23:24 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dcm_mode(&mut self) -> HP_MODEM_DCM_MODE_W { + HP_MODEM_DCM_MODE_W::new(self, 23) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_xpd_bias(&mut self) -> HP_MODEM_XPD_BIAS_W { + HP_MODEM_XPD_BIAS_W::new(self, 25) + } + #[doc = "Bits 26:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dbg_atten(&mut self) -> HP_MODEM_DBG_ATTEN_W { + HP_MODEM_DBG_ATTEN_W::new(self, 26) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_pd_cur(&mut self) -> HP_MODEM_PD_CUR_W { + HP_MODEM_PD_CUR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep(&mut self) -> SLEEP_W { + SLEEP_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_bias::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_BIAS_SPEC; +impl crate::RegisterSpec for HP_MODEM_BIAS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_bias::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_BIAS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_BIAS to value 0x0050_0000"] +impl crate::Resettable for HP_MODEM_BIAS_SPEC { + const RESET_VALUE: Self::Ux = 0x0050_0000; +} diff --git a/esp32p4/src/pmu/hp_modem_dig_power.rs b/esp32p4/src/pmu/hp_modem_dig_power.rs new file mode 100644 index 0000000000..2b7c814d1f --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_dig_power.rs @@ -0,0 +1,122 @@ +#[doc = "Register `HP_MODEM_DIG_POWER` reader"] +pub type R = crate::R; +#[doc = "Register `HP_MODEM_DIG_POWER` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_DCDC_SWITCH_PD_EN` reader - need_des"] +pub type HP_MODEM_DCDC_SWITCH_PD_EN_R = crate::BitReader; +#[doc = "Field `HP_MODEM_DCDC_SWITCH_PD_EN` writer - need_des"] +pub type HP_MODEM_DCDC_SWITCH_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_HP_MEM_DSLP` writer - need_des"] +pub type HP_MODEM_HP_MEM_DSLP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_PD_HP_MEM_PD_EN` writer - need_des"] +pub type HP_MODEM_PD_HP_MEM_PD_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_MODEM_PD_HP_WIFI_PD_EN` writer - need_des"] +pub type HP_MODEM_PD_HP_WIFI_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_PD_HP_CPU_PD_EN` writer - need_des"] +pub type HP_MODEM_PD_HP_CPU_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_PD_CNNT_PD_EN` writer - need_des"] +pub type HP_MODEM_PD_CNNT_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_PD_TOP_PD_EN` writer - need_des"] +pub type HP_MODEM_PD_TOP_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + pub fn hp_modem_dcdc_switch_pd_en(&self) -> HP_MODEM_DCDC_SWITCH_PD_EN_R { + HP_MODEM_DCDC_SWITCH_PD_EN_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_MODEM_DIG_POWER") + .field( + "hp_modem_dcdc_switch_pd_en", + &format_args!("{}", self.hp_modem_dcdc_switch_pd_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dcdc_switch_pd_en( + &mut self, + ) -> HP_MODEM_DCDC_SWITCH_PD_EN_W { + HP_MODEM_DCDC_SWITCH_PD_EN_W::new(self, 21) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_hp_mem_dslp(&mut self) -> HP_MODEM_HP_MEM_DSLP_W { + HP_MODEM_HP_MEM_DSLP_W::new(self, 22) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_pd_hp_mem_pd_en( + &mut self, + ) -> HP_MODEM_PD_HP_MEM_PD_EN_W { + HP_MODEM_PD_HP_MEM_PD_EN_W::new(self, 23) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_pd_hp_wifi_pd_en( + &mut self, + ) -> HP_MODEM_PD_HP_WIFI_PD_EN_W { + HP_MODEM_PD_HP_WIFI_PD_EN_W::new(self, 27) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_pd_hp_cpu_pd_en( + &mut self, + ) -> HP_MODEM_PD_HP_CPU_PD_EN_W { + HP_MODEM_PD_HP_CPU_PD_EN_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_pd_cnnt_pd_en(&mut self) -> HP_MODEM_PD_CNNT_PD_EN_W { + HP_MODEM_PD_CNNT_PD_EN_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_pd_top_pd_en(&mut self) -> HP_MODEM_PD_TOP_PD_EN_W { + HP_MODEM_PD_TOP_PD_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_modem_dig_power::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_dig_power::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_DIG_POWER_SPEC; +impl crate::RegisterSpec for HP_MODEM_DIG_POWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_modem_dig_power::R`](R) reader structure"] +impl crate::Readable for HP_MODEM_DIG_POWER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_modem_dig_power::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_DIG_POWER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_DIG_POWER to value 0"] +impl crate::Resettable for HP_MODEM_DIG_POWER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_modem_hp_ck_power.rs b/esp32p4/src/pmu/hp_modem_hp_ck_power.rs new file mode 100644 index 0000000000..279b6cf2c8 --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_hp_ck_power.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_MODEM_HP_CK_POWER` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_I2C_ISO_EN` writer - need_des"] +pub type HP_MODEM_I2C_ISO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_I2C_RETENTION` writer - need_des"] +pub type HP_MODEM_I2C_RETENTION_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_XPD_PLL_I2C` writer - need_des"] +pub type HP_MODEM_XPD_PLL_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_MODEM_XPD_PLL` writer - need_des"] +pub type HP_MODEM_XPD_PLL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_i2c_iso_en(&mut self) -> HP_MODEM_I2C_ISO_EN_W { + HP_MODEM_I2C_ISO_EN_W::new(self, 21) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_i2c_retention( + &mut self, + ) -> HP_MODEM_I2C_RETENTION_W { + HP_MODEM_I2C_RETENTION_W::new(self, 22) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_xpd_pll_i2c(&mut self) -> HP_MODEM_XPD_PLL_I2C_W { + HP_MODEM_XPD_PLL_I2C_W::new(self, 23) + } + #[doc = "Bits 27:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_xpd_pll(&mut self) -> HP_MODEM_XPD_PLL_W { + HP_MODEM_XPD_PLL_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_hp_ck_power::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_HP_CK_POWER_SPEC; +impl crate::RegisterSpec for HP_MODEM_HP_CK_POWER_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_hp_ck_power::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_HP_CK_POWER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_HP_CK_POWER to value 0"] +impl crate::Resettable for HP_MODEM_HP_CK_POWER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_modem_hp_regulator0.rs b/esp32p4/src/pmu/hp_modem_hp_regulator0.rs new file mode 100644 index 0000000000..d90cb55455 --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_hp_regulator0.rs @@ -0,0 +1,94 @@ +#[doc = "Register `HP_MODEM_HP_REGULATOR0` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_HP_REGULATOR_SLP_MEM_XPD` writer - need_des"] +pub type HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD` writer - need_des"] +pub type HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_HP_REGULATOR_XPD` writer - need_des"] +pub type HP_MODEM_HP_REGULATOR_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS` writer - need_des"] +pub type HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS` writer - need_des"] +pub type HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_MODEM_HP_REGULATOR_DBIAS` writer - need_des"] +pub type HP_MODEM_HP_REGULATOR_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 16 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_hp_regulator_slp_mem_xpd( + &mut self, + ) -> HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_W { + HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_W::new(self, 16) + } + #[doc = "Bit 17 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_hp_regulator_slp_logic_xpd( + &mut self, + ) -> HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_W { + HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_W::new(self, 17) + } + #[doc = "Bit 18 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_hp_regulator_xpd( + &mut self, + ) -> HP_MODEM_HP_REGULATOR_XPD_W { + HP_MODEM_HP_REGULATOR_XPD_W::new(self, 18) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_hp_regulator_slp_mem_dbias( + &mut self, + ) -> HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_W { + HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_W::new(self, 19) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_hp_regulator_slp_logic_dbias( + &mut self, + ) -> HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_W { + HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_W::new(self, 23) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_hp_regulator_dbias( + &mut self, + ) -> HP_MODEM_HP_REGULATOR_DBIAS_W { + HP_MODEM_HP_REGULATOR_DBIAS_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_hp_regulator0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_HP_REGULATOR0_SPEC; +impl crate::RegisterSpec for HP_MODEM_HP_REGULATOR0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_hp_regulator0::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_HP_REGULATOR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_HP_REGULATOR0 to value 0xc667_0000"] +impl crate::Resettable for HP_MODEM_HP_REGULATOR0_SPEC { + const RESET_VALUE: Self::Ux = 0xc667_0000; +} diff --git a/esp32p4/src/pmu/hp_modem_hp_regulator1.rs b/esp32p4/src/pmu/hp_modem_hp_regulator1.rs new file mode 100644 index 0000000000..c75e48bba5 --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_hp_regulator1.rs @@ -0,0 +1,44 @@ +#[doc = "Register `HP_MODEM_HP_REGULATOR1` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_HP_REGULATOR_DRV_B` writer - need_des"] +pub type HP_MODEM_HP_REGULATOR_DRV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 8:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_hp_regulator_drv_b( + &mut self, + ) -> HP_MODEM_HP_REGULATOR_DRV_B_W { + HP_MODEM_HP_REGULATOR_DRV_B_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_hp_regulator1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_HP_REGULATOR1_SPEC; +impl crate::RegisterSpec for HP_MODEM_HP_REGULATOR1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_hp_regulator1::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_HP_REGULATOR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_HP_REGULATOR1 to value 0"] +impl crate::Resettable for HP_MODEM_HP_REGULATOR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_modem_hp_sys_cntl.rs b/esp32p4/src/pmu/hp_modem_hp_sys_cntl.rs new file mode 100644 index 0000000000..0713294926 --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_hp_sys_cntl.rs @@ -0,0 +1,104 @@ +#[doc = "Register `HP_MODEM_HP_SYS_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_HP_POWER_DET_BYPASS` writer - need_des"] +pub type HP_MODEM_HP_POWER_DET_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_UART_WAKEUP_EN` writer - need_des"] +pub type HP_MODEM_UART_WAKEUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_LP_PAD_HOLD_ALL` writer - need_des"] +pub type HP_MODEM_LP_PAD_HOLD_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_HP_PAD_HOLD_ALL` writer - need_des"] +pub type HP_MODEM_HP_PAD_HOLD_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_DIG_PAD_SLP_SEL` writer - need_des"] +pub type HP_MODEM_DIG_PAD_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_DIG_PAUSE_WDT` writer - need_des"] +pub type HP_MODEM_DIG_PAUSE_WDT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_DIG_CPU_STALL` writer - need_des"] +pub type HP_MODEM_DIG_CPU_STALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 23 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_hp_power_det_bypass( + &mut self, + ) -> HP_MODEM_HP_POWER_DET_BYPASS_W { + HP_MODEM_HP_POWER_DET_BYPASS_W::new(self, 23) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_uart_wakeup_en( + &mut self, + ) -> HP_MODEM_UART_WAKEUP_EN_W { + HP_MODEM_UART_WAKEUP_EN_W::new(self, 24) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_lp_pad_hold_all( + &mut self, + ) -> HP_MODEM_LP_PAD_HOLD_ALL_W { + HP_MODEM_LP_PAD_HOLD_ALL_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_hp_pad_hold_all( + &mut self, + ) -> HP_MODEM_HP_PAD_HOLD_ALL_W { + HP_MODEM_HP_PAD_HOLD_ALL_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dig_pad_slp_sel( + &mut self, + ) -> HP_MODEM_DIG_PAD_SLP_SEL_W { + HP_MODEM_DIG_PAD_SLP_SEL_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dig_pause_wdt( + &mut self, + ) -> HP_MODEM_DIG_PAUSE_WDT_W { + HP_MODEM_DIG_PAUSE_WDT_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dig_cpu_stall( + &mut self, + ) -> HP_MODEM_DIG_CPU_STALL_W { + HP_MODEM_DIG_CPU_STALL_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_hp_sys_cntl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_HP_SYS_CNTL_SPEC; +impl crate::RegisterSpec for HP_MODEM_HP_SYS_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_hp_sys_cntl::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_HP_SYS_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_HP_SYS_CNTL to value 0"] +impl crate::Resettable for HP_MODEM_HP_SYS_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_modem_icg_hp_apb.rs b/esp32p4/src/pmu/hp_modem_icg_hp_apb.rs new file mode 100644 index 0000000000..e4fc276d3a --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_icg_hp_apb.rs @@ -0,0 +1,44 @@ +#[doc = "Register `HP_MODEM_ICG_HP_APB` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_DIG_ICG_APB_EN` writer - need_des"] +pub type HP_MODEM_DIG_ICG_APB_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dig_icg_apb_en( + &mut self, + ) -> HP_MODEM_DIG_ICG_APB_EN_W { + HP_MODEM_DIG_ICG_APB_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_icg_hp_apb::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_ICG_HP_APB_SPEC; +impl crate::RegisterSpec for HP_MODEM_ICG_HP_APB_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_icg_hp_apb::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_ICG_HP_APB_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_ICG_HP_APB to value 0xffff_ffff"] +impl crate::Resettable for HP_MODEM_ICG_HP_APB_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/pmu/hp_modem_icg_hp_func.rs b/esp32p4/src/pmu/hp_modem_icg_hp_func.rs new file mode 100644 index 0000000000..9425c67475 --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_icg_hp_func.rs @@ -0,0 +1,44 @@ +#[doc = "Register `HP_MODEM_ICG_HP_FUNC` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_DIG_ICG_FUNC_EN` writer - need_des"] +pub type HP_MODEM_DIG_ICG_FUNC_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dig_icg_func_en( + &mut self, + ) -> HP_MODEM_DIG_ICG_FUNC_EN_W { + HP_MODEM_DIG_ICG_FUNC_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_icg_hp_func::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_ICG_HP_FUNC_SPEC; +impl crate::RegisterSpec for HP_MODEM_ICG_HP_FUNC_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_icg_hp_func::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_ICG_HP_FUNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_ICG_HP_FUNC to value 0xffff_ffff"] +impl crate::Resettable for HP_MODEM_ICG_HP_FUNC_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/pmu/hp_modem_icg_modem.rs b/esp32p4/src/pmu/hp_modem_icg_modem.rs new file mode 100644 index 0000000000..3f0806246b --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_icg_modem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `HP_MODEM_ICG_MODEM` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_DIG_ICG_MODEM_CODE` writer - need_des"] +pub type HP_MODEM_DIG_ICG_MODEM_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dig_icg_modem_code( + &mut self, + ) -> HP_MODEM_DIG_ICG_MODEM_CODE_W { + HP_MODEM_DIG_ICG_MODEM_CODE_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_icg_modem::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_ICG_MODEM_SPEC; +impl crate::RegisterSpec for HP_MODEM_ICG_MODEM_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_icg_modem::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_ICG_MODEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_ICG_MODEM to value 0"] +impl crate::Resettable for HP_MODEM_ICG_MODEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_modem_sysclk.rs b/esp32p4/src/pmu/hp_modem_sysclk.rs new file mode 100644 index 0000000000..fe72032e14 --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_sysclk.rs @@ -0,0 +1,78 @@ +#[doc = "Register `HP_MODEM_SYSCLK` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_DIG_SYS_CLK_NO_DIV` writer - need_des"] +pub type HP_MODEM_DIG_SYS_CLK_NO_DIV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_ICG_SYS_CLOCK_EN` writer - need_des"] +pub type HP_MODEM_ICG_SYS_CLOCK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_SYS_CLK_SLP_SEL` writer - need_des"] +pub type HP_MODEM_SYS_CLK_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_ICG_SLP_SEL` writer - need_des"] +pub type HP_MODEM_ICG_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM_DIG_SYS_CLK_SEL` writer - need_des"] +pub type HP_MODEM_DIG_SYS_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dig_sys_clk_no_div( + &mut self, + ) -> HP_MODEM_DIG_SYS_CLK_NO_DIV_W { + HP_MODEM_DIG_SYS_CLK_NO_DIV_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_icg_sys_clock_en( + &mut self, + ) -> HP_MODEM_ICG_SYS_CLOCK_EN_W { + HP_MODEM_ICG_SYS_CLOCK_EN_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_sys_clk_slp_sel(&mut self) -> HP_MODEM_SYS_CLK_SLP_SEL_W { + HP_MODEM_SYS_CLK_SLP_SEL_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_icg_slp_sel(&mut self) -> HP_MODEM_ICG_SLP_SEL_W { + HP_MODEM_ICG_SLP_SEL_W::new(self, 29) + } + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_dig_sys_clk_sel(&mut self) -> HP_MODEM_DIG_SYS_CLK_SEL_W { + HP_MODEM_DIG_SYS_CLK_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_sysclk::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_SYSCLK_SPEC; +impl crate::RegisterSpec for HP_MODEM_SYSCLK_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_sysclk::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_SYSCLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_SYSCLK to value 0"] +impl crate::Resettable for HP_MODEM_SYSCLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_modem_xtal.rs b/esp32p4/src/pmu/hp_modem_xtal.rs new file mode 100644 index 0000000000..4eca7161ba --- /dev/null +++ b/esp32p4/src/pmu/hp_modem_xtal.rs @@ -0,0 +1,42 @@ +#[doc = "Register `HP_MODEM_XTAL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM_XPD_XTAL` writer - need_des"] +pub type HP_MODEM_XPD_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem_xpd_xtal(&mut self) -> HP_MODEM_XPD_XTAL_W { + HP_MODEM_XPD_XTAL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_modem_xtal::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_MODEM_XTAL_SPEC; +impl crate::RegisterSpec for HP_MODEM_XTAL_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_modem_xtal::W`](W) writer structure"] +impl crate::Writable for HP_MODEM_XTAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_MODEM_XTAL to value 0x8000_0000"] +impl crate::Resettable for HP_MODEM_XTAL_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_0000; +} diff --git a/esp32p4/src/pmu/hp_regulator_cfg.rs b/esp32p4/src/pmu/hp_regulator_cfg.rs new file mode 100644 index 0000000000..e2ab897653 --- /dev/null +++ b/esp32p4/src/pmu/hp_regulator_cfg.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_REGULATOR_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `HP_REGULATOR_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `DIG_REGULATOR_EN_CAL` reader - need_des"] +pub type DIG_REGULATOR_EN_CAL_R = crate::BitReader; +#[doc = "Field `DIG_REGULATOR_EN_CAL` writer - need_des"] +pub type DIG_REGULATOR_EN_CAL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn dig_regulator_en_cal(&self) -> DIG_REGULATOR_EN_CAL_R { + DIG_REGULATOR_EN_CAL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_REGULATOR_CFG") + .field( + "dig_regulator_en_cal", + &format_args!("{}", self.dig_regulator_en_cal().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn dig_regulator_en_cal(&mut self) -> DIG_REGULATOR_EN_CAL_W { + DIG_REGULATOR_EN_CAL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_regulator_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_regulator_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_REGULATOR_CFG_SPEC; +impl crate::RegisterSpec for HP_REGULATOR_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_regulator_cfg::R`](R) reader structure"] +impl crate::Readable for HP_REGULATOR_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_regulator_cfg::W`](W) writer structure"] +impl crate::Writable for HP_REGULATOR_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_REGULATOR_CFG to value 0"] +impl crate::Resettable for HP_REGULATOR_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_backup.rs b/esp32p4/src/pmu/hp_sleep_backup.rs new file mode 100644 index 0000000000..0af462ff47 --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_backup.rs @@ -0,0 +1,274 @@ +#[doc = "Register `HP_SLEEP_BACKUP` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_BACKUP` writer"] +pub type W = crate::W; +#[doc = "Field `HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE` reader - need_des"] +pub type HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_R = crate::FieldReader; +#[doc = "Field `HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE` writer - need_des"] +pub type HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE` reader - need_des"] +pub type HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE` writer - need_des"] +pub type HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_SLEEP_RETENTION_MODE` reader - need_des"] +pub type HP_SLEEP_RETENTION_MODE_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_RETENTION_MODE` writer - need_des"] +pub type HP_SLEEP_RETENTION_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM2SLEEP_RETENTION_EN` reader - need_des"] +pub type HP_MODEM2SLEEP_RETENTION_EN_R = crate::BitReader; +#[doc = "Field `HP_MODEM2SLEEP_RETENTION_EN` writer - need_des"] +pub type HP_MODEM2SLEEP_RETENTION_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE2SLEEP_RETENTION_EN` reader - need_des"] +pub type HP_ACTIVE2SLEEP_RETENTION_EN_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE2SLEEP_RETENTION_EN` writer - need_des"] +pub type HP_ACTIVE2SLEEP_RETENTION_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_MODEM2SLEEP_BACKUP_CLK_SEL` reader - need_des"] +pub type HP_MODEM2SLEEP_BACKUP_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `HP_MODEM2SLEEP_BACKUP_CLK_SEL` writer - need_des"] +pub type HP_MODEM2SLEEP_BACKUP_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_ACTIVE2SLEEP_BACKUP_CLK_SEL` reader - need_des"] +pub type HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE2SLEEP_BACKUP_CLK_SEL` writer - need_des"] +pub type HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_MODEM2SLEEP_BACKUP_MODE` reader - need_des"] +pub type HP_MODEM2SLEEP_BACKUP_MODE_R = crate::FieldReader; +#[doc = "Field `HP_MODEM2SLEEP_BACKUP_MODE` writer - need_des"] +pub type HP_MODEM2SLEEP_BACKUP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_ACTIVE2SLEEP_BACKUP_MODE` reader - need_des"] +pub type HP_ACTIVE2SLEEP_BACKUP_MODE_R = crate::FieldReader; +#[doc = "Field `HP_ACTIVE2SLEEP_BACKUP_MODE` writer - need_des"] +pub type HP_ACTIVE2SLEEP_BACKUP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `HP_MODEM2SLEEP_BACKUP_EN` reader - need_des"] +pub type HP_MODEM2SLEEP_BACKUP_EN_R = crate::BitReader; +#[doc = "Field `HP_MODEM2SLEEP_BACKUP_EN` writer - need_des"] +pub type HP_MODEM2SLEEP_BACKUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_ACTIVE2SLEEP_BACKUP_EN` reader - need_des"] +pub type HP_ACTIVE2SLEEP_BACKUP_EN_R = crate::BitReader; +#[doc = "Field `HP_ACTIVE2SLEEP_BACKUP_EN` writer - need_des"] +pub type HP_ACTIVE2SLEEP_BACKUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 6:7 - need_des"] + #[inline(always)] + pub fn hp_modem2sleep_backup_modem_clk_code(&self) -> HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_R { + HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - need_des"] + #[inline(always)] + pub fn hp_active2sleep_backup_modem_clk_code(&self) -> HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_R { + HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + pub fn hp_sleep_retention_mode(&self) -> HP_SLEEP_RETENTION_MODE_R { + HP_SLEEP_RETENTION_MODE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + pub fn hp_modem2sleep_retention_en(&self) -> HP_MODEM2SLEEP_RETENTION_EN_R { + HP_MODEM2SLEEP_RETENTION_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn hp_active2sleep_retention_en(&self) -> HP_ACTIVE2SLEEP_RETENTION_EN_R { + HP_ACTIVE2SLEEP_RETENTION_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 16:17 - need_des"] + #[inline(always)] + pub fn hp_modem2sleep_backup_clk_sel(&self) -> HP_MODEM2SLEEP_BACKUP_CLK_SEL_R { + HP_MODEM2SLEEP_BACKUP_CLK_SEL_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - need_des"] + #[inline(always)] + pub fn hp_active2sleep_backup_clk_sel(&self) -> HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_R { + HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + pub fn hp_modem2sleep_backup_mode(&self) -> HP_MODEM2SLEEP_BACKUP_MODE_R { + HP_MODEM2SLEEP_BACKUP_MODE_R::new(((self.bits >> 23) & 7) as u8) + } + #[doc = "Bits 26:28 - need_des"] + #[inline(always)] + pub fn hp_active2sleep_backup_mode(&self) -> HP_ACTIVE2SLEEP_BACKUP_MODE_R { + HP_ACTIVE2SLEEP_BACKUP_MODE_R::new(((self.bits >> 26) & 7) as u8) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn hp_modem2sleep_backup_en(&self) -> HP_MODEM2SLEEP_BACKUP_EN_R { + HP_MODEM2SLEEP_BACKUP_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_active2sleep_backup_en(&self) -> HP_ACTIVE2SLEEP_BACKUP_EN_R { + HP_ACTIVE2SLEEP_BACKUP_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_BACKUP") + .field( + "hp_modem2sleep_backup_modem_clk_code", + &format_args!("{}", self.hp_modem2sleep_backup_modem_clk_code().bits()), + ) + .field( + "hp_active2sleep_backup_modem_clk_code", + &format_args!("{}", self.hp_active2sleep_backup_modem_clk_code().bits()), + ) + .field( + "hp_sleep_retention_mode", + &format_args!("{}", self.hp_sleep_retention_mode().bit()), + ) + .field( + "hp_modem2sleep_retention_en", + &format_args!("{}", self.hp_modem2sleep_retention_en().bit()), + ) + .field( + "hp_active2sleep_retention_en", + &format_args!("{}", self.hp_active2sleep_retention_en().bit()), + ) + .field( + "hp_modem2sleep_backup_clk_sel", + &format_args!("{}", self.hp_modem2sleep_backup_clk_sel().bits()), + ) + .field( + "hp_active2sleep_backup_clk_sel", + &format_args!("{}", self.hp_active2sleep_backup_clk_sel().bits()), + ) + .field( + "hp_modem2sleep_backup_mode", + &format_args!("{}", self.hp_modem2sleep_backup_mode().bits()), + ) + .field( + "hp_active2sleep_backup_mode", + &format_args!("{}", self.hp_active2sleep_backup_mode().bits()), + ) + .field( + "hp_modem2sleep_backup_en", + &format_args!("{}", self.hp_modem2sleep_backup_en().bit()), + ) + .field( + "hp_active2sleep_backup_en", + &format_args!("{}", self.hp_active2sleep_backup_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 6:7 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem2sleep_backup_modem_clk_code( + &mut self, + ) -> HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_W { + HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_W::new(self, 6) + } + #[doc = "Bits 8:9 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active2sleep_backup_modem_clk_code( + &mut self, + ) -> HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_W { + HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_W::new(self, 8) + } + #[doc = "Bit 10 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_retention_mode(&mut self) -> HP_SLEEP_RETENTION_MODE_W { + HP_SLEEP_RETENTION_MODE_W::new(self, 10) + } + #[doc = "Bit 12 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem2sleep_retention_en( + &mut self, + ) -> HP_MODEM2SLEEP_RETENTION_EN_W { + HP_MODEM2SLEEP_RETENTION_EN_W::new(self, 12) + } + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active2sleep_retention_en( + &mut self, + ) -> HP_ACTIVE2SLEEP_RETENTION_EN_W { + HP_ACTIVE2SLEEP_RETENTION_EN_W::new(self, 13) + } + #[doc = "Bits 16:17 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem2sleep_backup_clk_sel( + &mut self, + ) -> HP_MODEM2SLEEP_BACKUP_CLK_SEL_W { + HP_MODEM2SLEEP_BACKUP_CLK_SEL_W::new(self, 16) + } + #[doc = "Bits 18:19 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active2sleep_backup_clk_sel( + &mut self, + ) -> HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_W { + HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_W::new(self, 18) + } + #[doc = "Bits 23:25 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem2sleep_backup_mode( + &mut self, + ) -> HP_MODEM2SLEEP_BACKUP_MODE_W { + HP_MODEM2SLEEP_BACKUP_MODE_W::new(self, 23) + } + #[doc = "Bits 26:28 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active2sleep_backup_mode( + &mut self, + ) -> HP_ACTIVE2SLEEP_BACKUP_MODE_W { + HP_ACTIVE2SLEEP_BACKUP_MODE_W::new(self, 26) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_modem2sleep_backup_en(&mut self) -> HP_MODEM2SLEEP_BACKUP_EN_W { + HP_MODEM2SLEEP_BACKUP_EN_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_active2sleep_backup_en( + &mut self, + ) -> HP_ACTIVE2SLEEP_BACKUP_EN_W { + HP_ACTIVE2SLEEP_BACKUP_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_backup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_backup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_BACKUP_SPEC; +impl crate::RegisterSpec for HP_SLEEP_BACKUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_backup::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_BACKUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_backup::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_BACKUP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_BACKUP to value 0"] +impl crate::Resettable for HP_SLEEP_BACKUP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_backup_clk.rs b/esp32p4/src/pmu/hp_sleep_backup_clk.rs new file mode 100644 index 0000000000..e7705f783e --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_backup_clk.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_SLEEP_BACKUP_CLK` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_BACKUP_CLK` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_BACKUP_ICG_FUNC_EN` reader - need_des"] +pub type HP_SLEEP_BACKUP_ICG_FUNC_EN_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_BACKUP_ICG_FUNC_EN` writer - need_des"] +pub type HP_SLEEP_BACKUP_ICG_FUNC_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn hp_sleep_backup_icg_func_en(&self) -> HP_SLEEP_BACKUP_ICG_FUNC_EN_R { + HP_SLEEP_BACKUP_ICG_FUNC_EN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_BACKUP_CLK") + .field( + "hp_sleep_backup_icg_func_en", + &format_args!("{}", self.hp_sleep_backup_icg_func_en().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_backup_icg_func_en( + &mut self, + ) -> HP_SLEEP_BACKUP_ICG_FUNC_EN_W { + HP_SLEEP_BACKUP_ICG_FUNC_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_backup_clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_backup_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_BACKUP_CLK_SPEC; +impl crate::RegisterSpec for HP_SLEEP_BACKUP_CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_backup_clk::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_BACKUP_CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_backup_clk::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_BACKUP_CLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_BACKUP_CLK to value 0"] +impl crate::Resettable for HP_SLEEP_BACKUP_CLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_bias.rs b/esp32p4/src/pmu/hp_sleep_bias.rs new file mode 100644 index 0000000000..ac9e76a744 --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_bias.rs @@ -0,0 +1,158 @@ +#[doc = "Register `HP_SLEEP_BIAS` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_BIAS` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_DCM_VSET` reader - need_des"] +pub type HP_SLEEP_DCM_VSET_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_DCM_VSET` writer - need_des"] +pub type HP_SLEEP_DCM_VSET_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `HP_SLEEP_DCM_MODE` reader - need_des"] +pub type HP_SLEEP_DCM_MODE_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_DCM_MODE` writer - need_des"] +pub type HP_SLEEP_DCM_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_SLEEP_XPD_BIAS` reader - need_des"] +pub type HP_SLEEP_XPD_BIAS_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_XPD_BIAS` writer - need_des"] +pub type HP_SLEEP_XPD_BIAS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_DBG_ATTEN` reader - need_des"] +pub type HP_SLEEP_DBG_ATTEN_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_DBG_ATTEN` writer - need_des"] +pub type HP_SLEEP_DBG_ATTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_SLEEP_PD_CUR` reader - need_des"] +pub type HP_SLEEP_PD_CUR_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_PD_CUR` writer - need_des"] +pub type HP_SLEEP_PD_CUR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEP` reader - need_des"] +pub type SLEEP_R = crate::BitReader; +#[doc = "Field `SLEEP` writer - need_des"] +pub type SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + pub fn hp_sleep_dcm_vset(&self) -> HP_SLEEP_DCM_VSET_R { + HP_SLEEP_DCM_VSET_R::new(((self.bits >> 18) & 0x1f) as u8) + } + #[doc = "Bits 23:24 - need_des"] + #[inline(always)] + pub fn hp_sleep_dcm_mode(&self) -> HP_SLEEP_DCM_MODE_R { + HP_SLEEP_DCM_MODE_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn hp_sleep_xpd_bias(&self) -> HP_SLEEP_XPD_BIAS_R { + HP_SLEEP_XPD_BIAS_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 26:29 - need_des"] + #[inline(always)] + pub fn hp_sleep_dbg_atten(&self) -> HP_SLEEP_DBG_ATTEN_R { + HP_SLEEP_DBG_ATTEN_R::new(((self.bits >> 26) & 0x0f) as u8) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn hp_sleep_pd_cur(&self) -> HP_SLEEP_PD_CUR_R { + HP_SLEEP_PD_CUR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn sleep(&self) -> SLEEP_R { + SLEEP_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_BIAS") + .field( + "hp_sleep_dcm_vset", + &format_args!("{}", self.hp_sleep_dcm_vset().bits()), + ) + .field( + "hp_sleep_dcm_mode", + &format_args!("{}", self.hp_sleep_dcm_mode().bits()), + ) + .field( + "hp_sleep_xpd_bias", + &format_args!("{}", self.hp_sleep_xpd_bias().bit()), + ) + .field( + "hp_sleep_dbg_atten", + &format_args!("{}", self.hp_sleep_dbg_atten().bits()), + ) + .field( + "hp_sleep_pd_cur", + &format_args!("{}", self.hp_sleep_pd_cur().bit()), + ) + .field("sleep", &format_args!("{}", self.sleep().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dcm_vset(&mut self) -> HP_SLEEP_DCM_VSET_W { + HP_SLEEP_DCM_VSET_W::new(self, 18) + } + #[doc = "Bits 23:24 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dcm_mode(&mut self) -> HP_SLEEP_DCM_MODE_W { + HP_SLEEP_DCM_MODE_W::new(self, 23) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_xpd_bias(&mut self) -> HP_SLEEP_XPD_BIAS_W { + HP_SLEEP_XPD_BIAS_W::new(self, 25) + } + #[doc = "Bits 26:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dbg_atten(&mut self) -> HP_SLEEP_DBG_ATTEN_W { + HP_SLEEP_DBG_ATTEN_W::new(self, 26) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_pd_cur(&mut self) -> HP_SLEEP_PD_CUR_W { + HP_SLEEP_PD_CUR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep(&mut self) -> SLEEP_W { + SLEEP_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_bias::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_bias::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_BIAS_SPEC; +impl crate::RegisterSpec for HP_SLEEP_BIAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_bias::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_BIAS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_bias::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_BIAS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_BIAS to value 0x0050_0000"] +impl crate::Resettable for HP_SLEEP_BIAS_SPEC { + const RESET_VALUE: Self::Ux = 0x0050_0000; +} diff --git a/esp32p4/src/pmu/hp_sleep_dig_power.rs b/esp32p4/src/pmu/hp_sleep_dig_power.rs new file mode 100644 index 0000000000..a38b52419c --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_dig_power.rs @@ -0,0 +1,146 @@ +#[doc = "Register `HP_SLEEP_DIG_POWER` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_DIG_POWER` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_DCDC_SWITCH_PD_EN` reader - need_des"] +pub type HP_SLEEP_DCDC_SWITCH_PD_EN_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_DCDC_SWITCH_PD_EN` writer - need_des"] +pub type HP_SLEEP_DCDC_SWITCH_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_HP_MEM_DSLP` reader - need_des"] +pub type HP_SLEEP_HP_MEM_DSLP_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_HP_MEM_DSLP` writer - need_des"] +pub type HP_SLEEP_HP_MEM_DSLP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_PD_HP_MEM_PD_EN` reader - need_des"] +pub type HP_SLEEP_PD_HP_MEM_PD_EN_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_PD_HP_MEM_PD_EN` writer - need_des"] +pub type HP_SLEEP_PD_HP_MEM_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_PD_CNNT_PD_EN` reader - need_des"] +pub type HP_SLEEP_PD_CNNT_PD_EN_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_PD_CNNT_PD_EN` writer - need_des"] +pub type HP_SLEEP_PD_CNNT_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_PD_TOP_PD_EN` reader - need_des"] +pub type HP_SLEEP_PD_TOP_PD_EN_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_PD_TOP_PD_EN` writer - need_des"] +pub type HP_SLEEP_PD_TOP_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + pub fn hp_sleep_dcdc_switch_pd_en(&self) -> HP_SLEEP_DCDC_SWITCH_PD_EN_R { + HP_SLEEP_DCDC_SWITCH_PD_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + pub fn hp_sleep_hp_mem_dslp(&self) -> HP_SLEEP_HP_MEM_DSLP_R { + HP_SLEEP_HP_MEM_DSLP_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - need_des"] + #[inline(always)] + pub fn hp_sleep_pd_hp_mem_pd_en(&self) -> HP_SLEEP_PD_HP_MEM_PD_EN_R { + HP_SLEEP_PD_HP_MEM_PD_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn hp_sleep_pd_cnnt_pd_en(&self) -> HP_SLEEP_PD_CNNT_PD_EN_R { + HP_SLEEP_PD_CNNT_PD_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_sleep_pd_top_pd_en(&self) -> HP_SLEEP_PD_TOP_PD_EN_R { + HP_SLEEP_PD_TOP_PD_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_DIG_POWER") + .field( + "hp_sleep_dcdc_switch_pd_en", + &format_args!("{}", self.hp_sleep_dcdc_switch_pd_en().bit()), + ) + .field( + "hp_sleep_hp_mem_dslp", + &format_args!("{}", self.hp_sleep_hp_mem_dslp().bit()), + ) + .field( + "hp_sleep_pd_hp_mem_pd_en", + &format_args!("{}", self.hp_sleep_pd_hp_mem_pd_en().bit()), + ) + .field( + "hp_sleep_pd_cnnt_pd_en", + &format_args!("{}", self.hp_sleep_pd_cnnt_pd_en().bit()), + ) + .field( + "hp_sleep_pd_top_pd_en", + &format_args!("{}", self.hp_sleep_pd_top_pd_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dcdc_switch_pd_en( + &mut self, + ) -> HP_SLEEP_DCDC_SWITCH_PD_EN_W { + HP_SLEEP_DCDC_SWITCH_PD_EN_W::new(self, 21) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_hp_mem_dslp(&mut self) -> HP_SLEEP_HP_MEM_DSLP_W { + HP_SLEEP_HP_MEM_DSLP_W::new(self, 22) + } + #[doc = "Bit 23 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_pd_hp_mem_pd_en( + &mut self, + ) -> HP_SLEEP_PD_HP_MEM_PD_EN_W { + HP_SLEEP_PD_HP_MEM_PD_EN_W::new(self, 23) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_pd_cnnt_pd_en(&mut self) -> HP_SLEEP_PD_CNNT_PD_EN_W { + HP_SLEEP_PD_CNNT_PD_EN_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_pd_top_pd_en(&mut self) -> HP_SLEEP_PD_TOP_PD_EN_W { + HP_SLEEP_PD_TOP_PD_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_dig_power::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_dig_power::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_DIG_POWER_SPEC; +impl crate::RegisterSpec for HP_SLEEP_DIG_POWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_dig_power::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_DIG_POWER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_dig_power::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_DIG_POWER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_DIG_POWER to value 0"] +impl crate::Resettable for HP_SLEEP_DIG_POWER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_hp_ck_power.rs b/esp32p4/src/pmu/hp_sleep_hp_ck_power.rs new file mode 100644 index 0000000000..21a3b56698 --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_hp_ck_power.rs @@ -0,0 +1,125 @@ +#[doc = "Register `HP_SLEEP_HP_CK_POWER` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_HP_CK_POWER` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_I2C_ISO_EN` reader - need_des"] +pub type HP_SLEEP_I2C_ISO_EN_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_I2C_ISO_EN` writer - need_des"] +pub type HP_SLEEP_I2C_ISO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_I2C_RETENTION` reader - need_des"] +pub type HP_SLEEP_I2C_RETENTION_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_I2C_RETENTION` writer - need_des"] +pub type HP_SLEEP_I2C_RETENTION_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_XPD_PLL_I2C` reader - need_des"] +pub type HP_SLEEP_XPD_PLL_I2C_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_XPD_PLL_I2C` writer - need_des"] +pub type HP_SLEEP_XPD_PLL_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_SLEEP_XPD_PLL` reader - need_des"] +pub type HP_SLEEP_XPD_PLL_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_XPD_PLL` writer - need_des"] +pub type HP_SLEEP_XPD_PLL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + pub fn hp_sleep_i2c_iso_en(&self) -> HP_SLEEP_I2C_ISO_EN_R { + HP_SLEEP_I2C_ISO_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + pub fn hp_sleep_i2c_retention(&self) -> HP_SLEEP_I2C_RETENTION_R { + HP_SLEEP_I2C_RETENTION_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + pub fn hp_sleep_xpd_pll_i2c(&self) -> HP_SLEEP_XPD_PLL_I2C_R { + HP_SLEEP_XPD_PLL_I2C_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bits 27:30 - need_des"] + #[inline(always)] + pub fn hp_sleep_xpd_pll(&self) -> HP_SLEEP_XPD_PLL_R { + HP_SLEEP_XPD_PLL_R::new(((self.bits >> 27) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_HP_CK_POWER") + .field( + "hp_sleep_i2c_iso_en", + &format_args!("{}", self.hp_sleep_i2c_iso_en().bit()), + ) + .field( + "hp_sleep_i2c_retention", + &format_args!("{}", self.hp_sleep_i2c_retention().bit()), + ) + .field( + "hp_sleep_xpd_pll_i2c", + &format_args!("{}", self.hp_sleep_xpd_pll_i2c().bits()), + ) + .field( + "hp_sleep_xpd_pll", + &format_args!("{}", self.hp_sleep_xpd_pll().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_i2c_iso_en(&mut self) -> HP_SLEEP_I2C_ISO_EN_W { + HP_SLEEP_I2C_ISO_EN_W::new(self, 21) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_i2c_retention( + &mut self, + ) -> HP_SLEEP_I2C_RETENTION_W { + HP_SLEEP_I2C_RETENTION_W::new(self, 22) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_xpd_pll_i2c(&mut self) -> HP_SLEEP_XPD_PLL_I2C_W { + HP_SLEEP_XPD_PLL_I2C_W::new(self, 23) + } + #[doc = "Bits 27:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_xpd_pll(&mut self) -> HP_SLEEP_XPD_PLL_W { + HP_SLEEP_XPD_PLL_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_hp_ck_power::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_hp_ck_power::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_HP_CK_POWER_SPEC; +impl crate::RegisterSpec for HP_SLEEP_HP_CK_POWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_hp_ck_power::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_HP_CK_POWER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_hp_ck_power::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_HP_CK_POWER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_HP_CK_POWER to value 0"] +impl crate::Resettable for HP_SLEEP_HP_CK_POWER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_hp_regulator0.rs b/esp32p4/src/pmu/hp_sleep_hp_regulator0.rs new file mode 100644 index 0000000000..da44fb75a7 --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_hp_regulator0.rs @@ -0,0 +1,173 @@ +#[doc = "Register `HP_SLEEP_HP_REGULATOR0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_HP_REGULATOR0` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD` reader - need_des"] +pub type HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD` writer - need_des"] +pub type HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD` reader - need_des"] +pub type HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD` writer - need_des"] +pub type HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_XPD` reader - need_des"] +pub type HP_SLEEP_HP_REGULATOR_XPD_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_XPD` writer - need_des"] +pub type HP_SLEEP_HP_REGULATOR_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS` reader - need_des"] +pub type HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS` writer - need_des"] +pub type HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS` reader - need_des"] +pub type HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS` writer - need_des"] +pub type HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_DBIAS` reader - need_des"] +pub type HP_SLEEP_HP_REGULATOR_DBIAS_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_DBIAS` writer - need_des"] +pub type HP_SLEEP_HP_REGULATOR_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bit 16 - need_des"] + #[inline(always)] + pub fn hp_sleep_hp_regulator_slp_mem_xpd(&self) -> HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_R { + HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - need_des"] + #[inline(always)] + pub fn hp_sleep_hp_regulator_slp_logic_xpd(&self) -> HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_R { + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - need_des"] + #[inline(always)] + pub fn hp_sleep_hp_regulator_xpd(&self) -> HP_SLEEP_HP_REGULATOR_XPD_R { + HP_SLEEP_HP_REGULATOR_XPD_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + pub fn hp_sleep_hp_regulator_slp_mem_dbias(&self) -> HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_R { + HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_R::new(((self.bits >> 19) & 0x0f) as u8) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + pub fn hp_sleep_hp_regulator_slp_logic_dbias(&self) -> HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_R { + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + pub fn hp_sleep_hp_regulator_dbias(&self) -> HP_SLEEP_HP_REGULATOR_DBIAS_R { + HP_SLEEP_HP_REGULATOR_DBIAS_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_HP_REGULATOR0") + .field( + "hp_sleep_hp_regulator_slp_mem_xpd", + &format_args!("{}", self.hp_sleep_hp_regulator_slp_mem_xpd().bit()), + ) + .field( + "hp_sleep_hp_regulator_slp_logic_xpd", + &format_args!("{}", self.hp_sleep_hp_regulator_slp_logic_xpd().bit()), + ) + .field( + "hp_sleep_hp_regulator_xpd", + &format_args!("{}", self.hp_sleep_hp_regulator_xpd().bit()), + ) + .field( + "hp_sleep_hp_regulator_slp_mem_dbias", + &format_args!("{}", self.hp_sleep_hp_regulator_slp_mem_dbias().bits()), + ) + .field( + "hp_sleep_hp_regulator_slp_logic_dbias", + &format_args!("{}", self.hp_sleep_hp_regulator_slp_logic_dbias().bits()), + ) + .field( + "hp_sleep_hp_regulator_dbias", + &format_args!("{}", self.hp_sleep_hp_regulator_dbias().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 16 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_hp_regulator_slp_mem_xpd( + &mut self, + ) -> HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_W { + HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_W::new(self, 16) + } + #[doc = "Bit 17 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_hp_regulator_slp_logic_xpd( + &mut self, + ) -> HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_W { + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_W::new(self, 17) + } + #[doc = "Bit 18 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_hp_regulator_xpd( + &mut self, + ) -> HP_SLEEP_HP_REGULATOR_XPD_W { + HP_SLEEP_HP_REGULATOR_XPD_W::new(self, 18) + } + #[doc = "Bits 19:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_hp_regulator_slp_mem_dbias( + &mut self, + ) -> HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_W { + HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_W::new(self, 19) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_hp_regulator_slp_logic_dbias( + &mut self, + ) -> HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_W { + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_W::new(self, 23) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_hp_regulator_dbias( + &mut self, + ) -> HP_SLEEP_HP_REGULATOR_DBIAS_W { + HP_SLEEP_HP_REGULATOR_DBIAS_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_hp_regulator0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_hp_regulator0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_HP_REGULATOR0_SPEC; +impl crate::RegisterSpec for HP_SLEEP_HP_REGULATOR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_hp_regulator0::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_HP_REGULATOR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_hp_regulator0::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_HP_REGULATOR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_HP_REGULATOR0 to value 0xc667_0000"] +impl crate::Resettable for HP_SLEEP_HP_REGULATOR0_SPEC { + const RESET_VALUE: Self::Ux = 0xc667_0000; +} diff --git a/esp32p4/src/pmu/hp_sleep_hp_regulator1.rs b/esp32p4/src/pmu/hp_sleep_hp_regulator1.rs new file mode 100644 index 0000000000..63a586e627 --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_hp_regulator1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_SLEEP_HP_REGULATOR1` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_HP_REGULATOR1` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_DRV_B` reader - need_des"] +pub type HP_SLEEP_HP_REGULATOR_DRV_B_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_HP_REGULATOR_DRV_B` writer - need_des"] +pub type HP_SLEEP_HP_REGULATOR_DRV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 26:31 - need_des"] + #[inline(always)] + pub fn hp_sleep_hp_regulator_drv_b(&self) -> HP_SLEEP_HP_REGULATOR_DRV_B_R { + HP_SLEEP_HP_REGULATOR_DRV_B_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_HP_REGULATOR1") + .field( + "hp_sleep_hp_regulator_drv_b", + &format_args!("{}", self.hp_sleep_hp_regulator_drv_b().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 26:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_hp_regulator_drv_b( + &mut self, + ) -> HP_SLEEP_HP_REGULATOR_DRV_B_W { + HP_SLEEP_HP_REGULATOR_DRV_B_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_hp_regulator1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_hp_regulator1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_HP_REGULATOR1_SPEC; +impl crate::RegisterSpec for HP_SLEEP_HP_REGULATOR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_hp_regulator1::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_HP_REGULATOR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_hp_regulator1::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_HP_REGULATOR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_HP_REGULATOR1 to value 0"] +impl crate::Resettable for HP_SLEEP_HP_REGULATOR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_hp_sys_cntl.rs b/esp32p4/src/pmu/hp_sleep_hp_sys_cntl.rs new file mode 100644 index 0000000000..1c9a2b1ac4 --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_hp_sys_cntl.rs @@ -0,0 +1,194 @@ +#[doc = "Register `HP_SLEEP_HP_SYS_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_HP_SYS_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_HP_POWER_DET_BYPASS` reader - need_des"] +pub type HP_SLEEP_HP_POWER_DET_BYPASS_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_HP_POWER_DET_BYPASS` writer - need_des"] +pub type HP_SLEEP_HP_POWER_DET_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_UART_WAKEUP_EN` reader - need_des"] +pub type HP_SLEEP_UART_WAKEUP_EN_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_UART_WAKEUP_EN` writer - need_des"] +pub type HP_SLEEP_UART_WAKEUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_LP_PAD_HOLD_ALL` reader - need_des"] +pub type HP_SLEEP_LP_PAD_HOLD_ALL_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_LP_PAD_HOLD_ALL` writer - need_des"] +pub type HP_SLEEP_LP_PAD_HOLD_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_HP_PAD_HOLD_ALL` reader - need_des"] +pub type HP_SLEEP_HP_PAD_HOLD_ALL_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_HP_PAD_HOLD_ALL` writer - need_des"] +pub type HP_SLEEP_HP_PAD_HOLD_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_DIG_PAD_SLP_SEL` reader - need_des"] +pub type HP_SLEEP_DIG_PAD_SLP_SEL_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_DIG_PAD_SLP_SEL` writer - need_des"] +pub type HP_SLEEP_DIG_PAD_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_DIG_PAUSE_WDT` reader - need_des"] +pub type HP_SLEEP_DIG_PAUSE_WDT_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_DIG_PAUSE_WDT` writer - need_des"] +pub type HP_SLEEP_DIG_PAUSE_WDT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_DIG_CPU_STALL` reader - need_des"] +pub type HP_SLEEP_DIG_CPU_STALL_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_DIG_CPU_STALL` writer - need_des"] +pub type HP_SLEEP_DIG_CPU_STALL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 23 - need_des"] + #[inline(always)] + pub fn hp_sleep_hp_power_det_bypass(&self) -> HP_SLEEP_HP_POWER_DET_BYPASS_R { + HP_SLEEP_HP_POWER_DET_BYPASS_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + pub fn hp_sleep_uart_wakeup_en(&self) -> HP_SLEEP_UART_WAKEUP_EN_R { + HP_SLEEP_UART_WAKEUP_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn hp_sleep_lp_pad_hold_all(&self) -> HP_SLEEP_LP_PAD_HOLD_ALL_R { + HP_SLEEP_LP_PAD_HOLD_ALL_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn hp_sleep_hp_pad_hold_all(&self) -> HP_SLEEP_HP_PAD_HOLD_ALL_R { + HP_SLEEP_HP_PAD_HOLD_ALL_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn hp_sleep_dig_pad_slp_sel(&self) -> HP_SLEEP_DIG_PAD_SLP_SEL_R { + HP_SLEEP_DIG_PAD_SLP_SEL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn hp_sleep_dig_pause_wdt(&self) -> HP_SLEEP_DIG_PAUSE_WDT_R { + HP_SLEEP_DIG_PAUSE_WDT_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn hp_sleep_dig_cpu_stall(&self) -> HP_SLEEP_DIG_CPU_STALL_R { + HP_SLEEP_DIG_CPU_STALL_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_HP_SYS_CNTL") + .field( + "hp_sleep_hp_power_det_bypass", + &format_args!("{}", self.hp_sleep_hp_power_det_bypass().bit()), + ) + .field( + "hp_sleep_uart_wakeup_en", + &format_args!("{}", self.hp_sleep_uart_wakeup_en().bit()), + ) + .field( + "hp_sleep_lp_pad_hold_all", + &format_args!("{}", self.hp_sleep_lp_pad_hold_all().bit()), + ) + .field( + "hp_sleep_hp_pad_hold_all", + &format_args!("{}", self.hp_sleep_hp_pad_hold_all().bit()), + ) + .field( + "hp_sleep_dig_pad_slp_sel", + &format_args!("{}", self.hp_sleep_dig_pad_slp_sel().bit()), + ) + .field( + "hp_sleep_dig_pause_wdt", + &format_args!("{}", self.hp_sleep_dig_pause_wdt().bit()), + ) + .field( + "hp_sleep_dig_cpu_stall", + &format_args!("{}", self.hp_sleep_dig_cpu_stall().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 23 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_hp_power_det_bypass( + &mut self, + ) -> HP_SLEEP_HP_POWER_DET_BYPASS_W { + HP_SLEEP_HP_POWER_DET_BYPASS_W::new(self, 23) + } + #[doc = "Bit 24 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_uart_wakeup_en( + &mut self, + ) -> HP_SLEEP_UART_WAKEUP_EN_W { + HP_SLEEP_UART_WAKEUP_EN_W::new(self, 24) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_lp_pad_hold_all( + &mut self, + ) -> HP_SLEEP_LP_PAD_HOLD_ALL_W { + HP_SLEEP_LP_PAD_HOLD_ALL_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_hp_pad_hold_all( + &mut self, + ) -> HP_SLEEP_HP_PAD_HOLD_ALL_W { + HP_SLEEP_HP_PAD_HOLD_ALL_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dig_pad_slp_sel( + &mut self, + ) -> HP_SLEEP_DIG_PAD_SLP_SEL_W { + HP_SLEEP_DIG_PAD_SLP_SEL_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dig_pause_wdt( + &mut self, + ) -> HP_SLEEP_DIG_PAUSE_WDT_W { + HP_SLEEP_DIG_PAUSE_WDT_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dig_cpu_stall( + &mut self, + ) -> HP_SLEEP_DIG_CPU_STALL_W { + HP_SLEEP_DIG_CPU_STALL_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_hp_sys_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_hp_sys_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_HP_SYS_CNTL_SPEC; +impl crate::RegisterSpec for HP_SLEEP_HP_SYS_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_hp_sys_cntl::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_HP_SYS_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_hp_sys_cntl::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_HP_SYS_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_HP_SYS_CNTL to value 0"] +impl crate::Resettable for HP_SLEEP_HP_SYS_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_icg_hp_apb.rs b/esp32p4/src/pmu/hp_sleep_icg_hp_apb.rs new file mode 100644 index 0000000000..77717057f6 --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_icg_hp_apb.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_SLEEP_ICG_HP_APB` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_ICG_HP_APB` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_DIG_ICG_APB_EN` reader - need_des"] +pub type HP_SLEEP_DIG_ICG_APB_EN_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_DIG_ICG_APB_EN` writer - need_des"] +pub type HP_SLEEP_DIG_ICG_APB_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn hp_sleep_dig_icg_apb_en(&self) -> HP_SLEEP_DIG_ICG_APB_EN_R { + HP_SLEEP_DIG_ICG_APB_EN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_ICG_HP_APB") + .field( + "hp_sleep_dig_icg_apb_en", + &format_args!("{}", self.hp_sleep_dig_icg_apb_en().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dig_icg_apb_en( + &mut self, + ) -> HP_SLEEP_DIG_ICG_APB_EN_W { + HP_SLEEP_DIG_ICG_APB_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_icg_hp_apb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_icg_hp_apb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_ICG_HP_APB_SPEC; +impl crate::RegisterSpec for HP_SLEEP_ICG_HP_APB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_icg_hp_apb::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_ICG_HP_APB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_icg_hp_apb::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_ICG_HP_APB_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_ICG_HP_APB to value 0xffff_ffff"] +impl crate::Resettable for HP_SLEEP_ICG_HP_APB_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/pmu/hp_sleep_icg_hp_func.rs b/esp32p4/src/pmu/hp_sleep_icg_hp_func.rs new file mode 100644 index 0000000000..2538cdadad --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_icg_hp_func.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_SLEEP_ICG_HP_FUNC` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_ICG_HP_FUNC` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_DIG_ICG_FUNC_EN` reader - need_des"] +pub type HP_SLEEP_DIG_ICG_FUNC_EN_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_DIG_ICG_FUNC_EN` writer - need_des"] +pub type HP_SLEEP_DIG_ICG_FUNC_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + pub fn hp_sleep_dig_icg_func_en(&self) -> HP_SLEEP_DIG_ICG_FUNC_EN_R { + HP_SLEEP_DIG_ICG_FUNC_EN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_ICG_HP_FUNC") + .field( + "hp_sleep_dig_icg_func_en", + &format_args!("{}", self.hp_sleep_dig_icg_func_en().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dig_icg_func_en( + &mut self, + ) -> HP_SLEEP_DIG_ICG_FUNC_EN_W { + HP_SLEEP_DIG_ICG_FUNC_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_icg_hp_func::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_icg_hp_func::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_ICG_HP_FUNC_SPEC; +impl crate::RegisterSpec for HP_SLEEP_ICG_HP_FUNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_icg_hp_func::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_ICG_HP_FUNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_icg_hp_func::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_ICG_HP_FUNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_ICG_HP_FUNC to value 0xffff_ffff"] +impl crate::Resettable for HP_SLEEP_ICG_HP_FUNC_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/pmu/hp_sleep_icg_modem.rs b/esp32p4/src/pmu/hp_sleep_icg_modem.rs new file mode 100644 index 0000000000..7800cd20df --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_icg_modem.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_SLEEP_ICG_MODEM` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_ICG_MODEM` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_DIG_ICG_MODEM_CODE` reader - need_des"] +pub type HP_SLEEP_DIG_ICG_MODEM_CODE_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_DIG_ICG_MODEM_CODE` writer - need_des"] +pub type HP_SLEEP_DIG_ICG_MODEM_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + pub fn hp_sleep_dig_icg_modem_code(&self) -> HP_SLEEP_DIG_ICG_MODEM_CODE_R { + HP_SLEEP_DIG_ICG_MODEM_CODE_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_ICG_MODEM") + .field( + "hp_sleep_dig_icg_modem_code", + &format_args!("{}", self.hp_sleep_dig_icg_modem_code().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dig_icg_modem_code( + &mut self, + ) -> HP_SLEEP_DIG_ICG_MODEM_CODE_W { + HP_SLEEP_DIG_ICG_MODEM_CODE_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_icg_modem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_icg_modem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_ICG_MODEM_SPEC; +impl crate::RegisterSpec for HP_SLEEP_ICG_MODEM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_icg_modem::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_ICG_MODEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_icg_modem::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_ICG_MODEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_ICG_MODEM to value 0"] +impl crate::Resettable for HP_SLEEP_ICG_MODEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_lp_ck_power.rs b/esp32p4/src/pmu/hp_sleep_lp_ck_power.rs new file mode 100644 index 0000000000..774c23a504 --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_lp_ck_power.rs @@ -0,0 +1,142 @@ +#[doc = "Register `HP_SLEEP_LP_CK_POWER` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_LP_CK_POWER` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_XPD_LPPLL` reader - need_des"] +pub type HP_SLEEP_XPD_LPPLL_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_XPD_LPPLL` writer - need_des"] +pub type HP_SLEEP_XPD_LPPLL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_XPD_XTAL32K` reader - need_des"] +pub type HP_SLEEP_XPD_XTAL32K_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_XPD_XTAL32K` writer - need_des"] +pub type HP_SLEEP_XPD_XTAL32K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_XPD_RC32K` reader - need_des"] +pub type HP_SLEEP_XPD_RC32K_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_XPD_RC32K` writer - need_des"] +pub type HP_SLEEP_XPD_RC32K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_XPD_FOSC_CLK` reader - need_des"] +pub type HP_SLEEP_XPD_FOSC_CLK_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_XPD_FOSC_CLK` writer - need_des"] +pub type HP_SLEEP_XPD_FOSC_CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_PD_OSC_CLK` reader - need_des"] +pub type HP_SLEEP_PD_OSC_CLK_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_PD_OSC_CLK` writer - need_des"] +pub type HP_SLEEP_PD_OSC_CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn hp_sleep_xpd_lppll(&self) -> HP_SLEEP_XPD_LPPLL_R { + HP_SLEEP_XPD_LPPLL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn hp_sleep_xpd_xtal32k(&self) -> HP_SLEEP_XPD_XTAL32K_R { + HP_SLEEP_XPD_XTAL32K_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn hp_sleep_xpd_rc32k(&self) -> HP_SLEEP_XPD_RC32K_R { + HP_SLEEP_XPD_RC32K_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn hp_sleep_xpd_fosc_clk(&self) -> HP_SLEEP_XPD_FOSC_CLK_R { + HP_SLEEP_XPD_FOSC_CLK_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_sleep_pd_osc_clk(&self) -> HP_SLEEP_PD_OSC_CLK_R { + HP_SLEEP_PD_OSC_CLK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_LP_CK_POWER") + .field( + "hp_sleep_xpd_lppll", + &format_args!("{}", self.hp_sleep_xpd_lppll().bit()), + ) + .field( + "hp_sleep_xpd_xtal32k", + &format_args!("{}", self.hp_sleep_xpd_xtal32k().bit()), + ) + .field( + "hp_sleep_xpd_rc32k", + &format_args!("{}", self.hp_sleep_xpd_rc32k().bit()), + ) + .field( + "hp_sleep_xpd_fosc_clk", + &format_args!("{}", self.hp_sleep_xpd_fosc_clk().bit()), + ) + .field( + "hp_sleep_pd_osc_clk", + &format_args!("{}", self.hp_sleep_pd_osc_clk().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_xpd_lppll(&mut self) -> HP_SLEEP_XPD_LPPLL_W { + HP_SLEEP_XPD_LPPLL_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_xpd_xtal32k(&mut self) -> HP_SLEEP_XPD_XTAL32K_W { + HP_SLEEP_XPD_XTAL32K_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_xpd_rc32k(&mut self) -> HP_SLEEP_XPD_RC32K_W { + HP_SLEEP_XPD_RC32K_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_xpd_fosc_clk(&mut self) -> HP_SLEEP_XPD_FOSC_CLK_W { + HP_SLEEP_XPD_FOSC_CLK_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_pd_osc_clk(&mut self) -> HP_SLEEP_PD_OSC_CLK_W { + HP_SLEEP_PD_OSC_CLK_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_lp_ck_power::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_lp_ck_power::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_LP_CK_POWER_SPEC; +impl crate::RegisterSpec for HP_SLEEP_LP_CK_POWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_lp_ck_power::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_LP_CK_POWER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_lp_ck_power::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_LP_CK_POWER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_LP_CK_POWER to value 0x4000_0000"] +impl crate::Resettable for HP_SLEEP_LP_CK_POWER_SPEC { + const RESET_VALUE: Self::Ux = 0x4000_0000; +} diff --git a/esp32p4/src/pmu/hp_sleep_lp_dcdc_reserve.rs b/esp32p4/src/pmu/hp_sleep_lp_dcdc_reserve.rs new file mode 100644 index 0000000000..f373adb641 --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_lp_dcdc_reserve.rs @@ -0,0 +1,44 @@ +#[doc = "Register `HP_SLEEP_LP_DCDC_RESERVE` writer"] +pub type W = crate::W; +#[doc = "Field `PMU_HP_SLEEP_LP_DCDC_RESERVE` writer - need_des"] +pub type PMU_HP_SLEEP_LP_DCDC_RESERVE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn pmu_hp_sleep_lp_dcdc_reserve( + &mut self, + ) -> PMU_HP_SLEEP_LP_DCDC_RESERVE_W { + PMU_HP_SLEEP_LP_DCDC_RESERVE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_lp_dcdc_reserve::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_LP_DCDC_RESERVE_SPEC; +impl crate::RegisterSpec for HP_SLEEP_LP_DCDC_RESERVE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_lp_dcdc_reserve::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_LP_DCDC_RESERVE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_LP_DCDC_RESERVE to value 0"] +impl crate::Resettable for HP_SLEEP_LP_DCDC_RESERVE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_lp_dig_power.rs b/esp32p4/src/pmu/hp_sleep_lp_dig_power.rs new file mode 100644 index 0000000000..f950259ad4 --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_lp_dig_power.rs @@ -0,0 +1,148 @@ +#[doc = "Register `HP_SLEEP_LP_DIG_POWER` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_LP_DIG_POWER` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_LP_PAD_SLP_SEL` reader - need_des"] +pub type HP_SLEEP_LP_PAD_SLP_SEL_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_LP_PAD_SLP_SEL` writer - need_des"] +pub type HP_SLEEP_LP_PAD_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_BOD_SOURCE_SEL` reader - need_des"] +pub type HP_SLEEP_BOD_SOURCE_SEL_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_BOD_SOURCE_SEL` writer - need_des"] +pub type HP_SLEEP_BOD_SOURCE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_VDDBAT_MODE` reader - need_des"] +pub type HP_SLEEP_VDDBAT_MODE_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_VDDBAT_MODE` writer - need_des"] +pub type HP_SLEEP_VDDBAT_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HP_SLEEP_LP_MEM_DSLP` reader - need_des"] +pub type HP_SLEEP_LP_MEM_DSLP_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_LP_MEM_DSLP` writer - need_des"] +pub type HP_SLEEP_LP_MEM_DSLP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_PD_LP_PERI_PD_EN` reader - need_des"] +pub type HP_SLEEP_PD_LP_PERI_PD_EN_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_PD_LP_PERI_PD_EN` writer - need_des"] +pub type HP_SLEEP_PD_LP_PERI_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn hp_sleep_lp_pad_slp_sel(&self) -> HP_SLEEP_LP_PAD_SLP_SEL_R { + HP_SLEEP_LP_PAD_SLP_SEL_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn hp_sleep_bod_source_sel(&self) -> HP_SLEEP_BOD_SOURCE_SEL_R { + HP_SLEEP_BOD_SOURCE_SEL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:29 - need_des"] + #[inline(always)] + pub fn hp_sleep_vddbat_mode(&self) -> HP_SLEEP_VDDBAT_MODE_R { + HP_SLEEP_VDDBAT_MODE_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn hp_sleep_lp_mem_dslp(&self) -> HP_SLEEP_LP_MEM_DSLP_R { + HP_SLEEP_LP_MEM_DSLP_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_sleep_pd_lp_peri_pd_en(&self) -> HP_SLEEP_PD_LP_PERI_PD_EN_R { + HP_SLEEP_PD_LP_PERI_PD_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_LP_DIG_POWER") + .field( + "hp_sleep_lp_pad_slp_sel", + &format_args!("{}", self.hp_sleep_lp_pad_slp_sel().bit()), + ) + .field( + "hp_sleep_bod_source_sel", + &format_args!("{}", self.hp_sleep_bod_source_sel().bit()), + ) + .field( + "hp_sleep_vddbat_mode", + &format_args!("{}", self.hp_sleep_vddbat_mode().bits()), + ) + .field( + "hp_sleep_lp_mem_dslp", + &format_args!("{}", self.hp_sleep_lp_mem_dslp().bit()), + ) + .field( + "hp_sleep_pd_lp_peri_pd_en", + &format_args!("{}", self.hp_sleep_pd_lp_peri_pd_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_lp_pad_slp_sel( + &mut self, + ) -> HP_SLEEP_LP_PAD_SLP_SEL_W { + HP_SLEEP_LP_PAD_SLP_SEL_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_bod_source_sel( + &mut self, + ) -> HP_SLEEP_BOD_SOURCE_SEL_W { + HP_SLEEP_BOD_SOURCE_SEL_W::new(self, 27) + } + #[doc = "Bits 28:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_vddbat_mode(&mut self) -> HP_SLEEP_VDDBAT_MODE_W { + HP_SLEEP_VDDBAT_MODE_W::new(self, 28) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_lp_mem_dslp(&mut self) -> HP_SLEEP_LP_MEM_DSLP_W { + HP_SLEEP_LP_MEM_DSLP_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_pd_lp_peri_pd_en( + &mut self, + ) -> HP_SLEEP_PD_LP_PERI_PD_EN_W { + HP_SLEEP_PD_LP_PERI_PD_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_lp_dig_power::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_lp_dig_power::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_LP_DIG_POWER_SPEC; +impl crate::RegisterSpec for HP_SLEEP_LP_DIG_POWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_lp_dig_power::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_LP_DIG_POWER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_lp_dig_power::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_LP_DIG_POWER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_LP_DIG_POWER to value 0"] +impl crate::Resettable for HP_SLEEP_LP_DIG_POWER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_lp_regulator0.rs b/esp32p4/src/pmu/hp_sleep_lp_regulator0.rs new file mode 100644 index 0000000000..db6c325b45 --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_lp_regulator0.rs @@ -0,0 +1,131 @@ +#[doc = "Register `HP_SLEEP_LP_REGULATOR0` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_LP_REGULATOR0` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_LP_REGULATOR_SLP_XPD` reader - need_des"] +pub type HP_SLEEP_LP_REGULATOR_SLP_XPD_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_LP_REGULATOR_SLP_XPD` writer - need_des"] +pub type HP_SLEEP_LP_REGULATOR_SLP_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_LP_REGULATOR_XPD` reader - need_des"] +pub type HP_SLEEP_LP_REGULATOR_XPD_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_LP_REGULATOR_XPD` writer - need_des"] +pub type HP_SLEEP_LP_REGULATOR_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_LP_REGULATOR_SLP_DBIAS` reader - need_des"] +pub type HP_SLEEP_LP_REGULATOR_SLP_DBIAS_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_LP_REGULATOR_SLP_DBIAS` writer - need_des"] +pub type HP_SLEEP_LP_REGULATOR_SLP_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HP_SLEEP_LP_REGULATOR_DBIAS` reader - need_des"] +pub type HP_SLEEP_LP_REGULATOR_DBIAS_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_LP_REGULATOR_DBIAS` writer - need_des"] +pub type HP_SLEEP_LP_REGULATOR_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + pub fn hp_sleep_lp_regulator_slp_xpd(&self) -> HP_SLEEP_LP_REGULATOR_SLP_XPD_R { + HP_SLEEP_LP_REGULATOR_SLP_XPD_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + pub fn hp_sleep_lp_regulator_xpd(&self) -> HP_SLEEP_LP_REGULATOR_XPD_R { + HP_SLEEP_LP_REGULATOR_XPD_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + pub fn hp_sleep_lp_regulator_slp_dbias(&self) -> HP_SLEEP_LP_REGULATOR_SLP_DBIAS_R { + HP_SLEEP_LP_REGULATOR_SLP_DBIAS_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + pub fn hp_sleep_lp_regulator_dbias(&self) -> HP_SLEEP_LP_REGULATOR_DBIAS_R { + HP_SLEEP_LP_REGULATOR_DBIAS_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_LP_REGULATOR0") + .field( + "hp_sleep_lp_regulator_slp_xpd", + &format_args!("{}", self.hp_sleep_lp_regulator_slp_xpd().bit()), + ) + .field( + "hp_sleep_lp_regulator_xpd", + &format_args!("{}", self.hp_sleep_lp_regulator_xpd().bit()), + ) + .field( + "hp_sleep_lp_regulator_slp_dbias", + &format_args!("{}", self.hp_sleep_lp_regulator_slp_dbias().bits()), + ) + .field( + "hp_sleep_lp_regulator_dbias", + &format_args!("{}", self.hp_sleep_lp_regulator_dbias().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_lp_regulator_slp_xpd( + &mut self, + ) -> HP_SLEEP_LP_REGULATOR_SLP_XPD_W { + HP_SLEEP_LP_REGULATOR_SLP_XPD_W::new(self, 21) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_lp_regulator_xpd( + &mut self, + ) -> HP_SLEEP_LP_REGULATOR_XPD_W { + HP_SLEEP_LP_REGULATOR_XPD_W::new(self, 22) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_lp_regulator_slp_dbias( + &mut self, + ) -> HP_SLEEP_LP_REGULATOR_SLP_DBIAS_W { + HP_SLEEP_LP_REGULATOR_SLP_DBIAS_W::new(self, 23) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_lp_regulator_dbias( + &mut self, + ) -> HP_SLEEP_LP_REGULATOR_DBIAS_W { + HP_SLEEP_LP_REGULATOR_DBIAS_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_lp_regulator0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_lp_regulator0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_LP_REGULATOR0_SPEC; +impl crate::RegisterSpec for HP_SLEEP_LP_REGULATOR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_lp_regulator0::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_LP_REGULATOR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_lp_regulator0::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_LP_REGULATOR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_LP_REGULATOR0 to value 0xc660_0000"] +impl crate::Resettable for HP_SLEEP_LP_REGULATOR0_SPEC { + const RESET_VALUE: Self::Ux = 0xc660_0000; +} diff --git a/esp32p4/src/pmu/hp_sleep_lp_regulator1.rs b/esp32p4/src/pmu/hp_sleep_lp_regulator1.rs new file mode 100644 index 0000000000..ef6c3ff9fc --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_lp_regulator1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `HP_SLEEP_LP_REGULATOR1` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_LP_REGULATOR1` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_LP_REGULATOR_DRV_B` reader - need_des"] +pub type HP_SLEEP_LP_REGULATOR_DRV_B_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_LP_REGULATOR_DRV_B` writer - need_des"] +pub type HP_SLEEP_LP_REGULATOR_DRV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 26:31 - need_des"] + #[inline(always)] + pub fn hp_sleep_lp_regulator_drv_b(&self) -> HP_SLEEP_LP_REGULATOR_DRV_B_R { + HP_SLEEP_LP_REGULATOR_DRV_B_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_LP_REGULATOR1") + .field( + "hp_sleep_lp_regulator_drv_b", + &format_args!("{}", self.hp_sleep_lp_regulator_drv_b().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 26:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_lp_regulator_drv_b( + &mut self, + ) -> HP_SLEEP_LP_REGULATOR_DRV_B_W { + HP_SLEEP_LP_REGULATOR_DRV_B_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_lp_regulator1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_lp_regulator1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_LP_REGULATOR1_SPEC; +impl crate::RegisterSpec for HP_SLEEP_LP_REGULATOR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_lp_regulator1::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_LP_REGULATOR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_lp_regulator1::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_LP_REGULATOR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_LP_REGULATOR1 to value 0"] +impl crate::Resettable for HP_SLEEP_LP_REGULATOR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_sysclk.rs b/esp32p4/src/pmu/hp_sleep_sysclk.rs new file mode 100644 index 0000000000..207ee48e2a --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_sysclk.rs @@ -0,0 +1,146 @@ +#[doc = "Register `HP_SLEEP_SYSCLK` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_SYSCLK` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_DIG_SYS_CLK_NO_DIV` reader - need_des"] +pub type HP_SLEEP_DIG_SYS_CLK_NO_DIV_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_DIG_SYS_CLK_NO_DIV` writer - need_des"] +pub type HP_SLEEP_DIG_SYS_CLK_NO_DIV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_ICG_SYS_CLOCK_EN` reader - need_des"] +pub type HP_SLEEP_ICG_SYS_CLOCK_EN_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_ICG_SYS_CLOCK_EN` writer - need_des"] +pub type HP_SLEEP_ICG_SYS_CLOCK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_SYS_CLK_SLP_SEL` reader - need_des"] +pub type HP_SLEEP_SYS_CLK_SLP_SEL_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_SYS_CLK_SLP_SEL` writer - need_des"] +pub type HP_SLEEP_SYS_CLK_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_ICG_SLP_SEL` reader - need_des"] +pub type HP_SLEEP_ICG_SLP_SEL_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_ICG_SLP_SEL` writer - need_des"] +pub type HP_SLEEP_ICG_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SLEEP_DIG_SYS_CLK_SEL` reader - need_des"] +pub type HP_SLEEP_DIG_SYS_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `HP_SLEEP_DIG_SYS_CLK_SEL` writer - need_des"] +pub type HP_SLEEP_DIG_SYS_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn hp_sleep_dig_sys_clk_no_div(&self) -> HP_SLEEP_DIG_SYS_CLK_NO_DIV_R { + HP_SLEEP_DIG_SYS_CLK_NO_DIV_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn hp_sleep_icg_sys_clock_en(&self) -> HP_SLEEP_ICG_SYS_CLOCK_EN_R { + HP_SLEEP_ICG_SYS_CLOCK_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn hp_sleep_sys_clk_slp_sel(&self) -> HP_SLEEP_SYS_CLK_SLP_SEL_R { + HP_SLEEP_SYS_CLK_SLP_SEL_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn hp_sleep_icg_slp_sel(&self) -> HP_SLEEP_ICG_SLP_SEL_R { + HP_SLEEP_ICG_SLP_SEL_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + pub fn hp_sleep_dig_sys_clk_sel(&self) -> HP_SLEEP_DIG_SYS_CLK_SEL_R { + HP_SLEEP_DIG_SYS_CLK_SEL_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_SYSCLK") + .field( + "hp_sleep_dig_sys_clk_no_div", + &format_args!("{}", self.hp_sleep_dig_sys_clk_no_div().bit()), + ) + .field( + "hp_sleep_icg_sys_clock_en", + &format_args!("{}", self.hp_sleep_icg_sys_clock_en().bit()), + ) + .field( + "hp_sleep_sys_clk_slp_sel", + &format_args!("{}", self.hp_sleep_sys_clk_slp_sel().bit()), + ) + .field( + "hp_sleep_icg_slp_sel", + &format_args!("{}", self.hp_sleep_icg_slp_sel().bit()), + ) + .field( + "hp_sleep_dig_sys_clk_sel", + &format_args!("{}", self.hp_sleep_dig_sys_clk_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dig_sys_clk_no_div( + &mut self, + ) -> HP_SLEEP_DIG_SYS_CLK_NO_DIV_W { + HP_SLEEP_DIG_SYS_CLK_NO_DIV_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_icg_sys_clock_en( + &mut self, + ) -> HP_SLEEP_ICG_SYS_CLOCK_EN_W { + HP_SLEEP_ICG_SYS_CLOCK_EN_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_sys_clk_slp_sel(&mut self) -> HP_SLEEP_SYS_CLK_SLP_SEL_W { + HP_SLEEP_SYS_CLK_SLP_SEL_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_icg_slp_sel(&mut self) -> HP_SLEEP_ICG_SLP_SEL_W { + HP_SLEEP_ICG_SLP_SEL_W::new(self, 29) + } + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_dig_sys_clk_sel(&mut self) -> HP_SLEEP_DIG_SYS_CLK_SEL_W { + HP_SLEEP_DIG_SYS_CLK_SEL_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_sysclk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_sysclk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_SYSCLK_SPEC; +impl crate::RegisterSpec for HP_SLEEP_SYSCLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_sysclk::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_SYSCLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_sysclk::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_SYSCLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_SYSCLK to value 0"] +impl crate::Resettable for HP_SLEEP_SYSCLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/hp_sleep_xtal.rs b/esp32p4/src/pmu/hp_sleep_xtal.rs new file mode 100644 index 0000000000..1e22653bed --- /dev/null +++ b/esp32p4/src/pmu/hp_sleep_xtal.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HP_SLEEP_XTAL` reader"] +pub type R = crate::R; +#[doc = "Register `HP_SLEEP_XTAL` writer"] +pub type W = crate::W; +#[doc = "Field `HP_SLEEP_XPD_XTAL` reader - need_des"] +pub type HP_SLEEP_XPD_XTAL_R = crate::BitReader; +#[doc = "Field `HP_SLEEP_XPD_XTAL` writer - need_des"] +pub type HP_SLEEP_XPD_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_sleep_xpd_xtal(&self) -> HP_SLEEP_XPD_XTAL_R { + HP_SLEEP_XPD_XTAL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HP_SLEEP_XTAL") + .field( + "hp_sleep_xpd_xtal", + &format_args!("{}", self.hp_sleep_xpd_xtal().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sleep_xpd_xtal(&mut self) -> HP_SLEEP_XPD_XTAL_W { + HP_SLEEP_XPD_XTAL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_sleep_xtal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hp_sleep_xtal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HP_SLEEP_XTAL_SPEC; +impl crate::RegisterSpec for HP_SLEEP_XTAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hp_sleep_xtal::R`](R) reader structure"] +impl crate::Readable for HP_SLEEP_XTAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hp_sleep_xtal::W`](W) writer structure"] +impl crate::Writable for HP_SLEEP_XTAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HP_SLEEP_XTAL to value 0x8000_0000"] +impl crate::Resettable for HP_SLEEP_XTAL_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_0000; +} diff --git a/esp32p4/src/pmu/imm_hp_apb_icg.rs b/esp32p4/src/pmu/imm_hp_apb_icg.rs new file mode 100644 index 0000000000..90f68d238e --- /dev/null +++ b/esp32p4/src/pmu/imm_hp_apb_icg.rs @@ -0,0 +1,42 @@ +#[doc = "Register `IMM_HP_APB_ICG` writer"] +pub type W = crate::W; +#[doc = "Field `UPDATE_DIG_ICG_APB_EN` writer - need_des"] +pub type UPDATE_DIG_ICG_APB_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn update_dig_icg_apb_en(&mut self) -> UPDATE_DIG_ICG_APB_EN_W { + UPDATE_DIG_ICG_APB_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_hp_apb_icg::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IMM_HP_APB_ICG_SPEC; +impl crate::RegisterSpec for IMM_HP_APB_ICG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`imm_hp_apb_icg::W`](W) writer structure"] +impl crate::Writable for IMM_HP_APB_ICG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IMM_HP_APB_ICG to value 0"] +impl crate::Resettable for IMM_HP_APB_ICG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/imm_hp_ck_power.rs b/esp32p4/src/pmu/imm_hp_ck_power.rs new file mode 100644 index 0000000000..d8dc89245e --- /dev/null +++ b/esp32p4/src/pmu/imm_hp_ck_power.rs @@ -0,0 +1,181 @@ +#[doc = "Register `IMM_HP_CK_POWER` reader"] +pub type R = crate::R; +#[doc = "Register `IMM_HP_CK_POWER` writer"] +pub type W = crate::W; +#[doc = "Field `TIE_LOW_CALI_XTAL_ICG` reader - need_des"] +pub type TIE_LOW_CALI_XTAL_ICG_R = crate::BitReader; +#[doc = "Field `TIE_LOW_CALI_XTAL_ICG` writer - need_des"] +pub type TIE_LOW_CALI_XTAL_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_LOW_GLOBAL_PLL_ICG` writer - need_des"] +pub type TIE_LOW_GLOBAL_PLL_ICG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TIE_LOW_GLOBAL_XTAL_ICG` writer - need_des"] +pub type TIE_LOW_GLOBAL_XTAL_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_LOW_I2C_RETENTION` writer - need_des"] +pub type TIE_LOW_I2C_RETENTION_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_LOW_XPD_PLL_I2C` writer - need_des"] +pub type TIE_LOW_XPD_PLL_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TIE_LOW_XPD_PLL` writer - need_des"] +pub type TIE_LOW_XPD_PLL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TIE_LOW_XPD_XTAL` writer - need_des"] +pub type TIE_LOW_XPD_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_HIGH_CALI_XTAL_ICG` reader - need_des"] +pub type TIE_HIGH_CALI_XTAL_ICG_R = crate::BitReader; +#[doc = "Field `TIE_HIGH_CALI_XTAL_ICG` writer - need_des"] +pub type TIE_HIGH_CALI_XTAL_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_HIGH_GLOBAL_PLL_ICG` writer - need_des"] +pub type TIE_HIGH_GLOBAL_PLL_ICG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TIE_HIGH_GLOBAL_XTAL_ICG` writer - need_des"] +pub type TIE_HIGH_GLOBAL_XTAL_ICG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_HIGH_I2C_RETENTION` writer - need_des"] +pub type TIE_HIGH_I2C_RETENTION_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_HIGH_XPD_PLL_I2C` writer - need_des"] +pub type TIE_HIGH_XPD_PLL_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TIE_HIGH_XPD_PLL` writer - need_des"] +pub type TIE_HIGH_XPD_PLL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TIE_HIGH_XPD_XTAL` writer - need_des"] +pub type TIE_HIGH_XPD_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn tie_low_cali_xtal_icg(&self) -> TIE_LOW_CALI_XTAL_ICG_R { + TIE_LOW_CALI_XTAL_ICG_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 16 - need_des"] + #[inline(always)] + pub fn tie_high_cali_xtal_icg(&self) -> TIE_HIGH_CALI_XTAL_ICG_R { + TIE_HIGH_CALI_XTAL_ICG_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IMM_HP_CK_POWER") + .field( + "tie_low_cali_xtal_icg", + &format_args!("{}", self.tie_low_cali_xtal_icg().bit()), + ) + .field( + "tie_high_cali_xtal_icg", + &format_args!("{}", self.tie_high_cali_xtal_icg().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_cali_xtal_icg(&mut self) -> TIE_LOW_CALI_XTAL_ICG_W { + TIE_LOW_CALI_XTAL_ICG_W::new(self, 0) + } + #[doc = "Bits 1:4 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_global_pll_icg(&mut self) -> TIE_LOW_GLOBAL_PLL_ICG_W { + TIE_LOW_GLOBAL_PLL_ICG_W::new(self, 1) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_global_xtal_icg(&mut self) -> TIE_LOW_GLOBAL_XTAL_ICG_W { + TIE_LOW_GLOBAL_XTAL_ICG_W::new(self, 5) + } + #[doc = "Bit 6 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_i2c_retention(&mut self) -> TIE_LOW_I2C_RETENTION_W { + TIE_LOW_I2C_RETENTION_W::new(self, 6) + } + #[doc = "Bits 7:10 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_xpd_pll_i2c(&mut self) -> TIE_LOW_XPD_PLL_I2C_W { + TIE_LOW_XPD_PLL_I2C_W::new(self, 7) + } + #[doc = "Bits 11:14 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_xpd_pll(&mut self) -> TIE_LOW_XPD_PLL_W { + TIE_LOW_XPD_PLL_W::new(self, 11) + } + #[doc = "Bit 15 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_xpd_xtal(&mut self) -> TIE_LOW_XPD_XTAL_W { + TIE_LOW_XPD_XTAL_W::new(self, 15) + } + #[doc = "Bit 16 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_cali_xtal_icg(&mut self) -> TIE_HIGH_CALI_XTAL_ICG_W { + TIE_HIGH_CALI_XTAL_ICG_W::new(self, 16) + } + #[doc = "Bits 17:20 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_global_pll_icg(&mut self) -> TIE_HIGH_GLOBAL_PLL_ICG_W { + TIE_HIGH_GLOBAL_PLL_ICG_W::new(self, 17) + } + #[doc = "Bit 21 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_global_xtal_icg(&mut self) -> TIE_HIGH_GLOBAL_XTAL_ICG_W { + TIE_HIGH_GLOBAL_XTAL_ICG_W::new(self, 21) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_i2c_retention(&mut self) -> TIE_HIGH_I2C_RETENTION_W { + TIE_HIGH_I2C_RETENTION_W::new(self, 22) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_xpd_pll_i2c(&mut self) -> TIE_HIGH_XPD_PLL_I2C_W { + TIE_HIGH_XPD_PLL_I2C_W::new(self, 23) + } + #[doc = "Bits 27:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_xpd_pll(&mut self) -> TIE_HIGH_XPD_PLL_W { + TIE_HIGH_XPD_PLL_W::new(self, 27) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_xpd_xtal(&mut self) -> TIE_HIGH_XPD_XTAL_W { + TIE_HIGH_XPD_XTAL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imm_hp_ck_power::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_hp_ck_power::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IMM_HP_CK_POWER_SPEC; +impl crate::RegisterSpec for IMM_HP_CK_POWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`imm_hp_ck_power::R`](R) reader structure"] +impl crate::Readable for IMM_HP_CK_POWER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`imm_hp_ck_power::W`](W) writer structure"] +impl crate::Writable for IMM_HP_CK_POWER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IMM_HP_CK_POWER to value 0"] +impl crate::Resettable for IMM_HP_CK_POWER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/imm_hp_func_icg.rs b/esp32p4/src/pmu/imm_hp_func_icg.rs new file mode 100644 index 0000000000..8aac80aaa3 --- /dev/null +++ b/esp32p4/src/pmu/imm_hp_func_icg.rs @@ -0,0 +1,42 @@ +#[doc = "Register `IMM_HP_FUNC_ICG` writer"] +pub type W = crate::W; +#[doc = "Field `UPDATE_DIG_ICG_FUNC_EN` writer - need_des"] +pub type UPDATE_DIG_ICG_FUNC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn update_dig_icg_func_en(&mut self) -> UPDATE_DIG_ICG_FUNC_EN_W { + UPDATE_DIG_ICG_FUNC_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_hp_func_icg::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IMM_HP_FUNC_ICG_SPEC; +impl crate::RegisterSpec for IMM_HP_FUNC_ICG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`imm_hp_func_icg::W`](W) writer structure"] +impl crate::Writable for IMM_HP_FUNC_ICG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IMM_HP_FUNC_ICG to value 0"] +impl crate::Resettable for IMM_HP_FUNC_ICG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/imm_i2c_iso.rs b/esp32p4/src/pmu/imm_i2c_iso.rs new file mode 100644 index 0000000000..08a45362d6 --- /dev/null +++ b/esp32p4/src/pmu/imm_i2c_iso.rs @@ -0,0 +1,50 @@ +#[doc = "Register `IMM_I2C_ISO` writer"] +pub type W = crate::W; +#[doc = "Field `TIE_HIGH_I2C_ISO_EN` writer - need_des"] +pub type TIE_HIGH_I2C_ISO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_LOW_I2C_ISO_EN` writer - need_des"] +pub type TIE_LOW_I2C_ISO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_i2c_iso_en(&mut self) -> TIE_HIGH_I2C_ISO_EN_W { + TIE_HIGH_I2C_ISO_EN_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_i2c_iso_en(&mut self) -> TIE_LOW_I2C_ISO_EN_W { + TIE_LOW_I2C_ISO_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_i2c_iso::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IMM_I2C_ISO_SPEC; +impl crate::RegisterSpec for IMM_I2C_ISO_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`imm_i2c_iso::W`](W) writer structure"] +impl crate::Writable for IMM_I2C_ISO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IMM_I2C_ISO to value 0"] +impl crate::Resettable for IMM_I2C_ISO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/imm_lp_icg.rs b/esp32p4/src/pmu/imm_lp_icg.rs new file mode 100644 index 0000000000..c934881828 --- /dev/null +++ b/esp32p4/src/pmu/imm_lp_icg.rs @@ -0,0 +1,50 @@ +#[doc = "Register `IMM_LP_ICG` writer"] +pub type W = crate::W; +#[doc = "Field `TIE_LOW_LP_ROOTCLK_SEL` writer - need_des"] +pub type TIE_LOW_LP_ROOTCLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_HIGH_LP_ROOTCLK_SEL` writer - need_des"] +pub type TIE_HIGH_LP_ROOTCLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_lp_rootclk_sel(&mut self) -> TIE_LOW_LP_ROOTCLK_SEL_W { + TIE_LOW_LP_ROOTCLK_SEL_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_lp_rootclk_sel(&mut self) -> TIE_HIGH_LP_ROOTCLK_SEL_W { + TIE_HIGH_LP_ROOTCLK_SEL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_lp_icg::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IMM_LP_ICG_SPEC; +impl crate::RegisterSpec for IMM_LP_ICG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`imm_lp_icg::W`](W) writer structure"] +impl crate::Writable for IMM_LP_ICG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IMM_LP_ICG to value 0"] +impl crate::Resettable for IMM_LP_ICG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/imm_modem_icg.rs b/esp32p4/src/pmu/imm_modem_icg.rs new file mode 100644 index 0000000000..4411beef4b --- /dev/null +++ b/esp32p4/src/pmu/imm_modem_icg.rs @@ -0,0 +1,42 @@ +#[doc = "Register `IMM_MODEM_ICG` writer"] +pub type W = crate::W; +#[doc = "Field `UPDATE_DIG_ICG_MODEM_EN` writer - need_des"] +pub type UPDATE_DIG_ICG_MODEM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn update_dig_icg_modem_en(&mut self) -> UPDATE_DIG_ICG_MODEM_EN_W { + UPDATE_DIG_ICG_MODEM_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_modem_icg::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IMM_MODEM_ICG_SPEC; +impl crate::RegisterSpec for IMM_MODEM_ICG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`imm_modem_icg::W`](W) writer structure"] +impl crate::Writable for IMM_MODEM_ICG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IMM_MODEM_ICG to value 0"] +impl crate::Resettable for IMM_MODEM_ICG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/imm_pad_hold_all.rs b/esp32p4/src/pmu/imm_pad_hold_all.rs new file mode 100644 index 0000000000..a7ca960e5c --- /dev/null +++ b/esp32p4/src/pmu/imm_pad_hold_all.rs @@ -0,0 +1,129 @@ +#[doc = "Register `IMM_PAD_HOLD_ALL` reader"] +pub type R = crate::R; +#[doc = "Register `IMM_PAD_HOLD_ALL` writer"] +pub type W = crate::W; +#[doc = "Field `PAD_SLP_SEL` reader - need_des"] +pub type PAD_SLP_SEL_R = crate::BitReader; +#[doc = "Field `LP_PAD_HOLD_ALL` reader - need_des"] +pub type LP_PAD_HOLD_ALL_R = crate::BitReader; +#[doc = "Field `HP_PAD_HOLD_ALL` reader - need_des"] +pub type HP_PAD_HOLD_ALL_R = crate::BitReader; +#[doc = "Field `TIE_HIGH_PAD_SLP_SEL` writer - need_des"] +pub type TIE_HIGH_PAD_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_LOW_PAD_SLP_SEL` writer - need_des"] +pub type TIE_LOW_PAD_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_HIGH_LP_PAD_HOLD_ALL` writer - need_des"] +pub type TIE_HIGH_LP_PAD_HOLD_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_LOW_LP_PAD_HOLD_ALL` writer - need_des"] +pub type TIE_LOW_LP_PAD_HOLD_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_HIGH_HP_PAD_HOLD_ALL` writer - need_des"] +pub type TIE_HIGH_HP_PAD_HOLD_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_LOW_HP_PAD_HOLD_ALL` writer - need_des"] +pub type TIE_LOW_HP_PAD_HOLD_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn pad_slp_sel(&self) -> PAD_SLP_SEL_R { + PAD_SLP_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn lp_pad_hold_all(&self) -> LP_PAD_HOLD_ALL_R { + LP_PAD_HOLD_ALL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + pub fn hp_pad_hold_all(&self) -> HP_PAD_HOLD_ALL_R { + HP_PAD_HOLD_ALL_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IMM_PAD_HOLD_ALL") + .field("pad_slp_sel", &format_args!("{}", self.pad_slp_sel().bit())) + .field( + "lp_pad_hold_all", + &format_args!("{}", self.lp_pad_hold_all().bit()), + ) + .field( + "hp_pad_hold_all", + &format_args!("{}", self.hp_pad_hold_all().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_pad_slp_sel(&mut self) -> TIE_HIGH_PAD_SLP_SEL_W { + TIE_HIGH_PAD_SLP_SEL_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_pad_slp_sel(&mut self) -> TIE_LOW_PAD_SLP_SEL_W { + TIE_LOW_PAD_SLP_SEL_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_lp_pad_hold_all( + &mut self, + ) -> TIE_HIGH_LP_PAD_HOLD_ALL_W { + TIE_HIGH_LP_PAD_HOLD_ALL_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_lp_pad_hold_all(&mut self) -> TIE_LOW_LP_PAD_HOLD_ALL_W { + TIE_LOW_LP_PAD_HOLD_ALL_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_hp_pad_hold_all( + &mut self, + ) -> TIE_HIGH_HP_PAD_HOLD_ALL_W { + TIE_HIGH_HP_PAD_HOLD_ALL_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_hp_pad_hold_all(&mut self) -> TIE_LOW_HP_PAD_HOLD_ALL_W { + TIE_LOW_HP_PAD_HOLD_ALL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imm_pad_hold_all::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_pad_hold_all::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IMM_PAD_HOLD_ALL_SPEC; +impl crate::RegisterSpec for IMM_PAD_HOLD_ALL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`imm_pad_hold_all::R`](R) reader structure"] +impl crate::Readable for IMM_PAD_HOLD_ALL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`imm_pad_hold_all::W`](W) writer structure"] +impl crate::Writable for IMM_PAD_HOLD_ALL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IMM_PAD_HOLD_ALL to value 0"] +impl crate::Resettable for IMM_PAD_HOLD_ALL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/imm_sleep_sysclk.rs b/esp32p4/src/pmu/imm_sleep_sysclk.rs new file mode 100644 index 0000000000..c7dfbfc4f5 --- /dev/null +++ b/esp32p4/src/pmu/imm_sleep_sysclk.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IMM_SLEEP_SYSCLK` writer"] +pub type W = crate::W; +#[doc = "Field `UPDATE_DIG_ICG_SWITCH` writer - need_des"] +pub type UPDATE_DIG_ICG_SWITCH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_LOW_ICG_SLP_SEL` writer - need_des"] +pub type TIE_LOW_ICG_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIE_HIGH_ICG_SLP_SEL` writer - need_des"] +pub type TIE_HIGH_ICG_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UPDATE_DIG_SYS_CLK_SEL` writer - need_des"] +pub type UPDATE_DIG_SYS_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn update_dig_icg_switch(&mut self) -> UPDATE_DIG_ICG_SWITCH_W { + UPDATE_DIG_ICG_SWITCH_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_low_icg_slp_sel(&mut self) -> TIE_LOW_ICG_SLP_SEL_W { + TIE_LOW_ICG_SLP_SEL_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn tie_high_icg_slp_sel(&mut self) -> TIE_HIGH_ICG_SLP_SEL_W { + TIE_HIGH_ICG_SLP_SEL_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn update_dig_sys_clk_sel(&mut self) -> UPDATE_DIG_SYS_CLK_SEL_W { + UPDATE_DIG_SYS_CLK_SEL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imm_sleep_sysclk::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IMM_SLEEP_SYSCLK_SPEC; +impl crate::RegisterSpec for IMM_SLEEP_SYSCLK_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`imm_sleep_sysclk::W`](W) writer structure"] +impl crate::Writable for IMM_SLEEP_SYSCLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IMM_SLEEP_SYSCLK to value 0"] +impl crate::Resettable for IMM_SLEEP_SYSCLK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/int_raw.rs b/esp32p4/src/pmu/int_raw.rs new file mode 100644 index 0000000000..903c23cee2 --- /dev/null +++ b/esp32p4/src/pmu/int_raw.rs @@ -0,0 +1,391 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW` reader - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW` writer - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW` reader - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW` writer - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW` reader - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW` writer - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW` reader - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW` writer - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CPU_EXC_INT_RAW` reader - need_des"] +pub type LP_CPU_EXC_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_CPU_EXC_INT_RAW` writer - need_des"] +pub type LP_CPU_EXC_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_IDLE_INT_RAW` reader - need_des"] +pub type SDIO_IDLE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SDIO_IDLE_INT_RAW` writer - need_des"] +pub type SDIO_IDLE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_INT_RAW` reader - need_des"] +pub type SW_INT_RAW_R = crate::BitReader; +#[doc = "Field `SW_INT_RAW` writer - need_des"] +pub type SW_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOC_SLEEP_REJECT_INT_RAW` reader - need_des"] +pub type SOC_SLEEP_REJECT_INT_RAW_R = crate::BitReader; +#[doc = "Field `SOC_SLEEP_REJECT_INT_RAW` writer - need_des"] +pub type SOC_SLEEP_REJECT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOC_WAKEUP_INT_RAW` reader - need_des"] +pub type SOC_WAKEUP_INT_RAW_R = crate::BitReader; +#[doc = "Field `SOC_WAKEUP_INT_RAW` writer - need_des"] +pub type SOC_WAKEUP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_0_hp_int_raw(&self) -> _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_R { + _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_0_hp_int_raw(&self) -> _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_R { + _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_1_hp_int_raw(&self) -> _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_R { + _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_1_hp_int_raw(&self) -> _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_R { + _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_0_hp_int_raw(&self) -> _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_R { + _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_0_hp_int_raw(&self) -> _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_R { + _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_1_hp_int_raw(&self) -> _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_R { + _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_1_hp_int_raw(&self) -> _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_R { + _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_0_hp_int_raw(&self) -> _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_R { + _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_0_hp_int_raw(&self) -> _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_R { + _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_1_hp_int_raw(&self) -> _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_R { + _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_1_hp_int_raw(&self) -> _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_R { + _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_cpu_exc_int_raw(&self) -> LP_CPU_EXC_INT_RAW_R { + LP_CPU_EXC_INT_RAW_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn sdio_idle_int_raw(&self) -> SDIO_IDLE_INT_RAW_R { + SDIO_IDLE_INT_RAW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn sw_int_raw(&self) -> SW_INT_RAW_R { + SW_INT_RAW_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn soc_sleep_reject_int_raw(&self) -> SOC_SLEEP_REJECT_INT_RAW_R { + SOC_SLEEP_REJECT_INT_RAW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn soc_wakeup_int_raw(&self) -> SOC_WAKEUP_INT_RAW_R { + SOC_WAKEUP_INT_RAW_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "_0p1a_cnt_target0_reach_0_hp_int_raw", + &format_args!("{}", self._0p1a_cnt_target0_reach_0_hp_int_raw().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_0_hp_int_raw", + &format_args!("{}", self._0p1a_cnt_target1_reach_0_hp_int_raw().bit()), + ) + .field( + "_0p1a_cnt_target0_reach_1_hp_int_raw", + &format_args!("{}", self._0p1a_cnt_target0_reach_1_hp_int_raw().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_1_hp_int_raw", + &format_args!("{}", self._0p1a_cnt_target1_reach_1_hp_int_raw().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_0_hp_int_raw", + &format_args!("{}", self._0p2a_cnt_target0_reach_0_hp_int_raw().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_0_hp_int_raw", + &format_args!("{}", self._0p2a_cnt_target1_reach_0_hp_int_raw().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_1_hp_int_raw", + &format_args!("{}", self._0p2a_cnt_target0_reach_1_hp_int_raw().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_1_hp_int_raw", + &format_args!("{}", self._0p2a_cnt_target1_reach_1_hp_int_raw().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_0_hp_int_raw", + &format_args!("{}", self._0p3a_cnt_target0_reach_0_hp_int_raw().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_0_hp_int_raw", + &format_args!("{}", self._0p3a_cnt_target1_reach_0_hp_int_raw().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_1_hp_int_raw", + &format_args!("{}", self._0p3a_cnt_target0_reach_1_hp_int_raw().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_1_hp_int_raw", + &format_args!("{}", self._0p3a_cnt_target1_reach_1_hp_int_raw().bit()), + ) + .field( + "lp_cpu_exc_int_raw", + &format_args!("{}", self.lp_cpu_exc_int_raw().bit()), + ) + .field( + "sdio_idle_int_raw", + &format_args!("{}", self.sdio_idle_int_raw().bit()), + ) + .field("sw_int_raw", &format_args!("{}", self.sw_int_raw().bit())) + .field( + "soc_sleep_reject_int_raw", + &format_args!("{}", self.soc_sleep_reject_int_raw().bit()), + ) + .field( + "soc_wakeup_int_raw", + &format_args!("{}", self.soc_wakeup_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_0_hp_int_raw( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_W { + _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_0_hp_int_raw( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_W { + _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW_W::new(self, 15) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_1_hp_int_raw( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_W { + _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW_W::new(self, 16) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_1_hp_int_raw( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_W { + _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW_W::new(self, 17) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_0_hp_int_raw( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_W { + _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW_W::new(self, 18) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_0_hp_int_raw( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_W { + _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW_W::new(self, 19) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_1_hp_int_raw( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_W { + _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW_W::new(self, 20) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_1_hp_int_raw( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_W { + _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW_W::new(self, 21) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_0_hp_int_raw( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_W { + _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW_W::new(self, 22) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_0_hp_int_raw( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_W { + _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW_W::new(self, 23) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_1_hp_int_raw( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_W { + _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW_W::new(self, 24) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_1_hp_int_raw( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_W { + _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW_W::new(self, 25) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_exc_int_raw(&mut self) -> LP_CPU_EXC_INT_RAW_W { + LP_CPU_EXC_INT_RAW_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn sdio_idle_int_raw(&mut self) -> SDIO_IDLE_INT_RAW_W { + SDIO_IDLE_INT_RAW_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn sw_int_raw(&mut self) -> SW_INT_RAW_W { + SW_INT_RAW_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn soc_sleep_reject_int_raw(&mut self) -> SOC_SLEEP_REJECT_INT_RAW_W { + SOC_SLEEP_REJECT_INT_RAW_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn soc_wakeup_int_raw(&mut self) -> SOC_WAKEUP_INT_RAW_W { + SOC_WAKEUP_INT_RAW_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_cpu_pwr0.rs b/esp32p4/src/pmu/lp_cpu_pwr0.rs new file mode 100644 index 0000000000..2e800219fa --- /dev/null +++ b/esp32p4/src/pmu/lp_cpu_pwr0.rs @@ -0,0 +1,202 @@ +#[doc = "Register `LP_CPU_PWR0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_CPU_PWR0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_CPU_WAITI_RDY` reader - need_des"] +pub type LP_CPU_WAITI_RDY_R = crate::BitReader; +#[doc = "Field `LP_CPU_STALL_RDY` reader - need_des"] +pub type LP_CPU_STALL_RDY_R = crate::BitReader; +#[doc = "Field `LP_CPU_FORCE_STALL` reader - need_des"] +pub type LP_CPU_FORCE_STALL_R = crate::BitReader; +#[doc = "Field `LP_CPU_FORCE_STALL` writer - need_des"] +pub type LP_CPU_FORCE_STALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CPU_SLP_WAITI_FLAG_EN` reader - need_des"] +pub type LP_CPU_SLP_WAITI_FLAG_EN_R = crate::BitReader; +#[doc = "Field `LP_CPU_SLP_WAITI_FLAG_EN` writer - need_des"] +pub type LP_CPU_SLP_WAITI_FLAG_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CPU_SLP_STALL_FLAG_EN` reader - need_des"] +pub type LP_CPU_SLP_STALL_FLAG_EN_R = crate::BitReader; +#[doc = "Field `LP_CPU_SLP_STALL_FLAG_EN` writer - need_des"] +pub type LP_CPU_SLP_STALL_FLAG_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CPU_SLP_STALL_WAIT` reader - need_des"] +pub type LP_CPU_SLP_STALL_WAIT_R = crate::FieldReader; +#[doc = "Field `LP_CPU_SLP_STALL_WAIT` writer - need_des"] +pub type LP_CPU_SLP_STALL_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `LP_CPU_SLP_STALL_EN` reader - need_des"] +pub type LP_CPU_SLP_STALL_EN_R = crate::BitReader; +#[doc = "Field `LP_CPU_SLP_STALL_EN` writer - need_des"] +pub type LP_CPU_SLP_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CPU_SLP_RESET_EN` reader - need_des"] +pub type LP_CPU_SLP_RESET_EN_R = crate::BitReader; +#[doc = "Field `LP_CPU_SLP_RESET_EN` writer - need_des"] +pub type LP_CPU_SLP_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CPU_SLP_BYPASS_INTR_EN` reader - need_des"] +pub type LP_CPU_SLP_BYPASS_INTR_EN_R = crate::BitReader; +#[doc = "Field `LP_CPU_SLP_BYPASS_INTR_EN` writer - need_des"] +pub type LP_CPU_SLP_BYPASS_INTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn lp_cpu_waiti_rdy(&self) -> LP_CPU_WAITI_RDY_R { + LP_CPU_WAITI_RDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn lp_cpu_stall_rdy(&self) -> LP_CPU_STALL_RDY_R { + LP_CPU_STALL_RDY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 18 - need_des"] + #[inline(always)] + pub fn lp_cpu_force_stall(&self) -> LP_CPU_FORCE_STALL_R { + LP_CPU_FORCE_STALL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - need_des"] + #[inline(always)] + pub fn lp_cpu_slp_waiti_flag_en(&self) -> LP_CPU_SLP_WAITI_FLAG_EN_R { + LP_CPU_SLP_WAITI_FLAG_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - need_des"] + #[inline(always)] + pub fn lp_cpu_slp_stall_flag_en(&self) -> LP_CPU_SLP_STALL_FLAG_EN_R { + LP_CPU_SLP_STALL_FLAG_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:28 - need_des"] + #[inline(always)] + pub fn lp_cpu_slp_stall_wait(&self) -> LP_CPU_SLP_STALL_WAIT_R { + LP_CPU_SLP_STALL_WAIT_R::new(((self.bits >> 21) & 0xff) as u8) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn lp_cpu_slp_stall_en(&self) -> LP_CPU_SLP_STALL_EN_R { + LP_CPU_SLP_STALL_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_cpu_slp_reset_en(&self) -> LP_CPU_SLP_RESET_EN_R { + LP_CPU_SLP_RESET_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_cpu_slp_bypass_intr_en(&self) -> LP_CPU_SLP_BYPASS_INTR_EN_R { + LP_CPU_SLP_BYPASS_INTR_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CPU_PWR0") + .field( + "lp_cpu_waiti_rdy", + &format_args!("{}", self.lp_cpu_waiti_rdy().bit()), + ) + .field( + "lp_cpu_stall_rdy", + &format_args!("{}", self.lp_cpu_stall_rdy().bit()), + ) + .field( + "lp_cpu_force_stall", + &format_args!("{}", self.lp_cpu_force_stall().bit()), + ) + .field( + "lp_cpu_slp_waiti_flag_en", + &format_args!("{}", self.lp_cpu_slp_waiti_flag_en().bit()), + ) + .field( + "lp_cpu_slp_stall_flag_en", + &format_args!("{}", self.lp_cpu_slp_stall_flag_en().bit()), + ) + .field( + "lp_cpu_slp_stall_wait", + &format_args!("{}", self.lp_cpu_slp_stall_wait().bits()), + ) + .field( + "lp_cpu_slp_stall_en", + &format_args!("{}", self.lp_cpu_slp_stall_en().bit()), + ) + .field( + "lp_cpu_slp_reset_en", + &format_args!("{}", self.lp_cpu_slp_reset_en().bit()), + ) + .field( + "lp_cpu_slp_bypass_intr_en", + &format_args!("{}", self.lp_cpu_slp_bypass_intr_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 18 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_force_stall(&mut self) -> LP_CPU_FORCE_STALL_W { + LP_CPU_FORCE_STALL_W::new(self, 18) + } + #[doc = "Bit 19 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_slp_waiti_flag_en(&mut self) -> LP_CPU_SLP_WAITI_FLAG_EN_W { + LP_CPU_SLP_WAITI_FLAG_EN_W::new(self, 19) + } + #[doc = "Bit 20 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_slp_stall_flag_en(&mut self) -> LP_CPU_SLP_STALL_FLAG_EN_W { + LP_CPU_SLP_STALL_FLAG_EN_W::new(self, 20) + } + #[doc = "Bits 21:28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_slp_stall_wait(&mut self) -> LP_CPU_SLP_STALL_WAIT_W { + LP_CPU_SLP_STALL_WAIT_W::new(self, 21) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_slp_stall_en(&mut self) -> LP_CPU_SLP_STALL_EN_W { + LP_CPU_SLP_STALL_EN_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_slp_reset_en(&mut self) -> LP_CPU_SLP_RESET_EN_W { + LP_CPU_SLP_RESET_EN_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_slp_bypass_intr_en(&mut self) -> LP_CPU_SLP_BYPASS_INTR_EN_W { + LP_CPU_SLP_BYPASS_INTR_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_cpu_pwr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CPU_PWR0_SPEC; +impl crate::RegisterSpec for LP_CPU_PWR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_cpu_pwr0::R`](R) reader structure"] +impl crate::Readable for LP_CPU_PWR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_cpu_pwr0::W`](W) writer structure"] +impl crate::Writable for LP_CPU_PWR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_CPU_PWR0 to value 0x1ff0_0000"] +impl crate::Resettable for LP_CPU_PWR0_SPEC { + const RESET_VALUE: Self::Ux = 0x1ff0_0000; +} diff --git a/esp32p4/src/pmu/lp_cpu_pwr1.rs b/esp32p4/src/pmu/lp_cpu_pwr1.rs new file mode 100644 index 0000000000..2bae80568e --- /dev/null +++ b/esp32p4/src/pmu/lp_cpu_pwr1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `LP_CPU_PWR1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_CPU_SLEEP_REQ` writer - need_des"] +pub type LP_CPU_SLEEP_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_sleep_req(&mut self) -> LP_CPU_SLEEP_REQ_W { + LP_CPU_SLEEP_REQ_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_cpu_pwr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CPU_PWR1_SPEC; +impl crate::RegisterSpec for LP_CPU_PWR1_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`lp_cpu_pwr1::W`](W) writer structure"] +impl crate::Writable for LP_CPU_PWR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_CPU_PWR1 to value 0"] +impl crate::Resettable for LP_CPU_PWR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_cpu_pwr2.rs b/esp32p4/src/pmu/lp_cpu_pwr2.rs new file mode 100644 index 0000000000..96f5d9db22 --- /dev/null +++ b/esp32p4/src/pmu/lp_cpu_pwr2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_CPU_PWR2` reader"] +pub type R = crate::R; +#[doc = "Register `LP_CPU_PWR2` writer"] +pub type W = crate::W; +#[doc = "Field `LP_CPU_WAKEUP_EN` reader - need_des"] +pub type LP_CPU_WAKEUP_EN_R = crate::FieldReader; +#[doc = "Field `LP_CPU_WAKEUP_EN` writer - need_des"] +pub type LP_CPU_WAKEUP_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn lp_cpu_wakeup_en(&self) -> LP_CPU_WAKEUP_EN_R { + LP_CPU_WAKEUP_EN_R::new(self.bits & 0x7fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CPU_PWR2") + .field( + "lp_cpu_wakeup_en", + &format_args!("{}", self.lp_cpu_wakeup_en().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_wakeup_en(&mut self) -> LP_CPU_WAKEUP_EN_W { + LP_CPU_WAKEUP_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_cpu_pwr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CPU_PWR2_SPEC; +impl crate::RegisterSpec for LP_CPU_PWR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_cpu_pwr2::R`](R) reader structure"] +impl crate::Readable for LP_CPU_PWR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_cpu_pwr2::W`](W) writer structure"] +impl crate::Writable for LP_CPU_PWR2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_CPU_PWR2 to value 0"] +impl crate::Resettable for LP_CPU_PWR2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_cpu_pwr3.rs b/esp32p4/src/pmu/lp_cpu_pwr3.rs new file mode 100644 index 0000000000..7a79a615d9 --- /dev/null +++ b/esp32p4/src/pmu/lp_cpu_pwr3.rs @@ -0,0 +1,39 @@ +#[doc = "Register `LP_CPU_PWR3` reader"] +pub type R = crate::R; +#[doc = "Field `LP_CPU_WAKEUP_CAUSE` reader - need_des"] +pub type LP_CPU_WAKEUP_CAUSE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn lp_cpu_wakeup_cause(&self) -> LP_CPU_WAKEUP_CAUSE_R { + LP_CPU_WAKEUP_CAUSE_R::new(self.bits & 0x7fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CPU_PWR3") + .field( + "lp_cpu_wakeup_cause", + &format_args!("{}", self.lp_cpu_wakeup_cause().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CPU_PWR3_SPEC; +impl crate::RegisterSpec for LP_CPU_PWR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_cpu_pwr3::R`](R) reader structure"] +impl crate::Readable for LP_CPU_PWR3_SPEC {} +#[doc = "`reset()` method sets LP_CPU_PWR3 to value 0"] +impl crate::Resettable for LP_CPU_PWR3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_cpu_pwr4.rs b/esp32p4/src/pmu/lp_cpu_pwr4.rs new file mode 100644 index 0000000000..6347a6499d --- /dev/null +++ b/esp32p4/src/pmu/lp_cpu_pwr4.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_CPU_PWR4` reader"] +pub type R = crate::R; +#[doc = "Register `LP_CPU_PWR4` writer"] +pub type W = crate::W; +#[doc = "Field `LP_CPU_REJECT_EN` reader - need_des"] +pub type LP_CPU_REJECT_EN_R = crate::FieldReader; +#[doc = "Field `LP_CPU_REJECT_EN` writer - need_des"] +pub type LP_CPU_REJECT_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn lp_cpu_reject_en(&self) -> LP_CPU_REJECT_EN_R { + LP_CPU_REJECT_EN_R::new(self.bits & 0x7fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CPU_PWR4") + .field( + "lp_cpu_reject_en", + &format_args!("{}", self.lp_cpu_reject_en().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_reject_en(&mut self) -> LP_CPU_REJECT_EN_W { + LP_CPU_REJECT_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_cpu_pwr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CPU_PWR4_SPEC; +impl crate::RegisterSpec for LP_CPU_PWR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_cpu_pwr4::R`](R) reader structure"] +impl crate::Readable for LP_CPU_PWR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_cpu_pwr4::W`](W) writer structure"] +impl crate::Writable for LP_CPU_PWR4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_CPU_PWR4 to value 0"] +impl crate::Resettable for LP_CPU_PWR4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_cpu_pwr5.rs b/esp32p4/src/pmu/lp_cpu_pwr5.rs new file mode 100644 index 0000000000..4720bbdbba --- /dev/null +++ b/esp32p4/src/pmu/lp_cpu_pwr5.rs @@ -0,0 +1,39 @@ +#[doc = "Register `LP_CPU_PWR5` reader"] +pub type R = crate::R; +#[doc = "Field `LP_CPU_REJECT_CAUSE` reader - need_des"] +pub type LP_CPU_REJECT_CAUSE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn lp_cpu_reject_cause(&self) -> LP_CPU_REJECT_CAUSE_R { + LP_CPU_REJECT_CAUSE_R::new(self.bits & 0x7fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_CPU_PWR5") + .field( + "lp_cpu_reject_cause", + &format_args!("{}", self.lp_cpu_reject_cause().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_CPU_PWR5_SPEC; +impl crate::RegisterSpec for LP_CPU_PWR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_cpu_pwr5::R`](R) reader structure"] +impl crate::Readable for LP_CPU_PWR5_SPEC {} +#[doc = "`reset()` method sets LP_CPU_PWR5 to value 0"] +impl crate::Resettable for LP_CPU_PWR5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_int_clr.rs b/esp32p4/src/pmu/lp_int_clr.rs new file mode 100644 index 0000000000..8761eaf2ab --- /dev/null +++ b/esp32p4/src/pmu/lp_int_clr.rs @@ -0,0 +1,220 @@ +#[doc = "Register `LP_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `LP_CPU_SLEEP_REJECT_LP_INT_CLR` writer - need_des"] +pub type LP_CPU_SLEEP_REJECT_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR` writer - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR` writer - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR` writer - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR` writer - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CPU_WAKEUP_INT_CLR` writer - need_des"] +pub type LP_CPU_WAKEUP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_END_INT_CLR` writer - need_des"] +pub type SLEEP_SWITCH_ACTIVE_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_END_INT_CLR` writer - need_des"] +pub type ACTIVE_SWITCH_SLEEP_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_START_INT_CLR` writer - need_des"] +pub type SLEEP_SWITCH_ACTIVE_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_START_INT_CLR` writer - need_des"] +pub type ACTIVE_SWITCH_SLEEP_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SW_TRIGGER_INT_CLR` writer - need_des"] +pub type HP_SW_TRIGGER_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_sleep_reject_lp_int_clr( + &mut self, + ) -> LP_CPU_SLEEP_REJECT_LP_INT_CLR_W { + LP_CPU_SLEEP_REJECT_LP_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_0_lp_int_clr( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_W { + _0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_0_lp_int_clr( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_W { + _0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_1_lp_int_clr( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_W { + _0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_1_lp_int_clr( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_W { + _0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_0_lp_int_clr( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_W { + _0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_0_lp_int_clr( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_W { + _0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_1_lp_int_clr( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_W { + _0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_1_lp_int_clr( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_W { + _0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_0_lp_int_clr( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_W { + _0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_0_lp_int_clr( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_W { + _0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_1_lp_int_clr( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_W { + _0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_1_lp_int_clr( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_W { + _0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_wakeup_int_clr(&mut self) -> LP_CPU_WAKEUP_INT_CLR_W { + LP_CPU_WAKEUP_INT_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep_switch_active_end_int_clr( + &mut self, + ) -> SLEEP_SWITCH_ACTIVE_END_INT_CLR_W { + SLEEP_SWITCH_ACTIVE_END_INT_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn active_switch_sleep_end_int_clr( + &mut self, + ) -> ACTIVE_SWITCH_SLEEP_END_INT_CLR_W { + ACTIVE_SWITCH_SLEEP_END_INT_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep_switch_active_start_int_clr( + &mut self, + ) -> SLEEP_SWITCH_ACTIVE_START_INT_CLR_W { + SLEEP_SWITCH_ACTIVE_START_INT_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn active_switch_sleep_start_int_clr( + &mut self, + ) -> ACTIVE_SWITCH_SLEEP_START_INT_CLR_W { + ACTIVE_SWITCH_SLEEP_START_INT_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sw_trigger_int_clr(&mut self) -> HP_SW_TRIGGER_INT_CLR_W { + HP_SW_TRIGGER_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_INT_CLR_SPEC; +impl crate::RegisterSpec for LP_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`lp_int_clr::W`](W) writer structure"] +impl crate::Writable for LP_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_INT_CLR to value 0"] +impl crate::Resettable for LP_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_int_ena.rs b/esp32p4/src/pmu/lp_int_ena.rs new file mode 100644 index 0000000000..b22653b02f --- /dev/null +++ b/esp32p4/src/pmu/lp_int_ena.rs @@ -0,0 +1,442 @@ +#[doc = "Register `LP_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `LP_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `LP_CPU_SLEEP_REJECT_INT_ENA` reader - need_des"] +pub type LP_CPU_SLEEP_REJECT_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_CPU_SLEEP_REJECT_INT_ENA` writer - need_des"] +pub type LP_CPU_SLEEP_REJECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA` reader - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA` writer - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA` reader - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA` writer - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA` reader - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA` writer - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA` reader - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA` writer - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CPU_WAKEUP_INT_ENA` reader - need_des"] +pub type LP_CPU_WAKEUP_INT_ENA_R = crate::BitReader; +#[doc = "Field `LP_CPU_WAKEUP_INT_ENA` writer - need_des"] +pub type LP_CPU_WAKEUP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_END_INT_ENA` reader - need_des"] +pub type SLEEP_SWITCH_ACTIVE_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_END_INT_ENA` writer - need_des"] +pub type SLEEP_SWITCH_ACTIVE_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_END_INT_ENA` reader - need_des"] +pub type ACTIVE_SWITCH_SLEEP_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_END_INT_ENA` writer - need_des"] +pub type ACTIVE_SWITCH_SLEEP_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_START_INT_ENA` reader - need_des"] +pub type SLEEP_SWITCH_ACTIVE_START_INT_ENA_R = crate::BitReader; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_START_INT_ENA` writer - need_des"] +pub type SLEEP_SWITCH_ACTIVE_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_START_INT_ENA` reader - need_des"] +pub type ACTIVE_SWITCH_SLEEP_START_INT_ENA_R = crate::BitReader; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_START_INT_ENA` writer - need_des"] +pub type ACTIVE_SWITCH_SLEEP_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SW_TRIGGER_INT_ENA` reader - need_des"] +pub type HP_SW_TRIGGER_INT_ENA_R = crate::BitReader; +#[doc = "Field `HP_SW_TRIGGER_INT_ENA` writer - need_des"] +pub type HP_SW_TRIGGER_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn lp_cpu_sleep_reject_int_ena(&self) -> LP_CPU_SLEEP_REJECT_INT_ENA_R { + LP_CPU_SLEEP_REJECT_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_0_lp_int_ena(&self) -> _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_R { + _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_0_lp_int_ena(&self) -> _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_R { + _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_1_lp_int_ena(&self) -> _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_R { + _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_1_lp_int_ena(&self) -> _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_R { + _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_0_lp_int_ena(&self) -> _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_R { + _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_0_lp_int_ena(&self) -> _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_R { + _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_1_lp_int_ena(&self) -> _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_R { + _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_1_lp_int_ena(&self) -> _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_R { + _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_0_lp_int_ena(&self) -> _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_R { + _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_0_lp_int_ena(&self) -> _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_R { + _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_1_lp_int_ena(&self) -> _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_R { + _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_1_lp_int_ena(&self) -> _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_R { + _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn lp_cpu_wakeup_int_ena(&self) -> LP_CPU_WAKEUP_INT_ENA_R { + LP_CPU_WAKEUP_INT_ENA_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn sleep_switch_active_end_int_ena(&self) -> SLEEP_SWITCH_ACTIVE_END_INT_ENA_R { + SLEEP_SWITCH_ACTIVE_END_INT_ENA_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn active_switch_sleep_end_int_ena(&self) -> ACTIVE_SWITCH_SLEEP_END_INT_ENA_R { + ACTIVE_SWITCH_SLEEP_END_INT_ENA_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn sleep_switch_active_start_int_ena(&self) -> SLEEP_SWITCH_ACTIVE_START_INT_ENA_R { + SLEEP_SWITCH_ACTIVE_START_INT_ENA_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn active_switch_sleep_start_int_ena(&self) -> ACTIVE_SWITCH_SLEEP_START_INT_ENA_R { + ACTIVE_SWITCH_SLEEP_START_INT_ENA_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_sw_trigger_int_ena(&self) -> HP_SW_TRIGGER_INT_ENA_R { + HP_SW_TRIGGER_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_INT_ENA") + .field( + "lp_cpu_sleep_reject_int_ena", + &format_args!("{}", self.lp_cpu_sleep_reject_int_ena().bit()), + ) + .field( + "_0p1a_cnt_target0_reach_0_lp_int_ena", + &format_args!("{}", self._0p1a_cnt_target0_reach_0_lp_int_ena().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_0_lp_int_ena", + &format_args!("{}", self._0p1a_cnt_target1_reach_0_lp_int_ena().bit()), + ) + .field( + "_0p1a_cnt_target0_reach_1_lp_int_ena", + &format_args!("{}", self._0p1a_cnt_target0_reach_1_lp_int_ena().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_1_lp_int_ena", + &format_args!("{}", self._0p1a_cnt_target1_reach_1_lp_int_ena().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_0_lp_int_ena", + &format_args!("{}", self._0p2a_cnt_target0_reach_0_lp_int_ena().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_0_lp_int_ena", + &format_args!("{}", self._0p2a_cnt_target1_reach_0_lp_int_ena().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_1_lp_int_ena", + &format_args!("{}", self._0p2a_cnt_target0_reach_1_lp_int_ena().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_1_lp_int_ena", + &format_args!("{}", self._0p2a_cnt_target1_reach_1_lp_int_ena().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_0_lp_int_ena", + &format_args!("{}", self._0p3a_cnt_target0_reach_0_lp_int_ena().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_0_lp_int_ena", + &format_args!("{}", self._0p3a_cnt_target1_reach_0_lp_int_ena().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_1_lp_int_ena", + &format_args!("{}", self._0p3a_cnt_target0_reach_1_lp_int_ena().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_1_lp_int_ena", + &format_args!("{}", self._0p3a_cnt_target1_reach_1_lp_int_ena().bit()), + ) + .field( + "lp_cpu_wakeup_int_ena", + &format_args!("{}", self.lp_cpu_wakeup_int_ena().bit()), + ) + .field( + "sleep_switch_active_end_int_ena", + &format_args!("{}", self.sleep_switch_active_end_int_ena().bit()), + ) + .field( + "active_switch_sleep_end_int_ena", + &format_args!("{}", self.active_switch_sleep_end_int_ena().bit()), + ) + .field( + "sleep_switch_active_start_int_ena", + &format_args!("{}", self.sleep_switch_active_start_int_ena().bit()), + ) + .field( + "active_switch_sleep_start_int_ena", + &format_args!("{}", self.active_switch_sleep_start_int_ena().bit()), + ) + .field( + "hp_sw_trigger_int_ena", + &format_args!("{}", self.hp_sw_trigger_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_sleep_reject_int_ena( + &mut self, + ) -> LP_CPU_SLEEP_REJECT_INT_ENA_W { + LP_CPU_SLEEP_REJECT_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_0_lp_int_ena( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_W { + _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_0_lp_int_ena( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_W { + _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_1_lp_int_ena( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_W { + _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_1_lp_int_ena( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_W { + _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_0_lp_int_ena( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_W { + _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA_W::new(self, 18) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_0_lp_int_ena( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_W { + _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA_W::new(self, 19) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_1_lp_int_ena( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_W { + _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA_W::new(self, 20) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_1_lp_int_ena( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_W { + _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA_W::new(self, 21) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_0_lp_int_ena( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_W { + _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA_W::new(self, 22) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_0_lp_int_ena( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_W { + _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA_W::new(self, 23) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_1_lp_int_ena( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_W { + _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA_W::new(self, 24) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_1_lp_int_ena( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_W { + _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_wakeup_int_ena(&mut self) -> LP_CPU_WAKEUP_INT_ENA_W { + LP_CPU_WAKEUP_INT_ENA_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep_switch_active_end_int_ena( + &mut self, + ) -> SLEEP_SWITCH_ACTIVE_END_INT_ENA_W { + SLEEP_SWITCH_ACTIVE_END_INT_ENA_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn active_switch_sleep_end_int_ena( + &mut self, + ) -> ACTIVE_SWITCH_SLEEP_END_INT_ENA_W { + ACTIVE_SWITCH_SLEEP_END_INT_ENA_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep_switch_active_start_int_ena( + &mut self, + ) -> SLEEP_SWITCH_ACTIVE_START_INT_ENA_W { + SLEEP_SWITCH_ACTIVE_START_INT_ENA_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn active_switch_sleep_start_int_ena( + &mut self, + ) -> ACTIVE_SWITCH_SLEEP_START_INT_ENA_W { + ACTIVE_SWITCH_SLEEP_START_INT_ENA_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sw_trigger_int_ena(&mut self) -> HP_SW_TRIGGER_INT_ENA_W { + HP_SW_TRIGGER_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_INT_ENA_SPEC; +impl crate::RegisterSpec for LP_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_int_ena::R`](R) reader structure"] +impl crate::Readable for LP_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_int_ena::W`](W) writer structure"] +impl crate::Writable for LP_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_INT_ENA to value 0"] +impl crate::Resettable for LP_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_int_raw.rs b/esp32p4/src/pmu/lp_int_raw.rs new file mode 100644 index 0000000000..976e38746a --- /dev/null +++ b/esp32p4/src/pmu/lp_int_raw.rs @@ -0,0 +1,442 @@ +#[doc = "Register `LP_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `LP_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `LP_CPU_SLEEP_REJECT_INT_RAW` reader - need_des"] +pub type LP_CPU_SLEEP_REJECT_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_CPU_SLEEP_REJECT_INT_RAW` writer - need_des"] +pub type LP_CPU_SLEEP_REJECT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW` reader - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW` writer - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW` reader - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW` writer - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW` writer - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW` writer - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW` writer - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW` reader - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW` writer - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW` reader - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW` writer - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW` writer - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_CPU_WAKEUP_INT_RAW` reader - need_des"] +pub type LP_CPU_WAKEUP_INT_RAW_R = crate::BitReader; +#[doc = "Field `LP_CPU_WAKEUP_INT_RAW` writer - need_des"] +pub type LP_CPU_WAKEUP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_END_INT_RAW` reader - need_des"] +pub type SLEEP_SWITCH_ACTIVE_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_END_INT_RAW` writer - need_des"] +pub type SLEEP_SWITCH_ACTIVE_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_END_INT_RAW` reader - need_des"] +pub type ACTIVE_SWITCH_SLEEP_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_END_INT_RAW` writer - need_des"] +pub type ACTIVE_SWITCH_SLEEP_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_START_INT_RAW` reader - need_des"] +pub type SLEEP_SWITCH_ACTIVE_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_START_INT_RAW` writer - need_des"] +pub type SLEEP_SWITCH_ACTIVE_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_START_INT_RAW` reader - need_des"] +pub type ACTIVE_SWITCH_SLEEP_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_START_INT_RAW` writer - need_des"] +pub type ACTIVE_SWITCH_SLEEP_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HP_SW_TRIGGER_INT_RAW` reader - need_des"] +pub type HP_SW_TRIGGER_INT_RAW_R = crate::BitReader; +#[doc = "Field `HP_SW_TRIGGER_INT_RAW` writer - need_des"] +pub type HP_SW_TRIGGER_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn lp_cpu_sleep_reject_int_raw(&self) -> LP_CPU_SLEEP_REJECT_INT_RAW_R { + LP_CPU_SLEEP_REJECT_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_0_lp_int_raw(&self) -> _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_R { + _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_0_lp_int_raw(&self) -> _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_R { + _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_1_lp_int_raw(&self) -> _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_R { + _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_1_lp_int_raw(&self) -> _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_R { + _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_0_lp_int_raw(&self) -> _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_R { + _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_0_lp_int_raw(&self) -> _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_R { + _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_1_lp_int_raw(&self) -> _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_R { + _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_1_lp_int_raw(&self) -> _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_R { + _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_0_lp_int_raw(&self) -> _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_R { + _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_0_lp_int_raw(&self) -> _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_R { + _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_1_lp_int_raw(&self) -> _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_R { + _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_1_lp_int_raw(&self) -> _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_R { + _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn lp_cpu_wakeup_int_raw(&self) -> LP_CPU_WAKEUP_INT_RAW_R { + LP_CPU_WAKEUP_INT_RAW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn sleep_switch_active_end_int_raw(&self) -> SLEEP_SWITCH_ACTIVE_END_INT_RAW_R { + SLEEP_SWITCH_ACTIVE_END_INT_RAW_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn active_switch_sleep_end_int_raw(&self) -> ACTIVE_SWITCH_SLEEP_END_INT_RAW_R { + ACTIVE_SWITCH_SLEEP_END_INT_RAW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn sleep_switch_active_start_int_raw(&self) -> SLEEP_SWITCH_ACTIVE_START_INT_RAW_R { + SLEEP_SWITCH_ACTIVE_START_INT_RAW_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn active_switch_sleep_start_int_raw(&self) -> ACTIVE_SWITCH_SLEEP_START_INT_RAW_R { + ACTIVE_SWITCH_SLEEP_START_INT_RAW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_sw_trigger_int_raw(&self) -> HP_SW_TRIGGER_INT_RAW_R { + HP_SW_TRIGGER_INT_RAW_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_INT_RAW") + .field( + "lp_cpu_sleep_reject_int_raw", + &format_args!("{}", self.lp_cpu_sleep_reject_int_raw().bit()), + ) + .field( + "_0p1a_cnt_target0_reach_0_lp_int_raw", + &format_args!("{}", self._0p1a_cnt_target0_reach_0_lp_int_raw().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_0_lp_int_raw", + &format_args!("{}", self._0p1a_cnt_target1_reach_0_lp_int_raw().bit()), + ) + .field( + "_0p1a_cnt_target0_reach_1_lp_int_raw", + &format_args!("{}", self._0p1a_cnt_target0_reach_1_lp_int_raw().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_1_lp_int_raw", + &format_args!("{}", self._0p1a_cnt_target1_reach_1_lp_int_raw().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_0_lp_int_raw", + &format_args!("{}", self._0p2a_cnt_target0_reach_0_lp_int_raw().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_0_lp_int_raw", + &format_args!("{}", self._0p2a_cnt_target1_reach_0_lp_int_raw().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_1_lp_int_raw", + &format_args!("{}", self._0p2a_cnt_target0_reach_1_lp_int_raw().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_1_lp_int_raw", + &format_args!("{}", self._0p2a_cnt_target1_reach_1_lp_int_raw().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_0_lp_int_raw", + &format_args!("{}", self._0p3a_cnt_target0_reach_0_lp_int_raw().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_0_lp_int_raw", + &format_args!("{}", self._0p3a_cnt_target1_reach_0_lp_int_raw().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_1_lp_int_raw", + &format_args!("{}", self._0p3a_cnt_target0_reach_1_lp_int_raw().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_1_lp_int_raw", + &format_args!("{}", self._0p3a_cnt_target1_reach_1_lp_int_raw().bit()), + ) + .field( + "lp_cpu_wakeup_int_raw", + &format_args!("{}", self.lp_cpu_wakeup_int_raw().bit()), + ) + .field( + "sleep_switch_active_end_int_raw", + &format_args!("{}", self.sleep_switch_active_end_int_raw().bit()), + ) + .field( + "active_switch_sleep_end_int_raw", + &format_args!("{}", self.active_switch_sleep_end_int_raw().bit()), + ) + .field( + "sleep_switch_active_start_int_raw", + &format_args!("{}", self.sleep_switch_active_start_int_raw().bit()), + ) + .field( + "active_switch_sleep_start_int_raw", + &format_args!("{}", self.active_switch_sleep_start_int_raw().bit()), + ) + .field( + "hp_sw_trigger_int_raw", + &format_args!("{}", self.hp_sw_trigger_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 13 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_sleep_reject_int_raw( + &mut self, + ) -> LP_CPU_SLEEP_REJECT_INT_RAW_W { + LP_CPU_SLEEP_REJECT_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_0_lp_int_raw( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_W { + _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_0_lp_int_raw( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_W { + _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW_W::new(self, 15) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target0_reach_1_lp_int_raw( + &mut self, + ) -> _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_W { + _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW_W::new(self, 16) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p1a_cnt_target1_reach_1_lp_int_raw( + &mut self, + ) -> _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_W { + _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW_W::new(self, 17) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_0_lp_int_raw( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_W { + _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW_W::new(self, 18) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_0_lp_int_raw( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_W { + _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW_W::new(self, 19) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target0_reach_1_lp_int_raw( + &mut self, + ) -> _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_W { + _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW_W::new(self, 20) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p2a_cnt_target1_reach_1_lp_int_raw( + &mut self, + ) -> _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_W { + _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW_W::new(self, 21) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_0_lp_int_raw( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_W { + _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW_W::new(self, 22) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_0_lp_int_raw( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_W { + _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW_W::new(self, 23) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target0_reach_1_lp_int_raw( + &mut self, + ) -> _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_W { + _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW_W::new(self, 24) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + #[must_use] + pub fn _0p3a_cnt_target1_reach_1_lp_int_raw( + &mut self, + ) -> _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_W { + _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_cpu_wakeup_int_raw(&mut self) -> LP_CPU_WAKEUP_INT_RAW_W { + LP_CPU_WAKEUP_INT_RAW_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep_switch_active_end_int_raw( + &mut self, + ) -> SLEEP_SWITCH_ACTIVE_END_INT_RAW_W { + SLEEP_SWITCH_ACTIVE_END_INT_RAW_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn active_switch_sleep_end_int_raw( + &mut self, + ) -> ACTIVE_SWITCH_SLEEP_END_INT_RAW_W { + ACTIVE_SWITCH_SLEEP_END_INT_RAW_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep_switch_active_start_int_raw( + &mut self, + ) -> SLEEP_SWITCH_ACTIVE_START_INT_RAW_W { + SLEEP_SWITCH_ACTIVE_START_INT_RAW_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn active_switch_sleep_start_int_raw( + &mut self, + ) -> ACTIVE_SWITCH_SLEEP_START_INT_RAW_W { + ACTIVE_SWITCH_SLEEP_START_INT_RAW_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_sw_trigger_int_raw(&mut self) -> HP_SW_TRIGGER_INT_RAW_W { + HP_SW_TRIGGER_INT_RAW_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_INT_RAW_SPEC; +impl crate::RegisterSpec for LP_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_int_raw::R`](R) reader structure"] +impl crate::Readable for LP_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_int_raw::W`](W) writer structure"] +impl crate::Writable for LP_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_INT_RAW to value 0"] +impl crate::Resettable for LP_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_int_st.rs b/esp32p4/src/pmu/lp_int_st.rs new file mode 100644 index 0000000000..98bba22f6a --- /dev/null +++ b/esp32p4/src/pmu/lp_int_st.rs @@ -0,0 +1,237 @@ +#[doc = "Register `LP_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `LP_CPU_SLEEP_REJECT_INT_ST` reader - need_des"] +pub type LP_CPU_SLEEP_REJECT_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_0_LP_INT_ST` reader - reg_0p1a_0_counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_0_LP_INT_ST` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET0_REACH_1_LP_INT_ST` reader - reg_0p1a_0 counter after xpd reach target0"] +pub type _0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P1A_CNT_TARGET1_REACH_1_LP_INT_ST` reader - reg_0p1a_1_counter after xpd reach target1"] +pub type _0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_0_LP_INT_ST` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_0_LP_INT_ST` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET0_REACH_1_LP_INT_ST` reader - reg_0p2a_0 counter after xpd reach target0"] +pub type _0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P2A_CNT_TARGET1_REACH_1_LP_INT_ST` reader - reg_0p2a_1_counter after xpd reach target1"] +pub type _0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_0_LP_INT_ST` reader - reg_0p3a_0 counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_0_LP_INT_ST` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET0_REACH_1_LP_INT_ST` reader - reg_0p3a_0_counter after xpd reach target0"] +pub type _0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `_0P3A_CNT_TARGET1_REACH_1_LP_INT_ST` reader - reg_0p3a_1_counter after xpd reach target1"] +pub type _0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_R = crate::BitReader; +#[doc = "Field `LP_CPU_WAKEUP_INT_ST` reader - need_des"] +pub type LP_CPU_WAKEUP_INT_ST_R = crate::BitReader; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_END_INT_ST` reader - need_des"] +pub type SLEEP_SWITCH_ACTIVE_END_INT_ST_R = crate::BitReader; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_END_INT_ST` reader - need_des"] +pub type ACTIVE_SWITCH_SLEEP_END_INT_ST_R = crate::BitReader; +#[doc = "Field `SLEEP_SWITCH_ACTIVE_START_INT_ST` reader - need_des"] +pub type SLEEP_SWITCH_ACTIVE_START_INT_ST_R = crate::BitReader; +#[doc = "Field `ACTIVE_SWITCH_SLEEP_START_INT_ST` reader - need_des"] +pub type ACTIVE_SWITCH_SLEEP_START_INT_ST_R = crate::BitReader; +#[doc = "Field `HP_SW_TRIGGER_INT_ST` reader - need_des"] +pub type HP_SW_TRIGGER_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 13 - need_des"] + #[inline(always)] + pub fn lp_cpu_sleep_reject_int_st(&self) -> LP_CPU_SLEEP_REJECT_INT_ST_R { + LP_CPU_SLEEP_REJECT_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_0_lp_int_st(&self) -> _0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_R { + _0P1A_CNT_TARGET0_REACH_0_LP_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_0_lp_int_st(&self) -> _0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_R { + _0P1A_CNT_TARGET1_REACH_0_LP_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - reg_0p1a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p1a_cnt_target0_reach_1_lp_int_st(&self) -> _0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_R { + _0P1A_CNT_TARGET0_REACH_1_LP_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - reg_0p1a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p1a_cnt_target1_reach_1_lp_int_st(&self) -> _0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_R { + _0P1A_CNT_TARGET1_REACH_1_LP_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_0_lp_int_st(&self) -> _0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_R { + _0P2A_CNT_TARGET0_REACH_0_LP_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_0_lp_int_st(&self) -> _0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_R { + _0P2A_CNT_TARGET1_REACH_0_LP_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - reg_0p2a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p2a_cnt_target0_reach_1_lp_int_st(&self) -> _0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_R { + _0P2A_CNT_TARGET0_REACH_1_LP_INT_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - reg_0p2a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p2a_cnt_target1_reach_1_lp_int_st(&self) -> _0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_R { + _0P2A_CNT_TARGET1_REACH_1_LP_INT_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - reg_0p3a_0 counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_0_lp_int_st(&self) -> _0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_R { + _0P3A_CNT_TARGET0_REACH_0_LP_INT_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_0_lp_int_st(&self) -> _0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_R { + _0P3A_CNT_TARGET1_REACH_0_LP_INT_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - reg_0p3a_0_counter after xpd reach target0"] + #[inline(always)] + pub fn _0p3a_cnt_target0_reach_1_lp_int_st(&self) -> _0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_R { + _0P3A_CNT_TARGET0_REACH_1_LP_INT_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reg_0p3a_1_counter after xpd reach target1"] + #[inline(always)] + pub fn _0p3a_cnt_target1_reach_1_lp_int_st(&self) -> _0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_R { + _0P3A_CNT_TARGET1_REACH_1_LP_INT_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn lp_cpu_wakeup_int_st(&self) -> LP_CPU_WAKEUP_INT_ST_R { + LP_CPU_WAKEUP_INT_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn sleep_switch_active_end_int_st(&self) -> SLEEP_SWITCH_ACTIVE_END_INT_ST_R { + SLEEP_SWITCH_ACTIVE_END_INT_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn active_switch_sleep_end_int_st(&self) -> ACTIVE_SWITCH_SLEEP_END_INT_ST_R { + ACTIVE_SWITCH_SLEEP_END_INT_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn sleep_switch_active_start_int_st(&self) -> SLEEP_SWITCH_ACTIVE_START_INT_ST_R { + SLEEP_SWITCH_ACTIVE_START_INT_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn active_switch_sleep_start_int_st(&self) -> ACTIVE_SWITCH_SLEEP_START_INT_ST_R { + ACTIVE_SWITCH_SLEEP_START_INT_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn hp_sw_trigger_int_st(&self) -> HP_SW_TRIGGER_INT_ST_R { + HP_SW_TRIGGER_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_INT_ST") + .field( + "lp_cpu_sleep_reject_int_st", + &format_args!("{}", self.lp_cpu_sleep_reject_int_st().bit()), + ) + .field( + "_0p1a_cnt_target0_reach_0_lp_int_st", + &format_args!("{}", self._0p1a_cnt_target0_reach_0_lp_int_st().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_0_lp_int_st", + &format_args!("{}", self._0p1a_cnt_target1_reach_0_lp_int_st().bit()), + ) + .field( + "_0p1a_cnt_target0_reach_1_lp_int_st", + &format_args!("{}", self._0p1a_cnt_target0_reach_1_lp_int_st().bit()), + ) + .field( + "_0p1a_cnt_target1_reach_1_lp_int_st", + &format_args!("{}", self._0p1a_cnt_target1_reach_1_lp_int_st().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_0_lp_int_st", + &format_args!("{}", self._0p2a_cnt_target0_reach_0_lp_int_st().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_0_lp_int_st", + &format_args!("{}", self._0p2a_cnt_target1_reach_0_lp_int_st().bit()), + ) + .field( + "_0p2a_cnt_target0_reach_1_lp_int_st", + &format_args!("{}", self._0p2a_cnt_target0_reach_1_lp_int_st().bit()), + ) + .field( + "_0p2a_cnt_target1_reach_1_lp_int_st", + &format_args!("{}", self._0p2a_cnt_target1_reach_1_lp_int_st().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_0_lp_int_st", + &format_args!("{}", self._0p3a_cnt_target0_reach_0_lp_int_st().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_0_lp_int_st", + &format_args!("{}", self._0p3a_cnt_target1_reach_0_lp_int_st().bit()), + ) + .field( + "_0p3a_cnt_target0_reach_1_lp_int_st", + &format_args!("{}", self._0p3a_cnt_target0_reach_1_lp_int_st().bit()), + ) + .field( + "_0p3a_cnt_target1_reach_1_lp_int_st", + &format_args!("{}", self._0p3a_cnt_target1_reach_1_lp_int_st().bit()), + ) + .field( + "lp_cpu_wakeup_int_st", + &format_args!("{}", self.lp_cpu_wakeup_int_st().bit()), + ) + .field( + "sleep_switch_active_end_int_st", + &format_args!("{}", self.sleep_switch_active_end_int_st().bit()), + ) + .field( + "active_switch_sleep_end_int_st", + &format_args!("{}", self.active_switch_sleep_end_int_st().bit()), + ) + .field( + "sleep_switch_active_start_int_st", + &format_args!("{}", self.sleep_switch_active_start_int_st().bit()), + ) + .field( + "active_switch_sleep_start_int_st", + &format_args!("{}", self.active_switch_sleep_start_int_st().bit()), + ) + .field( + "hp_sw_trigger_int_st", + &format_args!("{}", self.hp_sw_trigger_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_INT_ST_SPEC; +impl crate::RegisterSpec for LP_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_int_st::R`](R) reader structure"] +impl crate::Readable for LP_INT_ST_SPEC {} +#[doc = "`reset()` method sets LP_INT_ST to value 0"] +impl crate::Resettable for LP_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_sleep_bias.rs b/esp32p4/src/pmu/lp_sleep_bias.rs new file mode 100644 index 0000000000..d642e15641 --- /dev/null +++ b/esp32p4/src/pmu/lp_sleep_bias.rs @@ -0,0 +1,120 @@ +#[doc = "Register `LP_SLEEP_BIAS` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SLEEP_BIAS` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SLEEP_XPD_BIAS` reader - need_des"] +pub type LP_SLEEP_XPD_BIAS_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_XPD_BIAS` writer - need_des"] +pub type LP_SLEEP_XPD_BIAS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_SLEEP_DBG_ATTEN` reader - need_des"] +pub type LP_SLEEP_DBG_ATTEN_R = crate::FieldReader; +#[doc = "Field `LP_SLEEP_DBG_ATTEN` writer - need_des"] +pub type LP_SLEEP_DBG_ATTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LP_SLEEP_PD_CUR` reader - need_des"] +pub type LP_SLEEP_PD_CUR_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_PD_CUR` writer - need_des"] +pub type LP_SLEEP_PD_CUR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEP` reader - need_des"] +pub type SLEEP_R = crate::BitReader; +#[doc = "Field `SLEEP` writer - need_des"] +pub type SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn lp_sleep_xpd_bias(&self) -> LP_SLEEP_XPD_BIAS_R { + LP_SLEEP_XPD_BIAS_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 26:29 - need_des"] + #[inline(always)] + pub fn lp_sleep_dbg_atten(&self) -> LP_SLEEP_DBG_ATTEN_R { + LP_SLEEP_DBG_ATTEN_R::new(((self.bits >> 26) & 0x0f) as u8) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_sleep_pd_cur(&self) -> LP_SLEEP_PD_CUR_R { + LP_SLEEP_PD_CUR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn sleep(&self) -> SLEEP_R { + SLEEP_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SLEEP_BIAS") + .field( + "lp_sleep_xpd_bias", + &format_args!("{}", self.lp_sleep_xpd_bias().bit()), + ) + .field( + "lp_sleep_dbg_atten", + &format_args!("{}", self.lp_sleep_dbg_atten().bits()), + ) + .field( + "lp_sleep_pd_cur", + &format_args!("{}", self.lp_sleep_pd_cur().bit()), + ) + .field("sleep", &format_args!("{}", self.sleep().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_xpd_bias(&mut self) -> LP_SLEEP_XPD_BIAS_W { + LP_SLEEP_XPD_BIAS_W::new(self, 25) + } + #[doc = "Bits 26:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_dbg_atten(&mut self) -> LP_SLEEP_DBG_ATTEN_W { + LP_SLEEP_DBG_ATTEN_W::new(self, 26) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_pd_cur(&mut self) -> LP_SLEEP_PD_CUR_W { + LP_SLEEP_PD_CUR_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep(&mut self) -> SLEEP_W { + SLEEP_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_bias::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_bias::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SLEEP_BIAS_SPEC; +impl crate::RegisterSpec for LP_SLEEP_BIAS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_sleep_bias::R`](R) reader structure"] +impl crate::Readable for LP_SLEEP_BIAS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_sleep_bias::W`](W) writer structure"] +impl crate::Writable for LP_SLEEP_BIAS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SLEEP_BIAS to value 0"] +impl crate::Resettable for LP_SLEEP_BIAS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_sleep_lp_bias_reserve.rs b/esp32p4/src/pmu/lp_sleep_lp_bias_reserve.rs new file mode 100644 index 0000000000..f273cc4570 --- /dev/null +++ b/esp32p4/src/pmu/lp_sleep_lp_bias_reserve.rs @@ -0,0 +1,44 @@ +#[doc = "Register `LP_SLEEP_LP_BIAS_RESERVE` writer"] +pub type W = crate::W; +#[doc = "Field `PMU_LP_SLEEP_LP_BIAS_RESERVE` writer - need_des"] +pub type PMU_LP_SLEEP_LP_BIAS_RESERVE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn pmu_lp_sleep_lp_bias_reserve( + &mut self, + ) -> PMU_LP_SLEEP_LP_BIAS_RESERVE_W { + PMU_LP_SLEEP_LP_BIAS_RESERVE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_lp_bias_reserve::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SLEEP_LP_BIAS_RESERVE_SPEC; +impl crate::RegisterSpec for LP_SLEEP_LP_BIAS_RESERVE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`lp_sleep_lp_bias_reserve::W`](W) writer structure"] +impl crate::Writable for LP_SLEEP_LP_BIAS_RESERVE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SLEEP_LP_BIAS_RESERVE to value 0"] +impl crate::Resettable for LP_SLEEP_LP_BIAS_RESERVE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_sleep_lp_ck_power.rs b/esp32p4/src/pmu/lp_sleep_lp_ck_power.rs new file mode 100644 index 0000000000..6417aff27f --- /dev/null +++ b/esp32p4/src/pmu/lp_sleep_lp_ck_power.rs @@ -0,0 +1,142 @@ +#[doc = "Register `LP_SLEEP_LP_CK_POWER` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SLEEP_LP_CK_POWER` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SLEEP_XPD_LPPLL` reader - need_des"] +pub type LP_SLEEP_XPD_LPPLL_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_XPD_LPPLL` writer - need_des"] +pub type LP_SLEEP_XPD_LPPLL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_SLEEP_XPD_XTAL32K` reader - need_des"] +pub type LP_SLEEP_XPD_XTAL32K_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_XPD_XTAL32K` writer - need_des"] +pub type LP_SLEEP_XPD_XTAL32K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_SLEEP_XPD_RC32K` reader - need_des"] +pub type LP_SLEEP_XPD_RC32K_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_XPD_RC32K` writer - need_des"] +pub type LP_SLEEP_XPD_RC32K_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_SLEEP_XPD_FOSC_CLK` reader - need_des"] +pub type LP_SLEEP_XPD_FOSC_CLK_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_XPD_FOSC_CLK` writer - need_des"] +pub type LP_SLEEP_XPD_FOSC_CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_SLEEP_PD_OSC_CLK` reader - need_des"] +pub type LP_SLEEP_PD_OSC_CLK_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_PD_OSC_CLK` writer - need_des"] +pub type LP_SLEEP_PD_OSC_CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_sleep_xpd_lppll(&self) -> LP_SLEEP_XPD_LPPLL_R { + LP_SLEEP_XPD_LPPLL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn lp_sleep_xpd_xtal32k(&self) -> LP_SLEEP_XPD_XTAL32K_R { + LP_SLEEP_XPD_XTAL32K_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn lp_sleep_xpd_rc32k(&self) -> LP_SLEEP_XPD_RC32K_R { + LP_SLEEP_XPD_RC32K_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_sleep_xpd_fosc_clk(&self) -> LP_SLEEP_XPD_FOSC_CLK_R { + LP_SLEEP_XPD_FOSC_CLK_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_sleep_pd_osc_clk(&self) -> LP_SLEEP_PD_OSC_CLK_R { + LP_SLEEP_PD_OSC_CLK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SLEEP_LP_CK_POWER") + .field( + "lp_sleep_xpd_lppll", + &format_args!("{}", self.lp_sleep_xpd_lppll().bit()), + ) + .field( + "lp_sleep_xpd_xtal32k", + &format_args!("{}", self.lp_sleep_xpd_xtal32k().bit()), + ) + .field( + "lp_sleep_xpd_rc32k", + &format_args!("{}", self.lp_sleep_xpd_rc32k().bit()), + ) + .field( + "lp_sleep_xpd_fosc_clk", + &format_args!("{}", self.lp_sleep_xpd_fosc_clk().bit()), + ) + .field( + "lp_sleep_pd_osc_clk", + &format_args!("{}", self.lp_sleep_pd_osc_clk().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_xpd_lppll(&mut self) -> LP_SLEEP_XPD_LPPLL_W { + LP_SLEEP_XPD_LPPLL_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_xpd_xtal32k(&mut self) -> LP_SLEEP_XPD_XTAL32K_W { + LP_SLEEP_XPD_XTAL32K_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_xpd_rc32k(&mut self) -> LP_SLEEP_XPD_RC32K_W { + LP_SLEEP_XPD_RC32K_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_xpd_fosc_clk(&mut self) -> LP_SLEEP_XPD_FOSC_CLK_W { + LP_SLEEP_XPD_FOSC_CLK_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_pd_osc_clk(&mut self) -> LP_SLEEP_PD_OSC_CLK_W { + LP_SLEEP_PD_OSC_CLK_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_lp_ck_power::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_lp_ck_power::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SLEEP_LP_CK_POWER_SPEC; +impl crate::RegisterSpec for LP_SLEEP_LP_CK_POWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_sleep_lp_ck_power::R`](R) reader structure"] +impl crate::Readable for LP_SLEEP_LP_CK_POWER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_sleep_lp_ck_power::W`](W) writer structure"] +impl crate::Writable for LP_SLEEP_LP_CK_POWER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SLEEP_LP_CK_POWER to value 0x4000_0000"] +impl crate::Resettable for LP_SLEEP_LP_CK_POWER_SPEC { + const RESET_VALUE: Self::Ux = 0x4000_0000; +} diff --git a/esp32p4/src/pmu/lp_sleep_lp_dig_power.rs b/esp32p4/src/pmu/lp_sleep_lp_dig_power.rs new file mode 100644 index 0000000000..c50ab59687 --- /dev/null +++ b/esp32p4/src/pmu/lp_sleep_lp_dig_power.rs @@ -0,0 +1,148 @@ +#[doc = "Register `LP_SLEEP_LP_DIG_POWER` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SLEEP_LP_DIG_POWER` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SLEEP_LP_PAD_SLP_SEL` reader - need_des"] +pub type LP_SLEEP_LP_PAD_SLP_SEL_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_LP_PAD_SLP_SEL` writer - need_des"] +pub type LP_SLEEP_LP_PAD_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_SLEEP_BOD_SOURCE_SEL` reader - need_des"] +pub type LP_SLEEP_BOD_SOURCE_SEL_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_BOD_SOURCE_SEL` writer - need_des"] +pub type LP_SLEEP_BOD_SOURCE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_SLEEP_VDDBAT_MODE` reader - need_des"] +pub type LP_SLEEP_VDDBAT_MODE_R = crate::FieldReader; +#[doc = "Field `LP_SLEEP_VDDBAT_MODE` writer - need_des"] +pub type LP_SLEEP_VDDBAT_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_SLEEP_LP_MEM_DSLP` reader - need_des"] +pub type LP_SLEEP_LP_MEM_DSLP_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_LP_MEM_DSLP` writer - need_des"] +pub type LP_SLEEP_LP_MEM_DSLP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_SLEEP_PD_LP_PERI_PD_EN` reader - need_des"] +pub type LP_SLEEP_PD_LP_PERI_PD_EN_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_PD_LP_PERI_PD_EN` writer - need_des"] +pub type LP_SLEEP_PD_LP_PERI_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn lp_sleep_lp_pad_slp_sel(&self) -> LP_SLEEP_LP_PAD_SLP_SEL_R { + LP_SLEEP_LP_PAD_SLP_SEL_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn lp_sleep_bod_source_sel(&self) -> LP_SLEEP_BOD_SOURCE_SEL_R { + LP_SLEEP_BOD_SOURCE_SEL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:29 - need_des"] + #[inline(always)] + pub fn lp_sleep_vddbat_mode(&self) -> LP_SLEEP_VDDBAT_MODE_R { + LP_SLEEP_VDDBAT_MODE_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn lp_sleep_lp_mem_dslp(&self) -> LP_SLEEP_LP_MEM_DSLP_R { + LP_SLEEP_LP_MEM_DSLP_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_sleep_pd_lp_peri_pd_en(&self) -> LP_SLEEP_PD_LP_PERI_PD_EN_R { + LP_SLEEP_PD_LP_PERI_PD_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SLEEP_LP_DIG_POWER") + .field( + "lp_sleep_lp_pad_slp_sel", + &format_args!("{}", self.lp_sleep_lp_pad_slp_sel().bit()), + ) + .field( + "lp_sleep_bod_source_sel", + &format_args!("{}", self.lp_sleep_bod_source_sel().bit()), + ) + .field( + "lp_sleep_vddbat_mode", + &format_args!("{}", self.lp_sleep_vddbat_mode().bits()), + ) + .field( + "lp_sleep_lp_mem_dslp", + &format_args!("{}", self.lp_sleep_lp_mem_dslp().bit()), + ) + .field( + "lp_sleep_pd_lp_peri_pd_en", + &format_args!("{}", self.lp_sleep_pd_lp_peri_pd_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_lp_pad_slp_sel( + &mut self, + ) -> LP_SLEEP_LP_PAD_SLP_SEL_W { + LP_SLEEP_LP_PAD_SLP_SEL_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_bod_source_sel( + &mut self, + ) -> LP_SLEEP_BOD_SOURCE_SEL_W { + LP_SLEEP_BOD_SOURCE_SEL_W::new(self, 27) + } + #[doc = "Bits 28:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_vddbat_mode(&mut self) -> LP_SLEEP_VDDBAT_MODE_W { + LP_SLEEP_VDDBAT_MODE_W::new(self, 28) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_lp_mem_dslp(&mut self) -> LP_SLEEP_LP_MEM_DSLP_W { + LP_SLEEP_LP_MEM_DSLP_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_pd_lp_peri_pd_en( + &mut self, + ) -> LP_SLEEP_PD_LP_PERI_PD_EN_W { + LP_SLEEP_PD_LP_PERI_PD_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_lp_dig_power::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_lp_dig_power::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SLEEP_LP_DIG_POWER_SPEC; +impl crate::RegisterSpec for LP_SLEEP_LP_DIG_POWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_sleep_lp_dig_power::R`](R) reader structure"] +impl crate::Readable for LP_SLEEP_LP_DIG_POWER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_sleep_lp_dig_power::W`](W) writer structure"] +impl crate::Writable for LP_SLEEP_LP_DIG_POWER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SLEEP_LP_DIG_POWER to value 0"] +impl crate::Resettable for LP_SLEEP_LP_DIG_POWER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_sleep_lp_regulator0.rs b/esp32p4/src/pmu/lp_sleep_lp_regulator0.rs new file mode 100644 index 0000000000..cae95f92d3 --- /dev/null +++ b/esp32p4/src/pmu/lp_sleep_lp_regulator0.rs @@ -0,0 +1,131 @@ +#[doc = "Register `LP_SLEEP_LP_REGULATOR0` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SLEEP_LP_REGULATOR0` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SLEEP_LP_REGULATOR_SLP_XPD` reader - need_des"] +pub type LP_SLEEP_LP_REGULATOR_SLP_XPD_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_LP_REGULATOR_SLP_XPD` writer - need_des"] +pub type LP_SLEEP_LP_REGULATOR_SLP_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_SLEEP_LP_REGULATOR_XPD` reader - need_des"] +pub type LP_SLEEP_LP_REGULATOR_XPD_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_LP_REGULATOR_XPD` writer - need_des"] +pub type LP_SLEEP_LP_REGULATOR_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_SLEEP_LP_REGULATOR_SLP_DBIAS` reader - need_des"] +pub type LP_SLEEP_LP_REGULATOR_SLP_DBIAS_R = crate::FieldReader; +#[doc = "Field `LP_SLEEP_LP_REGULATOR_SLP_DBIAS` writer - need_des"] +pub type LP_SLEEP_LP_REGULATOR_SLP_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `LP_SLEEP_LP_REGULATOR_DBIAS` reader - need_des"] +pub type LP_SLEEP_LP_REGULATOR_DBIAS_R = crate::FieldReader; +#[doc = "Field `LP_SLEEP_LP_REGULATOR_DBIAS` writer - need_des"] +pub type LP_SLEEP_LP_REGULATOR_DBIAS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + pub fn lp_sleep_lp_regulator_slp_xpd(&self) -> LP_SLEEP_LP_REGULATOR_SLP_XPD_R { + LP_SLEEP_LP_REGULATOR_SLP_XPD_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + pub fn lp_sleep_lp_regulator_xpd(&self) -> LP_SLEEP_LP_REGULATOR_XPD_R { + LP_SLEEP_LP_REGULATOR_XPD_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + pub fn lp_sleep_lp_regulator_slp_dbias(&self) -> LP_SLEEP_LP_REGULATOR_SLP_DBIAS_R { + LP_SLEEP_LP_REGULATOR_SLP_DBIAS_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + pub fn lp_sleep_lp_regulator_dbias(&self) -> LP_SLEEP_LP_REGULATOR_DBIAS_R { + LP_SLEEP_LP_REGULATOR_DBIAS_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SLEEP_LP_REGULATOR0") + .field( + "lp_sleep_lp_regulator_slp_xpd", + &format_args!("{}", self.lp_sleep_lp_regulator_slp_xpd().bit()), + ) + .field( + "lp_sleep_lp_regulator_xpd", + &format_args!("{}", self.lp_sleep_lp_regulator_xpd().bit()), + ) + .field( + "lp_sleep_lp_regulator_slp_dbias", + &format_args!("{}", self.lp_sleep_lp_regulator_slp_dbias().bits()), + ) + .field( + "lp_sleep_lp_regulator_dbias", + &format_args!("{}", self.lp_sleep_lp_regulator_dbias().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 21 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_lp_regulator_slp_xpd( + &mut self, + ) -> LP_SLEEP_LP_REGULATOR_SLP_XPD_W { + LP_SLEEP_LP_REGULATOR_SLP_XPD_W::new(self, 21) + } + #[doc = "Bit 22 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_lp_regulator_xpd( + &mut self, + ) -> LP_SLEEP_LP_REGULATOR_XPD_W { + LP_SLEEP_LP_REGULATOR_XPD_W::new(self, 22) + } + #[doc = "Bits 23:26 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_lp_regulator_slp_dbias( + &mut self, + ) -> LP_SLEEP_LP_REGULATOR_SLP_DBIAS_W { + LP_SLEEP_LP_REGULATOR_SLP_DBIAS_W::new(self, 23) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_lp_regulator_dbias( + &mut self, + ) -> LP_SLEEP_LP_REGULATOR_DBIAS_W { + LP_SLEEP_LP_REGULATOR_DBIAS_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_lp_regulator0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_lp_regulator0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SLEEP_LP_REGULATOR0_SPEC; +impl crate::RegisterSpec for LP_SLEEP_LP_REGULATOR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_sleep_lp_regulator0::R`](R) reader structure"] +impl crate::Readable for LP_SLEEP_LP_REGULATOR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_sleep_lp_regulator0::W`](W) writer structure"] +impl crate::Writable for LP_SLEEP_LP_REGULATOR0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SLEEP_LP_REGULATOR0 to value 0xc660_0000"] +impl crate::Resettable for LP_SLEEP_LP_REGULATOR0_SPEC { + const RESET_VALUE: Self::Ux = 0xc660_0000; +} diff --git a/esp32p4/src/pmu/lp_sleep_lp_regulator1.rs b/esp32p4/src/pmu/lp_sleep_lp_regulator1.rs new file mode 100644 index 0000000000..6131880203 --- /dev/null +++ b/esp32p4/src/pmu/lp_sleep_lp_regulator1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `LP_SLEEP_LP_REGULATOR1` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SLEEP_LP_REGULATOR1` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SLEEP_LP_REGULATOR_DRV_B` reader - need_des"] +pub type LP_SLEEP_LP_REGULATOR_DRV_B_R = crate::FieldReader; +#[doc = "Field `LP_SLEEP_LP_REGULATOR_DRV_B` writer - need_des"] +pub type LP_SLEEP_LP_REGULATOR_DRV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 26:31 - need_des"] + #[inline(always)] + pub fn lp_sleep_lp_regulator_drv_b(&self) -> LP_SLEEP_LP_REGULATOR_DRV_B_R { + LP_SLEEP_LP_REGULATOR_DRV_B_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SLEEP_LP_REGULATOR1") + .field( + "lp_sleep_lp_regulator_drv_b", + &format_args!("{}", self.lp_sleep_lp_regulator_drv_b().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 26:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_lp_regulator_drv_b( + &mut self, + ) -> LP_SLEEP_LP_REGULATOR_DRV_B_W { + LP_SLEEP_LP_REGULATOR_DRV_B_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_lp_regulator1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_lp_regulator1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SLEEP_LP_REGULATOR1_SPEC; +impl crate::RegisterSpec for LP_SLEEP_LP_REGULATOR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_sleep_lp_regulator1::R`](R) reader structure"] +impl crate::Readable for LP_SLEEP_LP_REGULATOR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_sleep_lp_regulator1::W`](W) writer structure"] +impl crate::Writable for LP_SLEEP_LP_REGULATOR1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SLEEP_LP_REGULATOR1 to value 0"] +impl crate::Resettable for LP_SLEEP_LP_REGULATOR1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/lp_sleep_xtal.rs b/esp32p4/src/pmu/lp_sleep_xtal.rs new file mode 100644 index 0000000000..9ecd1a733b --- /dev/null +++ b/esp32p4/src/pmu/lp_sleep_xtal.rs @@ -0,0 +1,66 @@ +#[doc = "Register `LP_SLEEP_XTAL` reader"] +pub type R = crate::R; +#[doc = "Register `LP_SLEEP_XTAL` writer"] +pub type W = crate::W; +#[doc = "Field `LP_SLEEP_XPD_XTAL` reader - need_des"] +pub type LP_SLEEP_XPD_XTAL_R = crate::BitReader; +#[doc = "Field `LP_SLEEP_XPD_XTAL` writer - need_des"] +pub type LP_SLEEP_XPD_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_sleep_xpd_xtal(&self) -> LP_SLEEP_XPD_XTAL_R { + LP_SLEEP_XPD_XTAL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LP_SLEEP_XTAL") + .field( + "lp_sleep_xpd_xtal", + &format_args!("{}", self.lp_sleep_xpd_xtal().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_sleep_xpd_xtal(&mut self) -> LP_SLEEP_XPD_XTAL_W { + LP_SLEEP_XPD_XTAL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_sleep_xtal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_sleep_xtal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LP_SLEEP_XTAL_SPEC; +impl crate::RegisterSpec for LP_SLEEP_XTAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lp_sleep_xtal::R`](R) reader structure"] +impl crate::Readable for LP_SLEEP_XTAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lp_sleep_xtal::W`](W) writer structure"] +impl crate::Writable for LP_SLEEP_XTAL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LP_SLEEP_XTAL to value 0x8000_0000"] +impl crate::Resettable for LP_SLEEP_XTAL_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_0000; +} diff --git a/esp32p4/src/pmu/main_state.rs b/esp32p4/src/pmu/main_state.rs new file mode 100644 index 0000000000..fcd1bb48d8 --- /dev/null +++ b/esp32p4/src/pmu/main_state.rs @@ -0,0 +1,99 @@ +#[doc = "Register `MAIN_STATE` reader"] +pub type R = crate::R; +#[doc = "Register `MAIN_STATE` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE_CALI_PMU_CNTL` reader - need_des"] +pub type ENABLE_CALI_PMU_CNTL_R = crate::BitReader; +#[doc = "Field `ENABLE_CALI_PMU_CNTL` writer - need_des"] +pub type ENABLE_CALI_PMU_CNTL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PMU_MAIN_LAST_ST_STATE` reader - need_des"] +pub type PMU_MAIN_LAST_ST_STATE_R = crate::FieldReader; +#[doc = "Field `PMU_MAIN_TAR_ST_STATE` reader - need_des"] +pub type PMU_MAIN_TAR_ST_STATE_R = crate::FieldReader; +#[doc = "Field `PMU_MAIN_CUR_ST_STATE` reader - need_des"] +pub type PMU_MAIN_CUR_ST_STATE_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn enable_cali_pmu_cntl(&self) -> ENABLE_CALI_PMU_CNTL_R { + ENABLE_CALI_PMU_CNTL_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 11:17 - need_des"] + #[inline(always)] + pub fn pmu_main_last_st_state(&self) -> PMU_MAIN_LAST_ST_STATE_R { + PMU_MAIN_LAST_ST_STATE_R::new(((self.bits >> 11) & 0x7f) as u8) + } + #[doc = "Bits 18:24 - need_des"] + #[inline(always)] + pub fn pmu_main_tar_st_state(&self) -> PMU_MAIN_TAR_ST_STATE_R { + PMU_MAIN_TAR_ST_STATE_R::new(((self.bits >> 18) & 0x7f) as u8) + } + #[doc = "Bits 25:31 - need_des"] + #[inline(always)] + pub fn pmu_main_cur_st_state(&self) -> PMU_MAIN_CUR_ST_STATE_R { + PMU_MAIN_CUR_ST_STATE_R::new(((self.bits >> 25) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MAIN_STATE") + .field( + "enable_cali_pmu_cntl", + &format_args!("{}", self.enable_cali_pmu_cntl().bit()), + ) + .field( + "pmu_main_last_st_state", + &format_args!("{}", self.pmu_main_last_st_state().bits()), + ) + .field( + "pmu_main_tar_st_state", + &format_args!("{}", self.pmu_main_tar_st_state().bits()), + ) + .field( + "pmu_main_cur_st_state", + &format_args!("{}", self.pmu_main_cur_st_state().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn enable_cali_pmu_cntl(&mut self) -> ENABLE_CALI_PMU_CNTL_W { + ENABLE_CALI_PMU_CNTL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_state::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`main_state::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MAIN_STATE_SPEC; +impl crate::RegisterSpec for MAIN_STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`main_state::R`](R) reader structure"] +impl crate::Readable for MAIN_STATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`main_state::W`](W) writer structure"] +impl crate::Writable for MAIN_STATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MAIN_STATE to value 0x0810_0801"] +impl crate::Resettable for MAIN_STATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0810_0801; +} diff --git a/esp32p4/src/pmu/por_status.rs b/esp32p4/src/pmu/por_status.rs new file mode 100644 index 0000000000..dca209c372 --- /dev/null +++ b/esp32p4/src/pmu/por_status.rs @@ -0,0 +1,36 @@ +#[doc = "Register `POR_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `POR_DONE` reader - need_des"] +pub type POR_DONE_R = crate::BitReader; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn por_done(&self) -> POR_DONE_R { + POR_DONE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POR_STATUS") + .field("por_done", &format_args!("{}", self.por_done().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`por_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POR_STATUS_SPEC; +impl crate::RegisterSpec for POR_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`por_status::R`](R) reader structure"] +impl crate::Readable for POR_STATUS_SPEC {} +#[doc = "`reset()` method sets POR_STATUS to value 0x8000_0000"] +impl crate::Resettable for POR_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_0000; +} diff --git a/esp32p4/src/pmu/power_ck_wait_cntl.rs b/esp32p4/src/pmu/power_ck_wait_cntl.rs new file mode 100644 index 0000000000..f7d373052e --- /dev/null +++ b/esp32p4/src/pmu/power_ck_wait_cntl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `POWER_CK_WAIT_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_CK_WAIT_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `PMU_WAIT_XTL_STABLE` reader - need_des"] +pub type PMU_WAIT_XTL_STABLE_R = crate::FieldReader; +#[doc = "Field `PMU_WAIT_XTL_STABLE` writer - need_des"] +pub type PMU_WAIT_XTL_STABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `PMU_WAIT_PLL_STABLE` reader - need_des"] +pub type PMU_WAIT_PLL_STABLE_R = crate::FieldReader; +#[doc = "Field `PMU_WAIT_PLL_STABLE` writer - need_des"] +pub type PMU_WAIT_PLL_STABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + pub fn pmu_wait_xtl_stable(&self) -> PMU_WAIT_XTL_STABLE_R { + PMU_WAIT_XTL_STABLE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - need_des"] + #[inline(always)] + pub fn pmu_wait_pll_stable(&self) -> PMU_WAIT_PLL_STABLE_R { + PMU_WAIT_PLL_STABLE_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_CK_WAIT_CNTL") + .field( + "pmu_wait_xtl_stable", + &format_args!("{}", self.pmu_wait_xtl_stable().bits()), + ) + .field( + "pmu_wait_pll_stable", + &format_args!("{}", self.pmu_wait_pll_stable().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn pmu_wait_xtl_stable(&mut self) -> PMU_WAIT_XTL_STABLE_W { + PMU_WAIT_XTL_STABLE_W::new(self, 0) + } + #[doc = "Bits 16:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn pmu_wait_pll_stable(&mut self) -> PMU_WAIT_PLL_STABLE_W { + PMU_WAIT_PLL_STABLE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_ck_wait_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_ck_wait_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_CK_WAIT_CNTL_SPEC; +impl crate::RegisterSpec for POWER_CK_WAIT_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_ck_wait_cntl::R`](R) reader structure"] +impl crate::Readable for POWER_CK_WAIT_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_ck_wait_cntl::W`](W) writer structure"] +impl crate::Writable for POWER_CK_WAIT_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_CK_WAIT_CNTL to value 0x0100_0100"] +impl crate::Resettable for POWER_CK_WAIT_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x0100_0100; +} diff --git a/esp32p4/src/pmu/power_dcdc_switch.rs b/esp32p4/src/pmu/power_dcdc_switch.rs new file mode 100644 index 0000000000..35c559e7ea --- /dev/null +++ b/esp32p4/src/pmu/power_dcdc_switch.rs @@ -0,0 +1,85 @@ +#[doc = "Register `POWER_DCDC_SWITCH` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_DCDC_SWITCH` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_DCDC_SWITCH_PU` reader - need_des"] +pub type FORCE_DCDC_SWITCH_PU_R = crate::BitReader; +#[doc = "Field `FORCE_DCDC_SWITCH_PU` writer - need_des"] +pub type FORCE_DCDC_SWITCH_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_DCDC_SWITCH_PD` reader - need_des"] +pub type FORCE_DCDC_SWITCH_PD_R = crate::BitReader; +#[doc = "Field `FORCE_DCDC_SWITCH_PD` writer - need_des"] +pub type FORCE_DCDC_SWITCH_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn force_dcdc_switch_pu(&self) -> FORCE_DCDC_SWITCH_PU_R { + FORCE_DCDC_SWITCH_PU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn force_dcdc_switch_pd(&self) -> FORCE_DCDC_SWITCH_PD_R { + FORCE_DCDC_SWITCH_PD_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_DCDC_SWITCH") + .field( + "force_dcdc_switch_pu", + &format_args!("{}", self.force_dcdc_switch_pu().bit()), + ) + .field( + "force_dcdc_switch_pd", + &format_args!("{}", self.force_dcdc_switch_pd().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_dcdc_switch_pu(&mut self) -> FORCE_DCDC_SWITCH_PU_W { + FORCE_DCDC_SWITCH_PU_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_dcdc_switch_pd(&mut self) -> FORCE_DCDC_SWITCH_PD_W { + FORCE_DCDC_SWITCH_PD_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_dcdc_switch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_dcdc_switch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_DCDC_SWITCH_SPEC; +impl crate::RegisterSpec for POWER_DCDC_SWITCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_dcdc_switch::R`](R) reader structure"] +impl crate::Readable for POWER_DCDC_SWITCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_dcdc_switch::W`](W) writer structure"] +impl crate::Writable for POWER_DCDC_SWITCH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_DCDC_SWITCH to value 0x01"] +impl crate::Resettable for POWER_DCDC_SWITCH_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/pmu/power_hp_pad.rs b/esp32p4/src/pmu/power_hp_pad.rs new file mode 100644 index 0000000000..de71b62d3a --- /dev/null +++ b/esp32p4/src/pmu/power_hp_pad.rs @@ -0,0 +1,85 @@ +#[doc = "Register `POWER_HP_PAD` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_HP_PAD` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_HP_PAD_NO_ISO_ALL` reader - need_des"] +pub type FORCE_HP_PAD_NO_ISO_ALL_R = crate::BitReader; +#[doc = "Field `FORCE_HP_PAD_NO_ISO_ALL` writer - need_des"] +pub type FORCE_HP_PAD_NO_ISO_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_HP_PAD_ISO_ALL` reader - need_des"] +pub type FORCE_HP_PAD_ISO_ALL_R = crate::BitReader; +#[doc = "Field `FORCE_HP_PAD_ISO_ALL` writer - need_des"] +pub type FORCE_HP_PAD_ISO_ALL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn force_hp_pad_no_iso_all(&self) -> FORCE_HP_PAD_NO_ISO_ALL_R { + FORCE_HP_PAD_NO_ISO_ALL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn force_hp_pad_iso_all(&self) -> FORCE_HP_PAD_ISO_ALL_R { + FORCE_HP_PAD_ISO_ALL_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_HP_PAD") + .field( + "force_hp_pad_no_iso_all", + &format_args!("{}", self.force_hp_pad_no_iso_all().bit()), + ) + .field( + "force_hp_pad_iso_all", + &format_args!("{}", self.force_hp_pad_iso_all().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_hp_pad_no_iso_all(&mut self) -> FORCE_HP_PAD_NO_ISO_ALL_W { + FORCE_HP_PAD_NO_ISO_ALL_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_hp_pad_iso_all(&mut self) -> FORCE_HP_PAD_ISO_ALL_W { + FORCE_HP_PAD_ISO_ALL_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_hp_pad::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_hp_pad::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_HP_PAD_SPEC; +impl crate::RegisterSpec for POWER_HP_PAD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_hp_pad::R`](R) reader structure"] +impl crate::Readable for POWER_HP_PAD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_hp_pad::W`](W) writer structure"] +impl crate::Writable for POWER_HP_PAD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_HP_PAD to value 0"] +impl crate::Resettable for POWER_HP_PAD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/power_pd_cnnt_cntl.rs b/esp32p4/src/pmu/power_pd_cnnt_cntl.rs new file mode 100644 index 0000000000..19da2e42c6 --- /dev/null +++ b/esp32p4/src/pmu/power_pd_cnnt_cntl.rs @@ -0,0 +1,161 @@ +#[doc = "Register `POWER_PD_CNNT_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_PD_CNNT_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_CNNT_RESET` reader - need_des"] +pub type FORCE_CNNT_RESET_R = crate::BitReader; +#[doc = "Field `FORCE_CNNT_RESET` writer - need_des"] +pub type FORCE_CNNT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_CNNT_ISO` reader - need_des"] +pub type FORCE_CNNT_ISO_R = crate::BitReader; +#[doc = "Field `FORCE_CNNT_ISO` writer - need_des"] +pub type FORCE_CNNT_ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_CNNT_PU` reader - need_des"] +pub type FORCE_CNNT_PU_R = crate::BitReader; +#[doc = "Field `FORCE_CNNT_PU` writer - need_des"] +pub type FORCE_CNNT_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_CNNT_NO_RESET` reader - need_des"] +pub type FORCE_CNNT_NO_RESET_R = crate::BitReader; +#[doc = "Field `FORCE_CNNT_NO_RESET` writer - need_des"] +pub type FORCE_CNNT_NO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_CNNT_NO_ISO` reader - need_des"] +pub type FORCE_CNNT_NO_ISO_R = crate::BitReader; +#[doc = "Field `FORCE_CNNT_NO_ISO` writer - need_des"] +pub type FORCE_CNNT_NO_ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_CNNT_PD` reader - need_des"] +pub type FORCE_CNNT_PD_R = crate::BitReader; +#[doc = "Field `FORCE_CNNT_PD` writer - need_des"] +pub type FORCE_CNNT_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn force_cnnt_reset(&self) -> FORCE_CNNT_RESET_R { + FORCE_CNNT_RESET_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn force_cnnt_iso(&self) -> FORCE_CNNT_ISO_R { + FORCE_CNNT_ISO_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + pub fn force_cnnt_pu(&self) -> FORCE_CNNT_PU_R { + FORCE_CNNT_PU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + pub fn force_cnnt_no_reset(&self) -> FORCE_CNNT_NO_RESET_R { + FORCE_CNNT_NO_RESET_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + pub fn force_cnnt_no_iso(&self) -> FORCE_CNNT_NO_ISO_R { + FORCE_CNNT_NO_ISO_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + pub fn force_cnnt_pd(&self) -> FORCE_CNNT_PD_R { + FORCE_CNNT_PD_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_PD_CNNT_CNTL") + .field( + "force_cnnt_reset", + &format_args!("{}", self.force_cnnt_reset().bit()), + ) + .field( + "force_cnnt_iso", + &format_args!("{}", self.force_cnnt_iso().bit()), + ) + .field( + "force_cnnt_pu", + &format_args!("{}", self.force_cnnt_pu().bit()), + ) + .field( + "force_cnnt_no_reset", + &format_args!("{}", self.force_cnnt_no_reset().bit()), + ) + .field( + "force_cnnt_no_iso", + &format_args!("{}", self.force_cnnt_no_iso().bit()), + ) + .field( + "force_cnnt_pd", + &format_args!("{}", self.force_cnnt_pd().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_cnnt_reset(&mut self) -> FORCE_CNNT_RESET_W { + FORCE_CNNT_RESET_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_cnnt_iso(&mut self) -> FORCE_CNNT_ISO_W { + FORCE_CNNT_ISO_W::new(self, 1) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_cnnt_pu(&mut self) -> FORCE_CNNT_PU_W { + FORCE_CNNT_PU_W::new(self, 2) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_cnnt_no_reset(&mut self) -> FORCE_CNNT_NO_RESET_W { + FORCE_CNNT_NO_RESET_W::new(self, 3) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_cnnt_no_iso(&mut self) -> FORCE_CNNT_NO_ISO_W { + FORCE_CNNT_NO_ISO_W::new(self, 4) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_cnnt_pd(&mut self) -> FORCE_CNNT_PD_W { + FORCE_CNNT_PD_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_cnnt_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_cnnt_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_PD_CNNT_CNTL_SPEC; +impl crate::RegisterSpec for POWER_PD_CNNT_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_pd_cnnt_cntl::R`](R) reader structure"] +impl crate::Readable for POWER_PD_CNNT_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_pd_cnnt_cntl::W`](W) writer structure"] +impl crate::Writable for POWER_PD_CNNT_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_PD_CNNT_CNTL to value 0x1c"] +impl crate::Resettable for POWER_PD_CNNT_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x1c; +} diff --git a/esp32p4/src/pmu/power_pd_cnnt_mask.rs b/esp32p4/src/pmu/power_pd_cnnt_mask.rs new file mode 100644 index 0000000000..caf0e83cb4 --- /dev/null +++ b/esp32p4/src/pmu/power_pd_cnnt_mask.rs @@ -0,0 +1,85 @@ +#[doc = "Register `POWER_PD_CNNT_MASK` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_PD_CNNT_MASK` writer"] +pub type W = crate::W; +#[doc = "Field `XPD_CNNT_MASK` reader - need_des"] +pub type XPD_CNNT_MASK_R = crate::FieldReader; +#[doc = "Field `XPD_CNNT_MASK` writer - need_des"] +pub type XPD_CNNT_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PD_CNNT_MASK` reader - need_des"] +pub type PD_CNNT_MASK_R = crate::FieldReader; +#[doc = "Field `PD_CNNT_MASK` writer - need_des"] +pub type PD_CNNT_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + pub fn xpd_cnnt_mask(&self) -> XPD_CNNT_MASK_R { + XPD_CNNT_MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + pub fn pd_cnnt_mask(&self) -> PD_CNNT_MASK_R { + PD_CNNT_MASK_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_PD_CNNT_MASK") + .field( + "xpd_cnnt_mask", + &format_args!("{}", self.xpd_cnnt_mask().bits()), + ) + .field( + "pd_cnnt_mask", + &format_args!("{}", self.pd_cnnt_mask().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + #[must_use] + pub fn xpd_cnnt_mask(&mut self) -> XPD_CNNT_MASK_W { + XPD_CNNT_MASK_W::new(self, 0) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn pd_cnnt_mask(&mut self) -> PD_CNNT_MASK_W { + PD_CNNT_MASK_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_cnnt_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_cnnt_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_PD_CNNT_MASK_SPEC; +impl crate::RegisterSpec for POWER_PD_CNNT_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_pd_cnnt_mask::R`](R) reader structure"] +impl crate::Readable for POWER_PD_CNNT_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_pd_cnnt_mask::W`](W) writer structure"] +impl crate::Writable for POWER_PD_CNNT_MASK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_PD_CNNT_MASK to value 0"] +impl crate::Resettable for POWER_PD_CNNT_MASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/power_pd_hpmem_cntl.rs b/esp32p4/src/pmu/power_pd_hpmem_cntl.rs new file mode 100644 index 0000000000..462779a5a9 --- /dev/null +++ b/esp32p4/src/pmu/power_pd_hpmem_cntl.rs @@ -0,0 +1,161 @@ +#[doc = "Register `POWER_PD_HPMEM_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_PD_HPMEM_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_HP_MEM_RESET` reader - need_des"] +pub type FORCE_HP_MEM_RESET_R = crate::BitReader; +#[doc = "Field `FORCE_HP_MEM_RESET` writer - need_des"] +pub type FORCE_HP_MEM_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_HP_MEM_ISO` reader - need_des"] +pub type FORCE_HP_MEM_ISO_R = crate::BitReader; +#[doc = "Field `FORCE_HP_MEM_ISO` writer - need_des"] +pub type FORCE_HP_MEM_ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_HP_MEM_PU` reader - need_des"] +pub type FORCE_HP_MEM_PU_R = crate::BitReader; +#[doc = "Field `FORCE_HP_MEM_PU` writer - need_des"] +pub type FORCE_HP_MEM_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_HP_MEM_NO_RESET` reader - need_des"] +pub type FORCE_HP_MEM_NO_RESET_R = crate::BitReader; +#[doc = "Field `FORCE_HP_MEM_NO_RESET` writer - need_des"] +pub type FORCE_HP_MEM_NO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_HP_MEM_NO_ISO` reader - need_des"] +pub type FORCE_HP_MEM_NO_ISO_R = crate::BitReader; +#[doc = "Field `FORCE_HP_MEM_NO_ISO` writer - need_des"] +pub type FORCE_HP_MEM_NO_ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_HP_MEM_PD` reader - need_des"] +pub type FORCE_HP_MEM_PD_R = crate::BitReader; +#[doc = "Field `FORCE_HP_MEM_PD` writer - need_des"] +pub type FORCE_HP_MEM_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn force_hp_mem_reset(&self) -> FORCE_HP_MEM_RESET_R { + FORCE_HP_MEM_RESET_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn force_hp_mem_iso(&self) -> FORCE_HP_MEM_ISO_R { + FORCE_HP_MEM_ISO_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + pub fn force_hp_mem_pu(&self) -> FORCE_HP_MEM_PU_R { + FORCE_HP_MEM_PU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + pub fn force_hp_mem_no_reset(&self) -> FORCE_HP_MEM_NO_RESET_R { + FORCE_HP_MEM_NO_RESET_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + pub fn force_hp_mem_no_iso(&self) -> FORCE_HP_MEM_NO_ISO_R { + FORCE_HP_MEM_NO_ISO_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + pub fn force_hp_mem_pd(&self) -> FORCE_HP_MEM_PD_R { + FORCE_HP_MEM_PD_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_PD_HPMEM_CNTL") + .field( + "force_hp_mem_reset", + &format_args!("{}", self.force_hp_mem_reset().bit()), + ) + .field( + "force_hp_mem_iso", + &format_args!("{}", self.force_hp_mem_iso().bit()), + ) + .field( + "force_hp_mem_pu", + &format_args!("{}", self.force_hp_mem_pu().bit()), + ) + .field( + "force_hp_mem_no_reset", + &format_args!("{}", self.force_hp_mem_no_reset().bit()), + ) + .field( + "force_hp_mem_no_iso", + &format_args!("{}", self.force_hp_mem_no_iso().bit()), + ) + .field( + "force_hp_mem_pd", + &format_args!("{}", self.force_hp_mem_pd().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_hp_mem_reset(&mut self) -> FORCE_HP_MEM_RESET_W { + FORCE_HP_MEM_RESET_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_hp_mem_iso(&mut self) -> FORCE_HP_MEM_ISO_W { + FORCE_HP_MEM_ISO_W::new(self, 1) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_hp_mem_pu(&mut self) -> FORCE_HP_MEM_PU_W { + FORCE_HP_MEM_PU_W::new(self, 2) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_hp_mem_no_reset(&mut self) -> FORCE_HP_MEM_NO_RESET_W { + FORCE_HP_MEM_NO_RESET_W::new(self, 3) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_hp_mem_no_iso(&mut self) -> FORCE_HP_MEM_NO_ISO_W { + FORCE_HP_MEM_NO_ISO_W::new(self, 4) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_hp_mem_pd(&mut self) -> FORCE_HP_MEM_PD_W { + FORCE_HP_MEM_PD_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_hpmem_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_hpmem_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_PD_HPMEM_CNTL_SPEC; +impl crate::RegisterSpec for POWER_PD_HPMEM_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_pd_hpmem_cntl::R`](R) reader structure"] +impl crate::Readable for POWER_PD_HPMEM_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_pd_hpmem_cntl::W`](W) writer structure"] +impl crate::Writable for POWER_PD_HPMEM_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_PD_HPMEM_CNTL to value 0x1c"] +impl crate::Resettable for POWER_PD_HPMEM_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x1c; +} diff --git a/esp32p4/src/pmu/power_pd_hpmem_mask.rs b/esp32p4/src/pmu/power_pd_hpmem_mask.rs new file mode 100644 index 0000000000..382d77a612 --- /dev/null +++ b/esp32p4/src/pmu/power_pd_hpmem_mask.rs @@ -0,0 +1,85 @@ +#[doc = "Register `POWER_PD_HPMEM_MASK` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_PD_HPMEM_MASK` writer"] +pub type W = crate::W; +#[doc = "Field `XPD_HP_MEM_MASK` reader - need_des"] +pub type XPD_HP_MEM_MASK_R = crate::FieldReader; +#[doc = "Field `XPD_HP_MEM_MASK` writer - need_des"] +pub type XPD_HP_MEM_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PD_HP_MEM_MASK` reader - need_des"] +pub type PD_HP_MEM_MASK_R = crate::FieldReader; +#[doc = "Field `PD_HP_MEM_MASK` writer - need_des"] +pub type PD_HP_MEM_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - need_des"] + #[inline(always)] + pub fn xpd_hp_mem_mask(&self) -> XPD_HP_MEM_MASK_R { + XPD_HP_MEM_MASK_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 26:31 - need_des"] + #[inline(always)] + pub fn pd_hp_mem_mask(&self) -> PD_HP_MEM_MASK_R { + PD_HP_MEM_MASK_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_PD_HPMEM_MASK") + .field( + "xpd_hp_mem_mask", + &format_args!("{}", self.xpd_hp_mem_mask().bits()), + ) + .field( + "pd_hp_mem_mask", + &format_args!("{}", self.pd_hp_mem_mask().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - need_des"] + #[inline(always)] + #[must_use] + pub fn xpd_hp_mem_mask(&mut self) -> XPD_HP_MEM_MASK_W { + XPD_HP_MEM_MASK_W::new(self, 0) + } + #[doc = "Bits 26:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn pd_hp_mem_mask(&mut self) -> PD_HP_MEM_MASK_W { + PD_HP_MEM_MASK_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_hpmem_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_hpmem_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_PD_HPMEM_MASK_SPEC; +impl crate::RegisterSpec for POWER_PD_HPMEM_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_pd_hpmem_mask::R`](R) reader structure"] +impl crate::Readable for POWER_PD_HPMEM_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_pd_hpmem_mask::W`](W) writer structure"] +impl crate::Writable for POWER_PD_HPMEM_MASK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_PD_HPMEM_MASK to value 0"] +impl crate::Resettable for POWER_PD_HPMEM_MASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/power_pd_lpperi_cntl.rs b/esp32p4/src/pmu/power_pd_lpperi_cntl.rs new file mode 100644 index 0000000000..8c14cffd71 --- /dev/null +++ b/esp32p4/src/pmu/power_pd_lpperi_cntl.rs @@ -0,0 +1,163 @@ +#[doc = "Register `POWER_PD_LPPERI_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_PD_LPPERI_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_LP_PERI_RESET` reader - need_des"] +pub type FORCE_LP_PERI_RESET_R = crate::BitReader; +#[doc = "Field `FORCE_LP_PERI_RESET` writer - need_des"] +pub type FORCE_LP_PERI_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_LP_PERI_ISO` reader - need_des"] +pub type FORCE_LP_PERI_ISO_R = crate::BitReader; +#[doc = "Field `FORCE_LP_PERI_ISO` writer - need_des"] +pub type FORCE_LP_PERI_ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_LP_PERI_PU` reader - need_des"] +pub type FORCE_LP_PERI_PU_R = crate::BitReader; +#[doc = "Field `FORCE_LP_PERI_PU` writer - need_des"] +pub type FORCE_LP_PERI_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_LP_PERI_NO_RESET` reader - need_des"] +pub type FORCE_LP_PERI_NO_RESET_R = crate::BitReader; +#[doc = "Field `FORCE_LP_PERI_NO_RESET` writer - need_des"] +pub type FORCE_LP_PERI_NO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_LP_PERI_NO_ISO` reader - need_des"] +pub type FORCE_LP_PERI_NO_ISO_R = crate::BitReader; +#[doc = "Field `FORCE_LP_PERI_NO_ISO` writer - need_des"] +pub type FORCE_LP_PERI_NO_ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_LP_PERI_PD` reader - need_des"] +pub type FORCE_LP_PERI_PD_R = crate::BitReader; +#[doc = "Field `FORCE_LP_PERI_PD` writer - need_des"] +pub type FORCE_LP_PERI_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn force_lp_peri_reset(&self) -> FORCE_LP_PERI_RESET_R { + FORCE_LP_PERI_RESET_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn force_lp_peri_iso(&self) -> FORCE_LP_PERI_ISO_R { + FORCE_LP_PERI_ISO_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + pub fn force_lp_peri_pu(&self) -> FORCE_LP_PERI_PU_R { + FORCE_LP_PERI_PU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + pub fn force_lp_peri_no_reset(&self) -> FORCE_LP_PERI_NO_RESET_R { + FORCE_LP_PERI_NO_RESET_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + pub fn force_lp_peri_no_iso(&self) -> FORCE_LP_PERI_NO_ISO_R { + FORCE_LP_PERI_NO_ISO_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + pub fn force_lp_peri_pd(&self) -> FORCE_LP_PERI_PD_R { + FORCE_LP_PERI_PD_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_PD_LPPERI_CNTL") + .field( + "force_lp_peri_reset", + &format_args!("{}", self.force_lp_peri_reset().bit()), + ) + .field( + "force_lp_peri_iso", + &format_args!("{}", self.force_lp_peri_iso().bit()), + ) + .field( + "force_lp_peri_pu", + &format_args!("{}", self.force_lp_peri_pu().bit()), + ) + .field( + "force_lp_peri_no_reset", + &format_args!("{}", self.force_lp_peri_no_reset().bit()), + ) + .field( + "force_lp_peri_no_iso", + &format_args!("{}", self.force_lp_peri_no_iso().bit()), + ) + .field( + "force_lp_peri_pd", + &format_args!("{}", self.force_lp_peri_pd().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_lp_peri_reset(&mut self) -> FORCE_LP_PERI_RESET_W { + FORCE_LP_PERI_RESET_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_lp_peri_iso(&mut self) -> FORCE_LP_PERI_ISO_W { + FORCE_LP_PERI_ISO_W::new(self, 1) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_lp_peri_pu(&mut self) -> FORCE_LP_PERI_PU_W { + FORCE_LP_PERI_PU_W::new(self, 2) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_lp_peri_no_reset( + &mut self, + ) -> FORCE_LP_PERI_NO_RESET_W { + FORCE_LP_PERI_NO_RESET_W::new(self, 3) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_lp_peri_no_iso(&mut self) -> FORCE_LP_PERI_NO_ISO_W { + FORCE_LP_PERI_NO_ISO_W::new(self, 4) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_lp_peri_pd(&mut self) -> FORCE_LP_PERI_PD_W { + FORCE_LP_PERI_PD_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_lpperi_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_lpperi_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_PD_LPPERI_CNTL_SPEC; +impl crate::RegisterSpec for POWER_PD_LPPERI_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_pd_lpperi_cntl::R`](R) reader structure"] +impl crate::Readable for POWER_PD_LPPERI_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_pd_lpperi_cntl::W`](W) writer structure"] +impl crate::Writable for POWER_PD_LPPERI_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_PD_LPPERI_CNTL to value 0x1c"] +impl crate::Resettable for POWER_PD_LPPERI_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x1c; +} diff --git a/esp32p4/src/pmu/power_pd_lpperi_mask.rs b/esp32p4/src/pmu/power_pd_lpperi_mask.rs new file mode 100644 index 0000000000..fc8fa330ff --- /dev/null +++ b/esp32p4/src/pmu/power_pd_lpperi_mask.rs @@ -0,0 +1,85 @@ +#[doc = "Register `POWER_PD_LPPERI_MASK` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_PD_LPPERI_MASK` writer"] +pub type W = crate::W; +#[doc = "Field `XPD_LP_PERI_MASK` reader - need_des"] +pub type XPD_LP_PERI_MASK_R = crate::FieldReader; +#[doc = "Field `XPD_LP_PERI_MASK` writer - need_des"] +pub type XPD_LP_PERI_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PD_LP_PERI_MASK` reader - need_des"] +pub type PD_LP_PERI_MASK_R = crate::FieldReader; +#[doc = "Field `PD_LP_PERI_MASK` writer - need_des"] +pub type PD_LP_PERI_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + pub fn xpd_lp_peri_mask(&self) -> XPD_LP_PERI_MASK_R { + XPD_LP_PERI_MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + pub fn pd_lp_peri_mask(&self) -> PD_LP_PERI_MASK_R { + PD_LP_PERI_MASK_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_PD_LPPERI_MASK") + .field( + "xpd_lp_peri_mask", + &format_args!("{}", self.xpd_lp_peri_mask().bits()), + ) + .field( + "pd_lp_peri_mask", + &format_args!("{}", self.pd_lp_peri_mask().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + #[must_use] + pub fn xpd_lp_peri_mask(&mut self) -> XPD_LP_PERI_MASK_W { + XPD_LP_PERI_MASK_W::new(self, 0) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn pd_lp_peri_mask(&mut self) -> PD_LP_PERI_MASK_W { + PD_LP_PERI_MASK_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_lpperi_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_lpperi_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_PD_LPPERI_MASK_SPEC; +impl crate::RegisterSpec for POWER_PD_LPPERI_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_pd_lpperi_mask::R`](R) reader structure"] +impl crate::Readable for POWER_PD_LPPERI_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_pd_lpperi_mask::W`](W) writer structure"] +impl crate::Writable for POWER_PD_LPPERI_MASK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_PD_LPPERI_MASK to value 0"] +impl crate::Resettable for POWER_PD_LPPERI_MASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/power_pd_top_cntl.rs b/esp32p4/src/pmu/power_pd_top_cntl.rs new file mode 100644 index 0000000000..1a015d25c0 --- /dev/null +++ b/esp32p4/src/pmu/power_pd_top_cntl.rs @@ -0,0 +1,161 @@ +#[doc = "Register `POWER_PD_TOP_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_PD_TOP_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `FORCE_TOP_RESET` reader - need_des"] +pub type FORCE_TOP_RESET_R = crate::BitReader; +#[doc = "Field `FORCE_TOP_RESET` writer - need_des"] +pub type FORCE_TOP_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_TOP_ISO` reader - need_des"] +pub type FORCE_TOP_ISO_R = crate::BitReader; +#[doc = "Field `FORCE_TOP_ISO` writer - need_des"] +pub type FORCE_TOP_ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_TOP_PU` reader - need_des"] +pub type FORCE_TOP_PU_R = crate::BitReader; +#[doc = "Field `FORCE_TOP_PU` writer - need_des"] +pub type FORCE_TOP_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_TOP_NO_RESET` reader - need_des"] +pub type FORCE_TOP_NO_RESET_R = crate::BitReader; +#[doc = "Field `FORCE_TOP_NO_RESET` writer - need_des"] +pub type FORCE_TOP_NO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_TOP_NO_ISO` reader - need_des"] +pub type FORCE_TOP_NO_ISO_R = crate::BitReader; +#[doc = "Field `FORCE_TOP_NO_ISO` writer - need_des"] +pub type FORCE_TOP_NO_ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_TOP_PD` reader - need_des"] +pub type FORCE_TOP_PD_R = crate::BitReader; +#[doc = "Field `FORCE_TOP_PD` writer - need_des"] +pub type FORCE_TOP_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn force_top_reset(&self) -> FORCE_TOP_RESET_R { + FORCE_TOP_RESET_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + pub fn force_top_iso(&self) -> FORCE_TOP_ISO_R { + FORCE_TOP_ISO_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + pub fn force_top_pu(&self) -> FORCE_TOP_PU_R { + FORCE_TOP_PU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + pub fn force_top_no_reset(&self) -> FORCE_TOP_NO_RESET_R { + FORCE_TOP_NO_RESET_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + pub fn force_top_no_iso(&self) -> FORCE_TOP_NO_ISO_R { + FORCE_TOP_NO_ISO_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + pub fn force_top_pd(&self) -> FORCE_TOP_PD_R { + FORCE_TOP_PD_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_PD_TOP_CNTL") + .field( + "force_top_reset", + &format_args!("{}", self.force_top_reset().bit()), + ) + .field( + "force_top_iso", + &format_args!("{}", self.force_top_iso().bit()), + ) + .field( + "force_top_pu", + &format_args!("{}", self.force_top_pu().bit()), + ) + .field( + "force_top_no_reset", + &format_args!("{}", self.force_top_no_reset().bit()), + ) + .field( + "force_top_no_iso", + &format_args!("{}", self.force_top_no_iso().bit()), + ) + .field( + "force_top_pd", + &format_args!("{}", self.force_top_pd().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_top_reset(&mut self) -> FORCE_TOP_RESET_W { + FORCE_TOP_RESET_W::new(self, 0) + } + #[doc = "Bit 1 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_top_iso(&mut self) -> FORCE_TOP_ISO_W { + FORCE_TOP_ISO_W::new(self, 1) + } + #[doc = "Bit 2 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_top_pu(&mut self) -> FORCE_TOP_PU_W { + FORCE_TOP_PU_W::new(self, 2) + } + #[doc = "Bit 3 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_top_no_reset(&mut self) -> FORCE_TOP_NO_RESET_W { + FORCE_TOP_NO_RESET_W::new(self, 3) + } + #[doc = "Bit 4 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_top_no_iso(&mut self) -> FORCE_TOP_NO_ISO_W { + FORCE_TOP_NO_ISO_W::new(self, 4) + } + #[doc = "Bit 5 - need_des"] + #[inline(always)] + #[must_use] + pub fn force_top_pd(&mut self) -> FORCE_TOP_PD_W { + FORCE_TOP_PD_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_top_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_top_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_PD_TOP_CNTL_SPEC; +impl crate::RegisterSpec for POWER_PD_TOP_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_pd_top_cntl::R`](R) reader structure"] +impl crate::Readable for POWER_PD_TOP_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_pd_top_cntl::W`](W) writer structure"] +impl crate::Writable for POWER_PD_TOP_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_PD_TOP_CNTL to value 0x1c"] +impl crate::Resettable for POWER_PD_TOP_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x1c; +} diff --git a/esp32p4/src/pmu/power_pd_top_mask.rs b/esp32p4/src/pmu/power_pd_top_mask.rs new file mode 100644 index 0000000000..21b72c9064 --- /dev/null +++ b/esp32p4/src/pmu/power_pd_top_mask.rs @@ -0,0 +1,85 @@ +#[doc = "Register `POWER_PD_TOP_MASK` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_PD_TOP_MASK` writer"] +pub type W = crate::W; +#[doc = "Field `XPD_TOP_MASK` reader - need_des"] +pub type XPD_TOP_MASK_R = crate::FieldReader; +#[doc = "Field `XPD_TOP_MASK` writer - need_des"] +pub type XPD_TOP_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PD_TOP_MASK` reader - need_des"] +pub type PD_TOP_MASK_R = crate::FieldReader; +#[doc = "Field `PD_TOP_MASK` writer - need_des"] +pub type PD_TOP_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + pub fn xpd_top_mask(&self) -> XPD_TOP_MASK_R { + XPD_TOP_MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + pub fn pd_top_mask(&self) -> PD_TOP_MASK_R { + PD_TOP_MASK_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_PD_TOP_MASK") + .field( + "xpd_top_mask", + &format_args!("{}", self.xpd_top_mask().bits()), + ) + .field( + "pd_top_mask", + &format_args!("{}", self.pd_top_mask().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - need_des"] + #[inline(always)] + #[must_use] + pub fn xpd_top_mask(&mut self) -> XPD_TOP_MASK_W { + XPD_TOP_MASK_W::new(self, 0) + } + #[doc = "Bits 27:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn pd_top_mask(&mut self) -> PD_TOP_MASK_W { + PD_TOP_MASK_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_pd_top_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_pd_top_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_PD_TOP_MASK_SPEC; +impl crate::RegisterSpec for POWER_PD_TOP_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_pd_top_mask::R`](R) reader structure"] +impl crate::Readable for POWER_PD_TOP_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_pd_top_mask::W`](W) writer structure"] +impl crate::Writable for POWER_PD_TOP_MASK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_PD_TOP_MASK to value 0"] +impl crate::Resettable for POWER_PD_TOP_MASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/power_wait_timer0.rs b/esp32p4/src/pmu/power_wait_timer0.rs new file mode 100644 index 0000000000..d370596452 --- /dev/null +++ b/esp32p4/src/pmu/power_wait_timer0.rs @@ -0,0 +1,104 @@ +#[doc = "Register `POWER_WAIT_TIMER0` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_WAIT_TIMER0` writer"] +pub type W = crate::W; +#[doc = "Field `DG_HP_POWERDOWN_TIMER` reader - need_des"] +pub type DG_HP_POWERDOWN_TIMER_R = crate::FieldReader; +#[doc = "Field `DG_HP_POWERDOWN_TIMER` writer - need_des"] +pub type DG_HP_POWERDOWN_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `DG_HP_POWERUP_TIMER` reader - need_des"] +pub type DG_HP_POWERUP_TIMER_R = crate::FieldReader; +#[doc = "Field `DG_HP_POWERUP_TIMER` writer - need_des"] +pub type DG_HP_POWERUP_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `DG_HP_WAIT_TIMER` reader - need_des"] +pub type DG_HP_WAIT_TIMER_R = crate::FieldReader; +#[doc = "Field `DG_HP_WAIT_TIMER` writer - need_des"] +pub type DG_HP_WAIT_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 5:13 - need_des"] + #[inline(always)] + pub fn dg_hp_powerdown_timer(&self) -> DG_HP_POWERDOWN_TIMER_R { + DG_HP_POWERDOWN_TIMER_R::new(((self.bits >> 5) & 0x01ff) as u16) + } + #[doc = "Bits 14:22 - need_des"] + #[inline(always)] + pub fn dg_hp_powerup_timer(&self) -> DG_HP_POWERUP_TIMER_R { + DG_HP_POWERUP_TIMER_R::new(((self.bits >> 14) & 0x01ff) as u16) + } + #[doc = "Bits 23:31 - need_des"] + #[inline(always)] + pub fn dg_hp_wait_timer(&self) -> DG_HP_WAIT_TIMER_R { + DG_HP_WAIT_TIMER_R::new(((self.bits >> 23) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_WAIT_TIMER0") + .field( + "dg_hp_powerdown_timer", + &format_args!("{}", self.dg_hp_powerdown_timer().bits()), + ) + .field( + "dg_hp_powerup_timer", + &format_args!("{}", self.dg_hp_powerup_timer().bits()), + ) + .field( + "dg_hp_wait_timer", + &format_args!("{}", self.dg_hp_wait_timer().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 5:13 - need_des"] + #[inline(always)] + #[must_use] + pub fn dg_hp_powerdown_timer(&mut self) -> DG_HP_POWERDOWN_TIMER_W { + DG_HP_POWERDOWN_TIMER_W::new(self, 5) + } + #[doc = "Bits 14:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn dg_hp_powerup_timer(&mut self) -> DG_HP_POWERUP_TIMER_W { + DG_HP_POWERUP_TIMER_W::new(self, 14) + } + #[doc = "Bits 23:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn dg_hp_wait_timer(&mut self) -> DG_HP_WAIT_TIMER_W { + DG_HP_WAIT_TIMER_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_wait_timer0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_wait_timer0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_WAIT_TIMER0_SPEC; +impl crate::RegisterSpec for POWER_WAIT_TIMER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_wait_timer0::R`](R) reader structure"] +impl crate::Readable for POWER_WAIT_TIMER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_wait_timer0::W`](W) writer structure"] +impl crate::Writable for POWER_WAIT_TIMER0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_WAIT_TIMER0 to value 0x7fbf_dfe0"] +impl crate::Resettable for POWER_WAIT_TIMER0_SPEC { + const RESET_VALUE: Self::Ux = 0x7fbf_dfe0; +} diff --git a/esp32p4/src/pmu/power_wait_timer1.rs b/esp32p4/src/pmu/power_wait_timer1.rs new file mode 100644 index 0000000000..bb310cdedf --- /dev/null +++ b/esp32p4/src/pmu/power_wait_timer1.rs @@ -0,0 +1,104 @@ +#[doc = "Register `POWER_WAIT_TIMER1` reader"] +pub type R = crate::R; +#[doc = "Register `POWER_WAIT_TIMER1` writer"] +pub type W = crate::W; +#[doc = "Field `DG_LP_POWERDOWN_TIMER` reader - need_des"] +pub type DG_LP_POWERDOWN_TIMER_R = crate::FieldReader; +#[doc = "Field `DG_LP_POWERDOWN_TIMER` writer - need_des"] +pub type DG_LP_POWERDOWN_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `DG_LP_POWERUP_TIMER` reader - need_des"] +pub type DG_LP_POWERUP_TIMER_R = crate::FieldReader; +#[doc = "Field `DG_LP_POWERUP_TIMER` writer - need_des"] +pub type DG_LP_POWERUP_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `DG_LP_WAIT_TIMER` reader - need_des"] +pub type DG_LP_WAIT_TIMER_R = crate::FieldReader; +#[doc = "Field `DG_LP_WAIT_TIMER` writer - need_des"] +pub type DG_LP_WAIT_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 5:13 - need_des"] + #[inline(always)] + pub fn dg_lp_powerdown_timer(&self) -> DG_LP_POWERDOWN_TIMER_R { + DG_LP_POWERDOWN_TIMER_R::new(((self.bits >> 5) & 0x01ff) as u16) + } + #[doc = "Bits 14:22 - need_des"] + #[inline(always)] + pub fn dg_lp_powerup_timer(&self) -> DG_LP_POWERUP_TIMER_R { + DG_LP_POWERUP_TIMER_R::new(((self.bits >> 14) & 0x01ff) as u16) + } + #[doc = "Bits 23:31 - need_des"] + #[inline(always)] + pub fn dg_lp_wait_timer(&self) -> DG_LP_WAIT_TIMER_R { + DG_LP_WAIT_TIMER_R::new(((self.bits >> 23) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWER_WAIT_TIMER1") + .field( + "dg_lp_powerdown_timer", + &format_args!("{}", self.dg_lp_powerdown_timer().bits()), + ) + .field( + "dg_lp_powerup_timer", + &format_args!("{}", self.dg_lp_powerup_timer().bits()), + ) + .field( + "dg_lp_wait_timer", + &format_args!("{}", self.dg_lp_wait_timer().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 5:13 - need_des"] + #[inline(always)] + #[must_use] + pub fn dg_lp_powerdown_timer(&mut self) -> DG_LP_POWERDOWN_TIMER_W { + DG_LP_POWERDOWN_TIMER_W::new(self, 5) + } + #[doc = "Bits 14:22 - need_des"] + #[inline(always)] + #[must_use] + pub fn dg_lp_powerup_timer(&mut self) -> DG_LP_POWERUP_TIMER_W { + DG_LP_POWERUP_TIMER_W::new(self, 14) + } + #[doc = "Bits 23:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn dg_lp_wait_timer(&mut self) -> DG_LP_WAIT_TIMER_W { + DG_LP_WAIT_TIMER_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_wait_timer1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_wait_timer1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWER_WAIT_TIMER1_SPEC; +impl crate::RegisterSpec for POWER_WAIT_TIMER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`power_wait_timer1::R`](R) reader structure"] +impl crate::Readable for POWER_WAIT_TIMER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`power_wait_timer1::W`](W) writer structure"] +impl crate::Writable for POWER_WAIT_TIMER1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POWER_WAIT_TIMER1 to value 0x7fbf_dfe0"] +impl crate::Resettable for POWER_WAIT_TIMER1_SPEC { + const RESET_VALUE: Self::Ux = 0x7fbf_dfe0; +} diff --git a/esp32p4/src/pmu/pwr_state.rs b/esp32p4/src/pmu/pwr_state.rs new file mode 100644 index 0000000000..3df2174da7 --- /dev/null +++ b/esp32p4/src/pmu/pwr_state.rs @@ -0,0 +1,61 @@ +#[doc = "Register `PWR_STATE` reader"] +pub type R = crate::R; +#[doc = "Field `PMU_BACKUP_ST_STATE` reader - need_des"] +pub type PMU_BACKUP_ST_STATE_R = crate::FieldReader; +#[doc = "Field `PMU_LP_PWR_ST_STATE` reader - need_des"] +pub type PMU_LP_PWR_ST_STATE_R = crate::FieldReader; +#[doc = "Field `PMU_HP_PWR_ST_STATE` reader - need_des"] +pub type PMU_HP_PWR_ST_STATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 13:17 - need_des"] + #[inline(always)] + pub fn pmu_backup_st_state(&self) -> PMU_BACKUP_ST_STATE_R { + PMU_BACKUP_ST_STATE_R::new(((self.bits >> 13) & 0x1f) as u8) + } + #[doc = "Bits 18:22 - need_des"] + #[inline(always)] + pub fn pmu_lp_pwr_st_state(&self) -> PMU_LP_PWR_ST_STATE_R { + PMU_LP_PWR_ST_STATE_R::new(((self.bits >> 18) & 0x1f) as u8) + } + #[doc = "Bits 23:31 - need_des"] + #[inline(always)] + pub fn pmu_hp_pwr_st_state(&self) -> PMU_HP_PWR_ST_STATE_R { + PMU_HP_PWR_ST_STATE_R::new(((self.bits >> 23) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWR_STATE") + .field( + "pmu_backup_st_state", + &format_args!("{}", self.pmu_backup_st_state().bits()), + ) + .field( + "pmu_lp_pwr_st_state", + &format_args!("{}", self.pmu_lp_pwr_st_state().bits()), + ) + .field( + "pmu_hp_pwr_st_state", + &format_args!("{}", self.pmu_hp_pwr_st_state().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwr_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWR_STATE_SPEC; +impl crate::RegisterSpec for PWR_STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwr_state::R`](R) reader structure"] +impl crate::Readable for PWR_STATE_SPEC {} +#[doc = "`reset()` method sets PWR_STATE to value 0x0080_2000"] +impl crate::Resettable for PWR_STATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_2000; +} diff --git a/esp32p4/src/pmu/rdn_eco.rs b/esp32p4/src/pmu/rdn_eco.rs new file mode 100644 index 0000000000..3ae3f6ef5b --- /dev/null +++ b/esp32p4/src/pmu/rdn_eco.rs @@ -0,0 +1,77 @@ +#[doc = "Register `RDN_ECO` reader"] +pub type R = crate::R; +#[doc = "Register `RDN_ECO` writer"] +pub type W = crate::W; +#[doc = "Field `PMU_RDN_ECO_RESULT` reader - need_des"] +pub type PMU_RDN_ECO_RESULT_R = crate::BitReader; +#[doc = "Field `PMU_RDN_ECO_EN` reader - need_des"] +pub type PMU_RDN_ECO_EN_R = crate::BitReader; +#[doc = "Field `PMU_RDN_ECO_EN` writer - need_des"] +pub type PMU_RDN_ECO_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - need_des"] + #[inline(always)] + pub fn pmu_rdn_eco_result(&self) -> PMU_RDN_ECO_RESULT_R { + PMU_RDN_ECO_RESULT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn pmu_rdn_eco_en(&self) -> PMU_RDN_ECO_EN_R { + PMU_RDN_ECO_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RDN_ECO") + .field( + "pmu_rdn_eco_result", + &format_args!("{}", self.pmu_rdn_eco_result().bit()), + ) + .field( + "pmu_rdn_eco_en", + &format_args!("{}", self.pmu_rdn_eco_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn pmu_rdn_eco_en(&mut self) -> PMU_RDN_ECO_EN_W { + PMU_RDN_ECO_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdn_eco::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdn_eco::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RDN_ECO_SPEC; +impl crate::RegisterSpec for RDN_ECO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rdn_eco::R`](R) reader structure"] +impl crate::Readable for RDN_ECO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rdn_eco::W`](W) writer structure"] +impl crate::Writable for RDN_ECO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RDN_ECO to value 0"] +impl crate::Resettable for RDN_ECO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/rf_pwc.rs b/esp32p4/src/pmu/rf_pwc.rs new file mode 100644 index 0000000000..8f5f491274 --- /dev/null +++ b/esp32p4/src/pmu/rf_pwc.rs @@ -0,0 +1,180 @@ +#[doc = "Register `RF_PWC` reader"] +pub type R = crate::R; +#[doc = "Register `RF_PWC` writer"] +pub type W = crate::W; +#[doc = "Field `MSPI_PHY_XPD` reader - need_des"] +pub type MSPI_PHY_XPD_R = crate::BitReader; +#[doc = "Field `MSPI_PHY_XPD` writer - need_des"] +pub type MSPI_PHY_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDIO_PLL_XPD` reader - need_des"] +pub type SDIO_PLL_XPD_R = crate::BitReader; +#[doc = "Field `SDIO_PLL_XPD` writer - need_des"] +pub type SDIO_PLL_XPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PERIF_I2C_RSTB` reader - need_des"] +pub type PERIF_I2C_RSTB_R = crate::BitReader; +#[doc = "Field `PERIF_I2C_RSTB` writer - need_des"] +pub type PERIF_I2C_RSTB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XPD_PERIF_I2C` reader - need_des"] +pub type XPD_PERIF_I2C_R = crate::BitReader; +#[doc = "Field `XPD_PERIF_I2C` writer - need_des"] +pub type XPD_PERIF_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XPD_TXRF_I2C` reader - need_des"] +pub type XPD_TXRF_I2C_R = crate::BitReader; +#[doc = "Field `XPD_TXRF_I2C` writer - need_des"] +pub type XPD_TXRF_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XPD_RFRX_PBUS` reader - need_des"] +pub type XPD_RFRX_PBUS_R = crate::BitReader; +#[doc = "Field `XPD_RFRX_PBUS` writer - need_des"] +pub type XPD_RFRX_PBUS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XPD_CKGEN_I2C` reader - need_des"] +pub type XPD_CKGEN_I2C_R = crate::BitReader; +#[doc = "Field `XPD_CKGEN_I2C` writer - need_des"] +pub type XPD_CKGEN_I2C_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 24 - need_des"] + #[inline(always)] + pub fn mspi_phy_xpd(&self) -> MSPI_PHY_XPD_R { + MSPI_PHY_XPD_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + pub fn sdio_pll_xpd(&self) -> SDIO_PLL_XPD_R { + SDIO_PLL_XPD_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + pub fn perif_i2c_rstb(&self) -> PERIF_I2C_RSTB_R { + PERIF_I2C_RSTB_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + pub fn xpd_perif_i2c(&self) -> XPD_PERIF_I2C_R { + XPD_PERIF_I2C_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + pub fn xpd_txrf_i2c(&self) -> XPD_TXRF_I2C_R { + XPD_TXRF_I2C_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + pub fn xpd_rfrx_pbus(&self) -> XPD_RFRX_PBUS_R { + XPD_RFRX_PBUS_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn xpd_ckgen_i2c(&self) -> XPD_CKGEN_I2C_R { + XPD_CKGEN_I2C_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RF_PWC") + .field( + "mspi_phy_xpd", + &format_args!("{}", self.mspi_phy_xpd().bit()), + ) + .field( + "sdio_pll_xpd", + &format_args!("{}", self.sdio_pll_xpd().bit()), + ) + .field( + "perif_i2c_rstb", + &format_args!("{}", self.perif_i2c_rstb().bit()), + ) + .field( + "xpd_perif_i2c", + &format_args!("{}", self.xpd_perif_i2c().bit()), + ) + .field( + "xpd_txrf_i2c", + &format_args!("{}", self.xpd_txrf_i2c().bit()), + ) + .field( + "xpd_rfrx_pbus", + &format_args!("{}", self.xpd_rfrx_pbus().bit()), + ) + .field( + "xpd_ckgen_i2c", + &format_args!("{}", self.xpd_ckgen_i2c().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 24 - need_des"] + #[inline(always)] + #[must_use] + pub fn mspi_phy_xpd(&mut self) -> MSPI_PHY_XPD_W { + MSPI_PHY_XPD_W::new(self, 24) + } + #[doc = "Bit 25 - need_des"] + #[inline(always)] + #[must_use] + pub fn sdio_pll_xpd(&mut self) -> SDIO_PLL_XPD_W { + SDIO_PLL_XPD_W::new(self, 25) + } + #[doc = "Bit 26 - need_des"] + #[inline(always)] + #[must_use] + pub fn perif_i2c_rstb(&mut self) -> PERIF_I2C_RSTB_W { + PERIF_I2C_RSTB_W::new(self, 26) + } + #[doc = "Bit 27 - need_des"] + #[inline(always)] + #[must_use] + pub fn xpd_perif_i2c(&mut self) -> XPD_PERIF_I2C_W { + XPD_PERIF_I2C_W::new(self, 27) + } + #[doc = "Bit 28 - need_des"] + #[inline(always)] + #[must_use] + pub fn xpd_txrf_i2c(&mut self) -> XPD_TXRF_I2C_W { + XPD_TXRF_I2C_W::new(self, 28) + } + #[doc = "Bit 29 - need_des"] + #[inline(always)] + #[must_use] + pub fn xpd_rfrx_pbus(&mut self) -> XPD_RFRX_PBUS_W { + XPD_RFRX_PBUS_W::new(self, 29) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn xpd_ckgen_i2c(&mut self) -> XPD_CKGEN_I2C_W { + XPD_CKGEN_I2C_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rf_pwc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rf_pwc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RF_PWC_SPEC; +impl crate::RegisterSpec for RF_PWC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rf_pwc::R`](R) reader structure"] +impl crate::Readable for RF_PWC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rf_pwc::W`](W) writer structure"] +impl crate::Writable for RF_PWC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RF_PWC to value 0x0800_0000"] +impl crate::Resettable for RF_PWC_SPEC { + const RESET_VALUE: Self::Ux = 0x0800_0000; +} diff --git a/esp32p4/src/pmu/sdio_wakeup_cntl.rs b/esp32p4/src/pmu/sdio_wakeup_cntl.rs new file mode 100644 index 0000000000..a212cc9137 --- /dev/null +++ b/esp32p4/src/pmu/sdio_wakeup_cntl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SDIO_WAKEUP_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `SDIO_WAKEUP_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `SDIO_ACT_DNUM` reader - need_des"] +pub type SDIO_ACT_DNUM_R = crate::FieldReader; +#[doc = "Field `SDIO_ACT_DNUM` writer - need_des"] +pub type SDIO_ACT_DNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - need_des"] + #[inline(always)] + pub fn sdio_act_dnum(&self) -> SDIO_ACT_DNUM_R { + SDIO_ACT_DNUM_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SDIO_WAKEUP_CNTL") + .field( + "sdio_act_dnum", + &format_args!("{}", self.sdio_act_dnum().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - need_des"] + #[inline(always)] + #[must_use] + pub fn sdio_act_dnum(&mut self) -> SDIO_ACT_DNUM_W { + SDIO_ACT_DNUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdio_wakeup_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdio_wakeup_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SDIO_WAKEUP_CNTL_SPEC; +impl crate::RegisterSpec for SDIO_WAKEUP_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sdio_wakeup_cntl::R`](R) reader structure"] +impl crate::Readable for SDIO_WAKEUP_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sdio_wakeup_cntl::W`](W) writer structure"] +impl crate::Writable for SDIO_WAKEUP_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDIO_WAKEUP_CNTL to value 0x03ff"] +impl crate::Resettable for SDIO_WAKEUP_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x03ff; +} diff --git a/esp32p4/src/pmu/slp_wakeup_cntl0.rs b/esp32p4/src/pmu/slp_wakeup_cntl0.rs new file mode 100644 index 0000000000..de6d8070bf --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_cntl0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SLP_WAKEUP_CNTL0` writer"] +pub type W = crate::W; +#[doc = "Field `SLEEP_REQ` writer - need_des"] +pub type SLEEP_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep_req(&mut self) -> SLEEP_REQ_W { + SLEEP_REQ_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_CNTL0_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_CNTL0_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`slp_wakeup_cntl0::W`](W) writer structure"] +impl crate::Writable for SLP_WAKEUP_CNTL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLP_WAKEUP_CNTL0 to value 0"] +impl crate::Resettable for SLP_WAKEUP_CNTL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/slp_wakeup_cntl1.rs b/esp32p4/src/pmu/slp_wakeup_cntl1.rs new file mode 100644 index 0000000000..5098397b8e --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_cntl1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SLP_WAKEUP_CNTL1` reader"] +pub type R = crate::R; +#[doc = "Register `SLP_WAKEUP_CNTL1` writer"] +pub type W = crate::W; +#[doc = "Field `SLEEP_REJECT_ENA` reader - need_des"] +pub type SLEEP_REJECT_ENA_R = crate::FieldReader; +#[doc = "Field `SLEEP_REJECT_ENA` writer - need_des"] +pub type SLEEP_REJECT_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `SLP_REJECT_EN` reader - need_des"] +pub type SLP_REJECT_EN_R = crate::BitReader; +#[doc = "Field `SLP_REJECT_EN` writer - need_des"] +pub type SLP_REJECT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn sleep_reject_ena(&self) -> SLEEP_REJECT_ENA_R { + SLEEP_REJECT_ENA_R::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn slp_reject_en(&self) -> SLP_REJECT_EN_R { + SLP_REJECT_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLP_WAKEUP_CNTL1") + .field( + "sleep_reject_ena", + &format_args!("{}", self.sleep_reject_ena().bits()), + ) + .field( + "slp_reject_en", + &format_args!("{}", self.slp_reject_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep_reject_ena(&mut self) -> SLEEP_REJECT_ENA_W { + SLEEP_REJECT_ENA_W::new(self, 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn slp_reject_en(&mut self) -> SLP_REJECT_EN_W { + SLP_REJECT_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_CNTL1_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_CNTL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slp_wakeup_cntl1::R`](R) reader structure"] +impl crate::Readable for SLP_WAKEUP_CNTL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slp_wakeup_cntl1::W`](W) writer structure"] +impl crate::Writable for SLP_WAKEUP_CNTL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLP_WAKEUP_CNTL1 to value 0"] +impl crate::Resettable for SLP_WAKEUP_CNTL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/slp_wakeup_cntl2.rs b/esp32p4/src/pmu/slp_wakeup_cntl2.rs new file mode 100644 index 0000000000..44ceef52c0 --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_cntl2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SLP_WAKEUP_CNTL2` reader"] +pub type R = crate::R; +#[doc = "Register `SLP_WAKEUP_CNTL2` writer"] +pub type W = crate::W; +#[doc = "Field `WAKEUP_ENA` reader - need_des"] +pub type WAKEUP_ENA_R = crate::FieldReader; +#[doc = "Field `WAKEUP_ENA` writer - need_des"] +pub type WAKEUP_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn wakeup_ena(&self) -> WAKEUP_ENA_R { + WAKEUP_ENA_R::new(self.bits & 0x7fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLP_WAKEUP_CNTL2") + .field("wakeup_ena", &format_args!("{}", self.wakeup_ena().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + #[must_use] + pub fn wakeup_ena(&mut self) -> WAKEUP_ENA_W { + WAKEUP_ENA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_CNTL2_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_CNTL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slp_wakeup_cntl2::R`](R) reader structure"] +impl crate::Readable for SLP_WAKEUP_CNTL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slp_wakeup_cntl2::W`](W) writer structure"] +impl crate::Writable for SLP_WAKEUP_CNTL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLP_WAKEUP_CNTL2 to value 0"] +impl crate::Resettable for SLP_WAKEUP_CNTL2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/slp_wakeup_cntl3.rs b/esp32p4/src/pmu/slp_wakeup_cntl3.rs new file mode 100644 index 0000000000..5784160d05 --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_cntl3.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SLP_WAKEUP_CNTL3` reader"] +pub type R = crate::R; +#[doc = "Register `SLP_WAKEUP_CNTL3` writer"] +pub type W = crate::W; +#[doc = "Field `LP_MIN_SLP_VAL` reader - need_des"] +pub type LP_MIN_SLP_VAL_R = crate::FieldReader; +#[doc = "Field `LP_MIN_SLP_VAL` writer - need_des"] +pub type LP_MIN_SLP_VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `HP_MIN_SLP_VAL` reader - need_des"] +pub type HP_MIN_SLP_VAL_R = crate::FieldReader; +#[doc = "Field `HP_MIN_SLP_VAL` writer - need_des"] +pub type HP_MIN_SLP_VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SLEEP_PRT_SEL` reader - need_des"] +pub type SLEEP_PRT_SEL_R = crate::FieldReader; +#[doc = "Field `SLEEP_PRT_SEL` writer - need_des"] +pub type SLEEP_PRT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + pub fn lp_min_slp_val(&self) -> LP_MIN_SLP_VAL_R { + LP_MIN_SLP_VAL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - need_des"] + #[inline(always)] + pub fn hp_min_slp_val(&self) -> HP_MIN_SLP_VAL_R { + HP_MIN_SLP_VAL_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:17 - need_des"] + #[inline(always)] + pub fn sleep_prt_sel(&self) -> SLEEP_PRT_SEL_R { + SLEEP_PRT_SEL_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLP_WAKEUP_CNTL3") + .field( + "lp_min_slp_val", + &format_args!("{}", self.lp_min_slp_val().bits()), + ) + .field( + "hp_min_slp_val", + &format_args!("{}", self.hp_min_slp_val().bits()), + ) + .field( + "sleep_prt_sel", + &format_args!("{}", self.sleep_prt_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_min_slp_val(&mut self) -> LP_MIN_SLP_VAL_W { + LP_MIN_SLP_VAL_W::new(self, 0) + } + #[doc = "Bits 8:15 - need_des"] + #[inline(always)] + #[must_use] + pub fn hp_min_slp_val(&mut self) -> HP_MIN_SLP_VAL_W { + HP_MIN_SLP_VAL_W::new(self, 8) + } + #[doc = "Bits 16:17 - need_des"] + #[inline(always)] + #[must_use] + pub fn sleep_prt_sel(&mut self) -> SLEEP_PRT_SEL_W { + SLEEP_PRT_SEL_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_CNTL3_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_CNTL3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slp_wakeup_cntl3::R`](R) reader structure"] +impl crate::Readable for SLP_WAKEUP_CNTL3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slp_wakeup_cntl3::W`](W) writer structure"] +impl crate::Writable for SLP_WAKEUP_CNTL3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLP_WAKEUP_CNTL3 to value 0"] +impl crate::Resettable for SLP_WAKEUP_CNTL3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/slp_wakeup_cntl4.rs b/esp32p4/src/pmu/slp_wakeup_cntl4.rs new file mode 100644 index 0000000000..b55198cefc --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_cntl4.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SLP_WAKEUP_CNTL4` writer"] +pub type W = crate::W; +#[doc = "Field `SLP_REJECT_CAUSE_CLR` writer - need_des"] +pub type SLP_REJECT_CAUSE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn slp_reject_cause_clr(&mut self) -> SLP_REJECT_CAUSE_CLR_W { + SLP_REJECT_CAUSE_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl4::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_CNTL4_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_CNTL4_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`slp_wakeup_cntl4::W`](W) writer structure"] +impl crate::Writable for SLP_WAKEUP_CNTL4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLP_WAKEUP_CNTL4 to value 0"] +impl crate::Resettable for SLP_WAKEUP_CNTL4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/slp_wakeup_cntl5.rs b/esp32p4/src/pmu/slp_wakeup_cntl5.rs new file mode 100644 index 0000000000..4bc3674f9d --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_cntl5.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SLP_WAKEUP_CNTL5` reader"] +pub type R = crate::R; +#[doc = "Register `SLP_WAKEUP_CNTL5` writer"] +pub type W = crate::W; +#[doc = "Field `MODEM_WAIT_TARGET` reader - need_des"] +pub type MODEM_WAIT_TARGET_R = crate::FieldReader; +#[doc = "Field `MODEM_WAIT_TARGET` writer - need_des"] +pub type MODEM_WAIT_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +#[doc = "Field `LP_ANA_WAIT_TARGET` reader - need_des"] +pub type LP_ANA_WAIT_TARGET_R = crate::FieldReader; +#[doc = "Field `LP_ANA_WAIT_TARGET` writer - need_des"] +pub type LP_ANA_WAIT_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:19 - need_des"] + #[inline(always)] + pub fn modem_wait_target(&self) -> MODEM_WAIT_TARGET_R { + MODEM_WAIT_TARGET_R::new(self.bits & 0x000f_ffff) + } + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + pub fn lp_ana_wait_target(&self) -> LP_ANA_WAIT_TARGET_R { + LP_ANA_WAIT_TARGET_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLP_WAKEUP_CNTL5") + .field( + "modem_wait_target", + &format_args!("{}", self.modem_wait_target().bits()), + ) + .field( + "lp_ana_wait_target", + &format_args!("{}", self.lp_ana_wait_target().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - need_des"] + #[inline(always)] + #[must_use] + pub fn modem_wait_target(&mut self) -> MODEM_WAIT_TARGET_W { + MODEM_WAIT_TARGET_W::new(self, 0) + } + #[doc = "Bits 24:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_ana_wait_target(&mut self) -> LP_ANA_WAIT_TARGET_W { + LP_ANA_WAIT_TARGET_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_CNTL5_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_CNTL5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slp_wakeup_cntl5::R`](R) reader structure"] +impl crate::Readable for SLP_WAKEUP_CNTL5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slp_wakeup_cntl5::W`](W) writer structure"] +impl crate::Writable for SLP_WAKEUP_CNTL5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLP_WAKEUP_CNTL5 to value 0x0100_0080"] +impl crate::Resettable for SLP_WAKEUP_CNTL5_SPEC { + const RESET_VALUE: Self::Ux = 0x0100_0080; +} diff --git a/esp32p4/src/pmu/slp_wakeup_cntl6.rs b/esp32p4/src/pmu/slp_wakeup_cntl6.rs new file mode 100644 index 0000000000..e3425ca3b9 --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_cntl6.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SLP_WAKEUP_CNTL6` reader"] +pub type R = crate::R; +#[doc = "Register `SLP_WAKEUP_CNTL6` writer"] +pub type W = crate::W; +#[doc = "Field `SOC_WAKEUP_WAIT` reader - need_des"] +pub type SOC_WAKEUP_WAIT_R = crate::FieldReader; +#[doc = "Field `SOC_WAKEUP_WAIT` writer - need_des"] +pub type SOC_WAKEUP_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +#[doc = "Field `SOC_WAKEUP_WAIT_CFG` reader - need_des"] +pub type SOC_WAKEUP_WAIT_CFG_R = crate::FieldReader; +#[doc = "Field `SOC_WAKEUP_WAIT_CFG` writer - need_des"] +pub type SOC_WAKEUP_WAIT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:19 - need_des"] + #[inline(always)] + pub fn soc_wakeup_wait(&self) -> SOC_WAKEUP_WAIT_R { + SOC_WAKEUP_WAIT_R::new(self.bits & 0x000f_ffff) + } + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + pub fn soc_wakeup_wait_cfg(&self) -> SOC_WAKEUP_WAIT_CFG_R { + SOC_WAKEUP_WAIT_CFG_R::new(((self.bits >> 30) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLP_WAKEUP_CNTL6") + .field( + "soc_wakeup_wait", + &format_args!("{}", self.soc_wakeup_wait().bits()), + ) + .field( + "soc_wakeup_wait_cfg", + &format_args!("{}", self.soc_wakeup_wait_cfg().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - need_des"] + #[inline(always)] + #[must_use] + pub fn soc_wakeup_wait(&mut self) -> SOC_WAKEUP_WAIT_W { + SOC_WAKEUP_WAIT_W::new(self, 0) + } + #[doc = "Bits 30:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn soc_wakeup_wait_cfg(&mut self) -> SOC_WAKEUP_WAIT_CFG_W { + SOC_WAKEUP_WAIT_CFG_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_CNTL6_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_CNTL6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slp_wakeup_cntl6::R`](R) reader structure"] +impl crate::Readable for SLP_WAKEUP_CNTL6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slp_wakeup_cntl6::W`](W) writer structure"] +impl crate::Writable for SLP_WAKEUP_CNTL6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLP_WAKEUP_CNTL6 to value 0x80"] +impl crate::Resettable for SLP_WAKEUP_CNTL6_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/pmu/slp_wakeup_cntl7.rs b/esp32p4/src/pmu/slp_wakeup_cntl7.rs new file mode 100644 index 0000000000..6432569080 --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_cntl7.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SLP_WAKEUP_CNTL7` reader"] +pub type R = crate::R; +#[doc = "Register `SLP_WAKEUP_CNTL7` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_WAIT_TARGET` reader - need_des"] +pub type ANA_WAIT_TARGET_R = crate::FieldReader; +#[doc = "Field `ANA_WAIT_TARGET` writer - need_des"] +pub type ANA_WAIT_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - need_des"] + #[inline(always)] + pub fn ana_wait_target(&self) -> ANA_WAIT_TARGET_R { + ANA_WAIT_TARGET_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLP_WAKEUP_CNTL7") + .field( + "ana_wait_target", + &format_args!("{}", self.ana_wait_target().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn ana_wait_target(&mut self) -> ANA_WAIT_TARGET_W { + ANA_WAIT_TARGET_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_CNTL7_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_CNTL7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slp_wakeup_cntl7::R`](R) reader structure"] +impl crate::Readable for SLP_WAKEUP_CNTL7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slp_wakeup_cntl7::W`](W) writer structure"] +impl crate::Writable for SLP_WAKEUP_CNTL7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLP_WAKEUP_CNTL7 to value 0x0001_0000"] +impl crate::Resettable for SLP_WAKEUP_CNTL7_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0000; +} diff --git a/esp32p4/src/pmu/slp_wakeup_cntl8.rs b/esp32p4/src/pmu/slp_wakeup_cntl8.rs new file mode 100644 index 0000000000..fd9a72e533 --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_cntl8.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SLP_WAKEUP_CNTL8` reader"] +pub type R = crate::R; +#[doc = "Register `SLP_WAKEUP_CNTL8` writer"] +pub type W = crate::W; +#[doc = "Field `LP_LITE_WAKEUP_ENA` reader - need_des"] +pub type LP_LITE_WAKEUP_ENA_R = crate::BitReader; +#[doc = "Field `LP_LITE_WAKEUP_ENA` writer - need_des"] +pub type LP_LITE_WAKEUP_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_lite_wakeup_ena(&self) -> LP_LITE_WAKEUP_ENA_R { + LP_LITE_WAKEUP_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLP_WAKEUP_CNTL8") + .field( + "lp_lite_wakeup_ena", + &format_args!("{}", self.lp_lite_wakeup_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn lp_lite_wakeup_ena(&mut self) -> LP_LITE_WAKEUP_ENA_W { + LP_LITE_WAKEUP_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cntl8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slp_wakeup_cntl8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_CNTL8_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_CNTL8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slp_wakeup_cntl8::R`](R) reader structure"] +impl crate::Readable for SLP_WAKEUP_CNTL8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`slp_wakeup_cntl8::W`](W) writer structure"] +impl crate::Writable for SLP_WAKEUP_CNTL8_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLP_WAKEUP_CNTL8 to value 0"] +impl crate::Resettable for SLP_WAKEUP_CNTL8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/slp_wakeup_status0.rs b/esp32p4/src/pmu/slp_wakeup_status0.rs new file mode 100644 index 0000000000..db08f92331 --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_status0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SLP_WAKEUP_STATUS0` reader"] +pub type R = crate::R; +#[doc = "Field `WAKEUP_CAUSE` reader - need_des"] +pub type WAKEUP_CAUSE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn wakeup_cause(&self) -> WAKEUP_CAUSE_R { + WAKEUP_CAUSE_R::new(self.bits & 0x7fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLP_WAKEUP_STATUS0") + .field( + "wakeup_cause", + &format_args!("{}", self.wakeup_cause().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_STATUS0_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_STATUS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slp_wakeup_status0::R`](R) reader structure"] +impl crate::Readable for SLP_WAKEUP_STATUS0_SPEC {} +#[doc = "`reset()` method sets SLP_WAKEUP_STATUS0 to value 0"] +impl crate::Resettable for SLP_WAKEUP_STATUS0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/slp_wakeup_status1.rs b/esp32p4/src/pmu/slp_wakeup_status1.rs new file mode 100644 index 0000000000..7c2f176968 --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_status1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SLP_WAKEUP_STATUS1` reader"] +pub type R = crate::R; +#[doc = "Field `REJECT_CAUSE` reader - need_des"] +pub type REJECT_CAUSE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:30 - need_des"] + #[inline(always)] + pub fn reject_cause(&self) -> REJECT_CAUSE_R { + REJECT_CAUSE_R::new(self.bits & 0x7fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLP_WAKEUP_STATUS1") + .field( + "reject_cause", + &format_args!("{}", self.reject_cause().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_STATUS1_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_STATUS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slp_wakeup_status1::R`](R) reader structure"] +impl crate::Readable for SLP_WAKEUP_STATUS1_SPEC {} +#[doc = "`reset()` method sets SLP_WAKEUP_STATUS1 to value 0"] +impl crate::Resettable for SLP_WAKEUP_STATUS1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/slp_wakeup_status2.rs b/esp32p4/src/pmu/slp_wakeup_status2.rs new file mode 100644 index 0000000000..7694119e30 --- /dev/null +++ b/esp32p4/src/pmu/slp_wakeup_status2.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SLP_WAKEUP_STATUS2` reader"] +pub type R = crate::R; +#[doc = "Field `LP_LITE_WAKEUP_CAUSE` reader - need_des"] +pub type LP_LITE_WAKEUP_CAUSE_R = crate::BitReader; +impl R { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn lp_lite_wakeup_cause(&self) -> LP_LITE_WAKEUP_CAUSE_R { + LP_LITE_WAKEUP_CAUSE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLP_WAKEUP_STATUS2") + .field( + "lp_lite_wakeup_cause", + &format_args!("{}", self.lp_lite_wakeup_cause().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLP_WAKEUP_STATUS2_SPEC; +impl crate::RegisterSpec for SLP_WAKEUP_STATUS2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`slp_wakeup_status2::R`](R) reader structure"] +impl crate::Readable for SLP_WAKEUP_STATUS2_SPEC {} +#[doc = "`reset()` method sets SLP_WAKEUP_STATUS2 to value 0"] +impl crate::Resettable for SLP_WAKEUP_STATUS2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/touch_pwr_cntl.rs b/esp32p4/src/pmu/touch_pwr_cntl.rs new file mode 100644 index 0000000000..3c0ee0ba7b --- /dev/null +++ b/esp32p4/src/pmu/touch_pwr_cntl.rs @@ -0,0 +1,123 @@ +#[doc = "Register `TOUCH_PWR_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `TOUCH_PWR_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `TOUCH_WAIT_CYCLES` reader - need_des"] +pub type TOUCH_WAIT_CYCLES_R = crate::FieldReader; +#[doc = "Field `TOUCH_WAIT_CYCLES` writer - need_des"] +pub type TOUCH_WAIT_CYCLES_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `TOUCH_SLEEP_CYCLES` reader - need_des"] +pub type TOUCH_SLEEP_CYCLES_R = crate::FieldReader; +#[doc = "Field `TOUCH_SLEEP_CYCLES` writer - need_des"] +pub type TOUCH_SLEEP_CYCLES_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `TOUCH_FORCE_DONE` reader - need_des"] +pub type TOUCH_FORCE_DONE_R = crate::BitReader; +#[doc = "Field `TOUCH_FORCE_DONE` writer - need_des"] +pub type TOUCH_FORCE_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TOUCH_SLEEP_TIMER_EN` reader - need_des"] +pub type TOUCH_SLEEP_TIMER_EN_R = crate::BitReader; +#[doc = "Field `TOUCH_SLEEP_TIMER_EN` writer - need_des"] +pub type TOUCH_SLEEP_TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 5:13 - need_des"] + #[inline(always)] + pub fn touch_wait_cycles(&self) -> TOUCH_WAIT_CYCLES_R { + TOUCH_WAIT_CYCLES_R::new(((self.bits >> 5) & 0x01ff) as u16) + } + #[doc = "Bits 14:29 - need_des"] + #[inline(always)] + pub fn touch_sleep_cycles(&self) -> TOUCH_SLEEP_CYCLES_R { + TOUCH_SLEEP_CYCLES_R::new(((self.bits >> 14) & 0xffff) as u16) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + pub fn touch_force_done(&self) -> TOUCH_FORCE_DONE_R { + TOUCH_FORCE_DONE_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + pub fn touch_sleep_timer_en(&self) -> TOUCH_SLEEP_TIMER_EN_R { + TOUCH_SLEEP_TIMER_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TOUCH_PWR_CNTL") + .field( + "touch_wait_cycles", + &format_args!("{}", self.touch_wait_cycles().bits()), + ) + .field( + "touch_sleep_cycles", + &format_args!("{}", self.touch_sleep_cycles().bits()), + ) + .field( + "touch_force_done", + &format_args!("{}", self.touch_force_done().bit()), + ) + .field( + "touch_sleep_timer_en", + &format_args!("{}", self.touch_sleep_timer_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 5:13 - need_des"] + #[inline(always)] + #[must_use] + pub fn touch_wait_cycles(&mut self) -> TOUCH_WAIT_CYCLES_W { + TOUCH_WAIT_CYCLES_W::new(self, 5) + } + #[doc = "Bits 14:29 - need_des"] + #[inline(always)] + #[must_use] + pub fn touch_sleep_cycles(&mut self) -> TOUCH_SLEEP_CYCLES_W { + TOUCH_SLEEP_CYCLES_W::new(self, 14) + } + #[doc = "Bit 30 - need_des"] + #[inline(always)] + #[must_use] + pub fn touch_force_done(&mut self) -> TOUCH_FORCE_DONE_W { + TOUCH_FORCE_DONE_W::new(self, 30) + } + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn touch_sleep_timer_en(&mut self) -> TOUCH_SLEEP_TIMER_EN_W { + TOUCH_SLEEP_TIMER_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`touch_pwr_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`touch_pwr_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TOUCH_PWR_CNTL_SPEC; +impl crate::RegisterSpec for TOUCH_PWR_CNTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`touch_pwr_cntl::R`](R) reader structure"] +impl crate::Readable for TOUCH_PWR_CNTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`touch_pwr_cntl::W`](W) writer structure"] +impl crate::Writable for TOUCH_PWR_CNTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TOUCH_PWR_CNTL to value 0x0019_0140"] +impl crate::Resettable for TOUCH_PWR_CNTL_SPEC { + const RESET_VALUE: Self::Ux = 0x0019_0140; +} diff --git a/esp32p4/src/pmu/vddbat_cfg.rs b/esp32p4/src/pmu/vddbat_cfg.rs new file mode 100644 index 0000000000..f5bbf59835 --- /dev/null +++ b/esp32p4/src/pmu/vddbat_cfg.rs @@ -0,0 +1,66 @@ +#[doc = "Register `VDDBAT_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `VDDBAT_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `ANA_VDDBAT_MODE` reader - need_des"] +pub type ANA_VDDBAT_MODE_R = crate::FieldReader; +#[doc = "Field `VDDBAT_SW_UPDATE` writer - need_des"] +pub type VDDBAT_SW_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - need_des"] + #[inline(always)] + pub fn ana_vddbat_mode(&self) -> ANA_VDDBAT_MODE_R { + ANA_VDDBAT_MODE_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VDDBAT_CFG") + .field( + "ana_vddbat_mode", + &format_args!("{}", self.ana_vddbat_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - need_des"] + #[inline(always)] + #[must_use] + pub fn vddbat_sw_update(&mut self) -> VDDBAT_SW_UPDATE_W { + VDDBAT_SW_UPDATE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vddbat_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vddbat_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VDDBAT_CFG_SPEC; +impl crate::RegisterSpec for VDDBAT_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vddbat_cfg::R`](R) reader structure"] +impl crate::Readable for VDDBAT_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vddbat_cfg::W`](W) writer structure"] +impl crate::Writable for VDDBAT_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VDDBAT_CFG to value 0"] +impl crate::Resettable for VDDBAT_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pmu/xtal_slp.rs b/esp32p4/src/pmu/xtal_slp.rs new file mode 100644 index 0000000000..f1f7574267 --- /dev/null +++ b/esp32p4/src/pmu/xtal_slp.rs @@ -0,0 +1,63 @@ +#[doc = "Register `XTAL_SLP` reader"] +pub type R = crate::R; +#[doc = "Register `XTAL_SLP` writer"] +pub type W = crate::W; +#[doc = "Field `CNT_TARGET` reader - need_des"] +pub type CNT_TARGET_R = crate::FieldReader; +#[doc = "Field `CNT_TARGET` writer - need_des"] +pub type CNT_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - need_des"] + #[inline(always)] + pub fn cnt_target(&self) -> CNT_TARGET_R { + CNT_TARGET_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("XTAL_SLP") + .field("cnt_target", &format_args!("{}", self.cnt_target().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:31 - need_des"] + #[inline(always)] + #[must_use] + pub fn cnt_target(&mut self) -> CNT_TARGET_W { + CNT_TARGET_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xtal_slp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xtal_slp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct XTAL_SLP_SPEC; +impl crate::RegisterSpec for XTAL_SLP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`xtal_slp::R`](R) reader structure"] +impl crate::Readable for XTAL_SLP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`xtal_slp::W`](W) writer structure"] +impl crate::Writable for XTAL_SLP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets XTAL_SLP to value 0x000f_0000"] +impl crate::Resettable for XTAL_SLP_SPEC { + const RESET_VALUE: Self::Ux = 0x000f_0000; +} diff --git a/esp32p4/src/ppa.rs b/esp32p4/src/ppa.rs new file mode 100644 index 0000000000..f7325c2486 --- /dev/null +++ b/esp32p4/src/ppa.rs @@ -0,0 +1,351 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + blend0_clut_data: BLEND0_CLUT_DATA, + blend1_clut_data: BLEND1_CLUT_DATA, + _reserved2: [u8; 0x04], + clut_conf: CLUT_CONF, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + sr_color_mode: SR_COLOR_MODE, + blend_color_mode: BLEND_COLOR_MODE, + sr_byte_order: SR_BYTE_ORDER, + blend_byte_order: BLEND_BYTE_ORDER, + _reserved11: [u8; 0x04], + blend_trans_mode: BLEND_TRANS_MODE, + sr_fix_alpha: SR_FIX_ALPHA, + blend_tx_size: BLEND_TX_SIZE, + blend_fix_alpha: BLEND_FIX_ALPHA, + _reserved15: [u8; 0x04], + blend_rgb: BLEND_RGB, + blend_fix_pixel: BLEND_FIX_PIXEL, + ck_fg_low: CK_FG_LOW, + ck_fg_high: CK_FG_HIGH, + ck_bg_low: CK_BG_LOW, + ck_bg_high: CK_BG_HIGH, + ck_default: CK_DEFAULT, + sr_scal_rotate: SR_SCAL_ROTATE, + sr_mem_pd: SR_MEM_PD, + reg_conf: REG_CONF, + clut_cnt: CLUT_CNT, + blend_st: BLEND_ST, + sr_param_err_st: SR_PARAM_ERR_ST, + sr_status: SR_STATUS, + eco_low: ECO_LOW, + eco_high: ECO_HIGH, + eco_cell_ctrl: ECO_CELL_CTRL, + sram_ctrl: SRAM_CTRL, + _reserved33: [u8; 0x70], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - CLUT sram data read/write register in background plane of blender"] + #[inline(always)] + pub const fn blend0_clut_data(&self) -> &BLEND0_CLUT_DATA { + &self.blend0_clut_data + } + #[doc = "0x04 - CLUT sram data read/write register in foreground plane of blender"] + #[inline(always)] + pub const fn blend1_clut_data(&self) -> &BLEND1_CLUT_DATA { + &self.blend1_clut_data + } + #[doc = "0x0c - CLUT configure register"] + #[inline(always)] + pub const fn clut_conf(&self) -> &CLUT_CONF { + &self.clut_conf + } + #[doc = "0x10 - Raw status interrupt"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x14 - Masked interrupt"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x18 - Interrupt enable bits"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x1c - Interrupt clear bits"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x20 - Scaling and rotating engine color mode register"] + #[inline(always)] + pub const fn sr_color_mode(&self) -> &SR_COLOR_MODE { + &self.sr_color_mode + } + #[doc = "0x24 - blending engine color mode register"] + #[inline(always)] + pub const fn blend_color_mode(&self) -> &BLEND_COLOR_MODE { + &self.blend_color_mode + } + #[doc = "0x28 - Scaling and rotating engine byte order register"] + #[inline(always)] + pub const fn sr_byte_order(&self) -> &SR_BYTE_ORDER { + &self.sr_byte_order + } + #[doc = "0x2c - Blending engine byte order register"] + #[inline(always)] + pub const fn blend_byte_order(&self) -> &BLEND_BYTE_ORDER { + &self.blend_byte_order + } + #[doc = "0x34 - Blending engine mode configure register"] + #[inline(always)] + pub const fn blend_trans_mode(&self) -> &BLEND_TRANS_MODE { + &self.blend_trans_mode + } + #[doc = "0x38 - Scaling and rotating engine alpha override register"] + #[inline(always)] + pub const fn sr_fix_alpha(&self) -> &SR_FIX_ALPHA { + &self.sr_fix_alpha + } + #[doc = "0x3c - Fix pixel filling mode image size register"] + #[inline(always)] + pub const fn blend_tx_size(&self) -> &BLEND_TX_SIZE { + &self.blend_tx_size + } + #[doc = "0x40 - Blending engine alpha override register"] + #[inline(always)] + pub const fn blend_fix_alpha(&self) -> &BLEND_FIX_ALPHA { + &self.blend_fix_alpha + } + #[doc = "0x48 - RGB color register"] + #[inline(always)] + pub const fn blend_rgb(&self) -> &BLEND_RGB { + &self.blend_rgb + } + #[doc = "0x4c - Blending engine fix pixel register"] + #[inline(always)] + pub const fn blend_fix_pixel(&self) -> &BLEND_FIX_PIXEL { + &self.blend_fix_pixel + } + #[doc = "0x50 - foreground color key lower threshold"] + #[inline(always)] + pub const fn ck_fg_low(&self) -> &CK_FG_LOW { + &self.ck_fg_low + } + #[doc = "0x54 - foreground color key higher threshold"] + #[inline(always)] + pub const fn ck_fg_high(&self) -> &CK_FG_HIGH { + &self.ck_fg_high + } + #[doc = "0x58 - background color key lower threshold"] + #[inline(always)] + pub const fn ck_bg_low(&self) -> &CK_BG_LOW { + &self.ck_bg_low + } + #[doc = "0x5c - background color key higher threshold"] + #[inline(always)] + pub const fn ck_bg_high(&self) -> &CK_BG_HIGH { + &self.ck_bg_high + } + #[doc = "0x60 - default value when foreground and background both in color key range"] + #[inline(always)] + pub const fn ck_default(&self) -> &CK_DEFAULT { + &self.ck_default + } + #[doc = "0x64 - Scaling and rotating coefficient register"] + #[inline(always)] + pub const fn sr_scal_rotate(&self) -> &SR_SCAL_ROTATE { + &self.sr_scal_rotate + } + #[doc = "0x68 - SR memory power done register"] + #[inline(always)] + pub const fn sr_mem_pd(&self) -> &SR_MEM_PD { + &self.sr_mem_pd + } + #[doc = "0x6c - Register clock enable register"] + #[inline(always)] + pub const fn reg_conf(&self) -> ®_CONF { + &self.reg_conf + } + #[doc = "0x70 - BLEND CLUT write counter register"] + #[inline(always)] + pub const fn clut_cnt(&self) -> &CLUT_CNT { + &self.clut_cnt + } + #[doc = "0x74 - Blending engine status register"] + #[inline(always)] + pub const fn blend_st(&self) -> &BLEND_ST { + &self.blend_st + } + #[doc = "0x78 - Scaling and rotating coefficient error register"] + #[inline(always)] + pub const fn sr_param_err_st(&self) -> &SR_PARAM_ERR_ST { + &self.sr_param_err_st + } + #[doc = "0x7c - SR FSM register"] + #[inline(always)] + pub const fn sr_status(&self) -> &SR_STATUS { + &self.sr_status + } + #[doc = "0x80 - Reserved."] + #[inline(always)] + pub const fn eco_low(&self) -> &ECO_LOW { + &self.eco_low + } + #[doc = "0x84 - Reserved."] + #[inline(always)] + pub const fn eco_high(&self) -> &ECO_HIGH { + &self.eco_high + } + #[doc = "0x88 - Reserved."] + #[inline(always)] + pub const fn eco_cell_ctrl(&self) -> &ECO_CELL_CTRL { + &self.eco_cell_ctrl + } + #[doc = "0x8c - PPA SRAM Control Register"] + #[inline(always)] + pub const fn sram_ctrl(&self) -> &SRAM_CTRL { + &self.sram_ctrl + } + #[doc = "0x100 - PPA Version register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "BLEND0_CLUT_DATA (rw) register accessor: CLUT sram data read/write register in background plane of blender\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend0_clut_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend0_clut_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blend0_clut_data`] module"] +pub type BLEND0_CLUT_DATA = crate::Reg; +#[doc = "CLUT sram data read/write register in background plane of blender"] +pub mod blend0_clut_data; +#[doc = "BLEND1_CLUT_DATA (rw) register accessor: CLUT sram data read/write register in foreground plane of blender\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend1_clut_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend1_clut_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blend1_clut_data`] module"] +pub type BLEND1_CLUT_DATA = crate::Reg; +#[doc = "CLUT sram data read/write register in foreground plane of blender"] +pub mod blend1_clut_data; +#[doc = "CLUT_CONF (rw) register accessor: CLUT configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clut_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clut_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clut_conf`] module"] +pub type CLUT_CONF = crate::Reg; +#[doc = "CLUT configure register"] +pub mod clut_conf; +#[doc = "INT_RAW (rw) register accessor: Raw status interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Raw status interrupt"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Masked interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Masked interrupt"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable bits"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear bits"] +pub mod int_clr; +#[doc = "SR_COLOR_MODE (rw) register accessor: Scaling and rotating engine color mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_color_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr_color_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr_color_mode`] module"] +pub type SR_COLOR_MODE = crate::Reg; +#[doc = "Scaling and rotating engine color mode register"] +pub mod sr_color_mode; +#[doc = "BLEND_COLOR_MODE (rw) register accessor: blending engine color mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_color_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_color_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blend_color_mode`] module"] +pub type BLEND_COLOR_MODE = crate::Reg; +#[doc = "blending engine color mode register"] +pub mod blend_color_mode; +#[doc = "SR_BYTE_ORDER (rw) register accessor: Scaling and rotating engine byte order register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_byte_order::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr_byte_order::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr_byte_order`] module"] +pub type SR_BYTE_ORDER = crate::Reg; +#[doc = "Scaling and rotating engine byte order register"] +pub mod sr_byte_order; +#[doc = "BLEND_BYTE_ORDER (rw) register accessor: Blending engine byte order register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_byte_order::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_byte_order::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blend_byte_order`] module"] +pub type BLEND_BYTE_ORDER = crate::Reg; +#[doc = "Blending engine byte order register"] +pub mod blend_byte_order; +#[doc = "BLEND_TRANS_MODE (rw) register accessor: Blending engine mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_trans_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_trans_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blend_trans_mode`] module"] +pub type BLEND_TRANS_MODE = crate::Reg; +#[doc = "Blending engine mode configure register"] +pub mod blend_trans_mode; +#[doc = "SR_FIX_ALPHA (rw) register accessor: Scaling and rotating engine alpha override register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_fix_alpha::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr_fix_alpha::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr_fix_alpha`] module"] +pub type SR_FIX_ALPHA = crate::Reg; +#[doc = "Scaling and rotating engine alpha override register"] +pub mod sr_fix_alpha; +#[doc = "BLEND_TX_SIZE (rw) register accessor: Fix pixel filling mode image size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_tx_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_tx_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blend_tx_size`] module"] +pub type BLEND_TX_SIZE = crate::Reg; +#[doc = "Fix pixel filling mode image size register"] +pub mod blend_tx_size; +#[doc = "BLEND_FIX_ALPHA (rw) register accessor: Blending engine alpha override register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_fix_alpha::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_fix_alpha::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blend_fix_alpha`] module"] +pub type BLEND_FIX_ALPHA = crate::Reg; +#[doc = "Blending engine alpha override register"] +pub mod blend_fix_alpha; +#[doc = "BLEND_RGB (rw) register accessor: RGB color register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_rgb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_rgb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blend_rgb`] module"] +pub type BLEND_RGB = crate::Reg; +#[doc = "RGB color register"] +pub mod blend_rgb; +#[doc = "BLEND_FIX_PIXEL (rw) register accessor: Blending engine fix pixel register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_fix_pixel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_fix_pixel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blend_fix_pixel`] module"] +pub type BLEND_FIX_PIXEL = crate::Reg; +#[doc = "Blending engine fix pixel register"] +pub mod blend_fix_pixel; +#[doc = "CK_FG_LOW (rw) register accessor: foreground color key lower threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ck_fg_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ck_fg_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ck_fg_low`] module"] +pub type CK_FG_LOW = crate::Reg; +#[doc = "foreground color key lower threshold"] +pub mod ck_fg_low; +#[doc = "CK_FG_HIGH (rw) register accessor: foreground color key higher threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ck_fg_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ck_fg_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ck_fg_high`] module"] +pub type CK_FG_HIGH = crate::Reg; +#[doc = "foreground color key higher threshold"] +pub mod ck_fg_high; +#[doc = "CK_BG_LOW (rw) register accessor: background color key lower threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ck_bg_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ck_bg_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ck_bg_low`] module"] +pub type CK_BG_LOW = crate::Reg; +#[doc = "background color key lower threshold"] +pub mod ck_bg_low; +#[doc = "CK_BG_HIGH (rw) register accessor: background color key higher threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ck_bg_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ck_bg_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ck_bg_high`] module"] +pub type CK_BG_HIGH = crate::Reg; +#[doc = "background color key higher threshold"] +pub mod ck_bg_high; +#[doc = "CK_DEFAULT (rw) register accessor: default value when foreground and background both in color key range\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ck_default::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ck_default::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ck_default`] module"] +pub type CK_DEFAULT = crate::Reg; +#[doc = "default value when foreground and background both in color key range"] +pub mod ck_default; +#[doc = "SR_SCAL_ROTATE (rw) register accessor: Scaling and rotating coefficient register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_scal_rotate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr_scal_rotate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr_scal_rotate`] module"] +pub type SR_SCAL_ROTATE = crate::Reg; +#[doc = "Scaling and rotating coefficient register"] +pub mod sr_scal_rotate; +#[doc = "SR_MEM_PD (rw) register accessor: SR memory power done register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_mem_pd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr_mem_pd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr_mem_pd`] module"] +pub type SR_MEM_PD = crate::Reg; +#[doc = "SR memory power done register"] +pub mod sr_mem_pd; +#[doc = "REG_CONF (rw) register accessor: Register clock enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_conf`] module"] +pub type REG_CONF = crate::Reg; +#[doc = "Register clock enable register"] +pub mod reg_conf; +#[doc = "CLUT_CNT (r) register accessor: BLEND CLUT write counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clut_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clut_cnt`] module"] +pub type CLUT_CNT = crate::Reg; +#[doc = "BLEND CLUT write counter register"] +pub mod clut_cnt; +#[doc = "BLEND_ST (r) register accessor: Blending engine status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blend_st`] module"] +pub type BLEND_ST = crate::Reg; +#[doc = "Blending engine status register"] +pub mod blend_st; +#[doc = "SR_PARAM_ERR_ST (r) register accessor: Scaling and rotating coefficient error register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_param_err_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr_param_err_st`] module"] +pub type SR_PARAM_ERR_ST = crate::Reg; +#[doc = "Scaling and rotating coefficient error register"] +pub mod sr_param_err_st; +#[doc = "SR_STATUS (r) register accessor: SR FSM register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr_status`] module"] +pub type SR_STATUS = crate::Reg; +#[doc = "SR FSM register"] +pub mod sr_status; +#[doc = "ECO_LOW (rw) register accessor: Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_low`] module"] +pub type ECO_LOW = crate::Reg; +#[doc = "Reserved."] +pub mod eco_low; +#[doc = "ECO_HIGH (rw) register accessor: Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_high`] module"] +pub type ECO_HIGH = crate::Reg; +#[doc = "Reserved."] +pub mod eco_high; +#[doc = "ECO_CELL_CTRL (rw) register accessor: Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_cell_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_cell_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_cell_ctrl`] module"] +pub type ECO_CELL_CTRL = crate::Reg; +#[doc = "Reserved."] +pub mod eco_cell_ctrl; +#[doc = "SRAM_CTRL (rw) register accessor: PPA SRAM Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sram_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ctrl`] module"] +pub type SRAM_CTRL = crate::Reg; +#[doc = "PPA SRAM Control Register"] +pub mod sram_ctrl; +#[doc = "DATE (rw) register accessor: PPA Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "PPA Version register"] +pub mod date; diff --git a/esp32p4/src/ppa/blend0_clut_data.rs b/esp32p4/src/ppa/blend0_clut_data.rs new file mode 100644 index 0000000000..0f10944f2d --- /dev/null +++ b/esp32p4/src/ppa/blend0_clut_data.rs @@ -0,0 +1,66 @@ +#[doc = "Register `BLEND0_CLUT_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `BLEND0_CLUT_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `RDWR_WORD_BLEND0_CLUT` reader - Write and read data to/from CLUT RAM in background plane of blender engine through this field in fifo mode."] +pub type RDWR_WORD_BLEND0_CLUT_R = crate::FieldReader; +#[doc = "Field `RDWR_WORD_BLEND0_CLUT` writer - Write and read data to/from CLUT RAM in background plane of blender engine through this field in fifo mode."] +pub type RDWR_WORD_BLEND0_CLUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Write and read data to/from CLUT RAM in background plane of blender engine through this field in fifo mode."] + #[inline(always)] + pub fn rdwr_word_blend0_clut(&self) -> RDWR_WORD_BLEND0_CLUT_R { + RDWR_WORD_BLEND0_CLUT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLEND0_CLUT_DATA") + .field( + "rdwr_word_blend0_clut", + &format_args!("{}", self.rdwr_word_blend0_clut().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Write and read data to/from CLUT RAM in background plane of blender engine through this field in fifo mode."] + #[inline(always)] + #[must_use] + pub fn rdwr_word_blend0_clut(&mut self) -> RDWR_WORD_BLEND0_CLUT_W { + RDWR_WORD_BLEND0_CLUT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "CLUT sram data read/write register in background plane of blender\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend0_clut_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend0_clut_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLEND0_CLUT_DATA_SPEC; +impl crate::RegisterSpec for BLEND0_CLUT_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blend0_clut_data::R`](R) reader structure"] +impl crate::Readable for BLEND0_CLUT_DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blend0_clut_data::W`](W) writer structure"] +impl crate::Writable for BLEND0_CLUT_DATA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLEND0_CLUT_DATA to value 0"] +impl crate::Resettable for BLEND0_CLUT_DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/blend1_clut_data.rs b/esp32p4/src/ppa/blend1_clut_data.rs new file mode 100644 index 0000000000..12fed62d1b --- /dev/null +++ b/esp32p4/src/ppa/blend1_clut_data.rs @@ -0,0 +1,66 @@ +#[doc = "Register `BLEND1_CLUT_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `BLEND1_CLUT_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `RDWR_WORD_BLEND1_CLUT` reader - Write and read data to/from CLUT RAM in foreground plane of blender engine through this field in fifo mode."] +pub type RDWR_WORD_BLEND1_CLUT_R = crate::FieldReader; +#[doc = "Field `RDWR_WORD_BLEND1_CLUT` writer - Write and read data to/from CLUT RAM in foreground plane of blender engine through this field in fifo mode."] +pub type RDWR_WORD_BLEND1_CLUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Write and read data to/from CLUT RAM in foreground plane of blender engine through this field in fifo mode."] + #[inline(always)] + pub fn rdwr_word_blend1_clut(&self) -> RDWR_WORD_BLEND1_CLUT_R { + RDWR_WORD_BLEND1_CLUT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLEND1_CLUT_DATA") + .field( + "rdwr_word_blend1_clut", + &format_args!("{}", self.rdwr_word_blend1_clut().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Write and read data to/from CLUT RAM in foreground plane of blender engine through this field in fifo mode."] + #[inline(always)] + #[must_use] + pub fn rdwr_word_blend1_clut(&mut self) -> RDWR_WORD_BLEND1_CLUT_W { + RDWR_WORD_BLEND1_CLUT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "CLUT sram data read/write register in foreground plane of blender\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend1_clut_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend1_clut_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLEND1_CLUT_DATA_SPEC; +impl crate::RegisterSpec for BLEND1_CLUT_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blend1_clut_data::R`](R) reader structure"] +impl crate::Readable for BLEND1_CLUT_DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blend1_clut_data::W`](W) writer structure"] +impl crate::Writable for BLEND1_CLUT_DATA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLEND1_CLUT_DATA to value 0"] +impl crate::Resettable for BLEND1_CLUT_DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/blend_byte_order.rs b/esp32p4/src/ppa/blend_byte_order.rs new file mode 100644 index 0000000000..47d5617fbd --- /dev/null +++ b/esp32p4/src/ppa/blend_byte_order.rs @@ -0,0 +1,123 @@ +#[doc = "Register `BLEND_BYTE_ORDER` reader"] +pub type R = crate::R; +#[doc = "Register `BLEND_BYTE_ORDER` writer"] +pub type W = crate::W; +#[doc = "Field `BLEND0_RX_BYTE_SWAP_EN` reader - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] +pub type BLEND0_RX_BYTE_SWAP_EN_R = crate::BitReader; +#[doc = "Field `BLEND0_RX_BYTE_SWAP_EN` writer - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] +pub type BLEND0_RX_BYTE_SWAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND1_RX_BYTE_SWAP_EN` reader - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] +pub type BLEND1_RX_BYTE_SWAP_EN_R = crate::BitReader; +#[doc = "Field `BLEND1_RX_BYTE_SWAP_EN` writer - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] +pub type BLEND1_RX_BYTE_SWAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND0_RX_RGB_SWAP_EN` reader - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] +pub type BLEND0_RX_RGB_SWAP_EN_R = crate::BitReader; +#[doc = "Field `BLEND0_RX_RGB_SWAP_EN` writer - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] +pub type BLEND0_RX_RGB_SWAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND1_RX_RGB_SWAP_EN` reader - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] +pub type BLEND1_RX_RGB_SWAP_EN_R = crate::BitReader; +#[doc = "Field `BLEND1_RX_RGB_SWAP_EN` writer - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] +pub type BLEND1_RX_RGB_SWAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] + #[inline(always)] + pub fn blend0_rx_byte_swap_en(&self) -> BLEND0_RX_BYTE_SWAP_EN_R { + BLEND0_RX_BYTE_SWAP_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] + #[inline(always)] + pub fn blend1_rx_byte_swap_en(&self) -> BLEND1_RX_BYTE_SWAP_EN_R { + BLEND1_RX_BYTE_SWAP_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] + #[inline(always)] + pub fn blend0_rx_rgb_swap_en(&self) -> BLEND0_RX_RGB_SWAP_EN_R { + BLEND0_RX_RGB_SWAP_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] + #[inline(always)] + pub fn blend1_rx_rgb_swap_en(&self) -> BLEND1_RX_RGB_SWAP_EN_R { + BLEND1_RX_RGB_SWAP_EN_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLEND_BYTE_ORDER") + .field( + "blend0_rx_byte_swap_en", + &format_args!("{}", self.blend0_rx_byte_swap_en().bit()), + ) + .field( + "blend1_rx_byte_swap_en", + &format_args!("{}", self.blend1_rx_byte_swap_en().bit()), + ) + .field( + "blend0_rx_rgb_swap_en", + &format_args!("{}", self.blend0_rx_rgb_swap_en().bit()), + ) + .field( + "blend1_rx_rgb_swap_en", + &format_args!("{}", self.blend1_rx_rgb_swap_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] + #[inline(always)] + #[must_use] + pub fn blend0_rx_byte_swap_en(&mut self) -> BLEND0_RX_BYTE_SWAP_EN_W { + BLEND0_RX_BYTE_SWAP_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] + #[inline(always)] + #[must_use] + pub fn blend1_rx_byte_swap_en(&mut self) -> BLEND1_RX_BYTE_SWAP_EN_W { + BLEND1_RX_BYTE_SWAP_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] + #[inline(always)] + #[must_use] + pub fn blend0_rx_rgb_swap_en(&mut self) -> BLEND0_RX_RGB_SWAP_EN_W { + BLEND0_RX_RGB_SWAP_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] + #[inline(always)] + #[must_use] + pub fn blend1_rx_rgb_swap_en(&mut self) -> BLEND1_RX_RGB_SWAP_EN_W { + BLEND1_RX_RGB_SWAP_EN_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Blending engine byte order register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_byte_order::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_byte_order::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLEND_BYTE_ORDER_SPEC; +impl crate::RegisterSpec for BLEND_BYTE_ORDER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blend_byte_order::R`](R) reader structure"] +impl crate::Readable for BLEND_BYTE_ORDER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blend_byte_order::W`](W) writer structure"] +impl crate::Writable for BLEND_BYTE_ORDER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLEND_BYTE_ORDER to value 0"] +impl crate::Resettable for BLEND_BYTE_ORDER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/blend_color_mode.rs b/esp32p4/src/ppa/blend_color_mode.rs new file mode 100644 index 0000000000..2a96c7a6ae --- /dev/null +++ b/esp32p4/src/ppa/blend_color_mode.rs @@ -0,0 +1,104 @@ +#[doc = "Register `BLEND_COLOR_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `BLEND_COLOR_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `BLEND0_RX_CM` reader - The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4."] +pub type BLEND0_RX_CM_R = crate::FieldReader; +#[doc = "Field `BLEND0_RX_CM` writer - The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4."] +pub type BLEND0_RX_CM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `BLEND1_RX_CM` reader - The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4."] +pub type BLEND1_RX_CM_R = crate::FieldReader; +#[doc = "Field `BLEND1_RX_CM` writer - The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4."] +pub type BLEND1_RX_CM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `BLEND_TX_CM` reader - The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved.."] +pub type BLEND_TX_CM_R = crate::FieldReader; +#[doc = "Field `BLEND_TX_CM` writer - The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved.."] +pub type BLEND_TX_CM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4."] + #[inline(always)] + pub fn blend0_rx_cm(&self) -> BLEND0_RX_CM_R { + BLEND0_RX_CM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4."] + #[inline(always)] + pub fn blend1_rx_cm(&self) -> BLEND1_RX_CM_R { + BLEND1_RX_CM_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved.."] + #[inline(always)] + pub fn blend_tx_cm(&self) -> BLEND_TX_CM_R { + BLEND_TX_CM_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLEND_COLOR_MODE") + .field( + "blend0_rx_cm", + &format_args!("{}", self.blend0_rx_cm().bits()), + ) + .field( + "blend1_rx_cm", + &format_args!("{}", self.blend1_rx_cm().bits()), + ) + .field( + "blend_tx_cm", + &format_args!("{}", self.blend_tx_cm().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4."] + #[inline(always)] + #[must_use] + pub fn blend0_rx_cm(&mut self) -> BLEND0_RX_CM_W { + BLEND0_RX_CM_W::new(self, 0) + } + #[doc = "Bits 4:7 - The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4."] + #[inline(always)] + #[must_use] + pub fn blend1_rx_cm(&mut self) -> BLEND1_RX_CM_W { + BLEND1_RX_CM_W::new(self, 4) + } + #[doc = "Bits 8:11 - The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved.."] + #[inline(always)] + #[must_use] + pub fn blend_tx_cm(&mut self) -> BLEND_TX_CM_W { + BLEND_TX_CM_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "blending engine color mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_color_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_color_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLEND_COLOR_MODE_SPEC; +impl crate::RegisterSpec for BLEND_COLOR_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blend_color_mode::R`](R) reader structure"] +impl crate::Readable for BLEND_COLOR_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blend_color_mode::W`](W) writer structure"] +impl crate::Writable for BLEND_COLOR_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLEND_COLOR_MODE to value 0"] +impl crate::Resettable for BLEND_COLOR_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/blend_fix_alpha.rs b/esp32p4/src/ppa/blend_fix_alpha.rs new file mode 100644 index 0000000000..ed586a1fa6 --- /dev/null +++ b/esp32p4/src/ppa/blend_fix_alpha.rs @@ -0,0 +1,161 @@ +#[doc = "Register `BLEND_FIX_ALPHA` reader"] +pub type R = crate::R; +#[doc = "Register `BLEND_FIX_ALPHA` writer"] +pub type W = crate::W; +#[doc = "Field `BLEND0_RX_FIX_ALPHA` reader - The value would replace the alpha value in received pixel for background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled."] +pub type BLEND0_RX_FIX_ALPHA_R = crate::FieldReader; +#[doc = "Field `BLEND0_RX_FIX_ALPHA` writer - The value would replace the alpha value in received pixel for background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled."] +pub type BLEND0_RX_FIX_ALPHA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BLEND1_RX_FIX_ALPHA` reader - The value would replace the alpha value in received pixel for foreground plane of blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled."] +pub type BLEND1_RX_FIX_ALPHA_R = crate::FieldReader; +#[doc = "Field `BLEND1_RX_FIX_ALPHA` writer - The value would replace the alpha value in received pixel for foreground plane of blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled."] +pub type BLEND1_RX_FIX_ALPHA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BLEND0_RX_ALPHA_MOD` reader - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] +pub type BLEND0_RX_ALPHA_MOD_R = crate::FieldReader; +#[doc = "Field `BLEND0_RX_ALPHA_MOD` writer - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] +pub type BLEND0_RX_ALPHA_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `BLEND1_RX_ALPHA_MOD` reader - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] +pub type BLEND1_RX_ALPHA_MOD_R = crate::FieldReader; +#[doc = "Field `BLEND1_RX_ALPHA_MOD` writer - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] +pub type BLEND1_RX_ALPHA_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `BLEND0_RX_ALPHA_INV` reader - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] +pub type BLEND0_RX_ALPHA_INV_R = crate::BitReader; +#[doc = "Field `BLEND0_RX_ALPHA_INV` writer - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] +pub type BLEND0_RX_ALPHA_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND1_RX_ALPHA_INV` reader - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] +pub type BLEND1_RX_ALPHA_INV_R = crate::BitReader; +#[doc = "Field `BLEND1_RX_ALPHA_INV` writer - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] +pub type BLEND1_RX_ALPHA_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - The value would replace the alpha value in received pixel for background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled."] + #[inline(always)] + pub fn blend0_rx_fix_alpha(&self) -> BLEND0_RX_FIX_ALPHA_R { + BLEND0_RX_FIX_ALPHA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - The value would replace the alpha value in received pixel for foreground plane of blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled."] + #[inline(always)] + pub fn blend1_rx_fix_alpha(&self) -> BLEND1_RX_FIX_ALPHA_R { + BLEND1_RX_FIX_ALPHA_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:17 - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] + #[inline(always)] + pub fn blend0_rx_alpha_mod(&self) -> BLEND0_RX_ALPHA_MOD_R { + BLEND0_RX_ALPHA_MOD_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19 - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] + #[inline(always)] + pub fn blend1_rx_alpha_mod(&self) -> BLEND1_RX_ALPHA_MOD_R { + BLEND1_RX_ALPHA_MOD_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 20 - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] + #[inline(always)] + pub fn blend0_rx_alpha_inv(&self) -> BLEND0_RX_ALPHA_INV_R { + BLEND0_RX_ALPHA_INV_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] + #[inline(always)] + pub fn blend1_rx_alpha_inv(&self) -> BLEND1_RX_ALPHA_INV_R { + BLEND1_RX_ALPHA_INV_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLEND_FIX_ALPHA") + .field( + "blend0_rx_fix_alpha", + &format_args!("{}", self.blend0_rx_fix_alpha().bits()), + ) + .field( + "blend1_rx_fix_alpha", + &format_args!("{}", self.blend1_rx_fix_alpha().bits()), + ) + .field( + "blend0_rx_alpha_mod", + &format_args!("{}", self.blend0_rx_alpha_mod().bits()), + ) + .field( + "blend1_rx_alpha_mod", + &format_args!("{}", self.blend1_rx_alpha_mod().bits()), + ) + .field( + "blend0_rx_alpha_inv", + &format_args!("{}", self.blend0_rx_alpha_inv().bit()), + ) + .field( + "blend1_rx_alpha_inv", + &format_args!("{}", self.blend1_rx_alpha_inv().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - The value would replace the alpha value in received pixel for background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled."] + #[inline(always)] + #[must_use] + pub fn blend0_rx_fix_alpha(&mut self) -> BLEND0_RX_FIX_ALPHA_W { + BLEND0_RX_FIX_ALPHA_W::new(self, 0) + } + #[doc = "Bits 8:15 - The value would replace the alpha value in received pixel for foreground plane of blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled."] + #[inline(always)] + #[must_use] + pub fn blend1_rx_fix_alpha(&mut self) -> BLEND1_RX_FIX_ALPHA_W { + BLEND1_RX_FIX_ALPHA_W::new(self, 8) + } + #[doc = "Bits 16:17 - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] + #[inline(always)] + #[must_use] + pub fn blend0_rx_alpha_mod(&mut self) -> BLEND0_RX_ALPHA_MOD_W { + BLEND0_RX_ALPHA_MOD_W::new(self, 16) + } + #[doc = "Bits 18:19 - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] + #[inline(always)] + #[must_use] + pub fn blend1_rx_alpha_mod(&mut self) -> BLEND1_RX_ALPHA_MOD_W { + BLEND1_RX_ALPHA_MOD_W::new(self, 18) + } + #[doc = "Bit 20 - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] + #[inline(always)] + #[must_use] + pub fn blend0_rx_alpha_inv(&mut self) -> BLEND0_RX_ALPHA_INV_W { + BLEND0_RX_ALPHA_INV_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] + #[inline(always)] + #[must_use] + pub fn blend1_rx_alpha_inv(&mut self) -> BLEND1_RX_ALPHA_INV_W { + BLEND1_RX_ALPHA_INV_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Blending engine alpha override register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_fix_alpha::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_fix_alpha::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLEND_FIX_ALPHA_SPEC; +impl crate::RegisterSpec for BLEND_FIX_ALPHA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blend_fix_alpha::R`](R) reader structure"] +impl crate::Readable for BLEND_FIX_ALPHA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blend_fix_alpha::W`](W) writer structure"] +impl crate::Writable for BLEND_FIX_ALPHA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLEND_FIX_ALPHA to value 0x8080"] +impl crate::Resettable for BLEND_FIX_ALPHA_SPEC { + const RESET_VALUE: Self::Ux = 0x8080; +} diff --git a/esp32p4/src/ppa/blend_fix_pixel.rs b/esp32p4/src/ppa/blend_fix_pixel.rs new file mode 100644 index 0000000000..f260f5adb2 --- /dev/null +++ b/esp32p4/src/ppa/blend_fix_pixel.rs @@ -0,0 +1,66 @@ +#[doc = "Register `BLEND_FIX_PIXEL` reader"] +pub type R = crate::R; +#[doc = "Register `BLEND_FIX_PIXEL` writer"] +pub type W = crate::W; +#[doc = "Field `BLEND_TX_FIX_PIXEL` reader - The configure fix pixel in fix pixel filling mode for blender engine."] +pub type BLEND_TX_FIX_PIXEL_R = crate::FieldReader; +#[doc = "Field `BLEND_TX_FIX_PIXEL` writer - The configure fix pixel in fix pixel filling mode for blender engine."] +pub type BLEND_TX_FIX_PIXEL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The configure fix pixel in fix pixel filling mode for blender engine."] + #[inline(always)] + pub fn blend_tx_fix_pixel(&self) -> BLEND_TX_FIX_PIXEL_R { + BLEND_TX_FIX_PIXEL_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLEND_FIX_PIXEL") + .field( + "blend_tx_fix_pixel", + &format_args!("{}", self.blend_tx_fix_pixel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The configure fix pixel in fix pixel filling mode for blender engine."] + #[inline(always)] + #[must_use] + pub fn blend_tx_fix_pixel(&mut self) -> BLEND_TX_FIX_PIXEL_W { + BLEND_TX_FIX_PIXEL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Blending engine fix pixel register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_fix_pixel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_fix_pixel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLEND_FIX_PIXEL_SPEC; +impl crate::RegisterSpec for BLEND_FIX_PIXEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blend_fix_pixel::R`](R) reader structure"] +impl crate::Readable for BLEND_FIX_PIXEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blend_fix_pixel::W`](W) writer structure"] +impl crate::Writable for BLEND_FIX_PIXEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLEND_FIX_PIXEL to value 0"] +impl crate::Resettable for BLEND_FIX_PIXEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/blend_rgb.rs b/esp32p4/src/ppa/blend_rgb.rs new file mode 100644 index 0000000000..349944911d --- /dev/null +++ b/esp32p4/src/ppa/blend_rgb.rs @@ -0,0 +1,104 @@ +#[doc = "Register `BLEND_RGB` reader"] +pub type R = crate::R; +#[doc = "Register `BLEND_RGB` writer"] +pub type W = crate::W; +#[doc = "Field `BLEND1_RX_B` reader - blue color for A4/A8 mode."] +pub type BLEND1_RX_B_R = crate::FieldReader; +#[doc = "Field `BLEND1_RX_B` writer - blue color for A4/A8 mode."] +pub type BLEND1_RX_B_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BLEND1_RX_G` reader - green color for A4/A8 mode."] +pub type BLEND1_RX_G_R = crate::FieldReader; +#[doc = "Field `BLEND1_RX_G` writer - green color for A4/A8 mode."] +pub type BLEND1_RX_G_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BLEND1_RX_R` reader - red color for A4/A8 mode."] +pub type BLEND1_RX_R_R = crate::FieldReader; +#[doc = "Field `BLEND1_RX_R` writer - red color for A4/A8 mode."] +pub type BLEND1_RX_R_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - blue color for A4/A8 mode."] + #[inline(always)] + pub fn blend1_rx_b(&self) -> BLEND1_RX_B_R { + BLEND1_RX_B_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - green color for A4/A8 mode."] + #[inline(always)] + pub fn blend1_rx_g(&self) -> BLEND1_RX_G_R { + BLEND1_RX_G_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - red color for A4/A8 mode."] + #[inline(always)] + pub fn blend1_rx_r(&self) -> BLEND1_RX_R_R { + BLEND1_RX_R_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLEND_RGB") + .field( + "blend1_rx_b", + &format_args!("{}", self.blend1_rx_b().bits()), + ) + .field( + "blend1_rx_g", + &format_args!("{}", self.blend1_rx_g().bits()), + ) + .field( + "blend1_rx_r", + &format_args!("{}", self.blend1_rx_r().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - blue color for A4/A8 mode."] + #[inline(always)] + #[must_use] + pub fn blend1_rx_b(&mut self) -> BLEND1_RX_B_W { + BLEND1_RX_B_W::new(self, 0) + } + #[doc = "Bits 8:15 - green color for A4/A8 mode."] + #[inline(always)] + #[must_use] + pub fn blend1_rx_g(&mut self) -> BLEND1_RX_G_W { + BLEND1_RX_G_W::new(self, 8) + } + #[doc = "Bits 16:23 - red color for A4/A8 mode."] + #[inline(always)] + #[must_use] + pub fn blend1_rx_r(&mut self) -> BLEND1_RX_R_W { + BLEND1_RX_R_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RGB color register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_rgb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_rgb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLEND_RGB_SPEC; +impl crate::RegisterSpec for BLEND_RGB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blend_rgb::R`](R) reader structure"] +impl crate::Readable for BLEND_RGB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blend_rgb::W`](W) writer structure"] +impl crate::Writable for BLEND_RGB_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLEND_RGB to value 0x0080_8080"] +impl crate::Resettable for BLEND_RGB_SPEC { + const RESET_VALUE: Self::Ux = 0x0080_8080; +} diff --git a/esp32p4/src/ppa/blend_st.rs b/esp32p4/src/ppa/blend_st.rs new file mode 100644 index 0000000000..8f6d2e5971 --- /dev/null +++ b/esp32p4/src/ppa/blend_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `BLEND_ST` reader"] +pub type R = crate::R; +#[doc = "Field `BLEND_SIZE_DIFF_ST` reader - 1: indicate the size of two image is different."] +pub type BLEND_SIZE_DIFF_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - 1: indicate the size of two image is different."] + #[inline(always)] + pub fn blend_size_diff_st(&self) -> BLEND_SIZE_DIFF_ST_R { + BLEND_SIZE_DIFF_ST_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLEND_ST") + .field( + "blend_size_diff_st", + &format_args!("{}", self.blend_size_diff_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Blending engine status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLEND_ST_SPEC; +impl crate::RegisterSpec for BLEND_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blend_st::R`](R) reader structure"] +impl crate::Readable for BLEND_ST_SPEC {} +#[doc = "`reset()` method sets BLEND_ST to value 0"] +impl crate::Resettable for BLEND_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/blend_trans_mode.rs b/esp32p4/src/ppa/blend_trans_mode.rs new file mode 100644 index 0000000000..0f1c38d4ea --- /dev/null +++ b/esp32p4/src/ppa/blend_trans_mode.rs @@ -0,0 +1,125 @@ +#[doc = "Register `BLEND_TRANS_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `BLEND_TRANS_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `BLEND_EN` reader - Set this bit to enable alpha blending."] +pub type BLEND_EN_R = crate::BitReader; +#[doc = "Field `BLEND_EN` writer - Set this bit to enable alpha blending."] +pub type BLEND_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND_BYPASS` reader - Set this bit to bypass blender. Then background date would be output."] +pub type BLEND_BYPASS_R = crate::BitReader; +#[doc = "Field `BLEND_BYPASS` writer - Set this bit to bypass blender. Then background date would be output."] +pub type BLEND_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND_FIX_PIXEL_FILL_EN` reader - This bit is used to enable fix pixel filling. When this mode is enable only Tx channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL."] +pub type BLEND_FIX_PIXEL_FILL_EN_R = crate::BitReader; +#[doc = "Field `BLEND_FIX_PIXEL_FILL_EN` writer - This bit is used to enable fix pixel filling. When this mode is enable only Tx channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL."] +pub type BLEND_FIX_PIXEL_FILL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UPDATE` writer - Set this bit to update the transfer mode. Only the bit is set the transfer mode is valid."] +pub type UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND_RST` reader - write 1 then write 0 to reset blending engine."] +pub type BLEND_RST_R = crate::BitReader; +#[doc = "Field `BLEND_RST` writer - write 1 then write 0 to reset blending engine."] +pub type BLEND_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable alpha blending."] + #[inline(always)] + pub fn blend_en(&self) -> BLEND_EN_R { + BLEND_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to bypass blender. Then background date would be output."] + #[inline(always)] + pub fn blend_bypass(&self) -> BLEND_BYPASS_R { + BLEND_BYPASS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This bit is used to enable fix pixel filling. When this mode is enable only Tx channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL."] + #[inline(always)] + pub fn blend_fix_pixel_fill_en(&self) -> BLEND_FIX_PIXEL_FILL_EN_R { + BLEND_FIX_PIXEL_FILL_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - write 1 then write 0 to reset blending engine."] + #[inline(always)] + pub fn blend_rst(&self) -> BLEND_RST_R { + BLEND_RST_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLEND_TRANS_MODE") + .field("blend_en", &format_args!("{}", self.blend_en().bit())) + .field( + "blend_bypass", + &format_args!("{}", self.blend_bypass().bit()), + ) + .field( + "blend_fix_pixel_fill_en", + &format_args!("{}", self.blend_fix_pixel_fill_en().bit()), + ) + .field("blend_rst", &format_args!("{}", self.blend_rst().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable alpha blending."] + #[inline(always)] + #[must_use] + pub fn blend_en(&mut self) -> BLEND_EN_W { + BLEND_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to bypass blender. Then background date would be output."] + #[inline(always)] + #[must_use] + pub fn blend_bypass(&mut self) -> BLEND_BYPASS_W { + BLEND_BYPASS_W::new(self, 1) + } + #[doc = "Bit 2 - This bit is used to enable fix pixel filling. When this mode is enable only Tx channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL."] + #[inline(always)] + #[must_use] + pub fn blend_fix_pixel_fill_en(&mut self) -> BLEND_FIX_PIXEL_FILL_EN_W { + BLEND_FIX_PIXEL_FILL_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to update the transfer mode. Only the bit is set the transfer mode is valid."] + #[inline(always)] + #[must_use] + pub fn update(&mut self) -> UPDATE_W { + UPDATE_W::new(self, 3) + } + #[doc = "Bit 4 - write 1 then write 0 to reset blending engine."] + #[inline(always)] + #[must_use] + pub fn blend_rst(&mut self) -> BLEND_RST_W { + BLEND_RST_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Blending engine mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_trans_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_trans_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLEND_TRANS_MODE_SPEC; +impl crate::RegisterSpec for BLEND_TRANS_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blend_trans_mode::R`](R) reader structure"] +impl crate::Readable for BLEND_TRANS_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blend_trans_mode::W`](W) writer structure"] +impl crate::Writable for BLEND_TRANS_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLEND_TRANS_MODE to value 0"] +impl crate::Resettable for BLEND_TRANS_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/blend_tx_size.rs b/esp32p4/src/ppa/blend_tx_size.rs new file mode 100644 index 0000000000..1ca63a4b1e --- /dev/null +++ b/esp32p4/src/ppa/blend_tx_size.rs @@ -0,0 +1,79 @@ +#[doc = "Register `BLEND_TX_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `BLEND_TX_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `BLEND_HB` reader - The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel"] +pub type BLEND_HB_R = crate::FieldReader; +#[doc = "Field `BLEND_HB` writer - The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel"] +pub type BLEND_HB_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `BLEND_VB` reader - The vertical width of image block that would be filled in fix pixel filling mode. The unit is pixel"] +pub type BLEND_VB_R = crate::FieldReader; +#[doc = "Field `BLEND_VB` writer - The vertical width of image block that would be filled in fix pixel filling mode. The unit is pixel"] +pub type BLEND_VB_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel"] + #[inline(always)] + pub fn blend_hb(&self) -> BLEND_HB_R { + BLEND_HB_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 14:27 - The vertical width of image block that would be filled in fix pixel filling mode. The unit is pixel"] + #[inline(always)] + pub fn blend_vb(&self) -> BLEND_VB_R { + BLEND_VB_R::new(((self.bits >> 14) & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLEND_TX_SIZE") + .field("blend_hb", &format_args!("{}", self.blend_hb().bits())) + .field("blend_vb", &format_args!("{}", self.blend_vb().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel"] + #[inline(always)] + #[must_use] + pub fn blend_hb(&mut self) -> BLEND_HB_W { + BLEND_HB_W::new(self, 0) + } + #[doc = "Bits 14:27 - The vertical width of image block that would be filled in fix pixel filling mode. The unit is pixel"] + #[inline(always)] + #[must_use] + pub fn blend_vb(&mut self) -> BLEND_VB_W { + BLEND_VB_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Fix pixel filling mode image size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_tx_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blend_tx_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLEND_TX_SIZE_SPEC; +impl crate::RegisterSpec for BLEND_TX_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blend_tx_size::R`](R) reader structure"] +impl crate::Readable for BLEND_TX_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blend_tx_size::W`](W) writer structure"] +impl crate::Writable for BLEND_TX_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLEND_TX_SIZE to value 0"] +impl crate::Resettable for BLEND_TX_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/ck_bg_high.rs b/esp32p4/src/ppa/ck_bg_high.rs new file mode 100644 index 0000000000..0b572e12d0 --- /dev/null +++ b/esp32p4/src/ppa/ck_bg_high.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CK_BG_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `CK_BG_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `COLORKEY_BG_B_HIGH` reader - color key higher threshold of background b channel"] +pub type COLORKEY_BG_B_HIGH_R = crate::FieldReader; +#[doc = "Field `COLORKEY_BG_B_HIGH` writer - color key higher threshold of background b channel"] +pub type COLORKEY_BG_B_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLORKEY_BG_G_HIGH` reader - color key higher threshold of background g channel"] +pub type COLORKEY_BG_G_HIGH_R = crate::FieldReader; +#[doc = "Field `COLORKEY_BG_G_HIGH` writer - color key higher threshold of background g channel"] +pub type COLORKEY_BG_G_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLORKEY_BG_R_HIGH` reader - color key higher threshold of background r channel"] +pub type COLORKEY_BG_R_HIGH_R = crate::FieldReader; +#[doc = "Field `COLORKEY_BG_R_HIGH` writer - color key higher threshold of background r channel"] +pub type COLORKEY_BG_R_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - color key higher threshold of background b channel"] + #[inline(always)] + pub fn colorkey_bg_b_high(&self) -> COLORKEY_BG_B_HIGH_R { + COLORKEY_BG_B_HIGH_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - color key higher threshold of background g channel"] + #[inline(always)] + pub fn colorkey_bg_g_high(&self) -> COLORKEY_BG_G_HIGH_R { + COLORKEY_BG_G_HIGH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - color key higher threshold of background r channel"] + #[inline(always)] + pub fn colorkey_bg_r_high(&self) -> COLORKEY_BG_R_HIGH_R { + COLORKEY_BG_R_HIGH_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CK_BG_HIGH") + .field( + "colorkey_bg_b_high", + &format_args!("{}", self.colorkey_bg_b_high().bits()), + ) + .field( + "colorkey_bg_g_high", + &format_args!("{}", self.colorkey_bg_g_high().bits()), + ) + .field( + "colorkey_bg_r_high", + &format_args!("{}", self.colorkey_bg_r_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - color key higher threshold of background b channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_bg_b_high(&mut self) -> COLORKEY_BG_B_HIGH_W { + COLORKEY_BG_B_HIGH_W::new(self, 0) + } + #[doc = "Bits 8:15 - color key higher threshold of background g channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_bg_g_high(&mut self) -> COLORKEY_BG_G_HIGH_W { + COLORKEY_BG_G_HIGH_W::new(self, 8) + } + #[doc = "Bits 16:23 - color key higher threshold of background r channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_bg_r_high(&mut self) -> COLORKEY_BG_R_HIGH_W { + COLORKEY_BG_R_HIGH_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "background color key higher threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ck_bg_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ck_bg_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CK_BG_HIGH_SPEC; +impl crate::RegisterSpec for CK_BG_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ck_bg_high::R`](R) reader structure"] +impl crate::Readable for CK_BG_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ck_bg_high::W`](W) writer structure"] +impl crate::Writable for CK_BG_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CK_BG_HIGH to value 0"] +impl crate::Resettable for CK_BG_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/ck_bg_low.rs b/esp32p4/src/ppa/ck_bg_low.rs new file mode 100644 index 0000000000..2fb5b74ee7 --- /dev/null +++ b/esp32p4/src/ppa/ck_bg_low.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CK_BG_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `CK_BG_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `COLORKEY_BG_B_LOW` reader - color key lower threshold of background b channel"] +pub type COLORKEY_BG_B_LOW_R = crate::FieldReader; +#[doc = "Field `COLORKEY_BG_B_LOW` writer - color key lower threshold of background b channel"] +pub type COLORKEY_BG_B_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLORKEY_BG_G_LOW` reader - color key lower threshold of background g channel"] +pub type COLORKEY_BG_G_LOW_R = crate::FieldReader; +#[doc = "Field `COLORKEY_BG_G_LOW` writer - color key lower threshold of background g channel"] +pub type COLORKEY_BG_G_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLORKEY_BG_R_LOW` reader - color key lower threshold of background r channel"] +pub type COLORKEY_BG_R_LOW_R = crate::FieldReader; +#[doc = "Field `COLORKEY_BG_R_LOW` writer - color key lower threshold of background r channel"] +pub type COLORKEY_BG_R_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - color key lower threshold of background b channel"] + #[inline(always)] + pub fn colorkey_bg_b_low(&self) -> COLORKEY_BG_B_LOW_R { + COLORKEY_BG_B_LOW_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - color key lower threshold of background g channel"] + #[inline(always)] + pub fn colorkey_bg_g_low(&self) -> COLORKEY_BG_G_LOW_R { + COLORKEY_BG_G_LOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - color key lower threshold of background r channel"] + #[inline(always)] + pub fn colorkey_bg_r_low(&self) -> COLORKEY_BG_R_LOW_R { + COLORKEY_BG_R_LOW_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CK_BG_LOW") + .field( + "colorkey_bg_b_low", + &format_args!("{}", self.colorkey_bg_b_low().bits()), + ) + .field( + "colorkey_bg_g_low", + &format_args!("{}", self.colorkey_bg_g_low().bits()), + ) + .field( + "colorkey_bg_r_low", + &format_args!("{}", self.colorkey_bg_r_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - color key lower threshold of background b channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_bg_b_low(&mut self) -> COLORKEY_BG_B_LOW_W { + COLORKEY_BG_B_LOW_W::new(self, 0) + } + #[doc = "Bits 8:15 - color key lower threshold of background g channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_bg_g_low(&mut self) -> COLORKEY_BG_G_LOW_W { + COLORKEY_BG_G_LOW_W::new(self, 8) + } + #[doc = "Bits 16:23 - color key lower threshold of background r channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_bg_r_low(&mut self) -> COLORKEY_BG_R_LOW_W { + COLORKEY_BG_R_LOW_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "background color key lower threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ck_bg_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ck_bg_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CK_BG_LOW_SPEC; +impl crate::RegisterSpec for CK_BG_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ck_bg_low::R`](R) reader structure"] +impl crate::Readable for CK_BG_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ck_bg_low::W`](W) writer structure"] +impl crate::Writable for CK_BG_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CK_BG_LOW to value 0x00ff_ffff"] +impl crate::Resettable for CK_BG_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0x00ff_ffff; +} diff --git a/esp32p4/src/ppa/ck_default.rs b/esp32p4/src/ppa/ck_default.rs new file mode 100644 index 0000000000..5656c1f5b8 --- /dev/null +++ b/esp32p4/src/ppa/ck_default.rs @@ -0,0 +1,123 @@ +#[doc = "Register `CK_DEFAULT` reader"] +pub type R = crate::R; +#[doc = "Register `CK_DEFAULT` writer"] +pub type W = crate::W; +#[doc = "Field `COLORKEY_DEFAULT_B` reader - default B channle value of color key"] +pub type COLORKEY_DEFAULT_B_R = crate::FieldReader; +#[doc = "Field `COLORKEY_DEFAULT_B` writer - default B channle value of color key"] +pub type COLORKEY_DEFAULT_B_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLORKEY_DEFAULT_G` reader - default G channle value of color key"] +pub type COLORKEY_DEFAULT_G_R = crate::FieldReader; +#[doc = "Field `COLORKEY_DEFAULT_G` writer - default G channle value of color key"] +pub type COLORKEY_DEFAULT_G_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLORKEY_DEFAULT_R` reader - default R channle value of color key"] +pub type COLORKEY_DEFAULT_R_R = crate::FieldReader; +#[doc = "Field `COLORKEY_DEFAULT_R` writer - default R channle value of color key"] +pub type COLORKEY_DEFAULT_R_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLORKEY_FG_BG_REVERSE` reader - when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the result is fg"] +pub type COLORKEY_FG_BG_REVERSE_R = crate::BitReader; +#[doc = "Field `COLORKEY_FG_BG_REVERSE` writer - when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the result is fg"] +pub type COLORKEY_FG_BG_REVERSE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - default B channle value of color key"] + #[inline(always)] + pub fn colorkey_default_b(&self) -> COLORKEY_DEFAULT_B_R { + COLORKEY_DEFAULT_B_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - default G channle value of color key"] + #[inline(always)] + pub fn colorkey_default_g(&self) -> COLORKEY_DEFAULT_G_R { + COLORKEY_DEFAULT_G_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - default R channle value of color key"] + #[inline(always)] + pub fn colorkey_default_r(&self) -> COLORKEY_DEFAULT_R_R { + COLORKEY_DEFAULT_R_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 24 - when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the result is fg"] + #[inline(always)] + pub fn colorkey_fg_bg_reverse(&self) -> COLORKEY_FG_BG_REVERSE_R { + COLORKEY_FG_BG_REVERSE_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CK_DEFAULT") + .field( + "colorkey_default_b", + &format_args!("{}", self.colorkey_default_b().bits()), + ) + .field( + "colorkey_default_g", + &format_args!("{}", self.colorkey_default_g().bits()), + ) + .field( + "colorkey_default_r", + &format_args!("{}", self.colorkey_default_r().bits()), + ) + .field( + "colorkey_fg_bg_reverse", + &format_args!("{}", self.colorkey_fg_bg_reverse().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - default B channle value of color key"] + #[inline(always)] + #[must_use] + pub fn colorkey_default_b(&mut self) -> COLORKEY_DEFAULT_B_W { + COLORKEY_DEFAULT_B_W::new(self, 0) + } + #[doc = "Bits 8:15 - default G channle value of color key"] + #[inline(always)] + #[must_use] + pub fn colorkey_default_g(&mut self) -> COLORKEY_DEFAULT_G_W { + COLORKEY_DEFAULT_G_W::new(self, 8) + } + #[doc = "Bits 16:23 - default R channle value of color key"] + #[inline(always)] + #[must_use] + pub fn colorkey_default_r(&mut self) -> COLORKEY_DEFAULT_R_W { + COLORKEY_DEFAULT_R_W::new(self, 16) + } + #[doc = "Bit 24 - when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the result is fg"] + #[inline(always)] + #[must_use] + pub fn colorkey_fg_bg_reverse(&mut self) -> COLORKEY_FG_BG_REVERSE_W { + COLORKEY_FG_BG_REVERSE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "default value when foreground and background both in color key range\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ck_default::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ck_default::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CK_DEFAULT_SPEC; +impl crate::RegisterSpec for CK_DEFAULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ck_default::R`](R) reader structure"] +impl crate::Readable for CK_DEFAULT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ck_default::W`](W) writer structure"] +impl crate::Writable for CK_DEFAULT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CK_DEFAULT to value 0"] +impl crate::Resettable for CK_DEFAULT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/ck_fg_high.rs b/esp32p4/src/ppa/ck_fg_high.rs new file mode 100644 index 0000000000..cec0d5cc0d --- /dev/null +++ b/esp32p4/src/ppa/ck_fg_high.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CK_FG_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `CK_FG_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `COLORKEY_FG_B_HIGH` reader - color key higher threshold of foreground b channel"] +pub type COLORKEY_FG_B_HIGH_R = crate::FieldReader; +#[doc = "Field `COLORKEY_FG_B_HIGH` writer - color key higher threshold of foreground b channel"] +pub type COLORKEY_FG_B_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLORKEY_FG_G_HIGH` reader - color key higher threshold of foreground g channel"] +pub type COLORKEY_FG_G_HIGH_R = crate::FieldReader; +#[doc = "Field `COLORKEY_FG_G_HIGH` writer - color key higher threshold of foreground g channel"] +pub type COLORKEY_FG_G_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLORKEY_FG_R_HIGH` reader - color key higher threshold of foreground r channel"] +pub type COLORKEY_FG_R_HIGH_R = crate::FieldReader; +#[doc = "Field `COLORKEY_FG_R_HIGH` writer - color key higher threshold of foreground r channel"] +pub type COLORKEY_FG_R_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - color key higher threshold of foreground b channel"] + #[inline(always)] + pub fn colorkey_fg_b_high(&self) -> COLORKEY_FG_B_HIGH_R { + COLORKEY_FG_B_HIGH_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - color key higher threshold of foreground g channel"] + #[inline(always)] + pub fn colorkey_fg_g_high(&self) -> COLORKEY_FG_G_HIGH_R { + COLORKEY_FG_G_HIGH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - color key higher threshold of foreground r channel"] + #[inline(always)] + pub fn colorkey_fg_r_high(&self) -> COLORKEY_FG_R_HIGH_R { + COLORKEY_FG_R_HIGH_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CK_FG_HIGH") + .field( + "colorkey_fg_b_high", + &format_args!("{}", self.colorkey_fg_b_high().bits()), + ) + .field( + "colorkey_fg_g_high", + &format_args!("{}", self.colorkey_fg_g_high().bits()), + ) + .field( + "colorkey_fg_r_high", + &format_args!("{}", self.colorkey_fg_r_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - color key higher threshold of foreground b channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_fg_b_high(&mut self) -> COLORKEY_FG_B_HIGH_W { + COLORKEY_FG_B_HIGH_W::new(self, 0) + } + #[doc = "Bits 8:15 - color key higher threshold of foreground g channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_fg_g_high(&mut self) -> COLORKEY_FG_G_HIGH_W { + COLORKEY_FG_G_HIGH_W::new(self, 8) + } + #[doc = "Bits 16:23 - color key higher threshold of foreground r channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_fg_r_high(&mut self) -> COLORKEY_FG_R_HIGH_W { + COLORKEY_FG_R_HIGH_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "foreground color key higher threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ck_fg_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ck_fg_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CK_FG_HIGH_SPEC; +impl crate::RegisterSpec for CK_FG_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ck_fg_high::R`](R) reader structure"] +impl crate::Readable for CK_FG_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ck_fg_high::W`](W) writer structure"] +impl crate::Writable for CK_FG_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CK_FG_HIGH to value 0"] +impl crate::Resettable for CK_FG_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/ck_fg_low.rs b/esp32p4/src/ppa/ck_fg_low.rs new file mode 100644 index 0000000000..329329d8e6 --- /dev/null +++ b/esp32p4/src/ppa/ck_fg_low.rs @@ -0,0 +1,104 @@ +#[doc = "Register `CK_FG_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `CK_FG_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `COLORKEY_FG_B_LOW` reader - color key lower threshold of foreground b channel"] +pub type COLORKEY_FG_B_LOW_R = crate::FieldReader; +#[doc = "Field `COLORKEY_FG_B_LOW` writer - color key lower threshold of foreground b channel"] +pub type COLORKEY_FG_B_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLORKEY_FG_G_LOW` reader - color key lower threshold of foreground g channel"] +pub type COLORKEY_FG_G_LOW_R = crate::FieldReader; +#[doc = "Field `COLORKEY_FG_G_LOW` writer - color key lower threshold of foreground g channel"] +pub type COLORKEY_FG_G_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `COLORKEY_FG_R_LOW` reader - color key lower threshold of foreground r channel"] +pub type COLORKEY_FG_R_LOW_R = crate::FieldReader; +#[doc = "Field `COLORKEY_FG_R_LOW` writer - color key lower threshold of foreground r channel"] +pub type COLORKEY_FG_R_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - color key lower threshold of foreground b channel"] + #[inline(always)] + pub fn colorkey_fg_b_low(&self) -> COLORKEY_FG_B_LOW_R { + COLORKEY_FG_B_LOW_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - color key lower threshold of foreground g channel"] + #[inline(always)] + pub fn colorkey_fg_g_low(&self) -> COLORKEY_FG_G_LOW_R { + COLORKEY_FG_G_LOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - color key lower threshold of foreground r channel"] + #[inline(always)] + pub fn colorkey_fg_r_low(&self) -> COLORKEY_FG_R_LOW_R { + COLORKEY_FG_R_LOW_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CK_FG_LOW") + .field( + "colorkey_fg_b_low", + &format_args!("{}", self.colorkey_fg_b_low().bits()), + ) + .field( + "colorkey_fg_g_low", + &format_args!("{}", self.colorkey_fg_g_low().bits()), + ) + .field( + "colorkey_fg_r_low", + &format_args!("{}", self.colorkey_fg_r_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - color key lower threshold of foreground b channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_fg_b_low(&mut self) -> COLORKEY_FG_B_LOW_W { + COLORKEY_FG_B_LOW_W::new(self, 0) + } + #[doc = "Bits 8:15 - color key lower threshold of foreground g channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_fg_g_low(&mut self) -> COLORKEY_FG_G_LOW_W { + COLORKEY_FG_G_LOW_W::new(self, 8) + } + #[doc = "Bits 16:23 - color key lower threshold of foreground r channel"] + #[inline(always)] + #[must_use] + pub fn colorkey_fg_r_low(&mut self) -> COLORKEY_FG_R_LOW_W { + COLORKEY_FG_R_LOW_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "foreground color key lower threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ck_fg_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ck_fg_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CK_FG_LOW_SPEC; +impl crate::RegisterSpec for CK_FG_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ck_fg_low::R`](R) reader structure"] +impl crate::Readable for CK_FG_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ck_fg_low::W`](W) writer structure"] +impl crate::Writable for CK_FG_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CK_FG_LOW to value 0x00ff_ffff"] +impl crate::Resettable for CK_FG_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0x00ff_ffff; +} diff --git a/esp32p4/src/ppa/clut_cnt.rs b/esp32p4/src/ppa/clut_cnt.rs new file mode 100644 index 0000000000..26c7616d59 --- /dev/null +++ b/esp32p4/src/ppa/clut_cnt.rs @@ -0,0 +1,50 @@ +#[doc = "Register `CLUT_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `BLEND0_CLUT_CNT` reader - The write data counter of BLEND0 CLUT in fifo mode."] +pub type BLEND0_CLUT_CNT_R = crate::FieldReader; +#[doc = "Field `BLEND1_CLUT_CNT` reader - The write data counter of BLEND1 CLUT in fifo mode."] +pub type BLEND1_CLUT_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:8 - The write data counter of BLEND0 CLUT in fifo mode."] + #[inline(always)] + pub fn blend0_clut_cnt(&self) -> BLEND0_CLUT_CNT_R { + BLEND0_CLUT_CNT_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:17 - The write data counter of BLEND1 CLUT in fifo mode."] + #[inline(always)] + pub fn blend1_clut_cnt(&self) -> BLEND1_CLUT_CNT_R { + BLEND1_CLUT_CNT_R::new(((self.bits >> 9) & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLUT_CNT") + .field( + "blend0_clut_cnt", + &format_args!("{}", self.blend0_clut_cnt().bits()), + ) + .field( + "blend1_clut_cnt", + &format_args!("{}", self.blend1_clut_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "BLEND CLUT write counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clut_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLUT_CNT_SPEC; +impl crate::RegisterSpec for CLUT_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clut_cnt::R`](R) reader structure"] +impl crate::Readable for CLUT_CNT_SPEC {} +#[doc = "`reset()` method sets CLUT_CNT to value 0"] +impl crate::Resettable for CLUT_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/clut_conf.rs b/esp32p4/src/ppa/clut_conf.rs new file mode 100644 index 0000000000..e4bee03275 --- /dev/null +++ b/esp32p4/src/ppa/clut_conf.rs @@ -0,0 +1,199 @@ +#[doc = "Register `CLUT_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CLUT_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `APB_FIFO_MASK` reader - 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode."] +pub type APB_FIFO_MASK_R = crate::BitReader; +#[doc = "Field `APB_FIFO_MASK` writer - 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode."] +pub type APB_FIFO_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND0_CLUT_MEM_RST` reader - Write 1 then write 0 to this bit to reset BLEND0 CLUT."] +pub type BLEND0_CLUT_MEM_RST_R = crate::BitReader; +#[doc = "Field `BLEND0_CLUT_MEM_RST` writer - Write 1 then write 0 to this bit to reset BLEND0 CLUT."] +pub type BLEND0_CLUT_MEM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND1_CLUT_MEM_RST` reader - Write 1 then write 0 to this bit to reset BLEND1 CLUT."] +pub type BLEND1_CLUT_MEM_RST_R = crate::BitReader; +#[doc = "Field `BLEND1_CLUT_MEM_RST` writer - Write 1 then write 0 to this bit to reset BLEND1 CLUT."] +pub type BLEND1_CLUT_MEM_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND0_CLUT_MEM_RDADDR_RST` reader - Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode."] +pub type BLEND0_CLUT_MEM_RDADDR_RST_R = crate::BitReader; +#[doc = "Field `BLEND0_CLUT_MEM_RDADDR_RST` writer - Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode."] +pub type BLEND0_CLUT_MEM_RDADDR_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND1_CLUT_MEM_RDADDR_RST` reader - Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode."] +pub type BLEND1_CLUT_MEM_RDADDR_RST_R = crate::BitReader; +#[doc = "Field `BLEND1_CLUT_MEM_RDADDR_RST` writer - Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode."] +pub type BLEND1_CLUT_MEM_RDADDR_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND0_CLUT_MEM_FORCE_PD` reader - 1: force power down BLEND CLUT memory."] +pub type BLEND0_CLUT_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `BLEND0_CLUT_MEM_FORCE_PD` writer - 1: force power down BLEND CLUT memory."] +pub type BLEND0_CLUT_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND0_CLUT_MEM_FORCE_PU` reader - 1: force power up BLEND CLUT memory."] +pub type BLEND0_CLUT_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `BLEND0_CLUT_MEM_FORCE_PU` writer - 1: force power up BLEND CLUT memory."] +pub type BLEND0_CLUT_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND0_CLUT_MEM_CLK_ENA` reader - 1: Force clock on for BLEND CLUT memory."] +pub type BLEND0_CLUT_MEM_CLK_ENA_R = crate::BitReader; +#[doc = "Field `BLEND0_CLUT_MEM_CLK_ENA` writer - 1: Force clock on for BLEND CLUT memory."] +pub type BLEND0_CLUT_MEM_CLK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode."] + #[inline(always)] + pub fn apb_fifo_mask(&self) -> APB_FIFO_MASK_R { + APB_FIFO_MASK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 then write 0 to this bit to reset BLEND0 CLUT."] + #[inline(always)] + pub fn blend0_clut_mem_rst(&self) -> BLEND0_CLUT_MEM_RST_R { + BLEND0_CLUT_MEM_RST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 then write 0 to this bit to reset BLEND1 CLUT."] + #[inline(always)] + pub fn blend1_clut_mem_rst(&self) -> BLEND1_CLUT_MEM_RST_R { + BLEND1_CLUT_MEM_RST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode."] + #[inline(always)] + pub fn blend0_clut_mem_rdaddr_rst(&self) -> BLEND0_CLUT_MEM_RDADDR_RST_R { + BLEND0_CLUT_MEM_RDADDR_RST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode."] + #[inline(always)] + pub fn blend1_clut_mem_rdaddr_rst(&self) -> BLEND1_CLUT_MEM_RDADDR_RST_R { + BLEND1_CLUT_MEM_RDADDR_RST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - 1: force power down BLEND CLUT memory."] + #[inline(always)] + pub fn blend0_clut_mem_force_pd(&self) -> BLEND0_CLUT_MEM_FORCE_PD_R { + BLEND0_CLUT_MEM_FORCE_PD_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1: force power up BLEND CLUT memory."] + #[inline(always)] + pub fn blend0_clut_mem_force_pu(&self) -> BLEND0_CLUT_MEM_FORCE_PU_R { + BLEND0_CLUT_MEM_FORCE_PU_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 1: Force clock on for BLEND CLUT memory."] + #[inline(always)] + pub fn blend0_clut_mem_clk_ena(&self) -> BLEND0_CLUT_MEM_CLK_ENA_R { + BLEND0_CLUT_MEM_CLK_ENA_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLUT_CONF") + .field( + "apb_fifo_mask", + &format_args!("{}", self.apb_fifo_mask().bit()), + ) + .field( + "blend0_clut_mem_rst", + &format_args!("{}", self.blend0_clut_mem_rst().bit()), + ) + .field( + "blend1_clut_mem_rst", + &format_args!("{}", self.blend1_clut_mem_rst().bit()), + ) + .field( + "blend0_clut_mem_rdaddr_rst", + &format_args!("{}", self.blend0_clut_mem_rdaddr_rst().bit()), + ) + .field( + "blend1_clut_mem_rdaddr_rst", + &format_args!("{}", self.blend1_clut_mem_rdaddr_rst().bit()), + ) + .field( + "blend0_clut_mem_force_pd", + &format_args!("{}", self.blend0_clut_mem_force_pd().bit()), + ) + .field( + "blend0_clut_mem_force_pu", + &format_args!("{}", self.blend0_clut_mem_force_pu().bit()), + ) + .field( + "blend0_clut_mem_clk_ena", + &format_args!("{}", self.blend0_clut_mem_clk_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode."] + #[inline(always)] + #[must_use] + pub fn apb_fifo_mask(&mut self) -> APB_FIFO_MASK_W { + APB_FIFO_MASK_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 then write 0 to this bit to reset BLEND0 CLUT."] + #[inline(always)] + #[must_use] + pub fn blend0_clut_mem_rst(&mut self) -> BLEND0_CLUT_MEM_RST_W { + BLEND0_CLUT_MEM_RST_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 then write 0 to this bit to reset BLEND1 CLUT."] + #[inline(always)] + #[must_use] + pub fn blend1_clut_mem_rst(&mut self) -> BLEND1_CLUT_MEM_RST_W { + BLEND1_CLUT_MEM_RST_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode."] + #[inline(always)] + #[must_use] + pub fn blend0_clut_mem_rdaddr_rst(&mut self) -> BLEND0_CLUT_MEM_RDADDR_RST_W { + BLEND0_CLUT_MEM_RDADDR_RST_W::new(self, 3) + } + #[doc = "Bit 4 - Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode."] + #[inline(always)] + #[must_use] + pub fn blend1_clut_mem_rdaddr_rst(&mut self) -> BLEND1_CLUT_MEM_RDADDR_RST_W { + BLEND1_CLUT_MEM_RDADDR_RST_W::new(self, 4) + } + #[doc = "Bit 5 - 1: force power down BLEND CLUT memory."] + #[inline(always)] + #[must_use] + pub fn blend0_clut_mem_force_pd(&mut self) -> BLEND0_CLUT_MEM_FORCE_PD_W { + BLEND0_CLUT_MEM_FORCE_PD_W::new(self, 5) + } + #[doc = "Bit 6 - 1: force power up BLEND CLUT memory."] + #[inline(always)] + #[must_use] + pub fn blend0_clut_mem_force_pu(&mut self) -> BLEND0_CLUT_MEM_FORCE_PU_W { + BLEND0_CLUT_MEM_FORCE_PU_W::new(self, 6) + } + #[doc = "Bit 7 - 1: Force clock on for BLEND CLUT memory."] + #[inline(always)] + #[must_use] + pub fn blend0_clut_mem_clk_ena(&mut self) -> BLEND0_CLUT_MEM_CLK_ENA_W { + BLEND0_CLUT_MEM_CLK_ENA_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "CLUT configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clut_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clut_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLUT_CONF_SPEC; +impl crate::RegisterSpec for CLUT_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clut_conf::R`](R) reader structure"] +impl crate::Readable for CLUT_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clut_conf::W`](W) writer structure"] +impl crate::Writable for CLUT_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLUT_CONF to value 0"] +impl crate::Resettable for CLUT_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/date.rs b/esp32p4/src/ppa/date.rs new file mode 100644 index 0000000000..e762b406f7 --- /dev/null +++ b/esp32p4/src/ppa/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - register version."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - register version."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - register version."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - register version."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PPA Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_4041"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_4041; +} diff --git a/esp32p4/src/ppa/eco_cell_ctrl.rs b/esp32p4/src/ppa/eco_cell_ctrl.rs new file mode 100644 index 0000000000..84d56621aa --- /dev/null +++ b/esp32p4/src/ppa/eco_cell_ctrl.rs @@ -0,0 +1,71 @@ +#[doc = "Register `ECO_CELL_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_CELL_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_RESULT` reader - Reserved."] +pub type RDN_RESULT_R = crate::BitReader; +#[doc = "Field `RDN_ENA` reader - Reserved."] +pub type RDN_ENA_R = crate::BitReader; +#[doc = "Field `RDN_ENA` writer - Reserved."] +pub type RDN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved."] + #[inline(always)] + pub fn rdn_result(&self) -> RDN_RESULT_R { + RDN_RESULT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved."] + #[inline(always)] + pub fn rdn_ena(&self) -> RDN_ENA_R { + RDN_ENA_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_CELL_CTRL") + .field("rdn_result", &format_args!("{}", self.rdn_result().bit())) + .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 1 - Reserved."] + #[inline(always)] + #[must_use] + pub fn rdn_ena(&mut self) -> RDN_ENA_W { + RDN_ENA_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_cell_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_cell_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_CELL_CTRL_SPEC; +impl crate::RegisterSpec for ECO_CELL_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_cell_ctrl::R`](R) reader structure"] +impl crate::Readable for ECO_CELL_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_cell_ctrl::W`](W) writer structure"] +impl crate::Writable for ECO_CELL_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_CELL_CTRL to value 0"] +impl crate::Resettable for ECO_CELL_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/eco_high.rs b/esp32p4/src/ppa/eco_high.rs new file mode 100644 index 0000000000..7f2e9ce761 --- /dev/null +++ b/esp32p4/src/ppa/eco_high.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `RND_ECO_HIGH` reader - Reserved."] +pub type RND_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `RND_ECO_HIGH` writer - Reserved."] +pub type RND_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + pub fn rnd_eco_high(&self) -> RND_ECO_HIGH_R { + RND_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_HIGH") + .field( + "rnd_eco_high", + &format_args!("{}", self.rnd_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + #[must_use] + pub fn rnd_eco_high(&mut self) -> RND_ECO_HIGH_W { + RND_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_HIGH_SPEC; +impl crate::RegisterSpec for ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_high::R`](R) reader structure"] +impl crate::Readable for ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_high::W`](W) writer structure"] +impl crate::Writable for ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_HIGH to value 0xffff_ffff"] +impl crate::Resettable for ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/ppa/eco_low.rs b/esp32p4/src/ppa/eco_low.rs new file mode 100644 index 0000000000..2a818a833f --- /dev/null +++ b/esp32p4/src/ppa/eco_low.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `RND_ECO_LOW` reader - Reserved."] +pub type RND_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `RND_ECO_LOW` writer - Reserved."] +pub type RND_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + pub fn rnd_eco_low(&self) -> RND_ECO_LOW_R { + RND_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_LOW") + .field( + "rnd_eco_low", + &format_args!("{}", self.rnd_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + #[must_use] + pub fn rnd_eco_low(&mut self) -> RND_ECO_LOW_W { + RND_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_LOW_SPEC; +impl crate::RegisterSpec for ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_low::R`](R) reader structure"] +impl crate::Readable for ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_low::W`](W) writer structure"] +impl crate::Writable for ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_LOW to value 0"] +impl crate::Resettable for ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/int_clr.rs b/esp32p4/src/ppa/int_clr.rs new file mode 100644 index 0000000000..dbdf8b1e0f --- /dev/null +++ b/esp32p4/src/ppa/int_clr.rs @@ -0,0 +1,58 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `SR_EOF_INT_CLR` writer - Set this bit to clear the PPA_SR_EOF_INT interrupt."] +pub type SR_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND_EOF_INT_CLR` writer - Set this bit to clear the PPA_BLEND_EOF_INT interrupt."] +pub type BLEND_EOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_PARAM_CFG_ERR_INT_CLR` writer - Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt."] +pub type SR_PARAM_CFG_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the PPA_SR_EOF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn sr_eof_int_clr(&mut self) -> SR_EOF_INT_CLR_W { + SR_EOF_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the PPA_BLEND_EOF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn blend_eof_int_clr(&mut self) -> BLEND_EOF_INT_CLR_W { + BLEND_EOF_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn sr_param_cfg_err_int_clr(&mut self) -> SR_PARAM_CFG_ERR_INT_CLR_W { + SR_PARAM_CFG_ERR_INT_CLR_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/int_ena.rs b/esp32p4/src/ppa/int_ena.rs new file mode 100644 index 0000000000..e56f267017 --- /dev/null +++ b/esp32p4/src/ppa/int_ena.rs @@ -0,0 +1,104 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `SR_EOF_INT_ENA` reader - The interrupt enable bit for the PPA_SR_EOF_INT interrupt."] +pub type SR_EOF_INT_ENA_R = crate::BitReader; +#[doc = "Field `SR_EOF_INT_ENA` writer - The interrupt enable bit for the PPA_SR_EOF_INT interrupt."] +pub type SR_EOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND_EOF_INT_ENA` reader - The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt."] +pub type BLEND_EOF_INT_ENA_R = crate::BitReader; +#[doc = "Field `BLEND_EOF_INT_ENA` writer - The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt."] +pub type BLEND_EOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_PARAM_CFG_ERR_INT_ENA` reader - The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt."] +pub type SR_PARAM_CFG_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SR_PARAM_CFG_ERR_INT_ENA` writer - The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt."] +pub type SR_PARAM_CFG_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the PPA_SR_EOF_INT interrupt."] + #[inline(always)] + pub fn sr_eof_int_ena(&self) -> SR_EOF_INT_ENA_R { + SR_EOF_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt."] + #[inline(always)] + pub fn blend_eof_int_ena(&self) -> BLEND_EOF_INT_ENA_R { + BLEND_EOF_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt."] + #[inline(always)] + pub fn sr_param_cfg_err_int_ena(&self) -> SR_PARAM_CFG_ERR_INT_ENA_R { + SR_PARAM_CFG_ERR_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "sr_eof_int_ena", + &format_args!("{}", self.sr_eof_int_ena().bit()), + ) + .field( + "blend_eof_int_ena", + &format_args!("{}", self.blend_eof_int_ena().bit()), + ) + .field( + "sr_param_cfg_err_int_ena", + &format_args!("{}", self.sr_param_cfg_err_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the PPA_SR_EOF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn sr_eof_int_ena(&mut self) -> SR_EOF_INT_ENA_W { + SR_EOF_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn blend_eof_int_ena(&mut self) -> BLEND_EOF_INT_ENA_W { + BLEND_EOF_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn sr_param_cfg_err_int_ena(&mut self) -> SR_PARAM_CFG_ERR_INT_ENA_W { + SR_PARAM_CFG_ERR_INT_ENA_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/int_raw.rs b/esp32p4/src/ppa/int_raw.rs new file mode 100644 index 0000000000..bea883c302 --- /dev/null +++ b/esp32p4/src/ppa/int_raw.rs @@ -0,0 +1,104 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `SR_EOF_INT_RAW` reader - The raw interrupt bit turns to high level when scaling and rotating engine calculate one frame image."] +pub type SR_EOF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SR_EOF_INT_RAW` writer - The raw interrupt bit turns to high level when scaling and rotating engine calculate one frame image."] +pub type SR_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BLEND_EOF_INT_RAW` reader - The raw interrupt bit turns to high level when blending engine calculate one frame image."] +pub type BLEND_EOF_INT_RAW_R = crate::BitReader; +#[doc = "Field `BLEND_EOF_INT_RAW` writer - The raw interrupt bit turns to high level when blending engine calculate one frame image."] +pub type BLEND_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_PARAM_CFG_ERR_INT_RAW` reader - The raw interrupt bit turns to high level when the configured scaling and rotating coefficient is wrong. User can check the reasons through register PPA_SR_PARAM_ERR_ST_REG."] +pub type SR_PARAM_CFG_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SR_PARAM_CFG_ERR_INT_RAW` writer - The raw interrupt bit turns to high level when the configured scaling and rotating coefficient is wrong. User can check the reasons through register PPA_SR_PARAM_ERR_ST_REG."] +pub type SR_PARAM_CFG_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when scaling and rotating engine calculate one frame image."] + #[inline(always)] + pub fn sr_eof_int_raw(&self) -> SR_EOF_INT_RAW_R { + SR_EOF_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when blending engine calculate one frame image."] + #[inline(always)] + pub fn blend_eof_int_raw(&self) -> BLEND_EOF_INT_RAW_R { + BLEND_EOF_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the configured scaling and rotating coefficient is wrong. User can check the reasons through register PPA_SR_PARAM_ERR_ST_REG."] + #[inline(always)] + pub fn sr_param_cfg_err_int_raw(&self) -> SR_PARAM_CFG_ERR_INT_RAW_R { + SR_PARAM_CFG_ERR_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "sr_eof_int_raw", + &format_args!("{}", self.sr_eof_int_raw().bit()), + ) + .field( + "blend_eof_int_raw", + &format_args!("{}", self.blend_eof_int_raw().bit()), + ) + .field( + "sr_param_cfg_err_int_raw", + &format_args!("{}", self.sr_param_cfg_err_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when scaling and rotating engine calculate one frame image."] + #[inline(always)] + #[must_use] + pub fn sr_eof_int_raw(&mut self) -> SR_EOF_INT_RAW_W { + SR_EOF_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when blending engine calculate one frame image."] + #[inline(always)] + #[must_use] + pub fn blend_eof_int_raw(&mut self) -> BLEND_EOF_INT_RAW_W { + BLEND_EOF_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when the configured scaling and rotating coefficient is wrong. User can check the reasons through register PPA_SR_PARAM_ERR_ST_REG."] + #[inline(always)] + #[must_use] + pub fn sr_param_cfg_err_int_raw(&mut self) -> SR_PARAM_CFG_ERR_INT_RAW_W { + SR_PARAM_CFG_ERR_INT_RAW_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Raw status interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/int_st.rs b/esp32p4/src/ppa/int_st.rs new file mode 100644 index 0000000000..eb9b82810d --- /dev/null +++ b/esp32p4/src/ppa/int_st.rs @@ -0,0 +1,61 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `SR_EOF_INT_ST` reader - The raw interrupt status bit for the PPA_SR_EOF_INT interrupt."] +pub type SR_EOF_INT_ST_R = crate::BitReader; +#[doc = "Field `BLEND_EOF_INT_ST` reader - The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt."] +pub type BLEND_EOF_INT_ST_R = crate::BitReader; +#[doc = "Field `SR_PARAM_CFG_ERR_INT_ST` reader - The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt."] +pub type SR_PARAM_CFG_ERR_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the PPA_SR_EOF_INT interrupt."] + #[inline(always)] + pub fn sr_eof_int_st(&self) -> SR_EOF_INT_ST_R { + SR_EOF_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt."] + #[inline(always)] + pub fn blend_eof_int_st(&self) -> BLEND_EOF_INT_ST_R { + BLEND_EOF_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt."] + #[inline(always)] + pub fn sr_param_cfg_err_int_st(&self) -> SR_PARAM_CFG_ERR_INT_ST_R { + SR_PARAM_CFG_ERR_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "sr_eof_int_st", + &format_args!("{}", self.sr_eof_int_st().bit()), + ) + .field( + "blend_eof_int_st", + &format_args!("{}", self.blend_eof_int_st().bit()), + ) + .field( + "sr_param_cfg_err_int_st", + &format_args!("{}", self.sr_param_cfg_err_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Masked interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/reg_conf.rs b/esp32p4/src/ppa/reg_conf.rs new file mode 100644 index 0000000000..4b23f22ca3 --- /dev/null +++ b/esp32p4/src/ppa/reg_conf.rs @@ -0,0 +1,63 @@ +#[doc = "Register `REG_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `REG_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - PPA register clock gate enable signal."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - PPA register clock gate enable signal."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - PPA register clock gate enable signal."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_CONF") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - PPA register clock gate enable signal."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Register clock enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_CONF_SPEC; +impl crate::RegisterSpec for REG_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_conf::R`](R) reader structure"] +impl crate::Readable for REG_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_conf::W`](W) writer structure"] +impl crate::Writable for REG_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_CONF to value 0"] +impl crate::Resettable for REG_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/sr_byte_order.rs b/esp32p4/src/ppa/sr_byte_order.rs new file mode 100644 index 0000000000..4550a5c3f4 --- /dev/null +++ b/esp32p4/src/ppa/sr_byte_order.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SR_BYTE_ORDER` reader"] +pub type R = crate::R; +#[doc = "Register `SR_BYTE_ORDER` writer"] +pub type W = crate::W; +#[doc = "Field `SR_RX_BYTE_SWAP_EN` reader - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] +pub type SR_RX_BYTE_SWAP_EN_R = crate::BitReader; +#[doc = "Field `SR_RX_BYTE_SWAP_EN` writer - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] +pub type SR_RX_BYTE_SWAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_RX_RGB_SWAP_EN` reader - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] +pub type SR_RX_RGB_SWAP_EN_R = crate::BitReader; +#[doc = "Field `SR_RX_RGB_SWAP_EN` writer - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] +pub type SR_RX_RGB_SWAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_MACRO_BK_RO_BYPASS` reader - Set this bit to 1 to bypass the macro block order function. This function is used to improve efficient accessing external memory."] +pub type SR_MACRO_BK_RO_BYPASS_R = crate::BitReader; +#[doc = "Field `SR_MACRO_BK_RO_BYPASS` writer - Set this bit to 1 to bypass the macro block order function. This function is used to improve efficient accessing external memory."] +pub type SR_MACRO_BK_RO_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] + #[inline(always)] + pub fn sr_rx_byte_swap_en(&self) -> SR_RX_BYTE_SWAP_EN_R { + SR_RX_BYTE_SWAP_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] + #[inline(always)] + pub fn sr_rx_rgb_swap_en(&self) -> SR_RX_RGB_SWAP_EN_R { + SR_RX_RGB_SWAP_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to 1 to bypass the macro block order function. This function is used to improve efficient accessing external memory."] + #[inline(always)] + pub fn sr_macro_bk_ro_bypass(&self) -> SR_MACRO_BK_RO_BYPASS_R { + SR_MACRO_BK_RO_BYPASS_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SR_BYTE_ORDER") + .field( + "sr_rx_byte_swap_en", + &format_args!("{}", self.sr_rx_byte_swap_en().bit()), + ) + .field( + "sr_rx_rgb_swap_en", + &format_args!("{}", self.sr_rx_rgb_swap_en().bit()), + ) + .field( + "sr_macro_bk_ro_bypass", + &format_args!("{}", self.sr_macro_bk_ro_bypass().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."] + #[inline(always)] + #[must_use] + pub fn sr_rx_byte_swap_en(&mut self) -> SR_RX_BYTE_SWAP_EN_W { + SR_RX_BYTE_SWAP_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr."] + #[inline(always)] + #[must_use] + pub fn sr_rx_rgb_swap_en(&mut self) -> SR_RX_RGB_SWAP_EN_W { + SR_RX_RGB_SWAP_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to 1 to bypass the macro block order function. This function is used to improve efficient accessing external memory."] + #[inline(always)] + #[must_use] + pub fn sr_macro_bk_ro_bypass(&mut self) -> SR_MACRO_BK_RO_BYPASS_W { + SR_MACRO_BK_RO_BYPASS_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Scaling and rotating engine byte order register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_byte_order::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr_byte_order::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SR_BYTE_ORDER_SPEC; +impl crate::RegisterSpec for SR_BYTE_ORDER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr_byte_order::R`](R) reader structure"] +impl crate::Readable for SR_BYTE_ORDER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sr_byte_order::W`](W) writer structure"] +impl crate::Writable for SR_BYTE_ORDER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SR_BYTE_ORDER to value 0"] +impl crate::Resettable for SR_BYTE_ORDER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/sr_color_mode.rs b/esp32p4/src/ppa/sr_color_mode.rs new file mode 100644 index 0000000000..dc7c0deb9c --- /dev/null +++ b/esp32p4/src/ppa/sr_color_mode.rs @@ -0,0 +1,155 @@ +#[doc = "Register `SR_COLOR_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SR_COLOR_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SR_RX_CM` reader - The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved."] +pub type SR_RX_CM_R = crate::FieldReader; +#[doc = "Field `SR_RX_CM` writer - The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved."] +pub type SR_RX_CM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SR_TX_CM` reader - The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved."] +pub type SR_TX_CM_R = crate::FieldReader; +#[doc = "Field `SR_TX_CM` writer - The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved."] +pub type SR_TX_CM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `YUV_RX_RANGE` reader - YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range"] +pub type YUV_RX_RANGE_R = crate::BitReader; +#[doc = "Field `YUV_RX_RANGE` writer - YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range"] +pub type YUV_RX_RANGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `YUV_TX_RANGE` reader - YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range"] +pub type YUV_TX_RANGE_R = crate::BitReader; +#[doc = "Field `YUV_TX_RANGE` writer - YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range"] +pub type YUV_TX_RANGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `YUV2RGB_PROTOCAL` reader - YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709"] +pub type YUV2RGB_PROTOCAL_R = crate::BitReader; +#[doc = "Field `YUV2RGB_PROTOCAL` writer - YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709"] +pub type YUV2RGB_PROTOCAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RGB2YUV_PROTOCAL` reader - RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709"] +pub type RGB2YUV_PROTOCAL_R = crate::BitReader; +#[doc = "Field `RGB2YUV_PROTOCAL` writer - RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709"] +pub type RGB2YUV_PROTOCAL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved."] + #[inline(always)] + pub fn sr_rx_cm(&self) -> SR_RX_CM_R { + SR_RX_CM_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved."] + #[inline(always)] + pub fn sr_tx_cm(&self) -> SR_TX_CM_R { + SR_TX_CM_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8 - YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range"] + #[inline(always)] + pub fn yuv_rx_range(&self) -> YUV_RX_RANGE_R { + YUV_RX_RANGE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range"] + #[inline(always)] + pub fn yuv_tx_range(&self) -> YUV_TX_RANGE_R { + YUV_TX_RANGE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709"] + #[inline(always)] + pub fn yuv2rgb_protocal(&self) -> YUV2RGB_PROTOCAL_R { + YUV2RGB_PROTOCAL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709"] + #[inline(always)] + pub fn rgb2yuv_protocal(&self) -> RGB2YUV_PROTOCAL_R { + RGB2YUV_PROTOCAL_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SR_COLOR_MODE") + .field("sr_rx_cm", &format_args!("{}", self.sr_rx_cm().bits())) + .field("sr_tx_cm", &format_args!("{}", self.sr_tx_cm().bits())) + .field( + "yuv_rx_range", + &format_args!("{}", self.yuv_rx_range().bit()), + ) + .field( + "yuv_tx_range", + &format_args!("{}", self.yuv_tx_range().bit()), + ) + .field( + "yuv2rgb_protocal", + &format_args!("{}", self.yuv2rgb_protocal().bit()), + ) + .field( + "rgb2yuv_protocal", + &format_args!("{}", self.rgb2yuv_protocal().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved."] + #[inline(always)] + #[must_use] + pub fn sr_rx_cm(&mut self) -> SR_RX_CM_W { + SR_RX_CM_W::new(self, 0) + } + #[doc = "Bits 4:7 - The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved."] + #[inline(always)] + #[must_use] + pub fn sr_tx_cm(&mut self) -> SR_TX_CM_W { + SR_TX_CM_W::new(self, 4) + } + #[doc = "Bit 8 - YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range"] + #[inline(always)] + #[must_use] + pub fn yuv_rx_range(&mut self) -> YUV_RX_RANGE_W { + YUV_RX_RANGE_W::new(self, 8) + } + #[doc = "Bit 9 - YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range"] + #[inline(always)] + #[must_use] + pub fn yuv_tx_range(&mut self) -> YUV_TX_RANGE_W { + YUV_TX_RANGE_W::new(self, 9) + } + #[doc = "Bit 10 - YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709"] + #[inline(always)] + #[must_use] + pub fn yuv2rgb_protocal(&mut self) -> YUV2RGB_PROTOCAL_W { + YUV2RGB_PROTOCAL_W::new(self, 10) + } + #[doc = "Bit 11 - RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709"] + #[inline(always)] + #[must_use] + pub fn rgb2yuv_protocal(&mut self) -> RGB2YUV_PROTOCAL_W { + RGB2YUV_PROTOCAL_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Scaling and rotating engine color mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_color_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr_color_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SR_COLOR_MODE_SPEC; +impl crate::RegisterSpec for SR_COLOR_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr_color_mode::R`](R) reader structure"] +impl crate::Readable for SR_COLOR_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sr_color_mode::W`](W) writer structure"] +impl crate::Writable for SR_COLOR_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SR_COLOR_MODE to value 0"] +impl crate::Resettable for SR_COLOR_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/sr_fix_alpha.rs b/esp32p4/src/ppa/sr_fix_alpha.rs new file mode 100644 index 0000000000..466250bc81 --- /dev/null +++ b/esp32p4/src/ppa/sr_fix_alpha.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SR_FIX_ALPHA` reader"] +pub type R = crate::R; +#[doc = "Register `SR_FIX_ALPHA` writer"] +pub type W = crate::W; +#[doc = "Field `SR_RX_FIX_ALPHA` reader - The value would replace the alpha value in received pixel for Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN is enabled."] +pub type SR_RX_FIX_ALPHA_R = crate::FieldReader; +#[doc = "Field `SR_RX_FIX_ALPHA` writer - The value would replace the alpha value in received pixel for Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN is enabled."] +pub type SR_RX_FIX_ALPHA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SR_RX_ALPHA_MOD` reader - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] +pub type SR_RX_ALPHA_MOD_R = crate::FieldReader; +#[doc = "Field `SR_RX_ALPHA_MOD` writer - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] +pub type SR_RX_ALPHA_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SR_RX_ALPHA_INV` reader - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] +pub type SR_RX_ALPHA_INV_R = crate::BitReader; +#[doc = "Field `SR_RX_ALPHA_INV` writer - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] +pub type SR_RX_ALPHA_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - The value would replace the alpha value in received pixel for Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN is enabled."] + #[inline(always)] + pub fn sr_rx_fix_alpha(&self) -> SR_RX_FIX_ALPHA_R { + SR_RX_FIX_ALPHA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:9 - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] + #[inline(always)] + pub fn sr_rx_alpha_mod(&self) -> SR_RX_ALPHA_MOD_R { + SR_RX_ALPHA_MOD_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] + #[inline(always)] + pub fn sr_rx_alpha_inv(&self) -> SR_RX_ALPHA_INV_R { + SR_RX_ALPHA_INV_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SR_FIX_ALPHA") + .field( + "sr_rx_fix_alpha", + &format_args!("{}", self.sr_rx_fix_alpha().bits()), + ) + .field( + "sr_rx_alpha_mod", + &format_args!("{}", self.sr_rx_alpha_mod().bits()), + ) + .field( + "sr_rx_alpha_inv", + &format_args!("{}", self.sr_rx_alpha_inv().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - The value would replace the alpha value in received pixel for Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN is enabled."] + #[inline(always)] + #[must_use] + pub fn sr_rx_fix_alpha(&mut self) -> SR_RX_FIX_ALPHA_W { + SR_RX_FIX_ALPHA_W::new(self, 0) + } + #[doc = "Bits 8:9 - Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256."] + #[inline(always)] + #[must_use] + pub fn sr_rx_alpha_mod(&mut self) -> SR_RX_ALPHA_MOD_W { + SR_RX_ALPHA_MOD_W::new(self, 8) + } + #[doc = "Bit 10 - Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255."] + #[inline(always)] + #[must_use] + pub fn sr_rx_alpha_inv(&mut self) -> SR_RX_ALPHA_INV_W { + SR_RX_ALPHA_INV_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Scaling and rotating engine alpha override register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_fix_alpha::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr_fix_alpha::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SR_FIX_ALPHA_SPEC; +impl crate::RegisterSpec for SR_FIX_ALPHA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr_fix_alpha::R`](R) reader structure"] +impl crate::Readable for SR_FIX_ALPHA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sr_fix_alpha::W`](W) writer structure"] +impl crate::Writable for SR_FIX_ALPHA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SR_FIX_ALPHA to value 0x80"] +impl crate::Resettable for SR_FIX_ALPHA_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/ppa/sr_mem_pd.rs b/esp32p4/src/ppa/sr_mem_pd.rs new file mode 100644 index 0000000000..963efae079 --- /dev/null +++ b/esp32p4/src/ppa/sr_mem_pd.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SR_MEM_PD` reader"] +pub type R = crate::R; +#[doc = "Register `SR_MEM_PD` writer"] +pub type W = crate::W; +#[doc = "Field `SR_MEM_CLK_ENA` reader - Set this bit to force clock enable of scaling and rotating engine's data memory."] +pub type SR_MEM_CLK_ENA_R = crate::BitReader; +#[doc = "Field `SR_MEM_CLK_ENA` writer - Set this bit to force clock enable of scaling and rotating engine's data memory."] +pub type SR_MEM_CLK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_MEM_FORCE_PD` reader - Set this bit to force power down scaling and rotating engine's data memory."] +pub type SR_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `SR_MEM_FORCE_PD` writer - Set this bit to force power down scaling and rotating engine's data memory."] +pub type SR_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_MEM_FORCE_PU` reader - Set this bit to force power up scaling and rotating engine's data memory."] +pub type SR_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `SR_MEM_FORCE_PU` writer - Set this bit to force power up scaling and rotating engine's data memory."] +pub type SR_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to force clock enable of scaling and rotating engine's data memory."] + #[inline(always)] + pub fn sr_mem_clk_ena(&self) -> SR_MEM_CLK_ENA_R { + SR_MEM_CLK_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to force power down scaling and rotating engine's data memory."] + #[inline(always)] + pub fn sr_mem_force_pd(&self) -> SR_MEM_FORCE_PD_R { + SR_MEM_FORCE_PD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to force power up scaling and rotating engine's data memory."] + #[inline(always)] + pub fn sr_mem_force_pu(&self) -> SR_MEM_FORCE_PU_R { + SR_MEM_FORCE_PU_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SR_MEM_PD") + .field( + "sr_mem_clk_ena", + &format_args!("{}", self.sr_mem_clk_ena().bit()), + ) + .field( + "sr_mem_force_pd", + &format_args!("{}", self.sr_mem_force_pd().bit()), + ) + .field( + "sr_mem_force_pu", + &format_args!("{}", self.sr_mem_force_pu().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to force clock enable of scaling and rotating engine's data memory."] + #[inline(always)] + #[must_use] + pub fn sr_mem_clk_ena(&mut self) -> SR_MEM_CLK_ENA_W { + SR_MEM_CLK_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to force power down scaling and rotating engine's data memory."] + #[inline(always)] + #[must_use] + pub fn sr_mem_force_pd(&mut self) -> SR_MEM_FORCE_PD_W { + SR_MEM_FORCE_PD_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to force power up scaling and rotating engine's data memory."] + #[inline(always)] + #[must_use] + pub fn sr_mem_force_pu(&mut self) -> SR_MEM_FORCE_PU_W { + SR_MEM_FORCE_PU_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SR memory power done register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_mem_pd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr_mem_pd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SR_MEM_PD_SPEC; +impl crate::RegisterSpec for SR_MEM_PD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr_mem_pd::R`](R) reader structure"] +impl crate::Readable for SR_MEM_PD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sr_mem_pd::W`](W) writer structure"] +impl crate::Writable for SR_MEM_PD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SR_MEM_PD to value 0"] +impl crate::Resettable for SR_MEM_PD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/sr_param_err_st.rs b/esp32p4/src/ppa/sr_param_err_st.rs new file mode 100644 index 0000000000..bb4cb4418a --- /dev/null +++ b/esp32p4/src/ppa/sr_param_err_st.rs @@ -0,0 +1,182 @@ +#[doc = "Register `SR_PARAM_ERR_ST` reader"] +pub type R = crate::R; +#[doc = "Field `TX_DSCR_VB_ERR_ST` reader - The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive descriptor is larger than VA in 2DDMA receive descriptor."] +pub type TX_DSCR_VB_ERR_ST_R = crate::BitReader; +#[doc = "Field `TX_DSCR_HB_ERR_ST` reader - The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive descriptor is larger than HA in 2DDMA receive descriptor."] +pub type TX_DSCR_HB_ERR_ST_R = crate::BitReader; +#[doc = "Field `Y_RX_SCAL_EQUAL_0_ERR_ST` reader - The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0."] +pub type Y_RX_SCAL_EQUAL_0_ERR_ST_R = crate::BitReader; +#[doc = "Field `RX_DSCR_VB_ERR_ST` reader - The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor"] +pub type RX_DSCR_VB_ERR_ST_R = crate::BitReader; +#[doc = "Field `YDST_LEN_TOO_SAMLL_ERR_ST` reader - The error is that the scaled image width is 0. For example. when source width is 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as the result would be floored."] +pub type YDST_LEN_TOO_SAMLL_ERR_ST_R = crate::BitReader; +#[doc = "Field `YDST_LEN_TOO_LARGE_ERR_ST` reader - The error is that the scaled width is larger than (2^13 - 1)."] +pub type YDST_LEN_TOO_LARGE_ERR_ST_R = crate::BitReader; +#[doc = "Field `X_RX_SCAL_EQUAL_0_ERR_ST` reader - The error is that the scaled image height is 0."] +pub type X_RX_SCAL_EQUAL_0_ERR_ST_R = crate::BitReader; +#[doc = "Field `RX_DSCR_HB_ERR_ST` reader - The error is that the HB in 2DDMA transmit descriptor plus the offset of X coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit descriptor."] +pub type RX_DSCR_HB_ERR_ST_R = crate::BitReader; +#[doc = "Field `XDST_LEN_TOO_SAMLL_ERR_ST` reader - The error is that the scaled image height is 0. For example. when source height is 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as the result would be floored."] +pub type XDST_LEN_TOO_SAMLL_ERR_ST_R = crate::BitReader; +#[doc = "Field `XDST_LEN_TOO_LARGE_ERR_ST` reader - The error is that the scaled image height is larger than (2^13 - 1)."] +pub type XDST_LEN_TOO_LARGE_ERR_ST_R = crate::BitReader; +#[doc = "Field `X_YUV420_RX_SCALE_ERR_ST` reader - The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 rx"] +pub type X_YUV420_RX_SCALE_ERR_ST_R = crate::BitReader; +#[doc = "Field `Y_YUV420_RX_SCALE_ERR_ST` reader - The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 rx"] +pub type Y_YUV420_RX_SCALE_ERR_ST_R = crate::BitReader; +#[doc = "Field `X_YUV420_TX_SCALE_ERR_ST` reader - The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 tx"] +pub type X_YUV420_TX_SCALE_ERR_ST_R = crate::BitReader; +#[doc = "Field `Y_YUV420_TX_SCALE_ERR_ST` reader - The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 tx"] +pub type Y_YUV420_TX_SCALE_ERR_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive descriptor is larger than VA in 2DDMA receive descriptor."] + #[inline(always)] + pub fn tx_dscr_vb_err_st(&self) -> TX_DSCR_VB_ERR_ST_R { + TX_DSCR_VB_ERR_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive descriptor is larger than HA in 2DDMA receive descriptor."] + #[inline(always)] + pub fn tx_dscr_hb_err_st(&self) -> TX_DSCR_HB_ERR_ST_R { + TX_DSCR_HB_ERR_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0."] + #[inline(always)] + pub fn y_rx_scal_equal_0_err_st(&self) -> Y_RX_SCAL_EQUAL_0_ERR_ST_R { + Y_RX_SCAL_EQUAL_0_ERR_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor"] + #[inline(always)] + pub fn rx_dscr_vb_err_st(&self) -> RX_DSCR_VB_ERR_ST_R { + RX_DSCR_VB_ERR_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The error is that the scaled image width is 0. For example. when source width is 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as the result would be floored."] + #[inline(always)] + pub fn ydst_len_too_samll_err_st(&self) -> YDST_LEN_TOO_SAMLL_ERR_ST_R { + YDST_LEN_TOO_SAMLL_ERR_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The error is that the scaled width is larger than (2^13 - 1)."] + #[inline(always)] + pub fn ydst_len_too_large_err_st(&self) -> YDST_LEN_TOO_LARGE_ERR_ST_R { + YDST_LEN_TOO_LARGE_ERR_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The error is that the scaled image height is 0."] + #[inline(always)] + pub fn x_rx_scal_equal_0_err_st(&self) -> X_RX_SCAL_EQUAL_0_ERR_ST_R { + X_RX_SCAL_EQUAL_0_ERR_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The error is that the HB in 2DDMA transmit descriptor plus the offset of X coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit descriptor."] + #[inline(always)] + pub fn rx_dscr_hb_err_st(&self) -> RX_DSCR_HB_ERR_ST_R { + RX_DSCR_HB_ERR_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The error is that the scaled image height is 0. For example. when source height is 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as the result would be floored."] + #[inline(always)] + pub fn xdst_len_too_samll_err_st(&self) -> XDST_LEN_TOO_SAMLL_ERR_ST_R { + XDST_LEN_TOO_SAMLL_ERR_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The error is that the scaled image height is larger than (2^13 - 1)."] + #[inline(always)] + pub fn xdst_len_too_large_err_st(&self) -> XDST_LEN_TOO_LARGE_ERR_ST_R { + XDST_LEN_TOO_LARGE_ERR_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 rx"] + #[inline(always)] + pub fn x_yuv420_rx_scale_err_st(&self) -> X_YUV420_RX_SCALE_ERR_ST_R { + X_YUV420_RX_SCALE_ERR_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 rx"] + #[inline(always)] + pub fn y_yuv420_rx_scale_err_st(&self) -> Y_YUV420_RX_SCALE_ERR_ST_R { + Y_YUV420_RX_SCALE_ERR_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 tx"] + #[inline(always)] + pub fn x_yuv420_tx_scale_err_st(&self) -> X_YUV420_TX_SCALE_ERR_ST_R { + X_YUV420_TX_SCALE_ERR_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 tx"] + #[inline(always)] + pub fn y_yuv420_tx_scale_err_st(&self) -> Y_YUV420_TX_SCALE_ERR_ST_R { + Y_YUV420_TX_SCALE_ERR_ST_R::new(((self.bits >> 13) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SR_PARAM_ERR_ST") + .field( + "tx_dscr_vb_err_st", + &format_args!("{}", self.tx_dscr_vb_err_st().bit()), + ) + .field( + "tx_dscr_hb_err_st", + &format_args!("{}", self.tx_dscr_hb_err_st().bit()), + ) + .field( + "y_rx_scal_equal_0_err_st", + &format_args!("{}", self.y_rx_scal_equal_0_err_st().bit()), + ) + .field( + "rx_dscr_vb_err_st", + &format_args!("{}", self.rx_dscr_vb_err_st().bit()), + ) + .field( + "ydst_len_too_samll_err_st", + &format_args!("{}", self.ydst_len_too_samll_err_st().bit()), + ) + .field( + "ydst_len_too_large_err_st", + &format_args!("{}", self.ydst_len_too_large_err_st().bit()), + ) + .field( + "x_rx_scal_equal_0_err_st", + &format_args!("{}", self.x_rx_scal_equal_0_err_st().bit()), + ) + .field( + "rx_dscr_hb_err_st", + &format_args!("{}", self.rx_dscr_hb_err_st().bit()), + ) + .field( + "xdst_len_too_samll_err_st", + &format_args!("{}", self.xdst_len_too_samll_err_st().bit()), + ) + .field( + "xdst_len_too_large_err_st", + &format_args!("{}", self.xdst_len_too_large_err_st().bit()), + ) + .field( + "x_yuv420_rx_scale_err_st", + &format_args!("{}", self.x_yuv420_rx_scale_err_st().bit()), + ) + .field( + "y_yuv420_rx_scale_err_st", + &format_args!("{}", self.y_yuv420_rx_scale_err_st().bit()), + ) + .field( + "x_yuv420_tx_scale_err_st", + &format_args!("{}", self.x_yuv420_tx_scale_err_st().bit()), + ) + .field( + "y_yuv420_tx_scale_err_st", + &format_args!("{}", self.y_yuv420_tx_scale_err_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Scaling and rotating coefficient error register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_param_err_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SR_PARAM_ERR_ST_SPEC; +impl crate::RegisterSpec for SR_PARAM_ERR_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr_param_err_st::R`](R) reader structure"] +impl crate::Readable for SR_PARAM_ERR_ST_SPEC {} +#[doc = "`reset()` method sets SR_PARAM_ERR_ST to value 0"] +impl crate::Resettable for SR_PARAM_ERR_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/sr_scal_rotate.rs b/esp32p4/src/ppa/sr_scal_rotate.rs new file mode 100644 index 0000000000..4d10903ff4 --- /dev/null +++ b/esp32p4/src/ppa/sr_scal_rotate.rs @@ -0,0 +1,201 @@ +#[doc = "Register `SR_SCAL_ROTATE` reader"] +pub type R = crate::R; +#[doc = "Register `SR_SCAL_ROTATE` writer"] +pub type W = crate::W; +#[doc = "Field `SR_SCAL_X_INT` reader - The integrated part of scaling coefficient in X direction."] +pub type SR_SCAL_X_INT_R = crate::FieldReader; +#[doc = "Field `SR_SCAL_X_INT` writer - The integrated part of scaling coefficient in X direction."] +pub type SR_SCAL_X_INT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SR_SCAL_X_FRAG` reader - The fragment part of scaling coefficient in X direction."] +pub type SR_SCAL_X_FRAG_R = crate::FieldReader; +#[doc = "Field `SR_SCAL_X_FRAG` writer - The fragment part of scaling coefficient in X direction."] +pub type SR_SCAL_X_FRAG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SR_SCAL_Y_INT` reader - The integrated part of scaling coefficient in Y direction."] +pub type SR_SCAL_Y_INT_R = crate::FieldReader; +#[doc = "Field `SR_SCAL_Y_INT` writer - The integrated part of scaling coefficient in Y direction."] +pub type SR_SCAL_Y_INT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SR_SCAL_Y_FRAG` reader - The fragment part of scaling coefficient in Y direction."] +pub type SR_SCAL_Y_FRAG_R = crate::FieldReader; +#[doc = "Field `SR_SCAL_Y_FRAG` writer - The fragment part of scaling coefficient in Y direction."] +pub type SR_SCAL_Y_FRAG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SR_ROTATE_ANGLE` reader - The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree."] +pub type SR_ROTATE_ANGLE_R = crate::FieldReader; +#[doc = "Field `SR_ROTATE_ANGLE` writer - The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree."] +pub type SR_ROTATE_ANGLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SCAL_ROTATE_RST` reader - Write 1 then write 0 to this bit to reset scaling and rotating engine."] +pub type SCAL_ROTATE_RST_R = crate::BitReader; +#[doc = "Field `SCAL_ROTATE_RST` writer - Write 1 then write 0 to this bit to reset scaling and rotating engine."] +pub type SCAL_ROTATE_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCAL_ROTATE_START` writer - Write 1 to enable scaling and rotating engine after parameter is configured."] +pub type SCAL_ROTATE_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_MIRROR_X` reader - Image mirror in X direction. 0: disable, 1: enable"] +pub type SR_MIRROR_X_R = crate::BitReader; +#[doc = "Field `SR_MIRROR_X` writer - Image mirror in X direction. 0: disable, 1: enable"] +pub type SR_MIRROR_X_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SR_MIRROR_Y` reader - Image mirror in Y direction. 0: disable, 1: enable"] +pub type SR_MIRROR_Y_R = crate::BitReader; +#[doc = "Field `SR_MIRROR_Y` writer - Image mirror in Y direction. 0: disable, 1: enable"] +pub type SR_MIRROR_Y_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - The integrated part of scaling coefficient in X direction."] + #[inline(always)] + pub fn sr_scal_x_int(&self) -> SR_SCAL_X_INT_R { + SR_SCAL_X_INT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - The fragment part of scaling coefficient in X direction."] + #[inline(always)] + pub fn sr_scal_x_frag(&self) -> SR_SCAL_X_FRAG_R { + SR_SCAL_X_FRAG_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:19 - The integrated part of scaling coefficient in Y direction."] + #[inline(always)] + pub fn sr_scal_y_int(&self) -> SR_SCAL_Y_INT_R { + SR_SCAL_Y_INT_R::new(((self.bits >> 12) & 0xff) as u8) + } + #[doc = "Bits 20:23 - The fragment part of scaling coefficient in Y direction."] + #[inline(always)] + pub fn sr_scal_y_frag(&self) -> SR_SCAL_Y_FRAG_R { + SR_SCAL_Y_FRAG_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:25 - The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree."] + #[inline(always)] + pub fn sr_rotate_angle(&self) -> SR_ROTATE_ANGLE_R { + SR_ROTATE_ANGLE_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - Write 1 then write 0 to this bit to reset scaling and rotating engine."] + #[inline(always)] + pub fn scal_rotate_rst(&self) -> SCAL_ROTATE_RST_R { + SCAL_ROTATE_RST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 28 - Image mirror in X direction. 0: disable, 1: enable"] + #[inline(always)] + pub fn sr_mirror_x(&self) -> SR_MIRROR_X_R { + SR_MIRROR_X_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Image mirror in Y direction. 0: disable, 1: enable"] + #[inline(always)] + pub fn sr_mirror_y(&self) -> SR_MIRROR_Y_R { + SR_MIRROR_Y_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SR_SCAL_ROTATE") + .field( + "sr_scal_x_int", + &format_args!("{}", self.sr_scal_x_int().bits()), + ) + .field( + "sr_scal_x_frag", + &format_args!("{}", self.sr_scal_x_frag().bits()), + ) + .field( + "sr_scal_y_int", + &format_args!("{}", self.sr_scal_y_int().bits()), + ) + .field( + "sr_scal_y_frag", + &format_args!("{}", self.sr_scal_y_frag().bits()), + ) + .field( + "sr_rotate_angle", + &format_args!("{}", self.sr_rotate_angle().bits()), + ) + .field( + "scal_rotate_rst", + &format_args!("{}", self.scal_rotate_rst().bit()), + ) + .field("sr_mirror_x", &format_args!("{}", self.sr_mirror_x().bit())) + .field("sr_mirror_y", &format_args!("{}", self.sr_mirror_y().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - The integrated part of scaling coefficient in X direction."] + #[inline(always)] + #[must_use] + pub fn sr_scal_x_int(&mut self) -> SR_SCAL_X_INT_W { + SR_SCAL_X_INT_W::new(self, 0) + } + #[doc = "Bits 8:11 - The fragment part of scaling coefficient in X direction."] + #[inline(always)] + #[must_use] + pub fn sr_scal_x_frag(&mut self) -> SR_SCAL_X_FRAG_W { + SR_SCAL_X_FRAG_W::new(self, 8) + } + #[doc = "Bits 12:19 - The integrated part of scaling coefficient in Y direction."] + #[inline(always)] + #[must_use] + pub fn sr_scal_y_int(&mut self) -> SR_SCAL_Y_INT_W { + SR_SCAL_Y_INT_W::new(self, 12) + } + #[doc = "Bits 20:23 - The fragment part of scaling coefficient in Y direction."] + #[inline(always)] + #[must_use] + pub fn sr_scal_y_frag(&mut self) -> SR_SCAL_Y_FRAG_W { + SR_SCAL_Y_FRAG_W::new(self, 20) + } + #[doc = "Bits 24:25 - The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree."] + #[inline(always)] + #[must_use] + pub fn sr_rotate_angle(&mut self) -> SR_ROTATE_ANGLE_W { + SR_ROTATE_ANGLE_W::new(self, 24) + } + #[doc = "Bit 26 - Write 1 then write 0 to this bit to reset scaling and rotating engine."] + #[inline(always)] + #[must_use] + pub fn scal_rotate_rst(&mut self) -> SCAL_ROTATE_RST_W { + SCAL_ROTATE_RST_W::new(self, 26) + } + #[doc = "Bit 27 - Write 1 to enable scaling and rotating engine after parameter is configured."] + #[inline(always)] + #[must_use] + pub fn scal_rotate_start(&mut self) -> SCAL_ROTATE_START_W { + SCAL_ROTATE_START_W::new(self, 27) + } + #[doc = "Bit 28 - Image mirror in X direction. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn sr_mirror_x(&mut self) -> SR_MIRROR_X_W { + SR_MIRROR_X_W::new(self, 28) + } + #[doc = "Bit 29 - Image mirror in Y direction. 0: disable, 1: enable"] + #[inline(always)] + #[must_use] + pub fn sr_mirror_y(&mut self) -> SR_MIRROR_Y_W { + SR_MIRROR_Y_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Scaling and rotating coefficient register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_scal_rotate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr_scal_rotate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SR_SCAL_ROTATE_SPEC; +impl crate::RegisterSpec for SR_SCAL_ROTATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr_scal_rotate::R`](R) reader structure"] +impl crate::Readable for SR_SCAL_ROTATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sr_scal_rotate::W`](W) writer structure"] +impl crate::Writable for SR_SCAL_ROTATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SR_SCAL_ROTATE to value 0x1001"] +impl crate::Resettable for SR_SCAL_ROTATE_SPEC { + const RESET_VALUE: Self::Ux = 0x1001; +} diff --git a/esp32p4/src/ppa/sr_status.rs b/esp32p4/src/ppa/sr_status.rs new file mode 100644 index 0000000000..73b48a30b4 --- /dev/null +++ b/esp32p4/src/ppa/sr_status.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SR_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `SR_RX_DSCR_SAMPLE_STATE` reader - Reserved."] +pub type SR_RX_DSCR_SAMPLE_STATE_R = crate::FieldReader; +#[doc = "Field `SR_RX_SCAN_STATE` reader - Reserved."] +pub type SR_RX_SCAN_STATE_R = crate::FieldReader; +#[doc = "Field `SR_TX_DSCR_SAMPLE_STATE` reader - Reserved."] +pub type SR_TX_DSCR_SAMPLE_STATE_R = crate::FieldReader; +#[doc = "Field `SR_TX_SCAN_STATE` reader - Reserved."] +pub type SR_TX_SCAN_STATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Reserved."] + #[inline(always)] + pub fn sr_rx_dscr_sample_state(&self) -> SR_RX_DSCR_SAMPLE_STATE_R { + SR_RX_DSCR_SAMPLE_STATE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Reserved."] + #[inline(always)] + pub fn sr_rx_scan_state(&self) -> SR_RX_SCAN_STATE_R { + SR_RX_SCAN_STATE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Reserved."] + #[inline(always)] + pub fn sr_tx_dscr_sample_state(&self) -> SR_TX_DSCR_SAMPLE_STATE_R { + SR_TX_DSCR_SAMPLE_STATE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:8 - Reserved."] + #[inline(always)] + pub fn sr_tx_scan_state(&self) -> SR_TX_SCAN_STATE_R { + SR_TX_SCAN_STATE_R::new(((self.bits >> 6) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SR_STATUS") + .field( + "sr_rx_dscr_sample_state", + &format_args!("{}", self.sr_rx_dscr_sample_state().bits()), + ) + .field( + "sr_rx_scan_state", + &format_args!("{}", self.sr_rx_scan_state().bits()), + ) + .field( + "sr_tx_dscr_sample_state", + &format_args!("{}", self.sr_tx_dscr_sample_state().bits()), + ) + .field( + "sr_tx_scan_state", + &format_args!("{}", self.sr_tx_scan_state().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "SR FSM register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SR_STATUS_SPEC; +impl crate::RegisterSpec for SR_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr_status::R`](R) reader structure"] +impl crate::Readable for SR_STATUS_SPEC {} +#[doc = "`reset()` method sets SR_STATUS to value 0"] +impl crate::Resettable for SR_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/ppa/sram_ctrl.rs b/esp32p4/src/ppa/sram_ctrl.rs new file mode 100644 index 0000000000..4f70928366 --- /dev/null +++ b/esp32p4/src/ppa/sram_ctrl.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SRAM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `MEM_AUX_CTRL` reader - Control signals"] +pub type MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `MEM_AUX_CTRL` writer - Control signals"] +pub type MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - Control signals"] + #[inline(always)] + pub fn mem_aux_ctrl(&self) -> MEM_AUX_CTRL_R { + MEM_AUX_CTRL_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SRAM_CTRL") + .field( + "mem_aux_ctrl", + &format_args!("{}", self.mem_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Control signals"] + #[inline(always)] + #[must_use] + pub fn mem_aux_ctrl(&mut self) -> MEM_AUX_CTRL_W { + MEM_AUX_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PPA SRAM Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sram_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM_CTRL_SPEC; +impl crate::RegisterSpec for SRAM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram_ctrl::R`](R) reader structure"] +impl crate::Readable for SRAM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram_ctrl::W`](W) writer structure"] +impl crate::Writable for SRAM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SRAM_CTRL to value 0x1320"] +impl crate::Resettable for SRAM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x1320; +} diff --git a/esp32p4/src/pvt.rs b/esp32p4/src/pvt.rs new file mode 100644 index 0000000000..8db266cd08 --- /dev/null +++ b/esp32p4/src/pvt.rs @@ -0,0 +1,1344 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + pmup_bitmap_high0: PMUP_BITMAP_HIGH0, + pmup_bitmap_high1: PMUP_BITMAP_HIGH1, + pmup_bitmap_high2: PMUP_BITMAP_HIGH2, + pmup_bitmap_high3: PMUP_BITMAP_HIGH3, + pmup_bitmap_high4: PMUP_BITMAP_HIGH4, + pmup_bitmap_low0: PMUP_BITMAP_LOW0, + pmup_bitmap_low1: PMUP_BITMAP_LOW1, + pmup_bitmap_low2: PMUP_BITMAP_LOW2, + pmup_bitmap_low3: PMUP_BITMAP_LOW3, + pmup_bitmap_low4: PMUP_BITMAP_LOW4, + pmup_drv_cfg: PMUP_DRV_CFG, + pmup_channel_cfg: PMUP_CHANNEL_CFG, + clk_cfg: CLK_CFG, + dbias_channel_sel0: DBIAS_CHANNEL_SEL0, + dbias_channel_sel1: DBIAS_CHANNEL_SEL1, + dbias_channel0_sel: DBIAS_CHANNEL0_SEL, + dbias_channel1_sel: DBIAS_CHANNEL1_SEL, + dbias_channel2_sel: DBIAS_CHANNEL2_SEL, + dbias_channel3_sel: DBIAS_CHANNEL3_SEL, + dbias_channel4_sel: DBIAS_CHANNEL4_SEL, + dbias_cmd0: DBIAS_CMD0, + dbias_cmd1: DBIAS_CMD1, + dbias_cmd2: DBIAS_CMD2, + dbias_cmd3: DBIAS_CMD3, + dbias_cmd4: DBIAS_CMD4, + dbias_timer: DBIAS_TIMER, + comb_pd_site0_unit0_vt0_conf1: COMB_PD_SITE0_UNIT0_VT0_CONF1, + comb_pd_site0_unit1_vt0_conf1: COMB_PD_SITE0_UNIT1_VT0_CONF1, + comb_pd_site0_unit2_vt0_conf1: COMB_PD_SITE0_UNIT2_VT0_CONF1, + comb_pd_site0_unit3_vt0_conf1: COMB_PD_SITE0_UNIT3_VT0_CONF1, + comb_pd_site0_unit0_vt1_conf1: COMB_PD_SITE0_UNIT0_VT1_CONF1, + comb_pd_site0_unit1_vt1_conf1: COMB_PD_SITE0_UNIT1_VT1_CONF1, + comb_pd_site0_unit2_vt1_conf1: COMB_PD_SITE0_UNIT2_VT1_CONF1, + comb_pd_site0_unit3_vt1_conf1: COMB_PD_SITE0_UNIT3_VT1_CONF1, + comb_pd_site0_unit0_vt2_conf1: COMB_PD_SITE0_UNIT0_VT2_CONF1, + comb_pd_site0_unit1_vt2_conf1: COMB_PD_SITE0_UNIT1_VT2_CONF1, + comb_pd_site0_unit2_vt2_conf1: COMB_PD_SITE0_UNIT2_VT2_CONF1, + comb_pd_site0_unit3_vt2_conf1: COMB_PD_SITE0_UNIT3_VT2_CONF1, + comb_pd_site1_unit0_vt0_conf1: COMB_PD_SITE1_UNIT0_VT0_CONF1, + comb_pd_site1_unit1_vt0_conf1: COMB_PD_SITE1_UNIT1_VT0_CONF1, + comb_pd_site1_unit2_vt0_conf1: COMB_PD_SITE1_UNIT2_VT0_CONF1, + comb_pd_site1_unit3_vt0_conf1: COMB_PD_SITE1_UNIT3_VT0_CONF1, + comb_pd_site1_unit0_vt1_conf1: COMB_PD_SITE1_UNIT0_VT1_CONF1, + comb_pd_site1_unit1_vt1_conf1: COMB_PD_SITE1_UNIT1_VT1_CONF1, + comb_pd_site1_unit2_vt1_conf1: COMB_PD_SITE1_UNIT2_VT1_CONF1, + comb_pd_site1_unit3_vt1_conf1: COMB_PD_SITE1_UNIT3_VT1_CONF1, + comb_pd_site1_unit0_vt2_conf1: COMB_PD_SITE1_UNIT0_VT2_CONF1, + comb_pd_site1_unit1_vt2_conf1: COMB_PD_SITE1_UNIT1_VT2_CONF1, + comb_pd_site1_unit2_vt2_conf1: COMB_PD_SITE1_UNIT2_VT2_CONF1, + comb_pd_site1_unit3_vt2_conf1: COMB_PD_SITE1_UNIT3_VT2_CONF1, + comb_pd_site2_unit0_vt0_conf1: COMB_PD_SITE2_UNIT0_VT0_CONF1, + comb_pd_site2_unit1_vt0_conf1: COMB_PD_SITE2_UNIT1_VT0_CONF1, + comb_pd_site2_unit2_vt0_conf1: COMB_PD_SITE2_UNIT2_VT0_CONF1, + comb_pd_site2_unit3_vt0_conf1: COMB_PD_SITE2_UNIT3_VT0_CONF1, + comb_pd_site2_unit0_vt1_conf1: COMB_PD_SITE2_UNIT0_VT1_CONF1, + comb_pd_site2_unit1_vt1_conf1: COMB_PD_SITE2_UNIT1_VT1_CONF1, + comb_pd_site2_unit2_vt1_conf1: COMB_PD_SITE2_UNIT2_VT1_CONF1, + comb_pd_site2_unit3_vt1_conf1: COMB_PD_SITE2_UNIT3_VT1_CONF1, + comb_pd_site2_unit0_vt2_conf1: COMB_PD_SITE2_UNIT0_VT2_CONF1, + comb_pd_site2_unit1_vt2_conf1: COMB_PD_SITE2_UNIT1_VT2_CONF1, + comb_pd_site2_unit2_vt2_conf1: COMB_PD_SITE2_UNIT2_VT2_CONF1, + comb_pd_site2_unit3_vt2_conf1: COMB_PD_SITE2_UNIT3_VT2_CONF1, + comb_pd_site3_unit0_vt0_conf1: COMB_PD_SITE3_UNIT0_VT0_CONF1, + comb_pd_site3_unit1_vt0_conf1: COMB_PD_SITE3_UNIT1_VT0_CONF1, + comb_pd_site3_unit2_vt0_conf1: COMB_PD_SITE3_UNIT2_VT0_CONF1, + comb_pd_site3_unit3_vt0_conf1: COMB_PD_SITE3_UNIT3_VT0_CONF1, + comb_pd_site3_unit0_vt1_conf1: COMB_PD_SITE3_UNIT0_VT1_CONF1, + comb_pd_site3_unit1_vt1_conf1: COMB_PD_SITE3_UNIT1_VT1_CONF1, + comb_pd_site3_unit2_vt1_conf1: COMB_PD_SITE3_UNIT2_VT1_CONF1, + comb_pd_site3_unit3_vt1_conf1: COMB_PD_SITE3_UNIT3_VT1_CONF1, + comb_pd_site3_unit0_vt2_conf1: COMB_PD_SITE3_UNIT0_VT2_CONF1, + comb_pd_site3_unit1_vt2_conf1: COMB_PD_SITE3_UNIT1_VT2_CONF1, + comb_pd_site3_unit2_vt2_conf1: COMB_PD_SITE3_UNIT2_VT2_CONF1, + comb_pd_site3_unit3_vt2_conf1: COMB_PD_SITE3_UNIT3_VT2_CONF1, + comb_pd_site0_unit0_vt0_conf2: COMB_PD_SITE0_UNIT0_VT0_CONF2, + comb_pd_site0_unit1_vt0_conf2: COMB_PD_SITE0_UNIT1_VT0_CONF2, + comb_pd_site0_unit2_vt0_conf2: COMB_PD_SITE0_UNIT2_VT0_CONF2, + comb_pd_site0_unit3_vt0_conf2: COMB_PD_SITE0_UNIT3_VT0_CONF2, + comb_pd_site0_unit0_vt1_conf2: COMB_PD_SITE0_UNIT0_VT1_CONF2, + comb_pd_site0_unit1_vt1_conf2: COMB_PD_SITE0_UNIT1_VT1_CONF2, + comb_pd_site0_unit2_vt1_conf2: COMB_PD_SITE0_UNIT2_VT1_CONF2, + comb_pd_site0_unit3_vt1_conf2: COMB_PD_SITE0_UNIT3_VT1_CONF2, + comb_pd_site0_unit0_vt2_conf2: COMB_PD_SITE0_UNIT0_VT2_CONF2, + comb_pd_site0_unit1_vt2_conf2: COMB_PD_SITE0_UNIT1_VT2_CONF2, + comb_pd_site0_unit2_vt2_conf2: COMB_PD_SITE0_UNIT2_VT2_CONF2, + comb_pd_site0_unit3_vt2_conf2: COMB_PD_SITE0_UNIT3_VT2_CONF2, + comb_pd_site1_unit0_vt0_conf2: COMB_PD_SITE1_UNIT0_VT0_CONF2, + comb_pd_site1_unit1_vt0_conf2: COMB_PD_SITE1_UNIT1_VT0_CONF2, + comb_pd_site1_unit2_vt0_conf2: COMB_PD_SITE1_UNIT2_VT0_CONF2, + comb_pd_site1_unit3_vt0_conf2: COMB_PD_SITE1_UNIT3_VT0_CONF2, + comb_pd_site1_unit0_vt1_conf2: COMB_PD_SITE1_UNIT0_VT1_CONF2, + comb_pd_site1_unit1_vt1_conf2: COMB_PD_SITE1_UNIT1_VT1_CONF2, + comb_pd_site1_unit2_vt1_conf2: COMB_PD_SITE1_UNIT2_VT1_CONF2, + comb_pd_site1_unit3_vt1_conf2: COMB_PD_SITE1_UNIT3_VT1_CONF2, + comb_pd_site1_unit0_vt2_conf2: COMB_PD_SITE1_UNIT0_VT2_CONF2, + comb_pd_site1_unit1_vt2_conf2: COMB_PD_SITE1_UNIT1_VT2_CONF2, + comb_pd_site1_unit2_vt2_conf2: COMB_PD_SITE1_UNIT2_VT2_CONF2, + comb_pd_site1_unit3_vt2_conf2: COMB_PD_SITE1_UNIT3_VT2_CONF2, + comb_pd_site2_unit0_vt0_conf2: COMB_PD_SITE2_UNIT0_VT0_CONF2, + comb_pd_site2_unit1_vt0_conf2: COMB_PD_SITE2_UNIT1_VT0_CONF2, + comb_pd_site2_unit2_vt0_conf2: COMB_PD_SITE2_UNIT2_VT0_CONF2, + comb_pd_site2_unit3_vt0_conf2: COMB_PD_SITE2_UNIT3_VT0_CONF2, + comb_pd_site2_unit0_vt1_conf2: COMB_PD_SITE2_UNIT0_VT1_CONF2, + comb_pd_site2_unit1_vt1_conf2: COMB_PD_SITE2_UNIT1_VT1_CONF2, + comb_pd_site2_unit2_vt1_conf2: COMB_PD_SITE2_UNIT2_VT1_CONF2, + comb_pd_site2_unit3_vt1_conf2: COMB_PD_SITE2_UNIT3_VT1_CONF2, + comb_pd_site2_unit0_vt2_conf2: COMB_PD_SITE2_UNIT0_VT2_CONF2, + comb_pd_site2_unit1_vt2_conf2: COMB_PD_SITE2_UNIT1_VT2_CONF2, + comb_pd_site2_unit2_vt2_conf2: COMB_PD_SITE2_UNIT2_VT2_CONF2, + comb_pd_site2_unit3_vt2_conf2: COMB_PD_SITE2_UNIT3_VT2_CONF2, + comb_pd_site3_unit0_vt0_conf2: COMB_PD_SITE3_UNIT0_VT0_CONF2, + comb_pd_site3_unit1_vt0_conf2: COMB_PD_SITE3_UNIT1_VT0_CONF2, + comb_pd_site3_unit2_vt0_conf2: COMB_PD_SITE3_UNIT2_VT0_CONF2, + comb_pd_site3_unit3_vt0_conf2: COMB_PD_SITE3_UNIT3_VT0_CONF2, + comb_pd_site3_unit0_vt1_conf2: COMB_PD_SITE3_UNIT0_VT1_CONF2, + comb_pd_site3_unit1_vt1_conf2: COMB_PD_SITE3_UNIT1_VT1_CONF2, + comb_pd_site3_unit2_vt1_conf2: COMB_PD_SITE3_UNIT2_VT1_CONF2, + comb_pd_site3_unit3_vt1_conf2: COMB_PD_SITE3_UNIT3_VT1_CONF2, + comb_pd_site3_unit0_vt2_conf2: COMB_PD_SITE3_UNIT0_VT2_CONF2, + comb_pd_site3_unit1_vt2_conf2: COMB_PD_SITE3_UNIT1_VT2_CONF2, + comb_pd_site3_unit2_vt2_conf2: COMB_PD_SITE3_UNIT2_VT2_CONF2, + comb_pd_site3_unit3_vt2_conf2: COMB_PD_SITE3_UNIT3_VT2_CONF2, + value_update: VALUE_UPDATE, + _reserved123: [u8; 0x0e10], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - select valid pvt channel"] + #[inline(always)] + pub const fn pmup_bitmap_high0(&self) -> &PMUP_BITMAP_HIGH0 { + &self.pmup_bitmap_high0 + } + #[doc = "0x04 - select valid pvt channel"] + #[inline(always)] + pub const fn pmup_bitmap_high1(&self) -> &PMUP_BITMAP_HIGH1 { + &self.pmup_bitmap_high1 + } + #[doc = "0x08 - select valid pvt channel"] + #[inline(always)] + pub const fn pmup_bitmap_high2(&self) -> &PMUP_BITMAP_HIGH2 { + &self.pmup_bitmap_high2 + } + #[doc = "0x0c - select valid pvt channel"] + #[inline(always)] + pub const fn pmup_bitmap_high3(&self) -> &PMUP_BITMAP_HIGH3 { + &self.pmup_bitmap_high3 + } + #[doc = "0x10 - select valid pvt channel"] + #[inline(always)] + pub const fn pmup_bitmap_high4(&self) -> &PMUP_BITMAP_HIGH4 { + &self.pmup_bitmap_high4 + } + #[doc = "0x14 - select valid pvt channel"] + #[inline(always)] + pub const fn pmup_bitmap_low0(&self) -> &PMUP_BITMAP_LOW0 { + &self.pmup_bitmap_low0 + } + #[doc = "0x18 - select valid pvt channel"] + #[inline(always)] + pub const fn pmup_bitmap_low1(&self) -> &PMUP_BITMAP_LOW1 { + &self.pmup_bitmap_low1 + } + #[doc = "0x1c - select valid pvt channel"] + #[inline(always)] + pub const fn pmup_bitmap_low2(&self) -> &PMUP_BITMAP_LOW2 { + &self.pmup_bitmap_low2 + } + #[doc = "0x20 - select valid pvt channel"] + #[inline(always)] + pub const fn pmup_bitmap_low3(&self) -> &PMUP_BITMAP_LOW3 { + &self.pmup_bitmap_low3 + } + #[doc = "0x24 - select valid pvt channel"] + #[inline(always)] + pub const fn pmup_bitmap_low4(&self) -> &PMUP_BITMAP_LOW4 { + &self.pmup_bitmap_low4 + } + #[doc = "0x28 - configure pump drv"] + #[inline(always)] + pub const fn pmup_drv_cfg(&self) -> &PMUP_DRV_CFG { + &self.pmup_drv_cfg + } + #[doc = "0x2c - configure the code of valid pump channel code"] + #[inline(always)] + pub const fn pmup_channel_cfg(&self) -> &PMUP_CHANNEL_CFG { + &self.pmup_channel_cfg + } + #[doc = "0x30 - configure pvt clk"] + #[inline(always)] + pub const fn clk_cfg(&self) -> &CLK_CFG { + &self.clk_cfg + } + #[doc = "0x34 - needs desc"] + #[inline(always)] + pub const fn dbias_channel_sel0(&self) -> &DBIAS_CHANNEL_SEL0 { + &self.dbias_channel_sel0 + } + #[doc = "0x38 - needs desc"] + #[inline(always)] + pub const fn dbias_channel_sel1(&self) -> &DBIAS_CHANNEL_SEL1 { + &self.dbias_channel_sel1 + } + #[doc = "0x3c - needs desc"] + #[inline(always)] + pub const fn dbias_channel0_sel(&self) -> &DBIAS_CHANNEL0_SEL { + &self.dbias_channel0_sel + } + #[doc = "0x40 - needs desc"] + #[inline(always)] + pub const fn dbias_channel1_sel(&self) -> &DBIAS_CHANNEL1_SEL { + &self.dbias_channel1_sel + } + #[doc = "0x44 - needs desc"] + #[inline(always)] + pub const fn dbias_channel2_sel(&self) -> &DBIAS_CHANNEL2_SEL { + &self.dbias_channel2_sel + } + #[doc = "0x48 - needs desc"] + #[inline(always)] + pub const fn dbias_channel3_sel(&self) -> &DBIAS_CHANNEL3_SEL { + &self.dbias_channel3_sel + } + #[doc = "0x4c - needs desc"] + #[inline(always)] + pub const fn dbias_channel4_sel(&self) -> &DBIAS_CHANNEL4_SEL { + &self.dbias_channel4_sel + } + #[doc = "0x50 - needs desc"] + #[inline(always)] + pub const fn dbias_cmd0(&self) -> &DBIAS_CMD0 { + &self.dbias_cmd0 + } + #[doc = "0x54 - needs desc"] + #[inline(always)] + pub const fn dbias_cmd1(&self) -> &DBIAS_CMD1 { + &self.dbias_cmd1 + } + #[doc = "0x58 - needs desc"] + #[inline(always)] + pub const fn dbias_cmd2(&self) -> &DBIAS_CMD2 { + &self.dbias_cmd2 + } + #[doc = "0x5c - needs desc"] + #[inline(always)] + pub const fn dbias_cmd3(&self) -> &DBIAS_CMD3 { + &self.dbias_cmd3 + } + #[doc = "0x60 - needs desc"] + #[inline(always)] + pub const fn dbias_cmd4(&self) -> &DBIAS_CMD4 { + &self.dbias_cmd4 + } + #[doc = "0x64 - needs desc"] + #[inline(always)] + pub const fn dbias_timer(&self) -> &DBIAS_TIMER { + &self.dbias_timer + } + #[doc = "0x68 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit0_vt0_conf1(&self) -> &COMB_PD_SITE0_UNIT0_VT0_CONF1 { + &self.comb_pd_site0_unit0_vt0_conf1 + } + #[doc = "0x6c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit1_vt0_conf1(&self) -> &COMB_PD_SITE0_UNIT1_VT0_CONF1 { + &self.comb_pd_site0_unit1_vt0_conf1 + } + #[doc = "0x70 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit2_vt0_conf1(&self) -> &COMB_PD_SITE0_UNIT2_VT0_CONF1 { + &self.comb_pd_site0_unit2_vt0_conf1 + } + #[doc = "0x74 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit3_vt0_conf1(&self) -> &COMB_PD_SITE0_UNIT3_VT0_CONF1 { + &self.comb_pd_site0_unit3_vt0_conf1 + } + #[doc = "0x78 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit0_vt1_conf1(&self) -> &COMB_PD_SITE0_UNIT0_VT1_CONF1 { + &self.comb_pd_site0_unit0_vt1_conf1 + } + #[doc = "0x7c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit1_vt1_conf1(&self) -> &COMB_PD_SITE0_UNIT1_VT1_CONF1 { + &self.comb_pd_site0_unit1_vt1_conf1 + } + #[doc = "0x80 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit2_vt1_conf1(&self) -> &COMB_PD_SITE0_UNIT2_VT1_CONF1 { + &self.comb_pd_site0_unit2_vt1_conf1 + } + #[doc = "0x84 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit3_vt1_conf1(&self) -> &COMB_PD_SITE0_UNIT3_VT1_CONF1 { + &self.comb_pd_site0_unit3_vt1_conf1 + } + #[doc = "0x88 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit0_vt2_conf1(&self) -> &COMB_PD_SITE0_UNIT0_VT2_CONF1 { + &self.comb_pd_site0_unit0_vt2_conf1 + } + #[doc = "0x8c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit1_vt2_conf1(&self) -> &COMB_PD_SITE0_UNIT1_VT2_CONF1 { + &self.comb_pd_site0_unit1_vt2_conf1 + } + #[doc = "0x90 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit2_vt2_conf1(&self) -> &COMB_PD_SITE0_UNIT2_VT2_CONF1 { + &self.comb_pd_site0_unit2_vt2_conf1 + } + #[doc = "0x94 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit3_vt2_conf1(&self) -> &COMB_PD_SITE0_UNIT3_VT2_CONF1 { + &self.comb_pd_site0_unit3_vt2_conf1 + } + #[doc = "0x98 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit0_vt0_conf1(&self) -> &COMB_PD_SITE1_UNIT0_VT0_CONF1 { + &self.comb_pd_site1_unit0_vt0_conf1 + } + #[doc = "0x9c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit1_vt0_conf1(&self) -> &COMB_PD_SITE1_UNIT1_VT0_CONF1 { + &self.comb_pd_site1_unit1_vt0_conf1 + } + #[doc = "0xa0 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit2_vt0_conf1(&self) -> &COMB_PD_SITE1_UNIT2_VT0_CONF1 { + &self.comb_pd_site1_unit2_vt0_conf1 + } + #[doc = "0xa4 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit3_vt0_conf1(&self) -> &COMB_PD_SITE1_UNIT3_VT0_CONF1 { + &self.comb_pd_site1_unit3_vt0_conf1 + } + #[doc = "0xa8 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit0_vt1_conf1(&self) -> &COMB_PD_SITE1_UNIT0_VT1_CONF1 { + &self.comb_pd_site1_unit0_vt1_conf1 + } + #[doc = "0xac - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit1_vt1_conf1(&self) -> &COMB_PD_SITE1_UNIT1_VT1_CONF1 { + &self.comb_pd_site1_unit1_vt1_conf1 + } + #[doc = "0xb0 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit2_vt1_conf1(&self) -> &COMB_PD_SITE1_UNIT2_VT1_CONF1 { + &self.comb_pd_site1_unit2_vt1_conf1 + } + #[doc = "0xb4 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit3_vt1_conf1(&self) -> &COMB_PD_SITE1_UNIT3_VT1_CONF1 { + &self.comb_pd_site1_unit3_vt1_conf1 + } + #[doc = "0xb8 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit0_vt2_conf1(&self) -> &COMB_PD_SITE1_UNIT0_VT2_CONF1 { + &self.comb_pd_site1_unit0_vt2_conf1 + } + #[doc = "0xbc - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit1_vt2_conf1(&self) -> &COMB_PD_SITE1_UNIT1_VT2_CONF1 { + &self.comb_pd_site1_unit1_vt2_conf1 + } + #[doc = "0xc0 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit2_vt2_conf1(&self) -> &COMB_PD_SITE1_UNIT2_VT2_CONF1 { + &self.comb_pd_site1_unit2_vt2_conf1 + } + #[doc = "0xc4 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit3_vt2_conf1(&self) -> &COMB_PD_SITE1_UNIT3_VT2_CONF1 { + &self.comb_pd_site1_unit3_vt2_conf1 + } + #[doc = "0xc8 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit0_vt0_conf1(&self) -> &COMB_PD_SITE2_UNIT0_VT0_CONF1 { + &self.comb_pd_site2_unit0_vt0_conf1 + } + #[doc = "0xcc - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit1_vt0_conf1(&self) -> &COMB_PD_SITE2_UNIT1_VT0_CONF1 { + &self.comb_pd_site2_unit1_vt0_conf1 + } + #[doc = "0xd0 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit2_vt0_conf1(&self) -> &COMB_PD_SITE2_UNIT2_VT0_CONF1 { + &self.comb_pd_site2_unit2_vt0_conf1 + } + #[doc = "0xd4 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit3_vt0_conf1(&self) -> &COMB_PD_SITE2_UNIT3_VT0_CONF1 { + &self.comb_pd_site2_unit3_vt0_conf1 + } + #[doc = "0xd8 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit0_vt1_conf1(&self) -> &COMB_PD_SITE2_UNIT0_VT1_CONF1 { + &self.comb_pd_site2_unit0_vt1_conf1 + } + #[doc = "0xdc - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit1_vt1_conf1(&self) -> &COMB_PD_SITE2_UNIT1_VT1_CONF1 { + &self.comb_pd_site2_unit1_vt1_conf1 + } + #[doc = "0xe0 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit2_vt1_conf1(&self) -> &COMB_PD_SITE2_UNIT2_VT1_CONF1 { + &self.comb_pd_site2_unit2_vt1_conf1 + } + #[doc = "0xe4 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit3_vt1_conf1(&self) -> &COMB_PD_SITE2_UNIT3_VT1_CONF1 { + &self.comb_pd_site2_unit3_vt1_conf1 + } + #[doc = "0xe8 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit0_vt2_conf1(&self) -> &COMB_PD_SITE2_UNIT0_VT2_CONF1 { + &self.comb_pd_site2_unit0_vt2_conf1 + } + #[doc = "0xec - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit1_vt2_conf1(&self) -> &COMB_PD_SITE2_UNIT1_VT2_CONF1 { + &self.comb_pd_site2_unit1_vt2_conf1 + } + #[doc = "0xf0 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit2_vt2_conf1(&self) -> &COMB_PD_SITE2_UNIT2_VT2_CONF1 { + &self.comb_pd_site2_unit2_vt2_conf1 + } + #[doc = "0xf4 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit3_vt2_conf1(&self) -> &COMB_PD_SITE2_UNIT3_VT2_CONF1 { + &self.comb_pd_site2_unit3_vt2_conf1 + } + #[doc = "0xf8 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit0_vt0_conf1(&self) -> &COMB_PD_SITE3_UNIT0_VT0_CONF1 { + &self.comb_pd_site3_unit0_vt0_conf1 + } + #[doc = "0xfc - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit1_vt0_conf1(&self) -> &COMB_PD_SITE3_UNIT1_VT0_CONF1 { + &self.comb_pd_site3_unit1_vt0_conf1 + } + #[doc = "0x100 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit2_vt0_conf1(&self) -> &COMB_PD_SITE3_UNIT2_VT0_CONF1 { + &self.comb_pd_site3_unit2_vt0_conf1 + } + #[doc = "0x104 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit3_vt0_conf1(&self) -> &COMB_PD_SITE3_UNIT3_VT0_CONF1 { + &self.comb_pd_site3_unit3_vt0_conf1 + } + #[doc = "0x108 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit0_vt1_conf1(&self) -> &COMB_PD_SITE3_UNIT0_VT1_CONF1 { + &self.comb_pd_site3_unit0_vt1_conf1 + } + #[doc = "0x10c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit1_vt1_conf1(&self) -> &COMB_PD_SITE3_UNIT1_VT1_CONF1 { + &self.comb_pd_site3_unit1_vt1_conf1 + } + #[doc = "0x110 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit2_vt1_conf1(&self) -> &COMB_PD_SITE3_UNIT2_VT1_CONF1 { + &self.comb_pd_site3_unit2_vt1_conf1 + } + #[doc = "0x114 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit3_vt1_conf1(&self) -> &COMB_PD_SITE3_UNIT3_VT1_CONF1 { + &self.comb_pd_site3_unit3_vt1_conf1 + } + #[doc = "0x118 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit0_vt2_conf1(&self) -> &COMB_PD_SITE3_UNIT0_VT2_CONF1 { + &self.comb_pd_site3_unit0_vt2_conf1 + } + #[doc = "0x11c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit1_vt2_conf1(&self) -> &COMB_PD_SITE3_UNIT1_VT2_CONF1 { + &self.comb_pd_site3_unit1_vt2_conf1 + } + #[doc = "0x120 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit2_vt2_conf1(&self) -> &COMB_PD_SITE3_UNIT2_VT2_CONF1 { + &self.comb_pd_site3_unit2_vt2_conf1 + } + #[doc = "0x124 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit3_vt2_conf1(&self) -> &COMB_PD_SITE3_UNIT3_VT2_CONF1 { + &self.comb_pd_site3_unit3_vt2_conf1 + } + #[doc = "0x128 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit0_vt0_conf2(&self) -> &COMB_PD_SITE0_UNIT0_VT0_CONF2 { + &self.comb_pd_site0_unit0_vt0_conf2 + } + #[doc = "0x12c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit1_vt0_conf2(&self) -> &COMB_PD_SITE0_UNIT1_VT0_CONF2 { + &self.comb_pd_site0_unit1_vt0_conf2 + } + #[doc = "0x130 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit2_vt0_conf2(&self) -> &COMB_PD_SITE0_UNIT2_VT0_CONF2 { + &self.comb_pd_site0_unit2_vt0_conf2 + } + #[doc = "0x134 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit3_vt0_conf2(&self) -> &COMB_PD_SITE0_UNIT3_VT0_CONF2 { + &self.comb_pd_site0_unit3_vt0_conf2 + } + #[doc = "0x138 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit0_vt1_conf2(&self) -> &COMB_PD_SITE0_UNIT0_VT1_CONF2 { + &self.comb_pd_site0_unit0_vt1_conf2 + } + #[doc = "0x13c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit1_vt1_conf2(&self) -> &COMB_PD_SITE0_UNIT1_VT1_CONF2 { + &self.comb_pd_site0_unit1_vt1_conf2 + } + #[doc = "0x140 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit2_vt1_conf2(&self) -> &COMB_PD_SITE0_UNIT2_VT1_CONF2 { + &self.comb_pd_site0_unit2_vt1_conf2 + } + #[doc = "0x144 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit3_vt1_conf2(&self) -> &COMB_PD_SITE0_UNIT3_VT1_CONF2 { + &self.comb_pd_site0_unit3_vt1_conf2 + } + #[doc = "0x148 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit0_vt2_conf2(&self) -> &COMB_PD_SITE0_UNIT0_VT2_CONF2 { + &self.comb_pd_site0_unit0_vt2_conf2 + } + #[doc = "0x14c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit1_vt2_conf2(&self) -> &COMB_PD_SITE0_UNIT1_VT2_CONF2 { + &self.comb_pd_site0_unit1_vt2_conf2 + } + #[doc = "0x150 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit2_vt2_conf2(&self) -> &COMB_PD_SITE0_UNIT2_VT2_CONF2 { + &self.comb_pd_site0_unit2_vt2_conf2 + } + #[doc = "0x154 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site0_unit3_vt2_conf2(&self) -> &COMB_PD_SITE0_UNIT3_VT2_CONF2 { + &self.comb_pd_site0_unit3_vt2_conf2 + } + #[doc = "0x158 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit0_vt0_conf2(&self) -> &COMB_PD_SITE1_UNIT0_VT0_CONF2 { + &self.comb_pd_site1_unit0_vt0_conf2 + } + #[doc = "0x15c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit1_vt0_conf2(&self) -> &COMB_PD_SITE1_UNIT1_VT0_CONF2 { + &self.comb_pd_site1_unit1_vt0_conf2 + } + #[doc = "0x160 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit2_vt0_conf2(&self) -> &COMB_PD_SITE1_UNIT2_VT0_CONF2 { + &self.comb_pd_site1_unit2_vt0_conf2 + } + #[doc = "0x164 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit3_vt0_conf2(&self) -> &COMB_PD_SITE1_UNIT3_VT0_CONF2 { + &self.comb_pd_site1_unit3_vt0_conf2 + } + #[doc = "0x168 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit0_vt1_conf2(&self) -> &COMB_PD_SITE1_UNIT0_VT1_CONF2 { + &self.comb_pd_site1_unit0_vt1_conf2 + } + #[doc = "0x16c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit1_vt1_conf2(&self) -> &COMB_PD_SITE1_UNIT1_VT1_CONF2 { + &self.comb_pd_site1_unit1_vt1_conf2 + } + #[doc = "0x170 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit2_vt1_conf2(&self) -> &COMB_PD_SITE1_UNIT2_VT1_CONF2 { + &self.comb_pd_site1_unit2_vt1_conf2 + } + #[doc = "0x174 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit3_vt1_conf2(&self) -> &COMB_PD_SITE1_UNIT3_VT1_CONF2 { + &self.comb_pd_site1_unit3_vt1_conf2 + } + #[doc = "0x178 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit0_vt2_conf2(&self) -> &COMB_PD_SITE1_UNIT0_VT2_CONF2 { + &self.comb_pd_site1_unit0_vt2_conf2 + } + #[doc = "0x17c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit1_vt2_conf2(&self) -> &COMB_PD_SITE1_UNIT1_VT2_CONF2 { + &self.comb_pd_site1_unit1_vt2_conf2 + } + #[doc = "0x180 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit2_vt2_conf2(&self) -> &COMB_PD_SITE1_UNIT2_VT2_CONF2 { + &self.comb_pd_site1_unit2_vt2_conf2 + } + #[doc = "0x184 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site1_unit3_vt2_conf2(&self) -> &COMB_PD_SITE1_UNIT3_VT2_CONF2 { + &self.comb_pd_site1_unit3_vt2_conf2 + } + #[doc = "0x188 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit0_vt0_conf2(&self) -> &COMB_PD_SITE2_UNIT0_VT0_CONF2 { + &self.comb_pd_site2_unit0_vt0_conf2 + } + #[doc = "0x18c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit1_vt0_conf2(&self) -> &COMB_PD_SITE2_UNIT1_VT0_CONF2 { + &self.comb_pd_site2_unit1_vt0_conf2 + } + #[doc = "0x190 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit2_vt0_conf2(&self) -> &COMB_PD_SITE2_UNIT2_VT0_CONF2 { + &self.comb_pd_site2_unit2_vt0_conf2 + } + #[doc = "0x194 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit3_vt0_conf2(&self) -> &COMB_PD_SITE2_UNIT3_VT0_CONF2 { + &self.comb_pd_site2_unit3_vt0_conf2 + } + #[doc = "0x198 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit0_vt1_conf2(&self) -> &COMB_PD_SITE2_UNIT0_VT1_CONF2 { + &self.comb_pd_site2_unit0_vt1_conf2 + } + #[doc = "0x19c - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit1_vt1_conf2(&self) -> &COMB_PD_SITE2_UNIT1_VT1_CONF2 { + &self.comb_pd_site2_unit1_vt1_conf2 + } + #[doc = "0x1a0 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit2_vt1_conf2(&self) -> &COMB_PD_SITE2_UNIT2_VT1_CONF2 { + &self.comb_pd_site2_unit2_vt1_conf2 + } + #[doc = "0x1a4 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit3_vt1_conf2(&self) -> &COMB_PD_SITE2_UNIT3_VT1_CONF2 { + &self.comb_pd_site2_unit3_vt1_conf2 + } + #[doc = "0x1a8 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit0_vt2_conf2(&self) -> &COMB_PD_SITE2_UNIT0_VT2_CONF2 { + &self.comb_pd_site2_unit0_vt2_conf2 + } + #[doc = "0x1ac - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit1_vt2_conf2(&self) -> &COMB_PD_SITE2_UNIT1_VT2_CONF2 { + &self.comb_pd_site2_unit1_vt2_conf2 + } + #[doc = "0x1b0 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit2_vt2_conf2(&self) -> &COMB_PD_SITE2_UNIT2_VT2_CONF2 { + &self.comb_pd_site2_unit2_vt2_conf2 + } + #[doc = "0x1b4 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site2_unit3_vt2_conf2(&self) -> &COMB_PD_SITE2_UNIT3_VT2_CONF2 { + &self.comb_pd_site2_unit3_vt2_conf2 + } + #[doc = "0x1b8 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit0_vt0_conf2(&self) -> &COMB_PD_SITE3_UNIT0_VT0_CONF2 { + &self.comb_pd_site3_unit0_vt0_conf2 + } + #[doc = "0x1bc - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit1_vt0_conf2(&self) -> &COMB_PD_SITE3_UNIT1_VT0_CONF2 { + &self.comb_pd_site3_unit1_vt0_conf2 + } + #[doc = "0x1c0 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit2_vt0_conf2(&self) -> &COMB_PD_SITE3_UNIT2_VT0_CONF2 { + &self.comb_pd_site3_unit2_vt0_conf2 + } + #[doc = "0x1c4 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit3_vt0_conf2(&self) -> &COMB_PD_SITE3_UNIT3_VT0_CONF2 { + &self.comb_pd_site3_unit3_vt0_conf2 + } + #[doc = "0x1c8 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit0_vt1_conf2(&self) -> &COMB_PD_SITE3_UNIT0_VT1_CONF2 { + &self.comb_pd_site3_unit0_vt1_conf2 + } + #[doc = "0x1cc - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit1_vt1_conf2(&self) -> &COMB_PD_SITE3_UNIT1_VT1_CONF2 { + &self.comb_pd_site3_unit1_vt1_conf2 + } + #[doc = "0x1d0 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit2_vt1_conf2(&self) -> &COMB_PD_SITE3_UNIT2_VT1_CONF2 { + &self.comb_pd_site3_unit2_vt1_conf2 + } + #[doc = "0x1d4 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit3_vt1_conf2(&self) -> &COMB_PD_SITE3_UNIT3_VT1_CONF2 { + &self.comb_pd_site3_unit3_vt1_conf2 + } + #[doc = "0x1d8 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit0_vt2_conf2(&self) -> &COMB_PD_SITE3_UNIT0_VT2_CONF2 { + &self.comb_pd_site3_unit0_vt2_conf2 + } + #[doc = "0x1dc - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit1_vt2_conf2(&self) -> &COMB_PD_SITE3_UNIT1_VT2_CONF2 { + &self.comb_pd_site3_unit1_vt2_conf2 + } + #[doc = "0x1e0 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit2_vt2_conf2(&self) -> &COMB_PD_SITE3_UNIT2_VT2_CONF2 { + &self.comb_pd_site3_unit2_vt2_conf2 + } + #[doc = "0x1e4 - needs desc"] + #[inline(always)] + pub const fn comb_pd_site3_unit3_vt2_conf2(&self) -> &COMB_PD_SITE3_UNIT3_VT2_CONF2 { + &self.comb_pd_site3_unit3_vt2_conf2 + } + #[doc = "0x1e8 - needs field desc"] + #[inline(always)] + pub const fn value_update(&self) -> &VALUE_UPDATE { + &self.value_update + } + #[doc = "0xffc - version register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "PMUP_BITMAP_HIGH0 (rw) register accessor: select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_high0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_high0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_bitmap_high0`] module"] +pub type PMUP_BITMAP_HIGH0 = crate::Reg; +#[doc = "select valid pvt channel"] +pub mod pmup_bitmap_high0; +#[doc = "PMUP_BITMAP_HIGH1 (rw) register accessor: select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_high1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_high1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_bitmap_high1`] module"] +pub type PMUP_BITMAP_HIGH1 = crate::Reg; +#[doc = "select valid pvt channel"] +pub mod pmup_bitmap_high1; +#[doc = "PMUP_BITMAP_HIGH2 (rw) register accessor: select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_high2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_high2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_bitmap_high2`] module"] +pub type PMUP_BITMAP_HIGH2 = crate::Reg; +#[doc = "select valid pvt channel"] +pub mod pmup_bitmap_high2; +#[doc = "PMUP_BITMAP_HIGH3 (rw) register accessor: select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_high3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_high3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_bitmap_high3`] module"] +pub type PMUP_BITMAP_HIGH3 = crate::Reg; +#[doc = "select valid pvt channel"] +pub mod pmup_bitmap_high3; +#[doc = "PMUP_BITMAP_HIGH4 (rw) register accessor: select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_high4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_high4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_bitmap_high4`] module"] +pub type PMUP_BITMAP_HIGH4 = crate::Reg; +#[doc = "select valid pvt channel"] +pub mod pmup_bitmap_high4; +#[doc = "PMUP_BITMAP_LOW0 (rw) register accessor: select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_low0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_low0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_bitmap_low0`] module"] +pub type PMUP_BITMAP_LOW0 = crate::Reg; +#[doc = "select valid pvt channel"] +pub mod pmup_bitmap_low0; +#[doc = "PMUP_BITMAP_LOW1 (rw) register accessor: select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_low1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_low1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_bitmap_low1`] module"] +pub type PMUP_BITMAP_LOW1 = crate::Reg; +#[doc = "select valid pvt channel"] +pub mod pmup_bitmap_low1; +#[doc = "PMUP_BITMAP_LOW2 (rw) register accessor: select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_low2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_low2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_bitmap_low2`] module"] +pub type PMUP_BITMAP_LOW2 = crate::Reg; +#[doc = "select valid pvt channel"] +pub mod pmup_bitmap_low2; +#[doc = "PMUP_BITMAP_LOW3 (rw) register accessor: select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_low3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_low3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_bitmap_low3`] module"] +pub type PMUP_BITMAP_LOW3 = crate::Reg; +#[doc = "select valid pvt channel"] +pub mod pmup_bitmap_low3; +#[doc = "PMUP_BITMAP_LOW4 (rw) register accessor: select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_low4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_low4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_bitmap_low4`] module"] +pub type PMUP_BITMAP_LOW4 = crate::Reg; +#[doc = "select valid pvt channel"] +pub mod pmup_bitmap_low4; +#[doc = "PMUP_DRV_CFG (rw) register accessor: configure pump drv\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_drv_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_drv_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_drv_cfg`] module"] +pub type PMUP_DRV_CFG = crate::Reg; +#[doc = "configure pump drv"] +pub mod pmup_drv_cfg; +#[doc = "PMUP_CHANNEL_CFG (rw) register accessor: configure the code of valid pump channel code\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_channel_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_channel_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmup_channel_cfg`] module"] +pub type PMUP_CHANNEL_CFG = crate::Reg; +#[doc = "configure the code of valid pump channel code"] +pub mod pmup_channel_cfg; +#[doc = "CLK_CFG (rw) register accessor: configure pvt clk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_cfg`] module"] +pub type CLK_CFG = crate::Reg; +#[doc = "configure pvt clk"] +pub mod clk_cfg; +#[doc = "DBIAS_CHANNEL_SEL0 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel_sel0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel_sel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_channel_sel0`] module"] +pub type DBIAS_CHANNEL_SEL0 = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_channel_sel0; +#[doc = "DBIAS_CHANNEL_SEL1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel_sel1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel_sel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_channel_sel1`] module"] +pub type DBIAS_CHANNEL_SEL1 = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_channel_sel1; +#[doc = "DBIAS_CHANNEL0_SEL (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel0_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel0_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_channel0_sel`] module"] +pub type DBIAS_CHANNEL0_SEL = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_channel0_sel; +#[doc = "DBIAS_CHANNEL1_SEL (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel1_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel1_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_channel1_sel`] module"] +pub type DBIAS_CHANNEL1_SEL = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_channel1_sel; +#[doc = "DBIAS_CHANNEL2_SEL (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel2_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel2_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_channel2_sel`] module"] +pub type DBIAS_CHANNEL2_SEL = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_channel2_sel; +#[doc = "DBIAS_CHANNEL3_SEL (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel3_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel3_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_channel3_sel`] module"] +pub type DBIAS_CHANNEL3_SEL = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_channel3_sel; +#[doc = "DBIAS_CHANNEL4_SEL (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel4_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel4_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_channel4_sel`] module"] +pub type DBIAS_CHANNEL4_SEL = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_channel4_sel; +#[doc = "DBIAS_CMD0 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_cmd0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_cmd0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_cmd0`] module"] +pub type DBIAS_CMD0 = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_cmd0; +#[doc = "DBIAS_CMD1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_cmd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_cmd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_cmd1`] module"] +pub type DBIAS_CMD1 = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_cmd1; +#[doc = "DBIAS_CMD2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_cmd2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_cmd2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_cmd2`] module"] +pub type DBIAS_CMD2 = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_cmd2; +#[doc = "DBIAS_CMD3 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_cmd3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_cmd3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_cmd3`] module"] +pub type DBIAS_CMD3 = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_cmd3; +#[doc = "DBIAS_CMD4 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_cmd4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_cmd4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_cmd4`] module"] +pub type DBIAS_CMD4 = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_cmd4; +#[doc = "DBIAS_TIMER (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_timer::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_timer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbias_timer`] module"] +pub type DBIAS_TIMER = crate::Reg; +#[doc = "needs desc"] +pub mod dbias_timer; +#[doc = "COMB_PD_SITE0_UNIT0_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit0_vt0_conf1`] module"] +pub type COMB_PD_SITE0_UNIT0_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit0_vt0_conf1; +#[doc = "COMB_PD_SITE0_UNIT1_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit1_vt0_conf1`] module"] +pub type COMB_PD_SITE0_UNIT1_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit1_vt0_conf1; +#[doc = "COMB_PD_SITE0_UNIT2_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit2_vt0_conf1`] module"] +pub type COMB_PD_SITE0_UNIT2_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit2_vt0_conf1; +#[doc = "COMB_PD_SITE0_UNIT3_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit3_vt0_conf1`] module"] +pub type COMB_PD_SITE0_UNIT3_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit3_vt0_conf1; +#[doc = "COMB_PD_SITE0_UNIT0_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit0_vt1_conf1`] module"] +pub type COMB_PD_SITE0_UNIT0_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit0_vt1_conf1; +#[doc = "COMB_PD_SITE0_UNIT1_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit1_vt1_conf1`] module"] +pub type COMB_PD_SITE0_UNIT1_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit1_vt1_conf1; +#[doc = "COMB_PD_SITE0_UNIT2_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit2_vt1_conf1`] module"] +pub type COMB_PD_SITE0_UNIT2_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit2_vt1_conf1; +#[doc = "COMB_PD_SITE0_UNIT3_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit3_vt1_conf1`] module"] +pub type COMB_PD_SITE0_UNIT3_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit3_vt1_conf1; +#[doc = "COMB_PD_SITE0_UNIT0_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit0_vt2_conf1`] module"] +pub type COMB_PD_SITE0_UNIT0_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit0_vt2_conf1; +#[doc = "COMB_PD_SITE0_UNIT1_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit1_vt2_conf1`] module"] +pub type COMB_PD_SITE0_UNIT1_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit1_vt2_conf1; +#[doc = "COMB_PD_SITE0_UNIT2_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit2_vt2_conf1`] module"] +pub type COMB_PD_SITE0_UNIT2_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit2_vt2_conf1; +#[doc = "COMB_PD_SITE0_UNIT3_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit3_vt2_conf1`] module"] +pub type COMB_PD_SITE0_UNIT3_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit3_vt2_conf1; +#[doc = "COMB_PD_SITE1_UNIT0_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit0_vt0_conf1`] module"] +pub type COMB_PD_SITE1_UNIT0_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit0_vt0_conf1; +#[doc = "COMB_PD_SITE1_UNIT1_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit1_vt0_conf1`] module"] +pub type COMB_PD_SITE1_UNIT1_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit1_vt0_conf1; +#[doc = "COMB_PD_SITE1_UNIT2_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit2_vt0_conf1`] module"] +pub type COMB_PD_SITE1_UNIT2_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit2_vt0_conf1; +#[doc = "COMB_PD_SITE1_UNIT3_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit3_vt0_conf1`] module"] +pub type COMB_PD_SITE1_UNIT3_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit3_vt0_conf1; +#[doc = "COMB_PD_SITE1_UNIT0_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit0_vt1_conf1`] module"] +pub type COMB_PD_SITE1_UNIT0_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit0_vt1_conf1; +#[doc = "COMB_PD_SITE1_UNIT1_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit1_vt1_conf1`] module"] +pub type COMB_PD_SITE1_UNIT1_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit1_vt1_conf1; +#[doc = "COMB_PD_SITE1_UNIT2_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit2_vt1_conf1`] module"] +pub type COMB_PD_SITE1_UNIT2_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit2_vt1_conf1; +#[doc = "COMB_PD_SITE1_UNIT3_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit3_vt1_conf1`] module"] +pub type COMB_PD_SITE1_UNIT3_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit3_vt1_conf1; +#[doc = "COMB_PD_SITE1_UNIT0_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit0_vt2_conf1`] module"] +pub type COMB_PD_SITE1_UNIT0_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit0_vt2_conf1; +#[doc = "COMB_PD_SITE1_UNIT1_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit1_vt2_conf1`] module"] +pub type COMB_PD_SITE1_UNIT1_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit1_vt2_conf1; +#[doc = "COMB_PD_SITE1_UNIT2_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit2_vt2_conf1`] module"] +pub type COMB_PD_SITE1_UNIT2_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit2_vt2_conf1; +#[doc = "COMB_PD_SITE1_UNIT3_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit3_vt2_conf1`] module"] +pub type COMB_PD_SITE1_UNIT3_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit3_vt2_conf1; +#[doc = "COMB_PD_SITE2_UNIT0_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit0_vt0_conf1`] module"] +pub type COMB_PD_SITE2_UNIT0_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit0_vt0_conf1; +#[doc = "COMB_PD_SITE2_UNIT1_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit1_vt0_conf1`] module"] +pub type COMB_PD_SITE2_UNIT1_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit1_vt0_conf1; +#[doc = "COMB_PD_SITE2_UNIT2_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit2_vt0_conf1`] module"] +pub type COMB_PD_SITE2_UNIT2_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit2_vt0_conf1; +#[doc = "COMB_PD_SITE2_UNIT3_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit3_vt0_conf1`] module"] +pub type COMB_PD_SITE2_UNIT3_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit3_vt0_conf1; +#[doc = "COMB_PD_SITE2_UNIT0_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit0_vt1_conf1`] module"] +pub type COMB_PD_SITE2_UNIT0_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit0_vt1_conf1; +#[doc = "COMB_PD_SITE2_UNIT1_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit1_vt1_conf1`] module"] +pub type COMB_PD_SITE2_UNIT1_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit1_vt1_conf1; +#[doc = "COMB_PD_SITE2_UNIT2_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit2_vt1_conf1`] module"] +pub type COMB_PD_SITE2_UNIT2_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit2_vt1_conf1; +#[doc = "COMB_PD_SITE2_UNIT3_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit3_vt1_conf1`] module"] +pub type COMB_PD_SITE2_UNIT3_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit3_vt1_conf1; +#[doc = "COMB_PD_SITE2_UNIT0_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit0_vt2_conf1`] module"] +pub type COMB_PD_SITE2_UNIT0_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit0_vt2_conf1; +#[doc = "COMB_PD_SITE2_UNIT1_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit1_vt2_conf1`] module"] +pub type COMB_PD_SITE2_UNIT1_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit1_vt2_conf1; +#[doc = "COMB_PD_SITE2_UNIT2_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit2_vt2_conf1`] module"] +pub type COMB_PD_SITE2_UNIT2_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit2_vt2_conf1; +#[doc = "COMB_PD_SITE2_UNIT3_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit3_vt2_conf1`] module"] +pub type COMB_PD_SITE2_UNIT3_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit3_vt2_conf1; +#[doc = "COMB_PD_SITE3_UNIT0_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit0_vt0_conf1`] module"] +pub type COMB_PD_SITE3_UNIT0_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit0_vt0_conf1; +#[doc = "COMB_PD_SITE3_UNIT1_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit1_vt0_conf1`] module"] +pub type COMB_PD_SITE3_UNIT1_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit1_vt0_conf1; +#[doc = "COMB_PD_SITE3_UNIT2_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit2_vt0_conf1`] module"] +pub type COMB_PD_SITE3_UNIT2_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit2_vt0_conf1; +#[doc = "COMB_PD_SITE3_UNIT3_VT0_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt0_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt0_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit3_vt0_conf1`] module"] +pub type COMB_PD_SITE3_UNIT3_VT0_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit3_vt0_conf1; +#[doc = "COMB_PD_SITE3_UNIT0_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit0_vt1_conf1`] module"] +pub type COMB_PD_SITE3_UNIT0_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit0_vt1_conf1; +#[doc = "COMB_PD_SITE3_UNIT1_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit1_vt1_conf1`] module"] +pub type COMB_PD_SITE3_UNIT1_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit1_vt1_conf1; +#[doc = "COMB_PD_SITE3_UNIT2_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit2_vt1_conf1`] module"] +pub type COMB_PD_SITE3_UNIT2_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit2_vt1_conf1; +#[doc = "COMB_PD_SITE3_UNIT3_VT1_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt1_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt1_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit3_vt1_conf1`] module"] +pub type COMB_PD_SITE3_UNIT3_VT1_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit3_vt1_conf1; +#[doc = "COMB_PD_SITE3_UNIT0_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit0_vt2_conf1`] module"] +pub type COMB_PD_SITE3_UNIT0_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit0_vt2_conf1; +#[doc = "COMB_PD_SITE3_UNIT1_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit1_vt2_conf1`] module"] +pub type COMB_PD_SITE3_UNIT1_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit1_vt2_conf1; +#[doc = "COMB_PD_SITE3_UNIT2_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit2_vt2_conf1`] module"] +pub type COMB_PD_SITE3_UNIT2_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit2_vt2_conf1; +#[doc = "COMB_PD_SITE3_UNIT3_VT2_CONF1 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt2_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt2_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit3_vt2_conf1`] module"] +pub type COMB_PD_SITE3_UNIT3_VT2_CONF1 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit3_vt2_conf1; +#[doc = "COMB_PD_SITE0_UNIT0_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit0_vt0_conf2`] module"] +pub type COMB_PD_SITE0_UNIT0_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit0_vt0_conf2; +#[doc = "COMB_PD_SITE0_UNIT1_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit1_vt0_conf2`] module"] +pub type COMB_PD_SITE0_UNIT1_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit1_vt0_conf2; +#[doc = "COMB_PD_SITE0_UNIT2_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit2_vt0_conf2`] module"] +pub type COMB_PD_SITE0_UNIT2_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit2_vt0_conf2; +#[doc = "COMB_PD_SITE0_UNIT3_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit3_vt0_conf2`] module"] +pub type COMB_PD_SITE0_UNIT3_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit3_vt0_conf2; +#[doc = "COMB_PD_SITE0_UNIT0_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit0_vt1_conf2`] module"] +pub type COMB_PD_SITE0_UNIT0_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit0_vt1_conf2; +#[doc = "COMB_PD_SITE0_UNIT1_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit1_vt1_conf2`] module"] +pub type COMB_PD_SITE0_UNIT1_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit1_vt1_conf2; +#[doc = "COMB_PD_SITE0_UNIT2_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit2_vt1_conf2`] module"] +pub type COMB_PD_SITE0_UNIT2_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit2_vt1_conf2; +#[doc = "COMB_PD_SITE0_UNIT3_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit3_vt1_conf2`] module"] +pub type COMB_PD_SITE0_UNIT3_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit3_vt1_conf2; +#[doc = "COMB_PD_SITE0_UNIT0_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit0_vt2_conf2`] module"] +pub type COMB_PD_SITE0_UNIT0_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit0_vt2_conf2; +#[doc = "COMB_PD_SITE0_UNIT1_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit1_vt2_conf2`] module"] +pub type COMB_PD_SITE0_UNIT1_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit1_vt2_conf2; +#[doc = "COMB_PD_SITE0_UNIT2_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit2_vt2_conf2`] module"] +pub type COMB_PD_SITE0_UNIT2_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit2_vt2_conf2; +#[doc = "COMB_PD_SITE0_UNIT3_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site0_unit3_vt2_conf2`] module"] +pub type COMB_PD_SITE0_UNIT3_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site0_unit3_vt2_conf2; +#[doc = "COMB_PD_SITE1_UNIT0_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit0_vt0_conf2`] module"] +pub type COMB_PD_SITE1_UNIT0_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit0_vt0_conf2; +#[doc = "COMB_PD_SITE1_UNIT1_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit1_vt0_conf2`] module"] +pub type COMB_PD_SITE1_UNIT1_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit1_vt0_conf2; +#[doc = "COMB_PD_SITE1_UNIT2_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit2_vt0_conf2`] module"] +pub type COMB_PD_SITE1_UNIT2_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit2_vt0_conf2; +#[doc = "COMB_PD_SITE1_UNIT3_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit3_vt0_conf2`] module"] +pub type COMB_PD_SITE1_UNIT3_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit3_vt0_conf2; +#[doc = "COMB_PD_SITE1_UNIT0_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit0_vt1_conf2`] module"] +pub type COMB_PD_SITE1_UNIT0_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit0_vt1_conf2; +#[doc = "COMB_PD_SITE1_UNIT1_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit1_vt1_conf2`] module"] +pub type COMB_PD_SITE1_UNIT1_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit1_vt1_conf2; +#[doc = "COMB_PD_SITE1_UNIT2_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit2_vt1_conf2`] module"] +pub type COMB_PD_SITE1_UNIT2_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit2_vt1_conf2; +#[doc = "COMB_PD_SITE1_UNIT3_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit3_vt1_conf2`] module"] +pub type COMB_PD_SITE1_UNIT3_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit3_vt1_conf2; +#[doc = "COMB_PD_SITE1_UNIT0_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit0_vt2_conf2`] module"] +pub type COMB_PD_SITE1_UNIT0_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit0_vt2_conf2; +#[doc = "COMB_PD_SITE1_UNIT1_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit1_vt2_conf2`] module"] +pub type COMB_PD_SITE1_UNIT1_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit1_vt2_conf2; +#[doc = "COMB_PD_SITE1_UNIT2_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit2_vt2_conf2`] module"] +pub type COMB_PD_SITE1_UNIT2_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit2_vt2_conf2; +#[doc = "COMB_PD_SITE1_UNIT3_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site1_unit3_vt2_conf2`] module"] +pub type COMB_PD_SITE1_UNIT3_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site1_unit3_vt2_conf2; +#[doc = "COMB_PD_SITE2_UNIT0_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit0_vt0_conf2`] module"] +pub type COMB_PD_SITE2_UNIT0_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit0_vt0_conf2; +#[doc = "COMB_PD_SITE2_UNIT1_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit1_vt0_conf2`] module"] +pub type COMB_PD_SITE2_UNIT1_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit1_vt0_conf2; +#[doc = "COMB_PD_SITE2_UNIT2_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit2_vt0_conf2`] module"] +pub type COMB_PD_SITE2_UNIT2_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit2_vt0_conf2; +#[doc = "COMB_PD_SITE2_UNIT3_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit3_vt0_conf2`] module"] +pub type COMB_PD_SITE2_UNIT3_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit3_vt0_conf2; +#[doc = "COMB_PD_SITE2_UNIT0_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit0_vt1_conf2`] module"] +pub type COMB_PD_SITE2_UNIT0_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit0_vt1_conf2; +#[doc = "COMB_PD_SITE2_UNIT1_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit1_vt1_conf2`] module"] +pub type COMB_PD_SITE2_UNIT1_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit1_vt1_conf2; +#[doc = "COMB_PD_SITE2_UNIT2_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit2_vt1_conf2`] module"] +pub type COMB_PD_SITE2_UNIT2_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit2_vt1_conf2; +#[doc = "COMB_PD_SITE2_UNIT3_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit3_vt1_conf2`] module"] +pub type COMB_PD_SITE2_UNIT3_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit3_vt1_conf2; +#[doc = "COMB_PD_SITE2_UNIT0_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit0_vt2_conf2`] module"] +pub type COMB_PD_SITE2_UNIT0_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit0_vt2_conf2; +#[doc = "COMB_PD_SITE2_UNIT1_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit1_vt2_conf2`] module"] +pub type COMB_PD_SITE2_UNIT1_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit1_vt2_conf2; +#[doc = "COMB_PD_SITE2_UNIT2_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit2_vt2_conf2`] module"] +pub type COMB_PD_SITE2_UNIT2_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit2_vt2_conf2; +#[doc = "COMB_PD_SITE2_UNIT3_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site2_unit3_vt2_conf2`] module"] +pub type COMB_PD_SITE2_UNIT3_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site2_unit3_vt2_conf2; +#[doc = "COMB_PD_SITE3_UNIT0_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit0_vt0_conf2`] module"] +pub type COMB_PD_SITE3_UNIT0_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit0_vt0_conf2; +#[doc = "COMB_PD_SITE3_UNIT1_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit1_vt0_conf2`] module"] +pub type COMB_PD_SITE3_UNIT1_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit1_vt0_conf2; +#[doc = "COMB_PD_SITE3_UNIT2_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit2_vt0_conf2`] module"] +pub type COMB_PD_SITE3_UNIT2_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit2_vt0_conf2; +#[doc = "COMB_PD_SITE3_UNIT3_VT0_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt0_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt0_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit3_vt0_conf2`] module"] +pub type COMB_PD_SITE3_UNIT3_VT0_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit3_vt0_conf2; +#[doc = "COMB_PD_SITE3_UNIT0_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit0_vt1_conf2`] module"] +pub type COMB_PD_SITE3_UNIT0_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit0_vt1_conf2; +#[doc = "COMB_PD_SITE3_UNIT1_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit1_vt1_conf2`] module"] +pub type COMB_PD_SITE3_UNIT1_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit1_vt1_conf2; +#[doc = "COMB_PD_SITE3_UNIT2_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit2_vt1_conf2`] module"] +pub type COMB_PD_SITE3_UNIT2_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit2_vt1_conf2; +#[doc = "COMB_PD_SITE3_UNIT3_VT1_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt1_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt1_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit3_vt1_conf2`] module"] +pub type COMB_PD_SITE3_UNIT3_VT1_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit3_vt1_conf2; +#[doc = "COMB_PD_SITE3_UNIT0_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit0_vt2_conf2`] module"] +pub type COMB_PD_SITE3_UNIT0_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit0_vt2_conf2; +#[doc = "COMB_PD_SITE3_UNIT1_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit1_vt2_conf2`] module"] +pub type COMB_PD_SITE3_UNIT1_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit1_vt2_conf2; +#[doc = "COMB_PD_SITE3_UNIT2_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit2_vt2_conf2`] module"] +pub type COMB_PD_SITE3_UNIT2_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit2_vt2_conf2; +#[doc = "COMB_PD_SITE3_UNIT3_VT2_CONF2 (rw) register accessor: needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt2_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt2_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comb_pd_site3_unit3_vt2_conf2`] module"] +pub type COMB_PD_SITE3_UNIT3_VT2_CONF2 = + crate::Reg; +#[doc = "needs desc"] +pub mod comb_pd_site3_unit3_vt2_conf2; +#[doc = "VALUE_UPDATE (rw) register accessor: needs field desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value_update::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value_update::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value_update`] module"] +pub type VALUE_UPDATE = crate::Reg; +#[doc = "needs field desc"] +pub mod value_update; +#[doc = "DATE (rw) register accessor: version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "version register"] +pub mod date; diff --git a/esp32p4/src/pvt/clk_cfg.rs b/esp32p4/src/pvt/clk_cfg.rs new file mode 100644 index 0000000000..325db2f9b8 --- /dev/null +++ b/esp32p4/src/pvt/clk_cfg.rs @@ -0,0 +1,101 @@ +#[doc = "Register `CLK_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_CLK_DIV_NUM` reader - needs field desc"] +pub type PUMP_CLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `PUMP_CLK_DIV_NUM` writer - needs field desc"] +pub type PUMP_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `MONITOR_CLK_PVT_EN` reader - needs field desc"] +pub type MONITOR_CLK_PVT_EN_R = crate::BitReader; +#[doc = "Field `MONITOR_CLK_PVT_EN` writer - needs field desc"] +pub type MONITOR_CLK_PVT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SEL` reader - select pvt clk"] +pub type CLK_SEL_R = crate::BitReader; +#[doc = "Field `CLK_SEL` writer - select pvt clk"] +pub type CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - needs field desc"] + #[inline(always)] + pub fn pump_clk_div_num(&self) -> PUMP_CLK_DIV_NUM_R { + PUMP_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - needs field desc"] + #[inline(always)] + pub fn monitor_clk_pvt_en(&self) -> MONITOR_CLK_PVT_EN_R { + MONITOR_CLK_PVT_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 31 - select pvt clk"] + #[inline(always)] + pub fn clk_sel(&self) -> CLK_SEL_R { + CLK_SEL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_CFG") + .field( + "pump_clk_div_num", + &format_args!("{}", self.pump_clk_div_num().bits()), + ) + .field( + "monitor_clk_pvt_en", + &format_args!("{}", self.monitor_clk_pvt_en().bit()), + ) + .field("clk_sel", &format_args!("{}", self.clk_sel().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn pump_clk_div_num(&mut self) -> PUMP_CLK_DIV_NUM_W { + PUMP_CLK_DIV_NUM_W::new(self, 0) + } + #[doc = "Bit 8 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_clk_pvt_en(&mut self) -> MONITOR_CLK_PVT_EN_W { + MONITOR_CLK_PVT_EN_W::new(self, 8) + } + #[doc = "Bit 31 - select pvt clk"] + #[inline(always)] + #[must_use] + pub fn clk_sel(&mut self) -> CLK_SEL_W { + CLK_SEL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "configure pvt clk\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_CFG_SPEC; +impl crate::RegisterSpec for CLK_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_cfg::R`](R) reader structure"] +impl crate::Readable for CLK_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_cfg::W`](W) writer structure"] +impl crate::Writable for CLK_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_CFG to value 0"] +impl crate::Resettable for CLK_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf1.rs new file mode 100644 index 0000000000..82450ebad4 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE0_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE0_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE0_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE0_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE0_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE0_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE0_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE0_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE0_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE0_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE0_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE0_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site0_unit0(&self) -> MONITOR_EN_VT0_PD_SITE0_UNIT0_R { + MONITOR_EN_VT0_PD_SITE0_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site0_unit0(&self) -> DELAY_LIMIT_VT0_PD_SITE0_UNIT0_R { + DELAY_LIMIT_VT0_PD_SITE0_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site0_unit0(&self) -> DELAY_NUM_O_VT0_PD_SITE0_UNIT0_R { + DELAY_NUM_O_VT0_PD_SITE0_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site0_unit0(&self) -> TIMING_ERR_VT0_PD_SITE0_UNIT0_R { + TIMING_ERR_VT0_PD_SITE0_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT0_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site0_unit0", + &format_args!("{}", self.monitor_en_vt0_pd_site0_unit0().bit()), + ) + .field( + "delay_limit_vt0_pd_site0_unit0", + &format_args!("{}", self.delay_limit_vt0_pd_site0_unit0().bits()), + ) + .field( + "delay_num_o_vt0_pd_site0_unit0", + &format_args!("{}", self.delay_num_o_vt0_pd_site0_unit0().bits()), + ) + .field( + "timing_err_vt0_pd_site0_unit0", + &format_args!("{}", self.timing_err_vt0_pd_site0_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site0_unit0( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE0_UNIT0_W { + MONITOR_EN_VT0_PD_SITE0_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site0_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site0_unit0( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE0_UNIT0_W { + DELAY_LIMIT_VT0_PD_SITE0_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT0_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT0_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit0_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT0_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit0_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT0_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT0_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT0_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf2.rs new file mode 100644 index 0000000000..3c6ecf6bd1 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE0_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE0_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site0_unit0(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_R { + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site0_unit0(&self) -> DELAY_OVF_VT0_PD_SITE0_UNIT0_R { + DELAY_OVF_VT0_PD_SITE0_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site0_unit0(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_R { + TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT0_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site0_unit0", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site0_unit0().bits()), + ) + .field( + "delay_ovf_vt0_pd_site0_unit0", + &format_args!("{}", self.delay_ovf_vt0_pd_site0_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site0_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site0_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site0_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_W { + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT0_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT0_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit0_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT0_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit0_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT0_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT0_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT0_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf1.rs new file mode 100644 index 0000000000..a76108ab4a --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE0_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE0_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE0_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE0_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE0_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE0_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE0_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE0_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE0_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE0_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE0_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE0_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site0_unit0(&self) -> MONITOR_EN_VT1_PD_SITE0_UNIT0_R { + MONITOR_EN_VT1_PD_SITE0_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site0_unit0(&self) -> DELAY_LIMIT_VT1_PD_SITE0_UNIT0_R { + DELAY_LIMIT_VT1_PD_SITE0_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site0_unit0(&self) -> DELAY_NUM_O_VT1_PD_SITE0_UNIT0_R { + DELAY_NUM_O_VT1_PD_SITE0_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site0_unit0(&self) -> TIMING_ERR_VT1_PD_SITE0_UNIT0_R { + TIMING_ERR_VT1_PD_SITE0_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT0_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site0_unit0", + &format_args!("{}", self.monitor_en_vt1_pd_site0_unit0().bit()), + ) + .field( + "delay_limit_vt1_pd_site0_unit0", + &format_args!("{}", self.delay_limit_vt1_pd_site0_unit0().bits()), + ) + .field( + "delay_num_o_vt1_pd_site0_unit0", + &format_args!("{}", self.delay_num_o_vt1_pd_site0_unit0().bits()), + ) + .field( + "timing_err_vt1_pd_site0_unit0", + &format_args!("{}", self.timing_err_vt1_pd_site0_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site0_unit0( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE0_UNIT0_W { + MONITOR_EN_VT1_PD_SITE0_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site0_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site0_unit0( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE0_UNIT0_W { + DELAY_LIMIT_VT1_PD_SITE0_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT0_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT0_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit0_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT0_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit0_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT0_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT0_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT0_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf2.rs new file mode 100644 index 0000000000..a3c8c21f65 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE0_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE0_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site0_unit0(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_R { + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site0_unit0(&self) -> DELAY_OVF_VT1_PD_SITE0_UNIT0_R { + DELAY_OVF_VT1_PD_SITE0_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site0_unit0(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_R { + TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT0_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site0_unit0", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site0_unit0().bits()), + ) + .field( + "delay_ovf_vt1_pd_site0_unit0", + &format_args!("{}", self.delay_ovf_vt1_pd_site0_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site0_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site0_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site0_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_W { + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT0_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT0_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit0_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT0_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit0_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT0_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT0_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT0_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf1.rs new file mode 100644 index 0000000000..eaaded5527 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE0_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE0_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE0_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE0_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE0_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE0_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE0_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE0_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE0_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE0_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE0_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE0_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site0_unit0(&self) -> MONITOR_EN_VT2_PD_SITE0_UNIT0_R { + MONITOR_EN_VT2_PD_SITE0_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site0_unit0(&self) -> DELAY_LIMIT_VT2_PD_SITE0_UNIT0_R { + DELAY_LIMIT_VT2_PD_SITE0_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site0_unit0(&self) -> DELAY_NUM_O_VT2_PD_SITE0_UNIT0_R { + DELAY_NUM_O_VT2_PD_SITE0_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site0_unit0(&self) -> TIMING_ERR_VT2_PD_SITE0_UNIT0_R { + TIMING_ERR_VT2_PD_SITE0_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT0_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site0_unit0", + &format_args!("{}", self.monitor_en_vt2_pd_site0_unit0().bit()), + ) + .field( + "delay_limit_vt2_pd_site0_unit0", + &format_args!("{}", self.delay_limit_vt2_pd_site0_unit0().bits()), + ) + .field( + "delay_num_o_vt2_pd_site0_unit0", + &format_args!("{}", self.delay_num_o_vt2_pd_site0_unit0().bits()), + ) + .field( + "timing_err_vt2_pd_site0_unit0", + &format_args!("{}", self.timing_err_vt2_pd_site0_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site0_unit0( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE0_UNIT0_W { + MONITOR_EN_VT2_PD_SITE0_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site0_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site0_unit0( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE0_UNIT0_W { + DELAY_LIMIT_VT2_PD_SITE0_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT0_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT0_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit0_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT0_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit0_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT0_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT0_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT0_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf2.rs new file mode 100644 index 0000000000..8c92dedd57 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT0_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE0_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE0_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site0_unit0(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_R { + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site0_unit0(&self) -> DELAY_OVF_VT2_PD_SITE0_UNIT0_R { + DELAY_OVF_VT2_PD_SITE0_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site0_unit0(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_R { + TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT0_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site0_unit0", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site0_unit0().bits()), + ) + .field( + "delay_ovf_vt2_pd_site0_unit0", + &format_args!("{}", self.delay_ovf_vt2_pd_site0_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site0_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site0_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site0_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_W { + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit0_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit0_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT0_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT0_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit0_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT0_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit0_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT0_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT0_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT0_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf1.rs new file mode 100644 index 0000000000..a0c9c28a89 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE0_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE0_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE0_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE0_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE0_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE0_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE0_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE0_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE0_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE0_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE0_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE0_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site0_unit1(&self) -> MONITOR_EN_VT0_PD_SITE0_UNIT1_R { + MONITOR_EN_VT0_PD_SITE0_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site0_unit1(&self) -> DELAY_LIMIT_VT0_PD_SITE0_UNIT1_R { + DELAY_LIMIT_VT0_PD_SITE0_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site0_unit1(&self) -> DELAY_NUM_O_VT0_PD_SITE0_UNIT1_R { + DELAY_NUM_O_VT0_PD_SITE0_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site0_unit1(&self) -> TIMING_ERR_VT0_PD_SITE0_UNIT1_R { + TIMING_ERR_VT0_PD_SITE0_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT1_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site0_unit1", + &format_args!("{}", self.monitor_en_vt0_pd_site0_unit1().bit()), + ) + .field( + "delay_limit_vt0_pd_site0_unit1", + &format_args!("{}", self.delay_limit_vt0_pd_site0_unit1().bits()), + ) + .field( + "delay_num_o_vt0_pd_site0_unit1", + &format_args!("{}", self.delay_num_o_vt0_pd_site0_unit1().bits()), + ) + .field( + "timing_err_vt0_pd_site0_unit1", + &format_args!("{}", self.timing_err_vt0_pd_site0_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site0_unit1( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE0_UNIT1_W { + MONITOR_EN_VT0_PD_SITE0_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site0_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site0_unit1( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE0_UNIT1_W { + DELAY_LIMIT_VT0_PD_SITE0_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT1_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT1_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit1_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT1_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit1_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT1_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT1_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT1_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf2.rs new file mode 100644 index 0000000000..85ff94b594 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE0_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE0_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site0_unit1(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_R { + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site0_unit1(&self) -> DELAY_OVF_VT0_PD_SITE0_UNIT1_R { + DELAY_OVF_VT0_PD_SITE0_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site0_unit1(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_R { + TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT1_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site0_unit1", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site0_unit1().bits()), + ) + .field( + "delay_ovf_vt0_pd_site0_unit1", + &format_args!("{}", self.delay_ovf_vt0_pd_site0_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site0_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site0_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site0_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_W { + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT1_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT1_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit1_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT1_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit1_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT1_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT1_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT1_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf1.rs new file mode 100644 index 0000000000..19ab23b6cb --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE0_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE0_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE0_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE0_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE0_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE0_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE0_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE0_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE0_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE0_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE0_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE0_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site0_unit1(&self) -> MONITOR_EN_VT1_PD_SITE0_UNIT1_R { + MONITOR_EN_VT1_PD_SITE0_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site0_unit1(&self) -> DELAY_LIMIT_VT1_PD_SITE0_UNIT1_R { + DELAY_LIMIT_VT1_PD_SITE0_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site0_unit1(&self) -> DELAY_NUM_O_VT1_PD_SITE0_UNIT1_R { + DELAY_NUM_O_VT1_PD_SITE0_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site0_unit1(&self) -> TIMING_ERR_VT1_PD_SITE0_UNIT1_R { + TIMING_ERR_VT1_PD_SITE0_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT1_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site0_unit1", + &format_args!("{}", self.monitor_en_vt1_pd_site0_unit1().bit()), + ) + .field( + "delay_limit_vt1_pd_site0_unit1", + &format_args!("{}", self.delay_limit_vt1_pd_site0_unit1().bits()), + ) + .field( + "delay_num_o_vt1_pd_site0_unit1", + &format_args!("{}", self.delay_num_o_vt1_pd_site0_unit1().bits()), + ) + .field( + "timing_err_vt1_pd_site0_unit1", + &format_args!("{}", self.timing_err_vt1_pd_site0_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site0_unit1( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE0_UNIT1_W { + MONITOR_EN_VT1_PD_SITE0_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site0_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site0_unit1( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE0_UNIT1_W { + DELAY_LIMIT_VT1_PD_SITE0_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT1_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT1_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit1_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT1_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit1_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT1_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT1_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT1_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf2.rs new file mode 100644 index 0000000000..443d8f76de --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE0_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE0_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site0_unit1(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_R { + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site0_unit1(&self) -> DELAY_OVF_VT1_PD_SITE0_UNIT1_R { + DELAY_OVF_VT1_PD_SITE0_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site0_unit1(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_R { + TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT1_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site0_unit1", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site0_unit1().bits()), + ) + .field( + "delay_ovf_vt1_pd_site0_unit1", + &format_args!("{}", self.delay_ovf_vt1_pd_site0_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site0_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site0_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site0_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_W { + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT1_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT1_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit1_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT1_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit1_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT1_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT1_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT1_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf1.rs new file mode 100644 index 0000000000..ac7d1f2477 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE0_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE0_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE0_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE0_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE0_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE0_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE0_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE0_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE0_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE0_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE0_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE0_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site0_unit1(&self) -> MONITOR_EN_VT2_PD_SITE0_UNIT1_R { + MONITOR_EN_VT2_PD_SITE0_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site0_unit1(&self) -> DELAY_LIMIT_VT2_PD_SITE0_UNIT1_R { + DELAY_LIMIT_VT2_PD_SITE0_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site0_unit1(&self) -> DELAY_NUM_O_VT2_PD_SITE0_UNIT1_R { + DELAY_NUM_O_VT2_PD_SITE0_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site0_unit1(&self) -> TIMING_ERR_VT2_PD_SITE0_UNIT1_R { + TIMING_ERR_VT2_PD_SITE0_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT1_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site0_unit1", + &format_args!("{}", self.monitor_en_vt2_pd_site0_unit1().bit()), + ) + .field( + "delay_limit_vt2_pd_site0_unit1", + &format_args!("{}", self.delay_limit_vt2_pd_site0_unit1().bits()), + ) + .field( + "delay_num_o_vt2_pd_site0_unit1", + &format_args!("{}", self.delay_num_o_vt2_pd_site0_unit1().bits()), + ) + .field( + "timing_err_vt2_pd_site0_unit1", + &format_args!("{}", self.timing_err_vt2_pd_site0_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site0_unit1( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE0_UNIT1_W { + MONITOR_EN_VT2_PD_SITE0_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site0_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site0_unit1( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE0_UNIT1_W { + DELAY_LIMIT_VT2_PD_SITE0_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT1_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT1_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit1_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT1_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit1_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT1_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT1_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT1_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf2.rs new file mode 100644 index 0000000000..ad9d0568a3 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT1_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE0_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE0_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site0_unit1(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_R { + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site0_unit1(&self) -> DELAY_OVF_VT2_PD_SITE0_UNIT1_R { + DELAY_OVF_VT2_PD_SITE0_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site0_unit1(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_R { + TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT1_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site0_unit1", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site0_unit1().bits()), + ) + .field( + "delay_ovf_vt2_pd_site0_unit1", + &format_args!("{}", self.delay_ovf_vt2_pd_site0_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site0_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site0_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site0_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_W { + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit1_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit1_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT1_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT1_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit1_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT1_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit1_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT1_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT1_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT1_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf1.rs new file mode 100644 index 0000000000..66bd7d9687 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE0_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE0_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE0_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE0_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE0_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE0_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE0_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE0_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE0_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE0_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE0_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE0_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site0_unit2(&self) -> MONITOR_EN_VT0_PD_SITE0_UNIT2_R { + MONITOR_EN_VT0_PD_SITE0_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site0_unit2(&self) -> DELAY_LIMIT_VT0_PD_SITE0_UNIT2_R { + DELAY_LIMIT_VT0_PD_SITE0_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site0_unit2(&self) -> DELAY_NUM_O_VT0_PD_SITE0_UNIT2_R { + DELAY_NUM_O_VT0_PD_SITE0_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site0_unit2(&self) -> TIMING_ERR_VT0_PD_SITE0_UNIT2_R { + TIMING_ERR_VT0_PD_SITE0_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT2_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site0_unit2", + &format_args!("{}", self.monitor_en_vt0_pd_site0_unit2().bit()), + ) + .field( + "delay_limit_vt0_pd_site0_unit2", + &format_args!("{}", self.delay_limit_vt0_pd_site0_unit2().bits()), + ) + .field( + "delay_num_o_vt0_pd_site0_unit2", + &format_args!("{}", self.delay_num_o_vt0_pd_site0_unit2().bits()), + ) + .field( + "timing_err_vt0_pd_site0_unit2", + &format_args!("{}", self.timing_err_vt0_pd_site0_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site0_unit2( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE0_UNIT2_W { + MONITOR_EN_VT0_PD_SITE0_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site0_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site0_unit2( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE0_UNIT2_W { + DELAY_LIMIT_VT0_PD_SITE0_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT2_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT2_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit2_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT2_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit2_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT2_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT2_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT2_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf2.rs new file mode 100644 index 0000000000..3d38622947 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE0_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE0_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site0_unit2(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_R { + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site0_unit2(&self) -> DELAY_OVF_VT0_PD_SITE0_UNIT2_R { + DELAY_OVF_VT0_PD_SITE0_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site0_unit2(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_R { + TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT2_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site0_unit2", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site0_unit2().bits()), + ) + .field( + "delay_ovf_vt0_pd_site0_unit2", + &format_args!("{}", self.delay_ovf_vt0_pd_site0_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site0_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site0_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site0_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_W { + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT2_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT2_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit2_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT2_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit2_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT2_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT2_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT2_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf1.rs new file mode 100644 index 0000000000..d89d986c67 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE0_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE0_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE0_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE0_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE0_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE0_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE0_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE0_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE0_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE0_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE0_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE0_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site0_unit2(&self) -> MONITOR_EN_VT1_PD_SITE0_UNIT2_R { + MONITOR_EN_VT1_PD_SITE0_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site0_unit2(&self) -> DELAY_LIMIT_VT1_PD_SITE0_UNIT2_R { + DELAY_LIMIT_VT1_PD_SITE0_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site0_unit2(&self) -> DELAY_NUM_O_VT1_PD_SITE0_UNIT2_R { + DELAY_NUM_O_VT1_PD_SITE0_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site0_unit2(&self) -> TIMING_ERR_VT1_PD_SITE0_UNIT2_R { + TIMING_ERR_VT1_PD_SITE0_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT2_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site0_unit2", + &format_args!("{}", self.monitor_en_vt1_pd_site0_unit2().bit()), + ) + .field( + "delay_limit_vt1_pd_site0_unit2", + &format_args!("{}", self.delay_limit_vt1_pd_site0_unit2().bits()), + ) + .field( + "delay_num_o_vt1_pd_site0_unit2", + &format_args!("{}", self.delay_num_o_vt1_pd_site0_unit2().bits()), + ) + .field( + "timing_err_vt1_pd_site0_unit2", + &format_args!("{}", self.timing_err_vt1_pd_site0_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site0_unit2( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE0_UNIT2_W { + MONITOR_EN_VT1_PD_SITE0_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site0_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site0_unit2( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE0_UNIT2_W { + DELAY_LIMIT_VT1_PD_SITE0_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT2_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT2_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit2_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT2_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit2_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT2_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT2_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT2_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf2.rs new file mode 100644 index 0000000000..030adc6009 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE0_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE0_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site0_unit2(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_R { + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site0_unit2(&self) -> DELAY_OVF_VT1_PD_SITE0_UNIT2_R { + DELAY_OVF_VT1_PD_SITE0_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site0_unit2(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_R { + TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT2_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site0_unit2", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site0_unit2().bits()), + ) + .field( + "delay_ovf_vt1_pd_site0_unit2", + &format_args!("{}", self.delay_ovf_vt1_pd_site0_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site0_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site0_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site0_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_W { + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT2_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT2_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit2_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT2_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit2_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT2_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT2_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT2_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf1.rs new file mode 100644 index 0000000000..5c01dc836d --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE0_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE0_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE0_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE0_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE0_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE0_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE0_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE0_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE0_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE0_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE0_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE0_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site0_unit2(&self) -> MONITOR_EN_VT2_PD_SITE0_UNIT2_R { + MONITOR_EN_VT2_PD_SITE0_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site0_unit2(&self) -> DELAY_LIMIT_VT2_PD_SITE0_UNIT2_R { + DELAY_LIMIT_VT2_PD_SITE0_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site0_unit2(&self) -> DELAY_NUM_O_VT2_PD_SITE0_UNIT2_R { + DELAY_NUM_O_VT2_PD_SITE0_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site0_unit2(&self) -> TIMING_ERR_VT2_PD_SITE0_UNIT2_R { + TIMING_ERR_VT2_PD_SITE0_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT2_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site0_unit2", + &format_args!("{}", self.monitor_en_vt2_pd_site0_unit2().bit()), + ) + .field( + "delay_limit_vt2_pd_site0_unit2", + &format_args!("{}", self.delay_limit_vt2_pd_site0_unit2().bits()), + ) + .field( + "delay_num_o_vt2_pd_site0_unit2", + &format_args!("{}", self.delay_num_o_vt2_pd_site0_unit2().bits()), + ) + .field( + "timing_err_vt2_pd_site0_unit2", + &format_args!("{}", self.timing_err_vt2_pd_site0_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site0_unit2( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE0_UNIT2_W { + MONITOR_EN_VT2_PD_SITE0_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site0_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site0_unit2( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE0_UNIT2_W { + DELAY_LIMIT_VT2_PD_SITE0_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT2_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT2_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit2_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT2_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit2_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT2_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT2_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT2_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf2.rs new file mode 100644 index 0000000000..1b165a4ec3 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT2_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE0_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE0_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site0_unit2(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_R { + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site0_unit2(&self) -> DELAY_OVF_VT2_PD_SITE0_UNIT2_R { + DELAY_OVF_VT2_PD_SITE0_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site0_unit2(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_R { + TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT2_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site0_unit2", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site0_unit2().bits()), + ) + .field( + "delay_ovf_vt2_pd_site0_unit2", + &format_args!("{}", self.delay_ovf_vt2_pd_site0_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site0_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site0_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site0_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_W { + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit2_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit2_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT2_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT2_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit2_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT2_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit2_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT2_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT2_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT2_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf1.rs new file mode 100644 index 0000000000..908eb82443 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE0_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE0_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE0_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE0_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE0_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE0_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE0_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE0_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE0_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE0_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE0_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE0_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site0_unit3(&self) -> MONITOR_EN_VT0_PD_SITE0_UNIT3_R { + MONITOR_EN_VT0_PD_SITE0_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site0_unit3(&self) -> DELAY_LIMIT_VT0_PD_SITE0_UNIT3_R { + DELAY_LIMIT_VT0_PD_SITE0_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site0_unit3(&self) -> DELAY_NUM_O_VT0_PD_SITE0_UNIT3_R { + DELAY_NUM_O_VT0_PD_SITE0_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site0_unit3(&self) -> TIMING_ERR_VT0_PD_SITE0_UNIT3_R { + TIMING_ERR_VT0_PD_SITE0_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT3_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site0_unit3", + &format_args!("{}", self.monitor_en_vt0_pd_site0_unit3().bit()), + ) + .field( + "delay_limit_vt0_pd_site0_unit3", + &format_args!("{}", self.delay_limit_vt0_pd_site0_unit3().bits()), + ) + .field( + "delay_num_o_vt0_pd_site0_unit3", + &format_args!("{}", self.delay_num_o_vt0_pd_site0_unit3().bits()), + ) + .field( + "timing_err_vt0_pd_site0_unit3", + &format_args!("{}", self.timing_err_vt0_pd_site0_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site0_unit3( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE0_UNIT3_W { + MONITOR_EN_VT0_PD_SITE0_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site0_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site0_unit3( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE0_UNIT3_W { + DELAY_LIMIT_VT0_PD_SITE0_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT3_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT3_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit3_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT3_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit3_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT3_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT3_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT3_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf2.rs new file mode 100644 index 0000000000..73c0090a3b --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE0_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE0_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site0_unit3(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_R { + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site0_unit3(&self) -> DELAY_OVF_VT0_PD_SITE0_UNIT3_R { + DELAY_OVF_VT0_PD_SITE0_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site0_unit3(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_R { + TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT3_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site0_unit3", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site0_unit3().bits()), + ) + .field( + "delay_ovf_vt0_pd_site0_unit3", + &format_args!("{}", self.delay_ovf_vt0_pd_site0_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site0_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site0_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site0_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_W { + MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT3_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT3_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit3_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT3_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit3_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT3_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT3_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT3_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf1.rs new file mode 100644 index 0000000000..a620660c96 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE0_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE0_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE0_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE0_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE0_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE0_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE0_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE0_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE0_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE0_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE0_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE0_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site0_unit3(&self) -> MONITOR_EN_VT1_PD_SITE0_UNIT3_R { + MONITOR_EN_VT1_PD_SITE0_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site0_unit3(&self) -> DELAY_LIMIT_VT1_PD_SITE0_UNIT3_R { + DELAY_LIMIT_VT1_PD_SITE0_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site0_unit3(&self) -> DELAY_NUM_O_VT1_PD_SITE0_UNIT3_R { + DELAY_NUM_O_VT1_PD_SITE0_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site0_unit3(&self) -> TIMING_ERR_VT1_PD_SITE0_UNIT3_R { + TIMING_ERR_VT1_PD_SITE0_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT3_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site0_unit3", + &format_args!("{}", self.monitor_en_vt1_pd_site0_unit3().bit()), + ) + .field( + "delay_limit_vt1_pd_site0_unit3", + &format_args!("{}", self.delay_limit_vt1_pd_site0_unit3().bits()), + ) + .field( + "delay_num_o_vt1_pd_site0_unit3", + &format_args!("{}", self.delay_num_o_vt1_pd_site0_unit3().bits()), + ) + .field( + "timing_err_vt1_pd_site0_unit3", + &format_args!("{}", self.timing_err_vt1_pd_site0_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site0_unit3( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE0_UNIT3_W { + MONITOR_EN_VT1_PD_SITE0_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site0_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site0_unit3( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE0_UNIT3_W { + DELAY_LIMIT_VT1_PD_SITE0_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT3_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT3_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit3_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT3_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit3_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT3_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT3_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT3_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf2.rs new file mode 100644 index 0000000000..5136a92a5c --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE0_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE0_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site0_unit3(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_R { + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site0_unit3(&self) -> DELAY_OVF_VT1_PD_SITE0_UNIT3_R { + DELAY_OVF_VT1_PD_SITE0_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site0_unit3(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_R { + TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT3_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site0_unit3", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site0_unit3().bits()), + ) + .field( + "delay_ovf_vt1_pd_site0_unit3", + &format_args!("{}", self.delay_ovf_vt1_pd_site0_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site0_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site0_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site0_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_W { + MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT3_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT3_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit3_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT3_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit3_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT3_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT3_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT3_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf1.rs new file mode 100644 index 0000000000..a86d9eab04 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE0_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE0_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE0_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE0_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE0_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE0_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE0_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE0_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE0_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE0_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE0_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE0_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site0_unit3(&self) -> MONITOR_EN_VT2_PD_SITE0_UNIT3_R { + MONITOR_EN_VT2_PD_SITE0_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site0_unit3(&self) -> DELAY_LIMIT_VT2_PD_SITE0_UNIT3_R { + DELAY_LIMIT_VT2_PD_SITE0_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site0_unit3(&self) -> DELAY_NUM_O_VT2_PD_SITE0_UNIT3_R { + DELAY_NUM_O_VT2_PD_SITE0_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site0_unit3(&self) -> TIMING_ERR_VT2_PD_SITE0_UNIT3_R { + TIMING_ERR_VT2_PD_SITE0_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT3_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site0_unit3", + &format_args!("{}", self.monitor_en_vt2_pd_site0_unit3().bit()), + ) + .field( + "delay_limit_vt2_pd_site0_unit3", + &format_args!("{}", self.delay_limit_vt2_pd_site0_unit3().bits()), + ) + .field( + "delay_num_o_vt2_pd_site0_unit3", + &format_args!("{}", self.delay_num_o_vt2_pd_site0_unit3().bits()), + ) + .field( + "timing_err_vt2_pd_site0_unit3", + &format_args!("{}", self.timing_err_vt2_pd_site0_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site0_unit3( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE0_UNIT3_W { + MONITOR_EN_VT2_PD_SITE0_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site0_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site0_unit3( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE0_UNIT3_W { + DELAY_LIMIT_VT2_PD_SITE0_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT3_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT3_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit3_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT3_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit3_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT3_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT3_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE0_UNIT3_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf2.rs new file mode 100644 index 0000000000..114f1c72c8 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE0_UNIT3_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE0_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE0_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site0_unit3(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_R { + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site0_unit3(&self) -> DELAY_OVF_VT2_PD_SITE0_UNIT3_R { + DELAY_OVF_VT2_PD_SITE0_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site0_unit3(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_R { + TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE0_UNIT3_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site0_unit3", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site0_unit3().bits()), + ) + .field( + "delay_ovf_vt2_pd_site0_unit3", + &format_args!("{}", self.delay_ovf_vt2_pd_site0_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site0_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site0_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site0_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_W { + MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site0_unit3_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site0_unit3_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE0_UNIT3_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE0_UNIT3_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site0_unit3_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE0_UNIT3_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site0_unit3_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE0_UNIT3_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE0_UNIT3_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE0_UNIT3_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf1.rs new file mode 100644 index 0000000000..26ac1c5a6f --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE1_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE1_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE1_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE1_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE1_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE1_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE1_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE1_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE1_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE1_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE1_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE1_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site1_unit0(&self) -> MONITOR_EN_VT0_PD_SITE1_UNIT0_R { + MONITOR_EN_VT0_PD_SITE1_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site1_unit0(&self) -> DELAY_LIMIT_VT0_PD_SITE1_UNIT0_R { + DELAY_LIMIT_VT0_PD_SITE1_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site1_unit0(&self) -> DELAY_NUM_O_VT0_PD_SITE1_UNIT0_R { + DELAY_NUM_O_VT0_PD_SITE1_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site1_unit0(&self) -> TIMING_ERR_VT0_PD_SITE1_UNIT0_R { + TIMING_ERR_VT0_PD_SITE1_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT0_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site1_unit0", + &format_args!("{}", self.monitor_en_vt0_pd_site1_unit0().bit()), + ) + .field( + "delay_limit_vt0_pd_site1_unit0", + &format_args!("{}", self.delay_limit_vt0_pd_site1_unit0().bits()), + ) + .field( + "delay_num_o_vt0_pd_site1_unit0", + &format_args!("{}", self.delay_num_o_vt0_pd_site1_unit0().bits()), + ) + .field( + "timing_err_vt0_pd_site1_unit0", + &format_args!("{}", self.timing_err_vt0_pd_site1_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site1_unit0( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE1_UNIT0_W { + MONITOR_EN_VT0_PD_SITE1_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site1_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site1_unit0( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE1_UNIT0_W { + DELAY_LIMIT_VT0_PD_SITE1_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT0_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT0_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit0_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT0_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit0_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT0_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT0_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT0_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf2.rs new file mode 100644 index 0000000000..c0f10beaef --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE1_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE1_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site1_unit0(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_R { + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site1_unit0(&self) -> DELAY_OVF_VT0_PD_SITE1_UNIT0_R { + DELAY_OVF_VT0_PD_SITE1_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site1_unit0(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_R { + TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT0_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site1_unit0", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site1_unit0().bits()), + ) + .field( + "delay_ovf_vt0_pd_site1_unit0", + &format_args!("{}", self.delay_ovf_vt0_pd_site1_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site1_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site1_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site1_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_W { + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT0_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT0_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit0_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT0_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit0_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT0_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT0_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT0_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf1.rs new file mode 100644 index 0000000000..b15ab1f17c --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE1_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE1_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE1_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE1_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE1_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE1_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE1_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE1_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE1_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE1_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE1_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE1_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site1_unit0(&self) -> MONITOR_EN_VT1_PD_SITE1_UNIT0_R { + MONITOR_EN_VT1_PD_SITE1_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site1_unit0(&self) -> DELAY_LIMIT_VT1_PD_SITE1_UNIT0_R { + DELAY_LIMIT_VT1_PD_SITE1_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site1_unit0(&self) -> DELAY_NUM_O_VT1_PD_SITE1_UNIT0_R { + DELAY_NUM_O_VT1_PD_SITE1_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site1_unit0(&self) -> TIMING_ERR_VT1_PD_SITE1_UNIT0_R { + TIMING_ERR_VT1_PD_SITE1_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT0_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site1_unit0", + &format_args!("{}", self.monitor_en_vt1_pd_site1_unit0().bit()), + ) + .field( + "delay_limit_vt1_pd_site1_unit0", + &format_args!("{}", self.delay_limit_vt1_pd_site1_unit0().bits()), + ) + .field( + "delay_num_o_vt1_pd_site1_unit0", + &format_args!("{}", self.delay_num_o_vt1_pd_site1_unit0().bits()), + ) + .field( + "timing_err_vt1_pd_site1_unit0", + &format_args!("{}", self.timing_err_vt1_pd_site1_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site1_unit0( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE1_UNIT0_W { + MONITOR_EN_VT1_PD_SITE1_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site1_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site1_unit0( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE1_UNIT0_W { + DELAY_LIMIT_VT1_PD_SITE1_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT0_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT0_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit0_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT0_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit0_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT0_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT0_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT0_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf2.rs new file mode 100644 index 0000000000..df92694477 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE1_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE1_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site1_unit0(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_R { + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site1_unit0(&self) -> DELAY_OVF_VT1_PD_SITE1_UNIT0_R { + DELAY_OVF_VT1_PD_SITE1_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site1_unit0(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_R { + TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT0_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site1_unit0", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site1_unit0().bits()), + ) + .field( + "delay_ovf_vt1_pd_site1_unit0", + &format_args!("{}", self.delay_ovf_vt1_pd_site1_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site1_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site1_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site1_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_W { + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT0_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT0_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit0_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT0_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit0_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT0_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT0_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT0_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf1.rs new file mode 100644 index 0000000000..b2c7f18d31 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE1_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE1_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE1_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE1_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE1_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE1_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE1_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE1_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE1_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE1_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE1_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE1_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site1_unit0(&self) -> MONITOR_EN_VT2_PD_SITE1_UNIT0_R { + MONITOR_EN_VT2_PD_SITE1_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site1_unit0(&self) -> DELAY_LIMIT_VT2_PD_SITE1_UNIT0_R { + DELAY_LIMIT_VT2_PD_SITE1_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site1_unit0(&self) -> DELAY_NUM_O_VT2_PD_SITE1_UNIT0_R { + DELAY_NUM_O_VT2_PD_SITE1_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site1_unit0(&self) -> TIMING_ERR_VT2_PD_SITE1_UNIT0_R { + TIMING_ERR_VT2_PD_SITE1_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT0_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site1_unit0", + &format_args!("{}", self.monitor_en_vt2_pd_site1_unit0().bit()), + ) + .field( + "delay_limit_vt2_pd_site1_unit0", + &format_args!("{}", self.delay_limit_vt2_pd_site1_unit0().bits()), + ) + .field( + "delay_num_o_vt2_pd_site1_unit0", + &format_args!("{}", self.delay_num_o_vt2_pd_site1_unit0().bits()), + ) + .field( + "timing_err_vt2_pd_site1_unit0", + &format_args!("{}", self.timing_err_vt2_pd_site1_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site1_unit0( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE1_UNIT0_W { + MONITOR_EN_VT2_PD_SITE1_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site1_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site1_unit0( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE1_UNIT0_W { + DELAY_LIMIT_VT2_PD_SITE1_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT0_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT0_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit0_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT0_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit0_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT0_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT0_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT0_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf2.rs new file mode 100644 index 0000000000..4d57d1c569 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT0_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE1_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE1_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site1_unit0(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_R { + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site1_unit0(&self) -> DELAY_OVF_VT2_PD_SITE1_UNIT0_R { + DELAY_OVF_VT2_PD_SITE1_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site1_unit0(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_R { + TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT0_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site1_unit0", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site1_unit0().bits()), + ) + .field( + "delay_ovf_vt2_pd_site1_unit0", + &format_args!("{}", self.delay_ovf_vt2_pd_site1_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site1_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site1_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site1_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_W { + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit0_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit0_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT0_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT0_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit0_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT0_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit0_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT0_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT0_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT0_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf1.rs new file mode 100644 index 0000000000..b73b6f66b1 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE1_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE1_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE1_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE1_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE1_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE1_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE1_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE1_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE1_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE1_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE1_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE1_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site1_unit1(&self) -> MONITOR_EN_VT0_PD_SITE1_UNIT1_R { + MONITOR_EN_VT0_PD_SITE1_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site1_unit1(&self) -> DELAY_LIMIT_VT0_PD_SITE1_UNIT1_R { + DELAY_LIMIT_VT0_PD_SITE1_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site1_unit1(&self) -> DELAY_NUM_O_VT0_PD_SITE1_UNIT1_R { + DELAY_NUM_O_VT0_PD_SITE1_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site1_unit1(&self) -> TIMING_ERR_VT0_PD_SITE1_UNIT1_R { + TIMING_ERR_VT0_PD_SITE1_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT1_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site1_unit1", + &format_args!("{}", self.monitor_en_vt0_pd_site1_unit1().bit()), + ) + .field( + "delay_limit_vt0_pd_site1_unit1", + &format_args!("{}", self.delay_limit_vt0_pd_site1_unit1().bits()), + ) + .field( + "delay_num_o_vt0_pd_site1_unit1", + &format_args!("{}", self.delay_num_o_vt0_pd_site1_unit1().bits()), + ) + .field( + "timing_err_vt0_pd_site1_unit1", + &format_args!("{}", self.timing_err_vt0_pd_site1_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site1_unit1( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE1_UNIT1_W { + MONITOR_EN_VT0_PD_SITE1_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site1_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site1_unit1( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE1_UNIT1_W { + DELAY_LIMIT_VT0_PD_SITE1_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT1_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT1_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit1_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT1_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit1_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT1_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT1_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT1_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf2.rs new file mode 100644 index 0000000000..0cedb2c417 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE1_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE1_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site1_unit1(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_R { + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site1_unit1(&self) -> DELAY_OVF_VT0_PD_SITE1_UNIT1_R { + DELAY_OVF_VT0_PD_SITE1_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site1_unit1(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_R { + TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT1_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site1_unit1", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site1_unit1().bits()), + ) + .field( + "delay_ovf_vt0_pd_site1_unit1", + &format_args!("{}", self.delay_ovf_vt0_pd_site1_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site1_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site1_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site1_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_W { + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT1_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT1_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit1_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT1_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit1_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT1_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT1_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT1_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf1.rs new file mode 100644 index 0000000000..2c1d10cf0a --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE1_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE1_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE1_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE1_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE1_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE1_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE1_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE1_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE1_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE1_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE1_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE1_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site1_unit1(&self) -> MONITOR_EN_VT1_PD_SITE1_UNIT1_R { + MONITOR_EN_VT1_PD_SITE1_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site1_unit1(&self) -> DELAY_LIMIT_VT1_PD_SITE1_UNIT1_R { + DELAY_LIMIT_VT1_PD_SITE1_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site1_unit1(&self) -> DELAY_NUM_O_VT1_PD_SITE1_UNIT1_R { + DELAY_NUM_O_VT1_PD_SITE1_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site1_unit1(&self) -> TIMING_ERR_VT1_PD_SITE1_UNIT1_R { + TIMING_ERR_VT1_PD_SITE1_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT1_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site1_unit1", + &format_args!("{}", self.monitor_en_vt1_pd_site1_unit1().bit()), + ) + .field( + "delay_limit_vt1_pd_site1_unit1", + &format_args!("{}", self.delay_limit_vt1_pd_site1_unit1().bits()), + ) + .field( + "delay_num_o_vt1_pd_site1_unit1", + &format_args!("{}", self.delay_num_o_vt1_pd_site1_unit1().bits()), + ) + .field( + "timing_err_vt1_pd_site1_unit1", + &format_args!("{}", self.timing_err_vt1_pd_site1_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site1_unit1( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE1_UNIT1_W { + MONITOR_EN_VT1_PD_SITE1_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site1_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site1_unit1( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE1_UNIT1_W { + DELAY_LIMIT_VT1_PD_SITE1_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT1_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT1_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit1_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT1_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit1_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT1_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT1_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT1_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf2.rs new file mode 100644 index 0000000000..1647f5dfa6 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE1_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE1_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site1_unit1(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_R { + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site1_unit1(&self) -> DELAY_OVF_VT1_PD_SITE1_UNIT1_R { + DELAY_OVF_VT1_PD_SITE1_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site1_unit1(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_R { + TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT1_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site1_unit1", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site1_unit1().bits()), + ) + .field( + "delay_ovf_vt1_pd_site1_unit1", + &format_args!("{}", self.delay_ovf_vt1_pd_site1_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site1_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site1_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site1_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_W { + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT1_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT1_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit1_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT1_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit1_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT1_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT1_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT1_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf1.rs new file mode 100644 index 0000000000..e8b22c53c4 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE1_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE1_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE1_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE1_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE1_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE1_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE1_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE1_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE1_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE1_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE1_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE1_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site1_unit1(&self) -> MONITOR_EN_VT2_PD_SITE1_UNIT1_R { + MONITOR_EN_VT2_PD_SITE1_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site1_unit1(&self) -> DELAY_LIMIT_VT2_PD_SITE1_UNIT1_R { + DELAY_LIMIT_VT2_PD_SITE1_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site1_unit1(&self) -> DELAY_NUM_O_VT2_PD_SITE1_UNIT1_R { + DELAY_NUM_O_VT2_PD_SITE1_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site1_unit1(&self) -> TIMING_ERR_VT2_PD_SITE1_UNIT1_R { + TIMING_ERR_VT2_PD_SITE1_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT1_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site1_unit1", + &format_args!("{}", self.monitor_en_vt2_pd_site1_unit1().bit()), + ) + .field( + "delay_limit_vt2_pd_site1_unit1", + &format_args!("{}", self.delay_limit_vt2_pd_site1_unit1().bits()), + ) + .field( + "delay_num_o_vt2_pd_site1_unit1", + &format_args!("{}", self.delay_num_o_vt2_pd_site1_unit1().bits()), + ) + .field( + "timing_err_vt2_pd_site1_unit1", + &format_args!("{}", self.timing_err_vt2_pd_site1_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site1_unit1( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE1_UNIT1_W { + MONITOR_EN_VT2_PD_SITE1_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site1_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site1_unit1( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE1_UNIT1_W { + DELAY_LIMIT_VT2_PD_SITE1_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT1_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT1_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit1_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT1_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit1_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT1_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT1_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT1_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf2.rs new file mode 100644 index 0000000000..2d049b356d --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT1_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE1_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE1_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site1_unit1(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_R { + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site1_unit1(&self) -> DELAY_OVF_VT2_PD_SITE1_UNIT1_R { + DELAY_OVF_VT2_PD_SITE1_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site1_unit1(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_R { + TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT1_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site1_unit1", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site1_unit1().bits()), + ) + .field( + "delay_ovf_vt2_pd_site1_unit1", + &format_args!("{}", self.delay_ovf_vt2_pd_site1_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site1_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site1_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site1_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_W { + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit1_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit1_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT1_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT1_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit1_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT1_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit1_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT1_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT1_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT1_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf1.rs new file mode 100644 index 0000000000..5a0cda1786 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE1_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE1_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE1_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE1_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE1_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE1_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE1_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE1_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE1_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE1_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE1_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE1_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site1_unit2(&self) -> MONITOR_EN_VT0_PD_SITE1_UNIT2_R { + MONITOR_EN_VT0_PD_SITE1_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site1_unit2(&self) -> DELAY_LIMIT_VT0_PD_SITE1_UNIT2_R { + DELAY_LIMIT_VT0_PD_SITE1_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site1_unit2(&self) -> DELAY_NUM_O_VT0_PD_SITE1_UNIT2_R { + DELAY_NUM_O_VT0_PD_SITE1_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site1_unit2(&self) -> TIMING_ERR_VT0_PD_SITE1_UNIT2_R { + TIMING_ERR_VT0_PD_SITE1_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT2_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site1_unit2", + &format_args!("{}", self.monitor_en_vt0_pd_site1_unit2().bit()), + ) + .field( + "delay_limit_vt0_pd_site1_unit2", + &format_args!("{}", self.delay_limit_vt0_pd_site1_unit2().bits()), + ) + .field( + "delay_num_o_vt0_pd_site1_unit2", + &format_args!("{}", self.delay_num_o_vt0_pd_site1_unit2().bits()), + ) + .field( + "timing_err_vt0_pd_site1_unit2", + &format_args!("{}", self.timing_err_vt0_pd_site1_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site1_unit2( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE1_UNIT2_W { + MONITOR_EN_VT0_PD_SITE1_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site1_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site1_unit2( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE1_UNIT2_W { + DELAY_LIMIT_VT0_PD_SITE1_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT2_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT2_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit2_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT2_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit2_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT2_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT2_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT2_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf2.rs new file mode 100644 index 0000000000..0491b45158 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE1_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE1_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site1_unit2(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_R { + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site1_unit2(&self) -> DELAY_OVF_VT0_PD_SITE1_UNIT2_R { + DELAY_OVF_VT0_PD_SITE1_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site1_unit2(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_R { + TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT2_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site1_unit2", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site1_unit2().bits()), + ) + .field( + "delay_ovf_vt0_pd_site1_unit2", + &format_args!("{}", self.delay_ovf_vt0_pd_site1_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site1_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site1_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site1_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_W { + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT2_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT2_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit2_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT2_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit2_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT2_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT2_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT2_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf1.rs new file mode 100644 index 0000000000..343aaeb911 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE1_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE1_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE1_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE1_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE1_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE1_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE1_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE1_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE1_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE1_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE1_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE1_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site1_unit2(&self) -> MONITOR_EN_VT1_PD_SITE1_UNIT2_R { + MONITOR_EN_VT1_PD_SITE1_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site1_unit2(&self) -> DELAY_LIMIT_VT1_PD_SITE1_UNIT2_R { + DELAY_LIMIT_VT1_PD_SITE1_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site1_unit2(&self) -> DELAY_NUM_O_VT1_PD_SITE1_UNIT2_R { + DELAY_NUM_O_VT1_PD_SITE1_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site1_unit2(&self) -> TIMING_ERR_VT1_PD_SITE1_UNIT2_R { + TIMING_ERR_VT1_PD_SITE1_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT2_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site1_unit2", + &format_args!("{}", self.monitor_en_vt1_pd_site1_unit2().bit()), + ) + .field( + "delay_limit_vt1_pd_site1_unit2", + &format_args!("{}", self.delay_limit_vt1_pd_site1_unit2().bits()), + ) + .field( + "delay_num_o_vt1_pd_site1_unit2", + &format_args!("{}", self.delay_num_o_vt1_pd_site1_unit2().bits()), + ) + .field( + "timing_err_vt1_pd_site1_unit2", + &format_args!("{}", self.timing_err_vt1_pd_site1_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site1_unit2( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE1_UNIT2_W { + MONITOR_EN_VT1_PD_SITE1_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site1_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site1_unit2( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE1_UNIT2_W { + DELAY_LIMIT_VT1_PD_SITE1_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT2_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT2_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit2_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT2_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit2_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT2_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT2_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT2_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf2.rs new file mode 100644 index 0000000000..e7e780160f --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE1_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE1_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site1_unit2(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_R { + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site1_unit2(&self) -> DELAY_OVF_VT1_PD_SITE1_UNIT2_R { + DELAY_OVF_VT1_PD_SITE1_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site1_unit2(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_R { + TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT2_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site1_unit2", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site1_unit2().bits()), + ) + .field( + "delay_ovf_vt1_pd_site1_unit2", + &format_args!("{}", self.delay_ovf_vt1_pd_site1_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site1_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site1_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site1_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_W { + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT2_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT2_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit2_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT2_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit2_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT2_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT2_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT2_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf1.rs new file mode 100644 index 0000000000..a1ecd6d5a7 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE1_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE1_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE1_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE1_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE1_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE1_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE1_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE1_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE1_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE1_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE1_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE1_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site1_unit2(&self) -> MONITOR_EN_VT2_PD_SITE1_UNIT2_R { + MONITOR_EN_VT2_PD_SITE1_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site1_unit2(&self) -> DELAY_LIMIT_VT2_PD_SITE1_UNIT2_R { + DELAY_LIMIT_VT2_PD_SITE1_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site1_unit2(&self) -> DELAY_NUM_O_VT2_PD_SITE1_UNIT2_R { + DELAY_NUM_O_VT2_PD_SITE1_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site1_unit2(&self) -> TIMING_ERR_VT2_PD_SITE1_UNIT2_R { + TIMING_ERR_VT2_PD_SITE1_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT2_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site1_unit2", + &format_args!("{}", self.monitor_en_vt2_pd_site1_unit2().bit()), + ) + .field( + "delay_limit_vt2_pd_site1_unit2", + &format_args!("{}", self.delay_limit_vt2_pd_site1_unit2().bits()), + ) + .field( + "delay_num_o_vt2_pd_site1_unit2", + &format_args!("{}", self.delay_num_o_vt2_pd_site1_unit2().bits()), + ) + .field( + "timing_err_vt2_pd_site1_unit2", + &format_args!("{}", self.timing_err_vt2_pd_site1_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site1_unit2( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE1_UNIT2_W { + MONITOR_EN_VT2_PD_SITE1_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site1_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site1_unit2( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE1_UNIT2_W { + DELAY_LIMIT_VT2_PD_SITE1_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT2_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT2_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit2_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT2_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit2_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT2_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT2_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT2_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf2.rs new file mode 100644 index 0000000000..e9836c591d --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT2_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE1_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE1_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site1_unit2(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_R { + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site1_unit2(&self) -> DELAY_OVF_VT2_PD_SITE1_UNIT2_R { + DELAY_OVF_VT2_PD_SITE1_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site1_unit2(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_R { + TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT2_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site1_unit2", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site1_unit2().bits()), + ) + .field( + "delay_ovf_vt2_pd_site1_unit2", + &format_args!("{}", self.delay_ovf_vt2_pd_site1_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site1_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site1_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site1_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_W { + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit2_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit2_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT2_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT2_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit2_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT2_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit2_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT2_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT2_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT2_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf1.rs new file mode 100644 index 0000000000..c2d46dd645 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE1_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE1_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE1_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE1_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE1_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE1_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE1_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE1_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE1_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE1_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE1_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE1_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site1_unit3(&self) -> MONITOR_EN_VT0_PD_SITE1_UNIT3_R { + MONITOR_EN_VT0_PD_SITE1_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site1_unit3(&self) -> DELAY_LIMIT_VT0_PD_SITE1_UNIT3_R { + DELAY_LIMIT_VT0_PD_SITE1_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site1_unit3(&self) -> DELAY_NUM_O_VT0_PD_SITE1_UNIT3_R { + DELAY_NUM_O_VT0_PD_SITE1_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site1_unit3(&self) -> TIMING_ERR_VT0_PD_SITE1_UNIT3_R { + TIMING_ERR_VT0_PD_SITE1_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT3_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site1_unit3", + &format_args!("{}", self.monitor_en_vt0_pd_site1_unit3().bit()), + ) + .field( + "delay_limit_vt0_pd_site1_unit3", + &format_args!("{}", self.delay_limit_vt0_pd_site1_unit3().bits()), + ) + .field( + "delay_num_o_vt0_pd_site1_unit3", + &format_args!("{}", self.delay_num_o_vt0_pd_site1_unit3().bits()), + ) + .field( + "timing_err_vt0_pd_site1_unit3", + &format_args!("{}", self.timing_err_vt0_pd_site1_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site1_unit3( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE1_UNIT3_W { + MONITOR_EN_VT0_PD_SITE1_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site1_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site1_unit3( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE1_UNIT3_W { + DELAY_LIMIT_VT0_PD_SITE1_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT3_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT3_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit3_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT3_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit3_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT3_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT3_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT3_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf2.rs new file mode 100644 index 0000000000..518abe8e4c --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE1_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE1_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site1_unit3(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_R { + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site1_unit3(&self) -> DELAY_OVF_VT0_PD_SITE1_UNIT3_R { + DELAY_OVF_VT0_PD_SITE1_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site1_unit3(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_R { + TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT3_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site1_unit3", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site1_unit3().bits()), + ) + .field( + "delay_ovf_vt0_pd_site1_unit3", + &format_args!("{}", self.delay_ovf_vt0_pd_site1_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site1_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site1_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site1_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_W { + MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT3_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT3_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit3_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT3_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit3_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT3_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT3_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT3_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf1.rs new file mode 100644 index 0000000000..609941708b --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE1_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE1_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE1_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE1_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE1_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE1_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE1_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE1_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE1_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE1_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE1_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE1_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site1_unit3(&self) -> MONITOR_EN_VT1_PD_SITE1_UNIT3_R { + MONITOR_EN_VT1_PD_SITE1_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site1_unit3(&self) -> DELAY_LIMIT_VT1_PD_SITE1_UNIT3_R { + DELAY_LIMIT_VT1_PD_SITE1_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site1_unit3(&self) -> DELAY_NUM_O_VT1_PD_SITE1_UNIT3_R { + DELAY_NUM_O_VT1_PD_SITE1_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site1_unit3(&self) -> TIMING_ERR_VT1_PD_SITE1_UNIT3_R { + TIMING_ERR_VT1_PD_SITE1_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT3_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site1_unit3", + &format_args!("{}", self.monitor_en_vt1_pd_site1_unit3().bit()), + ) + .field( + "delay_limit_vt1_pd_site1_unit3", + &format_args!("{}", self.delay_limit_vt1_pd_site1_unit3().bits()), + ) + .field( + "delay_num_o_vt1_pd_site1_unit3", + &format_args!("{}", self.delay_num_o_vt1_pd_site1_unit3().bits()), + ) + .field( + "timing_err_vt1_pd_site1_unit3", + &format_args!("{}", self.timing_err_vt1_pd_site1_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site1_unit3( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE1_UNIT3_W { + MONITOR_EN_VT1_PD_SITE1_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site1_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site1_unit3( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE1_UNIT3_W { + DELAY_LIMIT_VT1_PD_SITE1_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT3_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT3_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit3_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT3_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit3_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT3_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT3_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT3_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf2.rs new file mode 100644 index 0000000000..aa90c17e1c --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE1_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE1_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site1_unit3(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_R { + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site1_unit3(&self) -> DELAY_OVF_VT1_PD_SITE1_UNIT3_R { + DELAY_OVF_VT1_PD_SITE1_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site1_unit3(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_R { + TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT3_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site1_unit3", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site1_unit3().bits()), + ) + .field( + "delay_ovf_vt1_pd_site1_unit3", + &format_args!("{}", self.delay_ovf_vt1_pd_site1_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site1_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site1_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site1_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_W { + MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT3_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT3_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit3_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT3_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit3_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT3_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT3_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT3_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf1.rs new file mode 100644 index 0000000000..55ae45805f --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE1_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE1_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE1_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE1_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE1_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE1_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE1_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE1_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE1_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE1_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE1_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE1_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site1_unit3(&self) -> MONITOR_EN_VT2_PD_SITE1_UNIT3_R { + MONITOR_EN_VT2_PD_SITE1_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site1_unit3(&self) -> DELAY_LIMIT_VT2_PD_SITE1_UNIT3_R { + DELAY_LIMIT_VT2_PD_SITE1_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site1_unit3(&self) -> DELAY_NUM_O_VT2_PD_SITE1_UNIT3_R { + DELAY_NUM_O_VT2_PD_SITE1_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site1_unit3(&self) -> TIMING_ERR_VT2_PD_SITE1_UNIT3_R { + TIMING_ERR_VT2_PD_SITE1_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT3_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site1_unit3", + &format_args!("{}", self.monitor_en_vt2_pd_site1_unit3().bit()), + ) + .field( + "delay_limit_vt2_pd_site1_unit3", + &format_args!("{}", self.delay_limit_vt2_pd_site1_unit3().bits()), + ) + .field( + "delay_num_o_vt2_pd_site1_unit3", + &format_args!("{}", self.delay_num_o_vt2_pd_site1_unit3().bits()), + ) + .field( + "timing_err_vt2_pd_site1_unit3", + &format_args!("{}", self.timing_err_vt2_pd_site1_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site1_unit3( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE1_UNIT3_W { + MONITOR_EN_VT2_PD_SITE1_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site1_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site1_unit3( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE1_UNIT3_W { + DELAY_LIMIT_VT2_PD_SITE1_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT3_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT3_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit3_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT3_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit3_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT3_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT3_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE1_UNIT3_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf2.rs new file mode 100644 index 0000000000..ab68902fb6 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE1_UNIT3_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE1_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE1_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site1_unit3(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_R { + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site1_unit3(&self) -> DELAY_OVF_VT2_PD_SITE1_UNIT3_R { + DELAY_OVF_VT2_PD_SITE1_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site1_unit3(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_R { + TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE1_UNIT3_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site1_unit3", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site1_unit3().bits()), + ) + .field( + "delay_ovf_vt2_pd_site1_unit3", + &format_args!("{}", self.delay_ovf_vt2_pd_site1_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site1_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site1_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site1_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_W { + MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site1_unit3_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site1_unit3_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE1_UNIT3_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE1_UNIT3_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site1_unit3_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE1_UNIT3_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site1_unit3_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE1_UNIT3_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE1_UNIT3_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE1_UNIT3_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf1.rs new file mode 100644 index 0000000000..3846e6bb9b --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE2_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE2_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE2_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE2_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE2_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE2_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE2_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE2_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE2_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE2_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE2_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE2_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site2_unit0(&self) -> MONITOR_EN_VT0_PD_SITE2_UNIT0_R { + MONITOR_EN_VT0_PD_SITE2_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site2_unit0(&self) -> DELAY_LIMIT_VT0_PD_SITE2_UNIT0_R { + DELAY_LIMIT_VT0_PD_SITE2_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site2_unit0(&self) -> DELAY_NUM_O_VT0_PD_SITE2_UNIT0_R { + DELAY_NUM_O_VT0_PD_SITE2_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site2_unit0(&self) -> TIMING_ERR_VT0_PD_SITE2_UNIT0_R { + TIMING_ERR_VT0_PD_SITE2_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT0_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site2_unit0", + &format_args!("{}", self.monitor_en_vt0_pd_site2_unit0().bit()), + ) + .field( + "delay_limit_vt0_pd_site2_unit0", + &format_args!("{}", self.delay_limit_vt0_pd_site2_unit0().bits()), + ) + .field( + "delay_num_o_vt0_pd_site2_unit0", + &format_args!("{}", self.delay_num_o_vt0_pd_site2_unit0().bits()), + ) + .field( + "timing_err_vt0_pd_site2_unit0", + &format_args!("{}", self.timing_err_vt0_pd_site2_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site2_unit0( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE2_UNIT0_W { + MONITOR_EN_VT0_PD_SITE2_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site2_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site2_unit0( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE2_UNIT0_W { + DELAY_LIMIT_VT0_PD_SITE2_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT0_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT0_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit0_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT0_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit0_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT0_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT0_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT0_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf2.rs new file mode 100644 index 0000000000..1554b5d21b --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE2_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE2_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site2_unit0(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_R { + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site2_unit0(&self) -> DELAY_OVF_VT0_PD_SITE2_UNIT0_R { + DELAY_OVF_VT0_PD_SITE2_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site2_unit0(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_R { + TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT0_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site2_unit0", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site2_unit0().bits()), + ) + .field( + "delay_ovf_vt0_pd_site2_unit0", + &format_args!("{}", self.delay_ovf_vt0_pd_site2_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site2_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site2_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site2_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_W { + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT0_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT0_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit0_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT0_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit0_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT0_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT0_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT0_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf1.rs new file mode 100644 index 0000000000..0301479756 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE2_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE2_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE2_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE2_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE2_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE2_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE2_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE2_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE2_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE2_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE2_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE2_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site2_unit0(&self) -> MONITOR_EN_VT1_PD_SITE2_UNIT0_R { + MONITOR_EN_VT1_PD_SITE2_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site2_unit0(&self) -> DELAY_LIMIT_VT1_PD_SITE2_UNIT0_R { + DELAY_LIMIT_VT1_PD_SITE2_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site2_unit0(&self) -> DELAY_NUM_O_VT1_PD_SITE2_UNIT0_R { + DELAY_NUM_O_VT1_PD_SITE2_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site2_unit0(&self) -> TIMING_ERR_VT1_PD_SITE2_UNIT0_R { + TIMING_ERR_VT1_PD_SITE2_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT0_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site2_unit0", + &format_args!("{}", self.monitor_en_vt1_pd_site2_unit0().bit()), + ) + .field( + "delay_limit_vt1_pd_site2_unit0", + &format_args!("{}", self.delay_limit_vt1_pd_site2_unit0().bits()), + ) + .field( + "delay_num_o_vt1_pd_site2_unit0", + &format_args!("{}", self.delay_num_o_vt1_pd_site2_unit0().bits()), + ) + .field( + "timing_err_vt1_pd_site2_unit0", + &format_args!("{}", self.timing_err_vt1_pd_site2_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site2_unit0( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE2_UNIT0_W { + MONITOR_EN_VT1_PD_SITE2_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site2_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site2_unit0( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE2_UNIT0_W { + DELAY_LIMIT_VT1_PD_SITE2_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT0_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT0_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit0_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT0_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit0_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT0_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT0_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT0_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf2.rs new file mode 100644 index 0000000000..01ad7e6c5e --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE2_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE2_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site2_unit0(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_R { + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site2_unit0(&self) -> DELAY_OVF_VT1_PD_SITE2_UNIT0_R { + DELAY_OVF_VT1_PD_SITE2_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site2_unit0(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_R { + TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT0_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site2_unit0", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site2_unit0().bits()), + ) + .field( + "delay_ovf_vt1_pd_site2_unit0", + &format_args!("{}", self.delay_ovf_vt1_pd_site2_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site2_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site2_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site2_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_W { + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT0_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT0_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit0_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT0_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit0_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT0_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT0_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT0_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf1.rs new file mode 100644 index 0000000000..aba2e8bdf6 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE2_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE2_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE2_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE2_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE2_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE2_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE2_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE2_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE2_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE2_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE2_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE2_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site2_unit0(&self) -> MONITOR_EN_VT2_PD_SITE2_UNIT0_R { + MONITOR_EN_VT2_PD_SITE2_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site2_unit0(&self) -> DELAY_LIMIT_VT2_PD_SITE2_UNIT0_R { + DELAY_LIMIT_VT2_PD_SITE2_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site2_unit0(&self) -> DELAY_NUM_O_VT2_PD_SITE2_UNIT0_R { + DELAY_NUM_O_VT2_PD_SITE2_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site2_unit0(&self) -> TIMING_ERR_VT2_PD_SITE2_UNIT0_R { + TIMING_ERR_VT2_PD_SITE2_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT0_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site2_unit0", + &format_args!("{}", self.monitor_en_vt2_pd_site2_unit0().bit()), + ) + .field( + "delay_limit_vt2_pd_site2_unit0", + &format_args!("{}", self.delay_limit_vt2_pd_site2_unit0().bits()), + ) + .field( + "delay_num_o_vt2_pd_site2_unit0", + &format_args!("{}", self.delay_num_o_vt2_pd_site2_unit0().bits()), + ) + .field( + "timing_err_vt2_pd_site2_unit0", + &format_args!("{}", self.timing_err_vt2_pd_site2_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site2_unit0( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE2_UNIT0_W { + MONITOR_EN_VT2_PD_SITE2_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site2_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site2_unit0( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE2_UNIT0_W { + DELAY_LIMIT_VT2_PD_SITE2_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT0_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT0_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit0_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT0_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit0_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT0_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT0_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT0_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf2.rs new file mode 100644 index 0000000000..3d0a93c314 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT0_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE2_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE2_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site2_unit0(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_R { + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site2_unit0(&self) -> DELAY_OVF_VT2_PD_SITE2_UNIT0_R { + DELAY_OVF_VT2_PD_SITE2_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site2_unit0(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_R { + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT0_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site2_unit0", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site2_unit0().bits()), + ) + .field( + "delay_ovf_vt2_pd_site2_unit0", + &format_args!("{}", self.delay_ovf_vt2_pd_site2_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site2_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site2_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site2_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_W { + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit0_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit0_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT0_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT0_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit0_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT0_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit0_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT0_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT0_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT0_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf1.rs new file mode 100644 index 0000000000..e32661bd88 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE2_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE2_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE2_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE2_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE2_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE2_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE2_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE2_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE2_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE2_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE2_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE2_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site2_unit1(&self) -> MONITOR_EN_VT0_PD_SITE2_UNIT1_R { + MONITOR_EN_VT0_PD_SITE2_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site2_unit1(&self) -> DELAY_LIMIT_VT0_PD_SITE2_UNIT1_R { + DELAY_LIMIT_VT0_PD_SITE2_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site2_unit1(&self) -> DELAY_NUM_O_VT0_PD_SITE2_UNIT1_R { + DELAY_NUM_O_VT0_PD_SITE2_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site2_unit1(&self) -> TIMING_ERR_VT0_PD_SITE2_UNIT1_R { + TIMING_ERR_VT0_PD_SITE2_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT1_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site2_unit1", + &format_args!("{}", self.monitor_en_vt0_pd_site2_unit1().bit()), + ) + .field( + "delay_limit_vt0_pd_site2_unit1", + &format_args!("{}", self.delay_limit_vt0_pd_site2_unit1().bits()), + ) + .field( + "delay_num_o_vt0_pd_site2_unit1", + &format_args!("{}", self.delay_num_o_vt0_pd_site2_unit1().bits()), + ) + .field( + "timing_err_vt0_pd_site2_unit1", + &format_args!("{}", self.timing_err_vt0_pd_site2_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site2_unit1( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE2_UNIT1_W { + MONITOR_EN_VT0_PD_SITE2_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site2_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site2_unit1( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE2_UNIT1_W { + DELAY_LIMIT_VT0_PD_SITE2_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT1_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT1_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit1_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT1_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit1_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT1_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT1_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT1_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf2.rs new file mode 100644 index 0000000000..03c9fd4dcc --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE2_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE2_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site2_unit1(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_R { + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site2_unit1(&self) -> DELAY_OVF_VT0_PD_SITE2_UNIT1_R { + DELAY_OVF_VT0_PD_SITE2_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site2_unit1(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_R { + TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT1_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site2_unit1", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site2_unit1().bits()), + ) + .field( + "delay_ovf_vt0_pd_site2_unit1", + &format_args!("{}", self.delay_ovf_vt0_pd_site2_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site2_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site2_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site2_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_W { + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT1_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT1_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit1_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT1_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit1_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT1_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT1_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT1_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf1.rs new file mode 100644 index 0000000000..94efa8a45c --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE2_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE2_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE2_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE2_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE2_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE2_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE2_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE2_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE2_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE2_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE2_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE2_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site2_unit1(&self) -> MONITOR_EN_VT1_PD_SITE2_UNIT1_R { + MONITOR_EN_VT1_PD_SITE2_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site2_unit1(&self) -> DELAY_LIMIT_VT1_PD_SITE2_UNIT1_R { + DELAY_LIMIT_VT1_PD_SITE2_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site2_unit1(&self) -> DELAY_NUM_O_VT1_PD_SITE2_UNIT1_R { + DELAY_NUM_O_VT1_PD_SITE2_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site2_unit1(&self) -> TIMING_ERR_VT1_PD_SITE2_UNIT1_R { + TIMING_ERR_VT1_PD_SITE2_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT1_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site2_unit1", + &format_args!("{}", self.monitor_en_vt1_pd_site2_unit1().bit()), + ) + .field( + "delay_limit_vt1_pd_site2_unit1", + &format_args!("{}", self.delay_limit_vt1_pd_site2_unit1().bits()), + ) + .field( + "delay_num_o_vt1_pd_site2_unit1", + &format_args!("{}", self.delay_num_o_vt1_pd_site2_unit1().bits()), + ) + .field( + "timing_err_vt1_pd_site2_unit1", + &format_args!("{}", self.timing_err_vt1_pd_site2_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site2_unit1( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE2_UNIT1_W { + MONITOR_EN_VT1_PD_SITE2_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site2_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site2_unit1( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE2_UNIT1_W { + DELAY_LIMIT_VT1_PD_SITE2_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT1_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT1_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit1_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT1_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit1_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT1_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT1_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT1_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf2.rs new file mode 100644 index 0000000000..eb571d3219 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE2_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE2_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site2_unit1(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_R { + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site2_unit1(&self) -> DELAY_OVF_VT1_PD_SITE2_UNIT1_R { + DELAY_OVF_VT1_PD_SITE2_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site2_unit1(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_R { + TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT1_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site2_unit1", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site2_unit1().bits()), + ) + .field( + "delay_ovf_vt1_pd_site2_unit1", + &format_args!("{}", self.delay_ovf_vt1_pd_site2_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site2_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site2_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site2_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_W { + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT1_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT1_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit1_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT1_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit1_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT1_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT1_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT1_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf1.rs new file mode 100644 index 0000000000..5757e831c5 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE2_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE2_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE2_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE2_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE2_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE2_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE2_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE2_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE2_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE2_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE2_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE2_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site2_unit1(&self) -> MONITOR_EN_VT2_PD_SITE2_UNIT1_R { + MONITOR_EN_VT2_PD_SITE2_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site2_unit1(&self) -> DELAY_LIMIT_VT2_PD_SITE2_UNIT1_R { + DELAY_LIMIT_VT2_PD_SITE2_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site2_unit1(&self) -> DELAY_NUM_O_VT2_PD_SITE2_UNIT1_R { + DELAY_NUM_O_VT2_PD_SITE2_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site2_unit1(&self) -> TIMING_ERR_VT2_PD_SITE2_UNIT1_R { + TIMING_ERR_VT2_PD_SITE2_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT1_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site2_unit1", + &format_args!("{}", self.monitor_en_vt2_pd_site2_unit1().bit()), + ) + .field( + "delay_limit_vt2_pd_site2_unit1", + &format_args!("{}", self.delay_limit_vt2_pd_site2_unit1().bits()), + ) + .field( + "delay_num_o_vt2_pd_site2_unit1", + &format_args!("{}", self.delay_num_o_vt2_pd_site2_unit1().bits()), + ) + .field( + "timing_err_vt2_pd_site2_unit1", + &format_args!("{}", self.timing_err_vt2_pd_site2_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site2_unit1( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE2_UNIT1_W { + MONITOR_EN_VT2_PD_SITE2_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site2_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site2_unit1( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE2_UNIT1_W { + DELAY_LIMIT_VT2_PD_SITE2_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT1_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT1_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit1_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT1_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit1_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT1_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT1_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT1_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf2.rs new file mode 100644 index 0000000000..45d3829a53 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT1_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE2_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE2_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site2_unit1(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_R { + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site2_unit1(&self) -> DELAY_OVF_VT2_PD_SITE2_UNIT1_R { + DELAY_OVF_VT2_PD_SITE2_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site2_unit1(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_R { + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT1_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site2_unit1", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site2_unit1().bits()), + ) + .field( + "delay_ovf_vt2_pd_site2_unit1", + &format_args!("{}", self.delay_ovf_vt2_pd_site2_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site2_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site2_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site2_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_W { + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit1_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit1_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT1_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT1_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit1_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT1_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit1_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT1_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT1_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT1_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf1.rs new file mode 100644 index 0000000000..ed3e7b6d12 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE2_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE2_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE2_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE2_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE2_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE2_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE2_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE2_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE2_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE2_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE2_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE2_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site2_unit2(&self) -> MONITOR_EN_VT0_PD_SITE2_UNIT2_R { + MONITOR_EN_VT0_PD_SITE2_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site2_unit2(&self) -> DELAY_LIMIT_VT0_PD_SITE2_UNIT2_R { + DELAY_LIMIT_VT0_PD_SITE2_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site2_unit2(&self) -> DELAY_NUM_O_VT0_PD_SITE2_UNIT2_R { + DELAY_NUM_O_VT0_PD_SITE2_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site2_unit2(&self) -> TIMING_ERR_VT0_PD_SITE2_UNIT2_R { + TIMING_ERR_VT0_PD_SITE2_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT2_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site2_unit2", + &format_args!("{}", self.monitor_en_vt0_pd_site2_unit2().bit()), + ) + .field( + "delay_limit_vt0_pd_site2_unit2", + &format_args!("{}", self.delay_limit_vt0_pd_site2_unit2().bits()), + ) + .field( + "delay_num_o_vt0_pd_site2_unit2", + &format_args!("{}", self.delay_num_o_vt0_pd_site2_unit2().bits()), + ) + .field( + "timing_err_vt0_pd_site2_unit2", + &format_args!("{}", self.timing_err_vt0_pd_site2_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site2_unit2( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE2_UNIT2_W { + MONITOR_EN_VT0_PD_SITE2_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site2_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site2_unit2( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE2_UNIT2_W { + DELAY_LIMIT_VT0_PD_SITE2_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT2_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT2_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit2_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT2_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit2_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT2_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT2_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT2_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf2.rs new file mode 100644 index 0000000000..928395319d --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE2_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE2_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site2_unit2(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_R { + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site2_unit2(&self) -> DELAY_OVF_VT0_PD_SITE2_UNIT2_R { + DELAY_OVF_VT0_PD_SITE2_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site2_unit2(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_R { + TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT2_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site2_unit2", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site2_unit2().bits()), + ) + .field( + "delay_ovf_vt0_pd_site2_unit2", + &format_args!("{}", self.delay_ovf_vt0_pd_site2_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site2_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site2_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site2_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_W { + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT2_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT2_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit2_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT2_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit2_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT2_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT2_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT2_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf1.rs new file mode 100644 index 0000000000..e22fecffc0 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE2_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE2_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE2_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE2_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE2_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE2_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE2_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE2_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE2_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE2_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE2_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE2_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site2_unit2(&self) -> MONITOR_EN_VT1_PD_SITE2_UNIT2_R { + MONITOR_EN_VT1_PD_SITE2_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site2_unit2(&self) -> DELAY_LIMIT_VT1_PD_SITE2_UNIT2_R { + DELAY_LIMIT_VT1_PD_SITE2_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site2_unit2(&self) -> DELAY_NUM_O_VT1_PD_SITE2_UNIT2_R { + DELAY_NUM_O_VT1_PD_SITE2_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site2_unit2(&self) -> TIMING_ERR_VT1_PD_SITE2_UNIT2_R { + TIMING_ERR_VT1_PD_SITE2_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT2_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site2_unit2", + &format_args!("{}", self.monitor_en_vt1_pd_site2_unit2().bit()), + ) + .field( + "delay_limit_vt1_pd_site2_unit2", + &format_args!("{}", self.delay_limit_vt1_pd_site2_unit2().bits()), + ) + .field( + "delay_num_o_vt1_pd_site2_unit2", + &format_args!("{}", self.delay_num_o_vt1_pd_site2_unit2().bits()), + ) + .field( + "timing_err_vt1_pd_site2_unit2", + &format_args!("{}", self.timing_err_vt1_pd_site2_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site2_unit2( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE2_UNIT2_W { + MONITOR_EN_VT1_PD_SITE2_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site2_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site2_unit2( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE2_UNIT2_W { + DELAY_LIMIT_VT1_PD_SITE2_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT2_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT2_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit2_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT2_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit2_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT2_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT2_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT2_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf2.rs new file mode 100644 index 0000000000..00df9476d6 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE2_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE2_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site2_unit2(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_R { + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site2_unit2(&self) -> DELAY_OVF_VT1_PD_SITE2_UNIT2_R { + DELAY_OVF_VT1_PD_SITE2_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site2_unit2(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_R { + TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT2_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site2_unit2", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site2_unit2().bits()), + ) + .field( + "delay_ovf_vt1_pd_site2_unit2", + &format_args!("{}", self.delay_ovf_vt1_pd_site2_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site2_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site2_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site2_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_W { + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT2_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT2_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit2_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT2_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit2_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT2_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT2_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT2_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf1.rs new file mode 100644 index 0000000000..84a8675904 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE2_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE2_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE2_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE2_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE2_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE2_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE2_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE2_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE2_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE2_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE2_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE2_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site2_unit2(&self) -> MONITOR_EN_VT2_PD_SITE2_UNIT2_R { + MONITOR_EN_VT2_PD_SITE2_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site2_unit2(&self) -> DELAY_LIMIT_VT2_PD_SITE2_UNIT2_R { + DELAY_LIMIT_VT2_PD_SITE2_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site2_unit2(&self) -> DELAY_NUM_O_VT2_PD_SITE2_UNIT2_R { + DELAY_NUM_O_VT2_PD_SITE2_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site2_unit2(&self) -> TIMING_ERR_VT2_PD_SITE2_UNIT2_R { + TIMING_ERR_VT2_PD_SITE2_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT2_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site2_unit2", + &format_args!("{}", self.monitor_en_vt2_pd_site2_unit2().bit()), + ) + .field( + "delay_limit_vt2_pd_site2_unit2", + &format_args!("{}", self.delay_limit_vt2_pd_site2_unit2().bits()), + ) + .field( + "delay_num_o_vt2_pd_site2_unit2", + &format_args!("{}", self.delay_num_o_vt2_pd_site2_unit2().bits()), + ) + .field( + "timing_err_vt2_pd_site2_unit2", + &format_args!("{}", self.timing_err_vt2_pd_site2_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site2_unit2( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE2_UNIT2_W { + MONITOR_EN_VT2_PD_SITE2_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site2_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site2_unit2( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE2_UNIT2_W { + DELAY_LIMIT_VT2_PD_SITE2_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT2_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT2_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit2_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT2_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit2_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT2_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT2_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT2_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf2.rs new file mode 100644 index 0000000000..0c0cc39d94 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT2_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE2_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE2_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site2_unit2(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_R { + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site2_unit2(&self) -> DELAY_OVF_VT2_PD_SITE2_UNIT2_R { + DELAY_OVF_VT2_PD_SITE2_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site2_unit2(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_R { + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT2_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site2_unit2", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site2_unit2().bits()), + ) + .field( + "delay_ovf_vt2_pd_site2_unit2", + &format_args!("{}", self.delay_ovf_vt2_pd_site2_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site2_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site2_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site2_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_W { + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit2_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit2_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT2_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT2_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit2_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT2_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit2_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT2_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT2_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT2_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf1.rs new file mode 100644 index 0000000000..1e1121d145 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE2_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE2_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE2_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE2_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE2_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE2_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE2_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE2_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE2_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE2_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE2_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE2_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site2_unit3(&self) -> MONITOR_EN_VT0_PD_SITE2_UNIT3_R { + MONITOR_EN_VT0_PD_SITE2_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site2_unit3(&self) -> DELAY_LIMIT_VT0_PD_SITE2_UNIT3_R { + DELAY_LIMIT_VT0_PD_SITE2_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site2_unit3(&self) -> DELAY_NUM_O_VT0_PD_SITE2_UNIT3_R { + DELAY_NUM_O_VT0_PD_SITE2_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site2_unit3(&self) -> TIMING_ERR_VT0_PD_SITE2_UNIT3_R { + TIMING_ERR_VT0_PD_SITE2_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT3_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site2_unit3", + &format_args!("{}", self.monitor_en_vt0_pd_site2_unit3().bit()), + ) + .field( + "delay_limit_vt0_pd_site2_unit3", + &format_args!("{}", self.delay_limit_vt0_pd_site2_unit3().bits()), + ) + .field( + "delay_num_o_vt0_pd_site2_unit3", + &format_args!("{}", self.delay_num_o_vt0_pd_site2_unit3().bits()), + ) + .field( + "timing_err_vt0_pd_site2_unit3", + &format_args!("{}", self.timing_err_vt0_pd_site2_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site2_unit3( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE2_UNIT3_W { + MONITOR_EN_VT0_PD_SITE2_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site2_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site2_unit3( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE2_UNIT3_W { + DELAY_LIMIT_VT0_PD_SITE2_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT3_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT3_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit3_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT3_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit3_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT3_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT3_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT3_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf2.rs new file mode 100644 index 0000000000..7a3e664974 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE2_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE2_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site2_unit3(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_R { + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site2_unit3(&self) -> DELAY_OVF_VT0_PD_SITE2_UNIT3_R { + DELAY_OVF_VT0_PD_SITE2_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site2_unit3(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_R { + TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT3_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site2_unit3", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site2_unit3().bits()), + ) + .field( + "delay_ovf_vt0_pd_site2_unit3", + &format_args!("{}", self.delay_ovf_vt0_pd_site2_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site2_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site2_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site2_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_W { + MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT3_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT3_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit3_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT3_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit3_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT3_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT3_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT3_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf1.rs new file mode 100644 index 0000000000..10597a251d --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE2_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE2_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE2_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE2_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE2_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE2_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE2_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE2_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE2_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE2_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE2_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE2_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site2_unit3(&self) -> MONITOR_EN_VT1_PD_SITE2_UNIT3_R { + MONITOR_EN_VT1_PD_SITE2_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site2_unit3(&self) -> DELAY_LIMIT_VT1_PD_SITE2_UNIT3_R { + DELAY_LIMIT_VT1_PD_SITE2_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site2_unit3(&self) -> DELAY_NUM_O_VT1_PD_SITE2_UNIT3_R { + DELAY_NUM_O_VT1_PD_SITE2_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site2_unit3(&self) -> TIMING_ERR_VT1_PD_SITE2_UNIT3_R { + TIMING_ERR_VT1_PD_SITE2_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT3_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site2_unit3", + &format_args!("{}", self.monitor_en_vt1_pd_site2_unit3().bit()), + ) + .field( + "delay_limit_vt1_pd_site2_unit3", + &format_args!("{}", self.delay_limit_vt1_pd_site2_unit3().bits()), + ) + .field( + "delay_num_o_vt1_pd_site2_unit3", + &format_args!("{}", self.delay_num_o_vt1_pd_site2_unit3().bits()), + ) + .field( + "timing_err_vt1_pd_site2_unit3", + &format_args!("{}", self.timing_err_vt1_pd_site2_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site2_unit3( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE2_UNIT3_W { + MONITOR_EN_VT1_PD_SITE2_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site2_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site2_unit3( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE2_UNIT3_W { + DELAY_LIMIT_VT1_PD_SITE2_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT3_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT3_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit3_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT3_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit3_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT3_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT3_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT3_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf2.rs new file mode 100644 index 0000000000..e722c7d1b5 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE2_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE2_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site2_unit3(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_R { + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site2_unit3(&self) -> DELAY_OVF_VT1_PD_SITE2_UNIT3_R { + DELAY_OVF_VT1_PD_SITE2_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site2_unit3(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_R { + TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT3_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site2_unit3", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site2_unit3().bits()), + ) + .field( + "delay_ovf_vt1_pd_site2_unit3", + &format_args!("{}", self.delay_ovf_vt1_pd_site2_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site2_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site2_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site2_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_W { + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT3_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT3_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit3_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT3_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit3_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT3_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT3_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT3_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf1.rs new file mode 100644 index 0000000000..2156e9d20a --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE2_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE2_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE2_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE2_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE2_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE2_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE2_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE2_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE2_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE2_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE2_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE2_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site2_unit3(&self) -> MONITOR_EN_VT2_PD_SITE2_UNIT3_R { + MONITOR_EN_VT2_PD_SITE2_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site2_unit3(&self) -> DELAY_LIMIT_VT2_PD_SITE2_UNIT3_R { + DELAY_LIMIT_VT2_PD_SITE2_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site2_unit3(&self) -> DELAY_NUM_O_VT2_PD_SITE2_UNIT3_R { + DELAY_NUM_O_VT2_PD_SITE2_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site2_unit3(&self) -> TIMING_ERR_VT2_PD_SITE2_UNIT3_R { + TIMING_ERR_VT2_PD_SITE2_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT3_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site2_unit3", + &format_args!("{}", self.monitor_en_vt2_pd_site2_unit3().bit()), + ) + .field( + "delay_limit_vt2_pd_site2_unit3", + &format_args!("{}", self.delay_limit_vt2_pd_site2_unit3().bits()), + ) + .field( + "delay_num_o_vt2_pd_site2_unit3", + &format_args!("{}", self.delay_num_o_vt2_pd_site2_unit3().bits()), + ) + .field( + "timing_err_vt2_pd_site2_unit3", + &format_args!("{}", self.timing_err_vt2_pd_site2_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site2_unit3( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE2_UNIT3_W { + MONITOR_EN_VT2_PD_SITE2_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site2_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site2_unit3( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE2_UNIT3_W { + DELAY_LIMIT_VT2_PD_SITE2_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT3_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT3_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit3_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT3_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit3_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT3_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT3_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE2_UNIT3_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf2.rs new file mode 100644 index 0000000000..1b7d5fb442 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE2_UNIT3_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE2_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE2_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site2_unit3(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_R { + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site2_unit3(&self) -> DELAY_OVF_VT2_PD_SITE2_UNIT3_R { + DELAY_OVF_VT2_PD_SITE2_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site2_unit3(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_R { + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE2_UNIT3_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site2_unit3", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site2_unit3().bits()), + ) + .field( + "delay_ovf_vt2_pd_site2_unit3", + &format_args!("{}", self.delay_ovf_vt2_pd_site2_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site2_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site2_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site2_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_W { + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site2_unit3_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site2_unit3_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE2_UNIT3_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE2_UNIT3_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site2_unit3_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE2_UNIT3_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site2_unit3_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE2_UNIT3_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE2_UNIT3_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE2_UNIT3_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf1.rs new file mode 100644 index 0000000000..3bc687bf00 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE3_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE3_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE3_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE3_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE3_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE3_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE3_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE3_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE3_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE3_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE3_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE3_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site3_unit0(&self) -> MONITOR_EN_VT0_PD_SITE3_UNIT0_R { + MONITOR_EN_VT0_PD_SITE3_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site3_unit0(&self) -> DELAY_LIMIT_VT0_PD_SITE3_UNIT0_R { + DELAY_LIMIT_VT0_PD_SITE3_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site3_unit0(&self) -> DELAY_NUM_O_VT0_PD_SITE3_UNIT0_R { + DELAY_NUM_O_VT0_PD_SITE3_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site3_unit0(&self) -> TIMING_ERR_VT0_PD_SITE3_UNIT0_R { + TIMING_ERR_VT0_PD_SITE3_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT0_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site3_unit0", + &format_args!("{}", self.monitor_en_vt0_pd_site3_unit0().bit()), + ) + .field( + "delay_limit_vt0_pd_site3_unit0", + &format_args!("{}", self.delay_limit_vt0_pd_site3_unit0().bits()), + ) + .field( + "delay_num_o_vt0_pd_site3_unit0", + &format_args!("{}", self.delay_num_o_vt0_pd_site3_unit0().bits()), + ) + .field( + "timing_err_vt0_pd_site3_unit0", + &format_args!("{}", self.timing_err_vt0_pd_site3_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site3_unit0( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE3_UNIT0_W { + MONITOR_EN_VT0_PD_SITE3_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site3_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site3_unit0( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE3_UNIT0_W { + DELAY_LIMIT_VT0_PD_SITE3_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT0_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT0_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit0_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT0_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit0_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT0_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT0_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT0_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf2.rs new file mode 100644 index 0000000000..8c2867322a --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE3_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE3_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site3_unit0(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_R { + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site3_unit0(&self) -> DELAY_OVF_VT0_PD_SITE3_UNIT0_R { + DELAY_OVF_VT0_PD_SITE3_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site3_unit0(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_R { + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT0_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site3_unit0", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site3_unit0().bits()), + ) + .field( + "delay_ovf_vt0_pd_site3_unit0", + &format_args!("{}", self.delay_ovf_vt0_pd_site3_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site3_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site3_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site3_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_W { + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT0_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT0_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit0_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT0_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit0_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT0_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT0_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT0_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf1.rs new file mode 100644 index 0000000000..80c9b7e280 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE3_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE3_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE3_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE3_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE3_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE3_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE3_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE3_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE3_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE3_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE3_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE3_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site3_unit0(&self) -> MONITOR_EN_VT1_PD_SITE3_UNIT0_R { + MONITOR_EN_VT1_PD_SITE3_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site3_unit0(&self) -> DELAY_LIMIT_VT1_PD_SITE3_UNIT0_R { + DELAY_LIMIT_VT1_PD_SITE3_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site3_unit0(&self) -> DELAY_NUM_O_VT1_PD_SITE3_UNIT0_R { + DELAY_NUM_O_VT1_PD_SITE3_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site3_unit0(&self) -> TIMING_ERR_VT1_PD_SITE3_UNIT0_R { + TIMING_ERR_VT1_PD_SITE3_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT0_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site3_unit0", + &format_args!("{}", self.monitor_en_vt1_pd_site3_unit0().bit()), + ) + .field( + "delay_limit_vt1_pd_site3_unit0", + &format_args!("{}", self.delay_limit_vt1_pd_site3_unit0().bits()), + ) + .field( + "delay_num_o_vt1_pd_site3_unit0", + &format_args!("{}", self.delay_num_o_vt1_pd_site3_unit0().bits()), + ) + .field( + "timing_err_vt1_pd_site3_unit0", + &format_args!("{}", self.timing_err_vt1_pd_site3_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site3_unit0( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE3_UNIT0_W { + MONITOR_EN_VT1_PD_SITE3_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site3_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site3_unit0( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE3_UNIT0_W { + DELAY_LIMIT_VT1_PD_SITE3_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT0_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT0_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit0_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT0_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit0_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT0_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT0_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT0_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf2.rs new file mode 100644 index 0000000000..c812f5f8ce --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE3_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE3_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site3_unit0(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_R { + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site3_unit0(&self) -> DELAY_OVF_VT1_PD_SITE3_UNIT0_R { + DELAY_OVF_VT1_PD_SITE3_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site3_unit0(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_R { + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT0_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site3_unit0", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site3_unit0().bits()), + ) + .field( + "delay_ovf_vt1_pd_site3_unit0", + &format_args!("{}", self.delay_ovf_vt1_pd_site3_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site3_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site3_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site3_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_W { + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT0_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT0_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit0_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT0_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit0_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT0_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT0_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT0_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf1.rs new file mode 100644 index 0000000000..8b8920ed31 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE3_UNIT0` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE3_UNIT0_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE3_UNIT0` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE3_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE3_UNIT0` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE3_UNIT0_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE3_UNIT0` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE3_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE3_UNIT0` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE3_UNIT0_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE3_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE3_UNIT0_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site3_unit0(&self) -> MONITOR_EN_VT2_PD_SITE3_UNIT0_R { + MONITOR_EN_VT2_PD_SITE3_UNIT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site3_unit0(&self) -> DELAY_LIMIT_VT2_PD_SITE3_UNIT0_R { + DELAY_LIMIT_VT2_PD_SITE3_UNIT0_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site3_unit0(&self) -> DELAY_NUM_O_VT2_PD_SITE3_UNIT0_R { + DELAY_NUM_O_VT2_PD_SITE3_UNIT0_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site3_unit0(&self) -> TIMING_ERR_VT2_PD_SITE3_UNIT0_R { + TIMING_ERR_VT2_PD_SITE3_UNIT0_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT0_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site3_unit0", + &format_args!("{}", self.monitor_en_vt2_pd_site3_unit0().bit()), + ) + .field( + "delay_limit_vt2_pd_site3_unit0", + &format_args!("{}", self.delay_limit_vt2_pd_site3_unit0().bits()), + ) + .field( + "delay_num_o_vt2_pd_site3_unit0", + &format_args!("{}", self.delay_num_o_vt2_pd_site3_unit0().bits()), + ) + .field( + "timing_err_vt2_pd_site3_unit0", + &format_args!("{}", self.timing_err_vt2_pd_site3_unit0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site3_unit0( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE3_UNIT0_W { + MONITOR_EN_VT2_PD_SITE3_UNIT0_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site3_unit0( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site3_unit0( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE3_UNIT0_W { + DELAY_LIMIT_VT2_PD_SITE3_UNIT0_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT0_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT0_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit0_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT0_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit0_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT0_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT0_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT0_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf2.rs new file mode 100644 index 0000000000..193e0d78ba --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT0_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE3_UNIT0` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE3_UNIT0_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site3_unit0(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_R { + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site3_unit0(&self) -> DELAY_OVF_VT2_PD_SITE3_UNIT0_R { + DELAY_OVF_VT2_PD_SITE3_UNIT0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site3_unit0(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_R { + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT0_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site3_unit0", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site3_unit0().bits()), + ) + .field( + "delay_ovf_vt2_pd_site3_unit0", + &format_args!("{}", self.delay_ovf_vt2_pd_site3_unit0().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site3_unit0", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site3_unit0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site3_unit0( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_W { + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit0_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit0_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT0_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT0_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit0_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT0_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit0_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT0_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT0_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT0_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf1.rs new file mode 100644 index 0000000000..12c44100ac --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE3_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE3_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE3_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE3_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE3_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE3_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE3_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE3_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE3_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE3_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE3_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE3_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site3_unit1(&self) -> MONITOR_EN_VT0_PD_SITE3_UNIT1_R { + MONITOR_EN_VT0_PD_SITE3_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site3_unit1(&self) -> DELAY_LIMIT_VT0_PD_SITE3_UNIT1_R { + DELAY_LIMIT_VT0_PD_SITE3_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site3_unit1(&self) -> DELAY_NUM_O_VT0_PD_SITE3_UNIT1_R { + DELAY_NUM_O_VT0_PD_SITE3_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site3_unit1(&self) -> TIMING_ERR_VT0_PD_SITE3_UNIT1_R { + TIMING_ERR_VT0_PD_SITE3_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT1_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site3_unit1", + &format_args!("{}", self.monitor_en_vt0_pd_site3_unit1().bit()), + ) + .field( + "delay_limit_vt0_pd_site3_unit1", + &format_args!("{}", self.delay_limit_vt0_pd_site3_unit1().bits()), + ) + .field( + "delay_num_o_vt0_pd_site3_unit1", + &format_args!("{}", self.delay_num_o_vt0_pd_site3_unit1().bits()), + ) + .field( + "timing_err_vt0_pd_site3_unit1", + &format_args!("{}", self.timing_err_vt0_pd_site3_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site3_unit1( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE3_UNIT1_W { + MONITOR_EN_VT0_PD_SITE3_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site3_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site3_unit1( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE3_UNIT1_W { + DELAY_LIMIT_VT0_PD_SITE3_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT1_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT1_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit1_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT1_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit1_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT1_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT1_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT1_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf2.rs new file mode 100644 index 0000000000..9dbb1fcf6e --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE3_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE3_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site3_unit1(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_R { + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site3_unit1(&self) -> DELAY_OVF_VT0_PD_SITE3_UNIT1_R { + DELAY_OVF_VT0_PD_SITE3_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site3_unit1(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_R { + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT1_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site3_unit1", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site3_unit1().bits()), + ) + .field( + "delay_ovf_vt0_pd_site3_unit1", + &format_args!("{}", self.delay_ovf_vt0_pd_site3_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site3_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site3_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site3_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_W { + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT1_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT1_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit1_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT1_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit1_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT1_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT1_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT1_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf1.rs new file mode 100644 index 0000000000..b9e47fe22d --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE3_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE3_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE3_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE3_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE3_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE3_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE3_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE3_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE3_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE3_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE3_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE3_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site3_unit1(&self) -> MONITOR_EN_VT1_PD_SITE3_UNIT1_R { + MONITOR_EN_VT1_PD_SITE3_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site3_unit1(&self) -> DELAY_LIMIT_VT1_PD_SITE3_UNIT1_R { + DELAY_LIMIT_VT1_PD_SITE3_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site3_unit1(&self) -> DELAY_NUM_O_VT1_PD_SITE3_UNIT1_R { + DELAY_NUM_O_VT1_PD_SITE3_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site3_unit1(&self) -> TIMING_ERR_VT1_PD_SITE3_UNIT1_R { + TIMING_ERR_VT1_PD_SITE3_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT1_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site3_unit1", + &format_args!("{}", self.monitor_en_vt1_pd_site3_unit1().bit()), + ) + .field( + "delay_limit_vt1_pd_site3_unit1", + &format_args!("{}", self.delay_limit_vt1_pd_site3_unit1().bits()), + ) + .field( + "delay_num_o_vt1_pd_site3_unit1", + &format_args!("{}", self.delay_num_o_vt1_pd_site3_unit1().bits()), + ) + .field( + "timing_err_vt1_pd_site3_unit1", + &format_args!("{}", self.timing_err_vt1_pd_site3_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site3_unit1( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE3_UNIT1_W { + MONITOR_EN_VT1_PD_SITE3_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site3_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site3_unit1( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE3_UNIT1_W { + DELAY_LIMIT_VT1_PD_SITE3_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT1_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT1_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit1_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT1_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit1_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT1_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT1_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT1_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf2.rs new file mode 100644 index 0000000000..4ba9cb8c11 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE3_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE3_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site3_unit1(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_R { + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site3_unit1(&self) -> DELAY_OVF_VT1_PD_SITE3_UNIT1_R { + DELAY_OVF_VT1_PD_SITE3_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site3_unit1(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_R { + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT1_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site3_unit1", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site3_unit1().bits()), + ) + .field( + "delay_ovf_vt1_pd_site3_unit1", + &format_args!("{}", self.delay_ovf_vt1_pd_site3_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site3_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site3_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site3_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_W { + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT1_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT1_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit1_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT1_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit1_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT1_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT1_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT1_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf1.rs new file mode 100644 index 0000000000..89568e1757 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE3_UNIT1` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE3_UNIT1_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE3_UNIT1` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE3_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE3_UNIT1` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE3_UNIT1_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE3_UNIT1` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE3_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE3_UNIT1` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE3_UNIT1_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE3_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE3_UNIT1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site3_unit1(&self) -> MONITOR_EN_VT2_PD_SITE3_UNIT1_R { + MONITOR_EN_VT2_PD_SITE3_UNIT1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site3_unit1(&self) -> DELAY_LIMIT_VT2_PD_SITE3_UNIT1_R { + DELAY_LIMIT_VT2_PD_SITE3_UNIT1_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site3_unit1(&self) -> DELAY_NUM_O_VT2_PD_SITE3_UNIT1_R { + DELAY_NUM_O_VT2_PD_SITE3_UNIT1_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site3_unit1(&self) -> TIMING_ERR_VT2_PD_SITE3_UNIT1_R { + TIMING_ERR_VT2_PD_SITE3_UNIT1_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT1_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site3_unit1", + &format_args!("{}", self.monitor_en_vt2_pd_site3_unit1().bit()), + ) + .field( + "delay_limit_vt2_pd_site3_unit1", + &format_args!("{}", self.delay_limit_vt2_pd_site3_unit1().bits()), + ) + .field( + "delay_num_o_vt2_pd_site3_unit1", + &format_args!("{}", self.delay_num_o_vt2_pd_site3_unit1().bits()), + ) + .field( + "timing_err_vt2_pd_site3_unit1", + &format_args!("{}", self.timing_err_vt2_pd_site3_unit1().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site3_unit1( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE3_UNIT1_W { + MONITOR_EN_VT2_PD_SITE3_UNIT1_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site3_unit1( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site3_unit1( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE3_UNIT1_W { + DELAY_LIMIT_VT2_PD_SITE3_UNIT1_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT1_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT1_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit1_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT1_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit1_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT1_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT1_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT1_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf2.rs new file mode 100644 index 0000000000..30547ce4d8 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT1_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE3_UNIT1` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE3_UNIT1_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site3_unit1(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_R { + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site3_unit1(&self) -> DELAY_OVF_VT2_PD_SITE3_UNIT1_R { + DELAY_OVF_VT2_PD_SITE3_UNIT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site3_unit1(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_R { + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT1_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site3_unit1", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site3_unit1().bits()), + ) + .field( + "delay_ovf_vt2_pd_site3_unit1", + &format_args!("{}", self.delay_ovf_vt2_pd_site3_unit1().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site3_unit1", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site3_unit1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site3_unit1( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_W { + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit1_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit1_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT1_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT1_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit1_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT1_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit1_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT1_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT1_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT1_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf1.rs new file mode 100644 index 0000000000..aec06f6f4b --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE3_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE3_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE3_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE3_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE3_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE3_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE3_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE3_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE3_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE3_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE3_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE3_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site3_unit2(&self) -> MONITOR_EN_VT0_PD_SITE3_UNIT2_R { + MONITOR_EN_VT0_PD_SITE3_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site3_unit2(&self) -> DELAY_LIMIT_VT0_PD_SITE3_UNIT2_R { + DELAY_LIMIT_VT0_PD_SITE3_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site3_unit2(&self) -> DELAY_NUM_O_VT0_PD_SITE3_UNIT2_R { + DELAY_NUM_O_VT0_PD_SITE3_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site3_unit2(&self) -> TIMING_ERR_VT0_PD_SITE3_UNIT2_R { + TIMING_ERR_VT0_PD_SITE3_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT2_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site3_unit2", + &format_args!("{}", self.monitor_en_vt0_pd_site3_unit2().bit()), + ) + .field( + "delay_limit_vt0_pd_site3_unit2", + &format_args!("{}", self.delay_limit_vt0_pd_site3_unit2().bits()), + ) + .field( + "delay_num_o_vt0_pd_site3_unit2", + &format_args!("{}", self.delay_num_o_vt0_pd_site3_unit2().bits()), + ) + .field( + "timing_err_vt0_pd_site3_unit2", + &format_args!("{}", self.timing_err_vt0_pd_site3_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site3_unit2( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE3_UNIT2_W { + MONITOR_EN_VT0_PD_SITE3_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site3_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site3_unit2( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE3_UNIT2_W { + DELAY_LIMIT_VT0_PD_SITE3_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT2_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT2_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit2_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT2_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit2_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT2_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT2_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT2_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf2.rs new file mode 100644 index 0000000000..7f62ab87de --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE3_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE3_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site3_unit2(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_R { + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site3_unit2(&self) -> DELAY_OVF_VT0_PD_SITE3_UNIT2_R { + DELAY_OVF_VT0_PD_SITE3_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site3_unit2(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_R { + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT2_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site3_unit2", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site3_unit2().bits()), + ) + .field( + "delay_ovf_vt0_pd_site3_unit2", + &format_args!("{}", self.delay_ovf_vt0_pd_site3_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site3_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site3_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site3_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_W { + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT2_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT2_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit2_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT2_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit2_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT2_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT2_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT2_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf1.rs new file mode 100644 index 0000000000..c3cbc3d479 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE3_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE3_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE3_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE3_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE3_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE3_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE3_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE3_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE3_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE3_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE3_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE3_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site3_unit2(&self) -> MONITOR_EN_VT1_PD_SITE3_UNIT2_R { + MONITOR_EN_VT1_PD_SITE3_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site3_unit2(&self) -> DELAY_LIMIT_VT1_PD_SITE3_UNIT2_R { + DELAY_LIMIT_VT1_PD_SITE3_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site3_unit2(&self) -> DELAY_NUM_O_VT1_PD_SITE3_UNIT2_R { + DELAY_NUM_O_VT1_PD_SITE3_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site3_unit2(&self) -> TIMING_ERR_VT1_PD_SITE3_UNIT2_R { + TIMING_ERR_VT1_PD_SITE3_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT2_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site3_unit2", + &format_args!("{}", self.monitor_en_vt1_pd_site3_unit2().bit()), + ) + .field( + "delay_limit_vt1_pd_site3_unit2", + &format_args!("{}", self.delay_limit_vt1_pd_site3_unit2().bits()), + ) + .field( + "delay_num_o_vt1_pd_site3_unit2", + &format_args!("{}", self.delay_num_o_vt1_pd_site3_unit2().bits()), + ) + .field( + "timing_err_vt1_pd_site3_unit2", + &format_args!("{}", self.timing_err_vt1_pd_site3_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site3_unit2( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE3_UNIT2_W { + MONITOR_EN_VT1_PD_SITE3_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site3_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site3_unit2( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE3_UNIT2_W { + DELAY_LIMIT_VT1_PD_SITE3_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT2_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT2_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit2_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT2_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit2_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT2_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT2_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT2_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf2.rs new file mode 100644 index 0000000000..5dd3222284 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE3_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE3_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site3_unit2(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_R { + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site3_unit2(&self) -> DELAY_OVF_VT1_PD_SITE3_UNIT2_R { + DELAY_OVF_VT1_PD_SITE3_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site3_unit2(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_R { + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT2_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site3_unit2", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site3_unit2().bits()), + ) + .field( + "delay_ovf_vt1_pd_site3_unit2", + &format_args!("{}", self.delay_ovf_vt1_pd_site3_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site3_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site3_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site3_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_W { + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT2_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT2_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit2_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT2_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit2_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT2_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT2_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT2_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf1.rs new file mode 100644 index 0000000000..1933423098 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE3_UNIT2` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE3_UNIT2_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE3_UNIT2` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE3_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE3_UNIT2` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE3_UNIT2_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE3_UNIT2` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE3_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE3_UNIT2` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE3_UNIT2_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE3_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE3_UNIT2_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site3_unit2(&self) -> MONITOR_EN_VT2_PD_SITE3_UNIT2_R { + MONITOR_EN_VT2_PD_SITE3_UNIT2_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site3_unit2(&self) -> DELAY_LIMIT_VT2_PD_SITE3_UNIT2_R { + DELAY_LIMIT_VT2_PD_SITE3_UNIT2_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site3_unit2(&self) -> DELAY_NUM_O_VT2_PD_SITE3_UNIT2_R { + DELAY_NUM_O_VT2_PD_SITE3_UNIT2_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site3_unit2(&self) -> TIMING_ERR_VT2_PD_SITE3_UNIT2_R { + TIMING_ERR_VT2_PD_SITE3_UNIT2_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT2_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site3_unit2", + &format_args!("{}", self.monitor_en_vt2_pd_site3_unit2().bit()), + ) + .field( + "delay_limit_vt2_pd_site3_unit2", + &format_args!("{}", self.delay_limit_vt2_pd_site3_unit2().bits()), + ) + .field( + "delay_num_o_vt2_pd_site3_unit2", + &format_args!("{}", self.delay_num_o_vt2_pd_site3_unit2().bits()), + ) + .field( + "timing_err_vt2_pd_site3_unit2", + &format_args!("{}", self.timing_err_vt2_pd_site3_unit2().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site3_unit2( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE3_UNIT2_W { + MONITOR_EN_VT2_PD_SITE3_UNIT2_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site3_unit2( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site3_unit2( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE3_UNIT2_W { + DELAY_LIMIT_VT2_PD_SITE3_UNIT2_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT2_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT2_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit2_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT2_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit2_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT2_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT2_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT2_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf2.rs new file mode 100644 index 0000000000..a92fb89e60 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT2_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE3_UNIT2` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE3_UNIT2_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site3_unit2(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_R { + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site3_unit2(&self) -> DELAY_OVF_VT2_PD_SITE3_UNIT2_R { + DELAY_OVF_VT2_PD_SITE3_UNIT2_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site3_unit2(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_R { + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT2_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site3_unit2", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site3_unit2().bits()), + ) + .field( + "delay_ovf_vt2_pd_site3_unit2", + &format_args!("{}", self.delay_ovf_vt2_pd_site3_unit2().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site3_unit2", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site3_unit2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site3_unit2( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_W { + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit2_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit2_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT2_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT2_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit2_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT2_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit2_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT2_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT2_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT2_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf1.rs new file mode 100644 index 0000000000..de4ab035cc --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT0_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT0_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE3_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE3_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT0_PD_SITE3_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT0_PD_SITE3_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE3_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE3_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT0_PD_SITE3_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT0_PD_SITE3_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT0_PD_SITE3_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT0_PD_SITE3_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT0_PD_SITE3_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT0_PD_SITE3_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt0_pd_site3_unit3(&self) -> MONITOR_EN_VT0_PD_SITE3_UNIT3_R { + MONITOR_EN_VT0_PD_SITE3_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt0_pd_site3_unit3(&self) -> DELAY_LIMIT_VT0_PD_SITE3_UNIT3_R { + DELAY_LIMIT_VT0_PD_SITE3_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt0_pd_site3_unit3(&self) -> DELAY_NUM_O_VT0_PD_SITE3_UNIT3_R { + DELAY_NUM_O_VT0_PD_SITE3_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt0_pd_site3_unit3(&self) -> TIMING_ERR_VT0_PD_SITE3_UNIT3_R { + TIMING_ERR_VT0_PD_SITE3_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT3_VT0_CONF1") + .field( + "monitor_en_vt0_pd_site3_unit3", + &format_args!("{}", self.monitor_en_vt0_pd_site3_unit3().bit()), + ) + .field( + "delay_limit_vt0_pd_site3_unit3", + &format_args!("{}", self.delay_limit_vt0_pd_site3_unit3().bits()), + ) + .field( + "delay_num_o_vt0_pd_site3_unit3", + &format_args!("{}", self.delay_num_o_vt0_pd_site3_unit3().bits()), + ) + .field( + "timing_err_vt0_pd_site3_unit3", + &format_args!("{}", self.timing_err_vt0_pd_site3_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt0_pd_site3_unit3( + &mut self, + ) -> MONITOR_EN_VT0_PD_SITE3_UNIT3_W { + MONITOR_EN_VT0_PD_SITE3_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt0_pd_site3_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_W { + TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt0_pd_site3_unit3( + &mut self, + ) -> DELAY_LIMIT_VT0_PD_SITE3_UNIT3_W { + DELAY_LIMIT_VT0_PD_SITE3_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt0_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt0_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT3_VT0_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT3_VT0_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit3_vt0_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT3_VT0_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit3_vt0_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT3_VT0_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT3_VT0_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT3_VT0_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf2.rs new file mode 100644 index 0000000000..f848a67143 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT0_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT0_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT0_PD_SITE3_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT0_PD_SITE3_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt0_pd_site3_unit3(&self) -> MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_R { + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt0_pd_site3_unit3(&self) -> DELAY_OVF_VT0_PD_SITE3_UNIT3_R { + DELAY_OVF_VT0_PD_SITE3_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt0_pd_site3_unit3(&self) -> TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_R { + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT3_VT0_CONF2") + .field( + "monitor_edg_mod_vt0_pd_site3_unit3", + &format_args!("{}", self.monitor_edg_mod_vt0_pd_site3_unit3().bits()), + ) + .field( + "delay_ovf_vt0_pd_site3_unit3", + &format_args!("{}", self.delay_ovf_vt0_pd_site3_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt0_pd_site3_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site3_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt0_pd_site3_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_W { + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt0_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt0_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT3_VT0_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT3_VT0_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit3_vt0_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT3_VT0_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit3_vt0_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT3_VT0_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT3_VT0_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT3_VT0_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf1.rs new file mode 100644 index 0000000000..b9a970c522 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT1_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT1_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE3_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE3_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT1_PD_SITE3_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT1_PD_SITE3_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE3_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE3_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT1_PD_SITE3_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT1_PD_SITE3_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT1_PD_SITE3_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT1_PD_SITE3_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT1_PD_SITE3_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT1_PD_SITE3_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt1_pd_site3_unit3(&self) -> MONITOR_EN_VT1_PD_SITE3_UNIT3_R { + MONITOR_EN_VT1_PD_SITE3_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt1_pd_site3_unit3(&self) -> DELAY_LIMIT_VT1_PD_SITE3_UNIT3_R { + DELAY_LIMIT_VT1_PD_SITE3_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt1_pd_site3_unit3(&self) -> DELAY_NUM_O_VT1_PD_SITE3_UNIT3_R { + DELAY_NUM_O_VT1_PD_SITE3_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt1_pd_site3_unit3(&self) -> TIMING_ERR_VT1_PD_SITE3_UNIT3_R { + TIMING_ERR_VT1_PD_SITE3_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT3_VT1_CONF1") + .field( + "monitor_en_vt1_pd_site3_unit3", + &format_args!("{}", self.monitor_en_vt1_pd_site3_unit3().bit()), + ) + .field( + "delay_limit_vt1_pd_site3_unit3", + &format_args!("{}", self.delay_limit_vt1_pd_site3_unit3().bits()), + ) + .field( + "delay_num_o_vt1_pd_site3_unit3", + &format_args!("{}", self.delay_num_o_vt1_pd_site3_unit3().bits()), + ) + .field( + "timing_err_vt1_pd_site3_unit3", + &format_args!("{}", self.timing_err_vt1_pd_site3_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt1_pd_site3_unit3( + &mut self, + ) -> MONITOR_EN_VT1_PD_SITE3_UNIT3_W { + MONITOR_EN_VT1_PD_SITE3_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt1_pd_site3_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_W { + TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt1_pd_site3_unit3( + &mut self, + ) -> DELAY_LIMIT_VT1_PD_SITE3_UNIT3_W { + DELAY_LIMIT_VT1_PD_SITE3_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt1_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt1_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT3_VT1_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT3_VT1_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit3_vt1_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT3_VT1_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit3_vt1_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT3_VT1_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT3_VT1_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT3_VT1_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf2.rs new file mode 100644 index 0000000000..329f654f7f --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT1_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT1_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT1_PD_SITE3_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT1_PD_SITE3_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt1_pd_site3_unit3(&self) -> MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_R { + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt1_pd_site3_unit3(&self) -> DELAY_OVF_VT1_PD_SITE3_UNIT3_R { + DELAY_OVF_VT1_PD_SITE3_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt1_pd_site3_unit3(&self) -> TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_R { + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT3_VT1_CONF2") + .field( + "monitor_edg_mod_vt1_pd_site3_unit3", + &format_args!("{}", self.monitor_edg_mod_vt1_pd_site3_unit3().bits()), + ) + .field( + "delay_ovf_vt1_pd_site3_unit3", + &format_args!("{}", self.delay_ovf_vt1_pd_site3_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt1_pd_site3_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site3_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt1_pd_site3_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_W { + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt1_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt1_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT3_VT1_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT3_VT1_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit3_vt1_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT3_VT1_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit3_vt1_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT3_VT1_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT3_VT1_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT3_VT1_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf1.rs new file mode 100644 index 0000000000..105bea2113 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf1.rs @@ -0,0 +1,121 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT2_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT2_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE3_UNIT3` reader - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE3_UNIT3_R = crate::BitReader; +#[doc = "Field `MONITOR_EN_VT2_PD_SITE3_UNIT3` writer - needs field desc"] +pub type MONITOR_EN_VT2_PD_SITE3_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3` writer - needs field desc"] +pub type TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE3_UNIT3` reader - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE3_UNIT3_R = crate::FieldReader; +#[doc = "Field `DELAY_LIMIT_VT2_PD_SITE3_UNIT3` writer - needs field desc"] +pub type DELAY_LIMIT_VT2_PD_SITE3_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DELAY_NUM_O_VT2_PD_SITE3_UNIT3` reader - needs field desc"] +pub type DELAY_NUM_O_VT2_PD_SITE3_UNIT3_R = crate::FieldReader; +#[doc = "Field `TIMING_ERR_VT2_PD_SITE3_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_VT2_PD_SITE3_UNIT3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + pub fn monitor_en_vt2_pd_site3_unit3(&self) -> MONITOR_EN_VT2_PD_SITE3_UNIT3_R { + MONITOR_EN_VT2_PD_SITE3_UNIT3_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + pub fn delay_limit_vt2_pd_site3_unit3(&self) -> DELAY_LIMIT_VT2_PD_SITE3_UNIT3_R { + DELAY_LIMIT_VT2_PD_SITE3_UNIT3_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bits 23:30 - needs field desc"] + #[inline(always)] + pub fn delay_num_o_vt2_pd_site3_unit3(&self) -> DELAY_NUM_O_VT2_PD_SITE3_UNIT3_R { + DELAY_NUM_O_VT2_PD_SITE3_UNIT3_R::new(((self.bits >> 23) & 0xff) as u8) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timing_err_vt2_pd_site3_unit3(&self) -> TIMING_ERR_VT2_PD_SITE3_UNIT3_R { + TIMING_ERR_VT2_PD_SITE3_UNIT3_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT3_VT2_CONF1") + .field( + "monitor_en_vt2_pd_site3_unit3", + &format_args!("{}", self.monitor_en_vt2_pd_site3_unit3().bit()), + ) + .field( + "delay_limit_vt2_pd_site3_unit3", + &format_args!("{}", self.delay_limit_vt2_pd_site3_unit3().bits()), + ) + .field( + "delay_num_o_vt2_pd_site3_unit3", + &format_args!("{}", self.delay_num_o_vt2_pd_site3_unit3().bits()), + ) + .field( + "timing_err_vt2_pd_site3_unit3", + &format_args!("{}", self.timing_err_vt2_pd_site3_unit3().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_en_vt2_pd_site3_unit3( + &mut self, + ) -> MONITOR_EN_VT2_PD_SITE3_UNIT3_W { + MONITOR_EN_VT2_PD_SITE3_UNIT3_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timing_err_cnt_clr_vt2_pd_site3_unit3( + &mut self, + ) -> TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_W { + TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_W::new(self, 1) + } + #[doc = "Bits 2:9 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn delay_limit_vt2_pd_site3_unit3( + &mut self, + ) -> DELAY_LIMIT_VT2_PD_SITE3_UNIT3_W { + DELAY_LIMIT_VT2_PD_SITE3_UNIT3_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt2_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt2_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT3_VT2_CONF1_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT3_VT2_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit3_vt2_conf1::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT3_VT2_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit3_vt2_conf1::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT3_VT2_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT3_VT2_CONF1 to value 0x50"] +impl crate::Resettable for COMB_PD_SITE3_UNIT3_VT2_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x50; +} diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf2.rs new file mode 100644 index 0000000000..487f325b32 --- /dev/null +++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf2.rs @@ -0,0 +1,90 @@ +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT2_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `COMB_PD_SITE3_UNIT3_VT2_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3` reader - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_R = crate::FieldReader; +#[doc = "Field `MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3` writer - needs field desc"] +pub type MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DELAY_OVF_VT2_PD_SITE3_UNIT3` reader - needs field desc"] +pub type DELAY_OVF_VT2_PD_SITE3_UNIT3_R = crate::BitReader; +#[doc = "Field `TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3` reader - needs field desc"] +pub type TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + pub fn monitor_edg_mod_vt2_pd_site3_unit3(&self) -> MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_R { + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 15 - needs field desc"] + #[inline(always)] + pub fn delay_ovf_vt2_pd_site3_unit3(&self) -> DELAY_OVF_VT2_PD_SITE3_UNIT3_R { + DELAY_OVF_VT2_PD_SITE3_UNIT3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - needs field desc"] + #[inline(always)] + pub fn timing_err_cnt_o_vt2_pd_site3_unit3(&self) -> TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_R { + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("COMB_PD_SITE3_UNIT3_VT2_CONF2") + .field( + "monitor_edg_mod_vt2_pd_site3_unit3", + &format_args!("{}", self.monitor_edg_mod_vt2_pd_site3_unit3().bits()), + ) + .field( + "delay_ovf_vt2_pd_site3_unit3", + &format_args!("{}", self.delay_ovf_vt2_pd_site3_unit3().bit()), + ) + .field( + "timing_err_cnt_o_vt2_pd_site3_unit3", + &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site3_unit3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn monitor_edg_mod_vt2_pd_site3_unit3( + &mut self, + ) -> MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_W { + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pd_site3_unit3_vt2_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comb_pd_site3_unit3_vt2_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMB_PD_SITE3_UNIT3_VT2_CONF2_SPEC; +impl crate::RegisterSpec for COMB_PD_SITE3_UNIT3_VT2_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`comb_pd_site3_unit3_vt2_conf2::R`](R) reader structure"] +impl crate::Readable for COMB_PD_SITE3_UNIT3_VT2_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`comb_pd_site3_unit3_vt2_conf2::W`](W) writer structure"] +impl crate::Writable for COMB_PD_SITE3_UNIT3_VT2_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMB_PD_SITE3_UNIT3_VT2_CONF2 to value 0"] +impl crate::Resettable for COMB_PD_SITE3_UNIT3_VT2_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/date.rs b/esp32p4/src/pvt/date.rs new file mode 100644 index 0000000000..a3adfd79ac --- /dev/null +++ b/esp32p4/src/pvt/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - version register"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - version register"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - version register"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - version register"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0211_2130"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0211_2130; +} diff --git a/esp32p4/src/pvt/dbias_channel0_sel.rs b/esp32p4/src/pvt/dbias_channel0_sel.rs new file mode 100644 index 0000000000..aea0d35b41 --- /dev/null +++ b/esp32p4/src/pvt/dbias_channel0_sel.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DBIAS_CHANNEL0_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CHANNEL0_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CHANNEL0_CFG` reader - needs field desc"] +pub type DBIAS_CHANNEL0_CFG_R = crate::FieldReader; +#[doc = "Field `DBIAS_CHANNEL0_CFG` writer - needs field desc"] +pub type DBIAS_CHANNEL0_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + pub fn dbias_channel0_cfg(&self) -> DBIAS_CHANNEL0_CFG_R { + DBIAS_CHANNEL0_CFG_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CHANNEL0_SEL") + .field( + "dbias_channel0_cfg", + &format_args!("{}", self.dbias_channel0_cfg().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_channel0_cfg(&mut self) -> DBIAS_CHANNEL0_CFG_W { + DBIAS_CHANNEL0_CFG_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel0_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel0_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CHANNEL0_SEL_SPEC; +impl crate::RegisterSpec for DBIAS_CHANNEL0_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_channel0_sel::R`](R) reader structure"] +impl crate::Readable for DBIAS_CHANNEL0_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_channel0_sel::W`](W) writer structure"] +impl crate::Writable for DBIAS_CHANNEL0_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CHANNEL0_SEL to value 0"] +impl crate::Resettable for DBIAS_CHANNEL0_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/dbias_channel1_sel.rs b/esp32p4/src/pvt/dbias_channel1_sel.rs new file mode 100644 index 0000000000..b08f00f93e --- /dev/null +++ b/esp32p4/src/pvt/dbias_channel1_sel.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DBIAS_CHANNEL1_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CHANNEL1_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CHANNEL1_CFG` reader - needs field desc"] +pub type DBIAS_CHANNEL1_CFG_R = crate::FieldReader; +#[doc = "Field `DBIAS_CHANNEL1_CFG` writer - needs field desc"] +pub type DBIAS_CHANNEL1_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + pub fn dbias_channel1_cfg(&self) -> DBIAS_CHANNEL1_CFG_R { + DBIAS_CHANNEL1_CFG_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CHANNEL1_SEL") + .field( + "dbias_channel1_cfg", + &format_args!("{}", self.dbias_channel1_cfg().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_channel1_cfg(&mut self) -> DBIAS_CHANNEL1_CFG_W { + DBIAS_CHANNEL1_CFG_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel1_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel1_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CHANNEL1_SEL_SPEC; +impl crate::RegisterSpec for DBIAS_CHANNEL1_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_channel1_sel::R`](R) reader structure"] +impl crate::Readable for DBIAS_CHANNEL1_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_channel1_sel::W`](W) writer structure"] +impl crate::Writable for DBIAS_CHANNEL1_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CHANNEL1_SEL to value 0"] +impl crate::Resettable for DBIAS_CHANNEL1_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/dbias_channel2_sel.rs b/esp32p4/src/pvt/dbias_channel2_sel.rs new file mode 100644 index 0000000000..0a9cd76212 --- /dev/null +++ b/esp32p4/src/pvt/dbias_channel2_sel.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DBIAS_CHANNEL2_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CHANNEL2_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CHANNEL2_CFG` reader - needs field desc"] +pub type DBIAS_CHANNEL2_CFG_R = crate::FieldReader; +#[doc = "Field `DBIAS_CHANNEL2_CFG` writer - needs field desc"] +pub type DBIAS_CHANNEL2_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + pub fn dbias_channel2_cfg(&self) -> DBIAS_CHANNEL2_CFG_R { + DBIAS_CHANNEL2_CFG_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CHANNEL2_SEL") + .field( + "dbias_channel2_cfg", + &format_args!("{}", self.dbias_channel2_cfg().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_channel2_cfg(&mut self) -> DBIAS_CHANNEL2_CFG_W { + DBIAS_CHANNEL2_CFG_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel2_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel2_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CHANNEL2_SEL_SPEC; +impl crate::RegisterSpec for DBIAS_CHANNEL2_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_channel2_sel::R`](R) reader structure"] +impl crate::Readable for DBIAS_CHANNEL2_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_channel2_sel::W`](W) writer structure"] +impl crate::Writable for DBIAS_CHANNEL2_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CHANNEL2_SEL to value 0"] +impl crate::Resettable for DBIAS_CHANNEL2_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/dbias_channel3_sel.rs b/esp32p4/src/pvt/dbias_channel3_sel.rs new file mode 100644 index 0000000000..cc64605247 --- /dev/null +++ b/esp32p4/src/pvt/dbias_channel3_sel.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DBIAS_CHANNEL3_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CHANNEL3_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CHANNEL3_CFG` reader - needs field desc"] +pub type DBIAS_CHANNEL3_CFG_R = crate::FieldReader; +#[doc = "Field `DBIAS_CHANNEL3_CFG` writer - needs field desc"] +pub type DBIAS_CHANNEL3_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + pub fn dbias_channel3_cfg(&self) -> DBIAS_CHANNEL3_CFG_R { + DBIAS_CHANNEL3_CFG_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CHANNEL3_SEL") + .field( + "dbias_channel3_cfg", + &format_args!("{}", self.dbias_channel3_cfg().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_channel3_cfg(&mut self) -> DBIAS_CHANNEL3_CFG_W { + DBIAS_CHANNEL3_CFG_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel3_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel3_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CHANNEL3_SEL_SPEC; +impl crate::RegisterSpec for DBIAS_CHANNEL3_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_channel3_sel::R`](R) reader structure"] +impl crate::Readable for DBIAS_CHANNEL3_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_channel3_sel::W`](W) writer structure"] +impl crate::Writable for DBIAS_CHANNEL3_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CHANNEL3_SEL to value 0"] +impl crate::Resettable for DBIAS_CHANNEL3_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/dbias_channel4_sel.rs b/esp32p4/src/pvt/dbias_channel4_sel.rs new file mode 100644 index 0000000000..f7abe562ba --- /dev/null +++ b/esp32p4/src/pvt/dbias_channel4_sel.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DBIAS_CHANNEL4_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CHANNEL4_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CHANNEL4_CFG` reader - needs field desc"] +pub type DBIAS_CHANNEL4_CFG_R = crate::FieldReader; +#[doc = "Field `DBIAS_CHANNEL4_CFG` writer - needs field desc"] +pub type DBIAS_CHANNEL4_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + pub fn dbias_channel4_cfg(&self) -> DBIAS_CHANNEL4_CFG_R { + DBIAS_CHANNEL4_CFG_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CHANNEL4_SEL") + .field( + "dbias_channel4_cfg", + &format_args!("{}", self.dbias_channel4_cfg().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_channel4_cfg(&mut self) -> DBIAS_CHANNEL4_CFG_W { + DBIAS_CHANNEL4_CFG_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel4_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel4_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CHANNEL4_SEL_SPEC; +impl crate::RegisterSpec for DBIAS_CHANNEL4_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_channel4_sel::R`](R) reader structure"] +impl crate::Readable for DBIAS_CHANNEL4_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_channel4_sel::W`](W) writer structure"] +impl crate::Writable for DBIAS_CHANNEL4_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CHANNEL4_SEL to value 0"] +impl crate::Resettable for DBIAS_CHANNEL4_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/dbias_channel_sel0.rs b/esp32p4/src/pvt/dbias_channel_sel0.rs new file mode 100644 index 0000000000..4bbd44bb1a --- /dev/null +++ b/esp32p4/src/pvt/dbias_channel_sel0.rs @@ -0,0 +1,123 @@ +#[doc = "Register `DBIAS_CHANNEL_SEL0` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CHANNEL_SEL0` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CHANNEL3_SEL` reader - needs field desc"] +pub type DBIAS_CHANNEL3_SEL_R = crate::FieldReader; +#[doc = "Field `DBIAS_CHANNEL3_SEL` writer - needs field desc"] +pub type DBIAS_CHANNEL3_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `DBIAS_CHANNEL2_SEL` reader - needs field desc"] +pub type DBIAS_CHANNEL2_SEL_R = crate::FieldReader; +#[doc = "Field `DBIAS_CHANNEL2_SEL` writer - needs field desc"] +pub type DBIAS_CHANNEL2_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `DBIAS_CHANNEL1_SEL` reader - needs field desc"] +pub type DBIAS_CHANNEL1_SEL_R = crate::FieldReader; +#[doc = "Field `DBIAS_CHANNEL1_SEL` writer - needs field desc"] +pub type DBIAS_CHANNEL1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `DBIAS_CHANNEL0_SEL` reader - needs field desc"] +pub type DBIAS_CHANNEL0_SEL_R = crate::FieldReader; +#[doc = "Field `DBIAS_CHANNEL0_SEL` writer - needs field desc"] +pub type DBIAS_CHANNEL0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 4:10 - needs field desc"] + #[inline(always)] + pub fn dbias_channel3_sel(&self) -> DBIAS_CHANNEL3_SEL_R { + DBIAS_CHANNEL3_SEL_R::new(((self.bits >> 4) & 0x7f) as u8) + } + #[doc = "Bits 11:17 - needs field desc"] + #[inline(always)] + pub fn dbias_channel2_sel(&self) -> DBIAS_CHANNEL2_SEL_R { + DBIAS_CHANNEL2_SEL_R::new(((self.bits >> 11) & 0x7f) as u8) + } + #[doc = "Bits 18:24 - needs field desc"] + #[inline(always)] + pub fn dbias_channel1_sel(&self) -> DBIAS_CHANNEL1_SEL_R { + DBIAS_CHANNEL1_SEL_R::new(((self.bits >> 18) & 0x7f) as u8) + } + #[doc = "Bits 25:31 - needs field desc"] + #[inline(always)] + pub fn dbias_channel0_sel(&self) -> DBIAS_CHANNEL0_SEL_R { + DBIAS_CHANNEL0_SEL_R::new(((self.bits >> 25) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CHANNEL_SEL0") + .field( + "dbias_channel3_sel", + &format_args!("{}", self.dbias_channel3_sel().bits()), + ) + .field( + "dbias_channel2_sel", + &format_args!("{}", self.dbias_channel2_sel().bits()), + ) + .field( + "dbias_channel1_sel", + &format_args!("{}", self.dbias_channel1_sel().bits()), + ) + .field( + "dbias_channel0_sel", + &format_args!("{}", self.dbias_channel0_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 4:10 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_channel3_sel(&mut self) -> DBIAS_CHANNEL3_SEL_W { + DBIAS_CHANNEL3_SEL_W::new(self, 4) + } + #[doc = "Bits 11:17 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_channel2_sel(&mut self) -> DBIAS_CHANNEL2_SEL_W { + DBIAS_CHANNEL2_SEL_W::new(self, 11) + } + #[doc = "Bits 18:24 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_channel1_sel(&mut self) -> DBIAS_CHANNEL1_SEL_W { + DBIAS_CHANNEL1_SEL_W::new(self, 18) + } + #[doc = "Bits 25:31 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_channel0_sel(&mut self) -> DBIAS_CHANNEL0_SEL_W { + DBIAS_CHANNEL0_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel_sel0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel_sel0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CHANNEL_SEL0_SPEC; +impl crate::RegisterSpec for DBIAS_CHANNEL_SEL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_channel_sel0::R`](R) reader structure"] +impl crate::Readable for DBIAS_CHANNEL_SEL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_channel_sel0::W`](W) writer structure"] +impl crate::Writable for DBIAS_CHANNEL_SEL0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CHANNEL_SEL0 to value 0x8102_0400"] +impl crate::Resettable for DBIAS_CHANNEL_SEL0_SPEC { + const RESET_VALUE: Self::Ux = 0x8102_0400; +} diff --git a/esp32p4/src/pvt/dbias_channel_sel1.rs b/esp32p4/src/pvt/dbias_channel_sel1.rs new file mode 100644 index 0000000000..fc29ee4930 --- /dev/null +++ b/esp32p4/src/pvt/dbias_channel_sel1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DBIAS_CHANNEL_SEL1` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CHANNEL_SEL1` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CHANNEL4_SEL` reader - needs field desc"] +pub type DBIAS_CHANNEL4_SEL_R = crate::FieldReader; +#[doc = "Field `DBIAS_CHANNEL4_SEL` writer - needs field desc"] +pub type DBIAS_CHANNEL4_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 25:31 - needs field desc"] + #[inline(always)] + pub fn dbias_channel4_sel(&self) -> DBIAS_CHANNEL4_SEL_R { + DBIAS_CHANNEL4_SEL_R::new(((self.bits >> 25) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CHANNEL_SEL1") + .field( + "dbias_channel4_sel", + &format_args!("{}", self.dbias_channel4_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 25:31 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_channel4_sel(&mut self) -> DBIAS_CHANNEL4_SEL_W { + DBIAS_CHANNEL4_SEL_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_channel_sel1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_channel_sel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CHANNEL_SEL1_SPEC; +impl crate::RegisterSpec for DBIAS_CHANNEL_SEL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_channel_sel1::R`](R) reader structure"] +impl crate::Readable for DBIAS_CHANNEL_SEL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_channel_sel1::W`](W) writer structure"] +impl crate::Writable for DBIAS_CHANNEL_SEL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CHANNEL_SEL1 to value 0x8000_0000"] +impl crate::Resettable for DBIAS_CHANNEL_SEL1_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_0000; +} diff --git a/esp32p4/src/pvt/dbias_cmd0.rs b/esp32p4/src/pvt/dbias_cmd0.rs new file mode 100644 index 0000000000..34269bf09f --- /dev/null +++ b/esp32p4/src/pvt/dbias_cmd0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DBIAS_CMD0` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CMD0` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CMD0` reader - needs field desc"] +pub type DBIAS_CMD0_R = crate::FieldReader; +#[doc = "Field `DBIAS_CMD0` writer - needs field desc"] +pub type DBIAS_CMD0_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + pub fn dbias_cmd0(&self) -> DBIAS_CMD0_R { + DBIAS_CMD0_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CMD0") + .field("dbias_cmd0", &format_args!("{}", self.dbias_cmd0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_cmd0(&mut self) -> DBIAS_CMD0_W { + DBIAS_CMD0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_cmd0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_cmd0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CMD0_SPEC; +impl crate::RegisterSpec for DBIAS_CMD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_cmd0::R`](R) reader structure"] +impl crate::Readable for DBIAS_CMD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_cmd0::W`](W) writer structure"] +impl crate::Writable for DBIAS_CMD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CMD0 to value 0"] +impl crate::Resettable for DBIAS_CMD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/dbias_cmd1.rs b/esp32p4/src/pvt/dbias_cmd1.rs new file mode 100644 index 0000000000..1bd688f377 --- /dev/null +++ b/esp32p4/src/pvt/dbias_cmd1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DBIAS_CMD1` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CMD1` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CMD1` reader - needs field desc"] +pub type DBIAS_CMD1_R = crate::FieldReader; +#[doc = "Field `DBIAS_CMD1` writer - needs field desc"] +pub type DBIAS_CMD1_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + pub fn dbias_cmd1(&self) -> DBIAS_CMD1_R { + DBIAS_CMD1_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CMD1") + .field("dbias_cmd1", &format_args!("{}", self.dbias_cmd1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_cmd1(&mut self) -> DBIAS_CMD1_W { + DBIAS_CMD1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_cmd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_cmd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CMD1_SPEC; +impl crate::RegisterSpec for DBIAS_CMD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_cmd1::R`](R) reader structure"] +impl crate::Readable for DBIAS_CMD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_cmd1::W`](W) writer structure"] +impl crate::Writable for DBIAS_CMD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CMD1 to value 0"] +impl crate::Resettable for DBIAS_CMD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/dbias_cmd2.rs b/esp32p4/src/pvt/dbias_cmd2.rs new file mode 100644 index 0000000000..5c59f3aba9 --- /dev/null +++ b/esp32p4/src/pvt/dbias_cmd2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DBIAS_CMD2` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CMD2` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CMD2` reader - needs field desc"] +pub type DBIAS_CMD2_R = crate::FieldReader; +#[doc = "Field `DBIAS_CMD2` writer - needs field desc"] +pub type DBIAS_CMD2_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + pub fn dbias_cmd2(&self) -> DBIAS_CMD2_R { + DBIAS_CMD2_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CMD2") + .field("dbias_cmd2", &format_args!("{}", self.dbias_cmd2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_cmd2(&mut self) -> DBIAS_CMD2_W { + DBIAS_CMD2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_cmd2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_cmd2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CMD2_SPEC; +impl crate::RegisterSpec for DBIAS_CMD2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_cmd2::R`](R) reader structure"] +impl crate::Readable for DBIAS_CMD2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_cmd2::W`](W) writer structure"] +impl crate::Writable for DBIAS_CMD2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CMD2 to value 0"] +impl crate::Resettable for DBIAS_CMD2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/dbias_cmd3.rs b/esp32p4/src/pvt/dbias_cmd3.rs new file mode 100644 index 0000000000..d42a42870f --- /dev/null +++ b/esp32p4/src/pvt/dbias_cmd3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DBIAS_CMD3` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CMD3` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CMD3` reader - needs field desc"] +pub type DBIAS_CMD3_R = crate::FieldReader; +#[doc = "Field `DBIAS_CMD3` writer - needs field desc"] +pub type DBIAS_CMD3_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + pub fn dbias_cmd3(&self) -> DBIAS_CMD3_R { + DBIAS_CMD3_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CMD3") + .field("dbias_cmd3", &format_args!("{}", self.dbias_cmd3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_cmd3(&mut self) -> DBIAS_CMD3_W { + DBIAS_CMD3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_cmd3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_cmd3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CMD3_SPEC; +impl crate::RegisterSpec for DBIAS_CMD3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_cmd3::R`](R) reader structure"] +impl crate::Readable for DBIAS_CMD3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_cmd3::W`](W) writer structure"] +impl crate::Writable for DBIAS_CMD3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CMD3 to value 0"] +impl crate::Resettable for DBIAS_CMD3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/dbias_cmd4.rs b/esp32p4/src/pvt/dbias_cmd4.rs new file mode 100644 index 0000000000..00614e20b3 --- /dev/null +++ b/esp32p4/src/pvt/dbias_cmd4.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DBIAS_CMD4` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_CMD4` writer"] +pub type W = crate::W; +#[doc = "Field `DBIAS_CMD4` reader - needs field desc"] +pub type DBIAS_CMD4_R = crate::FieldReader; +#[doc = "Field `DBIAS_CMD4` writer - needs field desc"] +pub type DBIAS_CMD4_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + pub fn dbias_cmd4(&self) -> DBIAS_CMD4_R { + DBIAS_CMD4_R::new(self.bits & 0x0001_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_CMD4") + .field("dbias_cmd4", &format_args!("{}", self.dbias_cmd4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:16 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn dbias_cmd4(&mut self) -> DBIAS_CMD4_W { + DBIAS_CMD4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_cmd4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_cmd4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_CMD4_SPEC; +impl crate::RegisterSpec for DBIAS_CMD4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_cmd4::R`](R) reader structure"] +impl crate::Readable for DBIAS_CMD4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_cmd4::W`](W) writer structure"] +impl crate::Writable for DBIAS_CMD4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_CMD4 to value 0"] +impl crate::Resettable for DBIAS_CMD4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/dbias_timer.rs b/esp32p4/src/pvt/dbias_timer.rs new file mode 100644 index 0000000000..2bae6f7508 --- /dev/null +++ b/esp32p4/src/pvt/dbias_timer.rs @@ -0,0 +1,82 @@ +#[doc = "Register `DBIAS_TIMER` reader"] +pub type R = crate::R; +#[doc = "Register `DBIAS_TIMER` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_TARGET` reader - needs field desc"] +pub type TIMER_TARGET_R = crate::FieldReader; +#[doc = "Field `TIMER_TARGET` writer - needs field desc"] +pub type TIMER_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `TIMER_EN` reader - needs field desc"] +pub type TIMER_EN_R = crate::BitReader; +#[doc = "Field `TIMER_EN` writer - needs field desc"] +pub type TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 15:30 - needs field desc"] + #[inline(always)] + pub fn timer_target(&self) -> TIMER_TARGET_R { + TIMER_TARGET_R::new(((self.bits >> 15) & 0xffff) as u16) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + pub fn timer_en(&self) -> TIMER_EN_R { + TIMER_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBIAS_TIMER") + .field( + "timer_target", + &format_args!("{}", self.timer_target().bits()), + ) + .field("timer_en", &format_args!("{}", self.timer_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 15:30 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timer_target(&mut self) -> TIMER_TARGET_W { + TIMER_TARGET_W::new(self, 15) + } + #[doc = "Bit 31 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn timer_en(&mut self) -> TIMER_EN_W { + TIMER_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbias_timer::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbias_timer::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBIAS_TIMER_SPEC; +impl crate::RegisterSpec for DBIAS_TIMER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbias_timer::R`](R) reader structure"] +impl crate::Readable for DBIAS_TIMER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbias_timer::W`](W) writer structure"] +impl crate::Writable for DBIAS_TIMER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBIAS_TIMER to value 0x7fff_8000"] +impl crate::Resettable for DBIAS_TIMER_SPEC { + const RESET_VALUE: Self::Ux = 0x7fff_8000; +} diff --git a/esp32p4/src/pvt/pmup_bitmap_high0.rs b/esp32p4/src/pvt/pmup_bitmap_high0.rs new file mode 100644 index 0000000000..233b02c323 --- /dev/null +++ b/esp32p4/src/pvt/pmup_bitmap_high0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMUP_BITMAP_HIGH0` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_BITMAP_HIGH0` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_BITMAP_HIGH0` reader - select valid high channel0"] +pub type PUMP_BITMAP_HIGH0_R = crate::FieldReader; +#[doc = "Field `PUMP_BITMAP_HIGH0` writer - select valid high channel0"] +pub type PUMP_BITMAP_HIGH0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - select valid high channel0"] + #[inline(always)] + pub fn pump_bitmap_high0(&self) -> PUMP_BITMAP_HIGH0_R { + PUMP_BITMAP_HIGH0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_BITMAP_HIGH0") + .field( + "pump_bitmap_high0", + &format_args!("{}", self.pump_bitmap_high0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - select valid high channel0"] + #[inline(always)] + #[must_use] + pub fn pump_bitmap_high0(&mut self) -> PUMP_BITMAP_HIGH0_W { + PUMP_BITMAP_HIGH0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_high0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_high0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_BITMAP_HIGH0_SPEC; +impl crate::RegisterSpec for PMUP_BITMAP_HIGH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_bitmap_high0::R`](R) reader structure"] +impl crate::Readable for PMUP_BITMAP_HIGH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_bitmap_high0::W`](W) writer structure"] +impl crate::Writable for PMUP_BITMAP_HIGH0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_BITMAP_HIGH0 to value 0"] +impl crate::Resettable for PMUP_BITMAP_HIGH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/pmup_bitmap_high1.rs b/esp32p4/src/pvt/pmup_bitmap_high1.rs new file mode 100644 index 0000000000..9ab1d07dd6 --- /dev/null +++ b/esp32p4/src/pvt/pmup_bitmap_high1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMUP_BITMAP_HIGH1` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_BITMAP_HIGH1` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_BITMAP_HIGH1` reader - select valid high channel1"] +pub type PUMP_BITMAP_HIGH1_R = crate::FieldReader; +#[doc = "Field `PUMP_BITMAP_HIGH1` writer - select valid high channel1"] +pub type PUMP_BITMAP_HIGH1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - select valid high channel1"] + #[inline(always)] + pub fn pump_bitmap_high1(&self) -> PUMP_BITMAP_HIGH1_R { + PUMP_BITMAP_HIGH1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_BITMAP_HIGH1") + .field( + "pump_bitmap_high1", + &format_args!("{}", self.pump_bitmap_high1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - select valid high channel1"] + #[inline(always)] + #[must_use] + pub fn pump_bitmap_high1(&mut self) -> PUMP_BITMAP_HIGH1_W { + PUMP_BITMAP_HIGH1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_high1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_high1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_BITMAP_HIGH1_SPEC; +impl crate::RegisterSpec for PMUP_BITMAP_HIGH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_bitmap_high1::R`](R) reader structure"] +impl crate::Readable for PMUP_BITMAP_HIGH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_bitmap_high1::W`](W) writer structure"] +impl crate::Writable for PMUP_BITMAP_HIGH1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_BITMAP_HIGH1 to value 0"] +impl crate::Resettable for PMUP_BITMAP_HIGH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/pmup_bitmap_high2.rs b/esp32p4/src/pvt/pmup_bitmap_high2.rs new file mode 100644 index 0000000000..2531326744 --- /dev/null +++ b/esp32p4/src/pvt/pmup_bitmap_high2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMUP_BITMAP_HIGH2` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_BITMAP_HIGH2` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_BITMAP_HIGH2` reader - select valid high channel2"] +pub type PUMP_BITMAP_HIGH2_R = crate::FieldReader; +#[doc = "Field `PUMP_BITMAP_HIGH2` writer - select valid high channel2"] +pub type PUMP_BITMAP_HIGH2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - select valid high channel2"] + #[inline(always)] + pub fn pump_bitmap_high2(&self) -> PUMP_BITMAP_HIGH2_R { + PUMP_BITMAP_HIGH2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_BITMAP_HIGH2") + .field( + "pump_bitmap_high2", + &format_args!("{}", self.pump_bitmap_high2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - select valid high channel2"] + #[inline(always)] + #[must_use] + pub fn pump_bitmap_high2(&mut self) -> PUMP_BITMAP_HIGH2_W { + PUMP_BITMAP_HIGH2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_high2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_high2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_BITMAP_HIGH2_SPEC; +impl crate::RegisterSpec for PMUP_BITMAP_HIGH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_bitmap_high2::R`](R) reader structure"] +impl crate::Readable for PMUP_BITMAP_HIGH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_bitmap_high2::W`](W) writer structure"] +impl crate::Writable for PMUP_BITMAP_HIGH2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_BITMAP_HIGH2 to value 0"] +impl crate::Resettable for PMUP_BITMAP_HIGH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/pmup_bitmap_high3.rs b/esp32p4/src/pvt/pmup_bitmap_high3.rs new file mode 100644 index 0000000000..041077697b --- /dev/null +++ b/esp32p4/src/pvt/pmup_bitmap_high3.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMUP_BITMAP_HIGH3` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_BITMAP_HIGH3` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_BITMAP_HIGH3` reader - select valid high channel3"] +pub type PUMP_BITMAP_HIGH3_R = crate::FieldReader; +#[doc = "Field `PUMP_BITMAP_HIGH3` writer - select valid high channel3"] +pub type PUMP_BITMAP_HIGH3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - select valid high channel3"] + #[inline(always)] + pub fn pump_bitmap_high3(&self) -> PUMP_BITMAP_HIGH3_R { + PUMP_BITMAP_HIGH3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_BITMAP_HIGH3") + .field( + "pump_bitmap_high3", + &format_args!("{}", self.pump_bitmap_high3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - select valid high channel3"] + #[inline(always)] + #[must_use] + pub fn pump_bitmap_high3(&mut self) -> PUMP_BITMAP_HIGH3_W { + PUMP_BITMAP_HIGH3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_high3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_high3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_BITMAP_HIGH3_SPEC; +impl crate::RegisterSpec for PMUP_BITMAP_HIGH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_bitmap_high3::R`](R) reader structure"] +impl crate::Readable for PMUP_BITMAP_HIGH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_bitmap_high3::W`](W) writer structure"] +impl crate::Writable for PMUP_BITMAP_HIGH3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_BITMAP_HIGH3 to value 0"] +impl crate::Resettable for PMUP_BITMAP_HIGH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/pmup_bitmap_high4.rs b/esp32p4/src/pvt/pmup_bitmap_high4.rs new file mode 100644 index 0000000000..1654341c14 --- /dev/null +++ b/esp32p4/src/pvt/pmup_bitmap_high4.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMUP_BITMAP_HIGH4` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_BITMAP_HIGH4` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_BITMAP_HIGH4` reader - select valid high channel4"] +pub type PUMP_BITMAP_HIGH4_R = crate::FieldReader; +#[doc = "Field `PUMP_BITMAP_HIGH4` writer - select valid high channel4"] +pub type PUMP_BITMAP_HIGH4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - select valid high channel4"] + #[inline(always)] + pub fn pump_bitmap_high4(&self) -> PUMP_BITMAP_HIGH4_R { + PUMP_BITMAP_HIGH4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_BITMAP_HIGH4") + .field( + "pump_bitmap_high4", + &format_args!("{}", self.pump_bitmap_high4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - select valid high channel4"] + #[inline(always)] + #[must_use] + pub fn pump_bitmap_high4(&mut self) -> PUMP_BITMAP_HIGH4_W { + PUMP_BITMAP_HIGH4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_high4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_high4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_BITMAP_HIGH4_SPEC; +impl crate::RegisterSpec for PMUP_BITMAP_HIGH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_bitmap_high4::R`](R) reader structure"] +impl crate::Readable for PMUP_BITMAP_HIGH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_bitmap_high4::W`](W) writer structure"] +impl crate::Writable for PMUP_BITMAP_HIGH4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_BITMAP_HIGH4 to value 0"] +impl crate::Resettable for PMUP_BITMAP_HIGH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/pmup_bitmap_low0.rs b/esp32p4/src/pvt/pmup_bitmap_low0.rs new file mode 100644 index 0000000000..2094a2c442 --- /dev/null +++ b/esp32p4/src/pvt/pmup_bitmap_low0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMUP_BITMAP_LOW0` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_BITMAP_LOW0` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_BITMAP_LOW0` reader - select valid low channel0"] +pub type PUMP_BITMAP_LOW0_R = crate::FieldReader; +#[doc = "Field `PUMP_BITMAP_LOW0` writer - select valid low channel0"] +pub type PUMP_BITMAP_LOW0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - select valid low channel0"] + #[inline(always)] + pub fn pump_bitmap_low0(&self) -> PUMP_BITMAP_LOW0_R { + PUMP_BITMAP_LOW0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_BITMAP_LOW0") + .field( + "pump_bitmap_low0", + &format_args!("{}", self.pump_bitmap_low0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - select valid low channel0"] + #[inline(always)] + #[must_use] + pub fn pump_bitmap_low0(&mut self) -> PUMP_BITMAP_LOW0_W { + PUMP_BITMAP_LOW0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_low0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_low0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_BITMAP_LOW0_SPEC; +impl crate::RegisterSpec for PMUP_BITMAP_LOW0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_bitmap_low0::R`](R) reader structure"] +impl crate::Readable for PMUP_BITMAP_LOW0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_bitmap_low0::W`](W) writer structure"] +impl crate::Writable for PMUP_BITMAP_LOW0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_BITMAP_LOW0 to value 0"] +impl crate::Resettable for PMUP_BITMAP_LOW0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/pmup_bitmap_low1.rs b/esp32p4/src/pvt/pmup_bitmap_low1.rs new file mode 100644 index 0000000000..d92099a751 --- /dev/null +++ b/esp32p4/src/pvt/pmup_bitmap_low1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMUP_BITMAP_LOW1` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_BITMAP_LOW1` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_BITMAP_LOW1` reader - select valid low channel1"] +pub type PUMP_BITMAP_LOW1_R = crate::FieldReader; +#[doc = "Field `PUMP_BITMAP_LOW1` writer - select valid low channel1"] +pub type PUMP_BITMAP_LOW1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - select valid low channel1"] + #[inline(always)] + pub fn pump_bitmap_low1(&self) -> PUMP_BITMAP_LOW1_R { + PUMP_BITMAP_LOW1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_BITMAP_LOW1") + .field( + "pump_bitmap_low1", + &format_args!("{}", self.pump_bitmap_low1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - select valid low channel1"] + #[inline(always)] + #[must_use] + pub fn pump_bitmap_low1(&mut self) -> PUMP_BITMAP_LOW1_W { + PUMP_BITMAP_LOW1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_low1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_low1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_BITMAP_LOW1_SPEC; +impl crate::RegisterSpec for PMUP_BITMAP_LOW1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_bitmap_low1::R`](R) reader structure"] +impl crate::Readable for PMUP_BITMAP_LOW1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_bitmap_low1::W`](W) writer structure"] +impl crate::Writable for PMUP_BITMAP_LOW1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_BITMAP_LOW1 to value 0"] +impl crate::Resettable for PMUP_BITMAP_LOW1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/pmup_bitmap_low2.rs b/esp32p4/src/pvt/pmup_bitmap_low2.rs new file mode 100644 index 0000000000..b10c754cd9 --- /dev/null +++ b/esp32p4/src/pvt/pmup_bitmap_low2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMUP_BITMAP_LOW2` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_BITMAP_LOW2` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_BITMAP_LOW2` reader - select valid low channel2"] +pub type PUMP_BITMAP_LOW2_R = crate::FieldReader; +#[doc = "Field `PUMP_BITMAP_LOW2` writer - select valid low channel2"] +pub type PUMP_BITMAP_LOW2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - select valid low channel2"] + #[inline(always)] + pub fn pump_bitmap_low2(&self) -> PUMP_BITMAP_LOW2_R { + PUMP_BITMAP_LOW2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_BITMAP_LOW2") + .field( + "pump_bitmap_low2", + &format_args!("{}", self.pump_bitmap_low2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - select valid low channel2"] + #[inline(always)] + #[must_use] + pub fn pump_bitmap_low2(&mut self) -> PUMP_BITMAP_LOW2_W { + PUMP_BITMAP_LOW2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_low2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_low2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_BITMAP_LOW2_SPEC; +impl crate::RegisterSpec for PMUP_BITMAP_LOW2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_bitmap_low2::R`](R) reader structure"] +impl crate::Readable for PMUP_BITMAP_LOW2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_bitmap_low2::W`](W) writer structure"] +impl crate::Writable for PMUP_BITMAP_LOW2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_BITMAP_LOW2 to value 0"] +impl crate::Resettable for PMUP_BITMAP_LOW2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/pmup_bitmap_low3.rs b/esp32p4/src/pvt/pmup_bitmap_low3.rs new file mode 100644 index 0000000000..0631f0002b --- /dev/null +++ b/esp32p4/src/pvt/pmup_bitmap_low3.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMUP_BITMAP_LOW3` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_BITMAP_LOW3` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_BITMAP_LOW3` reader - select valid low channel3"] +pub type PUMP_BITMAP_LOW3_R = crate::FieldReader; +#[doc = "Field `PUMP_BITMAP_LOW3` writer - select valid low channel3"] +pub type PUMP_BITMAP_LOW3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - select valid low channel3"] + #[inline(always)] + pub fn pump_bitmap_low3(&self) -> PUMP_BITMAP_LOW3_R { + PUMP_BITMAP_LOW3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_BITMAP_LOW3") + .field( + "pump_bitmap_low3", + &format_args!("{}", self.pump_bitmap_low3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - select valid low channel3"] + #[inline(always)] + #[must_use] + pub fn pump_bitmap_low3(&mut self) -> PUMP_BITMAP_LOW3_W { + PUMP_BITMAP_LOW3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_low3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_low3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_BITMAP_LOW3_SPEC; +impl crate::RegisterSpec for PMUP_BITMAP_LOW3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_bitmap_low3::R`](R) reader structure"] +impl crate::Readable for PMUP_BITMAP_LOW3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_bitmap_low3::W`](W) writer structure"] +impl crate::Writable for PMUP_BITMAP_LOW3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_BITMAP_LOW3 to value 0"] +impl crate::Resettable for PMUP_BITMAP_LOW3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/pmup_bitmap_low4.rs b/esp32p4/src/pvt/pmup_bitmap_low4.rs new file mode 100644 index 0000000000..ee7dac6aad --- /dev/null +++ b/esp32p4/src/pvt/pmup_bitmap_low4.rs @@ -0,0 +1,66 @@ +#[doc = "Register `PMUP_BITMAP_LOW4` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_BITMAP_LOW4` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_BITMAP_LOW4` reader - select valid low channel4"] +pub type PUMP_BITMAP_LOW4_R = crate::FieldReader; +#[doc = "Field `PUMP_BITMAP_LOW4` writer - select valid low channel4"] +pub type PUMP_BITMAP_LOW4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - select valid low channel4"] + #[inline(always)] + pub fn pump_bitmap_low4(&self) -> PUMP_BITMAP_LOW4_R { + PUMP_BITMAP_LOW4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_BITMAP_LOW4") + .field( + "pump_bitmap_low4", + &format_args!("{}", self.pump_bitmap_low4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - select valid low channel4"] + #[inline(always)] + #[must_use] + pub fn pump_bitmap_low4(&mut self) -> PUMP_BITMAP_LOW4_W { + PUMP_BITMAP_LOW4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "select valid pvt channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_bitmap_low4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_bitmap_low4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_BITMAP_LOW4_SPEC; +impl crate::RegisterSpec for PMUP_BITMAP_LOW4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_bitmap_low4::R`](R) reader structure"] +impl crate::Readable for PMUP_BITMAP_LOW4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_bitmap_low4::W`](W) writer structure"] +impl crate::Writable for PMUP_BITMAP_LOW4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_BITMAP_LOW4 to value 0"] +impl crate::Resettable for PMUP_BITMAP_LOW4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/pmup_channel_cfg.rs b/esp32p4/src/pvt/pmup_channel_cfg.rs new file mode 100644 index 0000000000..58ad8a54d6 --- /dev/null +++ b/esp32p4/src/pvt/pmup_channel_cfg.rs @@ -0,0 +1,142 @@ +#[doc = "Register `PMUP_CHANNEL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_CHANNEL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_CHANNEL_CODE4` reader - configure cmd4 code"] +pub type PUMP_CHANNEL_CODE4_R = crate::FieldReader; +#[doc = "Field `PUMP_CHANNEL_CODE4` writer - configure cmd4 code"] +pub type PUMP_CHANNEL_CODE4_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PUMP_CHANNEL_CODE3` reader - configure cmd3 code"] +pub type PUMP_CHANNEL_CODE3_R = crate::FieldReader; +#[doc = "Field `PUMP_CHANNEL_CODE3` writer - configure cmd3 code"] +pub type PUMP_CHANNEL_CODE3_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PUMP_CHANNEL_CODE2` reader - configure cmd2 code"] +pub type PUMP_CHANNEL_CODE2_R = crate::FieldReader; +#[doc = "Field `PUMP_CHANNEL_CODE2` writer - configure cmd2 code"] +pub type PUMP_CHANNEL_CODE2_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PUMP_CHANNEL_CODE1` reader - configure cmd1 code"] +pub type PUMP_CHANNEL_CODE1_R = crate::FieldReader; +#[doc = "Field `PUMP_CHANNEL_CODE1` writer - configure cmd1 code"] +pub type PUMP_CHANNEL_CODE1_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PUMP_CHANNEL_CODE0` reader - configure cmd0 code"] +pub type PUMP_CHANNEL_CODE0_R = crate::FieldReader; +#[doc = "Field `PUMP_CHANNEL_CODE0` writer - configure cmd0 code"] +pub type PUMP_CHANNEL_CODE0_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 7:11 - configure cmd4 code"] + #[inline(always)] + pub fn pump_channel_code4(&self) -> PUMP_CHANNEL_CODE4_R { + PUMP_CHANNEL_CODE4_R::new(((self.bits >> 7) & 0x1f) as u8) + } + #[doc = "Bits 12:16 - configure cmd3 code"] + #[inline(always)] + pub fn pump_channel_code3(&self) -> PUMP_CHANNEL_CODE3_R { + PUMP_CHANNEL_CODE3_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - configure cmd2 code"] + #[inline(always)] + pub fn pump_channel_code2(&self) -> PUMP_CHANNEL_CODE2_R { + PUMP_CHANNEL_CODE2_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:26 - configure cmd1 code"] + #[inline(always)] + pub fn pump_channel_code1(&self) -> PUMP_CHANNEL_CODE1_R { + PUMP_CHANNEL_CODE1_R::new(((self.bits >> 22) & 0x1f) as u8) + } + #[doc = "Bits 27:31 - configure cmd0 code"] + #[inline(always)] + pub fn pump_channel_code0(&self) -> PUMP_CHANNEL_CODE0_R { + PUMP_CHANNEL_CODE0_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_CHANNEL_CFG") + .field( + "pump_channel_code4", + &format_args!("{}", self.pump_channel_code4().bits()), + ) + .field( + "pump_channel_code3", + &format_args!("{}", self.pump_channel_code3().bits()), + ) + .field( + "pump_channel_code2", + &format_args!("{}", self.pump_channel_code2().bits()), + ) + .field( + "pump_channel_code1", + &format_args!("{}", self.pump_channel_code1().bits()), + ) + .field( + "pump_channel_code0", + &format_args!("{}", self.pump_channel_code0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 7:11 - configure cmd4 code"] + #[inline(always)] + #[must_use] + pub fn pump_channel_code4(&mut self) -> PUMP_CHANNEL_CODE4_W { + PUMP_CHANNEL_CODE4_W::new(self, 7) + } + #[doc = "Bits 12:16 - configure cmd3 code"] + #[inline(always)] + #[must_use] + pub fn pump_channel_code3(&mut self) -> PUMP_CHANNEL_CODE3_W { + PUMP_CHANNEL_CODE3_W::new(self, 12) + } + #[doc = "Bits 17:21 - configure cmd2 code"] + #[inline(always)] + #[must_use] + pub fn pump_channel_code2(&mut self) -> PUMP_CHANNEL_CODE2_W { + PUMP_CHANNEL_CODE2_W::new(self, 17) + } + #[doc = "Bits 22:26 - configure cmd1 code"] + #[inline(always)] + #[must_use] + pub fn pump_channel_code1(&mut self) -> PUMP_CHANNEL_CODE1_W { + PUMP_CHANNEL_CODE1_W::new(self, 22) + } + #[doc = "Bits 27:31 - configure cmd0 code"] + #[inline(always)] + #[must_use] + pub fn pump_channel_code0(&mut self) -> PUMP_CHANNEL_CODE0_W { + PUMP_CHANNEL_CODE0_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "configure the code of valid pump channel code\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_channel_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_channel_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_CHANNEL_CFG_SPEC; +impl crate::RegisterSpec for PMUP_CHANNEL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_channel_cfg::R`](R) reader structure"] +impl crate::Readable for PMUP_CHANNEL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_channel_cfg::W`](W) writer structure"] +impl crate::Writable for PMUP_CHANNEL_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_CHANNEL_CFG to value 0"] +impl crate::Resettable for PMUP_CHANNEL_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/pmup_drv_cfg.rs b/esp32p4/src/pvt/pmup_drv_cfg.rs new file mode 100644 index 0000000000..169e0eb8f0 --- /dev/null +++ b/esp32p4/src/pvt/pmup_drv_cfg.rs @@ -0,0 +1,159 @@ +#[doc = "Register `PMUP_DRV_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `PMUP_DRV_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `PUMP_EN` reader - configure pvt charge xpd"] +pub type PUMP_EN_R = crate::BitReader; +#[doc = "Field `PUMP_EN` writer - configure pvt charge xpd"] +pub type PUMP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - force register clken"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - force register clken"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PUMP_DRV4` reader - configure cmd4 drv"] +pub type PUMP_DRV4_R = crate::FieldReader; +#[doc = "Field `PUMP_DRV4` writer - configure cmd4 drv"] +pub type PUMP_DRV4_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PUMP_DRV3` reader - configure cmd3 drv"] +pub type PUMP_DRV3_R = crate::FieldReader; +#[doc = "Field `PUMP_DRV3` writer - configure cmd3 drv"] +pub type PUMP_DRV3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PUMP_DRV2` reader - configure cmd2 drv"] +pub type PUMP_DRV2_R = crate::FieldReader; +#[doc = "Field `PUMP_DRV2` writer - configure cmd2 drv"] +pub type PUMP_DRV2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PUMP_DRV1` reader - configure cmd1 drv"] +pub type PUMP_DRV1_R = crate::FieldReader; +#[doc = "Field `PUMP_DRV1` writer - configure cmd1 drv"] +pub type PUMP_DRV1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PUMP_DRV0` reader - configure cmd0 drv"] +pub type PUMP_DRV0_R = crate::FieldReader; +#[doc = "Field `PUMP_DRV0` writer - configure cmd0 drv"] +pub type PUMP_DRV0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 9 - configure pvt charge xpd"] + #[inline(always)] + pub fn pump_en(&self) -> PUMP_EN_R { + PUMP_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - force register clken"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 11:14 - configure cmd4 drv"] + #[inline(always)] + pub fn pump_drv4(&self) -> PUMP_DRV4_R { + PUMP_DRV4_R::new(((self.bits >> 11) & 0x0f) as u8) + } + #[doc = "Bits 15:18 - configure cmd3 drv"] + #[inline(always)] + pub fn pump_drv3(&self) -> PUMP_DRV3_R { + PUMP_DRV3_R::new(((self.bits >> 15) & 0x0f) as u8) + } + #[doc = "Bits 19:22 - configure cmd2 drv"] + #[inline(always)] + pub fn pump_drv2(&self) -> PUMP_DRV2_R { + PUMP_DRV2_R::new(((self.bits >> 19) & 0x0f) as u8) + } + #[doc = "Bits 23:26 - configure cmd1 drv"] + #[inline(always)] + pub fn pump_drv1(&self) -> PUMP_DRV1_R { + PUMP_DRV1_R::new(((self.bits >> 23) & 0x0f) as u8) + } + #[doc = "Bits 27:30 - configure cmd0 drv"] + #[inline(always)] + pub fn pump_drv0(&self) -> PUMP_DRV0_R { + PUMP_DRV0_R::new(((self.bits >> 27) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PMUP_DRV_CFG") + .field("pump_en", &format_args!("{}", self.pump_en().bit())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field("pump_drv4", &format_args!("{}", self.pump_drv4().bits())) + .field("pump_drv3", &format_args!("{}", self.pump_drv3().bits())) + .field("pump_drv2", &format_args!("{}", self.pump_drv2().bits())) + .field("pump_drv1", &format_args!("{}", self.pump_drv1().bits())) + .field("pump_drv0", &format_args!("{}", self.pump_drv0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 9 - configure pvt charge xpd"] + #[inline(always)] + #[must_use] + pub fn pump_en(&mut self) -> PUMP_EN_W { + PUMP_EN_W::new(self, 9) + } + #[doc = "Bit 10 - force register clken"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 10) + } + #[doc = "Bits 11:14 - configure cmd4 drv"] + #[inline(always)] + #[must_use] + pub fn pump_drv4(&mut self) -> PUMP_DRV4_W { + PUMP_DRV4_W::new(self, 11) + } + #[doc = "Bits 15:18 - configure cmd3 drv"] + #[inline(always)] + #[must_use] + pub fn pump_drv3(&mut self) -> PUMP_DRV3_W { + PUMP_DRV3_W::new(self, 15) + } + #[doc = "Bits 19:22 - configure cmd2 drv"] + #[inline(always)] + #[must_use] + pub fn pump_drv2(&mut self) -> PUMP_DRV2_W { + PUMP_DRV2_W::new(self, 19) + } + #[doc = "Bits 23:26 - configure cmd1 drv"] + #[inline(always)] + #[must_use] + pub fn pump_drv1(&mut self) -> PUMP_DRV1_W { + PUMP_DRV1_W::new(self, 23) + } + #[doc = "Bits 27:30 - configure cmd0 drv"] + #[inline(always)] + #[must_use] + pub fn pump_drv0(&mut self) -> PUMP_DRV0_W { + PUMP_DRV0_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "configure pump drv\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmup_drv_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmup_drv_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PMUP_DRV_CFG_SPEC; +impl crate::RegisterSpec for PMUP_DRV_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmup_drv_cfg::R`](R) reader structure"] +impl crate::Readable for PMUP_DRV_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmup_drv_cfg::W`](W) writer structure"] +impl crate::Writable for PMUP_DRV_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUP_DRV_CFG to value 0"] +impl crate::Resettable for PMUP_DRV_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/pvt/value_update.rs b/esp32p4/src/pvt/value_update.rs new file mode 100644 index 0000000000..a9d59fb6d4 --- /dev/null +++ b/esp32p4/src/pvt/value_update.rs @@ -0,0 +1,71 @@ +#[doc = "Register `VALUE_UPDATE` reader"] +pub type R = crate::R; +#[doc = "Register `VALUE_UPDATE` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE_UPDATE` writer - needs field desc"] +pub type VALUE_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BYPASS` reader - needs field desc"] +pub type BYPASS_R = crate::BitReader; +#[doc = "Field `BYPASS` writer - needs field desc"] +pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + pub fn bypass(&self) -> BYPASS_R { + BYPASS_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VALUE_UPDATE") + .field("bypass", &format_args!("{}", self.bypass().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn value_update(&mut self) -> VALUE_UPDATE_W { + VALUE_UPDATE_W::new(self, 0) + } + #[doc = "Bit 1 - needs field desc"] + #[inline(always)] + #[must_use] + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "needs field desc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value_update::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value_update::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VALUE_UPDATE_SPEC; +impl crate::RegisterSpec for VALUE_UPDATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`value_update::R`](R) reader structure"] +impl crate::Readable for VALUE_UPDATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`value_update::W`](W) writer structure"] +impl crate::Writable for VALUE_UPDATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VALUE_UPDATE to value 0"] +impl crate::Resettable for VALUE_UPDATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rmt.rs b/esp32p4/src/rmt.rs new file mode 100644 index 0000000000..90b1e2bcda --- /dev/null +++ b/esp32p4/src/rmt.rs @@ -0,0 +1,423 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + tx_chdata: [TX_CHDATA; 4], + rx_chdata: [RX_CHDATA; 4], + tx_chconf0: [TX_CHCONF0; 4], + rx_chconf0: (), + _reserved4: [u8; 0x04], + rx_chconf1: (), + _reserved5: [u8; 0x1c], + tx_chstatus: [TX_CHSTATUS; 4], + rx_chstatus: [RX_CHSTATUS; 4], + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + chcarrier_duty: [CHCARRIER_DUTY; 4], + ch_rx_carrier_rm: [CH_RX_CARRIER_RM; 4], + ch_tx_lim: [CH_TX_LIM; 4], + ch_rx_lim: [CH_RX_LIM; 4], + sys_conf: SYS_CONF, + tx_sim: TX_SIM, + ref_cnt_rst: REF_CNT_RST, + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00..0x10 - The read and write data register for CHANNEL%s by apb fifo access."] + #[inline(always)] + pub const fn tx_chdata(&self, n: usize) -> &TX_CHDATA { + &self.tx_chdata[n] + } + #[doc = "0x00 - The read and write data register for CHANNEL0 by apb fifo access."] + #[inline(always)] + pub const fn tx_ch0data(&self) -> &TX_CHDATA { + &self.tx_chdata(0) + } + #[doc = "0x04 - The read and write data register for CHANNEL1 by apb fifo access."] + #[inline(always)] + pub const fn tx_ch1data(&self) -> &TX_CHDATA { + &self.tx_chdata(1) + } + #[doc = "0x08 - The read and write data register for CHANNEL2 by apb fifo access."] + #[inline(always)] + pub const fn tx_ch2data(&self) -> &TX_CHDATA { + &self.tx_chdata(2) + } + #[doc = "0x0c - The read and write data register for CHANNEL3 by apb fifo access."] + #[inline(always)] + pub const fn tx_ch3data(&self) -> &TX_CHDATA { + &self.tx_chdata(3) + } + #[doc = "0x10..0x20 - The read and write data register for CHANNEL$n by apb fifo access."] + #[inline(always)] + pub const fn rx_chdata(&self, n: usize) -> &RX_CHDATA { + &self.rx_chdata[n] + } + #[doc = "0x10 - The read and write data register for CHANNEL$n by apb fifo access."] + #[inline(always)] + pub const fn rx_ch0data(&self) -> &RX_CHDATA { + &self.rx_chdata(0) + } + #[doc = "0x14 - The read and write data register for CHANNEL$n by apb fifo access."] + #[inline(always)] + pub const fn rx_ch1data(&self) -> &RX_CHDATA { + &self.rx_chdata(1) + } + #[doc = "0x18 - The read and write data register for CHANNEL$n by apb fifo access."] + #[inline(always)] + pub const fn rx_ch2data(&self) -> &RX_CHDATA { + &self.rx_chdata(2) + } + #[doc = "0x1c - The read and write data register for CHANNEL$n by apb fifo access."] + #[inline(always)] + pub const fn rx_ch3data(&self) -> &RX_CHDATA { + &self.rx_chdata(3) + } + #[doc = "0x20..0x30 - Channel %s configure register 0"] + #[inline(always)] + pub const fn tx_chconf0(&self, n: usize) -> &TX_CHCONF0 { + &self.tx_chconf0[n] + } + #[doc = "0x20 - Channel 0 configure register 0"] + #[inline(always)] + pub const fn tx_ch0conf0(&self) -> &TX_CHCONF0 { + &self.tx_chconf0(0) + } + #[doc = "0x24 - Channel 1 configure register 0"] + #[inline(always)] + pub const fn tx_ch1conf0(&self) -> &TX_CHCONF0 { + &self.tx_chconf0(1) + } + #[doc = "0x28 - Channel 2 configure register 0"] + #[inline(always)] + pub const fn tx_ch2conf0(&self) -> &TX_CHCONF0 { + &self.tx_chconf0(2) + } + #[doc = "0x2c - Channel 3 configure register 0"] + #[inline(always)] + pub const fn tx_ch3conf0(&self) -> &TX_CHCONF0 { + &self.tx_chconf0(3) + } + #[doc = "0x30..0x40 - Channel %s configure register 0"] + #[inline(always)] + pub const fn rx_chconf0(&self, n: usize) -> &RX_CHCONF0 { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(48).add(8 * n).cast() } + } + #[doc = "0x30 - Channel 0 configure register 0"] + #[inline(always)] + pub const fn rx_ch0conf0(&self) -> &RX_CHCONF0 { + &self.rx_chconf0(0) + } + #[doc = "0x38 - Channel 1 configure register 0"] + #[inline(always)] + pub const fn rx_ch1conf0(&self) -> &RX_CHCONF0 { + &self.rx_chconf0(1) + } + #[doc = "0x40 - Channel 2 configure register 0"] + #[inline(always)] + pub const fn rx_ch2conf0(&self) -> &RX_CHCONF0 { + &self.rx_chconf0(2) + } + #[doc = "0x48 - Channel 3 configure register 0"] + #[inline(always)] + pub const fn rx_ch3conf0(&self) -> &RX_CHCONF0 { + &self.rx_chconf0(3) + } + #[doc = "0x34..0x44 - Channel %s configure register 1"] + #[inline(always)] + pub const fn rx_chconf1(&self, n: usize) -> &RX_CHCONF1 { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(52).add(8 * n).cast() } + } + #[doc = "0x34 - Channel 0 configure register 1"] + #[inline(always)] + pub const fn rx_ch0conf1(&self) -> &RX_CHCONF1 { + &self.rx_chconf1(0) + } + #[doc = "0x3c - Channel 1 configure register 1"] + #[inline(always)] + pub const fn rx_ch1conf1(&self) -> &RX_CHCONF1 { + &self.rx_chconf1(1) + } + #[doc = "0x44 - Channel 2 configure register 1"] + #[inline(always)] + pub const fn rx_ch2conf1(&self) -> &RX_CHCONF1 { + &self.rx_chconf1(2) + } + #[doc = "0x4c - Channel 3 configure register 1"] + #[inline(always)] + pub const fn rx_ch3conf1(&self) -> &RX_CHCONF1 { + &self.rx_chconf1(3) + } + #[doc = "0x50..0x60 - Channel %s status register"] + #[inline(always)] + pub const fn tx_chstatus(&self, n: usize) -> &TX_CHSTATUS { + &self.tx_chstatus[n] + } + #[doc = "0x50 - Channel 0 status register"] + #[inline(always)] + pub const fn tx_ch0status(&self) -> &TX_CHSTATUS { + &self.tx_chstatus(0) + } + #[doc = "0x54 - Channel 1 status register"] + #[inline(always)] + pub const fn tx_ch1status(&self) -> &TX_CHSTATUS { + &self.tx_chstatus(1) + } + #[doc = "0x58 - Channel 2 status register"] + #[inline(always)] + pub const fn tx_ch2status(&self) -> &TX_CHSTATUS { + &self.tx_chstatus(2) + } + #[doc = "0x5c - Channel 3 status register"] + #[inline(always)] + pub const fn tx_ch3status(&self) -> &TX_CHSTATUS { + &self.tx_chstatus(3) + } + #[doc = "0x60..0x70 - Channel %s status register"] + #[inline(always)] + pub const fn rx_chstatus(&self, n: usize) -> &RX_CHSTATUS { + &self.rx_chstatus[n] + } + #[doc = "0x60 - Channel 0 status register"] + #[inline(always)] + pub const fn rx_ch0status(&self) -> &RX_CHSTATUS { + &self.rx_chstatus(0) + } + #[doc = "0x64 - Channel 1 status register"] + #[inline(always)] + pub const fn rx_ch1status(&self) -> &RX_CHSTATUS { + &self.rx_chstatus(1) + } + #[doc = "0x68 - Channel 2 status register"] + #[inline(always)] + pub const fn rx_ch2status(&self) -> &RX_CHSTATUS { + &self.rx_chstatus(2) + } + #[doc = "0x6c - Channel 3 status register"] + #[inline(always)] + pub const fn rx_ch3status(&self) -> &RX_CHSTATUS { + &self.rx_chstatus(3) + } + #[doc = "0x70 - Raw interrupt status"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x74 - Masked interrupt status"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x78 - Interrupt enable bits"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x7c - Interrupt clear bits"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x80..0x90 - Channel %s duty cycle configuration register"] + #[inline(always)] + pub const fn chcarrier_duty(&self, n: usize) -> &CHCARRIER_DUTY { + &self.chcarrier_duty[n] + } + #[doc = "0x80 - Channel 0 duty cycle configuration register"] + #[inline(always)] + pub const fn ch0carrier_duty(&self) -> &CHCARRIER_DUTY { + &self.chcarrier_duty(0) + } + #[doc = "0x84 - Channel 1 duty cycle configuration register"] + #[inline(always)] + pub const fn ch1carrier_duty(&self) -> &CHCARRIER_DUTY { + &self.chcarrier_duty(1) + } + #[doc = "0x88 - Channel 2 duty cycle configuration register"] + #[inline(always)] + pub const fn ch2carrier_duty(&self) -> &CHCARRIER_DUTY { + &self.chcarrier_duty(2) + } + #[doc = "0x8c - Channel 3 duty cycle configuration register"] + #[inline(always)] + pub const fn ch3carrier_duty(&self) -> &CHCARRIER_DUTY { + &self.chcarrier_duty(3) + } + #[doc = "0x90..0xa0 - Channel %s carrier remove register"] + #[inline(always)] + pub const fn ch_rx_carrier_rm(&self, n: usize) -> &CH_RX_CARRIER_RM { + &self.ch_rx_carrier_rm[n] + } + #[doc = "0x90 - Channel 0 carrier remove register"] + #[inline(always)] + pub const fn ch0_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM { + &self.ch_rx_carrier_rm(0) + } + #[doc = "0x94 - Channel 1 carrier remove register"] + #[inline(always)] + pub const fn ch1_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM { + &self.ch_rx_carrier_rm(1) + } + #[doc = "0x98 - Channel 2 carrier remove register"] + #[inline(always)] + pub const fn ch2_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM { + &self.ch_rx_carrier_rm(2) + } + #[doc = "0x9c - Channel 3 carrier remove register"] + #[inline(always)] + pub const fn ch3_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM { + &self.ch_rx_carrier_rm(3) + } + #[doc = "0xa0..0xb0 - Channel %s Tx event configuration register"] + #[inline(always)] + pub const fn ch_tx_lim(&self, n: usize) -> &CH_TX_LIM { + &self.ch_tx_lim[n] + } + #[doc = "0xa0 - Channel 0 Tx event configuration register"] + #[inline(always)] + pub const fn ch0_tx_lim(&self) -> &CH_TX_LIM { + &self.ch_tx_lim(0) + } + #[doc = "0xa4 - Channel 1 Tx event configuration register"] + #[inline(always)] + pub const fn ch1_tx_lim(&self) -> &CH_TX_LIM { + &self.ch_tx_lim(1) + } + #[doc = "0xa8 - Channel 2 Tx event configuration register"] + #[inline(always)] + pub const fn ch2_tx_lim(&self) -> &CH_TX_LIM { + &self.ch_tx_lim(2) + } + #[doc = "0xac - Channel 3 Tx event configuration register"] + #[inline(always)] + pub const fn ch3_tx_lim(&self) -> &CH_TX_LIM { + &self.ch_tx_lim(3) + } + #[doc = "0xb0..0xc0 - Channel %s Rx event configuration register"] + #[inline(always)] + pub const fn ch_rx_lim(&self, n: usize) -> &CH_RX_LIM { + &self.ch_rx_lim[n] + } + #[doc = "0xb0 - Channel 0 Rx event configuration register"] + #[inline(always)] + pub const fn ch0_rx_lim(&self) -> &CH_RX_LIM { + &self.ch_rx_lim(0) + } + #[doc = "0xb4 - Channel 1 Rx event configuration register"] + #[inline(always)] + pub const fn ch1_rx_lim(&self) -> &CH_RX_LIM { + &self.ch_rx_lim(1) + } + #[doc = "0xb8 - Channel 2 Rx event configuration register"] + #[inline(always)] + pub const fn ch2_rx_lim(&self) -> &CH_RX_LIM { + &self.ch_rx_lim(2) + } + #[doc = "0xbc - Channel 3 Rx event configuration register"] + #[inline(always)] + pub const fn ch3_rx_lim(&self) -> &CH_RX_LIM { + &self.ch_rx_lim(3) + } + #[doc = "0xc0 - RMT apb configuration register"] + #[inline(always)] + pub const fn sys_conf(&self) -> &SYS_CONF { + &self.sys_conf + } + #[doc = "0xc4 - RMT TX synchronous register"] + #[inline(always)] + pub const fn tx_sim(&self) -> &TX_SIM { + &self.tx_sim + } + #[doc = "0xc8 - RMT clock divider reset register"] + #[inline(always)] + pub const fn ref_cnt_rst(&self) -> &REF_CNT_RST { + &self.ref_cnt_rst + } + #[doc = "0xcc - RMT version register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "TX_CHDATA (r) register accessor: The read and write data register for CHANNEL%s by apb fifo access.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_chdata::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_chdata`] module"] +pub type TX_CHDATA = crate::Reg; +#[doc = "The read and write data register for CHANNEL%s by apb fifo access."] +pub mod tx_chdata; +#[doc = "RX_CHDATA (r) register accessor: The read and write data register for CHANNEL$n by apb fifo access.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chdata::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_chdata`] module"] +pub type RX_CHDATA = crate::Reg; +#[doc = "The read and write data register for CHANNEL$n by apb fifo access."] +pub mod rx_chdata; +#[doc = "TX_CHCONF0 (rw) register accessor: Channel %s configure register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_chconf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_chconf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_chconf0`] module"] +pub type TX_CHCONF0 = crate::Reg; +#[doc = "Channel %s configure register 0"] +pub mod tx_chconf0; +#[doc = "RX_CHCONF0 (rw) register accessor: Channel %s configure register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chconf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_chconf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_chconf0`] module"] +pub type RX_CHCONF0 = crate::Reg; +#[doc = "Channel %s configure register 0"] +pub mod rx_chconf0; +#[doc = "RX_CHCONF1 (rw) register accessor: Channel %s configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chconf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_chconf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_chconf1`] module"] +pub type RX_CHCONF1 = crate::Reg; +#[doc = "Channel %s configure register 1"] +pub mod rx_chconf1; +#[doc = "TX_CHSTATUS (r) register accessor: Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_chstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_chstatus`] module"] +pub type TX_CHSTATUS = crate::Reg; +#[doc = "Channel %s status register"] +pub mod tx_chstatus; +#[doc = "RX_CHSTATUS (r) register accessor: Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_chstatus`] module"] +pub type RX_CHSTATUS = crate::Reg; +#[doc = "Channel %s status register"] +pub mod rx_chstatus; +#[doc = "INT_RAW (rw) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Raw interrupt status"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Masked interrupt status"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable bits"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear bits"] +pub mod int_clr; +#[doc = "CHCARRIER_DUTY (rw) register accessor: Channel %s duty cycle configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chcarrier_duty::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chcarrier_duty::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chcarrier_duty`] module"] +pub type CHCARRIER_DUTY = crate::Reg; +#[doc = "Channel %s duty cycle configuration register"] +pub mod chcarrier_duty; +#[doc = "CH_RX_CARRIER_RM (rw) register accessor: Channel %s carrier remove register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_rx_carrier_rm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_rx_carrier_rm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_rx_carrier_rm`] module"] +pub type CH_RX_CARRIER_RM = crate::Reg; +#[doc = "Channel %s carrier remove register"] +pub mod ch_rx_carrier_rm; +#[doc = "CH_TX_LIM (rw) register accessor: Channel %s Tx event configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_tx_lim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_tx_lim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_tx_lim`] module"] +pub type CH_TX_LIM = crate::Reg; +#[doc = "Channel %s Tx event configuration register"] +pub mod ch_tx_lim; +#[doc = "CH_RX_LIM (rw) register accessor: Channel %s Rx event configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_rx_lim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_rx_lim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_rx_lim`] module"] +pub type CH_RX_LIM = crate::Reg; +#[doc = "Channel %s Rx event configuration register"] +pub mod ch_rx_lim; +#[doc = "SYS_CONF (rw) register accessor: RMT apb configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_conf`] module"] +pub type SYS_CONF = crate::Reg; +#[doc = "RMT apb configuration register"] +pub mod sys_conf; +#[doc = "TX_SIM (rw) register accessor: RMT TX synchronous register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_sim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_sim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_sim`] module"] +pub type TX_SIM = crate::Reg; +#[doc = "RMT TX synchronous register"] +pub mod tx_sim; +#[doc = "REF_CNT_RST (w) register accessor: RMT clock divider reset register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_cnt_rst::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ref_cnt_rst`] module"] +pub type REF_CNT_RST = crate::Reg; +#[doc = "RMT clock divider reset register"] +pub mod ref_cnt_rst; +#[doc = "DATE (rw) register accessor: RMT version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "RMT version register"] +pub mod date; diff --git a/esp32p4/src/rmt/ch_rx_carrier_rm.rs b/esp32p4/src/rmt/ch_rx_carrier_rm.rs new file mode 100644 index 0000000000..225033ef01 --- /dev/null +++ b/esp32p4/src/rmt/ch_rx_carrier_rm.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CH%s_RX_CARRIER_RM` reader"] +pub type R = crate::R; +#[doc = "Register `CH%s_RX_CARRIER_RM` writer"] +pub type W = crate::W; +#[doc = "Field `CARRIER_LOW_THRES_CH` reader - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s."] +pub type CARRIER_LOW_THRES_CH_R = crate::FieldReader; +#[doc = "Field `CARRIER_LOW_THRES_CH` writer - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s."] +pub type CARRIER_LOW_THRES_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CARRIER_HIGH_THRES_CH` reader - The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s."] +pub type CARRIER_HIGH_THRES_CH_R = crate::FieldReader; +#[doc = "Field `CARRIER_HIGH_THRES_CH` writer - The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s."] +pub type CARRIER_HIGH_THRES_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s."] + #[inline(always)] + pub fn carrier_low_thres_ch(&self) -> CARRIER_LOW_THRES_CH_R { + CARRIER_LOW_THRES_CH_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s."] + #[inline(always)] + pub fn carrier_high_thres_ch(&self) -> CARRIER_HIGH_THRES_CH_R { + CARRIER_HIGH_THRES_CH_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH_RX_CARRIER_RM") + .field( + "carrier_low_thres_ch", + &format_args!("{}", self.carrier_low_thres_ch().bits()), + ) + .field( + "carrier_high_thres_ch", + &format_args!("{}", self.carrier_high_thres_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s."] + #[inline(always)] + #[must_use] + pub fn carrier_low_thres_ch(&mut self) -> CARRIER_LOW_THRES_CH_W { + CARRIER_LOW_THRES_CH_W::new(self, 0) + } + #[doc = "Bits 16:31 - The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s."] + #[inline(always)] + #[must_use] + pub fn carrier_high_thres_ch(&mut self) -> CARRIER_HIGH_THRES_CH_W { + CARRIER_HIGH_THRES_CH_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel %s carrier remove register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_rx_carrier_rm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_rx_carrier_rm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_RX_CARRIER_RM_SPEC; +impl crate::RegisterSpec for CH_RX_CARRIER_RM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_rx_carrier_rm::R`](R) reader structure"] +impl crate::Readable for CH_RX_CARRIER_RM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_rx_carrier_rm::W`](W) writer structure"] +impl crate::Writable for CH_RX_CARRIER_RM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH%s_RX_CARRIER_RM to value 0"] +impl crate::Resettable for CH_RX_CARRIER_RM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rmt/ch_rx_lim.rs b/esp32p4/src/rmt/ch_rx_lim.rs new file mode 100644 index 0000000000..7b24c9ae5a --- /dev/null +++ b/esp32p4/src/rmt/ch_rx_lim.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH%s_RX_LIM` reader"] +pub type R = crate::R; +#[doc = "Register `CH%s_RX_LIM` writer"] +pub type W = crate::W; +#[doc = "Field `RX_LIM_CH4` reader - This register is used to configure the maximum entries that CHANNEL%s can receive."] +pub type RX_LIM_CH4_R = crate::FieldReader; +#[doc = "Field `RX_LIM_CH4` writer - This register is used to configure the maximum entries that CHANNEL%s can receive."] +pub type RX_LIM_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can receive."] + #[inline(always)] + pub fn rx_lim_ch4(&self) -> RX_LIM_CH4_R { + RX_LIM_CH4_R::new((self.bits & 0x01ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH_RX_LIM") + .field("rx_lim_ch4", &format_args!("{}", self.rx_lim_ch4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can receive."] + #[inline(always)] + #[must_use] + pub fn rx_lim_ch4(&mut self) -> RX_LIM_CH4_W { + RX_LIM_CH4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel %s Rx event configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_rx_lim::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_rx_lim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_RX_LIM_SPEC; +impl crate::RegisterSpec for CH_RX_LIM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_rx_lim::R`](R) reader structure"] +impl crate::Readable for CH_RX_LIM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_rx_lim::W`](W) writer structure"] +impl crate::Writable for CH_RX_LIM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH%s_RX_LIM to value 0x80"] +impl crate::Resettable for CH_RX_LIM_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/rmt/ch_tx_lim.rs b/esp32p4/src/rmt/ch_tx_lim.rs new file mode 100644 index 0000000000..c67daaa0ed --- /dev/null +++ b/esp32p4/src/rmt/ch_tx_lim.rs @@ -0,0 +1,128 @@ +#[doc = "Register `CH%s_TX_LIM` reader"] +pub type R = crate::R; +#[doc = "Register `CH%s_TX_LIM` writer"] +pub type W = crate::W; +#[doc = "Field `TX_LIM_CH` reader - This register is used to configure the maximum entries that CHANNEL%s can send out."] +pub type TX_LIM_CH_R = crate::FieldReader; +#[doc = "Field `TX_LIM_CH` writer - This register is used to configure the maximum entries that CHANNEL%s can send out."] +pub type TX_LIM_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +#[doc = "Field `TX_LOOP_NUM_CH` reader - This register is used to configure the maximum loop count when tx_conti_mode is valid."] +pub type TX_LOOP_NUM_CH_R = crate::FieldReader; +#[doc = "Field `TX_LOOP_NUM_CH` writer - This register is used to configure the maximum loop count when tx_conti_mode is valid."] +pub type TX_LOOP_NUM_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `TX_LOOP_CNT_EN_CH` reader - This register is the enabled bit for loop count."] +pub type TX_LOOP_CNT_EN_CH_R = crate::BitReader; +#[doc = "Field `TX_LOOP_CNT_EN_CH` writer - This register is the enabled bit for loop count."] +pub type TX_LOOP_CNT_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOP_COUNT_RESET_CH` writer - This register is used to reset the loop count when tx_conti_mode is valid."] +pub type LOOP_COUNT_RESET_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOP_STOP_EN_CH` reader - This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s."] +pub type LOOP_STOP_EN_CH_R = crate::BitReader; +#[doc = "Field `LOOP_STOP_EN_CH` writer - This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s."] +pub type LOOP_STOP_EN_CH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can send out."] + #[inline(always)] + pub fn tx_lim_ch(&self) -> TX_LIM_CH_R { + TX_LIM_CH_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:18 - This register is used to configure the maximum loop count when tx_conti_mode is valid."] + #[inline(always)] + pub fn tx_loop_num_ch(&self) -> TX_LOOP_NUM_CH_R { + TX_LOOP_NUM_CH_R::new(((self.bits >> 9) & 0x03ff) as u16) + } + #[doc = "Bit 19 - This register is the enabled bit for loop count."] + #[inline(always)] + pub fn tx_loop_cnt_en_ch(&self) -> TX_LOOP_CNT_EN_CH_R { + TX_LOOP_CNT_EN_CH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s."] + #[inline(always)] + pub fn loop_stop_en_ch(&self) -> LOOP_STOP_EN_CH_R { + LOOP_STOP_EN_CH_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH_TX_LIM") + .field("tx_lim_ch", &format_args!("{}", self.tx_lim_ch().bits())) + .field( + "tx_loop_num_ch", + &format_args!("{}", self.tx_loop_num_ch().bits()), + ) + .field( + "tx_loop_cnt_en_ch", + &format_args!("{}", self.tx_loop_cnt_en_ch().bit()), + ) + .field( + "loop_stop_en_ch", + &format_args!("{}", self.loop_stop_en_ch().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can send out."] + #[inline(always)] + #[must_use] + pub fn tx_lim_ch(&mut self) -> TX_LIM_CH_W { + TX_LIM_CH_W::new(self, 0) + } + #[doc = "Bits 9:18 - This register is used to configure the maximum loop count when tx_conti_mode is valid."] + #[inline(always)] + #[must_use] + pub fn tx_loop_num_ch(&mut self) -> TX_LOOP_NUM_CH_W { + TX_LOOP_NUM_CH_W::new(self, 9) + } + #[doc = "Bit 19 - This register is the enabled bit for loop count."] + #[inline(always)] + #[must_use] + pub fn tx_loop_cnt_en_ch(&mut self) -> TX_LOOP_CNT_EN_CH_W { + TX_LOOP_CNT_EN_CH_W::new(self, 19) + } + #[doc = "Bit 20 - This register is used to reset the loop count when tx_conti_mode is valid."] + #[inline(always)] + #[must_use] + pub fn loop_count_reset_ch(&mut self) -> LOOP_COUNT_RESET_CH_W { + LOOP_COUNT_RESET_CH_W::new(self, 20) + } + #[doc = "Bit 21 - This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s."] + #[inline(always)] + #[must_use] + pub fn loop_stop_en_ch(&mut self) -> LOOP_STOP_EN_CH_W { + LOOP_STOP_EN_CH_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel %s Tx event configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_tx_lim::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_tx_lim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_TX_LIM_SPEC; +impl crate::RegisterSpec for CH_TX_LIM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_tx_lim::R`](R) reader structure"] +impl crate::Readable for CH_TX_LIM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_tx_lim::W`](W) writer structure"] +impl crate::Writable for CH_TX_LIM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH%s_TX_LIM to value 0x80"] +impl crate::Resettable for CH_TX_LIM_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/rmt/chcarrier_duty.rs b/esp32p4/src/rmt/chcarrier_duty.rs new file mode 100644 index 0000000000..389d7010a0 --- /dev/null +++ b/esp32p4/src/rmt/chcarrier_duty.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CH%sCARRIER_DUTY` reader"] +pub type R = crate::R; +#[doc = "Register `CH%sCARRIER_DUTY` writer"] +pub type W = crate::W; +#[doc = "Field `CARRIER_LOW_CH` reader - This register is used to configure carrier wave 's low level clock period for CHANNEL%s."] +pub type CARRIER_LOW_CH_R = crate::FieldReader; +#[doc = "Field `CARRIER_LOW_CH` writer - This register is used to configure carrier wave 's low level clock period for CHANNEL%s."] +pub type CARRIER_LOW_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CARRIER_HIGH_CH` reader - This register is used to configure carrier wave 's high level clock period for CHANNEL%s."] +pub type CARRIER_HIGH_CH_R = crate::FieldReader; +#[doc = "Field `CARRIER_HIGH_CH` writer - This register is used to configure carrier wave 's high level clock period for CHANNEL%s."] +pub type CARRIER_HIGH_CH_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to configure carrier wave 's low level clock period for CHANNEL%s."] + #[inline(always)] + pub fn carrier_low_ch(&self) -> CARRIER_LOW_CH_R { + CARRIER_LOW_CH_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - This register is used to configure carrier wave 's high level clock period for CHANNEL%s."] + #[inline(always)] + pub fn carrier_high_ch(&self) -> CARRIER_HIGH_CH_R { + CARRIER_HIGH_CH_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CHCARRIER_DUTY") + .field( + "carrier_low_ch", + &format_args!("{}", self.carrier_low_ch().bits()), + ) + .field( + "carrier_high_ch", + &format_args!("{}", self.carrier_high_ch().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to configure carrier wave 's low level clock period for CHANNEL%s."] + #[inline(always)] + #[must_use] + pub fn carrier_low_ch(&mut self) -> CARRIER_LOW_CH_W { + CARRIER_LOW_CH_W::new(self, 0) + } + #[doc = "Bits 16:31 - This register is used to configure carrier wave 's high level clock period for CHANNEL%s."] + #[inline(always)] + #[must_use] + pub fn carrier_high_ch(&mut self) -> CARRIER_HIGH_CH_W { + CARRIER_HIGH_CH_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel %s duty cycle configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chcarrier_duty::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chcarrier_duty::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHCARRIER_DUTY_SPEC; +impl crate::RegisterSpec for CHCARRIER_DUTY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chcarrier_duty::R`](R) reader structure"] +impl crate::Readable for CHCARRIER_DUTY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chcarrier_duty::W`](W) writer structure"] +impl crate::Writable for CHCARRIER_DUTY_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH%sCARRIER_DUTY to value 0x0040_0040"] +impl crate::Resettable for CHCARRIER_DUTY_SPEC { + const RESET_VALUE: Self::Ux = 0x0040_0040; +} diff --git a/esp32p4/src/rmt/date.rs b/esp32p4/src/rmt/date.rs new file mode 100644 index 0000000000..40e6cb3fc1 --- /dev/null +++ b/esp32p4/src/rmt/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - This is the version register."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - This is the version register."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - This is the version register."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - This is the version register."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RMT version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0220_1111"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_1111; +} diff --git a/esp32p4/src/rmt/int_clr.rs b/esp32p4/src/rmt/int_clr.rs new file mode 100644 index 0000000000..bbbb4b2410 --- /dev/null +++ b/esp32p4/src/rmt/int_clr.rs @@ -0,0 +1,278 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_TX_END_INT_CLR` writer - Set this bit to clear theCH0_TX_END_INT interrupt."] +pub type CH0_TX_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_TX_END_INT_CLR` writer - Set this bit to clear theCH1_TX_END_INT interrupt."] +pub type CH1_TX_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_TX_END_INT_CLR` writer - Set this bit to clear theCH2_TX_END_INT interrupt."] +pub type CH2_TX_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_TX_END_INT_CLR` writer - Set this bit to clear theCH3_TX_END_INT interrupt."] +pub type CH3_TX_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH0_ERR_INT_CLR` writer - Set this bit to clear theCH0_ERR_INT interrupt."] +pub type TX_CH0_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH1_ERR_INT_CLR` writer - Set this bit to clear theCH1_ERR_INT interrupt."] +pub type TX_CH1_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH2_ERR_INT_CLR` writer - Set this bit to clear theCH2_ERR_INT interrupt."] +pub type TX_CH2_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH3_ERR_INT_CLR` writer - Set this bit to clear theCH3_ERR_INT interrupt."] +pub type TX_CH3_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH0_TX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt."] +pub type CH0_TX_THR_EVENT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_TX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt."] +pub type CH1_TX_THR_EVENT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_TX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt."] +pub type CH2_TX_THR_EVENT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_TX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt."] +pub type CH3_TX_THR_EVENT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH0_TX_LOOP_INT_CLR` writer - Set this bit to clear theCH0_TX_LOOP_INT interrupt."] +pub type CH0_TX_LOOP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_TX_LOOP_INT_CLR` writer - Set this bit to clear theCH1_TX_LOOP_INT interrupt."] +pub type CH1_TX_LOOP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_TX_LOOP_INT_CLR` writer - Set this bit to clear theCH2_TX_LOOP_INT interrupt."] +pub type CH2_TX_LOOP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_TX_LOOP_INT_CLR` writer - Set this bit to clear theCH3_TX_LOOP_INT interrupt."] +pub type CH3_TX_LOOP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_RX_END_INT_CLR` writer - Set this bit to clear theCH4_RX_END_INT interrupt."] +pub type CH4_RX_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5_RX_END_INT_CLR` writer - Set this bit to clear theCH5_RX_END_INT interrupt."] +pub type CH5_RX_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6_RX_END_INT_CLR` writer - Set this bit to clear theCH6_RX_END_INT interrupt."] +pub type CH6_RX_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7_RX_END_INT_CLR` writer - Set this bit to clear theCH7_RX_END_INT interrupt."] +pub type CH7_RX_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH4_ERR_INT_CLR` writer - Set this bit to clear theCH4_ERR_INT interrupt."] +pub type RX_CH4_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH5_ERR_INT_CLR` writer - Set this bit to clear theCH5_ERR_INT interrupt."] +pub type RX_CH5_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH6_ERR_INT_CLR` writer - Set this bit to clear theCH6_ERR_INT interrupt."] +pub type RX_CH6_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH7_ERR_INT_CLR` writer - Set this bit to clear theCH7_ERR_INT interrupt."] +pub type RX_CH7_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_RX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."] +pub type CH4_RX_THR_EVENT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5_RX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt."] +pub type CH5_RX_THR_EVENT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6_RX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt."] +pub type CH6_RX_THR_EVENT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7_RX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt."] +pub type CH7_RX_THR_EVENT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH3_DMA_ACCESS_FAIL_INT_CLR` writer - Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt."] +pub type TX_CH3_DMA_ACCESS_FAIL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH7_DMA_ACCESS_FAIL_INT_CLR` writer - Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt."] +pub type RX_CH7_DMA_ACCESS_FAIL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear theCH0_TX_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch0_tx_end_int_clr(&mut self) -> CH0_TX_END_INT_CLR_W { + CH0_TX_END_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear theCH1_TX_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch1_tx_end_int_clr(&mut self) -> CH1_TX_END_INT_CLR_W { + CH1_TX_END_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear theCH2_TX_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch2_tx_end_int_clr(&mut self) -> CH2_TX_END_INT_CLR_W { + CH2_TX_END_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear theCH3_TX_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch3_tx_end_int_clr(&mut self) -> CH3_TX_END_INT_CLR_W { + CH3_TX_END_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear theCH0_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn tx_ch0_err_int_clr(&mut self) -> TX_CH0_ERR_INT_CLR_W { + TX_CH0_ERR_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear theCH1_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn tx_ch1_err_int_clr(&mut self) -> TX_CH1_ERR_INT_CLR_W { + TX_CH1_ERR_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear theCH2_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn tx_ch2_err_int_clr(&mut self) -> TX_CH2_ERR_INT_CLR_W { + TX_CH2_ERR_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear theCH3_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn tx_ch3_err_int_clr(&mut self) -> TX_CH3_ERR_INT_CLR_W { + TX_CH3_ERR_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch0_tx_thr_event_int_clr(&mut self) -> CH0_TX_THR_EVENT_INT_CLR_W { + CH0_TX_THR_EVENT_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch1_tx_thr_event_int_clr(&mut self) -> CH1_TX_THR_EVENT_INT_CLR_W { + CH1_TX_THR_EVENT_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch2_tx_thr_event_int_clr(&mut self) -> CH2_TX_THR_EVENT_INT_CLR_W { + CH2_TX_THR_EVENT_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch3_tx_thr_event_int_clr(&mut self) -> CH3_TX_THR_EVENT_INT_CLR_W { + CH3_TX_THR_EVENT_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Set this bit to clear theCH0_TX_LOOP_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch0_tx_loop_int_clr(&mut self) -> CH0_TX_LOOP_INT_CLR_W { + CH0_TX_LOOP_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Set this bit to clear theCH1_TX_LOOP_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch1_tx_loop_int_clr(&mut self) -> CH1_TX_LOOP_INT_CLR_W { + CH1_TX_LOOP_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Set this bit to clear theCH2_TX_LOOP_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch2_tx_loop_int_clr(&mut self) -> CH2_TX_LOOP_INT_CLR_W { + CH2_TX_LOOP_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Set this bit to clear theCH3_TX_LOOP_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch3_tx_loop_int_clr(&mut self) -> CH3_TX_LOOP_INT_CLR_W { + CH3_TX_LOOP_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Set this bit to clear theCH4_RX_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch4_rx_end_int_clr(&mut self) -> CH4_RX_END_INT_CLR_W { + CH4_RX_END_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Set this bit to clear theCH5_RX_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch5_rx_end_int_clr(&mut self) -> CH5_RX_END_INT_CLR_W { + CH5_RX_END_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Set this bit to clear theCH6_RX_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch6_rx_end_int_clr(&mut self) -> CH6_RX_END_INT_CLR_W { + CH6_RX_END_INT_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Set this bit to clear theCH7_RX_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch7_rx_end_int_clr(&mut self) -> CH7_RX_END_INT_CLR_W { + CH7_RX_END_INT_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Set this bit to clear theCH4_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rx_ch4_err_int_clr(&mut self) -> RX_CH4_ERR_INT_CLR_W { + RX_CH4_ERR_INT_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to clear theCH5_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rx_ch5_err_int_clr(&mut self) -> RX_CH5_ERR_INT_CLR_W { + RX_CH5_ERR_INT_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to clear theCH6_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rx_ch6_err_int_clr(&mut self) -> RX_CH6_ERR_INT_CLR_W { + RX_CH6_ERR_INT_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Set this bit to clear theCH7_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rx_ch7_err_int_clr(&mut self) -> RX_CH7_ERR_INT_CLR_W { + RX_CH7_ERR_INT_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch4_rx_thr_event_int_clr(&mut self) -> CH4_RX_THR_EVENT_INT_CLR_W { + CH4_RX_THR_EVENT_INT_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch5_rx_thr_event_int_clr(&mut self) -> CH5_RX_THR_EVENT_INT_CLR_W { + CH5_RX_THR_EVENT_INT_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch6_rx_thr_event_int_clr(&mut self) -> CH6_RX_THR_EVENT_INT_CLR_W { + CH6_RX_THR_EVENT_INT_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn ch7_rx_thr_event_int_clr(&mut self) -> CH7_RX_THR_EVENT_INT_CLR_W { + CH7_RX_THR_EVENT_INT_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn tx_ch3_dma_access_fail_int_clr( + &mut self, + ) -> TX_CH3_DMA_ACCESS_FAIL_INT_CLR_W { + TX_CH3_DMA_ACCESS_FAIL_INT_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn rx_ch7_dma_access_fail_int_clr( + &mut self, + ) -> RX_CH7_DMA_ACCESS_FAIL_INT_CLR_W { + RX_CH7_DMA_ACCESS_FAIL_INT_CLR_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rmt/int_ena.rs b/esp32p4/src/rmt/int_ena.rs new file mode 100644 index 0000000000..32e395985d --- /dev/null +++ b/esp32p4/src/rmt/int_ena.rs @@ -0,0 +1,621 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_TX_END_INT_ENA` reader - The interrupt enable bit for CH0_TX_END_INT."] +pub type CH0_TX_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH0_TX_END_INT_ENA` writer - The interrupt enable bit for CH0_TX_END_INT."] +pub type CH0_TX_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_TX_END_INT_ENA` reader - The interrupt enable bit for CH1_TX_END_INT."] +pub type CH1_TX_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH1_TX_END_INT_ENA` writer - The interrupt enable bit for CH1_TX_END_INT."] +pub type CH1_TX_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_TX_END_INT_ENA` reader - The interrupt enable bit for CH2_TX_END_INT."] +pub type CH2_TX_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH2_TX_END_INT_ENA` writer - The interrupt enable bit for CH2_TX_END_INT."] +pub type CH2_TX_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_TX_END_INT_ENA` reader - The interrupt enable bit for CH3_TX_END_INT."] +pub type CH3_TX_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH3_TX_END_INT_ENA` writer - The interrupt enable bit for CH3_TX_END_INT."] +pub type CH3_TX_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH0_ERR_INT_ENA` reader - The interrupt enable bit for CH0_ERR_INT."] +pub type TX_CH0_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_CH0_ERR_INT_ENA` writer - The interrupt enable bit for CH0_ERR_INT."] +pub type TX_CH0_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH1_ERR_INT_ENA` reader - The interrupt enable bit for CH1_ERR_INT."] +pub type TX_CH1_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_CH1_ERR_INT_ENA` writer - The interrupt enable bit for CH1_ERR_INT."] +pub type TX_CH1_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH2_ERR_INT_ENA` reader - The interrupt enable bit for CH2_ERR_INT."] +pub type TX_CH2_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_CH2_ERR_INT_ENA` writer - The interrupt enable bit for CH2_ERR_INT."] +pub type TX_CH2_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH3_ERR_INT_ENA` reader - The interrupt enable bit for CH3_ERR_INT."] +pub type TX_CH3_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_CH3_ERR_INT_ENA` writer - The interrupt enable bit for CH3_ERR_INT."] +pub type TX_CH3_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH0_TX_THR_EVENT_INT_ENA` reader - The interrupt enable bit for CH0_TX_THR_EVENT_INT."] +pub type CH0_TX_THR_EVENT_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH0_TX_THR_EVENT_INT_ENA` writer - The interrupt enable bit for CH0_TX_THR_EVENT_INT."] +pub type CH0_TX_THR_EVENT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_TX_THR_EVENT_INT_ENA` reader - The interrupt enable bit for CH1_TX_THR_EVENT_INT."] +pub type CH1_TX_THR_EVENT_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH1_TX_THR_EVENT_INT_ENA` writer - The interrupt enable bit for CH1_TX_THR_EVENT_INT."] +pub type CH1_TX_THR_EVENT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_TX_THR_EVENT_INT_ENA` reader - The interrupt enable bit for CH2_TX_THR_EVENT_INT."] +pub type CH2_TX_THR_EVENT_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH2_TX_THR_EVENT_INT_ENA` writer - The interrupt enable bit for CH2_TX_THR_EVENT_INT."] +pub type CH2_TX_THR_EVENT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_TX_THR_EVENT_INT_ENA` reader - The interrupt enable bit for CH3_TX_THR_EVENT_INT."] +pub type CH3_TX_THR_EVENT_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH3_TX_THR_EVENT_INT_ENA` writer - The interrupt enable bit for CH3_TX_THR_EVENT_INT."] +pub type CH3_TX_THR_EVENT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH0_TX_LOOP_INT_ENA` reader - The interrupt enable bit for CH0_TX_LOOP_INT."] +pub type CH0_TX_LOOP_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH0_TX_LOOP_INT_ENA` writer - The interrupt enable bit for CH0_TX_LOOP_INT."] +pub type CH0_TX_LOOP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_TX_LOOP_INT_ENA` reader - The interrupt enable bit for CH1_TX_LOOP_INT."] +pub type CH1_TX_LOOP_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH1_TX_LOOP_INT_ENA` writer - The interrupt enable bit for CH1_TX_LOOP_INT."] +pub type CH1_TX_LOOP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_TX_LOOP_INT_ENA` reader - The interrupt enable bit for CH2_TX_LOOP_INT."] +pub type CH2_TX_LOOP_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH2_TX_LOOP_INT_ENA` writer - The interrupt enable bit for CH2_TX_LOOP_INT."] +pub type CH2_TX_LOOP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_TX_LOOP_INT_ENA` reader - The interrupt enable bit for CH3_TX_LOOP_INT."] +pub type CH3_TX_LOOP_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH3_TX_LOOP_INT_ENA` writer - The interrupt enable bit for CH3_TX_LOOP_INT."] +pub type CH3_TX_LOOP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_RX_END_INT_ENA` reader - The interrupt enable bit for CH4_RX_END_INT."] +pub type CH4_RX_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH4_RX_END_INT_ENA` writer - The interrupt enable bit for CH4_RX_END_INT."] +pub type CH4_RX_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5_RX_END_INT_ENA` reader - The interrupt enable bit for CH5_RX_END_INT."] +pub type CH5_RX_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH5_RX_END_INT_ENA` writer - The interrupt enable bit for CH5_RX_END_INT."] +pub type CH5_RX_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6_RX_END_INT_ENA` reader - The interrupt enable bit for CH6_RX_END_INT."] +pub type CH6_RX_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH6_RX_END_INT_ENA` writer - The interrupt enable bit for CH6_RX_END_INT."] +pub type CH6_RX_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7_RX_END_INT_ENA` reader - The interrupt enable bit for CH7_RX_END_INT."] +pub type CH7_RX_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH7_RX_END_INT_ENA` writer - The interrupt enable bit for CH7_RX_END_INT."] +pub type CH7_RX_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_ERR_INT_ENA` reader - The interrupt enable bit for CH4_ERR_INT."] +pub type CH4_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH4_ERR_INT_ENA` writer - The interrupt enable bit for CH4_ERR_INT."] +pub type CH4_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5_ERR_INT_ENA` reader - The interrupt enable bit for CH5_ERR_INT."] +pub type CH5_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH5_ERR_INT_ENA` writer - The interrupt enable bit for CH5_ERR_INT."] +pub type CH5_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6_ERR_INT_ENA` reader - The interrupt enable bit for CH6_ERR_INT."] +pub type CH6_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH6_ERR_INT_ENA` writer - The interrupt enable bit for CH6_ERR_INT."] +pub type CH6_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7_ERR_INT_ENA` reader - The interrupt enable bit for CH7_ERR_INT."] +pub type CH7_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH7_ERR_INT_ENA` writer - The interrupt enable bit for CH7_ERR_INT."] +pub type CH7_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_RX_THR_EVENT_INT_ENA` reader - The interrupt enable bit for CH4_RX_THR_EVENT_INT."] +pub type CH4_RX_THR_EVENT_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH4_RX_THR_EVENT_INT_ENA` writer - The interrupt enable bit for CH4_RX_THR_EVENT_INT."] +pub type CH4_RX_THR_EVENT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5_RX_THR_EVENT_INT_ENA` reader - The interrupt enable bit for CH5_RX_THR_EVENT_INT."] +pub type CH5_RX_THR_EVENT_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH5_RX_THR_EVENT_INT_ENA` writer - The interrupt enable bit for CH5_RX_THR_EVENT_INT."] +pub type CH5_RX_THR_EVENT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6_RX_THR_EVENT_INT_ENA` reader - The interrupt enable bit for CH6_RX_THR_EVENT_INT."] +pub type CH6_RX_THR_EVENT_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH6_RX_THR_EVENT_INT_ENA` writer - The interrupt enable bit for CH6_RX_THR_EVENT_INT."] +pub type CH6_RX_THR_EVENT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7_RX_THR_EVENT_INT_ENA` reader - The interrupt enable bit for CH7_RX_THR_EVENT_INT."] +pub type CH7_RX_THR_EVENT_INT_ENA_R = crate::BitReader; +#[doc = "Field `CH7_RX_THR_EVENT_INT_ENA` writer - The interrupt enable bit for CH7_RX_THR_EVENT_INT."] +pub type CH7_RX_THR_EVENT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH3_DMA_ACCESS_FAIL_INT_ENA` reader - The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT."] +pub type TX_CH3_DMA_ACCESS_FAIL_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_CH3_DMA_ACCESS_FAIL_INT_ENA` writer - The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT."] +pub type TX_CH3_DMA_ACCESS_FAIL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH7_DMA_ACCESS_FAIL_INT_ENA` reader - The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT."] +pub type RX_CH7_DMA_ACCESS_FAIL_INT_ENA_R = crate::BitReader; +#[doc = "Field `RX_CH7_DMA_ACCESS_FAIL_INT_ENA` writer - The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT."] +pub type RX_CH7_DMA_ACCESS_FAIL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for CH0_TX_END_INT."] + #[inline(always)] + pub fn ch0_tx_end_int_ena(&self) -> CH0_TX_END_INT_ENA_R { + CH0_TX_END_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for CH1_TX_END_INT."] + #[inline(always)] + pub fn ch1_tx_end_int_ena(&self) -> CH1_TX_END_INT_ENA_R { + CH1_TX_END_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for CH2_TX_END_INT."] + #[inline(always)] + pub fn ch2_tx_end_int_ena(&self) -> CH2_TX_END_INT_ENA_R { + CH2_TX_END_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for CH3_TX_END_INT."] + #[inline(always)] + pub fn ch3_tx_end_int_ena(&self) -> CH3_TX_END_INT_ENA_R { + CH3_TX_END_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for CH0_ERR_INT."] + #[inline(always)] + pub fn tx_ch0_err_int_ena(&self) -> TX_CH0_ERR_INT_ENA_R { + TX_CH0_ERR_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for CH1_ERR_INT."] + #[inline(always)] + pub fn tx_ch1_err_int_ena(&self) -> TX_CH1_ERR_INT_ENA_R { + TX_CH1_ERR_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for CH2_ERR_INT."] + #[inline(always)] + pub fn tx_ch2_err_int_ena(&self) -> TX_CH2_ERR_INT_ENA_R { + TX_CH2_ERR_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for CH3_ERR_INT."] + #[inline(always)] + pub fn tx_ch3_err_int_ena(&self) -> TX_CH3_ERR_INT_ENA_R { + TX_CH3_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for CH0_TX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch0_tx_thr_event_int_ena(&self) -> CH0_TX_THR_EVENT_INT_ENA_R { + CH0_TX_THR_EVENT_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt enable bit for CH1_TX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch1_tx_thr_event_int_ena(&self) -> CH1_TX_THR_EVENT_INT_ENA_R { + CH1_TX_THR_EVENT_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The interrupt enable bit for CH2_TX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch2_tx_thr_event_int_ena(&self) -> CH2_TX_THR_EVENT_INT_ENA_R { + CH2_TX_THR_EVENT_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The interrupt enable bit for CH3_TX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch3_tx_thr_event_int_ena(&self) -> CH3_TX_THR_EVENT_INT_ENA_R { + CH3_TX_THR_EVENT_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The interrupt enable bit for CH0_TX_LOOP_INT."] + #[inline(always)] + pub fn ch0_tx_loop_int_ena(&self) -> CH0_TX_LOOP_INT_ENA_R { + CH0_TX_LOOP_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The interrupt enable bit for CH1_TX_LOOP_INT."] + #[inline(always)] + pub fn ch1_tx_loop_int_ena(&self) -> CH1_TX_LOOP_INT_ENA_R { + CH1_TX_LOOP_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The interrupt enable bit for CH2_TX_LOOP_INT."] + #[inline(always)] + pub fn ch2_tx_loop_int_ena(&self) -> CH2_TX_LOOP_INT_ENA_R { + CH2_TX_LOOP_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The interrupt enable bit for CH3_TX_LOOP_INT."] + #[inline(always)] + pub fn ch3_tx_loop_int_ena(&self) -> CH3_TX_LOOP_INT_ENA_R { + CH3_TX_LOOP_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The interrupt enable bit for CH4_RX_END_INT."] + #[inline(always)] + pub fn ch4_rx_end_int_ena(&self) -> CH4_RX_END_INT_ENA_R { + CH4_RX_END_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The interrupt enable bit for CH5_RX_END_INT."] + #[inline(always)] + pub fn ch5_rx_end_int_ena(&self) -> CH5_RX_END_INT_ENA_R { + CH5_RX_END_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The interrupt enable bit for CH6_RX_END_INT."] + #[inline(always)] + pub fn ch6_rx_end_int_ena(&self) -> CH6_RX_END_INT_ENA_R { + CH6_RX_END_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The interrupt enable bit for CH7_RX_END_INT."] + #[inline(always)] + pub fn ch7_rx_end_int_ena(&self) -> CH7_RX_END_INT_ENA_R { + CH7_RX_END_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The interrupt enable bit for CH4_ERR_INT."] + #[inline(always)] + pub fn ch4_err_int_ena(&self) -> CH4_ERR_INT_ENA_R { + CH4_ERR_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The interrupt enable bit for CH5_ERR_INT."] + #[inline(always)] + pub fn ch5_err_int_ena(&self) -> CH5_ERR_INT_ENA_R { + CH5_ERR_INT_ENA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - The interrupt enable bit for CH6_ERR_INT."] + #[inline(always)] + pub fn ch6_err_int_ena(&self) -> CH6_ERR_INT_ENA_R { + CH6_ERR_INT_ENA_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - The interrupt enable bit for CH7_ERR_INT."] + #[inline(always)] + pub fn ch7_err_int_ena(&self) -> CH7_ERR_INT_ENA_R { + CH7_ERR_INT_ENA_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - The interrupt enable bit for CH4_RX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch4_rx_thr_event_int_ena(&self) -> CH4_RX_THR_EVENT_INT_ENA_R { + CH4_RX_THR_EVENT_INT_ENA_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - The interrupt enable bit for CH5_RX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch5_rx_thr_event_int_ena(&self) -> CH5_RX_THR_EVENT_INT_ENA_R { + CH5_RX_THR_EVENT_INT_ENA_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - The interrupt enable bit for CH6_RX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch6_rx_thr_event_int_ena(&self) -> CH6_RX_THR_EVENT_INT_ENA_R { + CH6_RX_THR_EVENT_INT_ENA_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - The interrupt enable bit for CH7_RX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch7_rx_thr_event_int_ena(&self) -> CH7_RX_THR_EVENT_INT_ENA_R { + CH7_RX_THR_EVENT_INT_ENA_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT."] + #[inline(always)] + pub fn tx_ch3_dma_access_fail_int_ena(&self) -> TX_CH3_DMA_ACCESS_FAIL_INT_ENA_R { + TX_CH3_DMA_ACCESS_FAIL_INT_ENA_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT."] + #[inline(always)] + pub fn rx_ch7_dma_access_fail_int_ena(&self) -> RX_CH7_DMA_ACCESS_FAIL_INT_ENA_R { + RX_CH7_DMA_ACCESS_FAIL_INT_ENA_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "ch0_tx_end_int_ena", + &format_args!("{}", self.ch0_tx_end_int_ena().bit()), + ) + .field( + "ch1_tx_end_int_ena", + &format_args!("{}", self.ch1_tx_end_int_ena().bit()), + ) + .field( + "ch2_tx_end_int_ena", + &format_args!("{}", self.ch2_tx_end_int_ena().bit()), + ) + .field( + "ch3_tx_end_int_ena", + &format_args!("{}", self.ch3_tx_end_int_ena().bit()), + ) + .field( + "tx_ch0_err_int_ena", + &format_args!("{}", self.tx_ch0_err_int_ena().bit()), + ) + .field( + "tx_ch1_err_int_ena", + &format_args!("{}", self.tx_ch1_err_int_ena().bit()), + ) + .field( + "tx_ch2_err_int_ena", + &format_args!("{}", self.tx_ch2_err_int_ena().bit()), + ) + .field( + "tx_ch3_err_int_ena", + &format_args!("{}", self.tx_ch3_err_int_ena().bit()), + ) + .field( + "ch0_tx_thr_event_int_ena", + &format_args!("{}", self.ch0_tx_thr_event_int_ena().bit()), + ) + .field( + "ch1_tx_thr_event_int_ena", + &format_args!("{}", self.ch1_tx_thr_event_int_ena().bit()), + ) + .field( + "ch2_tx_thr_event_int_ena", + &format_args!("{}", self.ch2_tx_thr_event_int_ena().bit()), + ) + .field( + "ch3_tx_thr_event_int_ena", + &format_args!("{}", self.ch3_tx_thr_event_int_ena().bit()), + ) + .field( + "ch0_tx_loop_int_ena", + &format_args!("{}", self.ch0_tx_loop_int_ena().bit()), + ) + .field( + "ch1_tx_loop_int_ena", + &format_args!("{}", self.ch1_tx_loop_int_ena().bit()), + ) + .field( + "ch2_tx_loop_int_ena", + &format_args!("{}", self.ch2_tx_loop_int_ena().bit()), + ) + .field( + "ch3_tx_loop_int_ena", + &format_args!("{}", self.ch3_tx_loop_int_ena().bit()), + ) + .field( + "ch4_rx_end_int_ena", + &format_args!("{}", self.ch4_rx_end_int_ena().bit()), + ) + .field( + "ch5_rx_end_int_ena", + &format_args!("{}", self.ch5_rx_end_int_ena().bit()), + ) + .field( + "ch6_rx_end_int_ena", + &format_args!("{}", self.ch6_rx_end_int_ena().bit()), + ) + .field( + "ch7_rx_end_int_ena", + &format_args!("{}", self.ch7_rx_end_int_ena().bit()), + ) + .field( + "ch4_err_int_ena", + &format_args!("{}", self.ch4_err_int_ena().bit()), + ) + .field( + "ch5_err_int_ena", + &format_args!("{}", self.ch5_err_int_ena().bit()), + ) + .field( + "ch6_err_int_ena", + &format_args!("{}", self.ch6_err_int_ena().bit()), + ) + .field( + "ch7_err_int_ena", + &format_args!("{}", self.ch7_err_int_ena().bit()), + ) + .field( + "ch4_rx_thr_event_int_ena", + &format_args!("{}", self.ch4_rx_thr_event_int_ena().bit()), + ) + .field( + "ch5_rx_thr_event_int_ena", + &format_args!("{}", self.ch5_rx_thr_event_int_ena().bit()), + ) + .field( + "ch6_rx_thr_event_int_ena", + &format_args!("{}", self.ch6_rx_thr_event_int_ena().bit()), + ) + .field( + "ch7_rx_thr_event_int_ena", + &format_args!("{}", self.ch7_rx_thr_event_int_ena().bit()), + ) + .field( + "tx_ch3_dma_access_fail_int_ena", + &format_args!("{}", self.tx_ch3_dma_access_fail_int_ena().bit()), + ) + .field( + "rx_ch7_dma_access_fail_int_ena", + &format_args!("{}", self.rx_ch7_dma_access_fail_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for CH0_TX_END_INT."] + #[inline(always)] + #[must_use] + pub fn ch0_tx_end_int_ena(&mut self) -> CH0_TX_END_INT_ENA_W { + CH0_TX_END_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for CH1_TX_END_INT."] + #[inline(always)] + #[must_use] + pub fn ch1_tx_end_int_ena(&mut self) -> CH1_TX_END_INT_ENA_W { + CH1_TX_END_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for CH2_TX_END_INT."] + #[inline(always)] + #[must_use] + pub fn ch2_tx_end_int_ena(&mut self) -> CH2_TX_END_INT_ENA_W { + CH2_TX_END_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for CH3_TX_END_INT."] + #[inline(always)] + #[must_use] + pub fn ch3_tx_end_int_ena(&mut self) -> CH3_TX_END_INT_ENA_W { + CH3_TX_END_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for CH0_ERR_INT."] + #[inline(always)] + #[must_use] + pub fn tx_ch0_err_int_ena(&mut self) -> TX_CH0_ERR_INT_ENA_W { + TX_CH0_ERR_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for CH1_ERR_INT."] + #[inline(always)] + #[must_use] + pub fn tx_ch1_err_int_ena(&mut self) -> TX_CH1_ERR_INT_ENA_W { + TX_CH1_ERR_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for CH2_ERR_INT."] + #[inline(always)] + #[must_use] + pub fn tx_ch2_err_int_ena(&mut self) -> TX_CH2_ERR_INT_ENA_W { + TX_CH2_ERR_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for CH3_ERR_INT."] + #[inline(always)] + #[must_use] + pub fn tx_ch3_err_int_ena(&mut self) -> TX_CH3_ERR_INT_ENA_W { + TX_CH3_ERR_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for CH0_TX_THR_EVENT_INT."] + #[inline(always)] + #[must_use] + pub fn ch0_tx_thr_event_int_ena(&mut self) -> CH0_TX_THR_EVENT_INT_ENA_W { + CH0_TX_THR_EVENT_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt enable bit for CH1_TX_THR_EVENT_INT."] + #[inline(always)] + #[must_use] + pub fn ch1_tx_thr_event_int_ena(&mut self) -> CH1_TX_THR_EVENT_INT_ENA_W { + CH1_TX_THR_EVENT_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - The interrupt enable bit for CH2_TX_THR_EVENT_INT."] + #[inline(always)] + #[must_use] + pub fn ch2_tx_thr_event_int_ena(&mut self) -> CH2_TX_THR_EVENT_INT_ENA_W { + CH2_TX_THR_EVENT_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - The interrupt enable bit for CH3_TX_THR_EVENT_INT."] + #[inline(always)] + #[must_use] + pub fn ch3_tx_thr_event_int_ena(&mut self) -> CH3_TX_THR_EVENT_INT_ENA_W { + CH3_TX_THR_EVENT_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - The interrupt enable bit for CH0_TX_LOOP_INT."] + #[inline(always)] + #[must_use] + pub fn ch0_tx_loop_int_ena(&mut self) -> CH0_TX_LOOP_INT_ENA_W { + CH0_TX_LOOP_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - The interrupt enable bit for CH1_TX_LOOP_INT."] + #[inline(always)] + #[must_use] + pub fn ch1_tx_loop_int_ena(&mut self) -> CH1_TX_LOOP_INT_ENA_W { + CH1_TX_LOOP_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - The interrupt enable bit for CH2_TX_LOOP_INT."] + #[inline(always)] + #[must_use] + pub fn ch2_tx_loop_int_ena(&mut self) -> CH2_TX_LOOP_INT_ENA_W { + CH2_TX_LOOP_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - The interrupt enable bit for CH3_TX_LOOP_INT."] + #[inline(always)] + #[must_use] + pub fn ch3_tx_loop_int_ena(&mut self) -> CH3_TX_LOOP_INT_ENA_W { + CH3_TX_LOOP_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - The interrupt enable bit for CH4_RX_END_INT."] + #[inline(always)] + #[must_use] + pub fn ch4_rx_end_int_ena(&mut self) -> CH4_RX_END_INT_ENA_W { + CH4_RX_END_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - The interrupt enable bit for CH5_RX_END_INT."] + #[inline(always)] + #[must_use] + pub fn ch5_rx_end_int_ena(&mut self) -> CH5_RX_END_INT_ENA_W { + CH5_RX_END_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 18 - The interrupt enable bit for CH6_RX_END_INT."] + #[inline(always)] + #[must_use] + pub fn ch6_rx_end_int_ena(&mut self) -> CH6_RX_END_INT_ENA_W { + CH6_RX_END_INT_ENA_W::new(self, 18) + } + #[doc = "Bit 19 - The interrupt enable bit for CH7_RX_END_INT."] + #[inline(always)] + #[must_use] + pub fn ch7_rx_end_int_ena(&mut self) -> CH7_RX_END_INT_ENA_W { + CH7_RX_END_INT_ENA_W::new(self, 19) + } + #[doc = "Bit 20 - The interrupt enable bit for CH4_ERR_INT."] + #[inline(always)] + #[must_use] + pub fn ch4_err_int_ena(&mut self) -> CH4_ERR_INT_ENA_W { + CH4_ERR_INT_ENA_W::new(self, 20) + } + #[doc = "Bit 21 - The interrupt enable bit for CH5_ERR_INT."] + #[inline(always)] + #[must_use] + pub fn ch5_err_int_ena(&mut self) -> CH5_ERR_INT_ENA_W { + CH5_ERR_INT_ENA_W::new(self, 21) + } + #[doc = "Bit 22 - The interrupt enable bit for CH6_ERR_INT."] + #[inline(always)] + #[must_use] + pub fn ch6_err_int_ena(&mut self) -> CH6_ERR_INT_ENA_W { + CH6_ERR_INT_ENA_W::new(self, 22) + } + #[doc = "Bit 23 - The interrupt enable bit for CH7_ERR_INT."] + #[inline(always)] + #[must_use] + pub fn ch7_err_int_ena(&mut self) -> CH7_ERR_INT_ENA_W { + CH7_ERR_INT_ENA_W::new(self, 23) + } + #[doc = "Bit 24 - The interrupt enable bit for CH4_RX_THR_EVENT_INT."] + #[inline(always)] + #[must_use] + pub fn ch4_rx_thr_event_int_ena(&mut self) -> CH4_RX_THR_EVENT_INT_ENA_W { + CH4_RX_THR_EVENT_INT_ENA_W::new(self, 24) + } + #[doc = "Bit 25 - The interrupt enable bit for CH5_RX_THR_EVENT_INT."] + #[inline(always)] + #[must_use] + pub fn ch5_rx_thr_event_int_ena(&mut self) -> CH5_RX_THR_EVENT_INT_ENA_W { + CH5_RX_THR_EVENT_INT_ENA_W::new(self, 25) + } + #[doc = "Bit 26 - The interrupt enable bit for CH6_RX_THR_EVENT_INT."] + #[inline(always)] + #[must_use] + pub fn ch6_rx_thr_event_int_ena(&mut self) -> CH6_RX_THR_EVENT_INT_ENA_W { + CH6_RX_THR_EVENT_INT_ENA_W::new(self, 26) + } + #[doc = "Bit 27 - The interrupt enable bit for CH7_RX_THR_EVENT_INT."] + #[inline(always)] + #[must_use] + pub fn ch7_rx_thr_event_int_ena(&mut self) -> CH7_RX_THR_EVENT_INT_ENA_W { + CH7_RX_THR_EVENT_INT_ENA_W::new(self, 27) + } + #[doc = "Bit 28 - The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT."] + #[inline(always)] + #[must_use] + pub fn tx_ch3_dma_access_fail_int_ena( + &mut self, + ) -> TX_CH3_DMA_ACCESS_FAIL_INT_ENA_W { + TX_CH3_DMA_ACCESS_FAIL_INT_ENA_W::new(self, 28) + } + #[doc = "Bit 29 - The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT."] + #[inline(always)] + #[must_use] + pub fn rx_ch7_dma_access_fail_int_ena( + &mut self, + ) -> RX_CH7_DMA_ACCESS_FAIL_INT_ENA_W { + RX_CH7_DMA_ACCESS_FAIL_INT_ENA_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rmt/int_raw.rs b/esp32p4/src/rmt/int_raw.rs new file mode 100644 index 0000000000..c3166152a4 --- /dev/null +++ b/esp32p4/src/rmt/int_raw.rs @@ -0,0 +1,621 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_TX_END_INT_RAW` reader - The interrupt raw bit for CHANNEL0. Triggered when transmission done."] +pub type CH0_TX_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH0_TX_END_INT_RAW` writer - The interrupt raw bit for CHANNEL0. Triggered when transmission done."] +pub type CH0_TX_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_TX_END_INT_RAW` reader - The interrupt raw bit for CHANNEL1. Triggered when transmission done."] +pub type CH1_TX_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH1_TX_END_INT_RAW` writer - The interrupt raw bit for CHANNEL1. Triggered when transmission done."] +pub type CH1_TX_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_TX_END_INT_RAW` reader - The interrupt raw bit for CHANNEL2. Triggered when transmission done."] +pub type CH2_TX_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH2_TX_END_INT_RAW` writer - The interrupt raw bit for CHANNEL2. Triggered when transmission done."] +pub type CH2_TX_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_TX_END_INT_RAW` reader - The interrupt raw bit for CHANNEL3. Triggered when transmission done."] +pub type CH3_TX_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH3_TX_END_INT_RAW` writer - The interrupt raw bit for CHANNEL3. Triggered when transmission done."] +pub type CH3_TX_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH0_ERR_INT_RAW` reader - The interrupt raw bit for CHANNEL0. Triggered when error occurs."] +pub type TX_CH0_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_CH0_ERR_INT_RAW` writer - The interrupt raw bit for CHANNEL0. Triggered when error occurs."] +pub type TX_CH0_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH1_ERR_INT_RAW` reader - The interrupt raw bit for CHANNEL1. Triggered when error occurs."] +pub type TX_CH1_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_CH1_ERR_INT_RAW` writer - The interrupt raw bit for CHANNEL1. Triggered when error occurs."] +pub type TX_CH1_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH2_ERR_INT_RAW` reader - The interrupt raw bit for CHANNEL2. Triggered when error occurs."] +pub type TX_CH2_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_CH2_ERR_INT_RAW` writer - The interrupt raw bit for CHANNEL2. Triggered when error occurs."] +pub type TX_CH2_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH3_ERR_INT_RAW` reader - The interrupt raw bit for CHANNEL3. Triggered when error occurs."] +pub type TX_CH3_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_CH3_ERR_INT_RAW` writer - The interrupt raw bit for CHANNEL3. Triggered when error occurs."] +pub type TX_CH3_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH0_TX_THR_EVENT_INT_RAW` reader - The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value."] +pub type CH0_TX_THR_EVENT_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH0_TX_THR_EVENT_INT_RAW` writer - The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value."] +pub type CH0_TX_THR_EVENT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_TX_THR_EVENT_INT_RAW` reader - The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value."] +pub type CH1_TX_THR_EVENT_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH1_TX_THR_EVENT_INT_RAW` writer - The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value."] +pub type CH1_TX_THR_EVENT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_TX_THR_EVENT_INT_RAW` reader - The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value."] +pub type CH2_TX_THR_EVENT_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH2_TX_THR_EVENT_INT_RAW` writer - The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value."] +pub type CH2_TX_THR_EVENT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_TX_THR_EVENT_INT_RAW` reader - The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value."] +pub type CH3_TX_THR_EVENT_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH3_TX_THR_EVENT_INT_RAW` writer - The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value."] +pub type CH3_TX_THR_EVENT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH0_TX_LOOP_INT_RAW` reader - The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value."] +pub type CH0_TX_LOOP_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH0_TX_LOOP_INT_RAW` writer - The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value."] +pub type CH0_TX_LOOP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1_TX_LOOP_INT_RAW` reader - The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value."] +pub type CH1_TX_LOOP_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH1_TX_LOOP_INT_RAW` writer - The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value."] +pub type CH1_TX_LOOP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2_TX_LOOP_INT_RAW` reader - The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value."] +pub type CH2_TX_LOOP_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH2_TX_LOOP_INT_RAW` writer - The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value."] +pub type CH2_TX_LOOP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3_TX_LOOP_INT_RAW` reader - The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value."] +pub type CH3_TX_LOOP_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH3_TX_LOOP_INT_RAW` writer - The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value."] +pub type CH3_TX_LOOP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_RX_END_INT_RAW` reader - The interrupt raw bit for CHANNEL4. Triggered when reception done."] +pub type CH4_RX_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH4_RX_END_INT_RAW` writer - The interrupt raw bit for CHANNEL4. Triggered when reception done."] +pub type CH4_RX_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5_RX_END_INT_RAW` reader - The interrupt raw bit for CHANNEL5. Triggered when reception done."] +pub type CH5_RX_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH5_RX_END_INT_RAW` writer - The interrupt raw bit for CHANNEL5. Triggered when reception done."] +pub type CH5_RX_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6_RX_END_INT_RAW` reader - The interrupt raw bit for CHANNEL6. Triggered when reception done."] +pub type CH6_RX_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH6_RX_END_INT_RAW` writer - The interrupt raw bit for CHANNEL6. Triggered when reception done."] +pub type CH6_RX_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7_RX_END_INT_RAW` reader - The interrupt raw bit for CHANNEL7. Triggered when reception done."] +pub type CH7_RX_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH7_RX_END_INT_RAW` writer - The interrupt raw bit for CHANNEL7. Triggered when reception done."] +pub type CH7_RX_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH4_ERR_INT_RAW` reader - The interrupt raw bit for CHANNEL4. Triggered when error occurs."] +pub type RX_CH4_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_CH4_ERR_INT_RAW` writer - The interrupt raw bit for CHANNEL4. Triggered when error occurs."] +pub type RX_CH4_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH5_ERR_INT_RAW` reader - The interrupt raw bit for CHANNEL5. Triggered when error occurs."] +pub type RX_CH5_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_CH5_ERR_INT_RAW` writer - The interrupt raw bit for CHANNEL5. Triggered when error occurs."] +pub type RX_CH5_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH6_ERR_INT_RAW` reader - The interrupt raw bit for CHANNEL6. Triggered when error occurs."] +pub type RX_CH6_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_CH6_ERR_INT_RAW` writer - The interrupt raw bit for CHANNEL6. Triggered when error occurs."] +pub type RX_CH6_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH7_ERR_INT_RAW` reader - The interrupt raw bit for CHANNEL7. Triggered when error occurs."] +pub type RX_CH7_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_CH7_ERR_INT_RAW` writer - The interrupt raw bit for CHANNEL7. Triggered when error occurs."] +pub type RX_CH7_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4_RX_THR_EVENT_INT_RAW` reader - The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value."] +pub type CH4_RX_THR_EVENT_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH4_RX_THR_EVENT_INT_RAW` writer - The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value."] +pub type CH4_RX_THR_EVENT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5_RX_THR_EVENT_INT_RAW` reader - The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value."] +pub type CH5_RX_THR_EVENT_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH5_RX_THR_EVENT_INT_RAW` writer - The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value."] +pub type CH5_RX_THR_EVENT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6_RX_THR_EVENT_INT_RAW` reader - The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value."] +pub type CH6_RX_THR_EVENT_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH6_RX_THR_EVENT_INT_RAW` writer - The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value."] +pub type CH6_RX_THR_EVENT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7_RX_THR_EVENT_INT_RAW` reader - The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value."] +pub type CH7_RX_THR_EVENT_INT_RAW_R = crate::BitReader; +#[doc = "Field `CH7_RX_THR_EVENT_INT_RAW` writer - The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value."] +pub type CH7_RX_THR_EVENT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CH3_DMA_ACCESS_FAIL_INT_RAW` reader - The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails."] +pub type TX_CH3_DMA_ACCESS_FAIL_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_CH3_DMA_ACCESS_FAIL_INT_RAW` writer - The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails."] +pub type TX_CH3_DMA_ACCESS_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_CH7_DMA_ACCESS_FAIL_INT_RAW` reader - The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails."] +pub type RX_CH7_DMA_ACCESS_FAIL_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_CH7_DMA_ACCESS_FAIL_INT_RAW` writer - The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails."] +pub type RX_CH7_DMA_ACCESS_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt raw bit for CHANNEL0. Triggered when transmission done."] + #[inline(always)] + pub fn ch0_tx_end_int_raw(&self) -> CH0_TX_END_INT_RAW_R { + CH0_TX_END_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt raw bit for CHANNEL1. Triggered when transmission done."] + #[inline(always)] + pub fn ch1_tx_end_int_raw(&self) -> CH1_TX_END_INT_RAW_R { + CH1_TX_END_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt raw bit for CHANNEL2. Triggered when transmission done."] + #[inline(always)] + pub fn ch2_tx_end_int_raw(&self) -> CH2_TX_END_INT_RAW_R { + CH2_TX_END_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt raw bit for CHANNEL3. Triggered when transmission done."] + #[inline(always)] + pub fn ch3_tx_end_int_raw(&self) -> CH3_TX_END_INT_RAW_R { + CH3_TX_END_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt raw bit for CHANNEL0. Triggered when error occurs."] + #[inline(always)] + pub fn tx_ch0_err_int_raw(&self) -> TX_CH0_ERR_INT_RAW_R { + TX_CH0_ERR_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt raw bit for CHANNEL1. Triggered when error occurs."] + #[inline(always)] + pub fn tx_ch1_err_int_raw(&self) -> TX_CH1_ERR_INT_RAW_R { + TX_CH1_ERR_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt raw bit for CHANNEL2. Triggered when error occurs."] + #[inline(always)] + pub fn tx_ch2_err_int_raw(&self) -> TX_CH2_ERR_INT_RAW_R { + TX_CH2_ERR_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt raw bit for CHANNEL3. Triggered when error occurs."] + #[inline(always)] + pub fn tx_ch3_err_int_raw(&self) -> TX_CH3_ERR_INT_RAW_R { + TX_CH3_ERR_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value."] + #[inline(always)] + pub fn ch0_tx_thr_event_int_raw(&self) -> CH0_TX_THR_EVENT_INT_RAW_R { + CH0_TX_THR_EVENT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value."] + #[inline(always)] + pub fn ch1_tx_thr_event_int_raw(&self) -> CH1_TX_THR_EVENT_INT_RAW_R { + CH1_TX_THR_EVENT_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value."] + #[inline(always)] + pub fn ch2_tx_thr_event_int_raw(&self) -> CH2_TX_THR_EVENT_INT_RAW_R { + CH2_TX_THR_EVENT_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value."] + #[inline(always)] + pub fn ch3_tx_thr_event_int_raw(&self) -> CH3_TX_THR_EVENT_INT_RAW_R { + CH3_TX_THR_EVENT_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value."] + #[inline(always)] + pub fn ch0_tx_loop_int_raw(&self) -> CH0_TX_LOOP_INT_RAW_R { + CH0_TX_LOOP_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value."] + #[inline(always)] + pub fn ch1_tx_loop_int_raw(&self) -> CH1_TX_LOOP_INT_RAW_R { + CH1_TX_LOOP_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value."] + #[inline(always)] + pub fn ch2_tx_loop_int_raw(&self) -> CH2_TX_LOOP_INT_RAW_R { + CH2_TX_LOOP_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value."] + #[inline(always)] + pub fn ch3_tx_loop_int_raw(&self) -> CH3_TX_LOOP_INT_RAW_R { + CH3_TX_LOOP_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The interrupt raw bit for CHANNEL4. Triggered when reception done."] + #[inline(always)] + pub fn ch4_rx_end_int_raw(&self) -> CH4_RX_END_INT_RAW_R { + CH4_RX_END_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The interrupt raw bit for CHANNEL5. Triggered when reception done."] + #[inline(always)] + pub fn ch5_rx_end_int_raw(&self) -> CH5_RX_END_INT_RAW_R { + CH5_RX_END_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The interrupt raw bit for CHANNEL6. Triggered when reception done."] + #[inline(always)] + pub fn ch6_rx_end_int_raw(&self) -> CH6_RX_END_INT_RAW_R { + CH6_RX_END_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The interrupt raw bit for CHANNEL7. Triggered when reception done."] + #[inline(always)] + pub fn ch7_rx_end_int_raw(&self) -> CH7_RX_END_INT_RAW_R { + CH7_RX_END_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The interrupt raw bit for CHANNEL4. Triggered when error occurs."] + #[inline(always)] + pub fn rx_ch4_err_int_raw(&self) -> RX_CH4_ERR_INT_RAW_R { + RX_CH4_ERR_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The interrupt raw bit for CHANNEL5. Triggered when error occurs."] + #[inline(always)] + pub fn rx_ch5_err_int_raw(&self) -> RX_CH5_ERR_INT_RAW_R { + RX_CH5_ERR_INT_RAW_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - The interrupt raw bit for CHANNEL6. Triggered when error occurs."] + #[inline(always)] + pub fn rx_ch6_err_int_raw(&self) -> RX_CH6_ERR_INT_RAW_R { + RX_CH6_ERR_INT_RAW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - The interrupt raw bit for CHANNEL7. Triggered when error occurs."] + #[inline(always)] + pub fn rx_ch7_err_int_raw(&self) -> RX_CH7_ERR_INT_RAW_R { + RX_CH7_ERR_INT_RAW_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value."] + #[inline(always)] + pub fn ch4_rx_thr_event_int_raw(&self) -> CH4_RX_THR_EVENT_INT_RAW_R { + CH4_RX_THR_EVENT_INT_RAW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value."] + #[inline(always)] + pub fn ch5_rx_thr_event_int_raw(&self) -> CH5_RX_THR_EVENT_INT_RAW_R { + CH5_RX_THR_EVENT_INT_RAW_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value."] + #[inline(always)] + pub fn ch6_rx_thr_event_int_raw(&self) -> CH6_RX_THR_EVENT_INT_RAW_R { + CH6_RX_THR_EVENT_INT_RAW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value."] + #[inline(always)] + pub fn ch7_rx_thr_event_int_raw(&self) -> CH7_RX_THR_EVENT_INT_RAW_R { + CH7_RX_THR_EVENT_INT_RAW_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails."] + #[inline(always)] + pub fn tx_ch3_dma_access_fail_int_raw(&self) -> TX_CH3_DMA_ACCESS_FAIL_INT_RAW_R { + TX_CH3_DMA_ACCESS_FAIL_INT_RAW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails."] + #[inline(always)] + pub fn rx_ch7_dma_access_fail_int_raw(&self) -> RX_CH7_DMA_ACCESS_FAIL_INT_RAW_R { + RX_CH7_DMA_ACCESS_FAIL_INT_RAW_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "ch0_tx_end_int_raw", + &format_args!("{}", self.ch0_tx_end_int_raw().bit()), + ) + .field( + "ch1_tx_end_int_raw", + &format_args!("{}", self.ch1_tx_end_int_raw().bit()), + ) + .field( + "ch2_tx_end_int_raw", + &format_args!("{}", self.ch2_tx_end_int_raw().bit()), + ) + .field( + "ch3_tx_end_int_raw", + &format_args!("{}", self.ch3_tx_end_int_raw().bit()), + ) + .field( + "tx_ch0_err_int_raw", + &format_args!("{}", self.tx_ch0_err_int_raw().bit()), + ) + .field( + "tx_ch1_err_int_raw", + &format_args!("{}", self.tx_ch1_err_int_raw().bit()), + ) + .field( + "tx_ch2_err_int_raw", + &format_args!("{}", self.tx_ch2_err_int_raw().bit()), + ) + .field( + "tx_ch3_err_int_raw", + &format_args!("{}", self.tx_ch3_err_int_raw().bit()), + ) + .field( + "ch0_tx_thr_event_int_raw", + &format_args!("{}", self.ch0_tx_thr_event_int_raw().bit()), + ) + .field( + "ch1_tx_thr_event_int_raw", + &format_args!("{}", self.ch1_tx_thr_event_int_raw().bit()), + ) + .field( + "ch2_tx_thr_event_int_raw", + &format_args!("{}", self.ch2_tx_thr_event_int_raw().bit()), + ) + .field( + "ch3_tx_thr_event_int_raw", + &format_args!("{}", self.ch3_tx_thr_event_int_raw().bit()), + ) + .field( + "ch0_tx_loop_int_raw", + &format_args!("{}", self.ch0_tx_loop_int_raw().bit()), + ) + .field( + "ch1_tx_loop_int_raw", + &format_args!("{}", self.ch1_tx_loop_int_raw().bit()), + ) + .field( + "ch2_tx_loop_int_raw", + &format_args!("{}", self.ch2_tx_loop_int_raw().bit()), + ) + .field( + "ch3_tx_loop_int_raw", + &format_args!("{}", self.ch3_tx_loop_int_raw().bit()), + ) + .field( + "ch4_rx_end_int_raw", + &format_args!("{}", self.ch4_rx_end_int_raw().bit()), + ) + .field( + "ch5_rx_end_int_raw", + &format_args!("{}", self.ch5_rx_end_int_raw().bit()), + ) + .field( + "ch6_rx_end_int_raw", + &format_args!("{}", self.ch6_rx_end_int_raw().bit()), + ) + .field( + "ch7_rx_end_int_raw", + &format_args!("{}", self.ch7_rx_end_int_raw().bit()), + ) + .field( + "rx_ch4_err_int_raw", + &format_args!("{}", self.rx_ch4_err_int_raw().bit()), + ) + .field( + "rx_ch5_err_int_raw", + &format_args!("{}", self.rx_ch5_err_int_raw().bit()), + ) + .field( + "rx_ch6_err_int_raw", + &format_args!("{}", self.rx_ch6_err_int_raw().bit()), + ) + .field( + "rx_ch7_err_int_raw", + &format_args!("{}", self.rx_ch7_err_int_raw().bit()), + ) + .field( + "ch4_rx_thr_event_int_raw", + &format_args!("{}", self.ch4_rx_thr_event_int_raw().bit()), + ) + .field( + "ch5_rx_thr_event_int_raw", + &format_args!("{}", self.ch5_rx_thr_event_int_raw().bit()), + ) + .field( + "ch6_rx_thr_event_int_raw", + &format_args!("{}", self.ch6_rx_thr_event_int_raw().bit()), + ) + .field( + "ch7_rx_thr_event_int_raw", + &format_args!("{}", self.ch7_rx_thr_event_int_raw().bit()), + ) + .field( + "tx_ch3_dma_access_fail_int_raw", + &format_args!("{}", self.tx_ch3_dma_access_fail_int_raw().bit()), + ) + .field( + "rx_ch7_dma_access_fail_int_raw", + &format_args!("{}", self.rx_ch7_dma_access_fail_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt raw bit for CHANNEL0. Triggered when transmission done."] + #[inline(always)] + #[must_use] + pub fn ch0_tx_end_int_raw(&mut self) -> CH0_TX_END_INT_RAW_W { + CH0_TX_END_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt raw bit for CHANNEL1. Triggered when transmission done."] + #[inline(always)] + #[must_use] + pub fn ch1_tx_end_int_raw(&mut self) -> CH1_TX_END_INT_RAW_W { + CH1_TX_END_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt raw bit for CHANNEL2. Triggered when transmission done."] + #[inline(always)] + #[must_use] + pub fn ch2_tx_end_int_raw(&mut self) -> CH2_TX_END_INT_RAW_W { + CH2_TX_END_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt raw bit for CHANNEL3. Triggered when transmission done."] + #[inline(always)] + #[must_use] + pub fn ch3_tx_end_int_raw(&mut self) -> CH3_TX_END_INT_RAW_W { + CH3_TX_END_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt raw bit for CHANNEL0. Triggered when error occurs."] + #[inline(always)] + #[must_use] + pub fn tx_ch0_err_int_raw(&mut self) -> TX_CH0_ERR_INT_RAW_W { + TX_CH0_ERR_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt raw bit for CHANNEL1. Triggered when error occurs."] + #[inline(always)] + #[must_use] + pub fn tx_ch1_err_int_raw(&mut self) -> TX_CH1_ERR_INT_RAW_W { + TX_CH1_ERR_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt raw bit for CHANNEL2. Triggered when error occurs."] + #[inline(always)] + #[must_use] + pub fn tx_ch2_err_int_raw(&mut self) -> TX_CH2_ERR_INT_RAW_W { + TX_CH2_ERR_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt raw bit for CHANNEL3. Triggered when error occurs."] + #[inline(always)] + #[must_use] + pub fn tx_ch3_err_int_raw(&mut self) -> TX_CH3_ERR_INT_RAW_W { + TX_CH3_ERR_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value."] + #[inline(always)] + #[must_use] + pub fn ch0_tx_thr_event_int_raw(&mut self) -> CH0_TX_THR_EVENT_INT_RAW_W { + CH0_TX_THR_EVENT_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value."] + #[inline(always)] + #[must_use] + pub fn ch1_tx_thr_event_int_raw(&mut self) -> CH1_TX_THR_EVENT_INT_RAW_W { + CH1_TX_THR_EVENT_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value."] + #[inline(always)] + #[must_use] + pub fn ch2_tx_thr_event_int_raw(&mut self) -> CH2_TX_THR_EVENT_INT_RAW_W { + CH2_TX_THR_EVENT_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value."] + #[inline(always)] + #[must_use] + pub fn ch3_tx_thr_event_int_raw(&mut self) -> CH3_TX_THR_EVENT_INT_RAW_W { + CH3_TX_THR_EVENT_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 12 - The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value."] + #[inline(always)] + #[must_use] + pub fn ch0_tx_loop_int_raw(&mut self) -> CH0_TX_LOOP_INT_RAW_W { + CH0_TX_LOOP_INT_RAW_W::new(self, 12) + } + #[doc = "Bit 13 - The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value."] + #[inline(always)] + #[must_use] + pub fn ch1_tx_loop_int_raw(&mut self) -> CH1_TX_LOOP_INT_RAW_W { + CH1_TX_LOOP_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 14 - The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value."] + #[inline(always)] + #[must_use] + pub fn ch2_tx_loop_int_raw(&mut self) -> CH2_TX_LOOP_INT_RAW_W { + CH2_TX_LOOP_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value."] + #[inline(always)] + #[must_use] + pub fn ch3_tx_loop_int_raw(&mut self) -> CH3_TX_LOOP_INT_RAW_W { + CH3_TX_LOOP_INT_RAW_W::new(self, 15) + } + #[doc = "Bit 16 - The interrupt raw bit for CHANNEL4. Triggered when reception done."] + #[inline(always)] + #[must_use] + pub fn ch4_rx_end_int_raw(&mut self) -> CH4_RX_END_INT_RAW_W { + CH4_RX_END_INT_RAW_W::new(self, 16) + } + #[doc = "Bit 17 - The interrupt raw bit for CHANNEL5. Triggered when reception done."] + #[inline(always)] + #[must_use] + pub fn ch5_rx_end_int_raw(&mut self) -> CH5_RX_END_INT_RAW_W { + CH5_RX_END_INT_RAW_W::new(self, 17) + } + #[doc = "Bit 18 - The interrupt raw bit for CHANNEL6. Triggered when reception done."] + #[inline(always)] + #[must_use] + pub fn ch6_rx_end_int_raw(&mut self) -> CH6_RX_END_INT_RAW_W { + CH6_RX_END_INT_RAW_W::new(self, 18) + } + #[doc = "Bit 19 - The interrupt raw bit for CHANNEL7. Triggered when reception done."] + #[inline(always)] + #[must_use] + pub fn ch7_rx_end_int_raw(&mut self) -> CH7_RX_END_INT_RAW_W { + CH7_RX_END_INT_RAW_W::new(self, 19) + } + #[doc = "Bit 20 - The interrupt raw bit for CHANNEL4. Triggered when error occurs."] + #[inline(always)] + #[must_use] + pub fn rx_ch4_err_int_raw(&mut self) -> RX_CH4_ERR_INT_RAW_W { + RX_CH4_ERR_INT_RAW_W::new(self, 20) + } + #[doc = "Bit 21 - The interrupt raw bit for CHANNEL5. Triggered when error occurs."] + #[inline(always)] + #[must_use] + pub fn rx_ch5_err_int_raw(&mut self) -> RX_CH5_ERR_INT_RAW_W { + RX_CH5_ERR_INT_RAW_W::new(self, 21) + } + #[doc = "Bit 22 - The interrupt raw bit for CHANNEL6. Triggered when error occurs."] + #[inline(always)] + #[must_use] + pub fn rx_ch6_err_int_raw(&mut self) -> RX_CH6_ERR_INT_RAW_W { + RX_CH6_ERR_INT_RAW_W::new(self, 22) + } + #[doc = "Bit 23 - The interrupt raw bit for CHANNEL7. Triggered when error occurs."] + #[inline(always)] + #[must_use] + pub fn rx_ch7_err_int_raw(&mut self) -> RX_CH7_ERR_INT_RAW_W { + RX_CH7_ERR_INT_RAW_W::new(self, 23) + } + #[doc = "Bit 24 - The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value."] + #[inline(always)] + #[must_use] + pub fn ch4_rx_thr_event_int_raw(&mut self) -> CH4_RX_THR_EVENT_INT_RAW_W { + CH4_RX_THR_EVENT_INT_RAW_W::new(self, 24) + } + #[doc = "Bit 25 - The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value."] + #[inline(always)] + #[must_use] + pub fn ch5_rx_thr_event_int_raw(&mut self) -> CH5_RX_THR_EVENT_INT_RAW_W { + CH5_RX_THR_EVENT_INT_RAW_W::new(self, 25) + } + #[doc = "Bit 26 - The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value."] + #[inline(always)] + #[must_use] + pub fn ch6_rx_thr_event_int_raw(&mut self) -> CH6_RX_THR_EVENT_INT_RAW_W { + CH6_RX_THR_EVENT_INT_RAW_W::new(self, 26) + } + #[doc = "Bit 27 - The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value."] + #[inline(always)] + #[must_use] + pub fn ch7_rx_thr_event_int_raw(&mut self) -> CH7_RX_THR_EVENT_INT_RAW_W { + CH7_RX_THR_EVENT_INT_RAW_W::new(self, 27) + } + #[doc = "Bit 28 - The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails."] + #[inline(always)] + #[must_use] + pub fn tx_ch3_dma_access_fail_int_raw( + &mut self, + ) -> TX_CH3_DMA_ACCESS_FAIL_INT_RAW_W { + TX_CH3_DMA_ACCESS_FAIL_INT_RAW_W::new(self, 28) + } + #[doc = "Bit 29 - The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails."] + #[inline(always)] + #[must_use] + pub fn rx_ch7_dma_access_fail_int_raw( + &mut self, + ) -> RX_CH7_DMA_ACCESS_FAIL_INT_RAW_W { + RX_CH7_DMA_ACCESS_FAIL_INT_RAW_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rmt/int_st.rs b/esp32p4/src/rmt/int_st.rs new file mode 100644 index 0000000000..285d1b9ba2 --- /dev/null +++ b/esp32p4/src/rmt/int_st.rs @@ -0,0 +1,358 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `CH0_TX_END_INT_ST` reader - The masked interrupt status bit for CH0_TX_END_INT."] +pub type CH0_TX_END_INT_ST_R = crate::BitReader; +#[doc = "Field `CH1_TX_END_INT_ST` reader - The masked interrupt status bit for CH1_TX_END_INT."] +pub type CH1_TX_END_INT_ST_R = crate::BitReader; +#[doc = "Field `CH2_TX_END_INT_ST` reader - The masked interrupt status bit for CH2_TX_END_INT."] +pub type CH2_TX_END_INT_ST_R = crate::BitReader; +#[doc = "Field `CH3_TX_END_INT_ST` reader - The masked interrupt status bit for CH3_TX_END_INT."] +pub type CH3_TX_END_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_CH0_ERR_INT_ST` reader - The masked interrupt status bit for CH0_ERR_INT."] +pub type TX_CH0_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_CH1_ERR_INT_ST` reader - The masked interrupt status bit for CH1_ERR_INT."] +pub type TX_CH1_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_CH2_ERR_INT_ST` reader - The masked interrupt status bit for CH2_ERR_INT."] +pub type TX_CH2_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_CH3_ERR_INT_ST` reader - The masked interrupt status bit for CH3_ERR_INT."] +pub type TX_CH3_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `CH0_TX_THR_EVENT_INT_ST` reader - The masked interrupt status bit for CH0_TX_THR_EVENT_INT."] +pub type CH0_TX_THR_EVENT_INT_ST_R = crate::BitReader; +#[doc = "Field `CH1_TX_THR_EVENT_INT_ST` reader - The masked interrupt status bit for CH1_TX_THR_EVENT_INT."] +pub type CH1_TX_THR_EVENT_INT_ST_R = crate::BitReader; +#[doc = "Field `CH2_TX_THR_EVENT_INT_ST` reader - The masked interrupt status bit for CH2_TX_THR_EVENT_INT."] +pub type CH2_TX_THR_EVENT_INT_ST_R = crate::BitReader; +#[doc = "Field `CH3_TX_THR_EVENT_INT_ST` reader - The masked interrupt status bit for CH3_TX_THR_EVENT_INT."] +pub type CH3_TX_THR_EVENT_INT_ST_R = crate::BitReader; +#[doc = "Field `CH0_TX_LOOP_INT_ST` reader - The masked interrupt status bit for CH0_TX_LOOP_INT."] +pub type CH0_TX_LOOP_INT_ST_R = crate::BitReader; +#[doc = "Field `CH1_TX_LOOP_INT_ST` reader - The masked interrupt status bit for CH1_TX_LOOP_INT."] +pub type CH1_TX_LOOP_INT_ST_R = crate::BitReader; +#[doc = "Field `CH2_TX_LOOP_INT_ST` reader - The masked interrupt status bit for CH2_TX_LOOP_INT."] +pub type CH2_TX_LOOP_INT_ST_R = crate::BitReader; +#[doc = "Field `CH3_TX_LOOP_INT_ST` reader - The masked interrupt status bit for CH3_TX_LOOP_INT."] +pub type CH3_TX_LOOP_INT_ST_R = crate::BitReader; +#[doc = "Field `CH4_RX_END_INT_ST` reader - The masked interrupt status bit for CH4_RX_END_INT."] +pub type CH4_RX_END_INT_ST_R = crate::BitReader; +#[doc = "Field `CH5_RX_END_INT_ST` reader - The masked interrupt status bit for CH5_RX_END_INT."] +pub type CH5_RX_END_INT_ST_R = crate::BitReader; +#[doc = "Field `CH6_RX_END_INT_ST` reader - The masked interrupt status bit for CH6_RX_END_INT."] +pub type CH6_RX_END_INT_ST_R = crate::BitReader; +#[doc = "Field `CH7_RX_END_INT_ST` reader - The masked interrupt status bit for CH7_RX_END_INT."] +pub type CH7_RX_END_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_CH4_ERR_INT_ST` reader - The masked interrupt status bit for CH4_ERR_INT."] +pub type RX_CH4_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_CH5_ERR_INT_ST` reader - The masked interrupt status bit for CH5_ERR_INT."] +pub type RX_CH5_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_CH6_ERR_INT_ST` reader - The masked interrupt status bit for CH6_ERR_INT."] +pub type RX_CH6_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_CH7_ERR_INT_ST` reader - The masked interrupt status bit for CH7_ERR_INT."] +pub type RX_CH7_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `CH4_RX_THR_EVENT_INT_ST` reader - The masked interrupt status bit for CH4_RX_THR_EVENT_INT."] +pub type CH4_RX_THR_EVENT_INT_ST_R = crate::BitReader; +#[doc = "Field `CH5_RX_THR_EVENT_INT_ST` reader - The masked interrupt status bit for CH5_RX_THR_EVENT_INT."] +pub type CH5_RX_THR_EVENT_INT_ST_R = crate::BitReader; +#[doc = "Field `CH6_RX_THR_EVENT_INT_ST` reader - The masked interrupt status bit for CH6_RX_THR_EVENT_INT."] +pub type CH6_RX_THR_EVENT_INT_ST_R = crate::BitReader; +#[doc = "Field `CH7_RX_THR_EVENT_INT_ST` reader - The masked interrupt status bit for CH7_RX_THR_EVENT_INT."] +pub type CH7_RX_THR_EVENT_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_CH3_DMA_ACCESS_FAIL_INT_ST` reader - The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT."] +pub type TX_CH3_DMA_ACCESS_FAIL_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_CH7_DMA_ACCESS_FAIL_INT_ST` reader - The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT."] +pub type RX_CH7_DMA_ACCESS_FAIL_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status bit for CH0_TX_END_INT."] + #[inline(always)] + pub fn ch0_tx_end_int_st(&self) -> CH0_TX_END_INT_ST_R { + CH0_TX_END_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status bit for CH1_TX_END_INT."] + #[inline(always)] + pub fn ch1_tx_end_int_st(&self) -> CH1_TX_END_INT_ST_R { + CH1_TX_END_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status bit for CH2_TX_END_INT."] + #[inline(always)] + pub fn ch2_tx_end_int_st(&self) -> CH2_TX_END_INT_ST_R { + CH2_TX_END_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The masked interrupt status bit for CH3_TX_END_INT."] + #[inline(always)] + pub fn ch3_tx_end_int_st(&self) -> CH3_TX_END_INT_ST_R { + CH3_TX_END_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The masked interrupt status bit for CH0_ERR_INT."] + #[inline(always)] + pub fn tx_ch0_err_int_st(&self) -> TX_CH0_ERR_INT_ST_R { + TX_CH0_ERR_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The masked interrupt status bit for CH1_ERR_INT."] + #[inline(always)] + pub fn tx_ch1_err_int_st(&self) -> TX_CH1_ERR_INT_ST_R { + TX_CH1_ERR_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The masked interrupt status bit for CH2_ERR_INT."] + #[inline(always)] + pub fn tx_ch2_err_int_st(&self) -> TX_CH2_ERR_INT_ST_R { + TX_CH2_ERR_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The masked interrupt status bit for CH3_ERR_INT."] + #[inline(always)] + pub fn tx_ch3_err_int_st(&self) -> TX_CH3_ERR_INT_ST_R { + TX_CH3_ERR_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The masked interrupt status bit for CH0_TX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch0_tx_thr_event_int_st(&self) -> CH0_TX_THR_EVENT_INT_ST_R { + CH0_TX_THR_EVENT_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The masked interrupt status bit for CH1_TX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch1_tx_thr_event_int_st(&self) -> CH1_TX_THR_EVENT_INT_ST_R { + CH1_TX_THR_EVENT_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The masked interrupt status bit for CH2_TX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch2_tx_thr_event_int_st(&self) -> CH2_TX_THR_EVENT_INT_ST_R { + CH2_TX_THR_EVENT_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The masked interrupt status bit for CH3_TX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch3_tx_thr_event_int_st(&self) -> CH3_TX_THR_EVENT_INT_ST_R { + CH3_TX_THR_EVENT_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The masked interrupt status bit for CH0_TX_LOOP_INT."] + #[inline(always)] + pub fn ch0_tx_loop_int_st(&self) -> CH0_TX_LOOP_INT_ST_R { + CH0_TX_LOOP_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The masked interrupt status bit for CH1_TX_LOOP_INT."] + #[inline(always)] + pub fn ch1_tx_loop_int_st(&self) -> CH1_TX_LOOP_INT_ST_R { + CH1_TX_LOOP_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The masked interrupt status bit for CH2_TX_LOOP_INT."] + #[inline(always)] + pub fn ch2_tx_loop_int_st(&self) -> CH2_TX_LOOP_INT_ST_R { + CH2_TX_LOOP_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The masked interrupt status bit for CH3_TX_LOOP_INT."] + #[inline(always)] + pub fn ch3_tx_loop_int_st(&self) -> CH3_TX_LOOP_INT_ST_R { + CH3_TX_LOOP_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The masked interrupt status bit for CH4_RX_END_INT."] + #[inline(always)] + pub fn ch4_rx_end_int_st(&self) -> CH4_RX_END_INT_ST_R { + CH4_RX_END_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The masked interrupt status bit for CH5_RX_END_INT."] + #[inline(always)] + pub fn ch5_rx_end_int_st(&self) -> CH5_RX_END_INT_ST_R { + CH5_RX_END_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The masked interrupt status bit for CH6_RX_END_INT."] + #[inline(always)] + pub fn ch6_rx_end_int_st(&self) -> CH6_RX_END_INT_ST_R { + CH6_RX_END_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The masked interrupt status bit for CH7_RX_END_INT."] + #[inline(always)] + pub fn ch7_rx_end_int_st(&self) -> CH7_RX_END_INT_ST_R { + CH7_RX_END_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The masked interrupt status bit for CH4_ERR_INT."] + #[inline(always)] + pub fn rx_ch4_err_int_st(&self) -> RX_CH4_ERR_INT_ST_R { + RX_CH4_ERR_INT_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - The masked interrupt status bit for CH5_ERR_INT."] + #[inline(always)] + pub fn rx_ch5_err_int_st(&self) -> RX_CH5_ERR_INT_ST_R { + RX_CH5_ERR_INT_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - The masked interrupt status bit for CH6_ERR_INT."] + #[inline(always)] + pub fn rx_ch6_err_int_st(&self) -> RX_CH6_ERR_INT_ST_R { + RX_CH6_ERR_INT_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - The masked interrupt status bit for CH7_ERR_INT."] + #[inline(always)] + pub fn rx_ch7_err_int_st(&self) -> RX_CH7_ERR_INT_ST_R { + RX_CH7_ERR_INT_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - The masked interrupt status bit for CH4_RX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch4_rx_thr_event_int_st(&self) -> CH4_RX_THR_EVENT_INT_ST_R { + CH4_RX_THR_EVENT_INT_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - The masked interrupt status bit for CH5_RX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch5_rx_thr_event_int_st(&self) -> CH5_RX_THR_EVENT_INT_ST_R { + CH5_RX_THR_EVENT_INT_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - The masked interrupt status bit for CH6_RX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch6_rx_thr_event_int_st(&self) -> CH6_RX_THR_EVENT_INT_ST_R { + CH6_RX_THR_EVENT_INT_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - The masked interrupt status bit for CH7_RX_THR_EVENT_INT."] + #[inline(always)] + pub fn ch7_rx_thr_event_int_st(&self) -> CH7_RX_THR_EVENT_INT_ST_R { + CH7_RX_THR_EVENT_INT_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT."] + #[inline(always)] + pub fn tx_ch3_dma_access_fail_int_st(&self) -> TX_CH3_DMA_ACCESS_FAIL_INT_ST_R { + TX_CH3_DMA_ACCESS_FAIL_INT_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT."] + #[inline(always)] + pub fn rx_ch7_dma_access_fail_int_st(&self) -> RX_CH7_DMA_ACCESS_FAIL_INT_ST_R { + RX_CH7_DMA_ACCESS_FAIL_INT_ST_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "ch0_tx_end_int_st", + &format_args!("{}", self.ch0_tx_end_int_st().bit()), + ) + .field( + "ch1_tx_end_int_st", + &format_args!("{}", self.ch1_tx_end_int_st().bit()), + ) + .field( + "ch2_tx_end_int_st", + &format_args!("{}", self.ch2_tx_end_int_st().bit()), + ) + .field( + "ch3_tx_end_int_st", + &format_args!("{}", self.ch3_tx_end_int_st().bit()), + ) + .field( + "tx_ch0_err_int_st", + &format_args!("{}", self.tx_ch0_err_int_st().bit()), + ) + .field( + "tx_ch1_err_int_st", + &format_args!("{}", self.tx_ch1_err_int_st().bit()), + ) + .field( + "tx_ch2_err_int_st", + &format_args!("{}", self.tx_ch2_err_int_st().bit()), + ) + .field( + "tx_ch3_err_int_st", + &format_args!("{}", self.tx_ch3_err_int_st().bit()), + ) + .field( + "ch0_tx_thr_event_int_st", + &format_args!("{}", self.ch0_tx_thr_event_int_st().bit()), + ) + .field( + "ch1_tx_thr_event_int_st", + &format_args!("{}", self.ch1_tx_thr_event_int_st().bit()), + ) + .field( + "ch2_tx_thr_event_int_st", + &format_args!("{}", self.ch2_tx_thr_event_int_st().bit()), + ) + .field( + "ch3_tx_thr_event_int_st", + &format_args!("{}", self.ch3_tx_thr_event_int_st().bit()), + ) + .field( + "ch0_tx_loop_int_st", + &format_args!("{}", self.ch0_tx_loop_int_st().bit()), + ) + .field( + "ch1_tx_loop_int_st", + &format_args!("{}", self.ch1_tx_loop_int_st().bit()), + ) + .field( + "ch2_tx_loop_int_st", + &format_args!("{}", self.ch2_tx_loop_int_st().bit()), + ) + .field( + "ch3_tx_loop_int_st", + &format_args!("{}", self.ch3_tx_loop_int_st().bit()), + ) + .field( + "ch4_rx_end_int_st", + &format_args!("{}", self.ch4_rx_end_int_st().bit()), + ) + .field( + "ch5_rx_end_int_st", + &format_args!("{}", self.ch5_rx_end_int_st().bit()), + ) + .field( + "ch6_rx_end_int_st", + &format_args!("{}", self.ch6_rx_end_int_st().bit()), + ) + .field( + "ch7_rx_end_int_st", + &format_args!("{}", self.ch7_rx_end_int_st().bit()), + ) + .field( + "rx_ch4_err_int_st", + &format_args!("{}", self.rx_ch4_err_int_st().bit()), + ) + .field( + "rx_ch5_err_int_st", + &format_args!("{}", self.rx_ch5_err_int_st().bit()), + ) + .field( + "rx_ch6_err_int_st", + &format_args!("{}", self.rx_ch6_err_int_st().bit()), + ) + .field( + "rx_ch7_err_int_st", + &format_args!("{}", self.rx_ch7_err_int_st().bit()), + ) + .field( + "ch4_rx_thr_event_int_st", + &format_args!("{}", self.ch4_rx_thr_event_int_st().bit()), + ) + .field( + "ch5_rx_thr_event_int_st", + &format_args!("{}", self.ch5_rx_thr_event_int_st().bit()), + ) + .field( + "ch6_rx_thr_event_int_st", + &format_args!("{}", self.ch6_rx_thr_event_int_st().bit()), + ) + .field( + "ch7_rx_thr_event_int_st", + &format_args!("{}", self.ch7_rx_thr_event_int_st().bit()), + ) + .field( + "tx_ch3_dma_access_fail_int_st", + &format_args!("{}", self.tx_ch3_dma_access_fail_int_st().bit()), + ) + .field( + "rx_ch7_dma_access_fail_int_st", + &format_args!("{}", self.rx_ch7_dma_access_fail_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rmt/ref_cnt_rst.rs b/esp32p4/src/rmt/ref_cnt_rst.rs new file mode 100644 index 0000000000..de18f2e278 --- /dev/null +++ b/esp32p4/src/rmt/ref_cnt_rst.rs @@ -0,0 +1,98 @@ +#[doc = "Register `REF_CNT_RST` writer"] +pub type W = crate::W; +#[doc = "Field `TX_REF_CNT_RST_CH0` writer - This register is used to reset the clock divider of CHANNEL0."] +pub type TX_REF_CNT_RST_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_REF_CNT_RST_CH1` writer - This register is used to reset the clock divider of CHANNEL1."] +pub type TX_REF_CNT_RST_CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_REF_CNT_RST_CH2` writer - This register is used to reset the clock divider of CHANNEL2."] +pub type TX_REF_CNT_RST_CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_REF_CNT_RST_CH3` writer - This register is used to reset the clock divider of CHANNEL3."] +pub type TX_REF_CNT_RST_CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_REF_CNT_RST_CH4` writer - This register is used to reset the clock divider of CHANNEL4."] +pub type RX_REF_CNT_RST_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_REF_CNT_RST_CH5` writer - This register is used to reset the clock divider of CHANNEL5."] +pub type RX_REF_CNT_RST_CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_REF_CNT_RST_CH6` writer - This register is used to reset the clock divider of CHANNEL6."] +pub type RX_REF_CNT_RST_CH6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_REF_CNT_RST_CH7` writer - This register is used to reset the clock divider of CHANNEL7."] +pub type RX_REF_CNT_RST_CH7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - This register is used to reset the clock divider of CHANNEL0."] + #[inline(always)] + #[must_use] + pub fn tx_ref_cnt_rst_ch0(&mut self) -> TX_REF_CNT_RST_CH0_W { + TX_REF_CNT_RST_CH0_W::new(self, 0) + } + #[doc = "Bit 1 - This register is used to reset the clock divider of CHANNEL1."] + #[inline(always)] + #[must_use] + pub fn tx_ref_cnt_rst_ch1(&mut self) -> TX_REF_CNT_RST_CH1_W { + TX_REF_CNT_RST_CH1_W::new(self, 1) + } + #[doc = "Bit 2 - This register is used to reset the clock divider of CHANNEL2."] + #[inline(always)] + #[must_use] + pub fn tx_ref_cnt_rst_ch2(&mut self) -> TX_REF_CNT_RST_CH2_W { + TX_REF_CNT_RST_CH2_W::new(self, 2) + } + #[doc = "Bit 3 - This register is used to reset the clock divider of CHANNEL3."] + #[inline(always)] + #[must_use] + pub fn tx_ref_cnt_rst_ch3(&mut self) -> TX_REF_CNT_RST_CH3_W { + TX_REF_CNT_RST_CH3_W::new(self, 3) + } + #[doc = "Bit 4 - This register is used to reset the clock divider of CHANNEL4."] + #[inline(always)] + #[must_use] + pub fn rx_ref_cnt_rst_ch4(&mut self) -> RX_REF_CNT_RST_CH4_W { + RX_REF_CNT_RST_CH4_W::new(self, 4) + } + #[doc = "Bit 5 - This register is used to reset the clock divider of CHANNEL5."] + #[inline(always)] + #[must_use] + pub fn rx_ref_cnt_rst_ch5(&mut self) -> RX_REF_CNT_RST_CH5_W { + RX_REF_CNT_RST_CH5_W::new(self, 5) + } + #[doc = "Bit 6 - This register is used to reset the clock divider of CHANNEL6."] + #[inline(always)] + #[must_use] + pub fn rx_ref_cnt_rst_ch6(&mut self) -> RX_REF_CNT_RST_CH6_W { + RX_REF_CNT_RST_CH6_W::new(self, 6) + } + #[doc = "Bit 7 - This register is used to reset the clock divider of CHANNEL7."] + #[inline(always)] + #[must_use] + pub fn rx_ref_cnt_rst_ch7(&mut self) -> RX_REF_CNT_RST_CH7_W { + RX_REF_CNT_RST_CH7_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RMT clock divider reset register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_cnt_rst::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REF_CNT_RST_SPEC; +impl crate::RegisterSpec for REF_CNT_RST_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ref_cnt_rst::W`](W) writer structure"] +impl crate::Writable for REF_CNT_RST_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REF_CNT_RST to value 0"] +impl crate::Resettable for REF_CNT_RST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rmt/rx_chconf0.rs b/esp32p4/src/rmt/rx_chconf0.rs new file mode 100644 index 0000000000..30391ca04c --- /dev/null +++ b/esp32p4/src/rmt/rx_chconf0.rs @@ -0,0 +1,142 @@ +#[doc = "Register `RX_CH%sCONF0` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CH%sCONF0` writer"] +pub type W = crate::W; +#[doc = "Field `DIV_CNT_CH4` reader - This register is used to configure the divider for clock of CHANNEL%s."] +pub type DIV_CNT_CH4_R = crate::FieldReader; +#[doc = "Field `DIV_CNT_CH4` writer - This register is used to configure the divider for clock of CHANNEL%s."] +pub type DIV_CNT_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `IDLE_THRES_CH4` reader - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."] +pub type IDLE_THRES_CH4_R = crate::FieldReader; +#[doc = "Field `IDLE_THRES_CH4` writer - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."] +pub type IDLE_THRES_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `MEM_SIZE_CH4` reader - This register is used to configure the maximum size of memory allocated to CHANNEL%s."] +pub type MEM_SIZE_CH4_R = crate::FieldReader; +#[doc = "Field `MEM_SIZE_CH4` writer - This register is used to configure the maximum size of memory allocated to CHANNEL%s."] +pub type MEM_SIZE_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CARRIER_EN_CH4` reader - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."] +pub type CARRIER_EN_CH4_R = crate::BitReader; +#[doc = "Field `CARRIER_EN_CH4` writer - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."] +pub type CARRIER_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CARRIER_OUT_LV_CH4` reader - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."] +pub type CARRIER_OUT_LV_CH4_R = crate::BitReader; +#[doc = "Field `CARRIER_OUT_LV_CH4` writer - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."] +pub type CARRIER_OUT_LV_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."] + #[inline(always)] + pub fn div_cnt_ch4(&self) -> DIV_CNT_CH4_R { + DIV_CNT_CH4_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:22 - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."] + #[inline(always)] + pub fn idle_thres_ch4(&self) -> IDLE_THRES_CH4_R { + IDLE_THRES_CH4_R::new(((self.bits >> 8) & 0x7fff) as u16) + } + #[doc = "Bits 24:27 - This register is used to configure the maximum size of memory allocated to CHANNEL%s."] + #[inline(always)] + pub fn mem_size_ch4(&self) -> MEM_SIZE_CH4_R { + MEM_SIZE_CH4_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."] + #[inline(always)] + pub fn carrier_en_ch4(&self) -> CARRIER_EN_CH4_R { + CARRIER_EN_CH4_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."] + #[inline(always)] + pub fn carrier_out_lv_ch4(&self) -> CARRIER_OUT_LV_CH4_R { + CARRIER_OUT_LV_CH4_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CHCONF0") + .field( + "div_cnt_ch4", + &format_args!("{}", self.div_cnt_ch4().bits()), + ) + .field( + "idle_thres_ch4", + &format_args!("{}", self.idle_thres_ch4().bits()), + ) + .field( + "mem_size_ch4", + &format_args!("{}", self.mem_size_ch4().bits()), + ) + .field( + "carrier_en_ch4", + &format_args!("{}", self.carrier_en_ch4().bit()), + ) + .field( + "carrier_out_lv_ch4", + &format_args!("{}", self.carrier_out_lv_ch4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."] + #[inline(always)] + #[must_use] + pub fn div_cnt_ch4(&mut self) -> DIV_CNT_CH4_W { + DIV_CNT_CH4_W::new(self, 0) + } + #[doc = "Bits 8:22 - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."] + #[inline(always)] + #[must_use] + pub fn idle_thres_ch4(&mut self) -> IDLE_THRES_CH4_W { + IDLE_THRES_CH4_W::new(self, 8) + } + #[doc = "Bits 24:27 - This register is used to configure the maximum size of memory allocated to CHANNEL%s."] + #[inline(always)] + #[must_use] + pub fn mem_size_ch4(&mut self) -> MEM_SIZE_CH4_W { + MEM_SIZE_CH4_W::new(self, 24) + } + #[doc = "Bit 28 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."] + #[inline(always)] + #[must_use] + pub fn carrier_en_ch4(&mut self) -> CARRIER_EN_CH4_W { + CARRIER_EN_CH4_W::new(self, 28) + } + #[doc = "Bit 29 - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."] + #[inline(always)] + #[must_use] + pub fn carrier_out_lv_ch4(&mut self) -> CARRIER_OUT_LV_CH4_W { + CARRIER_OUT_LV_CH4_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel %s configure register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chconf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_chconf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CHCONF0_SPEC; +impl crate::RegisterSpec for RX_CHCONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_chconf0::R`](R) reader structure"] +impl crate::Readable for RX_CHCONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_chconf0::W`](W) writer structure"] +impl crate::Writable for RX_CHCONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CH%sCONF0 to value 0x317f_ff02"] +impl crate::Resettable for RX_CHCONF0_SPEC { + const RESET_VALUE: Self::Ux = 0x317f_ff02; +} diff --git a/esp32p4/src/rmt/rx_chconf1.rs b/esp32p4/src/rmt/rx_chconf1.rs new file mode 100644 index 0000000000..48b0d55140 --- /dev/null +++ b/esp32p4/src/rmt/rx_chconf1.rs @@ -0,0 +1,171 @@ +#[doc = "Register `RX_CH%sCONF1` reader"] +pub type R = crate::R; +#[doc = "Register `RX_CH%sCONF1` writer"] +pub type W = crate::W; +#[doc = "Field `RX_EN_CH4` reader - Set this bit to enable receiver to receive data on CHANNEL%s."] +pub type RX_EN_CH4_R = crate::BitReader; +#[doc = "Field `RX_EN_CH4` writer - Set this bit to enable receiver to receive data on CHANNEL%s."] +pub type RX_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_WR_RST_CH4` writer - Set this bit to reset write ram address for CHANNEL%s by accessing receiver."] +pub type MEM_WR_RST_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB_MEM_RST_CH4` writer - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo."] +pub type APB_MEM_RST_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_OWNER_CH4` reader - This register marks the ownership of CHANNEL%s's ram block.1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram."] +pub type MEM_OWNER_CH4_R = crate::BitReader; +#[doc = "Field `MEM_OWNER_CH4` writer - This register marks the ownership of CHANNEL%s's ram block.1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram."] +pub type MEM_OWNER_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FILTER_EN_CH4` reader - This is the receive filter's enable bit for CHANNEL%s."] +pub type RX_FILTER_EN_CH4_R = crate::BitReader; +#[doc = "Field `RX_FILTER_EN_CH4` writer - This is the receive filter's enable bit for CHANNEL%s."] +pub type RX_FILTER_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_FILTER_THRES_CH4` reader - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode)."] +pub type RX_FILTER_THRES_CH4_R = crate::FieldReader; +#[doc = "Field `RX_FILTER_THRES_CH4` writer - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode)."] +pub type RX_FILTER_THRES_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `MEM_RX_WRAP_EN_CH4` reader - This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size."] +pub type MEM_RX_WRAP_EN_CH4_R = crate::BitReader; +#[doc = "Field `MEM_RX_WRAP_EN_CH4` writer - This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size."] +pub type MEM_RX_WRAP_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AFIFO_RST_CH4` writer - Reserved"] +pub type AFIFO_RST_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CONF_UPDATE_CH4` writer - synchronization bit for CHANNEL%s"] +pub type CONF_UPDATE_CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable receiver to receive data on CHANNEL%s."] + #[inline(always)] + pub fn rx_en_ch4(&self) -> RX_EN_CH4_R { + RX_EN_CH4_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 3 - This register marks the ownership of CHANNEL%s's ram block.1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram."] + #[inline(always)] + pub fn mem_owner_ch4(&self) -> MEM_OWNER_CH4_R { + MEM_OWNER_CH4_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This is the receive filter's enable bit for CHANNEL%s."] + #[inline(always)] + pub fn rx_filter_en_ch4(&self) -> RX_FILTER_EN_CH4_R { + RX_FILTER_EN_CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:12 - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode)."] + #[inline(always)] + pub fn rx_filter_thres_ch4(&self) -> RX_FILTER_THRES_CH4_R { + RX_FILTER_THRES_CH4_R::new(((self.bits >> 5) & 0xff) as u8) + } + #[doc = "Bit 13 - This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size."] + #[inline(always)] + pub fn mem_rx_wrap_en_ch4(&self) -> MEM_RX_WRAP_EN_CH4_R { + MEM_RX_WRAP_EN_CH4_R::new(((self.bits >> 13) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CHCONF1") + .field("rx_en_ch4", &format_args!("{}", self.rx_en_ch4().bit())) + .field( + "mem_owner_ch4", + &format_args!("{}", self.mem_owner_ch4().bit()), + ) + .field( + "rx_filter_en_ch4", + &format_args!("{}", self.rx_filter_en_ch4().bit()), + ) + .field( + "rx_filter_thres_ch4", + &format_args!("{}", self.rx_filter_thres_ch4().bits()), + ) + .field( + "mem_rx_wrap_en_ch4", + &format_args!("{}", self.mem_rx_wrap_en_ch4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable receiver to receive data on CHANNEL%s."] + #[inline(always)] + #[must_use] + pub fn rx_en_ch4(&mut self) -> RX_EN_CH4_W { + RX_EN_CH4_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to reset write ram address for CHANNEL%s by accessing receiver."] + #[inline(always)] + #[must_use] + pub fn mem_wr_rst_ch4(&mut self) -> MEM_WR_RST_CH4_W { + MEM_WR_RST_CH4_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo."] + #[inline(always)] + #[must_use] + pub fn apb_mem_rst_ch4(&mut self) -> APB_MEM_RST_CH4_W { + APB_MEM_RST_CH4_W::new(self, 2) + } + #[doc = "Bit 3 - This register marks the ownership of CHANNEL%s's ram block.1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram."] + #[inline(always)] + #[must_use] + pub fn mem_owner_ch4(&mut self) -> MEM_OWNER_CH4_W { + MEM_OWNER_CH4_W::new(self, 3) + } + #[doc = "Bit 4 - This is the receive filter's enable bit for CHANNEL%s."] + #[inline(always)] + #[must_use] + pub fn rx_filter_en_ch4(&mut self) -> RX_FILTER_EN_CH4_W { + RX_FILTER_EN_CH4_W::new(self, 4) + } + #[doc = "Bits 5:12 - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode)."] + #[inline(always)] + #[must_use] + pub fn rx_filter_thres_ch4(&mut self) -> RX_FILTER_THRES_CH4_W { + RX_FILTER_THRES_CH4_W::new(self, 5) + } + #[doc = "Bit 13 - This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size."] + #[inline(always)] + #[must_use] + pub fn mem_rx_wrap_en_ch4(&mut self) -> MEM_RX_WRAP_EN_CH4_W { + MEM_RX_WRAP_EN_CH4_W::new(self, 13) + } + #[doc = "Bit 14 - Reserved"] + #[inline(always)] + #[must_use] + pub fn afifo_rst_ch4(&mut self) -> AFIFO_RST_CH4_W { + AFIFO_RST_CH4_W::new(self, 14) + } + #[doc = "Bit 15 - synchronization bit for CHANNEL%s"] + #[inline(always)] + #[must_use] + pub fn conf_update_ch4(&mut self) -> CONF_UPDATE_CH4_W { + CONF_UPDATE_CH4_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel %s configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chconf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_chconf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CHCONF1_SPEC; +impl crate::RegisterSpec for RX_CHCONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_chconf1::R`](R) reader structure"] +impl crate::Readable for RX_CHCONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_chconf1::W`](W) writer structure"] +impl crate::Writable for RX_CHCONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_CH%sCONF1 to value 0x01e8"] +impl crate::Resettable for RX_CHCONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x01e8; +} diff --git a/esp32p4/src/rmt/rx_chdata.rs b/esp32p4/src/rmt/rx_chdata.rs new file mode 100644 index 0000000000..14bdb7888e --- /dev/null +++ b/esp32p4/src/rmt/rx_chdata.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RX_CH%sDATA` reader"] +pub type R = crate::R; +#[doc = "Field `CHDATA` reader - Read and write data for channel 0 via APB FIFO."] +pub type CHDATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Read and write data for channel 0 via APB FIFO."] + #[inline(always)] + pub fn chdata(&self) -> CHDATA_R { + CHDATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CHDATA") + .field("chdata", &format_args!("{}", self.chdata().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The read and write data register for CHANNEL$n by apb fifo access.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chdata::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CHDATA_SPEC; +impl crate::RegisterSpec for RX_CHDATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_chdata::R`](R) reader structure"] +impl crate::Readable for RX_CHDATA_SPEC {} +#[doc = "`reset()` method sets RX_CH%sDATA to value 0"] +impl crate::Resettable for RX_CHDATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rmt/rx_chstatus.rs b/esp32p4/src/rmt/rx_chstatus.rs new file mode 100644 index 0000000000..99ad44d5d0 --- /dev/null +++ b/esp32p4/src/rmt/rx_chstatus.rs @@ -0,0 +1,91 @@ +#[doc = "Register `RX_CH%sSTATUS` reader"] +pub type R = crate::R; +#[doc = "Field `MEM_WADDR_EX_CH4` reader - This register records the memory address offset when receiver of CHANNEL%s is using the RAM."] +pub type MEM_WADDR_EX_CH4_R = crate::FieldReader; +#[doc = "Field `APB_MEM_RADDR_CH4` reader - This register records the memory address offset when reads RAM over APB bus."] +pub type APB_MEM_RADDR_CH4_R = crate::FieldReader; +#[doc = "Field `STATE_CH4` reader - This register records the FSM status of CHANNEL%s."] +pub type STATE_CH4_R = crate::FieldReader; +#[doc = "Field `MEM_OWNER_ERR_CH4` reader - This status bit will be set when the ownership of memory block is wrong."] +pub type MEM_OWNER_ERR_CH4_R = crate::BitReader; +#[doc = "Field `MEM_FULL_CH4` reader - This status bit will be set if the receiver receives more data than the memory size."] +pub type MEM_FULL_CH4_R = crate::BitReader; +#[doc = "Field `APB_MEM_RD_ERR_CH4` reader - This status bit will be set if the offset address out of memory size when reads via APB bus."] +pub type APB_MEM_RD_ERR_CH4_R = crate::BitReader; +impl R { + #[doc = "Bits 0:9 - This register records the memory address offset when receiver of CHANNEL%s is using the RAM."] + #[inline(always)] + pub fn mem_waddr_ex_ch4(&self) -> MEM_WADDR_EX_CH4_R { + MEM_WADDR_EX_CH4_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 11:20 - This register records the memory address offset when reads RAM over APB bus."] + #[inline(always)] + pub fn apb_mem_raddr_ch4(&self) -> APB_MEM_RADDR_CH4_R { + APB_MEM_RADDR_CH4_R::new(((self.bits >> 11) & 0x03ff) as u16) + } + #[doc = "Bits 22:24 - This register records the FSM status of CHANNEL%s."] + #[inline(always)] + pub fn state_ch4(&self) -> STATE_CH4_R { + STATE_CH4_R::new(((self.bits >> 22) & 7) as u8) + } + #[doc = "Bit 25 - This status bit will be set when the ownership of memory block is wrong."] + #[inline(always)] + pub fn mem_owner_err_ch4(&self) -> MEM_OWNER_ERR_CH4_R { + MEM_OWNER_ERR_CH4_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - This status bit will be set if the receiver receives more data than the memory size."] + #[inline(always)] + pub fn mem_full_ch4(&self) -> MEM_FULL_CH4_R { + MEM_FULL_CH4_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - This status bit will be set if the offset address out of memory size when reads via APB bus."] + #[inline(always)] + pub fn apb_mem_rd_err_ch4(&self) -> APB_MEM_RD_ERR_CH4_R { + APB_MEM_RD_ERR_CH4_R::new(((self.bits >> 27) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_CHSTATUS") + .field( + "mem_waddr_ex_ch4", + &format_args!("{}", self.mem_waddr_ex_ch4().bits()), + ) + .field( + "apb_mem_raddr_ch4", + &format_args!("{}", self.apb_mem_raddr_ch4().bits()), + ) + .field("state_ch4", &format_args!("{}", self.state_ch4().bits())) + .field( + "mem_owner_err_ch4", + &format_args!("{}", self.mem_owner_err_ch4().bit()), + ) + .field( + "mem_full_ch4", + &format_args!("{}", self.mem_full_ch4().bit()), + ) + .field( + "apb_mem_rd_err_ch4", + &format_args!("{}", self.apb_mem_rd_err_ch4().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_CHSTATUS_SPEC; +impl crate::RegisterSpec for RX_CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_chstatus::R`](R) reader structure"] +impl crate::Readable for RX_CHSTATUS_SPEC {} +#[doc = "`reset()` method sets RX_CH%sSTATUS to value 0x0006_00c0"] +impl crate::Resettable for RX_CHSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x0006_00c0; +} diff --git a/esp32p4/src/rmt/sys_conf.rs b/esp32p4/src/rmt/sys_conf.rs new file mode 100644 index 0000000000..d5c4c642ed --- /dev/null +++ b/esp32p4/src/rmt/sys_conf.rs @@ -0,0 +1,222 @@ +#[doc = "Register `SYS_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `SYS_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `APB_FIFO_MASK` reader - 1'h1: access memory directly. 1'h0: access memory by FIFO."] +pub type APB_FIFO_MASK_R = crate::BitReader; +#[doc = "Field `APB_FIFO_MASK` writer - 1'h1: access memory directly. 1'h0: access memory by FIFO."] +pub type APB_FIFO_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_CLK_FORCE_ON` reader - Set this bit to enable the clock for RMT memory."] +pub type MEM_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `MEM_CLK_FORCE_ON` writer - Set this bit to enable the clock for RMT memory."] +pub type MEM_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_FORCE_PD` reader - Set this bit to power down RMT memory."] +pub type MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PD` writer - Set this bit to power down RMT memory."] +pub type MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_FORCE_PU` reader - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."] +pub type MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PU` writer - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."] +pub type MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCLK_DIV_NUM` reader - the integral part of the fractional divisor"] +pub type SCLK_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_NUM` writer - the integral part of the fractional divisor"] +pub type SCLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SCLK_DIV_A` reader - the numerator of the fractional part of the fractional divisor"] +pub type SCLK_DIV_A_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_A` writer - the numerator of the fractional part of the fractional divisor"] +pub type SCLK_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_DIV_B` reader - the denominator of the fractional part of the fractional divisor"] +pub type SCLK_DIV_B_R = crate::FieldReader; +#[doc = "Field `SCLK_DIV_B` writer - the denominator of the fractional part of the fractional divisor"] +pub type SCLK_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SCLK_SEL` reader - choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL"] +pub type SCLK_SEL_R = crate::FieldReader; +#[doc = "Field `SCLK_SEL` writer - choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL"] +pub type SCLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SCLK_ACTIVE` reader - rmt_sclk switch"] +pub type SCLK_ACTIVE_R = crate::BitReader; +#[doc = "Field `SCLK_ACTIVE` writer - rmt_sclk switch"] +pub type SCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1'h1: access memory directly. 1'h0: access memory by FIFO."] + #[inline(always)] + pub fn apb_fifo_mask(&self) -> APB_FIFO_MASK_R { + APB_FIFO_MASK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to enable the clock for RMT memory."] + #[inline(always)] + pub fn mem_clk_force_on(&self) -> MEM_CLK_FORCE_ON_R { + MEM_CLK_FORCE_ON_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to power down RMT memory."] + #[inline(always)] + pub fn mem_force_pd(&self) -> MEM_FORCE_PD_R { + MEM_FORCE_PD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."] + #[inline(always)] + pub fn mem_force_pu(&self) -> MEM_FORCE_PU_R { + MEM_FORCE_PU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:11 - the integral part of the fractional divisor"] + #[inline(always)] + pub fn sclk_div_num(&self) -> SCLK_DIV_NUM_R { + SCLK_DIV_NUM_R::new(((self.bits >> 4) & 0xff) as u8) + } + #[doc = "Bits 12:17 - the numerator of the fractional part of the fractional divisor"] + #[inline(always)] + pub fn sclk_div_a(&self) -> SCLK_DIV_A_R { + SCLK_DIV_A_R::new(((self.bits >> 12) & 0x3f) as u8) + } + #[doc = "Bits 18:23 - the denominator of the fractional part of the fractional divisor"] + #[inline(always)] + pub fn sclk_div_b(&self) -> SCLK_DIV_B_R { + SCLK_DIV_B_R::new(((self.bits >> 18) & 0x3f) as u8) + } + #[doc = "Bits 24:25 - choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL"] + #[inline(always)] + pub fn sclk_sel(&self) -> SCLK_SEL_R { + SCLK_SEL_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 26 - rmt_sclk switch"] + #[inline(always)] + pub fn sclk_active(&self) -> SCLK_ACTIVE_R { + SCLK_ACTIVE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 31 - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYS_CONF") + .field( + "apb_fifo_mask", + &format_args!("{}", self.apb_fifo_mask().bit()), + ) + .field( + "mem_clk_force_on", + &format_args!("{}", self.mem_clk_force_on().bit()), + ) + .field( + "mem_force_pd", + &format_args!("{}", self.mem_force_pd().bit()), + ) + .field( + "mem_force_pu", + &format_args!("{}", self.mem_force_pu().bit()), + ) + .field( + "sclk_div_num", + &format_args!("{}", self.sclk_div_num().bits()), + ) + .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits())) + .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits())) + .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits())) + .field("sclk_active", &format_args!("{}", self.sclk_active().bit())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1'h1: access memory directly. 1'h0: access memory by FIFO."] + #[inline(always)] + #[must_use] + pub fn apb_fifo_mask(&mut self) -> APB_FIFO_MASK_W { + APB_FIFO_MASK_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to enable the clock for RMT memory."] + #[inline(always)] + #[must_use] + pub fn mem_clk_force_on(&mut self) -> MEM_CLK_FORCE_ON_W { + MEM_CLK_FORCE_ON_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to power down RMT memory."] + #[inline(always)] + #[must_use] + pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W { + MEM_FORCE_PD_W::new(self, 2) + } + #[doc = "Bit 3 - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode."] + #[inline(always)] + #[must_use] + pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W { + MEM_FORCE_PU_W::new(self, 3) + } + #[doc = "Bits 4:11 - the integral part of the fractional divisor"] + #[inline(always)] + #[must_use] + pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W { + SCLK_DIV_NUM_W::new(self, 4) + } + #[doc = "Bits 12:17 - the numerator of the fractional part of the fractional divisor"] + #[inline(always)] + #[must_use] + pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W { + SCLK_DIV_A_W::new(self, 12) + } + #[doc = "Bits 18:23 - the denominator of the fractional part of the fractional divisor"] + #[inline(always)] + #[must_use] + pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W { + SCLK_DIV_B_W::new(self, 18) + } + #[doc = "Bits 24:25 - choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL"] + #[inline(always)] + #[must_use] + pub fn sclk_sel(&mut self) -> SCLK_SEL_W { + SCLK_SEL_W::new(self, 24) + } + #[doc = "Bit 26 - rmt_sclk switch"] + #[inline(always)] + #[must_use] + pub fn sclk_active(&mut self) -> SCLK_ACTIVE_W { + SCLK_ACTIVE_W::new(self, 26) + } + #[doc = "Bit 31 - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RMT apb configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYS_CONF_SPEC; +impl crate::RegisterSpec for SYS_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sys_conf::R`](R) reader structure"] +impl crate::Readable for SYS_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sys_conf::W`](W) writer structure"] +impl crate::Writable for SYS_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SYS_CONF to value 0x0500_0010"] +impl crate::Resettable for SYS_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0500_0010; +} diff --git a/esp32p4/src/rmt/tx_chconf0.rs b/esp32p4/src/rmt/tx_chconf0.rs new file mode 100644 index 0000000000..7f346ff0eb --- /dev/null +++ b/esp32p4/src/rmt/tx_chconf0.rs @@ -0,0 +1,274 @@ +#[doc = "Register `TX_CH%sCONF0` reader"] +pub type R = crate::R; +#[doc = "Register `TX_CH%sCONF0` writer"] +pub type W = crate::W; +#[doc = "Field `TX_START_CH0` writer - Set this bit to start sending data on CHANNEL%s."] +pub type TX_START_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_RD_RST_CH0` writer - Set this bit to reset read ram address for CHANNEL%s by accessing transmitter."] +pub type MEM_RD_RST_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB_MEM_RST_CH0` writer - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo."] +pub type APB_MEM_RST_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CONTI_MODE_CH0` reader - Set this bit to restart transmission from the first data to the last data in CHANNEL%s."] +pub type TX_CONTI_MODE_CH0_R = crate::BitReader; +#[doc = "Field `TX_CONTI_MODE_CH0` writer - Set this bit to restart transmission from the first data to the last data in CHANNEL%s."] +pub type TX_CONTI_MODE_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_TX_WRAP_EN_CH0` reader - This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size."] +pub type MEM_TX_WRAP_EN_CH0_R = crate::BitReader; +#[doc = "Field `MEM_TX_WRAP_EN_CH0` writer - This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size."] +pub type MEM_TX_WRAP_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE_OUT_LV_CH0` reader - This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state."] +pub type IDLE_OUT_LV_CH0_R = crate::BitReader; +#[doc = "Field `IDLE_OUT_LV_CH0` writer - This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state."] +pub type IDLE_OUT_LV_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE_OUT_EN_CH0` reader - This is the output enable-control bit for CHANNEL%s in IDLE state."] +pub type IDLE_OUT_EN_CH0_R = crate::BitReader; +#[doc = "Field `IDLE_OUT_EN_CH0` writer - This is the output enable-control bit for CHANNEL%s in IDLE state."] +pub type IDLE_OUT_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_STOP_CH0` reader - Set this bit to stop the transmitter of CHANNEL%s sending data out."] +pub type TX_STOP_CH0_R = crate::BitReader; +#[doc = "Field `TX_STOP_CH0` writer - Set this bit to stop the transmitter of CHANNEL%s sending data out."] +pub type TX_STOP_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIV_CNT_CH0` reader - This register is used to configure the divider for clock of CHANNEL%s."] +pub type DIV_CNT_CH0_R = crate::FieldReader; +#[doc = "Field `DIV_CNT_CH0` writer - This register is used to configure the divider for clock of CHANNEL%s."] +pub type DIV_CNT_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `MEM_SIZE_CH0` reader - This register is used to configure the maximum size of memory allocated to CHANNEL%s."] +pub type MEM_SIZE_CH0_R = crate::FieldReader; +#[doc = "Field `MEM_SIZE_CH0` writer - This register is used to configure the maximum size of memory allocated to CHANNEL%s."] +pub type MEM_SIZE_CH0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CARRIER_EFF_EN_CH0` reader - 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1."] +pub type CARRIER_EFF_EN_CH0_R = crate::BitReader; +#[doc = "Field `CARRIER_EFF_EN_CH0` writer - 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1."] +pub type CARRIER_EFF_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CARRIER_EN_CH0` reader - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."] +pub type CARRIER_EN_CH0_R = crate::BitReader; +#[doc = "Field `CARRIER_EN_CH0` writer - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."] +pub type CARRIER_EN_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CARRIER_OUT_LV_CH0` reader - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."] +pub type CARRIER_OUT_LV_CH0_R = crate::BitReader; +#[doc = "Field `CARRIER_OUT_LV_CH0` writer - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."] +pub type CARRIER_OUT_LV_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AFIFO_RST_CH0` writer - Reserved"] +pub type AFIFO_RST_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CONF_UPDATE_CH0` writer - synchronization bit for CHANNEL%s"] +pub type CONF_UPDATE_CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 3 - Set this bit to restart transmission from the first data to the last data in CHANNEL%s."] + #[inline(always)] + pub fn tx_conti_mode_ch0(&self) -> TX_CONTI_MODE_CH0_R { + TX_CONTI_MODE_CH0_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size."] + #[inline(always)] + pub fn mem_tx_wrap_en_ch0(&self) -> MEM_TX_WRAP_EN_CH0_R { + MEM_TX_WRAP_EN_CH0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state."] + #[inline(always)] + pub fn idle_out_lv_ch0(&self) -> IDLE_OUT_LV_CH0_R { + IDLE_OUT_LV_CH0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This is the output enable-control bit for CHANNEL%s in IDLE state."] + #[inline(always)] + pub fn idle_out_en_ch0(&self) -> IDLE_OUT_EN_CH0_R { + IDLE_OUT_EN_CH0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set this bit to stop the transmitter of CHANNEL%s sending data out."] + #[inline(always)] + pub fn tx_stop_ch0(&self) -> TX_STOP_CH0_R { + TX_STOP_CH0_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:15 - This register is used to configure the divider for clock of CHANNEL%s."] + #[inline(always)] + pub fn div_cnt_ch0(&self) -> DIV_CNT_CH0_R { + DIV_CNT_CH0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:19 - This register is used to configure the maximum size of memory allocated to CHANNEL%s."] + #[inline(always)] + pub fn mem_size_ch0(&self) -> MEM_SIZE_CH0_R { + MEM_SIZE_CH0_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1."] + #[inline(always)] + pub fn carrier_eff_en_ch0(&self) -> CARRIER_EFF_EN_CH0_R { + CARRIER_EFF_EN_CH0_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."] + #[inline(always)] + pub fn carrier_en_ch0(&self) -> CARRIER_EN_CH0_R { + CARRIER_EN_CH0_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."] + #[inline(always)] + pub fn carrier_out_lv_ch0(&self) -> CARRIER_OUT_LV_CH0_R { + CARRIER_OUT_LV_CH0_R::new(((self.bits >> 22) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CHCONF0") + .field( + "tx_conti_mode_ch0", + &format_args!("{}", self.tx_conti_mode_ch0().bit()), + ) + .field( + "mem_tx_wrap_en_ch0", + &format_args!("{}", self.mem_tx_wrap_en_ch0().bit()), + ) + .field( + "idle_out_lv_ch0", + &format_args!("{}", self.idle_out_lv_ch0().bit()), + ) + .field( + "idle_out_en_ch0", + &format_args!("{}", self.idle_out_en_ch0().bit()), + ) + .field("tx_stop_ch0", &format_args!("{}", self.tx_stop_ch0().bit())) + .field( + "div_cnt_ch0", + &format_args!("{}", self.div_cnt_ch0().bits()), + ) + .field( + "mem_size_ch0", + &format_args!("{}", self.mem_size_ch0().bits()), + ) + .field( + "carrier_eff_en_ch0", + &format_args!("{}", self.carrier_eff_en_ch0().bit()), + ) + .field( + "carrier_en_ch0", + &format_args!("{}", self.carrier_en_ch0().bit()), + ) + .field( + "carrier_out_lv_ch0", + &format_args!("{}", self.carrier_out_lv_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to start sending data on CHANNEL%s."] + #[inline(always)] + #[must_use] + pub fn tx_start_ch0(&mut self) -> TX_START_CH0_W { + TX_START_CH0_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to reset read ram address for CHANNEL%s by accessing transmitter."] + #[inline(always)] + #[must_use] + pub fn mem_rd_rst_ch0(&mut self) -> MEM_RD_RST_CH0_W { + MEM_RD_RST_CH0_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo."] + #[inline(always)] + #[must_use] + pub fn apb_mem_rst_ch0(&mut self) -> APB_MEM_RST_CH0_W { + APB_MEM_RST_CH0_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to restart transmission from the first data to the last data in CHANNEL%s."] + #[inline(always)] + #[must_use] + pub fn tx_conti_mode_ch0(&mut self) -> TX_CONTI_MODE_CH0_W { + TX_CONTI_MODE_CH0_W::new(self, 3) + } + #[doc = "Bit 4 - This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size."] + #[inline(always)] + #[must_use] + pub fn mem_tx_wrap_en_ch0(&mut self) -> MEM_TX_WRAP_EN_CH0_W { + MEM_TX_WRAP_EN_CH0_W::new(self, 4) + } + #[doc = "Bit 5 - This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state."] + #[inline(always)] + #[must_use] + pub fn idle_out_lv_ch0(&mut self) -> IDLE_OUT_LV_CH0_W { + IDLE_OUT_LV_CH0_W::new(self, 5) + } + #[doc = "Bit 6 - This is the output enable-control bit for CHANNEL%s in IDLE state."] + #[inline(always)] + #[must_use] + pub fn idle_out_en_ch0(&mut self) -> IDLE_OUT_EN_CH0_W { + IDLE_OUT_EN_CH0_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to stop the transmitter of CHANNEL%s sending data out."] + #[inline(always)] + #[must_use] + pub fn tx_stop_ch0(&mut self) -> TX_STOP_CH0_W { + TX_STOP_CH0_W::new(self, 7) + } + #[doc = "Bits 8:15 - This register is used to configure the divider for clock of CHANNEL%s."] + #[inline(always)] + #[must_use] + pub fn div_cnt_ch0(&mut self) -> DIV_CNT_CH0_W { + DIV_CNT_CH0_W::new(self, 8) + } + #[doc = "Bits 16:19 - This register is used to configure the maximum size of memory allocated to CHANNEL%s."] + #[inline(always)] + #[must_use] + pub fn mem_size_ch0(&mut self) -> MEM_SIZE_CH0_W { + MEM_SIZE_CH0_W::new(self, 16) + } + #[doc = "Bit 20 - 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1."] + #[inline(always)] + #[must_use] + pub fn carrier_eff_en_ch0(&mut self) -> CARRIER_EFF_EN_CH0_W { + CARRIER_EFF_EN_CH0_W::new(self, 20) + } + #[doc = "Bit 21 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."] + #[inline(always)] + #[must_use] + pub fn carrier_en_ch0(&mut self) -> CARRIER_EN_CH0_W { + CARRIER_EN_CH0_W::new(self, 21) + } + #[doc = "Bit 22 - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."] + #[inline(always)] + #[must_use] + pub fn carrier_out_lv_ch0(&mut self) -> CARRIER_OUT_LV_CH0_W { + CARRIER_OUT_LV_CH0_W::new(self, 22) + } + #[doc = "Bit 23 - Reserved"] + #[inline(always)] + #[must_use] + pub fn afifo_rst_ch0(&mut self) -> AFIFO_RST_CH0_W { + AFIFO_RST_CH0_W::new(self, 23) + } + #[doc = "Bit 24 - synchronization bit for CHANNEL%s"] + #[inline(always)] + #[must_use] + pub fn conf_update_ch0(&mut self) -> CONF_UPDATE_CH0_W { + CONF_UPDATE_CH0_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel %s configure register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_chconf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_chconf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CHCONF0_SPEC; +impl crate::RegisterSpec for TX_CHCONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_chconf0::R`](R) reader structure"] +impl crate::Readable for TX_CHCONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_chconf0::W`](W) writer structure"] +impl crate::Writable for TX_CHCONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_CH%sCONF0 to value 0x0071_0200"] +impl crate::Resettable for TX_CHCONF0_SPEC { + const RESET_VALUE: Self::Ux = 0x0071_0200; +} diff --git a/esp32p4/src/rmt/tx_chdata.rs b/esp32p4/src/rmt/tx_chdata.rs new file mode 100644 index 0000000000..76c1df4b2c --- /dev/null +++ b/esp32p4/src/rmt/tx_chdata.rs @@ -0,0 +1,36 @@ +#[doc = "Register `TX_CH%sDATA` reader"] +pub type R = crate::R; +#[doc = "Field `CHDATA` reader - Read and write data for channel %s via APB FIFO."] +pub type CHDATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Read and write data for channel %s via APB FIFO."] + #[inline(always)] + pub fn chdata(&self) -> CHDATA_R { + CHDATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CHDATA") + .field("chdata", &format_args!("{}", self.chdata().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "The read and write data register for CHANNEL%s by apb fifo access.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_chdata::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CHDATA_SPEC; +impl crate::RegisterSpec for TX_CHDATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_chdata::R`](R) reader structure"] +impl crate::Readable for TX_CHDATA_SPEC {} +#[doc = "`reset()` method sets TX_CH%sDATA to value 0"] +impl crate::Resettable for TX_CHDATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rmt/tx_chstatus.rs b/esp32p4/src/rmt/tx_chstatus.rs new file mode 100644 index 0000000000..67d0d6ec82 --- /dev/null +++ b/esp32p4/src/rmt/tx_chstatus.rs @@ -0,0 +1,80 @@ +#[doc = "Register `TX_CH%sSTATUS` reader"] +pub type R = crate::R; +#[doc = "Field `MEM_RADDR_EX_CH0` reader - This register records the memory address offset when transmitter of CHANNEL%s is using the RAM."] +pub type MEM_RADDR_EX_CH0_R = crate::FieldReader; +#[doc = "Field `APB_MEM_WADDR_CH0` reader - This register records the memory address offset when writes RAM over APB bus."] +pub type APB_MEM_WADDR_CH0_R = crate::FieldReader; +#[doc = "Field `STATE_CH0` reader - This register records the FSM status of CHANNEL%s."] +pub type STATE_CH0_R = crate::FieldReader; +#[doc = "Field `MEM_EMPTY_CH0` reader - This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled."] +pub type MEM_EMPTY_CH0_R = crate::BitReader; +#[doc = "Field `APB_MEM_WR_ERR_CH0` reader - This status bit will be set if the offset address out of memory size when writes via APB bus."] +pub type APB_MEM_WR_ERR_CH0_R = crate::BitReader; +impl R { + #[doc = "Bits 0:9 - This register records the memory address offset when transmitter of CHANNEL%s is using the RAM."] + #[inline(always)] + pub fn mem_raddr_ex_ch0(&self) -> MEM_RADDR_EX_CH0_R { + MEM_RADDR_EX_CH0_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 11:20 - This register records the memory address offset when writes RAM over APB bus."] + #[inline(always)] + pub fn apb_mem_waddr_ch0(&self) -> APB_MEM_WADDR_CH0_R { + APB_MEM_WADDR_CH0_R::new(((self.bits >> 11) & 0x03ff) as u16) + } + #[doc = "Bits 22:24 - This register records the FSM status of CHANNEL%s."] + #[inline(always)] + pub fn state_ch0(&self) -> STATE_CH0_R { + STATE_CH0_R::new(((self.bits >> 22) & 7) as u8) + } + #[doc = "Bit 25 - This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled."] + #[inline(always)] + pub fn mem_empty_ch0(&self) -> MEM_EMPTY_CH0_R { + MEM_EMPTY_CH0_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - This status bit will be set if the offset address out of memory size when writes via APB bus."] + #[inline(always)] + pub fn apb_mem_wr_err_ch0(&self) -> APB_MEM_WR_ERR_CH0_R { + APB_MEM_WR_ERR_CH0_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_CHSTATUS") + .field( + "mem_raddr_ex_ch0", + &format_args!("{}", self.mem_raddr_ex_ch0().bits()), + ) + .field( + "apb_mem_waddr_ch0", + &format_args!("{}", self.apb_mem_waddr_ch0().bits()), + ) + .field("state_ch0", &format_args!("{}", self.state_ch0().bits())) + .field( + "mem_empty_ch0", + &format_args!("{}", self.mem_empty_ch0().bit()), + ) + .field( + "apb_mem_wr_err_ch0", + &format_args!("{}", self.apb_mem_wr_err_ch0().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_chstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_CHSTATUS_SPEC; +impl crate::RegisterSpec for TX_CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_chstatus::R`](R) reader structure"] +impl crate::Readable for TX_CHSTATUS_SPEC {} +#[doc = "`reset()` method sets TX_CH%sSTATUS to value 0"] +impl crate::Resettable for TX_CHSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rmt/tx_sim.rs b/esp32p4/src/rmt/tx_sim.rs new file mode 100644 index 0000000000..13bc0af374 --- /dev/null +++ b/esp32p4/src/rmt/tx_sim.rs @@ -0,0 +1,127 @@ +#[doc = "Register `TX_SIM` reader"] +pub type R = crate::R; +#[doc = "Register `TX_SIM` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels."] +pub type CH0_R = crate::BitReader; +#[doc = "Field `CH0` writer - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels."] +pub type CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels."] +pub type CH1_R = crate::BitReader; +#[doc = "Field `CH1` writer - Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels."] +pub type CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels."] +pub type CH2_R = crate::BitReader; +#[doc = "Field `CH2` writer - Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels."] +pub type CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels."] +pub type CH3_R = crate::BitReader; +#[doc = "Field `CH3` writer - Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels."] +pub type CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN` reader - This register is used to enable multiple of channels to start sending data synchronously."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - This register is used to enable multiple of channels to start sending data synchronously."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels."] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels."] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels."] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels."] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This register is used to enable multiple of channels to start sending data synchronously."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_SIM") + .field("ch0", &format_args!("{}", self.ch0().bit())) + .field("ch1", &format_args!("{}", self.ch1().bit())) + .field("ch2", &format_args!("{}", self.ch2().bit())) + .field("ch3", &format_args!("{}", self.ch3().bit())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels."] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> CH0_W { + CH0_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels."] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> CH1_W { + CH1_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels."] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> CH2_W { + CH2_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels."] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> CH3_W { + CH3_W::new(self, 3) + } + #[doc = "Bit 4 - This register is used to enable multiple of channels to start sending data synchronously."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RMT TX synchronous register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_sim::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_sim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_SIM_SPEC; +impl crate::RegisterSpec for TX_SIM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_sim::R`](R) reader structure"] +impl crate::Readable for TX_SIM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_sim::W`](W) writer structure"] +impl crate::Writable for TX_SIM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_SIM to value 0"] +impl crate::Resettable for TX_SIM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa.rs b/esp32p4/src/rsa.rs new file mode 100644 index 0000000000..43435a8ed4 --- /dev/null +++ b/esp32p4/src/rsa.rs @@ -0,0 +1,181 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + m_mem: [M_MEM; 16], + _reserved1: [u8; 0x01f0], + z_mem: [Z_MEM; 16], + _reserved2: [u8; 0x01f0], + y_mem: [Y_MEM; 16], + _reserved3: [u8; 0x01f0], + x_mem: [X_MEM; 16], + _reserved4: [u8; 0x01f0], + m_prime: M_PRIME, + mode: MODE, + query_clean: QUERY_CLEAN, + set_start_modexp: SET_START_MODEXP, + set_start_modmult: SET_START_MODMULT, + set_start_mult: SET_START_MULT, + query_idle: QUERY_IDLE, + int_clr: INT_CLR, + constant_time: CONSTANT_TIME, + search_enable: SEARCH_ENABLE, + search_pos: SEARCH_POS, + int_ena: INT_ENA, + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00..0x10 - Represents M"] + #[inline(always)] + pub const fn m_mem(&self, n: usize) -> &M_MEM { + &self.m_mem[n] + } + #[doc = "0x200..0x210 - Represents Z"] + #[inline(always)] + pub const fn z_mem(&self, n: usize) -> &Z_MEM { + &self.z_mem[n] + } + #[doc = "0x400..0x410 - Represents Y"] + #[inline(always)] + pub const fn y_mem(&self, n: usize) -> &Y_MEM { + &self.y_mem[n] + } + #[doc = "0x600..0x610 - Represents X"] + #[inline(always)] + pub const fn x_mem(&self, n: usize) -> &X_MEM { + &self.x_mem[n] + } + #[doc = "0x800 - Represents M’"] + #[inline(always)] + pub const fn m_prime(&self) -> &M_PRIME { + &self.m_prime + } + #[doc = "0x804 - Configures RSA length"] + #[inline(always)] + pub const fn mode(&self) -> &MODE { + &self.mode + } + #[doc = "0x808 - RSA clean register"] + #[inline(always)] + pub const fn query_clean(&self) -> &QUERY_CLEAN { + &self.query_clean + } + #[doc = "0x80c - Starts modular exponentiation"] + #[inline(always)] + pub const fn set_start_modexp(&self) -> &SET_START_MODEXP { + &self.set_start_modexp + } + #[doc = "0x810 - Starts modular multiplication"] + #[inline(always)] + pub const fn set_start_modmult(&self) -> &SET_START_MODMULT { + &self.set_start_modmult + } + #[doc = "0x814 - Starts multiplication"] + #[inline(always)] + pub const fn set_start_mult(&self) -> &SET_START_MULT { + &self.set_start_mult + } + #[doc = "0x818 - Represents the RSA status"] + #[inline(always)] + pub const fn query_idle(&self) -> &QUERY_IDLE { + &self.query_idle + } + #[doc = "0x81c - Clears RSA interrupt"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x820 - Configures the constant_time option"] + #[inline(always)] + pub const fn constant_time(&self) -> &CONSTANT_TIME { + &self.constant_time + } + #[doc = "0x824 - Configures the search option"] + #[inline(always)] + pub const fn search_enable(&self) -> &SEARCH_ENABLE { + &self.search_enable + } + #[doc = "0x828 - Configures the search position"] + #[inline(always)] + pub const fn search_pos(&self) -> &SEARCH_POS { + &self.search_pos + } + #[doc = "0x82c - Enables the RSA interrupt"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x830 - Version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "M_MEM (rw) register accessor: Represents M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@m_mem`] module"] +pub type M_MEM = crate::Reg; +#[doc = "Represents M"] +pub mod m_mem; +#[doc = "Z_MEM (rw) register accessor: Represents Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@z_mem`] module"] +pub type Z_MEM = crate::Reg; +#[doc = "Represents Z"] +pub mod z_mem; +#[doc = "Y_MEM (rw) register accessor: Represents Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@y_mem`] module"] +pub type Y_MEM = crate::Reg; +#[doc = "Represents Y"] +pub mod y_mem; +#[doc = "X_MEM (rw) register accessor: Represents X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@x_mem`] module"] +pub type X_MEM = crate::Reg; +#[doc = "Represents X"] +pub mod x_mem; +#[doc = "M_PRIME (rw) register accessor: Represents M’\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_prime::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_prime::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@m_prime`] module"] +pub type M_PRIME = crate::Reg; +#[doc = "Represents M’"] +pub mod m_prime; +#[doc = "MODE (rw) register accessor: Configures RSA length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`] module"] +pub type MODE = crate::Reg; +#[doc = "Configures RSA length"] +pub mod mode; +#[doc = "QUERY_CLEAN (r) register accessor: RSA clean register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_clean::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@query_clean`] module"] +pub type QUERY_CLEAN = crate::Reg; +#[doc = "RSA clean register"] +pub mod query_clean; +#[doc = "SET_START_MODEXP (w) register accessor: Starts modular exponentiation\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_start_modexp::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_start_modexp`] module"] +pub type SET_START_MODEXP = crate::Reg; +#[doc = "Starts modular exponentiation"] +pub mod set_start_modexp; +#[doc = "SET_START_MODMULT (w) register accessor: Starts modular multiplication\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_start_modmult::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_start_modmult`] module"] +pub type SET_START_MODMULT = crate::Reg; +#[doc = "Starts modular multiplication"] +pub mod set_start_modmult; +#[doc = "SET_START_MULT (w) register accessor: Starts multiplication\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_start_mult::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_start_mult`] module"] +pub type SET_START_MULT = crate::Reg; +#[doc = "Starts multiplication"] +pub mod set_start_mult; +#[doc = "QUERY_IDLE (r) register accessor: Represents the RSA status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_idle::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@query_idle`] module"] +pub type QUERY_IDLE = crate::Reg; +#[doc = "Represents the RSA status"] +pub mod query_idle; +#[doc = "INT_CLR (w) register accessor: Clears RSA interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Clears RSA interrupt"] +pub mod int_clr; +#[doc = "CONSTANT_TIME (rw) register accessor: Configures the constant_time option\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`constant_time::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`constant_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@constant_time`] module"] +pub type CONSTANT_TIME = crate::Reg; +#[doc = "Configures the constant_time option"] +pub mod constant_time; +#[doc = "SEARCH_ENABLE (rw) register accessor: Configures the search option\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`search_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`search_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@search_enable`] module"] +pub type SEARCH_ENABLE = crate::Reg; +#[doc = "Configures the search option"] +pub mod search_enable; +#[doc = "SEARCH_POS (rw) register accessor: Configures the search position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`search_pos::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`search_pos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@search_pos`] module"] +pub type SEARCH_POS = crate::Reg; +#[doc = "Configures the search position"] +pub mod search_pos; +#[doc = "INT_ENA (rw) register accessor: Enables the RSA interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Enables the RSA interrupt"] +pub mod int_ena; +#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version control register"] +pub mod date; diff --git a/esp32p4/src/rsa/constant_time.rs b/esp32p4/src/rsa/constant_time.rs new file mode 100644 index 0000000000..3479fc8ee7 --- /dev/null +++ b/esp32p4/src/rsa/constant_time.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CONSTANT_TIME` reader"] +pub type R = crate::R; +#[doc = "Register `CONSTANT_TIME` writer"] +pub type W = crate::W; +#[doc = "Field `CONSTANT_TIME` reader - Configures the constant_time option. 0: Acceleration 1: No acceleration (default)"] +pub type CONSTANT_TIME_R = crate::BitReader; +#[doc = "Field `CONSTANT_TIME` writer - Configures the constant_time option. 0: Acceleration 1: No acceleration (default)"] +pub type CONSTANT_TIME_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures the constant_time option. 0: Acceleration 1: No acceleration (default)"] + #[inline(always)] + pub fn constant_time(&self) -> CONSTANT_TIME_R { + CONSTANT_TIME_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONSTANT_TIME") + .field( + "constant_time", + &format_args!("{}", self.constant_time().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures the constant_time option. 0: Acceleration 1: No acceleration (default)"] + #[inline(always)] + #[must_use] + pub fn constant_time(&mut self) -> CONSTANT_TIME_W { + CONSTANT_TIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the constant_time option\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`constant_time::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`constant_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONSTANT_TIME_SPEC; +impl crate::RegisterSpec for CONSTANT_TIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`constant_time::R`](R) reader structure"] +impl crate::Readable for CONSTANT_TIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`constant_time::W`](W) writer structure"] +impl crate::Writable for CONSTANT_TIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONSTANT_TIME to value 0x01"] +impl crate::Resettable for CONSTANT_TIME_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/rsa/date.rs b/esp32p4/src/rsa/date.rs new file mode 100644 index 0000000000..2f2859296c --- /dev/null +++ b/esp32p4/src/rsa/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - Version control register."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - Version control register."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 0:29 - Version control register."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x3fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:29 - Version control register."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x2020_0618"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2020_0618; +} diff --git a/esp32p4/src/rsa/int_clr.rs b/esp32p4/src/rsa/int_clr.rs new file mode 100644 index 0000000000..75dacc58f1 --- /dev/null +++ b/esp32p4/src/rsa/int_clr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CLEAR_INTERRUPT` writer - Write 1 to clear the RSA interrupt."] +pub type CLEAR_INTERRUPT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to clear the RSA interrupt."] + #[inline(always)] + #[must_use] + pub fn clear_interrupt(&mut self) -> CLEAR_INTERRUPT_W { + CLEAR_INTERRUPT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clears RSA interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/int_ena.rs b/esp32p4/src/rsa/int_ena.rs new file mode 100644 index 0000000000..6d4963a8b6 --- /dev/null +++ b/esp32p4/src/rsa/int_ena.rs @@ -0,0 +1,63 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `INT_ENA` reader - Write 1 to enable the RSA interrupt."] +pub type INT_ENA_R = crate::BitReader; +#[doc = "Field `INT_ENA` writer - Write 1 to enable the RSA interrupt."] +pub type INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 to enable the RSA interrupt."] + #[inline(always)] + pub fn int_ena(&self) -> INT_ENA_R { + INT_ENA_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field("int_ena", &format_args!("{}", self.int_ena().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to enable the RSA interrupt."] + #[inline(always)] + #[must_use] + pub fn int_ena(&mut self) -> INT_ENA_W { + INT_ENA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Enables the RSA interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/m_mem.rs b/esp32p4/src/rsa/m_mem.rs new file mode 100644 index 0000000000..5e07318c45 --- /dev/null +++ b/esp32p4/src/rsa/m_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `M_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `M_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Represents M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M_MEM_SPEC; +impl crate::RegisterSpec for M_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`m_mem::R`](R) reader structure"] +impl crate::Readable for M_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m_mem::W`](W) writer structure"] +impl crate::Writable for M_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets M_MEM[%s] to value 0"] +impl crate::Resettable for M_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/m_prime.rs b/esp32p4/src/rsa/m_prime.rs new file mode 100644 index 0000000000..8ad9477f44 --- /dev/null +++ b/esp32p4/src/rsa/m_prime.rs @@ -0,0 +1,63 @@ +#[doc = "Register `M_PRIME` reader"] +pub type R = crate::R; +#[doc = "Register `M_PRIME` writer"] +pub type W = crate::W; +#[doc = "Field `M_PRIME` reader - Represents M’"] +pub type M_PRIME_R = crate::FieldReader; +#[doc = "Field `M_PRIME` writer - Represents M’"] +pub type M_PRIME_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Represents M’"] + #[inline(always)] + pub fn m_prime(&self) -> M_PRIME_R { + M_PRIME_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("M_PRIME") + .field("m_prime", &format_args!("{}", self.m_prime().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Represents M’"] + #[inline(always)] + #[must_use] + pub fn m_prime(&mut self) -> M_PRIME_W { + M_PRIME_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Represents M’\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_prime::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_prime::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M_PRIME_SPEC; +impl crate::RegisterSpec for M_PRIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`m_prime::R`](R) reader structure"] +impl crate::Readable for M_PRIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m_prime::W`](W) writer structure"] +impl crate::Writable for M_PRIME_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets M_PRIME to value 0"] +impl crate::Resettable for M_PRIME_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/mode.rs b/esp32p4/src/rsa/mode.rs new file mode 100644 index 0000000000..a9ab87cc41 --- /dev/null +++ b/esp32p4/src/rsa/mode.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MODE` reader"] +pub type R = crate::R; +#[doc = "Register `MODE` writer"] +pub type W = crate::W; +#[doc = "Field `MODE` reader - Configures the RSA length."] +pub type MODE_R = crate::FieldReader; +#[doc = "Field `MODE` writer - Configures the RSA length."] +pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Configures the RSA length."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new((self.bits & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MODE") + .field("mode", &format_args!("{}", self.mode().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:6 - Configures the RSA length."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures RSA length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MODE_SPEC; +impl crate::RegisterSpec for MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mode::R`](R) reader structure"] +impl crate::Readable for MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"] +impl crate::Writable for MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MODE to value 0"] +impl crate::Resettable for MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/query_clean.rs b/esp32p4/src/rsa/query_clean.rs new file mode 100644 index 0000000000..e8e52fb7dc --- /dev/null +++ b/esp32p4/src/rsa/query_clean.rs @@ -0,0 +1,36 @@ +#[doc = "Register `QUERY_CLEAN` reader"] +pub type R = crate::R; +#[doc = "Field `QUERY_CLEAN` reader - Represents whether or not the RSA memory completes initialization. 0: Not complete 1: Completed"] +pub type QUERY_CLEAN_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Represents whether or not the RSA memory completes initialization. 0: Not complete 1: Completed"] + #[inline(always)] + pub fn query_clean(&self) -> QUERY_CLEAN_R { + QUERY_CLEAN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("QUERY_CLEAN") + .field("query_clean", &format_args!("{}", self.query_clean().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RSA clean register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_clean::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QUERY_CLEAN_SPEC; +impl crate::RegisterSpec for QUERY_CLEAN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`query_clean::R`](R) reader structure"] +impl crate::Readable for QUERY_CLEAN_SPEC {} +#[doc = "`reset()` method sets QUERY_CLEAN to value 0"] +impl crate::Resettable for QUERY_CLEAN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/query_idle.rs b/esp32p4/src/rsa/query_idle.rs new file mode 100644 index 0000000000..0e16f2dc0b --- /dev/null +++ b/esp32p4/src/rsa/query_idle.rs @@ -0,0 +1,36 @@ +#[doc = "Register `QUERY_IDLE` reader"] +pub type R = crate::R; +#[doc = "Field `QUERY_IDLE` reader - Represents the RSA status. 0: Busy 1: Idle"] +pub type QUERY_IDLE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Represents the RSA status. 0: Busy 1: Idle"] + #[inline(always)] + pub fn query_idle(&self) -> QUERY_IDLE_R { + QUERY_IDLE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("QUERY_IDLE") + .field("query_idle", &format_args!("{}", self.query_idle().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Represents the RSA status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_idle::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QUERY_IDLE_SPEC; +impl crate::RegisterSpec for QUERY_IDLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`query_idle::R`](R) reader structure"] +impl crate::Readable for QUERY_IDLE_SPEC {} +#[doc = "`reset()` method sets QUERY_IDLE to value 0"] +impl crate::Resettable for QUERY_IDLE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/search_enable.rs b/esp32p4/src/rsa/search_enable.rs new file mode 100644 index 0000000000..4300db0bb2 --- /dev/null +++ b/esp32p4/src/rsa/search_enable.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SEARCH_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `SEARCH_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `SEARCH_ENABLE` reader - Configure the search option. 0: No acceleration (default) 1: Acceleration This option should be used together with RSA_SEARCH_POS."] +pub type SEARCH_ENABLE_R = crate::BitReader; +#[doc = "Field `SEARCH_ENABLE` writer - Configure the search option. 0: No acceleration (default) 1: Acceleration This option should be used together with RSA_SEARCH_POS."] +pub type SEARCH_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configure the search option. 0: No acceleration (default) 1: Acceleration This option should be used together with RSA_SEARCH_POS."] + #[inline(always)] + pub fn search_enable(&self) -> SEARCH_ENABLE_R { + SEARCH_ENABLE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SEARCH_ENABLE") + .field( + "search_enable", + &format_args!("{}", self.search_enable().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configure the search option. 0: No acceleration (default) 1: Acceleration This option should be used together with RSA_SEARCH_POS."] + #[inline(always)] + #[must_use] + pub fn search_enable(&mut self) -> SEARCH_ENABLE_W { + SEARCH_ENABLE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the search option\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`search_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`search_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SEARCH_ENABLE_SPEC; +impl crate::RegisterSpec for SEARCH_ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`search_enable::R`](R) reader structure"] +impl crate::Readable for SEARCH_ENABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`search_enable::W`](W) writer structure"] +impl crate::Writable for SEARCH_ENABLE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SEARCH_ENABLE to value 0"] +impl crate::Resettable for SEARCH_ENABLE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/search_pos.rs b/esp32p4/src/rsa/search_pos.rs new file mode 100644 index 0000000000..9b14cd22f4 --- /dev/null +++ b/esp32p4/src/rsa/search_pos.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SEARCH_POS` reader"] +pub type R = crate::R; +#[doc = "Register `SEARCH_POS` writer"] +pub type W = crate::W; +#[doc = "Field `SEARCH_POS` reader - Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high."] +pub type SEARCH_POS_R = crate::FieldReader; +#[doc = "Field `SEARCH_POS` writer - Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high."] +pub type SEARCH_POS_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high."] + #[inline(always)] + pub fn search_pos(&self) -> SEARCH_POS_R { + SEARCH_POS_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SEARCH_POS") + .field("search_pos", &format_args!("{}", self.search_pos().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high."] + #[inline(always)] + #[must_use] + pub fn search_pos(&mut self) -> SEARCH_POS_W { + SEARCH_POS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configures the search position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`search_pos::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`search_pos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SEARCH_POS_SPEC; +impl crate::RegisterSpec for SEARCH_POS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`search_pos::R`](R) reader structure"] +impl crate::Readable for SEARCH_POS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`search_pos::W`](W) writer structure"] +impl crate::Writable for SEARCH_POS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SEARCH_POS to value 0"] +impl crate::Resettable for SEARCH_POS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/set_start_modexp.rs b/esp32p4/src/rsa/set_start_modexp.rs new file mode 100644 index 0000000000..14ca750d03 --- /dev/null +++ b/esp32p4/src/rsa/set_start_modexp.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_START_MODEXP` writer"] +pub type W = crate::W; +#[doc = "Field `SET_START_MODEXP` writer - Configure whether or not to start the modular exponentiation. 0: No effect 1: Start"] +pub type SET_START_MODEXP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configure whether or not to start the modular exponentiation. 0: No effect 1: Start"] + #[inline(always)] + #[must_use] + pub fn set_start_modexp(&mut self) -> SET_START_MODEXP_W { + SET_START_MODEXP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Starts modular exponentiation\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_start_modexp::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_START_MODEXP_SPEC; +impl crate::RegisterSpec for SET_START_MODEXP_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_start_modexp::W`](W) writer structure"] +impl crate::Writable for SET_START_MODEXP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_START_MODEXP to value 0"] +impl crate::Resettable for SET_START_MODEXP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/set_start_modmult.rs b/esp32p4/src/rsa/set_start_modmult.rs new file mode 100644 index 0000000000..443a139842 --- /dev/null +++ b/esp32p4/src/rsa/set_start_modmult.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_START_MODMULT` writer"] +pub type W = crate::W; +#[doc = "Field `SET_START_MODMULT` writer - Configure whether or not to start the modular multiplication. 0: No effect 1: Start"] +pub type SET_START_MODMULT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configure whether or not to start the modular multiplication. 0: No effect 1: Start"] + #[inline(always)] + #[must_use] + pub fn set_start_modmult(&mut self) -> SET_START_MODMULT_W { + SET_START_MODMULT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Starts modular multiplication\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_start_modmult::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_START_MODMULT_SPEC; +impl crate::RegisterSpec for SET_START_MODMULT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_start_modmult::W`](W) writer structure"] +impl crate::Writable for SET_START_MODMULT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_START_MODMULT to value 0"] +impl crate::Resettable for SET_START_MODMULT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/set_start_mult.rs b/esp32p4/src/rsa/set_start_mult.rs new file mode 100644 index 0000000000..a566c1832d --- /dev/null +++ b/esp32p4/src/rsa/set_start_mult.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_START_MULT` writer"] +pub type W = crate::W; +#[doc = "Field `SET_START_MULT` writer - Configure whether or not to start the multiplication. 0: No effect 1: Start"] +pub type SET_START_MULT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configure whether or not to start the multiplication. 0: No effect 1: Start"] + #[inline(always)] + #[must_use] + pub fn set_start_mult(&mut self) -> SET_START_MULT_W { + SET_START_MULT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Starts multiplication\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set_start_mult::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_START_MULT_SPEC; +impl crate::RegisterSpec for SET_START_MULT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`set_start_mult::W`](W) writer structure"] +impl crate::Writable for SET_START_MULT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SET_START_MULT to value 0"] +impl crate::Resettable for SET_START_MULT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/x_mem.rs b/esp32p4/src/rsa/x_mem.rs new file mode 100644 index 0000000000..29d756b35e --- /dev/null +++ b/esp32p4/src/rsa/x_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `X_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `X_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Represents X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct X_MEM_SPEC; +impl crate::RegisterSpec for X_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`x_mem::R`](R) reader structure"] +impl crate::Readable for X_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`x_mem::W`](W) writer structure"] +impl crate::Writable for X_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets X_MEM[%s] to value 0"] +impl crate::Resettable for X_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/y_mem.rs b/esp32p4/src/rsa/y_mem.rs new file mode 100644 index 0000000000..ae0d53015c --- /dev/null +++ b/esp32p4/src/rsa/y_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `Y_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `Y_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Represents Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Y_MEM_SPEC; +impl crate::RegisterSpec for Y_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`y_mem::R`](R) reader structure"] +impl crate::Readable for Y_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`y_mem::W`](W) writer structure"] +impl crate::Writable for Y_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets Y_MEM[%s] to value 0"] +impl crate::Resettable for Y_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/rsa/z_mem.rs b/esp32p4/src/rsa/z_mem.rs new file mode 100644 index 0000000000..25603a57bf --- /dev/null +++ b/esp32p4/src/rsa/z_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `Z_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `Z_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Represents Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Z_MEM_SPEC; +impl crate::RegisterSpec for Z_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`z_mem::R`](R) reader structure"] +impl crate::Readable for Z_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`z_mem::W`](W) writer structure"] +impl crate::Writable for Z_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets Z_MEM[%s] to value 0"] +impl crate::Resettable for Z_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost.rs b/esp32p4/src/sdhost.rs new file mode 100644 index 0000000000..289a07728e --- /dev/null +++ b/esp32p4/src/sdhost.rs @@ -0,0 +1,454 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + ctrl: CTRL, + _reserved1: [u8; 0x04], + clkdiv: CLKDIV, + clksrc: CLKSRC, + clkena: CLKENA, + tmout: TMOUT, + ctype: CTYPE, + blksiz: BLKSIZ, + bytcnt: BYTCNT, + intmask: INTMASK, + cmdarg: CMDARG, + cmd: CMD, + resp0: RESP0, + resp1: RESP1, + resp2: RESP2, + resp3: RESP3, + mintsts: MINTSTS, + rintsts: RINTSTS, + status: STATUS, + fifoth: FIFOTH, + cdetect: CDETECT, + wrtprt: WRTPRT, + _reserved21: [u8; 0x04], + tcbcnt: TCBCNT, + tbbcnt: TBBCNT, + debnce: DEBNCE, + usrid: USRID, + verid: VERID, + hcon: HCON, + uhs: UHS, + rst_n: RST_N, + _reserved29: [u8; 0x04], + bmod: BMOD, + pldmnd: PLDMND, + dbaddr: DBADDR, + idsts: IDSTS, + idinten: IDINTEN, + dscaddr: DSCADDR, + bufaddr: BUFADDR, + _reserved36: [u8; 0x64], + cardthrctl: CARDTHRCTL, + _reserved37: [u8; 0x08], + emmcddr: EMMCDDR, + enshift: ENSHIFT, + _reserved39: [u8; 0xec], + buffifo: BUFFIFO, + _reserved40: [u8; 0x05fc], + clk_edge_sel: CLK_EDGE_SEL, + raw_ints: RAW_INTS, + dll_clk_conf: DLL_CLK_CONF, + dll_conf: DLL_CONF, +} +impl RegisterBlock { + #[doc = "0x00 - Control register"] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0x08 - Clock divider configuration register"] + #[inline(always)] + pub const fn clkdiv(&self) -> &CLKDIV { + &self.clkdiv + } + #[doc = "0x0c - Clock source selection register"] + #[inline(always)] + pub const fn clksrc(&self) -> &CLKSRC { + &self.clksrc + } + #[doc = "0x10 - Clock enable register"] + #[inline(always)] + pub const fn clkena(&self) -> &CLKENA { + &self.clkena + } + #[doc = "0x14 - Data and response timeout configuration register"] + #[inline(always)] + pub const fn tmout(&self) -> &TMOUT { + &self.tmout + } + #[doc = "0x18 - Card bus width configuration register"] + #[inline(always)] + pub const fn ctype(&self) -> &CTYPE { + &self.ctype + } + #[doc = "0x1c - Card data block size configuration register"] + #[inline(always)] + pub const fn blksiz(&self) -> &BLKSIZ { + &self.blksiz + } + #[doc = "0x20 - Data transfer length configuration register"] + #[inline(always)] + pub const fn bytcnt(&self) -> &BYTCNT { + &self.bytcnt + } + #[doc = "0x24 - SDIO interrupt mask register"] + #[inline(always)] + pub const fn intmask(&self) -> &INTMASK { + &self.intmask + } + #[doc = "0x28 - Command argument data register"] + #[inline(always)] + pub const fn cmdarg(&self) -> &CMDARG { + &self.cmdarg + } + #[doc = "0x2c - Command and boot configuration register"] + #[inline(always)] + pub const fn cmd(&self) -> &CMD { + &self.cmd + } + #[doc = "0x30 - Response data register"] + #[inline(always)] + pub const fn resp0(&self) -> &RESP0 { + &self.resp0 + } + #[doc = "0x34 - Long response data register"] + #[inline(always)] + pub const fn resp1(&self) -> &RESP1 { + &self.resp1 + } + #[doc = "0x38 - Long response data register"] + #[inline(always)] + pub const fn resp2(&self) -> &RESP2 { + &self.resp2 + } + #[doc = "0x3c - Long response data register"] + #[inline(always)] + pub const fn resp3(&self) -> &RESP3 { + &self.resp3 + } + #[doc = "0x40 - Masked interrupt status register"] + #[inline(always)] + pub const fn mintsts(&self) -> &MINTSTS { + &self.mintsts + } + #[doc = "0x44 - Raw interrupt status register"] + #[inline(always)] + pub const fn rintsts(&self) -> &RINTSTS { + &self.rintsts + } + #[doc = "0x48 - SD/MMC status register"] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0x4c - FIFO configuration register"] + #[inline(always)] + pub const fn fifoth(&self) -> &FIFOTH { + &self.fifoth + } + #[doc = "0x50 - Card detect register"] + #[inline(always)] + pub const fn cdetect(&self) -> &CDETECT { + &self.cdetect + } + #[doc = "0x54 - Card write protection (WP) status register"] + #[inline(always)] + pub const fn wrtprt(&self) -> &WRTPRT { + &self.wrtprt + } + #[doc = "0x5c - Transferred byte count register"] + #[inline(always)] + pub const fn tcbcnt(&self) -> &TCBCNT { + &self.tcbcnt + } + #[doc = "0x60 - Transferred byte count register"] + #[inline(always)] + pub const fn tbbcnt(&self) -> &TBBCNT { + &self.tbbcnt + } + #[doc = "0x64 - Debounce filter time configuration register"] + #[inline(always)] + pub const fn debnce(&self) -> &DEBNCE { + &self.debnce + } + #[doc = "0x68 - User ID (scratchpad) register"] + #[inline(always)] + pub const fn usrid(&self) -> &USRID { + &self.usrid + } + #[doc = "0x6c - Version ID (scratchpad) register"] + #[inline(always)] + pub const fn verid(&self) -> &VERID { + &self.verid + } + #[doc = "0x70 - Hardware feature register"] + #[inline(always)] + pub const fn hcon(&self) -> &HCON { + &self.hcon + } + #[doc = "0x74 - UHS-1 register"] + #[inline(always)] + pub const fn uhs(&self) -> &UHS { + &self.uhs + } + #[doc = "0x78 - Card reset register"] + #[inline(always)] + pub const fn rst_n(&self) -> &RST_N { + &self.rst_n + } + #[doc = "0x80 - Burst mode transfer configuration register"] + #[inline(always)] + pub const fn bmod(&self) -> &BMOD { + &self.bmod + } + #[doc = "0x84 - Poll demand configuration register"] + #[inline(always)] + pub const fn pldmnd(&self) -> &PLDMND { + &self.pldmnd + } + #[doc = "0x88 - Descriptor base address register"] + #[inline(always)] + pub const fn dbaddr(&self) -> &DBADDR { + &self.dbaddr + } + #[doc = "0x8c - IDMAC status register"] + #[inline(always)] + pub const fn idsts(&self) -> &IDSTS { + &self.idsts + } + #[doc = "0x90 - IDMAC interrupt enable register"] + #[inline(always)] + pub const fn idinten(&self) -> &IDINTEN { + &self.idinten + } + #[doc = "0x94 - Host descriptor address pointer"] + #[inline(always)] + pub const fn dscaddr(&self) -> &DSCADDR { + &self.dscaddr + } + #[doc = "0x98 - Host buffer address pointer register"] + #[inline(always)] + pub const fn bufaddr(&self) -> &BUFADDR { + &self.bufaddr + } + #[doc = "0x100 - Card Threshold Control register"] + #[inline(always)] + pub const fn cardthrctl(&self) -> &CARDTHRCTL { + &self.cardthrctl + } + #[doc = "0x10c - eMMC DDR register"] + #[inline(always)] + pub const fn emmcddr(&self) -> &EMMCDDR { + &self.emmcddr + } + #[doc = "0x110 - Enable Phase Shift register"] + #[inline(always)] + pub const fn enshift(&self) -> &ENSHIFT { + &self.enshift + } + #[doc = "0x200 - CPU write and read transmit data by FIFO"] + #[inline(always)] + pub const fn buffifo(&self) -> &BUFFIFO { + &self.buffifo + } + #[doc = "0x800 - SDIO control register."] + #[inline(always)] + pub const fn clk_edge_sel(&self) -> &CLK_EDGE_SEL { + &self.clk_edge_sel + } + #[doc = "0x804 - SDIO raw ints register."] + #[inline(always)] + pub const fn raw_ints(&self) -> &RAW_INTS { + &self.raw_ints + } + #[doc = "0x808 - SDIO DLL clock control register."] + #[inline(always)] + pub const fn dll_clk_conf(&self) -> &DLL_CLK_CONF { + &self.dll_clk_conf + } + #[doc = "0x80c - SDIO DLL configuration register."] + #[inline(always)] + pub const fn dll_conf(&self) -> &DLL_CONF { + &self.dll_conf + } +} +#[doc = "CTRL (rw) register accessor: Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"] +pub type CTRL = crate::Reg; +#[doc = "Control register"] +pub mod ctrl; +#[doc = "CLKDIV (rw) register accessor: Clock divider configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`] module"] +pub type CLKDIV = crate::Reg; +#[doc = "Clock divider configuration register"] +pub mod clkdiv; +#[doc = "CLKSRC (rw) register accessor: Clock source selection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksrc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksrc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksrc`] module"] +pub type CLKSRC = crate::Reg; +#[doc = "Clock source selection register"] +pub mod clksrc; +#[doc = "CLKENA (rw) register accessor: Clock enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkena`] module"] +pub type CLKENA = crate::Reg; +#[doc = "Clock enable register"] +pub mod clkena; +#[doc = "TMOUT (rw) register accessor: Data and response timeout configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmout::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmout`] module"] +pub type TMOUT = crate::Reg; +#[doc = "Data and response timeout configuration register"] +pub mod tmout; +#[doc = "CTYPE (rw) register accessor: Card bus width configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctype::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctype::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctype`] module"] +pub type CTYPE = crate::Reg; +#[doc = "Card bus width configuration register"] +pub mod ctype; +#[doc = "BLKSIZ (rw) register accessor: Card data block size configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blksiz::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blksiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@blksiz`] module"] +pub type BLKSIZ = crate::Reg; +#[doc = "Card data block size configuration register"] +pub mod blksiz; +#[doc = "BYTCNT (rw) register accessor: Data transfer length configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bytcnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bytcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bytcnt`] module"] +pub type BYTCNT = crate::Reg; +#[doc = "Data transfer length configuration register"] +pub mod bytcnt; +#[doc = "INTMASK (rw) register accessor: SDIO interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intmask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intmask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intmask`] module"] +pub type INTMASK = crate::Reg; +#[doc = "SDIO interrupt mask register"] +pub mod intmask; +#[doc = "CMDARG (rw) register accessor: Command argument data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdarg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdarg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdarg`] module"] +pub type CMDARG = crate::Reg; +#[doc = "Command argument data register"] +pub mod cmdarg; +#[doc = "CMD (rw) register accessor: Command and boot configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"] +pub type CMD = crate::Reg; +#[doc = "Command and boot configuration register"] +pub mod cmd; +#[doc = "RESP0 (r) register accessor: Response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp0`] module"] +pub type RESP0 = crate::Reg; +#[doc = "Response data register"] +pub mod resp0; +#[doc = "RESP1 (r) register accessor: Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp1`] module"] +pub type RESP1 = crate::Reg; +#[doc = "Long response data register"] +pub mod resp1; +#[doc = "RESP2 (r) register accessor: Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp2`] module"] +pub type RESP2 = crate::Reg; +#[doc = "Long response data register"] +pub mod resp2; +#[doc = "RESP3 (r) register accessor: Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resp3`] module"] +pub type RESP3 = crate::Reg; +#[doc = "Long response data register"] +pub mod resp3; +#[doc = "MINTSTS (r) register accessor: Masked interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mintsts::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mintsts`] module"] +pub type MINTSTS = crate::Reg; +#[doc = "Masked interrupt status register"] +pub mod mintsts; +#[doc = "RINTSTS (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rintsts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rintsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rintsts`] module"] +pub type RINTSTS = crate::Reg; +#[doc = "Raw interrupt status register"] +pub mod rintsts; +#[doc = "STATUS (r) register accessor: SD/MMC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +pub type STATUS = crate::Reg; +#[doc = "SD/MMC status register"] +pub mod status; +#[doc = "FIFOTH (rw) register accessor: FIFO configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifoth::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifoth::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifoth`] module"] +pub type FIFOTH = crate::Reg; +#[doc = "FIFO configuration register"] +pub mod fifoth; +#[doc = "CDETECT (r) register accessor: Card detect register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdetect::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cdetect`] module"] +pub type CDETECT = crate::Reg; +#[doc = "Card detect register"] +pub mod cdetect; +#[doc = "WRTPRT (r) register accessor: Card write protection (WP) status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wrtprt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wrtprt`] module"] +pub type WRTPRT = crate::Reg; +#[doc = "Card write protection (WP) status register"] +pub mod wrtprt; +#[doc = "TCBCNT (r) register accessor: Transferred byte count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcbcnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcbcnt`] module"] +pub type TCBCNT = crate::Reg; +#[doc = "Transferred byte count register"] +pub mod tcbcnt; +#[doc = "TBBCNT (r) register accessor: Transferred byte count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbbcnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tbbcnt`] module"] +pub type TBBCNT = crate::Reg; +#[doc = "Transferred byte count register"] +pub mod tbbcnt; +#[doc = "DEBNCE (rw) register accessor: Debounce filter time configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debnce::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debnce::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debnce`] module"] +pub type DEBNCE = crate::Reg; +#[doc = "Debounce filter time configuration register"] +pub mod debnce; +#[doc = "USRID (rw) register accessor: User ID (scratchpad) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usrid::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usrid::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usrid`] module"] +pub type USRID = crate::Reg; +#[doc = "User ID (scratchpad) register"] +pub mod usrid; +#[doc = "VERID (r) register accessor: Version ID (scratchpad) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`verid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@verid`] module"] +pub type VERID = crate::Reg; +#[doc = "Version ID (scratchpad) register"] +pub mod verid; +#[doc = "HCON (r) register accessor: Hardware feature register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcon::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcon`] module"] +pub type HCON = crate::Reg; +#[doc = "Hardware feature register"] +pub mod hcon; +#[doc = "UHS (rw) register accessor: UHS-1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uhs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uhs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uhs`] module"] +pub type UHS = crate::Reg; +#[doc = "UHS-1 register"] +pub mod uhs; +#[doc = "RST_N (rw) register accessor: Card reset register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_n::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_n::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_n`] module"] +pub type RST_N = crate::Reg; +#[doc = "Card reset register"] +pub mod rst_n; +#[doc = "BMOD (rw) register accessor: Burst mode transfer configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmod::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmod::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bmod`] module"] +pub type BMOD = crate::Reg; +#[doc = "Burst mode transfer configuration register"] +pub mod bmod; +#[doc = "PLDMND (w) register accessor: Poll demand configuration register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pldmnd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pldmnd`] module"] +pub type PLDMND = crate::Reg; +#[doc = "Poll demand configuration register"] +pub mod pldmnd; +#[doc = "DBADDR (rw) register accessor: Descriptor base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbaddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbaddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbaddr`] module"] +pub type DBADDR = crate::Reg; +#[doc = "Descriptor base address register"] +pub mod dbaddr; +#[doc = "IDSTS (rw) register accessor: IDMAC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idsts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idsts`] module"] +pub type IDSTS = crate::Reg; +#[doc = "IDMAC status register"] +pub mod idsts; +#[doc = "IDINTEN (rw) register accessor: IDMAC interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idinten::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idinten::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idinten`] module"] +pub type IDINTEN = crate::Reg; +#[doc = "IDMAC interrupt enable register"] +pub mod idinten; +#[doc = "DSCADDR (r) register accessor: Host descriptor address pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dscaddr`] module"] +pub type DSCADDR = crate::Reg; +#[doc = "Host descriptor address pointer"] +pub mod dscaddr; +#[doc = "BUFADDR (r) register accessor: Host buffer address pointer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bufaddr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bufaddr`] module"] +pub type BUFADDR = crate::Reg; +#[doc = "Host buffer address pointer register"] +pub mod bufaddr; +#[doc = "CARDTHRCTL (rw) register accessor: Card Threshold Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cardthrctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cardthrctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cardthrctl`] module"] +pub type CARDTHRCTL = crate::Reg; +#[doc = "Card Threshold Control register"] +pub mod cardthrctl; +#[doc = "EMMCDDR (rw) register accessor: eMMC DDR register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emmcddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emmcddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emmcddr`] module"] +pub type EMMCDDR = crate::Reg; +#[doc = "eMMC DDR register"] +pub mod emmcddr; +#[doc = "ENSHIFT (rw) register accessor: Enable Phase Shift register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enshift::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enshift::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enshift`] module"] +pub type ENSHIFT = crate::Reg; +#[doc = "Enable Phase Shift register"] +pub mod enshift; +#[doc = "BUFFIFO (rw) register accessor: CPU write and read transmit data by FIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buffifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buffifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@buffifo`] module"] +pub type BUFFIFO = crate::Reg; +#[doc = "CPU write and read transmit data by FIFO"] +pub mod buffifo; +#[doc = "CLK_EDGE_SEL (rw) register accessor: SDIO control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_edge_sel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_edge_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_edge_sel`] module"] +pub type CLK_EDGE_SEL = crate::Reg; +#[doc = "SDIO control register."] +pub mod clk_edge_sel; +#[doc = "RAW_INTS (r) register accessor: SDIO raw ints register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_ints`] module"] +pub type RAW_INTS = crate::Reg; +#[doc = "SDIO raw ints register."] +pub mod raw_ints; +#[doc = "DLL_CLK_CONF (rw) register accessor: SDIO DLL clock control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll_clk_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll_clk_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll_clk_conf`] module"] +pub type DLL_CLK_CONF = crate::Reg; +#[doc = "SDIO DLL clock control register."] +pub mod dll_clk_conf; +#[doc = "DLL_CONF (rw) register accessor: SDIO DLL configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll_conf`] module"] +pub type DLL_CONF = crate::Reg; +#[doc = "SDIO DLL configuration register."] +pub mod dll_conf; diff --git a/esp32p4/src/sdhost/blksiz.rs b/esp32p4/src/sdhost/blksiz.rs new file mode 100644 index 0000000000..5d656dcd49 --- /dev/null +++ b/esp32p4/src/sdhost/blksiz.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BLKSIZ` reader"] +pub type R = crate::R; +#[doc = "Register `BLKSIZ` writer"] +pub type W = crate::W; +#[doc = "Field `BLOCK_SIZE` reader - Block size."] +pub type BLOCK_SIZE_R = crate::FieldReader; +#[doc = "Field `BLOCK_SIZE` writer - Block size."] +pub type BLOCK_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Block size."] + #[inline(always)] + pub fn block_size(&self) -> BLOCK_SIZE_R { + BLOCK_SIZE_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BLKSIZ") + .field("block_size", &format_args!("{}", self.block_size().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Block size."] + #[inline(always)] + #[must_use] + pub fn block_size(&mut self) -> BLOCK_SIZE_W { + BLOCK_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Card data block size configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blksiz::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blksiz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BLKSIZ_SPEC; +impl crate::RegisterSpec for BLKSIZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`blksiz::R`](R) reader structure"] +impl crate::Readable for BLKSIZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blksiz::W`](W) writer structure"] +impl crate::Writable for BLKSIZ_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BLKSIZ to value 0x0200"] +impl crate::Resettable for BLKSIZ_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/esp32p4/src/sdhost/bmod.rs b/esp32p4/src/sdhost/bmod.rs new file mode 100644 index 0000000000..64b941532d --- /dev/null +++ b/esp32p4/src/sdhost/bmod.rs @@ -0,0 +1,111 @@ +#[doc = "Register `BMOD` reader"] +pub type R = crate::R; +#[doc = "Register `BMOD` writer"] +pub type W = crate::W; +#[doc = "Field `SWR` reader - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."] +pub type SWR_R = crate::BitReader; +#[doc = "Field `SWR` writer - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."] +pub type SWR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FB` reader - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."] +pub type FB_R = crate::BitReader; +#[doc = "Field `FB` writer - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."] +pub type FB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE` reader - IDMAC Enable. When set, the IDMAC is enabled."] +pub type DE_R = crate::BitReader; +#[doc = "Field `DE` writer - IDMAC Enable. When set, the IDMAC is enabled."] +pub type DE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PBL` reader - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access."] +pub type PBL_R = crate::FieldReader; +#[doc = "Field `PBL` writer - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access."] +pub type PBL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."] + #[inline(always)] + pub fn swr(&self) -> SWR_R { + SWR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."] + #[inline(always)] + pub fn fb(&self) -> FB_R { + FB_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 7 - IDMAC Enable. When set, the IDMAC is enabled."] + #[inline(always)] + pub fn de(&self) -> DE_R { + DE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access."] + #[inline(always)] + pub fn pbl(&self) -> PBL_R { + PBL_R::new(((self.bits >> 8) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BMOD") + .field("swr", &format_args!("{}", self.swr().bit())) + .field("fb", &format_args!("{}", self.fb().bit())) + .field("de", &format_args!("{}", self.de().bit())) + .field("pbl", &format_args!("{}", self.pbl().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."] + #[inline(always)] + #[must_use] + pub fn swr(&mut self) -> SWR_W { + SWR_W::new(self, 0) + } + #[doc = "Bit 1 - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."] + #[inline(always)] + #[must_use] + pub fn fb(&mut self) -> FB_W { + FB_W::new(self, 1) + } + #[doc = "Bit 7 - IDMAC Enable. When set, the IDMAC is enabled."] + #[inline(always)] + #[must_use] + pub fn de(&mut self) -> DE_W { + DE_W::new(self, 7) + } + #[doc = "Bits 8:10 - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access."] + #[inline(always)] + #[must_use] + pub fn pbl(&mut self) -> PBL_W { + PBL_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Burst mode transfer configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmod::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmod::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BMOD_SPEC; +impl crate::RegisterSpec for BMOD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bmod::R`](R) reader structure"] +impl crate::Readable for BMOD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bmod::W`](W) writer structure"] +impl crate::Writable for BMOD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BMOD to value 0"] +impl crate::Resettable for BMOD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/bufaddr.rs b/esp32p4/src/sdhost/bufaddr.rs new file mode 100644 index 0000000000..90e98e0932 --- /dev/null +++ b/esp32p4/src/sdhost/bufaddr.rs @@ -0,0 +1,36 @@ +#[doc = "Register `BUFADDR` reader"] +pub type R = crate::R; +#[doc = "Field `BUFADDR` reader - Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC."] +pub type BUFADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC."] + #[inline(always)] + pub fn bufaddr(&self) -> BUFADDR_R { + BUFADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUFADDR") + .field("bufaddr", &format_args!("{}", self.bufaddr().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Host buffer address pointer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bufaddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUFADDR_SPEC; +impl crate::RegisterSpec for BUFADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bufaddr::R`](R) reader structure"] +impl crate::Readable for BUFADDR_SPEC {} +#[doc = "`reset()` method sets BUFADDR to value 0"] +impl crate::Resettable for BUFADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/buffifo.rs b/esp32p4/src/sdhost/buffifo.rs new file mode 100644 index 0000000000..5705daa25e --- /dev/null +++ b/esp32p4/src/sdhost/buffifo.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BUFFIFO` reader"] +pub type R = crate::R; +#[doc = "Register `BUFFIFO` writer"] +pub type W = crate::W; +#[doc = "Field `BUFFIFO` reader - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."] +pub type BUFFIFO_R = crate::FieldReader; +#[doc = "Field `BUFFIFO` writer - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."] +pub type BUFFIFO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."] + #[inline(always)] + pub fn buffifo(&self) -> BUFFIFO_R { + BUFFIFO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUFFIFO") + .field("buffifo", &format_args!("{}", self.buffifo().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."] + #[inline(always)] + #[must_use] + pub fn buffifo(&mut self) -> BUFFIFO_W { + BUFFIFO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "CPU write and read transmit data by FIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buffifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buffifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUFFIFO_SPEC; +impl crate::RegisterSpec for BUFFIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`buffifo::R`](R) reader structure"] +impl crate::Readable for BUFFIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`buffifo::W`](W) writer structure"] +impl crate::Writable for BUFFIFO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BUFFIFO to value 0"] +impl crate::Resettable for BUFFIFO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/bytcnt.rs b/esp32p4/src/sdhost/bytcnt.rs new file mode 100644 index 0000000000..fef219efa5 --- /dev/null +++ b/esp32p4/src/sdhost/bytcnt.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BYTCNT` reader"] +pub type R = crate::R; +#[doc = "Register `BYTCNT` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE_COUNT` reader - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."] +pub type BYTE_COUNT_R = crate::FieldReader; +#[doc = "Field `BYTE_COUNT` writer - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."] +pub type BYTE_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."] + #[inline(always)] + pub fn byte_count(&self) -> BYTE_COUNT_R { + BYTE_COUNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BYTCNT") + .field("byte_count", &format_args!("{}", self.byte_count().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."] + #[inline(always)] + #[must_use] + pub fn byte_count(&mut self) -> BYTE_COUNT_W { + BYTE_COUNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data transfer length configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bytcnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bytcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BYTCNT_SPEC; +impl crate::RegisterSpec for BYTCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bytcnt::R`](R) reader structure"] +impl crate::Readable for BYTCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bytcnt::W`](W) writer structure"] +impl crate::Writable for BYTCNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BYTCNT to value 0x0200"] +impl crate::Resettable for BYTCNT_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/esp32p4/src/sdhost/cardthrctl.rs b/esp32p4/src/sdhost/cardthrctl.rs new file mode 100644 index 0000000000..e9251b88eb --- /dev/null +++ b/esp32p4/src/sdhost/cardthrctl.rs @@ -0,0 +1,117 @@ +#[doc = "Register `CARDTHRCTL` reader"] +pub type R = crate::R; +#[doc = "Register `CARDTHRCTL` writer"] +pub type W = crate::W; +#[doc = "Field `CARDRDTHREN` reader - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."] +pub type CARDRDTHREN_R = crate::BitReader; +#[doc = "Field `CARDRDTHREN` writer - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."] +pub type CARDRDTHREN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CARDCLRINTEN` reader - Busy clear interrupt generation: 1'b0-Busy clear interrypt disabled. 1'b1-Busy clear interrypt enabled."] +pub type CARDCLRINTEN_R = crate::BitReader; +#[doc = "Field `CARDCLRINTEN` writer - Busy clear interrupt generation: 1'b0-Busy clear interrypt disabled. 1'b1-Busy clear interrypt enabled."] +pub type CARDCLRINTEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CARDWRTHREN` reader - Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled."] +pub type CARDWRTHREN_R = crate::BitReader; +#[doc = "Field `CARDWRTHREN` writer - Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled."] +pub type CARDWRTHREN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CARDTHRESHOLD` reader - The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1."] +pub type CARDTHRESHOLD_R = crate::FieldReader; +#[doc = "Field `CARDTHRESHOLD` writer - The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1."] +pub type CARDTHRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."] + #[inline(always)] + pub fn cardrdthren(&self) -> CARDRDTHREN_R { + CARDRDTHREN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Busy clear interrupt generation: 1'b0-Busy clear interrypt disabled. 1'b1-Busy clear interrypt enabled."] + #[inline(always)] + pub fn cardclrinten(&self) -> CARDCLRINTEN_R { + CARDCLRINTEN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled."] + #[inline(always)] + pub fn cardwrthren(&self) -> CARDWRTHREN_R { + CARDWRTHREN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 16:31 - The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1."] + #[inline(always)] + pub fn cardthreshold(&self) -> CARDTHRESHOLD_R { + CARDTHRESHOLD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CARDTHRCTL") + .field("cardrdthren", &format_args!("{}", self.cardrdthren().bit())) + .field( + "cardclrinten", + &format_args!("{}", self.cardclrinten().bit()), + ) + .field("cardwrthren", &format_args!("{}", self.cardwrthren().bit())) + .field( + "cardthreshold", + &format_args!("{}", self.cardthreshold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."] + #[inline(always)] + #[must_use] + pub fn cardrdthren(&mut self) -> CARDRDTHREN_W { + CARDRDTHREN_W::new(self, 0) + } + #[doc = "Bit 1 - Busy clear interrupt generation: 1'b0-Busy clear interrypt disabled. 1'b1-Busy clear interrypt enabled."] + #[inline(always)] + #[must_use] + pub fn cardclrinten(&mut self) -> CARDCLRINTEN_W { + CARDCLRINTEN_W::new(self, 1) + } + #[doc = "Bit 2 - Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled."] + #[inline(always)] + #[must_use] + pub fn cardwrthren(&mut self) -> CARDWRTHREN_W { + CARDWRTHREN_W::new(self, 2) + } + #[doc = "Bits 16:31 - The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1."] + #[inline(always)] + #[must_use] + pub fn cardthreshold(&mut self) -> CARDTHRESHOLD_W { + CARDTHRESHOLD_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Card Threshold Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cardthrctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cardthrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CARDTHRCTL_SPEC; +impl crate::RegisterSpec for CARDTHRCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cardthrctl::R`](R) reader structure"] +impl crate::Readable for CARDTHRCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cardthrctl::W`](W) writer structure"] +impl crate::Writable for CARDTHRCTL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CARDTHRCTL to value 0"] +impl crate::Resettable for CARDTHRCTL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/cdetect.rs b/esp32p4/src/sdhost/cdetect.rs new file mode 100644 index 0000000000..afd68b96a4 --- /dev/null +++ b/esp32p4/src/sdhost/cdetect.rs @@ -0,0 +1,39 @@ +#[doc = "Register `CDETECT` reader"] +pub type R = crate::R; +#[doc = "Field `CARD_DETECT_N` reader - Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented."] +pub type CARD_DETECT_N_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented."] + #[inline(always)] + pub fn card_detect_n(&self) -> CARD_DETECT_N_R { + CARD_DETECT_N_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CDETECT") + .field( + "card_detect_n", + &format_args!("{}", self.card_detect_n().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Card detect register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdetect::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CDETECT_SPEC; +impl crate::RegisterSpec for CDETECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cdetect::R`](R) reader structure"] +impl crate::Readable for CDETECT_SPEC {} +#[doc = "`reset()` method sets CDETECT to value 0"] +impl crate::Resettable for CDETECT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/clk_edge_sel.rs b/esp32p4/src/sdhost/clk_edge_sel.rs new file mode 100644 index 0000000000..1f7dc6e3c0 --- /dev/null +++ b/esp32p4/src/sdhost/clk_edge_sel.rs @@ -0,0 +1,228 @@ +#[doc = "Register `CLK_EDGE_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_EDGE_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `CCLKIN_EDGE_DRV_SEL` reader - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."] +pub type CCLKIN_EDGE_DRV_SEL_R = crate::FieldReader; +#[doc = "Field `CCLKIN_EDGE_DRV_SEL` writer - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."] +pub type CCLKIN_EDGE_DRV_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CCLKIN_EDGE_SAM_SEL` reader - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."] +pub type CCLKIN_EDGE_SAM_SEL_R = crate::FieldReader; +#[doc = "Field `CCLKIN_EDGE_SAM_SEL` writer - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."] +pub type CCLKIN_EDGE_SAM_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CCLKIN_EDGE_SLF_SEL` reader - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."] +pub type CCLKIN_EDGE_SLF_SEL_R = crate::FieldReader; +#[doc = "Field `CCLKIN_EDGE_SLF_SEL` writer - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."] +pub type CCLKIN_EDGE_SLF_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CCLLKIN_EDGE_H` reader - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."] +pub type CCLLKIN_EDGE_H_R = crate::FieldReader; +#[doc = "Field `CCLLKIN_EDGE_H` writer - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."] +pub type CCLLKIN_EDGE_H_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CCLLKIN_EDGE_L` reader - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."] +pub type CCLLKIN_EDGE_L_R = crate::FieldReader; +#[doc = "Field `CCLLKIN_EDGE_L` writer - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."] +pub type CCLLKIN_EDGE_L_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CCLLKIN_EDGE_N` reader - The clock division of cclk_in."] +pub type CCLLKIN_EDGE_N_R = crate::FieldReader; +#[doc = "Field `CCLLKIN_EDGE_N` writer - The clock division of cclk_in."] +pub type CCLLKIN_EDGE_N_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ESDIO_MODE` reader - Enable esdio mode."] +pub type ESDIO_MODE_R = crate::BitReader; +#[doc = "Field `ESDIO_MODE` writer - Enable esdio mode."] +pub type ESDIO_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ESD_MODE` reader - Enable esd mode."] +pub type ESD_MODE_R = crate::BitReader; +#[doc = "Field `ESD_MODE` writer - Enable esd mode."] +pub type ESD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CCLK_EN` reader - Sdio clock enable."] +pub type CCLK_EN_R = crate::BitReader; +#[doc = "Field `CCLK_EN` writer - Sdio clock enable."] +pub type CCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ULTRA_HIGH_SPEED_MODE` reader - Enable ultra high speed mode, use dll to generate clk."] +pub type ULTRA_HIGH_SPEED_MODE_R = crate::BitReader; +#[doc = "Field `ULTRA_HIGH_SPEED_MODE` writer - Enable ultra high speed mode, use dll to generate clk."] +pub type ULTRA_HIGH_SPEED_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."] + #[inline(always)] + pub fn cclkin_edge_drv_sel(&self) -> CCLKIN_EDGE_DRV_SEL_R { + CCLKIN_EDGE_DRV_SEL_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."] + #[inline(always)] + pub fn cclkin_edge_sam_sel(&self) -> CCLKIN_EDGE_SAM_SEL_R { + CCLKIN_EDGE_SAM_SEL_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."] + #[inline(always)] + pub fn cclkin_edge_slf_sel(&self) -> CCLKIN_EDGE_SLF_SEL_R { + CCLKIN_EDGE_SLF_SEL_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."] + #[inline(always)] + pub fn ccllkin_edge_h(&self) -> CCLLKIN_EDGE_H_R { + CCLLKIN_EDGE_H_R::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."] + #[inline(always)] + pub fn ccllkin_edge_l(&self) -> CCLLKIN_EDGE_L_R { + CCLLKIN_EDGE_L_R::new(((self.bits >> 13) & 0x0f) as u8) + } + #[doc = "Bits 17:20 - The clock division of cclk_in."] + #[inline(always)] + pub fn ccllkin_edge_n(&self) -> CCLLKIN_EDGE_N_R { + CCLLKIN_EDGE_N_R::new(((self.bits >> 17) & 0x0f) as u8) + } + #[doc = "Bit 21 - Enable esdio mode."] + #[inline(always)] + pub fn esdio_mode(&self) -> ESDIO_MODE_R { + ESDIO_MODE_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Enable esd mode."] + #[inline(always)] + pub fn esd_mode(&self) -> ESD_MODE_R { + ESD_MODE_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Sdio clock enable."] + #[inline(always)] + pub fn cclk_en(&self) -> CCLK_EN_R { + CCLK_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Enable ultra high speed mode, use dll to generate clk."] + #[inline(always)] + pub fn ultra_high_speed_mode(&self) -> ULTRA_HIGH_SPEED_MODE_R { + ULTRA_HIGH_SPEED_MODE_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_EDGE_SEL") + .field( + "cclkin_edge_drv_sel", + &format_args!("{}", self.cclkin_edge_drv_sel().bits()), + ) + .field( + "cclkin_edge_sam_sel", + &format_args!("{}", self.cclkin_edge_sam_sel().bits()), + ) + .field( + "cclkin_edge_slf_sel", + &format_args!("{}", self.cclkin_edge_slf_sel().bits()), + ) + .field( + "ccllkin_edge_h", + &format_args!("{}", self.ccllkin_edge_h().bits()), + ) + .field( + "ccllkin_edge_l", + &format_args!("{}", self.ccllkin_edge_l().bits()), + ) + .field( + "ccllkin_edge_n", + &format_args!("{}", self.ccllkin_edge_n().bits()), + ) + .field("esdio_mode", &format_args!("{}", self.esdio_mode().bit())) + .field("esd_mode", &format_args!("{}", self.esd_mode().bit())) + .field("cclk_en", &format_args!("{}", self.cclk_en().bit())) + .field( + "ultra_high_speed_mode", + &format_args!("{}", self.ultra_high_speed_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."] + #[inline(always)] + #[must_use] + pub fn cclkin_edge_drv_sel(&mut self) -> CCLKIN_EDGE_DRV_SEL_W { + CCLKIN_EDGE_DRV_SEL_W::new(self, 0) + } + #[doc = "Bits 3:5 - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."] + #[inline(always)] + #[must_use] + pub fn cclkin_edge_sam_sel(&mut self) -> CCLKIN_EDGE_SAM_SEL_W { + CCLKIN_EDGE_SAM_SEL_W::new(self, 3) + } + #[doc = "Bits 6:8 - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."] + #[inline(always)] + #[must_use] + pub fn cclkin_edge_slf_sel(&mut self) -> CCLKIN_EDGE_SLF_SEL_W { + CCLKIN_EDGE_SLF_SEL_W::new(self, 6) + } + #[doc = "Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."] + #[inline(always)] + #[must_use] + pub fn ccllkin_edge_h(&mut self) -> CCLLKIN_EDGE_H_W { + CCLLKIN_EDGE_H_W::new(self, 9) + } + #[doc = "Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."] + #[inline(always)] + #[must_use] + pub fn ccllkin_edge_l(&mut self) -> CCLLKIN_EDGE_L_W { + CCLLKIN_EDGE_L_W::new(self, 13) + } + #[doc = "Bits 17:20 - The clock division of cclk_in."] + #[inline(always)] + #[must_use] + pub fn ccllkin_edge_n(&mut self) -> CCLLKIN_EDGE_N_W { + CCLLKIN_EDGE_N_W::new(self, 17) + } + #[doc = "Bit 21 - Enable esdio mode."] + #[inline(always)] + #[must_use] + pub fn esdio_mode(&mut self) -> ESDIO_MODE_W { + ESDIO_MODE_W::new(self, 21) + } + #[doc = "Bit 22 - Enable esd mode."] + #[inline(always)] + #[must_use] + pub fn esd_mode(&mut self) -> ESD_MODE_W { + ESD_MODE_W::new(self, 22) + } + #[doc = "Bit 23 - Sdio clock enable."] + #[inline(always)] + #[must_use] + pub fn cclk_en(&mut self) -> CCLK_EN_W { + CCLK_EN_W::new(self, 23) + } + #[doc = "Bit 24 - Enable ultra high speed mode, use dll to generate clk."] + #[inline(always)] + #[must_use] + pub fn ultra_high_speed_mode(&mut self) -> ULTRA_HIGH_SPEED_MODE_W { + ULTRA_HIGH_SPEED_MODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SDIO control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_edge_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_edge_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_EDGE_SEL_SPEC; +impl crate::RegisterSpec for CLK_EDGE_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_edge_sel::R`](R) reader structure"] +impl crate::Readable for CLK_EDGE_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_edge_sel::W`](W) writer structure"] +impl crate::Writable for CLK_EDGE_SEL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_EDGE_SEL to value 0x0082_0200"] +impl crate::Resettable for CLK_EDGE_SEL_SPEC { + const RESET_VALUE: Self::Ux = 0x0082_0200; +} diff --git a/esp32p4/src/sdhost/clkdiv.rs b/esp32p4/src/sdhost/clkdiv.rs new file mode 100644 index 0000000000..a8c8710b1e --- /dev/null +++ b/esp32p4/src/sdhost/clkdiv.rs @@ -0,0 +1,123 @@ +#[doc = "Register `CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_DIVIDER0` reader - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] +pub type CLK_DIVIDER0_R = crate::FieldReader; +#[doc = "Field `CLK_DIVIDER0` writer - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] +pub type CLK_DIVIDER0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CLK_DIVIDER1` reader - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] +pub type CLK_DIVIDER1_R = crate::FieldReader; +#[doc = "Field `CLK_DIVIDER1` writer - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] +pub type CLK_DIVIDER1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CLK_DIVIDER2` reader - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] +pub type CLK_DIVIDER2_R = crate::FieldReader; +#[doc = "Field `CLK_DIVIDER2` writer - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] +pub type CLK_DIVIDER2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CLK_DIVIDER3` reader - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] +pub type CLK_DIVIDER3_R = crate::FieldReader; +#[doc = "Field `CLK_DIVIDER3` writer - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] +pub type CLK_DIVIDER3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] + #[inline(always)] + pub fn clk_divider0(&self) -> CLK_DIVIDER0_R { + CLK_DIVIDER0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] + #[inline(always)] + pub fn clk_divider1(&self) -> CLK_DIVIDER1_R { + CLK_DIVIDER1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] + #[inline(always)] + pub fn clk_divider2(&self) -> CLK_DIVIDER2_R { + CLK_DIVIDER2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] + #[inline(always)] + pub fn clk_divider3(&self) -> CLK_DIVIDER3_R { + CLK_DIVIDER3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLKDIV") + .field( + "clk_divider0", + &format_args!("{}", self.clk_divider0().bits()), + ) + .field( + "clk_divider1", + &format_args!("{}", self.clk_divider1().bits()), + ) + .field( + "clk_divider2", + &format_args!("{}", self.clk_divider2().bits()), + ) + .field( + "clk_divider3", + &format_args!("{}", self.clk_divider3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] + #[inline(always)] + #[must_use] + pub fn clk_divider0(&mut self) -> CLK_DIVIDER0_W { + CLK_DIVIDER0_W::new(self, 0) + } + #[doc = "Bits 8:15 - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] + #[inline(always)] + #[must_use] + pub fn clk_divider1(&mut self) -> CLK_DIVIDER1_W { + CLK_DIVIDER1_W::new(self, 8) + } + #[doc = "Bits 16:23 - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] + #[inline(always)] + #[must_use] + pub fn clk_divider2(&mut self) -> CLK_DIVIDER2_W { + CLK_DIVIDER2_W::new(self, 16) + } + #[doc = "Bits 24:31 - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."] + #[inline(always)] + #[must_use] + pub fn clk_divider3(&mut self) -> CLK_DIVIDER3_W { + CLK_DIVIDER3_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock divider configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLKDIV_SPEC; +impl crate::RegisterSpec for CLKDIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv::R`](R) reader structure"] +impl crate::Readable for CLKDIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"] +impl crate::Writable for CLKDIV_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLKDIV to value 0"] +impl crate::Resettable for CLKDIV_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/clkena.rs b/esp32p4/src/sdhost/clkena.rs new file mode 100644 index 0000000000..4cd65477da --- /dev/null +++ b/esp32p4/src/sdhost/clkena.rs @@ -0,0 +1,82 @@ +#[doc = "Register `CLKENA` reader"] +pub type R = crate::R; +#[doc = "Register `CLKENA` writer"] +pub type W = crate::W; +#[doc = "Field `CCLK_ENABLE` reader - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."] +pub type CCLK_ENABLE_R = crate::FieldReader; +#[doc = "Field `CCLK_ENABLE` writer - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."] +pub type CCLK_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LP_ENABLE` reader - Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled."] +pub type LP_ENABLE_R = crate::FieldReader; +#[doc = "Field `LP_ENABLE` writer - Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled."] +pub type LP_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."] + #[inline(always)] + pub fn cclk_enable(&self) -> CCLK_ENABLE_R { + CCLK_ENABLE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 16:17 - Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled."] + #[inline(always)] + pub fn lp_enable(&self) -> LP_ENABLE_R { + LP_ENABLE_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLKENA") + .field( + "cclk_enable", + &format_args!("{}", self.cclk_enable().bits()), + ) + .field("lp_enable", &format_args!("{}", self.lp_enable().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."] + #[inline(always)] + #[must_use] + pub fn cclk_enable(&mut self) -> CCLK_ENABLE_W { + CCLK_ENABLE_W::new(self, 0) + } + #[doc = "Bits 16:17 - Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled."] + #[inline(always)] + #[must_use] + pub fn lp_enable(&mut self) -> LP_ENABLE_W { + LP_ENABLE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLKENA_SPEC; +impl crate::RegisterSpec for CLKENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkena::R`](R) reader structure"] +impl crate::Readable for CLKENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clkena::W`](W) writer structure"] +impl crate::Writable for CLKENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLKENA to value 0"] +impl crate::Resettable for CLKENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/clksrc.rs b/esp32p4/src/sdhost/clksrc.rs new file mode 100644 index 0000000000..8baaed542a --- /dev/null +++ b/esp32p4/src/sdhost/clksrc.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLKSRC` reader"] +pub type R = crate::R; +#[doc = "Register `CLKSRC` writer"] +pub type W = crate::W; +#[doc = "Field `CLKSRC` reader - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."] +pub type CLKSRC_R = crate::FieldReader; +#[doc = "Field `CLKSRC` writer - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."] +pub type CLKSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."] + #[inline(always)] + pub fn clksrc(&self) -> CLKSRC_R { + CLKSRC_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLKSRC") + .field("clksrc", &format_args!("{}", self.clksrc().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."] + #[inline(always)] + #[must_use] + pub fn clksrc(&mut self) -> CLKSRC_W { + CLKSRC_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock source selection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksrc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksrc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLKSRC_SPEC; +impl crate::RegisterSpec for CLKSRC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clksrc::R`](R) reader structure"] +impl crate::Readable for CLKSRC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clksrc::W`](W) writer structure"] +impl crate::Writable for CLKSRC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLKSRC to value 0"] +impl crate::Resettable for CLKSRC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/cmd.rs b/esp32p4/src/sdhost/cmd.rs new file mode 100644 index 0000000000..8fdd9d082b --- /dev/null +++ b/esp32p4/src/sdhost/cmd.rs @@ -0,0 +1,358 @@ +#[doc = "Register `CMD` reader"] +pub type R = crate::R; +#[doc = "Register `CMD` writer"] +pub type W = crate::W; +#[doc = "Field `INDEX` reader - Command index."] +pub type INDEX_R = crate::FieldReader; +#[doc = "Field `INDEX` writer - Command index."] +pub type INDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `RESPONSE_EXPECT` reader - 0: No response expected from card; 1: Response expected from card."] +pub type RESPONSE_EXPECT_R = crate::BitReader; +#[doc = "Field `RESPONSE_EXPECT` writer - 0: No response expected from card; 1: Response expected from card."] +pub type RESPONSE_EXPECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESPONSE_LENGTH` reader - 0: Short response expected from card; 1: Long response expected from card."] +pub type RESPONSE_LENGTH_R = crate::BitReader; +#[doc = "Field `RESPONSE_LENGTH` writer - 0: Short response expected from card; 1: Long response expected from card."] +pub type RESPONSE_LENGTH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHECK_RESPONSE_CRC` reader - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."] +pub type CHECK_RESPONSE_CRC_R = crate::BitReader; +#[doc = "Field `CHECK_RESPONSE_CRC` writer - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."] +pub type CHECK_RESPONSE_CRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA_EXPECTED` reader - 0: No data transfer expected; 1: Data transfer expected."] +pub type DATA_EXPECTED_R = crate::BitReader; +#[doc = "Field `DATA_EXPECTED` writer - 0: No data transfer expected; 1: Data transfer expected."] +pub type DATA_EXPECTED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `READ_WRITE` reader - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."] +pub type READ_WRITE_R = crate::BitReader; +#[doc = "Field `READ_WRITE` writer - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."] +pub type READ_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSFER_MODE` reader - 0: Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."] +pub type TRANSFER_MODE_R = crate::BitReader; +#[doc = "Field `TRANSFER_MODE` writer - 0: Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."] +pub type TRANSFER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_AUTO_STOP` reader - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."] +pub type SEND_AUTO_STOP_R = crate::BitReader; +#[doc = "Field `SEND_AUTO_STOP` writer - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."] +pub type SEND_AUTO_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAIT_PRVDATA_COMPLETE` reader - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."] +pub type WAIT_PRVDATA_COMPLETE_R = crate::BitReader; +#[doc = "Field `WAIT_PRVDATA_COMPLETE` writer - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."] +pub type WAIT_PRVDATA_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STOP_ABORT_CMD` reader - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."] +pub type STOP_ABORT_CMD_R = crate::BitReader; +#[doc = "Field `STOP_ABORT_CMD` writer - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."] +pub type STOP_ABORT_CMD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_INITIALIZATION` reader - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."] +pub type SEND_INITIALIZATION_R = crate::BitReader; +#[doc = "Field `SEND_INITIALIZATION` writer - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."] +pub type SEND_INITIALIZATION_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CARD_NUMBER` reader - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."] +pub type CARD_NUMBER_R = crate::FieldReader; +#[doc = "Field `CARD_NUMBER` writer - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."] +pub type CARD_NUMBER_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `UPDATE_CLOCK_REGISTERS_ONLY` reader - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."] +pub type UPDATE_CLOCK_REGISTERS_ONLY_R = crate::BitReader; +#[doc = "Field `UPDATE_CLOCK_REGISTERS_ONLY` writer - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."] +pub type UPDATE_CLOCK_REGISTERS_ONLY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `READ_CEATA_DEVICE` reader - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."] +pub type READ_CEATA_DEVICE_R = crate::BitReader; +#[doc = "Field `READ_CEATA_DEVICE` writer - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."] +pub type READ_CEATA_DEVICE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CCS_EXPECTED` reader - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."] +pub type CCS_EXPECTED_R = crate::BitReader; +#[doc = "Field `CCS_EXPECTED` writer - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."] +pub type CCS_EXPECTED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USE_HOLE` reader - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."] +pub type USE_HOLE_R = crate::BitReader; +#[doc = "Field `USE_HOLE` writer - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."] +pub type USE_HOLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `START_CMD` reader - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."] +pub type START_CMD_R = crate::BitReader; +#[doc = "Field `START_CMD` writer - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."] +pub type START_CMD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - Command index."] + #[inline(always)] + pub fn index(&self) -> INDEX_R { + INDEX_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - 0: No response expected from card; 1: Response expected from card."] + #[inline(always)] + pub fn response_expect(&self) -> RESPONSE_EXPECT_R { + RESPONSE_EXPECT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 0: Short response expected from card; 1: Long response expected from card."] + #[inline(always)] + pub fn response_length(&self) -> RESPONSE_LENGTH_R { + RESPONSE_LENGTH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."] + #[inline(always)] + pub fn check_response_crc(&self) -> CHECK_RESPONSE_CRC_R { + CHECK_RESPONSE_CRC_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 0: No data transfer expected; 1: Data transfer expected."] + #[inline(always)] + pub fn data_expected(&self) -> DATA_EXPECTED_R { + DATA_EXPECTED_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."] + #[inline(always)] + pub fn read_write(&self) -> READ_WRITE_R { + READ_WRITE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - 0: Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."] + #[inline(always)] + pub fn transfer_mode(&self) -> TRANSFER_MODE_R { + TRANSFER_MODE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."] + #[inline(always)] + pub fn send_auto_stop(&self) -> SEND_AUTO_STOP_R { + SEND_AUTO_STOP_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."] + #[inline(always)] + pub fn wait_prvdata_complete(&self) -> WAIT_PRVDATA_COMPLETE_R { + WAIT_PRVDATA_COMPLETE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."] + #[inline(always)] + pub fn stop_abort_cmd(&self) -> STOP_ABORT_CMD_R { + STOP_ABORT_CMD_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."] + #[inline(always)] + pub fn send_initialization(&self) -> SEND_INITIALIZATION_R { + SEND_INITIALIZATION_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:20 - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."] + #[inline(always)] + pub fn card_number(&self) -> CARD_NUMBER_R { + CARD_NUMBER_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bit 21 - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."] + #[inline(always)] + pub fn update_clock_registers_only(&self) -> UPDATE_CLOCK_REGISTERS_ONLY_R { + UPDATE_CLOCK_REGISTERS_ONLY_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."] + #[inline(always)] + pub fn read_ceata_device(&self) -> READ_CEATA_DEVICE_R { + READ_CEATA_DEVICE_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."] + #[inline(always)] + pub fn ccs_expected(&self) -> CCS_EXPECTED_R { + CCS_EXPECTED_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 29 - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."] + #[inline(always)] + pub fn use_hole(&self) -> USE_HOLE_R { + USE_HOLE_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 31 - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."] + #[inline(always)] + pub fn start_cmd(&self) -> START_CMD_R { + START_CMD_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CMD") + .field("index", &format_args!("{}", self.index().bits())) + .field( + "response_expect", + &format_args!("{}", self.response_expect().bit()), + ) + .field( + "response_length", + &format_args!("{}", self.response_length().bit()), + ) + .field( + "check_response_crc", + &format_args!("{}", self.check_response_crc().bit()), + ) + .field( + "data_expected", + &format_args!("{}", self.data_expected().bit()), + ) + .field("read_write", &format_args!("{}", self.read_write().bit())) + .field( + "transfer_mode", + &format_args!("{}", self.transfer_mode().bit()), + ) + .field( + "send_auto_stop", + &format_args!("{}", self.send_auto_stop().bit()), + ) + .field( + "wait_prvdata_complete", + &format_args!("{}", self.wait_prvdata_complete().bit()), + ) + .field( + "stop_abort_cmd", + &format_args!("{}", self.stop_abort_cmd().bit()), + ) + .field( + "send_initialization", + &format_args!("{}", self.send_initialization().bit()), + ) + .field( + "card_number", + &format_args!("{}", self.card_number().bits()), + ) + .field( + "update_clock_registers_only", + &format_args!("{}", self.update_clock_registers_only().bit()), + ) + .field( + "read_ceata_device", + &format_args!("{}", self.read_ceata_device().bit()), + ) + .field( + "ccs_expected", + &format_args!("{}", self.ccs_expected().bit()), + ) + .field("use_hole", &format_args!("{}", self.use_hole().bit())) + .field("start_cmd", &format_args!("{}", self.start_cmd().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - Command index."] + #[inline(always)] + #[must_use] + pub fn index(&mut self) -> INDEX_W { + INDEX_W::new(self, 0) + } + #[doc = "Bit 6 - 0: No response expected from card; 1: Response expected from card."] + #[inline(always)] + #[must_use] + pub fn response_expect(&mut self) -> RESPONSE_EXPECT_W { + RESPONSE_EXPECT_W::new(self, 6) + } + #[doc = "Bit 7 - 0: Short response expected from card; 1: Long response expected from card."] + #[inline(always)] + #[must_use] + pub fn response_length(&mut self) -> RESPONSE_LENGTH_W { + RESPONSE_LENGTH_W::new(self, 7) + } + #[doc = "Bit 8 - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."] + #[inline(always)] + #[must_use] + pub fn check_response_crc(&mut self) -> CHECK_RESPONSE_CRC_W { + CHECK_RESPONSE_CRC_W::new(self, 8) + } + #[doc = "Bit 9 - 0: No data transfer expected; 1: Data transfer expected."] + #[inline(always)] + #[must_use] + pub fn data_expected(&mut self) -> DATA_EXPECTED_W { + DATA_EXPECTED_W::new(self, 9) + } + #[doc = "Bit 10 - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."] + #[inline(always)] + #[must_use] + pub fn read_write(&mut self) -> READ_WRITE_W { + READ_WRITE_W::new(self, 10) + } + #[doc = "Bit 11 - 0: Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."] + #[inline(always)] + #[must_use] + pub fn transfer_mode(&mut self) -> TRANSFER_MODE_W { + TRANSFER_MODE_W::new(self, 11) + } + #[doc = "Bit 12 - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."] + #[inline(always)] + #[must_use] + pub fn send_auto_stop(&mut self) -> SEND_AUTO_STOP_W { + SEND_AUTO_STOP_W::new(self, 12) + } + #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE\\] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."] + #[inline(always)] + #[must_use] + pub fn wait_prvdata_complete(&mut self) -> WAIT_PRVDATA_COMPLETE_W { + WAIT_PRVDATA_COMPLETE_W::new(self, 13) + } + #[doc = "Bit 14 - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."] + #[inline(always)] + #[must_use] + pub fn stop_abort_cmd(&mut self) -> STOP_ABORT_CMD_W { + STOP_ABORT_CMD_W::new(self, 14) + } + #[doc = "Bit 15 - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."] + #[inline(always)] + #[must_use] + pub fn send_initialization(&mut self) -> SEND_INITIALIZATION_W { + SEND_INITIALIZATION_W::new(self, 15) + } + #[doc = "Bits 16:20 - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."] + #[inline(always)] + #[must_use] + pub fn card_number(&mut self) -> CARD_NUMBER_W { + CARD_NUMBER_W::new(self, 16) + } + #[doc = "Bit 21 - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."] + #[inline(always)] + #[must_use] + pub fn update_clock_registers_only(&mut self) -> UPDATE_CLOCK_REGISTERS_ONLY_W { + UPDATE_CLOCK_REGISTERS_ONLY_W::new(self, 21) + } + #[doc = "Bit 22 - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."] + #[inline(always)] + #[must_use] + pub fn read_ceata_device(&mut self) -> READ_CEATA_DEVICE_W { + READ_CEATA_DEVICE_W::new(self, 22) + } + #[doc = "Bit 23 - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."] + #[inline(always)] + #[must_use] + pub fn ccs_expected(&mut self) -> CCS_EXPECTED_W { + CCS_EXPECTED_W::new(self, 23) + } + #[doc = "Bit 29 - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."] + #[inline(always)] + #[must_use] + pub fn use_hole(&mut self) -> USE_HOLE_W { + USE_HOLE_W::new(self, 29) + } + #[doc = "Bit 31 - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."] + #[inline(always)] + #[must_use] + pub fn start_cmd(&mut self) -> START_CMD_W { + START_CMD_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Command and boot configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CMD_SPEC; +impl crate::RegisterSpec for CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmd::R`](R) reader structure"] +impl crate::Readable for CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"] +impl crate::Writable for CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMD to value 0x2000_0000"] +impl crate::Resettable for CMD_SPEC { + const RESET_VALUE: Self::Ux = 0x2000_0000; +} diff --git a/esp32p4/src/sdhost/cmdarg.rs b/esp32p4/src/sdhost/cmdarg.rs new file mode 100644 index 0000000000..b3d88b19a1 --- /dev/null +++ b/esp32p4/src/sdhost/cmdarg.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CMDARG` reader"] +pub type R = crate::R; +#[doc = "Register `CMDARG` writer"] +pub type W = crate::W; +#[doc = "Field `CMDARG` reader - Value indicates command argument to be passed to the card."] +pub type CMDARG_R = crate::FieldReader; +#[doc = "Field `CMDARG` writer - Value indicates command argument to be passed to the card."] +pub type CMDARG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Value indicates command argument to be passed to the card."] + #[inline(always)] + pub fn cmdarg(&self) -> CMDARG_R { + CMDARG_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CMDARG") + .field("cmdarg", &format_args!("{}", self.cmdarg().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Value indicates command argument to be passed to the card."] + #[inline(always)] + #[must_use] + pub fn cmdarg(&mut self) -> CMDARG_W { + CMDARG_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Command argument data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdarg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdarg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CMDARG_SPEC; +impl crate::RegisterSpec for CMDARG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmdarg::R`](R) reader structure"] +impl crate::Readable for CMDARG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmdarg::W`](W) writer structure"] +impl crate::Writable for CMDARG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMDARG to value 0"] +impl crate::Resettable for CMDARG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/ctrl.rs b/esp32p4/src/sdhost/ctrl.rs new file mode 100644 index 0000000000..e413f76998 --- /dev/null +++ b/esp32p4/src/sdhost/ctrl.rs @@ -0,0 +1,222 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CONTROLLER_RESET` reader - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."] +pub type CONTROLLER_RESET_R = crate::BitReader; +#[doc = "Field `CONTROLLER_RESET` writer - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."] +pub type CONTROLLER_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_RESET` reader - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."] +pub type FIFO_RESET_R = crate::BitReader; +#[doc = "Field `FIFO_RESET` writer - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."] +pub type FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_RESET` reader - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."] +pub type DMA_RESET_R = crate::BitReader; +#[doc = "Field `DMA_RESET` writer - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."] +pub type DMA_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INT_ENABLE` reader - Global interrupt enable/disable bit. 0: Disable; 1: Enable."] +pub type INT_ENABLE_R = crate::BitReader; +#[doc = "Field `INT_ENABLE` writer - Global interrupt enable/disable bit. 0: Disable; 1: Enable."] +pub type INT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `READ_WAIT` reader - For sending read-wait to SDIO cards."] +pub type READ_WAIT_R = crate::BitReader; +#[doc = "Field `READ_WAIT` writer - For sending read-wait to SDIO cards."] +pub type READ_WAIT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_IRQ_RESPONSE` reader - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."] +pub type SEND_IRQ_RESPONSE_R = crate::BitReader; +#[doc = "Field `SEND_IRQ_RESPONSE` writer - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."] +pub type SEND_IRQ_RESPONSE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ABORT_READ_DATA` reader - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."] +pub type ABORT_READ_DATA_R = crate::BitReader; +#[doc = "Field `ABORT_READ_DATA` writer - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."] +pub type ABORT_READ_DATA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_CCSD` reader - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."] +pub type SEND_CCSD_R = crate::BitReader; +#[doc = "Field `SEND_CCSD` writer - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."] +pub type SEND_CCSD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_AUTO_STOP_CCSD` reader - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."] +pub type SEND_AUTO_STOP_CCSD_R = crate::BitReader; +#[doc = "Field `SEND_AUTO_STOP_CCSD` writer - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."] +pub type SEND_AUTO_STOP_CCSD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CEATA_DEVICE_INTERRUPT_STATUS` reader - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."] +pub type CEATA_DEVICE_INTERRUPT_STATUS_R = crate::BitReader; +#[doc = "Field `CEATA_DEVICE_INTERRUPT_STATUS` writer - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."] +pub type CEATA_DEVICE_INTERRUPT_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."] + #[inline(always)] + pub fn controller_reset(&self) -> CONTROLLER_RESET_R { + CONTROLLER_RESET_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."] + #[inline(always)] + pub fn fifo_reset(&self) -> FIFO_RESET_R { + FIFO_RESET_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."] + #[inline(always)] + pub fn dma_reset(&self) -> DMA_RESET_R { + DMA_RESET_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Global interrupt enable/disable bit. 0: Disable; 1: Enable."] + #[inline(always)] + pub fn int_enable(&self) -> INT_ENABLE_R { + INT_ENABLE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - For sending read-wait to SDIO cards."] + #[inline(always)] + pub fn read_wait(&self) -> READ_WAIT_R { + READ_WAIT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."] + #[inline(always)] + pub fn send_irq_response(&self) -> SEND_IRQ_RESPONSE_R { + SEND_IRQ_RESPONSE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."] + #[inline(always)] + pub fn abort_read_data(&self) -> ABORT_READ_DATA_R { + ABORT_READ_DATA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."] + #[inline(always)] + pub fn send_ccsd(&self) -> SEND_CCSD_R { + SEND_CCSD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."] + #[inline(always)] + pub fn send_auto_stop_ccsd(&self) -> SEND_AUTO_STOP_CCSD_R { + SEND_AUTO_STOP_CCSD_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."] + #[inline(always)] + pub fn ceata_device_interrupt_status(&self) -> CEATA_DEVICE_INTERRUPT_STATUS_R { + CEATA_DEVICE_INTERRUPT_STATUS_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTRL") + .field( + "controller_reset", + &format_args!("{}", self.controller_reset().bit()), + ) + .field("fifo_reset", &format_args!("{}", self.fifo_reset().bit())) + .field("dma_reset", &format_args!("{}", self.dma_reset().bit())) + .field("int_enable", &format_args!("{}", self.int_enable().bit())) + .field("read_wait", &format_args!("{}", self.read_wait().bit())) + .field( + "send_irq_response", + &format_args!("{}", self.send_irq_response().bit()), + ) + .field( + "abort_read_data", + &format_args!("{}", self.abort_read_data().bit()), + ) + .field("send_ccsd", &format_args!("{}", self.send_ccsd().bit())) + .field( + "send_auto_stop_ccsd", + &format_args!("{}", self.send_auto_stop_ccsd().bit()), + ) + .field( + "ceata_device_interrupt_status", + &format_args!("{}", self.ceata_device_interrupt_status().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."] + #[inline(always)] + #[must_use] + pub fn controller_reset(&mut self) -> CONTROLLER_RESET_W { + CONTROLLER_RESET_W::new(self, 0) + } + #[doc = "Bit 1 - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."] + #[inline(always)] + #[must_use] + pub fn fifo_reset(&mut self) -> FIFO_RESET_W { + FIFO_RESET_W::new(self, 1) + } + #[doc = "Bit 2 - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."] + #[inline(always)] + #[must_use] + pub fn dma_reset(&mut self) -> DMA_RESET_W { + DMA_RESET_W::new(self, 2) + } + #[doc = "Bit 4 - Global interrupt enable/disable bit. 0: Disable; 1: Enable."] + #[inline(always)] + #[must_use] + pub fn int_enable(&mut self) -> INT_ENABLE_W { + INT_ENABLE_W::new(self, 4) + } + #[doc = "Bit 6 - For sending read-wait to SDIO cards."] + #[inline(always)] + #[must_use] + pub fn read_wait(&mut self) -> READ_WAIT_W { + READ_WAIT_W::new(self, 6) + } + #[doc = "Bit 7 - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."] + #[inline(always)] + #[must_use] + pub fn send_irq_response(&mut self) -> SEND_IRQ_RESPONSE_W { + SEND_IRQ_RESPONSE_W::new(self, 7) + } + #[doc = "Bit 8 - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."] + #[inline(always)] + #[must_use] + pub fn abort_read_data(&mut self) -> ABORT_READ_DATA_W { + ABORT_READ_DATA_W::new(self, 8) + } + #[doc = "Bit 9 - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."] + #[inline(always)] + #[must_use] + pub fn send_ccsd(&mut self) -> SEND_CCSD_W { + SEND_CCSD_W::new(self, 9) + } + #[doc = "Bit 10 - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."] + #[inline(always)] + #[must_use] + pub fn send_auto_stop_ccsd(&mut self) -> SEND_AUTO_STOP_CCSD_W { + SEND_AUTO_STOP_CCSD_W::new(self, 10) + } + #[doc = "Bit 11 - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."] + #[inline(always)] + #[must_use] + pub fn ceata_device_interrupt_status(&mut self) -> CEATA_DEVICE_INTERRUPT_STATUS_W { + CEATA_DEVICE_INTERRUPT_STATUS_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/ctype.rs b/esp32p4/src/sdhost/ctype.rs new file mode 100644 index 0000000000..15188a4ac2 --- /dev/null +++ b/esp32p4/src/sdhost/ctype.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CTYPE` reader"] +pub type R = crate::R; +#[doc = "Register `CTYPE` writer"] +pub type W = crate::W; +#[doc = "Field `CARD_WIDTH4` reader - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."] +pub type CARD_WIDTH4_R = crate::FieldReader; +#[doc = "Field `CARD_WIDTH4` writer - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."] +pub type CARD_WIDTH4_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CARD_WIDTH8` reader - One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit\\[17:16\\] correspond to card\\[1:0\\] respectively."] +pub type CARD_WIDTH8_R = crate::FieldReader; +#[doc = "Field `CARD_WIDTH8` writer - One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit\\[17:16\\] correspond to card\\[1:0\\] respectively."] +pub type CARD_WIDTH8_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."] + #[inline(always)] + pub fn card_width4(&self) -> CARD_WIDTH4_R { + CARD_WIDTH4_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 16:17 - One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit\\[17:16\\] correspond to card\\[1:0\\] respectively."] + #[inline(always)] + pub fn card_width8(&self) -> CARD_WIDTH8_R { + CARD_WIDTH8_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CTYPE") + .field( + "card_width4", + &format_args!("{}", self.card_width4().bits()), + ) + .field( + "card_width8", + &format_args!("{}", self.card_width8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."] + #[inline(always)] + #[must_use] + pub fn card_width4(&mut self) -> CARD_WIDTH4_W { + CARD_WIDTH4_W::new(self, 0) + } + #[doc = "Bits 16:17 - One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit\\[17:16\\] correspond to card\\[1:0\\] respectively."] + #[inline(always)] + #[must_use] + pub fn card_width8(&mut self) -> CARD_WIDTH8_W { + CARD_WIDTH8_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Card bus width configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctype::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctype::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTYPE_SPEC; +impl crate::RegisterSpec for CTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctype::R`](R) reader structure"] +impl crate::Readable for CTYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctype::W`](W) writer structure"] +impl crate::Writable for CTYPE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTYPE to value 0"] +impl crate::Resettable for CTYPE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/dbaddr.rs b/esp32p4/src/sdhost/dbaddr.rs new file mode 100644 index 0000000000..348c2c99a8 --- /dev/null +++ b/esp32p4/src/sdhost/dbaddr.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DBADDR` reader"] +pub type R = crate::R; +#[doc = "Register `DBADDR` writer"] +pub type W = crate::W; +#[doc = "Field `DBADDR` reader - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."] +pub type DBADDR_R = crate::FieldReader; +#[doc = "Field `DBADDR` writer - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."] +pub type DBADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."] + #[inline(always)] + pub fn dbaddr(&self) -> DBADDR_R { + DBADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DBADDR") + .field("dbaddr", &format_args!("{}", self.dbaddr().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."] + #[inline(always)] + #[must_use] + pub fn dbaddr(&mut self) -> DBADDR_W { + DBADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Descriptor base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbaddr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBADDR_SPEC; +impl crate::RegisterSpec for DBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbaddr::R`](R) reader structure"] +impl crate::Readable for DBADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbaddr::W`](W) writer structure"] +impl crate::Writable for DBADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBADDR to value 0"] +impl crate::Resettable for DBADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/debnce.rs b/esp32p4/src/sdhost/debnce.rs new file mode 100644 index 0000000000..c5f99cd76d --- /dev/null +++ b/esp32p4/src/sdhost/debnce.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DEBNCE` reader"] +pub type R = crate::R; +#[doc = "Register `DEBNCE` writer"] +pub type W = crate::W; +#[doc = "Field `DEBOUNCE_COUNT` reader - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."] +pub type DEBOUNCE_COUNT_R = crate::FieldReader; +#[doc = "Field `DEBOUNCE_COUNT` writer - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."] +pub type DEBOUNCE_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."] + #[inline(always)] + pub fn debounce_count(&self) -> DEBOUNCE_COUNT_R { + DEBOUNCE_COUNT_R::new(self.bits & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DEBNCE") + .field( + "debounce_count", + &format_args!("{}", self.debounce_count().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."] + #[inline(always)] + #[must_use] + pub fn debounce_count(&mut self) -> DEBOUNCE_COUNT_W { + DEBOUNCE_COUNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Debounce filter time configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debnce::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debnce::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEBNCE_SPEC; +impl crate::RegisterSpec for DEBNCE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`debnce::R`](R) reader structure"] +impl crate::Readable for DEBNCE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`debnce::W`](W) writer structure"] +impl crate::Writable for DEBNCE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DEBNCE to value 0"] +impl crate::Resettable for DEBNCE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/dll_clk_conf.rs b/esp32p4/src/sdhost/dll_clk_conf.rs new file mode 100644 index 0000000000..45c494f301 --- /dev/null +++ b/esp32p4/src/sdhost/dll_clk_conf.rs @@ -0,0 +1,161 @@ +#[doc = "Register `DLL_CLK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `DLL_CLK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `DLL_CCLK_IN_SLF_EN` reader - Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_SLF_EN_R = crate::BitReader; +#[doc = "Field `DLL_CCLK_IN_SLF_EN` writer - Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_SLF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DLL_CCLK_IN_DRV_EN` reader - Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_DRV_EN_R = crate::BitReader; +#[doc = "Field `DLL_CCLK_IN_DRV_EN` writer - Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_DRV_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DLL_CCLK_IN_SAM_EN` reader - Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_SAM_EN_R = crate::BitReader; +#[doc = "Field `DLL_CCLK_IN_SAM_EN` writer - Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_SAM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DLL_CCLK_IN_SLF_PHASE` reader - It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_SLF_PHASE_R = crate::FieldReader; +#[doc = "Field `DLL_CCLK_IN_SLF_PHASE` writer - It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_SLF_PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `DLL_CCLK_IN_DRV_PHASE` reader - It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_DRV_PHASE_R = crate::FieldReader; +#[doc = "Field `DLL_CCLK_IN_DRV_PHASE` writer - It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_DRV_PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `DLL_CCLK_IN_SAM_PHASE` reader - It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_SAM_PHASE_R = crate::FieldReader; +#[doc = "Field `DLL_CCLK_IN_SAM_PHASE` writer - It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1."] +pub type DLL_CCLK_IN_SAM_PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + pub fn dll_cclk_in_slf_en(&self) -> DLL_CCLK_IN_SLF_EN_R { + DLL_CCLK_IN_SLF_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + pub fn dll_cclk_in_drv_en(&self) -> DLL_CCLK_IN_DRV_EN_R { + DLL_CCLK_IN_DRV_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + pub fn dll_cclk_in_sam_en(&self) -> DLL_CCLK_IN_SAM_EN_R { + DLL_CCLK_IN_SAM_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:8 - It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + pub fn dll_cclk_in_slf_phase(&self) -> DLL_CCLK_IN_SLF_PHASE_R { + DLL_CCLK_IN_SLF_PHASE_R::new(((self.bits >> 3) & 0x3f) as u8) + } + #[doc = "Bits 9:14 - It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + pub fn dll_cclk_in_drv_phase(&self) -> DLL_CCLK_IN_DRV_PHASE_R { + DLL_CCLK_IN_DRV_PHASE_R::new(((self.bits >> 9) & 0x3f) as u8) + } + #[doc = "Bits 15:20 - It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + pub fn dll_cclk_in_sam_phase(&self) -> DLL_CCLK_IN_SAM_PHASE_R { + DLL_CCLK_IN_SAM_PHASE_R::new(((self.bits >> 15) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DLL_CLK_CONF") + .field( + "dll_cclk_in_slf_en", + &format_args!("{}", self.dll_cclk_in_slf_en().bit()), + ) + .field( + "dll_cclk_in_drv_en", + &format_args!("{}", self.dll_cclk_in_drv_en().bit()), + ) + .field( + "dll_cclk_in_sam_en", + &format_args!("{}", self.dll_cclk_in_sam_en().bit()), + ) + .field( + "dll_cclk_in_slf_phase", + &format_args!("{}", self.dll_cclk_in_slf_phase().bits()), + ) + .field( + "dll_cclk_in_drv_phase", + &format_args!("{}", self.dll_cclk_in_drv_phase().bits()), + ) + .field( + "dll_cclk_in_sam_phase", + &format_args!("{}", self.dll_cclk_in_sam_phase().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + #[must_use] + pub fn dll_cclk_in_slf_en(&mut self) -> DLL_CCLK_IN_SLF_EN_W { + DLL_CCLK_IN_SLF_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + #[must_use] + pub fn dll_cclk_in_drv_en(&mut self) -> DLL_CCLK_IN_DRV_EN_W { + DLL_CCLK_IN_DRV_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + #[must_use] + pub fn dll_cclk_in_sam_en(&mut self) -> DLL_CCLK_IN_SAM_EN_W { + DLL_CCLK_IN_SAM_EN_W::new(self, 2) + } + #[doc = "Bits 3:8 - It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + #[must_use] + pub fn dll_cclk_in_slf_phase(&mut self) -> DLL_CCLK_IN_SLF_PHASE_W { + DLL_CCLK_IN_SLF_PHASE_W::new(self, 3) + } + #[doc = "Bits 9:14 - It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + #[must_use] + pub fn dll_cclk_in_drv_phase(&mut self) -> DLL_CCLK_IN_DRV_PHASE_W { + DLL_CCLK_IN_DRV_PHASE_W::new(self, 9) + } + #[doc = "Bits 15:20 - It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1."] + #[inline(always)] + #[must_use] + pub fn dll_cclk_in_sam_phase(&mut self) -> DLL_CCLK_IN_SAM_PHASE_W { + DLL_CCLK_IN_SAM_PHASE_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SDIO DLL clock control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll_clk_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll_clk_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DLL_CLK_CONF_SPEC; +impl crate::RegisterSpec for DLL_CLK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dll_clk_conf::R`](R) reader structure"] +impl crate::Readable for DLL_CLK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dll_clk_conf::W`](W) writer structure"] +impl crate::Writable for DLL_CLK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DLL_CLK_CONF to value 0"] +impl crate::Resettable for DLL_CLK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/dll_conf.rs b/esp32p4/src/sdhost/dll_conf.rs new file mode 100644 index 0000000000..ee3ae6a2ac --- /dev/null +++ b/esp32p4/src/sdhost/dll_conf.rs @@ -0,0 +1,74 @@ +#[doc = "Register `DLL_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `DLL_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `DLL_CAL_STOP` reader - Set 1 to stop calibration."] +pub type DLL_CAL_STOP_R = crate::BitReader; +#[doc = "Field `DLL_CAL_STOP` writer - Set 1 to stop calibration."] +pub type DLL_CAL_STOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DLL_CAL_END` reader - 1 means calibration finished."] +pub type DLL_CAL_END_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Set 1 to stop calibration."] + #[inline(always)] + pub fn dll_cal_stop(&self) -> DLL_CAL_STOP_R { + DLL_CAL_STOP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1 means calibration finished."] + #[inline(always)] + pub fn dll_cal_end(&self) -> DLL_CAL_END_R { + DLL_CAL_END_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DLL_CONF") + .field( + "dll_cal_stop", + &format_args!("{}", self.dll_cal_stop().bit()), + ) + .field("dll_cal_end", &format_args!("{}", self.dll_cal_end().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 to stop calibration."] + #[inline(always)] + #[must_use] + pub fn dll_cal_stop(&mut self) -> DLL_CAL_STOP_W { + DLL_CAL_STOP_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SDIO DLL configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DLL_CONF_SPEC; +impl crate::RegisterSpec for DLL_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dll_conf::R`](R) reader structure"] +impl crate::Readable for DLL_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dll_conf::W`](W) writer structure"] +impl crate::Writable for DLL_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DLL_CONF to value 0"] +impl crate::Resettable for DLL_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/dscaddr.rs b/esp32p4/src/sdhost/dscaddr.rs new file mode 100644 index 0000000000..2fe11ab50c --- /dev/null +++ b/esp32p4/src/sdhost/dscaddr.rs @@ -0,0 +1,36 @@ +#[doc = "Register `DSCADDR` reader"] +pub type R = crate::R; +#[doc = "Field `DSCADDR` reader - Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC."] +pub type DSCADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC."] + #[inline(always)] + pub fn dscaddr(&self) -> DSCADDR_R { + DSCADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSCADDR") + .field("dscaddr", &format_args!("{}", self.dscaddr().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Host descriptor address pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscaddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DSCADDR_SPEC; +impl crate::RegisterSpec for DSCADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dscaddr::R`](R) reader structure"] +impl crate::Readable for DSCADDR_SPEC {} +#[doc = "`reset()` method sets DSCADDR to value 0"] +impl crate::Resettable for DSCADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/emmcddr.rs b/esp32p4/src/sdhost/emmcddr.rs new file mode 100644 index 0000000000..f0d8f73f63 --- /dev/null +++ b/esp32p4/src/sdhost/emmcddr.rs @@ -0,0 +1,82 @@ +#[doc = "Register `EMMCDDR` reader"] +pub type R = crate::R; +#[doc = "Register `EMMCDDR` writer"] +pub type W = crate::W; +#[doc = "Field `HALFSTARTBIT` reader - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."] +pub type HALFSTARTBIT_R = crate::FieldReader; +#[doc = "Field `HALFSTARTBIT` writer - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."] +pub type HALFSTARTBIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `HS400_MODE` reader - Set 1 to enable HS400 mode."] +pub type HS400_MODE_R = crate::BitReader; +#[doc = "Field `HS400_MODE` writer - Set 1 to enable HS400 mode."] +pub type HS400_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."] + #[inline(always)] + pub fn halfstartbit(&self) -> HALFSTARTBIT_R { + HALFSTARTBIT_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 31 - Set 1 to enable HS400 mode."] + #[inline(always)] + pub fn hs400_mode(&self) -> HS400_MODE_R { + HS400_MODE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EMMCDDR") + .field( + "halfstartbit", + &format_args!("{}", self.halfstartbit().bits()), + ) + .field("hs400_mode", &format_args!("{}", self.hs400_mode().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."] + #[inline(always)] + #[must_use] + pub fn halfstartbit(&mut self) -> HALFSTARTBIT_W { + HALFSTARTBIT_W::new(self, 0) + } + #[doc = "Bit 31 - Set 1 to enable HS400 mode."] + #[inline(always)] + #[must_use] + pub fn hs400_mode(&mut self) -> HS400_MODE_W { + HS400_MODE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "eMMC DDR register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emmcddr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emmcddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EMMCDDR_SPEC; +impl crate::RegisterSpec for EMMCDDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`emmcddr::R`](R) reader structure"] +impl crate::Readable for EMMCDDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`emmcddr::W`](W) writer structure"] +impl crate::Writable for EMMCDDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EMMCDDR to value 0"] +impl crate::Resettable for EMMCDDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/enshift.rs b/esp32p4/src/sdhost/enshift.rs new file mode 100644 index 0000000000..b798c0553c --- /dev/null +++ b/esp32p4/src/sdhost/enshift.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ENSHIFT` reader"] +pub type R = crate::R; +#[doc = "Register `ENSHIFT` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE_SHIFT` reader - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."] +pub type ENABLE_SHIFT_R = crate::FieldReader; +#[doc = "Field `ENABLE_SHIFT` writer - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."] +pub type ENABLE_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."] + #[inline(always)] + pub fn enable_shift(&self) -> ENABLE_SHIFT_R { + ENABLE_SHIFT_R::new((self.bits & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ENSHIFT") + .field( + "enable_shift", + &format_args!("{}", self.enable_shift().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."] + #[inline(always)] + #[must_use] + pub fn enable_shift(&mut self) -> ENABLE_SHIFT_W { + ENABLE_SHIFT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Enable Phase Shift register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enshift::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enshift::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENSHIFT_SPEC; +impl crate::RegisterSpec for ENSHIFT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`enshift::R`](R) reader structure"] +impl crate::Readable for ENSHIFT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enshift::W`](W) writer structure"] +impl crate::Writable for ENSHIFT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ENSHIFT to value 0"] +impl crate::Resettable for ENSHIFT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/fifoth.rs b/esp32p4/src/sdhost/fifoth.rs new file mode 100644 index 0000000000..7f3cb85681 --- /dev/null +++ b/esp32p4/src/sdhost/fifoth.rs @@ -0,0 +1,100 @@ +#[doc = "Register `FIFOTH` reader"] +pub type R = crate::R; +#[doc = "Register `FIFOTH` writer"] +pub type W = crate::W; +#[doc = "Field `TX_WMARK` reader - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."] +pub type TX_WMARK_R = crate::FieldReader; +#[doc = "Field `TX_WMARK` writer - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."] +pub type TX_WMARK_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `RX_WMARK` reader - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."] +pub type RX_WMARK_R = crate::FieldReader; +#[doc = "Field `RX_WMARK` writer - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."] +pub type RX_WMARK_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `DMA_MULTIPLE_TRANSACTION_SIZE` reader - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."] +pub type DMA_MULTIPLE_TRANSACTION_SIZE_R = crate::FieldReader; +#[doc = "Field `DMA_MULTIPLE_TRANSACTION_SIZE` writer - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."] +pub type DMA_MULTIPLE_TRANSACTION_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."] + #[inline(always)] + pub fn tx_wmark(&self) -> TX_WMARK_R { + TX_WMARK_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:26 - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."] + #[inline(always)] + pub fn rx_wmark(&self) -> RX_WMARK_R { + RX_WMARK_R::new(((self.bits >> 16) & 0x07ff) as u16) + } + #[doc = "Bits 28:30 - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."] + #[inline(always)] + pub fn dma_multiple_transaction_size(&self) -> DMA_MULTIPLE_TRANSACTION_SIZE_R { + DMA_MULTIPLE_TRANSACTION_SIZE_R::new(((self.bits >> 28) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFOTH") + .field("tx_wmark", &format_args!("{}", self.tx_wmark().bits())) + .field("rx_wmark", &format_args!("{}", self.rx_wmark().bits())) + .field( + "dma_multiple_transaction_size", + &format_args!("{}", self.dma_multiple_transaction_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."] + #[inline(always)] + #[must_use] + pub fn tx_wmark(&mut self) -> TX_WMARK_W { + TX_WMARK_W::new(self, 0) + } + #[doc = "Bits 16:26 - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."] + #[inline(always)] + #[must_use] + pub fn rx_wmark(&mut self) -> RX_WMARK_W { + RX_WMARK_W::new(self, 16) + } + #[doc = "Bits 28:30 - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."] + #[inline(always)] + #[must_use] + pub fn dma_multiple_transaction_size( + &mut self, + ) -> DMA_MULTIPLE_TRANSACTION_SIZE_W { + DMA_MULTIPLE_TRANSACTION_SIZE_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "FIFO configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifoth::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifoth::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFOTH_SPEC; +impl crate::RegisterSpec for FIFOTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifoth::R`](R) reader structure"] +impl crate::Readable for FIFOTH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifoth::W`](W) writer structure"] +impl crate::Writable for FIFOTH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FIFOTH to value 0"] +impl crate::Resettable for FIFOTH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/hcon.rs b/esp32p4/src/sdhost/hcon.rs new file mode 100644 index 0000000000..63d04723f6 --- /dev/null +++ b/esp32p4/src/sdhost/hcon.rs @@ -0,0 +1,103 @@ +#[doc = "Register `HCON` reader"] +pub type R = crate::R; +#[doc = "Field `CARD_TYPE` reader - Hardware support SDIO and MMC."] +pub type CARD_TYPE_R = crate::BitReader; +#[doc = "Field `CARD_NUM` reader - Support card number is 2."] +pub type CARD_NUM_R = crate::FieldReader; +#[doc = "Field `BUS_TYPE` reader - Register config is APB bus."] +pub type BUS_TYPE_R = crate::BitReader; +#[doc = "Field `DATA_WIDTH` reader - Regisger data widht is 32."] +pub type DATA_WIDTH_R = crate::FieldReader; +#[doc = "Field `ADDR_WIDTH` reader - Register address width is 32."] +pub type ADDR_WIDTH_R = crate::FieldReader; +#[doc = "Field `DMA_WIDTH` reader - DMA data witdth is 32."] +pub type DMA_WIDTH_R = crate::FieldReader; +#[doc = "Field `RAM_INDISE` reader - Inside RAM in SDMMC module."] +pub type RAM_INDISE_R = crate::BitReader; +#[doc = "Field `HOLD` reader - Have a hold regiser in data path ."] +pub type HOLD_R = crate::BitReader; +#[doc = "Field `NUM_CLK_DIV` reader - Have 4 clk divider in design ."] +pub type NUM_CLK_DIV_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Hardware support SDIO and MMC."] + #[inline(always)] + pub fn card_type(&self) -> CARD_TYPE_R { + CARD_TYPE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:5 - Support card number is 2."] + #[inline(always)] + pub fn card_num(&self) -> CARD_NUM_R { + CARD_NUM_R::new(((self.bits >> 1) & 0x1f) as u8) + } + #[doc = "Bit 6 - Register config is APB bus."] + #[inline(always)] + pub fn bus_type(&self) -> BUS_TYPE_R { + BUS_TYPE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:9 - Regisger data widht is 32."] + #[inline(always)] + pub fn data_width(&self) -> DATA_WIDTH_R { + DATA_WIDTH_R::new(((self.bits >> 7) & 7) as u8) + } + #[doc = "Bits 10:15 - Register address width is 32."] + #[inline(always)] + pub fn addr_width(&self) -> ADDR_WIDTH_R { + ADDR_WIDTH_R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 18:20 - DMA data witdth is 32."] + #[inline(always)] + pub fn dma_width(&self) -> DMA_WIDTH_R { + DMA_WIDTH_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bit 21 - Inside RAM in SDMMC module."] + #[inline(always)] + pub fn ram_indise(&self) -> RAM_INDISE_R { + RAM_INDISE_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Have a hold regiser in data path ."] + #[inline(always)] + pub fn hold(&self) -> HOLD_R { + HOLD_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:25 - Have 4 clk divider in design ."] + #[inline(always)] + pub fn num_clk_div(&self) -> NUM_CLK_DIV_R { + NUM_CLK_DIV_R::new(((self.bits >> 24) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HCON") + .field("card_type", &format_args!("{}", self.card_type().bit())) + .field("card_num", &format_args!("{}", self.card_num().bits())) + .field("bus_type", &format_args!("{}", self.bus_type().bit())) + .field("data_width", &format_args!("{}", self.data_width().bits())) + .field("addr_width", &format_args!("{}", self.addr_width().bits())) + .field("dma_width", &format_args!("{}", self.dma_width().bits())) + .field("ram_indise", &format_args!("{}", self.ram_indise().bit())) + .field("hold", &format_args!("{}", self.hold().bit())) + .field( + "num_clk_div", + &format_args!("{}", self.num_clk_div().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Hardware feature register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcon::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HCON_SPEC; +impl crate::RegisterSpec for HCON_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hcon::R`](R) reader structure"] +impl crate::Readable for HCON_SPEC {} +#[doc = "`reset()` method sets HCON to value 0x0344_4cc3"] +impl crate::Resettable for HCON_SPEC { + const RESET_VALUE: Self::Ux = 0x0344_4cc3; +} diff --git a/esp32p4/src/sdhost/idinten.rs b/esp32p4/src/sdhost/idinten.rs new file mode 100644 index 0000000000..aa27bb83ac --- /dev/null +++ b/esp32p4/src/sdhost/idinten.rs @@ -0,0 +1,159 @@ +#[doc = "Register `IDINTEN` reader"] +pub type R = crate::R; +#[doc = "Register `IDINTEN` writer"] +pub type W = crate::W; +#[doc = "Field `TI` reader - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."] +pub type TI_R = crate::BitReader; +#[doc = "Field `TI` writer - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."] +pub type TI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RI` reader - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."] +pub type RI_R = crate::BitReader; +#[doc = "Field `RI` writer - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."] +pub type RI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FBE` reader - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."] +pub type FBE_R = crate::BitReader; +#[doc = "Field `FBE` writer - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."] +pub type FBE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DU` reader - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."] +pub type DU_R = crate::BitReader; +#[doc = "Field `DU` writer - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."] +pub type DU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CES` reader - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."] +pub type CES_R = crate::BitReader; +#[doc = "Field `CES` writer - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."] +pub type CES_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NI` reader - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN\\[0\\]: Transmit Interrupt; IDINTEN\\[1\\]: Receive Interrupt."] +pub type NI_R = crate::BitReader; +#[doc = "Field `NI` writer - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN\\[0\\]: Transmit Interrupt; IDINTEN\\[1\\]: Receive Interrupt."] +pub type NI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AI` reader - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN\\[2\\]: Fatal Bus Error Interrupt; IDINTEN\\[4\\]: DU Interrupt."] +pub type AI_R = crate::BitReader; +#[doc = "Field `AI` writer - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN\\[2\\]: Fatal Bus Error Interrupt; IDINTEN\\[4\\]: DU Interrupt."] +pub type AI_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."] + #[inline(always)] + pub fn ti(&self) -> TI_R { + TI_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."] + #[inline(always)] + pub fn ri(&self) -> RI_R { + RI_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."] + #[inline(always)] + pub fn fbe(&self) -> FBE_R { + FBE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."] + #[inline(always)] + pub fn du(&self) -> DU_R { + DU_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."] + #[inline(always)] + pub fn ces(&self) -> CES_R { + CES_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN\\[0\\]: Transmit Interrupt; IDINTEN\\[1\\]: Receive Interrupt."] + #[inline(always)] + pub fn ni(&self) -> NI_R { + NI_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN\\[2\\]: Fatal Bus Error Interrupt; IDINTEN\\[4\\]: DU Interrupt."] + #[inline(always)] + pub fn ai(&self) -> AI_R { + AI_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IDINTEN") + .field("ti", &format_args!("{}", self.ti().bit())) + .field("ri", &format_args!("{}", self.ri().bit())) + .field("fbe", &format_args!("{}", self.fbe().bit())) + .field("du", &format_args!("{}", self.du().bit())) + .field("ces", &format_args!("{}", self.ces().bit())) + .field("ni", &format_args!("{}", self.ni().bit())) + .field("ai", &format_args!("{}", self.ai().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."] + #[inline(always)] + #[must_use] + pub fn ti(&mut self) -> TI_W { + TI_W::new(self, 0) + } + #[doc = "Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."] + #[inline(always)] + #[must_use] + pub fn ri(&mut self) -> RI_W { + RI_W::new(self, 1) + } + #[doc = "Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."] + #[inline(always)] + #[must_use] + pub fn fbe(&mut self) -> FBE_W { + FBE_W::new(self, 2) + } + #[doc = "Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."] + #[inline(always)] + #[must_use] + pub fn du(&mut self) -> DU_W { + DU_W::new(self, 4) + } + #[doc = "Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."] + #[inline(always)] + #[must_use] + pub fn ces(&mut self) -> CES_W { + CES_W::new(self, 5) + } + #[doc = "Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN\\[0\\]: Transmit Interrupt; IDINTEN\\[1\\]: Receive Interrupt."] + #[inline(always)] + #[must_use] + pub fn ni(&mut self) -> NI_W { + NI_W::new(self, 8) + } + #[doc = "Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN\\[2\\]: Fatal Bus Error Interrupt; IDINTEN\\[4\\]: DU Interrupt."] + #[inline(always)] + #[must_use] + pub fn ai(&mut self) -> AI_W { + AI_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "IDMAC interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idinten::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idinten::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IDINTEN_SPEC; +impl crate::RegisterSpec for IDINTEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`idinten::R`](R) reader structure"] +impl crate::Readable for IDINTEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`idinten::W`](W) writer structure"] +impl crate::Writable for IDINTEN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IDINTEN to value 0"] +impl crate::Resettable for IDINTEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/idsts.rs b/esp32p4/src/sdhost/idsts.rs new file mode 100644 index 0000000000..543fdcb83b --- /dev/null +++ b/esp32p4/src/sdhost/idsts.rs @@ -0,0 +1,191 @@ +#[doc = "Register `IDSTS` reader"] +pub type R = crate::R; +#[doc = "Register `IDSTS` writer"] +pub type W = crate::W; +#[doc = "Field `TI` reader - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."] +pub type TI_R = crate::BitReader; +#[doc = "Field `TI` writer - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."] +pub type TI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RI` reader - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."] +pub type RI_R = crate::BitReader; +#[doc = "Field `RI` writer - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."] +pub type RI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FBE` reader - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."] +pub type FBE_R = crate::BitReader; +#[doc = "Field `FBE` writer - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."] +pub type FBE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DU` reader - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."] +pub type DU_R = crate::BitReader; +#[doc = "Field `DU` writer - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."] +pub type DU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CES` reader - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."] +pub type CES_R = crate::BitReader; +#[doc = "Field `CES` writer - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."] +pub type CES_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NIS` reader - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."] +pub type NIS_R = crate::BitReader; +#[doc = "Field `NIS` writer - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."] +pub type NIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AIS` reader - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."] +pub type AIS_R = crate::BitReader; +#[doc = "Field `AIS` writer - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."] +pub type AIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FBE_CODE` reader - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."] +pub type FBE_CODE_R = crate::FieldReader; +#[doc = "Field `FBE_CODE` writer - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."] +pub type FBE_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `FSM` reader - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."] +pub type FSM_R = crate::FieldReader; +#[doc = "Field `FSM` writer - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."] +pub type FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."] + #[inline(always)] + pub fn ti(&self) -> TI_R { + TI_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."] + #[inline(always)] + pub fn ri(&self) -> RI_R { + RI_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."] + #[inline(always)] + pub fn fbe(&self) -> FBE_R { + FBE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."] + #[inline(always)] + pub fn du(&self) -> DU_R { + DU_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."] + #[inline(always)] + pub fn ces(&self) -> CES_R { + CES_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."] + #[inline(always)] + pub fn nis(&self) -> NIS_R { + NIS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."] + #[inline(always)] + pub fn ais(&self) -> AIS_R { + AIS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:12 - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."] + #[inline(always)] + pub fn fbe_code(&self) -> FBE_CODE_R { + FBE_CODE_R::new(((self.bits >> 10) & 7) as u8) + } + #[doc = "Bits 13:16 - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."] + #[inline(always)] + pub fn fsm(&self) -> FSM_R { + FSM_R::new(((self.bits >> 13) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IDSTS") + .field("ti", &format_args!("{}", self.ti().bit())) + .field("ri", &format_args!("{}", self.ri().bit())) + .field("fbe", &format_args!("{}", self.fbe().bit())) + .field("du", &format_args!("{}", self.du().bit())) + .field("ces", &format_args!("{}", self.ces().bit())) + .field("nis", &format_args!("{}", self.nis().bit())) + .field("ais", &format_args!("{}", self.ais().bit())) + .field("fbe_code", &format_args!("{}", self.fbe_code().bits())) + .field("fsm", &format_args!("{}", self.fsm().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."] + #[inline(always)] + #[must_use] + pub fn ti(&mut self) -> TI_W { + TI_W::new(self, 0) + } + #[doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."] + #[inline(always)] + #[must_use] + pub fn ri(&mut self) -> RI_W { + RI_W::new(self, 1) + } + #[doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."] + #[inline(always)] + #[must_use] + pub fn fbe(&mut self) -> FBE_W { + FBE_W::new(self, 2) + } + #[doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."] + #[inline(always)] + #[must_use] + pub fn du(&mut self) -> DU_W { + DU_W::new(self, 4) + } + #[doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."] + #[inline(always)] + #[must_use] + pub fn ces(&mut self) -> CES_W { + CES_W::new(self, 5) + } + #[doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."] + #[inline(always)] + #[must_use] + pub fn nis(&mut self) -> NIS_W { + NIS_W::new(self, 8) + } + #[doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."] + #[inline(always)] + #[must_use] + pub fn ais(&mut self) -> AIS_W { + AIS_W::new(self, 9) + } + #[doc = "Bits 10:12 - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."] + #[inline(always)] + #[must_use] + pub fn fbe_code(&mut self) -> FBE_CODE_W { + FBE_CODE_W::new(self, 10) + } + #[doc = "Bits 13:16 - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."] + #[inline(always)] + #[must_use] + pub fn fsm(&mut self) -> FSM_W { + FSM_W::new(self, 13) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "IDMAC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idsts::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IDSTS_SPEC; +impl crate::RegisterSpec for IDSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`idsts::R`](R) reader structure"] +impl crate::Readable for IDSTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`idsts::W`](W) writer structure"] +impl crate::Writable for IDSTS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IDSTS to value 0"] +impl crate::Resettable for IDSTS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/intmask.rs b/esp32p4/src/sdhost/intmask.rs new file mode 100644 index 0000000000..6e0892b34f --- /dev/null +++ b/esp32p4/src/sdhost/intmask.rs @@ -0,0 +1,82 @@ +#[doc = "Register `INTMASK` reader"] +pub type R = crate::R; +#[doc = "Register `INTMASK` writer"] +pub type W = crate::W; +#[doc = "Field `INT_MASK` reader - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."] +pub type INT_MASK_R = crate::FieldReader; +#[doc = "Field `INT_MASK` writer - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."] +pub type INT_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SDIO_INT_MASK` reader - SDIO interrupt mask, one bit for each card. Bit\\[17:16\\] correspond to card\\[15:0\\] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt."] +pub type SDIO_INT_MASK_R = crate::FieldReader; +#[doc = "Field `SDIO_INT_MASK` writer - SDIO interrupt mask, one bit for each card. Bit\\[17:16\\] correspond to card\\[15:0\\] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt."] +pub type SDIO_INT_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:15 - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."] + #[inline(always)] + pub fn int_mask(&self) -> INT_MASK_R { + INT_MASK_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:17 - SDIO interrupt mask, one bit for each card. Bit\\[17:16\\] correspond to card\\[15:0\\] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt."] + #[inline(always)] + pub fn sdio_int_mask(&self) -> SDIO_INT_MASK_R { + SDIO_INT_MASK_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTMASK") + .field("int_mask", &format_args!("{}", self.int_mask().bits())) + .field( + "sdio_int_mask", + &format_args!("{}", self.sdio_int_mask().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."] + #[inline(always)] + #[must_use] + pub fn int_mask(&mut self) -> INT_MASK_W { + INT_MASK_W::new(self, 0) + } + #[doc = "Bits 16:17 - SDIO interrupt mask, one bit for each card. Bit\\[17:16\\] correspond to card\\[15:0\\] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt."] + #[inline(always)] + #[must_use] + pub fn sdio_int_mask(&mut self) -> SDIO_INT_MASK_W { + SDIO_INT_MASK_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SDIO interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intmask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intmask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTMASK_SPEC; +impl crate::RegisterSpec for INTMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intmask::R`](R) reader structure"] +impl crate::Readable for INTMASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intmask::W`](W) writer structure"] +impl crate::Writable for INTMASK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTMASK to value 0"] +impl crate::Resettable for INTMASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/mintsts.rs b/esp32p4/src/sdhost/mintsts.rs new file mode 100644 index 0000000000..c847b0bc6b --- /dev/null +++ b/esp32p4/src/sdhost/mintsts.rs @@ -0,0 +1,50 @@ +#[doc = "Register `MINTSTS` reader"] +pub type R = crate::R; +#[doc = "Field `INT_STATUS_MSK` reader - Interrupt enabled only if corresponding bit in interrupt mask register is set. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."] +pub type INT_STATUS_MSK_R = crate::FieldReader; +#[doc = "Field `SDIO_INTERRUPT_MSK` reader - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt)."] +pub type SDIO_INTERRUPT_MSK_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Interrupt enabled only if corresponding bit in interrupt mask register is set. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."] + #[inline(always)] + pub fn int_status_msk(&self) -> INT_STATUS_MSK_R { + INT_STATUS_MSK_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:17 - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt)."] + #[inline(always)] + pub fn sdio_interrupt_msk(&self) -> SDIO_INTERRUPT_MSK_R { + SDIO_INTERRUPT_MSK_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MINTSTS") + .field( + "int_status_msk", + &format_args!("{}", self.int_status_msk().bits()), + ) + .field( + "sdio_interrupt_msk", + &format_args!("{}", self.sdio_interrupt_msk().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Masked interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mintsts::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MINTSTS_SPEC; +impl crate::RegisterSpec for MINTSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mintsts::R`](R) reader structure"] +impl crate::Readable for MINTSTS_SPEC {} +#[doc = "`reset()` method sets MINTSTS to value 0"] +impl crate::Resettable for MINTSTS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/pldmnd.rs b/esp32p4/src/sdhost/pldmnd.rs new file mode 100644 index 0000000000..abb24c4f3d --- /dev/null +++ b/esp32p4/src/sdhost/pldmnd.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PLDMND` writer"] +pub type W = crate::W; +#[doc = "Field `PD` writer - Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only ."] +pub type PD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only ."] + #[inline(always)] + #[must_use] + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Poll demand configuration register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pldmnd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PLDMND_SPEC; +impl crate::RegisterSpec for PLDMND_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`pldmnd::W`](W) writer structure"] +impl crate::Writable for PLDMND_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PLDMND to value 0"] +impl crate::Resettable for PLDMND_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/raw_ints.rs b/esp32p4/src/sdhost/raw_ints.rs new file mode 100644 index 0000000000..8468dbdde2 --- /dev/null +++ b/esp32p4/src/sdhost/raw_ints.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RAW_INTS` reader"] +pub type R = crate::R; +#[doc = "Field `RAW_INTS` reader - It indicates raw ints."] +pub type RAW_INTS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - It indicates raw ints."] + #[inline(always)] + pub fn raw_ints(&self) -> RAW_INTS_R { + RAW_INTS_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RAW_INTS") + .field("raw_ints", &format_args!("{}", self.raw_ints().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "SDIO raw ints register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_ints::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RAW_INTS_SPEC; +impl crate::RegisterSpec for RAW_INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`raw_ints::R`](R) reader structure"] +impl crate::Readable for RAW_INTS_SPEC {} +#[doc = "`reset()` method sets RAW_INTS to value 0"] +impl crate::Resettable for RAW_INTS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/resp0.rs b/esp32p4/src/sdhost/resp0.rs new file mode 100644 index 0000000000..c037dea15a --- /dev/null +++ b/esp32p4/src/sdhost/resp0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RESP0` reader"] +pub type R = crate::R; +#[doc = "Field `RESPONSE0` reader - Bit\\[31:0\\] of response."] +pub type RESPONSE0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Bit\\[31:0\\] of response."] + #[inline(always)] + pub fn response0(&self) -> RESPONSE0_R { + RESPONSE0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESP0") + .field("response0", &format_args!("{}", self.response0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESP0_SPEC; +impl crate::RegisterSpec for RESP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`resp0::R`](R) reader structure"] +impl crate::Readable for RESP0_SPEC {} +#[doc = "`reset()` method sets RESP0 to value 0"] +impl crate::Resettable for RESP0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/resp1.rs b/esp32p4/src/sdhost/resp1.rs new file mode 100644 index 0000000000..239b6595be --- /dev/null +++ b/esp32p4/src/sdhost/resp1.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RESP1` reader"] +pub type R = crate::R; +#[doc = "Field `RESPONSE1` reader - Bit\\[63:32\\] of long response."] +pub type RESPONSE1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Bit\\[63:32\\] of long response."] + #[inline(always)] + pub fn response1(&self) -> RESPONSE1_R { + RESPONSE1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESP1") + .field("response1", &format_args!("{}", self.response1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESP1_SPEC; +impl crate::RegisterSpec for RESP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`resp1::R`](R) reader structure"] +impl crate::Readable for RESP1_SPEC {} +#[doc = "`reset()` method sets RESP1 to value 0"] +impl crate::Resettable for RESP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/resp2.rs b/esp32p4/src/sdhost/resp2.rs new file mode 100644 index 0000000000..7ed9179b9d --- /dev/null +++ b/esp32p4/src/sdhost/resp2.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RESP2` reader"] +pub type R = crate::R; +#[doc = "Field `RESPONSE2` reader - Bit\\[95:64\\] of long response."] +pub type RESPONSE2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Bit\\[95:64\\] of long response."] + #[inline(always)] + pub fn response2(&self) -> RESPONSE2_R { + RESPONSE2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESP2") + .field("response2", &format_args!("{}", self.response2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESP2_SPEC; +impl crate::RegisterSpec for RESP2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`resp2::R`](R) reader structure"] +impl crate::Readable for RESP2_SPEC {} +#[doc = "`reset()` method sets RESP2 to value 0"] +impl crate::Resettable for RESP2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/resp3.rs b/esp32p4/src/sdhost/resp3.rs new file mode 100644 index 0000000000..1ce0b8a3bc --- /dev/null +++ b/esp32p4/src/sdhost/resp3.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RESP3` reader"] +pub type R = crate::R; +#[doc = "Field `RESPONSE3` reader - Bit\\[127:96\\] of long response."] +pub type RESPONSE3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Bit\\[127:96\\] of long response."] + #[inline(always)] + pub fn response3(&self) -> RESPONSE3_R { + RESPONSE3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESP3") + .field("response3", &format_args!("{}", self.response3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESP3_SPEC; +impl crate::RegisterSpec for RESP3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`resp3::R`](R) reader structure"] +impl crate::Readable for RESP3_SPEC {} +#[doc = "`reset()` method sets RESP3 to value 0"] +impl crate::Resettable for RESP3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/rintsts.rs b/esp32p4/src/sdhost/rintsts.rs new file mode 100644 index 0000000000..f595205c85 --- /dev/null +++ b/esp32p4/src/sdhost/rintsts.rs @@ -0,0 +1,85 @@ +#[doc = "Register `RINTSTS` reader"] +pub type R = crate::R; +#[doc = "Register `RINTSTS` writer"] +pub type W = crate::W; +#[doc = "Field `INT_STATUS_RAW` reader - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."] +pub type INT_STATUS_RAW_R = crate::FieldReader; +#[doc = "Field `INT_STATUS_RAW` writer - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."] +pub type INT_STATUS_RAW_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SDIO_INTERRUPT_RAW` reader - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card."] +pub type SDIO_INTERRUPT_RAW_R = crate::FieldReader; +#[doc = "Field `SDIO_INTERRUPT_RAW` writer - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card."] +pub type SDIO_INTERRUPT_RAW_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:15 - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."] + #[inline(always)] + pub fn int_status_raw(&self) -> INT_STATUS_RAW_R { + INT_STATUS_RAW_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:17 - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card."] + #[inline(always)] + pub fn sdio_interrupt_raw(&self) -> SDIO_INTERRUPT_RAW_R { + SDIO_INTERRUPT_RAW_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RINTSTS") + .field( + "int_status_raw", + &format_args!("{}", self.int_status_raw().bits()), + ) + .field( + "sdio_interrupt_raw", + &format_args!("{}", self.sdio_interrupt_raw().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."] + #[inline(always)] + #[must_use] + pub fn int_status_raw(&mut self) -> INT_STATUS_RAW_W { + INT_STATUS_RAW_W::new(self, 0) + } + #[doc = "Bits 16:17 - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card."] + #[inline(always)] + #[must_use] + pub fn sdio_interrupt_raw(&mut self) -> SDIO_INTERRUPT_RAW_W { + SDIO_INTERRUPT_RAW_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Raw interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rintsts::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rintsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RINTSTS_SPEC; +impl crate::RegisterSpec for RINTSTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rintsts::R`](R) reader structure"] +impl crate::Readable for RINTSTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rintsts::W`](W) writer structure"] +impl crate::Writable for RINTSTS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RINTSTS to value 0"] +impl crate::Resettable for RINTSTS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/rst_n.rs b/esp32p4/src/sdhost/rst_n.rs new file mode 100644 index 0000000000..068f2ce8f2 --- /dev/null +++ b/esp32p4/src/sdhost/rst_n.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RST_N` reader"] +pub type R = crate::R; +#[doc = "Register `RST_N` writer"] +pub type W = crate::W; +#[doc = "Field `CARD_RESET` reader - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."] +pub type CARD_RESET_R = crate::FieldReader; +#[doc = "Field `CARD_RESET` writer - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."] +pub type CARD_RESET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."] + #[inline(always)] + pub fn card_reset(&self) -> CARD_RESET_R { + CARD_RESET_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RST_N") + .field("card_reset", &format_args!("{}", self.card_reset().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."] + #[inline(always)] + #[must_use] + pub fn card_reset(&mut self) -> CARD_RESET_W { + CARD_RESET_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Card reset register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_n::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_n::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RST_N_SPEC; +impl crate::RegisterSpec for RST_N_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rst_n::R`](R) reader structure"] +impl crate::Readable for RST_N_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rst_n::W`](W) writer structure"] +impl crate::Writable for RST_N_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RST_N to value 0x01"] +impl crate::Resettable for RST_N_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/sdhost/status.rs b/esp32p4/src/sdhost/status.rs new file mode 100644 index 0000000000..e6fa3f2c60 --- /dev/null +++ b/esp32p4/src/sdhost/status.rs @@ -0,0 +1,126 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_RX_WATERMARK` reader - FIFO reached Receive watermark level, not qualified with data transfer."] +pub type FIFO_RX_WATERMARK_R = crate::BitReader; +#[doc = "Field `FIFO_TX_WATERMARK` reader - FIFO reached Transmit watermark level, not qualified with data transfer."] +pub type FIFO_TX_WATERMARK_R = crate::BitReader; +#[doc = "Field `FIFO_EMPTY` reader - FIFO is empty status."] +pub type FIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `FIFO_FULL` reader - FIFO is full status."] +pub type FIFO_FULL_R = crate::BitReader; +#[doc = "Field `COMMAND_FSM_STATES` reader - Command FSM states. 0: Idle; 1: Send init sequence; 2: Send cmd start bit; 3: Send cmd tx bit; 4: Send cmd index + arg; 5: Send cmd crc7; 6: Send cmd end bit; 7: Receive resp start bit; 8: Receive resp IRQ response; 9: Receive resp tx bit; 10: Receive resp cmd idx; 11: Receive resp data; 12: Receive resp crc7; 13: Receive resp end bit; 14: Cmd path wait NCC; 15: Wait, cmd-to-response turnaround."] +pub type COMMAND_FSM_STATES_R = crate::FieldReader; +#[doc = "Field `DATA_3_STATUS` reader - Raw selected sdhost_card_data\\[3\\], checks whether card is present. 0: card not present; 1: card present."] +pub type DATA_3_STATUS_R = crate::BitReader; +#[doc = "Field `DATA_BUSY` reader - Inverted version of raw selected sdhost_card_data\\[0\\]. 0: Card data not busy; 1: Card data busy."] +pub type DATA_BUSY_R = crate::BitReader; +#[doc = "Field `DATA_STATE_MC_BUSY` reader - Data transmit or receive state-machine is busy."] +pub type DATA_STATE_MC_BUSY_R = crate::BitReader; +#[doc = "Field `RESPONSE_INDEX` reader - Index of previous response, including any auto-stop sent by core."] +pub type RESPONSE_INDEX_R = crate::FieldReader; +#[doc = "Field `FIFO_COUNT` reader - FIFO count, number of filled locations in FIFO."] +pub type FIFO_COUNT_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - FIFO reached Receive watermark level, not qualified with data transfer."] + #[inline(always)] + pub fn fifo_rx_watermark(&self) -> FIFO_RX_WATERMARK_R { + FIFO_RX_WATERMARK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - FIFO reached Transmit watermark level, not qualified with data transfer."] + #[inline(always)] + pub fn fifo_tx_watermark(&self) -> FIFO_TX_WATERMARK_R { + FIFO_TX_WATERMARK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FIFO is empty status."] + #[inline(always)] + pub fn fifo_empty(&self) -> FIFO_EMPTY_R { + FIFO_EMPTY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - FIFO is full status."] + #[inline(always)] + pub fn fifo_full(&self) -> FIFO_FULL_R { + FIFO_FULL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - Command FSM states. 0: Idle; 1: Send init sequence; 2: Send cmd start bit; 3: Send cmd tx bit; 4: Send cmd index + arg; 5: Send cmd crc7; 6: Send cmd end bit; 7: Receive resp start bit; 8: Receive resp IRQ response; 9: Receive resp tx bit; 10: Receive resp cmd idx; 11: Receive resp data; 12: Receive resp crc7; 13: Receive resp end bit; 14: Cmd path wait NCC; 15: Wait, cmd-to-response turnaround."] + #[inline(always)] + pub fn command_fsm_states(&self) -> COMMAND_FSM_STATES_R { + COMMAND_FSM_STATES_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8 - Raw selected sdhost_card_data\\[3\\], checks whether card is present. 0: card not present; 1: card present."] + #[inline(always)] + pub fn data_3_status(&self) -> DATA_3_STATUS_R { + DATA_3_STATUS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Inverted version of raw selected sdhost_card_data\\[0\\]. 0: Card data not busy; 1: Card data busy."] + #[inline(always)] + pub fn data_busy(&self) -> DATA_BUSY_R { + DATA_BUSY_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Data transmit or receive state-machine is busy."] + #[inline(always)] + pub fn data_state_mc_busy(&self) -> DATA_STATE_MC_BUSY_R { + DATA_STATE_MC_BUSY_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 11:16 - Index of previous response, including any auto-stop sent by core."] + #[inline(always)] + pub fn response_index(&self) -> RESPONSE_INDEX_R { + RESPONSE_INDEX_R::new(((self.bits >> 11) & 0x3f) as u8) + } + #[doc = "Bits 17:29 - FIFO count, number of filled locations in FIFO."] + #[inline(always)] + pub fn fifo_count(&self) -> FIFO_COUNT_R { + FIFO_COUNT_R::new(((self.bits >> 17) & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field( + "fifo_rx_watermark", + &format_args!("{}", self.fifo_rx_watermark().bit()), + ) + .field( + "fifo_tx_watermark", + &format_args!("{}", self.fifo_tx_watermark().bit()), + ) + .field("fifo_empty", &format_args!("{}", self.fifo_empty().bit())) + .field("fifo_full", &format_args!("{}", self.fifo_full().bit())) + .field( + "command_fsm_states", + &format_args!("{}", self.command_fsm_states().bits()), + ) + .field( + "data_3_status", + &format_args!("{}", self.data_3_status().bit()), + ) + .field("data_busy", &format_args!("{}", self.data_busy().bit())) + .field( + "data_state_mc_busy", + &format_args!("{}", self.data_state_mc_busy().bit()), + ) + .field( + "response_index", + &format_args!("{}", self.response_index().bits()), + ) + .field("fifo_count", &format_args!("{}", self.fifo_count().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "SD/MMC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`reset()` method sets STATUS to value 0x0716"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x0716; +} diff --git a/esp32p4/src/sdhost/tbbcnt.rs b/esp32p4/src/sdhost/tbbcnt.rs new file mode 100644 index 0000000000..2f6bd8bd3e --- /dev/null +++ b/esp32p4/src/sdhost/tbbcnt.rs @@ -0,0 +1,36 @@ +#[doc = "Register `TBBCNT` reader"] +pub type R = crate::R; +#[doc = "Field `TBBCNT` reader - Number of bytes transferred between Host/DMA memory and BIU FIFO."] +pub type TBBCNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of bytes transferred between Host/DMA memory and BIU FIFO."] + #[inline(always)] + pub fn tbbcnt(&self) -> TBBCNT_R { + TBBCNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TBBCNT") + .field("tbbcnt", &format_args!("{}", self.tbbcnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Transferred byte count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbbcnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TBBCNT_SPEC; +impl crate::RegisterSpec for TBBCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tbbcnt::R`](R) reader structure"] +impl crate::Readable for TBBCNT_SPEC {} +#[doc = "`reset()` method sets TBBCNT to value 0"] +impl crate::Resettable for TBBCNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/tcbcnt.rs b/esp32p4/src/sdhost/tcbcnt.rs new file mode 100644 index 0000000000..3ad2d15371 --- /dev/null +++ b/esp32p4/src/sdhost/tcbcnt.rs @@ -0,0 +1,36 @@ +#[doc = "Register `TCBCNT` reader"] +pub type R = crate::R; +#[doc = "Field `TCBCNT` reader - Number of bytes transferred by CIU unit to card."] +pub type TCBCNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of bytes transferred by CIU unit to card."] + #[inline(always)] + pub fn tcbcnt(&self) -> TCBCNT_R { + TCBCNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCBCNT") + .field("tcbcnt", &format_args!("{}", self.tcbcnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Transferred byte count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcbcnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TCBCNT_SPEC; +impl crate::RegisterSpec for TCBCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tcbcnt::R`](R) reader structure"] +impl crate::Readable for TCBCNT_SPEC {} +#[doc = "`reset()` method sets TCBCNT to value 0"] +impl crate::Resettable for TCBCNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/tmout.rs b/esp32p4/src/sdhost/tmout.rs new file mode 100644 index 0000000000..88b7d3bcd8 --- /dev/null +++ b/esp32p4/src/sdhost/tmout.rs @@ -0,0 +1,85 @@ +#[doc = "Register `TMOUT` reader"] +pub type R = crate::R; +#[doc = "Register `TMOUT` writer"] +pub type W = crate::W; +#[doc = "Field `RESPONSE_TIMEOUT` reader - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."] +pub type RESPONSE_TIMEOUT_R = crate::FieldReader; +#[doc = "Field `RESPONSE_TIMEOUT` writer - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."] +pub type RESPONSE_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DATA_TIMEOUT` reader - Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled."] +pub type DATA_TIMEOUT_R = crate::FieldReader; +#[doc = "Field `DATA_TIMEOUT` writer - Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled."] +pub type DATA_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:7 - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."] + #[inline(always)] + pub fn response_timeout(&self) -> RESPONSE_TIMEOUT_R { + RESPONSE_TIMEOUT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:31 - Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled."] + #[inline(always)] + pub fn data_timeout(&self) -> DATA_TIMEOUT_R { + DATA_TIMEOUT_R::new((self.bits >> 8) & 0x00ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TMOUT") + .field( + "response_timeout", + &format_args!("{}", self.response_timeout().bits()), + ) + .field( + "data_timeout", + &format_args!("{}", self.data_timeout().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."] + #[inline(always)] + #[must_use] + pub fn response_timeout(&mut self) -> RESPONSE_TIMEOUT_W { + RESPONSE_TIMEOUT_W::new(self, 0) + } + #[doc = "Bits 8:31 - Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled."] + #[inline(always)] + #[must_use] + pub fn data_timeout(&mut self) -> DATA_TIMEOUT_W { + DATA_TIMEOUT_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data and response timeout configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmout::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TMOUT_SPEC; +impl crate::RegisterSpec for TMOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmout::R`](R) reader structure"] +impl crate::Readable for TMOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tmout::W`](W) writer structure"] +impl crate::Writable for TMOUT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TMOUT to value 0xffff_ff40"] +impl crate::Resettable for TMOUT_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ff40; +} diff --git a/esp32p4/src/sdhost/uhs.rs b/esp32p4/src/sdhost/uhs.rs new file mode 100644 index 0000000000..984023d320 --- /dev/null +++ b/esp32p4/src/sdhost/uhs.rs @@ -0,0 +1,63 @@ +#[doc = "Register `UHS` reader"] +pub type R = crate::R; +#[doc = "Register `UHS` writer"] +pub type W = crate::W; +#[doc = "Field `DDR` reader - DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe."] +pub type DDR_R = crate::FieldReader; +#[doc = "Field `DDR` writer - DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe."] +pub type DDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 16:17 - DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe."] + #[inline(always)] + pub fn ddr(&self) -> DDR_R { + DDR_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UHS") + .field("ddr", &format_args!("{}", self.ddr().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:17 - DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe."] + #[inline(always)] + #[must_use] + pub fn ddr(&mut self) -> DDR_W { + DDR_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHS-1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uhs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uhs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UHS_SPEC; +impl crate::RegisterSpec for UHS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uhs::R`](R) reader structure"] +impl crate::Readable for UHS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uhs::W`](W) writer structure"] +impl crate::Writable for UHS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UHS to value 0"] +impl crate::Resettable for UHS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/usrid.rs b/esp32p4/src/sdhost/usrid.rs new file mode 100644 index 0000000000..1a3c71f3ba --- /dev/null +++ b/esp32p4/src/sdhost/usrid.rs @@ -0,0 +1,63 @@ +#[doc = "Register `USRID` reader"] +pub type R = crate::R; +#[doc = "Register `USRID` writer"] +pub type W = crate::W; +#[doc = "Field `USRID` reader - User identification register, value set by user. Can also be used as a scratchpad register by user."] +pub type USRID_R = crate::FieldReader; +#[doc = "Field `USRID` writer - User identification register, value set by user. Can also be used as a scratchpad register by user."] +pub type USRID_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - User identification register, value set by user. Can also be used as a scratchpad register by user."] + #[inline(always)] + pub fn usrid(&self) -> USRID_R { + USRID_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USRID") + .field("usrid", &format_args!("{}", self.usrid().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - User identification register, value set by user. Can also be used as a scratchpad register by user."] + #[inline(always)] + #[must_use] + pub fn usrid(&mut self) -> USRID_W { + USRID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "User ID (scratchpad) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usrid::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usrid::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USRID_SPEC; +impl crate::RegisterSpec for USRID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usrid::R`](R) reader structure"] +impl crate::Readable for USRID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usrid::W`](W) writer structure"] +impl crate::Writable for USRID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USRID to value 0"] +impl crate::Resettable for USRID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sdhost/verid.rs b/esp32p4/src/sdhost/verid.rs new file mode 100644 index 0000000000..13996b85a5 --- /dev/null +++ b/esp32p4/src/sdhost/verid.rs @@ -0,0 +1,36 @@ +#[doc = "Register `VERID` reader"] +pub type R = crate::R; +#[doc = "Field `VERSIONID` reader - Hardware version register. Can also be read by fireware."] +pub type VERSIONID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Hardware version register. Can also be read by fireware."] + #[inline(always)] + pub fn versionid(&self) -> VERSIONID_R { + VERSIONID_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("VERID") + .field("versionid", &format_args!("{}", self.versionid().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Version ID (scratchpad) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VERID_SPEC; +impl crate::RegisterSpec for VERID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`verid::R`](R) reader structure"] +impl crate::Readable for VERID_SPEC {} +#[doc = "`reset()` method sets VERID to value 0x5432_270a"] +impl crate::Resettable for VERID_SPEC { + const RESET_VALUE: Self::Ux = 0x5432_270a; +} diff --git a/esp32p4/src/sdhost/wrtprt.rs b/esp32p4/src/sdhost/wrtprt.rs new file mode 100644 index 0000000000..7f61753d84 --- /dev/null +++ b/esp32p4/src/sdhost/wrtprt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `WRTPRT` reader"] +pub type R = crate::R; +#[doc = "Field `WRITE_PROTECT` reader - Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented."] +pub type WRITE_PROTECT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented."] + #[inline(always)] + pub fn write_protect(&self) -> WRITE_PROTECT_R { + WRITE_PROTECT_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WRTPRT") + .field( + "write_protect", + &format_args!("{}", self.write_protect().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Card write protection (WP) status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wrtprt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WRTPRT_SPEC; +impl crate::RegisterSpec for WRTPRT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wrtprt::R`](R) reader structure"] +impl crate::Readable for WRTPRT_SPEC {} +#[doc = "`reset()` method sets WRTPRT to value 0"] +impl crate::Resettable for WRTPRT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha.rs b/esp32p4/src/sha.rs new file mode 100644 index 0000000000..0241fe9cff --- /dev/null +++ b/esp32p4/src/sha.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + mode: MODE, + t_string: T_STRING, + t_length: T_LENGTH, + dma_block_num: DMA_BLOCK_NUM, + start: START, + continue_: CONTINUE, + busy: BUSY, + dma_start: DMA_START, + dma_continue: DMA_CONTINUE, + clear_irq: CLEAR_IRQ, + irq_ena: IRQ_ENA, + date: DATE, + _reserved12: [u8; 0x10], + h_mem: [H_MEM; 64], + m_mem: [M_MEM; 64], +} +impl RegisterBlock { + #[doc = "0x00 - Initial configuration register."] + #[inline(always)] + pub const fn mode(&self) -> &MODE { + &self.mode + } + #[doc = "0x04 - SHA 512/t configuration register 0."] + #[inline(always)] + pub const fn t_string(&self) -> &T_STRING { + &self.t_string + } + #[doc = "0x08 - SHA 512/t configuration register 1."] + #[inline(always)] + pub const fn t_length(&self) -> &T_LENGTH { + &self.t_length + } + #[doc = "0x0c - DMA configuration register 0."] + #[inline(always)] + pub const fn dma_block_num(&self) -> &DMA_BLOCK_NUM { + &self.dma_block_num + } + #[doc = "0x10 - Typical SHA configuration register 0."] + #[inline(always)] + pub const fn start(&self) -> &START { + &self.start + } + #[doc = "0x14 - Typical SHA configuration register 1."] + #[inline(always)] + pub const fn continue_(&self) -> &CONTINUE { + &self.continue_ + } + #[doc = "0x18 - Busy register."] + #[inline(always)] + pub const fn busy(&self) -> &BUSY { + &self.busy + } + #[doc = "0x1c - DMA configuration register 1."] + #[inline(always)] + pub const fn dma_start(&self) -> &DMA_START { + &self.dma_start + } + #[doc = "0x20 - DMA configuration register 2."] + #[inline(always)] + pub const fn dma_continue(&self) -> &DMA_CONTINUE { + &self.dma_continue + } + #[doc = "0x24 - Interrupt clear register."] + #[inline(always)] + pub const fn clear_irq(&self) -> &CLEAR_IRQ { + &self.clear_irq + } + #[doc = "0x28 - Interrupt enable register."] + #[inline(always)] + pub const fn irq_ena(&self) -> &IRQ_ENA { + &self.irq_ena + } + #[doc = "0x2c - Date register."] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } + #[doc = "0x40..0x80 - Sha H memory which contains intermediate hash or finial hash."] + #[inline(always)] + pub const fn h_mem(&self, n: usize) -> &H_MEM { + &self.h_mem[n] + } + #[doc = "0x80..0xc0 - Sha M memory which contains message."] + #[inline(always)] + pub const fn m_mem(&self, n: usize) -> &M_MEM { + &self.m_mem[n] + } +} +#[doc = "MODE (rw) register accessor: Initial configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`] module"] +pub type MODE = crate::Reg; +#[doc = "Initial configuration register."] +pub mod mode; +#[doc = "T_STRING (rw) register accessor: SHA 512/t configuration register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t_string::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t_string::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t_string`] module"] +pub type T_STRING = crate::Reg; +#[doc = "SHA 512/t configuration register 0."] +pub mod t_string; +#[doc = "T_LENGTH (rw) register accessor: SHA 512/t configuration register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t_length::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t_length::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t_length`] module"] +pub type T_LENGTH = crate::Reg; +#[doc = "SHA 512/t configuration register 1."] +pub mod t_length; +#[doc = "DMA_BLOCK_NUM (rw) register accessor: DMA configuration register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_block_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_block_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_block_num`] module"] +pub type DMA_BLOCK_NUM = crate::Reg; +#[doc = "DMA configuration register 0."] +pub mod dma_block_num; +#[doc = "START (r) register accessor: Typical SHA configuration register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`start::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@start`] module"] +pub type START = crate::Reg; +#[doc = "Typical SHA configuration register 0."] +pub mod start; +#[doc = "CONTINUE (r) register accessor: Typical SHA configuration register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`continue_::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@continue_`] module"] +pub type CONTINUE = crate::Reg; +#[doc = "Typical SHA configuration register 1."] +pub mod continue_; +#[doc = "BUSY (r) register accessor: Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`busy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@busy`] module"] +pub type BUSY = crate::Reg; +#[doc = "Busy register."] +pub mod busy; +#[doc = "DMA_START (w) register accessor: DMA configuration register 1.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_start::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_start`] module"] +pub type DMA_START = crate::Reg; +#[doc = "DMA configuration register 1."] +pub mod dma_start; +#[doc = "DMA_CONTINUE (w) register accessor: DMA configuration register 2.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_continue::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_continue`] module"] +pub type DMA_CONTINUE = crate::Reg; +#[doc = "DMA configuration register 2."] +pub mod dma_continue; +#[doc = "CLEAR_IRQ (w) register accessor: Interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear_irq::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear_irq`] module"] +pub type CLEAR_IRQ = crate::Reg; +#[doc = "Interrupt clear register."] +pub mod clear_irq; +#[doc = "IRQ_ENA (rw) register accessor: Interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_ena`] module"] +pub type IRQ_ENA = crate::Reg; +#[doc = "Interrupt enable register."] +pub mod irq_ena; +#[doc = "DATE (rw) register accessor: Date register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Date register."] +pub mod date; +#[doc = "H_MEM (rw) register accessor: Sha H memory which contains intermediate hash or finial hash.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h_mem`] module"] +pub type H_MEM = crate::Reg; +#[doc = "Sha H memory which contains intermediate hash or finial hash."] +pub mod h_mem; +#[doc = "M_MEM (rw) register accessor: Sha M memory which contains message.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@m_mem`] module"] +pub type M_MEM = crate::Reg; +#[doc = "Sha M memory which contains message."] +pub mod m_mem; diff --git a/esp32p4/src/sha/busy.rs b/esp32p4/src/sha/busy.rs new file mode 100644 index 0000000000..9af2af58a7 --- /dev/null +++ b/esp32p4/src/sha/busy.rs @@ -0,0 +1,36 @@ +#[doc = "Register `BUSY` reader"] +pub type R = crate::R; +#[doc = "Field `STATE` reader - Sha busy state. 1'b0: idle. 1'b1: busy."] +pub type STATE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Sha busy state. 1'b0: idle. 1'b1: busy."] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUSY") + .field("state", &format_args!("{}", self.state().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`busy::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUSY_SPEC; +impl crate::RegisterSpec for BUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`busy::R`](R) reader structure"] +impl crate::Readable for BUSY_SPEC {} +#[doc = "`reset()` method sets BUSY to value 0"] +impl crate::Resettable for BUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/clear_irq.rs b/esp32p4/src/sha/clear_irq.rs new file mode 100644 index 0000000000..746b5a4055 --- /dev/null +++ b/esp32p4/src/sha/clear_irq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CLEAR_IRQ` writer"] +pub type W = crate::W; +#[doc = "Field `CLEAR_INTERRUPT` writer - Clear sha interrupt."] +pub type CLEAR_INTERRUPT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Clear sha interrupt."] + #[inline(always)] + #[must_use] + pub fn clear_interrupt(&mut self) -> CLEAR_INTERRUPT_W { + CLEAR_INTERRUPT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear_irq::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLEAR_IRQ_SPEC; +impl crate::RegisterSpec for CLEAR_IRQ_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`clear_irq::W`](W) writer structure"] +impl crate::Writable for CLEAR_IRQ_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLEAR_IRQ to value 0"] +impl crate::Resettable for CLEAR_IRQ_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/continue_.rs b/esp32p4/src/sha/continue_.rs new file mode 100644 index 0000000000..ce3c67b1f3 --- /dev/null +++ b/esp32p4/src/sha/continue_.rs @@ -0,0 +1,36 @@ +#[doc = "Register `CONTINUE` reader"] +pub type R = crate::R; +#[doc = "Field `CONTINUE` reader - Reserved."] +pub type CONTINUE_R = crate::FieldReader; +impl R { + #[doc = "Bits 1:31 - Reserved."] + #[inline(always)] + pub fn continue_(&self) -> CONTINUE_R { + CONTINUE_R::new((self.bits >> 1) & 0x7fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONTINUE") + .field("continue_", &format_args!("{}", self.continue_().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Typical SHA configuration register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`continue_::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONTINUE_SPEC; +impl crate::RegisterSpec for CONTINUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`continue_::R`](R) reader structure"] +impl crate::Readable for CONTINUE_SPEC {} +#[doc = "`reset()` method sets CONTINUE to value 0"] +impl crate::Resettable for CONTINUE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/date.rs b/esp32p4/src/sha/date.rs new file mode 100644 index 0000000000..b9eae3e321 --- /dev/null +++ b/esp32p4/src/sha/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - Sha date information/ sha version information."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - Sha date information/ sha version information."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 0:29 - Sha date information/ sha version information."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x3fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:29 - Sha date information/ sha version information."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Date register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x2020_1229"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2020_1229; +} diff --git a/esp32p4/src/sha/dma_block_num.rs b/esp32p4/src/sha/dma_block_num.rs new file mode 100644 index 0000000000..cf3545861d --- /dev/null +++ b/esp32p4/src/sha/dma_block_num.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DMA_BLOCK_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_BLOCK_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_BLOCK_NUM` reader - Dma-sha block number."] +pub type DMA_BLOCK_NUM_R = crate::FieldReader; +#[doc = "Field `DMA_BLOCK_NUM` writer - Dma-sha block number."] +pub type DMA_BLOCK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Dma-sha block number."] + #[inline(always)] + pub fn dma_block_num(&self) -> DMA_BLOCK_NUM_R { + DMA_BLOCK_NUM_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA_BLOCK_NUM") + .field( + "dma_block_num", + &format_args!("{}", self.dma_block_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - Dma-sha block number."] + #[inline(always)] + #[must_use] + pub fn dma_block_num(&mut self) -> DMA_BLOCK_NUM_W { + DMA_BLOCK_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DMA configuration register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_block_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_block_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_BLOCK_NUM_SPEC; +impl crate::RegisterSpec for DMA_BLOCK_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_block_num::R`](R) reader structure"] +impl crate::Readable for DMA_BLOCK_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_block_num::W`](W) writer structure"] +impl crate::Writable for DMA_BLOCK_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_BLOCK_NUM to value 0"] +impl crate::Resettable for DMA_BLOCK_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/dma_continue.rs b/esp32p4/src/sha/dma_continue.rs new file mode 100644 index 0000000000..2daf6d1a04 --- /dev/null +++ b/esp32p4/src/sha/dma_continue.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DMA_CONTINUE` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_CONTINUE` writer - Continue dma-sha."] +pub type DMA_CONTINUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Continue dma-sha."] + #[inline(always)] + #[must_use] + pub fn dma_continue(&mut self) -> DMA_CONTINUE_W { + DMA_CONTINUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DMA configuration register 2.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_continue::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_CONTINUE_SPEC; +impl crate::RegisterSpec for DMA_CONTINUE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`dma_continue::W`](W) writer structure"] +impl crate::Writable for DMA_CONTINUE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_CONTINUE to value 0"] +impl crate::Resettable for DMA_CONTINUE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/dma_start.rs b/esp32p4/src/sha/dma_start.rs new file mode 100644 index 0000000000..1ce63d262c --- /dev/null +++ b/esp32p4/src/sha/dma_start.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DMA_START` writer"] +pub type W = crate::W; +#[doc = "Field `DMA_START` writer - Start dma-sha."] +pub type DMA_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Start dma-sha."] + #[inline(always)] + #[must_use] + pub fn dma_start(&mut self) -> DMA_START_W { + DMA_START_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "DMA configuration register 1.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_start::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_START_SPEC; +impl crate::RegisterSpec for DMA_START_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`dma_start::W`](W) writer structure"] +impl crate::Writable for DMA_START_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DMA_START to value 0"] +impl crate::Resettable for DMA_START_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/h_mem.rs b/esp32p4/src/sha/h_mem.rs new file mode 100644 index 0000000000..15c6ad0243 --- /dev/null +++ b/esp32p4/src/sha/h_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `H_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `H_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Sha H memory which contains intermediate hash or finial hash.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct H_MEM_SPEC; +impl crate::RegisterSpec for H_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`h_mem::R`](R) reader structure"] +impl crate::Readable for H_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`h_mem::W`](W) writer structure"] +impl crate::Writable for H_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets H_MEM[%s] to value 0"] +impl crate::Resettable for H_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/irq_ena.rs b/esp32p4/src/sha/irq_ena.rs new file mode 100644 index 0000000000..4d3cc44a92 --- /dev/null +++ b/esp32p4/src/sha/irq_ena.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IRQ_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `INTERRUPT_ENA` reader - Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable."] +pub type INTERRUPT_ENA_R = crate::BitReader; +#[doc = "Field `INTERRUPT_ENA` writer - Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable."] +pub type INTERRUPT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable."] + #[inline(always)] + pub fn interrupt_ena(&self) -> INTERRUPT_ENA_R { + INTERRUPT_ENA_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IRQ_ENA") + .field( + "interrupt_ena", + &format_args!("{}", self.interrupt_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable."] + #[inline(always)] + #[must_use] + pub fn interrupt_ena(&mut self) -> INTERRUPT_ENA_W { + INTERRUPT_ENA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ_ENA_SPEC; +impl crate::RegisterSpec for IRQ_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_ena::R`](R) reader structure"] +impl crate::Readable for IRQ_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq_ena::W`](W) writer structure"] +impl crate::Writable for IRQ_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IRQ_ENA to value 0"] +impl crate::Resettable for IRQ_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/m_mem.rs b/esp32p4/src/sha/m_mem.rs new file mode 100644 index 0000000000..a874ab77f2 --- /dev/null +++ b/esp32p4/src/sha/m_mem.rs @@ -0,0 +1,44 @@ +#[doc = "Register `M_MEM[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `M_MEM[%s]` writer"] +pub type W = crate::W; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Sha M memory which contains message.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M_MEM_SPEC; +impl crate::RegisterSpec for M_MEM_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [`m_mem::R`](R) reader structure"] +impl crate::Readable for M_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m_mem::W`](W) writer structure"] +impl crate::Writable for M_MEM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets M_MEM[%s] to value 0"] +impl crate::Resettable for M_MEM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/mode.rs b/esp32p4/src/sha/mode.rs new file mode 100644 index 0000000000..25f3cc64ab --- /dev/null +++ b/esp32p4/src/sha/mode.rs @@ -0,0 +1,63 @@ +#[doc = "Register `MODE` reader"] +pub type R = crate::R; +#[doc = "Register `MODE` writer"] +pub type W = crate::W; +#[doc = "Field `MODE` reader - Sha mode."] +pub type MODE_R = crate::FieldReader; +#[doc = "Field `MODE` writer - Sha mode."] +pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - Sha mode."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MODE") + .field("mode", &format_args!("{}", self.mode().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Sha mode."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Initial configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MODE_SPEC; +impl crate::RegisterSpec for MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mode::R`](R) reader structure"] +impl crate::Readable for MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"] +impl crate::Writable for MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MODE to value 0"] +impl crate::Resettable for MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/start.rs b/esp32p4/src/sha/start.rs new file mode 100644 index 0000000000..ef875dbc53 --- /dev/null +++ b/esp32p4/src/sha/start.rs @@ -0,0 +1,36 @@ +#[doc = "Register `START` reader"] +pub type R = crate::R; +#[doc = "Field `START` reader - Reserved."] +pub type START_R = crate::FieldReader; +impl R { + #[doc = "Bits 1:31 - Reserved."] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new((self.bits >> 1) & 0x7fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("START") + .field("start", &format_args!("{}", self.start().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Typical SHA configuration register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`start::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct START_SPEC; +impl crate::RegisterSpec for START_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`start::R`](R) reader structure"] +impl crate::Readable for START_SPEC {} +#[doc = "`reset()` method sets START to value 0"] +impl crate::Resettable for START_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/t_length.rs b/esp32p4/src/sha/t_length.rs new file mode 100644 index 0000000000..48b41bf35f --- /dev/null +++ b/esp32p4/src/sha/t_length.rs @@ -0,0 +1,63 @@ +#[doc = "Register `T_LENGTH` reader"] +pub type R = crate::R; +#[doc = "Register `T_LENGTH` writer"] +pub type W = crate::W; +#[doc = "Field `T_LENGTH` reader - Sha t_length (used if and only if mode == SHA_512/t)."] +pub type T_LENGTH_R = crate::FieldReader; +#[doc = "Field `T_LENGTH` writer - Sha t_length (used if and only if mode == SHA_512/t)."] +pub type T_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Sha t_length (used if and only if mode == SHA_512/t)."] + #[inline(always)] + pub fn t_length(&self) -> T_LENGTH_R { + T_LENGTH_R::new((self.bits & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T_LENGTH") + .field("t_length", &format_args!("{}", self.t_length().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - Sha t_length (used if and only if mode == SHA_512/t)."] + #[inline(always)] + #[must_use] + pub fn t_length(&mut self) -> T_LENGTH_W { + T_LENGTH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SHA 512/t configuration register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t_length::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t_length::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T_LENGTH_SPEC; +impl crate::RegisterSpec for T_LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t_length::R`](R) reader structure"] +impl crate::Readable for T_LENGTH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`t_length::W`](W) writer structure"] +impl crate::Writable for T_LENGTH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets T_LENGTH to value 0"] +impl crate::Resettable for T_LENGTH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/sha/t_string.rs b/esp32p4/src/sha/t_string.rs new file mode 100644 index 0000000000..7e9625df9c --- /dev/null +++ b/esp32p4/src/sha/t_string.rs @@ -0,0 +1,63 @@ +#[doc = "Register `T_STRING` reader"] +pub type R = crate::R; +#[doc = "Register `T_STRING` writer"] +pub type W = crate::W; +#[doc = "Field `T_STRING` reader - Sha t_string (used if and only if mode == SHA_512/t)."] +pub type T_STRING_R = crate::FieldReader; +#[doc = "Field `T_STRING` writer - Sha t_string (used if and only if mode == SHA_512/t)."] +pub type T_STRING_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Sha t_string (used if and only if mode == SHA_512/t)."] + #[inline(always)] + pub fn t_string(&self) -> T_STRING_R { + T_STRING_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T_STRING") + .field("t_string", &format_args!("{}", self.t_string().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Sha t_string (used if and only if mode == SHA_512/t)."] + #[inline(always)] + #[must_use] + pub fn t_string(&mut self) -> T_STRING_W { + T_STRING_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SHA 512/t configuration register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t_string::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t_string::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T_STRING_SPEC; +impl crate::RegisterSpec for T_STRING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t_string::R`](R) reader structure"] +impl crate::Readable for T_STRING_SPEC {} +#[doc = "`write(|w| ..)` method takes [`t_string::W`](W) writer structure"] +impl crate::Writable for T_STRING_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets T_STRING to value 0"] +impl crate::Resettable for T_STRING_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm.rs b/esp32p4/src/soc_etm.rs new file mode 100644 index 0000000000..ca1d296df9 --- /dev/null +++ b/esp32p4/src/soc_etm.rs @@ -0,0 +1,1387 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + ch_ena_ad0: CH_ENA_AD0, + ch_ena_ad0_set: CH_ENA_AD0_SET, + ch_ena_ad0_clr: CH_ENA_AD0_CLR, + ch_ena_ad1: CH_ENA_AD1, + ch_ena_ad1_set: CH_ENA_AD1_SET, + ch_ena_ad1_clr: CH_ENA_AD1_CLR, + ch0_evt_id: CH0_EVT_ID, + ch0_task_id: CH0_TASK_ID, + ch1_evt_id: CH1_EVT_ID, + ch1_task_id: CH1_TASK_ID, + ch2_evt_id: CH2_EVT_ID, + ch2_task_id: CH2_TASK_ID, + ch3_evt_id: CH3_EVT_ID, + ch3_task_id: CH3_TASK_ID, + ch4_evt_id: CH4_EVT_ID, + ch4_task_id: CH4_TASK_ID, + ch5_evt_id: CH5_EVT_ID, + ch5_task_id: CH5_TASK_ID, + ch6_evt_id: CH6_EVT_ID, + ch6_task_id: CH6_TASK_ID, + ch7_evt_id: CH7_EVT_ID, + ch7_task_id: CH7_TASK_ID, + ch8_evt_id: CH8_EVT_ID, + ch8_task_id: CH8_TASK_ID, + ch9_evt_id: CH9_EVT_ID, + ch9_task_id: CH9_TASK_ID, + ch10_evt_id: CH10_EVT_ID, + ch10_task_id: CH10_TASK_ID, + ch11_evt_id: CH11_EVT_ID, + ch11_task_id: CH11_TASK_ID, + ch12_evt_id: CH12_EVT_ID, + ch12_task_id: CH12_TASK_ID, + ch13_evt_id: CH13_EVT_ID, + ch13_task_id: CH13_TASK_ID, + ch14_evt_id: CH14_EVT_ID, + ch14_task_id: CH14_TASK_ID, + ch15_evt_id: CH15_EVT_ID, + ch15_task_id: CH15_TASK_ID, + ch16_evt_id: CH16_EVT_ID, + ch16_task_id: CH16_TASK_ID, + ch17_evt_id: CH17_EVT_ID, + ch17_task_id: CH17_TASK_ID, + ch18_evt_id: CH18_EVT_ID, + ch18_task_id: CH18_TASK_ID, + ch19_evt_id: CH19_EVT_ID, + ch19_task_id: CH19_TASK_ID, + ch20_evt_id: CH20_EVT_ID, + ch20_task_id: CH20_TASK_ID, + ch21_evt_id: CH21_EVT_ID, + ch21_task_id: CH21_TASK_ID, + ch22_evt_id: CH22_EVT_ID, + ch22_task_id: CH22_TASK_ID, + ch23_evt_id: CH23_EVT_ID, + ch23_task_id: CH23_TASK_ID, + ch24_evt_id: CH24_EVT_ID, + ch24_task_id: CH24_TASK_ID, + ch25_evt_id: CH25_EVT_ID, + ch25_task_id: CH25_TASK_ID, + ch26_evt_id: CH26_EVT_ID, + ch26_task_id: CH26_TASK_ID, + ch27_evt_id: CH27_EVT_ID, + ch27_task_id: CH27_TASK_ID, + ch28_evt_id: CH28_EVT_ID, + ch28_task_id: CH28_TASK_ID, + ch29_evt_id: CH29_EVT_ID, + ch29_task_id: CH29_TASK_ID, + ch30_evt_id: CH30_EVT_ID, + ch30_task_id: CH30_TASK_ID, + ch31_evt_id: CH31_EVT_ID, + ch31_task_id: CH31_TASK_ID, + ch32_evt_id: CH32_EVT_ID, + ch32_task_id: CH32_TASK_ID, + ch33_evt_id: CH33_EVT_ID, + ch33_task_id: CH33_TASK_ID, + ch34_evt_id: CH34_EVT_ID, + ch34_task_id: CH34_TASK_ID, + ch35_evt_id: CH35_EVT_ID, + ch35_task_id: CH35_TASK_ID, + ch36_evt_id: CH36_EVT_ID, + ch36_task_id: CH36_TASK_ID, + ch37_evt_id: CH37_EVT_ID, + ch37_task_id: CH37_TASK_ID, + ch38_evt_id: CH38_EVT_ID, + ch38_task_id: CH38_TASK_ID, + ch39_evt_id: CH39_EVT_ID, + ch39_task_id: CH39_TASK_ID, + ch40_evt_id: CH40_EVT_ID, + ch40_task_id: CH40_TASK_ID, + ch41_evt_id: CH41_EVT_ID, + ch41_task_id: CH41_TASK_ID, + ch42_evt_id: CH42_EVT_ID, + ch42_task_id: CH42_TASK_ID, + ch43_evt_id: CH43_EVT_ID, + ch43_task_id: CH43_TASK_ID, + ch44_evt_id: CH44_EVT_ID, + ch44_task_id: CH44_TASK_ID, + ch45_evt_id: CH45_EVT_ID, + ch45_task_id: CH45_TASK_ID, + ch46_evt_id: CH46_EVT_ID, + ch46_task_id: CH46_TASK_ID, + ch47_evt_id: CH47_EVT_ID, + ch47_task_id: CH47_TASK_ID, + ch48_evt_id: CH48_EVT_ID, + ch48_task_id: CH48_TASK_ID, + ch49_evt_id: CH49_EVT_ID, + ch49_task_id: CH49_TASK_ID, + evt_st0: EVT_ST0, + evt_st0_clr: EVT_ST0_CLR, + evt_st1: EVT_ST1, + evt_st1_clr: EVT_ST1_CLR, + evt_st2: EVT_ST2, + evt_st2_clr: EVT_ST2_CLR, + evt_st3: EVT_ST3, + evt_st3_clr: EVT_ST3_CLR, + evt_st4: EVT_ST4, + evt_st4_clr: EVT_ST4_CLR, + evt_st5: EVT_ST5, + evt_st5_clr: EVT_ST5_CLR, + evt_st6: EVT_ST6, + evt_st6_clr: EVT_ST6_CLR, + evt_st7: EVT_ST7, + evt_st7_clr: EVT_ST7_CLR, + task_st0: TASK_ST0, + task_st0_clr: TASK_ST0_CLR, + task_st1: TASK_ST1, + task_st1_clr: TASK_ST1_CLR, + task_st2: TASK_ST2, + task_st2_clr: TASK_ST2_CLR, + task_st3: TASK_ST3, + task_st3_clr: TASK_ST3_CLR, + task_st4: TASK_ST4, + task_st4_clr: TASK_ST4_CLR, + task_st5: TASK_ST5, + task_st5_clr: TASK_ST5_CLR, + task_st6: TASK_ST6, + task_st6_clr: TASK_ST6_CLR, + clk_en: CLK_EN, + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - Channel enable status register"] + #[inline(always)] + pub const fn ch_ena_ad0(&self) -> &CH_ENA_AD0 { + &self.ch_ena_ad0 + } + #[doc = "0x04 - Channel enable set register"] + #[inline(always)] + pub const fn ch_ena_ad0_set(&self) -> &CH_ENA_AD0_SET { + &self.ch_ena_ad0_set + } + #[doc = "0x08 - Channel enable clear register"] + #[inline(always)] + pub const fn ch_ena_ad0_clr(&self) -> &CH_ENA_AD0_CLR { + &self.ch_ena_ad0_clr + } + #[doc = "0x0c - Channel enable status register"] + #[inline(always)] + pub const fn ch_ena_ad1(&self) -> &CH_ENA_AD1 { + &self.ch_ena_ad1 + } + #[doc = "0x10 - Channel enable set register"] + #[inline(always)] + pub const fn ch_ena_ad1_set(&self) -> &CH_ENA_AD1_SET { + &self.ch_ena_ad1_set + } + #[doc = "0x14 - Channel enable clear register"] + #[inline(always)] + pub const fn ch_ena_ad1_clr(&self) -> &CH_ENA_AD1_CLR { + &self.ch_ena_ad1_clr + } + #[doc = "0x18 - Channel0 event id register"] + #[inline(always)] + pub const fn ch0_evt_id(&self) -> &CH0_EVT_ID { + &self.ch0_evt_id + } + #[doc = "0x1c - Channel0 task id register"] + #[inline(always)] + pub const fn ch0_task_id(&self) -> &CH0_TASK_ID { + &self.ch0_task_id + } + #[doc = "0x20 - Channel1 event id register"] + #[inline(always)] + pub const fn ch1_evt_id(&self) -> &CH1_EVT_ID { + &self.ch1_evt_id + } + #[doc = "0x24 - Channel1 task id register"] + #[inline(always)] + pub const fn ch1_task_id(&self) -> &CH1_TASK_ID { + &self.ch1_task_id + } + #[doc = "0x28 - Channel2 event id register"] + #[inline(always)] + pub const fn ch2_evt_id(&self) -> &CH2_EVT_ID { + &self.ch2_evt_id + } + #[doc = "0x2c - Channel2 task id register"] + #[inline(always)] + pub const fn ch2_task_id(&self) -> &CH2_TASK_ID { + &self.ch2_task_id + } + #[doc = "0x30 - Channel3 event id register"] + #[inline(always)] + pub const fn ch3_evt_id(&self) -> &CH3_EVT_ID { + &self.ch3_evt_id + } + #[doc = "0x34 - Channel3 task id register"] + #[inline(always)] + pub const fn ch3_task_id(&self) -> &CH3_TASK_ID { + &self.ch3_task_id + } + #[doc = "0x38 - Channel4 event id register"] + #[inline(always)] + pub const fn ch4_evt_id(&self) -> &CH4_EVT_ID { + &self.ch4_evt_id + } + #[doc = "0x3c - Channel4 task id register"] + #[inline(always)] + pub const fn ch4_task_id(&self) -> &CH4_TASK_ID { + &self.ch4_task_id + } + #[doc = "0x40 - Channel5 event id register"] + #[inline(always)] + pub const fn ch5_evt_id(&self) -> &CH5_EVT_ID { + &self.ch5_evt_id + } + #[doc = "0x44 - Channel5 task id register"] + #[inline(always)] + pub const fn ch5_task_id(&self) -> &CH5_TASK_ID { + &self.ch5_task_id + } + #[doc = "0x48 - Channel6 event id register"] + #[inline(always)] + pub const fn ch6_evt_id(&self) -> &CH6_EVT_ID { + &self.ch6_evt_id + } + #[doc = "0x4c - Channel6 task id register"] + #[inline(always)] + pub const fn ch6_task_id(&self) -> &CH6_TASK_ID { + &self.ch6_task_id + } + #[doc = "0x50 - Channel7 event id register"] + #[inline(always)] + pub const fn ch7_evt_id(&self) -> &CH7_EVT_ID { + &self.ch7_evt_id + } + #[doc = "0x54 - Channel7 task id register"] + #[inline(always)] + pub const fn ch7_task_id(&self) -> &CH7_TASK_ID { + &self.ch7_task_id + } + #[doc = "0x58 - Channel8 event id register"] + #[inline(always)] + pub const fn ch8_evt_id(&self) -> &CH8_EVT_ID { + &self.ch8_evt_id + } + #[doc = "0x5c - Channel8 task id register"] + #[inline(always)] + pub const fn ch8_task_id(&self) -> &CH8_TASK_ID { + &self.ch8_task_id + } + #[doc = "0x60 - Channel9 event id register"] + #[inline(always)] + pub const fn ch9_evt_id(&self) -> &CH9_EVT_ID { + &self.ch9_evt_id + } + #[doc = "0x64 - Channel9 task id register"] + #[inline(always)] + pub const fn ch9_task_id(&self) -> &CH9_TASK_ID { + &self.ch9_task_id + } + #[doc = "0x68 - Channel10 event id register"] + #[inline(always)] + pub const fn ch10_evt_id(&self) -> &CH10_EVT_ID { + &self.ch10_evt_id + } + #[doc = "0x6c - Channel10 task id register"] + #[inline(always)] + pub const fn ch10_task_id(&self) -> &CH10_TASK_ID { + &self.ch10_task_id + } + #[doc = "0x70 - Channel11 event id register"] + #[inline(always)] + pub const fn ch11_evt_id(&self) -> &CH11_EVT_ID { + &self.ch11_evt_id + } + #[doc = "0x74 - Channel11 task id register"] + #[inline(always)] + pub const fn ch11_task_id(&self) -> &CH11_TASK_ID { + &self.ch11_task_id + } + #[doc = "0x78 - Channel12 event id register"] + #[inline(always)] + pub const fn ch12_evt_id(&self) -> &CH12_EVT_ID { + &self.ch12_evt_id + } + #[doc = "0x7c - Channel12 task id register"] + #[inline(always)] + pub const fn ch12_task_id(&self) -> &CH12_TASK_ID { + &self.ch12_task_id + } + #[doc = "0x80 - Channel13 event id register"] + #[inline(always)] + pub const fn ch13_evt_id(&self) -> &CH13_EVT_ID { + &self.ch13_evt_id + } + #[doc = "0x84 - Channel13 task id register"] + #[inline(always)] + pub const fn ch13_task_id(&self) -> &CH13_TASK_ID { + &self.ch13_task_id + } + #[doc = "0x88 - Channel14 event id register"] + #[inline(always)] + pub const fn ch14_evt_id(&self) -> &CH14_EVT_ID { + &self.ch14_evt_id + } + #[doc = "0x8c - Channel14 task id register"] + #[inline(always)] + pub const fn ch14_task_id(&self) -> &CH14_TASK_ID { + &self.ch14_task_id + } + #[doc = "0x90 - Channel15 event id register"] + #[inline(always)] + pub const fn ch15_evt_id(&self) -> &CH15_EVT_ID { + &self.ch15_evt_id + } + #[doc = "0x94 - Channel15 task id register"] + #[inline(always)] + pub const fn ch15_task_id(&self) -> &CH15_TASK_ID { + &self.ch15_task_id + } + #[doc = "0x98 - Channel16 event id register"] + #[inline(always)] + pub const fn ch16_evt_id(&self) -> &CH16_EVT_ID { + &self.ch16_evt_id + } + #[doc = "0x9c - Channel16 task id register"] + #[inline(always)] + pub const fn ch16_task_id(&self) -> &CH16_TASK_ID { + &self.ch16_task_id + } + #[doc = "0xa0 - Channel17 event id register"] + #[inline(always)] + pub const fn ch17_evt_id(&self) -> &CH17_EVT_ID { + &self.ch17_evt_id + } + #[doc = "0xa4 - Channel17 task id register"] + #[inline(always)] + pub const fn ch17_task_id(&self) -> &CH17_TASK_ID { + &self.ch17_task_id + } + #[doc = "0xa8 - Channel18 event id register"] + #[inline(always)] + pub const fn ch18_evt_id(&self) -> &CH18_EVT_ID { + &self.ch18_evt_id + } + #[doc = "0xac - Channel18 task id register"] + #[inline(always)] + pub const fn ch18_task_id(&self) -> &CH18_TASK_ID { + &self.ch18_task_id + } + #[doc = "0xb0 - Channel19 event id register"] + #[inline(always)] + pub const fn ch19_evt_id(&self) -> &CH19_EVT_ID { + &self.ch19_evt_id + } + #[doc = "0xb4 - Channel19 task id register"] + #[inline(always)] + pub const fn ch19_task_id(&self) -> &CH19_TASK_ID { + &self.ch19_task_id + } + #[doc = "0xb8 - Channel20 event id register"] + #[inline(always)] + pub const fn ch20_evt_id(&self) -> &CH20_EVT_ID { + &self.ch20_evt_id + } + #[doc = "0xbc - Channel20 task id register"] + #[inline(always)] + pub const fn ch20_task_id(&self) -> &CH20_TASK_ID { + &self.ch20_task_id + } + #[doc = "0xc0 - Channel21 event id register"] + #[inline(always)] + pub const fn ch21_evt_id(&self) -> &CH21_EVT_ID { + &self.ch21_evt_id + } + #[doc = "0xc4 - Channel21 task id register"] + #[inline(always)] + pub const fn ch21_task_id(&self) -> &CH21_TASK_ID { + &self.ch21_task_id + } + #[doc = "0xc8 - Channel22 event id register"] + #[inline(always)] + pub const fn ch22_evt_id(&self) -> &CH22_EVT_ID { + &self.ch22_evt_id + } + #[doc = "0xcc - Channel22 task id register"] + #[inline(always)] + pub const fn ch22_task_id(&self) -> &CH22_TASK_ID { + &self.ch22_task_id + } + #[doc = "0xd0 - Channel23 event id register"] + #[inline(always)] + pub const fn ch23_evt_id(&self) -> &CH23_EVT_ID { + &self.ch23_evt_id + } + #[doc = "0xd4 - Channel23 task id register"] + #[inline(always)] + pub const fn ch23_task_id(&self) -> &CH23_TASK_ID { + &self.ch23_task_id + } + #[doc = "0xd8 - Channel24 event id register"] + #[inline(always)] + pub const fn ch24_evt_id(&self) -> &CH24_EVT_ID { + &self.ch24_evt_id + } + #[doc = "0xdc - Channel24 task id register"] + #[inline(always)] + pub const fn ch24_task_id(&self) -> &CH24_TASK_ID { + &self.ch24_task_id + } + #[doc = "0xe0 - Channel25 event id register"] + #[inline(always)] + pub const fn ch25_evt_id(&self) -> &CH25_EVT_ID { + &self.ch25_evt_id + } + #[doc = "0xe4 - Channel25 task id register"] + #[inline(always)] + pub const fn ch25_task_id(&self) -> &CH25_TASK_ID { + &self.ch25_task_id + } + #[doc = "0xe8 - Channel26 event id register"] + #[inline(always)] + pub const fn ch26_evt_id(&self) -> &CH26_EVT_ID { + &self.ch26_evt_id + } + #[doc = "0xec - Channel26 task id register"] + #[inline(always)] + pub const fn ch26_task_id(&self) -> &CH26_TASK_ID { + &self.ch26_task_id + } + #[doc = "0xf0 - Channel27 event id register"] + #[inline(always)] + pub const fn ch27_evt_id(&self) -> &CH27_EVT_ID { + &self.ch27_evt_id + } + #[doc = "0xf4 - Channel27 task id register"] + #[inline(always)] + pub const fn ch27_task_id(&self) -> &CH27_TASK_ID { + &self.ch27_task_id + } + #[doc = "0xf8 - Channel28 event id register"] + #[inline(always)] + pub const fn ch28_evt_id(&self) -> &CH28_EVT_ID { + &self.ch28_evt_id + } + #[doc = "0xfc - Channel28 task id register"] + #[inline(always)] + pub const fn ch28_task_id(&self) -> &CH28_TASK_ID { + &self.ch28_task_id + } + #[doc = "0x100 - Channel29 event id register"] + #[inline(always)] + pub const fn ch29_evt_id(&self) -> &CH29_EVT_ID { + &self.ch29_evt_id + } + #[doc = "0x104 - Channel29 task id register"] + #[inline(always)] + pub const fn ch29_task_id(&self) -> &CH29_TASK_ID { + &self.ch29_task_id + } + #[doc = "0x108 - Channel30 event id register"] + #[inline(always)] + pub const fn ch30_evt_id(&self) -> &CH30_EVT_ID { + &self.ch30_evt_id + } + #[doc = "0x10c - Channel30 task id register"] + #[inline(always)] + pub const fn ch30_task_id(&self) -> &CH30_TASK_ID { + &self.ch30_task_id + } + #[doc = "0x110 - Channel31 event id register"] + #[inline(always)] + pub const fn ch31_evt_id(&self) -> &CH31_EVT_ID { + &self.ch31_evt_id + } + #[doc = "0x114 - Channel31 task id register"] + #[inline(always)] + pub const fn ch31_task_id(&self) -> &CH31_TASK_ID { + &self.ch31_task_id + } + #[doc = "0x118 - Channel32 event id register"] + #[inline(always)] + pub const fn ch32_evt_id(&self) -> &CH32_EVT_ID { + &self.ch32_evt_id + } + #[doc = "0x11c - Channel32 task id register"] + #[inline(always)] + pub const fn ch32_task_id(&self) -> &CH32_TASK_ID { + &self.ch32_task_id + } + #[doc = "0x120 - Channel33 event id register"] + #[inline(always)] + pub const fn ch33_evt_id(&self) -> &CH33_EVT_ID { + &self.ch33_evt_id + } + #[doc = "0x124 - Channel33 task id register"] + #[inline(always)] + pub const fn ch33_task_id(&self) -> &CH33_TASK_ID { + &self.ch33_task_id + } + #[doc = "0x128 - Channel34 event id register"] + #[inline(always)] + pub const fn ch34_evt_id(&self) -> &CH34_EVT_ID { + &self.ch34_evt_id + } + #[doc = "0x12c - Channel34 task id register"] + #[inline(always)] + pub const fn ch34_task_id(&self) -> &CH34_TASK_ID { + &self.ch34_task_id + } + #[doc = "0x130 - Channel35 event id register"] + #[inline(always)] + pub const fn ch35_evt_id(&self) -> &CH35_EVT_ID { + &self.ch35_evt_id + } + #[doc = "0x134 - Channel35 task id register"] + #[inline(always)] + pub const fn ch35_task_id(&self) -> &CH35_TASK_ID { + &self.ch35_task_id + } + #[doc = "0x138 - Channel36 event id register"] + #[inline(always)] + pub const fn ch36_evt_id(&self) -> &CH36_EVT_ID { + &self.ch36_evt_id + } + #[doc = "0x13c - Channel36 task id register"] + #[inline(always)] + pub const fn ch36_task_id(&self) -> &CH36_TASK_ID { + &self.ch36_task_id + } + #[doc = "0x140 - Channel37 event id register"] + #[inline(always)] + pub const fn ch37_evt_id(&self) -> &CH37_EVT_ID { + &self.ch37_evt_id + } + #[doc = "0x144 - Channel37 task id register"] + #[inline(always)] + pub const fn ch37_task_id(&self) -> &CH37_TASK_ID { + &self.ch37_task_id + } + #[doc = "0x148 - Channel38 event id register"] + #[inline(always)] + pub const fn ch38_evt_id(&self) -> &CH38_EVT_ID { + &self.ch38_evt_id + } + #[doc = "0x14c - Channel38 task id register"] + #[inline(always)] + pub const fn ch38_task_id(&self) -> &CH38_TASK_ID { + &self.ch38_task_id + } + #[doc = "0x150 - Channel39 event id register"] + #[inline(always)] + pub const fn ch39_evt_id(&self) -> &CH39_EVT_ID { + &self.ch39_evt_id + } + #[doc = "0x154 - Channel39 task id register"] + #[inline(always)] + pub const fn ch39_task_id(&self) -> &CH39_TASK_ID { + &self.ch39_task_id + } + #[doc = "0x158 - Channel40 event id register"] + #[inline(always)] + pub const fn ch40_evt_id(&self) -> &CH40_EVT_ID { + &self.ch40_evt_id + } + #[doc = "0x15c - Channel40 task id register"] + #[inline(always)] + pub const fn ch40_task_id(&self) -> &CH40_TASK_ID { + &self.ch40_task_id + } + #[doc = "0x160 - Channel41 event id register"] + #[inline(always)] + pub const fn ch41_evt_id(&self) -> &CH41_EVT_ID { + &self.ch41_evt_id + } + #[doc = "0x164 - Channel41 task id register"] + #[inline(always)] + pub const fn ch41_task_id(&self) -> &CH41_TASK_ID { + &self.ch41_task_id + } + #[doc = "0x168 - Channel42 event id register"] + #[inline(always)] + pub const fn ch42_evt_id(&self) -> &CH42_EVT_ID { + &self.ch42_evt_id + } + #[doc = "0x16c - Channel42 task id register"] + #[inline(always)] + pub const fn ch42_task_id(&self) -> &CH42_TASK_ID { + &self.ch42_task_id + } + #[doc = "0x170 - Channel43 event id register"] + #[inline(always)] + pub const fn ch43_evt_id(&self) -> &CH43_EVT_ID { + &self.ch43_evt_id + } + #[doc = "0x174 - Channel43 task id register"] + #[inline(always)] + pub const fn ch43_task_id(&self) -> &CH43_TASK_ID { + &self.ch43_task_id + } + #[doc = "0x178 - Channel44 event id register"] + #[inline(always)] + pub const fn ch44_evt_id(&self) -> &CH44_EVT_ID { + &self.ch44_evt_id + } + #[doc = "0x17c - Channel44 task id register"] + #[inline(always)] + pub const fn ch44_task_id(&self) -> &CH44_TASK_ID { + &self.ch44_task_id + } + #[doc = "0x180 - Channel45 event id register"] + #[inline(always)] + pub const fn ch45_evt_id(&self) -> &CH45_EVT_ID { + &self.ch45_evt_id + } + #[doc = "0x184 - Channel45 task id register"] + #[inline(always)] + pub const fn ch45_task_id(&self) -> &CH45_TASK_ID { + &self.ch45_task_id + } + #[doc = "0x188 - Channel46 event id register"] + #[inline(always)] + pub const fn ch46_evt_id(&self) -> &CH46_EVT_ID { + &self.ch46_evt_id + } + #[doc = "0x18c - Channel46 task id register"] + #[inline(always)] + pub const fn ch46_task_id(&self) -> &CH46_TASK_ID { + &self.ch46_task_id + } + #[doc = "0x190 - Channel47 event id register"] + #[inline(always)] + pub const fn ch47_evt_id(&self) -> &CH47_EVT_ID { + &self.ch47_evt_id + } + #[doc = "0x194 - Channel47 task id register"] + #[inline(always)] + pub const fn ch47_task_id(&self) -> &CH47_TASK_ID { + &self.ch47_task_id + } + #[doc = "0x198 - Channel48 event id register"] + #[inline(always)] + pub const fn ch48_evt_id(&self) -> &CH48_EVT_ID { + &self.ch48_evt_id + } + #[doc = "0x19c - Channel48 task id register"] + #[inline(always)] + pub const fn ch48_task_id(&self) -> &CH48_TASK_ID { + &self.ch48_task_id + } + #[doc = "0x1a0 - Channel49 event id register"] + #[inline(always)] + pub const fn ch49_evt_id(&self) -> &CH49_EVT_ID { + &self.ch49_evt_id + } + #[doc = "0x1a4 - Channel49 task id register"] + #[inline(always)] + pub const fn ch49_task_id(&self) -> &CH49_TASK_ID { + &self.ch49_task_id + } + #[doc = "0x1a8 - Events trigger status register"] + #[inline(always)] + pub const fn evt_st0(&self) -> &EVT_ST0 { + &self.evt_st0 + } + #[doc = "0x1ac - Events trigger status clear register"] + #[inline(always)] + pub const fn evt_st0_clr(&self) -> &EVT_ST0_CLR { + &self.evt_st0_clr + } + #[doc = "0x1b0 - Events trigger status register"] + #[inline(always)] + pub const fn evt_st1(&self) -> &EVT_ST1 { + &self.evt_st1 + } + #[doc = "0x1b4 - Events trigger status clear register"] + #[inline(always)] + pub const fn evt_st1_clr(&self) -> &EVT_ST1_CLR { + &self.evt_st1_clr + } + #[doc = "0x1b8 - Events trigger status register"] + #[inline(always)] + pub const fn evt_st2(&self) -> &EVT_ST2 { + &self.evt_st2 + } + #[doc = "0x1bc - Events trigger status clear register"] + #[inline(always)] + pub const fn evt_st2_clr(&self) -> &EVT_ST2_CLR { + &self.evt_st2_clr + } + #[doc = "0x1c0 - Events trigger status register"] + #[inline(always)] + pub const fn evt_st3(&self) -> &EVT_ST3 { + &self.evt_st3 + } + #[doc = "0x1c4 - Events trigger status clear register"] + #[inline(always)] + pub const fn evt_st3_clr(&self) -> &EVT_ST3_CLR { + &self.evt_st3_clr + } + #[doc = "0x1c8 - Events trigger status register"] + #[inline(always)] + pub const fn evt_st4(&self) -> &EVT_ST4 { + &self.evt_st4 + } + #[doc = "0x1cc - Events trigger status clear register"] + #[inline(always)] + pub const fn evt_st4_clr(&self) -> &EVT_ST4_CLR { + &self.evt_st4_clr + } + #[doc = "0x1d0 - Events trigger status register"] + #[inline(always)] + pub const fn evt_st5(&self) -> &EVT_ST5 { + &self.evt_st5 + } + #[doc = "0x1d4 - Events trigger status clear register"] + #[inline(always)] + pub const fn evt_st5_clr(&self) -> &EVT_ST5_CLR { + &self.evt_st5_clr + } + #[doc = "0x1d8 - Events trigger status register"] + #[inline(always)] + pub const fn evt_st6(&self) -> &EVT_ST6 { + &self.evt_st6 + } + #[doc = "0x1dc - Events trigger status clear register"] + #[inline(always)] + pub const fn evt_st6_clr(&self) -> &EVT_ST6_CLR { + &self.evt_st6_clr + } + #[doc = "0x1e0 - Events trigger status register"] + #[inline(always)] + pub const fn evt_st7(&self) -> &EVT_ST7 { + &self.evt_st7 + } + #[doc = "0x1e4 - Events trigger status clear register"] + #[inline(always)] + pub const fn evt_st7_clr(&self) -> &EVT_ST7_CLR { + &self.evt_st7_clr + } + #[doc = "0x1e8 - Tasks trigger status register"] + #[inline(always)] + pub const fn task_st0(&self) -> &TASK_ST0 { + &self.task_st0 + } + #[doc = "0x1ec - Tasks trigger status clear register"] + #[inline(always)] + pub const fn task_st0_clr(&self) -> &TASK_ST0_CLR { + &self.task_st0_clr + } + #[doc = "0x1f0 - Tasks trigger status register"] + #[inline(always)] + pub const fn task_st1(&self) -> &TASK_ST1 { + &self.task_st1 + } + #[doc = "0x1f4 - Tasks trigger status clear register"] + #[inline(always)] + pub const fn task_st1_clr(&self) -> &TASK_ST1_CLR { + &self.task_st1_clr + } + #[doc = "0x1f8 - Tasks trigger status register"] + #[inline(always)] + pub const fn task_st2(&self) -> &TASK_ST2 { + &self.task_st2 + } + #[doc = "0x1fc - Tasks trigger status clear register"] + #[inline(always)] + pub const fn task_st2_clr(&self) -> &TASK_ST2_CLR { + &self.task_st2_clr + } + #[doc = "0x200 - Tasks trigger status register"] + #[inline(always)] + pub const fn task_st3(&self) -> &TASK_ST3 { + &self.task_st3 + } + #[doc = "0x204 - Tasks trigger status clear register"] + #[inline(always)] + pub const fn task_st3_clr(&self) -> &TASK_ST3_CLR { + &self.task_st3_clr + } + #[doc = "0x208 - Tasks trigger status register"] + #[inline(always)] + pub const fn task_st4(&self) -> &TASK_ST4 { + &self.task_st4 + } + #[doc = "0x20c - Tasks trigger status clear register"] + #[inline(always)] + pub const fn task_st4_clr(&self) -> &TASK_ST4_CLR { + &self.task_st4_clr + } + #[doc = "0x210 - Tasks trigger status register"] + #[inline(always)] + pub const fn task_st5(&self) -> &TASK_ST5 { + &self.task_st5 + } + #[doc = "0x214 - Tasks trigger status clear register"] + #[inline(always)] + pub const fn task_st5_clr(&self) -> &TASK_ST5_CLR { + &self.task_st5_clr + } + #[doc = "0x218 - Tasks trigger status register"] + #[inline(always)] + pub const fn task_st6(&self) -> &TASK_ST6 { + &self.task_st6 + } + #[doc = "0x21c - Tasks trigger status clear register"] + #[inline(always)] + pub const fn task_st6_clr(&self) -> &TASK_ST6_CLR { + &self.task_st6_clr + } + #[doc = "0x220 - ETM clock enable register"] + #[inline(always)] + pub const fn clk_en(&self) -> &CLK_EN { + &self.clk_en + } + #[doc = "0x224 - ETM date register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "CH_ENA_AD0 (rw) register accessor: Channel enable status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_ena_ad0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad0`] module"] +pub type CH_ENA_AD0 = crate::Reg; +#[doc = "Channel enable status register"] +pub mod ch_ena_ad0; +#[doc = "CH_ENA_AD0_SET (w) register accessor: Channel enable set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad0_set`] module"] +pub type CH_ENA_AD0_SET = crate::Reg; +#[doc = "Channel enable set register"] +pub mod ch_ena_ad0_set; +#[doc = "CH_ENA_AD0_CLR (w) register accessor: Channel enable clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad0_clr`] module"] +pub type CH_ENA_AD0_CLR = crate::Reg; +#[doc = "Channel enable clear register"] +pub mod ch_ena_ad0_clr; +#[doc = "CH_ENA_AD1 (rw) register accessor: Channel enable status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_ena_ad1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad1`] module"] +pub type CH_ENA_AD1 = crate::Reg; +#[doc = "Channel enable status register"] +pub mod ch_ena_ad1; +#[doc = "CH_ENA_AD1_SET (w) register accessor: Channel enable set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad1_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad1_set`] module"] +pub type CH_ENA_AD1_SET = crate::Reg; +#[doc = "Channel enable set register"] +pub mod ch_ena_ad1_set; +#[doc = "CH_ENA_AD1_CLR (w) register accessor: Channel enable clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad1_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad1_clr`] module"] +pub type CH_ENA_AD1_CLR = crate::Reg; +#[doc = "Channel enable clear register"] +pub mod ch_ena_ad1_clr; +#[doc = "CH0_EVT_ID (rw) register accessor: Channel0 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch0_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch0_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0_evt_id`] module"] +pub type CH0_EVT_ID = crate::Reg; +#[doc = "Channel0 event id register"] +pub mod ch0_evt_id; +#[doc = "CH0_TASK_ID (rw) register accessor: Channel0 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch0_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch0_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch0_task_id`] module"] +pub type CH0_TASK_ID = crate::Reg; +#[doc = "Channel0 task id register"] +pub mod ch0_task_id; +#[doc = "CH1_EVT_ID (rw) register accessor: Channel1 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_evt_id`] module"] +pub type CH1_EVT_ID = crate::Reg; +#[doc = "Channel1 event id register"] +pub mod ch1_evt_id; +#[doc = "CH1_TASK_ID (rw) register accessor: Channel1 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch1_task_id`] module"] +pub type CH1_TASK_ID = crate::Reg; +#[doc = "Channel1 task id register"] +pub mod ch1_task_id; +#[doc = "CH2_EVT_ID (rw) register accessor: Channel2 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_evt_id`] module"] +pub type CH2_EVT_ID = crate::Reg; +#[doc = "Channel2 event id register"] +pub mod ch2_evt_id; +#[doc = "CH2_TASK_ID (rw) register accessor: Channel2 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch2_task_id`] module"] +pub type CH2_TASK_ID = crate::Reg; +#[doc = "Channel2 task id register"] +pub mod ch2_task_id; +#[doc = "CH3_EVT_ID (rw) register accessor: Channel3 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_evt_id`] module"] +pub type CH3_EVT_ID = crate::Reg; +#[doc = "Channel3 event id register"] +pub mod ch3_evt_id; +#[doc = "CH3_TASK_ID (rw) register accessor: Channel3 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch3_task_id`] module"] +pub type CH3_TASK_ID = crate::Reg; +#[doc = "Channel3 task id register"] +pub mod ch3_task_id; +#[doc = "CH4_EVT_ID (rw) register accessor: Channel4 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_evt_id`] module"] +pub type CH4_EVT_ID = crate::Reg; +#[doc = "Channel4 event id register"] +pub mod ch4_evt_id; +#[doc = "CH4_TASK_ID (rw) register accessor: Channel4 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch4_task_id`] module"] +pub type CH4_TASK_ID = crate::Reg; +#[doc = "Channel4 task id register"] +pub mod ch4_task_id; +#[doc = "CH5_EVT_ID (rw) register accessor: Channel5 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch5_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch5_evt_id`] module"] +pub type CH5_EVT_ID = crate::Reg; +#[doc = "Channel5 event id register"] +pub mod ch5_evt_id; +#[doc = "CH5_TASK_ID (rw) register accessor: Channel5 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch5_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch5_task_id`] module"] +pub type CH5_TASK_ID = crate::Reg; +#[doc = "Channel5 task id register"] +pub mod ch5_task_id; +#[doc = "CH6_EVT_ID (rw) register accessor: Channel6 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch6_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch6_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch6_evt_id`] module"] +pub type CH6_EVT_ID = crate::Reg; +#[doc = "Channel6 event id register"] +pub mod ch6_evt_id; +#[doc = "CH6_TASK_ID (rw) register accessor: Channel6 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch6_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch6_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch6_task_id`] module"] +pub type CH6_TASK_ID = crate::Reg; +#[doc = "Channel6 task id register"] +pub mod ch6_task_id; +#[doc = "CH7_EVT_ID (rw) register accessor: Channel7 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch7_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch7_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch7_evt_id`] module"] +pub type CH7_EVT_ID = crate::Reg; +#[doc = "Channel7 event id register"] +pub mod ch7_evt_id; +#[doc = "CH7_TASK_ID (rw) register accessor: Channel7 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch7_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch7_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch7_task_id`] module"] +pub type CH7_TASK_ID = crate::Reg; +#[doc = "Channel7 task id register"] +pub mod ch7_task_id; +#[doc = "CH8_EVT_ID (rw) register accessor: Channel8 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch8_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch8_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch8_evt_id`] module"] +pub type CH8_EVT_ID = crate::Reg; +#[doc = "Channel8 event id register"] +pub mod ch8_evt_id; +#[doc = "CH8_TASK_ID (rw) register accessor: Channel8 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch8_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch8_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch8_task_id`] module"] +pub type CH8_TASK_ID = crate::Reg; +#[doc = "Channel8 task id register"] +pub mod ch8_task_id; +#[doc = "CH9_EVT_ID (rw) register accessor: Channel9 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch9_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch9_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch9_evt_id`] module"] +pub type CH9_EVT_ID = crate::Reg; +#[doc = "Channel9 event id register"] +pub mod ch9_evt_id; +#[doc = "CH9_TASK_ID (rw) register accessor: Channel9 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch9_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch9_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch9_task_id`] module"] +pub type CH9_TASK_ID = crate::Reg; +#[doc = "Channel9 task id register"] +pub mod ch9_task_id; +#[doc = "CH10_EVT_ID (rw) register accessor: Channel10 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch10_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch10_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch10_evt_id`] module"] +pub type CH10_EVT_ID = crate::Reg; +#[doc = "Channel10 event id register"] +pub mod ch10_evt_id; +#[doc = "CH10_TASK_ID (rw) register accessor: Channel10 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch10_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch10_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch10_task_id`] module"] +pub type CH10_TASK_ID = crate::Reg; +#[doc = "Channel10 task id register"] +pub mod ch10_task_id; +#[doc = "CH11_EVT_ID (rw) register accessor: Channel11 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch11_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch11_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch11_evt_id`] module"] +pub type CH11_EVT_ID = crate::Reg; +#[doc = "Channel11 event id register"] +pub mod ch11_evt_id; +#[doc = "CH11_TASK_ID (rw) register accessor: Channel11 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch11_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch11_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch11_task_id`] module"] +pub type CH11_TASK_ID = crate::Reg; +#[doc = "Channel11 task id register"] +pub mod ch11_task_id; +#[doc = "CH12_EVT_ID (rw) register accessor: Channel12 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch12_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch12_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch12_evt_id`] module"] +pub type CH12_EVT_ID = crate::Reg; +#[doc = "Channel12 event id register"] +pub mod ch12_evt_id; +#[doc = "CH12_TASK_ID (rw) register accessor: Channel12 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch12_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch12_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch12_task_id`] module"] +pub type CH12_TASK_ID = crate::Reg; +#[doc = "Channel12 task id register"] +pub mod ch12_task_id; +#[doc = "CH13_EVT_ID (rw) register accessor: Channel13 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch13_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch13_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch13_evt_id`] module"] +pub type CH13_EVT_ID = crate::Reg; +#[doc = "Channel13 event id register"] +pub mod ch13_evt_id; +#[doc = "CH13_TASK_ID (rw) register accessor: Channel13 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch13_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch13_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch13_task_id`] module"] +pub type CH13_TASK_ID = crate::Reg; +#[doc = "Channel13 task id register"] +pub mod ch13_task_id; +#[doc = "CH14_EVT_ID (rw) register accessor: Channel14 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch14_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch14_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch14_evt_id`] module"] +pub type CH14_EVT_ID = crate::Reg; +#[doc = "Channel14 event id register"] +pub mod ch14_evt_id; +#[doc = "CH14_TASK_ID (rw) register accessor: Channel14 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch14_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch14_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch14_task_id`] module"] +pub type CH14_TASK_ID = crate::Reg; +#[doc = "Channel14 task id register"] +pub mod ch14_task_id; +#[doc = "CH15_EVT_ID (rw) register accessor: Channel15 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch15_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch15_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch15_evt_id`] module"] +pub type CH15_EVT_ID = crate::Reg; +#[doc = "Channel15 event id register"] +pub mod ch15_evt_id; +#[doc = "CH15_TASK_ID (rw) register accessor: Channel15 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch15_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch15_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch15_task_id`] module"] +pub type CH15_TASK_ID = crate::Reg; +#[doc = "Channel15 task id register"] +pub mod ch15_task_id; +#[doc = "CH16_EVT_ID (rw) register accessor: Channel16 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch16_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch16_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch16_evt_id`] module"] +pub type CH16_EVT_ID = crate::Reg; +#[doc = "Channel16 event id register"] +pub mod ch16_evt_id; +#[doc = "CH16_TASK_ID (rw) register accessor: Channel16 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch16_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch16_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch16_task_id`] module"] +pub type CH16_TASK_ID = crate::Reg; +#[doc = "Channel16 task id register"] +pub mod ch16_task_id; +#[doc = "CH17_EVT_ID (rw) register accessor: Channel17 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch17_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch17_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch17_evt_id`] module"] +pub type CH17_EVT_ID = crate::Reg; +#[doc = "Channel17 event id register"] +pub mod ch17_evt_id; +#[doc = "CH17_TASK_ID (rw) register accessor: Channel17 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch17_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch17_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch17_task_id`] module"] +pub type CH17_TASK_ID = crate::Reg; +#[doc = "Channel17 task id register"] +pub mod ch17_task_id; +#[doc = "CH18_EVT_ID (rw) register accessor: Channel18 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch18_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch18_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch18_evt_id`] module"] +pub type CH18_EVT_ID = crate::Reg; +#[doc = "Channel18 event id register"] +pub mod ch18_evt_id; +#[doc = "CH18_TASK_ID (rw) register accessor: Channel18 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch18_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch18_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch18_task_id`] module"] +pub type CH18_TASK_ID = crate::Reg; +#[doc = "Channel18 task id register"] +pub mod ch18_task_id; +#[doc = "CH19_EVT_ID (rw) register accessor: Channel19 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch19_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch19_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch19_evt_id`] module"] +pub type CH19_EVT_ID = crate::Reg; +#[doc = "Channel19 event id register"] +pub mod ch19_evt_id; +#[doc = "CH19_TASK_ID (rw) register accessor: Channel19 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch19_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch19_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch19_task_id`] module"] +pub type CH19_TASK_ID = crate::Reg; +#[doc = "Channel19 task id register"] +pub mod ch19_task_id; +#[doc = "CH20_EVT_ID (rw) register accessor: Channel20 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch20_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch20_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch20_evt_id`] module"] +pub type CH20_EVT_ID = crate::Reg; +#[doc = "Channel20 event id register"] +pub mod ch20_evt_id; +#[doc = "CH20_TASK_ID (rw) register accessor: Channel20 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch20_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch20_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch20_task_id`] module"] +pub type CH20_TASK_ID = crate::Reg; +#[doc = "Channel20 task id register"] +pub mod ch20_task_id; +#[doc = "CH21_EVT_ID (rw) register accessor: Channel21 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch21_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch21_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch21_evt_id`] module"] +pub type CH21_EVT_ID = crate::Reg; +#[doc = "Channel21 event id register"] +pub mod ch21_evt_id; +#[doc = "CH21_TASK_ID (rw) register accessor: Channel21 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch21_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch21_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch21_task_id`] module"] +pub type CH21_TASK_ID = crate::Reg; +#[doc = "Channel21 task id register"] +pub mod ch21_task_id; +#[doc = "CH22_EVT_ID (rw) register accessor: Channel22 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch22_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch22_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch22_evt_id`] module"] +pub type CH22_EVT_ID = crate::Reg; +#[doc = "Channel22 event id register"] +pub mod ch22_evt_id; +#[doc = "CH22_TASK_ID (rw) register accessor: Channel22 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch22_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch22_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch22_task_id`] module"] +pub type CH22_TASK_ID = crate::Reg; +#[doc = "Channel22 task id register"] +pub mod ch22_task_id; +#[doc = "CH23_EVT_ID (rw) register accessor: Channel23 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch23_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch23_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch23_evt_id`] module"] +pub type CH23_EVT_ID = crate::Reg; +#[doc = "Channel23 event id register"] +pub mod ch23_evt_id; +#[doc = "CH23_TASK_ID (rw) register accessor: Channel23 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch23_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch23_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch23_task_id`] module"] +pub type CH23_TASK_ID = crate::Reg; +#[doc = "Channel23 task id register"] +pub mod ch23_task_id; +#[doc = "CH24_EVT_ID (rw) register accessor: Channel24 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch24_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch24_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch24_evt_id`] module"] +pub type CH24_EVT_ID = crate::Reg; +#[doc = "Channel24 event id register"] +pub mod ch24_evt_id; +#[doc = "CH24_TASK_ID (rw) register accessor: Channel24 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch24_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch24_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch24_task_id`] module"] +pub type CH24_TASK_ID = crate::Reg; +#[doc = "Channel24 task id register"] +pub mod ch24_task_id; +#[doc = "CH25_EVT_ID (rw) register accessor: Channel25 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch25_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch25_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch25_evt_id`] module"] +pub type CH25_EVT_ID = crate::Reg; +#[doc = "Channel25 event id register"] +pub mod ch25_evt_id; +#[doc = "CH25_TASK_ID (rw) register accessor: Channel25 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch25_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch25_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch25_task_id`] module"] +pub type CH25_TASK_ID = crate::Reg; +#[doc = "Channel25 task id register"] +pub mod ch25_task_id; +#[doc = "CH26_EVT_ID (rw) register accessor: Channel26 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch26_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch26_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch26_evt_id`] module"] +pub type CH26_EVT_ID = crate::Reg; +#[doc = "Channel26 event id register"] +pub mod ch26_evt_id; +#[doc = "CH26_TASK_ID (rw) register accessor: Channel26 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch26_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch26_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch26_task_id`] module"] +pub type CH26_TASK_ID = crate::Reg; +#[doc = "Channel26 task id register"] +pub mod ch26_task_id; +#[doc = "CH27_EVT_ID (rw) register accessor: Channel27 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch27_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch27_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch27_evt_id`] module"] +pub type CH27_EVT_ID = crate::Reg; +#[doc = "Channel27 event id register"] +pub mod ch27_evt_id; +#[doc = "CH27_TASK_ID (rw) register accessor: Channel27 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch27_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch27_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch27_task_id`] module"] +pub type CH27_TASK_ID = crate::Reg; +#[doc = "Channel27 task id register"] +pub mod ch27_task_id; +#[doc = "CH28_EVT_ID (rw) register accessor: Channel28 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch28_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch28_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch28_evt_id`] module"] +pub type CH28_EVT_ID = crate::Reg; +#[doc = "Channel28 event id register"] +pub mod ch28_evt_id; +#[doc = "CH28_TASK_ID (rw) register accessor: Channel28 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch28_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch28_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch28_task_id`] module"] +pub type CH28_TASK_ID = crate::Reg; +#[doc = "Channel28 task id register"] +pub mod ch28_task_id; +#[doc = "CH29_EVT_ID (rw) register accessor: Channel29 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch29_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch29_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch29_evt_id`] module"] +pub type CH29_EVT_ID = crate::Reg; +#[doc = "Channel29 event id register"] +pub mod ch29_evt_id; +#[doc = "CH29_TASK_ID (rw) register accessor: Channel29 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch29_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch29_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch29_task_id`] module"] +pub type CH29_TASK_ID = crate::Reg; +#[doc = "Channel29 task id register"] +pub mod ch29_task_id; +#[doc = "CH30_EVT_ID (rw) register accessor: Channel30 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch30_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch30_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch30_evt_id`] module"] +pub type CH30_EVT_ID = crate::Reg; +#[doc = "Channel30 event id register"] +pub mod ch30_evt_id; +#[doc = "CH30_TASK_ID (rw) register accessor: Channel30 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch30_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch30_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch30_task_id`] module"] +pub type CH30_TASK_ID = crate::Reg; +#[doc = "Channel30 task id register"] +pub mod ch30_task_id; +#[doc = "CH31_EVT_ID (rw) register accessor: Channel31 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch31_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch31_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch31_evt_id`] module"] +pub type CH31_EVT_ID = crate::Reg; +#[doc = "Channel31 event id register"] +pub mod ch31_evt_id; +#[doc = "CH31_TASK_ID (rw) register accessor: Channel31 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch31_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch31_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch31_task_id`] module"] +pub type CH31_TASK_ID = crate::Reg; +#[doc = "Channel31 task id register"] +pub mod ch31_task_id; +#[doc = "CH32_EVT_ID (rw) register accessor: Channel32 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch32_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch32_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch32_evt_id`] module"] +pub type CH32_EVT_ID = crate::Reg; +#[doc = "Channel32 event id register"] +pub mod ch32_evt_id; +#[doc = "CH32_TASK_ID (rw) register accessor: Channel32 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch32_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch32_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch32_task_id`] module"] +pub type CH32_TASK_ID = crate::Reg; +#[doc = "Channel32 task id register"] +pub mod ch32_task_id; +#[doc = "CH33_EVT_ID (rw) register accessor: Channel33 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch33_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch33_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch33_evt_id`] module"] +pub type CH33_EVT_ID = crate::Reg; +#[doc = "Channel33 event id register"] +pub mod ch33_evt_id; +#[doc = "CH33_TASK_ID (rw) register accessor: Channel33 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch33_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch33_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch33_task_id`] module"] +pub type CH33_TASK_ID = crate::Reg; +#[doc = "Channel33 task id register"] +pub mod ch33_task_id; +#[doc = "CH34_EVT_ID (rw) register accessor: Channel34 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch34_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch34_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch34_evt_id`] module"] +pub type CH34_EVT_ID = crate::Reg; +#[doc = "Channel34 event id register"] +pub mod ch34_evt_id; +#[doc = "CH34_TASK_ID (rw) register accessor: Channel34 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch34_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch34_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch34_task_id`] module"] +pub type CH34_TASK_ID = crate::Reg; +#[doc = "Channel34 task id register"] +pub mod ch34_task_id; +#[doc = "CH35_EVT_ID (rw) register accessor: Channel35 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch35_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch35_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch35_evt_id`] module"] +pub type CH35_EVT_ID = crate::Reg; +#[doc = "Channel35 event id register"] +pub mod ch35_evt_id; +#[doc = "CH35_TASK_ID (rw) register accessor: Channel35 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch35_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch35_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch35_task_id`] module"] +pub type CH35_TASK_ID = crate::Reg; +#[doc = "Channel35 task id register"] +pub mod ch35_task_id; +#[doc = "CH36_EVT_ID (rw) register accessor: Channel36 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch36_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch36_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch36_evt_id`] module"] +pub type CH36_EVT_ID = crate::Reg; +#[doc = "Channel36 event id register"] +pub mod ch36_evt_id; +#[doc = "CH36_TASK_ID (rw) register accessor: Channel36 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch36_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch36_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch36_task_id`] module"] +pub type CH36_TASK_ID = crate::Reg; +#[doc = "Channel36 task id register"] +pub mod ch36_task_id; +#[doc = "CH37_EVT_ID (rw) register accessor: Channel37 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch37_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch37_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch37_evt_id`] module"] +pub type CH37_EVT_ID = crate::Reg; +#[doc = "Channel37 event id register"] +pub mod ch37_evt_id; +#[doc = "CH37_TASK_ID (rw) register accessor: Channel37 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch37_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch37_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch37_task_id`] module"] +pub type CH37_TASK_ID = crate::Reg; +#[doc = "Channel37 task id register"] +pub mod ch37_task_id; +#[doc = "CH38_EVT_ID (rw) register accessor: Channel38 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch38_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch38_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch38_evt_id`] module"] +pub type CH38_EVT_ID = crate::Reg; +#[doc = "Channel38 event id register"] +pub mod ch38_evt_id; +#[doc = "CH38_TASK_ID (rw) register accessor: Channel38 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch38_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch38_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch38_task_id`] module"] +pub type CH38_TASK_ID = crate::Reg; +#[doc = "Channel38 task id register"] +pub mod ch38_task_id; +#[doc = "CH39_EVT_ID (rw) register accessor: Channel39 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch39_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch39_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch39_evt_id`] module"] +pub type CH39_EVT_ID = crate::Reg; +#[doc = "Channel39 event id register"] +pub mod ch39_evt_id; +#[doc = "CH39_TASK_ID (rw) register accessor: Channel39 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch39_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch39_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch39_task_id`] module"] +pub type CH39_TASK_ID = crate::Reg; +#[doc = "Channel39 task id register"] +pub mod ch39_task_id; +#[doc = "CH40_EVT_ID (rw) register accessor: Channel40 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch40_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch40_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch40_evt_id`] module"] +pub type CH40_EVT_ID = crate::Reg; +#[doc = "Channel40 event id register"] +pub mod ch40_evt_id; +#[doc = "CH40_TASK_ID (rw) register accessor: Channel40 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch40_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch40_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch40_task_id`] module"] +pub type CH40_TASK_ID = crate::Reg; +#[doc = "Channel40 task id register"] +pub mod ch40_task_id; +#[doc = "CH41_EVT_ID (rw) register accessor: Channel41 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch41_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch41_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch41_evt_id`] module"] +pub type CH41_EVT_ID = crate::Reg; +#[doc = "Channel41 event id register"] +pub mod ch41_evt_id; +#[doc = "CH41_TASK_ID (rw) register accessor: Channel41 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch41_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch41_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch41_task_id`] module"] +pub type CH41_TASK_ID = crate::Reg; +#[doc = "Channel41 task id register"] +pub mod ch41_task_id; +#[doc = "CH42_EVT_ID (rw) register accessor: Channel42 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch42_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch42_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch42_evt_id`] module"] +pub type CH42_EVT_ID = crate::Reg; +#[doc = "Channel42 event id register"] +pub mod ch42_evt_id; +#[doc = "CH42_TASK_ID (rw) register accessor: Channel42 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch42_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch42_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch42_task_id`] module"] +pub type CH42_TASK_ID = crate::Reg; +#[doc = "Channel42 task id register"] +pub mod ch42_task_id; +#[doc = "CH43_EVT_ID (rw) register accessor: Channel43 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch43_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch43_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch43_evt_id`] module"] +pub type CH43_EVT_ID = crate::Reg; +#[doc = "Channel43 event id register"] +pub mod ch43_evt_id; +#[doc = "CH43_TASK_ID (rw) register accessor: Channel43 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch43_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch43_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch43_task_id`] module"] +pub type CH43_TASK_ID = crate::Reg; +#[doc = "Channel43 task id register"] +pub mod ch43_task_id; +#[doc = "CH44_EVT_ID (rw) register accessor: Channel44 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch44_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch44_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch44_evt_id`] module"] +pub type CH44_EVT_ID = crate::Reg; +#[doc = "Channel44 event id register"] +pub mod ch44_evt_id; +#[doc = "CH44_TASK_ID (rw) register accessor: Channel44 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch44_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch44_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch44_task_id`] module"] +pub type CH44_TASK_ID = crate::Reg; +#[doc = "Channel44 task id register"] +pub mod ch44_task_id; +#[doc = "CH45_EVT_ID (rw) register accessor: Channel45 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch45_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch45_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch45_evt_id`] module"] +pub type CH45_EVT_ID = crate::Reg; +#[doc = "Channel45 event id register"] +pub mod ch45_evt_id; +#[doc = "CH45_TASK_ID (rw) register accessor: Channel45 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch45_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch45_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch45_task_id`] module"] +pub type CH45_TASK_ID = crate::Reg; +#[doc = "Channel45 task id register"] +pub mod ch45_task_id; +#[doc = "CH46_EVT_ID (rw) register accessor: Channel46 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch46_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch46_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch46_evt_id`] module"] +pub type CH46_EVT_ID = crate::Reg; +#[doc = "Channel46 event id register"] +pub mod ch46_evt_id; +#[doc = "CH46_TASK_ID (rw) register accessor: Channel46 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch46_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch46_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch46_task_id`] module"] +pub type CH46_TASK_ID = crate::Reg; +#[doc = "Channel46 task id register"] +pub mod ch46_task_id; +#[doc = "CH47_EVT_ID (rw) register accessor: Channel47 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch47_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch47_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch47_evt_id`] module"] +pub type CH47_EVT_ID = crate::Reg; +#[doc = "Channel47 event id register"] +pub mod ch47_evt_id; +#[doc = "CH47_TASK_ID (rw) register accessor: Channel47 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch47_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch47_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch47_task_id`] module"] +pub type CH47_TASK_ID = crate::Reg; +#[doc = "Channel47 task id register"] +pub mod ch47_task_id; +#[doc = "CH48_EVT_ID (rw) register accessor: Channel48 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch48_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch48_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch48_evt_id`] module"] +pub type CH48_EVT_ID = crate::Reg; +#[doc = "Channel48 event id register"] +pub mod ch48_evt_id; +#[doc = "CH48_TASK_ID (rw) register accessor: Channel48 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch48_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch48_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch48_task_id`] module"] +pub type CH48_TASK_ID = crate::Reg; +#[doc = "Channel48 task id register"] +pub mod ch48_task_id; +#[doc = "CH49_EVT_ID (rw) register accessor: Channel49 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch49_evt_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch49_evt_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch49_evt_id`] module"] +pub type CH49_EVT_ID = crate::Reg; +#[doc = "Channel49 event id register"] +pub mod ch49_evt_id; +#[doc = "CH49_TASK_ID (rw) register accessor: Channel49 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch49_task_id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch49_task_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch49_task_id`] module"] +pub type CH49_TASK_ID = crate::Reg; +#[doc = "Channel49 task id register"] +pub mod ch49_task_id; +#[doc = "EVT_ST0 (rw) register accessor: Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st0`] module"] +pub type EVT_ST0 = crate::Reg; +#[doc = "Events trigger status register"] +pub mod evt_st0; +#[doc = "EVT_ST0_CLR (w) register accessor: Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st0_clr`] module"] +pub type EVT_ST0_CLR = crate::Reg; +#[doc = "Events trigger status clear register"] +pub mod evt_st0_clr; +#[doc = "EVT_ST1 (rw) register accessor: Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st1`] module"] +pub type EVT_ST1 = crate::Reg; +#[doc = "Events trigger status register"] +pub mod evt_st1; +#[doc = "EVT_ST1_CLR (w) register accessor: Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st1_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st1_clr`] module"] +pub type EVT_ST1_CLR = crate::Reg; +#[doc = "Events trigger status clear register"] +pub mod evt_st1_clr; +#[doc = "EVT_ST2 (rw) register accessor: Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st2`] module"] +pub type EVT_ST2 = crate::Reg; +#[doc = "Events trigger status register"] +pub mod evt_st2; +#[doc = "EVT_ST2_CLR (w) register accessor: Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st2_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st2_clr`] module"] +pub type EVT_ST2_CLR = crate::Reg; +#[doc = "Events trigger status clear register"] +pub mod evt_st2_clr; +#[doc = "EVT_ST3 (rw) register accessor: Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st3`] module"] +pub type EVT_ST3 = crate::Reg; +#[doc = "Events trigger status register"] +pub mod evt_st3; +#[doc = "EVT_ST3_CLR (w) register accessor: Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st3_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st3_clr`] module"] +pub type EVT_ST3_CLR = crate::Reg; +#[doc = "Events trigger status clear register"] +pub mod evt_st3_clr; +#[doc = "EVT_ST4 (rw) register accessor: Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st4`] module"] +pub type EVT_ST4 = crate::Reg; +#[doc = "Events trigger status register"] +pub mod evt_st4; +#[doc = "EVT_ST4_CLR (w) register accessor: Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st4_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st4_clr`] module"] +pub type EVT_ST4_CLR = crate::Reg; +#[doc = "Events trigger status clear register"] +pub mod evt_st4_clr; +#[doc = "EVT_ST5 (rw) register accessor: Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st5`] module"] +pub type EVT_ST5 = crate::Reg; +#[doc = "Events trigger status register"] +pub mod evt_st5; +#[doc = "EVT_ST5_CLR (w) register accessor: Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st5_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st5_clr`] module"] +pub type EVT_ST5_CLR = crate::Reg; +#[doc = "Events trigger status clear register"] +pub mod evt_st5_clr; +#[doc = "EVT_ST6 (rw) register accessor: Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st6`] module"] +pub type EVT_ST6 = crate::Reg; +#[doc = "Events trigger status register"] +pub mod evt_st6; +#[doc = "EVT_ST6_CLR (w) register accessor: Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st6_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st6_clr`] module"] +pub type EVT_ST6_CLR = crate::Reg; +#[doc = "Events trigger status clear register"] +pub mod evt_st6_clr; +#[doc = "EVT_ST7 (rw) register accessor: Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st7`] module"] +pub type EVT_ST7 = crate::Reg; +#[doc = "Events trigger status register"] +pub mod evt_st7; +#[doc = "EVT_ST7_CLR (w) register accessor: Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st7_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_st7_clr`] module"] +pub type EVT_ST7_CLR = crate::Reg; +#[doc = "Events trigger status clear register"] +pub mod evt_st7_clr; +#[doc = "TASK_ST0 (rw) register accessor: Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st0`] module"] +pub type TASK_ST0 = crate::Reg; +#[doc = "Tasks trigger status register"] +pub mod task_st0; +#[doc = "TASK_ST0_CLR (w) register accessor: Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st0_clr`] module"] +pub type TASK_ST0_CLR = crate::Reg; +#[doc = "Tasks trigger status clear register"] +pub mod task_st0_clr; +#[doc = "TASK_ST1 (rw) register accessor: Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st1`] module"] +pub type TASK_ST1 = crate::Reg; +#[doc = "Tasks trigger status register"] +pub mod task_st1; +#[doc = "TASK_ST1_CLR (w) register accessor: Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st1_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st1_clr`] module"] +pub type TASK_ST1_CLR = crate::Reg; +#[doc = "Tasks trigger status clear register"] +pub mod task_st1_clr; +#[doc = "TASK_ST2 (rw) register accessor: Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st2`] module"] +pub type TASK_ST2 = crate::Reg; +#[doc = "Tasks trigger status register"] +pub mod task_st2; +#[doc = "TASK_ST2_CLR (w) register accessor: Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st2_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st2_clr`] module"] +pub type TASK_ST2_CLR = crate::Reg; +#[doc = "Tasks trigger status clear register"] +pub mod task_st2_clr; +#[doc = "TASK_ST3 (rw) register accessor: Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st3`] module"] +pub type TASK_ST3 = crate::Reg; +#[doc = "Tasks trigger status register"] +pub mod task_st3; +#[doc = "TASK_ST3_CLR (w) register accessor: Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st3_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st3_clr`] module"] +pub type TASK_ST3_CLR = crate::Reg; +#[doc = "Tasks trigger status clear register"] +pub mod task_st3_clr; +#[doc = "TASK_ST4 (rw) register accessor: Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st4`] module"] +pub type TASK_ST4 = crate::Reg; +#[doc = "Tasks trigger status register"] +pub mod task_st4; +#[doc = "TASK_ST4_CLR (w) register accessor: Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st4_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st4_clr`] module"] +pub type TASK_ST4_CLR = crate::Reg; +#[doc = "Tasks trigger status clear register"] +pub mod task_st4_clr; +#[doc = "TASK_ST5 (rw) register accessor: Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st5`] module"] +pub type TASK_ST5 = crate::Reg; +#[doc = "Tasks trigger status register"] +pub mod task_st5; +#[doc = "TASK_ST5_CLR (w) register accessor: Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st5_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st5_clr`] module"] +pub type TASK_ST5_CLR = crate::Reg; +#[doc = "Tasks trigger status clear register"] +pub mod task_st5_clr; +#[doc = "TASK_ST6 (rw) register accessor: Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st6`] module"] +pub type TASK_ST6 = crate::Reg; +#[doc = "Tasks trigger status register"] +pub mod task_st6; +#[doc = "TASK_ST6_CLR (w) register accessor: Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st6_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@task_st6_clr`] module"] +pub type TASK_ST6_CLR = crate::Reg; +#[doc = "Tasks trigger status clear register"] +pub mod task_st6_clr; +#[doc = "CLK_EN (rw) register accessor: ETM clock enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_en`] module"] +pub type CLK_EN = crate::Reg; +#[doc = "ETM clock enable register"] +pub mod clk_en; +#[doc = "DATE (rw) register accessor: ETM date register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "ETM date register"] +pub mod date; diff --git a/esp32p4/src/soc_etm/ch0_evt_id.rs b/esp32p4/src/soc_etm/ch0_evt_id.rs new file mode 100644 index 0000000000..ea25d23ef5 --- /dev/null +++ b/esp32p4/src/soc_etm/ch0_evt_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH0_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH0_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_EVT_ID` reader - Configures ch0_evt_id"] +pub type CH0_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH0_EVT_ID` writer - Configures ch0_evt_id"] +pub type CH0_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch0_evt_id"] + #[inline(always)] + pub fn ch0_evt_id(&self) -> CH0_EVT_ID_R { + CH0_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH0_EVT_ID") + .field("ch0_evt_id", &format_args!("{}", self.ch0_evt_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch0_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch0_evt_id(&mut self) -> CH0_EVT_ID_W { + CH0_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel0 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch0_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch0_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH0_EVT_ID_SPEC; +impl crate::RegisterSpec for CH0_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch0_evt_id::R`](R) reader structure"] +impl crate::Readable for CH0_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch0_evt_id::W`](W) writer structure"] +impl crate::Writable for CH0_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH0_EVT_ID to value 0"] +impl crate::Resettable for CH0_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch0_task_id.rs b/esp32p4/src/soc_etm/ch0_task_id.rs new file mode 100644 index 0000000000..746024e9f2 --- /dev/null +++ b/esp32p4/src/soc_etm/ch0_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH0_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH0_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_TASK_ID` reader - Configures ch0_task_id"] +pub type CH0_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH0_TASK_ID` writer - Configures ch0_task_id"] +pub type CH0_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch0_task_id"] + #[inline(always)] + pub fn ch0_task_id(&self) -> CH0_TASK_ID_R { + CH0_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH0_TASK_ID") + .field( + "ch0_task_id", + &format_args!("{}", self.ch0_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch0_task_id"] + #[inline(always)] + #[must_use] + pub fn ch0_task_id(&mut self) -> CH0_TASK_ID_W { + CH0_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel0 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch0_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch0_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH0_TASK_ID_SPEC; +impl crate::RegisterSpec for CH0_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch0_task_id::R`](R) reader structure"] +impl crate::Readable for CH0_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch0_task_id::W`](W) writer structure"] +impl crate::Writable for CH0_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH0_TASK_ID to value 0"] +impl crate::Resettable for CH0_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch10_evt_id.rs b/esp32p4/src/soc_etm/ch10_evt_id.rs new file mode 100644 index 0000000000..488feae39e --- /dev/null +++ b/esp32p4/src/soc_etm/ch10_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH10_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH10_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH10_EVT_ID` reader - Configures ch10_evt_id"] +pub type CH10_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH10_EVT_ID` writer - Configures ch10_evt_id"] +pub type CH10_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch10_evt_id"] + #[inline(always)] + pub fn ch10_evt_id(&self) -> CH10_EVT_ID_R { + CH10_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH10_EVT_ID") + .field( + "ch10_evt_id", + &format_args!("{}", self.ch10_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch10_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch10_evt_id(&mut self) -> CH10_EVT_ID_W { + CH10_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel10 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch10_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch10_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH10_EVT_ID_SPEC; +impl crate::RegisterSpec for CH10_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch10_evt_id::R`](R) reader structure"] +impl crate::Readable for CH10_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch10_evt_id::W`](W) writer structure"] +impl crate::Writable for CH10_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH10_EVT_ID to value 0"] +impl crate::Resettable for CH10_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch10_task_id.rs b/esp32p4/src/soc_etm/ch10_task_id.rs new file mode 100644 index 0000000000..9cc27df19f --- /dev/null +++ b/esp32p4/src/soc_etm/ch10_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH10_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH10_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH10_TASK_ID` reader - Configures ch10_task_id"] +pub type CH10_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH10_TASK_ID` writer - Configures ch10_task_id"] +pub type CH10_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch10_task_id"] + #[inline(always)] + pub fn ch10_task_id(&self) -> CH10_TASK_ID_R { + CH10_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH10_TASK_ID") + .field( + "ch10_task_id", + &format_args!("{}", self.ch10_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch10_task_id"] + #[inline(always)] + #[must_use] + pub fn ch10_task_id(&mut self) -> CH10_TASK_ID_W { + CH10_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel10 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch10_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch10_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH10_TASK_ID_SPEC; +impl crate::RegisterSpec for CH10_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch10_task_id::R`](R) reader structure"] +impl crate::Readable for CH10_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch10_task_id::W`](W) writer structure"] +impl crate::Writable for CH10_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH10_TASK_ID to value 0"] +impl crate::Resettable for CH10_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch11_evt_id.rs b/esp32p4/src/soc_etm/ch11_evt_id.rs new file mode 100644 index 0000000000..0eb7fb4abf --- /dev/null +++ b/esp32p4/src/soc_etm/ch11_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH11_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH11_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH11_EVT_ID` reader - Configures ch11_evt_id"] +pub type CH11_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH11_EVT_ID` writer - Configures ch11_evt_id"] +pub type CH11_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch11_evt_id"] + #[inline(always)] + pub fn ch11_evt_id(&self) -> CH11_EVT_ID_R { + CH11_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH11_EVT_ID") + .field( + "ch11_evt_id", + &format_args!("{}", self.ch11_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch11_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch11_evt_id(&mut self) -> CH11_EVT_ID_W { + CH11_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel11 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch11_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch11_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH11_EVT_ID_SPEC; +impl crate::RegisterSpec for CH11_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch11_evt_id::R`](R) reader structure"] +impl crate::Readable for CH11_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch11_evt_id::W`](W) writer structure"] +impl crate::Writable for CH11_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH11_EVT_ID to value 0"] +impl crate::Resettable for CH11_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch11_task_id.rs b/esp32p4/src/soc_etm/ch11_task_id.rs new file mode 100644 index 0000000000..7eae107881 --- /dev/null +++ b/esp32p4/src/soc_etm/ch11_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH11_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH11_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH11_TASK_ID` reader - Configures ch11_task_id"] +pub type CH11_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH11_TASK_ID` writer - Configures ch11_task_id"] +pub type CH11_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch11_task_id"] + #[inline(always)] + pub fn ch11_task_id(&self) -> CH11_TASK_ID_R { + CH11_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH11_TASK_ID") + .field( + "ch11_task_id", + &format_args!("{}", self.ch11_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch11_task_id"] + #[inline(always)] + #[must_use] + pub fn ch11_task_id(&mut self) -> CH11_TASK_ID_W { + CH11_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel11 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch11_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch11_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH11_TASK_ID_SPEC; +impl crate::RegisterSpec for CH11_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch11_task_id::R`](R) reader structure"] +impl crate::Readable for CH11_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch11_task_id::W`](W) writer structure"] +impl crate::Writable for CH11_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH11_TASK_ID to value 0"] +impl crate::Resettable for CH11_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch12_evt_id.rs b/esp32p4/src/soc_etm/ch12_evt_id.rs new file mode 100644 index 0000000000..f6ccb20807 --- /dev/null +++ b/esp32p4/src/soc_etm/ch12_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH12_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH12_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH12_EVT_ID` reader - Configures ch12_evt_id"] +pub type CH12_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH12_EVT_ID` writer - Configures ch12_evt_id"] +pub type CH12_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch12_evt_id"] + #[inline(always)] + pub fn ch12_evt_id(&self) -> CH12_EVT_ID_R { + CH12_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH12_EVT_ID") + .field( + "ch12_evt_id", + &format_args!("{}", self.ch12_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch12_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch12_evt_id(&mut self) -> CH12_EVT_ID_W { + CH12_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel12 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch12_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch12_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH12_EVT_ID_SPEC; +impl crate::RegisterSpec for CH12_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch12_evt_id::R`](R) reader structure"] +impl crate::Readable for CH12_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch12_evt_id::W`](W) writer structure"] +impl crate::Writable for CH12_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH12_EVT_ID to value 0"] +impl crate::Resettable for CH12_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch12_task_id.rs b/esp32p4/src/soc_etm/ch12_task_id.rs new file mode 100644 index 0000000000..3a9c1a655c --- /dev/null +++ b/esp32p4/src/soc_etm/ch12_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH12_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH12_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH12_TASK_ID` reader - Configures ch12_task_id"] +pub type CH12_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH12_TASK_ID` writer - Configures ch12_task_id"] +pub type CH12_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch12_task_id"] + #[inline(always)] + pub fn ch12_task_id(&self) -> CH12_TASK_ID_R { + CH12_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH12_TASK_ID") + .field( + "ch12_task_id", + &format_args!("{}", self.ch12_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch12_task_id"] + #[inline(always)] + #[must_use] + pub fn ch12_task_id(&mut self) -> CH12_TASK_ID_W { + CH12_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel12 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch12_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch12_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH12_TASK_ID_SPEC; +impl crate::RegisterSpec for CH12_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch12_task_id::R`](R) reader structure"] +impl crate::Readable for CH12_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch12_task_id::W`](W) writer structure"] +impl crate::Writable for CH12_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH12_TASK_ID to value 0"] +impl crate::Resettable for CH12_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch13_evt_id.rs b/esp32p4/src/soc_etm/ch13_evt_id.rs new file mode 100644 index 0000000000..131fa1418f --- /dev/null +++ b/esp32p4/src/soc_etm/ch13_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH13_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH13_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH13_EVT_ID` reader - Configures ch13_evt_id"] +pub type CH13_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH13_EVT_ID` writer - Configures ch13_evt_id"] +pub type CH13_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch13_evt_id"] + #[inline(always)] + pub fn ch13_evt_id(&self) -> CH13_EVT_ID_R { + CH13_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH13_EVT_ID") + .field( + "ch13_evt_id", + &format_args!("{}", self.ch13_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch13_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch13_evt_id(&mut self) -> CH13_EVT_ID_W { + CH13_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel13 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch13_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch13_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH13_EVT_ID_SPEC; +impl crate::RegisterSpec for CH13_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch13_evt_id::R`](R) reader structure"] +impl crate::Readable for CH13_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch13_evt_id::W`](W) writer structure"] +impl crate::Writable for CH13_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH13_EVT_ID to value 0"] +impl crate::Resettable for CH13_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch13_task_id.rs b/esp32p4/src/soc_etm/ch13_task_id.rs new file mode 100644 index 0000000000..d85e600248 --- /dev/null +++ b/esp32p4/src/soc_etm/ch13_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH13_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH13_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH13_TASK_ID` reader - Configures ch13_task_id"] +pub type CH13_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH13_TASK_ID` writer - Configures ch13_task_id"] +pub type CH13_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch13_task_id"] + #[inline(always)] + pub fn ch13_task_id(&self) -> CH13_TASK_ID_R { + CH13_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH13_TASK_ID") + .field( + "ch13_task_id", + &format_args!("{}", self.ch13_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch13_task_id"] + #[inline(always)] + #[must_use] + pub fn ch13_task_id(&mut self) -> CH13_TASK_ID_W { + CH13_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel13 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch13_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch13_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH13_TASK_ID_SPEC; +impl crate::RegisterSpec for CH13_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch13_task_id::R`](R) reader structure"] +impl crate::Readable for CH13_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch13_task_id::W`](W) writer structure"] +impl crate::Writable for CH13_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH13_TASK_ID to value 0"] +impl crate::Resettable for CH13_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch14_evt_id.rs b/esp32p4/src/soc_etm/ch14_evt_id.rs new file mode 100644 index 0000000000..c0cca267f0 --- /dev/null +++ b/esp32p4/src/soc_etm/ch14_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH14_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH14_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH14_EVT_ID` reader - Configures ch14_evt_id"] +pub type CH14_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH14_EVT_ID` writer - Configures ch14_evt_id"] +pub type CH14_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch14_evt_id"] + #[inline(always)] + pub fn ch14_evt_id(&self) -> CH14_EVT_ID_R { + CH14_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH14_EVT_ID") + .field( + "ch14_evt_id", + &format_args!("{}", self.ch14_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch14_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch14_evt_id(&mut self) -> CH14_EVT_ID_W { + CH14_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel14 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch14_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch14_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH14_EVT_ID_SPEC; +impl crate::RegisterSpec for CH14_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch14_evt_id::R`](R) reader structure"] +impl crate::Readable for CH14_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch14_evt_id::W`](W) writer structure"] +impl crate::Writable for CH14_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH14_EVT_ID to value 0"] +impl crate::Resettable for CH14_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch14_task_id.rs b/esp32p4/src/soc_etm/ch14_task_id.rs new file mode 100644 index 0000000000..7af634d31d --- /dev/null +++ b/esp32p4/src/soc_etm/ch14_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH14_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH14_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH14_TASK_ID` reader - Configures ch14_task_id"] +pub type CH14_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH14_TASK_ID` writer - Configures ch14_task_id"] +pub type CH14_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch14_task_id"] + #[inline(always)] + pub fn ch14_task_id(&self) -> CH14_TASK_ID_R { + CH14_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH14_TASK_ID") + .field( + "ch14_task_id", + &format_args!("{}", self.ch14_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch14_task_id"] + #[inline(always)] + #[must_use] + pub fn ch14_task_id(&mut self) -> CH14_TASK_ID_W { + CH14_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel14 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch14_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch14_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH14_TASK_ID_SPEC; +impl crate::RegisterSpec for CH14_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch14_task_id::R`](R) reader structure"] +impl crate::Readable for CH14_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch14_task_id::W`](W) writer structure"] +impl crate::Writable for CH14_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH14_TASK_ID to value 0"] +impl crate::Resettable for CH14_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch15_evt_id.rs b/esp32p4/src/soc_etm/ch15_evt_id.rs new file mode 100644 index 0000000000..08a97b2576 --- /dev/null +++ b/esp32p4/src/soc_etm/ch15_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH15_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH15_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH15_EVT_ID` reader - Configures ch15_evt_id"] +pub type CH15_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH15_EVT_ID` writer - Configures ch15_evt_id"] +pub type CH15_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch15_evt_id"] + #[inline(always)] + pub fn ch15_evt_id(&self) -> CH15_EVT_ID_R { + CH15_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH15_EVT_ID") + .field( + "ch15_evt_id", + &format_args!("{}", self.ch15_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch15_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch15_evt_id(&mut self) -> CH15_EVT_ID_W { + CH15_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel15 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch15_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch15_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH15_EVT_ID_SPEC; +impl crate::RegisterSpec for CH15_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch15_evt_id::R`](R) reader structure"] +impl crate::Readable for CH15_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch15_evt_id::W`](W) writer structure"] +impl crate::Writable for CH15_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH15_EVT_ID to value 0"] +impl crate::Resettable for CH15_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch15_task_id.rs b/esp32p4/src/soc_etm/ch15_task_id.rs new file mode 100644 index 0000000000..eaa69d3971 --- /dev/null +++ b/esp32p4/src/soc_etm/ch15_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH15_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH15_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH15_TASK_ID` reader - Configures ch15_task_id"] +pub type CH15_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH15_TASK_ID` writer - Configures ch15_task_id"] +pub type CH15_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch15_task_id"] + #[inline(always)] + pub fn ch15_task_id(&self) -> CH15_TASK_ID_R { + CH15_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH15_TASK_ID") + .field( + "ch15_task_id", + &format_args!("{}", self.ch15_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch15_task_id"] + #[inline(always)] + #[must_use] + pub fn ch15_task_id(&mut self) -> CH15_TASK_ID_W { + CH15_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel15 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch15_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch15_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH15_TASK_ID_SPEC; +impl crate::RegisterSpec for CH15_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch15_task_id::R`](R) reader structure"] +impl crate::Readable for CH15_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch15_task_id::W`](W) writer structure"] +impl crate::Writable for CH15_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH15_TASK_ID to value 0"] +impl crate::Resettable for CH15_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch16_evt_id.rs b/esp32p4/src/soc_etm/ch16_evt_id.rs new file mode 100644 index 0000000000..33d90be000 --- /dev/null +++ b/esp32p4/src/soc_etm/ch16_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH16_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH16_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH16_EVT_ID` reader - Configures ch16_evt_id"] +pub type CH16_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH16_EVT_ID` writer - Configures ch16_evt_id"] +pub type CH16_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch16_evt_id"] + #[inline(always)] + pub fn ch16_evt_id(&self) -> CH16_EVT_ID_R { + CH16_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH16_EVT_ID") + .field( + "ch16_evt_id", + &format_args!("{}", self.ch16_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch16_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch16_evt_id(&mut self) -> CH16_EVT_ID_W { + CH16_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel16 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch16_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch16_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH16_EVT_ID_SPEC; +impl crate::RegisterSpec for CH16_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch16_evt_id::R`](R) reader structure"] +impl crate::Readable for CH16_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch16_evt_id::W`](W) writer structure"] +impl crate::Writable for CH16_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH16_EVT_ID to value 0"] +impl crate::Resettable for CH16_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch16_task_id.rs b/esp32p4/src/soc_etm/ch16_task_id.rs new file mode 100644 index 0000000000..a5a04761f9 --- /dev/null +++ b/esp32p4/src/soc_etm/ch16_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH16_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH16_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH16_TASK_ID` reader - Configures ch16_task_id"] +pub type CH16_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH16_TASK_ID` writer - Configures ch16_task_id"] +pub type CH16_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch16_task_id"] + #[inline(always)] + pub fn ch16_task_id(&self) -> CH16_TASK_ID_R { + CH16_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH16_TASK_ID") + .field( + "ch16_task_id", + &format_args!("{}", self.ch16_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch16_task_id"] + #[inline(always)] + #[must_use] + pub fn ch16_task_id(&mut self) -> CH16_TASK_ID_W { + CH16_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel16 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch16_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch16_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH16_TASK_ID_SPEC; +impl crate::RegisterSpec for CH16_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch16_task_id::R`](R) reader structure"] +impl crate::Readable for CH16_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch16_task_id::W`](W) writer structure"] +impl crate::Writable for CH16_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH16_TASK_ID to value 0"] +impl crate::Resettable for CH16_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch17_evt_id.rs b/esp32p4/src/soc_etm/ch17_evt_id.rs new file mode 100644 index 0000000000..90f90d795a --- /dev/null +++ b/esp32p4/src/soc_etm/ch17_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH17_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH17_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH17_EVT_ID` reader - Configures ch17_evt_id"] +pub type CH17_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH17_EVT_ID` writer - Configures ch17_evt_id"] +pub type CH17_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch17_evt_id"] + #[inline(always)] + pub fn ch17_evt_id(&self) -> CH17_EVT_ID_R { + CH17_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH17_EVT_ID") + .field( + "ch17_evt_id", + &format_args!("{}", self.ch17_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch17_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch17_evt_id(&mut self) -> CH17_EVT_ID_W { + CH17_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel17 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch17_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch17_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH17_EVT_ID_SPEC; +impl crate::RegisterSpec for CH17_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch17_evt_id::R`](R) reader structure"] +impl crate::Readable for CH17_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch17_evt_id::W`](W) writer structure"] +impl crate::Writable for CH17_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH17_EVT_ID to value 0"] +impl crate::Resettable for CH17_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch17_task_id.rs b/esp32p4/src/soc_etm/ch17_task_id.rs new file mode 100644 index 0000000000..938c52987a --- /dev/null +++ b/esp32p4/src/soc_etm/ch17_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH17_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH17_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH17_TASK_ID` reader - Configures ch17_task_id"] +pub type CH17_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH17_TASK_ID` writer - Configures ch17_task_id"] +pub type CH17_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch17_task_id"] + #[inline(always)] + pub fn ch17_task_id(&self) -> CH17_TASK_ID_R { + CH17_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH17_TASK_ID") + .field( + "ch17_task_id", + &format_args!("{}", self.ch17_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch17_task_id"] + #[inline(always)] + #[must_use] + pub fn ch17_task_id(&mut self) -> CH17_TASK_ID_W { + CH17_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel17 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch17_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch17_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH17_TASK_ID_SPEC; +impl crate::RegisterSpec for CH17_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch17_task_id::R`](R) reader structure"] +impl crate::Readable for CH17_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch17_task_id::W`](W) writer structure"] +impl crate::Writable for CH17_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH17_TASK_ID to value 0"] +impl crate::Resettable for CH17_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch18_evt_id.rs b/esp32p4/src/soc_etm/ch18_evt_id.rs new file mode 100644 index 0000000000..2fd5c30587 --- /dev/null +++ b/esp32p4/src/soc_etm/ch18_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH18_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH18_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH18_EVT_ID` reader - Configures ch18_evt_id"] +pub type CH18_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH18_EVT_ID` writer - Configures ch18_evt_id"] +pub type CH18_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch18_evt_id"] + #[inline(always)] + pub fn ch18_evt_id(&self) -> CH18_EVT_ID_R { + CH18_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH18_EVT_ID") + .field( + "ch18_evt_id", + &format_args!("{}", self.ch18_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch18_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch18_evt_id(&mut self) -> CH18_EVT_ID_W { + CH18_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel18 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch18_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch18_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH18_EVT_ID_SPEC; +impl crate::RegisterSpec for CH18_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch18_evt_id::R`](R) reader structure"] +impl crate::Readable for CH18_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch18_evt_id::W`](W) writer structure"] +impl crate::Writable for CH18_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH18_EVT_ID to value 0"] +impl crate::Resettable for CH18_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch18_task_id.rs b/esp32p4/src/soc_etm/ch18_task_id.rs new file mode 100644 index 0000000000..83ec014516 --- /dev/null +++ b/esp32p4/src/soc_etm/ch18_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH18_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH18_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH18_TASK_ID` reader - Configures ch18_task_id"] +pub type CH18_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH18_TASK_ID` writer - Configures ch18_task_id"] +pub type CH18_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch18_task_id"] + #[inline(always)] + pub fn ch18_task_id(&self) -> CH18_TASK_ID_R { + CH18_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH18_TASK_ID") + .field( + "ch18_task_id", + &format_args!("{}", self.ch18_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch18_task_id"] + #[inline(always)] + #[must_use] + pub fn ch18_task_id(&mut self) -> CH18_TASK_ID_W { + CH18_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel18 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch18_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch18_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH18_TASK_ID_SPEC; +impl crate::RegisterSpec for CH18_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch18_task_id::R`](R) reader structure"] +impl crate::Readable for CH18_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch18_task_id::W`](W) writer structure"] +impl crate::Writable for CH18_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH18_TASK_ID to value 0"] +impl crate::Resettable for CH18_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch19_evt_id.rs b/esp32p4/src/soc_etm/ch19_evt_id.rs new file mode 100644 index 0000000000..3826d7a0de --- /dev/null +++ b/esp32p4/src/soc_etm/ch19_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH19_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH19_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH19_EVT_ID` reader - Configures ch19_evt_id"] +pub type CH19_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH19_EVT_ID` writer - Configures ch19_evt_id"] +pub type CH19_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch19_evt_id"] + #[inline(always)] + pub fn ch19_evt_id(&self) -> CH19_EVT_ID_R { + CH19_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH19_EVT_ID") + .field( + "ch19_evt_id", + &format_args!("{}", self.ch19_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch19_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch19_evt_id(&mut self) -> CH19_EVT_ID_W { + CH19_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel19 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch19_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch19_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH19_EVT_ID_SPEC; +impl crate::RegisterSpec for CH19_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch19_evt_id::R`](R) reader structure"] +impl crate::Readable for CH19_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch19_evt_id::W`](W) writer structure"] +impl crate::Writable for CH19_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH19_EVT_ID to value 0"] +impl crate::Resettable for CH19_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch19_task_id.rs b/esp32p4/src/soc_etm/ch19_task_id.rs new file mode 100644 index 0000000000..d4ddd679d6 --- /dev/null +++ b/esp32p4/src/soc_etm/ch19_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH19_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH19_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH19_TASK_ID` reader - Configures ch19_task_id"] +pub type CH19_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH19_TASK_ID` writer - Configures ch19_task_id"] +pub type CH19_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch19_task_id"] + #[inline(always)] + pub fn ch19_task_id(&self) -> CH19_TASK_ID_R { + CH19_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH19_TASK_ID") + .field( + "ch19_task_id", + &format_args!("{}", self.ch19_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch19_task_id"] + #[inline(always)] + #[must_use] + pub fn ch19_task_id(&mut self) -> CH19_TASK_ID_W { + CH19_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel19 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch19_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch19_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH19_TASK_ID_SPEC; +impl crate::RegisterSpec for CH19_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch19_task_id::R`](R) reader structure"] +impl crate::Readable for CH19_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch19_task_id::W`](W) writer structure"] +impl crate::Writable for CH19_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH19_TASK_ID to value 0"] +impl crate::Resettable for CH19_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch1_evt_id.rs b/esp32p4/src/soc_etm/ch1_evt_id.rs new file mode 100644 index 0000000000..8d0d928349 --- /dev/null +++ b/esp32p4/src/soc_etm/ch1_evt_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH1_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_EVT_ID` reader - Configures ch1_evt_id"] +pub type CH1_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH1_EVT_ID` writer - Configures ch1_evt_id"] +pub type CH1_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch1_evt_id"] + #[inline(always)] + pub fn ch1_evt_id(&self) -> CH1_EVT_ID_R { + CH1_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_EVT_ID") + .field("ch1_evt_id", &format_args!("{}", self.ch1_evt_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch1_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch1_evt_id(&mut self) -> CH1_EVT_ID_W { + CH1_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel1 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_EVT_ID_SPEC; +impl crate::RegisterSpec for CH1_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_evt_id::R`](R) reader structure"] +impl crate::Readable for CH1_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_evt_id::W`](W) writer structure"] +impl crate::Writable for CH1_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_EVT_ID to value 0"] +impl crate::Resettable for CH1_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch1_task_id.rs b/esp32p4/src/soc_etm/ch1_task_id.rs new file mode 100644 index 0000000000..f2f07883f2 --- /dev/null +++ b/esp32p4/src/soc_etm/ch1_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH1_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_TASK_ID` reader - Configures ch1_task_id"] +pub type CH1_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH1_TASK_ID` writer - Configures ch1_task_id"] +pub type CH1_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch1_task_id"] + #[inline(always)] + pub fn ch1_task_id(&self) -> CH1_TASK_ID_R { + CH1_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH1_TASK_ID") + .field( + "ch1_task_id", + &format_args!("{}", self.ch1_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch1_task_id"] + #[inline(always)] + #[must_use] + pub fn ch1_task_id(&mut self) -> CH1_TASK_ID_W { + CH1_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel1 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch1_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch1_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_TASK_ID_SPEC; +impl crate::RegisterSpec for CH1_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_task_id::R`](R) reader structure"] +impl crate::Readable for CH1_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_task_id::W`](W) writer structure"] +impl crate::Writable for CH1_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH1_TASK_ID to value 0"] +impl crate::Resettable for CH1_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch20_evt_id.rs b/esp32p4/src/soc_etm/ch20_evt_id.rs new file mode 100644 index 0000000000..a30c2ac939 --- /dev/null +++ b/esp32p4/src/soc_etm/ch20_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH20_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH20_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH20_EVT_ID` reader - Configures ch20_evt_id"] +pub type CH20_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH20_EVT_ID` writer - Configures ch20_evt_id"] +pub type CH20_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch20_evt_id"] + #[inline(always)] + pub fn ch20_evt_id(&self) -> CH20_EVT_ID_R { + CH20_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH20_EVT_ID") + .field( + "ch20_evt_id", + &format_args!("{}", self.ch20_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch20_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch20_evt_id(&mut self) -> CH20_EVT_ID_W { + CH20_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel20 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch20_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch20_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH20_EVT_ID_SPEC; +impl crate::RegisterSpec for CH20_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch20_evt_id::R`](R) reader structure"] +impl crate::Readable for CH20_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch20_evt_id::W`](W) writer structure"] +impl crate::Writable for CH20_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH20_EVT_ID to value 0"] +impl crate::Resettable for CH20_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch20_task_id.rs b/esp32p4/src/soc_etm/ch20_task_id.rs new file mode 100644 index 0000000000..ab6341bffa --- /dev/null +++ b/esp32p4/src/soc_etm/ch20_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH20_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH20_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH20_TASK_ID` reader - Configures ch20_task_id"] +pub type CH20_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH20_TASK_ID` writer - Configures ch20_task_id"] +pub type CH20_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch20_task_id"] + #[inline(always)] + pub fn ch20_task_id(&self) -> CH20_TASK_ID_R { + CH20_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH20_TASK_ID") + .field( + "ch20_task_id", + &format_args!("{}", self.ch20_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch20_task_id"] + #[inline(always)] + #[must_use] + pub fn ch20_task_id(&mut self) -> CH20_TASK_ID_W { + CH20_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel20 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch20_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch20_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH20_TASK_ID_SPEC; +impl crate::RegisterSpec for CH20_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch20_task_id::R`](R) reader structure"] +impl crate::Readable for CH20_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch20_task_id::W`](W) writer structure"] +impl crate::Writable for CH20_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH20_TASK_ID to value 0"] +impl crate::Resettable for CH20_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch21_evt_id.rs b/esp32p4/src/soc_etm/ch21_evt_id.rs new file mode 100644 index 0000000000..cfb7f3f88a --- /dev/null +++ b/esp32p4/src/soc_etm/ch21_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH21_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH21_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH21_EVT_ID` reader - Configures ch21_evt_id"] +pub type CH21_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH21_EVT_ID` writer - Configures ch21_evt_id"] +pub type CH21_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch21_evt_id"] + #[inline(always)] + pub fn ch21_evt_id(&self) -> CH21_EVT_ID_R { + CH21_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH21_EVT_ID") + .field( + "ch21_evt_id", + &format_args!("{}", self.ch21_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch21_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch21_evt_id(&mut self) -> CH21_EVT_ID_W { + CH21_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel21 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch21_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch21_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH21_EVT_ID_SPEC; +impl crate::RegisterSpec for CH21_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch21_evt_id::R`](R) reader structure"] +impl crate::Readable for CH21_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch21_evt_id::W`](W) writer structure"] +impl crate::Writable for CH21_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH21_EVT_ID to value 0"] +impl crate::Resettable for CH21_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch21_task_id.rs b/esp32p4/src/soc_etm/ch21_task_id.rs new file mode 100644 index 0000000000..e3d4419deb --- /dev/null +++ b/esp32p4/src/soc_etm/ch21_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH21_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH21_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH21_TASK_ID` reader - Configures ch21_task_id"] +pub type CH21_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH21_TASK_ID` writer - Configures ch21_task_id"] +pub type CH21_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch21_task_id"] + #[inline(always)] + pub fn ch21_task_id(&self) -> CH21_TASK_ID_R { + CH21_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH21_TASK_ID") + .field( + "ch21_task_id", + &format_args!("{}", self.ch21_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch21_task_id"] + #[inline(always)] + #[must_use] + pub fn ch21_task_id(&mut self) -> CH21_TASK_ID_W { + CH21_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel21 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch21_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch21_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH21_TASK_ID_SPEC; +impl crate::RegisterSpec for CH21_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch21_task_id::R`](R) reader structure"] +impl crate::Readable for CH21_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch21_task_id::W`](W) writer structure"] +impl crate::Writable for CH21_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH21_TASK_ID to value 0"] +impl crate::Resettable for CH21_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch22_evt_id.rs b/esp32p4/src/soc_etm/ch22_evt_id.rs new file mode 100644 index 0000000000..b11ded7d5d --- /dev/null +++ b/esp32p4/src/soc_etm/ch22_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH22_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH22_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH22_EVT_ID` reader - Configures ch22_evt_id"] +pub type CH22_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH22_EVT_ID` writer - Configures ch22_evt_id"] +pub type CH22_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch22_evt_id"] + #[inline(always)] + pub fn ch22_evt_id(&self) -> CH22_EVT_ID_R { + CH22_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH22_EVT_ID") + .field( + "ch22_evt_id", + &format_args!("{}", self.ch22_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch22_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch22_evt_id(&mut self) -> CH22_EVT_ID_W { + CH22_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel22 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch22_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch22_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH22_EVT_ID_SPEC; +impl crate::RegisterSpec for CH22_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch22_evt_id::R`](R) reader structure"] +impl crate::Readable for CH22_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch22_evt_id::W`](W) writer structure"] +impl crate::Writable for CH22_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH22_EVT_ID to value 0"] +impl crate::Resettable for CH22_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch22_task_id.rs b/esp32p4/src/soc_etm/ch22_task_id.rs new file mode 100644 index 0000000000..89cf3351bc --- /dev/null +++ b/esp32p4/src/soc_etm/ch22_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH22_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH22_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH22_TASK_ID` reader - Configures ch22_task_id"] +pub type CH22_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH22_TASK_ID` writer - Configures ch22_task_id"] +pub type CH22_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch22_task_id"] + #[inline(always)] + pub fn ch22_task_id(&self) -> CH22_TASK_ID_R { + CH22_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH22_TASK_ID") + .field( + "ch22_task_id", + &format_args!("{}", self.ch22_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch22_task_id"] + #[inline(always)] + #[must_use] + pub fn ch22_task_id(&mut self) -> CH22_TASK_ID_W { + CH22_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel22 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch22_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch22_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH22_TASK_ID_SPEC; +impl crate::RegisterSpec for CH22_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch22_task_id::R`](R) reader structure"] +impl crate::Readable for CH22_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch22_task_id::W`](W) writer structure"] +impl crate::Writable for CH22_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH22_TASK_ID to value 0"] +impl crate::Resettable for CH22_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch23_evt_id.rs b/esp32p4/src/soc_etm/ch23_evt_id.rs new file mode 100644 index 0000000000..8a44d689a5 --- /dev/null +++ b/esp32p4/src/soc_etm/ch23_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH23_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH23_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH23_EVT_ID` reader - Configures ch23_evt_id"] +pub type CH23_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH23_EVT_ID` writer - Configures ch23_evt_id"] +pub type CH23_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch23_evt_id"] + #[inline(always)] + pub fn ch23_evt_id(&self) -> CH23_EVT_ID_R { + CH23_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH23_EVT_ID") + .field( + "ch23_evt_id", + &format_args!("{}", self.ch23_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch23_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch23_evt_id(&mut self) -> CH23_EVT_ID_W { + CH23_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel23 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch23_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch23_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH23_EVT_ID_SPEC; +impl crate::RegisterSpec for CH23_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch23_evt_id::R`](R) reader structure"] +impl crate::Readable for CH23_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch23_evt_id::W`](W) writer structure"] +impl crate::Writable for CH23_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH23_EVT_ID to value 0"] +impl crate::Resettable for CH23_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch23_task_id.rs b/esp32p4/src/soc_etm/ch23_task_id.rs new file mode 100644 index 0000000000..732acdc5b0 --- /dev/null +++ b/esp32p4/src/soc_etm/ch23_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH23_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH23_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH23_TASK_ID` reader - Configures ch23_task_id"] +pub type CH23_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH23_TASK_ID` writer - Configures ch23_task_id"] +pub type CH23_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch23_task_id"] + #[inline(always)] + pub fn ch23_task_id(&self) -> CH23_TASK_ID_R { + CH23_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH23_TASK_ID") + .field( + "ch23_task_id", + &format_args!("{}", self.ch23_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch23_task_id"] + #[inline(always)] + #[must_use] + pub fn ch23_task_id(&mut self) -> CH23_TASK_ID_W { + CH23_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel23 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch23_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch23_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH23_TASK_ID_SPEC; +impl crate::RegisterSpec for CH23_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch23_task_id::R`](R) reader structure"] +impl crate::Readable for CH23_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch23_task_id::W`](W) writer structure"] +impl crate::Writable for CH23_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH23_TASK_ID to value 0"] +impl crate::Resettable for CH23_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch24_evt_id.rs b/esp32p4/src/soc_etm/ch24_evt_id.rs new file mode 100644 index 0000000000..700c9ed9d2 --- /dev/null +++ b/esp32p4/src/soc_etm/ch24_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH24_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH24_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH24_EVT_ID` reader - Configures ch24_evt_id"] +pub type CH24_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH24_EVT_ID` writer - Configures ch24_evt_id"] +pub type CH24_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch24_evt_id"] + #[inline(always)] + pub fn ch24_evt_id(&self) -> CH24_EVT_ID_R { + CH24_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH24_EVT_ID") + .field( + "ch24_evt_id", + &format_args!("{}", self.ch24_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch24_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch24_evt_id(&mut self) -> CH24_EVT_ID_W { + CH24_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel24 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch24_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch24_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH24_EVT_ID_SPEC; +impl crate::RegisterSpec for CH24_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch24_evt_id::R`](R) reader structure"] +impl crate::Readable for CH24_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch24_evt_id::W`](W) writer structure"] +impl crate::Writable for CH24_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH24_EVT_ID to value 0"] +impl crate::Resettable for CH24_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch24_task_id.rs b/esp32p4/src/soc_etm/ch24_task_id.rs new file mode 100644 index 0000000000..03be48425b --- /dev/null +++ b/esp32p4/src/soc_etm/ch24_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH24_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH24_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH24_TASK_ID` reader - Configures ch24_task_id"] +pub type CH24_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH24_TASK_ID` writer - Configures ch24_task_id"] +pub type CH24_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch24_task_id"] + #[inline(always)] + pub fn ch24_task_id(&self) -> CH24_TASK_ID_R { + CH24_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH24_TASK_ID") + .field( + "ch24_task_id", + &format_args!("{}", self.ch24_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch24_task_id"] + #[inline(always)] + #[must_use] + pub fn ch24_task_id(&mut self) -> CH24_TASK_ID_W { + CH24_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel24 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch24_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch24_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH24_TASK_ID_SPEC; +impl crate::RegisterSpec for CH24_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch24_task_id::R`](R) reader structure"] +impl crate::Readable for CH24_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch24_task_id::W`](W) writer structure"] +impl crate::Writable for CH24_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH24_TASK_ID to value 0"] +impl crate::Resettable for CH24_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch25_evt_id.rs b/esp32p4/src/soc_etm/ch25_evt_id.rs new file mode 100644 index 0000000000..7792d356af --- /dev/null +++ b/esp32p4/src/soc_etm/ch25_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH25_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH25_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH25_EVT_ID` reader - Configures ch25_evt_id"] +pub type CH25_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH25_EVT_ID` writer - Configures ch25_evt_id"] +pub type CH25_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch25_evt_id"] + #[inline(always)] + pub fn ch25_evt_id(&self) -> CH25_EVT_ID_R { + CH25_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH25_EVT_ID") + .field( + "ch25_evt_id", + &format_args!("{}", self.ch25_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch25_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch25_evt_id(&mut self) -> CH25_EVT_ID_W { + CH25_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel25 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch25_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch25_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH25_EVT_ID_SPEC; +impl crate::RegisterSpec for CH25_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch25_evt_id::R`](R) reader structure"] +impl crate::Readable for CH25_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch25_evt_id::W`](W) writer structure"] +impl crate::Writable for CH25_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH25_EVT_ID to value 0"] +impl crate::Resettable for CH25_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch25_task_id.rs b/esp32p4/src/soc_etm/ch25_task_id.rs new file mode 100644 index 0000000000..f5c2dc99ac --- /dev/null +++ b/esp32p4/src/soc_etm/ch25_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH25_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH25_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH25_TASK_ID` reader - Configures ch25_task_id"] +pub type CH25_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH25_TASK_ID` writer - Configures ch25_task_id"] +pub type CH25_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch25_task_id"] + #[inline(always)] + pub fn ch25_task_id(&self) -> CH25_TASK_ID_R { + CH25_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH25_TASK_ID") + .field( + "ch25_task_id", + &format_args!("{}", self.ch25_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch25_task_id"] + #[inline(always)] + #[must_use] + pub fn ch25_task_id(&mut self) -> CH25_TASK_ID_W { + CH25_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel25 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch25_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch25_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH25_TASK_ID_SPEC; +impl crate::RegisterSpec for CH25_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch25_task_id::R`](R) reader structure"] +impl crate::Readable for CH25_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch25_task_id::W`](W) writer structure"] +impl crate::Writable for CH25_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH25_TASK_ID to value 0"] +impl crate::Resettable for CH25_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch26_evt_id.rs b/esp32p4/src/soc_etm/ch26_evt_id.rs new file mode 100644 index 0000000000..783fcee87d --- /dev/null +++ b/esp32p4/src/soc_etm/ch26_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH26_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH26_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH26_EVT_ID` reader - Configures ch26_evt_id"] +pub type CH26_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH26_EVT_ID` writer - Configures ch26_evt_id"] +pub type CH26_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch26_evt_id"] + #[inline(always)] + pub fn ch26_evt_id(&self) -> CH26_EVT_ID_R { + CH26_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH26_EVT_ID") + .field( + "ch26_evt_id", + &format_args!("{}", self.ch26_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch26_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch26_evt_id(&mut self) -> CH26_EVT_ID_W { + CH26_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel26 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch26_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch26_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH26_EVT_ID_SPEC; +impl crate::RegisterSpec for CH26_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch26_evt_id::R`](R) reader structure"] +impl crate::Readable for CH26_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch26_evt_id::W`](W) writer structure"] +impl crate::Writable for CH26_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH26_EVT_ID to value 0"] +impl crate::Resettable for CH26_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch26_task_id.rs b/esp32p4/src/soc_etm/ch26_task_id.rs new file mode 100644 index 0000000000..4d7ed1a7fc --- /dev/null +++ b/esp32p4/src/soc_etm/ch26_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH26_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH26_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH26_TASK_ID` reader - Configures ch26_task_id"] +pub type CH26_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH26_TASK_ID` writer - Configures ch26_task_id"] +pub type CH26_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch26_task_id"] + #[inline(always)] + pub fn ch26_task_id(&self) -> CH26_TASK_ID_R { + CH26_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH26_TASK_ID") + .field( + "ch26_task_id", + &format_args!("{}", self.ch26_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch26_task_id"] + #[inline(always)] + #[must_use] + pub fn ch26_task_id(&mut self) -> CH26_TASK_ID_W { + CH26_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel26 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch26_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch26_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH26_TASK_ID_SPEC; +impl crate::RegisterSpec for CH26_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch26_task_id::R`](R) reader structure"] +impl crate::Readable for CH26_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch26_task_id::W`](W) writer structure"] +impl crate::Writable for CH26_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH26_TASK_ID to value 0"] +impl crate::Resettable for CH26_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch27_evt_id.rs b/esp32p4/src/soc_etm/ch27_evt_id.rs new file mode 100644 index 0000000000..4d19006388 --- /dev/null +++ b/esp32p4/src/soc_etm/ch27_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH27_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH27_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH27_EVT_ID` reader - Configures ch27_evt_id"] +pub type CH27_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH27_EVT_ID` writer - Configures ch27_evt_id"] +pub type CH27_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch27_evt_id"] + #[inline(always)] + pub fn ch27_evt_id(&self) -> CH27_EVT_ID_R { + CH27_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH27_EVT_ID") + .field( + "ch27_evt_id", + &format_args!("{}", self.ch27_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch27_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch27_evt_id(&mut self) -> CH27_EVT_ID_W { + CH27_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel27 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch27_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch27_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH27_EVT_ID_SPEC; +impl crate::RegisterSpec for CH27_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch27_evt_id::R`](R) reader structure"] +impl crate::Readable for CH27_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch27_evt_id::W`](W) writer structure"] +impl crate::Writable for CH27_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH27_EVT_ID to value 0"] +impl crate::Resettable for CH27_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch27_task_id.rs b/esp32p4/src/soc_etm/ch27_task_id.rs new file mode 100644 index 0000000000..a9e4df9bfe --- /dev/null +++ b/esp32p4/src/soc_etm/ch27_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH27_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH27_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH27_TASK_ID` reader - Configures ch27_task_id"] +pub type CH27_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH27_TASK_ID` writer - Configures ch27_task_id"] +pub type CH27_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch27_task_id"] + #[inline(always)] + pub fn ch27_task_id(&self) -> CH27_TASK_ID_R { + CH27_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH27_TASK_ID") + .field( + "ch27_task_id", + &format_args!("{}", self.ch27_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch27_task_id"] + #[inline(always)] + #[must_use] + pub fn ch27_task_id(&mut self) -> CH27_TASK_ID_W { + CH27_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel27 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch27_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch27_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH27_TASK_ID_SPEC; +impl crate::RegisterSpec for CH27_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch27_task_id::R`](R) reader structure"] +impl crate::Readable for CH27_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch27_task_id::W`](W) writer structure"] +impl crate::Writable for CH27_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH27_TASK_ID to value 0"] +impl crate::Resettable for CH27_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch28_evt_id.rs b/esp32p4/src/soc_etm/ch28_evt_id.rs new file mode 100644 index 0000000000..d485329a5d --- /dev/null +++ b/esp32p4/src/soc_etm/ch28_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH28_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH28_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH28_EVT_ID` reader - Configures ch28_evt_id"] +pub type CH28_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH28_EVT_ID` writer - Configures ch28_evt_id"] +pub type CH28_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch28_evt_id"] + #[inline(always)] + pub fn ch28_evt_id(&self) -> CH28_EVT_ID_R { + CH28_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH28_EVT_ID") + .field( + "ch28_evt_id", + &format_args!("{}", self.ch28_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch28_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch28_evt_id(&mut self) -> CH28_EVT_ID_W { + CH28_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel28 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch28_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch28_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH28_EVT_ID_SPEC; +impl crate::RegisterSpec for CH28_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch28_evt_id::R`](R) reader structure"] +impl crate::Readable for CH28_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch28_evt_id::W`](W) writer structure"] +impl crate::Writable for CH28_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH28_EVT_ID to value 0"] +impl crate::Resettable for CH28_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch28_task_id.rs b/esp32p4/src/soc_etm/ch28_task_id.rs new file mode 100644 index 0000000000..ef4c14dd2b --- /dev/null +++ b/esp32p4/src/soc_etm/ch28_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH28_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH28_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH28_TASK_ID` reader - Configures ch28_task_id"] +pub type CH28_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH28_TASK_ID` writer - Configures ch28_task_id"] +pub type CH28_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch28_task_id"] + #[inline(always)] + pub fn ch28_task_id(&self) -> CH28_TASK_ID_R { + CH28_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH28_TASK_ID") + .field( + "ch28_task_id", + &format_args!("{}", self.ch28_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch28_task_id"] + #[inline(always)] + #[must_use] + pub fn ch28_task_id(&mut self) -> CH28_TASK_ID_W { + CH28_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel28 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch28_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch28_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH28_TASK_ID_SPEC; +impl crate::RegisterSpec for CH28_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch28_task_id::R`](R) reader structure"] +impl crate::Readable for CH28_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch28_task_id::W`](W) writer structure"] +impl crate::Writable for CH28_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH28_TASK_ID to value 0"] +impl crate::Resettable for CH28_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch29_evt_id.rs b/esp32p4/src/soc_etm/ch29_evt_id.rs new file mode 100644 index 0000000000..ec2057c5ba --- /dev/null +++ b/esp32p4/src/soc_etm/ch29_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH29_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH29_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH29_EVT_ID` reader - Configures ch29_evt_id"] +pub type CH29_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH29_EVT_ID` writer - Configures ch29_evt_id"] +pub type CH29_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch29_evt_id"] + #[inline(always)] + pub fn ch29_evt_id(&self) -> CH29_EVT_ID_R { + CH29_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH29_EVT_ID") + .field( + "ch29_evt_id", + &format_args!("{}", self.ch29_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch29_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch29_evt_id(&mut self) -> CH29_EVT_ID_W { + CH29_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel29 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch29_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch29_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH29_EVT_ID_SPEC; +impl crate::RegisterSpec for CH29_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch29_evt_id::R`](R) reader structure"] +impl crate::Readable for CH29_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch29_evt_id::W`](W) writer structure"] +impl crate::Writable for CH29_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH29_EVT_ID to value 0"] +impl crate::Resettable for CH29_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch29_task_id.rs b/esp32p4/src/soc_etm/ch29_task_id.rs new file mode 100644 index 0000000000..24c6e7dcb3 --- /dev/null +++ b/esp32p4/src/soc_etm/ch29_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH29_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH29_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH29_TASK_ID` reader - Configures ch29_task_id"] +pub type CH29_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH29_TASK_ID` writer - Configures ch29_task_id"] +pub type CH29_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch29_task_id"] + #[inline(always)] + pub fn ch29_task_id(&self) -> CH29_TASK_ID_R { + CH29_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH29_TASK_ID") + .field( + "ch29_task_id", + &format_args!("{}", self.ch29_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch29_task_id"] + #[inline(always)] + #[must_use] + pub fn ch29_task_id(&mut self) -> CH29_TASK_ID_W { + CH29_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel29 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch29_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch29_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH29_TASK_ID_SPEC; +impl crate::RegisterSpec for CH29_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch29_task_id::R`](R) reader structure"] +impl crate::Readable for CH29_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch29_task_id::W`](W) writer structure"] +impl crate::Writable for CH29_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH29_TASK_ID to value 0"] +impl crate::Resettable for CH29_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch2_evt_id.rs b/esp32p4/src/soc_etm/ch2_evt_id.rs new file mode 100644 index 0000000000..719c7440f8 --- /dev/null +++ b/esp32p4/src/soc_etm/ch2_evt_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH2_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_EVT_ID` reader - Configures ch2_evt_id"] +pub type CH2_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH2_EVT_ID` writer - Configures ch2_evt_id"] +pub type CH2_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch2_evt_id"] + #[inline(always)] + pub fn ch2_evt_id(&self) -> CH2_EVT_ID_R { + CH2_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_EVT_ID") + .field("ch2_evt_id", &format_args!("{}", self.ch2_evt_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch2_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch2_evt_id(&mut self) -> CH2_EVT_ID_W { + CH2_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel2 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_EVT_ID_SPEC; +impl crate::RegisterSpec for CH2_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_evt_id::R`](R) reader structure"] +impl crate::Readable for CH2_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_evt_id::W`](W) writer structure"] +impl crate::Writable for CH2_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_EVT_ID to value 0"] +impl crate::Resettable for CH2_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch2_task_id.rs b/esp32p4/src/soc_etm/ch2_task_id.rs new file mode 100644 index 0000000000..09b1e89e02 --- /dev/null +++ b/esp32p4/src/soc_etm/ch2_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH2_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_TASK_ID` reader - Configures ch2_task_id"] +pub type CH2_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH2_TASK_ID` writer - Configures ch2_task_id"] +pub type CH2_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch2_task_id"] + #[inline(always)] + pub fn ch2_task_id(&self) -> CH2_TASK_ID_R { + CH2_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH2_TASK_ID") + .field( + "ch2_task_id", + &format_args!("{}", self.ch2_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch2_task_id"] + #[inline(always)] + #[must_use] + pub fn ch2_task_id(&mut self) -> CH2_TASK_ID_W { + CH2_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel2 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch2_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch2_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_TASK_ID_SPEC; +impl crate::RegisterSpec for CH2_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_task_id::R`](R) reader structure"] +impl crate::Readable for CH2_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_task_id::W`](W) writer structure"] +impl crate::Writable for CH2_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH2_TASK_ID to value 0"] +impl crate::Resettable for CH2_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch30_evt_id.rs b/esp32p4/src/soc_etm/ch30_evt_id.rs new file mode 100644 index 0000000000..3a630ff868 --- /dev/null +++ b/esp32p4/src/soc_etm/ch30_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH30_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH30_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH30_EVT_ID` reader - Configures ch30_evt_id"] +pub type CH30_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH30_EVT_ID` writer - Configures ch30_evt_id"] +pub type CH30_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch30_evt_id"] + #[inline(always)] + pub fn ch30_evt_id(&self) -> CH30_EVT_ID_R { + CH30_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH30_EVT_ID") + .field( + "ch30_evt_id", + &format_args!("{}", self.ch30_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch30_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch30_evt_id(&mut self) -> CH30_EVT_ID_W { + CH30_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel30 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch30_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch30_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH30_EVT_ID_SPEC; +impl crate::RegisterSpec for CH30_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch30_evt_id::R`](R) reader structure"] +impl crate::Readable for CH30_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch30_evt_id::W`](W) writer structure"] +impl crate::Writable for CH30_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH30_EVT_ID to value 0"] +impl crate::Resettable for CH30_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch30_task_id.rs b/esp32p4/src/soc_etm/ch30_task_id.rs new file mode 100644 index 0000000000..807f7f9eb9 --- /dev/null +++ b/esp32p4/src/soc_etm/ch30_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH30_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH30_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH30_TASK_ID` reader - Configures ch30_task_id"] +pub type CH30_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH30_TASK_ID` writer - Configures ch30_task_id"] +pub type CH30_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch30_task_id"] + #[inline(always)] + pub fn ch30_task_id(&self) -> CH30_TASK_ID_R { + CH30_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH30_TASK_ID") + .field( + "ch30_task_id", + &format_args!("{}", self.ch30_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch30_task_id"] + #[inline(always)] + #[must_use] + pub fn ch30_task_id(&mut self) -> CH30_TASK_ID_W { + CH30_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel30 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch30_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch30_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH30_TASK_ID_SPEC; +impl crate::RegisterSpec for CH30_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch30_task_id::R`](R) reader structure"] +impl crate::Readable for CH30_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch30_task_id::W`](W) writer structure"] +impl crate::Writable for CH30_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH30_TASK_ID to value 0"] +impl crate::Resettable for CH30_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch31_evt_id.rs b/esp32p4/src/soc_etm/ch31_evt_id.rs new file mode 100644 index 0000000000..c6b717a03f --- /dev/null +++ b/esp32p4/src/soc_etm/ch31_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH31_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH31_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH31_EVT_ID` reader - Configures ch31_evt_id"] +pub type CH31_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH31_EVT_ID` writer - Configures ch31_evt_id"] +pub type CH31_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch31_evt_id"] + #[inline(always)] + pub fn ch31_evt_id(&self) -> CH31_EVT_ID_R { + CH31_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH31_EVT_ID") + .field( + "ch31_evt_id", + &format_args!("{}", self.ch31_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch31_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch31_evt_id(&mut self) -> CH31_EVT_ID_W { + CH31_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel31 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch31_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch31_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH31_EVT_ID_SPEC; +impl crate::RegisterSpec for CH31_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch31_evt_id::R`](R) reader structure"] +impl crate::Readable for CH31_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch31_evt_id::W`](W) writer structure"] +impl crate::Writable for CH31_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH31_EVT_ID to value 0"] +impl crate::Resettable for CH31_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch31_task_id.rs b/esp32p4/src/soc_etm/ch31_task_id.rs new file mode 100644 index 0000000000..94eda53419 --- /dev/null +++ b/esp32p4/src/soc_etm/ch31_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH31_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH31_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH31_TASK_ID` reader - Configures ch31_task_id"] +pub type CH31_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH31_TASK_ID` writer - Configures ch31_task_id"] +pub type CH31_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch31_task_id"] + #[inline(always)] + pub fn ch31_task_id(&self) -> CH31_TASK_ID_R { + CH31_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH31_TASK_ID") + .field( + "ch31_task_id", + &format_args!("{}", self.ch31_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch31_task_id"] + #[inline(always)] + #[must_use] + pub fn ch31_task_id(&mut self) -> CH31_TASK_ID_W { + CH31_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel31 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch31_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch31_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH31_TASK_ID_SPEC; +impl crate::RegisterSpec for CH31_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch31_task_id::R`](R) reader structure"] +impl crate::Readable for CH31_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch31_task_id::W`](W) writer structure"] +impl crate::Writable for CH31_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH31_TASK_ID to value 0"] +impl crate::Resettable for CH31_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch32_evt_id.rs b/esp32p4/src/soc_etm/ch32_evt_id.rs new file mode 100644 index 0000000000..c817db7c79 --- /dev/null +++ b/esp32p4/src/soc_etm/ch32_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH32_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH32_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH32_EVT_ID` reader - Configures ch32_evt_id"] +pub type CH32_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH32_EVT_ID` writer - Configures ch32_evt_id"] +pub type CH32_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch32_evt_id"] + #[inline(always)] + pub fn ch32_evt_id(&self) -> CH32_EVT_ID_R { + CH32_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH32_EVT_ID") + .field( + "ch32_evt_id", + &format_args!("{}", self.ch32_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch32_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch32_evt_id(&mut self) -> CH32_EVT_ID_W { + CH32_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel32 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch32_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch32_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH32_EVT_ID_SPEC; +impl crate::RegisterSpec for CH32_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch32_evt_id::R`](R) reader structure"] +impl crate::Readable for CH32_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch32_evt_id::W`](W) writer structure"] +impl crate::Writable for CH32_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH32_EVT_ID to value 0"] +impl crate::Resettable for CH32_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch32_task_id.rs b/esp32p4/src/soc_etm/ch32_task_id.rs new file mode 100644 index 0000000000..87a49d1abc --- /dev/null +++ b/esp32p4/src/soc_etm/ch32_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH32_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH32_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH32_TASK_ID` reader - Configures ch32_task_id"] +pub type CH32_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH32_TASK_ID` writer - Configures ch32_task_id"] +pub type CH32_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch32_task_id"] + #[inline(always)] + pub fn ch32_task_id(&self) -> CH32_TASK_ID_R { + CH32_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH32_TASK_ID") + .field( + "ch32_task_id", + &format_args!("{}", self.ch32_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch32_task_id"] + #[inline(always)] + #[must_use] + pub fn ch32_task_id(&mut self) -> CH32_TASK_ID_W { + CH32_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel32 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch32_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch32_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH32_TASK_ID_SPEC; +impl crate::RegisterSpec for CH32_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch32_task_id::R`](R) reader structure"] +impl crate::Readable for CH32_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch32_task_id::W`](W) writer structure"] +impl crate::Writable for CH32_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH32_TASK_ID to value 0"] +impl crate::Resettable for CH32_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch33_evt_id.rs b/esp32p4/src/soc_etm/ch33_evt_id.rs new file mode 100644 index 0000000000..c8966fec45 --- /dev/null +++ b/esp32p4/src/soc_etm/ch33_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH33_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH33_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH33_EVT_ID` reader - Configures ch33_evt_id"] +pub type CH33_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH33_EVT_ID` writer - Configures ch33_evt_id"] +pub type CH33_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch33_evt_id"] + #[inline(always)] + pub fn ch33_evt_id(&self) -> CH33_EVT_ID_R { + CH33_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH33_EVT_ID") + .field( + "ch33_evt_id", + &format_args!("{}", self.ch33_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch33_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch33_evt_id(&mut self) -> CH33_EVT_ID_W { + CH33_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel33 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch33_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch33_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH33_EVT_ID_SPEC; +impl crate::RegisterSpec for CH33_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch33_evt_id::R`](R) reader structure"] +impl crate::Readable for CH33_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch33_evt_id::W`](W) writer structure"] +impl crate::Writable for CH33_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH33_EVT_ID to value 0"] +impl crate::Resettable for CH33_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch33_task_id.rs b/esp32p4/src/soc_etm/ch33_task_id.rs new file mode 100644 index 0000000000..d65e174092 --- /dev/null +++ b/esp32p4/src/soc_etm/ch33_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH33_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH33_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH33_TASK_ID` reader - Configures ch33_task_id"] +pub type CH33_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH33_TASK_ID` writer - Configures ch33_task_id"] +pub type CH33_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch33_task_id"] + #[inline(always)] + pub fn ch33_task_id(&self) -> CH33_TASK_ID_R { + CH33_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH33_TASK_ID") + .field( + "ch33_task_id", + &format_args!("{}", self.ch33_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch33_task_id"] + #[inline(always)] + #[must_use] + pub fn ch33_task_id(&mut self) -> CH33_TASK_ID_W { + CH33_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel33 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch33_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch33_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH33_TASK_ID_SPEC; +impl crate::RegisterSpec for CH33_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch33_task_id::R`](R) reader structure"] +impl crate::Readable for CH33_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch33_task_id::W`](W) writer structure"] +impl crate::Writable for CH33_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH33_TASK_ID to value 0"] +impl crate::Resettable for CH33_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch34_evt_id.rs b/esp32p4/src/soc_etm/ch34_evt_id.rs new file mode 100644 index 0000000000..eb13cab4d3 --- /dev/null +++ b/esp32p4/src/soc_etm/ch34_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH34_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH34_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH34_EVT_ID` reader - Configures ch34_evt_id"] +pub type CH34_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH34_EVT_ID` writer - Configures ch34_evt_id"] +pub type CH34_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch34_evt_id"] + #[inline(always)] + pub fn ch34_evt_id(&self) -> CH34_EVT_ID_R { + CH34_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH34_EVT_ID") + .field( + "ch34_evt_id", + &format_args!("{}", self.ch34_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch34_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch34_evt_id(&mut self) -> CH34_EVT_ID_W { + CH34_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel34 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch34_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch34_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH34_EVT_ID_SPEC; +impl crate::RegisterSpec for CH34_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch34_evt_id::R`](R) reader structure"] +impl crate::Readable for CH34_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch34_evt_id::W`](W) writer structure"] +impl crate::Writable for CH34_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH34_EVT_ID to value 0"] +impl crate::Resettable for CH34_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch34_task_id.rs b/esp32p4/src/soc_etm/ch34_task_id.rs new file mode 100644 index 0000000000..4850fa366f --- /dev/null +++ b/esp32p4/src/soc_etm/ch34_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH34_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH34_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH34_TASK_ID` reader - Configures ch34_task_id"] +pub type CH34_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH34_TASK_ID` writer - Configures ch34_task_id"] +pub type CH34_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch34_task_id"] + #[inline(always)] + pub fn ch34_task_id(&self) -> CH34_TASK_ID_R { + CH34_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH34_TASK_ID") + .field( + "ch34_task_id", + &format_args!("{}", self.ch34_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch34_task_id"] + #[inline(always)] + #[must_use] + pub fn ch34_task_id(&mut self) -> CH34_TASK_ID_W { + CH34_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel34 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch34_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch34_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH34_TASK_ID_SPEC; +impl crate::RegisterSpec for CH34_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch34_task_id::R`](R) reader structure"] +impl crate::Readable for CH34_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch34_task_id::W`](W) writer structure"] +impl crate::Writable for CH34_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH34_TASK_ID to value 0"] +impl crate::Resettable for CH34_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch35_evt_id.rs b/esp32p4/src/soc_etm/ch35_evt_id.rs new file mode 100644 index 0000000000..99de2d324d --- /dev/null +++ b/esp32p4/src/soc_etm/ch35_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH35_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH35_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH35_EVT_ID` reader - Configures ch35_evt_id"] +pub type CH35_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH35_EVT_ID` writer - Configures ch35_evt_id"] +pub type CH35_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch35_evt_id"] + #[inline(always)] + pub fn ch35_evt_id(&self) -> CH35_EVT_ID_R { + CH35_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH35_EVT_ID") + .field( + "ch35_evt_id", + &format_args!("{}", self.ch35_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch35_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch35_evt_id(&mut self) -> CH35_EVT_ID_W { + CH35_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel35 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch35_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch35_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH35_EVT_ID_SPEC; +impl crate::RegisterSpec for CH35_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch35_evt_id::R`](R) reader structure"] +impl crate::Readable for CH35_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch35_evt_id::W`](W) writer structure"] +impl crate::Writable for CH35_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH35_EVT_ID to value 0"] +impl crate::Resettable for CH35_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch35_task_id.rs b/esp32p4/src/soc_etm/ch35_task_id.rs new file mode 100644 index 0000000000..4821c2f017 --- /dev/null +++ b/esp32p4/src/soc_etm/ch35_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH35_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH35_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH35_TASK_ID` reader - Configures ch35_task_id"] +pub type CH35_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH35_TASK_ID` writer - Configures ch35_task_id"] +pub type CH35_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch35_task_id"] + #[inline(always)] + pub fn ch35_task_id(&self) -> CH35_TASK_ID_R { + CH35_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH35_TASK_ID") + .field( + "ch35_task_id", + &format_args!("{}", self.ch35_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch35_task_id"] + #[inline(always)] + #[must_use] + pub fn ch35_task_id(&mut self) -> CH35_TASK_ID_W { + CH35_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel35 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch35_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch35_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH35_TASK_ID_SPEC; +impl crate::RegisterSpec for CH35_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch35_task_id::R`](R) reader structure"] +impl crate::Readable for CH35_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch35_task_id::W`](W) writer structure"] +impl crate::Writable for CH35_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH35_TASK_ID to value 0"] +impl crate::Resettable for CH35_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch36_evt_id.rs b/esp32p4/src/soc_etm/ch36_evt_id.rs new file mode 100644 index 0000000000..05065113ed --- /dev/null +++ b/esp32p4/src/soc_etm/ch36_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH36_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH36_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH36_EVT_ID` reader - Configures ch36_evt_id"] +pub type CH36_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH36_EVT_ID` writer - Configures ch36_evt_id"] +pub type CH36_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch36_evt_id"] + #[inline(always)] + pub fn ch36_evt_id(&self) -> CH36_EVT_ID_R { + CH36_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH36_EVT_ID") + .field( + "ch36_evt_id", + &format_args!("{}", self.ch36_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch36_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch36_evt_id(&mut self) -> CH36_EVT_ID_W { + CH36_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel36 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch36_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch36_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH36_EVT_ID_SPEC; +impl crate::RegisterSpec for CH36_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch36_evt_id::R`](R) reader structure"] +impl crate::Readable for CH36_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch36_evt_id::W`](W) writer structure"] +impl crate::Writable for CH36_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH36_EVT_ID to value 0"] +impl crate::Resettable for CH36_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch36_task_id.rs b/esp32p4/src/soc_etm/ch36_task_id.rs new file mode 100644 index 0000000000..e370ab0ac8 --- /dev/null +++ b/esp32p4/src/soc_etm/ch36_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH36_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH36_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH36_TASK_ID` reader - Configures ch36_task_id"] +pub type CH36_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH36_TASK_ID` writer - Configures ch36_task_id"] +pub type CH36_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch36_task_id"] + #[inline(always)] + pub fn ch36_task_id(&self) -> CH36_TASK_ID_R { + CH36_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH36_TASK_ID") + .field( + "ch36_task_id", + &format_args!("{}", self.ch36_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch36_task_id"] + #[inline(always)] + #[must_use] + pub fn ch36_task_id(&mut self) -> CH36_TASK_ID_W { + CH36_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel36 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch36_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch36_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH36_TASK_ID_SPEC; +impl crate::RegisterSpec for CH36_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch36_task_id::R`](R) reader structure"] +impl crate::Readable for CH36_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch36_task_id::W`](W) writer structure"] +impl crate::Writable for CH36_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH36_TASK_ID to value 0"] +impl crate::Resettable for CH36_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch37_evt_id.rs b/esp32p4/src/soc_etm/ch37_evt_id.rs new file mode 100644 index 0000000000..54038bd74a --- /dev/null +++ b/esp32p4/src/soc_etm/ch37_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH37_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH37_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH37_EVT_ID` reader - Configures ch37_evt_id"] +pub type CH37_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH37_EVT_ID` writer - Configures ch37_evt_id"] +pub type CH37_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch37_evt_id"] + #[inline(always)] + pub fn ch37_evt_id(&self) -> CH37_EVT_ID_R { + CH37_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH37_EVT_ID") + .field( + "ch37_evt_id", + &format_args!("{}", self.ch37_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch37_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch37_evt_id(&mut self) -> CH37_EVT_ID_W { + CH37_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel37 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch37_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch37_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH37_EVT_ID_SPEC; +impl crate::RegisterSpec for CH37_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch37_evt_id::R`](R) reader structure"] +impl crate::Readable for CH37_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch37_evt_id::W`](W) writer structure"] +impl crate::Writable for CH37_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH37_EVT_ID to value 0"] +impl crate::Resettable for CH37_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch37_task_id.rs b/esp32p4/src/soc_etm/ch37_task_id.rs new file mode 100644 index 0000000000..476516550c --- /dev/null +++ b/esp32p4/src/soc_etm/ch37_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH37_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH37_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH37_TASK_ID` reader - Configures ch37_task_id"] +pub type CH37_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH37_TASK_ID` writer - Configures ch37_task_id"] +pub type CH37_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch37_task_id"] + #[inline(always)] + pub fn ch37_task_id(&self) -> CH37_TASK_ID_R { + CH37_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH37_TASK_ID") + .field( + "ch37_task_id", + &format_args!("{}", self.ch37_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch37_task_id"] + #[inline(always)] + #[must_use] + pub fn ch37_task_id(&mut self) -> CH37_TASK_ID_W { + CH37_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel37 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch37_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch37_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH37_TASK_ID_SPEC; +impl crate::RegisterSpec for CH37_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch37_task_id::R`](R) reader structure"] +impl crate::Readable for CH37_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch37_task_id::W`](W) writer structure"] +impl crate::Writable for CH37_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH37_TASK_ID to value 0"] +impl crate::Resettable for CH37_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch38_evt_id.rs b/esp32p4/src/soc_etm/ch38_evt_id.rs new file mode 100644 index 0000000000..8abff1fc1a --- /dev/null +++ b/esp32p4/src/soc_etm/ch38_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH38_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH38_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH38_EVT_ID` reader - Configures ch38_evt_id"] +pub type CH38_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH38_EVT_ID` writer - Configures ch38_evt_id"] +pub type CH38_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch38_evt_id"] + #[inline(always)] + pub fn ch38_evt_id(&self) -> CH38_EVT_ID_R { + CH38_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH38_EVT_ID") + .field( + "ch38_evt_id", + &format_args!("{}", self.ch38_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch38_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch38_evt_id(&mut self) -> CH38_EVT_ID_W { + CH38_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel38 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch38_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch38_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH38_EVT_ID_SPEC; +impl crate::RegisterSpec for CH38_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch38_evt_id::R`](R) reader structure"] +impl crate::Readable for CH38_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch38_evt_id::W`](W) writer structure"] +impl crate::Writable for CH38_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH38_EVT_ID to value 0"] +impl crate::Resettable for CH38_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch38_task_id.rs b/esp32p4/src/soc_etm/ch38_task_id.rs new file mode 100644 index 0000000000..f1a81a9033 --- /dev/null +++ b/esp32p4/src/soc_etm/ch38_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH38_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH38_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH38_TASK_ID` reader - Configures ch38_task_id"] +pub type CH38_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH38_TASK_ID` writer - Configures ch38_task_id"] +pub type CH38_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch38_task_id"] + #[inline(always)] + pub fn ch38_task_id(&self) -> CH38_TASK_ID_R { + CH38_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH38_TASK_ID") + .field( + "ch38_task_id", + &format_args!("{}", self.ch38_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch38_task_id"] + #[inline(always)] + #[must_use] + pub fn ch38_task_id(&mut self) -> CH38_TASK_ID_W { + CH38_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel38 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch38_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch38_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH38_TASK_ID_SPEC; +impl crate::RegisterSpec for CH38_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch38_task_id::R`](R) reader structure"] +impl crate::Readable for CH38_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch38_task_id::W`](W) writer structure"] +impl crate::Writable for CH38_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH38_TASK_ID to value 0"] +impl crate::Resettable for CH38_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch39_evt_id.rs b/esp32p4/src/soc_etm/ch39_evt_id.rs new file mode 100644 index 0000000000..585e4551b1 --- /dev/null +++ b/esp32p4/src/soc_etm/ch39_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH39_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH39_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH39_EVT_ID` reader - Configures ch39_evt_id"] +pub type CH39_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH39_EVT_ID` writer - Configures ch39_evt_id"] +pub type CH39_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch39_evt_id"] + #[inline(always)] + pub fn ch39_evt_id(&self) -> CH39_EVT_ID_R { + CH39_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH39_EVT_ID") + .field( + "ch39_evt_id", + &format_args!("{}", self.ch39_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch39_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch39_evt_id(&mut self) -> CH39_EVT_ID_W { + CH39_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel39 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch39_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch39_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH39_EVT_ID_SPEC; +impl crate::RegisterSpec for CH39_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch39_evt_id::R`](R) reader structure"] +impl crate::Readable for CH39_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch39_evt_id::W`](W) writer structure"] +impl crate::Writable for CH39_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH39_EVT_ID to value 0"] +impl crate::Resettable for CH39_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch39_task_id.rs b/esp32p4/src/soc_etm/ch39_task_id.rs new file mode 100644 index 0000000000..7f0ed72d47 --- /dev/null +++ b/esp32p4/src/soc_etm/ch39_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH39_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH39_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH39_TASK_ID` reader - Configures ch39_task_id"] +pub type CH39_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH39_TASK_ID` writer - Configures ch39_task_id"] +pub type CH39_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch39_task_id"] + #[inline(always)] + pub fn ch39_task_id(&self) -> CH39_TASK_ID_R { + CH39_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH39_TASK_ID") + .field( + "ch39_task_id", + &format_args!("{}", self.ch39_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch39_task_id"] + #[inline(always)] + #[must_use] + pub fn ch39_task_id(&mut self) -> CH39_TASK_ID_W { + CH39_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel39 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch39_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch39_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH39_TASK_ID_SPEC; +impl crate::RegisterSpec for CH39_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch39_task_id::R`](R) reader structure"] +impl crate::Readable for CH39_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch39_task_id::W`](W) writer structure"] +impl crate::Writable for CH39_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH39_TASK_ID to value 0"] +impl crate::Resettable for CH39_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch3_evt_id.rs b/esp32p4/src/soc_etm/ch3_evt_id.rs new file mode 100644 index 0000000000..8b132bac17 --- /dev/null +++ b/esp32p4/src/soc_etm/ch3_evt_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH3_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_EVT_ID` reader - Configures ch3_evt_id"] +pub type CH3_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH3_EVT_ID` writer - Configures ch3_evt_id"] +pub type CH3_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch3_evt_id"] + #[inline(always)] + pub fn ch3_evt_id(&self) -> CH3_EVT_ID_R { + CH3_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_EVT_ID") + .field("ch3_evt_id", &format_args!("{}", self.ch3_evt_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch3_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch3_evt_id(&mut self) -> CH3_EVT_ID_W { + CH3_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel3 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_EVT_ID_SPEC; +impl crate::RegisterSpec for CH3_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_evt_id::R`](R) reader structure"] +impl crate::Readable for CH3_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_evt_id::W`](W) writer structure"] +impl crate::Writable for CH3_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_EVT_ID to value 0"] +impl crate::Resettable for CH3_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch3_task_id.rs b/esp32p4/src/soc_etm/ch3_task_id.rs new file mode 100644 index 0000000000..47ab24fd41 --- /dev/null +++ b/esp32p4/src/soc_etm/ch3_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH3_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_TASK_ID` reader - Configures ch3_task_id"] +pub type CH3_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH3_TASK_ID` writer - Configures ch3_task_id"] +pub type CH3_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch3_task_id"] + #[inline(always)] + pub fn ch3_task_id(&self) -> CH3_TASK_ID_R { + CH3_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH3_TASK_ID") + .field( + "ch3_task_id", + &format_args!("{}", self.ch3_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch3_task_id"] + #[inline(always)] + #[must_use] + pub fn ch3_task_id(&mut self) -> CH3_TASK_ID_W { + CH3_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel3 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch3_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch3_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_TASK_ID_SPEC; +impl crate::RegisterSpec for CH3_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_task_id::R`](R) reader structure"] +impl crate::Readable for CH3_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_task_id::W`](W) writer structure"] +impl crate::Writable for CH3_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH3_TASK_ID to value 0"] +impl crate::Resettable for CH3_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch40_evt_id.rs b/esp32p4/src/soc_etm/ch40_evt_id.rs new file mode 100644 index 0000000000..d78abc2945 --- /dev/null +++ b/esp32p4/src/soc_etm/ch40_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH40_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH40_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH40_EVT_ID` reader - Configures ch40_evt_id"] +pub type CH40_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH40_EVT_ID` writer - Configures ch40_evt_id"] +pub type CH40_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch40_evt_id"] + #[inline(always)] + pub fn ch40_evt_id(&self) -> CH40_EVT_ID_R { + CH40_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH40_EVT_ID") + .field( + "ch40_evt_id", + &format_args!("{}", self.ch40_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch40_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch40_evt_id(&mut self) -> CH40_EVT_ID_W { + CH40_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel40 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch40_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch40_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH40_EVT_ID_SPEC; +impl crate::RegisterSpec for CH40_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch40_evt_id::R`](R) reader structure"] +impl crate::Readable for CH40_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch40_evt_id::W`](W) writer structure"] +impl crate::Writable for CH40_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH40_EVT_ID to value 0"] +impl crate::Resettable for CH40_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch40_task_id.rs b/esp32p4/src/soc_etm/ch40_task_id.rs new file mode 100644 index 0000000000..bd89bba008 --- /dev/null +++ b/esp32p4/src/soc_etm/ch40_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH40_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH40_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH40_TASK_ID` reader - Configures ch40_task_id"] +pub type CH40_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH40_TASK_ID` writer - Configures ch40_task_id"] +pub type CH40_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch40_task_id"] + #[inline(always)] + pub fn ch40_task_id(&self) -> CH40_TASK_ID_R { + CH40_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH40_TASK_ID") + .field( + "ch40_task_id", + &format_args!("{}", self.ch40_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch40_task_id"] + #[inline(always)] + #[must_use] + pub fn ch40_task_id(&mut self) -> CH40_TASK_ID_W { + CH40_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel40 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch40_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch40_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH40_TASK_ID_SPEC; +impl crate::RegisterSpec for CH40_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch40_task_id::R`](R) reader structure"] +impl crate::Readable for CH40_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch40_task_id::W`](W) writer structure"] +impl crate::Writable for CH40_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH40_TASK_ID to value 0"] +impl crate::Resettable for CH40_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch41_evt_id.rs b/esp32p4/src/soc_etm/ch41_evt_id.rs new file mode 100644 index 0000000000..a1dedf5eb1 --- /dev/null +++ b/esp32p4/src/soc_etm/ch41_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH41_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH41_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH41_EVT_ID` reader - Configures ch41_evt_id"] +pub type CH41_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH41_EVT_ID` writer - Configures ch41_evt_id"] +pub type CH41_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch41_evt_id"] + #[inline(always)] + pub fn ch41_evt_id(&self) -> CH41_EVT_ID_R { + CH41_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH41_EVT_ID") + .field( + "ch41_evt_id", + &format_args!("{}", self.ch41_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch41_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch41_evt_id(&mut self) -> CH41_EVT_ID_W { + CH41_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel41 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch41_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch41_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH41_EVT_ID_SPEC; +impl crate::RegisterSpec for CH41_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch41_evt_id::R`](R) reader structure"] +impl crate::Readable for CH41_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch41_evt_id::W`](W) writer structure"] +impl crate::Writable for CH41_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH41_EVT_ID to value 0"] +impl crate::Resettable for CH41_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch41_task_id.rs b/esp32p4/src/soc_etm/ch41_task_id.rs new file mode 100644 index 0000000000..76af8d3334 --- /dev/null +++ b/esp32p4/src/soc_etm/ch41_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH41_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH41_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH41_TASK_ID` reader - Configures ch41_task_id"] +pub type CH41_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH41_TASK_ID` writer - Configures ch41_task_id"] +pub type CH41_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch41_task_id"] + #[inline(always)] + pub fn ch41_task_id(&self) -> CH41_TASK_ID_R { + CH41_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH41_TASK_ID") + .field( + "ch41_task_id", + &format_args!("{}", self.ch41_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch41_task_id"] + #[inline(always)] + #[must_use] + pub fn ch41_task_id(&mut self) -> CH41_TASK_ID_W { + CH41_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel41 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch41_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch41_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH41_TASK_ID_SPEC; +impl crate::RegisterSpec for CH41_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch41_task_id::R`](R) reader structure"] +impl crate::Readable for CH41_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch41_task_id::W`](W) writer structure"] +impl crate::Writable for CH41_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH41_TASK_ID to value 0"] +impl crate::Resettable for CH41_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch42_evt_id.rs b/esp32p4/src/soc_etm/ch42_evt_id.rs new file mode 100644 index 0000000000..8df76c5f69 --- /dev/null +++ b/esp32p4/src/soc_etm/ch42_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH42_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH42_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH42_EVT_ID` reader - Configures ch42_evt_id"] +pub type CH42_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH42_EVT_ID` writer - Configures ch42_evt_id"] +pub type CH42_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch42_evt_id"] + #[inline(always)] + pub fn ch42_evt_id(&self) -> CH42_EVT_ID_R { + CH42_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH42_EVT_ID") + .field( + "ch42_evt_id", + &format_args!("{}", self.ch42_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch42_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch42_evt_id(&mut self) -> CH42_EVT_ID_W { + CH42_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel42 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch42_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch42_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH42_EVT_ID_SPEC; +impl crate::RegisterSpec for CH42_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch42_evt_id::R`](R) reader structure"] +impl crate::Readable for CH42_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch42_evt_id::W`](W) writer structure"] +impl crate::Writable for CH42_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH42_EVT_ID to value 0"] +impl crate::Resettable for CH42_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch42_task_id.rs b/esp32p4/src/soc_etm/ch42_task_id.rs new file mode 100644 index 0000000000..7507dd3170 --- /dev/null +++ b/esp32p4/src/soc_etm/ch42_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH42_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH42_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH42_TASK_ID` reader - Configures ch42_task_id"] +pub type CH42_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH42_TASK_ID` writer - Configures ch42_task_id"] +pub type CH42_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch42_task_id"] + #[inline(always)] + pub fn ch42_task_id(&self) -> CH42_TASK_ID_R { + CH42_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH42_TASK_ID") + .field( + "ch42_task_id", + &format_args!("{}", self.ch42_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch42_task_id"] + #[inline(always)] + #[must_use] + pub fn ch42_task_id(&mut self) -> CH42_TASK_ID_W { + CH42_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel42 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch42_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch42_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH42_TASK_ID_SPEC; +impl crate::RegisterSpec for CH42_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch42_task_id::R`](R) reader structure"] +impl crate::Readable for CH42_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch42_task_id::W`](W) writer structure"] +impl crate::Writable for CH42_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH42_TASK_ID to value 0"] +impl crate::Resettable for CH42_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch43_evt_id.rs b/esp32p4/src/soc_etm/ch43_evt_id.rs new file mode 100644 index 0000000000..e17ae9f296 --- /dev/null +++ b/esp32p4/src/soc_etm/ch43_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH43_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH43_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH43_EVT_ID` reader - Configures ch43_evt_id"] +pub type CH43_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH43_EVT_ID` writer - Configures ch43_evt_id"] +pub type CH43_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch43_evt_id"] + #[inline(always)] + pub fn ch43_evt_id(&self) -> CH43_EVT_ID_R { + CH43_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH43_EVT_ID") + .field( + "ch43_evt_id", + &format_args!("{}", self.ch43_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch43_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch43_evt_id(&mut self) -> CH43_EVT_ID_W { + CH43_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel43 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch43_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch43_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH43_EVT_ID_SPEC; +impl crate::RegisterSpec for CH43_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch43_evt_id::R`](R) reader structure"] +impl crate::Readable for CH43_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch43_evt_id::W`](W) writer structure"] +impl crate::Writable for CH43_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH43_EVT_ID to value 0"] +impl crate::Resettable for CH43_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch43_task_id.rs b/esp32p4/src/soc_etm/ch43_task_id.rs new file mode 100644 index 0000000000..fa925686c0 --- /dev/null +++ b/esp32p4/src/soc_etm/ch43_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH43_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH43_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH43_TASK_ID` reader - Configures ch43_task_id"] +pub type CH43_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH43_TASK_ID` writer - Configures ch43_task_id"] +pub type CH43_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch43_task_id"] + #[inline(always)] + pub fn ch43_task_id(&self) -> CH43_TASK_ID_R { + CH43_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH43_TASK_ID") + .field( + "ch43_task_id", + &format_args!("{}", self.ch43_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch43_task_id"] + #[inline(always)] + #[must_use] + pub fn ch43_task_id(&mut self) -> CH43_TASK_ID_W { + CH43_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel43 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch43_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch43_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH43_TASK_ID_SPEC; +impl crate::RegisterSpec for CH43_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch43_task_id::R`](R) reader structure"] +impl crate::Readable for CH43_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch43_task_id::W`](W) writer structure"] +impl crate::Writable for CH43_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH43_TASK_ID to value 0"] +impl crate::Resettable for CH43_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch44_evt_id.rs b/esp32p4/src/soc_etm/ch44_evt_id.rs new file mode 100644 index 0000000000..b53269a65a --- /dev/null +++ b/esp32p4/src/soc_etm/ch44_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH44_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH44_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH44_EVT_ID` reader - Configures ch44_evt_id"] +pub type CH44_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH44_EVT_ID` writer - Configures ch44_evt_id"] +pub type CH44_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch44_evt_id"] + #[inline(always)] + pub fn ch44_evt_id(&self) -> CH44_EVT_ID_R { + CH44_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH44_EVT_ID") + .field( + "ch44_evt_id", + &format_args!("{}", self.ch44_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch44_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch44_evt_id(&mut self) -> CH44_EVT_ID_W { + CH44_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel44 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch44_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch44_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH44_EVT_ID_SPEC; +impl crate::RegisterSpec for CH44_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch44_evt_id::R`](R) reader structure"] +impl crate::Readable for CH44_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch44_evt_id::W`](W) writer structure"] +impl crate::Writable for CH44_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH44_EVT_ID to value 0"] +impl crate::Resettable for CH44_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch44_task_id.rs b/esp32p4/src/soc_etm/ch44_task_id.rs new file mode 100644 index 0000000000..f1862acb91 --- /dev/null +++ b/esp32p4/src/soc_etm/ch44_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH44_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH44_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH44_TASK_ID` reader - Configures ch44_task_id"] +pub type CH44_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH44_TASK_ID` writer - Configures ch44_task_id"] +pub type CH44_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch44_task_id"] + #[inline(always)] + pub fn ch44_task_id(&self) -> CH44_TASK_ID_R { + CH44_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH44_TASK_ID") + .field( + "ch44_task_id", + &format_args!("{}", self.ch44_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch44_task_id"] + #[inline(always)] + #[must_use] + pub fn ch44_task_id(&mut self) -> CH44_TASK_ID_W { + CH44_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel44 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch44_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch44_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH44_TASK_ID_SPEC; +impl crate::RegisterSpec for CH44_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch44_task_id::R`](R) reader structure"] +impl crate::Readable for CH44_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch44_task_id::W`](W) writer structure"] +impl crate::Writable for CH44_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH44_TASK_ID to value 0"] +impl crate::Resettable for CH44_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch45_evt_id.rs b/esp32p4/src/soc_etm/ch45_evt_id.rs new file mode 100644 index 0000000000..629dbcd0f0 --- /dev/null +++ b/esp32p4/src/soc_etm/ch45_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH45_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH45_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH45_EVT_ID` reader - Configures ch45_evt_id"] +pub type CH45_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH45_EVT_ID` writer - Configures ch45_evt_id"] +pub type CH45_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch45_evt_id"] + #[inline(always)] + pub fn ch45_evt_id(&self) -> CH45_EVT_ID_R { + CH45_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH45_EVT_ID") + .field( + "ch45_evt_id", + &format_args!("{}", self.ch45_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch45_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch45_evt_id(&mut self) -> CH45_EVT_ID_W { + CH45_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel45 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch45_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch45_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH45_EVT_ID_SPEC; +impl crate::RegisterSpec for CH45_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch45_evt_id::R`](R) reader structure"] +impl crate::Readable for CH45_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch45_evt_id::W`](W) writer structure"] +impl crate::Writable for CH45_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH45_EVT_ID to value 0"] +impl crate::Resettable for CH45_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch45_task_id.rs b/esp32p4/src/soc_etm/ch45_task_id.rs new file mode 100644 index 0000000000..d137620ee5 --- /dev/null +++ b/esp32p4/src/soc_etm/ch45_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH45_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH45_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH45_TASK_ID` reader - Configures ch45_task_id"] +pub type CH45_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH45_TASK_ID` writer - Configures ch45_task_id"] +pub type CH45_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch45_task_id"] + #[inline(always)] + pub fn ch45_task_id(&self) -> CH45_TASK_ID_R { + CH45_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH45_TASK_ID") + .field( + "ch45_task_id", + &format_args!("{}", self.ch45_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch45_task_id"] + #[inline(always)] + #[must_use] + pub fn ch45_task_id(&mut self) -> CH45_TASK_ID_W { + CH45_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel45 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch45_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch45_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH45_TASK_ID_SPEC; +impl crate::RegisterSpec for CH45_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch45_task_id::R`](R) reader structure"] +impl crate::Readable for CH45_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch45_task_id::W`](W) writer structure"] +impl crate::Writable for CH45_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH45_TASK_ID to value 0"] +impl crate::Resettable for CH45_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch46_evt_id.rs b/esp32p4/src/soc_etm/ch46_evt_id.rs new file mode 100644 index 0000000000..95aecc336f --- /dev/null +++ b/esp32p4/src/soc_etm/ch46_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH46_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH46_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH46_EVT_ID` reader - Configures ch46_evt_id"] +pub type CH46_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH46_EVT_ID` writer - Configures ch46_evt_id"] +pub type CH46_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch46_evt_id"] + #[inline(always)] + pub fn ch46_evt_id(&self) -> CH46_EVT_ID_R { + CH46_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH46_EVT_ID") + .field( + "ch46_evt_id", + &format_args!("{}", self.ch46_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch46_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch46_evt_id(&mut self) -> CH46_EVT_ID_W { + CH46_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel46 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch46_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch46_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH46_EVT_ID_SPEC; +impl crate::RegisterSpec for CH46_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch46_evt_id::R`](R) reader structure"] +impl crate::Readable for CH46_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch46_evt_id::W`](W) writer structure"] +impl crate::Writable for CH46_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH46_EVT_ID to value 0"] +impl crate::Resettable for CH46_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch46_task_id.rs b/esp32p4/src/soc_etm/ch46_task_id.rs new file mode 100644 index 0000000000..6491de18d4 --- /dev/null +++ b/esp32p4/src/soc_etm/ch46_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH46_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH46_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH46_TASK_ID` reader - Configures ch46_task_id"] +pub type CH46_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH46_TASK_ID` writer - Configures ch46_task_id"] +pub type CH46_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch46_task_id"] + #[inline(always)] + pub fn ch46_task_id(&self) -> CH46_TASK_ID_R { + CH46_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH46_TASK_ID") + .field( + "ch46_task_id", + &format_args!("{}", self.ch46_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch46_task_id"] + #[inline(always)] + #[must_use] + pub fn ch46_task_id(&mut self) -> CH46_TASK_ID_W { + CH46_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel46 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch46_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch46_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH46_TASK_ID_SPEC; +impl crate::RegisterSpec for CH46_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch46_task_id::R`](R) reader structure"] +impl crate::Readable for CH46_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch46_task_id::W`](W) writer structure"] +impl crate::Writable for CH46_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH46_TASK_ID to value 0"] +impl crate::Resettable for CH46_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch47_evt_id.rs b/esp32p4/src/soc_etm/ch47_evt_id.rs new file mode 100644 index 0000000000..bd3fb3e65b --- /dev/null +++ b/esp32p4/src/soc_etm/ch47_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH47_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH47_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH47_EVT_ID` reader - Configures ch47_evt_id"] +pub type CH47_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH47_EVT_ID` writer - Configures ch47_evt_id"] +pub type CH47_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch47_evt_id"] + #[inline(always)] + pub fn ch47_evt_id(&self) -> CH47_EVT_ID_R { + CH47_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH47_EVT_ID") + .field( + "ch47_evt_id", + &format_args!("{}", self.ch47_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch47_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch47_evt_id(&mut self) -> CH47_EVT_ID_W { + CH47_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel47 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch47_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch47_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH47_EVT_ID_SPEC; +impl crate::RegisterSpec for CH47_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch47_evt_id::R`](R) reader structure"] +impl crate::Readable for CH47_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch47_evt_id::W`](W) writer structure"] +impl crate::Writable for CH47_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH47_EVT_ID to value 0"] +impl crate::Resettable for CH47_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch47_task_id.rs b/esp32p4/src/soc_etm/ch47_task_id.rs new file mode 100644 index 0000000000..dec69ebbf0 --- /dev/null +++ b/esp32p4/src/soc_etm/ch47_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH47_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH47_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH47_TASK_ID` reader - Configures ch47_task_id"] +pub type CH47_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH47_TASK_ID` writer - Configures ch47_task_id"] +pub type CH47_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch47_task_id"] + #[inline(always)] + pub fn ch47_task_id(&self) -> CH47_TASK_ID_R { + CH47_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH47_TASK_ID") + .field( + "ch47_task_id", + &format_args!("{}", self.ch47_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch47_task_id"] + #[inline(always)] + #[must_use] + pub fn ch47_task_id(&mut self) -> CH47_TASK_ID_W { + CH47_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel47 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch47_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch47_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH47_TASK_ID_SPEC; +impl crate::RegisterSpec for CH47_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch47_task_id::R`](R) reader structure"] +impl crate::Readable for CH47_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch47_task_id::W`](W) writer structure"] +impl crate::Writable for CH47_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH47_TASK_ID to value 0"] +impl crate::Resettable for CH47_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch48_evt_id.rs b/esp32p4/src/soc_etm/ch48_evt_id.rs new file mode 100644 index 0000000000..aa50c358be --- /dev/null +++ b/esp32p4/src/soc_etm/ch48_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH48_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH48_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH48_EVT_ID` reader - Configures ch48_evt_id"] +pub type CH48_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH48_EVT_ID` writer - Configures ch48_evt_id"] +pub type CH48_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch48_evt_id"] + #[inline(always)] + pub fn ch48_evt_id(&self) -> CH48_EVT_ID_R { + CH48_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH48_EVT_ID") + .field( + "ch48_evt_id", + &format_args!("{}", self.ch48_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch48_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch48_evt_id(&mut self) -> CH48_EVT_ID_W { + CH48_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel48 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch48_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch48_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH48_EVT_ID_SPEC; +impl crate::RegisterSpec for CH48_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch48_evt_id::R`](R) reader structure"] +impl crate::Readable for CH48_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch48_evt_id::W`](W) writer structure"] +impl crate::Writable for CH48_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH48_EVT_ID to value 0"] +impl crate::Resettable for CH48_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch48_task_id.rs b/esp32p4/src/soc_etm/ch48_task_id.rs new file mode 100644 index 0000000000..34a11308e3 --- /dev/null +++ b/esp32p4/src/soc_etm/ch48_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH48_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH48_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH48_TASK_ID` reader - Configures ch48_task_id"] +pub type CH48_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH48_TASK_ID` writer - Configures ch48_task_id"] +pub type CH48_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch48_task_id"] + #[inline(always)] + pub fn ch48_task_id(&self) -> CH48_TASK_ID_R { + CH48_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH48_TASK_ID") + .field( + "ch48_task_id", + &format_args!("{}", self.ch48_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch48_task_id"] + #[inline(always)] + #[must_use] + pub fn ch48_task_id(&mut self) -> CH48_TASK_ID_W { + CH48_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel48 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch48_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch48_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH48_TASK_ID_SPEC; +impl crate::RegisterSpec for CH48_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch48_task_id::R`](R) reader structure"] +impl crate::Readable for CH48_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch48_task_id::W`](W) writer structure"] +impl crate::Writable for CH48_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH48_TASK_ID to value 0"] +impl crate::Resettable for CH48_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch49_evt_id.rs b/esp32p4/src/soc_etm/ch49_evt_id.rs new file mode 100644 index 0000000000..e0c19aa740 --- /dev/null +++ b/esp32p4/src/soc_etm/ch49_evt_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH49_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH49_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH49_EVT_ID` reader - Configures ch49_evt_id"] +pub type CH49_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH49_EVT_ID` writer - Configures ch49_evt_id"] +pub type CH49_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch49_evt_id"] + #[inline(always)] + pub fn ch49_evt_id(&self) -> CH49_EVT_ID_R { + CH49_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH49_EVT_ID") + .field( + "ch49_evt_id", + &format_args!("{}", self.ch49_evt_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch49_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch49_evt_id(&mut self) -> CH49_EVT_ID_W { + CH49_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel49 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch49_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch49_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH49_EVT_ID_SPEC; +impl crate::RegisterSpec for CH49_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch49_evt_id::R`](R) reader structure"] +impl crate::Readable for CH49_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch49_evt_id::W`](W) writer structure"] +impl crate::Writable for CH49_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH49_EVT_ID to value 0"] +impl crate::Resettable for CH49_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch49_task_id.rs b/esp32p4/src/soc_etm/ch49_task_id.rs new file mode 100644 index 0000000000..72bf8367b5 --- /dev/null +++ b/esp32p4/src/soc_etm/ch49_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH49_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH49_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH49_TASK_ID` reader - Configures ch49_task_id"] +pub type CH49_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH49_TASK_ID` writer - Configures ch49_task_id"] +pub type CH49_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch49_task_id"] + #[inline(always)] + pub fn ch49_task_id(&self) -> CH49_TASK_ID_R { + CH49_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH49_TASK_ID") + .field( + "ch49_task_id", + &format_args!("{}", self.ch49_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch49_task_id"] + #[inline(always)] + #[must_use] + pub fn ch49_task_id(&mut self) -> CH49_TASK_ID_W { + CH49_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel49 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch49_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch49_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH49_TASK_ID_SPEC; +impl crate::RegisterSpec for CH49_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch49_task_id::R`](R) reader structure"] +impl crate::Readable for CH49_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch49_task_id::W`](W) writer structure"] +impl crate::Writable for CH49_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH49_TASK_ID to value 0"] +impl crate::Resettable for CH49_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch4_evt_id.rs b/esp32p4/src/soc_etm/ch4_evt_id.rs new file mode 100644 index 0000000000..0bdc471642 --- /dev/null +++ b/esp32p4/src/soc_etm/ch4_evt_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH4_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_EVT_ID` reader - Configures ch4_evt_id"] +pub type CH4_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH4_EVT_ID` writer - Configures ch4_evt_id"] +pub type CH4_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch4_evt_id"] + #[inline(always)] + pub fn ch4_evt_id(&self) -> CH4_EVT_ID_R { + CH4_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_EVT_ID") + .field("ch4_evt_id", &format_args!("{}", self.ch4_evt_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch4_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch4_evt_id(&mut self) -> CH4_EVT_ID_W { + CH4_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel4 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_EVT_ID_SPEC; +impl crate::RegisterSpec for CH4_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_evt_id::R`](R) reader structure"] +impl crate::Readable for CH4_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_evt_id::W`](W) writer structure"] +impl crate::Writable for CH4_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_EVT_ID to value 0"] +impl crate::Resettable for CH4_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch4_task_id.rs b/esp32p4/src/soc_etm/ch4_task_id.rs new file mode 100644 index 0000000000..1db423ff9c --- /dev/null +++ b/esp32p4/src/soc_etm/ch4_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH4_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_TASK_ID` reader - Configures ch4_task_id"] +pub type CH4_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH4_TASK_ID` writer - Configures ch4_task_id"] +pub type CH4_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch4_task_id"] + #[inline(always)] + pub fn ch4_task_id(&self) -> CH4_TASK_ID_R { + CH4_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH4_TASK_ID") + .field( + "ch4_task_id", + &format_args!("{}", self.ch4_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch4_task_id"] + #[inline(always)] + #[must_use] + pub fn ch4_task_id(&mut self) -> CH4_TASK_ID_W { + CH4_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel4 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch4_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch4_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_TASK_ID_SPEC; +impl crate::RegisterSpec for CH4_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_task_id::R`](R) reader structure"] +impl crate::Readable for CH4_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_task_id::W`](W) writer structure"] +impl crate::Writable for CH4_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH4_TASK_ID to value 0"] +impl crate::Resettable for CH4_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch5_evt_id.rs b/esp32p4/src/soc_etm/ch5_evt_id.rs new file mode 100644 index 0000000000..f69ee5f616 --- /dev/null +++ b/esp32p4/src/soc_etm/ch5_evt_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH5_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH5_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH5_EVT_ID` reader - Configures ch5_evt_id"] +pub type CH5_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH5_EVT_ID` writer - Configures ch5_evt_id"] +pub type CH5_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch5_evt_id"] + #[inline(always)] + pub fn ch5_evt_id(&self) -> CH5_EVT_ID_R { + CH5_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH5_EVT_ID") + .field("ch5_evt_id", &format_args!("{}", self.ch5_evt_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch5_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch5_evt_id(&mut self) -> CH5_EVT_ID_W { + CH5_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel5 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch5_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH5_EVT_ID_SPEC; +impl crate::RegisterSpec for CH5_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch5_evt_id::R`](R) reader structure"] +impl crate::Readable for CH5_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch5_evt_id::W`](W) writer structure"] +impl crate::Writable for CH5_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH5_EVT_ID to value 0"] +impl crate::Resettable for CH5_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch5_task_id.rs b/esp32p4/src/soc_etm/ch5_task_id.rs new file mode 100644 index 0000000000..c64db3fea8 --- /dev/null +++ b/esp32p4/src/soc_etm/ch5_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH5_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH5_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH5_TASK_ID` reader - Configures ch5_task_id"] +pub type CH5_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH5_TASK_ID` writer - Configures ch5_task_id"] +pub type CH5_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch5_task_id"] + #[inline(always)] + pub fn ch5_task_id(&self) -> CH5_TASK_ID_R { + CH5_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH5_TASK_ID") + .field( + "ch5_task_id", + &format_args!("{}", self.ch5_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch5_task_id"] + #[inline(always)] + #[must_use] + pub fn ch5_task_id(&mut self) -> CH5_TASK_ID_W { + CH5_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel5 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch5_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch5_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH5_TASK_ID_SPEC; +impl crate::RegisterSpec for CH5_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch5_task_id::R`](R) reader structure"] +impl crate::Readable for CH5_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch5_task_id::W`](W) writer structure"] +impl crate::Writable for CH5_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH5_TASK_ID to value 0"] +impl crate::Resettable for CH5_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch6_evt_id.rs b/esp32p4/src/soc_etm/ch6_evt_id.rs new file mode 100644 index 0000000000..f0025696b0 --- /dev/null +++ b/esp32p4/src/soc_etm/ch6_evt_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH6_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH6_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH6_EVT_ID` reader - Configures ch6_evt_id"] +pub type CH6_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH6_EVT_ID` writer - Configures ch6_evt_id"] +pub type CH6_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch6_evt_id"] + #[inline(always)] + pub fn ch6_evt_id(&self) -> CH6_EVT_ID_R { + CH6_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH6_EVT_ID") + .field("ch6_evt_id", &format_args!("{}", self.ch6_evt_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch6_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch6_evt_id(&mut self) -> CH6_EVT_ID_W { + CH6_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel6 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch6_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch6_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH6_EVT_ID_SPEC; +impl crate::RegisterSpec for CH6_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch6_evt_id::R`](R) reader structure"] +impl crate::Readable for CH6_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch6_evt_id::W`](W) writer structure"] +impl crate::Writable for CH6_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH6_EVT_ID to value 0"] +impl crate::Resettable for CH6_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch6_task_id.rs b/esp32p4/src/soc_etm/ch6_task_id.rs new file mode 100644 index 0000000000..263673a7b9 --- /dev/null +++ b/esp32p4/src/soc_etm/ch6_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH6_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH6_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH6_TASK_ID` reader - Configures ch6_task_id"] +pub type CH6_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH6_TASK_ID` writer - Configures ch6_task_id"] +pub type CH6_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch6_task_id"] + #[inline(always)] + pub fn ch6_task_id(&self) -> CH6_TASK_ID_R { + CH6_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH6_TASK_ID") + .field( + "ch6_task_id", + &format_args!("{}", self.ch6_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch6_task_id"] + #[inline(always)] + #[must_use] + pub fn ch6_task_id(&mut self) -> CH6_TASK_ID_W { + CH6_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel6 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch6_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch6_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH6_TASK_ID_SPEC; +impl crate::RegisterSpec for CH6_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch6_task_id::R`](R) reader structure"] +impl crate::Readable for CH6_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch6_task_id::W`](W) writer structure"] +impl crate::Writable for CH6_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH6_TASK_ID to value 0"] +impl crate::Resettable for CH6_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch7_evt_id.rs b/esp32p4/src/soc_etm/ch7_evt_id.rs new file mode 100644 index 0000000000..01acb563b1 --- /dev/null +++ b/esp32p4/src/soc_etm/ch7_evt_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH7_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH7_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH7_EVT_ID` reader - Configures ch7_evt_id"] +pub type CH7_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH7_EVT_ID` writer - Configures ch7_evt_id"] +pub type CH7_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch7_evt_id"] + #[inline(always)] + pub fn ch7_evt_id(&self) -> CH7_EVT_ID_R { + CH7_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH7_EVT_ID") + .field("ch7_evt_id", &format_args!("{}", self.ch7_evt_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch7_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch7_evt_id(&mut self) -> CH7_EVT_ID_W { + CH7_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel7 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch7_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch7_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH7_EVT_ID_SPEC; +impl crate::RegisterSpec for CH7_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch7_evt_id::R`](R) reader structure"] +impl crate::Readable for CH7_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch7_evt_id::W`](W) writer structure"] +impl crate::Writable for CH7_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH7_EVT_ID to value 0"] +impl crate::Resettable for CH7_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch7_task_id.rs b/esp32p4/src/soc_etm/ch7_task_id.rs new file mode 100644 index 0000000000..7e71f9b495 --- /dev/null +++ b/esp32p4/src/soc_etm/ch7_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH7_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH7_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH7_TASK_ID` reader - Configures ch7_task_id"] +pub type CH7_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH7_TASK_ID` writer - Configures ch7_task_id"] +pub type CH7_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch7_task_id"] + #[inline(always)] + pub fn ch7_task_id(&self) -> CH7_TASK_ID_R { + CH7_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH7_TASK_ID") + .field( + "ch7_task_id", + &format_args!("{}", self.ch7_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch7_task_id"] + #[inline(always)] + #[must_use] + pub fn ch7_task_id(&mut self) -> CH7_TASK_ID_W { + CH7_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel7 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch7_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch7_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH7_TASK_ID_SPEC; +impl crate::RegisterSpec for CH7_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch7_task_id::R`](R) reader structure"] +impl crate::Readable for CH7_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch7_task_id::W`](W) writer structure"] +impl crate::Writable for CH7_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH7_TASK_ID to value 0"] +impl crate::Resettable for CH7_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch8_evt_id.rs b/esp32p4/src/soc_etm/ch8_evt_id.rs new file mode 100644 index 0000000000..4f11e6325d --- /dev/null +++ b/esp32p4/src/soc_etm/ch8_evt_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH8_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH8_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH8_EVT_ID` reader - Configures ch8_evt_id"] +pub type CH8_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH8_EVT_ID` writer - Configures ch8_evt_id"] +pub type CH8_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch8_evt_id"] + #[inline(always)] + pub fn ch8_evt_id(&self) -> CH8_EVT_ID_R { + CH8_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH8_EVT_ID") + .field("ch8_evt_id", &format_args!("{}", self.ch8_evt_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch8_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch8_evt_id(&mut self) -> CH8_EVT_ID_W { + CH8_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel8 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch8_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch8_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH8_EVT_ID_SPEC; +impl crate::RegisterSpec for CH8_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch8_evt_id::R`](R) reader structure"] +impl crate::Readable for CH8_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch8_evt_id::W`](W) writer structure"] +impl crate::Writable for CH8_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH8_EVT_ID to value 0"] +impl crate::Resettable for CH8_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch8_task_id.rs b/esp32p4/src/soc_etm/ch8_task_id.rs new file mode 100644 index 0000000000..64b17cd8ea --- /dev/null +++ b/esp32p4/src/soc_etm/ch8_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH8_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH8_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH8_TASK_ID` reader - Configures ch8_task_id"] +pub type CH8_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH8_TASK_ID` writer - Configures ch8_task_id"] +pub type CH8_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch8_task_id"] + #[inline(always)] + pub fn ch8_task_id(&self) -> CH8_TASK_ID_R { + CH8_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH8_TASK_ID") + .field( + "ch8_task_id", + &format_args!("{}", self.ch8_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch8_task_id"] + #[inline(always)] + #[must_use] + pub fn ch8_task_id(&mut self) -> CH8_TASK_ID_W { + CH8_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel8 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch8_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch8_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH8_TASK_ID_SPEC; +impl crate::RegisterSpec for CH8_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch8_task_id::R`](R) reader structure"] +impl crate::Readable for CH8_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch8_task_id::W`](W) writer structure"] +impl crate::Writable for CH8_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH8_TASK_ID to value 0"] +impl crate::Resettable for CH8_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch9_evt_id.rs b/esp32p4/src/soc_etm/ch9_evt_id.rs new file mode 100644 index 0000000000..5e8e2ed23a --- /dev/null +++ b/esp32p4/src/soc_etm/ch9_evt_id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CH9_EVT_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH9_EVT_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH9_EVT_ID` reader - Configures ch9_evt_id"] +pub type CH9_EVT_ID_R = crate::FieldReader; +#[doc = "Field `CH9_EVT_ID` writer - Configures ch9_evt_id"] +pub type CH9_EVT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch9_evt_id"] + #[inline(always)] + pub fn ch9_evt_id(&self) -> CH9_EVT_ID_R { + CH9_EVT_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH9_EVT_ID") + .field("ch9_evt_id", &format_args!("{}", self.ch9_evt_id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch9_evt_id"] + #[inline(always)] + #[must_use] + pub fn ch9_evt_id(&mut self) -> CH9_EVT_ID_W { + CH9_EVT_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel9 event id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch9_evt_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch9_evt_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH9_EVT_ID_SPEC; +impl crate::RegisterSpec for CH9_EVT_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch9_evt_id::R`](R) reader structure"] +impl crate::Readable for CH9_EVT_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch9_evt_id::W`](W) writer structure"] +impl crate::Writable for CH9_EVT_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH9_EVT_ID to value 0"] +impl crate::Resettable for CH9_EVT_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch9_task_id.rs b/esp32p4/src/soc_etm/ch9_task_id.rs new file mode 100644 index 0000000000..77e7727189 --- /dev/null +++ b/esp32p4/src/soc_etm/ch9_task_id.rs @@ -0,0 +1,66 @@ +#[doc = "Register `CH9_TASK_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CH9_TASK_ID` writer"] +pub type W = crate::W; +#[doc = "Field `CH9_TASK_ID` reader - Configures ch9_task_id"] +pub type CH9_TASK_ID_R = crate::FieldReader; +#[doc = "Field `CH9_TASK_ID` writer - Configures ch9_task_id"] +pub type CH9_TASK_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures ch9_task_id"] + #[inline(always)] + pub fn ch9_task_id(&self) -> CH9_TASK_ID_R { + CH9_TASK_ID_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH9_TASK_ID") + .field( + "ch9_task_id", + &format_args!("{}", self.ch9_task_id().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures ch9_task_id"] + #[inline(always)] + #[must_use] + pub fn ch9_task_id(&mut self) -> CH9_TASK_ID_W { + CH9_TASK_ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel9 task id register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch9_task_id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch9_task_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH9_TASK_ID_SPEC; +impl crate::RegisterSpec for CH9_TASK_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch9_task_id::R`](R) reader structure"] +impl crate::Readable for CH9_TASK_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch9_task_id::W`](W) writer structure"] +impl crate::Writable for CH9_TASK_ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH9_TASK_ID to value 0"] +impl crate::Resettable for CH9_TASK_ID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch_ena_ad0.rs b/esp32p4/src/soc_etm/ch_ena_ad0.rs new file mode 100644 index 0000000000..47d9324299 --- /dev/null +++ b/esp32p4/src/soc_etm/ch_ena_ad0.rs @@ -0,0 +1,559 @@ +#[doc = "Register `CH_ENA_AD0` reader"] +pub type R = crate::R; +#[doc = "Register `CH_ENA_AD0` writer"] +pub type W = crate::W; +#[doc = "Field `CH_ENA0` reader - Represents ch0 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA0_R = crate::BitReader; +#[doc = "Field `CH_ENA0` writer - Represents ch0 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA1` reader - Represents ch1 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA1_R = crate::BitReader; +#[doc = "Field `CH_ENA1` writer - Represents ch1 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA2` reader - Represents ch2 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA2_R = crate::BitReader; +#[doc = "Field `CH_ENA2` writer - Represents ch2 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA3` reader - Represents ch3 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA3_R = crate::BitReader; +#[doc = "Field `CH_ENA3` writer - Represents ch3 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA4` reader - Represents ch4 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA4_R = crate::BitReader; +#[doc = "Field `CH_ENA4` writer - Represents ch4 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA5` reader - Represents ch5 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA5_R = crate::BitReader; +#[doc = "Field `CH_ENA5` writer - Represents ch5 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA6` reader - Represents ch6 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA6_R = crate::BitReader; +#[doc = "Field `CH_ENA6` writer - Represents ch6 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA7` reader - Represents ch7 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA7_R = crate::BitReader; +#[doc = "Field `CH_ENA7` writer - Represents ch7 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA8` reader - Represents ch8 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA8_R = crate::BitReader; +#[doc = "Field `CH_ENA8` writer - Represents ch8 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA9` reader - Represents ch9 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA9_R = crate::BitReader; +#[doc = "Field `CH_ENA9` writer - Represents ch9 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA10` reader - Represents ch10 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA10_R = crate::BitReader; +#[doc = "Field `CH_ENA10` writer - Represents ch10 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA11` reader - Represents ch11 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA11_R = crate::BitReader; +#[doc = "Field `CH_ENA11` writer - Represents ch11 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA12` reader - Represents ch12 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA12_R = crate::BitReader; +#[doc = "Field `CH_ENA12` writer - Represents ch12 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA13` reader - Represents ch13 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA13_R = crate::BitReader; +#[doc = "Field `CH_ENA13` writer - Represents ch13 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA14` reader - Represents ch14 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA14_R = crate::BitReader; +#[doc = "Field `CH_ENA14` writer - Represents ch14 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA15` reader - Represents ch15 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA15_R = crate::BitReader; +#[doc = "Field `CH_ENA15` writer - Represents ch15 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA15_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA16` reader - Represents ch16 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA16_R = crate::BitReader; +#[doc = "Field `CH_ENA16` writer - Represents ch16 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA16_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA17` reader - Represents ch17 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA17_R = crate::BitReader; +#[doc = "Field `CH_ENA17` writer - Represents ch17 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA17_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA18` reader - Represents ch18 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA18_R = crate::BitReader; +#[doc = "Field `CH_ENA18` writer - Represents ch18 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA18_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA19` reader - Represents ch19 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA19_R = crate::BitReader; +#[doc = "Field `CH_ENA19` writer - Represents ch19 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA19_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA20` reader - Represents ch20 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA20_R = crate::BitReader; +#[doc = "Field `CH_ENA20` writer - Represents ch20 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA20_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA21` reader - Represents ch21 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA21_R = crate::BitReader; +#[doc = "Field `CH_ENA21` writer - Represents ch21 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA21_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA22` reader - Represents ch22 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA22_R = crate::BitReader; +#[doc = "Field `CH_ENA22` writer - Represents ch22 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA22_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA23` reader - Represents ch23 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA23_R = crate::BitReader; +#[doc = "Field `CH_ENA23` writer - Represents ch23 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA23_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA24` reader - Represents ch24 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA24_R = crate::BitReader; +#[doc = "Field `CH_ENA24` writer - Represents ch24 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA24_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA25` reader - Represents ch25 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA25_R = crate::BitReader; +#[doc = "Field `CH_ENA25` writer - Represents ch25 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA25_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA26` reader - Represents ch26 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA26_R = crate::BitReader; +#[doc = "Field `CH_ENA26` writer - Represents ch26 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA26_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA27` reader - Represents ch27 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA27_R = crate::BitReader; +#[doc = "Field `CH_ENA27` writer - Represents ch27 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA27_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA28` reader - Represents ch28 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA28_R = crate::BitReader; +#[doc = "Field `CH_ENA28` writer - Represents ch28 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA28_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA29` reader - Represents ch29 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA29_R = crate::BitReader; +#[doc = "Field `CH_ENA29` writer - Represents ch29 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA29_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA30` reader - Represents ch30 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA30_R = crate::BitReader; +#[doc = "Field `CH_ENA30` writer - Represents ch30 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA30_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA31` reader - Represents ch31 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA31_R = crate::BitReader; +#[doc = "Field `CH_ENA31` writer - Represents ch31 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA31_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents ch0 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena0(&self) -> CH_ENA0_R { + CH_ENA0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents ch1 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena1(&self) -> CH_ENA1_R { + CH_ENA1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents ch2 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena2(&self) -> CH_ENA2_R { + CH_ENA2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents ch3 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena3(&self) -> CH_ENA3_R { + CH_ENA3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents ch4 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena4(&self) -> CH_ENA4_R { + CH_ENA4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents ch5 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena5(&self) -> CH_ENA5_R { + CH_ENA5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents ch6 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena6(&self) -> CH_ENA6_R { + CH_ENA6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents ch7 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena7(&self) -> CH_ENA7_R { + CH_ENA7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents ch8 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena8(&self) -> CH_ENA8_R { + CH_ENA8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents ch9 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena9(&self) -> CH_ENA9_R { + CH_ENA9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents ch10 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena10(&self) -> CH_ENA10_R { + CH_ENA10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents ch11 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena11(&self) -> CH_ENA11_R { + CH_ENA11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents ch12 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena12(&self) -> CH_ENA12_R { + CH_ENA12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents ch13 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena13(&self) -> CH_ENA13_R { + CH_ENA13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents ch14 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena14(&self) -> CH_ENA14_R { + CH_ENA14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents ch15 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena15(&self) -> CH_ENA15_R { + CH_ENA15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents ch16 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena16(&self) -> CH_ENA16_R { + CH_ENA16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents ch17 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena17(&self) -> CH_ENA17_R { + CH_ENA17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents ch18 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena18(&self) -> CH_ENA18_R { + CH_ENA18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents ch19 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena19(&self) -> CH_ENA19_R { + CH_ENA19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents ch20 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena20(&self) -> CH_ENA20_R { + CH_ENA20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents ch21 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena21(&self) -> CH_ENA21_R { + CH_ENA21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents ch22 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena22(&self) -> CH_ENA22_R { + CH_ENA22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents ch23 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena23(&self) -> CH_ENA23_R { + CH_ENA23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents ch24 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena24(&self) -> CH_ENA24_R { + CH_ENA24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents ch25 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena25(&self) -> CH_ENA25_R { + CH_ENA25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents ch26 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena26(&self) -> CH_ENA26_R { + CH_ENA26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents ch27 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena27(&self) -> CH_ENA27_R { + CH_ENA27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents ch28 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena28(&self) -> CH_ENA28_R { + CH_ENA28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents ch29 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena29(&self) -> CH_ENA29_R { + CH_ENA29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents ch30 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena30(&self) -> CH_ENA30_R { + CH_ENA30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents ch31 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena31(&self) -> CH_ENA31_R { + CH_ENA31_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH_ENA_AD0") + .field("ch_ena0", &format_args!("{}", self.ch_ena0().bit())) + .field("ch_ena1", &format_args!("{}", self.ch_ena1().bit())) + .field("ch_ena2", &format_args!("{}", self.ch_ena2().bit())) + .field("ch_ena3", &format_args!("{}", self.ch_ena3().bit())) + .field("ch_ena4", &format_args!("{}", self.ch_ena4().bit())) + .field("ch_ena5", &format_args!("{}", self.ch_ena5().bit())) + .field("ch_ena6", &format_args!("{}", self.ch_ena6().bit())) + .field("ch_ena7", &format_args!("{}", self.ch_ena7().bit())) + .field("ch_ena8", &format_args!("{}", self.ch_ena8().bit())) + .field("ch_ena9", &format_args!("{}", self.ch_ena9().bit())) + .field("ch_ena10", &format_args!("{}", self.ch_ena10().bit())) + .field("ch_ena11", &format_args!("{}", self.ch_ena11().bit())) + .field("ch_ena12", &format_args!("{}", self.ch_ena12().bit())) + .field("ch_ena13", &format_args!("{}", self.ch_ena13().bit())) + .field("ch_ena14", &format_args!("{}", self.ch_ena14().bit())) + .field("ch_ena15", &format_args!("{}", self.ch_ena15().bit())) + .field("ch_ena16", &format_args!("{}", self.ch_ena16().bit())) + .field("ch_ena17", &format_args!("{}", self.ch_ena17().bit())) + .field("ch_ena18", &format_args!("{}", self.ch_ena18().bit())) + .field("ch_ena19", &format_args!("{}", self.ch_ena19().bit())) + .field("ch_ena20", &format_args!("{}", self.ch_ena20().bit())) + .field("ch_ena21", &format_args!("{}", self.ch_ena21().bit())) + .field("ch_ena22", &format_args!("{}", self.ch_ena22().bit())) + .field("ch_ena23", &format_args!("{}", self.ch_ena23().bit())) + .field("ch_ena24", &format_args!("{}", self.ch_ena24().bit())) + .field("ch_ena25", &format_args!("{}", self.ch_ena25().bit())) + .field("ch_ena26", &format_args!("{}", self.ch_ena26().bit())) + .field("ch_ena27", &format_args!("{}", self.ch_ena27().bit())) + .field("ch_ena28", &format_args!("{}", self.ch_ena28().bit())) + .field("ch_ena29", &format_args!("{}", self.ch_ena29().bit())) + .field("ch_ena30", &format_args!("{}", self.ch_ena30().bit())) + .field("ch_ena31", &format_args!("{}", self.ch_ena31().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents ch0 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena0(&mut self) -> CH_ENA0_W { + CH_ENA0_W::new(self, 0) + } + #[doc = "Bit 1 - Represents ch1 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena1(&mut self) -> CH_ENA1_W { + CH_ENA1_W::new(self, 1) + } + #[doc = "Bit 2 - Represents ch2 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena2(&mut self) -> CH_ENA2_W { + CH_ENA2_W::new(self, 2) + } + #[doc = "Bit 3 - Represents ch3 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena3(&mut self) -> CH_ENA3_W { + CH_ENA3_W::new(self, 3) + } + #[doc = "Bit 4 - Represents ch4 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena4(&mut self) -> CH_ENA4_W { + CH_ENA4_W::new(self, 4) + } + #[doc = "Bit 5 - Represents ch5 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena5(&mut self) -> CH_ENA5_W { + CH_ENA5_W::new(self, 5) + } + #[doc = "Bit 6 - Represents ch6 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena6(&mut self) -> CH_ENA6_W { + CH_ENA6_W::new(self, 6) + } + #[doc = "Bit 7 - Represents ch7 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena7(&mut self) -> CH_ENA7_W { + CH_ENA7_W::new(self, 7) + } + #[doc = "Bit 8 - Represents ch8 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena8(&mut self) -> CH_ENA8_W { + CH_ENA8_W::new(self, 8) + } + #[doc = "Bit 9 - Represents ch9 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena9(&mut self) -> CH_ENA9_W { + CH_ENA9_W::new(self, 9) + } + #[doc = "Bit 10 - Represents ch10 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena10(&mut self) -> CH_ENA10_W { + CH_ENA10_W::new(self, 10) + } + #[doc = "Bit 11 - Represents ch11 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena11(&mut self) -> CH_ENA11_W { + CH_ENA11_W::new(self, 11) + } + #[doc = "Bit 12 - Represents ch12 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena12(&mut self) -> CH_ENA12_W { + CH_ENA12_W::new(self, 12) + } + #[doc = "Bit 13 - Represents ch13 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena13(&mut self) -> CH_ENA13_W { + CH_ENA13_W::new(self, 13) + } + #[doc = "Bit 14 - Represents ch14 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena14(&mut self) -> CH_ENA14_W { + CH_ENA14_W::new(self, 14) + } + #[doc = "Bit 15 - Represents ch15 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena15(&mut self) -> CH_ENA15_W { + CH_ENA15_W::new(self, 15) + } + #[doc = "Bit 16 - Represents ch16 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena16(&mut self) -> CH_ENA16_W { + CH_ENA16_W::new(self, 16) + } + #[doc = "Bit 17 - Represents ch17 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena17(&mut self) -> CH_ENA17_W { + CH_ENA17_W::new(self, 17) + } + #[doc = "Bit 18 - Represents ch18 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena18(&mut self) -> CH_ENA18_W { + CH_ENA18_W::new(self, 18) + } + #[doc = "Bit 19 - Represents ch19 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena19(&mut self) -> CH_ENA19_W { + CH_ENA19_W::new(self, 19) + } + #[doc = "Bit 20 - Represents ch20 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena20(&mut self) -> CH_ENA20_W { + CH_ENA20_W::new(self, 20) + } + #[doc = "Bit 21 - Represents ch21 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena21(&mut self) -> CH_ENA21_W { + CH_ENA21_W::new(self, 21) + } + #[doc = "Bit 22 - Represents ch22 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena22(&mut self) -> CH_ENA22_W { + CH_ENA22_W::new(self, 22) + } + #[doc = "Bit 23 - Represents ch23 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena23(&mut self) -> CH_ENA23_W { + CH_ENA23_W::new(self, 23) + } + #[doc = "Bit 24 - Represents ch24 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena24(&mut self) -> CH_ENA24_W { + CH_ENA24_W::new(self, 24) + } + #[doc = "Bit 25 - Represents ch25 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena25(&mut self) -> CH_ENA25_W { + CH_ENA25_W::new(self, 25) + } + #[doc = "Bit 26 - Represents ch26 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena26(&mut self) -> CH_ENA26_W { + CH_ENA26_W::new(self, 26) + } + #[doc = "Bit 27 - Represents ch27 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena27(&mut self) -> CH_ENA27_W { + CH_ENA27_W::new(self, 27) + } + #[doc = "Bit 28 - Represents ch28 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena28(&mut self) -> CH_ENA28_W { + CH_ENA28_W::new(self, 28) + } + #[doc = "Bit 29 - Represents ch29 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena29(&mut self) -> CH_ENA29_W { + CH_ENA29_W::new(self, 29) + } + #[doc = "Bit 30 - Represents ch30 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena30(&mut self) -> CH_ENA30_W { + CH_ENA30_W::new(self, 30) + } + #[doc = "Bit 31 - Represents ch31 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena31(&mut self) -> CH_ENA31_W { + CH_ENA31_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel enable status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_ena_ad0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_ENA_AD0_SPEC; +impl crate::RegisterSpec for CH_ENA_AD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_ena_ad0::R`](R) reader structure"] +impl crate::Readable for CH_ENA_AD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_ena_ad0::W`](W) writer structure"] +impl crate::Writable for CH_ENA_AD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH_ENA_AD0 to value 0"] +impl crate::Resettable for CH_ENA_AD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch_ena_ad0_clr.rs b/esp32p4/src/soc_etm/ch_ena_ad0_clr.rs new file mode 100644 index 0000000000..36448d3df9 --- /dev/null +++ b/esp32p4/src/soc_etm/ch_ena_ad0_clr.rs @@ -0,0 +1,290 @@ +#[doc = "Register `CH_ENA_AD0_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH_CLR0` writer - Configures whether or not to clear ch0 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR1` writer - Configures whether or not to clear ch1 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR2` writer - Configures whether or not to clear ch2 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR3` writer - Configures whether or not to clear ch3 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR4` writer - Configures whether or not to clear ch4 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR5` writer - Configures whether or not to clear ch5 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR6` writer - Configures whether or not to clear ch6 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR7` writer - Configures whether or not to clear ch7 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR8` writer - Configures whether or not to clear ch8 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR9` writer - Configures whether or not to clear ch9 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR10` writer - Configures whether or not to clear ch10 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR11` writer - Configures whether or not to clear ch11 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR12` writer - Configures whether or not to clear ch12 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR13` writer - Configures whether or not to clear ch13 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR14` writer - Configures whether or not to clear ch14 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR15` writer - Configures whether or not to clear ch15 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR15_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR16` writer - Configures whether or not to clear ch16 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR16_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR17` writer - Configures whether or not to clear ch17 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR17_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR18` writer - Configures whether or not to clear ch18 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR18_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR19` writer - Configures whether or not to clear ch19 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR19_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR20` writer - Configures whether or not to clear ch20 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR20_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR21` writer - Configures whether or not to clear ch21 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR21_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR22` writer - Configures whether or not to clear ch22 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR22_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR23` writer - Configures whether or not to clear ch23 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR23_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR24` writer - Configures whether or not to clear ch24 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR24_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR25` writer - Configures whether or not to clear ch25 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR25_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR26` writer - Configures whether or not to clear ch26 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR26_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR27` writer - Configures whether or not to clear ch27 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR27_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR28` writer - Configures whether or not to clear ch28 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR28_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR29` writer - Configures whether or not to clear ch29 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR29_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR30` writer - Configures whether or not to clear ch30 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR30_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR31` writer - Configures whether or not to clear ch31 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR31_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear ch0 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr0(&mut self) -> CH_CLR0_W { + CH_CLR0_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear ch1 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr1(&mut self) -> CH_CLR1_W { + CH_CLR1_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear ch2 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr2(&mut self) -> CH_CLR2_W { + CH_CLR2_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear ch3 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr3(&mut self) -> CH_CLR3_W { + CH_CLR3_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear ch4 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr4(&mut self) -> CH_CLR4_W { + CH_CLR4_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear ch5 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr5(&mut self) -> CH_CLR5_W { + CH_CLR5_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear ch6 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr6(&mut self) -> CH_CLR6_W { + CH_CLR6_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear ch7 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr7(&mut self) -> CH_CLR7_W { + CH_CLR7_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear ch8 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr8(&mut self) -> CH_CLR8_W { + CH_CLR8_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear ch9 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr9(&mut self) -> CH_CLR9_W { + CH_CLR9_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear ch10 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr10(&mut self) -> CH_CLR10_W { + CH_CLR10_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear ch11 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr11(&mut self) -> CH_CLR11_W { + CH_CLR11_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear ch12 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr12(&mut self) -> CH_CLR12_W { + CH_CLR12_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear ch13 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr13(&mut self) -> CH_CLR13_W { + CH_CLR13_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear ch14 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr14(&mut self) -> CH_CLR14_W { + CH_CLR14_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear ch15 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr15(&mut self) -> CH_CLR15_W { + CH_CLR15_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear ch16 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr16(&mut self) -> CH_CLR16_W { + CH_CLR16_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear ch17 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr17(&mut self) -> CH_CLR17_W { + CH_CLR17_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear ch18 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr18(&mut self) -> CH_CLR18_W { + CH_CLR18_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear ch19 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr19(&mut self) -> CH_CLR19_W { + CH_CLR19_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear ch20 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr20(&mut self) -> CH_CLR20_W { + CH_CLR20_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear ch21 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr21(&mut self) -> CH_CLR21_W { + CH_CLR21_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear ch22 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr22(&mut self) -> CH_CLR22_W { + CH_CLR22_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear ch23 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr23(&mut self) -> CH_CLR23_W { + CH_CLR23_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear ch24 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr24(&mut self) -> CH_CLR24_W { + CH_CLR24_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear ch25 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr25(&mut self) -> CH_CLR25_W { + CH_CLR25_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear ch26 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr26(&mut self) -> CH_CLR26_W { + CH_CLR26_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear ch27 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr27(&mut self) -> CH_CLR27_W { + CH_CLR27_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear ch28 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr28(&mut self) -> CH_CLR28_W { + CH_CLR28_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear ch29 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr29(&mut self) -> CH_CLR29_W { + CH_CLR29_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear ch30 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr30(&mut self) -> CH_CLR30_W { + CH_CLR30_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear ch31 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr31(&mut self) -> CH_CLR31_W { + CH_CLR31_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel enable clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad0_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_ENA_AD0_CLR_SPEC; +impl crate::RegisterSpec for CH_ENA_AD0_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch_ena_ad0_clr::W`](W) writer structure"] +impl crate::Writable for CH_ENA_AD0_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH_ENA_AD0_CLR to value 0"] +impl crate::Resettable for CH_ENA_AD0_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch_ena_ad0_set.rs b/esp32p4/src/soc_etm/ch_ena_ad0_set.rs new file mode 100644 index 0000000000..01ab5958a6 --- /dev/null +++ b/esp32p4/src/soc_etm/ch_ena_ad0_set.rs @@ -0,0 +1,290 @@ +#[doc = "Register `CH_ENA_AD0_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH_SET0` writer - Configures whether or not to enable ch0.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET1` writer - Configures whether or not to enable ch1.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET2` writer - Configures whether or not to enable ch2.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET3` writer - Configures whether or not to enable ch3.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET4` writer - Configures whether or not to enable ch4.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET5` writer - Configures whether or not to enable ch5.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET6` writer - Configures whether or not to enable ch6.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET7` writer - Configures whether or not to enable ch7.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET8` writer - Configures whether or not to enable ch8.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET9` writer - Configures whether or not to enable ch9.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET10` writer - Configures whether or not to enable ch10.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET11` writer - Configures whether or not to enable ch11.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET11_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET12` writer - Configures whether or not to enable ch12.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET12_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET13` writer - Configures whether or not to enable ch13.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET14` writer - Configures whether or not to enable ch14.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET14_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET15` writer - Configures whether or not to enable ch15.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET15_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET16` writer - Configures whether or not to enable ch16.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET16_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET17` writer - Configures whether or not to enable ch17.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET17_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET18` writer - Configures whether or not to enable ch18.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET18_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET19` writer - Configures whether or not to enable ch19.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET19_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET20` writer - Configures whether or not to enable ch20.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET20_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET21` writer - Configures whether or not to enable ch21.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET21_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET22` writer - Configures whether or not to enable ch22.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET22_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET23` writer - Configures whether or not to enable ch23.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET23_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET24` writer - Configures whether or not to enable ch24.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET24_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET25` writer - Configures whether or not to enable ch25.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET25_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET26` writer - Configures whether or not to enable ch26.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET26_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET27` writer - Configures whether or not to enable ch27.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET27_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET28` writer - Configures whether or not to enable ch28.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET28_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET29` writer - Configures whether or not to enable ch29.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET29_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET30` writer - Configures whether or not to enable ch30.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET30_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET31` writer - Configures whether or not to enable ch31.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET31_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable ch0.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set0(&mut self) -> CH_SET0_W { + CH_SET0_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to enable ch1.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set1(&mut self) -> CH_SET1_W { + CH_SET1_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to enable ch2.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set2(&mut self) -> CH_SET2_W { + CH_SET2_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to enable ch3.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set3(&mut self) -> CH_SET3_W { + CH_SET3_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to enable ch4.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set4(&mut self) -> CH_SET4_W { + CH_SET4_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to enable ch5.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set5(&mut self) -> CH_SET5_W { + CH_SET5_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to enable ch6.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set6(&mut self) -> CH_SET6_W { + CH_SET6_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to enable ch7.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set7(&mut self) -> CH_SET7_W { + CH_SET7_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to enable ch8.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set8(&mut self) -> CH_SET8_W { + CH_SET8_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to enable ch9.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set9(&mut self) -> CH_SET9_W { + CH_SET9_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to enable ch10.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set10(&mut self) -> CH_SET10_W { + CH_SET10_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to enable ch11.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set11(&mut self) -> CH_SET11_W { + CH_SET11_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to enable ch12.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set12(&mut self) -> CH_SET12_W { + CH_SET12_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to enable ch13.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set13(&mut self) -> CH_SET13_W { + CH_SET13_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to enable ch14.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set14(&mut self) -> CH_SET14_W { + CH_SET14_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to enable ch15.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set15(&mut self) -> CH_SET15_W { + CH_SET15_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to enable ch16.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set16(&mut self) -> CH_SET16_W { + CH_SET16_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to enable ch17.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set17(&mut self) -> CH_SET17_W { + CH_SET17_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to enable ch18.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set18(&mut self) -> CH_SET18_W { + CH_SET18_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to enable ch19.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set19(&mut self) -> CH_SET19_W { + CH_SET19_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to enable ch20.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set20(&mut self) -> CH_SET20_W { + CH_SET20_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to enable ch21.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set21(&mut self) -> CH_SET21_W { + CH_SET21_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to enable ch22.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set22(&mut self) -> CH_SET22_W { + CH_SET22_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to enable ch23.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set23(&mut self) -> CH_SET23_W { + CH_SET23_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to enable ch24.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set24(&mut self) -> CH_SET24_W { + CH_SET24_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to enable ch25.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set25(&mut self) -> CH_SET25_W { + CH_SET25_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to enable ch26.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set26(&mut self) -> CH_SET26_W { + CH_SET26_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to enable ch27.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set27(&mut self) -> CH_SET27_W { + CH_SET27_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to enable ch28.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set28(&mut self) -> CH_SET28_W { + CH_SET28_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to enable ch29.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set29(&mut self) -> CH_SET29_W { + CH_SET29_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to enable ch30.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set30(&mut self) -> CH_SET30_W { + CH_SET30_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to enable ch31.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set31(&mut self) -> CH_SET31_W { + CH_SET31_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel enable set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad0_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_ENA_AD0_SET_SPEC; +impl crate::RegisterSpec for CH_ENA_AD0_SET_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch_ena_ad0_set::W`](W) writer structure"] +impl crate::Writable for CH_ENA_AD0_SET_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH_ENA_AD0_SET to value 0"] +impl crate::Resettable for CH_ENA_AD0_SET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch_ena_ad1.rs b/esp32p4/src/soc_etm/ch_ena_ad1.rs new file mode 100644 index 0000000000..fd37b18769 --- /dev/null +++ b/esp32p4/src/soc_etm/ch_ena_ad1.rs @@ -0,0 +1,335 @@ +#[doc = "Register `CH_ENA_AD1` reader"] +pub type R = crate::R; +#[doc = "Register `CH_ENA_AD1` writer"] +pub type W = crate::W; +#[doc = "Field `CH_ENA32` reader - Represents ch32 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA32_R = crate::BitReader; +#[doc = "Field `CH_ENA32` writer - Represents ch32 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA32_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA33` reader - Represents ch33 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA33_R = crate::BitReader; +#[doc = "Field `CH_ENA33` writer - Represents ch33 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA33_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA34` reader - Represents ch34 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA34_R = crate::BitReader; +#[doc = "Field `CH_ENA34` writer - Represents ch34 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA34_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA35` reader - Represents ch35 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA35_R = crate::BitReader; +#[doc = "Field `CH_ENA35` writer - Represents ch35 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA35_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA36` reader - Represents ch36 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA36_R = crate::BitReader; +#[doc = "Field `CH_ENA36` writer - Represents ch36 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA36_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA37` reader - Represents ch37 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA37_R = crate::BitReader; +#[doc = "Field `CH_ENA37` writer - Represents ch37 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA37_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA38` reader - Represents ch38 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA38_R = crate::BitReader; +#[doc = "Field `CH_ENA38` writer - Represents ch38 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA38_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA39` reader - Represents ch39 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA39_R = crate::BitReader; +#[doc = "Field `CH_ENA39` writer - Represents ch39 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA39_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA40` reader - Represents ch40 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA40_R = crate::BitReader; +#[doc = "Field `CH_ENA40` writer - Represents ch40 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA40_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA41` reader - Represents ch41 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA41_R = crate::BitReader; +#[doc = "Field `CH_ENA41` writer - Represents ch41 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA41_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA42` reader - Represents ch42 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA42_R = crate::BitReader; +#[doc = "Field `CH_ENA42` writer - Represents ch42 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA42_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA43` reader - Represents ch43 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA43_R = crate::BitReader; +#[doc = "Field `CH_ENA43` writer - Represents ch43 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA43_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA44` reader - Represents ch44 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA44_R = crate::BitReader; +#[doc = "Field `CH_ENA44` writer - Represents ch44 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA44_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA45` reader - Represents ch45 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA45_R = crate::BitReader; +#[doc = "Field `CH_ENA45` writer - Represents ch45 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA45_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA46` reader - Represents ch46 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA46_R = crate::BitReader; +#[doc = "Field `CH_ENA46` writer - Represents ch46 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA46_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA47` reader - Represents ch47 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA47_R = crate::BitReader; +#[doc = "Field `CH_ENA47` writer - Represents ch47 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA47_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA48` reader - Represents ch48 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA48_R = crate::BitReader; +#[doc = "Field `CH_ENA48` writer - Represents ch48 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA48_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_ENA49` reader - Represents ch49 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA49_R = crate::BitReader; +#[doc = "Field `CH_ENA49` writer - Represents ch49 enable status.\\\\0: Disable\\\\1: Enable"] +pub type CH_ENA49_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents ch32 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena32(&self) -> CH_ENA32_R { + CH_ENA32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents ch33 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena33(&self) -> CH_ENA33_R { + CH_ENA33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents ch34 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena34(&self) -> CH_ENA34_R { + CH_ENA34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents ch35 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena35(&self) -> CH_ENA35_R { + CH_ENA35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents ch36 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena36(&self) -> CH_ENA36_R { + CH_ENA36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents ch37 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena37(&self) -> CH_ENA37_R { + CH_ENA37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents ch38 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena38(&self) -> CH_ENA38_R { + CH_ENA38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents ch39 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena39(&self) -> CH_ENA39_R { + CH_ENA39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents ch40 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena40(&self) -> CH_ENA40_R { + CH_ENA40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents ch41 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena41(&self) -> CH_ENA41_R { + CH_ENA41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents ch42 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena42(&self) -> CH_ENA42_R { + CH_ENA42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents ch43 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena43(&self) -> CH_ENA43_R { + CH_ENA43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents ch44 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena44(&self) -> CH_ENA44_R { + CH_ENA44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents ch45 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena45(&self) -> CH_ENA45_R { + CH_ENA45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents ch46 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena46(&self) -> CH_ENA46_R { + CH_ENA46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents ch47 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena47(&self) -> CH_ENA47_R { + CH_ENA47_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents ch48 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena48(&self) -> CH_ENA48_R { + CH_ENA48_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents ch49 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + pub fn ch_ena49(&self) -> CH_ENA49_R { + CH_ENA49_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CH_ENA_AD1") + .field("ch_ena32", &format_args!("{}", self.ch_ena32().bit())) + .field("ch_ena33", &format_args!("{}", self.ch_ena33().bit())) + .field("ch_ena34", &format_args!("{}", self.ch_ena34().bit())) + .field("ch_ena35", &format_args!("{}", self.ch_ena35().bit())) + .field("ch_ena36", &format_args!("{}", self.ch_ena36().bit())) + .field("ch_ena37", &format_args!("{}", self.ch_ena37().bit())) + .field("ch_ena38", &format_args!("{}", self.ch_ena38().bit())) + .field("ch_ena39", &format_args!("{}", self.ch_ena39().bit())) + .field("ch_ena40", &format_args!("{}", self.ch_ena40().bit())) + .field("ch_ena41", &format_args!("{}", self.ch_ena41().bit())) + .field("ch_ena42", &format_args!("{}", self.ch_ena42().bit())) + .field("ch_ena43", &format_args!("{}", self.ch_ena43().bit())) + .field("ch_ena44", &format_args!("{}", self.ch_ena44().bit())) + .field("ch_ena45", &format_args!("{}", self.ch_ena45().bit())) + .field("ch_ena46", &format_args!("{}", self.ch_ena46().bit())) + .field("ch_ena47", &format_args!("{}", self.ch_ena47().bit())) + .field("ch_ena48", &format_args!("{}", self.ch_ena48().bit())) + .field("ch_ena49", &format_args!("{}", self.ch_ena49().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents ch32 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena32(&mut self) -> CH_ENA32_W { + CH_ENA32_W::new(self, 0) + } + #[doc = "Bit 1 - Represents ch33 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena33(&mut self) -> CH_ENA33_W { + CH_ENA33_W::new(self, 1) + } + #[doc = "Bit 2 - Represents ch34 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena34(&mut self) -> CH_ENA34_W { + CH_ENA34_W::new(self, 2) + } + #[doc = "Bit 3 - Represents ch35 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena35(&mut self) -> CH_ENA35_W { + CH_ENA35_W::new(self, 3) + } + #[doc = "Bit 4 - Represents ch36 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena36(&mut self) -> CH_ENA36_W { + CH_ENA36_W::new(self, 4) + } + #[doc = "Bit 5 - Represents ch37 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena37(&mut self) -> CH_ENA37_W { + CH_ENA37_W::new(self, 5) + } + #[doc = "Bit 6 - Represents ch38 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena38(&mut self) -> CH_ENA38_W { + CH_ENA38_W::new(self, 6) + } + #[doc = "Bit 7 - Represents ch39 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena39(&mut self) -> CH_ENA39_W { + CH_ENA39_W::new(self, 7) + } + #[doc = "Bit 8 - Represents ch40 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena40(&mut self) -> CH_ENA40_W { + CH_ENA40_W::new(self, 8) + } + #[doc = "Bit 9 - Represents ch41 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena41(&mut self) -> CH_ENA41_W { + CH_ENA41_W::new(self, 9) + } + #[doc = "Bit 10 - Represents ch42 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena42(&mut self) -> CH_ENA42_W { + CH_ENA42_W::new(self, 10) + } + #[doc = "Bit 11 - Represents ch43 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena43(&mut self) -> CH_ENA43_W { + CH_ENA43_W::new(self, 11) + } + #[doc = "Bit 12 - Represents ch44 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena44(&mut self) -> CH_ENA44_W { + CH_ENA44_W::new(self, 12) + } + #[doc = "Bit 13 - Represents ch45 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena45(&mut self) -> CH_ENA45_W { + CH_ENA45_W::new(self, 13) + } + #[doc = "Bit 14 - Represents ch46 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena46(&mut self) -> CH_ENA46_W { + CH_ENA46_W::new(self, 14) + } + #[doc = "Bit 15 - Represents ch47 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena47(&mut self) -> CH_ENA47_W { + CH_ENA47_W::new(self, 15) + } + #[doc = "Bit 16 - Represents ch48 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena48(&mut self) -> CH_ENA48_W { + CH_ENA48_W::new(self, 16) + } + #[doc = "Bit 17 - Represents ch49 enable status.\\\\0: Disable\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_ena49(&mut self) -> CH_ENA49_W { + CH_ENA49_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel enable status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_ena_ad1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_ENA_AD1_SPEC; +impl crate::RegisterSpec for CH_ENA_AD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_ena_ad1::R`](R) reader structure"] +impl crate::Readable for CH_ENA_AD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_ena_ad1::W`](W) writer structure"] +impl crate::Writable for CH_ENA_AD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH_ENA_AD1 to value 0"] +impl crate::Resettable for CH_ENA_AD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch_ena_ad1_clr.rs b/esp32p4/src/soc_etm/ch_ena_ad1_clr.rs new file mode 100644 index 0000000000..753e8ac4dc --- /dev/null +++ b/esp32p4/src/soc_etm/ch_ena_ad1_clr.rs @@ -0,0 +1,178 @@ +#[doc = "Register `CH_ENA_AD1_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH_CLR32` writer - Configures whether or not to clear ch32 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR32_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR33` writer - Configures whether or not to clear ch33 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR33_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR34` writer - Configures whether or not to clear ch34 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR34_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR35` writer - Configures whether or not to clear ch35 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR35_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR36` writer - Configures whether or not to clear ch36 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR36_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR37` writer - Configures whether or not to clear ch37 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR37_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR38` writer - Configures whether or not to clear ch38 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR38_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR39` writer - Configures whether or not to clear ch39 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR39_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR40` writer - Configures whether or not to clear ch40 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR40_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR41` writer - Configures whether or not to clear ch41 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR41_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR42` writer - Configures whether or not to clear ch42 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR42_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR43` writer - Configures whether or not to clear ch43 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR43_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR44` writer - Configures whether or not to clear ch44 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR44_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR45` writer - Configures whether or not to clear ch45 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR45_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR46` writer - Configures whether or not to clear ch46 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR46_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR47` writer - Configures whether or not to clear ch47 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR47_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR48` writer - Configures whether or not to clear ch48 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR48_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_CLR49` writer - Configures whether or not to clear ch49 enable.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type CH_CLR49_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear ch32 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr32(&mut self) -> CH_CLR32_W { + CH_CLR32_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear ch33 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr33(&mut self) -> CH_CLR33_W { + CH_CLR33_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear ch34 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr34(&mut self) -> CH_CLR34_W { + CH_CLR34_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear ch35 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr35(&mut self) -> CH_CLR35_W { + CH_CLR35_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear ch36 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr36(&mut self) -> CH_CLR36_W { + CH_CLR36_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear ch37 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr37(&mut self) -> CH_CLR37_W { + CH_CLR37_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear ch38 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr38(&mut self) -> CH_CLR38_W { + CH_CLR38_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear ch39 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr39(&mut self) -> CH_CLR39_W { + CH_CLR39_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear ch40 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr40(&mut self) -> CH_CLR40_W { + CH_CLR40_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear ch41 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr41(&mut self) -> CH_CLR41_W { + CH_CLR41_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear ch42 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr42(&mut self) -> CH_CLR42_W { + CH_CLR42_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear ch43 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr43(&mut self) -> CH_CLR43_W { + CH_CLR43_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear ch44 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr44(&mut self) -> CH_CLR44_W { + CH_CLR44_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear ch45 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr45(&mut self) -> CH_CLR45_W { + CH_CLR45_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear ch46 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr46(&mut self) -> CH_CLR46_W { + CH_CLR46_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear ch47 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr47(&mut self) -> CH_CLR47_W { + CH_CLR47_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear ch48 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr48(&mut self) -> CH_CLR48_W { + CH_CLR48_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear ch49 enable.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ch_clr49(&mut self) -> CH_CLR49_W { + CH_CLR49_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel enable clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad1_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_ENA_AD1_CLR_SPEC; +impl crate::RegisterSpec for CH_ENA_AD1_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch_ena_ad1_clr::W`](W) writer structure"] +impl crate::Writable for CH_ENA_AD1_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH_ENA_AD1_CLR to value 0"] +impl crate::Resettable for CH_ENA_AD1_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/ch_ena_ad1_set.rs b/esp32p4/src/soc_etm/ch_ena_ad1_set.rs new file mode 100644 index 0000000000..f8e9eb383e --- /dev/null +++ b/esp32p4/src/soc_etm/ch_ena_ad1_set.rs @@ -0,0 +1,178 @@ +#[doc = "Register `CH_ENA_AD1_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH_SET32` writer - Configures whether or not to enable ch32.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET32_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET33` writer - Configures whether or not to enable ch33.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET33_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET34` writer - Configures whether or not to enable ch34.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET34_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET35` writer - Configures whether or not to enable ch35.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET35_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET36` writer - Configures whether or not to enable ch36.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET36_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET37` writer - Configures whether or not to enable ch37.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET37_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET38` writer - Configures whether or not to enable ch38.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET38_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET39` writer - Configures whether or not to enable ch39.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET39_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET40` writer - Configures whether or not to enable ch40.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET40_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET41` writer - Configures whether or not to enable ch41.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET41_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET42` writer - Configures whether or not to enable ch42.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET42_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET43` writer - Configures whether or not to enable ch43.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET43_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET44` writer - Configures whether or not to enable ch44.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET44_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET45` writer - Configures whether or not to enable ch45.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET45_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET46` writer - Configures whether or not to enable ch46.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET46_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET47` writer - Configures whether or not to enable ch47.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET47_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET48` writer - Configures whether or not to enable ch48.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET48_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH_SET49` writer - Configures whether or not to enable ch49.\\\\0: Invalid, No effect\\\\1: Enable"] +pub type CH_SET49_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to enable ch32.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set32(&mut self) -> CH_SET32_W { + CH_SET32_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to enable ch33.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set33(&mut self) -> CH_SET33_W { + CH_SET33_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to enable ch34.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set34(&mut self) -> CH_SET34_W { + CH_SET34_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to enable ch35.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set35(&mut self) -> CH_SET35_W { + CH_SET35_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to enable ch36.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set36(&mut self) -> CH_SET36_W { + CH_SET36_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to enable ch37.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set37(&mut self) -> CH_SET37_W { + CH_SET37_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to enable ch38.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set38(&mut self) -> CH_SET38_W { + CH_SET38_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to enable ch39.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set39(&mut self) -> CH_SET39_W { + CH_SET39_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to enable ch40.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set40(&mut self) -> CH_SET40_W { + CH_SET40_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to enable ch41.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set41(&mut self) -> CH_SET41_W { + CH_SET41_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to enable ch42.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set42(&mut self) -> CH_SET42_W { + CH_SET42_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to enable ch43.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set43(&mut self) -> CH_SET43_W { + CH_SET43_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to enable ch44.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set44(&mut self) -> CH_SET44_W { + CH_SET44_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to enable ch45.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set45(&mut self) -> CH_SET45_W { + CH_SET45_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to enable ch46.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set46(&mut self) -> CH_SET46_W { + CH_SET46_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to enable ch47.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set47(&mut self) -> CH_SET47_W { + CH_SET47_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to enable ch48.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set48(&mut self) -> CH_SET48_W { + CH_SET48_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to enable ch49.\\\\0: Invalid, No effect\\\\1: Enable"] + #[inline(always)] + #[must_use] + pub fn ch_set49(&mut self) -> CH_SET49_W { + CH_SET49_W::new(self, 17) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Channel enable set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_ena_ad1_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_ENA_AD1_SET_SPEC; +impl crate::RegisterSpec for CH_ENA_AD1_SET_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ch_ena_ad1_set::W`](W) writer structure"] +impl crate::Writable for CH_ENA_AD1_SET_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CH_ENA_AD1_SET to value 0"] +impl crate::Resettable for CH_ENA_AD1_SET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/clk_en.rs b/esp32p4/src/soc_etm/clk_en.rs new file mode 100644 index 0000000000..a778575dc3 --- /dev/null +++ b/esp32p4/src/soc_etm/clk_en.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLK_EN` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_EN` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_EN") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ETM clock enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_EN_SPEC; +impl crate::RegisterSpec for CLK_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_en::R`](R) reader structure"] +impl crate::Readable for CLK_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_en::W`](W) writer structure"] +impl crate::Writable for CLK_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_EN to value 0"] +impl crate::Resettable for CLK_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/date.rs b/esp32p4/src/soc_etm/date.rs new file mode 100644 index 0000000000..e99ad6480f --- /dev/null +++ b/esp32p4/src/soc_etm/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - Configures the version."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - Configures the version."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Configures the version."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Configures the version."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ETM date register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_3031"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_3031; +} diff --git a/esp32p4/src/soc_etm/evt_st0.rs b/esp32p4/src/soc_etm/evt_st0.rs new file mode 100644 index 0000000000..1d144693c9 --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st0.rs @@ -0,0 +1,663 @@ +#[doc = "Register `EVT_ST0` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_ST0` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_EVT_CH0_RISE_EDGE_ST` reader - Represents GPIO_evt_ch0_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH0_RISE_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH0_RISE_EDGE_ST` writer - Represents GPIO_evt_ch0_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH0_RISE_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH1_RISE_EDGE_ST` reader - Represents GPIO_evt_ch1_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH1_RISE_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH1_RISE_EDGE_ST` writer - Represents GPIO_evt_ch1_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH1_RISE_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH2_RISE_EDGE_ST` reader - Represents GPIO_evt_ch2_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH2_RISE_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH2_RISE_EDGE_ST` writer - Represents GPIO_evt_ch2_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH2_RISE_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH3_RISE_EDGE_ST` reader - Represents GPIO_evt_ch3_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH3_RISE_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH3_RISE_EDGE_ST` writer - Represents GPIO_evt_ch3_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH3_RISE_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH4_RISE_EDGE_ST` reader - Represents GPIO_evt_ch4_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH4_RISE_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH4_RISE_EDGE_ST` writer - Represents GPIO_evt_ch4_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH4_RISE_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH5_RISE_EDGE_ST` reader - Represents GPIO_evt_ch5_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH5_RISE_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH5_RISE_EDGE_ST` writer - Represents GPIO_evt_ch5_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH5_RISE_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH6_RISE_EDGE_ST` reader - Represents GPIO_evt_ch6_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH6_RISE_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH6_RISE_EDGE_ST` writer - Represents GPIO_evt_ch6_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH6_RISE_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH7_RISE_EDGE_ST` reader - Represents GPIO_evt_ch7_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH7_RISE_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH7_RISE_EDGE_ST` writer - Represents GPIO_evt_ch7_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH7_RISE_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH0_FALL_EDGE_ST` reader - Represents GPIO_evt_ch0_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH0_FALL_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH0_FALL_EDGE_ST` writer - Represents GPIO_evt_ch0_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH0_FALL_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH1_FALL_EDGE_ST` reader - Represents GPIO_evt_ch1_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH1_FALL_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH1_FALL_EDGE_ST` writer - Represents GPIO_evt_ch1_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH1_FALL_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH2_FALL_EDGE_ST` reader - Represents GPIO_evt_ch2_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH2_FALL_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH2_FALL_EDGE_ST` writer - Represents GPIO_evt_ch2_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH2_FALL_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH3_FALL_EDGE_ST` reader - Represents GPIO_evt_ch3_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH3_FALL_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH3_FALL_EDGE_ST` writer - Represents GPIO_evt_ch3_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH3_FALL_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH4_FALL_EDGE_ST` reader - Represents GPIO_evt_ch4_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH4_FALL_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH4_FALL_EDGE_ST` writer - Represents GPIO_evt_ch4_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH4_FALL_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH5_FALL_EDGE_ST` reader - Represents GPIO_evt_ch5_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH5_FALL_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH5_FALL_EDGE_ST` writer - Represents GPIO_evt_ch5_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH5_FALL_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH6_FALL_EDGE_ST` reader - Represents GPIO_evt_ch6_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH6_FALL_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH6_FALL_EDGE_ST` writer - Represents GPIO_evt_ch6_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH6_FALL_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH7_FALL_EDGE_ST` reader - Represents GPIO_evt_ch7_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH7_FALL_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH7_FALL_EDGE_ST` writer - Represents GPIO_evt_ch7_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH7_FALL_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH0_ANY_EDGE_ST` reader - Represents GPIO_evt_ch0_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH0_ANY_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH0_ANY_EDGE_ST` writer - Represents GPIO_evt_ch0_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH0_ANY_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH1_ANY_EDGE_ST` reader - Represents GPIO_evt_ch1_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH1_ANY_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH1_ANY_EDGE_ST` writer - Represents GPIO_evt_ch1_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH1_ANY_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH2_ANY_EDGE_ST` reader - Represents GPIO_evt_ch2_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH2_ANY_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH2_ANY_EDGE_ST` writer - Represents GPIO_evt_ch2_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH2_ANY_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH3_ANY_EDGE_ST` reader - Represents GPIO_evt_ch3_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH3_ANY_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH3_ANY_EDGE_ST` writer - Represents GPIO_evt_ch3_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH3_ANY_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH4_ANY_EDGE_ST` reader - Represents GPIO_evt_ch4_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH4_ANY_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH4_ANY_EDGE_ST` writer - Represents GPIO_evt_ch4_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH4_ANY_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH5_ANY_EDGE_ST` reader - Represents GPIO_evt_ch5_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH5_ANY_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH5_ANY_EDGE_ST` writer - Represents GPIO_evt_ch5_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH5_ANY_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH6_ANY_EDGE_ST` reader - Represents GPIO_evt_ch6_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH6_ANY_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH6_ANY_EDGE_ST` writer - Represents GPIO_evt_ch6_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH6_ANY_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH7_ANY_EDGE_ST` reader - Represents GPIO_evt_ch7_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH7_ANY_EDGE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_CH7_ANY_EDGE_ST` writer - Represents GPIO_evt_ch7_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_CH7_ANY_EDGE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_ZERO_DET_POS0_ST` reader - Represents GPIO_evt_zero_det_pos0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_ZERO_DET_POS0_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_ZERO_DET_POS0_ST` writer - Represents GPIO_evt_zero_det_pos0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_ZERO_DET_POS0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_ZERO_DET_NEG0_ST` reader - Represents GPIO_evt_zero_det_neg0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_ZERO_DET_NEG0_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_ZERO_DET_NEG0_ST` writer - Represents GPIO_evt_zero_det_neg0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_ZERO_DET_NEG0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_ZERO_DET_POS1_ST` reader - Represents GPIO_evt_zero_det_pos1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_ZERO_DET_POS1_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_ZERO_DET_POS1_ST` writer - Represents GPIO_evt_zero_det_pos1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_ZERO_DET_POS1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_ZERO_DET_NEG1_ST` reader - Represents GPIO_evt_zero_det_neg1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_ZERO_DET_NEG1_ST_R = crate::BitReader; +#[doc = "Field `GPIO_EVT_ZERO_DET_NEG1_ST` writer - Represents GPIO_evt_zero_det_neg1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_EVT_ZERO_DET_NEG1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH0_ST` reader - Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH0_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH0_ST` writer - Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH1_ST` reader - Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH1_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH1_ST` writer - Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH2_ST` reader - Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH2_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH2_ST` writer - Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH3_ST` reader - Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH3_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH3_ST` writer - Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents GPIO_evt_ch0_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch0_rise_edge_st(&self) -> GPIO_EVT_CH0_RISE_EDGE_ST_R { + GPIO_EVT_CH0_RISE_EDGE_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents GPIO_evt_ch1_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch1_rise_edge_st(&self) -> GPIO_EVT_CH1_RISE_EDGE_ST_R { + GPIO_EVT_CH1_RISE_EDGE_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents GPIO_evt_ch2_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch2_rise_edge_st(&self) -> GPIO_EVT_CH2_RISE_EDGE_ST_R { + GPIO_EVT_CH2_RISE_EDGE_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents GPIO_evt_ch3_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch3_rise_edge_st(&self) -> GPIO_EVT_CH3_RISE_EDGE_ST_R { + GPIO_EVT_CH3_RISE_EDGE_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents GPIO_evt_ch4_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch4_rise_edge_st(&self) -> GPIO_EVT_CH4_RISE_EDGE_ST_R { + GPIO_EVT_CH4_RISE_EDGE_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents GPIO_evt_ch5_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch5_rise_edge_st(&self) -> GPIO_EVT_CH5_RISE_EDGE_ST_R { + GPIO_EVT_CH5_RISE_EDGE_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents GPIO_evt_ch6_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch6_rise_edge_st(&self) -> GPIO_EVT_CH6_RISE_EDGE_ST_R { + GPIO_EVT_CH6_RISE_EDGE_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents GPIO_evt_ch7_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch7_rise_edge_st(&self) -> GPIO_EVT_CH7_RISE_EDGE_ST_R { + GPIO_EVT_CH7_RISE_EDGE_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents GPIO_evt_ch0_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch0_fall_edge_st(&self) -> GPIO_EVT_CH0_FALL_EDGE_ST_R { + GPIO_EVT_CH0_FALL_EDGE_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents GPIO_evt_ch1_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch1_fall_edge_st(&self) -> GPIO_EVT_CH1_FALL_EDGE_ST_R { + GPIO_EVT_CH1_FALL_EDGE_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents GPIO_evt_ch2_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch2_fall_edge_st(&self) -> GPIO_EVT_CH2_FALL_EDGE_ST_R { + GPIO_EVT_CH2_FALL_EDGE_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents GPIO_evt_ch3_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch3_fall_edge_st(&self) -> GPIO_EVT_CH3_FALL_EDGE_ST_R { + GPIO_EVT_CH3_FALL_EDGE_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents GPIO_evt_ch4_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch4_fall_edge_st(&self) -> GPIO_EVT_CH4_FALL_EDGE_ST_R { + GPIO_EVT_CH4_FALL_EDGE_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents GPIO_evt_ch5_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch5_fall_edge_st(&self) -> GPIO_EVT_CH5_FALL_EDGE_ST_R { + GPIO_EVT_CH5_FALL_EDGE_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents GPIO_evt_ch6_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch6_fall_edge_st(&self) -> GPIO_EVT_CH6_FALL_EDGE_ST_R { + GPIO_EVT_CH6_FALL_EDGE_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents GPIO_evt_ch7_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch7_fall_edge_st(&self) -> GPIO_EVT_CH7_FALL_EDGE_ST_R { + GPIO_EVT_CH7_FALL_EDGE_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents GPIO_evt_ch0_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch0_any_edge_st(&self) -> GPIO_EVT_CH0_ANY_EDGE_ST_R { + GPIO_EVT_CH0_ANY_EDGE_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents GPIO_evt_ch1_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch1_any_edge_st(&self) -> GPIO_EVT_CH1_ANY_EDGE_ST_R { + GPIO_EVT_CH1_ANY_EDGE_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents GPIO_evt_ch2_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch2_any_edge_st(&self) -> GPIO_EVT_CH2_ANY_EDGE_ST_R { + GPIO_EVT_CH2_ANY_EDGE_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents GPIO_evt_ch3_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch3_any_edge_st(&self) -> GPIO_EVT_CH3_ANY_EDGE_ST_R { + GPIO_EVT_CH3_ANY_EDGE_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents GPIO_evt_ch4_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch4_any_edge_st(&self) -> GPIO_EVT_CH4_ANY_EDGE_ST_R { + GPIO_EVT_CH4_ANY_EDGE_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents GPIO_evt_ch5_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch5_any_edge_st(&self) -> GPIO_EVT_CH5_ANY_EDGE_ST_R { + GPIO_EVT_CH5_ANY_EDGE_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents GPIO_evt_ch6_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch6_any_edge_st(&self) -> GPIO_EVT_CH6_ANY_EDGE_ST_R { + GPIO_EVT_CH6_ANY_EDGE_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents GPIO_evt_ch7_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_ch7_any_edge_st(&self) -> GPIO_EVT_CH7_ANY_EDGE_ST_R { + GPIO_EVT_CH7_ANY_EDGE_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents GPIO_evt_zero_det_pos0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_zero_det_pos0_st(&self) -> GPIO_EVT_ZERO_DET_POS0_ST_R { + GPIO_EVT_ZERO_DET_POS0_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents GPIO_evt_zero_det_neg0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_zero_det_neg0_st(&self) -> GPIO_EVT_ZERO_DET_NEG0_ST_R { + GPIO_EVT_ZERO_DET_NEG0_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents GPIO_evt_zero_det_pos1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_zero_det_pos1_st(&self) -> GPIO_EVT_ZERO_DET_POS1_ST_R { + GPIO_EVT_ZERO_DET_POS1_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents GPIO_evt_zero_det_neg1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_evt_zero_det_neg1_st(&self) -> GPIO_EVT_ZERO_DET_NEG1_ST_R { + GPIO_EVT_ZERO_DET_NEG1_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_duty_chng_end_ch0_st(&self) -> LEDC_EVT_DUTY_CHNG_END_CH0_ST_R { + LEDC_EVT_DUTY_CHNG_END_CH0_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_duty_chng_end_ch1_st(&self) -> LEDC_EVT_DUTY_CHNG_END_CH1_ST_R { + LEDC_EVT_DUTY_CHNG_END_CH1_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_duty_chng_end_ch2_st(&self) -> LEDC_EVT_DUTY_CHNG_END_CH2_ST_R { + LEDC_EVT_DUTY_CHNG_END_CH2_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_duty_chng_end_ch3_st(&self) -> LEDC_EVT_DUTY_CHNG_END_CH3_ST_R { + LEDC_EVT_DUTY_CHNG_END_CH3_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_ST0") + .field( + "gpio_evt_ch0_rise_edge_st", + &format_args!("{}", self.gpio_evt_ch0_rise_edge_st().bit()), + ) + .field( + "gpio_evt_ch1_rise_edge_st", + &format_args!("{}", self.gpio_evt_ch1_rise_edge_st().bit()), + ) + .field( + "gpio_evt_ch2_rise_edge_st", + &format_args!("{}", self.gpio_evt_ch2_rise_edge_st().bit()), + ) + .field( + "gpio_evt_ch3_rise_edge_st", + &format_args!("{}", self.gpio_evt_ch3_rise_edge_st().bit()), + ) + .field( + "gpio_evt_ch4_rise_edge_st", + &format_args!("{}", self.gpio_evt_ch4_rise_edge_st().bit()), + ) + .field( + "gpio_evt_ch5_rise_edge_st", + &format_args!("{}", self.gpio_evt_ch5_rise_edge_st().bit()), + ) + .field( + "gpio_evt_ch6_rise_edge_st", + &format_args!("{}", self.gpio_evt_ch6_rise_edge_st().bit()), + ) + .field( + "gpio_evt_ch7_rise_edge_st", + &format_args!("{}", self.gpio_evt_ch7_rise_edge_st().bit()), + ) + .field( + "gpio_evt_ch0_fall_edge_st", + &format_args!("{}", self.gpio_evt_ch0_fall_edge_st().bit()), + ) + .field( + "gpio_evt_ch1_fall_edge_st", + &format_args!("{}", self.gpio_evt_ch1_fall_edge_st().bit()), + ) + .field( + "gpio_evt_ch2_fall_edge_st", + &format_args!("{}", self.gpio_evt_ch2_fall_edge_st().bit()), + ) + .field( + "gpio_evt_ch3_fall_edge_st", + &format_args!("{}", self.gpio_evt_ch3_fall_edge_st().bit()), + ) + .field( + "gpio_evt_ch4_fall_edge_st", + &format_args!("{}", self.gpio_evt_ch4_fall_edge_st().bit()), + ) + .field( + "gpio_evt_ch5_fall_edge_st", + &format_args!("{}", self.gpio_evt_ch5_fall_edge_st().bit()), + ) + .field( + "gpio_evt_ch6_fall_edge_st", + &format_args!("{}", self.gpio_evt_ch6_fall_edge_st().bit()), + ) + .field( + "gpio_evt_ch7_fall_edge_st", + &format_args!("{}", self.gpio_evt_ch7_fall_edge_st().bit()), + ) + .field( + "gpio_evt_ch0_any_edge_st", + &format_args!("{}", self.gpio_evt_ch0_any_edge_st().bit()), + ) + .field( + "gpio_evt_ch1_any_edge_st", + &format_args!("{}", self.gpio_evt_ch1_any_edge_st().bit()), + ) + .field( + "gpio_evt_ch2_any_edge_st", + &format_args!("{}", self.gpio_evt_ch2_any_edge_st().bit()), + ) + .field( + "gpio_evt_ch3_any_edge_st", + &format_args!("{}", self.gpio_evt_ch3_any_edge_st().bit()), + ) + .field( + "gpio_evt_ch4_any_edge_st", + &format_args!("{}", self.gpio_evt_ch4_any_edge_st().bit()), + ) + .field( + "gpio_evt_ch5_any_edge_st", + &format_args!("{}", self.gpio_evt_ch5_any_edge_st().bit()), + ) + .field( + "gpio_evt_ch6_any_edge_st", + &format_args!("{}", self.gpio_evt_ch6_any_edge_st().bit()), + ) + .field( + "gpio_evt_ch7_any_edge_st", + &format_args!("{}", self.gpio_evt_ch7_any_edge_st().bit()), + ) + .field( + "gpio_evt_zero_det_pos0_st", + &format_args!("{}", self.gpio_evt_zero_det_pos0_st().bit()), + ) + .field( + "gpio_evt_zero_det_neg0_st", + &format_args!("{}", self.gpio_evt_zero_det_neg0_st().bit()), + ) + .field( + "gpio_evt_zero_det_pos1_st", + &format_args!("{}", self.gpio_evt_zero_det_pos1_st().bit()), + ) + .field( + "gpio_evt_zero_det_neg1_st", + &format_args!("{}", self.gpio_evt_zero_det_neg1_st().bit()), + ) + .field( + "ledc_evt_duty_chng_end_ch0_st", + &format_args!("{}", self.ledc_evt_duty_chng_end_ch0_st().bit()), + ) + .field( + "ledc_evt_duty_chng_end_ch1_st", + &format_args!("{}", self.ledc_evt_duty_chng_end_ch1_st().bit()), + ) + .field( + "ledc_evt_duty_chng_end_ch2_st", + &format_args!("{}", self.ledc_evt_duty_chng_end_ch2_st().bit()), + ) + .field( + "ledc_evt_duty_chng_end_ch3_st", + &format_args!("{}", self.ledc_evt_duty_chng_end_ch3_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents GPIO_evt_ch0_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch0_rise_edge_st(&mut self) -> GPIO_EVT_CH0_RISE_EDGE_ST_W { + GPIO_EVT_CH0_RISE_EDGE_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents GPIO_evt_ch1_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch1_rise_edge_st(&mut self) -> GPIO_EVT_CH1_RISE_EDGE_ST_W { + GPIO_EVT_CH1_RISE_EDGE_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents GPIO_evt_ch2_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch2_rise_edge_st(&mut self) -> GPIO_EVT_CH2_RISE_EDGE_ST_W { + GPIO_EVT_CH2_RISE_EDGE_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents GPIO_evt_ch3_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch3_rise_edge_st(&mut self) -> GPIO_EVT_CH3_RISE_EDGE_ST_W { + GPIO_EVT_CH3_RISE_EDGE_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents GPIO_evt_ch4_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch4_rise_edge_st(&mut self) -> GPIO_EVT_CH4_RISE_EDGE_ST_W { + GPIO_EVT_CH4_RISE_EDGE_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents GPIO_evt_ch5_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch5_rise_edge_st(&mut self) -> GPIO_EVT_CH5_RISE_EDGE_ST_W { + GPIO_EVT_CH5_RISE_EDGE_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents GPIO_evt_ch6_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch6_rise_edge_st(&mut self) -> GPIO_EVT_CH6_RISE_EDGE_ST_W { + GPIO_EVT_CH6_RISE_EDGE_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents GPIO_evt_ch7_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch7_rise_edge_st(&mut self) -> GPIO_EVT_CH7_RISE_EDGE_ST_W { + GPIO_EVT_CH7_RISE_EDGE_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents GPIO_evt_ch0_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch0_fall_edge_st(&mut self) -> GPIO_EVT_CH0_FALL_EDGE_ST_W { + GPIO_EVT_CH0_FALL_EDGE_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents GPIO_evt_ch1_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch1_fall_edge_st(&mut self) -> GPIO_EVT_CH1_FALL_EDGE_ST_W { + GPIO_EVT_CH1_FALL_EDGE_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents GPIO_evt_ch2_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch2_fall_edge_st(&mut self) -> GPIO_EVT_CH2_FALL_EDGE_ST_W { + GPIO_EVT_CH2_FALL_EDGE_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents GPIO_evt_ch3_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch3_fall_edge_st(&mut self) -> GPIO_EVT_CH3_FALL_EDGE_ST_W { + GPIO_EVT_CH3_FALL_EDGE_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents GPIO_evt_ch4_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch4_fall_edge_st(&mut self) -> GPIO_EVT_CH4_FALL_EDGE_ST_W { + GPIO_EVT_CH4_FALL_EDGE_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents GPIO_evt_ch5_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch5_fall_edge_st(&mut self) -> GPIO_EVT_CH5_FALL_EDGE_ST_W { + GPIO_EVT_CH5_FALL_EDGE_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents GPIO_evt_ch6_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch6_fall_edge_st(&mut self) -> GPIO_EVT_CH6_FALL_EDGE_ST_W { + GPIO_EVT_CH6_FALL_EDGE_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents GPIO_evt_ch7_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch7_fall_edge_st(&mut self) -> GPIO_EVT_CH7_FALL_EDGE_ST_W { + GPIO_EVT_CH7_FALL_EDGE_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents GPIO_evt_ch0_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch0_any_edge_st(&mut self) -> GPIO_EVT_CH0_ANY_EDGE_ST_W { + GPIO_EVT_CH0_ANY_EDGE_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents GPIO_evt_ch1_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch1_any_edge_st(&mut self) -> GPIO_EVT_CH1_ANY_EDGE_ST_W { + GPIO_EVT_CH1_ANY_EDGE_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents GPIO_evt_ch2_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch2_any_edge_st(&mut self) -> GPIO_EVT_CH2_ANY_EDGE_ST_W { + GPIO_EVT_CH2_ANY_EDGE_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents GPIO_evt_ch3_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch3_any_edge_st(&mut self) -> GPIO_EVT_CH3_ANY_EDGE_ST_W { + GPIO_EVT_CH3_ANY_EDGE_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents GPIO_evt_ch4_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch4_any_edge_st(&mut self) -> GPIO_EVT_CH4_ANY_EDGE_ST_W { + GPIO_EVT_CH4_ANY_EDGE_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents GPIO_evt_ch5_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch5_any_edge_st(&mut self) -> GPIO_EVT_CH5_ANY_EDGE_ST_W { + GPIO_EVT_CH5_ANY_EDGE_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents GPIO_evt_ch6_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch6_any_edge_st(&mut self) -> GPIO_EVT_CH6_ANY_EDGE_ST_W { + GPIO_EVT_CH6_ANY_EDGE_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents GPIO_evt_ch7_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch7_any_edge_st(&mut self) -> GPIO_EVT_CH7_ANY_EDGE_ST_W { + GPIO_EVT_CH7_ANY_EDGE_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents GPIO_evt_zero_det_pos0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_zero_det_pos0_st(&mut self) -> GPIO_EVT_ZERO_DET_POS0_ST_W { + GPIO_EVT_ZERO_DET_POS0_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents GPIO_evt_zero_det_neg0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_zero_det_neg0_st(&mut self) -> GPIO_EVT_ZERO_DET_NEG0_ST_W { + GPIO_EVT_ZERO_DET_NEG0_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents GPIO_evt_zero_det_pos1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_zero_det_pos1_st(&mut self) -> GPIO_EVT_ZERO_DET_POS1_ST_W { + GPIO_EVT_ZERO_DET_POS1_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents GPIO_evt_zero_det_neg1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_zero_det_neg1_st(&mut self) -> GPIO_EVT_ZERO_DET_NEG1_ST_W { + GPIO_EVT_ZERO_DET_NEG1_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch0_st( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH0_ST_W { + LEDC_EVT_DUTY_CHNG_END_CH0_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch1_st( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH1_ST_W { + LEDC_EVT_DUTY_CHNG_END_CH1_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch2_st( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH2_ST_W { + LEDC_EVT_DUTY_CHNG_END_CH2_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch3_st( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH3_ST_W { + LEDC_EVT_DUTY_CHNG_END_CH3_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST0_SPEC; +impl crate::RegisterSpec for EVT_ST0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_st0::R`](R) reader structure"] +impl crate::Readable for EVT_ST0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_st0::W`](W) writer structure"] +impl crate::Writable for EVT_ST0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST0 to value 0"] +impl crate::Resettable for EVT_ST0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st0_clr.rs b/esp32p4/src/soc_etm/evt_st0_clr.rs new file mode 100644 index 0000000000..256f7ec551 --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st0_clr.rs @@ -0,0 +1,354 @@ +#[doc = "Register `EVT_ST0_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_EVT_CH0_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH0_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH1_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH1_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH2_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH2_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH3_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH3_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH4_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH4_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH5_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH5_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH6_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH6_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH7_RISE_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH7_RISE_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH0_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH0_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH1_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH1_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH2_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH2_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH3_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH3_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH4_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH4_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH5_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH5_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH6_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH6_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH7_FALL_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH7_FALL_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH0_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH0_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH1_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH1_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH2_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH2_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH3_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH3_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH4_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH4_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH5_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH5_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH6_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH6_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_CH7_ANY_EDGE_ST_CLR` writer - Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_CH7_ANY_EDGE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_ZERO_DET_POS0_ST_CLR` writer - Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_ZERO_DET_POS0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_ZERO_DET_NEG0_ST_CLR` writer - Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_ZERO_DET_NEG0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_ZERO_DET_POS1_ST_CLR` writer - Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_ZERO_DET_POS1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_EVT_ZERO_DET_NEG1_ST_CLR` writer - Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_EVT_ZERO_DET_NEG1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch0_rise_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH0_RISE_EDGE_ST_CLR_W { + GPIO_EVT_CH0_RISE_EDGE_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch1_rise_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH1_RISE_EDGE_ST_CLR_W { + GPIO_EVT_CH1_RISE_EDGE_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch2_rise_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH2_RISE_EDGE_ST_CLR_W { + GPIO_EVT_CH2_RISE_EDGE_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch3_rise_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH3_RISE_EDGE_ST_CLR_W { + GPIO_EVT_CH3_RISE_EDGE_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch4_rise_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH4_RISE_EDGE_ST_CLR_W { + GPIO_EVT_CH4_RISE_EDGE_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch5_rise_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH5_RISE_EDGE_ST_CLR_W { + GPIO_EVT_CH5_RISE_EDGE_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch6_rise_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH6_RISE_EDGE_ST_CLR_W { + GPIO_EVT_CH6_RISE_EDGE_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch7_rise_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH7_RISE_EDGE_ST_CLR_W { + GPIO_EVT_CH7_RISE_EDGE_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch0_fall_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH0_FALL_EDGE_ST_CLR_W { + GPIO_EVT_CH0_FALL_EDGE_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch1_fall_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH1_FALL_EDGE_ST_CLR_W { + GPIO_EVT_CH1_FALL_EDGE_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch2_fall_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH2_FALL_EDGE_ST_CLR_W { + GPIO_EVT_CH2_FALL_EDGE_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch3_fall_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH3_FALL_EDGE_ST_CLR_W { + GPIO_EVT_CH3_FALL_EDGE_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch4_fall_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH4_FALL_EDGE_ST_CLR_W { + GPIO_EVT_CH4_FALL_EDGE_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch5_fall_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH5_FALL_EDGE_ST_CLR_W { + GPIO_EVT_CH5_FALL_EDGE_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch6_fall_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH6_FALL_EDGE_ST_CLR_W { + GPIO_EVT_CH6_FALL_EDGE_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch7_fall_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH7_FALL_EDGE_ST_CLR_W { + GPIO_EVT_CH7_FALL_EDGE_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch0_any_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH0_ANY_EDGE_ST_CLR_W { + GPIO_EVT_CH0_ANY_EDGE_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch1_any_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH1_ANY_EDGE_ST_CLR_W { + GPIO_EVT_CH1_ANY_EDGE_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch2_any_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH2_ANY_EDGE_ST_CLR_W { + GPIO_EVT_CH2_ANY_EDGE_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch3_any_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH3_ANY_EDGE_ST_CLR_W { + GPIO_EVT_CH3_ANY_EDGE_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch4_any_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH4_ANY_EDGE_ST_CLR_W { + GPIO_EVT_CH4_ANY_EDGE_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch5_any_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH5_ANY_EDGE_ST_CLR_W { + GPIO_EVT_CH5_ANY_EDGE_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch6_any_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH6_ANY_EDGE_ST_CLR_W { + GPIO_EVT_CH6_ANY_EDGE_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_ch7_any_edge_st_clr( + &mut self, + ) -> GPIO_EVT_CH7_ANY_EDGE_ST_CLR_W { + GPIO_EVT_CH7_ANY_EDGE_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_zero_det_pos0_st_clr( + &mut self, + ) -> GPIO_EVT_ZERO_DET_POS0_ST_CLR_W { + GPIO_EVT_ZERO_DET_POS0_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_zero_det_neg0_st_clr( + &mut self, + ) -> GPIO_EVT_ZERO_DET_NEG0_ST_CLR_W { + GPIO_EVT_ZERO_DET_NEG0_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_zero_det_pos1_st_clr( + &mut self, + ) -> GPIO_EVT_ZERO_DET_POS1_ST_CLR_W { + GPIO_EVT_ZERO_DET_POS1_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_evt_zero_det_neg1_st_clr( + &mut self, + ) -> GPIO_EVT_ZERO_DET_NEG1_ST_CLR_W { + GPIO_EVT_ZERO_DET_NEG1_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch0_st_clr( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_W { + LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch1_st_clr( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_W { + LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch2_st_clr( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_W { + LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch3_st_clr( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_W { + LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st0_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST0_CLR_SPEC; +impl crate::RegisterSpec for EVT_ST0_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`evt_st0_clr::W`](W) writer structure"] +impl crate::Writable for EVT_ST0_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST0_CLR to value 0"] +impl crate::Resettable for EVT_ST0_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st1.rs b/esp32p4/src/soc_etm/evt_st1.rs new file mode 100644 index 0000000000..a4f0c0678e --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st1.rs @@ -0,0 +1,663 @@ +#[doc = "Register `EVT_ST1` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_ST1` writer"] +pub type W = crate::W; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH4_ST` reader - Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH4_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH4_ST` writer - Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH5_ST` reader - Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH5_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH5_ST` writer - Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH5_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH6_ST` reader - Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH6_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH6_ST` writer - Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH6_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH7_ST` reader - Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH7_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH7_ST` writer - Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_DUTY_CHNG_END_CH7_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH0_ST` reader - Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH0_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH0_ST` writer - Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH1_ST` reader - Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH1_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH1_ST` writer - Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH2_ST` reader - Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH2_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH2_ST` writer - Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH3_ST` reader - Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH3_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH3_ST` writer - Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH4_ST` reader - Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH4_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH4_ST` writer - Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH5_ST` reader - Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH5_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH5_ST` writer - Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH5_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH6_ST` reader - Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH6_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH6_ST` writer - Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH6_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH7_ST` reader - Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH7_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH7_ST` writer - Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_OVF_CNT_PLS_CH7_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER0_ST` reader - Represents LEDC_evt_time_ovf_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIME_OVF_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER0_ST` writer - Represents LEDC_evt_time_ovf_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIME_OVF_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER1_ST` reader - Represents LEDC_evt_time_ovf_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIME_OVF_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER1_ST` writer - Represents LEDC_evt_time_ovf_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIME_OVF_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER2_ST` reader - Represents LEDC_evt_time_ovf_timer2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIME_OVF_TIMER2_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER2_ST` writer - Represents LEDC_evt_time_ovf_timer2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIME_OVF_TIMER2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER3_ST` reader - Represents LEDC_evt_time_ovf_timer3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIME_OVF_TIMER3_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER3_ST` writer - Represents LEDC_evt_time_ovf_timer3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIME_OVF_TIMER3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIMER0_CMP_ST` reader - Represents LEDC_evt_timer0_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIMER0_CMP_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_TIMER0_CMP_ST` writer - Represents LEDC_evt_timer0_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIMER0_CMP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIMER1_CMP_ST` reader - Represents LEDC_evt_timer1_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIMER1_CMP_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_TIMER1_CMP_ST` writer - Represents LEDC_evt_timer1_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIMER1_CMP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIMER2_CMP_ST` reader - Represents LEDC_evt_timer2_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIMER2_CMP_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_TIMER2_CMP_ST` writer - Represents LEDC_evt_timer2_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIMER2_CMP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIMER3_CMP_ST` reader - Represents LEDC_evt_timer3_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIMER3_CMP_ST_R = crate::BitReader; +#[doc = "Field `LEDC_EVT_TIMER3_CMP_ST` writer - Represents LEDC_evt_timer3_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_EVT_TIMER3_CMP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_EVT_CNT_CMP_TIMER0_ST` reader - Represents TG0_evt_cnt_cmp_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_EVT_CNT_CMP_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG0_EVT_CNT_CMP_TIMER0_ST` writer - Represents TG0_evt_cnt_cmp_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_EVT_CNT_CMP_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_EVT_CNT_CMP_TIMER1_ST` reader - Represents TG0_evt_cnt_cmp_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_EVT_CNT_CMP_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG0_EVT_CNT_CMP_TIMER1_ST` writer - Represents TG0_evt_cnt_cmp_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_EVT_CNT_CMP_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_EVT_CNT_CMP_TIMER0_ST` reader - Represents TG1_evt_cnt_cmp_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_EVT_CNT_CMP_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG1_EVT_CNT_CMP_TIMER0_ST` writer - Represents TG1_evt_cnt_cmp_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_EVT_CNT_CMP_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_EVT_CNT_CMP_TIMER1_ST` reader - Represents TG1_evt_cnt_cmp_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_EVT_CNT_CMP_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG1_EVT_CNT_CMP_TIMER1_ST` writer - Represents TG1_evt_cnt_cmp_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_EVT_CNT_CMP_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSTIMER_EVT_CNT_CMP0_ST` reader - Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type SYSTIMER_EVT_CNT_CMP0_ST_R = crate::BitReader; +#[doc = "Field `SYSTIMER_EVT_CNT_CMP0_ST` writer - Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type SYSTIMER_EVT_CNT_CMP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSTIMER_EVT_CNT_CMP1_ST` reader - Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type SYSTIMER_EVT_CNT_CMP1_ST_R = crate::BitReader; +#[doc = "Field `SYSTIMER_EVT_CNT_CMP1_ST` writer - Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type SYSTIMER_EVT_CNT_CMP1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSTIMER_EVT_CNT_CMP2_ST` reader - Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type SYSTIMER_EVT_CNT_CMP2_ST_R = crate::BitReader; +#[doc = "Field `SYSTIMER_EVT_CNT_CMP2_ST` writer - Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type SYSTIMER_EVT_CNT_CMP2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER0_STOP_ST` reader - Represents MCPWM0_evt_timer0_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER0_STOP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TIMER0_STOP_ST` writer - Represents MCPWM0_evt_timer0_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER0_STOP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER1_STOP_ST` reader - Represents MCPWM0_evt_timer1_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER1_STOP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TIMER1_STOP_ST` writer - Represents MCPWM0_evt_timer1_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER1_STOP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER2_STOP_ST` reader - Represents MCPWM0_evt_timer2_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER2_STOP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TIMER2_STOP_ST` writer - Represents MCPWM0_evt_timer2_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER2_STOP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER0_TEZ_ST` reader - Represents MCPWM0_evt_timer0_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER0_TEZ_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TIMER0_TEZ_ST` writer - Represents MCPWM0_evt_timer0_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER0_TEZ_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER1_TEZ_ST` reader - Represents MCPWM0_evt_timer1_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER1_TEZ_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TIMER1_TEZ_ST` writer - Represents MCPWM0_evt_timer1_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER1_TEZ_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_duty_chng_end_ch4_st(&self) -> LEDC_EVT_DUTY_CHNG_END_CH4_ST_R { + LEDC_EVT_DUTY_CHNG_END_CH4_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_duty_chng_end_ch5_st(&self) -> LEDC_EVT_DUTY_CHNG_END_CH5_ST_R { + LEDC_EVT_DUTY_CHNG_END_CH5_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_duty_chng_end_ch6_st(&self) -> LEDC_EVT_DUTY_CHNG_END_CH6_ST_R { + LEDC_EVT_DUTY_CHNG_END_CH6_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_duty_chng_end_ch7_st(&self) -> LEDC_EVT_DUTY_CHNG_END_CH7_ST_R { + LEDC_EVT_DUTY_CHNG_END_CH7_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_ovf_cnt_pls_ch0_st(&self) -> LEDC_EVT_OVF_CNT_PLS_CH0_ST_R { + LEDC_EVT_OVF_CNT_PLS_CH0_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_ovf_cnt_pls_ch1_st(&self) -> LEDC_EVT_OVF_CNT_PLS_CH1_ST_R { + LEDC_EVT_OVF_CNT_PLS_CH1_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_ovf_cnt_pls_ch2_st(&self) -> LEDC_EVT_OVF_CNT_PLS_CH2_ST_R { + LEDC_EVT_OVF_CNT_PLS_CH2_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_ovf_cnt_pls_ch3_st(&self) -> LEDC_EVT_OVF_CNT_PLS_CH3_ST_R { + LEDC_EVT_OVF_CNT_PLS_CH3_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_ovf_cnt_pls_ch4_st(&self) -> LEDC_EVT_OVF_CNT_PLS_CH4_ST_R { + LEDC_EVT_OVF_CNT_PLS_CH4_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_ovf_cnt_pls_ch5_st(&self) -> LEDC_EVT_OVF_CNT_PLS_CH5_ST_R { + LEDC_EVT_OVF_CNT_PLS_CH5_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_ovf_cnt_pls_ch6_st(&self) -> LEDC_EVT_OVF_CNT_PLS_CH6_ST_R { + LEDC_EVT_OVF_CNT_PLS_CH6_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_ovf_cnt_pls_ch7_st(&self) -> LEDC_EVT_OVF_CNT_PLS_CH7_ST_R { + LEDC_EVT_OVF_CNT_PLS_CH7_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents LEDC_evt_time_ovf_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_time_ovf_timer0_st(&self) -> LEDC_EVT_TIME_OVF_TIMER0_ST_R { + LEDC_EVT_TIME_OVF_TIMER0_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents LEDC_evt_time_ovf_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_time_ovf_timer1_st(&self) -> LEDC_EVT_TIME_OVF_TIMER1_ST_R { + LEDC_EVT_TIME_OVF_TIMER1_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents LEDC_evt_time_ovf_timer2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_time_ovf_timer2_st(&self) -> LEDC_EVT_TIME_OVF_TIMER2_ST_R { + LEDC_EVT_TIME_OVF_TIMER2_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents LEDC_evt_time_ovf_timer3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_time_ovf_timer3_st(&self) -> LEDC_EVT_TIME_OVF_TIMER3_ST_R { + LEDC_EVT_TIME_OVF_TIMER3_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents LEDC_evt_timer0_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_timer0_cmp_st(&self) -> LEDC_EVT_TIMER0_CMP_ST_R { + LEDC_EVT_TIMER0_CMP_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents LEDC_evt_timer1_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_timer1_cmp_st(&self) -> LEDC_EVT_TIMER1_CMP_ST_R { + LEDC_EVT_TIMER1_CMP_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents LEDC_evt_timer2_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_timer2_cmp_st(&self) -> LEDC_EVT_TIMER2_CMP_ST_R { + LEDC_EVT_TIMER2_CMP_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents LEDC_evt_timer3_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_evt_timer3_cmp_st(&self) -> LEDC_EVT_TIMER3_CMP_ST_R { + LEDC_EVT_TIMER3_CMP_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents TG0_evt_cnt_cmp_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_evt_cnt_cmp_timer0_st(&self) -> TG0_EVT_CNT_CMP_TIMER0_ST_R { + TG0_EVT_CNT_CMP_TIMER0_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents TG0_evt_cnt_cmp_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_evt_cnt_cmp_timer1_st(&self) -> TG0_EVT_CNT_CMP_TIMER1_ST_R { + TG0_EVT_CNT_CMP_TIMER1_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents TG1_evt_cnt_cmp_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_evt_cnt_cmp_timer0_st(&self) -> TG1_EVT_CNT_CMP_TIMER0_ST_R { + TG1_EVT_CNT_CMP_TIMER0_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents TG1_evt_cnt_cmp_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_evt_cnt_cmp_timer1_st(&self) -> TG1_EVT_CNT_CMP_TIMER1_ST_R { + TG1_EVT_CNT_CMP_TIMER1_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn systimer_evt_cnt_cmp0_st(&self) -> SYSTIMER_EVT_CNT_CMP0_ST_R { + SYSTIMER_EVT_CNT_CMP0_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn systimer_evt_cnt_cmp1_st(&self) -> SYSTIMER_EVT_CNT_CMP1_ST_R { + SYSTIMER_EVT_CNT_CMP1_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn systimer_evt_cnt_cmp2_st(&self) -> SYSTIMER_EVT_CNT_CMP2_ST_R { + SYSTIMER_EVT_CNT_CMP2_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents MCPWM0_evt_timer0_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_timer0_stop_st(&self) -> MCPWM0_EVT_TIMER0_STOP_ST_R { + MCPWM0_EVT_TIMER0_STOP_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents MCPWM0_evt_timer1_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_timer1_stop_st(&self) -> MCPWM0_EVT_TIMER1_STOP_ST_R { + MCPWM0_EVT_TIMER1_STOP_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents MCPWM0_evt_timer2_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_timer2_stop_st(&self) -> MCPWM0_EVT_TIMER2_STOP_ST_R { + MCPWM0_EVT_TIMER2_STOP_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents MCPWM0_evt_timer0_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_timer0_tez_st(&self) -> MCPWM0_EVT_TIMER0_TEZ_ST_R { + MCPWM0_EVT_TIMER0_TEZ_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents MCPWM0_evt_timer1_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_timer1_tez_st(&self) -> MCPWM0_EVT_TIMER1_TEZ_ST_R { + MCPWM0_EVT_TIMER1_TEZ_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_ST1") + .field( + "ledc_evt_duty_chng_end_ch4_st", + &format_args!("{}", self.ledc_evt_duty_chng_end_ch4_st().bit()), + ) + .field( + "ledc_evt_duty_chng_end_ch5_st", + &format_args!("{}", self.ledc_evt_duty_chng_end_ch5_st().bit()), + ) + .field( + "ledc_evt_duty_chng_end_ch6_st", + &format_args!("{}", self.ledc_evt_duty_chng_end_ch6_st().bit()), + ) + .field( + "ledc_evt_duty_chng_end_ch7_st", + &format_args!("{}", self.ledc_evt_duty_chng_end_ch7_st().bit()), + ) + .field( + "ledc_evt_ovf_cnt_pls_ch0_st", + &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch0_st().bit()), + ) + .field( + "ledc_evt_ovf_cnt_pls_ch1_st", + &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch1_st().bit()), + ) + .field( + "ledc_evt_ovf_cnt_pls_ch2_st", + &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch2_st().bit()), + ) + .field( + "ledc_evt_ovf_cnt_pls_ch3_st", + &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch3_st().bit()), + ) + .field( + "ledc_evt_ovf_cnt_pls_ch4_st", + &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch4_st().bit()), + ) + .field( + "ledc_evt_ovf_cnt_pls_ch5_st", + &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch5_st().bit()), + ) + .field( + "ledc_evt_ovf_cnt_pls_ch6_st", + &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch6_st().bit()), + ) + .field( + "ledc_evt_ovf_cnt_pls_ch7_st", + &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch7_st().bit()), + ) + .field( + "ledc_evt_time_ovf_timer0_st", + &format_args!("{}", self.ledc_evt_time_ovf_timer0_st().bit()), + ) + .field( + "ledc_evt_time_ovf_timer1_st", + &format_args!("{}", self.ledc_evt_time_ovf_timer1_st().bit()), + ) + .field( + "ledc_evt_time_ovf_timer2_st", + &format_args!("{}", self.ledc_evt_time_ovf_timer2_st().bit()), + ) + .field( + "ledc_evt_time_ovf_timer3_st", + &format_args!("{}", self.ledc_evt_time_ovf_timer3_st().bit()), + ) + .field( + "ledc_evt_timer0_cmp_st", + &format_args!("{}", self.ledc_evt_timer0_cmp_st().bit()), + ) + .field( + "ledc_evt_timer1_cmp_st", + &format_args!("{}", self.ledc_evt_timer1_cmp_st().bit()), + ) + .field( + "ledc_evt_timer2_cmp_st", + &format_args!("{}", self.ledc_evt_timer2_cmp_st().bit()), + ) + .field( + "ledc_evt_timer3_cmp_st", + &format_args!("{}", self.ledc_evt_timer3_cmp_st().bit()), + ) + .field( + "tg0_evt_cnt_cmp_timer0_st", + &format_args!("{}", self.tg0_evt_cnt_cmp_timer0_st().bit()), + ) + .field( + "tg0_evt_cnt_cmp_timer1_st", + &format_args!("{}", self.tg0_evt_cnt_cmp_timer1_st().bit()), + ) + .field( + "tg1_evt_cnt_cmp_timer0_st", + &format_args!("{}", self.tg1_evt_cnt_cmp_timer0_st().bit()), + ) + .field( + "tg1_evt_cnt_cmp_timer1_st", + &format_args!("{}", self.tg1_evt_cnt_cmp_timer1_st().bit()), + ) + .field( + "systimer_evt_cnt_cmp0_st", + &format_args!("{}", self.systimer_evt_cnt_cmp0_st().bit()), + ) + .field( + "systimer_evt_cnt_cmp1_st", + &format_args!("{}", self.systimer_evt_cnt_cmp1_st().bit()), + ) + .field( + "systimer_evt_cnt_cmp2_st", + &format_args!("{}", self.systimer_evt_cnt_cmp2_st().bit()), + ) + .field( + "mcpwm0_evt_timer0_stop_st", + &format_args!("{}", self.mcpwm0_evt_timer0_stop_st().bit()), + ) + .field( + "mcpwm0_evt_timer1_stop_st", + &format_args!("{}", self.mcpwm0_evt_timer1_stop_st().bit()), + ) + .field( + "mcpwm0_evt_timer2_stop_st", + &format_args!("{}", self.mcpwm0_evt_timer2_stop_st().bit()), + ) + .field( + "mcpwm0_evt_timer0_tez_st", + &format_args!("{}", self.mcpwm0_evt_timer0_tez_st().bit()), + ) + .field( + "mcpwm0_evt_timer1_tez_st", + &format_args!("{}", self.mcpwm0_evt_timer1_tez_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch4_st( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH4_ST_W { + LEDC_EVT_DUTY_CHNG_END_CH4_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch5_st( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH5_ST_W { + LEDC_EVT_DUTY_CHNG_END_CH5_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch6_st( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH6_ST_W { + LEDC_EVT_DUTY_CHNG_END_CH6_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch7_st( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH7_ST_W { + LEDC_EVT_DUTY_CHNG_END_CH7_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch0_st(&mut self) -> LEDC_EVT_OVF_CNT_PLS_CH0_ST_W { + LEDC_EVT_OVF_CNT_PLS_CH0_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch1_st(&mut self) -> LEDC_EVT_OVF_CNT_PLS_CH1_ST_W { + LEDC_EVT_OVF_CNT_PLS_CH1_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch2_st(&mut self) -> LEDC_EVT_OVF_CNT_PLS_CH2_ST_W { + LEDC_EVT_OVF_CNT_PLS_CH2_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch3_st(&mut self) -> LEDC_EVT_OVF_CNT_PLS_CH3_ST_W { + LEDC_EVT_OVF_CNT_PLS_CH3_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch4_st(&mut self) -> LEDC_EVT_OVF_CNT_PLS_CH4_ST_W { + LEDC_EVT_OVF_CNT_PLS_CH4_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch5_st(&mut self) -> LEDC_EVT_OVF_CNT_PLS_CH5_ST_W { + LEDC_EVT_OVF_CNT_PLS_CH5_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch6_st(&mut self) -> LEDC_EVT_OVF_CNT_PLS_CH6_ST_W { + LEDC_EVT_OVF_CNT_PLS_CH6_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch7_st(&mut self) -> LEDC_EVT_OVF_CNT_PLS_CH7_ST_W { + LEDC_EVT_OVF_CNT_PLS_CH7_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents LEDC_evt_time_ovf_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_time_ovf_timer0_st(&mut self) -> LEDC_EVT_TIME_OVF_TIMER0_ST_W { + LEDC_EVT_TIME_OVF_TIMER0_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents LEDC_evt_time_ovf_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_time_ovf_timer1_st(&mut self) -> LEDC_EVT_TIME_OVF_TIMER1_ST_W { + LEDC_EVT_TIME_OVF_TIMER1_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents LEDC_evt_time_ovf_timer2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_time_ovf_timer2_st(&mut self) -> LEDC_EVT_TIME_OVF_TIMER2_ST_W { + LEDC_EVT_TIME_OVF_TIMER2_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents LEDC_evt_time_ovf_timer3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_time_ovf_timer3_st(&mut self) -> LEDC_EVT_TIME_OVF_TIMER3_ST_W { + LEDC_EVT_TIME_OVF_TIMER3_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents LEDC_evt_timer0_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_timer0_cmp_st(&mut self) -> LEDC_EVT_TIMER0_CMP_ST_W { + LEDC_EVT_TIMER0_CMP_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents LEDC_evt_timer1_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_timer1_cmp_st(&mut self) -> LEDC_EVT_TIMER1_CMP_ST_W { + LEDC_EVT_TIMER1_CMP_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents LEDC_evt_timer2_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_timer2_cmp_st(&mut self) -> LEDC_EVT_TIMER2_CMP_ST_W { + LEDC_EVT_TIMER2_CMP_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents LEDC_evt_timer3_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_timer3_cmp_st(&mut self) -> LEDC_EVT_TIMER3_CMP_ST_W { + LEDC_EVT_TIMER3_CMP_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents TG0_evt_cnt_cmp_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_evt_cnt_cmp_timer0_st(&mut self) -> TG0_EVT_CNT_CMP_TIMER0_ST_W { + TG0_EVT_CNT_CMP_TIMER0_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents TG0_evt_cnt_cmp_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_evt_cnt_cmp_timer1_st(&mut self) -> TG0_EVT_CNT_CMP_TIMER1_ST_W { + TG0_EVT_CNT_CMP_TIMER1_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents TG1_evt_cnt_cmp_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_evt_cnt_cmp_timer0_st(&mut self) -> TG1_EVT_CNT_CMP_TIMER0_ST_W { + TG1_EVT_CNT_CMP_TIMER0_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents TG1_evt_cnt_cmp_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_evt_cnt_cmp_timer1_st(&mut self) -> TG1_EVT_CNT_CMP_TIMER1_ST_W { + TG1_EVT_CNT_CMP_TIMER1_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn systimer_evt_cnt_cmp0_st(&mut self) -> SYSTIMER_EVT_CNT_CMP0_ST_W { + SYSTIMER_EVT_CNT_CMP0_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn systimer_evt_cnt_cmp1_st(&mut self) -> SYSTIMER_EVT_CNT_CMP1_ST_W { + SYSTIMER_EVT_CNT_CMP1_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn systimer_evt_cnt_cmp2_st(&mut self) -> SYSTIMER_EVT_CNT_CMP2_ST_W { + SYSTIMER_EVT_CNT_CMP2_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents MCPWM0_evt_timer0_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer0_stop_st(&mut self) -> MCPWM0_EVT_TIMER0_STOP_ST_W { + MCPWM0_EVT_TIMER0_STOP_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents MCPWM0_evt_timer1_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer1_stop_st(&mut self) -> MCPWM0_EVT_TIMER1_STOP_ST_W { + MCPWM0_EVT_TIMER1_STOP_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents MCPWM0_evt_timer2_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer2_stop_st(&mut self) -> MCPWM0_EVT_TIMER2_STOP_ST_W { + MCPWM0_EVT_TIMER2_STOP_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents MCPWM0_evt_timer0_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer0_tez_st(&mut self) -> MCPWM0_EVT_TIMER0_TEZ_ST_W { + MCPWM0_EVT_TIMER0_TEZ_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents MCPWM0_evt_timer1_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer1_tez_st(&mut self) -> MCPWM0_EVT_TIMER1_TEZ_ST_W { + MCPWM0_EVT_TIMER1_TEZ_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST1_SPEC; +impl crate::RegisterSpec for EVT_ST1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_st1::R`](R) reader structure"] +impl crate::Readable for EVT_ST1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_st1::W`](W) writer structure"] +impl crate::Writable for EVT_ST1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST1 to value 0"] +impl crate::Resettable for EVT_ST1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st1_clr.rs b/esp32p4/src/soc_etm/evt_st1_clr.rs new file mode 100644 index 0000000000..e93e62c97e --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st1_clr.rs @@ -0,0 +1,346 @@ +#[doc = "Register `EVT_ST1_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR` writer - Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR` writer - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR` writer - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR` writer - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR` writer - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR` writer - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR` writer - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR` writer - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR` writer - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER0_ST_CLR` writer - Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER1_ST_CLR` writer - Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER2_ST_CLR` writer - Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIME_OVF_TIMER3_ST_CLR` writer - Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIMER0_CMP_ST_CLR` writer - Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_TIMER0_CMP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIMER1_CMP_ST_CLR` writer - Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_TIMER1_CMP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIMER2_CMP_ST_CLR` writer - Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_TIMER2_CMP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_EVT_TIMER3_CMP_ST_CLR` writer - Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_EVT_TIMER3_CMP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_EVT_CNT_CMP_TIMER0_ST_CLR` writer - Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_EVT_CNT_CMP_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_EVT_CNT_CMP_TIMER1_ST_CLR` writer - Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_EVT_CNT_CMP_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_EVT_CNT_CMP_TIMER0_ST_CLR` writer - Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_EVT_CNT_CMP_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_EVT_CNT_CMP_TIMER1_ST_CLR` writer - Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_EVT_CNT_CMP_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSTIMER_EVT_CNT_CMP0_ST_CLR` writer - Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type SYSTIMER_EVT_CNT_CMP0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSTIMER_EVT_CNT_CMP1_ST_CLR` writer - Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type SYSTIMER_EVT_CNT_CMP1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSTIMER_EVT_CNT_CMP2_ST_CLR` writer - Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type SYSTIMER_EVT_CNT_CMP2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER0_STOP_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TIMER0_STOP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER1_STOP_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TIMER1_STOP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER2_STOP_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TIMER2_STOP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER0_TEZ_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TIMER0_TEZ_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER1_TEZ_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TIMER1_TEZ_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch4_st_clr( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_W { + LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch5_st_clr( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_W { + LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch6_st_clr( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_W { + LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_duty_chng_end_ch7_st_clr( + &mut self, + ) -> LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_W { + LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch0_st_clr( + &mut self, + ) -> LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_W { + LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch1_st_clr( + &mut self, + ) -> LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_W { + LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch2_st_clr( + &mut self, + ) -> LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_W { + LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch3_st_clr( + &mut self, + ) -> LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_W { + LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch4_st_clr( + &mut self, + ) -> LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_W { + LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch5_st_clr( + &mut self, + ) -> LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_W { + LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch6_st_clr( + &mut self, + ) -> LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_W { + LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_ovf_cnt_pls_ch7_st_clr( + &mut self, + ) -> LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_W { + LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_time_ovf_timer0_st_clr( + &mut self, + ) -> LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_W { + LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_time_ovf_timer1_st_clr( + &mut self, + ) -> LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_W { + LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_time_ovf_timer2_st_clr( + &mut self, + ) -> LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_W { + LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_time_ovf_timer3_st_clr( + &mut self, + ) -> LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_W { + LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_timer0_cmp_st_clr(&mut self) -> LEDC_EVT_TIMER0_CMP_ST_CLR_W { + LEDC_EVT_TIMER0_CMP_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_timer1_cmp_st_clr(&mut self) -> LEDC_EVT_TIMER1_CMP_ST_CLR_W { + LEDC_EVT_TIMER1_CMP_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_timer2_cmp_st_clr(&mut self) -> LEDC_EVT_TIMER2_CMP_ST_CLR_W { + LEDC_EVT_TIMER2_CMP_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_evt_timer3_cmp_st_clr(&mut self) -> LEDC_EVT_TIMER3_CMP_ST_CLR_W { + LEDC_EVT_TIMER3_CMP_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_evt_cnt_cmp_timer0_st_clr( + &mut self, + ) -> TG0_EVT_CNT_CMP_TIMER0_ST_CLR_W { + TG0_EVT_CNT_CMP_TIMER0_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_evt_cnt_cmp_timer1_st_clr( + &mut self, + ) -> TG0_EVT_CNT_CMP_TIMER1_ST_CLR_W { + TG0_EVT_CNT_CMP_TIMER1_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_evt_cnt_cmp_timer0_st_clr( + &mut self, + ) -> TG1_EVT_CNT_CMP_TIMER0_ST_CLR_W { + TG1_EVT_CNT_CMP_TIMER0_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_evt_cnt_cmp_timer1_st_clr( + &mut self, + ) -> TG1_EVT_CNT_CMP_TIMER1_ST_CLR_W { + TG1_EVT_CNT_CMP_TIMER1_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn systimer_evt_cnt_cmp0_st_clr( + &mut self, + ) -> SYSTIMER_EVT_CNT_CMP0_ST_CLR_W { + SYSTIMER_EVT_CNT_CMP0_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn systimer_evt_cnt_cmp1_st_clr( + &mut self, + ) -> SYSTIMER_EVT_CNT_CMP1_ST_CLR_W { + SYSTIMER_EVT_CNT_CMP1_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn systimer_evt_cnt_cmp2_st_clr( + &mut self, + ) -> SYSTIMER_EVT_CNT_CMP2_ST_CLR_W { + SYSTIMER_EVT_CNT_CMP2_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer0_stop_st_clr( + &mut self, + ) -> MCPWM0_EVT_TIMER0_STOP_ST_CLR_W { + MCPWM0_EVT_TIMER0_STOP_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer1_stop_st_clr( + &mut self, + ) -> MCPWM0_EVT_TIMER1_STOP_ST_CLR_W { + MCPWM0_EVT_TIMER1_STOP_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer2_stop_st_clr( + &mut self, + ) -> MCPWM0_EVT_TIMER2_STOP_ST_CLR_W { + MCPWM0_EVT_TIMER2_STOP_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer0_tez_st_clr( + &mut self, + ) -> MCPWM0_EVT_TIMER0_TEZ_ST_CLR_W { + MCPWM0_EVT_TIMER0_TEZ_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer1_tez_st_clr( + &mut self, + ) -> MCPWM0_EVT_TIMER1_TEZ_ST_CLR_W { + MCPWM0_EVT_TIMER1_TEZ_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st1_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST1_CLR_SPEC; +impl crate::RegisterSpec for EVT_ST1_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`evt_st1_clr::W`](W) writer structure"] +impl crate::Writable for EVT_ST1_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST1_CLR to value 0"] +impl crate::Resettable for EVT_ST1_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st2.rs b/esp32p4/src/soc_etm/evt_st2.rs new file mode 100644 index 0000000000..772331631b --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st2.rs @@ -0,0 +1,655 @@ +#[doc = "Register `EVT_ST2` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_ST2` writer"] +pub type W = crate::W; +#[doc = "Field `MCPWM0_EVT_TIMER2_TEZ_ST` reader - Represents MCPWM0_evt_timer2_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER2_TEZ_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TIMER2_TEZ_ST` writer - Represents MCPWM0_evt_timer2_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER2_TEZ_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER0_TEP_ST` reader - Represents MCPWM0_evt_timer0_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER0_TEP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TIMER0_TEP_ST` writer - Represents MCPWM0_evt_timer0_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER0_TEP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER1_TEP_ST` reader - Represents MCPWM0_evt_timer1_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER1_TEP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TIMER1_TEP_ST` writer - Represents MCPWM0_evt_timer1_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER1_TEP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER2_TEP_ST` reader - Represents MCPWM0_evt_timer2_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER2_TEP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TIMER2_TEP_ST` writer - Represents MCPWM0_evt_timer2_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TIMER2_TEP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP0_TEA_ST` reader - Represents MCPWM0_evt_op0_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP0_TEA_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP0_TEA_ST` writer - Represents MCPWM0_evt_op0_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP0_TEA_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP1_TEA_ST` reader - Represents MCPWM0_evt_op1_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP1_TEA_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP1_TEA_ST` writer - Represents MCPWM0_evt_op1_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP1_TEA_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP2_TEA_ST` reader - Represents MCPWM0_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP2_TEA_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP2_TEA_ST` writer - Represents MCPWM0_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP2_TEA_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP0_TEB_ST` reader - Represents MCPWM0_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP0_TEB_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP0_TEB_ST` writer - Represents MCPWM0_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP0_TEB_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP1_TEB_ST` reader - Represents MCPWM0_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP1_TEB_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP1_TEB_ST` writer - Represents MCPWM0_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP1_TEB_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP2_TEB_ST` reader - Represents MCPWM0_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP2_TEB_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP2_TEB_ST` writer - Represents MCPWM0_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP2_TEB_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F0_ST` reader - Represents MCPWM0_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F0_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_F0_ST` writer - Represents MCPWM0_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F1_ST` reader - Represents MCPWM0_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_F1_ST` writer - Represents MCPWM0_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F2_ST` reader - Represents MCPWM0_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_F2_ST` writer - Represents MCPWM0_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F0_CLR_ST` reader - Represents MCPWM0_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F0_CLR_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_F0_CLR_ST` writer - Represents MCPWM0_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F0_CLR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F1_CLR_ST` reader - Represents MCPWM0_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F1_CLR_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_F1_CLR_ST` writer - Represents MCPWM0_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F1_CLR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F2_CLR_ST` reader - Represents MCPWM0_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F2_CLR_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_F2_CLR_ST` writer - Represents MCPWM0_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_F2_CLR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ0_CBC_ST` reader - Represents MCPWM0_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ0_CBC_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TZ0_CBC_ST` writer - Represents MCPWM0_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ0_CBC_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ1_CBC_ST` reader - Represents MCPWM0_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ1_CBC_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TZ1_CBC_ST` writer - Represents MCPWM0_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ1_CBC_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ2_CBC_ST` reader - Represents MCPWM0_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ2_CBC_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TZ2_CBC_ST` writer - Represents MCPWM0_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ2_CBC_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ0_OST_ST` reader - Represents MCPWM0_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ0_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TZ0_OST_ST` writer - Represents MCPWM0_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ1_OST_ST` reader - Represents MCPWM0_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ1_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TZ1_OST_ST` writer - Represents MCPWM0_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ2_OST_ST` reader - Represents MCPWM0_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ2_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_TZ2_OST_ST` writer - Represents MCPWM0_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_TZ2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_CAP0_ST` reader - Represents MCPWM0_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_CAP0_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_CAP0_ST` writer - Represents MCPWM0_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_CAP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_CAP1_ST` reader - Represents MCPWM0_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_CAP1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_CAP1_ST` writer - Represents MCPWM0_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_CAP1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_CAP2_ST` reader - Represents MCPWM0_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_CAP2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_CAP2_ST` writer - Represents MCPWM0_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_CAP2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP0_TEE1_ST` reader - Represents MCPWM0_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP0_TEE1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP0_TEE1_ST` writer - Represents MCPWM0_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP0_TEE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP1_TEE1_ST` reader - Represents MCPWM0_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP1_TEE1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP1_TEE1_ST` writer - Represents MCPWM0_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP1_TEE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP2_TEE1_ST` reader - Represents MCPWM0_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP2_TEE1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP2_TEE1_ST` writer - Represents MCPWM0_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP2_TEE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP0_TEE2_ST` reader - Represents MCPWM0_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP0_TEE2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP0_TEE2_ST` writer - Represents MCPWM0_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP0_TEE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP1_TEE2_ST` reader - Represents MCPWM0_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP1_TEE2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP1_TEE2_ST` writer - Represents MCPWM0_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP1_TEE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP2_TEE2_ST` reader - Represents MCPWM0_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP2_TEE2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_EVT_OP2_TEE2_ST` writer - Represents MCPWM0_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_EVT_OP2_TEE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER0_STOP_ST` reader - Represents MCPWM1_evt_timer0_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER0_STOP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TIMER0_STOP_ST` writer - Represents MCPWM1_evt_timer0_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER0_STOP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents MCPWM0_evt_timer2_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_timer2_tez_st(&self) -> MCPWM0_EVT_TIMER2_TEZ_ST_R { + MCPWM0_EVT_TIMER2_TEZ_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents MCPWM0_evt_timer0_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_timer0_tep_st(&self) -> MCPWM0_EVT_TIMER0_TEP_ST_R { + MCPWM0_EVT_TIMER0_TEP_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents MCPWM0_evt_timer1_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_timer1_tep_st(&self) -> MCPWM0_EVT_TIMER1_TEP_ST_R { + MCPWM0_EVT_TIMER1_TEP_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents MCPWM0_evt_timer2_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_timer2_tep_st(&self) -> MCPWM0_EVT_TIMER2_TEP_ST_R { + MCPWM0_EVT_TIMER2_TEP_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents MCPWM0_evt_op0_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op0_tea_st(&self) -> MCPWM0_EVT_OP0_TEA_ST_R { + MCPWM0_EVT_OP0_TEA_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents MCPWM0_evt_op1_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op1_tea_st(&self) -> MCPWM0_EVT_OP1_TEA_ST_R { + MCPWM0_EVT_OP1_TEA_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents MCPWM0_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op2_tea_st(&self) -> MCPWM0_EVT_OP2_TEA_ST_R { + MCPWM0_EVT_OP2_TEA_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents MCPWM0_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op0_teb_st(&self) -> MCPWM0_EVT_OP0_TEB_ST_R { + MCPWM0_EVT_OP0_TEB_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents MCPWM0_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op1_teb_st(&self) -> MCPWM0_EVT_OP1_TEB_ST_R { + MCPWM0_EVT_OP1_TEB_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents MCPWM0_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op2_teb_st(&self) -> MCPWM0_EVT_OP2_TEB_ST_R { + MCPWM0_EVT_OP2_TEB_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents MCPWM0_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_f0_st(&self) -> MCPWM0_EVT_F0_ST_R { + MCPWM0_EVT_F0_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents MCPWM0_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_f1_st(&self) -> MCPWM0_EVT_F1_ST_R { + MCPWM0_EVT_F1_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents MCPWM0_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_f2_st(&self) -> MCPWM0_EVT_F2_ST_R { + MCPWM0_EVT_F2_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents MCPWM0_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_f0_clr_st(&self) -> MCPWM0_EVT_F0_CLR_ST_R { + MCPWM0_EVT_F0_CLR_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents MCPWM0_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_f1_clr_st(&self) -> MCPWM0_EVT_F1_CLR_ST_R { + MCPWM0_EVT_F1_CLR_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents MCPWM0_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_f2_clr_st(&self) -> MCPWM0_EVT_F2_CLR_ST_R { + MCPWM0_EVT_F2_CLR_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents MCPWM0_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_tz0_cbc_st(&self) -> MCPWM0_EVT_TZ0_CBC_ST_R { + MCPWM0_EVT_TZ0_CBC_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents MCPWM0_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_tz1_cbc_st(&self) -> MCPWM0_EVT_TZ1_CBC_ST_R { + MCPWM0_EVT_TZ1_CBC_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents MCPWM0_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_tz2_cbc_st(&self) -> MCPWM0_EVT_TZ2_CBC_ST_R { + MCPWM0_EVT_TZ2_CBC_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents MCPWM0_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_tz0_ost_st(&self) -> MCPWM0_EVT_TZ0_OST_ST_R { + MCPWM0_EVT_TZ0_OST_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents MCPWM0_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_tz1_ost_st(&self) -> MCPWM0_EVT_TZ1_OST_ST_R { + MCPWM0_EVT_TZ1_OST_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents MCPWM0_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_tz2_ost_st(&self) -> MCPWM0_EVT_TZ2_OST_ST_R { + MCPWM0_EVT_TZ2_OST_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents MCPWM0_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_cap0_st(&self) -> MCPWM0_EVT_CAP0_ST_R { + MCPWM0_EVT_CAP0_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents MCPWM0_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_cap1_st(&self) -> MCPWM0_EVT_CAP1_ST_R { + MCPWM0_EVT_CAP1_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents MCPWM0_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_cap2_st(&self) -> MCPWM0_EVT_CAP2_ST_R { + MCPWM0_EVT_CAP2_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents MCPWM0_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op0_tee1_st(&self) -> MCPWM0_EVT_OP0_TEE1_ST_R { + MCPWM0_EVT_OP0_TEE1_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents MCPWM0_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op1_tee1_st(&self) -> MCPWM0_EVT_OP1_TEE1_ST_R { + MCPWM0_EVT_OP1_TEE1_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents MCPWM0_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op2_tee1_st(&self) -> MCPWM0_EVT_OP2_TEE1_ST_R { + MCPWM0_EVT_OP2_TEE1_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents MCPWM0_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op0_tee2_st(&self) -> MCPWM0_EVT_OP0_TEE2_ST_R { + MCPWM0_EVT_OP0_TEE2_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents MCPWM0_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op1_tee2_st(&self) -> MCPWM0_EVT_OP1_TEE2_ST_R { + MCPWM0_EVT_OP1_TEE2_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents MCPWM0_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_evt_op2_tee2_st(&self) -> MCPWM0_EVT_OP2_TEE2_ST_R { + MCPWM0_EVT_OP2_TEE2_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents MCPWM1_evt_timer0_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_timer0_stop_st(&self) -> MCPWM1_EVT_TIMER0_STOP_ST_R { + MCPWM1_EVT_TIMER0_STOP_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_ST2") + .field( + "mcpwm0_evt_timer2_tez_st", + &format_args!("{}", self.mcpwm0_evt_timer2_tez_st().bit()), + ) + .field( + "mcpwm0_evt_timer0_tep_st", + &format_args!("{}", self.mcpwm0_evt_timer0_tep_st().bit()), + ) + .field( + "mcpwm0_evt_timer1_tep_st", + &format_args!("{}", self.mcpwm0_evt_timer1_tep_st().bit()), + ) + .field( + "mcpwm0_evt_timer2_tep_st", + &format_args!("{}", self.mcpwm0_evt_timer2_tep_st().bit()), + ) + .field( + "mcpwm0_evt_op0_tea_st", + &format_args!("{}", self.mcpwm0_evt_op0_tea_st().bit()), + ) + .field( + "mcpwm0_evt_op1_tea_st", + &format_args!("{}", self.mcpwm0_evt_op1_tea_st().bit()), + ) + .field( + "mcpwm0_evt_op2_tea_st", + &format_args!("{}", self.mcpwm0_evt_op2_tea_st().bit()), + ) + .field( + "mcpwm0_evt_op0_teb_st", + &format_args!("{}", self.mcpwm0_evt_op0_teb_st().bit()), + ) + .field( + "mcpwm0_evt_op1_teb_st", + &format_args!("{}", self.mcpwm0_evt_op1_teb_st().bit()), + ) + .field( + "mcpwm0_evt_op2_teb_st", + &format_args!("{}", self.mcpwm0_evt_op2_teb_st().bit()), + ) + .field( + "mcpwm0_evt_f0_st", + &format_args!("{}", self.mcpwm0_evt_f0_st().bit()), + ) + .field( + "mcpwm0_evt_f1_st", + &format_args!("{}", self.mcpwm0_evt_f1_st().bit()), + ) + .field( + "mcpwm0_evt_f2_st", + &format_args!("{}", self.mcpwm0_evt_f2_st().bit()), + ) + .field( + "mcpwm0_evt_f0_clr_st", + &format_args!("{}", self.mcpwm0_evt_f0_clr_st().bit()), + ) + .field( + "mcpwm0_evt_f1_clr_st", + &format_args!("{}", self.mcpwm0_evt_f1_clr_st().bit()), + ) + .field( + "mcpwm0_evt_f2_clr_st", + &format_args!("{}", self.mcpwm0_evt_f2_clr_st().bit()), + ) + .field( + "mcpwm0_evt_tz0_cbc_st", + &format_args!("{}", self.mcpwm0_evt_tz0_cbc_st().bit()), + ) + .field( + "mcpwm0_evt_tz1_cbc_st", + &format_args!("{}", self.mcpwm0_evt_tz1_cbc_st().bit()), + ) + .field( + "mcpwm0_evt_tz2_cbc_st", + &format_args!("{}", self.mcpwm0_evt_tz2_cbc_st().bit()), + ) + .field( + "mcpwm0_evt_tz0_ost_st", + &format_args!("{}", self.mcpwm0_evt_tz0_ost_st().bit()), + ) + .field( + "mcpwm0_evt_tz1_ost_st", + &format_args!("{}", self.mcpwm0_evt_tz1_ost_st().bit()), + ) + .field( + "mcpwm0_evt_tz2_ost_st", + &format_args!("{}", self.mcpwm0_evt_tz2_ost_st().bit()), + ) + .field( + "mcpwm0_evt_cap0_st", + &format_args!("{}", self.mcpwm0_evt_cap0_st().bit()), + ) + .field( + "mcpwm0_evt_cap1_st", + &format_args!("{}", self.mcpwm0_evt_cap1_st().bit()), + ) + .field( + "mcpwm0_evt_cap2_st", + &format_args!("{}", self.mcpwm0_evt_cap2_st().bit()), + ) + .field( + "mcpwm0_evt_op0_tee1_st", + &format_args!("{}", self.mcpwm0_evt_op0_tee1_st().bit()), + ) + .field( + "mcpwm0_evt_op1_tee1_st", + &format_args!("{}", self.mcpwm0_evt_op1_tee1_st().bit()), + ) + .field( + "mcpwm0_evt_op2_tee1_st", + &format_args!("{}", self.mcpwm0_evt_op2_tee1_st().bit()), + ) + .field( + "mcpwm0_evt_op0_tee2_st", + &format_args!("{}", self.mcpwm0_evt_op0_tee2_st().bit()), + ) + .field( + "mcpwm0_evt_op1_tee2_st", + &format_args!("{}", self.mcpwm0_evt_op1_tee2_st().bit()), + ) + .field( + "mcpwm0_evt_op2_tee2_st", + &format_args!("{}", self.mcpwm0_evt_op2_tee2_st().bit()), + ) + .field( + "mcpwm1_evt_timer0_stop_st", + &format_args!("{}", self.mcpwm1_evt_timer0_stop_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents MCPWM0_evt_timer2_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer2_tez_st(&mut self) -> MCPWM0_EVT_TIMER2_TEZ_ST_W { + MCPWM0_EVT_TIMER2_TEZ_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents MCPWM0_evt_timer0_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer0_tep_st(&mut self) -> MCPWM0_EVT_TIMER0_TEP_ST_W { + MCPWM0_EVT_TIMER0_TEP_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents MCPWM0_evt_timer1_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer1_tep_st(&mut self) -> MCPWM0_EVT_TIMER1_TEP_ST_W { + MCPWM0_EVT_TIMER1_TEP_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents MCPWM0_evt_timer2_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer2_tep_st(&mut self) -> MCPWM0_EVT_TIMER2_TEP_ST_W { + MCPWM0_EVT_TIMER2_TEP_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents MCPWM0_evt_op0_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op0_tea_st(&mut self) -> MCPWM0_EVT_OP0_TEA_ST_W { + MCPWM0_EVT_OP0_TEA_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents MCPWM0_evt_op1_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op1_tea_st(&mut self) -> MCPWM0_EVT_OP1_TEA_ST_W { + MCPWM0_EVT_OP1_TEA_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents MCPWM0_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op2_tea_st(&mut self) -> MCPWM0_EVT_OP2_TEA_ST_W { + MCPWM0_EVT_OP2_TEA_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents MCPWM0_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op0_teb_st(&mut self) -> MCPWM0_EVT_OP0_TEB_ST_W { + MCPWM0_EVT_OP0_TEB_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents MCPWM0_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op1_teb_st(&mut self) -> MCPWM0_EVT_OP1_TEB_ST_W { + MCPWM0_EVT_OP1_TEB_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents MCPWM0_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op2_teb_st(&mut self) -> MCPWM0_EVT_OP2_TEB_ST_W { + MCPWM0_EVT_OP2_TEB_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents MCPWM0_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f0_st(&mut self) -> MCPWM0_EVT_F0_ST_W { + MCPWM0_EVT_F0_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents MCPWM0_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f1_st(&mut self) -> MCPWM0_EVT_F1_ST_W { + MCPWM0_EVT_F1_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents MCPWM0_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f2_st(&mut self) -> MCPWM0_EVT_F2_ST_W { + MCPWM0_EVT_F2_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents MCPWM0_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f0_clr_st(&mut self) -> MCPWM0_EVT_F0_CLR_ST_W { + MCPWM0_EVT_F0_CLR_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents MCPWM0_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f1_clr_st(&mut self) -> MCPWM0_EVT_F1_CLR_ST_W { + MCPWM0_EVT_F1_CLR_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents MCPWM0_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f2_clr_st(&mut self) -> MCPWM0_EVT_F2_CLR_ST_W { + MCPWM0_EVT_F2_CLR_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents MCPWM0_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz0_cbc_st(&mut self) -> MCPWM0_EVT_TZ0_CBC_ST_W { + MCPWM0_EVT_TZ0_CBC_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents MCPWM0_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz1_cbc_st(&mut self) -> MCPWM0_EVT_TZ1_CBC_ST_W { + MCPWM0_EVT_TZ1_CBC_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents MCPWM0_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz2_cbc_st(&mut self) -> MCPWM0_EVT_TZ2_CBC_ST_W { + MCPWM0_EVT_TZ2_CBC_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents MCPWM0_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz0_ost_st(&mut self) -> MCPWM0_EVT_TZ0_OST_ST_W { + MCPWM0_EVT_TZ0_OST_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents MCPWM0_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz1_ost_st(&mut self) -> MCPWM0_EVT_TZ1_OST_ST_W { + MCPWM0_EVT_TZ1_OST_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents MCPWM0_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz2_ost_st(&mut self) -> MCPWM0_EVT_TZ2_OST_ST_W { + MCPWM0_EVT_TZ2_OST_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents MCPWM0_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_cap0_st(&mut self) -> MCPWM0_EVT_CAP0_ST_W { + MCPWM0_EVT_CAP0_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents MCPWM0_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_cap1_st(&mut self) -> MCPWM0_EVT_CAP1_ST_W { + MCPWM0_EVT_CAP1_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents MCPWM0_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_cap2_st(&mut self) -> MCPWM0_EVT_CAP2_ST_W { + MCPWM0_EVT_CAP2_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents MCPWM0_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op0_tee1_st(&mut self) -> MCPWM0_EVT_OP0_TEE1_ST_W { + MCPWM0_EVT_OP0_TEE1_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents MCPWM0_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op1_tee1_st(&mut self) -> MCPWM0_EVT_OP1_TEE1_ST_W { + MCPWM0_EVT_OP1_TEE1_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents MCPWM0_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op2_tee1_st(&mut self) -> MCPWM0_EVT_OP2_TEE1_ST_W { + MCPWM0_EVT_OP2_TEE1_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents MCPWM0_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op0_tee2_st(&mut self) -> MCPWM0_EVT_OP0_TEE2_ST_W { + MCPWM0_EVT_OP0_TEE2_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents MCPWM0_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op1_tee2_st(&mut self) -> MCPWM0_EVT_OP1_TEE2_ST_W { + MCPWM0_EVT_OP1_TEE2_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents MCPWM0_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op2_tee2_st(&mut self) -> MCPWM0_EVT_OP2_TEE2_ST_W { + MCPWM0_EVT_OP2_TEE2_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents MCPWM1_evt_timer0_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer0_stop_st(&mut self) -> MCPWM1_EVT_TIMER0_STOP_ST_W { + MCPWM1_EVT_TIMER0_STOP_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST2_SPEC; +impl crate::RegisterSpec for EVT_ST2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_st2::R`](R) reader structure"] +impl crate::Readable for EVT_ST2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_st2::W`](W) writer structure"] +impl crate::Writable for EVT_ST2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST2 to value 0"] +impl crate::Resettable for EVT_ST2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st2_clr.rs b/esp32p4/src/soc_etm/evt_st2_clr.rs new file mode 100644 index 0000000000..fb022ddaff --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st2_clr.rs @@ -0,0 +1,300 @@ +#[doc = "Register `EVT_ST2_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `MCPWM0_EVT_TIMER2_TEZ_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TIMER2_TEZ_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER0_TEP_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TIMER0_TEP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER1_TEP_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TIMER1_TEP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TIMER2_TEP_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TIMER2_TEP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP0_TEA_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP0_TEA_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP1_TEA_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP1_TEA_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP2_TEA_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP2_TEA_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP0_TEB_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP0_TEB_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP1_TEB_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP1_TEB_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP2_TEB_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP2_TEB_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F0_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_F0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F1_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_F1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F2_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_F2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F0_CLR_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_F0_CLR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F1_CLR_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_F1_CLR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_F2_CLR_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_F2_CLR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ0_CBC_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TZ0_CBC_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ1_CBC_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TZ1_CBC_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ2_CBC_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TZ2_CBC_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ0_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TZ0_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ1_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TZ1_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_TZ2_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_TZ2_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_CAP0_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_CAP0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_CAP1_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_CAP1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_CAP2_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_CAP2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP0_TEE1_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP0_TEE1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP1_TEE1_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP1_TEE1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP2_TEE1_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP2_TEE1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP0_TEE2_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP0_TEE2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP1_TEE2_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP1_TEE2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_EVT_OP2_TEE2_ST_CLR` writer - Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_EVT_OP2_TEE2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER0_STOP_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TIMER0_STOP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer2_tez_st_clr( + &mut self, + ) -> MCPWM0_EVT_TIMER2_TEZ_ST_CLR_W { + MCPWM0_EVT_TIMER2_TEZ_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer0_tep_st_clr( + &mut self, + ) -> MCPWM0_EVT_TIMER0_TEP_ST_CLR_W { + MCPWM0_EVT_TIMER0_TEP_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer1_tep_st_clr( + &mut self, + ) -> MCPWM0_EVT_TIMER1_TEP_ST_CLR_W { + MCPWM0_EVT_TIMER1_TEP_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_timer2_tep_st_clr( + &mut self, + ) -> MCPWM0_EVT_TIMER2_TEP_ST_CLR_W { + MCPWM0_EVT_TIMER2_TEP_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op0_tea_st_clr(&mut self) -> MCPWM0_EVT_OP0_TEA_ST_CLR_W { + MCPWM0_EVT_OP0_TEA_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op1_tea_st_clr(&mut self) -> MCPWM0_EVT_OP1_TEA_ST_CLR_W { + MCPWM0_EVT_OP1_TEA_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op2_tea_st_clr(&mut self) -> MCPWM0_EVT_OP2_TEA_ST_CLR_W { + MCPWM0_EVT_OP2_TEA_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op0_teb_st_clr(&mut self) -> MCPWM0_EVT_OP0_TEB_ST_CLR_W { + MCPWM0_EVT_OP0_TEB_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op1_teb_st_clr(&mut self) -> MCPWM0_EVT_OP1_TEB_ST_CLR_W { + MCPWM0_EVT_OP1_TEB_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op2_teb_st_clr(&mut self) -> MCPWM0_EVT_OP2_TEB_ST_CLR_W { + MCPWM0_EVT_OP2_TEB_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f0_st_clr(&mut self) -> MCPWM0_EVT_F0_ST_CLR_W { + MCPWM0_EVT_F0_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f1_st_clr(&mut self) -> MCPWM0_EVT_F1_ST_CLR_W { + MCPWM0_EVT_F1_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f2_st_clr(&mut self) -> MCPWM0_EVT_F2_ST_CLR_W { + MCPWM0_EVT_F2_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f0_clr_st_clr(&mut self) -> MCPWM0_EVT_F0_CLR_ST_CLR_W { + MCPWM0_EVT_F0_CLR_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f1_clr_st_clr(&mut self) -> MCPWM0_EVT_F1_CLR_ST_CLR_W { + MCPWM0_EVT_F1_CLR_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_f2_clr_st_clr(&mut self) -> MCPWM0_EVT_F2_CLR_ST_CLR_W { + MCPWM0_EVT_F2_CLR_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz0_cbc_st_clr(&mut self) -> MCPWM0_EVT_TZ0_CBC_ST_CLR_W { + MCPWM0_EVT_TZ0_CBC_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz1_cbc_st_clr(&mut self) -> MCPWM0_EVT_TZ1_CBC_ST_CLR_W { + MCPWM0_EVT_TZ1_CBC_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz2_cbc_st_clr(&mut self) -> MCPWM0_EVT_TZ2_CBC_ST_CLR_W { + MCPWM0_EVT_TZ2_CBC_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz0_ost_st_clr(&mut self) -> MCPWM0_EVT_TZ0_OST_ST_CLR_W { + MCPWM0_EVT_TZ0_OST_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz1_ost_st_clr(&mut self) -> MCPWM0_EVT_TZ1_OST_ST_CLR_W { + MCPWM0_EVT_TZ1_OST_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_tz2_ost_st_clr(&mut self) -> MCPWM0_EVT_TZ2_OST_ST_CLR_W { + MCPWM0_EVT_TZ2_OST_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_cap0_st_clr(&mut self) -> MCPWM0_EVT_CAP0_ST_CLR_W { + MCPWM0_EVT_CAP0_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_cap1_st_clr(&mut self) -> MCPWM0_EVT_CAP1_ST_CLR_W { + MCPWM0_EVT_CAP1_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_cap2_st_clr(&mut self) -> MCPWM0_EVT_CAP2_ST_CLR_W { + MCPWM0_EVT_CAP2_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op0_tee1_st_clr(&mut self) -> MCPWM0_EVT_OP0_TEE1_ST_CLR_W { + MCPWM0_EVT_OP0_TEE1_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op1_tee1_st_clr(&mut self) -> MCPWM0_EVT_OP1_TEE1_ST_CLR_W { + MCPWM0_EVT_OP1_TEE1_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op2_tee1_st_clr(&mut self) -> MCPWM0_EVT_OP2_TEE1_ST_CLR_W { + MCPWM0_EVT_OP2_TEE1_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op0_tee2_st_clr(&mut self) -> MCPWM0_EVT_OP0_TEE2_ST_CLR_W { + MCPWM0_EVT_OP0_TEE2_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op1_tee2_st_clr(&mut self) -> MCPWM0_EVT_OP1_TEE2_ST_CLR_W { + MCPWM0_EVT_OP1_TEE2_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_evt_op2_tee2_st_clr(&mut self) -> MCPWM0_EVT_OP2_TEE2_ST_CLR_W { + MCPWM0_EVT_OP2_TEE2_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer0_stop_st_clr( + &mut self, + ) -> MCPWM1_EVT_TIMER0_STOP_ST_CLR_W { + MCPWM1_EVT_TIMER0_STOP_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st2_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST2_CLR_SPEC; +impl crate::RegisterSpec for EVT_ST2_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`evt_st2_clr::W`](W) writer structure"] +impl crate::Writable for EVT_ST2_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST2_CLR to value 0"] +impl crate::Resettable for EVT_ST2_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st3.rs b/esp32p4/src/soc_etm/evt_st3.rs new file mode 100644 index 0000000000..7c494a7a3d --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st3.rs @@ -0,0 +1,655 @@ +#[doc = "Register `EVT_ST3` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_ST3` writer"] +pub type W = crate::W; +#[doc = "Field `MCPWM1_EVT_TIMER1_STOP_ST` reader - Represents MCPWM1_evt_timer1_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER1_STOP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TIMER1_STOP_ST` writer - Represents MCPWM1_evt_timer1_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER1_STOP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER2_STOP_ST` reader - Represents MCPWM1_evt_timer2_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER2_STOP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TIMER2_STOP_ST` writer - Represents MCPWM1_evt_timer2_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER2_STOP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER0_TEZ_ST` reader - Represents MCPWM1_evt_timer0_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER0_TEZ_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TIMER0_TEZ_ST` writer - Represents MCPWM1_evt_timer0_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER0_TEZ_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER1_TEZ_ST` reader - Represents MCPWM1_evt_timer1_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER1_TEZ_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TIMER1_TEZ_ST` writer - Represents MCPWM1_evt_timer1_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER1_TEZ_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER2_TEZ_ST` reader - Represents MCPWM1_evt_timer2_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER2_TEZ_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TIMER2_TEZ_ST` writer - Represents MCPWM1_evt_timer2_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER2_TEZ_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER0_TEP_ST` reader - Represents MCPWM1_evt_timer0_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER0_TEP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TIMER0_TEP_ST` writer - Represents MCPWM1_evt_timer0_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER0_TEP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER1_TEP_ST` reader - Represents MCPWM1_evt_timer1_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER1_TEP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TIMER1_TEP_ST` writer - Represents MCPWM1_evt_timer1_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER1_TEP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER2_TEP_ST` reader - Represents MCPWM1_evt_timer2_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER2_TEP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TIMER2_TEP_ST` writer - Represents MCPWM1_evt_timer2_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TIMER2_TEP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP0_TEA_ST` reader - Represents MCPWM1_evt_op0_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP0_TEA_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP0_TEA_ST` writer - Represents MCPWM1_evt_op0_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP0_TEA_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP1_TEA_ST` reader - Represents MCPWM1_evt_op1_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP1_TEA_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP1_TEA_ST` writer - Represents MCPWM1_evt_op1_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP1_TEA_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP2_TEA_ST` reader - Represents MCPWM1_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP2_TEA_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP2_TEA_ST` writer - Represents MCPWM1_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP2_TEA_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP0_TEB_ST` reader - Represents MCPWM1_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP0_TEB_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP0_TEB_ST` writer - Represents MCPWM1_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP0_TEB_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP1_TEB_ST` reader - Represents MCPWM1_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP1_TEB_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP1_TEB_ST` writer - Represents MCPWM1_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP1_TEB_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP2_TEB_ST` reader - Represents MCPWM1_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP2_TEB_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP2_TEB_ST` writer - Represents MCPWM1_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP2_TEB_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F0_ST` reader - Represents MCPWM1_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F0_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_F0_ST` writer - Represents MCPWM1_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F1_ST` reader - Represents MCPWM1_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_F1_ST` writer - Represents MCPWM1_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F2_ST` reader - Represents MCPWM1_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_F2_ST` writer - Represents MCPWM1_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F0_CLR_ST` reader - Represents MCPWM1_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F0_CLR_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_F0_CLR_ST` writer - Represents MCPWM1_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F0_CLR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F1_CLR_ST` reader - Represents MCPWM1_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F1_CLR_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_F1_CLR_ST` writer - Represents MCPWM1_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F1_CLR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F2_CLR_ST` reader - Represents MCPWM1_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F2_CLR_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_F2_CLR_ST` writer - Represents MCPWM1_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_F2_CLR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ0_CBC_ST` reader - Represents MCPWM1_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ0_CBC_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TZ0_CBC_ST` writer - Represents MCPWM1_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ0_CBC_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ1_CBC_ST` reader - Represents MCPWM1_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ1_CBC_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TZ1_CBC_ST` writer - Represents MCPWM1_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ1_CBC_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ2_CBC_ST` reader - Represents MCPWM1_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ2_CBC_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TZ2_CBC_ST` writer - Represents MCPWM1_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ2_CBC_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ0_OST_ST` reader - Represents MCPWM1_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ0_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TZ0_OST_ST` writer - Represents MCPWM1_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ1_OST_ST` reader - Represents MCPWM1_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ1_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TZ1_OST_ST` writer - Represents MCPWM1_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ2_OST_ST` reader - Represents MCPWM1_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ2_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_TZ2_OST_ST` writer - Represents MCPWM1_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_TZ2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_CAP0_ST` reader - Represents MCPWM1_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_CAP0_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_CAP0_ST` writer - Represents MCPWM1_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_CAP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_CAP1_ST` reader - Represents MCPWM1_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_CAP1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_CAP1_ST` writer - Represents MCPWM1_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_CAP1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_CAP2_ST` reader - Represents MCPWM1_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_CAP2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_CAP2_ST` writer - Represents MCPWM1_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_CAP2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP0_TEE1_ST` reader - Represents MCPWM1_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP0_TEE1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP0_TEE1_ST` writer - Represents MCPWM1_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP0_TEE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP1_TEE1_ST` reader - Represents MCPWM1_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP1_TEE1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP1_TEE1_ST` writer - Represents MCPWM1_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP1_TEE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP2_TEE1_ST` reader - Represents MCPWM1_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP2_TEE1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP2_TEE1_ST` writer - Represents MCPWM1_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP2_TEE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents MCPWM1_evt_timer1_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_timer1_stop_st(&self) -> MCPWM1_EVT_TIMER1_STOP_ST_R { + MCPWM1_EVT_TIMER1_STOP_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents MCPWM1_evt_timer2_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_timer2_stop_st(&self) -> MCPWM1_EVT_TIMER2_STOP_ST_R { + MCPWM1_EVT_TIMER2_STOP_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents MCPWM1_evt_timer0_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_timer0_tez_st(&self) -> MCPWM1_EVT_TIMER0_TEZ_ST_R { + MCPWM1_EVT_TIMER0_TEZ_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents MCPWM1_evt_timer1_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_timer1_tez_st(&self) -> MCPWM1_EVT_TIMER1_TEZ_ST_R { + MCPWM1_EVT_TIMER1_TEZ_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents MCPWM1_evt_timer2_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_timer2_tez_st(&self) -> MCPWM1_EVT_TIMER2_TEZ_ST_R { + MCPWM1_EVT_TIMER2_TEZ_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents MCPWM1_evt_timer0_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_timer0_tep_st(&self) -> MCPWM1_EVT_TIMER0_TEP_ST_R { + MCPWM1_EVT_TIMER0_TEP_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents MCPWM1_evt_timer1_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_timer1_tep_st(&self) -> MCPWM1_EVT_TIMER1_TEP_ST_R { + MCPWM1_EVT_TIMER1_TEP_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents MCPWM1_evt_timer2_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_timer2_tep_st(&self) -> MCPWM1_EVT_TIMER2_TEP_ST_R { + MCPWM1_EVT_TIMER2_TEP_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents MCPWM1_evt_op0_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op0_tea_st(&self) -> MCPWM1_EVT_OP0_TEA_ST_R { + MCPWM1_EVT_OP0_TEA_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents MCPWM1_evt_op1_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op1_tea_st(&self) -> MCPWM1_EVT_OP1_TEA_ST_R { + MCPWM1_EVT_OP1_TEA_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents MCPWM1_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op2_tea_st(&self) -> MCPWM1_EVT_OP2_TEA_ST_R { + MCPWM1_EVT_OP2_TEA_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents MCPWM1_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op0_teb_st(&self) -> MCPWM1_EVT_OP0_TEB_ST_R { + MCPWM1_EVT_OP0_TEB_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents MCPWM1_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op1_teb_st(&self) -> MCPWM1_EVT_OP1_TEB_ST_R { + MCPWM1_EVT_OP1_TEB_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents MCPWM1_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op2_teb_st(&self) -> MCPWM1_EVT_OP2_TEB_ST_R { + MCPWM1_EVT_OP2_TEB_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents MCPWM1_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_f0_st(&self) -> MCPWM1_EVT_F0_ST_R { + MCPWM1_EVT_F0_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents MCPWM1_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_f1_st(&self) -> MCPWM1_EVT_F1_ST_R { + MCPWM1_EVT_F1_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents MCPWM1_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_f2_st(&self) -> MCPWM1_EVT_F2_ST_R { + MCPWM1_EVT_F2_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents MCPWM1_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_f0_clr_st(&self) -> MCPWM1_EVT_F0_CLR_ST_R { + MCPWM1_EVT_F0_CLR_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents MCPWM1_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_f1_clr_st(&self) -> MCPWM1_EVT_F1_CLR_ST_R { + MCPWM1_EVT_F1_CLR_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents MCPWM1_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_f2_clr_st(&self) -> MCPWM1_EVT_F2_CLR_ST_R { + MCPWM1_EVT_F2_CLR_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents MCPWM1_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_tz0_cbc_st(&self) -> MCPWM1_EVT_TZ0_CBC_ST_R { + MCPWM1_EVT_TZ0_CBC_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents MCPWM1_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_tz1_cbc_st(&self) -> MCPWM1_EVT_TZ1_CBC_ST_R { + MCPWM1_EVT_TZ1_CBC_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents MCPWM1_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_tz2_cbc_st(&self) -> MCPWM1_EVT_TZ2_CBC_ST_R { + MCPWM1_EVT_TZ2_CBC_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents MCPWM1_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_tz0_ost_st(&self) -> MCPWM1_EVT_TZ0_OST_ST_R { + MCPWM1_EVT_TZ0_OST_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents MCPWM1_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_tz1_ost_st(&self) -> MCPWM1_EVT_TZ1_OST_ST_R { + MCPWM1_EVT_TZ1_OST_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents MCPWM1_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_tz2_ost_st(&self) -> MCPWM1_EVT_TZ2_OST_ST_R { + MCPWM1_EVT_TZ2_OST_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents MCPWM1_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_cap0_st(&self) -> MCPWM1_EVT_CAP0_ST_R { + MCPWM1_EVT_CAP0_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents MCPWM1_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_cap1_st(&self) -> MCPWM1_EVT_CAP1_ST_R { + MCPWM1_EVT_CAP1_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents MCPWM1_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_cap2_st(&self) -> MCPWM1_EVT_CAP2_ST_R { + MCPWM1_EVT_CAP2_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents MCPWM1_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op0_tee1_st(&self) -> MCPWM1_EVT_OP0_TEE1_ST_R { + MCPWM1_EVT_OP0_TEE1_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents MCPWM1_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op1_tee1_st(&self) -> MCPWM1_EVT_OP1_TEE1_ST_R { + MCPWM1_EVT_OP1_TEE1_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents MCPWM1_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op2_tee1_st(&self) -> MCPWM1_EVT_OP2_TEE1_ST_R { + MCPWM1_EVT_OP2_TEE1_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_ST3") + .field( + "mcpwm1_evt_timer1_stop_st", + &format_args!("{}", self.mcpwm1_evt_timer1_stop_st().bit()), + ) + .field( + "mcpwm1_evt_timer2_stop_st", + &format_args!("{}", self.mcpwm1_evt_timer2_stop_st().bit()), + ) + .field( + "mcpwm1_evt_timer0_tez_st", + &format_args!("{}", self.mcpwm1_evt_timer0_tez_st().bit()), + ) + .field( + "mcpwm1_evt_timer1_tez_st", + &format_args!("{}", self.mcpwm1_evt_timer1_tez_st().bit()), + ) + .field( + "mcpwm1_evt_timer2_tez_st", + &format_args!("{}", self.mcpwm1_evt_timer2_tez_st().bit()), + ) + .field( + "mcpwm1_evt_timer0_tep_st", + &format_args!("{}", self.mcpwm1_evt_timer0_tep_st().bit()), + ) + .field( + "mcpwm1_evt_timer1_tep_st", + &format_args!("{}", self.mcpwm1_evt_timer1_tep_st().bit()), + ) + .field( + "mcpwm1_evt_timer2_tep_st", + &format_args!("{}", self.mcpwm1_evt_timer2_tep_st().bit()), + ) + .field( + "mcpwm1_evt_op0_tea_st", + &format_args!("{}", self.mcpwm1_evt_op0_tea_st().bit()), + ) + .field( + "mcpwm1_evt_op1_tea_st", + &format_args!("{}", self.mcpwm1_evt_op1_tea_st().bit()), + ) + .field( + "mcpwm1_evt_op2_tea_st", + &format_args!("{}", self.mcpwm1_evt_op2_tea_st().bit()), + ) + .field( + "mcpwm1_evt_op0_teb_st", + &format_args!("{}", self.mcpwm1_evt_op0_teb_st().bit()), + ) + .field( + "mcpwm1_evt_op1_teb_st", + &format_args!("{}", self.mcpwm1_evt_op1_teb_st().bit()), + ) + .field( + "mcpwm1_evt_op2_teb_st", + &format_args!("{}", self.mcpwm1_evt_op2_teb_st().bit()), + ) + .field( + "mcpwm1_evt_f0_st", + &format_args!("{}", self.mcpwm1_evt_f0_st().bit()), + ) + .field( + "mcpwm1_evt_f1_st", + &format_args!("{}", self.mcpwm1_evt_f1_st().bit()), + ) + .field( + "mcpwm1_evt_f2_st", + &format_args!("{}", self.mcpwm1_evt_f2_st().bit()), + ) + .field( + "mcpwm1_evt_f0_clr_st", + &format_args!("{}", self.mcpwm1_evt_f0_clr_st().bit()), + ) + .field( + "mcpwm1_evt_f1_clr_st", + &format_args!("{}", self.mcpwm1_evt_f1_clr_st().bit()), + ) + .field( + "mcpwm1_evt_f2_clr_st", + &format_args!("{}", self.mcpwm1_evt_f2_clr_st().bit()), + ) + .field( + "mcpwm1_evt_tz0_cbc_st", + &format_args!("{}", self.mcpwm1_evt_tz0_cbc_st().bit()), + ) + .field( + "mcpwm1_evt_tz1_cbc_st", + &format_args!("{}", self.mcpwm1_evt_tz1_cbc_st().bit()), + ) + .field( + "mcpwm1_evt_tz2_cbc_st", + &format_args!("{}", self.mcpwm1_evt_tz2_cbc_st().bit()), + ) + .field( + "mcpwm1_evt_tz0_ost_st", + &format_args!("{}", self.mcpwm1_evt_tz0_ost_st().bit()), + ) + .field( + "mcpwm1_evt_tz1_ost_st", + &format_args!("{}", self.mcpwm1_evt_tz1_ost_st().bit()), + ) + .field( + "mcpwm1_evt_tz2_ost_st", + &format_args!("{}", self.mcpwm1_evt_tz2_ost_st().bit()), + ) + .field( + "mcpwm1_evt_cap0_st", + &format_args!("{}", self.mcpwm1_evt_cap0_st().bit()), + ) + .field( + "mcpwm1_evt_cap1_st", + &format_args!("{}", self.mcpwm1_evt_cap1_st().bit()), + ) + .field( + "mcpwm1_evt_cap2_st", + &format_args!("{}", self.mcpwm1_evt_cap2_st().bit()), + ) + .field( + "mcpwm1_evt_op0_tee1_st", + &format_args!("{}", self.mcpwm1_evt_op0_tee1_st().bit()), + ) + .field( + "mcpwm1_evt_op1_tee1_st", + &format_args!("{}", self.mcpwm1_evt_op1_tee1_st().bit()), + ) + .field( + "mcpwm1_evt_op2_tee1_st", + &format_args!("{}", self.mcpwm1_evt_op2_tee1_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents MCPWM1_evt_timer1_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer1_stop_st(&mut self) -> MCPWM1_EVT_TIMER1_STOP_ST_W { + MCPWM1_EVT_TIMER1_STOP_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents MCPWM1_evt_timer2_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer2_stop_st(&mut self) -> MCPWM1_EVT_TIMER2_STOP_ST_W { + MCPWM1_EVT_TIMER2_STOP_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents MCPWM1_evt_timer0_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer0_tez_st(&mut self) -> MCPWM1_EVT_TIMER0_TEZ_ST_W { + MCPWM1_EVT_TIMER0_TEZ_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents MCPWM1_evt_timer1_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer1_tez_st(&mut self) -> MCPWM1_EVT_TIMER1_TEZ_ST_W { + MCPWM1_EVT_TIMER1_TEZ_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents MCPWM1_evt_timer2_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer2_tez_st(&mut self) -> MCPWM1_EVT_TIMER2_TEZ_ST_W { + MCPWM1_EVT_TIMER2_TEZ_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents MCPWM1_evt_timer0_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer0_tep_st(&mut self) -> MCPWM1_EVT_TIMER0_TEP_ST_W { + MCPWM1_EVT_TIMER0_TEP_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents MCPWM1_evt_timer1_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer1_tep_st(&mut self) -> MCPWM1_EVT_TIMER1_TEP_ST_W { + MCPWM1_EVT_TIMER1_TEP_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents MCPWM1_evt_timer2_tep trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer2_tep_st(&mut self) -> MCPWM1_EVT_TIMER2_TEP_ST_W { + MCPWM1_EVT_TIMER2_TEP_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents MCPWM1_evt_op0_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op0_tea_st(&mut self) -> MCPWM1_EVT_OP0_TEA_ST_W { + MCPWM1_EVT_OP0_TEA_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents MCPWM1_evt_op1_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op1_tea_st(&mut self) -> MCPWM1_EVT_OP1_TEA_ST_W { + MCPWM1_EVT_OP1_TEA_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents MCPWM1_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op2_tea_st(&mut self) -> MCPWM1_EVT_OP2_TEA_ST_W { + MCPWM1_EVT_OP2_TEA_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents MCPWM1_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op0_teb_st(&mut self) -> MCPWM1_EVT_OP0_TEB_ST_W { + MCPWM1_EVT_OP0_TEB_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents MCPWM1_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op1_teb_st(&mut self) -> MCPWM1_EVT_OP1_TEB_ST_W { + MCPWM1_EVT_OP1_TEB_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents MCPWM1_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op2_teb_st(&mut self) -> MCPWM1_EVT_OP2_TEB_ST_W { + MCPWM1_EVT_OP2_TEB_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents MCPWM1_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f0_st(&mut self) -> MCPWM1_EVT_F0_ST_W { + MCPWM1_EVT_F0_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents MCPWM1_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f1_st(&mut self) -> MCPWM1_EVT_F1_ST_W { + MCPWM1_EVT_F1_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents MCPWM1_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f2_st(&mut self) -> MCPWM1_EVT_F2_ST_W { + MCPWM1_EVT_F2_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents MCPWM1_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f0_clr_st(&mut self) -> MCPWM1_EVT_F0_CLR_ST_W { + MCPWM1_EVT_F0_CLR_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents MCPWM1_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f1_clr_st(&mut self) -> MCPWM1_EVT_F1_CLR_ST_W { + MCPWM1_EVT_F1_CLR_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents MCPWM1_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f2_clr_st(&mut self) -> MCPWM1_EVT_F2_CLR_ST_W { + MCPWM1_EVT_F2_CLR_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents MCPWM1_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz0_cbc_st(&mut self) -> MCPWM1_EVT_TZ0_CBC_ST_W { + MCPWM1_EVT_TZ0_CBC_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents MCPWM1_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz1_cbc_st(&mut self) -> MCPWM1_EVT_TZ1_CBC_ST_W { + MCPWM1_EVT_TZ1_CBC_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents MCPWM1_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz2_cbc_st(&mut self) -> MCPWM1_EVT_TZ2_CBC_ST_W { + MCPWM1_EVT_TZ2_CBC_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents MCPWM1_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz0_ost_st(&mut self) -> MCPWM1_EVT_TZ0_OST_ST_W { + MCPWM1_EVT_TZ0_OST_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents MCPWM1_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz1_ost_st(&mut self) -> MCPWM1_EVT_TZ1_OST_ST_W { + MCPWM1_EVT_TZ1_OST_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents MCPWM1_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz2_ost_st(&mut self) -> MCPWM1_EVT_TZ2_OST_ST_W { + MCPWM1_EVT_TZ2_OST_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents MCPWM1_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_cap0_st(&mut self) -> MCPWM1_EVT_CAP0_ST_W { + MCPWM1_EVT_CAP0_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents MCPWM1_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_cap1_st(&mut self) -> MCPWM1_EVT_CAP1_ST_W { + MCPWM1_EVT_CAP1_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents MCPWM1_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_cap2_st(&mut self) -> MCPWM1_EVT_CAP2_ST_W { + MCPWM1_EVT_CAP2_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents MCPWM1_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op0_tee1_st(&mut self) -> MCPWM1_EVT_OP0_TEE1_ST_W { + MCPWM1_EVT_OP0_TEE1_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents MCPWM1_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op1_tee1_st(&mut self) -> MCPWM1_EVT_OP1_TEE1_ST_W { + MCPWM1_EVT_OP1_TEE1_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents MCPWM1_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op2_tee1_st(&mut self) -> MCPWM1_EVT_OP2_TEE1_ST_W { + MCPWM1_EVT_OP2_TEE1_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST3_SPEC; +impl crate::RegisterSpec for EVT_ST3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_st3::R`](R) reader structure"] +impl crate::Readable for EVT_ST3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_st3::W`](W) writer structure"] +impl crate::Writable for EVT_ST3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST3 to value 0"] +impl crate::Resettable for EVT_ST3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st3_clr.rs b/esp32p4/src/soc_etm/evt_st3_clr.rs new file mode 100644 index 0000000000..cda3ed718d --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st3_clr.rs @@ -0,0 +1,306 @@ +#[doc = "Register `EVT_ST3_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `MCPWM1_EVT_TIMER1_STOP_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TIMER1_STOP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER2_STOP_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TIMER2_STOP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER0_TEZ_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TIMER0_TEZ_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER1_TEZ_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TIMER1_TEZ_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER2_TEZ_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TIMER2_TEZ_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER0_TEP_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TIMER0_TEP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER1_TEP_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TIMER1_TEP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TIMER2_TEP_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TIMER2_TEP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP0_TEA_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op0_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP0_TEA_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP1_TEA_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op1_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP1_TEA_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP2_TEA_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op2_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP2_TEA_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP0_TEB_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op0_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP0_TEB_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP1_TEB_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op1_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP1_TEB_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP2_TEB_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op2_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP2_TEB_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F0_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_F0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F1_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_F1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F2_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_F2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F0_CLR_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_f0_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_F0_CLR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F1_CLR_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_f1_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_F1_CLR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_F2_CLR_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_f2_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_F2_CLR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ0_CBC_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TZ0_CBC_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ1_CBC_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TZ1_CBC_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ2_CBC_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TZ2_CBC_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ0_OST_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TZ0_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ1_OST_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TZ1_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_TZ2_OST_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_TZ2_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_CAP0_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_CAP0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_CAP1_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_CAP1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_CAP2_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_CAP2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP0_TEE1_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP0_TEE1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP1_TEE1_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP1_TEE1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP2_TEE1_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP2_TEE1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer1_stop_st_clr( + &mut self, + ) -> MCPWM1_EVT_TIMER1_STOP_ST_CLR_W { + MCPWM1_EVT_TIMER1_STOP_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer2_stop_st_clr( + &mut self, + ) -> MCPWM1_EVT_TIMER2_STOP_ST_CLR_W { + MCPWM1_EVT_TIMER2_STOP_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer0_tez_st_clr( + &mut self, + ) -> MCPWM1_EVT_TIMER0_TEZ_ST_CLR_W { + MCPWM1_EVT_TIMER0_TEZ_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer1_tez_st_clr( + &mut self, + ) -> MCPWM1_EVT_TIMER1_TEZ_ST_CLR_W { + MCPWM1_EVT_TIMER1_TEZ_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer2_tez_st_clr( + &mut self, + ) -> MCPWM1_EVT_TIMER2_TEZ_ST_CLR_W { + MCPWM1_EVT_TIMER2_TEZ_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer0_tep_st_clr( + &mut self, + ) -> MCPWM1_EVT_TIMER0_TEP_ST_CLR_W { + MCPWM1_EVT_TIMER0_TEP_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer1_tep_st_clr( + &mut self, + ) -> MCPWM1_EVT_TIMER1_TEP_ST_CLR_W { + MCPWM1_EVT_TIMER1_TEP_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_timer2_tep_st_clr( + &mut self, + ) -> MCPWM1_EVT_TIMER2_TEP_ST_CLR_W { + MCPWM1_EVT_TIMER2_TEP_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear MCPWM1_evt_op0_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op0_tea_st_clr(&mut self) -> MCPWM1_EVT_OP0_TEA_ST_CLR_W { + MCPWM1_EVT_OP0_TEA_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear MCPWM1_evt_op1_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op1_tea_st_clr(&mut self) -> MCPWM1_EVT_OP1_TEA_ST_CLR_W { + MCPWM1_EVT_OP1_TEA_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear MCPWM1_evt_op2_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op2_tea_st_clr(&mut self) -> MCPWM1_EVT_OP2_TEA_ST_CLR_W { + MCPWM1_EVT_OP2_TEA_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear MCPWM1_evt_op0_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op0_teb_st_clr(&mut self) -> MCPWM1_EVT_OP0_TEB_ST_CLR_W { + MCPWM1_EVT_OP0_TEB_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear MCPWM1_evt_op1_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op1_teb_st_clr(&mut self) -> MCPWM1_EVT_OP1_TEB_ST_CLR_W { + MCPWM1_EVT_OP1_TEB_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear MCPWM1_evt_op2_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op2_teb_st_clr(&mut self) -> MCPWM1_EVT_OP2_TEB_ST_CLR_W { + MCPWM1_EVT_OP2_TEB_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f0_st_clr(&mut self) -> MCPWM1_EVT_F0_ST_CLR_W { + MCPWM1_EVT_F0_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f1_st_clr(&mut self) -> MCPWM1_EVT_F1_ST_CLR_W { + MCPWM1_EVT_F1_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f2_st_clr(&mut self) -> MCPWM1_EVT_F2_ST_CLR_W { + MCPWM1_EVT_F2_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear MCPWM1_evt_f0_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f0_clr_st_clr(&mut self) -> MCPWM1_EVT_F0_CLR_ST_CLR_W { + MCPWM1_EVT_F0_CLR_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear MCPWM1_evt_f1_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f1_clr_st_clr(&mut self) -> MCPWM1_EVT_F1_CLR_ST_CLR_W { + MCPWM1_EVT_F1_CLR_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear MCPWM1_evt_f2_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_f2_clr_st_clr(&mut self) -> MCPWM1_EVT_F2_CLR_ST_CLR_W { + MCPWM1_EVT_F2_CLR_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz0_cbc_st_clr(&mut self) -> MCPWM1_EVT_TZ0_CBC_ST_CLR_W { + MCPWM1_EVT_TZ0_CBC_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz1_cbc_st_clr(&mut self) -> MCPWM1_EVT_TZ1_CBC_ST_CLR_W { + MCPWM1_EVT_TZ1_CBC_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz2_cbc_st_clr(&mut self) -> MCPWM1_EVT_TZ2_CBC_ST_CLR_W { + MCPWM1_EVT_TZ2_CBC_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz0_ost_st_clr(&mut self) -> MCPWM1_EVT_TZ0_OST_ST_CLR_W { + MCPWM1_EVT_TZ0_OST_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz1_ost_st_clr(&mut self) -> MCPWM1_EVT_TZ1_OST_ST_CLR_W { + MCPWM1_EVT_TZ1_OST_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_tz2_ost_st_clr(&mut self) -> MCPWM1_EVT_TZ2_OST_ST_CLR_W { + MCPWM1_EVT_TZ2_OST_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_cap0_st_clr(&mut self) -> MCPWM1_EVT_CAP0_ST_CLR_W { + MCPWM1_EVT_CAP0_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_cap1_st_clr(&mut self) -> MCPWM1_EVT_CAP1_ST_CLR_W { + MCPWM1_EVT_CAP1_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_cap2_st_clr(&mut self) -> MCPWM1_EVT_CAP2_ST_CLR_W { + MCPWM1_EVT_CAP2_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op0_tee1_st_clr(&mut self) -> MCPWM1_EVT_OP0_TEE1_ST_CLR_W { + MCPWM1_EVT_OP0_TEE1_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op1_tee1_st_clr(&mut self) -> MCPWM1_EVT_OP1_TEE1_ST_CLR_W { + MCPWM1_EVT_OP1_TEE1_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op2_tee1_st_clr(&mut self) -> MCPWM1_EVT_OP2_TEE1_ST_CLR_W { + MCPWM1_EVT_OP2_TEE1_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st3_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST3_CLR_SPEC; +impl crate::RegisterSpec for EVT_ST3_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`evt_st3_clr::W`](W) writer structure"] +impl crate::Writable for EVT_ST3_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST3_CLR to value 0"] +impl crate::Resettable for EVT_ST3_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st4.rs b/esp32p4/src/soc_etm/evt_st4.rs new file mode 100644 index 0000000000..1d8e3aa76e --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st4.rs @@ -0,0 +1,655 @@ +#[doc = "Register `EVT_ST4` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_ST4` writer"] +pub type W = crate::W; +#[doc = "Field `MCPWM1_EVT_OP0_TEE2_ST` reader - Represents MCPWM1_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP0_TEE2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP0_TEE2_ST` writer - Represents MCPWM1_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP0_TEE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP1_TEE2_ST` reader - Represents MCPWM1_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP1_TEE2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP1_TEE2_ST` writer - Represents MCPWM1_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP1_TEE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP2_TEE2_ST` reader - Represents MCPWM1_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP2_TEE2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_EVT_OP2_TEE2_ST` writer - Represents MCPWM1_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_EVT_OP2_TEE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_CONV_CMPLT0_ST` reader - Represents ADC_evt_conv_cmplt0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_CONV_CMPLT0_ST_R = crate::BitReader; +#[doc = "Field `ADC_EVT_CONV_CMPLT0_ST` writer - Represents ADC_evt_conv_cmplt0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_CONV_CMPLT0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH0_ST` reader - Represents ADC_evt_eq_above_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_EQ_ABOVE_THRESH0_ST_R = crate::BitReader; +#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH0_ST` writer - Represents ADC_evt_eq_above_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_EQ_ABOVE_THRESH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH1_ST` reader - Represents ADC_evt_eq_above_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_EQ_ABOVE_THRESH1_ST_R = crate::BitReader; +#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH1_ST` writer - Represents ADC_evt_eq_above_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_EQ_ABOVE_THRESH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH0_ST` reader - Represents ADC_evt_eq_below_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_EQ_BELOW_THRESH0_ST_R = crate::BitReader; +#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH0_ST` writer - Represents ADC_evt_eq_below_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_EQ_BELOW_THRESH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH1_ST` reader - Represents ADC_evt_eq_below_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_EQ_BELOW_THRESH1_ST_R = crate::BitReader; +#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH1_ST` writer - Represents ADC_evt_eq_below_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_EQ_BELOW_THRESH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_RESULT_DONE0_ST` reader - Represents ADC_evt_result_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_RESULT_DONE0_ST_R = crate::BitReader; +#[doc = "Field `ADC_EVT_RESULT_DONE0_ST` writer - Represents ADC_evt_result_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_RESULT_DONE0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_STOPPED0_ST` reader - Represents ADC_evt_stopped0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_STOPPED0_ST_R = crate::BitReader; +#[doc = "Field `ADC_EVT_STOPPED0_ST` writer - Represents ADC_evt_stopped0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_STOPPED0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_STARTED0_ST` reader - Represents ADC_evt_started0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_STARTED0_ST_R = crate::BitReader; +#[doc = "Field `ADC_EVT_STARTED0_ST` writer - Represents ADC_evt_started0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_EVT_STARTED0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_DONE0_ST` reader - Represents REGDMA_evt_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_DONE0_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_EVT_DONE0_ST` writer - Represents REGDMA_evt_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_DONE0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_DONE1_ST` reader - Represents REGDMA_evt_done1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_DONE1_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_EVT_DONE1_ST` writer - Represents REGDMA_evt_done1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_DONE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_DONE2_ST` reader - Represents REGDMA_evt_done2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_DONE2_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_EVT_DONE2_ST` writer - Represents REGDMA_evt_done2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_DONE2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_DONE3_ST` reader - Represents REGDMA_evt_done3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_DONE3_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_EVT_DONE3_ST` writer - Represents REGDMA_evt_done3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_DONE3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_ERR0_ST` reader - Represents REGDMA_evt_err0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_ERR0_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_EVT_ERR0_ST` writer - Represents REGDMA_evt_err0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_ERR0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_ERR1_ST` reader - Represents REGDMA_evt_err1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_ERR1_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_EVT_ERR1_ST` writer - Represents REGDMA_evt_err1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_ERR1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_ERR2_ST` reader - Represents REGDMA_evt_err2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_ERR2_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_EVT_ERR2_ST` writer - Represents REGDMA_evt_err2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_ERR2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_ERR3_ST` reader - Represents REGDMA_evt_err3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_ERR3_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_EVT_ERR3_ST` writer - Represents REGDMA_evt_err3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_EVT_ERR3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMPSNSR_EVT_OVER_LIMIT_ST` reader - Represents TMPSNSR_evt_over_limit trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TMPSNSR_EVT_OVER_LIMIT_ST_R = crate::BitReader; +#[doc = "Field `TMPSNSR_EVT_OVER_LIMIT_ST` writer - Represents TMPSNSR_evt_over_limit trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TMPSNSR_EVT_OVER_LIMIT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_EVT_RX_DONE_ST` reader - Represents I2S0_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_EVT_RX_DONE_ST_R = crate::BitReader; +#[doc = "Field `I2S0_EVT_RX_DONE_ST` writer - Represents I2S0_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_EVT_RX_DONE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_EVT_TX_DONE_ST` reader - Represents I2S0_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_EVT_TX_DONE_ST_R = crate::BitReader; +#[doc = "Field `I2S0_EVT_TX_DONE_ST` writer - Represents I2S0_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_EVT_TX_DONE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_EVT_X_WORDS_RECEIVED_ST` reader - Represents I2S0_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_EVT_X_WORDS_RECEIVED_ST_R = crate::BitReader; +#[doc = "Field `I2S0_EVT_X_WORDS_RECEIVED_ST` writer - Represents I2S0_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_EVT_X_WORDS_RECEIVED_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_EVT_X_WORDS_SENT_ST` reader - Represents I2S0_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_EVT_X_WORDS_SENT_ST_R = crate::BitReader; +#[doc = "Field `I2S0_EVT_X_WORDS_SENT_ST` writer - Represents I2S0_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_EVT_X_WORDS_SENT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_EVT_RX_DONE_ST` reader - Represents I2S1_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_EVT_RX_DONE_ST_R = crate::BitReader; +#[doc = "Field `I2S1_EVT_RX_DONE_ST` writer - Represents I2S1_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_EVT_RX_DONE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_EVT_TX_DONE_ST` reader - Represents I2S1_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_EVT_TX_DONE_ST_R = crate::BitReader; +#[doc = "Field `I2S1_EVT_TX_DONE_ST` writer - Represents I2S1_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_EVT_TX_DONE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_EVT_X_WORDS_RECEIVED_ST` reader - Represents I2S1_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_EVT_X_WORDS_RECEIVED_ST_R = crate::BitReader; +#[doc = "Field `I2S1_EVT_X_WORDS_RECEIVED_ST` writer - Represents I2S1_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_EVT_X_WORDS_RECEIVED_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_EVT_X_WORDS_SENT_ST` reader - Represents I2S1_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_EVT_X_WORDS_SENT_ST_R = crate::BitReader; +#[doc = "Field `I2S1_EVT_X_WORDS_SENT_ST` writer - Represents I2S1_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_EVT_X_WORDS_SENT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_EVT_RX_DONE_ST` reader - Represents I2S2_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_EVT_RX_DONE_ST_R = crate::BitReader; +#[doc = "Field `I2S2_EVT_RX_DONE_ST` writer - Represents I2S2_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_EVT_RX_DONE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_EVT_TX_DONE_ST` reader - Represents I2S2_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_EVT_TX_DONE_ST_R = crate::BitReader; +#[doc = "Field `I2S2_EVT_TX_DONE_ST` writer - Represents I2S2_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_EVT_TX_DONE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_EVT_X_WORDS_RECEIVED_ST` reader - Represents I2S2_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_EVT_X_WORDS_RECEIVED_ST_R = crate::BitReader; +#[doc = "Field `I2S2_EVT_X_WORDS_RECEIVED_ST` writer - Represents I2S2_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_EVT_X_WORDS_RECEIVED_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_EVT_X_WORDS_SENT_ST` reader - Represents I2S2_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_EVT_X_WORDS_SENT_ST_R = crate::BitReader; +#[doc = "Field `I2S2_EVT_X_WORDS_SENT_ST` writer - Represents I2S2_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_EVT_X_WORDS_SENT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents MCPWM1_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op0_tee2_st(&self) -> MCPWM1_EVT_OP0_TEE2_ST_R { + MCPWM1_EVT_OP0_TEE2_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents MCPWM1_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op1_tee2_st(&self) -> MCPWM1_EVT_OP1_TEE2_ST_R { + MCPWM1_EVT_OP1_TEE2_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents MCPWM1_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_evt_op2_tee2_st(&self) -> MCPWM1_EVT_OP2_TEE2_ST_R { + MCPWM1_EVT_OP2_TEE2_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents ADC_evt_conv_cmplt0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_evt_conv_cmplt0_st(&self) -> ADC_EVT_CONV_CMPLT0_ST_R { + ADC_EVT_CONV_CMPLT0_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents ADC_evt_eq_above_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_evt_eq_above_thresh0_st(&self) -> ADC_EVT_EQ_ABOVE_THRESH0_ST_R { + ADC_EVT_EQ_ABOVE_THRESH0_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents ADC_evt_eq_above_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_evt_eq_above_thresh1_st(&self) -> ADC_EVT_EQ_ABOVE_THRESH1_ST_R { + ADC_EVT_EQ_ABOVE_THRESH1_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents ADC_evt_eq_below_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_evt_eq_below_thresh0_st(&self) -> ADC_EVT_EQ_BELOW_THRESH0_ST_R { + ADC_EVT_EQ_BELOW_THRESH0_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents ADC_evt_eq_below_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_evt_eq_below_thresh1_st(&self) -> ADC_EVT_EQ_BELOW_THRESH1_ST_R { + ADC_EVT_EQ_BELOW_THRESH1_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents ADC_evt_result_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_evt_result_done0_st(&self) -> ADC_EVT_RESULT_DONE0_ST_R { + ADC_EVT_RESULT_DONE0_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents ADC_evt_stopped0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_evt_stopped0_st(&self) -> ADC_EVT_STOPPED0_ST_R { + ADC_EVT_STOPPED0_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents ADC_evt_started0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_evt_started0_st(&self) -> ADC_EVT_STARTED0_ST_R { + ADC_EVT_STARTED0_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents REGDMA_evt_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_evt_done0_st(&self) -> REGDMA_EVT_DONE0_ST_R { + REGDMA_EVT_DONE0_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents REGDMA_evt_done1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_evt_done1_st(&self) -> REGDMA_EVT_DONE1_ST_R { + REGDMA_EVT_DONE1_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents REGDMA_evt_done2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_evt_done2_st(&self) -> REGDMA_EVT_DONE2_ST_R { + REGDMA_EVT_DONE2_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents REGDMA_evt_done3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_evt_done3_st(&self) -> REGDMA_EVT_DONE3_ST_R { + REGDMA_EVT_DONE3_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents REGDMA_evt_err0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_evt_err0_st(&self) -> REGDMA_EVT_ERR0_ST_R { + REGDMA_EVT_ERR0_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents REGDMA_evt_err1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_evt_err1_st(&self) -> REGDMA_EVT_ERR1_ST_R { + REGDMA_EVT_ERR1_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents REGDMA_evt_err2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_evt_err2_st(&self) -> REGDMA_EVT_ERR2_ST_R { + REGDMA_EVT_ERR2_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents REGDMA_evt_err3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_evt_err3_st(&self) -> REGDMA_EVT_ERR3_ST_R { + REGDMA_EVT_ERR3_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents TMPSNSR_evt_over_limit trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tmpsnsr_evt_over_limit_st(&self) -> TMPSNSR_EVT_OVER_LIMIT_ST_R { + TMPSNSR_EVT_OVER_LIMIT_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents I2S0_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s0_evt_rx_done_st(&self) -> I2S0_EVT_RX_DONE_ST_R { + I2S0_EVT_RX_DONE_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents I2S0_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s0_evt_tx_done_st(&self) -> I2S0_EVT_TX_DONE_ST_R { + I2S0_EVT_TX_DONE_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents I2S0_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s0_evt_x_words_received_st(&self) -> I2S0_EVT_X_WORDS_RECEIVED_ST_R { + I2S0_EVT_X_WORDS_RECEIVED_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents I2S0_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s0_evt_x_words_sent_st(&self) -> I2S0_EVT_X_WORDS_SENT_ST_R { + I2S0_EVT_X_WORDS_SENT_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents I2S1_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s1_evt_rx_done_st(&self) -> I2S1_EVT_RX_DONE_ST_R { + I2S1_EVT_RX_DONE_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents I2S1_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s1_evt_tx_done_st(&self) -> I2S1_EVT_TX_DONE_ST_R { + I2S1_EVT_TX_DONE_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents I2S1_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s1_evt_x_words_received_st(&self) -> I2S1_EVT_X_WORDS_RECEIVED_ST_R { + I2S1_EVT_X_WORDS_RECEIVED_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents I2S1_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s1_evt_x_words_sent_st(&self) -> I2S1_EVT_X_WORDS_SENT_ST_R { + I2S1_EVT_X_WORDS_SENT_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents I2S2_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s2_evt_rx_done_st(&self) -> I2S2_EVT_RX_DONE_ST_R { + I2S2_EVT_RX_DONE_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents I2S2_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s2_evt_tx_done_st(&self) -> I2S2_EVT_TX_DONE_ST_R { + I2S2_EVT_TX_DONE_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents I2S2_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s2_evt_x_words_received_st(&self) -> I2S2_EVT_X_WORDS_RECEIVED_ST_R { + I2S2_EVT_X_WORDS_RECEIVED_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents I2S2_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s2_evt_x_words_sent_st(&self) -> I2S2_EVT_X_WORDS_SENT_ST_R { + I2S2_EVT_X_WORDS_SENT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_ST4") + .field( + "mcpwm1_evt_op0_tee2_st", + &format_args!("{}", self.mcpwm1_evt_op0_tee2_st().bit()), + ) + .field( + "mcpwm1_evt_op1_tee2_st", + &format_args!("{}", self.mcpwm1_evt_op1_tee2_st().bit()), + ) + .field( + "mcpwm1_evt_op2_tee2_st", + &format_args!("{}", self.mcpwm1_evt_op2_tee2_st().bit()), + ) + .field( + "adc_evt_conv_cmplt0_st", + &format_args!("{}", self.adc_evt_conv_cmplt0_st().bit()), + ) + .field( + "adc_evt_eq_above_thresh0_st", + &format_args!("{}", self.adc_evt_eq_above_thresh0_st().bit()), + ) + .field( + "adc_evt_eq_above_thresh1_st", + &format_args!("{}", self.adc_evt_eq_above_thresh1_st().bit()), + ) + .field( + "adc_evt_eq_below_thresh0_st", + &format_args!("{}", self.adc_evt_eq_below_thresh0_st().bit()), + ) + .field( + "adc_evt_eq_below_thresh1_st", + &format_args!("{}", self.adc_evt_eq_below_thresh1_st().bit()), + ) + .field( + "adc_evt_result_done0_st", + &format_args!("{}", self.adc_evt_result_done0_st().bit()), + ) + .field( + "adc_evt_stopped0_st", + &format_args!("{}", self.adc_evt_stopped0_st().bit()), + ) + .field( + "adc_evt_started0_st", + &format_args!("{}", self.adc_evt_started0_st().bit()), + ) + .field( + "regdma_evt_done0_st", + &format_args!("{}", self.regdma_evt_done0_st().bit()), + ) + .field( + "regdma_evt_done1_st", + &format_args!("{}", self.regdma_evt_done1_st().bit()), + ) + .field( + "regdma_evt_done2_st", + &format_args!("{}", self.regdma_evt_done2_st().bit()), + ) + .field( + "regdma_evt_done3_st", + &format_args!("{}", self.regdma_evt_done3_st().bit()), + ) + .field( + "regdma_evt_err0_st", + &format_args!("{}", self.regdma_evt_err0_st().bit()), + ) + .field( + "regdma_evt_err1_st", + &format_args!("{}", self.regdma_evt_err1_st().bit()), + ) + .field( + "regdma_evt_err2_st", + &format_args!("{}", self.regdma_evt_err2_st().bit()), + ) + .field( + "regdma_evt_err3_st", + &format_args!("{}", self.regdma_evt_err3_st().bit()), + ) + .field( + "tmpsnsr_evt_over_limit_st", + &format_args!("{}", self.tmpsnsr_evt_over_limit_st().bit()), + ) + .field( + "i2s0_evt_rx_done_st", + &format_args!("{}", self.i2s0_evt_rx_done_st().bit()), + ) + .field( + "i2s0_evt_tx_done_st", + &format_args!("{}", self.i2s0_evt_tx_done_st().bit()), + ) + .field( + "i2s0_evt_x_words_received_st", + &format_args!("{}", self.i2s0_evt_x_words_received_st().bit()), + ) + .field( + "i2s0_evt_x_words_sent_st", + &format_args!("{}", self.i2s0_evt_x_words_sent_st().bit()), + ) + .field( + "i2s1_evt_rx_done_st", + &format_args!("{}", self.i2s1_evt_rx_done_st().bit()), + ) + .field( + "i2s1_evt_tx_done_st", + &format_args!("{}", self.i2s1_evt_tx_done_st().bit()), + ) + .field( + "i2s1_evt_x_words_received_st", + &format_args!("{}", self.i2s1_evt_x_words_received_st().bit()), + ) + .field( + "i2s1_evt_x_words_sent_st", + &format_args!("{}", self.i2s1_evt_x_words_sent_st().bit()), + ) + .field( + "i2s2_evt_rx_done_st", + &format_args!("{}", self.i2s2_evt_rx_done_st().bit()), + ) + .field( + "i2s2_evt_tx_done_st", + &format_args!("{}", self.i2s2_evt_tx_done_st().bit()), + ) + .field( + "i2s2_evt_x_words_received_st", + &format_args!("{}", self.i2s2_evt_x_words_received_st().bit()), + ) + .field( + "i2s2_evt_x_words_sent_st", + &format_args!("{}", self.i2s2_evt_x_words_sent_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents MCPWM1_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op0_tee2_st(&mut self) -> MCPWM1_EVT_OP0_TEE2_ST_W { + MCPWM1_EVT_OP0_TEE2_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents MCPWM1_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op1_tee2_st(&mut self) -> MCPWM1_EVT_OP1_TEE2_ST_W { + MCPWM1_EVT_OP1_TEE2_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents MCPWM1_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op2_tee2_st(&mut self) -> MCPWM1_EVT_OP2_TEE2_ST_W { + MCPWM1_EVT_OP2_TEE2_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents ADC_evt_conv_cmplt0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_evt_conv_cmplt0_st(&mut self) -> ADC_EVT_CONV_CMPLT0_ST_W { + ADC_EVT_CONV_CMPLT0_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents ADC_evt_eq_above_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_evt_eq_above_thresh0_st(&mut self) -> ADC_EVT_EQ_ABOVE_THRESH0_ST_W { + ADC_EVT_EQ_ABOVE_THRESH0_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents ADC_evt_eq_above_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_evt_eq_above_thresh1_st(&mut self) -> ADC_EVT_EQ_ABOVE_THRESH1_ST_W { + ADC_EVT_EQ_ABOVE_THRESH1_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents ADC_evt_eq_below_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_evt_eq_below_thresh0_st(&mut self) -> ADC_EVT_EQ_BELOW_THRESH0_ST_W { + ADC_EVT_EQ_BELOW_THRESH0_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents ADC_evt_eq_below_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_evt_eq_below_thresh1_st(&mut self) -> ADC_EVT_EQ_BELOW_THRESH1_ST_W { + ADC_EVT_EQ_BELOW_THRESH1_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents ADC_evt_result_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_evt_result_done0_st(&mut self) -> ADC_EVT_RESULT_DONE0_ST_W { + ADC_EVT_RESULT_DONE0_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents ADC_evt_stopped0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_evt_stopped0_st(&mut self) -> ADC_EVT_STOPPED0_ST_W { + ADC_EVT_STOPPED0_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents ADC_evt_started0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_evt_started0_st(&mut self) -> ADC_EVT_STARTED0_ST_W { + ADC_EVT_STARTED0_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents REGDMA_evt_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_done0_st(&mut self) -> REGDMA_EVT_DONE0_ST_W { + REGDMA_EVT_DONE0_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents REGDMA_evt_done1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_done1_st(&mut self) -> REGDMA_EVT_DONE1_ST_W { + REGDMA_EVT_DONE1_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents REGDMA_evt_done2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_done2_st(&mut self) -> REGDMA_EVT_DONE2_ST_W { + REGDMA_EVT_DONE2_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents REGDMA_evt_done3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_done3_st(&mut self) -> REGDMA_EVT_DONE3_ST_W { + REGDMA_EVT_DONE3_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents REGDMA_evt_err0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_err0_st(&mut self) -> REGDMA_EVT_ERR0_ST_W { + REGDMA_EVT_ERR0_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents REGDMA_evt_err1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_err1_st(&mut self) -> REGDMA_EVT_ERR1_ST_W { + REGDMA_EVT_ERR1_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents REGDMA_evt_err2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_err2_st(&mut self) -> REGDMA_EVT_ERR2_ST_W { + REGDMA_EVT_ERR2_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents REGDMA_evt_err3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_err3_st(&mut self) -> REGDMA_EVT_ERR3_ST_W { + REGDMA_EVT_ERR3_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents TMPSNSR_evt_over_limit trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tmpsnsr_evt_over_limit_st(&mut self) -> TMPSNSR_EVT_OVER_LIMIT_ST_W { + TMPSNSR_EVT_OVER_LIMIT_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents I2S0_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s0_evt_rx_done_st(&mut self) -> I2S0_EVT_RX_DONE_ST_W { + I2S0_EVT_RX_DONE_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents I2S0_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s0_evt_tx_done_st(&mut self) -> I2S0_EVT_TX_DONE_ST_W { + I2S0_EVT_TX_DONE_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents I2S0_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s0_evt_x_words_received_st(&mut self) -> I2S0_EVT_X_WORDS_RECEIVED_ST_W { + I2S0_EVT_X_WORDS_RECEIVED_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents I2S0_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s0_evt_x_words_sent_st(&mut self) -> I2S0_EVT_X_WORDS_SENT_ST_W { + I2S0_EVT_X_WORDS_SENT_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents I2S1_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s1_evt_rx_done_st(&mut self) -> I2S1_EVT_RX_DONE_ST_W { + I2S1_EVT_RX_DONE_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents I2S1_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s1_evt_tx_done_st(&mut self) -> I2S1_EVT_TX_DONE_ST_W { + I2S1_EVT_TX_DONE_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents I2S1_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s1_evt_x_words_received_st(&mut self) -> I2S1_EVT_X_WORDS_RECEIVED_ST_W { + I2S1_EVT_X_WORDS_RECEIVED_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents I2S1_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s1_evt_x_words_sent_st(&mut self) -> I2S1_EVT_X_WORDS_SENT_ST_W { + I2S1_EVT_X_WORDS_SENT_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents I2S2_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s2_evt_rx_done_st(&mut self) -> I2S2_EVT_RX_DONE_ST_W { + I2S2_EVT_RX_DONE_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents I2S2_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s2_evt_tx_done_st(&mut self) -> I2S2_EVT_TX_DONE_ST_W { + I2S2_EVT_TX_DONE_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents I2S2_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s2_evt_x_words_received_st(&mut self) -> I2S2_EVT_X_WORDS_RECEIVED_ST_W { + I2S2_EVT_X_WORDS_RECEIVED_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents I2S2_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s2_evt_x_words_sent_st(&mut self) -> I2S2_EVT_X_WORDS_SENT_ST_W { + I2S2_EVT_X_WORDS_SENT_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST4_SPEC; +impl crate::RegisterSpec for EVT_ST4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_st4::R`](R) reader structure"] +impl crate::Readable for EVT_ST4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_st4::W`](W) writer structure"] +impl crate::Writable for EVT_ST4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST4 to value 0"] +impl crate::Resettable for EVT_ST4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st4_clr.rs b/esp32p4/src/soc_etm/evt_st4_clr.rs new file mode 100644 index 0000000000..38b4044676 --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st4_clr.rs @@ -0,0 +1,314 @@ +#[doc = "Register `EVT_ST4_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `MCPWM1_EVT_OP0_TEE2_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP0_TEE2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP1_TEE2_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP1_TEE2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_EVT_OP2_TEE2_ST_CLR` writer - Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_EVT_OP2_TEE2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_CONV_CMPLT0_ST_CLR` writer - Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_EVT_CONV_CMPLT0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR` writer - Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR` writer - Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH0_ST_CLR` writer - Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_EQ_BELOW_THRESH1_ST_CLR` writer - Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_RESULT_DONE0_ST_CLR` writer - Configures whether or not to clear ADC_evt_result_done0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_EVT_RESULT_DONE0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_STOPPED0_ST_CLR` writer - Configures whether or not to clear ADC_evt_stopped0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_EVT_STOPPED0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_EVT_STARTED0_ST_CLR` writer - Configures whether or not to clear ADC_evt_started0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_EVT_STARTED0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_DONE0_ST_CLR` writer - Configures whether or not to clear REGDMA_evt_done0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_EVT_DONE0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_DONE1_ST_CLR` writer - Configures whether or not to clear REGDMA_evt_done1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_EVT_DONE1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_DONE2_ST_CLR` writer - Configures whether or not to clear REGDMA_evt_done2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_EVT_DONE2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_DONE3_ST_CLR` writer - Configures whether or not to clear REGDMA_evt_done3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_EVT_DONE3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_ERR0_ST_CLR` writer - Configures whether or not to clear REGDMA_evt_err0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_EVT_ERR0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_ERR1_ST_CLR` writer - Configures whether or not to clear REGDMA_evt_err1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_EVT_ERR1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_ERR2_ST_CLR` writer - Configures whether or not to clear REGDMA_evt_err2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_EVT_ERR2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_EVT_ERR3_ST_CLR` writer - Configures whether or not to clear REGDMA_evt_err3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_EVT_ERR3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMPSNSR_EVT_OVER_LIMIT_ST_CLR` writer - Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TMPSNSR_EVT_OVER_LIMIT_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_EVT_RX_DONE_ST_CLR` writer - Configures whether or not to clear I2S0_evt_rx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S0_EVT_RX_DONE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_EVT_TX_DONE_ST_CLR` writer - Configures whether or not to clear I2S0_evt_tx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S0_EVT_TX_DONE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_EVT_X_WORDS_RECEIVED_ST_CLR` writer - Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_EVT_X_WORDS_SENT_ST_CLR` writer - Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S0_EVT_X_WORDS_SENT_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_EVT_RX_DONE_ST_CLR` writer - Configures whether or not to clear I2S1_evt_rx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S1_EVT_RX_DONE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_EVT_TX_DONE_ST_CLR` writer - Configures whether or not to clear I2S1_evt_tx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S1_EVT_TX_DONE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_EVT_X_WORDS_RECEIVED_ST_CLR` writer - Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_EVT_X_WORDS_SENT_ST_CLR` writer - Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S1_EVT_X_WORDS_SENT_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_EVT_RX_DONE_ST_CLR` writer - Configures whether or not to clear I2S2_evt_rx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S2_EVT_RX_DONE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_EVT_TX_DONE_ST_CLR` writer - Configures whether or not to clear I2S2_evt_tx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S2_EVT_TX_DONE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_EVT_X_WORDS_RECEIVED_ST_CLR` writer - Configures whether or not to clear I2S2_evt_x_words_received trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_EVT_X_WORDS_SENT_ST_CLR` writer - Configures whether or not to clear I2S2_evt_x_words_sent trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S2_EVT_X_WORDS_SENT_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op0_tee2_st_clr(&mut self) -> MCPWM1_EVT_OP0_TEE2_ST_CLR_W { + MCPWM1_EVT_OP0_TEE2_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op1_tee2_st_clr(&mut self) -> MCPWM1_EVT_OP1_TEE2_ST_CLR_W { + MCPWM1_EVT_OP1_TEE2_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_evt_op2_tee2_st_clr(&mut self) -> MCPWM1_EVT_OP2_TEE2_ST_CLR_W { + MCPWM1_EVT_OP2_TEE2_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_evt_conv_cmplt0_st_clr(&mut self) -> ADC_EVT_CONV_CMPLT0_ST_CLR_W { + ADC_EVT_CONV_CMPLT0_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_evt_eq_above_thresh0_st_clr( + &mut self, + ) -> ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_W { + ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_evt_eq_above_thresh1_st_clr( + &mut self, + ) -> ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_W { + ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_evt_eq_below_thresh0_st_clr( + &mut self, + ) -> ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_W { + ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_evt_eq_below_thresh1_st_clr( + &mut self, + ) -> ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_W { + ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear ADC_evt_result_done0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_evt_result_done0_st_clr( + &mut self, + ) -> ADC_EVT_RESULT_DONE0_ST_CLR_W { + ADC_EVT_RESULT_DONE0_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear ADC_evt_stopped0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_evt_stopped0_st_clr(&mut self) -> ADC_EVT_STOPPED0_ST_CLR_W { + ADC_EVT_STOPPED0_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear ADC_evt_started0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_evt_started0_st_clr(&mut self) -> ADC_EVT_STARTED0_ST_CLR_W { + ADC_EVT_STARTED0_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear REGDMA_evt_done0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_done0_st_clr(&mut self) -> REGDMA_EVT_DONE0_ST_CLR_W { + REGDMA_EVT_DONE0_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear REGDMA_evt_done1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_done1_st_clr(&mut self) -> REGDMA_EVT_DONE1_ST_CLR_W { + REGDMA_EVT_DONE1_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear REGDMA_evt_done2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_done2_st_clr(&mut self) -> REGDMA_EVT_DONE2_ST_CLR_W { + REGDMA_EVT_DONE2_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear REGDMA_evt_done3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_done3_st_clr(&mut self) -> REGDMA_EVT_DONE3_ST_CLR_W { + REGDMA_EVT_DONE3_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear REGDMA_evt_err0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_err0_st_clr(&mut self) -> REGDMA_EVT_ERR0_ST_CLR_W { + REGDMA_EVT_ERR0_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear REGDMA_evt_err1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_err1_st_clr(&mut self) -> REGDMA_EVT_ERR1_ST_CLR_W { + REGDMA_EVT_ERR1_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear REGDMA_evt_err2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_err2_st_clr(&mut self) -> REGDMA_EVT_ERR2_ST_CLR_W { + REGDMA_EVT_ERR2_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear REGDMA_evt_err3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_evt_err3_st_clr(&mut self) -> REGDMA_EVT_ERR3_ST_CLR_W { + REGDMA_EVT_ERR3_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tmpsnsr_evt_over_limit_st_clr( + &mut self, + ) -> TMPSNSR_EVT_OVER_LIMIT_ST_CLR_W { + TMPSNSR_EVT_OVER_LIMIT_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear I2S0_evt_rx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s0_evt_rx_done_st_clr(&mut self) -> I2S0_EVT_RX_DONE_ST_CLR_W { + I2S0_EVT_RX_DONE_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear I2S0_evt_tx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s0_evt_tx_done_st_clr(&mut self) -> I2S0_EVT_TX_DONE_ST_CLR_W { + I2S0_EVT_TX_DONE_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s0_evt_x_words_received_st_clr( + &mut self, + ) -> I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_W { + I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s0_evt_x_words_sent_st_clr( + &mut self, + ) -> I2S0_EVT_X_WORDS_SENT_ST_CLR_W { + I2S0_EVT_X_WORDS_SENT_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear I2S1_evt_rx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s1_evt_rx_done_st_clr(&mut self) -> I2S1_EVT_RX_DONE_ST_CLR_W { + I2S1_EVT_RX_DONE_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear I2S1_evt_tx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s1_evt_tx_done_st_clr(&mut self) -> I2S1_EVT_TX_DONE_ST_CLR_W { + I2S1_EVT_TX_DONE_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s1_evt_x_words_received_st_clr( + &mut self, + ) -> I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_W { + I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s1_evt_x_words_sent_st_clr( + &mut self, + ) -> I2S1_EVT_X_WORDS_SENT_ST_CLR_W { + I2S1_EVT_X_WORDS_SENT_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear I2S2_evt_rx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s2_evt_rx_done_st_clr(&mut self) -> I2S2_EVT_RX_DONE_ST_CLR_W { + I2S2_EVT_RX_DONE_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear I2S2_evt_tx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s2_evt_tx_done_st_clr(&mut self) -> I2S2_EVT_TX_DONE_ST_CLR_W { + I2S2_EVT_TX_DONE_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear I2S2_evt_x_words_received trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s2_evt_x_words_received_st_clr( + &mut self, + ) -> I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_W { + I2S2_EVT_X_WORDS_RECEIVED_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear I2S2_evt_x_words_sent trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s2_evt_x_words_sent_st_clr( + &mut self, + ) -> I2S2_EVT_X_WORDS_SENT_ST_CLR_W { + I2S2_EVT_X_WORDS_SENT_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st4_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST4_CLR_SPEC; +impl crate::RegisterSpec for EVT_ST4_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`evt_st4_clr::W`](W) writer structure"] +impl crate::Writable for EVT_ST4_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST4_CLR to value 0"] +impl crate::Resettable for EVT_ST4_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st5.rs b/esp32p4/src/soc_etm/evt_st5.rs new file mode 100644 index 0000000000..e9d68a3c3b --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st5.rs @@ -0,0 +1,689 @@ +#[doc = "Register `EVT_ST5` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_ST5` writer"] +pub type W = crate::W; +#[doc = "Field `ULP_EVT_ERR_INTR_ST` reader - Represents ULP_evt_err_intr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ULP_EVT_ERR_INTR_ST_R = crate::BitReader; +#[doc = "Field `ULP_EVT_ERR_INTR_ST` writer - Represents ULP_evt_err_intr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ULP_EVT_ERR_INTR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ULP_EVT_HALT_ST` reader - Represents ULP_evt_halt trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ULP_EVT_HALT_ST_R = crate::BitReader; +#[doc = "Field `ULP_EVT_HALT_ST` writer - Represents ULP_evt_halt trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ULP_EVT_HALT_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ULP_EVT_START_INTR_ST` reader - Represents ULP_evt_start_intr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ULP_EVT_START_INTR_ST_R = crate::BitReader; +#[doc = "Field `ULP_EVT_START_INTR_ST` writer - Represents ULP_evt_start_intr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ULP_EVT_START_INTR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_EVT_TICK_ST` reader - Represents RTC_evt_tick trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_EVT_TICK_ST_R = crate::BitReader; +#[doc = "Field `RTC_EVT_TICK_ST` writer - Represents RTC_evt_tick trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_EVT_TICK_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_EVT_OVF_ST` reader - Represents RTC_evt_ovf trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_EVT_OVF_ST_R = crate::BitReader; +#[doc = "Field `RTC_EVT_OVF_ST` writer - Represents RTC_evt_ovf trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_EVT_OVF_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_EVT_CMP_ST` reader - Represents RTC_evt_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_EVT_CMP_ST_R = crate::BitReader; +#[doc = "Field `RTC_EVT_CMP_ST` writer - Represents RTC_evt_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_EVT_CMP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH0_ST` reader - Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_DONE_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH0_ST` writer - Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_DONE_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH1_ST` reader - Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_DONE_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH1_ST` writer - Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_DONE_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH2_ST` reader - Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_DONE_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH2_ST` writer - Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_DONE_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST` reader - Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST` writer - Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST` reader - Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST` writer - Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST` reader - Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST` writer - Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST` reader - Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST` writer - Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST` reader - Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST` writer - Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST` reader - Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST` writer - Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST` reader - Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST` writer - Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST` reader - Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST` writer - Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST` reader - Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST` writer - Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH0_ST` reader - Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_DONE_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH0_ST` writer - Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_DONE_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH1_ST` reader - Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_DONE_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH1_ST` writer - Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_DONE_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH2_ST` reader - Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_DONE_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH2_ST` writer - Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_DONE_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH0_ST` reader - Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_EOF_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH0_ST` writer - Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_EOF_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH1_ST` reader - Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_EOF_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH1_ST` writer - Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_EOF_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH2_ST` reader - Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_EOF_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH2_ST` writer - Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_EOF_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST` reader - Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST` writer - Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST` reader - Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST` writer - Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST` reader - Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST` writer - Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST` reader - Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST` writer - Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST` reader - Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST` writer - Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST` reader - Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST` writer - Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST` reader - Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST` writer - Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST` reader - Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST` writer - Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents ULP_evt_err_intr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ulp_evt_err_intr_st(&self) -> ULP_EVT_ERR_INTR_ST_R { + ULP_EVT_ERR_INTR_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents ULP_evt_halt trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ulp_evt_halt_st(&self) -> ULP_EVT_HALT_ST_R { + ULP_EVT_HALT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents ULP_evt_start_intr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ulp_evt_start_intr_st(&self) -> ULP_EVT_START_INTR_ST_R { + ULP_EVT_START_INTR_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents RTC_evt_tick trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn rtc_evt_tick_st(&self) -> RTC_EVT_TICK_ST_R { + RTC_EVT_TICK_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents RTC_evt_ovf trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn rtc_evt_ovf_st(&self) -> RTC_EVT_OVF_ST_R { + RTC_EVT_OVF_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents RTC_evt_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn rtc_evt_cmp_st(&self) -> RTC_EVT_CMP_ST_R { + RTC_EVT_CMP_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_done_ch0_st(&self) -> PDMA_AHB_EVT_IN_DONE_CH0_ST_R { + PDMA_AHB_EVT_IN_DONE_CH0_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_done_ch1_st(&self) -> PDMA_AHB_EVT_IN_DONE_CH1_ST_R { + PDMA_AHB_EVT_IN_DONE_CH1_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_done_ch2_st(&self) -> PDMA_AHB_EVT_IN_DONE_CH2_ST_R { + PDMA_AHB_EVT_IN_DONE_CH2_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_suc_eof_ch0_st(&self) -> PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_R { + PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_suc_eof_ch1_st(&self) -> PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_R { + PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_suc_eof_ch2_st(&self) -> PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_R { + PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_fifo_empty_ch0_st(&self) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_R { + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_fifo_empty_ch1_st(&self) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_R { + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_fifo_empty_ch2_st(&self) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_R { + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_fifo_full_ch0_st(&self) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_R { + PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_fifo_full_ch1_st(&self) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_R { + PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_in_fifo_full_ch2_st(&self) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_R { + PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_done_ch0_st(&self) -> PDMA_AHB_EVT_OUT_DONE_CH0_ST_R { + PDMA_AHB_EVT_OUT_DONE_CH0_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_done_ch1_st(&self) -> PDMA_AHB_EVT_OUT_DONE_CH1_ST_R { + PDMA_AHB_EVT_OUT_DONE_CH1_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_done_ch2_st(&self) -> PDMA_AHB_EVT_OUT_DONE_CH2_ST_R { + PDMA_AHB_EVT_OUT_DONE_CH2_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_eof_ch0_st(&self) -> PDMA_AHB_EVT_OUT_EOF_CH0_ST_R { + PDMA_AHB_EVT_OUT_EOF_CH0_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_eof_ch1_st(&self) -> PDMA_AHB_EVT_OUT_EOF_CH1_ST_R { + PDMA_AHB_EVT_OUT_EOF_CH1_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_eof_ch2_st(&self) -> PDMA_AHB_EVT_OUT_EOF_CH2_ST_R { + PDMA_AHB_EVT_OUT_EOF_CH2_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_total_eof_ch0_st(&self) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_R { + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_total_eof_ch1_st(&self) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_R { + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_total_eof_ch2_st(&self) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_R { + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_fifo_empty_ch0_st(&self) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_R { + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_fifo_empty_ch1_st(&self) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_R { + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_fifo_empty_ch2_st(&self) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_R { + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_fifo_full_ch0_st(&self) -> PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_R { + PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_fifo_full_ch1_st(&self) -> PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_R { + PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_ST5") + .field( + "ulp_evt_err_intr_st", + &format_args!("{}", self.ulp_evt_err_intr_st().bit()), + ) + .field( + "ulp_evt_halt_st", + &format_args!("{}", self.ulp_evt_halt_st().bit()), + ) + .field( + "ulp_evt_start_intr_st", + &format_args!("{}", self.ulp_evt_start_intr_st().bit()), + ) + .field( + "rtc_evt_tick_st", + &format_args!("{}", self.rtc_evt_tick_st().bit()), + ) + .field( + "rtc_evt_ovf_st", + &format_args!("{}", self.rtc_evt_ovf_st().bit()), + ) + .field( + "rtc_evt_cmp_st", + &format_args!("{}", self.rtc_evt_cmp_st().bit()), + ) + .field( + "pdma_ahb_evt_in_done_ch0_st", + &format_args!("{}", self.pdma_ahb_evt_in_done_ch0_st().bit()), + ) + .field( + "pdma_ahb_evt_in_done_ch1_st", + &format_args!("{}", self.pdma_ahb_evt_in_done_ch1_st().bit()), + ) + .field( + "pdma_ahb_evt_in_done_ch2_st", + &format_args!("{}", self.pdma_ahb_evt_in_done_ch2_st().bit()), + ) + .field( + "pdma_ahb_evt_in_suc_eof_ch0_st", + &format_args!("{}", self.pdma_ahb_evt_in_suc_eof_ch0_st().bit()), + ) + .field( + "pdma_ahb_evt_in_suc_eof_ch1_st", + &format_args!("{}", self.pdma_ahb_evt_in_suc_eof_ch1_st().bit()), + ) + .field( + "pdma_ahb_evt_in_suc_eof_ch2_st", + &format_args!("{}", self.pdma_ahb_evt_in_suc_eof_ch2_st().bit()), + ) + .field( + "pdma_ahb_evt_in_fifo_empty_ch0_st", + &format_args!("{}", self.pdma_ahb_evt_in_fifo_empty_ch0_st().bit()), + ) + .field( + "pdma_ahb_evt_in_fifo_empty_ch1_st", + &format_args!("{}", self.pdma_ahb_evt_in_fifo_empty_ch1_st().bit()), + ) + .field( + "pdma_ahb_evt_in_fifo_empty_ch2_st", + &format_args!("{}", self.pdma_ahb_evt_in_fifo_empty_ch2_st().bit()), + ) + .field( + "pdma_ahb_evt_in_fifo_full_ch0_st", + &format_args!("{}", self.pdma_ahb_evt_in_fifo_full_ch0_st().bit()), + ) + .field( + "pdma_ahb_evt_in_fifo_full_ch1_st", + &format_args!("{}", self.pdma_ahb_evt_in_fifo_full_ch1_st().bit()), + ) + .field( + "pdma_ahb_evt_in_fifo_full_ch2_st", + &format_args!("{}", self.pdma_ahb_evt_in_fifo_full_ch2_st().bit()), + ) + .field( + "pdma_ahb_evt_out_done_ch0_st", + &format_args!("{}", self.pdma_ahb_evt_out_done_ch0_st().bit()), + ) + .field( + "pdma_ahb_evt_out_done_ch1_st", + &format_args!("{}", self.pdma_ahb_evt_out_done_ch1_st().bit()), + ) + .field( + "pdma_ahb_evt_out_done_ch2_st", + &format_args!("{}", self.pdma_ahb_evt_out_done_ch2_st().bit()), + ) + .field( + "pdma_ahb_evt_out_eof_ch0_st", + &format_args!("{}", self.pdma_ahb_evt_out_eof_ch0_st().bit()), + ) + .field( + "pdma_ahb_evt_out_eof_ch1_st", + &format_args!("{}", self.pdma_ahb_evt_out_eof_ch1_st().bit()), + ) + .field( + "pdma_ahb_evt_out_eof_ch2_st", + &format_args!("{}", self.pdma_ahb_evt_out_eof_ch2_st().bit()), + ) + .field( + "pdma_ahb_evt_out_total_eof_ch0_st", + &format_args!("{}", self.pdma_ahb_evt_out_total_eof_ch0_st().bit()), + ) + .field( + "pdma_ahb_evt_out_total_eof_ch1_st", + &format_args!("{}", self.pdma_ahb_evt_out_total_eof_ch1_st().bit()), + ) + .field( + "pdma_ahb_evt_out_total_eof_ch2_st", + &format_args!("{}", self.pdma_ahb_evt_out_total_eof_ch2_st().bit()), + ) + .field( + "pdma_ahb_evt_out_fifo_empty_ch0_st", + &format_args!("{}", self.pdma_ahb_evt_out_fifo_empty_ch0_st().bit()), + ) + .field( + "pdma_ahb_evt_out_fifo_empty_ch1_st", + &format_args!("{}", self.pdma_ahb_evt_out_fifo_empty_ch1_st().bit()), + ) + .field( + "pdma_ahb_evt_out_fifo_empty_ch2_st", + &format_args!("{}", self.pdma_ahb_evt_out_fifo_empty_ch2_st().bit()), + ) + .field( + "pdma_ahb_evt_out_fifo_full_ch0_st", + &format_args!("{}", self.pdma_ahb_evt_out_fifo_full_ch0_st().bit()), + ) + .field( + "pdma_ahb_evt_out_fifo_full_ch1_st", + &format_args!("{}", self.pdma_ahb_evt_out_fifo_full_ch1_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents ULP_evt_err_intr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ulp_evt_err_intr_st(&mut self) -> ULP_EVT_ERR_INTR_ST_W { + ULP_EVT_ERR_INTR_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents ULP_evt_halt trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ulp_evt_halt_st(&mut self) -> ULP_EVT_HALT_ST_W { + ULP_EVT_HALT_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents ULP_evt_start_intr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ulp_evt_start_intr_st(&mut self) -> ULP_EVT_START_INTR_ST_W { + ULP_EVT_START_INTR_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents RTC_evt_tick trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn rtc_evt_tick_st(&mut self) -> RTC_EVT_TICK_ST_W { + RTC_EVT_TICK_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents RTC_evt_ovf trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn rtc_evt_ovf_st(&mut self) -> RTC_EVT_OVF_ST_W { + RTC_EVT_OVF_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents RTC_evt_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn rtc_evt_cmp_st(&mut self) -> RTC_EVT_CMP_ST_W { + RTC_EVT_CMP_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_done_ch0_st(&mut self) -> PDMA_AHB_EVT_IN_DONE_CH0_ST_W { + PDMA_AHB_EVT_IN_DONE_CH0_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_done_ch1_st(&mut self) -> PDMA_AHB_EVT_IN_DONE_CH1_ST_W { + PDMA_AHB_EVT_IN_DONE_CH1_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_done_ch2_st(&mut self) -> PDMA_AHB_EVT_IN_DONE_CH2_ST_W { + PDMA_AHB_EVT_IN_DONE_CH2_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_suc_eof_ch0_st( + &mut self, + ) -> PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_W { + PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_suc_eof_ch1_st( + &mut self, + ) -> PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_W { + PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_suc_eof_ch2_st( + &mut self, + ) -> PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_W { + PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_empty_ch0_st( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_W { + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_empty_ch1_st( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_W { + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_empty_ch2_st( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_W { + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_full_ch0_st( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_W { + PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_full_ch1_st( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_W { + PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_full_ch2_st( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_W { + PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_done_ch0_st(&mut self) -> PDMA_AHB_EVT_OUT_DONE_CH0_ST_W { + PDMA_AHB_EVT_OUT_DONE_CH0_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_done_ch1_st(&mut self) -> PDMA_AHB_EVT_OUT_DONE_CH1_ST_W { + PDMA_AHB_EVT_OUT_DONE_CH1_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_done_ch2_st(&mut self) -> PDMA_AHB_EVT_OUT_DONE_CH2_ST_W { + PDMA_AHB_EVT_OUT_DONE_CH2_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_eof_ch0_st(&mut self) -> PDMA_AHB_EVT_OUT_EOF_CH0_ST_W { + PDMA_AHB_EVT_OUT_EOF_CH0_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_eof_ch1_st(&mut self) -> PDMA_AHB_EVT_OUT_EOF_CH1_ST_W { + PDMA_AHB_EVT_OUT_EOF_CH1_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_eof_ch2_st(&mut self) -> PDMA_AHB_EVT_OUT_EOF_CH2_ST_W { + PDMA_AHB_EVT_OUT_EOF_CH2_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_total_eof_ch0_st( + &mut self, + ) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_W { + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_total_eof_ch1_st( + &mut self, + ) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_W { + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_total_eof_ch2_st( + &mut self, + ) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_W { + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_empty_ch0_st( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_W { + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_empty_ch1_st( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_W { + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_empty_ch2_st( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_W { + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_full_ch0_st( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_W { + PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_full_ch1_st( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_W { + PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST5_SPEC; +impl crate::RegisterSpec for EVT_ST5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_st5::R`](R) reader structure"] +impl crate::Readable for EVT_ST5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_st5::W`](W) writer structure"] +impl crate::Writable for EVT_ST5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST5 to value 0"] +impl crate::Resettable for EVT_ST5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st5_clr.rs b/esp32p4/src/soc_etm/evt_st5_clr.rs new file mode 100644 index 0000000000..c5a45a8de1 --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st5_clr.rs @@ -0,0 +1,342 @@ +#[doc = "Register `EVT_ST5_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `ULP_EVT_ERR_INTR_ST_CLR` writer - Configures whether or not to clear ULP_evt_err_intr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ULP_EVT_ERR_INTR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ULP_EVT_HALT_ST_CLR` writer - Configures whether or not to clear ULP_evt_halt trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ULP_EVT_HALT_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ULP_EVT_START_INTR_ST_CLR` writer - Configures whether or not to clear ULP_evt_start_intr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ULP_EVT_START_INTR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_EVT_TICK_ST_CLR` writer - Configures whether or not to clear RTC_evt_tick trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type RTC_EVT_TICK_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_EVT_OVF_ST_CLR` writer - Configures whether or not to clear RTC_evt_ovf trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type RTC_EVT_OVF_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_EVT_CMP_ST_CLR` writer - Configures whether or not to clear RTC_evt_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type RTC_EVT_CMP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear ULP_evt_err_intr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ulp_evt_err_intr_st_clr(&mut self) -> ULP_EVT_ERR_INTR_ST_CLR_W { + ULP_EVT_ERR_INTR_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear ULP_evt_halt trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ulp_evt_halt_st_clr(&mut self) -> ULP_EVT_HALT_ST_CLR_W { + ULP_EVT_HALT_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear ULP_evt_start_intr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ulp_evt_start_intr_st_clr(&mut self) -> ULP_EVT_START_INTR_ST_CLR_W { + ULP_EVT_START_INTR_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear RTC_evt_tick trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn rtc_evt_tick_st_clr(&mut self) -> RTC_EVT_TICK_ST_CLR_W { + RTC_EVT_TICK_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear RTC_evt_ovf trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn rtc_evt_ovf_st_clr(&mut self) -> RTC_EVT_OVF_ST_CLR_W { + RTC_EVT_OVF_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear RTC_evt_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn rtc_evt_cmp_st_clr(&mut self) -> RTC_EVT_CMP_ST_CLR_W { + RTC_EVT_CMP_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_done_ch0_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_W { + PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_done_ch1_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_W { + PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_done_ch2_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_W { + PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_suc_eof_ch0_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_W { + PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_suc_eof_ch1_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_W { + PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_suc_eof_ch2_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_W { + PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_empty_ch0_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_W { + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_empty_ch1_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_W { + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_empty_ch2_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_W { + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_full_ch0_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_W { + PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_full_ch1_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_W { + PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_in_fifo_full_ch2_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_W { + PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_done_ch0_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_W { + PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_done_ch1_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_W { + PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_done_ch2_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_W { + PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_eof_ch0_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_W { + PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_eof_ch1_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_W { + PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_eof_ch2_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_W { + PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_total_eof_ch0_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W { + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_total_eof_ch1_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W { + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_total_eof_ch2_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W { + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_empty_ch0_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W { + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_empty_ch1_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W { + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_empty_ch2_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W { + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_full_ch0_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W { + PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_full_ch1_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W { + PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st5_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST5_CLR_SPEC; +impl crate::RegisterSpec for EVT_ST5_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`evt_st5_clr::W`](W) writer structure"] +impl crate::Writable for EVT_ST5_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST5_CLR to value 0"] +impl crate::Resettable for EVT_ST5_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st6.rs b/esp32p4/src/soc_etm/evt_st6.rs new file mode 100644 index 0000000000..5e49ec5680 --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st6.rs @@ -0,0 +1,693 @@ +#[doc = "Register `EVT_ST6` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_ST6` writer"] +pub type W = crate::W; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST` reader - Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST` writer - Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_DONE_CH0_ST` reader - Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_DONE_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_DONE_CH0_ST` writer - Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_DONE_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_DONE_CH1_ST` reader - Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_DONE_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_DONE_CH1_ST` writer - Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_DONE_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_DONE_CH2_ST` reader - Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_DONE_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_DONE_CH2_ST` writer - Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_DONE_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST` reader - Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST` writer - Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST` reader - Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST` writer - Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST` reader - Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST` writer - Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST` reader - Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST` writer - Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST` reader - Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST` writer - Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST` reader - Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST` writer - Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST` reader - Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST` writer - Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST` reader - Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST` writer - Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST` reader - Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST` writer - Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_DONE_CH0_ST` reader - Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_DONE_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_DONE_CH0_ST` writer - Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_DONE_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_DONE_CH1_ST` reader - Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_DONE_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_DONE_CH1_ST` writer - Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_DONE_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_DONE_CH2_ST` reader - Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_DONE_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_DONE_CH2_ST` writer - Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_DONE_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_EOF_CH0_ST` reader - Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_EOF_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_EOF_CH0_ST` writer - Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_EOF_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_EOF_CH1_ST` reader - Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_EOF_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_EOF_CH1_ST` writer - Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_EOF_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_EOF_CH2_ST` reader - Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_EOF_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_EOF_CH2_ST` writer - Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_EOF_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST` reader - Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST` writer - Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST` reader - Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST` writer - Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST` reader - Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST` writer - Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST` reader - Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST` writer - Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST` reader - Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST` writer - Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST` reader - Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST` writer - Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST` reader - Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST` writer - Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST` reader - Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST` writer - Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST` reader - Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST` writer - Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PMU_EVT_SLEEP_WEEKUP_ST` reader - Represents PMU_evt_sleep_weekup trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PMU_EVT_SLEEP_WEEKUP_ST_R = crate::BitReader; +#[doc = "Field `PMU_EVT_SLEEP_WEEKUP_ST` writer - Represents PMU_evt_sleep_weekup trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PMU_EVT_SLEEP_WEEKUP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_IN_DONE_CH0_ST` reader - Represents DMA2D_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_IN_DONE_CH0_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_IN_DONE_CH0_ST` writer - Represents DMA2D_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_IN_DONE_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_IN_DONE_CH1_ST` reader - Represents DMA2D_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_IN_DONE_CH1_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_IN_DONE_CH1_ST` writer - Represents DMA2D_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_IN_DONE_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_IN_SUC_EOF_CH0_ST` reader - Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_IN_SUC_EOF_CH0_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_IN_SUC_EOF_CH0_ST` writer - Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_IN_SUC_EOF_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_evt_out_fifo_full_ch2_st(&self) -> PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_R { + PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_done_ch0_st(&self) -> PDMA_AXI_EVT_IN_DONE_CH0_ST_R { + PDMA_AXI_EVT_IN_DONE_CH0_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_done_ch1_st(&self) -> PDMA_AXI_EVT_IN_DONE_CH1_ST_R { + PDMA_AXI_EVT_IN_DONE_CH1_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_done_ch2_st(&self) -> PDMA_AXI_EVT_IN_DONE_CH2_ST_R { + PDMA_AXI_EVT_IN_DONE_CH2_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_suc_eof_ch0_st(&self) -> PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_R { + PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_suc_eof_ch1_st(&self) -> PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_R { + PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_suc_eof_ch2_st(&self) -> PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_R { + PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_fifo_empty_ch0_st(&self) -> PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_R { + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_fifo_empty_ch1_st(&self) -> PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_R { + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_fifo_empty_ch2_st(&self) -> PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_R { + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_fifo_full_ch0_st(&self) -> PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_R { + PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_fifo_full_ch1_st(&self) -> PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_R { + PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_in_fifo_full_ch2_st(&self) -> PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_R { + PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_done_ch0_st(&self) -> PDMA_AXI_EVT_OUT_DONE_CH0_ST_R { + PDMA_AXI_EVT_OUT_DONE_CH0_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_done_ch1_st(&self) -> PDMA_AXI_EVT_OUT_DONE_CH1_ST_R { + PDMA_AXI_EVT_OUT_DONE_CH1_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_done_ch2_st(&self) -> PDMA_AXI_EVT_OUT_DONE_CH2_ST_R { + PDMA_AXI_EVT_OUT_DONE_CH2_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_eof_ch0_st(&self) -> PDMA_AXI_EVT_OUT_EOF_CH0_ST_R { + PDMA_AXI_EVT_OUT_EOF_CH0_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_eof_ch1_st(&self) -> PDMA_AXI_EVT_OUT_EOF_CH1_ST_R { + PDMA_AXI_EVT_OUT_EOF_CH1_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_eof_ch2_st(&self) -> PDMA_AXI_EVT_OUT_EOF_CH2_ST_R { + PDMA_AXI_EVT_OUT_EOF_CH2_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_total_eof_ch0_st(&self) -> PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_R { + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_total_eof_ch1_st(&self) -> PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_R { + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_total_eof_ch2_st(&self) -> PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_R { + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_fifo_empty_ch0_st(&self) -> PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_R { + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_fifo_empty_ch1_st(&self) -> PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_R { + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_fifo_empty_ch2_st(&self) -> PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_R { + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_fifo_full_ch0_st(&self) -> PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_R { + PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_fifo_full_ch1_st(&self) -> PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_R { + PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_evt_out_fifo_full_ch2_st(&self) -> PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_R { + PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents PMU_evt_sleep_weekup trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pmu_evt_sleep_weekup_st(&self) -> PMU_EVT_SLEEP_WEEKUP_ST_R { + PMU_EVT_SLEEP_WEEKUP_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents DMA2D_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_in_done_ch0_st(&self) -> DMA2D_EVT_IN_DONE_CH0_ST_R { + DMA2D_EVT_IN_DONE_CH0_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents DMA2D_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_in_done_ch1_st(&self) -> DMA2D_EVT_IN_DONE_CH1_ST_R { + DMA2D_EVT_IN_DONE_CH1_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_in_suc_eof_ch0_st(&self) -> DMA2D_EVT_IN_SUC_EOF_CH0_ST_R { + DMA2D_EVT_IN_SUC_EOF_CH0_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_ST6") + .field( + "pdma_ahb_evt_out_fifo_full_ch2_st", + &format_args!("{}", self.pdma_ahb_evt_out_fifo_full_ch2_st().bit()), + ) + .field( + "pdma_axi_evt_in_done_ch0_st", + &format_args!("{}", self.pdma_axi_evt_in_done_ch0_st().bit()), + ) + .field( + "pdma_axi_evt_in_done_ch1_st", + &format_args!("{}", self.pdma_axi_evt_in_done_ch1_st().bit()), + ) + .field( + "pdma_axi_evt_in_done_ch2_st", + &format_args!("{}", self.pdma_axi_evt_in_done_ch2_st().bit()), + ) + .field( + "pdma_axi_evt_in_suc_eof_ch0_st", + &format_args!("{}", self.pdma_axi_evt_in_suc_eof_ch0_st().bit()), + ) + .field( + "pdma_axi_evt_in_suc_eof_ch1_st", + &format_args!("{}", self.pdma_axi_evt_in_suc_eof_ch1_st().bit()), + ) + .field( + "pdma_axi_evt_in_suc_eof_ch2_st", + &format_args!("{}", self.pdma_axi_evt_in_suc_eof_ch2_st().bit()), + ) + .field( + "pdma_axi_evt_in_fifo_empty_ch0_st", + &format_args!("{}", self.pdma_axi_evt_in_fifo_empty_ch0_st().bit()), + ) + .field( + "pdma_axi_evt_in_fifo_empty_ch1_st", + &format_args!("{}", self.pdma_axi_evt_in_fifo_empty_ch1_st().bit()), + ) + .field( + "pdma_axi_evt_in_fifo_empty_ch2_st", + &format_args!("{}", self.pdma_axi_evt_in_fifo_empty_ch2_st().bit()), + ) + .field( + "pdma_axi_evt_in_fifo_full_ch0_st", + &format_args!("{}", self.pdma_axi_evt_in_fifo_full_ch0_st().bit()), + ) + .field( + "pdma_axi_evt_in_fifo_full_ch1_st", + &format_args!("{}", self.pdma_axi_evt_in_fifo_full_ch1_st().bit()), + ) + .field( + "pdma_axi_evt_in_fifo_full_ch2_st", + &format_args!("{}", self.pdma_axi_evt_in_fifo_full_ch2_st().bit()), + ) + .field( + "pdma_axi_evt_out_done_ch0_st", + &format_args!("{}", self.pdma_axi_evt_out_done_ch0_st().bit()), + ) + .field( + "pdma_axi_evt_out_done_ch1_st", + &format_args!("{}", self.pdma_axi_evt_out_done_ch1_st().bit()), + ) + .field( + "pdma_axi_evt_out_done_ch2_st", + &format_args!("{}", self.pdma_axi_evt_out_done_ch2_st().bit()), + ) + .field( + "pdma_axi_evt_out_eof_ch0_st", + &format_args!("{}", self.pdma_axi_evt_out_eof_ch0_st().bit()), + ) + .field( + "pdma_axi_evt_out_eof_ch1_st", + &format_args!("{}", self.pdma_axi_evt_out_eof_ch1_st().bit()), + ) + .field( + "pdma_axi_evt_out_eof_ch2_st", + &format_args!("{}", self.pdma_axi_evt_out_eof_ch2_st().bit()), + ) + .field( + "pdma_axi_evt_out_total_eof_ch0_st", + &format_args!("{}", self.pdma_axi_evt_out_total_eof_ch0_st().bit()), + ) + .field( + "pdma_axi_evt_out_total_eof_ch1_st", + &format_args!("{}", self.pdma_axi_evt_out_total_eof_ch1_st().bit()), + ) + .field( + "pdma_axi_evt_out_total_eof_ch2_st", + &format_args!("{}", self.pdma_axi_evt_out_total_eof_ch2_st().bit()), + ) + .field( + "pdma_axi_evt_out_fifo_empty_ch0_st", + &format_args!("{}", self.pdma_axi_evt_out_fifo_empty_ch0_st().bit()), + ) + .field( + "pdma_axi_evt_out_fifo_empty_ch1_st", + &format_args!("{}", self.pdma_axi_evt_out_fifo_empty_ch1_st().bit()), + ) + .field( + "pdma_axi_evt_out_fifo_empty_ch2_st", + &format_args!("{}", self.pdma_axi_evt_out_fifo_empty_ch2_st().bit()), + ) + .field( + "pdma_axi_evt_out_fifo_full_ch0_st", + &format_args!("{}", self.pdma_axi_evt_out_fifo_full_ch0_st().bit()), + ) + .field( + "pdma_axi_evt_out_fifo_full_ch1_st", + &format_args!("{}", self.pdma_axi_evt_out_fifo_full_ch1_st().bit()), + ) + .field( + "pdma_axi_evt_out_fifo_full_ch2_st", + &format_args!("{}", self.pdma_axi_evt_out_fifo_full_ch2_st().bit()), + ) + .field( + "pmu_evt_sleep_weekup_st", + &format_args!("{}", self.pmu_evt_sleep_weekup_st().bit()), + ) + .field( + "dma2d_evt_in_done_ch0_st", + &format_args!("{}", self.dma2d_evt_in_done_ch0_st().bit()), + ) + .field( + "dma2d_evt_in_done_ch1_st", + &format_args!("{}", self.dma2d_evt_in_done_ch1_st().bit()), + ) + .field( + "dma2d_evt_in_suc_eof_ch0_st", + &format_args!("{}", self.dma2d_evt_in_suc_eof_ch0_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_full_ch2_st( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_W { + PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_done_ch0_st(&mut self) -> PDMA_AXI_EVT_IN_DONE_CH0_ST_W { + PDMA_AXI_EVT_IN_DONE_CH0_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_done_ch1_st(&mut self) -> PDMA_AXI_EVT_IN_DONE_CH1_ST_W { + PDMA_AXI_EVT_IN_DONE_CH1_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_done_ch2_st(&mut self) -> PDMA_AXI_EVT_IN_DONE_CH2_ST_W { + PDMA_AXI_EVT_IN_DONE_CH2_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_suc_eof_ch0_st( + &mut self, + ) -> PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_W { + PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_suc_eof_ch1_st( + &mut self, + ) -> PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_W { + PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_suc_eof_ch2_st( + &mut self, + ) -> PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_W { + PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_empty_ch0_st( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_W { + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_empty_ch1_st( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_W { + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_empty_ch2_st( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_W { + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_full_ch0_st( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_W { + PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_full_ch1_st( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_W { + PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_full_ch2_st( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_W { + PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_done_ch0_st(&mut self) -> PDMA_AXI_EVT_OUT_DONE_CH0_ST_W { + PDMA_AXI_EVT_OUT_DONE_CH0_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_done_ch1_st(&mut self) -> PDMA_AXI_EVT_OUT_DONE_CH1_ST_W { + PDMA_AXI_EVT_OUT_DONE_CH1_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_done_ch2_st(&mut self) -> PDMA_AXI_EVT_OUT_DONE_CH2_ST_W { + PDMA_AXI_EVT_OUT_DONE_CH2_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_eof_ch0_st(&mut self) -> PDMA_AXI_EVT_OUT_EOF_CH0_ST_W { + PDMA_AXI_EVT_OUT_EOF_CH0_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_eof_ch1_st(&mut self) -> PDMA_AXI_EVT_OUT_EOF_CH1_ST_W { + PDMA_AXI_EVT_OUT_EOF_CH1_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_eof_ch2_st(&mut self) -> PDMA_AXI_EVT_OUT_EOF_CH2_ST_W { + PDMA_AXI_EVT_OUT_EOF_CH2_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_total_eof_ch0_st( + &mut self, + ) -> PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_W { + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_total_eof_ch1_st( + &mut self, + ) -> PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_W { + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_total_eof_ch2_st( + &mut self, + ) -> PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_W { + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_empty_ch0_st( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_W { + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_empty_ch1_st( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_W { + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_empty_ch2_st( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_W { + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_full_ch0_st( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_W { + PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_full_ch1_st( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_W { + PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_full_ch2_st( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_W { + PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents PMU_evt_sleep_weekup trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pmu_evt_sleep_weekup_st(&mut self) -> PMU_EVT_SLEEP_WEEKUP_ST_W { + PMU_EVT_SLEEP_WEEKUP_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents DMA2D_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_in_done_ch0_st(&mut self) -> DMA2D_EVT_IN_DONE_CH0_ST_W { + DMA2D_EVT_IN_DONE_CH0_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents DMA2D_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_in_done_ch1_st(&mut self) -> DMA2D_EVT_IN_DONE_CH1_ST_W { + DMA2D_EVT_IN_DONE_CH1_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_in_suc_eof_ch0_st(&mut self) -> DMA2D_EVT_IN_SUC_EOF_CH0_ST_W { + DMA2D_EVT_IN_SUC_EOF_CH0_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST6_SPEC; +impl crate::RegisterSpec for EVT_ST6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_st6::R`](R) reader structure"] +impl crate::Readable for EVT_ST6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_st6::W`](W) writer structure"] +impl crate::Writable for EVT_ST6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST6 to value 0"] +impl crate::Resettable for EVT_ST6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st6_clr.rs b/esp32p4/src/soc_etm/evt_st6_clr.rs new file mode 100644 index 0000000000..152574315b --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st6_clr.rs @@ -0,0 +1,354 @@ +#[doc = "Register `EVT_ST6_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PMU_EVT_SLEEP_WEEKUP_ST_CLR` writer - Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PMU_EVT_SLEEP_WEEKUP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_IN_DONE_CH0_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_IN_DONE_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_IN_DONE_CH1_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_IN_DONE_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_evt_out_fifo_full_ch2_st_clr( + &mut self, + ) -> PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_W { + PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_done_ch0_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_W { + PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_done_ch1_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_W { + PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_done_ch2_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_W { + PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_suc_eof_ch0_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_W { + PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_suc_eof_ch1_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_W { + PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_suc_eof_ch2_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_W { + PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_empty_ch0_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_W { + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_empty_ch1_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_W { + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_empty_ch2_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_W { + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_full_ch0_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_W { + PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_full_ch1_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_W { + PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_in_fifo_full_ch2_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_W { + PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_done_ch0_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_W { + PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_done_ch1_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_W { + PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_done_ch2_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_W { + PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_eof_ch0_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_W { + PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_eof_ch1_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_W { + PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_eof_ch2_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_W { + PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_total_eof_ch0_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W { + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_total_eof_ch1_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W { + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_total_eof_ch2_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W { + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_empty_ch0_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W { + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_empty_ch1_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W { + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_empty_ch2_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W { + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_full_ch0_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W { + PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_full_ch1_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W { + PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_evt_out_fifo_full_ch2_st_clr( + &mut self, + ) -> PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_W { + PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pmu_evt_sleep_weekup_st_clr( + &mut self, + ) -> PMU_EVT_SLEEP_WEEKUP_ST_CLR_W { + PMU_EVT_SLEEP_WEEKUP_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_in_done_ch0_st_clr( + &mut self, + ) -> DMA2D_EVT_IN_DONE_CH0_ST_CLR_W { + DMA2D_EVT_IN_DONE_CH0_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_in_done_ch1_st_clr( + &mut self, + ) -> DMA2D_EVT_IN_DONE_CH1_ST_CLR_W { + DMA2D_EVT_IN_DONE_CH1_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_in_suc_eof_ch0_st_clr( + &mut self, + ) -> DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_W { + DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st6_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST6_CLR_SPEC; +impl crate::RegisterSpec for EVT_ST6_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`evt_st6_clr::W`](W) writer structure"] +impl crate::Writable for EVT_ST6_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST6_CLR to value 0"] +impl crate::Resettable for EVT_ST6_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st7.rs b/esp32p4/src/soc_etm/evt_st7.rs new file mode 100644 index 0000000000..b039b0ab28 --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st7.rs @@ -0,0 +1,243 @@ +#[doc = "Register `EVT_ST7` reader"] +pub type R = crate::R; +#[doc = "Register `EVT_ST7` writer"] +pub type W = crate::W; +#[doc = "Field `DMA2D_EVT_IN_SUC_EOF_CH1_ST` reader - Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_IN_SUC_EOF_CH1_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_IN_SUC_EOF_CH1_ST` writer - Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_IN_SUC_EOF_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_DONE_CH0_ST` reader - Represents DMA2D_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_DONE_CH0_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_OUT_DONE_CH0_ST` writer - Represents DMA2D_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_DONE_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_DONE_CH1_ST` reader - Represents DMA2D_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_DONE_CH1_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_OUT_DONE_CH1_ST` writer - Represents DMA2D_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_DONE_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_DONE_CH2_ST` reader - Represents DMA2D_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_DONE_CH2_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_OUT_DONE_CH2_ST` writer - Represents DMA2D_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_DONE_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_EOF_CH0_ST` reader - Represents DMA2D_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_EOF_CH0_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_OUT_EOF_CH0_ST` writer - Represents DMA2D_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_EOF_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_EOF_CH1_ST` reader - Represents DMA2D_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_EOF_CH1_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_OUT_EOF_CH1_ST` writer - Represents DMA2D_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_EOF_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_EOF_CH2_ST` reader - Represents DMA2D_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_EOF_CH2_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_OUT_EOF_CH2_ST` writer - Represents DMA2D_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_EOF_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST` reader - Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST` writer - Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST` reader - Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST` writer - Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST` reader - Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST` writer - Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_in_suc_eof_ch1_st(&self) -> DMA2D_EVT_IN_SUC_EOF_CH1_ST_R { + DMA2D_EVT_IN_SUC_EOF_CH1_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents DMA2D_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_out_done_ch0_st(&self) -> DMA2D_EVT_OUT_DONE_CH0_ST_R { + DMA2D_EVT_OUT_DONE_CH0_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents DMA2D_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_out_done_ch1_st(&self) -> DMA2D_EVT_OUT_DONE_CH1_ST_R { + DMA2D_EVT_OUT_DONE_CH1_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents DMA2D_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_out_done_ch2_st(&self) -> DMA2D_EVT_OUT_DONE_CH2_ST_R { + DMA2D_EVT_OUT_DONE_CH2_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents DMA2D_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_out_eof_ch0_st(&self) -> DMA2D_EVT_OUT_EOF_CH0_ST_R { + DMA2D_EVT_OUT_EOF_CH0_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents DMA2D_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_out_eof_ch1_st(&self) -> DMA2D_EVT_OUT_EOF_CH1_ST_R { + DMA2D_EVT_OUT_EOF_CH1_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents DMA2D_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_out_eof_ch2_st(&self) -> DMA2D_EVT_OUT_EOF_CH2_ST_R { + DMA2D_EVT_OUT_EOF_CH2_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_out_total_eof_ch0_st(&self) -> DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_R { + DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_out_total_eof_ch1_st(&self) -> DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_R { + DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_evt_out_total_eof_ch2_st(&self) -> DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_R { + DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVT_ST7") + .field( + "dma2d_evt_in_suc_eof_ch1_st", + &format_args!("{}", self.dma2d_evt_in_suc_eof_ch1_st().bit()), + ) + .field( + "dma2d_evt_out_done_ch0_st", + &format_args!("{}", self.dma2d_evt_out_done_ch0_st().bit()), + ) + .field( + "dma2d_evt_out_done_ch1_st", + &format_args!("{}", self.dma2d_evt_out_done_ch1_st().bit()), + ) + .field( + "dma2d_evt_out_done_ch2_st", + &format_args!("{}", self.dma2d_evt_out_done_ch2_st().bit()), + ) + .field( + "dma2d_evt_out_eof_ch0_st", + &format_args!("{}", self.dma2d_evt_out_eof_ch0_st().bit()), + ) + .field( + "dma2d_evt_out_eof_ch1_st", + &format_args!("{}", self.dma2d_evt_out_eof_ch1_st().bit()), + ) + .field( + "dma2d_evt_out_eof_ch2_st", + &format_args!("{}", self.dma2d_evt_out_eof_ch2_st().bit()), + ) + .field( + "dma2d_evt_out_total_eof_ch0_st", + &format_args!("{}", self.dma2d_evt_out_total_eof_ch0_st().bit()), + ) + .field( + "dma2d_evt_out_total_eof_ch1_st", + &format_args!("{}", self.dma2d_evt_out_total_eof_ch1_st().bit()), + ) + .field( + "dma2d_evt_out_total_eof_ch2_st", + &format_args!("{}", self.dma2d_evt_out_total_eof_ch2_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_in_suc_eof_ch1_st(&mut self) -> DMA2D_EVT_IN_SUC_EOF_CH1_ST_W { + DMA2D_EVT_IN_SUC_EOF_CH1_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents DMA2D_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_done_ch0_st(&mut self) -> DMA2D_EVT_OUT_DONE_CH0_ST_W { + DMA2D_EVT_OUT_DONE_CH0_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents DMA2D_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_done_ch1_st(&mut self) -> DMA2D_EVT_OUT_DONE_CH1_ST_W { + DMA2D_EVT_OUT_DONE_CH1_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents DMA2D_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_done_ch2_st(&mut self) -> DMA2D_EVT_OUT_DONE_CH2_ST_W { + DMA2D_EVT_OUT_DONE_CH2_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents DMA2D_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_eof_ch0_st(&mut self) -> DMA2D_EVT_OUT_EOF_CH0_ST_W { + DMA2D_EVT_OUT_EOF_CH0_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents DMA2D_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_eof_ch1_st(&mut self) -> DMA2D_EVT_OUT_EOF_CH1_ST_W { + DMA2D_EVT_OUT_EOF_CH1_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents DMA2D_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_eof_ch2_st(&mut self) -> DMA2D_EVT_OUT_EOF_CH2_ST_W { + DMA2D_EVT_OUT_EOF_CH2_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_total_eof_ch0_st( + &mut self, + ) -> DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_W { + DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_total_eof_ch1_st( + &mut self, + ) -> DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_W { + DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_total_eof_ch2_st( + &mut self, + ) -> DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_W { + DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_st7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST7_SPEC; +impl crate::RegisterSpec for EVT_ST7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`evt_st7::R`](R) reader structure"] +impl crate::Readable for EVT_ST7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`evt_st7::W`](W) writer structure"] +impl crate::Writable for EVT_ST7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST7 to value 0"] +impl crate::Resettable for EVT_ST7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/evt_st7_clr.rs b/esp32p4/src/soc_etm/evt_st7_clr.rs new file mode 100644 index 0000000000..46409ec2a2 --- /dev/null +++ b/esp32p4/src/soc_etm/evt_st7_clr.rs @@ -0,0 +1,134 @@ +#[doc = "Register `EVT_ST7_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_DONE_CH0_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_OUT_DONE_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_DONE_CH1_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_OUT_DONE_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_DONE_CH2_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_OUT_DONE_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_EOF_CH0_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_OUT_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_EOF_CH1_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_OUT_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_EOF_CH2_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_OUT_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR` writer - Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_in_suc_eof_ch1_st_clr( + &mut self, + ) -> DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_W { + DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_done_ch0_st_clr( + &mut self, + ) -> DMA2D_EVT_OUT_DONE_CH0_ST_CLR_W { + DMA2D_EVT_OUT_DONE_CH0_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_done_ch1_st_clr( + &mut self, + ) -> DMA2D_EVT_OUT_DONE_CH1_ST_CLR_W { + DMA2D_EVT_OUT_DONE_CH1_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_done_ch2_st_clr( + &mut self, + ) -> DMA2D_EVT_OUT_DONE_CH2_ST_CLR_W { + DMA2D_EVT_OUT_DONE_CH2_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_eof_ch0_st_clr( + &mut self, + ) -> DMA2D_EVT_OUT_EOF_CH0_ST_CLR_W { + DMA2D_EVT_OUT_EOF_CH0_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_eof_ch1_st_clr( + &mut self, + ) -> DMA2D_EVT_OUT_EOF_CH1_ST_CLR_W { + DMA2D_EVT_OUT_EOF_CH1_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_eof_ch2_st_clr( + &mut self, + ) -> DMA2D_EVT_OUT_EOF_CH2_ST_CLR_W { + DMA2D_EVT_OUT_EOF_CH2_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_total_eof_ch0_st_clr( + &mut self, + ) -> DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W { + DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_total_eof_ch1_st_clr( + &mut self, + ) -> DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W { + DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_evt_out_total_eof_ch2_st_clr( + &mut self, + ) -> DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W { + DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Events trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_st7_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EVT_ST7_CLR_SPEC; +impl crate::RegisterSpec for EVT_ST7_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`evt_st7_clr::W`](W) writer structure"] +impl crate::Writable for EVT_ST7_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVT_ST7_CLR to value 0"] +impl crate::Resettable for EVT_ST7_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st0.rs b/esp32p4/src/soc_etm/task_st0.rs new file mode 100644 index 0000000000..89f38b1a15 --- /dev/null +++ b/esp32p4/src/soc_etm/task_st0.rs @@ -0,0 +1,671 @@ +#[doc = "Register `TASK_ST0` reader"] +pub type R = crate::R; +#[doc = "Register `TASK_ST0` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_TASK_CH0_SET_ST` reader - Represents GPIO_task_ch0_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH0_SET_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH0_SET_ST` writer - Represents GPIO_task_ch0_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH0_SET_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH1_SET_ST` reader - Represents GPIO_task_ch1_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH1_SET_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH1_SET_ST` writer - Represents GPIO_task_ch1_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH1_SET_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH2_SET_ST` reader - Represents GPIO_task_ch2_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH2_SET_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH2_SET_ST` writer - Represents GPIO_task_ch2_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH2_SET_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH3_SET_ST` reader - Represents GPIO_task_ch3_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH3_SET_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH3_SET_ST` writer - Represents GPIO_task_ch3_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH3_SET_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH4_SET_ST` reader - Represents GPIO_task_ch4_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH4_SET_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH4_SET_ST` writer - Represents GPIO_task_ch4_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH4_SET_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH5_SET_ST` reader - Represents GPIO_task_ch5_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH5_SET_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH5_SET_ST` writer - Represents GPIO_task_ch5_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH5_SET_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH6_SET_ST` reader - Represents GPIO_task_ch6_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH6_SET_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH6_SET_ST` writer - Represents GPIO_task_ch6_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH6_SET_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH7_SET_ST` reader - Represents GPIO_task_ch7_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH7_SET_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH7_SET_ST` writer - Represents GPIO_task_ch7_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH7_SET_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH0_CLEAR_ST` reader - Represents GPIO_task_ch0_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH0_CLEAR_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH0_CLEAR_ST` writer - Represents GPIO_task_ch0_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH0_CLEAR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH1_CLEAR_ST` reader - Represents GPIO_task_ch1_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH1_CLEAR_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH1_CLEAR_ST` writer - Represents GPIO_task_ch1_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH1_CLEAR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH2_CLEAR_ST` reader - Represents GPIO_task_ch2_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH2_CLEAR_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH2_CLEAR_ST` writer - Represents GPIO_task_ch2_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH2_CLEAR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH3_CLEAR_ST` reader - Represents GPIO_task_ch3_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH3_CLEAR_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH3_CLEAR_ST` writer - Represents GPIO_task_ch3_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH3_CLEAR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH4_CLEAR_ST` reader - Represents GPIO_task_ch4_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH4_CLEAR_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH4_CLEAR_ST` writer - Represents GPIO_task_ch4_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH4_CLEAR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH5_CLEAR_ST` reader - Represents GPIO_task_ch5_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH5_CLEAR_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH5_CLEAR_ST` writer - Represents GPIO_task_ch5_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH5_CLEAR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH6_CLEAR_ST` reader - Represents GPIO_task_ch6_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH6_CLEAR_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH6_CLEAR_ST` writer - Represents GPIO_task_ch6_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH6_CLEAR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH7_CLEAR_ST` reader - Represents GPIO_task_ch7_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH7_CLEAR_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH7_CLEAR_ST` writer - Represents GPIO_task_ch7_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH7_CLEAR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH0_TOGGLE_ST` reader - Represents GPIO_task_ch0_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH0_TOGGLE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH0_TOGGLE_ST` writer - Represents GPIO_task_ch0_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH0_TOGGLE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH1_TOGGLE_ST` reader - Represents GPIO_task_ch1_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH1_TOGGLE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH1_TOGGLE_ST` writer - Represents GPIO_task_ch1_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH1_TOGGLE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH2_TOGGLE_ST` reader - Represents GPIO_task_ch2_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH2_TOGGLE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH2_TOGGLE_ST` writer - Represents GPIO_task_ch2_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH2_TOGGLE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH3_TOGGLE_ST` reader - Represents GPIO_task_ch3_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH3_TOGGLE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH3_TOGGLE_ST` writer - Represents GPIO_task_ch3_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH3_TOGGLE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH4_TOGGLE_ST` reader - Represents GPIO_task_ch4_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH4_TOGGLE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH4_TOGGLE_ST` writer - Represents GPIO_task_ch4_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH4_TOGGLE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH5_TOGGLE_ST` reader - Represents GPIO_task_ch5_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH5_TOGGLE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH5_TOGGLE_ST` writer - Represents GPIO_task_ch5_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH5_TOGGLE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH6_TOGGLE_ST` reader - Represents GPIO_task_ch6_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH6_TOGGLE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH6_TOGGLE_ST` writer - Represents GPIO_task_ch6_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH6_TOGGLE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH7_TOGGLE_ST` reader - Represents GPIO_task_ch7_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH7_TOGGLE_ST_R = crate::BitReader; +#[doc = "Field `GPIO_TASK_CH7_TOGGLE_ST` writer - Represents GPIO_task_ch7_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type GPIO_TASK_CH7_TOGGLE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER0_RES_UPDATE_ST` reader - Represents LEDC_task_timer0_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER0_RES_UPDATE_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER0_RES_UPDATE_ST` writer - Represents LEDC_task_timer0_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER0_RES_UPDATE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER1_RES_UPDATE_ST` reader - Represents LEDC_task_timer1_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER1_RES_UPDATE_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER1_RES_UPDATE_ST` writer - Represents LEDC_task_timer1_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER1_RES_UPDATE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER2_RES_UPDATE_ST` reader - Represents LEDC_task_timer2_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER2_RES_UPDATE_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER2_RES_UPDATE_ST` writer - Represents LEDC_task_timer2_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER2_RES_UPDATE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER3_RES_UPDATE_ST` reader - Represents LEDC_task_timer3_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER3_RES_UPDATE_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER3_RES_UPDATE_ST` writer - Represents LEDC_task_timer3_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER3_RES_UPDATE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST` reader - Represents LEDC_task_duty_scale_update_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST` writer - Represents LEDC_task_duty_scale_update_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST` reader - Represents LEDC_task_duty_scale_update_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST` writer - Represents LEDC_task_duty_scale_update_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST` reader - Represents LEDC_task_duty_scale_update_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST` writer - Represents LEDC_task_duty_scale_update_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST` reader - Represents LEDC_task_duty_scale_update_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST` writer - Represents LEDC_task_duty_scale_update_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents GPIO_task_ch0_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch0_set_st(&self) -> GPIO_TASK_CH0_SET_ST_R { + GPIO_TASK_CH0_SET_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents GPIO_task_ch1_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch1_set_st(&self) -> GPIO_TASK_CH1_SET_ST_R { + GPIO_TASK_CH1_SET_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents GPIO_task_ch2_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch2_set_st(&self) -> GPIO_TASK_CH2_SET_ST_R { + GPIO_TASK_CH2_SET_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents GPIO_task_ch3_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch3_set_st(&self) -> GPIO_TASK_CH3_SET_ST_R { + GPIO_TASK_CH3_SET_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents GPIO_task_ch4_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch4_set_st(&self) -> GPIO_TASK_CH4_SET_ST_R { + GPIO_TASK_CH4_SET_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents GPIO_task_ch5_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch5_set_st(&self) -> GPIO_TASK_CH5_SET_ST_R { + GPIO_TASK_CH5_SET_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents GPIO_task_ch6_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch6_set_st(&self) -> GPIO_TASK_CH6_SET_ST_R { + GPIO_TASK_CH6_SET_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents GPIO_task_ch7_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch7_set_st(&self) -> GPIO_TASK_CH7_SET_ST_R { + GPIO_TASK_CH7_SET_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents GPIO_task_ch0_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch0_clear_st(&self) -> GPIO_TASK_CH0_CLEAR_ST_R { + GPIO_TASK_CH0_CLEAR_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents GPIO_task_ch1_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch1_clear_st(&self) -> GPIO_TASK_CH1_CLEAR_ST_R { + GPIO_TASK_CH1_CLEAR_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents GPIO_task_ch2_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch2_clear_st(&self) -> GPIO_TASK_CH2_CLEAR_ST_R { + GPIO_TASK_CH2_CLEAR_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents GPIO_task_ch3_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch3_clear_st(&self) -> GPIO_TASK_CH3_CLEAR_ST_R { + GPIO_TASK_CH3_CLEAR_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents GPIO_task_ch4_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch4_clear_st(&self) -> GPIO_TASK_CH4_CLEAR_ST_R { + GPIO_TASK_CH4_CLEAR_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents GPIO_task_ch5_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch5_clear_st(&self) -> GPIO_TASK_CH5_CLEAR_ST_R { + GPIO_TASK_CH5_CLEAR_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents GPIO_task_ch6_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch6_clear_st(&self) -> GPIO_TASK_CH6_CLEAR_ST_R { + GPIO_TASK_CH6_CLEAR_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents GPIO_task_ch7_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch7_clear_st(&self) -> GPIO_TASK_CH7_CLEAR_ST_R { + GPIO_TASK_CH7_CLEAR_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents GPIO_task_ch0_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch0_toggle_st(&self) -> GPIO_TASK_CH0_TOGGLE_ST_R { + GPIO_TASK_CH0_TOGGLE_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents GPIO_task_ch1_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch1_toggle_st(&self) -> GPIO_TASK_CH1_TOGGLE_ST_R { + GPIO_TASK_CH1_TOGGLE_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents GPIO_task_ch2_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch2_toggle_st(&self) -> GPIO_TASK_CH2_TOGGLE_ST_R { + GPIO_TASK_CH2_TOGGLE_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents GPIO_task_ch3_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch3_toggle_st(&self) -> GPIO_TASK_CH3_TOGGLE_ST_R { + GPIO_TASK_CH3_TOGGLE_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents GPIO_task_ch4_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch4_toggle_st(&self) -> GPIO_TASK_CH4_TOGGLE_ST_R { + GPIO_TASK_CH4_TOGGLE_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents GPIO_task_ch5_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch5_toggle_st(&self) -> GPIO_TASK_CH5_TOGGLE_ST_R { + GPIO_TASK_CH5_TOGGLE_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents GPIO_task_ch6_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch6_toggle_st(&self) -> GPIO_TASK_CH6_TOGGLE_ST_R { + GPIO_TASK_CH6_TOGGLE_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents GPIO_task_ch7_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn gpio_task_ch7_toggle_st(&self) -> GPIO_TASK_CH7_TOGGLE_ST_R { + GPIO_TASK_CH7_TOGGLE_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents LEDC_task_timer0_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer0_res_update_st(&self) -> LEDC_TASK_TIMER0_RES_UPDATE_ST_R { + LEDC_TASK_TIMER0_RES_UPDATE_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents LEDC_task_timer1_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer1_res_update_st(&self) -> LEDC_TASK_TIMER1_RES_UPDATE_ST_R { + LEDC_TASK_TIMER1_RES_UPDATE_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents LEDC_task_timer2_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer2_res_update_st(&self) -> LEDC_TASK_TIMER2_RES_UPDATE_ST_R { + LEDC_TASK_TIMER2_RES_UPDATE_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents LEDC_task_timer3_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer3_res_update_st(&self) -> LEDC_TASK_TIMER3_RES_UPDATE_ST_R { + LEDC_TASK_TIMER3_RES_UPDATE_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents LEDC_task_duty_scale_update_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_duty_scale_update_ch0_st(&self) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_R { + LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents LEDC_task_duty_scale_update_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_duty_scale_update_ch1_st(&self) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_R { + LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents LEDC_task_duty_scale_update_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_duty_scale_update_ch2_st(&self) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_R { + LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents LEDC_task_duty_scale_update_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_duty_scale_update_ch3_st(&self) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_R { + LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TASK_ST0") + .field( + "gpio_task_ch0_set_st", + &format_args!("{}", self.gpio_task_ch0_set_st().bit()), + ) + .field( + "gpio_task_ch1_set_st", + &format_args!("{}", self.gpio_task_ch1_set_st().bit()), + ) + .field( + "gpio_task_ch2_set_st", + &format_args!("{}", self.gpio_task_ch2_set_st().bit()), + ) + .field( + "gpio_task_ch3_set_st", + &format_args!("{}", self.gpio_task_ch3_set_st().bit()), + ) + .field( + "gpio_task_ch4_set_st", + &format_args!("{}", self.gpio_task_ch4_set_st().bit()), + ) + .field( + "gpio_task_ch5_set_st", + &format_args!("{}", self.gpio_task_ch5_set_st().bit()), + ) + .field( + "gpio_task_ch6_set_st", + &format_args!("{}", self.gpio_task_ch6_set_st().bit()), + ) + .field( + "gpio_task_ch7_set_st", + &format_args!("{}", self.gpio_task_ch7_set_st().bit()), + ) + .field( + "gpio_task_ch0_clear_st", + &format_args!("{}", self.gpio_task_ch0_clear_st().bit()), + ) + .field( + "gpio_task_ch1_clear_st", + &format_args!("{}", self.gpio_task_ch1_clear_st().bit()), + ) + .field( + "gpio_task_ch2_clear_st", + &format_args!("{}", self.gpio_task_ch2_clear_st().bit()), + ) + .field( + "gpio_task_ch3_clear_st", + &format_args!("{}", self.gpio_task_ch3_clear_st().bit()), + ) + .field( + "gpio_task_ch4_clear_st", + &format_args!("{}", self.gpio_task_ch4_clear_st().bit()), + ) + .field( + "gpio_task_ch5_clear_st", + &format_args!("{}", self.gpio_task_ch5_clear_st().bit()), + ) + .field( + "gpio_task_ch6_clear_st", + &format_args!("{}", self.gpio_task_ch6_clear_st().bit()), + ) + .field( + "gpio_task_ch7_clear_st", + &format_args!("{}", self.gpio_task_ch7_clear_st().bit()), + ) + .field( + "gpio_task_ch0_toggle_st", + &format_args!("{}", self.gpio_task_ch0_toggle_st().bit()), + ) + .field( + "gpio_task_ch1_toggle_st", + &format_args!("{}", self.gpio_task_ch1_toggle_st().bit()), + ) + .field( + "gpio_task_ch2_toggle_st", + &format_args!("{}", self.gpio_task_ch2_toggle_st().bit()), + ) + .field( + "gpio_task_ch3_toggle_st", + &format_args!("{}", self.gpio_task_ch3_toggle_st().bit()), + ) + .field( + "gpio_task_ch4_toggle_st", + &format_args!("{}", self.gpio_task_ch4_toggle_st().bit()), + ) + .field( + "gpio_task_ch5_toggle_st", + &format_args!("{}", self.gpio_task_ch5_toggle_st().bit()), + ) + .field( + "gpio_task_ch6_toggle_st", + &format_args!("{}", self.gpio_task_ch6_toggle_st().bit()), + ) + .field( + "gpio_task_ch7_toggle_st", + &format_args!("{}", self.gpio_task_ch7_toggle_st().bit()), + ) + .field( + "ledc_task_timer0_res_update_st", + &format_args!("{}", self.ledc_task_timer0_res_update_st().bit()), + ) + .field( + "ledc_task_timer1_res_update_st", + &format_args!("{}", self.ledc_task_timer1_res_update_st().bit()), + ) + .field( + "ledc_task_timer2_res_update_st", + &format_args!("{}", self.ledc_task_timer2_res_update_st().bit()), + ) + .field( + "ledc_task_timer3_res_update_st", + &format_args!("{}", self.ledc_task_timer3_res_update_st().bit()), + ) + .field( + "ledc_task_duty_scale_update_ch0_st", + &format_args!("{}", self.ledc_task_duty_scale_update_ch0_st().bit()), + ) + .field( + "ledc_task_duty_scale_update_ch1_st", + &format_args!("{}", self.ledc_task_duty_scale_update_ch1_st().bit()), + ) + .field( + "ledc_task_duty_scale_update_ch2_st", + &format_args!("{}", self.ledc_task_duty_scale_update_ch2_st().bit()), + ) + .field( + "ledc_task_duty_scale_update_ch3_st", + &format_args!("{}", self.ledc_task_duty_scale_update_ch3_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents GPIO_task_ch0_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch0_set_st(&mut self) -> GPIO_TASK_CH0_SET_ST_W { + GPIO_TASK_CH0_SET_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents GPIO_task_ch1_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch1_set_st(&mut self) -> GPIO_TASK_CH1_SET_ST_W { + GPIO_TASK_CH1_SET_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents GPIO_task_ch2_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch2_set_st(&mut self) -> GPIO_TASK_CH2_SET_ST_W { + GPIO_TASK_CH2_SET_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents GPIO_task_ch3_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch3_set_st(&mut self) -> GPIO_TASK_CH3_SET_ST_W { + GPIO_TASK_CH3_SET_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents GPIO_task_ch4_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch4_set_st(&mut self) -> GPIO_TASK_CH4_SET_ST_W { + GPIO_TASK_CH4_SET_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents GPIO_task_ch5_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch5_set_st(&mut self) -> GPIO_TASK_CH5_SET_ST_W { + GPIO_TASK_CH5_SET_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents GPIO_task_ch6_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch6_set_st(&mut self) -> GPIO_TASK_CH6_SET_ST_W { + GPIO_TASK_CH6_SET_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents GPIO_task_ch7_set trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch7_set_st(&mut self) -> GPIO_TASK_CH7_SET_ST_W { + GPIO_TASK_CH7_SET_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents GPIO_task_ch0_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch0_clear_st(&mut self) -> GPIO_TASK_CH0_CLEAR_ST_W { + GPIO_TASK_CH0_CLEAR_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents GPIO_task_ch1_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch1_clear_st(&mut self) -> GPIO_TASK_CH1_CLEAR_ST_W { + GPIO_TASK_CH1_CLEAR_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents GPIO_task_ch2_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch2_clear_st(&mut self) -> GPIO_TASK_CH2_CLEAR_ST_W { + GPIO_TASK_CH2_CLEAR_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents GPIO_task_ch3_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch3_clear_st(&mut self) -> GPIO_TASK_CH3_CLEAR_ST_W { + GPIO_TASK_CH3_CLEAR_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents GPIO_task_ch4_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch4_clear_st(&mut self) -> GPIO_TASK_CH4_CLEAR_ST_W { + GPIO_TASK_CH4_CLEAR_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents GPIO_task_ch5_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch5_clear_st(&mut self) -> GPIO_TASK_CH5_CLEAR_ST_W { + GPIO_TASK_CH5_CLEAR_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents GPIO_task_ch6_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch6_clear_st(&mut self) -> GPIO_TASK_CH6_CLEAR_ST_W { + GPIO_TASK_CH6_CLEAR_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents GPIO_task_ch7_clear trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch7_clear_st(&mut self) -> GPIO_TASK_CH7_CLEAR_ST_W { + GPIO_TASK_CH7_CLEAR_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents GPIO_task_ch0_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch0_toggle_st(&mut self) -> GPIO_TASK_CH0_TOGGLE_ST_W { + GPIO_TASK_CH0_TOGGLE_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents GPIO_task_ch1_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch1_toggle_st(&mut self) -> GPIO_TASK_CH1_TOGGLE_ST_W { + GPIO_TASK_CH1_TOGGLE_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents GPIO_task_ch2_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch2_toggle_st(&mut self) -> GPIO_TASK_CH2_TOGGLE_ST_W { + GPIO_TASK_CH2_TOGGLE_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents GPIO_task_ch3_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch3_toggle_st(&mut self) -> GPIO_TASK_CH3_TOGGLE_ST_W { + GPIO_TASK_CH3_TOGGLE_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents GPIO_task_ch4_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch4_toggle_st(&mut self) -> GPIO_TASK_CH4_TOGGLE_ST_W { + GPIO_TASK_CH4_TOGGLE_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents GPIO_task_ch5_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch5_toggle_st(&mut self) -> GPIO_TASK_CH5_TOGGLE_ST_W { + GPIO_TASK_CH5_TOGGLE_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents GPIO_task_ch6_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch6_toggle_st(&mut self) -> GPIO_TASK_CH6_TOGGLE_ST_W { + GPIO_TASK_CH6_TOGGLE_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents GPIO_task_ch7_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch7_toggle_st(&mut self) -> GPIO_TASK_CH7_TOGGLE_ST_W { + GPIO_TASK_CH7_TOGGLE_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents LEDC_task_timer0_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer0_res_update_st( + &mut self, + ) -> LEDC_TASK_TIMER0_RES_UPDATE_ST_W { + LEDC_TASK_TIMER0_RES_UPDATE_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents LEDC_task_timer1_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer1_res_update_st( + &mut self, + ) -> LEDC_TASK_TIMER1_RES_UPDATE_ST_W { + LEDC_TASK_TIMER1_RES_UPDATE_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents LEDC_task_timer2_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer2_res_update_st( + &mut self, + ) -> LEDC_TASK_TIMER2_RES_UPDATE_ST_W { + LEDC_TASK_TIMER2_RES_UPDATE_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents LEDC_task_timer3_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer3_res_update_st( + &mut self, + ) -> LEDC_TASK_TIMER3_RES_UPDATE_ST_W { + LEDC_TASK_TIMER3_RES_UPDATE_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents LEDC_task_duty_scale_update_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch0_st( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents LEDC_task_duty_scale_update_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch1_st( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents LEDC_task_duty_scale_update_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch2_st( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents LEDC_task_duty_scale_update_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch3_st( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST0_SPEC; +impl crate::RegisterSpec for TASK_ST0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`task_st0::R`](R) reader structure"] +impl crate::Readable for TASK_ST0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`task_st0::W`](W) writer structure"] +impl crate::Writable for TASK_ST0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST0 to value 0"] +impl crate::Resettable for TASK_ST0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st0_clr.rs b/esp32p4/src/soc_etm/task_st0_clr.rs new file mode 100644 index 0000000000..9e1b685cec --- /dev/null +++ b/esp32p4/src/soc_etm/task_st0_clr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `TASK_ST0_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_TASK_CH0_SET_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch0_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH0_SET_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH1_SET_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch1_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH1_SET_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH2_SET_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch2_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH2_SET_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH3_SET_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch3_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH3_SET_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH4_SET_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch4_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH4_SET_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH5_SET_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch5_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH5_SET_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH6_SET_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch6_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH6_SET_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH7_SET_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch7_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH7_SET_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH0_CLEAR_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH0_CLEAR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH1_CLEAR_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH1_CLEAR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH2_CLEAR_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH2_CLEAR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH3_CLEAR_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH3_CLEAR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH4_CLEAR_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH4_CLEAR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH5_CLEAR_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH5_CLEAR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH6_CLEAR_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH6_CLEAR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH7_CLEAR_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH7_CLEAR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH0_TOGGLE_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH0_TOGGLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH1_TOGGLE_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH1_TOGGLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH2_TOGGLE_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH2_TOGGLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH3_TOGGLE_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH3_TOGGLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH4_TOGGLE_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH4_TOGGLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH5_TOGGLE_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH5_TOGGLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH6_TOGGLE_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH6_TOGGLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_TASK_CH7_TOGGLE_ST_CLR` writer - Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type GPIO_TASK_CH7_TOGGLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR` writer - Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR` writer - Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR` writer - Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR` writer - Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear GPIO_task_ch0_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch0_set_st_clr(&mut self) -> GPIO_TASK_CH0_SET_ST_CLR_W { + GPIO_TASK_CH0_SET_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear GPIO_task_ch1_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch1_set_st_clr(&mut self) -> GPIO_TASK_CH1_SET_ST_CLR_W { + GPIO_TASK_CH1_SET_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear GPIO_task_ch2_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch2_set_st_clr(&mut self) -> GPIO_TASK_CH2_SET_ST_CLR_W { + GPIO_TASK_CH2_SET_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear GPIO_task_ch3_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch3_set_st_clr(&mut self) -> GPIO_TASK_CH3_SET_ST_CLR_W { + GPIO_TASK_CH3_SET_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear GPIO_task_ch4_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch4_set_st_clr(&mut self) -> GPIO_TASK_CH4_SET_ST_CLR_W { + GPIO_TASK_CH4_SET_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear GPIO_task_ch5_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch5_set_st_clr(&mut self) -> GPIO_TASK_CH5_SET_ST_CLR_W { + GPIO_TASK_CH5_SET_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear GPIO_task_ch6_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch6_set_st_clr(&mut self) -> GPIO_TASK_CH6_SET_ST_CLR_W { + GPIO_TASK_CH6_SET_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear GPIO_task_ch7_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch7_set_st_clr(&mut self) -> GPIO_TASK_CH7_SET_ST_CLR_W { + GPIO_TASK_CH7_SET_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch0_clear_st_clr( + &mut self, + ) -> GPIO_TASK_CH0_CLEAR_ST_CLR_W { + GPIO_TASK_CH0_CLEAR_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch1_clear_st_clr( + &mut self, + ) -> GPIO_TASK_CH1_CLEAR_ST_CLR_W { + GPIO_TASK_CH1_CLEAR_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch2_clear_st_clr( + &mut self, + ) -> GPIO_TASK_CH2_CLEAR_ST_CLR_W { + GPIO_TASK_CH2_CLEAR_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch3_clear_st_clr( + &mut self, + ) -> GPIO_TASK_CH3_CLEAR_ST_CLR_W { + GPIO_TASK_CH3_CLEAR_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch4_clear_st_clr( + &mut self, + ) -> GPIO_TASK_CH4_CLEAR_ST_CLR_W { + GPIO_TASK_CH4_CLEAR_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch5_clear_st_clr( + &mut self, + ) -> GPIO_TASK_CH5_CLEAR_ST_CLR_W { + GPIO_TASK_CH5_CLEAR_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch6_clear_st_clr( + &mut self, + ) -> GPIO_TASK_CH6_CLEAR_ST_CLR_W { + GPIO_TASK_CH6_CLEAR_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch7_clear_st_clr( + &mut self, + ) -> GPIO_TASK_CH7_CLEAR_ST_CLR_W { + GPIO_TASK_CH7_CLEAR_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch0_toggle_st_clr( + &mut self, + ) -> GPIO_TASK_CH0_TOGGLE_ST_CLR_W { + GPIO_TASK_CH0_TOGGLE_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch1_toggle_st_clr( + &mut self, + ) -> GPIO_TASK_CH1_TOGGLE_ST_CLR_W { + GPIO_TASK_CH1_TOGGLE_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch2_toggle_st_clr( + &mut self, + ) -> GPIO_TASK_CH2_TOGGLE_ST_CLR_W { + GPIO_TASK_CH2_TOGGLE_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch3_toggle_st_clr( + &mut self, + ) -> GPIO_TASK_CH3_TOGGLE_ST_CLR_W { + GPIO_TASK_CH3_TOGGLE_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch4_toggle_st_clr( + &mut self, + ) -> GPIO_TASK_CH4_TOGGLE_ST_CLR_W { + GPIO_TASK_CH4_TOGGLE_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch5_toggle_st_clr( + &mut self, + ) -> GPIO_TASK_CH5_TOGGLE_ST_CLR_W { + GPIO_TASK_CH5_TOGGLE_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch6_toggle_st_clr( + &mut self, + ) -> GPIO_TASK_CH6_TOGGLE_ST_CLR_W { + GPIO_TASK_CH6_TOGGLE_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn gpio_task_ch7_toggle_st_clr( + &mut self, + ) -> GPIO_TASK_CH7_TOGGLE_ST_CLR_W { + GPIO_TASK_CH7_TOGGLE_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer0_res_update_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_W { + LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer1_res_update_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_W { + LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer2_res_update_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_W { + LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer3_res_update_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_W { + LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch0_st_clr( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch1_st_clr( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch2_st_clr( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch3_st_clr( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st0_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST0_CLR_SPEC; +impl crate::RegisterSpec for TASK_ST0_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`task_st0_clr::W`](W) writer structure"] +impl crate::Writable for TASK_ST0_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST0_CLR to value 0"] +impl crate::Resettable for TASK_ST0_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st1.rs b/esp32p4/src/soc_etm/task_st1.rs new file mode 100644 index 0000000000..541f2f7603 --- /dev/null +++ b/esp32p4/src/soc_etm/task_st1.rs @@ -0,0 +1,695 @@ +#[doc = "Register `TASK_ST1` reader"] +pub type R = crate::R; +#[doc = "Register `TASK_ST1` writer"] +pub type W = crate::W; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST` reader - Represents LEDC_task_duty_scale_update_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST` writer - Represents LEDC_task_duty_scale_update_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST` reader - Represents LEDC_task_duty_scale_update_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST` writer - Represents LEDC_task_duty_scale_update_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST` reader - Represents LEDC_task_duty_scale_update_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST` writer - Represents LEDC_task_duty_scale_update_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST` reader - Represents LEDC_task_duty_scale_update_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST` writer - Represents LEDC_task_duty_scale_update_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER0_CAP_ST` reader - Represents LEDC_task_timer0_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER0_CAP_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER0_CAP_ST` writer - Represents LEDC_task_timer0_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER0_CAP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER1_CAP_ST` reader - Represents LEDC_task_timer1_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER1_CAP_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER1_CAP_ST` writer - Represents LEDC_task_timer1_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER1_CAP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER2_CAP_ST` reader - Represents LEDC_task_timer2_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER2_CAP_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER2_CAP_ST` writer - Represents LEDC_task_timer2_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER2_CAP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER3_CAP_ST` reader - Represents LEDC_task_timer3_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER3_CAP_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER3_CAP_ST` writer - Represents LEDC_task_timer3_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER3_CAP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH0_ST` reader - Represents LEDC_task_sig_out_dis_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH0_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH0_ST` writer - Represents LEDC_task_sig_out_dis_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH1_ST` reader - Represents LEDC_task_sig_out_dis_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH1_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH1_ST` writer - Represents LEDC_task_sig_out_dis_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH2_ST` reader - Represents LEDC_task_sig_out_dis_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH2_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH2_ST` writer - Represents LEDC_task_sig_out_dis_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH3_ST` reader - Represents LEDC_task_sig_out_dis_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH3_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH3_ST` writer - Represents LEDC_task_sig_out_dis_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH4_ST` reader - Represents LEDC_task_sig_out_dis_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH4_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH4_ST` writer - Represents LEDC_task_sig_out_dis_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH5_ST` reader - Represents LEDC_task_sig_out_dis_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH5_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH5_ST` writer - Represents LEDC_task_sig_out_dis_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH5_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH6_ST` reader - Represents LEDC_task_sig_out_dis_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH6_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH6_ST` writer - Represents LEDC_task_sig_out_dis_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH6_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH7_ST` reader - Represents LEDC_task_sig_out_dis_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH7_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH7_ST` writer - Represents LEDC_task_sig_out_dis_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_SIG_OUT_DIS_CH7_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH0_ST` reader - Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH0_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH0_ST` writer - Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH1_ST` reader - Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH1_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH1_ST` writer - Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH2_ST` reader - Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH2_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH2_ST` writer - Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH3_ST` reader - Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH3_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH3_ST` writer - Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH4_ST` reader - Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH4_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH4_ST` writer - Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH5_ST` reader - Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH5_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH5_ST` writer - Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH5_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH6_ST` reader - Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH6_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH6_ST` writer - Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH6_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH7_ST` reader - Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH7_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH7_ST` writer - Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_OVF_CNT_RST_CH7_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER0_RST_ST` reader - Represents LEDC_task_timer0_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER0_RST_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER0_RST_ST` writer - Represents LEDC_task_timer0_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER0_RST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER1_RST_ST` reader - Represents LEDC_task_timer1_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER1_RST_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER1_RST_ST` writer - Represents LEDC_task_timer1_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER1_RST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER2_RST_ST` reader - Represents LEDC_task_timer2_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER2_RST_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER2_RST_ST` writer - Represents LEDC_task_timer2_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER2_RST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER3_RST_ST` reader - Represents LEDC_task_timer3_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER3_RST_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER3_RST_ST` writer - Represents LEDC_task_timer3_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER3_RST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER0_RESUME_ST` reader - Represents LEDC_task_timer0_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER0_RESUME_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER0_RESUME_ST` writer - Represents LEDC_task_timer0_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER0_RESUME_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER1_RESUME_ST` reader - Represents LEDC_task_timer1_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER1_RESUME_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER1_RESUME_ST` writer - Represents LEDC_task_timer1_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER1_RESUME_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER2_RESUME_ST` reader - Represents LEDC_task_timer2_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER2_RESUME_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER2_RESUME_ST` writer - Represents LEDC_task_timer2_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER2_RESUME_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER3_RESUME_ST` reader - Represents LEDC_task_timer3_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER3_RESUME_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER3_RESUME_ST` writer - Represents LEDC_task_timer3_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER3_RESUME_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents LEDC_task_duty_scale_update_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_duty_scale_update_ch4_st(&self) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_R { + LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents LEDC_task_duty_scale_update_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_duty_scale_update_ch5_st(&self) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_R { + LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents LEDC_task_duty_scale_update_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_duty_scale_update_ch6_st(&self) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_R { + LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents LEDC_task_duty_scale_update_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_duty_scale_update_ch7_st(&self) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_R { + LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents LEDC_task_timer0_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer0_cap_st(&self) -> LEDC_TASK_TIMER0_CAP_ST_R { + LEDC_TASK_TIMER0_CAP_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents LEDC_task_timer1_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer1_cap_st(&self) -> LEDC_TASK_TIMER1_CAP_ST_R { + LEDC_TASK_TIMER1_CAP_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents LEDC_task_timer2_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer2_cap_st(&self) -> LEDC_TASK_TIMER2_CAP_ST_R { + LEDC_TASK_TIMER2_CAP_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents LEDC_task_timer3_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer3_cap_st(&self) -> LEDC_TASK_TIMER3_CAP_ST_R { + LEDC_TASK_TIMER3_CAP_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents LEDC_task_sig_out_dis_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_sig_out_dis_ch0_st(&self) -> LEDC_TASK_SIG_OUT_DIS_CH0_ST_R { + LEDC_TASK_SIG_OUT_DIS_CH0_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents LEDC_task_sig_out_dis_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_sig_out_dis_ch1_st(&self) -> LEDC_TASK_SIG_OUT_DIS_CH1_ST_R { + LEDC_TASK_SIG_OUT_DIS_CH1_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents LEDC_task_sig_out_dis_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_sig_out_dis_ch2_st(&self) -> LEDC_TASK_SIG_OUT_DIS_CH2_ST_R { + LEDC_TASK_SIG_OUT_DIS_CH2_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents LEDC_task_sig_out_dis_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_sig_out_dis_ch3_st(&self) -> LEDC_TASK_SIG_OUT_DIS_CH3_ST_R { + LEDC_TASK_SIG_OUT_DIS_CH3_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents LEDC_task_sig_out_dis_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_sig_out_dis_ch4_st(&self) -> LEDC_TASK_SIG_OUT_DIS_CH4_ST_R { + LEDC_TASK_SIG_OUT_DIS_CH4_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents LEDC_task_sig_out_dis_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_sig_out_dis_ch5_st(&self) -> LEDC_TASK_SIG_OUT_DIS_CH5_ST_R { + LEDC_TASK_SIG_OUT_DIS_CH5_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents LEDC_task_sig_out_dis_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_sig_out_dis_ch6_st(&self) -> LEDC_TASK_SIG_OUT_DIS_CH6_ST_R { + LEDC_TASK_SIG_OUT_DIS_CH6_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents LEDC_task_sig_out_dis_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_sig_out_dis_ch7_st(&self) -> LEDC_TASK_SIG_OUT_DIS_CH7_ST_R { + LEDC_TASK_SIG_OUT_DIS_CH7_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_ovf_cnt_rst_ch0_st(&self) -> LEDC_TASK_OVF_CNT_RST_CH0_ST_R { + LEDC_TASK_OVF_CNT_RST_CH0_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_ovf_cnt_rst_ch1_st(&self) -> LEDC_TASK_OVF_CNT_RST_CH1_ST_R { + LEDC_TASK_OVF_CNT_RST_CH1_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_ovf_cnt_rst_ch2_st(&self) -> LEDC_TASK_OVF_CNT_RST_CH2_ST_R { + LEDC_TASK_OVF_CNT_RST_CH2_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_ovf_cnt_rst_ch3_st(&self) -> LEDC_TASK_OVF_CNT_RST_CH3_ST_R { + LEDC_TASK_OVF_CNT_RST_CH3_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_ovf_cnt_rst_ch4_st(&self) -> LEDC_TASK_OVF_CNT_RST_CH4_ST_R { + LEDC_TASK_OVF_CNT_RST_CH4_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_ovf_cnt_rst_ch5_st(&self) -> LEDC_TASK_OVF_CNT_RST_CH5_ST_R { + LEDC_TASK_OVF_CNT_RST_CH5_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_ovf_cnt_rst_ch6_st(&self) -> LEDC_TASK_OVF_CNT_RST_CH6_ST_R { + LEDC_TASK_OVF_CNT_RST_CH6_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_ovf_cnt_rst_ch7_st(&self) -> LEDC_TASK_OVF_CNT_RST_CH7_ST_R { + LEDC_TASK_OVF_CNT_RST_CH7_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents LEDC_task_timer0_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer0_rst_st(&self) -> LEDC_TASK_TIMER0_RST_ST_R { + LEDC_TASK_TIMER0_RST_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents LEDC_task_timer1_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer1_rst_st(&self) -> LEDC_TASK_TIMER1_RST_ST_R { + LEDC_TASK_TIMER1_RST_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents LEDC_task_timer2_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer2_rst_st(&self) -> LEDC_TASK_TIMER2_RST_ST_R { + LEDC_TASK_TIMER2_RST_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents LEDC_task_timer3_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer3_rst_st(&self) -> LEDC_TASK_TIMER3_RST_ST_R { + LEDC_TASK_TIMER3_RST_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents LEDC_task_timer0_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer0_resume_st(&self) -> LEDC_TASK_TIMER0_RESUME_ST_R { + LEDC_TASK_TIMER0_RESUME_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents LEDC_task_timer1_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer1_resume_st(&self) -> LEDC_TASK_TIMER1_RESUME_ST_R { + LEDC_TASK_TIMER1_RESUME_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents LEDC_task_timer2_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer2_resume_st(&self) -> LEDC_TASK_TIMER2_RESUME_ST_R { + LEDC_TASK_TIMER2_RESUME_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents LEDC_task_timer3_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer3_resume_st(&self) -> LEDC_TASK_TIMER3_RESUME_ST_R { + LEDC_TASK_TIMER3_RESUME_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TASK_ST1") + .field( + "ledc_task_duty_scale_update_ch4_st", + &format_args!("{}", self.ledc_task_duty_scale_update_ch4_st().bit()), + ) + .field( + "ledc_task_duty_scale_update_ch5_st", + &format_args!("{}", self.ledc_task_duty_scale_update_ch5_st().bit()), + ) + .field( + "ledc_task_duty_scale_update_ch6_st", + &format_args!("{}", self.ledc_task_duty_scale_update_ch6_st().bit()), + ) + .field( + "ledc_task_duty_scale_update_ch7_st", + &format_args!("{}", self.ledc_task_duty_scale_update_ch7_st().bit()), + ) + .field( + "ledc_task_timer0_cap_st", + &format_args!("{}", self.ledc_task_timer0_cap_st().bit()), + ) + .field( + "ledc_task_timer1_cap_st", + &format_args!("{}", self.ledc_task_timer1_cap_st().bit()), + ) + .field( + "ledc_task_timer2_cap_st", + &format_args!("{}", self.ledc_task_timer2_cap_st().bit()), + ) + .field( + "ledc_task_timer3_cap_st", + &format_args!("{}", self.ledc_task_timer3_cap_st().bit()), + ) + .field( + "ledc_task_sig_out_dis_ch0_st", + &format_args!("{}", self.ledc_task_sig_out_dis_ch0_st().bit()), + ) + .field( + "ledc_task_sig_out_dis_ch1_st", + &format_args!("{}", self.ledc_task_sig_out_dis_ch1_st().bit()), + ) + .field( + "ledc_task_sig_out_dis_ch2_st", + &format_args!("{}", self.ledc_task_sig_out_dis_ch2_st().bit()), + ) + .field( + "ledc_task_sig_out_dis_ch3_st", + &format_args!("{}", self.ledc_task_sig_out_dis_ch3_st().bit()), + ) + .field( + "ledc_task_sig_out_dis_ch4_st", + &format_args!("{}", self.ledc_task_sig_out_dis_ch4_st().bit()), + ) + .field( + "ledc_task_sig_out_dis_ch5_st", + &format_args!("{}", self.ledc_task_sig_out_dis_ch5_st().bit()), + ) + .field( + "ledc_task_sig_out_dis_ch6_st", + &format_args!("{}", self.ledc_task_sig_out_dis_ch6_st().bit()), + ) + .field( + "ledc_task_sig_out_dis_ch7_st", + &format_args!("{}", self.ledc_task_sig_out_dis_ch7_st().bit()), + ) + .field( + "ledc_task_ovf_cnt_rst_ch0_st", + &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch0_st().bit()), + ) + .field( + "ledc_task_ovf_cnt_rst_ch1_st", + &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch1_st().bit()), + ) + .field( + "ledc_task_ovf_cnt_rst_ch2_st", + &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch2_st().bit()), + ) + .field( + "ledc_task_ovf_cnt_rst_ch3_st", + &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch3_st().bit()), + ) + .field( + "ledc_task_ovf_cnt_rst_ch4_st", + &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch4_st().bit()), + ) + .field( + "ledc_task_ovf_cnt_rst_ch5_st", + &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch5_st().bit()), + ) + .field( + "ledc_task_ovf_cnt_rst_ch6_st", + &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch6_st().bit()), + ) + .field( + "ledc_task_ovf_cnt_rst_ch7_st", + &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch7_st().bit()), + ) + .field( + "ledc_task_timer0_rst_st", + &format_args!("{}", self.ledc_task_timer0_rst_st().bit()), + ) + .field( + "ledc_task_timer1_rst_st", + &format_args!("{}", self.ledc_task_timer1_rst_st().bit()), + ) + .field( + "ledc_task_timer2_rst_st", + &format_args!("{}", self.ledc_task_timer2_rst_st().bit()), + ) + .field( + "ledc_task_timer3_rst_st", + &format_args!("{}", self.ledc_task_timer3_rst_st().bit()), + ) + .field( + "ledc_task_timer0_resume_st", + &format_args!("{}", self.ledc_task_timer0_resume_st().bit()), + ) + .field( + "ledc_task_timer1_resume_st", + &format_args!("{}", self.ledc_task_timer1_resume_st().bit()), + ) + .field( + "ledc_task_timer2_resume_st", + &format_args!("{}", self.ledc_task_timer2_resume_st().bit()), + ) + .field( + "ledc_task_timer3_resume_st", + &format_args!("{}", self.ledc_task_timer3_resume_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents LEDC_task_duty_scale_update_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch4_st( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents LEDC_task_duty_scale_update_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch5_st( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents LEDC_task_duty_scale_update_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch6_st( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents LEDC_task_duty_scale_update_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch7_st( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents LEDC_task_timer0_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer0_cap_st(&mut self) -> LEDC_TASK_TIMER0_CAP_ST_W { + LEDC_TASK_TIMER0_CAP_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents LEDC_task_timer1_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer1_cap_st(&mut self) -> LEDC_TASK_TIMER1_CAP_ST_W { + LEDC_TASK_TIMER1_CAP_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents LEDC_task_timer2_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer2_cap_st(&mut self) -> LEDC_TASK_TIMER2_CAP_ST_W { + LEDC_TASK_TIMER2_CAP_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents LEDC_task_timer3_cap trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer3_cap_st(&mut self) -> LEDC_TASK_TIMER3_CAP_ST_W { + LEDC_TASK_TIMER3_CAP_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents LEDC_task_sig_out_dis_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch0_st( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH0_ST_W { + LEDC_TASK_SIG_OUT_DIS_CH0_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents LEDC_task_sig_out_dis_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch1_st( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH1_ST_W { + LEDC_TASK_SIG_OUT_DIS_CH1_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents LEDC_task_sig_out_dis_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch2_st( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH2_ST_W { + LEDC_TASK_SIG_OUT_DIS_CH2_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents LEDC_task_sig_out_dis_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch3_st( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH3_ST_W { + LEDC_TASK_SIG_OUT_DIS_CH3_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents LEDC_task_sig_out_dis_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch4_st( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH4_ST_W { + LEDC_TASK_SIG_OUT_DIS_CH4_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents LEDC_task_sig_out_dis_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch5_st( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH5_ST_W { + LEDC_TASK_SIG_OUT_DIS_CH5_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents LEDC_task_sig_out_dis_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch6_st( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH6_ST_W { + LEDC_TASK_SIG_OUT_DIS_CH6_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents LEDC_task_sig_out_dis_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch7_st( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH7_ST_W { + LEDC_TASK_SIG_OUT_DIS_CH7_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch0_st( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH0_ST_W { + LEDC_TASK_OVF_CNT_RST_CH0_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch1_st( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH1_ST_W { + LEDC_TASK_OVF_CNT_RST_CH1_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch2_st( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH2_ST_W { + LEDC_TASK_OVF_CNT_RST_CH2_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch3_st( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH3_ST_W { + LEDC_TASK_OVF_CNT_RST_CH3_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch4_st( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH4_ST_W { + LEDC_TASK_OVF_CNT_RST_CH4_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch5_st( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH5_ST_W { + LEDC_TASK_OVF_CNT_RST_CH5_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch6_st( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH6_ST_W { + LEDC_TASK_OVF_CNT_RST_CH6_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch7_st( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH7_ST_W { + LEDC_TASK_OVF_CNT_RST_CH7_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents LEDC_task_timer0_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer0_rst_st(&mut self) -> LEDC_TASK_TIMER0_RST_ST_W { + LEDC_TASK_TIMER0_RST_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents LEDC_task_timer1_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer1_rst_st(&mut self) -> LEDC_TASK_TIMER1_RST_ST_W { + LEDC_TASK_TIMER1_RST_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents LEDC_task_timer2_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer2_rst_st(&mut self) -> LEDC_TASK_TIMER2_RST_ST_W { + LEDC_TASK_TIMER2_RST_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents LEDC_task_timer3_rst trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer3_rst_st(&mut self) -> LEDC_TASK_TIMER3_RST_ST_W { + LEDC_TASK_TIMER3_RST_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents LEDC_task_timer0_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer0_resume_st(&mut self) -> LEDC_TASK_TIMER0_RESUME_ST_W { + LEDC_TASK_TIMER0_RESUME_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents LEDC_task_timer1_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer1_resume_st(&mut self) -> LEDC_TASK_TIMER1_RESUME_ST_W { + LEDC_TASK_TIMER1_RESUME_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents LEDC_task_timer2_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer2_resume_st(&mut self) -> LEDC_TASK_TIMER2_RESUME_ST_W { + LEDC_TASK_TIMER2_RESUME_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents LEDC_task_timer3_resume trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer3_resume_st(&mut self) -> LEDC_TASK_TIMER3_RESUME_ST_W { + LEDC_TASK_TIMER3_RESUME_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST1_SPEC; +impl crate::RegisterSpec for TASK_ST1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`task_st1::R`](R) reader structure"] +impl crate::Readable for TASK_ST1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`task_st1::W`](W) writer structure"] +impl crate::Writable for TASK_ST1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST1 to value 0"] +impl crate::Resettable for TASK_ST1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st1_clr.rs b/esp32p4/src/soc_etm/task_st1_clr.rs new file mode 100644 index 0000000000..8799edec29 --- /dev/null +++ b/esp32p4/src/soc_etm/task_st1_clr.rs @@ -0,0 +1,354 @@ +#[doc = "Register `TASK_ST1_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR` writer - Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR` writer - Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR` writer - Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR` writer - Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER0_CAP_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER0_CAP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER1_CAP_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER1_CAP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER2_CAP_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER2_CAP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER3_CAP_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER3_CAP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR` writer - Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR` writer - Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR` writer - Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR` writer - Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR` writer - Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR` writer - Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR` writer - Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR` writer - Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR` writer - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR` writer - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR` writer - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR` writer - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR` writer - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR` writer - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR` writer - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR` writer - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER0_RST_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER0_RST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER1_RST_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER1_RST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER2_RST_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER2_RST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER3_RST_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER3_RST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER0_RESUME_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER0_RESUME_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER1_RESUME_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER1_RESUME_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER2_RESUME_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER2_RESUME_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER3_RESUME_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER3_RESUME_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch4_st_clr( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch5_st_clr( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch6_st_clr( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_duty_scale_update_ch7_st_clr( + &mut self, + ) -> LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_W { + LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer0_cap_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER0_CAP_ST_CLR_W { + LEDC_TASK_TIMER0_CAP_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer1_cap_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER1_CAP_ST_CLR_W { + LEDC_TASK_TIMER1_CAP_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer2_cap_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER2_CAP_ST_CLR_W { + LEDC_TASK_TIMER2_CAP_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer3_cap_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER3_CAP_ST_CLR_W { + LEDC_TASK_TIMER3_CAP_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch0_st_clr( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_W { + LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch1_st_clr( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_W { + LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch2_st_clr( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_W { + LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch3_st_clr( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_W { + LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch4_st_clr( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_W { + LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch5_st_clr( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_W { + LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch6_st_clr( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_W { + LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_sig_out_dis_ch7_st_clr( + &mut self, + ) -> LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_W { + LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch0_st_clr( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_W { + LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch1_st_clr( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_W { + LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch2_st_clr( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_W { + LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch3_st_clr( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_W { + LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch4_st_clr( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_W { + LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch5_st_clr( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_W { + LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch6_st_clr( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_W { + LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_ovf_cnt_rst_ch7_st_clr( + &mut self, + ) -> LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_W { + LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer0_rst_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER0_RST_ST_CLR_W { + LEDC_TASK_TIMER0_RST_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer1_rst_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER1_RST_ST_CLR_W { + LEDC_TASK_TIMER1_RST_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer2_rst_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER2_RST_ST_CLR_W { + LEDC_TASK_TIMER2_RST_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer3_rst_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER3_RST_ST_CLR_W { + LEDC_TASK_TIMER3_RST_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer0_resume_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER0_RESUME_ST_CLR_W { + LEDC_TASK_TIMER0_RESUME_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer1_resume_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER1_RESUME_ST_CLR_W { + LEDC_TASK_TIMER1_RESUME_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer2_resume_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER2_RESUME_ST_CLR_W { + LEDC_TASK_TIMER2_RESUME_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer3_resume_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER3_RESUME_ST_CLR_W { + LEDC_TASK_TIMER3_RESUME_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st1_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST1_CLR_SPEC; +impl crate::RegisterSpec for TASK_ST1_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`task_st1_clr::W`](W) writer structure"] +impl crate::Writable for TASK_ST1_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST1_CLR to value 0"] +impl crate::Resettable for TASK_ST1_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st2.rs b/esp32p4/src/soc_etm/task_st2.rs new file mode 100644 index 0000000000..d8807a9f7e --- /dev/null +++ b/esp32p4/src/soc_etm/task_st2.rs @@ -0,0 +1,709 @@ +#[doc = "Register `TASK_ST2` reader"] +pub type R = crate::R; +#[doc = "Register `TASK_ST2` writer"] +pub type W = crate::W; +#[doc = "Field `LEDC_TASK_TIMER0_PAUSE_ST` reader - Represents LEDC_task_timer0_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER0_PAUSE_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER0_PAUSE_ST` writer - Represents LEDC_task_timer0_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER0_PAUSE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER1_PAUSE_ST` reader - Represents LEDC_task_timer1_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER1_PAUSE_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER1_PAUSE_ST` writer - Represents LEDC_task_timer1_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER1_PAUSE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER2_PAUSE_ST` reader - Represents LEDC_task_timer2_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER2_PAUSE_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER2_PAUSE_ST` writer - Represents LEDC_task_timer2_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER2_PAUSE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER3_PAUSE_ST` reader - Represents LEDC_task_timer3_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER3_PAUSE_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_TIMER3_PAUSE_ST` writer - Represents LEDC_task_timer3_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_TIMER3_PAUSE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH0_ST` reader - Represents LEDC_task_gamma_restart_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH0_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH0_ST` writer - Represents LEDC_task_gamma_restart_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH1_ST` reader - Represents LEDC_task_gamma_restart_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH1_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH1_ST` writer - Represents LEDC_task_gamma_restart_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH2_ST` reader - Represents LEDC_task_gamma_restart_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH2_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH2_ST` writer - Represents LEDC_task_gamma_restart_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH3_ST` reader - Represents LEDC_task_gamma_restart_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH3_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH3_ST` writer - Represents LEDC_task_gamma_restart_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH4_ST` reader - Represents LEDC_task_gamma_restart_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH4_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH4_ST` writer - Represents LEDC_task_gamma_restart_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH5_ST` reader - Represents LEDC_task_gamma_restart_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH5_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH5_ST` writer - Represents LEDC_task_gamma_restart_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH5_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH6_ST` reader - Represents LEDC_task_gamma_restart_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH6_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH6_ST` writer - Represents LEDC_task_gamma_restart_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH6_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH7_ST` reader - Represents LEDC_task_gamma_restart_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH7_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH7_ST` writer - Represents LEDC_task_gamma_restart_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESTART_CH7_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH0_ST` reader - Represents LEDC_task_gamma_pause_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH0_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH0_ST` writer - Represents LEDC_task_gamma_pause_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH1_ST` reader - Represents LEDC_task_gamma_pause_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH1_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH1_ST` writer - Represents LEDC_task_gamma_pause_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH2_ST` reader - Represents LEDC_task_gamma_pause_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH2_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH2_ST` writer - Represents LEDC_task_gamma_pause_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH3_ST` reader - Represents LEDC_task_gamma_pause_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH3_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH3_ST` writer - Represents LEDC_task_gamma_pause_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH4_ST` reader - Represents LEDC_task_gamma_pause_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH4_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH4_ST` writer - Represents LEDC_task_gamma_pause_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH5_ST` reader - Represents LEDC_task_gamma_pause_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH5_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH5_ST` writer - Represents LEDC_task_gamma_pause_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH5_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH6_ST` reader - Represents LEDC_task_gamma_pause_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH6_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH6_ST` writer - Represents LEDC_task_gamma_pause_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH6_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH7_ST` reader - Represents LEDC_task_gamma_pause_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH7_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH7_ST` writer - Represents LEDC_task_gamma_pause_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_PAUSE_CH7_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH0_ST` reader - Represents LEDC_task_gamma_resume_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH0_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH0_ST` writer - Represents LEDC_task_gamma_resume_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH1_ST` reader - Represents LEDC_task_gamma_resume_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH1_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH1_ST` writer - Represents LEDC_task_gamma_resume_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH2_ST` reader - Represents LEDC_task_gamma_resume_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH2_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH2_ST` writer - Represents LEDC_task_gamma_resume_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH3_ST` reader - Represents LEDC_task_gamma_resume_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH3_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH3_ST` writer - Represents LEDC_task_gamma_resume_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH4_ST` reader - Represents LEDC_task_gamma_resume_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH4_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH4_ST` writer - Represents LEDC_task_gamma_resume_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH4_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH5_ST` reader - Represents LEDC_task_gamma_resume_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH5_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH5_ST` writer - Represents LEDC_task_gamma_resume_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH5_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH6_ST` reader - Represents LEDC_task_gamma_resume_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH6_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH6_ST` writer - Represents LEDC_task_gamma_resume_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH6_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH7_ST` reader - Represents LEDC_task_gamma_resume_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH7_ST_R = crate::BitReader; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH7_ST` writer - Represents LEDC_task_gamma_resume_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type LEDC_TASK_GAMMA_RESUME_CH7_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_START_TIMER0_ST` reader - Represents TG0_task_cnt_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_START_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG0_TASK_CNT_START_TIMER0_ST` writer - Represents TG0_task_cnt_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_START_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_ALARM_START_TIMER0_ST` reader - Represents TG0_task_alarm_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_ALARM_START_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG0_TASK_ALARM_START_TIMER0_ST` writer - Represents TG0_task_alarm_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_ALARM_START_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_STOP_TIMER0_ST` reader - Represents TG0_task_cnt_stop_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_STOP_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG0_TASK_CNT_STOP_TIMER0_ST` writer - Represents TG0_task_cnt_stop_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_STOP_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_RELOAD_TIMER0_ST` reader - Represents TG0_task_cnt_reload_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_RELOAD_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG0_TASK_CNT_RELOAD_TIMER0_ST` writer - Represents TG0_task_cnt_reload_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_RELOAD_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents LEDC_task_timer0_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer0_pause_st(&self) -> LEDC_TASK_TIMER0_PAUSE_ST_R { + LEDC_TASK_TIMER0_PAUSE_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents LEDC_task_timer1_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer1_pause_st(&self) -> LEDC_TASK_TIMER1_PAUSE_ST_R { + LEDC_TASK_TIMER1_PAUSE_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents LEDC_task_timer2_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer2_pause_st(&self) -> LEDC_TASK_TIMER2_PAUSE_ST_R { + LEDC_TASK_TIMER2_PAUSE_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents LEDC_task_timer3_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_timer3_pause_st(&self) -> LEDC_TASK_TIMER3_PAUSE_ST_R { + LEDC_TASK_TIMER3_PAUSE_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents LEDC_task_gamma_restart_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_restart_ch0_st(&self) -> LEDC_TASK_GAMMA_RESTART_CH0_ST_R { + LEDC_TASK_GAMMA_RESTART_CH0_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents LEDC_task_gamma_restart_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_restart_ch1_st(&self) -> LEDC_TASK_GAMMA_RESTART_CH1_ST_R { + LEDC_TASK_GAMMA_RESTART_CH1_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents LEDC_task_gamma_restart_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_restart_ch2_st(&self) -> LEDC_TASK_GAMMA_RESTART_CH2_ST_R { + LEDC_TASK_GAMMA_RESTART_CH2_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents LEDC_task_gamma_restart_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_restart_ch3_st(&self) -> LEDC_TASK_GAMMA_RESTART_CH3_ST_R { + LEDC_TASK_GAMMA_RESTART_CH3_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents LEDC_task_gamma_restart_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_restart_ch4_st(&self) -> LEDC_TASK_GAMMA_RESTART_CH4_ST_R { + LEDC_TASK_GAMMA_RESTART_CH4_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents LEDC_task_gamma_restart_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_restart_ch5_st(&self) -> LEDC_TASK_GAMMA_RESTART_CH5_ST_R { + LEDC_TASK_GAMMA_RESTART_CH5_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents LEDC_task_gamma_restart_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_restart_ch6_st(&self) -> LEDC_TASK_GAMMA_RESTART_CH6_ST_R { + LEDC_TASK_GAMMA_RESTART_CH6_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents LEDC_task_gamma_restart_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_restart_ch7_st(&self) -> LEDC_TASK_GAMMA_RESTART_CH7_ST_R { + LEDC_TASK_GAMMA_RESTART_CH7_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents LEDC_task_gamma_pause_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_pause_ch0_st(&self) -> LEDC_TASK_GAMMA_PAUSE_CH0_ST_R { + LEDC_TASK_GAMMA_PAUSE_CH0_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents LEDC_task_gamma_pause_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_pause_ch1_st(&self) -> LEDC_TASK_GAMMA_PAUSE_CH1_ST_R { + LEDC_TASK_GAMMA_PAUSE_CH1_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents LEDC_task_gamma_pause_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_pause_ch2_st(&self) -> LEDC_TASK_GAMMA_PAUSE_CH2_ST_R { + LEDC_TASK_GAMMA_PAUSE_CH2_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents LEDC_task_gamma_pause_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_pause_ch3_st(&self) -> LEDC_TASK_GAMMA_PAUSE_CH3_ST_R { + LEDC_TASK_GAMMA_PAUSE_CH3_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents LEDC_task_gamma_pause_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_pause_ch4_st(&self) -> LEDC_TASK_GAMMA_PAUSE_CH4_ST_R { + LEDC_TASK_GAMMA_PAUSE_CH4_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents LEDC_task_gamma_pause_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_pause_ch5_st(&self) -> LEDC_TASK_GAMMA_PAUSE_CH5_ST_R { + LEDC_TASK_GAMMA_PAUSE_CH5_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents LEDC_task_gamma_pause_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_pause_ch6_st(&self) -> LEDC_TASK_GAMMA_PAUSE_CH6_ST_R { + LEDC_TASK_GAMMA_PAUSE_CH6_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents LEDC_task_gamma_pause_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_pause_ch7_st(&self) -> LEDC_TASK_GAMMA_PAUSE_CH7_ST_R { + LEDC_TASK_GAMMA_PAUSE_CH7_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents LEDC_task_gamma_resume_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_resume_ch0_st(&self) -> LEDC_TASK_GAMMA_RESUME_CH0_ST_R { + LEDC_TASK_GAMMA_RESUME_CH0_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents LEDC_task_gamma_resume_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_resume_ch1_st(&self) -> LEDC_TASK_GAMMA_RESUME_CH1_ST_R { + LEDC_TASK_GAMMA_RESUME_CH1_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents LEDC_task_gamma_resume_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_resume_ch2_st(&self) -> LEDC_TASK_GAMMA_RESUME_CH2_ST_R { + LEDC_TASK_GAMMA_RESUME_CH2_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents LEDC_task_gamma_resume_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_resume_ch3_st(&self) -> LEDC_TASK_GAMMA_RESUME_CH3_ST_R { + LEDC_TASK_GAMMA_RESUME_CH3_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents LEDC_task_gamma_resume_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_resume_ch4_st(&self) -> LEDC_TASK_GAMMA_RESUME_CH4_ST_R { + LEDC_TASK_GAMMA_RESUME_CH4_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents LEDC_task_gamma_resume_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_resume_ch5_st(&self) -> LEDC_TASK_GAMMA_RESUME_CH5_ST_R { + LEDC_TASK_GAMMA_RESUME_CH5_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents LEDC_task_gamma_resume_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_resume_ch6_st(&self) -> LEDC_TASK_GAMMA_RESUME_CH6_ST_R { + LEDC_TASK_GAMMA_RESUME_CH6_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents LEDC_task_gamma_resume_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ledc_task_gamma_resume_ch7_st(&self) -> LEDC_TASK_GAMMA_RESUME_CH7_ST_R { + LEDC_TASK_GAMMA_RESUME_CH7_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents TG0_task_cnt_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_task_cnt_start_timer0_st(&self) -> TG0_TASK_CNT_START_TIMER0_ST_R { + TG0_TASK_CNT_START_TIMER0_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents TG0_task_alarm_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_task_alarm_start_timer0_st(&self) -> TG0_TASK_ALARM_START_TIMER0_ST_R { + TG0_TASK_ALARM_START_TIMER0_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents TG0_task_cnt_stop_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_task_cnt_stop_timer0_st(&self) -> TG0_TASK_CNT_STOP_TIMER0_ST_R { + TG0_TASK_CNT_STOP_TIMER0_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents TG0_task_cnt_reload_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_task_cnt_reload_timer0_st(&self) -> TG0_TASK_CNT_RELOAD_TIMER0_ST_R { + TG0_TASK_CNT_RELOAD_TIMER0_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TASK_ST2") + .field( + "ledc_task_timer0_pause_st", + &format_args!("{}", self.ledc_task_timer0_pause_st().bit()), + ) + .field( + "ledc_task_timer1_pause_st", + &format_args!("{}", self.ledc_task_timer1_pause_st().bit()), + ) + .field( + "ledc_task_timer2_pause_st", + &format_args!("{}", self.ledc_task_timer2_pause_st().bit()), + ) + .field( + "ledc_task_timer3_pause_st", + &format_args!("{}", self.ledc_task_timer3_pause_st().bit()), + ) + .field( + "ledc_task_gamma_restart_ch0_st", + &format_args!("{}", self.ledc_task_gamma_restart_ch0_st().bit()), + ) + .field( + "ledc_task_gamma_restart_ch1_st", + &format_args!("{}", self.ledc_task_gamma_restart_ch1_st().bit()), + ) + .field( + "ledc_task_gamma_restart_ch2_st", + &format_args!("{}", self.ledc_task_gamma_restart_ch2_st().bit()), + ) + .field( + "ledc_task_gamma_restart_ch3_st", + &format_args!("{}", self.ledc_task_gamma_restart_ch3_st().bit()), + ) + .field( + "ledc_task_gamma_restart_ch4_st", + &format_args!("{}", self.ledc_task_gamma_restart_ch4_st().bit()), + ) + .field( + "ledc_task_gamma_restart_ch5_st", + &format_args!("{}", self.ledc_task_gamma_restart_ch5_st().bit()), + ) + .field( + "ledc_task_gamma_restart_ch6_st", + &format_args!("{}", self.ledc_task_gamma_restart_ch6_st().bit()), + ) + .field( + "ledc_task_gamma_restart_ch7_st", + &format_args!("{}", self.ledc_task_gamma_restart_ch7_st().bit()), + ) + .field( + "ledc_task_gamma_pause_ch0_st", + &format_args!("{}", self.ledc_task_gamma_pause_ch0_st().bit()), + ) + .field( + "ledc_task_gamma_pause_ch1_st", + &format_args!("{}", self.ledc_task_gamma_pause_ch1_st().bit()), + ) + .field( + "ledc_task_gamma_pause_ch2_st", + &format_args!("{}", self.ledc_task_gamma_pause_ch2_st().bit()), + ) + .field( + "ledc_task_gamma_pause_ch3_st", + &format_args!("{}", self.ledc_task_gamma_pause_ch3_st().bit()), + ) + .field( + "ledc_task_gamma_pause_ch4_st", + &format_args!("{}", self.ledc_task_gamma_pause_ch4_st().bit()), + ) + .field( + "ledc_task_gamma_pause_ch5_st", + &format_args!("{}", self.ledc_task_gamma_pause_ch5_st().bit()), + ) + .field( + "ledc_task_gamma_pause_ch6_st", + &format_args!("{}", self.ledc_task_gamma_pause_ch6_st().bit()), + ) + .field( + "ledc_task_gamma_pause_ch7_st", + &format_args!("{}", self.ledc_task_gamma_pause_ch7_st().bit()), + ) + .field( + "ledc_task_gamma_resume_ch0_st", + &format_args!("{}", self.ledc_task_gamma_resume_ch0_st().bit()), + ) + .field( + "ledc_task_gamma_resume_ch1_st", + &format_args!("{}", self.ledc_task_gamma_resume_ch1_st().bit()), + ) + .field( + "ledc_task_gamma_resume_ch2_st", + &format_args!("{}", self.ledc_task_gamma_resume_ch2_st().bit()), + ) + .field( + "ledc_task_gamma_resume_ch3_st", + &format_args!("{}", self.ledc_task_gamma_resume_ch3_st().bit()), + ) + .field( + "ledc_task_gamma_resume_ch4_st", + &format_args!("{}", self.ledc_task_gamma_resume_ch4_st().bit()), + ) + .field( + "ledc_task_gamma_resume_ch5_st", + &format_args!("{}", self.ledc_task_gamma_resume_ch5_st().bit()), + ) + .field( + "ledc_task_gamma_resume_ch6_st", + &format_args!("{}", self.ledc_task_gamma_resume_ch6_st().bit()), + ) + .field( + "ledc_task_gamma_resume_ch7_st", + &format_args!("{}", self.ledc_task_gamma_resume_ch7_st().bit()), + ) + .field( + "tg0_task_cnt_start_timer0_st", + &format_args!("{}", self.tg0_task_cnt_start_timer0_st().bit()), + ) + .field( + "tg0_task_alarm_start_timer0_st", + &format_args!("{}", self.tg0_task_alarm_start_timer0_st().bit()), + ) + .field( + "tg0_task_cnt_stop_timer0_st", + &format_args!("{}", self.tg0_task_cnt_stop_timer0_st().bit()), + ) + .field( + "tg0_task_cnt_reload_timer0_st", + &format_args!("{}", self.tg0_task_cnt_reload_timer0_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents LEDC_task_timer0_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer0_pause_st(&mut self) -> LEDC_TASK_TIMER0_PAUSE_ST_W { + LEDC_TASK_TIMER0_PAUSE_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents LEDC_task_timer1_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer1_pause_st(&mut self) -> LEDC_TASK_TIMER1_PAUSE_ST_W { + LEDC_TASK_TIMER1_PAUSE_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents LEDC_task_timer2_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer2_pause_st(&mut self) -> LEDC_TASK_TIMER2_PAUSE_ST_W { + LEDC_TASK_TIMER2_PAUSE_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents LEDC_task_timer3_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer3_pause_st(&mut self) -> LEDC_TASK_TIMER3_PAUSE_ST_W { + LEDC_TASK_TIMER3_PAUSE_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents LEDC_task_gamma_restart_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch0_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH0_ST_W { + LEDC_TASK_GAMMA_RESTART_CH0_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents LEDC_task_gamma_restart_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch1_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH1_ST_W { + LEDC_TASK_GAMMA_RESTART_CH1_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents LEDC_task_gamma_restart_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch2_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH2_ST_W { + LEDC_TASK_GAMMA_RESTART_CH2_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents LEDC_task_gamma_restart_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch3_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH3_ST_W { + LEDC_TASK_GAMMA_RESTART_CH3_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents LEDC_task_gamma_restart_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch4_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH4_ST_W { + LEDC_TASK_GAMMA_RESTART_CH4_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents LEDC_task_gamma_restart_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch5_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH5_ST_W { + LEDC_TASK_GAMMA_RESTART_CH5_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents LEDC_task_gamma_restart_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch6_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH6_ST_W { + LEDC_TASK_GAMMA_RESTART_CH6_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents LEDC_task_gamma_restart_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch7_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH7_ST_W { + LEDC_TASK_GAMMA_RESTART_CH7_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents LEDC_task_gamma_pause_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch0_st( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH0_ST_W { + LEDC_TASK_GAMMA_PAUSE_CH0_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents LEDC_task_gamma_pause_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch1_st( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH1_ST_W { + LEDC_TASK_GAMMA_PAUSE_CH1_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents LEDC_task_gamma_pause_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch2_st( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH2_ST_W { + LEDC_TASK_GAMMA_PAUSE_CH2_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents LEDC_task_gamma_pause_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch3_st( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH3_ST_W { + LEDC_TASK_GAMMA_PAUSE_CH3_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents LEDC_task_gamma_pause_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch4_st( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH4_ST_W { + LEDC_TASK_GAMMA_PAUSE_CH4_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents LEDC_task_gamma_pause_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch5_st( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH5_ST_W { + LEDC_TASK_GAMMA_PAUSE_CH5_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents LEDC_task_gamma_pause_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch6_st( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH6_ST_W { + LEDC_TASK_GAMMA_PAUSE_CH6_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents LEDC_task_gamma_pause_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch7_st( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH7_ST_W { + LEDC_TASK_GAMMA_PAUSE_CH7_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents LEDC_task_gamma_resume_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch0_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH0_ST_W { + LEDC_TASK_GAMMA_RESUME_CH0_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents LEDC_task_gamma_resume_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch1_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH1_ST_W { + LEDC_TASK_GAMMA_RESUME_CH1_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents LEDC_task_gamma_resume_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch2_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH2_ST_W { + LEDC_TASK_GAMMA_RESUME_CH2_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents LEDC_task_gamma_resume_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch3_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH3_ST_W { + LEDC_TASK_GAMMA_RESUME_CH3_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents LEDC_task_gamma_resume_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch4_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH4_ST_W { + LEDC_TASK_GAMMA_RESUME_CH4_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents LEDC_task_gamma_resume_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch5_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH5_ST_W { + LEDC_TASK_GAMMA_RESUME_CH5_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents LEDC_task_gamma_resume_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch6_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH6_ST_W { + LEDC_TASK_GAMMA_RESUME_CH6_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents LEDC_task_gamma_resume_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch7_st( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH7_ST_W { + LEDC_TASK_GAMMA_RESUME_CH7_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents TG0_task_cnt_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_start_timer0_st( + &mut self, + ) -> TG0_TASK_CNT_START_TIMER0_ST_W { + TG0_TASK_CNT_START_TIMER0_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents TG0_task_alarm_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_task_alarm_start_timer0_st( + &mut self, + ) -> TG0_TASK_ALARM_START_TIMER0_ST_W { + TG0_TASK_ALARM_START_TIMER0_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents TG0_task_cnt_stop_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_stop_timer0_st(&mut self) -> TG0_TASK_CNT_STOP_TIMER0_ST_W { + TG0_TASK_CNT_STOP_TIMER0_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents TG0_task_cnt_reload_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_reload_timer0_st( + &mut self, + ) -> TG0_TASK_CNT_RELOAD_TIMER0_ST_W { + TG0_TASK_CNT_RELOAD_TIMER0_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST2_SPEC; +impl crate::RegisterSpec for TASK_ST2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`task_st2::R`](R) reader structure"] +impl crate::Readable for TASK_ST2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`task_st2::W`](W) writer structure"] +impl crate::Writable for TASK_ST2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST2 to value 0"] +impl crate::Resettable for TASK_ST2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st2_clr.rs b/esp32p4/src/soc_etm/task_st2_clr.rs new file mode 100644 index 0000000000..86e8db37a6 --- /dev/null +++ b/esp32p4/src/soc_etm/task_st2_clr.rs @@ -0,0 +1,354 @@ +#[doc = "Register `TASK_ST2_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `LEDC_TASK_TIMER0_PAUSE_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER0_PAUSE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER1_PAUSE_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER1_PAUSE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER2_PAUSE_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER2_PAUSE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_TIMER3_PAUSE_ST_CLR` writer - Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_TIMER3_PAUSE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR` writer - Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_START_TIMER0_ST_CLR` writer - Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_TASK_CNT_START_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_ALARM_START_TIMER0_ST_CLR` writer - Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_TASK_ALARM_START_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_STOP_TIMER0_ST_CLR` writer - Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_TASK_CNT_STOP_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR` writer - Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer0_pause_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER0_PAUSE_ST_CLR_W { + LEDC_TASK_TIMER0_PAUSE_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer1_pause_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER1_PAUSE_ST_CLR_W { + LEDC_TASK_TIMER1_PAUSE_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer2_pause_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER2_PAUSE_ST_CLR_W { + LEDC_TASK_TIMER2_PAUSE_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_timer3_pause_st_clr( + &mut self, + ) -> LEDC_TASK_TIMER3_PAUSE_ST_CLR_W { + LEDC_TASK_TIMER3_PAUSE_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch0_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_W { + LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch1_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_W { + LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch2_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_W { + LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch3_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_W { + LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch4_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_W { + LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch5_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_W { + LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch6_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_W { + LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_restart_ch7_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_W { + LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch0_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_W { + LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch1_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_W { + LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch2_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_W { + LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch3_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_W { + LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch4_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_W { + LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch5_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_W { + LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch6_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_W { + LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_pause_ch7_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_W { + LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch0_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_W { + LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch1_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_W { + LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch2_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_W { + LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch3_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_W { + LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch4_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_W { + LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch5_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_W { + LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch6_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_W { + LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ledc_task_gamma_resume_ch7_st_clr( + &mut self, + ) -> LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_W { + LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_start_timer0_st_clr( + &mut self, + ) -> TG0_TASK_CNT_START_TIMER0_ST_CLR_W { + TG0_TASK_CNT_START_TIMER0_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_task_alarm_start_timer0_st_clr( + &mut self, + ) -> TG0_TASK_ALARM_START_TIMER0_ST_CLR_W { + TG0_TASK_ALARM_START_TIMER0_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_stop_timer0_st_clr( + &mut self, + ) -> TG0_TASK_CNT_STOP_TIMER0_ST_CLR_W { + TG0_TASK_CNT_STOP_TIMER0_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_reload_timer0_st_clr( + &mut self, + ) -> TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_W { + TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st2_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST2_CLR_SPEC; +impl crate::RegisterSpec for TASK_ST2_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`task_st2_clr::W`](W) writer structure"] +impl crate::Writable for TASK_ST2_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST2_CLR to value 0"] +impl crate::Resettable for TASK_ST2_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st3.rs b/esp32p4/src/soc_etm/task_st3.rs new file mode 100644 index 0000000000..22b00e00fa --- /dev/null +++ b/esp32p4/src/soc_etm/task_st3.rs @@ -0,0 +1,679 @@ +#[doc = "Register `TASK_ST3` reader"] +pub type R = crate::R; +#[doc = "Register `TASK_ST3` writer"] +pub type W = crate::W; +#[doc = "Field `TG0_TASK_CNT_CAP_TIMER0_ST` reader - Represents TG0_task_cnt_cap_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_CAP_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG0_TASK_CNT_CAP_TIMER0_ST` writer - Represents TG0_task_cnt_cap_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_CAP_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_START_TIMER1_ST` reader - Represents TG0_task_cnt_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_START_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG0_TASK_CNT_START_TIMER1_ST` writer - Represents TG0_task_cnt_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_START_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_ALARM_START_TIMER1_ST` reader - Represents TG0_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_ALARM_START_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG0_TASK_ALARM_START_TIMER1_ST` writer - Represents TG0_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_ALARM_START_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_STOP_TIMER1_ST` reader - Represents TG0_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_STOP_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG0_TASK_CNT_STOP_TIMER1_ST` writer - Represents TG0_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_STOP_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_RELOAD_TIMER1_ST` reader - Represents TG0_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_RELOAD_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG0_TASK_CNT_RELOAD_TIMER1_ST` writer - Represents TG0_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_RELOAD_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_CAP_TIMER1_ST` reader - Represents TG0_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_CAP_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG0_TASK_CNT_CAP_TIMER1_ST` writer - Represents TG0_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG0_TASK_CNT_CAP_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_START_TIMER0_ST` reader - Represents TG1_task_cnt_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_START_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG1_TASK_CNT_START_TIMER0_ST` writer - Represents TG1_task_cnt_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_START_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_ALARM_START_TIMER0_ST` reader - Represents TG1_task_alarm_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_ALARM_START_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG1_TASK_ALARM_START_TIMER0_ST` writer - Represents TG1_task_alarm_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_ALARM_START_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_STOP_TIMER0_ST` reader - Represents TG1_task_cnt_stop_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_STOP_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG1_TASK_CNT_STOP_TIMER0_ST` writer - Represents TG1_task_cnt_stop_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_STOP_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_RELOAD_TIMER0_ST` reader - Represents TG1_task_cnt_reload_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_RELOAD_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG1_TASK_CNT_RELOAD_TIMER0_ST` writer - Represents TG1_task_cnt_reload_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_RELOAD_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_CAP_TIMER0_ST` reader - Represents TG1_task_cnt_cap_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_CAP_TIMER0_ST_R = crate::BitReader; +#[doc = "Field `TG1_TASK_CNT_CAP_TIMER0_ST` writer - Represents TG1_task_cnt_cap_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_CAP_TIMER0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_START_TIMER1_ST` reader - Represents TG1_task_cnt_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_START_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG1_TASK_CNT_START_TIMER1_ST` writer - Represents TG1_task_cnt_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_START_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_ALARM_START_TIMER1_ST` reader - Represents TG1_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_ALARM_START_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG1_TASK_ALARM_START_TIMER1_ST` writer - Represents TG1_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_ALARM_START_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_STOP_TIMER1_ST` reader - Represents TG1_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_STOP_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG1_TASK_CNT_STOP_TIMER1_ST` writer - Represents TG1_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_STOP_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_RELOAD_TIMER1_ST` reader - Represents TG1_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_RELOAD_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG1_TASK_CNT_RELOAD_TIMER1_ST` writer - Represents TG1_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_RELOAD_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_CAP_TIMER1_ST` reader - Represents TG1_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_CAP_TIMER1_ST_R = crate::BitReader; +#[doc = "Field `TG1_TASK_CNT_CAP_TIMER1_ST` writer - Represents TG1_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TG1_TASK_CNT_CAP_TIMER1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR0_A_UP_ST` reader - Represents MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR0_A_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CMPR0_A_UP_ST` writer - Represents MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR0_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR1_A_UP_ST` reader - Represents MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR1_A_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CMPR1_A_UP_ST` writer - Represents MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR1_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR2_A_UP_ST` reader - Represents MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR2_A_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CMPR2_A_UP_ST` writer - Represents MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR2_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR0_B_UP_ST` reader - Represents MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR0_B_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CMPR0_B_UP_ST` writer - Represents MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR0_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR1_B_UP_ST` reader - Represents MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR1_B_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CMPR1_B_UP_ST` writer - Represents MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR1_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR2_B_UP_ST` reader - Represents MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR2_B_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CMPR2_B_UP_ST` writer - Represents MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CMPR2_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_GEN_STOP_ST` reader - Represents MCPWM0_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_GEN_STOP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_GEN_STOP_ST` writer - Represents MCPWM0_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_GEN_STOP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER0_SYN_ST` reader - Represents MCPWM0_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER0_SYN_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_TIMER0_SYN_ST` writer - Represents MCPWM0_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER0_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER1_SYN_ST` reader - Represents MCPWM0_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER1_SYN_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_TIMER1_SYN_ST` writer - Represents MCPWM0_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER1_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER2_SYN_ST` reader - Represents MCPWM0_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER2_SYN_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_TIMER2_SYN_ST` writer - Represents MCPWM0_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER2_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER0_PERIOD_UP_ST` reader - Represents MCPWM0_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER0_PERIOD_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_TIMER0_PERIOD_UP_ST` writer - Represents MCPWM0_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER0_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER1_PERIOD_UP_ST` reader - Represents MCPWM0_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER1_PERIOD_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_TIMER1_PERIOD_UP_ST` writer - Represents MCPWM0_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER1_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER2_PERIOD_UP_ST` reader - Represents MCPWM0_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER2_PERIOD_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_TIMER2_PERIOD_UP_ST` writer - Represents MCPWM0_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TIMER2_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TZ0_OST_ST` reader - Represents MCPWM0_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TZ0_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_TZ0_OST_ST` writer - Represents MCPWM0_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TZ0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TZ1_OST_ST` reader - Represents MCPWM0_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TZ1_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_TZ1_OST_ST` writer - Represents MCPWM0_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TZ1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TZ2_OST_ST` reader - Represents MCPWM0_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TZ2_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_TZ2_OST_ST` writer - Represents MCPWM0_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_TZ2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents TG0_task_cnt_cap_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_task_cnt_cap_timer0_st(&self) -> TG0_TASK_CNT_CAP_TIMER0_ST_R { + TG0_TASK_CNT_CAP_TIMER0_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents TG0_task_cnt_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_task_cnt_start_timer1_st(&self) -> TG0_TASK_CNT_START_TIMER1_ST_R { + TG0_TASK_CNT_START_TIMER1_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents TG0_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_task_alarm_start_timer1_st(&self) -> TG0_TASK_ALARM_START_TIMER1_ST_R { + TG0_TASK_ALARM_START_TIMER1_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents TG0_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_task_cnt_stop_timer1_st(&self) -> TG0_TASK_CNT_STOP_TIMER1_ST_R { + TG0_TASK_CNT_STOP_TIMER1_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents TG0_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_task_cnt_reload_timer1_st(&self) -> TG0_TASK_CNT_RELOAD_TIMER1_ST_R { + TG0_TASK_CNT_RELOAD_TIMER1_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents TG0_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg0_task_cnt_cap_timer1_st(&self) -> TG0_TASK_CNT_CAP_TIMER1_ST_R { + TG0_TASK_CNT_CAP_TIMER1_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents TG1_task_cnt_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_task_cnt_start_timer0_st(&self) -> TG1_TASK_CNT_START_TIMER0_ST_R { + TG1_TASK_CNT_START_TIMER0_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents TG1_task_alarm_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_task_alarm_start_timer0_st(&self) -> TG1_TASK_ALARM_START_TIMER0_ST_R { + TG1_TASK_ALARM_START_TIMER0_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents TG1_task_cnt_stop_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_task_cnt_stop_timer0_st(&self) -> TG1_TASK_CNT_STOP_TIMER0_ST_R { + TG1_TASK_CNT_STOP_TIMER0_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents TG1_task_cnt_reload_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_task_cnt_reload_timer0_st(&self) -> TG1_TASK_CNT_RELOAD_TIMER0_ST_R { + TG1_TASK_CNT_RELOAD_TIMER0_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents TG1_task_cnt_cap_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_task_cnt_cap_timer0_st(&self) -> TG1_TASK_CNT_CAP_TIMER0_ST_R { + TG1_TASK_CNT_CAP_TIMER0_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents TG1_task_cnt_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_task_cnt_start_timer1_st(&self) -> TG1_TASK_CNT_START_TIMER1_ST_R { + TG1_TASK_CNT_START_TIMER1_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents TG1_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_task_alarm_start_timer1_st(&self) -> TG1_TASK_ALARM_START_TIMER1_ST_R { + TG1_TASK_ALARM_START_TIMER1_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents TG1_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_task_cnt_stop_timer1_st(&self) -> TG1_TASK_CNT_STOP_TIMER1_ST_R { + TG1_TASK_CNT_STOP_TIMER1_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents TG1_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_task_cnt_reload_timer1_st(&self) -> TG1_TASK_CNT_RELOAD_TIMER1_ST_R { + TG1_TASK_CNT_RELOAD_TIMER1_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents TG1_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tg1_task_cnt_cap_timer1_st(&self) -> TG1_TASK_CNT_CAP_TIMER1_ST_R { + TG1_TASK_CNT_CAP_TIMER1_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_cmpr0_a_up_st(&self) -> MCPWM0_TASK_CMPR0_A_UP_ST_R { + MCPWM0_TASK_CMPR0_A_UP_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_cmpr1_a_up_st(&self) -> MCPWM0_TASK_CMPR1_A_UP_ST_R { + MCPWM0_TASK_CMPR1_A_UP_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_cmpr2_a_up_st(&self) -> MCPWM0_TASK_CMPR2_A_UP_ST_R { + MCPWM0_TASK_CMPR2_A_UP_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_cmpr0_b_up_st(&self) -> MCPWM0_TASK_CMPR0_B_UP_ST_R { + MCPWM0_TASK_CMPR0_B_UP_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_cmpr1_b_up_st(&self) -> MCPWM0_TASK_CMPR1_B_UP_ST_R { + MCPWM0_TASK_CMPR1_B_UP_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_cmpr2_b_up_st(&self) -> MCPWM0_TASK_CMPR2_B_UP_ST_R { + MCPWM0_TASK_CMPR2_B_UP_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents MCPWM0_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_gen_stop_st(&self) -> MCPWM0_TASK_GEN_STOP_ST_R { + MCPWM0_TASK_GEN_STOP_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents MCPWM0_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_timer0_syn_st(&self) -> MCPWM0_TASK_TIMER0_SYN_ST_R { + MCPWM0_TASK_TIMER0_SYN_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents MCPWM0_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_timer1_syn_st(&self) -> MCPWM0_TASK_TIMER1_SYN_ST_R { + MCPWM0_TASK_TIMER1_SYN_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents MCPWM0_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_timer2_syn_st(&self) -> MCPWM0_TASK_TIMER2_SYN_ST_R { + MCPWM0_TASK_TIMER2_SYN_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents MCPWM0_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_timer0_period_up_st(&self) -> MCPWM0_TASK_TIMER0_PERIOD_UP_ST_R { + MCPWM0_TASK_TIMER0_PERIOD_UP_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents MCPWM0_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_timer1_period_up_st(&self) -> MCPWM0_TASK_TIMER1_PERIOD_UP_ST_R { + MCPWM0_TASK_TIMER1_PERIOD_UP_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents MCPWM0_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_timer2_period_up_st(&self) -> MCPWM0_TASK_TIMER2_PERIOD_UP_ST_R { + MCPWM0_TASK_TIMER2_PERIOD_UP_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents MCPWM0_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_tz0_ost_st(&self) -> MCPWM0_TASK_TZ0_OST_ST_R { + MCPWM0_TASK_TZ0_OST_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents MCPWM0_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_tz1_ost_st(&self) -> MCPWM0_TASK_TZ1_OST_ST_R { + MCPWM0_TASK_TZ1_OST_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents MCPWM0_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_tz2_ost_st(&self) -> MCPWM0_TASK_TZ2_OST_ST_R { + MCPWM0_TASK_TZ2_OST_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TASK_ST3") + .field( + "tg0_task_cnt_cap_timer0_st", + &format_args!("{}", self.tg0_task_cnt_cap_timer0_st().bit()), + ) + .field( + "tg0_task_cnt_start_timer1_st", + &format_args!("{}", self.tg0_task_cnt_start_timer1_st().bit()), + ) + .field( + "tg0_task_alarm_start_timer1_st", + &format_args!("{}", self.tg0_task_alarm_start_timer1_st().bit()), + ) + .field( + "tg0_task_cnt_stop_timer1_st", + &format_args!("{}", self.tg0_task_cnt_stop_timer1_st().bit()), + ) + .field( + "tg0_task_cnt_reload_timer1_st", + &format_args!("{}", self.tg0_task_cnt_reload_timer1_st().bit()), + ) + .field( + "tg0_task_cnt_cap_timer1_st", + &format_args!("{}", self.tg0_task_cnt_cap_timer1_st().bit()), + ) + .field( + "tg1_task_cnt_start_timer0_st", + &format_args!("{}", self.tg1_task_cnt_start_timer0_st().bit()), + ) + .field( + "tg1_task_alarm_start_timer0_st", + &format_args!("{}", self.tg1_task_alarm_start_timer0_st().bit()), + ) + .field( + "tg1_task_cnt_stop_timer0_st", + &format_args!("{}", self.tg1_task_cnt_stop_timer0_st().bit()), + ) + .field( + "tg1_task_cnt_reload_timer0_st", + &format_args!("{}", self.tg1_task_cnt_reload_timer0_st().bit()), + ) + .field( + "tg1_task_cnt_cap_timer0_st", + &format_args!("{}", self.tg1_task_cnt_cap_timer0_st().bit()), + ) + .field( + "tg1_task_cnt_start_timer1_st", + &format_args!("{}", self.tg1_task_cnt_start_timer1_st().bit()), + ) + .field( + "tg1_task_alarm_start_timer1_st", + &format_args!("{}", self.tg1_task_alarm_start_timer1_st().bit()), + ) + .field( + "tg1_task_cnt_stop_timer1_st", + &format_args!("{}", self.tg1_task_cnt_stop_timer1_st().bit()), + ) + .field( + "tg1_task_cnt_reload_timer1_st", + &format_args!("{}", self.tg1_task_cnt_reload_timer1_st().bit()), + ) + .field( + "tg1_task_cnt_cap_timer1_st", + &format_args!("{}", self.tg1_task_cnt_cap_timer1_st().bit()), + ) + .field( + "mcpwm0_task_cmpr0_a_up_st", + &format_args!("{}", self.mcpwm0_task_cmpr0_a_up_st().bit()), + ) + .field( + "mcpwm0_task_cmpr1_a_up_st", + &format_args!("{}", self.mcpwm0_task_cmpr1_a_up_st().bit()), + ) + .field( + "mcpwm0_task_cmpr2_a_up_st", + &format_args!("{}", self.mcpwm0_task_cmpr2_a_up_st().bit()), + ) + .field( + "mcpwm0_task_cmpr0_b_up_st", + &format_args!("{}", self.mcpwm0_task_cmpr0_b_up_st().bit()), + ) + .field( + "mcpwm0_task_cmpr1_b_up_st", + &format_args!("{}", self.mcpwm0_task_cmpr1_b_up_st().bit()), + ) + .field( + "mcpwm0_task_cmpr2_b_up_st", + &format_args!("{}", self.mcpwm0_task_cmpr2_b_up_st().bit()), + ) + .field( + "mcpwm0_task_gen_stop_st", + &format_args!("{}", self.mcpwm0_task_gen_stop_st().bit()), + ) + .field( + "mcpwm0_task_timer0_syn_st", + &format_args!("{}", self.mcpwm0_task_timer0_syn_st().bit()), + ) + .field( + "mcpwm0_task_timer1_syn_st", + &format_args!("{}", self.mcpwm0_task_timer1_syn_st().bit()), + ) + .field( + "mcpwm0_task_timer2_syn_st", + &format_args!("{}", self.mcpwm0_task_timer2_syn_st().bit()), + ) + .field( + "mcpwm0_task_timer0_period_up_st", + &format_args!("{}", self.mcpwm0_task_timer0_period_up_st().bit()), + ) + .field( + "mcpwm0_task_timer1_period_up_st", + &format_args!("{}", self.mcpwm0_task_timer1_period_up_st().bit()), + ) + .field( + "mcpwm0_task_timer2_period_up_st", + &format_args!("{}", self.mcpwm0_task_timer2_period_up_st().bit()), + ) + .field( + "mcpwm0_task_tz0_ost_st", + &format_args!("{}", self.mcpwm0_task_tz0_ost_st().bit()), + ) + .field( + "mcpwm0_task_tz1_ost_st", + &format_args!("{}", self.mcpwm0_task_tz1_ost_st().bit()), + ) + .field( + "mcpwm0_task_tz2_ost_st", + &format_args!("{}", self.mcpwm0_task_tz2_ost_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents TG0_task_cnt_cap_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_cap_timer0_st(&mut self) -> TG0_TASK_CNT_CAP_TIMER0_ST_W { + TG0_TASK_CNT_CAP_TIMER0_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents TG0_task_cnt_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_start_timer1_st( + &mut self, + ) -> TG0_TASK_CNT_START_TIMER1_ST_W { + TG0_TASK_CNT_START_TIMER1_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents TG0_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_task_alarm_start_timer1_st( + &mut self, + ) -> TG0_TASK_ALARM_START_TIMER1_ST_W { + TG0_TASK_ALARM_START_TIMER1_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents TG0_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_stop_timer1_st(&mut self) -> TG0_TASK_CNT_STOP_TIMER1_ST_W { + TG0_TASK_CNT_STOP_TIMER1_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents TG0_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_reload_timer1_st( + &mut self, + ) -> TG0_TASK_CNT_RELOAD_TIMER1_ST_W { + TG0_TASK_CNT_RELOAD_TIMER1_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents TG0_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_cap_timer1_st(&mut self) -> TG0_TASK_CNT_CAP_TIMER1_ST_W { + TG0_TASK_CNT_CAP_TIMER1_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents TG1_task_cnt_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_start_timer0_st( + &mut self, + ) -> TG1_TASK_CNT_START_TIMER0_ST_W { + TG1_TASK_CNT_START_TIMER0_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents TG1_task_alarm_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_task_alarm_start_timer0_st( + &mut self, + ) -> TG1_TASK_ALARM_START_TIMER0_ST_W { + TG1_TASK_ALARM_START_TIMER0_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents TG1_task_cnt_stop_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_stop_timer0_st(&mut self) -> TG1_TASK_CNT_STOP_TIMER0_ST_W { + TG1_TASK_CNT_STOP_TIMER0_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents TG1_task_cnt_reload_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_reload_timer0_st( + &mut self, + ) -> TG1_TASK_CNT_RELOAD_TIMER0_ST_W { + TG1_TASK_CNT_RELOAD_TIMER0_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents TG1_task_cnt_cap_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_cap_timer0_st(&mut self) -> TG1_TASK_CNT_CAP_TIMER0_ST_W { + TG1_TASK_CNT_CAP_TIMER0_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents TG1_task_cnt_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_start_timer1_st( + &mut self, + ) -> TG1_TASK_CNT_START_TIMER1_ST_W { + TG1_TASK_CNT_START_TIMER1_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents TG1_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_task_alarm_start_timer1_st( + &mut self, + ) -> TG1_TASK_ALARM_START_TIMER1_ST_W { + TG1_TASK_ALARM_START_TIMER1_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents TG1_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_stop_timer1_st(&mut self) -> TG1_TASK_CNT_STOP_TIMER1_ST_W { + TG1_TASK_CNT_STOP_TIMER1_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents TG1_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_reload_timer1_st( + &mut self, + ) -> TG1_TASK_CNT_RELOAD_TIMER1_ST_W { + TG1_TASK_CNT_RELOAD_TIMER1_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents TG1_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_cap_timer1_st(&mut self) -> TG1_TASK_CNT_CAP_TIMER1_ST_W { + TG1_TASK_CNT_CAP_TIMER1_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr0_a_up_st(&mut self) -> MCPWM0_TASK_CMPR0_A_UP_ST_W { + MCPWM0_TASK_CMPR0_A_UP_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr1_a_up_st(&mut self) -> MCPWM0_TASK_CMPR1_A_UP_ST_W { + MCPWM0_TASK_CMPR1_A_UP_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr2_a_up_st(&mut self) -> MCPWM0_TASK_CMPR2_A_UP_ST_W { + MCPWM0_TASK_CMPR2_A_UP_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr0_b_up_st(&mut self) -> MCPWM0_TASK_CMPR0_B_UP_ST_W { + MCPWM0_TASK_CMPR0_B_UP_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr1_b_up_st(&mut self) -> MCPWM0_TASK_CMPR1_B_UP_ST_W { + MCPWM0_TASK_CMPR1_B_UP_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr2_b_up_st(&mut self) -> MCPWM0_TASK_CMPR2_B_UP_ST_W { + MCPWM0_TASK_CMPR2_B_UP_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents MCPWM0_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_gen_stop_st(&mut self) -> MCPWM0_TASK_GEN_STOP_ST_W { + MCPWM0_TASK_GEN_STOP_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents MCPWM0_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer0_syn_st(&mut self) -> MCPWM0_TASK_TIMER0_SYN_ST_W { + MCPWM0_TASK_TIMER0_SYN_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents MCPWM0_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer1_syn_st(&mut self) -> MCPWM0_TASK_TIMER1_SYN_ST_W { + MCPWM0_TASK_TIMER1_SYN_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents MCPWM0_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer2_syn_st(&mut self) -> MCPWM0_TASK_TIMER2_SYN_ST_W { + MCPWM0_TASK_TIMER2_SYN_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents MCPWM0_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer0_period_up_st( + &mut self, + ) -> MCPWM0_TASK_TIMER0_PERIOD_UP_ST_W { + MCPWM0_TASK_TIMER0_PERIOD_UP_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents MCPWM0_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer1_period_up_st( + &mut self, + ) -> MCPWM0_TASK_TIMER1_PERIOD_UP_ST_W { + MCPWM0_TASK_TIMER1_PERIOD_UP_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents MCPWM0_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer2_period_up_st( + &mut self, + ) -> MCPWM0_TASK_TIMER2_PERIOD_UP_ST_W { + MCPWM0_TASK_TIMER2_PERIOD_UP_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents MCPWM0_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_tz0_ost_st(&mut self) -> MCPWM0_TASK_TZ0_OST_ST_W { + MCPWM0_TASK_TZ0_OST_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents MCPWM0_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_tz1_ost_st(&mut self) -> MCPWM0_TASK_TZ1_OST_ST_W { + MCPWM0_TASK_TZ1_OST_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents MCPWM0_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_tz2_ost_st(&mut self) -> MCPWM0_TASK_TZ2_OST_ST_W { + MCPWM0_TASK_TZ2_OST_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST3_SPEC; +impl crate::RegisterSpec for TASK_ST3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`task_st3::R`](R) reader structure"] +impl crate::Readable for TASK_ST3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`task_st3::W`](W) writer structure"] +impl crate::Writable for TASK_ST3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST3 to value 0"] +impl crate::Resettable for TASK_ST3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st3_clr.rs b/esp32p4/src/soc_etm/task_st3_clr.rs new file mode 100644 index 0000000000..5189665add --- /dev/null +++ b/esp32p4/src/soc_etm/task_st3_clr.rs @@ -0,0 +1,354 @@ +#[doc = "Register `TASK_ST3_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `TG0_TASK_CNT_CAP_TIMER0_ST_CLR` writer - Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_TASK_CNT_CAP_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_START_TIMER1_ST_CLR` writer - Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_TASK_CNT_START_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_ALARM_START_TIMER1_ST_CLR` writer - Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_TASK_ALARM_START_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_STOP_TIMER1_ST_CLR` writer - Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_TASK_CNT_STOP_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR` writer - Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG0_TASK_CNT_CAP_TIMER1_ST_CLR` writer - Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG0_TASK_CNT_CAP_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_START_TIMER0_ST_CLR` writer - Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_TASK_CNT_START_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_ALARM_START_TIMER0_ST_CLR` writer - Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_TASK_ALARM_START_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_STOP_TIMER0_ST_CLR` writer - Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_TASK_CNT_STOP_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR` writer - Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_CAP_TIMER0_ST_CLR` writer - Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_TASK_CNT_CAP_TIMER0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_START_TIMER1_ST_CLR` writer - Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_TASK_CNT_START_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_ALARM_START_TIMER1_ST_CLR` writer - Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_TASK_ALARM_START_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_STOP_TIMER1_ST_CLR` writer - Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_TASK_CNT_STOP_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR` writer - Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TG1_TASK_CNT_CAP_TIMER1_ST_CLR` writer - Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TG1_TASK_CNT_CAP_TIMER1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR0_A_UP_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CMPR0_A_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR1_A_UP_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CMPR1_A_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR2_A_UP_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CMPR2_A_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR0_B_UP_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CMPR0_B_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR1_B_UP_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CMPR1_B_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CMPR2_B_UP_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CMPR2_B_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_GEN_STOP_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_GEN_STOP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER0_SYN_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_TIMER0_SYN_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER1_SYN_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_TIMER1_SYN_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER2_SYN_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_TIMER2_SYN_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TZ0_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_TZ0_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TZ1_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_TZ1_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_TZ2_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_TZ2_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_cap_timer0_st_clr( + &mut self, + ) -> TG0_TASK_CNT_CAP_TIMER0_ST_CLR_W { + TG0_TASK_CNT_CAP_TIMER0_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_start_timer1_st_clr( + &mut self, + ) -> TG0_TASK_CNT_START_TIMER1_ST_CLR_W { + TG0_TASK_CNT_START_TIMER1_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_task_alarm_start_timer1_st_clr( + &mut self, + ) -> TG0_TASK_ALARM_START_TIMER1_ST_CLR_W { + TG0_TASK_ALARM_START_TIMER1_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_stop_timer1_st_clr( + &mut self, + ) -> TG0_TASK_CNT_STOP_TIMER1_ST_CLR_W { + TG0_TASK_CNT_STOP_TIMER1_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_reload_timer1_st_clr( + &mut self, + ) -> TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_W { + TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg0_task_cnt_cap_timer1_st_clr( + &mut self, + ) -> TG0_TASK_CNT_CAP_TIMER1_ST_CLR_W { + TG0_TASK_CNT_CAP_TIMER1_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_start_timer0_st_clr( + &mut self, + ) -> TG1_TASK_CNT_START_TIMER0_ST_CLR_W { + TG1_TASK_CNT_START_TIMER0_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_task_alarm_start_timer0_st_clr( + &mut self, + ) -> TG1_TASK_ALARM_START_TIMER0_ST_CLR_W { + TG1_TASK_ALARM_START_TIMER0_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_stop_timer0_st_clr( + &mut self, + ) -> TG1_TASK_CNT_STOP_TIMER0_ST_CLR_W { + TG1_TASK_CNT_STOP_TIMER0_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_reload_timer0_st_clr( + &mut self, + ) -> TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_W { + TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_cap_timer0_st_clr( + &mut self, + ) -> TG1_TASK_CNT_CAP_TIMER0_ST_CLR_W { + TG1_TASK_CNT_CAP_TIMER0_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_start_timer1_st_clr( + &mut self, + ) -> TG1_TASK_CNT_START_TIMER1_ST_CLR_W { + TG1_TASK_CNT_START_TIMER1_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_task_alarm_start_timer1_st_clr( + &mut self, + ) -> TG1_TASK_ALARM_START_TIMER1_ST_CLR_W { + TG1_TASK_ALARM_START_TIMER1_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_stop_timer1_st_clr( + &mut self, + ) -> TG1_TASK_CNT_STOP_TIMER1_ST_CLR_W { + TG1_TASK_CNT_STOP_TIMER1_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_reload_timer1_st_clr( + &mut self, + ) -> TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_W { + TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tg1_task_cnt_cap_timer1_st_clr( + &mut self, + ) -> TG1_TASK_CNT_CAP_TIMER1_ST_CLR_W { + TG1_TASK_CNT_CAP_TIMER1_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr0_a_up_st_clr( + &mut self, + ) -> MCPWM0_TASK_CMPR0_A_UP_ST_CLR_W { + MCPWM0_TASK_CMPR0_A_UP_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr1_a_up_st_clr( + &mut self, + ) -> MCPWM0_TASK_CMPR1_A_UP_ST_CLR_W { + MCPWM0_TASK_CMPR1_A_UP_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr2_a_up_st_clr( + &mut self, + ) -> MCPWM0_TASK_CMPR2_A_UP_ST_CLR_W { + MCPWM0_TASK_CMPR2_A_UP_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr0_b_up_st_clr( + &mut self, + ) -> MCPWM0_TASK_CMPR0_B_UP_ST_CLR_W { + MCPWM0_TASK_CMPR0_B_UP_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr1_b_up_st_clr( + &mut self, + ) -> MCPWM0_TASK_CMPR1_B_UP_ST_CLR_W { + MCPWM0_TASK_CMPR1_B_UP_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cmpr2_b_up_st_clr( + &mut self, + ) -> MCPWM0_TASK_CMPR2_B_UP_ST_CLR_W { + MCPWM0_TASK_CMPR2_B_UP_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_gen_stop_st_clr( + &mut self, + ) -> MCPWM0_TASK_GEN_STOP_ST_CLR_W { + MCPWM0_TASK_GEN_STOP_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer0_syn_st_clr( + &mut self, + ) -> MCPWM0_TASK_TIMER0_SYN_ST_CLR_W { + MCPWM0_TASK_TIMER0_SYN_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer1_syn_st_clr( + &mut self, + ) -> MCPWM0_TASK_TIMER1_SYN_ST_CLR_W { + MCPWM0_TASK_TIMER1_SYN_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer2_syn_st_clr( + &mut self, + ) -> MCPWM0_TASK_TIMER2_SYN_ST_CLR_W { + MCPWM0_TASK_TIMER2_SYN_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer0_period_up_st_clr( + &mut self, + ) -> MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_W { + MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer1_period_up_st_clr( + &mut self, + ) -> MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_W { + MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_timer2_period_up_st_clr( + &mut self, + ) -> MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_W { + MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_tz0_ost_st_clr( + &mut self, + ) -> MCPWM0_TASK_TZ0_OST_ST_CLR_W { + MCPWM0_TASK_TZ0_OST_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_tz1_ost_st_clr( + &mut self, + ) -> MCPWM0_TASK_TZ1_OST_ST_CLR_W { + MCPWM0_TASK_TZ1_OST_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_tz2_ost_st_clr( + &mut self, + ) -> MCPWM0_TASK_TZ2_OST_ST_CLR_W { + MCPWM0_TASK_TZ2_OST_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st3_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST3_CLR_SPEC; +impl crate::RegisterSpec for TASK_ST3_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`task_st3_clr::W`](W) writer structure"] +impl crate::Writable for TASK_ST3_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST3_CLR to value 0"] +impl crate::Resettable for TASK_ST3_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st4.rs b/esp32p4/src/soc_etm/task_st4.rs new file mode 100644 index 0000000000..340fbe9ed5 --- /dev/null +++ b/esp32p4/src/soc_etm/task_st4.rs @@ -0,0 +1,661 @@ +#[doc = "Register `TASK_ST4` reader"] +pub type R = crate::R; +#[doc = "Register `TASK_ST4` writer"] +pub type W = crate::W; +#[doc = "Field `MCPWM0_TASK_CLR0_OST_ST` reader - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CLR0_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CLR0_OST_ST` writer - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CLR0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CLR1_OST_ST` reader - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CLR1_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CLR1_OST_ST` writer - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CLR1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CLR2_OST_ST` reader - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CLR2_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CLR2_OST_ST` writer - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CLR2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CAP0_ST` reader - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CAP0_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CAP0_ST` writer - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CAP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CAP1_ST` reader - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CAP1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CAP1_ST` writer - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CAP1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CAP2_ST` reader - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CAP2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM0_TASK_CAP2_ST` writer - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM0_TASK_CAP2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR0_A_UP_ST` reader - Represents MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR0_A_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CMPR0_A_UP_ST` writer - Represents MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR0_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR1_A_UP_ST` reader - Represents MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR1_A_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CMPR1_A_UP_ST` writer - Represents MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR1_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR2_A_UP_ST` reader - Represents MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR2_A_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CMPR2_A_UP_ST` writer - Represents MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR2_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR0_B_UP_ST` reader - Represents MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR0_B_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CMPR0_B_UP_ST` writer - Represents MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR0_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR1_B_UP_ST` reader - Represents MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR1_B_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CMPR1_B_UP_ST` writer - Represents MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR1_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR2_B_UP_ST` reader - Represents MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR2_B_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CMPR2_B_UP_ST` writer - Represents MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CMPR2_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_GEN_STOP_ST` reader - Represents MCPWM1_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_GEN_STOP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_GEN_STOP_ST` writer - Represents MCPWM1_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_GEN_STOP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER0_SYN_ST` reader - Represents MCPWM1_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER0_SYN_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_TIMER0_SYN_ST` writer - Represents MCPWM1_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER0_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER1_SYN_ST` reader - Represents MCPWM1_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER1_SYN_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_TIMER1_SYN_ST` writer - Represents MCPWM1_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER1_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER2_SYN_ST` reader - Represents MCPWM1_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER2_SYN_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_TIMER2_SYN_ST` writer - Represents MCPWM1_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER2_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER0_PERIOD_UP_ST` reader - Represents MCPWM1_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER0_PERIOD_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_TIMER0_PERIOD_UP_ST` writer - Represents MCPWM1_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER0_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER1_PERIOD_UP_ST` reader - Represents MCPWM1_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER1_PERIOD_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_TIMER1_PERIOD_UP_ST` writer - Represents MCPWM1_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER1_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER2_PERIOD_UP_ST` reader - Represents MCPWM1_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER2_PERIOD_UP_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_TIMER2_PERIOD_UP_ST` writer - Represents MCPWM1_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TIMER2_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TZ0_OST_ST` reader - Represents MCPWM1_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TZ0_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_TZ0_OST_ST` writer - Represents MCPWM1_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TZ0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TZ1_OST_ST` reader - Represents MCPWM1_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TZ1_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_TZ1_OST_ST` writer - Represents MCPWM1_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TZ1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TZ2_OST_ST` reader - Represents MCPWM1_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TZ2_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_TZ2_OST_ST` writer - Represents MCPWM1_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_TZ2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CLR0_OST_ST` reader - Represents MCPWM1_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CLR0_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CLR0_OST_ST` writer - Represents MCPWM1_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CLR0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CLR1_OST_ST` reader - Represents MCPWM1_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CLR1_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CLR1_OST_ST` writer - Represents MCPWM1_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CLR1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CLR2_OST_ST` reader - Represents MCPWM1_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CLR2_OST_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CLR2_OST_ST` writer - Represents MCPWM1_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CLR2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CAP0_ST` reader - Represents MCPWM1_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CAP0_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CAP0_ST` writer - Represents MCPWM1_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CAP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CAP1_ST` reader - Represents MCPWM1_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CAP1_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CAP1_ST` writer - Represents MCPWM1_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CAP1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CAP2_ST` reader - Represents MCPWM1_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CAP2_ST_R = crate::BitReader; +#[doc = "Field `MCPWM1_TASK_CAP2_ST` writer - Represents MCPWM1_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type MCPWM1_TASK_CAP2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_TASK_SAMPLE0_ST` reader - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_TASK_SAMPLE0_ST_R = crate::BitReader; +#[doc = "Field `ADC_TASK_SAMPLE0_ST` writer - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_TASK_SAMPLE0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_TASK_SAMPLE1_ST` reader - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_TASK_SAMPLE1_ST_R = crate::BitReader; +#[doc = "Field `ADC_TASK_SAMPLE1_ST` writer - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_TASK_SAMPLE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_TASK_START0_ST` reader - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_TASK_START0_ST_R = crate::BitReader; +#[doc = "Field `ADC_TASK_START0_ST` writer - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_TASK_START0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_TASK_STOP0_ST` reader - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_TASK_STOP0_ST_R = crate::BitReader; +#[doc = "Field `ADC_TASK_STOP0_ST` writer - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ADC_TASK_STOP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_clr0_ost_st(&self) -> MCPWM0_TASK_CLR0_OST_ST_R { + MCPWM0_TASK_CLR0_OST_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_clr1_ost_st(&self) -> MCPWM0_TASK_CLR1_OST_ST_R { + MCPWM0_TASK_CLR1_OST_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_clr2_ost_st(&self) -> MCPWM0_TASK_CLR2_OST_ST_R { + MCPWM0_TASK_CLR2_OST_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_cap0_st(&self) -> MCPWM0_TASK_CAP0_ST_R { + MCPWM0_TASK_CAP0_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_cap1_st(&self) -> MCPWM0_TASK_CAP1_ST_R { + MCPWM0_TASK_CAP1_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm0_task_cap2_st(&self) -> MCPWM0_TASK_CAP2_ST_R { + MCPWM0_TASK_CAP2_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_cmpr0_a_up_st(&self) -> MCPWM1_TASK_CMPR0_A_UP_ST_R { + MCPWM1_TASK_CMPR0_A_UP_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_cmpr1_a_up_st(&self) -> MCPWM1_TASK_CMPR1_A_UP_ST_R { + MCPWM1_TASK_CMPR1_A_UP_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_cmpr2_a_up_st(&self) -> MCPWM1_TASK_CMPR2_A_UP_ST_R { + MCPWM1_TASK_CMPR2_A_UP_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_cmpr0_b_up_st(&self) -> MCPWM1_TASK_CMPR0_B_UP_ST_R { + MCPWM1_TASK_CMPR0_B_UP_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_cmpr1_b_up_st(&self) -> MCPWM1_TASK_CMPR1_B_UP_ST_R { + MCPWM1_TASK_CMPR1_B_UP_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_cmpr2_b_up_st(&self) -> MCPWM1_TASK_CMPR2_B_UP_ST_R { + MCPWM1_TASK_CMPR2_B_UP_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents MCPWM1_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_gen_stop_st(&self) -> MCPWM1_TASK_GEN_STOP_ST_R { + MCPWM1_TASK_GEN_STOP_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents MCPWM1_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_timer0_syn_st(&self) -> MCPWM1_TASK_TIMER0_SYN_ST_R { + MCPWM1_TASK_TIMER0_SYN_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents MCPWM1_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_timer1_syn_st(&self) -> MCPWM1_TASK_TIMER1_SYN_ST_R { + MCPWM1_TASK_TIMER1_SYN_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents MCPWM1_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_timer2_syn_st(&self) -> MCPWM1_TASK_TIMER2_SYN_ST_R { + MCPWM1_TASK_TIMER2_SYN_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents MCPWM1_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_timer0_period_up_st(&self) -> MCPWM1_TASK_TIMER0_PERIOD_UP_ST_R { + MCPWM1_TASK_TIMER0_PERIOD_UP_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents MCPWM1_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_timer1_period_up_st(&self) -> MCPWM1_TASK_TIMER1_PERIOD_UP_ST_R { + MCPWM1_TASK_TIMER1_PERIOD_UP_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents MCPWM1_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_timer2_period_up_st(&self) -> MCPWM1_TASK_TIMER2_PERIOD_UP_ST_R { + MCPWM1_TASK_TIMER2_PERIOD_UP_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents MCPWM1_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_tz0_ost_st(&self) -> MCPWM1_TASK_TZ0_OST_ST_R { + MCPWM1_TASK_TZ0_OST_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents MCPWM1_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_tz1_ost_st(&self) -> MCPWM1_TASK_TZ1_OST_ST_R { + MCPWM1_TASK_TZ1_OST_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents MCPWM1_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_tz2_ost_st(&self) -> MCPWM1_TASK_TZ2_OST_ST_R { + MCPWM1_TASK_TZ2_OST_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents MCPWM1_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_clr0_ost_st(&self) -> MCPWM1_TASK_CLR0_OST_ST_R { + MCPWM1_TASK_CLR0_OST_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents MCPWM1_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_clr1_ost_st(&self) -> MCPWM1_TASK_CLR1_OST_ST_R { + MCPWM1_TASK_CLR1_OST_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents MCPWM1_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_clr2_ost_st(&self) -> MCPWM1_TASK_CLR2_OST_ST_R { + MCPWM1_TASK_CLR2_OST_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents MCPWM1_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_cap0_st(&self) -> MCPWM1_TASK_CAP0_ST_R { + MCPWM1_TASK_CAP0_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents MCPWM1_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_cap1_st(&self) -> MCPWM1_TASK_CAP1_ST_R { + MCPWM1_TASK_CAP1_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents MCPWM1_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn mcpwm1_task_cap2_st(&self) -> MCPWM1_TASK_CAP2_ST_R { + MCPWM1_TASK_CAP2_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_task_sample0_st(&self) -> ADC_TASK_SAMPLE0_ST_R { + ADC_TASK_SAMPLE0_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_task_sample1_st(&self) -> ADC_TASK_SAMPLE1_ST_R { + ADC_TASK_SAMPLE1_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_task_start0_st(&self) -> ADC_TASK_START0_ST_R { + ADC_TASK_START0_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn adc_task_stop0_st(&self) -> ADC_TASK_STOP0_ST_R { + ADC_TASK_STOP0_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TASK_ST4") + .field( + "mcpwm0_task_clr0_ost_st", + &format_args!("{}", self.mcpwm0_task_clr0_ost_st().bit()), + ) + .field( + "mcpwm0_task_clr1_ost_st", + &format_args!("{}", self.mcpwm0_task_clr1_ost_st().bit()), + ) + .field( + "mcpwm0_task_clr2_ost_st", + &format_args!("{}", self.mcpwm0_task_clr2_ost_st().bit()), + ) + .field( + "mcpwm0_task_cap0_st", + &format_args!("{}", self.mcpwm0_task_cap0_st().bit()), + ) + .field( + "mcpwm0_task_cap1_st", + &format_args!("{}", self.mcpwm0_task_cap1_st().bit()), + ) + .field( + "mcpwm0_task_cap2_st", + &format_args!("{}", self.mcpwm0_task_cap2_st().bit()), + ) + .field( + "mcpwm1_task_cmpr0_a_up_st", + &format_args!("{}", self.mcpwm1_task_cmpr0_a_up_st().bit()), + ) + .field( + "mcpwm1_task_cmpr1_a_up_st", + &format_args!("{}", self.mcpwm1_task_cmpr1_a_up_st().bit()), + ) + .field( + "mcpwm1_task_cmpr2_a_up_st", + &format_args!("{}", self.mcpwm1_task_cmpr2_a_up_st().bit()), + ) + .field( + "mcpwm1_task_cmpr0_b_up_st", + &format_args!("{}", self.mcpwm1_task_cmpr0_b_up_st().bit()), + ) + .field( + "mcpwm1_task_cmpr1_b_up_st", + &format_args!("{}", self.mcpwm1_task_cmpr1_b_up_st().bit()), + ) + .field( + "mcpwm1_task_cmpr2_b_up_st", + &format_args!("{}", self.mcpwm1_task_cmpr2_b_up_st().bit()), + ) + .field( + "mcpwm1_task_gen_stop_st", + &format_args!("{}", self.mcpwm1_task_gen_stop_st().bit()), + ) + .field( + "mcpwm1_task_timer0_syn_st", + &format_args!("{}", self.mcpwm1_task_timer0_syn_st().bit()), + ) + .field( + "mcpwm1_task_timer1_syn_st", + &format_args!("{}", self.mcpwm1_task_timer1_syn_st().bit()), + ) + .field( + "mcpwm1_task_timer2_syn_st", + &format_args!("{}", self.mcpwm1_task_timer2_syn_st().bit()), + ) + .field( + "mcpwm1_task_timer0_period_up_st", + &format_args!("{}", self.mcpwm1_task_timer0_period_up_st().bit()), + ) + .field( + "mcpwm1_task_timer1_period_up_st", + &format_args!("{}", self.mcpwm1_task_timer1_period_up_st().bit()), + ) + .field( + "mcpwm1_task_timer2_period_up_st", + &format_args!("{}", self.mcpwm1_task_timer2_period_up_st().bit()), + ) + .field( + "mcpwm1_task_tz0_ost_st", + &format_args!("{}", self.mcpwm1_task_tz0_ost_st().bit()), + ) + .field( + "mcpwm1_task_tz1_ost_st", + &format_args!("{}", self.mcpwm1_task_tz1_ost_st().bit()), + ) + .field( + "mcpwm1_task_tz2_ost_st", + &format_args!("{}", self.mcpwm1_task_tz2_ost_st().bit()), + ) + .field( + "mcpwm1_task_clr0_ost_st", + &format_args!("{}", self.mcpwm1_task_clr0_ost_st().bit()), + ) + .field( + "mcpwm1_task_clr1_ost_st", + &format_args!("{}", self.mcpwm1_task_clr1_ost_st().bit()), + ) + .field( + "mcpwm1_task_clr2_ost_st", + &format_args!("{}", self.mcpwm1_task_clr2_ost_st().bit()), + ) + .field( + "mcpwm1_task_cap0_st", + &format_args!("{}", self.mcpwm1_task_cap0_st().bit()), + ) + .field( + "mcpwm1_task_cap1_st", + &format_args!("{}", self.mcpwm1_task_cap1_st().bit()), + ) + .field( + "mcpwm1_task_cap2_st", + &format_args!("{}", self.mcpwm1_task_cap2_st().bit()), + ) + .field( + "adc_task_sample0_st", + &format_args!("{}", self.adc_task_sample0_st().bit()), + ) + .field( + "adc_task_sample1_st", + &format_args!("{}", self.adc_task_sample1_st().bit()), + ) + .field( + "adc_task_start0_st", + &format_args!("{}", self.adc_task_start0_st().bit()), + ) + .field( + "adc_task_stop0_st", + &format_args!("{}", self.adc_task_stop0_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_clr0_ost_st(&mut self) -> MCPWM0_TASK_CLR0_OST_ST_W { + MCPWM0_TASK_CLR0_OST_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_clr1_ost_st(&mut self) -> MCPWM0_TASK_CLR1_OST_ST_W { + MCPWM0_TASK_CLR1_OST_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_clr2_ost_st(&mut self) -> MCPWM0_TASK_CLR2_OST_ST_W { + MCPWM0_TASK_CLR2_OST_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cap0_st(&mut self) -> MCPWM0_TASK_CAP0_ST_W { + MCPWM0_TASK_CAP0_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cap1_st(&mut self) -> MCPWM0_TASK_CAP1_ST_W { + MCPWM0_TASK_CAP1_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cap2_st(&mut self) -> MCPWM0_TASK_CAP2_ST_W { + MCPWM0_TASK_CAP2_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr0_a_up_st(&mut self) -> MCPWM1_TASK_CMPR0_A_UP_ST_W { + MCPWM1_TASK_CMPR0_A_UP_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr1_a_up_st(&mut self) -> MCPWM1_TASK_CMPR1_A_UP_ST_W { + MCPWM1_TASK_CMPR1_A_UP_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr2_a_up_st(&mut self) -> MCPWM1_TASK_CMPR2_A_UP_ST_W { + MCPWM1_TASK_CMPR2_A_UP_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr0_b_up_st(&mut self) -> MCPWM1_TASK_CMPR0_B_UP_ST_W { + MCPWM1_TASK_CMPR0_B_UP_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr1_b_up_st(&mut self) -> MCPWM1_TASK_CMPR1_B_UP_ST_W { + MCPWM1_TASK_CMPR1_B_UP_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr2_b_up_st(&mut self) -> MCPWM1_TASK_CMPR2_B_UP_ST_W { + MCPWM1_TASK_CMPR2_B_UP_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents MCPWM1_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_gen_stop_st(&mut self) -> MCPWM1_TASK_GEN_STOP_ST_W { + MCPWM1_TASK_GEN_STOP_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents MCPWM1_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer0_syn_st(&mut self) -> MCPWM1_TASK_TIMER0_SYN_ST_W { + MCPWM1_TASK_TIMER0_SYN_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents MCPWM1_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer1_syn_st(&mut self) -> MCPWM1_TASK_TIMER1_SYN_ST_W { + MCPWM1_TASK_TIMER1_SYN_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents MCPWM1_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer2_syn_st(&mut self) -> MCPWM1_TASK_TIMER2_SYN_ST_W { + MCPWM1_TASK_TIMER2_SYN_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents MCPWM1_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer0_period_up_st( + &mut self, + ) -> MCPWM1_TASK_TIMER0_PERIOD_UP_ST_W { + MCPWM1_TASK_TIMER0_PERIOD_UP_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents MCPWM1_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer1_period_up_st( + &mut self, + ) -> MCPWM1_TASK_TIMER1_PERIOD_UP_ST_W { + MCPWM1_TASK_TIMER1_PERIOD_UP_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents MCPWM1_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer2_period_up_st( + &mut self, + ) -> MCPWM1_TASK_TIMER2_PERIOD_UP_ST_W { + MCPWM1_TASK_TIMER2_PERIOD_UP_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents MCPWM1_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_tz0_ost_st(&mut self) -> MCPWM1_TASK_TZ0_OST_ST_W { + MCPWM1_TASK_TZ0_OST_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents MCPWM1_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_tz1_ost_st(&mut self) -> MCPWM1_TASK_TZ1_OST_ST_W { + MCPWM1_TASK_TZ1_OST_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents MCPWM1_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_tz2_ost_st(&mut self) -> MCPWM1_TASK_TZ2_OST_ST_W { + MCPWM1_TASK_TZ2_OST_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents MCPWM1_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_clr0_ost_st(&mut self) -> MCPWM1_TASK_CLR0_OST_ST_W { + MCPWM1_TASK_CLR0_OST_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents MCPWM1_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_clr1_ost_st(&mut self) -> MCPWM1_TASK_CLR1_OST_ST_W { + MCPWM1_TASK_CLR1_OST_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents MCPWM1_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_clr2_ost_st(&mut self) -> MCPWM1_TASK_CLR2_OST_ST_W { + MCPWM1_TASK_CLR2_OST_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents MCPWM1_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cap0_st(&mut self) -> MCPWM1_TASK_CAP0_ST_W { + MCPWM1_TASK_CAP0_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents MCPWM1_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cap1_st(&mut self) -> MCPWM1_TASK_CAP1_ST_W { + MCPWM1_TASK_CAP1_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents MCPWM1_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cap2_st(&mut self) -> MCPWM1_TASK_CAP2_ST_W { + MCPWM1_TASK_CAP2_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_task_sample0_st(&mut self) -> ADC_TASK_SAMPLE0_ST_W { + ADC_TASK_SAMPLE0_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_task_sample1_st(&mut self) -> ADC_TASK_SAMPLE1_ST_W { + ADC_TASK_SAMPLE1_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_task_start0_st(&mut self) -> ADC_TASK_START0_ST_W { + ADC_TASK_START0_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn adc_task_stop0_st(&mut self) -> ADC_TASK_STOP0_ST_W { + ADC_TASK_STOP0_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST4_SPEC; +impl crate::RegisterSpec for TASK_ST4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`task_st4::R`](R) reader structure"] +impl crate::Readable for TASK_ST4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`task_st4::W`](W) writer structure"] +impl crate::Writable for TASK_ST4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST4 to value 0"] +impl crate::Resettable for TASK_ST4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st4_clr.rs b/esp32p4/src/soc_etm/task_st4_clr.rs new file mode 100644 index 0000000000..d9329014b7 --- /dev/null +++ b/esp32p4/src/soc_etm/task_st4_clr.rs @@ -0,0 +1,334 @@ +#[doc = "Register `TASK_ST4_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `MCPWM0_TASK_CLR0_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CLR0_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CLR1_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CLR1_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CLR2_OST_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CLR2_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CAP0_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CAP0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CAP1_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CAP1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM0_TASK_CAP2_ST_CLR` writer - Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM0_TASK_CAP2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR0_A_UP_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CMPR0_A_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR1_A_UP_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CMPR1_A_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR2_A_UP_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CMPR2_A_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR0_B_UP_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CMPR0_B_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR1_B_UP_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CMPR1_B_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CMPR2_B_UP_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CMPR2_B_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_GEN_STOP_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_gen_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_GEN_STOP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER0_SYN_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_timer0_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_TIMER0_SYN_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER1_SYN_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_timer1_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_TIMER1_SYN_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER2_SYN_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_timer2_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_TIMER2_SYN_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TZ0_OST_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_TZ0_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TZ1_OST_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_TZ1_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_TZ2_OST_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_TZ2_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CLR0_OST_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_clr0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CLR0_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CLR1_OST_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_clr1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CLR1_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CLR2_OST_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_clr2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CLR2_OST_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CAP0_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CAP0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CAP1_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CAP1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MCPWM1_TASK_CAP2_ST_CLR` writer - Configures whether or not to clear MCPWM1_task_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type MCPWM1_TASK_CAP2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_TASK_SAMPLE0_ST_CLR` writer - Configures whether or not to clear ADC_task_sample0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_TASK_SAMPLE0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_TASK_SAMPLE1_ST_CLR` writer - Configures whether or not to clear ADC_task_sample1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_TASK_SAMPLE1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_TASK_START0_ST_CLR` writer - Configures whether or not to clear ADC_task_start0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_TASK_START0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_TASK_STOP0_ST_CLR` writer - Configures whether or not to clear ADC_task_stop0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ADC_TASK_STOP0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_clr0_ost_st_clr( + &mut self, + ) -> MCPWM0_TASK_CLR0_OST_ST_CLR_W { + MCPWM0_TASK_CLR0_OST_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_clr1_ost_st_clr( + &mut self, + ) -> MCPWM0_TASK_CLR1_OST_ST_CLR_W { + MCPWM0_TASK_CLR1_OST_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_clr2_ost_st_clr( + &mut self, + ) -> MCPWM0_TASK_CLR2_OST_ST_CLR_W { + MCPWM0_TASK_CLR2_OST_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cap0_st_clr(&mut self) -> MCPWM0_TASK_CAP0_ST_CLR_W { + MCPWM0_TASK_CAP0_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cap1_st_clr(&mut self) -> MCPWM0_TASK_CAP1_ST_CLR_W { + MCPWM0_TASK_CAP1_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm0_task_cap2_st_clr(&mut self) -> MCPWM0_TASK_CAP2_ST_CLR_W { + MCPWM0_TASK_CAP2_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr0_a_up_st_clr( + &mut self, + ) -> MCPWM1_TASK_CMPR0_A_UP_ST_CLR_W { + MCPWM1_TASK_CMPR0_A_UP_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr1_a_up_st_clr( + &mut self, + ) -> MCPWM1_TASK_CMPR1_A_UP_ST_CLR_W { + MCPWM1_TASK_CMPR1_A_UP_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr2_a_up_st_clr( + &mut self, + ) -> MCPWM1_TASK_CMPR2_A_UP_ST_CLR_W { + MCPWM1_TASK_CMPR2_A_UP_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr0_b_up_st_clr( + &mut self, + ) -> MCPWM1_TASK_CMPR0_B_UP_ST_CLR_W { + MCPWM1_TASK_CMPR0_B_UP_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr1_b_up_st_clr( + &mut self, + ) -> MCPWM1_TASK_CMPR1_B_UP_ST_CLR_W { + MCPWM1_TASK_CMPR1_B_UP_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cmpr2_b_up_st_clr( + &mut self, + ) -> MCPWM1_TASK_CMPR2_B_UP_ST_CLR_W { + MCPWM1_TASK_CMPR2_B_UP_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear MCPWM1_task_gen_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_gen_stop_st_clr( + &mut self, + ) -> MCPWM1_TASK_GEN_STOP_ST_CLR_W { + MCPWM1_TASK_GEN_STOP_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear MCPWM1_task_timer0_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer0_syn_st_clr( + &mut self, + ) -> MCPWM1_TASK_TIMER0_SYN_ST_CLR_W { + MCPWM1_TASK_TIMER0_SYN_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear MCPWM1_task_timer1_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer1_syn_st_clr( + &mut self, + ) -> MCPWM1_TASK_TIMER1_SYN_ST_CLR_W { + MCPWM1_TASK_TIMER1_SYN_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear MCPWM1_task_timer2_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer2_syn_st_clr( + &mut self, + ) -> MCPWM1_TASK_TIMER2_SYN_ST_CLR_W { + MCPWM1_TASK_TIMER2_SYN_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer0_period_up_st_clr( + &mut self, + ) -> MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_W { + MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer1_period_up_st_clr( + &mut self, + ) -> MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_W { + MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_timer2_period_up_st_clr( + &mut self, + ) -> MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_W { + MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear MCPWM1_task_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_tz0_ost_st_clr( + &mut self, + ) -> MCPWM1_TASK_TZ0_OST_ST_CLR_W { + MCPWM1_TASK_TZ0_OST_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear MCPWM1_task_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_tz1_ost_st_clr( + &mut self, + ) -> MCPWM1_TASK_TZ1_OST_ST_CLR_W { + MCPWM1_TASK_TZ1_OST_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear MCPWM1_task_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_tz2_ost_st_clr( + &mut self, + ) -> MCPWM1_TASK_TZ2_OST_ST_CLR_W { + MCPWM1_TASK_TZ2_OST_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear MCPWM1_task_clr0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_clr0_ost_st_clr( + &mut self, + ) -> MCPWM1_TASK_CLR0_OST_ST_CLR_W { + MCPWM1_TASK_CLR0_OST_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear MCPWM1_task_clr1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_clr1_ost_st_clr( + &mut self, + ) -> MCPWM1_TASK_CLR1_OST_ST_CLR_W { + MCPWM1_TASK_CLR1_OST_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear MCPWM1_task_clr2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_clr2_ost_st_clr( + &mut self, + ) -> MCPWM1_TASK_CLR2_OST_ST_CLR_W { + MCPWM1_TASK_CLR2_OST_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear MCPWM1_task_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cap0_st_clr(&mut self) -> MCPWM1_TASK_CAP0_ST_CLR_W { + MCPWM1_TASK_CAP0_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear MCPWM1_task_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cap1_st_clr(&mut self) -> MCPWM1_TASK_CAP1_ST_CLR_W { + MCPWM1_TASK_CAP1_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear MCPWM1_task_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn mcpwm1_task_cap2_st_clr(&mut self) -> MCPWM1_TASK_CAP2_ST_CLR_W { + MCPWM1_TASK_CAP2_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear ADC_task_sample0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_task_sample0_st_clr(&mut self) -> ADC_TASK_SAMPLE0_ST_CLR_W { + ADC_TASK_SAMPLE0_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear ADC_task_sample1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_task_sample1_st_clr(&mut self) -> ADC_TASK_SAMPLE1_ST_CLR_W { + ADC_TASK_SAMPLE1_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear ADC_task_start0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_task_start0_st_clr(&mut self) -> ADC_TASK_START0_ST_CLR_W { + ADC_TASK_START0_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear ADC_task_stop0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn adc_task_stop0_st_clr(&mut self) -> ADC_TASK_STOP0_ST_CLR_W { + ADC_TASK_STOP0_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st4_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST4_CLR_SPEC; +impl crate::RegisterSpec for TASK_ST4_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`task_st4_clr::W`](W) writer structure"] +impl crate::Writable for TASK_ST4_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST4_CLR to value 0"] +impl crate::Resettable for TASK_ST4_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st5.rs b/esp32p4/src/soc_etm/task_st5.rs new file mode 100644 index 0000000000..9c08a45101 --- /dev/null +++ b/esp32p4/src/soc_etm/task_st5.rs @@ -0,0 +1,673 @@ +#[doc = "Register `TASK_ST5` reader"] +pub type R = crate::R; +#[doc = "Register `TASK_ST5` writer"] +pub type W = crate::W; +#[doc = "Field `REGDMA_TASK_START0_ST` reader - Represents REGDMA_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_TASK_START0_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_TASK_START0_ST` writer - Represents REGDMA_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_TASK_START0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_TASK_START1_ST` reader - Represents REGDMA_task_start1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_TASK_START1_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_TASK_START1_ST` writer - Represents REGDMA_task_start1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_TASK_START1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_TASK_START2_ST` reader - Represents REGDMA_task_start2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_TASK_START2_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_TASK_START2_ST` writer - Represents REGDMA_task_start2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_TASK_START2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_TASK_START3_ST` reader - Represents REGDMA_task_start3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_TASK_START3_ST_R = crate::BitReader; +#[doc = "Field `REGDMA_TASK_START3_ST` writer - Represents REGDMA_task_start3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type REGDMA_TASK_START3_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMPSNSR_TASK_START_SAMPLE_ST` reader - Represents TMPSNSR_task_start_sample trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TMPSNSR_TASK_START_SAMPLE_ST_R = crate::BitReader; +#[doc = "Field `TMPSNSR_TASK_START_SAMPLE_ST` writer - Represents TMPSNSR_task_start_sample trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TMPSNSR_TASK_START_SAMPLE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMPSNSR_TASK_STOP_SAMPLE_ST` reader - Represents TMPSNSR_task_stop_sample trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TMPSNSR_TASK_STOP_SAMPLE_ST_R = crate::BitReader; +#[doc = "Field `TMPSNSR_TASK_STOP_SAMPLE_ST` writer - Represents TMPSNSR_task_stop_sample trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type TMPSNSR_TASK_STOP_SAMPLE_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_TASK_START_RX_ST` reader - Represents I2S0_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_TASK_START_RX_ST_R = crate::BitReader; +#[doc = "Field `I2S0_TASK_START_RX_ST` writer - Represents I2S0_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_TASK_START_RX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_TASK_START_TX_ST` reader - Represents I2S0_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_TASK_START_TX_ST_R = crate::BitReader; +#[doc = "Field `I2S0_TASK_START_TX_ST` writer - Represents I2S0_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_TASK_START_TX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_TASK_STOP_RX_ST` reader - Represents I2S0_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_TASK_STOP_RX_ST_R = crate::BitReader; +#[doc = "Field `I2S0_TASK_STOP_RX_ST` writer - Represents I2S0_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_TASK_STOP_RX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_TASK_STOP_TX_ST` reader - Represents I2S0_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_TASK_STOP_TX_ST_R = crate::BitReader; +#[doc = "Field `I2S0_TASK_STOP_TX_ST` writer - Represents I2S0_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S0_TASK_STOP_TX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_TASK_START_RX_ST` reader - Represents I2S1_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_TASK_START_RX_ST_R = crate::BitReader; +#[doc = "Field `I2S1_TASK_START_RX_ST` writer - Represents I2S1_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_TASK_START_RX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_TASK_START_TX_ST` reader - Represents I2S1_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_TASK_START_TX_ST_R = crate::BitReader; +#[doc = "Field `I2S1_TASK_START_TX_ST` writer - Represents I2S1_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_TASK_START_TX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_TASK_STOP_RX_ST` reader - Represents I2S1_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_TASK_STOP_RX_ST_R = crate::BitReader; +#[doc = "Field `I2S1_TASK_STOP_RX_ST` writer - Represents I2S1_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_TASK_STOP_RX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_TASK_STOP_TX_ST` reader - Represents I2S1_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_TASK_STOP_TX_ST_R = crate::BitReader; +#[doc = "Field `I2S1_TASK_STOP_TX_ST` writer - Represents I2S1_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S1_TASK_STOP_TX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_TASK_START_RX_ST` reader - Represents I2S2_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_TASK_START_RX_ST_R = crate::BitReader; +#[doc = "Field `I2S2_TASK_START_RX_ST` writer - Represents I2S2_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_TASK_START_RX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_TASK_START_TX_ST` reader - Represents I2S2_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_TASK_START_TX_ST_R = crate::BitReader; +#[doc = "Field `I2S2_TASK_START_TX_ST` writer - Represents I2S2_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_TASK_START_TX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_TASK_STOP_RX_ST` reader - Represents I2S2_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_TASK_STOP_RX_ST_R = crate::BitReader; +#[doc = "Field `I2S2_TASK_STOP_RX_ST` writer - Represents I2S2_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_TASK_STOP_RX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_TASK_STOP_TX_ST` reader - Represents I2S2_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_TASK_STOP_TX_ST_R = crate::BitReader; +#[doc = "Field `I2S2_TASK_STOP_TX_ST` writer - Represents I2S2_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type I2S2_TASK_STOP_TX_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ULP_TASK_WAKEUP_CPU_ST` reader - Represents ULP_task_wakeup_cpu trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ULP_TASK_WAKEUP_CPU_ST_R = crate::BitReader; +#[doc = "Field `ULP_TASK_WAKEUP_CPU_ST` writer - Represents ULP_task_wakeup_cpu trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ULP_TASK_WAKEUP_CPU_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ULP_TASK_INT_CPU_ST` reader - Represents ULP_task_int_cpu trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ULP_TASK_INT_CPU_ST_R = crate::BitReader; +#[doc = "Field `ULP_TASK_INT_CPU_ST` writer - Represents ULP_task_int_cpu trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type ULP_TASK_INT_CPU_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_TASK_START_ST` reader - Represents RTC_task_start trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_TASK_START_ST_R = crate::BitReader; +#[doc = "Field `RTC_TASK_START_ST` writer - Represents RTC_task_start trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_TASK_START_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_TASK_STOP_ST` reader - Represents RTC_task_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_TASK_STOP_ST_R = crate::BitReader; +#[doc = "Field `RTC_TASK_STOP_ST` writer - Represents RTC_task_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_TASK_STOP_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_TASK_CLR_ST` reader - Represents RTC_task_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_TASK_CLR_ST_R = crate::BitReader; +#[doc = "Field `RTC_TASK_CLR_ST` writer - Represents RTC_task_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_TASK_CLR_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_TASK_TRIGGERFLW_ST` reader - Represents RTC_task_triggerflw trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_TASK_TRIGGERFLW_ST_R = crate::BitReader; +#[doc = "Field `RTC_TASK_TRIGGERFLW_ST` writer - Represents RTC_task_triggerflw trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type RTC_TASK_TRIGGERFLW_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_IN_START_CH0_ST` reader - Represents PDMA_AHB_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_IN_START_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_TASK_IN_START_CH0_ST` writer - Represents PDMA_AHB_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_IN_START_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_IN_START_CH1_ST` reader - Represents PDMA_AHB_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_IN_START_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_TASK_IN_START_CH1_ST` writer - Represents PDMA_AHB_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_IN_START_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_IN_START_CH2_ST` reader - Represents PDMA_AHB_task_in_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_IN_START_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_TASK_IN_START_CH2_ST` writer - Represents PDMA_AHB_task_in_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_IN_START_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH0_ST` reader - Represents PDMA_AHB_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_OUT_START_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH0_ST` writer - Represents PDMA_AHB_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_OUT_START_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH1_ST` reader - Represents PDMA_AHB_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_OUT_START_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH1_ST` writer - Represents PDMA_AHB_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_OUT_START_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH2_ST` reader - Represents PDMA_AHB_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_OUT_START_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH2_ST` writer - Represents PDMA_AHB_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AHB_TASK_OUT_START_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_TASK_IN_START_CH0_ST` reader - Represents PDMA_AXI_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_IN_START_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_TASK_IN_START_CH0_ST` writer - Represents PDMA_AXI_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_IN_START_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_TASK_IN_START_CH1_ST` reader - Represents PDMA_AXI_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_IN_START_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_TASK_IN_START_CH1_ST` writer - Represents PDMA_AXI_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_IN_START_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents REGDMA_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_task_start0_st(&self) -> REGDMA_TASK_START0_ST_R { + REGDMA_TASK_START0_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents REGDMA_task_start1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_task_start1_st(&self) -> REGDMA_TASK_START1_ST_R { + REGDMA_TASK_START1_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents REGDMA_task_start2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_task_start2_st(&self) -> REGDMA_TASK_START2_ST_R { + REGDMA_TASK_START2_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents REGDMA_task_start3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn regdma_task_start3_st(&self) -> REGDMA_TASK_START3_ST_R { + REGDMA_TASK_START3_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents TMPSNSR_task_start_sample trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tmpsnsr_task_start_sample_st(&self) -> TMPSNSR_TASK_START_SAMPLE_ST_R { + TMPSNSR_TASK_START_SAMPLE_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents TMPSNSR_task_stop_sample trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn tmpsnsr_task_stop_sample_st(&self) -> TMPSNSR_TASK_STOP_SAMPLE_ST_R { + TMPSNSR_TASK_STOP_SAMPLE_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents I2S0_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s0_task_start_rx_st(&self) -> I2S0_TASK_START_RX_ST_R { + I2S0_TASK_START_RX_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents I2S0_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s0_task_start_tx_st(&self) -> I2S0_TASK_START_TX_ST_R { + I2S0_TASK_START_TX_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents I2S0_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s0_task_stop_rx_st(&self) -> I2S0_TASK_STOP_RX_ST_R { + I2S0_TASK_STOP_RX_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents I2S0_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s0_task_stop_tx_st(&self) -> I2S0_TASK_STOP_TX_ST_R { + I2S0_TASK_STOP_TX_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents I2S1_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s1_task_start_rx_st(&self) -> I2S1_TASK_START_RX_ST_R { + I2S1_TASK_START_RX_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents I2S1_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s1_task_start_tx_st(&self) -> I2S1_TASK_START_TX_ST_R { + I2S1_TASK_START_TX_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents I2S1_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s1_task_stop_rx_st(&self) -> I2S1_TASK_STOP_RX_ST_R { + I2S1_TASK_STOP_RX_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents I2S1_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s1_task_stop_tx_st(&self) -> I2S1_TASK_STOP_TX_ST_R { + I2S1_TASK_STOP_TX_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents I2S2_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s2_task_start_rx_st(&self) -> I2S2_TASK_START_RX_ST_R { + I2S2_TASK_START_RX_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Represents I2S2_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s2_task_start_tx_st(&self) -> I2S2_TASK_START_TX_ST_R { + I2S2_TASK_START_TX_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Represents I2S2_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s2_task_stop_rx_st(&self) -> I2S2_TASK_STOP_RX_ST_R { + I2S2_TASK_STOP_RX_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Represents I2S2_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn i2s2_task_stop_tx_st(&self) -> I2S2_TASK_STOP_TX_ST_R { + I2S2_TASK_STOP_TX_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Represents ULP_task_wakeup_cpu trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ulp_task_wakeup_cpu_st(&self) -> ULP_TASK_WAKEUP_CPU_ST_R { + ULP_TASK_WAKEUP_CPU_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Represents ULP_task_int_cpu trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn ulp_task_int_cpu_st(&self) -> ULP_TASK_INT_CPU_ST_R { + ULP_TASK_INT_CPU_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Represents RTC_task_start trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn rtc_task_start_st(&self) -> RTC_TASK_START_ST_R { + RTC_TASK_START_ST_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Represents RTC_task_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn rtc_task_stop_st(&self) -> RTC_TASK_STOP_ST_R { + RTC_TASK_STOP_ST_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Represents RTC_task_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn rtc_task_clr_st(&self) -> RTC_TASK_CLR_ST_R { + RTC_TASK_CLR_ST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Represents RTC_task_triggerflw trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn rtc_task_triggerflw_st(&self) -> RTC_TASK_TRIGGERFLW_ST_R { + RTC_TASK_TRIGGERFLW_ST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Represents PDMA_AHB_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_task_in_start_ch0_st(&self) -> PDMA_AHB_TASK_IN_START_CH0_ST_R { + PDMA_AHB_TASK_IN_START_CH0_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Represents PDMA_AHB_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_task_in_start_ch1_st(&self) -> PDMA_AHB_TASK_IN_START_CH1_ST_R { + PDMA_AHB_TASK_IN_START_CH1_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Represents PDMA_AHB_task_in_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_task_in_start_ch2_st(&self) -> PDMA_AHB_TASK_IN_START_CH2_ST_R { + PDMA_AHB_TASK_IN_START_CH2_ST_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Represents PDMA_AHB_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_task_out_start_ch0_st(&self) -> PDMA_AHB_TASK_OUT_START_CH0_ST_R { + PDMA_AHB_TASK_OUT_START_CH0_ST_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Represents PDMA_AHB_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_task_out_start_ch1_st(&self) -> PDMA_AHB_TASK_OUT_START_CH1_ST_R { + PDMA_AHB_TASK_OUT_START_CH1_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Represents PDMA_AHB_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_ahb_task_out_start_ch2_st(&self) -> PDMA_AHB_TASK_OUT_START_CH2_ST_R { + PDMA_AHB_TASK_OUT_START_CH2_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Represents PDMA_AXI_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_task_in_start_ch0_st(&self) -> PDMA_AXI_TASK_IN_START_CH0_ST_R { + PDMA_AXI_TASK_IN_START_CH0_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Represents PDMA_AXI_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_task_in_start_ch1_st(&self) -> PDMA_AXI_TASK_IN_START_CH1_ST_R { + PDMA_AXI_TASK_IN_START_CH1_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TASK_ST5") + .field( + "regdma_task_start0_st", + &format_args!("{}", self.regdma_task_start0_st().bit()), + ) + .field( + "regdma_task_start1_st", + &format_args!("{}", self.regdma_task_start1_st().bit()), + ) + .field( + "regdma_task_start2_st", + &format_args!("{}", self.regdma_task_start2_st().bit()), + ) + .field( + "regdma_task_start3_st", + &format_args!("{}", self.regdma_task_start3_st().bit()), + ) + .field( + "tmpsnsr_task_start_sample_st", + &format_args!("{}", self.tmpsnsr_task_start_sample_st().bit()), + ) + .field( + "tmpsnsr_task_stop_sample_st", + &format_args!("{}", self.tmpsnsr_task_stop_sample_st().bit()), + ) + .field( + "i2s0_task_start_rx_st", + &format_args!("{}", self.i2s0_task_start_rx_st().bit()), + ) + .field( + "i2s0_task_start_tx_st", + &format_args!("{}", self.i2s0_task_start_tx_st().bit()), + ) + .field( + "i2s0_task_stop_rx_st", + &format_args!("{}", self.i2s0_task_stop_rx_st().bit()), + ) + .field( + "i2s0_task_stop_tx_st", + &format_args!("{}", self.i2s0_task_stop_tx_st().bit()), + ) + .field( + "i2s1_task_start_rx_st", + &format_args!("{}", self.i2s1_task_start_rx_st().bit()), + ) + .field( + "i2s1_task_start_tx_st", + &format_args!("{}", self.i2s1_task_start_tx_st().bit()), + ) + .field( + "i2s1_task_stop_rx_st", + &format_args!("{}", self.i2s1_task_stop_rx_st().bit()), + ) + .field( + "i2s1_task_stop_tx_st", + &format_args!("{}", self.i2s1_task_stop_tx_st().bit()), + ) + .field( + "i2s2_task_start_rx_st", + &format_args!("{}", self.i2s2_task_start_rx_st().bit()), + ) + .field( + "i2s2_task_start_tx_st", + &format_args!("{}", self.i2s2_task_start_tx_st().bit()), + ) + .field( + "i2s2_task_stop_rx_st", + &format_args!("{}", self.i2s2_task_stop_rx_st().bit()), + ) + .field( + "i2s2_task_stop_tx_st", + &format_args!("{}", self.i2s2_task_stop_tx_st().bit()), + ) + .field( + "ulp_task_wakeup_cpu_st", + &format_args!("{}", self.ulp_task_wakeup_cpu_st().bit()), + ) + .field( + "ulp_task_int_cpu_st", + &format_args!("{}", self.ulp_task_int_cpu_st().bit()), + ) + .field( + "rtc_task_start_st", + &format_args!("{}", self.rtc_task_start_st().bit()), + ) + .field( + "rtc_task_stop_st", + &format_args!("{}", self.rtc_task_stop_st().bit()), + ) + .field( + "rtc_task_clr_st", + &format_args!("{}", self.rtc_task_clr_st().bit()), + ) + .field( + "rtc_task_triggerflw_st", + &format_args!("{}", self.rtc_task_triggerflw_st().bit()), + ) + .field( + "pdma_ahb_task_in_start_ch0_st", + &format_args!("{}", self.pdma_ahb_task_in_start_ch0_st().bit()), + ) + .field( + "pdma_ahb_task_in_start_ch1_st", + &format_args!("{}", self.pdma_ahb_task_in_start_ch1_st().bit()), + ) + .field( + "pdma_ahb_task_in_start_ch2_st", + &format_args!("{}", self.pdma_ahb_task_in_start_ch2_st().bit()), + ) + .field( + "pdma_ahb_task_out_start_ch0_st", + &format_args!("{}", self.pdma_ahb_task_out_start_ch0_st().bit()), + ) + .field( + "pdma_ahb_task_out_start_ch1_st", + &format_args!("{}", self.pdma_ahb_task_out_start_ch1_st().bit()), + ) + .field( + "pdma_ahb_task_out_start_ch2_st", + &format_args!("{}", self.pdma_ahb_task_out_start_ch2_st().bit()), + ) + .field( + "pdma_axi_task_in_start_ch0_st", + &format_args!("{}", self.pdma_axi_task_in_start_ch0_st().bit()), + ) + .field( + "pdma_axi_task_in_start_ch1_st", + &format_args!("{}", self.pdma_axi_task_in_start_ch1_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents REGDMA_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_task_start0_st(&mut self) -> REGDMA_TASK_START0_ST_W { + REGDMA_TASK_START0_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents REGDMA_task_start1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_task_start1_st(&mut self) -> REGDMA_TASK_START1_ST_W { + REGDMA_TASK_START1_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents REGDMA_task_start2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_task_start2_st(&mut self) -> REGDMA_TASK_START2_ST_W { + REGDMA_TASK_START2_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents REGDMA_task_start3 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn regdma_task_start3_st(&mut self) -> REGDMA_TASK_START3_ST_W { + REGDMA_TASK_START3_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents TMPSNSR_task_start_sample trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tmpsnsr_task_start_sample_st( + &mut self, + ) -> TMPSNSR_TASK_START_SAMPLE_ST_W { + TMPSNSR_TASK_START_SAMPLE_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents TMPSNSR_task_stop_sample trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn tmpsnsr_task_stop_sample_st(&mut self) -> TMPSNSR_TASK_STOP_SAMPLE_ST_W { + TMPSNSR_TASK_STOP_SAMPLE_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents I2S0_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s0_task_start_rx_st(&mut self) -> I2S0_TASK_START_RX_ST_W { + I2S0_TASK_START_RX_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents I2S0_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s0_task_start_tx_st(&mut self) -> I2S0_TASK_START_TX_ST_W { + I2S0_TASK_START_TX_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents I2S0_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s0_task_stop_rx_st(&mut self) -> I2S0_TASK_STOP_RX_ST_W { + I2S0_TASK_STOP_RX_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents I2S0_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s0_task_stop_tx_st(&mut self) -> I2S0_TASK_STOP_TX_ST_W { + I2S0_TASK_STOP_TX_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents I2S1_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s1_task_start_rx_st(&mut self) -> I2S1_TASK_START_RX_ST_W { + I2S1_TASK_START_RX_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents I2S1_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s1_task_start_tx_st(&mut self) -> I2S1_TASK_START_TX_ST_W { + I2S1_TASK_START_TX_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents I2S1_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s1_task_stop_rx_st(&mut self) -> I2S1_TASK_STOP_RX_ST_W { + I2S1_TASK_STOP_RX_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents I2S1_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s1_task_stop_tx_st(&mut self) -> I2S1_TASK_STOP_TX_ST_W { + I2S1_TASK_STOP_TX_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents I2S2_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s2_task_start_rx_st(&mut self) -> I2S2_TASK_START_RX_ST_W { + I2S2_TASK_START_RX_ST_W::new(self, 14) + } + #[doc = "Bit 15 - Represents I2S2_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s2_task_start_tx_st(&mut self) -> I2S2_TASK_START_TX_ST_W { + I2S2_TASK_START_TX_ST_W::new(self, 15) + } + #[doc = "Bit 16 - Represents I2S2_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s2_task_stop_rx_st(&mut self) -> I2S2_TASK_STOP_RX_ST_W { + I2S2_TASK_STOP_RX_ST_W::new(self, 16) + } + #[doc = "Bit 17 - Represents I2S2_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn i2s2_task_stop_tx_st(&mut self) -> I2S2_TASK_STOP_TX_ST_W { + I2S2_TASK_STOP_TX_ST_W::new(self, 17) + } + #[doc = "Bit 18 - Represents ULP_task_wakeup_cpu trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ulp_task_wakeup_cpu_st(&mut self) -> ULP_TASK_WAKEUP_CPU_ST_W { + ULP_TASK_WAKEUP_CPU_ST_W::new(self, 18) + } + #[doc = "Bit 19 - Represents ULP_task_int_cpu trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn ulp_task_int_cpu_st(&mut self) -> ULP_TASK_INT_CPU_ST_W { + ULP_TASK_INT_CPU_ST_W::new(self, 19) + } + #[doc = "Bit 20 - Represents RTC_task_start trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn rtc_task_start_st(&mut self) -> RTC_TASK_START_ST_W { + RTC_TASK_START_ST_W::new(self, 20) + } + #[doc = "Bit 21 - Represents RTC_task_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn rtc_task_stop_st(&mut self) -> RTC_TASK_STOP_ST_W { + RTC_TASK_STOP_ST_W::new(self, 21) + } + #[doc = "Bit 22 - Represents RTC_task_clr trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn rtc_task_clr_st(&mut self) -> RTC_TASK_CLR_ST_W { + RTC_TASK_CLR_ST_W::new(self, 22) + } + #[doc = "Bit 23 - Represents RTC_task_triggerflw trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn rtc_task_triggerflw_st(&mut self) -> RTC_TASK_TRIGGERFLW_ST_W { + RTC_TASK_TRIGGERFLW_ST_W::new(self, 23) + } + #[doc = "Bit 24 - Represents PDMA_AHB_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_in_start_ch0_st( + &mut self, + ) -> PDMA_AHB_TASK_IN_START_CH0_ST_W { + PDMA_AHB_TASK_IN_START_CH0_ST_W::new(self, 24) + } + #[doc = "Bit 25 - Represents PDMA_AHB_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_in_start_ch1_st( + &mut self, + ) -> PDMA_AHB_TASK_IN_START_CH1_ST_W { + PDMA_AHB_TASK_IN_START_CH1_ST_W::new(self, 25) + } + #[doc = "Bit 26 - Represents PDMA_AHB_task_in_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_in_start_ch2_st( + &mut self, + ) -> PDMA_AHB_TASK_IN_START_CH2_ST_W { + PDMA_AHB_TASK_IN_START_CH2_ST_W::new(self, 26) + } + #[doc = "Bit 27 - Represents PDMA_AHB_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_out_start_ch0_st( + &mut self, + ) -> PDMA_AHB_TASK_OUT_START_CH0_ST_W { + PDMA_AHB_TASK_OUT_START_CH0_ST_W::new(self, 27) + } + #[doc = "Bit 28 - Represents PDMA_AHB_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_out_start_ch1_st( + &mut self, + ) -> PDMA_AHB_TASK_OUT_START_CH1_ST_W { + PDMA_AHB_TASK_OUT_START_CH1_ST_W::new(self, 28) + } + #[doc = "Bit 29 - Represents PDMA_AHB_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_out_start_ch2_st( + &mut self, + ) -> PDMA_AHB_TASK_OUT_START_CH2_ST_W { + PDMA_AHB_TASK_OUT_START_CH2_ST_W::new(self, 29) + } + #[doc = "Bit 30 - Represents PDMA_AXI_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_in_start_ch0_st( + &mut self, + ) -> PDMA_AXI_TASK_IN_START_CH0_ST_W { + PDMA_AXI_TASK_IN_START_CH0_ST_W::new(self, 30) + } + #[doc = "Bit 31 - Represents PDMA_AXI_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_in_start_ch1_st( + &mut self, + ) -> PDMA_AXI_TASK_IN_START_CH1_ST_W { + PDMA_AXI_TASK_IN_START_CH1_ST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST5_SPEC; +impl crate::RegisterSpec for TASK_ST5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`task_st5::R`](R) reader structure"] +impl crate::Readable for TASK_ST5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`task_st5::W`](W) writer structure"] +impl crate::Writable for TASK_ST5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST5 to value 0"] +impl crate::Resettable for TASK_ST5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st5_clr.rs b/esp32p4/src/soc_etm/task_st5_clr.rs new file mode 100644 index 0000000000..d30db79d58 --- /dev/null +++ b/esp32p4/src/soc_etm/task_st5_clr.rs @@ -0,0 +1,314 @@ +#[doc = "Register `TASK_ST5_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `REGDMA_TASK_START0_ST_CLR` writer - Configures whether or not to clear REGDMA_task_start0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_TASK_START0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_TASK_START1_ST_CLR` writer - Configures whether or not to clear REGDMA_task_start1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_TASK_START1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_TASK_START2_ST_CLR` writer - Configures whether or not to clear REGDMA_task_start2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_TASK_START2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REGDMA_TASK_START3_ST_CLR` writer - Configures whether or not to clear REGDMA_task_start3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type REGDMA_TASK_START3_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMPSNSR_TASK_START_SAMPLE_ST_CLR` writer - Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TMPSNSR_TASK_START_SAMPLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMPSNSR_TASK_STOP_SAMPLE_ST_CLR` writer - Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_TASK_START_RX_ST_CLR` writer - Configures whether or not to clear I2S0_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S0_TASK_START_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_TASK_START_TX_ST_CLR` writer - Configures whether or not to clear I2S0_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S0_TASK_START_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_TASK_STOP_RX_ST_CLR` writer - Configures whether or not to clear I2S0_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S0_TASK_STOP_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S0_TASK_STOP_TX_ST_CLR` writer - Configures whether or not to clear I2S0_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S0_TASK_STOP_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_TASK_START_RX_ST_CLR` writer - Configures whether or not to clear I2S1_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S1_TASK_START_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_TASK_START_TX_ST_CLR` writer - Configures whether or not to clear I2S1_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S1_TASK_START_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_TASK_STOP_RX_ST_CLR` writer - Configures whether or not to clear I2S1_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S1_TASK_STOP_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S1_TASK_STOP_TX_ST_CLR` writer - Configures whether or not to clear I2S1_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S1_TASK_STOP_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_TASK_START_RX_ST_CLR` writer - Configures whether or not to clear I2S2_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S2_TASK_START_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_TASK_START_TX_ST_CLR` writer - Configures whether or not to clear I2S2_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S2_TASK_START_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_TASK_STOP_RX_ST_CLR` writer - Configures whether or not to clear I2S2_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S2_TASK_STOP_RX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2S2_TASK_STOP_TX_ST_CLR` writer - Configures whether or not to clear I2S2_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type I2S2_TASK_STOP_TX_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ULP_TASK_WAKEUP_CPU_ST_CLR` writer - Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ULP_TASK_WAKEUP_CPU_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ULP_TASK_INT_CPU_ST_CLR` writer - Configures whether or not to clear ULP_task_int_cpu trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type ULP_TASK_INT_CPU_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_TASK_START_ST_CLR` writer - Configures whether or not to clear RTC_task_start trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type RTC_TASK_START_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_TASK_STOP_ST_CLR` writer - Configures whether or not to clear RTC_task_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type RTC_TASK_STOP_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_TASK_CLR_ST_CLR` writer - Configures whether or not to clear RTC_task_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type RTC_TASK_CLR_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_TASK_TRIGGERFLW_ST_CLR` writer - Configures whether or not to clear RTC_task_triggerflw trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type RTC_TASK_TRIGGERFLW_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_IN_START_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_TASK_IN_START_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_IN_START_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_TASK_IN_START_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_IN_START_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_TASK_IN_START_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AHB_TASK_OUT_START_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_TASK_IN_START_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_TASK_IN_START_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_TASK_IN_START_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_TASK_IN_START_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear REGDMA_task_start0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_task_start0_st_clr(&mut self) -> REGDMA_TASK_START0_ST_CLR_W { + REGDMA_TASK_START0_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear REGDMA_task_start1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_task_start1_st_clr(&mut self) -> REGDMA_TASK_START1_ST_CLR_W { + REGDMA_TASK_START1_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear REGDMA_task_start2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_task_start2_st_clr(&mut self) -> REGDMA_TASK_START2_ST_CLR_W { + REGDMA_TASK_START2_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear REGDMA_task_start3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn regdma_task_start3_st_clr(&mut self) -> REGDMA_TASK_START3_ST_CLR_W { + REGDMA_TASK_START3_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tmpsnsr_task_start_sample_st_clr( + &mut self, + ) -> TMPSNSR_TASK_START_SAMPLE_ST_CLR_W { + TMPSNSR_TASK_START_SAMPLE_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn tmpsnsr_task_stop_sample_st_clr( + &mut self, + ) -> TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_W { + TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear I2S0_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s0_task_start_rx_st_clr(&mut self) -> I2S0_TASK_START_RX_ST_CLR_W { + I2S0_TASK_START_RX_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear I2S0_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s0_task_start_tx_st_clr(&mut self) -> I2S0_TASK_START_TX_ST_CLR_W { + I2S0_TASK_START_TX_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear I2S0_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s0_task_stop_rx_st_clr(&mut self) -> I2S0_TASK_STOP_RX_ST_CLR_W { + I2S0_TASK_STOP_RX_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear I2S0_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s0_task_stop_tx_st_clr(&mut self) -> I2S0_TASK_STOP_TX_ST_CLR_W { + I2S0_TASK_STOP_TX_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear I2S1_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s1_task_start_rx_st_clr(&mut self) -> I2S1_TASK_START_RX_ST_CLR_W { + I2S1_TASK_START_RX_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear I2S1_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s1_task_start_tx_st_clr(&mut self) -> I2S1_TASK_START_TX_ST_CLR_W { + I2S1_TASK_START_TX_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear I2S1_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s1_task_stop_rx_st_clr(&mut self) -> I2S1_TASK_STOP_RX_ST_CLR_W { + I2S1_TASK_STOP_RX_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear I2S1_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s1_task_stop_tx_st_clr(&mut self) -> I2S1_TASK_STOP_TX_ST_CLR_W { + I2S1_TASK_STOP_TX_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear I2S2_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s2_task_start_rx_st_clr(&mut self) -> I2S2_TASK_START_RX_ST_CLR_W { + I2S2_TASK_START_RX_ST_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Configures whether or not to clear I2S2_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s2_task_start_tx_st_clr(&mut self) -> I2S2_TASK_START_TX_ST_CLR_W { + I2S2_TASK_START_TX_ST_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Configures whether or not to clear I2S2_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s2_task_stop_rx_st_clr(&mut self) -> I2S2_TASK_STOP_RX_ST_CLR_W { + I2S2_TASK_STOP_RX_ST_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Configures whether or not to clear I2S2_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn i2s2_task_stop_tx_st_clr(&mut self) -> I2S2_TASK_STOP_TX_ST_CLR_W { + I2S2_TASK_STOP_TX_ST_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ulp_task_wakeup_cpu_st_clr( + &mut self, + ) -> ULP_TASK_WAKEUP_CPU_ST_CLR_W { + ULP_TASK_WAKEUP_CPU_ST_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Configures whether or not to clear ULP_task_int_cpu trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn ulp_task_int_cpu_st_clr(&mut self) -> ULP_TASK_INT_CPU_ST_CLR_W { + ULP_TASK_INT_CPU_ST_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - Configures whether or not to clear RTC_task_start trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn rtc_task_start_st_clr(&mut self) -> RTC_TASK_START_ST_CLR_W { + RTC_TASK_START_ST_CLR_W::new(self, 20) + } + #[doc = "Bit 21 - Configures whether or not to clear RTC_task_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn rtc_task_stop_st_clr(&mut self) -> RTC_TASK_STOP_ST_CLR_W { + RTC_TASK_STOP_ST_CLR_W::new(self, 21) + } + #[doc = "Bit 22 - Configures whether or not to clear RTC_task_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn rtc_task_clr_st_clr(&mut self) -> RTC_TASK_CLR_ST_CLR_W { + RTC_TASK_CLR_ST_CLR_W::new(self, 22) + } + #[doc = "Bit 23 - Configures whether or not to clear RTC_task_triggerflw trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn rtc_task_triggerflw_st_clr( + &mut self, + ) -> RTC_TASK_TRIGGERFLW_ST_CLR_W { + RTC_TASK_TRIGGERFLW_ST_CLR_W::new(self, 23) + } + #[doc = "Bit 24 - Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_in_start_ch0_st_clr( + &mut self, + ) -> PDMA_AHB_TASK_IN_START_CH0_ST_CLR_W { + PDMA_AHB_TASK_IN_START_CH0_ST_CLR_W::new(self, 24) + } + #[doc = "Bit 25 - Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_in_start_ch1_st_clr( + &mut self, + ) -> PDMA_AHB_TASK_IN_START_CH1_ST_CLR_W { + PDMA_AHB_TASK_IN_START_CH1_ST_CLR_W::new(self, 25) + } + #[doc = "Bit 26 - Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_in_start_ch2_st_clr( + &mut self, + ) -> PDMA_AHB_TASK_IN_START_CH2_ST_CLR_W { + PDMA_AHB_TASK_IN_START_CH2_ST_CLR_W::new(self, 26) + } + #[doc = "Bit 27 - Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_out_start_ch0_st_clr( + &mut self, + ) -> PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_W { + PDMA_AHB_TASK_OUT_START_CH0_ST_CLR_W::new(self, 27) + } + #[doc = "Bit 28 - Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_out_start_ch1_st_clr( + &mut self, + ) -> PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_W { + PDMA_AHB_TASK_OUT_START_CH1_ST_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_ahb_task_out_start_ch2_st_clr( + &mut self, + ) -> PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_W { + PDMA_AHB_TASK_OUT_START_CH2_ST_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_in_start_ch0_st_clr( + &mut self, + ) -> PDMA_AXI_TASK_IN_START_CH0_ST_CLR_W { + PDMA_AXI_TASK_IN_START_CH0_ST_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_in_start_ch1_st_clr( + &mut self, + ) -> PDMA_AXI_TASK_IN_START_CH1_ST_CLR_W { + PDMA_AXI_TASK_IN_START_CH1_ST_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st5_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST5_CLR_SPEC; +impl crate::RegisterSpec for TASK_ST5_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`task_st5_clr::W`](W) writer structure"] +impl crate::Writable for TASK_ST5_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST5_CLR to value 0"] +impl crate::Resettable for TASK_ST5_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st6.rs b/esp32p4/src/soc_etm/task_st6.rs new file mode 100644 index 0000000000..e850385ad8 --- /dev/null +++ b/esp32p4/src/soc_etm/task_st6.rs @@ -0,0 +1,350 @@ +#[doc = "Register `TASK_ST6` reader"] +pub type R = crate::R; +#[doc = "Register `TASK_ST6` writer"] +pub type W = crate::W; +#[doc = "Field `PDMA_AXI_TASK_IN_START_CH2_ST` reader - Represents PDMA_AXI_task_in_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_IN_START_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_TASK_IN_START_CH2_ST` writer - Represents PDMA_AXI_task_in_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_IN_START_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_TASK_OUT_START_CH0_ST` reader - Represents PDMA_AXI_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_OUT_START_CH0_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_TASK_OUT_START_CH0_ST` writer - Represents PDMA_AXI_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_OUT_START_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_TASK_OUT_START_CH1_ST` reader - Represents PDMA_AXI_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_OUT_START_CH1_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_TASK_OUT_START_CH1_ST` writer - Represents PDMA_AXI_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_OUT_START_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_TASK_OUT_START_CH2_ST` reader - Represents PDMA_AXI_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_OUT_START_CH2_ST_R = crate::BitReader; +#[doc = "Field `PDMA_AXI_TASK_OUT_START_CH2_ST` writer - Represents PDMA_AXI_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PDMA_AXI_TASK_OUT_START_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PMU_TASK_SLEEP_REQ_ST` reader - Represents PMU_task_sleep_req trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PMU_TASK_SLEEP_REQ_ST_R = crate::BitReader; +#[doc = "Field `PMU_TASK_SLEEP_REQ_ST` writer - Represents PMU_task_sleep_req trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type PMU_TASK_SLEEP_REQ_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_IN_START_CH0_ST` reader - Represents DMA2D_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_IN_START_CH0_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_TASK_IN_START_CH0_ST` writer - Represents DMA2D_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_IN_START_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_IN_START_CH1_ST` reader - Represents DMA2D_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_IN_START_CH1_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_TASK_IN_START_CH1_ST` writer - Represents DMA2D_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_IN_START_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_IN_DSCR_READY_CH0_ST` reader - Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_IN_DSCR_READY_CH0_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_TASK_IN_DSCR_READY_CH0_ST` writer - Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_IN_DSCR_READY_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_IN_DSCR_READY_CH1_ST` reader - Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_IN_DSCR_READY_CH1_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_TASK_IN_DSCR_READY_CH1_ST` writer - Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_IN_DSCR_READY_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_START_CH0_ST` reader - Represents DMA2D_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_START_CH0_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_TASK_OUT_START_CH0_ST` writer - Represents DMA2D_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_START_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_START_CH1_ST` reader - Represents DMA2D_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_START_CH1_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_TASK_OUT_START_CH1_ST` writer - Represents DMA2D_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_START_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_START_CH2_ST` reader - Represents DMA2D_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_START_CH2_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_TASK_OUT_START_CH2_ST` writer - Represents DMA2D_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_START_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_DSCR_READY_CH0_ST` reader - Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_DSCR_READY_CH0_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_TASK_OUT_DSCR_READY_CH0_ST` writer - Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_DSCR_READY_CH0_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_DSCR_READY_CH1_ST` reader - Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_DSCR_READY_CH1_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_TASK_OUT_DSCR_READY_CH1_ST` writer - Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_DSCR_READY_CH1_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_DSCR_READY_CH2_ST` reader - Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_DSCR_READY_CH2_ST_R = crate::BitReader; +#[doc = "Field `DMA2D_TASK_OUT_DSCR_READY_CH2_ST` writer - Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] +pub type DMA2D_TASK_OUT_DSCR_READY_CH2_ST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Represents PDMA_AXI_task_in_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_task_in_start_ch2_st(&self) -> PDMA_AXI_TASK_IN_START_CH2_ST_R { + PDMA_AXI_TASK_IN_START_CH2_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Represents PDMA_AXI_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_task_out_start_ch0_st(&self) -> PDMA_AXI_TASK_OUT_START_CH0_ST_R { + PDMA_AXI_TASK_OUT_START_CH0_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Represents PDMA_AXI_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_task_out_start_ch1_st(&self) -> PDMA_AXI_TASK_OUT_START_CH1_ST_R { + PDMA_AXI_TASK_OUT_START_CH1_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Represents PDMA_AXI_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pdma_axi_task_out_start_ch2_st(&self) -> PDMA_AXI_TASK_OUT_START_CH2_ST_R { + PDMA_AXI_TASK_OUT_START_CH2_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Represents PMU_task_sleep_req trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn pmu_task_sleep_req_st(&self) -> PMU_TASK_SLEEP_REQ_ST_R { + PMU_TASK_SLEEP_REQ_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Represents DMA2D_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_task_in_start_ch0_st(&self) -> DMA2D_TASK_IN_START_CH0_ST_R { + DMA2D_TASK_IN_START_CH0_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Represents DMA2D_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_task_in_start_ch1_st(&self) -> DMA2D_TASK_IN_START_CH1_ST_R { + DMA2D_TASK_IN_START_CH1_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_task_in_dscr_ready_ch0_st(&self) -> DMA2D_TASK_IN_DSCR_READY_CH0_ST_R { + DMA2D_TASK_IN_DSCR_READY_CH0_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_task_in_dscr_ready_ch1_st(&self) -> DMA2D_TASK_IN_DSCR_READY_CH1_ST_R { + DMA2D_TASK_IN_DSCR_READY_CH1_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Represents DMA2D_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_task_out_start_ch0_st(&self) -> DMA2D_TASK_OUT_START_CH0_ST_R { + DMA2D_TASK_OUT_START_CH0_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Represents DMA2D_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_task_out_start_ch1_st(&self) -> DMA2D_TASK_OUT_START_CH1_ST_R { + DMA2D_TASK_OUT_START_CH1_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Represents DMA2D_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_task_out_start_ch2_st(&self) -> DMA2D_TASK_OUT_START_CH2_ST_R { + DMA2D_TASK_OUT_START_CH2_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_task_out_dscr_ready_ch0_st(&self) -> DMA2D_TASK_OUT_DSCR_READY_CH0_ST_R { + DMA2D_TASK_OUT_DSCR_READY_CH0_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_task_out_dscr_ready_ch1_st(&self) -> DMA2D_TASK_OUT_DSCR_READY_CH1_ST_R { + DMA2D_TASK_OUT_DSCR_READY_CH1_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + pub fn dma2d_task_out_dscr_ready_ch2_st(&self) -> DMA2D_TASK_OUT_DSCR_READY_CH2_ST_R { + DMA2D_TASK_OUT_DSCR_READY_CH2_ST_R::new(((self.bits >> 14) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TASK_ST6") + .field( + "pdma_axi_task_in_start_ch2_st", + &format_args!("{}", self.pdma_axi_task_in_start_ch2_st().bit()), + ) + .field( + "pdma_axi_task_out_start_ch0_st", + &format_args!("{}", self.pdma_axi_task_out_start_ch0_st().bit()), + ) + .field( + "pdma_axi_task_out_start_ch1_st", + &format_args!("{}", self.pdma_axi_task_out_start_ch1_st().bit()), + ) + .field( + "pdma_axi_task_out_start_ch2_st", + &format_args!("{}", self.pdma_axi_task_out_start_ch2_st().bit()), + ) + .field( + "pmu_task_sleep_req_st", + &format_args!("{}", self.pmu_task_sleep_req_st().bit()), + ) + .field( + "dma2d_task_in_start_ch0_st", + &format_args!("{}", self.dma2d_task_in_start_ch0_st().bit()), + ) + .field( + "dma2d_task_in_start_ch1_st", + &format_args!("{}", self.dma2d_task_in_start_ch1_st().bit()), + ) + .field( + "dma2d_task_in_dscr_ready_ch0_st", + &format_args!("{}", self.dma2d_task_in_dscr_ready_ch0_st().bit()), + ) + .field( + "dma2d_task_in_dscr_ready_ch1_st", + &format_args!("{}", self.dma2d_task_in_dscr_ready_ch1_st().bit()), + ) + .field( + "dma2d_task_out_start_ch0_st", + &format_args!("{}", self.dma2d_task_out_start_ch0_st().bit()), + ) + .field( + "dma2d_task_out_start_ch1_st", + &format_args!("{}", self.dma2d_task_out_start_ch1_st().bit()), + ) + .field( + "dma2d_task_out_start_ch2_st", + &format_args!("{}", self.dma2d_task_out_start_ch2_st().bit()), + ) + .field( + "dma2d_task_out_dscr_ready_ch0_st", + &format_args!("{}", self.dma2d_task_out_dscr_ready_ch0_st().bit()), + ) + .field( + "dma2d_task_out_dscr_ready_ch1_st", + &format_args!("{}", self.dma2d_task_out_dscr_ready_ch1_st().bit()), + ) + .field( + "dma2d_task_out_dscr_ready_ch2_st", + &format_args!("{}", self.dma2d_task_out_dscr_ready_ch2_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Represents PDMA_AXI_task_in_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_in_start_ch2_st( + &mut self, + ) -> PDMA_AXI_TASK_IN_START_CH2_ST_W { + PDMA_AXI_TASK_IN_START_CH2_ST_W::new(self, 0) + } + #[doc = "Bit 1 - Represents PDMA_AXI_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_out_start_ch0_st( + &mut self, + ) -> PDMA_AXI_TASK_OUT_START_CH0_ST_W { + PDMA_AXI_TASK_OUT_START_CH0_ST_W::new(self, 1) + } + #[doc = "Bit 2 - Represents PDMA_AXI_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_out_start_ch1_st( + &mut self, + ) -> PDMA_AXI_TASK_OUT_START_CH1_ST_W { + PDMA_AXI_TASK_OUT_START_CH1_ST_W::new(self, 2) + } + #[doc = "Bit 3 - Represents PDMA_AXI_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_out_start_ch2_st( + &mut self, + ) -> PDMA_AXI_TASK_OUT_START_CH2_ST_W { + PDMA_AXI_TASK_OUT_START_CH2_ST_W::new(self, 3) + } + #[doc = "Bit 4 - Represents PMU_task_sleep_req trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn pmu_task_sleep_req_st(&mut self) -> PMU_TASK_SLEEP_REQ_ST_W { + PMU_TASK_SLEEP_REQ_ST_W::new(self, 4) + } + #[doc = "Bit 5 - Represents DMA2D_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_in_start_ch0_st(&mut self) -> DMA2D_TASK_IN_START_CH0_ST_W { + DMA2D_TASK_IN_START_CH0_ST_W::new(self, 5) + } + #[doc = "Bit 6 - Represents DMA2D_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_in_start_ch1_st(&mut self) -> DMA2D_TASK_IN_START_CH1_ST_W { + DMA2D_TASK_IN_START_CH1_ST_W::new(self, 6) + } + #[doc = "Bit 7 - Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_in_dscr_ready_ch0_st( + &mut self, + ) -> DMA2D_TASK_IN_DSCR_READY_CH0_ST_W { + DMA2D_TASK_IN_DSCR_READY_CH0_ST_W::new(self, 7) + } + #[doc = "Bit 8 - Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_in_dscr_ready_ch1_st( + &mut self, + ) -> DMA2D_TASK_IN_DSCR_READY_CH1_ST_W { + DMA2D_TASK_IN_DSCR_READY_CH1_ST_W::new(self, 8) + } + #[doc = "Bit 9 - Represents DMA2D_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_start_ch0_st(&mut self) -> DMA2D_TASK_OUT_START_CH0_ST_W { + DMA2D_TASK_OUT_START_CH0_ST_W::new(self, 9) + } + #[doc = "Bit 10 - Represents DMA2D_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_start_ch1_st(&mut self) -> DMA2D_TASK_OUT_START_CH1_ST_W { + DMA2D_TASK_OUT_START_CH1_ST_W::new(self, 10) + } + #[doc = "Bit 11 - Represents DMA2D_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_start_ch2_st(&mut self) -> DMA2D_TASK_OUT_START_CH2_ST_W { + DMA2D_TASK_OUT_START_CH2_ST_W::new(self, 11) + } + #[doc = "Bit 12 - Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_dscr_ready_ch0_st( + &mut self, + ) -> DMA2D_TASK_OUT_DSCR_READY_CH0_ST_W { + DMA2D_TASK_OUT_DSCR_READY_CH0_ST_W::new(self, 12) + } + #[doc = "Bit 13 - Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_dscr_ready_ch1_st( + &mut self, + ) -> DMA2D_TASK_OUT_DSCR_READY_CH1_ST_W { + DMA2D_TASK_OUT_DSCR_READY_CH1_ST_W::new(self, 13) + } + #[doc = "Bit 14 - Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_dscr_ready_ch2_st( + &mut self, + ) -> DMA2D_TASK_OUT_DSCR_READY_CH2_ST_W { + DMA2D_TASK_OUT_DSCR_READY_CH2_ST_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST6_SPEC; +impl crate::RegisterSpec for TASK_ST6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`task_st6::R`](R) reader structure"] +impl crate::Readable for TASK_ST6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`task_st6::W`](W) writer structure"] +impl crate::Writable for TASK_ST6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST6 to value 0"] +impl crate::Resettable for TASK_ST6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/soc_etm/task_st6_clr.rs b/esp32p4/src/soc_etm/task_st6_clr.rs new file mode 100644 index 0000000000..e51d192a54 --- /dev/null +++ b/esp32p4/src/soc_etm/task_st6_clr.rs @@ -0,0 +1,182 @@ +#[doc = "Register `TASK_ST6_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `PDMA_AXI_TASK_IN_START_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_TASK_IN_START_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_TASK_OUT_START_CH0_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_TASK_OUT_START_CH1_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDMA_AXI_TASK_OUT_START_CH2_ST_CLR` writer - Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PMU_TASK_SLEEP_REQ_ST_CLR` writer - Configures whether or not to clear PMU_task_sleep_req trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type PMU_TASK_SLEEP_REQ_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_IN_START_CH0_ST_CLR` writer - Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_TASK_IN_START_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_IN_START_CH1_ST_CLR` writer - Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_TASK_IN_START_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR` writer - Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR` writer - Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_START_CH0_ST_CLR` writer - Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_TASK_OUT_START_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_START_CH1_ST_CLR` writer - Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_TASK_OUT_START_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_START_CH2_ST_CLR` writer - Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_TASK_OUT_START_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR` writer - Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR` writer - Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR` writer - Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] +pub type DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_in_start_ch2_st_clr( + &mut self, + ) -> PDMA_AXI_TASK_IN_START_CH2_ST_CLR_W { + PDMA_AXI_TASK_IN_START_CH2_ST_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_out_start_ch0_st_clr( + &mut self, + ) -> PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_W { + PDMA_AXI_TASK_OUT_START_CH0_ST_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_out_start_ch1_st_clr( + &mut self, + ) -> PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_W { + PDMA_AXI_TASK_OUT_START_CH1_ST_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pdma_axi_task_out_start_ch2_st_clr( + &mut self, + ) -> PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_W { + PDMA_AXI_TASK_OUT_START_CH2_ST_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Configures whether or not to clear PMU_task_sleep_req trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn pmu_task_sleep_req_st_clr(&mut self) -> PMU_TASK_SLEEP_REQ_ST_CLR_W { + PMU_TASK_SLEEP_REQ_ST_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_in_start_ch0_st_clr( + &mut self, + ) -> DMA2D_TASK_IN_START_CH0_ST_CLR_W { + DMA2D_TASK_IN_START_CH0_ST_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_in_start_ch1_st_clr( + &mut self, + ) -> DMA2D_TASK_IN_START_CH1_ST_CLR_W { + DMA2D_TASK_IN_START_CH1_ST_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_in_dscr_ready_ch0_st_clr( + &mut self, + ) -> DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_W { + DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_in_dscr_ready_ch1_st_clr( + &mut self, + ) -> DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_W { + DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_start_ch0_st_clr( + &mut self, + ) -> DMA2D_TASK_OUT_START_CH0_ST_CLR_W { + DMA2D_TASK_OUT_START_CH0_ST_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_start_ch1_st_clr( + &mut self, + ) -> DMA2D_TASK_OUT_START_CH1_ST_CLR_W { + DMA2D_TASK_OUT_START_CH1_ST_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_start_ch2_st_clr( + &mut self, + ) -> DMA2D_TASK_OUT_START_CH2_ST_CLR_W { + DMA2D_TASK_OUT_START_CH2_ST_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_dscr_ready_ch0_st_clr( + &mut self, + ) -> DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_W { + DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_dscr_ready_ch1_st_clr( + &mut self, + ) -> DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_W { + DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear"] + #[inline(always)] + #[must_use] + pub fn dma2d_task_out_dscr_ready_ch2_st_clr( + &mut self, + ) -> DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_W { + DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tasks trigger status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st6_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TASK_ST6_CLR_SPEC; +impl crate::RegisterSpec for TASK_ST6_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`task_st6_clr::W`](W) writer structure"] +impl crate::Writable for TASK_ST6_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TASK_ST6_CLR to value 0"] +impl crate::Resettable for TASK_ST6_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0.rs b/esp32p4/src/spi0.rs new file mode 100644 index 0000000000..eeddda76ff --- /dev/null +++ b/esp32p4/src/spi0.rs @@ -0,0 +1,797 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + spi_mem_cmd: SPI_MEM_CMD, + _reserved1: [u8; 0x04], + spi_mem_ctrl: SPI_MEM_CTRL, + spi_mem_ctrl1: SPI_MEM_CTRL1, + spi_mem_ctrl2: SPI_MEM_CTRL2, + spi_mem_clock: SPI_MEM_CLOCK, + spi_mem_user: SPI_MEM_USER, + spi_mem_user1: SPI_MEM_USER1, + spi_mem_user2: SPI_MEM_USER2, + _reserved8: [u8; 0x08], + spi_mem_rd_status: SPI_MEM_RD_STATUS, + _reserved9: [u8; 0x04], + spi_mem_misc: SPI_MEM_MISC, + _reserved10: [u8; 0x04], + spi_mem_cache_fctrl: SPI_MEM_CACHE_FCTRL, + spi_mem_cache_sctrl: SPI_MEM_CACHE_SCTRL, + spi_mem_sram_cmd: SPI_MEM_SRAM_CMD, + spi_mem_sram_drd_cmd: SPI_MEM_SRAM_DRD_CMD, + spi_mem_sram_dwr_cmd: SPI_MEM_SRAM_DWR_CMD, + spi_mem_sram_clk: SPI_MEM_SRAM_CLK, + spi_mem_fsm: SPI_MEM_FSM, + _reserved17: [u8; 0x68], + spi_mem_int_ena: SPI_MEM_INT_ENA, + spi_mem_int_clr: SPI_MEM_INT_CLR, + spi_mem_int_raw: SPI_MEM_INT_RAW, + spi_mem_int_st: SPI_MEM_INT_ST, + _reserved21: [u8; 0x04], + spi_mem_ddr: SPI_MEM_DDR, + spi_smem_ddr: SPI_SMEM_DDR, + _reserved23: [u8; 0x24], + spi_fmem_pms_attr: [SPI_FMEM_PMS_ATTR; 4], + spi_fmem_pms_addr: [SPI_FMEM_PMS_ADDR; 4], + spi_fmem_pms_size: [SPI_FMEM_PMS_SIZE; 4], + spi_smem_pms_attr: [SPI_SMEM_PMS_ATTR; 4], + spi_smem_pms_addr: [SPI_SMEM_PMS_ADDR; 4], + spi_smem_pms_size: [SPI_SMEM_PMS_SIZE; 4], + _reserved29: [u8; 0x04], + spi_mem_pms_reject: SPI_MEM_PMS_REJECT, + spi_mem_ecc_ctrl: SPI_MEM_ECC_CTRL, + spi_mem_ecc_err_addr: SPI_MEM_ECC_ERR_ADDR, + spi_mem_axi_err_addr: SPI_MEM_AXI_ERR_ADDR, + spi_smem_ecc_ctrl: SPI_SMEM_ECC_CTRL, + spi_smem_axi_addr_ctrl: SPI_SMEM_AXI_ADDR_CTRL, + spi_mem_axi_err_resp_en: SPI_MEM_AXI_ERR_RESP_EN, + spi_mem_timing_cali: SPI_MEM_TIMING_CALI, + spi_mem_din_mode: SPI_MEM_DIN_MODE, + spi_mem_din_num: SPI_MEM_DIN_NUM, + spi_mem_dout_mode: SPI_MEM_DOUT_MODE, + spi_smem_timing_cali: SPI_SMEM_TIMING_CALI, + spi_smem_din_mode: SPI_SMEM_DIN_MODE, + spi_smem_din_num: SPI_SMEM_DIN_NUM, + spi_smem_dout_mode: SPI_SMEM_DOUT_MODE, + spi_smem_ac: SPI_SMEM_AC, + spi_smem_din_hex_mode: SPI_SMEM_DIN_HEX_MODE, + spi_smem_din_hex_num: SPI_SMEM_DIN_HEX_NUM, + spi_smem_dout_hex_mode: SPI_SMEM_DOUT_HEX_MODE, + _reserved48: [u8; 0x50], + spi_mem_clock_gate: SPI_MEM_CLOCK_GATE, + _reserved49: [u8; 0xfc], + spi_mem_xts_plain_base: SPI_MEM_XTS_PLAIN_BASE, + _reserved50: [u8; 0x3c], + spi_mem_xts_linesize: SPI_MEM_XTS_LINESIZE, + spi_mem_xts_destination: SPI_MEM_XTS_DESTINATION, + spi_mem_xts_physical_address: SPI_MEM_XTS_PHYSICAL_ADDRESS, + spi_mem_xts_trigger: SPI_MEM_XTS_TRIGGER, + spi_mem_xts_release: SPI_MEM_XTS_RELEASE, + spi_mem_xts_destroy: SPI_MEM_XTS_DESTROY, + spi_mem_xts_state: SPI_MEM_XTS_STATE, + spi_mem_xts_date: SPI_MEM_XTS_DATE, + _reserved58: [u8; 0x1c], + spi_mem_mmu_item_content: SPI_MEM_MMU_ITEM_CONTENT, + spi_mem_mmu_item_index: SPI_MEM_MMU_ITEM_INDEX, + spi_mem_mmu_power_ctrl: SPI_MEM_MMU_POWER_CTRL, + spi_mem_dpa_ctrl: SPI_MEM_DPA_CTRL, + _reserved62: [u8; 0x64], + spi_mem_registerrnd_eco_high: SPI_MEM_REGISTERRND_ECO_HIGH, + spi_mem_registerrnd_eco_low: SPI_MEM_REGISTERRND_ECO_LOW, + _reserved64: [u8; 0x04], + spi_mem_date: SPI_MEM_DATE, +} +impl RegisterBlock { + #[doc = "0x00 - SPI0 FSM status register"] + #[inline(always)] + pub const fn spi_mem_cmd(&self) -> &SPI_MEM_CMD { + &self.spi_mem_cmd + } + #[doc = "0x08 - SPI0 control register."] + #[inline(always)] + pub const fn spi_mem_ctrl(&self) -> &SPI_MEM_CTRL { + &self.spi_mem_ctrl + } + #[doc = "0x0c - SPI0 control1 register."] + #[inline(always)] + pub const fn spi_mem_ctrl1(&self) -> &SPI_MEM_CTRL1 { + &self.spi_mem_ctrl1 + } + #[doc = "0x10 - SPI0 control2 register."] + #[inline(always)] + pub const fn spi_mem_ctrl2(&self) -> &SPI_MEM_CTRL2 { + &self.spi_mem_ctrl2 + } + #[doc = "0x14 - SPI clock division control register."] + #[inline(always)] + pub const fn spi_mem_clock(&self) -> &SPI_MEM_CLOCK { + &self.spi_mem_clock + } + #[doc = "0x18 - SPI0 user register."] + #[inline(always)] + pub const fn spi_mem_user(&self) -> &SPI_MEM_USER { + &self.spi_mem_user + } + #[doc = "0x1c - SPI0 user1 register."] + #[inline(always)] + pub const fn spi_mem_user1(&self) -> &SPI_MEM_USER1 { + &self.spi_mem_user1 + } + #[doc = "0x20 - SPI0 user2 register."] + #[inline(always)] + pub const fn spi_mem_user2(&self) -> &SPI_MEM_USER2 { + &self.spi_mem_user2 + } + #[doc = "0x2c - SPI0 read control register."] + #[inline(always)] + pub const fn spi_mem_rd_status(&self) -> &SPI_MEM_RD_STATUS { + &self.spi_mem_rd_status + } + #[doc = "0x34 - SPI0 misc register"] + #[inline(always)] + pub const fn spi_mem_misc(&self) -> &SPI_MEM_MISC { + &self.spi_mem_misc + } + #[doc = "0x3c - SPI0 bit mode control register."] + #[inline(always)] + pub const fn spi_mem_cache_fctrl(&self) -> &SPI_MEM_CACHE_FCTRL { + &self.spi_mem_cache_fctrl + } + #[doc = "0x40 - SPI0 external RAM control register"] + #[inline(always)] + pub const fn spi_mem_cache_sctrl(&self) -> &SPI_MEM_CACHE_SCTRL { + &self.spi_mem_cache_sctrl + } + #[doc = "0x44 - SPI0 external RAM mode control register"] + #[inline(always)] + pub const fn spi_mem_sram_cmd(&self) -> &SPI_MEM_SRAM_CMD { + &self.spi_mem_sram_cmd + } + #[doc = "0x48 - SPI0 external RAM DDR read command control register"] + #[inline(always)] + pub const fn spi_mem_sram_drd_cmd(&self) -> &SPI_MEM_SRAM_DRD_CMD { + &self.spi_mem_sram_drd_cmd + } + #[doc = "0x4c - SPI0 external RAM DDR write command control register"] + #[inline(always)] + pub const fn spi_mem_sram_dwr_cmd(&self) -> &SPI_MEM_SRAM_DWR_CMD { + &self.spi_mem_sram_dwr_cmd + } + #[doc = "0x50 - SPI0 external RAM clock control register"] + #[inline(always)] + pub const fn spi_mem_sram_clk(&self) -> &SPI_MEM_SRAM_CLK { + &self.spi_mem_sram_clk + } + #[doc = "0x54 - SPI0 FSM status register"] + #[inline(always)] + pub const fn spi_mem_fsm(&self) -> &SPI_MEM_FSM { + &self.spi_mem_fsm + } + #[doc = "0xc0 - SPI0 interrupt enable register"] + #[inline(always)] + pub const fn spi_mem_int_ena(&self) -> &SPI_MEM_INT_ENA { + &self.spi_mem_int_ena + } + #[doc = "0xc4 - SPI0 interrupt clear register"] + #[inline(always)] + pub const fn spi_mem_int_clr(&self) -> &SPI_MEM_INT_CLR { + &self.spi_mem_int_clr + } + #[doc = "0xc8 - SPI0 interrupt raw register"] + #[inline(always)] + pub const fn spi_mem_int_raw(&self) -> &SPI_MEM_INT_RAW { + &self.spi_mem_int_raw + } + #[doc = "0xcc - SPI0 interrupt status register"] + #[inline(always)] + pub const fn spi_mem_int_st(&self) -> &SPI_MEM_INT_ST { + &self.spi_mem_int_st + } + #[doc = "0xd4 - SPI0 flash DDR mode control register"] + #[inline(always)] + pub const fn spi_mem_ddr(&self) -> &SPI_MEM_DDR { + &self.spi_mem_ddr + } + #[doc = "0xd8 - SPI0 external RAM DDR mode control register"] + #[inline(always)] + pub const fn spi_smem_ddr(&self) -> &SPI_SMEM_DDR { + &self.spi_smem_ddr + } + #[doc = "0x100..0x110 - MSPI flash PMS section %s attribute register"] + #[inline(always)] + pub const fn spi_fmem_pms_attr(&self, n: usize) -> &SPI_FMEM_PMS_ATTR { + &self.spi_fmem_pms_attr[n] + } + #[doc = "0x100 - MSPI flash PMS section 0 attribute register"] + #[inline(always)] + pub const fn spi_fmem_pms0_attr(&self) -> &SPI_FMEM_PMS_ATTR { + &self.spi_fmem_pms_attr(0) + } + #[doc = "0x104 - MSPI flash PMS section 1 attribute register"] + #[inline(always)] + pub const fn spi_fmem_pms1_attr(&self) -> &SPI_FMEM_PMS_ATTR { + &self.spi_fmem_pms_attr(1) + } + #[doc = "0x108 - MSPI flash PMS section 2 attribute register"] + #[inline(always)] + pub const fn spi_fmem_pms2_attr(&self) -> &SPI_FMEM_PMS_ATTR { + &self.spi_fmem_pms_attr(2) + } + #[doc = "0x10c - MSPI flash PMS section 3 attribute register"] + #[inline(always)] + pub const fn spi_fmem_pms3_attr(&self) -> &SPI_FMEM_PMS_ATTR { + &self.spi_fmem_pms_attr(3) + } + #[doc = "0x110..0x120 - SPI1 flash PMS section %s start address register"] + #[inline(always)] + pub const fn spi_fmem_pms_addr(&self, n: usize) -> &SPI_FMEM_PMS_ADDR { + &self.spi_fmem_pms_addr[n] + } + #[doc = "0x110 - SPI1 flash PMS section 0 start address register"] + #[inline(always)] + pub const fn spi_fmem_pms0_addr(&self) -> &SPI_FMEM_PMS_ADDR { + &self.spi_fmem_pms_addr(0) + } + #[doc = "0x114 - SPI1 flash PMS section 1 start address register"] + #[inline(always)] + pub const fn spi_fmem_pms1_addr(&self) -> &SPI_FMEM_PMS_ADDR { + &self.spi_fmem_pms_addr(1) + } + #[doc = "0x118 - SPI1 flash PMS section 2 start address register"] + #[inline(always)] + pub const fn spi_fmem_pms2_addr(&self) -> &SPI_FMEM_PMS_ADDR { + &self.spi_fmem_pms_addr(2) + } + #[doc = "0x11c - SPI1 flash PMS section 3 start address register"] + #[inline(always)] + pub const fn spi_fmem_pms3_addr(&self) -> &SPI_FMEM_PMS_ADDR { + &self.spi_fmem_pms_addr(3) + } + #[doc = "0x120..0x130 - SPI1 flash PMS section %s start address register"] + #[inline(always)] + pub const fn spi_fmem_pms_size(&self, n: usize) -> &SPI_FMEM_PMS_SIZE { + &self.spi_fmem_pms_size[n] + } + #[doc = "0x120 - SPI1 flash PMS section 0 start address register"] + #[inline(always)] + pub const fn spi_fmem_pms0_size(&self) -> &SPI_FMEM_PMS_SIZE { + &self.spi_fmem_pms_size(0) + } + #[doc = "0x124 - SPI1 flash PMS section 1 start address register"] + #[inline(always)] + pub const fn spi_fmem_pms1_size(&self) -> &SPI_FMEM_PMS_SIZE { + &self.spi_fmem_pms_size(1) + } + #[doc = "0x128 - SPI1 flash PMS section 2 start address register"] + #[inline(always)] + pub const fn spi_fmem_pms2_size(&self) -> &SPI_FMEM_PMS_SIZE { + &self.spi_fmem_pms_size(2) + } + #[doc = "0x12c - SPI1 flash PMS section 3 start address register"] + #[inline(always)] + pub const fn spi_fmem_pms3_size(&self) -> &SPI_FMEM_PMS_SIZE { + &self.spi_fmem_pms_size(3) + } + #[doc = "0x130..0x140 - SPI1 flash PMS section %s start address register"] + #[inline(always)] + pub const fn spi_smem_pms_attr(&self, n: usize) -> &SPI_SMEM_PMS_ATTR { + &self.spi_smem_pms_attr[n] + } + #[doc = "0x130 - SPI1 flash PMS section 0 start address register"] + #[inline(always)] + pub const fn spi_smem_pms0_attr(&self) -> &SPI_SMEM_PMS_ATTR { + &self.spi_smem_pms_attr(0) + } + #[doc = "0x134 - SPI1 flash PMS section 1 start address register"] + #[inline(always)] + pub const fn spi_smem_pms1_attr(&self) -> &SPI_SMEM_PMS_ATTR { + &self.spi_smem_pms_attr(1) + } + #[doc = "0x138 - SPI1 flash PMS section 2 start address register"] + #[inline(always)] + pub const fn spi_smem_pms2_attr(&self) -> &SPI_SMEM_PMS_ATTR { + &self.spi_smem_pms_attr(2) + } + #[doc = "0x13c - SPI1 flash PMS section 3 start address register"] + #[inline(always)] + pub const fn spi_smem_pms3_attr(&self) -> &SPI_SMEM_PMS_ATTR { + &self.spi_smem_pms_attr(3) + } + #[doc = "0x140..0x150 - SPI1 external RAM PMS section %s start address register"] + #[inline(always)] + pub const fn spi_smem_pms_addr(&self, n: usize) -> &SPI_SMEM_PMS_ADDR { + &self.spi_smem_pms_addr[n] + } + #[doc = "0x140 - SPI1 external RAM PMS section 0 start address register"] + #[inline(always)] + pub const fn spi_smem_pms0_addr(&self) -> &SPI_SMEM_PMS_ADDR { + &self.spi_smem_pms_addr(0) + } + #[doc = "0x144 - SPI1 external RAM PMS section 1 start address register"] + #[inline(always)] + pub const fn spi_smem_pms1_addr(&self) -> &SPI_SMEM_PMS_ADDR { + &self.spi_smem_pms_addr(1) + } + #[doc = "0x148 - SPI1 external RAM PMS section 2 start address register"] + #[inline(always)] + pub const fn spi_smem_pms2_addr(&self) -> &SPI_SMEM_PMS_ADDR { + &self.spi_smem_pms_addr(2) + } + #[doc = "0x14c - SPI1 external RAM PMS section 3 start address register"] + #[inline(always)] + pub const fn spi_smem_pms3_addr(&self) -> &SPI_SMEM_PMS_ADDR { + &self.spi_smem_pms_addr(3) + } + #[doc = "0x150..0x160 - SPI1 external RAM PMS section %s start address register"] + #[inline(always)] + pub const fn spi_smem_pms_size(&self, n: usize) -> &SPI_SMEM_PMS_SIZE { + &self.spi_smem_pms_size[n] + } + #[doc = "0x150 - SPI1 external RAM PMS section 0 start address register"] + #[inline(always)] + pub const fn spi_smem_pms0_size(&self) -> &SPI_SMEM_PMS_SIZE { + &self.spi_smem_pms_size(0) + } + #[doc = "0x154 - SPI1 external RAM PMS section 1 start address register"] + #[inline(always)] + pub const fn spi_smem_pms1_size(&self) -> &SPI_SMEM_PMS_SIZE { + &self.spi_smem_pms_size(1) + } + #[doc = "0x158 - SPI1 external RAM PMS section 2 start address register"] + #[inline(always)] + pub const fn spi_smem_pms2_size(&self) -> &SPI_SMEM_PMS_SIZE { + &self.spi_smem_pms_size(2) + } + #[doc = "0x15c - SPI1 external RAM PMS section 3 start address register"] + #[inline(always)] + pub const fn spi_smem_pms3_size(&self) -> &SPI_SMEM_PMS_SIZE { + &self.spi_smem_pms_size(3) + } + #[doc = "0x164 - SPI1 access reject register"] + #[inline(always)] + pub const fn spi_mem_pms_reject(&self) -> &SPI_MEM_PMS_REJECT { + &self.spi_mem_pms_reject + } + #[doc = "0x168 - MSPI ECC control register"] + #[inline(always)] + pub const fn spi_mem_ecc_ctrl(&self) -> &SPI_MEM_ECC_CTRL { + &self.spi_mem_ecc_ctrl + } + #[doc = "0x16c - MSPI ECC error address register"] + #[inline(always)] + pub const fn spi_mem_ecc_err_addr(&self) -> &SPI_MEM_ECC_ERR_ADDR { + &self.spi_mem_ecc_err_addr + } + #[doc = "0x170 - SPI0 AXI request error address."] + #[inline(always)] + pub const fn spi_mem_axi_err_addr(&self) -> &SPI_MEM_AXI_ERR_ADDR { + &self.spi_mem_axi_err_addr + } + #[doc = "0x174 - MSPI ECC control register"] + #[inline(always)] + pub const fn spi_smem_ecc_ctrl(&self) -> &SPI_SMEM_ECC_CTRL { + &self.spi_smem_ecc_ctrl + } + #[doc = "0x178 - SPI0 AXI address control register"] + #[inline(always)] + pub const fn spi_smem_axi_addr_ctrl(&self) -> &SPI_SMEM_AXI_ADDR_CTRL { + &self.spi_smem_axi_addr_ctrl + } + #[doc = "0x17c - SPI0 AXI error response enable register"] + #[inline(always)] + pub const fn spi_mem_axi_err_resp_en(&self) -> &SPI_MEM_AXI_ERR_RESP_EN { + &self.spi_mem_axi_err_resp_en + } + #[doc = "0x180 - SPI0 flash timing calibration register"] + #[inline(always)] + pub const fn spi_mem_timing_cali(&self) -> &SPI_MEM_TIMING_CALI { + &self.spi_mem_timing_cali + } + #[doc = "0x184 - MSPI flash input timing delay mode control register"] + #[inline(always)] + pub const fn spi_mem_din_mode(&self) -> &SPI_MEM_DIN_MODE { + &self.spi_mem_din_mode + } + #[doc = "0x188 - MSPI flash input timing delay number control register"] + #[inline(always)] + pub const fn spi_mem_din_num(&self) -> &SPI_MEM_DIN_NUM { + &self.spi_mem_din_num + } + #[doc = "0x18c - MSPI flash output timing adjustment control register"] + #[inline(always)] + pub const fn spi_mem_dout_mode(&self) -> &SPI_MEM_DOUT_MODE { + &self.spi_mem_dout_mode + } + #[doc = "0x190 - MSPI external RAM timing calibration register"] + #[inline(always)] + pub const fn spi_smem_timing_cali(&self) -> &SPI_SMEM_TIMING_CALI { + &self.spi_smem_timing_cali + } + #[doc = "0x194 - MSPI external RAM input timing delay mode control register"] + #[inline(always)] + pub const fn spi_smem_din_mode(&self) -> &SPI_SMEM_DIN_MODE { + &self.spi_smem_din_mode + } + #[doc = "0x198 - MSPI external RAM input timing delay number control register"] + #[inline(always)] + pub const fn spi_smem_din_num(&self) -> &SPI_SMEM_DIN_NUM { + &self.spi_smem_din_num + } + #[doc = "0x19c - MSPI external RAM output timing adjustment control register"] + #[inline(always)] + pub const fn spi_smem_dout_mode(&self) -> &SPI_SMEM_DOUT_MODE { + &self.spi_smem_dout_mode + } + #[doc = "0x1a0 - MSPI external RAM ECC and SPI CS timing control register"] + #[inline(always)] + pub const fn spi_smem_ac(&self) -> &SPI_SMEM_AC { + &self.spi_smem_ac + } + #[doc = "0x1a4 - MSPI 16x external RAM input timing delay mode control register"] + #[inline(always)] + pub const fn spi_smem_din_hex_mode(&self) -> &SPI_SMEM_DIN_HEX_MODE { + &self.spi_smem_din_hex_mode + } + #[doc = "0x1a8 - MSPI 16x external RAM input timing delay number control register"] + #[inline(always)] + pub const fn spi_smem_din_hex_num(&self) -> &SPI_SMEM_DIN_HEX_NUM { + &self.spi_smem_din_hex_num + } + #[doc = "0x1ac - MSPI 16x external RAM output timing adjustment control register"] + #[inline(always)] + pub const fn spi_smem_dout_hex_mode(&self) -> &SPI_SMEM_DOUT_HEX_MODE { + &self.spi_smem_dout_hex_mode + } + #[doc = "0x200 - SPI0 clock gate register"] + #[inline(always)] + pub const fn spi_mem_clock_gate(&self) -> &SPI_MEM_CLOCK_GATE { + &self.spi_mem_clock_gate + } + #[doc = "0x300 - The base address of the memory that stores plaintext in Manual Encryption"] + #[inline(always)] + pub const fn spi_mem_xts_plain_base(&self) -> &SPI_MEM_XTS_PLAIN_BASE { + &self.spi_mem_xts_plain_base + } + #[doc = "0x340 - Manual Encryption Line-Size register"] + #[inline(always)] + pub const fn spi_mem_xts_linesize(&self) -> &SPI_MEM_XTS_LINESIZE { + &self.spi_mem_xts_linesize + } + #[doc = "0x344 - Manual Encryption destination register"] + #[inline(always)] + pub const fn spi_mem_xts_destination(&self) -> &SPI_MEM_XTS_DESTINATION { + &self.spi_mem_xts_destination + } + #[doc = "0x348 - Manual Encryption physical address register"] + #[inline(always)] + pub const fn spi_mem_xts_physical_address(&self) -> &SPI_MEM_XTS_PHYSICAL_ADDRESS { + &self.spi_mem_xts_physical_address + } + #[doc = "0x34c - Manual Encryption physical address register"] + #[inline(always)] + pub const fn spi_mem_xts_trigger(&self) -> &SPI_MEM_XTS_TRIGGER { + &self.spi_mem_xts_trigger + } + #[doc = "0x350 - Manual Encryption physical address register"] + #[inline(always)] + pub const fn spi_mem_xts_release(&self) -> &SPI_MEM_XTS_RELEASE { + &self.spi_mem_xts_release + } + #[doc = "0x354 - Manual Encryption physical address register"] + #[inline(always)] + pub const fn spi_mem_xts_destroy(&self) -> &SPI_MEM_XTS_DESTROY { + &self.spi_mem_xts_destroy + } + #[doc = "0x358 - Manual Encryption physical address register"] + #[inline(always)] + pub const fn spi_mem_xts_state(&self) -> &SPI_MEM_XTS_STATE { + &self.spi_mem_xts_state + } + #[doc = "0x35c - Manual Encryption version register"] + #[inline(always)] + pub const fn spi_mem_xts_date(&self) -> &SPI_MEM_XTS_DATE { + &self.spi_mem_xts_date + } + #[doc = "0x37c - MSPI-MMU item content register"] + #[inline(always)] + pub const fn spi_mem_mmu_item_content(&self) -> &SPI_MEM_MMU_ITEM_CONTENT { + &self.spi_mem_mmu_item_content + } + #[doc = "0x380 - MSPI-MMU item index register"] + #[inline(always)] + pub const fn spi_mem_mmu_item_index(&self) -> &SPI_MEM_MMU_ITEM_INDEX { + &self.spi_mem_mmu_item_index + } + #[doc = "0x384 - MSPI MMU power control register"] + #[inline(always)] + pub const fn spi_mem_mmu_power_ctrl(&self) -> &SPI_MEM_MMU_POWER_CTRL { + &self.spi_mem_mmu_power_ctrl + } + #[doc = "0x388 - SPI memory cryption DPA register"] + #[inline(always)] + pub const fn spi_mem_dpa_ctrl(&self) -> &SPI_MEM_DPA_CTRL { + &self.spi_mem_dpa_ctrl + } + #[doc = "0x3f0 - MSPI ECO high register"] + #[inline(always)] + pub const fn spi_mem_registerrnd_eco_high(&self) -> &SPI_MEM_REGISTERRND_ECO_HIGH { + &self.spi_mem_registerrnd_eco_high + } + #[doc = "0x3f4 - MSPI ECO low register"] + #[inline(always)] + pub const fn spi_mem_registerrnd_eco_low(&self) -> &SPI_MEM_REGISTERRND_ECO_LOW { + &self.spi_mem_registerrnd_eco_low + } + #[doc = "0x3fc - SPI0 version control register"] + #[inline(always)] + pub const fn spi_mem_date(&self) -> &SPI_MEM_DATE { + &self.spi_mem_date + } +} +#[doc = "SPI_MEM_CMD (r) register accessor: SPI0 FSM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_cmd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_cmd`] module"] +pub type SPI_MEM_CMD = crate::Reg; +#[doc = "SPI0 FSM status register"] +pub mod spi_mem_cmd; +#[doc = "SPI_MEM_CTRL (rw) register accessor: SPI0 control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_ctrl`] module"] +pub type SPI_MEM_CTRL = crate::Reg; +#[doc = "SPI0 control register."] +pub mod spi_mem_ctrl; +#[doc = "SPI_MEM_CTRL1 (rw) register accessor: SPI0 control1 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_ctrl1`] module"] +pub type SPI_MEM_CTRL1 = crate::Reg; +#[doc = "SPI0 control1 register."] +pub mod spi_mem_ctrl1; +#[doc = "SPI_MEM_CTRL2 (rw) register accessor: SPI0 control2 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ctrl2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_ctrl2`] module"] +pub type SPI_MEM_CTRL2 = crate::Reg; +#[doc = "SPI0 control2 register."] +pub mod spi_mem_ctrl2; +#[doc = "SPI_MEM_CLOCK (rw) register accessor: SPI clock division control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_clock::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_clock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_clock`] module"] +pub type SPI_MEM_CLOCK = crate::Reg; +#[doc = "SPI clock division control register."] +pub mod spi_mem_clock; +#[doc = "SPI_MEM_USER (rw) register accessor: SPI0 user register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_user`] module"] +pub type SPI_MEM_USER = crate::Reg; +#[doc = "SPI0 user register."] +pub mod spi_mem_user; +#[doc = "SPI_MEM_USER1 (rw) register accessor: SPI0 user1 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_user1`] module"] +pub type SPI_MEM_USER1 = crate::Reg; +#[doc = "SPI0 user1 register."] +pub mod spi_mem_user1; +#[doc = "SPI_MEM_USER2 (rw) register accessor: SPI0 user2 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_user2`] module"] +pub type SPI_MEM_USER2 = crate::Reg; +#[doc = "SPI0 user2 register."] +pub mod spi_mem_user2; +#[doc = "SPI_MEM_RD_STATUS (rw) register accessor: SPI0 read control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_rd_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_rd_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_rd_status`] module"] +pub type SPI_MEM_RD_STATUS = crate::Reg; +#[doc = "SPI0 read control register."] +pub mod spi_mem_rd_status; +#[doc = "SPI_MEM_MISC (rw) register accessor: SPI0 misc register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_misc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_misc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_misc`] module"] +pub type SPI_MEM_MISC = crate::Reg; +#[doc = "SPI0 misc register"] +pub mod spi_mem_misc; +#[doc = "SPI_MEM_CACHE_FCTRL (rw) register accessor: SPI0 bit mode control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_cache_fctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_cache_fctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_cache_fctrl`] module"] +pub type SPI_MEM_CACHE_FCTRL = crate::Reg; +#[doc = "SPI0 bit mode control register."] +pub mod spi_mem_cache_fctrl; +#[doc = "SPI_MEM_CACHE_SCTRL (rw) register accessor: SPI0 external RAM control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_cache_sctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_cache_sctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_cache_sctrl`] module"] +pub type SPI_MEM_CACHE_SCTRL = crate::Reg; +#[doc = "SPI0 external RAM control register"] +pub mod spi_mem_cache_sctrl; +#[doc = "SPI_MEM_SRAM_CMD (rw) register accessor: SPI0 external RAM mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_sram_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_sram_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_sram_cmd`] module"] +pub type SPI_MEM_SRAM_CMD = crate::Reg; +#[doc = "SPI0 external RAM mode control register"] +pub mod spi_mem_sram_cmd; +#[doc = "SPI_MEM_SRAM_DRD_CMD (rw) register accessor: SPI0 external RAM DDR read command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_sram_drd_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_sram_drd_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_sram_drd_cmd`] module"] +pub type SPI_MEM_SRAM_DRD_CMD = crate::Reg; +#[doc = "SPI0 external RAM DDR read command control register"] +pub mod spi_mem_sram_drd_cmd; +#[doc = "SPI_MEM_SRAM_DWR_CMD (rw) register accessor: SPI0 external RAM DDR write command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_sram_dwr_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_sram_dwr_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_sram_dwr_cmd`] module"] +pub type SPI_MEM_SRAM_DWR_CMD = crate::Reg; +#[doc = "SPI0 external RAM DDR write command control register"] +pub mod spi_mem_sram_dwr_cmd; +#[doc = "SPI_MEM_SRAM_CLK (rw) register accessor: SPI0 external RAM clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_sram_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_sram_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_sram_clk`] module"] +pub type SPI_MEM_SRAM_CLK = crate::Reg; +#[doc = "SPI0 external RAM clock control register"] +pub mod spi_mem_sram_clk; +#[doc = "SPI_MEM_FSM (rw) register accessor: SPI0 FSM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_fsm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_fsm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_fsm`] module"] +pub type SPI_MEM_FSM = crate::Reg; +#[doc = "SPI0 FSM status register"] +pub mod spi_mem_fsm; +#[doc = "SPI_MEM_INT_ENA (rw) register accessor: SPI0 interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_int_ena`] module"] +pub type SPI_MEM_INT_ENA = crate::Reg; +#[doc = "SPI0 interrupt enable register"] +pub mod spi_mem_int_ena; +#[doc = "SPI_MEM_INT_CLR (w) register accessor: SPI0 interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_int_clr`] module"] +pub type SPI_MEM_INT_CLR = crate::Reg; +#[doc = "SPI0 interrupt clear register"] +pub mod spi_mem_int_clr; +#[doc = "SPI_MEM_INT_RAW (rw) register accessor: SPI0 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_int_raw`] module"] +pub type SPI_MEM_INT_RAW = crate::Reg; +#[doc = "SPI0 interrupt raw register"] +pub mod spi_mem_int_raw; +#[doc = "SPI_MEM_INT_ST (r) register accessor: SPI0 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_int_st`] module"] +pub type SPI_MEM_INT_ST = crate::Reg; +#[doc = "SPI0 interrupt status register"] +pub mod spi_mem_int_st; +#[doc = "SPI_MEM_DDR (rw) register accessor: SPI0 flash DDR mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_ddr`] module"] +pub type SPI_MEM_DDR = crate::Reg; +#[doc = "SPI0 flash DDR mode control register"] +pub mod spi_mem_ddr; +#[doc = "SPI_SMEM_DDR (rw) register accessor: SPI0 external RAM DDR mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_ddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_ddr`] module"] +pub type SPI_SMEM_DDR = crate::Reg; +#[doc = "SPI0 external RAM DDR mode control register"] +pub mod spi_smem_ddr; +#[doc = "SPI_FMEM_PMS_ATTR (rw) register accessor: MSPI flash PMS section %s attribute register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_fmem_pms_attr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_fmem_pms_attr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_fmem_pms_attr`] module"] +pub type SPI_FMEM_PMS_ATTR = crate::Reg; +#[doc = "MSPI flash PMS section %s attribute register"] +pub mod spi_fmem_pms_attr; +#[doc = "SPI_FMEM_PMS_ADDR (rw) register accessor: SPI1 flash PMS section %s start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_fmem_pms_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_fmem_pms_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_fmem_pms_addr`] module"] +pub type SPI_FMEM_PMS_ADDR = crate::Reg; +#[doc = "SPI1 flash PMS section %s start address register"] +pub mod spi_fmem_pms_addr; +#[doc = "SPI_FMEM_PMS_SIZE (rw) register accessor: SPI1 flash PMS section %s start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_fmem_pms_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_fmem_pms_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_fmem_pms_size`] module"] +pub type SPI_FMEM_PMS_SIZE = crate::Reg; +#[doc = "SPI1 flash PMS section %s start address register"] +pub mod spi_fmem_pms_size; +#[doc = "SPI_SMEM_PMS_ATTR (rw) register accessor: SPI1 flash PMS section %s start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_pms_attr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_pms_attr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_pms_attr`] module"] +pub type SPI_SMEM_PMS_ATTR = crate::Reg; +#[doc = "SPI1 flash PMS section %s start address register"] +pub mod spi_smem_pms_attr; +#[doc = "SPI_SMEM_PMS_ADDR (rw) register accessor: SPI1 external RAM PMS section %s start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_pms_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_pms_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_pms_addr`] module"] +pub type SPI_SMEM_PMS_ADDR = crate::Reg; +#[doc = "SPI1 external RAM PMS section %s start address register"] +pub mod spi_smem_pms_addr; +#[doc = "SPI_SMEM_PMS_SIZE (rw) register accessor: SPI1 external RAM PMS section %s start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_pms_size::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_pms_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_pms_size`] module"] +pub type SPI_SMEM_PMS_SIZE = crate::Reg; +#[doc = "SPI1 external RAM PMS section %s start address register"] +pub mod spi_smem_pms_size; +#[doc = "SPI_MEM_PMS_REJECT (rw) register accessor: SPI1 access reject register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_pms_reject::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_pms_reject::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_pms_reject`] module"] +pub type SPI_MEM_PMS_REJECT = crate::Reg; +#[doc = "SPI1 access reject register"] +pub mod spi_mem_pms_reject; +#[doc = "SPI_MEM_ECC_CTRL (rw) register accessor: MSPI ECC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ecc_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ecc_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_ecc_ctrl`] module"] +pub type SPI_MEM_ECC_CTRL = crate::Reg; +#[doc = "MSPI ECC control register"] +pub mod spi_mem_ecc_ctrl; +#[doc = "SPI_MEM_ECC_ERR_ADDR (r) register accessor: MSPI ECC error address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ecc_err_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_ecc_err_addr`] module"] +pub type SPI_MEM_ECC_ERR_ADDR = crate::Reg; +#[doc = "MSPI ECC error address register"] +pub mod spi_mem_ecc_err_addr; +#[doc = "SPI_MEM_AXI_ERR_ADDR (r) register accessor: SPI0 AXI request error address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_axi_err_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_axi_err_addr`] module"] +pub type SPI_MEM_AXI_ERR_ADDR = crate::Reg; +#[doc = "SPI0 AXI request error address."] +pub mod spi_mem_axi_err_addr; +#[doc = "SPI_SMEM_ECC_CTRL (rw) register accessor: MSPI ECC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ecc_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_ecc_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_ecc_ctrl`] module"] +pub type SPI_SMEM_ECC_CTRL = crate::Reg; +#[doc = "MSPI ECC control register"] +pub mod spi_smem_ecc_ctrl; +#[doc = "SPI_SMEM_AXI_ADDR_CTRL (r) register accessor: SPI0 AXI address control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_axi_addr_ctrl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_axi_addr_ctrl`] module"] +pub type SPI_SMEM_AXI_ADDR_CTRL = crate::Reg; +#[doc = "SPI0 AXI address control register"] +pub mod spi_smem_axi_addr_ctrl; +#[doc = "SPI_MEM_AXI_ERR_RESP_EN (rw) register accessor: SPI0 AXI error response enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_axi_err_resp_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_axi_err_resp_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_axi_err_resp_en`] module"] +pub type SPI_MEM_AXI_ERR_RESP_EN = + crate::Reg; +#[doc = "SPI0 AXI error response enable register"] +pub mod spi_mem_axi_err_resp_en; +#[doc = "SPI_MEM_TIMING_CALI (rw) register accessor: SPI0 flash timing calibration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_timing_cali::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_timing_cali::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_timing_cali`] module"] +pub type SPI_MEM_TIMING_CALI = crate::Reg; +#[doc = "SPI0 flash timing calibration register"] +pub mod spi_mem_timing_cali; +#[doc = "SPI_MEM_DIN_MODE (rw) register accessor: MSPI flash input timing delay mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_din_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_din_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_din_mode`] module"] +pub type SPI_MEM_DIN_MODE = crate::Reg; +#[doc = "MSPI flash input timing delay mode control register"] +pub mod spi_mem_din_mode; +#[doc = "SPI_MEM_DIN_NUM (rw) register accessor: MSPI flash input timing delay number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_din_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_din_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_din_num`] module"] +pub type SPI_MEM_DIN_NUM = crate::Reg; +#[doc = "MSPI flash input timing delay number control register"] +pub mod spi_mem_din_num; +#[doc = "SPI_MEM_DOUT_MODE (rw) register accessor: MSPI flash output timing adjustment control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_dout_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_dout_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_dout_mode`] module"] +pub type SPI_MEM_DOUT_MODE = crate::Reg; +#[doc = "MSPI flash output timing adjustment control register"] +pub mod spi_mem_dout_mode; +#[doc = "SPI_SMEM_TIMING_CALI (rw) register accessor: MSPI external RAM timing calibration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_timing_cali::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_timing_cali::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_timing_cali`] module"] +pub type SPI_SMEM_TIMING_CALI = crate::Reg; +#[doc = "MSPI external RAM timing calibration register"] +pub mod spi_smem_timing_cali; +#[doc = "SPI_SMEM_DIN_MODE (rw) register accessor: MSPI external RAM input timing delay mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_din_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_din_mode`] module"] +pub type SPI_SMEM_DIN_MODE = crate::Reg; +#[doc = "MSPI external RAM input timing delay mode control register"] +pub mod spi_smem_din_mode; +#[doc = "SPI_SMEM_DIN_NUM (rw) register accessor: MSPI external RAM input timing delay number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_din_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_din_num`] module"] +pub type SPI_SMEM_DIN_NUM = crate::Reg; +#[doc = "MSPI external RAM input timing delay number control register"] +pub mod spi_smem_din_num; +#[doc = "SPI_SMEM_DOUT_MODE (rw) register accessor: MSPI external RAM output timing adjustment control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_dout_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_dout_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_dout_mode`] module"] +pub type SPI_SMEM_DOUT_MODE = crate::Reg; +#[doc = "MSPI external RAM output timing adjustment control register"] +pub mod spi_smem_dout_mode; +#[doc = "SPI_SMEM_AC (rw) register accessor: MSPI external RAM ECC and SPI CS timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ac::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_ac::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_ac`] module"] +pub type SPI_SMEM_AC = crate::Reg; +#[doc = "MSPI external RAM ECC and SPI CS timing control register"] +pub mod spi_smem_ac; +#[doc = "SPI_SMEM_DIN_HEX_MODE (rw) register accessor: MSPI 16x external RAM input timing delay mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_hex_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_din_hex_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_din_hex_mode`] module"] +pub type SPI_SMEM_DIN_HEX_MODE = crate::Reg; +#[doc = "MSPI 16x external RAM input timing delay mode control register"] +pub mod spi_smem_din_hex_mode; +#[doc = "SPI_SMEM_DIN_HEX_NUM (rw) register accessor: MSPI 16x external RAM input timing delay number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_hex_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_din_hex_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_din_hex_num`] module"] +pub type SPI_SMEM_DIN_HEX_NUM = crate::Reg; +#[doc = "MSPI 16x external RAM input timing delay number control register"] +pub mod spi_smem_din_hex_num; +#[doc = "SPI_SMEM_DOUT_HEX_MODE (rw) register accessor: MSPI 16x external RAM output timing adjustment control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_dout_hex_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_dout_hex_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_smem_dout_hex_mode`] module"] +pub type SPI_SMEM_DOUT_HEX_MODE = crate::Reg; +#[doc = "MSPI 16x external RAM output timing adjustment control register"] +pub mod spi_smem_dout_hex_mode; +#[doc = "SPI_MEM_CLOCK_GATE (rw) register accessor: SPI0 clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_clock_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_clock_gate`] module"] +pub type SPI_MEM_CLOCK_GATE = crate::Reg; +#[doc = "SPI0 clock gate register"] +pub mod spi_mem_clock_gate; +#[doc = "SPI_MEM_XTS_PLAIN_BASE (rw) register accessor: The base address of the memory that stores plaintext in Manual Encryption\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_plain_base::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_plain_base::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_xts_plain_base`] module"] +pub type SPI_MEM_XTS_PLAIN_BASE = crate::Reg; +#[doc = "The base address of the memory that stores plaintext in Manual Encryption"] +pub mod spi_mem_xts_plain_base; +#[doc = "SPI_MEM_XTS_LINESIZE (rw) register accessor: Manual Encryption Line-Size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_linesize::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_linesize::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_xts_linesize`] module"] +pub type SPI_MEM_XTS_LINESIZE = crate::Reg; +#[doc = "Manual Encryption Line-Size register"] +pub mod spi_mem_xts_linesize; +#[doc = "SPI_MEM_XTS_DESTINATION (rw) register accessor: Manual Encryption destination register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_destination::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_destination::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_xts_destination`] module"] +pub type SPI_MEM_XTS_DESTINATION = + crate::Reg; +#[doc = "Manual Encryption destination register"] +pub mod spi_mem_xts_destination; +#[doc = "SPI_MEM_XTS_PHYSICAL_ADDRESS (rw) register accessor: Manual Encryption physical address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_physical_address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_physical_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_xts_physical_address`] module"] +pub type SPI_MEM_XTS_PHYSICAL_ADDRESS = + crate::Reg; +#[doc = "Manual Encryption physical address register"] +pub mod spi_mem_xts_physical_address; +#[doc = "SPI_MEM_XTS_TRIGGER (w) register accessor: Manual Encryption physical address register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_trigger::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_xts_trigger`] module"] +pub type SPI_MEM_XTS_TRIGGER = crate::Reg; +#[doc = "Manual Encryption physical address register"] +pub mod spi_mem_xts_trigger; +#[doc = "SPI_MEM_XTS_RELEASE (w) register accessor: Manual Encryption physical address register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_release::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_xts_release`] module"] +pub type SPI_MEM_XTS_RELEASE = crate::Reg; +#[doc = "Manual Encryption physical address register"] +pub mod spi_mem_xts_release; +#[doc = "SPI_MEM_XTS_DESTROY (w) register accessor: Manual Encryption physical address register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_destroy::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_xts_destroy`] module"] +pub type SPI_MEM_XTS_DESTROY = crate::Reg; +#[doc = "Manual Encryption physical address register"] +pub mod spi_mem_xts_destroy; +#[doc = "SPI_MEM_XTS_STATE (r) register accessor: Manual Encryption physical address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_xts_state`] module"] +pub type SPI_MEM_XTS_STATE = crate::Reg; +#[doc = "Manual Encryption physical address register"] +pub mod spi_mem_xts_state; +#[doc = "SPI_MEM_XTS_DATE (rw) register accessor: Manual Encryption version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_xts_date`] module"] +pub type SPI_MEM_XTS_DATE = crate::Reg; +#[doc = "Manual Encryption version register"] +pub mod spi_mem_xts_date; +#[doc = "SPI_MEM_MMU_ITEM_CONTENT (rw) register accessor: MSPI-MMU item content register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_mmu_item_content::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_mmu_item_content::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_mmu_item_content`] module"] +pub type SPI_MEM_MMU_ITEM_CONTENT = + crate::Reg; +#[doc = "MSPI-MMU item content register"] +pub mod spi_mem_mmu_item_content; +#[doc = "SPI_MEM_MMU_ITEM_INDEX (rw) register accessor: MSPI-MMU item index register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_mmu_item_index::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_mmu_item_index::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_mmu_item_index`] module"] +pub type SPI_MEM_MMU_ITEM_INDEX = crate::Reg; +#[doc = "MSPI-MMU item index register"] +pub mod spi_mem_mmu_item_index; +#[doc = "SPI_MEM_MMU_POWER_CTRL (rw) register accessor: MSPI MMU power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_mmu_power_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_mmu_power_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_mmu_power_ctrl`] module"] +pub type SPI_MEM_MMU_POWER_CTRL = crate::Reg; +#[doc = "MSPI MMU power control register"] +pub mod spi_mem_mmu_power_ctrl; +#[doc = "SPI_MEM_DPA_CTRL (rw) register accessor: SPI memory cryption DPA register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_dpa_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_dpa_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_dpa_ctrl`] module"] +pub type SPI_MEM_DPA_CTRL = crate::Reg; +#[doc = "SPI memory cryption DPA register"] +pub mod spi_mem_dpa_ctrl; +#[doc = "SPI_MEM_REGISTERRND_ECO_HIGH (rw) register accessor: MSPI ECO high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_registerrnd_eco_high::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_registerrnd_eco_high::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_registerrnd_eco_high`] module"] +pub type SPI_MEM_REGISTERRND_ECO_HIGH = + crate::Reg; +#[doc = "MSPI ECO high register"] +pub mod spi_mem_registerrnd_eco_high; +#[doc = "SPI_MEM_REGISTERRND_ECO_LOW (rw) register accessor: MSPI ECO low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_registerrnd_eco_low::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_registerrnd_eco_low::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_registerrnd_eco_low`] module"] +pub type SPI_MEM_REGISTERRND_ECO_LOW = + crate::Reg; +#[doc = "MSPI ECO low register"] +pub mod spi_mem_registerrnd_eco_low; +#[doc = "SPI_MEM_DATE (rw) register accessor: SPI0 version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_date`] module"] +pub type SPI_MEM_DATE = crate::Reg; +#[doc = "SPI0 version control register"] +pub mod spi_mem_date; diff --git a/esp32p4/src/spi0/spi_fmem_pms_addr.rs b/esp32p4/src/spi0/spi_fmem_pms_addr.rs new file mode 100644 index 0000000000..0bb9e821ab --- /dev/null +++ b/esp32p4/src/spi0/spi_fmem_pms_addr.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_FMEM_PMS%s_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_FMEM_PMS%s_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `S` reader - SPI1 flash PMS section %s start address value"] +pub type S_R = crate::FieldReader; +#[doc = "Field `S` writer - SPI1 flash PMS section %s start address value"] +pub type S_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 0:26 - SPI1 flash PMS section %s start address value"] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(self.bits & 0x07ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_FMEM_PMS_ADDR") + .field("s", &format_args!("{}", self.s().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:26 - SPI1 flash PMS section %s start address value"] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 flash PMS section %s start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_fmem_pms_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_fmem_pms_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_FMEM_PMS_ADDR_SPEC; +impl crate::RegisterSpec for SPI_FMEM_PMS_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_fmem_pms_addr::R`](R) reader structure"] +impl crate::Readable for SPI_FMEM_PMS_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_fmem_pms_addr::W`](W) writer structure"] +impl crate::Writable for SPI_FMEM_PMS_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_FMEM_PMS%s_ADDR to value 0"] +impl crate::Resettable for SPI_FMEM_PMS_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_fmem_pms_attr.rs b/esp32p4/src/spi0/spi_fmem_pms_attr.rs new file mode 100644 index 0000000000..226477a2a2 --- /dev/null +++ b/esp32p4/src/spi0/spi_fmem_pms_attr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SPI_FMEM_PMS%s_ATTR` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_FMEM_PMS%s_ATTR` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_FMEM_PMS_RD_ATTR` reader - 1: SPI1 flash PMS section %s read accessible. 0: Not allowed."] +pub type SPI_FMEM_PMS_RD_ATTR_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_PMS_RD_ATTR` writer - 1: SPI1 flash PMS section %s read accessible. 0: Not allowed."] +pub type SPI_FMEM_PMS_RD_ATTR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_PMS_WR_ATTR` reader - 1: SPI1 flash PMS section %s write accessible. 0: Not allowed."] +pub type SPI_FMEM_PMS_WR_ATTR_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_PMS_WR_ATTR` writer - 1: SPI1 flash PMS section %s write accessible. 0: Not allowed."] +pub type SPI_FMEM_PMS_WR_ATTR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_PMS_ECC` reader - SPI1 flash PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG."] +pub type SPI_FMEM_PMS_ECC_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_PMS_ECC` writer - SPI1 flash PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG."] +pub type SPI_FMEM_PMS_ECC_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: SPI1 flash PMS section %s read accessible. 0: Not allowed."] + #[inline(always)] + pub fn spi_fmem_pms_rd_attr(&self) -> SPI_FMEM_PMS_RD_ATTR_R { + SPI_FMEM_PMS_RD_ATTR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: SPI1 flash PMS section %s write accessible. 0: Not allowed."] + #[inline(always)] + pub fn spi_fmem_pms_wr_attr(&self) -> SPI_FMEM_PMS_WR_ATTR_R { + SPI_FMEM_PMS_WR_ATTR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI1 flash PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG."] + #[inline(always)] + pub fn spi_fmem_pms_ecc(&self) -> SPI_FMEM_PMS_ECC_R { + SPI_FMEM_PMS_ECC_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_FMEM_PMS_ATTR") + .field( + "spi_fmem_pms_rd_attr", + &format_args!("{}", self.spi_fmem_pms_rd_attr().bit()), + ) + .field( + "spi_fmem_pms_wr_attr", + &format_args!("{}", self.spi_fmem_pms_wr_attr().bit()), + ) + .field( + "spi_fmem_pms_ecc", + &format_args!("{}", self.spi_fmem_pms_ecc().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: SPI1 flash PMS section %s read accessible. 0: Not allowed."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_pms_rd_attr(&mut self) -> SPI_FMEM_PMS_RD_ATTR_W { + SPI_FMEM_PMS_RD_ATTR_W::new(self, 0) + } + #[doc = "Bit 1 - 1: SPI1 flash PMS section %s write accessible. 0: Not allowed."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_pms_wr_attr(&mut self) -> SPI_FMEM_PMS_WR_ATTR_W { + SPI_FMEM_PMS_WR_ATTR_W::new(self, 1) + } + #[doc = "Bit 2 - SPI1 flash PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_pms_ecc(&mut self) -> SPI_FMEM_PMS_ECC_W { + SPI_FMEM_PMS_ECC_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI flash PMS section %s attribute register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_fmem_pms_attr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_fmem_pms_attr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_FMEM_PMS_ATTR_SPEC; +impl crate::RegisterSpec for SPI_FMEM_PMS_ATTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_fmem_pms_attr::R`](R) reader structure"] +impl crate::Readable for SPI_FMEM_PMS_ATTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_fmem_pms_attr::W`](W) writer structure"] +impl crate::Writable for SPI_FMEM_PMS_ATTR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_FMEM_PMS%s_ATTR to value 0x03"] +impl crate::Resettable for SPI_FMEM_PMS_ATTR_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/spi0/spi_fmem_pms_size.rs b/esp32p4/src/spi0/spi_fmem_pms_size.rs new file mode 100644 index 0000000000..52c677a2f7 --- /dev/null +++ b/esp32p4/src/spi0/spi_fmem_pms_size.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_FMEM_PMS%s_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_FMEM_PMS%s_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_FMEM_PMS_SIZE` reader - SPI1 flash PMS section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)"] +pub type SPI_FMEM_PMS_SIZE_R = crate::FieldReader; +#[doc = "Field `SPI_FMEM_PMS_SIZE` writer - SPI1 flash PMS section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)"] +pub type SPI_FMEM_PMS_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bits 0:14 - SPI1 flash PMS section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)"] + #[inline(always)] + pub fn spi_fmem_pms_size(&self) -> SPI_FMEM_PMS_SIZE_R { + SPI_FMEM_PMS_SIZE_R::new((self.bits & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_FMEM_PMS_SIZE") + .field( + "spi_fmem_pms_size", + &format_args!("{}", self.spi_fmem_pms_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:14 - SPI1 flash PMS section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)"] + #[inline(always)] + #[must_use] + pub fn spi_fmem_pms_size(&mut self) -> SPI_FMEM_PMS_SIZE_W { + SPI_FMEM_PMS_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 flash PMS section %s start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_fmem_pms_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_fmem_pms_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_FMEM_PMS_SIZE_SPEC; +impl crate::RegisterSpec for SPI_FMEM_PMS_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_fmem_pms_size::R`](R) reader structure"] +impl crate::Readable for SPI_FMEM_PMS_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_fmem_pms_size::W`](W) writer structure"] +impl crate::Writable for SPI_FMEM_PMS_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_FMEM_PMS%s_SIZE to value 0x1000"] +impl crate::Resettable for SPI_FMEM_PMS_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0x1000; +} diff --git a/esp32p4/src/spi0/spi_mem_axi_err_addr.rs b/esp32p4/src/spi0/spi_mem_axi_err_addr.rs new file mode 100644 index 0000000000..38771ba860 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_axi_err_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SPI_MEM_AXI_ERR_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `SPI_MEM_AXI_ERR_ADDR` reader - This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set."] +pub type SPI_MEM_AXI_ERR_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:26 - This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set."] + #[inline(always)] + pub fn spi_mem_axi_err_addr(&self) -> SPI_MEM_AXI_ERR_ADDR_R { + SPI_MEM_AXI_ERR_ADDR_R::new(self.bits & 0x07ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_AXI_ERR_ADDR") + .field( + "spi_mem_axi_err_addr", + &format_args!("{}", self.spi_mem_axi_err_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "SPI0 AXI request error address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_axi_err_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_AXI_ERR_ADDR_SPEC; +impl crate::RegisterSpec for SPI_MEM_AXI_ERR_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_axi_err_addr::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_AXI_ERR_ADDR_SPEC {} +#[doc = "`reset()` method sets SPI_MEM_AXI_ERR_ADDR to value 0"] +impl crate::Resettable for SPI_MEM_AXI_ERR_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_axi_err_resp_en.rs b/esp32p4/src/spi0/spi_mem_axi_err_resp_en.rs new file mode 100644 index 0000000000..601662bd8b --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_axi_err_resp_en.rs @@ -0,0 +1,299 @@ +#[doc = "Register `SPI_MEM_AXI_ERR_RESP_EN` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_AXI_ERR_RESP_EN` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_AW_RESP_EN_MMU_VLD` reader - Set this bit to enable AXI response function for mmu valid err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_MMU_VLD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AW_RESP_EN_MMU_VLD` writer - Set this bit to enable AXI response function for mmu valid err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_MMU_VLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AW_RESP_EN_MMU_GID` reader - Set this bit to enable AXI response function for mmu gid err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_MMU_GID_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AW_RESP_EN_MMU_GID` writer - Set this bit to enable AXI response function for mmu gid err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_MMU_GID_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AW_RESP_EN_AXI_SIZE` reader - Set this bit to enable AXI response function for axi size err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_AXI_SIZE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AW_RESP_EN_AXI_SIZE` writer - Set this bit to enable AXI response function for axi size err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_AXI_SIZE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AW_RESP_EN_AXI_FLASH` reader - Set this bit to enable AXI response function for axi flash err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_AXI_FLASH_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AW_RESP_EN_AXI_FLASH` writer - Set this bit to enable AXI response function for axi flash err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_AXI_FLASH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AW_RESP_EN_MMU_ECC` reader - Set this bit to enable AXI response function for mmu ecc err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_MMU_ECC_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AW_RESP_EN_MMU_ECC` writer - Set this bit to enable AXI response function for mmu ecc err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_MMU_ECC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AW_RESP_EN_MMU_SENS` reader - Set this bit to enable AXI response function for mmu sens in err axi write trans."] +pub type SPI_MEM_AW_RESP_EN_MMU_SENS_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AW_RESP_EN_MMU_SENS` writer - Set this bit to enable AXI response function for mmu sens in err axi write trans."] +pub type SPI_MEM_AW_RESP_EN_MMU_SENS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AW_RESP_EN_AXI_WSTRB` reader - Set this bit to enable AXI response function for axi wstrb err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_AXI_WSTRB_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AW_RESP_EN_AXI_WSTRB` writer - Set this bit to enable AXI response function for axi wstrb err in axi write trans."] +pub type SPI_MEM_AW_RESP_EN_AXI_WSTRB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AR_RESP_EN_MMU_VLD` reader - Set this bit to enable AXI response function for mmu valid err in axi read trans."] +pub type SPI_MEM_AR_RESP_EN_MMU_VLD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AR_RESP_EN_MMU_VLD` writer - Set this bit to enable AXI response function for mmu valid err in axi read trans."] +pub type SPI_MEM_AR_RESP_EN_MMU_VLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AR_RESP_EN_MMU_GID` reader - Set this bit to enable AXI response function for mmu gid err in axi read trans."] +pub type SPI_MEM_AR_RESP_EN_MMU_GID_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AR_RESP_EN_MMU_GID` writer - Set this bit to enable AXI response function for mmu gid err in axi read trans."] +pub type SPI_MEM_AR_RESP_EN_MMU_GID_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AR_RESP_EN_MMU_ECC` reader - Set this bit to enable AXI response function for mmu ecc err in axi read trans."] +pub type SPI_MEM_AR_RESP_EN_MMU_ECC_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AR_RESP_EN_MMU_ECC` writer - Set this bit to enable AXI response function for mmu ecc err in axi read trans."] +pub type SPI_MEM_AR_RESP_EN_MMU_ECC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AR_RESP_EN_MMU_SENS` reader - Set this bit to enable AXI response function for mmu sensitive err in axi read trans."] +pub type SPI_MEM_AR_RESP_EN_MMU_SENS_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AR_RESP_EN_MMU_SENS` writer - Set this bit to enable AXI response function for mmu sensitive err in axi read trans."] +pub type SPI_MEM_AR_RESP_EN_MMU_SENS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AR_RESP_EN_AXI_SIZE` reader - Set this bit to enable AXI response function for axi size err in axi read trans."] +pub type SPI_MEM_AR_RESP_EN_AXI_SIZE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AR_RESP_EN_AXI_SIZE` writer - Set this bit to enable AXI response function for axi size err in axi read trans."] +pub type SPI_MEM_AR_RESP_EN_AXI_SIZE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable AXI response function for mmu valid err in axi write trans."] + #[inline(always)] + pub fn spi_mem_aw_resp_en_mmu_vld(&self) -> SPI_MEM_AW_RESP_EN_MMU_VLD_R { + SPI_MEM_AW_RESP_EN_MMU_VLD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to enable AXI response function for mmu gid err in axi write trans."] + #[inline(always)] + pub fn spi_mem_aw_resp_en_mmu_gid(&self) -> SPI_MEM_AW_RESP_EN_MMU_GID_R { + SPI_MEM_AW_RESP_EN_MMU_GID_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to enable AXI response function for axi size err in axi write trans."] + #[inline(always)] + pub fn spi_mem_aw_resp_en_axi_size(&self) -> SPI_MEM_AW_RESP_EN_AXI_SIZE_R { + SPI_MEM_AW_RESP_EN_AXI_SIZE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to enable AXI response function for axi flash err in axi write trans."] + #[inline(always)] + pub fn spi_mem_aw_resp_en_axi_flash(&self) -> SPI_MEM_AW_RESP_EN_AXI_FLASH_R { + SPI_MEM_AW_RESP_EN_AXI_FLASH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable AXI response function for mmu ecc err in axi write trans."] + #[inline(always)] + pub fn spi_mem_aw_resp_en_mmu_ecc(&self) -> SPI_MEM_AW_RESP_EN_MMU_ECC_R { + SPI_MEM_AW_RESP_EN_MMU_ECC_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set this bit to enable AXI response function for mmu sens in err axi write trans."] + #[inline(always)] + pub fn spi_mem_aw_resp_en_mmu_sens(&self) -> SPI_MEM_AW_RESP_EN_MMU_SENS_R { + SPI_MEM_AW_RESP_EN_MMU_SENS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set this bit to enable AXI response function for axi wstrb err in axi write trans."] + #[inline(always)] + pub fn spi_mem_aw_resp_en_axi_wstrb(&self) -> SPI_MEM_AW_RESP_EN_AXI_WSTRB_R { + SPI_MEM_AW_RESP_EN_AXI_WSTRB_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set this bit to enable AXI response function for mmu valid err in axi read trans."] + #[inline(always)] + pub fn spi_mem_ar_resp_en_mmu_vld(&self) -> SPI_MEM_AR_RESP_EN_MMU_VLD_R { + SPI_MEM_AR_RESP_EN_MMU_VLD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Set this bit to enable AXI response function for mmu gid err in axi read trans."] + #[inline(always)] + pub fn spi_mem_ar_resp_en_mmu_gid(&self) -> SPI_MEM_AR_RESP_EN_MMU_GID_R { + SPI_MEM_AR_RESP_EN_MMU_GID_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Set this bit to enable AXI response function for mmu ecc err in axi read trans."] + #[inline(always)] + pub fn spi_mem_ar_resp_en_mmu_ecc(&self) -> SPI_MEM_AR_RESP_EN_MMU_ECC_R { + SPI_MEM_AR_RESP_EN_MMU_ECC_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Set this bit to enable AXI response function for mmu sensitive err in axi read trans."] + #[inline(always)] + pub fn spi_mem_ar_resp_en_mmu_sens(&self) -> SPI_MEM_AR_RESP_EN_MMU_SENS_R { + SPI_MEM_AR_RESP_EN_MMU_SENS_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Set this bit to enable AXI response function for axi size err in axi read trans."] + #[inline(always)] + pub fn spi_mem_ar_resp_en_axi_size(&self) -> SPI_MEM_AR_RESP_EN_AXI_SIZE_R { + SPI_MEM_AR_RESP_EN_AXI_SIZE_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_AXI_ERR_RESP_EN") + .field( + "spi_mem_aw_resp_en_mmu_vld", + &format_args!("{}", self.spi_mem_aw_resp_en_mmu_vld().bit()), + ) + .field( + "spi_mem_aw_resp_en_mmu_gid", + &format_args!("{}", self.spi_mem_aw_resp_en_mmu_gid().bit()), + ) + .field( + "spi_mem_aw_resp_en_axi_size", + &format_args!("{}", self.spi_mem_aw_resp_en_axi_size().bit()), + ) + .field( + "spi_mem_aw_resp_en_axi_flash", + &format_args!("{}", self.spi_mem_aw_resp_en_axi_flash().bit()), + ) + .field( + "spi_mem_aw_resp_en_mmu_ecc", + &format_args!("{}", self.spi_mem_aw_resp_en_mmu_ecc().bit()), + ) + .field( + "spi_mem_aw_resp_en_mmu_sens", + &format_args!("{}", self.spi_mem_aw_resp_en_mmu_sens().bit()), + ) + .field( + "spi_mem_aw_resp_en_axi_wstrb", + &format_args!("{}", self.spi_mem_aw_resp_en_axi_wstrb().bit()), + ) + .field( + "spi_mem_ar_resp_en_mmu_vld", + &format_args!("{}", self.spi_mem_ar_resp_en_mmu_vld().bit()), + ) + .field( + "spi_mem_ar_resp_en_mmu_gid", + &format_args!("{}", self.spi_mem_ar_resp_en_mmu_gid().bit()), + ) + .field( + "spi_mem_ar_resp_en_mmu_ecc", + &format_args!("{}", self.spi_mem_ar_resp_en_mmu_ecc().bit()), + ) + .field( + "spi_mem_ar_resp_en_mmu_sens", + &format_args!("{}", self.spi_mem_ar_resp_en_mmu_sens().bit()), + ) + .field( + "spi_mem_ar_resp_en_axi_size", + &format_args!("{}", self.spi_mem_ar_resp_en_axi_size().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable AXI response function for mmu valid err in axi write trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_aw_resp_en_mmu_vld( + &mut self, + ) -> SPI_MEM_AW_RESP_EN_MMU_VLD_W { + SPI_MEM_AW_RESP_EN_MMU_VLD_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to enable AXI response function for mmu gid err in axi write trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_aw_resp_en_mmu_gid( + &mut self, + ) -> SPI_MEM_AW_RESP_EN_MMU_GID_W { + SPI_MEM_AW_RESP_EN_MMU_GID_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to enable AXI response function for axi size err in axi write trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_aw_resp_en_axi_size( + &mut self, + ) -> SPI_MEM_AW_RESP_EN_AXI_SIZE_W { + SPI_MEM_AW_RESP_EN_AXI_SIZE_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to enable AXI response function for axi flash err in axi write trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_aw_resp_en_axi_flash( + &mut self, + ) -> SPI_MEM_AW_RESP_EN_AXI_FLASH_W { + SPI_MEM_AW_RESP_EN_AXI_FLASH_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable AXI response function for mmu ecc err in axi write trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_aw_resp_en_mmu_ecc( + &mut self, + ) -> SPI_MEM_AW_RESP_EN_MMU_ECC_W { + SPI_MEM_AW_RESP_EN_MMU_ECC_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to enable AXI response function for mmu sens in err axi write trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_aw_resp_en_mmu_sens( + &mut self, + ) -> SPI_MEM_AW_RESP_EN_MMU_SENS_W { + SPI_MEM_AW_RESP_EN_MMU_SENS_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to enable AXI response function for axi wstrb err in axi write trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_aw_resp_en_axi_wstrb( + &mut self, + ) -> SPI_MEM_AW_RESP_EN_AXI_WSTRB_W { + SPI_MEM_AW_RESP_EN_AXI_WSTRB_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to enable AXI response function for mmu valid err in axi read trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ar_resp_en_mmu_vld( + &mut self, + ) -> SPI_MEM_AR_RESP_EN_MMU_VLD_W { + SPI_MEM_AR_RESP_EN_MMU_VLD_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to enable AXI response function for mmu gid err in axi read trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ar_resp_en_mmu_gid( + &mut self, + ) -> SPI_MEM_AR_RESP_EN_MMU_GID_W { + SPI_MEM_AR_RESP_EN_MMU_GID_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to enable AXI response function for mmu ecc err in axi read trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ar_resp_en_mmu_ecc( + &mut self, + ) -> SPI_MEM_AR_RESP_EN_MMU_ECC_W { + SPI_MEM_AR_RESP_EN_MMU_ECC_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to enable AXI response function for mmu sensitive err in axi read trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ar_resp_en_mmu_sens( + &mut self, + ) -> SPI_MEM_AR_RESP_EN_MMU_SENS_W { + SPI_MEM_AR_RESP_EN_MMU_SENS_W::new(self, 10) + } + #[doc = "Bit 11 - Set this bit to enable AXI response function for axi size err in axi read trans."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ar_resp_en_axi_size( + &mut self, + ) -> SPI_MEM_AR_RESP_EN_AXI_SIZE_W { + SPI_MEM_AR_RESP_EN_AXI_SIZE_W::new(self, 11) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 AXI error response enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_axi_err_resp_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_axi_err_resp_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_AXI_ERR_RESP_EN_SPEC; +impl crate::RegisterSpec for SPI_MEM_AXI_ERR_RESP_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_axi_err_resp_en::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_AXI_ERR_RESP_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_axi_err_resp_en::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_AXI_ERR_RESP_EN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_AXI_ERR_RESP_EN to value 0"] +impl crate::Resettable for SPI_MEM_AXI_ERR_RESP_EN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_cache_fctrl.rs b/esp32p4/src/spi0/spi_mem_cache_fctrl.rs new file mode 100644 index 0000000000..7b844241ae --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_cache_fctrl.rs @@ -0,0 +1,262 @@ +#[doc = "Register `SPI_MEM_CACHE_FCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CACHE_FCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_AXI_REQ_EN` reader - For SPI0, AXI master access enable, 1: enable, 0:disable."] +pub type SPI_MEM_AXI_REQ_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AXI_REQ_EN` writer - For SPI0, AXI master access enable, 1: enable, 0:disable."] +pub type SPI_MEM_AXI_REQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_CACHE_USR_ADDR_4BYTE` reader - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."] +pub type SPI_MEM_CACHE_USR_ADDR_4BYTE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CACHE_USR_ADDR_4BYTE` writer - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."] +pub type SPI_MEM_CACHE_USR_ADDR_4BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_CACHE_FLASH_USR_CMD` reader - For SPI0, cache read flash for user define command, 1: enable, 0:disable."] +pub type SPI_MEM_CACHE_FLASH_USR_CMD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CACHE_FLASH_USR_CMD` writer - For SPI0, cache read flash for user define command, 1: enable, 0:disable."] +pub type SPI_MEM_CACHE_FLASH_USR_CMD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDIN_DUAL` reader - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FDIN_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDIN_DUAL` writer - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FDIN_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDOUT_DUAL` reader - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FDOUT_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDOUT_DUAL` writer - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FDOUT_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FADDR_DUAL` reader - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FADDR_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FADDR_DUAL` writer - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDIN_QUAD` reader - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FDIN_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDIN_QUAD` writer - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FDIN_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDOUT_QUAD` reader - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FDOUT_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDOUT_QUAD` writer - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FDOUT_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FADDR_QUAD` reader - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FADDR_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FADDR_QUAD` writer - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SAME_AW_AR_ADDR_CHK_EN` reader - Set this bit to check AXI read/write the same address region."] +pub type SPI_SAME_AW_AR_ADDR_CHK_EN_R = crate::BitReader; +#[doc = "Field `SPI_SAME_AW_AR_ADDR_CHK_EN` writer - Set this bit to check AXI read/write the same address region."] +pub type SPI_SAME_AW_AR_ADDR_CHK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CLOSE_AXI_INF_EN` reader - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP."] +pub type SPI_CLOSE_AXI_INF_EN_R = crate::BitReader; +#[doc = "Field `SPI_CLOSE_AXI_INF_EN` writer - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP."] +pub type SPI_CLOSE_AXI_INF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - For SPI0, AXI master access enable, 1: enable, 0:disable."] + #[inline(always)] + pub fn spi_mem_axi_req_en(&self) -> SPI_MEM_AXI_REQ_EN_R { + SPI_MEM_AXI_REQ_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."] + #[inline(always)] + pub fn spi_mem_cache_usr_addr_4byte(&self) -> SPI_MEM_CACHE_USR_ADDR_4BYTE_R { + SPI_MEM_CACHE_USR_ADDR_4BYTE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - For SPI0, cache read flash for user define command, 1: enable, 0:disable."] + #[inline(always)] + pub fn spi_mem_cache_flash_usr_cmd(&self) -> SPI_MEM_CACHE_FLASH_USR_CMD_R { + SPI_MEM_CACHE_FLASH_USR_CMD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + pub fn spi_mem_fdin_dual(&self) -> SPI_MEM_FDIN_DUAL_R { + SPI_MEM_FDIN_DUAL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + pub fn spi_mem_fdout_dual(&self) -> SPI_MEM_FDOUT_DUAL_R { + SPI_MEM_FDOUT_DUAL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + pub fn spi_mem_faddr_dual(&self) -> SPI_MEM_FADDR_DUAL_R { + SPI_MEM_FADDR_DUAL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + pub fn spi_mem_fdin_quad(&self) -> SPI_MEM_FDIN_QUAD_R { + SPI_MEM_FDIN_QUAD_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + pub fn spi_mem_fdout_quad(&self) -> SPI_MEM_FDOUT_QUAD_R { + SPI_MEM_FDOUT_QUAD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + pub fn spi_mem_faddr_quad(&self) -> SPI_MEM_FADDR_QUAD_R { + SPI_MEM_FADDR_QUAD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 30 - Set this bit to check AXI read/write the same address region."] + #[inline(always)] + pub fn spi_same_aw_ar_addr_chk_en(&self) -> SPI_SAME_AW_AR_ADDR_CHK_EN_R { + SPI_SAME_AW_AR_ADDR_CHK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP."] + #[inline(always)] + pub fn spi_close_axi_inf_en(&self) -> SPI_CLOSE_AXI_INF_EN_R { + SPI_CLOSE_AXI_INF_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CACHE_FCTRL") + .field( + "spi_mem_axi_req_en", + &format_args!("{}", self.spi_mem_axi_req_en().bit()), + ) + .field( + "spi_mem_cache_usr_addr_4byte", + &format_args!("{}", self.spi_mem_cache_usr_addr_4byte().bit()), + ) + .field( + "spi_mem_cache_flash_usr_cmd", + &format_args!("{}", self.spi_mem_cache_flash_usr_cmd().bit()), + ) + .field( + "spi_mem_fdin_dual", + &format_args!("{}", self.spi_mem_fdin_dual().bit()), + ) + .field( + "spi_mem_fdout_dual", + &format_args!("{}", self.spi_mem_fdout_dual().bit()), + ) + .field( + "spi_mem_faddr_dual", + &format_args!("{}", self.spi_mem_faddr_dual().bit()), + ) + .field( + "spi_mem_fdin_quad", + &format_args!("{}", self.spi_mem_fdin_quad().bit()), + ) + .field( + "spi_mem_fdout_quad", + &format_args!("{}", self.spi_mem_fdout_quad().bit()), + ) + .field( + "spi_mem_faddr_quad", + &format_args!("{}", self.spi_mem_faddr_quad().bit()), + ) + .field( + "spi_same_aw_ar_addr_chk_en", + &format_args!("{}", self.spi_same_aw_ar_addr_chk_en().bit()), + ) + .field( + "spi_close_axi_inf_en", + &format_args!("{}", self.spi_close_axi_inf_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - For SPI0, AXI master access enable, 1: enable, 0:disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_axi_req_en(&mut self) -> SPI_MEM_AXI_REQ_EN_W { + SPI_MEM_AXI_REQ_EN_W::new(self, 0) + } + #[doc = "Bit 1 - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cache_usr_addr_4byte( + &mut self, + ) -> SPI_MEM_CACHE_USR_ADDR_4BYTE_W { + SPI_MEM_CACHE_USR_ADDR_4BYTE_W::new(self, 1) + } + #[doc = "Bit 2 - For SPI0, cache read flash for user define command, 1: enable, 0:disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cache_flash_usr_cmd( + &mut self, + ) -> SPI_MEM_CACHE_FLASH_USR_CMD_W { + SPI_MEM_CACHE_FLASH_USR_CMD_W::new(self, 2) + } + #[doc = "Bit 3 - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdin_dual(&mut self) -> SPI_MEM_FDIN_DUAL_W { + SPI_MEM_FDIN_DUAL_W::new(self, 3) + } + #[doc = "Bit 4 - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdout_dual(&mut self) -> SPI_MEM_FDOUT_DUAL_W { + SPI_MEM_FDOUT_DUAL_W::new(self, 4) + } + #[doc = "Bit 5 - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_faddr_dual(&mut self) -> SPI_MEM_FADDR_DUAL_W { + SPI_MEM_FADDR_DUAL_W::new(self, 5) + } + #[doc = "Bit 6 - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdin_quad(&mut self) -> SPI_MEM_FDIN_QUAD_W { + SPI_MEM_FDIN_QUAD_W::new(self, 6) + } + #[doc = "Bit 7 - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdout_quad(&mut self) -> SPI_MEM_FDOUT_QUAD_W { + SPI_MEM_FDOUT_QUAD_W::new(self, 7) + } + #[doc = "Bit 8 - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_faddr_quad(&mut self) -> SPI_MEM_FADDR_QUAD_W { + SPI_MEM_FADDR_QUAD_W::new(self, 8) + } + #[doc = "Bit 30 - Set this bit to check AXI read/write the same address region."] + #[inline(always)] + #[must_use] + pub fn spi_same_aw_ar_addr_chk_en( + &mut self, + ) -> SPI_SAME_AW_AR_ADDR_CHK_EN_W { + SPI_SAME_AW_AR_ADDR_CHK_EN_W::new(self, 30) + } + #[doc = "Bit 31 - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP."] + #[inline(always)] + #[must_use] + pub fn spi_close_axi_inf_en(&mut self) -> SPI_CLOSE_AXI_INF_EN_W { + SPI_CLOSE_AXI_INF_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 bit mode control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_cache_fctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_cache_fctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CACHE_FCTRL_SPEC; +impl crate::RegisterSpec for SPI_MEM_CACHE_FCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_cache_fctrl::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CACHE_FCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_cache_fctrl::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CACHE_FCTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CACHE_FCTRL to value 0xc000_0000"] +impl crate::Resettable for SPI_MEM_CACHE_FCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0xc000_0000; +} diff --git a/esp32p4/src/spi0/spi_mem_cache_sctrl.rs b/esp32p4/src/spi0/spi_mem_cache_sctrl.rs new file mode 100644 index 0000000000..18caf5198c --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_cache_sctrl.rs @@ -0,0 +1,272 @@ +#[doc = "Register `SPI_MEM_CACHE_SCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CACHE_SCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CACHE_USR_SADDR_4BYTE` reader - For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable."] +pub type SPI_MEM_CACHE_USR_SADDR_4BYTE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CACHE_USR_SADDR_4BYTE` writer - For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable."] +pub type SPI_MEM_CACHE_USR_SADDR_4BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_SRAM_DIO` reader - For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable"] +pub type SPI_MEM_USR_SRAM_DIO_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_SRAM_DIO` writer - For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable"] +pub type SPI_MEM_USR_SRAM_DIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_SRAM_QIO` reader - For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable"] +pub type SPI_MEM_USR_SRAM_QIO_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_SRAM_QIO` writer - For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable"] +pub type SPI_MEM_USR_SRAM_QIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_WR_SRAM_DUMMY` reader - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations."] +pub type SPI_MEM_USR_WR_SRAM_DUMMY_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_WR_SRAM_DUMMY` writer - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations."] +pub type SPI_MEM_USR_WR_SRAM_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_RD_SRAM_DUMMY` reader - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations."] +pub type SPI_MEM_USR_RD_SRAM_DUMMY_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_RD_SRAM_DUMMY` writer - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations."] +pub type SPI_MEM_USR_RD_SRAM_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_RCMD` reader - For SPI0, In the external RAM mode cache read external RAM for user define command."] +pub type SPI_MEM_CACHE_SRAM_USR_RCMD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_RCMD` writer - For SPI0, In the external RAM mode cache read external RAM for user define command."] +pub type SPI_MEM_CACHE_SRAM_USR_RCMD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SRAM_RDUMMY_CYCLELEN` reader - For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1)."] +pub type SPI_MEM_SRAM_RDUMMY_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_SRAM_RDUMMY_CYCLELEN` writer - For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1)."] +pub type SPI_MEM_SRAM_RDUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_MEM_SRAM_ADDR_BITLEN` reader - For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1)."] +pub type SPI_MEM_SRAM_ADDR_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_SRAM_ADDR_BITLEN` writer - For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1)."] +pub type SPI_MEM_SRAM_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_WCMD` reader - For SPI0, In the external RAM mode cache write sram for user define command"] +pub type SPI_MEM_CACHE_SRAM_USR_WCMD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_WCMD` writer - For SPI0, In the external RAM mode cache write sram for user define command"] +pub type SPI_MEM_CACHE_SRAM_USR_WCMD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SRAM_OCT` reader - reserved"] +pub type SPI_MEM_SRAM_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SRAM_OCT` writer - reserved"] +pub type SPI_MEM_SRAM_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SRAM_WDUMMY_CYCLELEN` reader - For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1)."] +pub type SPI_MEM_SRAM_WDUMMY_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_SRAM_WDUMMY_CYCLELEN` writer - For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1)."] +pub type SPI_MEM_SRAM_WDUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable."] + #[inline(always)] + pub fn spi_mem_cache_usr_saddr_4byte(&self) -> SPI_MEM_CACHE_USR_SADDR_4BYTE_R { + SPI_MEM_CACHE_USR_SADDR_4BYTE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable"] + #[inline(always)] + pub fn spi_mem_usr_sram_dio(&self) -> SPI_MEM_USR_SRAM_DIO_R { + SPI_MEM_USR_SRAM_DIO_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable"] + #[inline(always)] + pub fn spi_mem_usr_sram_qio(&self) -> SPI_MEM_USR_SRAM_QIO_R { + SPI_MEM_USR_SRAM_QIO_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations."] + #[inline(always)] + pub fn spi_mem_usr_wr_sram_dummy(&self) -> SPI_MEM_USR_WR_SRAM_DUMMY_R { + SPI_MEM_USR_WR_SRAM_DUMMY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations."] + #[inline(always)] + pub fn spi_mem_usr_rd_sram_dummy(&self) -> SPI_MEM_USR_RD_SRAM_DUMMY_R { + SPI_MEM_USR_RD_SRAM_DUMMY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - For SPI0, In the external RAM mode cache read external RAM for user define command."] + #[inline(always)] + pub fn spi_mem_cache_sram_usr_rcmd(&self) -> SPI_MEM_CACHE_SRAM_USR_RCMD_R { + SPI_MEM_CACHE_SRAM_USR_RCMD_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:11 - For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1)."] + #[inline(always)] + pub fn spi_mem_sram_rdummy_cyclelen(&self) -> SPI_MEM_SRAM_RDUMMY_CYCLELEN_R { + SPI_MEM_SRAM_RDUMMY_CYCLELEN_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 14:19 - For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1)."] + #[inline(always)] + pub fn spi_mem_sram_addr_bitlen(&self) -> SPI_MEM_SRAM_ADDR_BITLEN_R { + SPI_MEM_SRAM_ADDR_BITLEN_R::new(((self.bits >> 14) & 0x3f) as u8) + } + #[doc = "Bit 20 - For SPI0, In the external RAM mode cache write sram for user define command"] + #[inline(always)] + pub fn spi_mem_cache_sram_usr_wcmd(&self) -> SPI_MEM_CACHE_SRAM_USR_WCMD_R { + SPI_MEM_CACHE_SRAM_USR_WCMD_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - reserved"] + #[inline(always)] + pub fn spi_mem_sram_oct(&self) -> SPI_MEM_SRAM_OCT_R { + SPI_MEM_SRAM_OCT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 22:27 - For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1)."] + #[inline(always)] + pub fn spi_mem_sram_wdummy_cyclelen(&self) -> SPI_MEM_SRAM_WDUMMY_CYCLELEN_R { + SPI_MEM_SRAM_WDUMMY_CYCLELEN_R::new(((self.bits >> 22) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CACHE_SCTRL") + .field( + "spi_mem_cache_usr_saddr_4byte", + &format_args!("{}", self.spi_mem_cache_usr_saddr_4byte().bit()), + ) + .field( + "spi_mem_usr_sram_dio", + &format_args!("{}", self.spi_mem_usr_sram_dio().bit()), + ) + .field( + "spi_mem_usr_sram_qio", + &format_args!("{}", self.spi_mem_usr_sram_qio().bit()), + ) + .field( + "spi_mem_usr_wr_sram_dummy", + &format_args!("{}", self.spi_mem_usr_wr_sram_dummy().bit()), + ) + .field( + "spi_mem_usr_rd_sram_dummy", + &format_args!("{}", self.spi_mem_usr_rd_sram_dummy().bit()), + ) + .field( + "spi_mem_cache_sram_usr_rcmd", + &format_args!("{}", self.spi_mem_cache_sram_usr_rcmd().bit()), + ) + .field( + "spi_mem_sram_rdummy_cyclelen", + &format_args!("{}", self.spi_mem_sram_rdummy_cyclelen().bits()), + ) + .field( + "spi_mem_sram_addr_bitlen", + &format_args!("{}", self.spi_mem_sram_addr_bitlen().bits()), + ) + .field( + "spi_mem_cache_sram_usr_wcmd", + &format_args!("{}", self.spi_mem_cache_sram_usr_wcmd().bit()), + ) + .field( + "spi_mem_sram_oct", + &format_args!("{}", self.spi_mem_sram_oct().bit()), + ) + .field( + "spi_mem_sram_wdummy_cyclelen", + &format_args!("{}", self.spi_mem_sram_wdummy_cyclelen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cache_usr_saddr_4byte( + &mut self, + ) -> SPI_MEM_CACHE_USR_SADDR_4BYTE_W { + SPI_MEM_CACHE_USR_SADDR_4BYTE_W::new(self, 0) + } + #[doc = "Bit 1 - For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_sram_dio(&mut self) -> SPI_MEM_USR_SRAM_DIO_W { + SPI_MEM_USR_SRAM_DIO_W::new(self, 1) + } + #[doc = "Bit 2 - For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_sram_qio(&mut self) -> SPI_MEM_USR_SRAM_QIO_W { + SPI_MEM_USR_SRAM_QIO_W::new(self, 2) + } + #[doc = "Bit 3 - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_wr_sram_dummy( + &mut self, + ) -> SPI_MEM_USR_WR_SRAM_DUMMY_W { + SPI_MEM_USR_WR_SRAM_DUMMY_W::new(self, 3) + } + #[doc = "Bit 4 - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_rd_sram_dummy( + &mut self, + ) -> SPI_MEM_USR_RD_SRAM_DUMMY_W { + SPI_MEM_USR_RD_SRAM_DUMMY_W::new(self, 4) + } + #[doc = "Bit 5 - For SPI0, In the external RAM mode cache read external RAM for user define command."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cache_sram_usr_rcmd( + &mut self, + ) -> SPI_MEM_CACHE_SRAM_USR_RCMD_W { + SPI_MEM_CACHE_SRAM_USR_RCMD_W::new(self, 5) + } + #[doc = "Bits 6:11 - For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sram_rdummy_cyclelen( + &mut self, + ) -> SPI_MEM_SRAM_RDUMMY_CYCLELEN_W { + SPI_MEM_SRAM_RDUMMY_CYCLELEN_W::new(self, 6) + } + #[doc = "Bits 14:19 - For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sram_addr_bitlen( + &mut self, + ) -> SPI_MEM_SRAM_ADDR_BITLEN_W { + SPI_MEM_SRAM_ADDR_BITLEN_W::new(self, 14) + } + #[doc = "Bit 20 - For SPI0, In the external RAM mode cache write sram for user define command"] + #[inline(always)] + #[must_use] + pub fn spi_mem_cache_sram_usr_wcmd( + &mut self, + ) -> SPI_MEM_CACHE_SRAM_USR_WCMD_W { + SPI_MEM_CACHE_SRAM_USR_WCMD_W::new(self, 20) + } + #[doc = "Bit 21 - reserved"] + #[inline(always)] + #[must_use] + pub fn spi_mem_sram_oct(&mut self) -> SPI_MEM_SRAM_OCT_W { + SPI_MEM_SRAM_OCT_W::new(self, 21) + } + #[doc = "Bits 22:27 - For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sram_wdummy_cyclelen( + &mut self, + ) -> SPI_MEM_SRAM_WDUMMY_CYCLELEN_W { + SPI_MEM_SRAM_WDUMMY_CYCLELEN_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 external RAM control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_cache_sctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_cache_sctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CACHE_SCTRL_SPEC; +impl crate::RegisterSpec for SPI_MEM_CACHE_SCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_cache_sctrl::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CACHE_SCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_cache_sctrl::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CACHE_SCTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CACHE_SCTRL to value 0x0055_c070"] +impl crate::Resettable for SPI_MEM_CACHE_SCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0055_c070; +} diff --git a/esp32p4/src/spi0/spi_mem_clock.rs b/esp32p4/src/spi0/spi_mem_clock.rs new file mode 100644 index 0000000000..1145f2a482 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_clock.rs @@ -0,0 +1,123 @@ +#[doc = "Register `SPI_MEM_CLOCK` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CLOCK` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CLKCNT_L` reader - In the master mode it must be equal to spi_mem_clkcnt_N."] +pub type SPI_MEM_CLKCNT_L_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CLKCNT_L` writer - In the master mode it must be equal to spi_mem_clkcnt_N."] +pub type SPI_MEM_CLKCNT_L_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MEM_CLKCNT_H` reader - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."] +pub type SPI_MEM_CLKCNT_H_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CLKCNT_H` writer - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."] +pub type SPI_MEM_CLKCNT_H_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MEM_CLKCNT_N` reader - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] +pub type SPI_MEM_CLKCNT_N_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CLKCNT_N` writer - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] +pub type SPI_MEM_CLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MEM_CLK_EQU_SYSCLK` reader - 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock."] +pub type SPI_MEM_CLK_EQU_SYSCLK_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CLK_EQU_SYSCLK` writer - 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock."] +pub type SPI_MEM_CLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."] + #[inline(always)] + pub fn spi_mem_clkcnt_l(&self) -> SPI_MEM_CLKCNT_L_R { + SPI_MEM_CLKCNT_L_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."] + #[inline(always)] + pub fn spi_mem_clkcnt_h(&self) -> SPI_MEM_CLKCNT_H_R { + SPI_MEM_CLKCNT_H_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] + #[inline(always)] + pub fn spi_mem_clkcnt_n(&self) -> SPI_MEM_CLKCNT_N_R { + SPI_MEM_CLKCNT_N_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 31 - 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock."] + #[inline(always)] + pub fn spi_mem_clk_equ_sysclk(&self) -> SPI_MEM_CLK_EQU_SYSCLK_R { + SPI_MEM_CLK_EQU_SYSCLK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CLOCK") + .field( + "spi_mem_clkcnt_l", + &format_args!("{}", self.spi_mem_clkcnt_l().bits()), + ) + .field( + "spi_mem_clkcnt_h", + &format_args!("{}", self.spi_mem_clkcnt_h().bits()), + ) + .field( + "spi_mem_clkcnt_n", + &format_args!("{}", self.spi_mem_clkcnt_n().bits()), + ) + .field( + "spi_mem_clk_equ_sysclk", + &format_args!("{}", self.spi_mem_clk_equ_sysclk().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."] + #[inline(always)] + #[must_use] + pub fn spi_mem_clkcnt_l(&mut self) -> SPI_MEM_CLKCNT_L_W { + SPI_MEM_CLKCNT_L_W::new(self, 0) + } + #[doc = "Bits 8:15 - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_clkcnt_h(&mut self) -> SPI_MEM_CLKCNT_H_W { + SPI_MEM_CLKCNT_H_W::new(self, 8) + } + #[doc = "Bits 16:23 - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] + #[inline(always)] + #[must_use] + pub fn spi_mem_clkcnt_n(&mut self) -> SPI_MEM_CLKCNT_N_W { + SPI_MEM_CLKCNT_N_W::new(self, 16) + } + #[doc = "Bit 31 - 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock."] + #[inline(always)] + #[must_use] + pub fn spi_mem_clk_equ_sysclk(&mut self) -> SPI_MEM_CLK_EQU_SYSCLK_W { + SPI_MEM_CLK_EQU_SYSCLK_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI clock division control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_clock::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_clock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CLOCK_SPEC; +impl crate::RegisterSpec for SPI_MEM_CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_clock::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CLOCK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_clock::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CLOCK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CLOCK to value 0x0003_0103"] +impl crate::Resettable for SPI_MEM_CLOCK_SPEC { + const RESET_VALUE: Self::Ux = 0x0003_0103; +} diff --git a/esp32p4/src/spi0/spi_mem_clock_gate.rs b/esp32p4/src/spi0/spi_mem_clock_gate.rs new file mode 100644 index 0000000000..59c36e2bdd --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_clock_gate.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_MEM_CLOCK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CLOCK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_CLK_EN` reader - Register clock gate enable signal. 1: Enable. 0: Disable."] +pub type SPI_CLK_EN_R = crate::BitReader; +#[doc = "Field `SPI_CLK_EN` writer - Register clock gate enable signal. 1: Enable. 0: Disable."] +pub type SPI_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."] + #[inline(always)] + pub fn spi_clk_en(&self) -> SPI_CLK_EN_R { + SPI_CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CLOCK_GATE") + .field("spi_clk_en", &format_args!("{}", self.spi_clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."] + #[inline(always)] + #[must_use] + pub fn spi_clk_en(&mut self) -> SPI_CLK_EN_W { + SPI_CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_clock_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_clock_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CLOCK_GATE_SPEC; +impl crate::RegisterSpec for SPI_MEM_CLOCK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_clock_gate::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CLOCK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_clock_gate::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CLOCK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CLOCK_GATE to value 0x01"] +impl crate::Resettable for SPI_MEM_CLOCK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/spi0/spi_mem_cmd.rs b/esp32p4/src/spi0/spi_mem_cmd.rs new file mode 100644 index 0000000000..980fcb542a --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_cmd.rs @@ -0,0 +1,58 @@ +#[doc = "Register `SPI_MEM_CMD` reader"] +pub type R = crate::R; +#[doc = "Field `SPI_MEM_MST_ST` reader - The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state."] +pub type SPI_MEM_MST_ST_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_SLV_ST` reader - The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state."] +pub type SPI_MEM_SLV_ST_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR` reader - SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_USR_R = crate::BitReader; +impl R { + #[doc = "Bits 0:3 - The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state."] + #[inline(always)] + pub fn spi_mem_mst_st(&self) -> SPI_MEM_MST_ST_R { + SPI_MEM_MST_ST_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state."] + #[inline(always)] + pub fn spi_mem_slv_st(&self) -> SPI_MEM_SLV_ST_R { + SPI_MEM_SLV_ST_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 18 - SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_usr(&self) -> SPI_MEM_USR_R { + SPI_MEM_USR_R::new(((self.bits >> 18) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CMD") + .field( + "spi_mem_mst_st", + &format_args!("{}", self.spi_mem_mst_st().bits()), + ) + .field( + "spi_mem_slv_st", + &format_args!("{}", self.spi_mem_slv_st().bits()), + ) + .field("spi_mem_usr", &format_args!("{}", self.spi_mem_usr().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "SPI0 FSM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_cmd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CMD_SPEC; +impl crate::RegisterSpec for SPI_MEM_CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_cmd::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CMD_SPEC {} +#[doc = "`reset()` method sets SPI_MEM_CMD to value 0"] +impl crate::Resettable for SPI_MEM_CMD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_ctrl.rs b/esp32p4/src/spi0/spi_mem_ctrl.rs new file mode 100644 index 0000000000..55e47f903d --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_ctrl.rs @@ -0,0 +1,407 @@ +#[doc = "Register `SPI_MEM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_WDUMMY_DQS_ALWAYS_OUT` reader - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller."] +pub type SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WDUMMY_DQS_ALWAYS_OUT` writer - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller."] +pub type SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WDUMMY_ALWAYS_OUT` reader - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."] +pub type SPI_MEM_WDUMMY_ALWAYS_OUT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WDUMMY_ALWAYS_OUT` writer - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."] +pub type SPI_MEM_WDUMMY_ALWAYS_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDUMMY_RIN` reader - In an MSPI read data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase."] +pub type SPI_MEM_FDUMMY_RIN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDUMMY_RIN` writer - In an MSPI read data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase."] +pub type SPI_MEM_FDUMMY_RIN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDUMMY_WOUT` reader - In an MSPI write data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash."] +pub type SPI_MEM_FDUMMY_WOUT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDUMMY_WOUT` writer - In an MSPI write data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash."] +pub type SPI_MEM_FDUMMY_WOUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDOUT_OCT` reader - Apply 8 signals during write-data phase 1:enable 0: disable"] +pub type SPI_MEM_FDOUT_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDOUT_OCT` writer - Apply 8 signals during write-data phase 1:enable 0: disable"] +pub type SPI_MEM_FDOUT_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDIN_OCT` reader - Apply 8 signals during read-data phase 1:enable 0: disable"] +pub type SPI_MEM_FDIN_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDIN_OCT` writer - Apply 8 signals during read-data phase 1:enable 0: disable"] +pub type SPI_MEM_FDIN_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FADDR_OCT` reader - Apply 8 signals during address phase 1:enable 0: disable"] +pub type SPI_MEM_FADDR_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FADDR_OCT` writer - Apply 8 signals during address phase 1:enable 0: disable"] +pub type SPI_MEM_FADDR_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FCMD_QUAD` reader - Apply 4 signals during command phase 1:enable 0: disable"] +pub type SPI_MEM_FCMD_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FCMD_QUAD` writer - Apply 4 signals during command phase 1:enable 0: disable"] +pub type SPI_MEM_FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FCMD_OCT` reader - Apply 8 signals during command phase 1:enable 0: disable"] +pub type SPI_MEM_FCMD_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FCMD_OCT` writer - Apply 8 signals during command phase 1:enable 0: disable"] +pub type SPI_MEM_FCMD_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FASTRD_MODE` reader - This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable."] +pub type SPI_MEM_FASTRD_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FASTRD_MODE` writer - This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable."] +pub type SPI_MEM_FASTRD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low"] +pub type SPI_MEM_Q_POL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low"] +pub type SPI_MEM_Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low"] +pub type SPI_MEM_D_POL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low"] +pub type SPI_MEM_D_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WP` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low."] +pub type SPI_MEM_WP_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WP` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low."] +pub type SPI_MEM_WP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FREAD_DIO` reader - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_DIO_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FREAD_DIO` writer - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_DIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FREAD_QIO` reader - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_QIO_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FREAD_QIO` writer - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_QIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DQS_IE_ALWAYS_ON` reader - When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."] +pub type SPI_MEM_DQS_IE_ALWAYS_ON_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DQS_IE_ALWAYS_ON` writer - When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."] +pub type SPI_MEM_DQS_IE_ALWAYS_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DATA_IE_ALWAYS_ON` reader - When accesses to flash, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."] +pub type SPI_MEM_DATA_IE_ALWAYS_ON_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DATA_IE_ALWAYS_ON` writer - When accesses to flash, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."] +pub type SPI_MEM_DATA_IE_ALWAYS_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller."] + #[inline(always)] + pub fn spi_mem_wdummy_dqs_always_out(&self) -> SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_R { + SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."] + #[inline(always)] + pub fn spi_mem_wdummy_always_out(&self) -> SPI_MEM_WDUMMY_ALWAYS_OUT_R { + SPI_MEM_WDUMMY_ALWAYS_OUT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - In an MSPI read data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase."] + #[inline(always)] + pub fn spi_mem_fdummy_rin(&self) -> SPI_MEM_FDUMMY_RIN_R { + SPI_MEM_FDUMMY_RIN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - In an MSPI write data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash."] + #[inline(always)] + pub fn spi_mem_fdummy_wout(&self) -> SPI_MEM_FDUMMY_WOUT_R { + SPI_MEM_FDUMMY_WOUT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Apply 8 signals during write-data phase 1:enable 0: disable"] + #[inline(always)] + pub fn spi_mem_fdout_oct(&self) -> SPI_MEM_FDOUT_OCT_R { + SPI_MEM_FDOUT_OCT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Apply 8 signals during read-data phase 1:enable 0: disable"] + #[inline(always)] + pub fn spi_mem_fdin_oct(&self) -> SPI_MEM_FDIN_OCT_R { + SPI_MEM_FDIN_OCT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Apply 8 signals during address phase 1:enable 0: disable"] + #[inline(always)] + pub fn spi_mem_faddr_oct(&self) -> SPI_MEM_FADDR_OCT_R { + SPI_MEM_FADDR_OCT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"] + #[inline(always)] + pub fn spi_mem_fcmd_quad(&self) -> SPI_MEM_FCMD_QUAD_R { + SPI_MEM_FCMD_QUAD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Apply 8 signals during command phase 1:enable 0: disable"] + #[inline(always)] + pub fn spi_mem_fcmd_oct(&self) -> SPI_MEM_FCMD_OCT_R { + SPI_MEM_FCMD_OCT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 13 - This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_fastrd_mode(&self) -> SPI_MEM_FASTRD_MODE_R { + SPI_MEM_FASTRD_MODE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_fread_dual(&self) -> SPI_MEM_FREAD_DUAL_R { + SPI_MEM_FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"] + #[inline(always)] + pub fn spi_mem_q_pol(&self) -> SPI_MEM_Q_POL_R { + SPI_MEM_Q_POL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"] + #[inline(always)] + pub fn spi_mem_d_pol(&self) -> SPI_MEM_D_POL_R { + SPI_MEM_D_POL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_fread_quad(&self) -> SPI_MEM_FREAD_QUAD_R { + SPI_MEM_FREAD_QUAD_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."] + #[inline(always)] + pub fn spi_mem_wp(&self) -> SPI_MEM_WP_R { + SPI_MEM_WP_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_fread_dio(&self) -> SPI_MEM_FREAD_DIO_R { + SPI_MEM_FREAD_DIO_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_fread_qio(&self) -> SPI_MEM_FREAD_QIO_R { + SPI_MEM_FREAD_QIO_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 30 - When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."] + #[inline(always)] + pub fn spi_mem_dqs_ie_always_on(&self) -> SPI_MEM_DQS_IE_ALWAYS_ON_R { + SPI_MEM_DQS_IE_ALWAYS_ON_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - When accesses to flash, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."] + #[inline(always)] + pub fn spi_mem_data_ie_always_on(&self) -> SPI_MEM_DATA_IE_ALWAYS_ON_R { + SPI_MEM_DATA_IE_ALWAYS_ON_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CTRL") + .field( + "spi_mem_wdummy_dqs_always_out", + &format_args!("{}", self.spi_mem_wdummy_dqs_always_out().bit()), + ) + .field( + "spi_mem_wdummy_always_out", + &format_args!("{}", self.spi_mem_wdummy_always_out().bit()), + ) + .field( + "spi_mem_fdummy_rin", + &format_args!("{}", self.spi_mem_fdummy_rin().bit()), + ) + .field( + "spi_mem_fdummy_wout", + &format_args!("{}", self.spi_mem_fdummy_wout().bit()), + ) + .field( + "spi_mem_fdout_oct", + &format_args!("{}", self.spi_mem_fdout_oct().bit()), + ) + .field( + "spi_mem_fdin_oct", + &format_args!("{}", self.spi_mem_fdin_oct().bit()), + ) + .field( + "spi_mem_faddr_oct", + &format_args!("{}", self.spi_mem_faddr_oct().bit()), + ) + .field( + "spi_mem_fcmd_quad", + &format_args!("{}", self.spi_mem_fcmd_quad().bit()), + ) + .field( + "spi_mem_fcmd_oct", + &format_args!("{}", self.spi_mem_fcmd_oct().bit()), + ) + .field( + "spi_mem_fastrd_mode", + &format_args!("{}", self.spi_mem_fastrd_mode().bit()), + ) + .field( + "spi_mem_fread_dual", + &format_args!("{}", self.spi_mem_fread_dual().bit()), + ) + .field( + "spi_mem_q_pol", + &format_args!("{}", self.spi_mem_q_pol().bit()), + ) + .field( + "spi_mem_d_pol", + &format_args!("{}", self.spi_mem_d_pol().bit()), + ) + .field( + "spi_mem_fread_quad", + &format_args!("{}", self.spi_mem_fread_quad().bit()), + ) + .field("spi_mem_wp", &format_args!("{}", self.spi_mem_wp().bit())) + .field( + "spi_mem_fread_dio", + &format_args!("{}", self.spi_mem_fread_dio().bit()), + ) + .field( + "spi_mem_fread_qio", + &format_args!("{}", self.spi_mem_fread_qio().bit()), + ) + .field( + "spi_mem_dqs_ie_always_on", + &format_args!("{}", self.spi_mem_dqs_ie_always_on().bit()), + ) + .field( + "spi_mem_data_ie_always_on", + &format_args!("{}", self.spi_mem_data_ie_always_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wdummy_dqs_always_out( + &mut self, + ) -> SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_W { + SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_W::new(self, 0) + } + #[doc = "Bit 1 - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wdummy_always_out(&mut self) -> SPI_MEM_WDUMMY_ALWAYS_OUT_W { + SPI_MEM_WDUMMY_ALWAYS_OUT_W::new(self, 1) + } + #[doc = "Bit 2 - In an MSPI read data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdummy_rin(&mut self) -> SPI_MEM_FDUMMY_RIN_W { + SPI_MEM_FDUMMY_RIN_W::new(self, 2) + } + #[doc = "Bit 3 - In an MSPI write data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdummy_wout(&mut self) -> SPI_MEM_FDUMMY_WOUT_W { + SPI_MEM_FDUMMY_WOUT_W::new(self, 3) + } + #[doc = "Bit 4 - Apply 8 signals during write-data phase 1:enable 0: disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdout_oct(&mut self) -> SPI_MEM_FDOUT_OCT_W { + SPI_MEM_FDOUT_OCT_W::new(self, 4) + } + #[doc = "Bit 5 - Apply 8 signals during read-data phase 1:enable 0: disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdin_oct(&mut self) -> SPI_MEM_FDIN_OCT_W { + SPI_MEM_FDIN_OCT_W::new(self, 5) + } + #[doc = "Bit 6 - Apply 8 signals during address phase 1:enable 0: disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_faddr_oct(&mut self) -> SPI_MEM_FADDR_OCT_W { + SPI_MEM_FADDR_OCT_W::new(self, 6) + } + #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_fcmd_quad(&mut self) -> SPI_MEM_FCMD_QUAD_W { + SPI_MEM_FCMD_QUAD_W::new(self, 8) + } + #[doc = "Bit 9 - Apply 8 signals during command phase 1:enable 0: disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_fcmd_oct(&mut self) -> SPI_MEM_FCMD_OCT_W { + SPI_MEM_FCMD_OCT_W::new(self, 9) + } + #[doc = "Bit 13 - This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fastrd_mode(&mut self) -> SPI_MEM_FASTRD_MODE_W { + SPI_MEM_FASTRD_MODE_W::new(self, 13) + } + #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fread_dual(&mut self) -> SPI_MEM_FREAD_DUAL_W { + SPI_MEM_FREAD_DUAL_W::new(self, 14) + } + #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"] + #[inline(always)] + #[must_use] + pub fn spi_mem_q_pol(&mut self) -> SPI_MEM_Q_POL_W { + SPI_MEM_Q_POL_W::new(self, 18) + } + #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"] + #[inline(always)] + #[must_use] + pub fn spi_mem_d_pol(&mut self) -> SPI_MEM_D_POL_W { + SPI_MEM_D_POL_W::new(self, 19) + } + #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fread_quad(&mut self) -> SPI_MEM_FREAD_QUAD_W { + SPI_MEM_FREAD_QUAD_W::new(self, 20) + } + #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wp(&mut self) -> SPI_MEM_WP_W { + SPI_MEM_WP_W::new(self, 21) + } + #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fread_dio(&mut self) -> SPI_MEM_FREAD_DIO_W { + SPI_MEM_FREAD_DIO_W::new(self, 23) + } + #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fread_qio(&mut self) -> SPI_MEM_FREAD_QIO_W { + SPI_MEM_FREAD_QIO_W::new(self, 24) + } + #[doc = "Bit 30 - When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_dqs_ie_always_on(&mut self) -> SPI_MEM_DQS_IE_ALWAYS_ON_W { + SPI_MEM_DQS_IE_ALWAYS_ON_W::new(self, 30) + } + #[doc = "Bit 31 - When accesses to flash, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_data_ie_always_on(&mut self) -> SPI_MEM_DATA_IE_ALWAYS_ON_W { + SPI_MEM_DATA_IE_ALWAYS_ON_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CTRL_SPEC; +impl crate::RegisterSpec for SPI_MEM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_ctrl::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_ctrl::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CTRL to value 0x802c_200c"] +impl crate::Resettable for SPI_MEM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x802c_200c; +} diff --git a/esp32p4/src/spi0/spi_mem_ctrl1.rs b/esp32p4/src/spi0/spi_mem_ctrl1.rs new file mode 100644 index 0000000000..043f7e4c48 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_ctrl1.rs @@ -0,0 +1,237 @@ +#[doc = "Register `SPI_MEM_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."] +pub type SPI_MEM_CLK_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CLK_MODE` writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."] +pub type SPI_MEM_CLK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_AR_SIZE0_1_SUPPORT_EN` reader - 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR."] +pub type SPI_AR_SIZE0_1_SUPPORT_EN_R = crate::BitReader; +#[doc = "Field `SPI_AR_SIZE0_1_SUPPORT_EN` writer - 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR."] +pub type SPI_AR_SIZE0_1_SUPPORT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_AW_SIZE0_1_SUPPORT_EN` reader - 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR."] +pub type SPI_AW_SIZE0_1_SUPPORT_EN_R = crate::BitReader; +#[doc = "Field `SPI_AW_SIZE0_1_SUPPORT_EN` writer - 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR."] +pub type SPI_AW_SIZE0_1_SUPPORT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_AXI_RDATA_BACK_FAST` reader - 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available."] +pub type SPI_AXI_RDATA_BACK_FAST_R = crate::BitReader; +#[doc = "Field `SPI_AXI_RDATA_BACK_FAST` writer - 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available."] +pub type SPI_AXI_RDATA_BACK_FAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_RRESP_ECC_ERR_EN` reader - 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG."] +pub type SPI_MEM_RRESP_ECC_ERR_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_RRESP_ECC_ERR_EN` writer - 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG."] +pub type SPI_MEM_RRESP_ECC_ERR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AR_SPLICE_EN` reader - Set this bit to enable AXI Read Splice-transfer."] +pub type SPI_MEM_AR_SPLICE_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AR_SPLICE_EN` writer - Set this bit to enable AXI Read Splice-transfer."] +pub type SPI_MEM_AR_SPLICE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AW_SPLICE_EN` reader - Set this bit to enable AXI Write Splice-transfer."] +pub type SPI_MEM_AW_SPLICE_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AW_SPLICE_EN` writer - Set this bit to enable AXI Write Splice-transfer."] +pub type SPI_MEM_AW_SPLICE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_RAM0_EN` reader - When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time."] +pub type SPI_MEM_RAM0_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DUAL_RAM_EN` reader - Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time."] +pub type SPI_MEM_DUAL_RAM_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FAST_WRITE_EN` reader - Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2."] +pub type SPI_MEM_FAST_WRITE_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FAST_WRITE_EN` writer - Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2."] +pub type SPI_MEM_FAST_WRITE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_RXFIFO_RST` writer - The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO."] +pub type SPI_MEM_RXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_TXFIFO_RST` writer - The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO."] +pub type SPI_MEM_TXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."] + #[inline(always)] + pub fn spi_mem_clk_mode(&self) -> SPI_MEM_CLK_MODE_R { + SPI_MEM_CLK_MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 21 - 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR."] + #[inline(always)] + pub fn spi_ar_size0_1_support_en(&self) -> SPI_AR_SIZE0_1_SUPPORT_EN_R { + SPI_AR_SIZE0_1_SUPPORT_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR."] + #[inline(always)] + pub fn spi_aw_size0_1_support_en(&self) -> SPI_AW_SIZE0_1_SUPPORT_EN_R { + SPI_AW_SIZE0_1_SUPPORT_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available."] + #[inline(always)] + pub fn spi_axi_rdata_back_fast(&self) -> SPI_AXI_RDATA_BACK_FAST_R { + SPI_AXI_RDATA_BACK_FAST_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG."] + #[inline(always)] + pub fn spi_mem_rresp_ecc_err_en(&self) -> SPI_MEM_RRESP_ECC_ERR_EN_R { + SPI_MEM_RRESP_ECC_ERR_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Set this bit to enable AXI Read Splice-transfer."] + #[inline(always)] + pub fn spi_mem_ar_splice_en(&self) -> SPI_MEM_AR_SPLICE_EN_R { + SPI_MEM_AR_SPLICE_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to enable AXI Write Splice-transfer."] + #[inline(always)] + pub fn spi_mem_aw_splice_en(&self) -> SPI_MEM_AW_SPLICE_EN_R { + SPI_MEM_AW_SPLICE_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time."] + #[inline(always)] + pub fn spi_mem_ram0_en(&self) -> SPI_MEM_RAM0_EN_R { + SPI_MEM_RAM0_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time."] + #[inline(always)] + pub fn spi_mem_dual_ram_en(&self) -> SPI_MEM_DUAL_RAM_EN_R { + SPI_MEM_DUAL_RAM_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2."] + #[inline(always)] + pub fn spi_mem_fast_write_en(&self) -> SPI_MEM_FAST_WRITE_EN_R { + SPI_MEM_FAST_WRITE_EN_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CTRL1") + .field( + "spi_mem_clk_mode", + &format_args!("{}", self.spi_mem_clk_mode().bits()), + ) + .field( + "spi_ar_size0_1_support_en", + &format_args!("{}", self.spi_ar_size0_1_support_en().bit()), + ) + .field( + "spi_aw_size0_1_support_en", + &format_args!("{}", self.spi_aw_size0_1_support_en().bit()), + ) + .field( + "spi_axi_rdata_back_fast", + &format_args!("{}", self.spi_axi_rdata_back_fast().bit()), + ) + .field( + "spi_mem_rresp_ecc_err_en", + &format_args!("{}", self.spi_mem_rresp_ecc_err_en().bit()), + ) + .field( + "spi_mem_ar_splice_en", + &format_args!("{}", self.spi_mem_ar_splice_en().bit()), + ) + .field( + "spi_mem_aw_splice_en", + &format_args!("{}", self.spi_mem_aw_splice_en().bit()), + ) + .field( + "spi_mem_ram0_en", + &format_args!("{}", self.spi_mem_ram0_en().bit()), + ) + .field( + "spi_mem_dual_ram_en", + &format_args!("{}", self.spi_mem_dual_ram_en().bit()), + ) + .field( + "spi_mem_fast_write_en", + &format_args!("{}", self.spi_mem_fast_write_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."] + #[inline(always)] + #[must_use] + pub fn spi_mem_clk_mode(&mut self) -> SPI_MEM_CLK_MODE_W { + SPI_MEM_CLK_MODE_W::new(self, 0) + } + #[doc = "Bit 21 - 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR."] + #[inline(always)] + #[must_use] + pub fn spi_ar_size0_1_support_en(&mut self) -> SPI_AR_SIZE0_1_SUPPORT_EN_W { + SPI_AR_SIZE0_1_SUPPORT_EN_W::new(self, 21) + } + #[doc = "Bit 22 - 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR."] + #[inline(always)] + #[must_use] + pub fn spi_aw_size0_1_support_en(&mut self) -> SPI_AW_SIZE0_1_SUPPORT_EN_W { + SPI_AW_SIZE0_1_SUPPORT_EN_W::new(self, 22) + } + #[doc = "Bit 23 - 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available."] + #[inline(always)] + #[must_use] + pub fn spi_axi_rdata_back_fast(&mut self) -> SPI_AXI_RDATA_BACK_FAST_W { + SPI_AXI_RDATA_BACK_FAST_W::new(self, 23) + } + #[doc = "Bit 24 - 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG."] + #[inline(always)] + #[must_use] + pub fn spi_mem_rresp_ecc_err_en(&mut self) -> SPI_MEM_RRESP_ECC_ERR_EN_W { + SPI_MEM_RRESP_ECC_ERR_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Set this bit to enable AXI Read Splice-transfer."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ar_splice_en(&mut self) -> SPI_MEM_AR_SPLICE_EN_W { + SPI_MEM_AR_SPLICE_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to enable AXI Write Splice-transfer."] + #[inline(always)] + #[must_use] + pub fn spi_mem_aw_splice_en(&mut self) -> SPI_MEM_AW_SPLICE_EN_W { + SPI_MEM_AW_SPLICE_EN_W::new(self, 26) + } + #[doc = "Bit 29 - Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fast_write_en(&mut self) -> SPI_MEM_FAST_WRITE_EN_W { + SPI_MEM_FAST_WRITE_EN_W::new(self, 29) + } + #[doc = "Bit 30 - The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO."] + #[inline(always)] + #[must_use] + pub fn spi_mem_rxfifo_rst(&mut self) -> SPI_MEM_RXFIFO_RST_W { + SPI_MEM_RXFIFO_RST_W::new(self, 30) + } + #[doc = "Bit 31 - The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO."] + #[inline(always)] + #[must_use] + pub fn spi_mem_txfifo_rst(&mut self) -> SPI_MEM_TXFIFO_RST_W { + SPI_MEM_TXFIFO_RST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 control1 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CTRL1_SPEC; +impl crate::RegisterSpec for SPI_MEM_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_ctrl1::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_ctrl1::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CTRL1 to value 0x28e0_0000"] +impl crate::Resettable for SPI_MEM_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0x28e0_0000; +} diff --git a/esp32p4/src/spi0/spi_mem_ctrl2.rs b/esp32p4/src/spi0/spi_mem_ctrl2.rs new file mode 100644 index 0000000000..28755da332 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_ctrl2.rs @@ -0,0 +1,192 @@ +#[doc = "Register `SPI_MEM_CTRL2` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CS_SETUP_TIME` reader - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit."] +pub type SPI_MEM_CS_SETUP_TIME_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CS_SETUP_TIME` writer - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit."] +pub type SPI_MEM_CS_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SPI_MEM_CS_HOLD_TIME` reader - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit."] +pub type SPI_MEM_CS_HOLD_TIME_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CS_HOLD_TIME` writer - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit."] +pub type SPI_MEM_CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SPI_MEM_ECC_CS_HOLD_TIME` reader - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash."] +pub type SPI_MEM_ECC_CS_HOLD_TIME_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_ECC_CS_HOLD_TIME` writer - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash."] +pub type SPI_MEM_ECC_CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_MEM_ECC_SKIP_PAGE_CORNER` reader - 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash."] +pub type SPI_MEM_ECC_SKIP_PAGE_CORNER_R = crate::BitReader; +#[doc = "Field `SPI_MEM_ECC_SKIP_PAGE_CORNER` writer - 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash."] +pub type SPI_MEM_ECC_SKIP_PAGE_CORNER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_ECC_16TO18_BYTE_EN` reader - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash."] +pub type SPI_MEM_ECC_16TO18_BYTE_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_ECC_16TO18_BYTE_EN` writer - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash."] +pub type SPI_MEM_ECC_16TO18_BYTE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SPLIT_TRANS_EN` reader - Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not."] +pub type SPI_MEM_SPLIT_TRANS_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SPLIT_TRANS_EN` writer - Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not."] +pub type SPI_MEM_SPLIT_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_CS_HOLD_DELAY` reader - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."] +pub type SPI_MEM_CS_HOLD_DELAY_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CS_HOLD_DELAY` writer - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."] +pub type SPI_MEM_CS_HOLD_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_MEM_SYNC_RESET` writer - The spi0_mst_st and spi0_slv_st will be reset."] +pub type SPI_MEM_SYNC_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit."] + #[inline(always)] + pub fn spi_mem_cs_setup_time(&self) -> SPI_MEM_CS_SETUP_TIME_R { + SPI_MEM_CS_SETUP_TIME_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit."] + #[inline(always)] + pub fn spi_mem_cs_hold_time(&self) -> SPI_MEM_CS_HOLD_TIME_R { + SPI_MEM_CS_HOLD_TIME_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:12 - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash."] + #[inline(always)] + pub fn spi_mem_ecc_cs_hold_time(&self) -> SPI_MEM_ECC_CS_HOLD_TIME_R { + SPI_MEM_ECC_CS_HOLD_TIME_R::new(((self.bits >> 10) & 7) as u8) + } + #[doc = "Bit 13 - 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash."] + #[inline(always)] + pub fn spi_mem_ecc_skip_page_corner(&self) -> SPI_MEM_ECC_SKIP_PAGE_CORNER_R { + SPI_MEM_ECC_SKIP_PAGE_CORNER_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash."] + #[inline(always)] + pub fn spi_mem_ecc_16to18_byte_en(&self) -> SPI_MEM_ECC_16TO18_BYTE_EN_R { + SPI_MEM_ECC_16TO18_BYTE_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 24 - Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not."] + #[inline(always)] + pub fn spi_mem_split_trans_en(&self) -> SPI_MEM_SPLIT_TRANS_EN_R { + SPI_MEM_SPLIT_TRANS_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."] + #[inline(always)] + pub fn spi_mem_cs_hold_delay(&self) -> SPI_MEM_CS_HOLD_DELAY_R { + SPI_MEM_CS_HOLD_DELAY_R::new(((self.bits >> 25) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CTRL2") + .field( + "spi_mem_cs_setup_time", + &format_args!("{}", self.spi_mem_cs_setup_time().bits()), + ) + .field( + "spi_mem_cs_hold_time", + &format_args!("{}", self.spi_mem_cs_hold_time().bits()), + ) + .field( + "spi_mem_ecc_cs_hold_time", + &format_args!("{}", self.spi_mem_ecc_cs_hold_time().bits()), + ) + .field( + "spi_mem_ecc_skip_page_corner", + &format_args!("{}", self.spi_mem_ecc_skip_page_corner().bit()), + ) + .field( + "spi_mem_ecc_16to18_byte_en", + &format_args!("{}", self.spi_mem_ecc_16to18_byte_en().bit()), + ) + .field( + "spi_mem_split_trans_en", + &format_args!("{}", self.spi_mem_split_trans_en().bit()), + ) + .field( + "spi_mem_cs_hold_delay", + &format_args!("{}", self.spi_mem_cs_hold_delay().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:4 - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cs_setup_time(&mut self) -> SPI_MEM_CS_SETUP_TIME_W { + SPI_MEM_CS_SETUP_TIME_W::new(self, 0) + } + #[doc = "Bits 5:9 - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cs_hold_time(&mut self) -> SPI_MEM_CS_HOLD_TIME_W { + SPI_MEM_CS_HOLD_TIME_W::new(self, 5) + } + #[doc = "Bits 10:12 - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ecc_cs_hold_time(&mut self) -> SPI_MEM_ECC_CS_HOLD_TIME_W { + SPI_MEM_ECC_CS_HOLD_TIME_W::new(self, 10) + } + #[doc = "Bit 13 - 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ecc_skip_page_corner( + &mut self, + ) -> SPI_MEM_ECC_SKIP_PAGE_CORNER_W { + SPI_MEM_ECC_SKIP_PAGE_CORNER_W::new(self, 13) + } + #[doc = "Bit 14 - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ecc_16to18_byte_en( + &mut self, + ) -> SPI_MEM_ECC_16TO18_BYTE_EN_W { + SPI_MEM_ECC_16TO18_BYTE_EN_W::new(self, 14) + } + #[doc = "Bit 24 - Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not."] + #[inline(always)] + #[must_use] + pub fn spi_mem_split_trans_en(&mut self) -> SPI_MEM_SPLIT_TRANS_EN_W { + SPI_MEM_SPLIT_TRANS_EN_W::new(self, 24) + } + #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cs_hold_delay(&mut self) -> SPI_MEM_CS_HOLD_DELAY_W { + SPI_MEM_CS_HOLD_DELAY_W::new(self, 25) + } + #[doc = "Bit 31 - The spi0_mst_st and spi0_slv_st will be reset."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sync_reset(&mut self) -> SPI_MEM_SYNC_RESET_W { + SPI_MEM_SYNC_RESET_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 control2 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ctrl2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CTRL2_SPEC; +impl crate::RegisterSpec for SPI_MEM_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_ctrl2::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CTRL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_ctrl2::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CTRL2 to value 0x0100_2c21"] +impl crate::Resettable for SPI_MEM_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0x0100_2c21; +} diff --git a/esp32p4/src/spi0/spi_mem_date.rs b/esp32p4/src/spi0/spi_mem_date.rs new file mode 100644 index 0000000000..c23a40da60 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_date.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_DATE` reader - SPI0 register version."] +pub type SPI_MEM_DATE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DATE` writer - SPI0 register version."] +pub type SPI_MEM_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - SPI0 register version."] + #[inline(always)] + pub fn spi_mem_date(&self) -> SPI_MEM_DATE_R { + SPI_MEM_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_DATE") + .field( + "spi_mem_date", + &format_args!("{}", self.spi_mem_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - SPI0 register version."] + #[inline(always)] + #[must_use] + pub fn spi_mem_date(&mut self) -> SPI_MEM_DATE_W { + SPI_MEM_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_DATE_SPEC; +impl crate::RegisterSpec for SPI_MEM_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_date::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_date::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_DATE to value 0x0230_3100"] +impl crate::Resettable for SPI_MEM_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_3100; +} diff --git a/esp32p4/src/spi0/spi_mem_ddr.rs b/esp32p4/src/spi0/spi_mem_ddr.rs new file mode 100644 index 0000000000..48042e1d8d --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_ddr.rs @@ -0,0 +1,351 @@ +#[doc = "Register `SPI_MEM_DDR` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_DDR` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_FMEM_DDR_EN` reader - 1: in DDR mode, 0 in SDR mode"] +pub type SPI_FMEM_DDR_EN_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DDR_EN` writer - 1: in DDR mode, 0 in SDR mode"] +pub type SPI_FMEM_DDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_VAR_DUMMY` reader - Set the bit to enable variable dummy cycle in spi DDR mode."] +pub type SPI_FMEM_VAR_DUMMY_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_VAR_DUMMY` writer - Set the bit to enable variable dummy cycle in spi DDR mode."] +pub type SPI_FMEM_VAR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_DDR_RDAT_SWP` reader - Set the bit to reorder rx data of the word in spi DDR mode."] +pub type SPI_FMEM_DDR_RDAT_SWP_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DDR_RDAT_SWP` writer - Set the bit to reorder rx data of the word in spi DDR mode."] +pub type SPI_FMEM_DDR_RDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_DDR_WDAT_SWP` reader - Set the bit to reorder tx data of the word in spi DDR mode."] +pub type SPI_FMEM_DDR_WDAT_SWP_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DDR_WDAT_SWP` writer - Set the bit to reorder tx data of the word in spi DDR mode."] +pub type SPI_FMEM_DDR_WDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_DDR_CMD_DIS` reader - the bit is used to disable dual edge in command phase when DDR mode."] +pub type SPI_FMEM_DDR_CMD_DIS_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DDR_CMD_DIS` writer - the bit is used to disable dual edge in command phase when DDR mode."] +pub type SPI_FMEM_DDR_CMD_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_OUTMINBYTELEN` reader - It is the minimum output data length in the panda device."] +pub type SPI_FMEM_OUTMINBYTELEN_R = crate::FieldReader; +#[doc = "Field `SPI_FMEM_OUTMINBYTELEN` writer - It is the minimum output data length in the panda device."] +pub type SPI_FMEM_OUTMINBYTELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `SPI_FMEM_TX_DDR_MSK_EN` reader - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash."] +pub type SPI_FMEM_TX_DDR_MSK_EN_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_TX_DDR_MSK_EN` writer - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash."] +pub type SPI_FMEM_TX_DDR_MSK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_RX_DDR_MSK_EN` reader - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash."] +pub type SPI_FMEM_RX_DDR_MSK_EN_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_RX_DDR_MSK_EN` writer - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash."] +pub type SPI_FMEM_RX_DDR_MSK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_USR_DDR_DQS_THD` reader - The delay number of data strobe which from memory based on SPI clock."] +pub type SPI_FMEM_USR_DDR_DQS_THD_R = crate::FieldReader; +#[doc = "Field `SPI_FMEM_USR_DDR_DQS_THD` writer - The delay number of data strobe which from memory based on SPI clock."] +pub type SPI_FMEM_USR_DDR_DQS_THD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP` reader - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] +pub type SPI_FMEM_DDR_DQS_LOOP_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP` writer - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] +pub type SPI_FMEM_DDR_DQS_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_CLK_DIFF_EN` reader - Set this bit to enable the differential SPI_CLK#."] +pub type SPI_FMEM_CLK_DIFF_EN_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_CLK_DIFF_EN` writer - Set this bit to enable the differential SPI_CLK#."] +pub type SPI_FMEM_CLK_DIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_DQS_CA_IN` reader - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] +pub type SPI_FMEM_DQS_CA_IN_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DQS_CA_IN` writer - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] +pub type SPI_FMEM_DQS_CA_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_HYPERBUS_DUMMY_2X` reader - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] +pub type SPI_FMEM_HYPERBUS_DUMMY_2X_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_HYPERBUS_DUMMY_2X` writer - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] +pub type SPI_FMEM_HYPERBUS_DUMMY_2X_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_CLK_DIFF_INV` reader - Set this bit to invert SPI_DIFF when accesses to flash. ."] +pub type SPI_FMEM_CLK_DIFF_INV_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_CLK_DIFF_INV` writer - Set this bit to invert SPI_DIFF when accesses to flash. ."] +pub type SPI_FMEM_CLK_DIFF_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_OCTA_RAM_ADDR` reader - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] +pub type SPI_FMEM_OCTA_RAM_ADDR_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_OCTA_RAM_ADDR` writer - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] +pub type SPI_FMEM_OCTA_RAM_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_HYPERBUS_CA` reader - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] +pub type SPI_FMEM_HYPERBUS_CA_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_HYPERBUS_CA` writer - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] +pub type SPI_FMEM_HYPERBUS_CA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: in DDR mode, 0 in SDR mode"] + #[inline(always)] + pub fn spi_fmem_ddr_en(&self) -> SPI_FMEM_DDR_EN_R { + SPI_FMEM_DDR_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in spi DDR mode."] + #[inline(always)] + pub fn spi_fmem_var_dummy(&self) -> SPI_FMEM_VAR_DUMMY_R { + SPI_FMEM_VAR_DUMMY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set the bit to reorder rx data of the word in spi DDR mode."] + #[inline(always)] + pub fn spi_fmem_ddr_rdat_swp(&self) -> SPI_FMEM_DDR_RDAT_SWP_R { + SPI_FMEM_DDR_RDAT_SWP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set the bit to reorder tx data of the word in spi DDR mode."] + #[inline(always)] + pub fn spi_fmem_ddr_wdat_swp(&self) -> SPI_FMEM_DDR_WDAT_SWP_R { + SPI_FMEM_DDR_WDAT_SWP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the bit is used to disable dual edge in command phase when DDR mode."] + #[inline(always)] + pub fn spi_fmem_ddr_cmd_dis(&self) -> SPI_FMEM_DDR_CMD_DIS_R { + SPI_FMEM_DDR_CMD_DIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:11 - It is the minimum output data length in the panda device."] + #[inline(always)] + pub fn spi_fmem_outminbytelen(&self) -> SPI_FMEM_OUTMINBYTELEN_R { + SPI_FMEM_OUTMINBYTELEN_R::new(((self.bits >> 5) & 0x7f) as u8) + } + #[doc = "Bit 12 - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash."] + #[inline(always)] + pub fn spi_fmem_tx_ddr_msk_en(&self) -> SPI_FMEM_TX_DDR_MSK_EN_R { + SPI_FMEM_TX_DDR_MSK_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash."] + #[inline(always)] + pub fn spi_fmem_rx_ddr_msk_en(&self) -> SPI_FMEM_RX_DDR_MSK_EN_R { + SPI_FMEM_RX_DDR_MSK_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI clock."] + #[inline(always)] + pub fn spi_fmem_usr_ddr_dqs_thd(&self) -> SPI_FMEM_USR_DDR_DQS_THD_R { + SPI_FMEM_USR_DDR_DQS_THD_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bit 21 - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] + #[inline(always)] + pub fn spi_fmem_ddr_dqs_loop(&self) -> SPI_FMEM_DDR_DQS_LOOP_R { + SPI_FMEM_DDR_DQS_LOOP_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."] + #[inline(always)] + pub fn spi_fmem_clk_diff_en(&self) -> SPI_FMEM_CLK_DIFF_EN_R { + SPI_FMEM_CLK_DIFF_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] + #[inline(always)] + pub fn spi_fmem_dqs_ca_in(&self) -> SPI_FMEM_DQS_CA_IN_R { + SPI_FMEM_DQS_CA_IN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] + #[inline(always)] + pub fn spi_fmem_hyperbus_dummy_2x(&self) -> SPI_FMEM_HYPERBUS_DUMMY_2X_R { + SPI_FMEM_HYPERBUS_DUMMY_2X_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. ."] + #[inline(always)] + pub fn spi_fmem_clk_diff_inv(&self) -> SPI_FMEM_CLK_DIFF_INV_R { + SPI_FMEM_CLK_DIFF_INV_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] + #[inline(always)] + pub fn spi_fmem_octa_ram_addr(&self) -> SPI_FMEM_OCTA_RAM_ADDR_R { + SPI_FMEM_OCTA_RAM_ADDR_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] + #[inline(always)] + pub fn spi_fmem_hyperbus_ca(&self) -> SPI_FMEM_HYPERBUS_CA_R { + SPI_FMEM_HYPERBUS_CA_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_DDR") + .field( + "spi_fmem_ddr_en", + &format_args!("{}", self.spi_fmem_ddr_en().bit()), + ) + .field( + "spi_fmem_var_dummy", + &format_args!("{}", self.spi_fmem_var_dummy().bit()), + ) + .field( + "spi_fmem_ddr_rdat_swp", + &format_args!("{}", self.spi_fmem_ddr_rdat_swp().bit()), + ) + .field( + "spi_fmem_ddr_wdat_swp", + &format_args!("{}", self.spi_fmem_ddr_wdat_swp().bit()), + ) + .field( + "spi_fmem_ddr_cmd_dis", + &format_args!("{}", self.spi_fmem_ddr_cmd_dis().bit()), + ) + .field( + "spi_fmem_outminbytelen", + &format_args!("{}", self.spi_fmem_outminbytelen().bits()), + ) + .field( + "spi_fmem_tx_ddr_msk_en", + &format_args!("{}", self.spi_fmem_tx_ddr_msk_en().bit()), + ) + .field( + "spi_fmem_rx_ddr_msk_en", + &format_args!("{}", self.spi_fmem_rx_ddr_msk_en().bit()), + ) + .field( + "spi_fmem_usr_ddr_dqs_thd", + &format_args!("{}", self.spi_fmem_usr_ddr_dqs_thd().bits()), + ) + .field( + "spi_fmem_ddr_dqs_loop", + &format_args!("{}", self.spi_fmem_ddr_dqs_loop().bit()), + ) + .field( + "spi_fmem_clk_diff_en", + &format_args!("{}", self.spi_fmem_clk_diff_en().bit()), + ) + .field( + "spi_fmem_dqs_ca_in", + &format_args!("{}", self.spi_fmem_dqs_ca_in().bit()), + ) + .field( + "spi_fmem_hyperbus_dummy_2x", + &format_args!("{}", self.spi_fmem_hyperbus_dummy_2x().bit()), + ) + .field( + "spi_fmem_clk_diff_inv", + &format_args!("{}", self.spi_fmem_clk_diff_inv().bit()), + ) + .field( + "spi_fmem_octa_ram_addr", + &format_args!("{}", self.spi_fmem_octa_ram_addr().bit()), + ) + .field( + "spi_fmem_hyperbus_ca", + &format_args!("{}", self.spi_fmem_hyperbus_ca().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: in DDR mode, 0 in SDR mode"] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ddr_en(&mut self) -> SPI_FMEM_DDR_EN_W { + SPI_FMEM_DDR_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in spi DDR mode."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_var_dummy(&mut self) -> SPI_FMEM_VAR_DUMMY_W { + SPI_FMEM_VAR_DUMMY_W::new(self, 1) + } + #[doc = "Bit 2 - Set the bit to reorder rx data of the word in spi DDR mode."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ddr_rdat_swp(&mut self) -> SPI_FMEM_DDR_RDAT_SWP_W { + SPI_FMEM_DDR_RDAT_SWP_W::new(self, 2) + } + #[doc = "Bit 3 - Set the bit to reorder tx data of the word in spi DDR mode."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ddr_wdat_swp(&mut self) -> SPI_FMEM_DDR_WDAT_SWP_W { + SPI_FMEM_DDR_WDAT_SWP_W::new(self, 3) + } + #[doc = "Bit 4 - the bit is used to disable dual edge in command phase when DDR mode."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ddr_cmd_dis(&mut self) -> SPI_FMEM_DDR_CMD_DIS_W { + SPI_FMEM_DDR_CMD_DIS_W::new(self, 4) + } + #[doc = "Bits 5:11 - It is the minimum output data length in the panda device."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_outminbytelen(&mut self) -> SPI_FMEM_OUTMINBYTELEN_W { + SPI_FMEM_OUTMINBYTELEN_W::new(self, 5) + } + #[doc = "Bit 12 - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_tx_ddr_msk_en(&mut self) -> SPI_FMEM_TX_DDR_MSK_EN_W { + SPI_FMEM_TX_DDR_MSK_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_rx_ddr_msk_en(&mut self) -> SPI_FMEM_RX_DDR_MSK_EN_W { + SPI_FMEM_RX_DDR_MSK_EN_W::new(self, 13) + } + #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI clock."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_usr_ddr_dqs_thd(&mut self) -> SPI_FMEM_USR_DDR_DQS_THD_W { + SPI_FMEM_USR_DDR_DQS_THD_W::new(self, 14) + } + #[doc = "Bit 21 - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ddr_dqs_loop(&mut self) -> SPI_FMEM_DDR_DQS_LOOP_W { + SPI_FMEM_DDR_DQS_LOOP_W::new(self, 21) + } + #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_clk_diff_en(&mut self) -> SPI_FMEM_CLK_DIFF_EN_W { + SPI_FMEM_CLK_DIFF_EN_W::new(self, 24) + } + #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_dqs_ca_in(&mut self) -> SPI_FMEM_DQS_CA_IN_W { + SPI_FMEM_DQS_CA_IN_W::new(self, 26) + } + #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_hyperbus_dummy_2x(&mut self) -> SPI_FMEM_HYPERBUS_DUMMY_2X_W { + SPI_FMEM_HYPERBUS_DUMMY_2X_W::new(self, 27) + } + #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. ."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_clk_diff_inv(&mut self) -> SPI_FMEM_CLK_DIFF_INV_W { + SPI_FMEM_CLK_DIFF_INV_W::new(self, 28) + } + #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_octa_ram_addr(&mut self) -> SPI_FMEM_OCTA_RAM_ADDR_W { + SPI_FMEM_OCTA_RAM_ADDR_W::new(self, 29) + } + #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_hyperbus_ca(&mut self) -> SPI_FMEM_HYPERBUS_CA_W { + SPI_FMEM_HYPERBUS_CA_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 flash DDR mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ddr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_DDR_SPEC; +impl crate::RegisterSpec for SPI_MEM_DDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_ddr::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_DDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_ddr::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_DDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_DDR to value 0x3020"] +impl crate::Resettable for SPI_MEM_DDR_SPEC { + const RESET_VALUE: Self::Ux = 0x3020; +} diff --git a/esp32p4/src/spi0/spi_mem_din_mode.rs b/esp32p4/src/spi0/spi_mem_din_mode.rs new file mode 100644 index 0000000000..18d6f5ae3e --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_din_mode.rs @@ -0,0 +1,218 @@ +#[doc = "Register `SPI_MEM_DIN_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_DIN_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_DIN0_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_MEM_DIN0_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN0_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_MEM_DIN0_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_MEM_DIN1_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_MEM_DIN1_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN1_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_MEM_DIN1_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_MEM_DIN2_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_MEM_DIN2_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN2_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_MEM_DIN2_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_MEM_DIN3_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_MEM_DIN3_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN3_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_MEM_DIN3_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_MEM_DIN4_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] +pub type SPI_MEM_DIN4_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN4_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] +pub type SPI_MEM_DIN4_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_MEM_DIN5_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] +pub type SPI_MEM_DIN5_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN5_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] +pub type SPI_MEM_DIN5_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_MEM_DIN6_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] +pub type SPI_MEM_DIN6_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN6_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] +pub type SPI_MEM_DIN6_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_MEM_DIN7_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] +pub type SPI_MEM_DIN7_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN7_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] +pub type SPI_MEM_DIN7_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_MEM_DINS_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] +pub type SPI_MEM_DINS_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DINS_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] +pub type SPI_MEM_DINS_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_mem_din0_mode(&self) -> SPI_MEM_DIN0_MODE_R { + SPI_MEM_DIN0_MODE_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_mem_din1_mode(&self) -> SPI_MEM_DIN1_MODE_R { + SPI_MEM_DIN1_MODE_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_mem_din2_mode(&self) -> SPI_MEM_DIN2_MODE_R { + SPI_MEM_DIN2_MODE_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_mem_din3_mode(&self) -> SPI_MEM_DIN3_MODE_R { + SPI_MEM_DIN3_MODE_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] + #[inline(always)] + pub fn spi_mem_din4_mode(&self) -> SPI_MEM_DIN4_MODE_R { + SPI_MEM_DIN4_MODE_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] + #[inline(always)] + pub fn spi_mem_din5_mode(&self) -> SPI_MEM_DIN5_MODE_R { + SPI_MEM_DIN5_MODE_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] + #[inline(always)] + pub fn spi_mem_din6_mode(&self) -> SPI_MEM_DIN6_MODE_R { + SPI_MEM_DIN6_MODE_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] + #[inline(always)] + pub fn spi_mem_din7_mode(&self) -> SPI_MEM_DIN7_MODE_R { + SPI_MEM_DIN7_MODE_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] + #[inline(always)] + pub fn spi_mem_dins_mode(&self) -> SPI_MEM_DINS_MODE_R { + SPI_MEM_DINS_MODE_R::new(((self.bits >> 24) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_DIN_MODE") + .field( + "spi_mem_din0_mode", + &format_args!("{}", self.spi_mem_din0_mode().bits()), + ) + .field( + "spi_mem_din1_mode", + &format_args!("{}", self.spi_mem_din1_mode().bits()), + ) + .field( + "spi_mem_din2_mode", + &format_args!("{}", self.spi_mem_din2_mode().bits()), + ) + .field( + "spi_mem_din3_mode", + &format_args!("{}", self.spi_mem_din3_mode().bits()), + ) + .field( + "spi_mem_din4_mode", + &format_args!("{}", self.spi_mem_din4_mode().bits()), + ) + .field( + "spi_mem_din5_mode", + &format_args!("{}", self.spi_mem_din5_mode().bits()), + ) + .field( + "spi_mem_din6_mode", + &format_args!("{}", self.spi_mem_din6_mode().bits()), + ) + .field( + "spi_mem_din7_mode", + &format_args!("{}", self.spi_mem_din7_mode().bits()), + ) + .field( + "spi_mem_dins_mode", + &format_args!("{}", self.spi_mem_dins_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_mem_din0_mode(&mut self) -> SPI_MEM_DIN0_MODE_W { + SPI_MEM_DIN0_MODE_W::new(self, 0) + } + #[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_mem_din1_mode(&mut self) -> SPI_MEM_DIN1_MODE_W { + SPI_MEM_DIN1_MODE_W::new(self, 3) + } + #[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_mem_din2_mode(&mut self) -> SPI_MEM_DIN2_MODE_W { + SPI_MEM_DIN2_MODE_W::new(self, 6) + } + #[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_mem_din3_mode(&mut self) -> SPI_MEM_DIN3_MODE_W { + SPI_MEM_DIN3_MODE_W::new(self, 9) + } + #[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] + #[inline(always)] + #[must_use] + pub fn spi_mem_din4_mode(&mut self) -> SPI_MEM_DIN4_MODE_W { + SPI_MEM_DIN4_MODE_W::new(self, 12) + } + #[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] + #[inline(always)] + #[must_use] + pub fn spi_mem_din5_mode(&mut self) -> SPI_MEM_DIN5_MODE_W { + SPI_MEM_DIN5_MODE_W::new(self, 15) + } + #[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] + #[inline(always)] + #[must_use] + pub fn spi_mem_din6_mode(&mut self) -> SPI_MEM_DIN6_MODE_W { + SPI_MEM_DIN6_MODE_W::new(self, 18) + } + #[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] + #[inline(always)] + #[must_use] + pub fn spi_mem_din7_mode(&mut self) -> SPI_MEM_DIN7_MODE_W { + SPI_MEM_DIN7_MODE_W::new(self, 21) + } + #[doc = "Bits 24:26 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk"] + #[inline(always)] + #[must_use] + pub fn spi_mem_dins_mode(&mut self) -> SPI_MEM_DINS_MODE_W { + SPI_MEM_DINS_MODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI flash input timing delay mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_din_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_din_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_DIN_MODE_SPEC; +impl crate::RegisterSpec for SPI_MEM_DIN_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_din_mode::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_DIN_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_din_mode::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_DIN_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_DIN_MODE to value 0"] +impl crate::Resettable for SPI_MEM_DIN_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_din_num.rs b/esp32p4/src/spi0/spi_mem_din_num.rs new file mode 100644 index 0000000000..0463bb80e8 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_din_num.rs @@ -0,0 +1,218 @@ +#[doc = "Register `SPI_MEM_DIN_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_DIN_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_DIN0_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN0_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN0_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN0_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_MEM_DIN1_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN1_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN1_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN1_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_MEM_DIN2_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN2_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN2_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN2_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_MEM_DIN3_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN3_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN3_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN3_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_MEM_DIN4_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN4_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN4_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN4_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_MEM_DIN5_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN5_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN5_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN5_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_MEM_DIN6_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN6_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN6_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN6_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_MEM_DIN7_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN7_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DIN7_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DIN7_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_MEM_DINS_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DINS_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DINS_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_MEM_DINS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_mem_din0_num(&self) -> SPI_MEM_DIN0_NUM_R { + SPI_MEM_DIN0_NUM_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_mem_din1_num(&self) -> SPI_MEM_DIN1_NUM_R { + SPI_MEM_DIN1_NUM_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_mem_din2_num(&self) -> SPI_MEM_DIN2_NUM_R { + SPI_MEM_DIN2_NUM_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_mem_din3_num(&self) -> SPI_MEM_DIN3_NUM_R { + SPI_MEM_DIN3_NUM_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_mem_din4_num(&self) -> SPI_MEM_DIN4_NUM_R { + SPI_MEM_DIN4_NUM_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_mem_din5_num(&self) -> SPI_MEM_DIN5_NUM_R { + SPI_MEM_DIN5_NUM_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_mem_din6_num(&self) -> SPI_MEM_DIN6_NUM_R { + SPI_MEM_DIN6_NUM_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_mem_din7_num(&self) -> SPI_MEM_DIN7_NUM_R { + SPI_MEM_DIN7_NUM_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_mem_dins_num(&self) -> SPI_MEM_DINS_NUM_R { + SPI_MEM_DINS_NUM_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_DIN_NUM") + .field( + "spi_mem_din0_num", + &format_args!("{}", self.spi_mem_din0_num().bits()), + ) + .field( + "spi_mem_din1_num", + &format_args!("{}", self.spi_mem_din1_num().bits()), + ) + .field( + "spi_mem_din2_num", + &format_args!("{}", self.spi_mem_din2_num().bits()), + ) + .field( + "spi_mem_din3_num", + &format_args!("{}", self.spi_mem_din3_num().bits()), + ) + .field( + "spi_mem_din4_num", + &format_args!("{}", self.spi_mem_din4_num().bits()), + ) + .field( + "spi_mem_din5_num", + &format_args!("{}", self.spi_mem_din5_num().bits()), + ) + .field( + "spi_mem_din6_num", + &format_args!("{}", self.spi_mem_din6_num().bits()), + ) + .field( + "spi_mem_din7_num", + &format_args!("{}", self.spi_mem_din7_num().bits()), + ) + .field( + "spi_mem_dins_num", + &format_args!("{}", self.spi_mem_dins_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_mem_din0_num(&mut self) -> SPI_MEM_DIN0_NUM_W { + SPI_MEM_DIN0_NUM_W::new(self, 0) + } + #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_mem_din1_num(&mut self) -> SPI_MEM_DIN1_NUM_W { + SPI_MEM_DIN1_NUM_W::new(self, 2) + } + #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_mem_din2_num(&mut self) -> SPI_MEM_DIN2_NUM_W { + SPI_MEM_DIN2_NUM_W::new(self, 4) + } + #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_mem_din3_num(&mut self) -> SPI_MEM_DIN3_NUM_W { + SPI_MEM_DIN3_NUM_W::new(self, 6) + } + #[doc = "Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_mem_din4_num(&mut self) -> SPI_MEM_DIN4_NUM_W { + SPI_MEM_DIN4_NUM_W::new(self, 8) + } + #[doc = "Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_mem_din5_num(&mut self) -> SPI_MEM_DIN5_NUM_W { + SPI_MEM_DIN5_NUM_W::new(self, 10) + } + #[doc = "Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_mem_din6_num(&mut self) -> SPI_MEM_DIN6_NUM_W { + SPI_MEM_DIN6_NUM_W::new(self, 12) + } + #[doc = "Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_mem_din7_num(&mut self) -> SPI_MEM_DIN7_NUM_W { + SPI_MEM_DIN7_NUM_W::new(self, 14) + } + #[doc = "Bits 16:17 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_mem_dins_num(&mut self) -> SPI_MEM_DINS_NUM_W { + SPI_MEM_DINS_NUM_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI flash input timing delay number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_din_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_din_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_DIN_NUM_SPEC; +impl crate::RegisterSpec for SPI_MEM_DIN_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_din_num::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_DIN_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_din_num::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_DIN_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_DIN_NUM to value 0"] +impl crate::Resettable for SPI_MEM_DIN_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_dout_mode.rs b/esp32p4/src/spi0/spi_mem_dout_mode.rs new file mode 100644 index 0000000000..ae7f178cbf --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_dout_mode.rs @@ -0,0 +1,218 @@ +#[doc = "Register `SPI_MEM_DOUT_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_DOUT_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_DOUT0_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_MEM_DOUT0_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DOUT0_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_MEM_DOUT0_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DOUT1_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_MEM_DOUT1_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DOUT1_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_MEM_DOUT1_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DOUT2_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_MEM_DOUT2_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DOUT2_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_MEM_DOUT2_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DOUT3_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_MEM_DOUT3_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DOUT3_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_MEM_DOUT3_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DOUT4_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] +pub type SPI_MEM_DOUT4_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DOUT4_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] +pub type SPI_MEM_DOUT4_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DOUT5_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] +pub type SPI_MEM_DOUT5_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DOUT5_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] +pub type SPI_MEM_DOUT5_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DOUT6_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] +pub type SPI_MEM_DOUT6_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DOUT6_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] +pub type SPI_MEM_DOUT6_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DOUT7_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] +pub type SPI_MEM_DOUT7_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DOUT7_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] +pub type SPI_MEM_DOUT7_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DOUTS_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] +pub type SPI_MEM_DOUTS_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DOUTS_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] +pub type SPI_MEM_DOUTS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_mem_dout0_mode(&self) -> SPI_MEM_DOUT0_MODE_R { + SPI_MEM_DOUT0_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_mem_dout1_mode(&self) -> SPI_MEM_DOUT1_MODE_R { + SPI_MEM_DOUT1_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_mem_dout2_mode(&self) -> SPI_MEM_DOUT2_MODE_R { + SPI_MEM_DOUT2_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_mem_dout3_mode(&self) -> SPI_MEM_DOUT3_MODE_R { + SPI_MEM_DOUT3_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] + #[inline(always)] + pub fn spi_mem_dout4_mode(&self) -> SPI_MEM_DOUT4_MODE_R { + SPI_MEM_DOUT4_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] + #[inline(always)] + pub fn spi_mem_dout5_mode(&self) -> SPI_MEM_DOUT5_MODE_R { + SPI_MEM_DOUT5_MODE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] + #[inline(always)] + pub fn spi_mem_dout6_mode(&self) -> SPI_MEM_DOUT6_MODE_R { + SPI_MEM_DOUT6_MODE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] + #[inline(always)] + pub fn spi_mem_dout7_mode(&self) -> SPI_MEM_DOUT7_MODE_R { + SPI_MEM_DOUT7_MODE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] + #[inline(always)] + pub fn spi_mem_douts_mode(&self) -> SPI_MEM_DOUTS_MODE_R { + SPI_MEM_DOUTS_MODE_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_DOUT_MODE") + .field( + "spi_mem_dout0_mode", + &format_args!("{}", self.spi_mem_dout0_mode().bit()), + ) + .field( + "spi_mem_dout1_mode", + &format_args!("{}", self.spi_mem_dout1_mode().bit()), + ) + .field( + "spi_mem_dout2_mode", + &format_args!("{}", self.spi_mem_dout2_mode().bit()), + ) + .field( + "spi_mem_dout3_mode", + &format_args!("{}", self.spi_mem_dout3_mode().bit()), + ) + .field( + "spi_mem_dout4_mode", + &format_args!("{}", self.spi_mem_dout4_mode().bit()), + ) + .field( + "spi_mem_dout5_mode", + &format_args!("{}", self.spi_mem_dout5_mode().bit()), + ) + .field( + "spi_mem_dout6_mode", + &format_args!("{}", self.spi_mem_dout6_mode().bit()), + ) + .field( + "spi_mem_dout7_mode", + &format_args!("{}", self.spi_mem_dout7_mode().bit()), + ) + .field( + "spi_mem_douts_mode", + &format_args!("{}", self.spi_mem_douts_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_mem_dout0_mode(&mut self) -> SPI_MEM_DOUT0_MODE_W { + SPI_MEM_DOUT0_MODE_W::new(self, 0) + } + #[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_mem_dout1_mode(&mut self) -> SPI_MEM_DOUT1_MODE_W { + SPI_MEM_DOUT1_MODE_W::new(self, 1) + } + #[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_mem_dout2_mode(&mut self) -> SPI_MEM_DOUT2_MODE_W { + SPI_MEM_DOUT2_MODE_W::new(self, 2) + } + #[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_mem_dout3_mode(&mut self) -> SPI_MEM_DOUT3_MODE_W { + SPI_MEM_DOUT3_MODE_W::new(self, 3) + } + #[doc = "Bit 4 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] + #[inline(always)] + #[must_use] + pub fn spi_mem_dout4_mode(&mut self) -> SPI_MEM_DOUT4_MODE_W { + SPI_MEM_DOUT4_MODE_W::new(self, 4) + } + #[doc = "Bit 5 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] + #[inline(always)] + #[must_use] + pub fn spi_mem_dout5_mode(&mut self) -> SPI_MEM_DOUT5_MODE_W { + SPI_MEM_DOUT5_MODE_W::new(self, 5) + } + #[doc = "Bit 6 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] + #[inline(always)] + #[must_use] + pub fn spi_mem_dout6_mode(&mut self) -> SPI_MEM_DOUT6_MODE_W { + SPI_MEM_DOUT6_MODE_W::new(self, 6) + } + #[doc = "Bit 7 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] + #[inline(always)] + #[must_use] + pub fn spi_mem_dout7_mode(&mut self) -> SPI_MEM_DOUT7_MODE_W { + SPI_MEM_DOUT7_MODE_W::new(self, 7) + } + #[doc = "Bit 8 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"] + #[inline(always)] + #[must_use] + pub fn spi_mem_douts_mode(&mut self) -> SPI_MEM_DOUTS_MODE_W { + SPI_MEM_DOUTS_MODE_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI flash output timing adjustment control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_dout_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_dout_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_DOUT_MODE_SPEC; +impl crate::RegisterSpec for SPI_MEM_DOUT_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_dout_mode::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_DOUT_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_dout_mode::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_DOUT_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_DOUT_MODE to value 0"] +impl crate::Resettable for SPI_MEM_DOUT_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_dpa_ctrl.rs b/esp32p4/src/spi0/spi_mem_dpa_ctrl.rs new file mode 100644 index 0000000000..d3e62f73ce --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_dpa_ctrl.rs @@ -0,0 +1,108 @@ +#[doc = "Register `SPI_MEM_DPA_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_DPA_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_CRYPT_SECURITY_LEVEL` reader - Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)"] +pub type SPI_CRYPT_SECURITY_LEVEL_R = crate::FieldReader; +#[doc = "Field `SPI_CRYPT_SECURITY_LEVEL` writer - Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)"] +pub type SPI_CRYPT_SECURITY_LEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_CRYPT_CALC_D_DPA_EN` reader - Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1."] +pub type SPI_CRYPT_CALC_D_DPA_EN_R = crate::BitReader; +#[doc = "Field `SPI_CRYPT_CALC_D_DPA_EN` writer - Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1."] +pub type SPI_CRYPT_CALC_D_DPA_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CRYPT_DPA_SELECT_REGISTER` reader - 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits."] +pub type SPI_CRYPT_DPA_SELECT_REGISTER_R = crate::BitReader; +#[doc = "Field `SPI_CRYPT_DPA_SELECT_REGISTER` writer - 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits."] +pub type SPI_CRYPT_DPA_SELECT_REGISTER_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)"] + #[inline(always)] + pub fn spi_crypt_security_level(&self) -> SPI_CRYPT_SECURITY_LEVEL_R { + SPI_CRYPT_SECURITY_LEVEL_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1."] + #[inline(always)] + pub fn spi_crypt_calc_d_dpa_en(&self) -> SPI_CRYPT_CALC_D_DPA_EN_R { + SPI_CRYPT_CALC_D_DPA_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits."] + #[inline(always)] + pub fn spi_crypt_dpa_select_register(&self) -> SPI_CRYPT_DPA_SELECT_REGISTER_R { + SPI_CRYPT_DPA_SELECT_REGISTER_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_DPA_CTRL") + .field( + "spi_crypt_security_level", + &format_args!("{}", self.spi_crypt_security_level().bits()), + ) + .field( + "spi_crypt_calc_d_dpa_en", + &format_args!("{}", self.spi_crypt_calc_d_dpa_en().bit()), + ) + .field( + "spi_crypt_dpa_select_register", + &format_args!("{}", self.spi_crypt_dpa_select_register().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)"] + #[inline(always)] + #[must_use] + pub fn spi_crypt_security_level( + &mut self, + ) -> SPI_CRYPT_SECURITY_LEVEL_W { + SPI_CRYPT_SECURITY_LEVEL_W::new(self, 0) + } + #[doc = "Bit 3 - Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1."] + #[inline(always)] + #[must_use] + pub fn spi_crypt_calc_d_dpa_en(&mut self) -> SPI_CRYPT_CALC_D_DPA_EN_W { + SPI_CRYPT_CALC_D_DPA_EN_W::new(self, 3) + } + #[doc = "Bit 4 - 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits."] + #[inline(always)] + #[must_use] + pub fn spi_crypt_dpa_select_register( + &mut self, + ) -> SPI_CRYPT_DPA_SELECT_REGISTER_W { + SPI_CRYPT_DPA_SELECT_REGISTER_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI memory cryption DPA register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_dpa_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_dpa_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_DPA_CTRL_SPEC; +impl crate::RegisterSpec for SPI_MEM_DPA_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_dpa_ctrl::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_DPA_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_dpa_ctrl::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_DPA_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_DPA_CTRL to value 0x0f"] +impl crate::Resettable for SPI_MEM_DPA_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/esp32p4/src/spi0/spi_mem_ecc_ctrl.rs b/esp32p4/src/spi0/spi_mem_ecc_ctrl.rs new file mode 100644 index 0000000000..a8d895e2c4 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_ecc_ctrl.rs @@ -0,0 +1,187 @@ +#[doc = "Register `SPI_MEM_ECC_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_ECC_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_ECC_ERR_CNT` reader - This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set."] +pub type SPI_MEM_ECC_ERR_CNT_R = crate::FieldReader; +#[doc = "Field `SPI_FMEM_ECC_ERR_INT_NUM` reader - Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt."] +pub type SPI_FMEM_ECC_ERR_INT_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_FMEM_ECC_ERR_INT_NUM` writer - Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt."] +pub type SPI_FMEM_ECC_ERR_INT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_FMEM_ECC_ERR_INT_EN` reader - Set this bit to calculate the error times of MSPI ECC read when accesses to flash."] +pub type SPI_FMEM_ECC_ERR_INT_EN_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_ECC_ERR_INT_EN` writer - Set this bit to calculate the error times of MSPI ECC read when accesses to flash."] +pub type SPI_FMEM_ECC_ERR_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_PAGE_SIZE` reader - Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."] +pub type SPI_FMEM_PAGE_SIZE_R = crate::FieldReader; +#[doc = "Field `SPI_FMEM_PAGE_SIZE` writer - Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."] +pub type SPI_FMEM_PAGE_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_FMEM_ECC_ADDR_EN` reader - Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1."] +pub type SPI_FMEM_ECC_ADDR_EN_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_ECC_ADDR_EN` writer - Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1."] +pub type SPI_FMEM_ECC_ADDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_ECC_ADDR_EN` reader - Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer."] +pub type SPI_MEM_USR_ECC_ADDR_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_ECC_ADDR_EN` writer - Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer."] +pub type SPI_MEM_USR_ECC_ADDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN` reader - 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information."] +pub type SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN` writer - 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information."] +pub type SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_ECC_ERR_BITS` reader - Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)"] +pub type SPI_MEM_ECC_ERR_BITS_R = crate::FieldReader; +impl R { + #[doc = "Bits 5:10 - This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set."] + #[inline(always)] + pub fn spi_mem_ecc_err_cnt(&self) -> SPI_MEM_ECC_ERR_CNT_R { + SPI_MEM_ECC_ERR_CNT_R::new(((self.bits >> 5) & 0x3f) as u8) + } + #[doc = "Bits 11:16 - Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_fmem_ecc_err_int_num(&self) -> SPI_FMEM_ECC_ERR_INT_NUM_R { + SPI_FMEM_ECC_ERR_INT_NUM_R::new(((self.bits >> 11) & 0x3f) as u8) + } + #[doc = "Bit 17 - Set this bit to calculate the error times of MSPI ECC read when accesses to flash."] + #[inline(always)] + pub fn spi_fmem_ecc_err_int_en(&self) -> SPI_FMEM_ECC_ERR_INT_EN_R { + SPI_FMEM_ECC_ERR_INT_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."] + #[inline(always)] + pub fn spi_fmem_page_size(&self) -> SPI_FMEM_PAGE_SIZE_R { + SPI_FMEM_PAGE_SIZE_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 20 - Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1."] + #[inline(always)] + pub fn spi_fmem_ecc_addr_en(&self) -> SPI_FMEM_ECC_ADDR_EN_R { + SPI_FMEM_ECC_ADDR_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer."] + #[inline(always)] + pub fn spi_mem_usr_ecc_addr_en(&self) -> SPI_MEM_USR_ECC_ADDR_EN_R { + SPI_MEM_USR_ECC_ADDR_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 24 - 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information."] + #[inline(always)] + pub fn spi_mem_ecc_continue_record_err_en(&self) -> SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_R { + SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:31 - Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)"] + #[inline(always)] + pub fn spi_mem_ecc_err_bits(&self) -> SPI_MEM_ECC_ERR_BITS_R { + SPI_MEM_ECC_ERR_BITS_R::new(((self.bits >> 25) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_ECC_CTRL") + .field( + "spi_mem_ecc_err_cnt", + &format_args!("{}", self.spi_mem_ecc_err_cnt().bits()), + ) + .field( + "spi_fmem_ecc_err_int_num", + &format_args!("{}", self.spi_fmem_ecc_err_int_num().bits()), + ) + .field( + "spi_fmem_ecc_err_int_en", + &format_args!("{}", self.spi_fmem_ecc_err_int_en().bit()), + ) + .field( + "spi_fmem_page_size", + &format_args!("{}", self.spi_fmem_page_size().bits()), + ) + .field( + "spi_fmem_ecc_addr_en", + &format_args!("{}", self.spi_fmem_ecc_addr_en().bit()), + ) + .field( + "spi_mem_usr_ecc_addr_en", + &format_args!("{}", self.spi_mem_usr_ecc_addr_en().bit()), + ) + .field( + "spi_mem_ecc_continue_record_err_en", + &format_args!("{}", self.spi_mem_ecc_continue_record_err_en().bit()), + ) + .field( + "spi_mem_ecc_err_bits", + &format_args!("{}", self.spi_mem_ecc_err_bits().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 11:16 - Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ecc_err_int_num( + &mut self, + ) -> SPI_FMEM_ECC_ERR_INT_NUM_W { + SPI_FMEM_ECC_ERR_INT_NUM_W::new(self, 11) + } + #[doc = "Bit 17 - Set this bit to calculate the error times of MSPI ECC read when accesses to flash."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ecc_err_int_en(&mut self) -> SPI_FMEM_ECC_ERR_INT_EN_W { + SPI_FMEM_ECC_ERR_INT_EN_W::new(self, 17) + } + #[doc = "Bits 18:19 - Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_page_size(&mut self) -> SPI_FMEM_PAGE_SIZE_W { + SPI_FMEM_PAGE_SIZE_W::new(self, 18) + } + #[doc = "Bit 20 - Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ecc_addr_en(&mut self) -> SPI_FMEM_ECC_ADDR_EN_W { + SPI_FMEM_ECC_ADDR_EN_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_ecc_addr_en(&mut self) -> SPI_MEM_USR_ECC_ADDR_EN_W { + SPI_MEM_USR_ECC_ADDR_EN_W::new(self, 21) + } + #[doc = "Bit 24 - 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ecc_continue_record_err_en( + &mut self, + ) -> SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_W { + SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI ECC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ecc_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ecc_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_ECC_CTRL_SPEC; +impl crate::RegisterSpec for SPI_MEM_ECC_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_ecc_ctrl::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_ECC_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_ecc_ctrl::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_ECC_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_ECC_CTRL to value 0x0100_5000"] +impl crate::Resettable for SPI_MEM_ECC_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0100_5000; +} diff --git a/esp32p4/src/spi0/spi_mem_ecc_err_addr.rs b/esp32p4/src/spi0/spi_mem_ecc_err_addr.rs new file mode 100644 index 0000000000..3f4b176923 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_ecc_err_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SPI_MEM_ECC_ERR_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `SPI_MEM_ECC_ERR_ADDR` reader - This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set."] +pub type SPI_MEM_ECC_ERR_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:26 - This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set."] + #[inline(always)] + pub fn spi_mem_ecc_err_addr(&self) -> SPI_MEM_ECC_ERR_ADDR_R { + SPI_MEM_ECC_ERR_ADDR_R::new(self.bits & 0x07ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_ECC_ERR_ADDR") + .field( + "spi_mem_ecc_err_addr", + &format_args!("{}", self.spi_mem_ecc_err_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "MSPI ECC error address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ecc_err_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_ECC_ERR_ADDR_SPEC; +impl crate::RegisterSpec for SPI_MEM_ECC_ERR_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_ecc_err_addr::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_ECC_ERR_ADDR_SPEC {} +#[doc = "`reset()` method sets SPI_MEM_ECC_ERR_ADDR to value 0"] +impl crate::Resettable for SPI_MEM_ECC_ERR_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_fsm.rs b/esp32p4/src/spi0/spi_mem_fsm.rs new file mode 100644 index 0000000000..645da7f7b1 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_fsm.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_FSM` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_FSM` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_LOCK_DELAY_TIME` reader - The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1."] +pub type SPI_MEM_LOCK_DELAY_TIME_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_LOCK_DELAY_TIME` writer - The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1."] +pub type SPI_MEM_LOCK_DELAY_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 7:11 - The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1."] + #[inline(always)] + pub fn spi_mem_lock_delay_time(&self) -> SPI_MEM_LOCK_DELAY_TIME_R { + SPI_MEM_LOCK_DELAY_TIME_R::new(((self.bits >> 7) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_FSM") + .field( + "spi_mem_lock_delay_time", + &format_args!("{}", self.spi_mem_lock_delay_time().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 7:11 - The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1."] + #[inline(always)] + #[must_use] + pub fn spi_mem_lock_delay_time(&mut self) -> SPI_MEM_LOCK_DELAY_TIME_W { + SPI_MEM_LOCK_DELAY_TIME_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 FSM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_fsm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_fsm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_FSM_SPEC; +impl crate::RegisterSpec for SPI_MEM_FSM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_fsm::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_FSM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_fsm::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_FSM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_FSM to value 0x0200"] +impl crate::Resettable for SPI_MEM_FSM_SPEC { + const RESET_VALUE: Self::Ux = 0x0200; +} diff --git a/esp32p4/src/spi0/spi_mem_int_clr.rs b/esp32p4/src/spi0/spi_mem_int_clr.rs new file mode 100644 index 0000000000..6cbe3aa5a8 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_int_clr.rs @@ -0,0 +1,142 @@ +#[doc = "Register `SPI_MEM_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_CLR` writer - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt."] +pub type SPI_MEM_SLV_ST_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_CLR` writer - The clear bit for SPI_MEM_MST_ST_END_INT interrupt."] +pub type SPI_MEM_MST_ST_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_ECC_ERR_INT_CLR` writer - The clear bit for SPI_MEM_ECC_ERR_INT interrupt."] +pub type SPI_MEM_ECC_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_PMS_REJECT_INT_CLR` writer - The clear bit for SPI_MEM_PMS_REJECT_INT interrupt."] +pub type SPI_MEM_PMS_REJECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AXI_RADDR_ERR_INT_CLR` writer - The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt."] +pub type SPI_MEM_AXI_RADDR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR` writer - The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt."] +pub type SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AXI_WADDR_ERR_INT_CLR` writer - The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt."] +pub type SPI_MEM_AXI_WADDR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DQS0_AFIFO_OVF_INT_CLR` writer - The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt."] +pub type SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DQS1_AFIFO_OVF_INT_CLR` writer - The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt."] +pub type SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_BUS_FIFO1_UDF_INT_CLR` writer - The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt."] +pub type SPI_MEM_BUS_FIFO1_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_BUS_FIFO0_UDF_INT_CLR` writer - The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt."] +pub type SPI_MEM_BUS_FIFO0_UDF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 3 - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_slv_st_end_int_clr( + &mut self, + ) -> SPI_MEM_SLV_ST_END_INT_CLR_W { + SPI_MEM_SLV_ST_END_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - The clear bit for SPI_MEM_MST_ST_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_mst_st_end_int_clr( + &mut self, + ) -> SPI_MEM_MST_ST_END_INT_CLR_W { + SPI_MEM_MST_ST_END_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - The clear bit for SPI_MEM_ECC_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ecc_err_int_clr(&mut self) -> SPI_MEM_ECC_ERR_INT_CLR_W { + SPI_MEM_ECC_ERR_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - The clear bit for SPI_MEM_PMS_REJECT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_pms_reject_int_clr( + &mut self, + ) -> SPI_MEM_PMS_REJECT_INT_CLR_W { + SPI_MEM_PMS_REJECT_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_axi_raddr_err_int_clr( + &mut self, + ) -> SPI_MEM_AXI_RADDR_ERR_INT_CLR_W { + SPI_MEM_AXI_RADDR_ERR_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_axi_wr_flash_err_int_clr( + &mut self, + ) -> SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_W { + SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_axi_waddr_err_int_clr( + &mut self, + ) -> SPI_MEM_AXI_WADDR_ERR_INT_CLR_W { + SPI_MEM_AXI_WADDR_ERR_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 28 - The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_dqs0_afifo_ovf_int_clr( + &mut self, + ) -> SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_W { + SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_W::new(self, 28) + } + #[doc = "Bit 29 - The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_dqs1_afifo_ovf_int_clr( + &mut self, + ) -> SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_W { + SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_W::new(self, 29) + } + #[doc = "Bit 30 - The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_bus_fifo1_udf_int_clr( + &mut self, + ) -> SPI_MEM_BUS_FIFO1_UDF_INT_CLR_W { + SPI_MEM_BUS_FIFO1_UDF_INT_CLR_W::new(self, 30) + } + #[doc = "Bit 31 - The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_bus_fifo0_udf_int_clr( + &mut self, + ) -> SPI_MEM_BUS_FIFO0_UDF_INT_CLR_W { + SPI_MEM_BUS_FIFO0_UDF_INT_CLR_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_INT_CLR_SPEC; +impl crate::RegisterSpec for SPI_MEM_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`spi_mem_int_clr::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_INT_CLR to value 0"] +impl crate::Resettable for SPI_MEM_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_int_ena.rs b/esp32p4/src/spi0/spi_mem_int_ena.rs new file mode 100644 index 0000000000..e6340481d5 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_int_ena.rs @@ -0,0 +1,276 @@ +#[doc = "Register `SPI_MEM_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_ENA` reader - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."] +pub type SPI_MEM_SLV_ST_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_ENA` writer - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."] +pub type SPI_MEM_SLV_ST_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_ENA` reader - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."] +pub type SPI_MEM_MST_ST_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_ENA` writer - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."] +pub type SPI_MEM_MST_ST_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_ECC_ERR_INT_ENA` reader - The enable bit for SPI_MEM_ECC_ERR_INT interrupt."] +pub type SPI_MEM_ECC_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_ECC_ERR_INT_ENA` writer - The enable bit for SPI_MEM_ECC_ERR_INT interrupt."] +pub type SPI_MEM_ECC_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_PMS_REJECT_INT_ENA` reader - The enable bit for SPI_MEM_PMS_REJECT_INT interrupt."] +pub type SPI_MEM_PMS_REJECT_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PMS_REJECT_INT_ENA` writer - The enable bit for SPI_MEM_PMS_REJECT_INT interrupt."] +pub type SPI_MEM_PMS_REJECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AXI_RADDR_ERR_INT_ENA` reader - The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt."] +pub type SPI_MEM_AXI_RADDR_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AXI_RADDR_ERR_INT_ENA` writer - The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt."] +pub type SPI_MEM_AXI_RADDR_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA` reader - The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt."] +pub type SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA` writer - The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt."] +pub type SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AXI_WADDR_ERR_INT__ENA` reader - The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt."] +pub type SPI_MEM_AXI_WADDR_ERR_INT__ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AXI_WADDR_ERR_INT__ENA` writer - The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt."] +pub type SPI_MEM_AXI_WADDR_ERR_INT__ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DQS0_AFIFO_OVF_INT_ENA` reader - The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt."] +pub type SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DQS0_AFIFO_OVF_INT_ENA` writer - The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt."] +pub type SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DQS1_AFIFO_OVF_INT_ENA` reader - The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt."] +pub type SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DQS1_AFIFO_OVF_INT_ENA` writer - The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt."] +pub type SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_BUS_FIFO1_UDF_INT_ENA` reader - The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt."] +pub type SPI_MEM_BUS_FIFO1_UDF_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_BUS_FIFO1_UDF_INT_ENA` writer - The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt."] +pub type SPI_MEM_BUS_FIFO1_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_BUS_FIFO0_UDF_INT_ENA` reader - The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt."] +pub type SPI_MEM_BUS_FIFO0_UDF_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_BUS_FIFO0_UDF_INT_ENA` writer - The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt."] +pub type SPI_MEM_BUS_FIFO0_UDF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_slv_st_end_int_ena(&self) -> SPI_MEM_SLV_ST_END_INT_ENA_R { + SPI_MEM_SLV_ST_END_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_mst_st_end_int_ena(&self) -> SPI_MEM_MST_ST_END_INT_ENA_R { + SPI_MEM_MST_ST_END_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The enable bit for SPI_MEM_ECC_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mem_ecc_err_int_ena(&self) -> SPI_MEM_ECC_ERR_INT_ENA_R { + SPI_MEM_ECC_ERR_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The enable bit for SPI_MEM_PMS_REJECT_INT interrupt."] + #[inline(always)] + pub fn spi_mem_pms_reject_int_ena(&self) -> SPI_MEM_PMS_REJECT_INT_ENA_R { + SPI_MEM_PMS_REJECT_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mem_axi_raddr_err_int_ena(&self) -> SPI_MEM_AXI_RADDR_ERR_INT_ENA_R { + SPI_MEM_AXI_RADDR_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mem_axi_wr_flash_err_int_ena(&self) -> SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_R { + SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mem_axi_waddr_err_int__ena(&self) -> SPI_MEM_AXI_WADDR_ERR_INT__ENA_R { + SPI_MEM_AXI_WADDR_ERR_INT__ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 28 - The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn spi_mem_dqs0_afifo_ovf_int_ena(&self) -> SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_R { + SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn spi_mem_dqs1_afifo_ovf_int_ena(&self) -> SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_R { + SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt."] + #[inline(always)] + pub fn spi_mem_bus_fifo1_udf_int_ena(&self) -> SPI_MEM_BUS_FIFO1_UDF_INT_ENA_R { + SPI_MEM_BUS_FIFO1_UDF_INT_ENA_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt."] + #[inline(always)] + pub fn spi_mem_bus_fifo0_udf_int_ena(&self) -> SPI_MEM_BUS_FIFO0_UDF_INT_ENA_R { + SPI_MEM_BUS_FIFO0_UDF_INT_ENA_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_INT_ENA") + .field( + "spi_mem_slv_st_end_int_ena", + &format_args!("{}", self.spi_mem_slv_st_end_int_ena().bit()), + ) + .field( + "spi_mem_mst_st_end_int_ena", + &format_args!("{}", self.spi_mem_mst_st_end_int_ena().bit()), + ) + .field( + "spi_mem_ecc_err_int_ena", + &format_args!("{}", self.spi_mem_ecc_err_int_ena().bit()), + ) + .field( + "spi_mem_pms_reject_int_ena", + &format_args!("{}", self.spi_mem_pms_reject_int_ena().bit()), + ) + .field( + "spi_mem_axi_raddr_err_int_ena", + &format_args!("{}", self.spi_mem_axi_raddr_err_int_ena().bit()), + ) + .field( + "spi_mem_axi_wr_flash_err_int_ena", + &format_args!("{}", self.spi_mem_axi_wr_flash_err_int_ena().bit()), + ) + .field( + "spi_mem_axi_waddr_err_int__ena", + &format_args!("{}", self.spi_mem_axi_waddr_err_int__ena().bit()), + ) + .field( + "spi_mem_dqs0_afifo_ovf_int_ena", + &format_args!("{}", self.spi_mem_dqs0_afifo_ovf_int_ena().bit()), + ) + .field( + "spi_mem_dqs1_afifo_ovf_int_ena", + &format_args!("{}", self.spi_mem_dqs1_afifo_ovf_int_ena().bit()), + ) + .field( + "spi_mem_bus_fifo1_udf_int_ena", + &format_args!("{}", self.spi_mem_bus_fifo1_udf_int_ena().bit()), + ) + .field( + "spi_mem_bus_fifo0_udf_int_ena", + &format_args!("{}", self.spi_mem_bus_fifo0_udf_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_slv_st_end_int_ena( + &mut self, + ) -> SPI_MEM_SLV_ST_END_INT_ENA_W { + SPI_MEM_SLV_ST_END_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_mst_st_end_int_ena( + &mut self, + ) -> SPI_MEM_MST_ST_END_INT_ENA_W { + SPI_MEM_MST_ST_END_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The enable bit for SPI_MEM_ECC_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ecc_err_int_ena(&mut self) -> SPI_MEM_ECC_ERR_INT_ENA_W { + SPI_MEM_ECC_ERR_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The enable bit for SPI_MEM_PMS_REJECT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_pms_reject_int_ena( + &mut self, + ) -> SPI_MEM_PMS_REJECT_INT_ENA_W { + SPI_MEM_PMS_REJECT_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_axi_raddr_err_int_ena( + &mut self, + ) -> SPI_MEM_AXI_RADDR_ERR_INT_ENA_W { + SPI_MEM_AXI_RADDR_ERR_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_axi_wr_flash_err_int_ena( + &mut self, + ) -> SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_W { + SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_axi_waddr_err_int__ena( + &mut self, + ) -> SPI_MEM_AXI_WADDR_ERR_INT__ENA_W { + SPI_MEM_AXI_WADDR_ERR_INT__ENA_W::new(self, 9) + } + #[doc = "Bit 28 - The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_dqs0_afifo_ovf_int_ena( + &mut self, + ) -> SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_W { + SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_W::new(self, 28) + } + #[doc = "Bit 29 - The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_dqs1_afifo_ovf_int_ena( + &mut self, + ) -> SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_W { + SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_W::new(self, 29) + } + #[doc = "Bit 30 - The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_bus_fifo1_udf_int_ena( + &mut self, + ) -> SPI_MEM_BUS_FIFO1_UDF_INT_ENA_W { + SPI_MEM_BUS_FIFO1_UDF_INT_ENA_W::new(self, 30) + } + #[doc = "Bit 31 - The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_bus_fifo0_udf_int_ena( + &mut self, + ) -> SPI_MEM_BUS_FIFO0_UDF_INT_ENA_W { + SPI_MEM_BUS_FIFO0_UDF_INT_ENA_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_INT_ENA_SPEC; +impl crate::RegisterSpec for SPI_MEM_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_int_ena::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_int_ena::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_INT_ENA to value 0"] +impl crate::Resettable for SPI_MEM_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_int_raw.rs b/esp32p4/src/spi0/spi_mem_int_raw.rs new file mode 100644 index 0000000000..13b2482789 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_int_raw.rs @@ -0,0 +1,276 @@ +#[doc = "Register `SPI_MEM_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_RAW` reader - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"] +pub type SPI_MEM_SLV_ST_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_RAW` writer - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"] +pub type SPI_MEM_SLV_ST_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_RAW` reader - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."] +pub type SPI_MEM_MST_ST_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_RAW` writer - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."] +pub type SPI_MEM_MST_ST_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_ECC_ERR_INT_RAW` reader - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered."] +pub type SPI_MEM_ECC_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_ECC_ERR_INT_RAW` writer - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered."] +pub type SPI_MEM_ECC_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_PMS_REJECT_INT_RAW` reader - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."] +pub type SPI_MEM_PMS_REJECT_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PMS_REJECT_INT_RAW` writer - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."] +pub type SPI_MEM_PMS_REJECT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AXI_RADDR_ERR_INT_RAW` reader - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."] +pub type SPI_MEM_AXI_RADDR_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AXI_RADDR_ERR_INT_RAW` writer - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."] +pub type SPI_MEM_AXI_RADDR_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW` reader - The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others."] +pub type SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW` writer - The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others."] +pub type SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AXI_WADDR_ERR_INT_RAW` reader - The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others."] +pub type SPI_MEM_AXI_WADDR_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AXI_WADDR_ERR_INT_RAW` writer - The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others."] +pub type SPI_MEM_AXI_WADDR_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DQS0_AFIFO_OVF_INT_RAW` reader - The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow."] +pub type SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DQS0_AFIFO_OVF_INT_RAW` writer - The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow."] +pub type SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_DQS1_AFIFO_OVF_INT_RAW` reader - The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow."] +pub type SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DQS1_AFIFO_OVF_INT_RAW` writer - The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow."] +pub type SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_BUS_FIFO1_UDF_INT_RAW` reader - The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow."] +pub type SPI_MEM_BUS_FIFO1_UDF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_BUS_FIFO1_UDF_INT_RAW` writer - The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow."] +pub type SPI_MEM_BUS_FIFO1_UDF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_BUS_FIFO0_UDF_INT_RAW` reader - The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow."] +pub type SPI_MEM_BUS_FIFO0_UDF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_BUS_FIFO0_UDF_INT_RAW` writer - The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow."] +pub type SPI_MEM_BUS_FIFO0_UDF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"] + #[inline(always)] + pub fn spi_mem_slv_st_end_int_raw(&self) -> SPI_MEM_SLV_ST_END_INT_RAW_R { + SPI_MEM_SLV_ST_END_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."] + #[inline(always)] + pub fn spi_mem_mst_st_end_int_raw(&self) -> SPI_MEM_MST_ST_END_INT_RAW_R { + SPI_MEM_MST_ST_END_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered."] + #[inline(always)] + pub fn spi_mem_ecc_err_int_raw(&self) -> SPI_MEM_ECC_ERR_INT_RAW_R { + SPI_MEM_ECC_ERR_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."] + #[inline(always)] + pub fn spi_mem_pms_reject_int_raw(&self) -> SPI_MEM_PMS_REJECT_INT_RAW_R { + SPI_MEM_PMS_REJECT_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."] + #[inline(always)] + pub fn spi_mem_axi_raddr_err_int_raw(&self) -> SPI_MEM_AXI_RADDR_ERR_INT_RAW_R { + SPI_MEM_AXI_RADDR_ERR_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others."] + #[inline(always)] + pub fn spi_mem_axi_wr_flash_err_int_raw(&self) -> SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_R { + SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others."] + #[inline(always)] + pub fn spi_mem_axi_waddr_err_int_raw(&self) -> SPI_MEM_AXI_WADDR_ERR_INT_RAW_R { + SPI_MEM_AXI_WADDR_ERR_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 28 - The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow."] + #[inline(always)] + pub fn spi_mem_dqs0_afifo_ovf_int_raw(&self) -> SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_R { + SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow."] + #[inline(always)] + pub fn spi_mem_dqs1_afifo_ovf_int_raw(&self) -> SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_R { + SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow."] + #[inline(always)] + pub fn spi_mem_bus_fifo1_udf_int_raw(&self) -> SPI_MEM_BUS_FIFO1_UDF_INT_RAW_R { + SPI_MEM_BUS_FIFO1_UDF_INT_RAW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow."] + #[inline(always)] + pub fn spi_mem_bus_fifo0_udf_int_raw(&self) -> SPI_MEM_BUS_FIFO0_UDF_INT_RAW_R { + SPI_MEM_BUS_FIFO0_UDF_INT_RAW_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_INT_RAW") + .field( + "spi_mem_slv_st_end_int_raw", + &format_args!("{}", self.spi_mem_slv_st_end_int_raw().bit()), + ) + .field( + "spi_mem_mst_st_end_int_raw", + &format_args!("{}", self.spi_mem_mst_st_end_int_raw().bit()), + ) + .field( + "spi_mem_ecc_err_int_raw", + &format_args!("{}", self.spi_mem_ecc_err_int_raw().bit()), + ) + .field( + "spi_mem_pms_reject_int_raw", + &format_args!("{}", self.spi_mem_pms_reject_int_raw().bit()), + ) + .field( + "spi_mem_axi_raddr_err_int_raw", + &format_args!("{}", self.spi_mem_axi_raddr_err_int_raw().bit()), + ) + .field( + "spi_mem_axi_wr_flash_err_int_raw", + &format_args!("{}", self.spi_mem_axi_wr_flash_err_int_raw().bit()), + ) + .field( + "spi_mem_axi_waddr_err_int_raw", + &format_args!("{}", self.spi_mem_axi_waddr_err_int_raw().bit()), + ) + .field( + "spi_mem_dqs0_afifo_ovf_int_raw", + &format_args!("{}", self.spi_mem_dqs0_afifo_ovf_int_raw().bit()), + ) + .field( + "spi_mem_dqs1_afifo_ovf_int_raw", + &format_args!("{}", self.spi_mem_dqs1_afifo_ovf_int_raw().bit()), + ) + .field( + "spi_mem_bus_fifo1_udf_int_raw", + &format_args!("{}", self.spi_mem_bus_fifo1_udf_int_raw().bit()), + ) + .field( + "spi_mem_bus_fifo0_udf_int_raw", + &format_args!("{}", self.spi_mem_bus_fifo0_udf_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"] + #[inline(always)] + #[must_use] + pub fn spi_mem_slv_st_end_int_raw( + &mut self, + ) -> SPI_MEM_SLV_ST_END_INT_RAW_W { + SPI_MEM_SLV_ST_END_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_mst_st_end_int_raw( + &mut self, + ) -> SPI_MEM_MST_ST_END_INT_RAW_W { + SPI_MEM_MST_ST_END_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ecc_err_int_raw(&mut self) -> SPI_MEM_ECC_ERR_INT_RAW_W { + SPI_MEM_ECC_ERR_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_pms_reject_int_raw( + &mut self, + ) -> SPI_MEM_PMS_REJECT_INT_RAW_W { + SPI_MEM_PMS_REJECT_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_axi_raddr_err_int_raw( + &mut self, + ) -> SPI_MEM_AXI_RADDR_ERR_INT_RAW_W { + SPI_MEM_AXI_RADDR_ERR_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_axi_wr_flash_err_int_raw( + &mut self, + ) -> SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_W { + SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_axi_waddr_err_int_raw( + &mut self, + ) -> SPI_MEM_AXI_WADDR_ERR_INT_RAW_W { + SPI_MEM_AXI_WADDR_ERR_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 28 - The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow."] + #[inline(always)] + #[must_use] + pub fn spi_mem_dqs0_afifo_ovf_int_raw( + &mut self, + ) -> SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_W { + SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_W::new(self, 28) + } + #[doc = "Bit 29 - The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow."] + #[inline(always)] + #[must_use] + pub fn spi_mem_dqs1_afifo_ovf_int_raw( + &mut self, + ) -> SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_W { + SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_W::new(self, 29) + } + #[doc = "Bit 30 - The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow."] + #[inline(always)] + #[must_use] + pub fn spi_mem_bus_fifo1_udf_int_raw( + &mut self, + ) -> SPI_MEM_BUS_FIFO1_UDF_INT_RAW_W { + SPI_MEM_BUS_FIFO1_UDF_INT_RAW_W::new(self, 30) + } + #[doc = "Bit 31 - The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow."] + #[inline(always)] + #[must_use] + pub fn spi_mem_bus_fifo0_udf_int_raw( + &mut self, + ) -> SPI_MEM_BUS_FIFO0_UDF_INT_RAW_W { + SPI_MEM_BUS_FIFO0_UDF_INT_RAW_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_INT_RAW_SPEC; +impl crate::RegisterSpec for SPI_MEM_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_int_raw::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_int_raw::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_INT_RAW to value 0"] +impl crate::Resettable for SPI_MEM_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_int_st.rs b/esp32p4/src/spi0/spi_mem_int_st.rs new file mode 100644 index 0000000000..b1e503e508 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_int_st.rs @@ -0,0 +1,149 @@ +#[doc = "Register `SPI_MEM_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_ST` reader - The status bit for SPI_MEM_SLV_ST_END_INT interrupt."] +pub type SPI_MEM_SLV_ST_END_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_ST` reader - The status bit for SPI_MEM_MST_ST_END_INT interrupt."] +pub type SPI_MEM_MST_ST_END_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_ECC_ERR_INT_ST` reader - The status bit for SPI_MEM_ECC_ERR_INT interrupt."] +pub type SPI_MEM_ECC_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PMS_REJECT_INT_ST` reader - The status bit for SPI_MEM_PMS_REJECT_INT interrupt."] +pub type SPI_MEM_PMS_REJECT_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AXI_RADDR_ERR_INT_ST` reader - The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt."] +pub type SPI_MEM_AXI_RADDR_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AXI_WR_FLASH_ERR_INT_ST` reader - The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt."] +pub type SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_AXI_WADDR_ERR_INT_ST` reader - The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt."] +pub type SPI_MEM_AXI_WADDR_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DQS0_AFIFO_OVF_INT_ST` reader - The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt."] +pub type SPI_MEM_DQS0_AFIFO_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DQS1_AFIFO_OVF_INT_ST` reader - The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt."] +pub type SPI_MEM_DQS1_AFIFO_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_BUS_FIFO1_UDF_INT_ST` reader - The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt."] +pub type SPI_MEM_BUS_FIFO1_UDF_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_BUS_FIFO0_UDF_INT_ST` reader - The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt."] +pub type SPI_MEM_BUS_FIFO0_UDF_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 3 - The status bit for SPI_MEM_SLV_ST_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_slv_st_end_int_st(&self) -> SPI_MEM_SLV_ST_END_INT_ST_R { + SPI_MEM_SLV_ST_END_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The status bit for SPI_MEM_MST_ST_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_mst_st_end_int_st(&self) -> SPI_MEM_MST_ST_END_INT_ST_R { + SPI_MEM_MST_ST_END_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The status bit for SPI_MEM_ECC_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mem_ecc_err_int_st(&self) -> SPI_MEM_ECC_ERR_INT_ST_R { + SPI_MEM_ECC_ERR_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The status bit for SPI_MEM_PMS_REJECT_INT interrupt."] + #[inline(always)] + pub fn spi_mem_pms_reject_int_st(&self) -> SPI_MEM_PMS_REJECT_INT_ST_R { + SPI_MEM_PMS_REJECT_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mem_axi_raddr_err_int_st(&self) -> SPI_MEM_AXI_RADDR_ERR_INT_ST_R { + SPI_MEM_AXI_RADDR_ERR_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mem_axi_wr_flash_err_int_st(&self) -> SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_R { + SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mem_axi_waddr_err_int_st(&self) -> SPI_MEM_AXI_WADDR_ERR_INT_ST_R { + SPI_MEM_AXI_WADDR_ERR_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 28 - The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn spi_mem_dqs0_afifo_ovf_int_st(&self) -> SPI_MEM_DQS0_AFIFO_OVF_INT_ST_R { + SPI_MEM_DQS0_AFIFO_OVF_INT_ST_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt."] + #[inline(always)] + pub fn spi_mem_dqs1_afifo_ovf_int_st(&self) -> SPI_MEM_DQS1_AFIFO_OVF_INT_ST_R { + SPI_MEM_DQS1_AFIFO_OVF_INT_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt."] + #[inline(always)] + pub fn spi_mem_bus_fifo1_udf_int_st(&self) -> SPI_MEM_BUS_FIFO1_UDF_INT_ST_R { + SPI_MEM_BUS_FIFO1_UDF_INT_ST_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt."] + #[inline(always)] + pub fn spi_mem_bus_fifo0_udf_int_st(&self) -> SPI_MEM_BUS_FIFO0_UDF_INT_ST_R { + SPI_MEM_BUS_FIFO0_UDF_INT_ST_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_INT_ST") + .field( + "spi_mem_slv_st_end_int_st", + &format_args!("{}", self.spi_mem_slv_st_end_int_st().bit()), + ) + .field( + "spi_mem_mst_st_end_int_st", + &format_args!("{}", self.spi_mem_mst_st_end_int_st().bit()), + ) + .field( + "spi_mem_ecc_err_int_st", + &format_args!("{}", self.spi_mem_ecc_err_int_st().bit()), + ) + .field( + "spi_mem_pms_reject_int_st", + &format_args!("{}", self.spi_mem_pms_reject_int_st().bit()), + ) + .field( + "spi_mem_axi_raddr_err_int_st", + &format_args!("{}", self.spi_mem_axi_raddr_err_int_st().bit()), + ) + .field( + "spi_mem_axi_wr_flash_err_int_st", + &format_args!("{}", self.spi_mem_axi_wr_flash_err_int_st().bit()), + ) + .field( + "spi_mem_axi_waddr_err_int_st", + &format_args!("{}", self.spi_mem_axi_waddr_err_int_st().bit()), + ) + .field( + "spi_mem_dqs0_afifo_ovf_int_st", + &format_args!("{}", self.spi_mem_dqs0_afifo_ovf_int_st().bit()), + ) + .field( + "spi_mem_dqs1_afifo_ovf_int_st", + &format_args!("{}", self.spi_mem_dqs1_afifo_ovf_int_st().bit()), + ) + .field( + "spi_mem_bus_fifo1_udf_int_st", + &format_args!("{}", self.spi_mem_bus_fifo1_udf_int_st().bit()), + ) + .field( + "spi_mem_bus_fifo0_udf_int_st", + &format_args!("{}", self.spi_mem_bus_fifo0_udf_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "SPI0 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_INT_ST_SPEC; +impl crate::RegisterSpec for SPI_MEM_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_int_st::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_INT_ST_SPEC {} +#[doc = "`reset()` method sets SPI_MEM_INT_ST to value 0"] +impl crate::Resettable for SPI_MEM_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_misc.rs b/esp32p4/src/spi0/spi_mem_misc.rs new file mode 100644 index 0000000000..152c46b319 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_misc.rs @@ -0,0 +1,123 @@ +#[doc = "Register `SPI_MEM_MISC` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_MISC` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_FSUB_PIN` reader - For SPI0, flash is connected to SUBPINs."] +pub type SPI_MEM_FSUB_PIN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FSUB_PIN` writer - For SPI0, flash is connected to SUBPINs."] +pub type SPI_MEM_FSUB_PIN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SSUB_PIN` reader - For SPI0, sram is connected to SUBPINs."] +pub type SPI_MEM_SSUB_PIN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SSUB_PIN` writer - For SPI0, sram is connected to SUBPINs."] +pub type SPI_MEM_SSUB_PIN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_CK_IDLE_EDGE` reader - 1: SPI_CLK line is high when idle 0: spi clk line is low when idle"] +pub type SPI_MEM_CK_IDLE_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CK_IDLE_EDGE` writer - 1: SPI_CLK line is high when idle 0: spi clk line is low when idle"] +pub type SPI_MEM_CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_CS_KEEP_ACTIVE` reader - SPI_CS line keep low when the bit is set."] +pub type SPI_MEM_CS_KEEP_ACTIVE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CS_KEEP_ACTIVE` writer - SPI_CS line keep low when the bit is set."] +pub type SPI_MEM_CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 7 - For SPI0, flash is connected to SUBPINs."] + #[inline(always)] + pub fn spi_mem_fsub_pin(&self) -> SPI_MEM_FSUB_PIN_R { + SPI_MEM_FSUB_PIN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - For SPI0, sram is connected to SUBPINs."] + #[inline(always)] + pub fn spi_mem_ssub_pin(&self) -> SPI_MEM_SSUB_PIN_R { + SPI_MEM_SSUB_PIN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: SPI_CLK line is high when idle 0: spi clk line is low when idle"] + #[inline(always)] + pub fn spi_mem_ck_idle_edge(&self) -> SPI_MEM_CK_IDLE_EDGE_R { + SPI_MEM_CK_IDLE_EDGE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SPI_CS line keep low when the bit is set."] + #[inline(always)] + pub fn spi_mem_cs_keep_active(&self) -> SPI_MEM_CS_KEEP_ACTIVE_R { + SPI_MEM_CS_KEEP_ACTIVE_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_MISC") + .field( + "spi_mem_fsub_pin", + &format_args!("{}", self.spi_mem_fsub_pin().bit()), + ) + .field( + "spi_mem_ssub_pin", + &format_args!("{}", self.spi_mem_ssub_pin().bit()), + ) + .field( + "spi_mem_ck_idle_edge", + &format_args!("{}", self.spi_mem_ck_idle_edge().bit()), + ) + .field( + "spi_mem_cs_keep_active", + &format_args!("{}", self.spi_mem_cs_keep_active().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 7 - For SPI0, flash is connected to SUBPINs."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fsub_pin(&mut self) -> SPI_MEM_FSUB_PIN_W { + SPI_MEM_FSUB_PIN_W::new(self, 7) + } + #[doc = "Bit 8 - For SPI0, sram is connected to SUBPINs."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ssub_pin(&mut self) -> SPI_MEM_SSUB_PIN_W { + SPI_MEM_SSUB_PIN_W::new(self, 8) + } + #[doc = "Bit 9 - 1: SPI_CLK line is high when idle 0: spi clk line is low when idle"] + #[inline(always)] + #[must_use] + pub fn spi_mem_ck_idle_edge(&mut self) -> SPI_MEM_CK_IDLE_EDGE_W { + SPI_MEM_CK_IDLE_EDGE_W::new(self, 9) + } + #[doc = "Bit 10 - SPI_CS line keep low when the bit is set."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cs_keep_active(&mut self) -> SPI_MEM_CS_KEEP_ACTIVE_W { + SPI_MEM_CS_KEEP_ACTIVE_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 misc register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_misc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_misc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_MISC_SPEC; +impl crate::RegisterSpec for SPI_MEM_MISC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_misc::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_MISC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_misc::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_MISC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_MISC to value 0"] +impl crate::Resettable for SPI_MEM_MISC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_mmu_item_content.rs b/esp32p4/src/spi0/spi_mem_mmu_item_content.rs new file mode 100644 index 0000000000..942200e609 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_mmu_item_content.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SPI_MEM_MMU_ITEM_CONTENT` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_MMU_ITEM_CONTENT` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MMU_ITEM_CONTENT` reader - MSPI-MMU item content"] +pub type SPI_MMU_ITEM_CONTENT_R = crate::FieldReader; +#[doc = "Field `SPI_MMU_ITEM_CONTENT` writer - MSPI-MMU item content"] +pub type SPI_MMU_ITEM_CONTENT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - MSPI-MMU item content"] + #[inline(always)] + pub fn spi_mmu_item_content(&self) -> SPI_MMU_ITEM_CONTENT_R { + SPI_MMU_ITEM_CONTENT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_MMU_ITEM_CONTENT") + .field( + "spi_mmu_item_content", + &format_args!("{}", self.spi_mmu_item_content().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - MSPI-MMU item content"] + #[inline(always)] + #[must_use] + pub fn spi_mmu_item_content( + &mut self, + ) -> SPI_MMU_ITEM_CONTENT_W { + SPI_MMU_ITEM_CONTENT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI-MMU item content register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_mmu_item_content::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_mmu_item_content::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_MMU_ITEM_CONTENT_SPEC; +impl crate::RegisterSpec for SPI_MEM_MMU_ITEM_CONTENT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_mmu_item_content::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_MMU_ITEM_CONTENT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_mmu_item_content::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_MMU_ITEM_CONTENT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_MMU_ITEM_CONTENT to value 0x037c"] +impl crate::Resettable for SPI_MEM_MMU_ITEM_CONTENT_SPEC { + const RESET_VALUE: Self::Ux = 0x037c; +} diff --git a/esp32p4/src/spi0/spi_mem_mmu_item_index.rs b/esp32p4/src/spi0/spi_mem_mmu_item_index.rs new file mode 100644 index 0000000000..9051c3203e --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_mmu_item_index.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_MMU_ITEM_INDEX` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_MMU_ITEM_INDEX` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MMU_ITEM_INDEX` reader - MSPI-MMU item index"] +pub type SPI_MMU_ITEM_INDEX_R = crate::FieldReader; +#[doc = "Field `SPI_MMU_ITEM_INDEX` writer - MSPI-MMU item index"] +pub type SPI_MMU_ITEM_INDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - MSPI-MMU item index"] + #[inline(always)] + pub fn spi_mmu_item_index(&self) -> SPI_MMU_ITEM_INDEX_R { + SPI_MMU_ITEM_INDEX_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_MMU_ITEM_INDEX") + .field( + "spi_mmu_item_index", + &format_args!("{}", self.spi_mmu_item_index().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - MSPI-MMU item index"] + #[inline(always)] + #[must_use] + pub fn spi_mmu_item_index(&mut self) -> SPI_MMU_ITEM_INDEX_W { + SPI_MMU_ITEM_INDEX_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI-MMU item index register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_mmu_item_index::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_mmu_item_index::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_MMU_ITEM_INDEX_SPEC; +impl crate::RegisterSpec for SPI_MEM_MMU_ITEM_INDEX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_mmu_item_index::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_MMU_ITEM_INDEX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_mmu_item_index::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_MMU_ITEM_INDEX_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_MMU_ITEM_INDEX to value 0"] +impl crate::Resettable for SPI_MEM_MMU_ITEM_INDEX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_mmu_power_ctrl.rs b/esp32p4/src/spi0/spi_mem_mmu_power_ctrl.rs new file mode 100644 index 0000000000..d84af6713e --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_mmu_power_ctrl.rs @@ -0,0 +1,153 @@ +#[doc = "Register `SPI_MEM_MMU_POWER_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_MMU_POWER_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MMU_MEM_FORCE_ON` reader - Set this bit to enable mmu-memory clock force on"] +pub type SPI_MMU_MEM_FORCE_ON_R = crate::BitReader; +#[doc = "Field `SPI_MMU_MEM_FORCE_ON` writer - Set this bit to enable mmu-memory clock force on"] +pub type SPI_MMU_MEM_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MMU_MEM_FORCE_PD` reader - Set this bit to force mmu-memory powerdown"] +pub type SPI_MMU_MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `SPI_MMU_MEM_FORCE_PD` writer - Set this bit to force mmu-memory powerdown"] +pub type SPI_MMU_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MMU_MEM_FORCE_PU` reader - Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc."] +pub type SPI_MMU_MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `SPI_MMU_MEM_FORCE_PU` writer - Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc."] +pub type SPI_MMU_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_AUX_CTRL` reader - MMU PSRAM aux control register"] +pub type SPI_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_AUX_CTRL` writer - MMU PSRAM aux control register"] +pub type SPI_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `SPI_MEM_RDN_ENA` reader - ECO register enable bit"] +pub type SPI_MEM_RDN_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_RDN_ENA` writer - ECO register enable bit"] +pub type SPI_MEM_RDN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_RDN_RESULT` reader - MSPI module clock domain and AXI clock domain ECO register result register"] +pub type SPI_MEM_RDN_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Set this bit to enable mmu-memory clock force on"] + #[inline(always)] + pub fn spi_mmu_mem_force_on(&self) -> SPI_MMU_MEM_FORCE_ON_R { + SPI_MMU_MEM_FORCE_ON_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to force mmu-memory powerdown"] + #[inline(always)] + pub fn spi_mmu_mem_force_pd(&self) -> SPI_MMU_MEM_FORCE_PD_R { + SPI_MMU_MEM_FORCE_PD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc."] + #[inline(always)] + pub fn spi_mmu_mem_force_pu(&self) -> SPI_MMU_MEM_FORCE_PU_R { + SPI_MMU_MEM_FORCE_PU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 16:29 - MMU PSRAM aux control register"] + #[inline(always)] + pub fn spi_mem_aux_ctrl(&self) -> SPI_MEM_AUX_CTRL_R { + SPI_MEM_AUX_CTRL_R::new(((self.bits >> 16) & 0x3fff) as u16) + } + #[doc = "Bit 30 - ECO register enable bit"] + #[inline(always)] + pub fn spi_mem_rdn_ena(&self) -> SPI_MEM_RDN_ENA_R { + SPI_MEM_RDN_ENA_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - MSPI module clock domain and AXI clock domain ECO register result register"] + #[inline(always)] + pub fn spi_mem_rdn_result(&self) -> SPI_MEM_RDN_RESULT_R { + SPI_MEM_RDN_RESULT_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_MMU_POWER_CTRL") + .field( + "spi_mmu_mem_force_on", + &format_args!("{}", self.spi_mmu_mem_force_on().bit()), + ) + .field( + "spi_mmu_mem_force_pd", + &format_args!("{}", self.spi_mmu_mem_force_pd().bit()), + ) + .field( + "spi_mmu_mem_force_pu", + &format_args!("{}", self.spi_mmu_mem_force_pu().bit()), + ) + .field( + "spi_mem_aux_ctrl", + &format_args!("{}", self.spi_mem_aux_ctrl().bits()), + ) + .field( + "spi_mem_rdn_ena", + &format_args!("{}", self.spi_mem_rdn_ena().bit()), + ) + .field( + "spi_mem_rdn_result", + &format_args!("{}", self.spi_mem_rdn_result().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable mmu-memory clock force on"] + #[inline(always)] + #[must_use] + pub fn spi_mmu_mem_force_on(&mut self) -> SPI_MMU_MEM_FORCE_ON_W { + SPI_MMU_MEM_FORCE_ON_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to force mmu-memory powerdown"] + #[inline(always)] + #[must_use] + pub fn spi_mmu_mem_force_pd(&mut self) -> SPI_MMU_MEM_FORCE_PD_W { + SPI_MMU_MEM_FORCE_PD_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc."] + #[inline(always)] + #[must_use] + pub fn spi_mmu_mem_force_pu(&mut self) -> SPI_MMU_MEM_FORCE_PU_W { + SPI_MMU_MEM_FORCE_PU_W::new(self, 2) + } + #[doc = "Bits 16:29 - MMU PSRAM aux control register"] + #[inline(always)] + #[must_use] + pub fn spi_mem_aux_ctrl(&mut self) -> SPI_MEM_AUX_CTRL_W { + SPI_MEM_AUX_CTRL_W::new(self, 16) + } + #[doc = "Bit 30 - ECO register enable bit"] + #[inline(always)] + #[must_use] + pub fn spi_mem_rdn_ena(&mut self) -> SPI_MEM_RDN_ENA_W { + SPI_MEM_RDN_ENA_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI MMU power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_mmu_power_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_mmu_power_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_MMU_POWER_CTRL_SPEC; +impl crate::RegisterSpec for SPI_MEM_MMU_POWER_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_mmu_power_ctrl::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_MMU_POWER_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_mmu_power_ctrl::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_MMU_POWER_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_MMU_POWER_CTRL to value 0x1320_0004"] +impl crate::Resettable for SPI_MEM_MMU_POWER_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x1320_0004; +} diff --git a/esp32p4/src/spi0/spi_mem_pms_reject.rs b/esp32p4/src/spi0/spi_mem_pms_reject.rs new file mode 100644 index 0000000000..f8d5c4b625 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_pms_reject.rs @@ -0,0 +1,121 @@ +#[doc = "Register `SPI_MEM_PMS_REJECT` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_PMS_REJECT` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_REJECT_ADDR` reader - This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set."] +pub type SPI_MEM_REJECT_ADDR_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_PM_EN` reader - Set this bit to enable SPI0/1 transfer permission control function."] +pub type SPI_MEM_PM_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PM_EN` writer - Set this bit to enable SPI0/1 transfer permission control function."] +pub type SPI_MEM_PM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_PMS_LD` reader - 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set."] +pub type SPI_MEM_PMS_LD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PMS_ST` reader - 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set."] +pub type SPI_MEM_PMS_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PMS_MULTI_HIT` reader - 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set."] +pub type SPI_MEM_PMS_MULTI_HIT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PMS_IVD` reader - 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set."] +pub type SPI_MEM_PMS_IVD_R = crate::BitReader; +impl R { + #[doc = "Bits 0:26 - This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set."] + #[inline(always)] + pub fn spi_mem_reject_addr(&self) -> SPI_MEM_REJECT_ADDR_R { + SPI_MEM_REJECT_ADDR_R::new(self.bits & 0x07ff_ffff) + } + #[doc = "Bit 27 - Set this bit to enable SPI0/1 transfer permission control function."] + #[inline(always)] + pub fn spi_mem_pm_en(&self) -> SPI_MEM_PM_EN_R { + SPI_MEM_PM_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set."] + #[inline(always)] + pub fn spi_mem_pms_ld(&self) -> SPI_MEM_PMS_LD_R { + SPI_MEM_PMS_LD_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set."] + #[inline(always)] + pub fn spi_mem_pms_st(&self) -> SPI_MEM_PMS_ST_R { + SPI_MEM_PMS_ST_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set."] + #[inline(always)] + pub fn spi_mem_pms_multi_hit(&self) -> SPI_MEM_PMS_MULTI_HIT_R { + SPI_MEM_PMS_MULTI_HIT_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set."] + #[inline(always)] + pub fn spi_mem_pms_ivd(&self) -> SPI_MEM_PMS_IVD_R { + SPI_MEM_PMS_IVD_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_PMS_REJECT") + .field( + "spi_mem_reject_addr", + &format_args!("{}", self.spi_mem_reject_addr().bits()), + ) + .field( + "spi_mem_pm_en", + &format_args!("{}", self.spi_mem_pm_en().bit()), + ) + .field( + "spi_mem_pms_ld", + &format_args!("{}", self.spi_mem_pms_ld().bit()), + ) + .field( + "spi_mem_pms_st", + &format_args!("{}", self.spi_mem_pms_st().bit()), + ) + .field( + "spi_mem_pms_multi_hit", + &format_args!("{}", self.spi_mem_pms_multi_hit().bit()), + ) + .field( + "spi_mem_pms_ivd", + &format_args!("{}", self.spi_mem_pms_ivd().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 27 - Set this bit to enable SPI0/1 transfer permission control function."] + #[inline(always)] + #[must_use] + pub fn spi_mem_pm_en(&mut self) -> SPI_MEM_PM_EN_W { + SPI_MEM_PM_EN_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 access reject register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_pms_reject::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_pms_reject::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_PMS_REJECT_SPEC; +impl crate::RegisterSpec for SPI_MEM_PMS_REJECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_pms_reject::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_PMS_REJECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_pms_reject::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_PMS_REJECT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_PMS_REJECT to value 0"] +impl crate::Resettable for SPI_MEM_PMS_REJECT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_rd_status.rs b/esp32p4/src/spi0/spi_mem_rd_status.rs new file mode 100644 index 0000000000..5c549a2c71 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_rd_status.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_RD_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_RD_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_WB_MODE` reader - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."] +pub type SPI_MEM_WB_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_WB_MODE` writer - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."] +pub type SPI_MEM_WB_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."] + #[inline(always)] + pub fn spi_mem_wb_mode(&self) -> SPI_MEM_WB_MODE_R { + SPI_MEM_WB_MODE_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_RD_STATUS") + .field( + "spi_mem_wb_mode", + &format_args!("{}", self.spi_mem_wb_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wb_mode(&mut self) -> SPI_MEM_WB_MODE_W { + SPI_MEM_WB_MODE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 read control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_rd_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_rd_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_RD_STATUS_SPEC; +impl crate::RegisterSpec for SPI_MEM_RD_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_rd_status::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_RD_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_rd_status::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_RD_STATUS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_RD_STATUS to value 0"] +impl crate::Resettable for SPI_MEM_RD_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_registerrnd_eco_high.rs b/esp32p4/src/spi0/spi_mem_registerrnd_eco_high.rs new file mode 100644 index 0000000000..7cf2b9cecd --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_registerrnd_eco_high.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SPI_MEM_REGISTERRND_ECO_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_REGISTERRND_ECO_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_REGISTERRND_ECO_HIGH` reader - ECO high register"] +pub type SPI_MEM_REGISTERRND_ECO_HIGH_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_REGISTERRND_ECO_HIGH` writer - ECO high register"] +pub type SPI_MEM_REGISTERRND_ECO_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - ECO high register"] + #[inline(always)] + pub fn spi_mem_registerrnd_eco_high(&self) -> SPI_MEM_REGISTERRND_ECO_HIGH_R { + SPI_MEM_REGISTERRND_ECO_HIGH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_REGISTERRND_ECO_HIGH") + .field( + "spi_mem_registerrnd_eco_high", + &format_args!("{}", self.spi_mem_registerrnd_eco_high().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - ECO high register"] + #[inline(always)] + #[must_use] + pub fn spi_mem_registerrnd_eco_high( + &mut self, + ) -> SPI_MEM_REGISTERRND_ECO_HIGH_W { + SPI_MEM_REGISTERRND_ECO_HIGH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI ECO high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_registerrnd_eco_high::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_registerrnd_eco_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_REGISTERRND_ECO_HIGH_SPEC; +impl crate::RegisterSpec for SPI_MEM_REGISTERRND_ECO_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_registerrnd_eco_high::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_REGISTERRND_ECO_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_registerrnd_eco_high::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_REGISTERRND_ECO_HIGH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_REGISTERRND_ECO_HIGH to value 0x037c"] +impl crate::Resettable for SPI_MEM_REGISTERRND_ECO_HIGH_SPEC { + const RESET_VALUE: Self::Ux = 0x037c; +} diff --git a/esp32p4/src/spi0/spi_mem_registerrnd_eco_low.rs b/esp32p4/src/spi0/spi_mem_registerrnd_eco_low.rs new file mode 100644 index 0000000000..5ea48d8931 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_registerrnd_eco_low.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SPI_MEM_REGISTERRND_ECO_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_REGISTERRND_ECO_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_REGISTERRND_ECO_LOW` reader - ECO low register"] +pub type SPI_MEM_REGISTERRND_ECO_LOW_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_REGISTERRND_ECO_LOW` writer - ECO low register"] +pub type SPI_MEM_REGISTERRND_ECO_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - ECO low register"] + #[inline(always)] + pub fn spi_mem_registerrnd_eco_low(&self) -> SPI_MEM_REGISTERRND_ECO_LOW_R { + SPI_MEM_REGISTERRND_ECO_LOW_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_REGISTERRND_ECO_LOW") + .field( + "spi_mem_registerrnd_eco_low", + &format_args!("{}", self.spi_mem_registerrnd_eco_low().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - ECO low register"] + #[inline(always)] + #[must_use] + pub fn spi_mem_registerrnd_eco_low( + &mut self, + ) -> SPI_MEM_REGISTERRND_ECO_LOW_W { + SPI_MEM_REGISTERRND_ECO_LOW_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI ECO low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_registerrnd_eco_low::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_registerrnd_eco_low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_REGISTERRND_ECO_LOW_SPEC; +impl crate::RegisterSpec for SPI_MEM_REGISTERRND_ECO_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_registerrnd_eco_low::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_REGISTERRND_ECO_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_registerrnd_eco_low::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_REGISTERRND_ECO_LOW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_REGISTERRND_ECO_LOW to value 0x037c"] +impl crate::Resettable for SPI_MEM_REGISTERRND_ECO_LOW_SPEC { + const RESET_VALUE: Self::Ux = 0x037c; +} diff --git a/esp32p4/src/spi0/spi_mem_sram_clk.rs b/esp32p4/src/spi0/spi_mem_sram_clk.rs new file mode 100644 index 0000000000..a5d548d861 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_sram_clk.rs @@ -0,0 +1,123 @@ +#[doc = "Register `SPI_MEM_SRAM_CLK` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_SRAM_CLK` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_SCLKCNT_L` reader - For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N."] +pub type SPI_MEM_SCLKCNT_L_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_SCLKCNT_L` writer - For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N."] +pub type SPI_MEM_SCLKCNT_L_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MEM_SCLKCNT_H` reader - For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)."] +pub type SPI_MEM_SCLKCNT_H_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_SCLKCNT_H` writer - For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)."] +pub type SPI_MEM_SCLKCNT_H_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MEM_SCLKCNT_N` reader - For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] +pub type SPI_MEM_SCLKCNT_N_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_SCLKCNT_N` writer - For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] +pub type SPI_MEM_SCLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MEM_SCLK_EQU_SYSCLK` reader - For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock."] +pub type SPI_MEM_SCLK_EQU_SYSCLK_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SCLK_EQU_SYSCLK` writer - For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock."] +pub type SPI_MEM_SCLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N."] + #[inline(always)] + pub fn spi_mem_sclkcnt_l(&self) -> SPI_MEM_SCLKCNT_L_R { + SPI_MEM_SCLKCNT_L_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)."] + #[inline(always)] + pub fn spi_mem_sclkcnt_h(&self) -> SPI_MEM_SCLKCNT_H_R { + SPI_MEM_SCLKCNT_H_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] + #[inline(always)] + pub fn spi_mem_sclkcnt_n(&self) -> SPI_MEM_SCLKCNT_N_R { + SPI_MEM_SCLKCNT_N_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 31 - For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock."] + #[inline(always)] + pub fn spi_mem_sclk_equ_sysclk(&self) -> SPI_MEM_SCLK_EQU_SYSCLK_R { + SPI_MEM_SCLK_EQU_SYSCLK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_SRAM_CLK") + .field( + "spi_mem_sclkcnt_l", + &format_args!("{}", self.spi_mem_sclkcnt_l().bits()), + ) + .field( + "spi_mem_sclkcnt_h", + &format_args!("{}", self.spi_mem_sclkcnt_h().bits()), + ) + .field( + "spi_mem_sclkcnt_n", + &format_args!("{}", self.spi_mem_sclkcnt_n().bits()), + ) + .field( + "spi_mem_sclk_equ_sysclk", + &format_args!("{}", self.spi_mem_sclk_equ_sysclk().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sclkcnt_l(&mut self) -> SPI_MEM_SCLKCNT_L_W { + SPI_MEM_SCLKCNT_L_W::new(self, 0) + } + #[doc = "Bits 8:15 - For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sclkcnt_h(&mut self) -> SPI_MEM_SCLKCNT_H_W { + SPI_MEM_SCLKCNT_H_W::new(self, 8) + } + #[doc = "Bits 16:23 - For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] + #[inline(always)] + #[must_use] + pub fn spi_mem_sclkcnt_n(&mut self) -> SPI_MEM_SCLKCNT_N_W { + SPI_MEM_SCLKCNT_N_W::new(self, 16) + } + #[doc = "Bit 31 - For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sclk_equ_sysclk(&mut self) -> SPI_MEM_SCLK_EQU_SYSCLK_W { + SPI_MEM_SCLK_EQU_SYSCLK_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 external RAM clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_sram_clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_sram_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_SRAM_CLK_SPEC; +impl crate::RegisterSpec for SPI_MEM_SRAM_CLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_sram_clk::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_SRAM_CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_sram_clk::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_SRAM_CLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_SRAM_CLK to value 0x0003_0103"] +impl crate::Resettable for SPI_MEM_SRAM_CLK_SPEC { + const RESET_VALUE: Self::Ux = 0x0003_0103; +} diff --git a/esp32p4/src/spi0/spi_mem_sram_cmd.rs b/esp32p4/src/spi0/spi_mem_sram_cmd.rs new file mode 100644 index 0000000000..d3907af79b --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_sram_cmd.rs @@ -0,0 +1,454 @@ +#[doc = "Register `SPI_MEM_SRAM_CMD` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_SRAM_CMD` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_SCLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on."] +pub type SPI_MEM_SCLK_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_SCLK_MODE` writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on."] +pub type SPI_MEM_SCLK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_MEM_SWB_MODE` reader - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit."] +pub type SPI_MEM_SWB_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_SWB_MODE` writer - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit."] +pub type SPI_MEM_SWB_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MEM_SDIN_DUAL` reader - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] +pub type SPI_MEM_SDIN_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SDIN_DUAL` writer - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] +pub type SPI_MEM_SDIN_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SDOUT_DUAL` reader - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] +pub type SPI_MEM_SDOUT_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SDOUT_DUAL` writer - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] +pub type SPI_MEM_SDOUT_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SADDR_DUAL` reader - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] +pub type SPI_MEM_SADDR_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SADDR_DUAL` writer - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] +pub type SPI_MEM_SADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SDIN_QUAD` reader - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] +pub type SPI_MEM_SDIN_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SDIN_QUAD` writer - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] +pub type SPI_MEM_SDIN_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SDOUT_QUAD` reader - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] +pub type SPI_MEM_SDOUT_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SDOUT_QUAD` writer - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] +pub type SPI_MEM_SDOUT_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SADDR_QUAD` reader - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] +pub type SPI_MEM_SADDR_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SADDR_QUAD` writer - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] +pub type SPI_MEM_SADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SCMD_QUAD` reader - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] +pub type SPI_MEM_SCMD_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SCMD_QUAD` writer - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] +pub type SPI_MEM_SCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SDIN_OCT` reader - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable."] +pub type SPI_MEM_SDIN_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SDIN_OCT` writer - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable."] +pub type SPI_MEM_SDIN_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SDOUT_OCT` reader - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable."] +pub type SPI_MEM_SDOUT_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SDOUT_OCT` writer - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable."] +pub type SPI_MEM_SDOUT_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SADDR_OCT` reader - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable."] +pub type SPI_MEM_SADDR_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SADDR_OCT` writer - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable."] +pub type SPI_MEM_SADDR_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SCMD_OCT` reader - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable."] +pub type SPI_MEM_SCMD_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SCMD_OCT` writer - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable."] +pub type SPI_MEM_SCMD_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SDUMMY_RIN` reader - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."] +pub type SPI_MEM_SDUMMY_RIN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SDUMMY_RIN` writer - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."] +pub type SPI_MEM_SDUMMY_RIN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SDUMMY_WOUT` reader - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."] +pub type SPI_MEM_SDUMMY_WOUT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SDUMMY_WOUT` writer - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."] +pub type SPI_MEM_SDUMMY_WOUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT` reader - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller."] +pub type SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT` writer - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller."] +pub type SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_WDUMMY_ALWAYS_OUT` reader - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."] +pub type SPI_SMEM_WDUMMY_ALWAYS_OUT_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_WDUMMY_ALWAYS_OUT` writer - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."] +pub type SPI_SMEM_WDUMMY_ALWAYS_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SDIN_HEX` reader - For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable."] +pub type SPI_MEM_SDIN_HEX_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SDIN_HEX` writer - For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable."] +pub type SPI_MEM_SDIN_HEX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SDOUT_HEX` reader - For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable."] +pub type SPI_MEM_SDOUT_HEX_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SDOUT_HEX` writer - For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable."] +pub type SPI_MEM_SDOUT_HEX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DQS_IE_ALWAYS_ON` reader - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."] +pub type SPI_SMEM_DQS_IE_ALWAYS_ON_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DQS_IE_ALWAYS_ON` writer - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."] +pub type SPI_SMEM_DQS_IE_ALWAYS_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DATA_IE_ALWAYS_ON` reader - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."] +pub type SPI_SMEM_DATA_IE_ALWAYS_ON_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DATA_IE_ALWAYS_ON` writer - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."] +pub type SPI_SMEM_DATA_IE_ALWAYS_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on."] + #[inline(always)] + pub fn spi_mem_sclk_mode(&self) -> SPI_MEM_SCLK_MODE_R { + SPI_MEM_SCLK_MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:9 - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit."] + #[inline(always)] + pub fn spi_mem_swb_mode(&self) -> SPI_MEM_SWB_MODE_R { + SPI_MEM_SWB_MODE_R::new(((self.bits >> 2) & 0xff) as u8) + } + #[doc = "Bit 10 - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] + #[inline(always)] + pub fn spi_mem_sdin_dual(&self) -> SPI_MEM_SDIN_DUAL_R { + SPI_MEM_SDIN_DUAL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] + #[inline(always)] + pub fn spi_mem_sdout_dual(&self) -> SPI_MEM_SDOUT_DUAL_R { + SPI_MEM_SDOUT_DUAL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] + #[inline(always)] + pub fn spi_mem_saddr_dual(&self) -> SPI_MEM_SADDR_DUAL_R { + SPI_MEM_SADDR_DUAL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 14 - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] + #[inline(always)] + pub fn spi_mem_sdin_quad(&self) -> SPI_MEM_SDIN_QUAD_R { + SPI_MEM_SDIN_QUAD_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] + #[inline(always)] + pub fn spi_mem_sdout_quad(&self) -> SPI_MEM_SDOUT_QUAD_R { + SPI_MEM_SDOUT_QUAD_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] + #[inline(always)] + pub fn spi_mem_saddr_quad(&self) -> SPI_MEM_SADDR_QUAD_R { + SPI_MEM_SADDR_QUAD_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] + #[inline(always)] + pub fn spi_mem_scmd_quad(&self) -> SPI_MEM_SCMD_QUAD_R { + SPI_MEM_SCMD_QUAD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_sdin_oct(&self) -> SPI_MEM_SDIN_OCT_R { + SPI_MEM_SDIN_OCT_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_sdout_oct(&self) -> SPI_MEM_SDOUT_OCT_R { + SPI_MEM_SDOUT_OCT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_saddr_oct(&self) -> SPI_MEM_SADDR_OCT_R { + SPI_MEM_SADDR_OCT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_scmd_oct(&self) -> SPI_MEM_SCMD_OCT_R { + SPI_MEM_SCMD_OCT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."] + #[inline(always)] + pub fn spi_mem_sdummy_rin(&self) -> SPI_MEM_SDUMMY_RIN_R { + SPI_MEM_SDUMMY_RIN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."] + #[inline(always)] + pub fn spi_mem_sdummy_wout(&self) -> SPI_MEM_SDUMMY_WOUT_R { + SPI_MEM_SDUMMY_WOUT_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller."] + #[inline(always)] + pub fn spi_smem_wdummy_dqs_always_out(&self) -> SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R { + SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."] + #[inline(always)] + pub fn spi_smem_wdummy_always_out(&self) -> SPI_SMEM_WDUMMY_ALWAYS_OUT_R { + SPI_SMEM_WDUMMY_ALWAYS_OUT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_sdin_hex(&self) -> SPI_MEM_SDIN_HEX_R { + SPI_MEM_SDIN_HEX_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_sdout_hex(&self) -> SPI_MEM_SDOUT_HEX_R { + SPI_MEM_SDOUT_HEX_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 30 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."] + #[inline(always)] + pub fn spi_smem_dqs_ie_always_on(&self) -> SPI_SMEM_DQS_IE_ALWAYS_ON_R { + SPI_SMEM_DQS_IE_ALWAYS_ON_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."] + #[inline(always)] + pub fn spi_smem_data_ie_always_on(&self) -> SPI_SMEM_DATA_IE_ALWAYS_ON_R { + SPI_SMEM_DATA_IE_ALWAYS_ON_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_SRAM_CMD") + .field( + "spi_mem_sclk_mode", + &format_args!("{}", self.spi_mem_sclk_mode().bits()), + ) + .field( + "spi_mem_swb_mode", + &format_args!("{}", self.spi_mem_swb_mode().bits()), + ) + .field( + "spi_mem_sdin_dual", + &format_args!("{}", self.spi_mem_sdin_dual().bit()), + ) + .field( + "spi_mem_sdout_dual", + &format_args!("{}", self.spi_mem_sdout_dual().bit()), + ) + .field( + "spi_mem_saddr_dual", + &format_args!("{}", self.spi_mem_saddr_dual().bit()), + ) + .field( + "spi_mem_sdin_quad", + &format_args!("{}", self.spi_mem_sdin_quad().bit()), + ) + .field( + "spi_mem_sdout_quad", + &format_args!("{}", self.spi_mem_sdout_quad().bit()), + ) + .field( + "spi_mem_saddr_quad", + &format_args!("{}", self.spi_mem_saddr_quad().bit()), + ) + .field( + "spi_mem_scmd_quad", + &format_args!("{}", self.spi_mem_scmd_quad().bit()), + ) + .field( + "spi_mem_sdin_oct", + &format_args!("{}", self.spi_mem_sdin_oct().bit()), + ) + .field( + "spi_mem_sdout_oct", + &format_args!("{}", self.spi_mem_sdout_oct().bit()), + ) + .field( + "spi_mem_saddr_oct", + &format_args!("{}", self.spi_mem_saddr_oct().bit()), + ) + .field( + "spi_mem_scmd_oct", + &format_args!("{}", self.spi_mem_scmd_oct().bit()), + ) + .field( + "spi_mem_sdummy_rin", + &format_args!("{}", self.spi_mem_sdummy_rin().bit()), + ) + .field( + "spi_mem_sdummy_wout", + &format_args!("{}", self.spi_mem_sdummy_wout().bit()), + ) + .field( + "spi_smem_wdummy_dqs_always_out", + &format_args!("{}", self.spi_smem_wdummy_dqs_always_out().bit()), + ) + .field( + "spi_smem_wdummy_always_out", + &format_args!("{}", self.spi_smem_wdummy_always_out().bit()), + ) + .field( + "spi_mem_sdin_hex", + &format_args!("{}", self.spi_mem_sdin_hex().bit()), + ) + .field( + "spi_mem_sdout_hex", + &format_args!("{}", self.spi_mem_sdout_hex().bit()), + ) + .field( + "spi_smem_dqs_ie_always_on", + &format_args!("{}", self.spi_smem_dqs_ie_always_on().bit()), + ) + .field( + "spi_smem_data_ie_always_on", + &format_args!("{}", self.spi_smem_data_ie_always_on().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sclk_mode(&mut self) -> SPI_MEM_SCLK_MODE_W { + SPI_MEM_SCLK_MODE_W::new(self, 0) + } + #[doc = "Bits 2:9 - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit."] + #[inline(always)] + #[must_use] + pub fn spi_mem_swb_mode(&mut self) -> SPI_MEM_SWB_MODE_W { + SPI_MEM_SWB_MODE_W::new(self, 2) + } + #[doc = "Bit 10 - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sdin_dual(&mut self) -> SPI_MEM_SDIN_DUAL_W { + SPI_MEM_SDIN_DUAL_W::new(self, 10) + } + #[doc = "Bit 11 - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sdout_dual(&mut self) -> SPI_MEM_SDOUT_DUAL_W { + SPI_MEM_SDOUT_DUAL_W::new(self, 11) + } + #[doc = "Bit 12 - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_saddr_dual(&mut self) -> SPI_MEM_SADDR_DUAL_W { + SPI_MEM_SADDR_DUAL_W::new(self, 12) + } + #[doc = "Bit 14 - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sdin_quad(&mut self) -> SPI_MEM_SDIN_QUAD_W { + SPI_MEM_SDIN_QUAD_W::new(self, 14) + } + #[doc = "Bit 15 - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sdout_quad(&mut self) -> SPI_MEM_SDOUT_QUAD_W { + SPI_MEM_SDOUT_QUAD_W::new(self, 15) + } + #[doc = "Bit 16 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_saddr_quad(&mut self) -> SPI_MEM_SADDR_QUAD_W { + SPI_MEM_SADDR_QUAD_W::new(self, 16) + } + #[doc = "Bit 17 - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_scmd_quad(&mut self) -> SPI_MEM_SCMD_QUAD_W { + SPI_MEM_SCMD_QUAD_W::new(self, 17) + } + #[doc = "Bit 18 - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sdin_oct(&mut self) -> SPI_MEM_SDIN_OCT_W { + SPI_MEM_SDIN_OCT_W::new(self, 18) + } + #[doc = "Bit 19 - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sdout_oct(&mut self) -> SPI_MEM_SDOUT_OCT_W { + SPI_MEM_SDOUT_OCT_W::new(self, 19) + } + #[doc = "Bit 20 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_saddr_oct(&mut self) -> SPI_MEM_SADDR_OCT_W { + SPI_MEM_SADDR_OCT_W::new(self, 20) + } + #[doc = "Bit 21 - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_scmd_oct(&mut self) -> SPI_MEM_SCMD_OCT_W { + SPI_MEM_SCMD_OCT_W::new(self, 21) + } + #[doc = "Bit 22 - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sdummy_rin(&mut self) -> SPI_MEM_SDUMMY_RIN_W { + SPI_MEM_SDUMMY_RIN_W::new(self, 22) + } + #[doc = "Bit 23 - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sdummy_wout(&mut self) -> SPI_MEM_SDUMMY_WOUT_W { + SPI_MEM_SDUMMY_WOUT_W::new(self, 23) + } + #[doc = "Bit 24 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller."] + #[inline(always)] + #[must_use] + pub fn spi_smem_wdummy_dqs_always_out( + &mut self, + ) -> SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_W { + SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_W::new(self, 24) + } + #[doc = "Bit 25 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."] + #[inline(always)] + #[must_use] + pub fn spi_smem_wdummy_always_out( + &mut self, + ) -> SPI_SMEM_WDUMMY_ALWAYS_OUT_W { + SPI_SMEM_WDUMMY_ALWAYS_OUT_W::new(self, 25) + } + #[doc = "Bit 26 - For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sdin_hex(&mut self) -> SPI_MEM_SDIN_HEX_W { + SPI_MEM_SDIN_HEX_W::new(self, 26) + } + #[doc = "Bit 27 - For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sdout_hex(&mut self) -> SPI_MEM_SDOUT_HEX_W { + SPI_MEM_SDOUT_HEX_W::new(self, 27) + } + #[doc = "Bit 30 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_smem_dqs_ie_always_on( + &mut self, + ) -> SPI_SMEM_DQS_IE_ALWAYS_ON_W { + SPI_SMEM_DQS_IE_ALWAYS_ON_W::new(self, 30) + } + #[doc = "Bit 31 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_smem_data_ie_always_on( + &mut self, + ) -> SPI_SMEM_DATA_IE_ALWAYS_ON_W { + SPI_SMEM_DATA_IE_ALWAYS_ON_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 external RAM mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_sram_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_sram_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_SRAM_CMD_SPEC; +impl crate::RegisterSpec for SPI_MEM_SRAM_CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_sram_cmd::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_SRAM_CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_sram_cmd::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_SRAM_CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_SRAM_CMD to value 0x80c0_0000"] +impl crate::Resettable for SPI_MEM_SRAM_CMD_SPEC { + const RESET_VALUE: Self::Ux = 0x80c0_0000; +} diff --git a/esp32p4/src/spi0/spi_mem_sram_drd_cmd.rs b/esp32p4/src/spi0/spi_mem_sram_drd_cmd.rs new file mode 100644 index 0000000000..32b8ec4343 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_sram_drd_cmd.rs @@ -0,0 +1,89 @@ +#[doc = "Register `SPI_MEM_SRAM_DRD_CMD` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_SRAM_DRD_CMD` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE` reader - For SPI0,When cache mode is enable it is the read command value of command phase for sram."] +pub type SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE` writer - For SPI0,When cache mode is enable it is the read command value of command phase for sram."] +pub type SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN` reader - For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1)."] +pub type SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN` writer - For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1)."] +pub type SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - For SPI0,When cache mode is enable it is the read command value of command phase for sram."] + #[inline(always)] + pub fn spi_mem_cache_sram_usr_rd_cmd_value(&self) -> SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_R { + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 28:31 - For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1)."] + #[inline(always)] + pub fn spi_mem_cache_sram_usr_rd_cmd_bitlen(&self) -> SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_R { + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_SRAM_DRD_CMD") + .field( + "spi_mem_cache_sram_usr_rd_cmd_value", + &format_args!("{}", self.spi_mem_cache_sram_usr_rd_cmd_value().bits()), + ) + .field( + "spi_mem_cache_sram_usr_rd_cmd_bitlen", + &format_args!("{}", self.spi_mem_cache_sram_usr_rd_cmd_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - For SPI0,When cache mode is enable it is the read command value of command phase for sram."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cache_sram_usr_rd_cmd_value( + &mut self, + ) -> SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_W { + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_W::new(self, 0) + } + #[doc = "Bits 28:31 - For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cache_sram_usr_rd_cmd_bitlen( + &mut self, + ) -> SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_W { + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 external RAM DDR read command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_sram_drd_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_sram_drd_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_SRAM_DRD_CMD_SPEC; +impl crate::RegisterSpec for SPI_MEM_SRAM_DRD_CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_sram_drd_cmd::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_SRAM_DRD_CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_sram_drd_cmd::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_SRAM_DRD_CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_SRAM_DRD_CMD to value 0"] +impl crate::Resettable for SPI_MEM_SRAM_DRD_CMD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_sram_dwr_cmd.rs b/esp32p4/src/spi0/spi_mem_sram_dwr_cmd.rs new file mode 100644 index 0000000000..eeee5cb1f4 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_sram_dwr_cmd.rs @@ -0,0 +1,89 @@ +#[doc = "Register `SPI_MEM_SRAM_DWR_CMD` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_SRAM_DWR_CMD` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE` reader - For SPI0,When cache mode is enable it is the write command value of command phase for sram."] +pub type SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE` writer - For SPI0,When cache mode is enable it is the write command value of command phase for sram."] +pub type SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN` reader - For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1)."] +pub type SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN` writer - For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1)."] +pub type SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - For SPI0,When cache mode is enable it is the write command value of command phase for sram."] + #[inline(always)] + pub fn spi_mem_cache_sram_usr_wr_cmd_value(&self) -> SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_R { + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 28:31 - For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1)."] + #[inline(always)] + pub fn spi_mem_cache_sram_usr_wr_cmd_bitlen(&self) -> SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_R { + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_SRAM_DWR_CMD") + .field( + "spi_mem_cache_sram_usr_wr_cmd_value", + &format_args!("{}", self.spi_mem_cache_sram_usr_wr_cmd_value().bits()), + ) + .field( + "spi_mem_cache_sram_usr_wr_cmd_bitlen", + &format_args!("{}", self.spi_mem_cache_sram_usr_wr_cmd_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - For SPI0,When cache mode is enable it is the write command value of command phase for sram."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cache_sram_usr_wr_cmd_value( + &mut self, + ) -> SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_W { + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_W::new(self, 0) + } + #[doc = "Bits 28:31 - For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cache_sram_usr_wr_cmd_bitlen( + &mut self, + ) -> SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_W { + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 external RAM DDR write command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_sram_dwr_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_sram_dwr_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_SRAM_DWR_CMD_SPEC; +impl crate::RegisterSpec for SPI_MEM_SRAM_DWR_CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_sram_dwr_cmd::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_SRAM_DWR_CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_sram_dwr_cmd::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_SRAM_DWR_CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_SRAM_DWR_CMD to value 0"] +impl crate::Resettable for SPI_MEM_SRAM_DWR_CMD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_timing_cali.rs b/esp32p4/src/spi0/spi_mem_timing_cali.rs new file mode 100644 index 0000000000..5493ad0e38 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_timing_cali.rs @@ -0,0 +1,135 @@ +#[doc = "Register `SPI_MEM_TIMING_CALI` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_TIMING_CALI` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_TIMING_CLK_ENA` reader - The bit is used to enable timing adjust clock for all reading operations."] +pub type SPI_MEM_TIMING_CLK_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_TIMING_CLK_ENA` writer - The bit is used to enable timing adjust clock for all reading operations."] +pub type SPI_MEM_TIMING_CLK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_TIMING_CALI` reader - The bit is used to enable timing auto-calibration for all reading operations."] +pub type SPI_MEM_TIMING_CALI_R = crate::BitReader; +#[doc = "Field `SPI_MEM_TIMING_CALI` writer - The bit is used to enable timing auto-calibration for all reading operations."] +pub type SPI_MEM_TIMING_CALI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_EXTRA_DUMMY_CYCLELEN` reader - add extra dummy spi clock cycle length for spi clock calibration."] +pub type SPI_MEM_EXTRA_DUMMY_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_EXTRA_DUMMY_CYCLELEN` writer - add extra dummy spi clock cycle length for spi clock calibration."] +pub type SPI_MEM_EXTRA_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_MEM_DLL_TIMING_CALI` reader - Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash."] +pub type SPI_MEM_DLL_TIMING_CALI_R = crate::BitReader; +#[doc = "Field `SPI_MEM_DLL_TIMING_CALI` writer - Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash."] +pub type SPI_MEM_DLL_TIMING_CALI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UPDATE` writer - Set this bit to update delay mode, delay num and extra dummy in MSPI."] +pub type UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."] + #[inline(always)] + pub fn spi_mem_timing_clk_ena(&self) -> SPI_MEM_TIMING_CLK_ENA_R { + SPI_MEM_TIMING_CLK_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."] + #[inline(always)] + pub fn spi_mem_timing_cali(&self) -> SPI_MEM_TIMING_CALI_R { + SPI_MEM_TIMING_CALI_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."] + #[inline(always)] + pub fn spi_mem_extra_dummy_cyclelen(&self) -> SPI_MEM_EXTRA_DUMMY_CYCLELEN_R { + SPI_MEM_EXTRA_DUMMY_CYCLELEN_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bit 5 - Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash."] + #[inline(always)] + pub fn spi_mem_dll_timing_cali(&self) -> SPI_MEM_DLL_TIMING_CALI_R { + SPI_MEM_DLL_TIMING_CALI_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_TIMING_CALI") + .field( + "spi_mem_timing_clk_ena", + &format_args!("{}", self.spi_mem_timing_clk_ena().bit()), + ) + .field( + "spi_mem_timing_cali", + &format_args!("{}", self.spi_mem_timing_cali().bit()), + ) + .field( + "spi_mem_extra_dummy_cyclelen", + &format_args!("{}", self.spi_mem_extra_dummy_cyclelen().bits()), + ) + .field( + "spi_mem_dll_timing_cali", + &format_args!("{}", self.spi_mem_dll_timing_cali().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."] + #[inline(always)] + #[must_use] + pub fn spi_mem_timing_clk_ena(&mut self) -> SPI_MEM_TIMING_CLK_ENA_W { + SPI_MEM_TIMING_CLK_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."] + #[inline(always)] + #[must_use] + pub fn spi_mem_timing_cali(&mut self) -> SPI_MEM_TIMING_CALI_W { + SPI_MEM_TIMING_CALI_W::new(self, 1) + } + #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."] + #[inline(always)] + #[must_use] + pub fn spi_mem_extra_dummy_cyclelen( + &mut self, + ) -> SPI_MEM_EXTRA_DUMMY_CYCLELEN_W { + SPI_MEM_EXTRA_DUMMY_CYCLELEN_W::new(self, 2) + } + #[doc = "Bit 5 - Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash."] + #[inline(always)] + #[must_use] + pub fn spi_mem_dll_timing_cali( + &mut self, + ) -> SPI_MEM_DLL_TIMING_CALI_W { + SPI_MEM_DLL_TIMING_CALI_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to update delay mode, delay num and extra dummy in MSPI."] + #[inline(always)] + #[must_use] + pub fn update(&mut self) -> UPDATE_W { + UPDATE_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 flash timing calibration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_timing_cali::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_timing_cali::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_TIMING_CALI_SPEC; +impl crate::RegisterSpec for SPI_MEM_TIMING_CALI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_timing_cali::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_TIMING_CALI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_timing_cali::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_TIMING_CALI_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_TIMING_CALI to value 0x01"] +impl crate::Resettable for SPI_MEM_TIMING_CALI_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/spi0/spi_mem_user.rs b/esp32p4/src/spi0/spi_mem_user.rs new file mode 100644 index 0000000000..36b96ded68 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_user.rs @@ -0,0 +1,142 @@ +#[doc = "Register `SPI_MEM_USER` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_USER` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CS_HOLD` reader - spi cs keep low when spi is in done phase. 1: enable 0: disable."] +pub type SPI_MEM_CS_HOLD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CS_HOLD` writer - spi cs keep low when spi is in done phase. 1: enable 0: disable."] +pub type SPI_MEM_CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_CS_SETUP` reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] +pub type SPI_MEM_CS_SETUP_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CS_SETUP` writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] +pub type SPI_MEM_CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_CK_OUT_EDGE` reader - The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3."] +pub type SPI_MEM_CK_OUT_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CK_OUT_EDGE` writer - The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3."] +pub type SPI_MEM_CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_DUMMY_IDLE` reader - spi clock is disable in dummy phase when the bit is enable."] +pub type SPI_MEM_USR_DUMMY_IDLE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_DUMMY_IDLE` writer - spi clock is disable in dummy phase when the bit is enable."] +pub type SPI_MEM_USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_DUMMY` reader - This bit enable the dummy phase of an operation."] +pub type SPI_MEM_USR_DUMMY_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_DUMMY` writer - This bit enable the dummy phase of an operation."] +pub type SPI_MEM_USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_cs_hold(&self) -> SPI_MEM_CS_HOLD_R { + SPI_MEM_CS_HOLD_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_cs_setup(&self) -> SPI_MEM_CS_SETUP_R { + SPI_MEM_CS_SETUP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3."] + #[inline(always)] + pub fn spi_mem_ck_out_edge(&self) -> SPI_MEM_CK_OUT_EDGE_R { + SPI_MEM_CK_OUT_EDGE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable."] + #[inline(always)] + pub fn spi_mem_usr_dummy_idle(&self) -> SPI_MEM_USR_DUMMY_IDLE_R { + SPI_MEM_USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 29 - This bit enable the dummy phase of an operation."] + #[inline(always)] + pub fn spi_mem_usr_dummy(&self) -> SPI_MEM_USR_DUMMY_R { + SPI_MEM_USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_USER") + .field( + "spi_mem_cs_hold", + &format_args!("{}", self.spi_mem_cs_hold().bit()), + ) + .field( + "spi_mem_cs_setup", + &format_args!("{}", self.spi_mem_cs_setup().bit()), + ) + .field( + "spi_mem_ck_out_edge", + &format_args!("{}", self.spi_mem_ck_out_edge().bit()), + ) + .field( + "spi_mem_usr_dummy_idle", + &format_args!("{}", self.spi_mem_usr_dummy_idle().bit()), + ) + .field( + "spi_mem_usr_dummy", + &format_args!("{}", self.spi_mem_usr_dummy().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cs_hold(&mut self) -> SPI_MEM_CS_HOLD_W { + SPI_MEM_CS_HOLD_W::new(self, 6) + } + #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cs_setup(&mut self) -> SPI_MEM_CS_SETUP_W { + SPI_MEM_CS_SETUP_W::new(self, 7) + } + #[doc = "Bit 9 - The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ck_out_edge(&mut self) -> SPI_MEM_CK_OUT_EDGE_W { + SPI_MEM_CK_OUT_EDGE_W::new(self, 9) + } + #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_dummy_idle(&mut self) -> SPI_MEM_USR_DUMMY_IDLE_W { + SPI_MEM_USR_DUMMY_IDLE_W::new(self, 26) + } + #[doc = "Bit 29 - This bit enable the dummy phase of an operation."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_dummy(&mut self) -> SPI_MEM_USR_DUMMY_W { + SPI_MEM_USR_DUMMY_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 user register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_USER_SPEC; +impl crate::RegisterSpec for SPI_MEM_USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_user::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_USER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_user::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_USER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_USER to value 0"] +impl crate::Resettable for SPI_MEM_USER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_user1.rs b/esp32p4/src/spi0/spi_mem_user1.rs new file mode 100644 index 0000000000..57f421f7bf --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_user1.rs @@ -0,0 +1,98 @@ +#[doc = "Register `SPI_MEM_USER1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_USER1` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_USR_DUMMY_CYCLELEN` reader - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."] +pub type SPI_MEM_USR_DUMMY_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_DUMMY_CYCLELEN` writer - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."] +pub type SPI_MEM_USR_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_MEM_USR_DBYTELEN` reader - SPI0 USR_CMD read or write data byte length -1"] +pub type SPI_MEM_USR_DBYTELEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_ADDR_BITLEN` reader - The length in bits of address phase. The register value shall be (bit_num-1)."] +pub type SPI_MEM_USR_ADDR_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_ADDR_BITLEN` writer - The length in bits of address phase. The register value shall be (bit_num-1)."] +pub type SPI_MEM_USR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."] + #[inline(always)] + pub fn spi_mem_usr_dummy_cyclelen(&self) -> SPI_MEM_USR_DUMMY_CYCLELEN_R { + SPI_MEM_USR_DUMMY_CYCLELEN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:8 - SPI0 USR_CMD read or write data byte length -1"] + #[inline(always)] + pub fn spi_mem_usr_dbytelen(&self) -> SPI_MEM_USR_DBYTELEN_R { + SPI_MEM_USR_DBYTELEN_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."] + #[inline(always)] + pub fn spi_mem_usr_addr_bitlen(&self) -> SPI_MEM_USR_ADDR_BITLEN_R { + SPI_MEM_USR_ADDR_BITLEN_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_USER1") + .field( + "spi_mem_usr_dummy_cyclelen", + &format_args!("{}", self.spi_mem_usr_dummy_cyclelen().bits()), + ) + .field( + "spi_mem_usr_dbytelen", + &format_args!("{}", self.spi_mem_usr_dbytelen().bits()), + ) + .field( + "spi_mem_usr_addr_bitlen", + &format_args!("{}", self.spi_mem_usr_addr_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_dummy_cyclelen( + &mut self, + ) -> SPI_MEM_USR_DUMMY_CYCLELEN_W { + SPI_MEM_USR_DUMMY_CYCLELEN_W::new(self, 0) + } + #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_addr_bitlen(&mut self) -> SPI_MEM_USR_ADDR_BITLEN_W { + SPI_MEM_USR_ADDR_BITLEN_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 user1 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_USER1_SPEC; +impl crate::RegisterSpec for SPI_MEM_USER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_user1::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_USER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_user1::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_USER1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_USER1 to value 0x5c00_0047"] +impl crate::Resettable for SPI_MEM_USER1_SPEC { + const RESET_VALUE: Self::Ux = 0x5c00_0047; +} diff --git a/esp32p4/src/spi0/spi_mem_user2.rs b/esp32p4/src/spi0/spi_mem_user2.rs new file mode 100644 index 0000000000..4b1887712f --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_user2.rs @@ -0,0 +1,87 @@ +#[doc = "Register `SPI_MEM_USER2` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_USER2` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_USR_COMMAND_VALUE` reader - The value of command."] +pub type SPI_MEM_USR_COMMAND_VALUE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_COMMAND_VALUE` writer - The value of command."] +pub type SPI_MEM_USR_COMMAND_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SPI_MEM_USR_COMMAND_BITLEN` reader - The length in bits of command phase. The register value shall be (bit_num-1)"] +pub type SPI_MEM_USR_COMMAND_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_COMMAND_BITLEN` writer - The length in bits of command phase. The register value shall be (bit_num-1)"] +pub type SPI_MEM_USR_COMMAND_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - The value of command."] + #[inline(always)] + pub fn spi_mem_usr_command_value(&self) -> SPI_MEM_USR_COMMAND_VALUE_R { + SPI_MEM_USR_COMMAND_VALUE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 28:31 - The length in bits of command phase. The register value shall be (bit_num-1)"] + #[inline(always)] + pub fn spi_mem_usr_command_bitlen(&self) -> SPI_MEM_USR_COMMAND_BITLEN_R { + SPI_MEM_USR_COMMAND_BITLEN_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_USER2") + .field( + "spi_mem_usr_command_value", + &format_args!("{}", self.spi_mem_usr_command_value().bits()), + ) + .field( + "spi_mem_usr_command_bitlen", + &format_args!("{}", self.spi_mem_usr_command_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - The value of command."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_command_value(&mut self) -> SPI_MEM_USR_COMMAND_VALUE_W { + SPI_MEM_USR_COMMAND_VALUE_W::new(self, 0) + } + #[doc = "Bits 28:31 - The length in bits of command phase. The register value shall be (bit_num-1)"] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_command_bitlen( + &mut self, + ) -> SPI_MEM_USR_COMMAND_BITLEN_W { + SPI_MEM_USR_COMMAND_BITLEN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 user2 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_USER2_SPEC; +impl crate::RegisterSpec for SPI_MEM_USER2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_user2::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_USER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_user2::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_USER2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_USER2 to value 0x7000_0000"] +impl crate::Resettable for SPI_MEM_USER2_SPEC { + const RESET_VALUE: Self::Ux = 0x7000_0000; +} diff --git a/esp32p4/src/spi0/spi_mem_xts_date.rs b/esp32p4/src/spi0/spi_mem_xts_date.rs new file mode 100644 index 0000000000..a4fb0d91f3 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_xts_date.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_XTS_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_XTS_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_XTS_DATE` reader - This bits stores the last modified-time of manual encryption feature."] +pub type SPI_XTS_DATE_R = crate::FieldReader; +#[doc = "Field `SPI_XTS_DATE` writer - This bits stores the last modified-time of manual encryption feature."] +pub type SPI_XTS_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 0:29 - This bits stores the last modified-time of manual encryption feature."] + #[inline(always)] + pub fn spi_xts_date(&self) -> SPI_XTS_DATE_R { + SPI_XTS_DATE_R::new(self.bits & 0x3fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_XTS_DATE") + .field( + "spi_xts_date", + &format_args!("{}", self.spi_xts_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:29 - This bits stores the last modified-time of manual encryption feature."] + #[inline(always)] + #[must_use] + pub fn spi_xts_date(&mut self) -> SPI_XTS_DATE_W { + SPI_XTS_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Manual Encryption version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_XTS_DATE_SPEC; +impl crate::RegisterSpec for SPI_MEM_XTS_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_xts_date::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_XTS_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_xts_date::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_XTS_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_XTS_DATE to value 0x2020_1010"] +impl crate::Resettable for SPI_MEM_XTS_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2020_1010; +} diff --git a/esp32p4/src/spi0/spi_mem_xts_destination.rs b/esp32p4/src/spi0/spi_mem_xts_destination.rs new file mode 100644 index 0000000000..32c3c21737 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_xts_destination.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_XTS_DESTINATION` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_XTS_DESTINATION` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_XTS_DESTINATION` reader - This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used."] +pub type SPI_XTS_DESTINATION_R = crate::BitReader; +#[doc = "Field `SPI_XTS_DESTINATION` writer - This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used."] +pub type SPI_XTS_DESTINATION_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used."] + #[inline(always)] + pub fn spi_xts_destination(&self) -> SPI_XTS_DESTINATION_R { + SPI_XTS_DESTINATION_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_XTS_DESTINATION") + .field( + "spi_xts_destination", + &format_args!("{}", self.spi_xts_destination().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used."] + #[inline(always)] + #[must_use] + pub fn spi_xts_destination(&mut self) -> SPI_XTS_DESTINATION_W { + SPI_XTS_DESTINATION_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Manual Encryption destination register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_destination::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_destination::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_XTS_DESTINATION_SPEC; +impl crate::RegisterSpec for SPI_MEM_XTS_DESTINATION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_xts_destination::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_XTS_DESTINATION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_xts_destination::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_XTS_DESTINATION_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_XTS_DESTINATION to value 0"] +impl crate::Resettable for SPI_MEM_XTS_DESTINATION_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_xts_destroy.rs b/esp32p4/src/spi0/spi_mem_xts_destroy.rs new file mode 100644 index 0000000000..0f0c544106 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_xts_destroy.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SPI_MEM_XTS_DESTROY` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_XTS_DESTROY` writer - Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0."] +pub type SPI_XTS_DESTROY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0."] + #[inline(always)] + #[must_use] + pub fn spi_xts_destroy(&mut self) -> SPI_XTS_DESTROY_W { + SPI_XTS_DESTROY_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Manual Encryption physical address register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_destroy::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_XTS_DESTROY_SPEC; +impl crate::RegisterSpec for SPI_MEM_XTS_DESTROY_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`spi_mem_xts_destroy::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_XTS_DESTROY_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_XTS_DESTROY to value 0"] +impl crate::Resettable for SPI_MEM_XTS_DESTROY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_xts_linesize.rs b/esp32p4/src/spi0/spi_mem_xts_linesize.rs new file mode 100644 index 0000000000..e39d3a5051 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_xts_linesize.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_XTS_LINESIZE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_XTS_LINESIZE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_XTS_LINESIZE` reader - This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved."] +pub type SPI_XTS_LINESIZE_R = crate::FieldReader; +#[doc = "Field `SPI_XTS_LINESIZE` writer - This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved."] +pub type SPI_XTS_LINESIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved."] + #[inline(always)] + pub fn spi_xts_linesize(&self) -> SPI_XTS_LINESIZE_R { + SPI_XTS_LINESIZE_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_XTS_LINESIZE") + .field( + "spi_xts_linesize", + &format_args!("{}", self.spi_xts_linesize().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved."] + #[inline(always)] + #[must_use] + pub fn spi_xts_linesize(&mut self) -> SPI_XTS_LINESIZE_W { + SPI_XTS_LINESIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Manual Encryption Line-Size register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_linesize::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_linesize::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_XTS_LINESIZE_SPEC; +impl crate::RegisterSpec for SPI_MEM_XTS_LINESIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_xts_linesize::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_XTS_LINESIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_xts_linesize::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_XTS_LINESIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_XTS_LINESIZE to value 0"] +impl crate::Resettable for SPI_MEM_XTS_LINESIZE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_xts_physical_address.rs b/esp32p4/src/spi0/spi_mem_xts_physical_address.rs new file mode 100644 index 0000000000..a98d32e05f --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_xts_physical_address.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SPI_MEM_XTS_PHYSICAL_ADDRESS` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_XTS_PHYSICAL_ADDRESS` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_XTS_PHYSICAL_ADDRESS` reader - This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter."] +pub type SPI_XTS_PHYSICAL_ADDRESS_R = crate::FieldReader; +#[doc = "Field `SPI_XTS_PHYSICAL_ADDRESS` writer - This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter."] +pub type SPI_XTS_PHYSICAL_ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>; +impl R { + #[doc = "Bits 0:25 - This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter."] + #[inline(always)] + pub fn spi_xts_physical_address(&self) -> SPI_XTS_PHYSICAL_ADDRESS_R { + SPI_XTS_PHYSICAL_ADDRESS_R::new(self.bits & 0x03ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_XTS_PHYSICAL_ADDRESS") + .field( + "spi_xts_physical_address", + &format_args!("{}", self.spi_xts_physical_address().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:25 - This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter."] + #[inline(always)] + #[must_use] + pub fn spi_xts_physical_address( + &mut self, + ) -> SPI_XTS_PHYSICAL_ADDRESS_W { + SPI_XTS_PHYSICAL_ADDRESS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Manual Encryption physical address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_physical_address::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_physical_address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_XTS_PHYSICAL_ADDRESS_SPEC; +impl crate::RegisterSpec for SPI_MEM_XTS_PHYSICAL_ADDRESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_xts_physical_address::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_XTS_PHYSICAL_ADDRESS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_xts_physical_address::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_XTS_PHYSICAL_ADDRESS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_XTS_PHYSICAL_ADDRESS to value 0"] +impl crate::Resettable for SPI_MEM_XTS_PHYSICAL_ADDRESS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_xts_plain_base.rs b/esp32p4/src/spi0/spi_mem_xts_plain_base.rs new file mode 100644 index 0000000000..f13f8de7af --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_xts_plain_base.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_XTS_PLAIN_BASE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_XTS_PLAIN_BASE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_XTS_PLAIN` reader - This field is only used to generate include file in c case. This field is useless. Please do not use this field."] +pub type SPI_XTS_PLAIN_R = crate::FieldReader; +#[doc = "Field `SPI_XTS_PLAIN` writer - This field is only used to generate include file in c case. This field is useless. Please do not use this field."] +pub type SPI_XTS_PLAIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This field is only used to generate include file in c case. This field is useless. Please do not use this field."] + #[inline(always)] + pub fn spi_xts_plain(&self) -> SPI_XTS_PLAIN_R { + SPI_XTS_PLAIN_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_XTS_PLAIN_BASE") + .field( + "spi_xts_plain", + &format_args!("{}", self.spi_xts_plain().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This field is only used to generate include file in c case. This field is useless. Please do not use this field."] + #[inline(always)] + #[must_use] + pub fn spi_xts_plain(&mut self) -> SPI_XTS_PLAIN_W { + SPI_XTS_PLAIN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "The base address of the memory that stores plaintext in Manual Encryption\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_plain_base::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_plain_base::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_XTS_PLAIN_BASE_SPEC; +impl crate::RegisterSpec for SPI_MEM_XTS_PLAIN_BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_xts_plain_base::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_XTS_PLAIN_BASE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_xts_plain_base::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_XTS_PLAIN_BASE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_XTS_PLAIN_BASE to value 0"] +impl crate::Resettable for SPI_MEM_XTS_PLAIN_BASE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_xts_release.rs b/esp32p4/src/spi0/spi_mem_xts_release.rs new file mode 100644 index 0000000000..b4aa12decc --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_xts_release.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SPI_MEM_XTS_RELEASE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_XTS_RELEASE` writer - Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3."] +pub type SPI_XTS_RELEASE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3."] + #[inline(always)] + #[must_use] + pub fn spi_xts_release(&mut self) -> SPI_XTS_RELEASE_W { + SPI_XTS_RELEASE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Manual Encryption physical address register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_release::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_XTS_RELEASE_SPEC; +impl crate::RegisterSpec for SPI_MEM_XTS_RELEASE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`spi_mem_xts_release::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_XTS_RELEASE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_XTS_RELEASE to value 0"] +impl crate::Resettable for SPI_MEM_XTS_RELEASE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_xts_state.rs b/esp32p4/src/spi0/spi_mem_xts_state.rs new file mode 100644 index 0000000000..18e9a8daa8 --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_xts_state.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SPI_MEM_XTS_STATE` reader"] +pub type R = crate::R; +#[doc = "Field `SPI_XTS_STATE` reader - This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi."] +pub type SPI_XTS_STATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi."] + #[inline(always)] + pub fn spi_xts_state(&self) -> SPI_XTS_STATE_R { + SPI_XTS_STATE_R::new((self.bits & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_XTS_STATE") + .field( + "spi_xts_state", + &format_args!("{}", self.spi_xts_state().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Manual Encryption physical address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_xts_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_XTS_STATE_SPEC; +impl crate::RegisterSpec for SPI_MEM_XTS_STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_xts_state::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_XTS_STATE_SPEC {} +#[doc = "`reset()` method sets SPI_MEM_XTS_STATE to value 0"] +impl crate::Resettable for SPI_MEM_XTS_STATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_mem_xts_trigger.rs b/esp32p4/src/spi0/spi_mem_xts_trigger.rs new file mode 100644 index 0000000000..eb3485256c --- /dev/null +++ b/esp32p4/src/spi0/spi_mem_xts_trigger.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SPI_MEM_XTS_TRIGGER` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_XTS_TRIGGER` writer - Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2."] +pub type SPI_XTS_TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2."] + #[inline(always)] + #[must_use] + pub fn spi_xts_trigger(&mut self) -> SPI_XTS_TRIGGER_W { + SPI_XTS_TRIGGER_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Manual Encryption physical address register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_xts_trigger::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_XTS_TRIGGER_SPEC; +impl crate::RegisterSpec for SPI_MEM_XTS_TRIGGER_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`spi_mem_xts_trigger::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_XTS_TRIGGER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_XTS_TRIGGER to value 0"] +impl crate::Resettable for SPI_MEM_XTS_TRIGGER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_smem_ac.rs b/esp32p4/src/spi0/spi_smem_ac.rs new file mode 100644 index 0000000000..f9d6f9f2f0 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_ac.rs @@ -0,0 +1,222 @@ +#[doc = "Register `SPI_SMEM_AC` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_AC` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SMEM_CS_SETUP` reader - For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] +pub type SPI_SMEM_CS_SETUP_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_CS_SETUP` writer - For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] +pub type SPI_SMEM_CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_CS_HOLD` reader - For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable."] +pub type SPI_SMEM_CS_HOLD_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_CS_HOLD` writer - For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable."] +pub type SPI_SMEM_CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_CS_SETUP_TIME` reader - For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit."] +pub type SPI_SMEM_CS_SETUP_TIME_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_CS_SETUP_TIME` writer - For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit."] +pub type SPI_SMEM_CS_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SPI_SMEM_CS_HOLD_TIME` reader - For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit."] +pub type SPI_SMEM_CS_HOLD_TIME_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_CS_HOLD_TIME` writer - For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit."] +pub type SPI_SMEM_CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SPI_SMEM_ECC_CS_HOLD_TIME` reader - SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM."] +pub type SPI_SMEM_ECC_CS_HOLD_TIME_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_ECC_CS_HOLD_TIME` writer - SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM."] +pub type SPI_SMEM_ECC_CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_ECC_SKIP_PAGE_CORNER` reader - 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM."] +pub type SPI_SMEM_ECC_SKIP_PAGE_CORNER_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_ECC_SKIP_PAGE_CORNER` writer - 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM."] +pub type SPI_SMEM_ECC_SKIP_PAGE_CORNER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_ECC_16TO18_BYTE_EN` reader - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM."] +pub type SPI_SMEM_ECC_16TO18_BYTE_EN_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_ECC_16TO18_BYTE_EN` writer - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM."] +pub type SPI_SMEM_ECC_16TO18_BYTE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_CS_HOLD_DELAY` reader - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."] +pub type SPI_SMEM_CS_HOLD_DELAY_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_CS_HOLD_DELAY` writer - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."] +pub type SPI_SMEM_CS_HOLD_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_SMEM_SPLIT_TRANS_EN` reader - Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not."] +pub type SPI_SMEM_SPLIT_TRANS_EN_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_SPLIT_TRANS_EN` writer - Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not."] +pub type SPI_SMEM_SPLIT_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_smem_cs_setup(&self) -> SPI_SMEM_CS_SETUP_R { + SPI_SMEM_CS_SETUP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_smem_cs_hold(&self) -> SPI_SMEM_CS_HOLD_R { + SPI_SMEM_CS_HOLD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:6 - For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit."] + #[inline(always)] + pub fn spi_smem_cs_setup_time(&self) -> SPI_SMEM_CS_SETUP_TIME_R { + SPI_SMEM_CS_SETUP_TIME_R::new(((self.bits >> 2) & 0x1f) as u8) + } + #[doc = "Bits 7:11 - For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit."] + #[inline(always)] + pub fn spi_smem_cs_hold_time(&self) -> SPI_SMEM_CS_HOLD_TIME_R { + SPI_SMEM_CS_HOLD_TIME_R::new(((self.bits >> 7) & 0x1f) as u8) + } + #[doc = "Bits 12:14 - SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM."] + #[inline(always)] + pub fn spi_smem_ecc_cs_hold_time(&self) -> SPI_SMEM_ECC_CS_HOLD_TIME_R { + SPI_SMEM_ECC_CS_HOLD_TIME_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM."] + #[inline(always)] + pub fn spi_smem_ecc_skip_page_corner(&self) -> SPI_SMEM_ECC_SKIP_PAGE_CORNER_R { + SPI_SMEM_ECC_SKIP_PAGE_CORNER_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM."] + #[inline(always)] + pub fn spi_smem_ecc_16to18_byte_en(&self) -> SPI_SMEM_ECC_16TO18_BYTE_EN_R { + SPI_SMEM_ECC_16TO18_BYTE_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."] + #[inline(always)] + pub fn spi_smem_cs_hold_delay(&self) -> SPI_SMEM_CS_HOLD_DELAY_R { + SPI_SMEM_CS_HOLD_DELAY_R::new(((self.bits >> 25) & 0x3f) as u8) + } + #[doc = "Bit 31 - Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not."] + #[inline(always)] + pub fn spi_smem_split_trans_en(&self) -> SPI_SMEM_SPLIT_TRANS_EN_R { + SPI_SMEM_SPLIT_TRANS_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_AC") + .field( + "spi_smem_cs_setup", + &format_args!("{}", self.spi_smem_cs_setup().bit()), + ) + .field( + "spi_smem_cs_hold", + &format_args!("{}", self.spi_smem_cs_hold().bit()), + ) + .field( + "spi_smem_cs_setup_time", + &format_args!("{}", self.spi_smem_cs_setup_time().bits()), + ) + .field( + "spi_smem_cs_hold_time", + &format_args!("{}", self.spi_smem_cs_hold_time().bits()), + ) + .field( + "spi_smem_ecc_cs_hold_time", + &format_args!("{}", self.spi_smem_ecc_cs_hold_time().bits()), + ) + .field( + "spi_smem_ecc_skip_page_corner", + &format_args!("{}", self.spi_smem_ecc_skip_page_corner().bit()), + ) + .field( + "spi_smem_ecc_16to18_byte_en", + &format_args!("{}", self.spi_smem_ecc_16to18_byte_en().bit()), + ) + .field( + "spi_smem_cs_hold_delay", + &format_args!("{}", self.spi_smem_cs_hold_delay().bits()), + ) + .field( + "spi_smem_split_trans_en", + &format_args!("{}", self.spi_smem_split_trans_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_smem_cs_setup(&mut self) -> SPI_SMEM_CS_SETUP_W { + SPI_SMEM_CS_SETUP_W::new(self, 0) + } + #[doc = "Bit 1 - For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_smem_cs_hold(&mut self) -> SPI_SMEM_CS_HOLD_W { + SPI_SMEM_CS_HOLD_W::new(self, 1) + } + #[doc = "Bits 2:6 - For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit."] + #[inline(always)] + #[must_use] + pub fn spi_smem_cs_setup_time(&mut self) -> SPI_SMEM_CS_SETUP_TIME_W { + SPI_SMEM_CS_SETUP_TIME_W::new(self, 2) + } + #[doc = "Bits 7:11 - For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit."] + #[inline(always)] + #[must_use] + pub fn spi_smem_cs_hold_time(&mut self) -> SPI_SMEM_CS_HOLD_TIME_W { + SPI_SMEM_CS_HOLD_TIME_W::new(self, 7) + } + #[doc = "Bits 12:14 - SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM."] + #[inline(always)] + #[must_use] + pub fn spi_smem_ecc_cs_hold_time(&mut self) -> SPI_SMEM_ECC_CS_HOLD_TIME_W { + SPI_SMEM_ECC_CS_HOLD_TIME_W::new(self, 12) + } + #[doc = "Bit 15 - 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM."] + #[inline(always)] + #[must_use] + pub fn spi_smem_ecc_skip_page_corner( + &mut self, + ) -> SPI_SMEM_ECC_SKIP_PAGE_CORNER_W { + SPI_SMEM_ECC_SKIP_PAGE_CORNER_W::new(self, 15) + } + #[doc = "Bit 16 - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM."] + #[inline(always)] + #[must_use] + pub fn spi_smem_ecc_16to18_byte_en( + &mut self, + ) -> SPI_SMEM_ECC_16TO18_BYTE_EN_W { + SPI_SMEM_ECC_16TO18_BYTE_EN_W::new(self, 16) + } + #[doc = "Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY\\[5:0\\] + 1) MSPI core clock cycles."] + #[inline(always)] + #[must_use] + pub fn spi_smem_cs_hold_delay(&mut self) -> SPI_SMEM_CS_HOLD_DELAY_W { + SPI_SMEM_CS_HOLD_DELAY_W::new(self, 25) + } + #[doc = "Bit 31 - Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not."] + #[inline(always)] + #[must_use] + pub fn spi_smem_split_trans_en(&mut self) -> SPI_SMEM_SPLIT_TRANS_EN_W { + SPI_SMEM_SPLIT_TRANS_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI external RAM ECC and SPI CS timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ac::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_ac::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_AC_SPEC; +impl crate::RegisterSpec for SPI_SMEM_AC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_ac::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_AC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_ac::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_AC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_AC to value 0x8000_b084"] +impl crate::Resettable for SPI_SMEM_AC_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_b084; +} diff --git a/esp32p4/src/spi0/spi_smem_axi_addr_ctrl.rs b/esp32p4/src/spi0/spi_smem_axi_addr_ctrl.rs new file mode 100644 index 0000000000..0911ecbc04 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_axi_addr_ctrl.rs @@ -0,0 +1,94 @@ +#[doc = "Register `SPI_SMEM_AXI_ADDR_CTRL` reader"] +pub type R = crate::R; +#[doc = "Field `SPI_MEM_ALL_FIFO_EMPTY` reader - The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others."] +pub type SPI_MEM_ALL_FIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `SPI_RDATA_AFIFO_REMPTY` reader - 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending."] +pub type SPI_RDATA_AFIFO_REMPTY_R = crate::BitReader; +#[doc = "Field `SPI_RADDR_AFIFO_REMPTY` reader - 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending."] +pub type SPI_RADDR_AFIFO_REMPTY_R = crate::BitReader; +#[doc = "Field `SPI_WDATA_AFIFO_REMPTY` reader - 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending."] +pub type SPI_WDATA_AFIFO_REMPTY_R = crate::BitReader; +#[doc = "Field `SPI_WBLEN_AFIFO_REMPTY` reader - 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending."] +pub type SPI_WBLEN_AFIFO_REMPTY_R = crate::BitReader; +#[doc = "Field `SPI_ALL_AXI_TRANS_AFIFO_EMPTY` reader - This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE."] +pub type SPI_ALL_AXI_TRANS_AFIFO_EMPTY_R = crate::BitReader; +impl R { + #[doc = "Bit 26 - The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others."] + #[inline(always)] + pub fn spi_mem_all_fifo_empty(&self) -> SPI_MEM_ALL_FIFO_EMPTY_R { + SPI_MEM_ALL_FIFO_EMPTY_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending."] + #[inline(always)] + pub fn spi_rdata_afifo_rempty(&self) -> SPI_RDATA_AFIFO_REMPTY_R { + SPI_RDATA_AFIFO_REMPTY_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending."] + #[inline(always)] + pub fn spi_raddr_afifo_rempty(&self) -> SPI_RADDR_AFIFO_REMPTY_R { + SPI_RADDR_AFIFO_REMPTY_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending."] + #[inline(always)] + pub fn spi_wdata_afifo_rempty(&self) -> SPI_WDATA_AFIFO_REMPTY_R { + SPI_WDATA_AFIFO_REMPTY_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending."] + #[inline(always)] + pub fn spi_wblen_afifo_rempty(&self) -> SPI_WBLEN_AFIFO_REMPTY_R { + SPI_WBLEN_AFIFO_REMPTY_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE."] + #[inline(always)] + pub fn spi_all_axi_trans_afifo_empty(&self) -> SPI_ALL_AXI_TRANS_AFIFO_EMPTY_R { + SPI_ALL_AXI_TRANS_AFIFO_EMPTY_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_AXI_ADDR_CTRL") + .field( + "spi_mem_all_fifo_empty", + &format_args!("{}", self.spi_mem_all_fifo_empty().bit()), + ) + .field( + "spi_rdata_afifo_rempty", + &format_args!("{}", self.spi_rdata_afifo_rempty().bit()), + ) + .field( + "spi_raddr_afifo_rempty", + &format_args!("{}", self.spi_raddr_afifo_rempty().bit()), + ) + .field( + "spi_wdata_afifo_rempty", + &format_args!("{}", self.spi_wdata_afifo_rempty().bit()), + ) + .field( + "spi_wblen_afifo_rempty", + &format_args!("{}", self.spi_wblen_afifo_rempty().bit()), + ) + .field( + "spi_all_axi_trans_afifo_empty", + &format_args!("{}", self.spi_all_axi_trans_afifo_empty().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "SPI0 AXI address control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_axi_addr_ctrl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_AXI_ADDR_CTRL_SPEC; +impl crate::RegisterSpec for SPI_SMEM_AXI_ADDR_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_axi_addr_ctrl::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_AXI_ADDR_CTRL_SPEC {} +#[doc = "`reset()` method sets SPI_SMEM_AXI_ADDR_CTRL to value 0xfc00_0000"] +impl crate::Resettable for SPI_SMEM_AXI_ADDR_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0xfc00_0000; +} diff --git a/esp32p4/src/spi0/spi_smem_ddr.rs b/esp32p4/src/spi0/spi_smem_ddr.rs new file mode 100644 index 0000000000..d9c2ac3601 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_ddr.rs @@ -0,0 +1,338 @@ +#[doc = "Register `SPI_SMEM_DDR` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_DDR` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - 1: in DDR mode, 0 in SDR mode"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - 1: in DDR mode, 0 in SDR mode"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_VAR_DUMMY` reader - Set the bit to enable variable dummy cycle in spi DDR mode."] +pub type SPI_SMEM_VAR_DUMMY_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_VAR_DUMMY` writer - Set the bit to enable variable dummy cycle in spi DDR mode."] +pub type SPI_SMEM_VAR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RDAT_SWP` reader - Set the bit to reorder rx data of the word in spi DDR mode."] +pub type RDAT_SWP_R = crate::BitReader; +#[doc = "Field `RDAT_SWP` writer - Set the bit to reorder rx data of the word in spi DDR mode."] +pub type RDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDAT_SWP` reader - Set the bit to reorder tx data of the word in spi DDR mode."] +pub type WDAT_SWP_R = crate::BitReader; +#[doc = "Field `WDAT_SWP` writer - Set the bit to reorder tx data of the word in spi DDR mode."] +pub type WDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CMD_DIS` reader - the bit is used to disable dual edge in command phase when DDR mode."] +pub type CMD_DIS_R = crate::BitReader; +#[doc = "Field `CMD_DIS` writer - the bit is used to disable dual edge in command phase when DDR mode."] +pub type CMD_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_OUTMINBYTELEN` reader - It is the minimum output data length in the DDR psram."] +pub type SPI_SMEM_OUTMINBYTELEN_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_OUTMINBYTELEN` writer - It is the minimum output data length in the DDR psram."] +pub type SPI_SMEM_OUTMINBYTELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `SPI_SMEM_TX_DDR_MSK_EN` reader - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM."] +pub type SPI_SMEM_TX_DDR_MSK_EN_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_TX_DDR_MSK_EN` writer - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM."] +pub type SPI_SMEM_TX_DDR_MSK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_RX_DDR_MSK_EN` reader - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM."] +pub type SPI_SMEM_RX_DDR_MSK_EN_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_RX_DDR_MSK_EN` writer - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM."] +pub type SPI_SMEM_RX_DDR_MSK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_USR_DDR_DQS_THD` reader - The delay number of data strobe which from memory based on SPI clock."] +pub type SPI_SMEM_USR_DDR_DQS_THD_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_USR_DDR_DQS_THD` writer - The delay number of data strobe which from memory based on SPI clock."] +pub type SPI_SMEM_USR_DDR_DQS_THD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `DQS_LOOP` reader - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] +pub type DQS_LOOP_R = crate::BitReader; +#[doc = "Field `DQS_LOOP` writer - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] +pub type DQS_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_CLK_DIFF_EN` reader - Set this bit to enable the differential SPI_CLK#."] +pub type SPI_SMEM_CLK_DIFF_EN_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_CLK_DIFF_EN` writer - Set this bit to enable the differential SPI_CLK#."] +pub type SPI_SMEM_CLK_DIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DQS_CA_IN` reader - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] +pub type SPI_SMEM_DQS_CA_IN_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DQS_CA_IN` writer - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] +pub type SPI_SMEM_DQS_CA_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_HYPERBUS_DUMMY_2X` reader - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] +pub type SPI_SMEM_HYPERBUS_DUMMY_2X_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_HYPERBUS_DUMMY_2X` writer - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] +pub type SPI_SMEM_HYPERBUS_DUMMY_2X_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_CLK_DIFF_INV` reader - Set this bit to invert SPI_DIFF when accesses to external RAM. ."] +pub type SPI_SMEM_CLK_DIFF_INV_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_CLK_DIFF_INV` writer - Set this bit to invert SPI_DIFF when accesses to external RAM. ."] +pub type SPI_SMEM_CLK_DIFF_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_OCTA_RAM_ADDR` reader - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] +pub type SPI_SMEM_OCTA_RAM_ADDR_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_OCTA_RAM_ADDR` writer - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] +pub type SPI_SMEM_OCTA_RAM_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_HYPERBUS_CA` reader - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] +pub type SPI_SMEM_HYPERBUS_CA_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_HYPERBUS_CA` writer - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] +pub type SPI_SMEM_HYPERBUS_CA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: in DDR mode, 0 in SDR mode"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in spi DDR mode."] + #[inline(always)] + pub fn spi_smem_var_dummy(&self) -> SPI_SMEM_VAR_DUMMY_R { + SPI_SMEM_VAR_DUMMY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set the bit to reorder rx data of the word in spi DDR mode."] + #[inline(always)] + pub fn rdat_swp(&self) -> RDAT_SWP_R { + RDAT_SWP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set the bit to reorder tx data of the word in spi DDR mode."] + #[inline(always)] + pub fn wdat_swp(&self) -> WDAT_SWP_R { + WDAT_SWP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the bit is used to disable dual edge in command phase when DDR mode."] + #[inline(always)] + pub fn cmd_dis(&self) -> CMD_DIS_R { + CMD_DIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:11 - It is the minimum output data length in the DDR psram."] + #[inline(always)] + pub fn spi_smem_outminbytelen(&self) -> SPI_SMEM_OUTMINBYTELEN_R { + SPI_SMEM_OUTMINBYTELEN_R::new(((self.bits >> 5) & 0x7f) as u8) + } + #[doc = "Bit 12 - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM."] + #[inline(always)] + pub fn spi_smem_tx_ddr_msk_en(&self) -> SPI_SMEM_TX_DDR_MSK_EN_R { + SPI_SMEM_TX_DDR_MSK_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM."] + #[inline(always)] + pub fn spi_smem_rx_ddr_msk_en(&self) -> SPI_SMEM_RX_DDR_MSK_EN_R { + SPI_SMEM_RX_DDR_MSK_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI clock."] + #[inline(always)] + pub fn spi_smem_usr_ddr_dqs_thd(&self) -> SPI_SMEM_USR_DDR_DQS_THD_R { + SPI_SMEM_USR_DDR_DQS_THD_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bit 21 - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] + #[inline(always)] + pub fn dqs_loop(&self) -> DQS_LOOP_R { + DQS_LOOP_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."] + #[inline(always)] + pub fn spi_smem_clk_diff_en(&self) -> SPI_SMEM_CLK_DIFF_EN_R { + SPI_SMEM_CLK_DIFF_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] + #[inline(always)] + pub fn spi_smem_dqs_ca_in(&self) -> SPI_SMEM_DQS_CA_IN_R { + SPI_SMEM_DQS_CA_IN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] + #[inline(always)] + pub fn spi_smem_hyperbus_dummy_2x(&self) -> SPI_SMEM_HYPERBUS_DUMMY_2X_R { + SPI_SMEM_HYPERBUS_DUMMY_2X_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to external RAM. ."] + #[inline(always)] + pub fn spi_smem_clk_diff_inv(&self) -> SPI_SMEM_CLK_DIFF_INV_R { + SPI_SMEM_CLK_DIFF_INV_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] + #[inline(always)] + pub fn spi_smem_octa_ram_addr(&self) -> SPI_SMEM_OCTA_RAM_ADDR_R { + SPI_SMEM_OCTA_RAM_ADDR_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] + #[inline(always)] + pub fn spi_smem_hyperbus_ca(&self) -> SPI_SMEM_HYPERBUS_CA_R { + SPI_SMEM_HYPERBUS_CA_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_DDR") + .field("en", &format_args!("{}", self.en().bit())) + .field( + "spi_smem_var_dummy", + &format_args!("{}", self.spi_smem_var_dummy().bit()), + ) + .field("rdat_swp", &format_args!("{}", self.rdat_swp().bit())) + .field("wdat_swp", &format_args!("{}", self.wdat_swp().bit())) + .field("cmd_dis", &format_args!("{}", self.cmd_dis().bit())) + .field( + "spi_smem_outminbytelen", + &format_args!("{}", self.spi_smem_outminbytelen().bits()), + ) + .field( + "spi_smem_tx_ddr_msk_en", + &format_args!("{}", self.spi_smem_tx_ddr_msk_en().bit()), + ) + .field( + "spi_smem_rx_ddr_msk_en", + &format_args!("{}", self.spi_smem_rx_ddr_msk_en().bit()), + ) + .field( + "spi_smem_usr_ddr_dqs_thd", + &format_args!("{}", self.spi_smem_usr_ddr_dqs_thd().bits()), + ) + .field("dqs_loop", &format_args!("{}", self.dqs_loop().bit())) + .field( + "spi_smem_clk_diff_en", + &format_args!("{}", self.spi_smem_clk_diff_en().bit()), + ) + .field( + "spi_smem_dqs_ca_in", + &format_args!("{}", self.spi_smem_dqs_ca_in().bit()), + ) + .field( + "spi_smem_hyperbus_dummy_2x", + &format_args!("{}", self.spi_smem_hyperbus_dummy_2x().bit()), + ) + .field( + "spi_smem_clk_diff_inv", + &format_args!("{}", self.spi_smem_clk_diff_inv().bit()), + ) + .field( + "spi_smem_octa_ram_addr", + &format_args!("{}", self.spi_smem_octa_ram_addr().bit()), + ) + .field( + "spi_smem_hyperbus_ca", + &format_args!("{}", self.spi_smem_hyperbus_ca().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: in DDR mode, 0 in SDR mode"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in spi DDR mode."] + #[inline(always)] + #[must_use] + pub fn spi_smem_var_dummy(&mut self) -> SPI_SMEM_VAR_DUMMY_W { + SPI_SMEM_VAR_DUMMY_W::new(self, 1) + } + #[doc = "Bit 2 - Set the bit to reorder rx data of the word in spi DDR mode."] + #[inline(always)] + #[must_use] + pub fn rdat_swp(&mut self) -> RDAT_SWP_W { + RDAT_SWP_W::new(self, 2) + } + #[doc = "Bit 3 - Set the bit to reorder tx data of the word in spi DDR mode."] + #[inline(always)] + #[must_use] + pub fn wdat_swp(&mut self) -> WDAT_SWP_W { + WDAT_SWP_W::new(self, 3) + } + #[doc = "Bit 4 - the bit is used to disable dual edge in command phase when DDR mode."] + #[inline(always)] + #[must_use] + pub fn cmd_dis(&mut self) -> CMD_DIS_W { + CMD_DIS_W::new(self, 4) + } + #[doc = "Bits 5:11 - It is the minimum output data length in the DDR psram."] + #[inline(always)] + #[must_use] + pub fn spi_smem_outminbytelen(&mut self) -> SPI_SMEM_OUTMINBYTELEN_W { + SPI_SMEM_OUTMINBYTELEN_W::new(self, 5) + } + #[doc = "Bit 12 - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM."] + #[inline(always)] + #[must_use] + pub fn spi_smem_tx_ddr_msk_en(&mut self) -> SPI_SMEM_TX_DDR_MSK_EN_W { + SPI_SMEM_TX_DDR_MSK_EN_W::new(self, 12) + } + #[doc = "Bit 13 - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM."] + #[inline(always)] + #[must_use] + pub fn spi_smem_rx_ddr_msk_en(&mut self) -> SPI_SMEM_RX_DDR_MSK_EN_W { + SPI_SMEM_RX_DDR_MSK_EN_W::new(self, 13) + } + #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI clock."] + #[inline(always)] + #[must_use] + pub fn spi_smem_usr_ddr_dqs_thd(&mut self) -> SPI_SMEM_USR_DDR_DQS_THD_W { + SPI_SMEM_USR_DDR_DQS_THD_W::new(self, 14) + } + #[doc = "Bit 21 - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] + #[inline(always)] + #[must_use] + pub fn dqs_loop(&mut self) -> DQS_LOOP_W { + DQS_LOOP_W::new(self, 21) + } + #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."] + #[inline(always)] + #[must_use] + pub fn spi_smem_clk_diff_en(&mut self) -> SPI_SMEM_CLK_DIFF_EN_W { + SPI_SMEM_CLK_DIFF_EN_W::new(self, 24) + } + #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] + #[inline(always)] + #[must_use] + pub fn spi_smem_dqs_ca_in(&mut self) -> SPI_SMEM_DQS_CA_IN_W { + SPI_SMEM_DQS_CA_IN_W::new(self, 26) + } + #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] + #[inline(always)] + #[must_use] + pub fn spi_smem_hyperbus_dummy_2x( + &mut self, + ) -> SPI_SMEM_HYPERBUS_DUMMY_2X_W { + SPI_SMEM_HYPERBUS_DUMMY_2X_W::new(self, 27) + } + #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to external RAM. ."] + #[inline(always)] + #[must_use] + pub fn spi_smem_clk_diff_inv(&mut self) -> SPI_SMEM_CLK_DIFF_INV_W { + SPI_SMEM_CLK_DIFF_INV_W::new(self, 28) + } + #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] + #[inline(always)] + #[must_use] + pub fn spi_smem_octa_ram_addr(&mut self) -> SPI_SMEM_OCTA_RAM_ADDR_W { + SPI_SMEM_OCTA_RAM_ADDR_W::new(self, 29) + } + #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] + #[inline(always)] + #[must_use] + pub fn spi_smem_hyperbus_ca(&mut self) -> SPI_SMEM_HYPERBUS_CA_W { + SPI_SMEM_HYPERBUS_CA_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI0 external RAM DDR mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ddr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_ddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_DDR_SPEC; +impl crate::RegisterSpec for SPI_SMEM_DDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_ddr::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_DDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_ddr::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_DDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_DDR to value 0x3020"] +impl crate::Resettable for SPI_SMEM_DDR_SPEC { + const RESET_VALUE: Self::Ux = 0x3020; +} diff --git a/esp32p4/src/spi0/spi_smem_din_hex_mode.rs b/esp32p4/src/spi0/spi_smem_din_hex_mode.rs new file mode 100644 index 0000000000..ed37f440c7 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_din_hex_mode.rs @@ -0,0 +1,220 @@ +#[doc = "Register `SPI_SMEM_DIN_HEX_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_DIN_HEX_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SMEM_DIN08_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN08_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN08_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN08_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN09_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN09_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN09_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN09_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN10_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN10_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN10_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN10_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN11_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN11_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN11_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN11_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN12_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN12_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN12_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN12_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN13_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN13_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN13_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN13_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN14_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN14_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN14_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN14_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN15_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN15_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN15_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN15_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DINS_HEX_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DINS_HEX_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DINS_HEX_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DINS_HEX_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din08_mode(&self) -> SPI_SMEM_DIN08_MODE_R { + SPI_SMEM_DIN08_MODE_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din09_mode(&self) -> SPI_SMEM_DIN09_MODE_R { + SPI_SMEM_DIN09_MODE_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din10_mode(&self) -> SPI_SMEM_DIN10_MODE_R { + SPI_SMEM_DIN10_MODE_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din11_mode(&self) -> SPI_SMEM_DIN11_MODE_R { + SPI_SMEM_DIN11_MODE_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din12_mode(&self) -> SPI_SMEM_DIN12_MODE_R { + SPI_SMEM_DIN12_MODE_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din13_mode(&self) -> SPI_SMEM_DIN13_MODE_R { + SPI_SMEM_DIN13_MODE_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din14_mode(&self) -> SPI_SMEM_DIN14_MODE_R { + SPI_SMEM_DIN14_MODE_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din15_mode(&self) -> SPI_SMEM_DIN15_MODE_R { + SPI_SMEM_DIN15_MODE_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dins_hex_mode(&self) -> SPI_SMEM_DINS_HEX_MODE_R { + SPI_SMEM_DINS_HEX_MODE_R::new(((self.bits >> 24) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_DIN_HEX_MODE") + .field( + "spi_smem_din08_mode", + &format_args!("{}", self.spi_smem_din08_mode().bits()), + ) + .field( + "spi_smem_din09_mode", + &format_args!("{}", self.spi_smem_din09_mode().bits()), + ) + .field( + "spi_smem_din10_mode", + &format_args!("{}", self.spi_smem_din10_mode().bits()), + ) + .field( + "spi_smem_din11_mode", + &format_args!("{}", self.spi_smem_din11_mode().bits()), + ) + .field( + "spi_smem_din12_mode", + &format_args!("{}", self.spi_smem_din12_mode().bits()), + ) + .field( + "spi_smem_din13_mode", + &format_args!("{}", self.spi_smem_din13_mode().bits()), + ) + .field( + "spi_smem_din14_mode", + &format_args!("{}", self.spi_smem_din14_mode().bits()), + ) + .field( + "spi_smem_din15_mode", + &format_args!("{}", self.spi_smem_din15_mode().bits()), + ) + .field( + "spi_smem_dins_hex_mode", + &format_args!("{}", self.spi_smem_dins_hex_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din08_mode(&mut self) -> SPI_SMEM_DIN08_MODE_W { + SPI_SMEM_DIN08_MODE_W::new(self, 0) + } + #[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din09_mode(&mut self) -> SPI_SMEM_DIN09_MODE_W { + SPI_SMEM_DIN09_MODE_W::new(self, 3) + } + #[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din10_mode(&mut self) -> SPI_SMEM_DIN10_MODE_W { + SPI_SMEM_DIN10_MODE_W::new(self, 6) + } + #[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din11_mode(&mut self) -> SPI_SMEM_DIN11_MODE_W { + SPI_SMEM_DIN11_MODE_W::new(self, 9) + } + #[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din12_mode(&mut self) -> SPI_SMEM_DIN12_MODE_W { + SPI_SMEM_DIN12_MODE_W::new(self, 12) + } + #[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din13_mode(&mut self) -> SPI_SMEM_DIN13_MODE_W { + SPI_SMEM_DIN13_MODE_W::new(self, 15) + } + #[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din14_mode(&mut self) -> SPI_SMEM_DIN14_MODE_W { + SPI_SMEM_DIN14_MODE_W::new(self, 18) + } + #[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din15_mode(&mut self) -> SPI_SMEM_DIN15_MODE_W { + SPI_SMEM_DIN15_MODE_W::new(self, 21) + } + #[doc = "Bits 24:26 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dins_hex_mode( + &mut self, + ) -> SPI_SMEM_DINS_HEX_MODE_W { + SPI_SMEM_DINS_HEX_MODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI 16x external RAM input timing delay mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_hex_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_din_hex_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_DIN_HEX_MODE_SPEC; +impl crate::RegisterSpec for SPI_SMEM_DIN_HEX_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_din_hex_mode::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_DIN_HEX_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_din_hex_mode::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_DIN_HEX_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_DIN_HEX_MODE to value 0"] +impl crate::Resettable for SPI_SMEM_DIN_HEX_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_smem_din_hex_num.rs b/esp32p4/src/spi0/spi_smem_din_hex_num.rs new file mode 100644 index 0000000000..8ea9d2a1b5 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_din_hex_num.rs @@ -0,0 +1,218 @@ +#[doc = "Register `SPI_SMEM_DIN_HEX_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_DIN_HEX_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SMEM_DIN08_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN08_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN08_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN08_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN09_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN09_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN09_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN09_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN10_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN10_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN10_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN10_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN11_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN11_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN11_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN11_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN12_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN12_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN12_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN12_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN13_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN13_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN13_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN13_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN14_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN14_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN14_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN14_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN15_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN15_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN15_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN15_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DINS_HEX_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DINS_HEX_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DINS_HEX_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DINS_HEX_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din08_num(&self) -> SPI_SMEM_DIN08_NUM_R { + SPI_SMEM_DIN08_NUM_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din09_num(&self) -> SPI_SMEM_DIN09_NUM_R { + SPI_SMEM_DIN09_NUM_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din10_num(&self) -> SPI_SMEM_DIN10_NUM_R { + SPI_SMEM_DIN10_NUM_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din11_num(&self) -> SPI_SMEM_DIN11_NUM_R { + SPI_SMEM_DIN11_NUM_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din12_num(&self) -> SPI_SMEM_DIN12_NUM_R { + SPI_SMEM_DIN12_NUM_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din13_num(&self) -> SPI_SMEM_DIN13_NUM_R { + SPI_SMEM_DIN13_NUM_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din14_num(&self) -> SPI_SMEM_DIN14_NUM_R { + SPI_SMEM_DIN14_NUM_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din15_num(&self) -> SPI_SMEM_DIN15_NUM_R { + SPI_SMEM_DIN15_NUM_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_dins_hex_num(&self) -> SPI_SMEM_DINS_HEX_NUM_R { + SPI_SMEM_DINS_HEX_NUM_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_DIN_HEX_NUM") + .field( + "spi_smem_din08_num", + &format_args!("{}", self.spi_smem_din08_num().bits()), + ) + .field( + "spi_smem_din09_num", + &format_args!("{}", self.spi_smem_din09_num().bits()), + ) + .field( + "spi_smem_din10_num", + &format_args!("{}", self.spi_smem_din10_num().bits()), + ) + .field( + "spi_smem_din11_num", + &format_args!("{}", self.spi_smem_din11_num().bits()), + ) + .field( + "spi_smem_din12_num", + &format_args!("{}", self.spi_smem_din12_num().bits()), + ) + .field( + "spi_smem_din13_num", + &format_args!("{}", self.spi_smem_din13_num().bits()), + ) + .field( + "spi_smem_din14_num", + &format_args!("{}", self.spi_smem_din14_num().bits()), + ) + .field( + "spi_smem_din15_num", + &format_args!("{}", self.spi_smem_din15_num().bits()), + ) + .field( + "spi_smem_dins_hex_num", + &format_args!("{}", self.spi_smem_dins_hex_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din08_num(&mut self) -> SPI_SMEM_DIN08_NUM_W { + SPI_SMEM_DIN08_NUM_W::new(self, 0) + } + #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din09_num(&mut self) -> SPI_SMEM_DIN09_NUM_W { + SPI_SMEM_DIN09_NUM_W::new(self, 2) + } + #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din10_num(&mut self) -> SPI_SMEM_DIN10_NUM_W { + SPI_SMEM_DIN10_NUM_W::new(self, 4) + } + #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din11_num(&mut self) -> SPI_SMEM_DIN11_NUM_W { + SPI_SMEM_DIN11_NUM_W::new(self, 6) + } + #[doc = "Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din12_num(&mut self) -> SPI_SMEM_DIN12_NUM_W { + SPI_SMEM_DIN12_NUM_W::new(self, 8) + } + #[doc = "Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din13_num(&mut self) -> SPI_SMEM_DIN13_NUM_W { + SPI_SMEM_DIN13_NUM_W::new(self, 10) + } + #[doc = "Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din14_num(&mut self) -> SPI_SMEM_DIN14_NUM_W { + SPI_SMEM_DIN14_NUM_W::new(self, 12) + } + #[doc = "Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din15_num(&mut self) -> SPI_SMEM_DIN15_NUM_W { + SPI_SMEM_DIN15_NUM_W::new(self, 14) + } + #[doc = "Bits 16:17 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_dins_hex_num(&mut self) -> SPI_SMEM_DINS_HEX_NUM_W { + SPI_SMEM_DINS_HEX_NUM_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI 16x external RAM input timing delay number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_hex_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_din_hex_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_DIN_HEX_NUM_SPEC; +impl crate::RegisterSpec for SPI_SMEM_DIN_HEX_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_din_hex_num::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_DIN_HEX_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_din_hex_num::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_DIN_HEX_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_DIN_HEX_NUM to value 0"] +impl crate::Resettable for SPI_SMEM_DIN_HEX_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_smem_din_mode.rs b/esp32p4/src/spi0/spi_smem_din_mode.rs new file mode 100644 index 0000000000..9a392a31c1 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_din_mode.rs @@ -0,0 +1,218 @@ +#[doc = "Register `SPI_SMEM_DIN_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_DIN_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SMEM_DIN0_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN0_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN0_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN0_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN1_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN1_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN1_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN1_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN2_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN2_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN2_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN2_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN3_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN3_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN3_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN3_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN4_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN4_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN4_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN4_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN5_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN5_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN5_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN5_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN6_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN6_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN6_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN6_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DIN7_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN7_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN7_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DIN7_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DINS_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DINS_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DINS_MODE` writer - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] +pub type SPI_SMEM_DINS_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din0_mode(&self) -> SPI_SMEM_DIN0_MODE_R { + SPI_SMEM_DIN0_MODE_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din1_mode(&self) -> SPI_SMEM_DIN1_MODE_R { + SPI_SMEM_DIN1_MODE_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din2_mode(&self) -> SPI_SMEM_DIN2_MODE_R { + SPI_SMEM_DIN2_MODE_R::new(((self.bits >> 6) & 7) as u8) + } + #[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din3_mode(&self) -> SPI_SMEM_DIN3_MODE_R { + SPI_SMEM_DIN3_MODE_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din4_mode(&self) -> SPI_SMEM_DIN4_MODE_R { + SPI_SMEM_DIN4_MODE_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din5_mode(&self) -> SPI_SMEM_DIN5_MODE_R { + SPI_SMEM_DIN5_MODE_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din6_mode(&self) -> SPI_SMEM_DIN6_MODE_R { + SPI_SMEM_DIN6_MODE_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_din7_mode(&self) -> SPI_SMEM_DIN7_MODE_R { + SPI_SMEM_DIN7_MODE_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:26 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dins_mode(&self) -> SPI_SMEM_DINS_MODE_R { + SPI_SMEM_DINS_MODE_R::new(((self.bits >> 24) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_DIN_MODE") + .field( + "spi_smem_din0_mode", + &format_args!("{}", self.spi_smem_din0_mode().bits()), + ) + .field( + "spi_smem_din1_mode", + &format_args!("{}", self.spi_smem_din1_mode().bits()), + ) + .field( + "spi_smem_din2_mode", + &format_args!("{}", self.spi_smem_din2_mode().bits()), + ) + .field( + "spi_smem_din3_mode", + &format_args!("{}", self.spi_smem_din3_mode().bits()), + ) + .field( + "spi_smem_din4_mode", + &format_args!("{}", self.spi_smem_din4_mode().bits()), + ) + .field( + "spi_smem_din5_mode", + &format_args!("{}", self.spi_smem_din5_mode().bits()), + ) + .field( + "spi_smem_din6_mode", + &format_args!("{}", self.spi_smem_din6_mode().bits()), + ) + .field( + "spi_smem_din7_mode", + &format_args!("{}", self.spi_smem_din7_mode().bits()), + ) + .field( + "spi_smem_dins_mode", + &format_args!("{}", self.spi_smem_dins_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din0_mode(&mut self) -> SPI_SMEM_DIN0_MODE_W { + SPI_SMEM_DIN0_MODE_W::new(self, 0) + } + #[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din1_mode(&mut self) -> SPI_SMEM_DIN1_MODE_W { + SPI_SMEM_DIN1_MODE_W::new(self, 3) + } + #[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din2_mode(&mut self) -> SPI_SMEM_DIN2_MODE_W { + SPI_SMEM_DIN2_MODE_W::new(self, 6) + } + #[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din3_mode(&mut self) -> SPI_SMEM_DIN3_MODE_W { + SPI_SMEM_DIN3_MODE_W::new(self, 9) + } + #[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din4_mode(&mut self) -> SPI_SMEM_DIN4_MODE_W { + SPI_SMEM_DIN4_MODE_W::new(self, 12) + } + #[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din5_mode(&mut self) -> SPI_SMEM_DIN5_MODE_W { + SPI_SMEM_DIN5_MODE_W::new(self, 15) + } + #[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din6_mode(&mut self) -> SPI_SMEM_DIN6_MODE_W { + SPI_SMEM_DIN6_MODE_W::new(self, 18) + } + #[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_din7_mode(&mut self) -> SPI_SMEM_DIN7_MODE_W { + SPI_SMEM_DIN7_MODE_W::new(self, 21) + } + #[doc = "Bits 24:26 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dins_mode(&mut self) -> SPI_SMEM_DINS_MODE_W { + SPI_SMEM_DINS_MODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI external RAM input timing delay mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_din_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_DIN_MODE_SPEC; +impl crate::RegisterSpec for SPI_SMEM_DIN_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_din_mode::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_DIN_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_din_mode::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_DIN_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_DIN_MODE to value 0"] +impl crate::Resettable for SPI_SMEM_DIN_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_smem_din_num.rs b/esp32p4/src/spi0/spi_smem_din_num.rs new file mode 100644 index 0000000000..ca9e795837 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_din_num.rs @@ -0,0 +1,218 @@ +#[doc = "Register `SPI_SMEM_DIN_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_DIN_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SMEM_DIN0_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN0_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN0_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN0_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN1_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN1_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN1_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN1_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN2_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN2_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN2_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN2_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN3_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN3_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN3_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN3_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN4_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN4_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN4_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN4_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN5_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN5_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN5_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN5_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN6_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN6_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN6_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN6_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DIN7_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN7_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DIN7_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DIN7_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_DINS_NUM` reader - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DINS_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_DINS_NUM` writer - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] +pub type SPI_SMEM_DINS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din0_num(&self) -> SPI_SMEM_DIN0_NUM_R { + SPI_SMEM_DIN0_NUM_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din1_num(&self) -> SPI_SMEM_DIN1_NUM_R { + SPI_SMEM_DIN1_NUM_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din2_num(&self) -> SPI_SMEM_DIN2_NUM_R { + SPI_SMEM_DIN2_NUM_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din3_num(&self) -> SPI_SMEM_DIN3_NUM_R { + SPI_SMEM_DIN3_NUM_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din4_num(&self) -> SPI_SMEM_DIN4_NUM_R { + SPI_SMEM_DIN4_NUM_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din5_num(&self) -> SPI_SMEM_DIN5_NUM_R { + SPI_SMEM_DIN5_NUM_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din6_num(&self) -> SPI_SMEM_DIN6_NUM_R { + SPI_SMEM_DIN6_NUM_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_din7_num(&self) -> SPI_SMEM_DIN7_NUM_R { + SPI_SMEM_DIN7_NUM_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + pub fn spi_smem_dins_num(&self) -> SPI_SMEM_DINS_NUM_R { + SPI_SMEM_DINS_NUM_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_DIN_NUM") + .field( + "spi_smem_din0_num", + &format_args!("{}", self.spi_smem_din0_num().bits()), + ) + .field( + "spi_smem_din1_num", + &format_args!("{}", self.spi_smem_din1_num().bits()), + ) + .field( + "spi_smem_din2_num", + &format_args!("{}", self.spi_smem_din2_num().bits()), + ) + .field( + "spi_smem_din3_num", + &format_args!("{}", self.spi_smem_din3_num().bits()), + ) + .field( + "spi_smem_din4_num", + &format_args!("{}", self.spi_smem_din4_num().bits()), + ) + .field( + "spi_smem_din5_num", + &format_args!("{}", self.spi_smem_din5_num().bits()), + ) + .field( + "spi_smem_din6_num", + &format_args!("{}", self.spi_smem_din6_num().bits()), + ) + .field( + "spi_smem_din7_num", + &format_args!("{}", self.spi_smem_din7_num().bits()), + ) + .field( + "spi_smem_dins_num", + &format_args!("{}", self.spi_smem_dins_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din0_num(&mut self) -> SPI_SMEM_DIN0_NUM_W { + SPI_SMEM_DIN0_NUM_W::new(self, 0) + } + #[doc = "Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din1_num(&mut self) -> SPI_SMEM_DIN1_NUM_W { + SPI_SMEM_DIN1_NUM_W::new(self, 2) + } + #[doc = "Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din2_num(&mut self) -> SPI_SMEM_DIN2_NUM_W { + SPI_SMEM_DIN2_NUM_W::new(self, 4) + } + #[doc = "Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din3_num(&mut self) -> SPI_SMEM_DIN3_NUM_W { + SPI_SMEM_DIN3_NUM_W::new(self, 6) + } + #[doc = "Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din4_num(&mut self) -> SPI_SMEM_DIN4_NUM_W { + SPI_SMEM_DIN4_NUM_W::new(self, 8) + } + #[doc = "Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din5_num(&mut self) -> SPI_SMEM_DIN5_NUM_W { + SPI_SMEM_DIN5_NUM_W::new(self, 10) + } + #[doc = "Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din6_num(&mut self) -> SPI_SMEM_DIN6_NUM_W { + SPI_SMEM_DIN6_NUM_W::new(self, 12) + } + #[doc = "Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_din7_num(&mut self) -> SPI_SMEM_DIN7_NUM_W { + SPI_SMEM_DIN7_NUM_W::new(self, 14) + } + #[doc = "Bits 16:17 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."] + #[inline(always)] + #[must_use] + pub fn spi_smem_dins_num(&mut self) -> SPI_SMEM_DINS_NUM_W { + SPI_SMEM_DINS_NUM_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI external RAM input timing delay number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_din_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_DIN_NUM_SPEC; +impl crate::RegisterSpec for SPI_SMEM_DIN_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_din_num::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_DIN_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_din_num::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_DIN_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_DIN_NUM to value 0"] +impl crate::Resettable for SPI_SMEM_DIN_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_smem_dout_hex_mode.rs b/esp32p4/src/spi0/spi_smem_dout_hex_mode.rs new file mode 100644 index 0000000000..3017bb2394 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_dout_hex_mode.rs @@ -0,0 +1,220 @@ +#[doc = "Register `SPI_SMEM_DOUT_HEX_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_DOUT_HEX_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SMEM_DOUT08_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT08_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT08_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT08_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT09_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT09_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT09_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT09_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT10_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT10_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT10_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT10_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT11_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT11_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT11_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT11_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT12_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT12_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT12_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT12_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT13_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT13_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT13_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT13_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT14_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT14_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT14_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT14_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT15_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT15_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT15_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT15_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUTS_HEX_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUTS_HEX_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUTS_HEX_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUTS_HEX_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout08_mode(&self) -> SPI_SMEM_DOUT08_MODE_R { + SPI_SMEM_DOUT08_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout09_mode(&self) -> SPI_SMEM_DOUT09_MODE_R { + SPI_SMEM_DOUT09_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout10_mode(&self) -> SPI_SMEM_DOUT10_MODE_R { + SPI_SMEM_DOUT10_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout11_mode(&self) -> SPI_SMEM_DOUT11_MODE_R { + SPI_SMEM_DOUT11_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout12_mode(&self) -> SPI_SMEM_DOUT12_MODE_R { + SPI_SMEM_DOUT12_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout13_mode(&self) -> SPI_SMEM_DOUT13_MODE_R { + SPI_SMEM_DOUT13_MODE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout14_mode(&self) -> SPI_SMEM_DOUT14_MODE_R { + SPI_SMEM_DOUT14_MODE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout15_mode(&self) -> SPI_SMEM_DOUT15_MODE_R { + SPI_SMEM_DOUT15_MODE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_douts_hex_mode(&self) -> SPI_SMEM_DOUTS_HEX_MODE_R { + SPI_SMEM_DOUTS_HEX_MODE_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_DOUT_HEX_MODE") + .field( + "spi_smem_dout08_mode", + &format_args!("{}", self.spi_smem_dout08_mode().bit()), + ) + .field( + "spi_smem_dout09_mode", + &format_args!("{}", self.spi_smem_dout09_mode().bit()), + ) + .field( + "spi_smem_dout10_mode", + &format_args!("{}", self.spi_smem_dout10_mode().bit()), + ) + .field( + "spi_smem_dout11_mode", + &format_args!("{}", self.spi_smem_dout11_mode().bit()), + ) + .field( + "spi_smem_dout12_mode", + &format_args!("{}", self.spi_smem_dout12_mode().bit()), + ) + .field( + "spi_smem_dout13_mode", + &format_args!("{}", self.spi_smem_dout13_mode().bit()), + ) + .field( + "spi_smem_dout14_mode", + &format_args!("{}", self.spi_smem_dout14_mode().bit()), + ) + .field( + "spi_smem_dout15_mode", + &format_args!("{}", self.spi_smem_dout15_mode().bit()), + ) + .field( + "spi_smem_douts_hex_mode", + &format_args!("{}", self.spi_smem_douts_hex_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout08_mode(&mut self) -> SPI_SMEM_DOUT08_MODE_W { + SPI_SMEM_DOUT08_MODE_W::new(self, 0) + } + #[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout09_mode(&mut self) -> SPI_SMEM_DOUT09_MODE_W { + SPI_SMEM_DOUT09_MODE_W::new(self, 1) + } + #[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout10_mode(&mut self) -> SPI_SMEM_DOUT10_MODE_W { + SPI_SMEM_DOUT10_MODE_W::new(self, 2) + } + #[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout11_mode(&mut self) -> SPI_SMEM_DOUT11_MODE_W { + SPI_SMEM_DOUT11_MODE_W::new(self, 3) + } + #[doc = "Bit 4 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout12_mode(&mut self) -> SPI_SMEM_DOUT12_MODE_W { + SPI_SMEM_DOUT12_MODE_W::new(self, 4) + } + #[doc = "Bit 5 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout13_mode(&mut self) -> SPI_SMEM_DOUT13_MODE_W { + SPI_SMEM_DOUT13_MODE_W::new(self, 5) + } + #[doc = "Bit 6 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout14_mode(&mut self) -> SPI_SMEM_DOUT14_MODE_W { + SPI_SMEM_DOUT14_MODE_W::new(self, 6) + } + #[doc = "Bit 7 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout15_mode(&mut self) -> SPI_SMEM_DOUT15_MODE_W { + SPI_SMEM_DOUT15_MODE_W::new(self, 7) + } + #[doc = "Bit 8 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_douts_hex_mode( + &mut self, + ) -> SPI_SMEM_DOUTS_HEX_MODE_W { + SPI_SMEM_DOUTS_HEX_MODE_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI 16x external RAM output timing adjustment control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_dout_hex_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_dout_hex_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_DOUT_HEX_MODE_SPEC; +impl crate::RegisterSpec for SPI_SMEM_DOUT_HEX_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_dout_hex_mode::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_DOUT_HEX_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_dout_hex_mode::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_DOUT_HEX_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_DOUT_HEX_MODE to value 0"] +impl crate::Resettable for SPI_SMEM_DOUT_HEX_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_smem_dout_mode.rs b/esp32p4/src/spi0/spi_smem_dout_mode.rs new file mode 100644 index 0000000000..0d0a624555 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_dout_mode.rs @@ -0,0 +1,218 @@ +#[doc = "Register `SPI_SMEM_DOUT_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_DOUT_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SMEM_DOUT0_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT0_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT0_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT0_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT1_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT1_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT1_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT1_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT2_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT2_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT2_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT2_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT3_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT3_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT3_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT3_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT4_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT4_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT4_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT4_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT5_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT5_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT5_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT5_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT6_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT6_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT6_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT6_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUT7_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT7_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUT7_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUT7_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_DOUTS_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUTS_MODE_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DOUTS_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] +pub type SPI_SMEM_DOUTS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout0_mode(&self) -> SPI_SMEM_DOUT0_MODE_R { + SPI_SMEM_DOUT0_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout1_mode(&self) -> SPI_SMEM_DOUT1_MODE_R { + SPI_SMEM_DOUT1_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout2_mode(&self) -> SPI_SMEM_DOUT2_MODE_R { + SPI_SMEM_DOUT2_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout3_mode(&self) -> SPI_SMEM_DOUT3_MODE_R { + SPI_SMEM_DOUT3_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout4_mode(&self) -> SPI_SMEM_DOUT4_MODE_R { + SPI_SMEM_DOUT4_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout5_mode(&self) -> SPI_SMEM_DOUT5_MODE_R { + SPI_SMEM_DOUT5_MODE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout6_mode(&self) -> SPI_SMEM_DOUT6_MODE_R { + SPI_SMEM_DOUT6_MODE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_dout7_mode(&self) -> SPI_SMEM_DOUT7_MODE_R { + SPI_SMEM_DOUT7_MODE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + pub fn spi_smem_douts_mode(&self) -> SPI_SMEM_DOUTS_MODE_R { + SPI_SMEM_DOUTS_MODE_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_DOUT_MODE") + .field( + "spi_smem_dout0_mode", + &format_args!("{}", self.spi_smem_dout0_mode().bit()), + ) + .field( + "spi_smem_dout1_mode", + &format_args!("{}", self.spi_smem_dout1_mode().bit()), + ) + .field( + "spi_smem_dout2_mode", + &format_args!("{}", self.spi_smem_dout2_mode().bit()), + ) + .field( + "spi_smem_dout3_mode", + &format_args!("{}", self.spi_smem_dout3_mode().bit()), + ) + .field( + "spi_smem_dout4_mode", + &format_args!("{}", self.spi_smem_dout4_mode().bit()), + ) + .field( + "spi_smem_dout5_mode", + &format_args!("{}", self.spi_smem_dout5_mode().bit()), + ) + .field( + "spi_smem_dout6_mode", + &format_args!("{}", self.spi_smem_dout6_mode().bit()), + ) + .field( + "spi_smem_dout7_mode", + &format_args!("{}", self.spi_smem_dout7_mode().bit()), + ) + .field( + "spi_smem_douts_mode", + &format_args!("{}", self.spi_smem_douts_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout0_mode(&mut self) -> SPI_SMEM_DOUT0_MODE_W { + SPI_SMEM_DOUT0_MODE_W::new(self, 0) + } + #[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout1_mode(&mut self) -> SPI_SMEM_DOUT1_MODE_W { + SPI_SMEM_DOUT1_MODE_W::new(self, 1) + } + #[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout2_mode(&mut self) -> SPI_SMEM_DOUT2_MODE_W { + SPI_SMEM_DOUT2_MODE_W::new(self, 2) + } + #[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout3_mode(&mut self) -> SPI_SMEM_DOUT3_MODE_W { + SPI_SMEM_DOUT3_MODE_W::new(self, 3) + } + #[doc = "Bit 4 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout4_mode(&mut self) -> SPI_SMEM_DOUT4_MODE_W { + SPI_SMEM_DOUT4_MODE_W::new(self, 4) + } + #[doc = "Bit 5 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout5_mode(&mut self) -> SPI_SMEM_DOUT5_MODE_W { + SPI_SMEM_DOUT5_MODE_W::new(self, 5) + } + #[doc = "Bit 6 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout6_mode(&mut self) -> SPI_SMEM_DOUT6_MODE_W { + SPI_SMEM_DOUT6_MODE_W::new(self, 6) + } + #[doc = "Bit 7 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_dout7_mode(&mut self) -> SPI_SMEM_DOUT7_MODE_W { + SPI_SMEM_DOUT7_MODE_W::new(self, 7) + } + #[doc = "Bit 8 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"] + #[inline(always)] + #[must_use] + pub fn spi_smem_douts_mode(&mut self) -> SPI_SMEM_DOUTS_MODE_W { + SPI_SMEM_DOUTS_MODE_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI external RAM output timing adjustment control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_dout_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_dout_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_DOUT_MODE_SPEC; +impl crate::RegisterSpec for SPI_SMEM_DOUT_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_dout_mode::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_DOUT_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_dout_mode::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_DOUT_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_DOUT_MODE to value 0"] +impl crate::Resettable for SPI_SMEM_DOUT_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_smem_ecc_ctrl.rs b/esp32p4/src/spi0/spi_smem_ecc_ctrl.rs new file mode 100644 index 0000000000..535a87f209 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_ecc_ctrl.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SPI_SMEM_ECC_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_ECC_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SMEM_ECC_ERR_INT_EN` reader - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM."] +pub type SPI_SMEM_ECC_ERR_INT_EN_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_ECC_ERR_INT_EN` writer - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM."] +pub type SPI_SMEM_ECC_ERR_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_PAGE_SIZE` reader - Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."] +pub type SPI_SMEM_PAGE_SIZE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_PAGE_SIZE` writer - Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."] +pub type SPI_SMEM_PAGE_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_SMEM_ECC_ADDR_EN` reader - Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1."] +pub type SPI_SMEM_ECC_ADDR_EN_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_ECC_ADDR_EN` writer - Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1."] +pub type SPI_SMEM_ECC_ADDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 17 - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM."] + #[inline(always)] + pub fn spi_smem_ecc_err_int_en(&self) -> SPI_SMEM_ECC_ERR_INT_EN_R { + SPI_SMEM_ECC_ERR_INT_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."] + #[inline(always)] + pub fn spi_smem_page_size(&self) -> SPI_SMEM_PAGE_SIZE_R { + SPI_SMEM_PAGE_SIZE_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 20 - Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1."] + #[inline(always)] + pub fn spi_smem_ecc_addr_en(&self) -> SPI_SMEM_ECC_ADDR_EN_R { + SPI_SMEM_ECC_ADDR_EN_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_ECC_CTRL") + .field( + "spi_smem_ecc_err_int_en", + &format_args!("{}", self.spi_smem_ecc_err_int_en().bit()), + ) + .field( + "spi_smem_page_size", + &format_args!("{}", self.spi_smem_page_size().bits()), + ) + .field( + "spi_smem_ecc_addr_en", + &format_args!("{}", self.spi_smem_ecc_addr_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 17 - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM."] + #[inline(always)] + #[must_use] + pub fn spi_smem_ecc_err_int_en(&mut self) -> SPI_SMEM_ECC_ERR_INT_EN_W { + SPI_SMEM_ECC_ERR_INT_EN_W::new(self, 17) + } + #[doc = "Bits 18:19 - Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."] + #[inline(always)] + #[must_use] + pub fn spi_smem_page_size(&mut self) -> SPI_SMEM_PAGE_SIZE_W { + SPI_SMEM_PAGE_SIZE_W::new(self, 18) + } + #[doc = "Bit 20 - Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1."] + #[inline(always)] + #[must_use] + pub fn spi_smem_ecc_addr_en(&mut self) -> SPI_SMEM_ECC_ADDR_EN_W { + SPI_SMEM_ECC_ADDR_EN_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI ECC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ecc_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_ecc_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_ECC_CTRL_SPEC; +impl crate::RegisterSpec for SPI_SMEM_ECC_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_ecc_ctrl::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_ECC_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_ecc_ctrl::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_ECC_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_ECC_CTRL to value 0x0008_0000"] +impl crate::Resettable for SPI_SMEM_ECC_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0008_0000; +} diff --git a/esp32p4/src/spi0/spi_smem_pms_addr.rs b/esp32p4/src/spi0/spi_smem_pms_addr.rs new file mode 100644 index 0000000000..77496729c0 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_pms_addr.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_SMEM_PMS%s_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_PMS%s_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `S` reader - SPI1 external RAM PMS section %s start address value"] +pub type S_R = crate::FieldReader; +#[doc = "Field `S` writer - SPI1 external RAM PMS section %s start address value"] +pub type S_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 0:26 - SPI1 external RAM PMS section %s start address value"] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(self.bits & 0x07ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_PMS_ADDR") + .field("s", &format_args!("{}", self.s().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:26 - SPI1 external RAM PMS section %s start address value"] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 external RAM PMS section %s start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_pms_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_pms_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_PMS_ADDR_SPEC; +impl crate::RegisterSpec for SPI_SMEM_PMS_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_pms_addr::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_PMS_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_pms_addr::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_PMS_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_PMS%s_ADDR to value 0"] +impl crate::Resettable for SPI_SMEM_PMS_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi0/spi_smem_pms_attr.rs b/esp32p4/src/spi0/spi_smem_pms_attr.rs new file mode 100644 index 0000000000..8138627944 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_pms_attr.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SPI_SMEM_PMS%s_ATTR` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_PMS%s_ATTR` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SMEM_PMS_RD_ATTR` reader - 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed."] +pub type SPI_SMEM_PMS_RD_ATTR_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_PMS_RD_ATTR` writer - 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed."] +pub type SPI_SMEM_PMS_RD_ATTR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_PMS_WR_ATTR` reader - 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed."] +pub type SPI_SMEM_PMS_WR_ATTR_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_PMS_WR_ATTR` writer - 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed."] +pub type SPI_SMEM_PMS_WR_ATTR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_PMS_ECC` reader - SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG."] +pub type SPI_SMEM_PMS_ECC_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_PMS_ECC` writer - SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG."] +pub type SPI_SMEM_PMS_ECC_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed."] + #[inline(always)] + pub fn spi_smem_pms_rd_attr(&self) -> SPI_SMEM_PMS_RD_ATTR_R { + SPI_SMEM_PMS_RD_ATTR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed."] + #[inline(always)] + pub fn spi_smem_pms_wr_attr(&self) -> SPI_SMEM_PMS_WR_ATTR_R { + SPI_SMEM_PMS_WR_ATTR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG."] + #[inline(always)] + pub fn spi_smem_pms_ecc(&self) -> SPI_SMEM_PMS_ECC_R { + SPI_SMEM_PMS_ECC_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_PMS_ATTR") + .field( + "spi_smem_pms_rd_attr", + &format_args!("{}", self.spi_smem_pms_rd_attr().bit()), + ) + .field( + "spi_smem_pms_wr_attr", + &format_args!("{}", self.spi_smem_pms_wr_attr().bit()), + ) + .field( + "spi_smem_pms_ecc", + &format_args!("{}", self.spi_smem_pms_ecc().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed."] + #[inline(always)] + #[must_use] + pub fn spi_smem_pms_rd_attr(&mut self) -> SPI_SMEM_PMS_RD_ATTR_W { + SPI_SMEM_PMS_RD_ATTR_W::new(self, 0) + } + #[doc = "Bit 1 - 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed."] + #[inline(always)] + #[must_use] + pub fn spi_smem_pms_wr_attr(&mut self) -> SPI_SMEM_PMS_WR_ATTR_W { + SPI_SMEM_PMS_WR_ATTR_W::new(self, 1) + } + #[doc = "Bit 2 - SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG."] + #[inline(always)] + #[must_use] + pub fn spi_smem_pms_ecc(&mut self) -> SPI_SMEM_PMS_ECC_W { + SPI_SMEM_PMS_ECC_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 flash PMS section %s start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_pms_attr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_pms_attr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_PMS_ATTR_SPEC; +impl crate::RegisterSpec for SPI_SMEM_PMS_ATTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_pms_attr::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_PMS_ATTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_pms_attr::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_PMS_ATTR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_PMS%s_ATTR to value 0x03"] +impl crate::Resettable for SPI_SMEM_PMS_ATTR_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/spi0/spi_smem_pms_size.rs b/esp32p4/src/spi0/spi_smem_pms_size.rs new file mode 100644 index 0000000000..3ec6680413 --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_pms_size.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_SMEM_PMS%s_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_PMS%s_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SMEM_PMS_SIZE` reader - SPI1 external RAM PMS section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)"] +pub type SPI_SMEM_PMS_SIZE_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_PMS_SIZE` writer - SPI1 external RAM PMS section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)"] +pub type SPI_SMEM_PMS_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bits 0:14 - SPI1 external RAM PMS section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)"] + #[inline(always)] + pub fn spi_smem_pms_size(&self) -> SPI_SMEM_PMS_SIZE_R { + SPI_SMEM_PMS_SIZE_R::new((self.bits & 0x7fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_PMS_SIZE") + .field( + "spi_smem_pms_size", + &format_args!("{}", self.spi_smem_pms_size().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:14 - SPI1 external RAM PMS section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)"] + #[inline(always)] + #[must_use] + pub fn spi_smem_pms_size(&mut self) -> SPI_SMEM_PMS_SIZE_W { + SPI_SMEM_PMS_SIZE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 external RAM PMS section %s start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_pms_size::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_pms_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_PMS_SIZE_SPEC; +impl crate::RegisterSpec for SPI_SMEM_PMS_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_pms_size::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_PMS_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_pms_size::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_PMS_SIZE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_PMS%s_SIZE to value 0x1000"] +impl crate::Resettable for SPI_SMEM_PMS_SIZE_SPEC { + const RESET_VALUE: Self::Ux = 0x1000; +} diff --git a/esp32p4/src/spi0/spi_smem_timing_cali.rs b/esp32p4/src/spi0/spi_smem_timing_cali.rs new file mode 100644 index 0000000000..3b53ab9e4e --- /dev/null +++ b/esp32p4/src/spi0/spi_smem_timing_cali.rs @@ -0,0 +1,129 @@ +#[doc = "Register `SPI_SMEM_TIMING_CALI` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SMEM_TIMING_CALI` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SMEM_TIMING_CLK_ENA` reader - For sram, the bit is used to enable timing adjust clock for all reading operations."] +pub type SPI_SMEM_TIMING_CLK_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_TIMING_CLK_ENA` writer - For sram, the bit is used to enable timing adjust clock for all reading operations."] +pub type SPI_SMEM_TIMING_CLK_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_TIMING_CALI` reader - For sram, the bit is used to enable timing auto-calibration for all reading operations."] +pub type SPI_SMEM_TIMING_CALI_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_TIMING_CALI` writer - For sram, the bit is used to enable timing auto-calibration for all reading operations."] +pub type SPI_SMEM_TIMING_CALI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SMEM_EXTRA_DUMMY_CYCLELEN` reader - For sram, add extra dummy spi clock cycle length for spi clock calibration."] +pub type SPI_SMEM_EXTRA_DUMMY_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `SPI_SMEM_EXTRA_DUMMY_CYCLELEN` writer - For sram, add extra dummy spi clock cycle length for spi clock calibration."] +pub type SPI_SMEM_EXTRA_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SMEM_DLL_TIMING_CALI` reader - Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM."] +pub type SPI_SMEM_DLL_TIMING_CALI_R = crate::BitReader; +#[doc = "Field `SPI_SMEM_DLL_TIMING_CALI` writer - Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM."] +pub type SPI_SMEM_DLL_TIMING_CALI_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - For sram, the bit is used to enable timing adjust clock for all reading operations."] + #[inline(always)] + pub fn spi_smem_timing_clk_ena(&self) -> SPI_SMEM_TIMING_CLK_ENA_R { + SPI_SMEM_TIMING_CLK_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - For sram, the bit is used to enable timing auto-calibration for all reading operations."] + #[inline(always)] + pub fn spi_smem_timing_cali(&self) -> SPI_SMEM_TIMING_CALI_R { + SPI_SMEM_TIMING_CALI_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - For sram, add extra dummy spi clock cycle length for spi clock calibration."] + #[inline(always)] + pub fn spi_smem_extra_dummy_cyclelen(&self) -> SPI_SMEM_EXTRA_DUMMY_CYCLELEN_R { + SPI_SMEM_EXTRA_DUMMY_CYCLELEN_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bit 5 - Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM."] + #[inline(always)] + pub fn spi_smem_dll_timing_cali(&self) -> SPI_SMEM_DLL_TIMING_CALI_R { + SPI_SMEM_DLL_TIMING_CALI_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SMEM_TIMING_CALI") + .field( + "spi_smem_timing_clk_ena", + &format_args!("{}", self.spi_smem_timing_clk_ena().bit()), + ) + .field( + "spi_smem_timing_cali", + &format_args!("{}", self.spi_smem_timing_cali().bit()), + ) + .field( + "spi_smem_extra_dummy_cyclelen", + &format_args!("{}", self.spi_smem_extra_dummy_cyclelen().bits()), + ) + .field( + "spi_smem_dll_timing_cali", + &format_args!("{}", self.spi_smem_dll_timing_cali().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - For sram, the bit is used to enable timing adjust clock for all reading operations."] + #[inline(always)] + #[must_use] + pub fn spi_smem_timing_clk_ena( + &mut self, + ) -> SPI_SMEM_TIMING_CLK_ENA_W { + SPI_SMEM_TIMING_CLK_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - For sram, the bit is used to enable timing auto-calibration for all reading operations."] + #[inline(always)] + #[must_use] + pub fn spi_smem_timing_cali(&mut self) -> SPI_SMEM_TIMING_CALI_W { + SPI_SMEM_TIMING_CALI_W::new(self, 1) + } + #[doc = "Bits 2:4 - For sram, add extra dummy spi clock cycle length for spi clock calibration."] + #[inline(always)] + #[must_use] + pub fn spi_smem_extra_dummy_cyclelen( + &mut self, + ) -> SPI_SMEM_EXTRA_DUMMY_CYCLELEN_W { + SPI_SMEM_EXTRA_DUMMY_CYCLELEN_W::new(self, 2) + } + #[doc = "Bit 5 - Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM."] + #[inline(always)] + #[must_use] + pub fn spi_smem_dll_timing_cali( + &mut self, + ) -> SPI_SMEM_DLL_TIMING_CALI_W { + SPI_SMEM_DLL_TIMING_CALI_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "MSPI external RAM timing calibration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_timing_cali::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_smem_timing_cali::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SMEM_TIMING_CALI_SPEC; +impl crate::RegisterSpec for SPI_SMEM_TIMING_CALI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_smem_timing_cali::R`](R) reader structure"] +impl crate::Readable for SPI_SMEM_TIMING_CALI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_smem_timing_cali::W`](W) writer structure"] +impl crate::Writable for SPI_SMEM_TIMING_CALI_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SMEM_TIMING_CALI to value 0x01"] +impl crate::Resettable for SPI_SMEM_TIMING_CALI_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/spi1.rs b/esp32p4/src/spi1.rs new file mode 100644 index 0000000000..541a86ab83 --- /dev/null +++ b/esp32p4/src/spi1.rs @@ -0,0 +1,445 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + spi_mem_cmd: SPI_MEM_CMD, + spi_mem_addr: SPI_MEM_ADDR, + spi_mem_ctrl: SPI_MEM_CTRL, + spi_mem_ctrl1: SPI_MEM_CTRL1, + spi_mem_ctrl2: SPI_MEM_CTRL2, + spi_mem_clock: SPI_MEM_CLOCK, + spi_mem_user: SPI_MEM_USER, + spi_mem_user1: SPI_MEM_USER1, + spi_mem_user2: SPI_MEM_USER2, + spi_mem_mosi_dlen: SPI_MEM_MOSI_DLEN, + spi_mem_miso_dlen: SPI_MEM_MISO_DLEN, + spi_mem_rd_status: SPI_MEM_RD_STATUS, + _reserved12: [u8; 0x04], + spi_mem_misc: SPI_MEM_MISC, + spi_mem_tx_crc: SPI_MEM_TX_CRC, + spi_mem_cache_fctrl: SPI_MEM_CACHE_FCTRL, + _reserved15: [u8; 0x18], + spi_mem_w0: SPI_MEM_W0, + spi_mem_w1: SPI_MEM_W1, + spi_mem_w2: SPI_MEM_W2, + spi_mem_w3: SPI_MEM_W3, + spi_mem_w4: SPI_MEM_W4, + spi_mem_w5: SPI_MEM_W5, + spi_mem_w6: SPI_MEM_W6, + spi_mem_w7: SPI_MEM_W7, + spi_mem_w8: SPI_MEM_W8, + spi_mem_w9: SPI_MEM_W9, + spi_mem_w10: SPI_MEM_W10, + spi_mem_w11: SPI_MEM_W11, + spi_mem_w12: SPI_MEM_W12, + spi_mem_w13: SPI_MEM_W13, + spi_mem_w14: SPI_MEM_W14, + spi_mem_w15: SPI_MEM_W15, + spi_mem_flash_waiti_ctrl: SPI_MEM_FLASH_WAITI_CTRL, + spi_mem_flash_sus_ctrl: SPI_MEM_FLASH_SUS_CTRL, + spi_mem_flash_sus_cmd: SPI_MEM_FLASH_SUS_CMD, + spi_mem_sus_status: SPI_MEM_SUS_STATUS, + _reserved35: [u8; 0x18], + spi_mem_int_ena: SPI_MEM_INT_ENA, + spi_mem_int_clr: SPI_MEM_INT_CLR, + spi_mem_int_raw: SPI_MEM_INT_RAW, + spi_mem_int_st: SPI_MEM_INT_ST, + _reserved39: [u8; 0x04], + spi_mem_ddr: SPI_MEM_DDR, + _reserved40: [u8; 0xa8], + spi_mem_timing_cali: SPI_MEM_TIMING_CALI, + _reserved41: [u8; 0x7c], + spi_mem_clock_gate: SPI_MEM_CLOCK_GATE, + _reserved42: [u8; 0x01f8], + spi_mem_date: SPI_MEM_DATE, +} +impl RegisterBlock { + #[doc = "0x00 - SPI1 memory command register"] + #[inline(always)] + pub const fn spi_mem_cmd(&self) -> &SPI_MEM_CMD { + &self.spi_mem_cmd + } + #[doc = "0x04 - SPI1 address register"] + #[inline(always)] + pub const fn spi_mem_addr(&self) -> &SPI_MEM_ADDR { + &self.spi_mem_addr + } + #[doc = "0x08 - SPI1 control register."] + #[inline(always)] + pub const fn spi_mem_ctrl(&self) -> &SPI_MEM_CTRL { + &self.spi_mem_ctrl + } + #[doc = "0x0c - SPI1 control1 register."] + #[inline(always)] + pub const fn spi_mem_ctrl1(&self) -> &SPI_MEM_CTRL1 { + &self.spi_mem_ctrl1 + } + #[doc = "0x10 - SPI1 control2 register."] + #[inline(always)] + pub const fn spi_mem_ctrl2(&self) -> &SPI_MEM_CTRL2 { + &self.spi_mem_ctrl2 + } + #[doc = "0x14 - SPI1 clock division control register."] + #[inline(always)] + pub const fn spi_mem_clock(&self) -> &SPI_MEM_CLOCK { + &self.spi_mem_clock + } + #[doc = "0x18 - SPI1 user register."] + #[inline(always)] + pub const fn spi_mem_user(&self) -> &SPI_MEM_USER { + &self.spi_mem_user + } + #[doc = "0x1c - SPI1 user1 register."] + #[inline(always)] + pub const fn spi_mem_user1(&self) -> &SPI_MEM_USER1 { + &self.spi_mem_user1 + } + #[doc = "0x20 - SPI1 user2 register."] + #[inline(always)] + pub const fn spi_mem_user2(&self) -> &SPI_MEM_USER2 { + &self.spi_mem_user2 + } + #[doc = "0x24 - SPI1 send data bit length control register."] + #[inline(always)] + pub const fn spi_mem_mosi_dlen(&self) -> &SPI_MEM_MOSI_DLEN { + &self.spi_mem_mosi_dlen + } + #[doc = "0x28 - SPI1 receive data bit length control register."] + #[inline(always)] + pub const fn spi_mem_miso_dlen(&self) -> &SPI_MEM_MISO_DLEN { + &self.spi_mem_miso_dlen + } + #[doc = "0x2c - SPI1 status register."] + #[inline(always)] + pub const fn spi_mem_rd_status(&self) -> &SPI_MEM_RD_STATUS { + &self.spi_mem_rd_status + } + #[doc = "0x34 - SPI1 misc register"] + #[inline(always)] + pub const fn spi_mem_misc(&self) -> &SPI_MEM_MISC { + &self.spi_mem_misc + } + #[doc = "0x38 - SPI1 TX CRC data register."] + #[inline(always)] + pub const fn spi_mem_tx_crc(&self) -> &SPI_MEM_TX_CRC { + &self.spi_mem_tx_crc + } + #[doc = "0x3c - SPI1 bit mode control register."] + #[inline(always)] + pub const fn spi_mem_cache_fctrl(&self) -> &SPI_MEM_CACHE_FCTRL { + &self.spi_mem_cache_fctrl + } + #[doc = "0x58 - SPI1 memory data buffer0"] + #[inline(always)] + pub const fn spi_mem_w0(&self) -> &SPI_MEM_W0 { + &self.spi_mem_w0 + } + #[doc = "0x5c - SPI1 memory data buffer1"] + #[inline(always)] + pub const fn spi_mem_w1(&self) -> &SPI_MEM_W1 { + &self.spi_mem_w1 + } + #[doc = "0x60 - SPI1 memory data buffer2"] + #[inline(always)] + pub const fn spi_mem_w2(&self) -> &SPI_MEM_W2 { + &self.spi_mem_w2 + } + #[doc = "0x64 - SPI1 memory data buffer3"] + #[inline(always)] + pub const fn spi_mem_w3(&self) -> &SPI_MEM_W3 { + &self.spi_mem_w3 + } + #[doc = "0x68 - SPI1 memory data buffer4"] + #[inline(always)] + pub const fn spi_mem_w4(&self) -> &SPI_MEM_W4 { + &self.spi_mem_w4 + } + #[doc = "0x6c - SPI1 memory data buffer5"] + #[inline(always)] + pub const fn spi_mem_w5(&self) -> &SPI_MEM_W5 { + &self.spi_mem_w5 + } + #[doc = "0x70 - SPI1 memory data buffer6"] + #[inline(always)] + pub const fn spi_mem_w6(&self) -> &SPI_MEM_W6 { + &self.spi_mem_w6 + } + #[doc = "0x74 - SPI1 memory data buffer7"] + #[inline(always)] + pub const fn spi_mem_w7(&self) -> &SPI_MEM_W7 { + &self.spi_mem_w7 + } + #[doc = "0x78 - SPI1 memory data buffer8"] + #[inline(always)] + pub const fn spi_mem_w8(&self) -> &SPI_MEM_W8 { + &self.spi_mem_w8 + } + #[doc = "0x7c - SPI1 memory data buffer9"] + #[inline(always)] + pub const fn spi_mem_w9(&self) -> &SPI_MEM_W9 { + &self.spi_mem_w9 + } + #[doc = "0x80 - SPI1 memory data buffer10"] + #[inline(always)] + pub const fn spi_mem_w10(&self) -> &SPI_MEM_W10 { + &self.spi_mem_w10 + } + #[doc = "0x84 - SPI1 memory data buffer11"] + #[inline(always)] + pub const fn spi_mem_w11(&self) -> &SPI_MEM_W11 { + &self.spi_mem_w11 + } + #[doc = "0x88 - SPI1 memory data buffer12"] + #[inline(always)] + pub const fn spi_mem_w12(&self) -> &SPI_MEM_W12 { + &self.spi_mem_w12 + } + #[doc = "0x8c - SPI1 memory data buffer13"] + #[inline(always)] + pub const fn spi_mem_w13(&self) -> &SPI_MEM_W13 { + &self.spi_mem_w13 + } + #[doc = "0x90 - SPI1 memory data buffer14"] + #[inline(always)] + pub const fn spi_mem_w14(&self) -> &SPI_MEM_W14 { + &self.spi_mem_w14 + } + #[doc = "0x94 - SPI1 memory data buffer15"] + #[inline(always)] + pub const fn spi_mem_w15(&self) -> &SPI_MEM_W15 { + &self.spi_mem_w15 + } + #[doc = "0x98 - SPI1 wait idle control register"] + #[inline(always)] + pub const fn spi_mem_flash_waiti_ctrl(&self) -> &SPI_MEM_FLASH_WAITI_CTRL { + &self.spi_mem_flash_waiti_ctrl + } + #[doc = "0x9c - SPI1 flash suspend control register"] + #[inline(always)] + pub const fn spi_mem_flash_sus_ctrl(&self) -> &SPI_MEM_FLASH_SUS_CTRL { + &self.spi_mem_flash_sus_ctrl + } + #[doc = "0xa0 - SPI1 flash suspend command register"] + #[inline(always)] + pub const fn spi_mem_flash_sus_cmd(&self) -> &SPI_MEM_FLASH_SUS_CMD { + &self.spi_mem_flash_sus_cmd + } + #[doc = "0xa4 - SPI1 flash suspend status register"] + #[inline(always)] + pub const fn spi_mem_sus_status(&self) -> &SPI_MEM_SUS_STATUS { + &self.spi_mem_sus_status + } + #[doc = "0xc0 - SPI1 interrupt enable register"] + #[inline(always)] + pub const fn spi_mem_int_ena(&self) -> &SPI_MEM_INT_ENA { + &self.spi_mem_int_ena + } + #[doc = "0xc4 - SPI1 interrupt clear register"] + #[inline(always)] + pub const fn spi_mem_int_clr(&self) -> &SPI_MEM_INT_CLR { + &self.spi_mem_int_clr + } + #[doc = "0xc8 - SPI1 interrupt raw register"] + #[inline(always)] + pub const fn spi_mem_int_raw(&self) -> &SPI_MEM_INT_RAW { + &self.spi_mem_int_raw + } + #[doc = "0xcc - SPI1 interrupt status register"] + #[inline(always)] + pub const fn spi_mem_int_st(&self) -> &SPI_MEM_INT_ST { + &self.spi_mem_int_st + } + #[doc = "0xd4 - SPI1 DDR control register"] + #[inline(always)] + pub const fn spi_mem_ddr(&self) -> &SPI_MEM_DDR { + &self.spi_mem_ddr + } + #[doc = "0x180 - SPI1 timing control register"] + #[inline(always)] + pub const fn spi_mem_timing_cali(&self) -> &SPI_MEM_TIMING_CALI { + &self.spi_mem_timing_cali + } + #[doc = "0x200 - SPI1 clk_gate register"] + #[inline(always)] + pub const fn spi_mem_clock_gate(&self) -> &SPI_MEM_CLOCK_GATE { + &self.spi_mem_clock_gate + } + #[doc = "0x3fc - Version control register"] + #[inline(always)] + pub const fn spi_mem_date(&self) -> &SPI_MEM_DATE { + &self.spi_mem_date + } +} +#[doc = "SPI_MEM_CMD (rw) register accessor: SPI1 memory command register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_cmd`] module"] +pub type SPI_MEM_CMD = crate::Reg; +#[doc = "SPI1 memory command register"] +pub mod spi_mem_cmd; +#[doc = "SPI_MEM_ADDR (rw) register accessor: SPI1 address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_addr`] module"] +pub type SPI_MEM_ADDR = crate::Reg; +#[doc = "SPI1 address register"] +pub mod spi_mem_addr; +#[doc = "SPI_MEM_CTRL (rw) register accessor: SPI1 control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_ctrl`] module"] +pub type SPI_MEM_CTRL = crate::Reg; +#[doc = "SPI1 control register."] +pub mod spi_mem_ctrl; +#[doc = "SPI_MEM_CTRL1 (rw) register accessor: SPI1 control1 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_ctrl1`] module"] +pub type SPI_MEM_CTRL1 = crate::Reg; +#[doc = "SPI1 control1 register."] +pub mod spi_mem_ctrl1; +#[doc = "SPI_MEM_CTRL2 (w) register accessor: SPI1 control2 register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_ctrl2`] module"] +pub type SPI_MEM_CTRL2 = crate::Reg; +#[doc = "SPI1 control2 register."] +pub mod spi_mem_ctrl2; +#[doc = "SPI_MEM_CLOCK (rw) register accessor: SPI1 clock division control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_clock::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_clock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_clock`] module"] +pub type SPI_MEM_CLOCK = crate::Reg; +#[doc = "SPI1 clock division control register."] +pub mod spi_mem_clock; +#[doc = "SPI_MEM_USER (rw) register accessor: SPI1 user register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_user`] module"] +pub type SPI_MEM_USER = crate::Reg; +#[doc = "SPI1 user register."] +pub mod spi_mem_user; +#[doc = "SPI_MEM_USER1 (rw) register accessor: SPI1 user1 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_user1`] module"] +pub type SPI_MEM_USER1 = crate::Reg; +#[doc = "SPI1 user1 register."] +pub mod spi_mem_user1; +#[doc = "SPI_MEM_USER2 (rw) register accessor: SPI1 user2 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_user2`] module"] +pub type SPI_MEM_USER2 = crate::Reg; +#[doc = "SPI1 user2 register."] +pub mod spi_mem_user2; +#[doc = "SPI_MEM_MOSI_DLEN (rw) register accessor: SPI1 send data bit length control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_mosi_dlen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_mosi_dlen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_mosi_dlen`] module"] +pub type SPI_MEM_MOSI_DLEN = crate::Reg; +#[doc = "SPI1 send data bit length control register."] +pub mod spi_mem_mosi_dlen; +#[doc = "SPI_MEM_MISO_DLEN (rw) register accessor: SPI1 receive data bit length control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_miso_dlen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_miso_dlen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_miso_dlen`] module"] +pub type SPI_MEM_MISO_DLEN = crate::Reg; +#[doc = "SPI1 receive data bit length control register."] +pub mod spi_mem_miso_dlen; +#[doc = "SPI_MEM_RD_STATUS (rw) register accessor: SPI1 status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_rd_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_rd_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_rd_status`] module"] +pub type SPI_MEM_RD_STATUS = crate::Reg; +#[doc = "SPI1 status register."] +pub mod spi_mem_rd_status; +#[doc = "SPI_MEM_MISC (rw) register accessor: SPI1 misc register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_misc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_misc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_misc`] module"] +pub type SPI_MEM_MISC = crate::Reg; +#[doc = "SPI1 misc register"] +pub mod spi_mem_misc; +#[doc = "SPI_MEM_TX_CRC (r) register accessor: SPI1 TX CRC data register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_tx_crc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_tx_crc`] module"] +pub type SPI_MEM_TX_CRC = crate::Reg; +#[doc = "SPI1 TX CRC data register."] +pub mod spi_mem_tx_crc; +#[doc = "SPI_MEM_CACHE_FCTRL (rw) register accessor: SPI1 bit mode control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_cache_fctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_cache_fctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_cache_fctrl`] module"] +pub type SPI_MEM_CACHE_FCTRL = crate::Reg; +#[doc = "SPI1 bit mode control register."] +pub mod spi_mem_cache_fctrl; +#[doc = "SPI_MEM_W0 (rw) register accessor: SPI1 memory data buffer0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w0`] module"] +pub type SPI_MEM_W0 = crate::Reg; +#[doc = "SPI1 memory data buffer0"] +pub mod spi_mem_w0; +#[doc = "SPI_MEM_W1 (rw) register accessor: SPI1 memory data buffer1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w1`] module"] +pub type SPI_MEM_W1 = crate::Reg; +#[doc = "SPI1 memory data buffer1"] +pub mod spi_mem_w1; +#[doc = "SPI_MEM_W2 (rw) register accessor: SPI1 memory data buffer2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w2`] module"] +pub type SPI_MEM_W2 = crate::Reg; +#[doc = "SPI1 memory data buffer2"] +pub mod spi_mem_w2; +#[doc = "SPI_MEM_W3 (rw) register accessor: SPI1 memory data buffer3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w3`] module"] +pub type SPI_MEM_W3 = crate::Reg; +#[doc = "SPI1 memory data buffer3"] +pub mod spi_mem_w3; +#[doc = "SPI_MEM_W4 (rw) register accessor: SPI1 memory data buffer4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w4`] module"] +pub type SPI_MEM_W4 = crate::Reg; +#[doc = "SPI1 memory data buffer4"] +pub mod spi_mem_w4; +#[doc = "SPI_MEM_W5 (rw) register accessor: SPI1 memory data buffer5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w5`] module"] +pub type SPI_MEM_W5 = crate::Reg; +#[doc = "SPI1 memory data buffer5"] +pub mod spi_mem_w5; +#[doc = "SPI_MEM_W6 (rw) register accessor: SPI1 memory data buffer6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w6`] module"] +pub type SPI_MEM_W6 = crate::Reg; +#[doc = "SPI1 memory data buffer6"] +pub mod spi_mem_w6; +#[doc = "SPI_MEM_W7 (rw) register accessor: SPI1 memory data buffer7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w7`] module"] +pub type SPI_MEM_W7 = crate::Reg; +#[doc = "SPI1 memory data buffer7"] +pub mod spi_mem_w7; +#[doc = "SPI_MEM_W8 (rw) register accessor: SPI1 memory data buffer8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w8`] module"] +pub type SPI_MEM_W8 = crate::Reg; +#[doc = "SPI1 memory data buffer8"] +pub mod spi_mem_w8; +#[doc = "SPI_MEM_W9 (rw) register accessor: SPI1 memory data buffer9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w9`] module"] +pub type SPI_MEM_W9 = crate::Reg; +#[doc = "SPI1 memory data buffer9"] +pub mod spi_mem_w9; +#[doc = "SPI_MEM_W10 (rw) register accessor: SPI1 memory data buffer10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w10`] module"] +pub type SPI_MEM_W10 = crate::Reg; +#[doc = "SPI1 memory data buffer10"] +pub mod spi_mem_w10; +#[doc = "SPI_MEM_W11 (rw) register accessor: SPI1 memory data buffer11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w11`] module"] +pub type SPI_MEM_W11 = crate::Reg; +#[doc = "SPI1 memory data buffer11"] +pub mod spi_mem_w11; +#[doc = "SPI_MEM_W12 (rw) register accessor: SPI1 memory data buffer12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w12`] module"] +pub type SPI_MEM_W12 = crate::Reg; +#[doc = "SPI1 memory data buffer12"] +pub mod spi_mem_w12; +#[doc = "SPI_MEM_W13 (rw) register accessor: SPI1 memory data buffer13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w13`] module"] +pub type SPI_MEM_W13 = crate::Reg; +#[doc = "SPI1 memory data buffer13"] +pub mod spi_mem_w13; +#[doc = "SPI_MEM_W14 (rw) register accessor: SPI1 memory data buffer14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w14`] module"] +pub type SPI_MEM_W14 = crate::Reg; +#[doc = "SPI1 memory data buffer14"] +pub mod spi_mem_w14; +#[doc = "SPI_MEM_W15 (rw) register accessor: SPI1 memory data buffer15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_w15`] module"] +pub type SPI_MEM_W15 = crate::Reg; +#[doc = "SPI1 memory data buffer15"] +pub mod spi_mem_w15; +#[doc = "SPI_MEM_FLASH_WAITI_CTRL (rw) register accessor: SPI1 wait idle control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_flash_waiti_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_flash_waiti_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_flash_waiti_ctrl`] module"] +pub type SPI_MEM_FLASH_WAITI_CTRL = + crate::Reg; +#[doc = "SPI1 wait idle control register"] +pub mod spi_mem_flash_waiti_ctrl; +#[doc = "SPI_MEM_FLASH_SUS_CTRL (rw) register accessor: SPI1 flash suspend control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_flash_sus_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_flash_sus_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_flash_sus_ctrl`] module"] +pub type SPI_MEM_FLASH_SUS_CTRL = crate::Reg; +#[doc = "SPI1 flash suspend control register"] +pub mod spi_mem_flash_sus_ctrl; +#[doc = "SPI_MEM_FLASH_SUS_CMD (rw) register accessor: SPI1 flash suspend command register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_flash_sus_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_flash_sus_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_flash_sus_cmd`] module"] +pub type SPI_MEM_FLASH_SUS_CMD = crate::Reg; +#[doc = "SPI1 flash suspend command register"] +pub mod spi_mem_flash_sus_cmd; +#[doc = "SPI_MEM_SUS_STATUS (rw) register accessor: SPI1 flash suspend status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_sus_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_sus_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_sus_status`] module"] +pub type SPI_MEM_SUS_STATUS = crate::Reg; +#[doc = "SPI1 flash suspend status register"] +pub mod spi_mem_sus_status; +#[doc = "SPI_MEM_INT_ENA (rw) register accessor: SPI1 interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_int_ena`] module"] +pub type SPI_MEM_INT_ENA = crate::Reg; +#[doc = "SPI1 interrupt enable register"] +pub mod spi_mem_int_ena; +#[doc = "SPI_MEM_INT_CLR (w) register accessor: SPI1 interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_int_clr`] module"] +pub type SPI_MEM_INT_CLR = crate::Reg; +#[doc = "SPI1 interrupt clear register"] +pub mod spi_mem_int_clr; +#[doc = "SPI_MEM_INT_RAW (rw) register accessor: SPI1 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_int_raw`] module"] +pub type SPI_MEM_INT_RAW = crate::Reg; +#[doc = "SPI1 interrupt raw register"] +pub mod spi_mem_int_raw; +#[doc = "SPI_MEM_INT_ST (r) register accessor: SPI1 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_int_st`] module"] +pub type SPI_MEM_INT_ST = crate::Reg; +#[doc = "SPI1 interrupt status register"] +pub mod spi_mem_int_st; +#[doc = "SPI_MEM_DDR (rw) register accessor: SPI1 DDR control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_ddr`] module"] +pub type SPI_MEM_DDR = crate::Reg; +#[doc = "SPI1 DDR control register"] +pub mod spi_mem_ddr; +#[doc = "SPI_MEM_TIMING_CALI (rw) register accessor: SPI1 timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_timing_cali::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_timing_cali::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_timing_cali`] module"] +pub type SPI_MEM_TIMING_CALI = crate::Reg; +#[doc = "SPI1 timing control register"] +pub mod spi_mem_timing_cali; +#[doc = "SPI_MEM_CLOCK_GATE (rw) register accessor: SPI1 clk_gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_clock_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_clock_gate`] module"] +pub type SPI_MEM_CLOCK_GATE = crate::Reg; +#[doc = "SPI1 clk_gate register"] +pub mod spi_mem_clock_gate; +#[doc = "SPI_MEM_DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_mem_date`] module"] +pub type SPI_MEM_DATE = crate::Reg; +#[doc = "Version control register"] +pub mod spi_mem_date; diff --git a/esp32p4/src/spi1/spi_mem_addr.rs b/esp32p4/src/spi1/spi_mem_addr.rs new file mode 100644 index 0000000000..02f5ad76c4 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_USR_ADDR_VALUE` reader - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer."] +pub type SPI_MEM_USR_ADDR_VALUE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_ADDR_VALUE` writer - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer."] +pub type SPI_MEM_USR_ADDR_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer."] + #[inline(always)] + pub fn spi_mem_usr_addr_value(&self) -> SPI_MEM_USR_ADDR_VALUE_R { + SPI_MEM_USR_ADDR_VALUE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_ADDR") + .field( + "spi_mem_usr_addr_value", + &format_args!("{}", self.spi_mem_usr_addr_value().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_addr_value(&mut self) -> SPI_MEM_USR_ADDR_VALUE_W { + SPI_MEM_USR_ADDR_VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_ADDR_SPEC; +impl crate::RegisterSpec for SPI_MEM_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_addr::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_addr::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_ADDR to value 0"] +impl crate::Resettable for SPI_MEM_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_cache_fctrl.rs b/esp32p4/src/spi1/spi_mem_cache_fctrl.rs new file mode 100644 index 0000000000..5317b8e4df --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_cache_fctrl.rs @@ -0,0 +1,182 @@ +#[doc = "Register `SPI_MEM_CACHE_FCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CACHE_FCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CACHE_USR_ADDR_4BYTE` reader - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."] +pub type SPI_MEM_CACHE_USR_ADDR_4BYTE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CACHE_USR_ADDR_4BYTE` writer - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."] +pub type SPI_MEM_CACHE_USR_ADDR_4BYTE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDIN_DUAL` reader - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FDIN_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDIN_DUAL` writer - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FDIN_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDOUT_DUAL` reader - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FDOUT_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDOUT_DUAL` writer - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FDOUT_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FADDR_DUAL` reader - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FADDR_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FADDR_DUAL` writer - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] +pub type SPI_MEM_FADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDIN_QUAD` reader - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FDIN_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDIN_QUAD` writer - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FDIN_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDOUT_QUAD` reader - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FDOUT_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDOUT_QUAD` writer - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FDOUT_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FADDR_QUAD` reader - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FADDR_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FADDR_QUAD` writer - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] +pub type SPI_MEM_FADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."] + #[inline(always)] + pub fn spi_mem_cache_usr_addr_4byte(&self) -> SPI_MEM_CACHE_USR_ADDR_4BYTE_R { + SPI_MEM_CACHE_USR_ADDR_4BYTE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + pub fn spi_mem_fdin_dual(&self) -> SPI_MEM_FDIN_DUAL_R { + SPI_MEM_FDIN_DUAL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + pub fn spi_mem_fdout_dual(&self) -> SPI_MEM_FDOUT_DUAL_R { + SPI_MEM_FDOUT_DUAL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + pub fn spi_mem_faddr_dual(&self) -> SPI_MEM_FADDR_DUAL_R { + SPI_MEM_FADDR_DUAL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + pub fn spi_mem_fdin_quad(&self) -> SPI_MEM_FDIN_QUAD_R { + SPI_MEM_FDIN_QUAD_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + pub fn spi_mem_fdout_quad(&self) -> SPI_MEM_FDOUT_QUAD_R { + SPI_MEM_FDOUT_QUAD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + pub fn spi_mem_faddr_quad(&self) -> SPI_MEM_FADDR_QUAD_R { + SPI_MEM_FADDR_QUAD_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CACHE_FCTRL") + .field( + "spi_mem_cache_usr_addr_4byte", + &format_args!("{}", self.spi_mem_cache_usr_addr_4byte().bit()), + ) + .field( + "spi_mem_fdin_dual", + &format_args!("{}", self.spi_mem_fdin_dual().bit()), + ) + .field( + "spi_mem_fdout_dual", + &format_args!("{}", self.spi_mem_fdout_dual().bit()), + ) + .field( + "spi_mem_faddr_dual", + &format_args!("{}", self.spi_mem_faddr_dual().bit()), + ) + .field( + "spi_mem_fdin_quad", + &format_args!("{}", self.spi_mem_fdin_quad().bit()), + ) + .field( + "spi_mem_fdout_quad", + &format_args!("{}", self.spi_mem_fdout_quad().bit()), + ) + .field( + "spi_mem_faddr_quad", + &format_args!("{}", self.spi_mem_faddr_quad().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cache_usr_addr_4byte( + &mut self, + ) -> SPI_MEM_CACHE_USR_ADDR_4BYTE_W { + SPI_MEM_CACHE_USR_ADDR_4BYTE_W::new(self, 1) + } + #[doc = "Bit 3 - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdin_dual(&mut self) -> SPI_MEM_FDIN_DUAL_W { + SPI_MEM_FDIN_DUAL_W::new(self, 3) + } + #[doc = "Bit 4 - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdout_dual(&mut self) -> SPI_MEM_FDOUT_DUAL_W { + SPI_MEM_FDOUT_DUAL_W::new(self, 4) + } + #[doc = "Bit 5 - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_faddr_dual(&mut self) -> SPI_MEM_FADDR_DUAL_W { + SPI_MEM_FADDR_DUAL_W::new(self, 5) + } + #[doc = "Bit 6 - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdin_quad(&mut self) -> SPI_MEM_FDIN_QUAD_W { + SPI_MEM_FDIN_QUAD_W::new(self, 6) + } + #[doc = "Bit 7 - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdout_quad(&mut self) -> SPI_MEM_FDOUT_QUAD_W { + SPI_MEM_FDOUT_QUAD_W::new(self, 7) + } + #[doc = "Bit 8 - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."] + #[inline(always)] + #[must_use] + pub fn spi_mem_faddr_quad(&mut self) -> SPI_MEM_FADDR_QUAD_W { + SPI_MEM_FADDR_QUAD_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 bit mode control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_cache_fctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_cache_fctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CACHE_FCTRL_SPEC; +impl crate::RegisterSpec for SPI_MEM_CACHE_FCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_cache_fctrl::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CACHE_FCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_cache_fctrl::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CACHE_FCTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CACHE_FCTRL to value 0"] +impl crate::Resettable for SPI_MEM_CACHE_FCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_clock.rs b/esp32p4/src/spi1/spi_mem_clock.rs new file mode 100644 index 0000000000..1cdfb0cf34 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_clock.rs @@ -0,0 +1,123 @@ +#[doc = "Register `SPI_MEM_CLOCK` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CLOCK` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CLKCNT_L` reader - In the master mode it must be equal to spi_mem_clkcnt_N."] +pub type SPI_MEM_CLKCNT_L_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CLKCNT_L` writer - In the master mode it must be equal to spi_mem_clkcnt_N."] +pub type SPI_MEM_CLKCNT_L_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MEM_CLKCNT_H` reader - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."] +pub type SPI_MEM_CLKCNT_H_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CLKCNT_H` writer - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."] +pub type SPI_MEM_CLKCNT_H_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MEM_CLKCNT_N` reader - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] +pub type SPI_MEM_CLKCNT_N_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CLKCNT_N` writer - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] +pub type SPI_MEM_CLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MEM_CLK_EQU_SYSCLK` reader - reserved"] +pub type SPI_MEM_CLK_EQU_SYSCLK_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CLK_EQU_SYSCLK` writer - reserved"] +pub type SPI_MEM_CLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."] + #[inline(always)] + pub fn spi_mem_clkcnt_l(&self) -> SPI_MEM_CLKCNT_L_R { + SPI_MEM_CLKCNT_L_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."] + #[inline(always)] + pub fn spi_mem_clkcnt_h(&self) -> SPI_MEM_CLKCNT_H_R { + SPI_MEM_CLKCNT_H_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] + #[inline(always)] + pub fn spi_mem_clkcnt_n(&self) -> SPI_MEM_CLKCNT_N_R { + SPI_MEM_CLKCNT_N_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 31 - reserved"] + #[inline(always)] + pub fn spi_mem_clk_equ_sysclk(&self) -> SPI_MEM_CLK_EQU_SYSCLK_R { + SPI_MEM_CLK_EQU_SYSCLK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CLOCK") + .field( + "spi_mem_clkcnt_l", + &format_args!("{}", self.spi_mem_clkcnt_l().bits()), + ) + .field( + "spi_mem_clkcnt_h", + &format_args!("{}", self.spi_mem_clkcnt_h().bits()), + ) + .field( + "spi_mem_clkcnt_n", + &format_args!("{}", self.spi_mem_clkcnt_n().bits()), + ) + .field( + "spi_mem_clk_equ_sysclk", + &format_args!("{}", self.spi_mem_clk_equ_sysclk().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."] + #[inline(always)] + #[must_use] + pub fn spi_mem_clkcnt_l(&mut self) -> SPI_MEM_CLKCNT_L_W { + SPI_MEM_CLKCNT_L_W::new(self, 0) + } + #[doc = "Bits 8:15 - In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_clkcnt_h(&mut self) -> SPI_MEM_CLKCNT_H_W { + SPI_MEM_CLKCNT_H_W::new(self, 8) + } + #[doc = "Bits 16:23 - In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)"] + #[inline(always)] + #[must_use] + pub fn spi_mem_clkcnt_n(&mut self) -> SPI_MEM_CLKCNT_N_W { + SPI_MEM_CLKCNT_N_W::new(self, 16) + } + #[doc = "Bit 31 - reserved"] + #[inline(always)] + #[must_use] + pub fn spi_mem_clk_equ_sysclk(&mut self) -> SPI_MEM_CLK_EQU_SYSCLK_W { + SPI_MEM_CLK_EQU_SYSCLK_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 clock division control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_clock::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_clock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CLOCK_SPEC; +impl crate::RegisterSpec for SPI_MEM_CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_clock::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CLOCK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_clock::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CLOCK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CLOCK to value 0x0003_0103"] +impl crate::Resettable for SPI_MEM_CLOCK_SPEC { + const RESET_VALUE: Self::Ux = 0x0003_0103; +} diff --git a/esp32p4/src/spi1/spi_mem_clock_gate.rs b/esp32p4/src/spi1/spi_mem_clock_gate.rs new file mode 100644 index 0000000000..6b8c9d6735 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_clock_gate.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_CLOCK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CLOCK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CLK_EN` reader - Register clock gate enable signal. 1: Enable. 0: Disable."] +pub type SPI_MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CLK_EN` writer - Register clock gate enable signal. 1: Enable. 0: Disable."] +pub type SPI_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."] + #[inline(always)] + pub fn spi_mem_clk_en(&self) -> SPI_MEM_CLK_EN_R { + SPI_MEM_CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CLOCK_GATE") + .field( + "spi_mem_clk_en", + &format_args!("{}", self.spi_mem_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_clk_en(&mut self) -> SPI_MEM_CLK_EN_W { + SPI_MEM_CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 clk_gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_clock_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_clock_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CLOCK_GATE_SPEC; +impl crate::RegisterSpec for SPI_MEM_CLOCK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_clock_gate::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CLOCK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_clock_gate::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CLOCK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CLOCK_GATE to value 0x01"] +impl crate::Resettable for SPI_MEM_CLOCK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/spi1/spi_mem_cmd.rs b/esp32p4/src/spi1/spi_mem_cmd.rs new file mode 100644 index 0000000000..08ba8b166a --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_cmd.rs @@ -0,0 +1,351 @@ +#[doc = "Register `SPI_MEM_CMD` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CMD` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_MST_ST` reader - The current status of SPI1 master FSM."] +pub type SPI_MEM_MST_ST_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_SLV_ST` reader - The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state."] +pub type SPI_MEM_SLV_ST_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_FLASH_PE` reader - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_PE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_PE` writer - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_PE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR` reader - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_USR_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR` writer - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_USR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_HPM` reader - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_HPM_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_HPM` writer - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_HPM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_RES` reader - This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_RES_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_RES` writer - This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_RES_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_DP` reader - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_DP_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_DP` writer - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_CE` reader - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_CE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_CE` writer - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_CE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_BE` reader - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_BE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_BE` writer - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_BE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_SE` reader - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_SE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_SE` writer - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_SE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_PP` reader - Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."] +pub type SPI_MEM_FLASH_PP_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_PP` writer - Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."] +pub type SPI_MEM_FLASH_PP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_WRSR` reader - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_WRSR_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_WRSR` writer - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_WRSR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_RDSR` reader - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_RDSR_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_RDSR` writer - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_RDSR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_RDID` reader - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] +pub type SPI_MEM_FLASH_RDID_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_RDID` writer - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] +pub type SPI_MEM_FLASH_RDID_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_WRDI` reader - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] +pub type SPI_MEM_FLASH_WRDI_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_WRDI` writer - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] +pub type SPI_MEM_FLASH_WRDI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_WREN` reader - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] +pub type SPI_MEM_FLASH_WREN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_WREN` writer - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] +pub type SPI_MEM_FLASH_WREN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_READ` reader - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] +pub type SPI_MEM_FLASH_READ_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_READ` writer - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] +pub type SPI_MEM_FLASH_READ_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - The current status of SPI1 master FSM."] + #[inline(always)] + pub fn spi_mem_mst_st(&self) -> SPI_MEM_MST_ST_R { + SPI_MEM_MST_ST_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state."] + #[inline(always)] + pub fn spi_mem_slv_st(&self) -> SPI_MEM_SLV_ST_R { + SPI_MEM_SLV_ST_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_pe(&self) -> SPI_MEM_FLASH_PE_R { + SPI_MEM_FLASH_PE_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_usr(&self) -> SPI_MEM_USR_R { + SPI_MEM_USR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_hpm(&self) -> SPI_MEM_FLASH_HPM_R { + SPI_MEM_FLASH_HPM_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_res(&self) -> SPI_MEM_FLASH_RES_R { + SPI_MEM_FLASH_RES_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_dp(&self) -> SPI_MEM_FLASH_DP_R { + SPI_MEM_FLASH_DP_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_ce(&self) -> SPI_MEM_FLASH_CE_R { + SPI_MEM_FLASH_CE_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_be(&self) -> SPI_MEM_FLASH_BE_R { + SPI_MEM_FLASH_BE_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_se(&self) -> SPI_MEM_FLASH_SE_R { + SPI_MEM_FLASH_SE_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_pp(&self) -> SPI_MEM_FLASH_PP_R { + SPI_MEM_FLASH_PP_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_wrsr(&self) -> SPI_MEM_FLASH_WRSR_R { + SPI_MEM_FLASH_WRSR_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_rdsr(&self) -> SPI_MEM_FLASH_RDSR_R { + SPI_MEM_FLASH_RDSR_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_rdid(&self) -> SPI_MEM_FLASH_RDID_R { + SPI_MEM_FLASH_RDID_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_wrdi(&self) -> SPI_MEM_FLASH_WRDI_R { + SPI_MEM_FLASH_WRDI_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_wren(&self) -> SPI_MEM_FLASH_WREN_R { + SPI_MEM_FLASH_WREN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_read(&self) -> SPI_MEM_FLASH_READ_R { + SPI_MEM_FLASH_READ_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CMD") + .field( + "spi_mem_mst_st", + &format_args!("{}", self.spi_mem_mst_st().bits()), + ) + .field( + "spi_mem_slv_st", + &format_args!("{}", self.spi_mem_slv_st().bits()), + ) + .field( + "spi_mem_flash_pe", + &format_args!("{}", self.spi_mem_flash_pe().bit()), + ) + .field("spi_mem_usr", &format_args!("{}", self.spi_mem_usr().bit())) + .field( + "spi_mem_flash_hpm", + &format_args!("{}", self.spi_mem_flash_hpm().bit()), + ) + .field( + "spi_mem_flash_res", + &format_args!("{}", self.spi_mem_flash_res().bit()), + ) + .field( + "spi_mem_flash_dp", + &format_args!("{}", self.spi_mem_flash_dp().bit()), + ) + .field( + "spi_mem_flash_ce", + &format_args!("{}", self.spi_mem_flash_ce().bit()), + ) + .field( + "spi_mem_flash_be", + &format_args!("{}", self.spi_mem_flash_be().bit()), + ) + .field( + "spi_mem_flash_se", + &format_args!("{}", self.spi_mem_flash_se().bit()), + ) + .field( + "spi_mem_flash_pp", + &format_args!("{}", self.spi_mem_flash_pp().bit()), + ) + .field( + "spi_mem_flash_wrsr", + &format_args!("{}", self.spi_mem_flash_wrsr().bit()), + ) + .field( + "spi_mem_flash_rdsr", + &format_args!("{}", self.spi_mem_flash_rdsr().bit()), + ) + .field( + "spi_mem_flash_rdid", + &format_args!("{}", self.spi_mem_flash_rdid().bit()), + ) + .field( + "spi_mem_flash_wrdi", + &format_args!("{}", self.spi_mem_flash_wrdi().bit()), + ) + .field( + "spi_mem_flash_wren", + &format_args!("{}", self.spi_mem_flash_wren().bit()), + ) + .field( + "spi_mem_flash_read", + &format_args!("{}", self.spi_mem_flash_read().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_pe(&mut self) -> SPI_MEM_FLASH_PE_W { + SPI_MEM_FLASH_PE_W::new(self, 17) + } + #[doc = "Bit 18 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr(&mut self) -> SPI_MEM_USR_W { + SPI_MEM_USR_W::new(self, 18) + } + #[doc = "Bit 19 - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_hpm(&mut self) -> SPI_MEM_FLASH_HPM_W { + SPI_MEM_FLASH_HPM_W::new(self, 19) + } + #[doc = "Bit 20 - This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_res(&mut self) -> SPI_MEM_FLASH_RES_W { + SPI_MEM_FLASH_RES_W::new(self, 20) + } + #[doc = "Bit 21 - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_dp(&mut self) -> SPI_MEM_FLASH_DP_W { + SPI_MEM_FLASH_DP_W::new(self, 21) + } + #[doc = "Bit 22 - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_ce(&mut self) -> SPI_MEM_FLASH_CE_W { + SPI_MEM_FLASH_CE_W::new(self, 22) + } + #[doc = "Bit 23 - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_be(&mut self) -> SPI_MEM_FLASH_BE_W { + SPI_MEM_FLASH_BE_W::new(self, 23) + } + #[doc = "Bit 24 - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_se(&mut self) -> SPI_MEM_FLASH_SE_W { + SPI_MEM_FLASH_SE_W::new(self, 24) + } + #[doc = "Bit 25 - Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_pp(&mut self) -> SPI_MEM_FLASH_PP_W { + SPI_MEM_FLASH_PP_W::new(self, 25) + } + #[doc = "Bit 26 - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_wrsr(&mut self) -> SPI_MEM_FLASH_WRSR_W { + SPI_MEM_FLASH_WRSR_W::new(self, 26) + } + #[doc = "Bit 27 - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_rdsr(&mut self) -> SPI_MEM_FLASH_RDSR_W { + SPI_MEM_FLASH_RDSR_W::new(self, 27) + } + #[doc = "Bit 28 - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_rdid(&mut self) -> SPI_MEM_FLASH_RDID_W { + SPI_MEM_FLASH_RDID_W::new(self, 28) + } + #[doc = "Bit 29 - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_wrdi(&mut self) -> SPI_MEM_FLASH_WRDI_W { + SPI_MEM_FLASH_WRDI_W::new(self, 29) + } + #[doc = "Bit 30 - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_wren(&mut self) -> SPI_MEM_FLASH_WREN_W { + SPI_MEM_FLASH_WREN_W::new(self, 30) + } + #[doc = "Bit 31 - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_read(&mut self) -> SPI_MEM_FLASH_READ_W { + SPI_MEM_FLASH_READ_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory command register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CMD_SPEC; +impl crate::RegisterSpec for SPI_MEM_CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_cmd::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_cmd::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CMD to value 0"] +impl crate::Resettable for SPI_MEM_CMD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_ctrl.rs b/esp32p4/src/spi1/spi_mem_ctrl.rs new file mode 100644 index 0000000000..2145221c4d --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_ctrl.rs @@ -0,0 +1,405 @@ +#[doc = "Register `SPI_MEM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_FDUMMY_RIN` reader - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."] +pub type SPI_MEM_FDUMMY_RIN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDUMMY_RIN` writer - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."] +pub type SPI_MEM_FDUMMY_RIN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDUMMY_WOUT` reader - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."] +pub type SPI_MEM_FDUMMY_WOUT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDUMMY_WOUT` writer - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."] +pub type SPI_MEM_FDUMMY_WOUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDOUT_OCT` reader - Apply 8 signals during write-data phase 1:enable 0: disable"] +pub type SPI_MEM_FDOUT_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDOUT_OCT` writer - Apply 8 signals during write-data phase 1:enable 0: disable"] +pub type SPI_MEM_FDOUT_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FDIN_OCT` reader - Apply 8 signals during read-data phase 1:enable 0: disable"] +pub type SPI_MEM_FDIN_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FDIN_OCT` writer - Apply 8 signals during read-data phase 1:enable 0: disable"] +pub type SPI_MEM_FDIN_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FADDR_OCT` reader - Apply 8 signals during address phase 1:enable 0: disable"] +pub type SPI_MEM_FADDR_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FADDR_OCT` writer - Apply 8 signals during address phase 1:enable 0: disable"] +pub type SPI_MEM_FADDR_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FCMD_QUAD` reader - Apply 4 signals during command phase 1:enable 0: disable"] +pub type SPI_MEM_FCMD_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FCMD_QUAD` writer - Apply 4 signals during command phase 1:enable 0: disable"] +pub type SPI_MEM_FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FCMD_OCT` reader - Apply 8 signals during command phase 1:enable 0: disable"] +pub type SPI_MEM_FCMD_OCT_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FCMD_OCT` writer - Apply 8 signals during command phase 1:enable 0: disable"] +pub type SPI_MEM_FCMD_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FCS_CRC_EN` reader - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."] +pub type SPI_MEM_FCS_CRC_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FCS_CRC_EN` writer - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."] +pub type SPI_MEM_FCS_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_TX_CRC_EN` reader - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"] +pub type SPI_MEM_TX_CRC_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_TX_CRC_EN` writer - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"] +pub type SPI_MEM_TX_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FASTRD_MODE` reader - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."] +pub type SPI_MEM_FASTRD_MODE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FASTRD_MODE` writer - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."] +pub type SPI_MEM_FASTRD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_RESANDRES` reader - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."] +pub type SPI_MEM_RESANDRES_R = crate::BitReader; +#[doc = "Field `SPI_MEM_RESANDRES` writer - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."] +pub type SPI_MEM_RESANDRES_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low"] +pub type SPI_MEM_Q_POL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low"] +pub type SPI_MEM_Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low"] +pub type SPI_MEM_D_POL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low"] +pub type SPI_MEM_D_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WP` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low."] +pub type SPI_MEM_WP_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WP` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low."] +pub type SPI_MEM_WP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WRSR_2B` reader - two bytes data will be written to status register when it is set. 1: enable 0: disable."] +pub type SPI_MEM_WRSR_2B_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WRSR_2B` writer - two bytes data will be written to status register when it is set. 1: enable 0: disable."] +pub type SPI_MEM_WRSR_2B_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FREAD_DIO` reader - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_DIO_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FREAD_DIO` writer - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_DIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FREAD_QIO` reader - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_QIO_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FREAD_QIO` writer - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."] +pub type SPI_MEM_FREAD_QIO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."] + #[inline(always)] + pub fn spi_mem_fdummy_rin(&self) -> SPI_MEM_FDUMMY_RIN_R { + SPI_MEM_FDUMMY_RIN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."] + #[inline(always)] + pub fn spi_mem_fdummy_wout(&self) -> SPI_MEM_FDUMMY_WOUT_R { + SPI_MEM_FDUMMY_WOUT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Apply 8 signals during write-data phase 1:enable 0: disable"] + #[inline(always)] + pub fn spi_mem_fdout_oct(&self) -> SPI_MEM_FDOUT_OCT_R { + SPI_MEM_FDOUT_OCT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Apply 8 signals during read-data phase 1:enable 0: disable"] + #[inline(always)] + pub fn spi_mem_fdin_oct(&self) -> SPI_MEM_FDIN_OCT_R { + SPI_MEM_FDIN_OCT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Apply 8 signals during address phase 1:enable 0: disable"] + #[inline(always)] + pub fn spi_mem_faddr_oct(&self) -> SPI_MEM_FADDR_OCT_R { + SPI_MEM_FADDR_OCT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"] + #[inline(always)] + pub fn spi_mem_fcmd_quad(&self) -> SPI_MEM_FCMD_QUAD_R { + SPI_MEM_FCMD_QUAD_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Apply 8 signals during command phase 1:enable 0: disable"] + #[inline(always)] + pub fn spi_mem_fcmd_oct(&self) -> SPI_MEM_FCMD_OCT_R { + SPI_MEM_FCMD_OCT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."] + #[inline(always)] + pub fn spi_mem_fcs_crc_en(&self) -> SPI_MEM_FCS_CRC_EN_R { + SPI_MEM_FCS_CRC_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"] + #[inline(always)] + pub fn spi_mem_tx_crc_en(&self) -> SPI_MEM_TX_CRC_EN_R { + SPI_MEM_TX_CRC_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_fastrd_mode(&self) -> SPI_MEM_FASTRD_MODE_R { + SPI_MEM_FASTRD_MODE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_fread_dual(&self) -> SPI_MEM_FREAD_DUAL_R { + SPI_MEM_FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_resandres(&self) -> SPI_MEM_RESANDRES_R { + SPI_MEM_RESANDRES_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"] + #[inline(always)] + pub fn spi_mem_q_pol(&self) -> SPI_MEM_Q_POL_R { + SPI_MEM_Q_POL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"] + #[inline(always)] + pub fn spi_mem_d_pol(&self) -> SPI_MEM_D_POL_R { + SPI_MEM_D_POL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_fread_quad(&self) -> SPI_MEM_FREAD_QUAD_R { + SPI_MEM_FREAD_QUAD_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."] + #[inline(always)] + pub fn spi_mem_wp(&self) -> SPI_MEM_WP_R { + SPI_MEM_WP_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_wrsr_2b(&self) -> SPI_MEM_WRSR_2B_R { + SPI_MEM_WRSR_2B_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_fread_dio(&self) -> SPI_MEM_FREAD_DIO_R { + SPI_MEM_FREAD_DIO_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_fread_qio(&self) -> SPI_MEM_FREAD_QIO_R { + SPI_MEM_FREAD_QIO_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CTRL") + .field( + "spi_mem_fdummy_rin", + &format_args!("{}", self.spi_mem_fdummy_rin().bit()), + ) + .field( + "spi_mem_fdummy_wout", + &format_args!("{}", self.spi_mem_fdummy_wout().bit()), + ) + .field( + "spi_mem_fdout_oct", + &format_args!("{}", self.spi_mem_fdout_oct().bit()), + ) + .field( + "spi_mem_fdin_oct", + &format_args!("{}", self.spi_mem_fdin_oct().bit()), + ) + .field( + "spi_mem_faddr_oct", + &format_args!("{}", self.spi_mem_faddr_oct().bit()), + ) + .field( + "spi_mem_fcmd_quad", + &format_args!("{}", self.spi_mem_fcmd_quad().bit()), + ) + .field( + "spi_mem_fcmd_oct", + &format_args!("{}", self.spi_mem_fcmd_oct().bit()), + ) + .field( + "spi_mem_fcs_crc_en", + &format_args!("{}", self.spi_mem_fcs_crc_en().bit()), + ) + .field( + "spi_mem_tx_crc_en", + &format_args!("{}", self.spi_mem_tx_crc_en().bit()), + ) + .field( + "spi_mem_fastrd_mode", + &format_args!("{}", self.spi_mem_fastrd_mode().bit()), + ) + .field( + "spi_mem_fread_dual", + &format_args!("{}", self.spi_mem_fread_dual().bit()), + ) + .field( + "spi_mem_resandres", + &format_args!("{}", self.spi_mem_resandres().bit()), + ) + .field( + "spi_mem_q_pol", + &format_args!("{}", self.spi_mem_q_pol().bit()), + ) + .field( + "spi_mem_d_pol", + &format_args!("{}", self.spi_mem_d_pol().bit()), + ) + .field( + "spi_mem_fread_quad", + &format_args!("{}", self.spi_mem_fread_quad().bit()), + ) + .field("spi_mem_wp", &format_args!("{}", self.spi_mem_wp().bit())) + .field( + "spi_mem_wrsr_2b", + &format_args!("{}", self.spi_mem_wrsr_2b().bit()), + ) + .field( + "spi_mem_fread_dio", + &format_args!("{}", self.spi_mem_fread_dio().bit()), + ) + .field( + "spi_mem_fread_qio", + &format_args!("{}", self.spi_mem_fread_qio().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdummy_rin(&mut self) -> SPI_MEM_FDUMMY_RIN_W { + SPI_MEM_FDUMMY_RIN_W::new(self, 2) + } + #[doc = "Bit 3 - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdummy_wout(&mut self) -> SPI_MEM_FDUMMY_WOUT_W { + SPI_MEM_FDUMMY_WOUT_W::new(self, 3) + } + #[doc = "Bit 4 - Apply 8 signals during write-data phase 1:enable 0: disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdout_oct(&mut self) -> SPI_MEM_FDOUT_OCT_W { + SPI_MEM_FDOUT_OCT_W::new(self, 4) + } + #[doc = "Bit 5 - Apply 8 signals during read-data phase 1:enable 0: disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_fdin_oct(&mut self) -> SPI_MEM_FDIN_OCT_W { + SPI_MEM_FDIN_OCT_W::new(self, 5) + } + #[doc = "Bit 6 - Apply 8 signals during address phase 1:enable 0: disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_faddr_oct(&mut self) -> SPI_MEM_FADDR_OCT_W { + SPI_MEM_FADDR_OCT_W::new(self, 6) + } + #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_fcmd_quad(&mut self) -> SPI_MEM_FCMD_QUAD_W { + SPI_MEM_FCMD_QUAD_W::new(self, 8) + } + #[doc = "Bit 9 - Apply 8 signals during command phase 1:enable 0: disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_fcmd_oct(&mut self) -> SPI_MEM_FCMD_OCT_W { + SPI_MEM_FCMD_OCT_W::new(self, 9) + } + #[doc = "Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fcs_crc_en(&mut self) -> SPI_MEM_FCS_CRC_EN_W { + SPI_MEM_FCS_CRC_EN_W::new(self, 10) + } + #[doc = "Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"] + #[inline(always)] + #[must_use] + pub fn spi_mem_tx_crc_en(&mut self) -> SPI_MEM_TX_CRC_EN_W { + SPI_MEM_TX_CRC_EN_W::new(self, 11) + } + #[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fastrd_mode(&mut self) -> SPI_MEM_FASTRD_MODE_W { + SPI_MEM_FASTRD_MODE_W::new(self, 13) + } + #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fread_dual(&mut self) -> SPI_MEM_FREAD_DUAL_W { + SPI_MEM_FREAD_DUAL_W::new(self, 14) + } + #[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_resandres(&mut self) -> SPI_MEM_RESANDRES_W { + SPI_MEM_RESANDRES_W::new(self, 15) + } + #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"] + #[inline(always)] + #[must_use] + pub fn spi_mem_q_pol(&mut self) -> SPI_MEM_Q_POL_W { + SPI_MEM_Q_POL_W::new(self, 18) + } + #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"] + #[inline(always)] + #[must_use] + pub fn spi_mem_d_pol(&mut self) -> SPI_MEM_D_POL_W { + SPI_MEM_D_POL_W::new(self, 19) + } + #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fread_quad(&mut self) -> SPI_MEM_FREAD_QUAD_W { + SPI_MEM_FREAD_QUAD_W::new(self, 20) + } + #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wp(&mut self) -> SPI_MEM_WP_W { + SPI_MEM_WP_W::new(self, 21) + } + #[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wrsr_2b(&mut self) -> SPI_MEM_WRSR_2B_W { + SPI_MEM_WRSR_2B_W::new(self, 22) + } + #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fread_dio(&mut self) -> SPI_MEM_FREAD_DIO_W { + SPI_MEM_FREAD_DIO_W::new(self, 23) + } + #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fread_qio(&mut self) -> SPI_MEM_FREAD_QIO_W { + SPI_MEM_FREAD_QIO_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CTRL_SPEC; +impl crate::RegisterSpec for SPI_MEM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_ctrl::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_ctrl::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CTRL to value 0x002c_a00c"] +impl crate::Resettable for SPI_MEM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x002c_a00c; +} diff --git a/esp32p4/src/spi1/spi_mem_ctrl1.rs b/esp32p4/src/spi1/spi_mem_ctrl1.rs new file mode 100644 index 0000000000..f2d8a72a0c --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_ctrl1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SPI_MEM_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."] +pub type SPI_MEM_CLK_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CLK_MODE` writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."] +pub type SPI_MEM_CLK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_MEM_CS_HOLD_DLY_RES` reader - After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 512) SPI_CLK cycles."] +pub type SPI_MEM_CS_HOLD_DLY_RES_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_CS_HOLD_DLY_RES` writer - After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 512) SPI_CLK cycles."] +pub type SPI_MEM_CS_HOLD_DLY_RES_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."] + #[inline(always)] + pub fn spi_mem_clk_mode(&self) -> SPI_MEM_CLK_MODE_R { + SPI_MEM_CLK_MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:11 - After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 512) SPI_CLK cycles."] + #[inline(always)] + pub fn spi_mem_cs_hold_dly_res(&self) -> SPI_MEM_CS_HOLD_DLY_RES_R { + SPI_MEM_CS_HOLD_DLY_RES_R::new(((self.bits >> 2) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_CTRL1") + .field( + "spi_mem_clk_mode", + &format_args!("{}", self.spi_mem_clk_mode().bits()), + ) + .field( + "spi_mem_cs_hold_dly_res", + &format_args!("{}", self.spi_mem_cs_hold_dly_res().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."] + #[inline(always)] + #[must_use] + pub fn spi_mem_clk_mode(&mut self) -> SPI_MEM_CLK_MODE_W { + SPI_MEM_CLK_MODE_W::new(self, 0) + } + #[doc = "Bits 2:11 - After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 512) SPI_CLK cycles."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cs_hold_dly_res(&mut self) -> SPI_MEM_CS_HOLD_DLY_RES_W { + SPI_MEM_CS_HOLD_DLY_RES_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 control1 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CTRL1_SPEC; +impl crate::RegisterSpec for SPI_MEM_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_ctrl1::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_ctrl1::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CTRL1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CTRL1 to value 0x0ffc"] +impl crate::Resettable for SPI_MEM_CTRL1_SPEC { + const RESET_VALUE: Self::Ux = 0x0ffc; +} diff --git a/esp32p4/src/spi1/spi_mem_ctrl2.rs b/esp32p4/src/spi1/spi_mem_ctrl2.rs new file mode 100644 index 0000000000..0f0dae38ac --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_ctrl2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SPI_MEM_CTRL2` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_SYNC_RESET` writer - The FSM will be reset."] +pub type SPI_MEM_SYNC_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 31 - The FSM will be reset."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sync_reset(&mut self) -> SPI_MEM_SYNC_RESET_W { + SPI_MEM_SYNC_RESET_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 control2 register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ctrl2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_CTRL2_SPEC; +impl crate::RegisterSpec for SPI_MEM_CTRL2_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`spi_mem_ctrl2::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_CTRL2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_CTRL2 to value 0"] +impl crate::Resettable for SPI_MEM_CTRL2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_date.rs b/esp32p4/src/spi1/spi_mem_date.rs new file mode 100644 index 0000000000..dd012bf2a5 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_date.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_DATE` reader - Version control register"] +pub type SPI_MEM_DATE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_DATE` writer - Version control register"] +pub type SPI_MEM_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Version control register"] + #[inline(always)] + pub fn spi_mem_date(&self) -> SPI_MEM_DATE_R { + SPI_MEM_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_DATE") + .field( + "spi_mem_date", + &format_args!("{}", self.spi_mem_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Version control register"] + #[inline(always)] + #[must_use] + pub fn spi_mem_date(&mut self) -> SPI_MEM_DATE_W { + SPI_MEM_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_DATE_SPEC; +impl crate::RegisterSpec for SPI_MEM_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_date::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_date::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_DATE to value 0x0211_1240"] +impl crate::Resettable for SPI_MEM_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0211_1240; +} diff --git a/esp32p4/src/spi1/spi_mem_ddr.rs b/esp32p4/src/spi1/spi_mem_ddr.rs new file mode 100644 index 0000000000..e4aebea28c --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_ddr.rs @@ -0,0 +1,313 @@ +#[doc = "Register `SPI_MEM_DDR` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_DDR` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_FMEM_DDR_EN` reader - 1: in ddr mode, 0 in sdr mode"] +pub type SPI_FMEM_DDR_EN_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DDR_EN` writer - 1: in ddr mode, 0 in sdr mode"] +pub type SPI_FMEM_DDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_VAR_DUMMY` reader - Set the bit to enable variable dummy cycle in spi ddr mode."] +pub type SPI_FMEM_VAR_DUMMY_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_VAR_DUMMY` writer - Set the bit to enable variable dummy cycle in spi ddr mode."] +pub type SPI_FMEM_VAR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_DDR_RDAT_SWP` reader - Set the bit to reorder rx data of the word in spi ddr mode."] +pub type SPI_FMEM_DDR_RDAT_SWP_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DDR_RDAT_SWP` writer - Set the bit to reorder rx data of the word in spi ddr mode."] +pub type SPI_FMEM_DDR_RDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_DDR_WDAT_SWP` reader - Set the bit to reorder tx data of the word in spi ddr mode."] +pub type SPI_FMEM_DDR_WDAT_SWP_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DDR_WDAT_SWP` writer - Set the bit to reorder tx data of the word in spi ddr mode."] +pub type SPI_FMEM_DDR_WDAT_SWP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_DDR_CMD_DIS` reader - the bit is used to disable dual edge in command phase when ddr mode."] +pub type SPI_FMEM_DDR_CMD_DIS_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DDR_CMD_DIS` writer - the bit is used to disable dual edge in command phase when ddr mode."] +pub type SPI_FMEM_DDR_CMD_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_OUTMINBYTELEN` reader - It is the minimum output data length in the panda device."] +pub type SPI_FMEM_OUTMINBYTELEN_R = crate::FieldReader; +#[doc = "Field `SPI_FMEM_OUTMINBYTELEN` writer - It is the minimum output data length in the panda device."] +pub type SPI_FMEM_OUTMINBYTELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `SPI_FMEM_USR_DDR_DQS_THD` reader - The delay number of data strobe which from memory based on SPI clock."] +pub type SPI_FMEM_USR_DDR_DQS_THD_R = crate::FieldReader; +#[doc = "Field `SPI_FMEM_USR_DDR_DQS_THD` writer - The delay number of data strobe which from memory based on SPI clock."] +pub type SPI_FMEM_USR_DDR_DQS_THD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP` reader - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] +pub type SPI_FMEM_DDR_DQS_LOOP_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP` writer - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] +pub type SPI_FMEM_DDR_DQS_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_CLK_DIFF_EN` reader - Set this bit to enable the differential SPI_CLK#."] +pub type SPI_FMEM_CLK_DIFF_EN_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_CLK_DIFF_EN` writer - Set this bit to enable the differential SPI_CLK#."] +pub type SPI_FMEM_CLK_DIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_DQS_CA_IN` reader - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] +pub type SPI_FMEM_DQS_CA_IN_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_DQS_CA_IN` writer - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] +pub type SPI_FMEM_DQS_CA_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_HYPERBUS_DUMMY_2X` reader - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] +pub type SPI_FMEM_HYPERBUS_DUMMY_2X_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_HYPERBUS_DUMMY_2X` writer - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] +pub type SPI_FMEM_HYPERBUS_DUMMY_2X_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_CLK_DIFF_INV` reader - Set this bit to invert SPI_DIFF when accesses to flash. ."] +pub type SPI_FMEM_CLK_DIFF_INV_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_CLK_DIFF_INV` writer - Set this bit to invert SPI_DIFF when accesses to flash. ."] +pub type SPI_FMEM_CLK_DIFF_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_OCTA_RAM_ADDR` reader - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] +pub type SPI_FMEM_OCTA_RAM_ADDR_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_OCTA_RAM_ADDR` writer - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] +pub type SPI_FMEM_OCTA_RAM_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FMEM_HYPERBUS_CA` reader - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] +pub type SPI_FMEM_HYPERBUS_CA_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_HYPERBUS_CA` writer - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] +pub type SPI_FMEM_HYPERBUS_CA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: in ddr mode, 0 in sdr mode"] + #[inline(always)] + pub fn spi_fmem_ddr_en(&self) -> SPI_FMEM_DDR_EN_R { + SPI_FMEM_DDR_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in spi ddr mode."] + #[inline(always)] + pub fn spi_fmem_var_dummy(&self) -> SPI_FMEM_VAR_DUMMY_R { + SPI_FMEM_VAR_DUMMY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set the bit to reorder rx data of the word in spi ddr mode."] + #[inline(always)] + pub fn spi_fmem_ddr_rdat_swp(&self) -> SPI_FMEM_DDR_RDAT_SWP_R { + SPI_FMEM_DDR_RDAT_SWP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set the bit to reorder tx data of the word in spi ddr mode."] + #[inline(always)] + pub fn spi_fmem_ddr_wdat_swp(&self) -> SPI_FMEM_DDR_WDAT_SWP_R { + SPI_FMEM_DDR_WDAT_SWP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - the bit is used to disable dual edge in command phase when ddr mode."] + #[inline(always)] + pub fn spi_fmem_ddr_cmd_dis(&self) -> SPI_FMEM_DDR_CMD_DIS_R { + SPI_FMEM_DDR_CMD_DIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:11 - It is the minimum output data length in the panda device."] + #[inline(always)] + pub fn spi_fmem_outminbytelen(&self) -> SPI_FMEM_OUTMINBYTELEN_R { + SPI_FMEM_OUTMINBYTELEN_R::new(((self.bits >> 5) & 0x7f) as u8) + } + #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI clock."] + #[inline(always)] + pub fn spi_fmem_usr_ddr_dqs_thd(&self) -> SPI_FMEM_USR_DDR_DQS_THD_R { + SPI_FMEM_USR_DDR_DQS_THD_R::new(((self.bits >> 14) & 0x7f) as u8) + } + #[doc = "Bit 21 - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] + #[inline(always)] + pub fn spi_fmem_ddr_dqs_loop(&self) -> SPI_FMEM_DDR_DQS_LOOP_R { + SPI_FMEM_DDR_DQS_LOOP_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."] + #[inline(always)] + pub fn spi_fmem_clk_diff_en(&self) -> SPI_FMEM_CLK_DIFF_EN_R { + SPI_FMEM_CLK_DIFF_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] + #[inline(always)] + pub fn spi_fmem_dqs_ca_in(&self) -> SPI_FMEM_DQS_CA_IN_R { + SPI_FMEM_DQS_CA_IN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] + #[inline(always)] + pub fn spi_fmem_hyperbus_dummy_2x(&self) -> SPI_FMEM_HYPERBUS_DUMMY_2X_R { + SPI_FMEM_HYPERBUS_DUMMY_2X_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. ."] + #[inline(always)] + pub fn spi_fmem_clk_diff_inv(&self) -> SPI_FMEM_CLK_DIFF_INV_R { + SPI_FMEM_CLK_DIFF_INV_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] + #[inline(always)] + pub fn spi_fmem_octa_ram_addr(&self) -> SPI_FMEM_OCTA_RAM_ADDR_R { + SPI_FMEM_OCTA_RAM_ADDR_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] + #[inline(always)] + pub fn spi_fmem_hyperbus_ca(&self) -> SPI_FMEM_HYPERBUS_CA_R { + SPI_FMEM_HYPERBUS_CA_R::new(((self.bits >> 30) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_DDR") + .field( + "spi_fmem_ddr_en", + &format_args!("{}", self.spi_fmem_ddr_en().bit()), + ) + .field( + "spi_fmem_var_dummy", + &format_args!("{}", self.spi_fmem_var_dummy().bit()), + ) + .field( + "spi_fmem_ddr_rdat_swp", + &format_args!("{}", self.spi_fmem_ddr_rdat_swp().bit()), + ) + .field( + "spi_fmem_ddr_wdat_swp", + &format_args!("{}", self.spi_fmem_ddr_wdat_swp().bit()), + ) + .field( + "spi_fmem_ddr_cmd_dis", + &format_args!("{}", self.spi_fmem_ddr_cmd_dis().bit()), + ) + .field( + "spi_fmem_outminbytelen", + &format_args!("{}", self.spi_fmem_outminbytelen().bits()), + ) + .field( + "spi_fmem_usr_ddr_dqs_thd", + &format_args!("{}", self.spi_fmem_usr_ddr_dqs_thd().bits()), + ) + .field( + "spi_fmem_ddr_dqs_loop", + &format_args!("{}", self.spi_fmem_ddr_dqs_loop().bit()), + ) + .field( + "spi_fmem_clk_diff_en", + &format_args!("{}", self.spi_fmem_clk_diff_en().bit()), + ) + .field( + "spi_fmem_dqs_ca_in", + &format_args!("{}", self.spi_fmem_dqs_ca_in().bit()), + ) + .field( + "spi_fmem_hyperbus_dummy_2x", + &format_args!("{}", self.spi_fmem_hyperbus_dummy_2x().bit()), + ) + .field( + "spi_fmem_clk_diff_inv", + &format_args!("{}", self.spi_fmem_clk_diff_inv().bit()), + ) + .field( + "spi_fmem_octa_ram_addr", + &format_args!("{}", self.spi_fmem_octa_ram_addr().bit()), + ) + .field( + "spi_fmem_hyperbus_ca", + &format_args!("{}", self.spi_fmem_hyperbus_ca().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: in ddr mode, 0 in sdr mode"] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ddr_en(&mut self) -> SPI_FMEM_DDR_EN_W { + SPI_FMEM_DDR_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in spi ddr mode."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_var_dummy(&mut self) -> SPI_FMEM_VAR_DUMMY_W { + SPI_FMEM_VAR_DUMMY_W::new(self, 1) + } + #[doc = "Bit 2 - Set the bit to reorder rx data of the word in spi ddr mode."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ddr_rdat_swp(&mut self) -> SPI_FMEM_DDR_RDAT_SWP_W { + SPI_FMEM_DDR_RDAT_SWP_W::new(self, 2) + } + #[doc = "Bit 3 - Set the bit to reorder tx data of the word in spi ddr mode."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ddr_wdat_swp(&mut self) -> SPI_FMEM_DDR_WDAT_SWP_W { + SPI_FMEM_DDR_WDAT_SWP_W::new(self, 3) + } + #[doc = "Bit 4 - the bit is used to disable dual edge in command phase when ddr mode."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ddr_cmd_dis(&mut self) -> SPI_FMEM_DDR_CMD_DIS_W { + SPI_FMEM_DDR_CMD_DIS_W::new(self, 4) + } + #[doc = "Bits 5:11 - It is the minimum output data length in the panda device."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_outminbytelen(&mut self) -> SPI_FMEM_OUTMINBYTELEN_W { + SPI_FMEM_OUTMINBYTELEN_W::new(self, 5) + } + #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI clock."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_usr_ddr_dqs_thd(&mut self) -> SPI_FMEM_USR_DDR_DQS_THD_W { + SPI_FMEM_USR_DDR_DQS_THD_W::new(self, 14) + } + #[doc = "Bit 21 - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_ddr_dqs_loop(&mut self) -> SPI_FMEM_DDR_DQS_LOOP_W { + SPI_FMEM_DDR_DQS_LOOP_W::new(self, 21) + } + #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_clk_diff_en(&mut self) -> SPI_FMEM_CLK_DIFF_EN_W { + SPI_FMEM_CLK_DIFF_EN_W::new(self, 24) + } + #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_dqs_ca_in(&mut self) -> SPI_FMEM_DQS_CA_IN_W { + SPI_FMEM_DQS_CA_IN_W::new(self, 26) + } + #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_hyperbus_dummy_2x(&mut self) -> SPI_FMEM_HYPERBUS_DUMMY_2X_W { + SPI_FMEM_HYPERBUS_DUMMY_2X_W::new(self, 27) + } + #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. ."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_clk_diff_inv(&mut self) -> SPI_FMEM_CLK_DIFF_INV_W { + SPI_FMEM_CLK_DIFF_INV_W::new(self, 28) + } + #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_octa_ram_addr(&mut self) -> SPI_FMEM_OCTA_RAM_ADDR_W { + SPI_FMEM_OCTA_RAM_ADDR_W::new(self, 29) + } + #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."] + #[inline(always)] + #[must_use] + pub fn spi_fmem_hyperbus_ca(&mut self) -> SPI_FMEM_HYPERBUS_CA_W { + SPI_FMEM_HYPERBUS_CA_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 DDR control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_ddr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_ddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_DDR_SPEC; +impl crate::RegisterSpec for SPI_MEM_DDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_ddr::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_DDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_ddr::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_DDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_DDR to value 0x20"] +impl crate::Resettable for SPI_MEM_DDR_SPEC { + const RESET_VALUE: Self::Ux = 0x20; +} diff --git a/esp32p4/src/spi1/spi_mem_flash_sus_cmd.rs b/esp32p4/src/spi1/spi_mem_flash_sus_cmd.rs new file mode 100644 index 0000000000..aeee38ff33 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_flash_sus_cmd.rs @@ -0,0 +1,89 @@ +#[doc = "Register `SPI_MEM_FLASH_SUS_CMD` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_FLASH_SUS_CMD` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_FLASH_PES_COMMAND` reader - Program/Erase suspend command."] +pub type SPI_MEM_FLASH_PES_COMMAND_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_FLASH_PES_COMMAND` writer - Program/Erase suspend command."] +pub type SPI_MEM_FLASH_PES_COMMAND_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SPI_MEM_WAIT_PESR_COMMAND` reader - Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash."] +pub type SPI_MEM_WAIT_PESR_COMMAND_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_WAIT_PESR_COMMAND` writer - Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash."] +pub type SPI_MEM_WAIT_PESR_COMMAND_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Program/Erase suspend command."] + #[inline(always)] + pub fn spi_mem_flash_pes_command(&self) -> SPI_MEM_FLASH_PES_COMMAND_R { + SPI_MEM_FLASH_PES_COMMAND_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash."] + #[inline(always)] + pub fn spi_mem_wait_pesr_command(&self) -> SPI_MEM_WAIT_PESR_COMMAND_R { + SPI_MEM_WAIT_PESR_COMMAND_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_FLASH_SUS_CMD") + .field( + "spi_mem_flash_pes_command", + &format_args!("{}", self.spi_mem_flash_pes_command().bits()), + ) + .field( + "spi_mem_wait_pesr_command", + &format_args!("{}", self.spi_mem_wait_pesr_command().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Program/Erase suspend command."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_pes_command( + &mut self, + ) -> SPI_MEM_FLASH_PES_COMMAND_W { + SPI_MEM_FLASH_PES_COMMAND_W::new(self, 0) + } + #[doc = "Bits 16:31 - Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wait_pesr_command( + &mut self, + ) -> SPI_MEM_WAIT_PESR_COMMAND_W { + SPI_MEM_WAIT_PESR_COMMAND_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 flash suspend command register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_flash_sus_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_flash_sus_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_FLASH_SUS_CMD_SPEC; +impl crate::RegisterSpec for SPI_MEM_FLASH_SUS_CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_flash_sus_cmd::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_FLASH_SUS_CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_flash_sus_cmd::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_FLASH_SUS_CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_FLASH_SUS_CMD to value 0x0005_7575"] +impl crate::Resettable for SPI_MEM_FLASH_SUS_CMD_SPEC { + const RESET_VALUE: Self::Ux = 0x0005_7575; +} diff --git a/esp32p4/src/spi1/spi_mem_flash_sus_ctrl.rs b/esp32p4/src/spi1/spi_mem_flash_sus_ctrl.rs new file mode 100644 index 0000000000..544470e3a4 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_flash_sus_ctrl.rs @@ -0,0 +1,262 @@ +#[doc = "Register `SPI_MEM_FLASH_SUS_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_FLASH_SUS_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_FLASH_PER` reader - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_PER_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_PER` writer - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_PER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_PES` reader - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_PES_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_PES` writer - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] +pub type SPI_MEM_FLASH_PES_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_PER_WAIT_EN` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent."] +pub type SPI_MEM_FLASH_PER_WAIT_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_PER_WAIT_EN` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent."] +pub type SPI_MEM_FLASH_PER_WAIT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_PES_WAIT_EN` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent."] +pub type SPI_MEM_FLASH_PES_WAIT_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_PES_WAIT_EN` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent."] +pub type SPI_MEM_FLASH_PES_WAIT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_PES_PER_EN` reader - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done."] +pub type SPI_MEM_PES_PER_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PES_PER_EN` writer - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done."] +pub type SPI_MEM_PES_PER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_PES_EN` reader - Set this bit to enable Auto-suspending function."] +pub type SPI_MEM_FLASH_PES_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_PES_EN` writer - Set this bit to enable Auto-suspending function."] +pub type SPI_MEM_FLASH_PES_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_PESR_END_MSK` reader - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in\\[15:0\\](only status_in\\[7:0\\] is valid when only one byte of data is read out, status_in\\[15:0\\] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in\\[15:0\\]^ SPI_MEM_PESR_END_MSK\\[15:0\\]."] +pub type SPI_MEM_PESR_END_MSK_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_PESR_END_MSK` writer - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in\\[15:0\\](only status_in\\[7:0\\] is valid when only one byte of data is read out, status_in\\[15:0\\] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in\\[15:0\\]^ SPI_MEM_PESR_END_MSK\\[15:0\\]."] +pub type SPI_MEM_PESR_END_MSK_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SPI_FMEM_RD_SUS_2B` reader - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit"] +pub type SPI_FMEM_RD_SUS_2B_R = crate::BitReader; +#[doc = "Field `SPI_FMEM_RD_SUS_2B` writer - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit"] +pub type SPI_FMEM_RD_SUS_2B_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_PER_END_EN` reader - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0."] +pub type SPI_MEM_PER_END_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PER_END_EN` writer - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0."] +pub type SPI_MEM_PER_END_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_PES_END_EN` reader - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0."] +pub type SPI_MEM_PES_END_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PES_END_EN` writer - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0."] +pub type SPI_MEM_PES_END_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SUS_TIMEOUT_CNT` reader - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT\\[6:0\\] times, it will be treated as check pass."] +pub type SPI_MEM_SUS_TIMEOUT_CNT_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_SUS_TIMEOUT_CNT` writer - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT\\[6:0\\] times, it will be treated as check pass."] +pub type SPI_MEM_SUS_TIMEOUT_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_per(&self) -> SPI_MEM_FLASH_PER_R { + SPI_MEM_FLASH_PER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_flash_pes(&self) -> SPI_MEM_FLASH_PES_R { + SPI_MEM_FLASH_PES_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent."] + #[inline(always)] + pub fn spi_mem_flash_per_wait_en(&self) -> SPI_MEM_FLASH_PER_WAIT_EN_R { + SPI_MEM_FLASH_PER_WAIT_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent."] + #[inline(always)] + pub fn spi_mem_flash_pes_wait_en(&self) -> SPI_MEM_FLASH_PES_WAIT_EN_R { + SPI_MEM_FLASH_PES_WAIT_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done."] + #[inline(always)] + pub fn spi_mem_pes_per_en(&self) -> SPI_MEM_PES_PER_EN_R { + SPI_MEM_PES_PER_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set this bit to enable Auto-suspending function."] + #[inline(always)] + pub fn spi_mem_flash_pes_en(&self) -> SPI_MEM_FLASH_PES_EN_R { + SPI_MEM_FLASH_PES_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:21 - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in\\[15:0\\](only status_in\\[7:0\\] is valid when only one byte of data is read out, status_in\\[15:0\\] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in\\[15:0\\]^ SPI_MEM_PESR_END_MSK\\[15:0\\]."] + #[inline(always)] + pub fn spi_mem_pesr_end_msk(&self) -> SPI_MEM_PESR_END_MSK_R { + SPI_MEM_PESR_END_MSK_R::new(((self.bits >> 6) & 0xffff) as u16) + } + #[doc = "Bit 22 - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit"] + #[inline(always)] + pub fn spi_fmem_rd_sus_2b(&self) -> SPI_FMEM_RD_SUS_2B_R { + SPI_FMEM_RD_SUS_2B_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0."] + #[inline(always)] + pub fn spi_mem_per_end_en(&self) -> SPI_MEM_PER_END_EN_R { + SPI_MEM_PER_END_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0."] + #[inline(always)] + pub fn spi_mem_pes_end_en(&self) -> SPI_MEM_PES_END_EN_R { + SPI_MEM_PES_END_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 25:31 - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT\\[6:0\\] times, it will be treated as check pass."] + #[inline(always)] + pub fn spi_mem_sus_timeout_cnt(&self) -> SPI_MEM_SUS_TIMEOUT_CNT_R { + SPI_MEM_SUS_TIMEOUT_CNT_R::new(((self.bits >> 25) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_FLASH_SUS_CTRL") + .field( + "spi_mem_flash_per", + &format_args!("{}", self.spi_mem_flash_per().bit()), + ) + .field( + "spi_mem_flash_pes", + &format_args!("{}", self.spi_mem_flash_pes().bit()), + ) + .field( + "spi_mem_flash_per_wait_en", + &format_args!("{}", self.spi_mem_flash_per_wait_en().bit()), + ) + .field( + "spi_mem_flash_pes_wait_en", + &format_args!("{}", self.spi_mem_flash_pes_wait_en().bit()), + ) + .field( + "spi_mem_pes_per_en", + &format_args!("{}", self.spi_mem_pes_per_en().bit()), + ) + .field( + "spi_mem_flash_pes_en", + &format_args!("{}", self.spi_mem_flash_pes_en().bit()), + ) + .field( + "spi_mem_pesr_end_msk", + &format_args!("{}", self.spi_mem_pesr_end_msk().bits()), + ) + .field( + "spi_fmem_rd_sus_2b", + &format_args!("{}", self.spi_fmem_rd_sus_2b().bit()), + ) + .field( + "spi_mem_per_end_en", + &format_args!("{}", self.spi_mem_per_end_en().bit()), + ) + .field( + "spi_mem_pes_end_en", + &format_args!("{}", self.spi_mem_pes_end_en().bit()), + ) + .field( + "spi_mem_sus_timeout_cnt", + &format_args!("{}", self.spi_mem_sus_timeout_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_per(&mut self) -> SPI_MEM_FLASH_PER_W { + SPI_MEM_FLASH_PER_W::new(self, 0) + } + #[doc = "Bit 1 - program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_pes(&mut self) -> SPI_MEM_FLASH_PES_W { + SPI_MEM_FLASH_PES_W::new(self, 1) + } + #[doc = "Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_per_wait_en( + &mut self, + ) -> SPI_MEM_FLASH_PER_WAIT_EN_W { + SPI_MEM_FLASH_PER_WAIT_EN_W::new(self, 2) + } + #[doc = "Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_pes_wait_en( + &mut self, + ) -> SPI_MEM_FLASH_PES_WAIT_EN_W { + SPI_MEM_FLASH_PES_WAIT_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done."] + #[inline(always)] + #[must_use] + pub fn spi_mem_pes_per_en(&mut self) -> SPI_MEM_PES_PER_EN_W { + SPI_MEM_PES_PER_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to enable Auto-suspending function."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_pes_en(&mut self) -> SPI_MEM_FLASH_PES_EN_W { + SPI_MEM_FLASH_PES_EN_W::new(self, 5) + } + #[doc = "Bits 6:21 - The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in\\[15:0\\](only status_in\\[7:0\\] is valid when only one byte of data is read out, status_in\\[15:0\\] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in\\[15:0\\]^ SPI_MEM_PESR_END_MSK\\[15:0\\]."] + #[inline(always)] + #[must_use] + pub fn spi_mem_pesr_end_msk(&mut self) -> SPI_MEM_PESR_END_MSK_W { + SPI_MEM_PESR_END_MSK_W::new(self, 6) + } + #[doc = "Bit 22 - 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit"] + #[inline(always)] + #[must_use] + pub fn spi_fmem_rd_sus_2b(&mut self) -> SPI_FMEM_RD_SUS_2B_W { + SPI_FMEM_RD_SUS_2B_W::new(self, 22) + } + #[doc = "Bit 23 - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0."] + #[inline(always)] + #[must_use] + pub fn spi_mem_per_end_en(&mut self) -> SPI_MEM_PER_END_EN_W { + SPI_MEM_PER_END_EN_W::new(self, 23) + } + #[doc = "Bit 24 - 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0."] + #[inline(always)] + #[must_use] + pub fn spi_mem_pes_end_en(&mut self) -> SPI_MEM_PES_END_EN_W { + SPI_MEM_PES_END_EN_W::new(self, 24) + } + #[doc = "Bits 25:31 - When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT\\[6:0\\] times, it will be treated as check pass."] + #[inline(always)] + #[must_use] + pub fn spi_mem_sus_timeout_cnt( + &mut self, + ) -> SPI_MEM_SUS_TIMEOUT_CNT_W { + SPI_MEM_SUS_TIMEOUT_CNT_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 flash suspend control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_flash_sus_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_flash_sus_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_FLASH_SUS_CTRL_SPEC; +impl crate::RegisterSpec for SPI_MEM_FLASH_SUS_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_flash_sus_ctrl::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_FLASH_SUS_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_flash_sus_ctrl::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_FLASH_SUS_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_FLASH_SUS_CTRL to value 0x0800_2000"] +impl crate::Resettable for SPI_MEM_FLASH_SUS_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0800_2000; +} diff --git a/esp32p4/src/spi1/spi_mem_flash_waiti_ctrl.rs b/esp32p4/src/spi1/spi_mem_flash_waiti_ctrl.rs new file mode 100644 index 0000000000..6bd9d17f2d --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_flash_waiti_ctrl.rs @@ -0,0 +1,188 @@ +#[doc = "Register `SPI_MEM_FLASH_WAITI_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_FLASH_WAITI_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_WAITI_EN` reader - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported."] +pub type SPI_MEM_WAITI_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WAITI_EN` writer - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported."] +pub type SPI_MEM_WAITI_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WAITI_DUMMY` reader - The dummy phase enable when wait flash idle (RDSR)"] +pub type SPI_MEM_WAITI_DUMMY_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WAITI_DUMMY` writer - The dummy phase enable when wait flash idle (RDSR)"] +pub type SPI_MEM_WAITI_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WAITI_ADDR_EN` reader - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer."] +pub type SPI_MEM_WAITI_ADDR_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WAITI_ADDR_EN` writer - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer."] +pub type SPI_MEM_WAITI_ADDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WAITI_ADDR_CYCLELEN` reader - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN\\[1:0\\] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared."] +pub type SPI_MEM_WAITI_ADDR_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_WAITI_ADDR_CYCLELEN` writer - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN\\[1:0\\] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared."] +pub type SPI_MEM_WAITI_ADDR_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_MEM_WAITI_CMD_2B` reader - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8."] +pub type SPI_MEM_WAITI_CMD_2B_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WAITI_CMD_2B` writer - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8."] +pub type SPI_MEM_WAITI_CMD_2B_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WAITI_DUMMY_CYCLELEN` reader - The dummy cycle length when wait flash idle(RDSR)."] +pub type SPI_MEM_WAITI_DUMMY_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_WAITI_DUMMY_CYCLELEN` writer - The dummy cycle length when wait flash idle(RDSR)."] +pub type SPI_MEM_WAITI_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_MEM_WAITI_CMD` reader - The command value to wait flash idle(RDSR)."] +pub type SPI_MEM_WAITI_CMD_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_WAITI_CMD` writer - The command value to wait flash idle(RDSR)."] +pub type SPI_MEM_WAITI_CMD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported."] + #[inline(always)] + pub fn spi_mem_waiti_en(&self) -> SPI_MEM_WAITI_EN_R { + SPI_MEM_WAITI_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The dummy phase enable when wait flash idle (RDSR)"] + #[inline(always)] + pub fn spi_mem_waiti_dummy(&self) -> SPI_MEM_WAITI_DUMMY_R { + SPI_MEM_WAITI_DUMMY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer."] + #[inline(always)] + pub fn spi_mem_waiti_addr_en(&self) -> SPI_MEM_WAITI_ADDR_EN_R { + SPI_MEM_WAITI_ADDR_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN\\[1:0\\] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared."] + #[inline(always)] + pub fn spi_mem_waiti_addr_cyclelen(&self) -> SPI_MEM_WAITI_ADDR_CYCLELEN_R { + SPI_MEM_WAITI_ADDR_CYCLELEN_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 9 - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8."] + #[inline(always)] + pub fn spi_mem_waiti_cmd_2b(&self) -> SPI_MEM_WAITI_CMD_2B_R { + SPI_MEM_WAITI_CMD_2B_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:15 - The dummy cycle length when wait flash idle(RDSR)."] + #[inline(always)] + pub fn spi_mem_waiti_dummy_cyclelen(&self) -> SPI_MEM_WAITI_DUMMY_CYCLELEN_R { + SPI_MEM_WAITI_DUMMY_CYCLELEN_R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:31 - The command value to wait flash idle(RDSR)."] + #[inline(always)] + pub fn spi_mem_waiti_cmd(&self) -> SPI_MEM_WAITI_CMD_R { + SPI_MEM_WAITI_CMD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_FLASH_WAITI_CTRL") + .field( + "spi_mem_waiti_en", + &format_args!("{}", self.spi_mem_waiti_en().bit()), + ) + .field( + "spi_mem_waiti_dummy", + &format_args!("{}", self.spi_mem_waiti_dummy().bit()), + ) + .field( + "spi_mem_waiti_addr_en", + &format_args!("{}", self.spi_mem_waiti_addr_en().bit()), + ) + .field( + "spi_mem_waiti_addr_cyclelen", + &format_args!("{}", self.spi_mem_waiti_addr_cyclelen().bits()), + ) + .field( + "spi_mem_waiti_cmd_2b", + &format_args!("{}", self.spi_mem_waiti_cmd_2b().bit()), + ) + .field( + "spi_mem_waiti_dummy_cyclelen", + &format_args!("{}", self.spi_mem_waiti_dummy_cyclelen().bits()), + ) + .field( + "spi_mem_waiti_cmd", + &format_args!("{}", self.spi_mem_waiti_cmd().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported."] + #[inline(always)] + #[must_use] + pub fn spi_mem_waiti_en(&mut self) -> SPI_MEM_WAITI_EN_W { + SPI_MEM_WAITI_EN_W::new(self, 0) + } + #[doc = "Bit 1 - The dummy phase enable when wait flash idle (RDSR)"] + #[inline(always)] + #[must_use] + pub fn spi_mem_waiti_dummy(&mut self) -> SPI_MEM_WAITI_DUMMY_W { + SPI_MEM_WAITI_DUMMY_W::new(self, 1) + } + #[doc = "Bit 2 - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer."] + #[inline(always)] + #[must_use] + pub fn spi_mem_waiti_addr_en( + &mut self, + ) -> SPI_MEM_WAITI_ADDR_EN_W { + SPI_MEM_WAITI_ADDR_EN_W::new(self, 2) + } + #[doc = "Bits 3:4 - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN\\[1:0\\] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared."] + #[inline(always)] + #[must_use] + pub fn spi_mem_waiti_addr_cyclelen( + &mut self, + ) -> SPI_MEM_WAITI_ADDR_CYCLELEN_W { + SPI_MEM_WAITI_ADDR_CYCLELEN_W::new(self, 3) + } + #[doc = "Bit 9 - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8."] + #[inline(always)] + #[must_use] + pub fn spi_mem_waiti_cmd_2b( + &mut self, + ) -> SPI_MEM_WAITI_CMD_2B_W { + SPI_MEM_WAITI_CMD_2B_W::new(self, 9) + } + #[doc = "Bits 10:15 - The dummy cycle length when wait flash idle(RDSR)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_waiti_dummy_cyclelen( + &mut self, + ) -> SPI_MEM_WAITI_DUMMY_CYCLELEN_W { + SPI_MEM_WAITI_DUMMY_CYCLELEN_W::new(self, 10) + } + #[doc = "Bits 16:31 - The command value to wait flash idle(RDSR)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_waiti_cmd(&mut self) -> SPI_MEM_WAITI_CMD_W { + SPI_MEM_WAITI_CMD_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 wait idle control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_flash_waiti_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_flash_waiti_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_FLASH_WAITI_CTRL_SPEC; +impl crate::RegisterSpec for SPI_MEM_FLASH_WAITI_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_flash_waiti_ctrl::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_FLASH_WAITI_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_flash_waiti_ctrl::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_FLASH_WAITI_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_FLASH_WAITI_CTRL to value 0x0005_0001"] +impl crate::Resettable for SPI_MEM_FLASH_WAITI_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0005_0001; +} diff --git a/esp32p4/src/spi1/spi_mem_int_clr.rs b/esp32p4/src/spi1/spi_mem_int_clr.rs new file mode 100644 index 0000000000..bc51d00a6b --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_int_clr.rs @@ -0,0 +1,88 @@ +#[doc = "Register `SPI_MEM_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_PER_END_INT_CLR` writer - The clear bit for SPI_MEM_PER_END_INT interrupt."] +pub type SPI_MEM_PER_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_PES_END_INT_CLR` writer - The clear bit for SPI_MEM_PES_END_INT interrupt."] +pub type SPI_MEM_PES_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WPE_END_INT_CLR` writer - The clear bit for SPI_MEM_WPE_END_INT interrupt."] +pub type SPI_MEM_WPE_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_CLR` writer - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt."] +pub type SPI_MEM_SLV_ST_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_CLR` writer - The clear bit for SPI_MEM_MST_ST_END_INT interrupt."] +pub type SPI_MEM_MST_ST_END_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_BROWN_OUT_INT_CLR` writer - The status bit for SPI_MEM_BROWN_OUT_INT interrupt."] +pub type SPI_MEM_BROWN_OUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - The clear bit for SPI_MEM_PER_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_per_end_int_clr(&mut self) -> SPI_MEM_PER_END_INT_CLR_W { + SPI_MEM_PER_END_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - The clear bit for SPI_MEM_PES_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_pes_end_int_clr(&mut self) -> SPI_MEM_PES_END_INT_CLR_W { + SPI_MEM_PES_END_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - The clear bit for SPI_MEM_WPE_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wpe_end_int_clr(&mut self) -> SPI_MEM_WPE_END_INT_CLR_W { + SPI_MEM_WPE_END_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_slv_st_end_int_clr( + &mut self, + ) -> SPI_MEM_SLV_ST_END_INT_CLR_W { + SPI_MEM_SLV_ST_END_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - The clear bit for SPI_MEM_MST_ST_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_mst_st_end_int_clr( + &mut self, + ) -> SPI_MEM_MST_ST_END_INT_CLR_W { + SPI_MEM_MST_ST_END_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 10 - The status bit for SPI_MEM_BROWN_OUT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_brown_out_int_clr( + &mut self, + ) -> SPI_MEM_BROWN_OUT_INT_CLR_W { + SPI_MEM_BROWN_OUT_INT_CLR_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_INT_CLR_SPEC; +impl crate::RegisterSpec for SPI_MEM_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`spi_mem_int_clr::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_INT_CLR to value 0"] +impl crate::Resettable for SPI_MEM_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_int_ena.rs b/esp32p4/src/spi1/spi_mem_int_ena.rs new file mode 100644 index 0000000000..4e713fad93 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_int_ena.rs @@ -0,0 +1,167 @@ +#[doc = "Register `SPI_MEM_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_PER_END_INT_ENA` reader - The enable bit for SPI_MEM_PER_END_INT interrupt."] +pub type SPI_MEM_PER_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PER_END_INT_ENA` writer - The enable bit for SPI_MEM_PER_END_INT interrupt."] +pub type SPI_MEM_PER_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_PES_END_INT_ENA` reader - The enable bit for SPI_MEM_PES_END_INT interrupt."] +pub type SPI_MEM_PES_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PES_END_INT_ENA` writer - The enable bit for SPI_MEM_PES_END_INT interrupt."] +pub type SPI_MEM_PES_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WPE_END_INT_ENA` reader - The enable bit for SPI_MEM_WPE_END_INT interrupt."] +pub type SPI_MEM_WPE_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WPE_END_INT_ENA` writer - The enable bit for SPI_MEM_WPE_END_INT interrupt."] +pub type SPI_MEM_WPE_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_ENA` reader - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."] +pub type SPI_MEM_SLV_ST_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_ENA` writer - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."] +pub type SPI_MEM_SLV_ST_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_ENA` reader - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."] +pub type SPI_MEM_MST_ST_END_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_ENA` writer - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."] +pub type SPI_MEM_MST_ST_END_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_BROWN_OUT_INT_ENA` reader - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."] +pub type SPI_MEM_BROWN_OUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MEM_BROWN_OUT_INT_ENA` writer - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."] +pub type SPI_MEM_BROWN_OUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_per_end_int_ena(&self) -> SPI_MEM_PER_END_INT_ENA_R { + SPI_MEM_PER_END_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The enable bit for SPI_MEM_PES_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_pes_end_int_ena(&self) -> SPI_MEM_PES_END_INT_ENA_R { + SPI_MEM_PES_END_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The enable bit for SPI_MEM_WPE_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_wpe_end_int_ena(&self) -> SPI_MEM_WPE_END_INT_ENA_R { + SPI_MEM_WPE_END_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_slv_st_end_int_ena(&self) -> SPI_MEM_SLV_ST_END_INT_ENA_R { + SPI_MEM_SLV_ST_END_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_mst_st_end_int_ena(&self) -> SPI_MEM_MST_ST_END_INT_ENA_R { + SPI_MEM_MST_ST_END_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 10 - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."] + #[inline(always)] + pub fn spi_mem_brown_out_int_ena(&self) -> SPI_MEM_BROWN_OUT_INT_ENA_R { + SPI_MEM_BROWN_OUT_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_INT_ENA") + .field( + "spi_mem_per_end_int_ena", + &format_args!("{}", self.spi_mem_per_end_int_ena().bit()), + ) + .field( + "spi_mem_pes_end_int_ena", + &format_args!("{}", self.spi_mem_pes_end_int_ena().bit()), + ) + .field( + "spi_mem_wpe_end_int_ena", + &format_args!("{}", self.spi_mem_wpe_end_int_ena().bit()), + ) + .field( + "spi_mem_slv_st_end_int_ena", + &format_args!("{}", self.spi_mem_slv_st_end_int_ena().bit()), + ) + .field( + "spi_mem_mst_st_end_int_ena", + &format_args!("{}", self.spi_mem_mst_st_end_int_ena().bit()), + ) + .field( + "spi_mem_brown_out_int_ena", + &format_args!("{}", self.spi_mem_brown_out_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_per_end_int_ena(&mut self) -> SPI_MEM_PER_END_INT_ENA_W { + SPI_MEM_PER_END_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The enable bit for SPI_MEM_PES_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_pes_end_int_ena(&mut self) -> SPI_MEM_PES_END_INT_ENA_W { + SPI_MEM_PES_END_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The enable bit for SPI_MEM_WPE_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wpe_end_int_ena(&mut self) -> SPI_MEM_WPE_END_INT_ENA_W { + SPI_MEM_WPE_END_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_slv_st_end_int_ena( + &mut self, + ) -> SPI_MEM_SLV_ST_END_INT_ENA_W { + SPI_MEM_SLV_ST_END_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_mst_st_end_int_ena( + &mut self, + ) -> SPI_MEM_MST_ST_END_INT_ENA_W { + SPI_MEM_MST_ST_END_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 10 - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mem_brown_out_int_ena( + &mut self, + ) -> SPI_MEM_BROWN_OUT_INT_ENA_W { + SPI_MEM_BROWN_OUT_INT_ENA_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_INT_ENA_SPEC; +impl crate::RegisterSpec for SPI_MEM_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_int_ena::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_int_ena::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_INT_ENA to value 0"] +impl crate::Resettable for SPI_MEM_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_int_raw.rs b/esp32p4/src/spi1/spi_mem_int_raw.rs new file mode 100644 index 0000000000..360d84ae76 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_int_raw.rs @@ -0,0 +1,167 @@ +#[doc = "Register `SPI_MEM_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_PER_END_INT_RAW` reader - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others."] +pub type SPI_MEM_PER_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PER_END_INT_RAW` writer - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others."] +pub type SPI_MEM_PER_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_PES_END_INT_RAW` reader - The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others."] +pub type SPI_MEM_PES_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PES_END_INT_RAW` writer - The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others."] +pub type SPI_MEM_PES_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WPE_END_INT_RAW` reader - The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others."] +pub type SPI_MEM_WPE_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WPE_END_INT_RAW` writer - The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others."] +pub type SPI_MEM_WPE_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_RAW` reader - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"] +pub type SPI_MEM_SLV_ST_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_RAW` writer - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"] +pub type SPI_MEM_SLV_ST_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_RAW` reader - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others."] +pub type SPI_MEM_MST_ST_END_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_RAW` writer - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others."] +pub type SPI_MEM_MST_ST_END_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_BROWN_OUT_INT_RAW` reader - The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others."] +pub type SPI_MEM_BROWN_OUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MEM_BROWN_OUT_INT_RAW` writer - The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others."] +pub type SPI_MEM_BROWN_OUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others."] + #[inline(always)] + pub fn spi_mem_per_end_int_raw(&self) -> SPI_MEM_PER_END_INT_RAW_R { + SPI_MEM_PER_END_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others."] + #[inline(always)] + pub fn spi_mem_pes_end_int_raw(&self) -> SPI_MEM_PES_END_INT_RAW_R { + SPI_MEM_PES_END_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others."] + #[inline(always)] + pub fn spi_mem_wpe_end_int_raw(&self) -> SPI_MEM_WPE_END_INT_RAW_R { + SPI_MEM_WPE_END_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"] + #[inline(always)] + pub fn spi_mem_slv_st_end_int_raw(&self) -> SPI_MEM_SLV_ST_END_INT_RAW_R { + SPI_MEM_SLV_ST_END_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others."] + #[inline(always)] + pub fn spi_mem_mst_st_end_int_raw(&self) -> SPI_MEM_MST_ST_END_INT_RAW_R { + SPI_MEM_MST_ST_END_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 10 - The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others."] + #[inline(always)] + pub fn spi_mem_brown_out_int_raw(&self) -> SPI_MEM_BROWN_OUT_INT_RAW_R { + SPI_MEM_BROWN_OUT_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_INT_RAW") + .field( + "spi_mem_per_end_int_raw", + &format_args!("{}", self.spi_mem_per_end_int_raw().bit()), + ) + .field( + "spi_mem_pes_end_int_raw", + &format_args!("{}", self.spi_mem_pes_end_int_raw().bit()), + ) + .field( + "spi_mem_wpe_end_int_raw", + &format_args!("{}", self.spi_mem_wpe_end_int_raw().bit()), + ) + .field( + "spi_mem_slv_st_end_int_raw", + &format_args!("{}", self.spi_mem_slv_st_end_int_raw().bit()), + ) + .field( + "spi_mem_mst_st_end_int_raw", + &format_args!("{}", self.spi_mem_mst_st_end_int_raw().bit()), + ) + .field( + "spi_mem_brown_out_int_raw", + &format_args!("{}", self.spi_mem_brown_out_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_per_end_int_raw(&mut self) -> SPI_MEM_PER_END_INT_RAW_W { + SPI_MEM_PER_END_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_pes_end_int_raw(&mut self) -> SPI_MEM_PES_END_INT_RAW_W { + SPI_MEM_PES_END_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wpe_end_int_raw(&mut self) -> SPI_MEM_WPE_END_INT_RAW_W { + SPI_MEM_WPE_END_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"] + #[inline(always)] + #[must_use] + pub fn spi_mem_slv_st_end_int_raw( + &mut self, + ) -> SPI_MEM_SLV_ST_END_INT_RAW_W { + SPI_MEM_SLV_ST_END_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_mst_st_end_int_raw( + &mut self, + ) -> SPI_MEM_MST_ST_END_INT_RAW_W { + SPI_MEM_MST_ST_END_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 10 - The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mem_brown_out_int_raw( + &mut self, + ) -> SPI_MEM_BROWN_OUT_INT_RAW_W { + SPI_MEM_BROWN_OUT_INT_RAW_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_INT_RAW_SPEC; +impl crate::RegisterSpec for SPI_MEM_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_int_raw::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_int_raw::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_INT_RAW to value 0"] +impl crate::Resettable for SPI_MEM_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_int_st.rs b/esp32p4/src/spi1/spi_mem_int_st.rs new file mode 100644 index 0000000000..3ea74e0d67 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_int_st.rs @@ -0,0 +1,94 @@ +#[doc = "Register `SPI_MEM_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `SPI_MEM_PER_END_INT_ST` reader - The status bit for SPI_MEM_PER_END_INT interrupt."] +pub type SPI_MEM_PER_END_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_PES_END_INT_ST` reader - The status bit for SPI_MEM_PES_END_INT interrupt."] +pub type SPI_MEM_PES_END_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WPE_END_INT_ST` reader - The status bit for SPI_MEM_WPE_END_INT interrupt."] +pub type SPI_MEM_WPE_END_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SLV_ST_END_INT_ST` reader - The status bit for SPI_MEM_SLV_ST_END_INT interrupt."] +pub type SPI_MEM_SLV_ST_END_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_MST_ST_END_INT_ST` reader - The status bit for SPI_MEM_MST_ST_END_INT interrupt."] +pub type SPI_MEM_MST_ST_END_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MEM_BROWN_OUT_INT_ST` reader - The status bit for SPI_MEM_BROWN_OUT_INT interrupt."] +pub type SPI_MEM_BROWN_OUT_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The status bit for SPI_MEM_PER_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_per_end_int_st(&self) -> SPI_MEM_PER_END_INT_ST_R { + SPI_MEM_PER_END_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The status bit for SPI_MEM_PES_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_pes_end_int_st(&self) -> SPI_MEM_PES_END_INT_ST_R { + SPI_MEM_PES_END_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The status bit for SPI_MEM_WPE_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_wpe_end_int_st(&self) -> SPI_MEM_WPE_END_INT_ST_R { + SPI_MEM_WPE_END_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The status bit for SPI_MEM_SLV_ST_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_slv_st_end_int_st(&self) -> SPI_MEM_SLV_ST_END_INT_ST_R { + SPI_MEM_SLV_ST_END_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The status bit for SPI_MEM_MST_ST_END_INT interrupt."] + #[inline(always)] + pub fn spi_mem_mst_st_end_int_st(&self) -> SPI_MEM_MST_ST_END_INT_ST_R { + SPI_MEM_MST_ST_END_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 10 - The status bit for SPI_MEM_BROWN_OUT_INT interrupt."] + #[inline(always)] + pub fn spi_mem_brown_out_int_st(&self) -> SPI_MEM_BROWN_OUT_INT_ST_R { + SPI_MEM_BROWN_OUT_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_INT_ST") + .field( + "spi_mem_per_end_int_st", + &format_args!("{}", self.spi_mem_per_end_int_st().bit()), + ) + .field( + "spi_mem_pes_end_int_st", + &format_args!("{}", self.spi_mem_pes_end_int_st().bit()), + ) + .field( + "spi_mem_wpe_end_int_st", + &format_args!("{}", self.spi_mem_wpe_end_int_st().bit()), + ) + .field( + "spi_mem_slv_st_end_int_st", + &format_args!("{}", self.spi_mem_slv_st_end_int_st().bit()), + ) + .field( + "spi_mem_mst_st_end_int_st", + &format_args!("{}", self.spi_mem_mst_st_end_int_st().bit()), + ) + .field( + "spi_mem_brown_out_int_st", + &format_args!("{}", self.spi_mem_brown_out_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "SPI1 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_INT_ST_SPEC; +impl crate::RegisterSpec for SPI_MEM_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_int_st::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_INT_ST_SPEC {} +#[doc = "`reset()` method sets SPI_MEM_INT_ST to value 0"] +impl crate::Resettable for SPI_MEM_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_misc.rs b/esp32p4/src/spi1/spi_mem_misc.rs new file mode 100644 index 0000000000..201d0f35df --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_misc.rs @@ -0,0 +1,123 @@ +#[doc = "Register `SPI_MEM_MISC` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_MISC` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CS0_DIS` reader - SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on."] +pub type SPI_MEM_CS0_DIS_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CS0_DIS` writer - SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on."] +pub type SPI_MEM_CS0_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_CS1_DIS` reader - SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on."] +pub type SPI_MEM_CS1_DIS_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CS1_DIS` writer - SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on."] +pub type SPI_MEM_CS1_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_CK_IDLE_EDGE` reader - 1: spi clk line is high when idle 0: spi clk line is low when idle"] +pub type SPI_MEM_CK_IDLE_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CK_IDLE_EDGE` writer - 1: spi clk line is high when idle 0: spi clk line is low when idle"] +pub type SPI_MEM_CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_CS_KEEP_ACTIVE` reader - spi cs line keep low when the bit is set."] +pub type SPI_MEM_CS_KEEP_ACTIVE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CS_KEEP_ACTIVE` writer - spi cs line keep low when the bit is set."] +pub type SPI_MEM_CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on."] + #[inline(always)] + pub fn spi_mem_cs0_dis(&self) -> SPI_MEM_CS0_DIS_R { + SPI_MEM_CS0_DIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on."] + #[inline(always)] + pub fn spi_mem_cs1_dis(&self) -> SPI_MEM_CS1_DIS_R { + SPI_MEM_CS1_DIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 9 - 1: spi clk line is high when idle 0: spi clk line is low when idle"] + #[inline(always)] + pub fn spi_mem_ck_idle_edge(&self) -> SPI_MEM_CK_IDLE_EDGE_R { + SPI_MEM_CK_IDLE_EDGE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - spi cs line keep low when the bit is set."] + #[inline(always)] + pub fn spi_mem_cs_keep_active(&self) -> SPI_MEM_CS_KEEP_ACTIVE_R { + SPI_MEM_CS_KEEP_ACTIVE_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_MISC") + .field( + "spi_mem_cs0_dis", + &format_args!("{}", self.spi_mem_cs0_dis().bit()), + ) + .field( + "spi_mem_cs1_dis", + &format_args!("{}", self.spi_mem_cs1_dis().bit()), + ) + .field( + "spi_mem_ck_idle_edge", + &format_args!("{}", self.spi_mem_ck_idle_edge().bit()), + ) + .field( + "spi_mem_cs_keep_active", + &format_args!("{}", self.spi_mem_cs_keep_active().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cs0_dis(&mut self) -> SPI_MEM_CS0_DIS_W { + SPI_MEM_CS0_DIS_W::new(self, 0) + } + #[doc = "Bit 1 - SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cs1_dis(&mut self) -> SPI_MEM_CS1_DIS_W { + SPI_MEM_CS1_DIS_W::new(self, 1) + } + #[doc = "Bit 9 - 1: spi clk line is high when idle 0: spi clk line is low when idle"] + #[inline(always)] + #[must_use] + pub fn spi_mem_ck_idle_edge(&mut self) -> SPI_MEM_CK_IDLE_EDGE_W { + SPI_MEM_CK_IDLE_EDGE_W::new(self, 9) + } + #[doc = "Bit 10 - spi cs line keep low when the bit is set."] + #[inline(always)] + #[must_use] + pub fn spi_mem_cs_keep_active(&mut self) -> SPI_MEM_CS_KEEP_ACTIVE_W { + SPI_MEM_CS_KEEP_ACTIVE_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 misc register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_misc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_misc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_MISC_SPEC; +impl crate::RegisterSpec for SPI_MEM_MISC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_misc::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_MISC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_misc::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_MISC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_MISC to value 0x02"] +impl crate::Resettable for SPI_MEM_MISC_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/spi1/spi_mem_miso_dlen.rs b/esp32p4/src/spi1/spi_mem_miso_dlen.rs new file mode 100644 index 0000000000..af02f9ee27 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_miso_dlen.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SPI_MEM_MISO_DLEN` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_MISO_DLEN` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_USR_MISO_DBITLEN` reader - The length in bits of read-data. The register value shall be (bit_num-1)."] +pub type SPI_MEM_USR_MISO_DBITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_MISO_DBITLEN` writer - The length in bits of read-data. The register value shall be (bit_num-1)."] +pub type SPI_MEM_USR_MISO_DBITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - The length in bits of read-data. The register value shall be (bit_num-1)."] + #[inline(always)] + pub fn spi_mem_usr_miso_dbitlen(&self) -> SPI_MEM_USR_MISO_DBITLEN_R { + SPI_MEM_USR_MISO_DBITLEN_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_MISO_DLEN") + .field( + "spi_mem_usr_miso_dbitlen", + &format_args!("{}", self.spi_mem_usr_miso_dbitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - The length in bits of read-data. The register value shall be (bit_num-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_miso_dbitlen( + &mut self, + ) -> SPI_MEM_USR_MISO_DBITLEN_W { + SPI_MEM_USR_MISO_DBITLEN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 receive data bit length control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_miso_dlen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_miso_dlen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_MISO_DLEN_SPEC; +impl crate::RegisterSpec for SPI_MEM_MISO_DLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_miso_dlen::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_MISO_DLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_miso_dlen::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_MISO_DLEN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_MISO_DLEN to value 0"] +impl crate::Resettable for SPI_MEM_MISO_DLEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_mosi_dlen.rs b/esp32p4/src/spi1/spi_mem_mosi_dlen.rs new file mode 100644 index 0000000000..09e4aee567 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_mosi_dlen.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SPI_MEM_MOSI_DLEN` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_MOSI_DLEN` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_USR_MOSI_DBITLEN` reader - The length in bits of write-data. The register value shall be (bit_num-1)."] +pub type SPI_MEM_USR_MOSI_DBITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_MOSI_DBITLEN` writer - The length in bits of write-data. The register value shall be (bit_num-1)."] +pub type SPI_MEM_USR_MOSI_DBITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - The length in bits of write-data. The register value shall be (bit_num-1)."] + #[inline(always)] + pub fn spi_mem_usr_mosi_dbitlen(&self) -> SPI_MEM_USR_MOSI_DBITLEN_R { + SPI_MEM_USR_MOSI_DBITLEN_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_MOSI_DLEN") + .field( + "spi_mem_usr_mosi_dbitlen", + &format_args!("{}", self.spi_mem_usr_mosi_dbitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - The length in bits of write-data. The register value shall be (bit_num-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_mosi_dbitlen( + &mut self, + ) -> SPI_MEM_USR_MOSI_DBITLEN_W { + SPI_MEM_USR_MOSI_DBITLEN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 send data bit length control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_mosi_dlen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_mosi_dlen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_MOSI_DLEN_SPEC; +impl crate::RegisterSpec for SPI_MEM_MOSI_DLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_mosi_dlen::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_MOSI_DLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_mosi_dlen::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_MOSI_DLEN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_MOSI_DLEN to value 0"] +impl crate::Resettable for SPI_MEM_MOSI_DLEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_rd_status.rs b/esp32p4/src/spi1/spi_mem_rd_status.rs new file mode 100644 index 0000000000..9c88ebef3d --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_rd_status.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SPI_MEM_RD_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_RD_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_STATUS` reader - The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit."] +pub type SPI_MEM_STATUS_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_STATUS` writer - The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit."] +pub type SPI_MEM_STATUS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SPI_MEM_WB_MODE` reader - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."] +pub type SPI_MEM_WB_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_WB_MODE` writer - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."] +pub type SPI_MEM_WB_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:15 - The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit."] + #[inline(always)] + pub fn spi_mem_status(&self) -> SPI_MEM_STATUS_R { + SPI_MEM_STATUS_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."] + #[inline(always)] + pub fn spi_mem_wb_mode(&self) -> SPI_MEM_WB_MODE_R { + SPI_MEM_WB_MODE_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_RD_STATUS") + .field( + "spi_mem_status", + &format_args!("{}", self.spi_mem_status().bits()), + ) + .field( + "spi_mem_wb_mode", + &format_args!("{}", self.spi_mem_wb_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit."] + #[inline(always)] + #[must_use] + pub fn spi_mem_status(&mut self) -> SPI_MEM_STATUS_W { + SPI_MEM_STATUS_W::new(self, 0) + } + #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wb_mode(&mut self) -> SPI_MEM_WB_MODE_W { + SPI_MEM_WB_MODE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_rd_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_rd_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_RD_STATUS_SPEC; +impl crate::RegisterSpec for SPI_MEM_RD_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_rd_status::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_RD_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_rd_status::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_RD_STATUS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_RD_STATUS to value 0"] +impl crate::Resettable for SPI_MEM_RD_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_sus_status.rs b/esp32p4/src/spi1/spi_mem_sus_status.rs new file mode 100644 index 0000000000..5325e0d337 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_sus_status.rs @@ -0,0 +1,253 @@ +#[doc = "Register `SPI_MEM_SUS_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_SUS_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_FLASH_SUS` reader - The status of flash suspend, only used in SPI1."] +pub type SPI_MEM_FLASH_SUS_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_SUS` writer - The status of flash suspend, only used in SPI1."] +pub type SPI_MEM_FLASH_SUS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_WAIT_PESR_CMD_2B` reader - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."] +pub type SPI_MEM_WAIT_PESR_CMD_2B_R = crate::BitReader; +#[doc = "Field `SPI_MEM_WAIT_PESR_CMD_2B` writer - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."] +pub type SPI_MEM_WAIT_PESR_CMD_2B_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_HPM_DLY_128` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."] +pub type SPI_MEM_FLASH_HPM_DLY_128_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_HPM_DLY_128` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."] +pub type SPI_MEM_FLASH_HPM_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_RES_DLY_128` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."] +pub type SPI_MEM_FLASH_RES_DLY_128_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_RES_DLY_128` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."] +pub type SPI_MEM_FLASH_RES_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_DP_DLY_128` reader - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."] +pub type SPI_MEM_FLASH_DP_DLY_128_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_DP_DLY_128` writer - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."] +pub type SPI_MEM_FLASH_DP_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_PER_DLY_128` reader - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."] +pub type SPI_MEM_FLASH_PER_DLY_128_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_PER_DLY_128` writer - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."] +pub type SPI_MEM_FLASH_PER_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_PES_DLY_128` reader - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."] +pub type SPI_MEM_FLASH_PES_DLY_128_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_PES_DLY_128` writer - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."] +pub type SPI_MEM_FLASH_PES_DLY_128_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_SPI0_LOCK_EN` reader - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."] +pub type SPI_MEM_SPI0_LOCK_EN_R = crate::BitReader; +#[doc = "Field `SPI_MEM_SPI0_LOCK_EN` writer - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."] +pub type SPI_MEM_SPI0_LOCK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_PESR_CMD_2B` reader - 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8."] +pub type SPI_MEM_FLASH_PESR_CMD_2B_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FLASH_PESR_CMD_2B` writer - 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8."] +pub type SPI_MEM_FLASH_PESR_CMD_2B_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FLASH_PER_COMMAND` reader - Program/Erase resume command."] +pub type SPI_MEM_FLASH_PER_COMMAND_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_FLASH_PER_COMMAND` writer - Program/Erase resume command."] +pub type SPI_MEM_FLASH_PER_COMMAND_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - The status of flash suspend, only used in SPI1."] + #[inline(always)] + pub fn spi_mem_flash_sus(&self) -> SPI_MEM_FLASH_SUS_R { + SPI_MEM_FLASH_SUS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."] + #[inline(always)] + pub fn spi_mem_wait_pesr_cmd_2b(&self) -> SPI_MEM_WAIT_PESR_CMD_2B_R { + SPI_MEM_WAIT_PESR_CMD_2B_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."] + #[inline(always)] + pub fn spi_mem_flash_hpm_dly_128(&self) -> SPI_MEM_FLASH_HPM_DLY_128_R { + SPI_MEM_FLASH_HPM_DLY_128_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."] + #[inline(always)] + pub fn spi_mem_flash_res_dly_128(&self) -> SPI_MEM_FLASH_RES_DLY_128_R { + SPI_MEM_FLASH_RES_DLY_128_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."] + #[inline(always)] + pub fn spi_mem_flash_dp_dly_128(&self) -> SPI_MEM_FLASH_DP_DLY_128_R { + SPI_MEM_FLASH_DP_DLY_128_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."] + #[inline(always)] + pub fn spi_mem_flash_per_dly_128(&self) -> SPI_MEM_FLASH_PER_DLY_128_R { + SPI_MEM_FLASH_PER_DLY_128_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."] + #[inline(always)] + pub fn spi_mem_flash_pes_dly_128(&self) -> SPI_MEM_FLASH_PES_DLY_128_R { + SPI_MEM_FLASH_PES_DLY_128_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."] + #[inline(always)] + pub fn spi_mem_spi0_lock_en(&self) -> SPI_MEM_SPI0_LOCK_EN_R { + SPI_MEM_SPI0_LOCK_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 15 - 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8."] + #[inline(always)] + pub fn spi_mem_flash_pesr_cmd_2b(&self) -> SPI_MEM_FLASH_PESR_CMD_2B_R { + SPI_MEM_FLASH_PESR_CMD_2B_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - Program/Erase resume command."] + #[inline(always)] + pub fn spi_mem_flash_per_command(&self) -> SPI_MEM_FLASH_PER_COMMAND_R { + SPI_MEM_FLASH_PER_COMMAND_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_SUS_STATUS") + .field( + "spi_mem_flash_sus", + &format_args!("{}", self.spi_mem_flash_sus().bit()), + ) + .field( + "spi_mem_wait_pesr_cmd_2b", + &format_args!("{}", self.spi_mem_wait_pesr_cmd_2b().bit()), + ) + .field( + "spi_mem_flash_hpm_dly_128", + &format_args!("{}", self.spi_mem_flash_hpm_dly_128().bit()), + ) + .field( + "spi_mem_flash_res_dly_128", + &format_args!("{}", self.spi_mem_flash_res_dly_128().bit()), + ) + .field( + "spi_mem_flash_dp_dly_128", + &format_args!("{}", self.spi_mem_flash_dp_dly_128().bit()), + ) + .field( + "spi_mem_flash_per_dly_128", + &format_args!("{}", self.spi_mem_flash_per_dly_128().bit()), + ) + .field( + "spi_mem_flash_pes_dly_128", + &format_args!("{}", self.spi_mem_flash_pes_dly_128().bit()), + ) + .field( + "spi_mem_spi0_lock_en", + &format_args!("{}", self.spi_mem_spi0_lock_en().bit()), + ) + .field( + "spi_mem_flash_pesr_cmd_2b", + &format_args!("{}", self.spi_mem_flash_pesr_cmd_2b().bit()), + ) + .field( + "spi_mem_flash_per_command", + &format_args!("{}", self.spi_mem_flash_per_command().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The status of flash suspend, only used in SPI1."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_sus(&mut self) -> SPI_MEM_FLASH_SUS_W { + SPI_MEM_FLASH_SUS_W::new(self, 0) + } + #[doc = "Bit 1 - 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[15:0\\] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND\\[7:0\\] to check SUS/SUS1/SUS2 bit."] + #[inline(always)] + #[must_use] + pub fn spi_mem_wait_pesr_cmd_2b( + &mut self, + ) -> SPI_MEM_WAIT_PESR_CMD_2B_W { + SPI_MEM_WAIT_PESR_CMD_2B_W::new(self, 1) + } + #[doc = "Bit 2 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after HPM command is sent."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_hpm_dly_128( + &mut self, + ) -> SPI_MEM_FLASH_HPM_DLY_128_W { + SPI_MEM_FLASH_HPM_DLY_128_W::new(self, 2) + } + #[doc = "Bit 3 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after RES command is sent."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_res_dly_128( + &mut self, + ) -> SPI_MEM_FLASH_RES_DLY_128_W { + SPI_MEM_FLASH_RES_DLY_128_W::new(self, 3) + } + #[doc = "Bit 4 - 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after DP command is sent."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_dp_dly_128( + &mut self, + ) -> SPI_MEM_FLASH_DP_DLY_128_W { + SPI_MEM_FLASH_DP_DLY_128_W::new(self, 4) + } + #[doc = "Bit 5 - Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PER command is sent."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_per_dly_128( + &mut self, + ) -> SPI_MEM_FLASH_PER_DLY_128_W { + SPI_MEM_FLASH_PER_DLY_128_W::new(self, 5) + } + #[doc = "Bit 6 - Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES\\[9:0\\] * 4) SPI_CLK cycles after PES command is sent."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_pes_dly_128( + &mut self, + ) -> SPI_MEM_FLASH_PES_DLY_128_W { + SPI_MEM_FLASH_PES_DLY_128_W::new(self, 6) + } + #[doc = "Bit 7 - 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it."] + #[inline(always)] + #[must_use] + pub fn spi_mem_spi0_lock_en(&mut self) -> SPI_MEM_SPI0_LOCK_EN_W { + SPI_MEM_SPI0_LOCK_EN_W::new(self, 7) + } + #[doc = "Bit 15 - 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_pesr_cmd_2b( + &mut self, + ) -> SPI_MEM_FLASH_PESR_CMD_2B_W { + SPI_MEM_FLASH_PESR_CMD_2B_W::new(self, 15) + } + #[doc = "Bits 16:31 - Program/Erase resume command."] + #[inline(always)] + #[must_use] + pub fn spi_mem_flash_per_command( + &mut self, + ) -> SPI_MEM_FLASH_PER_COMMAND_W { + SPI_MEM_FLASH_PER_COMMAND_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 flash suspend status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_sus_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_sus_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_SUS_STATUS_SPEC; +impl crate::RegisterSpec for SPI_MEM_SUS_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_sus_status::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_SUS_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_sus_status::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_SUS_STATUS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_SUS_STATUS to value 0x7a7a_0000"] +impl crate::Resettable for SPI_MEM_SUS_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x7a7a_0000; +} diff --git a/esp32p4/src/spi1/spi_mem_timing_cali.rs b/esp32p4/src/spi1/spi_mem_timing_cali.rs new file mode 100644 index 0000000000..4911d1bd0f --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_timing_cali.rs @@ -0,0 +1,87 @@ +#[doc = "Register `SPI_MEM_TIMING_CALI` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_TIMING_CALI` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_TIMING_CALI` reader - The bit is used to enable timing auto-calibration for all reading operations."] +pub type SPI_MEM_TIMING_CALI_R = crate::BitReader; +#[doc = "Field `SPI_MEM_TIMING_CALI` writer - The bit is used to enable timing auto-calibration for all reading operations."] +pub type SPI_MEM_TIMING_CALI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_EXTRA_DUMMY_CYCLELEN` reader - add extra dummy spi clock cycle length for spi clock calibration."] +pub type SPI_MEM_EXTRA_DUMMY_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_EXTRA_DUMMY_CYCLELEN` writer - add extra dummy spi clock cycle length for spi clock calibration."] +pub type SPI_MEM_EXTRA_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."] + #[inline(always)] + pub fn spi_mem_timing_cali(&self) -> SPI_MEM_TIMING_CALI_R { + SPI_MEM_TIMING_CALI_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."] + #[inline(always)] + pub fn spi_mem_extra_dummy_cyclelen(&self) -> SPI_MEM_EXTRA_DUMMY_CYCLELEN_R { + SPI_MEM_EXTRA_DUMMY_CYCLELEN_R::new(((self.bits >> 2) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_TIMING_CALI") + .field( + "spi_mem_timing_cali", + &format_args!("{}", self.spi_mem_timing_cali().bit()), + ) + .field( + "spi_mem_extra_dummy_cyclelen", + &format_args!("{}", self.spi_mem_extra_dummy_cyclelen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."] + #[inline(always)] + #[must_use] + pub fn spi_mem_timing_cali(&mut self) -> SPI_MEM_TIMING_CALI_W { + SPI_MEM_TIMING_CALI_W::new(self, 1) + } + #[doc = "Bits 2:4 - add extra dummy spi clock cycle length for spi clock calibration."] + #[inline(always)] + #[must_use] + pub fn spi_mem_extra_dummy_cyclelen( + &mut self, + ) -> SPI_MEM_EXTRA_DUMMY_CYCLELEN_W { + SPI_MEM_EXTRA_DUMMY_CYCLELEN_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_timing_cali::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_timing_cali::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_TIMING_CALI_SPEC; +impl crate::RegisterSpec for SPI_MEM_TIMING_CALI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_timing_cali::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_TIMING_CALI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_timing_cali::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_TIMING_CALI_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_TIMING_CALI to value 0"] +impl crate::Resettable for SPI_MEM_TIMING_CALI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_tx_crc.rs b/esp32p4/src/spi1/spi_mem_tx_crc.rs new file mode 100644 index 0000000000..908238c066 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_tx_crc.rs @@ -0,0 +1,36 @@ +#[doc = "Register `SPI_MEM_TX_CRC` reader"] +pub type R = crate::R; +#[doc = "Field `DATA` reader - For SPI1, the value of crc32."] +pub type DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - For SPI1, the value of crc32."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_TX_CRC") + .field("data", &format_args!("{}", self.data().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "SPI1 TX CRC data register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_tx_crc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_TX_CRC_SPEC; +impl crate::RegisterSpec for SPI_MEM_TX_CRC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_tx_crc::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_TX_CRC_SPEC {} +#[doc = "`reset()` method sets SPI_MEM_TX_CRC to value 0xffff_ffff"] +impl crate::Resettable for SPI_MEM_TX_CRC_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/spi1/spi_mem_user.rs b/esp32p4/src/spi1/spi_mem_user.rs new file mode 100644 index 0000000000..ce5c606b63 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_user.rs @@ -0,0 +1,294 @@ +#[doc = "Register `SPI_MEM_USER` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_USER` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_CK_OUT_EDGE` reader - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."] +pub type SPI_MEM_CK_OUT_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_CK_OUT_EDGE` writer - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."] +pub type SPI_MEM_CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FWRITE_DUAL` reader - In the write operations read-data phase apply 2 signals"] +pub type SPI_MEM_FWRITE_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FWRITE_DUAL` writer - In the write operations read-data phase apply 2 signals"] +pub type SPI_MEM_FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FWRITE_QUAD` reader - In the write operations read-data phase apply 4 signals"] +pub type SPI_MEM_FWRITE_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FWRITE_QUAD` writer - In the write operations read-data phase apply 4 signals"] +pub type SPI_MEM_FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FWRITE_DIO` reader - In the write operations address phase and read-data phase apply 2 signals."] +pub type SPI_MEM_FWRITE_DIO_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FWRITE_DIO` writer - In the write operations address phase and read-data phase apply 2 signals."] +pub type SPI_MEM_FWRITE_DIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_FWRITE_QIO` reader - In the write operations address phase and read-data phase apply 4 signals."] +pub type SPI_MEM_FWRITE_QIO_R = crate::BitReader; +#[doc = "Field `SPI_MEM_FWRITE_QIO` writer - In the write operations address phase and read-data phase apply 4 signals."] +pub type SPI_MEM_FWRITE_QIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_MISO_HIGHPART` reader - read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."] +pub type SPI_MEM_USR_MISO_HIGHPART_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_MISO_HIGHPART` writer - read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."] +pub type SPI_MEM_USR_MISO_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_MOSI_HIGHPART` reader - write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."] +pub type SPI_MEM_USR_MOSI_HIGHPART_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_MOSI_HIGHPART` writer - write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."] +pub type SPI_MEM_USR_MOSI_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_DUMMY_IDLE` reader - SPI clock is disable in dummy phase when the bit is enable."] +pub type SPI_MEM_USR_DUMMY_IDLE_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_DUMMY_IDLE` writer - SPI clock is disable in dummy phase when the bit is enable."] +pub type SPI_MEM_USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_MOSI` reader - This bit enable the write-data phase of an operation."] +pub type SPI_MEM_USR_MOSI_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_MOSI` writer - This bit enable the write-data phase of an operation."] +pub type SPI_MEM_USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_MISO` reader - This bit enable the read-data phase of an operation."] +pub type SPI_MEM_USR_MISO_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_MISO` writer - This bit enable the read-data phase of an operation."] +pub type SPI_MEM_USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_DUMMY` reader - This bit enable the dummy phase of an operation."] +pub type SPI_MEM_USR_DUMMY_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_DUMMY` writer - This bit enable the dummy phase of an operation."] +pub type SPI_MEM_USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_ADDR` reader - This bit enable the address phase of an operation."] +pub type SPI_MEM_USR_ADDR_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_ADDR` writer - This bit enable the address phase of an operation."] +pub type SPI_MEM_USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MEM_USR_COMMAND` reader - This bit enable the command phase of an operation."] +pub type SPI_MEM_USR_COMMAND_R = crate::BitReader; +#[doc = "Field `SPI_MEM_USR_COMMAND` writer - This bit enable the command phase of an operation."] +pub type SPI_MEM_USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 9 - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."] + #[inline(always)] + pub fn spi_mem_ck_out_edge(&self) -> SPI_MEM_CK_OUT_EDGE_R { + SPI_MEM_CK_OUT_EDGE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals"] + #[inline(always)] + pub fn spi_mem_fwrite_dual(&self) -> SPI_MEM_FWRITE_DUAL_R { + SPI_MEM_FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals"] + #[inline(always)] + pub fn spi_mem_fwrite_quad(&self) -> SPI_MEM_FWRITE_QUAD_R { + SPI_MEM_FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - In the write operations address phase and read-data phase apply 2 signals."] + #[inline(always)] + pub fn spi_mem_fwrite_dio(&self) -> SPI_MEM_FWRITE_DIO_R { + SPI_MEM_FWRITE_DIO_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - In the write operations address phase and read-data phase apply 4 signals."] + #[inline(always)] + pub fn spi_mem_fwrite_qio(&self) -> SPI_MEM_FWRITE_QIO_R { + SPI_MEM_FWRITE_QIO_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_usr_miso_highpart(&self) -> SPI_MEM_USR_MISO_HIGHPART_R { + SPI_MEM_USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."] + #[inline(always)] + pub fn spi_mem_usr_mosi_highpart(&self) -> SPI_MEM_USR_MOSI_HIGHPART_R { + SPI_MEM_USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - SPI clock is disable in dummy phase when the bit is enable."] + #[inline(always)] + pub fn spi_mem_usr_dummy_idle(&self) -> SPI_MEM_USR_DUMMY_IDLE_R { + SPI_MEM_USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - This bit enable the write-data phase of an operation."] + #[inline(always)] + pub fn spi_mem_usr_mosi(&self) -> SPI_MEM_USR_MOSI_R { + SPI_MEM_USR_MOSI_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - This bit enable the read-data phase of an operation."] + #[inline(always)] + pub fn spi_mem_usr_miso(&self) -> SPI_MEM_USR_MISO_R { + SPI_MEM_USR_MISO_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - This bit enable the dummy phase of an operation."] + #[inline(always)] + pub fn spi_mem_usr_dummy(&self) -> SPI_MEM_USR_DUMMY_R { + SPI_MEM_USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - This bit enable the address phase of an operation."] + #[inline(always)] + pub fn spi_mem_usr_addr(&self) -> SPI_MEM_USR_ADDR_R { + SPI_MEM_USR_ADDR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - This bit enable the command phase of an operation."] + #[inline(always)] + pub fn spi_mem_usr_command(&self) -> SPI_MEM_USR_COMMAND_R { + SPI_MEM_USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_USER") + .field( + "spi_mem_ck_out_edge", + &format_args!("{}", self.spi_mem_ck_out_edge().bit()), + ) + .field( + "spi_mem_fwrite_dual", + &format_args!("{}", self.spi_mem_fwrite_dual().bit()), + ) + .field( + "spi_mem_fwrite_quad", + &format_args!("{}", self.spi_mem_fwrite_quad().bit()), + ) + .field( + "spi_mem_fwrite_dio", + &format_args!("{}", self.spi_mem_fwrite_dio().bit()), + ) + .field( + "spi_mem_fwrite_qio", + &format_args!("{}", self.spi_mem_fwrite_qio().bit()), + ) + .field( + "spi_mem_usr_miso_highpart", + &format_args!("{}", self.spi_mem_usr_miso_highpart().bit()), + ) + .field( + "spi_mem_usr_mosi_highpart", + &format_args!("{}", self.spi_mem_usr_mosi_highpart().bit()), + ) + .field( + "spi_mem_usr_dummy_idle", + &format_args!("{}", self.spi_mem_usr_dummy_idle().bit()), + ) + .field( + "spi_mem_usr_mosi", + &format_args!("{}", self.spi_mem_usr_mosi().bit()), + ) + .field( + "spi_mem_usr_miso", + &format_args!("{}", self.spi_mem_usr_miso().bit()), + ) + .field( + "spi_mem_usr_dummy", + &format_args!("{}", self.spi_mem_usr_dummy().bit()), + ) + .field( + "spi_mem_usr_addr", + &format_args!("{}", self.spi_mem_usr_addr().bit()), + ) + .field( + "spi_mem_usr_command", + &format_args!("{}", self.spi_mem_usr_command().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 9 - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."] + #[inline(always)] + #[must_use] + pub fn spi_mem_ck_out_edge(&mut self) -> SPI_MEM_CK_OUT_EDGE_W { + SPI_MEM_CK_OUT_EDGE_W::new(self, 9) + } + #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals"] + #[inline(always)] + #[must_use] + pub fn spi_mem_fwrite_dual(&mut self) -> SPI_MEM_FWRITE_DUAL_W { + SPI_MEM_FWRITE_DUAL_W::new(self, 12) + } + #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals"] + #[inline(always)] + #[must_use] + pub fn spi_mem_fwrite_quad(&mut self) -> SPI_MEM_FWRITE_QUAD_W { + SPI_MEM_FWRITE_QUAD_W::new(self, 13) + } + #[doc = "Bit 14 - In the write operations address phase and read-data phase apply 2 signals."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fwrite_dio(&mut self) -> SPI_MEM_FWRITE_DIO_W { + SPI_MEM_FWRITE_DIO_W::new(self, 14) + } + #[doc = "Bit 15 - In the write operations address phase and read-data phase apply 4 signals."] + #[inline(always)] + #[must_use] + pub fn spi_mem_fwrite_qio(&mut self) -> SPI_MEM_FWRITE_QIO_W { + SPI_MEM_FWRITE_QIO_W::new(self, 15) + } + #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_miso_highpart(&mut self) -> SPI_MEM_USR_MISO_HIGHPART_W { + SPI_MEM_USR_MISO_HIGHPART_W::new(self, 24) + } + #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_mosi_highpart(&mut self) -> SPI_MEM_USR_MOSI_HIGHPART_W { + SPI_MEM_USR_MOSI_HIGHPART_W::new(self, 25) + } + #[doc = "Bit 26 - SPI clock is disable in dummy phase when the bit is enable."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_dummy_idle(&mut self) -> SPI_MEM_USR_DUMMY_IDLE_W { + SPI_MEM_USR_DUMMY_IDLE_W::new(self, 26) + } + #[doc = "Bit 27 - This bit enable the write-data phase of an operation."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_mosi(&mut self) -> SPI_MEM_USR_MOSI_W { + SPI_MEM_USR_MOSI_W::new(self, 27) + } + #[doc = "Bit 28 - This bit enable the read-data phase of an operation."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_miso(&mut self) -> SPI_MEM_USR_MISO_W { + SPI_MEM_USR_MISO_W::new(self, 28) + } + #[doc = "Bit 29 - This bit enable the dummy phase of an operation."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_dummy(&mut self) -> SPI_MEM_USR_DUMMY_W { + SPI_MEM_USR_DUMMY_W::new(self, 29) + } + #[doc = "Bit 30 - This bit enable the address phase of an operation."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_addr(&mut self) -> SPI_MEM_USR_ADDR_W { + SPI_MEM_USR_ADDR_W::new(self, 30) + } + #[doc = "Bit 31 - This bit enable the command phase of an operation."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_command(&mut self) -> SPI_MEM_USR_COMMAND_W { + SPI_MEM_USR_COMMAND_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 user register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_USER_SPEC; +impl crate::RegisterSpec for SPI_MEM_USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_user::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_USER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_user::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_USER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_USER to value 0x8000_0000"] +impl crate::Resettable for SPI_MEM_USER_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_0000; +} diff --git a/esp32p4/src/spi1/spi_mem_user1.rs b/esp32p4/src/spi1/spi_mem_user1.rs new file mode 100644 index 0000000000..c89d734603 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_user1.rs @@ -0,0 +1,87 @@ +#[doc = "Register `SPI_MEM_USER1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_USER1` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_USR_DUMMY_CYCLELEN` reader - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."] +pub type SPI_MEM_USR_DUMMY_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_DUMMY_CYCLELEN` writer - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."] +pub type SPI_MEM_USR_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_MEM_USR_ADDR_BITLEN` reader - The length in bits of address phase. The register value shall be (bit_num-1)."] +pub type SPI_MEM_USR_ADDR_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_ADDR_BITLEN` writer - The length in bits of address phase. The register value shall be (bit_num-1)."] +pub type SPI_MEM_USR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."] + #[inline(always)] + pub fn spi_mem_usr_dummy_cyclelen(&self) -> SPI_MEM_USR_DUMMY_CYCLELEN_R { + SPI_MEM_USR_DUMMY_CYCLELEN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."] + #[inline(always)] + pub fn spi_mem_usr_addr_bitlen(&self) -> SPI_MEM_USR_ADDR_BITLEN_R { + SPI_MEM_USR_ADDR_BITLEN_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_USER1") + .field( + "spi_mem_usr_dummy_cyclelen", + &format_args!("{}", self.spi_mem_usr_dummy_cyclelen().bits()), + ) + .field( + "spi_mem_usr_addr_bitlen", + &format_args!("{}", self.spi_mem_usr_addr_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_dummy_cyclelen( + &mut self, + ) -> SPI_MEM_USR_DUMMY_CYCLELEN_W { + SPI_MEM_USR_DUMMY_CYCLELEN_W::new(self, 0) + } + #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_addr_bitlen(&mut self) -> SPI_MEM_USR_ADDR_BITLEN_W { + SPI_MEM_USR_ADDR_BITLEN_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 user1 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_USER1_SPEC; +impl crate::RegisterSpec for SPI_MEM_USER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_user1::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_USER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_user1::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_USER1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_USER1 to value 0x5c00_0007"] +impl crate::Resettable for SPI_MEM_USER1_SPEC { + const RESET_VALUE: Self::Ux = 0x5c00_0007; +} diff --git a/esp32p4/src/spi1/spi_mem_user2.rs b/esp32p4/src/spi1/spi_mem_user2.rs new file mode 100644 index 0000000000..6c4b161236 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_user2.rs @@ -0,0 +1,87 @@ +#[doc = "Register `SPI_MEM_USER2` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_USER2` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_USR_COMMAND_VALUE` reader - The value of command."] +pub type SPI_MEM_USR_COMMAND_VALUE_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_COMMAND_VALUE` writer - The value of command."] +pub type SPI_MEM_USR_COMMAND_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SPI_MEM_USR_COMMAND_BITLEN` reader - The length in bits of command phase. The register value shall be (bit_num-1)"] +pub type SPI_MEM_USR_COMMAND_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_USR_COMMAND_BITLEN` writer - The length in bits of command phase. The register value shall be (bit_num-1)"] +pub type SPI_MEM_USR_COMMAND_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - The value of command."] + #[inline(always)] + pub fn spi_mem_usr_command_value(&self) -> SPI_MEM_USR_COMMAND_VALUE_R { + SPI_MEM_USR_COMMAND_VALUE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 28:31 - The length in bits of command phase. The register value shall be (bit_num-1)"] + #[inline(always)] + pub fn spi_mem_usr_command_bitlen(&self) -> SPI_MEM_USR_COMMAND_BITLEN_R { + SPI_MEM_USR_COMMAND_BITLEN_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_USER2") + .field( + "spi_mem_usr_command_value", + &format_args!("{}", self.spi_mem_usr_command_value().bits()), + ) + .field( + "spi_mem_usr_command_bitlen", + &format_args!("{}", self.spi_mem_usr_command_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - The value of command."] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_command_value(&mut self) -> SPI_MEM_USR_COMMAND_VALUE_W { + SPI_MEM_USR_COMMAND_VALUE_W::new(self, 0) + } + #[doc = "Bits 28:31 - The length in bits of command phase. The register value shall be (bit_num-1)"] + #[inline(always)] + #[must_use] + pub fn spi_mem_usr_command_bitlen( + &mut self, + ) -> SPI_MEM_USR_COMMAND_BITLEN_W { + SPI_MEM_USR_COMMAND_BITLEN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 user2 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_user2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_user2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_USER2_SPEC; +impl crate::RegisterSpec for SPI_MEM_USER2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_user2::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_USER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_user2::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_USER2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_USER2 to value 0x7000_0000"] +impl crate::Resettable for SPI_MEM_USER2_SPEC { + const RESET_VALUE: Self::Ux = 0x7000_0000; +} diff --git a/esp32p4/src/spi1/spi_mem_w0.rs b/esp32p4/src/spi1/spi_mem_w0.rs new file mode 100644 index 0000000000..cc17f57f39 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W0` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W0` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF0` reader - data buffer"] +pub type SPI_MEM_BUF0_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF0` writer - data buffer"] +pub type SPI_MEM_BUF0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf0(&self) -> SPI_MEM_BUF0_R { + SPI_MEM_BUF0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W0") + .field( + "spi_mem_buf0", + &format_args!("{}", self.spi_mem_buf0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf0(&mut self) -> SPI_MEM_BUF0_W { + SPI_MEM_BUF0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W0_SPEC; +impl crate::RegisterSpec for SPI_MEM_W0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w0::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w0::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W0 to value 0"] +impl crate::Resettable for SPI_MEM_W0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w1.rs b/esp32p4/src/spi1/spi_mem_w1.rs new file mode 100644 index 0000000000..5b697d0a30 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W1` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF1` reader - data buffer"] +pub type SPI_MEM_BUF1_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF1` writer - data buffer"] +pub type SPI_MEM_BUF1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf1(&self) -> SPI_MEM_BUF1_R { + SPI_MEM_BUF1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W1") + .field( + "spi_mem_buf1", + &format_args!("{}", self.spi_mem_buf1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf1(&mut self) -> SPI_MEM_BUF1_W { + SPI_MEM_BUF1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W1_SPEC; +impl crate::RegisterSpec for SPI_MEM_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w1::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w1::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W1 to value 0"] +impl crate::Resettable for SPI_MEM_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w10.rs b/esp32p4/src/spi1/spi_mem_w10.rs new file mode 100644 index 0000000000..d2b4ad1db4 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w10.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W10` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W10` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF10` reader - data buffer"] +pub type SPI_MEM_BUF10_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF10` writer - data buffer"] +pub type SPI_MEM_BUF10_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf10(&self) -> SPI_MEM_BUF10_R { + SPI_MEM_BUF10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W10") + .field( + "spi_mem_buf10", + &format_args!("{}", self.spi_mem_buf10().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf10(&mut self) -> SPI_MEM_BUF10_W { + SPI_MEM_BUF10_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W10_SPEC; +impl crate::RegisterSpec for SPI_MEM_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w10::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w10::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W10_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W10 to value 0"] +impl crate::Resettable for SPI_MEM_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w11.rs b/esp32p4/src/spi1/spi_mem_w11.rs new file mode 100644 index 0000000000..ef3ba699b1 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w11.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W11` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W11` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF11` reader - data buffer"] +pub type SPI_MEM_BUF11_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF11` writer - data buffer"] +pub type SPI_MEM_BUF11_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf11(&self) -> SPI_MEM_BUF11_R { + SPI_MEM_BUF11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W11") + .field( + "spi_mem_buf11", + &format_args!("{}", self.spi_mem_buf11().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf11(&mut self) -> SPI_MEM_BUF11_W { + SPI_MEM_BUF11_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W11_SPEC; +impl crate::RegisterSpec for SPI_MEM_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w11::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w11::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W11_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W11 to value 0"] +impl crate::Resettable for SPI_MEM_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w12.rs b/esp32p4/src/spi1/spi_mem_w12.rs new file mode 100644 index 0000000000..28de189f6b --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w12.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W12` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W12` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF12` reader - data buffer"] +pub type SPI_MEM_BUF12_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF12` writer - data buffer"] +pub type SPI_MEM_BUF12_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf12(&self) -> SPI_MEM_BUF12_R { + SPI_MEM_BUF12_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W12") + .field( + "spi_mem_buf12", + &format_args!("{}", self.spi_mem_buf12().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf12(&mut self) -> SPI_MEM_BUF12_W { + SPI_MEM_BUF12_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W12_SPEC; +impl crate::RegisterSpec for SPI_MEM_W12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w12::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w12::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W12_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W12 to value 0"] +impl crate::Resettable for SPI_MEM_W12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w13.rs b/esp32p4/src/spi1/spi_mem_w13.rs new file mode 100644 index 0000000000..13fd33ed02 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w13.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W13` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W13` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF13` reader - data buffer"] +pub type SPI_MEM_BUF13_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF13` writer - data buffer"] +pub type SPI_MEM_BUF13_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf13(&self) -> SPI_MEM_BUF13_R { + SPI_MEM_BUF13_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W13") + .field( + "spi_mem_buf13", + &format_args!("{}", self.spi_mem_buf13().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf13(&mut self) -> SPI_MEM_BUF13_W { + SPI_MEM_BUF13_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W13_SPEC; +impl crate::RegisterSpec for SPI_MEM_W13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w13::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w13::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W13_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W13 to value 0"] +impl crate::Resettable for SPI_MEM_W13_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w14.rs b/esp32p4/src/spi1/spi_mem_w14.rs new file mode 100644 index 0000000000..5cc6f431b7 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w14.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W14` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W14` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF14` reader - data buffer"] +pub type SPI_MEM_BUF14_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF14` writer - data buffer"] +pub type SPI_MEM_BUF14_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf14(&self) -> SPI_MEM_BUF14_R { + SPI_MEM_BUF14_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W14") + .field( + "spi_mem_buf14", + &format_args!("{}", self.spi_mem_buf14().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf14(&mut self) -> SPI_MEM_BUF14_W { + SPI_MEM_BUF14_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W14_SPEC; +impl crate::RegisterSpec for SPI_MEM_W14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w14::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w14::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W14_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W14 to value 0"] +impl crate::Resettable for SPI_MEM_W14_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w15.rs b/esp32p4/src/spi1/spi_mem_w15.rs new file mode 100644 index 0000000000..0cbc2fd1be --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w15.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W15` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W15` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF15` reader - data buffer"] +pub type SPI_MEM_BUF15_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF15` writer - data buffer"] +pub type SPI_MEM_BUF15_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf15(&self) -> SPI_MEM_BUF15_R { + SPI_MEM_BUF15_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W15") + .field( + "spi_mem_buf15", + &format_args!("{}", self.spi_mem_buf15().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf15(&mut self) -> SPI_MEM_BUF15_W { + SPI_MEM_BUF15_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W15_SPEC; +impl crate::RegisterSpec for SPI_MEM_W15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w15::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w15::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W15_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W15 to value 0"] +impl crate::Resettable for SPI_MEM_W15_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w2.rs b/esp32p4/src/spi1/spi_mem_w2.rs new file mode 100644 index 0000000000..f76b7236e3 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W2` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W2` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF2` reader - data buffer"] +pub type SPI_MEM_BUF2_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF2` writer - data buffer"] +pub type SPI_MEM_BUF2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf2(&self) -> SPI_MEM_BUF2_R { + SPI_MEM_BUF2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W2") + .field( + "spi_mem_buf2", + &format_args!("{}", self.spi_mem_buf2().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf2(&mut self) -> SPI_MEM_BUF2_W { + SPI_MEM_BUF2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W2_SPEC; +impl crate::RegisterSpec for SPI_MEM_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w2::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w2::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W2 to value 0"] +impl crate::Resettable for SPI_MEM_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w3.rs b/esp32p4/src/spi1/spi_mem_w3.rs new file mode 100644 index 0000000000..2785dc3017 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w3.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W3` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W3` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF3` reader - data buffer"] +pub type SPI_MEM_BUF3_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF3` writer - data buffer"] +pub type SPI_MEM_BUF3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf3(&self) -> SPI_MEM_BUF3_R { + SPI_MEM_BUF3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W3") + .field( + "spi_mem_buf3", + &format_args!("{}", self.spi_mem_buf3().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf3(&mut self) -> SPI_MEM_BUF3_W { + SPI_MEM_BUF3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W3_SPEC; +impl crate::RegisterSpec for SPI_MEM_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w3::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w3::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W3 to value 0"] +impl crate::Resettable for SPI_MEM_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w4.rs b/esp32p4/src/spi1/spi_mem_w4.rs new file mode 100644 index 0000000000..07abadaa44 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w4.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W4` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W4` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF4` reader - data buffer"] +pub type SPI_MEM_BUF4_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF4` writer - data buffer"] +pub type SPI_MEM_BUF4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf4(&self) -> SPI_MEM_BUF4_R { + SPI_MEM_BUF4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W4") + .field( + "spi_mem_buf4", + &format_args!("{}", self.spi_mem_buf4().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf4(&mut self) -> SPI_MEM_BUF4_W { + SPI_MEM_BUF4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W4_SPEC; +impl crate::RegisterSpec for SPI_MEM_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w4::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w4::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W4 to value 0"] +impl crate::Resettable for SPI_MEM_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w5.rs b/esp32p4/src/spi1/spi_mem_w5.rs new file mode 100644 index 0000000000..443606c2df --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w5.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W5` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W5` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF5` reader - data buffer"] +pub type SPI_MEM_BUF5_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF5` writer - data buffer"] +pub type SPI_MEM_BUF5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf5(&self) -> SPI_MEM_BUF5_R { + SPI_MEM_BUF5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W5") + .field( + "spi_mem_buf5", + &format_args!("{}", self.spi_mem_buf5().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf5(&mut self) -> SPI_MEM_BUF5_W { + SPI_MEM_BUF5_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W5_SPEC; +impl crate::RegisterSpec for SPI_MEM_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w5::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w5::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W5 to value 0"] +impl crate::Resettable for SPI_MEM_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w6.rs b/esp32p4/src/spi1/spi_mem_w6.rs new file mode 100644 index 0000000000..4afd199fd5 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w6.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W6` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W6` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF6` reader - data buffer"] +pub type SPI_MEM_BUF6_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF6` writer - data buffer"] +pub type SPI_MEM_BUF6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf6(&self) -> SPI_MEM_BUF6_R { + SPI_MEM_BUF6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W6") + .field( + "spi_mem_buf6", + &format_args!("{}", self.spi_mem_buf6().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf6(&mut self) -> SPI_MEM_BUF6_W { + SPI_MEM_BUF6_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W6_SPEC; +impl crate::RegisterSpec for SPI_MEM_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w6::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w6::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W6 to value 0"] +impl crate::Resettable for SPI_MEM_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w7.rs b/esp32p4/src/spi1/spi_mem_w7.rs new file mode 100644 index 0000000000..3b2426072a --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w7.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W7` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W7` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF7` reader - data buffer"] +pub type SPI_MEM_BUF7_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF7` writer - data buffer"] +pub type SPI_MEM_BUF7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf7(&self) -> SPI_MEM_BUF7_R { + SPI_MEM_BUF7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W7") + .field( + "spi_mem_buf7", + &format_args!("{}", self.spi_mem_buf7().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf7(&mut self) -> SPI_MEM_BUF7_W { + SPI_MEM_BUF7_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W7_SPEC; +impl crate::RegisterSpec for SPI_MEM_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w7::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w7::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W7 to value 0"] +impl crate::Resettable for SPI_MEM_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w8.rs b/esp32p4/src/spi1/spi_mem_w8.rs new file mode 100644 index 0000000000..de70aa3e82 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w8.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W8` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W8` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF8` reader - data buffer"] +pub type SPI_MEM_BUF8_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF8` writer - data buffer"] +pub type SPI_MEM_BUF8_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf8(&self) -> SPI_MEM_BUF8_R { + SPI_MEM_BUF8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W8") + .field( + "spi_mem_buf8", + &format_args!("{}", self.spi_mem_buf8().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf8(&mut self) -> SPI_MEM_BUF8_W { + SPI_MEM_BUF8_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W8_SPEC; +impl crate::RegisterSpec for SPI_MEM_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w8::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w8::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W8_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W8 to value 0"] +impl crate::Resettable for SPI_MEM_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi1/spi_mem_w9.rs b/esp32p4/src/spi1/spi_mem_w9.rs new file mode 100644 index 0000000000..6840d996d4 --- /dev/null +++ b/esp32p4/src/spi1/spi_mem_w9.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MEM_W9` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MEM_W9` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MEM_BUF9` reader - data buffer"] +pub type SPI_MEM_BUF9_R = crate::FieldReader; +#[doc = "Field `SPI_MEM_BUF9` writer - data buffer"] +pub type SPI_MEM_BUF9_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_mem_buf9(&self) -> SPI_MEM_BUF9_R { + SPI_MEM_BUF9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MEM_W9") + .field( + "spi_mem_buf9", + &format_args!("{}", self.spi_mem_buf9().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_mem_buf9(&mut self) -> SPI_MEM_BUF9_W { + SPI_MEM_BUF9_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI1 memory data buffer9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_w9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_mem_w9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MEM_W9_SPEC; +impl crate::RegisterSpec for SPI_MEM_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_mem_w9::R`](R) reader structure"] +impl crate::Readable for SPI_MEM_W9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_mem_w9::W`](W) writer structure"] +impl crate::Writable for SPI_MEM_W9_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MEM_W9 to value 0"] +impl crate::Resettable for SPI_MEM_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2.rs b/esp32p4/src/spi2.rs new file mode 100644 index 0000000000..2defae7f74 --- /dev/null +++ b/esp32p4/src/spi2.rs @@ -0,0 +1,390 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + spi_cmd: SPI_CMD, + spi_addr: SPI_ADDR, + spi_ctrl: SPI_CTRL, + spi_clock: SPI_CLOCK, + spi_user: SPI_USER, + spi_user1: SPI_USER1, + spi_user2: SPI_USER2, + spi_ms_dlen: SPI_MS_DLEN, + spi_misc: SPI_MISC, + spi_din_mode: SPI_DIN_MODE, + spi_din_num: SPI_DIN_NUM, + spi_dout_mode: SPI_DOUT_MODE, + spi_dma_conf: SPI_DMA_CONF, + spi_dma_int_ena: SPI_DMA_INT_ENA, + spi_dma_int_clr: SPI_DMA_INT_CLR, + spi_dma_int_raw: SPI_DMA_INT_RAW, + spi_dma_int_st: SPI_DMA_INT_ST, + spi_dma_int_set: SPI_DMA_INT_SET, + _reserved18: [u8; 0x50], + spi_w0: SPI_W0, + spi_w1: SPI_W1, + spi_w2: SPI_W2, + spi_w3: SPI_W3, + spi_w4: SPI_W4, + spi_w5: SPI_W5, + spi_w6: SPI_W6, + spi_w7: SPI_W7, + spi_w8: SPI_W8, + spi_w9: SPI_W9, + spi_w10: SPI_W10, + spi_w11: SPI_W11, + spi_w12: SPI_W12, + spi_w13: SPI_W13, + spi_w14: SPI_W14, + spi_w15: SPI_W15, + _reserved34: [u8; 0x08], + spi_slave: SPI_SLAVE, + spi_slave1: SPI_SLAVE1, + spi_clk_gate: SPI_CLK_GATE, + _reserved37: [u8; 0x04], + spi_date: SPI_DATE, +} +impl RegisterBlock { + #[doc = "0x00 - Command control register"] + #[inline(always)] + pub const fn spi_cmd(&self) -> &SPI_CMD { + &self.spi_cmd + } + #[doc = "0x04 - Address value register"] + #[inline(always)] + pub const fn spi_addr(&self) -> &SPI_ADDR { + &self.spi_addr + } + #[doc = "0x08 - SPI control register"] + #[inline(always)] + pub const fn spi_ctrl(&self) -> &SPI_CTRL { + &self.spi_ctrl + } + #[doc = "0x0c - SPI clock control register"] + #[inline(always)] + pub const fn spi_clock(&self) -> &SPI_CLOCK { + &self.spi_clock + } + #[doc = "0x10 - SPI USER control register"] + #[inline(always)] + pub const fn spi_user(&self) -> &SPI_USER { + &self.spi_user + } + #[doc = "0x14 - SPI USER control register 1"] + #[inline(always)] + pub const fn spi_user1(&self) -> &SPI_USER1 { + &self.spi_user1 + } + #[doc = "0x18 - SPI USER control register 2"] + #[inline(always)] + pub const fn spi_user2(&self) -> &SPI_USER2 { + &self.spi_user2 + } + #[doc = "0x1c - SPI data bit length control register"] + #[inline(always)] + pub const fn spi_ms_dlen(&self) -> &SPI_MS_DLEN { + &self.spi_ms_dlen + } + #[doc = "0x20 - SPI misc register"] + #[inline(always)] + pub const fn spi_misc(&self) -> &SPI_MISC { + &self.spi_misc + } + #[doc = "0x24 - SPI input delay mode configuration"] + #[inline(always)] + pub const fn spi_din_mode(&self) -> &SPI_DIN_MODE { + &self.spi_din_mode + } + #[doc = "0x28 - SPI input delay number configuration"] + #[inline(always)] + pub const fn spi_din_num(&self) -> &SPI_DIN_NUM { + &self.spi_din_num + } + #[doc = "0x2c - SPI output delay mode configuration"] + #[inline(always)] + pub const fn spi_dout_mode(&self) -> &SPI_DOUT_MODE { + &self.spi_dout_mode + } + #[doc = "0x30 - SPI DMA control register"] + #[inline(always)] + pub const fn spi_dma_conf(&self) -> &SPI_DMA_CONF { + &self.spi_dma_conf + } + #[doc = "0x34 - SPI interrupt enable register"] + #[inline(always)] + pub const fn spi_dma_int_ena(&self) -> &SPI_DMA_INT_ENA { + &self.spi_dma_int_ena + } + #[doc = "0x38 - SPI interrupt clear register"] + #[inline(always)] + pub const fn spi_dma_int_clr(&self) -> &SPI_DMA_INT_CLR { + &self.spi_dma_int_clr + } + #[doc = "0x3c - SPI interrupt raw register"] + #[inline(always)] + pub const fn spi_dma_int_raw(&self) -> &SPI_DMA_INT_RAW { + &self.spi_dma_int_raw + } + #[doc = "0x40 - SPI interrupt status register"] + #[inline(always)] + pub const fn spi_dma_int_st(&self) -> &SPI_DMA_INT_ST { + &self.spi_dma_int_st + } + #[doc = "0x44 - SPI interrupt software set register"] + #[inline(always)] + pub const fn spi_dma_int_set(&self) -> &SPI_DMA_INT_SET { + &self.spi_dma_int_set + } + #[doc = "0x98 - SPI CPU-controlled buffer0"] + #[inline(always)] + pub const fn spi_w0(&self) -> &SPI_W0 { + &self.spi_w0 + } + #[doc = "0x9c - SPI CPU-controlled buffer1"] + #[inline(always)] + pub const fn spi_w1(&self) -> &SPI_W1 { + &self.spi_w1 + } + #[doc = "0xa0 - SPI CPU-controlled buffer2"] + #[inline(always)] + pub const fn spi_w2(&self) -> &SPI_W2 { + &self.spi_w2 + } + #[doc = "0xa4 - SPI CPU-controlled buffer3"] + #[inline(always)] + pub const fn spi_w3(&self) -> &SPI_W3 { + &self.spi_w3 + } + #[doc = "0xa8 - SPI CPU-controlled buffer4"] + #[inline(always)] + pub const fn spi_w4(&self) -> &SPI_W4 { + &self.spi_w4 + } + #[doc = "0xac - SPI CPU-controlled buffer5"] + #[inline(always)] + pub const fn spi_w5(&self) -> &SPI_W5 { + &self.spi_w5 + } + #[doc = "0xb0 - SPI CPU-controlled buffer6"] + #[inline(always)] + pub const fn spi_w6(&self) -> &SPI_W6 { + &self.spi_w6 + } + #[doc = "0xb4 - SPI CPU-controlled buffer7"] + #[inline(always)] + pub const fn spi_w7(&self) -> &SPI_W7 { + &self.spi_w7 + } + #[doc = "0xb8 - SPI CPU-controlled buffer8"] + #[inline(always)] + pub const fn spi_w8(&self) -> &SPI_W8 { + &self.spi_w8 + } + #[doc = "0xbc - SPI CPU-controlled buffer9"] + #[inline(always)] + pub const fn spi_w9(&self) -> &SPI_W9 { + &self.spi_w9 + } + #[doc = "0xc0 - SPI CPU-controlled buffer10"] + #[inline(always)] + pub const fn spi_w10(&self) -> &SPI_W10 { + &self.spi_w10 + } + #[doc = "0xc4 - SPI CPU-controlled buffer11"] + #[inline(always)] + pub const fn spi_w11(&self) -> &SPI_W11 { + &self.spi_w11 + } + #[doc = "0xc8 - SPI CPU-controlled buffer12"] + #[inline(always)] + pub const fn spi_w12(&self) -> &SPI_W12 { + &self.spi_w12 + } + #[doc = "0xcc - SPI CPU-controlled buffer13"] + #[inline(always)] + pub const fn spi_w13(&self) -> &SPI_W13 { + &self.spi_w13 + } + #[doc = "0xd0 - SPI CPU-controlled buffer14"] + #[inline(always)] + pub const fn spi_w14(&self) -> &SPI_W14 { + &self.spi_w14 + } + #[doc = "0xd4 - SPI CPU-controlled buffer15"] + #[inline(always)] + pub const fn spi_w15(&self) -> &SPI_W15 { + &self.spi_w15 + } + #[doc = "0xe0 - SPI slave control register"] + #[inline(always)] + pub const fn spi_slave(&self) -> &SPI_SLAVE { + &self.spi_slave + } + #[doc = "0xe4 - SPI slave control register 1"] + #[inline(always)] + pub const fn spi_slave1(&self) -> &SPI_SLAVE1 { + &self.spi_slave1 + } + #[doc = "0xe8 - SPI module clock and register clock control"] + #[inline(always)] + pub const fn spi_clk_gate(&self) -> &SPI_CLK_GATE { + &self.spi_clk_gate + } + #[doc = "0xf0 - Version control"] + #[inline(always)] + pub const fn spi_date(&self) -> &SPI_DATE { + &self.spi_date + } +} +#[doc = "SPI_CMD (rw) register accessor: Command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_cmd`] module"] +pub type SPI_CMD = crate::Reg; +#[doc = "Command control register"] +pub mod spi_cmd; +#[doc = "SPI_ADDR (rw) register accessor: Address value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_addr`] module"] +pub type SPI_ADDR = crate::Reg; +#[doc = "Address value register"] +pub mod spi_addr; +#[doc = "SPI_CTRL (rw) register accessor: SPI control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrl`] module"] +pub type SPI_CTRL = crate::Reg; +#[doc = "SPI control register"] +pub mod spi_ctrl; +#[doc = "SPI_CLOCK (rw) register accessor: SPI clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clock::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_clock`] module"] +pub type SPI_CLOCK = crate::Reg; +#[doc = "SPI clock control register"] +pub mod spi_clock; +#[doc = "SPI_USER (rw) register accessor: SPI USER control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user`] module"] +pub type SPI_USER = crate::Reg; +#[doc = "SPI USER control register"] +pub mod spi_user; +#[doc = "SPI_USER1 (rw) register accessor: SPI USER control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user1`] module"] +pub type SPI_USER1 = crate::Reg; +#[doc = "SPI USER control register 1"] +pub mod spi_user1; +#[doc = "SPI_USER2 (rw) register accessor: SPI USER control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user2`] module"] +pub type SPI_USER2 = crate::Reg; +#[doc = "SPI USER control register 2"] +pub mod spi_user2; +#[doc = "SPI_MS_DLEN (rw) register accessor: SPI data bit length control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ms_dlen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ms_dlen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ms_dlen`] module"] +pub type SPI_MS_DLEN = crate::Reg; +#[doc = "SPI data bit length control register"] +pub mod spi_ms_dlen; +#[doc = "SPI_MISC (rw) register accessor: SPI misc register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_misc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_misc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_misc`] module"] +pub type SPI_MISC = crate::Reg; +#[doc = "SPI misc register"] +pub mod spi_misc; +#[doc = "SPI_DIN_MODE (rw) register accessor: SPI input delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_din_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_din_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_din_mode`] module"] +pub type SPI_DIN_MODE = crate::Reg; +#[doc = "SPI input delay mode configuration"] +pub mod spi_din_mode; +#[doc = "SPI_DIN_NUM (rw) register accessor: SPI input delay number configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_din_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_din_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_din_num`] module"] +pub type SPI_DIN_NUM = crate::Reg; +#[doc = "SPI input delay number configuration"] +pub mod spi_din_num; +#[doc = "SPI_DOUT_MODE (rw) register accessor: SPI output delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dout_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dout_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dout_mode`] module"] +pub type SPI_DOUT_MODE = crate::Reg; +#[doc = "SPI output delay mode configuration"] +pub mod spi_dout_mode; +#[doc = "SPI_DMA_CONF (rw) register accessor: SPI DMA control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_conf`] module"] +pub type SPI_DMA_CONF = crate::Reg; +#[doc = "SPI DMA control register"] +pub mod spi_dma_conf; +#[doc = "SPI_DMA_INT_ENA (rw) register accessor: SPI interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_int_ena`] module"] +pub type SPI_DMA_INT_ENA = crate::Reg; +#[doc = "SPI interrupt enable register"] +pub mod spi_dma_int_ena; +#[doc = "SPI_DMA_INT_CLR (w) register accessor: SPI interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_int_clr`] module"] +pub type SPI_DMA_INT_CLR = crate::Reg; +#[doc = "SPI interrupt clear register"] +pub mod spi_dma_int_clr; +#[doc = "SPI_DMA_INT_RAW (rw) register accessor: SPI interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_int_raw`] module"] +pub type SPI_DMA_INT_RAW = crate::Reg; +#[doc = "SPI interrupt raw register"] +pub mod spi_dma_int_raw; +#[doc = "SPI_DMA_INT_ST (r) register accessor: SPI interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_int_st`] module"] +pub type SPI_DMA_INT_ST = crate::Reg; +#[doc = "SPI interrupt status register"] +pub mod spi_dma_int_st; +#[doc = "SPI_DMA_INT_SET (w) register accessor: SPI interrupt software set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_int_set`] module"] +pub type SPI_DMA_INT_SET = crate::Reg; +#[doc = "SPI interrupt software set register"] +pub mod spi_dma_int_set; +#[doc = "SPI_W0 (rw) register accessor: SPI CPU-controlled buffer0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w0`] module"] +pub type SPI_W0 = crate::Reg; +#[doc = "SPI CPU-controlled buffer0"] +pub mod spi_w0; +#[doc = "SPI_W1 (rw) register accessor: SPI CPU-controlled buffer1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w1`] module"] +pub type SPI_W1 = crate::Reg; +#[doc = "SPI CPU-controlled buffer1"] +pub mod spi_w1; +#[doc = "SPI_W2 (rw) register accessor: SPI CPU-controlled buffer2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w2`] module"] +pub type SPI_W2 = crate::Reg; +#[doc = "SPI CPU-controlled buffer2"] +pub mod spi_w2; +#[doc = "SPI_W3 (rw) register accessor: SPI CPU-controlled buffer3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w3`] module"] +pub type SPI_W3 = crate::Reg; +#[doc = "SPI CPU-controlled buffer3"] +pub mod spi_w3; +#[doc = "SPI_W4 (rw) register accessor: SPI CPU-controlled buffer4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w4`] module"] +pub type SPI_W4 = crate::Reg; +#[doc = "SPI CPU-controlled buffer4"] +pub mod spi_w4; +#[doc = "SPI_W5 (rw) register accessor: SPI CPU-controlled buffer5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w5`] module"] +pub type SPI_W5 = crate::Reg; +#[doc = "SPI CPU-controlled buffer5"] +pub mod spi_w5; +#[doc = "SPI_W6 (rw) register accessor: SPI CPU-controlled buffer6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w6`] module"] +pub type SPI_W6 = crate::Reg; +#[doc = "SPI CPU-controlled buffer6"] +pub mod spi_w6; +#[doc = "SPI_W7 (rw) register accessor: SPI CPU-controlled buffer7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w7`] module"] +pub type SPI_W7 = crate::Reg; +#[doc = "SPI CPU-controlled buffer7"] +pub mod spi_w7; +#[doc = "SPI_W8 (rw) register accessor: SPI CPU-controlled buffer8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w8`] module"] +pub type SPI_W8 = crate::Reg; +#[doc = "SPI CPU-controlled buffer8"] +pub mod spi_w8; +#[doc = "SPI_W9 (rw) register accessor: SPI CPU-controlled buffer9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w9`] module"] +pub type SPI_W9 = crate::Reg; +#[doc = "SPI CPU-controlled buffer9"] +pub mod spi_w9; +#[doc = "SPI_W10 (rw) register accessor: SPI CPU-controlled buffer10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w10`] module"] +pub type SPI_W10 = crate::Reg; +#[doc = "SPI CPU-controlled buffer10"] +pub mod spi_w10; +#[doc = "SPI_W11 (rw) register accessor: SPI CPU-controlled buffer11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w11`] module"] +pub type SPI_W11 = crate::Reg; +#[doc = "SPI CPU-controlled buffer11"] +pub mod spi_w11; +#[doc = "SPI_W12 (rw) register accessor: SPI CPU-controlled buffer12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w12`] module"] +pub type SPI_W12 = crate::Reg; +#[doc = "SPI CPU-controlled buffer12"] +pub mod spi_w12; +#[doc = "SPI_W13 (rw) register accessor: SPI CPU-controlled buffer13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w13`] module"] +pub type SPI_W13 = crate::Reg; +#[doc = "SPI CPU-controlled buffer13"] +pub mod spi_w13; +#[doc = "SPI_W14 (rw) register accessor: SPI CPU-controlled buffer14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w14`] module"] +pub type SPI_W14 = crate::Reg; +#[doc = "SPI CPU-controlled buffer14"] +pub mod spi_w14; +#[doc = "SPI_W15 (rw) register accessor: SPI CPU-controlled buffer15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w15`] module"] +pub type SPI_W15 = crate::Reg; +#[doc = "SPI CPU-controlled buffer15"] +pub mod spi_w15; +#[doc = "SPI_SLAVE (rw) register accessor: SPI slave control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave`] module"] +pub type SPI_SLAVE = crate::Reg; +#[doc = "SPI slave control register"] +pub mod spi_slave; +#[doc = "SPI_SLAVE1 (rw) register accessor: SPI slave control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave1`] module"] +pub type SPI_SLAVE1 = crate::Reg; +#[doc = "SPI slave control register 1"] +pub mod spi_slave1; +#[doc = "SPI_CLK_GATE (rw) register accessor: SPI module clock and register clock control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clk_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clk_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_clk_gate`] module"] +pub type SPI_CLK_GATE = crate::Reg; +#[doc = "SPI module clock and register clock control"] +pub mod spi_clk_gate; +#[doc = "SPI_DATE (rw) register accessor: Version control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_date`] module"] +pub type SPI_DATE = crate::Reg; +#[doc = "Version control"] +pub mod spi_date; diff --git a/esp32p4/src/spi2/spi_addr.rs b/esp32p4/src/spi2/spi_addr.rs new file mode 100644 index 0000000000..9a124b32c6 --- /dev/null +++ b/esp32p4/src/spi2/spi_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_USR_ADDR_VALUE` reader - Address to slave. Can be configured in CONF state."] +pub type SPI_USR_ADDR_VALUE_R = crate::FieldReader; +#[doc = "Field `SPI_USR_ADDR_VALUE` writer - Address to slave. Can be configured in CONF state."] +pub type SPI_USR_ADDR_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_addr_value(&self) -> SPI_USR_ADDR_VALUE_R { + SPI_USR_ADDR_VALUE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_ADDR") + .field( + "spi_usr_addr_value", + &format_args!("{}", self.spi_usr_addr_value().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_addr_value(&mut self) -> SPI_USR_ADDR_VALUE_W { + SPI_USR_ADDR_VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Address value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_ADDR_SPEC; +impl crate::RegisterSpec for SPI_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_addr::R`](R) reader structure"] +impl crate::Readable for SPI_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_addr::W`](W) writer structure"] +impl crate::Writable for SPI_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_ADDR to value 0"] +impl crate::Resettable for SPI_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_clk_gate.rs b/esp32p4/src/spi2/spi_clk_gate.rs new file mode 100644 index 0000000000..73e52476cc --- /dev/null +++ b/esp32p4/src/spi2/spi_clk_gate.rs @@ -0,0 +1,101 @@ +#[doc = "Register `SPI_CLK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_CLK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_CLK_EN` reader - Set this bit to enable clk gate"] +pub type SPI_CLK_EN_R = crate::BitReader; +#[doc = "Field `SPI_CLK_EN` writer - Set this bit to enable clk gate"] +pub type SPI_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_CLK_ACTIVE` reader - Set this bit to power on the SPI module clock."] +pub type SPI_MST_CLK_ACTIVE_R = crate::BitReader; +#[doc = "Field `SPI_MST_CLK_ACTIVE` writer - Set this bit to power on the SPI module clock."] +pub type SPI_MST_CLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_CLK_SEL` reader - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."] +pub type SPI_MST_CLK_SEL_R = crate::BitReader; +#[doc = "Field `SPI_MST_CLK_SEL` writer - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."] +pub type SPI_MST_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable clk gate"] + #[inline(always)] + pub fn spi_clk_en(&self) -> SPI_CLK_EN_R { + SPI_CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to power on the SPI module clock."] + #[inline(always)] + pub fn spi_mst_clk_active(&self) -> SPI_MST_CLK_ACTIVE_R { + SPI_MST_CLK_ACTIVE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."] + #[inline(always)] + pub fn spi_mst_clk_sel(&self) -> SPI_MST_CLK_SEL_R { + SPI_MST_CLK_SEL_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_CLK_GATE") + .field("spi_clk_en", &format_args!("{}", self.spi_clk_en().bit())) + .field( + "spi_mst_clk_active", + &format_args!("{}", self.spi_mst_clk_active().bit()), + ) + .field( + "spi_mst_clk_sel", + &format_args!("{}", self.spi_mst_clk_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable clk gate"] + #[inline(always)] + #[must_use] + pub fn spi_clk_en(&mut self) -> SPI_CLK_EN_W { + SPI_CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to power on the SPI module clock."] + #[inline(always)] + #[must_use] + pub fn spi_mst_clk_active(&mut self) -> SPI_MST_CLK_ACTIVE_W { + SPI_MST_CLK_ACTIVE_W::new(self, 1) + } + #[doc = "Bit 2 - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."] + #[inline(always)] + #[must_use] + pub fn spi_mst_clk_sel(&mut self) -> SPI_MST_CLK_SEL_W { + SPI_MST_CLK_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI module clock and register clock control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clk_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clk_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_CLK_GATE_SPEC; +impl crate::RegisterSpec for SPI_CLK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_clk_gate::R`](R) reader structure"] +impl crate::Readable for SPI_CLK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_clk_gate::W`](W) writer structure"] +impl crate::Writable for SPI_CLK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_CLK_GATE to value 0"] +impl crate::Resettable for SPI_CLK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_clock.rs b/esp32p4/src/spi2/spi_clock.rs new file mode 100644 index 0000000000..b79447a272 --- /dev/null +++ b/esp32p4/src/spi2/spi_clock.rs @@ -0,0 +1,142 @@ +#[doc = "Register `SPI_CLOCK` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_CLOCK` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_CLKCNT_L` reader - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."] +pub type SPI_CLKCNT_L_R = crate::FieldReader; +#[doc = "Field `SPI_CLKCNT_L` writer - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."] +pub type SPI_CLKCNT_L_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_CLKCNT_H` reader - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."] +pub type SPI_CLKCNT_H_R = crate::FieldReader; +#[doc = "Field `SPI_CLKCNT_H` writer - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."] +pub type SPI_CLKCNT_H_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_CLKCNT_N` reader - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."] +pub type SPI_CLKCNT_N_R = crate::FieldReader; +#[doc = "Field `SPI_CLKCNT_N` writer - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."] +pub type SPI_CLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_CLKDIV_PRE` reader - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."] +pub type SPI_CLKDIV_PRE_R = crate::FieldReader; +#[doc = "Field `SPI_CLKDIV_PRE` writer - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."] +pub type SPI_CLKDIV_PRE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SPI_CLK_EQU_SYSCLK` reader - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."] +pub type SPI_CLK_EQU_SYSCLK_R = crate::BitReader; +#[doc = "Field `SPI_CLK_EQU_SYSCLK` writer - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."] +pub type SPI_CLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clkcnt_l(&self) -> SPI_CLKCNT_L_R { + SPI_CLKCNT_L_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clkcnt_h(&self) -> SPI_CLKCNT_H_R { + SPI_CLKCNT_H_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:17 - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clkcnt_n(&self) -> SPI_CLKCNT_N_R { + SPI_CLKCNT_N_R::new(((self.bits >> 12) & 0x3f) as u8) + } + #[doc = "Bits 18:21 - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clkdiv_pre(&self) -> SPI_CLKDIV_PRE_R { + SPI_CLKDIV_PRE_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 31 - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clk_equ_sysclk(&self) -> SPI_CLK_EQU_SYSCLK_R { + SPI_CLK_EQU_SYSCLK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_CLOCK") + .field( + "spi_clkcnt_l", + &format_args!("{}", self.spi_clkcnt_l().bits()), + ) + .field( + "spi_clkcnt_h", + &format_args!("{}", self.spi_clkcnt_h().bits()), + ) + .field( + "spi_clkcnt_n", + &format_args!("{}", self.spi_clkcnt_n().bits()), + ) + .field( + "spi_clkdiv_pre", + &format_args!("{}", self.spi_clkdiv_pre().bits()), + ) + .field( + "spi_clk_equ_sysclk", + &format_args!("{}", self.spi_clk_equ_sysclk().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clkcnt_l(&mut self) -> SPI_CLKCNT_L_W { + SPI_CLKCNT_L_W::new(self, 0) + } + #[doc = "Bits 6:11 - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clkcnt_h(&mut self) -> SPI_CLKCNT_H_W { + SPI_CLKCNT_H_W::new(self, 6) + } + #[doc = "Bits 12:17 - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clkcnt_n(&mut self) -> SPI_CLKCNT_N_W { + SPI_CLKCNT_N_W::new(self, 12) + } + #[doc = "Bits 18:21 - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clkdiv_pre(&mut self) -> SPI_CLKDIV_PRE_W { + SPI_CLKDIV_PRE_W::new(self, 18) + } + #[doc = "Bit 31 - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clk_equ_sysclk(&mut self) -> SPI_CLK_EQU_SYSCLK_W { + SPI_CLK_EQU_SYSCLK_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clock::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_CLOCK_SPEC; +impl crate::RegisterSpec for SPI_CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_clock::R`](R) reader structure"] +impl crate::Readable for SPI_CLOCK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_clock::W`](W) writer structure"] +impl crate::Writable for SPI_CLOCK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_CLOCK to value 0x8000_3043"] +impl crate::Resettable for SPI_CLOCK_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_3043; +} diff --git a/esp32p4/src/spi2/spi_cmd.rs b/esp32p4/src/spi2/spi_cmd.rs new file mode 100644 index 0000000000..e96880ab18 --- /dev/null +++ b/esp32p4/src/spi2/spi_cmd.rs @@ -0,0 +1,90 @@ +#[doc = "Register `SPI_CMD` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_CMD` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_CONF_BITLEN` reader - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."] +pub type SPI_CONF_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_CONF_BITLEN` writer - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."] +pub type SPI_CONF_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `SPI_UPDATE` writer - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode."] +pub type SPI_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR` reader - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."] +pub type SPI_USR_R = crate::BitReader; +#[doc = "Field `SPI_USR` writer - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."] +pub type SPI_USR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:17 - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_conf_bitlen(&self) -> SPI_CONF_BITLEN_R { + SPI_CONF_BITLEN_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."] + #[inline(always)] + pub fn spi_usr(&self) -> SPI_USR_R { + SPI_USR_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_CMD") + .field( + "spi_conf_bitlen", + &format_args!("{}", self.spi_conf_bitlen().bits()), + ) + .field("spi_usr", &format_args!("{}", self.spi_usr().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:17 - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_conf_bitlen(&mut self) -> SPI_CONF_BITLEN_W { + SPI_CONF_BITLEN_W::new(self, 0) + } + #[doc = "Bit 23 - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode."] + #[inline(always)] + #[must_use] + pub fn spi_update(&mut self) -> SPI_UPDATE_W { + SPI_UPDATE_W::new(self, 23) + } + #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."] + #[inline(always)] + #[must_use] + pub fn spi_usr(&mut self) -> SPI_USR_W { + SPI_USR_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_CMD_SPEC; +impl crate::RegisterSpec for SPI_CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_cmd::R`](R) reader structure"] +impl crate::Readable for SPI_CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_cmd::W`](W) writer structure"] +impl crate::Writable for SPI_CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_CMD to value 0"] +impl crate::Resettable for SPI_CMD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_ctrl.rs b/esp32p4/src/spi2/spi_ctrl.rs new file mode 100644 index 0000000000..79acbf3060 --- /dev/null +++ b/esp32p4/src/spi2/spi_ctrl.rs @@ -0,0 +1,342 @@ +#[doc = "Register `SPI_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DUMMY_OUT` reader - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."] +pub type SPI_DUMMY_OUT_R = crate::BitReader; +#[doc = "Field `SPI_DUMMY_OUT` writer - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."] +pub type SPI_DUMMY_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FADDR_DUAL` reader - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FADDR_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_FADDR_DUAL` writer - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FADDR_QUAD` reader - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FADDR_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_FADDR_QUAD` writer - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FADDR_OCT` reader - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FADDR_OCT_R = crate::BitReader; +#[doc = "Field `SPI_FADDR_OCT` writer - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FADDR_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FCMD_DUAL` reader - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FCMD_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_FCMD_DUAL` writer - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FCMD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FCMD_QUAD` reader - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FCMD_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_FCMD_QUAD` writer - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FCMD_OCT` reader - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FCMD_OCT_R = crate::BitReader; +#[doc = "Field `SPI_FCMD_OCT` writer - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FCMD_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_FREAD_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_FREAD_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FREAD_OCT` reader - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_FREAD_OCT_R = crate::BitReader; +#[doc = "Field `SPI_FREAD_OCT` writer - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_FREAD_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."] +pub type SPI_Q_POL_R = crate::BitReader; +#[doc = "Field `SPI_Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."] +pub type SPI_Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."] +pub type SPI_D_POL_R = crate::BitReader; +#[doc = "Field `SPI_D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."] +pub type SPI_D_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_HOLD_POL` reader - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] +pub type SPI_HOLD_POL_R = crate::BitReader; +#[doc = "Field `SPI_HOLD_POL` writer - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] +pub type SPI_HOLD_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_WP_POL` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] +pub type SPI_WP_POL_R = crate::BitReader; +#[doc = "Field `SPI_WP_POL` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] +pub type SPI_WP_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_RD_BIT_ORDER` reader - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."] +pub type SPI_RD_BIT_ORDER_R = crate::FieldReader; +#[doc = "Field `SPI_RD_BIT_ORDER` writer - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."] +pub type SPI_RD_BIT_ORDER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_WR_BIT_ORDER` reader - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."] +pub type SPI_WR_BIT_ORDER_R = crate::FieldReader; +#[doc = "Field `SPI_WR_BIT_ORDER` writer - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."] +pub type SPI_WR_BIT_ORDER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dummy_out(&self) -> SPI_DUMMY_OUT_R { + SPI_DUMMY_OUT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_faddr_dual(&self) -> SPI_FADDR_DUAL_R { + SPI_FADDR_DUAL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_faddr_quad(&self) -> SPI_FADDR_QUAD_R { + SPI_FADDR_QUAD_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_faddr_oct(&self) -> SPI_FADDR_OCT_R { + SPI_FADDR_OCT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fcmd_dual(&self) -> SPI_FCMD_DUAL_R { + SPI_FCMD_DUAL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fcmd_quad(&self) -> SPI_FCMD_QUAD_R { + SPI_FCMD_QUAD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fcmd_oct(&self) -> SPI_FCMD_OCT_R { + SPI_FCMD_OCT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fread_dual(&self) -> SPI_FREAD_DUAL_R { + SPI_FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fread_quad(&self) -> SPI_FREAD_QUAD_R { + SPI_FREAD_QUAD_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fread_oct(&self) -> SPI_FREAD_OCT_R { + SPI_FREAD_OCT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_q_pol(&self) -> SPI_Q_POL_R { + SPI_Q_POL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_d_pol(&self) -> SPI_D_POL_R { + SPI_D_POL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_hold_pol(&self) -> SPI_HOLD_POL_R { + SPI_HOLD_POL_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_wp_pol(&self) -> SPI_WP_POL_R { + SPI_WP_POL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 23:24 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_rd_bit_order(&self) -> SPI_RD_BIT_ORDER_R { + SPI_RD_BIT_ORDER_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bits 25:26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_wr_bit_order(&self) -> SPI_WR_BIT_ORDER_R { + SPI_WR_BIT_ORDER_R::new(((self.bits >> 25) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_CTRL") + .field( + "spi_dummy_out", + &format_args!("{}", self.spi_dummy_out().bit()), + ) + .field( + "spi_faddr_dual", + &format_args!("{}", self.spi_faddr_dual().bit()), + ) + .field( + "spi_faddr_quad", + &format_args!("{}", self.spi_faddr_quad().bit()), + ) + .field( + "spi_faddr_oct", + &format_args!("{}", self.spi_faddr_oct().bit()), + ) + .field( + "spi_fcmd_dual", + &format_args!("{}", self.spi_fcmd_dual().bit()), + ) + .field( + "spi_fcmd_quad", + &format_args!("{}", self.spi_fcmd_quad().bit()), + ) + .field( + "spi_fcmd_oct", + &format_args!("{}", self.spi_fcmd_oct().bit()), + ) + .field( + "spi_fread_dual", + &format_args!("{}", self.spi_fread_dual().bit()), + ) + .field( + "spi_fread_quad", + &format_args!("{}", self.spi_fread_quad().bit()), + ) + .field( + "spi_fread_oct", + &format_args!("{}", self.spi_fread_oct().bit()), + ) + .field("spi_q_pol", &format_args!("{}", self.spi_q_pol().bit())) + .field("spi_d_pol", &format_args!("{}", self.spi_d_pol().bit())) + .field( + "spi_hold_pol", + &format_args!("{}", self.spi_hold_pol().bit()), + ) + .field("spi_wp_pol", &format_args!("{}", self.spi_wp_pol().bit())) + .field( + "spi_rd_bit_order", + &format_args!("{}", self.spi_rd_bit_order().bits()), + ) + .field( + "spi_wr_bit_order", + &format_args!("{}", self.spi_wr_bit_order().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dummy_out(&mut self) -> SPI_DUMMY_OUT_W { + SPI_DUMMY_OUT_W::new(self, 3) + } + #[doc = "Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_faddr_dual(&mut self) -> SPI_FADDR_DUAL_W { + SPI_FADDR_DUAL_W::new(self, 5) + } + #[doc = "Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_faddr_quad(&mut self) -> SPI_FADDR_QUAD_W { + SPI_FADDR_QUAD_W::new(self, 6) + } + #[doc = "Bit 7 - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_faddr_oct(&mut self) -> SPI_FADDR_OCT_W { + SPI_FADDR_OCT_W::new(self, 7) + } + #[doc = "Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fcmd_dual(&mut self) -> SPI_FCMD_DUAL_W { + SPI_FCMD_DUAL_W::new(self, 8) + } + #[doc = "Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fcmd_quad(&mut self) -> SPI_FCMD_QUAD_W { + SPI_FCMD_QUAD_W::new(self, 9) + } + #[doc = "Bit 10 - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fcmd_oct(&mut self) -> SPI_FCMD_OCT_W { + SPI_FCMD_OCT_W::new(self, 10) + } + #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fread_dual(&mut self) -> SPI_FREAD_DUAL_W { + SPI_FREAD_DUAL_W::new(self, 14) + } + #[doc = "Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fread_quad(&mut self) -> SPI_FREAD_QUAD_W { + SPI_FREAD_QUAD_W::new(self, 15) + } + #[doc = "Bit 16 - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fread_oct(&mut self) -> SPI_FREAD_OCT_W { + SPI_FREAD_OCT_W::new(self, 16) + } + #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_q_pol(&mut self) -> SPI_Q_POL_W { + SPI_Q_POL_W::new(self, 18) + } + #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_d_pol(&mut self) -> SPI_D_POL_W { + SPI_D_POL_W::new(self, 19) + } + #[doc = "Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_hold_pol(&mut self) -> SPI_HOLD_POL_W { + SPI_HOLD_POL_W::new(self, 20) + } + #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_wp_pol(&mut self) -> SPI_WP_POL_W { + SPI_WP_POL_W::new(self, 21) + } + #[doc = "Bits 23:24 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_rd_bit_order(&mut self) -> SPI_RD_BIT_ORDER_W { + SPI_RD_BIT_ORDER_W::new(self, 23) + } + #[doc = "Bits 25:26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_wr_bit_order(&mut self) -> SPI_WR_BIT_ORDER_W { + SPI_WR_BIT_ORDER_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_CTRL_SPEC; +impl crate::RegisterSpec for SPI_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_ctrl::R`](R) reader structure"] +impl crate::Readable for SPI_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_ctrl::W`](W) writer structure"] +impl crate::Writable for SPI_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_CTRL to value 0x003c_0000"] +impl crate::Resettable for SPI_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x003c_0000; +} diff --git a/esp32p4/src/spi2/spi_date.rs b/esp32p4/src/spi2/spi_date.rs new file mode 100644 index 0000000000..54622f1ceb --- /dev/null +++ b/esp32p4/src/spi2/spi_date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DATE` reader - SPI register version."] +pub type SPI_DATE_R = crate::FieldReader; +#[doc = "Field `SPI_DATE` writer - SPI register version."] +pub type SPI_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - SPI register version."] + #[inline(always)] + pub fn spi_date(&self) -> SPI_DATE_R { + SPI_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DATE") + .field("spi_date", &format_args!("{}", self.spi_date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - SPI register version."] + #[inline(always)] + #[must_use] + pub fn spi_date(&mut self) -> SPI_DATE_W { + SPI_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DATE_SPEC; +impl crate::RegisterSpec for SPI_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_date::R`](R) reader structure"] +impl crate::Readable for SPI_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_date::W`](W) writer structure"] +impl crate::Writable for SPI_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DATE to value 0x0220_7202"] +impl crate::Resettable for SPI_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_7202; +} diff --git a/esp32p4/src/spi2/spi_din_mode.rs b/esp32p4/src/spi2/spi_din_mode.rs new file mode 100644 index 0000000000..3a0105bd6e --- /dev/null +++ b/esp32p4/src/spi2/spi_din_mode.rs @@ -0,0 +1,218 @@ +#[doc = "Register `SPI_DIN_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DIN_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DIN0_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN0_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN0_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN0_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN1_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN1_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN1_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN1_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN2_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN2_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN2_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN2_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN3_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN3_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN3_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN3_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN4_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN4_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN4_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN4_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN5_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN5_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN5_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN5_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN6_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN6_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN6_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN6_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN7_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN7_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN7_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN7_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_TIMING_HCLK_ACTIVE` reader - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."] +pub type SPI_TIMING_HCLK_ACTIVE_R = crate::BitReader; +#[doc = "Field `SPI_TIMING_HCLK_ACTIVE` writer - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."] +pub type SPI_TIMING_HCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din0_mode(&self) -> SPI_DIN0_MODE_R { + SPI_DIN0_MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din1_mode(&self) -> SPI_DIN1_MODE_R { + SPI_DIN1_MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din2_mode(&self) -> SPI_DIN2_MODE_R { + SPI_DIN2_MODE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din3_mode(&self) -> SPI_DIN3_MODE_R { + SPI_DIN3_MODE_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din4_mode(&self) -> SPI_DIN4_MODE_R { + SPI_DIN4_MODE_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din5_mode(&self) -> SPI_DIN5_MODE_R { + SPI_DIN5_MODE_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din6_mode(&self) -> SPI_DIN6_MODE_R { + SPI_DIN6_MODE_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din7_mode(&self) -> SPI_DIN7_MODE_R { + SPI_DIN7_MODE_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_timing_hclk_active(&self) -> SPI_TIMING_HCLK_ACTIVE_R { + SPI_TIMING_HCLK_ACTIVE_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DIN_MODE") + .field( + "spi_din0_mode", + &format_args!("{}", self.spi_din0_mode().bits()), + ) + .field( + "spi_din1_mode", + &format_args!("{}", self.spi_din1_mode().bits()), + ) + .field( + "spi_din2_mode", + &format_args!("{}", self.spi_din2_mode().bits()), + ) + .field( + "spi_din3_mode", + &format_args!("{}", self.spi_din3_mode().bits()), + ) + .field( + "spi_din4_mode", + &format_args!("{}", self.spi_din4_mode().bits()), + ) + .field( + "spi_din5_mode", + &format_args!("{}", self.spi_din5_mode().bits()), + ) + .field( + "spi_din6_mode", + &format_args!("{}", self.spi_din6_mode().bits()), + ) + .field( + "spi_din7_mode", + &format_args!("{}", self.spi_din7_mode().bits()), + ) + .field( + "spi_timing_hclk_active", + &format_args!("{}", self.spi_timing_hclk_active().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din0_mode(&mut self) -> SPI_DIN0_MODE_W { + SPI_DIN0_MODE_W::new(self, 0) + } + #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din1_mode(&mut self) -> SPI_DIN1_MODE_W { + SPI_DIN1_MODE_W::new(self, 2) + } + #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din2_mode(&mut self) -> SPI_DIN2_MODE_W { + SPI_DIN2_MODE_W::new(self, 4) + } + #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din3_mode(&mut self) -> SPI_DIN3_MODE_W { + SPI_DIN3_MODE_W::new(self, 6) + } + #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din4_mode(&mut self) -> SPI_DIN4_MODE_W { + SPI_DIN4_MODE_W::new(self, 8) + } + #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din5_mode(&mut self) -> SPI_DIN5_MODE_W { + SPI_DIN5_MODE_W::new(self, 10) + } + #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din6_mode(&mut self) -> SPI_DIN6_MODE_W { + SPI_DIN6_MODE_W::new(self, 12) + } + #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din7_mode(&mut self) -> SPI_DIN7_MODE_W { + SPI_DIN7_MODE_W::new(self, 14) + } + #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_timing_hclk_active(&mut self) -> SPI_TIMING_HCLK_ACTIVE_W { + SPI_TIMING_HCLK_ACTIVE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI input delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_din_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_din_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DIN_MODE_SPEC; +impl crate::RegisterSpec for SPI_DIN_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_din_mode::R`](R) reader structure"] +impl crate::Readable for SPI_DIN_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_din_mode::W`](W) writer structure"] +impl crate::Writable for SPI_DIN_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DIN_MODE to value 0"] +impl crate::Resettable for SPI_DIN_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_din_num.rs b/esp32p4/src/spi2/spi_din_num.rs new file mode 100644 index 0000000000..8242709a82 --- /dev/null +++ b/esp32p4/src/spi2/spi_din_num.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SPI_DIN_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DIN_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DIN0_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN0_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN0_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN0_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN1_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN1_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN1_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN1_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN2_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN2_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN2_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN2_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN3_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN3_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN3_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN3_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN4_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN4_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN4_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN4_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN5_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN5_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN5_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN5_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN6_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN6_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN6_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN6_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN7_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN7_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN7_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN7_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din0_num(&self) -> SPI_DIN0_NUM_R { + SPI_DIN0_NUM_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din1_num(&self) -> SPI_DIN1_NUM_R { + SPI_DIN1_NUM_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din2_num(&self) -> SPI_DIN2_NUM_R { + SPI_DIN2_NUM_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din3_num(&self) -> SPI_DIN3_NUM_R { + SPI_DIN3_NUM_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din4_num(&self) -> SPI_DIN4_NUM_R { + SPI_DIN4_NUM_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din5_num(&self) -> SPI_DIN5_NUM_R { + SPI_DIN5_NUM_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din6_num(&self) -> SPI_DIN6_NUM_R { + SPI_DIN6_NUM_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din7_num(&self) -> SPI_DIN7_NUM_R { + SPI_DIN7_NUM_R::new(((self.bits >> 14) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DIN_NUM") + .field( + "spi_din0_num", + &format_args!("{}", self.spi_din0_num().bits()), + ) + .field( + "spi_din1_num", + &format_args!("{}", self.spi_din1_num().bits()), + ) + .field( + "spi_din2_num", + &format_args!("{}", self.spi_din2_num().bits()), + ) + .field( + "spi_din3_num", + &format_args!("{}", self.spi_din3_num().bits()), + ) + .field( + "spi_din4_num", + &format_args!("{}", self.spi_din4_num().bits()), + ) + .field( + "spi_din5_num", + &format_args!("{}", self.spi_din5_num().bits()), + ) + .field( + "spi_din6_num", + &format_args!("{}", self.spi_din6_num().bits()), + ) + .field( + "spi_din7_num", + &format_args!("{}", self.spi_din7_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din0_num(&mut self) -> SPI_DIN0_NUM_W { + SPI_DIN0_NUM_W::new(self, 0) + } + #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din1_num(&mut self) -> SPI_DIN1_NUM_W { + SPI_DIN1_NUM_W::new(self, 2) + } + #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din2_num(&mut self) -> SPI_DIN2_NUM_W { + SPI_DIN2_NUM_W::new(self, 4) + } + #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din3_num(&mut self) -> SPI_DIN3_NUM_W { + SPI_DIN3_NUM_W::new(self, 6) + } + #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din4_num(&mut self) -> SPI_DIN4_NUM_W { + SPI_DIN4_NUM_W::new(self, 8) + } + #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din5_num(&mut self) -> SPI_DIN5_NUM_W { + SPI_DIN5_NUM_W::new(self, 10) + } + #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din6_num(&mut self) -> SPI_DIN6_NUM_W { + SPI_DIN6_NUM_W::new(self, 12) + } + #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din7_num(&mut self) -> SPI_DIN7_NUM_W { + SPI_DIN7_NUM_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI input delay number configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_din_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_din_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DIN_NUM_SPEC; +impl crate::RegisterSpec for SPI_DIN_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_din_num::R`](R) reader structure"] +impl crate::Readable for SPI_DIN_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_din_num::W`](W) writer structure"] +impl crate::Writable for SPI_DIN_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DIN_NUM to value 0"] +impl crate::Resettable for SPI_DIN_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_dma_conf.rs b/esp32p4/src/spi2/spi_dma_conf.rs new file mode 100644 index 0000000000..dc684a050d --- /dev/null +++ b/esp32p4/src/spi2/spi_dma_conf.rs @@ -0,0 +1,211 @@ +#[doc = "Register `SPI_DMA_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DMA_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY` reader - Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data."] +pub type SPI_DMA_OUTFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `SPI_DMA_INFIFO_FULL` reader - Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data."] +pub type SPI_DMA_INFIFO_FULL_R = crate::BitReader; +#[doc = "Field `SPI_DMA_SLV_SEG_TRANS_EN` reader - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."] +pub type SPI_DMA_SLV_SEG_TRANS_EN_R = crate::BitReader; +#[doc = "Field `SPI_DMA_SLV_SEG_TRANS_EN` writer - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."] +pub type SPI_DMA_SLV_SEG_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RX_SEG_TRANS_CLR_EN` reader - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."] +pub type SPI_SLV_RX_SEG_TRANS_CLR_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RX_SEG_TRANS_CLR_EN` writer - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."] +pub type SPI_SLV_RX_SEG_TRANS_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_TX_SEG_TRANS_CLR_EN` reader - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."] +pub type SPI_SLV_TX_SEG_TRANS_CLR_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_TX_SEG_TRANS_CLR_EN` writer - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."] +pub type SPI_SLV_TX_SEG_TRANS_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_RX_EOF_EN` reader - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."] +pub type SPI_RX_EOF_EN_R = crate::BitReader; +#[doc = "Field `SPI_RX_EOF_EN` writer - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."] +pub type SPI_RX_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_RX_ENA` reader - Set this bit to enable SPI DMA controlled receive data mode."] +pub type SPI_DMA_RX_ENA_R = crate::BitReader; +#[doc = "Field `SPI_DMA_RX_ENA` writer - Set this bit to enable SPI DMA controlled receive data mode."] +pub type SPI_DMA_RX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_TX_ENA` reader - Set this bit to enable SPI DMA controlled send data mode."] +pub type SPI_DMA_TX_ENA_R = crate::BitReader; +#[doc = "Field `SPI_DMA_TX_ENA` writer - Set this bit to enable SPI DMA controlled send data mode."] +pub type SPI_DMA_TX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_RX_AFIFO_RST` writer - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer."] +pub type SPI_RX_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_BUF_AFIFO_RST` writer - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer."] +pub type SPI_BUF_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_AFIFO_RST` writer - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer."] +pub type SPI_DMA_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data."] + #[inline(always)] + pub fn spi_dma_outfifo_empty(&self) -> SPI_DMA_OUTFIFO_EMPTY_R { + SPI_DMA_OUTFIFO_EMPTY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data."] + #[inline(always)] + pub fn spi_dma_infifo_full(&self) -> SPI_DMA_INFIFO_FULL_R { + SPI_DMA_INFIFO_FULL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."] + #[inline(always)] + pub fn spi_dma_slv_seg_trans_en(&self) -> SPI_DMA_SLV_SEG_TRANS_EN_R { + SPI_DMA_SLV_SEG_TRANS_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."] + #[inline(always)] + pub fn spi_slv_rx_seg_trans_clr_en(&self) -> SPI_SLV_RX_SEG_TRANS_CLR_EN_R { + SPI_SLV_RX_SEG_TRANS_CLR_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."] + #[inline(always)] + pub fn spi_slv_tx_seg_trans_clr_en(&self) -> SPI_SLV_TX_SEG_TRANS_CLR_EN_R { + SPI_SLV_TX_SEG_TRANS_CLR_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."] + #[inline(always)] + pub fn spi_rx_eof_en(&self) -> SPI_RX_EOF_EN_R { + SPI_RX_EOF_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 27 - Set this bit to enable SPI DMA controlled receive data mode."] + #[inline(always)] + pub fn spi_dma_rx_ena(&self) -> SPI_DMA_RX_ENA_R { + SPI_DMA_RX_ENA_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Set this bit to enable SPI DMA controlled send data mode."] + #[inline(always)] + pub fn spi_dma_tx_ena(&self) -> SPI_DMA_TX_ENA_R { + SPI_DMA_TX_ENA_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DMA_CONF") + .field( + "spi_dma_outfifo_empty", + &format_args!("{}", self.spi_dma_outfifo_empty().bit()), + ) + .field( + "spi_dma_infifo_full", + &format_args!("{}", self.spi_dma_infifo_full().bit()), + ) + .field( + "spi_dma_slv_seg_trans_en", + &format_args!("{}", self.spi_dma_slv_seg_trans_en().bit()), + ) + .field( + "spi_slv_rx_seg_trans_clr_en", + &format_args!("{}", self.spi_slv_rx_seg_trans_clr_en().bit()), + ) + .field( + "spi_slv_tx_seg_trans_clr_en", + &format_args!("{}", self.spi_slv_tx_seg_trans_clr_en().bit()), + ) + .field( + "spi_rx_eof_en", + &format_args!("{}", self.spi_rx_eof_en().bit()), + ) + .field( + "spi_dma_rx_ena", + &format_args!("{}", self.spi_dma_rx_ena().bit()), + ) + .field( + "spi_dma_tx_ena", + &format_args!("{}", self.spi_dma_tx_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_dma_slv_seg_trans_en(&mut self) -> SPI_DMA_SLV_SEG_TRANS_EN_W { + SPI_DMA_SLV_SEG_TRANS_EN_W::new(self, 18) + } + #[doc = "Bit 19 - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rx_seg_trans_clr_en( + &mut self, + ) -> SPI_SLV_RX_SEG_TRANS_CLR_EN_W { + SPI_SLV_RX_SEG_TRANS_CLR_EN_W::new(self, 19) + } + #[doc = "Bit 20 - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."] + #[inline(always)] + #[must_use] + pub fn spi_slv_tx_seg_trans_clr_en( + &mut self, + ) -> SPI_SLV_TX_SEG_TRANS_CLR_EN_W { + SPI_SLV_TX_SEG_TRANS_CLR_EN_W::new(self, 20) + } + #[doc = "Bit 21 - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."] + #[inline(always)] + #[must_use] + pub fn spi_rx_eof_en(&mut self) -> SPI_RX_EOF_EN_W { + SPI_RX_EOF_EN_W::new(self, 21) + } + #[doc = "Bit 27 - Set this bit to enable SPI DMA controlled receive data mode."] + #[inline(always)] + #[must_use] + pub fn spi_dma_rx_ena(&mut self) -> SPI_DMA_RX_ENA_W { + SPI_DMA_RX_ENA_W::new(self, 27) + } + #[doc = "Bit 28 - Set this bit to enable SPI DMA controlled send data mode."] + #[inline(always)] + #[must_use] + pub fn spi_dma_tx_ena(&mut self) -> SPI_DMA_TX_ENA_W { + SPI_DMA_TX_ENA_W::new(self, 28) + } + #[doc = "Bit 29 - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer."] + #[inline(always)] + #[must_use] + pub fn spi_rx_afifo_rst(&mut self) -> SPI_RX_AFIFO_RST_W { + SPI_RX_AFIFO_RST_W::new(self, 29) + } + #[doc = "Bit 30 - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer."] + #[inline(always)] + #[must_use] + pub fn spi_buf_afifo_rst(&mut self) -> SPI_BUF_AFIFO_RST_W { + SPI_BUF_AFIFO_RST_W::new(self, 30) + } + #[doc = "Bit 31 - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer."] + #[inline(always)] + #[must_use] + pub fn spi_dma_afifo_rst(&mut self) -> SPI_DMA_AFIFO_RST_W { + SPI_DMA_AFIFO_RST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI DMA control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_CONF_SPEC; +impl crate::RegisterSpec for SPI_DMA_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_dma_conf::R`](R) reader structure"] +impl crate::Readable for SPI_DMA_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_dma_conf::W`](W) writer structure"] +impl crate::Writable for SPI_DMA_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DMA_CONF to value 0x03"] +impl crate::Resettable for SPI_DMA_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/spi2/spi_dma_int_clr.rs b/esp32p4/src/spi2/spi_dma_int_clr.rs new file mode 100644 index 0000000000..a6a1001ef7 --- /dev/null +++ b/esp32p4/src/spi2/spi_dma_int_clr.rs @@ -0,0 +1,224 @@ +#[doc = "Register `SPI_DMA_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_CLR` writer - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR` writer - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EX_QPI_INT_CLR` writer - The clear bit for SPI slave Ex_QPI interrupt."] +pub type SPI_SLV_EX_QPI_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EN_QPI_INT_CLR` writer - The clear bit for SPI slave En_QPI interrupt."] +pub type SPI_SLV_EN_QPI_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD7_INT_CLR` writer - The clear bit for SPI slave CMD7 interrupt."] +pub type SPI_SLV_CMD7_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD8_INT_CLR` writer - The clear bit for SPI slave CMD8 interrupt."] +pub type SPI_SLV_CMD8_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD9_INT_CLR` writer - The clear bit for SPI slave CMD9 interrupt."] +pub type SPI_SLV_CMD9_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMDA_INT_CLR` writer - The clear bit for SPI slave CMDA interrupt."] +pub type SPI_SLV_CMDA_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_CLR` writer - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] +pub type SPI_SLV_RD_DMA_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_CLR` writer - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] +pub type SPI_SLV_WR_DMA_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_CLR` writer - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] +pub type SPI_SLV_RD_BUF_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_CLR` writer - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] +pub type SPI_SLV_WR_BUF_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_TRANS_DONE_INT_CLR` writer - The clear bit for SPI_TRANS_DONE_INT interrupt."] +pub type SPI_TRANS_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_CLR` writer - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SEG_MAGIC_ERR_INT_CLR` writer - The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt."] +pub type SPI_SEG_MAGIC_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_CLR` writer - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_CLR` writer - The clear bit for SPI_SLV_CMD_ERR_INT interrupt."] +pub type SPI_SLV_CMD_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR` writer - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR` writer - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP2_INT_CLR` writer - The clear bit for SPI_APP2_INT interrupt."] +pub type SPI_APP2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP1_INT_CLR` writer - The clear bit for SPI_APP1_INT interrupt."] +pub type SPI_APP1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_infifo_full_err_int_clr( + &mut self, + ) -> SPI_DMA_INFIFO_FULL_ERR_INT_CLR_W { + SPI_DMA_INFIFO_FULL_ERR_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_outfifo_empty_err_int_clr( + &mut self, + ) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_W { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - The clear bit for SPI slave Ex_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_ex_qpi_int_clr(&mut self) -> SPI_SLV_EX_QPI_INT_CLR_W { + SPI_SLV_EX_QPI_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - The clear bit for SPI slave En_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_en_qpi_int_clr(&mut self) -> SPI_SLV_EN_QPI_INT_CLR_W { + SPI_SLV_EN_QPI_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - The clear bit for SPI slave CMD7 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd7_int_clr(&mut self) -> SPI_SLV_CMD7_INT_CLR_W { + SPI_SLV_CMD7_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - The clear bit for SPI slave CMD8 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd8_int_clr(&mut self) -> SPI_SLV_CMD8_INT_CLR_W { + SPI_SLV_CMD8_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - The clear bit for SPI slave CMD9 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd9_int_clr(&mut self) -> SPI_SLV_CMD9_INT_CLR_W { + SPI_SLV_CMD9_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - The clear bit for SPI slave CMDA interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmda_int_clr(&mut self) -> SPI_SLV_CMDA_INT_CLR_W { + SPI_SLV_CMDA_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_dma_done_int_clr( + &mut self, + ) -> SPI_SLV_RD_DMA_DONE_INT_CLR_W { + SPI_SLV_RD_DMA_DONE_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_dma_done_int_clr( + &mut self, + ) -> SPI_SLV_WR_DMA_DONE_INT_CLR_W { + SPI_SLV_WR_DMA_DONE_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_buf_done_int_clr( + &mut self, + ) -> SPI_SLV_RD_BUF_DONE_INT_CLR_W { + SPI_SLV_RD_BUF_DONE_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_buf_done_int_clr( + &mut self, + ) -> SPI_SLV_WR_BUF_DONE_INT_CLR_W { + SPI_SLV_WR_BUF_DONE_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - The clear bit for SPI_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_trans_done_int_clr(&mut self) -> SPI_TRANS_DONE_INT_CLR_W { + SPI_TRANS_DONE_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_seg_trans_done_int_clr( + &mut self, + ) -> SPI_DMA_SEG_TRANS_DONE_INT_CLR_W { + SPI_DMA_SEG_TRANS_DONE_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_seg_magic_err_int_clr( + &mut self, + ) -> SPI_SEG_MAGIC_ERR_INT_CLR_W { + SPI_SEG_MAGIC_ERR_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_buf_addr_err_int_clr( + &mut self, + ) -> SPI_SLV_BUF_ADDR_ERR_INT_CLR_W { + SPI_SLV_BUF_ADDR_ERR_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - The clear bit for SPI_SLV_CMD_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd_err_int_clr(&mut self) -> SPI_SLV_CMD_ERR_INT_CLR_W { + SPI_SLV_CMD_ERR_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_rx_afifo_wfull_err_int_clr( + &mut self, + ) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_W { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_tx_afifo_rempty_err_int_clr( + &mut self, + ) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_W { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - The clear bit for SPI_APP2_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app2_int_clr(&mut self) -> SPI_APP2_INT_CLR_W { + SPI_APP2_INT_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - The clear bit for SPI_APP1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app1_int_clr(&mut self) -> SPI_APP1_INT_CLR_W { + SPI_APP1_INT_CLR_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_INT_CLR_SPEC; +impl crate::RegisterSpec for SPI_DMA_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`spi_dma_int_clr::W`](W) writer structure"] +impl crate::Writable for SPI_DMA_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DMA_INT_CLR to value 0"] +impl crate::Resettable for SPI_DMA_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_dma_int_ena.rs b/esp32p4/src/spi2/spi_dma_int_ena.rs new file mode 100644 index 0000000000..cc62b1f29a --- /dev/null +++ b/esp32p4/src/spi2/spi_dma_int_ena.rs @@ -0,0 +1,468 @@ +#[doc = "Register `SPI_DMA_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DMA_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_ENA` reader - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_ENA` writer - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA` reader - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA` writer - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EX_QPI_INT_ENA` reader - The enable bit for SPI slave Ex_QPI interrupt."] +pub type SPI_SLV_EX_QPI_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EX_QPI_INT_ENA` writer - The enable bit for SPI slave Ex_QPI interrupt."] +pub type SPI_SLV_EX_QPI_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EN_QPI_INT_ENA` reader - The enable bit for SPI slave En_QPI interrupt."] +pub type SPI_SLV_EN_QPI_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EN_QPI_INT_ENA` writer - The enable bit for SPI slave En_QPI interrupt."] +pub type SPI_SLV_EN_QPI_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD7_INT_ENA` reader - The enable bit for SPI slave CMD7 interrupt."] +pub type SPI_SLV_CMD7_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD7_INT_ENA` writer - The enable bit for SPI slave CMD7 interrupt."] +pub type SPI_SLV_CMD7_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD8_INT_ENA` reader - The enable bit for SPI slave CMD8 interrupt."] +pub type SPI_SLV_CMD8_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD8_INT_ENA` writer - The enable bit for SPI slave CMD8 interrupt."] +pub type SPI_SLV_CMD8_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD9_INT_ENA` reader - The enable bit for SPI slave CMD9 interrupt."] +pub type SPI_SLV_CMD9_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD9_INT_ENA` writer - The enable bit for SPI slave CMD9 interrupt."] +pub type SPI_SLV_CMD9_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMDA_INT_ENA` reader - The enable bit for SPI slave CMDA interrupt."] +pub type SPI_SLV_CMDA_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMDA_INT_ENA` writer - The enable bit for SPI slave CMDA interrupt."] +pub type SPI_SLV_CMDA_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_ENA` reader - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] +pub type SPI_SLV_RD_DMA_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_ENA` writer - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] +pub type SPI_SLV_RD_DMA_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_ENA` reader - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] +pub type SPI_SLV_WR_DMA_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_ENA` writer - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] +pub type SPI_SLV_WR_DMA_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_ENA` reader - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] +pub type SPI_SLV_RD_BUF_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_ENA` writer - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] +pub type SPI_SLV_RD_BUF_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_ENA` reader - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] +pub type SPI_SLV_WR_BUF_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_ENA` writer - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] +pub type SPI_SLV_WR_BUF_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_TRANS_DONE_INT_ENA` reader - The enable bit for SPI_TRANS_DONE_INT interrupt."] +pub type SPI_TRANS_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_TRANS_DONE_INT_ENA` writer - The enable bit for SPI_TRANS_DONE_INT interrupt."] +pub type SPI_TRANS_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_ENA` reader - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_ENA` writer - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SEG_MAGIC_ERR_INT_ENA` reader - The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt."] +pub type SPI_SEG_MAGIC_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SEG_MAGIC_ERR_INT_ENA` writer - The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt."] +pub type SPI_SEG_MAGIC_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_ENA` reader - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_ENA` writer - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_ENA` reader - The enable bit for SPI_SLV_CMD_ERR_INT interrupt."] +pub type SPI_SLV_CMD_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_ENA` writer - The enable bit for SPI_SLV_CMD_ERR_INT interrupt."] +pub type SPI_SLV_CMD_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA` reader - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA` writer - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA` reader - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA` writer - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP2_INT_ENA` reader - The enable bit for SPI_APP2_INT interrupt."] +pub type SPI_APP2_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_APP2_INT_ENA` writer - The enable bit for SPI_APP2_INT interrupt."] +pub type SPI_APP2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP1_INT_ENA` reader - The enable bit for SPI_APP1_INT interrupt."] +pub type SPI_APP1_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_APP1_INT_ENA` writer - The enable bit for SPI_APP1_INT interrupt."] +pub type SPI_APP1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_dma_infifo_full_err_int_ena(&self) -> SPI_DMA_INFIFO_FULL_ERR_INT_ENA_R { + SPI_DMA_INFIFO_FULL_ERR_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_dma_outfifo_empty_err_int_ena(&self) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_R { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The enable bit for SPI slave Ex_QPI interrupt."] + #[inline(always)] + pub fn spi_slv_ex_qpi_int_ena(&self) -> SPI_SLV_EX_QPI_INT_ENA_R { + SPI_SLV_EX_QPI_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The enable bit for SPI slave En_QPI interrupt."] + #[inline(always)] + pub fn spi_slv_en_qpi_int_ena(&self) -> SPI_SLV_EN_QPI_INT_ENA_R { + SPI_SLV_EN_QPI_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The enable bit for SPI slave CMD7 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd7_int_ena(&self) -> SPI_SLV_CMD7_INT_ENA_R { + SPI_SLV_CMD7_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The enable bit for SPI slave CMD8 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd8_int_ena(&self) -> SPI_SLV_CMD8_INT_ENA_R { + SPI_SLV_CMD8_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The enable bit for SPI slave CMD9 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd9_int_ena(&self) -> SPI_SLV_CMD9_INT_ENA_R { + SPI_SLV_CMD9_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The enable bit for SPI slave CMDA interrupt."] + #[inline(always)] + pub fn spi_slv_cmda_int_ena(&self) -> SPI_SLV_CMDA_INT_ENA_R { + SPI_SLV_CMDA_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_rd_dma_done_int_ena(&self) -> SPI_SLV_RD_DMA_DONE_INT_ENA_R { + SPI_SLV_RD_DMA_DONE_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_wr_dma_done_int_ena(&self) -> SPI_SLV_WR_DMA_DONE_INT_ENA_R { + SPI_SLV_WR_DMA_DONE_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_rd_buf_done_int_ena(&self) -> SPI_SLV_RD_BUF_DONE_INT_ENA_R { + SPI_SLV_RD_BUF_DONE_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_wr_buf_done_int_ena(&self) -> SPI_SLV_WR_BUF_DONE_INT_ENA_R { + SPI_SLV_WR_BUF_DONE_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The enable bit for SPI_TRANS_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_trans_done_int_ena(&self) -> SPI_TRANS_DONE_INT_ENA_R { + SPI_TRANS_DONE_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_dma_seg_trans_done_int_ena(&self) -> SPI_DMA_SEG_TRANS_DONE_INT_ENA_R { + SPI_DMA_SEG_TRANS_DONE_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_seg_magic_err_int_ena(&self) -> SPI_SEG_MAGIC_ERR_INT_ENA_R { + SPI_SEG_MAGIC_ERR_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_slv_buf_addr_err_int_ena(&self) -> SPI_SLV_BUF_ADDR_ERR_INT_ENA_R { + SPI_SLV_BUF_ADDR_ERR_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The enable bit for SPI_SLV_CMD_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_slv_cmd_err_int_ena(&self) -> SPI_SLV_CMD_ERR_INT_ENA_R { + SPI_SLV_CMD_ERR_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mst_rx_afifo_wfull_err_int_ena(&self) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_R { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mst_tx_afifo_rempty_err_int_ena(&self) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_R { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The enable bit for SPI_APP2_INT interrupt."] + #[inline(always)] + pub fn spi_app2_int_ena(&self) -> SPI_APP2_INT_ENA_R { + SPI_APP2_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The enable bit for SPI_APP1_INT interrupt."] + #[inline(always)] + pub fn spi_app1_int_ena(&self) -> SPI_APP1_INT_ENA_R { + SPI_APP1_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DMA_INT_ENA") + .field( + "spi_dma_infifo_full_err_int_ena", + &format_args!("{}", self.spi_dma_infifo_full_err_int_ena().bit()), + ) + .field( + "spi_dma_outfifo_empty_err_int_ena", + &format_args!("{}", self.spi_dma_outfifo_empty_err_int_ena().bit()), + ) + .field( + "spi_slv_ex_qpi_int_ena", + &format_args!("{}", self.spi_slv_ex_qpi_int_ena().bit()), + ) + .field( + "spi_slv_en_qpi_int_ena", + &format_args!("{}", self.spi_slv_en_qpi_int_ena().bit()), + ) + .field( + "spi_slv_cmd7_int_ena", + &format_args!("{}", self.spi_slv_cmd7_int_ena().bit()), + ) + .field( + "spi_slv_cmd8_int_ena", + &format_args!("{}", self.spi_slv_cmd8_int_ena().bit()), + ) + .field( + "spi_slv_cmd9_int_ena", + &format_args!("{}", self.spi_slv_cmd9_int_ena().bit()), + ) + .field( + "spi_slv_cmda_int_ena", + &format_args!("{}", self.spi_slv_cmda_int_ena().bit()), + ) + .field( + "spi_slv_rd_dma_done_int_ena", + &format_args!("{}", self.spi_slv_rd_dma_done_int_ena().bit()), + ) + .field( + "spi_slv_wr_dma_done_int_ena", + &format_args!("{}", self.spi_slv_wr_dma_done_int_ena().bit()), + ) + .field( + "spi_slv_rd_buf_done_int_ena", + &format_args!("{}", self.spi_slv_rd_buf_done_int_ena().bit()), + ) + .field( + "spi_slv_wr_buf_done_int_ena", + &format_args!("{}", self.spi_slv_wr_buf_done_int_ena().bit()), + ) + .field( + "spi_trans_done_int_ena", + &format_args!("{}", self.spi_trans_done_int_ena().bit()), + ) + .field( + "spi_dma_seg_trans_done_int_ena", + &format_args!("{}", self.spi_dma_seg_trans_done_int_ena().bit()), + ) + .field( + "spi_seg_magic_err_int_ena", + &format_args!("{}", self.spi_seg_magic_err_int_ena().bit()), + ) + .field( + "spi_slv_buf_addr_err_int_ena", + &format_args!("{}", self.spi_slv_buf_addr_err_int_ena().bit()), + ) + .field( + "spi_slv_cmd_err_int_ena", + &format_args!("{}", self.spi_slv_cmd_err_int_ena().bit()), + ) + .field( + "spi_mst_rx_afifo_wfull_err_int_ena", + &format_args!("{}", self.spi_mst_rx_afifo_wfull_err_int_ena().bit()), + ) + .field( + "spi_mst_tx_afifo_rempty_err_int_ena", + &format_args!("{}", self.spi_mst_tx_afifo_rempty_err_int_ena().bit()), + ) + .field( + "spi_app2_int_ena", + &format_args!("{}", self.spi_app2_int_ena().bit()), + ) + .field( + "spi_app1_int_ena", + &format_args!("{}", self.spi_app1_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_infifo_full_err_int_ena( + &mut self, + ) -> SPI_DMA_INFIFO_FULL_ERR_INT_ENA_W { + SPI_DMA_INFIFO_FULL_ERR_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_outfifo_empty_err_int_ena( + &mut self, + ) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_W { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The enable bit for SPI slave Ex_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_ex_qpi_int_ena(&mut self) -> SPI_SLV_EX_QPI_INT_ENA_W { + SPI_SLV_EX_QPI_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The enable bit for SPI slave En_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_en_qpi_int_ena(&mut self) -> SPI_SLV_EN_QPI_INT_ENA_W { + SPI_SLV_EN_QPI_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The enable bit for SPI slave CMD7 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd7_int_ena(&mut self) -> SPI_SLV_CMD7_INT_ENA_W { + SPI_SLV_CMD7_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The enable bit for SPI slave CMD8 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd8_int_ena(&mut self) -> SPI_SLV_CMD8_INT_ENA_W { + SPI_SLV_CMD8_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The enable bit for SPI slave CMD9 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd9_int_ena(&mut self) -> SPI_SLV_CMD9_INT_ENA_W { + SPI_SLV_CMD9_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The enable bit for SPI slave CMDA interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmda_int_ena(&mut self) -> SPI_SLV_CMDA_INT_ENA_W { + SPI_SLV_CMDA_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_dma_done_int_ena( + &mut self, + ) -> SPI_SLV_RD_DMA_DONE_INT_ENA_W { + SPI_SLV_RD_DMA_DONE_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_dma_done_int_ena( + &mut self, + ) -> SPI_SLV_WR_DMA_DONE_INT_ENA_W { + SPI_SLV_WR_DMA_DONE_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_buf_done_int_ena( + &mut self, + ) -> SPI_SLV_RD_BUF_DONE_INT_ENA_W { + SPI_SLV_RD_BUF_DONE_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_buf_done_int_ena( + &mut self, + ) -> SPI_SLV_WR_BUF_DONE_INT_ENA_W { + SPI_SLV_WR_BUF_DONE_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - The enable bit for SPI_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_trans_done_int_ena(&mut self) -> SPI_TRANS_DONE_INT_ENA_W { + SPI_TRANS_DONE_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_seg_trans_done_int_ena( + &mut self, + ) -> SPI_DMA_SEG_TRANS_DONE_INT_ENA_W { + SPI_DMA_SEG_TRANS_DONE_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_seg_magic_err_int_ena( + &mut self, + ) -> SPI_SEG_MAGIC_ERR_INT_ENA_W { + SPI_SEG_MAGIC_ERR_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_buf_addr_err_int_ena( + &mut self, + ) -> SPI_SLV_BUF_ADDR_ERR_INT_ENA_W { + SPI_SLV_BUF_ADDR_ERR_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - The enable bit for SPI_SLV_CMD_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd_err_int_ena(&mut self) -> SPI_SLV_CMD_ERR_INT_ENA_W { + SPI_SLV_CMD_ERR_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_rx_afifo_wfull_err_int_ena( + &mut self, + ) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_W { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 18 - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_tx_afifo_rempty_err_int_ena( + &mut self, + ) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_W { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_W::new(self, 18) + } + #[doc = "Bit 19 - The enable bit for SPI_APP2_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app2_int_ena(&mut self) -> SPI_APP2_INT_ENA_W { + SPI_APP2_INT_ENA_W::new(self, 19) + } + #[doc = "Bit 20 - The enable bit for SPI_APP1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app1_int_ena(&mut self) -> SPI_APP1_INT_ENA_W { + SPI_APP1_INT_ENA_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_INT_ENA_SPEC; +impl crate::RegisterSpec for SPI_DMA_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_dma_int_ena::R`](R) reader structure"] +impl crate::Readable for SPI_DMA_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_dma_int_ena::W`](W) writer structure"] +impl crate::Writable for SPI_DMA_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DMA_INT_ENA to value 0"] +impl crate::Resettable for SPI_DMA_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_dma_int_raw.rs b/esp32p4/src/spi2/spi_dma_int_raw.rs new file mode 100644 index 0000000000..79c585cc60 --- /dev/null +++ b/esp32p4/src/spi2/spi_dma_int_raw.rs @@ -0,0 +1,468 @@ +#[doc = "Register `SPI_DMA_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DMA_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_RAW` reader - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_RAW` writer - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW` reader - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW` writer - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EX_QPI_INT_RAW` reader - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."] +pub type SPI_SLV_EX_QPI_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EX_QPI_INT_RAW` writer - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."] +pub type SPI_SLV_EX_QPI_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EN_QPI_INT_RAW` reader - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."] +pub type SPI_SLV_EN_QPI_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EN_QPI_INT_RAW` writer - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."] +pub type SPI_SLV_EN_QPI_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD7_INT_RAW` reader - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD7_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD7_INT_RAW` writer - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD7_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD8_INT_RAW` reader - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD8_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD8_INT_RAW` writer - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD8_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD9_INT_RAW` reader - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD9_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD9_INT_RAW` writer - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD9_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMDA_INT_RAW` reader - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."] +pub type SPI_SLV_CMDA_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMDA_INT_RAW` writer - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."] +pub type SPI_SLV_CMDA_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_RAW` reader - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."] +pub type SPI_SLV_RD_DMA_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_RAW` writer - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."] +pub type SPI_SLV_RD_DMA_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_RAW` reader - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."] +pub type SPI_SLV_WR_DMA_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_RAW` writer - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."] +pub type SPI_SLV_WR_DMA_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_RAW` reader - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."] +pub type SPI_SLV_RD_BUF_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_RAW` writer - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."] +pub type SPI_SLV_RD_BUF_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_RAW` reader - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."] +pub type SPI_SLV_WR_BUF_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_RAW` writer - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."] +pub type SPI_SLV_WR_BUF_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_TRANS_DONE_INT_RAW` reader - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."] +pub type SPI_TRANS_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_TRANS_DONE_INT_RAW` writer - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."] +pub type SPI_TRANS_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_RAW` reader - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_RAW` writer - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SEG_MAGIC_ERR_INT_RAW` reader - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others."] +pub type SPI_SEG_MAGIC_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SEG_MAGIC_ERR_INT_RAW` writer - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others."] +pub type SPI_SEG_MAGIC_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_RAW` reader - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_RAW` writer - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_RAW` reader - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."] +pub type SPI_SLV_CMD_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_RAW` writer - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."] +pub type SPI_SLV_CMD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW` reader - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW` writer - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW` reader - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW` writer - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP2_INT_RAW` reader - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."] +pub type SPI_APP2_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_APP2_INT_RAW` writer - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."] +pub type SPI_APP2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP1_INT_RAW` reader - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."] +pub type SPI_APP1_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_APP1_INT_RAW` writer - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."] +pub type SPI_APP1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."] + #[inline(always)] + pub fn spi_dma_infifo_full_err_int_raw(&self) -> SPI_DMA_INFIFO_FULL_ERR_INT_RAW_R { + SPI_DMA_INFIFO_FULL_ERR_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."] + #[inline(always)] + pub fn spi_dma_outfifo_empty_err_int_raw(&self) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_R { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_ex_qpi_int_raw(&self) -> SPI_SLV_EX_QPI_INT_RAW_R { + SPI_SLV_EX_QPI_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_en_qpi_int_raw(&self) -> SPI_SLV_EN_QPI_INT_RAW_R { + SPI_SLV_EN_QPI_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_cmd7_int_raw(&self) -> SPI_SLV_CMD7_INT_RAW_R { + SPI_SLV_CMD7_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_cmd8_int_raw(&self) -> SPI_SLV_CMD8_INT_RAW_R { + SPI_SLV_CMD8_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_cmd9_int_raw(&self) -> SPI_SLV_CMD9_INT_RAW_R { + SPI_SLV_CMD9_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_cmda_int_raw(&self) -> SPI_SLV_CMDA_INT_RAW_R { + SPI_SLV_CMDA_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_rd_dma_done_int_raw(&self) -> SPI_SLV_RD_DMA_DONE_INT_RAW_R { + SPI_SLV_RD_DMA_DONE_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_wr_dma_done_int_raw(&self) -> SPI_SLV_WR_DMA_DONE_INT_RAW_R { + SPI_SLV_WR_DMA_DONE_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_rd_buf_done_int_raw(&self) -> SPI_SLV_RD_BUF_DONE_INT_RAW_R { + SPI_SLV_RD_BUF_DONE_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_wr_buf_done_int_raw(&self) -> SPI_SLV_WR_BUF_DONE_INT_RAW_R { + SPI_SLV_WR_BUF_DONE_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."] + #[inline(always)] + pub fn spi_trans_done_int_raw(&self) -> SPI_TRANS_DONE_INT_RAW_R { + SPI_TRANS_DONE_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."] + #[inline(always)] + pub fn spi_dma_seg_trans_done_int_raw(&self) -> SPI_DMA_SEG_TRANS_DONE_INT_RAW_R { + SPI_DMA_SEG_TRANS_DONE_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others."] + #[inline(always)] + pub fn spi_seg_magic_err_int_raw(&self) -> SPI_SEG_MAGIC_ERR_INT_RAW_R { + SPI_SEG_MAGIC_ERR_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."] + #[inline(always)] + pub fn spi_slv_buf_addr_err_int_raw(&self) -> SPI_SLV_BUF_ADDR_ERR_INT_RAW_R { + SPI_SLV_BUF_ADDR_ERR_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."] + #[inline(always)] + pub fn spi_slv_cmd_err_int_raw(&self) -> SPI_SLV_CMD_ERR_INT_RAW_R { + SPI_SLV_CMD_ERR_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."] + #[inline(always)] + pub fn spi_mst_rx_afifo_wfull_err_int_raw(&self) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_R { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."] + #[inline(always)] + pub fn spi_mst_tx_afifo_rempty_err_int_raw(&self) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_R { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."] + #[inline(always)] + pub fn spi_app2_int_raw(&self) -> SPI_APP2_INT_RAW_R { + SPI_APP2_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."] + #[inline(always)] + pub fn spi_app1_int_raw(&self) -> SPI_APP1_INT_RAW_R { + SPI_APP1_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DMA_INT_RAW") + .field( + "spi_dma_infifo_full_err_int_raw", + &format_args!("{}", self.spi_dma_infifo_full_err_int_raw().bit()), + ) + .field( + "spi_dma_outfifo_empty_err_int_raw", + &format_args!("{}", self.spi_dma_outfifo_empty_err_int_raw().bit()), + ) + .field( + "spi_slv_ex_qpi_int_raw", + &format_args!("{}", self.spi_slv_ex_qpi_int_raw().bit()), + ) + .field( + "spi_slv_en_qpi_int_raw", + &format_args!("{}", self.spi_slv_en_qpi_int_raw().bit()), + ) + .field( + "spi_slv_cmd7_int_raw", + &format_args!("{}", self.spi_slv_cmd7_int_raw().bit()), + ) + .field( + "spi_slv_cmd8_int_raw", + &format_args!("{}", self.spi_slv_cmd8_int_raw().bit()), + ) + .field( + "spi_slv_cmd9_int_raw", + &format_args!("{}", self.spi_slv_cmd9_int_raw().bit()), + ) + .field( + "spi_slv_cmda_int_raw", + &format_args!("{}", self.spi_slv_cmda_int_raw().bit()), + ) + .field( + "spi_slv_rd_dma_done_int_raw", + &format_args!("{}", self.spi_slv_rd_dma_done_int_raw().bit()), + ) + .field( + "spi_slv_wr_dma_done_int_raw", + &format_args!("{}", self.spi_slv_wr_dma_done_int_raw().bit()), + ) + .field( + "spi_slv_rd_buf_done_int_raw", + &format_args!("{}", self.spi_slv_rd_buf_done_int_raw().bit()), + ) + .field( + "spi_slv_wr_buf_done_int_raw", + &format_args!("{}", self.spi_slv_wr_buf_done_int_raw().bit()), + ) + .field( + "spi_trans_done_int_raw", + &format_args!("{}", self.spi_trans_done_int_raw().bit()), + ) + .field( + "spi_dma_seg_trans_done_int_raw", + &format_args!("{}", self.spi_dma_seg_trans_done_int_raw().bit()), + ) + .field( + "spi_seg_magic_err_int_raw", + &format_args!("{}", self.spi_seg_magic_err_int_raw().bit()), + ) + .field( + "spi_slv_buf_addr_err_int_raw", + &format_args!("{}", self.spi_slv_buf_addr_err_int_raw().bit()), + ) + .field( + "spi_slv_cmd_err_int_raw", + &format_args!("{}", self.spi_slv_cmd_err_int_raw().bit()), + ) + .field( + "spi_mst_rx_afifo_wfull_err_int_raw", + &format_args!("{}", self.spi_mst_rx_afifo_wfull_err_int_raw().bit()), + ) + .field( + "spi_mst_tx_afifo_rempty_err_int_raw", + &format_args!("{}", self.spi_mst_tx_afifo_rempty_err_int_raw().bit()), + ) + .field( + "spi_app2_int_raw", + &format_args!("{}", self.spi_app2_int_raw().bit()), + ) + .field( + "spi_app1_int_raw", + &format_args!("{}", self.spi_app1_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_dma_infifo_full_err_int_raw( + &mut self, + ) -> SPI_DMA_INFIFO_FULL_ERR_INT_RAW_W { + SPI_DMA_INFIFO_FULL_ERR_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_dma_outfifo_empty_err_int_raw( + &mut self, + ) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_W { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_ex_qpi_int_raw(&mut self) -> SPI_SLV_EX_QPI_INT_RAW_W { + SPI_SLV_EX_QPI_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_en_qpi_int_raw(&mut self) -> SPI_SLV_EN_QPI_INT_RAW_W { + SPI_SLV_EN_QPI_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd7_int_raw(&mut self) -> SPI_SLV_CMD7_INT_RAW_W { + SPI_SLV_CMD7_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd8_int_raw(&mut self) -> SPI_SLV_CMD8_INT_RAW_W { + SPI_SLV_CMD8_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd9_int_raw(&mut self) -> SPI_SLV_CMD9_INT_RAW_W { + SPI_SLV_CMD9_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmda_int_raw(&mut self) -> SPI_SLV_CMDA_INT_RAW_W { + SPI_SLV_CMDA_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_dma_done_int_raw( + &mut self, + ) -> SPI_SLV_RD_DMA_DONE_INT_RAW_W { + SPI_SLV_RD_DMA_DONE_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_dma_done_int_raw( + &mut self, + ) -> SPI_SLV_WR_DMA_DONE_INT_RAW_W { + SPI_SLV_WR_DMA_DONE_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_buf_done_int_raw( + &mut self, + ) -> SPI_SLV_RD_BUF_DONE_INT_RAW_W { + SPI_SLV_RD_BUF_DONE_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_buf_done_int_raw( + &mut self, + ) -> SPI_SLV_WR_BUF_DONE_INT_RAW_W { + SPI_SLV_WR_BUF_DONE_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 12 - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."] + #[inline(always)] + #[must_use] + pub fn spi_trans_done_int_raw(&mut self) -> SPI_TRANS_DONE_INT_RAW_W { + SPI_TRANS_DONE_INT_RAW_W::new(self, 12) + } + #[doc = "Bit 13 - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."] + #[inline(always)] + #[must_use] + pub fn spi_dma_seg_trans_done_int_raw( + &mut self, + ) -> SPI_DMA_SEG_TRANS_DONE_INT_RAW_W { + SPI_DMA_SEG_TRANS_DONE_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 14 - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others."] + #[inline(always)] + #[must_use] + pub fn spi_seg_magic_err_int_raw( + &mut self, + ) -> SPI_SEG_MAGIC_ERR_INT_RAW_W { + SPI_SEG_MAGIC_ERR_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_buf_addr_err_int_raw( + &mut self, + ) -> SPI_SLV_BUF_ADDR_ERR_INT_RAW_W { + SPI_SLV_BUF_ADDR_ERR_INT_RAW_W::new(self, 15) + } + #[doc = "Bit 16 - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd_err_int_raw(&mut self) -> SPI_SLV_CMD_ERR_INT_RAW_W { + SPI_SLV_CMD_ERR_INT_RAW_W::new(self, 16) + } + #[doc = "Bit 17 - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mst_rx_afifo_wfull_err_int_raw( + &mut self, + ) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_W { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_W::new(self, 17) + } + #[doc = "Bit 18 - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mst_tx_afifo_rempty_err_int_raw( + &mut self, + ) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_W { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_W::new(self, 18) + } + #[doc = "Bit 19 - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."] + #[inline(always)] + #[must_use] + pub fn spi_app2_int_raw(&mut self) -> SPI_APP2_INT_RAW_W { + SPI_APP2_INT_RAW_W::new(self, 19) + } + #[doc = "Bit 20 - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."] + #[inline(always)] + #[must_use] + pub fn spi_app1_int_raw(&mut self) -> SPI_APP1_INT_RAW_W { + SPI_APP1_INT_RAW_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_INT_RAW_SPEC; +impl crate::RegisterSpec for SPI_DMA_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_dma_int_raw::R`](R) reader structure"] +impl crate::Readable for SPI_DMA_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_dma_int_raw::W`](W) writer structure"] +impl crate::Writable for SPI_DMA_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DMA_INT_RAW to value 0"] +impl crate::Resettable for SPI_DMA_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_dma_int_set.rs b/esp32p4/src/spi2/spi_dma_int_set.rs new file mode 100644 index 0000000000..86aa8167f6 --- /dev/null +++ b/esp32p4/src/spi2/spi_dma_int_set.rs @@ -0,0 +1,224 @@ +#[doc = "Register `SPI_DMA_INT_SET` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_SET` writer - The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET` writer - The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EX_QPI_INT_SET` writer - The software set bit for SPI slave Ex_QPI interrupt."] +pub type SPI_SLV_EX_QPI_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EN_QPI_INT_SET` writer - The software set bit for SPI slave En_QPI interrupt."] +pub type SPI_SLV_EN_QPI_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD7_INT_SET` writer - The software set bit for SPI slave CMD7 interrupt."] +pub type SPI_SLV_CMD7_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD8_INT_SET` writer - The software set bit for SPI slave CMD8 interrupt."] +pub type SPI_SLV_CMD8_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD9_INT_SET` writer - The software set bit for SPI slave CMD9 interrupt."] +pub type SPI_SLV_CMD9_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMDA_INT_SET` writer - The software set bit for SPI slave CMDA interrupt."] +pub type SPI_SLV_CMDA_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_SET` writer - The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] +pub type SPI_SLV_RD_DMA_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_SET` writer - The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] +pub type SPI_SLV_WR_DMA_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_SET` writer - The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] +pub type SPI_SLV_RD_BUF_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_SET` writer - The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] +pub type SPI_SLV_WR_BUF_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_TRANS_DONE_INT_SET` writer - The software set bit for SPI_TRANS_DONE_INT interrupt."] +pub type SPI_TRANS_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_SET` writer - The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SEG_MAGIC_ERR_INT_SET` writer - The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt."] +pub type SPI_SEG_MAGIC_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_SET` writer - The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_SET` writer - The software set bit for SPI_SLV_CMD_ERR_INT interrupt."] +pub type SPI_SLV_CMD_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET` writer - The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET` writer - The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP2_INT_SET` writer - The software set bit for SPI_APP2_INT interrupt."] +pub type SPI_APP2_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP1_INT_SET` writer - The software set bit for SPI_APP1_INT interrupt."] +pub type SPI_APP1_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_infifo_full_err_int_set( + &mut self, + ) -> SPI_DMA_INFIFO_FULL_ERR_INT_SET_W { + SPI_DMA_INFIFO_FULL_ERR_INT_SET_W::new(self, 0) + } + #[doc = "Bit 1 - The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_outfifo_empty_err_int_set( + &mut self, + ) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_W { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_W::new(self, 1) + } + #[doc = "Bit 2 - The software set bit for SPI slave Ex_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_ex_qpi_int_set(&mut self) -> SPI_SLV_EX_QPI_INT_SET_W { + SPI_SLV_EX_QPI_INT_SET_W::new(self, 2) + } + #[doc = "Bit 3 - The software set bit for SPI slave En_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_en_qpi_int_set(&mut self) -> SPI_SLV_EN_QPI_INT_SET_W { + SPI_SLV_EN_QPI_INT_SET_W::new(self, 3) + } + #[doc = "Bit 4 - The software set bit for SPI slave CMD7 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd7_int_set(&mut self) -> SPI_SLV_CMD7_INT_SET_W { + SPI_SLV_CMD7_INT_SET_W::new(self, 4) + } + #[doc = "Bit 5 - The software set bit for SPI slave CMD8 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd8_int_set(&mut self) -> SPI_SLV_CMD8_INT_SET_W { + SPI_SLV_CMD8_INT_SET_W::new(self, 5) + } + #[doc = "Bit 6 - The software set bit for SPI slave CMD9 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd9_int_set(&mut self) -> SPI_SLV_CMD9_INT_SET_W { + SPI_SLV_CMD9_INT_SET_W::new(self, 6) + } + #[doc = "Bit 7 - The software set bit for SPI slave CMDA interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmda_int_set(&mut self) -> SPI_SLV_CMDA_INT_SET_W { + SPI_SLV_CMDA_INT_SET_W::new(self, 7) + } + #[doc = "Bit 8 - The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_dma_done_int_set( + &mut self, + ) -> SPI_SLV_RD_DMA_DONE_INT_SET_W { + SPI_SLV_RD_DMA_DONE_INT_SET_W::new(self, 8) + } + #[doc = "Bit 9 - The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_dma_done_int_set( + &mut self, + ) -> SPI_SLV_WR_DMA_DONE_INT_SET_W { + SPI_SLV_WR_DMA_DONE_INT_SET_W::new(self, 9) + } + #[doc = "Bit 10 - The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_buf_done_int_set( + &mut self, + ) -> SPI_SLV_RD_BUF_DONE_INT_SET_W { + SPI_SLV_RD_BUF_DONE_INT_SET_W::new(self, 10) + } + #[doc = "Bit 11 - The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_buf_done_int_set( + &mut self, + ) -> SPI_SLV_WR_BUF_DONE_INT_SET_W { + SPI_SLV_WR_BUF_DONE_INT_SET_W::new(self, 11) + } + #[doc = "Bit 12 - The software set bit for SPI_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_trans_done_int_set(&mut self) -> SPI_TRANS_DONE_INT_SET_W { + SPI_TRANS_DONE_INT_SET_W::new(self, 12) + } + #[doc = "Bit 13 - The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_seg_trans_done_int_set( + &mut self, + ) -> SPI_DMA_SEG_TRANS_DONE_INT_SET_W { + SPI_DMA_SEG_TRANS_DONE_INT_SET_W::new(self, 13) + } + #[doc = "Bit 14 - The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_seg_magic_err_int_set( + &mut self, + ) -> SPI_SEG_MAGIC_ERR_INT_SET_W { + SPI_SEG_MAGIC_ERR_INT_SET_W::new(self, 14) + } + #[doc = "Bit 15 - The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_buf_addr_err_int_set( + &mut self, + ) -> SPI_SLV_BUF_ADDR_ERR_INT_SET_W { + SPI_SLV_BUF_ADDR_ERR_INT_SET_W::new(self, 15) + } + #[doc = "Bit 16 - The software set bit for SPI_SLV_CMD_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd_err_int_set(&mut self) -> SPI_SLV_CMD_ERR_INT_SET_W { + SPI_SLV_CMD_ERR_INT_SET_W::new(self, 16) + } + #[doc = "Bit 17 - The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_rx_afifo_wfull_err_int_set( + &mut self, + ) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_W { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_W::new(self, 17) + } + #[doc = "Bit 18 - The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_tx_afifo_rempty_err_int_set( + &mut self, + ) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_W { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_W::new(self, 18) + } + #[doc = "Bit 19 - The software set bit for SPI_APP2_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app2_int_set(&mut self) -> SPI_APP2_INT_SET_W { + SPI_APP2_INT_SET_W::new(self, 19) + } + #[doc = "Bit 20 - The software set bit for SPI_APP1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app1_int_set(&mut self) -> SPI_APP1_INT_SET_W { + SPI_APP1_INT_SET_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI interrupt software set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_INT_SET_SPEC; +impl crate::RegisterSpec for SPI_DMA_INT_SET_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`spi_dma_int_set::W`](W) writer structure"] +impl crate::Writable for SPI_DMA_INT_SET_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DMA_INT_SET to value 0"] +impl crate::Resettable for SPI_DMA_INT_SET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_dma_int_st.rs b/esp32p4/src/spi2/spi_dma_int_st.rs new file mode 100644 index 0000000000..d3e08ec1f0 --- /dev/null +++ b/esp32p4/src/spi2/spi_dma_int_st.rs @@ -0,0 +1,259 @@ +#[doc = "Register `SPI_DMA_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_ST` reader - The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST` reader - The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EX_QPI_INT_ST` reader - The status bit for SPI slave Ex_QPI interrupt."] +pub type SPI_SLV_EX_QPI_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EN_QPI_INT_ST` reader - The status bit for SPI slave En_QPI interrupt."] +pub type SPI_SLV_EN_QPI_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD7_INT_ST` reader - The status bit for SPI slave CMD7 interrupt."] +pub type SPI_SLV_CMD7_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD8_INT_ST` reader - The status bit for SPI slave CMD8 interrupt."] +pub type SPI_SLV_CMD8_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD9_INT_ST` reader - The status bit for SPI slave CMD9 interrupt."] +pub type SPI_SLV_CMD9_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMDA_INT_ST` reader - The status bit for SPI slave CMDA interrupt."] +pub type SPI_SLV_CMDA_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_ST` reader - The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] +pub type SPI_SLV_RD_DMA_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_ST` reader - The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] +pub type SPI_SLV_WR_DMA_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_ST` reader - The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] +pub type SPI_SLV_RD_BUF_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_ST` reader - The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] +pub type SPI_SLV_WR_BUF_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_TRANS_DONE_INT_ST` reader - The status bit for SPI_TRANS_DONE_INT interrupt."] +pub type SPI_TRANS_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_ST` reader - The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SEG_MAGIC_ERR_INT_ST` reader - The status bit for SPI_SEG_MAGIC_ERR_INT interrupt."] +pub type SPI_SEG_MAGIC_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_ST` reader - The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_ST` reader - The status bit for SPI_SLV_CMD_ERR_INT interrupt."] +pub type SPI_SLV_CMD_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST` reader - The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST` reader - The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_APP2_INT_ST` reader - The status bit for SPI_APP2_INT interrupt."] +pub type SPI_APP2_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_APP1_INT_ST` reader - The status bit for SPI_APP1_INT interrupt."] +pub type SPI_APP1_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_dma_infifo_full_err_int_st(&self) -> SPI_DMA_INFIFO_FULL_ERR_INT_ST_R { + SPI_DMA_INFIFO_FULL_ERR_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_dma_outfifo_empty_err_int_st(&self) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_R { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The status bit for SPI slave Ex_QPI interrupt."] + #[inline(always)] + pub fn spi_slv_ex_qpi_int_st(&self) -> SPI_SLV_EX_QPI_INT_ST_R { + SPI_SLV_EX_QPI_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The status bit for SPI slave En_QPI interrupt."] + #[inline(always)] + pub fn spi_slv_en_qpi_int_st(&self) -> SPI_SLV_EN_QPI_INT_ST_R { + SPI_SLV_EN_QPI_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The status bit for SPI slave CMD7 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd7_int_st(&self) -> SPI_SLV_CMD7_INT_ST_R { + SPI_SLV_CMD7_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The status bit for SPI slave CMD8 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd8_int_st(&self) -> SPI_SLV_CMD8_INT_ST_R { + SPI_SLV_CMD8_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The status bit for SPI slave CMD9 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd9_int_st(&self) -> SPI_SLV_CMD9_INT_ST_R { + SPI_SLV_CMD9_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The status bit for SPI slave CMDA interrupt."] + #[inline(always)] + pub fn spi_slv_cmda_int_st(&self) -> SPI_SLV_CMDA_INT_ST_R { + SPI_SLV_CMDA_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_rd_dma_done_int_st(&self) -> SPI_SLV_RD_DMA_DONE_INT_ST_R { + SPI_SLV_RD_DMA_DONE_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_wr_dma_done_int_st(&self) -> SPI_SLV_WR_DMA_DONE_INT_ST_R { + SPI_SLV_WR_DMA_DONE_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_rd_buf_done_int_st(&self) -> SPI_SLV_RD_BUF_DONE_INT_ST_R { + SPI_SLV_RD_BUF_DONE_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_wr_buf_done_int_st(&self) -> SPI_SLV_WR_BUF_DONE_INT_ST_R { + SPI_SLV_WR_BUF_DONE_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The status bit for SPI_TRANS_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_trans_done_int_st(&self) -> SPI_TRANS_DONE_INT_ST_R { + SPI_TRANS_DONE_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_dma_seg_trans_done_int_st(&self) -> SPI_DMA_SEG_TRANS_DONE_INT_ST_R { + SPI_DMA_SEG_TRANS_DONE_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The status bit for SPI_SEG_MAGIC_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_seg_magic_err_int_st(&self) -> SPI_SEG_MAGIC_ERR_INT_ST_R { + SPI_SEG_MAGIC_ERR_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_slv_buf_addr_err_int_st(&self) -> SPI_SLV_BUF_ADDR_ERR_INT_ST_R { + SPI_SLV_BUF_ADDR_ERR_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The status bit for SPI_SLV_CMD_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_slv_cmd_err_int_st(&self) -> SPI_SLV_CMD_ERR_INT_ST_R { + SPI_SLV_CMD_ERR_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mst_rx_afifo_wfull_err_int_st(&self) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_R { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mst_tx_afifo_rempty_err_int_st(&self) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_R { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The status bit for SPI_APP2_INT interrupt."] + #[inline(always)] + pub fn spi_app2_int_st(&self) -> SPI_APP2_INT_ST_R { + SPI_APP2_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The status bit for SPI_APP1_INT interrupt."] + #[inline(always)] + pub fn spi_app1_int_st(&self) -> SPI_APP1_INT_ST_R { + SPI_APP1_INT_ST_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DMA_INT_ST") + .field( + "spi_dma_infifo_full_err_int_st", + &format_args!("{}", self.spi_dma_infifo_full_err_int_st().bit()), + ) + .field( + "spi_dma_outfifo_empty_err_int_st", + &format_args!("{}", self.spi_dma_outfifo_empty_err_int_st().bit()), + ) + .field( + "spi_slv_ex_qpi_int_st", + &format_args!("{}", self.spi_slv_ex_qpi_int_st().bit()), + ) + .field( + "spi_slv_en_qpi_int_st", + &format_args!("{}", self.spi_slv_en_qpi_int_st().bit()), + ) + .field( + "spi_slv_cmd7_int_st", + &format_args!("{}", self.spi_slv_cmd7_int_st().bit()), + ) + .field( + "spi_slv_cmd8_int_st", + &format_args!("{}", self.spi_slv_cmd8_int_st().bit()), + ) + .field( + "spi_slv_cmd9_int_st", + &format_args!("{}", self.spi_slv_cmd9_int_st().bit()), + ) + .field( + "spi_slv_cmda_int_st", + &format_args!("{}", self.spi_slv_cmda_int_st().bit()), + ) + .field( + "spi_slv_rd_dma_done_int_st", + &format_args!("{}", self.spi_slv_rd_dma_done_int_st().bit()), + ) + .field( + "spi_slv_wr_dma_done_int_st", + &format_args!("{}", self.spi_slv_wr_dma_done_int_st().bit()), + ) + .field( + "spi_slv_rd_buf_done_int_st", + &format_args!("{}", self.spi_slv_rd_buf_done_int_st().bit()), + ) + .field( + "spi_slv_wr_buf_done_int_st", + &format_args!("{}", self.spi_slv_wr_buf_done_int_st().bit()), + ) + .field( + "spi_trans_done_int_st", + &format_args!("{}", self.spi_trans_done_int_st().bit()), + ) + .field( + "spi_dma_seg_trans_done_int_st", + &format_args!("{}", self.spi_dma_seg_trans_done_int_st().bit()), + ) + .field( + "spi_seg_magic_err_int_st", + &format_args!("{}", self.spi_seg_magic_err_int_st().bit()), + ) + .field( + "spi_slv_buf_addr_err_int_st", + &format_args!("{}", self.spi_slv_buf_addr_err_int_st().bit()), + ) + .field( + "spi_slv_cmd_err_int_st", + &format_args!("{}", self.spi_slv_cmd_err_int_st().bit()), + ) + .field( + "spi_mst_rx_afifo_wfull_err_int_st", + &format_args!("{}", self.spi_mst_rx_afifo_wfull_err_int_st().bit()), + ) + .field( + "spi_mst_tx_afifo_rempty_err_int_st", + &format_args!("{}", self.spi_mst_tx_afifo_rempty_err_int_st().bit()), + ) + .field( + "spi_app2_int_st", + &format_args!("{}", self.spi_app2_int_st().bit()), + ) + .field( + "spi_app1_int_st", + &format_args!("{}", self.spi_app1_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "SPI interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_INT_ST_SPEC; +impl crate::RegisterSpec for SPI_DMA_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_dma_int_st::R`](R) reader structure"] +impl crate::Readable for SPI_DMA_INT_ST_SPEC {} +#[doc = "`reset()` method sets SPI_DMA_INT_ST to value 0"] +impl crate::Resettable for SPI_DMA_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_dout_mode.rs b/esp32p4/src/spi2/spi_dout_mode.rs new file mode 100644 index 0000000000..4c7fb39898 --- /dev/null +++ b/esp32p4/src/spi2/spi_dout_mode.rs @@ -0,0 +1,218 @@ +#[doc = "Register `SPI_DOUT_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DOUT_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DOUT0_MODE` reader - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT0_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT0_MODE` writer - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT0_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DOUT1_MODE` reader - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT1_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT1_MODE` writer - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT1_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DOUT2_MODE` reader - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT2_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT2_MODE` writer - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT2_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DOUT3_MODE` reader - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT3_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT3_MODE` writer - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT3_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DOUT4_MODE` reader - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT4_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT4_MODE` writer - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT4_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DOUT5_MODE` reader - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT5_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT5_MODE` writer - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT5_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DOUT6_MODE` reader - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT6_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT6_MODE` writer - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT6_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DOUT7_MODE` reader - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT7_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT7_MODE` writer - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT7_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_D_DQS_MODE` reader - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_D_DQS_MODE_R = crate::BitReader; +#[doc = "Field `SPI_D_DQS_MODE` writer - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_D_DQS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout0_mode(&self) -> SPI_DOUT0_MODE_R { + SPI_DOUT0_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout1_mode(&self) -> SPI_DOUT1_MODE_R { + SPI_DOUT1_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout2_mode(&self) -> SPI_DOUT2_MODE_R { + SPI_DOUT2_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout3_mode(&self) -> SPI_DOUT3_MODE_R { + SPI_DOUT3_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout4_mode(&self) -> SPI_DOUT4_MODE_R { + SPI_DOUT4_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout5_mode(&self) -> SPI_DOUT5_MODE_R { + SPI_DOUT5_MODE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout6_mode(&self) -> SPI_DOUT6_MODE_R { + SPI_DOUT6_MODE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout7_mode(&self) -> SPI_DOUT7_MODE_R { + SPI_DOUT7_MODE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_d_dqs_mode(&self) -> SPI_D_DQS_MODE_R { + SPI_D_DQS_MODE_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DOUT_MODE") + .field( + "spi_dout0_mode", + &format_args!("{}", self.spi_dout0_mode().bit()), + ) + .field( + "spi_dout1_mode", + &format_args!("{}", self.spi_dout1_mode().bit()), + ) + .field( + "spi_dout2_mode", + &format_args!("{}", self.spi_dout2_mode().bit()), + ) + .field( + "spi_dout3_mode", + &format_args!("{}", self.spi_dout3_mode().bit()), + ) + .field( + "spi_dout4_mode", + &format_args!("{}", self.spi_dout4_mode().bit()), + ) + .field( + "spi_dout5_mode", + &format_args!("{}", self.spi_dout5_mode().bit()), + ) + .field( + "spi_dout6_mode", + &format_args!("{}", self.spi_dout6_mode().bit()), + ) + .field( + "spi_dout7_mode", + &format_args!("{}", self.spi_dout7_mode().bit()), + ) + .field( + "spi_d_dqs_mode", + &format_args!("{}", self.spi_d_dqs_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout0_mode(&mut self) -> SPI_DOUT0_MODE_W { + SPI_DOUT0_MODE_W::new(self, 0) + } + #[doc = "Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout1_mode(&mut self) -> SPI_DOUT1_MODE_W { + SPI_DOUT1_MODE_W::new(self, 1) + } + #[doc = "Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout2_mode(&mut self) -> SPI_DOUT2_MODE_W { + SPI_DOUT2_MODE_W::new(self, 2) + } + #[doc = "Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout3_mode(&mut self) -> SPI_DOUT3_MODE_W { + SPI_DOUT3_MODE_W::new(self, 3) + } + #[doc = "Bit 4 - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout4_mode(&mut self) -> SPI_DOUT4_MODE_W { + SPI_DOUT4_MODE_W::new(self, 4) + } + #[doc = "Bit 5 - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout5_mode(&mut self) -> SPI_DOUT5_MODE_W { + SPI_DOUT5_MODE_W::new(self, 5) + } + #[doc = "Bit 6 - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout6_mode(&mut self) -> SPI_DOUT6_MODE_W { + SPI_DOUT6_MODE_W::new(self, 6) + } + #[doc = "Bit 7 - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout7_mode(&mut self) -> SPI_DOUT7_MODE_W { + SPI_DOUT7_MODE_W::new(self, 7) + } + #[doc = "Bit 8 - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_d_dqs_mode(&mut self) -> SPI_D_DQS_MODE_W { + SPI_D_DQS_MODE_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI output delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dout_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dout_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DOUT_MODE_SPEC; +impl crate::RegisterSpec for SPI_DOUT_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_dout_mode::R`](R) reader structure"] +impl crate::Readable for SPI_DOUT_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_dout_mode::W`](W) writer structure"] +impl crate::Writable for SPI_DOUT_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DOUT_MODE to value 0"] +impl crate::Resettable for SPI_DOUT_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_misc.rs b/esp32p4/src/spi2/spi_misc.rs new file mode 100644 index 0000000000..d2669b76e4 --- /dev/null +++ b/esp32p4/src/spi2/spi_misc.rs @@ -0,0 +1,349 @@ +#[doc = "Register `SPI_MISC` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MISC` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_CS0_DIS` reader - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."] +pub type SPI_CS0_DIS_R = crate::BitReader; +#[doc = "Field `SPI_CS0_DIS` writer - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."] +pub type SPI_CS0_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS1_DIS` reader - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."] +pub type SPI_CS1_DIS_R = crate::BitReader; +#[doc = "Field `SPI_CS1_DIS` writer - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."] +pub type SPI_CS1_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS2_DIS` reader - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."] +pub type SPI_CS2_DIS_R = crate::BitReader; +#[doc = "Field `SPI_CS2_DIS` writer - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."] +pub type SPI_CS2_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS3_DIS` reader - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."] +pub type SPI_CS3_DIS_R = crate::BitReader; +#[doc = "Field `SPI_CS3_DIS` writer - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."] +pub type SPI_CS3_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS4_DIS` reader - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."] +pub type SPI_CS4_DIS_R = crate::BitReader; +#[doc = "Field `SPI_CS4_DIS` writer - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."] +pub type SPI_CS4_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS5_DIS` reader - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."] +pub type SPI_CS5_DIS_R = crate::BitReader; +#[doc = "Field `SPI_CS5_DIS` writer - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."] +pub type SPI_CS5_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CK_DIS` reader - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."] +pub type SPI_CK_DIS_R = crate::BitReader; +#[doc = "Field `SPI_CK_DIS` writer - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."] +pub type SPI_CK_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MASTER_CS_POL` reader - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."] +pub type SPI_MASTER_CS_POL_R = crate::FieldReader; +#[doc = "Field `SPI_MASTER_CS_POL` writer - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."] +pub type SPI_MASTER_CS_POL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_CLK_DATA_DTR_EN` reader - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."] +pub type SPI_CLK_DATA_DTR_EN_R = crate::BitReader; +#[doc = "Field `SPI_CLK_DATA_DTR_EN` writer - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."] +pub type SPI_CLK_DATA_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DATA_DTR_EN` reader - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."] +pub type SPI_DATA_DTR_EN_R = crate::BitReader; +#[doc = "Field `SPI_DATA_DTR_EN` writer - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."] +pub type SPI_DATA_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_ADDR_DTR_EN` reader - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."] +pub type SPI_ADDR_DTR_EN_R = crate::BitReader; +#[doc = "Field `SPI_ADDR_DTR_EN` writer - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."] +pub type SPI_ADDR_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CMD_DTR_EN` reader - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."] +pub type SPI_CMD_DTR_EN_R = crate::BitReader; +#[doc = "Field `SPI_CMD_DTR_EN` writer - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."] +pub type SPI_CMD_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLAVE_CS_POL` reader - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."] +pub type SPI_SLAVE_CS_POL_R = crate::BitReader; +#[doc = "Field `SPI_SLAVE_CS_POL` writer - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."] +pub type SPI_SLAVE_CS_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DQS_IDLE_EDGE` reader - The default value of spi_dqs. Can be configured in CONF state."] +pub type SPI_DQS_IDLE_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_DQS_IDLE_EDGE` writer - The default value of spi_dqs. Can be configured in CONF state."] +pub type SPI_DQS_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CK_IDLE_EDGE` reader - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."] +pub type SPI_CK_IDLE_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_CK_IDLE_EDGE` writer - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."] +pub type SPI_CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS_KEEP_ACTIVE` reader - spi cs line keep low when the bit is set. Can be configured in CONF state."] +pub type SPI_CS_KEEP_ACTIVE_R = crate::BitReader; +#[doc = "Field `SPI_CS_KEEP_ACTIVE` writer - spi cs line keep low when the bit is set. Can be configured in CONF state."] +pub type SPI_CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_QUAD_DIN_PIN_SWAP` reader - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state."] +pub type SPI_QUAD_DIN_PIN_SWAP_R = crate::BitReader; +#[doc = "Field `SPI_QUAD_DIN_PIN_SWAP` writer - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state."] +pub type SPI_QUAD_DIN_PIN_SWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs0_dis(&self) -> SPI_CS0_DIS_R { + SPI_CS0_DIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs1_dis(&self) -> SPI_CS1_DIS_R { + SPI_CS1_DIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs2_dis(&self) -> SPI_CS2_DIS_R { + SPI_CS2_DIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs3_dis(&self) -> SPI_CS3_DIS_R { + SPI_CS3_DIS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs4_dis(&self) -> SPI_CS4_DIS_R { + SPI_CS4_DIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs5_dis(&self) -> SPI_CS5_DIS_R { + SPI_CS5_DIS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_ck_dis(&self) -> SPI_CK_DIS_R { + SPI_CK_DIS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_master_cs_pol(&self) -> SPI_MASTER_CS_POL_R { + SPI_MASTER_CS_POL_R::new(((self.bits >> 7) & 0x3f) as u8) + } + #[doc = "Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."] + #[inline(always)] + pub fn spi_clk_data_dtr_en(&self) -> SPI_CLK_DATA_DTR_EN_R { + SPI_CLK_DATA_DTR_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_data_dtr_en(&self) -> SPI_DATA_DTR_EN_R { + SPI_DATA_DTR_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_addr_dtr_en(&self) -> SPI_ADDR_DTR_EN_R { + SPI_ADDR_DTR_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cmd_dtr_en(&self) -> SPI_CMD_DTR_EN_R { + SPI_CMD_DTR_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_slave_cs_pol(&self) -> SPI_SLAVE_CS_POL_R { + SPI_SLAVE_CS_POL_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - The default value of spi_dqs. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dqs_idle_edge(&self) -> SPI_DQS_IDLE_EDGE_R { + SPI_DQS_IDLE_EDGE_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_ck_idle_edge(&self) -> SPI_CK_IDLE_EDGE_R { + SPI_CK_IDLE_EDGE_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs_keep_active(&self) -> SPI_CS_KEEP_ACTIVE_R { + SPI_CS_KEEP_ACTIVE_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_quad_din_pin_swap(&self) -> SPI_QUAD_DIN_PIN_SWAP_R { + SPI_QUAD_DIN_PIN_SWAP_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MISC") + .field("spi_cs0_dis", &format_args!("{}", self.spi_cs0_dis().bit())) + .field("spi_cs1_dis", &format_args!("{}", self.spi_cs1_dis().bit())) + .field("spi_cs2_dis", &format_args!("{}", self.spi_cs2_dis().bit())) + .field("spi_cs3_dis", &format_args!("{}", self.spi_cs3_dis().bit())) + .field("spi_cs4_dis", &format_args!("{}", self.spi_cs4_dis().bit())) + .field("spi_cs5_dis", &format_args!("{}", self.spi_cs5_dis().bit())) + .field("spi_ck_dis", &format_args!("{}", self.spi_ck_dis().bit())) + .field( + "spi_master_cs_pol", + &format_args!("{}", self.spi_master_cs_pol().bits()), + ) + .field( + "spi_clk_data_dtr_en", + &format_args!("{}", self.spi_clk_data_dtr_en().bit()), + ) + .field( + "spi_data_dtr_en", + &format_args!("{}", self.spi_data_dtr_en().bit()), + ) + .field( + "spi_addr_dtr_en", + &format_args!("{}", self.spi_addr_dtr_en().bit()), + ) + .field( + "spi_cmd_dtr_en", + &format_args!("{}", self.spi_cmd_dtr_en().bit()), + ) + .field( + "spi_slave_cs_pol", + &format_args!("{}", self.spi_slave_cs_pol().bit()), + ) + .field( + "spi_dqs_idle_edge", + &format_args!("{}", self.spi_dqs_idle_edge().bit()), + ) + .field( + "spi_ck_idle_edge", + &format_args!("{}", self.spi_ck_idle_edge().bit()), + ) + .field( + "spi_cs_keep_active", + &format_args!("{}", self.spi_cs_keep_active().bit()), + ) + .field( + "spi_quad_din_pin_swap", + &format_args!("{}", self.spi_quad_din_pin_swap().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs0_dis(&mut self) -> SPI_CS0_DIS_W { + SPI_CS0_DIS_W::new(self, 0) + } + #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs1_dis(&mut self) -> SPI_CS1_DIS_W { + SPI_CS1_DIS_W::new(self, 1) + } + #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs2_dis(&mut self) -> SPI_CS2_DIS_W { + SPI_CS2_DIS_W::new(self, 2) + } + #[doc = "Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs3_dis(&mut self) -> SPI_CS3_DIS_W { + SPI_CS3_DIS_W::new(self, 3) + } + #[doc = "Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs4_dis(&mut self) -> SPI_CS4_DIS_W { + SPI_CS4_DIS_W::new(self, 4) + } + #[doc = "Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs5_dis(&mut self) -> SPI_CS5_DIS_W { + SPI_CS5_DIS_W::new(self, 5) + } + #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_ck_dis(&mut self) -> SPI_CK_DIS_W { + SPI_CK_DIS_W::new(self, 6) + } + #[doc = "Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_master_cs_pol(&mut self) -> SPI_MASTER_CS_POL_W { + SPI_MASTER_CS_POL_W::new(self, 7) + } + #[doc = "Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."] + #[inline(always)] + #[must_use] + pub fn spi_clk_data_dtr_en(&mut self) -> SPI_CLK_DATA_DTR_EN_W { + SPI_CLK_DATA_DTR_EN_W::new(self, 16) + } + #[doc = "Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_data_dtr_en(&mut self) -> SPI_DATA_DTR_EN_W { + SPI_DATA_DTR_EN_W::new(self, 17) + } + #[doc = "Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_addr_dtr_en(&mut self) -> SPI_ADDR_DTR_EN_W { + SPI_ADDR_DTR_EN_W::new(self, 18) + } + #[doc = "Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cmd_dtr_en(&mut self) -> SPI_CMD_DTR_EN_W { + SPI_CMD_DTR_EN_W::new(self, 19) + } + #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_slave_cs_pol(&mut self) -> SPI_SLAVE_CS_POL_W { + SPI_SLAVE_CS_POL_W::new(self, 23) + } + #[doc = "Bit 24 - The default value of spi_dqs. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dqs_idle_edge(&mut self) -> SPI_DQS_IDLE_EDGE_W { + SPI_DQS_IDLE_EDGE_W::new(self, 24) + } + #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_ck_idle_edge(&mut self) -> SPI_CK_IDLE_EDGE_W { + SPI_CK_IDLE_EDGE_W::new(self, 29) + } + #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs_keep_active(&mut self) -> SPI_CS_KEEP_ACTIVE_W { + SPI_CS_KEEP_ACTIVE_W::new(self, 30) + } + #[doc = "Bit 31 - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_quad_din_pin_swap(&mut self) -> SPI_QUAD_DIN_PIN_SWAP_W { + SPI_QUAD_DIN_PIN_SWAP_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI misc register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_misc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_misc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MISC_SPEC; +impl crate::RegisterSpec for SPI_MISC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_misc::R`](R) reader structure"] +impl crate::Readable for SPI_MISC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_misc::W`](W) writer structure"] +impl crate::Writable for SPI_MISC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MISC to value 0x3e"] +impl crate::Resettable for SPI_MISC_SPEC { + const RESET_VALUE: Self::Ux = 0x3e; +} diff --git a/esp32p4/src/spi2/spi_ms_dlen.rs b/esp32p4/src/spi2/spi_ms_dlen.rs new file mode 100644 index 0000000000..e02bcd5556 --- /dev/null +++ b/esp32p4/src/spi2/spi_ms_dlen.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MS_DLEN` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MS_DLEN` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MS_DATA_BITLEN` reader - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_MS_DATA_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_MS_DATA_BITLEN` writer - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_MS_DATA_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +impl R { + #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + pub fn spi_ms_data_bitlen(&self) -> SPI_MS_DATA_BITLEN_R { + SPI_MS_DATA_BITLEN_R::new(self.bits & 0x0003_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MS_DLEN") + .field( + "spi_ms_data_bitlen", + &format_args!("{}", self.spi_ms_data_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_ms_data_bitlen(&mut self) -> SPI_MS_DATA_BITLEN_W { + SPI_MS_DATA_BITLEN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI data bit length control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ms_dlen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ms_dlen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MS_DLEN_SPEC; +impl crate::RegisterSpec for SPI_MS_DLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_ms_dlen::R`](R) reader structure"] +impl crate::Readable for SPI_MS_DLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_ms_dlen::W`](W) writer structure"] +impl crate::Writable for SPI_MS_DLEN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MS_DLEN to value 0"] +impl crate::Resettable for SPI_MS_DLEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_slave.rs b/esp32p4/src/spi2/spi_slave.rs new file mode 100644 index 0000000000..2e84842dfb --- /dev/null +++ b/esp32p4/src/spi2/spi_slave.rs @@ -0,0 +1,272 @@ +#[doc = "Register `SPI_SLAVE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SLAVE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_CLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."] +pub type SPI_CLK_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_CLK_MODE` writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."] +pub type SPI_CLK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_CLK_MODE_13` reader - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."] +pub type SPI_CLK_MODE_13_R = crate::BitReader; +#[doc = "Field `SPI_CLK_MODE_13` writer - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."] +pub type SPI_CLK_MODE_13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_RSCK_DATA_OUT` reader - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"] +pub type SPI_RSCK_DATA_OUT_R = crate::BitReader; +#[doc = "Field `SPI_RSCK_DATA_OUT` writer - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"] +pub type SPI_RSCK_DATA_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RDDMA_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"] +pub type SPI_SLV_RDDMA_BITLEN_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RDDMA_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"] +pub type SPI_SLV_RDDMA_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WRDMA_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"] +pub type SPI_SLV_WRDMA_BITLEN_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WRDMA_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"] +pub type SPI_SLV_WRDMA_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RDBUF_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"] +pub type SPI_SLV_RDBUF_BITLEN_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RDBUF_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"] +pub type SPI_SLV_RDBUF_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WRBUF_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"] +pub type SPI_SLV_WRBUF_BITLEN_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WRBUF_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"] +pub type SPI_SLV_WRBUF_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_LAST_BYTE_STRB` reader - Represents the effective bit of the last received data byte in SPI slave FD and HD mode."] +pub type SPI_SLV_LAST_BYTE_STRB_R = crate::FieldReader; +#[doc = "Field `SPI_DMA_SEG_MAGIC_VALUE` reader - The magic value of BM table in master DMA seg-trans."] +pub type SPI_DMA_SEG_MAGIC_VALUE_R = crate::FieldReader; +#[doc = "Field `SPI_DMA_SEG_MAGIC_VALUE` writer - The magic value of BM table in master DMA seg-trans."] +pub type SPI_DMA_SEG_MAGIC_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `MODE` reader - Set SPI work mode. 1: slave mode 0: master mode."] +pub type MODE_R = crate::BitReader; +#[doc = "Field `MODE` writer - Set SPI work mode. 1: slave mode 0: master mode."] +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SOFT_RESET` writer - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."] +pub type SPI_SOFT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_CONF` reader - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."] +pub type SPI_USR_CONF_R = crate::BitReader; +#[doc = "Field `SPI_USR_CONF` writer - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."] +pub type SPI_USR_CONF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_FD_WAIT_DMA_TX_DATA` reader - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."] +pub type SPI_MST_FD_WAIT_DMA_TX_DATA_R = crate::BitReader; +#[doc = "Field `SPI_MST_FD_WAIT_DMA_TX_DATA` writer - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."] +pub type SPI_MST_FD_WAIT_DMA_TX_DATA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clk_mode(&self) -> SPI_CLK_MODE_R { + SPI_CLK_MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."] + #[inline(always)] + pub fn spi_clk_mode_13(&self) -> SPI_CLK_MODE_13_R { + SPI_CLK_MODE_13_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"] + #[inline(always)] + pub fn spi_rsck_data_out(&self) -> SPI_RSCK_DATA_OUT_R { + SPI_RSCK_DATA_OUT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"] + #[inline(always)] + pub fn spi_slv_rddma_bitlen_en(&self) -> SPI_SLV_RDDMA_BITLEN_EN_R { + SPI_SLV_RDDMA_BITLEN_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"] + #[inline(always)] + pub fn spi_slv_wrdma_bitlen_en(&self) -> SPI_SLV_WRDMA_BITLEN_EN_R { + SPI_SLV_WRDMA_BITLEN_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"] + #[inline(always)] + pub fn spi_slv_rdbuf_bitlen_en(&self) -> SPI_SLV_RDBUF_BITLEN_EN_R { + SPI_SLV_RDBUF_BITLEN_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"] + #[inline(always)] + pub fn spi_slv_wrbuf_bitlen_en(&self) -> SPI_SLV_WRBUF_BITLEN_EN_R { + SPI_SLV_WRBUF_BITLEN_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:19 - Represents the effective bit of the last received data byte in SPI slave FD and HD mode."] + #[inline(always)] + pub fn spi_slv_last_byte_strb(&self) -> SPI_SLV_LAST_BYTE_STRB_R { + SPI_SLV_LAST_BYTE_STRB_R::new(((self.bits >> 12) & 0xff) as u8) + } + #[doc = "Bits 22:25 - The magic value of BM table in master DMA seg-trans."] + #[inline(always)] + pub fn spi_dma_seg_magic_value(&self) -> SPI_DMA_SEG_MAGIC_VALUE_R { + SPI_DMA_SEG_MAGIC_VALUE_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bit 26 - Set SPI work mode. 1: slave mode 0: master mode."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 28 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."] + #[inline(always)] + pub fn spi_usr_conf(&self) -> SPI_USR_CONF_R { + SPI_USR_CONF_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."] + #[inline(always)] + pub fn spi_mst_fd_wait_dma_tx_data(&self) -> SPI_MST_FD_WAIT_DMA_TX_DATA_R { + SPI_MST_FD_WAIT_DMA_TX_DATA_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SLAVE") + .field( + "spi_clk_mode", + &format_args!("{}", self.spi_clk_mode().bits()), + ) + .field( + "spi_clk_mode_13", + &format_args!("{}", self.spi_clk_mode_13().bit()), + ) + .field( + "spi_rsck_data_out", + &format_args!("{}", self.spi_rsck_data_out().bit()), + ) + .field( + "spi_slv_rddma_bitlen_en", + &format_args!("{}", self.spi_slv_rddma_bitlen_en().bit()), + ) + .field( + "spi_slv_wrdma_bitlen_en", + &format_args!("{}", self.spi_slv_wrdma_bitlen_en().bit()), + ) + .field( + "spi_slv_rdbuf_bitlen_en", + &format_args!("{}", self.spi_slv_rdbuf_bitlen_en().bit()), + ) + .field( + "spi_slv_wrbuf_bitlen_en", + &format_args!("{}", self.spi_slv_wrbuf_bitlen_en().bit()), + ) + .field( + "spi_slv_last_byte_strb", + &format_args!("{}", self.spi_slv_last_byte_strb().bits()), + ) + .field( + "spi_dma_seg_magic_value", + &format_args!("{}", self.spi_dma_seg_magic_value().bits()), + ) + .field("mode", &format_args!("{}", self.mode().bit())) + .field( + "spi_usr_conf", + &format_args!("{}", self.spi_usr_conf().bit()), + ) + .field( + "spi_mst_fd_wait_dma_tx_data", + &format_args!("{}", self.spi_mst_fd_wait_dma_tx_data().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clk_mode(&mut self) -> SPI_CLK_MODE_W { + SPI_CLK_MODE_W::new(self, 0) + } + #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."] + #[inline(always)] + #[must_use] + pub fn spi_clk_mode_13(&mut self) -> SPI_CLK_MODE_13_W { + SPI_CLK_MODE_13_W::new(self, 2) + } + #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"] + #[inline(always)] + #[must_use] + pub fn spi_rsck_data_out(&mut self) -> SPI_RSCK_DATA_OUT_W { + SPI_RSCK_DATA_OUT_W::new(self, 3) + } + #[doc = "Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"] + #[inline(always)] + #[must_use] + pub fn spi_slv_rddma_bitlen_en(&mut self) -> SPI_SLV_RDDMA_BITLEN_EN_W { + SPI_SLV_RDDMA_BITLEN_EN_W::new(self, 8) + } + #[doc = "Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"] + #[inline(always)] + #[must_use] + pub fn spi_slv_wrdma_bitlen_en(&mut self) -> SPI_SLV_WRDMA_BITLEN_EN_W { + SPI_SLV_WRDMA_BITLEN_EN_W::new(self, 9) + } + #[doc = "Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"] + #[inline(always)] + #[must_use] + pub fn spi_slv_rdbuf_bitlen_en(&mut self) -> SPI_SLV_RDBUF_BITLEN_EN_W { + SPI_SLV_RDBUF_BITLEN_EN_W::new(self, 10) + } + #[doc = "Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"] + #[inline(always)] + #[must_use] + pub fn spi_slv_wrbuf_bitlen_en(&mut self) -> SPI_SLV_WRBUF_BITLEN_EN_W { + SPI_SLV_WRBUF_BITLEN_EN_W::new(self, 11) + } + #[doc = "Bits 22:25 - The magic value of BM table in master DMA seg-trans."] + #[inline(always)] + #[must_use] + pub fn spi_dma_seg_magic_value(&mut self) -> SPI_DMA_SEG_MAGIC_VALUE_W { + SPI_DMA_SEG_MAGIC_VALUE_W::new(self, 22) + } + #[doc = "Bit 26 - Set SPI work mode. 1: slave mode 0: master mode."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 26) + } + #[doc = "Bit 27 - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_soft_reset(&mut self) -> SPI_SOFT_RESET_W { + SPI_SOFT_RESET_W::new(self, 27) + } + #[doc = "Bit 28 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."] + #[inline(always)] + #[must_use] + pub fn spi_usr_conf(&mut self) -> SPI_USR_CONF_W { + SPI_USR_CONF_W::new(self, 28) + } + #[doc = "Bit 29 - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."] + #[inline(always)] + #[must_use] + pub fn spi_mst_fd_wait_dma_tx_data(&mut self) -> SPI_MST_FD_WAIT_DMA_TX_DATA_W { + SPI_MST_FD_WAIT_DMA_TX_DATA_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI slave control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SLAVE_SPEC; +impl crate::RegisterSpec for SPI_SLAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_slave::R`](R) reader structure"] +impl crate::Readable for SPI_SLAVE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_slave::W`](W) writer structure"] +impl crate::Writable for SPI_SLAVE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SLAVE to value 0x0280_0000"] +impl crate::Resettable for SPI_SLAVE_SPEC { + const RESET_VALUE: Self::Ux = 0x0280_0000; +} diff --git a/esp32p4/src/spi2/spi_slave1.rs b/esp32p4/src/spi2/spi_slave1.rs new file mode 100644 index 0000000000..e1dda31559 --- /dev/null +++ b/esp32p4/src/spi2/spi_slave1.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SPI_SLAVE1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SLAVE1` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SLV_DATA_BITLEN` reader - The transferred data bit length in SPI slave FD and HD mode."] +pub type SPI_SLV_DATA_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_SLV_DATA_BITLEN` writer - The transferred data bit length in SPI slave FD and HD mode."] +pub type SPI_SLV_DATA_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `SPI_SLV_LAST_COMMAND` reader - In the slave mode it is the value of command."] +pub type SPI_SLV_LAST_COMMAND_R = crate::FieldReader; +#[doc = "Field `SPI_SLV_LAST_COMMAND` writer - In the slave mode it is the value of command."] +pub type SPI_SLV_LAST_COMMAND_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_SLV_LAST_ADDR` reader - In the slave mode it is the value of address."] +pub type SPI_SLV_LAST_ADDR_R = crate::FieldReader; +#[doc = "Field `SPI_SLV_LAST_ADDR` writer - In the slave mode it is the value of address."] +pub type SPI_SLV_LAST_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."] + #[inline(always)] + pub fn spi_slv_data_bitlen(&self) -> SPI_SLV_DATA_BITLEN_R { + SPI_SLV_DATA_BITLEN_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:25 - In the slave mode it is the value of command."] + #[inline(always)] + pub fn spi_slv_last_command(&self) -> SPI_SLV_LAST_COMMAND_R { + SPI_SLV_LAST_COMMAND_R::new(((self.bits >> 18) & 0xff) as u8) + } + #[doc = "Bits 26:31 - In the slave mode it is the value of address."] + #[inline(always)] + pub fn spi_slv_last_addr(&self) -> SPI_SLV_LAST_ADDR_R { + SPI_SLV_LAST_ADDR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SLAVE1") + .field( + "spi_slv_data_bitlen", + &format_args!("{}", self.spi_slv_data_bitlen().bits()), + ) + .field( + "spi_slv_last_command", + &format_args!("{}", self.spi_slv_last_command().bits()), + ) + .field( + "spi_slv_last_addr", + &format_args!("{}", self.spi_slv_last_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."] + #[inline(always)] + #[must_use] + pub fn spi_slv_data_bitlen(&mut self) -> SPI_SLV_DATA_BITLEN_W { + SPI_SLV_DATA_BITLEN_W::new(self, 0) + } + #[doc = "Bits 18:25 - In the slave mode it is the value of command."] + #[inline(always)] + #[must_use] + pub fn spi_slv_last_command(&mut self) -> SPI_SLV_LAST_COMMAND_W { + SPI_SLV_LAST_COMMAND_W::new(self, 18) + } + #[doc = "Bits 26:31 - In the slave mode it is the value of address."] + #[inline(always)] + #[must_use] + pub fn spi_slv_last_addr(&mut self) -> SPI_SLV_LAST_ADDR_W { + SPI_SLV_LAST_ADDR_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI slave control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SLAVE1_SPEC; +impl crate::RegisterSpec for SPI_SLAVE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_slave1::R`](R) reader structure"] +impl crate::Readable for SPI_SLAVE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_slave1::W`](W) writer structure"] +impl crate::Writable for SPI_SLAVE1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SLAVE1 to value 0"] +impl crate::Resettable for SPI_SLAVE1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_user.rs b/esp32p4/src/spi2/spi_user.rs new file mode 100644 index 0000000000..a11cdab15b --- /dev/null +++ b/esp32p4/src/spi2/spi_user.rs @@ -0,0 +1,437 @@ +#[doc = "Register `SPI_USER` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_USER` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DOUTDIN` reader - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_DOUTDIN_R = crate::BitReader; +#[doc = "Field `SPI_DOUTDIN` writer - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_DOUTDIN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_QPI_MODE` reader - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."] +pub type SPI_QPI_MODE_R = crate::BitReader; +#[doc = "Field `SPI_QPI_MODE` writer - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."] +pub type SPI_QPI_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_OPI_MODE` reader - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."] +pub type SPI_OPI_MODE_R = crate::BitReader; +#[doc = "Field `SPI_OPI_MODE` writer - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."] +pub type SPI_OPI_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_TSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."] +pub type SPI_TSCK_I_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_TSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."] +pub type SPI_TSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS_HOLD` reader - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_CS_HOLD_R = crate::BitReader; +#[doc = "Field `SPI_CS_HOLD` writer - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS_SETUP` reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_CS_SETUP_R = crate::BitReader; +#[doc = "Field `SPI_CS_SETUP` writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_RSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."] +pub type SPI_RSCK_I_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_RSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."] +pub type SPI_RSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CK_OUT_EDGE` reader - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."] +pub type SPI_CK_OUT_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_CK_OUT_EDGE` writer - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."] +pub type SPI_CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FWRITE_DUAL` reader - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."] +pub type SPI_FWRITE_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_FWRITE_DUAL` writer - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."] +pub type SPI_FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FWRITE_QUAD` reader - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."] +pub type SPI_FWRITE_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_FWRITE_QUAD` writer - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."] +pub type SPI_FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FWRITE_OCT` reader - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."] +pub type SPI_FWRITE_OCT_R = crate::BitReader; +#[doc = "Field `SPI_FWRITE_OCT` writer - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."] +pub type SPI_FWRITE_OCT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_CONF_NXT` reader - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."] +pub type SPI_USR_CONF_NXT_R = crate::BitReader; +#[doc = "Field `SPI_USR_CONF_NXT` writer - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."] +pub type SPI_USR_CONF_NXT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SIO` reader - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_SIO_R = crate::BitReader; +#[doc = "Field `SPI_SIO` writer - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_SIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_MISO_HIGHPART` reader - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_USR_MISO_HIGHPART_R = crate::BitReader; +#[doc = "Field `SPI_USR_MISO_HIGHPART` writer - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_USR_MISO_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_MOSI_HIGHPART` reader - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_USR_MOSI_HIGHPART_R = crate::BitReader; +#[doc = "Field `SPI_USR_MOSI_HIGHPART` writer - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_USR_MOSI_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_DUMMY_IDLE` reader - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."] +pub type SPI_USR_DUMMY_IDLE_R = crate::BitReader; +#[doc = "Field `SPI_USR_DUMMY_IDLE` writer - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."] +pub type SPI_USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_MOSI` reader - This bit enable the write-data phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_MOSI_R = crate::BitReader; +#[doc = "Field `SPI_USR_MOSI` writer - This bit enable the write-data phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_MISO` reader - This bit enable the read-data phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_MISO_R = crate::BitReader; +#[doc = "Field `SPI_USR_MISO` writer - This bit enable the read-data phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_DUMMY` reader - This bit enable the dummy phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_DUMMY_R = crate::BitReader; +#[doc = "Field `SPI_USR_DUMMY` writer - This bit enable the dummy phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_ADDR` reader - This bit enable the address phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_ADDR_R = crate::BitReader; +#[doc = "Field `SPI_USR_ADDR` writer - This bit enable the address phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_COMMAND` reader - This bit enable the command phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_COMMAND_R = crate::BitReader; +#[doc = "Field `SPI_USR_COMMAND` writer - This bit enable the command phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_doutdin(&self) -> SPI_DOUTDIN_R { + SPI_DOUTDIN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_qpi_mode(&self) -> SPI_QPI_MODE_R { + SPI_QPI_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_opi_mode(&self) -> SPI_OPI_MODE_R { + SPI_OPI_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."] + #[inline(always)] + pub fn spi_tsck_i_edge(&self) -> SPI_TSCK_I_EDGE_R { + SPI_TSCK_I_EDGE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs_hold(&self) -> SPI_CS_HOLD_R { + SPI_CS_HOLD_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs_setup(&self) -> SPI_CS_SETUP_R { + SPI_CS_SETUP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."] + #[inline(always)] + pub fn spi_rsck_i_edge(&self) -> SPI_RSCK_I_EDGE_R { + SPI_RSCK_I_EDGE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_ck_out_edge(&self) -> SPI_CK_OUT_EDGE_R { + SPI_CK_OUT_EDGE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fwrite_dual(&self) -> SPI_FWRITE_DUAL_R { + SPI_FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fwrite_quad(&self) -> SPI_FWRITE_QUAD_R { + SPI_FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fwrite_oct(&self) -> SPI_FWRITE_OCT_R { + SPI_FWRITE_OCT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_conf_nxt(&self) -> SPI_USR_CONF_NXT_R { + SPI_USR_CONF_NXT_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_sio(&self) -> SPI_SIO_R { + SPI_SIO_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_miso_highpart(&self) -> SPI_USR_MISO_HIGHPART_R { + SPI_USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_mosi_highpart(&self) -> SPI_USR_MOSI_HIGHPART_R { + SPI_USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_dummy_idle(&self) -> SPI_USR_DUMMY_IDLE_R { + SPI_USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_mosi(&self) -> SPI_USR_MOSI_R { + SPI_USR_MOSI_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_miso(&self) -> SPI_USR_MISO_R { + SPI_USR_MISO_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_dummy(&self) -> SPI_USR_DUMMY_R { + SPI_USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_addr(&self) -> SPI_USR_ADDR_R { + SPI_USR_ADDR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_command(&self) -> SPI_USR_COMMAND_R { + SPI_USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_USER") + .field("spi_doutdin", &format_args!("{}", self.spi_doutdin().bit())) + .field( + "spi_qpi_mode", + &format_args!("{}", self.spi_qpi_mode().bit()), + ) + .field( + "spi_opi_mode", + &format_args!("{}", self.spi_opi_mode().bit()), + ) + .field( + "spi_tsck_i_edge", + &format_args!("{}", self.spi_tsck_i_edge().bit()), + ) + .field("spi_cs_hold", &format_args!("{}", self.spi_cs_hold().bit())) + .field( + "spi_cs_setup", + &format_args!("{}", self.spi_cs_setup().bit()), + ) + .field( + "spi_rsck_i_edge", + &format_args!("{}", self.spi_rsck_i_edge().bit()), + ) + .field( + "spi_ck_out_edge", + &format_args!("{}", self.spi_ck_out_edge().bit()), + ) + .field( + "spi_fwrite_dual", + &format_args!("{}", self.spi_fwrite_dual().bit()), + ) + .field( + "spi_fwrite_quad", + &format_args!("{}", self.spi_fwrite_quad().bit()), + ) + .field( + "spi_fwrite_oct", + &format_args!("{}", self.spi_fwrite_oct().bit()), + ) + .field( + "spi_usr_conf_nxt", + &format_args!("{}", self.spi_usr_conf_nxt().bit()), + ) + .field("spi_sio", &format_args!("{}", self.spi_sio().bit())) + .field( + "spi_usr_miso_highpart", + &format_args!("{}", self.spi_usr_miso_highpart().bit()), + ) + .field( + "spi_usr_mosi_highpart", + &format_args!("{}", self.spi_usr_mosi_highpart().bit()), + ) + .field( + "spi_usr_dummy_idle", + &format_args!("{}", self.spi_usr_dummy_idle().bit()), + ) + .field( + "spi_usr_mosi", + &format_args!("{}", self.spi_usr_mosi().bit()), + ) + .field( + "spi_usr_miso", + &format_args!("{}", self.spi_usr_miso().bit()), + ) + .field( + "spi_usr_dummy", + &format_args!("{}", self.spi_usr_dummy().bit()), + ) + .field( + "spi_usr_addr", + &format_args!("{}", self.spi_usr_addr().bit()), + ) + .field( + "spi_usr_command", + &format_args!("{}", self.spi_usr_command().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_doutdin(&mut self) -> SPI_DOUTDIN_W { + SPI_DOUTDIN_W::new(self, 0) + } + #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_qpi_mode(&mut self) -> SPI_QPI_MODE_W { + SPI_QPI_MODE_W::new(self, 3) + } + #[doc = "Bit 4 - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_opi_mode(&mut self) -> SPI_OPI_MODE_W { + SPI_OPI_MODE_W::new(self, 4) + } + #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."] + #[inline(always)] + #[must_use] + pub fn spi_tsck_i_edge(&mut self) -> SPI_TSCK_I_EDGE_W { + SPI_TSCK_I_EDGE_W::new(self, 5) + } + #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs_hold(&mut self) -> SPI_CS_HOLD_W { + SPI_CS_HOLD_W::new(self, 6) + } + #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs_setup(&mut self) -> SPI_CS_SETUP_W { + SPI_CS_SETUP_W::new(self, 7) + } + #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."] + #[inline(always)] + #[must_use] + pub fn spi_rsck_i_edge(&mut self) -> SPI_RSCK_I_EDGE_W { + SPI_RSCK_I_EDGE_W::new(self, 8) + } + #[doc = "Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_ck_out_edge(&mut self) -> SPI_CK_OUT_EDGE_W { + SPI_CK_OUT_EDGE_W::new(self, 9) + } + #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fwrite_dual(&mut self) -> SPI_FWRITE_DUAL_W { + SPI_FWRITE_DUAL_W::new(self, 12) + } + #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fwrite_quad(&mut self) -> SPI_FWRITE_QUAD_W { + SPI_FWRITE_QUAD_W::new(self, 13) + } + #[doc = "Bit 14 - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fwrite_oct(&mut self) -> SPI_FWRITE_OCT_W { + SPI_FWRITE_OCT_W::new(self, 14) + } + #[doc = "Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_conf_nxt(&mut self) -> SPI_USR_CONF_NXT_W { + SPI_USR_CONF_NXT_W::new(self, 15) + } + #[doc = "Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_sio(&mut self) -> SPI_SIO_W { + SPI_SIO_W::new(self, 17) + } + #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_miso_highpart(&mut self) -> SPI_USR_MISO_HIGHPART_W { + SPI_USR_MISO_HIGHPART_W::new(self, 24) + } + #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_mosi_highpart(&mut self) -> SPI_USR_MOSI_HIGHPART_W { + SPI_USR_MOSI_HIGHPART_W::new(self, 25) + } + #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_dummy_idle(&mut self) -> SPI_USR_DUMMY_IDLE_W { + SPI_USR_DUMMY_IDLE_W::new(self, 26) + } + #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_mosi(&mut self) -> SPI_USR_MOSI_W { + SPI_USR_MOSI_W::new(self, 27) + } + #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_miso(&mut self) -> SPI_USR_MISO_W { + SPI_USR_MISO_W::new(self, 28) + } + #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_dummy(&mut self) -> SPI_USR_DUMMY_W { + SPI_USR_DUMMY_W::new(self, 29) + } + #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_addr(&mut self) -> SPI_USR_ADDR_W { + SPI_USR_ADDR_W::new(self, 30) + } + #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_command(&mut self) -> SPI_USR_COMMAND_W { + SPI_USR_COMMAND_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI USER control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_USER_SPEC; +impl crate::RegisterSpec for SPI_USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_user::R`](R) reader structure"] +impl crate::Readable for SPI_USER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_user::W`](W) writer structure"] +impl crate::Writable for SPI_USER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_USER to value 0x8000_00c0"] +impl crate::Resettable for SPI_USER_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_00c0; +} diff --git a/esp32p4/src/spi2/spi_user1.rs b/esp32p4/src/spi2/spi_user1.rs new file mode 100644 index 0000000000..7d382bc958 --- /dev/null +++ b/esp32p4/src/spi2/spi_user1.rs @@ -0,0 +1,142 @@ +#[doc = "Register `SPI_USER1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_USER1` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_USR_DUMMY_CYCLELEN` reader - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."] +pub type SPI_USR_DUMMY_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `SPI_USR_DUMMY_CYCLELEN` writer - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."] +pub type SPI_USR_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MST_WFULL_ERR_END_EN` reader - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."] +pub type SPI_MST_WFULL_ERR_END_EN_R = crate::BitReader; +#[doc = "Field `SPI_MST_WFULL_ERR_END_EN` writer - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."] +pub type SPI_MST_WFULL_ERR_END_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS_SETUP_TIME` reader - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."] +pub type SPI_CS_SETUP_TIME_R = crate::FieldReader; +#[doc = "Field `SPI_CS_SETUP_TIME` writer - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."] +pub type SPI_CS_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SPI_CS_HOLD_TIME` reader - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."] +pub type SPI_CS_HOLD_TIME_R = crate::FieldReader; +#[doc = "Field `SPI_CS_HOLD_TIME` writer - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."] +pub type SPI_CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SPI_USR_ADDR_BITLEN` reader - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_USR_ADDR_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_USR_ADDR_BITLEN` writer - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_USR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_dummy_cyclelen(&self) -> SPI_USR_DUMMY_CYCLELEN_R { + SPI_USR_DUMMY_CYCLELEN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 16 - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."] + #[inline(always)] + pub fn spi_mst_wfull_err_end_en(&self) -> SPI_MST_WFULL_ERR_END_EN_R { + SPI_MST_WFULL_ERR_END_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:21 - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs_setup_time(&self) -> SPI_CS_SETUP_TIME_R { + SPI_CS_SETUP_TIME_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:26 - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs_hold_time(&self) -> SPI_CS_HOLD_TIME_R { + SPI_CS_HOLD_TIME_R::new(((self.bits >> 22) & 0x1f) as u8) + } + #[doc = "Bits 27:31 - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_addr_bitlen(&self) -> SPI_USR_ADDR_BITLEN_R { + SPI_USR_ADDR_BITLEN_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_USER1") + .field( + "spi_usr_dummy_cyclelen", + &format_args!("{}", self.spi_usr_dummy_cyclelen().bits()), + ) + .field( + "spi_mst_wfull_err_end_en", + &format_args!("{}", self.spi_mst_wfull_err_end_en().bit()), + ) + .field( + "spi_cs_setup_time", + &format_args!("{}", self.spi_cs_setup_time().bits()), + ) + .field( + "spi_cs_hold_time", + &format_args!("{}", self.spi_cs_hold_time().bits()), + ) + .field( + "spi_usr_addr_bitlen", + &format_args!("{}", self.spi_usr_addr_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_dummy_cyclelen(&mut self) -> SPI_USR_DUMMY_CYCLELEN_W { + SPI_USR_DUMMY_CYCLELEN_W::new(self, 0) + } + #[doc = "Bit 16 - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."] + #[inline(always)] + #[must_use] + pub fn spi_mst_wfull_err_end_en(&mut self) -> SPI_MST_WFULL_ERR_END_EN_W { + SPI_MST_WFULL_ERR_END_EN_W::new(self, 16) + } + #[doc = "Bits 17:21 - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs_setup_time(&mut self) -> SPI_CS_SETUP_TIME_W { + SPI_CS_SETUP_TIME_W::new(self, 17) + } + #[doc = "Bits 22:26 - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs_hold_time(&mut self) -> SPI_CS_HOLD_TIME_W { + SPI_CS_HOLD_TIME_W::new(self, 22) + } + #[doc = "Bits 27:31 - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_addr_bitlen(&mut self) -> SPI_USR_ADDR_BITLEN_W { + SPI_USR_ADDR_BITLEN_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI USER control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_USER1_SPEC; +impl crate::RegisterSpec for SPI_USER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_user1::R`](R) reader structure"] +impl crate::Readable for SPI_USER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_user1::W`](W) writer structure"] +impl crate::Writable for SPI_USER1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_USER1 to value 0xb841_0007"] +impl crate::Resettable for SPI_USER1_SPEC { + const RESET_VALUE: Self::Ux = 0xb841_0007; +} diff --git a/esp32p4/src/spi2/spi_user2.rs b/esp32p4/src/spi2/spi_user2.rs new file mode 100644 index 0000000000..8fed5c2dc1 --- /dev/null +++ b/esp32p4/src/spi2/spi_user2.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SPI_USER2` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_USER2` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_USR_COMMAND_VALUE` reader - The value of command. Can be configured in CONF state."] +pub type SPI_USR_COMMAND_VALUE_R = crate::FieldReader; +#[doc = "Field `SPI_USR_COMMAND_VALUE` writer - The value of command. Can be configured in CONF state."] +pub type SPI_USR_COMMAND_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SPI_MST_REMPTY_ERR_END_EN` reader - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode."] +pub type SPI_MST_REMPTY_ERR_END_EN_R = crate::BitReader; +#[doc = "Field `SPI_MST_REMPTY_ERR_END_EN` writer - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode."] +pub type SPI_MST_REMPTY_ERR_END_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_COMMAND_BITLEN` reader - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_USR_COMMAND_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_USR_COMMAND_BITLEN` writer - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_USR_COMMAND_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_command_value(&self) -> SPI_USR_COMMAND_VALUE_R { + SPI_USR_COMMAND_VALUE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 27 - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode."] + #[inline(always)] + pub fn spi_mst_rempty_err_end_en(&self) -> SPI_MST_REMPTY_ERR_END_EN_R { + SPI_MST_REMPTY_ERR_END_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_command_bitlen(&self) -> SPI_USR_COMMAND_BITLEN_R { + SPI_USR_COMMAND_BITLEN_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_USER2") + .field( + "spi_usr_command_value", + &format_args!("{}", self.spi_usr_command_value().bits()), + ) + .field( + "spi_mst_rempty_err_end_en", + &format_args!("{}", self.spi_mst_rempty_err_end_en().bit()), + ) + .field( + "spi_usr_command_bitlen", + &format_args!("{}", self.spi_usr_command_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_command_value(&mut self) -> SPI_USR_COMMAND_VALUE_W { + SPI_USR_COMMAND_VALUE_W::new(self, 0) + } + #[doc = "Bit 27 - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode."] + #[inline(always)] + #[must_use] + pub fn spi_mst_rempty_err_end_en(&mut self) -> SPI_MST_REMPTY_ERR_END_EN_W { + SPI_MST_REMPTY_ERR_END_EN_W::new(self, 27) + } + #[doc = "Bits 28:31 - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_command_bitlen(&mut self) -> SPI_USR_COMMAND_BITLEN_W { + SPI_USR_COMMAND_BITLEN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI USER control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_USER2_SPEC; +impl crate::RegisterSpec for SPI_USER2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_user2::R`](R) reader structure"] +impl crate::Readable for SPI_USER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_user2::W`](W) writer structure"] +impl crate::Writable for SPI_USER2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_USER2 to value 0x7800_0000"] +impl crate::Resettable for SPI_USER2_SPEC { + const RESET_VALUE: Self::Ux = 0x7800_0000; +} diff --git a/esp32p4/src/spi2/spi_w0.rs b/esp32p4/src/spi2/spi_w0.rs new file mode 100644 index 0000000000..9c70c5c2f4 --- /dev/null +++ b/esp32p4/src/spi2/spi_w0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W0` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W0` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF0` reader - data buffer"] +pub type SPI_BUF0_R = crate::FieldReader; +#[doc = "Field `SPI_BUF0` writer - data buffer"] +pub type SPI_BUF0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf0(&self) -> SPI_BUF0_R { + SPI_BUF0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W0") + .field("spi_buf0", &format_args!("{}", self.spi_buf0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf0(&mut self) -> SPI_BUF0_W { + SPI_BUF0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W0_SPEC; +impl crate::RegisterSpec for SPI_W0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w0::R`](R) reader structure"] +impl crate::Readable for SPI_W0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w0::W`](W) writer structure"] +impl crate::Writable for SPI_W0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W0 to value 0"] +impl crate::Resettable for SPI_W0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w1.rs b/esp32p4/src/spi2/spi_w1.rs new file mode 100644 index 0000000000..d2246bb39a --- /dev/null +++ b/esp32p4/src/spi2/spi_w1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W1` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF1` reader - data buffer"] +pub type SPI_BUF1_R = crate::FieldReader; +#[doc = "Field `SPI_BUF1` writer - data buffer"] +pub type SPI_BUF1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf1(&self) -> SPI_BUF1_R { + SPI_BUF1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W1") + .field("spi_buf1", &format_args!("{}", self.spi_buf1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf1(&mut self) -> SPI_BUF1_W { + SPI_BUF1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W1_SPEC; +impl crate::RegisterSpec for SPI_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w1::R`](R) reader structure"] +impl crate::Readable for SPI_W1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w1::W`](W) writer structure"] +impl crate::Writable for SPI_W1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W1 to value 0"] +impl crate::Resettable for SPI_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w10.rs b/esp32p4/src/spi2/spi_w10.rs new file mode 100644 index 0000000000..324fa92a1e --- /dev/null +++ b/esp32p4/src/spi2/spi_w10.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W10` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W10` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF10` reader - data buffer"] +pub type SPI_BUF10_R = crate::FieldReader; +#[doc = "Field `SPI_BUF10` writer - data buffer"] +pub type SPI_BUF10_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf10(&self) -> SPI_BUF10_R { + SPI_BUF10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W10") + .field("spi_buf10", &format_args!("{}", self.spi_buf10().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf10(&mut self) -> SPI_BUF10_W { + SPI_BUF10_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W10_SPEC; +impl crate::RegisterSpec for SPI_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w10::R`](R) reader structure"] +impl crate::Readable for SPI_W10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w10::W`](W) writer structure"] +impl crate::Writable for SPI_W10_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W10 to value 0"] +impl crate::Resettable for SPI_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w11.rs b/esp32p4/src/spi2/spi_w11.rs new file mode 100644 index 0000000000..7b04dc7174 --- /dev/null +++ b/esp32p4/src/spi2/spi_w11.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W11` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W11` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF11` reader - data buffer"] +pub type SPI_BUF11_R = crate::FieldReader; +#[doc = "Field `SPI_BUF11` writer - data buffer"] +pub type SPI_BUF11_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf11(&self) -> SPI_BUF11_R { + SPI_BUF11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W11") + .field("spi_buf11", &format_args!("{}", self.spi_buf11().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf11(&mut self) -> SPI_BUF11_W { + SPI_BUF11_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W11_SPEC; +impl crate::RegisterSpec for SPI_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w11::R`](R) reader structure"] +impl crate::Readable for SPI_W11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w11::W`](W) writer structure"] +impl crate::Writable for SPI_W11_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W11 to value 0"] +impl crate::Resettable for SPI_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w12.rs b/esp32p4/src/spi2/spi_w12.rs new file mode 100644 index 0000000000..c73425c68e --- /dev/null +++ b/esp32p4/src/spi2/spi_w12.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W12` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W12` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF12` reader - data buffer"] +pub type SPI_BUF12_R = crate::FieldReader; +#[doc = "Field `SPI_BUF12` writer - data buffer"] +pub type SPI_BUF12_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf12(&self) -> SPI_BUF12_R { + SPI_BUF12_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W12") + .field("spi_buf12", &format_args!("{}", self.spi_buf12().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf12(&mut self) -> SPI_BUF12_W { + SPI_BUF12_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W12_SPEC; +impl crate::RegisterSpec for SPI_W12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w12::R`](R) reader structure"] +impl crate::Readable for SPI_W12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w12::W`](W) writer structure"] +impl crate::Writable for SPI_W12_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W12 to value 0"] +impl crate::Resettable for SPI_W12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w13.rs b/esp32p4/src/spi2/spi_w13.rs new file mode 100644 index 0000000000..3930b40ee3 --- /dev/null +++ b/esp32p4/src/spi2/spi_w13.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W13` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W13` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF13` reader - data buffer"] +pub type SPI_BUF13_R = crate::FieldReader; +#[doc = "Field `SPI_BUF13` writer - data buffer"] +pub type SPI_BUF13_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf13(&self) -> SPI_BUF13_R { + SPI_BUF13_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W13") + .field("spi_buf13", &format_args!("{}", self.spi_buf13().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf13(&mut self) -> SPI_BUF13_W { + SPI_BUF13_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W13_SPEC; +impl crate::RegisterSpec for SPI_W13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w13::R`](R) reader structure"] +impl crate::Readable for SPI_W13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w13::W`](W) writer structure"] +impl crate::Writable for SPI_W13_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W13 to value 0"] +impl crate::Resettable for SPI_W13_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w14.rs b/esp32p4/src/spi2/spi_w14.rs new file mode 100644 index 0000000000..598007d8cc --- /dev/null +++ b/esp32p4/src/spi2/spi_w14.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W14` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W14` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF14` reader - data buffer"] +pub type SPI_BUF14_R = crate::FieldReader; +#[doc = "Field `SPI_BUF14` writer - data buffer"] +pub type SPI_BUF14_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf14(&self) -> SPI_BUF14_R { + SPI_BUF14_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W14") + .field("spi_buf14", &format_args!("{}", self.spi_buf14().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf14(&mut self) -> SPI_BUF14_W { + SPI_BUF14_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W14_SPEC; +impl crate::RegisterSpec for SPI_W14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w14::R`](R) reader structure"] +impl crate::Readable for SPI_W14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w14::W`](W) writer structure"] +impl crate::Writable for SPI_W14_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W14 to value 0"] +impl crate::Resettable for SPI_W14_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w15.rs b/esp32p4/src/spi2/spi_w15.rs new file mode 100644 index 0000000000..c1874cb7fa --- /dev/null +++ b/esp32p4/src/spi2/spi_w15.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W15` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W15` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF15` reader - data buffer"] +pub type SPI_BUF15_R = crate::FieldReader; +#[doc = "Field `SPI_BUF15` writer - data buffer"] +pub type SPI_BUF15_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf15(&self) -> SPI_BUF15_R { + SPI_BUF15_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W15") + .field("spi_buf15", &format_args!("{}", self.spi_buf15().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf15(&mut self) -> SPI_BUF15_W { + SPI_BUF15_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W15_SPEC; +impl crate::RegisterSpec for SPI_W15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w15::R`](R) reader structure"] +impl crate::Readable for SPI_W15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w15::W`](W) writer structure"] +impl crate::Writable for SPI_W15_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W15 to value 0"] +impl crate::Resettable for SPI_W15_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w2.rs b/esp32p4/src/spi2/spi_w2.rs new file mode 100644 index 0000000000..02efa5a2fb --- /dev/null +++ b/esp32p4/src/spi2/spi_w2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W2` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W2` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF2` reader - data buffer"] +pub type SPI_BUF2_R = crate::FieldReader; +#[doc = "Field `SPI_BUF2` writer - data buffer"] +pub type SPI_BUF2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf2(&self) -> SPI_BUF2_R { + SPI_BUF2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W2") + .field("spi_buf2", &format_args!("{}", self.spi_buf2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf2(&mut self) -> SPI_BUF2_W { + SPI_BUF2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W2_SPEC; +impl crate::RegisterSpec for SPI_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w2::R`](R) reader structure"] +impl crate::Readable for SPI_W2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w2::W`](W) writer structure"] +impl crate::Writable for SPI_W2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W2 to value 0"] +impl crate::Resettable for SPI_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w3.rs b/esp32p4/src/spi2/spi_w3.rs new file mode 100644 index 0000000000..37b01969e9 --- /dev/null +++ b/esp32p4/src/spi2/spi_w3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W3` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W3` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF3` reader - data buffer"] +pub type SPI_BUF3_R = crate::FieldReader; +#[doc = "Field `SPI_BUF3` writer - data buffer"] +pub type SPI_BUF3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf3(&self) -> SPI_BUF3_R { + SPI_BUF3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W3") + .field("spi_buf3", &format_args!("{}", self.spi_buf3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf3(&mut self) -> SPI_BUF3_W { + SPI_BUF3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W3_SPEC; +impl crate::RegisterSpec for SPI_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w3::R`](R) reader structure"] +impl crate::Readable for SPI_W3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w3::W`](W) writer structure"] +impl crate::Writable for SPI_W3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W3 to value 0"] +impl crate::Resettable for SPI_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w4.rs b/esp32p4/src/spi2/spi_w4.rs new file mode 100644 index 0000000000..3369cd6f01 --- /dev/null +++ b/esp32p4/src/spi2/spi_w4.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W4` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W4` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF4` reader - data buffer"] +pub type SPI_BUF4_R = crate::FieldReader; +#[doc = "Field `SPI_BUF4` writer - data buffer"] +pub type SPI_BUF4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf4(&self) -> SPI_BUF4_R { + SPI_BUF4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W4") + .field("spi_buf4", &format_args!("{}", self.spi_buf4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf4(&mut self) -> SPI_BUF4_W { + SPI_BUF4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W4_SPEC; +impl crate::RegisterSpec for SPI_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w4::R`](R) reader structure"] +impl crate::Readable for SPI_W4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w4::W`](W) writer structure"] +impl crate::Writable for SPI_W4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W4 to value 0"] +impl crate::Resettable for SPI_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w5.rs b/esp32p4/src/spi2/spi_w5.rs new file mode 100644 index 0000000000..4d3c5ab984 --- /dev/null +++ b/esp32p4/src/spi2/spi_w5.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W5` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W5` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF5` reader - data buffer"] +pub type SPI_BUF5_R = crate::FieldReader; +#[doc = "Field `SPI_BUF5` writer - data buffer"] +pub type SPI_BUF5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf5(&self) -> SPI_BUF5_R { + SPI_BUF5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W5") + .field("spi_buf5", &format_args!("{}", self.spi_buf5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf5(&mut self) -> SPI_BUF5_W { + SPI_BUF5_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W5_SPEC; +impl crate::RegisterSpec for SPI_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w5::R`](R) reader structure"] +impl crate::Readable for SPI_W5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w5::W`](W) writer structure"] +impl crate::Writable for SPI_W5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W5 to value 0"] +impl crate::Resettable for SPI_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w6.rs b/esp32p4/src/spi2/spi_w6.rs new file mode 100644 index 0000000000..f0b15ad83f --- /dev/null +++ b/esp32p4/src/spi2/spi_w6.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W6` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W6` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF6` reader - data buffer"] +pub type SPI_BUF6_R = crate::FieldReader; +#[doc = "Field `SPI_BUF6` writer - data buffer"] +pub type SPI_BUF6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf6(&self) -> SPI_BUF6_R { + SPI_BUF6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W6") + .field("spi_buf6", &format_args!("{}", self.spi_buf6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf6(&mut self) -> SPI_BUF6_W { + SPI_BUF6_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W6_SPEC; +impl crate::RegisterSpec for SPI_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w6::R`](R) reader structure"] +impl crate::Readable for SPI_W6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w6::W`](W) writer structure"] +impl crate::Writable for SPI_W6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W6 to value 0"] +impl crate::Resettable for SPI_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w7.rs b/esp32p4/src/spi2/spi_w7.rs new file mode 100644 index 0000000000..668139f0a2 --- /dev/null +++ b/esp32p4/src/spi2/spi_w7.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W7` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W7` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF7` reader - data buffer"] +pub type SPI_BUF7_R = crate::FieldReader; +#[doc = "Field `SPI_BUF7` writer - data buffer"] +pub type SPI_BUF7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf7(&self) -> SPI_BUF7_R { + SPI_BUF7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W7") + .field("spi_buf7", &format_args!("{}", self.spi_buf7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf7(&mut self) -> SPI_BUF7_W { + SPI_BUF7_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W7_SPEC; +impl crate::RegisterSpec for SPI_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w7::R`](R) reader structure"] +impl crate::Readable for SPI_W7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w7::W`](W) writer structure"] +impl crate::Writable for SPI_W7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W7 to value 0"] +impl crate::Resettable for SPI_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w8.rs b/esp32p4/src/spi2/spi_w8.rs new file mode 100644 index 0000000000..3d2f27b19a --- /dev/null +++ b/esp32p4/src/spi2/spi_w8.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W8` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W8` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF8` reader - data buffer"] +pub type SPI_BUF8_R = crate::FieldReader; +#[doc = "Field `SPI_BUF8` writer - data buffer"] +pub type SPI_BUF8_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf8(&self) -> SPI_BUF8_R { + SPI_BUF8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W8") + .field("spi_buf8", &format_args!("{}", self.spi_buf8().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf8(&mut self) -> SPI_BUF8_W { + SPI_BUF8_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W8_SPEC; +impl crate::RegisterSpec for SPI_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w8::R`](R) reader structure"] +impl crate::Readable for SPI_W8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w8::W`](W) writer structure"] +impl crate::Writable for SPI_W8_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W8 to value 0"] +impl crate::Resettable for SPI_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi2/spi_w9.rs b/esp32p4/src/spi2/spi_w9.rs new file mode 100644 index 0000000000..29c8beb1c8 --- /dev/null +++ b/esp32p4/src/spi2/spi_w9.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W9` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W9` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF9` reader - data buffer"] +pub type SPI_BUF9_R = crate::FieldReader; +#[doc = "Field `SPI_BUF9` writer - data buffer"] +pub type SPI_BUF9_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf9(&self) -> SPI_BUF9_R { + SPI_BUF9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W9") + .field("spi_buf9", &format_args!("{}", self.spi_buf9().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf9(&mut self) -> SPI_BUF9_W { + SPI_BUF9_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W9_SPEC; +impl crate::RegisterSpec for SPI_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w9::R`](R) reader structure"] +impl crate::Readable for SPI_W9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w9::W`](W) writer structure"] +impl crate::Writable for SPI_W9_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W9 to value 0"] +impl crate::Resettable for SPI_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3.rs b/esp32p4/src/spi3.rs new file mode 100644 index 0000000000..2defae7f74 --- /dev/null +++ b/esp32p4/src/spi3.rs @@ -0,0 +1,390 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + spi_cmd: SPI_CMD, + spi_addr: SPI_ADDR, + spi_ctrl: SPI_CTRL, + spi_clock: SPI_CLOCK, + spi_user: SPI_USER, + spi_user1: SPI_USER1, + spi_user2: SPI_USER2, + spi_ms_dlen: SPI_MS_DLEN, + spi_misc: SPI_MISC, + spi_din_mode: SPI_DIN_MODE, + spi_din_num: SPI_DIN_NUM, + spi_dout_mode: SPI_DOUT_MODE, + spi_dma_conf: SPI_DMA_CONF, + spi_dma_int_ena: SPI_DMA_INT_ENA, + spi_dma_int_clr: SPI_DMA_INT_CLR, + spi_dma_int_raw: SPI_DMA_INT_RAW, + spi_dma_int_st: SPI_DMA_INT_ST, + spi_dma_int_set: SPI_DMA_INT_SET, + _reserved18: [u8; 0x50], + spi_w0: SPI_W0, + spi_w1: SPI_W1, + spi_w2: SPI_W2, + spi_w3: SPI_W3, + spi_w4: SPI_W4, + spi_w5: SPI_W5, + spi_w6: SPI_W6, + spi_w7: SPI_W7, + spi_w8: SPI_W8, + spi_w9: SPI_W9, + spi_w10: SPI_W10, + spi_w11: SPI_W11, + spi_w12: SPI_W12, + spi_w13: SPI_W13, + spi_w14: SPI_W14, + spi_w15: SPI_W15, + _reserved34: [u8; 0x08], + spi_slave: SPI_SLAVE, + spi_slave1: SPI_SLAVE1, + spi_clk_gate: SPI_CLK_GATE, + _reserved37: [u8; 0x04], + spi_date: SPI_DATE, +} +impl RegisterBlock { + #[doc = "0x00 - Command control register"] + #[inline(always)] + pub const fn spi_cmd(&self) -> &SPI_CMD { + &self.spi_cmd + } + #[doc = "0x04 - Address value register"] + #[inline(always)] + pub const fn spi_addr(&self) -> &SPI_ADDR { + &self.spi_addr + } + #[doc = "0x08 - SPI control register"] + #[inline(always)] + pub const fn spi_ctrl(&self) -> &SPI_CTRL { + &self.spi_ctrl + } + #[doc = "0x0c - SPI clock control register"] + #[inline(always)] + pub const fn spi_clock(&self) -> &SPI_CLOCK { + &self.spi_clock + } + #[doc = "0x10 - SPI USER control register"] + #[inline(always)] + pub const fn spi_user(&self) -> &SPI_USER { + &self.spi_user + } + #[doc = "0x14 - SPI USER control register 1"] + #[inline(always)] + pub const fn spi_user1(&self) -> &SPI_USER1 { + &self.spi_user1 + } + #[doc = "0x18 - SPI USER control register 2"] + #[inline(always)] + pub const fn spi_user2(&self) -> &SPI_USER2 { + &self.spi_user2 + } + #[doc = "0x1c - SPI data bit length control register"] + #[inline(always)] + pub const fn spi_ms_dlen(&self) -> &SPI_MS_DLEN { + &self.spi_ms_dlen + } + #[doc = "0x20 - SPI misc register"] + #[inline(always)] + pub const fn spi_misc(&self) -> &SPI_MISC { + &self.spi_misc + } + #[doc = "0x24 - SPI input delay mode configuration"] + #[inline(always)] + pub const fn spi_din_mode(&self) -> &SPI_DIN_MODE { + &self.spi_din_mode + } + #[doc = "0x28 - SPI input delay number configuration"] + #[inline(always)] + pub const fn spi_din_num(&self) -> &SPI_DIN_NUM { + &self.spi_din_num + } + #[doc = "0x2c - SPI output delay mode configuration"] + #[inline(always)] + pub const fn spi_dout_mode(&self) -> &SPI_DOUT_MODE { + &self.spi_dout_mode + } + #[doc = "0x30 - SPI DMA control register"] + #[inline(always)] + pub const fn spi_dma_conf(&self) -> &SPI_DMA_CONF { + &self.spi_dma_conf + } + #[doc = "0x34 - SPI interrupt enable register"] + #[inline(always)] + pub const fn spi_dma_int_ena(&self) -> &SPI_DMA_INT_ENA { + &self.spi_dma_int_ena + } + #[doc = "0x38 - SPI interrupt clear register"] + #[inline(always)] + pub const fn spi_dma_int_clr(&self) -> &SPI_DMA_INT_CLR { + &self.spi_dma_int_clr + } + #[doc = "0x3c - SPI interrupt raw register"] + #[inline(always)] + pub const fn spi_dma_int_raw(&self) -> &SPI_DMA_INT_RAW { + &self.spi_dma_int_raw + } + #[doc = "0x40 - SPI interrupt status register"] + #[inline(always)] + pub const fn spi_dma_int_st(&self) -> &SPI_DMA_INT_ST { + &self.spi_dma_int_st + } + #[doc = "0x44 - SPI interrupt software set register"] + #[inline(always)] + pub const fn spi_dma_int_set(&self) -> &SPI_DMA_INT_SET { + &self.spi_dma_int_set + } + #[doc = "0x98 - SPI CPU-controlled buffer0"] + #[inline(always)] + pub const fn spi_w0(&self) -> &SPI_W0 { + &self.spi_w0 + } + #[doc = "0x9c - SPI CPU-controlled buffer1"] + #[inline(always)] + pub const fn spi_w1(&self) -> &SPI_W1 { + &self.spi_w1 + } + #[doc = "0xa0 - SPI CPU-controlled buffer2"] + #[inline(always)] + pub const fn spi_w2(&self) -> &SPI_W2 { + &self.spi_w2 + } + #[doc = "0xa4 - SPI CPU-controlled buffer3"] + #[inline(always)] + pub const fn spi_w3(&self) -> &SPI_W3 { + &self.spi_w3 + } + #[doc = "0xa8 - SPI CPU-controlled buffer4"] + #[inline(always)] + pub const fn spi_w4(&self) -> &SPI_W4 { + &self.spi_w4 + } + #[doc = "0xac - SPI CPU-controlled buffer5"] + #[inline(always)] + pub const fn spi_w5(&self) -> &SPI_W5 { + &self.spi_w5 + } + #[doc = "0xb0 - SPI CPU-controlled buffer6"] + #[inline(always)] + pub const fn spi_w6(&self) -> &SPI_W6 { + &self.spi_w6 + } + #[doc = "0xb4 - SPI CPU-controlled buffer7"] + #[inline(always)] + pub const fn spi_w7(&self) -> &SPI_W7 { + &self.spi_w7 + } + #[doc = "0xb8 - SPI CPU-controlled buffer8"] + #[inline(always)] + pub const fn spi_w8(&self) -> &SPI_W8 { + &self.spi_w8 + } + #[doc = "0xbc - SPI CPU-controlled buffer9"] + #[inline(always)] + pub const fn spi_w9(&self) -> &SPI_W9 { + &self.spi_w9 + } + #[doc = "0xc0 - SPI CPU-controlled buffer10"] + #[inline(always)] + pub const fn spi_w10(&self) -> &SPI_W10 { + &self.spi_w10 + } + #[doc = "0xc4 - SPI CPU-controlled buffer11"] + #[inline(always)] + pub const fn spi_w11(&self) -> &SPI_W11 { + &self.spi_w11 + } + #[doc = "0xc8 - SPI CPU-controlled buffer12"] + #[inline(always)] + pub const fn spi_w12(&self) -> &SPI_W12 { + &self.spi_w12 + } + #[doc = "0xcc - SPI CPU-controlled buffer13"] + #[inline(always)] + pub const fn spi_w13(&self) -> &SPI_W13 { + &self.spi_w13 + } + #[doc = "0xd0 - SPI CPU-controlled buffer14"] + #[inline(always)] + pub const fn spi_w14(&self) -> &SPI_W14 { + &self.spi_w14 + } + #[doc = "0xd4 - SPI CPU-controlled buffer15"] + #[inline(always)] + pub const fn spi_w15(&self) -> &SPI_W15 { + &self.spi_w15 + } + #[doc = "0xe0 - SPI slave control register"] + #[inline(always)] + pub const fn spi_slave(&self) -> &SPI_SLAVE { + &self.spi_slave + } + #[doc = "0xe4 - SPI slave control register 1"] + #[inline(always)] + pub const fn spi_slave1(&self) -> &SPI_SLAVE1 { + &self.spi_slave1 + } + #[doc = "0xe8 - SPI module clock and register clock control"] + #[inline(always)] + pub const fn spi_clk_gate(&self) -> &SPI_CLK_GATE { + &self.spi_clk_gate + } + #[doc = "0xf0 - Version control"] + #[inline(always)] + pub const fn spi_date(&self) -> &SPI_DATE { + &self.spi_date + } +} +#[doc = "SPI_CMD (rw) register accessor: Command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_cmd`] module"] +pub type SPI_CMD = crate::Reg; +#[doc = "Command control register"] +pub mod spi_cmd; +#[doc = "SPI_ADDR (rw) register accessor: Address value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_addr`] module"] +pub type SPI_ADDR = crate::Reg; +#[doc = "Address value register"] +pub mod spi_addr; +#[doc = "SPI_CTRL (rw) register accessor: SPI control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ctrl`] module"] +pub type SPI_CTRL = crate::Reg; +#[doc = "SPI control register"] +pub mod spi_ctrl; +#[doc = "SPI_CLOCK (rw) register accessor: SPI clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clock::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_clock`] module"] +pub type SPI_CLOCK = crate::Reg; +#[doc = "SPI clock control register"] +pub mod spi_clock; +#[doc = "SPI_USER (rw) register accessor: SPI USER control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user`] module"] +pub type SPI_USER = crate::Reg; +#[doc = "SPI USER control register"] +pub mod spi_user; +#[doc = "SPI_USER1 (rw) register accessor: SPI USER control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user1`] module"] +pub type SPI_USER1 = crate::Reg; +#[doc = "SPI USER control register 1"] +pub mod spi_user1; +#[doc = "SPI_USER2 (rw) register accessor: SPI USER control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_user2`] module"] +pub type SPI_USER2 = crate::Reg; +#[doc = "SPI USER control register 2"] +pub mod spi_user2; +#[doc = "SPI_MS_DLEN (rw) register accessor: SPI data bit length control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ms_dlen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ms_dlen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_ms_dlen`] module"] +pub type SPI_MS_DLEN = crate::Reg; +#[doc = "SPI data bit length control register"] +pub mod spi_ms_dlen; +#[doc = "SPI_MISC (rw) register accessor: SPI misc register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_misc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_misc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_misc`] module"] +pub type SPI_MISC = crate::Reg; +#[doc = "SPI misc register"] +pub mod spi_misc; +#[doc = "SPI_DIN_MODE (rw) register accessor: SPI input delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_din_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_din_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_din_mode`] module"] +pub type SPI_DIN_MODE = crate::Reg; +#[doc = "SPI input delay mode configuration"] +pub mod spi_din_mode; +#[doc = "SPI_DIN_NUM (rw) register accessor: SPI input delay number configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_din_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_din_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_din_num`] module"] +pub type SPI_DIN_NUM = crate::Reg; +#[doc = "SPI input delay number configuration"] +pub mod spi_din_num; +#[doc = "SPI_DOUT_MODE (rw) register accessor: SPI output delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dout_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dout_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dout_mode`] module"] +pub type SPI_DOUT_MODE = crate::Reg; +#[doc = "SPI output delay mode configuration"] +pub mod spi_dout_mode; +#[doc = "SPI_DMA_CONF (rw) register accessor: SPI DMA control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_conf`] module"] +pub type SPI_DMA_CONF = crate::Reg; +#[doc = "SPI DMA control register"] +pub mod spi_dma_conf; +#[doc = "SPI_DMA_INT_ENA (rw) register accessor: SPI interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_int_ena`] module"] +pub type SPI_DMA_INT_ENA = crate::Reg; +#[doc = "SPI interrupt enable register"] +pub mod spi_dma_int_ena; +#[doc = "SPI_DMA_INT_CLR (w) register accessor: SPI interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_int_clr`] module"] +pub type SPI_DMA_INT_CLR = crate::Reg; +#[doc = "SPI interrupt clear register"] +pub mod spi_dma_int_clr; +#[doc = "SPI_DMA_INT_RAW (rw) register accessor: SPI interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_int_raw`] module"] +pub type SPI_DMA_INT_RAW = crate::Reg; +#[doc = "SPI interrupt raw register"] +pub mod spi_dma_int_raw; +#[doc = "SPI_DMA_INT_ST (r) register accessor: SPI interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_int_st`] module"] +pub type SPI_DMA_INT_ST = crate::Reg; +#[doc = "SPI interrupt status register"] +pub mod spi_dma_int_st; +#[doc = "SPI_DMA_INT_SET (w) register accessor: SPI interrupt software set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_dma_int_set`] module"] +pub type SPI_DMA_INT_SET = crate::Reg; +#[doc = "SPI interrupt software set register"] +pub mod spi_dma_int_set; +#[doc = "SPI_W0 (rw) register accessor: SPI CPU-controlled buffer0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w0`] module"] +pub type SPI_W0 = crate::Reg; +#[doc = "SPI CPU-controlled buffer0"] +pub mod spi_w0; +#[doc = "SPI_W1 (rw) register accessor: SPI CPU-controlled buffer1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w1`] module"] +pub type SPI_W1 = crate::Reg; +#[doc = "SPI CPU-controlled buffer1"] +pub mod spi_w1; +#[doc = "SPI_W2 (rw) register accessor: SPI CPU-controlled buffer2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w2`] module"] +pub type SPI_W2 = crate::Reg; +#[doc = "SPI CPU-controlled buffer2"] +pub mod spi_w2; +#[doc = "SPI_W3 (rw) register accessor: SPI CPU-controlled buffer3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w3`] module"] +pub type SPI_W3 = crate::Reg; +#[doc = "SPI CPU-controlled buffer3"] +pub mod spi_w3; +#[doc = "SPI_W4 (rw) register accessor: SPI CPU-controlled buffer4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w4`] module"] +pub type SPI_W4 = crate::Reg; +#[doc = "SPI CPU-controlled buffer4"] +pub mod spi_w4; +#[doc = "SPI_W5 (rw) register accessor: SPI CPU-controlled buffer5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w5`] module"] +pub type SPI_W5 = crate::Reg; +#[doc = "SPI CPU-controlled buffer5"] +pub mod spi_w5; +#[doc = "SPI_W6 (rw) register accessor: SPI CPU-controlled buffer6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w6`] module"] +pub type SPI_W6 = crate::Reg; +#[doc = "SPI CPU-controlled buffer6"] +pub mod spi_w6; +#[doc = "SPI_W7 (rw) register accessor: SPI CPU-controlled buffer7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w7`] module"] +pub type SPI_W7 = crate::Reg; +#[doc = "SPI CPU-controlled buffer7"] +pub mod spi_w7; +#[doc = "SPI_W8 (rw) register accessor: SPI CPU-controlled buffer8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w8`] module"] +pub type SPI_W8 = crate::Reg; +#[doc = "SPI CPU-controlled buffer8"] +pub mod spi_w8; +#[doc = "SPI_W9 (rw) register accessor: SPI CPU-controlled buffer9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w9`] module"] +pub type SPI_W9 = crate::Reg; +#[doc = "SPI CPU-controlled buffer9"] +pub mod spi_w9; +#[doc = "SPI_W10 (rw) register accessor: SPI CPU-controlled buffer10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w10`] module"] +pub type SPI_W10 = crate::Reg; +#[doc = "SPI CPU-controlled buffer10"] +pub mod spi_w10; +#[doc = "SPI_W11 (rw) register accessor: SPI CPU-controlled buffer11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w11`] module"] +pub type SPI_W11 = crate::Reg; +#[doc = "SPI CPU-controlled buffer11"] +pub mod spi_w11; +#[doc = "SPI_W12 (rw) register accessor: SPI CPU-controlled buffer12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w12`] module"] +pub type SPI_W12 = crate::Reg; +#[doc = "SPI CPU-controlled buffer12"] +pub mod spi_w12; +#[doc = "SPI_W13 (rw) register accessor: SPI CPU-controlled buffer13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w13`] module"] +pub type SPI_W13 = crate::Reg; +#[doc = "SPI CPU-controlled buffer13"] +pub mod spi_w13; +#[doc = "SPI_W14 (rw) register accessor: SPI CPU-controlled buffer14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w14`] module"] +pub type SPI_W14 = crate::Reg; +#[doc = "SPI CPU-controlled buffer14"] +pub mod spi_w14; +#[doc = "SPI_W15 (rw) register accessor: SPI CPU-controlled buffer15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w15::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_w15`] module"] +pub type SPI_W15 = crate::Reg; +#[doc = "SPI CPU-controlled buffer15"] +pub mod spi_w15; +#[doc = "SPI_SLAVE (rw) register accessor: SPI slave control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave`] module"] +pub type SPI_SLAVE = crate::Reg; +#[doc = "SPI slave control register"] +pub mod spi_slave; +#[doc = "SPI_SLAVE1 (rw) register accessor: SPI slave control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_slave1`] module"] +pub type SPI_SLAVE1 = crate::Reg; +#[doc = "SPI slave control register 1"] +pub mod spi_slave1; +#[doc = "SPI_CLK_GATE (rw) register accessor: SPI module clock and register clock control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clk_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clk_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_clk_gate`] module"] +pub type SPI_CLK_GATE = crate::Reg; +#[doc = "SPI module clock and register clock control"] +pub mod spi_clk_gate; +#[doc = "SPI_DATE (rw) register accessor: Version control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_date`] module"] +pub type SPI_DATE = crate::Reg; +#[doc = "Version control"] +pub mod spi_date; diff --git a/esp32p4/src/spi3/spi_addr.rs b/esp32p4/src/spi3/spi_addr.rs new file mode 100644 index 0000000000..9a124b32c6 --- /dev/null +++ b/esp32p4/src/spi3/spi_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_USR_ADDR_VALUE` reader - Address to slave. Can be configured in CONF state."] +pub type SPI_USR_ADDR_VALUE_R = crate::FieldReader; +#[doc = "Field `SPI_USR_ADDR_VALUE` writer - Address to slave. Can be configured in CONF state."] +pub type SPI_USR_ADDR_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_addr_value(&self) -> SPI_USR_ADDR_VALUE_R { + SPI_USR_ADDR_VALUE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_ADDR") + .field( + "spi_usr_addr_value", + &format_args!("{}", self.spi_usr_addr_value().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_addr_value(&mut self) -> SPI_USR_ADDR_VALUE_W { + SPI_USR_ADDR_VALUE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Address value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_ADDR_SPEC; +impl crate::RegisterSpec for SPI_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_addr::R`](R) reader structure"] +impl crate::Readable for SPI_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_addr::W`](W) writer structure"] +impl crate::Writable for SPI_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_ADDR to value 0"] +impl crate::Resettable for SPI_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_clk_gate.rs b/esp32p4/src/spi3/spi_clk_gate.rs new file mode 100644 index 0000000000..73e52476cc --- /dev/null +++ b/esp32p4/src/spi3/spi_clk_gate.rs @@ -0,0 +1,101 @@ +#[doc = "Register `SPI_CLK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_CLK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_CLK_EN` reader - Set this bit to enable clk gate"] +pub type SPI_CLK_EN_R = crate::BitReader; +#[doc = "Field `SPI_CLK_EN` writer - Set this bit to enable clk gate"] +pub type SPI_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_CLK_ACTIVE` reader - Set this bit to power on the SPI module clock."] +pub type SPI_MST_CLK_ACTIVE_R = crate::BitReader; +#[doc = "Field `SPI_MST_CLK_ACTIVE` writer - Set this bit to power on the SPI module clock."] +pub type SPI_MST_CLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_CLK_SEL` reader - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."] +pub type SPI_MST_CLK_SEL_R = crate::BitReader; +#[doc = "Field `SPI_MST_CLK_SEL` writer - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."] +pub type SPI_MST_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable clk gate"] + #[inline(always)] + pub fn spi_clk_en(&self) -> SPI_CLK_EN_R { + SPI_CLK_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to power on the SPI module clock."] + #[inline(always)] + pub fn spi_mst_clk_active(&self) -> SPI_MST_CLK_ACTIVE_R { + SPI_MST_CLK_ACTIVE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."] + #[inline(always)] + pub fn spi_mst_clk_sel(&self) -> SPI_MST_CLK_SEL_R { + SPI_MST_CLK_SEL_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_CLK_GATE") + .field("spi_clk_en", &format_args!("{}", self.spi_clk_en().bit())) + .field( + "spi_mst_clk_active", + &format_args!("{}", self.spi_mst_clk_active().bit()), + ) + .field( + "spi_mst_clk_sel", + &format_args!("{}", self.spi_mst_clk_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable clk gate"] + #[inline(always)] + #[must_use] + pub fn spi_clk_en(&mut self) -> SPI_CLK_EN_W { + SPI_CLK_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to power on the SPI module clock."] + #[inline(always)] + #[must_use] + pub fn spi_mst_clk_active(&mut self) -> SPI_MST_CLK_ACTIVE_W { + SPI_MST_CLK_ACTIVE_W::new(self, 1) + } + #[doc = "Bit 2 - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK."] + #[inline(always)] + #[must_use] + pub fn spi_mst_clk_sel(&mut self) -> SPI_MST_CLK_SEL_W { + SPI_MST_CLK_SEL_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI module clock and register clock control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clk_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clk_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_CLK_GATE_SPEC; +impl crate::RegisterSpec for SPI_CLK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_clk_gate::R`](R) reader structure"] +impl crate::Readable for SPI_CLK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_clk_gate::W`](W) writer structure"] +impl crate::Writable for SPI_CLK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_CLK_GATE to value 0"] +impl crate::Resettable for SPI_CLK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_clock.rs b/esp32p4/src/spi3/spi_clock.rs new file mode 100644 index 0000000000..b79447a272 --- /dev/null +++ b/esp32p4/src/spi3/spi_clock.rs @@ -0,0 +1,142 @@ +#[doc = "Register `SPI_CLOCK` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_CLOCK` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_CLKCNT_L` reader - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."] +pub type SPI_CLKCNT_L_R = crate::FieldReader; +#[doc = "Field `SPI_CLKCNT_L` writer - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."] +pub type SPI_CLKCNT_L_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_CLKCNT_H` reader - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."] +pub type SPI_CLKCNT_H_R = crate::FieldReader; +#[doc = "Field `SPI_CLKCNT_H` writer - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."] +pub type SPI_CLKCNT_H_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_CLKCNT_N` reader - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."] +pub type SPI_CLKCNT_N_R = crate::FieldReader; +#[doc = "Field `SPI_CLKCNT_N` writer - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."] +pub type SPI_CLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SPI_CLKDIV_PRE` reader - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."] +pub type SPI_CLKDIV_PRE_R = crate::FieldReader; +#[doc = "Field `SPI_CLKDIV_PRE` writer - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."] +pub type SPI_CLKDIV_PRE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SPI_CLK_EQU_SYSCLK` reader - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."] +pub type SPI_CLK_EQU_SYSCLK_R = crate::BitReader; +#[doc = "Field `SPI_CLK_EQU_SYSCLK` writer - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."] +pub type SPI_CLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clkcnt_l(&self) -> SPI_CLKCNT_L_R { + SPI_CLKCNT_L_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clkcnt_h(&self) -> SPI_CLKCNT_H_R { + SPI_CLKCNT_H_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:17 - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clkcnt_n(&self) -> SPI_CLKCNT_N_R { + SPI_CLKCNT_N_R::new(((self.bits >> 12) & 0x3f) as u8) + } + #[doc = "Bits 18:21 - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clkdiv_pre(&self) -> SPI_CLKDIV_PRE_R { + SPI_CLKDIV_PRE_R::new(((self.bits >> 18) & 0x0f) as u8) + } + #[doc = "Bit 31 - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clk_equ_sysclk(&self) -> SPI_CLK_EQU_SYSCLK_R { + SPI_CLK_EQU_SYSCLK_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_CLOCK") + .field( + "spi_clkcnt_l", + &format_args!("{}", self.spi_clkcnt_l().bits()), + ) + .field( + "spi_clkcnt_h", + &format_args!("{}", self.spi_clkcnt_h().bits()), + ) + .field( + "spi_clkcnt_n", + &format_args!("{}", self.spi_clkcnt_n().bits()), + ) + .field( + "spi_clkdiv_pre", + &format_args!("{}", self.spi_clkdiv_pre().bits()), + ) + .field( + "spi_clk_equ_sysclk", + &format_args!("{}", self.spi_clk_equ_sysclk().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clkcnt_l(&mut self) -> SPI_CLKCNT_L_W { + SPI_CLKCNT_L_W::new(self, 0) + } + #[doc = "Bits 6:11 - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clkcnt_h(&mut self) -> SPI_CLKCNT_H_W { + SPI_CLKCNT_H_W::new(self, 6) + } + #[doc = "Bits 12:17 - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clkcnt_n(&mut self) -> SPI_CLKCNT_N_W { + SPI_CLKCNT_N_W::new(self, 12) + } + #[doc = "Bits 18:21 - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clkdiv_pre(&mut self) -> SPI_CLKDIV_PRE_W { + SPI_CLKDIV_PRE_W::new(self, 18) + } + #[doc = "Bit 31 - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clk_equ_sysclk(&mut self) -> SPI_CLK_EQU_SYSCLK_W { + SPI_CLK_EQU_SYSCLK_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_clock::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_clock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_CLOCK_SPEC; +impl crate::RegisterSpec for SPI_CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_clock::R`](R) reader structure"] +impl crate::Readable for SPI_CLOCK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_clock::W`](W) writer structure"] +impl crate::Writable for SPI_CLOCK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_CLOCK to value 0x8000_3043"] +impl crate::Resettable for SPI_CLOCK_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_3043; +} diff --git a/esp32p4/src/spi3/spi_cmd.rs b/esp32p4/src/spi3/spi_cmd.rs new file mode 100644 index 0000000000..1d6cfc2ca2 --- /dev/null +++ b/esp32p4/src/spi3/spi_cmd.rs @@ -0,0 +1,71 @@ +#[doc = "Register `SPI_CMD` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_CMD` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_UPDATE` writer - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode."] +pub type SPI_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR` reader - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."] +pub type SPI_USR_R = crate::BitReader; +#[doc = "Field `SPI_USR` writer - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."] +pub type SPI_USR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."] + #[inline(always)] + pub fn spi_usr(&self) -> SPI_USR_R { + SPI_USR_R::new(((self.bits >> 24) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_CMD") + .field("spi_usr", &format_args!("{}", self.spi_usr().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 23 - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode."] + #[inline(always)] + #[must_use] + pub fn spi_update(&mut self) -> SPI_UPDATE_W { + SPI_UPDATE_W::new(self, 23) + } + #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."] + #[inline(always)] + #[must_use] + pub fn spi_usr(&mut self) -> SPI_USR_W { + SPI_USR_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_CMD_SPEC; +impl crate::RegisterSpec for SPI_CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_cmd::R`](R) reader structure"] +impl crate::Readable for SPI_CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_cmd::W`](W) writer structure"] +impl crate::Writable for SPI_CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_CMD to value 0"] +impl crate::Resettable for SPI_CMD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_ctrl.rs b/esp32p4/src/spi3/spi_ctrl.rs new file mode 100644 index 0000000000..c955647154 --- /dev/null +++ b/esp32p4/src/spi3/spi_ctrl.rs @@ -0,0 +1,285 @@ +#[doc = "Register `SPI_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DUMMY_OUT` reader - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."] +pub type SPI_DUMMY_OUT_R = crate::BitReader; +#[doc = "Field `SPI_DUMMY_OUT` writer - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."] +pub type SPI_DUMMY_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FADDR_DUAL` reader - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FADDR_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_FADDR_DUAL` writer - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FADDR_QUAD` reader - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FADDR_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_FADDR_QUAD` writer - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FCMD_DUAL` reader - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FCMD_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_FCMD_DUAL` writer - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FCMD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FCMD_QUAD` reader - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FCMD_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_FCMD_QUAD` writer - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] +pub type SPI_FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_FREAD_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_FREAD_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."] +pub type SPI_Q_POL_R = crate::BitReader; +#[doc = "Field `SPI_Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."] +pub type SPI_Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."] +pub type SPI_D_POL_R = crate::BitReader; +#[doc = "Field `SPI_D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."] +pub type SPI_D_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_HOLD_POL` reader - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] +pub type SPI_HOLD_POL_R = crate::BitReader; +#[doc = "Field `SPI_HOLD_POL` writer - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] +pub type SPI_HOLD_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_WP_POL` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] +pub type SPI_WP_POL_R = crate::BitReader; +#[doc = "Field `SPI_WP_POL` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] +pub type SPI_WP_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_RD_BIT_ORDER` reader - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."] +pub type SPI_RD_BIT_ORDER_R = crate::FieldReader; +#[doc = "Field `SPI_RD_BIT_ORDER` writer - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."] +pub type SPI_RD_BIT_ORDER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_WR_BIT_ORDER` reader - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."] +pub type SPI_WR_BIT_ORDER_R = crate::FieldReader; +#[doc = "Field `SPI_WR_BIT_ORDER` writer - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."] +pub type SPI_WR_BIT_ORDER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dummy_out(&self) -> SPI_DUMMY_OUT_R { + SPI_DUMMY_OUT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_faddr_dual(&self) -> SPI_FADDR_DUAL_R { + SPI_FADDR_DUAL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_faddr_quad(&self) -> SPI_FADDR_QUAD_R { + SPI_FADDR_QUAD_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fcmd_dual(&self) -> SPI_FCMD_DUAL_R { + SPI_FCMD_DUAL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fcmd_quad(&self) -> SPI_FCMD_QUAD_R { + SPI_FCMD_QUAD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fread_dual(&self) -> SPI_FREAD_DUAL_R { + SPI_FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fread_quad(&self) -> SPI_FREAD_QUAD_R { + SPI_FREAD_QUAD_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_q_pol(&self) -> SPI_Q_POL_R { + SPI_Q_POL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_d_pol(&self) -> SPI_D_POL_R { + SPI_D_POL_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_hold_pol(&self) -> SPI_HOLD_POL_R { + SPI_HOLD_POL_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_wp_pol(&self) -> SPI_WP_POL_R { + SPI_WP_POL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 23:24 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_rd_bit_order(&self) -> SPI_RD_BIT_ORDER_R { + SPI_RD_BIT_ORDER_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bits 25:26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_wr_bit_order(&self) -> SPI_WR_BIT_ORDER_R { + SPI_WR_BIT_ORDER_R::new(((self.bits >> 25) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_CTRL") + .field( + "spi_dummy_out", + &format_args!("{}", self.spi_dummy_out().bit()), + ) + .field( + "spi_faddr_dual", + &format_args!("{}", self.spi_faddr_dual().bit()), + ) + .field( + "spi_faddr_quad", + &format_args!("{}", self.spi_faddr_quad().bit()), + ) + .field( + "spi_fcmd_dual", + &format_args!("{}", self.spi_fcmd_dual().bit()), + ) + .field( + "spi_fcmd_quad", + &format_args!("{}", self.spi_fcmd_quad().bit()), + ) + .field( + "spi_fread_dual", + &format_args!("{}", self.spi_fread_dual().bit()), + ) + .field( + "spi_fread_quad", + &format_args!("{}", self.spi_fread_quad().bit()), + ) + .field("spi_q_pol", &format_args!("{}", self.spi_q_pol().bit())) + .field("spi_d_pol", &format_args!("{}", self.spi_d_pol().bit())) + .field( + "spi_hold_pol", + &format_args!("{}", self.spi_hold_pol().bit()), + ) + .field("spi_wp_pol", &format_args!("{}", self.spi_wp_pol().bit())) + .field( + "spi_rd_bit_order", + &format_args!("{}", self.spi_rd_bit_order().bits()), + ) + .field( + "spi_wr_bit_order", + &format_args!("{}", self.spi_wr_bit_order().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dummy_out(&mut self) -> SPI_DUMMY_OUT_W { + SPI_DUMMY_OUT_W::new(self, 3) + } + #[doc = "Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_faddr_dual(&mut self) -> SPI_FADDR_DUAL_W { + SPI_FADDR_DUAL_W::new(self, 5) + } + #[doc = "Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_faddr_quad(&mut self) -> SPI_FADDR_QUAD_W { + SPI_FADDR_QUAD_W::new(self, 6) + } + #[doc = "Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fcmd_dual(&mut self) -> SPI_FCMD_DUAL_W { + SPI_FCMD_DUAL_W::new(self, 8) + } + #[doc = "Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fcmd_quad(&mut self) -> SPI_FCMD_QUAD_W { + SPI_FCMD_QUAD_W::new(self, 9) + } + #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fread_dual(&mut self) -> SPI_FREAD_DUAL_W { + SPI_FREAD_DUAL_W::new(self, 14) + } + #[doc = "Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fread_quad(&mut self) -> SPI_FREAD_QUAD_W { + SPI_FREAD_QUAD_W::new(self, 15) + } + #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_q_pol(&mut self) -> SPI_Q_POL_W { + SPI_Q_POL_W::new(self, 18) + } + #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_d_pol(&mut self) -> SPI_D_POL_W { + SPI_D_POL_W::new(self, 19) + } + #[doc = "Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_hold_pol(&mut self) -> SPI_HOLD_POL_W { + SPI_HOLD_POL_W::new(self, 20) + } + #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_wp_pol(&mut self) -> SPI_WP_POL_W { + SPI_WP_POL_W::new(self, 21) + } + #[doc = "Bits 23:24 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_rd_bit_order(&mut self) -> SPI_RD_BIT_ORDER_W { + SPI_RD_BIT_ORDER_W::new(self, 23) + } + #[doc = "Bits 25:26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_wr_bit_order(&mut self) -> SPI_WR_BIT_ORDER_W { + SPI_WR_BIT_ORDER_W::new(self, 25) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_CTRL_SPEC; +impl crate::RegisterSpec for SPI_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_ctrl::R`](R) reader structure"] +impl crate::Readable for SPI_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_ctrl::W`](W) writer structure"] +impl crate::Writable for SPI_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_CTRL to value 0x003c_0000"] +impl crate::Resettable for SPI_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x003c_0000; +} diff --git a/esp32p4/src/spi3/spi_date.rs b/esp32p4/src/spi3/spi_date.rs new file mode 100644 index 0000000000..54622f1ceb --- /dev/null +++ b/esp32p4/src/spi3/spi_date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DATE` reader - SPI register version."] +pub type SPI_DATE_R = crate::FieldReader; +#[doc = "Field `SPI_DATE` writer - SPI register version."] +pub type SPI_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - SPI register version."] + #[inline(always)] + pub fn spi_date(&self) -> SPI_DATE_R { + SPI_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DATE") + .field("spi_date", &format_args!("{}", self.spi_date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - SPI register version."] + #[inline(always)] + #[must_use] + pub fn spi_date(&mut self) -> SPI_DATE_W { + SPI_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DATE_SPEC; +impl crate::RegisterSpec for SPI_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_date::R`](R) reader structure"] +impl crate::Readable for SPI_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_date::W`](W) writer structure"] +impl crate::Writable for SPI_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DATE to value 0x0220_7202"] +impl crate::Resettable for SPI_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_7202; +} diff --git a/esp32p4/src/spi3/spi_din_mode.rs b/esp32p4/src/spi3/spi_din_mode.rs new file mode 100644 index 0000000000..34ee41f141 --- /dev/null +++ b/esp32p4/src/spi3/spi_din_mode.rs @@ -0,0 +1,142 @@ +#[doc = "Register `SPI_DIN_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DIN_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DIN0_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN0_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN0_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN0_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN1_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN1_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN1_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN1_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN2_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN2_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN2_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN2_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN3_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN3_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_DIN3_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] +pub type SPI_DIN3_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_TIMING_HCLK_ACTIVE` reader - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."] +pub type SPI_TIMING_HCLK_ACTIVE_R = crate::BitReader; +#[doc = "Field `SPI_TIMING_HCLK_ACTIVE` writer - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."] +pub type SPI_TIMING_HCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din0_mode(&self) -> SPI_DIN0_MODE_R { + SPI_DIN0_MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din1_mode(&self) -> SPI_DIN1_MODE_R { + SPI_DIN1_MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din2_mode(&self) -> SPI_DIN2_MODE_R { + SPI_DIN2_MODE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din3_mode(&self) -> SPI_DIN3_MODE_R { + SPI_DIN3_MODE_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_timing_hclk_active(&self) -> SPI_TIMING_HCLK_ACTIVE_R { + SPI_TIMING_HCLK_ACTIVE_R::new(((self.bits >> 16) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DIN_MODE") + .field( + "spi_din0_mode", + &format_args!("{}", self.spi_din0_mode().bits()), + ) + .field( + "spi_din1_mode", + &format_args!("{}", self.spi_din1_mode().bits()), + ) + .field( + "spi_din2_mode", + &format_args!("{}", self.spi_din2_mode().bits()), + ) + .field( + "spi_din3_mode", + &format_args!("{}", self.spi_din3_mode().bits()), + ) + .field( + "spi_timing_hclk_active", + &format_args!("{}", self.spi_timing_hclk_active().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din0_mode(&mut self) -> SPI_DIN0_MODE_W { + SPI_DIN0_MODE_W::new(self, 0) + } + #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din1_mode(&mut self) -> SPI_DIN1_MODE_W { + SPI_DIN1_MODE_W::new(self, 2) + } + #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din2_mode(&mut self) -> SPI_DIN2_MODE_W { + SPI_DIN2_MODE_W::new(self, 4) + } + #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din3_mode(&mut self) -> SPI_DIN3_MODE_W { + SPI_DIN3_MODE_W::new(self, 6) + } + #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_timing_hclk_active(&mut self) -> SPI_TIMING_HCLK_ACTIVE_W { + SPI_TIMING_HCLK_ACTIVE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI input delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_din_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_din_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DIN_MODE_SPEC; +impl crate::RegisterSpec for SPI_DIN_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_din_mode::R`](R) reader structure"] +impl crate::Readable for SPI_DIN_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_din_mode::W`](W) writer structure"] +impl crate::Writable for SPI_DIN_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DIN_MODE to value 0"] +impl crate::Resettable for SPI_DIN_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_din_num.rs b/esp32p4/src/spi3/spi_din_num.rs new file mode 100644 index 0000000000..51923d59ed --- /dev/null +++ b/esp32p4/src/spi3/spi_din_num.rs @@ -0,0 +1,123 @@ +#[doc = "Register `SPI_DIN_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DIN_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DIN0_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN0_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN0_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN0_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN1_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN1_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN1_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN1_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN2_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN2_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN2_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN2_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_DIN3_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN3_NUM_R = crate::FieldReader; +#[doc = "Field `SPI_DIN3_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] +pub type SPI_DIN3_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din0_num(&self) -> SPI_DIN0_NUM_R { + SPI_DIN0_NUM_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din1_num(&self) -> SPI_DIN1_NUM_R { + SPI_DIN1_NUM_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din2_num(&self) -> SPI_DIN2_NUM_R { + SPI_DIN2_NUM_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + pub fn spi_din3_num(&self) -> SPI_DIN3_NUM_R { + SPI_DIN3_NUM_R::new(((self.bits >> 6) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DIN_NUM") + .field( + "spi_din0_num", + &format_args!("{}", self.spi_din0_num().bits()), + ) + .field( + "spi_din1_num", + &format_args!("{}", self.spi_din1_num().bits()), + ) + .field( + "spi_din2_num", + &format_args!("{}", self.spi_din2_num().bits()), + ) + .field( + "spi_din3_num", + &format_args!("{}", self.spi_din3_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din0_num(&mut self) -> SPI_DIN0_NUM_W { + SPI_DIN0_NUM_W::new(self, 0) + } + #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din1_num(&mut self) -> SPI_DIN1_NUM_W { + SPI_DIN1_NUM_W::new(self, 2) + } + #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din2_num(&mut self) -> SPI_DIN2_NUM_W { + SPI_DIN2_NUM_W::new(self, 4) + } + #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_din3_num(&mut self) -> SPI_DIN3_NUM_W { + SPI_DIN3_NUM_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI input delay number configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_din_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_din_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DIN_NUM_SPEC; +impl crate::RegisterSpec for SPI_DIN_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_din_num::R`](R) reader structure"] +impl crate::Readable for SPI_DIN_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_din_num::W`](W) writer structure"] +impl crate::Writable for SPI_DIN_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DIN_NUM to value 0"] +impl crate::Resettable for SPI_DIN_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_dma_conf.rs b/esp32p4/src/spi3/spi_dma_conf.rs new file mode 100644 index 0000000000..dc684a050d --- /dev/null +++ b/esp32p4/src/spi3/spi_dma_conf.rs @@ -0,0 +1,211 @@ +#[doc = "Register `SPI_DMA_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DMA_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY` reader - Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data."] +pub type SPI_DMA_OUTFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `SPI_DMA_INFIFO_FULL` reader - Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data."] +pub type SPI_DMA_INFIFO_FULL_R = crate::BitReader; +#[doc = "Field `SPI_DMA_SLV_SEG_TRANS_EN` reader - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."] +pub type SPI_DMA_SLV_SEG_TRANS_EN_R = crate::BitReader; +#[doc = "Field `SPI_DMA_SLV_SEG_TRANS_EN` writer - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."] +pub type SPI_DMA_SLV_SEG_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RX_SEG_TRANS_CLR_EN` reader - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."] +pub type SPI_SLV_RX_SEG_TRANS_CLR_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RX_SEG_TRANS_CLR_EN` writer - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."] +pub type SPI_SLV_RX_SEG_TRANS_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_TX_SEG_TRANS_CLR_EN` reader - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."] +pub type SPI_SLV_TX_SEG_TRANS_CLR_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_TX_SEG_TRANS_CLR_EN` writer - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."] +pub type SPI_SLV_TX_SEG_TRANS_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_RX_EOF_EN` reader - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."] +pub type SPI_RX_EOF_EN_R = crate::BitReader; +#[doc = "Field `SPI_RX_EOF_EN` writer - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."] +pub type SPI_RX_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_RX_ENA` reader - Set this bit to enable SPI DMA controlled receive data mode."] +pub type SPI_DMA_RX_ENA_R = crate::BitReader; +#[doc = "Field `SPI_DMA_RX_ENA` writer - Set this bit to enable SPI DMA controlled receive data mode."] +pub type SPI_DMA_RX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_TX_ENA` reader - Set this bit to enable SPI DMA controlled send data mode."] +pub type SPI_DMA_TX_ENA_R = crate::BitReader; +#[doc = "Field `SPI_DMA_TX_ENA` writer - Set this bit to enable SPI DMA controlled send data mode."] +pub type SPI_DMA_TX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_RX_AFIFO_RST` writer - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer."] +pub type SPI_RX_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_BUF_AFIFO_RST` writer - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer."] +pub type SPI_BUF_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_AFIFO_RST` writer - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer."] +pub type SPI_DMA_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data."] + #[inline(always)] + pub fn spi_dma_outfifo_empty(&self) -> SPI_DMA_OUTFIFO_EMPTY_R { + SPI_DMA_OUTFIFO_EMPTY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data."] + #[inline(always)] + pub fn spi_dma_infifo_full(&self) -> SPI_DMA_INFIFO_FULL_R { + SPI_DMA_INFIFO_FULL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."] + #[inline(always)] + pub fn spi_dma_slv_seg_trans_en(&self) -> SPI_DMA_SLV_SEG_TRANS_EN_R { + SPI_DMA_SLV_SEG_TRANS_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."] + #[inline(always)] + pub fn spi_slv_rx_seg_trans_clr_en(&self) -> SPI_SLV_RX_SEG_TRANS_CLR_EN_R { + SPI_SLV_RX_SEG_TRANS_CLR_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."] + #[inline(always)] + pub fn spi_slv_tx_seg_trans_clr_en(&self) -> SPI_SLV_TX_SEG_TRANS_CLR_EN_R { + SPI_SLV_TX_SEG_TRANS_CLR_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."] + #[inline(always)] + pub fn spi_rx_eof_en(&self) -> SPI_RX_EOF_EN_R { + SPI_RX_EOF_EN_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 27 - Set this bit to enable SPI DMA controlled receive data mode."] + #[inline(always)] + pub fn spi_dma_rx_ena(&self) -> SPI_DMA_RX_ENA_R { + SPI_DMA_RX_ENA_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Set this bit to enable SPI DMA controlled send data mode."] + #[inline(always)] + pub fn spi_dma_tx_ena(&self) -> SPI_DMA_TX_ENA_R { + SPI_DMA_TX_ENA_R::new(((self.bits >> 28) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DMA_CONF") + .field( + "spi_dma_outfifo_empty", + &format_args!("{}", self.spi_dma_outfifo_empty().bit()), + ) + .field( + "spi_dma_infifo_full", + &format_args!("{}", self.spi_dma_infifo_full().bit()), + ) + .field( + "spi_dma_slv_seg_trans_en", + &format_args!("{}", self.spi_dma_slv_seg_trans_en().bit()), + ) + .field( + "spi_slv_rx_seg_trans_clr_en", + &format_args!("{}", self.spi_slv_rx_seg_trans_clr_en().bit()), + ) + .field( + "spi_slv_tx_seg_trans_clr_en", + &format_args!("{}", self.spi_slv_tx_seg_trans_clr_en().bit()), + ) + .field( + "spi_rx_eof_en", + &format_args!("{}", self.spi_rx_eof_en().bit()), + ) + .field( + "spi_dma_rx_ena", + &format_args!("{}", self.spi_dma_rx_ena().bit()), + ) + .field( + "spi_dma_tx_ena", + &format_args!("{}", self.spi_dma_tx_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."] + #[inline(always)] + #[must_use] + pub fn spi_dma_slv_seg_trans_en(&mut self) -> SPI_DMA_SLV_SEG_TRANS_EN_W { + SPI_DMA_SLV_SEG_TRANS_EN_W::new(self, 18) + } + #[doc = "Bit 19 - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rx_seg_trans_clr_en( + &mut self, + ) -> SPI_SLV_RX_SEG_TRANS_CLR_EN_W { + SPI_SLV_RX_SEG_TRANS_CLR_EN_W::new(self, 19) + } + #[doc = "Bit 20 - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."] + #[inline(always)] + #[must_use] + pub fn spi_slv_tx_seg_trans_clr_en( + &mut self, + ) -> SPI_SLV_TX_SEG_TRANS_CLR_EN_W { + SPI_SLV_TX_SEG_TRANS_CLR_EN_W::new(self, 20) + } + #[doc = "Bit 21 - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."] + #[inline(always)] + #[must_use] + pub fn spi_rx_eof_en(&mut self) -> SPI_RX_EOF_EN_W { + SPI_RX_EOF_EN_W::new(self, 21) + } + #[doc = "Bit 27 - Set this bit to enable SPI DMA controlled receive data mode."] + #[inline(always)] + #[must_use] + pub fn spi_dma_rx_ena(&mut self) -> SPI_DMA_RX_ENA_W { + SPI_DMA_RX_ENA_W::new(self, 27) + } + #[doc = "Bit 28 - Set this bit to enable SPI DMA controlled send data mode."] + #[inline(always)] + #[must_use] + pub fn spi_dma_tx_ena(&mut self) -> SPI_DMA_TX_ENA_W { + SPI_DMA_TX_ENA_W::new(self, 28) + } + #[doc = "Bit 29 - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer."] + #[inline(always)] + #[must_use] + pub fn spi_rx_afifo_rst(&mut self) -> SPI_RX_AFIFO_RST_W { + SPI_RX_AFIFO_RST_W::new(self, 29) + } + #[doc = "Bit 30 - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer."] + #[inline(always)] + #[must_use] + pub fn spi_buf_afifo_rst(&mut self) -> SPI_BUF_AFIFO_RST_W { + SPI_BUF_AFIFO_RST_W::new(self, 30) + } + #[doc = "Bit 31 - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer."] + #[inline(always)] + #[must_use] + pub fn spi_dma_afifo_rst(&mut self) -> SPI_DMA_AFIFO_RST_W { + SPI_DMA_AFIFO_RST_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI DMA control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_CONF_SPEC; +impl crate::RegisterSpec for SPI_DMA_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_dma_conf::R`](R) reader structure"] +impl crate::Readable for SPI_DMA_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_dma_conf::W`](W) writer structure"] +impl crate::Writable for SPI_DMA_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DMA_CONF to value 0x03"] +impl crate::Resettable for SPI_DMA_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x03; +} diff --git a/esp32p4/src/spi3/spi_dma_int_clr.rs b/esp32p4/src/spi3/spi_dma_int_clr.rs new file mode 100644 index 0000000000..292646550b --- /dev/null +++ b/esp32p4/src/spi3/spi_dma_int_clr.rs @@ -0,0 +1,214 @@ +#[doc = "Register `SPI_DMA_INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_CLR` writer - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR` writer - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EX_QPI_INT_CLR` writer - The clear bit for SPI slave Ex_QPI interrupt."] +pub type SPI_SLV_EX_QPI_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EN_QPI_INT_CLR` writer - The clear bit for SPI slave En_QPI interrupt."] +pub type SPI_SLV_EN_QPI_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD7_INT_CLR` writer - The clear bit for SPI slave CMD7 interrupt."] +pub type SPI_SLV_CMD7_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD8_INT_CLR` writer - The clear bit for SPI slave CMD8 interrupt."] +pub type SPI_SLV_CMD8_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD9_INT_CLR` writer - The clear bit for SPI slave CMD9 interrupt."] +pub type SPI_SLV_CMD9_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMDA_INT_CLR` writer - The clear bit for SPI slave CMDA interrupt."] +pub type SPI_SLV_CMDA_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_CLR` writer - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] +pub type SPI_SLV_RD_DMA_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_CLR` writer - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] +pub type SPI_SLV_WR_DMA_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_CLR` writer - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] +pub type SPI_SLV_RD_BUF_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_CLR` writer - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] +pub type SPI_SLV_WR_BUF_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_TRANS_DONE_INT_CLR` writer - The clear bit for SPI_TRANS_DONE_INT interrupt."] +pub type SPI_TRANS_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_CLR` writer - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_CLR` writer - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_CLR` writer - The clear bit for SPI_SLV_CMD_ERR_INT interrupt."] +pub type SPI_SLV_CMD_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR` writer - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR` writer - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP2_INT_CLR` writer - The clear bit for SPI_APP2_INT interrupt."] +pub type SPI_APP2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP1_INT_CLR` writer - The clear bit for SPI_APP1_INT interrupt."] +pub type SPI_APP1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_infifo_full_err_int_clr( + &mut self, + ) -> SPI_DMA_INFIFO_FULL_ERR_INT_CLR_W { + SPI_DMA_INFIFO_FULL_ERR_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_outfifo_empty_err_int_clr( + &mut self, + ) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_W { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - The clear bit for SPI slave Ex_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_ex_qpi_int_clr(&mut self) -> SPI_SLV_EX_QPI_INT_CLR_W { + SPI_SLV_EX_QPI_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - The clear bit for SPI slave En_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_en_qpi_int_clr(&mut self) -> SPI_SLV_EN_QPI_INT_CLR_W { + SPI_SLV_EN_QPI_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - The clear bit for SPI slave CMD7 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd7_int_clr(&mut self) -> SPI_SLV_CMD7_INT_CLR_W { + SPI_SLV_CMD7_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - The clear bit for SPI slave CMD8 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd8_int_clr(&mut self) -> SPI_SLV_CMD8_INT_CLR_W { + SPI_SLV_CMD8_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - The clear bit for SPI slave CMD9 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd9_int_clr(&mut self) -> SPI_SLV_CMD9_INT_CLR_W { + SPI_SLV_CMD9_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - The clear bit for SPI slave CMDA interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmda_int_clr(&mut self) -> SPI_SLV_CMDA_INT_CLR_W { + SPI_SLV_CMDA_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_dma_done_int_clr( + &mut self, + ) -> SPI_SLV_RD_DMA_DONE_INT_CLR_W { + SPI_SLV_RD_DMA_DONE_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_dma_done_int_clr( + &mut self, + ) -> SPI_SLV_WR_DMA_DONE_INT_CLR_W { + SPI_SLV_WR_DMA_DONE_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_buf_done_int_clr( + &mut self, + ) -> SPI_SLV_RD_BUF_DONE_INT_CLR_W { + SPI_SLV_RD_BUF_DONE_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_buf_done_int_clr( + &mut self, + ) -> SPI_SLV_WR_BUF_DONE_INT_CLR_W { + SPI_SLV_WR_BUF_DONE_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - The clear bit for SPI_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_trans_done_int_clr(&mut self) -> SPI_TRANS_DONE_INT_CLR_W { + SPI_TRANS_DONE_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_seg_trans_done_int_clr( + &mut self, + ) -> SPI_DMA_SEG_TRANS_DONE_INT_CLR_W { + SPI_DMA_SEG_TRANS_DONE_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 15 - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_buf_addr_err_int_clr( + &mut self, + ) -> SPI_SLV_BUF_ADDR_ERR_INT_CLR_W { + SPI_SLV_BUF_ADDR_ERR_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - The clear bit for SPI_SLV_CMD_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd_err_int_clr(&mut self) -> SPI_SLV_CMD_ERR_INT_CLR_W { + SPI_SLV_CMD_ERR_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_rx_afifo_wfull_err_int_clr( + &mut self, + ) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_W { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_tx_afifo_rempty_err_int_clr( + &mut self, + ) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_W { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - The clear bit for SPI_APP2_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app2_int_clr(&mut self) -> SPI_APP2_INT_CLR_W { + SPI_APP2_INT_CLR_W::new(self, 19) + } + #[doc = "Bit 20 - The clear bit for SPI_APP1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app1_int_clr(&mut self) -> SPI_APP1_INT_CLR_W { + SPI_APP1_INT_CLR_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_INT_CLR_SPEC; +impl crate::RegisterSpec for SPI_DMA_INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`spi_dma_int_clr::W`](W) writer structure"] +impl crate::Writable for SPI_DMA_INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DMA_INT_CLR to value 0"] +impl crate::Resettable for SPI_DMA_INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_dma_int_ena.rs b/esp32p4/src/spi3/spi_dma_int_ena.rs new file mode 100644 index 0000000000..051d63b4e3 --- /dev/null +++ b/esp32p4/src/spi3/spi_dma_int_ena.rs @@ -0,0 +1,447 @@ +#[doc = "Register `SPI_DMA_INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DMA_INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_ENA` reader - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_ENA` writer - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA` reader - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA` writer - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EX_QPI_INT_ENA` reader - The enable bit for SPI slave Ex_QPI interrupt."] +pub type SPI_SLV_EX_QPI_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EX_QPI_INT_ENA` writer - The enable bit for SPI slave Ex_QPI interrupt."] +pub type SPI_SLV_EX_QPI_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EN_QPI_INT_ENA` reader - The enable bit for SPI slave En_QPI interrupt."] +pub type SPI_SLV_EN_QPI_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EN_QPI_INT_ENA` writer - The enable bit for SPI slave En_QPI interrupt."] +pub type SPI_SLV_EN_QPI_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD7_INT_ENA` reader - The enable bit for SPI slave CMD7 interrupt."] +pub type SPI_SLV_CMD7_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD7_INT_ENA` writer - The enable bit for SPI slave CMD7 interrupt."] +pub type SPI_SLV_CMD7_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD8_INT_ENA` reader - The enable bit for SPI slave CMD8 interrupt."] +pub type SPI_SLV_CMD8_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD8_INT_ENA` writer - The enable bit for SPI slave CMD8 interrupt."] +pub type SPI_SLV_CMD8_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD9_INT_ENA` reader - The enable bit for SPI slave CMD9 interrupt."] +pub type SPI_SLV_CMD9_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD9_INT_ENA` writer - The enable bit for SPI slave CMD9 interrupt."] +pub type SPI_SLV_CMD9_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMDA_INT_ENA` reader - The enable bit for SPI slave CMDA interrupt."] +pub type SPI_SLV_CMDA_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMDA_INT_ENA` writer - The enable bit for SPI slave CMDA interrupt."] +pub type SPI_SLV_CMDA_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_ENA` reader - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] +pub type SPI_SLV_RD_DMA_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_ENA` writer - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] +pub type SPI_SLV_RD_DMA_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_ENA` reader - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] +pub type SPI_SLV_WR_DMA_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_ENA` writer - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] +pub type SPI_SLV_WR_DMA_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_ENA` reader - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] +pub type SPI_SLV_RD_BUF_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_ENA` writer - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] +pub type SPI_SLV_RD_BUF_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_ENA` reader - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] +pub type SPI_SLV_WR_BUF_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_ENA` writer - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] +pub type SPI_SLV_WR_BUF_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_TRANS_DONE_INT_ENA` reader - The enable bit for SPI_TRANS_DONE_INT interrupt."] +pub type SPI_TRANS_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_TRANS_DONE_INT_ENA` writer - The enable bit for SPI_TRANS_DONE_INT interrupt."] +pub type SPI_TRANS_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_ENA` reader - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_ENA` writer - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_ENA` reader - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_ENA` writer - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_ENA` reader - The enable bit for SPI_SLV_CMD_ERR_INT interrupt."] +pub type SPI_SLV_CMD_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_ENA` writer - The enable bit for SPI_SLV_CMD_ERR_INT interrupt."] +pub type SPI_SLV_CMD_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA` reader - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA` writer - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA` reader - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA` writer - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP2_INT_ENA` reader - The enable bit for SPI_APP2_INT interrupt."] +pub type SPI_APP2_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_APP2_INT_ENA` writer - The enable bit for SPI_APP2_INT interrupt."] +pub type SPI_APP2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP1_INT_ENA` reader - The enable bit for SPI_APP1_INT interrupt."] +pub type SPI_APP1_INT_ENA_R = crate::BitReader; +#[doc = "Field `SPI_APP1_INT_ENA` writer - The enable bit for SPI_APP1_INT interrupt."] +pub type SPI_APP1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_dma_infifo_full_err_int_ena(&self) -> SPI_DMA_INFIFO_FULL_ERR_INT_ENA_R { + SPI_DMA_INFIFO_FULL_ERR_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_dma_outfifo_empty_err_int_ena(&self) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_R { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The enable bit for SPI slave Ex_QPI interrupt."] + #[inline(always)] + pub fn spi_slv_ex_qpi_int_ena(&self) -> SPI_SLV_EX_QPI_INT_ENA_R { + SPI_SLV_EX_QPI_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The enable bit for SPI slave En_QPI interrupt."] + #[inline(always)] + pub fn spi_slv_en_qpi_int_ena(&self) -> SPI_SLV_EN_QPI_INT_ENA_R { + SPI_SLV_EN_QPI_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The enable bit for SPI slave CMD7 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd7_int_ena(&self) -> SPI_SLV_CMD7_INT_ENA_R { + SPI_SLV_CMD7_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The enable bit for SPI slave CMD8 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd8_int_ena(&self) -> SPI_SLV_CMD8_INT_ENA_R { + SPI_SLV_CMD8_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The enable bit for SPI slave CMD9 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd9_int_ena(&self) -> SPI_SLV_CMD9_INT_ENA_R { + SPI_SLV_CMD9_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The enable bit for SPI slave CMDA interrupt."] + #[inline(always)] + pub fn spi_slv_cmda_int_ena(&self) -> SPI_SLV_CMDA_INT_ENA_R { + SPI_SLV_CMDA_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_rd_dma_done_int_ena(&self) -> SPI_SLV_RD_DMA_DONE_INT_ENA_R { + SPI_SLV_RD_DMA_DONE_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_wr_dma_done_int_ena(&self) -> SPI_SLV_WR_DMA_DONE_INT_ENA_R { + SPI_SLV_WR_DMA_DONE_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_rd_buf_done_int_ena(&self) -> SPI_SLV_RD_BUF_DONE_INT_ENA_R { + SPI_SLV_RD_BUF_DONE_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_wr_buf_done_int_ena(&self) -> SPI_SLV_WR_BUF_DONE_INT_ENA_R { + SPI_SLV_WR_BUF_DONE_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The enable bit for SPI_TRANS_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_trans_done_int_ena(&self) -> SPI_TRANS_DONE_INT_ENA_R { + SPI_TRANS_DONE_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_dma_seg_trans_done_int_ena(&self) -> SPI_DMA_SEG_TRANS_DONE_INT_ENA_R { + SPI_DMA_SEG_TRANS_DONE_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_slv_buf_addr_err_int_ena(&self) -> SPI_SLV_BUF_ADDR_ERR_INT_ENA_R { + SPI_SLV_BUF_ADDR_ERR_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The enable bit for SPI_SLV_CMD_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_slv_cmd_err_int_ena(&self) -> SPI_SLV_CMD_ERR_INT_ENA_R { + SPI_SLV_CMD_ERR_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mst_rx_afifo_wfull_err_int_ena(&self) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_R { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mst_tx_afifo_rempty_err_int_ena(&self) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_R { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The enable bit for SPI_APP2_INT interrupt."] + #[inline(always)] + pub fn spi_app2_int_ena(&self) -> SPI_APP2_INT_ENA_R { + SPI_APP2_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The enable bit for SPI_APP1_INT interrupt."] + #[inline(always)] + pub fn spi_app1_int_ena(&self) -> SPI_APP1_INT_ENA_R { + SPI_APP1_INT_ENA_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DMA_INT_ENA") + .field( + "spi_dma_infifo_full_err_int_ena", + &format_args!("{}", self.spi_dma_infifo_full_err_int_ena().bit()), + ) + .field( + "spi_dma_outfifo_empty_err_int_ena", + &format_args!("{}", self.spi_dma_outfifo_empty_err_int_ena().bit()), + ) + .field( + "spi_slv_ex_qpi_int_ena", + &format_args!("{}", self.spi_slv_ex_qpi_int_ena().bit()), + ) + .field( + "spi_slv_en_qpi_int_ena", + &format_args!("{}", self.spi_slv_en_qpi_int_ena().bit()), + ) + .field( + "spi_slv_cmd7_int_ena", + &format_args!("{}", self.spi_slv_cmd7_int_ena().bit()), + ) + .field( + "spi_slv_cmd8_int_ena", + &format_args!("{}", self.spi_slv_cmd8_int_ena().bit()), + ) + .field( + "spi_slv_cmd9_int_ena", + &format_args!("{}", self.spi_slv_cmd9_int_ena().bit()), + ) + .field( + "spi_slv_cmda_int_ena", + &format_args!("{}", self.spi_slv_cmda_int_ena().bit()), + ) + .field( + "spi_slv_rd_dma_done_int_ena", + &format_args!("{}", self.spi_slv_rd_dma_done_int_ena().bit()), + ) + .field( + "spi_slv_wr_dma_done_int_ena", + &format_args!("{}", self.spi_slv_wr_dma_done_int_ena().bit()), + ) + .field( + "spi_slv_rd_buf_done_int_ena", + &format_args!("{}", self.spi_slv_rd_buf_done_int_ena().bit()), + ) + .field( + "spi_slv_wr_buf_done_int_ena", + &format_args!("{}", self.spi_slv_wr_buf_done_int_ena().bit()), + ) + .field( + "spi_trans_done_int_ena", + &format_args!("{}", self.spi_trans_done_int_ena().bit()), + ) + .field( + "spi_dma_seg_trans_done_int_ena", + &format_args!("{}", self.spi_dma_seg_trans_done_int_ena().bit()), + ) + .field( + "spi_slv_buf_addr_err_int_ena", + &format_args!("{}", self.spi_slv_buf_addr_err_int_ena().bit()), + ) + .field( + "spi_slv_cmd_err_int_ena", + &format_args!("{}", self.spi_slv_cmd_err_int_ena().bit()), + ) + .field( + "spi_mst_rx_afifo_wfull_err_int_ena", + &format_args!("{}", self.spi_mst_rx_afifo_wfull_err_int_ena().bit()), + ) + .field( + "spi_mst_tx_afifo_rempty_err_int_ena", + &format_args!("{}", self.spi_mst_tx_afifo_rempty_err_int_ena().bit()), + ) + .field( + "spi_app2_int_ena", + &format_args!("{}", self.spi_app2_int_ena().bit()), + ) + .field( + "spi_app1_int_ena", + &format_args!("{}", self.spi_app1_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_infifo_full_err_int_ena( + &mut self, + ) -> SPI_DMA_INFIFO_FULL_ERR_INT_ENA_W { + SPI_DMA_INFIFO_FULL_ERR_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_outfifo_empty_err_int_ena( + &mut self, + ) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_W { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The enable bit for SPI slave Ex_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_ex_qpi_int_ena(&mut self) -> SPI_SLV_EX_QPI_INT_ENA_W { + SPI_SLV_EX_QPI_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The enable bit for SPI slave En_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_en_qpi_int_ena(&mut self) -> SPI_SLV_EN_QPI_INT_ENA_W { + SPI_SLV_EN_QPI_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The enable bit for SPI slave CMD7 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd7_int_ena(&mut self) -> SPI_SLV_CMD7_INT_ENA_W { + SPI_SLV_CMD7_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The enable bit for SPI slave CMD8 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd8_int_ena(&mut self) -> SPI_SLV_CMD8_INT_ENA_W { + SPI_SLV_CMD8_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The enable bit for SPI slave CMD9 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd9_int_ena(&mut self) -> SPI_SLV_CMD9_INT_ENA_W { + SPI_SLV_CMD9_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The enable bit for SPI slave CMDA interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmda_int_ena(&mut self) -> SPI_SLV_CMDA_INT_ENA_W { + SPI_SLV_CMDA_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_dma_done_int_ena( + &mut self, + ) -> SPI_SLV_RD_DMA_DONE_INT_ENA_W { + SPI_SLV_RD_DMA_DONE_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_dma_done_int_ena( + &mut self, + ) -> SPI_SLV_WR_DMA_DONE_INT_ENA_W { + SPI_SLV_WR_DMA_DONE_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_buf_done_int_ena( + &mut self, + ) -> SPI_SLV_RD_BUF_DONE_INT_ENA_W { + SPI_SLV_RD_BUF_DONE_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_buf_done_int_ena( + &mut self, + ) -> SPI_SLV_WR_BUF_DONE_INT_ENA_W { + SPI_SLV_WR_BUF_DONE_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - The enable bit for SPI_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_trans_done_int_ena(&mut self) -> SPI_TRANS_DONE_INT_ENA_W { + SPI_TRANS_DONE_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_seg_trans_done_int_ena( + &mut self, + ) -> SPI_DMA_SEG_TRANS_DONE_INT_ENA_W { + SPI_DMA_SEG_TRANS_DONE_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 15 - The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_buf_addr_err_int_ena( + &mut self, + ) -> SPI_SLV_BUF_ADDR_ERR_INT_ENA_W { + SPI_SLV_BUF_ADDR_ERR_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - The enable bit for SPI_SLV_CMD_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd_err_int_ena(&mut self) -> SPI_SLV_CMD_ERR_INT_ENA_W { + SPI_SLV_CMD_ERR_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_rx_afifo_wfull_err_int_ena( + &mut self, + ) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_W { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 18 - The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_tx_afifo_rempty_err_int_ena( + &mut self, + ) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_W { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_W::new(self, 18) + } + #[doc = "Bit 19 - The enable bit for SPI_APP2_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app2_int_ena(&mut self) -> SPI_APP2_INT_ENA_W { + SPI_APP2_INT_ENA_W::new(self, 19) + } + #[doc = "Bit 20 - The enable bit for SPI_APP1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app1_int_ena(&mut self) -> SPI_APP1_INT_ENA_W { + SPI_APP1_INT_ENA_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_INT_ENA_SPEC; +impl crate::RegisterSpec for SPI_DMA_INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_dma_int_ena::R`](R) reader structure"] +impl crate::Readable for SPI_DMA_INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_dma_int_ena::W`](W) writer structure"] +impl crate::Writable for SPI_DMA_INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DMA_INT_ENA to value 0"] +impl crate::Resettable for SPI_DMA_INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_dma_int_raw.rs b/esp32p4/src/spi3/spi_dma_int_raw.rs new file mode 100644 index 0000000000..a0b04f8776 --- /dev/null +++ b/esp32p4/src/spi3/spi_dma_int_raw.rs @@ -0,0 +1,447 @@ +#[doc = "Register `SPI_DMA_INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DMA_INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_RAW` reader - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_RAW` writer - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW` reader - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW` writer - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EX_QPI_INT_RAW` reader - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."] +pub type SPI_SLV_EX_QPI_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EX_QPI_INT_RAW` writer - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."] +pub type SPI_SLV_EX_QPI_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EN_QPI_INT_RAW` reader - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."] +pub type SPI_SLV_EN_QPI_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EN_QPI_INT_RAW` writer - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."] +pub type SPI_SLV_EN_QPI_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD7_INT_RAW` reader - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD7_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD7_INT_RAW` writer - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD7_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD8_INT_RAW` reader - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD8_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD8_INT_RAW` writer - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD8_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD9_INT_RAW` reader - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD9_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD9_INT_RAW` writer - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."] +pub type SPI_SLV_CMD9_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMDA_INT_RAW` reader - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."] +pub type SPI_SLV_CMDA_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMDA_INT_RAW` writer - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."] +pub type SPI_SLV_CMDA_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_RAW` reader - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."] +pub type SPI_SLV_RD_DMA_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_RAW` writer - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."] +pub type SPI_SLV_RD_DMA_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_RAW` reader - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."] +pub type SPI_SLV_WR_DMA_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_RAW` writer - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."] +pub type SPI_SLV_WR_DMA_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_RAW` reader - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."] +pub type SPI_SLV_RD_BUF_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_RAW` writer - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."] +pub type SPI_SLV_RD_BUF_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_RAW` reader - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."] +pub type SPI_SLV_WR_BUF_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_RAW` writer - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."] +pub type SPI_SLV_WR_BUF_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_TRANS_DONE_INT_RAW` reader - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."] +pub type SPI_TRANS_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_TRANS_DONE_INT_RAW` writer - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."] +pub type SPI_TRANS_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_RAW` reader - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_RAW` writer - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_RAW` reader - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_RAW` writer - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_RAW` reader - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."] +pub type SPI_SLV_CMD_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_RAW` writer - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."] +pub type SPI_SLV_CMD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW` reader - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW` writer - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW` reader - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW` writer - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP2_INT_RAW` reader - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."] +pub type SPI_APP2_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_APP2_INT_RAW` writer - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."] +pub type SPI_APP2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP1_INT_RAW` reader - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."] +pub type SPI_APP1_INT_RAW_R = crate::BitReader; +#[doc = "Field `SPI_APP1_INT_RAW` writer - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."] +pub type SPI_APP1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."] + #[inline(always)] + pub fn spi_dma_infifo_full_err_int_raw(&self) -> SPI_DMA_INFIFO_FULL_ERR_INT_RAW_R { + SPI_DMA_INFIFO_FULL_ERR_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."] + #[inline(always)] + pub fn spi_dma_outfifo_empty_err_int_raw(&self) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_R { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_ex_qpi_int_raw(&self) -> SPI_SLV_EX_QPI_INT_RAW_R { + SPI_SLV_EX_QPI_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_en_qpi_int_raw(&self) -> SPI_SLV_EN_QPI_INT_RAW_R { + SPI_SLV_EN_QPI_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_cmd7_int_raw(&self) -> SPI_SLV_CMD7_INT_RAW_R { + SPI_SLV_CMD7_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_cmd8_int_raw(&self) -> SPI_SLV_CMD8_INT_RAW_R { + SPI_SLV_CMD8_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_cmd9_int_raw(&self) -> SPI_SLV_CMD9_INT_RAW_R { + SPI_SLV_CMD9_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_cmda_int_raw(&self) -> SPI_SLV_CMDA_INT_RAW_R { + SPI_SLV_CMDA_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_rd_dma_done_int_raw(&self) -> SPI_SLV_RD_DMA_DONE_INT_RAW_R { + SPI_SLV_RD_DMA_DONE_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_wr_dma_done_int_raw(&self) -> SPI_SLV_WR_DMA_DONE_INT_RAW_R { + SPI_SLV_WR_DMA_DONE_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_rd_buf_done_int_raw(&self) -> SPI_SLV_RD_BUF_DONE_INT_RAW_R { + SPI_SLV_RD_BUF_DONE_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."] + #[inline(always)] + pub fn spi_slv_wr_buf_done_int_raw(&self) -> SPI_SLV_WR_BUF_DONE_INT_RAW_R { + SPI_SLV_WR_BUF_DONE_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."] + #[inline(always)] + pub fn spi_trans_done_int_raw(&self) -> SPI_TRANS_DONE_INT_RAW_R { + SPI_TRANS_DONE_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."] + #[inline(always)] + pub fn spi_dma_seg_trans_done_int_raw(&self) -> SPI_DMA_SEG_TRANS_DONE_INT_RAW_R { + SPI_DMA_SEG_TRANS_DONE_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."] + #[inline(always)] + pub fn spi_slv_buf_addr_err_int_raw(&self) -> SPI_SLV_BUF_ADDR_ERR_INT_RAW_R { + SPI_SLV_BUF_ADDR_ERR_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."] + #[inline(always)] + pub fn spi_slv_cmd_err_int_raw(&self) -> SPI_SLV_CMD_ERR_INT_RAW_R { + SPI_SLV_CMD_ERR_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."] + #[inline(always)] + pub fn spi_mst_rx_afifo_wfull_err_int_raw(&self) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_R { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."] + #[inline(always)] + pub fn spi_mst_tx_afifo_rempty_err_int_raw(&self) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_R { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."] + #[inline(always)] + pub fn spi_app2_int_raw(&self) -> SPI_APP2_INT_RAW_R { + SPI_APP2_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."] + #[inline(always)] + pub fn spi_app1_int_raw(&self) -> SPI_APP1_INT_RAW_R { + SPI_APP1_INT_RAW_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DMA_INT_RAW") + .field( + "spi_dma_infifo_full_err_int_raw", + &format_args!("{}", self.spi_dma_infifo_full_err_int_raw().bit()), + ) + .field( + "spi_dma_outfifo_empty_err_int_raw", + &format_args!("{}", self.spi_dma_outfifo_empty_err_int_raw().bit()), + ) + .field( + "spi_slv_ex_qpi_int_raw", + &format_args!("{}", self.spi_slv_ex_qpi_int_raw().bit()), + ) + .field( + "spi_slv_en_qpi_int_raw", + &format_args!("{}", self.spi_slv_en_qpi_int_raw().bit()), + ) + .field( + "spi_slv_cmd7_int_raw", + &format_args!("{}", self.spi_slv_cmd7_int_raw().bit()), + ) + .field( + "spi_slv_cmd8_int_raw", + &format_args!("{}", self.spi_slv_cmd8_int_raw().bit()), + ) + .field( + "spi_slv_cmd9_int_raw", + &format_args!("{}", self.spi_slv_cmd9_int_raw().bit()), + ) + .field( + "spi_slv_cmda_int_raw", + &format_args!("{}", self.spi_slv_cmda_int_raw().bit()), + ) + .field( + "spi_slv_rd_dma_done_int_raw", + &format_args!("{}", self.spi_slv_rd_dma_done_int_raw().bit()), + ) + .field( + "spi_slv_wr_dma_done_int_raw", + &format_args!("{}", self.spi_slv_wr_dma_done_int_raw().bit()), + ) + .field( + "spi_slv_rd_buf_done_int_raw", + &format_args!("{}", self.spi_slv_rd_buf_done_int_raw().bit()), + ) + .field( + "spi_slv_wr_buf_done_int_raw", + &format_args!("{}", self.spi_slv_wr_buf_done_int_raw().bit()), + ) + .field( + "spi_trans_done_int_raw", + &format_args!("{}", self.spi_trans_done_int_raw().bit()), + ) + .field( + "spi_dma_seg_trans_done_int_raw", + &format_args!("{}", self.spi_dma_seg_trans_done_int_raw().bit()), + ) + .field( + "spi_slv_buf_addr_err_int_raw", + &format_args!("{}", self.spi_slv_buf_addr_err_int_raw().bit()), + ) + .field( + "spi_slv_cmd_err_int_raw", + &format_args!("{}", self.spi_slv_cmd_err_int_raw().bit()), + ) + .field( + "spi_mst_rx_afifo_wfull_err_int_raw", + &format_args!("{}", self.spi_mst_rx_afifo_wfull_err_int_raw().bit()), + ) + .field( + "spi_mst_tx_afifo_rempty_err_int_raw", + &format_args!("{}", self.spi_mst_tx_afifo_rempty_err_int_raw().bit()), + ) + .field( + "spi_app2_int_raw", + &format_args!("{}", self.spi_app2_int_raw().bit()), + ) + .field( + "spi_app1_int_raw", + &format_args!("{}", self.spi_app1_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_dma_infifo_full_err_int_raw( + &mut self, + ) -> SPI_DMA_INFIFO_FULL_ERR_INT_RAW_W { + SPI_DMA_INFIFO_FULL_ERR_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_dma_outfifo_empty_err_int_raw( + &mut self, + ) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_W { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_ex_qpi_int_raw(&mut self) -> SPI_SLV_EX_QPI_INT_RAW_W { + SPI_SLV_EX_QPI_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_en_qpi_int_raw(&mut self) -> SPI_SLV_EN_QPI_INT_RAW_W { + SPI_SLV_EN_QPI_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd7_int_raw(&mut self) -> SPI_SLV_CMD7_INT_RAW_W { + SPI_SLV_CMD7_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd8_int_raw(&mut self) -> SPI_SLV_CMD8_INT_RAW_W { + SPI_SLV_CMD8_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd9_int_raw(&mut self) -> SPI_SLV_CMD9_INT_RAW_W { + SPI_SLV_CMD9_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmda_int_raw(&mut self) -> SPI_SLV_CMDA_INT_RAW_W { + SPI_SLV_CMDA_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_dma_done_int_raw( + &mut self, + ) -> SPI_SLV_RD_DMA_DONE_INT_RAW_W { + SPI_SLV_RD_DMA_DONE_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_dma_done_int_raw( + &mut self, + ) -> SPI_SLV_WR_DMA_DONE_INT_RAW_W { + SPI_SLV_WR_DMA_DONE_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_buf_done_int_raw( + &mut self, + ) -> SPI_SLV_RD_BUF_DONE_INT_RAW_W { + SPI_SLV_RD_BUF_DONE_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_buf_done_int_raw( + &mut self, + ) -> SPI_SLV_WR_BUF_DONE_INT_RAW_W { + SPI_SLV_WR_BUF_DONE_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 12 - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others."] + #[inline(always)] + #[must_use] + pub fn spi_trans_done_int_raw(&mut self) -> SPI_TRANS_DONE_INT_RAW_W { + SPI_TRANS_DONE_INT_RAW_W::new(self, 12) + } + #[doc = "Bit 13 - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred."] + #[inline(always)] + #[must_use] + pub fn spi_dma_seg_trans_done_int_raw( + &mut self, + ) -> SPI_DMA_SEG_TRANS_DONE_INT_RAW_W { + SPI_DMA_SEG_TRANS_DONE_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 15 - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_buf_addr_err_int_raw( + &mut self, + ) -> SPI_SLV_BUF_ADDR_ERR_INT_RAW_W { + SPI_SLV_BUF_ADDR_ERR_INT_RAW_W::new(self, 15) + } + #[doc = "Bit 16 - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd_err_int_raw(&mut self) -> SPI_SLV_CMD_ERR_INT_RAW_W { + SPI_SLV_CMD_ERR_INT_RAW_W::new(self, 16) + } + #[doc = "Bit 17 - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mst_rx_afifo_wfull_err_int_raw( + &mut self, + ) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_W { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_W::new(self, 17) + } + #[doc = "Bit 18 - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others."] + #[inline(always)] + #[must_use] + pub fn spi_mst_tx_afifo_rempty_err_int_raw( + &mut self, + ) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_W { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_W::new(self, 18) + } + #[doc = "Bit 19 - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software."] + #[inline(always)] + #[must_use] + pub fn spi_app2_int_raw(&mut self) -> SPI_APP2_INT_RAW_W { + SPI_APP2_INT_RAW_W::new(self, 19) + } + #[doc = "Bit 20 - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software."] + #[inline(always)] + #[must_use] + pub fn spi_app1_int_raw(&mut self) -> SPI_APP1_INT_RAW_W { + SPI_APP1_INT_RAW_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_INT_RAW_SPEC; +impl crate::RegisterSpec for SPI_DMA_INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_dma_int_raw::R`](R) reader structure"] +impl crate::Readable for SPI_DMA_INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_dma_int_raw::W`](W) writer structure"] +impl crate::Writable for SPI_DMA_INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DMA_INT_RAW to value 0"] +impl crate::Resettable for SPI_DMA_INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_dma_int_set.rs b/esp32p4/src/spi3/spi_dma_int_set.rs new file mode 100644 index 0000000000..0ff69d088f --- /dev/null +++ b/esp32p4/src/spi3/spi_dma_int_set.rs @@ -0,0 +1,214 @@ +#[doc = "Register `SPI_DMA_INT_SET` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_SET` writer - The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET` writer - The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EX_QPI_INT_SET` writer - The software set bit for SPI slave Ex_QPI interrupt."] +pub type SPI_SLV_EX_QPI_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_EN_QPI_INT_SET` writer - The software set bit for SPI slave En_QPI interrupt."] +pub type SPI_SLV_EN_QPI_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD7_INT_SET` writer - The software set bit for SPI slave CMD7 interrupt."] +pub type SPI_SLV_CMD7_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD8_INT_SET` writer - The software set bit for SPI slave CMD8 interrupt."] +pub type SPI_SLV_CMD8_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD9_INT_SET` writer - The software set bit for SPI slave CMD9 interrupt."] +pub type SPI_SLV_CMD9_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMDA_INT_SET` writer - The software set bit for SPI slave CMDA interrupt."] +pub type SPI_SLV_CMDA_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_SET` writer - The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] +pub type SPI_SLV_RD_DMA_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_SET` writer - The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] +pub type SPI_SLV_WR_DMA_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_SET` writer - The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] +pub type SPI_SLV_RD_BUF_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_SET` writer - The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] +pub type SPI_SLV_WR_BUF_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_TRANS_DONE_INT_SET` writer - The software set bit for SPI_TRANS_DONE_INT interrupt."] +pub type SPI_TRANS_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_SET` writer - The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_SET` writer - The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_SET` writer - The software set bit for SPI_SLV_CMD_ERR_INT interrupt."] +pub type SPI_SLV_CMD_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET` writer - The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET` writer - The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP2_INT_SET` writer - The software set bit for SPI_APP2_INT interrupt."] +pub type SPI_APP2_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_APP1_INT_SET` writer - The software set bit for SPI_APP1_INT interrupt."] +pub type SPI_APP1_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_infifo_full_err_int_set( + &mut self, + ) -> SPI_DMA_INFIFO_FULL_ERR_INT_SET_W { + SPI_DMA_INFIFO_FULL_ERR_INT_SET_W::new(self, 0) + } + #[doc = "Bit 1 - The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_outfifo_empty_err_int_set( + &mut self, + ) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_W { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_W::new(self, 1) + } + #[doc = "Bit 2 - The software set bit for SPI slave Ex_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_ex_qpi_int_set(&mut self) -> SPI_SLV_EX_QPI_INT_SET_W { + SPI_SLV_EX_QPI_INT_SET_W::new(self, 2) + } + #[doc = "Bit 3 - The software set bit for SPI slave En_QPI interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_en_qpi_int_set(&mut self) -> SPI_SLV_EN_QPI_INT_SET_W { + SPI_SLV_EN_QPI_INT_SET_W::new(self, 3) + } + #[doc = "Bit 4 - The software set bit for SPI slave CMD7 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd7_int_set(&mut self) -> SPI_SLV_CMD7_INT_SET_W { + SPI_SLV_CMD7_INT_SET_W::new(self, 4) + } + #[doc = "Bit 5 - The software set bit for SPI slave CMD8 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd8_int_set(&mut self) -> SPI_SLV_CMD8_INT_SET_W { + SPI_SLV_CMD8_INT_SET_W::new(self, 5) + } + #[doc = "Bit 6 - The software set bit for SPI slave CMD9 interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd9_int_set(&mut self) -> SPI_SLV_CMD9_INT_SET_W { + SPI_SLV_CMD9_INT_SET_W::new(self, 6) + } + #[doc = "Bit 7 - The software set bit for SPI slave CMDA interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmda_int_set(&mut self) -> SPI_SLV_CMDA_INT_SET_W { + SPI_SLV_CMDA_INT_SET_W::new(self, 7) + } + #[doc = "Bit 8 - The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_dma_done_int_set( + &mut self, + ) -> SPI_SLV_RD_DMA_DONE_INT_SET_W { + SPI_SLV_RD_DMA_DONE_INT_SET_W::new(self, 8) + } + #[doc = "Bit 9 - The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_dma_done_int_set( + &mut self, + ) -> SPI_SLV_WR_DMA_DONE_INT_SET_W { + SPI_SLV_WR_DMA_DONE_INT_SET_W::new(self, 9) + } + #[doc = "Bit 10 - The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_rd_buf_done_int_set( + &mut self, + ) -> SPI_SLV_RD_BUF_DONE_INT_SET_W { + SPI_SLV_RD_BUF_DONE_INT_SET_W::new(self, 10) + } + #[doc = "Bit 11 - The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_wr_buf_done_int_set( + &mut self, + ) -> SPI_SLV_WR_BUF_DONE_INT_SET_W { + SPI_SLV_WR_BUF_DONE_INT_SET_W::new(self, 11) + } + #[doc = "Bit 12 - The software set bit for SPI_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_trans_done_int_set(&mut self) -> SPI_TRANS_DONE_INT_SET_W { + SPI_TRANS_DONE_INT_SET_W::new(self, 12) + } + #[doc = "Bit 13 - The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_dma_seg_trans_done_int_set( + &mut self, + ) -> SPI_DMA_SEG_TRANS_DONE_INT_SET_W { + SPI_DMA_SEG_TRANS_DONE_INT_SET_W::new(self, 13) + } + #[doc = "Bit 15 - The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_buf_addr_err_int_set( + &mut self, + ) -> SPI_SLV_BUF_ADDR_ERR_INT_SET_W { + SPI_SLV_BUF_ADDR_ERR_INT_SET_W::new(self, 15) + } + #[doc = "Bit 16 - The software set bit for SPI_SLV_CMD_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_slv_cmd_err_int_set(&mut self) -> SPI_SLV_CMD_ERR_INT_SET_W { + SPI_SLV_CMD_ERR_INT_SET_W::new(self, 16) + } + #[doc = "Bit 17 - The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_rx_afifo_wfull_err_int_set( + &mut self, + ) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_W { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_W::new(self, 17) + } + #[doc = "Bit 18 - The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_mst_tx_afifo_rempty_err_int_set( + &mut self, + ) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_W { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_W::new(self, 18) + } + #[doc = "Bit 19 - The software set bit for SPI_APP2_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app2_int_set(&mut self) -> SPI_APP2_INT_SET_W { + SPI_APP2_INT_SET_W::new(self, 19) + } + #[doc = "Bit 20 - The software set bit for SPI_APP1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn spi_app1_int_set(&mut self) -> SPI_APP1_INT_SET_W { + SPI_APP1_INT_SET_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI interrupt software set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dma_int_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_INT_SET_SPEC; +impl crate::RegisterSpec for SPI_DMA_INT_SET_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`spi_dma_int_set::W`](W) writer structure"] +impl crate::Writable for SPI_DMA_INT_SET_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DMA_INT_SET to value 0"] +impl crate::Resettable for SPI_DMA_INT_SET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_dma_int_st.rs b/esp32p4/src/spi3/spi_dma_int_st.rs new file mode 100644 index 0000000000..bc80aa3bfb --- /dev/null +++ b/esp32p4/src/spi3/spi_dma_int_st.rs @@ -0,0 +1,248 @@ +#[doc = "Register `SPI_DMA_INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `SPI_DMA_INFIFO_FULL_ERR_INT_ST` reader - The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] +pub type SPI_DMA_INFIFO_FULL_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST` reader - The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] +pub type SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EX_QPI_INT_ST` reader - The status bit for SPI slave Ex_QPI interrupt."] +pub type SPI_SLV_EX_QPI_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_EN_QPI_INT_ST` reader - The status bit for SPI slave En_QPI interrupt."] +pub type SPI_SLV_EN_QPI_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD7_INT_ST` reader - The status bit for SPI slave CMD7 interrupt."] +pub type SPI_SLV_CMD7_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD8_INT_ST` reader - The status bit for SPI slave CMD8 interrupt."] +pub type SPI_SLV_CMD8_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD9_INT_ST` reader - The status bit for SPI slave CMD9 interrupt."] +pub type SPI_SLV_CMD9_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMDA_INT_ST` reader - The status bit for SPI slave CMDA interrupt."] +pub type SPI_SLV_CMDA_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_DMA_DONE_INT_ST` reader - The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] +pub type SPI_SLV_RD_DMA_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_DMA_DONE_INT_ST` reader - The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] +pub type SPI_SLV_WR_DMA_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RD_BUF_DONE_INT_ST` reader - The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] +pub type SPI_SLV_RD_BUF_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WR_BUF_DONE_INT_ST` reader - The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] +pub type SPI_SLV_WR_BUF_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_TRANS_DONE_INT_ST` reader - The status bit for SPI_TRANS_DONE_INT interrupt."] +pub type SPI_TRANS_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_DMA_SEG_TRANS_DONE_INT_ST` reader - The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] +pub type SPI_DMA_SEG_TRANS_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_BUF_ADDR_ERR_INT_ST` reader - The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] +pub type SPI_SLV_BUF_ADDR_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_SLV_CMD_ERR_INT_ST` reader - The status bit for SPI_SLV_CMD_ERR_INT interrupt."] +pub type SPI_SLV_CMD_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST` reader - The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] +pub type SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST` reader - The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] +pub type SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_APP2_INT_ST` reader - The status bit for SPI_APP2_INT interrupt."] +pub type SPI_APP2_INT_ST_R = crate::BitReader; +#[doc = "Field `SPI_APP1_INT_ST` reader - The status bit for SPI_APP1_INT interrupt."] +pub type SPI_APP1_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_dma_infifo_full_err_int_st(&self) -> SPI_DMA_INFIFO_FULL_ERR_INT_ST_R { + SPI_DMA_INFIFO_FULL_ERR_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_dma_outfifo_empty_err_int_st(&self) -> SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_R { + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The status bit for SPI slave Ex_QPI interrupt."] + #[inline(always)] + pub fn spi_slv_ex_qpi_int_st(&self) -> SPI_SLV_EX_QPI_INT_ST_R { + SPI_SLV_EX_QPI_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The status bit for SPI slave En_QPI interrupt."] + #[inline(always)] + pub fn spi_slv_en_qpi_int_st(&self) -> SPI_SLV_EN_QPI_INT_ST_R { + SPI_SLV_EN_QPI_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The status bit for SPI slave CMD7 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd7_int_st(&self) -> SPI_SLV_CMD7_INT_ST_R { + SPI_SLV_CMD7_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The status bit for SPI slave CMD8 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd8_int_st(&self) -> SPI_SLV_CMD8_INT_ST_R { + SPI_SLV_CMD8_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The status bit for SPI slave CMD9 interrupt."] + #[inline(always)] + pub fn spi_slv_cmd9_int_st(&self) -> SPI_SLV_CMD9_INT_ST_R { + SPI_SLV_CMD9_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The status bit for SPI slave CMDA interrupt."] + #[inline(always)] + pub fn spi_slv_cmda_int_st(&self) -> SPI_SLV_CMDA_INT_ST_R { + SPI_SLV_CMDA_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_rd_dma_done_int_st(&self) -> SPI_SLV_RD_DMA_DONE_INT_ST_R { + SPI_SLV_RD_DMA_DONE_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_wr_dma_done_int_st(&self) -> SPI_SLV_WR_DMA_DONE_INT_ST_R { + SPI_SLV_WR_DMA_DONE_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_rd_buf_done_int_st(&self) -> SPI_SLV_RD_BUF_DONE_INT_ST_R { + SPI_SLV_RD_BUF_DONE_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_slv_wr_buf_done_int_st(&self) -> SPI_SLV_WR_BUF_DONE_INT_ST_R { + SPI_SLV_WR_BUF_DONE_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The status bit for SPI_TRANS_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_trans_done_int_st(&self) -> SPI_TRANS_DONE_INT_ST_R { + SPI_TRANS_DONE_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."] + #[inline(always)] + pub fn spi_dma_seg_trans_done_int_st(&self) -> SPI_DMA_SEG_TRANS_DONE_INT_ST_R { + SPI_DMA_SEG_TRANS_DONE_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_slv_buf_addr_err_int_st(&self) -> SPI_SLV_BUF_ADDR_ERR_INT_ST_R { + SPI_SLV_BUF_ADDR_ERR_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - The status bit for SPI_SLV_CMD_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_slv_cmd_err_int_st(&self) -> SPI_SLV_CMD_ERR_INT_ST_R { + SPI_SLV_CMD_ERR_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mst_rx_afifo_wfull_err_int_st(&self) -> SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_R { + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."] + #[inline(always)] + pub fn spi_mst_tx_afifo_rempty_err_int_st(&self) -> SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_R { + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - The status bit for SPI_APP2_INT interrupt."] + #[inline(always)] + pub fn spi_app2_int_st(&self) -> SPI_APP2_INT_ST_R { + SPI_APP2_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - The status bit for SPI_APP1_INT interrupt."] + #[inline(always)] + pub fn spi_app1_int_st(&self) -> SPI_APP1_INT_ST_R { + SPI_APP1_INT_ST_R::new(((self.bits >> 20) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DMA_INT_ST") + .field( + "spi_dma_infifo_full_err_int_st", + &format_args!("{}", self.spi_dma_infifo_full_err_int_st().bit()), + ) + .field( + "spi_dma_outfifo_empty_err_int_st", + &format_args!("{}", self.spi_dma_outfifo_empty_err_int_st().bit()), + ) + .field( + "spi_slv_ex_qpi_int_st", + &format_args!("{}", self.spi_slv_ex_qpi_int_st().bit()), + ) + .field( + "spi_slv_en_qpi_int_st", + &format_args!("{}", self.spi_slv_en_qpi_int_st().bit()), + ) + .field( + "spi_slv_cmd7_int_st", + &format_args!("{}", self.spi_slv_cmd7_int_st().bit()), + ) + .field( + "spi_slv_cmd8_int_st", + &format_args!("{}", self.spi_slv_cmd8_int_st().bit()), + ) + .field( + "spi_slv_cmd9_int_st", + &format_args!("{}", self.spi_slv_cmd9_int_st().bit()), + ) + .field( + "spi_slv_cmda_int_st", + &format_args!("{}", self.spi_slv_cmda_int_st().bit()), + ) + .field( + "spi_slv_rd_dma_done_int_st", + &format_args!("{}", self.spi_slv_rd_dma_done_int_st().bit()), + ) + .field( + "spi_slv_wr_dma_done_int_st", + &format_args!("{}", self.spi_slv_wr_dma_done_int_st().bit()), + ) + .field( + "spi_slv_rd_buf_done_int_st", + &format_args!("{}", self.spi_slv_rd_buf_done_int_st().bit()), + ) + .field( + "spi_slv_wr_buf_done_int_st", + &format_args!("{}", self.spi_slv_wr_buf_done_int_st().bit()), + ) + .field( + "spi_trans_done_int_st", + &format_args!("{}", self.spi_trans_done_int_st().bit()), + ) + .field( + "spi_dma_seg_trans_done_int_st", + &format_args!("{}", self.spi_dma_seg_trans_done_int_st().bit()), + ) + .field( + "spi_slv_buf_addr_err_int_st", + &format_args!("{}", self.spi_slv_buf_addr_err_int_st().bit()), + ) + .field( + "spi_slv_cmd_err_int_st", + &format_args!("{}", self.spi_slv_cmd_err_int_st().bit()), + ) + .field( + "spi_mst_rx_afifo_wfull_err_int_st", + &format_args!("{}", self.spi_mst_rx_afifo_wfull_err_int_st().bit()), + ) + .field( + "spi_mst_tx_afifo_rempty_err_int_st", + &format_args!("{}", self.spi_mst_tx_afifo_rempty_err_int_st().bit()), + ) + .field( + "spi_app2_int_st", + &format_args!("{}", self.spi_app2_int_st().bit()), + ) + .field( + "spi_app1_int_st", + &format_args!("{}", self.spi_app1_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "SPI interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dma_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DMA_INT_ST_SPEC; +impl crate::RegisterSpec for SPI_DMA_INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_dma_int_st::R`](R) reader structure"] +impl crate::Readable for SPI_DMA_INT_ST_SPEC {} +#[doc = "`reset()` method sets SPI_DMA_INT_ST to value 0"] +impl crate::Resettable for SPI_DMA_INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_dout_mode.rs b/esp32p4/src/spi3/spi_dout_mode.rs new file mode 100644 index 0000000000..072788eacc --- /dev/null +++ b/esp32p4/src/spi3/spi_dout_mode.rs @@ -0,0 +1,123 @@ +#[doc = "Register `SPI_DOUT_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_DOUT_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DOUT0_MODE` reader - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT0_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT0_MODE` writer - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT0_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DOUT1_MODE` reader - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT1_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT1_MODE` writer - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT1_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DOUT2_MODE` reader - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT2_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT2_MODE` writer - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT2_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_DOUT3_MODE` reader - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT3_MODE_R = crate::BitReader; +#[doc = "Field `SPI_DOUT3_MODE` writer - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] +pub type SPI_DOUT3_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout0_mode(&self) -> SPI_DOUT0_MODE_R { + SPI_DOUT0_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout1_mode(&self) -> SPI_DOUT1_MODE_R { + SPI_DOUT1_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout2_mode(&self) -> SPI_DOUT2_MODE_R { + SPI_DOUT2_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_dout3_mode(&self) -> SPI_DOUT3_MODE_R { + SPI_DOUT3_MODE_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_DOUT_MODE") + .field( + "spi_dout0_mode", + &format_args!("{}", self.spi_dout0_mode().bit()), + ) + .field( + "spi_dout1_mode", + &format_args!("{}", self.spi_dout1_mode().bit()), + ) + .field( + "spi_dout2_mode", + &format_args!("{}", self.spi_dout2_mode().bit()), + ) + .field( + "spi_dout3_mode", + &format_args!("{}", self.spi_dout3_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout0_mode(&mut self) -> SPI_DOUT0_MODE_W { + SPI_DOUT0_MODE_W::new(self, 0) + } + #[doc = "Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout1_mode(&mut self) -> SPI_DOUT1_MODE_W { + SPI_DOUT1_MODE_W::new(self, 1) + } + #[doc = "Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout2_mode(&mut self) -> SPI_DOUT2_MODE_W { + SPI_DOUT2_MODE_W::new(self, 2) + } + #[doc = "Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_dout3_mode(&mut self) -> SPI_DOUT3_MODE_W { + SPI_DOUT3_MODE_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI output delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_dout_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_dout_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_DOUT_MODE_SPEC; +impl crate::RegisterSpec for SPI_DOUT_MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_dout_mode::R`](R) reader structure"] +impl crate::Readable for SPI_DOUT_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_dout_mode::W`](W) writer structure"] +impl crate::Writable for SPI_DOUT_MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_DOUT_MODE to value 0"] +impl crate::Resettable for SPI_DOUT_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_misc.rs b/esp32p4/src/spi3/spi_misc.rs new file mode 100644 index 0000000000..252ce9af6a --- /dev/null +++ b/esp32p4/src/spi3/spi_misc.rs @@ -0,0 +1,206 @@ +#[doc = "Register `SPI_MISC` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MISC` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_CS0_DIS` reader - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."] +pub type SPI_CS0_DIS_R = crate::BitReader; +#[doc = "Field `SPI_CS0_DIS` writer - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."] +pub type SPI_CS0_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS1_DIS` reader - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."] +pub type SPI_CS1_DIS_R = crate::BitReader; +#[doc = "Field `SPI_CS1_DIS` writer - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."] +pub type SPI_CS1_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS2_DIS` reader - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."] +pub type SPI_CS2_DIS_R = crate::BitReader; +#[doc = "Field `SPI_CS2_DIS` writer - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."] +pub type SPI_CS2_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CK_DIS` reader - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."] +pub type SPI_CK_DIS_R = crate::BitReader; +#[doc = "Field `SPI_CK_DIS` writer - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."] +pub type SPI_CK_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MASTER_CS_POL` reader - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."] +pub type SPI_MASTER_CS_POL_R = crate::FieldReader; +#[doc = "Field `SPI_MASTER_CS_POL` writer - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."] +pub type SPI_MASTER_CS_POL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SPI_SLAVE_CS_POL` reader - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."] +pub type SPI_SLAVE_CS_POL_R = crate::BitReader; +#[doc = "Field `SPI_SLAVE_CS_POL` writer - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."] +pub type SPI_SLAVE_CS_POL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CK_IDLE_EDGE` reader - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."] +pub type SPI_CK_IDLE_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_CK_IDLE_EDGE` writer - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."] +pub type SPI_CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS_KEEP_ACTIVE` reader - spi cs line keep low when the bit is set. Can be configured in CONF state."] +pub type SPI_CS_KEEP_ACTIVE_R = crate::BitReader; +#[doc = "Field `SPI_CS_KEEP_ACTIVE` writer - spi cs line keep low when the bit is set. Can be configured in CONF state."] +pub type SPI_CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_QUAD_DIN_PIN_SWAP` reader - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."] +pub type SPI_QUAD_DIN_PIN_SWAP_R = crate::BitReader; +#[doc = "Field `SPI_QUAD_DIN_PIN_SWAP` writer - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."] +pub type SPI_QUAD_DIN_PIN_SWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs0_dis(&self) -> SPI_CS0_DIS_R { + SPI_CS0_DIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs1_dis(&self) -> SPI_CS1_DIS_R { + SPI_CS1_DIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs2_dis(&self) -> SPI_CS2_DIS_R { + SPI_CS2_DIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_ck_dis(&self) -> SPI_CK_DIS_R { + SPI_CK_DIS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:9 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_master_cs_pol(&self) -> SPI_MASTER_CS_POL_R { + SPI_MASTER_CS_POL_R::new(((self.bits >> 7) & 7) as u8) + } + #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_slave_cs_pol(&self) -> SPI_SLAVE_CS_POL_R { + SPI_SLAVE_CS_POL_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_ck_idle_edge(&self) -> SPI_CK_IDLE_EDGE_R { + SPI_CK_IDLE_EDGE_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs_keep_active(&self) -> SPI_CS_KEEP_ACTIVE_R { + SPI_CS_KEEP_ACTIVE_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_quad_din_pin_swap(&self) -> SPI_QUAD_DIN_PIN_SWAP_R { + SPI_QUAD_DIN_PIN_SWAP_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MISC") + .field("spi_cs0_dis", &format_args!("{}", self.spi_cs0_dis().bit())) + .field("spi_cs1_dis", &format_args!("{}", self.spi_cs1_dis().bit())) + .field("spi_cs2_dis", &format_args!("{}", self.spi_cs2_dis().bit())) + .field("spi_ck_dis", &format_args!("{}", self.spi_ck_dis().bit())) + .field( + "spi_master_cs_pol", + &format_args!("{}", self.spi_master_cs_pol().bits()), + ) + .field( + "spi_slave_cs_pol", + &format_args!("{}", self.spi_slave_cs_pol().bit()), + ) + .field( + "spi_ck_idle_edge", + &format_args!("{}", self.spi_ck_idle_edge().bit()), + ) + .field( + "spi_cs_keep_active", + &format_args!("{}", self.spi_cs_keep_active().bit()), + ) + .field( + "spi_quad_din_pin_swap", + &format_args!("{}", self.spi_quad_din_pin_swap().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs0_dis(&mut self) -> SPI_CS0_DIS_W { + SPI_CS0_DIS_W::new(self, 0) + } + #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs1_dis(&mut self) -> SPI_CS1_DIS_W { + SPI_CS1_DIS_W::new(self, 1) + } + #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs2_dis(&mut self) -> SPI_CS2_DIS_W { + SPI_CS2_DIS_W::new(self, 2) + } + #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_ck_dis(&mut self) -> SPI_CK_DIS_W { + SPI_CK_DIS_W::new(self, 6) + } + #[doc = "Bits 7:9 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_master_cs_pol(&mut self) -> SPI_MASTER_CS_POL_W { + SPI_MASTER_CS_POL_W::new(self, 7) + } + #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_slave_cs_pol(&mut self) -> SPI_SLAVE_CS_POL_W { + SPI_SLAVE_CS_POL_W::new(self, 23) + } + #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_ck_idle_edge(&mut self) -> SPI_CK_IDLE_EDGE_W { + SPI_CK_IDLE_EDGE_W::new(self, 29) + } + #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs_keep_active(&mut self) -> SPI_CS_KEEP_ACTIVE_W { + SPI_CS_KEEP_ACTIVE_W::new(self, 30) + } + #[doc = "Bit 31 - 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_quad_din_pin_swap(&mut self) -> SPI_QUAD_DIN_PIN_SWAP_W { + SPI_QUAD_DIN_PIN_SWAP_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI misc register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_misc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_misc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MISC_SPEC; +impl crate::RegisterSpec for SPI_MISC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_misc::R`](R) reader structure"] +impl crate::Readable for SPI_MISC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_misc::W`](W) writer structure"] +impl crate::Writable for SPI_MISC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MISC to value 0x06"] +impl crate::Resettable for SPI_MISC_SPEC { + const RESET_VALUE: Self::Ux = 0x06; +} diff --git a/esp32p4/src/spi3/spi_ms_dlen.rs b/esp32p4/src/spi3/spi_ms_dlen.rs new file mode 100644 index 0000000000..e02bcd5556 --- /dev/null +++ b/esp32p4/src/spi3/spi_ms_dlen.rs @@ -0,0 +1,66 @@ +#[doc = "Register `SPI_MS_DLEN` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_MS_DLEN` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_MS_DATA_BITLEN` reader - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_MS_DATA_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_MS_DATA_BITLEN` writer - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_MS_DATA_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +impl R { + #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + pub fn spi_ms_data_bitlen(&self) -> SPI_MS_DATA_BITLEN_R { + SPI_MS_DATA_BITLEN_R::new(self.bits & 0x0003_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_MS_DLEN") + .field( + "spi_ms_data_bitlen", + &format_args!("{}", self.spi_ms_data_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_ms_data_bitlen(&mut self) -> SPI_MS_DATA_BITLEN_W { + SPI_MS_DATA_BITLEN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI data bit length control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_ms_dlen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_ms_dlen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_MS_DLEN_SPEC; +impl crate::RegisterSpec for SPI_MS_DLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_ms_dlen::R`](R) reader structure"] +impl crate::Readable for SPI_MS_DLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_ms_dlen::W`](W) writer structure"] +impl crate::Writable for SPI_MS_DLEN_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_MS_DLEN to value 0"] +impl crate::Resettable for SPI_MS_DLEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_slave.rs b/esp32p4/src/spi3/spi_slave.rs new file mode 100644 index 0000000000..293a2f86a8 --- /dev/null +++ b/esp32p4/src/spi3/spi_slave.rs @@ -0,0 +1,234 @@ +#[doc = "Register `SPI_SLAVE` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SLAVE` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_CLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."] +pub type SPI_CLK_MODE_R = crate::FieldReader; +#[doc = "Field `SPI_CLK_MODE` writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."] +pub type SPI_CLK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPI_CLK_MODE_13` reader - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."] +pub type SPI_CLK_MODE_13_R = crate::BitReader; +#[doc = "Field `SPI_CLK_MODE_13` writer - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."] +pub type SPI_CLK_MODE_13_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_RSCK_DATA_OUT` reader - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"] +pub type SPI_RSCK_DATA_OUT_R = crate::BitReader; +#[doc = "Field `SPI_RSCK_DATA_OUT` writer - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"] +pub type SPI_RSCK_DATA_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RDDMA_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"] +pub type SPI_SLV_RDDMA_BITLEN_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RDDMA_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"] +pub type SPI_SLV_RDDMA_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WRDMA_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"] +pub type SPI_SLV_WRDMA_BITLEN_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WRDMA_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"] +pub type SPI_SLV_WRDMA_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_RDBUF_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"] +pub type SPI_SLV_RDBUF_BITLEN_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_RDBUF_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"] +pub type SPI_SLV_RDBUF_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_WRBUF_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"] +pub type SPI_SLV_WRBUF_BITLEN_EN_R = crate::BitReader; +#[doc = "Field `SPI_SLV_WRBUF_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"] +pub type SPI_SLV_WRBUF_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SLV_LAST_BYTE_STRB` reader - Represents the effective bit of the last received data byte in SPI slave FD and HD mode."] +pub type SPI_SLV_LAST_BYTE_STRB_R = crate::FieldReader; +#[doc = "Field `MODE` reader - Set SPI work mode. 1: slave mode 0: master mode."] +pub type MODE_R = crate::BitReader; +#[doc = "Field `MODE` writer - Set SPI work mode. 1: slave mode 0: master mode."] +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SOFT_RESET` writer - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."] +pub type SPI_SOFT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_MST_FD_WAIT_DMA_TX_DATA` reader - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."] +pub type SPI_MST_FD_WAIT_DMA_TX_DATA_R = crate::BitReader; +#[doc = "Field `SPI_MST_FD_WAIT_DMA_TX_DATA` writer - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."] +pub type SPI_MST_FD_WAIT_DMA_TX_DATA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_clk_mode(&self) -> SPI_CLK_MODE_R { + SPI_CLK_MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."] + #[inline(always)] + pub fn spi_clk_mode_13(&self) -> SPI_CLK_MODE_13_R { + SPI_CLK_MODE_13_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"] + #[inline(always)] + pub fn spi_rsck_data_out(&self) -> SPI_RSCK_DATA_OUT_R { + SPI_RSCK_DATA_OUT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"] + #[inline(always)] + pub fn spi_slv_rddma_bitlen_en(&self) -> SPI_SLV_RDDMA_BITLEN_EN_R { + SPI_SLV_RDDMA_BITLEN_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"] + #[inline(always)] + pub fn spi_slv_wrdma_bitlen_en(&self) -> SPI_SLV_WRDMA_BITLEN_EN_R { + SPI_SLV_WRDMA_BITLEN_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"] + #[inline(always)] + pub fn spi_slv_rdbuf_bitlen_en(&self) -> SPI_SLV_RDBUF_BITLEN_EN_R { + SPI_SLV_RDBUF_BITLEN_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"] + #[inline(always)] + pub fn spi_slv_wrbuf_bitlen_en(&self) -> SPI_SLV_WRBUF_BITLEN_EN_R { + SPI_SLV_WRBUF_BITLEN_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:19 - Represents the effective bit of the last received data byte in SPI slave FD and HD mode."] + #[inline(always)] + pub fn spi_slv_last_byte_strb(&self) -> SPI_SLV_LAST_BYTE_STRB_R { + SPI_SLV_LAST_BYTE_STRB_R::new(((self.bits >> 12) & 0xff) as u8) + } + #[doc = "Bit 26 - Set SPI work mode. 1: slave mode 0: master mode."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 29 - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."] + #[inline(always)] + pub fn spi_mst_fd_wait_dma_tx_data(&self) -> SPI_MST_FD_WAIT_DMA_TX_DATA_R { + SPI_MST_FD_WAIT_DMA_TX_DATA_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SLAVE") + .field( + "spi_clk_mode", + &format_args!("{}", self.spi_clk_mode().bits()), + ) + .field( + "spi_clk_mode_13", + &format_args!("{}", self.spi_clk_mode_13().bit()), + ) + .field( + "spi_rsck_data_out", + &format_args!("{}", self.spi_rsck_data_out().bit()), + ) + .field( + "spi_slv_rddma_bitlen_en", + &format_args!("{}", self.spi_slv_rddma_bitlen_en().bit()), + ) + .field( + "spi_slv_wrdma_bitlen_en", + &format_args!("{}", self.spi_slv_wrdma_bitlen_en().bit()), + ) + .field( + "spi_slv_rdbuf_bitlen_en", + &format_args!("{}", self.spi_slv_rdbuf_bitlen_en().bit()), + ) + .field( + "spi_slv_wrbuf_bitlen_en", + &format_args!("{}", self.spi_slv_wrbuf_bitlen_en().bit()), + ) + .field( + "spi_slv_last_byte_strb", + &format_args!("{}", self.spi_slv_last_byte_strb().bits()), + ) + .field("mode", &format_args!("{}", self.mode().bit())) + .field( + "spi_mst_fd_wait_dma_tx_data", + &format_args!("{}", self.spi_mst_fd_wait_dma_tx_data().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_clk_mode(&mut self) -> SPI_CLK_MODE_W { + SPI_CLK_MODE_W::new(self, 0) + } + #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."] + #[inline(always)] + #[must_use] + pub fn spi_clk_mode_13(&mut self) -> SPI_CLK_MODE_13_W { + SPI_CLK_MODE_13_W::new(self, 2) + } + #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"] + #[inline(always)] + #[must_use] + pub fn spi_rsck_data_out(&mut self) -> SPI_RSCK_DATA_OUT_W { + SPI_RSCK_DATA_OUT_W::new(self, 3) + } + #[doc = "Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"] + #[inline(always)] + #[must_use] + pub fn spi_slv_rddma_bitlen_en(&mut self) -> SPI_SLV_RDDMA_BITLEN_EN_W { + SPI_SLV_RDDMA_BITLEN_EN_W::new(self, 8) + } + #[doc = "Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"] + #[inline(always)] + #[must_use] + pub fn spi_slv_wrdma_bitlen_en(&mut self) -> SPI_SLV_WRDMA_BITLEN_EN_W { + SPI_SLV_WRDMA_BITLEN_EN_W::new(self, 9) + } + #[doc = "Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"] + #[inline(always)] + #[must_use] + pub fn spi_slv_rdbuf_bitlen_en(&mut self) -> SPI_SLV_RDBUF_BITLEN_EN_W { + SPI_SLV_RDBUF_BITLEN_EN_W::new(self, 10) + } + #[doc = "Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"] + #[inline(always)] + #[must_use] + pub fn spi_slv_wrbuf_bitlen_en(&mut self) -> SPI_SLV_WRBUF_BITLEN_EN_W { + SPI_SLV_WRBUF_BITLEN_EN_W::new(self, 11) + } + #[doc = "Bit 26 - Set SPI work mode. 1: slave mode 0: master mode."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 26) + } + #[doc = "Bit 27 - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_soft_reset(&mut self) -> SPI_SOFT_RESET_W { + SPI_SOFT_RESET_W::new(self, 27) + } + #[doc = "Bit 29 - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."] + #[inline(always)] + #[must_use] + pub fn spi_mst_fd_wait_dma_tx_data(&mut self) -> SPI_MST_FD_WAIT_DMA_TX_DATA_W { + SPI_MST_FD_WAIT_DMA_TX_DATA_W::new(self, 29) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI slave control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SLAVE_SPEC; +impl crate::RegisterSpec for SPI_SLAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_slave::R`](R) reader structure"] +impl crate::Readable for SPI_SLAVE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_slave::W`](W) writer structure"] +impl crate::Writable for SPI_SLAVE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SLAVE to value 0"] +impl crate::Resettable for SPI_SLAVE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_slave1.rs b/esp32p4/src/spi3/spi_slave1.rs new file mode 100644 index 0000000000..e1dda31559 --- /dev/null +++ b/esp32p4/src/spi3/spi_slave1.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SPI_SLAVE1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_SLAVE1` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_SLV_DATA_BITLEN` reader - The transferred data bit length in SPI slave FD and HD mode."] +pub type SPI_SLV_DATA_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_SLV_DATA_BITLEN` writer - The transferred data bit length in SPI slave FD and HD mode."] +pub type SPI_SLV_DATA_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `SPI_SLV_LAST_COMMAND` reader - In the slave mode it is the value of command."] +pub type SPI_SLV_LAST_COMMAND_R = crate::FieldReader; +#[doc = "Field `SPI_SLV_LAST_COMMAND` writer - In the slave mode it is the value of command."] +pub type SPI_SLV_LAST_COMMAND_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_SLV_LAST_ADDR` reader - In the slave mode it is the value of address."] +pub type SPI_SLV_LAST_ADDR_R = crate::FieldReader; +#[doc = "Field `SPI_SLV_LAST_ADDR` writer - In the slave mode it is the value of address."] +pub type SPI_SLV_LAST_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."] + #[inline(always)] + pub fn spi_slv_data_bitlen(&self) -> SPI_SLV_DATA_BITLEN_R { + SPI_SLV_DATA_BITLEN_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bits 18:25 - In the slave mode it is the value of command."] + #[inline(always)] + pub fn spi_slv_last_command(&self) -> SPI_SLV_LAST_COMMAND_R { + SPI_SLV_LAST_COMMAND_R::new(((self.bits >> 18) & 0xff) as u8) + } + #[doc = "Bits 26:31 - In the slave mode it is the value of address."] + #[inline(always)] + pub fn spi_slv_last_addr(&self) -> SPI_SLV_LAST_ADDR_R { + SPI_SLV_LAST_ADDR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_SLAVE1") + .field( + "spi_slv_data_bitlen", + &format_args!("{}", self.spi_slv_data_bitlen().bits()), + ) + .field( + "spi_slv_last_command", + &format_args!("{}", self.spi_slv_last_command().bits()), + ) + .field( + "spi_slv_last_addr", + &format_args!("{}", self.spi_slv_last_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."] + #[inline(always)] + #[must_use] + pub fn spi_slv_data_bitlen(&mut self) -> SPI_SLV_DATA_BITLEN_W { + SPI_SLV_DATA_BITLEN_W::new(self, 0) + } + #[doc = "Bits 18:25 - In the slave mode it is the value of command."] + #[inline(always)] + #[must_use] + pub fn spi_slv_last_command(&mut self) -> SPI_SLV_LAST_COMMAND_W { + SPI_SLV_LAST_COMMAND_W::new(self, 18) + } + #[doc = "Bits 26:31 - In the slave mode it is the value of address."] + #[inline(always)] + #[must_use] + pub fn spi_slv_last_addr(&mut self) -> SPI_SLV_LAST_ADDR_W { + SPI_SLV_LAST_ADDR_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI slave control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_slave1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_slave1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_SLAVE1_SPEC; +impl crate::RegisterSpec for SPI_SLAVE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_slave1::R`](R) reader structure"] +impl crate::Readable for SPI_SLAVE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_slave1::W`](W) writer structure"] +impl crate::Writable for SPI_SLAVE1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_SLAVE1 to value 0"] +impl crate::Resettable for SPI_SLAVE1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_user.rs b/esp32p4/src/spi3/spi_user.rs new file mode 100644 index 0000000000..e58761b122 --- /dev/null +++ b/esp32p4/src/spi3/spi_user.rs @@ -0,0 +1,380 @@ +#[doc = "Register `SPI_USER` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_USER` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_DOUTDIN` reader - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_DOUTDIN_R = crate::BitReader; +#[doc = "Field `SPI_DOUTDIN` writer - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_DOUTDIN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_QPI_MODE` reader - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."] +pub type SPI_QPI_MODE_R = crate::BitReader; +#[doc = "Field `SPI_QPI_MODE` writer - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."] +pub type SPI_QPI_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_TSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."] +pub type SPI_TSCK_I_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_TSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."] +pub type SPI_TSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS_HOLD` reader - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_CS_HOLD_R = crate::BitReader; +#[doc = "Field `SPI_CS_HOLD` writer - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS_SETUP` reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_CS_SETUP_R = crate::BitReader; +#[doc = "Field `SPI_CS_SETUP` writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_RSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."] +pub type SPI_RSCK_I_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_RSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."] +pub type SPI_RSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CK_OUT_EDGE` reader - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."] +pub type SPI_CK_OUT_EDGE_R = crate::BitReader; +#[doc = "Field `SPI_CK_OUT_EDGE` writer - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."] +pub type SPI_CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FWRITE_DUAL` reader - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."] +pub type SPI_FWRITE_DUAL_R = crate::BitReader; +#[doc = "Field `SPI_FWRITE_DUAL` writer - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."] +pub type SPI_FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_FWRITE_QUAD` reader - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."] +pub type SPI_FWRITE_QUAD_R = crate::BitReader; +#[doc = "Field `SPI_FWRITE_QUAD` writer - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."] +pub type SPI_FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_SIO` reader - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_SIO_R = crate::BitReader; +#[doc = "Field `SPI_SIO` writer - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_SIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_MISO_HIGHPART` reader - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_USR_MISO_HIGHPART_R = crate::BitReader; +#[doc = "Field `SPI_USR_MISO_HIGHPART` writer - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_USR_MISO_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_MOSI_HIGHPART` reader - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_USR_MOSI_HIGHPART_R = crate::BitReader; +#[doc = "Field `SPI_USR_MOSI_HIGHPART` writer - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] +pub type SPI_USR_MOSI_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_DUMMY_IDLE` reader - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."] +pub type SPI_USR_DUMMY_IDLE_R = crate::BitReader; +#[doc = "Field `SPI_USR_DUMMY_IDLE` writer - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."] +pub type SPI_USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_MOSI` reader - This bit enable the write-data phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_MOSI_R = crate::BitReader; +#[doc = "Field `SPI_USR_MOSI` writer - This bit enable the write-data phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_MISO` reader - This bit enable the read-data phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_MISO_R = crate::BitReader; +#[doc = "Field `SPI_USR_MISO` writer - This bit enable the read-data phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_DUMMY` reader - This bit enable the dummy phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_DUMMY_R = crate::BitReader; +#[doc = "Field `SPI_USR_DUMMY` writer - This bit enable the dummy phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_ADDR` reader - This bit enable the address phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_ADDR_R = crate::BitReader; +#[doc = "Field `SPI_USR_ADDR` writer - This bit enable the address phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_COMMAND` reader - This bit enable the command phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_COMMAND_R = crate::BitReader; +#[doc = "Field `SPI_USR_COMMAND` writer - This bit enable the command phase of an operation. Can be configured in CONF state."] +pub type SPI_USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_doutdin(&self) -> SPI_DOUTDIN_R { + SPI_DOUTDIN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_qpi_mode(&self) -> SPI_QPI_MODE_R { + SPI_QPI_MODE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."] + #[inline(always)] + pub fn spi_tsck_i_edge(&self) -> SPI_TSCK_I_EDGE_R { + SPI_TSCK_I_EDGE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs_hold(&self) -> SPI_CS_HOLD_R { + SPI_CS_HOLD_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs_setup(&self) -> SPI_CS_SETUP_R { + SPI_CS_SETUP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."] + #[inline(always)] + pub fn spi_rsck_i_edge(&self) -> SPI_RSCK_I_EDGE_R { + SPI_RSCK_I_EDGE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_ck_out_edge(&self) -> SPI_CK_OUT_EDGE_R { + SPI_CK_OUT_EDGE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fwrite_dual(&self) -> SPI_FWRITE_DUAL_R { + SPI_FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_fwrite_quad(&self) -> SPI_FWRITE_QUAD_R { + SPI_FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_sio(&self) -> SPI_SIO_R { + SPI_SIO_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_miso_highpart(&self) -> SPI_USR_MISO_HIGHPART_R { + SPI_USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_mosi_highpart(&self) -> SPI_USR_MOSI_HIGHPART_R { + SPI_USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_dummy_idle(&self) -> SPI_USR_DUMMY_IDLE_R { + SPI_USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_mosi(&self) -> SPI_USR_MOSI_R { + SPI_USR_MOSI_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_miso(&self) -> SPI_USR_MISO_R { + SPI_USR_MISO_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_dummy(&self) -> SPI_USR_DUMMY_R { + SPI_USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_addr(&self) -> SPI_USR_ADDR_R { + SPI_USR_ADDR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_command(&self) -> SPI_USR_COMMAND_R { + SPI_USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_USER") + .field("spi_doutdin", &format_args!("{}", self.spi_doutdin().bit())) + .field( + "spi_qpi_mode", + &format_args!("{}", self.spi_qpi_mode().bit()), + ) + .field( + "spi_tsck_i_edge", + &format_args!("{}", self.spi_tsck_i_edge().bit()), + ) + .field("spi_cs_hold", &format_args!("{}", self.spi_cs_hold().bit())) + .field( + "spi_cs_setup", + &format_args!("{}", self.spi_cs_setup().bit()), + ) + .field( + "spi_rsck_i_edge", + &format_args!("{}", self.spi_rsck_i_edge().bit()), + ) + .field( + "spi_ck_out_edge", + &format_args!("{}", self.spi_ck_out_edge().bit()), + ) + .field( + "spi_fwrite_dual", + &format_args!("{}", self.spi_fwrite_dual().bit()), + ) + .field( + "spi_fwrite_quad", + &format_args!("{}", self.spi_fwrite_quad().bit()), + ) + .field("spi_sio", &format_args!("{}", self.spi_sio().bit())) + .field( + "spi_usr_miso_highpart", + &format_args!("{}", self.spi_usr_miso_highpart().bit()), + ) + .field( + "spi_usr_mosi_highpart", + &format_args!("{}", self.spi_usr_mosi_highpart().bit()), + ) + .field( + "spi_usr_dummy_idle", + &format_args!("{}", self.spi_usr_dummy_idle().bit()), + ) + .field( + "spi_usr_mosi", + &format_args!("{}", self.spi_usr_mosi().bit()), + ) + .field( + "spi_usr_miso", + &format_args!("{}", self.spi_usr_miso().bit()), + ) + .field( + "spi_usr_dummy", + &format_args!("{}", self.spi_usr_dummy().bit()), + ) + .field( + "spi_usr_addr", + &format_args!("{}", self.spi_usr_addr().bit()), + ) + .field( + "spi_usr_command", + &format_args!("{}", self.spi_usr_command().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_doutdin(&mut self) -> SPI_DOUTDIN_W { + SPI_DOUTDIN_W::new(self, 0) + } + #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_qpi_mode(&mut self) -> SPI_QPI_MODE_W { + SPI_QPI_MODE_W::new(self, 3) + } + #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."] + #[inline(always)] + #[must_use] + pub fn spi_tsck_i_edge(&mut self) -> SPI_TSCK_I_EDGE_W { + SPI_TSCK_I_EDGE_W::new(self, 5) + } + #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs_hold(&mut self) -> SPI_CS_HOLD_W { + SPI_CS_HOLD_W::new(self, 6) + } + #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs_setup(&mut self) -> SPI_CS_SETUP_W { + SPI_CS_SETUP_W::new(self, 7) + } + #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."] + #[inline(always)] + #[must_use] + pub fn spi_rsck_i_edge(&mut self) -> SPI_RSCK_I_EDGE_W { + SPI_RSCK_I_EDGE_W::new(self, 8) + } + #[doc = "Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_ck_out_edge(&mut self) -> SPI_CK_OUT_EDGE_W { + SPI_CK_OUT_EDGE_W::new(self, 9) + } + #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fwrite_dual(&mut self) -> SPI_FWRITE_DUAL_W { + SPI_FWRITE_DUAL_W::new(self, 12) + } + #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_fwrite_quad(&mut self) -> SPI_FWRITE_QUAD_W { + SPI_FWRITE_QUAD_W::new(self, 13) + } + #[doc = "Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_sio(&mut self) -> SPI_SIO_W { + SPI_SIO_W::new(self, 17) + } + #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_miso_highpart(&mut self) -> SPI_USR_MISO_HIGHPART_W { + SPI_USR_MISO_HIGHPART_W::new(self, 24) + } + #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_mosi_highpart(&mut self) -> SPI_USR_MOSI_HIGHPART_W { + SPI_USR_MOSI_HIGHPART_W::new(self, 25) + } + #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_dummy_idle(&mut self) -> SPI_USR_DUMMY_IDLE_W { + SPI_USR_DUMMY_IDLE_W::new(self, 26) + } + #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_mosi(&mut self) -> SPI_USR_MOSI_W { + SPI_USR_MOSI_W::new(self, 27) + } + #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_miso(&mut self) -> SPI_USR_MISO_W { + SPI_USR_MISO_W::new(self, 28) + } + #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_dummy(&mut self) -> SPI_USR_DUMMY_W { + SPI_USR_DUMMY_W::new(self, 29) + } + #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_addr(&mut self) -> SPI_USR_ADDR_W { + SPI_USR_ADDR_W::new(self, 30) + } + #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_command(&mut self) -> SPI_USR_COMMAND_W { + SPI_USR_COMMAND_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI USER control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_USER_SPEC; +impl crate::RegisterSpec for SPI_USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_user::R`](R) reader structure"] +impl crate::Readable for SPI_USER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_user::W`](W) writer structure"] +impl crate::Writable for SPI_USER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_USER to value 0x8000_00c0"] +impl crate::Resettable for SPI_USER_SPEC { + const RESET_VALUE: Self::Ux = 0x8000_00c0; +} diff --git a/esp32p4/src/spi3/spi_user1.rs b/esp32p4/src/spi3/spi_user1.rs new file mode 100644 index 0000000000..7d382bc958 --- /dev/null +++ b/esp32p4/src/spi3/spi_user1.rs @@ -0,0 +1,142 @@ +#[doc = "Register `SPI_USER1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_USER1` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_USR_DUMMY_CYCLELEN` reader - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."] +pub type SPI_USR_DUMMY_CYCLELEN_R = crate::FieldReader; +#[doc = "Field `SPI_USR_DUMMY_CYCLELEN` writer - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."] +pub type SPI_USR_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SPI_MST_WFULL_ERR_END_EN` reader - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."] +pub type SPI_MST_WFULL_ERR_END_EN_R = crate::BitReader; +#[doc = "Field `SPI_MST_WFULL_ERR_END_EN` writer - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."] +pub type SPI_MST_WFULL_ERR_END_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_CS_SETUP_TIME` reader - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."] +pub type SPI_CS_SETUP_TIME_R = crate::FieldReader; +#[doc = "Field `SPI_CS_SETUP_TIME` writer - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."] +pub type SPI_CS_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SPI_CS_HOLD_TIME` reader - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."] +pub type SPI_CS_HOLD_TIME_R = crate::FieldReader; +#[doc = "Field `SPI_CS_HOLD_TIME` writer - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."] +pub type SPI_CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SPI_USR_ADDR_BITLEN` reader - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_USR_ADDR_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_USR_ADDR_BITLEN` writer - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_USR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_dummy_cyclelen(&self) -> SPI_USR_DUMMY_CYCLELEN_R { + SPI_USR_DUMMY_CYCLELEN_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 16 - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."] + #[inline(always)] + pub fn spi_mst_wfull_err_end_en(&self) -> SPI_MST_WFULL_ERR_END_EN_R { + SPI_MST_WFULL_ERR_END_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:21 - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs_setup_time(&self) -> SPI_CS_SETUP_TIME_R { + SPI_CS_SETUP_TIME_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:26 - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_cs_hold_time(&self) -> SPI_CS_HOLD_TIME_R { + SPI_CS_HOLD_TIME_R::new(((self.bits >> 22) & 0x1f) as u8) + } + #[doc = "Bits 27:31 - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_addr_bitlen(&self) -> SPI_USR_ADDR_BITLEN_R { + SPI_USR_ADDR_BITLEN_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_USER1") + .field( + "spi_usr_dummy_cyclelen", + &format_args!("{}", self.spi_usr_dummy_cyclelen().bits()), + ) + .field( + "spi_mst_wfull_err_end_en", + &format_args!("{}", self.spi_mst_wfull_err_end_en().bit()), + ) + .field( + "spi_cs_setup_time", + &format_args!("{}", self.spi_cs_setup_time().bits()), + ) + .field( + "spi_cs_hold_time", + &format_args!("{}", self.spi_cs_hold_time().bits()), + ) + .field( + "spi_usr_addr_bitlen", + &format_args!("{}", self.spi_usr_addr_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_dummy_cyclelen(&mut self) -> SPI_USR_DUMMY_CYCLELEN_W { + SPI_USR_DUMMY_CYCLELEN_W::new(self, 0) + } + #[doc = "Bit 16 - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode."] + #[inline(always)] + #[must_use] + pub fn spi_mst_wfull_err_end_en(&mut self) -> SPI_MST_WFULL_ERR_END_EN_W { + SPI_MST_WFULL_ERR_END_EN_W::new(self, 16) + } + #[doc = "Bits 17:21 - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs_setup_time(&mut self) -> SPI_CS_SETUP_TIME_W { + SPI_CS_SETUP_TIME_W::new(self, 17) + } + #[doc = "Bits 22:26 - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_cs_hold_time(&mut self) -> SPI_CS_HOLD_TIME_W { + SPI_CS_HOLD_TIME_W::new(self, 22) + } + #[doc = "Bits 27:31 - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_addr_bitlen(&mut self) -> SPI_USR_ADDR_BITLEN_W { + SPI_USR_ADDR_BITLEN_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI USER control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_USER1_SPEC; +impl crate::RegisterSpec for SPI_USER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_user1::R`](R) reader structure"] +impl crate::Readable for SPI_USER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_user1::W`](W) writer structure"] +impl crate::Writable for SPI_USER1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_USER1 to value 0xb841_0007"] +impl crate::Resettable for SPI_USER1_SPEC { + const RESET_VALUE: Self::Ux = 0xb841_0007; +} diff --git a/esp32p4/src/spi3/spi_user2.rs b/esp32p4/src/spi3/spi_user2.rs new file mode 100644 index 0000000000..8fed5c2dc1 --- /dev/null +++ b/esp32p4/src/spi3/spi_user2.rs @@ -0,0 +1,104 @@ +#[doc = "Register `SPI_USER2` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_USER2` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_USR_COMMAND_VALUE` reader - The value of command. Can be configured in CONF state."] +pub type SPI_USR_COMMAND_VALUE_R = crate::FieldReader; +#[doc = "Field `SPI_USR_COMMAND_VALUE` writer - The value of command. Can be configured in CONF state."] +pub type SPI_USR_COMMAND_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SPI_MST_REMPTY_ERR_END_EN` reader - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode."] +pub type SPI_MST_REMPTY_ERR_END_EN_R = crate::BitReader; +#[doc = "Field `SPI_MST_REMPTY_ERR_END_EN` writer - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode."] +pub type SPI_MST_REMPTY_ERR_END_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI_USR_COMMAND_BITLEN` reader - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_USR_COMMAND_BITLEN_R = crate::FieldReader; +#[doc = "Field `SPI_USR_COMMAND_BITLEN` writer - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state."] +pub type SPI_USR_COMMAND_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_command_value(&self) -> SPI_USR_COMMAND_VALUE_R { + SPI_USR_COMMAND_VALUE_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 27 - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode."] + #[inline(always)] + pub fn spi_mst_rempty_err_end_en(&self) -> SPI_MST_REMPTY_ERR_END_EN_R { + SPI_MST_REMPTY_ERR_END_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + pub fn spi_usr_command_bitlen(&self) -> SPI_USR_COMMAND_BITLEN_R { + SPI_USR_COMMAND_BITLEN_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_USER2") + .field( + "spi_usr_command_value", + &format_args!("{}", self.spi_usr_command_value().bits()), + ) + .field( + "spi_mst_rempty_err_end_en", + &format_args!("{}", self.spi_mst_rempty_err_end_en().bit()), + ) + .field( + "spi_usr_command_bitlen", + &format_args!("{}", self.spi_usr_command_bitlen().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_command_value(&mut self) -> SPI_USR_COMMAND_VALUE_W { + SPI_USR_COMMAND_VALUE_W::new(self, 0) + } + #[doc = "Bit 27 - 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode."] + #[inline(always)] + #[must_use] + pub fn spi_mst_rempty_err_end_en(&mut self) -> SPI_MST_REMPTY_ERR_END_EN_W { + SPI_MST_REMPTY_ERR_END_EN_W::new(self, 27) + } + #[doc = "Bits 28:31 - The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state."] + #[inline(always)] + #[must_use] + pub fn spi_usr_command_bitlen(&mut self) -> SPI_USR_COMMAND_BITLEN_W { + SPI_USR_COMMAND_BITLEN_W::new(self, 28) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI USER control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_user2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_user2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_USER2_SPEC; +impl crate::RegisterSpec for SPI_USER2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_user2::R`](R) reader structure"] +impl crate::Readable for SPI_USER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_user2::W`](W) writer structure"] +impl crate::Writable for SPI_USER2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_USER2 to value 0x7800_0000"] +impl crate::Resettable for SPI_USER2_SPEC { + const RESET_VALUE: Self::Ux = 0x7800_0000; +} diff --git a/esp32p4/src/spi3/spi_w0.rs b/esp32p4/src/spi3/spi_w0.rs new file mode 100644 index 0000000000..9c70c5c2f4 --- /dev/null +++ b/esp32p4/src/spi3/spi_w0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W0` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W0` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF0` reader - data buffer"] +pub type SPI_BUF0_R = crate::FieldReader; +#[doc = "Field `SPI_BUF0` writer - data buffer"] +pub type SPI_BUF0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf0(&self) -> SPI_BUF0_R { + SPI_BUF0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W0") + .field("spi_buf0", &format_args!("{}", self.spi_buf0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf0(&mut self) -> SPI_BUF0_W { + SPI_BUF0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W0_SPEC; +impl crate::RegisterSpec for SPI_W0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w0::R`](R) reader structure"] +impl crate::Readable for SPI_W0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w0::W`](W) writer structure"] +impl crate::Writable for SPI_W0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W0 to value 0"] +impl crate::Resettable for SPI_W0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w1.rs b/esp32p4/src/spi3/spi_w1.rs new file mode 100644 index 0000000000..d2246bb39a --- /dev/null +++ b/esp32p4/src/spi3/spi_w1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W1` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF1` reader - data buffer"] +pub type SPI_BUF1_R = crate::FieldReader; +#[doc = "Field `SPI_BUF1` writer - data buffer"] +pub type SPI_BUF1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf1(&self) -> SPI_BUF1_R { + SPI_BUF1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W1") + .field("spi_buf1", &format_args!("{}", self.spi_buf1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf1(&mut self) -> SPI_BUF1_W { + SPI_BUF1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W1_SPEC; +impl crate::RegisterSpec for SPI_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w1::R`](R) reader structure"] +impl crate::Readable for SPI_W1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w1::W`](W) writer structure"] +impl crate::Writable for SPI_W1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W1 to value 0"] +impl crate::Resettable for SPI_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w10.rs b/esp32p4/src/spi3/spi_w10.rs new file mode 100644 index 0000000000..324fa92a1e --- /dev/null +++ b/esp32p4/src/spi3/spi_w10.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W10` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W10` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF10` reader - data buffer"] +pub type SPI_BUF10_R = crate::FieldReader; +#[doc = "Field `SPI_BUF10` writer - data buffer"] +pub type SPI_BUF10_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf10(&self) -> SPI_BUF10_R { + SPI_BUF10_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W10") + .field("spi_buf10", &format_args!("{}", self.spi_buf10().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf10(&mut self) -> SPI_BUF10_W { + SPI_BUF10_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W10_SPEC; +impl crate::RegisterSpec for SPI_W10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w10::R`](R) reader structure"] +impl crate::Readable for SPI_W10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w10::W`](W) writer structure"] +impl crate::Writable for SPI_W10_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W10 to value 0"] +impl crate::Resettable for SPI_W10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w11.rs b/esp32p4/src/spi3/spi_w11.rs new file mode 100644 index 0000000000..7b04dc7174 --- /dev/null +++ b/esp32p4/src/spi3/spi_w11.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W11` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W11` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF11` reader - data buffer"] +pub type SPI_BUF11_R = crate::FieldReader; +#[doc = "Field `SPI_BUF11` writer - data buffer"] +pub type SPI_BUF11_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf11(&self) -> SPI_BUF11_R { + SPI_BUF11_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W11") + .field("spi_buf11", &format_args!("{}", self.spi_buf11().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf11(&mut self) -> SPI_BUF11_W { + SPI_BUF11_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W11_SPEC; +impl crate::RegisterSpec for SPI_W11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w11::R`](R) reader structure"] +impl crate::Readable for SPI_W11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w11::W`](W) writer structure"] +impl crate::Writable for SPI_W11_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W11 to value 0"] +impl crate::Resettable for SPI_W11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w12.rs b/esp32p4/src/spi3/spi_w12.rs new file mode 100644 index 0000000000..c73425c68e --- /dev/null +++ b/esp32p4/src/spi3/spi_w12.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W12` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W12` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF12` reader - data buffer"] +pub type SPI_BUF12_R = crate::FieldReader; +#[doc = "Field `SPI_BUF12` writer - data buffer"] +pub type SPI_BUF12_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf12(&self) -> SPI_BUF12_R { + SPI_BUF12_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W12") + .field("spi_buf12", &format_args!("{}", self.spi_buf12().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf12(&mut self) -> SPI_BUF12_W { + SPI_BUF12_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W12_SPEC; +impl crate::RegisterSpec for SPI_W12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w12::R`](R) reader structure"] +impl crate::Readable for SPI_W12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w12::W`](W) writer structure"] +impl crate::Writable for SPI_W12_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W12 to value 0"] +impl crate::Resettable for SPI_W12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w13.rs b/esp32p4/src/spi3/spi_w13.rs new file mode 100644 index 0000000000..3930b40ee3 --- /dev/null +++ b/esp32p4/src/spi3/spi_w13.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W13` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W13` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF13` reader - data buffer"] +pub type SPI_BUF13_R = crate::FieldReader; +#[doc = "Field `SPI_BUF13` writer - data buffer"] +pub type SPI_BUF13_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf13(&self) -> SPI_BUF13_R { + SPI_BUF13_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W13") + .field("spi_buf13", &format_args!("{}", self.spi_buf13().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf13(&mut self) -> SPI_BUF13_W { + SPI_BUF13_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W13_SPEC; +impl crate::RegisterSpec for SPI_W13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w13::R`](R) reader structure"] +impl crate::Readable for SPI_W13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w13::W`](W) writer structure"] +impl crate::Writable for SPI_W13_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W13 to value 0"] +impl crate::Resettable for SPI_W13_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w14.rs b/esp32p4/src/spi3/spi_w14.rs new file mode 100644 index 0000000000..598007d8cc --- /dev/null +++ b/esp32p4/src/spi3/spi_w14.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W14` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W14` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF14` reader - data buffer"] +pub type SPI_BUF14_R = crate::FieldReader; +#[doc = "Field `SPI_BUF14` writer - data buffer"] +pub type SPI_BUF14_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf14(&self) -> SPI_BUF14_R { + SPI_BUF14_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W14") + .field("spi_buf14", &format_args!("{}", self.spi_buf14().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf14(&mut self) -> SPI_BUF14_W { + SPI_BUF14_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W14_SPEC; +impl crate::RegisterSpec for SPI_W14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w14::R`](R) reader structure"] +impl crate::Readable for SPI_W14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w14::W`](W) writer structure"] +impl crate::Writable for SPI_W14_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W14 to value 0"] +impl crate::Resettable for SPI_W14_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w15.rs b/esp32p4/src/spi3/spi_w15.rs new file mode 100644 index 0000000000..c1874cb7fa --- /dev/null +++ b/esp32p4/src/spi3/spi_w15.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W15` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W15` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF15` reader - data buffer"] +pub type SPI_BUF15_R = crate::FieldReader; +#[doc = "Field `SPI_BUF15` writer - data buffer"] +pub type SPI_BUF15_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf15(&self) -> SPI_BUF15_R { + SPI_BUF15_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W15") + .field("spi_buf15", &format_args!("{}", self.spi_buf15().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf15(&mut self) -> SPI_BUF15_W { + SPI_BUF15_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w15::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W15_SPEC; +impl crate::RegisterSpec for SPI_W15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w15::R`](R) reader structure"] +impl crate::Readable for SPI_W15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w15::W`](W) writer structure"] +impl crate::Writable for SPI_W15_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W15 to value 0"] +impl crate::Resettable for SPI_W15_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w2.rs b/esp32p4/src/spi3/spi_w2.rs new file mode 100644 index 0000000000..02efa5a2fb --- /dev/null +++ b/esp32p4/src/spi3/spi_w2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W2` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W2` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF2` reader - data buffer"] +pub type SPI_BUF2_R = crate::FieldReader; +#[doc = "Field `SPI_BUF2` writer - data buffer"] +pub type SPI_BUF2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf2(&self) -> SPI_BUF2_R { + SPI_BUF2_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W2") + .field("spi_buf2", &format_args!("{}", self.spi_buf2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf2(&mut self) -> SPI_BUF2_W { + SPI_BUF2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W2_SPEC; +impl crate::RegisterSpec for SPI_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w2::R`](R) reader structure"] +impl crate::Readable for SPI_W2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w2::W`](W) writer structure"] +impl crate::Writable for SPI_W2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W2 to value 0"] +impl crate::Resettable for SPI_W2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w3.rs b/esp32p4/src/spi3/spi_w3.rs new file mode 100644 index 0000000000..37b01969e9 --- /dev/null +++ b/esp32p4/src/spi3/spi_w3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W3` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W3` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF3` reader - data buffer"] +pub type SPI_BUF3_R = crate::FieldReader; +#[doc = "Field `SPI_BUF3` writer - data buffer"] +pub type SPI_BUF3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf3(&self) -> SPI_BUF3_R { + SPI_BUF3_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W3") + .field("spi_buf3", &format_args!("{}", self.spi_buf3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf3(&mut self) -> SPI_BUF3_W { + SPI_BUF3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W3_SPEC; +impl crate::RegisterSpec for SPI_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w3::R`](R) reader structure"] +impl crate::Readable for SPI_W3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w3::W`](W) writer structure"] +impl crate::Writable for SPI_W3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W3 to value 0"] +impl crate::Resettable for SPI_W3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w4.rs b/esp32p4/src/spi3/spi_w4.rs new file mode 100644 index 0000000000..3369cd6f01 --- /dev/null +++ b/esp32p4/src/spi3/spi_w4.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W4` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W4` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF4` reader - data buffer"] +pub type SPI_BUF4_R = crate::FieldReader; +#[doc = "Field `SPI_BUF4` writer - data buffer"] +pub type SPI_BUF4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf4(&self) -> SPI_BUF4_R { + SPI_BUF4_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W4") + .field("spi_buf4", &format_args!("{}", self.spi_buf4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf4(&mut self) -> SPI_BUF4_W { + SPI_BUF4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W4_SPEC; +impl crate::RegisterSpec for SPI_W4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w4::R`](R) reader structure"] +impl crate::Readable for SPI_W4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w4::W`](W) writer structure"] +impl crate::Writable for SPI_W4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W4 to value 0"] +impl crate::Resettable for SPI_W4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w5.rs b/esp32p4/src/spi3/spi_w5.rs new file mode 100644 index 0000000000..4d3c5ab984 --- /dev/null +++ b/esp32p4/src/spi3/spi_w5.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W5` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W5` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF5` reader - data buffer"] +pub type SPI_BUF5_R = crate::FieldReader; +#[doc = "Field `SPI_BUF5` writer - data buffer"] +pub type SPI_BUF5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf5(&self) -> SPI_BUF5_R { + SPI_BUF5_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W5") + .field("spi_buf5", &format_args!("{}", self.spi_buf5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf5(&mut self) -> SPI_BUF5_W { + SPI_BUF5_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W5_SPEC; +impl crate::RegisterSpec for SPI_W5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w5::R`](R) reader structure"] +impl crate::Readable for SPI_W5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w5::W`](W) writer structure"] +impl crate::Writable for SPI_W5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W5 to value 0"] +impl crate::Resettable for SPI_W5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w6.rs b/esp32p4/src/spi3/spi_w6.rs new file mode 100644 index 0000000000..f0b15ad83f --- /dev/null +++ b/esp32p4/src/spi3/spi_w6.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W6` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W6` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF6` reader - data buffer"] +pub type SPI_BUF6_R = crate::FieldReader; +#[doc = "Field `SPI_BUF6` writer - data buffer"] +pub type SPI_BUF6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf6(&self) -> SPI_BUF6_R { + SPI_BUF6_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W6") + .field("spi_buf6", &format_args!("{}", self.spi_buf6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf6(&mut self) -> SPI_BUF6_W { + SPI_BUF6_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W6_SPEC; +impl crate::RegisterSpec for SPI_W6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w6::R`](R) reader structure"] +impl crate::Readable for SPI_W6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w6::W`](W) writer structure"] +impl crate::Writable for SPI_W6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W6 to value 0"] +impl crate::Resettable for SPI_W6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w7.rs b/esp32p4/src/spi3/spi_w7.rs new file mode 100644 index 0000000000..668139f0a2 --- /dev/null +++ b/esp32p4/src/spi3/spi_w7.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W7` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W7` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF7` reader - data buffer"] +pub type SPI_BUF7_R = crate::FieldReader; +#[doc = "Field `SPI_BUF7` writer - data buffer"] +pub type SPI_BUF7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf7(&self) -> SPI_BUF7_R { + SPI_BUF7_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W7") + .field("spi_buf7", &format_args!("{}", self.spi_buf7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf7(&mut self) -> SPI_BUF7_W { + SPI_BUF7_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W7_SPEC; +impl crate::RegisterSpec for SPI_W7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w7::R`](R) reader structure"] +impl crate::Readable for SPI_W7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w7::W`](W) writer structure"] +impl crate::Writable for SPI_W7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W7 to value 0"] +impl crate::Resettable for SPI_W7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w8.rs b/esp32p4/src/spi3/spi_w8.rs new file mode 100644 index 0000000000..3d2f27b19a --- /dev/null +++ b/esp32p4/src/spi3/spi_w8.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W8` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W8` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF8` reader - data buffer"] +pub type SPI_BUF8_R = crate::FieldReader; +#[doc = "Field `SPI_BUF8` writer - data buffer"] +pub type SPI_BUF8_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf8(&self) -> SPI_BUF8_R { + SPI_BUF8_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W8") + .field("spi_buf8", &format_args!("{}", self.spi_buf8().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf8(&mut self) -> SPI_BUF8_W { + SPI_BUF8_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W8_SPEC; +impl crate::RegisterSpec for SPI_W8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w8::R`](R) reader structure"] +impl crate::Readable for SPI_W8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w8::W`](W) writer structure"] +impl crate::Writable for SPI_W8_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W8 to value 0"] +impl crate::Resettable for SPI_W8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/spi3/spi_w9.rs b/esp32p4/src/spi3/spi_w9.rs new file mode 100644 index 0000000000..29c8beb1c8 --- /dev/null +++ b/esp32p4/src/spi3/spi_w9.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SPI_W9` reader"] +pub type R = crate::R; +#[doc = "Register `SPI_W9` writer"] +pub type W = crate::W; +#[doc = "Field `SPI_BUF9` reader - data buffer"] +pub type SPI_BUF9_R = crate::FieldReader; +#[doc = "Field `SPI_BUF9` writer - data buffer"] +pub type SPI_BUF9_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + pub fn spi_buf9(&self) -> SPI_BUF9_R { + SPI_BUF9_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI_W9") + .field("spi_buf9", &format_args!("{}", self.spi_buf9().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - data buffer"] + #[inline(always)] + #[must_use] + pub fn spi_buf9(&mut self) -> SPI_BUF9_W { + SPI_BUF9_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "SPI CPU-controlled buffer9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_w9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_w9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI_W9_SPEC; +impl crate::RegisterSpec for SPI_W9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi_w9::R`](R) reader structure"] +impl crate::Readable for SPI_W9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi_w9::W`](W) writer structure"] +impl crate::Writable for SPI_W9_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SPI_W9 to value 0"] +impl crate::Resettable for SPI_W9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer.rs b/esp32p4/src/systimer.rs new file mode 100644 index 0000000000..47b5552cf2 --- /dev/null +++ b/esp32p4/src/systimer.rs @@ -0,0 +1,368 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + conf: CONF, + unit0_op: UNIT0_OP, + unit1_op: UNIT1_OP, + unit0_load_hi: UNIT0_LOAD_HI, + unit0_load_lo: UNIT0_LOAD_LO, + unit1_load_hi: UNIT1_LOAD_HI, + unit1_load_lo: UNIT1_LOAD_LO, + target0_hi: TARGET0_HI, + target0_lo: TARGET0_LO, + target1_hi: TARGET1_HI, + target1_lo: TARGET1_LO, + target2_hi: TARGET2_HI, + target2_lo: TARGET2_LO, + target0_conf: TARGET0_CONF, + target1_conf: TARGET1_CONF, + target2_conf: TARGET2_CONF, + unit0_value_hi: UNIT0_VALUE_HI, + unit0_value_lo: UNIT0_VALUE_LO, + unit1_value_hi: UNIT1_VALUE_HI, + unit1_value_lo: UNIT1_VALUE_LO, + comp0_load: COMP0_LOAD, + comp1_load: COMP1_LOAD, + comp2_load: COMP2_LOAD, + unit0_load: UNIT0_LOAD, + unit1_load: UNIT1_LOAD, + int_ena: INT_ENA, + int_raw: INT_RAW, + int_clr: INT_CLR, + int_st: INT_ST, + real_target0_lo: REAL_TARGET0_LO, + real_target0_hi: REAL_TARGET0_HI, + real_target1_lo: REAL_TARGET1_LO, + real_target1_hi: REAL_TARGET1_HI, + real_target2_lo: REAL_TARGET2_LO, + real_target2_hi: REAL_TARGET2_HI, + _reserved35: [u8; 0x70], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - Configure system timer clock"] + #[inline(always)] + pub const fn conf(&self) -> &CONF { + &self.conf + } + #[doc = "0x04 - system timer unit0 value update register"] + #[inline(always)] + pub const fn unit0_op(&self) -> &UNIT0_OP { + &self.unit0_op + } + #[doc = "0x08 - system timer unit1 value update register"] + #[inline(always)] + pub const fn unit1_op(&self) -> &UNIT1_OP { + &self.unit1_op + } + #[doc = "0x0c - system timer unit0 value high load register"] + #[inline(always)] + pub const fn unit0_load_hi(&self) -> &UNIT0_LOAD_HI { + &self.unit0_load_hi + } + #[doc = "0x10 - system timer unit0 value low load register"] + #[inline(always)] + pub const fn unit0_load_lo(&self) -> &UNIT0_LOAD_LO { + &self.unit0_load_lo + } + #[doc = "0x14 - system timer unit1 value high load register"] + #[inline(always)] + pub const fn unit1_load_hi(&self) -> &UNIT1_LOAD_HI { + &self.unit1_load_hi + } + #[doc = "0x18 - system timer unit1 value low load register"] + #[inline(always)] + pub const fn unit1_load_lo(&self) -> &UNIT1_LOAD_LO { + &self.unit1_load_lo + } + #[doc = "0x1c - system timer comp0 value high register"] + #[inline(always)] + pub const fn target0_hi(&self) -> &TARGET0_HI { + &self.target0_hi + } + #[doc = "0x20 - system timer comp0 value low register"] + #[inline(always)] + pub const fn target0_lo(&self) -> &TARGET0_LO { + &self.target0_lo + } + #[doc = "0x24 - system timer comp1 value high register"] + #[inline(always)] + pub const fn target1_hi(&self) -> &TARGET1_HI { + &self.target1_hi + } + #[doc = "0x28 - system timer comp1 value low register"] + #[inline(always)] + pub const fn target1_lo(&self) -> &TARGET1_LO { + &self.target1_lo + } + #[doc = "0x2c - system timer comp2 value high register"] + #[inline(always)] + pub const fn target2_hi(&self) -> &TARGET2_HI { + &self.target2_hi + } + #[doc = "0x30 - system timer comp2 value low register"] + #[inline(always)] + pub const fn target2_lo(&self) -> &TARGET2_LO { + &self.target2_lo + } + #[doc = "0x34 - system timer comp0 target mode register"] + #[inline(always)] + pub const fn target0_conf(&self) -> &TARGET0_CONF { + &self.target0_conf + } + #[doc = "0x38 - system timer comp1 target mode register"] + #[inline(always)] + pub const fn target1_conf(&self) -> &TARGET1_CONF { + &self.target1_conf + } + #[doc = "0x3c - system timer comp2 target mode register"] + #[inline(always)] + pub const fn target2_conf(&self) -> &TARGET2_CONF { + &self.target2_conf + } + #[doc = "0x40 - system timer unit0 value high register"] + #[inline(always)] + pub const fn unit0_value_hi(&self) -> &UNIT0_VALUE_HI { + &self.unit0_value_hi + } + #[doc = "0x44 - system timer unit0 value low register"] + #[inline(always)] + pub const fn unit0_value_lo(&self) -> &UNIT0_VALUE_LO { + &self.unit0_value_lo + } + #[doc = "0x48 - system timer unit1 value high register"] + #[inline(always)] + pub const fn unit1_value_hi(&self) -> &UNIT1_VALUE_HI { + &self.unit1_value_hi + } + #[doc = "0x4c - system timer unit1 value low register"] + #[inline(always)] + pub const fn unit1_value_lo(&self) -> &UNIT1_VALUE_LO { + &self.unit1_value_lo + } + #[doc = "0x50 - system timer comp0 conf sync register"] + #[inline(always)] + pub const fn comp0_load(&self) -> &COMP0_LOAD { + &self.comp0_load + } + #[doc = "0x54 - system timer comp1 conf sync register"] + #[inline(always)] + pub const fn comp1_load(&self) -> &COMP1_LOAD { + &self.comp1_load + } + #[doc = "0x58 - system timer comp2 conf sync register"] + #[inline(always)] + pub const fn comp2_load(&self) -> &COMP2_LOAD { + &self.comp2_load + } + #[doc = "0x5c - system timer unit0 conf sync register"] + #[inline(always)] + pub const fn unit0_load(&self) -> &UNIT0_LOAD { + &self.unit0_load + } + #[doc = "0x60 - system timer unit1 conf sync register"] + #[inline(always)] + pub const fn unit1_load(&self) -> &UNIT1_LOAD { + &self.unit1_load + } + #[doc = "0x64 - systimer interrupt enable register"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x68 - systimer interrupt raw register"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x6c - systimer interrupt clear register"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x70 - systimer interrupt status register"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x74 - system timer comp0 actual target value low register"] + #[inline(always)] + pub const fn real_target0_lo(&self) -> &REAL_TARGET0_LO { + &self.real_target0_lo + } + #[doc = "0x78 - system timer comp0 actual target value high register"] + #[inline(always)] + pub const fn real_target0_hi(&self) -> &REAL_TARGET0_HI { + &self.real_target0_hi + } + #[doc = "0x7c - system timer comp1 actual target value low register"] + #[inline(always)] + pub const fn real_target1_lo(&self) -> &REAL_TARGET1_LO { + &self.real_target1_lo + } + #[doc = "0x80 - system timer comp1 actual target value high register"] + #[inline(always)] + pub const fn real_target1_hi(&self) -> &REAL_TARGET1_HI { + &self.real_target1_hi + } + #[doc = "0x84 - system timer comp2 actual target value low register"] + #[inline(always)] + pub const fn real_target2_lo(&self) -> &REAL_TARGET2_LO { + &self.real_target2_lo + } + #[doc = "0x88 - system timer comp2 actual target value high register"] + #[inline(always)] + pub const fn real_target2_hi(&self) -> &REAL_TARGET2_HI { + &self.real_target2_hi + } + #[doc = "0xfc - system timer version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "CONF (rw) register accessor: Configure system timer clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"] +pub type CONF = crate::Reg; +#[doc = "Configure system timer clock"] +pub mod conf; +#[doc = "UNIT0_OP (rw) register accessor: system timer unit0 value update register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit0_op::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit0_op::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit0_op`] module"] +pub type UNIT0_OP = crate::Reg; +#[doc = "system timer unit0 value update register"] +pub mod unit0_op; +#[doc = "UNIT1_OP (rw) register accessor: system timer unit1 value update register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit1_op::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit1_op::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit1_op`] module"] +pub type UNIT1_OP = crate::Reg; +#[doc = "system timer unit1 value update register"] +pub mod unit1_op; +#[doc = "UNIT0_LOAD_HI (rw) register accessor: system timer unit0 value high load register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit0_load_hi::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit0_load_hi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit0_load_hi`] module"] +pub type UNIT0_LOAD_HI = crate::Reg; +#[doc = "system timer unit0 value high load register"] +pub mod unit0_load_hi; +#[doc = "UNIT0_LOAD_LO (rw) register accessor: system timer unit0 value low load register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit0_load_lo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit0_load_lo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit0_load_lo`] module"] +pub type UNIT0_LOAD_LO = crate::Reg; +#[doc = "system timer unit0 value low load register"] +pub mod unit0_load_lo; +#[doc = "UNIT1_LOAD_HI (rw) register accessor: system timer unit1 value high load register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit1_load_hi::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit1_load_hi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit1_load_hi`] module"] +pub type UNIT1_LOAD_HI = crate::Reg; +#[doc = "system timer unit1 value high load register"] +pub mod unit1_load_hi; +#[doc = "UNIT1_LOAD_LO (rw) register accessor: system timer unit1 value low load register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit1_load_lo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit1_load_lo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit1_load_lo`] module"] +pub type UNIT1_LOAD_LO = crate::Reg; +#[doc = "system timer unit1 value low load register"] +pub mod unit1_load_lo; +#[doc = "TARGET0_HI (rw) register accessor: system timer comp0 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target0_hi::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target0_hi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target0_hi`] module"] +pub type TARGET0_HI = crate::Reg; +#[doc = "system timer comp0 value high register"] +pub mod target0_hi; +#[doc = "TARGET0_LO (rw) register accessor: system timer comp0 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target0_lo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target0_lo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target0_lo`] module"] +pub type TARGET0_LO = crate::Reg; +#[doc = "system timer comp0 value low register"] +pub mod target0_lo; +#[doc = "TARGET1_HI (rw) register accessor: system timer comp1 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target1_hi::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target1_hi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target1_hi`] module"] +pub type TARGET1_HI = crate::Reg; +#[doc = "system timer comp1 value high register"] +pub mod target1_hi; +#[doc = "TARGET1_LO (rw) register accessor: system timer comp1 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target1_lo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target1_lo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target1_lo`] module"] +pub type TARGET1_LO = crate::Reg; +#[doc = "system timer comp1 value low register"] +pub mod target1_lo; +#[doc = "TARGET2_HI (rw) register accessor: system timer comp2 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target2_hi::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target2_hi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target2_hi`] module"] +pub type TARGET2_HI = crate::Reg; +#[doc = "system timer comp2 value high register"] +pub mod target2_hi; +#[doc = "TARGET2_LO (rw) register accessor: system timer comp2 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target2_lo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target2_lo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target2_lo`] module"] +pub type TARGET2_LO = crate::Reg; +#[doc = "system timer comp2 value low register"] +pub mod target2_lo; +#[doc = "TARGET0_CONF (rw) register accessor: system timer comp0 target mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target0_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target0_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target0_conf`] module"] +pub type TARGET0_CONF = crate::Reg; +#[doc = "system timer comp0 target mode register"] +pub mod target0_conf; +#[doc = "TARGET1_CONF (rw) register accessor: system timer comp1 target mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target1_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target1_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target1_conf`] module"] +pub type TARGET1_CONF = crate::Reg; +#[doc = "system timer comp1 target mode register"] +pub mod target1_conf; +#[doc = "TARGET2_CONF (rw) register accessor: system timer comp2 target mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target2_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target2_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target2_conf`] module"] +pub type TARGET2_CONF = crate::Reg; +#[doc = "system timer comp2 target mode register"] +pub mod target2_conf; +#[doc = "UNIT0_VALUE_HI (r) register accessor: system timer unit0 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit0_value_hi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit0_value_hi`] module"] +pub type UNIT0_VALUE_HI = crate::Reg; +#[doc = "system timer unit0 value high register"] +pub mod unit0_value_hi; +#[doc = "UNIT0_VALUE_LO (r) register accessor: system timer unit0 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit0_value_lo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit0_value_lo`] module"] +pub type UNIT0_VALUE_LO = crate::Reg; +#[doc = "system timer unit0 value low register"] +pub mod unit0_value_lo; +#[doc = "UNIT1_VALUE_HI (r) register accessor: system timer unit1 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit1_value_hi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit1_value_hi`] module"] +pub type UNIT1_VALUE_HI = crate::Reg; +#[doc = "system timer unit1 value high register"] +pub mod unit1_value_hi; +#[doc = "UNIT1_VALUE_LO (r) register accessor: system timer unit1 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit1_value_lo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit1_value_lo`] module"] +pub type UNIT1_VALUE_LO = crate::Reg; +#[doc = "system timer unit1 value low register"] +pub mod unit1_value_lo; +#[doc = "COMP0_LOAD (w) register accessor: system timer comp0 conf sync register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp0_load::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp0_load`] module"] +pub type COMP0_LOAD = crate::Reg; +#[doc = "system timer comp0 conf sync register"] +pub mod comp0_load; +#[doc = "COMP1_LOAD (w) register accessor: system timer comp1 conf sync register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp1_load::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp1_load`] module"] +pub type COMP1_LOAD = crate::Reg; +#[doc = "system timer comp1 conf sync register"] +pub mod comp1_load; +#[doc = "COMP2_LOAD (w) register accessor: system timer comp2 conf sync register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp2_load::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@comp2_load`] module"] +pub type COMP2_LOAD = crate::Reg; +#[doc = "system timer comp2 conf sync register"] +pub mod comp2_load; +#[doc = "UNIT0_LOAD (w) register accessor: system timer unit0 conf sync register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit0_load::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit0_load`] module"] +pub type UNIT0_LOAD = crate::Reg; +#[doc = "system timer unit0 conf sync register"] +pub mod unit0_load; +#[doc = "UNIT1_LOAD (w) register accessor: system timer unit1 conf sync register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit1_load::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unit1_load`] module"] +pub type UNIT1_LOAD = crate::Reg; +#[doc = "system timer unit1 conf sync register"] +pub mod unit1_load; +#[doc = "INT_ENA (rw) register accessor: systimer interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "systimer interrupt enable register"] +pub mod int_ena; +#[doc = "INT_RAW (rw) register accessor: systimer interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "systimer interrupt raw register"] +pub mod int_raw; +#[doc = "INT_CLR (w) register accessor: systimer interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "systimer interrupt clear register"] +pub mod int_clr; +#[doc = "INT_ST (r) register accessor: systimer interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "systimer interrupt status register"] +pub mod int_st; +#[doc = "REAL_TARGET0_LO (r) register accessor: system timer comp0 actual target value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target0_lo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@real_target0_lo`] module"] +pub type REAL_TARGET0_LO = crate::Reg; +#[doc = "system timer comp0 actual target value low register"] +pub mod real_target0_lo; +#[doc = "REAL_TARGET0_HI (r) register accessor: system timer comp0 actual target value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target0_hi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@real_target0_hi`] module"] +pub type REAL_TARGET0_HI = crate::Reg; +#[doc = "system timer comp0 actual target value high register"] +pub mod real_target0_hi; +#[doc = "REAL_TARGET1_LO (r) register accessor: system timer comp1 actual target value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target1_lo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@real_target1_lo`] module"] +pub type REAL_TARGET1_LO = crate::Reg; +#[doc = "system timer comp1 actual target value low register"] +pub mod real_target1_lo; +#[doc = "REAL_TARGET1_HI (r) register accessor: system timer comp1 actual target value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target1_hi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@real_target1_hi`] module"] +pub type REAL_TARGET1_HI = crate::Reg; +#[doc = "system timer comp1 actual target value high register"] +pub mod real_target1_hi; +#[doc = "REAL_TARGET2_LO (r) register accessor: system timer comp2 actual target value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target2_lo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@real_target2_lo`] module"] +pub type REAL_TARGET2_LO = crate::Reg; +#[doc = "system timer comp2 actual target value low register"] +pub mod real_target2_lo; +#[doc = "REAL_TARGET2_HI (r) register accessor: system timer comp2 actual target value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target2_hi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@real_target2_hi`] module"] +pub type REAL_TARGET2_HI = crate::Reg; +#[doc = "system timer comp2 actual target value high register"] +pub mod real_target2_hi; +#[doc = "DATE (rw) register accessor: system timer version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "system timer version control register"] +pub mod date; diff --git a/esp32p4/src/systimer/comp0_load.rs b/esp32p4/src/systimer/comp0_load.rs new file mode 100644 index 0000000000..82a523683f --- /dev/null +++ b/esp32p4/src/systimer/comp0_load.rs @@ -0,0 +1,42 @@ +#[doc = "Register `COMP0_LOAD` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_COMP0_LOAD` writer - timer comp0 sync enable signal"] +pub type TIMER_COMP0_LOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - timer comp0 sync enable signal"] + #[inline(always)] + #[must_use] + pub fn timer_comp0_load(&mut self) -> TIMER_COMP0_LOAD_W { + TIMER_COMP0_LOAD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp0 conf sync register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp0_load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMP0_LOAD_SPEC; +impl crate::RegisterSpec for COMP0_LOAD_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`comp0_load::W`](W) writer structure"] +impl crate::Writable for COMP0_LOAD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMP0_LOAD to value 0"] +impl crate::Resettable for COMP0_LOAD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/comp1_load.rs b/esp32p4/src/systimer/comp1_load.rs new file mode 100644 index 0000000000..3fa8c3c53b --- /dev/null +++ b/esp32p4/src/systimer/comp1_load.rs @@ -0,0 +1,42 @@ +#[doc = "Register `COMP1_LOAD` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_COMP1_LOAD` writer - timer comp1 sync enable signal"] +pub type TIMER_COMP1_LOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - timer comp1 sync enable signal"] + #[inline(always)] + #[must_use] + pub fn timer_comp1_load(&mut self) -> TIMER_COMP1_LOAD_W { + TIMER_COMP1_LOAD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp1 conf sync register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp1_load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMP1_LOAD_SPEC; +impl crate::RegisterSpec for COMP1_LOAD_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`comp1_load::W`](W) writer structure"] +impl crate::Writable for COMP1_LOAD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMP1_LOAD to value 0"] +impl crate::Resettable for COMP1_LOAD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/comp2_load.rs b/esp32p4/src/systimer/comp2_load.rs new file mode 100644 index 0000000000..2a28e8813f --- /dev/null +++ b/esp32p4/src/systimer/comp2_load.rs @@ -0,0 +1,42 @@ +#[doc = "Register `COMP2_LOAD` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_COMP2_LOAD` writer - timer comp2 sync enable signal"] +pub type TIMER_COMP2_LOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - timer comp2 sync enable signal"] + #[inline(always)] + #[must_use] + pub fn timer_comp2_load(&mut self) -> TIMER_COMP2_LOAD_W { + TIMER_COMP2_LOAD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp2 conf sync register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp2_load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COMP2_LOAD_SPEC; +impl crate::RegisterSpec for COMP2_LOAD_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`comp2_load::W`](W) writer structure"] +impl crate::Writable for COMP2_LOAD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMP2_LOAD to value 0"] +impl crate::Resettable for COMP2_LOAD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/conf.rs b/esp32p4/src/systimer/conf.rs new file mode 100644 index 0000000000..ce55e19f31 --- /dev/null +++ b/esp32p4/src/systimer/conf.rs @@ -0,0 +1,269 @@ +#[doc = "Register `CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SYSTIMER_CLK_FO` reader - systimer clock force on"] +pub type SYSTIMER_CLK_FO_R = crate::BitReader; +#[doc = "Field `SYSTIMER_CLK_FO` writer - systimer clock force on"] +pub type SYSTIMER_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETM_EN` reader - enable systimer's etm task and event"] +pub type ETM_EN_R = crate::BitReader; +#[doc = "Field `ETM_EN` writer - enable systimer's etm task and event"] +pub type ETM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET2_WORK_EN` reader - target2 work enable"] +pub type TARGET2_WORK_EN_R = crate::BitReader; +#[doc = "Field `TARGET2_WORK_EN` writer - target2 work enable"] +pub type TARGET2_WORK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET1_WORK_EN` reader - target1 work enable"] +pub type TARGET1_WORK_EN_R = crate::BitReader; +#[doc = "Field `TARGET1_WORK_EN` writer - target1 work enable"] +pub type TARGET1_WORK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET0_WORK_EN` reader - target0 work enable"] +pub type TARGET0_WORK_EN_R = crate::BitReader; +#[doc = "Field `TARGET0_WORK_EN` writer - target0 work enable"] +pub type TARGET0_WORK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_UNIT1_CORE1_STALL_EN` reader - If timer unit1 is stalled when core1 stalled"] +pub type TIMER_UNIT1_CORE1_STALL_EN_R = crate::BitReader; +#[doc = "Field `TIMER_UNIT1_CORE1_STALL_EN` writer - If timer unit1 is stalled when core1 stalled"] +pub type TIMER_UNIT1_CORE1_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_UNIT1_CORE0_STALL_EN` reader - If timer unit1 is stalled when core0 stalled"] +pub type TIMER_UNIT1_CORE0_STALL_EN_R = crate::BitReader; +#[doc = "Field `TIMER_UNIT1_CORE0_STALL_EN` writer - If timer unit1 is stalled when core0 stalled"] +pub type TIMER_UNIT1_CORE0_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_UNIT0_CORE1_STALL_EN` reader - If timer unit0 is stalled when core1 stalled"] +pub type TIMER_UNIT0_CORE1_STALL_EN_R = crate::BitReader; +#[doc = "Field `TIMER_UNIT0_CORE1_STALL_EN` writer - If timer unit0 is stalled when core1 stalled"] +pub type TIMER_UNIT0_CORE1_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_UNIT0_CORE0_STALL_EN` reader - If timer unit0 is stalled when core0 stalled"] +pub type TIMER_UNIT0_CORE0_STALL_EN_R = crate::BitReader; +#[doc = "Field `TIMER_UNIT0_CORE0_STALL_EN` writer - If timer unit0 is stalled when core0 stalled"] +pub type TIMER_UNIT0_CORE0_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_UNIT1_WORK_EN` reader - timer unit1 work enable"] +pub type TIMER_UNIT1_WORK_EN_R = crate::BitReader; +#[doc = "Field `TIMER_UNIT1_WORK_EN` writer - timer unit1 work enable"] +pub type TIMER_UNIT1_WORK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_UNIT0_WORK_EN` reader - timer unit0 work enable"] +pub type TIMER_UNIT0_WORK_EN_R = crate::BitReader; +#[doc = "Field `TIMER_UNIT0_WORK_EN` writer - timer unit0 work enable"] +pub type TIMER_UNIT0_WORK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - register file clk gating"] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - register file clk gating"] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - systimer clock force on"] + #[inline(always)] + pub fn systimer_clk_fo(&self) -> SYSTIMER_CLK_FO_R { + SYSTIMER_CLK_FO_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - enable systimer's etm task and event"] + #[inline(always)] + pub fn etm_en(&self) -> ETM_EN_R { + ETM_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 22 - target2 work enable"] + #[inline(always)] + pub fn target2_work_en(&self) -> TARGET2_WORK_EN_R { + TARGET2_WORK_EN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - target1 work enable"] + #[inline(always)] + pub fn target1_work_en(&self) -> TARGET1_WORK_EN_R { + TARGET1_WORK_EN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - target0 work enable"] + #[inline(always)] + pub fn target0_work_en(&self) -> TARGET0_WORK_EN_R { + TARGET0_WORK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - If timer unit1 is stalled when core1 stalled"] + #[inline(always)] + pub fn timer_unit1_core1_stall_en(&self) -> TIMER_UNIT1_CORE1_STALL_EN_R { + TIMER_UNIT1_CORE1_STALL_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - If timer unit1 is stalled when core0 stalled"] + #[inline(always)] + pub fn timer_unit1_core0_stall_en(&self) -> TIMER_UNIT1_CORE0_STALL_EN_R { + TIMER_UNIT1_CORE0_STALL_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - If timer unit0 is stalled when core1 stalled"] + #[inline(always)] + pub fn timer_unit0_core1_stall_en(&self) -> TIMER_UNIT0_CORE1_STALL_EN_R { + TIMER_UNIT0_CORE1_STALL_EN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - If timer unit0 is stalled when core0 stalled"] + #[inline(always)] + pub fn timer_unit0_core0_stall_en(&self) -> TIMER_UNIT0_CORE0_STALL_EN_R { + TIMER_UNIT0_CORE0_STALL_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - timer unit1 work enable"] + #[inline(always)] + pub fn timer_unit1_work_en(&self) -> TIMER_UNIT1_WORK_EN_R { + TIMER_UNIT1_WORK_EN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - timer unit0 work enable"] + #[inline(always)] + pub fn timer_unit0_work_en(&self) -> TIMER_UNIT0_WORK_EN_R { + TIMER_UNIT0_WORK_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - register file clk gating"] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF") + .field( + "systimer_clk_fo", + &format_args!("{}", self.systimer_clk_fo().bit()), + ) + .field("etm_en", &format_args!("{}", self.etm_en().bit())) + .field( + "target2_work_en", + &format_args!("{}", self.target2_work_en().bit()), + ) + .field( + "target1_work_en", + &format_args!("{}", self.target1_work_en().bit()), + ) + .field( + "target0_work_en", + &format_args!("{}", self.target0_work_en().bit()), + ) + .field( + "timer_unit1_core1_stall_en", + &format_args!("{}", self.timer_unit1_core1_stall_en().bit()), + ) + .field( + "timer_unit1_core0_stall_en", + &format_args!("{}", self.timer_unit1_core0_stall_en().bit()), + ) + .field( + "timer_unit0_core1_stall_en", + &format_args!("{}", self.timer_unit0_core1_stall_en().bit()), + ) + .field( + "timer_unit0_core0_stall_en", + &format_args!("{}", self.timer_unit0_core0_stall_en().bit()), + ) + .field( + "timer_unit1_work_en", + &format_args!("{}", self.timer_unit1_work_en().bit()), + ) + .field( + "timer_unit0_work_en", + &format_args!("{}", self.timer_unit0_work_en().bit()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - systimer clock force on"] + #[inline(always)] + #[must_use] + pub fn systimer_clk_fo(&mut self) -> SYSTIMER_CLK_FO_W { + SYSTIMER_CLK_FO_W::new(self, 0) + } + #[doc = "Bit 1 - enable systimer's etm task and event"] + #[inline(always)] + #[must_use] + pub fn etm_en(&mut self) -> ETM_EN_W { + ETM_EN_W::new(self, 1) + } + #[doc = "Bit 22 - target2 work enable"] + #[inline(always)] + #[must_use] + pub fn target2_work_en(&mut self) -> TARGET2_WORK_EN_W { + TARGET2_WORK_EN_W::new(self, 22) + } + #[doc = "Bit 23 - target1 work enable"] + #[inline(always)] + #[must_use] + pub fn target1_work_en(&mut self) -> TARGET1_WORK_EN_W { + TARGET1_WORK_EN_W::new(self, 23) + } + #[doc = "Bit 24 - target0 work enable"] + #[inline(always)] + #[must_use] + pub fn target0_work_en(&mut self) -> TARGET0_WORK_EN_W { + TARGET0_WORK_EN_W::new(self, 24) + } + #[doc = "Bit 25 - If timer unit1 is stalled when core1 stalled"] + #[inline(always)] + #[must_use] + pub fn timer_unit1_core1_stall_en(&mut self) -> TIMER_UNIT1_CORE1_STALL_EN_W { + TIMER_UNIT1_CORE1_STALL_EN_W::new(self, 25) + } + #[doc = "Bit 26 - If timer unit1 is stalled when core0 stalled"] + #[inline(always)] + #[must_use] + pub fn timer_unit1_core0_stall_en(&mut self) -> TIMER_UNIT1_CORE0_STALL_EN_W { + TIMER_UNIT1_CORE0_STALL_EN_W::new(self, 26) + } + #[doc = "Bit 27 - If timer unit0 is stalled when core1 stalled"] + #[inline(always)] + #[must_use] + pub fn timer_unit0_core1_stall_en(&mut self) -> TIMER_UNIT0_CORE1_STALL_EN_W { + TIMER_UNIT0_CORE1_STALL_EN_W::new(self, 27) + } + #[doc = "Bit 28 - If timer unit0 is stalled when core0 stalled"] + #[inline(always)] + #[must_use] + pub fn timer_unit0_core0_stall_en(&mut self) -> TIMER_UNIT0_CORE0_STALL_EN_W { + TIMER_UNIT0_CORE0_STALL_EN_W::new(self, 28) + } + #[doc = "Bit 29 - timer unit1 work enable"] + #[inline(always)] + #[must_use] + pub fn timer_unit1_work_en(&mut self) -> TIMER_UNIT1_WORK_EN_W { + TIMER_UNIT1_WORK_EN_W::new(self, 29) + } + #[doc = "Bit 30 - timer unit0 work enable"] + #[inline(always)] + #[must_use] + pub fn timer_unit0_work_en(&mut self) -> TIMER_UNIT0_WORK_EN_W { + TIMER_UNIT0_WORK_EN_W::new(self, 30) + } + #[doc = "Bit 31 - register file clk gating"] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure system timer clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF_SPEC; +impl crate::RegisterSpec for CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf::R`](R) reader structure"] +impl crate::Readable for CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"] +impl crate::Writable for CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF to value 0x4600_0000"] +impl crate::Resettable for CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x4600_0000; +} diff --git a/esp32p4/src/systimer/date.rs b/esp32p4/src/systimer/date.rs new file mode 100644 index 0000000000..6474103252 --- /dev/null +++ b/esp32p4/src/systimer/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - systimer register version"] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - systimer register version"] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - systimer register version"] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - systimer register version"] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0220_1073"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_1073; +} diff --git a/esp32p4/src/systimer/int_clr.rs b/esp32p4/src/systimer/int_clr.rs new file mode 100644 index 0000000000..4e9db1103c --- /dev/null +++ b/esp32p4/src/systimer/int_clr.rs @@ -0,0 +1,58 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `TARGET0_INT_CLR` writer - interupt0 clear"] +pub type TARGET0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET1_INT_CLR` writer - interupt1 clear"] +pub type TARGET1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET2_INT_CLR` writer - interupt2 clear"] +pub type TARGET2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - interupt0 clear"] + #[inline(always)] + #[must_use] + pub fn target0_int_clr(&mut self) -> TARGET0_INT_CLR_W { + TARGET0_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - interupt1 clear"] + #[inline(always)] + #[must_use] + pub fn target1_int_clr(&mut self) -> TARGET1_INT_CLR_W { + TARGET1_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - interupt2 clear"] + #[inline(always)] + #[must_use] + pub fn target2_int_clr(&mut self) -> TARGET2_INT_CLR_W { + TARGET2_INT_CLR_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "systimer interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/int_ena.rs b/esp32p4/src/systimer/int_ena.rs new file mode 100644 index 0000000000..4fe7d8ac29 --- /dev/null +++ b/esp32p4/src/systimer/int_ena.rs @@ -0,0 +1,104 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `TARGET0_INT_ENA` reader - interupt0 enable"] +pub type TARGET0_INT_ENA_R = crate::BitReader; +#[doc = "Field `TARGET0_INT_ENA` writer - interupt0 enable"] +pub type TARGET0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET1_INT_ENA` reader - interupt1 enable"] +pub type TARGET1_INT_ENA_R = crate::BitReader; +#[doc = "Field `TARGET1_INT_ENA` writer - interupt1 enable"] +pub type TARGET1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET2_INT_ENA` reader - interupt2 enable"] +pub type TARGET2_INT_ENA_R = crate::BitReader; +#[doc = "Field `TARGET2_INT_ENA` writer - interupt2 enable"] +pub type TARGET2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - interupt0 enable"] + #[inline(always)] + pub fn target0_int_ena(&self) -> TARGET0_INT_ENA_R { + TARGET0_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - interupt1 enable"] + #[inline(always)] + pub fn target1_int_ena(&self) -> TARGET1_INT_ENA_R { + TARGET1_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - interupt2 enable"] + #[inline(always)] + pub fn target2_int_ena(&self) -> TARGET2_INT_ENA_R { + TARGET2_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "target0_int_ena", + &format_args!("{}", self.target0_int_ena().bit()), + ) + .field( + "target1_int_ena", + &format_args!("{}", self.target1_int_ena().bit()), + ) + .field( + "target2_int_ena", + &format_args!("{}", self.target2_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - interupt0 enable"] + #[inline(always)] + #[must_use] + pub fn target0_int_ena(&mut self) -> TARGET0_INT_ENA_W { + TARGET0_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - interupt1 enable"] + #[inline(always)] + #[must_use] + pub fn target1_int_ena(&mut self) -> TARGET1_INT_ENA_W { + TARGET1_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - interupt2 enable"] + #[inline(always)] + #[must_use] + pub fn target2_int_ena(&mut self) -> TARGET2_INT_ENA_W { + TARGET2_INT_ENA_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "systimer interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/int_raw.rs b/esp32p4/src/systimer/int_raw.rs new file mode 100644 index 0000000000..3cff301c54 --- /dev/null +++ b/esp32p4/src/systimer/int_raw.rs @@ -0,0 +1,104 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `TARGET0_INT_RAW` reader - interupt0 raw"] +pub type TARGET0_INT_RAW_R = crate::BitReader; +#[doc = "Field `TARGET0_INT_RAW` writer - interupt0 raw"] +pub type TARGET0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET1_INT_RAW` reader - interupt1 raw"] +pub type TARGET1_INT_RAW_R = crate::BitReader; +#[doc = "Field `TARGET1_INT_RAW` writer - interupt1 raw"] +pub type TARGET1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET2_INT_RAW` reader - interupt2 raw"] +pub type TARGET2_INT_RAW_R = crate::BitReader; +#[doc = "Field `TARGET2_INT_RAW` writer - interupt2 raw"] +pub type TARGET2_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - interupt0 raw"] + #[inline(always)] + pub fn target0_int_raw(&self) -> TARGET0_INT_RAW_R { + TARGET0_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - interupt1 raw"] + #[inline(always)] + pub fn target1_int_raw(&self) -> TARGET1_INT_RAW_R { + TARGET1_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - interupt2 raw"] + #[inline(always)] + pub fn target2_int_raw(&self) -> TARGET2_INT_RAW_R { + TARGET2_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "target0_int_raw", + &format_args!("{}", self.target0_int_raw().bit()), + ) + .field( + "target1_int_raw", + &format_args!("{}", self.target1_int_raw().bit()), + ) + .field( + "target2_int_raw", + &format_args!("{}", self.target2_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - interupt0 raw"] + #[inline(always)] + #[must_use] + pub fn target0_int_raw(&mut self) -> TARGET0_INT_RAW_W { + TARGET0_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - interupt1 raw"] + #[inline(always)] + #[must_use] + pub fn target1_int_raw(&mut self) -> TARGET1_INT_RAW_W { + TARGET1_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - interupt2 raw"] + #[inline(always)] + #[must_use] + pub fn target2_int_raw(&mut self) -> TARGET2_INT_RAW_W { + TARGET2_INT_RAW_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "systimer interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/int_st.rs b/esp32p4/src/systimer/int_st.rs new file mode 100644 index 0000000000..a6b2b0bd26 --- /dev/null +++ b/esp32p4/src/systimer/int_st.rs @@ -0,0 +1,61 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `TARGET0_INT_ST` reader - interupt0 status"] +pub type TARGET0_INT_ST_R = crate::BitReader; +#[doc = "Field `TARGET1_INT_ST` reader - interupt1 status"] +pub type TARGET1_INT_ST_R = crate::BitReader; +#[doc = "Field `TARGET2_INT_ST` reader - interupt2 status"] +pub type TARGET2_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - interupt0 status"] + #[inline(always)] + pub fn target0_int_st(&self) -> TARGET0_INT_ST_R { + TARGET0_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - interupt1 status"] + #[inline(always)] + pub fn target1_int_st(&self) -> TARGET1_INT_ST_R { + TARGET1_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - interupt2 status"] + #[inline(always)] + pub fn target2_int_st(&self) -> TARGET2_INT_ST_R { + TARGET2_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "target0_int_st", + &format_args!("{}", self.target0_int_st().bit()), + ) + .field( + "target1_int_st", + &format_args!("{}", self.target1_int_st().bit()), + ) + .field( + "target2_int_st", + &format_args!("{}", self.target2_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "systimer interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/real_target0_hi.rs b/esp32p4/src/systimer/real_target0_hi.rs new file mode 100644 index 0000000000..c3b7add42c --- /dev/null +++ b/esp32p4/src/systimer/real_target0_hi.rs @@ -0,0 +1,39 @@ +#[doc = "Register `REAL_TARGET0_HI` reader"] +pub type R = crate::R; +#[doc = "Field `TARGET0_HI_RO` reader - actual target value value high 20bits"] +pub type TARGET0_HI_RO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - actual target value value high 20bits"] + #[inline(always)] + pub fn target0_hi_ro(&self) -> TARGET0_HI_RO_R { + TARGET0_HI_RO_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REAL_TARGET0_HI") + .field( + "target0_hi_ro", + &format_args!("{}", self.target0_hi_ro().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "system timer comp0 actual target value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target0_hi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REAL_TARGET0_HI_SPEC; +impl crate::RegisterSpec for REAL_TARGET0_HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`real_target0_hi::R`](R) reader structure"] +impl crate::Readable for REAL_TARGET0_HI_SPEC {} +#[doc = "`reset()` method sets REAL_TARGET0_HI to value 0"] +impl crate::Resettable for REAL_TARGET0_HI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/real_target0_lo.rs b/esp32p4/src/systimer/real_target0_lo.rs new file mode 100644 index 0000000000..67078fe8bd --- /dev/null +++ b/esp32p4/src/systimer/real_target0_lo.rs @@ -0,0 +1,39 @@ +#[doc = "Register `REAL_TARGET0_LO` reader"] +pub type R = crate::R; +#[doc = "Field `TARGET0_LO_RO` reader - actual target value value low 32bits"] +pub type TARGET0_LO_RO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - actual target value value low 32bits"] + #[inline(always)] + pub fn target0_lo_ro(&self) -> TARGET0_LO_RO_R { + TARGET0_LO_RO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REAL_TARGET0_LO") + .field( + "target0_lo_ro", + &format_args!("{}", self.target0_lo_ro().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "system timer comp0 actual target value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target0_lo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REAL_TARGET0_LO_SPEC; +impl crate::RegisterSpec for REAL_TARGET0_LO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`real_target0_lo::R`](R) reader structure"] +impl crate::Readable for REAL_TARGET0_LO_SPEC {} +#[doc = "`reset()` method sets REAL_TARGET0_LO to value 0"] +impl crate::Resettable for REAL_TARGET0_LO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/real_target1_hi.rs b/esp32p4/src/systimer/real_target1_hi.rs new file mode 100644 index 0000000000..93ca010056 --- /dev/null +++ b/esp32p4/src/systimer/real_target1_hi.rs @@ -0,0 +1,39 @@ +#[doc = "Register `REAL_TARGET1_HI` reader"] +pub type R = crate::R; +#[doc = "Field `TARGET1_HI_RO` reader - actual target value value high 20bits"] +pub type TARGET1_HI_RO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - actual target value value high 20bits"] + #[inline(always)] + pub fn target1_hi_ro(&self) -> TARGET1_HI_RO_R { + TARGET1_HI_RO_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REAL_TARGET1_HI") + .field( + "target1_hi_ro", + &format_args!("{}", self.target1_hi_ro().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "system timer comp1 actual target value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target1_hi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REAL_TARGET1_HI_SPEC; +impl crate::RegisterSpec for REAL_TARGET1_HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`real_target1_hi::R`](R) reader structure"] +impl crate::Readable for REAL_TARGET1_HI_SPEC {} +#[doc = "`reset()` method sets REAL_TARGET1_HI to value 0"] +impl crate::Resettable for REAL_TARGET1_HI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/real_target1_lo.rs b/esp32p4/src/systimer/real_target1_lo.rs new file mode 100644 index 0000000000..58e46f8f9c --- /dev/null +++ b/esp32p4/src/systimer/real_target1_lo.rs @@ -0,0 +1,39 @@ +#[doc = "Register `REAL_TARGET1_LO` reader"] +pub type R = crate::R; +#[doc = "Field `TARGET1_LO_RO` reader - actual target value value low 32bits"] +pub type TARGET1_LO_RO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - actual target value value low 32bits"] + #[inline(always)] + pub fn target1_lo_ro(&self) -> TARGET1_LO_RO_R { + TARGET1_LO_RO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REAL_TARGET1_LO") + .field( + "target1_lo_ro", + &format_args!("{}", self.target1_lo_ro().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "system timer comp1 actual target value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target1_lo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REAL_TARGET1_LO_SPEC; +impl crate::RegisterSpec for REAL_TARGET1_LO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`real_target1_lo::R`](R) reader structure"] +impl crate::Readable for REAL_TARGET1_LO_SPEC {} +#[doc = "`reset()` method sets REAL_TARGET1_LO to value 0"] +impl crate::Resettable for REAL_TARGET1_LO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/real_target2_hi.rs b/esp32p4/src/systimer/real_target2_hi.rs new file mode 100644 index 0000000000..a475e2a455 --- /dev/null +++ b/esp32p4/src/systimer/real_target2_hi.rs @@ -0,0 +1,39 @@ +#[doc = "Register `REAL_TARGET2_HI` reader"] +pub type R = crate::R; +#[doc = "Field `TARGET2_HI_RO` reader - actual target value value high 20bits"] +pub type TARGET2_HI_RO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - actual target value value high 20bits"] + #[inline(always)] + pub fn target2_hi_ro(&self) -> TARGET2_HI_RO_R { + TARGET2_HI_RO_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REAL_TARGET2_HI") + .field( + "target2_hi_ro", + &format_args!("{}", self.target2_hi_ro().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "system timer comp2 actual target value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target2_hi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REAL_TARGET2_HI_SPEC; +impl crate::RegisterSpec for REAL_TARGET2_HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`real_target2_hi::R`](R) reader structure"] +impl crate::Readable for REAL_TARGET2_HI_SPEC {} +#[doc = "`reset()` method sets REAL_TARGET2_HI to value 0"] +impl crate::Resettable for REAL_TARGET2_HI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/real_target2_lo.rs b/esp32p4/src/systimer/real_target2_lo.rs new file mode 100644 index 0000000000..c8eac12e0e --- /dev/null +++ b/esp32p4/src/systimer/real_target2_lo.rs @@ -0,0 +1,39 @@ +#[doc = "Register `REAL_TARGET2_LO` reader"] +pub type R = crate::R; +#[doc = "Field `TARGET2_LO_RO` reader - actual target value value low 32bits"] +pub type TARGET2_LO_RO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - actual target value value low 32bits"] + #[inline(always)] + pub fn target2_lo_ro(&self) -> TARGET2_LO_RO_R { + TARGET2_LO_RO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REAL_TARGET2_LO") + .field( + "target2_lo_ro", + &format_args!("{}", self.target2_lo_ro().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "system timer comp2 actual target value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`real_target2_lo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REAL_TARGET2_LO_SPEC; +impl crate::RegisterSpec for REAL_TARGET2_LO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`real_target2_lo::R`](R) reader structure"] +impl crate::Readable for REAL_TARGET2_LO_SPEC {} +#[doc = "`reset()` method sets REAL_TARGET2_LO to value 0"] +impl crate::Resettable for REAL_TARGET2_LO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/target0_conf.rs b/esp32p4/src/systimer/target0_conf.rs new file mode 100644 index 0000000000..5174d2c5c9 --- /dev/null +++ b/esp32p4/src/systimer/target0_conf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `TARGET0_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET0_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `TARGET0_PERIOD` reader - target0 period"] +pub type TARGET0_PERIOD_R = crate::FieldReader; +#[doc = "Field `TARGET0_PERIOD` writer - target0 period"] +pub type TARGET0_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>; +#[doc = "Field `TARGET0_PERIOD_MODE` reader - Set target0 to period mode"] +pub type TARGET0_PERIOD_MODE_R = crate::BitReader; +#[doc = "Field `TARGET0_PERIOD_MODE` writer - Set target0 to period mode"] +pub type TARGET0_PERIOD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET0_TIMER_UNIT_SEL` reader - select which unit to compare"] +pub type TARGET0_TIMER_UNIT_SEL_R = crate::BitReader; +#[doc = "Field `TARGET0_TIMER_UNIT_SEL` writer - select which unit to compare"] +pub type TARGET0_TIMER_UNIT_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:25 - target0 period"] + #[inline(always)] + pub fn target0_period(&self) -> TARGET0_PERIOD_R { + TARGET0_PERIOD_R::new(self.bits & 0x03ff_ffff) + } + #[doc = "Bit 30 - Set target0 to period mode"] + #[inline(always)] + pub fn target0_period_mode(&self) -> TARGET0_PERIOD_MODE_R { + TARGET0_PERIOD_MODE_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - select which unit to compare"] + #[inline(always)] + pub fn target0_timer_unit_sel(&self) -> TARGET0_TIMER_UNIT_SEL_R { + TARGET0_TIMER_UNIT_SEL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TARGET0_CONF") + .field( + "target0_period", + &format_args!("{}", self.target0_period().bits()), + ) + .field( + "target0_period_mode", + &format_args!("{}", self.target0_period_mode().bit()), + ) + .field( + "target0_timer_unit_sel", + &format_args!("{}", self.target0_timer_unit_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:25 - target0 period"] + #[inline(always)] + #[must_use] + pub fn target0_period(&mut self) -> TARGET0_PERIOD_W { + TARGET0_PERIOD_W::new(self, 0) + } + #[doc = "Bit 30 - Set target0 to period mode"] + #[inline(always)] + #[must_use] + pub fn target0_period_mode(&mut self) -> TARGET0_PERIOD_MODE_W { + TARGET0_PERIOD_MODE_W::new(self, 30) + } + #[doc = "Bit 31 - select which unit to compare"] + #[inline(always)] + #[must_use] + pub fn target0_timer_unit_sel(&mut self) -> TARGET0_TIMER_UNIT_SEL_W { + TARGET0_TIMER_UNIT_SEL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp0 target mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target0_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target0_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TARGET0_CONF_SPEC; +impl crate::RegisterSpec for TARGET0_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`target0_conf::R`](R) reader structure"] +impl crate::Readable for TARGET0_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`target0_conf::W`](W) writer structure"] +impl crate::Writable for TARGET0_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TARGET0_CONF to value 0"] +impl crate::Resettable for TARGET0_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/target0_hi.rs b/esp32p4/src/systimer/target0_hi.rs new file mode 100644 index 0000000000..cf7822ddb2 --- /dev/null +++ b/esp32p4/src/systimer/target0_hi.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TARGET0_HI` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET0_HI` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_TARGET0_HI` reader - timer taget0 high 20 bits"] +pub type TIMER_TARGET0_HI_R = crate::FieldReader; +#[doc = "Field `TIMER_TARGET0_HI` writer - timer taget0 high 20 bits"] +pub type TIMER_TARGET0_HI_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - timer taget0 high 20 bits"] + #[inline(always)] + pub fn timer_target0_hi(&self) -> TIMER_TARGET0_HI_R { + TIMER_TARGET0_HI_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TARGET0_HI") + .field( + "timer_target0_hi", + &format_args!("{}", self.timer_target0_hi().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - timer taget0 high 20 bits"] + #[inline(always)] + #[must_use] + pub fn timer_target0_hi(&mut self) -> TIMER_TARGET0_HI_W { + TIMER_TARGET0_HI_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp0 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target0_hi::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target0_hi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TARGET0_HI_SPEC; +impl crate::RegisterSpec for TARGET0_HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`target0_hi::R`](R) reader structure"] +impl crate::Readable for TARGET0_HI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`target0_hi::W`](W) writer structure"] +impl crate::Writable for TARGET0_HI_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TARGET0_HI to value 0"] +impl crate::Resettable for TARGET0_HI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/target0_lo.rs b/esp32p4/src/systimer/target0_lo.rs new file mode 100644 index 0000000000..3b5da5a976 --- /dev/null +++ b/esp32p4/src/systimer/target0_lo.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TARGET0_LO` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET0_LO` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_TARGET0_LO` reader - timer taget0 low 32 bits"] +pub type TIMER_TARGET0_LO_R = crate::FieldReader; +#[doc = "Field `TIMER_TARGET0_LO` writer - timer taget0 low 32 bits"] +pub type TIMER_TARGET0_LO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - timer taget0 low 32 bits"] + #[inline(always)] + pub fn timer_target0_lo(&self) -> TIMER_TARGET0_LO_R { + TIMER_TARGET0_LO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TARGET0_LO") + .field( + "timer_target0_lo", + &format_args!("{}", self.timer_target0_lo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - timer taget0 low 32 bits"] + #[inline(always)] + #[must_use] + pub fn timer_target0_lo(&mut self) -> TIMER_TARGET0_LO_W { + TIMER_TARGET0_LO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp0 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target0_lo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target0_lo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TARGET0_LO_SPEC; +impl crate::RegisterSpec for TARGET0_LO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`target0_lo::R`](R) reader structure"] +impl crate::Readable for TARGET0_LO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`target0_lo::W`](W) writer structure"] +impl crate::Writable for TARGET0_LO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TARGET0_LO to value 0"] +impl crate::Resettable for TARGET0_LO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/target1_conf.rs b/esp32p4/src/systimer/target1_conf.rs new file mode 100644 index 0000000000..1ee078b08f --- /dev/null +++ b/esp32p4/src/systimer/target1_conf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `TARGET1_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET1_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `TARGET1_PERIOD` reader - target1 period"] +pub type TARGET1_PERIOD_R = crate::FieldReader; +#[doc = "Field `TARGET1_PERIOD` writer - target1 period"] +pub type TARGET1_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>; +#[doc = "Field `TARGET1_PERIOD_MODE` reader - Set target1 to period mode"] +pub type TARGET1_PERIOD_MODE_R = crate::BitReader; +#[doc = "Field `TARGET1_PERIOD_MODE` writer - Set target1 to period mode"] +pub type TARGET1_PERIOD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET1_TIMER_UNIT_SEL` reader - select which unit to compare"] +pub type TARGET1_TIMER_UNIT_SEL_R = crate::BitReader; +#[doc = "Field `TARGET1_TIMER_UNIT_SEL` writer - select which unit to compare"] +pub type TARGET1_TIMER_UNIT_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:25 - target1 period"] + #[inline(always)] + pub fn target1_period(&self) -> TARGET1_PERIOD_R { + TARGET1_PERIOD_R::new(self.bits & 0x03ff_ffff) + } + #[doc = "Bit 30 - Set target1 to period mode"] + #[inline(always)] + pub fn target1_period_mode(&self) -> TARGET1_PERIOD_MODE_R { + TARGET1_PERIOD_MODE_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - select which unit to compare"] + #[inline(always)] + pub fn target1_timer_unit_sel(&self) -> TARGET1_TIMER_UNIT_SEL_R { + TARGET1_TIMER_UNIT_SEL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TARGET1_CONF") + .field( + "target1_period", + &format_args!("{}", self.target1_period().bits()), + ) + .field( + "target1_period_mode", + &format_args!("{}", self.target1_period_mode().bit()), + ) + .field( + "target1_timer_unit_sel", + &format_args!("{}", self.target1_timer_unit_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:25 - target1 period"] + #[inline(always)] + #[must_use] + pub fn target1_period(&mut self) -> TARGET1_PERIOD_W { + TARGET1_PERIOD_W::new(self, 0) + } + #[doc = "Bit 30 - Set target1 to period mode"] + #[inline(always)] + #[must_use] + pub fn target1_period_mode(&mut self) -> TARGET1_PERIOD_MODE_W { + TARGET1_PERIOD_MODE_W::new(self, 30) + } + #[doc = "Bit 31 - select which unit to compare"] + #[inline(always)] + #[must_use] + pub fn target1_timer_unit_sel(&mut self) -> TARGET1_TIMER_UNIT_SEL_W { + TARGET1_TIMER_UNIT_SEL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp1 target mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target1_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target1_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TARGET1_CONF_SPEC; +impl crate::RegisterSpec for TARGET1_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`target1_conf::R`](R) reader structure"] +impl crate::Readable for TARGET1_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`target1_conf::W`](W) writer structure"] +impl crate::Writable for TARGET1_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TARGET1_CONF to value 0"] +impl crate::Resettable for TARGET1_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/target1_hi.rs b/esp32p4/src/systimer/target1_hi.rs new file mode 100644 index 0000000000..1c37228878 --- /dev/null +++ b/esp32p4/src/systimer/target1_hi.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TARGET1_HI` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET1_HI` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_TARGET1_HI` reader - timer taget1 high 20 bits"] +pub type TIMER_TARGET1_HI_R = crate::FieldReader; +#[doc = "Field `TIMER_TARGET1_HI` writer - timer taget1 high 20 bits"] +pub type TIMER_TARGET1_HI_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - timer taget1 high 20 bits"] + #[inline(always)] + pub fn timer_target1_hi(&self) -> TIMER_TARGET1_HI_R { + TIMER_TARGET1_HI_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TARGET1_HI") + .field( + "timer_target1_hi", + &format_args!("{}", self.timer_target1_hi().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - timer taget1 high 20 bits"] + #[inline(always)] + #[must_use] + pub fn timer_target1_hi(&mut self) -> TIMER_TARGET1_HI_W { + TIMER_TARGET1_HI_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp1 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target1_hi::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target1_hi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TARGET1_HI_SPEC; +impl crate::RegisterSpec for TARGET1_HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`target1_hi::R`](R) reader structure"] +impl crate::Readable for TARGET1_HI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`target1_hi::W`](W) writer structure"] +impl crate::Writable for TARGET1_HI_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TARGET1_HI to value 0"] +impl crate::Resettable for TARGET1_HI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/target1_lo.rs b/esp32p4/src/systimer/target1_lo.rs new file mode 100644 index 0000000000..3900e2648a --- /dev/null +++ b/esp32p4/src/systimer/target1_lo.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TARGET1_LO` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET1_LO` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_TARGET1_LO` reader - timer taget1 low 32 bits"] +pub type TIMER_TARGET1_LO_R = crate::FieldReader; +#[doc = "Field `TIMER_TARGET1_LO` writer - timer taget1 low 32 bits"] +pub type TIMER_TARGET1_LO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - timer taget1 low 32 bits"] + #[inline(always)] + pub fn timer_target1_lo(&self) -> TIMER_TARGET1_LO_R { + TIMER_TARGET1_LO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TARGET1_LO") + .field( + "timer_target1_lo", + &format_args!("{}", self.timer_target1_lo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - timer taget1 low 32 bits"] + #[inline(always)] + #[must_use] + pub fn timer_target1_lo(&mut self) -> TIMER_TARGET1_LO_W { + TIMER_TARGET1_LO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp1 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target1_lo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target1_lo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TARGET1_LO_SPEC; +impl crate::RegisterSpec for TARGET1_LO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`target1_lo::R`](R) reader structure"] +impl crate::Readable for TARGET1_LO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`target1_lo::W`](W) writer structure"] +impl crate::Writable for TARGET1_LO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TARGET1_LO to value 0"] +impl crate::Resettable for TARGET1_LO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/target2_conf.rs b/esp32p4/src/systimer/target2_conf.rs new file mode 100644 index 0000000000..1aa6daaba9 --- /dev/null +++ b/esp32p4/src/systimer/target2_conf.rs @@ -0,0 +1,104 @@ +#[doc = "Register `TARGET2_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET2_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `TARGET2_PERIOD` reader - target2 period"] +pub type TARGET2_PERIOD_R = crate::FieldReader; +#[doc = "Field `TARGET2_PERIOD` writer - target2 period"] +pub type TARGET2_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>; +#[doc = "Field `TARGET2_PERIOD_MODE` reader - Set target2 to period mode"] +pub type TARGET2_PERIOD_MODE_R = crate::BitReader; +#[doc = "Field `TARGET2_PERIOD_MODE` writer - Set target2 to period mode"] +pub type TARGET2_PERIOD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TARGET2_TIMER_UNIT_SEL` reader - select which unit to compare"] +pub type TARGET2_TIMER_UNIT_SEL_R = crate::BitReader; +#[doc = "Field `TARGET2_TIMER_UNIT_SEL` writer - select which unit to compare"] +pub type TARGET2_TIMER_UNIT_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:25 - target2 period"] + #[inline(always)] + pub fn target2_period(&self) -> TARGET2_PERIOD_R { + TARGET2_PERIOD_R::new(self.bits & 0x03ff_ffff) + } + #[doc = "Bit 30 - Set target2 to period mode"] + #[inline(always)] + pub fn target2_period_mode(&self) -> TARGET2_PERIOD_MODE_R { + TARGET2_PERIOD_MODE_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - select which unit to compare"] + #[inline(always)] + pub fn target2_timer_unit_sel(&self) -> TARGET2_TIMER_UNIT_SEL_R { + TARGET2_TIMER_UNIT_SEL_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TARGET2_CONF") + .field( + "target2_period", + &format_args!("{}", self.target2_period().bits()), + ) + .field( + "target2_period_mode", + &format_args!("{}", self.target2_period_mode().bit()), + ) + .field( + "target2_timer_unit_sel", + &format_args!("{}", self.target2_timer_unit_sel().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:25 - target2 period"] + #[inline(always)] + #[must_use] + pub fn target2_period(&mut self) -> TARGET2_PERIOD_W { + TARGET2_PERIOD_W::new(self, 0) + } + #[doc = "Bit 30 - Set target2 to period mode"] + #[inline(always)] + #[must_use] + pub fn target2_period_mode(&mut self) -> TARGET2_PERIOD_MODE_W { + TARGET2_PERIOD_MODE_W::new(self, 30) + } + #[doc = "Bit 31 - select which unit to compare"] + #[inline(always)] + #[must_use] + pub fn target2_timer_unit_sel(&mut self) -> TARGET2_TIMER_UNIT_SEL_W { + TARGET2_TIMER_UNIT_SEL_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp2 target mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target2_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target2_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TARGET2_CONF_SPEC; +impl crate::RegisterSpec for TARGET2_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`target2_conf::R`](R) reader structure"] +impl crate::Readable for TARGET2_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`target2_conf::W`](W) writer structure"] +impl crate::Writable for TARGET2_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TARGET2_CONF to value 0"] +impl crate::Resettable for TARGET2_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/target2_hi.rs b/esp32p4/src/systimer/target2_hi.rs new file mode 100644 index 0000000000..e2f5314b6b --- /dev/null +++ b/esp32p4/src/systimer/target2_hi.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TARGET2_HI` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET2_HI` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_TARGET2_HI` reader - timer taget2 high 20 bits"] +pub type TIMER_TARGET2_HI_R = crate::FieldReader; +#[doc = "Field `TIMER_TARGET2_HI` writer - timer taget2 high 20 bits"] +pub type TIMER_TARGET2_HI_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - timer taget2 high 20 bits"] + #[inline(always)] + pub fn timer_target2_hi(&self) -> TIMER_TARGET2_HI_R { + TIMER_TARGET2_HI_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TARGET2_HI") + .field( + "timer_target2_hi", + &format_args!("{}", self.timer_target2_hi().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - timer taget2 high 20 bits"] + #[inline(always)] + #[must_use] + pub fn timer_target2_hi(&mut self) -> TIMER_TARGET2_HI_W { + TIMER_TARGET2_HI_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp2 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target2_hi::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target2_hi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TARGET2_HI_SPEC; +impl crate::RegisterSpec for TARGET2_HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`target2_hi::R`](R) reader structure"] +impl crate::Readable for TARGET2_HI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`target2_hi::W`](W) writer structure"] +impl crate::Writable for TARGET2_HI_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TARGET2_HI to value 0"] +impl crate::Resettable for TARGET2_HI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/target2_lo.rs b/esp32p4/src/systimer/target2_lo.rs new file mode 100644 index 0000000000..2ad291684a --- /dev/null +++ b/esp32p4/src/systimer/target2_lo.rs @@ -0,0 +1,66 @@ +#[doc = "Register `TARGET2_LO` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET2_LO` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_TARGET2_LO` reader - timer taget2 low 32 bits"] +pub type TIMER_TARGET2_LO_R = crate::FieldReader; +#[doc = "Field `TIMER_TARGET2_LO` writer - timer taget2 low 32 bits"] +pub type TIMER_TARGET2_LO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - timer taget2 low 32 bits"] + #[inline(always)] + pub fn timer_target2_lo(&self) -> TIMER_TARGET2_LO_R { + TIMER_TARGET2_LO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TARGET2_LO") + .field( + "timer_target2_lo", + &format_args!("{}", self.timer_target2_lo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - timer taget2 low 32 bits"] + #[inline(always)] + #[must_use] + pub fn timer_target2_lo(&mut self) -> TIMER_TARGET2_LO_W { + TIMER_TARGET2_LO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer comp2 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target2_lo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target2_lo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TARGET2_LO_SPEC; +impl crate::RegisterSpec for TARGET2_LO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`target2_lo::R`](R) reader structure"] +impl crate::Readable for TARGET2_LO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`target2_lo::W`](W) writer structure"] +impl crate::Writable for TARGET2_LO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TARGET2_LO to value 0"] +impl crate::Resettable for TARGET2_LO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit0_load.rs b/esp32p4/src/systimer/unit0_load.rs new file mode 100644 index 0000000000..7adbf07c01 --- /dev/null +++ b/esp32p4/src/systimer/unit0_load.rs @@ -0,0 +1,42 @@ +#[doc = "Register `UNIT0_LOAD` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_UNIT0_LOAD` writer - timer unit0 sync enable signal"] +pub type TIMER_UNIT0_LOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - timer unit0 sync enable signal"] + #[inline(always)] + #[must_use] + pub fn timer_unit0_load(&mut self) -> TIMER_UNIT0_LOAD_W { + TIMER_UNIT0_LOAD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer unit0 conf sync register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit0_load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT0_LOAD_SPEC; +impl crate::RegisterSpec for UNIT0_LOAD_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`unit0_load::W`](W) writer structure"] +impl crate::Writable for UNIT0_LOAD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UNIT0_LOAD to value 0"] +impl crate::Resettable for UNIT0_LOAD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit0_load_hi.rs b/esp32p4/src/systimer/unit0_load_hi.rs new file mode 100644 index 0000000000..1c60938406 --- /dev/null +++ b/esp32p4/src/systimer/unit0_load_hi.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UNIT0_LOAD_HI` reader"] +pub type R = crate::R; +#[doc = "Register `UNIT0_LOAD_HI` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_UNIT0_LOAD_HI` reader - timer unit0 load high 20 bits"] +pub type TIMER_UNIT0_LOAD_HI_R = crate::FieldReader; +#[doc = "Field `TIMER_UNIT0_LOAD_HI` writer - timer unit0 load high 20 bits"] +pub type TIMER_UNIT0_LOAD_HI_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - timer unit0 load high 20 bits"] + #[inline(always)] + pub fn timer_unit0_load_hi(&self) -> TIMER_UNIT0_LOAD_HI_R { + TIMER_UNIT0_LOAD_HI_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UNIT0_LOAD_HI") + .field( + "timer_unit0_load_hi", + &format_args!("{}", self.timer_unit0_load_hi().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - timer unit0 load high 20 bits"] + #[inline(always)] + #[must_use] + pub fn timer_unit0_load_hi(&mut self) -> TIMER_UNIT0_LOAD_HI_W { + TIMER_UNIT0_LOAD_HI_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer unit0 value high load register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit0_load_hi::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit0_load_hi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT0_LOAD_HI_SPEC; +impl crate::RegisterSpec for UNIT0_LOAD_HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`unit0_load_hi::R`](R) reader structure"] +impl crate::Readable for UNIT0_LOAD_HI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`unit0_load_hi::W`](W) writer structure"] +impl crate::Writable for UNIT0_LOAD_HI_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UNIT0_LOAD_HI to value 0"] +impl crate::Resettable for UNIT0_LOAD_HI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit0_load_lo.rs b/esp32p4/src/systimer/unit0_load_lo.rs new file mode 100644 index 0000000000..44b5f65d62 --- /dev/null +++ b/esp32p4/src/systimer/unit0_load_lo.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UNIT0_LOAD_LO` reader"] +pub type R = crate::R; +#[doc = "Register `UNIT0_LOAD_LO` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_UNIT0_LOAD_LO` reader - timer unit0 load low 32 bits"] +pub type TIMER_UNIT0_LOAD_LO_R = crate::FieldReader; +#[doc = "Field `TIMER_UNIT0_LOAD_LO` writer - timer unit0 load low 32 bits"] +pub type TIMER_UNIT0_LOAD_LO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - timer unit0 load low 32 bits"] + #[inline(always)] + pub fn timer_unit0_load_lo(&self) -> TIMER_UNIT0_LOAD_LO_R { + TIMER_UNIT0_LOAD_LO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UNIT0_LOAD_LO") + .field( + "timer_unit0_load_lo", + &format_args!("{}", self.timer_unit0_load_lo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - timer unit0 load low 32 bits"] + #[inline(always)] + #[must_use] + pub fn timer_unit0_load_lo(&mut self) -> TIMER_UNIT0_LOAD_LO_W { + TIMER_UNIT0_LOAD_LO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer unit0 value low load register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit0_load_lo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit0_load_lo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT0_LOAD_LO_SPEC; +impl crate::RegisterSpec for UNIT0_LOAD_LO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`unit0_load_lo::R`](R) reader structure"] +impl crate::Readable for UNIT0_LOAD_LO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`unit0_load_lo::W`](W) writer structure"] +impl crate::Writable for UNIT0_LOAD_LO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UNIT0_LOAD_LO to value 0"] +impl crate::Resettable for UNIT0_LOAD_LO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit0_op.rs b/esp32p4/src/systimer/unit0_op.rs new file mode 100644 index 0000000000..0972e43af3 --- /dev/null +++ b/esp32p4/src/systimer/unit0_op.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UNIT0_OP` reader"] +pub type R = crate::R; +#[doc = "Register `UNIT0_OP` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_UNIT0_VALUE_VALID` reader - timer value is sync and valid"] +pub type TIMER_UNIT0_VALUE_VALID_R = crate::BitReader; +#[doc = "Field `TIMER_UNIT0_UPDATE` writer - update timer_unit0"] +pub type TIMER_UNIT0_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 29 - timer value is sync and valid"] + #[inline(always)] + pub fn timer_unit0_value_valid(&self) -> TIMER_UNIT0_VALUE_VALID_R { + TIMER_UNIT0_VALUE_VALID_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UNIT0_OP") + .field( + "timer_unit0_value_valid", + &format_args!("{}", self.timer_unit0_value_valid().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - update timer_unit0"] + #[inline(always)] + #[must_use] + pub fn timer_unit0_update(&mut self) -> TIMER_UNIT0_UPDATE_W { + TIMER_UNIT0_UPDATE_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer unit0 value update register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit0_op::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit0_op::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT0_OP_SPEC; +impl crate::RegisterSpec for UNIT0_OP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`unit0_op::R`](R) reader structure"] +impl crate::Readable for UNIT0_OP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`unit0_op::W`](W) writer structure"] +impl crate::Writable for UNIT0_OP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UNIT0_OP to value 0"] +impl crate::Resettable for UNIT0_OP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit0_value_hi.rs b/esp32p4/src/systimer/unit0_value_hi.rs new file mode 100644 index 0000000000..7da7e6b9b9 --- /dev/null +++ b/esp32p4/src/systimer/unit0_value_hi.rs @@ -0,0 +1,39 @@ +#[doc = "Register `UNIT0_VALUE_HI` reader"] +pub type R = crate::R; +#[doc = "Field `TIMER_UNIT0_VALUE_HI` reader - timer read value high 20bits"] +pub type TIMER_UNIT0_VALUE_HI_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - timer read value high 20bits"] + #[inline(always)] + pub fn timer_unit0_value_hi(&self) -> TIMER_UNIT0_VALUE_HI_R { + TIMER_UNIT0_VALUE_HI_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UNIT0_VALUE_HI") + .field( + "timer_unit0_value_hi", + &format_args!("{}", self.timer_unit0_value_hi().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "system timer unit0 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit0_value_hi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT0_VALUE_HI_SPEC; +impl crate::RegisterSpec for UNIT0_VALUE_HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`unit0_value_hi::R`](R) reader structure"] +impl crate::Readable for UNIT0_VALUE_HI_SPEC {} +#[doc = "`reset()` method sets UNIT0_VALUE_HI to value 0"] +impl crate::Resettable for UNIT0_VALUE_HI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit0_value_lo.rs b/esp32p4/src/systimer/unit0_value_lo.rs new file mode 100644 index 0000000000..1c35d48422 --- /dev/null +++ b/esp32p4/src/systimer/unit0_value_lo.rs @@ -0,0 +1,39 @@ +#[doc = "Register `UNIT0_VALUE_LO` reader"] +pub type R = crate::R; +#[doc = "Field `TIMER_UNIT0_VALUE_LO` reader - timer read value low 32bits"] +pub type TIMER_UNIT0_VALUE_LO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - timer read value low 32bits"] + #[inline(always)] + pub fn timer_unit0_value_lo(&self) -> TIMER_UNIT0_VALUE_LO_R { + TIMER_UNIT0_VALUE_LO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UNIT0_VALUE_LO") + .field( + "timer_unit0_value_lo", + &format_args!("{}", self.timer_unit0_value_lo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "system timer unit0 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit0_value_lo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT0_VALUE_LO_SPEC; +impl crate::RegisterSpec for UNIT0_VALUE_LO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`unit0_value_lo::R`](R) reader structure"] +impl crate::Readable for UNIT0_VALUE_LO_SPEC {} +#[doc = "`reset()` method sets UNIT0_VALUE_LO to value 0"] +impl crate::Resettable for UNIT0_VALUE_LO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit1_load.rs b/esp32p4/src/systimer/unit1_load.rs new file mode 100644 index 0000000000..6b43c63b78 --- /dev/null +++ b/esp32p4/src/systimer/unit1_load.rs @@ -0,0 +1,42 @@ +#[doc = "Register `UNIT1_LOAD` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_UNIT1_LOAD` writer - timer unit1 sync enable signal"] +pub type TIMER_UNIT1_LOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - timer unit1 sync enable signal"] + #[inline(always)] + #[must_use] + pub fn timer_unit1_load(&mut self) -> TIMER_UNIT1_LOAD_W { + TIMER_UNIT1_LOAD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer unit1 conf sync register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit1_load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT1_LOAD_SPEC; +impl crate::RegisterSpec for UNIT1_LOAD_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`unit1_load::W`](W) writer structure"] +impl crate::Writable for UNIT1_LOAD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UNIT1_LOAD to value 0"] +impl crate::Resettable for UNIT1_LOAD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit1_load_hi.rs b/esp32p4/src/systimer/unit1_load_hi.rs new file mode 100644 index 0000000000..1add5caac6 --- /dev/null +++ b/esp32p4/src/systimer/unit1_load_hi.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UNIT1_LOAD_HI` reader"] +pub type R = crate::R; +#[doc = "Register `UNIT1_LOAD_HI` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_UNIT1_LOAD_HI` reader - timer unit1 load high 20 bits"] +pub type TIMER_UNIT1_LOAD_HI_R = crate::FieldReader; +#[doc = "Field `TIMER_UNIT1_LOAD_HI` writer - timer unit1 load high 20 bits"] +pub type TIMER_UNIT1_LOAD_HI_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19 - timer unit1 load high 20 bits"] + #[inline(always)] + pub fn timer_unit1_load_hi(&self) -> TIMER_UNIT1_LOAD_HI_R { + TIMER_UNIT1_LOAD_HI_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UNIT1_LOAD_HI") + .field( + "timer_unit1_load_hi", + &format_args!("{}", self.timer_unit1_load_hi().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:19 - timer unit1 load high 20 bits"] + #[inline(always)] + #[must_use] + pub fn timer_unit1_load_hi(&mut self) -> TIMER_UNIT1_LOAD_HI_W { + TIMER_UNIT1_LOAD_HI_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer unit1 value high load register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit1_load_hi::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit1_load_hi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT1_LOAD_HI_SPEC; +impl crate::RegisterSpec for UNIT1_LOAD_HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`unit1_load_hi::R`](R) reader structure"] +impl crate::Readable for UNIT1_LOAD_HI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`unit1_load_hi::W`](W) writer structure"] +impl crate::Writable for UNIT1_LOAD_HI_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UNIT1_LOAD_HI to value 0"] +impl crate::Resettable for UNIT1_LOAD_HI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit1_load_lo.rs b/esp32p4/src/systimer/unit1_load_lo.rs new file mode 100644 index 0000000000..f038898e58 --- /dev/null +++ b/esp32p4/src/systimer/unit1_load_lo.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UNIT1_LOAD_LO` reader"] +pub type R = crate::R; +#[doc = "Register `UNIT1_LOAD_LO` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_UNIT1_LOAD_LO` reader - timer unit1 load low 32 bits"] +pub type TIMER_UNIT1_LOAD_LO_R = crate::FieldReader; +#[doc = "Field `TIMER_UNIT1_LOAD_LO` writer - timer unit1 load low 32 bits"] +pub type TIMER_UNIT1_LOAD_LO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - timer unit1 load low 32 bits"] + #[inline(always)] + pub fn timer_unit1_load_lo(&self) -> TIMER_UNIT1_LOAD_LO_R { + TIMER_UNIT1_LOAD_LO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UNIT1_LOAD_LO") + .field( + "timer_unit1_load_lo", + &format_args!("{}", self.timer_unit1_load_lo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - timer unit1 load low 32 bits"] + #[inline(always)] + #[must_use] + pub fn timer_unit1_load_lo(&mut self) -> TIMER_UNIT1_LOAD_LO_W { + TIMER_UNIT1_LOAD_LO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer unit1 value low load register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit1_load_lo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit1_load_lo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT1_LOAD_LO_SPEC; +impl crate::RegisterSpec for UNIT1_LOAD_LO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`unit1_load_lo::R`](R) reader structure"] +impl crate::Readable for UNIT1_LOAD_LO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`unit1_load_lo::W`](W) writer structure"] +impl crate::Writable for UNIT1_LOAD_LO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UNIT1_LOAD_LO to value 0"] +impl crate::Resettable for UNIT1_LOAD_LO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit1_op.rs b/esp32p4/src/systimer/unit1_op.rs new file mode 100644 index 0000000000..d3f48c6053 --- /dev/null +++ b/esp32p4/src/systimer/unit1_op.rs @@ -0,0 +1,66 @@ +#[doc = "Register `UNIT1_OP` reader"] +pub type R = crate::R; +#[doc = "Register `UNIT1_OP` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER_UNIT1_VALUE_VALID` reader - timer value is sync and valid"] +pub type TIMER_UNIT1_VALUE_VALID_R = crate::BitReader; +#[doc = "Field `TIMER_UNIT1_UPDATE` writer - update timer unit1"] +pub type TIMER_UNIT1_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 29 - timer value is sync and valid"] + #[inline(always)] + pub fn timer_unit1_value_valid(&self) -> TIMER_UNIT1_VALUE_VALID_R { + TIMER_UNIT1_VALUE_VALID_R::new(((self.bits >> 29) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UNIT1_OP") + .field( + "timer_unit1_value_valid", + &format_args!("{}", self.timer_unit1_value_valid().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 30 - update timer unit1"] + #[inline(always)] + #[must_use] + pub fn timer_unit1_update(&mut self) -> TIMER_UNIT1_UPDATE_W { + TIMER_UNIT1_UPDATE_W::new(self, 30) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "system timer unit1 value update register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit1_op::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unit1_op::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT1_OP_SPEC; +impl crate::RegisterSpec for UNIT1_OP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`unit1_op::R`](R) reader structure"] +impl crate::Readable for UNIT1_OP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`unit1_op::W`](W) writer structure"] +impl crate::Writable for UNIT1_OP_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets UNIT1_OP to value 0"] +impl crate::Resettable for UNIT1_OP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit1_value_hi.rs b/esp32p4/src/systimer/unit1_value_hi.rs new file mode 100644 index 0000000000..3c59b093ef --- /dev/null +++ b/esp32p4/src/systimer/unit1_value_hi.rs @@ -0,0 +1,39 @@ +#[doc = "Register `UNIT1_VALUE_HI` reader"] +pub type R = crate::R; +#[doc = "Field `TIMER_UNIT1_VALUE_HI` reader - timer read value high 20bits"] +pub type TIMER_UNIT1_VALUE_HI_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - timer read value high 20bits"] + #[inline(always)] + pub fn timer_unit1_value_hi(&self) -> TIMER_UNIT1_VALUE_HI_R { + TIMER_UNIT1_VALUE_HI_R::new(self.bits & 0x000f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UNIT1_VALUE_HI") + .field( + "timer_unit1_value_hi", + &format_args!("{}", self.timer_unit1_value_hi().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "system timer unit1 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit1_value_hi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT1_VALUE_HI_SPEC; +impl crate::RegisterSpec for UNIT1_VALUE_HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`unit1_value_hi::R`](R) reader structure"] +impl crate::Readable for UNIT1_VALUE_HI_SPEC {} +#[doc = "`reset()` method sets UNIT1_VALUE_HI to value 0"] +impl crate::Resettable for UNIT1_VALUE_HI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/systimer/unit1_value_lo.rs b/esp32p4/src/systimer/unit1_value_lo.rs new file mode 100644 index 0000000000..f672b4b9f5 --- /dev/null +++ b/esp32p4/src/systimer/unit1_value_lo.rs @@ -0,0 +1,39 @@ +#[doc = "Register `UNIT1_VALUE_LO` reader"] +pub type R = crate::R; +#[doc = "Field `TIMER_UNIT1_VALUE_LO` reader - timer read value low 32bits"] +pub type TIMER_UNIT1_VALUE_LO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - timer read value low 32bits"] + #[inline(always)] + pub fn timer_unit1_value_lo(&self) -> TIMER_UNIT1_VALUE_LO_R { + TIMER_UNIT1_VALUE_LO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UNIT1_VALUE_LO") + .field( + "timer_unit1_value_lo", + &format_args!("{}", self.timer_unit1_value_lo().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "system timer unit1 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unit1_value_lo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UNIT1_VALUE_LO_SPEC; +impl crate::RegisterSpec for UNIT1_VALUE_LO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`unit1_value_lo::R`](R) reader structure"] +impl crate::Readable for UNIT1_VALUE_LO_SPEC {} +#[doc = "`reset()` method sets UNIT1_VALUE_LO to value 0"] +impl crate::Resettable for UNIT1_VALUE_LO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0.rs b/esp32p4/src/timg0.rs new file mode 100644 index 0000000000..f822b3b382 --- /dev/null +++ b/esp32p4/src/timg0.rs @@ -0,0 +1,269 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + t0config: T0CONFIG, + t0lo: T0LO, + t0hi: T0HI, + t0update: T0UPDATE, + t0alarmlo: T0ALARMLO, + t0alarmhi: T0ALARMHI, + t0loadlo: T0LOADLO, + t0loadhi: T0LOADHI, + t0load: T0LOAD, + _reserved9: [u8; 0x24], + wdtconfig0: WDTCONFIG0, + wdtconfig1: WDTCONFIG1, + wdtconfig2: WDTCONFIG2, + wdtconfig3: WDTCONFIG3, + wdtconfig4: WDTCONFIG4, + wdtconfig5: WDTCONFIG5, + wdtfeed: WDTFEED, + wdtwprotect: WDTWPROTECT, + rtccalicfg: RTCCALICFG, + rtccalicfg1: RTCCALICFG1, + int_ena_timers: INT_ENA_TIMERS, + int_raw_timers: INT_RAW_TIMERS, + int_st_timers: INT_ST_TIMERS, + int_clr_timers: INT_CLR_TIMERS, + rtccalicfg2: RTCCALICFG2, + _reserved24: [u8; 0x74], + ntimers_date: NTIMERS_DATE, + regclk: REGCLK, +} +impl RegisterBlock { + #[doc = "0x00 - Timer %s configuration register"] + #[inline(always)] + pub const fn t0config(&self) -> &T0CONFIG { + &self.t0config + } + #[doc = "0x04 - Timer %s current value, low 32 bits"] + #[inline(always)] + pub const fn t0lo(&self) -> &T0LO { + &self.t0lo + } + #[doc = "0x08 - Timer %s current value, high 22 bits"] + #[inline(always)] + pub const fn t0hi(&self) -> &T0HI { + &self.t0hi + } + #[doc = "0x0c - Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG"] + #[inline(always)] + pub const fn t0update(&self) -> &T0UPDATE { + &self.t0update + } + #[doc = "0x10 - Timer %s alarm value, low 32 bits"] + #[inline(always)] + pub const fn t0alarmlo(&self) -> &T0ALARMLO { + &self.t0alarmlo + } + #[doc = "0x14 - Timer %s alarm value, high bits"] + #[inline(always)] + pub const fn t0alarmhi(&self) -> &T0ALARMHI { + &self.t0alarmhi + } + #[doc = "0x18 - Timer %s reload value, low 32 bits"] + #[inline(always)] + pub const fn t0loadlo(&self) -> &T0LOADLO { + &self.t0loadlo + } + #[doc = "0x1c - Timer %s reload value, high 22 bits"] + #[inline(always)] + pub const fn t0loadhi(&self) -> &T0LOADHI { + &self.t0loadhi + } + #[doc = "0x20 - Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG"] + #[inline(always)] + pub const fn t0load(&self) -> &T0LOAD { + &self.t0load + } + #[doc = "0x48 - Watchdog timer configuration register"] + #[inline(always)] + pub const fn wdtconfig0(&self) -> &WDTCONFIG0 { + &self.wdtconfig0 + } + #[doc = "0x4c - Watchdog timer prescaler register"] + #[inline(always)] + pub const fn wdtconfig1(&self) -> &WDTCONFIG1 { + &self.wdtconfig1 + } + #[doc = "0x50 - Watchdog timer stage 0 timeout value"] + #[inline(always)] + pub const fn wdtconfig2(&self) -> &WDTCONFIG2 { + &self.wdtconfig2 + } + #[doc = "0x54 - Watchdog timer stage 1 timeout value"] + #[inline(always)] + pub const fn wdtconfig3(&self) -> &WDTCONFIG3 { + &self.wdtconfig3 + } + #[doc = "0x58 - Watchdog timer stage 2 timeout value"] + #[inline(always)] + pub const fn wdtconfig4(&self) -> &WDTCONFIG4 { + &self.wdtconfig4 + } + #[doc = "0x5c - Watchdog timer stage 3 timeout value"] + #[inline(always)] + pub const fn wdtconfig5(&self) -> &WDTCONFIG5 { + &self.wdtconfig5 + } + #[doc = "0x60 - Write to feed the watchdog timer"] + #[inline(always)] + pub const fn wdtfeed(&self) -> &WDTFEED { + &self.wdtfeed + } + #[doc = "0x64 - Watchdog write protect register"] + #[inline(always)] + pub const fn wdtwprotect(&self) -> &WDTWPROTECT { + &self.wdtwprotect + } + #[doc = "0x68 - RTC calibration configure register"] + #[inline(always)] + pub const fn rtccalicfg(&self) -> &RTCCALICFG { + &self.rtccalicfg + } + #[doc = "0x6c - RTC calibration configure1 register"] + #[inline(always)] + pub const fn rtccalicfg1(&self) -> &RTCCALICFG1 { + &self.rtccalicfg1 + } + #[doc = "0x70 - Interrupt enable bits"] + #[inline(always)] + pub const fn int_ena_timers(&self) -> &INT_ENA_TIMERS { + &self.int_ena_timers + } + #[doc = "0x74 - Raw interrupt status"] + #[inline(always)] + pub const fn int_raw_timers(&self) -> &INT_RAW_TIMERS { + &self.int_raw_timers + } + #[doc = "0x78 - Masked interrupt status"] + #[inline(always)] + pub const fn int_st_timers(&self) -> &INT_ST_TIMERS { + &self.int_st_timers + } + #[doc = "0x7c - Interrupt clear bits"] + #[inline(always)] + pub const fn int_clr_timers(&self) -> &INT_CLR_TIMERS { + &self.int_clr_timers + } + #[doc = "0x80 - Timer group calibration register"] + #[inline(always)] + pub const fn rtccalicfg2(&self) -> &RTCCALICFG2 { + &self.rtccalicfg2 + } + #[doc = "0xf8 - Timer version control register"] + #[inline(always)] + pub const fn ntimers_date(&self) -> &NTIMERS_DATE { + &self.ntimers_date + } + #[doc = "0xfc - Timer group clock gate register"] + #[inline(always)] + pub const fn regclk(&self) -> ®CLK { + &self.regclk + } +} +#[doc = "T0CONFIG (rw) register accessor: Timer %s configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0config`] module"] +pub type T0CONFIG = crate::Reg; +#[doc = "Timer %s configuration register"] +pub mod t0config; +#[doc = "T0LO (r) register accessor: Timer %s current value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0lo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0lo`] module"] +pub type T0LO = crate::Reg; +#[doc = "Timer %s current value, low 32 bits"] +pub mod t0lo; +#[doc = "T0HI (r) register accessor: Timer %s current value, high 22 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0hi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0hi`] module"] +pub type T0HI = crate::Reg; +#[doc = "Timer %s current value, high 22 bits"] +pub mod t0hi; +#[doc = "T0UPDATE (rw) register accessor: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0update::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0update::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0update`] module"] +pub type T0UPDATE = crate::Reg; +#[doc = "Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG"] +pub mod t0update; +#[doc = "T0ALARMLO (rw) register accessor: Timer %s alarm value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0alarmlo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0alarmlo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0alarmlo`] module"] +pub type T0ALARMLO = crate::Reg; +#[doc = "Timer %s alarm value, low 32 bits"] +pub mod t0alarmlo; +#[doc = "T0ALARMHI (rw) register accessor: Timer %s alarm value, high bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0alarmhi::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0alarmhi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0alarmhi`] module"] +pub type T0ALARMHI = crate::Reg; +#[doc = "Timer %s alarm value, high bits"] +pub mod t0alarmhi; +#[doc = "T0LOADLO (rw) register accessor: Timer %s reload value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0loadlo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0loadlo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0loadlo`] module"] +pub type T0LOADLO = crate::Reg; +#[doc = "Timer %s reload value, low 32 bits"] +pub mod t0loadlo; +#[doc = "T0LOADHI (rw) register accessor: Timer %s reload value, high 22 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0loadhi::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0loadhi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0loadhi`] module"] +pub type T0LOADHI = crate::Reg; +#[doc = "Timer %s reload value, high 22 bits"] +pub mod t0loadhi; +#[doc = "T0LOAD (w) register accessor: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0load::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0load`] module"] +pub type T0LOAD = crate::Reg; +#[doc = "Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG"] +pub mod t0load; +#[doc = "WDTCONFIG0 (rw) register accessor: Watchdog timer configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtconfig0`] module"] +pub type WDTCONFIG0 = crate::Reg; +#[doc = "Watchdog timer configuration register"] +pub mod wdtconfig0; +#[doc = "WDTCONFIG1 (rw) register accessor: Watchdog timer prescaler register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtconfig1`] module"] +pub type WDTCONFIG1 = crate::Reg; +#[doc = "Watchdog timer prescaler register"] +pub mod wdtconfig1; +#[doc = "WDTCONFIG2 (rw) register accessor: Watchdog timer stage 0 timeout value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtconfig2`] module"] +pub type WDTCONFIG2 = crate::Reg; +#[doc = "Watchdog timer stage 0 timeout value"] +pub mod wdtconfig2; +#[doc = "WDTCONFIG3 (rw) register accessor: Watchdog timer stage 1 timeout value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtconfig3`] module"] +pub type WDTCONFIG3 = crate::Reg; +#[doc = "Watchdog timer stage 1 timeout value"] +pub mod wdtconfig3; +#[doc = "WDTCONFIG4 (rw) register accessor: Watchdog timer stage 2 timeout value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtconfig4`] module"] +pub type WDTCONFIG4 = crate::Reg; +#[doc = "Watchdog timer stage 2 timeout value"] +pub mod wdtconfig4; +#[doc = "WDTCONFIG5 (rw) register accessor: Watchdog timer stage 3 timeout value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtconfig5`] module"] +pub type WDTCONFIG5 = crate::Reg; +#[doc = "Watchdog timer stage 3 timeout value"] +pub mod wdtconfig5; +#[doc = "WDTFEED (w) register accessor: Write to feed the watchdog timer\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtfeed::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtfeed`] module"] +pub type WDTFEED = crate::Reg; +#[doc = "Write to feed the watchdog timer"] +pub mod wdtfeed; +#[doc = "WDTWPROTECT (rw) register accessor: Watchdog write protect register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtwprotect::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtwprotect::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtwprotect`] module"] +pub type WDTWPROTECT = crate::Reg; +#[doc = "Watchdog write protect register"] +pub mod wdtwprotect; +#[doc = "RTCCALICFG (rw) register accessor: RTC calibration configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtccalicfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtccalicfg`] module"] +pub type RTCCALICFG = crate::Reg; +#[doc = "RTC calibration configure register"] +pub mod rtccalicfg; +#[doc = "RTCCALICFG1 (r) register accessor: RTC calibration configure1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtccalicfg1`] module"] +pub type RTCCALICFG1 = crate::Reg; +#[doc = "RTC calibration configure1 register"] +pub mod rtccalicfg1; +#[doc = "INT_ENA_TIMERS (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena_timers::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena_timers::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena_timers`] module"] +pub type INT_ENA_TIMERS = crate::Reg; +#[doc = "Interrupt enable bits"] +pub mod int_ena_timers; +#[doc = "INT_RAW_TIMERS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw_timers::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw_timers`] module"] +pub type INT_RAW_TIMERS = crate::Reg; +#[doc = "Raw interrupt status"] +pub mod int_raw_timers; +#[doc = "INT_ST_TIMERS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_timers::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_timers`] module"] +pub type INT_ST_TIMERS = crate::Reg; +#[doc = "Masked interrupt status"] +pub mod int_st_timers; +#[doc = "INT_CLR_TIMERS (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr_timers::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr_timers`] module"] +pub type INT_CLR_TIMERS = crate::Reg; +#[doc = "Interrupt clear bits"] +pub mod int_clr_timers; +#[doc = "RTCCALICFG2 (rw) register accessor: Timer group calibration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtccalicfg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtccalicfg2`] module"] +pub type RTCCALICFG2 = crate::Reg; +#[doc = "Timer group calibration register"] +pub mod rtccalicfg2; +#[doc = "NTIMERS_DATE (rw) register accessor: Timer version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ntimers_date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ntimers_date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ntimers_date`] module"] +pub type NTIMERS_DATE = crate::Reg; +#[doc = "Timer version control register"] +pub mod ntimers_date; +#[doc = "REGCLK (rw) register accessor: Timer group clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regclk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@regclk`] module"] +pub type REGCLK = crate::Reg; +#[doc = "Timer group clock gate register"] +pub mod regclk; diff --git a/esp32p4/src/timg0/int_clr_timers.rs b/esp32p4/src/timg0/int_clr_timers.rs new file mode 100644 index 0000000000..e9ec165f94 --- /dev/null +++ b/esp32p4/src/timg0/int_clr_timers.rs @@ -0,0 +1,58 @@ +#[doc = "Register `INT_CLR_TIMERS` writer"] +pub type W = crate::W; +#[doc = "Field `T0_INT_CLR` writer - Set this bit to clear the TIMG_T0_INT interrupt."] +pub type T0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `T1_INT_CLR` writer - Set this bit to clear the TIMG_T1_INT interrupt."] +pub type T1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_INT_CLR` writer - Set this bit to clear the TIMG_WDT_INT interrupt."] +pub type WDT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the TIMG_T0_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn t0_int_clr(&mut self) -> T0_INT_CLR_W { + T0_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the TIMG_T1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn t1_int_clr(&mut self) -> T1_INT_CLR_W { + T1_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the TIMG_WDT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn wdt_int_clr(&mut self) -> WDT_INT_CLR_W { + WDT_INT_CLR_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr_timers::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_TIMERS_SPEC; +impl crate::RegisterSpec for INT_CLR_TIMERS_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr_timers::W`](W) writer structure"] +impl crate::Writable for INT_CLR_TIMERS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR_TIMERS to value 0"] +impl crate::Resettable for INT_CLR_TIMERS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/int_ena_timers.rs b/esp32p4/src/timg0/int_ena_timers.rs new file mode 100644 index 0000000000..093732691a --- /dev/null +++ b/esp32p4/src/timg0/int_ena_timers.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INT_ENA_TIMERS` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA_TIMERS` writer"] +pub type W = crate::W; +#[doc = "Field `T0_INT_ENA` reader - The interrupt enable bit for the TIMG_T0_INT interrupt."] +pub type T0_INT_ENA_R = crate::BitReader; +#[doc = "Field `T0_INT_ENA` writer - The interrupt enable bit for the TIMG_T0_INT interrupt."] +pub type T0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `T1_INT_ENA` reader - The interrupt enable bit for the TIMG_T1_INT interrupt."] +pub type T1_INT_ENA_R = crate::BitReader; +#[doc = "Field `T1_INT_ENA` writer - The interrupt enable bit for the TIMG_T1_INT interrupt."] +pub type T1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_INT_ENA` reader - The interrupt enable bit for the TIMG_WDT_INT interrupt."] +pub type WDT_INT_ENA_R = crate::BitReader; +#[doc = "Field `WDT_INT_ENA` writer - The interrupt enable bit for the TIMG_WDT_INT interrupt."] +pub type WDT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the TIMG_T0_INT interrupt."] + #[inline(always)] + pub fn t0_int_ena(&self) -> T0_INT_ENA_R { + T0_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the TIMG_T1_INT interrupt."] + #[inline(always)] + pub fn t1_int_ena(&self) -> T1_INT_ENA_R { + T1_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the TIMG_WDT_INT interrupt."] + #[inline(always)] + pub fn wdt_int_ena(&self) -> WDT_INT_ENA_R { + WDT_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA_TIMERS") + .field("t0_int_ena", &format_args!("{}", self.t0_int_ena().bit())) + .field("t1_int_ena", &format_args!("{}", self.t1_int_ena().bit())) + .field("wdt_int_ena", &format_args!("{}", self.wdt_int_ena().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the TIMG_T0_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn t0_int_ena(&mut self) -> T0_INT_ENA_W { + T0_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the TIMG_T1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn t1_int_ena(&mut self) -> T1_INT_ENA_W { + T1_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the TIMG_WDT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn wdt_int_ena(&mut self) -> WDT_INT_ENA_W { + WDT_INT_ENA_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena_timers::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena_timers::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_TIMERS_SPEC; +impl crate::RegisterSpec for INT_ENA_TIMERS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena_timers::R`](R) reader structure"] +impl crate::Readable for INT_ENA_TIMERS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena_timers::W`](W) writer structure"] +impl crate::Writable for INT_ENA_TIMERS_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA_TIMERS to value 0"] +impl crate::Resettable for INT_ENA_TIMERS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/int_raw_timers.rs b/esp32p4/src/timg0/int_raw_timers.rs new file mode 100644 index 0000000000..2c588d623a --- /dev/null +++ b/esp32p4/src/timg0/int_raw_timers.rs @@ -0,0 +1,52 @@ +#[doc = "Register `INT_RAW_TIMERS` reader"] +pub type R = crate::R; +#[doc = "Field `T0_INT_RAW` reader - The raw interrupt status bit for the TIMG_T0_INT interrupt."] +pub type T0_INT_RAW_R = crate::BitReader; +#[doc = "Field `T1_INT_RAW` reader - The raw interrupt status bit for the TIMG_T1_INT interrupt."] +pub type T1_INT_RAW_R = crate::BitReader; +#[doc = "Field `WDT_INT_RAW` reader - The raw interrupt status bit for the TIMG_WDT_INT interrupt."] +pub type WDT_INT_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the TIMG_T0_INT interrupt."] + #[inline(always)] + pub fn t0_int_raw(&self) -> T0_INT_RAW_R { + T0_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the TIMG_T1_INT interrupt."] + #[inline(always)] + pub fn t1_int_raw(&self) -> T1_INT_RAW_R { + T1_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the TIMG_WDT_INT interrupt."] + #[inline(always)] + pub fn wdt_int_raw(&self) -> WDT_INT_RAW_R { + WDT_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW_TIMERS") + .field("t0_int_raw", &format_args!("{}", self.t0_int_raw().bit())) + .field("t1_int_raw", &format_args!("{}", self.t1_int_raw().bit())) + .field("wdt_int_raw", &format_args!("{}", self.wdt_int_raw().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw_timers::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_TIMERS_SPEC; +impl crate::RegisterSpec for INT_RAW_TIMERS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw_timers::R`](R) reader structure"] +impl crate::Readable for INT_RAW_TIMERS_SPEC {} +#[doc = "`reset()` method sets INT_RAW_TIMERS to value 0"] +impl crate::Resettable for INT_RAW_TIMERS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/int_st_timers.rs b/esp32p4/src/timg0/int_st_timers.rs new file mode 100644 index 0000000000..1e01d4d424 --- /dev/null +++ b/esp32p4/src/timg0/int_st_timers.rs @@ -0,0 +1,52 @@ +#[doc = "Register `INT_ST_TIMERS` reader"] +pub type R = crate::R; +#[doc = "Field `T0_INT_ST` reader - The masked interrupt status bit for the TIMG_T0_INT interrupt."] +pub type T0_INT_ST_R = crate::BitReader; +#[doc = "Field `T1_INT_ST` reader - The masked interrupt status bit for the TIMG_T1_INT interrupt."] +pub type T1_INT_ST_R = crate::BitReader; +#[doc = "Field `WDT_INT_ST` reader - The masked interrupt status bit for the TIMG_WDT_INT interrupt."] +pub type WDT_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The masked interrupt status bit for the TIMG_T0_INT interrupt."] + #[inline(always)] + pub fn t0_int_st(&self) -> T0_INT_ST_R { + T0_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The masked interrupt status bit for the TIMG_T1_INT interrupt."] + #[inline(always)] + pub fn t1_int_st(&self) -> T1_INT_ST_R { + T1_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The masked interrupt status bit for the TIMG_WDT_INT interrupt."] + #[inline(always)] + pub fn wdt_int_st(&self) -> WDT_INT_ST_R { + WDT_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST_TIMERS") + .field("t0_int_st", &format_args!("{}", self.t0_int_st().bit())) + .field("t1_int_st", &format_args!("{}", self.t1_int_st().bit())) + .field("wdt_int_st", &format_args!("{}", self.wdt_int_st().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_timers::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_TIMERS_SPEC; +impl crate::RegisterSpec for INT_ST_TIMERS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st_timers::R`](R) reader structure"] +impl crate::Readable for INT_ST_TIMERS_SPEC {} +#[doc = "`reset()` method sets INT_ST_TIMERS to value 0"] +impl crate::Resettable for INT_ST_TIMERS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/ntimers_date.rs b/esp32p4/src/timg0/ntimers_date.rs new file mode 100644 index 0000000000..c92b0ed283 --- /dev/null +++ b/esp32p4/src/timg0/ntimers_date.rs @@ -0,0 +1,66 @@ +#[doc = "Register `NTIMERS_DATE` reader"] +pub type R = crate::R; +#[doc = "Register `NTIMERS_DATE` writer"] +pub type W = crate::W; +#[doc = "Field `NTIMGS_DATE` reader - Timer version control register"] +pub type NTIMGS_DATE_R = crate::FieldReader; +#[doc = "Field `NTIMGS_DATE` writer - Timer version control register"] +pub type NTIMGS_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - Timer version control register"] + #[inline(always)] + pub fn ntimgs_date(&self) -> NTIMGS_DATE_R { + NTIMGS_DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NTIMERS_DATE") + .field( + "ntimgs_date", + &format_args!("{}", self.ntimgs_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - Timer version control register"] + #[inline(always)] + #[must_use] + pub fn ntimgs_date(&mut self) -> NTIMGS_DATE_W { + NTIMGS_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timer version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ntimers_date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ntimers_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NTIMERS_DATE_SPEC; +impl crate::RegisterSpec for NTIMERS_DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ntimers_date::R`](R) reader structure"] +impl crate::Readable for NTIMERS_DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ntimers_date::W`](W) writer structure"] +impl crate::Writable for NTIMERS_DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets NTIMERS_DATE to value 0x0220_9142"] +impl crate::Resettable for NTIMERS_DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_9142; +} diff --git a/esp32p4/src/timg0/regclk.rs b/esp32p4/src/timg0/regclk.rs new file mode 100644 index 0000000000..d3a845d4e4 --- /dev/null +++ b/esp32p4/src/timg0/regclk.rs @@ -0,0 +1,117 @@ +#[doc = "Register `REGCLK` reader"] +pub type R = crate::R; +#[doc = "Register `REGCLK` writer"] +pub type W = crate::W; +#[doc = "Field `ETM_EN` reader - enable timer's etm task and event"] +pub type ETM_EN_R = crate::BitReader; +#[doc = "Field `ETM_EN` writer - enable timer's etm task and event"] +pub type ETM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_CLK_IS_ACTIVE` reader - enable WDT's clock"] +pub type WDT_CLK_IS_ACTIVE_R = crate::BitReader; +#[doc = "Field `WDT_CLK_IS_ACTIVE` writer - enable WDT's clock"] +pub type WDT_CLK_IS_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER_CLK_IS_ACTIVE` reader - enable Timer 30's clock"] +pub type TIMER_CLK_IS_ACTIVE_R = crate::BitReader; +#[doc = "Field `TIMER_CLK_IS_ACTIVE` writer - enable Timer 30's clock"] +pub type TIMER_CLK_IS_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 28 - enable timer's etm task and event"] + #[inline(always)] + pub fn etm_en(&self) -> ETM_EN_R { + ETM_EN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - enable WDT's clock"] + #[inline(always)] + pub fn wdt_clk_is_active(&self) -> WDT_CLK_IS_ACTIVE_R { + WDT_CLK_IS_ACTIVE_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - enable Timer 30's clock"] + #[inline(always)] + pub fn timer_clk_is_active(&self) -> TIMER_CLK_IS_ACTIVE_R { + TIMER_CLK_IS_ACTIVE_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REGCLK") + .field("etm_en", &format_args!("{}", self.etm_en().bit())) + .field( + "wdt_clk_is_active", + &format_args!("{}", self.wdt_clk_is_active().bit()), + ) + .field( + "timer_clk_is_active", + &format_args!("{}", self.timer_clk_is_active().bit()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 28 - enable timer's etm task and event"] + #[inline(always)] + #[must_use] + pub fn etm_en(&mut self) -> ETM_EN_W { + ETM_EN_W::new(self, 28) + } + #[doc = "Bit 29 - enable WDT's clock"] + #[inline(always)] + #[must_use] + pub fn wdt_clk_is_active(&mut self) -> WDT_CLK_IS_ACTIVE_W { + WDT_CLK_IS_ACTIVE_W::new(self, 29) + } + #[doc = "Bit 30 - enable Timer 30's clock"] + #[inline(always)] + #[must_use] + pub fn timer_clk_is_active(&mut self) -> TIMER_CLK_IS_ACTIVE_W { + TIMER_CLK_IS_ACTIVE_W::new(self, 30) + } + #[doc = "Bit 31 - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timer group clock gate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regclk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regclk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REGCLK_SPEC; +impl crate::RegisterSpec for REGCLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`regclk::R`](R) reader structure"] +impl crate::Readable for REGCLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`regclk::W`](W) writer structure"] +impl crate::Writable for REGCLK_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REGCLK to value 0x7000_0000"] +impl crate::Resettable for REGCLK_SPEC { + const RESET_VALUE: Self::Ux = 0x7000_0000; +} diff --git a/esp32p4/src/timg0/rtccalicfg.rs b/esp32p4/src/timg0/rtccalicfg.rs new file mode 100644 index 0000000000..b748af888e --- /dev/null +++ b/esp32p4/src/timg0/rtccalicfg.rs @@ -0,0 +1,134 @@ +#[doc = "Register `RTCCALICFG` reader"] +pub type R = crate::R; +#[doc = "Register `RTCCALICFG` writer"] +pub type W = crate::W; +#[doc = "Field `RTC_CALI_START_CYCLING` reader - 0: one-shot frequency calculation,1: periodic frequency calculation,"] +pub type RTC_CALI_START_CYCLING_R = crate::BitReader; +#[doc = "Field `RTC_CALI_START_CYCLING` writer - 0: one-shot frequency calculation,1: periodic frequency calculation,"] +pub type RTC_CALI_START_CYCLING_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC_CALI_CLK_SEL` reader - 0:rtc slow clock. 1:clk_8m, 2:xtal_32k."] +pub type RTC_CALI_CLK_SEL_R = crate::FieldReader; +#[doc = "Field `RTC_CALI_CLK_SEL` writer - 0:rtc slow clock. 1:clk_8m, 2:xtal_32k."] +pub type RTC_CALI_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RTC_CALI_RDY` reader - indicate one-shot frequency calculation is done."] +pub type RTC_CALI_RDY_R = crate::BitReader; +#[doc = "Field `RTC_CALI_MAX` reader - Configure the time to calculate RTC slow clock's frequency."] +pub type RTC_CALI_MAX_R = crate::FieldReader; +#[doc = "Field `RTC_CALI_MAX` writer - Configure the time to calculate RTC slow clock's frequency."] +pub type RTC_CALI_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `RTC_CALI_START` reader - Set this bit to start one-shot frequency calculation."] +pub type RTC_CALI_START_R = crate::BitReader; +#[doc = "Field `RTC_CALI_START` writer - Set this bit to start one-shot frequency calculation."] +pub type RTC_CALI_START_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 12 - 0: one-shot frequency calculation,1: periodic frequency calculation,"] + #[inline(always)] + pub fn rtc_cali_start_cycling(&self) -> RTC_CALI_START_CYCLING_R { + RTC_CALI_START_CYCLING_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:14 - 0:rtc slow clock. 1:clk_8m, 2:xtal_32k."] + #[inline(always)] + pub fn rtc_cali_clk_sel(&self) -> RTC_CALI_CLK_SEL_R { + RTC_CALI_CLK_SEL_R::new(((self.bits >> 13) & 3) as u8) + } + #[doc = "Bit 15 - indicate one-shot frequency calculation is done."] + #[inline(always)] + pub fn rtc_cali_rdy(&self) -> RTC_CALI_RDY_R { + RTC_CALI_RDY_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:30 - Configure the time to calculate RTC slow clock's frequency."] + #[inline(always)] + pub fn rtc_cali_max(&self) -> RTC_CALI_MAX_R { + RTC_CALI_MAX_R::new(((self.bits >> 16) & 0x7fff) as u16) + } + #[doc = "Bit 31 - Set this bit to start one-shot frequency calculation."] + #[inline(always)] + pub fn rtc_cali_start(&self) -> RTC_CALI_START_R { + RTC_CALI_START_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTCCALICFG") + .field( + "rtc_cali_start_cycling", + &format_args!("{}", self.rtc_cali_start_cycling().bit()), + ) + .field( + "rtc_cali_clk_sel", + &format_args!("{}", self.rtc_cali_clk_sel().bits()), + ) + .field( + "rtc_cali_rdy", + &format_args!("{}", self.rtc_cali_rdy().bit()), + ) + .field( + "rtc_cali_max", + &format_args!("{}", self.rtc_cali_max().bits()), + ) + .field( + "rtc_cali_start", + &format_args!("{}", self.rtc_cali_start().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 12 - 0: one-shot frequency calculation,1: periodic frequency calculation,"] + #[inline(always)] + #[must_use] + pub fn rtc_cali_start_cycling(&mut self) -> RTC_CALI_START_CYCLING_W { + RTC_CALI_START_CYCLING_W::new(self, 12) + } + #[doc = "Bits 13:14 - 0:rtc slow clock. 1:clk_8m, 2:xtal_32k."] + #[inline(always)] + #[must_use] + pub fn rtc_cali_clk_sel(&mut self) -> RTC_CALI_CLK_SEL_W { + RTC_CALI_CLK_SEL_W::new(self, 13) + } + #[doc = "Bits 16:30 - Configure the time to calculate RTC slow clock's frequency."] + #[inline(always)] + #[must_use] + pub fn rtc_cali_max(&mut self) -> RTC_CALI_MAX_W { + RTC_CALI_MAX_W::new(self, 16) + } + #[doc = "Bit 31 - Set this bit to start one-shot frequency calculation."] + #[inline(always)] + #[must_use] + pub fn rtc_cali_start(&mut self) -> RTC_CALI_START_W { + RTC_CALI_START_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RTC calibration configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtccalicfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RTCCALICFG_SPEC; +impl crate::RegisterSpec for RTCCALICFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rtccalicfg::R`](R) reader structure"] +impl crate::Readable for RTCCALICFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rtccalicfg::W`](W) writer structure"] +impl crate::Writable for RTCCALICFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RTCCALICFG to value 0x0001_1000"] +impl crate::Resettable for RTCCALICFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_1000; +} diff --git a/esp32p4/src/timg0/rtccalicfg1.rs b/esp32p4/src/timg0/rtccalicfg1.rs new file mode 100644 index 0000000000..5a8e5e70af --- /dev/null +++ b/esp32p4/src/timg0/rtccalicfg1.rs @@ -0,0 +1,50 @@ +#[doc = "Register `RTCCALICFG1` reader"] +pub type R = crate::R; +#[doc = "Field `RTC_CALI_CYCLING_DATA_VLD` reader - indicate periodic frequency calculation is done."] +pub type RTC_CALI_CYCLING_DATA_VLD_R = crate::BitReader; +#[doc = "Field `RTC_CALI_VALUE` reader - When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency."] +pub type RTC_CALI_VALUE_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - indicate periodic frequency calculation is done."] + #[inline(always)] + pub fn rtc_cali_cycling_data_vld(&self) -> RTC_CALI_CYCLING_DATA_VLD_R { + RTC_CALI_CYCLING_DATA_VLD_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 7:31 - When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency."] + #[inline(always)] + pub fn rtc_cali_value(&self) -> RTC_CALI_VALUE_R { + RTC_CALI_VALUE_R::new((self.bits >> 7) & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTCCALICFG1") + .field( + "rtc_cali_cycling_data_vld", + &format_args!("{}", self.rtc_cali_cycling_data_vld().bit()), + ) + .field( + "rtc_cali_value", + &format_args!("{}", self.rtc_cali_value().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "RTC calibration configure1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RTCCALICFG1_SPEC; +impl crate::RegisterSpec for RTCCALICFG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rtccalicfg1::R`](R) reader structure"] +impl crate::Readable for RTCCALICFG1_SPEC {} +#[doc = "`reset()` method sets RTCCALICFG1 to value 0"] +impl crate::Resettable for RTCCALICFG1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/rtccalicfg2.rs b/esp32p4/src/timg0/rtccalicfg2.rs new file mode 100644 index 0000000000..1a88896f78 --- /dev/null +++ b/esp32p4/src/timg0/rtccalicfg2.rs @@ -0,0 +1,96 @@ +#[doc = "Register `RTCCALICFG2` reader"] +pub type R = crate::R; +#[doc = "Register `RTCCALICFG2` writer"] +pub type W = crate::W; +#[doc = "Field `RTC_CALI_TIMEOUT` reader - RTC calibration timeout indicator"] +pub type RTC_CALI_TIMEOUT_R = crate::BitReader; +#[doc = "Field `RTC_CALI_TIMEOUT_RST_CNT` reader - Cycles that release calibration timeout reset"] +pub type RTC_CALI_TIMEOUT_RST_CNT_R = crate::FieldReader; +#[doc = "Field `RTC_CALI_TIMEOUT_RST_CNT` writer - Cycles that release calibration timeout reset"] +pub type RTC_CALI_TIMEOUT_RST_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RTC_CALI_TIMEOUT_THRES` reader - Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered."] +pub type RTC_CALI_TIMEOUT_THRES_R = crate::FieldReader; +#[doc = "Field `RTC_CALI_TIMEOUT_THRES` writer - Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered."] +pub type RTC_CALI_TIMEOUT_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +impl R { + #[doc = "Bit 0 - RTC calibration timeout indicator"] + #[inline(always)] + pub fn rtc_cali_timeout(&self) -> RTC_CALI_TIMEOUT_R { + RTC_CALI_TIMEOUT_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 3:6 - Cycles that release calibration timeout reset"] + #[inline(always)] + pub fn rtc_cali_timeout_rst_cnt(&self) -> RTC_CALI_TIMEOUT_RST_CNT_R { + RTC_CALI_TIMEOUT_RST_CNT_R::new(((self.bits >> 3) & 0x0f) as u8) + } + #[doc = "Bits 7:31 - Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered."] + #[inline(always)] + pub fn rtc_cali_timeout_thres(&self) -> RTC_CALI_TIMEOUT_THRES_R { + RTC_CALI_TIMEOUT_THRES_R::new((self.bits >> 7) & 0x01ff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTCCALICFG2") + .field( + "rtc_cali_timeout", + &format_args!("{}", self.rtc_cali_timeout().bit()), + ) + .field( + "rtc_cali_timeout_rst_cnt", + &format_args!("{}", self.rtc_cali_timeout_rst_cnt().bits()), + ) + .field( + "rtc_cali_timeout_thres", + &format_args!("{}", self.rtc_cali_timeout_thres().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 3:6 - Cycles that release calibration timeout reset"] + #[inline(always)] + #[must_use] + pub fn rtc_cali_timeout_rst_cnt(&mut self) -> RTC_CALI_TIMEOUT_RST_CNT_W { + RTC_CALI_TIMEOUT_RST_CNT_W::new(self, 3) + } + #[doc = "Bits 7:31 - Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered."] + #[inline(always)] + #[must_use] + pub fn rtc_cali_timeout_thres(&mut self) -> RTC_CALI_TIMEOUT_THRES_W { + RTC_CALI_TIMEOUT_THRES_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timer group calibration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtccalicfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RTCCALICFG2_SPEC; +impl crate::RegisterSpec for RTCCALICFG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rtccalicfg2::R`](R) reader structure"] +impl crate::Readable for RTCCALICFG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rtccalicfg2::W`](W) writer structure"] +impl crate::Writable for RTCCALICFG2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RTCCALICFG2 to value 0xffff_ff98"] +impl crate::Resettable for RTCCALICFG2_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ff98; +} diff --git a/esp32p4/src/timg0/t0alarmhi.rs b/esp32p4/src/timg0/t0alarmhi.rs new file mode 100644 index 0000000000..23209d9e87 --- /dev/null +++ b/esp32p4/src/timg0/t0alarmhi.rs @@ -0,0 +1,63 @@ +#[doc = "Register `T0ALARMHI` reader"] +pub type R = crate::R; +#[doc = "Register `T0ALARMHI` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM_HI` reader - Timer %s alarm trigger time-base counter value, high 22 bits."] +pub type ALARM_HI_R = crate::FieldReader; +#[doc = "Field `ALARM_HI` writer - Timer %s alarm trigger time-base counter value, high 22 bits."] +pub type ALARM_HI_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 0:21 - Timer %s alarm trigger time-base counter value, high 22 bits."] + #[inline(always)] + pub fn alarm_hi(&self) -> ALARM_HI_R { + ALARM_HI_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T0ALARMHI") + .field("alarm_hi", &format_args!("{}", self.alarm_hi().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:21 - Timer %s alarm trigger time-base counter value, high 22 bits."] + #[inline(always)] + #[must_use] + pub fn alarm_hi(&mut self) -> ALARM_HI_W { + ALARM_HI_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timer %s alarm value, high bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0alarmhi::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0alarmhi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T0ALARMHI_SPEC; +impl crate::RegisterSpec for T0ALARMHI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t0alarmhi::R`](R) reader structure"] +impl crate::Readable for T0ALARMHI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`t0alarmhi::W`](W) writer structure"] +impl crate::Writable for T0ALARMHI_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets T0ALARMHI to value 0"] +impl crate::Resettable for T0ALARMHI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/t0alarmlo.rs b/esp32p4/src/timg0/t0alarmlo.rs new file mode 100644 index 0000000000..cb568f687a --- /dev/null +++ b/esp32p4/src/timg0/t0alarmlo.rs @@ -0,0 +1,63 @@ +#[doc = "Register `T0ALARMLO` reader"] +pub type R = crate::R; +#[doc = "Register `T0ALARMLO` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM_LO` reader - Timer %s alarm trigger time-base counter value, low 32 bits."] +pub type ALARM_LO_R = crate::FieldReader; +#[doc = "Field `ALARM_LO` writer - Timer %s alarm trigger time-base counter value, low 32 bits."] +pub type ALARM_LO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, low 32 bits."] + #[inline(always)] + pub fn alarm_lo(&self) -> ALARM_LO_R { + ALARM_LO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T0ALARMLO") + .field("alarm_lo", &format_args!("{}", self.alarm_lo().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, low 32 bits."] + #[inline(always)] + #[must_use] + pub fn alarm_lo(&mut self) -> ALARM_LO_W { + ALARM_LO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timer %s alarm value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0alarmlo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0alarmlo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T0ALARMLO_SPEC; +impl crate::RegisterSpec for T0ALARMLO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t0alarmlo::R`](R) reader structure"] +impl crate::Readable for T0ALARMLO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`t0alarmlo::W`](W) writer structure"] +impl crate::Writable for T0ALARMLO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets T0ALARMLO to value 0"] +impl crate::Resettable for T0ALARMLO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/t0config.rs b/esp32p4/src/timg0/t0config.rs new file mode 100644 index 0000000000..cb0b78fff5 --- /dev/null +++ b/esp32p4/src/timg0/t0config.rs @@ -0,0 +1,151 @@ +#[doc = "Register `T0CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `T0CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `USE_XTAL` reader - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."] +pub type USE_XTAL_R = crate::BitReader; +#[doc = "Field `USE_XTAL` writer - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."] +pub type USE_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALARM_EN` reader - When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs."] +pub type ALARM_EN_R = crate::BitReader; +#[doc = "Field `ALARM_EN` writer - When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs."] +pub type ALARM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIVCNT_RST` writer - When set, Timer %s 's clock divider counter will be reset."] +pub type DIVCNT_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIVIDER` reader - Timer %s clock (T%s_clk) prescaler value."] +pub type DIVIDER_R = crate::FieldReader; +#[doc = "Field `DIVIDER` writer - Timer %s clock (T%s_clk) prescaler value."] +pub type DIVIDER_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `AUTORELOAD` reader - When set, timer %s auto-reload at alarm is enabled."] +pub type AUTORELOAD_R = crate::BitReader; +#[doc = "Field `AUTORELOAD` writer - When set, timer %s auto-reload at alarm is enabled."] +pub type AUTORELOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCREASE` reader - When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement."] +pub type INCREASE_R = crate::BitReader; +#[doc = "Field `INCREASE` writer - When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement."] +pub type INCREASE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN` reader - When set, the timer %s time-base counter is enabled."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - When set, the timer %s time-base counter is enabled."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."] + #[inline(always)] + pub fn use_xtal(&self) -> USE_XTAL_R { + USE_XTAL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs."] + #[inline(always)] + pub fn alarm_en(&self) -> ALARM_EN_R { + ALARM_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 13:28 - Timer %s clock (T%s_clk) prescaler value."] + #[inline(always)] + pub fn divider(&self) -> DIVIDER_R { + DIVIDER_R::new(((self.bits >> 13) & 0xffff) as u16) + } + #[doc = "Bit 29 - When set, timer %s auto-reload at alarm is enabled."] + #[inline(always)] + pub fn autoreload(&self) -> AUTORELOAD_R { + AUTORELOAD_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement."] + #[inline(always)] + pub fn increase(&self) -> INCREASE_R { + INCREASE_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - When set, the timer %s time-base counter is enabled."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T0CONFIG") + .field("use_xtal", &format_args!("{}", self.use_xtal().bit())) + .field("alarm_en", &format_args!("{}", self.alarm_en().bit())) + .field("divider", &format_args!("{}", self.divider().bits())) + .field("autoreload", &format_args!("{}", self.autoreload().bit())) + .field("increase", &format_args!("{}", self.increase().bit())) + .field("en", &format_args!("{}", self.en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."] + #[inline(always)] + #[must_use] + pub fn use_xtal(&mut self) -> USE_XTAL_W { + USE_XTAL_W::new(self, 9) + } + #[doc = "Bit 10 - When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs."] + #[inline(always)] + #[must_use] + pub fn alarm_en(&mut self) -> ALARM_EN_W { + ALARM_EN_W::new(self, 10) + } + #[doc = "Bit 12 - When set, Timer %s 's clock divider counter will be reset."] + #[inline(always)] + #[must_use] + pub fn divcnt_rst(&mut self) -> DIVCNT_RST_W { + DIVCNT_RST_W::new(self, 12) + } + #[doc = "Bits 13:28 - Timer %s clock (T%s_clk) prescaler value."] + #[inline(always)] + #[must_use] + pub fn divider(&mut self) -> DIVIDER_W { + DIVIDER_W::new(self, 13) + } + #[doc = "Bit 29 - When set, timer %s auto-reload at alarm is enabled."] + #[inline(always)] + #[must_use] + pub fn autoreload(&mut self) -> AUTORELOAD_W { + AUTORELOAD_W::new(self, 29) + } + #[doc = "Bit 30 - When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement."] + #[inline(always)] + #[must_use] + pub fn increase(&mut self) -> INCREASE_W { + INCREASE_W::new(self, 30) + } + #[doc = "Bit 31 - When set, the timer %s time-base counter is enabled."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timer %s configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T0CONFIG_SPEC; +impl crate::RegisterSpec for T0CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t0config::R`](R) reader structure"] +impl crate::Readable for T0CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`t0config::W`](W) writer structure"] +impl crate::Writable for T0CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets T0CONFIG to value 0x6000_2000"] +impl crate::Resettable for T0CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0x6000_2000; +} diff --git a/esp32p4/src/timg0/t0hi.rs b/esp32p4/src/timg0/t0hi.rs new file mode 100644 index 0000000000..e2e8730544 --- /dev/null +++ b/esp32p4/src/timg0/t0hi.rs @@ -0,0 +1,36 @@ +#[doc = "Register `T0HI` reader"] +pub type R = crate::R; +#[doc = "Field `HI` reader - After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter of timer %s can be read here."] +pub type HI_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter of timer %s can be read here."] + #[inline(always)] + pub fn hi(&self) -> HI_R { + HI_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T0HI") + .field("hi", &format_args!("{}", self.hi().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Timer %s current value, high 22 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0hi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T0HI_SPEC; +impl crate::RegisterSpec for T0HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t0hi::R`](R) reader structure"] +impl crate::Readable for T0HI_SPEC {} +#[doc = "`reset()` method sets T0HI to value 0"] +impl crate::Resettable for T0HI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/t0lo.rs b/esp32p4/src/timg0/t0lo.rs new file mode 100644 index 0000000000..686dffe440 --- /dev/null +++ b/esp32p4/src/timg0/t0lo.rs @@ -0,0 +1,36 @@ +#[doc = "Register `T0LO` reader"] +pub type R = crate::R; +#[doc = "Field `LO` reader - After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter of timer %s can be read here."] +pub type LO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter of timer %s can be read here."] + #[inline(always)] + pub fn lo(&self) -> LO_R { + LO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T0LO") + .field("lo", &format_args!("{}", self.lo().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Timer %s current value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0lo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T0LO_SPEC; +impl crate::RegisterSpec for T0LO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t0lo::R`](R) reader structure"] +impl crate::Readable for T0LO_SPEC {} +#[doc = "`reset()` method sets T0LO to value 0"] +impl crate::Resettable for T0LO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/t0load.rs b/esp32p4/src/timg0/t0load.rs new file mode 100644 index 0000000000..d1a40b9502 --- /dev/null +++ b/esp32p4/src/timg0/t0load.rs @@ -0,0 +1,42 @@ +#[doc = "Register `T0LOAD` writer"] +pub type W = crate::W; +#[doc = "Field `LOAD` writer - Write any value to trigger a timer %s time-base counter reload."] +pub type LOAD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - Write any value to trigger a timer %s time-base counter reload."] + #[inline(always)] + #[must_use] + pub fn load(&mut self) -> LOAD_W { + LOAD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T0LOAD_SPEC; +impl crate::RegisterSpec for T0LOAD_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`t0load::W`](W) writer structure"] +impl crate::Writable for T0LOAD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets T0LOAD to value 0"] +impl crate::Resettable for T0LOAD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/t0loadhi.rs b/esp32p4/src/timg0/t0loadhi.rs new file mode 100644 index 0000000000..3c2f7b5262 --- /dev/null +++ b/esp32p4/src/timg0/t0loadhi.rs @@ -0,0 +1,63 @@ +#[doc = "Register `T0LOADHI` reader"] +pub type R = crate::R; +#[doc = "Register `T0LOADHI` writer"] +pub type W = crate::W; +#[doc = "Field `LOAD_HI` reader - High 22 bits of the value that a reload will load onto timer %s time-base counter."] +pub type LOAD_HI_R = crate::FieldReader; +#[doc = "Field `LOAD_HI` writer - High 22 bits of the value that a reload will load onto timer %s time-base counter."] +pub type LOAD_HI_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 0:21 - High 22 bits of the value that a reload will load onto timer %s time-base counter."] + #[inline(always)] + pub fn load_hi(&self) -> LOAD_HI_R { + LOAD_HI_R::new(self.bits & 0x003f_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T0LOADHI") + .field("load_hi", &format_args!("{}", self.load_hi().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:21 - High 22 bits of the value that a reload will load onto timer %s time-base counter."] + #[inline(always)] + #[must_use] + pub fn load_hi(&mut self) -> LOAD_HI_W { + LOAD_HI_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timer %s reload value, high 22 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0loadhi::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0loadhi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T0LOADHI_SPEC; +impl crate::RegisterSpec for T0LOADHI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t0loadhi::R`](R) reader structure"] +impl crate::Readable for T0LOADHI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`t0loadhi::W`](W) writer structure"] +impl crate::Writable for T0LOADHI_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets T0LOADHI to value 0"] +impl crate::Resettable for T0LOADHI_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/t0loadlo.rs b/esp32p4/src/timg0/t0loadlo.rs new file mode 100644 index 0000000000..db782aff54 --- /dev/null +++ b/esp32p4/src/timg0/t0loadlo.rs @@ -0,0 +1,63 @@ +#[doc = "Register `T0LOADLO` reader"] +pub type R = crate::R; +#[doc = "Register `T0LOADLO` writer"] +pub type W = crate::W; +#[doc = "Field `LOAD_LO` reader - Low 32 bits of the value that a reload will load onto timer %s time-base Counter."] +pub type LOAD_LO_R = crate::FieldReader; +#[doc = "Field `LOAD_LO` writer - Low 32 bits of the value that a reload will load onto timer %s time-base Counter."] +pub type LOAD_LO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Low 32 bits of the value that a reload will load onto timer %s time-base Counter."] + #[inline(always)] + pub fn load_lo(&self) -> LOAD_LO_R { + LOAD_LO_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T0LOADLO") + .field("load_lo", &format_args!("{}", self.load_lo().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Low 32 bits of the value that a reload will load onto timer %s time-base Counter."] + #[inline(always)] + #[must_use] + pub fn load_lo(&mut self) -> LOAD_LO_W { + LOAD_LO_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timer %s reload value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0loadlo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0loadlo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T0LOADLO_SPEC; +impl crate::RegisterSpec for T0LOADLO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t0loadlo::R`](R) reader structure"] +impl crate::Readable for T0LOADLO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`t0loadlo::W`](W) writer structure"] +impl crate::Writable for T0LOADLO_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets T0LOADLO to value 0"] +impl crate::Resettable for T0LOADLO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/t0update.rs b/esp32p4/src/timg0/t0update.rs new file mode 100644 index 0000000000..653bcbe1b3 --- /dev/null +++ b/esp32p4/src/timg0/t0update.rs @@ -0,0 +1,63 @@ +#[doc = "Register `T0UPDATE` reader"] +pub type R = crate::R; +#[doc = "Register `T0UPDATE` writer"] +pub type W = crate::W; +#[doc = "Field `UPDATE` reader - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."] +pub type UPDATE_R = crate::BitReader; +#[doc = "Field `UPDATE` writer - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."] +pub type UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 31 - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."] + #[inline(always)] + pub fn update(&self) -> UPDATE_R { + UPDATE_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("T0UPDATE") + .field("update", &format_args!("{}", self.update().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 31 - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."] + #[inline(always)] + #[must_use] + pub fn update(&mut self) -> UPDATE_W { + UPDATE_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0update::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0update::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct T0UPDATE_SPEC; +impl crate::RegisterSpec for T0UPDATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`t0update::R`](R) reader structure"] +impl crate::Readable for T0UPDATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`t0update::W`](W) writer structure"] +impl crate::Writable for T0UPDATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets T0UPDATE to value 0"] +impl crate::Resettable for T0UPDATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/wdtconfig0.rs b/esp32p4/src/timg0/wdtconfig0.rs new file mode 100644 index 0000000000..85c0ef3da5 --- /dev/null +++ b/esp32p4/src/timg0/wdtconfig0.rs @@ -0,0 +1,249 @@ +#[doc = "Register `WDTCONFIG0` reader"] +pub type R = crate::R; +#[doc = "Register `WDTCONFIG0` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_APPCPU_RESET_EN` reader - WDT reset CPU enable."] +pub type WDT_APPCPU_RESET_EN_R = crate::BitReader; +#[doc = "Field `WDT_APPCPU_RESET_EN` writer - WDT reset CPU enable."] +pub type WDT_APPCPU_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_PROCPU_RESET_EN` reader - WDT reset CPU enable."] +pub type WDT_PROCPU_RESET_EN_R = crate::BitReader; +#[doc = "Field `WDT_PROCPU_RESET_EN` writer - WDT reset CPU enable."] +pub type WDT_PROCPU_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_FLASHBOOT_MOD_EN` reader - When set, Flash boot protection is enabled."] +pub type WDT_FLASHBOOT_MOD_EN_R = crate::BitReader; +#[doc = "Field `WDT_FLASHBOOT_MOD_EN` writer - When set, Flash boot protection is enabled."] +pub type WDT_FLASHBOOT_MOD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_SYS_RESET_LENGTH` reader - System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us."] +pub type WDT_SYS_RESET_LENGTH_R = crate::FieldReader; +#[doc = "Field `WDT_SYS_RESET_LENGTH` writer - System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us."] +pub type WDT_SYS_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WDT_CPU_RESET_LENGTH` reader - CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us."] +pub type WDT_CPU_RESET_LENGTH_R = crate::FieldReader; +#[doc = "Field `WDT_CPU_RESET_LENGTH` writer - CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us."] +pub type WDT_CPU_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WDT_USE_XTAL` reader - choose WDT clock:0-apb_clk, 1-xtal_clk."] +pub type WDT_USE_XTAL_R = crate::BitReader; +#[doc = "Field `WDT_USE_XTAL` writer - choose WDT clock:0-apb_clk, 1-xtal_clk."] +pub type WDT_USE_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_CONF_UPDATE_EN` writer - update the WDT configuration registers"] +pub type WDT_CONF_UPDATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_STG3` reader - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] +pub type WDT_STG3_R = crate::FieldReader; +#[doc = "Field `WDT_STG3` writer - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] +pub type WDT_STG3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `WDT_STG2` reader - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] +pub type WDT_STG2_R = crate::FieldReader; +#[doc = "Field `WDT_STG2` writer - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] +pub type WDT_STG2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `WDT_STG1` reader - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] +pub type WDT_STG1_R = crate::FieldReader; +#[doc = "Field `WDT_STG1` writer - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] +pub type WDT_STG1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `WDT_STG0` reader - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] +pub type WDT_STG0_R = crate::FieldReader; +#[doc = "Field `WDT_STG0` writer - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] +pub type WDT_STG0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `WDT_EN` reader - When set, MWDT is enabled."] +pub type WDT_EN_R = crate::BitReader; +#[doc = "Field `WDT_EN` writer - When set, MWDT is enabled."] +pub type WDT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 12 - WDT reset CPU enable."] + #[inline(always)] + pub fn wdt_appcpu_reset_en(&self) -> WDT_APPCPU_RESET_EN_R { + WDT_APPCPU_RESET_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - WDT reset CPU enable."] + #[inline(always)] + pub fn wdt_procpu_reset_en(&self) -> WDT_PROCPU_RESET_EN_R { + WDT_PROCPU_RESET_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - When set, Flash boot protection is enabled."] + #[inline(always)] + pub fn wdt_flashboot_mod_en(&self) -> WDT_FLASHBOOT_MOD_EN_R { + WDT_FLASHBOOT_MOD_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 15:17 - System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us."] + #[inline(always)] + pub fn wdt_sys_reset_length(&self) -> WDT_SYS_RESET_LENGTH_R { + WDT_SYS_RESET_LENGTH_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us."] + #[inline(always)] + pub fn wdt_cpu_reset_length(&self) -> WDT_CPU_RESET_LENGTH_R { + WDT_CPU_RESET_LENGTH_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bit 21 - choose WDT clock:0-apb_clk, 1-xtal_clk."] + #[inline(always)] + pub fn wdt_use_xtal(&self) -> WDT_USE_XTAL_R { + WDT_USE_XTAL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bits 23:24 - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] + #[inline(always)] + pub fn wdt_stg3(&self) -> WDT_STG3_R { + WDT_STG3_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bits 25:26 - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] + #[inline(always)] + pub fn wdt_stg2(&self) -> WDT_STG2_R { + WDT_STG2_R::new(((self.bits >> 25) & 3) as u8) + } + #[doc = "Bits 27:28 - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] + #[inline(always)] + pub fn wdt_stg1(&self) -> WDT_STG1_R { + WDT_STG1_R::new(((self.bits >> 27) & 3) as u8) + } + #[doc = "Bits 29:30 - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] + #[inline(always)] + pub fn wdt_stg0(&self) -> WDT_STG0_R { + WDT_STG0_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - When set, MWDT is enabled."] + #[inline(always)] + pub fn wdt_en(&self) -> WDT_EN_R { + WDT_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDTCONFIG0") + .field( + "wdt_appcpu_reset_en", + &format_args!("{}", self.wdt_appcpu_reset_en().bit()), + ) + .field( + "wdt_procpu_reset_en", + &format_args!("{}", self.wdt_procpu_reset_en().bit()), + ) + .field( + "wdt_flashboot_mod_en", + &format_args!("{}", self.wdt_flashboot_mod_en().bit()), + ) + .field( + "wdt_sys_reset_length", + &format_args!("{}", self.wdt_sys_reset_length().bits()), + ) + .field( + "wdt_cpu_reset_length", + &format_args!("{}", self.wdt_cpu_reset_length().bits()), + ) + .field( + "wdt_use_xtal", + &format_args!("{}", self.wdt_use_xtal().bit()), + ) + .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits())) + .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits())) + .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits())) + .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits())) + .field("wdt_en", &format_args!("{}", self.wdt_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 12 - WDT reset CPU enable."] + #[inline(always)] + #[must_use] + pub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W { + WDT_APPCPU_RESET_EN_W::new(self, 12) + } + #[doc = "Bit 13 - WDT reset CPU enable."] + #[inline(always)] + #[must_use] + pub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W { + WDT_PROCPU_RESET_EN_W::new(self, 13) + } + #[doc = "Bit 14 - When set, Flash boot protection is enabled."] + #[inline(always)] + #[must_use] + pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W { + WDT_FLASHBOOT_MOD_EN_W::new(self, 14) + } + #[doc = "Bits 15:17 - System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us."] + #[inline(always)] + #[must_use] + pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W { + WDT_SYS_RESET_LENGTH_W::new(self, 15) + } + #[doc = "Bits 18:20 - CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us."] + #[inline(always)] + #[must_use] + pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W { + WDT_CPU_RESET_LENGTH_W::new(self, 18) + } + #[doc = "Bit 21 - choose WDT clock:0-apb_clk, 1-xtal_clk."] + #[inline(always)] + #[must_use] + pub fn wdt_use_xtal(&mut self) -> WDT_USE_XTAL_W { + WDT_USE_XTAL_W::new(self, 21) + } + #[doc = "Bit 22 - update the WDT configuration registers"] + #[inline(always)] + #[must_use] + pub fn wdt_conf_update_en(&mut self) -> WDT_CONF_UPDATE_EN_W { + WDT_CONF_UPDATE_EN_W::new(self, 22) + } + #[doc = "Bits 23:24 - Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] + #[inline(always)] + #[must_use] + pub fn wdt_stg3(&mut self) -> WDT_STG3_W { + WDT_STG3_W::new(self, 23) + } + #[doc = "Bits 25:26 - Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] + #[inline(always)] + #[must_use] + pub fn wdt_stg2(&mut self) -> WDT_STG2_W { + WDT_STG2_W::new(self, 25) + } + #[doc = "Bits 27:28 - Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] + #[inline(always)] + #[must_use] + pub fn wdt_stg1(&mut self) -> WDT_STG1_W { + WDT_STG1_W::new(self, 27) + } + #[doc = "Bits 29:30 - Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system."] + #[inline(always)] + #[must_use] + pub fn wdt_stg0(&mut self) -> WDT_STG0_W { + WDT_STG0_W::new(self, 29) + } + #[doc = "Bit 31 - When set, MWDT is enabled."] + #[inline(always)] + #[must_use] + pub fn wdt_en(&mut self) -> WDT_EN_W { + WDT_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Watchdog timer configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDTCONFIG0_SPEC; +impl crate::RegisterSpec for WDTCONFIG0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtconfig0::R`](R) reader structure"] +impl crate::Readable for WDTCONFIG0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdtconfig0::W`](W) writer structure"] +impl crate::Writable for WDTCONFIG0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WDTCONFIG0 to value 0x0004_c000"] +impl crate::Resettable for WDTCONFIG0_SPEC { + const RESET_VALUE: Self::Ux = 0x0004_c000; +} diff --git a/esp32p4/src/timg0/wdtconfig1.rs b/esp32p4/src/timg0/wdtconfig1.rs new file mode 100644 index 0000000000..08a867efbd --- /dev/null +++ b/esp32p4/src/timg0/wdtconfig1.rs @@ -0,0 +1,74 @@ +#[doc = "Register `WDTCONFIG1` reader"] +pub type R = crate::R; +#[doc = "Register `WDTCONFIG1` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_DIVCNT_RST` writer - When set, WDT 's clock divider counter will be reset."] +pub type WDT_DIVCNT_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDT_CLK_PRESCALE` reader - MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE."] +pub type WDT_CLK_PRESCALE_R = crate::FieldReader; +#[doc = "Field `WDT_CLK_PRESCALE` writer - MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE."] +pub type WDT_CLK_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 16:31 - MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE."] + #[inline(always)] + pub fn wdt_clk_prescale(&self) -> WDT_CLK_PRESCALE_R { + WDT_CLK_PRESCALE_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDTCONFIG1") + .field( + "wdt_clk_prescale", + &format_args!("{}", self.wdt_clk_prescale().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - When set, WDT 's clock divider counter will be reset."] + #[inline(always)] + #[must_use] + pub fn wdt_divcnt_rst(&mut self) -> WDT_DIVCNT_RST_W { + WDT_DIVCNT_RST_W::new(self, 0) + } + #[doc = "Bits 16:31 - MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE."] + #[inline(always)] + #[must_use] + pub fn wdt_clk_prescale(&mut self) -> WDT_CLK_PRESCALE_W { + WDT_CLK_PRESCALE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Watchdog timer prescaler register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDTCONFIG1_SPEC; +impl crate::RegisterSpec for WDTCONFIG1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtconfig1::R`](R) reader structure"] +impl crate::Readable for WDTCONFIG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdtconfig1::W`](W) writer structure"] +impl crate::Writable for WDTCONFIG1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WDTCONFIG1 to value 0x0001_0000"] +impl crate::Resettable for WDTCONFIG1_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0000; +} diff --git a/esp32p4/src/timg0/wdtconfig2.rs b/esp32p4/src/timg0/wdtconfig2.rs new file mode 100644 index 0000000000..d1a18e8ee6 --- /dev/null +++ b/esp32p4/src/timg0/wdtconfig2.rs @@ -0,0 +1,66 @@ +#[doc = "Register `WDTCONFIG2` reader"] +pub type R = crate::R; +#[doc = "Register `WDTCONFIG2` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_STG0_HOLD` reader - Stage 0 timeout value, in MWDT clock cycles."] +pub type WDT_STG0_HOLD_R = crate::FieldReader; +#[doc = "Field `WDT_STG0_HOLD` writer - Stage 0 timeout value, in MWDT clock cycles."] +pub type WDT_STG0_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Stage 0 timeout value, in MWDT clock cycles."] + #[inline(always)] + pub fn wdt_stg0_hold(&self) -> WDT_STG0_HOLD_R { + WDT_STG0_HOLD_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDTCONFIG2") + .field( + "wdt_stg0_hold", + &format_args!("{}", self.wdt_stg0_hold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Stage 0 timeout value, in MWDT clock cycles."] + #[inline(always)] + #[must_use] + pub fn wdt_stg0_hold(&mut self) -> WDT_STG0_HOLD_W { + WDT_STG0_HOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Watchdog timer stage 0 timeout value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDTCONFIG2_SPEC; +impl crate::RegisterSpec for WDTCONFIG2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtconfig2::R`](R) reader structure"] +impl crate::Readable for WDTCONFIG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdtconfig2::W`](W) writer structure"] +impl crate::Writable for WDTCONFIG2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WDTCONFIG2 to value 0x018c_ba80"] +impl crate::Resettable for WDTCONFIG2_SPEC { + const RESET_VALUE: Self::Ux = 0x018c_ba80; +} diff --git a/esp32p4/src/timg0/wdtconfig3.rs b/esp32p4/src/timg0/wdtconfig3.rs new file mode 100644 index 0000000000..854174ab09 --- /dev/null +++ b/esp32p4/src/timg0/wdtconfig3.rs @@ -0,0 +1,66 @@ +#[doc = "Register `WDTCONFIG3` reader"] +pub type R = crate::R; +#[doc = "Register `WDTCONFIG3` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_STG1_HOLD` reader - Stage 1 timeout value, in MWDT clock cycles."] +pub type WDT_STG1_HOLD_R = crate::FieldReader; +#[doc = "Field `WDT_STG1_HOLD` writer - Stage 1 timeout value, in MWDT clock cycles."] +pub type WDT_STG1_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Stage 1 timeout value, in MWDT clock cycles."] + #[inline(always)] + pub fn wdt_stg1_hold(&self) -> WDT_STG1_HOLD_R { + WDT_STG1_HOLD_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDTCONFIG3") + .field( + "wdt_stg1_hold", + &format_args!("{}", self.wdt_stg1_hold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Stage 1 timeout value, in MWDT clock cycles."] + #[inline(always)] + #[must_use] + pub fn wdt_stg1_hold(&mut self) -> WDT_STG1_HOLD_W { + WDT_STG1_HOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Watchdog timer stage 1 timeout value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDTCONFIG3_SPEC; +impl crate::RegisterSpec for WDTCONFIG3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtconfig3::R`](R) reader structure"] +impl crate::Readable for WDTCONFIG3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdtconfig3::W`](W) writer structure"] +impl crate::Writable for WDTCONFIG3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WDTCONFIG3 to value 0x07ff_ffff"] +impl crate::Resettable for WDTCONFIG3_SPEC { + const RESET_VALUE: Self::Ux = 0x07ff_ffff; +} diff --git a/esp32p4/src/timg0/wdtconfig4.rs b/esp32p4/src/timg0/wdtconfig4.rs new file mode 100644 index 0000000000..009cdceb1c --- /dev/null +++ b/esp32p4/src/timg0/wdtconfig4.rs @@ -0,0 +1,66 @@ +#[doc = "Register `WDTCONFIG4` reader"] +pub type R = crate::R; +#[doc = "Register `WDTCONFIG4` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_STG2_HOLD` reader - Stage 2 timeout value, in MWDT clock cycles."] +pub type WDT_STG2_HOLD_R = crate::FieldReader; +#[doc = "Field `WDT_STG2_HOLD` writer - Stage 2 timeout value, in MWDT clock cycles."] +pub type WDT_STG2_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Stage 2 timeout value, in MWDT clock cycles."] + #[inline(always)] + pub fn wdt_stg2_hold(&self) -> WDT_STG2_HOLD_R { + WDT_STG2_HOLD_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDTCONFIG4") + .field( + "wdt_stg2_hold", + &format_args!("{}", self.wdt_stg2_hold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Stage 2 timeout value, in MWDT clock cycles."] + #[inline(always)] + #[must_use] + pub fn wdt_stg2_hold(&mut self) -> WDT_STG2_HOLD_W { + WDT_STG2_HOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Watchdog timer stage 2 timeout value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDTCONFIG4_SPEC; +impl crate::RegisterSpec for WDTCONFIG4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtconfig4::R`](R) reader structure"] +impl crate::Readable for WDTCONFIG4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdtconfig4::W`](W) writer structure"] +impl crate::Writable for WDTCONFIG4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WDTCONFIG4 to value 0x000f_ffff"] +impl crate::Resettable for WDTCONFIG4_SPEC { + const RESET_VALUE: Self::Ux = 0x000f_ffff; +} diff --git a/esp32p4/src/timg0/wdtconfig5.rs b/esp32p4/src/timg0/wdtconfig5.rs new file mode 100644 index 0000000000..84d9ac5f40 --- /dev/null +++ b/esp32p4/src/timg0/wdtconfig5.rs @@ -0,0 +1,66 @@ +#[doc = "Register `WDTCONFIG5` reader"] +pub type R = crate::R; +#[doc = "Register `WDTCONFIG5` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_STG3_HOLD` reader - Stage 3 timeout value, in MWDT clock cycles."] +pub type WDT_STG3_HOLD_R = crate::FieldReader; +#[doc = "Field `WDT_STG3_HOLD` writer - Stage 3 timeout value, in MWDT clock cycles."] +pub type WDT_STG3_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Stage 3 timeout value, in MWDT clock cycles."] + #[inline(always)] + pub fn wdt_stg3_hold(&self) -> WDT_STG3_HOLD_R { + WDT_STG3_HOLD_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDTCONFIG5") + .field( + "wdt_stg3_hold", + &format_args!("{}", self.wdt_stg3_hold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Stage 3 timeout value, in MWDT clock cycles."] + #[inline(always)] + #[must_use] + pub fn wdt_stg3_hold(&mut self) -> WDT_STG3_HOLD_W { + WDT_STG3_HOLD_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Watchdog timer stage 3 timeout value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtconfig5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtconfig5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDTCONFIG5_SPEC; +impl crate::RegisterSpec for WDTCONFIG5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtconfig5::R`](R) reader structure"] +impl crate::Readable for WDTCONFIG5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdtconfig5::W`](W) writer structure"] +impl crate::Writable for WDTCONFIG5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WDTCONFIG5 to value 0x000f_ffff"] +impl crate::Resettable for WDTCONFIG5_SPEC { + const RESET_VALUE: Self::Ux = 0x000f_ffff; +} diff --git a/esp32p4/src/timg0/wdtfeed.rs b/esp32p4/src/timg0/wdtfeed.rs new file mode 100644 index 0000000000..672e19cd45 --- /dev/null +++ b/esp32p4/src/timg0/wdtfeed.rs @@ -0,0 +1,42 @@ +#[doc = "Register `WDTFEED` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_FEED` writer - Write any value to feed the MWDT. (WO)"] +pub type WDT_FEED_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bits 0:31 - Write any value to feed the MWDT. (WO)"] + #[inline(always)] + #[must_use] + pub fn wdt_feed(&mut self) -> WDT_FEED_W { + WDT_FEED_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Write to feed the watchdog timer\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtfeed::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDTFEED_SPEC; +impl crate::RegisterSpec for WDTFEED_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`wdtfeed::W`](W) writer structure"] +impl crate::Writable for WDTFEED_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WDTFEED to value 0"] +impl crate::Resettable for WDTFEED_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/timg0/wdtwprotect.rs b/esp32p4/src/timg0/wdtwprotect.rs new file mode 100644 index 0000000000..dbc49cd23c --- /dev/null +++ b/esp32p4/src/timg0/wdtwprotect.rs @@ -0,0 +1,63 @@ +#[doc = "Register `WDTWPROTECT` reader"] +pub type R = crate::R; +#[doc = "Register `WDTWPROTECT` writer"] +pub type W = crate::W; +#[doc = "Field `WDT_WKEY` reader - If the register contains a different value than its reset value, write protection is enabled."] +pub type WDT_WKEY_R = crate::FieldReader; +#[doc = "Field `WDT_WKEY` writer - If the register contains a different value than its reset value, write protection is enabled."] +pub type WDT_WKEY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - If the register contains a different value than its reset value, write protection is enabled."] + #[inline(always)] + pub fn wdt_wkey(&self) -> WDT_WKEY_R { + WDT_WKEY_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDTWPROTECT") + .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - If the register contains a different value than its reset value, write protection is enabled."] + #[inline(always)] + #[must_use] + pub fn wdt_wkey(&mut self) -> WDT_WKEY_W { + WDT_WKEY_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Watchdog write protect register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtwprotect::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtwprotect::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDTWPROTECT_SPEC; +impl crate::RegisterSpec for WDTWPROTECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtwprotect::R`](R) reader structure"] +impl crate::Readable for WDTWPROTECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdtwprotect::W`](W) writer structure"] +impl crate::Writable for WDTWPROTECT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WDTWPROTECT to value 0x50d8_3aa1"] +impl crate::Resettable for WDTWPROTECT_SPEC { + const RESET_VALUE: Self::Ux = 0x50d8_3aa1; +} diff --git a/esp32p4/src/trace0.rs b/esp32p4/src/trace0.rs new file mode 100644 index 0000000000..3b7a34ac5f --- /dev/null +++ b/esp32p4/src/trace0.rs @@ -0,0 +1,201 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + mem_start_addr: MEM_START_ADDR, + mem_end_addr: MEM_END_ADDR, + mem_current_addr: MEM_CURRENT_ADDR, + mem_addr_update: MEM_ADDR_UPDATE, + fifo_status: FIFO_STATUS, + intr_ena: INTR_ENA, + intr_raw: INTR_RAW, + intr_clr: INTR_CLR, + trigger: TRIGGER, + config: CONFIG, + filter_control: FILTER_CONTROL, + filter_match_control: FILTER_MATCH_CONTROL, + filter_comparator_control: FILTER_COMPARATOR_CONTROL, + filter_p_comparator_match: FILTER_P_COMPARATOR_MATCH, + filter_s_comparator_match: FILTER_S_COMPARATOR_MATCH, + resync_prolonged: RESYNC_PROLONGED, + ahb_config: AHB_CONFIG, + clock_gate: CLOCK_GATE, + _reserved18: [u8; 0x03b4], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - mem start addr"] + #[inline(always)] + pub const fn mem_start_addr(&self) -> &MEM_START_ADDR { + &self.mem_start_addr + } + #[doc = "0x04 - mem end addr"] + #[inline(always)] + pub const fn mem_end_addr(&self) -> &MEM_END_ADDR { + &self.mem_end_addr + } + #[doc = "0x08 - mem current addr"] + #[inline(always)] + pub const fn mem_current_addr(&self) -> &MEM_CURRENT_ADDR { + &self.mem_current_addr + } + #[doc = "0x0c - mem addr update"] + #[inline(always)] + pub const fn mem_addr_update(&self) -> &MEM_ADDR_UPDATE { + &self.mem_addr_update + } + #[doc = "0x10 - fifo status register"] + #[inline(always)] + pub const fn fifo_status(&self) -> &FIFO_STATUS { + &self.fifo_status + } + #[doc = "0x14 - interrupt enable register"] + #[inline(always)] + pub const fn intr_ena(&self) -> &INTR_ENA { + &self.intr_ena + } + #[doc = "0x18 - interrupt status register"] + #[inline(always)] + pub const fn intr_raw(&self) -> &INTR_RAW { + &self.intr_raw + } + #[doc = "0x1c - interrupt clear register"] + #[inline(always)] + pub const fn intr_clr(&self) -> &INTR_CLR { + &self.intr_clr + } + #[doc = "0x20 - trigger register"] + #[inline(always)] + pub const fn trigger(&self) -> &TRIGGER { + &self.trigger + } + #[doc = "0x24 - trace configuration register"] + #[inline(always)] + pub const fn config(&self) -> &CONFIG { + &self.config + } + #[doc = "0x28 - filter control register"] + #[inline(always)] + pub const fn filter_control(&self) -> &FILTER_CONTROL { + &self.filter_control + } + #[doc = "0x2c - filter match control register"] + #[inline(always)] + pub const fn filter_match_control(&self) -> &FILTER_MATCH_CONTROL { + &self.filter_match_control + } + #[doc = "0x30 - filter comparator match control register"] + #[inline(always)] + pub const fn filter_comparator_control(&self) -> &FILTER_COMPARATOR_CONTROL { + &self.filter_comparator_control + } + #[doc = "0x34 - primary comparator match value"] + #[inline(always)] + pub const fn filter_p_comparator_match(&self) -> &FILTER_P_COMPARATOR_MATCH { + &self.filter_p_comparator_match + } + #[doc = "0x38 - secondary comparator match value"] + #[inline(always)] + pub const fn filter_s_comparator_match(&self) -> &FILTER_S_COMPARATOR_MATCH { + &self.filter_s_comparator_match + } + #[doc = "0x3c - resync configuration register"] + #[inline(always)] + pub const fn resync_prolonged(&self) -> &RESYNC_PROLONGED { + &self.resync_prolonged + } + #[doc = "0x40 - AHB config register"] + #[inline(always)] + pub const fn ahb_config(&self) -> &AHB_CONFIG { + &self.ahb_config + } + #[doc = "0x44 - Clock gate control register"] + #[inline(always)] + pub const fn clock_gate(&self) -> &CLOCK_GATE { + &self.clock_gate + } + #[doc = "0x3fc - Version control register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "MEM_START_ADDR (rw) register accessor: mem start addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_start_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_start_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_start_addr`] module"] +pub type MEM_START_ADDR = crate::Reg; +#[doc = "mem start addr"] +pub mod mem_start_addr; +#[doc = "MEM_END_ADDR (rw) register accessor: mem end addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_end_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_end_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_end_addr`] module"] +pub type MEM_END_ADDR = crate::Reg; +#[doc = "mem end addr"] +pub mod mem_end_addr; +#[doc = "MEM_CURRENT_ADDR (r) register accessor: mem current addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_current_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_current_addr`] module"] +pub type MEM_CURRENT_ADDR = crate::Reg; +#[doc = "mem current addr"] +pub mod mem_current_addr; +#[doc = "MEM_ADDR_UPDATE (w) register accessor: mem addr update\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_addr_update::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_addr_update`] module"] +pub type MEM_ADDR_UPDATE = crate::Reg; +#[doc = "mem addr update"] +pub mod mem_addr_update; +#[doc = "FIFO_STATUS (r) register accessor: fifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_status`] module"] +pub type FIFO_STATUS = crate::Reg; +#[doc = "fifo status register"] +pub mod fifo_status; +#[doc = "INTR_ENA (rw) register accessor: interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_ena`] module"] +pub type INTR_ENA = crate::Reg; +#[doc = "interrupt enable register"] +pub mod intr_ena; +#[doc = "INTR_RAW (r) register accessor: interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_raw`] module"] +pub type INTR_RAW = crate::Reg; +#[doc = "interrupt status register"] +pub mod intr_raw; +#[doc = "INTR_CLR (w) register accessor: interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_clr`] module"] +pub type INTR_CLR = crate::Reg; +#[doc = "interrupt clear register"] +pub mod intr_clr; +#[doc = "TRIGGER (rw) register accessor: trigger register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trigger::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trigger::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigger`] module"] +pub type TRIGGER = crate::Reg; +#[doc = "trigger register"] +pub mod trigger; +#[doc = "CONFIG (rw) register accessor: trace configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] module"] +pub type CONFIG = crate::Reg; +#[doc = "trace configuration register"] +pub mod config; +#[doc = "FILTER_CONTROL (rw) register accessor: filter control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_control`] module"] +pub type FILTER_CONTROL = crate::Reg; +#[doc = "filter control register"] +pub mod filter_control; +#[doc = "FILTER_MATCH_CONTROL (rw) register accessor: filter match control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_match_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_match_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_match_control`] module"] +pub type FILTER_MATCH_CONTROL = crate::Reg; +#[doc = "filter match control register"] +pub mod filter_match_control; +#[doc = "FILTER_COMPARATOR_CONTROL (rw) register accessor: filter comparator match control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_comparator_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_comparator_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_comparator_control`] module"] +pub type FILTER_COMPARATOR_CONTROL = + crate::Reg; +#[doc = "filter comparator match control register"] +pub mod filter_comparator_control; +#[doc = "FILTER_P_COMPARATOR_MATCH (rw) register accessor: primary comparator match value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_p_comparator_match::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_p_comparator_match::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_p_comparator_match`] module"] +pub type FILTER_P_COMPARATOR_MATCH = + crate::Reg; +#[doc = "primary comparator match value"] +pub mod filter_p_comparator_match; +#[doc = "FILTER_S_COMPARATOR_MATCH (rw) register accessor: secondary comparator match value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_s_comparator_match::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_s_comparator_match::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filter_s_comparator_match`] module"] +pub type FILTER_S_COMPARATOR_MATCH = + crate::Reg; +#[doc = "secondary comparator match value"] +pub mod filter_s_comparator_match; +#[doc = "RESYNC_PROLONGED (rw) register accessor: resync configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resync_prolonged::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resync_prolonged::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resync_prolonged`] module"] +pub type RESYNC_PROLONGED = crate::Reg; +#[doc = "resync configuration register"] +pub mod resync_prolonged; +#[doc = "AHB_CONFIG (rw) register accessor: AHB config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_config`] module"] +pub type AHB_CONFIG = crate::Reg; +#[doc = "AHB config register"] +pub mod ahb_config; +#[doc = "CLOCK_GATE (rw) register accessor: Clock gate control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"] +pub type CLOCK_GATE = crate::Reg; +#[doc = "Clock gate control register"] +pub mod clock_gate; +#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Version control register"] +pub mod date; diff --git a/esp32p4/src/trace0/ahb_config.rs b/esp32p4/src/trace0/ahb_config.rs new file mode 100644 index 0000000000..3e6c82695e --- /dev/null +++ b/esp32p4/src/trace0/ahb_config.rs @@ -0,0 +1,79 @@ +#[doc = "Register `AHB_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `AHB_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `HBURST` reader - set hburst"] +pub type HBURST_R = crate::FieldReader; +#[doc = "Field `HBURST` writer - set hburst"] +pub type HBURST_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `MAX_INCR` reader - set max continuous access for incr mode"] +pub type MAX_INCR_R = crate::FieldReader; +#[doc = "Field `MAX_INCR` writer - set max continuous access for incr mode"] +pub type MAX_INCR_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - set hburst"] + #[inline(always)] + pub fn hburst(&self) -> HBURST_R { + HBURST_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - set max continuous access for incr mode"] + #[inline(always)] + pub fn max_incr(&self) -> MAX_INCR_R { + MAX_INCR_R::new(((self.bits >> 3) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AHB_CONFIG") + .field("hburst", &format_args!("{}", self.hburst().bits())) + .field("max_incr", &format_args!("{}", self.max_incr().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - set hburst"] + #[inline(always)] + #[must_use] + pub fn hburst(&mut self) -> HBURST_W { + HBURST_W::new(self, 0) + } + #[doc = "Bits 3:5 - set max continuous access for incr mode"] + #[inline(always)] + #[must_use] + pub fn max_incr(&mut self) -> MAX_INCR_W { + MAX_INCR_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AHB config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AHB_CONFIG_SPEC; +impl crate::RegisterSpec for AHB_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ahb_config::R`](R) reader structure"] +impl crate::Readable for AHB_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ahb_config::W`](W) writer structure"] +impl crate::Writable for AHB_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHB_CONFIG to value 0"] +impl crate::Resettable for AHB_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/clock_gate.rs b/esp32p4/src/trace0/clock_gate.rs new file mode 100644 index 0000000000..10334899eb --- /dev/null +++ b/esp32p4/src/trace0/clock_gate.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLOCK_GATE` reader"] +pub type R = crate::R; +#[doc = "Register `CLOCK_GATE` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_EN` reader - The bit is used to enable clock gate when access all registers in this module."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - The bit is used to enable clock gate when access all registers in this module."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The bit is used to enable clock gate when access all registers in this module."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCK_GATE") + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The bit is used to enable clock gate when access all registers in this module."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock gate control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLOCK_GATE_SPEC; +impl crate::RegisterSpec for CLOCK_GATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"] +impl crate::Readable for CLOCK_GATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"] +impl crate::Writable for CLOCK_GATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"] +impl crate::Resettable for CLOCK_GATE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/trace0/config.rs b/esp32p4/src/trace0/config.rs new file mode 100644 index 0000000000..70c3656b20 --- /dev/null +++ b/esp32p4/src/trace0/config.rs @@ -0,0 +1,152 @@ +#[doc = "Register `CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `DM_TRIGGER_ENA` reader - Configure whether or not enable cpu trigger action.\\\\1: enable\\\\0:disable\\\\"] +pub type DM_TRIGGER_ENA_R = crate::BitReader; +#[doc = "Field `DM_TRIGGER_ENA` writer - Configure whether or not enable cpu trigger action.\\\\1: enable\\\\0:disable\\\\"] +pub type DM_TRIGGER_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESET_ENA` reader - Configure whether or not enable trace cpu haverest, when enabeld, if cpu have reset, the encoder will output a packet to report the address of the last instruction, and upon reset deassertion, the encoder start again.\\\\1: enabeld\\\\0: disabled\\\\"] +pub type RESET_ENA_R = crate::BitReader; +#[doc = "Field `RESET_ENA` writer - Configure whether or not enable trace cpu haverest, when enabeld, if cpu have reset, the encoder will output a packet to report the address of the last instruction, and upon reset deassertion, the encoder start again.\\\\1: enabeld\\\\0: disabled\\\\"] +pub type RESET_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HALT_ENA` reader - Configure whether or not enable trace cpu is halted, when enabeld, if the cpu halted, the encoder will output a packet to report the address of the last instruction, and upon halted deassertion, the encoder start again.When disabled, encoder will not report the last address before halted and first address after halted, cpu halted information will not be tracked. \\\\1: enabeld\\\\0: disabled\\\\"] +pub type HALT_ENA_R = crate::BitReader; +#[doc = "Field `HALT_ENA` writer - Configure whether or not enable trace cpu is halted, when enabeld, if the cpu halted, the encoder will output a packet to report the address of the last instruction, and upon halted deassertion, the encoder start again.When disabled, encoder will not report the last address before halted and first address after halted, cpu halted information will not be tracked. \\\\1: enabeld\\\\0: disabled\\\\"] +pub type HALT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STALL_ENA` reader - Configure whether or not enable stall cpu. When enabled, when the fifo almost full, the cpu will be stalled until the packets is able to write to fifo.\\\\1: enabled.\\\\0: disabled\\\\"] +pub type STALL_ENA_R = crate::BitReader; +#[doc = "Field `STALL_ENA` writer - Configure whether or not enable stall cpu. When enabled, when the fifo almost full, the cpu will be stalled until the packets is able to write to fifo.\\\\1: enabled.\\\\0: disabled\\\\"] +pub type STALL_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FULL_ADDRESS` reader - Configure whether or not enable full-address mode.\\\\1: full address mode.\\\\0: delta address mode\\\\"] +pub type FULL_ADDRESS_R = crate::BitReader; +#[doc = "Field `FULL_ADDRESS` writer - Configure whether or not enable full-address mode.\\\\1: full address mode.\\\\0: delta address mode\\\\"] +pub type FULL_ADDRESS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IMPLICIT_EXCEPT` reader - Configure whether or not enabel implicit exception mode. When enabled,, do not sent exception address, only exception cause in exception packets.\\\\1: enabled\\\\0: disabled\\\\"] +pub type IMPLICIT_EXCEPT_R = crate::BitReader; +#[doc = "Field `IMPLICIT_EXCEPT` writer - Configure whether or not enabel implicit exception mode. When enabled,, do not sent exception address, only exception cause in exception packets.\\\\1: enabled\\\\0: disabled\\\\"] +pub type IMPLICIT_EXCEPT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configure whether or not enable cpu trigger action.\\\\1: enable\\\\0:disable\\\\"] + #[inline(always)] + pub fn dm_trigger_ena(&self) -> DM_TRIGGER_ENA_R { + DM_TRIGGER_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Configure whether or not enable trace cpu haverest, when enabeld, if cpu have reset, the encoder will output a packet to report the address of the last instruction, and upon reset deassertion, the encoder start again.\\\\1: enabeld\\\\0: disabled\\\\"] + #[inline(always)] + pub fn reset_ena(&self) -> RESET_ENA_R { + RESET_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Configure whether or not enable trace cpu is halted, when enabeld, if the cpu halted, the encoder will output a packet to report the address of the last instruction, and upon halted deassertion, the encoder start again.When disabled, encoder will not report the last address before halted and first address after halted, cpu halted information will not be tracked. \\\\1: enabeld\\\\0: disabled\\\\"] + #[inline(always)] + pub fn halt_ena(&self) -> HALT_ENA_R { + HALT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configure whether or not enable stall cpu. When enabled, when the fifo almost full, the cpu will be stalled until the packets is able to write to fifo.\\\\1: enabled.\\\\0: disabled\\\\"] + #[inline(always)] + pub fn stall_ena(&self) -> STALL_ENA_R { + STALL_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Configure whether or not enable full-address mode.\\\\1: full address mode.\\\\0: delta address mode\\\\"] + #[inline(always)] + pub fn full_address(&self) -> FULL_ADDRESS_R { + FULL_ADDRESS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Configure whether or not enabel implicit exception mode. When enabled,, do not sent exception address, only exception cause in exception packets.\\\\1: enabled\\\\0: disabled\\\\"] + #[inline(always)] + pub fn implicit_except(&self) -> IMPLICIT_EXCEPT_R { + IMPLICIT_EXCEPT_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONFIG") + .field( + "dm_trigger_ena", + &format_args!("{}", self.dm_trigger_ena().bit()), + ) + .field("reset_ena", &format_args!("{}", self.reset_ena().bit())) + .field("halt_ena", &format_args!("{}", self.halt_ena().bit())) + .field("stall_ena", &format_args!("{}", self.stall_ena().bit())) + .field( + "full_address", + &format_args!("{}", self.full_address().bit()), + ) + .field( + "implicit_except", + &format_args!("{}", self.implicit_except().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configure whether or not enable cpu trigger action.\\\\1: enable\\\\0:disable\\\\"] + #[inline(always)] + #[must_use] + pub fn dm_trigger_ena(&mut self) -> DM_TRIGGER_ENA_W { + DM_TRIGGER_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Configure whether or not enable trace cpu haverest, when enabeld, if cpu have reset, the encoder will output a packet to report the address of the last instruction, and upon reset deassertion, the encoder start again.\\\\1: enabeld\\\\0: disabled\\\\"] + #[inline(always)] + #[must_use] + pub fn reset_ena(&mut self) -> RESET_ENA_W { + RESET_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Configure whether or not enable trace cpu is halted, when enabeld, if the cpu halted, the encoder will output a packet to report the address of the last instruction, and upon halted deassertion, the encoder start again.When disabled, encoder will not report the last address before halted and first address after halted, cpu halted information will not be tracked. \\\\1: enabeld\\\\0: disabled\\\\"] + #[inline(always)] + #[must_use] + pub fn halt_ena(&mut self) -> HALT_ENA_W { + HALT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Configure whether or not enable stall cpu. When enabled, when the fifo almost full, the cpu will be stalled until the packets is able to write to fifo.\\\\1: enabled.\\\\0: disabled\\\\"] + #[inline(always)] + #[must_use] + pub fn stall_ena(&mut self) -> STALL_ENA_W { + STALL_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Configure whether or not enable full-address mode.\\\\1: full address mode.\\\\0: delta address mode\\\\"] + #[inline(always)] + #[must_use] + pub fn full_address(&mut self) -> FULL_ADDRESS_W { + FULL_ADDRESS_W::new(self, 4) + } + #[doc = "Bit 5 - Configure whether or not enabel implicit exception mode. When enabled,, do not sent exception address, only exception cause in exception packets.\\\\1: enabled\\\\0: disabled\\\\"] + #[inline(always)] + #[must_use] + pub fn implicit_except(&mut self) -> IMPLICIT_EXCEPT_W { + IMPLICIT_EXCEPT_W::new(self, 5) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "trace configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`config::R`](R) reader structure"] +impl crate::Readable for CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/date.rs b/esp32p4/src/trace0/date.rs new file mode 100644 index 0000000000..b42d580284 --- /dev/null +++ b/esp32p4/src/trace0/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - version control register. Note that this default value stored is the latest date when the hardware logic was updated."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - version control register. Note that this default value stored is the latest date when the hardware logic was updated."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +impl R { + #[doc = "Bits 0:27 - version control register. Note that this default value stored is the latest date when the hardware logic was updated."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits & 0x0fff_ffff) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:27 - version control register. Note that this default value stored is the latest date when the hardware logic was updated."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0221_1300"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0221_1300; +} diff --git a/esp32p4/src/trace0/fifo_status.rs b/esp32p4/src/trace0/fifo_status.rs new file mode 100644 index 0000000000..53e11059d2 --- /dev/null +++ b/esp32p4/src/trace0/fifo_status.rs @@ -0,0 +1,47 @@ +#[doc = "Register `FIFO_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_EMPTY` reader - Represent whether the fifo is empty. \\\\1: empty \\\\0: not empty"] +pub type FIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `WORK_STATUS` reader - Represent trace work status: \\\\0: idle state \\\\1: working state\\\\ 2: wait state due to hart halted or havereset \\\\3: lost state"] +pub type WORK_STATUS_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Represent whether the fifo is empty. \\\\1: empty \\\\0: not empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FIFO_EMPTY_R { + FIFO_EMPTY_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Represent trace work status: \\\\0: idle state \\\\1: working state\\\\ 2: wait state due to hart halted or havereset \\\\3: lost state"] + #[inline(always)] + pub fn work_status(&self) -> WORK_STATUS_R { + WORK_STATUS_R::new(((self.bits >> 1) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO_STATUS") + .field("fifo_empty", &format_args!("{}", self.fifo_empty().bit())) + .field( + "work_status", + &format_args!("{}", self.work_status().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "fifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_STATUS_SPEC; +impl crate::RegisterSpec for FIFO_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_status::R`](R) reader structure"] +impl crate::Readable for FIFO_STATUS_SPEC {} +#[doc = "`reset()` method sets FIFO_STATUS to value 0x01"] +impl crate::Resettable for FIFO_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/trace0/filter_comparator_control.rs b/esp32p4/src/trace0/filter_comparator_control.rs new file mode 100644 index 0000000000..1655da03e7 --- /dev/null +++ b/esp32p4/src/trace0/filter_comparator_control.rs @@ -0,0 +1,159 @@ +#[doc = "Register `FILTER_COMPARATOR_CONTROL` reader"] +pub type R = crate::R; +#[doc = "Register `FILTER_COMPARATOR_CONTROL` writer"] +pub type W = crate::W; +#[doc = "Field `P_INPUT` reader - Determines which input to compare against the primary comparator, \\\\0: iaddr, \\\\1: tval."] +pub type P_INPUT_R = crate::BitReader; +#[doc = "Field `P_INPUT` writer - Determines which input to compare against the primary comparator, \\\\0: iaddr, \\\\1: tval."] +pub type P_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `P_FUNCTION` reader - Select the primary comparator function. \\\\0: equal, \\\\1: not equal, \\\\2: less than, \\\\3: less than or equal, \\\\4: greater than, \\\\5: greater than or equal, \\\\other: always match"] +pub type P_FUNCTION_R = crate::FieldReader; +#[doc = "Field `P_FUNCTION` writer - Select the primary comparator function. \\\\0: equal, \\\\1: not equal, \\\\2: less than, \\\\3: less than or equal, \\\\4: greater than, \\\\5: greater than or equal, \\\\other: always match"] +pub type P_FUNCTION_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `P_NOTIFY` reader - Generate a trace packet explicitly reporting the address that cause the primary match"] +pub type P_NOTIFY_R = crate::BitReader; +#[doc = "Field `P_NOTIFY` writer - Generate a trace packet explicitly reporting the address that cause the primary match"] +pub type P_NOTIFY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S_INPUT` reader - Determines which input to compare against the secondary comparator, \\\\0: iaddr, \\\\1: tval."] +pub type S_INPUT_R = crate::BitReader; +#[doc = "Field `S_INPUT` writer - Determines which input to compare against the secondary comparator, \\\\0: iaddr, \\\\1: tval."] +pub type S_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S_FUNCTION` reader - Select the secondary comparator function. \\\\0: equal, \\\\1: not equal, \\\\2: less than, \\\\3: less than or equal, \\\\4: greater than, \\\\5: greater than or equal, \\\\other: always match"] +pub type S_FUNCTION_R = crate::FieldReader; +#[doc = "Field `S_FUNCTION` writer - Select the secondary comparator function. \\\\0: equal, \\\\1: not equal, \\\\2: less than, \\\\3: less than or equal, \\\\4: greater than, \\\\5: greater than or equal, \\\\other: always match"] +pub type S_FUNCTION_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `S_NOTIFY` reader - Generate a trace packet explicitly reporting the address that cause the secondary match"] +pub type S_NOTIFY_R = crate::BitReader; +#[doc = "Field `S_NOTIFY` writer - Generate a trace packet explicitly reporting the address that cause the secondary match"] +pub type S_NOTIFY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MATCH_MODE` reader - 0: only primary matches, \\\\1: primary and secondary comparator both matches(P\\&\\&S),\\\\ 2:either primary or secondary comparator matches !(P\\&\\&S), \\\\3: set when primary matches and continue to match until after secondary comparator matches"] +pub type MATCH_MODE_R = crate::FieldReader; +#[doc = "Field `MATCH_MODE` writer - 0: only primary matches, \\\\1: primary and secondary comparator both matches(P\\&\\&S),\\\\ 2:either primary or secondary comparator matches !(P\\&\\&S), \\\\3: set when primary matches and continue to match until after secondary comparator matches"] +pub type MATCH_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Determines which input to compare against the primary comparator, \\\\0: iaddr, \\\\1: tval."] + #[inline(always)] + pub fn p_input(&self) -> P_INPUT_R { + P_INPUT_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:4 - Select the primary comparator function. \\\\0: equal, \\\\1: not equal, \\\\2: less than, \\\\3: less than or equal, \\\\4: greater than, \\\\5: greater than or equal, \\\\other: always match"] + #[inline(always)] + pub fn p_function(&self) -> P_FUNCTION_R { + P_FUNCTION_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bit 5 - Generate a trace packet explicitly reporting the address that cause the primary match"] + #[inline(always)] + pub fn p_notify(&self) -> P_NOTIFY_R { + P_NOTIFY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Determines which input to compare against the secondary comparator, \\\\0: iaddr, \\\\1: tval."] + #[inline(always)] + pub fn s_input(&self) -> S_INPUT_R { + S_INPUT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 10:12 - Select the secondary comparator function. \\\\0: equal, \\\\1: not equal, \\\\2: less than, \\\\3: less than or equal, \\\\4: greater than, \\\\5: greater than or equal, \\\\other: always match"] + #[inline(always)] + pub fn s_function(&self) -> S_FUNCTION_R { + S_FUNCTION_R::new(((self.bits >> 10) & 7) as u8) + } + #[doc = "Bit 13 - Generate a trace packet explicitly reporting the address that cause the secondary match"] + #[inline(always)] + pub fn s_notify(&self) -> S_NOTIFY_R { + S_NOTIFY_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 16:17 - 0: only primary matches, \\\\1: primary and secondary comparator both matches(P\\&\\&S),\\\\ 2:either primary or secondary comparator matches !(P\\&\\&S), \\\\3: set when primary matches and continue to match until after secondary comparator matches"] + #[inline(always)] + pub fn match_mode(&self) -> MATCH_MODE_R { + MATCH_MODE_R::new(((self.bits >> 16) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FILTER_COMPARATOR_CONTROL") + .field("p_input", &format_args!("{}", self.p_input().bit())) + .field("p_function", &format_args!("{}", self.p_function().bits())) + .field("p_notify", &format_args!("{}", self.p_notify().bit())) + .field("s_input", &format_args!("{}", self.s_input().bit())) + .field("s_function", &format_args!("{}", self.s_function().bits())) + .field("s_notify", &format_args!("{}", self.s_notify().bit())) + .field("match_mode", &format_args!("{}", self.match_mode().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Determines which input to compare against the primary comparator, \\\\0: iaddr, \\\\1: tval."] + #[inline(always)] + #[must_use] + pub fn p_input(&mut self) -> P_INPUT_W { + P_INPUT_W::new(self, 0) + } + #[doc = "Bits 2:4 - Select the primary comparator function. \\\\0: equal, \\\\1: not equal, \\\\2: less than, \\\\3: less than or equal, \\\\4: greater than, \\\\5: greater than or equal, \\\\other: always match"] + #[inline(always)] + #[must_use] + pub fn p_function(&mut self) -> P_FUNCTION_W { + P_FUNCTION_W::new(self, 2) + } + #[doc = "Bit 5 - Generate a trace packet explicitly reporting the address that cause the primary match"] + #[inline(always)] + #[must_use] + pub fn p_notify(&mut self) -> P_NOTIFY_W { + P_NOTIFY_W::new(self, 5) + } + #[doc = "Bit 8 - Determines which input to compare against the secondary comparator, \\\\0: iaddr, \\\\1: tval."] + #[inline(always)] + #[must_use] + pub fn s_input(&mut self) -> S_INPUT_W { + S_INPUT_W::new(self, 8) + } + #[doc = "Bits 10:12 - Select the secondary comparator function. \\\\0: equal, \\\\1: not equal, \\\\2: less than, \\\\3: less than or equal, \\\\4: greater than, \\\\5: greater than or equal, \\\\other: always match"] + #[inline(always)] + #[must_use] + pub fn s_function(&mut self) -> S_FUNCTION_W { + S_FUNCTION_W::new(self, 10) + } + #[doc = "Bit 13 - Generate a trace packet explicitly reporting the address that cause the secondary match"] + #[inline(always)] + #[must_use] + pub fn s_notify(&mut self) -> S_NOTIFY_W { + S_NOTIFY_W::new(self, 13) + } + #[doc = "Bits 16:17 - 0: only primary matches, \\\\1: primary and secondary comparator both matches(P\\&\\&S),\\\\ 2:either primary or secondary comparator matches !(P\\&\\&S), \\\\3: set when primary matches and continue to match until after secondary comparator matches"] + #[inline(always)] + #[must_use] + pub fn match_mode(&mut self) -> MATCH_MODE_W { + MATCH_MODE_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "filter comparator match control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_comparator_control::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_comparator_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FILTER_COMPARATOR_CONTROL_SPEC; +impl crate::RegisterSpec for FILTER_COMPARATOR_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`filter_comparator_control::R`](R) reader structure"] +impl crate::Readable for FILTER_COMPARATOR_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`filter_comparator_control::W`](W) writer structure"] +impl crate::Writable for FILTER_COMPARATOR_CONTROL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FILTER_COMPARATOR_CONTROL to value 0"] +impl crate::Resettable for FILTER_COMPARATOR_CONTROL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/filter_control.rs b/esp32p4/src/trace0/filter_control.rs new file mode 100644 index 0000000000..86b14a7646 --- /dev/null +++ b/esp32p4/src/trace0/filter_control.rs @@ -0,0 +1,136 @@ +#[doc = "Register `FILTER_CONTROL` reader"] +pub type R = crate::R; +#[doc = "Register `FILTER_CONTROL` writer"] +pub type W = crate::W; +#[doc = "Field `FILTER_EN` reader - Configure whether or not enable filter unit. \\\\1: enable filter.\\\\ 0: always match"] +pub type FILTER_EN_R = crate::BitReader; +#[doc = "Field `FILTER_EN` writer - Configure whether or not enable filter unit. \\\\1: enable filter.\\\\ 0: always match"] +pub type FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MATCH_COMP` reader - when set, the comparator must be high in order for the filter to match"] +pub type MATCH_COMP_R = crate::BitReader; +#[doc = "Field `MATCH_COMP` writer - when set, the comparator must be high in order for the filter to match"] +pub type MATCH_COMP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MATCH_PRIVILEGE` reader - when set, match privilege levels specified by \\hyperref\\[fielddesc:TRACEMATCHCHOICEPRIVILEGE\\]{TRACE_MATCH_CHOICE_PRIVILEGE}."] +pub type MATCH_PRIVILEGE_R = crate::BitReader; +#[doc = "Field `MATCH_PRIVILEGE` writer - when set, match privilege levels specified by \\hyperref\\[fielddesc:TRACEMATCHCHOICEPRIVILEGE\\]{TRACE_MATCH_CHOICE_PRIVILEGE}."] +pub type MATCH_PRIVILEGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MATCH_ECAUSE` reader - when set, start matching from exception cause codes specified by \\hyperref\\[fielddesc:TRACEMATCHCHOICEECAUSE\\]{TRACE_MATCH_CHOICE_ECAUSE}, and stop matching upon return from the 1st matching exception."] +pub type MATCH_ECAUSE_R = crate::BitReader; +#[doc = "Field `MATCH_ECAUSE` writer - when set, start matching from exception cause codes specified by \\hyperref\\[fielddesc:TRACEMATCHCHOICEECAUSE\\]{TRACE_MATCH_CHOICE_ECAUSE}, and stop matching upon return from the 1st matching exception."] +pub type MATCH_ECAUSE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MATCH_INTERRUPT` reader - when set, start matching from a trap with the interrupt level codes specified by \\hyperref\\[fielddesc:TRACEMATCHVALUEINTERRUPT\\]{TRACE_MATCH_VALUE_INTERRUPT}, and stop matching upon return from the 1st matching trap."] +pub type MATCH_INTERRUPT_R = crate::BitReader; +#[doc = "Field `MATCH_INTERRUPT` writer - when set, start matching from a trap with the interrupt level codes specified by \\hyperref\\[fielddesc:TRACEMATCHVALUEINTERRUPT\\]{TRACE_MATCH_VALUE_INTERRUPT}, and stop matching upon return from the 1st matching trap."] +pub type MATCH_INTERRUPT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Configure whether or not enable filter unit. \\\\1: enable filter.\\\\ 0: always match"] + #[inline(always)] + pub fn filter_en(&self) -> FILTER_EN_R { + FILTER_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - when set, the comparator must be high in order for the filter to match"] + #[inline(always)] + pub fn match_comp(&self) -> MATCH_COMP_R { + MATCH_COMP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - when set, match privilege levels specified by \\hyperref\\[fielddesc:TRACEMATCHCHOICEPRIVILEGE\\]{TRACE_MATCH_CHOICE_PRIVILEGE}."] + #[inline(always)] + pub fn match_privilege(&self) -> MATCH_PRIVILEGE_R { + MATCH_PRIVILEGE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - when set, start matching from exception cause codes specified by \\hyperref\\[fielddesc:TRACEMATCHCHOICEECAUSE\\]{TRACE_MATCH_CHOICE_ECAUSE}, and stop matching upon return from the 1st matching exception."] + #[inline(always)] + pub fn match_ecause(&self) -> MATCH_ECAUSE_R { + MATCH_ECAUSE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - when set, start matching from a trap with the interrupt level codes specified by \\hyperref\\[fielddesc:TRACEMATCHVALUEINTERRUPT\\]{TRACE_MATCH_VALUE_INTERRUPT}, and stop matching upon return from the 1st matching trap."] + #[inline(always)] + pub fn match_interrupt(&self) -> MATCH_INTERRUPT_R { + MATCH_INTERRUPT_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FILTER_CONTROL") + .field("filter_en", &format_args!("{}", self.filter_en().bit())) + .field("match_comp", &format_args!("{}", self.match_comp().bit())) + .field( + "match_privilege", + &format_args!("{}", self.match_privilege().bit()), + ) + .field( + "match_ecause", + &format_args!("{}", self.match_ecause().bit()), + ) + .field( + "match_interrupt", + &format_args!("{}", self.match_interrupt().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configure whether or not enable filter unit. \\\\1: enable filter.\\\\ 0: always match"] + #[inline(always)] + #[must_use] + pub fn filter_en(&mut self) -> FILTER_EN_W { + FILTER_EN_W::new(self, 0) + } + #[doc = "Bit 1 - when set, the comparator must be high in order for the filter to match"] + #[inline(always)] + #[must_use] + pub fn match_comp(&mut self) -> MATCH_COMP_W { + MATCH_COMP_W::new(self, 1) + } + #[doc = "Bit 2 - when set, match privilege levels specified by \\hyperref\\[fielddesc:TRACEMATCHCHOICEPRIVILEGE\\]{TRACE_MATCH_CHOICE_PRIVILEGE}."] + #[inline(always)] + #[must_use] + pub fn match_privilege(&mut self) -> MATCH_PRIVILEGE_W { + MATCH_PRIVILEGE_W::new(self, 2) + } + #[doc = "Bit 3 - when set, start matching from exception cause codes specified by \\hyperref\\[fielddesc:TRACEMATCHCHOICEECAUSE\\]{TRACE_MATCH_CHOICE_ECAUSE}, and stop matching upon return from the 1st matching exception."] + #[inline(always)] + #[must_use] + pub fn match_ecause(&mut self) -> MATCH_ECAUSE_W { + MATCH_ECAUSE_W::new(self, 3) + } + #[doc = "Bit 4 - when set, start matching from a trap with the interrupt level codes specified by \\hyperref\\[fielddesc:TRACEMATCHVALUEINTERRUPT\\]{TRACE_MATCH_VALUE_INTERRUPT}, and stop matching upon return from the 1st matching trap."] + #[inline(always)] + #[must_use] + pub fn match_interrupt(&mut self) -> MATCH_INTERRUPT_W { + MATCH_INTERRUPT_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "filter control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_control::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FILTER_CONTROL_SPEC; +impl crate::RegisterSpec for FILTER_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`filter_control::R`](R) reader structure"] +impl crate::Readable for FILTER_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`filter_control::W`](W) writer structure"] +impl crate::Writable for FILTER_CONTROL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FILTER_CONTROL to value 0"] +impl crate::Resettable for FILTER_CONTROL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/filter_match_control.rs b/esp32p4/src/trace0/filter_match_control.rs new file mode 100644 index 0000000000..7b79d7510a --- /dev/null +++ b/esp32p4/src/trace0/filter_match_control.rs @@ -0,0 +1,106 @@ +#[doc = "Register `FILTER_MATCH_CONTROL` reader"] +pub type R = crate::R; +#[doc = "Register `FILTER_MATCH_CONTROL` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH_CHOICE_PRIVILEGE` reader - Select match which privilege level when \\hyperref\\[fielddesc:TRACEMATCHPRIVILEGE\\]{TRACE_MATCH_PRIVILEGE} is set. \\\\1: machine mode. \\\\0: user mode"] +pub type MATCH_CHOICE_PRIVILEGE_R = crate::BitReader; +#[doc = "Field `MATCH_CHOICE_PRIVILEGE` writer - Select match which privilege level when \\hyperref\\[fielddesc:TRACEMATCHPRIVILEGE\\]{TRACE_MATCH_PRIVILEGE} is set. \\\\1: machine mode. \\\\0: user mode"] +pub type MATCH_CHOICE_PRIVILEGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MATCH_VALUE_INTERRUPT` reader - Select which match which itype when \\hyperref\\[fielddesc:TRACEMATCHINTERRUPT\\]{TRACE_MATCH_INTERRUP} is set. \\\\1: match itype of 2. \\\\0: match itype or 1."] +pub type MATCH_VALUE_INTERRUPT_R = crate::BitReader; +#[doc = "Field `MATCH_VALUE_INTERRUPT` writer - Select which match which itype when \\hyperref\\[fielddesc:TRACEMATCHINTERRUPT\\]{TRACE_MATCH_INTERRUP} is set. \\\\1: match itype of 2. \\\\0: match itype or 1."] +pub type MATCH_VALUE_INTERRUPT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MATCH_CHOICE_ECAUSE` reader - specified which ecause matched."] +pub type MATCH_CHOICE_ECAUSE_R = crate::FieldReader; +#[doc = "Field `MATCH_CHOICE_ECAUSE` writer - specified which ecause matched."] +pub type MATCH_CHOICE_ECAUSE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Select match which privilege level when \\hyperref\\[fielddesc:TRACEMATCHPRIVILEGE\\]{TRACE_MATCH_PRIVILEGE} is set. \\\\1: machine mode. \\\\0: user mode"] + #[inline(always)] + pub fn match_choice_privilege(&self) -> MATCH_CHOICE_PRIVILEGE_R { + MATCH_CHOICE_PRIVILEGE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Select which match which itype when \\hyperref\\[fielddesc:TRACEMATCHINTERRUPT\\]{TRACE_MATCH_INTERRUP} is set. \\\\1: match itype of 2. \\\\0: match itype or 1."] + #[inline(always)] + pub fn match_value_interrupt(&self) -> MATCH_VALUE_INTERRUPT_R { + MATCH_VALUE_INTERRUPT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:7 - specified which ecause matched."] + #[inline(always)] + pub fn match_choice_ecause(&self) -> MATCH_CHOICE_ECAUSE_R { + MATCH_CHOICE_ECAUSE_R::new(((self.bits >> 2) & 0x3f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FILTER_MATCH_CONTROL") + .field( + "match_choice_privilege", + &format_args!("{}", self.match_choice_privilege().bit()), + ) + .field( + "match_value_interrupt", + &format_args!("{}", self.match_value_interrupt().bit()), + ) + .field( + "match_choice_ecause", + &format_args!("{}", self.match_choice_ecause().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Select match which privilege level when \\hyperref\\[fielddesc:TRACEMATCHPRIVILEGE\\]{TRACE_MATCH_PRIVILEGE} is set. \\\\1: machine mode. \\\\0: user mode"] + #[inline(always)] + #[must_use] + pub fn match_choice_privilege( + &mut self, + ) -> MATCH_CHOICE_PRIVILEGE_W { + MATCH_CHOICE_PRIVILEGE_W::new(self, 0) + } + #[doc = "Bit 1 - Select which match which itype when \\hyperref\\[fielddesc:TRACEMATCHINTERRUPT\\]{TRACE_MATCH_INTERRUP} is set. \\\\1: match itype of 2. \\\\0: match itype or 1."] + #[inline(always)] + #[must_use] + pub fn match_value_interrupt(&mut self) -> MATCH_VALUE_INTERRUPT_W { + MATCH_VALUE_INTERRUPT_W::new(self, 1) + } + #[doc = "Bits 2:7 - specified which ecause matched."] + #[inline(always)] + #[must_use] + pub fn match_choice_ecause(&mut self) -> MATCH_CHOICE_ECAUSE_W { + MATCH_CHOICE_ECAUSE_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "filter match control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_match_control::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_match_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FILTER_MATCH_CONTROL_SPEC; +impl crate::RegisterSpec for FILTER_MATCH_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`filter_match_control::R`](R) reader structure"] +impl crate::Readable for FILTER_MATCH_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`filter_match_control::W`](W) writer structure"] +impl crate::Writable for FILTER_MATCH_CONTROL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FILTER_MATCH_CONTROL to value 0"] +impl crate::Resettable for FILTER_MATCH_CONTROL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/filter_p_comparator_match.rs b/esp32p4/src/trace0/filter_p_comparator_match.rs new file mode 100644 index 0000000000..2e00b69a5f --- /dev/null +++ b/esp32p4/src/trace0/filter_p_comparator_match.rs @@ -0,0 +1,63 @@ +#[doc = "Register `FILTER_P_COMPARATOR_MATCH` reader"] +pub type R = crate::R; +#[doc = "Register `FILTER_P_COMPARATOR_MATCH` writer"] +pub type W = crate::W; +#[doc = "Field `P_MATCH` reader - primary comparator match value"] +pub type P_MATCH_R = crate::FieldReader; +#[doc = "Field `P_MATCH` writer - primary comparator match value"] +pub type P_MATCH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - primary comparator match value"] + #[inline(always)] + pub fn p_match(&self) -> P_MATCH_R { + P_MATCH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FILTER_P_COMPARATOR_MATCH") + .field("p_match", &format_args!("{}", self.p_match().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - primary comparator match value"] + #[inline(always)] + #[must_use] + pub fn p_match(&mut self) -> P_MATCH_W { + P_MATCH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "primary comparator match value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_p_comparator_match::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_p_comparator_match::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FILTER_P_COMPARATOR_MATCH_SPEC; +impl crate::RegisterSpec for FILTER_P_COMPARATOR_MATCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`filter_p_comparator_match::R`](R) reader structure"] +impl crate::Readable for FILTER_P_COMPARATOR_MATCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`filter_p_comparator_match::W`](W) writer structure"] +impl crate::Writable for FILTER_P_COMPARATOR_MATCH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FILTER_P_COMPARATOR_MATCH to value 0"] +impl crate::Resettable for FILTER_P_COMPARATOR_MATCH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/filter_s_comparator_match.rs b/esp32p4/src/trace0/filter_s_comparator_match.rs new file mode 100644 index 0000000000..56f6e1bb12 --- /dev/null +++ b/esp32p4/src/trace0/filter_s_comparator_match.rs @@ -0,0 +1,63 @@ +#[doc = "Register `FILTER_S_COMPARATOR_MATCH` reader"] +pub type R = crate::R; +#[doc = "Register `FILTER_S_COMPARATOR_MATCH` writer"] +pub type W = crate::W; +#[doc = "Field `S_MATCH` reader - secondary comparator match value"] +pub type S_MATCH_R = crate::FieldReader; +#[doc = "Field `S_MATCH` writer - secondary comparator match value"] +pub type S_MATCH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - secondary comparator match value"] + #[inline(always)] + pub fn s_match(&self) -> S_MATCH_R { + S_MATCH_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FILTER_S_COMPARATOR_MATCH") + .field("s_match", &format_args!("{}", self.s_match().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - secondary comparator match value"] + #[inline(always)] + #[must_use] + pub fn s_match(&mut self) -> S_MATCH_W { + S_MATCH_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "secondary comparator match value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_s_comparator_match::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filter_s_comparator_match::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FILTER_S_COMPARATOR_MATCH_SPEC; +impl crate::RegisterSpec for FILTER_S_COMPARATOR_MATCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`filter_s_comparator_match::R`](R) reader structure"] +impl crate::Readable for FILTER_S_COMPARATOR_MATCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`filter_s_comparator_match::W`](W) writer structure"] +impl crate::Writable for FILTER_S_COMPARATOR_MATCH_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FILTER_S_COMPARATOR_MATCH to value 0"] +impl crate::Resettable for FILTER_S_COMPARATOR_MATCH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/intr_clr.rs b/esp32p4/src/trace0/intr_clr.rs new file mode 100644 index 0000000000..d309238c7c --- /dev/null +++ b/esp32p4/src/trace0/intr_clr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INTR_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_OVERFLOW_INTR_CLR` writer - Set 1 clear fifo overflow interrupt"] +pub type FIFO_OVERFLOW_INTR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_FULL_INTR_CLR` writer - Set 1 clear mem full interrupt"] +pub type MEM_FULL_INTR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set 1 clear fifo overflow interrupt"] + #[inline(always)] + #[must_use] + pub fn fifo_overflow_intr_clr(&mut self) -> FIFO_OVERFLOW_INTR_CLR_W { + FIFO_OVERFLOW_INTR_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set 1 clear mem full interrupt"] + #[inline(always)] + #[must_use] + pub fn mem_full_intr_clr(&mut self) -> MEM_FULL_INTR_CLR_W { + MEM_FULL_INTR_CLR_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_CLR_SPEC; +impl crate::RegisterSpec for INTR_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`intr_clr::W`](W) writer structure"] +impl crate::Writable for INTR_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTR_CLR to value 0"] +impl crate::Resettable for INTR_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/intr_ena.rs b/esp32p4/src/trace0/intr_ena.rs new file mode 100644 index 0000000000..962eff34a8 --- /dev/null +++ b/esp32p4/src/trace0/intr_ena.rs @@ -0,0 +1,85 @@ +#[doc = "Register `INTR_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INTR_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_OVERFLOW_INTR_ENA` reader - Set 1 enable fifo_overflow interrupt"] +pub type FIFO_OVERFLOW_INTR_ENA_R = crate::BitReader; +#[doc = "Field `FIFO_OVERFLOW_INTR_ENA` writer - Set 1 enable fifo_overflow interrupt"] +pub type FIFO_OVERFLOW_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_FULL_INTR_ENA` reader - Set 1 enable mem_full interrupt"] +pub type MEM_FULL_INTR_ENA_R = crate::BitReader; +#[doc = "Field `MEM_FULL_INTR_ENA` writer - Set 1 enable mem_full interrupt"] +pub type MEM_FULL_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set 1 enable fifo_overflow interrupt"] + #[inline(always)] + pub fn fifo_overflow_intr_ena(&self) -> FIFO_OVERFLOW_INTR_ENA_R { + FIFO_OVERFLOW_INTR_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set 1 enable mem_full interrupt"] + #[inline(always)] + pub fn mem_full_intr_ena(&self) -> MEM_FULL_INTR_ENA_R { + MEM_FULL_INTR_ENA_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_ENA") + .field( + "fifo_overflow_intr_ena", + &format_args!("{}", self.fifo_overflow_intr_ena().bit()), + ) + .field( + "mem_full_intr_ena", + &format_args!("{}", self.mem_full_intr_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set 1 enable fifo_overflow interrupt"] + #[inline(always)] + #[must_use] + pub fn fifo_overflow_intr_ena(&mut self) -> FIFO_OVERFLOW_INTR_ENA_W { + FIFO_OVERFLOW_INTR_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Set 1 enable mem_full interrupt"] + #[inline(always)] + #[must_use] + pub fn mem_full_intr_ena(&mut self) -> MEM_FULL_INTR_ENA_W { + MEM_FULL_INTR_ENA_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_ENA_SPEC; +impl crate::RegisterSpec for INTR_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_ena::R`](R) reader structure"] +impl crate::Readable for INTR_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr_ena::W`](W) writer structure"] +impl crate::Writable for INTR_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTR_ENA to value 0"] +impl crate::Resettable for INTR_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/intr_raw.rs b/esp32p4/src/trace0/intr_raw.rs new file mode 100644 index 0000000000..a2f506361f --- /dev/null +++ b/esp32p4/src/trace0/intr_raw.rs @@ -0,0 +1,50 @@ +#[doc = "Register `INTR_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_OVERFLOW_INTR_RAW` reader - fifo_overflow interrupt status"] +pub type FIFO_OVERFLOW_INTR_RAW_R = crate::BitReader; +#[doc = "Field `MEM_FULL_INTR_RAW` reader - mem_full interrupt status"] +pub type MEM_FULL_INTR_RAW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - fifo_overflow interrupt status"] + #[inline(always)] + pub fn fifo_overflow_intr_raw(&self) -> FIFO_OVERFLOW_INTR_RAW_R { + FIFO_OVERFLOW_INTR_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - mem_full interrupt status"] + #[inline(always)] + pub fn mem_full_intr_raw(&self) -> MEM_FULL_INTR_RAW_R { + MEM_FULL_INTR_RAW_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTR_RAW") + .field( + "fifo_overflow_intr_raw", + &format_args!("{}", self.fifo_overflow_intr_raw().bit()), + ) + .field( + "mem_full_intr_raw", + &format_args!("{}", self.mem_full_intr_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_RAW_SPEC; +impl crate::RegisterSpec for INTR_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr_raw::R`](R) reader structure"] +impl crate::Readable for INTR_RAW_SPEC {} +#[doc = "`reset()` method sets INTR_RAW to value 0"] +impl crate::Resettable for INTR_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/mem_addr_update.rs b/esp32p4/src/trace0/mem_addr_update.rs new file mode 100644 index 0000000000..2e120ad55f --- /dev/null +++ b/esp32p4/src/trace0/mem_addr_update.rs @@ -0,0 +1,42 @@ +#[doc = "Register `MEM_ADDR_UPDATE` writer"] +pub type W = crate::W; +#[doc = "Field `MEM_CURRENT_ADDR_UPDATE` writer - when set, the will \\hyperref\\[fielddesc:TRACEMEMCURRENTADDR\\]{TRACE_MEM_CURRENT_ADDR} update to \\hyperref\\[fielddesc:TRACEMEMSTARTADDR\\]{TRACE_MEM_START_ADDR}."] +pub type MEM_CURRENT_ADDR_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - when set, the will \\hyperref\\[fielddesc:TRACEMEMCURRENTADDR\\]{TRACE_MEM_CURRENT_ADDR} update to \\hyperref\\[fielddesc:TRACEMEMSTARTADDR\\]{TRACE_MEM_START_ADDR}."] + #[inline(always)] + #[must_use] + pub fn mem_current_addr_update(&mut self) -> MEM_CURRENT_ADDR_UPDATE_W { + MEM_CURRENT_ADDR_UPDATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "mem addr update\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_addr_update::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_ADDR_UPDATE_SPEC; +impl crate::RegisterSpec for MEM_ADDR_UPDATE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`mem_addr_update::W`](W) writer structure"] +impl crate::Writable for MEM_ADDR_UPDATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_ADDR_UPDATE to value 0"] +impl crate::Resettable for MEM_ADDR_UPDATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/mem_current_addr.rs b/esp32p4/src/trace0/mem_current_addr.rs new file mode 100644 index 0000000000..ab5bb4fcb6 --- /dev/null +++ b/esp32p4/src/trace0/mem_current_addr.rs @@ -0,0 +1,39 @@ +#[doc = "Register `MEM_CURRENT_ADDR` reader"] +pub type R = crate::R; +#[doc = "Field `MEM_CURRENT_ADDR` reader - current_mem_addr,indicate that next writing addr"] +pub type MEM_CURRENT_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - current_mem_addr,indicate that next writing addr"] + #[inline(always)] + pub fn mem_current_addr(&self) -> MEM_CURRENT_ADDR_R { + MEM_CURRENT_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_CURRENT_ADDR") + .field( + "mem_current_addr", + &format_args!("{}", self.mem_current_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "mem current addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_current_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_CURRENT_ADDR_SPEC; +impl crate::RegisterSpec for MEM_CURRENT_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_current_addr::R`](R) reader structure"] +impl crate::Readable for MEM_CURRENT_ADDR_SPEC {} +#[doc = "`reset()` method sets MEM_CURRENT_ADDR to value 0"] +impl crate::Resettable for MEM_CURRENT_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/mem_end_addr.rs b/esp32p4/src/trace0/mem_end_addr.rs new file mode 100644 index 0000000000..48cf6a1852 --- /dev/null +++ b/esp32p4/src/trace0/mem_end_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `MEM_END_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_END_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `MEM_END_ADDR` reader - The end address of trace memory"] +pub type MEM_END_ADDR_R = crate::FieldReader; +#[doc = "Field `MEM_END_ADDR` writer - The end address of trace memory"] +pub type MEM_END_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The end address of trace memory"] + #[inline(always)] + pub fn mem_end_addr(&self) -> MEM_END_ADDR_R { + MEM_END_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_END_ADDR") + .field( + "mem_end_addr", + &format_args!("{}", self.mem_end_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The end address of trace memory"] + #[inline(always)] + #[must_use] + pub fn mem_end_addr(&mut self) -> MEM_END_ADDR_W { + MEM_END_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "mem end addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_end_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_end_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_END_ADDR_SPEC; +impl crate::RegisterSpec for MEM_END_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_end_addr::R`](R) reader structure"] +impl crate::Readable for MEM_END_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_end_addr::W`](W) writer structure"] +impl crate::Writable for MEM_END_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_END_ADDR to value 0xffff_ffff"] +impl crate::Resettable for MEM_END_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/trace0/mem_start_addr.rs b/esp32p4/src/trace0/mem_start_addr.rs new file mode 100644 index 0000000000..d6b54d8f22 --- /dev/null +++ b/esp32p4/src/trace0/mem_start_addr.rs @@ -0,0 +1,66 @@ +#[doc = "Register `MEM_START_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_START_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `MEM_START_ADDR` reader - The start address of trace memory"] +pub type MEM_START_ADDR_R = crate::FieldReader; +#[doc = "Field `MEM_START_ADDR` writer - The start address of trace memory"] +pub type MEM_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The start address of trace memory"] + #[inline(always)] + pub fn mem_start_addr(&self) -> MEM_START_ADDR_R { + MEM_START_ADDR_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_START_ADDR") + .field( + "mem_start_addr", + &format_args!("{}", self.mem_start_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The start address of trace memory"] + #[inline(always)] + #[must_use] + pub fn mem_start_addr(&mut self) -> MEM_START_ADDR_W { + MEM_START_ADDR_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "mem start addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_start_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_start_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_START_ADDR_SPEC; +impl crate::RegisterSpec for MEM_START_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_start_addr::R`](R) reader structure"] +impl crate::Readable for MEM_START_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_start_addr::W`](W) writer structure"] +impl crate::Writable for MEM_START_ADDR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_START_ADDR to value 0"] +impl crate::Resettable for MEM_START_ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/trace0/resync_prolonged.rs b/esp32p4/src/trace0/resync_prolonged.rs new file mode 100644 index 0000000000..4f6dc69472 --- /dev/null +++ b/esp32p4/src/trace0/resync_prolonged.rs @@ -0,0 +1,85 @@ +#[doc = "Register `RESYNC_PROLONGED` reader"] +pub type R = crate::R; +#[doc = "Register `RESYNC_PROLONGED` writer"] +pub type W = crate::W; +#[doc = "Field `RESYNC_PROLONGED` reader - count number, when count to this value, send a sync package"] +pub type RESYNC_PROLONGED_R = crate::FieldReader; +#[doc = "Field `RESYNC_PROLONGED` writer - count number, when count to this value, send a sync package"] +pub type RESYNC_PROLONGED_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Field `RESYNC_MODE` reader - resyc mode sel: \\\\0: off, \\\\2: cycle count \\\\3: package num count"] +pub type RESYNC_MODE_R = crate::FieldReader; +#[doc = "Field `RESYNC_MODE` writer - resyc mode sel: \\\\0: off, \\\\2: cycle count \\\\3: package num count"] +pub type RESYNC_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:23 - count number, when count to this value, send a sync package"] + #[inline(always)] + pub fn resync_prolonged(&self) -> RESYNC_PROLONGED_R { + RESYNC_PROLONGED_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bits 24:25 - resyc mode sel: \\\\0: off, \\\\2: cycle count \\\\3: package num count"] + #[inline(always)] + pub fn resync_mode(&self) -> RESYNC_MODE_R { + RESYNC_MODE_R::new(((self.bits >> 24) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESYNC_PROLONGED") + .field( + "resync_prolonged", + &format_args!("{}", self.resync_prolonged().bits()), + ) + .field( + "resync_mode", + &format_args!("{}", self.resync_mode().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:23 - count number, when count to this value, send a sync package"] + #[inline(always)] + #[must_use] + pub fn resync_prolonged(&mut self) -> RESYNC_PROLONGED_W { + RESYNC_PROLONGED_W::new(self, 0) + } + #[doc = "Bits 24:25 - resyc mode sel: \\\\0: off, \\\\2: cycle count \\\\3: package num count"] + #[inline(always)] + #[must_use] + pub fn resync_mode(&mut self) -> RESYNC_MODE_W { + RESYNC_MODE_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "resync configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resync_prolonged::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resync_prolonged::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESYNC_PROLONGED_SPEC; +impl crate::RegisterSpec for RESYNC_PROLONGED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`resync_prolonged::R`](R) reader structure"] +impl crate::Readable for RESYNC_PROLONGED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resync_prolonged::W`](W) writer structure"] +impl crate::Writable for RESYNC_PROLONGED_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RESYNC_PROLONGED to value 0x80"] +impl crate::Resettable for RESYNC_PROLONGED_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/trace0/trigger.rs b/esp32p4/src/trace0/trigger.rs new file mode 100644 index 0000000000..35edce4d89 --- /dev/null +++ b/esp32p4/src/trace0/trigger.rs @@ -0,0 +1,95 @@ +#[doc = "Register `TRIGGER` reader"] +pub type R = crate::R; +#[doc = "Register `TRIGGER` writer"] +pub type W = crate::W; +#[doc = "Field `ON` writer - Configure whether or not start trace.\\\\1: start trace \\\\0: invalid\\\\"] +pub type ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OFF` writer - Configure whether or not stop trace.\\\\1: stop trace \\\\0: invalid\\\\"] +pub type OFF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_LOOP` reader - Configure memory loop mode. \\\\1: trace will loop wrtie trace_mem. \\\\0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\\\"] +pub type MEM_LOOP_R = crate::BitReader; +#[doc = "Field `MEM_LOOP` writer - Configure memory loop mode. \\\\1: trace will loop wrtie trace_mem. \\\\0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\\\"] +pub type MEM_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESTART_ENA` reader - Configure whether or not enable auto-restart.\\\\1: enable\\\\0: disable\\\\"] +pub type RESTART_ENA_R = crate::BitReader; +#[doc = "Field `RESTART_ENA` writer - Configure whether or not enable auto-restart.\\\\1: enable\\\\0: disable\\\\"] +pub type RESTART_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Configure memory loop mode. \\\\1: trace will loop wrtie trace_mem. \\\\0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\\\"] + #[inline(always)] + pub fn mem_loop(&self) -> MEM_LOOP_R { + MEM_LOOP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Configure whether or not enable auto-restart.\\\\1: enable\\\\0: disable\\\\"] + #[inline(always)] + pub fn restart_ena(&self) -> RESTART_ENA_R { + RESTART_ENA_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TRIGGER") + .field("mem_loop", &format_args!("{}", self.mem_loop().bit())) + .field("restart_ena", &format_args!("{}", self.restart_ena().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Configure whether or not start trace.\\\\1: start trace \\\\0: invalid\\\\"] + #[inline(always)] + #[must_use] + pub fn on(&mut self) -> ON_W { + ON_W::new(self, 0) + } + #[doc = "Bit 1 - Configure whether or not stop trace.\\\\1: stop trace \\\\0: invalid\\\\"] + #[inline(always)] + #[must_use] + pub fn off(&mut self) -> OFF_W { + OFF_W::new(self, 1) + } + #[doc = "Bit 2 - Configure memory loop mode. \\\\1: trace will loop wrtie trace_mem. \\\\0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\\\"] + #[inline(always)] + #[must_use] + pub fn mem_loop(&mut self) -> MEM_LOOP_W { + MEM_LOOP_W::new(self, 2) + } + #[doc = "Bit 3 - Configure whether or not enable auto-restart.\\\\1: enable\\\\0: disable\\\\"] + #[inline(always)] + #[must_use] + pub fn restart_ena(&mut self) -> RESTART_ENA_W { + RESTART_ENA_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "trigger register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trigger::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trigger::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRIGGER_SPEC; +impl crate::RegisterSpec for TRIGGER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trigger::R`](R) reader structure"] +impl crate::Readable for TRIGGER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trigger::W`](W) writer structure"] +impl crate::Writable for TRIGGER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TRIGGER to value 0x0c"] +impl crate::Resettable for TRIGGER_SPEC { + const RESET_VALUE: Self::Ux = 0x0c; +} diff --git a/esp32p4/src/twai0.rs b/esp32p4/src/twai0.rs new file mode 100644 index 0000000000..9c978c0570 --- /dev/null +++ b/esp32p4/src/twai0.rs @@ -0,0 +1,360 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + mode: MODE, + cmd: CMD, + status: STATUS, + interrupt: INTERRUPT, + interrupt_enable: INTERRUPT_ENABLE, + _reserved5: [u8; 0x04], + bus_timing_0: BUS_TIMING_0, + bus_timing_1: BUS_TIMING_1, + _reserved7: [u8; 0x0c], + arb_lost_cap: ARB_LOST_CAP, + err_code_cap: ERR_CODE_CAP, + err_warning_limit: ERR_WARNING_LIMIT, + rx_err_cnt: RX_ERR_CNT, + tx_err_cnt: TX_ERR_CNT, + data_0: DATA_0, + data_1: DATA_1, + data_2: DATA_2, + data_3: DATA_3, + data_4: DATA_4, + data_5: DATA_5, + data_6: DATA_6, + data_7: DATA_7, + data_8: DATA_8, + data_9: DATA_9, + data_10: DATA_10, + data_11: DATA_11, + data_12: DATA_12, + rx_message_counter: RX_MESSAGE_COUNTER, + _reserved26: [u8; 0x04], + clock_divider: CLOCK_DIVIDER, + sw_standby_cfg: SW_STANDBY_CFG, + hw_cfg: HW_CFG, + hw_standby_cnt: HW_STANDBY_CNT, + idle_intr_cnt: IDLE_INTR_CNT, + eco_cfg: ECO_CFG, + timestamp_data: TIMESTAMP_DATA, + timestamp_prescaler: TIMESTAMP_PRESCALER, + timestamp_cfg: TIMESTAMP_CFG, +} +impl RegisterBlock { + #[doc = "0x00 - TWAI mode register."] + #[inline(always)] + pub const fn mode(&self) -> &MODE { + &self.mode + } + #[doc = "0x04 - TWAI command register."] + #[inline(always)] + pub const fn cmd(&self) -> &CMD { + &self.cmd + } + #[doc = "0x08 - TWAI status register."] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0x0c - Interrupt signals' register."] + #[inline(always)] + pub const fn interrupt(&self) -> &INTERRUPT { + &self.interrupt + } + #[doc = "0x10 - Interrupt enable register."] + #[inline(always)] + pub const fn interrupt_enable(&self) -> &INTERRUPT_ENABLE { + &self.interrupt_enable + } + #[doc = "0x18 - Bit timing configuration register 0."] + #[inline(always)] + pub const fn bus_timing_0(&self) -> &BUS_TIMING_0 { + &self.bus_timing_0 + } + #[doc = "0x1c - Bit timing configuration register 1."] + #[inline(always)] + pub const fn bus_timing_1(&self) -> &BUS_TIMING_1 { + &self.bus_timing_1 + } + #[doc = "0x2c - TWAI arbiter lost capture register."] + #[inline(always)] + pub const fn arb_lost_cap(&self) -> &ARB_LOST_CAP { + &self.arb_lost_cap + } + #[doc = "0x30 - TWAI error info capture register."] + #[inline(always)] + pub const fn err_code_cap(&self) -> &ERR_CODE_CAP { + &self.err_code_cap + } + #[doc = "0x34 - TWAI error threshold configuration register."] + #[inline(always)] + pub const fn err_warning_limit(&self) -> &ERR_WARNING_LIMIT { + &self.err_warning_limit + } + #[doc = "0x38 - Rx error counter register."] + #[inline(always)] + pub const fn rx_err_cnt(&self) -> &RX_ERR_CNT { + &self.rx_err_cnt + } + #[doc = "0x3c - Tx error counter register."] + #[inline(always)] + pub const fn tx_err_cnt(&self) -> &TX_ERR_CNT { + &self.tx_err_cnt + } + #[doc = "0x40 - Data register 0."] + #[inline(always)] + pub const fn data_0(&self) -> &DATA_0 { + &self.data_0 + } + #[doc = "0x44 - Data register 1."] + #[inline(always)] + pub const fn data_1(&self) -> &DATA_1 { + &self.data_1 + } + #[doc = "0x48 - Data register 2."] + #[inline(always)] + pub const fn data_2(&self) -> &DATA_2 { + &self.data_2 + } + #[doc = "0x4c - Data register 3."] + #[inline(always)] + pub const fn data_3(&self) -> &DATA_3 { + &self.data_3 + } + #[doc = "0x50 - Data register 4."] + #[inline(always)] + pub const fn data_4(&self) -> &DATA_4 { + &self.data_4 + } + #[doc = "0x54 - Data register 5."] + #[inline(always)] + pub const fn data_5(&self) -> &DATA_5 { + &self.data_5 + } + #[doc = "0x58 - Data register 6."] + #[inline(always)] + pub const fn data_6(&self) -> &DATA_6 { + &self.data_6 + } + #[doc = "0x5c - Data register 7."] + #[inline(always)] + pub const fn data_7(&self) -> &DATA_7 { + &self.data_7 + } + #[doc = "0x60 - Data register 8."] + #[inline(always)] + pub const fn data_8(&self) -> &DATA_8 { + &self.data_8 + } + #[doc = "0x64 - Data register 9."] + #[inline(always)] + pub const fn data_9(&self) -> &DATA_9 { + &self.data_9 + } + #[doc = "0x68 - Data register 10."] + #[inline(always)] + pub const fn data_10(&self) -> &DATA_10 { + &self.data_10 + } + #[doc = "0x6c - Data register 11."] + #[inline(always)] + pub const fn data_11(&self) -> &DATA_11 { + &self.data_11 + } + #[doc = "0x70 - Data register 12."] + #[inline(always)] + pub const fn data_12(&self) -> &DATA_12 { + &self.data_12 + } + #[doc = "0x74 - Received message counter register."] + #[inline(always)] + pub const fn rx_message_counter(&self) -> &RX_MESSAGE_COUNTER { + &self.rx_message_counter + } + #[doc = "0x7c - Clock divider register."] + #[inline(always)] + pub const fn clock_divider(&self) -> &CLOCK_DIVIDER { + &self.clock_divider + } + #[doc = "0x80 - Software configure standby pin directly."] + #[inline(always)] + pub const fn sw_standby_cfg(&self) -> &SW_STANDBY_CFG { + &self.sw_standby_cfg + } + #[doc = "0x84 - Hardware configure standby pin."] + #[inline(always)] + pub const fn hw_cfg(&self) -> &HW_CFG { + &self.hw_cfg + } + #[doc = "0x88 - Configure standby counter."] + #[inline(always)] + pub const fn hw_standby_cnt(&self) -> &HW_STANDBY_CNT { + &self.hw_standby_cnt + } + #[doc = "0x8c - Configure idle interrupt counter."] + #[inline(always)] + pub const fn idle_intr_cnt(&self) -> &IDLE_INTR_CNT { + &self.idle_intr_cnt + } + #[doc = "0x90 - ECO configuration register."] + #[inline(always)] + pub const fn eco_cfg(&self) -> &ECO_CFG { + &self.eco_cfg + } + #[doc = "0x94 - Timestamp data register"] + #[inline(always)] + pub const fn timestamp_data(&self) -> &TIMESTAMP_DATA { + &self.timestamp_data + } + #[doc = "0x98 - Timestamp configuration register"] + #[inline(always)] + pub const fn timestamp_prescaler(&self) -> &TIMESTAMP_PRESCALER { + &self.timestamp_prescaler + } + #[doc = "0x9c - Timestamp configuration register"] + #[inline(always)] + pub const fn timestamp_cfg(&self) -> &TIMESTAMP_CFG { + &self.timestamp_cfg + } +} +#[doc = "MODE (rw) register accessor: TWAI mode register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`] module"] +pub type MODE = crate::Reg; +#[doc = "TWAI mode register."] +pub mod mode; +#[doc = "CMD (w) register accessor: TWAI command register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"] +pub type CMD = crate::Reg; +#[doc = "TWAI command register."] +pub mod cmd; +#[doc = "STATUS (r) register accessor: TWAI status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +pub type STATUS = crate::Reg; +#[doc = "TWAI status register."] +pub mod status; +#[doc = "INTERRUPT (r) register accessor: Interrupt signals' register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt`] module"] +pub type INTERRUPT = crate::Reg; +#[doc = "Interrupt signals' register."] +pub mod interrupt; +#[doc = "INTERRUPT_ENABLE (rw) register accessor: Interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt_enable`] module"] +pub type INTERRUPT_ENABLE = crate::Reg; +#[doc = "Interrupt enable register."] +pub mod interrupt_enable; +#[doc = "BUS_TIMING_0 (rw) register accessor: Bit timing configuration register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_timing_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_timing_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_timing_0`] module"] +pub type BUS_TIMING_0 = crate::Reg; +#[doc = "Bit timing configuration register 0."] +pub mod bus_timing_0; +#[doc = "BUS_TIMING_1 (rw) register accessor: Bit timing configuration register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_timing_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_timing_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_timing_1`] module"] +pub type BUS_TIMING_1 = crate::Reg; +#[doc = "Bit timing configuration register 1."] +pub mod bus_timing_1; +#[doc = "ARB_LOST_CAP (r) register accessor: TWAI arbiter lost capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_lost_cap::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arb_lost_cap`] module"] +pub type ARB_LOST_CAP = crate::Reg; +#[doc = "TWAI arbiter lost capture register."] +pub mod arb_lost_cap; +#[doc = "ERR_CODE_CAP (r) register accessor: TWAI error info capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_code_cap::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_code_cap`] module"] +pub type ERR_CODE_CAP = crate::Reg; +#[doc = "TWAI error info capture register."] +pub mod err_code_cap; +#[doc = "ERR_WARNING_LIMIT (rw) register accessor: TWAI error threshold configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_warning_limit::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err_warning_limit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_warning_limit`] module"] +pub type ERR_WARNING_LIMIT = crate::Reg; +#[doc = "TWAI error threshold configuration register."] +pub mod err_warning_limit; +#[doc = "RX_ERR_CNT (rw) register accessor: Rx error counter register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_err_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_err_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_err_cnt`] module"] +pub type RX_ERR_CNT = crate::Reg; +#[doc = "Rx error counter register."] +pub mod rx_err_cnt; +#[doc = "TX_ERR_CNT (rw) register accessor: Tx error counter register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_err_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_err_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_err_cnt`] module"] +pub type TX_ERR_CNT = crate::Reg; +#[doc = "Tx error counter register."] +pub mod tx_err_cnt; +#[doc = "DATA_0 (rw) register accessor: Data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_0`] module"] +pub type DATA_0 = crate::Reg; +#[doc = "Data register 0."] +pub mod data_0; +#[doc = "DATA_1 (rw) register accessor: Data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_1`] module"] +pub type DATA_1 = crate::Reg; +#[doc = "Data register 1."] +pub mod data_1; +#[doc = "DATA_2 (rw) register accessor: Data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_2`] module"] +pub type DATA_2 = crate::Reg; +#[doc = "Data register 2."] +pub mod data_2; +#[doc = "DATA_3 (rw) register accessor: Data register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_3`] module"] +pub type DATA_3 = crate::Reg; +#[doc = "Data register 3."] +pub mod data_3; +#[doc = "DATA_4 (rw) register accessor: Data register 4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_4`] module"] +pub type DATA_4 = crate::Reg; +#[doc = "Data register 4."] +pub mod data_4; +#[doc = "DATA_5 (rw) register accessor: Data register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_5`] module"] +pub type DATA_5 = crate::Reg; +#[doc = "Data register 5."] +pub mod data_5; +#[doc = "DATA_6 (rw) register accessor: Data register 6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_6`] module"] +pub type DATA_6 = crate::Reg; +#[doc = "Data register 6."] +pub mod data_6; +#[doc = "DATA_7 (rw) register accessor: Data register 7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_7`] module"] +pub type DATA_7 = crate::Reg; +#[doc = "Data register 7."] +pub mod data_7; +#[doc = "DATA_8 (rw) register accessor: Data register 8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_8`] module"] +pub type DATA_8 = crate::Reg; +#[doc = "Data register 8."] +pub mod data_8; +#[doc = "DATA_9 (rw) register accessor: Data register 9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_9`] module"] +pub type DATA_9 = crate::Reg; +#[doc = "Data register 9."] +pub mod data_9; +#[doc = "DATA_10 (rw) register accessor: Data register 10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_10`] module"] +pub type DATA_10 = crate::Reg; +#[doc = "Data register 10."] +pub mod data_10; +#[doc = "DATA_11 (rw) register accessor: Data register 11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_11`] module"] +pub type DATA_11 = crate::Reg; +#[doc = "Data register 11."] +pub mod data_11; +#[doc = "DATA_12 (rw) register accessor: Data register 12.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_12`] module"] +pub type DATA_12 = crate::Reg; +#[doc = "Data register 12."] +pub mod data_12; +#[doc = "RX_MESSAGE_COUNTER (r) register accessor: Received message counter register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_message_counter::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_message_counter`] module"] +pub type RX_MESSAGE_COUNTER = crate::Reg; +#[doc = "Received message counter register."] +pub mod rx_message_counter; +#[doc = "CLOCK_DIVIDER (rw) register accessor: Clock divider register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_divider::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_divider::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_divider`] module"] +pub type CLOCK_DIVIDER = crate::Reg; +#[doc = "Clock divider register."] +pub mod clock_divider; +#[doc = "SW_STANDBY_CFG (rw) register accessor: Software configure standby pin directly.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_standby_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_standby_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_standby_cfg`] module"] +pub type SW_STANDBY_CFG = crate::Reg; +#[doc = "Software configure standby pin directly."] +pub mod sw_standby_cfg; +#[doc = "HW_CFG (rw) register accessor: Hardware configure standby pin.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_cfg`] module"] +pub type HW_CFG = crate::Reg; +#[doc = "Hardware configure standby pin."] +pub mod hw_cfg; +#[doc = "HW_STANDBY_CNT (rw) register accessor: Configure standby counter.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_standby_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_standby_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hw_standby_cnt`] module"] +pub type HW_STANDBY_CNT = crate::Reg; +#[doc = "Configure standby counter."] +pub mod hw_standby_cnt; +#[doc = "IDLE_INTR_CNT (rw) register accessor: Configure idle interrupt counter.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle_intr_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idle_intr_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idle_intr_cnt`] module"] +pub type IDLE_INTR_CNT = crate::Reg; +#[doc = "Configure idle interrupt counter."] +pub mod idle_intr_cnt; +#[doc = "ECO_CFG (rw) register accessor: ECO configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_cfg`] module"] +pub type ECO_CFG = crate::Reg; +#[doc = "ECO configuration register."] +pub mod eco_cfg; +#[doc = "TIMESTAMP_DATA (r) register accessor: Timestamp data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timestamp_data`] module"] +pub type TIMESTAMP_DATA = crate::Reg; +#[doc = "Timestamp data register"] +pub mod timestamp_data; +#[doc = "TIMESTAMP_PRESCALER (rw) register accessor: Timestamp configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_prescaler::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_prescaler::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timestamp_prescaler`] module"] +pub type TIMESTAMP_PRESCALER = crate::Reg; +#[doc = "Timestamp configuration register"] +pub mod timestamp_prescaler; +#[doc = "TIMESTAMP_CFG (rw) register accessor: Timestamp configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timestamp_cfg`] module"] +pub type TIMESTAMP_CFG = crate::Reg; +#[doc = "Timestamp configuration register"] +pub mod timestamp_cfg; diff --git a/esp32p4/src/twai0/arb_lost_cap.rs b/esp32p4/src/twai0/arb_lost_cap.rs new file mode 100644 index 0000000000..9cd5d85eea --- /dev/null +++ b/esp32p4/src/twai0/arb_lost_cap.rs @@ -0,0 +1,39 @@ +#[doc = "Register `ARB_LOST_CAP` reader"] +pub type R = crate::R; +#[doc = "Field `ARBITRATION_LOST_CAPTURE` reader - This register contains information about the bit position of losing arbitration."] +pub type ARBITRATION_LOST_CAPTURE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - This register contains information about the bit position of losing arbitration."] + #[inline(always)] + pub fn arbitration_lost_capture(&self) -> ARBITRATION_LOST_CAPTURE_R { + ARBITRATION_LOST_CAPTURE_R::new((self.bits & 0x1f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ARB_LOST_CAP") + .field( + "arbitration_lost_capture", + &format_args!("{}", self.arbitration_lost_capture().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TWAI arbiter lost capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_lost_cap::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ARB_LOST_CAP_SPEC; +impl crate::RegisterSpec for ARB_LOST_CAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`arb_lost_cap::R`](R) reader structure"] +impl crate::Readable for ARB_LOST_CAP_SPEC {} +#[doc = "`reset()` method sets ARB_LOST_CAP to value 0"] +impl crate::Resettable for ARB_LOST_CAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/bus_timing_0.rs b/esp32p4/src/twai0/bus_timing_0.rs new file mode 100644 index 0000000000..82392aad86 --- /dev/null +++ b/esp32p4/src/twai0/bus_timing_0.rs @@ -0,0 +1,82 @@ +#[doc = "Register `BUS_TIMING_0` reader"] +pub type R = crate::R; +#[doc = "Register `BUS_TIMING_0` writer"] +pub type W = crate::W; +#[doc = "Field `BAUD_PRESC` reader - The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode."] +pub type BAUD_PRESC_R = crate::FieldReader; +#[doc = "Field `BAUD_PRESC` writer - The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode."] +pub type BAUD_PRESC_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `SYNC_JUMP_WIDTH` reader - The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode."] +pub type SYNC_JUMP_WIDTH_R = crate::FieldReader; +#[doc = "Field `SYNC_JUMP_WIDTH` writer - The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode."] +pub type SYNC_JUMP_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:13 - The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode."] + #[inline(always)] + pub fn baud_presc(&self) -> BAUD_PRESC_R { + BAUD_PRESC_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 14:15 - The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + pub fn sync_jump_width(&self) -> SYNC_JUMP_WIDTH_R { + SYNC_JUMP_WIDTH_R::new(((self.bits >> 14) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUS_TIMING_0") + .field("baud_presc", &format_args!("{}", self.baud_presc().bits())) + .field( + "sync_jump_width", + &format_args!("{}", self.sync_jump_width().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode."] + #[inline(always)] + #[must_use] + pub fn baud_presc(&mut self) -> BAUD_PRESC_W { + BAUD_PRESC_W::new(self, 0) + } + #[doc = "Bits 14:15 - The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + #[must_use] + pub fn sync_jump_width(&mut self) -> SYNC_JUMP_WIDTH_W { + SYNC_JUMP_WIDTH_W::new(self, 14) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Bit timing configuration register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_timing_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_timing_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUS_TIMING_0_SPEC; +impl crate::RegisterSpec for BUS_TIMING_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bus_timing_0::R`](R) reader structure"] +impl crate::Readable for BUS_TIMING_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bus_timing_0::W`](W) writer structure"] +impl crate::Writable for BUS_TIMING_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BUS_TIMING_0 to value 0"] +impl crate::Resettable for BUS_TIMING_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/bus_timing_1.rs b/esp32p4/src/twai0/bus_timing_1.rs new file mode 100644 index 0000000000..1bc95537e0 --- /dev/null +++ b/esp32p4/src/twai0/bus_timing_1.rs @@ -0,0 +1,104 @@ +#[doc = "Register `BUS_TIMING_1` reader"] +pub type R = crate::R; +#[doc = "Register `BUS_TIMING_1` writer"] +pub type W = crate::W; +#[doc = "Field `TIME_SEGMENT1` reader - The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode."] +pub type TIME_SEGMENT1_R = crate::FieldReader; +#[doc = "Field `TIME_SEGMENT1` writer - The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode."] +pub type TIME_SEGMENT1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TIME_SEGMENT2` reader - The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode."] +pub type TIME_SEGMENT2_R = crate::FieldReader; +#[doc = "Field `TIME_SEGMENT2` writer - The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode."] +pub type TIME_SEGMENT2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `TIME_SAMPLING` reader - 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode."] +pub type TIME_SAMPLING_R = crate::BitReader; +#[doc = "Field `TIME_SAMPLING` writer - 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode."] +pub type TIME_SAMPLING_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + pub fn time_segment1(&self) -> TIME_SEGMENT1_R { + TIME_SEGMENT1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:6 - The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + pub fn time_segment2(&self) -> TIME_SEGMENT2_R { + TIME_SEGMENT2_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + pub fn time_sampling(&self) -> TIME_SAMPLING_R { + TIME_SAMPLING_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUS_TIMING_1") + .field( + "time_segment1", + &format_args!("{}", self.time_segment1().bits()), + ) + .field( + "time_segment2", + &format_args!("{}", self.time_segment2().bits()), + ) + .field( + "time_sampling", + &format_args!("{}", self.time_sampling().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:3 - The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + #[must_use] + pub fn time_segment1(&mut self) -> TIME_SEGMENT1_W { + TIME_SEGMENT1_W::new(self, 0) + } + #[doc = "Bits 4:6 - The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + #[must_use] + pub fn time_segment2(&mut self) -> TIME_SEGMENT2_W { + TIME_SEGMENT2_W::new(self, 4) + } + #[doc = "Bit 7 - 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + #[must_use] + pub fn time_sampling(&mut self) -> TIME_SAMPLING_W { + TIME_SAMPLING_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Bit timing configuration register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_timing_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_timing_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUS_TIMING_1_SPEC; +impl crate::RegisterSpec for BUS_TIMING_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bus_timing_1::R`](R) reader structure"] +impl crate::Readable for BUS_TIMING_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bus_timing_1::W`](W) writer structure"] +impl crate::Writable for BUS_TIMING_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BUS_TIMING_1 to value 0"] +impl crate::Resettable for BUS_TIMING_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/clock_divider.rs b/esp32p4/src/twai0/clock_divider.rs new file mode 100644 index 0000000000..70f19945d5 --- /dev/null +++ b/esp32p4/src/twai0/clock_divider.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CLOCK_DIVIDER` reader"] +pub type R = crate::R; +#[doc = "Register `CLOCK_DIVIDER` writer"] +pub type W = crate::W; +#[doc = "Field `CD` reader - These bits are used to define the frequency at the external CLKOUT pin."] +pub type CD_R = crate::FieldReader; +#[doc = "Field `CD` writer - These bits are used to define the frequency at the external CLKOUT pin."] +pub type CD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CLOCK_OFF` reader - 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode."] +pub type CLOCK_OFF_R = crate::BitReader; +#[doc = "Field `CLOCK_OFF` writer - 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode."] +pub type CLOCK_OFF_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - These bits are used to define the frequency at the external CLKOUT pin."] + #[inline(always)] + pub fn cd(&self) -> CD_R { + CD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + pub fn clock_off(&self) -> CLOCK_OFF_R { + CLOCK_OFF_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCK_DIVIDER") + .field("cd", &format_args!("{}", self.cd().bits())) + .field("clock_off", &format_args!("{}", self.clock_off().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - These bits are used to define the frequency at the external CLKOUT pin."] + #[inline(always)] + #[must_use] + pub fn cd(&mut self) -> CD_W { + CD_W::new(self, 0) + } + #[doc = "Bit 8 - 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + #[must_use] + pub fn clock_off(&mut self) -> CLOCK_OFF_W { + CLOCK_OFF_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock divider register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_divider::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_divider::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLOCK_DIVIDER_SPEC; +impl crate::RegisterSpec for CLOCK_DIVIDER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clock_divider::R`](R) reader structure"] +impl crate::Readable for CLOCK_DIVIDER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clock_divider::W`](W) writer structure"] +impl crate::Writable for CLOCK_DIVIDER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLOCK_DIVIDER to value 0"] +impl crate::Resettable for CLOCK_DIVIDER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/cmd.rs b/esp32p4/src/twai0/cmd.rs new file mode 100644 index 0000000000..cf1d016890 --- /dev/null +++ b/esp32p4/src/twai0/cmd.rs @@ -0,0 +1,74 @@ +#[doc = "Register `CMD` writer"] +pub type W = crate::W; +#[doc = "Field `TX_REQUEST` writer - 1: present, a message shall be transmitted. 0: absent"] +pub type TX_REQUEST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ABORT_TX` writer - 1: present, if not already in progress, a pending transmission request is cancelled. 0: absent"] +pub type ABORT_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RELEASE_BUFFER` writer - 1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action"] +pub type RELEASE_BUFFER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_DATA_OVERRUN` writer - 1: clear, the data overrun status bit is cleared. 0: no action."] +pub type CLEAR_DATA_OVERRUN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SELF_RX_REQUEST` writer - 1: present, a message shall be transmitted and received simultaneously. 0: absent."] +pub type SELF_RX_REQUEST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - 1: present, a message shall be transmitted. 0: absent"] + #[inline(always)] + #[must_use] + pub fn tx_request(&mut self) -> TX_REQUEST_W { + TX_REQUEST_W::new(self, 0) + } + #[doc = "Bit 1 - 1: present, if not already in progress, a pending transmission request is cancelled. 0: absent"] + #[inline(always)] + #[must_use] + pub fn abort_tx(&mut self) -> ABORT_TX_W { + ABORT_TX_W::new(self, 1) + } + #[doc = "Bit 2 - 1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action"] + #[inline(always)] + #[must_use] + pub fn release_buffer(&mut self) -> RELEASE_BUFFER_W { + RELEASE_BUFFER_W::new(self, 2) + } + #[doc = "Bit 3 - 1: clear, the data overrun status bit is cleared. 0: no action."] + #[inline(always)] + #[must_use] + pub fn clear_data_overrun(&mut self) -> CLEAR_DATA_OVERRUN_W { + CLEAR_DATA_OVERRUN_W::new(self, 3) + } + #[doc = "Bit 4 - 1: present, a message shall be transmitted and received simultaneously. 0: absent."] + #[inline(always)] + #[must_use] + pub fn self_rx_request(&mut self) -> SELF_RX_REQUEST_W { + SELF_RX_REQUEST_W::new(self, 4) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TWAI command register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CMD_SPEC; +impl crate::RegisterSpec for CMD_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"] +impl crate::Writable for CMD_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMD to value 0"] +impl crate::Resettable for CMD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_0.rs b/esp32p4/src/twai0/data_0.rs new file mode 100644 index 0000000000..345964beef --- /dev/null +++ b/esp32p4/src/twai0/data_0.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_0` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_0` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_0` reader - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0."] +pub type DATA_0_R = crate::FieldReader; +#[doc = "Field `DATA_0` writer - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0."] +pub type DATA_0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0."] + #[inline(always)] + pub fn data_0(&self) -> DATA_0_R { + DATA_0_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_0") + .field("data_0", &format_args!("{}", self.data_0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0."] + #[inline(always)] + #[must_use] + pub fn data_0(&mut self) -> DATA_0_W { + DATA_0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_0_SPEC; +impl crate::RegisterSpec for DATA_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_0::R`](R) reader structure"] +impl crate::Readable for DATA_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_0::W`](W) writer structure"] +impl crate::Writable for DATA_0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_0 to value 0"] +impl crate::Resettable for DATA_0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_1.rs b/esp32p4/src/twai0/data_1.rs new file mode 100644 index 0000000000..43da97f4a8 --- /dev/null +++ b/esp32p4/src/twai0/data_1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_1` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_1` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_1` reader - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1."] +pub type DATA_1_R = crate::FieldReader; +#[doc = "Field `DATA_1` writer - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1."] +pub type DATA_1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1."] + #[inline(always)] + pub fn data_1(&self) -> DATA_1_R { + DATA_1_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_1") + .field("data_1", &format_args!("{}", self.data_1().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1."] + #[inline(always)] + #[must_use] + pub fn data_1(&mut self) -> DATA_1_W { + DATA_1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_1_SPEC; +impl crate::RegisterSpec for DATA_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_1::R`](R) reader structure"] +impl crate::Readable for DATA_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_1::W`](W) writer structure"] +impl crate::Writable for DATA_1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_1 to value 0"] +impl crate::Resettable for DATA_1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_10.rs b/esp32p4/src/twai0/data_10.rs new file mode 100644 index 0000000000..44c834ce02 --- /dev/null +++ b/esp32p4/src/twai0/data_10.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_10` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_10` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_10` reader - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10."] +pub type DATA_10_R = crate::FieldReader; +#[doc = "Field `DATA_10` writer - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10."] +pub type DATA_10_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10."] + #[inline(always)] + pub fn data_10(&self) -> DATA_10_R { + DATA_10_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_10") + .field("data_10", &format_args!("{}", self.data_10().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10."] + #[inline(always)] + #[must_use] + pub fn data_10(&mut self) -> DATA_10_W { + DATA_10_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_10_SPEC; +impl crate::RegisterSpec for DATA_10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_10::R`](R) reader structure"] +impl crate::Readable for DATA_10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_10::W`](W) writer structure"] +impl crate::Writable for DATA_10_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_10 to value 0"] +impl crate::Resettable for DATA_10_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_11.rs b/esp32p4/src/twai0/data_11.rs new file mode 100644 index 0000000000..02ac247d88 --- /dev/null +++ b/esp32p4/src/twai0/data_11.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_11` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_11` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_11` reader - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11."] +pub type DATA_11_R = crate::FieldReader; +#[doc = "Field `DATA_11` writer - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11."] +pub type DATA_11_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11."] + #[inline(always)] + pub fn data_11(&self) -> DATA_11_R { + DATA_11_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_11") + .field("data_11", &format_args!("{}", self.data_11().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11."] + #[inline(always)] + #[must_use] + pub fn data_11(&mut self) -> DATA_11_W { + DATA_11_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_11_SPEC; +impl crate::RegisterSpec for DATA_11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_11::R`](R) reader structure"] +impl crate::Readable for DATA_11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_11::W`](W) writer structure"] +impl crate::Writable for DATA_11_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_11 to value 0"] +impl crate::Resettable for DATA_11_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_12.rs b/esp32p4/src/twai0/data_12.rs new file mode 100644 index 0000000000..eedcf9b5ed --- /dev/null +++ b/esp32p4/src/twai0/data_12.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_12` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_12` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_12` reader - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12."] +pub type DATA_12_R = crate::FieldReader; +#[doc = "Field `DATA_12` writer - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12."] +pub type DATA_12_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12."] + #[inline(always)] + pub fn data_12(&self) -> DATA_12_R { + DATA_12_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_12") + .field("data_12", &format_args!("{}", self.data_12().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12."] + #[inline(always)] + #[must_use] + pub fn data_12(&mut self) -> DATA_12_W { + DATA_12_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 12.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_12_SPEC; +impl crate::RegisterSpec for DATA_12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_12::R`](R) reader structure"] +impl crate::Readable for DATA_12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_12::W`](W) writer structure"] +impl crate::Writable for DATA_12_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_12 to value 0"] +impl crate::Resettable for DATA_12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_2.rs b/esp32p4/src/twai0/data_2.rs new file mode 100644 index 0000000000..72e67ee448 --- /dev/null +++ b/esp32p4/src/twai0/data_2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_2` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_2` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_2` reader - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2."] +pub type DATA_2_R = crate::FieldReader; +#[doc = "Field `DATA_2` writer - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2."] +pub type DATA_2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2."] + #[inline(always)] + pub fn data_2(&self) -> DATA_2_R { + DATA_2_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_2") + .field("data_2", &format_args!("{}", self.data_2().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2."] + #[inline(always)] + #[must_use] + pub fn data_2(&mut self) -> DATA_2_W { + DATA_2_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_2_SPEC; +impl crate::RegisterSpec for DATA_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_2::R`](R) reader structure"] +impl crate::Readable for DATA_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_2::W`](W) writer structure"] +impl crate::Writable for DATA_2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_2 to value 0"] +impl crate::Resettable for DATA_2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_3.rs b/esp32p4/src/twai0/data_3.rs new file mode 100644 index 0000000000..ccd4197d1f --- /dev/null +++ b/esp32p4/src/twai0/data_3.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_3` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_3` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_3` reader - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3."] +pub type DATA_3_R = crate::FieldReader; +#[doc = "Field `DATA_3` writer - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3."] +pub type DATA_3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3."] + #[inline(always)] + pub fn data_3(&self) -> DATA_3_R { + DATA_3_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_3") + .field("data_3", &format_args!("{}", self.data_3().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3."] + #[inline(always)] + #[must_use] + pub fn data_3(&mut self) -> DATA_3_W { + DATA_3_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_3_SPEC; +impl crate::RegisterSpec for DATA_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_3::R`](R) reader structure"] +impl crate::Readable for DATA_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_3::W`](W) writer structure"] +impl crate::Writable for DATA_3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_3 to value 0"] +impl crate::Resettable for DATA_3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_4.rs b/esp32p4/src/twai0/data_4.rs new file mode 100644 index 0000000000..23911d9853 --- /dev/null +++ b/esp32p4/src/twai0/data_4.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_4` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_4` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_4` reader - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4."] +pub type DATA_4_R = crate::FieldReader; +#[doc = "Field `DATA_4` writer - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4."] +pub type DATA_4_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4."] + #[inline(always)] + pub fn data_4(&self) -> DATA_4_R { + DATA_4_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_4") + .field("data_4", &format_args!("{}", self.data_4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4."] + #[inline(always)] + #[must_use] + pub fn data_4(&mut self) -> DATA_4_W { + DATA_4_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_4_SPEC; +impl crate::RegisterSpec for DATA_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_4::R`](R) reader structure"] +impl crate::Readable for DATA_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_4::W`](W) writer structure"] +impl crate::Writable for DATA_4_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_4 to value 0"] +impl crate::Resettable for DATA_4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_5.rs b/esp32p4/src/twai0/data_5.rs new file mode 100644 index 0000000000..194a30972f --- /dev/null +++ b/esp32p4/src/twai0/data_5.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_5` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_5` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_5` reader - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5."] +pub type DATA_5_R = crate::FieldReader; +#[doc = "Field `DATA_5` writer - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5."] +pub type DATA_5_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5."] + #[inline(always)] + pub fn data_5(&self) -> DATA_5_R { + DATA_5_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_5") + .field("data_5", &format_args!("{}", self.data_5().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5."] + #[inline(always)] + #[must_use] + pub fn data_5(&mut self) -> DATA_5_W { + DATA_5_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_5_SPEC; +impl crate::RegisterSpec for DATA_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_5::R`](R) reader structure"] +impl crate::Readable for DATA_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_5::W`](W) writer structure"] +impl crate::Writable for DATA_5_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_5 to value 0"] +impl crate::Resettable for DATA_5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_6.rs b/esp32p4/src/twai0/data_6.rs new file mode 100644 index 0000000000..8a7e947b97 --- /dev/null +++ b/esp32p4/src/twai0/data_6.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_6` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_6` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_6` reader - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6."] +pub type DATA_6_R = crate::FieldReader; +#[doc = "Field `DATA_6` writer - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6."] +pub type DATA_6_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6."] + #[inline(always)] + pub fn data_6(&self) -> DATA_6_R { + DATA_6_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_6") + .field("data_6", &format_args!("{}", self.data_6().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6."] + #[inline(always)] + #[must_use] + pub fn data_6(&mut self) -> DATA_6_W { + DATA_6_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_6_SPEC; +impl crate::RegisterSpec for DATA_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_6::R`](R) reader structure"] +impl crate::Readable for DATA_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_6::W`](W) writer structure"] +impl crate::Writable for DATA_6_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_6 to value 0"] +impl crate::Resettable for DATA_6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_7.rs b/esp32p4/src/twai0/data_7.rs new file mode 100644 index 0000000000..0fa2ee5cd4 --- /dev/null +++ b/esp32p4/src/twai0/data_7.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_7` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_7` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_7` reader - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7."] +pub type DATA_7_R = crate::FieldReader; +#[doc = "Field `DATA_7` writer - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7."] +pub type DATA_7_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7."] + #[inline(always)] + pub fn data_7(&self) -> DATA_7_R { + DATA_7_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_7") + .field("data_7", &format_args!("{}", self.data_7().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7."] + #[inline(always)] + #[must_use] + pub fn data_7(&mut self) -> DATA_7_W { + DATA_7_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_7_SPEC; +impl crate::RegisterSpec for DATA_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_7::R`](R) reader structure"] +impl crate::Readable for DATA_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_7::W`](W) writer structure"] +impl crate::Writable for DATA_7_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_7 to value 0"] +impl crate::Resettable for DATA_7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_8.rs b/esp32p4/src/twai0/data_8.rs new file mode 100644 index 0000000000..5308febbc7 --- /dev/null +++ b/esp32p4/src/twai0/data_8.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_8` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_8` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_8` reader - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8."] +pub type DATA_8_R = crate::FieldReader; +#[doc = "Field `DATA_8` writer - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8."] +pub type DATA_8_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8."] + #[inline(always)] + pub fn data_8(&self) -> DATA_8_R { + DATA_8_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_8") + .field("data_8", &format_args!("{}", self.data_8().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8."] + #[inline(always)] + #[must_use] + pub fn data_8(&mut self) -> DATA_8_W { + DATA_8_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_8_SPEC; +impl crate::RegisterSpec for DATA_8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_8::R`](R) reader structure"] +impl crate::Readable for DATA_8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_8::W`](W) writer structure"] +impl crate::Writable for DATA_8_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_8 to value 0"] +impl crate::Resettable for DATA_8_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/data_9.rs b/esp32p4/src/twai0/data_9.rs new file mode 100644 index 0000000000..2a65bf2afd --- /dev/null +++ b/esp32p4/src/twai0/data_9.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATA_9` reader"] +pub type R = crate::R; +#[doc = "Register `DATA_9` writer"] +pub type W = crate::W; +#[doc = "Field `DATA_9` reader - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9."] +pub type DATA_9_R = crate::FieldReader; +#[doc = "Field `DATA_9` writer - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9."] +pub type DATA_9_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9."] + #[inline(always)] + pub fn data_9(&self) -> DATA_9_R { + DATA_9_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATA_9") + .field("data_9", &format_args!("{}", self.data_9().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9."] + #[inline(always)] + #[must_use] + pub fn data_9(&mut self) -> DATA_9_W { + DATA_9_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Data register 9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATA_9_SPEC; +impl crate::RegisterSpec for DATA_9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_9::R`](R) reader structure"] +impl crate::Readable for DATA_9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`data_9::W`](W) writer structure"] +impl crate::Writable for DATA_9_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA_9 to value 0"] +impl crate::Resettable for DATA_9_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/eco_cfg.rs b/esp32p4/src/twai0/eco_cfg.rs new file mode 100644 index 0000000000..e4643f6f4c --- /dev/null +++ b/esp32p4/src/twai0/eco_cfg.rs @@ -0,0 +1,71 @@ +#[doc = "Register `ECO_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `RDN_ENA` reader - Enable eco module."] +pub type RDN_ENA_R = crate::BitReader; +#[doc = "Field `RDN_ENA` writer - Enable eco module."] +pub type RDN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RDN_RESULT` reader - Output of eco module."] +pub type RDN_RESULT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Enable eco module."] + #[inline(always)] + pub fn rdn_ena(&self) -> RDN_ENA_R { + RDN_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Output of eco module."] + #[inline(always)] + pub fn rdn_result(&self) -> RDN_RESULT_R { + RDN_RESULT_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_CFG") + .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit())) + .field("rdn_result", &format_args!("{}", self.rdn_result().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable eco module."] + #[inline(always)] + #[must_use] + pub fn rdn_ena(&mut self) -> RDN_ENA_W { + RDN_ENA_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "ECO configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_CFG_SPEC; +impl crate::RegisterSpec for ECO_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_cfg::R`](R) reader structure"] +impl crate::Readable for ECO_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_cfg::W`](W) writer structure"] +impl crate::Writable for ECO_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_CFG to value 0x02"] +impl crate::Resettable for ECO_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/twai0/err_code_cap.rs b/esp32p4/src/twai0/err_code_cap.rs new file mode 100644 index 0000000000..45244ce1a3 --- /dev/null +++ b/esp32p4/src/twai0/err_code_cap.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ERR_CODE_CAP` reader"] +pub type R = crate::R; +#[doc = "Field `ERR_CAPTURE_CODE_SEGMENT` reader - This register contains information about the location of errors on the bus."] +pub type ERR_CAPTURE_CODE_SEGMENT_R = crate::FieldReader; +#[doc = "Field `ERR_CAPTURE_CODE_DIRECTION` reader - 1: RX, error occurred during reception. 0: TX, error occurred during transmission."] +pub type ERR_CAPTURE_CODE_DIRECTION_R = crate::BitReader; +#[doc = "Field `ERR_CAPTURE_CODE_TYPE` reader - 00: bit error. 01: form error. 10:stuff error. 11:other type of error."] +pub type ERR_CAPTURE_CODE_TYPE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - This register contains information about the location of errors on the bus."] + #[inline(always)] + pub fn err_capture_code_segment(&self) -> ERR_CAPTURE_CODE_SEGMENT_R { + ERR_CAPTURE_CODE_SEGMENT_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - 1: RX, error occurred during reception. 0: TX, error occurred during transmission."] + #[inline(always)] + pub fn err_capture_code_direction(&self) -> ERR_CAPTURE_CODE_DIRECTION_R { + ERR_CAPTURE_CODE_DIRECTION_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - 00: bit error. 01: form error. 10:stuff error. 11:other type of error."] + #[inline(always)] + pub fn err_capture_code_type(&self) -> ERR_CAPTURE_CODE_TYPE_R { + ERR_CAPTURE_CODE_TYPE_R::new(((self.bits >> 6) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ERR_CODE_CAP") + .field( + "err_capture_code_segment", + &format_args!("{}", self.err_capture_code_segment().bits()), + ) + .field( + "err_capture_code_direction", + &format_args!("{}", self.err_capture_code_direction().bit()), + ) + .field( + "err_capture_code_type", + &format_args!("{}", self.err_capture_code_type().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TWAI error info capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_code_cap::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ERR_CODE_CAP_SPEC; +impl crate::RegisterSpec for ERR_CODE_CAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`err_code_cap::R`](R) reader structure"] +impl crate::Readable for ERR_CODE_CAP_SPEC {} +#[doc = "`reset()` method sets ERR_CODE_CAP to value 0"] +impl crate::Resettable for ERR_CODE_CAP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/err_warning_limit.rs b/esp32p4/src/twai0/err_warning_limit.rs new file mode 100644 index 0000000000..33ce83a9ec --- /dev/null +++ b/esp32p4/src/twai0/err_warning_limit.rs @@ -0,0 +1,66 @@ +#[doc = "Register `ERR_WARNING_LIMIT` reader"] +pub type R = crate::R; +#[doc = "Register `ERR_WARNING_LIMIT` writer"] +pub type W = crate::W; +#[doc = "Field `ERR_WARNING_LIMIT` reader - The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode."] +pub type ERR_WARNING_LIMIT_R = crate::FieldReader; +#[doc = "Field `ERR_WARNING_LIMIT` writer - The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode."] +pub type ERR_WARNING_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + pub fn err_warning_limit(&self) -> ERR_WARNING_LIMIT_R { + ERR_WARNING_LIMIT_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ERR_WARNING_LIMIT") + .field( + "err_warning_limit", + &format_args!("{}", self.err_warning_limit().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + #[must_use] + pub fn err_warning_limit(&mut self) -> ERR_WARNING_LIMIT_W { + ERR_WARNING_LIMIT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TWAI error threshold configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_warning_limit::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err_warning_limit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ERR_WARNING_LIMIT_SPEC; +impl crate::RegisterSpec for ERR_WARNING_LIMIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`err_warning_limit::R`](R) reader structure"] +impl crate::Readable for ERR_WARNING_LIMIT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`err_warning_limit::W`](W) writer structure"] +impl crate::Writable for ERR_WARNING_LIMIT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ERR_WARNING_LIMIT to value 0x60"] +impl crate::Resettable for ERR_WARNING_LIMIT_SPEC { + const RESET_VALUE: Self::Ux = 0x60; +} diff --git a/esp32p4/src/twai0/hw_cfg.rs b/esp32p4/src/twai0/hw_cfg.rs new file mode 100644 index 0000000000..ed1de3ef26 --- /dev/null +++ b/esp32p4/src/twai0/hw_cfg.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HW_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `HW_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `HW_STANDBY_EN` reader - Enable function that hardware control standby pin."] +pub type HW_STANDBY_EN_R = crate::BitReader; +#[doc = "Field `HW_STANDBY_EN` writer - Enable function that hardware control standby pin."] +pub type HW_STANDBY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable function that hardware control standby pin."] + #[inline(always)] + pub fn hw_standby_en(&self) -> HW_STANDBY_EN_R { + HW_STANDBY_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HW_CFG") + .field( + "hw_standby_en", + &format_args!("{}", self.hw_standby_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable function that hardware control standby pin."] + #[inline(always)] + #[must_use] + pub fn hw_standby_en(&mut self) -> HW_STANDBY_EN_W { + HW_STANDBY_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Hardware configure standby pin.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HW_CFG_SPEC; +impl crate::RegisterSpec for HW_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hw_cfg::R`](R) reader structure"] +impl crate::Readable for HW_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hw_cfg::W`](W) writer structure"] +impl crate::Writable for HW_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HW_CFG to value 0"] +impl crate::Resettable for HW_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/hw_standby_cnt.rs b/esp32p4/src/twai0/hw_standby_cnt.rs new file mode 100644 index 0000000000..a602773f9a --- /dev/null +++ b/esp32p4/src/twai0/hw_standby_cnt.rs @@ -0,0 +1,66 @@ +#[doc = "Register `HW_STANDBY_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `HW_STANDBY_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `STANDBY_WAIT_CNT` reader - Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled."] +pub type STANDBY_WAIT_CNT_R = crate::FieldReader; +#[doc = "Field `STANDBY_WAIT_CNT` writer - Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled."] +pub type STANDBY_WAIT_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled."] + #[inline(always)] + pub fn standby_wait_cnt(&self) -> STANDBY_WAIT_CNT_R { + STANDBY_WAIT_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HW_STANDBY_CNT") + .field( + "standby_wait_cnt", + &format_args!("{}", self.standby_wait_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled."] + #[inline(always)] + #[must_use] + pub fn standby_wait_cnt(&mut self) -> STANDBY_WAIT_CNT_W { + STANDBY_WAIT_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure standby counter.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_standby_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hw_standby_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HW_STANDBY_CNT_SPEC; +impl crate::RegisterSpec for HW_STANDBY_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hw_standby_cnt::R`](R) reader structure"] +impl crate::Readable for HW_STANDBY_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hw_standby_cnt::W`](W) writer structure"] +impl crate::Writable for HW_STANDBY_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HW_STANDBY_CNT to value 0x01"] +impl crate::Resettable for HW_STANDBY_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/twai0/idle_intr_cnt.rs b/esp32p4/src/twai0/idle_intr_cnt.rs new file mode 100644 index 0000000000..dc96fda2b9 --- /dev/null +++ b/esp32p4/src/twai0/idle_intr_cnt.rs @@ -0,0 +1,66 @@ +#[doc = "Register `IDLE_INTR_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `IDLE_INTR_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `IDLE_INTR_CNT` reader - Configure the number of cycles before triggering idle interrupt."] +pub type IDLE_INTR_CNT_R = crate::FieldReader; +#[doc = "Field `IDLE_INTR_CNT` writer - Configure the number of cycles before triggering idle interrupt."] +pub type IDLE_INTR_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configure the number of cycles before triggering idle interrupt."] + #[inline(always)] + pub fn idle_intr_cnt(&self) -> IDLE_INTR_CNT_R { + IDLE_INTR_CNT_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IDLE_INTR_CNT") + .field( + "idle_intr_cnt", + &format_args!("{}", self.idle_intr_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configure the number of cycles before triggering idle interrupt."] + #[inline(always)] + #[must_use] + pub fn idle_intr_cnt(&mut self) -> IDLE_INTR_CNT_W { + IDLE_INTR_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configure idle interrupt counter.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle_intr_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idle_intr_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IDLE_INTR_CNT_SPEC; +impl crate::RegisterSpec for IDLE_INTR_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`idle_intr_cnt::R`](R) reader structure"] +impl crate::Readable for IDLE_INTR_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`idle_intr_cnt::W`](W) writer structure"] +impl crate::Writable for IDLE_INTR_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IDLE_INTR_CNT to value 0x01"] +impl crate::Resettable for IDLE_INTR_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/twai0/interrupt.rs b/esp32p4/src/twai0/interrupt.rs new file mode 100644 index 0000000000..f651b98f39 --- /dev/null +++ b/esp32p4/src/twai0/interrupt.rs @@ -0,0 +1,124 @@ +#[doc = "Register `INTERRUPT` reader"] +pub type R = crate::R; +#[doc = "Field `RECEIVE_INT_ST` reader - 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset"] +pub type RECEIVE_INT_ST_R = crate::BitReader; +#[doc = "Field `TRANSMIT_INT_ST` reader - 1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset"] +pub type TRANSMIT_INT_ST_R = crate::BitReader; +#[doc = "Field `ERR_WARNING_INT_ST` reader - 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset"] +pub type ERR_WARNING_INT_ST_R = crate::BitReader; +#[doc = "Field `DATA_OVERRUN_INT_ST` reader - 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset"] +pub type DATA_OVERRUN_INT_ST_R = crate::BitReader; +#[doc = "Field `TS_COUNTER_OVFL_INT_ST` reader - 1: this bit is set then the timestamp counter reaches the maximum value and overflow."] +pub type TS_COUNTER_OVFL_INT_ST_R = crate::BitReader; +#[doc = "Field `ERR_PASSIVE_INT_ST` reader - 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset"] +pub type ERR_PASSIVE_INT_ST_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST_INT_ST` reader - 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset"] +pub type ARBITRATION_LOST_INT_ST_R = crate::BitReader; +#[doc = "Field `BUS_ERR_INT_ST` reader - 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset"] +pub type BUS_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `IDLE_INT_ST` reader - 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset"] +pub type IDLE_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset"] + #[inline(always)] + pub fn receive_int_st(&self) -> RECEIVE_INT_ST_R { + RECEIVE_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset"] + #[inline(always)] + pub fn transmit_int_st(&self) -> TRANSMIT_INT_ST_R { + TRANSMIT_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset"] + #[inline(always)] + pub fn err_warning_int_st(&self) -> ERR_WARNING_INT_ST_R { + ERR_WARNING_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset"] + #[inline(always)] + pub fn data_overrun_int_st(&self) -> DATA_OVERRUN_INT_ST_R { + DATA_OVERRUN_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1: this bit is set then the timestamp counter reaches the maximum value and overflow."] + #[inline(always)] + pub fn ts_counter_ovfl_int_st(&self) -> TS_COUNTER_OVFL_INT_ST_R { + TS_COUNTER_OVFL_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset"] + #[inline(always)] + pub fn err_passive_int_st(&self) -> ERR_PASSIVE_INT_ST_R { + ERR_PASSIVE_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset"] + #[inline(always)] + pub fn arbitration_lost_int_st(&self) -> ARBITRATION_LOST_INT_ST_R { + ARBITRATION_LOST_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset"] + #[inline(always)] + pub fn bus_err_int_st(&self) -> BUS_ERR_INT_ST_R { + BUS_ERR_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset"] + #[inline(always)] + pub fn idle_int_st(&self) -> IDLE_INT_ST_R { + IDLE_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTERRUPT") + .field( + "receive_int_st", + &format_args!("{}", self.receive_int_st().bit()), + ) + .field( + "transmit_int_st", + &format_args!("{}", self.transmit_int_st().bit()), + ) + .field( + "err_warning_int_st", + &format_args!("{}", self.err_warning_int_st().bit()), + ) + .field( + "data_overrun_int_st", + &format_args!("{}", self.data_overrun_int_st().bit()), + ) + .field( + "ts_counter_ovfl_int_st", + &format_args!("{}", self.ts_counter_ovfl_int_st().bit()), + ) + .field( + "err_passive_int_st", + &format_args!("{}", self.err_passive_int_st().bit()), + ) + .field( + "arbitration_lost_int_st", + &format_args!("{}", self.arbitration_lost_int_st().bit()), + ) + .field( + "bus_err_int_st", + &format_args!("{}", self.bus_err_int_st().bit()), + ) + .field("idle_int_st", &format_args!("{}", self.idle_int_st().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Interrupt signals' register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERRUPT_SPEC; +impl crate::RegisterSpec for INTERRUPT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interrupt::R`](R) reader structure"] +impl crate::Readable for INTERRUPT_SPEC {} +#[doc = "`reset()` method sets INTERRUPT to value 0"] +impl crate::Resettable for INTERRUPT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/interrupt_enable.rs b/esp32p4/src/twai0/interrupt_enable.rs new file mode 100644 index 0000000000..18b8b4d9ed --- /dev/null +++ b/esp32p4/src/twai0/interrupt_enable.rs @@ -0,0 +1,214 @@ +#[doc = "Register `INTERRUPT_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `INTERRUPT_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `EXT_RECEIVE_INT_ENA` reader - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"] +pub type EXT_RECEIVE_INT_ENA_R = crate::BitReader; +#[doc = "Field `EXT_RECEIVE_INT_ENA` writer - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"] +pub type EXT_RECEIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXT_TRANSMIT_INT_ENA` reader - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"] +pub type EXT_TRANSMIT_INT_ENA_R = crate::BitReader; +#[doc = "Field `EXT_TRANSMIT_INT_ENA` writer - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"] +pub type EXT_TRANSMIT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXT_ERR_WARNING_INT_ENA` reader - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"] +pub type EXT_ERR_WARNING_INT_ENA_R = crate::BitReader; +#[doc = "Field `EXT_ERR_WARNING_INT_ENA` writer - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"] +pub type EXT_ERR_WARNING_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXT_DATA_OVERRUN_INT_ENA` reader - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"] +pub type EXT_DATA_OVERRUN_INT_ENA_R = crate::BitReader; +#[doc = "Field `EXT_DATA_OVERRUN_INT_ENA` writer - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"] +pub type EXT_DATA_OVERRUN_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TS_COUNTER_OVFL_INT_ENA` reader - enable the timestamp counter overflow interrupt request."] +pub type TS_COUNTER_OVFL_INT_ENA_R = crate::BitReader; +#[doc = "Field `TS_COUNTER_OVFL_INT_ENA` writer - enable the timestamp counter overflow interrupt request."] +pub type TS_COUNTER_OVFL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERR_PASSIVE_INT_ENA` reader - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"] +pub type ERR_PASSIVE_INT_ENA_R = crate::BitReader; +#[doc = "Field `ERR_PASSIVE_INT_ENA` writer - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"] +pub type ERR_PASSIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBITRATION_LOST_INT_ENA` reader - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"] +pub type ARBITRATION_LOST_INT_ENA_R = crate::BitReader; +#[doc = "Field `ARBITRATION_LOST_INT_ENA` writer - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"] +pub type ARBITRATION_LOST_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUS_ERR_INT_ENA` reader - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"] +pub type BUS_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `BUS_ERR_INT_ENA` writer - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"] +pub type BUS_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE_INT_ENA` reader - 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable"] +pub type IDLE_INT_ENA_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"] + #[inline(always)] + pub fn ext_receive_int_ena(&self) -> EXT_RECEIVE_INT_ENA_R { + EXT_RECEIVE_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"] + #[inline(always)] + pub fn ext_transmit_int_ena(&self) -> EXT_TRANSMIT_INT_ENA_R { + EXT_TRANSMIT_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"] + #[inline(always)] + pub fn ext_err_warning_int_ena(&self) -> EXT_ERR_WARNING_INT_ENA_R { + EXT_ERR_WARNING_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"] + #[inline(always)] + pub fn ext_data_overrun_int_ena(&self) -> EXT_DATA_OVERRUN_INT_ENA_R { + EXT_DATA_OVERRUN_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - enable the timestamp counter overflow interrupt request."] + #[inline(always)] + pub fn ts_counter_ovfl_int_ena(&self) -> TS_COUNTER_OVFL_INT_ENA_R { + TS_COUNTER_OVFL_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"] + #[inline(always)] + pub fn err_passive_int_ena(&self) -> ERR_PASSIVE_INT_ENA_R { + ERR_PASSIVE_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"] + #[inline(always)] + pub fn arbitration_lost_int_ena(&self) -> ARBITRATION_LOST_INT_ENA_R { + ARBITRATION_LOST_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"] + #[inline(always)] + pub fn bus_err_int_ena(&self) -> BUS_ERR_INT_ENA_R { + BUS_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable"] + #[inline(always)] + pub fn idle_int_ena(&self) -> IDLE_INT_ENA_R { + IDLE_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INTERRUPT_ENABLE") + .field( + "ext_receive_int_ena", + &format_args!("{}", self.ext_receive_int_ena().bit()), + ) + .field( + "ext_transmit_int_ena", + &format_args!("{}", self.ext_transmit_int_ena().bit()), + ) + .field( + "ext_err_warning_int_ena", + &format_args!("{}", self.ext_err_warning_int_ena().bit()), + ) + .field( + "ext_data_overrun_int_ena", + &format_args!("{}", self.ext_data_overrun_int_ena().bit()), + ) + .field( + "ts_counter_ovfl_int_ena", + &format_args!("{}", self.ts_counter_ovfl_int_ena().bit()), + ) + .field( + "err_passive_int_ena", + &format_args!("{}", self.err_passive_int_ena().bit()), + ) + .field( + "arbitration_lost_int_ena", + &format_args!("{}", self.arbitration_lost_int_ena().bit()), + ) + .field( + "bus_err_int_ena", + &format_args!("{}", self.bus_err_int_ena().bit()), + ) + .field( + "idle_int_ena", + &format_args!("{}", self.idle_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"] + #[inline(always)] + #[must_use] + pub fn ext_receive_int_ena(&mut self) -> EXT_RECEIVE_INT_ENA_W { + EXT_RECEIVE_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable"] + #[inline(always)] + #[must_use] + pub fn ext_transmit_int_ena(&mut self) -> EXT_TRANSMIT_INT_ENA_W { + EXT_TRANSMIT_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"] + #[inline(always)] + #[must_use] + pub fn ext_err_warning_int_ena(&mut self) -> EXT_ERR_WARNING_INT_ENA_W { + EXT_ERR_WARNING_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable"] + #[inline(always)] + #[must_use] + pub fn ext_data_overrun_int_ena( + &mut self, + ) -> EXT_DATA_OVERRUN_INT_ENA_W { + EXT_DATA_OVERRUN_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - enable the timestamp counter overflow interrupt request."] + #[inline(always)] + #[must_use] + pub fn ts_counter_ovfl_int_ena(&mut self) -> TS_COUNTER_OVFL_INT_ENA_W { + TS_COUNTER_OVFL_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable"] + #[inline(always)] + #[must_use] + pub fn err_passive_int_ena(&mut self) -> ERR_PASSIVE_INT_ENA_W { + ERR_PASSIVE_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable"] + #[inline(always)] + #[must_use] + pub fn arbitration_lost_int_ena( + &mut self, + ) -> ARBITRATION_LOST_INT_ENA_W { + ARBITRATION_LOST_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable"] + #[inline(always)] + #[must_use] + pub fn bus_err_int_ena(&mut self) -> BUS_ERR_INT_ENA_W { + BUS_ERR_INT_ENA_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERRUPT_ENABLE_SPEC; +impl crate::RegisterSpec for INTERRUPT_ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interrupt_enable::R`](R) reader structure"] +impl crate::Readable for INTERRUPT_ENABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interrupt_enable::W`](W) writer structure"] +impl crate::Writable for INTERRUPT_ENABLE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTERRUPT_ENABLE to value 0"] +impl crate::Resettable for INTERRUPT_ENABLE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/mode.rs b/esp32p4/src/twai0/mode.rs new file mode 100644 index 0000000000..2ed7be92cf --- /dev/null +++ b/esp32p4/src/twai0/mode.rs @@ -0,0 +1,120 @@ +#[doc = "Register `MODE` reader"] +pub type R = crate::R; +#[doc = "Register `MODE` writer"] +pub type W = crate::W; +#[doc = "Field `RESET_MODE` reader - 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode."] +pub type RESET_MODE_R = crate::BitReader; +#[doc = "Field `RESET_MODE` writer - 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode."] +pub type RESET_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LISTEN_ONLY_MODE` reader - 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal."] +pub type LISTEN_ONLY_MODE_R = crate::BitReader; +#[doc = "Field `LISTEN_ONLY_MODE` writer - 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal."] +pub type LISTEN_ONLY_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SELF_TEST_MODE` reader - 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission."] +pub type SELF_TEST_MODE_R = crate::BitReader; +#[doc = "Field `SELF_TEST_MODE` writer - 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission."] +pub type SELF_TEST_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACCEPTANCE_FILTER_MODE` reader - 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active)."] +pub type ACCEPTANCE_FILTER_MODE_R = crate::BitReader; +#[doc = "Field `ACCEPTANCE_FILTER_MODE` writer - 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active)."] +pub type ACCEPTANCE_FILTER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode."] + #[inline(always)] + pub fn reset_mode(&self) -> RESET_MODE_R { + RESET_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal."] + #[inline(always)] + pub fn listen_only_mode(&self) -> LISTEN_ONLY_MODE_R { + LISTEN_ONLY_MODE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission."] + #[inline(always)] + pub fn self_test_mode(&self) -> SELF_TEST_MODE_R { + SELF_TEST_MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active)."] + #[inline(always)] + pub fn acceptance_filter_mode(&self) -> ACCEPTANCE_FILTER_MODE_R { + ACCEPTANCE_FILTER_MODE_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MODE") + .field("reset_mode", &format_args!("{}", self.reset_mode().bit())) + .field( + "listen_only_mode", + &format_args!("{}", self.listen_only_mode().bit()), + ) + .field( + "self_test_mode", + &format_args!("{}", self.self_test_mode().bit()), + ) + .field( + "acceptance_filter_mode", + &format_args!("{}", self.acceptance_filter_mode().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode."] + #[inline(always)] + #[must_use] + pub fn reset_mode(&mut self) -> RESET_MODE_W { + RESET_MODE_W::new(self, 0) + } + #[doc = "Bit 1 - 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal."] + #[inline(always)] + #[must_use] + pub fn listen_only_mode(&mut self) -> LISTEN_ONLY_MODE_W { + LISTEN_ONLY_MODE_W::new(self, 1) + } + #[doc = "Bit 2 - 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission."] + #[inline(always)] + #[must_use] + pub fn self_test_mode(&mut self) -> SELF_TEST_MODE_W { + SELF_TEST_MODE_W::new(self, 2) + } + #[doc = "Bit 3 - 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active)."] + #[inline(always)] + #[must_use] + pub fn acceptance_filter_mode(&mut self) -> ACCEPTANCE_FILTER_MODE_W { + ACCEPTANCE_FILTER_MODE_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "TWAI mode register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MODE_SPEC; +impl crate::RegisterSpec for MODE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mode::R`](R) reader structure"] +impl crate::Readable for MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"] +impl crate::Writable for MODE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MODE to value 0x01"] +impl crate::Resettable for MODE_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/twai0/rx_err_cnt.rs b/esp32p4/src/twai0/rx_err_cnt.rs new file mode 100644 index 0000000000..f8432c29b5 --- /dev/null +++ b/esp32p4/src/twai0/rx_err_cnt.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RX_ERR_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `RX_ERR_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `RX_ERR_CNT` reader - The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."] +pub type RX_ERR_CNT_R = crate::FieldReader; +#[doc = "Field `RX_ERR_CNT` writer - The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."] +pub type RX_ERR_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + pub fn rx_err_cnt(&self) -> RX_ERR_CNT_R { + RX_ERR_CNT_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_ERR_CNT") + .field("rx_err_cnt", &format_args!("{}", self.rx_err_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + #[must_use] + pub fn rx_err_cnt(&mut self) -> RX_ERR_CNT_W { + RX_ERR_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Rx error counter register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_err_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_err_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_ERR_CNT_SPEC; +impl crate::RegisterSpec for RX_ERR_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_err_cnt::R`](R) reader structure"] +impl crate::Readable for RX_ERR_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_err_cnt::W`](W) writer structure"] +impl crate::Writable for RX_ERR_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_ERR_CNT to value 0"] +impl crate::Resettable for RX_ERR_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/rx_message_counter.rs b/esp32p4/src/twai0/rx_message_counter.rs new file mode 100644 index 0000000000..c8b25ce780 --- /dev/null +++ b/esp32p4/src/twai0/rx_message_counter.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RX_MESSAGE_COUNTER` reader"] +pub type R = crate::R; +#[doc = "Field `RX_MESSAGE_COUNTER` reader - Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command."] +pub type RX_MESSAGE_COUNTER_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:6 - Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command."] + #[inline(always)] + pub fn rx_message_counter(&self) -> RX_MESSAGE_COUNTER_R { + RX_MESSAGE_COUNTER_R::new((self.bits & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_MESSAGE_COUNTER") + .field( + "rx_message_counter", + &format_args!("{}", self.rx_message_counter().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Received message counter register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_message_counter::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_MESSAGE_COUNTER_SPEC; +impl crate::RegisterSpec for RX_MESSAGE_COUNTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_message_counter::R`](R) reader structure"] +impl crate::Readable for RX_MESSAGE_COUNTER_SPEC {} +#[doc = "`reset()` method sets RX_MESSAGE_COUNTER to value 0"] +impl crate::Resettable for RX_MESSAGE_COUNTER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/status.rs b/esp32p4/src/twai0/status.rs new file mode 100644 index 0000000000..c1c45664de --- /dev/null +++ b/esp32p4/src/twai0/status.rs @@ -0,0 +1,112 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `RECEIVE_BUFFER` reader - 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available"] +pub type RECEIVE_BUFFER_R = crate::BitReader; +#[doc = "Field `OVERRUN` reader - 1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given"] +pub type OVERRUN_R = crate::BitReader; +#[doc = "Field `TRANSMIT_BUFFER` reader - 1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted"] +pub type TRANSMIT_BUFFER_R = crate::BitReader; +#[doc = "Field `TRANSMISSION_COMPLETE` reader - 1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed"] +pub type TRANSMISSION_COMPLETE_R = crate::BitReader; +#[doc = "Field `RECEIVE` reader - 1: receive, the TWAI controller is receiving a message. 0: idle"] +pub type RECEIVE_R = crate::BitReader; +#[doc = "Field `TRANSMIT` reader - 1: transmit, the TWAI controller is transmitting a message. 0: idle"] +pub type TRANSMIT_R = crate::BitReader; +#[doc = "Field `ERR` reader - 1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `NODE_BUS_OFF` reader - 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities"] +pub type NODE_BUS_OFF_R = crate::BitReader; +#[doc = "Field `MISS` reader - 1: current message is destroyed because of FIFO overflow."] +pub type MISS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available"] + #[inline(always)] + pub fn receive_buffer(&self) -> RECEIVE_BUFFER_R { + RECEIVE_BUFFER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted"] + #[inline(always)] + pub fn transmit_buffer(&self) -> TRANSMIT_BUFFER_R { + TRANSMIT_BUFFER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed"] + #[inline(always)] + pub fn transmission_complete(&self) -> TRANSMISSION_COMPLETE_R { + TRANSMISSION_COMPLETE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1: receive, the TWAI controller is receiving a message. 0: idle"] + #[inline(always)] + pub fn receive(&self) -> RECEIVE_R { + RECEIVE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - 1: transmit, the TWAI controller is transmitting a message. 0: idle"] + #[inline(always)] + pub fn transmit(&self) -> TRANSMIT_R { + TRANSMIT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - 1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities"] + #[inline(always)] + pub fn node_bus_off(&self) -> NODE_BUS_OFF_R { + NODE_BUS_OFF_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - 1: current message is destroyed because of FIFO overflow."] + #[inline(always)] + pub fn miss(&self) -> MISS_R { + MISS_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field( + "receive_buffer", + &format_args!("{}", self.receive_buffer().bit()), + ) + .field("overrun", &format_args!("{}", self.overrun().bit())) + .field( + "transmit_buffer", + &format_args!("{}", self.transmit_buffer().bit()), + ) + .field( + "transmission_complete", + &format_args!("{}", self.transmission_complete().bit()), + ) + .field("receive", &format_args!("{}", self.receive().bit())) + .field("transmit", &format_args!("{}", self.transmit().bit())) + .field("err", &format_args!("{}", self.err().bit())) + .field( + "node_bus_off", + &format_args!("{}", self.node_bus_off().bit()), + ) + .field("miss", &format_args!("{}", self.miss().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "TWAI status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/sw_standby_cfg.rs b/esp32p4/src/twai0/sw_standby_cfg.rs new file mode 100644 index 0000000000..121d43a0b5 --- /dev/null +++ b/esp32p4/src/twai0/sw_standby_cfg.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SW_STANDBY_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `SW_STANDBY_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `SW_STANDBY_EN` reader - Enable standby pin."] +pub type SW_STANDBY_EN_R = crate::BitReader; +#[doc = "Field `SW_STANDBY_EN` writer - Enable standby pin."] +pub type SW_STANDBY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_STANDBY_CLR` reader - Clear standby pin."] +pub type SW_STANDBY_CLR_R = crate::BitReader; +#[doc = "Field `SW_STANDBY_CLR` writer - Clear standby pin."] +pub type SW_STANDBY_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable standby pin."] + #[inline(always)] + pub fn sw_standby_en(&self) -> SW_STANDBY_EN_R { + SW_STANDBY_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clear standby pin."] + #[inline(always)] + pub fn sw_standby_clr(&self) -> SW_STANDBY_CLR_R { + SW_STANDBY_CLR_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SW_STANDBY_CFG") + .field( + "sw_standby_en", + &format_args!("{}", self.sw_standby_en().bit()), + ) + .field( + "sw_standby_clr", + &format_args!("{}", self.sw_standby_clr().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable standby pin."] + #[inline(always)] + #[must_use] + pub fn sw_standby_en(&mut self) -> SW_STANDBY_EN_W { + SW_STANDBY_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Clear standby pin."] + #[inline(always)] + #[must_use] + pub fn sw_standby_clr(&mut self) -> SW_STANDBY_CLR_W { + SW_STANDBY_CLR_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Software configure standby pin directly.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_standby_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_standby_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_STANDBY_CFG_SPEC; +impl crate::RegisterSpec for SW_STANDBY_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_standby_cfg::R`](R) reader structure"] +impl crate::Readable for SW_STANDBY_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_standby_cfg::W`](W) writer structure"] +impl crate::Writable for SW_STANDBY_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SW_STANDBY_CFG to value 0x02"] +impl crate::Resettable for SW_STANDBY_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/twai0/timestamp_cfg.rs b/esp32p4/src/twai0/timestamp_cfg.rs new file mode 100644 index 0000000000..8fdea96cd7 --- /dev/null +++ b/esp32p4/src/twai0/timestamp_cfg.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TIMESTAMP_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `TIMESTAMP_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `TS_ENABLE` reader - enable the timestamp collection function."] +pub type TS_ENABLE_R = crate::BitReader; +#[doc = "Field `TS_ENABLE` writer - enable the timestamp collection function."] +pub type TS_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - enable the timestamp collection function."] + #[inline(always)] + pub fn ts_enable(&self) -> TS_ENABLE_R { + TS_ENABLE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMESTAMP_CFG") + .field("ts_enable", &format_args!("{}", self.ts_enable().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - enable the timestamp collection function."] + #[inline(always)] + #[must_use] + pub fn ts_enable(&mut self) -> TS_ENABLE_W { + TS_ENABLE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timestamp configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMESTAMP_CFG_SPEC; +impl crate::RegisterSpec for TIMESTAMP_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timestamp_cfg::R`](R) reader structure"] +impl crate::Readable for TIMESTAMP_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timestamp_cfg::W`](W) writer structure"] +impl crate::Writable for TIMESTAMP_CFG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMESTAMP_CFG to value 0"] +impl crate::Resettable for TIMESTAMP_CFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/timestamp_data.rs b/esp32p4/src/twai0/timestamp_data.rs new file mode 100644 index 0000000000..d178d856da --- /dev/null +++ b/esp32p4/src/twai0/timestamp_data.rs @@ -0,0 +1,39 @@ +#[doc = "Register `TIMESTAMP_DATA` reader"] +pub type R = crate::R; +#[doc = "Field `TIMESTAMP_DATA` reader - Data of timestamp of a CAN frame."] +pub type TIMESTAMP_DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Data of timestamp of a CAN frame."] + #[inline(always)] + pub fn timestamp_data(&self) -> TIMESTAMP_DATA_R { + TIMESTAMP_DATA_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMESTAMP_DATA") + .field( + "timestamp_data", + &format_args!("{}", self.timestamp_data().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Timestamp data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMESTAMP_DATA_SPEC; +impl crate::RegisterSpec for TIMESTAMP_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timestamp_data::R`](R) reader structure"] +impl crate::Readable for TIMESTAMP_DATA_SPEC {} +#[doc = "`reset()` method sets TIMESTAMP_DATA to value 0"] +impl crate::Resettable for TIMESTAMP_DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/twai0/timestamp_prescaler.rs b/esp32p4/src/twai0/timestamp_prescaler.rs new file mode 100644 index 0000000000..adff7d964d --- /dev/null +++ b/esp32p4/src/twai0/timestamp_prescaler.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TIMESTAMP_PRESCALER` reader"] +pub type R = crate::R; +#[doc = "Register `TIMESTAMP_PRESCALER` writer"] +pub type W = crate::W; +#[doc = "Field `TS_DIV_NUM` reader - Configures the clock division number of timestamp counter."] +pub type TS_DIV_NUM_R = crate::FieldReader; +#[doc = "Field `TS_DIV_NUM` writer - Configures the clock division number of timestamp counter."] +pub type TS_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Configures the clock division number of timestamp counter."] + #[inline(always)] + pub fn ts_div_num(&self) -> TS_DIV_NUM_R { + TS_DIV_NUM_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMESTAMP_PRESCALER") + .field("ts_div_num", &format_args!("{}", self.ts_div_num().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - Configures the clock division number of timestamp counter."] + #[inline(always)] + #[must_use] + pub fn ts_div_num(&mut self) -> TS_DIV_NUM_W { + TS_DIV_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timestamp configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_prescaler::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_prescaler::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMESTAMP_PRESCALER_SPEC; +impl crate::RegisterSpec for TIMESTAMP_PRESCALER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timestamp_prescaler::R`](R) reader structure"] +impl crate::Readable for TIMESTAMP_PRESCALER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timestamp_prescaler::W`](W) writer structure"] +impl crate::Writable for TIMESTAMP_PRESCALER_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TIMESTAMP_PRESCALER to value 0x1f"] +impl crate::Resettable for TIMESTAMP_PRESCALER_SPEC { + const RESET_VALUE: Self::Ux = 0x1f; +} diff --git a/esp32p4/src/twai0/tx_err_cnt.rs b/esp32p4/src/twai0/tx_err_cnt.rs new file mode 100644 index 0000000000..f0489e6245 --- /dev/null +++ b/esp32p4/src/twai0/tx_err_cnt.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TX_ERR_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `TX_ERR_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `TX_ERR_CNT` reader - The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."] +pub type TX_ERR_CNT_R = crate::FieldReader; +#[doc = "Field `TX_ERR_CNT` writer - The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."] +pub type TX_ERR_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + pub fn tx_err_cnt(&self) -> TX_ERR_CNT_R { + TX_ERR_CNT_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TX_ERR_CNT") + .field("tx_err_cnt", &format_args!("{}", self.tx_err_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."] + #[inline(always)] + #[must_use] + pub fn tx_err_cnt(&mut self) -> TX_ERR_CNT_W { + TX_ERR_CNT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tx error counter register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_err_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_err_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TX_ERR_CNT_SPEC; +impl crate::RegisterSpec for TX_ERR_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx_err_cnt::R`](R) reader structure"] +impl crate::Readable for TX_ERR_CNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tx_err_cnt::W`](W) writer structure"] +impl crate::Writable for TX_ERR_CNT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TX_ERR_CNT to value 0"] +impl crate::Resettable for TX_ERR_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0.rs b/esp32p4/src/uart0.rs new file mode 100644 index 0000000000..feed54d359 --- /dev/null +++ b/esp32p4/src/uart0.rs @@ -0,0 +1,389 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + fifo: FIFO, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + clkdiv_sync: CLKDIV_SYNC, + rx_filt: RX_FILT, + status: STATUS, + conf0_sync: CONF0_SYNC, + conf1: CONF1, + _reserved10: [u8; 0x04], + hwfc_conf_sync: HWFC_CONF_SYNC, + sleep_conf0: SLEEP_CONF0, + sleep_conf1: SLEEP_CONF1, + sleep_conf2: SLEEP_CONF2, + swfc_conf0_sync: SWFC_CONF0_SYNC, + swfc_conf1: SWFC_CONF1, + txbrk_conf_sync: TXBRK_CONF_SYNC, + idle_conf_sync: IDLE_CONF_SYNC, + rs485_conf_sync: RS485_CONF_SYNC, + at_cmd_precnt_sync: AT_CMD_PRECNT_SYNC, + at_cmd_postcnt_sync: AT_CMD_POSTCNT_SYNC, + at_cmd_gaptout_sync: AT_CMD_GAPTOUT_SYNC, + at_cmd_char_sync: AT_CMD_CHAR_SYNC, + mem_conf: MEM_CONF, + tout_conf_sync: TOUT_CONF_SYNC, + mem_tx_status: MEM_TX_STATUS, + mem_rx_status: MEM_RX_STATUS, + fsm_status: FSM_STATUS, + pospulse: POSPULSE, + negpulse: NEGPULSE, + lowpulse: LOWPULSE, + highpulse: HIGHPULSE, + rxd_cnt: RXD_CNT, + clk_conf: CLK_CONF, + date: DATE, + afifo_status: AFIFO_STATUS, + _reserved36: [u8; 0x04], + reg_update: REG_UPDATE, + id: ID, +} +impl RegisterBlock { + #[doc = "0x00 - FIFO data register"] + #[inline(always)] + pub const fn fifo(&self) -> &FIFO { + &self.fifo + } + #[doc = "0x04 - Raw interrupt status"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x08 - Masked interrupt status"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x0c - Interrupt enable bits"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x10 - Interrupt clear bits"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x14 - Clock divider configuration"] + #[inline(always)] + pub const fn clkdiv_sync(&self) -> &CLKDIV_SYNC { + &self.clkdiv_sync + } + #[doc = "0x18 - Rx Filter configuration"] + #[inline(always)] + pub const fn rx_filt(&self) -> &RX_FILT { + &self.rx_filt + } + #[doc = "0x1c - UART status register"] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0x20 - a"] + #[inline(always)] + pub const fn conf0_sync(&self) -> &CONF0_SYNC { + &self.conf0_sync + } + #[doc = "0x24 - Configuration register 1"] + #[inline(always)] + pub const fn conf1(&self) -> &CONF1 { + &self.conf1 + } + #[doc = "0x2c - Hardware flow-control configuration"] + #[inline(always)] + pub const fn hwfc_conf_sync(&self) -> &HWFC_CONF_SYNC { + &self.hwfc_conf_sync + } + #[doc = "0x30 - UART sleep configure register 0"] + #[inline(always)] + pub const fn sleep_conf0(&self) -> &SLEEP_CONF0 { + &self.sleep_conf0 + } + #[doc = "0x34 - UART sleep configure register 1"] + #[inline(always)] + pub const fn sleep_conf1(&self) -> &SLEEP_CONF1 { + &self.sleep_conf1 + } + #[doc = "0x38 - UART sleep configure register 2"] + #[inline(always)] + pub const fn sleep_conf2(&self) -> &SLEEP_CONF2 { + &self.sleep_conf2 + } + #[doc = "0x3c - Software flow-control character configuration"] + #[inline(always)] + pub const fn swfc_conf0_sync(&self) -> &SWFC_CONF0_SYNC { + &self.swfc_conf0_sync + } + #[doc = "0x40 - Software flow-control character configuration"] + #[inline(always)] + pub const fn swfc_conf1(&self) -> &SWFC_CONF1 { + &self.swfc_conf1 + } + #[doc = "0x44 - Tx Break character configuration"] + #[inline(always)] + pub const fn txbrk_conf_sync(&self) -> &TXBRK_CONF_SYNC { + &self.txbrk_conf_sync + } + #[doc = "0x48 - Frame-end idle configuration"] + #[inline(always)] + pub const fn idle_conf_sync(&self) -> &IDLE_CONF_SYNC { + &self.idle_conf_sync + } + #[doc = "0x4c - RS485 mode configuration"] + #[inline(always)] + pub const fn rs485_conf_sync(&self) -> &RS485_CONF_SYNC { + &self.rs485_conf_sync + } + #[doc = "0x50 - Pre-sequence timing configuration"] + #[inline(always)] + pub const fn at_cmd_precnt_sync(&self) -> &AT_CMD_PRECNT_SYNC { + &self.at_cmd_precnt_sync + } + #[doc = "0x54 - Post-sequence timing configuration"] + #[inline(always)] + pub const fn at_cmd_postcnt_sync(&self) -> &AT_CMD_POSTCNT_SYNC { + &self.at_cmd_postcnt_sync + } + #[doc = "0x58 - Timeout configuration"] + #[inline(always)] + pub const fn at_cmd_gaptout_sync(&self) -> &AT_CMD_GAPTOUT_SYNC { + &self.at_cmd_gaptout_sync + } + #[doc = "0x5c - AT escape sequence detection configuration"] + #[inline(always)] + pub const fn at_cmd_char_sync(&self) -> &AT_CMD_CHAR_SYNC { + &self.at_cmd_char_sync + } + #[doc = "0x60 - UART memory power configuration"] + #[inline(always)] + pub const fn mem_conf(&self) -> &MEM_CONF { + &self.mem_conf + } + #[doc = "0x64 - UART threshold and allocation configuration"] + #[inline(always)] + pub const fn tout_conf_sync(&self) -> &TOUT_CONF_SYNC { + &self.tout_conf_sync + } + #[doc = "0x68 - Tx-SRAM write and read offset address."] + #[inline(always)] + pub const fn mem_tx_status(&self) -> &MEM_TX_STATUS { + &self.mem_tx_status + } + #[doc = "0x6c - Rx-SRAM write and read offset address."] + #[inline(always)] + pub const fn mem_rx_status(&self) -> &MEM_RX_STATUS { + &self.mem_rx_status + } + #[doc = "0x70 - UART transmit and receive status."] + #[inline(always)] + pub const fn fsm_status(&self) -> &FSM_STATUS { + &self.fsm_status + } + #[doc = "0x74 - Autobaud high pulse register"] + #[inline(always)] + pub const fn pospulse(&self) -> &POSPULSE { + &self.pospulse + } + #[doc = "0x78 - Autobaud low pulse register"] + #[inline(always)] + pub const fn negpulse(&self) -> &NEGPULSE { + &self.negpulse + } + #[doc = "0x7c - Autobaud minimum low pulse duration register"] + #[inline(always)] + pub const fn lowpulse(&self) -> &LOWPULSE { + &self.lowpulse + } + #[doc = "0x80 - Autobaud minimum high pulse duration register"] + #[inline(always)] + pub const fn highpulse(&self) -> &HIGHPULSE { + &self.highpulse + } + #[doc = "0x84 - Autobaud edge change count register"] + #[inline(always)] + pub const fn rxd_cnt(&self) -> &RXD_CNT { + &self.rxd_cnt + } + #[doc = "0x88 - UART core clock configuration"] + #[inline(always)] + pub const fn clk_conf(&self) -> &CLK_CONF { + &self.clk_conf + } + #[doc = "0x8c - UART Version register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } + #[doc = "0x90 - UART AFIFO Status"] + #[inline(always)] + pub const fn afifo_status(&self) -> &AFIFO_STATUS { + &self.afifo_status + } + #[doc = "0x98 - UART Registers Configuration Update register"] + #[inline(always)] + pub const fn reg_update(&self) -> ®_UPDATE { + &self.reg_update + } + #[doc = "0x9c - UART ID register"] + #[inline(always)] + pub const fn id(&self) -> &ID { + &self.id + } +} +#[doc = "FIFO (r) register accessor: FIFO data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] module"] +pub type FIFO = crate::Reg; +#[doc = "FIFO data register"] +pub mod fifo; +#[doc = "INT_RAW (rw) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Raw interrupt status"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Masked interrupt status"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable bits"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear bits"] +pub mod int_clr; +#[doc = "CLKDIV_SYNC (rw) register accessor: Clock divider configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv_sync`] module"] +pub type CLKDIV_SYNC = crate::Reg; +#[doc = "Clock divider configuration"] +pub mod clkdiv_sync; +#[doc = "RX_FILT (rw) register accessor: Rx Filter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_filt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_filt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_filt`] module"] +pub type RX_FILT = crate::Reg; +#[doc = "Rx Filter configuration"] +pub mod rx_filt; +#[doc = "STATUS (r) register accessor: UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"] +pub type STATUS = crate::Reg; +#[doc = "UART status register"] +pub mod status; +#[doc = "CONF0_SYNC (rw) register accessor: a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf0_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf0_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf0_sync`] module"] +pub type CONF0_SYNC = crate::Reg; +#[doc = "a"] +pub mod conf0_sync; +#[doc = "CONF1 (rw) register accessor: Configuration register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf1`] module"] +pub type CONF1 = crate::Reg; +#[doc = "Configuration register 1"] +pub mod conf1; +#[doc = "HWFC_CONF_SYNC (rw) register accessor: Hardware flow-control configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwfc_conf_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwfc_conf_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwfc_conf_sync`] module"] +pub type HWFC_CONF_SYNC = crate::Reg; +#[doc = "Hardware flow-control configuration"] +pub mod hwfc_conf_sync; +#[doc = "SLEEP_CONF0 (rw) register accessor: UART sleep configure register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf0`] module"] +pub type SLEEP_CONF0 = crate::Reg; +#[doc = "UART sleep configure register 0"] +pub mod sleep_conf0; +#[doc = "SLEEP_CONF1 (rw) register accessor: UART sleep configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf1`] module"] +pub type SLEEP_CONF1 = crate::Reg; +#[doc = "UART sleep configure register 1"] +pub mod sleep_conf1; +#[doc = "SLEEP_CONF2 (rw) register accessor: UART sleep configure register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf2`] module"] +pub type SLEEP_CONF2 = crate::Reg; +#[doc = "UART sleep configure register 2"] +pub mod sleep_conf2; +#[doc = "SWFC_CONF0_SYNC (rw) register accessor: Software flow-control character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swfc_conf0_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swfc_conf0_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swfc_conf0_sync`] module"] +pub type SWFC_CONF0_SYNC = crate::Reg; +#[doc = "Software flow-control character configuration"] +pub mod swfc_conf0_sync; +#[doc = "SWFC_CONF1 (rw) register accessor: Software flow-control character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swfc_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swfc_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swfc_conf1`] module"] +pub type SWFC_CONF1 = crate::Reg; +#[doc = "Software flow-control character configuration"] +pub mod swfc_conf1; +#[doc = "TXBRK_CONF_SYNC (rw) register accessor: Tx Break character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbrk_conf_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbrk_conf_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbrk_conf_sync`] module"] +pub type TXBRK_CONF_SYNC = crate::Reg; +#[doc = "Tx Break character configuration"] +pub mod txbrk_conf_sync; +#[doc = "IDLE_CONF_SYNC (rw) register accessor: Frame-end idle configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle_conf_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idle_conf_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idle_conf_sync`] module"] +pub type IDLE_CONF_SYNC = crate::Reg; +#[doc = "Frame-end idle configuration"] +pub mod idle_conf_sync; +#[doc = "RS485_CONF_SYNC (rw) register accessor: RS485 mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rs485_conf_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rs485_conf_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rs485_conf_sync`] module"] +pub type RS485_CONF_SYNC = crate::Reg; +#[doc = "RS485 mode configuration"] +pub mod rs485_conf_sync; +#[doc = "AT_CMD_PRECNT_SYNC (rw) register accessor: Pre-sequence timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_precnt_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_precnt_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_precnt_sync`] module"] +pub type AT_CMD_PRECNT_SYNC = crate::Reg; +#[doc = "Pre-sequence timing configuration"] +pub mod at_cmd_precnt_sync; +#[doc = "AT_CMD_POSTCNT_SYNC (rw) register accessor: Post-sequence timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_postcnt_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_postcnt_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_postcnt_sync`] module"] +pub type AT_CMD_POSTCNT_SYNC = crate::Reg; +#[doc = "Post-sequence timing configuration"] +pub mod at_cmd_postcnt_sync; +#[doc = "AT_CMD_GAPTOUT_SYNC (rw) register accessor: Timeout configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_gaptout_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_gaptout_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_gaptout_sync`] module"] +pub type AT_CMD_GAPTOUT_SYNC = crate::Reg; +#[doc = "Timeout configuration"] +pub mod at_cmd_gaptout_sync; +#[doc = "AT_CMD_CHAR_SYNC (rw) register accessor: AT escape sequence detection configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_char_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_char_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_char_sync`] module"] +pub type AT_CMD_CHAR_SYNC = crate::Reg; +#[doc = "AT escape sequence detection configuration"] +pub mod at_cmd_char_sync; +#[doc = "MEM_CONF (rw) register accessor: UART memory power configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_conf`] module"] +pub type MEM_CONF = crate::Reg; +#[doc = "UART memory power configuration"] +pub mod mem_conf; +#[doc = "TOUT_CONF_SYNC (rw) register accessor: UART threshold and allocation configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tout_conf_sync::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tout_conf_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tout_conf_sync`] module"] +pub type TOUT_CONF_SYNC = crate::Reg; +#[doc = "UART threshold and allocation configuration"] +pub mod tout_conf_sync; +#[doc = "MEM_TX_STATUS (r) register accessor: Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_tx_status`] module"] +pub type MEM_TX_STATUS = crate::Reg; +#[doc = "Tx-SRAM write and read offset address."] +pub mod mem_tx_status; +#[doc = "MEM_RX_STATUS (r) register accessor: Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_rx_status`] module"] +pub type MEM_RX_STATUS = crate::Reg; +#[doc = "Rx-SRAM write and read offset address."] +pub mod mem_rx_status; +#[doc = "FSM_STATUS (r) register accessor: UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsm_status`] module"] +pub type FSM_STATUS = crate::Reg; +#[doc = "UART transmit and receive status."] +pub mod fsm_status; +#[doc = "POSPULSE (r) register accessor: Autobaud high pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pospulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pospulse`] module"] +pub type POSPULSE = crate::Reg; +#[doc = "Autobaud high pulse register"] +pub mod pospulse; +#[doc = "NEGPULSE (r) register accessor: Autobaud low pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`negpulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@negpulse`] module"] +pub type NEGPULSE = crate::Reg; +#[doc = "Autobaud low pulse register"] +pub mod negpulse; +#[doc = "LOWPULSE (r) register accessor: Autobaud minimum low pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lowpulse`] module"] +pub type LOWPULSE = crate::Reg; +#[doc = "Autobaud minimum low pulse duration register"] +pub mod lowpulse; +#[doc = "HIGHPULSE (r) register accessor: Autobaud minimum high pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`highpulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@highpulse`] module"] +pub type HIGHPULSE = crate::Reg; +#[doc = "Autobaud minimum high pulse duration register"] +pub mod highpulse; +#[doc = "RXD_CNT (r) register accessor: Autobaud edge change count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxd_cnt`] module"] +pub type RXD_CNT = crate::Reg; +#[doc = "Autobaud edge change count register"] +pub mod rxd_cnt; +#[doc = "CLK_CONF (rw) register accessor: UART core clock configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"] +pub type CLK_CONF = crate::Reg; +#[doc = "UART core clock configuration"] +pub mod clk_conf; +#[doc = "DATE (rw) register accessor: UART Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "UART Version register"] +pub mod date; +#[doc = "AFIFO_STATUS (r) register accessor: UART AFIFO Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`afifo_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@afifo_status`] module"] +pub type AFIFO_STATUS = crate::Reg; +#[doc = "UART AFIFO Status"] +pub mod afifo_status; +#[doc = "REG_UPDATE (rw) register accessor: UART Registers Configuration Update register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_update::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_update::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_update`] module"] +pub type REG_UPDATE = crate::Reg; +#[doc = "UART Registers Configuration Update register"] +pub mod reg_update; +#[doc = "ID (rw) register accessor: UART ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`] module"] +pub type ID = crate::Reg; +#[doc = "UART ID register"] +pub mod id; diff --git a/esp32p4/src/uart0/afifo_status.rs b/esp32p4/src/uart0/afifo_status.rs new file mode 100644 index 0000000000..fe85b494e8 --- /dev/null +++ b/esp32p4/src/uart0/afifo_status.rs @@ -0,0 +1,72 @@ +#[doc = "Register `AFIFO_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `TX_AFIFO_FULL` reader - Full signal of APB TX AFIFO."] +pub type TX_AFIFO_FULL_R = crate::BitReader; +#[doc = "Field `TX_AFIFO_EMPTY` reader - Empty signal of APB TX AFIFO."] +pub type TX_AFIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `RX_AFIFO_FULL` reader - Full signal of APB RX AFIFO."] +pub type RX_AFIFO_FULL_R = crate::BitReader; +#[doc = "Field `RX_AFIFO_EMPTY` reader - Empty signal of APB RX AFIFO."] +pub type RX_AFIFO_EMPTY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Full signal of APB TX AFIFO."] + #[inline(always)] + pub fn tx_afifo_full(&self) -> TX_AFIFO_FULL_R { + TX_AFIFO_FULL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Empty signal of APB TX AFIFO."] + #[inline(always)] + pub fn tx_afifo_empty(&self) -> TX_AFIFO_EMPTY_R { + TX_AFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Full signal of APB RX AFIFO."] + #[inline(always)] + pub fn rx_afifo_full(&self) -> RX_AFIFO_FULL_R { + RX_AFIFO_FULL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Empty signal of APB RX AFIFO."] + #[inline(always)] + pub fn rx_afifo_empty(&self) -> RX_AFIFO_EMPTY_R { + RX_AFIFO_EMPTY_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AFIFO_STATUS") + .field( + "tx_afifo_full", + &format_args!("{}", self.tx_afifo_full().bit()), + ) + .field( + "tx_afifo_empty", + &format_args!("{}", self.tx_afifo_empty().bit()), + ) + .field( + "rx_afifo_full", + &format_args!("{}", self.rx_afifo_full().bit()), + ) + .field( + "rx_afifo_empty", + &format_args!("{}", self.rx_afifo_empty().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "UART AFIFO Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`afifo_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AFIFO_STATUS_SPEC; +impl crate::RegisterSpec for AFIFO_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`afifo_status::R`](R) reader structure"] +impl crate::Readable for AFIFO_STATUS_SPEC {} +#[doc = "`reset()` method sets AFIFO_STATUS to value 0x0a"] +impl crate::Resettable for AFIFO_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x0a; +} diff --git a/esp32p4/src/uart0/at_cmd_char_sync.rs b/esp32p4/src/uart0/at_cmd_char_sync.rs new file mode 100644 index 0000000000..cd1d506e27 --- /dev/null +++ b/esp32p4/src/uart0/at_cmd_char_sync.rs @@ -0,0 +1,82 @@ +#[doc = "Register `AT_CMD_CHAR_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `AT_CMD_CHAR_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `AT_CMD_CHAR` reader - This register is used to configure the content of at_cmd char."] +pub type AT_CMD_CHAR_R = crate::FieldReader; +#[doc = "Field `AT_CMD_CHAR` writer - This register is used to configure the content of at_cmd char."] +pub type AT_CMD_CHAR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CHAR_NUM` reader - This register is used to configure the num of continuous at_cmd chars received by receiver."] +pub type CHAR_NUM_R = crate::FieldReader; +#[doc = "Field `CHAR_NUM` writer - This register is used to configure the num of continuous at_cmd chars received by receiver."] +pub type CHAR_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."] + #[inline(always)] + pub fn at_cmd_char(&self) -> AT_CMD_CHAR_R { + AT_CMD_CHAR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - This register is used to configure the num of continuous at_cmd chars received by receiver."] + #[inline(always)] + pub fn char_num(&self) -> CHAR_NUM_R { + CHAR_NUM_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AT_CMD_CHAR_SYNC") + .field( + "at_cmd_char", + &format_args!("{}", self.at_cmd_char().bits()), + ) + .field("char_num", &format_args!("{}", self.char_num().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."] + #[inline(always)] + #[must_use] + pub fn at_cmd_char(&mut self) -> AT_CMD_CHAR_W { + AT_CMD_CHAR_W::new(self, 0) + } + #[doc = "Bits 8:15 - This register is used to configure the num of continuous at_cmd chars received by receiver."] + #[inline(always)] + #[must_use] + pub fn char_num(&mut self) -> CHAR_NUM_W { + CHAR_NUM_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "AT escape sequence detection configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_char_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_char_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AT_CMD_CHAR_SYNC_SPEC; +impl crate::RegisterSpec for AT_CMD_CHAR_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`at_cmd_char_sync::R`](R) reader structure"] +impl crate::Readable for AT_CMD_CHAR_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`at_cmd_char_sync::W`](W) writer structure"] +impl crate::Writable for AT_CMD_CHAR_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AT_CMD_CHAR_SYNC to value 0x032b"] +impl crate::Resettable for AT_CMD_CHAR_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x032b; +} diff --git a/esp32p4/src/uart0/at_cmd_gaptout_sync.rs b/esp32p4/src/uart0/at_cmd_gaptout_sync.rs new file mode 100644 index 0000000000..6bc46424d1 --- /dev/null +++ b/esp32p4/src/uart0/at_cmd_gaptout_sync.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AT_CMD_GAPTOUT_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `AT_CMD_GAPTOUT_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `RX_GAP_TOUT` reader - This register is used to configure the duration time between the at_cmd chars."] +pub type RX_GAP_TOUT_R = crate::FieldReader; +#[doc = "Field `RX_GAP_TOUT` writer - This register is used to configure the duration time between the at_cmd chars."] +pub type RX_GAP_TOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."] + #[inline(always)] + pub fn rx_gap_tout(&self) -> RX_GAP_TOUT_R { + RX_GAP_TOUT_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AT_CMD_GAPTOUT_SYNC") + .field( + "rx_gap_tout", + &format_args!("{}", self.rx_gap_tout().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."] + #[inline(always)] + #[must_use] + pub fn rx_gap_tout(&mut self) -> RX_GAP_TOUT_W { + RX_GAP_TOUT_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Timeout configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_gaptout_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_gaptout_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AT_CMD_GAPTOUT_SYNC_SPEC; +impl crate::RegisterSpec for AT_CMD_GAPTOUT_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`at_cmd_gaptout_sync::R`](R) reader structure"] +impl crate::Readable for AT_CMD_GAPTOUT_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`at_cmd_gaptout_sync::W`](W) writer structure"] +impl crate::Writable for AT_CMD_GAPTOUT_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AT_CMD_GAPTOUT_SYNC to value 0x0b"] +impl crate::Resettable for AT_CMD_GAPTOUT_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x0b; +} diff --git a/esp32p4/src/uart0/at_cmd_postcnt_sync.rs b/esp32p4/src/uart0/at_cmd_postcnt_sync.rs new file mode 100644 index 0000000000..37b284b295 --- /dev/null +++ b/esp32p4/src/uart0/at_cmd_postcnt_sync.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AT_CMD_POSTCNT_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `AT_CMD_POSTCNT_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `POST_IDLE_NUM` reader - This register is used to configure the duration time between the last at_cmd and the next data."] +pub type POST_IDLE_NUM_R = crate::FieldReader; +#[doc = "Field `POST_IDLE_NUM` writer - This register is used to configure the duration time between the last at_cmd and the next data."] +pub type POST_IDLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."] + #[inline(always)] + pub fn post_idle_num(&self) -> POST_IDLE_NUM_R { + POST_IDLE_NUM_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AT_CMD_POSTCNT_SYNC") + .field( + "post_idle_num", + &format_args!("{}", self.post_idle_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."] + #[inline(always)] + #[must_use] + pub fn post_idle_num(&mut self) -> POST_IDLE_NUM_W { + POST_IDLE_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Post-sequence timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_postcnt_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_postcnt_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AT_CMD_POSTCNT_SYNC_SPEC; +impl crate::RegisterSpec for AT_CMD_POSTCNT_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`at_cmd_postcnt_sync::R`](R) reader structure"] +impl crate::Readable for AT_CMD_POSTCNT_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`at_cmd_postcnt_sync::W`](W) writer structure"] +impl crate::Writable for AT_CMD_POSTCNT_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AT_CMD_POSTCNT_SYNC to value 0x0901"] +impl crate::Resettable for AT_CMD_POSTCNT_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x0901; +} diff --git a/esp32p4/src/uart0/at_cmd_precnt_sync.rs b/esp32p4/src/uart0/at_cmd_precnt_sync.rs new file mode 100644 index 0000000000..847e9c7053 --- /dev/null +++ b/esp32p4/src/uart0/at_cmd_precnt_sync.rs @@ -0,0 +1,66 @@ +#[doc = "Register `AT_CMD_PRECNT_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `AT_CMD_PRECNT_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `PRE_IDLE_NUM` reader - This register is used to configure the idle duration time before the first at_cmd is received by receiver."] +pub type PRE_IDLE_NUM_R = crate::FieldReader; +#[doc = "Field `PRE_IDLE_NUM` writer - This register is used to configure the idle duration time before the first at_cmd is received by receiver."] +pub type PRE_IDLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."] + #[inline(always)] + pub fn pre_idle_num(&self) -> PRE_IDLE_NUM_R { + PRE_IDLE_NUM_R::new((self.bits & 0xffff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AT_CMD_PRECNT_SYNC") + .field( + "pre_idle_num", + &format_args!("{}", self.pre_idle_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."] + #[inline(always)] + #[must_use] + pub fn pre_idle_num(&mut self) -> PRE_IDLE_NUM_W { + PRE_IDLE_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Pre-sequence timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`at_cmd_precnt_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`at_cmd_precnt_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AT_CMD_PRECNT_SYNC_SPEC; +impl crate::RegisterSpec for AT_CMD_PRECNT_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`at_cmd_precnt_sync::R`](R) reader structure"] +impl crate::Readable for AT_CMD_PRECNT_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`at_cmd_precnt_sync::W`](W) writer structure"] +impl crate::Writable for AT_CMD_PRECNT_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AT_CMD_PRECNT_SYNC to value 0x0901"] +impl crate::Resettable for AT_CMD_PRECNT_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x0901; +} diff --git a/esp32p4/src/uart0/clk_conf.rs b/esp32p4/src/uart0/clk_conf.rs new file mode 100644 index 0000000000..414dc359bf --- /dev/null +++ b/esp32p4/src/uart0/clk_conf.rs @@ -0,0 +1,111 @@ +#[doc = "Register `CLK_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `TX_SCLK_EN` reader - Set this bit to enable UART Tx clock."] +pub type TX_SCLK_EN_R = crate::BitReader; +#[doc = "Field `TX_SCLK_EN` writer - Set this bit to enable UART Tx clock."] +pub type TX_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_SCLK_EN` reader - Set this bit to enable UART Rx clock."] +pub type RX_SCLK_EN_R = crate::BitReader; +#[doc = "Field `RX_SCLK_EN` writer - Set this bit to enable UART Rx clock."] +pub type RX_SCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_RST_CORE` reader - Write 1 then write 0 to this bit to reset UART Tx."] +pub type TX_RST_CORE_R = crate::BitReader; +#[doc = "Field `TX_RST_CORE` writer - Write 1 then write 0 to this bit to reset UART Tx."] +pub type TX_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_RST_CORE` reader - Write 1 then write 0 to this bit to reset UART Rx."] +pub type RX_RST_CORE_R = crate::BitReader; +#[doc = "Field `RX_RST_CORE` writer - Write 1 then write 0 to this bit to reset UART Rx."] +pub type RX_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 24 - Set this bit to enable UART Tx clock."] + #[inline(always)] + pub fn tx_sclk_en(&self) -> TX_SCLK_EN_R { + TX_SCLK_EN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Set this bit to enable UART Rx clock."] + #[inline(always)] + pub fn rx_sclk_en(&self) -> RX_SCLK_EN_R { + RX_SCLK_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Write 1 then write 0 to this bit to reset UART Tx."] + #[inline(always)] + pub fn tx_rst_core(&self) -> TX_RST_CORE_R { + TX_RST_CORE_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Write 1 then write 0 to this bit to reset UART Rx."] + #[inline(always)] + pub fn rx_rst_core(&self) -> RX_RST_CORE_R { + RX_RST_CORE_R::new(((self.bits >> 27) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLK_CONF") + .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit())) + .field("rx_sclk_en", &format_args!("{}", self.rx_sclk_en().bit())) + .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit())) + .field("rx_rst_core", &format_args!("{}", self.rx_rst_core().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 24 - Set this bit to enable UART Tx clock."] + #[inline(always)] + #[must_use] + pub fn tx_sclk_en(&mut self) -> TX_SCLK_EN_W { + TX_SCLK_EN_W::new(self, 24) + } + #[doc = "Bit 25 - Set this bit to enable UART Rx clock."] + #[inline(always)] + #[must_use] + pub fn rx_sclk_en(&mut self) -> RX_SCLK_EN_W { + RX_SCLK_EN_W::new(self, 25) + } + #[doc = "Bit 26 - Write 1 then write 0 to this bit to reset UART Tx."] + #[inline(always)] + #[must_use] + pub fn tx_rst_core(&mut self) -> TX_RST_CORE_W { + TX_RST_CORE_W::new(self, 26) + } + #[doc = "Bit 27 - Write 1 then write 0 to this bit to reset UART Rx."] + #[inline(always)] + #[must_use] + pub fn rx_rst_core(&mut self) -> RX_RST_CORE_W { + RX_RST_CORE_W::new(self, 27) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART core clock configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_CONF_SPEC; +impl crate::RegisterSpec for CLK_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"] +impl crate::Readable for CLK_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"] +impl crate::Writable for CLK_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLK_CONF to value 0x0300_0000"] +impl crate::Resettable for CLK_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0300_0000; +} diff --git a/esp32p4/src/uart0/clkdiv_sync.rs b/esp32p4/src/uart0/clkdiv_sync.rs new file mode 100644 index 0000000000..54ea1b108b --- /dev/null +++ b/esp32p4/src/uart0/clkdiv_sync.rs @@ -0,0 +1,82 @@ +#[doc = "Register `CLKDIV_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `CLKDIV` reader - The integral part of the frequency divider factor."] +pub type CLKDIV_R = crate::FieldReader; +#[doc = "Field `CLKDIV` writer - The integral part of the frequency divider factor."] +pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `CLKDIV_FRAG` reader - The decimal part of the frequency divider factor."] +pub type CLKDIV_FRAG_R = crate::FieldReader; +#[doc = "Field `CLKDIV_FRAG` writer - The decimal part of the frequency divider factor."] +pub type CLKDIV_FRAG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:11 - The integral part of the frequency divider factor."] + #[inline(always)] + pub fn clkdiv(&self) -> CLKDIV_R { + CLKDIV_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 20:23 - The decimal part of the frequency divider factor."] + #[inline(always)] + pub fn clkdiv_frag(&self) -> CLKDIV_FRAG_R { + CLKDIV_FRAG_R::new(((self.bits >> 20) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLKDIV_SYNC") + .field("clkdiv", &format_args!("{}", self.clkdiv().bits())) + .field( + "clkdiv_frag", + &format_args!("{}", self.clkdiv_frag().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:11 - The integral part of the frequency divider factor."] + #[inline(always)] + #[must_use] + pub fn clkdiv(&mut self) -> CLKDIV_W { + CLKDIV_W::new(self, 0) + } + #[doc = "Bits 20:23 - The decimal part of the frequency divider factor."] + #[inline(always)] + #[must_use] + pub fn clkdiv_frag(&mut self) -> CLKDIV_FRAG_W { + CLKDIV_FRAG_W::new(self, 20) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock divider configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLKDIV_SYNC_SPEC; +impl crate::RegisterSpec for CLKDIV_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv_sync::R`](R) reader structure"] +impl crate::Readable for CLKDIV_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clkdiv_sync::W`](W) writer structure"] +impl crate::Writable for CLKDIV_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLKDIV_SYNC to value 0x02b6"] +impl crate::Resettable for CLKDIV_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x02b6; +} diff --git a/esp32p4/src/uart0/conf0_sync.rs b/esp32p4/src/uart0/conf0_sync.rs new file mode 100644 index 0000000000..95a6cd06f8 --- /dev/null +++ b/esp32p4/src/uart0/conf0_sync.rs @@ -0,0 +1,405 @@ +#[doc = "Register `CONF0_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `CONF0_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `PARITY` reader - This register is used to configure the parity check mode."] +pub type PARITY_R = crate::BitReader; +#[doc = "Field `PARITY` writer - This register is used to configure the parity check mode."] +pub type PARITY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARITY_EN` reader - Set this bit to enable uart parity check."] +pub type PARITY_EN_R = crate::BitReader; +#[doc = "Field `PARITY_EN` writer - Set this bit to enable uart parity check."] +pub type PARITY_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BIT_NUM` reader - This register is used to set the length of data."] +pub type BIT_NUM_R = crate::FieldReader; +#[doc = "Field `BIT_NUM` writer - This register is used to set the length of data."] +pub type BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `STOP_BIT_NUM` reader - This register is used to set the length of stop bit."] +pub type STOP_BIT_NUM_R = crate::FieldReader; +#[doc = "Field `STOP_BIT_NUM` writer - This register is used to set the length of stop bit."] +pub type STOP_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TXD_BRK` reader - Set this bit to enbale transmitter to send NULL when the process of sending data is done."] +pub type TXD_BRK_R = crate::BitReader; +#[doc = "Field `TXD_BRK` writer - Set this bit to enbale transmitter to send NULL when the process of sending data is done."] +pub type TXD_BRK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRDA_DPLX` reader - Set this bit to enable IrDA loopback mode."] +pub type IRDA_DPLX_R = crate::BitReader; +#[doc = "Field `IRDA_DPLX` writer - Set this bit to enable IrDA loopback mode."] +pub type IRDA_DPLX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRDA_TX_EN` reader - This is the start enable bit for IrDA transmitter."] +pub type IRDA_TX_EN_R = crate::BitReader; +#[doc = "Field `IRDA_TX_EN` writer - This is the start enable bit for IrDA transmitter."] +pub type IRDA_TX_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRDA_WCTL` reader - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."] +pub type IRDA_WCTL_R = crate::BitReader; +#[doc = "Field `IRDA_WCTL` writer - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."] +pub type IRDA_WCTL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRDA_TX_INV` reader - Set this bit to invert the level of IrDA transmitter."] +pub type IRDA_TX_INV_R = crate::BitReader; +#[doc = "Field `IRDA_TX_INV` writer - Set this bit to invert the level of IrDA transmitter."] +pub type IRDA_TX_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRDA_RX_INV` reader - Set this bit to invert the level of IrDA receiver."] +pub type IRDA_RX_INV_R = crate::BitReader; +#[doc = "Field `IRDA_RX_INV` writer - Set this bit to invert the level of IrDA receiver."] +pub type IRDA_RX_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOPBACK` reader - Set this bit to enable uart loopback test mode."] +pub type LOOPBACK_R = crate::BitReader; +#[doc = "Field `LOOPBACK` writer - Set this bit to enable uart loopback test mode."] +pub type LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_FLOW_EN` reader - Set this bit to enable flow control function for transmitter."] +pub type TX_FLOW_EN_R = crate::BitReader; +#[doc = "Field `TX_FLOW_EN` writer - Set this bit to enable flow control function for transmitter."] +pub type TX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRDA_EN` reader - Set this bit to enable IrDA protocol."] +pub type IRDA_EN_R = crate::BitReader; +#[doc = "Field `IRDA_EN` writer - Set this bit to enable IrDA protocol."] +pub type IRDA_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXD_INV` reader - Set this bit to inverse the level value of uart rxd signal."] +pub type RXD_INV_R = crate::BitReader; +#[doc = "Field `RXD_INV` writer - Set this bit to inverse the level value of uart rxd signal."] +pub type RXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXD_INV` reader - Set this bit to inverse the level value of uart txd signal."] +pub type TXD_INV_R = crate::BitReader; +#[doc = "Field `TXD_INV` writer - Set this bit to inverse the level value of uart txd signal."] +pub type TXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIS_RX_DAT_OVF` reader - Disable UART Rx data overflow detect."] +pub type DIS_RX_DAT_OVF_R = crate::BitReader; +#[doc = "Field `DIS_RX_DAT_OVF` writer - Disable UART Rx data overflow detect."] +pub type DIS_RX_DAT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERR_WR_MASK` reader - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."] +pub type ERR_WR_MASK_R = crate::BitReader; +#[doc = "Field `ERR_WR_MASK` writer - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."] +pub type ERR_WR_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOBAUD_EN` reader - This is the enable bit for detecting baudrate."] +pub type AUTOBAUD_EN_R = crate::BitReader; +#[doc = "Field `AUTOBAUD_EN` writer - This is the enable bit for detecting baudrate."] +pub type AUTOBAUD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_CLK_EN` reader - UART memory clock gate enable signal."] +pub type MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `MEM_CLK_EN` writer - UART memory clock gate enable signal."] +pub type MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_RTS` reader - This register is used to configure the software rts signal which is used in software flow control."] +pub type SW_RTS_R = crate::BitReader; +#[doc = "Field `SW_RTS` writer - This register is used to configure the software rts signal which is used in software flow control."] +pub type SW_RTS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_RST` reader - Set this bit to reset the uart receive-FIFO."] +pub type RXFIFO_RST_R = crate::BitReader; +#[doc = "Field `RXFIFO_RST` writer - Set this bit to reset the uart receive-FIFO."] +pub type RXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_RST` reader - Set this bit to reset the uart transmit-FIFO."] +pub type TXFIFO_RST_R = crate::BitReader; +#[doc = "Field `TXFIFO_RST` writer - Set this bit to reset the uart transmit-FIFO."] +pub type TXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This register is used to configure the parity check mode."] + #[inline(always)] + pub fn parity(&self) -> PARITY_R { + PARITY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to enable uart parity check."] + #[inline(always)] + pub fn parity_en(&self) -> PARITY_EN_R { + PARITY_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - This register is used to set the length of data."] + #[inline(always)] + pub fn bit_num(&self) -> BIT_NUM_R { + BIT_NUM_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - This register is used to set the length of stop bit."] + #[inline(always)] + pub fn stop_bit_num(&self) -> STOP_BIT_NUM_R { + STOP_BIT_NUM_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."] + #[inline(always)] + pub fn txd_brk(&self) -> TXD_BRK_R { + TXD_BRK_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set this bit to enable IrDA loopback mode."] + #[inline(always)] + pub fn irda_dplx(&self) -> IRDA_DPLX_R { + IRDA_DPLX_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This is the start enable bit for IrDA transmitter."] + #[inline(always)] + pub fn irda_tx_en(&self) -> IRDA_TX_EN_R { + IRDA_TX_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."] + #[inline(always)] + pub fn irda_wctl(&self) -> IRDA_WCTL_R { + IRDA_WCTL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Set this bit to invert the level of IrDA transmitter."] + #[inline(always)] + pub fn irda_tx_inv(&self) -> IRDA_TX_INV_R { + IRDA_TX_INV_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Set this bit to invert the level of IrDA receiver."] + #[inline(always)] + pub fn irda_rx_inv(&self) -> IRDA_RX_INV_R { + IRDA_RX_INV_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Set this bit to enable uart loopback test mode."] + #[inline(always)] + pub fn loopback(&self) -> LOOPBACK_R { + LOOPBACK_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set this bit to enable flow control function for transmitter."] + #[inline(always)] + pub fn tx_flow_en(&self) -> TX_FLOW_EN_R { + TX_FLOW_EN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Set this bit to enable IrDA protocol."] + #[inline(always)] + pub fn irda_en(&self) -> IRDA_EN_R { + IRDA_EN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Set this bit to inverse the level value of uart rxd signal."] + #[inline(always)] + pub fn rxd_inv(&self) -> RXD_INV_R { + RXD_INV_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Set this bit to inverse the level value of uart txd signal."] + #[inline(always)] + pub fn txd_inv(&self) -> TXD_INV_R { + TXD_INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Disable UART Rx data overflow detect."] + #[inline(always)] + pub fn dis_rx_dat_ovf(&self) -> DIS_RX_DAT_OVF_R { + DIS_RX_DAT_OVF_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."] + #[inline(always)] + pub fn err_wr_mask(&self) -> ERR_WR_MASK_R { + ERR_WR_MASK_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - This is the enable bit for detecting baudrate."] + #[inline(always)] + pub fn autobaud_en(&self) -> AUTOBAUD_EN_R { + AUTOBAUD_EN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - UART memory clock gate enable signal."] + #[inline(always)] + pub fn mem_clk_en(&self) -> MEM_CLK_EN_R { + MEM_CLK_EN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - This register is used to configure the software rts signal which is used in software flow control."] + #[inline(always)] + pub fn sw_rts(&self) -> SW_RTS_R { + SW_RTS_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to reset the uart receive-FIFO."] + #[inline(always)] + pub fn rxfifo_rst(&self) -> RXFIFO_RST_R { + RXFIFO_RST_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Set this bit to reset the uart transmit-FIFO."] + #[inline(always)] + pub fn txfifo_rst(&self) -> TXFIFO_RST_R { + TXFIFO_RST_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF0_SYNC") + .field("parity", &format_args!("{}", self.parity().bit())) + .field("parity_en", &format_args!("{}", self.parity_en().bit())) + .field("bit_num", &format_args!("{}", self.bit_num().bits())) + .field( + "stop_bit_num", + &format_args!("{}", self.stop_bit_num().bits()), + ) + .field("txd_brk", &format_args!("{}", self.txd_brk().bit())) + .field("irda_dplx", &format_args!("{}", self.irda_dplx().bit())) + .field("irda_tx_en", &format_args!("{}", self.irda_tx_en().bit())) + .field("irda_wctl", &format_args!("{}", self.irda_wctl().bit())) + .field("irda_tx_inv", &format_args!("{}", self.irda_tx_inv().bit())) + .field("irda_rx_inv", &format_args!("{}", self.irda_rx_inv().bit())) + .field("loopback", &format_args!("{}", self.loopback().bit())) + .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit())) + .field("irda_en", &format_args!("{}", self.irda_en().bit())) + .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit())) + .field("txd_inv", &format_args!("{}", self.txd_inv().bit())) + .field( + "dis_rx_dat_ovf", + &format_args!("{}", self.dis_rx_dat_ovf().bit()), + ) + .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit())) + .field("autobaud_en", &format_args!("{}", self.autobaud_en().bit())) + .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit())) + .field("sw_rts", &format_args!("{}", self.sw_rts().bit())) + .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit())) + .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This register is used to configure the parity check mode."] + #[inline(always)] + #[must_use] + pub fn parity(&mut self) -> PARITY_W { + PARITY_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to enable uart parity check."] + #[inline(always)] + #[must_use] + pub fn parity_en(&mut self) -> PARITY_EN_W { + PARITY_EN_W::new(self, 1) + } + #[doc = "Bits 2:3 - This register is used to set the length of data."] + #[inline(always)] + #[must_use] + pub fn bit_num(&mut self) -> BIT_NUM_W { + BIT_NUM_W::new(self, 2) + } + #[doc = "Bits 4:5 - This register is used to set the length of stop bit."] + #[inline(always)] + #[must_use] + pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W { + STOP_BIT_NUM_W::new(self, 4) + } + #[doc = "Bit 6 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."] + #[inline(always)] + #[must_use] + pub fn txd_brk(&mut self) -> TXD_BRK_W { + TXD_BRK_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to enable IrDA loopback mode."] + #[inline(always)] + #[must_use] + pub fn irda_dplx(&mut self) -> IRDA_DPLX_W { + IRDA_DPLX_W::new(self, 7) + } + #[doc = "Bit 8 - This is the start enable bit for IrDA transmitter."] + #[inline(always)] + #[must_use] + pub fn irda_tx_en(&mut self) -> IRDA_TX_EN_W { + IRDA_TX_EN_W::new(self, 8) + } + #[doc = "Bit 9 - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."] + #[inline(always)] + #[must_use] + pub fn irda_wctl(&mut self) -> IRDA_WCTL_W { + IRDA_WCTL_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to invert the level of IrDA transmitter."] + #[inline(always)] + #[must_use] + pub fn irda_tx_inv(&mut self) -> IRDA_TX_INV_W { + IRDA_TX_INV_W::new(self, 10) + } + #[doc = "Bit 11 - Set this bit to invert the level of IrDA receiver."] + #[inline(always)] + #[must_use] + pub fn irda_rx_inv(&mut self) -> IRDA_RX_INV_W { + IRDA_RX_INV_W::new(self, 11) + } + #[doc = "Bit 12 - Set this bit to enable uart loopback test mode."] + #[inline(always)] + #[must_use] + pub fn loopback(&mut self) -> LOOPBACK_W { + LOOPBACK_W::new(self, 12) + } + #[doc = "Bit 13 - Set this bit to enable flow control function for transmitter."] + #[inline(always)] + #[must_use] + pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W { + TX_FLOW_EN_W::new(self, 13) + } + #[doc = "Bit 14 - Set this bit to enable IrDA protocol."] + #[inline(always)] + #[must_use] + pub fn irda_en(&mut self) -> IRDA_EN_W { + IRDA_EN_W::new(self, 14) + } + #[doc = "Bit 15 - Set this bit to inverse the level value of uart rxd signal."] + #[inline(always)] + #[must_use] + pub fn rxd_inv(&mut self) -> RXD_INV_W { + RXD_INV_W::new(self, 15) + } + #[doc = "Bit 16 - Set this bit to inverse the level value of uart txd signal."] + #[inline(always)] + #[must_use] + pub fn txd_inv(&mut self) -> TXD_INV_W { + TXD_INV_W::new(self, 16) + } + #[doc = "Bit 17 - Disable UART Rx data overflow detect."] + #[inline(always)] + #[must_use] + pub fn dis_rx_dat_ovf(&mut self) -> DIS_RX_DAT_OVF_W { + DIS_RX_DAT_OVF_W::new(self, 17) + } + #[doc = "Bit 18 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."] + #[inline(always)] + #[must_use] + pub fn err_wr_mask(&mut self) -> ERR_WR_MASK_W { + ERR_WR_MASK_W::new(self, 18) + } + #[doc = "Bit 19 - This is the enable bit for detecting baudrate."] + #[inline(always)] + #[must_use] + pub fn autobaud_en(&mut self) -> AUTOBAUD_EN_W { + AUTOBAUD_EN_W::new(self, 19) + } + #[doc = "Bit 20 - UART memory clock gate enable signal."] + #[inline(always)] + #[must_use] + pub fn mem_clk_en(&mut self) -> MEM_CLK_EN_W { + MEM_CLK_EN_W::new(self, 20) + } + #[doc = "Bit 21 - This register is used to configure the software rts signal which is used in software flow control."] + #[inline(always)] + #[must_use] + pub fn sw_rts(&mut self) -> SW_RTS_W { + SW_RTS_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to reset the uart receive-FIFO."] + #[inline(always)] + #[must_use] + pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W { + RXFIFO_RST_W::new(self, 22) + } + #[doc = "Bit 23 - Set this bit to reset the uart transmit-FIFO."] + #[inline(always)] + #[must_use] + pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W { + TXFIFO_RST_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf0_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf0_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF0_SYNC_SPEC; +impl crate::RegisterSpec for CONF0_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf0_sync::R`](R) reader structure"] +impl crate::Readable for CONF0_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf0_sync::W`](W) writer structure"] +impl crate::Writable for CONF0_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF0_SYNC to value 0x1c"] +impl crate::Resettable for CONF0_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x1c; +} diff --git a/esp32p4/src/uart0/conf1.rs b/esp32p4/src/uart0/conf1.rs new file mode 100644 index 0000000000..b1e01c64a9 --- /dev/null +++ b/esp32p4/src/uart0/conf1.rs @@ -0,0 +1,181 @@ +#[doc = "Register `CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_FULL_THRHD` reader - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."] +pub type RXFIFO_FULL_THRHD_R = crate::FieldReader; +#[doc = "Field `RXFIFO_FULL_THRHD` writer - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."] +pub type RXFIFO_FULL_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TXFIFO_EMPTY_THRHD` reader - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."] +pub type TXFIFO_EMPTY_THRHD_R = crate::FieldReader; +#[doc = "Field `TXFIFO_EMPTY_THRHD` writer - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."] +pub type TXFIFO_EMPTY_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CTS_INV` reader - Set this bit to inverse the level value of uart cts signal."] +pub type CTS_INV_R = crate::BitReader; +#[doc = "Field `CTS_INV` writer - Set this bit to inverse the level value of uart cts signal."] +pub type CTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSR_INV` reader - Set this bit to inverse the level value of uart dsr signal."] +pub type DSR_INV_R = crate::BitReader; +#[doc = "Field `DSR_INV` writer - Set this bit to inverse the level value of uart dsr signal."] +pub type DSR_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTS_INV` reader - Set this bit to inverse the level value of uart rts signal."] +pub type RTS_INV_R = crate::BitReader; +#[doc = "Field `RTS_INV` writer - Set this bit to inverse the level value of uart rts signal."] +pub type RTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DTR_INV` reader - Set this bit to inverse the level value of uart dtr signal."] +pub type DTR_INV_R = crate::BitReader; +#[doc = "Field `DTR_INV` writer - Set this bit to inverse the level value of uart dtr signal."] +pub type DTR_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_DTR` reader - This register is used to configure the software dtr signal which is used in software flow control."] +pub type SW_DTR_R = crate::BitReader; +#[doc = "Field `SW_DTR` writer - This register is used to configure the software dtr signal which is used in software flow control."] +pub type SW_DTR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."] + #[inline(always)] + pub fn rxfifo_full_thrhd(&self) -> RXFIFO_FULL_THRHD_R { + RXFIFO_FULL_THRHD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."] + #[inline(always)] + pub fn txfifo_empty_thrhd(&self) -> TXFIFO_EMPTY_THRHD_R { + TXFIFO_EMPTY_THRHD_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 16 - Set this bit to inverse the level value of uart cts signal."] + #[inline(always)] + pub fn cts_inv(&self) -> CTS_INV_R { + CTS_INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Set this bit to inverse the level value of uart dsr signal."] + #[inline(always)] + pub fn dsr_inv(&self) -> DSR_INV_R { + DSR_INV_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Set this bit to inverse the level value of uart rts signal."] + #[inline(always)] + pub fn rts_inv(&self) -> RTS_INV_R { + RTS_INV_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Set this bit to inverse the level value of uart dtr signal."] + #[inline(always)] + pub fn dtr_inv(&self) -> DTR_INV_R { + DTR_INV_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - This register is used to configure the software dtr signal which is used in software flow control."] + #[inline(always)] + pub fn sw_dtr(&self) -> SW_DTR_R { + SW_DTR_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 21) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF1") + .field( + "rxfifo_full_thrhd", + &format_args!("{}", self.rxfifo_full_thrhd().bits()), + ) + .field( + "txfifo_empty_thrhd", + &format_args!("{}", self.txfifo_empty_thrhd().bits()), + ) + .field("cts_inv", &format_args!("{}", self.cts_inv().bit())) + .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit())) + .field("rts_inv", &format_args!("{}", self.rts_inv().bit())) + .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit())) + .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit())) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."] + #[inline(always)] + #[must_use] + pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W { + RXFIFO_FULL_THRHD_W::new(self, 0) + } + #[doc = "Bits 8:15 - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."] + #[inline(always)] + #[must_use] + pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W { + TXFIFO_EMPTY_THRHD_W::new(self, 8) + } + #[doc = "Bit 16 - Set this bit to inverse the level value of uart cts signal."] + #[inline(always)] + #[must_use] + pub fn cts_inv(&mut self) -> CTS_INV_W { + CTS_INV_W::new(self, 16) + } + #[doc = "Bit 17 - Set this bit to inverse the level value of uart dsr signal."] + #[inline(always)] + #[must_use] + pub fn dsr_inv(&mut self) -> DSR_INV_W { + DSR_INV_W::new(self, 17) + } + #[doc = "Bit 18 - Set this bit to inverse the level value of uart rts signal."] + #[inline(always)] + #[must_use] + pub fn rts_inv(&mut self) -> RTS_INV_W { + RTS_INV_W::new(self, 18) + } + #[doc = "Bit 19 - Set this bit to inverse the level value of uart dtr signal."] + #[inline(always)] + #[must_use] + pub fn dtr_inv(&mut self) -> DTR_INV_W { + DTR_INV_W::new(self, 19) + } + #[doc = "Bit 20 - This register is used to configure the software dtr signal which is used in software flow control."] + #[inline(always)] + #[must_use] + pub fn sw_dtr(&mut self) -> SW_DTR_W { + SW_DTR_W::new(self, 20) + } + #[doc = "Bit 21 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 21) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF1_SPEC; +impl crate::RegisterSpec for CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf1::R`](R) reader structure"] +impl crate::Readable for CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf1::W`](W) writer structure"] +impl crate::Writable for CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF1 to value 0x6060"] +impl crate::Resettable for CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x6060; +} diff --git a/esp32p4/src/uart0/date.rs b/esp32p4/src/uart0/date.rs new file mode 100644 index 0000000000..0322224da8 --- /dev/null +++ b/esp32p4/src/uart0/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - This is the version register."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - This is the version register."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This is the version register."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This is the version register."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART Version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0230_5050"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0230_5050; +} diff --git a/esp32p4/src/uart0/fifo.rs b/esp32p4/src/uart0/fifo.rs new file mode 100644 index 0000000000..5670061c44 --- /dev/null +++ b/esp32p4/src/uart0/fifo.rs @@ -0,0 +1,39 @@ +#[doc = "Register `FIFO` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_RD_BYTE` reader - UART 0 accesses FIFO via this register."] +pub type RXFIFO_RD_BYTE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."] + #[inline(always)] + pub fn rxfifo_rd_byte(&self) -> RXFIFO_RD_BYTE_R { + RXFIFO_RD_BYTE_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FIFO") + .field( + "rxfifo_rd_byte", + &format_args!("{}", self.rxfifo_rd_byte().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "FIFO data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_SPEC; +impl crate::RegisterSpec for FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} +#[doc = "`reset()` method sets FIFO to value 0"] +impl crate::Resettable for FIFO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/fsm_status.rs b/esp32p4/src/uart0/fsm_status.rs new file mode 100644 index 0000000000..8a34e7ab1e --- /dev/null +++ b/esp32p4/src/uart0/fsm_status.rs @@ -0,0 +1,44 @@ +#[doc = "Register `FSM_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `ST_URX_OUT` reader - This is the status register of receiver."] +pub type ST_URX_OUT_R = crate::FieldReader; +#[doc = "Field `ST_UTX_OUT` reader - This is the status register of transmitter."] +pub type ST_UTX_OUT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - This is the status register of receiver."] + #[inline(always)] + pub fn st_urx_out(&self) -> ST_URX_OUT_R { + ST_URX_OUT_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - This is the status register of transmitter."] + #[inline(always)] + pub fn st_utx_out(&self) -> ST_UTX_OUT_R { + ST_UTX_OUT_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FSM_STATUS") + .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits())) + .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FSM_STATUS_SPEC; +impl crate::RegisterSpec for FSM_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fsm_status::R`](R) reader structure"] +impl crate::Readable for FSM_STATUS_SPEC {} +#[doc = "`reset()` method sets FSM_STATUS to value 0"] +impl crate::Resettable for FSM_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/highpulse.rs b/esp32p4/src/uart0/highpulse.rs new file mode 100644 index 0000000000..8e199ec2da --- /dev/null +++ b/esp32p4/src/uart0/highpulse.rs @@ -0,0 +1,36 @@ +#[doc = "Register `HIGHPULSE` reader"] +pub type R = crate::R; +#[doc = "Field `MIN_CNT` reader - This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process."] +pub type MIN_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process."] + #[inline(always)] + pub fn min_cnt(&self) -> MIN_CNT_R { + MIN_CNT_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HIGHPULSE") + .field("min_cnt", &format_args!("{}", self.min_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Autobaud minimum high pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`highpulse::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HIGHPULSE_SPEC; +impl crate::RegisterSpec for HIGHPULSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`highpulse::R`](R) reader structure"] +impl crate::Readable for HIGHPULSE_SPEC {} +#[doc = "`reset()` method sets HIGHPULSE to value 0x0fff"] +impl crate::Resettable for HIGHPULSE_SPEC { + const RESET_VALUE: Self::Ux = 0x0fff; +} diff --git a/esp32p4/src/uart0/hwfc_conf_sync.rs b/esp32p4/src/uart0/hwfc_conf_sync.rs new file mode 100644 index 0000000000..b8589aa438 --- /dev/null +++ b/esp32p4/src/uart0/hwfc_conf_sync.rs @@ -0,0 +1,82 @@ +#[doc = "Register `HWFC_CONF_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `HWFC_CONF_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `RX_FLOW_THRHD` reader - This register is used to configure the maximum amount of data that can be received when hardware flow control works."] +pub type RX_FLOW_THRHD_R = crate::FieldReader; +#[doc = "Field `RX_FLOW_THRHD` writer - This register is used to configure the maximum amount of data that can be received when hardware flow control works."] +pub type RX_FLOW_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RX_FLOW_EN` reader - This is the flow enable bit for UART receiver."] +pub type RX_FLOW_EN_R = crate::BitReader; +#[doc = "Field `RX_FLOW_EN` writer - This is the flow enable bit for UART receiver."] +pub type RX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."] + #[inline(always)] + pub fn rx_flow_thrhd(&self) -> RX_FLOW_THRHD_R { + RX_FLOW_THRHD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - This is the flow enable bit for UART receiver."] + #[inline(always)] + pub fn rx_flow_en(&self) -> RX_FLOW_EN_R { + RX_FLOW_EN_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HWFC_CONF_SYNC") + .field( + "rx_flow_thrhd", + &format_args!("{}", self.rx_flow_thrhd().bits()), + ) + .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."] + #[inline(always)] + #[must_use] + pub fn rx_flow_thrhd(&mut self) -> RX_FLOW_THRHD_W { + RX_FLOW_THRHD_W::new(self, 0) + } + #[doc = "Bit 8 - This is the flow enable bit for UART receiver."] + #[inline(always)] + #[must_use] + pub fn rx_flow_en(&mut self) -> RX_FLOW_EN_W { + RX_FLOW_EN_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Hardware flow-control configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hwfc_conf_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hwfc_conf_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HWFC_CONF_SYNC_SPEC; +impl crate::RegisterSpec for HWFC_CONF_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hwfc_conf_sync::R`](R) reader structure"] +impl crate::Readable for HWFC_CONF_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hwfc_conf_sync::W`](W) writer structure"] +impl crate::Writable for HWFC_CONF_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HWFC_CONF_SYNC to value 0"] +impl crate::Resettable for HWFC_CONF_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/id.rs b/esp32p4/src/uart0/id.rs new file mode 100644 index 0000000000..20d5d54393 --- /dev/null +++ b/esp32p4/src/uart0/id.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ID` reader"] +pub type R = crate::R; +#[doc = "Register `ID` writer"] +pub type W = crate::W; +#[doc = "Field `ID` reader - This register is used to configure the uart_id."] +pub type ID_R = crate::FieldReader; +#[doc = "Field `ID` writer - This register is used to configure the uart_id."] +pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is used to configure the uart_id."] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ID") + .field("id", &format_args!("{}", self.id().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - This register is used to configure the uart_id."] + #[inline(always)] + #[must_use] + pub fn id(&mut self) -> ID_W { + ID_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_SPEC; +impl crate::RegisterSpec for ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id::R`](R) reader structure"] +impl crate::Readable for ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id::W`](W) writer structure"] +impl crate::Writable for ID_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ID to value 0x0500"] +impl crate::Resettable for ID_SPEC { + const RESET_VALUE: Self::Ux = 0x0500; +} diff --git a/esp32p4/src/uart0/idle_conf_sync.rs b/esp32p4/src/uart0/idle_conf_sync.rs new file mode 100644 index 0000000000..99ae7c7b5b --- /dev/null +++ b/esp32p4/src/uart0/idle_conf_sync.rs @@ -0,0 +1,85 @@ +#[doc = "Register `IDLE_CONF_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `IDLE_CONF_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `RX_IDLE_THRHD` reader - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."] +pub type RX_IDLE_THRHD_R = crate::FieldReader; +#[doc = "Field `RX_IDLE_THRHD` writer - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."] +pub type RX_IDLE_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `TX_IDLE_NUM` reader - This register is used to configure the duration time between transfers."] +pub type TX_IDLE_NUM_R = crate::FieldReader; +#[doc = "Field `TX_IDLE_NUM` writer - This register is used to configure the duration time between transfers."] +pub type TX_IDLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."] + #[inline(always)] + pub fn rx_idle_thrhd(&self) -> RX_IDLE_THRHD_R { + RX_IDLE_THRHD_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:19 - This register is used to configure the duration time between transfers."] + #[inline(always)] + pub fn tx_idle_num(&self) -> TX_IDLE_NUM_R { + TX_IDLE_NUM_R::new(((self.bits >> 10) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IDLE_CONF_SYNC") + .field( + "rx_idle_thrhd", + &format_args!("{}", self.rx_idle_thrhd().bits()), + ) + .field( + "tx_idle_num", + &format_args!("{}", self.tx_idle_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."] + #[inline(always)] + #[must_use] + pub fn rx_idle_thrhd(&mut self) -> RX_IDLE_THRHD_W { + RX_IDLE_THRHD_W::new(self, 0) + } + #[doc = "Bits 10:19 - This register is used to configure the duration time between transfers."] + #[inline(always)] + #[must_use] + pub fn tx_idle_num(&mut self) -> TX_IDLE_NUM_W { + TX_IDLE_NUM_W::new(self, 10) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Frame-end idle configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle_conf_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idle_conf_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IDLE_CONF_SYNC_SPEC; +impl crate::RegisterSpec for IDLE_CONF_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`idle_conf_sync::R`](R) reader structure"] +impl crate::Readable for IDLE_CONF_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`idle_conf_sync::W`](W) writer structure"] +impl crate::Writable for IDLE_CONF_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets IDLE_CONF_SYNC to value 0x0004_0100"] +impl crate::Resettable for IDLE_CONF_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x0004_0100; +} diff --git a/esp32p4/src/uart0/int_clr.rs b/esp32p4/src/uart0/int_clr.rs new file mode 100644 index 0000000000..91f4a4d305 --- /dev/null +++ b/esp32p4/src/uart0/int_clr.rs @@ -0,0 +1,194 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_FULL_INT_CLR` writer - Set this bit to clear the rxfifo_full_int_raw interrupt."] +pub type RXFIFO_FULL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_EMPTY_INT_CLR` writer - Set this bit to clear txfifo_empty_int_raw interrupt."] +pub type TXFIFO_EMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARITY_ERR_INT_CLR` writer - Set this bit to clear parity_err_int_raw interrupt."] +pub type PARITY_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRM_ERR_INT_CLR` writer - Set this bit to clear frm_err_int_raw interrupt."] +pub type FRM_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF_INT_CLR` writer - Set this bit to clear rxfifo_ovf_int_raw interrupt."] +pub type RXFIFO_OVF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSR_CHG_INT_CLR` writer - Set this bit to clear the dsr_chg_int_raw interrupt."] +pub type DSR_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTS_CHG_INT_CLR` writer - Set this bit to clear the cts_chg_int_raw interrupt."] +pub type CTS_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRK_DET_INT_CLR` writer - Set this bit to clear the brk_det_int_raw interrupt."] +pub type BRK_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_TOUT_INT_CLR` writer - Set this bit to clear the rxfifo_tout_int_raw interrupt."] +pub type RXFIFO_TOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XON_INT_CLR` writer - Set this bit to clear the sw_xon_int_raw interrupt."] +pub type SW_XON_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XOFF_INT_CLR` writer - Set this bit to clear the sw_xoff_int_raw interrupt."] +pub type SW_XOFF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GLITCH_DET_INT_CLR` writer - Set this bit to clear the glitch_det_int_raw interrupt."] +pub type GLITCH_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_DONE_INT_CLR` writer - Set this bit to clear the tx_brk_done_int_raw interrupt.."] +pub type TX_BRK_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_CLR` writer - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."] +pub type TX_BRK_IDLE_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DONE_INT_CLR` writer - Set this bit to clear the tx_done_int_raw interrupt."] +pub type TX_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485_PARITY_ERR_INT_CLR` writer - Set this bit to clear the rs485_parity_err_int_raw interrupt."] +pub type RS485_PARITY_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485_FRM_ERR_INT_CLR` writer - Set this bit to clear the rs485_frm_err_int_raw interrupt."] +pub type RS485_FRM_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485_CLASH_INT_CLR` writer - Set this bit to clear the rs485_clash_int_raw interrupt."] +pub type RS485_CLASH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AT_CMD_CHAR_DET_INT_CLR` writer - Set this bit to clear the at_cmd_char_det_int_raw interrupt."] +pub type AT_CMD_CHAR_DET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAKEUP_INT_CLR` writer - Set this bit to clear the uart_wakeup_int_raw interrupt."] +pub type WAKEUP_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the rxfifo_full_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_full_int_clr(&mut self) -> RXFIFO_FULL_INT_CLR_W { + RXFIFO_FULL_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear txfifo_empty_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn txfifo_empty_int_clr(&mut self) -> TXFIFO_EMPTY_INT_CLR_W { + TXFIFO_EMPTY_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear parity_err_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn parity_err_int_clr(&mut self) -> PARITY_ERR_INT_CLR_W { + PARITY_ERR_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear frm_err_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn frm_err_int_clr(&mut self) -> FRM_ERR_INT_CLR_W { + FRM_ERR_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear rxfifo_ovf_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_ovf_int_clr(&mut self) -> RXFIFO_OVF_INT_CLR_W { + RXFIFO_OVF_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the dsr_chg_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn dsr_chg_int_clr(&mut self) -> DSR_CHG_INT_CLR_W { + DSR_CHG_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the cts_chg_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn cts_chg_int_clr(&mut self) -> CTS_CHG_INT_CLR_W { + CTS_CHG_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the brk_det_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn brk_det_int_clr(&mut self) -> BRK_DET_INT_CLR_W { + BRK_DET_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the rxfifo_tout_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn rxfifo_tout_int_clr(&mut self) -> RXFIFO_TOUT_INT_CLR_W { + RXFIFO_TOUT_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the sw_xon_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn sw_xon_int_clr(&mut self) -> SW_XON_INT_CLR_W { + SW_XON_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to clear the sw_xoff_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn sw_xoff_int_clr(&mut self) -> SW_XOFF_INT_CLR_W { + SW_XOFF_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Set this bit to clear the glitch_det_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn glitch_det_int_clr(&mut self) -> GLITCH_DET_INT_CLR_W { + GLITCH_DET_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Set this bit to clear the tx_brk_done_int_raw interrupt.."] + #[inline(always)] + #[must_use] + pub fn tx_brk_done_int_clr(&mut self) -> TX_BRK_DONE_INT_CLR_W { + TX_BRK_DONE_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn tx_brk_idle_done_int_clr(&mut self) -> TX_BRK_IDLE_DONE_INT_CLR_W { + TX_BRK_IDLE_DONE_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Set this bit to clear the tx_done_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn tx_done_int_clr(&mut self) -> TX_DONE_INT_CLR_W { + TX_DONE_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Set this bit to clear the rs485_parity_err_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn rs485_parity_err_int_clr(&mut self) -> RS485_PARITY_ERR_INT_CLR_W { + RS485_PARITY_ERR_INT_CLR_W::new(self, 15) + } + #[doc = "Bit 16 - Set this bit to clear the rs485_frm_err_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn rs485_frm_err_int_clr(&mut self) -> RS485_FRM_ERR_INT_CLR_W { + RS485_FRM_ERR_INT_CLR_W::new(self, 16) + } + #[doc = "Bit 17 - Set this bit to clear the rs485_clash_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn rs485_clash_int_clr(&mut self) -> RS485_CLASH_INT_CLR_W { + RS485_CLASH_INT_CLR_W::new(self, 17) + } + #[doc = "Bit 18 - Set this bit to clear the at_cmd_char_det_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn at_cmd_char_det_int_clr(&mut self) -> AT_CMD_CHAR_DET_INT_CLR_W { + AT_CMD_CHAR_DET_INT_CLR_W::new(self, 18) + } + #[doc = "Bit 19 - Set this bit to clear the uart_wakeup_int_raw interrupt."] + #[inline(always)] + #[must_use] + pub fn wakeup_int_clr(&mut self) -> WAKEUP_INT_CLR_W { + WAKEUP_INT_CLR_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/int_ena.rs b/esp32p4/src/uart0/int_ena.rs new file mode 100644 index 0000000000..10a957715c --- /dev/null +++ b/esp32p4/src/uart0/int_ena.rs @@ -0,0 +1,427 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_FULL_INT_ENA` reader - This is the enable bit for rxfifo_full_int_st register."] +pub type RXFIFO_FULL_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_FULL_INT_ENA` writer - This is the enable bit for rxfifo_full_int_st register."] +pub type RXFIFO_FULL_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_EMPTY_INT_ENA` reader - This is the enable bit for txfifo_empty_int_st register."] +pub type TXFIFO_EMPTY_INT_ENA_R = crate::BitReader; +#[doc = "Field `TXFIFO_EMPTY_INT_ENA` writer - This is the enable bit for txfifo_empty_int_st register."] +pub type TXFIFO_EMPTY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARITY_ERR_INT_ENA` reader - This is the enable bit for parity_err_int_st register."] +pub type PARITY_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `PARITY_ERR_INT_ENA` writer - This is the enable bit for parity_err_int_st register."] +pub type PARITY_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRM_ERR_INT_ENA` reader - This is the enable bit for frm_err_int_st register."] +pub type FRM_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `FRM_ERR_INT_ENA` writer - This is the enable bit for frm_err_int_st register."] +pub type FRM_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF_INT_ENA` reader - This is the enable bit for rxfifo_ovf_int_st register."] +pub type RXFIFO_OVF_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_ENA` writer - This is the enable bit for rxfifo_ovf_int_st register."] +pub type RXFIFO_OVF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSR_CHG_INT_ENA` reader - This is the enable bit for dsr_chg_int_st register."] +pub type DSR_CHG_INT_ENA_R = crate::BitReader; +#[doc = "Field `DSR_CHG_INT_ENA` writer - This is the enable bit for dsr_chg_int_st register."] +pub type DSR_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTS_CHG_INT_ENA` reader - This is the enable bit for cts_chg_int_st register."] +pub type CTS_CHG_INT_ENA_R = crate::BitReader; +#[doc = "Field `CTS_CHG_INT_ENA` writer - This is the enable bit for cts_chg_int_st register."] +pub type CTS_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRK_DET_INT_ENA` reader - This is the enable bit for brk_det_int_st register."] +pub type BRK_DET_INT_ENA_R = crate::BitReader; +#[doc = "Field `BRK_DET_INT_ENA` writer - This is the enable bit for brk_det_int_st register."] +pub type BRK_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_TOUT_INT_ENA` reader - This is the enable bit for rxfifo_tout_int_st register."] +pub type RXFIFO_TOUT_INT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_TOUT_INT_ENA` writer - This is the enable bit for rxfifo_tout_int_st register."] +pub type RXFIFO_TOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XON_INT_ENA` reader - This is the enable bit for sw_xon_int_st register."] +pub type SW_XON_INT_ENA_R = crate::BitReader; +#[doc = "Field `SW_XON_INT_ENA` writer - This is the enable bit for sw_xon_int_st register."] +pub type SW_XON_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XOFF_INT_ENA` reader - This is the enable bit for sw_xoff_int_st register."] +pub type SW_XOFF_INT_ENA_R = crate::BitReader; +#[doc = "Field `SW_XOFF_INT_ENA` writer - This is the enable bit for sw_xoff_int_st register."] +pub type SW_XOFF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GLITCH_DET_INT_ENA` reader - This is the enable bit for glitch_det_int_st register."] +pub type GLITCH_DET_INT_ENA_R = crate::BitReader; +#[doc = "Field `GLITCH_DET_INT_ENA` writer - This is the enable bit for glitch_det_int_st register."] +pub type GLITCH_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_DONE_INT_ENA` reader - This is the enable bit for tx_brk_done_int_st register."] +pub type TX_BRK_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_BRK_DONE_INT_ENA` writer - This is the enable bit for tx_brk_done_int_st register."] +pub type TX_BRK_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_ENA` reader - This is the enable bit for tx_brk_idle_done_int_st register."] +pub type TX_BRK_IDLE_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_ENA` writer - This is the enable bit for tx_brk_idle_done_int_st register."] +pub type TX_BRK_IDLE_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DONE_INT_ENA` reader - This is the enable bit for tx_done_int_st register."] +pub type TX_DONE_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_DONE_INT_ENA` writer - This is the enable bit for tx_done_int_st register."] +pub type TX_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485_PARITY_ERR_INT_ENA` reader - This is the enable bit for rs485_parity_err_int_st register."] +pub type RS485_PARITY_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `RS485_PARITY_ERR_INT_ENA` writer - This is the enable bit for rs485_parity_err_int_st register."] +pub type RS485_PARITY_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485_FRM_ERR_INT_ENA` reader - This is the enable bit for rs485_parity_err_int_st register."] +pub type RS485_FRM_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `RS485_FRM_ERR_INT_ENA` writer - This is the enable bit for rs485_parity_err_int_st register."] +pub type RS485_FRM_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485_CLASH_INT_ENA` reader - This is the enable bit for rs485_clash_int_st register."] +pub type RS485_CLASH_INT_ENA_R = crate::BitReader; +#[doc = "Field `RS485_CLASH_INT_ENA` writer - This is the enable bit for rs485_clash_int_st register."] +pub type RS485_CLASH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AT_CMD_CHAR_DET_INT_ENA` reader - This is the enable bit for at_cmd_char_det_int_st register."] +pub type AT_CMD_CHAR_DET_INT_ENA_R = crate::BitReader; +#[doc = "Field `AT_CMD_CHAR_DET_INT_ENA` writer - This is the enable bit for at_cmd_char_det_int_st register."] +pub type AT_CMD_CHAR_DET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAKEUP_INT_ENA` reader - This is the enable bit for uart_wakeup_int_st register."] +pub type WAKEUP_INT_ENA_R = crate::BitReader; +#[doc = "Field `WAKEUP_INT_ENA` writer - This is the enable bit for uart_wakeup_int_st register."] +pub type WAKEUP_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."] + #[inline(always)] + pub fn rxfifo_full_int_ena(&self) -> RXFIFO_FULL_INT_ENA_R { + RXFIFO_FULL_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This is the enable bit for txfifo_empty_int_st register."] + #[inline(always)] + pub fn txfifo_empty_int_ena(&self) -> TXFIFO_EMPTY_INT_ENA_R { + TXFIFO_EMPTY_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."] + #[inline(always)] + pub fn parity_err_int_ena(&self) -> PARITY_ERR_INT_ENA_R { + PARITY_ERR_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."] + #[inline(always)] + pub fn frm_err_int_ena(&self) -> FRM_ERR_INT_ENA_R { + FRM_ERR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."] + #[inline(always)] + pub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R { + RXFIFO_OVF_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."] + #[inline(always)] + pub fn dsr_chg_int_ena(&self) -> DSR_CHG_INT_ENA_R { + DSR_CHG_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."] + #[inline(always)] + pub fn cts_chg_int_ena(&self) -> CTS_CHG_INT_ENA_R { + CTS_CHG_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."] + #[inline(always)] + pub fn brk_det_int_ena(&self) -> BRK_DET_INT_ENA_R { + BRK_DET_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."] + #[inline(always)] + pub fn rxfifo_tout_int_ena(&self) -> RXFIFO_TOUT_INT_ENA_R { + RXFIFO_TOUT_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."] + #[inline(always)] + pub fn sw_xon_int_ena(&self) -> SW_XON_INT_ENA_R { + SW_XON_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."] + #[inline(always)] + pub fn sw_xoff_int_ena(&self) -> SW_XOFF_INT_ENA_R { + SW_XOFF_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."] + #[inline(always)] + pub fn glitch_det_int_ena(&self) -> GLITCH_DET_INT_ENA_R { + GLITCH_DET_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."] + #[inline(always)] + pub fn tx_brk_done_int_ena(&self) -> TX_BRK_DONE_INT_ENA_R { + TX_BRK_DONE_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."] + #[inline(always)] + pub fn tx_brk_idle_done_int_ena(&self) -> TX_BRK_IDLE_DONE_INT_ENA_R { + TX_BRK_IDLE_DONE_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."] + #[inline(always)] + pub fn tx_done_int_ena(&self) -> TX_DONE_INT_ENA_R { + TX_DONE_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - This is the enable bit for rs485_parity_err_int_st register."] + #[inline(always)] + pub fn rs485_parity_err_int_ena(&self) -> RS485_PARITY_ERR_INT_ENA_R { + RS485_PARITY_ERR_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - This is the enable bit for rs485_parity_err_int_st register."] + #[inline(always)] + pub fn rs485_frm_err_int_ena(&self) -> RS485_FRM_ERR_INT_ENA_R { + RS485_FRM_ERR_INT_ENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - This is the enable bit for rs485_clash_int_st register."] + #[inline(always)] + pub fn rs485_clash_int_ena(&self) -> RS485_CLASH_INT_ENA_R { + RS485_CLASH_INT_ENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."] + #[inline(always)] + pub fn at_cmd_char_det_int_ena(&self) -> AT_CMD_CHAR_DET_INT_ENA_R { + AT_CMD_CHAR_DET_INT_ENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - This is the enable bit for uart_wakeup_int_st register."] + #[inline(always)] + pub fn wakeup_int_ena(&self) -> WAKEUP_INT_ENA_R { + WAKEUP_INT_ENA_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "rxfifo_full_int_ena", + &format_args!("{}", self.rxfifo_full_int_ena().bit()), + ) + .field( + "txfifo_empty_int_ena", + &format_args!("{}", self.txfifo_empty_int_ena().bit()), + ) + .field( + "parity_err_int_ena", + &format_args!("{}", self.parity_err_int_ena().bit()), + ) + .field( + "frm_err_int_ena", + &format_args!("{}", self.frm_err_int_ena().bit()), + ) + .field( + "rxfifo_ovf_int_ena", + &format_args!("{}", self.rxfifo_ovf_int_ena().bit()), + ) + .field( + "dsr_chg_int_ena", + &format_args!("{}", self.dsr_chg_int_ena().bit()), + ) + .field( + "cts_chg_int_ena", + &format_args!("{}", self.cts_chg_int_ena().bit()), + ) + .field( + "brk_det_int_ena", + &format_args!("{}", self.brk_det_int_ena().bit()), + ) + .field( + "rxfifo_tout_int_ena", + &format_args!("{}", self.rxfifo_tout_int_ena().bit()), + ) + .field( + "sw_xon_int_ena", + &format_args!("{}", self.sw_xon_int_ena().bit()), + ) + .field( + "sw_xoff_int_ena", + &format_args!("{}", self.sw_xoff_int_ena().bit()), + ) + .field( + "glitch_det_int_ena", + &format_args!("{}", self.glitch_det_int_ena().bit()), + ) + .field( + "tx_brk_done_int_ena", + &format_args!("{}", self.tx_brk_done_int_ena().bit()), + ) + .field( + "tx_brk_idle_done_int_ena", + &format_args!("{}", self.tx_brk_idle_done_int_ena().bit()), + ) + .field( + "tx_done_int_ena", + &format_args!("{}", self.tx_done_int_ena().bit()), + ) + .field( + "rs485_parity_err_int_ena", + &format_args!("{}", self.rs485_parity_err_int_ena().bit()), + ) + .field( + "rs485_frm_err_int_ena", + &format_args!("{}", self.rs485_frm_err_int_ena().bit()), + ) + .field( + "rs485_clash_int_ena", + &format_args!("{}", self.rs485_clash_int_ena().bit()), + ) + .field( + "at_cmd_char_det_int_ena", + &format_args!("{}", self.at_cmd_char_det_int_ena().bit()), + ) + .field( + "wakeup_int_ena", + &format_args!("{}", self.wakeup_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."] + #[inline(always)] + #[must_use] + pub fn rxfifo_full_int_ena(&mut self) -> RXFIFO_FULL_INT_ENA_W { + RXFIFO_FULL_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - This is the enable bit for txfifo_empty_int_st register."] + #[inline(always)] + #[must_use] + pub fn txfifo_empty_int_ena(&mut self) -> TXFIFO_EMPTY_INT_ENA_W { + TXFIFO_EMPTY_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."] + #[inline(always)] + #[must_use] + pub fn parity_err_int_ena(&mut self) -> PARITY_ERR_INT_ENA_W { + PARITY_ERR_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."] + #[inline(always)] + #[must_use] + pub fn frm_err_int_ena(&mut self) -> FRM_ERR_INT_ENA_W { + FRM_ERR_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."] + #[inline(always)] + #[must_use] + pub fn rxfifo_ovf_int_ena(&mut self) -> RXFIFO_OVF_INT_ENA_W { + RXFIFO_OVF_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."] + #[inline(always)] + #[must_use] + pub fn dsr_chg_int_ena(&mut self) -> DSR_CHG_INT_ENA_W { + DSR_CHG_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."] + #[inline(always)] + #[must_use] + pub fn cts_chg_int_ena(&mut self) -> CTS_CHG_INT_ENA_W { + CTS_CHG_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."] + #[inline(always)] + #[must_use] + pub fn brk_det_int_ena(&mut self) -> BRK_DET_INT_ENA_W { + BRK_DET_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."] + #[inline(always)] + #[must_use] + pub fn rxfifo_tout_int_ena(&mut self) -> RXFIFO_TOUT_INT_ENA_W { + RXFIFO_TOUT_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."] + #[inline(always)] + #[must_use] + pub fn sw_xon_int_ena(&mut self) -> SW_XON_INT_ENA_W { + SW_XON_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."] + #[inline(always)] + #[must_use] + pub fn sw_xoff_int_ena(&mut self) -> SW_XOFF_INT_ENA_W { + SW_XOFF_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."] + #[inline(always)] + #[must_use] + pub fn glitch_det_int_ena(&mut self) -> GLITCH_DET_INT_ENA_W { + GLITCH_DET_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."] + #[inline(always)] + #[must_use] + pub fn tx_brk_done_int_ena(&mut self) -> TX_BRK_DONE_INT_ENA_W { + TX_BRK_DONE_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."] + #[inline(always)] + #[must_use] + pub fn tx_brk_idle_done_int_ena(&mut self) -> TX_BRK_IDLE_DONE_INT_ENA_W { + TX_BRK_IDLE_DONE_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."] + #[inline(always)] + #[must_use] + pub fn tx_done_int_ena(&mut self) -> TX_DONE_INT_ENA_W { + TX_DONE_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - This is the enable bit for rs485_parity_err_int_st register."] + #[inline(always)] + #[must_use] + pub fn rs485_parity_err_int_ena(&mut self) -> RS485_PARITY_ERR_INT_ENA_W { + RS485_PARITY_ERR_INT_ENA_W::new(self, 15) + } + #[doc = "Bit 16 - This is the enable bit for rs485_parity_err_int_st register."] + #[inline(always)] + #[must_use] + pub fn rs485_frm_err_int_ena(&mut self) -> RS485_FRM_ERR_INT_ENA_W { + RS485_FRM_ERR_INT_ENA_W::new(self, 16) + } + #[doc = "Bit 17 - This is the enable bit for rs485_clash_int_st register."] + #[inline(always)] + #[must_use] + pub fn rs485_clash_int_ena(&mut self) -> RS485_CLASH_INT_ENA_W { + RS485_CLASH_INT_ENA_W::new(self, 17) + } + #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."] + #[inline(always)] + #[must_use] + pub fn at_cmd_char_det_int_ena(&mut self) -> AT_CMD_CHAR_DET_INT_ENA_W { + AT_CMD_CHAR_DET_INT_ENA_W::new(self, 18) + } + #[doc = "Bit 19 - This is the enable bit for uart_wakeup_int_st register."] + #[inline(always)] + #[must_use] + pub fn wakeup_int_ena(&mut self) -> WAKEUP_INT_ENA_W { + WAKEUP_INT_ENA_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/int_raw.rs b/esp32p4/src/uart0/int_raw.rs new file mode 100644 index 0000000000..38227dde4b --- /dev/null +++ b/esp32p4/src/uart0/int_raw.rs @@ -0,0 +1,427 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO_FULL_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] +pub type RXFIFO_FULL_INT_RAW_R = crate::BitReader; +#[doc = "Field `RXFIFO_FULL_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] +pub type RXFIFO_FULL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO_EMPTY_INT_RAW` reader - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] +pub type TXFIFO_EMPTY_INT_RAW_R = crate::BitReader; +#[doc = "Field `TXFIFO_EMPTY_INT_RAW` writer - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] +pub type TXFIFO_EMPTY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARITY_ERR_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] +pub type PARITY_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `PARITY_ERR_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] +pub type PARITY_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRM_ERR_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a data frame error ."] +pub type FRM_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `FRM_ERR_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a data frame error ."] +pub type FRM_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_OVF_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] +pub type RXFIFO_OVF_INT_RAW_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] +pub type RXFIFO_OVF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSR_CHG_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] +pub type DSR_CHG_INT_RAW_R = crate::BitReader; +#[doc = "Field `DSR_CHG_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] +pub type DSR_CHG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTS_CHG_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] +pub type CTS_CHG_INT_RAW_R = crate::BitReader; +#[doc = "Field `CTS_CHG_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] +pub type CTS_CHG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BRK_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] +pub type BRK_DET_INT_RAW_R = crate::BitReader; +#[doc = "Field `BRK_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] +pub type BRK_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_TOUT_INT_RAW` reader - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] +pub type RXFIFO_TOUT_INT_RAW_R = crate::BitReader; +#[doc = "Field `RXFIFO_TOUT_INT_RAW` writer - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] +pub type RXFIFO_TOUT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XON_INT_RAW` reader - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] +pub type SW_XON_INT_RAW_R = crate::BitReader; +#[doc = "Field `SW_XON_INT_RAW` writer - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] +pub type SW_XON_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_XOFF_INT_RAW` reader - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] +pub type SW_XOFF_INT_RAW_R = crate::BitReader; +#[doc = "Field `SW_XOFF_INT_RAW` writer - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] +pub type SW_XOFF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GLITCH_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] +pub type GLITCH_DET_INT_RAW_R = crate::BitReader; +#[doc = "Field `GLITCH_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] +pub type GLITCH_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] +pub type TX_BRK_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_BRK_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] +pub type TX_BRK_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] +pub type TX_BRK_IDLE_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] +pub type TX_BRK_IDLE_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DONE_INT_RAW` reader - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] +pub type TX_DONE_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_DONE_INT_RAW` writer - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] +pub type TX_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485_PARITY_ERR_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode."] +pub type RS485_PARITY_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `RS485_PARITY_ERR_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode."] +pub type RS485_PARITY_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485_FRM_ERR_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode."] +pub type RS485_FRM_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `RS485_FRM_ERR_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode."] +pub type RS485_FRM_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485_CLASH_INT_RAW` reader - This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode."] +pub type RS485_CLASH_INT_RAW_R = crate::BitReader; +#[doc = "Field `RS485_CLASH_INT_RAW` writer - This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode."] +pub type RS485_CLASH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AT_CMD_CHAR_DET_INT_RAW` reader - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] +pub type AT_CMD_CHAR_DET_INT_RAW_R = crate::BitReader; +#[doc = "Field `AT_CMD_CHAR_DET_INT_RAW` writer - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] +pub type AT_CMD_CHAR_DET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAKEUP_INT_RAW` reader - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] +pub type WAKEUP_INT_RAW_R = crate::BitReader; +#[doc = "Field `WAKEUP_INT_RAW` writer - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] +pub type WAKEUP_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] + #[inline(always)] + pub fn rxfifo_full_int_raw(&self) -> RXFIFO_FULL_INT_RAW_R { + RXFIFO_FULL_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] + #[inline(always)] + pub fn txfifo_empty_int_raw(&self) -> TXFIFO_EMPTY_INT_RAW_R { + TXFIFO_EMPTY_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] + #[inline(always)] + pub fn parity_err_int_raw(&self) -> PARITY_ERR_INT_RAW_R { + PARITY_ERR_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This interrupt raw bit turns to high level when receiver detects a data frame error ."] + #[inline(always)] + pub fn frm_err_int_raw(&self) -> FRM_ERR_INT_RAW_R { + FRM_ERR_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] + #[inline(always)] + pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R { + RXFIFO_OVF_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] + #[inline(always)] + pub fn dsr_chg_int_raw(&self) -> DSR_CHG_INT_RAW_R { + DSR_CHG_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] + #[inline(always)] + pub fn cts_chg_int_raw(&self) -> CTS_CHG_INT_RAW_R { + CTS_CHG_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] + #[inline(always)] + pub fn brk_det_int_raw(&self) -> BRK_DET_INT_RAW_R { + BRK_DET_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] + #[inline(always)] + pub fn rxfifo_tout_int_raw(&self) -> RXFIFO_TOUT_INT_RAW_R { + RXFIFO_TOUT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] + #[inline(always)] + pub fn sw_xon_int_raw(&self) -> SW_XON_INT_RAW_R { + SW_XON_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] + #[inline(always)] + pub fn sw_xoff_int_raw(&self) -> SW_XOFF_INT_RAW_R { + SW_XOFF_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] + #[inline(always)] + pub fn glitch_det_int_raw(&self) -> GLITCH_DET_INT_RAW_R { + GLITCH_DET_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] + #[inline(always)] + pub fn tx_brk_done_int_raw(&self) -> TX_BRK_DONE_INT_RAW_R { + TX_BRK_DONE_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] + #[inline(always)] + pub fn tx_brk_idle_done_int_raw(&self) -> TX_BRK_IDLE_DONE_INT_RAW_R { + TX_BRK_IDLE_DONE_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] + #[inline(always)] + pub fn tx_done_int_raw(&self) -> TX_DONE_INT_RAW_R { + TX_DONE_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode."] + #[inline(always)] + pub fn rs485_parity_err_int_raw(&self) -> RS485_PARITY_ERR_INT_RAW_R { + RS485_PARITY_ERR_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode."] + #[inline(always)] + pub fn rs485_frm_err_int_raw(&self) -> RS485_FRM_ERR_INT_RAW_R { + RS485_FRM_ERR_INT_RAW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode."] + #[inline(always)] + pub fn rs485_clash_int_raw(&self) -> RS485_CLASH_INT_RAW_R { + RS485_CLASH_INT_RAW_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] + #[inline(always)] + pub fn at_cmd_char_det_int_raw(&self) -> AT_CMD_CHAR_DET_INT_RAW_R { + AT_CMD_CHAR_DET_INT_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] + #[inline(always)] + pub fn wakeup_int_raw(&self) -> WAKEUP_INT_RAW_R { + WAKEUP_INT_RAW_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "rxfifo_full_int_raw", + &format_args!("{}", self.rxfifo_full_int_raw().bit()), + ) + .field( + "txfifo_empty_int_raw", + &format_args!("{}", self.txfifo_empty_int_raw().bit()), + ) + .field( + "parity_err_int_raw", + &format_args!("{}", self.parity_err_int_raw().bit()), + ) + .field( + "frm_err_int_raw", + &format_args!("{}", self.frm_err_int_raw().bit()), + ) + .field( + "rxfifo_ovf_int_raw", + &format_args!("{}", self.rxfifo_ovf_int_raw().bit()), + ) + .field( + "dsr_chg_int_raw", + &format_args!("{}", self.dsr_chg_int_raw().bit()), + ) + .field( + "cts_chg_int_raw", + &format_args!("{}", self.cts_chg_int_raw().bit()), + ) + .field( + "brk_det_int_raw", + &format_args!("{}", self.brk_det_int_raw().bit()), + ) + .field( + "rxfifo_tout_int_raw", + &format_args!("{}", self.rxfifo_tout_int_raw().bit()), + ) + .field( + "sw_xon_int_raw", + &format_args!("{}", self.sw_xon_int_raw().bit()), + ) + .field( + "sw_xoff_int_raw", + &format_args!("{}", self.sw_xoff_int_raw().bit()), + ) + .field( + "glitch_det_int_raw", + &format_args!("{}", self.glitch_det_int_raw().bit()), + ) + .field( + "tx_brk_done_int_raw", + &format_args!("{}", self.tx_brk_done_int_raw().bit()), + ) + .field( + "tx_brk_idle_done_int_raw", + &format_args!("{}", self.tx_brk_idle_done_int_raw().bit()), + ) + .field( + "tx_done_int_raw", + &format_args!("{}", self.tx_done_int_raw().bit()), + ) + .field( + "rs485_parity_err_int_raw", + &format_args!("{}", self.rs485_parity_err_int_raw().bit()), + ) + .field( + "rs485_frm_err_int_raw", + &format_args!("{}", self.rs485_frm_err_int_raw().bit()), + ) + .field( + "rs485_clash_int_raw", + &format_args!("{}", self.rs485_clash_int_raw().bit()), + ) + .field( + "at_cmd_char_det_int_raw", + &format_args!("{}", self.at_cmd_char_det_int_raw().bit()), + ) + .field( + "wakeup_int_raw", + &format_args!("{}", self.wakeup_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."] + #[inline(always)] + #[must_use] + pub fn rxfifo_full_int_raw(&mut self) -> RXFIFO_FULL_INT_RAW_W { + RXFIFO_FULL_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies ."] + #[inline(always)] + #[must_use] + pub fn txfifo_empty_int_raw(&mut self) -> TXFIFO_EMPTY_INT_RAW_W { + TXFIFO_EMPTY_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - This interrupt raw bit turns to high level when receiver detects a parity error in the data."] + #[inline(always)] + #[must_use] + pub fn parity_err_int_raw(&mut self) -> PARITY_ERR_INT_RAW_W { + PARITY_ERR_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - This interrupt raw bit turns to high level when receiver detects a data frame error ."] + #[inline(always)] + #[must_use] + pub fn frm_err_int_raw(&mut self) -> FRM_ERR_INT_RAW_W { + FRM_ERR_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store."] + #[inline(always)] + #[must_use] + pub fn rxfifo_ovf_int_raw(&mut self) -> RXFIFO_OVF_INT_RAW_W { + RXFIFO_OVF_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal."] + #[inline(always)] + #[must_use] + pub fn dsr_chg_int_raw(&mut self) -> DSR_CHG_INT_RAW_W { + DSR_CHG_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal."] + #[inline(always)] + #[must_use] + pub fn cts_chg_int_raw(&mut self) -> CTS_CHG_INT_RAW_W { + CTS_CHG_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit."] + #[inline(always)] + #[must_use] + pub fn brk_det_int_raw(&mut self) -> BRK_DET_INT_RAW_W { + BRK_DET_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte."] + #[inline(always)] + #[must_use] + pub fn rxfifo_tout_int_raw(&mut self) -> RXFIFO_TOUT_INT_RAW_W { + RXFIFO_TOUT_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1."] + #[inline(always)] + #[must_use] + pub fn sw_xon_int_raw(&mut self) -> SW_XON_INT_RAW_W { + SW_XON_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1."] + #[inline(always)] + #[must_use] + pub fn sw_xoff_int_raw(&mut self) -> SW_XOFF_INT_RAW_W { + SW_XOFF_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit."] + #[inline(always)] + #[must_use] + pub fn glitch_det_int_raw(&mut self) -> GLITCH_DET_INT_RAW_W { + GLITCH_DET_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 12 - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent."] + #[inline(always)] + #[must_use] + pub fn tx_brk_done_int_raw(&mut self) -> TX_BRK_DONE_INT_RAW_W { + TX_BRK_DONE_INT_RAW_W::new(self, 12) + } + #[doc = "Bit 13 - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data."] + #[inline(always)] + #[must_use] + pub fn tx_brk_idle_done_int_raw(&mut self) -> TX_BRK_IDLE_DONE_INT_RAW_W { + TX_BRK_IDLE_DONE_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 14 - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO."] + #[inline(always)] + #[must_use] + pub fn tx_done_int_raw(&mut self) -> TX_DONE_INT_RAW_W { + TX_DONE_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode."] + #[inline(always)] + #[must_use] + pub fn rs485_parity_err_int_raw(&mut self) -> RS485_PARITY_ERR_INT_RAW_W { + RS485_PARITY_ERR_INT_RAW_W::new(self, 15) + } + #[doc = "Bit 16 - This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode."] + #[inline(always)] + #[must_use] + pub fn rs485_frm_err_int_raw(&mut self) -> RS485_FRM_ERR_INT_RAW_W { + RS485_FRM_ERR_INT_RAW_W::new(self, 16) + } + #[doc = "Bit 17 - This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode."] + #[inline(always)] + #[must_use] + pub fn rs485_clash_int_raw(&mut self) -> RS485_CLASH_INT_RAW_W { + RS485_CLASH_INT_RAW_W::new(self, 17) + } + #[doc = "Bit 18 - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char."] + #[inline(always)] + #[must_use] + pub fn at_cmd_char_det_int_raw(&mut self) -> AT_CMD_CHAR_DET_INT_RAW_W { + AT_CMD_CHAR_DET_INT_RAW_W::new(self, 18) + } + #[doc = "Bit 19 - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode."] + #[inline(always)] + #[must_use] + pub fn wakeup_int_raw(&mut self) -> WAKEUP_INT_RAW_W { + WAKEUP_INT_RAW_W::new(self, 19) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0x02"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/uart0/int_st.rs b/esp32p4/src/uart0/int_st.rs new file mode 100644 index 0000000000..07c161567c --- /dev/null +++ b/esp32p4/src/uart0/int_st.rs @@ -0,0 +1,248 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_FULL_INT_ST` reader - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."] +pub type RXFIFO_FULL_INT_ST_R = crate::BitReader; +#[doc = "Field `TXFIFO_EMPTY_INT_ST` reader - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."] +pub type TXFIFO_EMPTY_INT_ST_R = crate::BitReader; +#[doc = "Field `PARITY_ERR_INT_ST` reader - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."] +pub type PARITY_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `FRM_ERR_INT_ST` reader - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."] +pub type FRM_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `RXFIFO_OVF_INT_ST` reader - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."] +pub type RXFIFO_OVF_INT_ST_R = crate::BitReader; +#[doc = "Field `DSR_CHG_INT_ST` reader - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."] +pub type DSR_CHG_INT_ST_R = crate::BitReader; +#[doc = "Field `CTS_CHG_INT_ST` reader - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."] +pub type CTS_CHG_INT_ST_R = crate::BitReader; +#[doc = "Field `BRK_DET_INT_ST` reader - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."] +pub type BRK_DET_INT_ST_R = crate::BitReader; +#[doc = "Field `RXFIFO_TOUT_INT_ST` reader - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."] +pub type RXFIFO_TOUT_INT_ST_R = crate::BitReader; +#[doc = "Field `SW_XON_INT_ST` reader - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."] +pub type SW_XON_INT_ST_R = crate::BitReader; +#[doc = "Field `SW_XOFF_INT_ST` reader - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."] +pub type SW_XOFF_INT_ST_R = crate::BitReader; +#[doc = "Field `GLITCH_DET_INT_ST` reader - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."] +pub type GLITCH_DET_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_BRK_DONE_INT_ST` reader - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."] +pub type TX_BRK_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_BRK_IDLE_DONE_INT_ST` reader - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."] +pub type TX_BRK_IDLE_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_DONE_INT_ST` reader - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."] +pub type TX_DONE_INT_ST_R = crate::BitReader; +#[doc = "Field `RS485_PARITY_ERR_INT_ST` reader - This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1."] +pub type RS485_PARITY_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `RS485_FRM_ERR_INT_ST` reader - This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1."] +pub type RS485_FRM_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `RS485_CLASH_INT_ST` reader - This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1."] +pub type RS485_CLASH_INT_ST_R = crate::BitReader; +#[doc = "Field `AT_CMD_CHAR_DET_INT_ST` reader - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."] +pub type AT_CMD_CHAR_DET_INT_ST_R = crate::BitReader; +#[doc = "Field `WAKEUP_INT_ST` reader - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."] +pub type WAKEUP_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."] + #[inline(always)] + pub fn rxfifo_full_int_st(&self) -> RXFIFO_FULL_INT_ST_R { + RXFIFO_FULL_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."] + #[inline(always)] + pub fn txfifo_empty_int_st(&self) -> TXFIFO_EMPTY_INT_ST_R { + TXFIFO_EMPTY_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."] + #[inline(always)] + pub fn parity_err_int_st(&self) -> PARITY_ERR_INT_ST_R { + PARITY_ERR_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."] + #[inline(always)] + pub fn frm_err_int_st(&self) -> FRM_ERR_INT_ST_R { + FRM_ERR_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."] + #[inline(always)] + pub fn rxfifo_ovf_int_st(&self) -> RXFIFO_OVF_INT_ST_R { + RXFIFO_OVF_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."] + #[inline(always)] + pub fn dsr_chg_int_st(&self) -> DSR_CHG_INT_ST_R { + DSR_CHG_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."] + #[inline(always)] + pub fn cts_chg_int_st(&self) -> CTS_CHG_INT_ST_R { + CTS_CHG_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."] + #[inline(always)] + pub fn brk_det_int_st(&self) -> BRK_DET_INT_ST_R { + BRK_DET_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."] + #[inline(always)] + pub fn rxfifo_tout_int_st(&self) -> RXFIFO_TOUT_INT_ST_R { + RXFIFO_TOUT_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."] + #[inline(always)] + pub fn sw_xon_int_st(&self) -> SW_XON_INT_ST_R { + SW_XON_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."] + #[inline(always)] + pub fn sw_xoff_int_st(&self) -> SW_XOFF_INT_ST_R { + SW_XOFF_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."] + #[inline(always)] + pub fn glitch_det_int_st(&self) -> GLITCH_DET_INT_ST_R { + GLITCH_DET_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."] + #[inline(always)] + pub fn tx_brk_done_int_st(&self) -> TX_BRK_DONE_INT_ST_R { + TX_BRK_DONE_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."] + #[inline(always)] + pub fn tx_brk_idle_done_int_st(&self) -> TX_BRK_IDLE_DONE_INT_ST_R { + TX_BRK_IDLE_DONE_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."] + #[inline(always)] + pub fn tx_done_int_st(&self) -> TX_DONE_INT_ST_R { + TX_DONE_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1."] + #[inline(always)] + pub fn rs485_parity_err_int_st(&self) -> RS485_PARITY_ERR_INT_ST_R { + RS485_PARITY_ERR_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1."] + #[inline(always)] + pub fn rs485_frm_err_int_st(&self) -> RS485_FRM_ERR_INT_ST_R { + RS485_FRM_ERR_INT_ST_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1."] + #[inline(always)] + pub fn rs485_clash_int_st(&self) -> RS485_CLASH_INT_ST_R { + RS485_CLASH_INT_ST_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."] + #[inline(always)] + pub fn at_cmd_char_det_int_st(&self) -> AT_CMD_CHAR_DET_INT_ST_R { + AT_CMD_CHAR_DET_INT_ST_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."] + #[inline(always)] + pub fn wakeup_int_st(&self) -> WAKEUP_INT_ST_R { + WAKEUP_INT_ST_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "rxfifo_full_int_st", + &format_args!("{}", self.rxfifo_full_int_st().bit()), + ) + .field( + "txfifo_empty_int_st", + &format_args!("{}", self.txfifo_empty_int_st().bit()), + ) + .field( + "parity_err_int_st", + &format_args!("{}", self.parity_err_int_st().bit()), + ) + .field( + "frm_err_int_st", + &format_args!("{}", self.frm_err_int_st().bit()), + ) + .field( + "rxfifo_ovf_int_st", + &format_args!("{}", self.rxfifo_ovf_int_st().bit()), + ) + .field( + "dsr_chg_int_st", + &format_args!("{}", self.dsr_chg_int_st().bit()), + ) + .field( + "cts_chg_int_st", + &format_args!("{}", self.cts_chg_int_st().bit()), + ) + .field( + "brk_det_int_st", + &format_args!("{}", self.brk_det_int_st().bit()), + ) + .field( + "rxfifo_tout_int_st", + &format_args!("{}", self.rxfifo_tout_int_st().bit()), + ) + .field( + "sw_xon_int_st", + &format_args!("{}", self.sw_xon_int_st().bit()), + ) + .field( + "sw_xoff_int_st", + &format_args!("{}", self.sw_xoff_int_st().bit()), + ) + .field( + "glitch_det_int_st", + &format_args!("{}", self.glitch_det_int_st().bit()), + ) + .field( + "tx_brk_done_int_st", + &format_args!("{}", self.tx_brk_done_int_st().bit()), + ) + .field( + "tx_brk_idle_done_int_st", + &format_args!("{}", self.tx_brk_idle_done_int_st().bit()), + ) + .field( + "tx_done_int_st", + &format_args!("{}", self.tx_done_int_st().bit()), + ) + .field( + "rs485_parity_err_int_st", + &format_args!("{}", self.rs485_parity_err_int_st().bit()), + ) + .field( + "rs485_frm_err_int_st", + &format_args!("{}", self.rs485_frm_err_int_st().bit()), + ) + .field( + "rs485_clash_int_st", + &format_args!("{}", self.rs485_clash_int_st().bit()), + ) + .field( + "at_cmd_char_det_int_st", + &format_args!("{}", self.at_cmd_char_det_int_st().bit()), + ) + .field( + "wakeup_int_st", + &format_args!("{}", self.wakeup_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/lowpulse.rs b/esp32p4/src/uart0/lowpulse.rs new file mode 100644 index 0000000000..046500d940 --- /dev/null +++ b/esp32p4/src/uart0/lowpulse.rs @@ -0,0 +1,36 @@ +#[doc = "Register `LOWPULSE` reader"] +pub type R = crate::R; +#[doc = "Field `MIN_CNT` reader - This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process."] +pub type MIN_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process."] + #[inline(always)] + pub fn min_cnt(&self) -> MIN_CNT_R { + MIN_CNT_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("LOWPULSE") + .field("min_cnt", &format_args!("{}", self.min_cnt().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Autobaud minimum low pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpulse::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LOWPULSE_SPEC; +impl crate::RegisterSpec for LOWPULSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lowpulse::R`](R) reader structure"] +impl crate::Readable for LOWPULSE_SPEC {} +#[doc = "`reset()` method sets LOWPULSE to value 0x0fff"] +impl crate::Resettable for LOWPULSE_SPEC { + const RESET_VALUE: Self::Ux = 0x0fff; +} diff --git a/esp32p4/src/uart0/mem_conf.rs b/esp32p4/src/uart0/mem_conf.rs new file mode 100644 index 0000000000..8982b26108 --- /dev/null +++ b/esp32p4/src/uart0/mem_conf.rs @@ -0,0 +1,85 @@ +#[doc = "Register `MEM_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `MEM_FORCE_PD` reader - Set this bit to force power down UART memory."] +pub type MEM_FORCE_PD_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PD` writer - Set this bit to force power down UART memory."] +pub type MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEM_FORCE_PU` reader - Set this bit to force power up UART memory."] +pub type MEM_FORCE_PU_R = crate::BitReader; +#[doc = "Field `MEM_FORCE_PU` writer - Set this bit to force power up UART memory."] +pub type MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 25 - Set this bit to force power down UART memory."] + #[inline(always)] + pub fn mem_force_pd(&self) -> MEM_FORCE_PD_R { + MEM_FORCE_PD_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Set this bit to force power up UART memory."] + #[inline(always)] + pub fn mem_force_pu(&self) -> MEM_FORCE_PU_R { + MEM_FORCE_PU_R::new(((self.bits >> 26) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_CONF") + .field( + "mem_force_pd", + &format_args!("{}", self.mem_force_pd().bit()), + ) + .field( + "mem_force_pu", + &format_args!("{}", self.mem_force_pu().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 25 - Set this bit to force power down UART memory."] + #[inline(always)] + #[must_use] + pub fn mem_force_pd(&mut self) -> MEM_FORCE_PD_W { + MEM_FORCE_PD_W::new(self, 25) + } + #[doc = "Bit 26 - Set this bit to force power up UART memory."] + #[inline(always)] + #[must_use] + pub fn mem_force_pu(&mut self) -> MEM_FORCE_PU_W { + MEM_FORCE_PU_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART memory power configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_CONF_SPEC; +impl crate::RegisterSpec for MEM_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_conf::R`](R) reader structure"] +impl crate::Readable for MEM_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_conf::W`](W) writer structure"] +impl crate::Writable for MEM_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_CONF to value 0"] +impl crate::Resettable for MEM_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/mem_rx_status.rs b/esp32p4/src/uart0/mem_rx_status.rs new file mode 100644 index 0000000000..a1c6b598c8 --- /dev/null +++ b/esp32p4/src/uart0/mem_rx_status.rs @@ -0,0 +1,50 @@ +#[doc = "Register `MEM_RX_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `RX_SRAM_RADDR` reader - This register stores the offset read address in RX-SRAM."] +pub type RX_SRAM_RADDR_R = crate::FieldReader; +#[doc = "Field `RX_SRAM_WADDR` reader - This register stores the offset write address in Rx-SRAM."] +pub type RX_SRAM_WADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - This register stores the offset read address in RX-SRAM."] + #[inline(always)] + pub fn rx_sram_raddr(&self) -> RX_SRAM_RADDR_R { + RX_SRAM_RADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 9:16 - This register stores the offset write address in Rx-SRAM."] + #[inline(always)] + pub fn rx_sram_waddr(&self) -> RX_SRAM_WADDR_R { + RX_SRAM_WADDR_R::new(((self.bits >> 9) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_RX_STATUS") + .field( + "rx_sram_raddr", + &format_args!("{}", self.rx_sram_raddr().bits()), + ) + .field( + "rx_sram_waddr", + &format_args!("{}", self.rx_sram_waddr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_RX_STATUS_SPEC; +impl crate::RegisterSpec for MEM_RX_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_rx_status::R`](R) reader structure"] +impl crate::Readable for MEM_RX_STATUS_SPEC {} +#[doc = "`reset()` method sets MEM_RX_STATUS to value 0x0001_0080"] +impl crate::Resettable for MEM_RX_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x0001_0080; +} diff --git a/esp32p4/src/uart0/mem_tx_status.rs b/esp32p4/src/uart0/mem_tx_status.rs new file mode 100644 index 0000000000..cf1fe8c613 --- /dev/null +++ b/esp32p4/src/uart0/mem_tx_status.rs @@ -0,0 +1,50 @@ +#[doc = "Register `MEM_TX_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `TX_SRAM_WADDR` reader - This register stores the offset write address in Tx-SRAM."] +pub type TX_SRAM_WADDR_R = crate::FieldReader; +#[doc = "Field `TX_SRAM_RADDR` reader - This register stores the offset read address in Tx-SRAM."] +pub type TX_SRAM_RADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - This register stores the offset write address in Tx-SRAM."] + #[inline(always)] + pub fn tx_sram_waddr(&self) -> TX_SRAM_WADDR_R { + TX_SRAM_WADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 9:16 - This register stores the offset read address in Tx-SRAM."] + #[inline(always)] + pub fn tx_sram_raddr(&self) -> TX_SRAM_RADDR_R { + TX_SRAM_RADDR_R::new(((self.bits >> 9) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_TX_STATUS") + .field( + "tx_sram_waddr", + &format_args!("{}", self.tx_sram_waddr().bits()), + ) + .field( + "tx_sram_raddr", + &format_args!("{}", self.tx_sram_raddr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_TX_STATUS_SPEC; +impl crate::RegisterSpec for MEM_TX_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_tx_status::R`](R) reader structure"] +impl crate::Readable for MEM_TX_STATUS_SPEC {} +#[doc = "`reset()` method sets MEM_TX_STATUS to value 0"] +impl crate::Resettable for MEM_TX_STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/negpulse.rs b/esp32p4/src/uart0/negpulse.rs new file mode 100644 index 0000000000..6adb9c5672 --- /dev/null +++ b/esp32p4/src/uart0/negpulse.rs @@ -0,0 +1,39 @@ +#[doc = "Register `NEGPULSE` reader"] +pub type R = crate::R; +#[doc = "Field `NEGEDGE_MIN_CNT` reader - This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process."] +pub type NEGEDGE_MIN_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process."] + #[inline(always)] + pub fn negedge_min_cnt(&self) -> NEGEDGE_MIN_CNT_R { + NEGEDGE_MIN_CNT_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NEGPULSE") + .field( + "negedge_min_cnt", + &format_args!("{}", self.negedge_min_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Autobaud low pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`negpulse::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NEGPULSE_SPEC; +impl crate::RegisterSpec for NEGPULSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`negpulse::R`](R) reader structure"] +impl crate::Readable for NEGPULSE_SPEC {} +#[doc = "`reset()` method sets NEGPULSE to value 0x0fff"] +impl crate::Resettable for NEGPULSE_SPEC { + const RESET_VALUE: Self::Ux = 0x0fff; +} diff --git a/esp32p4/src/uart0/pospulse.rs b/esp32p4/src/uart0/pospulse.rs new file mode 100644 index 0000000000..702db307a1 --- /dev/null +++ b/esp32p4/src/uart0/pospulse.rs @@ -0,0 +1,39 @@ +#[doc = "Register `POSPULSE` reader"] +pub type R = crate::R; +#[doc = "Field `POSEDGE_MIN_CNT` reader - This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process."] +pub type POSEDGE_MIN_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process."] + #[inline(always)] + pub fn posedge_min_cnt(&self) -> POSEDGE_MIN_CNT_R { + POSEDGE_MIN_CNT_R::new((self.bits & 0x0fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POSPULSE") + .field( + "posedge_min_cnt", + &format_args!("{}", self.posedge_min_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Autobaud high pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pospulse::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POSPULSE_SPEC; +impl crate::RegisterSpec for POSPULSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pospulse::R`](R) reader structure"] +impl crate::Readable for POSPULSE_SPEC {} +#[doc = "`reset()` method sets POSPULSE to value 0x0fff"] +impl crate::Resettable for POSPULSE_SPEC { + const RESET_VALUE: Self::Ux = 0x0fff; +} diff --git a/esp32p4/src/uart0/reg_update.rs b/esp32p4/src/uart0/reg_update.rs new file mode 100644 index 0000000000..c74dde8a5f --- /dev/null +++ b/esp32p4/src/uart0/reg_update.rs @@ -0,0 +1,63 @@ +#[doc = "Register `REG_UPDATE` reader"] +pub type R = crate::R; +#[doc = "Register `REG_UPDATE` writer"] +pub type W = crate::W; +#[doc = "Field `REG_UPDATE` reader - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."] +pub type REG_UPDATE_R = crate::BitReader; +#[doc = "Field `REG_UPDATE` writer - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."] +pub type REG_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."] + #[inline(always)] + pub fn reg_update(&self) -> REG_UPDATE_R { + REG_UPDATE_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_UPDATE") + .field("reg_update", &format_args!("{}", self.reg_update().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."] + #[inline(always)] + #[must_use] + pub fn reg_update(&mut self) -> REG_UPDATE_W { + REG_UPDATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART Registers Configuration Update register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_update::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_update::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_UPDATE_SPEC; +impl crate::RegisterSpec for REG_UPDATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_update::R`](R) reader structure"] +impl crate::Readable for REG_UPDATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_update::W`](W) writer structure"] +impl crate::Writable for REG_UPDATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_UPDATE to value 0"] +impl crate::Resettable for REG_UPDATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/rs485_conf_sync.rs b/esp32p4/src/uart0/rs485_conf_sync.rs new file mode 100644 index 0000000000..48ea65a156 --- /dev/null +++ b/esp32p4/src/uart0/rs485_conf_sync.rs @@ -0,0 +1,171 @@ +#[doc = "Register `RS485_CONF_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `RS485_CONF_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `RS485_EN` reader - Set this bit to choose the rs485 mode."] +pub type RS485_EN_R = crate::BitReader; +#[doc = "Field `RS485_EN` writer - Set this bit to choose the rs485 mode."] +pub type RS485_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DL0_EN` reader - Set this bit to delay the stop bit by 1 bit."] +pub type DL0_EN_R = crate::BitReader; +#[doc = "Field `DL0_EN` writer - Set this bit to delay the stop bit by 1 bit."] +pub type DL0_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DL1_EN` reader - Set this bit to delay the stop bit by 1 bit."] +pub type DL1_EN_R = crate::BitReader; +#[doc = "Field `DL1_EN` writer - Set this bit to delay the stop bit by 1 bit."] +pub type DL1_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485TX_RX_EN` reader - Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode."] +pub type RS485TX_RX_EN_R = crate::BitReader; +#[doc = "Field `RS485TX_RX_EN` writer - Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode."] +pub type RS485TX_RX_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485RXBY_TX_EN` reader - 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy."] +pub type RS485RXBY_TX_EN_R = crate::BitReader; +#[doc = "Field `RS485RXBY_TX_EN` writer - 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy."] +pub type RS485RXBY_TX_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485_RX_DLY_NUM` reader - This register is used to delay the receiver's internal data signal."] +pub type RS485_RX_DLY_NUM_R = crate::BitReader; +#[doc = "Field `RS485_RX_DLY_NUM` writer - This register is used to delay the receiver's internal data signal."] +pub type RS485_RX_DLY_NUM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS485_TX_DLY_NUM` reader - This register is used to delay the transmitter's internal data signal."] +pub type RS485_TX_DLY_NUM_R = crate::FieldReader; +#[doc = "Field `RS485_TX_DLY_NUM` writer - This register is used to delay the transmitter's internal data signal."] +pub type RS485_TX_DLY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - Set this bit to choose the rs485 mode."] + #[inline(always)] + pub fn rs485_en(&self) -> RS485_EN_R { + RS485_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to delay the stop bit by 1 bit."] + #[inline(always)] + pub fn dl0_en(&self) -> DL0_EN_R { + DL0_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to delay the stop bit by 1 bit."] + #[inline(always)] + pub fn dl1_en(&self) -> DL1_EN_R { + DL1_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode."] + #[inline(always)] + pub fn rs485tx_rx_en(&self) -> RS485TX_RX_EN_R { + RS485TX_RX_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy."] + #[inline(always)] + pub fn rs485rxby_tx_en(&self) -> RS485RXBY_TX_EN_R { + RS485RXBY_TX_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This register is used to delay the receiver's internal data signal."] + #[inline(always)] + pub fn rs485_rx_dly_num(&self) -> RS485_RX_DLY_NUM_R { + RS485_RX_DLY_NUM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:9 - This register is used to delay the transmitter's internal data signal."] + #[inline(always)] + pub fn rs485_tx_dly_num(&self) -> RS485_TX_DLY_NUM_R { + RS485_TX_DLY_NUM_R::new(((self.bits >> 6) & 0x0f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RS485_CONF_SYNC") + .field("rs485_en", &format_args!("{}", self.rs485_en().bit())) + .field("dl0_en", &format_args!("{}", self.dl0_en().bit())) + .field("dl1_en", &format_args!("{}", self.dl1_en().bit())) + .field( + "rs485tx_rx_en", + &format_args!("{}", self.rs485tx_rx_en().bit()), + ) + .field( + "rs485rxby_tx_en", + &format_args!("{}", self.rs485rxby_tx_en().bit()), + ) + .field( + "rs485_rx_dly_num", + &format_args!("{}", self.rs485_rx_dly_num().bit()), + ) + .field( + "rs485_tx_dly_num", + &format_args!("{}", self.rs485_tx_dly_num().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to choose the rs485 mode."] + #[inline(always)] + #[must_use] + pub fn rs485_en(&mut self) -> RS485_EN_W { + RS485_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to delay the stop bit by 1 bit."] + #[inline(always)] + #[must_use] + pub fn dl0_en(&mut self) -> DL0_EN_W { + DL0_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to delay the stop bit by 1 bit."] + #[inline(always)] + #[must_use] + pub fn dl1_en(&mut self) -> DL1_EN_W { + DL1_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode."] + #[inline(always)] + #[must_use] + pub fn rs485tx_rx_en(&mut self) -> RS485TX_RX_EN_W { + RS485TX_RX_EN_W::new(self, 3) + } + #[doc = "Bit 4 - 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy."] + #[inline(always)] + #[must_use] + pub fn rs485rxby_tx_en(&mut self) -> RS485RXBY_TX_EN_W { + RS485RXBY_TX_EN_W::new(self, 4) + } + #[doc = "Bit 5 - This register is used to delay the receiver's internal data signal."] + #[inline(always)] + #[must_use] + pub fn rs485_rx_dly_num(&mut self) -> RS485_RX_DLY_NUM_W { + RS485_RX_DLY_NUM_W::new(self, 5) + } + #[doc = "Bits 6:9 - This register is used to delay the transmitter's internal data signal."] + #[inline(always)] + #[must_use] + pub fn rs485_tx_dly_num(&mut self) -> RS485_TX_DLY_NUM_W { + RS485_TX_DLY_NUM_W::new(self, 6) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "RS485 mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rs485_conf_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rs485_conf_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RS485_CONF_SYNC_SPEC; +impl crate::RegisterSpec for RS485_CONF_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rs485_conf_sync::R`](R) reader structure"] +impl crate::Readable for RS485_CONF_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rs485_conf_sync::W`](W) writer structure"] +impl crate::Writable for RS485_CONF_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RS485_CONF_SYNC to value 0"] +impl crate::Resettable for RS485_CONF_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/rx_filt.rs b/esp32p4/src/uart0/rx_filt.rs new file mode 100644 index 0000000000..ec984971fc --- /dev/null +++ b/esp32p4/src/uart0/rx_filt.rs @@ -0,0 +1,85 @@ +#[doc = "Register `RX_FILT` reader"] +pub type R = crate::R; +#[doc = "Register `RX_FILT` writer"] +pub type W = crate::W; +#[doc = "Field `GLITCH_FILT` reader - when input pulse width is lower than this value the pulse is ignored."] +pub type GLITCH_FILT_R = crate::FieldReader; +#[doc = "Field `GLITCH_FILT` writer - when input pulse width is lower than this value the pulse is ignored."] +pub type GLITCH_FILT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GLITCH_FILT_EN` reader - Set this bit to enable Rx signal filter."] +pub type GLITCH_FILT_EN_R = crate::BitReader; +#[doc = "Field `GLITCH_FILT_EN` writer - Set this bit to enable Rx signal filter."] +pub type GLITCH_FILT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."] + #[inline(always)] + pub fn glitch_filt(&self) -> GLITCH_FILT_R { + GLITCH_FILT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - Set this bit to enable Rx signal filter."] + #[inline(always)] + pub fn glitch_filt_en(&self) -> GLITCH_FILT_EN_R { + GLITCH_FILT_EN_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_FILT") + .field( + "glitch_filt", + &format_args!("{}", self.glitch_filt().bits()), + ) + .field( + "glitch_filt_en", + &format_args!("{}", self.glitch_filt_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."] + #[inline(always)] + #[must_use] + pub fn glitch_filt(&mut self) -> GLITCH_FILT_W { + GLITCH_FILT_W::new(self, 0) + } + #[doc = "Bit 8 - Set this bit to enable Rx signal filter."] + #[inline(always)] + #[must_use] + pub fn glitch_filt_en(&mut self) -> GLITCH_FILT_EN_W { + GLITCH_FILT_EN_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Rx Filter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_filt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_filt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_FILT_SPEC; +impl crate::RegisterSpec for RX_FILT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_filt::R`](R) reader structure"] +impl crate::Readable for RX_FILT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rx_filt::W`](W) writer structure"] +impl crate::Writable for RX_FILT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RX_FILT to value 0x08"] +impl crate::Resettable for RX_FILT_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/uart0/rxd_cnt.rs b/esp32p4/src/uart0/rxd_cnt.rs new file mode 100644 index 0000000000..fa91511233 --- /dev/null +++ b/esp32p4/src/uart0/rxd_cnt.rs @@ -0,0 +1,39 @@ +#[doc = "Register `RXD_CNT` reader"] +pub type R = crate::R; +#[doc = "Field `RXD_EDGE_CNT` reader - This register stores the count of rxd edge change. It is used in baud rate-detect process."] +pub type RXD_EDGE_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - This register stores the count of rxd edge change. It is used in baud rate-detect process."] + #[inline(always)] + pub fn rxd_edge_cnt(&self) -> RXD_EDGE_CNT_R { + RXD_EDGE_CNT_R::new((self.bits & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RXD_CNT") + .field( + "rxd_edge_cnt", + &format_args!("{}", self.rxd_edge_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Autobaud edge change count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RXD_CNT_SPEC; +impl crate::RegisterSpec for RXD_CNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxd_cnt::R`](R) reader structure"] +impl crate::Readable for RXD_CNT_SPEC {} +#[doc = "`reset()` method sets RXD_CNT to value 0"] +impl crate::Resettable for RXD_CNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/sleep_conf0.rs b/esp32p4/src/uart0/sleep_conf0.rs new file mode 100644 index 0000000000..e867f2b351 --- /dev/null +++ b/esp32p4/src/uart0/sleep_conf0.rs @@ -0,0 +1,111 @@ +#[doc = "Register `SLEEP_CONF0` reader"] +pub type R = crate::R; +#[doc = "Register `SLEEP_CONF0` writer"] +pub type W = crate::W; +#[doc = "Field `WK_CHAR1` reader - This register restores the specified wake up char1 to wake up"] +pub type WK_CHAR1_R = crate::FieldReader; +#[doc = "Field `WK_CHAR1` writer - This register restores the specified wake up char1 to wake up"] +pub type WK_CHAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WK_CHAR2` reader - This register restores the specified wake up char2 to wake up"] +pub type WK_CHAR2_R = crate::FieldReader; +#[doc = "Field `WK_CHAR2` writer - This register restores the specified wake up char2 to wake up"] +pub type WK_CHAR2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WK_CHAR3` reader - This register restores the specified wake up char3 to wake up"] +pub type WK_CHAR3_R = crate::FieldReader; +#[doc = "Field `WK_CHAR3` writer - This register restores the specified wake up char3 to wake up"] +pub type WK_CHAR3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WK_CHAR4` reader - This register restores the specified wake up char4 to wake up"] +pub type WK_CHAR4_R = crate::FieldReader; +#[doc = "Field `WK_CHAR4` writer - This register restores the specified wake up char4 to wake up"] +pub type WK_CHAR4_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This register restores the specified wake up char1 to wake up"] + #[inline(always)] + pub fn wk_char1(&self) -> WK_CHAR1_R { + WK_CHAR1_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - This register restores the specified wake up char2 to wake up"] + #[inline(always)] + pub fn wk_char2(&self) -> WK_CHAR2_R { + WK_CHAR2_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - This register restores the specified wake up char3 to wake up"] + #[inline(always)] + pub fn wk_char3(&self) -> WK_CHAR3_R { + WK_CHAR3_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - This register restores the specified wake up char4 to wake up"] + #[inline(always)] + pub fn wk_char4(&self) -> WK_CHAR4_R { + WK_CHAR4_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLEEP_CONF0") + .field("wk_char1", &format_args!("{}", self.wk_char1().bits())) + .field("wk_char2", &format_args!("{}", self.wk_char2().bits())) + .field("wk_char3", &format_args!("{}", self.wk_char3().bits())) + .field("wk_char4", &format_args!("{}", self.wk_char4().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register restores the specified wake up char1 to wake up"] + #[inline(always)] + #[must_use] + pub fn wk_char1(&mut self) -> WK_CHAR1_W { + WK_CHAR1_W::new(self, 0) + } + #[doc = "Bits 8:15 - This register restores the specified wake up char2 to wake up"] + #[inline(always)] + #[must_use] + pub fn wk_char2(&mut self) -> WK_CHAR2_W { + WK_CHAR2_W::new(self, 8) + } + #[doc = "Bits 16:23 - This register restores the specified wake up char3 to wake up"] + #[inline(always)] + #[must_use] + pub fn wk_char3(&mut self) -> WK_CHAR3_W { + WK_CHAR3_W::new(self, 16) + } + #[doc = "Bits 24:31 - This register restores the specified wake up char4 to wake up"] + #[inline(always)] + #[must_use] + pub fn wk_char4(&mut self) -> WK_CHAR4_W { + WK_CHAR4_W::new(self, 24) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART sleep configure register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLEEP_CONF0_SPEC; +impl crate::RegisterSpec for SLEEP_CONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sleep_conf0::R`](R) reader structure"] +impl crate::Readable for SLEEP_CONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sleep_conf0::W`](W) writer structure"] +impl crate::Writable for SLEEP_CONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLEEP_CONF0 to value 0"] +impl crate::Resettable for SLEEP_CONF0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/sleep_conf1.rs b/esp32p4/src/uart0/sleep_conf1.rs new file mode 100644 index 0000000000..27d56da2c5 --- /dev/null +++ b/esp32p4/src/uart0/sleep_conf1.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SLEEP_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `SLEEP_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `WK_CHAR0` reader - This register restores the specified char0 to wake up"] +pub type WK_CHAR0_R = crate::FieldReader; +#[doc = "Field `WK_CHAR0` writer - This register restores the specified char0 to wake up"] +pub type WK_CHAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This register restores the specified char0 to wake up"] + #[inline(always)] + pub fn wk_char0(&self) -> WK_CHAR0_R { + WK_CHAR0_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLEEP_CONF1") + .field("wk_char0", &format_args!("{}", self.wk_char0().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register restores the specified char0 to wake up"] + #[inline(always)] + #[must_use] + pub fn wk_char0(&mut self) -> WK_CHAR0_W { + WK_CHAR0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART sleep configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLEEP_CONF1_SPEC; +impl crate::RegisterSpec for SLEEP_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sleep_conf1::R`](R) reader structure"] +impl crate::Readable for SLEEP_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sleep_conf1::W`](W) writer structure"] +impl crate::Writable for SLEEP_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLEEP_CONF1 to value 0"] +impl crate::Resettable for SLEEP_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uart0/sleep_conf2.rs b/esp32p4/src/uart0/sleep_conf2.rs new file mode 100644 index 0000000000..77c396b371 --- /dev/null +++ b/esp32p4/src/uart0/sleep_conf2.rs @@ -0,0 +1,142 @@ +#[doc = "Register `SLEEP_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `SLEEP_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `ACTIVE_THRESHOLD` reader - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."] +pub type ACTIVE_THRESHOLD_R = crate::FieldReader; +#[doc = "Field `ACTIVE_THRESHOLD` writer - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."] +pub type ACTIVE_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `RX_WAKE_UP_THRHD` reader - In wake up mode 1 this field is used to set the received data number threshold to wake up chip."] +pub type RX_WAKE_UP_THRHD_R = crate::FieldReader; +#[doc = "Field `RX_WAKE_UP_THRHD` writer - In wake up mode 1 this field is used to set the received data number threshold to wake up chip."] +pub type RX_WAKE_UP_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WK_CHAR_NUM` reader - This register is used to select number of wake up char."] +pub type WK_CHAR_NUM_R = crate::FieldReader; +#[doc = "Field `WK_CHAR_NUM` writer - This register is used to select number of wake up char."] +pub type WK_CHAR_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WK_CHAR_MASK` reader - This register is used to mask wake up char."] +pub type WK_CHAR_MASK_R = crate::FieldReader; +#[doc = "Field `WK_CHAR_MASK` writer - This register is used to mask wake up char."] +pub type WK_CHAR_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `WK_MODE_SEL` reader - This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than"] +pub type WK_MODE_SEL_R = crate::FieldReader; +#[doc = "Field `WK_MODE_SEL` writer - This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than"] +pub type WK_MODE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."] + #[inline(always)] + pub fn active_threshold(&self) -> ACTIVE_THRESHOLD_R { + ACTIVE_THRESHOLD_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:17 - In wake up mode 1 this field is used to set the received data number threshold to wake up chip."] + #[inline(always)] + pub fn rx_wake_up_thrhd(&self) -> RX_WAKE_UP_THRHD_R { + RX_WAKE_UP_THRHD_R::new(((self.bits >> 10) & 0xff) as u8) + } + #[doc = "Bits 18:20 - This register is used to select number of wake up char."] + #[inline(always)] + pub fn wk_char_num(&self) -> WK_CHAR_NUM_R { + WK_CHAR_NUM_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 21:25 - This register is used to mask wake up char."] + #[inline(always)] + pub fn wk_char_mask(&self) -> WK_CHAR_MASK_R { + WK_CHAR_MASK_R::new(((self.bits >> 21) & 0x1f) as u8) + } + #[doc = "Bits 26:27 - This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than"] + #[inline(always)] + pub fn wk_mode_sel(&self) -> WK_MODE_SEL_R { + WK_MODE_SEL_R::new(((self.bits >> 26) & 3) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLEEP_CONF2") + .field( + "active_threshold", + &format_args!("{}", self.active_threshold().bits()), + ) + .field( + "rx_wake_up_thrhd", + &format_args!("{}", self.rx_wake_up_thrhd().bits()), + ) + .field( + "wk_char_num", + &format_args!("{}", self.wk_char_num().bits()), + ) + .field( + "wk_char_mask", + &format_args!("{}", self.wk_char_mask().bits()), + ) + .field( + "wk_mode_sel", + &format_args!("{}", self.wk_mode_sel().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."] + #[inline(always)] + #[must_use] + pub fn active_threshold(&mut self) -> ACTIVE_THRESHOLD_W { + ACTIVE_THRESHOLD_W::new(self, 0) + } + #[doc = "Bits 10:17 - In wake up mode 1 this field is used to set the received data number threshold to wake up chip."] + #[inline(always)] + #[must_use] + pub fn rx_wake_up_thrhd(&mut self) -> RX_WAKE_UP_THRHD_W { + RX_WAKE_UP_THRHD_W::new(self, 10) + } + #[doc = "Bits 18:20 - This register is used to select number of wake up char."] + #[inline(always)] + #[must_use] + pub fn wk_char_num(&mut self) -> WK_CHAR_NUM_W { + WK_CHAR_NUM_W::new(self, 18) + } + #[doc = "Bits 21:25 - This register is used to mask wake up char."] + #[inline(always)] + #[must_use] + pub fn wk_char_mask(&mut self) -> WK_CHAR_MASK_W { + WK_CHAR_MASK_W::new(self, 21) + } + #[doc = "Bits 26:27 - This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than"] + #[inline(always)] + #[must_use] + pub fn wk_mode_sel(&mut self) -> WK_MODE_SEL_W { + WK_MODE_SEL_W::new(self, 26) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART sleep configure register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sleep_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sleep_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLEEP_CONF2_SPEC; +impl crate::RegisterSpec for SLEEP_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sleep_conf2::R`](R) reader structure"] +impl crate::Readable for SLEEP_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sleep_conf2::W`](W) writer structure"] +impl crate::Writable for SLEEP_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLEEP_CONF2 to value 0x0014_04f0"] +impl crate::Resettable for SLEEP_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0x0014_04f0; +} diff --git a/esp32p4/src/uart0/status.rs b/esp32p4/src/uart0/status.rs new file mode 100644 index 0000000000..16267e2ba7 --- /dev/null +++ b/esp32p4/src/uart0/status.rs @@ -0,0 +1,92 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `RXFIFO_CNT` reader - Stores the byte number of valid data in Rx-FIFO."] +pub type RXFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `DSRN` reader - The register represent the level value of the internal uart dsr signal."] +pub type DSRN_R = crate::BitReader; +#[doc = "Field `CTSN` reader - This register represent the level value of the internal uart cts signal."] +pub type CTSN_R = crate::BitReader; +#[doc = "Field `RXD` reader - This register represent the level value of the internal uart rxd signal."] +pub type RXD_R = crate::BitReader; +#[doc = "Field `TXFIFO_CNT` reader - Stores the byte number of data in Tx-FIFO."] +pub type TXFIFO_CNT_R = crate::FieldReader; +#[doc = "Field `DTRN` reader - This bit represents the level of the internal uart dtr signal."] +pub type DTRN_R = crate::BitReader; +#[doc = "Field `RTSN` reader - This bit represents the level of the internal uart rts signal."] +pub type RTSN_R = crate::BitReader; +#[doc = "Field `TXD` reader - This bit represents the level of the internal uart txd signal."] +pub type TXD_R = crate::BitReader; +impl R { + #[doc = "Bits 0:7 - Stores the byte number of valid data in Rx-FIFO."] + #[inline(always)] + pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R { + RXFIFO_CNT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 13 - The register represent the level value of the internal uart dsr signal."] + #[inline(always)] + pub fn dsrn(&self) -> DSRN_R { + DSRN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - This register represent the level value of the internal uart cts signal."] + #[inline(always)] + pub fn ctsn(&self) -> CTSN_R { + CTSN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - This register represent the level value of the internal uart rxd signal."] + #[inline(always)] + pub fn rxd(&self) -> RXD_R { + RXD_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:23 - Stores the byte number of data in Tx-FIFO."] + #[inline(always)] + pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R { + TXFIFO_CNT_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bit 29 - This bit represents the level of the internal uart dtr signal."] + #[inline(always)] + pub fn dtrn(&self) -> DTRN_R { + DTRN_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - This bit represents the level of the internal uart rts signal."] + #[inline(always)] + pub fn rtsn(&self) -> RTSN_R { + RTSN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - This bit represents the level of the internal uart txd signal."] + #[inline(always)] + pub fn txd(&self) -> TXD_R { + TXD_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATUS") + .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits())) + .field("dsrn", &format_args!("{}", self.dsrn().bit())) + .field("ctsn", &format_args!("{}", self.ctsn().bit())) + .field("rxd", &format_args!("{}", self.rxd().bit())) + .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits())) + .field("dtrn", &format_args!("{}", self.dtrn().bit())) + .field("rtsn", &format_args!("{}", self.rtsn().bit())) + .field("txd", &format_args!("{}", self.txd().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`reset()` method sets STATUS to value 0xe000_c000"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0xe000_c000; +} diff --git a/esp32p4/src/uart0/swfc_conf0_sync.rs b/esp32p4/src/uart0/swfc_conf0_sync.rs new file mode 100644 index 0000000000..60cada4167 --- /dev/null +++ b/esp32p4/src/uart0/swfc_conf0_sync.rs @@ -0,0 +1,197 @@ +#[doc = "Register `SWFC_CONF0_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `SWFC_CONF0_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `XON_CHAR` reader - This register stores the Xon flow control char."] +pub type XON_CHAR_R = crate::FieldReader; +#[doc = "Field `XON_CHAR` writer - This register stores the Xon flow control char."] +pub type XON_CHAR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `XOFF_CHAR` reader - This register stores the Xoff flow control char."] +pub type XOFF_CHAR_R = crate::FieldReader; +#[doc = "Field `XOFF_CHAR` writer - This register stores the Xoff flow control char."] +pub type XOFF_CHAR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `XON_XOFF_STILL_SEND` reader - In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled."] +pub type XON_XOFF_STILL_SEND_R = crate::BitReader; +#[doc = "Field `XON_XOFF_STILL_SEND` writer - In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled."] +pub type XON_XOFF_STILL_SEND_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_FLOW_CON_EN` reader - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."] +pub type SW_FLOW_CON_EN_R = crate::BitReader; +#[doc = "Field `SW_FLOW_CON_EN` writer - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."] +pub type SW_FLOW_CON_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XONOFF_DEL` reader - Set this bit to remove flow control char from the received data."] +pub type XONOFF_DEL_R = crate::BitReader; +#[doc = "Field `XONOFF_DEL` writer - Set this bit to remove flow control char from the received data."] +pub type XONOFF_DEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_XON` reader - Set this bit to enable the transmitter to go on sending data."] +pub type FORCE_XON_R = crate::BitReader; +#[doc = "Field `FORCE_XON` writer - Set this bit to enable the transmitter to go on sending data."] +pub type FORCE_XON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_XOFF` reader - Set this bit to stop the transmitter from sending data."] +pub type FORCE_XOFF_R = crate::BitReader; +#[doc = "Field `FORCE_XOFF` writer - Set this bit to stop the transmitter from sending data."] +pub type FORCE_XOFF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_XON` reader - Set this bit to send Xon char. It is cleared by hardware automatically."] +pub type SEND_XON_R = crate::BitReader; +#[doc = "Field `SEND_XON` writer - Set this bit to send Xon char. It is cleared by hardware automatically."] +pub type SEND_XON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_XOFF` reader - Set this bit to send Xoff char. It is cleared by hardware automatically."] +pub type SEND_XOFF_R = crate::BitReader; +#[doc = "Field `SEND_XOFF` writer - Set this bit to send Xoff char. It is cleared by hardware automatically."] +pub type SEND_XOFF_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - This register stores the Xon flow control char."] + #[inline(always)] + pub fn xon_char(&self) -> XON_CHAR_R { + XON_CHAR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - This register stores the Xoff flow control char."] + #[inline(always)] + pub fn xoff_char(&self) -> XOFF_CHAR_R { + XOFF_CHAR_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 16 - In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled."] + #[inline(always)] + pub fn xon_xoff_still_send(&self) -> XON_XOFF_STILL_SEND_R { + XON_XOFF_STILL_SEND_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."] + #[inline(always)] + pub fn sw_flow_con_en(&self) -> SW_FLOW_CON_EN_R { + SW_FLOW_CON_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Set this bit to remove flow control char from the received data."] + #[inline(always)] + pub fn xonoff_del(&self) -> XONOFF_DEL_R { + XONOFF_DEL_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Set this bit to enable the transmitter to go on sending data."] + #[inline(always)] + pub fn force_xon(&self) -> FORCE_XON_R { + FORCE_XON_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Set this bit to stop the transmitter from sending data."] + #[inline(always)] + pub fn force_xoff(&self) -> FORCE_XOFF_R { + FORCE_XOFF_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Set this bit to send Xon char. It is cleared by hardware automatically."] + #[inline(always)] + pub fn send_xon(&self) -> SEND_XON_R { + SEND_XON_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Set this bit to send Xoff char. It is cleared by hardware automatically."] + #[inline(always)] + pub fn send_xoff(&self) -> SEND_XOFF_R { + SEND_XOFF_R::new(((self.bits >> 22) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SWFC_CONF0_SYNC") + .field("xon_char", &format_args!("{}", self.xon_char().bits())) + .field("xoff_char", &format_args!("{}", self.xoff_char().bits())) + .field( + "xon_xoff_still_send", + &format_args!("{}", self.xon_xoff_still_send().bit()), + ) + .field( + "sw_flow_con_en", + &format_args!("{}", self.sw_flow_con_en().bit()), + ) + .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit())) + .field("force_xon", &format_args!("{}", self.force_xon().bit())) + .field("force_xoff", &format_args!("{}", self.force_xoff().bit())) + .field("send_xon", &format_args!("{}", self.send_xon().bit())) + .field("send_xoff", &format_args!("{}", self.send_xoff().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register stores the Xon flow control char."] + #[inline(always)] + #[must_use] + pub fn xon_char(&mut self) -> XON_CHAR_W { + XON_CHAR_W::new(self, 0) + } + #[doc = "Bits 8:15 - This register stores the Xoff flow control char."] + #[inline(always)] + #[must_use] + pub fn xoff_char(&mut self) -> XOFF_CHAR_W { + XOFF_CHAR_W::new(self, 8) + } + #[doc = "Bit 16 - In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled."] + #[inline(always)] + #[must_use] + pub fn xon_xoff_still_send(&mut self) -> XON_XOFF_STILL_SEND_W { + XON_XOFF_STILL_SEND_W::new(self, 16) + } + #[doc = "Bit 17 - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."] + #[inline(always)] + #[must_use] + pub fn sw_flow_con_en(&mut self) -> SW_FLOW_CON_EN_W { + SW_FLOW_CON_EN_W::new(self, 17) + } + #[doc = "Bit 18 - Set this bit to remove flow control char from the received data."] + #[inline(always)] + #[must_use] + pub fn xonoff_del(&mut self) -> XONOFF_DEL_W { + XONOFF_DEL_W::new(self, 18) + } + #[doc = "Bit 19 - Set this bit to enable the transmitter to go on sending data."] + #[inline(always)] + #[must_use] + pub fn force_xon(&mut self) -> FORCE_XON_W { + FORCE_XON_W::new(self, 19) + } + #[doc = "Bit 20 - Set this bit to stop the transmitter from sending data."] + #[inline(always)] + #[must_use] + pub fn force_xoff(&mut self) -> FORCE_XOFF_W { + FORCE_XOFF_W::new(self, 20) + } + #[doc = "Bit 21 - Set this bit to send Xon char. It is cleared by hardware automatically."] + #[inline(always)] + #[must_use] + pub fn send_xon(&mut self) -> SEND_XON_W { + SEND_XON_W::new(self, 21) + } + #[doc = "Bit 22 - Set this bit to send Xoff char. It is cleared by hardware automatically."] + #[inline(always)] + #[must_use] + pub fn send_xoff(&mut self) -> SEND_XOFF_W { + SEND_XOFF_W::new(self, 22) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Software flow-control character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swfc_conf0_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swfc_conf0_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SWFC_CONF0_SYNC_SPEC; +impl crate::RegisterSpec for SWFC_CONF0_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`swfc_conf0_sync::R`](R) reader structure"] +impl crate::Readable for SWFC_CONF0_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`swfc_conf0_sync::W`](W) writer structure"] +impl crate::Writable for SWFC_CONF0_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SWFC_CONF0_SYNC to value 0x1311"] +impl crate::Resettable for SWFC_CONF0_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x1311; +} diff --git a/esp32p4/src/uart0/swfc_conf1.rs b/esp32p4/src/uart0/swfc_conf1.rs new file mode 100644 index 0000000000..9e90005bf6 --- /dev/null +++ b/esp32p4/src/uart0/swfc_conf1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `SWFC_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `SWFC_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `XON_THRESHOLD` reader - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."] +pub type XON_THRESHOLD_R = crate::FieldReader; +#[doc = "Field `XON_THRESHOLD` writer - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."] +pub type XON_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `XOFF_THRESHOLD` reader - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char."] +pub type XOFF_THRESHOLD_R = crate::FieldReader; +#[doc = "Field `XOFF_THRESHOLD` writer - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char."] +pub type XOFF_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."] + #[inline(always)] + pub fn xon_threshold(&self) -> XON_THRESHOLD_R { + XON_THRESHOLD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char."] + #[inline(always)] + pub fn xoff_threshold(&self) -> XOFF_THRESHOLD_R { + XOFF_THRESHOLD_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SWFC_CONF1") + .field( + "xon_threshold", + &format_args!("{}", self.xon_threshold().bits()), + ) + .field( + "xoff_threshold", + &format_args!("{}", self.xoff_threshold().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."] + #[inline(always)] + #[must_use] + pub fn xon_threshold(&mut self) -> XON_THRESHOLD_W { + XON_THRESHOLD_W::new(self, 0) + } + #[doc = "Bits 8:15 - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char."] + #[inline(always)] + #[must_use] + pub fn xoff_threshold(&mut self) -> XOFF_THRESHOLD_W { + XOFF_THRESHOLD_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Software flow-control character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swfc_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swfc_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SWFC_CONF1_SPEC; +impl crate::RegisterSpec for SWFC_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`swfc_conf1::R`](R) reader structure"] +impl crate::Readable for SWFC_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`swfc_conf1::W`](W) writer structure"] +impl crate::Writable for SWFC_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SWFC_CONF1 to value 0xe000"] +impl crate::Resettable for SWFC_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0xe000; +} diff --git a/esp32p4/src/uart0/tout_conf_sync.rs b/esp32p4/src/uart0/tout_conf_sync.rs new file mode 100644 index 0000000000..f182983145 --- /dev/null +++ b/esp32p4/src/uart0/tout_conf_sync.rs @@ -0,0 +1,101 @@ +#[doc = "Register `TOUT_CONF_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `TOUT_CONF_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `RX_TOUT_EN` reader - This is the enble bit for uart receiver's timeout function."] +pub type RX_TOUT_EN_R = crate::BitReader; +#[doc = "Field `RX_TOUT_EN` writer - This is the enble bit for uart receiver's timeout function."] +pub type RX_TOUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TOUT_FLOW_DIS` reader - Set this bit to stop accumulating idle_cnt when hardware flow control works."] +pub type RX_TOUT_FLOW_DIS_R = crate::BitReader; +#[doc = "Field `RX_TOUT_FLOW_DIS` writer - Set this bit to stop accumulating idle_cnt when hardware flow control works."] +pub type RX_TOUT_FLOW_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_TOUT_THRHD` reader - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."] +pub type RX_TOUT_THRHD_R = crate::FieldReader; +#[doc = "Field `RX_TOUT_THRHD` writer - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."] +pub type RX_TOUT_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bit 0 - This is the enble bit for uart receiver's timeout function."] + #[inline(always)] + pub fn rx_tout_en(&self) -> RX_TOUT_EN_R { + RX_TOUT_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to stop accumulating idle_cnt when hardware flow control works."] + #[inline(always)] + pub fn rx_tout_flow_dis(&self) -> RX_TOUT_FLOW_DIS_R { + RX_TOUT_FLOW_DIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:11 - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."] + #[inline(always)] + pub fn rx_tout_thrhd(&self) -> RX_TOUT_THRHD_R { + RX_TOUT_THRHD_R::new(((self.bits >> 2) & 0x03ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TOUT_CONF_SYNC") + .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit())) + .field( + "rx_tout_flow_dis", + &format_args!("{}", self.rx_tout_flow_dis().bit()), + ) + .field( + "rx_tout_thrhd", + &format_args!("{}", self.rx_tout_thrhd().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This is the enble bit for uart receiver's timeout function."] + #[inline(always)] + #[must_use] + pub fn rx_tout_en(&mut self) -> RX_TOUT_EN_W { + RX_TOUT_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to stop accumulating idle_cnt when hardware flow control works."] + #[inline(always)] + #[must_use] + pub fn rx_tout_flow_dis(&mut self) -> RX_TOUT_FLOW_DIS_W { + RX_TOUT_FLOW_DIS_W::new(self, 1) + } + #[doc = "Bits 2:11 - This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1."] + #[inline(always)] + #[must_use] + pub fn rx_tout_thrhd(&mut self) -> RX_TOUT_THRHD_W { + RX_TOUT_THRHD_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UART threshold and allocation configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tout_conf_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tout_conf_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TOUT_CONF_SYNC_SPEC; +impl crate::RegisterSpec for TOUT_CONF_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tout_conf_sync::R`](R) reader structure"] +impl crate::Readable for TOUT_CONF_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tout_conf_sync::W`](W) writer structure"] +impl crate::Writable for TOUT_CONF_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TOUT_CONF_SYNC to value 0x28"] +impl crate::Resettable for TOUT_CONF_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x28; +} diff --git a/esp32p4/src/uart0/txbrk_conf_sync.rs b/esp32p4/src/uart0/txbrk_conf_sync.rs new file mode 100644 index 0000000000..8589787271 --- /dev/null +++ b/esp32p4/src/uart0/txbrk_conf_sync.rs @@ -0,0 +1,63 @@ +#[doc = "Register `TXBRK_CONF_SYNC` reader"] +pub type R = crate::R; +#[doc = "Register `TXBRK_CONF_SYNC` writer"] +pub type W = crate::W; +#[doc = "Field `TX_BRK_NUM` reader - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."] +pub type TX_BRK_NUM_R = crate::FieldReader; +#[doc = "Field `TX_BRK_NUM` writer - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."] +pub type TX_BRK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."] + #[inline(always)] + pub fn tx_brk_num(&self) -> TX_BRK_NUM_R { + TX_BRK_NUM_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TXBRK_CONF_SYNC") + .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."] + #[inline(always)] + #[must_use] + pub fn tx_brk_num(&mut self) -> TX_BRK_NUM_W { + TX_BRK_NUM_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Tx Break character configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbrk_conf_sync::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbrk_conf_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TXBRK_CONF_SYNC_SPEC; +impl crate::RegisterSpec for TXBRK_CONF_SYNC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`txbrk_conf_sync::R`](R) reader structure"] +impl crate::Readable for TXBRK_CONF_SYNC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txbrk_conf_sync::W`](W) writer structure"] +impl crate::Writable for TXBRK_CONF_SYNC_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TXBRK_CONF_SYNC to value 0x0a"] +impl crate::Resettable for TXBRK_CONF_SYNC_SPEC { + const RESET_VALUE: Self::Ux = 0x0a; +} diff --git a/esp32p4/src/uhci0.rs b/esp32p4/src/uhci0.rs new file mode 100644 index 0000000000..a018256d0f --- /dev/null +++ b/esp32p4/src/uhci0.rs @@ -0,0 +1,337 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + conf0: CONF0, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + conf1: CONF1, + state0: STATE0, + state1: STATE1, + escape_conf: ESCAPE_CONF, + hung_conf: HUNG_CONF, + ack_num: ACK_NUM, + rx_head: RX_HEAD, + quick_sent: QUICK_SENT, + reg_q0_word0: REG_Q0_WORD0, + reg_q0_word1: REG_Q0_WORD1, + reg_q1_word0: REG_Q1_WORD0, + reg_q1_word1: REG_Q1_WORD1, + reg_q2_word0: REG_Q2_WORD0, + reg_q2_word1: REG_Q2_WORD1, + reg_q3_word0: REG_Q3_WORD0, + reg_q3_word1: REG_Q3_WORD1, + reg_q4_word0: REG_Q4_WORD0, + reg_q4_word1: REG_Q4_WORD1, + reg_q5_word0: REG_Q5_WORD0, + reg_q5_word1: REG_Q5_WORD1, + reg_q6_word0: REG_Q6_WORD0, + reg_q6_word1: REG_Q6_WORD1, + esc_conf0: ESC_CONF0, + esc_conf1: ESC_CONF1, + esc_conf2: ESC_CONF2, + esc_conf3: ESC_CONF3, + pkt_thres: PKT_THRES, + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - UHCI Configuration Register0"] + #[inline(always)] + pub const fn conf0(&self) -> &CONF0 { + &self.conf0 + } + #[doc = "0x04 - UHCI Interrupt Raw Register"] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x08 - UHCI Interrupt Status Register"] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x0c - UHCI Interrupt Enable Register"] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x10 - UHCI Interrupt Clear Register"] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x14 - UHCI Configuration Register1"] + #[inline(always)] + pub const fn conf1(&self) -> &CONF1 { + &self.conf1 + } + #[doc = "0x18 - UHCI Receive Status Register"] + #[inline(always)] + pub const fn state0(&self) -> &STATE0 { + &self.state0 + } + #[doc = "0x1c - UHCI Transmit Status Register"] + #[inline(always)] + pub const fn state1(&self) -> &STATE1 { + &self.state1 + } + #[doc = "0x20 - UHCI Escapes Configuration Register0"] + #[inline(always)] + pub const fn escape_conf(&self) -> &ESCAPE_CONF { + &self.escape_conf + } + #[doc = "0x24 - UHCI Hung Configuration Register0"] + #[inline(always)] + pub const fn hung_conf(&self) -> &HUNG_CONF { + &self.hung_conf + } + #[doc = "0x28 - UHCI Ack Value Configuration Register0"] + #[inline(always)] + pub const fn ack_num(&self) -> &ACK_NUM { + &self.ack_num + } + #[doc = "0x2c - UHCI Head Register"] + #[inline(always)] + pub const fn rx_head(&self) -> &RX_HEAD { + &self.rx_head + } + #[doc = "0x30 - UCHI Quick send Register"] + #[inline(always)] + pub const fn quick_sent(&self) -> &QUICK_SENT { + &self.quick_sent + } + #[doc = "0x34 - UHCI Q0_WORD0 Quick Send Register"] + #[inline(always)] + pub const fn reg_q0_word0(&self) -> ®_Q0_WORD0 { + &self.reg_q0_word0 + } + #[doc = "0x38 - UHCI Q0_WORD1 Quick Send Register"] + #[inline(always)] + pub const fn reg_q0_word1(&self) -> ®_Q0_WORD1 { + &self.reg_q0_word1 + } + #[doc = "0x3c - UHCI Q1_WORD0 Quick Send Register"] + #[inline(always)] + pub const fn reg_q1_word0(&self) -> ®_Q1_WORD0 { + &self.reg_q1_word0 + } + #[doc = "0x40 - UHCI Q1_WORD1 Quick Send Register"] + #[inline(always)] + pub const fn reg_q1_word1(&self) -> ®_Q1_WORD1 { + &self.reg_q1_word1 + } + #[doc = "0x44 - UHCI Q2_WORD0 Quick Send Register"] + #[inline(always)] + pub const fn reg_q2_word0(&self) -> ®_Q2_WORD0 { + &self.reg_q2_word0 + } + #[doc = "0x48 - UHCI Q2_WORD1 Quick Send Register"] + #[inline(always)] + pub const fn reg_q2_word1(&self) -> ®_Q2_WORD1 { + &self.reg_q2_word1 + } + #[doc = "0x4c - UHCI Q3_WORD0 Quick Send Register"] + #[inline(always)] + pub const fn reg_q3_word0(&self) -> ®_Q3_WORD0 { + &self.reg_q3_word0 + } + #[doc = "0x50 - UHCI Q3_WORD1 Quick Send Register"] + #[inline(always)] + pub const fn reg_q3_word1(&self) -> ®_Q3_WORD1 { + &self.reg_q3_word1 + } + #[doc = "0x54 - UHCI Q4_WORD0 Quick Send Register"] + #[inline(always)] + pub const fn reg_q4_word0(&self) -> ®_Q4_WORD0 { + &self.reg_q4_word0 + } + #[doc = "0x58 - UHCI Q4_WORD1 Quick Send Register"] + #[inline(always)] + pub const fn reg_q4_word1(&self) -> ®_Q4_WORD1 { + &self.reg_q4_word1 + } + #[doc = "0x5c - UHCI Q5_WORD0 Quick Send Register"] + #[inline(always)] + pub const fn reg_q5_word0(&self) -> ®_Q5_WORD0 { + &self.reg_q5_word0 + } + #[doc = "0x60 - UHCI Q5_WORD1 Quick Send Register"] + #[inline(always)] + pub const fn reg_q5_word1(&self) -> ®_Q5_WORD1 { + &self.reg_q5_word1 + } + #[doc = "0x64 - UHCI Q6_WORD0 Quick Send Register"] + #[inline(always)] + pub const fn reg_q6_word0(&self) -> ®_Q6_WORD0 { + &self.reg_q6_word0 + } + #[doc = "0x68 - UHCI Q6_WORD1 Quick Send Register"] + #[inline(always)] + pub const fn reg_q6_word1(&self) -> ®_Q6_WORD1 { + &self.reg_q6_word1 + } + #[doc = "0x6c - UHCI Escapes Sequence Configuration Register0"] + #[inline(always)] + pub const fn esc_conf0(&self) -> &ESC_CONF0 { + &self.esc_conf0 + } + #[doc = "0x70 - UHCI Escapes Sequence Configuration Register1"] + #[inline(always)] + pub const fn esc_conf1(&self) -> &ESC_CONF1 { + &self.esc_conf1 + } + #[doc = "0x74 - UHCI Escapes Sequence Configuration Register2"] + #[inline(always)] + pub const fn esc_conf2(&self) -> &ESC_CONF2 { + &self.esc_conf2 + } + #[doc = "0x78 - UHCI Escapes Sequence Configuration Register3"] + #[inline(always)] + pub const fn esc_conf3(&self) -> &ESC_CONF3 { + &self.esc_conf3 + } + #[doc = "0x7c - UCHI Packet Length Configuration Register"] + #[inline(always)] + pub const fn pkt_thres(&self) -> &PKT_THRES { + &self.pkt_thres + } + #[doc = "0x80 - UHCI Version Register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "CONF0 (rw) register accessor: UHCI Configuration Register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf0`] module"] +pub type CONF0 = crate::Reg; +#[doc = "UHCI Configuration Register0"] +pub mod conf0; +#[doc = "INT_RAW (rw) register accessor: UHCI Interrupt Raw Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "UHCI Interrupt Raw Register"] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: UHCI Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "UHCI Interrupt Status Register"] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: UHCI Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "UHCI Interrupt Enable Register"] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: UHCI Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "UHCI Interrupt Clear Register"] +pub mod int_clr; +#[doc = "CONF1 (rw) register accessor: UHCI Configuration Register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf1`] module"] +pub type CONF1 = crate::Reg; +#[doc = "UHCI Configuration Register1"] +pub mod conf1; +#[doc = "STATE0 (r) register accessor: UHCI Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state0`] module"] +pub type STATE0 = crate::Reg; +#[doc = "UHCI Receive Status Register"] +pub mod state0; +#[doc = "STATE1 (r) register accessor: UHCI Transmit Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state1`] module"] +pub type STATE1 = crate::Reg; +#[doc = "UHCI Transmit Status Register"] +pub mod state1; +#[doc = "ESCAPE_CONF (rw) register accessor: UHCI Escapes Configuration Register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`escape_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`escape_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@escape_conf`] module"] +pub type ESCAPE_CONF = crate::Reg; +#[doc = "UHCI Escapes Configuration Register0"] +pub mod escape_conf; +#[doc = "HUNG_CONF (rw) register accessor: UHCI Hung Configuration Register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hung_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hung_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hung_conf`] module"] +pub type HUNG_CONF = crate::Reg; +#[doc = "UHCI Hung Configuration Register0"] +pub mod hung_conf; +#[doc = "ACK_NUM (rw) register accessor: UHCI Ack Value Configuration Register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ack_num::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ack_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ack_num`] module"] +pub type ACK_NUM = crate::Reg; +#[doc = "UHCI Ack Value Configuration Register0"] +pub mod ack_num; +#[doc = "RX_HEAD (r) register accessor: UHCI Head Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_head::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_head`] module"] +pub type RX_HEAD = crate::Reg; +#[doc = "UHCI Head Register"] +pub mod rx_head; +#[doc = "QUICK_SENT (rw) register accessor: UCHI Quick send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`quick_sent::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`quick_sent::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@quick_sent`] module"] +pub type QUICK_SENT = crate::Reg; +#[doc = "UCHI Quick send Register"] +pub mod quick_sent; +#[doc = "REG_Q0_WORD0 (rw) register accessor: UHCI Q0_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q0_word0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q0_word0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q0_word0`] module"] +pub type REG_Q0_WORD0 = crate::Reg; +#[doc = "UHCI Q0_WORD0 Quick Send Register"] +pub mod reg_q0_word0; +#[doc = "REG_Q0_WORD1 (rw) register accessor: UHCI Q0_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q0_word1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q0_word1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q0_word1`] module"] +pub type REG_Q0_WORD1 = crate::Reg; +#[doc = "UHCI Q0_WORD1 Quick Send Register"] +pub mod reg_q0_word1; +#[doc = "REG_Q1_WORD0 (rw) register accessor: UHCI Q1_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q1_word0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q1_word0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q1_word0`] module"] +pub type REG_Q1_WORD0 = crate::Reg; +#[doc = "UHCI Q1_WORD0 Quick Send Register"] +pub mod reg_q1_word0; +#[doc = "REG_Q1_WORD1 (rw) register accessor: UHCI Q1_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q1_word1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q1_word1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q1_word1`] module"] +pub type REG_Q1_WORD1 = crate::Reg; +#[doc = "UHCI Q1_WORD1 Quick Send Register"] +pub mod reg_q1_word1; +#[doc = "REG_Q2_WORD0 (rw) register accessor: UHCI Q2_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q2_word0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q2_word0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q2_word0`] module"] +pub type REG_Q2_WORD0 = crate::Reg; +#[doc = "UHCI Q2_WORD0 Quick Send Register"] +pub mod reg_q2_word0; +#[doc = "REG_Q2_WORD1 (rw) register accessor: UHCI Q2_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q2_word1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q2_word1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q2_word1`] module"] +pub type REG_Q2_WORD1 = crate::Reg; +#[doc = "UHCI Q2_WORD1 Quick Send Register"] +pub mod reg_q2_word1; +#[doc = "REG_Q3_WORD0 (rw) register accessor: UHCI Q3_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q3_word0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q3_word0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q3_word0`] module"] +pub type REG_Q3_WORD0 = crate::Reg; +#[doc = "UHCI Q3_WORD0 Quick Send Register"] +pub mod reg_q3_word0; +#[doc = "REG_Q3_WORD1 (rw) register accessor: UHCI Q3_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q3_word1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q3_word1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q3_word1`] module"] +pub type REG_Q3_WORD1 = crate::Reg; +#[doc = "UHCI Q3_WORD1 Quick Send Register"] +pub mod reg_q3_word1; +#[doc = "REG_Q4_WORD0 (rw) register accessor: UHCI Q4_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q4_word0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q4_word0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q4_word0`] module"] +pub type REG_Q4_WORD0 = crate::Reg; +#[doc = "UHCI Q4_WORD0 Quick Send Register"] +pub mod reg_q4_word0; +#[doc = "REG_Q4_WORD1 (rw) register accessor: UHCI Q4_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q4_word1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q4_word1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q4_word1`] module"] +pub type REG_Q4_WORD1 = crate::Reg; +#[doc = "UHCI Q4_WORD1 Quick Send Register"] +pub mod reg_q4_word1; +#[doc = "REG_Q5_WORD0 (rw) register accessor: UHCI Q5_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q5_word0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q5_word0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q5_word0`] module"] +pub type REG_Q5_WORD0 = crate::Reg; +#[doc = "UHCI Q5_WORD0 Quick Send Register"] +pub mod reg_q5_word0; +#[doc = "REG_Q5_WORD1 (rw) register accessor: UHCI Q5_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q5_word1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q5_word1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q5_word1`] module"] +pub type REG_Q5_WORD1 = crate::Reg; +#[doc = "UHCI Q5_WORD1 Quick Send Register"] +pub mod reg_q5_word1; +#[doc = "REG_Q6_WORD0 (rw) register accessor: UHCI Q6_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q6_word0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q6_word0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q6_word0`] module"] +pub type REG_Q6_WORD0 = crate::Reg; +#[doc = "UHCI Q6_WORD0 Quick Send Register"] +pub mod reg_q6_word0; +#[doc = "REG_Q6_WORD1 (rw) register accessor: UHCI Q6_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q6_word1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q6_word1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_q6_word1`] module"] +pub type REG_Q6_WORD1 = crate::Reg; +#[doc = "UHCI Q6_WORD1 Quick Send Register"] +pub mod reg_q6_word1; +#[doc = "ESC_CONF0 (rw) register accessor: UHCI Escapes Sequence Configuration Register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esc_conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esc_conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esc_conf0`] module"] +pub type ESC_CONF0 = crate::Reg; +#[doc = "UHCI Escapes Sequence Configuration Register0"] +pub mod esc_conf0; +#[doc = "ESC_CONF1 (rw) register accessor: UHCI Escapes Sequence Configuration Register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esc_conf1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esc_conf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esc_conf1`] module"] +pub type ESC_CONF1 = crate::Reg; +#[doc = "UHCI Escapes Sequence Configuration Register1"] +pub mod esc_conf1; +#[doc = "ESC_CONF2 (rw) register accessor: UHCI Escapes Sequence Configuration Register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esc_conf2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esc_conf2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esc_conf2`] module"] +pub type ESC_CONF2 = crate::Reg; +#[doc = "UHCI Escapes Sequence Configuration Register2"] +pub mod esc_conf2; +#[doc = "ESC_CONF3 (rw) register accessor: UHCI Escapes Sequence Configuration Register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esc_conf3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esc_conf3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esc_conf3`] module"] +pub type ESC_CONF3 = crate::Reg; +#[doc = "UHCI Escapes Sequence Configuration Register3"] +pub mod esc_conf3; +#[doc = "PKT_THRES (rw) register accessor: UCHI Packet Length Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pkt_thres::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pkt_thres::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkt_thres`] module"] +pub type PKT_THRES = crate::Reg; +#[doc = "UCHI Packet Length Configuration Register"] +pub mod pkt_thres; +#[doc = "DATE (rw) register accessor: UHCI Version Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "UHCI Version Register"] +pub mod date; diff --git a/esp32p4/src/uhci0/ack_num.rs b/esp32p4/src/uhci0/ack_num.rs new file mode 100644 index 0000000000..27a3eb78af --- /dev/null +++ b/esp32p4/src/uhci0/ack_num.rs @@ -0,0 +1,71 @@ +#[doc = "Register `ACK_NUM` reader"] +pub type R = crate::R; +#[doc = "Register `ACK_NUM` writer"] +pub type W = crate::W; +#[doc = "Field `ACK_NUM` reader - Indicates the ACK number during software flow control."] +pub type ACK_NUM_R = crate::FieldReader; +#[doc = "Field `ACK_NUM` writer - Indicates the ACK number during software flow control."] +pub type ACK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LOAD` writer - Set this bit to load the ACK value of UHCI_ACK_NUM."] +pub type LOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - Indicates the ACK number during software flow control."] + #[inline(always)] + pub fn ack_num(&self) -> ACK_NUM_R { + ACK_NUM_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ACK_NUM") + .field("ack_num", &format_args!("{}", self.ack_num().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Indicates the ACK number during software flow control."] + #[inline(always)] + #[must_use] + pub fn ack_num(&mut self) -> ACK_NUM_W { + ACK_NUM_W::new(self, 0) + } + #[doc = "Bit 3 - Set this bit to load the ACK value of UHCI_ACK_NUM."] + #[inline(always)] + #[must_use] + pub fn load(&mut self) -> LOAD_W { + LOAD_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Ack Value Configuration Register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ack_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ack_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ACK_NUM_SPEC; +impl crate::RegisterSpec for ACK_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ack_num::R`](R) reader structure"] +impl crate::Readable for ACK_NUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ack_num::W`](W) writer structure"] +impl crate::Writable for ACK_NUM_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ACK_NUM to value 0"] +impl crate::Resettable for ACK_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/conf0.rs b/esp32p4/src/uhci0/conf0.rs new file mode 100644 index 0000000000..2fecccff9b --- /dev/null +++ b/esp32p4/src/uhci0/conf0.rs @@ -0,0 +1,232 @@ +#[doc = "Register `CONF0` reader"] +pub type R = crate::R; +#[doc = "Register `CONF0` writer"] +pub type W = crate::W; +#[doc = "Field `TX_RST` reader - Write 1 then write 0 to this bit to reset decode state machine."] +pub type TX_RST_R = crate::BitReader; +#[doc = "Field `TX_RST` writer - Write 1 then write 0 to this bit to reset decode state machine."] +pub type TX_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_RST` reader - Write 1 then write 0 to this bit to reset encode state machine."] +pub type RX_RST_R = crate::BitReader; +#[doc = "Field `RX_RST` writer - Write 1 then write 0 to this bit to reset encode state machine."] +pub type RX_RST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART_SEL` reader - Select which uart to connect with GDMA."] +pub type UART_SEL_R = crate::FieldReader; +#[doc = "Field `UART_SEL` writer - Select which uart to connect with GDMA."] +pub type UART_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SEPER_EN` reader - Set this bit to separate the data frame using a special char."] +pub type SEPER_EN_R = crate::BitReader; +#[doc = "Field `SEPER_EN` writer - Set this bit to separate the data frame using a special char."] +pub type SEPER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HEAD_EN` reader - Set this bit to encode the data packet with a formatting header."] +pub type HEAD_EN_R = crate::BitReader; +#[doc = "Field `HEAD_EN` writer - Set this bit to encode the data packet with a formatting header."] +pub type HEAD_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRC_REC_EN` reader - Set this bit to enable UHCI to receive the 16 bit CRC."] +pub type CRC_REC_EN_R = crate::BitReader; +#[doc = "Field `CRC_REC_EN` writer - Set this bit to enable UHCI to receive the 16 bit CRC."] +pub type CRC_REC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART_IDLE_EOF_EN` reader - If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state."] +pub type UART_IDLE_EOF_EN_R = crate::BitReader; +#[doc = "Field `UART_IDLE_EOF_EN` writer - If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state."] +pub type UART_IDLE_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LEN_EOF_EN` reader - If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received."] +pub type LEN_EOF_EN_R = crate::BitReader; +#[doc = "Field `LEN_EOF_EN` writer - If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received."] +pub type LEN_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENCODE_CRC_EN` reader - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."] +pub type ENCODE_CRC_EN_R = crate::BitReader; +#[doc = "Field `ENCODE_CRC_EN` writer - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."] +pub type ENCODE_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART_RX_BRK_EOF_EN` reader - If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART."] +pub type UART_RX_BRK_EOF_EN_R = crate::BitReader; +#[doc = "Field `UART_RX_BRK_EOF_EN` writer - If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART."] +pub type UART_RX_BRK_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 then write 0 to this bit to reset decode state machine."] + #[inline(always)] + pub fn tx_rst(&self) -> TX_RST_R { + TX_RST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 then write 0 to this bit to reset encode state machine."] + #[inline(always)] + pub fn rx_rst(&self) -> RX_RST_R { + RX_RST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - Select which uart to connect with GDMA."] + #[inline(always)] + pub fn uart_sel(&self) -> UART_SEL_R { + UART_SEL_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bit 5 - Set this bit to separate the data frame using a special char."] + #[inline(always)] + pub fn seper_en(&self) -> SEPER_EN_R { + SEPER_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set this bit to encode the data packet with a formatting header."] + #[inline(always)] + pub fn head_en(&self) -> HEAD_EN_R { + HEAD_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set this bit to enable UHCI to receive the 16 bit CRC."] + #[inline(always)] + pub fn crc_rec_en(&self) -> CRC_REC_EN_R { + CRC_REC_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state."] + #[inline(always)] + pub fn uart_idle_eof_en(&self) -> UART_IDLE_EOF_EN_R { + UART_IDLE_EOF_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received."] + #[inline(always)] + pub fn len_eof_en(&self) -> LEN_EOF_EN_R { + LEN_EOF_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."] + #[inline(always)] + pub fn encode_crc_en(&self) -> ENCODE_CRC_EN_R { + ENCODE_CRC_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART."] + #[inline(always)] + pub fn uart_rx_brk_eof_en(&self) -> UART_RX_BRK_EOF_EN_R { + UART_RX_BRK_EOF_EN_R::new(((self.bits >> 12) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF0") + .field("tx_rst", &format_args!("{}", self.tx_rst().bit())) + .field("rx_rst", &format_args!("{}", self.rx_rst().bit())) + .field("uart_sel", &format_args!("{}", self.uart_sel().bits())) + .field("seper_en", &format_args!("{}", self.seper_en().bit())) + .field("head_en", &format_args!("{}", self.head_en().bit())) + .field("crc_rec_en", &format_args!("{}", self.crc_rec_en().bit())) + .field( + "uart_idle_eof_en", + &format_args!("{}", self.uart_idle_eof_en().bit()), + ) + .field("len_eof_en", &format_args!("{}", self.len_eof_en().bit())) + .field( + "encode_crc_en", + &format_args!("{}", self.encode_crc_en().bit()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .field( + "uart_rx_brk_eof_en", + &format_args!("{}", self.uart_rx_brk_eof_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 then write 0 to this bit to reset decode state machine."] + #[inline(always)] + #[must_use] + pub fn tx_rst(&mut self) -> TX_RST_W { + TX_RST_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 then write 0 to this bit to reset encode state machine."] + #[inline(always)] + #[must_use] + pub fn rx_rst(&mut self) -> RX_RST_W { + RX_RST_W::new(self, 1) + } + #[doc = "Bits 2:4 - Select which uart to connect with GDMA."] + #[inline(always)] + #[must_use] + pub fn uart_sel(&mut self) -> UART_SEL_W { + UART_SEL_W::new(self, 2) + } + #[doc = "Bit 5 - Set this bit to separate the data frame using a special char."] + #[inline(always)] + #[must_use] + pub fn seper_en(&mut self) -> SEPER_EN_W { + SEPER_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to encode the data packet with a formatting header."] + #[inline(always)] + #[must_use] + pub fn head_en(&mut self) -> HEAD_EN_W { + HEAD_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to enable UHCI to receive the 16 bit CRC."] + #[inline(always)] + #[must_use] + pub fn crc_rec_en(&mut self) -> CRC_REC_EN_W { + CRC_REC_EN_W::new(self, 7) + } + #[doc = "Bit 8 - If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state."] + #[inline(always)] + #[must_use] + pub fn uart_idle_eof_en(&mut self) -> UART_IDLE_EOF_EN_W { + UART_IDLE_EOF_EN_W::new(self, 8) + } + #[doc = "Bit 9 - If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received."] + #[inline(always)] + #[must_use] + pub fn len_eof_en(&mut self) -> LEN_EOF_EN_W { + LEN_EOF_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."] + #[inline(always)] + #[must_use] + pub fn encode_crc_en(&mut self) -> ENCODE_CRC_EN_W { + ENCODE_CRC_EN_W::new(self, 10) + } + #[doc = "Bit 11 - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 11) + } + #[doc = "Bit 12 - If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART."] + #[inline(always)] + #[must_use] + pub fn uart_rx_brk_eof_en(&mut self) -> UART_RX_BRK_EOF_EN_W { + UART_RX_BRK_EOF_EN_W::new(self, 12) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Configuration Register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF0_SPEC; +impl crate::RegisterSpec for CONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf0::R`](R) reader structure"] +impl crate::Readable for CONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"] +impl crate::Writable for CONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF0 to value 0x06e0"] +impl crate::Resettable for CONF0_SPEC { + const RESET_VALUE: Self::Ux = 0x06e0; +} diff --git a/esp32p4/src/uhci0/conf1.rs b/esp32p4/src/uhci0/conf1.rs new file mode 100644 index 0000000000..a5d88757f3 --- /dev/null +++ b/esp32p4/src/uhci0/conf1.rs @@ -0,0 +1,182 @@ +#[doc = "Register `CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `CHECK_SUM_EN` reader - Set this bit to enable head checksum check when receiving."] +pub type CHECK_SUM_EN_R = crate::BitReader; +#[doc = "Field `CHECK_SUM_EN` writer - Set this bit to enable head checksum check when receiving."] +pub type CHECK_SUM_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHECK_SEQ_EN` reader - Set this bit to enable sequence number check when receiving."] +pub type CHECK_SEQ_EN_R = crate::BitReader; +#[doc = "Field `CHECK_SEQ_EN` writer - Set this bit to enable sequence number check when receiving."] +pub type CHECK_SEQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRC_DISABLE` reader - Set this bit to support CRC calculation, and data integrity check bit should 1."] +pub type CRC_DISABLE_R = crate::BitReader; +#[doc = "Field `CRC_DISABLE` writer - Set this bit to support CRC calculation, and data integrity check bit should 1."] +pub type CRC_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAVE_HEAD` reader - Set this bit to save data packet head when UHCI receive data."] +pub type SAVE_HEAD_R = crate::BitReader; +#[doc = "Field `SAVE_HEAD` writer - Set this bit to save data packet head when UHCI receive data."] +pub type SAVE_HEAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_CHECK_SUM_RE` reader - Set this bit to encode data packet with checksum."] +pub type TX_CHECK_SUM_RE_R = crate::BitReader; +#[doc = "Field `TX_CHECK_SUM_RE` writer - Set this bit to encode data packet with checksum."] +pub type TX_CHECK_SUM_RE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_ACK_NUM_RE` reader - Set this bit to encode data packet with ACK when reliable data packet is ready."] +pub type TX_ACK_NUM_RE_R = crate::BitReader; +#[doc = "Field `TX_ACK_NUM_RE` writer - Set this bit to encode data packet with ACK when reliable data packet is ready."] +pub type TX_ACK_NUM_RE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAIT_SW_START` reader - Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status."] +pub type WAIT_SW_START_R = crate::BitReader; +#[doc = "Field `WAIT_SW_START` writer - Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status."] +pub type WAIT_SW_START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SW_START` writer - Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT."] +pub type SW_START_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable head checksum check when receiving."] + #[inline(always)] + pub fn check_sum_en(&self) -> CHECK_SUM_EN_R { + CHECK_SUM_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to enable sequence number check when receiving."] + #[inline(always)] + pub fn check_seq_en(&self) -> CHECK_SEQ_EN_R { + CHECK_SEQ_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to support CRC calculation, and data integrity check bit should 1."] + #[inline(always)] + pub fn crc_disable(&self) -> CRC_DISABLE_R { + CRC_DISABLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to save data packet head when UHCI receive data."] + #[inline(always)] + pub fn save_head(&self) -> SAVE_HEAD_R { + SAVE_HEAD_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to encode data packet with checksum."] + #[inline(always)] + pub fn tx_check_sum_re(&self) -> TX_CHECK_SUM_RE_R { + TX_CHECK_SUM_RE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set this bit to encode data packet with ACK when reliable data packet is ready."] + #[inline(always)] + pub fn tx_ack_num_re(&self) -> TX_ACK_NUM_RE_R { + TX_ACK_NUM_RE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status."] + #[inline(always)] + pub fn wait_sw_start(&self) -> WAIT_SW_START_R { + WAIT_SW_START_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF1") + .field( + "check_sum_en", + &format_args!("{}", self.check_sum_en().bit()), + ) + .field( + "check_seq_en", + &format_args!("{}", self.check_seq_en().bit()), + ) + .field("crc_disable", &format_args!("{}", self.crc_disable().bit())) + .field("save_head", &format_args!("{}", self.save_head().bit())) + .field( + "tx_check_sum_re", + &format_args!("{}", self.tx_check_sum_re().bit()), + ) + .field( + "tx_ack_num_re", + &format_args!("{}", self.tx_ack_num_re().bit()), + ) + .field( + "wait_sw_start", + &format_args!("{}", self.wait_sw_start().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable head checksum check when receiving."] + #[inline(always)] + #[must_use] + pub fn check_sum_en(&mut self) -> CHECK_SUM_EN_W { + CHECK_SUM_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to enable sequence number check when receiving."] + #[inline(always)] + #[must_use] + pub fn check_seq_en(&mut self) -> CHECK_SEQ_EN_W { + CHECK_SEQ_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to support CRC calculation, and data integrity check bit should 1."] + #[inline(always)] + #[must_use] + pub fn crc_disable(&mut self) -> CRC_DISABLE_W { + CRC_DISABLE_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to save data packet head when UHCI receive data."] + #[inline(always)] + #[must_use] + pub fn save_head(&mut self) -> SAVE_HEAD_W { + SAVE_HEAD_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to encode data packet with checksum."] + #[inline(always)] + #[must_use] + pub fn tx_check_sum_re(&mut self) -> TX_CHECK_SUM_RE_W { + TX_CHECK_SUM_RE_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to encode data packet with ACK when reliable data packet is ready."] + #[inline(always)] + #[must_use] + pub fn tx_ack_num_re(&mut self) -> TX_ACK_NUM_RE_W { + TX_ACK_NUM_RE_W::new(self, 5) + } + #[doc = "Bit 7 - Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status."] + #[inline(always)] + #[must_use] + pub fn wait_sw_start(&mut self) -> WAIT_SW_START_W { + WAIT_SW_START_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT."] + #[inline(always)] + #[must_use] + pub fn sw_start(&mut self) -> SW_START_W { + SW_START_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Configuration Register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF1_SPEC; +impl crate::RegisterSpec for CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf1::R`](R) reader structure"] +impl crate::Readable for CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf1::W`](W) writer structure"] +impl crate::Writable for CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF1 to value 0x33"] +impl crate::Resettable for CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x33; +} diff --git a/esp32p4/src/uhci0/date.rs b/esp32p4/src/uhci0/date.rs new file mode 100644 index 0000000000..067d3e2797 --- /dev/null +++ b/esp32p4/src/uhci0/date.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `DATE` reader - Configures version."] +pub type DATE_R = crate::FieldReader; +#[doc = "Field `DATE` writer - Configures version."] +pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Configures version."] + #[inline(always)] + pub fn date(&self) -> DATE_R { + DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field("date", &format_args!("{}", self.date().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Configures version."] + #[inline(always)] + #[must_use] + pub fn date(&mut self) -> DATE_W { + DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Version Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0220_1100"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0220_1100; +} diff --git a/esp32p4/src/uhci0/esc_conf0.rs b/esp32p4/src/uhci0/esc_conf0.rs new file mode 100644 index 0000000000..9b61231d2d --- /dev/null +++ b/esp32p4/src/uhci0/esc_conf0.rs @@ -0,0 +1,101 @@ +#[doc = "Register `ESC_CONF0` reader"] +pub type R = crate::R; +#[doc = "Register `ESC_CONF0` writer"] +pub type W = crate::W; +#[doc = "Field `SEPER_CHAR` reader - Configures the delimiter for encoding, default value is 0xC0."] +pub type SEPER_CHAR_R = crate::FieldReader; +#[doc = "Field `SEPER_CHAR` writer - Configures the delimiter for encoding, default value is 0xC0."] +pub type SEPER_CHAR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SEPER_ESC_CHAR0` reader - Configures the first char of SLIP escape character, default value is 0xDB."] +pub type SEPER_ESC_CHAR0_R = crate::FieldReader; +#[doc = "Field `SEPER_ESC_CHAR0` writer - Configures the first char of SLIP escape character, default value is 0xDB."] +pub type SEPER_ESC_CHAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SEPER_ESC_CHAR1` reader - Configures the second char of SLIP escape character, default value is 0xDC."] +pub type SEPER_ESC_CHAR1_R = crate::FieldReader; +#[doc = "Field `SEPER_ESC_CHAR1` writer - Configures the second char of SLIP escape character, default value is 0xDC."] +pub type SEPER_ESC_CHAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures the delimiter for encoding, default value is 0xC0."] + #[inline(always)] + pub fn seper_char(&self) -> SEPER_CHAR_R { + SEPER_CHAR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Configures the first char of SLIP escape character, default value is 0xDB."] + #[inline(always)] + pub fn seper_esc_char0(&self) -> SEPER_ESC_CHAR0_R { + SEPER_ESC_CHAR0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Configures the second char of SLIP escape character, default value is 0xDC."] + #[inline(always)] + pub fn seper_esc_char1(&self) -> SEPER_ESC_CHAR1_R { + SEPER_ESC_CHAR1_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ESC_CONF0") + .field("seper_char", &format_args!("{}", self.seper_char().bits())) + .field( + "seper_esc_char0", + &format_args!("{}", self.seper_esc_char0().bits()), + ) + .field( + "seper_esc_char1", + &format_args!("{}", self.seper_esc_char1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures the delimiter for encoding, default value is 0xC0."] + #[inline(always)] + #[must_use] + pub fn seper_char(&mut self) -> SEPER_CHAR_W { + SEPER_CHAR_W::new(self, 0) + } + #[doc = "Bits 8:15 - Configures the first char of SLIP escape character, default value is 0xDB."] + #[inline(always)] + #[must_use] + pub fn seper_esc_char0(&mut self) -> SEPER_ESC_CHAR0_W { + SEPER_ESC_CHAR0_W::new(self, 8) + } + #[doc = "Bits 16:23 - Configures the second char of SLIP escape character, default value is 0xDC."] + #[inline(always)] + #[must_use] + pub fn seper_esc_char1(&mut self) -> SEPER_ESC_CHAR1_W { + SEPER_ESC_CHAR1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Escapes Sequence Configuration Register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esc_conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esc_conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ESC_CONF0_SPEC; +impl crate::RegisterSpec for ESC_CONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`esc_conf0::R`](R) reader structure"] +impl crate::Readable for ESC_CONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`esc_conf0::W`](W) writer structure"] +impl crate::Writable for ESC_CONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ESC_CONF0 to value 0x00dc_dbc0"] +impl crate::Resettable for ESC_CONF0_SPEC { + const RESET_VALUE: Self::Ux = 0x00dc_dbc0; +} diff --git a/esp32p4/src/uhci0/esc_conf1.rs b/esp32p4/src/uhci0/esc_conf1.rs new file mode 100644 index 0000000000..4fcaf8cdff --- /dev/null +++ b/esp32p4/src/uhci0/esc_conf1.rs @@ -0,0 +1,101 @@ +#[doc = "Register `ESC_CONF1` reader"] +pub type R = crate::R; +#[doc = "Register `ESC_CONF1` writer"] +pub type W = crate::W; +#[doc = "Field `ESC_SEQ0` reader - Configures the char needing encoding, which is 0xDB as flow control char by default."] +pub type ESC_SEQ0_R = crate::FieldReader; +#[doc = "Field `ESC_SEQ0` writer - Configures the char needing encoding, which is 0xDB as flow control char by default."] +pub type ESC_SEQ0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ESC_SEQ0_CHAR0` reader - Configures the first char of SLIP escape character, default value is 0xDB."] +pub type ESC_SEQ0_CHAR0_R = crate::FieldReader; +#[doc = "Field `ESC_SEQ0_CHAR0` writer - Configures the first char of SLIP escape character, default value is 0xDB."] +pub type ESC_SEQ0_CHAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ESC_SEQ0_CHAR1` reader - Configures the second char of SLIP escape character, default value is 0xDD."] +pub type ESC_SEQ0_CHAR1_R = crate::FieldReader; +#[doc = "Field `ESC_SEQ0_CHAR1` writer - Configures the second char of SLIP escape character, default value is 0xDD."] +pub type ESC_SEQ0_CHAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures the char needing encoding, which is 0xDB as flow control char by default."] + #[inline(always)] + pub fn esc_seq0(&self) -> ESC_SEQ0_R { + ESC_SEQ0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Configures the first char of SLIP escape character, default value is 0xDB."] + #[inline(always)] + pub fn esc_seq0_char0(&self) -> ESC_SEQ0_CHAR0_R { + ESC_SEQ0_CHAR0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Configures the second char of SLIP escape character, default value is 0xDD."] + #[inline(always)] + pub fn esc_seq0_char1(&self) -> ESC_SEQ0_CHAR1_R { + ESC_SEQ0_CHAR1_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ESC_CONF1") + .field("esc_seq0", &format_args!("{}", self.esc_seq0().bits())) + .field( + "esc_seq0_char0", + &format_args!("{}", self.esc_seq0_char0().bits()), + ) + .field( + "esc_seq0_char1", + &format_args!("{}", self.esc_seq0_char1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures the char needing encoding, which is 0xDB as flow control char by default."] + #[inline(always)] + #[must_use] + pub fn esc_seq0(&mut self) -> ESC_SEQ0_W { + ESC_SEQ0_W::new(self, 0) + } + #[doc = "Bits 8:15 - Configures the first char of SLIP escape character, default value is 0xDB."] + #[inline(always)] + #[must_use] + pub fn esc_seq0_char0(&mut self) -> ESC_SEQ0_CHAR0_W { + ESC_SEQ0_CHAR0_W::new(self, 8) + } + #[doc = "Bits 16:23 - Configures the second char of SLIP escape character, default value is 0xDD."] + #[inline(always)] + #[must_use] + pub fn esc_seq0_char1(&mut self) -> ESC_SEQ0_CHAR1_W { + ESC_SEQ0_CHAR1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Escapes Sequence Configuration Register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esc_conf1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esc_conf1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ESC_CONF1_SPEC; +impl crate::RegisterSpec for ESC_CONF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`esc_conf1::R`](R) reader structure"] +impl crate::Readable for ESC_CONF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`esc_conf1::W`](W) writer structure"] +impl crate::Writable for ESC_CONF1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ESC_CONF1 to value 0x00dd_dbdb"] +impl crate::Resettable for ESC_CONF1_SPEC { + const RESET_VALUE: Self::Ux = 0x00dd_dbdb; +} diff --git a/esp32p4/src/uhci0/esc_conf2.rs b/esp32p4/src/uhci0/esc_conf2.rs new file mode 100644 index 0000000000..4980357c30 --- /dev/null +++ b/esp32p4/src/uhci0/esc_conf2.rs @@ -0,0 +1,101 @@ +#[doc = "Register `ESC_CONF2` reader"] +pub type R = crate::R; +#[doc = "Register `ESC_CONF2` writer"] +pub type W = crate::W; +#[doc = "Field `ESC_SEQ1` reader - Configures the char needing encoding, which is 0x11 as flow control char by default."] +pub type ESC_SEQ1_R = crate::FieldReader; +#[doc = "Field `ESC_SEQ1` writer - Configures the char needing encoding, which is 0x11 as flow control char by default."] +pub type ESC_SEQ1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ESC_SEQ1_CHAR0` reader - Configures the first char of SLIP escape character, default value is 0xDB."] +pub type ESC_SEQ1_CHAR0_R = crate::FieldReader; +#[doc = "Field `ESC_SEQ1_CHAR0` writer - Configures the first char of SLIP escape character, default value is 0xDB."] +pub type ESC_SEQ1_CHAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ESC_SEQ1_CHAR1` reader - Configures the second char of SLIP escape character, default value is 0xDE."] +pub type ESC_SEQ1_CHAR1_R = crate::FieldReader; +#[doc = "Field `ESC_SEQ1_CHAR1` writer - Configures the second char of SLIP escape character, default value is 0xDE."] +pub type ESC_SEQ1_CHAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures the char needing encoding, which is 0x11 as flow control char by default."] + #[inline(always)] + pub fn esc_seq1(&self) -> ESC_SEQ1_R { + ESC_SEQ1_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Configures the first char of SLIP escape character, default value is 0xDB."] + #[inline(always)] + pub fn esc_seq1_char0(&self) -> ESC_SEQ1_CHAR0_R { + ESC_SEQ1_CHAR0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Configures the second char of SLIP escape character, default value is 0xDE."] + #[inline(always)] + pub fn esc_seq1_char1(&self) -> ESC_SEQ1_CHAR1_R { + ESC_SEQ1_CHAR1_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ESC_CONF2") + .field("esc_seq1", &format_args!("{}", self.esc_seq1().bits())) + .field( + "esc_seq1_char0", + &format_args!("{}", self.esc_seq1_char0().bits()), + ) + .field( + "esc_seq1_char1", + &format_args!("{}", self.esc_seq1_char1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures the char needing encoding, which is 0x11 as flow control char by default."] + #[inline(always)] + #[must_use] + pub fn esc_seq1(&mut self) -> ESC_SEQ1_W { + ESC_SEQ1_W::new(self, 0) + } + #[doc = "Bits 8:15 - Configures the first char of SLIP escape character, default value is 0xDB."] + #[inline(always)] + #[must_use] + pub fn esc_seq1_char0(&mut self) -> ESC_SEQ1_CHAR0_W { + ESC_SEQ1_CHAR0_W::new(self, 8) + } + #[doc = "Bits 16:23 - Configures the second char of SLIP escape character, default value is 0xDE."] + #[inline(always)] + #[must_use] + pub fn esc_seq1_char1(&mut self) -> ESC_SEQ1_CHAR1_W { + ESC_SEQ1_CHAR1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Escapes Sequence Configuration Register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esc_conf2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esc_conf2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ESC_CONF2_SPEC; +impl crate::RegisterSpec for ESC_CONF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`esc_conf2::R`](R) reader structure"] +impl crate::Readable for ESC_CONF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`esc_conf2::W`](W) writer structure"] +impl crate::Writable for ESC_CONF2_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ESC_CONF2 to value 0x00de_db11"] +impl crate::Resettable for ESC_CONF2_SPEC { + const RESET_VALUE: Self::Ux = 0x00de_db11; +} diff --git a/esp32p4/src/uhci0/esc_conf3.rs b/esp32p4/src/uhci0/esc_conf3.rs new file mode 100644 index 0000000000..9cc7b0d1e0 --- /dev/null +++ b/esp32p4/src/uhci0/esc_conf3.rs @@ -0,0 +1,101 @@ +#[doc = "Register `ESC_CONF3` reader"] +pub type R = crate::R; +#[doc = "Register `ESC_CONF3` writer"] +pub type W = crate::W; +#[doc = "Field `ESC_SEQ2` reader - Configures the char needing encoding, which is 0x13 as flow control char by default."] +pub type ESC_SEQ2_R = crate::FieldReader; +#[doc = "Field `ESC_SEQ2` writer - Configures the char needing encoding, which is 0x13 as flow control char by default."] +pub type ESC_SEQ2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ESC_SEQ2_CHAR0` reader - Configures the first char of SLIP escape character, default value is 0xDB."] +pub type ESC_SEQ2_CHAR0_R = crate::FieldReader; +#[doc = "Field `ESC_SEQ2_CHAR0` writer - Configures the first char of SLIP escape character, default value is 0xDB."] +pub type ESC_SEQ2_CHAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ESC_SEQ2_CHAR1` reader - Configures the second char of SLIP escape character, default value is 0xDF."] +pub type ESC_SEQ2_CHAR1_R = crate::FieldReader; +#[doc = "Field `ESC_SEQ2_CHAR1` writer - Configures the second char of SLIP escape character, default value is 0xDF."] +pub type ESC_SEQ2_CHAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Configures the char needing encoding, which is 0x13 as flow control char by default."] + #[inline(always)] + pub fn esc_seq2(&self) -> ESC_SEQ2_R { + ESC_SEQ2_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Configures the first char of SLIP escape character, default value is 0xDB."] + #[inline(always)] + pub fn esc_seq2_char0(&self) -> ESC_SEQ2_CHAR0_R { + ESC_SEQ2_CHAR0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Configures the second char of SLIP escape character, default value is 0xDF."] + #[inline(always)] + pub fn esc_seq2_char1(&self) -> ESC_SEQ2_CHAR1_R { + ESC_SEQ2_CHAR1_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ESC_CONF3") + .field("esc_seq2", &format_args!("{}", self.esc_seq2().bits())) + .field( + "esc_seq2_char0", + &format_args!("{}", self.esc_seq2_char0().bits()), + ) + .field( + "esc_seq2_char1", + &format_args!("{}", self.esc_seq2_char1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Configures the char needing encoding, which is 0x13 as flow control char by default."] + #[inline(always)] + #[must_use] + pub fn esc_seq2(&mut self) -> ESC_SEQ2_W { + ESC_SEQ2_W::new(self, 0) + } + #[doc = "Bits 8:15 - Configures the first char of SLIP escape character, default value is 0xDB."] + #[inline(always)] + #[must_use] + pub fn esc_seq2_char0(&mut self) -> ESC_SEQ2_CHAR0_W { + ESC_SEQ2_CHAR0_W::new(self, 8) + } + #[doc = "Bits 16:23 - Configures the second char of SLIP escape character, default value is 0xDF."] + #[inline(always)] + #[must_use] + pub fn esc_seq2_char1(&mut self) -> ESC_SEQ2_CHAR1_W { + ESC_SEQ2_CHAR1_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Escapes Sequence Configuration Register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`esc_conf3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esc_conf3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ESC_CONF3_SPEC; +impl crate::RegisterSpec for ESC_CONF3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`esc_conf3::R`](R) reader structure"] +impl crate::Readable for ESC_CONF3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`esc_conf3::W`](W) writer structure"] +impl crate::Writable for ESC_CONF3_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ESC_CONF3 to value 0x00df_db13"] +impl crate::Resettable for ESC_CONF3_SPEC { + const RESET_VALUE: Self::Ux = 0x00df_db13; +} diff --git a/esp32p4/src/uhci0/escape_conf.rs b/esp32p4/src/uhci0/escape_conf.rs new file mode 100644 index 0000000000..204071f393 --- /dev/null +++ b/esp32p4/src/uhci0/escape_conf.rs @@ -0,0 +1,199 @@ +#[doc = "Register `ESCAPE_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `ESCAPE_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `TX_C0_ESC_EN` reader - Set this bit to enable resolve char 0xC0 when DMA receiving data."] +pub type TX_C0_ESC_EN_R = crate::BitReader; +#[doc = "Field `TX_C0_ESC_EN` writer - Set this bit to enable resolve char 0xC0 when DMA receiving data."] +pub type TX_C0_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DB_ESC_EN` reader - Set this bit to enable resolve char 0xDB when DMA receiving data."] +pub type TX_DB_ESC_EN_R = crate::BitReader; +#[doc = "Field `TX_DB_ESC_EN` writer - Set this bit to enable resolve char 0xDB when DMA receiving data."] +pub type TX_DB_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_11_ESC_EN` reader - Set this bit to enable resolve flow control char 0x11 when DMA receiving data."] +pub type TX_11_ESC_EN_R = crate::BitReader; +#[doc = "Field `TX_11_ESC_EN` writer - Set this bit to enable resolve flow control char 0x11 when DMA receiving data."] +pub type TX_11_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_13_ESC_EN` reader - Set this bit to enable resolve flow control char 0x13 when DMA receiving data."] +pub type TX_13_ESC_EN_R = crate::BitReader; +#[doc = "Field `TX_13_ESC_EN` writer - Set this bit to enable resolve flow control char 0x13 when DMA receiving data."] +pub type TX_13_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_C0_ESC_EN` reader - Set this bit to enable replacing 0xC0 with special char when DMA receiving data."] +pub type RX_C0_ESC_EN_R = crate::BitReader; +#[doc = "Field `RX_C0_ESC_EN` writer - Set this bit to enable replacing 0xC0 with special char when DMA receiving data."] +pub type RX_C0_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DB_ESC_EN` reader - Set this bit to enable replacing 0xDB with special char when DMA receiving data."] +pub type RX_DB_ESC_EN_R = crate::BitReader; +#[doc = "Field `RX_DB_ESC_EN` writer - Set this bit to enable replacing 0xDB with special char when DMA receiving data."] +pub type RX_DB_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_11_ESC_EN` reader - Set this bit to enable replacing 0x11 with special char when DMA receiving data."] +pub type RX_11_ESC_EN_R = crate::BitReader; +#[doc = "Field `RX_11_ESC_EN` writer - Set this bit to enable replacing 0x11 with special char when DMA receiving data."] +pub type RX_11_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_13_ESC_EN` reader - Set this bit to enable replacing 0x13 with special char when DMA receiving data."] +pub type RX_13_ESC_EN_R = crate::BitReader; +#[doc = "Field `RX_13_ESC_EN` writer - Set this bit to enable replacing 0x13 with special char when DMA receiving data."] +pub type RX_13_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable resolve char 0xC0 when DMA receiving data."] + #[inline(always)] + pub fn tx_c0_esc_en(&self) -> TX_C0_ESC_EN_R { + TX_C0_ESC_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to enable resolve char 0xDB when DMA receiving data."] + #[inline(always)] + pub fn tx_db_esc_en(&self) -> TX_DB_ESC_EN_R { + TX_DB_ESC_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to enable resolve flow control char 0x11 when DMA receiving data."] + #[inline(always)] + pub fn tx_11_esc_en(&self) -> TX_11_ESC_EN_R { + TX_11_ESC_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to enable resolve flow control char 0x13 when DMA receiving data."] + #[inline(always)] + pub fn tx_13_esc_en(&self) -> TX_13_ESC_EN_R { + TX_13_ESC_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable replacing 0xC0 with special char when DMA receiving data."] + #[inline(always)] + pub fn rx_c0_esc_en(&self) -> RX_C0_ESC_EN_R { + RX_C0_ESC_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set this bit to enable replacing 0xDB with special char when DMA receiving data."] + #[inline(always)] + pub fn rx_db_esc_en(&self) -> RX_DB_ESC_EN_R { + RX_DB_ESC_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set this bit to enable replacing 0x11 with special char when DMA receiving data."] + #[inline(always)] + pub fn rx_11_esc_en(&self) -> RX_11_ESC_EN_R { + RX_11_ESC_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set this bit to enable replacing 0x13 with special char when DMA receiving data."] + #[inline(always)] + pub fn rx_13_esc_en(&self) -> RX_13_ESC_EN_R { + RX_13_ESC_EN_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ESCAPE_CONF") + .field( + "tx_c0_esc_en", + &format_args!("{}", self.tx_c0_esc_en().bit()), + ) + .field( + "tx_db_esc_en", + &format_args!("{}", self.tx_db_esc_en().bit()), + ) + .field( + "tx_11_esc_en", + &format_args!("{}", self.tx_11_esc_en().bit()), + ) + .field( + "tx_13_esc_en", + &format_args!("{}", self.tx_13_esc_en().bit()), + ) + .field( + "rx_c0_esc_en", + &format_args!("{}", self.rx_c0_esc_en().bit()), + ) + .field( + "rx_db_esc_en", + &format_args!("{}", self.rx_db_esc_en().bit()), + ) + .field( + "rx_11_esc_en", + &format_args!("{}", self.rx_11_esc_en().bit()), + ) + .field( + "rx_13_esc_en", + &format_args!("{}", self.rx_13_esc_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable resolve char 0xC0 when DMA receiving data."] + #[inline(always)] + #[must_use] + pub fn tx_c0_esc_en(&mut self) -> TX_C0_ESC_EN_W { + TX_C0_ESC_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to enable resolve char 0xDB when DMA receiving data."] + #[inline(always)] + #[must_use] + pub fn tx_db_esc_en(&mut self) -> TX_DB_ESC_EN_W { + TX_DB_ESC_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to enable resolve flow control char 0x11 when DMA receiving data."] + #[inline(always)] + #[must_use] + pub fn tx_11_esc_en(&mut self) -> TX_11_ESC_EN_W { + TX_11_ESC_EN_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to enable resolve flow control char 0x13 when DMA receiving data."] + #[inline(always)] + #[must_use] + pub fn tx_13_esc_en(&mut self) -> TX_13_ESC_EN_W { + TX_13_ESC_EN_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable replacing 0xC0 with special char when DMA receiving data."] + #[inline(always)] + #[must_use] + pub fn rx_c0_esc_en(&mut self) -> RX_C0_ESC_EN_W { + RX_C0_ESC_EN_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to enable replacing 0xDB with special char when DMA receiving data."] + #[inline(always)] + #[must_use] + pub fn rx_db_esc_en(&mut self) -> RX_DB_ESC_EN_W { + RX_DB_ESC_EN_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to enable replacing 0x11 with special char when DMA receiving data."] + #[inline(always)] + #[must_use] + pub fn rx_11_esc_en(&mut self) -> RX_11_ESC_EN_W { + RX_11_ESC_EN_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to enable replacing 0x13 with special char when DMA receiving data."] + #[inline(always)] + #[must_use] + pub fn rx_13_esc_en(&mut self) -> RX_13_ESC_EN_W { + RX_13_ESC_EN_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Escapes Configuration Register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`escape_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`escape_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ESCAPE_CONF_SPEC; +impl crate::RegisterSpec for ESCAPE_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`escape_conf::R`](R) reader structure"] +impl crate::Readable for ESCAPE_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`escape_conf::W`](W) writer structure"] +impl crate::Writable for ESCAPE_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ESCAPE_CONF to value 0x33"] +impl crate::Resettable for ESCAPE_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x33; +} diff --git a/esp32p4/src/uhci0/hung_conf.rs b/esp32p4/src/uhci0/hung_conf.rs new file mode 100644 index 0000000000..6ad3ef03a2 --- /dev/null +++ b/esp32p4/src/uhci0/hung_conf.rs @@ -0,0 +1,161 @@ +#[doc = "Register `HUNG_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `HUNG_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `TXFIFO_TIMEOUT` reader - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data."] +pub type TXFIFO_TIMEOUT_R = crate::FieldReader; +#[doc = "Field `TXFIFO_TIMEOUT` writer - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data."] +pub type TXFIFO_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TXFIFO_TIMEOUT_SHIFT` reader - Configures the maximum counter value."] +pub type TXFIFO_TIMEOUT_SHIFT_R = crate::FieldReader; +#[doc = "Field `TXFIFO_TIMEOUT_SHIFT` writer - Configures the maximum counter value."] +pub type TXFIFO_TIMEOUT_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `TXFIFO_TIMEOUT_ENA` reader - Set this bit to enable TX FIFO timeout when receiving."] +pub type TXFIFO_TIMEOUT_ENA_R = crate::BitReader; +#[doc = "Field `TXFIFO_TIMEOUT_ENA` writer - Set this bit to enable TX FIFO timeout when receiving."] +pub type TXFIFO_TIMEOUT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFIFO_TIMEOUT` reader - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data."] +pub type RXFIFO_TIMEOUT_R = crate::FieldReader; +#[doc = "Field `RXFIFO_TIMEOUT` writer - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data."] +pub type RXFIFO_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RXFIFO_TIMEOUT_SHIFT` reader - Configures the maximum counter value."] +pub type RXFIFO_TIMEOUT_SHIFT_R = crate::FieldReader; +#[doc = "Field `RXFIFO_TIMEOUT_SHIFT` writer - Configures the maximum counter value."] +pub type RXFIFO_TIMEOUT_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `RXFIFO_TIMEOUT_ENA` reader - Set this bit to enable TX FIFO timeout when DMA sending data."] +pub type RXFIFO_TIMEOUT_ENA_R = crate::BitReader; +#[doc = "Field `RXFIFO_TIMEOUT_ENA` writer - Set this bit to enable TX FIFO timeout when DMA sending data."] +pub type RXFIFO_TIMEOUT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data."] + #[inline(always)] + pub fn txfifo_timeout(&self) -> TXFIFO_TIMEOUT_R { + TXFIFO_TIMEOUT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Configures the maximum counter value."] + #[inline(always)] + pub fn txfifo_timeout_shift(&self) -> TXFIFO_TIMEOUT_SHIFT_R { + TXFIFO_TIMEOUT_SHIFT_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - Set this bit to enable TX FIFO timeout when receiving."] + #[inline(always)] + pub fn txfifo_timeout_ena(&self) -> TXFIFO_TIMEOUT_ENA_R { + TXFIFO_TIMEOUT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:19 - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data."] + #[inline(always)] + pub fn rxfifo_timeout(&self) -> RXFIFO_TIMEOUT_R { + RXFIFO_TIMEOUT_R::new(((self.bits >> 12) & 0xff) as u8) + } + #[doc = "Bits 20:22 - Configures the maximum counter value."] + #[inline(always)] + pub fn rxfifo_timeout_shift(&self) -> RXFIFO_TIMEOUT_SHIFT_R { + RXFIFO_TIMEOUT_SHIFT_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - Set this bit to enable TX FIFO timeout when DMA sending data."] + #[inline(always)] + pub fn rxfifo_timeout_ena(&self) -> RXFIFO_TIMEOUT_ENA_R { + RXFIFO_TIMEOUT_ENA_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HUNG_CONF") + .field( + "txfifo_timeout", + &format_args!("{}", self.txfifo_timeout().bits()), + ) + .field( + "txfifo_timeout_shift", + &format_args!("{}", self.txfifo_timeout_shift().bits()), + ) + .field( + "txfifo_timeout_ena", + &format_args!("{}", self.txfifo_timeout_ena().bit()), + ) + .field( + "rxfifo_timeout", + &format_args!("{}", self.rxfifo_timeout().bits()), + ) + .field( + "rxfifo_timeout_shift", + &format_args!("{}", self.rxfifo_timeout_shift().bits()), + ) + .field( + "rxfifo_timeout_ena", + &format_args!("{}", self.rxfifo_timeout_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data."] + #[inline(always)] + #[must_use] + pub fn txfifo_timeout(&mut self) -> TXFIFO_TIMEOUT_W { + TXFIFO_TIMEOUT_W::new(self, 0) + } + #[doc = "Bits 8:10 - Configures the maximum counter value."] + #[inline(always)] + #[must_use] + pub fn txfifo_timeout_shift(&mut self) -> TXFIFO_TIMEOUT_SHIFT_W { + TXFIFO_TIMEOUT_SHIFT_W::new(self, 8) + } + #[doc = "Bit 11 - Set this bit to enable TX FIFO timeout when receiving."] + #[inline(always)] + #[must_use] + pub fn txfifo_timeout_ena(&mut self) -> TXFIFO_TIMEOUT_ENA_W { + TXFIFO_TIMEOUT_ENA_W::new(self, 11) + } + #[doc = "Bits 12:19 - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data."] + #[inline(always)] + #[must_use] + pub fn rxfifo_timeout(&mut self) -> RXFIFO_TIMEOUT_W { + RXFIFO_TIMEOUT_W::new(self, 12) + } + #[doc = "Bits 20:22 - Configures the maximum counter value."] + #[inline(always)] + #[must_use] + pub fn rxfifo_timeout_shift(&mut self) -> RXFIFO_TIMEOUT_SHIFT_W { + RXFIFO_TIMEOUT_SHIFT_W::new(self, 20) + } + #[doc = "Bit 23 - Set this bit to enable TX FIFO timeout when DMA sending data."] + #[inline(always)] + #[must_use] + pub fn rxfifo_timeout_ena(&mut self) -> RXFIFO_TIMEOUT_ENA_W { + RXFIFO_TIMEOUT_ENA_W::new(self, 23) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Hung Configuration Register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hung_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hung_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HUNG_CONF_SPEC; +impl crate::RegisterSpec for HUNG_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hung_conf::R`](R) reader structure"] +impl crate::Readable for HUNG_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hung_conf::W`](W) writer structure"] +impl crate::Writable for HUNG_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HUNG_CONF to value 0x0081_0810"] +impl crate::Resettable for HUNG_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0081_0810; +} diff --git a/esp32p4/src/uhci0/int_clr.rs b/esp32p4/src/uhci0/int_clr.rs new file mode 100644 index 0000000000..0a5c60b880 --- /dev/null +++ b/esp32p4/src/uhci0/int_clr.rs @@ -0,0 +1,106 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RX_START_INT_CLR` writer - Set this bit to clear the raw interrupt of UHCI_RX_START_INT."] +pub type RX_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_START_INT_CLR` writer - Set this bit to clear the raw interrupt of UHCI_TX_START_INT."] +pub type TX_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_HUNG_INT_CLR` writer - Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT."] +pub type RX_HUNG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_HUNG_INT_CLR` writer - Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT."] +pub type TX_HUNG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_S_REG_Q_INT_CLR` writer - Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT."] +pub type SEND_S_REG_Q_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_A_REG_Q_INT_CLR` writer - Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT."] +pub type SEND_A_REG_Q_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_EOF_ERR_INT_CLR` writer - Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT."] +pub type OUTLINK_EOF_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APP_CTRL0_INT_CLR` writer - Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT."] +pub type APP_CTRL0_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APP_CTRL1_INT_CLR` writer - Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT."] +pub type APP_CTRL1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the raw interrupt of UHCI_RX_START_INT."] + #[inline(always)] + #[must_use] + pub fn rx_start_int_clr(&mut self) -> RX_START_INT_CLR_W { + RX_START_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the raw interrupt of UHCI_TX_START_INT."] + #[inline(always)] + #[must_use] + pub fn tx_start_int_clr(&mut self) -> TX_START_INT_CLR_W { + TX_START_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT."] + #[inline(always)] + #[must_use] + pub fn rx_hung_int_clr(&mut self) -> RX_HUNG_INT_CLR_W { + RX_HUNG_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT."] + #[inline(always)] + #[must_use] + pub fn tx_hung_int_clr(&mut self) -> TX_HUNG_INT_CLR_W { + TX_HUNG_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT."] + #[inline(always)] + #[must_use] + pub fn send_s_reg_q_int_clr(&mut self) -> SEND_S_REG_Q_INT_CLR_W { + SEND_S_REG_Q_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT."] + #[inline(always)] + #[must_use] + pub fn send_a_reg_q_int_clr(&mut self) -> SEND_A_REG_Q_INT_CLR_W { + SEND_A_REG_Q_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT."] + #[inline(always)] + #[must_use] + pub fn outlink_eof_err_int_clr(&mut self) -> OUTLINK_EOF_ERR_INT_CLR_W { + OUTLINK_EOF_ERR_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT."] + #[inline(always)] + #[must_use] + pub fn app_ctrl0_int_clr(&mut self) -> APP_CTRL0_INT_CLR_W { + APP_CTRL0_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT."] + #[inline(always)] + #[must_use] + pub fn app_ctrl1_int_clr(&mut self) -> APP_CTRL1_INT_CLR_W { + APP_CTRL1_INT_CLR_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/int_ena.rs b/esp32p4/src/uhci0/int_ena.rs new file mode 100644 index 0000000000..b9846c72dc --- /dev/null +++ b/esp32p4/src/uhci0/int_ena.rs @@ -0,0 +1,218 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `RX_START_INT_ENA` reader - Set this bit to enable the interrupt of UHCI_RX_START_INT."] +pub type RX_START_INT_ENA_R = crate::BitReader; +#[doc = "Field `RX_START_INT_ENA` writer - Set this bit to enable the interrupt of UHCI_RX_START_INT."] +pub type RX_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_START_INT_ENA` reader - Set this bit to enable the interrupt of UHCI_TX_START_INT."] +pub type TX_START_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_START_INT_ENA` writer - Set this bit to enable the interrupt of UHCI_TX_START_INT."] +pub type TX_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_HUNG_INT_ENA` reader - Set this bit to enable the interrupt of UHCI_RX_HUNG_INT."] +pub type RX_HUNG_INT_ENA_R = crate::BitReader; +#[doc = "Field `RX_HUNG_INT_ENA` writer - Set this bit to enable the interrupt of UHCI_RX_HUNG_INT."] +pub type RX_HUNG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_HUNG_INT_ENA` reader - Set this bit to enable the interrupt of UHCI_TX_HUNG_INT."] +pub type TX_HUNG_INT_ENA_R = crate::BitReader; +#[doc = "Field `TX_HUNG_INT_ENA` writer - Set this bit to enable the interrupt of UHCI_TX_HUNG_INT."] +pub type TX_HUNG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_S_REG_Q_INT_ENA` reader - Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT."] +pub type SEND_S_REG_Q_INT_ENA_R = crate::BitReader; +#[doc = "Field `SEND_S_REG_Q_INT_ENA` writer - Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT."] +pub type SEND_S_REG_Q_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_A_REG_Q_INT_ENA` reader - Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT."] +pub type SEND_A_REG_Q_INT_ENA_R = crate::BitReader; +#[doc = "Field `SEND_A_REG_Q_INT_ENA` writer - Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT."] +pub type SEND_A_REG_Q_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUTLINK_EOF_ERR_INT_ENA` reader - Set this bit to enable the interrupt of UHCI_OUT_EOF_INT."] +pub type OUTLINK_EOF_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `OUTLINK_EOF_ERR_INT_ENA` writer - Set this bit to enable the interrupt of UHCI_OUT_EOF_INT."] +pub type OUTLINK_EOF_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APP_CTRL0_INT_ENA` reader - Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT."] +pub type APP_CTRL0_INT_ENA_R = crate::BitReader; +#[doc = "Field `APP_CTRL0_INT_ENA` writer - Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT."] +pub type APP_CTRL0_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APP_CTRL1_INT_ENA` reader - Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT."] +pub type APP_CTRL1_INT_ENA_R = crate::BitReader; +#[doc = "Field `APP_CTRL1_INT_ENA` writer - Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT."] +pub type APP_CTRL1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set this bit to enable the interrupt of UHCI_RX_START_INT."] + #[inline(always)] + pub fn rx_start_int_ena(&self) -> RX_START_INT_ENA_R { + RX_START_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set this bit to enable the interrupt of UHCI_TX_START_INT."] + #[inline(always)] + pub fn tx_start_int_ena(&self) -> TX_START_INT_ENA_R { + TX_START_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to enable the interrupt of UHCI_RX_HUNG_INT."] + #[inline(always)] + pub fn rx_hung_int_ena(&self) -> RX_HUNG_INT_ENA_R { + RX_HUNG_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set this bit to enable the interrupt of UHCI_TX_HUNG_INT."] + #[inline(always)] + pub fn tx_hung_int_ena(&self) -> TX_HUNG_INT_ENA_R { + TX_HUNG_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT."] + #[inline(always)] + pub fn send_s_reg_q_int_ena(&self) -> SEND_S_REG_Q_INT_ENA_R { + SEND_S_REG_Q_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT."] + #[inline(always)] + pub fn send_a_reg_q_int_ena(&self) -> SEND_A_REG_Q_INT_ENA_R { + SEND_A_REG_Q_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set this bit to enable the interrupt of UHCI_OUT_EOF_INT."] + #[inline(always)] + pub fn outlink_eof_err_int_ena(&self) -> OUTLINK_EOF_ERR_INT_ENA_R { + OUTLINK_EOF_ERR_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT."] + #[inline(always)] + pub fn app_ctrl0_int_ena(&self) -> APP_CTRL0_INT_ENA_R { + APP_CTRL0_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT."] + #[inline(always)] + pub fn app_ctrl1_int_ena(&self) -> APP_CTRL1_INT_ENA_R { + APP_CTRL1_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "rx_start_int_ena", + &format_args!("{}", self.rx_start_int_ena().bit()), + ) + .field( + "tx_start_int_ena", + &format_args!("{}", self.tx_start_int_ena().bit()), + ) + .field( + "rx_hung_int_ena", + &format_args!("{}", self.rx_hung_int_ena().bit()), + ) + .field( + "tx_hung_int_ena", + &format_args!("{}", self.tx_hung_int_ena().bit()), + ) + .field( + "send_s_reg_q_int_ena", + &format_args!("{}", self.send_s_reg_q_int_ena().bit()), + ) + .field( + "send_a_reg_q_int_ena", + &format_args!("{}", self.send_a_reg_q_int_ena().bit()), + ) + .field( + "outlink_eof_err_int_ena", + &format_args!("{}", self.outlink_eof_err_int_ena().bit()), + ) + .field( + "app_ctrl0_int_ena", + &format_args!("{}", self.app_ctrl0_int_ena().bit()), + ) + .field( + "app_ctrl1_int_ena", + &format_args!("{}", self.app_ctrl1_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to enable the interrupt of UHCI_RX_START_INT."] + #[inline(always)] + #[must_use] + pub fn rx_start_int_ena(&mut self) -> RX_START_INT_ENA_W { + RX_START_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to enable the interrupt of UHCI_TX_START_INT."] + #[inline(always)] + #[must_use] + pub fn tx_start_int_ena(&mut self) -> TX_START_INT_ENA_W { + TX_START_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to enable the interrupt of UHCI_RX_HUNG_INT."] + #[inline(always)] + #[must_use] + pub fn rx_hung_int_ena(&mut self) -> RX_HUNG_INT_ENA_W { + RX_HUNG_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to enable the interrupt of UHCI_TX_HUNG_INT."] + #[inline(always)] + #[must_use] + pub fn tx_hung_int_ena(&mut self) -> TX_HUNG_INT_ENA_W { + TX_HUNG_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT."] + #[inline(always)] + #[must_use] + pub fn send_s_reg_q_int_ena(&mut self) -> SEND_S_REG_Q_INT_ENA_W { + SEND_S_REG_Q_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT."] + #[inline(always)] + #[must_use] + pub fn send_a_reg_q_int_ena(&mut self) -> SEND_A_REG_Q_INT_ENA_W { + SEND_A_REG_Q_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to enable the interrupt of UHCI_OUT_EOF_INT."] + #[inline(always)] + #[must_use] + pub fn outlink_eof_err_int_ena(&mut self) -> OUTLINK_EOF_ERR_INT_ENA_W { + OUTLINK_EOF_ERR_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT."] + #[inline(always)] + #[must_use] + pub fn app_ctrl0_int_ena(&mut self) -> APP_CTRL0_INT_ENA_W { + APP_CTRL0_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT."] + #[inline(always)] + #[must_use] + pub fn app_ctrl1_int_ena(&mut self) -> APP_CTRL1_INT_ENA_W { + APP_CTRL1_INT_ENA_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/int_raw.rs b/esp32p4/src/uhci0/int_raw.rs new file mode 100644 index 0000000000..ffa7d77776 --- /dev/null +++ b/esp32p4/src/uhci0/int_raw.rs @@ -0,0 +1,218 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `RX_START_INT_RAW` reader - Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully."] +pub type RX_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_START_INT_RAW` writer - Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully."] +pub type RX_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_START_INT_RAW` reader - Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter."] +pub type TX_START_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_START_INT_RAW` writer - Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter."] +pub type TX_START_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_HUNG_INT_RAW` reader - Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value."] +pub type RX_HUNG_INT_RAW_R = crate::BitReader; +#[doc = "Field `RX_HUNG_INT_RAW` writer - Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value."] +pub type RX_HUNG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_HUNG_INT_RAW` reader - Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value."] +pub type TX_HUNG_INT_RAW_R = crate::BitReader; +#[doc = "Field `TX_HUNG_INT_RAW` writer - Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value."] +pub type TX_HUNG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_S_REG_Q_INT_RAW` reader - Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode."] +pub type SEND_S_REG_Q_INT_RAW_R = crate::BitReader; +#[doc = "Field `SEND_S_REG_Q_INT_RAW` writer - Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode."] +pub type SEND_S_REG_Q_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_A_REG_Q_INT_RAW` reader - Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode."] +pub type SEND_A_REG_Q_INT_RAW_R = crate::BitReader; +#[doc = "Field `SEND_A_REG_Q_INT_RAW` writer - Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode."] +pub type SEND_A_REG_Q_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EOF_INT_RAW` reader - Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF."] +pub type OUT_EOF_INT_RAW_R = crate::BitReader; +#[doc = "Field `OUT_EOF_INT_RAW` writer - Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF."] +pub type OUT_EOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APP_CTRL0_INT_RAW` reader - Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1."] +pub type APP_CTRL0_INT_RAW_R = crate::BitReader; +#[doc = "Field `APP_CTRL0_INT_RAW` writer - Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1."] +pub type APP_CTRL0_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APP_CTRL1_INT_RAW` reader - Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1."] +pub type APP_CTRL1_INT_RAW_R = crate::BitReader; +#[doc = "Field `APP_CTRL1_INT_RAW` writer - Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1."] +pub type APP_CTRL1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully."] + #[inline(always)] + pub fn rx_start_int_raw(&self) -> RX_START_INT_RAW_R { + RX_START_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter."] + #[inline(always)] + pub fn tx_start_int_raw(&self) -> TX_START_INT_RAW_R { + TX_START_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value."] + #[inline(always)] + pub fn rx_hung_int_raw(&self) -> RX_HUNG_INT_RAW_R { + RX_HUNG_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value."] + #[inline(always)] + pub fn tx_hung_int_raw(&self) -> TX_HUNG_INT_RAW_R { + TX_HUNG_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode."] + #[inline(always)] + pub fn send_s_reg_q_int_raw(&self) -> SEND_S_REG_Q_INT_RAW_R { + SEND_S_REG_Q_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode."] + #[inline(always)] + pub fn send_a_reg_q_int_raw(&self) -> SEND_A_REG_Q_INT_RAW_R { + SEND_A_REG_Q_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF."] + #[inline(always)] + pub fn out_eof_int_raw(&self) -> OUT_EOF_INT_RAW_R { + OUT_EOF_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1."] + #[inline(always)] + pub fn app_ctrl0_int_raw(&self) -> APP_CTRL0_INT_RAW_R { + APP_CTRL0_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1."] + #[inline(always)] + pub fn app_ctrl1_int_raw(&self) -> APP_CTRL1_INT_RAW_R { + APP_CTRL1_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "rx_start_int_raw", + &format_args!("{}", self.rx_start_int_raw().bit()), + ) + .field( + "tx_start_int_raw", + &format_args!("{}", self.tx_start_int_raw().bit()), + ) + .field( + "rx_hung_int_raw", + &format_args!("{}", self.rx_hung_int_raw().bit()), + ) + .field( + "tx_hung_int_raw", + &format_args!("{}", self.tx_hung_int_raw().bit()), + ) + .field( + "send_s_reg_q_int_raw", + &format_args!("{}", self.send_s_reg_q_int_raw().bit()), + ) + .field( + "send_a_reg_q_int_raw", + &format_args!("{}", self.send_a_reg_q_int_raw().bit()), + ) + .field( + "out_eof_int_raw", + &format_args!("{}", self.out_eof_int_raw().bit()), + ) + .field( + "app_ctrl0_int_raw", + &format_args!("{}", self.app_ctrl0_int_raw().bit()), + ) + .field( + "app_ctrl1_int_raw", + &format_args!("{}", self.app_ctrl1_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully."] + #[inline(always)] + #[must_use] + pub fn rx_start_int_raw(&mut self) -> RX_START_INT_RAW_W { + RX_START_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter."] + #[inline(always)] + #[must_use] + pub fn tx_start_int_raw(&mut self) -> TX_START_INT_RAW_W { + TX_START_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value."] + #[inline(always)] + #[must_use] + pub fn rx_hung_int_raw(&mut self) -> RX_HUNG_INT_RAW_W { + RX_HUNG_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value."] + #[inline(always)] + #[must_use] + pub fn tx_hung_int_raw(&mut self) -> TX_HUNG_INT_RAW_W { + TX_HUNG_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode."] + #[inline(always)] + #[must_use] + pub fn send_s_reg_q_int_raw(&mut self) -> SEND_S_REG_Q_INT_RAW_W { + SEND_S_REG_Q_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode."] + #[inline(always)] + #[must_use] + pub fn send_a_reg_q_int_raw(&mut self) -> SEND_A_REG_Q_INT_RAW_W { + SEND_A_REG_Q_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF."] + #[inline(always)] + #[must_use] + pub fn out_eof_int_raw(&mut self) -> OUT_EOF_INT_RAW_W { + OUT_EOF_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1."] + #[inline(always)] + #[must_use] + pub fn app_ctrl0_int_raw(&mut self) -> APP_CTRL0_INT_RAW_W { + APP_CTRL0_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1."] + #[inline(always)] + #[must_use] + pub fn app_ctrl1_int_raw(&mut self) -> APP_CTRL1_INT_RAW_W { + APP_CTRL1_INT_RAW_W::new(self, 8) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Interrupt Raw Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/int_st.rs b/esp32p4/src/uhci0/int_st.rs new file mode 100644 index 0000000000..34825aa3eb --- /dev/null +++ b/esp32p4/src/uhci0/int_st.rs @@ -0,0 +1,127 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `RX_START_INT_ST` reader - Indicates the interrupt status of UHCI_RX_START_INT."] +pub type RX_START_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_START_INT_ST` reader - Indicates the interrupt status of UHCI_TX_START_INT."] +pub type TX_START_INT_ST_R = crate::BitReader; +#[doc = "Field `RX_HUNG_INT_ST` reader - Indicates the interrupt status of UHCI_RX_HUNG_INT."] +pub type RX_HUNG_INT_ST_R = crate::BitReader; +#[doc = "Field `TX_HUNG_INT_ST` reader - Indicates the interrupt status of UHCI_TX_HUNG_INT."] +pub type TX_HUNG_INT_ST_R = crate::BitReader; +#[doc = "Field `SEND_S_REG_Q_INT_ST` reader - Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT."] +pub type SEND_S_REG_Q_INT_ST_R = crate::BitReader; +#[doc = "Field `SEND_A_REG_Q_INT_ST` reader - Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT."] +pub type SEND_A_REG_Q_INT_ST_R = crate::BitReader; +#[doc = "Field `OUTLINK_EOF_ERR_INT_ST` reader - Indicates the interrupt status of UHCI_OUT_EOF_INT."] +pub type OUTLINK_EOF_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `APP_CTRL0_INT_ST` reader - Indicates the interrupt status of UHCI_APP_CTRL0_INT."] +pub type APP_CTRL0_INT_ST_R = crate::BitReader; +#[doc = "Field `APP_CTRL1_INT_ST` reader - Indicates the interrupt status of UHCI_APP_CTRL1_INT."] +pub type APP_CTRL1_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates the interrupt status of UHCI_RX_START_INT."] + #[inline(always)] + pub fn rx_start_int_st(&self) -> RX_START_INT_ST_R { + RX_START_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the interrupt status of UHCI_TX_START_INT."] + #[inline(always)] + pub fn tx_start_int_st(&self) -> TX_START_INT_ST_R { + TX_START_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates the interrupt status of UHCI_RX_HUNG_INT."] + #[inline(always)] + pub fn rx_hung_int_st(&self) -> RX_HUNG_INT_ST_R { + RX_HUNG_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates the interrupt status of UHCI_TX_HUNG_INT."] + #[inline(always)] + pub fn tx_hung_int_st(&self) -> TX_HUNG_INT_ST_R { + TX_HUNG_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT."] + #[inline(always)] + pub fn send_s_reg_q_int_st(&self) -> SEND_S_REG_Q_INT_ST_R { + SEND_S_REG_Q_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT."] + #[inline(always)] + pub fn send_a_reg_q_int_st(&self) -> SEND_A_REG_Q_INT_ST_R { + SEND_A_REG_Q_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Indicates the interrupt status of UHCI_OUT_EOF_INT."] + #[inline(always)] + pub fn outlink_eof_err_int_st(&self) -> OUTLINK_EOF_ERR_INT_ST_R { + OUTLINK_EOF_ERR_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Indicates the interrupt status of UHCI_APP_CTRL0_INT."] + #[inline(always)] + pub fn app_ctrl0_int_st(&self) -> APP_CTRL0_INT_ST_R { + APP_CTRL0_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Indicates the interrupt status of UHCI_APP_CTRL1_INT."] + #[inline(always)] + pub fn app_ctrl1_int_st(&self) -> APP_CTRL1_INT_ST_R { + APP_CTRL1_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "rx_start_int_st", + &format_args!("{}", self.rx_start_int_st().bit()), + ) + .field( + "tx_start_int_st", + &format_args!("{}", self.tx_start_int_st().bit()), + ) + .field( + "rx_hung_int_st", + &format_args!("{}", self.rx_hung_int_st().bit()), + ) + .field( + "tx_hung_int_st", + &format_args!("{}", self.tx_hung_int_st().bit()), + ) + .field( + "send_s_reg_q_int_st", + &format_args!("{}", self.send_s_reg_q_int_st().bit()), + ) + .field( + "send_a_reg_q_int_st", + &format_args!("{}", self.send_a_reg_q_int_st().bit()), + ) + .field( + "outlink_eof_err_int_st", + &format_args!("{}", self.outlink_eof_err_int_st().bit()), + ) + .field( + "app_ctrl0_int_st", + &format_args!("{}", self.app_ctrl0_int_st().bit()), + ) + .field( + "app_ctrl1_int_st", + &format_args!("{}", self.app_ctrl1_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "UHCI Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/pkt_thres.rs b/esp32p4/src/uhci0/pkt_thres.rs new file mode 100644 index 0000000000..f56933a714 --- /dev/null +++ b/esp32p4/src/uhci0/pkt_thres.rs @@ -0,0 +1,63 @@ +#[doc = "Register `PKT_THRES` reader"] +pub type R = crate::R; +#[doc = "Register `PKT_THRES` writer"] +pub type W = crate::W; +#[doc = "Field `PKT_THRS` reader - Configures the data packet's maximum length when UHCI_HEAD_EN is 0."] +pub type PKT_THRS_R = crate::FieldReader; +#[doc = "Field `PKT_THRS` writer - Configures the data packet's maximum length when UHCI_HEAD_EN is 0."] +pub type PKT_THRS_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>; +impl R { + #[doc = "Bits 0:12 - Configures the data packet's maximum length when UHCI_HEAD_EN is 0."] + #[inline(always)] + pub fn pkt_thrs(&self) -> PKT_THRS_R { + PKT_THRS_R::new((self.bits & 0x1fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PKT_THRES") + .field("pkt_thrs", &format_args!("{}", self.pkt_thrs().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:12 - Configures the data packet's maximum length when UHCI_HEAD_EN is 0."] + #[inline(always)] + #[must_use] + pub fn pkt_thrs(&mut self) -> PKT_THRS_W { + PKT_THRS_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UCHI Packet Length Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pkt_thres::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pkt_thres::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PKT_THRES_SPEC; +impl crate::RegisterSpec for PKT_THRES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pkt_thres::R`](R) reader structure"] +impl crate::Readable for PKT_THRES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pkt_thres::W`](W) writer structure"] +impl crate::Writable for PKT_THRES_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PKT_THRES to value 0x80"] +impl crate::Resettable for PKT_THRES_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/esp32p4/src/uhci0/quick_sent.rs b/esp32p4/src/uhci0/quick_sent.rs new file mode 100644 index 0000000000..c293d6df1a --- /dev/null +++ b/esp32p4/src/uhci0/quick_sent.rs @@ -0,0 +1,112 @@ +#[doc = "Register `QUICK_SENT` reader"] +pub type R = crate::R; +#[doc = "Register `QUICK_SENT` writer"] +pub type W = crate::W; +#[doc = "Field `SINGLE_SEND_NUM` reader - Configures single_send mode."] +pub type SINGLE_SEND_NUM_R = crate::FieldReader; +#[doc = "Field `SINGLE_SEND_NUM` writer - Configures single_send mode."] +pub type SINGLE_SEND_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SINGLE_SEND_EN` writer - Set this bit to enable sending short packet with single_send mode."] +pub type SINGLE_SEND_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALWAYS_SEND_NUM` reader - Configures always_send mode."] +pub type ALWAYS_SEND_NUM_R = crate::FieldReader; +#[doc = "Field `ALWAYS_SEND_NUM` writer - Configures always_send mode."] +pub type ALWAYS_SEND_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `ALWAYS_SEND_EN` reader - Set this bit to enable sending short packet with always_send mode."] +pub type ALWAYS_SEND_EN_R = crate::BitReader; +#[doc = "Field `ALWAYS_SEND_EN` writer - Set this bit to enable sending short packet with always_send mode."] +pub type ALWAYS_SEND_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - Configures single_send mode."] + #[inline(always)] + pub fn single_send_num(&self) -> SINGLE_SEND_NUM_R { + SINGLE_SEND_NUM_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 4:6 - Configures always_send mode."] + #[inline(always)] + pub fn always_send_num(&self) -> ALWAYS_SEND_NUM_R { + ALWAYS_SEND_NUM_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - Set this bit to enable sending short packet with always_send mode."] + #[inline(always)] + pub fn always_send_en(&self) -> ALWAYS_SEND_EN_R { + ALWAYS_SEND_EN_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("QUICK_SENT") + .field( + "single_send_num", + &format_args!("{}", self.single_send_num().bits()), + ) + .field( + "always_send_num", + &format_args!("{}", self.always_send_num().bits()), + ) + .field( + "always_send_en", + &format_args!("{}", self.always_send_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:2 - Configures single_send mode."] + #[inline(always)] + #[must_use] + pub fn single_send_num(&mut self) -> SINGLE_SEND_NUM_W { + SINGLE_SEND_NUM_W::new(self, 0) + } + #[doc = "Bit 3 - Set this bit to enable sending short packet with single_send mode."] + #[inline(always)] + #[must_use] + pub fn single_send_en(&mut self) -> SINGLE_SEND_EN_W { + SINGLE_SEND_EN_W::new(self, 3) + } + #[doc = "Bits 4:6 - Configures always_send mode."] + #[inline(always)] + #[must_use] + pub fn always_send_num(&mut self) -> ALWAYS_SEND_NUM_W { + ALWAYS_SEND_NUM_W::new(self, 4) + } + #[doc = "Bit 7 - Set this bit to enable sending short packet with always_send mode."] + #[inline(always)] + #[must_use] + pub fn always_send_en(&mut self) -> ALWAYS_SEND_EN_W { + ALWAYS_SEND_EN_W::new(self, 7) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UCHI Quick send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`quick_sent::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`quick_sent::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QUICK_SENT_SPEC; +impl crate::RegisterSpec for QUICK_SENT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`quick_sent::R`](R) reader structure"] +impl crate::Readable for QUICK_SENT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`quick_sent::W`](W) writer structure"] +impl crate::Writable for QUICK_SENT_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets QUICK_SENT to value 0"] +impl crate::Resettable for QUICK_SENT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q0_word0.rs b/esp32p4/src/uhci0/reg_q0_word0.rs new file mode 100644 index 0000000000..0c4ab4443c --- /dev/null +++ b/esp32p4/src/uhci0/reg_q0_word0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q0_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q0_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q0_WORD0` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q0_WORD0_R = crate::FieldReader; +#[doc = "Field `SEND_Q0_WORD0` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q0_WORD0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q0_word0(&self) -> SEND_Q0_WORD0_R { + SEND_Q0_WORD0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q0_WORD0") + .field( + "send_q0_word0", + &format_args!("{}", self.send_q0_word0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q0_word0(&mut self) -> SEND_Q0_WORD0_W { + SEND_Q0_WORD0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q0_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q0_word0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q0_word0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q0_WORD0_SPEC; +impl crate::RegisterSpec for REG_Q0_WORD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q0_word0::R`](R) reader structure"] +impl crate::Readable for REG_Q0_WORD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q0_word0::W`](W) writer structure"] +impl crate::Writable for REG_Q0_WORD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q0_WORD0 to value 0"] +impl crate::Resettable for REG_Q0_WORD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q0_word1.rs b/esp32p4/src/uhci0/reg_q0_word1.rs new file mode 100644 index 0000000000..85229a690d --- /dev/null +++ b/esp32p4/src/uhci0/reg_q0_word1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q0_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q0_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q0_WORD1` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q0_WORD1_R = crate::FieldReader; +#[doc = "Field `SEND_Q0_WORD1` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q0_WORD1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q0_word1(&self) -> SEND_Q0_WORD1_R { + SEND_Q0_WORD1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q0_WORD1") + .field( + "send_q0_word1", + &format_args!("{}", self.send_q0_word1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q0_word1(&mut self) -> SEND_Q0_WORD1_W { + SEND_Q0_WORD1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q0_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q0_word1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q0_word1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q0_WORD1_SPEC; +impl crate::RegisterSpec for REG_Q0_WORD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q0_word1::R`](R) reader structure"] +impl crate::Readable for REG_Q0_WORD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q0_word1::W`](W) writer structure"] +impl crate::Writable for REG_Q0_WORD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q0_WORD1 to value 0"] +impl crate::Resettable for REG_Q0_WORD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q1_word0.rs b/esp32p4/src/uhci0/reg_q1_word0.rs new file mode 100644 index 0000000000..9677f9899c --- /dev/null +++ b/esp32p4/src/uhci0/reg_q1_word0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q1_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q1_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q1_WORD0` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q1_WORD0_R = crate::FieldReader; +#[doc = "Field `SEND_Q1_WORD0` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q1_WORD0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q1_word0(&self) -> SEND_Q1_WORD0_R { + SEND_Q1_WORD0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q1_WORD0") + .field( + "send_q1_word0", + &format_args!("{}", self.send_q1_word0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q1_word0(&mut self) -> SEND_Q1_WORD0_W { + SEND_Q1_WORD0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q1_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q1_word0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q1_word0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q1_WORD0_SPEC; +impl crate::RegisterSpec for REG_Q1_WORD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q1_word0::R`](R) reader structure"] +impl crate::Readable for REG_Q1_WORD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q1_word0::W`](W) writer structure"] +impl crate::Writable for REG_Q1_WORD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q1_WORD0 to value 0"] +impl crate::Resettable for REG_Q1_WORD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q1_word1.rs b/esp32p4/src/uhci0/reg_q1_word1.rs new file mode 100644 index 0000000000..186fe498f1 --- /dev/null +++ b/esp32p4/src/uhci0/reg_q1_word1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q1_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q1_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q1_WORD1` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q1_WORD1_R = crate::FieldReader; +#[doc = "Field `SEND_Q1_WORD1` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q1_WORD1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q1_word1(&self) -> SEND_Q1_WORD1_R { + SEND_Q1_WORD1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q1_WORD1") + .field( + "send_q1_word1", + &format_args!("{}", self.send_q1_word1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q1_word1(&mut self) -> SEND_Q1_WORD1_W { + SEND_Q1_WORD1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q1_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q1_word1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q1_word1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q1_WORD1_SPEC; +impl crate::RegisterSpec for REG_Q1_WORD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q1_word1::R`](R) reader structure"] +impl crate::Readable for REG_Q1_WORD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q1_word1::W`](W) writer structure"] +impl crate::Writable for REG_Q1_WORD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q1_WORD1 to value 0"] +impl crate::Resettable for REG_Q1_WORD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q2_word0.rs b/esp32p4/src/uhci0/reg_q2_word0.rs new file mode 100644 index 0000000000..cfbd41f79a --- /dev/null +++ b/esp32p4/src/uhci0/reg_q2_word0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q2_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q2_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q2_WORD0` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q2_WORD0_R = crate::FieldReader; +#[doc = "Field `SEND_Q2_WORD0` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q2_WORD0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q2_word0(&self) -> SEND_Q2_WORD0_R { + SEND_Q2_WORD0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q2_WORD0") + .field( + "send_q2_word0", + &format_args!("{}", self.send_q2_word0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q2_word0(&mut self) -> SEND_Q2_WORD0_W { + SEND_Q2_WORD0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q2_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q2_word0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q2_word0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q2_WORD0_SPEC; +impl crate::RegisterSpec for REG_Q2_WORD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q2_word0::R`](R) reader structure"] +impl crate::Readable for REG_Q2_WORD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q2_word0::W`](W) writer structure"] +impl crate::Writable for REG_Q2_WORD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q2_WORD0 to value 0"] +impl crate::Resettable for REG_Q2_WORD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q2_word1.rs b/esp32p4/src/uhci0/reg_q2_word1.rs new file mode 100644 index 0000000000..623abae89c --- /dev/null +++ b/esp32p4/src/uhci0/reg_q2_word1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q2_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q2_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q2_WORD1` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q2_WORD1_R = crate::FieldReader; +#[doc = "Field `SEND_Q2_WORD1` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q2_WORD1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q2_word1(&self) -> SEND_Q2_WORD1_R { + SEND_Q2_WORD1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q2_WORD1") + .field( + "send_q2_word1", + &format_args!("{}", self.send_q2_word1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q2_word1(&mut self) -> SEND_Q2_WORD1_W { + SEND_Q2_WORD1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q2_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q2_word1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q2_word1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q2_WORD1_SPEC; +impl crate::RegisterSpec for REG_Q2_WORD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q2_word1::R`](R) reader structure"] +impl crate::Readable for REG_Q2_WORD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q2_word1::W`](W) writer structure"] +impl crate::Writable for REG_Q2_WORD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q2_WORD1 to value 0"] +impl crate::Resettable for REG_Q2_WORD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q3_word0.rs b/esp32p4/src/uhci0/reg_q3_word0.rs new file mode 100644 index 0000000000..ee548ed07b --- /dev/null +++ b/esp32p4/src/uhci0/reg_q3_word0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q3_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q3_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q3_WORD0` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q3_WORD0_R = crate::FieldReader; +#[doc = "Field `SEND_Q3_WORD0` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q3_WORD0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q3_word0(&self) -> SEND_Q3_WORD0_R { + SEND_Q3_WORD0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q3_WORD0") + .field( + "send_q3_word0", + &format_args!("{}", self.send_q3_word0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q3_word0(&mut self) -> SEND_Q3_WORD0_W { + SEND_Q3_WORD0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q3_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q3_word0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q3_word0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q3_WORD0_SPEC; +impl crate::RegisterSpec for REG_Q3_WORD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q3_word0::R`](R) reader structure"] +impl crate::Readable for REG_Q3_WORD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q3_word0::W`](W) writer structure"] +impl crate::Writable for REG_Q3_WORD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q3_WORD0 to value 0"] +impl crate::Resettable for REG_Q3_WORD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q3_word1.rs b/esp32p4/src/uhci0/reg_q3_word1.rs new file mode 100644 index 0000000000..053d9ee790 --- /dev/null +++ b/esp32p4/src/uhci0/reg_q3_word1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q3_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q3_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q3_WORD1` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q3_WORD1_R = crate::FieldReader; +#[doc = "Field `SEND_Q3_WORD1` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q3_WORD1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q3_word1(&self) -> SEND_Q3_WORD1_R { + SEND_Q3_WORD1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q3_WORD1") + .field( + "send_q3_word1", + &format_args!("{}", self.send_q3_word1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q3_word1(&mut self) -> SEND_Q3_WORD1_W { + SEND_Q3_WORD1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q3_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q3_word1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q3_word1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q3_WORD1_SPEC; +impl crate::RegisterSpec for REG_Q3_WORD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q3_word1::R`](R) reader structure"] +impl crate::Readable for REG_Q3_WORD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q3_word1::W`](W) writer structure"] +impl crate::Writable for REG_Q3_WORD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q3_WORD1 to value 0"] +impl crate::Resettable for REG_Q3_WORD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q4_word0.rs b/esp32p4/src/uhci0/reg_q4_word0.rs new file mode 100644 index 0000000000..15771df379 --- /dev/null +++ b/esp32p4/src/uhci0/reg_q4_word0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q4_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q4_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q4_WORD0` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q4_WORD0_R = crate::FieldReader; +#[doc = "Field `SEND_Q4_WORD0` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q4_WORD0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q4_word0(&self) -> SEND_Q4_WORD0_R { + SEND_Q4_WORD0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q4_WORD0") + .field( + "send_q4_word0", + &format_args!("{}", self.send_q4_word0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q4_word0(&mut self) -> SEND_Q4_WORD0_W { + SEND_Q4_WORD0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q4_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q4_word0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q4_word0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q4_WORD0_SPEC; +impl crate::RegisterSpec for REG_Q4_WORD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q4_word0::R`](R) reader structure"] +impl crate::Readable for REG_Q4_WORD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q4_word0::W`](W) writer structure"] +impl crate::Writable for REG_Q4_WORD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q4_WORD0 to value 0"] +impl crate::Resettable for REG_Q4_WORD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q4_word1.rs b/esp32p4/src/uhci0/reg_q4_word1.rs new file mode 100644 index 0000000000..0f376f8b67 --- /dev/null +++ b/esp32p4/src/uhci0/reg_q4_word1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q4_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q4_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q4_WORD1` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q4_WORD1_R = crate::FieldReader; +#[doc = "Field `SEND_Q4_WORD1` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q4_WORD1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q4_word1(&self) -> SEND_Q4_WORD1_R { + SEND_Q4_WORD1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q4_WORD1") + .field( + "send_q4_word1", + &format_args!("{}", self.send_q4_word1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q4_word1(&mut self) -> SEND_Q4_WORD1_W { + SEND_Q4_WORD1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q4_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q4_word1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q4_word1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q4_WORD1_SPEC; +impl crate::RegisterSpec for REG_Q4_WORD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q4_word1::R`](R) reader structure"] +impl crate::Readable for REG_Q4_WORD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q4_word1::W`](W) writer structure"] +impl crate::Writable for REG_Q4_WORD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q4_WORD1 to value 0"] +impl crate::Resettable for REG_Q4_WORD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q5_word0.rs b/esp32p4/src/uhci0/reg_q5_word0.rs new file mode 100644 index 0000000000..3e63abe4b0 --- /dev/null +++ b/esp32p4/src/uhci0/reg_q5_word0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q5_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q5_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q5_WORD0` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q5_WORD0_R = crate::FieldReader; +#[doc = "Field `SEND_Q5_WORD0` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q5_WORD0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q5_word0(&self) -> SEND_Q5_WORD0_R { + SEND_Q5_WORD0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q5_WORD0") + .field( + "send_q5_word0", + &format_args!("{}", self.send_q5_word0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q5_word0(&mut self) -> SEND_Q5_WORD0_W { + SEND_Q5_WORD0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q5_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q5_word0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q5_word0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q5_WORD0_SPEC; +impl crate::RegisterSpec for REG_Q5_WORD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q5_word0::R`](R) reader structure"] +impl crate::Readable for REG_Q5_WORD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q5_word0::W`](W) writer structure"] +impl crate::Writable for REG_Q5_WORD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q5_WORD0 to value 0"] +impl crate::Resettable for REG_Q5_WORD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q5_word1.rs b/esp32p4/src/uhci0/reg_q5_word1.rs new file mode 100644 index 0000000000..4a4770d660 --- /dev/null +++ b/esp32p4/src/uhci0/reg_q5_word1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q5_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q5_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q5_WORD1` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q5_WORD1_R = crate::FieldReader; +#[doc = "Field `SEND_Q5_WORD1` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q5_WORD1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q5_word1(&self) -> SEND_Q5_WORD1_R { + SEND_Q5_WORD1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q5_WORD1") + .field( + "send_q5_word1", + &format_args!("{}", self.send_q5_word1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q5_word1(&mut self) -> SEND_Q5_WORD1_W { + SEND_Q5_WORD1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q5_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q5_word1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q5_word1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q5_WORD1_SPEC; +impl crate::RegisterSpec for REG_Q5_WORD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q5_word1::R`](R) reader structure"] +impl crate::Readable for REG_Q5_WORD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q5_word1::W`](W) writer structure"] +impl crate::Writable for REG_Q5_WORD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q5_WORD1 to value 0"] +impl crate::Resettable for REG_Q5_WORD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q6_word0.rs b/esp32p4/src/uhci0/reg_q6_word0.rs new file mode 100644 index 0000000000..6ffbce7497 --- /dev/null +++ b/esp32p4/src/uhci0/reg_q6_word0.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q6_WORD0` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q6_WORD0` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q6_WORD0` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q6_WORD0_R = crate::FieldReader; +#[doc = "Field `SEND_Q6_WORD0` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q6_WORD0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q6_word0(&self) -> SEND_Q6_WORD0_R { + SEND_Q6_WORD0_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q6_WORD0") + .field( + "send_q6_word0", + &format_args!("{}", self.send_q6_word0().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q6_word0(&mut self) -> SEND_Q6_WORD0_W { + SEND_Q6_WORD0_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q6_WORD0 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q6_word0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q6_word0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q6_WORD0_SPEC; +impl crate::RegisterSpec for REG_Q6_WORD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q6_word0::R`](R) reader structure"] +impl crate::Readable for REG_Q6_WORD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q6_word0::W`](W) writer structure"] +impl crate::Writable for REG_Q6_WORD0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q6_WORD0 to value 0"] +impl crate::Resettable for REG_Q6_WORD0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/reg_q6_word1.rs b/esp32p4/src/uhci0/reg_q6_word1.rs new file mode 100644 index 0000000000..587720f040 --- /dev/null +++ b/esp32p4/src/uhci0/reg_q6_word1.rs @@ -0,0 +1,66 @@ +#[doc = "Register `REG_Q6_WORD1` reader"] +pub type R = crate::R; +#[doc = "Register `REG_Q6_WORD1` writer"] +pub type W = crate::W; +#[doc = "Field `SEND_Q6_WORD1` reader - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q6_WORD1_R = crate::FieldReader; +#[doc = "Field `SEND_Q6_WORD1` writer - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] +pub type SEND_Q6_WORD1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + pub fn send_q6_word1(&self) -> SEND_Q6_WORD1_R { + SEND_Q6_WORD1_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("REG_Q6_WORD1") + .field( + "send_q6_word1", + &format_args!("{}", self.send_q6_word1().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."] + #[inline(always)] + #[must_use] + pub fn send_q6_word1(&mut self) -> SEND_Q6_WORD1_W { + SEND_Q6_WORD1_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "UHCI Q6_WORD1 Quick Send Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reg_q6_word1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reg_q6_word1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REG_Q6_WORD1_SPEC; +impl crate::RegisterSpec for REG_Q6_WORD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reg_q6_word1::R`](R) reader structure"] +impl crate::Readable for REG_Q6_WORD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reg_q6_word1::W`](W) writer structure"] +impl crate::Writable for REG_Q6_WORD1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REG_Q6_WORD1 to value 0"] +impl crate::Resettable for REG_Q6_WORD1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/rx_head.rs b/esp32p4/src/uhci0/rx_head.rs new file mode 100644 index 0000000000..669d3b3f2f --- /dev/null +++ b/esp32p4/src/uhci0/rx_head.rs @@ -0,0 +1,36 @@ +#[doc = "Register `RX_HEAD` reader"] +pub type R = crate::R; +#[doc = "Field `RX_HEAD` reader - Stores the head of received packet."] +pub type RX_HEAD_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Stores the head of received packet."] + #[inline(always)] + pub fn rx_head(&self) -> RX_HEAD_R { + RX_HEAD_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RX_HEAD") + .field("rx_head", &format_args!("{}", self.rx_head().bits())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "UHCI Head Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_head::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RX_HEAD_SPEC; +impl crate::RegisterSpec for RX_HEAD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx_head::R`](R) reader structure"] +impl crate::Readable for RX_HEAD_SPEC {} +#[doc = "`reset()` method sets RX_HEAD to value 0"] +impl crate::Resettable for RX_HEAD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/state0.rs b/esp32p4/src/uhci0/state0.rs new file mode 100644 index 0000000000..794e07f4cd --- /dev/null +++ b/esp32p4/src/uhci0/state0.rs @@ -0,0 +1,50 @@ +#[doc = "Register `STATE0` reader"] +pub type R = crate::R; +#[doc = "Field `RX_ERR_CAUSE` reader - Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is not found, but received packet is completed. 3'b110: CRC check error."] +pub type RX_ERR_CAUSE_R = crate::FieldReader; +#[doc = "Field `DECODE_STATE` reader - Indicates UHCI decoder status."] +pub type DECODE_STATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is not found, but received packet is completed. 3'b110: CRC check error."] + #[inline(always)] + pub fn rx_err_cause(&self) -> RX_ERR_CAUSE_R { + RX_ERR_CAUSE_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Indicates UHCI decoder status."] + #[inline(always)] + pub fn decode_state(&self) -> DECODE_STATE_R { + DECODE_STATE_R::new(((self.bits >> 3) & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATE0") + .field( + "rx_err_cause", + &format_args!("{}", self.rx_err_cause().bits()), + ) + .field( + "decode_state", + &format_args!("{}", self.decode_state().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "UHCI Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATE0_SPEC; +impl crate::RegisterSpec for STATE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`state0::R`](R) reader structure"] +impl crate::Readable for STATE0_SPEC {} +#[doc = "`reset()` method sets STATE0 to value 0"] +impl crate::Resettable for STATE0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/uhci0/state1.rs b/esp32p4/src/uhci0/state1.rs new file mode 100644 index 0000000000..3ef15a04b3 --- /dev/null +++ b/esp32p4/src/uhci0/state1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `STATE1` reader"] +pub type R = crate::R; +#[doc = "Field `ENCODE_STATE` reader - Indicates UHCI encoder status."] +pub type ENCODE_STATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Indicates UHCI encoder status."] + #[inline(always)] + pub fn encode_state(&self) -> ENCODE_STATE_R { + ENCODE_STATE_R::new((self.bits & 7) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("STATE1") + .field( + "encode_state", + &format_args!("{}", self.encode_state().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "UHCI Transmit Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATE1_SPEC; +impl crate::RegisterSpec for STATE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`state1::R`](R) reader structure"] +impl crate::Readable for STATE1_SPEC {} +#[doc = "`reset()` method sets STATE1 to value 0"] +impl crate::Resettable for STATE1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device.rs b/esp32p4/src/usb_device.rs new file mode 100644 index 0000000000..5b12ab4269 --- /dev/null +++ b/esp32p4/src/usb_device.rs @@ -0,0 +1,357 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + ep1: EP1, + ep1_conf: EP1_CONF, + int_raw: INT_RAW, + int_st: INT_ST, + int_ena: INT_ENA, + int_clr: INT_CLR, + conf0: CONF0, + test: TEST, + jfifo_st: JFIFO_ST, + fram_num: FRAM_NUM, + in_ep0_st: IN_EP0_ST, + in_ep1_st: IN_EP1_ST, + in_ep2_st: IN_EP2_ST, + in_ep3_st: IN_EP3_ST, + out_ep0_st: OUT_EP0_ST, + out_ep1_st: OUT_EP1_ST, + out_ep2_st: OUT_EP2_ST, + misc_conf: MISC_CONF, + mem_conf: MEM_CONF, + chip_rst: CHIP_RST, + set_line_code_w0: SET_LINE_CODE_W0, + set_line_code_w1: SET_LINE_CODE_W1, + get_line_code_w0: GET_LINE_CODE_W0, + get_line_code_w1: GET_LINE_CODE_W1, + config_update: CONFIG_UPDATE, + ser_afifo_config: SER_AFIFO_CONFIG, + bus_reset_st: BUS_RESET_ST, + eco_low_48: ECO_LOW_48, + eco_high_48: ECO_HIGH_48, + eco_cell_ctrl_48: ECO_CELL_CTRL_48, + eco_low_apb: ECO_LOW_APB, + eco_high_apb: ECO_HIGH_APB, + eco_cell_ctrl_apb: ECO_CELL_CTRL_APB, + sram_ctrl: SRAM_CTRL, + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - FIFO access for the CDC-ACM data IN and OUT endpoints."] + #[inline(always)] + pub const fn ep1(&self) -> &EP1 { + &self.ep1 + } + #[doc = "0x04 - Configuration and control registers for the CDC-ACM FIFOs."] + #[inline(always)] + pub const fn ep1_conf(&self) -> &EP1_CONF { + &self.ep1_conf + } + #[doc = "0x08 - Interrupt raw status register."] + #[inline(always)] + pub const fn int_raw(&self) -> &INT_RAW { + &self.int_raw + } + #[doc = "0x0c - Interrupt status register."] + #[inline(always)] + pub const fn int_st(&self) -> &INT_ST { + &self.int_st + } + #[doc = "0x10 - Interrupt enable status register."] + #[inline(always)] + pub const fn int_ena(&self) -> &INT_ENA { + &self.int_ena + } + #[doc = "0x14 - Interrupt clear status register."] + #[inline(always)] + pub const fn int_clr(&self) -> &INT_CLR { + &self.int_clr + } + #[doc = "0x18 - PHY hardware configuration."] + #[inline(always)] + pub const fn conf0(&self) -> &CONF0 { + &self.conf0 + } + #[doc = "0x1c - Registers used for debugging the PHY."] + #[inline(always)] + pub const fn test(&self) -> &TEST { + &self.test + } + #[doc = "0x20 - JTAG FIFO status and control registers."] + #[inline(always)] + pub const fn jfifo_st(&self) -> &JFIFO_ST { + &self.jfifo_st + } + #[doc = "0x24 - Last received SOF frame index register."] + #[inline(always)] + pub const fn fram_num(&self) -> &FRAM_NUM { + &self.fram_num + } + #[doc = "0x28 - Control IN endpoint status information."] + #[inline(always)] + pub const fn in_ep0_st(&self) -> &IN_EP0_ST { + &self.in_ep0_st + } + #[doc = "0x2c - CDC-ACM IN endpoint status information."] + #[inline(always)] + pub const fn in_ep1_st(&self) -> &IN_EP1_ST { + &self.in_ep1_st + } + #[doc = "0x30 - CDC-ACM interrupt IN endpoint status information."] + #[inline(always)] + pub const fn in_ep2_st(&self) -> &IN_EP2_ST { + &self.in_ep2_st + } + #[doc = "0x34 - JTAG IN endpoint status information."] + #[inline(always)] + pub const fn in_ep3_st(&self) -> &IN_EP3_ST { + &self.in_ep3_st + } + #[doc = "0x38 - Control OUT endpoint status information."] + #[inline(always)] + pub const fn out_ep0_st(&self) -> &OUT_EP0_ST { + &self.out_ep0_st + } + #[doc = "0x3c - CDC-ACM OUT endpoint status information."] + #[inline(always)] + pub const fn out_ep1_st(&self) -> &OUT_EP1_ST { + &self.out_ep1_st + } + #[doc = "0x40 - JTAG OUT endpoint status information."] + #[inline(always)] + pub const fn out_ep2_st(&self) -> &OUT_EP2_ST { + &self.out_ep2_st + } + #[doc = "0x44 - Clock enable control"] + #[inline(always)] + pub const fn misc_conf(&self) -> &MISC_CONF { + &self.misc_conf + } + #[doc = "0x48 - Memory power control"] + #[inline(always)] + pub const fn mem_conf(&self) -> &MEM_CONF { + &self.mem_conf + } + #[doc = "0x4c - CDC-ACM chip reset control."] + #[inline(always)] + pub const fn chip_rst(&self) -> &CHIP_RST { + &self.chip_rst + } + #[doc = "0x50 - W0 of SET_LINE_CODING command."] + #[inline(always)] + pub const fn set_line_code_w0(&self) -> &SET_LINE_CODE_W0 { + &self.set_line_code_w0 + } + #[doc = "0x54 - W1 of SET_LINE_CODING command."] + #[inline(always)] + pub const fn set_line_code_w1(&self) -> &SET_LINE_CODE_W1 { + &self.set_line_code_w1 + } + #[doc = "0x58 - W0 of GET_LINE_CODING command."] + #[inline(always)] + pub const fn get_line_code_w0(&self) -> &GET_LINE_CODE_W0 { + &self.get_line_code_w0 + } + #[doc = "0x5c - W1 of GET_LINE_CODING command."] + #[inline(always)] + pub const fn get_line_code_w1(&self) -> &GET_LINE_CODE_W1 { + &self.get_line_code_w1 + } + #[doc = "0x60 - Configuration registers' value update"] + #[inline(always)] + pub const fn config_update(&self) -> &CONFIG_UPDATE { + &self.config_update + } + #[doc = "0x64 - Serial AFIFO configure register"] + #[inline(always)] + pub const fn ser_afifo_config(&self) -> &SER_AFIFO_CONFIG { + &self.ser_afifo_config + } + #[doc = "0x68 - USB Bus reset status register"] + #[inline(always)] + pub const fn bus_reset_st(&self) -> &BUS_RESET_ST { + &self.bus_reset_st + } + #[doc = "0x6c - Reserved."] + #[inline(always)] + pub const fn eco_low_48(&self) -> &ECO_LOW_48 { + &self.eco_low_48 + } + #[doc = "0x70 - Reserved."] + #[inline(always)] + pub const fn eco_high_48(&self) -> &ECO_HIGH_48 { + &self.eco_high_48 + } + #[doc = "0x74 - Reserved."] + #[inline(always)] + pub const fn eco_cell_ctrl_48(&self) -> &ECO_CELL_CTRL_48 { + &self.eco_cell_ctrl_48 + } + #[doc = "0x78 - Reserved."] + #[inline(always)] + pub const fn eco_low_apb(&self) -> &ECO_LOW_APB { + &self.eco_low_apb + } + #[doc = "0x7c - Reserved."] + #[inline(always)] + pub const fn eco_high_apb(&self) -> &ECO_HIGH_APB { + &self.eco_high_apb + } + #[doc = "0x80 - Reserved."] + #[inline(always)] + pub const fn eco_cell_ctrl_apb(&self) -> &ECO_CELL_CTRL_APB { + &self.eco_cell_ctrl_apb + } + #[doc = "0x84 - PPA SRAM Control Register"] + #[inline(always)] + pub const fn sram_ctrl(&self) -> &SRAM_CTRL { + &self.sram_ctrl + } + #[doc = "0x88 - Date register"] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "EP1 (r) register accessor: FIFO access for the CDC-ACM data IN and OUT endpoints.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ep1`] module"] +pub type EP1 = crate::Reg; +#[doc = "FIFO access for the CDC-ACM data IN and OUT endpoints."] +pub mod ep1; +#[doc = "EP1_CONF (rw) register accessor: Configuration and control registers for the CDC-ACM FIFOs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep1_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep1_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ep1_conf`] module"] +pub type EP1_CONF = crate::Reg; +#[doc = "Configuration and control registers for the CDC-ACM FIFOs."] +pub mod ep1_conf; +#[doc = "INT_RAW (rw) register accessor: Interrupt raw status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"] +pub type INT_RAW = crate::Reg; +#[doc = "Interrupt raw status register."] +pub mod int_raw; +#[doc = "INT_ST (r) register accessor: Interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"] +pub type INT_ST = crate::Reg; +#[doc = "Interrupt status register."] +pub mod int_st; +#[doc = "INT_ENA (rw) register accessor: Interrupt enable status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"] +pub type INT_ENA = crate::Reg; +#[doc = "Interrupt enable status register."] +pub mod int_ena; +#[doc = "INT_CLR (w) register accessor: Interrupt clear status register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"] +pub type INT_CLR = crate::Reg; +#[doc = "Interrupt clear status register."] +pub mod int_clr; +#[doc = "CONF0 (rw) register accessor: PHY hardware configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf0`] module"] +pub type CONF0 = crate::Reg; +#[doc = "PHY hardware configuration."] +pub mod conf0; +#[doc = "TEST (rw) register accessor: Registers used for debugging the PHY.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`test::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`test::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@test`] module"] +pub type TEST = crate::Reg; +#[doc = "Registers used for debugging the PHY."] +pub mod test; +#[doc = "JFIFO_ST (rw) register accessor: JTAG FIFO status and control registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`jfifo_st::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`jfifo_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jfifo_st`] module"] +pub type JFIFO_ST = crate::Reg; +#[doc = "JTAG FIFO status and control registers."] +pub mod jfifo_st; +#[doc = "FRAM_NUM (r) register accessor: Last received SOF frame index register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fram_num::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fram_num`] module"] +pub type FRAM_NUM = crate::Reg; +#[doc = "Last received SOF frame index register."] +pub mod fram_num; +#[doc = "IN_EP0_ST (r) register accessor: Control IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep0_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_ep0_st`] module"] +pub type IN_EP0_ST = crate::Reg; +#[doc = "Control IN endpoint status information."] +pub mod in_ep0_st; +#[doc = "IN_EP1_ST (r) register accessor: CDC-ACM IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep1_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_ep1_st`] module"] +pub type IN_EP1_ST = crate::Reg; +#[doc = "CDC-ACM IN endpoint status information."] +pub mod in_ep1_st; +#[doc = "IN_EP2_ST (r) register accessor: CDC-ACM interrupt IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep2_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_ep2_st`] module"] +pub type IN_EP2_ST = crate::Reg; +#[doc = "CDC-ACM interrupt IN endpoint status information."] +pub mod in_ep2_st; +#[doc = "IN_EP3_ST (r) register accessor: JTAG IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep3_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_ep3_st`] module"] +pub type IN_EP3_ST = crate::Reg; +#[doc = "JTAG IN endpoint status information."] +pub mod in_ep3_st; +#[doc = "OUT_EP0_ST (r) register accessor: Control OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep0_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_ep0_st`] module"] +pub type OUT_EP0_ST = crate::Reg; +#[doc = "Control OUT endpoint status information."] +pub mod out_ep0_st; +#[doc = "OUT_EP1_ST (r) register accessor: CDC-ACM OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep1_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_ep1_st`] module"] +pub type OUT_EP1_ST = crate::Reg; +#[doc = "CDC-ACM OUT endpoint status information."] +pub mod out_ep1_st; +#[doc = "OUT_EP2_ST (r) register accessor: JTAG OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep2_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_ep2_st`] module"] +pub type OUT_EP2_ST = crate::Reg; +#[doc = "JTAG OUT endpoint status information."] +pub mod out_ep2_st; +#[doc = "MISC_CONF (rw) register accessor: Clock enable control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`misc_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`misc_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc_conf`] module"] +pub type MISC_CONF = crate::Reg; +#[doc = "Clock enable control"] +pub mod misc_conf; +#[doc = "MEM_CONF (rw) register accessor: Memory power control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_conf`] module"] +pub type MEM_CONF = crate::Reg; +#[doc = "Memory power control"] +pub mod mem_conf; +#[doc = "CHIP_RST (rw) register accessor: CDC-ACM chip reset control.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chip_rst::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chip_rst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chip_rst`] module"] +pub type CHIP_RST = crate::Reg; +#[doc = "CDC-ACM chip reset control."] +pub mod chip_rst; +#[doc = "SET_LINE_CODE_W0 (r) register accessor: W0 of SET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set_line_code_w0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_line_code_w0`] module"] +pub type SET_LINE_CODE_W0 = crate::Reg; +#[doc = "W0 of SET_LINE_CODING command."] +pub mod set_line_code_w0; +#[doc = "SET_LINE_CODE_W1 (r) register accessor: W1 of SET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set_line_code_w1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set_line_code_w1`] module"] +pub type SET_LINE_CODE_W1 = crate::Reg; +#[doc = "W1 of SET_LINE_CODING command."] +pub mod set_line_code_w1; +#[doc = "GET_LINE_CODE_W0 (rw) register accessor: W0 of GET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`get_line_code_w0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`get_line_code_w0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@get_line_code_w0`] module"] +pub type GET_LINE_CODE_W0 = crate::Reg; +#[doc = "W0 of GET_LINE_CODING command."] +pub mod get_line_code_w0; +#[doc = "GET_LINE_CODE_W1 (rw) register accessor: W1 of GET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`get_line_code_w1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`get_line_code_w1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@get_line_code_w1`] module"] +pub type GET_LINE_CODE_W1 = crate::Reg; +#[doc = "W1 of GET_LINE_CODING command."] +pub mod get_line_code_w1; +#[doc = "CONFIG_UPDATE (w) register accessor: Configuration registers' value update\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config_update::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config_update`] module"] +pub type CONFIG_UPDATE = crate::Reg; +#[doc = "Configuration registers' value update"] +pub mod config_update; +#[doc = "SER_AFIFO_CONFIG (rw) register accessor: Serial AFIFO configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ser_afifo_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ser_afifo_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ser_afifo_config`] module"] +pub type SER_AFIFO_CONFIG = crate::Reg; +#[doc = "Serial AFIFO configure register"] +pub mod ser_afifo_config; +#[doc = "BUS_RESET_ST (r) register accessor: USB Bus reset status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_reset_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_reset_st`] module"] +pub type BUS_RESET_ST = crate::Reg; +#[doc = "USB Bus reset status register"] +pub mod bus_reset_st; +#[doc = "ECO_LOW_48 (rw) register accessor: Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_low_48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_low_48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_low_48`] module"] +pub type ECO_LOW_48 = crate::Reg; +#[doc = "Reserved."] +pub mod eco_low_48; +#[doc = "ECO_HIGH_48 (rw) register accessor: Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_high_48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_high_48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_high_48`] module"] +pub type ECO_HIGH_48 = crate::Reg; +#[doc = "Reserved."] +pub mod eco_high_48; +#[doc = "ECO_CELL_CTRL_48 (rw) register accessor: Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_cell_ctrl_48::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_cell_ctrl_48::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_cell_ctrl_48`] module"] +pub type ECO_CELL_CTRL_48 = crate::Reg; +#[doc = "Reserved."] +pub mod eco_cell_ctrl_48; +#[doc = "ECO_LOW_APB (rw) register accessor: Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_low_apb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_low_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_low_apb`] module"] +pub type ECO_LOW_APB = crate::Reg; +#[doc = "Reserved."] +pub mod eco_low_apb; +#[doc = "ECO_HIGH_APB (rw) register accessor: Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_high_apb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_high_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_high_apb`] module"] +pub type ECO_HIGH_APB = crate::Reg; +#[doc = "Reserved."] +pub mod eco_high_apb; +#[doc = "ECO_CELL_CTRL_APB (rw) register accessor: Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_cell_ctrl_apb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_cell_ctrl_apb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eco_cell_ctrl_apb`] module"] +pub type ECO_CELL_CTRL_APB = crate::Reg; +#[doc = "Reserved."] +pub mod eco_cell_ctrl_apb; +#[doc = "SRAM_CTRL (rw) register accessor: PPA SRAM Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sram_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ctrl`] module"] +pub type SRAM_CTRL = crate::Reg; +#[doc = "PPA SRAM Control Register"] +pub mod sram_ctrl; +#[doc = "DATE (rw) register accessor: Date register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Date register"] +pub mod date; diff --git a/esp32p4/src/usb_device/bus_reset_st.rs b/esp32p4/src/usb_device/bus_reset_st.rs new file mode 100644 index 0000000000..93abacb3da --- /dev/null +++ b/esp32p4/src/usb_device/bus_reset_st.rs @@ -0,0 +1,39 @@ +#[doc = "Register `BUS_RESET_ST` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_USB_BUS_RESET_ST` reader - USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released."] +pub type USB_SERIAL_JTAG_USB_BUS_RESET_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released."] + #[inline(always)] + pub fn usb_serial_jtag_usb_bus_reset_st(&self) -> USB_SERIAL_JTAG_USB_BUS_RESET_ST_R { + USB_SERIAL_JTAG_USB_BUS_RESET_ST_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUS_RESET_ST") + .field( + "usb_serial_jtag_usb_bus_reset_st", + &format_args!("{}", self.usb_serial_jtag_usb_bus_reset_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "USB Bus reset status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_reset_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUS_RESET_ST_SPEC; +impl crate::RegisterSpec for BUS_RESET_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bus_reset_st::R`](R) reader structure"] +impl crate::Readable for BUS_RESET_ST_SPEC {} +#[doc = "`reset()` method sets BUS_RESET_ST to value 0x01"] +impl crate::Resettable for BUS_RESET_ST_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/usb_device/chip_rst.rs b/esp32p4/src/usb_device/chip_rst.rs new file mode 100644 index 0000000000..3cddd15161 --- /dev/null +++ b/esp32p4/src/usb_device/chip_rst.rs @@ -0,0 +1,90 @@ +#[doc = "Register `CHIP_RST` reader"] +pub type R = crate::R; +#[doc = "Register `CHIP_RST` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_RTS` reader - 1: Chip reset is detected from usb serial channel. Software write 1 to clear it."] +pub type USB_SERIAL_JTAG_RTS_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_DTR` reader - 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it."] +pub type USB_SERIAL_JTAG_DTR_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS` reader - Set this bit to disable chip reset from usb serial channel to reset chip."] +pub type USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS` writer - Set this bit to disable chip reset from usb serial channel to reset chip."] +pub type USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: Chip reset is detected from usb serial channel. Software write 1 to clear it."] + #[inline(always)] + pub fn usb_serial_jtag_rts(&self) -> USB_SERIAL_JTAG_RTS_R { + USB_SERIAL_JTAG_RTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it."] + #[inline(always)] + pub fn usb_serial_jtag_dtr(&self) -> USB_SERIAL_JTAG_DTR_R { + USB_SERIAL_JTAG_DTR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set this bit to disable chip reset from usb serial channel to reset chip."] + #[inline(always)] + pub fn usb_serial_jtag_usb_uart_chip_rst_dis(&self) -> USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_R { + USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CHIP_RST") + .field( + "usb_serial_jtag_rts", + &format_args!("{}", self.usb_serial_jtag_rts().bit()), + ) + .field( + "usb_serial_jtag_dtr", + &format_args!("{}", self.usb_serial_jtag_dtr().bit()), + ) + .field( + "usb_serial_jtag_usb_uart_chip_rst_dis", + &format_args!("{}", self.usb_serial_jtag_usb_uart_chip_rst_dis().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 2 - Set this bit to disable chip reset from usb serial channel to reset chip."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_usb_uart_chip_rst_dis( + &mut self, + ) -> USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_W { + USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_W::new(self, 2) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "CDC-ACM chip reset control.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chip_rst::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chip_rst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHIP_RST_SPEC; +impl crate::RegisterSpec for CHIP_RST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chip_rst::R`](R) reader structure"] +impl crate::Readable for CHIP_RST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chip_rst::W`](W) writer structure"] +impl crate::Writable for CHIP_RST_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CHIP_RST to value 0"] +impl crate::Resettable for CHIP_RST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/conf0.rs b/esp32p4/src/usb_device/conf0.rs new file mode 100644 index 0000000000..dcf5950b7c --- /dev/null +++ b/esp32p4/src/usb_device/conf0.rs @@ -0,0 +1,321 @@ +#[doc = "Register `CONF0` reader"] +pub type R = crate::R; +#[doc = "Register `CONF0` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_PHY_SEL` reader - Select internal/external PHY"] +pub type USB_SERIAL_JTAG_PHY_SEL_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_PHY_SEL` writer - Select internal/external PHY"] +pub type USB_SERIAL_JTAG_PHY_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE` reader - Enable software control USB D+ D- exchange"] +pub type USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE` writer - Enable software control USB D+ D- exchange"] +pub type USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_EXCHG_PINS` reader - USB D+ D- exchange"] +pub type USB_SERIAL_JTAG_EXCHG_PINS_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_EXCHG_PINS` writer - USB D+ D- exchange"] +pub type USB_SERIAL_JTAG_EXCHG_PINS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_VREFH` reader - Control single-end input high threshold,1.76V to 2V, step 80mV"] +pub type USB_SERIAL_JTAG_VREFH_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_VREFH` writer - Control single-end input high threshold,1.76V to 2V, step 80mV"] +pub type USB_SERIAL_JTAG_VREFH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `USB_SERIAL_JTAG_VREFL` reader - Control single-end input low threshold,0.8V to 1.04V, step 80mV"] +pub type USB_SERIAL_JTAG_VREFL_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_VREFL` writer - Control single-end input low threshold,0.8V to 1.04V, step 80mV"] +pub type USB_SERIAL_JTAG_VREFL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `USB_SERIAL_JTAG_VREF_OVERRIDE` reader - Enable software control input threshold"] +pub type USB_SERIAL_JTAG_VREF_OVERRIDE_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_VREF_OVERRIDE` writer - Enable software control input threshold"] +pub type USB_SERIAL_JTAG_VREF_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_PAD_PULL_OVERRIDE` reader - Enable software control USB D+ D- pullup pulldown"] +pub type USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_PAD_PULL_OVERRIDE` writer - Enable software control USB D+ D- pullup pulldown"] +pub type USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_DP_PULLUP` reader - Control USB D+ pull up."] +pub type USB_SERIAL_JTAG_DP_PULLUP_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_DP_PULLUP` writer - Control USB D+ pull up."] +pub type USB_SERIAL_JTAG_DP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_DP_PULLDOWN` reader - Control USB D+ pull down."] +pub type USB_SERIAL_JTAG_DP_PULLDOWN_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_DP_PULLDOWN` writer - Control USB D+ pull down."] +pub type USB_SERIAL_JTAG_DP_PULLDOWN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_DM_PULLUP` reader - Control USB D- pull up."] +pub type USB_SERIAL_JTAG_DM_PULLUP_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_DM_PULLUP` writer - Control USB D- pull up."] +pub type USB_SERIAL_JTAG_DM_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_DM_PULLDOWN` reader - Control USB D- pull down."] +pub type USB_SERIAL_JTAG_DM_PULLDOWN_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_DM_PULLDOWN` writer - Control USB D- pull down."] +pub type USB_SERIAL_JTAG_DM_PULLDOWN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_PULLUP_VALUE` reader - Control pull up value."] +pub type USB_SERIAL_JTAG_PULLUP_VALUE_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_PULLUP_VALUE` writer - Control pull up value."] +pub type USB_SERIAL_JTAG_PULLUP_VALUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_USB_PAD_ENABLE` reader - Enable USB pad function."] +pub type USB_SERIAL_JTAG_USB_PAD_ENABLE_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_USB_PAD_ENABLE` writer - Enable USB pad function."] +pub type USB_SERIAL_JTAG_USB_PAD_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN` reader - Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix."] +pub type USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN` writer - Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix."] +pub type USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Select internal/external PHY"] + #[inline(always)] + pub fn usb_serial_jtag_phy_sel(&self) -> USB_SERIAL_JTAG_PHY_SEL_R { + USB_SERIAL_JTAG_PHY_SEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable software control USB D+ D- exchange"] + #[inline(always)] + pub fn usb_serial_jtag_exchg_pins_override(&self) -> USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_R { + USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - USB D+ D- exchange"] + #[inline(always)] + pub fn usb_serial_jtag_exchg_pins(&self) -> USB_SERIAL_JTAG_EXCHG_PINS_R { + USB_SERIAL_JTAG_EXCHG_PINS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - Control single-end input high threshold,1.76V to 2V, step 80mV"] + #[inline(always)] + pub fn usb_serial_jtag_vrefh(&self) -> USB_SERIAL_JTAG_VREFH_R { + USB_SERIAL_JTAG_VREFH_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bits 5:6 - Control single-end input low threshold,0.8V to 1.04V, step 80mV"] + #[inline(always)] + pub fn usb_serial_jtag_vrefl(&self) -> USB_SERIAL_JTAG_VREFL_R { + USB_SERIAL_JTAG_VREFL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Enable software control input threshold"] + #[inline(always)] + pub fn usb_serial_jtag_vref_override(&self) -> USB_SERIAL_JTAG_VREF_OVERRIDE_R { + USB_SERIAL_JTAG_VREF_OVERRIDE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable software control USB D+ D- pullup pulldown"] + #[inline(always)] + pub fn usb_serial_jtag_pad_pull_override(&self) -> USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_R { + USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Control USB D+ pull up."] + #[inline(always)] + pub fn usb_serial_jtag_dp_pullup(&self) -> USB_SERIAL_JTAG_DP_PULLUP_R { + USB_SERIAL_JTAG_DP_PULLUP_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Control USB D+ pull down."] + #[inline(always)] + pub fn usb_serial_jtag_dp_pulldown(&self) -> USB_SERIAL_JTAG_DP_PULLDOWN_R { + USB_SERIAL_JTAG_DP_PULLDOWN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Control USB D- pull up."] + #[inline(always)] + pub fn usb_serial_jtag_dm_pullup(&self) -> USB_SERIAL_JTAG_DM_PULLUP_R { + USB_SERIAL_JTAG_DM_PULLUP_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Control USB D- pull down."] + #[inline(always)] + pub fn usb_serial_jtag_dm_pulldown(&self) -> USB_SERIAL_JTAG_DM_PULLDOWN_R { + USB_SERIAL_JTAG_DM_PULLDOWN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Control pull up value."] + #[inline(always)] + pub fn usb_serial_jtag_pullup_value(&self) -> USB_SERIAL_JTAG_PULLUP_VALUE_R { + USB_SERIAL_JTAG_PULLUP_VALUE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Enable USB pad function."] + #[inline(always)] + pub fn usb_serial_jtag_usb_pad_enable(&self) -> USB_SERIAL_JTAG_USB_PAD_ENABLE_R { + USB_SERIAL_JTAG_USB_PAD_ENABLE_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix."] + #[inline(always)] + pub fn usb_serial_jtag_usb_jtag_bridge_en(&self) -> USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_R { + USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CONF0") + .field( + "usb_serial_jtag_phy_sel", + &format_args!("{}", self.usb_serial_jtag_phy_sel().bit()), + ) + .field( + "usb_serial_jtag_exchg_pins_override", + &format_args!("{}", self.usb_serial_jtag_exchg_pins_override().bit()), + ) + .field( + "usb_serial_jtag_exchg_pins", + &format_args!("{}", self.usb_serial_jtag_exchg_pins().bit()), + ) + .field( + "usb_serial_jtag_vrefh", + &format_args!("{}", self.usb_serial_jtag_vrefh().bits()), + ) + .field( + "usb_serial_jtag_vrefl", + &format_args!("{}", self.usb_serial_jtag_vrefl().bits()), + ) + .field( + "usb_serial_jtag_vref_override", + &format_args!("{}", self.usb_serial_jtag_vref_override().bit()), + ) + .field( + "usb_serial_jtag_pad_pull_override", + &format_args!("{}", self.usb_serial_jtag_pad_pull_override().bit()), + ) + .field( + "usb_serial_jtag_dp_pullup", + &format_args!("{}", self.usb_serial_jtag_dp_pullup().bit()), + ) + .field( + "usb_serial_jtag_dp_pulldown", + &format_args!("{}", self.usb_serial_jtag_dp_pulldown().bit()), + ) + .field( + "usb_serial_jtag_dm_pullup", + &format_args!("{}", self.usb_serial_jtag_dm_pullup().bit()), + ) + .field( + "usb_serial_jtag_dm_pulldown", + &format_args!("{}", self.usb_serial_jtag_dm_pulldown().bit()), + ) + .field( + "usb_serial_jtag_pullup_value", + &format_args!("{}", self.usb_serial_jtag_pullup_value().bit()), + ) + .field( + "usb_serial_jtag_usb_pad_enable", + &format_args!("{}", self.usb_serial_jtag_usb_pad_enable().bit()), + ) + .field( + "usb_serial_jtag_usb_jtag_bridge_en", + &format_args!("{}", self.usb_serial_jtag_usb_jtag_bridge_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Select internal/external PHY"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_phy_sel(&mut self) -> USB_SERIAL_JTAG_PHY_SEL_W { + USB_SERIAL_JTAG_PHY_SEL_W::new(self, 0) + } + #[doc = "Bit 1 - Enable software control USB D+ D- exchange"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_exchg_pins_override( + &mut self, + ) -> USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_W { + USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_W::new(self, 1) + } + #[doc = "Bit 2 - USB D+ D- exchange"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_exchg_pins(&mut self) -> USB_SERIAL_JTAG_EXCHG_PINS_W { + USB_SERIAL_JTAG_EXCHG_PINS_W::new(self, 2) + } + #[doc = "Bits 3:4 - Control single-end input high threshold,1.76V to 2V, step 80mV"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_vrefh(&mut self) -> USB_SERIAL_JTAG_VREFH_W { + USB_SERIAL_JTAG_VREFH_W::new(self, 3) + } + #[doc = "Bits 5:6 - Control single-end input low threshold,0.8V to 1.04V, step 80mV"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_vrefl(&mut self) -> USB_SERIAL_JTAG_VREFL_W { + USB_SERIAL_JTAG_VREFL_W::new(self, 5) + } + #[doc = "Bit 7 - Enable software control input threshold"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_vref_override(&mut self) -> USB_SERIAL_JTAG_VREF_OVERRIDE_W { + USB_SERIAL_JTAG_VREF_OVERRIDE_W::new(self, 7) + } + #[doc = "Bit 8 - Enable software control USB D+ D- pullup pulldown"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_pad_pull_override( + &mut self, + ) -> USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_W { + USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_W::new(self, 8) + } + #[doc = "Bit 9 - Control USB D+ pull up."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_dp_pullup(&mut self) -> USB_SERIAL_JTAG_DP_PULLUP_W { + USB_SERIAL_JTAG_DP_PULLUP_W::new(self, 9) + } + #[doc = "Bit 10 - Control USB D+ pull down."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_dp_pulldown(&mut self) -> USB_SERIAL_JTAG_DP_PULLDOWN_W { + USB_SERIAL_JTAG_DP_PULLDOWN_W::new(self, 10) + } + #[doc = "Bit 11 - Control USB D- pull up."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_dm_pullup(&mut self) -> USB_SERIAL_JTAG_DM_PULLUP_W { + USB_SERIAL_JTAG_DM_PULLUP_W::new(self, 11) + } + #[doc = "Bit 12 - Control USB D- pull down."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_dm_pulldown(&mut self) -> USB_SERIAL_JTAG_DM_PULLDOWN_W { + USB_SERIAL_JTAG_DM_PULLDOWN_W::new(self, 12) + } + #[doc = "Bit 13 - Control pull up value."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_pullup_value(&mut self) -> USB_SERIAL_JTAG_PULLUP_VALUE_W { + USB_SERIAL_JTAG_PULLUP_VALUE_W::new(self, 13) + } + #[doc = "Bit 14 - Enable USB pad function."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_usb_pad_enable( + &mut self, + ) -> USB_SERIAL_JTAG_USB_PAD_ENABLE_W { + USB_SERIAL_JTAG_USB_PAD_ENABLE_W::new(self, 14) + } + #[doc = "Bit 15 - Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_usb_jtag_bridge_en( + &mut self, + ) -> USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_W { + USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PHY hardware configuration.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONF0_SPEC; +impl crate::RegisterSpec for CONF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`conf0::R`](R) reader structure"] +impl crate::Readable for CONF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"] +impl crate::Writable for CONF0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONF0 to value 0x4200"] +impl crate::Resettable for CONF0_SPEC { + const RESET_VALUE: Self::Ux = 0x4200; +} diff --git a/esp32p4/src/usb_device/config_update.rs b/esp32p4/src/usb_device/config_update.rs new file mode 100644 index 0000000000..d0d0d83e62 --- /dev/null +++ b/esp32p4/src/usb_device/config_update.rs @@ -0,0 +1,44 @@ +#[doc = "Register `CONFIG_UPDATE` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_CONFIG_UPDATE` writer - Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain."] +pub type USB_SERIAL_JTAG_CONFIG_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_config_update( + &mut self, + ) -> USB_SERIAL_JTAG_CONFIG_UPDATE_W { + USB_SERIAL_JTAG_CONFIG_UPDATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration registers' value update\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config_update::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CONFIG_UPDATE_SPEC; +impl crate::RegisterSpec for CONFIG_UPDATE_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`config_update::W`](W) writer structure"] +impl crate::Writable for CONFIG_UPDATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONFIG_UPDATE to value 0"] +impl crate::Resettable for CONFIG_UPDATE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/date.rs b/esp32p4/src/usb_device/date.rs new file mode 100644 index 0000000000..15c2435ad1 --- /dev/null +++ b/esp32p4/src/usb_device/date.rs @@ -0,0 +1,66 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Register `DATE` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_DATE` reader - register version."] +pub type USB_SERIAL_JTAG_DATE_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_DATE` writer - register version."] +pub type USB_SERIAL_JTAG_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - register version."] + #[inline(always)] + pub fn usb_serial_jtag_date(&self) -> USB_SERIAL_JTAG_DATE_R { + USB_SERIAL_JTAG_DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field( + "usb_serial_jtag_date", + &format_args!("{}", self.usb_serial_jtag_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - register version."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_date(&mut self) -> USB_SERIAL_JTAG_DATE_W { + USB_SERIAL_JTAG_DATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Date register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"] +impl crate::Writable for DATE_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATE to value 0x0211_2010"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x0211_2010; +} diff --git a/esp32p4/src/usb_device/eco_cell_ctrl_48.rs b/esp32p4/src/usb_device/eco_cell_ctrl_48.rs new file mode 100644 index 0000000000..d0d0dca349 --- /dev/null +++ b/esp32p4/src/usb_device/eco_cell_ctrl_48.rs @@ -0,0 +1,79 @@ +#[doc = "Register `ECO_CELL_CTRL_48` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_CELL_CTRL_48` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_RDN_RESULT_48` reader - Reserved."] +pub type USB_SERIAL_JTAG_RDN_RESULT_48_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_RDN_ENA_48` reader - Reserved."] +pub type USB_SERIAL_JTAG_RDN_ENA_48_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_RDN_ENA_48` writer - Reserved."] +pub type USB_SERIAL_JTAG_RDN_ENA_48_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved."] + #[inline(always)] + pub fn usb_serial_jtag_rdn_result_48(&self) -> USB_SERIAL_JTAG_RDN_RESULT_48_R { + USB_SERIAL_JTAG_RDN_RESULT_48_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved."] + #[inline(always)] + pub fn usb_serial_jtag_rdn_ena_48(&self) -> USB_SERIAL_JTAG_RDN_ENA_48_R { + USB_SERIAL_JTAG_RDN_ENA_48_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_CELL_CTRL_48") + .field( + "usb_serial_jtag_rdn_result_48", + &format_args!("{}", self.usb_serial_jtag_rdn_result_48().bit()), + ) + .field( + "usb_serial_jtag_rdn_ena_48", + &format_args!("{}", self.usb_serial_jtag_rdn_ena_48().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 1 - Reserved."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_rdn_ena_48( + &mut self, + ) -> USB_SERIAL_JTAG_RDN_ENA_48_W { + USB_SERIAL_JTAG_RDN_ENA_48_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_cell_ctrl_48::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_cell_ctrl_48::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_CELL_CTRL_48_SPEC; +impl crate::RegisterSpec for ECO_CELL_CTRL_48_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_cell_ctrl_48::R`](R) reader structure"] +impl crate::Readable for ECO_CELL_CTRL_48_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_cell_ctrl_48::W`](W) writer structure"] +impl crate::Writable for ECO_CELL_CTRL_48_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_CELL_CTRL_48 to value 0"] +impl crate::Resettable for ECO_CELL_CTRL_48_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/eco_cell_ctrl_apb.rs b/esp32p4/src/usb_device/eco_cell_ctrl_apb.rs new file mode 100644 index 0000000000..bc8da11fb9 --- /dev/null +++ b/esp32p4/src/usb_device/eco_cell_ctrl_apb.rs @@ -0,0 +1,79 @@ +#[doc = "Register `ECO_CELL_CTRL_APB` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_CELL_CTRL_APB` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_RDN_RESULT_APB` reader - Reserved."] +pub type USB_SERIAL_JTAG_RDN_RESULT_APB_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_RDN_ENA_APB` reader - Reserved."] +pub type USB_SERIAL_JTAG_RDN_ENA_APB_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_RDN_ENA_APB` writer - Reserved."] +pub type USB_SERIAL_JTAG_RDN_ENA_APB_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved."] + #[inline(always)] + pub fn usb_serial_jtag_rdn_result_apb(&self) -> USB_SERIAL_JTAG_RDN_RESULT_APB_R { + USB_SERIAL_JTAG_RDN_RESULT_APB_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved."] + #[inline(always)] + pub fn usb_serial_jtag_rdn_ena_apb(&self) -> USB_SERIAL_JTAG_RDN_ENA_APB_R { + USB_SERIAL_JTAG_RDN_ENA_APB_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_CELL_CTRL_APB") + .field( + "usb_serial_jtag_rdn_result_apb", + &format_args!("{}", self.usb_serial_jtag_rdn_result_apb().bit()), + ) + .field( + "usb_serial_jtag_rdn_ena_apb", + &format_args!("{}", self.usb_serial_jtag_rdn_ena_apb().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 1 - Reserved."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_rdn_ena_apb( + &mut self, + ) -> USB_SERIAL_JTAG_RDN_ENA_APB_W { + USB_SERIAL_JTAG_RDN_ENA_APB_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_cell_ctrl_apb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_cell_ctrl_apb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_CELL_CTRL_APB_SPEC; +impl crate::RegisterSpec for ECO_CELL_CTRL_APB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_cell_ctrl_apb::R`](R) reader structure"] +impl crate::Readable for ECO_CELL_CTRL_APB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_cell_ctrl_apb::W`](W) writer structure"] +impl crate::Writable for ECO_CELL_CTRL_APB_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_CELL_CTRL_APB to value 0"] +impl crate::Resettable for ECO_CELL_CTRL_APB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/eco_high_48.rs b/esp32p4/src/usb_device/eco_high_48.rs new file mode 100644 index 0000000000..e34fd99616 --- /dev/null +++ b/esp32p4/src/usb_device/eco_high_48.rs @@ -0,0 +1,68 @@ +#[doc = "Register `ECO_HIGH_48` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_HIGH_48` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_RND_ECO_HIGH_48` reader - Reserved."] +pub type USB_SERIAL_JTAG_RND_ECO_HIGH_48_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_RND_ECO_HIGH_48` writer - Reserved."] +pub type USB_SERIAL_JTAG_RND_ECO_HIGH_48_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + pub fn usb_serial_jtag_rnd_eco_high_48(&self) -> USB_SERIAL_JTAG_RND_ECO_HIGH_48_R { + USB_SERIAL_JTAG_RND_ECO_HIGH_48_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_HIGH_48") + .field( + "usb_serial_jtag_rnd_eco_high_48", + &format_args!("{}", self.usb_serial_jtag_rnd_eco_high_48().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_rnd_eco_high_48( + &mut self, + ) -> USB_SERIAL_JTAG_RND_ECO_HIGH_48_W { + USB_SERIAL_JTAG_RND_ECO_HIGH_48_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_high_48::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_high_48::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_HIGH_48_SPEC; +impl crate::RegisterSpec for ECO_HIGH_48_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_high_48::R`](R) reader structure"] +impl crate::Readable for ECO_HIGH_48_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_high_48::W`](W) writer structure"] +impl crate::Writable for ECO_HIGH_48_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_HIGH_48 to value 0xffff_ffff"] +impl crate::Resettable for ECO_HIGH_48_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/usb_device/eco_high_apb.rs b/esp32p4/src/usb_device/eco_high_apb.rs new file mode 100644 index 0000000000..c92f9fcc05 --- /dev/null +++ b/esp32p4/src/usb_device/eco_high_apb.rs @@ -0,0 +1,68 @@ +#[doc = "Register `ECO_HIGH_APB` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_HIGH_APB` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_RND_ECO_HIGH_APB` reader - Reserved."] +pub type USB_SERIAL_JTAG_RND_ECO_HIGH_APB_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_RND_ECO_HIGH_APB` writer - Reserved."] +pub type USB_SERIAL_JTAG_RND_ECO_HIGH_APB_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + pub fn usb_serial_jtag_rnd_eco_high_apb(&self) -> USB_SERIAL_JTAG_RND_ECO_HIGH_APB_R { + USB_SERIAL_JTAG_RND_ECO_HIGH_APB_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_HIGH_APB") + .field( + "usb_serial_jtag_rnd_eco_high_apb", + &format_args!("{}", self.usb_serial_jtag_rnd_eco_high_apb().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_rnd_eco_high_apb( + &mut self, + ) -> USB_SERIAL_JTAG_RND_ECO_HIGH_APB_W { + USB_SERIAL_JTAG_RND_ECO_HIGH_APB_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_high_apb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_high_apb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_HIGH_APB_SPEC; +impl crate::RegisterSpec for ECO_HIGH_APB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_high_apb::R`](R) reader structure"] +impl crate::Readable for ECO_HIGH_APB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_high_apb::W`](W) writer structure"] +impl crate::Writable for ECO_HIGH_APB_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_HIGH_APB to value 0xffff_ffff"] +impl crate::Resettable for ECO_HIGH_APB_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/esp32p4/src/usb_device/eco_low_48.rs b/esp32p4/src/usb_device/eco_low_48.rs new file mode 100644 index 0000000000..bdbf7b9e00 --- /dev/null +++ b/esp32p4/src/usb_device/eco_low_48.rs @@ -0,0 +1,68 @@ +#[doc = "Register `ECO_LOW_48` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_LOW_48` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_RND_ECO_LOW_48` reader - Reserved."] +pub type USB_SERIAL_JTAG_RND_ECO_LOW_48_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_RND_ECO_LOW_48` writer - Reserved."] +pub type USB_SERIAL_JTAG_RND_ECO_LOW_48_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + pub fn usb_serial_jtag_rnd_eco_low_48(&self) -> USB_SERIAL_JTAG_RND_ECO_LOW_48_R { + USB_SERIAL_JTAG_RND_ECO_LOW_48_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_LOW_48") + .field( + "usb_serial_jtag_rnd_eco_low_48", + &format_args!("{}", self.usb_serial_jtag_rnd_eco_low_48().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_rnd_eco_low_48( + &mut self, + ) -> USB_SERIAL_JTAG_RND_ECO_LOW_48_W { + USB_SERIAL_JTAG_RND_ECO_LOW_48_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_low_48::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_low_48::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_LOW_48_SPEC; +impl crate::RegisterSpec for ECO_LOW_48_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_low_48::R`](R) reader structure"] +impl crate::Readable for ECO_LOW_48_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_low_48::W`](W) writer structure"] +impl crate::Writable for ECO_LOW_48_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_LOW_48 to value 0"] +impl crate::Resettable for ECO_LOW_48_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/eco_low_apb.rs b/esp32p4/src/usb_device/eco_low_apb.rs new file mode 100644 index 0000000000..25b97fc002 --- /dev/null +++ b/esp32p4/src/usb_device/eco_low_apb.rs @@ -0,0 +1,68 @@ +#[doc = "Register `ECO_LOW_APB` reader"] +pub type R = crate::R; +#[doc = "Register `ECO_LOW_APB` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_RND_ECO_LOW_APB` reader - Reserved."] +pub type USB_SERIAL_JTAG_RND_ECO_LOW_APB_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_RND_ECO_LOW_APB` writer - Reserved."] +pub type USB_SERIAL_JTAG_RND_ECO_LOW_APB_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + pub fn usb_serial_jtag_rnd_eco_low_apb(&self) -> USB_SERIAL_JTAG_RND_ECO_LOW_APB_R { + USB_SERIAL_JTAG_RND_ECO_LOW_APB_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ECO_LOW_APB") + .field( + "usb_serial_jtag_rnd_eco_low_apb", + &format_args!("{}", self.usb_serial_jtag_rnd_eco_low_apb().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - Reserved."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_rnd_eco_low_apb( + &mut self, + ) -> USB_SERIAL_JTAG_RND_ECO_LOW_APB_W { + USB_SERIAL_JTAG_RND_ECO_LOW_APB_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Reserved.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eco_low_apb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eco_low_apb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ECO_LOW_APB_SPEC; +impl crate::RegisterSpec for ECO_LOW_APB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`eco_low_apb::R`](R) reader structure"] +impl crate::Readable for ECO_LOW_APB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eco_low_apb::W`](W) writer structure"] +impl crate::Writable for ECO_LOW_APB_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ECO_LOW_APB to value 0"] +impl crate::Resettable for ECO_LOW_APB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/ep1.rs b/esp32p4/src/usb_device/ep1.rs new file mode 100644 index 0000000000..e9d9d8479a --- /dev/null +++ b/esp32p4/src/usb_device/ep1.rs @@ -0,0 +1,39 @@ +#[doc = "Register `EP1` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_RDWR_BYTE` reader - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."] +pub type USB_SERIAL_JTAG_RDWR_BYTE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."] + #[inline(always)] + pub fn usb_serial_jtag_rdwr_byte(&self) -> USB_SERIAL_JTAG_RDWR_BYTE_R { + USB_SERIAL_JTAG_RDWR_BYTE_R::new((self.bits & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EP1") + .field( + "usb_serial_jtag_rdwr_byte", + &format_args!("{}", self.usb_serial_jtag_rdwr_byte().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "FIFO access for the CDC-ACM data IN and OUT endpoints.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EP1_SPEC; +impl crate::RegisterSpec for EP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ep1::R`](R) reader structure"] +impl crate::Readable for EP1_SPEC {} +#[doc = "`reset()` method sets EP1 to value 0"] +impl crate::Resettable for EP1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/ep1_conf.rs b/esp32p4/src/usb_device/ep1_conf.rs new file mode 100644 index 0000000000..49d2dd0305 --- /dev/null +++ b/esp32p4/src/usb_device/ep1_conf.rs @@ -0,0 +1,81 @@ +#[doc = "Register `EP1_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `EP1_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_WR_DONE` writer - Set this bit to indicate writing byte data to UART Tx FIFO is done."] +pub type USB_SERIAL_JTAG_WR_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE` reader - 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host."] +pub type USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL` reader - 1'b1: Indicate there is data in UART Rx FIFO."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_R = crate::BitReader; +impl R { + #[doc = "Bit 1 - 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host."] + #[inline(always)] + pub fn usb_serial_jtag_serial_in_ep_data_free( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_R { + USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1'b1: Indicate there is data in UART Rx FIFO."] + #[inline(always)] + pub fn usb_serial_jtag_serial_out_ep_data_avail( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_R { + USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EP1_CONF") + .field( + "usb_serial_jtag_serial_in_ep_data_free", + &format_args!("{}", self.usb_serial_jtag_serial_in_ep_data_free().bit()), + ) + .field( + "usb_serial_jtag_serial_out_ep_data_avail", + &format_args!("{}", self.usb_serial_jtag_serial_out_ep_data_avail().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Set this bit to indicate writing byte data to UART Tx FIFO is done."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_wr_done(&mut self) -> USB_SERIAL_JTAG_WR_DONE_W { + USB_SERIAL_JTAG_WR_DONE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Configuration and control registers for the CDC-ACM FIFOs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ep1_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ep1_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EP1_CONF_SPEC; +impl crate::RegisterSpec for EP1_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ep1_conf::R`](R) reader structure"] +impl crate::Readable for EP1_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep1_conf::W`](W) writer structure"] +impl crate::Writable for EP1_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EP1_CONF to value 0x02"] +impl crate::Resettable for EP1_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/usb_device/fram_num.rs b/esp32p4/src/usb_device/fram_num.rs new file mode 100644 index 0000000000..8aa231b11a --- /dev/null +++ b/esp32p4/src/usb_device/fram_num.rs @@ -0,0 +1,39 @@ +#[doc = "Register `FRAM_NUM` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_SOF_FRAME_INDEX` reader - Frame index of received SOF frame."] +pub type USB_SERIAL_JTAG_SOF_FRAME_INDEX_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:10 - Frame index of received SOF frame."] + #[inline(always)] + pub fn usb_serial_jtag_sof_frame_index(&self) -> USB_SERIAL_JTAG_SOF_FRAME_INDEX_R { + USB_SERIAL_JTAG_SOF_FRAME_INDEX_R::new((self.bits & 0x07ff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FRAM_NUM") + .field( + "usb_serial_jtag_sof_frame_index", + &format_args!("{}", self.usb_serial_jtag_sof_frame_index().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Last received SOF frame index register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fram_num::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FRAM_NUM_SPEC; +impl crate::RegisterSpec for FRAM_NUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fram_num::R`](R) reader structure"] +impl crate::Readable for FRAM_NUM_SPEC {} +#[doc = "`reset()` method sets FRAM_NUM to value 0"] +impl crate::Resettable for FRAM_NUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/get_line_code_w0.rs b/esp32p4/src/usb_device/get_line_code_w0.rs new file mode 100644 index 0000000000..e63b18358d --- /dev/null +++ b/esp32p4/src/usb_device/get_line_code_w0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `GET_LINE_CODE_W0` reader"] +pub type R = crate::R; +#[doc = "Register `GET_LINE_CODE_W0` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_GET_DW_DTE_RATE` reader - The value of dwDTERate set by software which is requested by GET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_GET_DW_DTE_RATE_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_GET_DW_DTE_RATE` writer - The value of dwDTERate set by software which is requested by GET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_GET_DW_DTE_RATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The value of dwDTERate set by software which is requested by GET_LINE_CODING command."] + #[inline(always)] + pub fn usb_serial_jtag_get_dw_dte_rate(&self) -> USB_SERIAL_JTAG_GET_DW_DTE_RATE_R { + USB_SERIAL_JTAG_GET_DW_DTE_RATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GET_LINE_CODE_W0") + .field( + "usb_serial_jtag_get_dw_dte_rate", + &format_args!("{}", self.usb_serial_jtag_get_dw_dte_rate().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:31 - The value of dwDTERate set by software which is requested by GET_LINE_CODING command."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_get_dw_dte_rate( + &mut self, + ) -> USB_SERIAL_JTAG_GET_DW_DTE_RATE_W { + USB_SERIAL_JTAG_GET_DW_DTE_RATE_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "W0 of GET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`get_line_code_w0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`get_line_code_w0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GET_LINE_CODE_W0_SPEC; +impl crate::RegisterSpec for GET_LINE_CODE_W0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`get_line_code_w0::R`](R) reader structure"] +impl crate::Readable for GET_LINE_CODE_W0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`get_line_code_w0::W`](W) writer structure"] +impl crate::Writable for GET_LINE_CODE_W0_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GET_LINE_CODE_W0 to value 0"] +impl crate::Resettable for GET_LINE_CODE_W0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/get_line_code_w1.rs b/esp32p4/src/usb_device/get_line_code_w1.rs new file mode 100644 index 0000000000..a580bd4b4d --- /dev/null +++ b/esp32p4/src/usb_device/get_line_code_w1.rs @@ -0,0 +1,110 @@ +#[doc = "Register `GET_LINE_CODE_W1` reader"] +pub type R = crate::R; +#[doc = "Register `GET_LINE_CODE_W1` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_GET_BDATA_BITS` reader - The value of bCharFormat set by software which is requested by GET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_GET_BDATA_BITS_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_GET_BDATA_BITS` writer - The value of bCharFormat set by software which is requested by GET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_GET_BDATA_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `USB_SERIAL_JTAG_GET_BPARITY_TYPE` reader - The value of bParityTpye set by software which is requested by GET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_GET_BPARITY_TYPE_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_GET_BPARITY_TYPE` writer - The value of bParityTpye set by software which is requested by GET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_GET_BPARITY_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `USB_SERIAL_JTAG_GET_BCHAR_FORMAT` reader - The value of bDataBits set by software which is requested by GET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_GET_BCHAR_FORMAT_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_GET_BCHAR_FORMAT` writer - The value of bDataBits set by software which is requested by GET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_GET_BCHAR_FORMAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - The value of bCharFormat set by software which is requested by GET_LINE_CODING command."] + #[inline(always)] + pub fn usb_serial_jtag_get_bdata_bits(&self) -> USB_SERIAL_JTAG_GET_BDATA_BITS_R { + USB_SERIAL_JTAG_GET_BDATA_BITS_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - The value of bParityTpye set by software which is requested by GET_LINE_CODING command."] + #[inline(always)] + pub fn usb_serial_jtag_get_bparity_type(&self) -> USB_SERIAL_JTAG_GET_BPARITY_TYPE_R { + USB_SERIAL_JTAG_GET_BPARITY_TYPE_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - The value of bDataBits set by software which is requested by GET_LINE_CODING command."] + #[inline(always)] + pub fn usb_serial_jtag_get_bchar_format(&self) -> USB_SERIAL_JTAG_GET_BCHAR_FORMAT_R { + USB_SERIAL_JTAG_GET_BCHAR_FORMAT_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GET_LINE_CODE_W1") + .field( + "usb_serial_jtag_get_bdata_bits", + &format_args!("{}", self.usb_serial_jtag_get_bdata_bits().bits()), + ) + .field( + "usb_serial_jtag_get_bparity_type", + &format_args!("{}", self.usb_serial_jtag_get_bparity_type().bits()), + ) + .field( + "usb_serial_jtag_get_bchar_format", + &format_args!("{}", self.usb_serial_jtag_get_bchar_format().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:7 - The value of bCharFormat set by software which is requested by GET_LINE_CODING command."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_get_bdata_bits( + &mut self, + ) -> USB_SERIAL_JTAG_GET_BDATA_BITS_W { + USB_SERIAL_JTAG_GET_BDATA_BITS_W::new(self, 0) + } + #[doc = "Bits 8:15 - The value of bParityTpye set by software which is requested by GET_LINE_CODING command."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_get_bparity_type( + &mut self, + ) -> USB_SERIAL_JTAG_GET_BPARITY_TYPE_W { + USB_SERIAL_JTAG_GET_BPARITY_TYPE_W::new(self, 8) + } + #[doc = "Bits 16:23 - The value of bDataBits set by software which is requested by GET_LINE_CODING command."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_get_bchar_format( + &mut self, + ) -> USB_SERIAL_JTAG_GET_BCHAR_FORMAT_W { + USB_SERIAL_JTAG_GET_BCHAR_FORMAT_W::new(self, 16) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "W1 of GET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`get_line_code_w1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`get_line_code_w1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GET_LINE_CODE_W1_SPEC; +impl crate::RegisterSpec for GET_LINE_CODE_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`get_line_code_w1::R`](R) reader structure"] +impl crate::Readable for GET_LINE_CODE_W1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`get_line_code_w1::W`](W) writer structure"] +impl crate::Writable for GET_LINE_CODE_W1_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GET_LINE_CODE_W1 to value 0"] +impl crate::Resettable for GET_LINE_CODE_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/in_ep0_st.rs b/esp32p4/src/usb_device/in_ep0_st.rs new file mode 100644 index 0000000000..4a6566f9a6 --- /dev/null +++ b/esp32p4/src/usb_device/in_ep0_st.rs @@ -0,0 +1,61 @@ +#[doc = "Register `IN_EP0_ST` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP0_STATE` reader - State of IN Endpoint 0."] +pub type USB_SERIAL_JTAG_IN_EP0_STATE_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP0_WR_ADDR` reader - Write data address of IN endpoint 0."] +pub type USB_SERIAL_JTAG_IN_EP0_WR_ADDR_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP0_RD_ADDR` reader - Read data address of IN endpoint 0."] +pub type USB_SERIAL_JTAG_IN_EP0_RD_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - State of IN Endpoint 0."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep0_state(&self) -> USB_SERIAL_JTAG_IN_EP0_STATE_R { + USB_SERIAL_JTAG_IN_EP0_STATE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:8 - Write data address of IN endpoint 0."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep0_wr_addr(&self) -> USB_SERIAL_JTAG_IN_EP0_WR_ADDR_R { + USB_SERIAL_JTAG_IN_EP0_WR_ADDR_R::new(((self.bits >> 2) & 0x7f) as u8) + } + #[doc = "Bits 9:15 - Read data address of IN endpoint 0."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep0_rd_addr(&self) -> USB_SERIAL_JTAG_IN_EP0_RD_ADDR_R { + USB_SERIAL_JTAG_IN_EP0_RD_ADDR_R::new(((self.bits >> 9) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_EP0_ST") + .field( + "usb_serial_jtag_in_ep0_state", + &format_args!("{}", self.usb_serial_jtag_in_ep0_state().bits()), + ) + .field( + "usb_serial_jtag_in_ep0_wr_addr", + &format_args!("{}", self.usb_serial_jtag_in_ep0_wr_addr().bits()), + ) + .field( + "usb_serial_jtag_in_ep0_rd_addr", + &format_args!("{}", self.usb_serial_jtag_in_ep0_rd_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Control IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep0_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_EP0_ST_SPEC; +impl crate::RegisterSpec for IN_EP0_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_ep0_st::R`](R) reader structure"] +impl crate::Readable for IN_EP0_ST_SPEC {} +#[doc = "`reset()` method sets IN_EP0_ST to value 0x01"] +impl crate::Resettable for IN_EP0_ST_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/usb_device/in_ep1_st.rs b/esp32p4/src/usb_device/in_ep1_st.rs new file mode 100644 index 0000000000..39f39d97b1 --- /dev/null +++ b/esp32p4/src/usb_device/in_ep1_st.rs @@ -0,0 +1,61 @@ +#[doc = "Register `IN_EP1_ST` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP1_STATE` reader - State of IN Endpoint 1."] +pub type USB_SERIAL_JTAG_IN_EP1_STATE_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP1_WR_ADDR` reader - Write data address of IN endpoint 1."] +pub type USB_SERIAL_JTAG_IN_EP1_WR_ADDR_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP1_RD_ADDR` reader - Read data address of IN endpoint 1."] +pub type USB_SERIAL_JTAG_IN_EP1_RD_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - State of IN Endpoint 1."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep1_state(&self) -> USB_SERIAL_JTAG_IN_EP1_STATE_R { + USB_SERIAL_JTAG_IN_EP1_STATE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:8 - Write data address of IN endpoint 1."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep1_wr_addr(&self) -> USB_SERIAL_JTAG_IN_EP1_WR_ADDR_R { + USB_SERIAL_JTAG_IN_EP1_WR_ADDR_R::new(((self.bits >> 2) & 0x7f) as u8) + } + #[doc = "Bits 9:15 - Read data address of IN endpoint 1."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep1_rd_addr(&self) -> USB_SERIAL_JTAG_IN_EP1_RD_ADDR_R { + USB_SERIAL_JTAG_IN_EP1_RD_ADDR_R::new(((self.bits >> 9) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_EP1_ST") + .field( + "usb_serial_jtag_in_ep1_state", + &format_args!("{}", self.usb_serial_jtag_in_ep1_state().bits()), + ) + .field( + "usb_serial_jtag_in_ep1_wr_addr", + &format_args!("{}", self.usb_serial_jtag_in_ep1_wr_addr().bits()), + ) + .field( + "usb_serial_jtag_in_ep1_rd_addr", + &format_args!("{}", self.usb_serial_jtag_in_ep1_rd_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "CDC-ACM IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep1_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_EP1_ST_SPEC; +impl crate::RegisterSpec for IN_EP1_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_ep1_st::R`](R) reader structure"] +impl crate::Readable for IN_EP1_ST_SPEC {} +#[doc = "`reset()` method sets IN_EP1_ST to value 0x01"] +impl crate::Resettable for IN_EP1_ST_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/usb_device/in_ep2_st.rs b/esp32p4/src/usb_device/in_ep2_st.rs new file mode 100644 index 0000000000..1021fb7239 --- /dev/null +++ b/esp32p4/src/usb_device/in_ep2_st.rs @@ -0,0 +1,61 @@ +#[doc = "Register `IN_EP2_ST` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP2_STATE` reader - State of IN Endpoint 2."] +pub type USB_SERIAL_JTAG_IN_EP2_STATE_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP2_WR_ADDR` reader - Write data address of IN endpoint 2."] +pub type USB_SERIAL_JTAG_IN_EP2_WR_ADDR_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP2_RD_ADDR` reader - Read data address of IN endpoint 2."] +pub type USB_SERIAL_JTAG_IN_EP2_RD_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - State of IN Endpoint 2."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep2_state(&self) -> USB_SERIAL_JTAG_IN_EP2_STATE_R { + USB_SERIAL_JTAG_IN_EP2_STATE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:8 - Write data address of IN endpoint 2."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep2_wr_addr(&self) -> USB_SERIAL_JTAG_IN_EP2_WR_ADDR_R { + USB_SERIAL_JTAG_IN_EP2_WR_ADDR_R::new(((self.bits >> 2) & 0x7f) as u8) + } + #[doc = "Bits 9:15 - Read data address of IN endpoint 2."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep2_rd_addr(&self) -> USB_SERIAL_JTAG_IN_EP2_RD_ADDR_R { + USB_SERIAL_JTAG_IN_EP2_RD_ADDR_R::new(((self.bits >> 9) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_EP2_ST") + .field( + "usb_serial_jtag_in_ep2_state", + &format_args!("{}", self.usb_serial_jtag_in_ep2_state().bits()), + ) + .field( + "usb_serial_jtag_in_ep2_wr_addr", + &format_args!("{}", self.usb_serial_jtag_in_ep2_wr_addr().bits()), + ) + .field( + "usb_serial_jtag_in_ep2_rd_addr", + &format_args!("{}", self.usb_serial_jtag_in_ep2_rd_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "CDC-ACM interrupt IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep2_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_EP2_ST_SPEC; +impl crate::RegisterSpec for IN_EP2_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_ep2_st::R`](R) reader structure"] +impl crate::Readable for IN_EP2_ST_SPEC {} +#[doc = "`reset()` method sets IN_EP2_ST to value 0x01"] +impl crate::Resettable for IN_EP2_ST_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/usb_device/in_ep3_st.rs b/esp32p4/src/usb_device/in_ep3_st.rs new file mode 100644 index 0000000000..32bc4db76e --- /dev/null +++ b/esp32p4/src/usb_device/in_ep3_st.rs @@ -0,0 +1,61 @@ +#[doc = "Register `IN_EP3_ST` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP3_STATE` reader - State of IN Endpoint 3."] +pub type USB_SERIAL_JTAG_IN_EP3_STATE_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP3_WR_ADDR` reader - Write data address of IN endpoint 3."] +pub type USB_SERIAL_JTAG_IN_EP3_WR_ADDR_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_EP3_RD_ADDR` reader - Read data address of IN endpoint 3."] +pub type USB_SERIAL_JTAG_IN_EP3_RD_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - State of IN Endpoint 3."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep3_state(&self) -> USB_SERIAL_JTAG_IN_EP3_STATE_R { + USB_SERIAL_JTAG_IN_EP3_STATE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:8 - Write data address of IN endpoint 3."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep3_wr_addr(&self) -> USB_SERIAL_JTAG_IN_EP3_WR_ADDR_R { + USB_SERIAL_JTAG_IN_EP3_WR_ADDR_R::new(((self.bits >> 2) & 0x7f) as u8) + } + #[doc = "Bits 9:15 - Read data address of IN endpoint 3."] + #[inline(always)] + pub fn usb_serial_jtag_in_ep3_rd_addr(&self) -> USB_SERIAL_JTAG_IN_EP3_RD_ADDR_R { + USB_SERIAL_JTAG_IN_EP3_RD_ADDR_R::new(((self.bits >> 9) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IN_EP3_ST") + .field( + "usb_serial_jtag_in_ep3_state", + &format_args!("{}", self.usb_serial_jtag_in_ep3_state().bits()), + ) + .field( + "usb_serial_jtag_in_ep3_wr_addr", + &format_args!("{}", self.usb_serial_jtag_in_ep3_wr_addr().bits()), + ) + .field( + "usb_serial_jtag_in_ep3_rd_addr", + &format_args!("{}", self.usb_serial_jtag_in_ep3_rd_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "JTAG IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep3_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IN_EP3_ST_SPEC; +impl crate::RegisterSpec for IN_EP3_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`in_ep3_st::R`](R) reader structure"] +impl crate::Readable for IN_EP3_ST_SPEC {} +#[doc = "`reset()` method sets IN_EP3_ST to value 0x01"] +impl crate::Resettable for IN_EP3_ST_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/esp32p4/src/usb_device/int_clr.rs b/esp32p4/src/usb_device/int_clr.rs new file mode 100644 index 0000000000..c8443ab512 --- /dev/null +++ b/esp32p4/src/usb_device/int_clr.rs @@ -0,0 +1,192 @@ +#[doc = "Register `INT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR` writer - Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."] +pub type USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SOF_INT_CLR` writer - Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt."] +pub type USB_SERIAL_JTAG_SOF_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR` writer - Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR` writer - Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."] +pub type USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_PID_ERR_INT_CLR` writer - Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_PID_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_CRC5_ERR_INT_CLR` writer - Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_CRC16_ERR_INT_CLR` writer - Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_STUFF_ERR_INT_CLR` writer - Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR` writer - Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt."] +pub type USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR` writer - Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt."] +pub type USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR` writer - Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."] +pub type USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR` writer - Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."] +pub type USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_RTS_CHG_INT_CLR` writer - Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt."] +pub type USB_SERIAL_JTAG_RTS_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_DTR_CHG_INT_CLR` writer - Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt."] +pub type USB_SERIAL_JTAG_DTR_CHG_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR` writer - Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt."] +pub type USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR` writer - Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt."] +pub type USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W { + #[doc = "Bit 0 - Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_jtag_in_flush_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_W { + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_W::new(self, 0) + } + #[doc = "Bit 1 - Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_sof_int_clr(&mut self) -> USB_SERIAL_JTAG_SOF_INT_CLR_W { + USB_SERIAL_JTAG_SOF_INT_CLR_W::new(self, 1) + } + #[doc = "Bit 2 - Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_serial_out_recv_pkt_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_W { + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_W::new(self, 2) + } + #[doc = "Bit 3 - Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_serial_in_empty_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_W { + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_W::new(self, 3) + } + #[doc = "Bit 4 - Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_pid_err_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_PID_ERR_INT_CLR_W { + USB_SERIAL_JTAG_PID_ERR_INT_CLR_W::new(self, 4) + } + #[doc = "Bit 5 - Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_crc5_err_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_W { + USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_W::new(self, 5) + } + #[doc = "Bit 6 - Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_crc16_err_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_W { + USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_W::new(self, 6) + } + #[doc = "Bit 7 - Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_stuff_err_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_W { + USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_W::new(self, 7) + } + #[doc = "Bit 8 - Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_in_token_rec_in_ep1_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_W { + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_usb_bus_reset_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_W { + USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_W::new(self, 9) + } + #[doc = "Bit 10 - Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_out_ep1_zero_payload_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_W { + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_W::new(self, 10) + } + #[doc = "Bit 11 - Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_out_ep2_zero_payload_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_W { + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_W::new(self, 11) + } + #[doc = "Bit 12 - Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_rts_chg_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_RTS_CHG_INT_CLR_W { + USB_SERIAL_JTAG_RTS_CHG_INT_CLR_W::new(self, 12) + } + #[doc = "Bit 13 - Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_dtr_chg_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_DTR_CHG_INT_CLR_W { + USB_SERIAL_JTAG_DTR_CHG_INT_CLR_W::new(self, 13) + } + #[doc = "Bit 14 - Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_get_line_code_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_W { + USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_W::new(self, 14) + } + #[doc = "Bit 15 - Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_set_line_code_int_clr( + &mut self, + ) -> USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_W { + USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt clear status register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_CLR_SPEC; +impl crate::RegisterSpec for INT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"] +impl crate::Writable for INT_CLR_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_CLR to value 0"] +impl crate::Resettable for INT_CLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/int_ena.rs b/esp32p4/src/usb_device/int_ena.rs new file mode 100644 index 0000000000..d481dba124 --- /dev/null +++ b/esp32p4/src/usb_device/int_ena.rs @@ -0,0 +1,403 @@ +#[doc = "Register `INT_ENA` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ENA` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."] +pub type USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."] +pub type USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SOF_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt."] +pub type USB_SERIAL_JTAG_SOF_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SOF_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt."] +pub type USB_SERIAL_JTAG_SOF_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."] +pub type USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."] +pub type USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_PID_ERR_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_PID_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_PID_ERR_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_PID_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_CRC5_ERR_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_CRC5_ERR_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_CRC16_ERR_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_CRC16_ERR_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_STUFF_ERR_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_STUFF_ERR_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt."] +pub type USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt."] +pub type USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt."] +pub type USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt."] +pub type USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."] +pub type USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."] +pub type USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."] +pub type USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."] +pub type USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_RTS_CHG_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt."] +pub type USB_SERIAL_JTAG_RTS_CHG_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_RTS_CHG_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt."] +pub type USB_SERIAL_JTAG_RTS_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_DTR_CHG_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt."] +pub type USB_SERIAL_JTAG_DTR_CHG_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_DTR_CHG_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt."] +pub type USB_SERIAL_JTAG_DTR_CHG_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt."] +pub type USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt."] +pub type USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA` reader - The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt."] +pub type USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA` writer - The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt."] +pub type USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_jtag_in_flush_int_ena(&self) -> USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_R { + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_sof_int_ena(&self) -> USB_SERIAL_JTAG_SOF_INT_ENA_R { + USB_SERIAL_JTAG_SOF_INT_ENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_serial_out_recv_pkt_int_ena( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_R { + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_serial_in_empty_int_ena( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_R { + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_pid_err_int_ena(&self) -> USB_SERIAL_JTAG_PID_ERR_INT_ENA_R { + USB_SERIAL_JTAG_PID_ERR_INT_ENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_crc5_err_int_ena(&self) -> USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_R { + USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_crc16_err_int_ena(&self) -> USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_R { + USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_stuff_err_int_ena(&self) -> USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_R { + USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_in_token_rec_in_ep1_int_ena( + &self, + ) -> USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_R { + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_usb_bus_reset_int_ena(&self) -> USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_R { + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep1_zero_payload_int_ena( + &self, + ) -> USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_R { + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep2_zero_payload_int_ena( + &self, + ) -> USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_R { + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_rts_chg_int_ena(&self) -> USB_SERIAL_JTAG_RTS_CHG_INT_ENA_R { + USB_SERIAL_JTAG_RTS_CHG_INT_ENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_dtr_chg_int_ena(&self) -> USB_SERIAL_JTAG_DTR_CHG_INT_ENA_R { + USB_SERIAL_JTAG_DTR_CHG_INT_ENA_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_get_line_code_int_ena(&self) -> USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_R { + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_set_line_code_int_ena(&self) -> USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_R { + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ENA") + .field( + "usb_serial_jtag_jtag_in_flush_int_ena", + &format_args!("{}", self.usb_serial_jtag_jtag_in_flush_int_ena().bit()), + ) + .field( + "usb_serial_jtag_sof_int_ena", + &format_args!("{}", self.usb_serial_jtag_sof_int_ena().bit()), + ) + .field( + "usb_serial_jtag_serial_out_recv_pkt_int_ena", + &format_args!( + "{}", + self.usb_serial_jtag_serial_out_recv_pkt_int_ena().bit() + ), + ) + .field( + "usb_serial_jtag_serial_in_empty_int_ena", + &format_args!("{}", self.usb_serial_jtag_serial_in_empty_int_ena().bit()), + ) + .field( + "usb_serial_jtag_pid_err_int_ena", + &format_args!("{}", self.usb_serial_jtag_pid_err_int_ena().bit()), + ) + .field( + "usb_serial_jtag_crc5_err_int_ena", + &format_args!("{}", self.usb_serial_jtag_crc5_err_int_ena().bit()), + ) + .field( + "usb_serial_jtag_crc16_err_int_ena", + &format_args!("{}", self.usb_serial_jtag_crc16_err_int_ena().bit()), + ) + .field( + "usb_serial_jtag_stuff_err_int_ena", + &format_args!("{}", self.usb_serial_jtag_stuff_err_int_ena().bit()), + ) + .field( + "usb_serial_jtag_in_token_rec_in_ep1_int_ena", + &format_args!( + "{}", + self.usb_serial_jtag_in_token_rec_in_ep1_int_ena().bit() + ), + ) + .field( + "usb_serial_jtag_usb_bus_reset_int_ena", + &format_args!("{}", self.usb_serial_jtag_usb_bus_reset_int_ena().bit()), + ) + .field( + "usb_serial_jtag_out_ep1_zero_payload_int_ena", + &format_args!( + "{}", + self.usb_serial_jtag_out_ep1_zero_payload_int_ena().bit() + ), + ) + .field( + "usb_serial_jtag_out_ep2_zero_payload_int_ena", + &format_args!( + "{}", + self.usb_serial_jtag_out_ep2_zero_payload_int_ena().bit() + ), + ) + .field( + "usb_serial_jtag_rts_chg_int_ena", + &format_args!("{}", self.usb_serial_jtag_rts_chg_int_ena().bit()), + ) + .field( + "usb_serial_jtag_dtr_chg_int_ena", + &format_args!("{}", self.usb_serial_jtag_dtr_chg_int_ena().bit()), + ) + .field( + "usb_serial_jtag_get_line_code_int_ena", + &format_args!("{}", self.usb_serial_jtag_get_line_code_int_ena().bit()), + ) + .field( + "usb_serial_jtag_set_line_code_int_ena", + &format_args!("{}", self.usb_serial_jtag_set_line_code_int_ena().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_jtag_in_flush_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_W { + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_W::new(self, 0) + } + #[doc = "Bit 1 - The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_sof_int_ena(&mut self) -> USB_SERIAL_JTAG_SOF_INT_ENA_W { + USB_SERIAL_JTAG_SOF_INT_ENA_W::new(self, 1) + } + #[doc = "Bit 2 - The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_serial_out_recv_pkt_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_W { + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_W::new(self, 2) + } + #[doc = "Bit 3 - The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_serial_in_empty_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_W { + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_W::new(self, 3) + } + #[doc = "Bit 4 - The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_pid_err_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_PID_ERR_INT_ENA_W { + USB_SERIAL_JTAG_PID_ERR_INT_ENA_W::new(self, 4) + } + #[doc = "Bit 5 - The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_crc5_err_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_W { + USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_W::new(self, 5) + } + #[doc = "Bit 6 - The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_crc16_err_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_W { + USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_W::new(self, 6) + } + #[doc = "Bit 7 - The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_stuff_err_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_W { + USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_W::new(self, 7) + } + #[doc = "Bit 8 - The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_in_token_rec_in_ep1_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_W { + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_W::new(self, 8) + } + #[doc = "Bit 9 - The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_usb_bus_reset_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_W { + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_W::new(self, 9) + } + #[doc = "Bit 10 - The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_out_ep1_zero_payload_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_W { + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_W::new(self, 10) + } + #[doc = "Bit 11 - The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_out_ep2_zero_payload_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_W { + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_W::new(self, 11) + } + #[doc = "Bit 12 - The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_rts_chg_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_RTS_CHG_INT_ENA_W { + USB_SERIAL_JTAG_RTS_CHG_INT_ENA_W::new(self, 12) + } + #[doc = "Bit 13 - The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_dtr_chg_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_DTR_CHG_INT_ENA_W { + USB_SERIAL_JTAG_DTR_CHG_INT_ENA_W::new(self, 13) + } + #[doc = "Bit 14 - The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_get_line_code_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_W { + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_W::new(self, 14) + } + #[doc = "Bit 15 - The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_set_line_code_int_ena( + &mut self, + ) -> USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_W { + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt enable status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ENA_SPEC; +impl crate::RegisterSpec for INT_ENA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"] +impl crate::Readable for INT_ENA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"] +impl crate::Writable for INT_ENA_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_ENA to value 0"] +impl crate::Resettable for INT_ENA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/int_raw.rs b/esp32p4/src/usb_device/int_raw.rs new file mode 100644 index 0000000000..50993ed645 --- /dev/null +++ b/esp32p4/src/usb_device/int_raw.rs @@ -0,0 +1,403 @@ +#[doc = "Register `INT_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `INT_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW` reader - The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG."] +pub type USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW` writer - The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG."] +pub type USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SOF_INT_RAW` reader - The raw interrupt bit turns to high level when SOF frame is received."] +pub type USB_SERIAL_JTAG_SOF_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SOF_INT_RAW` writer - The raw interrupt bit turns to high level when SOF frame is received."] +pub type USB_SERIAL_JTAG_SOF_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW` reader - The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW` writer - The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW` reader - The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty."] +pub type USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW` writer - The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty."] +pub type USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_PID_ERR_INT_RAW` reader - The raw interrupt bit turns to high level when pid error is detected."] +pub type USB_SERIAL_JTAG_PID_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_PID_ERR_INT_RAW` writer - The raw interrupt bit turns to high level when pid error is detected."] +pub type USB_SERIAL_JTAG_PID_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_CRC5_ERR_INT_RAW` reader - The raw interrupt bit turns to high level when CRC5 error is detected."] +pub type USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_CRC5_ERR_INT_RAW` writer - The raw interrupt bit turns to high level when CRC5 error is detected."] +pub type USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_CRC16_ERR_INT_RAW` reader - The raw interrupt bit turns to high level when CRC16 error is detected."] +pub type USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_CRC16_ERR_INT_RAW` writer - The raw interrupt bit turns to high level when CRC16 error is detected."] +pub type USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_STUFF_ERR_INT_RAW` reader - The raw interrupt bit turns to high level when stuff error is detected."] +pub type USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_STUFF_ERR_INT_RAW` writer - The raw interrupt bit turns to high level when stuff error is detected."] +pub type USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW` reader - The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received."] +pub type USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW` writer - The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received."] +pub type USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW` reader - The raw interrupt bit turns to high level when usb bus reset is detected."] +pub type USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW` writer - The raw interrupt bit turns to high level when usb bus reset is detected."] +pub type USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW` reader - The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload."] +pub type USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW` writer - The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload."] +pub type USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW` reader - The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload."] +pub type USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW` writer - The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload."] +pub type USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_RTS_CHG_INT_RAW` reader - The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed."] +pub type USB_SERIAL_JTAG_RTS_CHG_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_RTS_CHG_INT_RAW` writer - The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed."] +pub type USB_SERIAL_JTAG_RTS_CHG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_DTR_CHG_INT_RAW` reader - The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed."] +pub type USB_SERIAL_JTAG_DTR_CHG_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_DTR_CHG_INT_RAW` writer - The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed."] +pub type USB_SERIAL_JTAG_DTR_CHG_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW` reader - The raw interrupt bit turns to high level when level of GET LINE CODING request is received."] +pub type USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW` writer - The raw interrupt bit turns to high level when level of GET LINE CODING request is received."] +pub type USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW` reader - The raw interrupt bit turns to high level when level of SET LINE CODING request is received."] +pub type USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW` writer - The raw interrupt bit turns to high level when level of SET LINE CODING request is received."] +pub type USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG."] + #[inline(always)] + pub fn usb_serial_jtag_jtag_in_flush_int_raw(&self) -> USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_R { + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when SOF frame is received."] + #[inline(always)] + pub fn usb_serial_jtag_sof_int_raw(&self) -> USB_SERIAL_JTAG_SOF_INT_RAW_R { + USB_SERIAL_JTAG_SOF_INT_RAW_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet."] + #[inline(always)] + pub fn usb_serial_jtag_serial_out_recv_pkt_int_raw( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_R { + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty."] + #[inline(always)] + pub fn usb_serial_jtag_serial_in_empty_int_raw( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_R { + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when pid error is detected."] + #[inline(always)] + pub fn usb_serial_jtag_pid_err_int_raw(&self) -> USB_SERIAL_JTAG_PID_ERR_INT_RAW_R { + USB_SERIAL_JTAG_PID_ERR_INT_RAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when CRC5 error is detected."] + #[inline(always)] + pub fn usb_serial_jtag_crc5_err_int_raw(&self) -> USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_R { + USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when CRC16 error is detected."] + #[inline(always)] + pub fn usb_serial_jtag_crc16_err_int_raw(&self) -> USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_R { + USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when stuff error is detected."] + #[inline(always)] + pub fn usb_serial_jtag_stuff_err_int_raw(&self) -> USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_R { + USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received."] + #[inline(always)] + pub fn usb_serial_jtag_in_token_rec_in_ep1_int_raw( + &self, + ) -> USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_R { + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when usb bus reset is detected."] + #[inline(always)] + pub fn usb_serial_jtag_usb_bus_reset_int_raw(&self) -> USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_R { + USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep1_zero_payload_int_raw( + &self, + ) -> USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_R { + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep2_zero_payload_int_raw( + &self, + ) -> USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_R { + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed."] + #[inline(always)] + pub fn usb_serial_jtag_rts_chg_int_raw(&self) -> USB_SERIAL_JTAG_RTS_CHG_INT_RAW_R { + USB_SERIAL_JTAG_RTS_CHG_INT_RAW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed."] + #[inline(always)] + pub fn usb_serial_jtag_dtr_chg_int_raw(&self) -> USB_SERIAL_JTAG_DTR_CHG_INT_RAW_R { + USB_SERIAL_JTAG_DTR_CHG_INT_RAW_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The raw interrupt bit turns to high level when level of GET LINE CODING request is received."] + #[inline(always)] + pub fn usb_serial_jtag_get_line_code_int_raw(&self) -> USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_R { + USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The raw interrupt bit turns to high level when level of SET LINE CODING request is received."] + #[inline(always)] + pub fn usb_serial_jtag_set_line_code_int_raw(&self) -> USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_R { + USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_RAW") + .field( + "usb_serial_jtag_jtag_in_flush_int_raw", + &format_args!("{}", self.usb_serial_jtag_jtag_in_flush_int_raw().bit()), + ) + .field( + "usb_serial_jtag_sof_int_raw", + &format_args!("{}", self.usb_serial_jtag_sof_int_raw().bit()), + ) + .field( + "usb_serial_jtag_serial_out_recv_pkt_int_raw", + &format_args!( + "{}", + self.usb_serial_jtag_serial_out_recv_pkt_int_raw().bit() + ), + ) + .field( + "usb_serial_jtag_serial_in_empty_int_raw", + &format_args!("{}", self.usb_serial_jtag_serial_in_empty_int_raw().bit()), + ) + .field( + "usb_serial_jtag_pid_err_int_raw", + &format_args!("{}", self.usb_serial_jtag_pid_err_int_raw().bit()), + ) + .field( + "usb_serial_jtag_crc5_err_int_raw", + &format_args!("{}", self.usb_serial_jtag_crc5_err_int_raw().bit()), + ) + .field( + "usb_serial_jtag_crc16_err_int_raw", + &format_args!("{}", self.usb_serial_jtag_crc16_err_int_raw().bit()), + ) + .field( + "usb_serial_jtag_stuff_err_int_raw", + &format_args!("{}", self.usb_serial_jtag_stuff_err_int_raw().bit()), + ) + .field( + "usb_serial_jtag_in_token_rec_in_ep1_int_raw", + &format_args!( + "{}", + self.usb_serial_jtag_in_token_rec_in_ep1_int_raw().bit() + ), + ) + .field( + "usb_serial_jtag_usb_bus_reset_int_raw", + &format_args!("{}", self.usb_serial_jtag_usb_bus_reset_int_raw().bit()), + ) + .field( + "usb_serial_jtag_out_ep1_zero_payload_int_raw", + &format_args!( + "{}", + self.usb_serial_jtag_out_ep1_zero_payload_int_raw().bit() + ), + ) + .field( + "usb_serial_jtag_out_ep2_zero_payload_int_raw", + &format_args!( + "{}", + self.usb_serial_jtag_out_ep2_zero_payload_int_raw().bit() + ), + ) + .field( + "usb_serial_jtag_rts_chg_int_raw", + &format_args!("{}", self.usb_serial_jtag_rts_chg_int_raw().bit()), + ) + .field( + "usb_serial_jtag_dtr_chg_int_raw", + &format_args!("{}", self.usb_serial_jtag_dtr_chg_int_raw().bit()), + ) + .field( + "usb_serial_jtag_get_line_code_int_raw", + &format_args!("{}", self.usb_serial_jtag_get_line_code_int_raw().bit()), + ) + .field( + "usb_serial_jtag_set_line_code_int_raw", + &format_args!("{}", self.usb_serial_jtag_set_line_code_int_raw().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_jtag_in_flush_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_W { + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_W::new(self, 0) + } + #[doc = "Bit 1 - The raw interrupt bit turns to high level when SOF frame is received."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_sof_int_raw(&mut self) -> USB_SERIAL_JTAG_SOF_INT_RAW_W { + USB_SERIAL_JTAG_SOF_INT_RAW_W::new(self, 1) + } + #[doc = "Bit 2 - The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_serial_out_recv_pkt_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_W { + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_W::new(self, 2) + } + #[doc = "Bit 3 - The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_serial_in_empty_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_W { + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_W::new(self, 3) + } + #[doc = "Bit 4 - The raw interrupt bit turns to high level when pid error is detected."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_pid_err_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_PID_ERR_INT_RAW_W { + USB_SERIAL_JTAG_PID_ERR_INT_RAW_W::new(self, 4) + } + #[doc = "Bit 5 - The raw interrupt bit turns to high level when CRC5 error is detected."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_crc5_err_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_W { + USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_W::new(self, 5) + } + #[doc = "Bit 6 - The raw interrupt bit turns to high level when CRC16 error is detected."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_crc16_err_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_W { + USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_W::new(self, 6) + } + #[doc = "Bit 7 - The raw interrupt bit turns to high level when stuff error is detected."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_stuff_err_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_W { + USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_W::new(self, 7) + } + #[doc = "Bit 8 - The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_in_token_rec_in_ep1_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_W { + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_W::new(self, 8) + } + #[doc = "Bit 9 - The raw interrupt bit turns to high level when usb bus reset is detected."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_usb_bus_reset_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_W { + USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_W::new(self, 9) + } + #[doc = "Bit 10 - The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_out_ep1_zero_payload_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_W { + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_W::new(self, 10) + } + #[doc = "Bit 11 - The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_out_ep2_zero_payload_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_W { + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_W::new(self, 11) + } + #[doc = "Bit 12 - The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_rts_chg_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_RTS_CHG_INT_RAW_W { + USB_SERIAL_JTAG_RTS_CHG_INT_RAW_W::new(self, 12) + } + #[doc = "Bit 13 - The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_dtr_chg_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_DTR_CHG_INT_RAW_W { + USB_SERIAL_JTAG_DTR_CHG_INT_RAW_W::new(self, 13) + } + #[doc = "Bit 14 - The raw interrupt bit turns to high level when level of GET LINE CODING request is received."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_get_line_code_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_W { + USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_W::new(self, 14) + } + #[doc = "Bit 15 - The raw interrupt bit turns to high level when level of SET LINE CODING request is received."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_set_line_code_int_raw( + &mut self, + ) -> USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_W { + USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_W::new(self, 15) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Interrupt raw status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_RAW_SPEC; +impl crate::RegisterSpec for INT_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"] +impl crate::Readable for INT_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"] +impl crate::Writable for INT_RAW_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INT_RAW to value 0x08"] +impl crate::Resettable for INT_RAW_SPEC { + const RESET_VALUE: Self::Ux = 0x08; +} diff --git a/esp32p4/src/usb_device/int_st.rs b/esp32p4/src/usb_device/int_st.rs new file mode 100644 index 0000000000..ace431408c --- /dev/null +++ b/esp32p4/src/usb_device/int_st.rs @@ -0,0 +1,226 @@ +#[doc = "Register `INT_ST` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."] +pub type USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SOF_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt."] +pub type USB_SERIAL_JTAG_SOF_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."] +pub type USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_PID_ERR_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_PID_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_CRC5_ERR_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_CRC5_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_CRC16_ERR_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_CRC16_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_STUFF_ERR_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt."] +pub type USB_SERIAL_JTAG_STUFF_ERR_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt."] +pub type USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt."] +pub type USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."] +pub type USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."] +pub type USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_RTS_CHG_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt."] +pub type USB_SERIAL_JTAG_RTS_CHG_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_DTR_CHG_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt."] +pub type USB_SERIAL_JTAG_DTR_CHG_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt."] +pub type USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST` reader - The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt."] +pub type USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_jtag_in_flush_int_st(&self) -> USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_R { + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_sof_int_st(&self) -> USB_SERIAL_JTAG_SOF_INT_ST_R { + USB_SERIAL_JTAG_SOF_INT_ST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_serial_out_recv_pkt_int_st( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_R { + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_serial_in_empty_int_st( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_R { + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_pid_err_int_st(&self) -> USB_SERIAL_JTAG_PID_ERR_INT_ST_R { + USB_SERIAL_JTAG_PID_ERR_INT_ST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_crc5_err_int_st(&self) -> USB_SERIAL_JTAG_CRC5_ERR_INT_ST_R { + USB_SERIAL_JTAG_CRC5_ERR_INT_ST_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_crc16_err_int_st(&self) -> USB_SERIAL_JTAG_CRC16_ERR_INT_ST_R { + USB_SERIAL_JTAG_CRC16_ERR_INT_ST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_stuff_err_int_st(&self) -> USB_SERIAL_JTAG_STUFF_ERR_INT_ST_R { + USB_SERIAL_JTAG_STUFF_ERR_INT_ST_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_in_token_rec_in_ep1_int_st( + &self, + ) -> USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_R { + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_usb_bus_reset_int_st(&self) -> USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_R { + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep1_zero_payload_int_st( + &self, + ) -> USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_R { + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep2_zero_payload_int_st( + &self, + ) -> USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_R { + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_rts_chg_int_st(&self) -> USB_SERIAL_JTAG_RTS_CHG_INT_ST_R { + USB_SERIAL_JTAG_RTS_CHG_INT_ST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_dtr_chg_int_st(&self) -> USB_SERIAL_JTAG_DTR_CHG_INT_ST_R { + USB_SERIAL_JTAG_DTR_CHG_INT_ST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_get_line_code_int_st(&self) -> USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_R { + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt."] + #[inline(always)] + pub fn usb_serial_jtag_set_line_code_int_st(&self) -> USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_R { + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("INT_ST") + .field( + "usb_serial_jtag_jtag_in_flush_int_st", + &format_args!("{}", self.usb_serial_jtag_jtag_in_flush_int_st().bit()), + ) + .field( + "usb_serial_jtag_sof_int_st", + &format_args!("{}", self.usb_serial_jtag_sof_int_st().bit()), + ) + .field( + "usb_serial_jtag_serial_out_recv_pkt_int_st", + &format_args!( + "{}", + self.usb_serial_jtag_serial_out_recv_pkt_int_st().bit() + ), + ) + .field( + "usb_serial_jtag_serial_in_empty_int_st", + &format_args!("{}", self.usb_serial_jtag_serial_in_empty_int_st().bit()), + ) + .field( + "usb_serial_jtag_pid_err_int_st", + &format_args!("{}", self.usb_serial_jtag_pid_err_int_st().bit()), + ) + .field( + "usb_serial_jtag_crc5_err_int_st", + &format_args!("{}", self.usb_serial_jtag_crc5_err_int_st().bit()), + ) + .field( + "usb_serial_jtag_crc16_err_int_st", + &format_args!("{}", self.usb_serial_jtag_crc16_err_int_st().bit()), + ) + .field( + "usb_serial_jtag_stuff_err_int_st", + &format_args!("{}", self.usb_serial_jtag_stuff_err_int_st().bit()), + ) + .field( + "usb_serial_jtag_in_token_rec_in_ep1_int_st", + &format_args!( + "{}", + self.usb_serial_jtag_in_token_rec_in_ep1_int_st().bit() + ), + ) + .field( + "usb_serial_jtag_usb_bus_reset_int_st", + &format_args!("{}", self.usb_serial_jtag_usb_bus_reset_int_st().bit()), + ) + .field( + "usb_serial_jtag_out_ep1_zero_payload_int_st", + &format_args!( + "{}", + self.usb_serial_jtag_out_ep1_zero_payload_int_st().bit() + ), + ) + .field( + "usb_serial_jtag_out_ep2_zero_payload_int_st", + &format_args!( + "{}", + self.usb_serial_jtag_out_ep2_zero_payload_int_st().bit() + ), + ) + .field( + "usb_serial_jtag_rts_chg_int_st", + &format_args!("{}", self.usb_serial_jtag_rts_chg_int_st().bit()), + ) + .field( + "usb_serial_jtag_dtr_chg_int_st", + &format_args!("{}", self.usb_serial_jtag_dtr_chg_int_st().bit()), + ) + .field( + "usb_serial_jtag_get_line_code_int_st", + &format_args!("{}", self.usb_serial_jtag_get_line_code_int_st().bit()), + ) + .field( + "usb_serial_jtag_set_line_code_int_st", + &format_args!("{}", self.usb_serial_jtag_set_line_code_int_st().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ST_SPEC; +impl crate::RegisterSpec for INT_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_st::R`](R) reader structure"] +impl crate::Readable for INT_ST_SPEC {} +#[doc = "`reset()` method sets INT_ST to value 0"] +impl crate::Resettable for INT_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/jfifo_st.rs b/esp32p4/src/usb_device/jfifo_st.rs new file mode 100644 index 0000000000..a2c2d00fd4 --- /dev/null +++ b/esp32p4/src/usb_device/jfifo_st.rs @@ -0,0 +1,155 @@ +#[doc = "Register `JFIFO_ST` reader"] +pub type R = crate::R; +#[doc = "Register `JFIFO_ST` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_IN_FIFO_CNT` reader - JTAT in fifo counter."] +pub type USB_SERIAL_JTAG_IN_FIFO_CNT_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_FIFO_EMPTY` reader - 1: JTAG in fifo is empty."] +pub type USB_SERIAL_JTAG_IN_FIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_FIFO_FULL` reader - 1: JTAG in fifo is full."] +pub type USB_SERIAL_JTAG_IN_FIFO_FULL_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_FIFO_CNT` reader - JTAT out fifo counter."] +pub type USB_SERIAL_JTAG_OUT_FIFO_CNT_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_FIFO_EMPTY` reader - 1: JTAG out fifo is empty."] +pub type USB_SERIAL_JTAG_OUT_FIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_FIFO_FULL` reader - 1: JTAG out fifo is full."] +pub type USB_SERIAL_JTAG_OUT_FIFO_FULL_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_FIFO_RESET` reader - Write 1 to reset JTAG in fifo."] +pub type USB_SERIAL_JTAG_IN_FIFO_RESET_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_IN_FIFO_RESET` writer - Write 1 to reset JTAG in fifo."] +pub type USB_SERIAL_JTAG_IN_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_OUT_FIFO_RESET` reader - Write 1 to reset JTAG out fifo."] +pub type USB_SERIAL_JTAG_OUT_FIFO_RESET_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_FIFO_RESET` writer - Write 1 to reset JTAG out fifo."] +pub type USB_SERIAL_JTAG_OUT_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - JTAT in fifo counter."] + #[inline(always)] + pub fn usb_serial_jtag_in_fifo_cnt(&self) -> USB_SERIAL_JTAG_IN_FIFO_CNT_R { + USB_SERIAL_JTAG_IN_FIFO_CNT_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - 1: JTAG in fifo is empty."] + #[inline(always)] + pub fn usb_serial_jtag_in_fifo_empty(&self) -> USB_SERIAL_JTAG_IN_FIFO_EMPTY_R { + USB_SERIAL_JTAG_IN_FIFO_EMPTY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1: JTAG in fifo is full."] + #[inline(always)] + pub fn usb_serial_jtag_in_fifo_full(&self) -> USB_SERIAL_JTAG_IN_FIFO_FULL_R { + USB_SERIAL_JTAG_IN_FIFO_FULL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - JTAT out fifo counter."] + #[inline(always)] + pub fn usb_serial_jtag_out_fifo_cnt(&self) -> USB_SERIAL_JTAG_OUT_FIFO_CNT_R { + USB_SERIAL_JTAG_OUT_FIFO_CNT_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - 1: JTAG out fifo is empty."] + #[inline(always)] + pub fn usb_serial_jtag_out_fifo_empty(&self) -> USB_SERIAL_JTAG_OUT_FIFO_EMPTY_R { + USB_SERIAL_JTAG_OUT_FIFO_EMPTY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - 1: JTAG out fifo is full."] + #[inline(always)] + pub fn usb_serial_jtag_out_fifo_full(&self) -> USB_SERIAL_JTAG_OUT_FIFO_FULL_R { + USB_SERIAL_JTAG_OUT_FIFO_FULL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Write 1 to reset JTAG in fifo."] + #[inline(always)] + pub fn usb_serial_jtag_in_fifo_reset(&self) -> USB_SERIAL_JTAG_IN_FIFO_RESET_R { + USB_SERIAL_JTAG_IN_FIFO_RESET_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write 1 to reset JTAG out fifo."] + #[inline(always)] + pub fn usb_serial_jtag_out_fifo_reset(&self) -> USB_SERIAL_JTAG_OUT_FIFO_RESET_R { + USB_SERIAL_JTAG_OUT_FIFO_RESET_R::new(((self.bits >> 9) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("JFIFO_ST") + .field( + "usb_serial_jtag_in_fifo_cnt", + &format_args!("{}", self.usb_serial_jtag_in_fifo_cnt().bits()), + ) + .field( + "usb_serial_jtag_in_fifo_empty", + &format_args!("{}", self.usb_serial_jtag_in_fifo_empty().bit()), + ) + .field( + "usb_serial_jtag_in_fifo_full", + &format_args!("{}", self.usb_serial_jtag_in_fifo_full().bit()), + ) + .field( + "usb_serial_jtag_out_fifo_cnt", + &format_args!("{}", self.usb_serial_jtag_out_fifo_cnt().bits()), + ) + .field( + "usb_serial_jtag_out_fifo_empty", + &format_args!("{}", self.usb_serial_jtag_out_fifo_empty().bit()), + ) + .field( + "usb_serial_jtag_out_fifo_full", + &format_args!("{}", self.usb_serial_jtag_out_fifo_full().bit()), + ) + .field( + "usb_serial_jtag_in_fifo_reset", + &format_args!("{}", self.usb_serial_jtag_in_fifo_reset().bit()), + ) + .field( + "usb_serial_jtag_out_fifo_reset", + &format_args!("{}", self.usb_serial_jtag_out_fifo_reset().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 8 - Write 1 to reset JTAG in fifo."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_in_fifo_reset( + &mut self, + ) -> USB_SERIAL_JTAG_IN_FIFO_RESET_W { + USB_SERIAL_JTAG_IN_FIFO_RESET_W::new(self, 8) + } + #[doc = "Bit 9 - Write 1 to reset JTAG out fifo."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_out_fifo_reset( + &mut self, + ) -> USB_SERIAL_JTAG_OUT_FIFO_RESET_W { + USB_SERIAL_JTAG_OUT_FIFO_RESET_W::new(self, 9) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "JTAG FIFO status and control registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`jfifo_st::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`jfifo_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct JFIFO_ST_SPEC; +impl crate::RegisterSpec for JFIFO_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`jfifo_st::R`](R) reader structure"] +impl crate::Readable for JFIFO_ST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`jfifo_st::W`](W) writer structure"] +impl crate::Writable for JFIFO_ST_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets JFIFO_ST to value 0x44"] +impl crate::Resettable for JFIFO_ST_SPEC { + const RESET_VALUE: Self::Ux = 0x44; +} diff --git a/esp32p4/src/usb_device/mem_conf.rs b/esp32p4/src/usb_device/mem_conf.rs new file mode 100644 index 0000000000..8ef3593c11 --- /dev/null +++ b/esp32p4/src/usb_device/mem_conf.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MEM_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `MEM_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_USB_MEM_PD` reader - 1: power down usb memory."] +pub type USB_SERIAL_JTAG_USB_MEM_PD_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_USB_MEM_PD` writer - 1: power down usb memory."] +pub type USB_SERIAL_JTAG_USB_MEM_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_USB_MEM_CLK_EN` reader - 1: Force clock on for usb memory."] +pub type USB_SERIAL_JTAG_USB_MEM_CLK_EN_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_USB_MEM_CLK_EN` writer - 1: Force clock on for usb memory."] +pub type USB_SERIAL_JTAG_USB_MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1: power down usb memory."] + #[inline(always)] + pub fn usb_serial_jtag_usb_mem_pd(&self) -> USB_SERIAL_JTAG_USB_MEM_PD_R { + USB_SERIAL_JTAG_USB_MEM_PD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: Force clock on for usb memory."] + #[inline(always)] + pub fn usb_serial_jtag_usb_mem_clk_en(&self) -> USB_SERIAL_JTAG_USB_MEM_CLK_EN_R { + USB_SERIAL_JTAG_USB_MEM_CLK_EN_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MEM_CONF") + .field( + "usb_serial_jtag_usb_mem_pd", + &format_args!("{}", self.usb_serial_jtag_usb_mem_pd().bit()), + ) + .field( + "usb_serial_jtag_usb_mem_clk_en", + &format_args!("{}", self.usb_serial_jtag_usb_mem_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1: power down usb memory."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_usb_mem_pd(&mut self) -> USB_SERIAL_JTAG_USB_MEM_PD_W { + USB_SERIAL_JTAG_USB_MEM_PD_W::new(self, 0) + } + #[doc = "Bit 1 - 1: Force clock on for usb memory."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_usb_mem_clk_en( + &mut self, + ) -> USB_SERIAL_JTAG_USB_MEM_CLK_EN_W { + USB_SERIAL_JTAG_USB_MEM_CLK_EN_W::new(self, 1) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Memory power control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mem_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEM_CONF_SPEC; +impl crate::RegisterSpec for MEM_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mem_conf::R`](R) reader structure"] +impl crate::Readable for MEM_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mem_conf::W`](W) writer structure"] +impl crate::Writable for MEM_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MEM_CONF to value 0x02"] +impl crate::Resettable for MEM_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/esp32p4/src/usb_device/misc_conf.rs b/esp32p4/src/usb_device/misc_conf.rs new file mode 100644 index 0000000000..d327c01176 --- /dev/null +++ b/esp32p4/src/usb_device/misc_conf.rs @@ -0,0 +1,66 @@ +#[doc = "Register `MISC_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `MISC_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_CLK_EN` reader - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type USB_SERIAL_JTAG_CLK_EN_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_CLK_EN` writer - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] +pub type USB_SERIAL_JTAG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + pub fn usb_serial_jtag_clk_en(&self) -> USB_SERIAL_JTAG_CLK_EN_R { + USB_SERIAL_JTAG_CLK_EN_R::new((self.bits & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MISC_CONF") + .field( + "usb_serial_jtag_clk_en", + &format_args!("{}", self.usb_serial_jtag_clk_en().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_clk_en(&mut self) -> USB_SERIAL_JTAG_CLK_EN_W { + USB_SERIAL_JTAG_CLK_EN_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Clock enable control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`misc_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`misc_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MISC_CONF_SPEC; +impl crate::RegisterSpec for MISC_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`misc_conf::R`](R) reader structure"] +impl crate::Readable for MISC_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`misc_conf::W`](W) writer structure"] +impl crate::Writable for MISC_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MISC_CONF to value 0"] +impl crate::Resettable for MISC_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/out_ep0_st.rs b/esp32p4/src/usb_device/out_ep0_st.rs new file mode 100644 index 0000000000..4159ca03c2 --- /dev/null +++ b/esp32p4/src/usb_device/out_ep0_st.rs @@ -0,0 +1,61 @@ +#[doc = "Register `OUT_EP0_ST` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP0_STATE` reader - State of OUT Endpoint 0."] +pub type USB_SERIAL_JTAG_OUT_EP0_STATE_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP0_WR_ADDR` reader - Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0."] +pub type USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP0_RD_ADDR` reader - Read data address of OUT endpoint 0."] +pub type USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - State of OUT Endpoint 0."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep0_state(&self) -> USB_SERIAL_JTAG_OUT_EP0_STATE_R { + USB_SERIAL_JTAG_OUT_EP0_STATE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:8 - Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep0_wr_addr(&self) -> USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_R { + USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_R::new(((self.bits >> 2) & 0x7f) as u8) + } + #[doc = "Bits 9:15 - Read data address of OUT endpoint 0."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep0_rd_addr(&self) -> USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_R { + USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_R::new(((self.bits >> 9) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EP0_ST") + .field( + "usb_serial_jtag_out_ep0_state", + &format_args!("{}", self.usb_serial_jtag_out_ep0_state().bits()), + ) + .field( + "usb_serial_jtag_out_ep0_wr_addr", + &format_args!("{}", self.usb_serial_jtag_out_ep0_wr_addr().bits()), + ) + .field( + "usb_serial_jtag_out_ep0_rd_addr", + &format_args!("{}", self.usb_serial_jtag_out_ep0_rd_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Control OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep0_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EP0_ST_SPEC; +impl crate::RegisterSpec for OUT_EP0_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_ep0_st::R`](R) reader structure"] +impl crate::Readable for OUT_EP0_ST_SPEC {} +#[doc = "`reset()` method sets OUT_EP0_ST to value 0"] +impl crate::Resettable for OUT_EP0_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/out_ep1_st.rs b/esp32p4/src/usb_device/out_ep1_st.rs new file mode 100644 index 0000000000..e7613e55d6 --- /dev/null +++ b/esp32p4/src/usb_device/out_ep1_st.rs @@ -0,0 +1,72 @@ +#[doc = "Register `OUT_EP1_ST` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP1_STATE` reader - State of OUT Endpoint 1."] +pub type USB_SERIAL_JTAG_OUT_EP1_STATE_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP1_WR_ADDR` reader - Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1."] +pub type USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP1_RD_ADDR` reader - Read data address of OUT endpoint 1."] +pub type USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT` reader - Data count in OUT endpoint 1 when one packet is received."] +pub type USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - State of OUT Endpoint 1."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep1_state(&self) -> USB_SERIAL_JTAG_OUT_EP1_STATE_R { + USB_SERIAL_JTAG_OUT_EP1_STATE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:8 - Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep1_wr_addr(&self) -> USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_R { + USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_R::new(((self.bits >> 2) & 0x7f) as u8) + } + #[doc = "Bits 9:15 - Read data address of OUT endpoint 1."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep1_rd_addr(&self) -> USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_R { + USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_R::new(((self.bits >> 9) & 0x7f) as u8) + } + #[doc = "Bits 16:22 - Data count in OUT endpoint 1 when one packet is received."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep1_rec_data_cnt(&self) -> USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_R { + USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_R::new(((self.bits >> 16) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EP1_ST") + .field( + "usb_serial_jtag_out_ep1_state", + &format_args!("{}", self.usb_serial_jtag_out_ep1_state().bits()), + ) + .field( + "usb_serial_jtag_out_ep1_wr_addr", + &format_args!("{}", self.usb_serial_jtag_out_ep1_wr_addr().bits()), + ) + .field( + "usb_serial_jtag_out_ep1_rd_addr", + &format_args!("{}", self.usb_serial_jtag_out_ep1_rd_addr().bits()), + ) + .field( + "usb_serial_jtag_out_ep1_rec_data_cnt", + &format_args!("{}", self.usb_serial_jtag_out_ep1_rec_data_cnt().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "CDC-ACM OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep1_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EP1_ST_SPEC; +impl crate::RegisterSpec for OUT_EP1_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_ep1_st::R`](R) reader structure"] +impl crate::Readable for OUT_EP1_ST_SPEC {} +#[doc = "`reset()` method sets OUT_EP1_ST to value 0"] +impl crate::Resettable for OUT_EP1_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/out_ep2_st.rs b/esp32p4/src/usb_device/out_ep2_st.rs new file mode 100644 index 0000000000..f72735b251 --- /dev/null +++ b/esp32p4/src/usb_device/out_ep2_st.rs @@ -0,0 +1,61 @@ +#[doc = "Register `OUT_EP2_ST` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP2_STATE` reader - State of OUT Endpoint 2."] +pub type USB_SERIAL_JTAG_OUT_EP2_STATE_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP2_WR_ADDR` reader - Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2."] +pub type USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_OUT_EP2_RD_ADDR` reader - Read data address of OUT endpoint 2."] +pub type USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - State of OUT Endpoint 2."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep2_state(&self) -> USB_SERIAL_JTAG_OUT_EP2_STATE_R { + USB_SERIAL_JTAG_OUT_EP2_STATE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:8 - Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep2_wr_addr(&self) -> USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_R { + USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_R::new(((self.bits >> 2) & 0x7f) as u8) + } + #[doc = "Bits 9:15 - Read data address of OUT endpoint 2."] + #[inline(always)] + pub fn usb_serial_jtag_out_ep2_rd_addr(&self) -> USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_R { + USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_R::new(((self.bits >> 9) & 0x7f) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OUT_EP2_ST") + .field( + "usb_serial_jtag_out_ep2_state", + &format_args!("{}", self.usb_serial_jtag_out_ep2_state().bits()), + ) + .field( + "usb_serial_jtag_out_ep2_wr_addr", + &format_args!("{}", self.usb_serial_jtag_out_ep2_wr_addr().bits()), + ) + .field( + "usb_serial_jtag_out_ep2_rd_addr", + &format_args!("{}", self.usb_serial_jtag_out_ep2_rd_addr().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "JTAG OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep2_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OUT_EP2_ST_SPEC; +impl crate::RegisterSpec for OUT_EP2_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`out_ep2_st::R`](R) reader structure"] +impl crate::Readable for OUT_EP2_ST_SPEC {} +#[doc = "`reset()` method sets OUT_EP2_ST to value 0"] +impl crate::Resettable for OUT_EP2_ST_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/ser_afifo_config.rs b/esp32p4/src/usb_device/ser_afifo_config.rs new file mode 100644 index 0000000000..2c83b98b3f --- /dev/null +++ b/esp32p4/src/usb_device/ser_afifo_config.rs @@ -0,0 +1,163 @@ +#[doc = "Register `SER_AFIFO_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `SER_AFIFO_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR` reader - Write 1 to reset CDC_ACM IN async FIFO write clock domain."] +pub type USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR` writer - Write 1 to reset CDC_ACM IN async FIFO write clock domain."] +pub type USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD` reader - Write 1 to reset CDC_ACM IN async FIFO read clock domain."] +pub type USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD` writer - Write 1 to reset CDC_ACM IN async FIFO read clock domain."] +pub type USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR` reader - Write 1 to reset CDC_ACM OUT async FIFO write clock domain."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR` writer - Write 1 to reset CDC_ACM OUT async FIFO write clock domain."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD` reader - Write 1 to reset CDC_ACM OUT async FIFO read clock domain."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD` writer - Write 1 to reset CDC_ACM OUT async FIFO read clock domain."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY` reader - CDC_ACM OUTOUT async FIFO empty signal in read clock domain."] +pub type USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL` reader - CDC_ACM OUT IN async FIFO empty signal in write clock domain."] +pub type USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Write 1 to reset CDC_ACM IN async FIFO write clock domain."] + #[inline(always)] + pub fn usb_serial_jtag_serial_in_afifo_reset_wr( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_R { + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to reset CDC_ACM IN async FIFO read clock domain."] + #[inline(always)] + pub fn usb_serial_jtag_serial_in_afifo_reset_rd( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_R { + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 to reset CDC_ACM OUT async FIFO write clock domain."] + #[inline(always)] + pub fn usb_serial_jtag_serial_out_afifo_reset_wr( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_R { + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1 to reset CDC_ACM OUT async FIFO read clock domain."] + #[inline(always)] + pub fn usb_serial_jtag_serial_out_afifo_reset_rd( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_R { + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - CDC_ACM OUTOUT async FIFO empty signal in read clock domain."] + #[inline(always)] + pub fn usb_serial_jtag_serial_out_afifo_rempty( + &self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_R { + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - CDC_ACM OUT IN async FIFO empty signal in write clock domain."] + #[inline(always)] + pub fn usb_serial_jtag_serial_in_afifo_wfull(&self) -> USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_R { + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SER_AFIFO_CONFIG") + .field( + "usb_serial_jtag_serial_in_afifo_reset_wr", + &format_args!("{}", self.usb_serial_jtag_serial_in_afifo_reset_wr().bit()), + ) + .field( + "usb_serial_jtag_serial_in_afifo_reset_rd", + &format_args!("{}", self.usb_serial_jtag_serial_in_afifo_reset_rd().bit()), + ) + .field( + "usb_serial_jtag_serial_out_afifo_reset_wr", + &format_args!("{}", self.usb_serial_jtag_serial_out_afifo_reset_wr().bit()), + ) + .field( + "usb_serial_jtag_serial_out_afifo_reset_rd", + &format_args!("{}", self.usb_serial_jtag_serial_out_afifo_reset_rd().bit()), + ) + .field( + "usb_serial_jtag_serial_out_afifo_rempty", + &format_args!("{}", self.usb_serial_jtag_serial_out_afifo_rempty().bit()), + ) + .field( + "usb_serial_jtag_serial_in_afifo_wfull", + &format_args!("{}", self.usb_serial_jtag_serial_in_afifo_wfull().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to reset CDC_ACM IN async FIFO write clock domain."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_serial_in_afifo_reset_wr( + &mut self, + ) -> USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_W { + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to reset CDC_ACM IN async FIFO read clock domain."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_serial_in_afifo_reset_rd( + &mut self, + ) -> USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_W { + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to reset CDC_ACM OUT async FIFO write clock domain."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_serial_out_afifo_reset_wr( + &mut self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_W { + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to reset CDC_ACM OUT async FIFO read clock domain."] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_serial_out_afifo_reset_rd( + &mut self, + ) -> USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_W { + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Serial AFIFO configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ser_afifo_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ser_afifo_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SER_AFIFO_CONFIG_SPEC; +impl crate::RegisterSpec for SER_AFIFO_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ser_afifo_config::R`](R) reader structure"] +impl crate::Readable for SER_AFIFO_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ser_afifo_config::W`](W) writer structure"] +impl crate::Writable for SER_AFIFO_CONFIG_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SER_AFIFO_CONFIG to value 0x10"] +impl crate::Resettable for SER_AFIFO_CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/esp32p4/src/usb_device/set_line_code_w0.rs b/esp32p4/src/usb_device/set_line_code_w0.rs new file mode 100644 index 0000000000..60c98a098b --- /dev/null +++ b/esp32p4/src/usb_device/set_line_code_w0.rs @@ -0,0 +1,39 @@ +#[doc = "Register `SET_LINE_CODE_W0` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_DW_DTE_RATE` reader - The value of dwDTERate set by host through SET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_DW_DTE_RATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - The value of dwDTERate set by host through SET_LINE_CODING command."] + #[inline(always)] + pub fn usb_serial_jtag_dw_dte_rate(&self) -> USB_SERIAL_JTAG_DW_DTE_RATE_R { + USB_SERIAL_JTAG_DW_DTE_RATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SET_LINE_CODE_W0") + .field( + "usb_serial_jtag_dw_dte_rate", + &format_args!("{}", self.usb_serial_jtag_dw_dte_rate().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "W0 of SET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set_line_code_w0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_LINE_CODE_W0_SPEC; +impl crate::RegisterSpec for SET_LINE_CODE_W0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`set_line_code_w0::R`](R) reader structure"] +impl crate::Readable for SET_LINE_CODE_W0_SPEC {} +#[doc = "`reset()` method sets SET_LINE_CODE_W0 to value 0"] +impl crate::Resettable for SET_LINE_CODE_W0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/set_line_code_w1.rs b/esp32p4/src/usb_device/set_line_code_w1.rs new file mode 100644 index 0000000000..db1b6994c1 --- /dev/null +++ b/esp32p4/src/usb_device/set_line_code_w1.rs @@ -0,0 +1,61 @@ +#[doc = "Register `SET_LINE_CODE_W1` reader"] +pub type R = crate::R; +#[doc = "Field `USB_SERIAL_JTAG_BCHAR_FORMAT` reader - The value of bCharFormat set by host through SET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_BCHAR_FORMAT_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_BPARITY_TYPE` reader - The value of bParityTpye set by host through SET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_BPARITY_TYPE_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_BDATA_BITS` reader - The value of bDataBits set by host through SET_LINE_CODING command."] +pub type USB_SERIAL_JTAG_BDATA_BITS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The value of bCharFormat set by host through SET_LINE_CODING command."] + #[inline(always)] + pub fn usb_serial_jtag_bchar_format(&self) -> USB_SERIAL_JTAG_BCHAR_FORMAT_R { + USB_SERIAL_JTAG_BCHAR_FORMAT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - The value of bParityTpye set by host through SET_LINE_CODING command."] + #[inline(always)] + pub fn usb_serial_jtag_bparity_type(&self) -> USB_SERIAL_JTAG_BPARITY_TYPE_R { + USB_SERIAL_JTAG_BPARITY_TYPE_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - The value of bDataBits set by host through SET_LINE_CODING command."] + #[inline(always)] + pub fn usb_serial_jtag_bdata_bits(&self) -> USB_SERIAL_JTAG_BDATA_BITS_R { + USB_SERIAL_JTAG_BDATA_BITS_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SET_LINE_CODE_W1") + .field( + "usb_serial_jtag_bchar_format", + &format_args!("{}", self.usb_serial_jtag_bchar_format().bits()), + ) + .field( + "usb_serial_jtag_bparity_type", + &format_args!("{}", self.usb_serial_jtag_bparity_type().bits()), + ) + .field( + "usb_serial_jtag_bdata_bits", + &format_args!("{}", self.usb_serial_jtag_bdata_bits().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "W1 of SET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set_line_code_w1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_LINE_CODE_W1_SPEC; +impl crate::RegisterSpec for SET_LINE_CODE_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`set_line_code_w1::R`](R) reader structure"] +impl crate::Readable for SET_LINE_CODE_W1_SPEC {} +#[doc = "`reset()` method sets SET_LINE_CODE_W1 to value 0"] +impl crate::Resettable for SET_LINE_CODE_W1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/src/usb_device/sram_ctrl.rs b/esp32p4/src/usb_device/sram_ctrl.rs new file mode 100644 index 0000000000..be994ca1eb --- /dev/null +++ b/esp32p4/src/usb_device/sram_ctrl.rs @@ -0,0 +1,68 @@ +#[doc = "Register `SRAM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_MEM_AUX_CTRL` reader - Control signals"] +pub type USB_SERIAL_JTAG_MEM_AUX_CTRL_R = crate::FieldReader; +#[doc = "Field `USB_SERIAL_JTAG_MEM_AUX_CTRL` writer - Control signals"] +pub type USB_SERIAL_JTAG_MEM_AUX_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +impl R { + #[doc = "Bits 0:13 - Control signals"] + #[inline(always)] + pub fn usb_serial_jtag_mem_aux_ctrl(&self) -> USB_SERIAL_JTAG_MEM_AUX_CTRL_R { + USB_SERIAL_JTAG_MEM_AUX_CTRL_R::new((self.bits & 0x3fff) as u16) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SRAM_CTRL") + .field( + "usb_serial_jtag_mem_aux_ctrl", + &format_args!("{}", self.usb_serial_jtag_mem_aux_ctrl().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bits 0:13 - Control signals"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_mem_aux_ctrl( + &mut self, + ) -> USB_SERIAL_JTAG_MEM_AUX_CTRL_W { + USB_SERIAL_JTAG_MEM_AUX_CTRL_W::new(self, 0) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "PPA SRAM Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sram_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM_CTRL_SPEC; +impl crate::RegisterSpec for SRAM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram_ctrl::R`](R) reader structure"] +impl crate::Readable for SRAM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram_ctrl::W`](W) writer structure"] +impl crate::Writable for SRAM_CTRL_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SRAM_CTRL to value 0x1320"] +impl crate::Resettable for SRAM_CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x1320; +} diff --git a/esp32p4/src/usb_device/test.rs b/esp32p4/src/usb_device/test.rs new file mode 100644 index 0000000000..88049ce475 --- /dev/null +++ b/esp32p4/src/usb_device/test.rs @@ -0,0 +1,156 @@ +#[doc = "Register `TEST` reader"] +pub type R = crate::R; +#[doc = "Register `TEST` writer"] +pub type W = crate::W; +#[doc = "Field `USB_SERIAL_JTAG_TEST_ENABLE` reader - Enable test of the USB pad"] +pub type USB_SERIAL_JTAG_TEST_ENABLE_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_TEST_ENABLE` writer - Enable test of the USB pad"] +pub type USB_SERIAL_JTAG_TEST_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_TEST_USB_OE` reader - USB pad oen in test"] +pub type USB_SERIAL_JTAG_TEST_USB_OE_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_TEST_USB_OE` writer - USB pad oen in test"] +pub type USB_SERIAL_JTAG_TEST_USB_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_TEST_TX_DP` reader - USB D+ tx value in test"] +pub type USB_SERIAL_JTAG_TEST_TX_DP_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_TEST_TX_DP` writer - USB D+ tx value in test"] +pub type USB_SERIAL_JTAG_TEST_TX_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_TEST_TX_DM` reader - USB D- tx value in test"] +pub type USB_SERIAL_JTAG_TEST_TX_DM_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_TEST_TX_DM` writer - USB D- tx value in test"] +pub type USB_SERIAL_JTAG_TEST_TX_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_SERIAL_JTAG_TEST_RX_RCV` reader - USB RCV value in test"] +pub type USB_SERIAL_JTAG_TEST_RX_RCV_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_TEST_RX_DP` reader - USB D+ rx value in test"] +pub type USB_SERIAL_JTAG_TEST_RX_DP_R = crate::BitReader; +#[doc = "Field `USB_SERIAL_JTAG_TEST_RX_DM` reader - USB D- rx value in test"] +pub type USB_SERIAL_JTAG_TEST_RX_DM_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Enable test of the USB pad"] + #[inline(always)] + pub fn usb_serial_jtag_test_enable(&self) -> USB_SERIAL_JTAG_TEST_ENABLE_R { + USB_SERIAL_JTAG_TEST_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - USB pad oen in test"] + #[inline(always)] + pub fn usb_serial_jtag_test_usb_oe(&self) -> USB_SERIAL_JTAG_TEST_USB_OE_R { + USB_SERIAL_JTAG_TEST_USB_OE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - USB D+ tx value in test"] + #[inline(always)] + pub fn usb_serial_jtag_test_tx_dp(&self) -> USB_SERIAL_JTAG_TEST_TX_DP_R { + USB_SERIAL_JTAG_TEST_TX_DP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - USB D- tx value in test"] + #[inline(always)] + pub fn usb_serial_jtag_test_tx_dm(&self) -> USB_SERIAL_JTAG_TEST_TX_DM_R { + USB_SERIAL_JTAG_TEST_TX_DM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - USB RCV value in test"] + #[inline(always)] + pub fn usb_serial_jtag_test_rx_rcv(&self) -> USB_SERIAL_JTAG_TEST_RX_RCV_R { + USB_SERIAL_JTAG_TEST_RX_RCV_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - USB D+ rx value in test"] + #[inline(always)] + pub fn usb_serial_jtag_test_rx_dp(&self) -> USB_SERIAL_JTAG_TEST_RX_DP_R { + USB_SERIAL_JTAG_TEST_RX_DP_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - USB D- rx value in test"] + #[inline(always)] + pub fn usb_serial_jtag_test_rx_dm(&self) -> USB_SERIAL_JTAG_TEST_RX_DM_R { + USB_SERIAL_JTAG_TEST_RX_DM_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TEST") + .field( + "usb_serial_jtag_test_enable", + &format_args!("{}", self.usb_serial_jtag_test_enable().bit()), + ) + .field( + "usb_serial_jtag_test_usb_oe", + &format_args!("{}", self.usb_serial_jtag_test_usb_oe().bit()), + ) + .field( + "usb_serial_jtag_test_tx_dp", + &format_args!("{}", self.usb_serial_jtag_test_tx_dp().bit()), + ) + .field( + "usb_serial_jtag_test_tx_dm", + &format_args!("{}", self.usb_serial_jtag_test_tx_dm().bit()), + ) + .field( + "usb_serial_jtag_test_rx_rcv", + &format_args!("{}", self.usb_serial_jtag_test_rx_rcv().bit()), + ) + .field( + "usb_serial_jtag_test_rx_dp", + &format_args!("{}", self.usb_serial_jtag_test_rx_dp().bit()), + ) + .field( + "usb_serial_jtag_test_rx_dm", + &format_args!("{}", self.usb_serial_jtag_test_rx_dm().bit()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable test of the USB pad"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_test_enable(&mut self) -> USB_SERIAL_JTAG_TEST_ENABLE_W { + USB_SERIAL_JTAG_TEST_ENABLE_W::new(self, 0) + } + #[doc = "Bit 1 - USB pad oen in test"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_test_usb_oe(&mut self) -> USB_SERIAL_JTAG_TEST_USB_OE_W { + USB_SERIAL_JTAG_TEST_USB_OE_W::new(self, 1) + } + #[doc = "Bit 2 - USB D+ tx value in test"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_test_tx_dp(&mut self) -> USB_SERIAL_JTAG_TEST_TX_DP_W { + USB_SERIAL_JTAG_TEST_TX_DP_W::new(self, 2) + } + #[doc = "Bit 3 - USB D- tx value in test"] + #[inline(always)] + #[must_use] + pub fn usb_serial_jtag_test_tx_dm(&mut self) -> USB_SERIAL_JTAG_TEST_TX_DM_W { + USB_SERIAL_JTAG_TEST_TX_DM_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "Registers used for debugging the PHY.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`test::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`test::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TEST_SPEC; +impl crate::RegisterSpec for TEST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`test::R`](R) reader structure"] +impl crate::Readable for TEST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`test::W`](W) writer structure"] +impl crate::Writable for TEST_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TEST to value 0x30"] +impl crate::Resettable for TEST_SPEC { + const RESET_VALUE: Self::Ux = 0x30; +} diff --git a/esp32p4/src/usb_wrap.rs b/esp32p4/src/usb_wrap.rs new file mode 100644 index 0000000000..948b45b788 --- /dev/null +++ b/esp32p4/src/usb_wrap.rs @@ -0,0 +1,38 @@ +#[doc = r"Register block"] +#[repr(C)] +#[cfg_attr(feature = "impl-register-debug", derive(Debug))] +pub struct RegisterBlock { + otg_conf: OTG_CONF, + test_conf: TEST_CONF, + _reserved2: [u8; 0x03f4], + date: DATE, +} +impl RegisterBlock { + #[doc = "0x00 - USB wrapper configuration registers."] + #[inline(always)] + pub const fn otg_conf(&self) -> &OTG_CONF { + &self.otg_conf + } + #[doc = "0x04 - USB wrapper test configuration registers."] + #[inline(always)] + pub const fn test_conf(&self) -> &TEST_CONF { + &self.test_conf + } + #[doc = "0x3fc - Date register."] + #[inline(always)] + pub const fn date(&self) -> &DATE { + &self.date + } +} +#[doc = "OTG_CONF (rw) register accessor: USB wrapper configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`otg_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`otg_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otg_conf`] module"] +pub type OTG_CONF = crate::Reg; +#[doc = "USB wrapper configuration registers."] +pub mod otg_conf; +#[doc = "TEST_CONF (rw) register accessor: USB wrapper test configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`test_conf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`test_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@test_conf`] module"] +pub type TEST_CONF = crate::Reg; +#[doc = "USB wrapper test configuration registers."] +pub mod test_conf; +#[doc = "DATE (r) register accessor: Date register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"] +pub type DATE = crate::Reg; +#[doc = "Date register."] +pub mod date; diff --git a/esp32p4/src/usb_wrap/date.rs b/esp32p4/src/usb_wrap/date.rs new file mode 100644 index 0000000000..4201d37b30 --- /dev/null +++ b/esp32p4/src/usb_wrap/date.rs @@ -0,0 +1,39 @@ +#[doc = "Register `DATE` reader"] +pub type R = crate::R; +#[doc = "Field `USB_WRAP_DATE` reader - Date register."] +pub type USB_WRAP_DATE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Date register."] + #[inline(always)] + pub fn usb_wrap_date(&self) -> USB_WRAP_DATE_R { + USB_WRAP_DATE_R::new(self.bits) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DATE") + .field( + "usb_wrap_date", + &format_args!("{}", self.usb_wrap_date().bits()), + ) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc = "Date register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DATE_SPEC; +impl crate::RegisterSpec for DATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`date::R`](R) reader structure"] +impl crate::Readable for DATE_SPEC {} +#[doc = "`reset()` method sets DATE to value 0x2303_0504"] +impl crate::Resettable for DATE_SPEC { + const RESET_VALUE: Self::Ux = 0x2303_0504; +} diff --git a/esp32p4/src/usb_wrap/otg_conf.rs b/esp32p4/src/usb_wrap/otg_conf.rs new file mode 100644 index 0000000000..e9d8c50dd2 --- /dev/null +++ b/esp32p4/src/usb_wrap/otg_conf.rs @@ -0,0 +1,438 @@ +#[doc = "Register `OTG_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `OTG_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `SRP_SESSEND_OVERRIDE` reader - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input, 1'b1: the signal is controlled by the software."] +pub type SRP_SESSEND_OVERRIDE_R = crate::BitReader; +#[doc = "Field `SRP_SESSEND_OVERRIDE` writer - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input, 1'b1: the signal is controlled by the software."] +pub type SRP_SESSEND_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRP_SESSEND_VALUE` reader - Software over-ride value of srp session end signal."] +pub type SRP_SESSEND_VALUE_R = crate::BitReader; +#[doc = "Field `SRP_SESSEND_VALUE` writer - Software over-ride value of srp session end signal."] +pub type SRP_SESSEND_VALUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_SEL` reader - Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY."] +pub type PHY_SEL_R = crate::BitReader; +#[doc = "Field `PHY_SEL` writer - Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY."] +pub type PHY_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DFIFO_FORCE_PD` reader - Force the dfifo to go into low power mode. The data in dfifo will not lost."] +pub type DFIFO_FORCE_PD_R = crate::BitReader; +#[doc = "Field `DFIFO_FORCE_PD` writer - Force the dfifo to go into low power mode. The data in dfifo will not lost."] +pub type DFIFO_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBNCE_FLTR_BYPASS` reader - Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals"] +pub type DBNCE_FLTR_BYPASS_R = crate::BitReader; +#[doc = "Field `DBNCE_FLTR_BYPASS` writer - Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals"] +pub type DBNCE_FLTR_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXCHG_PINS_OVERRIDE` reader - Enable software controlle USB D+ D- exchange"] +pub type EXCHG_PINS_OVERRIDE_R = crate::BitReader; +#[doc = "Field `EXCHG_PINS_OVERRIDE` writer - Enable software controlle USB D+ D- exchange"] +pub type EXCHG_PINS_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXCHG_PINS` reader - USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-."] +pub type EXCHG_PINS_R = crate::BitReader; +#[doc = "Field `EXCHG_PINS` writer - USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-."] +pub type EXCHG_PINS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VREFH` reader - Control single-end input high threshold,1.76V to 2V, step 80mV."] +pub type VREFH_R = crate::FieldReader; +#[doc = "Field `VREFH` writer - Control single-end input high threshold,1.76V to 2V, step 80mV."] +pub type VREFH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `VREFL` reader - Control single-end input low threshold,0.8V to 1.04V, step 80mV."] +pub type VREFL_R = crate::FieldReader; +#[doc = "Field `VREFL` writer - Control single-end input low threshold,0.8V to 1.04V, step 80mV."] +pub type VREFL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `VREF_OVERRIDE` reader - Enable software controlle input threshold."] +pub type VREF_OVERRIDE_R = crate::BitReader; +#[doc = "Field `VREF_OVERRIDE` writer - Enable software controlle input threshold."] +pub type VREF_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PAD_PULL_OVERRIDE` reader - Enable software controlle USB D+ D- pullup pulldown."] +pub type PAD_PULL_OVERRIDE_R = crate::BitReader; +#[doc = "Field `PAD_PULL_OVERRIDE` writer - Enable software controlle USB D+ D- pullup pulldown."] +pub type PAD_PULL_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DP_PULLUP` reader - Controlle USB D+ pullup."] +pub type DP_PULLUP_R = crate::BitReader; +#[doc = "Field `DP_PULLUP` writer - Controlle USB D+ pullup."] +pub type DP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DP_PULLDOWN` reader - Controlle USB D+ pulldown."] +pub type DP_PULLDOWN_R = crate::BitReader; +#[doc = "Field `DP_PULLDOWN` writer - Controlle USB D+ pulldown."] +pub type DP_PULLDOWN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DM_PULLUP` reader - Controlle USB D+ pullup."] +pub type DM_PULLUP_R = crate::BitReader; +#[doc = "Field `DM_PULLUP` writer - Controlle USB D+ pullup."] +pub type DM_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DM_PULLDOWN` reader - Controlle USB D+ pulldown."] +pub type DM_PULLDOWN_R = crate::BitReader; +#[doc = "Field `DM_PULLDOWN` writer - Controlle USB D+ pulldown."] +pub type DM_PULLDOWN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PULLUP_VALUE` reader - Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K."] +pub type PULLUP_VALUE_R = crate::BitReader; +#[doc = "Field `PULLUP_VALUE` writer - Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K."] +pub type PULLUP_VALUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_PAD_ENABLE` reader - Enable USB pad function."] +pub type USB_PAD_ENABLE_R = crate::BitReader; +#[doc = "Field `USB_PAD_ENABLE` writer - Enable USB pad function."] +pub type USB_PAD_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AHB_CLK_FORCE_ON` reader - Force ahb clock always on."] +pub type AHB_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `AHB_CLK_FORCE_ON` writer - Force ahb clock always on."] +pub type AHB_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_CLK_FORCE_ON` reader - Force phy clock always on."] +pub type PHY_CLK_FORCE_ON_R = crate::BitReader; +#[doc = "Field `PHY_CLK_FORCE_ON` writer - Force phy clock always on."] +pub type PHY_CLK_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_TX_EDGE_SEL` reader - Select phy tx signal output clock edge. 1'b0: negedge, 1'b1: posedge."] +pub type PHY_TX_EDGE_SEL_R = crate::BitReader; +#[doc = "Field `PHY_TX_EDGE_SEL` writer - Select phy tx signal output clock edge. 1'b0: negedge, 1'b1: posedge."] +pub type PHY_TX_EDGE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DFIFO_FORCE_PU` reader - Disable the dfifo to go into low power mode. The data in dfifo will not lost."] +pub type DFIFO_FORCE_PU_R = crate::BitReader; +#[doc = "Field `DFIFO_FORCE_PU` writer - Disable the dfifo to go into low power mode. The data in dfifo will not lost."] +pub type DFIFO_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_EN` reader - Disable auto clock gating of CSR registers."] +pub type CLK_EN_R = crate::BitReader; +#[doc = "Field `CLK_EN` writer - Disable auto clock gating of CSR registers."] +pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input, 1'b1: the signal is controlled by the software."] + #[inline(always)] + pub fn srp_sessend_override(&self) -> SRP_SESSEND_OVERRIDE_R { + SRP_SESSEND_OVERRIDE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Software over-ride value of srp session end signal."] + #[inline(always)] + pub fn srp_sessend_value(&self) -> SRP_SESSEND_VALUE_R { + SRP_SESSEND_VALUE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY."] + #[inline(always)] + pub fn phy_sel(&self) -> PHY_SEL_R { + PHY_SEL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Force the dfifo to go into low power mode. The data in dfifo will not lost."] + #[inline(always)] + pub fn dfifo_force_pd(&self) -> DFIFO_FORCE_PD_R { + DFIFO_FORCE_PD_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals"] + #[inline(always)] + pub fn dbnce_fltr_bypass(&self) -> DBNCE_FLTR_BYPASS_R { + DBNCE_FLTR_BYPASS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable software controlle USB D+ D- exchange"] + #[inline(always)] + pub fn exchg_pins_override(&self) -> EXCHG_PINS_OVERRIDE_R { + EXCHG_PINS_OVERRIDE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-."] + #[inline(always)] + pub fn exchg_pins(&self) -> EXCHG_PINS_R { + EXCHG_PINS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:8 - Control single-end input high threshold,1.76V to 2V, step 80mV."] + #[inline(always)] + pub fn vrefh(&self) -> VREFH_R { + VREFH_R::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 9:10 - Control single-end input low threshold,0.8V to 1.04V, step 80mV."] + #[inline(always)] + pub fn vrefl(&self) -> VREFL_R { + VREFL_R::new(((self.bits >> 9) & 3) as u8) + } + #[doc = "Bit 11 - Enable software controlle input threshold."] + #[inline(always)] + pub fn vref_override(&self) -> VREF_OVERRIDE_R { + VREF_OVERRIDE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable software controlle USB D+ D- pullup pulldown."] + #[inline(always)] + pub fn pad_pull_override(&self) -> PAD_PULL_OVERRIDE_R { + PAD_PULL_OVERRIDE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Controlle USB D+ pullup."] + #[inline(always)] + pub fn dp_pullup(&self) -> DP_PULLUP_R { + DP_PULLUP_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Controlle USB D+ pulldown."] + #[inline(always)] + pub fn dp_pulldown(&self) -> DP_PULLDOWN_R { + DP_PULLDOWN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Controlle USB D+ pullup."] + #[inline(always)] + pub fn dm_pullup(&self) -> DM_PULLUP_R { + DM_PULLUP_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Controlle USB D+ pulldown."] + #[inline(always)] + pub fn dm_pulldown(&self) -> DM_PULLDOWN_R { + DM_PULLDOWN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K."] + #[inline(always)] + pub fn pullup_value(&self) -> PULLUP_VALUE_R { + PULLUP_VALUE_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enable USB pad function."] + #[inline(always)] + pub fn usb_pad_enable(&self) -> USB_PAD_ENABLE_R { + USB_PAD_ENABLE_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Force ahb clock always on."] + #[inline(always)] + pub fn ahb_clk_force_on(&self) -> AHB_CLK_FORCE_ON_R { + AHB_CLK_FORCE_ON_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Force phy clock always on."] + #[inline(always)] + pub fn phy_clk_force_on(&self) -> PHY_CLK_FORCE_ON_R { + PHY_CLK_FORCE_ON_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Select phy tx signal output clock edge. 1'b0: negedge, 1'b1: posedge."] + #[inline(always)] + pub fn phy_tx_edge_sel(&self) -> PHY_TX_EDGE_SEL_R { + PHY_TX_EDGE_SEL_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Disable the dfifo to go into low power mode. The data in dfifo will not lost."] + #[inline(always)] + pub fn dfifo_force_pu(&self) -> DFIFO_FORCE_PU_R { + DFIFO_FORCE_PU_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 31 - Disable auto clock gating of CSR registers."] + #[inline(always)] + pub fn clk_en(&self) -> CLK_EN_R { + CLK_EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OTG_CONF") + .field( + "srp_sessend_override", + &format_args!("{}", self.srp_sessend_override().bit()), + ) + .field( + "srp_sessend_value", + &format_args!("{}", self.srp_sessend_value().bit()), + ) + .field("phy_sel", &format_args!("{}", self.phy_sel().bit())) + .field( + "dfifo_force_pd", + &format_args!("{}", self.dfifo_force_pd().bit()), + ) + .field( + "dbnce_fltr_bypass", + &format_args!("{}", self.dbnce_fltr_bypass().bit()), + ) + .field( + "exchg_pins_override", + &format_args!("{}", self.exchg_pins_override().bit()), + ) + .field("exchg_pins", &format_args!("{}", self.exchg_pins().bit())) + .field("vrefh", &format_args!("{}", self.vrefh().bits())) + .field("vrefl", &format_args!("{}", self.vrefl().bits())) + .field( + "vref_override", + &format_args!("{}", self.vref_override().bit()), + ) + .field( + "pad_pull_override", + &format_args!("{}", self.pad_pull_override().bit()), + ) + .field("dp_pullup", &format_args!("{}", self.dp_pullup().bit())) + .field("dp_pulldown", &format_args!("{}", self.dp_pulldown().bit())) + .field("dm_pullup", &format_args!("{}", self.dm_pullup().bit())) + .field("dm_pulldown", &format_args!("{}", self.dm_pulldown().bit())) + .field( + "pullup_value", + &format_args!("{}", self.pullup_value().bit()), + ) + .field( + "usb_pad_enable", + &format_args!("{}", self.usb_pad_enable().bit()), + ) + .field( + "ahb_clk_force_on", + &format_args!("{}", self.ahb_clk_force_on().bit()), + ) + .field( + "phy_clk_force_on", + &format_args!("{}", self.phy_clk_force_on().bit()), + ) + .field( + "phy_tx_edge_sel", + &format_args!("{}", self.phy_tx_edge_sel().bit()), + ) + .field( + "dfifo_force_pu", + &format_args!("{}", self.dfifo_force_pu().bit()), + ) + .field("clk_en", &format_args!("{}", self.clk_en().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input, 1'b1: the signal is controlled by the software."] + #[inline(always)] + #[must_use] + pub fn srp_sessend_override(&mut self) -> SRP_SESSEND_OVERRIDE_W { + SRP_SESSEND_OVERRIDE_W::new(self, 0) + } + #[doc = "Bit 1 - Software over-ride value of srp session end signal."] + #[inline(always)] + #[must_use] + pub fn srp_sessend_value(&mut self) -> SRP_SESSEND_VALUE_W { + SRP_SESSEND_VALUE_W::new(self, 1) + } + #[doc = "Bit 2 - Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY."] + #[inline(always)] + #[must_use] + pub fn phy_sel(&mut self) -> PHY_SEL_W { + PHY_SEL_W::new(self, 2) + } + #[doc = "Bit 3 - Force the dfifo to go into low power mode. The data in dfifo will not lost."] + #[inline(always)] + #[must_use] + pub fn dfifo_force_pd(&mut self) -> DFIFO_FORCE_PD_W { + DFIFO_FORCE_PD_W::new(self, 3) + } + #[doc = "Bit 4 - Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals"] + #[inline(always)] + #[must_use] + pub fn dbnce_fltr_bypass(&mut self) -> DBNCE_FLTR_BYPASS_W { + DBNCE_FLTR_BYPASS_W::new(self, 4) + } + #[doc = "Bit 5 - Enable software controlle USB D+ D- exchange"] + #[inline(always)] + #[must_use] + pub fn exchg_pins_override(&mut self) -> EXCHG_PINS_OVERRIDE_W { + EXCHG_PINS_OVERRIDE_W::new(self, 5) + } + #[doc = "Bit 6 - USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-."] + #[inline(always)] + #[must_use] + pub fn exchg_pins(&mut self) -> EXCHG_PINS_W { + EXCHG_PINS_W::new(self, 6) + } + #[doc = "Bits 7:8 - Control single-end input high threshold,1.76V to 2V, step 80mV."] + #[inline(always)] + #[must_use] + pub fn vrefh(&mut self) -> VREFH_W { + VREFH_W::new(self, 7) + } + #[doc = "Bits 9:10 - Control single-end input low threshold,0.8V to 1.04V, step 80mV."] + #[inline(always)] + #[must_use] + pub fn vrefl(&mut self) -> VREFL_W { + VREFL_W::new(self, 9) + } + #[doc = "Bit 11 - Enable software controlle input threshold."] + #[inline(always)] + #[must_use] + pub fn vref_override(&mut self) -> VREF_OVERRIDE_W { + VREF_OVERRIDE_W::new(self, 11) + } + #[doc = "Bit 12 - Enable software controlle USB D+ D- pullup pulldown."] + #[inline(always)] + #[must_use] + pub fn pad_pull_override(&mut self) -> PAD_PULL_OVERRIDE_W { + PAD_PULL_OVERRIDE_W::new(self, 12) + } + #[doc = "Bit 13 - Controlle USB D+ pullup."] + #[inline(always)] + #[must_use] + pub fn dp_pullup(&mut self) -> DP_PULLUP_W { + DP_PULLUP_W::new(self, 13) + } + #[doc = "Bit 14 - Controlle USB D+ pulldown."] + #[inline(always)] + #[must_use] + pub fn dp_pulldown(&mut self) -> DP_PULLDOWN_W { + DP_PULLDOWN_W::new(self, 14) + } + #[doc = "Bit 15 - Controlle USB D+ pullup."] + #[inline(always)] + #[must_use] + pub fn dm_pullup(&mut self) -> DM_PULLUP_W { + DM_PULLUP_W::new(self, 15) + } + #[doc = "Bit 16 - Controlle USB D+ pulldown."] + #[inline(always)] + #[must_use] + pub fn dm_pulldown(&mut self) -> DM_PULLDOWN_W { + DM_PULLDOWN_W::new(self, 16) + } + #[doc = "Bit 17 - Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K."] + #[inline(always)] + #[must_use] + pub fn pullup_value(&mut self) -> PULLUP_VALUE_W { + PULLUP_VALUE_W::new(self, 17) + } + #[doc = "Bit 18 - Enable USB pad function."] + #[inline(always)] + #[must_use] + pub fn usb_pad_enable(&mut self) -> USB_PAD_ENABLE_W { + USB_PAD_ENABLE_W::new(self, 18) + } + #[doc = "Bit 19 - Force ahb clock always on."] + #[inline(always)] + #[must_use] + pub fn ahb_clk_force_on(&mut self) -> AHB_CLK_FORCE_ON_W { + AHB_CLK_FORCE_ON_W::new(self, 19) + } + #[doc = "Bit 20 - Force phy clock always on."] + #[inline(always)] + #[must_use] + pub fn phy_clk_force_on(&mut self) -> PHY_CLK_FORCE_ON_W { + PHY_CLK_FORCE_ON_W::new(self, 20) + } + #[doc = "Bit 21 - Select phy tx signal output clock edge. 1'b0: negedge, 1'b1: posedge."] + #[inline(always)] + #[must_use] + pub fn phy_tx_edge_sel(&mut self) -> PHY_TX_EDGE_SEL_W { + PHY_TX_EDGE_SEL_W::new(self, 21) + } + #[doc = "Bit 22 - Disable the dfifo to go into low power mode. The data in dfifo will not lost."] + #[inline(always)] + #[must_use] + pub fn dfifo_force_pu(&mut self) -> DFIFO_FORCE_PU_W { + DFIFO_FORCE_PU_W::new(self, 22) + } + #[doc = "Bit 31 - Disable auto clock gating of CSR registers."] + #[inline(always)] + #[must_use] + pub fn clk_en(&mut self) -> CLK_EN_W { + CLK_EN_W::new(self, 31) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "USB wrapper configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`otg_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`otg_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OTG_CONF_SPEC; +impl crate::RegisterSpec for OTG_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`otg_conf::R`](R) reader structure"] +impl crate::Readable for OTG_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`otg_conf::W`](W) writer structure"] +impl crate::Writable for OTG_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OTG_CONF to value 0x0010_0000"] +impl crate::Resettable for OTG_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0x0010_0000; +} diff --git a/esp32p4/src/usb_wrap/test_conf.rs b/esp32p4/src/usb_wrap/test_conf.rs new file mode 100644 index 0000000000..dd0bed716b --- /dev/null +++ b/esp32p4/src/usb_wrap/test_conf.rs @@ -0,0 +1,135 @@ +#[doc = "Register `TEST_CONF` reader"] +pub type R = crate::R; +#[doc = "Register `TEST_CONF` writer"] +pub type W = crate::W; +#[doc = "Field `TEST_ENABLE` reader - Enable test of the USB pad."] +pub type TEST_ENABLE_R = crate::BitReader; +#[doc = "Field `TEST_ENABLE` writer - Enable test of the USB pad."] +pub type TEST_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TEST_USB_OE` reader - USB pad oen in test."] +pub type TEST_USB_OE_R = crate::BitReader; +#[doc = "Field `TEST_USB_OE` writer - USB pad oen in test."] +pub type TEST_USB_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TEST_TX_DP` reader - USB D+ tx value in test."] +pub type TEST_TX_DP_R = crate::BitReader; +#[doc = "Field `TEST_TX_DP` writer - USB D+ tx value in test."] +pub type TEST_TX_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TEST_TX_DM` reader - USB D- tx value in test."] +pub type TEST_TX_DM_R = crate::BitReader; +#[doc = "Field `TEST_TX_DM` writer - USB D- tx value in test."] +pub type TEST_TX_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TEST_RX_RCV` reader - USB differential rx value in test."] +pub type TEST_RX_RCV_R = crate::BitReader; +#[doc = "Field `TEST_RX_DP` reader - USB D+ rx value in test."] +pub type TEST_RX_DP_R = crate::BitReader; +#[doc = "Field `TEST_RX_DM` reader - USB D- rx value in test."] +pub type TEST_RX_DM_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Enable test of the USB pad."] + #[inline(always)] + pub fn test_enable(&self) -> TEST_ENABLE_R { + TEST_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - USB pad oen in test."] + #[inline(always)] + pub fn test_usb_oe(&self) -> TEST_USB_OE_R { + TEST_USB_OE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - USB D+ tx value in test."] + #[inline(always)] + pub fn test_tx_dp(&self) -> TEST_TX_DP_R { + TEST_TX_DP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - USB D- tx value in test."] + #[inline(always)] + pub fn test_tx_dm(&self) -> TEST_TX_DM_R { + TEST_TX_DM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - USB differential rx value in test."] + #[inline(always)] + pub fn test_rx_rcv(&self) -> TEST_RX_RCV_R { + TEST_RX_RCV_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - USB D+ rx value in test."] + #[inline(always)] + pub fn test_rx_dp(&self) -> TEST_RX_DP_R { + TEST_RX_DP_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - USB D- rx value in test."] + #[inline(always)] + pub fn test_rx_dm(&self) -> TEST_RX_DM_R { + TEST_RX_DM_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TEST_CONF") + .field("test_enable", &format_args!("{}", self.test_enable().bit())) + .field("test_usb_oe", &format_args!("{}", self.test_usb_oe().bit())) + .field("test_tx_dp", &format_args!("{}", self.test_tx_dp().bit())) + .field("test_tx_dm", &format_args!("{}", self.test_tx_dm().bit())) + .field("test_rx_rcv", &format_args!("{}", self.test_rx_rcv().bit())) + .field("test_rx_dp", &format_args!("{}", self.test_rx_dp().bit())) + .field("test_rx_dm", &format_args!("{}", self.test_rx_dm().bit())) + .finish() + } +} +#[cfg(feature = "impl-register-debug")] +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +impl W { + #[doc = "Bit 0 - Enable test of the USB pad."] + #[inline(always)] + #[must_use] + pub fn test_enable(&mut self) -> TEST_ENABLE_W { + TEST_ENABLE_W::new(self, 0) + } + #[doc = "Bit 1 - USB pad oen in test."] + #[inline(always)] + #[must_use] + pub fn test_usb_oe(&mut self) -> TEST_USB_OE_W { + TEST_USB_OE_W::new(self, 1) + } + #[doc = "Bit 2 - USB D+ tx value in test."] + #[inline(always)] + #[must_use] + pub fn test_tx_dp(&mut self) -> TEST_TX_DP_W { + TEST_TX_DP_W::new(self, 2) + } + #[doc = "Bit 3 - USB D- tx value in test."] + #[inline(always)] + #[must_use] + pub fn test_tx_dm(&mut self) -> TEST_TX_DM_W { + TEST_TX_DM_W::new(self, 3) + } + #[doc = r" Writes raw bits to the register."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = "USB wrapper test configuration registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`test_conf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`test_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TEST_CONF_SPEC; +impl crate::RegisterSpec for TEST_CONF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`test_conf::R`](R) reader structure"] +impl crate::Readable for TEST_CONF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`test_conf::W`](W) writer structure"] +impl crate::Writable for TEST_CONF_SPEC { + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TEST_CONF to value 0"] +impl crate::Resettable for TEST_CONF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/esp32p4/svd/esp32p4.base.svd b/esp32p4/svd/esp32p4.base.svd new file mode 100644 index 0000000000..ef258da6ef --- /dev/null +++ b/esp32p4/svd/esp32p4.base.svd @@ -0,0 +1,143794 @@ + + + ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. + ESPRESSIF + ESP32-P4 + ESP32 P-Series + 1 + 32-bit RISC-V MCU + Copyright 2023 Espressif Systems (Shanghai) PTE LTD + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + + RV32IMAFC + r0p0 + little + false + true + 0 + false + + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + ADC + ADC (Analog to Digital Converter) + ADC + 0x500DE000 + + 0x0 + 0x7C + registers + + + + CTRL + Register + 0x0 + 0x20 + 0x403FC120 + + + START_FORCE + need_des + 0 + 1 + read-write + + + START + need_des + 1 + 1 + read-write + + + WORK_MODE + 0: single mode, 1: double mode, 2: alternate mode + 2 + 2 + read-write + + + SAR_SEL + 0: SAR1, 1: SAR2, only work for single SAR mode + 4 + 1 + read-write + + + SAR_CLK_GATED + need_des + 5 + 1 + read-write + + + SAR_CLK_DIV + SAR clock divider + 6 + 8 + read-write + + + SAR1_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 14 + 4 + read-write + + + SAR2_PATT_LEN + 0 ~ 15 means length 1 ~ 16 + 18 + 4 + read-write + + + SAR1_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC1 CTRL + 22 + 1 + read-write + + + SAR2_PATT_P_CLEAR + clear the pointer of pattern table for DIG ADC2 CTRL + 23 + 1 + read-write + + + DATA_SAR_SEL + 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits. + 24 + 1 + read-write + + + DATA_TO_I2S + 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix + 25 + 1 + read-write + + + XPD_SAR1_FORCE + force option to xpd sar1 blocks + 26 + 2 + read-write + + + XPD_SAR2_FORCE + force option to xpd sar2 blocks + 28 + 2 + read-write + + + WAIT_ARB_CYCLE + wait arbit signal stable after sar_done + 30 + 2 + read-write + + + + + CTRL2 + Register + 0x4 + 0x20 + 0x0000A1FE + + + MEAS_NUM_LIMIT + need_des + 0 + 1 + read-write + + + MAX_MEAS_NUM + max conversion number + 1 + 8 + read-write + + + SAR1_INV + 1: data to DIG ADC1 CTRL is inverted, otherwise not + 9 + 1 + read-write + + + SAR2_INV + 1: data to DIG ADC2 CTRL is inverted, otherwise not + 10 + 1 + read-write + + + TIMER_SEL + 1: select saradc timer 0: i2s_ws trigger + 11 + 1 + read-write + + + TIMER_TARGET + to set saradc timer target + 12 + 12 + read-write + + + TIMER_EN + to enable saradc timer trigger + 24 + 1 + read-write + + + + + FILTER_CTRL1 + Register + 0x8 + 0x20 + + + FILTER_FACTOR1 + need_des + 26 + 3 + read-write + + + FILTER_FACTOR0 + need_des + 29 + 3 + read-write + + + + + FSM_WAIT + Register + 0xC + 0x20 + 0x00FF0808 + + + XPD_WAIT + need_des + 0 + 8 + read-write + + + RSTB_WAIT + need_des + 8 + 8 + read-write + + + STANDBY_WAIT + need_des + 16 + 8 + read-write + + + + + SAR1_STATUS + Register + 0x10 + 0x20 + + + SAR1_STATUS + 0 + 32 + read-only + + + + + SAR2_STATUS + Register + 0x14 + 0x20 + + + SAR2_STATUS + 0 + 32 + read-only + + + + + SAR1_PATT_TAB1 + Register + 0x18 + 0x20 + + + SAR1_PATT_TAB1 + item 0 ~ 3 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB2 + Register + 0x1C + 0x20 + + + SAR1_PATT_TAB2 + Item 4 ~ 7 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB3 + Register + 0x20 + 0x20 + + + SAR1_PATT_TAB3 + Item 8 ~ 11 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR1_PATT_TAB4 + Register + 0x24 + 0x20 + + + SAR1_PATT_TAB4 + Item 12 ~ 15 for pattern table 1 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB1 + Register + 0x28 + 0x20 + + + SAR2_PATT_TAB1 + item 0 ~ 3 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB2 + Register + 0x2C + 0x20 + + + SAR2_PATT_TAB2 + Item 4 ~ 7 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB3 + Register + 0x30 + 0x20 + + + SAR2_PATT_TAB3 + Item 8 ~ 11 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + SAR2_PATT_TAB4 + Register + 0x34 + 0x20 + + + SAR2_PATT_TAB4 + Item 12 ~ 15 for pattern table 2 (each item one byte) + 0 + 24 + read-write + + + + + ARB_CTRL + Register + 0x38 + 0x20 + 0x00000900 + + + ARB_APB_FORCE + adc2 arbiter force to enableapb controller + 2 + 1 + read-write + + + ARB_RTC_FORCE + adc2 arbiter force to enable rtc controller + 3 + 1 + read-write + + + ARB_WIFI_FORCE + adc2 arbiter force to enable wifi controller + 4 + 1 + read-write + + + ARB_GRANT_FORCE + adc2 arbiter force grant + 5 + 1 + read-write + + + ARB_APB_PRIORITY + Set adc2 arbiterapb priority + 6 + 2 + read-write + + + ARB_RTC_PRIORITY + Set adc2 arbiter rtc priority + 8 + 2 + read-write + + + ARB_WIFI_PRIORITY + Set adc2 arbiter wifi priority + 10 + 2 + read-write + + + ARB_FIX_PRIORITY + adc2 arbiter uses fixed priority + 12 + 1 + read-write + + + + + FILTER_CTRL0 + Register + 0x3C + 0x20 + 0x006B4000 + + + FILTER_CHANNEL1 + need_des + 14 + 5 + read-write + + + FILTER_CHANNEL0 + apb_adc1_filter_factor + 19 + 5 + read-write + + + FILTER_RESET + enable apb_adc1_filter + 31 + 1 + read-write + + + + + SAR1_DATA_STATUS + Register + 0x40 + 0x20 + + + APB_SARADC1_DATA + need_des + 0 + 17 + read-only + + + + + THRES0_CTRL + Register + 0x44 + 0x20 + 0x0003FFED + + + THRES0_CHANNEL + need_des + 0 + 5 + read-write + + + THRES0_HIGH + saradc1's thres0 monitor thres + 5 + 13 + read-write + + + THRES0_LOW + saradc1's thres0 monitor thres + 18 + 13 + read-write + + + + + THRES1_CTRL + Register + 0x48 + 0x20 + 0x0003FFED + + + THRES1_CHANNEL + need_des + 0 + 5 + read-write + + + THRES1_HIGH + saradc1's thres0 monitor thres + 5 + 13 + read-write + + + THRES1_LOW + saradc1's thres0 monitor thres + 18 + 13 + read-write + + + + + THRES_CTRL + Register + 0x4C + 0x20 + + + THRES_ALL_EN + need_des + 27 + 1 + read-write + + + THRES3_EN + need_des + 28 + 1 + read-write + + + THRES2_EN + need_des + 29 + 1 + read-write + + + THRES1_EN + need_des + 30 + 1 + read-write + + + THRES0_EN + need_des + 31 + 1 + read-write + + + + + INT_ENA + Register + 0x50 + 0x20 + + + THRES1_LOW_INT_ENA + need_des + 26 + 1 + read-write + + + THRES0_LOW_INT_ENA + need_des + 27 + 1 + read-write + + + THRES1_HIGH_INT_ENA + need_des + 28 + 1 + read-write + + + THRES0_HIGH_INT_ENA + need_des + 29 + 1 + read-write + + + SAR2_DONE_INT_ENA + need_des + 30 + 1 + read-write + + + SAR1_DONE_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_RAW + Register + 0x54 + 0x20 + + + THRES1_LOW_INT_RAW + need_des + 26 + 1 + read-write + + + THRES0_LOW_INT_RAW + need_des + 27 + 1 + read-write + + + THRES1_HIGH_INT_RAW + need_des + 28 + 1 + read-write + + + THRES0_HIGH_INT_RAW + need_des + 29 + 1 + read-write + + + SAR2_DONE_INT_RAW + need_des + 30 + 1 + read-write + + + SAR1_DONE_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + Register + 0x58 + 0x20 + + + THRES1_LOW_INT_ST + need_des + 26 + 1 + read-only + + + THRES0_LOW_INT_ST + need_des + 27 + 1 + read-only + + + THRES1_HIGH_INT_ST + need_des + 28 + 1 + read-only + + + THRES0_HIGH_INT_ST + need_des + 29 + 1 + read-only + + + APB_SARADC2_DONE_INT_ST + need_des + 30 + 1 + read-only + + + APB_SARADC1_DONE_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_CLR + Register + 0x5C + 0x20 + + + THRES1_LOW_INT_CLR + need_des + 26 + 1 + write-only + + + THRES0_LOW_INT_CLR + need_des + 27 + 1 + write-only + + + THRES1_HIGH_INT_CLR + need_des + 28 + 1 + write-only + + + THRES0_HIGH_INT_CLR + need_des + 29 + 1 + write-only + + + APB_SARADC2_DONE_INT_CLR + need_des + 30 + 1 + write-only + + + APB_SARADC1_DONE_INT_CLR + need_des + 31 + 1 + write-only + + + + + DMA_CONF + Register + 0x60 + 0x20 + 0x000000FF + + + APB_ADC_EOF_NUM + the dma_in_suc_eof gen when sample cnt = spi_eof_num + 0 + 16 + read-write + + + APB_ADC_RESET_FSM + reset_apb_adc_state + 30 + 1 + read-write + + + APB_ADC_TRANS + enable apb_adc use spi_dma + 31 + 1 + read-write + + + + + SAR2_DATA_STATUS + Register + 0x64 + 0x20 + + + APB_SARADC2_DATA + need_des + 0 + 17 + read-only + + + + + CALI + Register + 0x68 + 0x20 + 0x00008000 + + + CFG + need_des + 0 + 17 + read-write + + + + + RND_ECO_LOW + Register + 0x6C + 0x20 + + + RND_ECO_LOW + rnd eco low + 0 + 32 + read-write + + + + + RND_ECO_HIGH + Register + 0x70 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + rnd eco high + 0 + 32 + read-write + + + + + RND_ECO_CS + Register + 0x74 + 0x20 + + + RND_ECO_EN + need_des + 0 + 1 + read-write + + + RND_ECO_RESULT + need_des + 1 + 1 + read-only + + + + + CTRL_DATE + Register + 0x3FC + 0x20 + 0x02212260 + + + CTRL_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + AES + AES (Advanced Encryption Standard) Accelerator + AES + 0x50090000 + + 0x0 + 0xBC + registers + + + AES + 69 + + + + KEY_0 + Key material key_0 configure register + 0x0 + 0x20 + + + KEY_0 + This bits stores key_0 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_1 + Key material key_1 configure register + 0x4 + 0x20 + + + KEY_1 + This bits stores key_1 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_2 + Key material key_2 configure register + 0x8 + 0x20 + + + KEY_2 + This bits stores key_2 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_3 + Key material key_3 configure register + 0xC + 0x20 + + + KEY_3 + This bits stores key_3 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_4 + Key material key_4 configure register + 0x10 + 0x20 + + + KEY_4 + This bits stores key_4 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_5 + Key material key_5 configure register + 0x14 + 0x20 + + + KEY_5 + This bits stores key_5 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_6 + Key material key_6 configure register + 0x18 + 0x20 + + + KEY_6 + This bits stores key_6 that is a part of key material. + 0 + 32 + read-write + + + + + KEY_7 + Key material key_7 configure register + 0x1C + 0x20 + + + KEY_7 + This bits stores key_7 that is a part of key material. + 0 + 32 + read-write + + + + + TEXT_IN_0 + source text material text_in_0 configure register + 0x20 + 0x20 + + + TEXT_IN_0 + This bits stores text_in_0 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_1 + source text material text_in_1 configure register + 0x24 + 0x20 + + + TEXT_IN_1 + This bits stores text_in_1 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_2 + source text material text_in_2 configure register + 0x28 + 0x20 + + + TEXT_IN_2 + This bits stores text_in_2 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_IN_3 + source text material text_in_3 configure register + 0x2C + 0x20 + + + TEXT_IN_3 + This bits stores text_in_3 that is a part of source text material. + 0 + 32 + read-write + + + + + TEXT_OUT_0 + result text material text_out_0 configure register + 0x30 + 0x20 + + + TEXT_OUT_0 + This bits stores text_out_0 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_1 + result text material text_out_1 configure register + 0x34 + 0x20 + + + TEXT_OUT_1 + This bits stores text_out_1 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_2 + result text material text_out_2 configure register + 0x38 + 0x20 + + + TEXT_OUT_2 + This bits stores text_out_2 that is a part of result text material. + 0 + 32 + read-write + + + + + TEXT_OUT_3 + result text material text_out_3 configure register + 0x3C + 0x20 + + + TEXT_OUT_3 + This bits stores text_out_3 that is a part of result text material. + 0 + 32 + read-write + + + + + MODE + AES Mode register + 0x40 + 0x20 + + + MODE + This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. + 0 + 3 + read-write + + + + + ENDIAN + AES Endian configure register + 0x44 + 0x20 + + + ENDIAN + endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian + 0 + 6 + read-write + + + + + TRIGGER + AES trigger register + 0x48 + 0x20 + + + TRIGGER + Set this bit to start AES calculation. + 0 + 1 + write-only + + + + + STATE + AES state register + 0x4C + 0x20 + + + STATE + Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. + 0 + 2 + read-only + + + + + 16 + 0x1 + IV_MEM[%s] + The memory that stores initialization vector + 0x50 + 0x8 + + + 16 + 0x1 + H_MEM[%s] + The memory that stores GCM hash subkey + 0x60 + 0x8 + + + 16 + 0x1 + J0_MEM[%s] + The memory that stores J0 + 0x70 + 0x8 + + + 16 + 0x1 + T0_MEM[%s] + The memory that stores T0 + 0x80 + 0x8 + + + DMA_ENABLE + DMA-AES working mode register + 0x90 + 0x20 + + + DMA_ENABLE + 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. + 0 + 1 + read-write + + + + + BLOCK_MODE + AES cipher block mode register + 0x94 + 0x20 + + + BLOCK_MODE + Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. + 0 + 3 + read-write + + + + + BLOCK_NUM + AES block number register + 0x98 + 0x20 + + + BLOCK_NUM + Those bits stores the number of Plaintext/ciphertext block. + 0 + 32 + read-write + + + + + INC_SEL + Standard incrementing function configure register + 0x9C + 0x20 + + + INC_SEL + This bit decides the standard incrementing function. 0: INC32. 1: INC128. + 0 + 1 + read-write + + + + + AAD_BLOCK_NUM + Additional Authential Data block number register + 0xA0 + 0x20 + + + AAD_BLOCK_NUM + Those bits stores the number of AAD block. + 0 + 32 + read-write + + + + + REMAINDER_BIT_NUM + AES remainder bit number register + 0xA4 + 0x20 + + + REMAINDER_BIT_NUM + Those bits stores the number of remainder bit. + 0 + 7 + read-write + + + + + CONTINUE + AES continue register + 0xA8 + 0x20 + + + CONTINUE + Set this bit to continue GCM operation. + 0 + 1 + write-only + + + + + INT_CLEAR + AES Interrupt clear register + 0xAC + 0x20 + + + INT_CLEAR + Set this bit to clear the AES interrupt. + 0 + 1 + write-only + + + + + INT_ENA + AES Interrupt enable register + 0xB0 + 0x20 + + + INT_ENA + Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + 0 + 1 + read-write + + + + + DATE + AES version control register + 0xB4 + 0x20 + 0x20191210 + + + DATE + This bits stores the version information of AES. + 0 + 30 + read-write + + + + + DMA_EXIT + AES-DMA exit config + 0xB8 + 0x20 + + + DMA_EXIT + Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer. + 0 + 1 + write-only + + + + + + + LP_I2C_ANA_MST + LP_I2C_ANA_MST Peripheral + ANA_I2C_MST + 0x50124000 + + 0x0 + 0x3C + registers + + + + I2C0_CTRL + need des + 0x0 + 0x20 + + + I2C0_CTRL + need des + 0 + 25 + read-write + + + I2C0_BUSY + need des + 25 + 1 + read-only + + + + + I2C1_CTRL + need des + 0x4 + 0x20 + + + I2C1_CTRL + need des + 0 + 25 + read-write + + + I2C1_BUSY + need des + 25 + 1 + read-only + + + + + I2C0_CONF + need des + 0x8 + 0x20 + + + I2C0_CONF + need des + 0 + 24 + read-write + + + I2C0_STATUS + need des + 24 + 8 + read-only + + + + + I2C1_CONF + need des + 0xC + 0x20 + + + I2C1_CONF + need des + 0 + 24 + read-write + + + I2C1_STATUS + need des + 24 + 8 + read-only + + + + + I2C_BURST_CONF + need des + 0x10 + 0x20 + + + I2C_MST_BURST_CTRL + need des + 0 + 32 + read-write + + + + + I2C_BURST_STATUS + need des + 0x14 + 0x20 + 0x40000000 + + + I2C_MST_BURST_DONE + need des + 0 + 1 + read-only + + + I2C_MST0_BURST_ERR_FLAG + need des + 1 + 1 + read-only + + + I2C_MST1_BURST_ERR_FLAG + need des + 2 + 1 + read-only + + + I2C_MST_BURST_TIMEOUT_CNT + need des + 20 + 12 + read-write + + + + + ANA_CONF0 + need des + 0x18 + 0x20 + + + ANA_CONF0 + need des + 0 + 24 + read-write + + + ANA_STATUS0 + need des + 24 + 8 + read-only + + + + + ANA_CONF1 + need des + 0x1C + 0x20 + + + ANA_CONF1 + need des + 0 + 24 + read-write + + + ANA_STATUS1 + need des + 24 + 8 + read-only + + + + + ANA_CONF2 + need des + 0x20 + 0x20 + + + ANA_CONF2 + need des + 0 + 24 + read-write + + + ANA_STATUS2 + need des + 24 + 8 + read-only + + + + + I2C0_CTRL1 + need des + 0x24 + 0x20 + 0x00000042 + + + I2C0_SCL_PULSE_DUR + need des + 0 + 6 + read-write + + + I2C0_SDA_SIDE_GUARD + need des + 6 + 5 + read-write + + + + + I2C1_CTRL1 + need des + 0x28 + 0x20 + 0x00000042 + + + I2C1_SCL_PULSE_DUR + need des + 0 + 6 + read-write + + + I2C1_SDA_SIDE_GUARD + need des + 6 + 5 + read-write + + + + + HW_I2C_CTRL + need des + 0x2C + 0x20 + 0x00000042 + + + HW_I2C_SCL_PULSE_DUR + need des + 0 + 6 + read-write + + + HW_I2C_SDA_SIDE_GUARD + need des + 6 + 5 + read-write + + + ARBITER_DIS + need des + 11 + 1 + read-write + + + + + NOUSE + need des + 0x30 + 0x20 + + + I2C_MST_NOUSE + need des + 0 + 32 + read-write + + + + + CLK160M + need des + 0x34 + 0x20 + + + CLK_I2C_MST_SEL_160M + need des + 0 + 1 + read-write + + + + + DATE + need des + 0x38 + 0x20 + 0x02201300 + + + DATE + need des + 0 + 28 + read-write + + + I2C_MST_CLK_EN + need des + 28 + 1 + read-write + + + + + + + ASSIST_DEBUG + Debug Assist + ASSIST_DEBUG + 0x3FF06000 + + 0x0 + 0x100 + registers + + + ASSIST_DEBUG + 127 + + + + CORE_0_INTR_ENA + core0 monitor enable configuration register + 0x0 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_ENA + Core0 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_ENA + Core0 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_ENA + Core0 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_ENA + Core0 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_ENA + Core0 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_ENA + Core0 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_ENA + Core0 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_ENA + Core0 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_ENA + Core0 stackpoint underflow monitor enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_ENA + Core0 stackpoint overflow monitor enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_RAW + core0 monitor interrupt status register + 0x4 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RAW + Core0 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_0_AREA_DRAM0_0_WR_RAW + Core0 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_RD_RAW + Core0 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_0_AREA_DRAM0_1_WR_RAW + Core0 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_0_AREA_PIF_0_RD_RAW + Core0 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_0_AREA_PIF_0_WR_RAW + Core0 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_0_AREA_PIF_1_RD_RAW + Core0 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_0_AREA_PIF_1_WR_RAW + Core0 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_0_SP_SPILL_MIN_RAW + Core0 stackpoint underflow monitor interrupt status + 8 + 1 + read-only + + + CORE_0_SP_SPILL_MAX_RAW + Core0 stackpoint overflow monitor interrupt status + 9 + 1 + read-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_0_INTR_RLS + core0 monitor interrupt enable register + 0x8 + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_RLS + Core0 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_0_AREA_DRAM0_0_WR_RLS + Core0 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_RD_RLS + Core0 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_0_AREA_DRAM0_1_WR_RLS + Core0 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_0_AREA_PIF_0_RD_RLS + Core0 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_0_AREA_PIF_0_WR_RLS + Core0 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_0_AREA_PIF_1_RD_RLS + Core0 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_0_AREA_PIF_1_WR_RLS + Core0 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_0_SP_SPILL_MIN_RLS + Core0 stackpoint underflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_0_SP_SPILL_MAX_RLS + Core0 stackpoint overflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_0_INTR_CLR + core0 monitor interrupt clr register + 0xC + 0x20 + + + CORE_0_AREA_DRAM0_0_RD_CLR + Core0 dram0 area0 read monitor interrupt clr + 0 + 1 + write-only + + + CORE_0_AREA_DRAM0_0_WR_CLR + Core0 dram0 area0 write monitor interrupt clr + 1 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_RD_CLR + Core0 dram0 area1 read monitor interrupt clr + 2 + 1 + write-only + + + CORE_0_AREA_DRAM0_1_WR_CLR + Core0 dram0 area1 write monitor interrupt clr + 3 + 1 + write-only + + + CORE_0_AREA_PIF_0_RD_CLR + Core0 PIF area0 read monitor interrupt clr + 4 + 1 + write-only + + + CORE_0_AREA_PIF_0_WR_CLR + Core0 PIF area0 write monitor interrupt clr + 5 + 1 + write-only + + + CORE_0_AREA_PIF_1_RD_CLR + Core0 PIF area1 read monitor interrupt clr + 6 + 1 + write-only + + + CORE_0_AREA_PIF_1_WR_CLR + Core0 PIF area1 write monitor interrupt clr + 7 + 1 + write-only + + + CORE_0_SP_SPILL_MIN_CLR + Core0 stackpoint underflow monitor interrupt clr + 8 + 1 + write-only + + + CORE_0_SP_SPILL_MAX_CLR + Core0 stackpoint overflow monitor interrupt clr + 9 + 1 + write-only + + + CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + write-only + + + CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + write-only + + + + + CORE_0_AREA_DRAM0_0_MIN + core0 dram0 region0 addr configuration register + 0x10 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_0_MIN + Core0 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_0_MAX + core0 dram0 region0 addr configuration register + 0x14 + 0x20 + + + CORE_0_AREA_DRAM0_0_MAX + Core0 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MIN + core0 dram0 region1 addr configuration register + 0x18 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_DRAM0_1_MIN + Core0 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_DRAM0_1_MAX + core0 dram0 region1 addr configuration register + 0x1C + 0x20 + + + CORE_0_AREA_DRAM0_1_MAX + Core0 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MIN + core0 PIF region0 addr configuration register + 0x20 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_0_MIN + Core0 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_0_MAX + core0 PIF region0 addr configuration register + 0x24 + 0x20 + + + CORE_0_AREA_PIF_0_MAX + Core0 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MIN + core0 PIF region1 addr configuration register + 0x28 + 0x20 + 0xFFFFFFFF + + + CORE_0_AREA_PIF_1_MIN + Core0 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PIF_1_MAX + core0 PIF region1 addr configuration register + 0x2C + 0x20 + + + CORE_0_AREA_PIF_1_MAX + Core0 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_0_AREA_PC + core0 area pc status register + 0x30 + 0x20 + + + CORE_0_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_AREA_SP + core0 area sp status register + 0x34 + 0x20 + + + CORE_0_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_0_SP_MIN + stack min value + 0x38 + 0x20 + + + CORE_0_SP_MIN + core0 sp region configuration regsiter + 0 + 32 + read-write + + + + + CORE_0_SP_MAX + stack max value + 0x3C + 0x20 + 0xFFFFFFFF + + + CORE_0_SP_MAX + core0 sp pc status register + 0 + 32 + read-write + + + + + CORE_0_SP_PC + stack monitor pc status register + 0x40 + 0x20 + + + CORE_0_SP_PC + This regsiter stores the PC when trigger stack monitor. + 0 + 32 + read-only + + + + + CORE_0_RCD_EN + record enable configuration register + 0x44 + 0x20 + + + CORE_0_RCD_RECORDEN + Set 1 to enable record PC + 0 + 1 + read-write + + + CORE_0_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + 1 + 1 + read-write + + + + + CORE_0_RCD_PDEBUGPC + record status regsiter + 0x48 + 0x20 + + + CORE_0_RCD_PDEBUGPC + recorded PC + 0 + 32 + read-only + + + + + CORE_0_RCD_PDEBUGSP + record status regsiter + 0x4C + 0x20 + + + CORE_0_RCD_PDEBUGSP + recorded sp + 0 + 32 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_0 + exception monitor status register0 + 0x50 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_0 + reg_core_0_iram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_0 + reg_core_0_iram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_0 + reg_core_0_iram0_recording_loadstore_0 + 25 + 1 + read-only + + + + + CORE_0_IRAM0_EXCEPTION_MONITOR_1 + exception monitor status register1 + 0x54 + 0x20 + + + CORE_0_IRAM0_RECORDING_ADDR_1 + reg_core_0_iram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_0_IRAM0_RECORDING_WR_1 + reg_core_0_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_0_IRAM0_RECORDING_LOADSTORE_1 + reg_core_0_iram0_recording_loadstore_1 + 25 + 1 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register2 + 0x58 + 0x20 + + + CORE_0_DRAM0_RECORDING_WR_0 + reg_core_0_dram0_recording_wr_0 + 0 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_0 + reg_core_0_dram0_recording_byteen_0 + 1 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register3 + 0x5C + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_0 + reg_core_0_dram0_recording_addr_0 + 0 + 24 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_2 + exception monitor status register4 + 0x60 + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_0 + reg_core_0_dram0_recording_pc_0 + 0 + 32 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_3 + exception monitor status register5 + 0x64 + 0x20 + + + CORE_0_DRAM0_RECORDING_WR_1 + reg_core_0_dram0_recording_wr_1 + 0 + 1 + read-only + + + CORE_0_DRAM0_RECORDING_BYTEEN_1 + reg_core_0_dram0_recording_byteen_1 + 1 + 16 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_4 + exception monitor status register6 + 0x68 + 0x20 + + + CORE_0_DRAM0_RECORDING_ADDR_1 + reg_core_0_dram0_recording_addr_1 + 0 + 24 + read-only + + + + + CORE_0_DRAM0_EXCEPTION_MONITOR_5 + exception monitor status register7 + 0x6C + 0x20 + + + CORE_0_DRAM0_RECORDING_PC_1 + reg_core_0_dram0_recording_pc_1 + 0 + 32 + read-only + + + + + CORE_0_LASTPC_BEFORE_EXCEPTION + cpu status register + 0x70 + 0x20 + + + CORE_0_LASTPC_BEFORE_EXC + cpu's lastpc before exception + 0 + 32 + read-only + + + + + CORE_0_DEBUG_MODE + cpu status register + 0x74 + 0x20 + + + CORE_0_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. + 0 + 1 + read-only + + + CORE_0_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only + + + + + CORE_1_INTR_ENA + core1 monitor enable configuration register + 0x80 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_ENA + Core1 dram0 area0 read monitor enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_ENA + Core1 dram0 area0 write monitor enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_ENA + Core1 dram0 area1 read monitor enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_ENA + Core1 dram0 area1 write monitor enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_ENA + Core1 PIF area0 read monitor enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_ENA + Core1 PIF area0 write monitor enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_ENA + Core1 PIF area1 read monitor enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_ENA + Core1 PIF area1 write monitor enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_ENA + Core1 stackpoint underflow monitor enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_ENA + Core1 stackpoint overflow monitor enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_ENA + IBUS busy monitor enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_ENA + DBUS busy monitor enbale + 11 + 1 + read-write + + + + + CORE_1_INTR_RAW + core1 monitor interrupt status register + 0x84 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RAW + Core1 dram0 area0 read monitor interrupt status + 0 + 1 + read-only + + + CORE_1_AREA_DRAM0_0_WR_RAW + Core1 dram0 area0 write monitor interrupt status + 1 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_RD_RAW + Core1 dram0 area1 read monitor interrupt status + 2 + 1 + read-only + + + CORE_1_AREA_DRAM0_1_WR_RAW + Core1 dram0 area1 write monitor interrupt status + 3 + 1 + read-only + + + CORE_1_AREA_PIF_0_RD_RAW + Core1 PIF area0 read monitor interrupt status + 4 + 1 + read-only + + + CORE_1_AREA_PIF_0_WR_RAW + Core1 PIF area0 write monitor interrupt status + 5 + 1 + read-only + + + CORE_1_AREA_PIF_1_RD_RAW + Core1 PIF area1 read monitor interrupt status + 6 + 1 + read-only + + + CORE_1_AREA_PIF_1_WR_RAW + Core1 PIF area1 write monitor interrupt status + 7 + 1 + read-only + + + CORE_1_SP_SPILL_MIN_RAW + Core1 stackpoint underflow monitor interrupt status + 8 + 1 + read-only + + + CORE_1_SP_SPILL_MAX_RAW + Core1 stackpoint overflow monitor interrupt status + 9 + 1 + read-only + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RAW + IBUS busy monitor interrupt status + 10 + 1 + read-only + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RAW + DBUS busy monitor initerrupt status + 11 + 1 + read-only + + + + + CORE_1_INTR_RLS + core1 monitor interrupt enable register + 0x88 + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_RLS + Core1 dram0 area0 read monitor interrupt enable + 0 + 1 + read-write + + + CORE_1_AREA_DRAM0_0_WR_RLS + Core1 dram0 area0 write monitor interrupt enable + 1 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_RD_RLS + Core1 dram0 area1 read monitor interrupt enable + 2 + 1 + read-write + + + CORE_1_AREA_DRAM0_1_WR_RLS + Core1 dram0 area1 write monitor interrupt enable + 3 + 1 + read-write + + + CORE_1_AREA_PIF_0_RD_RLS + Core1 PIF area0 read monitor interrupt enable + 4 + 1 + read-write + + + CORE_1_AREA_PIF_0_WR_RLS + Core1 PIF area0 write monitor interrupt enable + 5 + 1 + read-write + + + CORE_1_AREA_PIF_1_RD_RLS + Core1 PIF area1 read monitor interrupt enable + 6 + 1 + read-write + + + CORE_1_AREA_PIF_1_WR_RLS + Core1 PIF area1 write monitor interrupt enable + 7 + 1 + read-write + + + CORE_1_SP_SPILL_MIN_RLS + Core1 stackpoint underflow monitor interrupt enable + 8 + 1 + read-write + + + CORE_1_SP_SPILL_MAX_RLS + Core1 stackpoint overflow monitor interrupt enable + 9 + 1 + read-write + + + CORE_1_IRAM0_EXCEPTION_MONITOR_RLS + IBUS busy monitor interrupt enable + 10 + 1 + read-write + + + CORE_1_DRAM0_EXCEPTION_MONITOR_RLS + DBUS busy monitor interrupt enbale + 11 + 1 + read-write + + + + + CORE_1_INTR_CLR + core1 monitor interrupt clr register + 0x8C + 0x20 + + + CORE_1_AREA_DRAM0_0_RD_CLR + Core1 dram0 area0 read monitor interrupt clr + 0 + 1 + write-only + + + CORE_1_AREA_DRAM0_0_WR_CLR + Core1 dram0 area0 write monitor interrupt clr + 1 + 1 + write-only + + + CORE_1_AREA_DRAM0_1_RD_CLR + Core1 dram0 area1 read monitor interrupt clr + 2 + 1 + write-only + + + CORE_1_AREA_DRAM0_1_WR_CLR + Core1 dram0 area1 write monitor interrupt clr + 3 + 1 + write-only + + + CORE_1_AREA_PIF_0_RD_CLR + Core1 PIF area0 read monitor interrupt clr + 4 + 1 + write-only + + + CORE_1_AREA_PIF_0_WR_CLR + Core1 PIF area0 write monitor interrupt clr + 5 + 1 + write-only + + + CORE_1_AREA_PIF_1_RD_CLR + Core1 PIF area1 read monitor interrupt clr + 6 + 1 + write-only + + + CORE_1_AREA_PIF_1_WR_CLR + Core1 PIF area1 write monitor interrupt clr + 7 + 1 + write-only + + + CORE_1_SP_SPILL_MIN_CLR + Core1 stackpoint underflow monitor interrupt clr + 8 + 1 + write-only + + + CORE_1_SP_SPILL_MAX_CLR + Core1 stackpoint overflow monitor interrupt clr + 9 + 1 + write-only + + + CORE_1_IRAM0_EXCEPTION_MONITOR_CLR + IBUS busy monitor interrupt clr + 10 + 1 + write-only + + + CORE_1_DRAM0_EXCEPTION_MONITOR_CLR + DBUS busy monitor interrupt clr + 11 + 1 + write-only + + + + + CORE_1_AREA_DRAM0_0_MIN + core1 dram0 region0 addr configuration register + 0x90 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_0_MIN + Core1 dram0 region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_0_MAX + core1 dram0 region0 addr configuration register + 0x94 + 0x20 + + + CORE_1_AREA_DRAM0_0_MAX + Core1 dram0 region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MIN + core1 dram0 region1 addr configuration register + 0x98 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_DRAM0_1_MIN + Core1 dram0 region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_DRAM0_1_MAX + core1 dram0 region1 addr configuration register + 0x9C + 0x20 + + + CORE_1_AREA_DRAM0_1_MAX + Core1 dram0 region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MIN + core1 PIF region0 addr configuration register + 0xA0 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_0_MIN + Core1 PIF region0 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_0_MAX + core1 PIF region0 addr configuration register + 0xA4 + 0x20 + + + CORE_1_AREA_PIF_0_MAX + Core1 PIF region0 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MIN + core1 PIF region1 addr configuration register + 0xA8 + 0x20 + 0xFFFFFFFF + + + CORE_1_AREA_PIF_1_MIN + Core1 PIF region1 start addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PIF_1_MAX + core1 PIF region1 addr configuration register + 0xAC + 0x20 + + + CORE_1_AREA_PIF_1_MAX + Core1 PIF region1 end addr + 0 + 32 + read-write + + + + + CORE_1_AREA_PC + core1 area pc status register + 0xB0 + 0x20 + + + CORE_1_AREA_PC + the stackpointer when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_AREA_SP + core1 area sp status register + 0xB4 + 0x20 + + + CORE_1_AREA_SP + the PC when first touch region monitor interrupt + 0 + 32 + read-only + + + + + CORE_1_SP_MIN + stack min value + 0xB8 + 0x20 + + + CORE_1_SP_MIN + core1 sp region configuration regsiter + 0 + 32 + read-write + + + + + CORE_1_SP_MAX + stack max value + 0xBC + 0x20 + 0xFFFFFFFF + + + CORE_1_SP_MAX + core1 sp pc status register + 0 + 32 + read-write + + + + + CORE_1_SP_PC + stack monitor pc status register + 0xC0 + 0x20 + + + CORE_1_SP_PC + This regsiter stores the PC when trigger stack monitor. + 0 + 32 + read-only + + + + + CORE_1_RCD_EN + record enable configuration register + 0xC4 + 0x20 + + + CORE_1_RCD_RECORDEN + Set 1 to enable record PC + 0 + 1 + read-write + + + CORE_1_RCD_PDEBUGEN + Set 1 to enable cpu pdebug function, must set this bit can get cpu PC + 1 + 1 + read-write + + + + + CORE_1_RCD_PDEBUGPC + record status regsiter + 0xC8 + 0x20 + + + CORE_1_RCD_PDEBUGPC + recorded PC + 0 + 32 + read-only + + + + + CORE_1_RCD_PDEBUGSP + record status regsiter + 0xCC + 0x20 + + + CORE_1_RCD_PDEBUGSP + recorded sp + 0 + 32 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_0 + exception monitor status register0 + 0xD0 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_0 + reg_core_1_iram0_recording_addr_0 + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_0 + reg_core_1_iram0_recording_wr_0 + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_0 + reg_core_1_iram0_recording_loadstore_0 + 25 + 1 + read-only + + + + + CORE_1_IRAM0_EXCEPTION_MONITOR_1 + exception monitor status register1 + 0xD4 + 0x20 + + + CORE_1_IRAM0_RECORDING_ADDR_1 + reg_core_1_iram0_recording_addr_1 + 0 + 24 + read-only + + + CORE_1_IRAM0_RECORDING_WR_1 + reg_core_1_iram0_recording_wr_1 + 24 + 1 + read-only + + + CORE_1_IRAM0_RECORDING_LOADSTORE_1 + reg_core_1_iram0_recording_loadstore_1 + 25 + 1 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register2 + 0xD8 + 0x20 + + + CORE_1_DRAM0_RECORDING_WR_0 + reg_core_1_dram0_recording_wr_0 + 0 + 1 + read-only + + + CORE_1_DRAM0_RECORDING_BYTEEN_0 + reg_core_1_dram0_recording_byteen_0 + 1 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register3 + 0xDC + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_0 + reg_core_1_dram0_recording_addr_0 + 0 + 24 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_2 + exception monitor status register4 + 0xE0 + 0x20 + + + CORE_1_DRAM0_RECORDING_PC_0 + reg_core_1_dram0_recording_pc_0 + 0 + 32 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_3 + exception monitor status register5 + 0xE4 + 0x20 + + + CORE_1_DRAM0_RECORDING_WR_1 + reg_core_1_dram0_recording_wr_1 + 0 + 1 + read-only + + + CORE_1_DRAM0_RECORDING_BYTEEN_1 + reg_core_1_dram0_recording_byteen_1 + 1 + 16 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_4 + exception monitor status register6 + 0xE8 + 0x20 + + + CORE_1_DRAM0_RECORDING_ADDR_1 + reg_core_1_dram0_recording_addr_1 + 0 + 24 + read-only + + + + + CORE_1_DRAM0_EXCEPTION_MONITOR_5 + exception monitor status register7 + 0xEC + 0x20 + + + CORE_1_DRAM0_RECORDING_PC_1 + reg_core_1_dram0_recording_pc_1 + 0 + 32 + read-only + + + + + CORE_1_LASTPC_BEFORE_EXCEPTION + cpu status register + 0xF0 + 0x20 + + + CORE_1_LASTPC_BEFORE_EXC + cpu's lastpc before exception + 0 + 32 + read-only + + + + + CORE_1_DEBUG_MODE + cpu status register + 0xF4 + 0x20 + + + CORE_1_DEBUG_MODE + cpu debug mode status, 1 means cpu enter debug mode. + 0 + 1 + read-only + + + CORE_1_DEBUG_MODULE_ACTIVE + cpu debug_module active status + 1 + 1 + read-only + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + exception monitor status register6 + 0x100 + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + reg_core_x_iram0_dram0_limit_cycle_0 + 0 + 20 + read-write + + + + + CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + exception monitor status register7 + 0x104 + 0x20 + + + CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + reg_core_x_iram0_dram0_limit_cycle_1 + 0 + 20 + read-write + + + + + CLOCK_GATE + clock register + 0x108 + 0x20 + 0x00000001 + + + CLK_EN + Set 1 force on the clock gate + 0 + 1 + read-write + + + + + DATE + version register + 0x3FC + 0x20 + 0x02109130 + + + ASSIST_DEBUG_DATE + version register + 0 + 28 + read-write + + + + + + + AXI_DMA + AXI_DMA Peripheral + AXI_DMA + 0x5008A000 + + 0x0 + 0x2D8 + registers + + + + 3 + 0x68 + IN_INT_RAW_CH%s + Raw status interrupt of channel 0 + 0x0 + 0x20 + + + IN_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_RAW + The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + 4 + 1 + read-write + + + INFIFO_L1_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 5 + 1 + read-write + + + INFIFO_L1_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 6 + 1 + read-write + + + INFIFO_L2_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 7 + 1 + read-write + + + INFIFO_L2_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 8 + 1 + read-write + + + INFIFO_L3_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + 9 + 1 + read-write + + + INFIFO_L3_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + 10 + 1 + read-write + + + + + 3 + 0x68 + IN_INT_ST_CH%s + Masked interrupt of channel 0 + 0x4 + 0x20 + + + IN_DONE_CH_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + IN_DSCR_EMPTY_CH_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_L1_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + INFIFO_L1_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 8 + 1 + read-only + + + INFIFO_L3_OVF_CH_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + 9 + 1 + read-only + + + INFIFO_L3_UDF_CH_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + 10 + 1 + read-only + + + + + 3 + 0x68 + IN_INT_ENA_CH%s + Interrupt enable bits of channel 0 + 0x8 + 0x20 + + + IN_DONE_CH_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + IN_DSCR_EMPTY_CH_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_L1_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_L1_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_L2_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + INFIFO_L2_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 8 + 1 + read-write + + + INFIFO_L3_OVF_CH_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + 9 + 1 + read-write + + + INFIFO_L3_UDF_CH_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + 10 + 1 + read-write + + + + + 3 + 0x68 + IN_INT_CLR_CH%s + Interrupt clear bits of channel 0 + 0xC + 0x20 + + + IN_DONE_CH_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH_INT_CLR + Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + IN_DSCR_EMPTY_CH_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_L1_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_L1_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_L2_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + INFIFO_L2_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 8 + 1 + write-only + + + INFIFO_L3_OVF_CH_INT_CLR + Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + 9 + 1 + write-only + + + INFIFO_L3_UDF_CH_INT_CLR + Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + 10 + 1 + write-only + + + + + 3 + 0x68 + IN_CONF0_CH%s + Configure 0 register of Rx channel 0 + 0x10 + 0x20 + + + IN_RST_CH + This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer. + 0 + 1 + read-write + + + IN_LOOP_TEST_CH + reserved + 1 + 1 + read-write + + + MEM_TRANS_EN_CH + Set this bit 1 to enable automatic transmitting data from memory to memory via AXI_DMA. + 2 + 1 + read-write + + + IN_ETM_EN_CH + Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. + 3 + 1 + read-write + + + IN_BURST_SIZE_SEL_CH + 3'b000-3'b100:burst length 8byte~128byte + 4 + 3 + read-write + + + IN_CMD_DISABLE_CH + 1:mean disable cmd of this ch0 + 7 + 1 + read-write + + + IN_ECC_AEC_EN_CH + 1: mean access ecc or aes domain,0: mean not + 8 + 1 + read-write + + + INDSCR_BURST_EN_CH + Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + 9 + 1 + read-write + + + + + 3 + 0x68 + IN_CONF1_CH%s + Configure 1 register of Rx channel 0 + 0x14 + 0x20 + + + IN_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0x68 + INFIFO_STATUS_CH%s + Receive FIFO status of Rx channel 0 + 0x18 + 0x20 + 0x00008803 + + + INFIFO_L3_FULL_CH + L3 Rx FIFO full signal for Rx channel 0. + 0 + 1 + read-only + + + INFIFO_L3_EMPTY_CH + L3 Rx FIFO empty signal for Rx channel 0. + 1 + 1 + read-only + + + INFIFO_L3_CNT_CH + The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. + 2 + 6 + read-only + + + INFIFO_L3_UDF_CH + L3 Rx FIFO under flow signal for Rx channel 0. + 8 + 1 + read-only + + + INFIFO_L3_OVF_CH + L3 Rx FIFO over flow signal for Rx channel 0. + 9 + 1 + read-only + + + INFIFO_L1_FULL_CH + L1 Rx FIFO full signal for Rx channel 0. + 10 + 1 + read-only + + + INFIFO_L1_EMPTY_CH + L1 Rx FIFO empty signal for Rx channel 0. + 11 + 1 + read-only + + + INFIFO_L1_UDF_CH + L1 Rx FIFO under flow signal for Rx channel 0. + 12 + 1 + read-only + + + INFIFO_L1_OVF_CH + L1 Rx FIFO over flow signal for Rx channel 0. + 13 + 1 + read-only + + + INFIFO_L2_FULL_CH + L2 Rx RAM full signal for Rx channel 0. + 14 + 1 + read-only + + + INFIFO_L2_EMPTY_CH + L2 Rx RAM empty signal for Rx channel 0. + 15 + 1 + read-only + + + INFIFO_L2_UDF_CH + L2 Rx FIFO under flow signal for Rx channel 0. + 16 + 1 + read-only + + + INFIFO_L2_OVF_CH + L2 Rx FIFO over flow signal for Rx channel 0. + 17 + 1 + read-only + + + IN_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + IN_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + IN_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + IN_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + IN_REMAIN_UNDER_5B_CH + reserved + 27 + 1 + read-only + + + IN_REMAIN_UNDER_6B_CH + reserved + 28 + 1 + read-only + + + IN_REMAIN_UNDER_7B_CH + reserved + 29 + 1 + read-only + + + IN_REMAIN_UNDER_8B_CH + reserved + 30 + 1 + read-only + + + IN_BUF_HUNGRY_CH + reserved + 31 + 1 + read-only + + + + + 3 + 0x68 + IN_POP_CH%s + Pop control register of Rx channel 0 + 0x1C + 0x20 + 0x00000800 + + + INFIFO_RDATA_CH + This register stores the data popping from AXI_DMA FIFO. + 0 + 12 + read-only + + + INFIFO_POP_CH + Set this bit to pop data from AXI_DMA FIFO. + 12 + 1 + write-only + + + + + 3 + 0x68 + IN_LINK1_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x20 + 0x20 + 0x00000011 + + + INLINK_AUTO_RET_CH + Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. + 0 + 1 + read-write + + + INLINK_STOP_CH + Set this bit to stop dealing with the inlink descriptors. + 1 + 1 + write-only + + + INLINK_START_CH + Set this bit to start dealing with the inlink descriptors. + 2 + 1 + write-only + + + INLINK_RESTART_CH + Set this bit to mount a new inlink descriptor. + 3 + 1 + write-only + + + INLINK_PARK_CH + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 4 + 1 + read-only + + + + + 3 + 0x68 + IN_LINK2_CH%s + Link descriptor configure and control register of Rx channel 0 + 0x24 + 0x20 + + + INLINK_ADDR_CH + This register stores the 20 least significant bits of the first inlink descriptor's address. + 0 + 32 + read-write + + + + + 3 + 0x68 + IN_STATE_CH%s + Receive status of Rx channel 0 + 0x28 + 0x20 + + + INLINK_DSCR_ADDR_CH + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + IN_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0x68 + IN_SUC_EOF_DES_ADDR_CH%s + Inlink descriptor address when EOF occurs of Rx channel 0 + 0x2C + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_ERR_EOF_DES_ADDR_CH%s + Inlink descriptor address when errors occur of Rx channel 0 + 0x30 + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH + This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_DSCR_CH%s + Current inlink descriptor address of Rx channel 0 + 0x34 + 0x20 + + + INLINK_DSCR_CH + The address of the current inlink descriptor x. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_DSCR_BF0_CH%s + The last inlink descriptor address of Rx channel 0 + 0x38 + 0x20 + + + INLINK_DSCR_BF0_CH + The address of the last inlink descriptor x-1. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_DSCR_BF1_CH%s + The second-to-last inlink descriptor address of Rx channel 0 + 0x3C + 0x20 + + + INLINK_DSCR_BF1_CH + The address of the second-to-last inlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0x68 + IN_PRI_CH%s + Priority register of Rx channel 0 + 0x40 + 0x20 + + + RX_PRI_CH + The priority of Rx channel 0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + RX_CH_ARB_WEIGH_CH + The weight of Rx channel 0 + 4 + 4 + read-write + + + RX_ARB_WEIGH_OPT_DIR_CH + 0: mean not optimazation weight function ,1: mean optimazation + 8 + 1 + read-write + + + + + 3 + 0x68 + IN_PERI_SEL_CH%s + Peripheral selection of Rx channel 0 + 0x44 + 0x20 + 0x0000003F + + + PERI_IN_SEL_CH + This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy + 0 + 6 + read-write + + + + + 3 + 0x68 + IN_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x48 + 0x20 + 0xFFFFFFFF + + + IN_CRC_INIT_DATA_CH + This register is used to config ch0 of rx crc initial value + 0 + 32 + read-write + + + + + 3 + 0x68 + RX_CRC_WIDTH_CH%s + This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x4C + 0x20 + + + RX_CRC_WIDTH_CH + reserved + 0 + 2 + read-write + + + RX_CRC_LAUTCH_FLGA_CH + reserved + 2 + 1 + read-write + + + + + 3 + 0x68 + IN_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x50 + 0x20 + + + IN_CRC_CLEAR_CH + This register is used to clear ch0 of rx crc result + 0 + 1 + read-write + + + + + 3 + 0x68 + IN_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x54 + 0x20 + + + IN_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of rx + 0 + 32 + read-only + + + + + 3 + 0x68 + RX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x58 + 0x20 + + + RX_CRC_EN_WR_DATA_CH + This register is used to enable rx ch0 crc 32bit on/off + 0 + 32 + read-write + + + + + 3 + 0x68 + RX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x5C + 0x20 + + + RX_CRC_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x68 + RX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x60 + 0x20 + + + RX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 16 + read-write + + + + + 3 + 0x68 + RX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x64 + 0x20 + + + RX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x68 + OUT_INT_RAW_CH%s + Raw status interrupt of channel0 + 0x138 + 0x20 + + + OUT_DONE_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel0. + 3 + 1 + read-write + + + OUTFIFO_L1_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + 4 + 1 + read-write + + + OUTFIFO_L1_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + 5 + 1 + read-write + + + OUTFIFO_L2_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + 6 + 1 + read-write + + + OUTFIFO_L2_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + 7 + 1 + read-write + + + OUTFIFO_L3_OVF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is overflow. + 8 + 1 + read-write + + + OUTFIFO_L3_UDF_CH_INT_RAW + This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is underflow. + 9 + 1 + read-write + + + + + 3 + 0x68 + OUT_INT_ST_CH%s + Masked interrupt of channel0 + 0x13C + 0x20 + + + OUT_DONE_CH_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_L1_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_L1_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUTFIFO_L3_OVF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-only + + + OUTFIFO_L3_UDF_CH_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-only + + + + + 3 + 0x68 + OUT_INT_ENA_CH%s + Interrupt enable bits of channel0 + 0x140 + 0x20 + + + OUT_DONE_CH_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_L1_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_L1_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_L2_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_L2_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUTFIFO_L3_OVF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + read-write + + + OUTFIFO_L3_UDF_CH_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + read-write + + + + + 3 + 0x68 + OUT_INT_CLR_CH%s + Interrupt clear bits of channel0 + 0x144 + 0x20 + + + OUT_DONE_CH_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_L1_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_L1_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_L2_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_L2_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUTFIFO_L3_OVF_CH_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. + 8 + 1 + write-only + + + OUTFIFO_L3_UDF_CH_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. + 9 + 1 + write-only + + + + + OUT_CONF0_CH0 + Configure 0 register of Tx channel0 + 0x148 + 0x20 + 0x00000008 + + + OUT_RST_CH0 + This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH0 + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH0 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH0 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is generated when data need to transmit has been popped from FIFO in AXI_DMA + 3 + 1 + read-write + + + OUT_ETM_EN_CH0 + Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm task. + 4 + 1 + read-write + + + OUT_BURST_SIZE_SEL_CH0 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 + read-write + + + OUT_CMD_DISABLE_CH0 + 1:mean disable cmd of this ch0 + 8 + 1 + read-write + + + OUT_ECC_AEC_EN_CH0 + 1: mean access ecc or aes domain,0: mean not + 9 + 1 + read-write + + + OUTDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link descriptor when accessing internal SRAM. + 10 + 1 + read-write + + + + + 3 + 0x68 + OUT_CONF1_CH%s + Configure 1 register of Tx channel0 + 0x14C + 0x20 + + + OUT_CHECK_OWNER_CH + Set this bit to enable checking the owner attribute of the link descriptor. + 12 + 1 + read-write + + + + + 3 + 0x68 + OUTFIFO_STATUS_CH%s + Transmit FIFO status of Tx channel0 + 0x150 + 0x20 + 0x7F808802 + + + OUTFIFO_L3_FULL_CH + L3 Tx FIFO full signal for Tx channel0. + 0 + 1 + read-only + + + OUTFIFO_L3_EMPTY_CH + L3 Tx FIFO empty signal for Tx channel0. + 1 + 1 + read-only + + + OUTFIFO_L3_CNT_CH + The register stores the byte number of the data in L3 Tx FIFO for Tx channel0. + 2 + 6 + read-only + + + OUTFIFO_L3_UDF_CH + L3 Tx FIFO under flow signal for Tx channel0. + 8 + 1 + read-only + + + OUTFIFO_L3_OVF_CH + L3 Tx FIFO over flow signal for Tx channel0. + 9 + 1 + read-only + + + OUTFIFO_L1_FULL_CH + L1 Tx FIFO full signal for Tx channel0. + 10 + 1 + read-only + + + OUTFIFO_L1_EMPTY_CH + L1 Tx FIFO empty signal for Tx channel0. + 11 + 1 + read-only + + + OUTFIFO_L1_UDF_CH + L1 Tx FIFO under flow signal for Tx channel0. + 12 + 1 + read-only + + + OUTFIFO_L1_OVF_CH + L1 Tx FIFO over flow signal for Tx channel0. + 13 + 1 + read-only + + + OUTFIFO_L2_FULL_CH + L2 Tx RAM full signal for Tx channel0. + 14 + 1 + read-only + + + OUTFIFO_L2_EMPTY_CH + L2 Tx RAM empty signal for Tx channel0. + 15 + 1 + read-only + + + OUTFIFO_L2_UDF_CH + L2 Tx FIFO under flow signal for Tx channel0. + 16 + 1 + read-only + + + OUTFIFO_L2_OVF_CH + L2 Tx FIFO over flow signal for Tx channel0. + 17 + 1 + read-only + + + OUT_REMAIN_UNDER_1B_CH + reserved + 23 + 1 + read-only + + + OUT_REMAIN_UNDER_2B_CH + reserved + 24 + 1 + read-only + + + OUT_REMAIN_UNDER_3B_CH + reserved + 25 + 1 + read-only + + + OUT_REMAIN_UNDER_4B_CH + reserved + 26 + 1 + read-only + + + OUT_REMAIN_UNDER_5B_CH + reserved + 27 + 1 + read-only + + + OUT_REMAIN_UNDER_6B_CH + reserved + 28 + 1 + read-only + + + OUT_REMAIN_UNDER_7B_CH + reserved + 29 + 1 + read-only + + + OUT_REMAIN_UNDER_8B_CH + reserved + 30 + 1 + read-only + + + + + 3 + 0x68 + OUT_PUSH_CH%s + Push control register of Tx channel0 + 0x154 + 0x20 + + + OUTFIFO_WDATA_CH + This register stores the data that need to be pushed into AXI_DMA FIFO. + 0 + 9 + read-write + + + OUTFIFO_PUSH_CH + Set this bit to push data into AXI_DMA FIFO. + 9 + 1 + write-only + + + + + 3 + 0x68 + OUT_LINK1_CH%s + Link descriptor configure and control register of Tx channel0 + 0x158 + 0x20 + 0x00000008 + + + OUTLINK_STOP_CH + Set this bit to stop dealing with the outlink descriptors. + 0 + 1 + write-only + + + OUTLINK_START_CH + Set this bit to start dealing with the outlink descriptors. + 1 + 1 + write-only + + + OUTLINK_RESTART_CH + Set this bit to restart a new outlink from the last address. + 2 + 1 + write-only + + + OUTLINK_PARK_CH + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 3 + 1 + read-only + + + + + 3 + 0x68 + OUT_LINK2_CH%s + Link descriptor configure and control register of Tx channel0 + 0x15C + 0x20 + + + OUTLINK_ADDR_CH + This register stores the 32 least significant bits of the first outlink descriptor's address. + 0 + 32 + read-write + + + + + 3 + 0x68 + OUT_STATE_CH%s + Transmit status of Tx channel0 + 0x160 + 0x20 + + + OUTLINK_DSCR_ADDR_CH + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH + reserved + 18 + 2 + read-only + + + OUT_STATE_CH + reserved + 20 + 3 + read-only + + + + + 3 + 0x68 + OUT_EOF_DES_ADDR_CH%s + Outlink descriptor address when EOF occurs of Tx channel0 + 0x164 + 0x20 + + + OUT_EOF_DES_ADDR_CH + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_EOF_BFR_DES_ADDR_CH%s + The last outlink descriptor address when EOF occurs of Tx channel0 + 0x168 + 0x20 + + + OUT_EOF_BFR_DES_ADDR_CH + This register stores the address of the outlink descriptor before the last outlink descriptor. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_DSCR_CH%s + Current outlink descriptor address of Tx channel0 + 0x16C + 0x20 + + + OUTLINK_DSCR_CH + The address of the current outlink descriptor y. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_DSCR_BF0_CH%s + The last outlink descriptor address of Tx channel0 + 0x170 + 0x20 + + + OUTLINK_DSCR_BF0_CH + The address of the last outlink descriptor y-1. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_DSCR_BF1_CH%s + The second-to-last outlink descriptor address of Tx channel0 + 0x174 + 0x20 + + + OUTLINK_DSCR_BF1_CH + The address of the second-to-last outlink descriptor x-2. + 0 + 32 + read-only + + + + + 3 + 0x68 + OUT_PRI_CH%s + Priority register of Tx channel0. + 0x178 + 0x20 + + + TX_PRI_CH + The priority of Tx channel0. The larger of the value the higher of the priority. + 0 + 4 + read-write + + + TX_CH_ARB_WEIGH_CH + The weight of Tx channel0 + 4 + 4 + read-write + + + TX_ARB_WEIGH_OPT_DIR_CH + 0: mean not optimazation weight function ,1: mean optimazation + 8 + 1 + read-write + + + + + 3 + 0x68 + OUT_PERI_SEL_CH%s + Peripheral selection of Tx channel0 + 0x17C + 0x20 + 0x0000003F + + + PERI_OUT_SEL_CH + This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy + 0 + 6 + read-write + + + + + 3 + 0x68 + OUT_CRC_INIT_DATA_CH%s + This register is used to config ch0 crc initial data(max 32 bit) + 0x180 + 0x20 + 0xFFFFFFFF + + + OUT_CRC_INIT_DATA_CH + This register is used to config ch0 of tx crc initial value + 0 + 32 + read-write + + + + + 3 + 0x68 + TX_CRC_WIDTH_CH%s + This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean 24<crc_width<=32 + 0x184 + 0x20 + + + TX_CRC_WIDTH_CH + reserved + 0 + 2 + read-write + + + TX_CRC_LAUTCH_FLGA_CH + reserved + 2 + 1 + read-write + + + + + 3 + 0x68 + OUT_CRC_CLEAR_CH%s + This register is used to clear ch0 crc result + 0x188 + 0x20 + + + OUT_CRC_CLEAR_CH + This register is used to clear ch0 of tx crc result + 0 + 1 + read-write + + + + + 3 + 0x68 + OUT_CRC_FINAL_RESULT_CH%s + This register is used to store ch0 crc result + 0x18C + 0x20 + + + OUT_CRC_FINAL_RESULT_CH + This register is used to store result ch0 of tx + 0 + 32 + read-only + + + + + 3 + 0x68 + TX_CRC_EN_WR_DATA_CH%s + This resister is used to config ch0 crc en for every bit + 0x190 + 0x20 + + + TX_CRC_EN_WR_DATA_CH + This register is used to enable tx ch0 crc 32bit on/off + 0 + 32 + read-write + + + + + 3 + 0x68 + TX_CRC_EN_ADDR_CH%s + This register is used to config ch0 crc en addr + 0x194 + 0x20 + + + TX_CRC_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + 3 + 0x68 + TX_CRC_DATA_EN_WR_DATA_CH%s + This register is used to config crc data_8bit en + 0x198 + 0x20 + + + TX_CRC_DATA_EN_WR_DATA_CH + reserved + 0 + 16 + read-write + + + + + 3 + 0x68 + TX_CRC_DATA_EN_ADDR_CH%s + This register is used to config addr of crc data_8bit en + 0x19C + 0x20 + + + TX_CRC_DATA_EN_ADDR_CH + reserved + 0 + 32 + read-write + + + + + OUT_CONF0_CH1 + Configure 0 register of Tx channel1 + 0x1B0 + 0x20 + 0x00000008 + + + OUT_RST_CH1 + This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH1 + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH1 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH1 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is generated when data need to transmit has been popped from FIFO in AXI_DMA + 3 + 1 + read-write + + + OUT_ETM_EN_CH1 + Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm task. + 4 + 1 + read-write + + + OUT_BURST_SIZE_SEL_CH1 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 + read-write + + + OUT_CMD_DISABLE_CH1 + 1:mean disable cmd of this ch1 + 8 + 1 + read-write + + + OUT_ECC_AEC_EN_CH1 + 1: mean access ecc or aes domain,0: mean not + 9 + 1 + read-write + + + OUTDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link descriptor when accessing internal SRAM. + 10 + 1 + read-write + + + + + OUT_CONF0_CH2 + Configure 0 register of Tx channel2 + 0x218 + 0x20 + 0x00000008 + + + OUT_RST_CH2 + This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer. + 0 + 1 + read-write + + + OUT_LOOP_TEST_CH2 + reserved + 1 + 1 + read-write + + + OUT_AUTO_WRBACK_CH2 + Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + 2 + 1 + read-write + + + OUT_EOF_MODE_CH2 + EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is generated when data need to transmit has been popped from FIFO in AXI_DMA + 3 + 1 + read-write + + + OUT_ETM_EN_CH2 + Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm task. + 4 + 1 + read-write + + + OUT_BURST_SIZE_SEL_CH2 + 3'b000-3'b100:burst length 8byte~128byte + 5 + 3 + read-write + + + OUT_CMD_DISABLE_CH2 + 1:mean disable cmd of this ch2 + 8 + 1 + read-write + + + OUT_ECC_AEC_EN_CH2 + 1: mean access ecc or aes domain,0: mean not + 9 + 1 + read-write + + + OUTDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link descriptor when accessing internal SRAM. + 10 + 1 + read-write + + + + + ARB_TIMEOUT + This retister is used to config arbiter time slice + 0x270 + 0x20 + + + TX + This register is used to config tx arbiter time out value + 0 + 16 + read-write + + + RX + This register is used to config rx arbiter time out value + 16 + 16 + read-write + + + + + WEIGHT_EN + This register is used to config arbiter weight function to on or off + 0x274 + 0x20 + + + TX + This register is used to config tx arbiter weight function off/on + 0 + 1 + read-write + + + RX + This register is used to config rx arbiter weight function off/on + 1 + 1 + read-write + + + + + IN_MEM_CONF + Mem power configure register of Rx channel + 0x278 + 0x20 + + + IN_MEM_CLK_FORCE_EN + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. + 0 + 1 + read-write + + + IN_MEM_FORCE_PU + Force power up ram + 1 + 1 + read-write + + + IN_MEM_FORCE_PD + Force power down ram + 2 + 1 + read-write + + + OUT_MEM_CLK_FORCE_EN + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA. + 3 + 1 + read-write + + + OUT_MEM_FORCE_PU + Force power up ram + 4 + 1 + read-write + + + OUT_MEM_FORCE_PD + Force power down ram + 5 + 1 + read-write + + + + + INTR_MEM_START_ADDR + The start address of accessible address space. + 0x27C + 0x20 + 0x30100000 + + + ACCESS_INTR_MEM_START_ADDR + The start address of accessible address space. + 0 + 32 + read-write + + + + + INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0x280 + 0x20 + 0x8FFFFFFF + + + ACCESS_INTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + EXTR_MEM_START_ADDR + The start address of accessible address space. + 0x284 + 0x20 + 0x30100000 + + + ACCESS_EXTR_MEM_START_ADDR + The start address of accessible address space. + 0 + 32 + read-write + + + + + EXTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0x288 + 0x20 + 0x8FFFFFFF + + + ACCESS_EXTR_MEM_END_ADDR + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + 3 + 0x4 + IN_RESET_AVAIL_CH%s + The rx channel 0 reset valid_flag register. + 0x28C + 0x20 + 0x00000001 + + + IN_RESET_AVAIL_CH + rx chan0 reset valid reg. + 0 + 1 + read-only + + + + + 3 + 0x4 + OUT_RESET_AVAIL_CH%s + The tx channel 0 reset valid_flag register. + 0x298 + 0x20 + 0x00000001 + + + OUT_RESET_AVAIL_CH + tx chan0 reset valid reg. + 0 + 1 + read-only + + + + + MISC_CONF + MISC register + 0x2A8 + 0x20 + + + AXIM_RST_WR_INTER + Set this bit then clear this bit to reset the internal axi_wr FSM. + 0 + 1 + read-write + + + AXIM_RST_RD_INTER + Set this bit then clear this bit to reset the internal axi_rd FSM. + 1 + 1 + read-write + + + ARB_PRI_DIS + Set this bit to disable priority arbitration function. + 3 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 4 + 1 + read-write + + + + + RDN_RESULT + reserved + 0x2AC + 0x20 + + + RDN_ENA + reserved + 0 + 1 + read-write + + + RDN_RESULT + reserved + 1 + 1 + read-only + + + + + RDN_ECO_HIGH + reserved + 0x2B0 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + The start address of accessible address space. + 0 + 32 + read-write + + + + + RDN_ECO_LOW + reserved + 0x2B4 + 0x20 + + + RDN_ECO_LOW + The start address of accessible address space. + 0 + 32 + read-write + + + + + WRESP_CNT + AXI wr responce cnt register. + 0x2B8 + 0x20 + + + WRESP_CNT + axi wr responce cnt reg. + 0 + 4 + read-only + + + + + RRESP_CNT + AXI wr responce cnt register. + 0x2BC + 0x20 + + + RRESP_CNT + axi rd responce cnt reg. + 0 + 4 + read-only + + + + + 3 + 0x4 + INFIFO_STATUS1_CH%s + Receive FIFO status of Rx channel 0 + 0x2C0 + 0x20 + + + L1INFIFO_CNT_CH + The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + 0 + 6 + read-only + + + L2INFIFO_CNT_CH + The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. + 6 + 4 + read-only + + + + + 3 + 0x4 + OUTFIFO_STATUS1_CH%s + Receive FIFO status of Tx channel 0 + 0x2CC + 0x20 + + + L1OUTFIFO_CNT_CH + The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + 0 + 6 + read-only + + + L2OUTFIFO_CNT_CH + The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. + 6 + 4 + read-only + + + + + DATE + Version control register + 0x2D8 + 0x20 + 0x02303140 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + BITSCRAMBLER + BITSCRAMBLER Peripheral + BITSCRAMBLER + 0x500A3000 + + 0x0 + 0x40 + registers + + + + TX_INST_CFG0 + Control and configuration registers + 0x0 + 0x20 + + + TX_INST_IDX + write this bits to specify the one of 8 instruction + 0 + 3 + read-write + + + TX_INST_POS + write this bits to specify the bit position of 257 bit instruction which in units of 32 bits + 3 + 4 + read-write + + + + + TX_INST_CFG1 + Control and configuration registers + 0x4 + 0x20 + 0x00000004 + + + TX_INST + write this bits to update instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG + 0 + 32 + read-write + + + + + RX_INST_CFG0 + Control and configuration registers + 0x8 + 0x20 + + + RX_INST_IDX + write this bits to specify the one of 8 instruction + 0 + 3 + read-write + + + RX_INST_POS + write this bits to specify the bit position of 257 bit instruction which in units of 32 bits + 3 + 4 + read-write + + + + + RX_INST_CFG1 + Control and configuration registers + 0xC + 0x20 + 0x0000000C + + + RX_INST + write this bits to update instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG + 0 + 32 + read-write + + + + + TX_LUT_CFG0 + Control and configuration registers + 0x10 + 0x20 + + + TX_LUT_IDX + write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_tx_lut_mode + 0 + 11 + read-write + + + TX_LUT_MODE + write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes + 11 + 2 + read-write + + + + + TX_LUT_CFG1 + Control and configuration registers + 0x14 + 0x20 + 0x00000014 + + + TX_LUT + write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG + 0 + 32 + read-write + + + + + RX_LUT_CFG0 + Control and configuration registers + 0x18 + 0x20 + + + RX_LUT_IDX + write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_rx_lut_mode + 0 + 11 + read-write + + + RX_LUT_MODE + write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4 bytes + 11 + 2 + read-write + + + + + RX_LUT_CFG1 + Control and configuration registers + 0x1C + 0x20 + 0x0000001C + + + RX_LUT + write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG + 0 + 32 + read-write + + + + + TX_TAILING_BITS + Control and configuration registers + 0x20 + 0x20 + + + TX_TAILING_BITS + write this bits to specify the extra data bit length after getting EOF + 0 + 16 + read-write + + + + + RX_TAILING_BITS + Control and configuration registers + 0x24 + 0x20 + + + RX_TAILING_BITS + write this bits to specify the extra data bit length after getting EOF + 0 + 16 + read-write + + + + + TX_CTRL + Control and configuration registers + 0x28 + 0x20 + 0x00000004 + + + TX_ENA + write this bit to enable the bitscrambler tx + 0 + 1 + read-write + + + TX_PAUSE + write this bit to pause the bitscrambler tx core + 1 + 1 + read-write + + + TX_HALT + write this bit to halt the bitscrambler tx core + 2 + 1 + read-write + + + TX_EOF_MODE + write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer + 3 + 1 + read-write + + + TX_COND_MODE + write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition + 4 + 1 + read-write + + + TX_FETCH_MODE + write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions + 5 + 1 + read-write + + + TX_HALT_MODE + write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back + 6 + 1 + read-write + + + TX_RD_DUMMY + write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data + 7 + 1 + read-write + + + TX_FIFO_RST + write this bit to reset the bitscrambler tx fifo + 8 + 1 + write-only + + + + + RX_CTRL + Control and configuration registers + 0x2C + 0x20 + 0x00000004 + + + RX_ENA + write this bit to enable the bitscrambler rx + 0 + 1 + read-write + + + RX_PAUSE + write this bit to pause the bitscrambler rx core + 1 + 1 + read-write + + + RX_HALT + write this bit to halt the bitscrambler rx core + 2 + 1 + read-write + + + RX_EOF_MODE + write this bit to ser the bitscrambler rx core EOF signal generating mode which is combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral buffer, 0 counter by write dma fifo + 3 + 1 + read-write + + + RX_COND_MODE + write this bit to specify the LOOP instruction condition mode of bitscrambler rx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition + 4 + 1 + read-write + + + RX_FETCH_MODE + write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions + 5 + 1 + read-write + + + RX_HALT_MODE + write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0: wait write data back done, , 1: ignore write data back + 6 + 1 + read-write + + + RX_RD_DUMMY + write this bit to set the bitscrambler rx core read data mode when EOF received.0: wait read data, 1: ignore read data + 7 + 1 + read-write + + + RX_FIFO_RST + write this bit to reset the bitscrambler rx fifo + 8 + 1 + write-only + + + + + TX_STATE + Status registers + 0x30 + 0x20 + 0x00000001 + + + TX_IN_IDLE + represents the bitscrambler tx core in halt mode + 0 + 1 + read-only + + + TX_IN_RUN + represents the bitscrambler tx core in run mode + 1 + 1 + read-only + + + TX_IN_WAIT + represents the bitscrambler tx core in wait mode to wait write back done + 2 + 1 + read-only + + + TX_IN_PAUSE + represents the bitscrambler tx core in pause mode + 3 + 1 + read-only + + + TX_FIFO_EMPTY + represents the bitscrambler tx fifo in empty state + 4 + 1 + read-only + + + TX_EOF_GET_CNT + represents the bytes numbers of bitscrambler tx core when get EOF + 16 + 14 + read-only + + + TX_EOF_OVERLOAD + represents the some EOFs will be lost for bitscrambler tx core + 30 + 1 + read-only + + + TX_EOF_TRACE_CLR + write this bit to clear reg_bitscrambler_tx_eof_overload and reg_bitscrambler_tx_eof_get_cnt registers + 31 + 1 + write-only + + + + + RX_STATE + Status registers + 0x34 + 0x20 + 0x00000001 + + + RX_IN_IDLE + represents the bitscrambler rx core in halt mode + 0 + 1 + read-only + + + RX_IN_RUN + represents the bitscrambler rx core in run mode + 1 + 1 + read-only + + + RX_IN_WAIT + represents the bitscrambler rx core in wait mode to wait write back done + 2 + 1 + read-only + + + RX_IN_PAUSE + represents the bitscrambler rx core in pause mode + 3 + 1 + read-only + + + RX_FIFO_FULL + represents the bitscrambler rx fifo in full state + 4 + 1 + read-only + + + RX_EOF_GET_CNT + represents the bytes numbers of bitscrambler rx core when get EOF + 16 + 14 + read-only + + + RX_EOF_OVERLOAD + represents the some EOFs will be lost for bitscrambler rx core + 30 + 1 + read-only + + + RX_EOF_TRACE_CLR + write this bit to clear reg_bitscrambler_rx_eof_overload and reg_bitscrambler_rx_eof_get_cnt registers + 31 + 1 + write-only + + + + + SYS + Control and configuration registers + 0xF8 + 0x20 + + + LOOP_MODE + write this bit to set the bitscrambler tx loop back to DMA rx + 0 + 1 + read-write + + + CLK_EN + Reserved + 31 + 1 + read-write + + + + + VERSION + Control and configuration registers + 0xFC + 0x20 + 0x02303240 + + + BITSCRAMBLER_VER + Reserved + 0 + 28 + read-write + + + + + + + CACHE + CACHE Peripheral + CACHE + 0x3FF10000 + + 0x0 + 0x3F0 + registers + + + CACHE + 83 + + + + L1_ICACHE_CTRL + L1 instruction Cache(L1-ICache) control register + 0x0 + 0x20 + + + L1_ICACHE_SHUT_IBUS0 + The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable + 0 + 1 + read-write + + + L1_ICACHE_SHUT_IBUS1 + The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable + 1 + 1 + read-write + + + L1_ICACHE_SHUT_IBUS2 + Reserved + 2 + 1 + read-only + + + L1_ICACHE_SHUT_IBUS3 + Reserved + 3 + 1 + read-only + + + L1_ICACHE_UNDEF_OP + Reserved + 8 + 8 + read-write + + + + + L1_DCACHE_CTRL + L1 data Cache(L1-DCache) control register + 0x4 + 0x20 + + + L1_DCACHE_SHUT_DBUS0 + The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable + 0 + 1 + read-write + + + L1_DCACHE_SHUT_DBUS1 + The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable + 1 + 1 + read-write + + + L1_DCACHE_SHUT_DBUS2 + Reserved + 2 + 1 + read-only + + + L1_DCACHE_SHUT_DBUS3 + Reserved + 3 + 1 + read-only + + + L1_DCACHE_SHUT_DMA + The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable + 4 + 1 + read-write + + + L1_DCACHE_UNDEF_OP + Reserved + 8 + 8 + read-write + + + + + L1_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x8 + 0x20 + + + BYPASS_L1_ICACHE0_EN + The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass. + 0 + 1 + read-write + + + BYPASS_L1_ICACHE1_EN + The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass. + 1 + 1 + read-write + + + BYPASS_L1_ICACHE2_EN + Reserved + 2 + 1 + read-only + + + BYPASS_L1_ICACHE3_EN + Reserved + 3 + 1 + read-only + + + BYPASS_L1_DCACHE_EN + The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass. + 4 + 1 + read-write + + + + + L1_CACHE_ATOMIC_CONF + L1 Cache atomic feature configure register + 0xC + 0x20 + 0x00000001 + + + L1_DCACHE_ATOMIC_EN + The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable. + 0 + 1 + read-write + + + + + L1_ICACHE_CACHESIZE_CONF + L1 instruction Cache CacheSize mode configure register + 0x10 + 0x20 + 0x00000040 + + + L1_ICACHE_CACHESIZE_256 + The field is used to configure cachesize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_ICACHE_CACHESIZE_512 + The field is used to configure cachesize of L1-ICache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_ICACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_ICACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_ICACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_ICACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L1_ICACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L1_ICACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L1_ICACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L1_ICACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L1_ICACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L1_ICACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L1_ICACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L1_ICACHE_BLOCKSIZE_CONF + L1 instruction Cache BlockSize mode configure register + 0x14 + 0x20 + 0x00000008 + + + L1_ICACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_ICACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L1_DCACHE_CACHESIZE_CONF + L1 data Cache CacheSize mode configure register + 0x18 + 0x20 + 0x00000100 + + + L1_DCACHE_CACHESIZE_256 + The field is used to configure cachesize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_DCACHE_CACHESIZE_512 + The field is used to configure cachesize of L1-DCache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_DCACHE_CACHESIZE_1K + The field is used to configure cachesize of L1-DCache as 1k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_DCACHE_CACHESIZE_2K + The field is used to configure cachesize of L1-DCache as 2k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_DCACHE_CACHESIZE_4K + The field is used to configure cachesize of L1-DCache as 4k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_DCACHE_CACHESIZE_8K + The field is used to configure cachesize of L1-DCache as 8k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L1_DCACHE_CACHESIZE_16K + The field is used to configure cachesize of L1-DCache as 16k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L1_DCACHE_CACHESIZE_32K + The field is used to configure cachesize of L1-DCache as 32k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L1_DCACHE_CACHESIZE_64K + The field is used to configure cachesize of L1-DCache as 64k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L1_DCACHE_CACHESIZE_128K + The field is used to configure cachesize of L1-DCache as 128k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-only + + + L1_DCACHE_CACHESIZE_256K + The field is used to configure cachesize of L1-DCache as 256k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-only + + + L1_DCACHE_CACHESIZE_512K + The field is used to configure cachesize of L1-DCache as 512k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-only + + + L1_DCACHE_CACHESIZE_1024K + The field is used to configure cachesize of L1-DCache as 1024k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L1_DCACHE_BLOCKSIZE_CONF + L1 data Cache BlockSize mode configure register + 0x1C + 0x20 + 0x00000008 + + + L1_DCACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L1_DCACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L1_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x20 + 0x20 + + + L1_ICACHE0_WRAP + Set this bit as 1 to enable L1-ICache0 wrap around mode. + 0 + 1 + read-write + + + L1_ICACHE1_WRAP + Set this bit as 1 to enable L1-ICache1 wrap around mode. + 1 + 1 + read-write + + + L1_ICACHE2_WRAP + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_WRAP + Reserved + 3 + 1 + read-only + + + L1_DCACHE_WRAP + Set this bit as 1 to enable L1-DCache wrap around mode. + 4 + 1 + read-write + + + + + L1_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x24 + 0x20 + 0x00055555 + + + L1_ICACHE0_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + L1_ICACHE0_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + L1_ICACHE0_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating. + 4 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_FORCE_PD + The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down + 5 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_FORCE_PU + The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up + 6 + 1 + read-write + + + L1_ICACHE2_TAG_MEM_FORCE_ON + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_PD + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_FORCE_PU + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_ON + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_PD + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_FORCE_PU + Reserved + 14 + 1 + read-only + + + L1_DCACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L1-DCache tag memory. 1: close gating, 0: open clock gating. + 16 + 1 + read-write + + + L1_DCACHE_TAG_MEM_FORCE_PD + The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power down + 17 + 1 + read-write + + + L1_DCACHE_TAG_MEM_FORCE_PU + The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up + 18 + 1 + read-write + + + + + L1_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x28 + 0x20 + 0x00055555 + + + L1_ICACHE0_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating. + 0 + 1 + read-write + + + L1_ICACHE0_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down + 1 + 1 + read-write + + + L1_ICACHE0_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up + 2 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating. + 4 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_FORCE_PD + The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down + 5 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_FORCE_PU + The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up + 6 + 1 + read-write + + + L1_ICACHE2_DATA_MEM_FORCE_ON + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_PD + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_FORCE_PU + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_ON + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_PD + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_FORCE_PU + Reserved + 14 + 1 + read-only + + + L1_DCACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L1-DCache data memory. 1: close gating, 0: open clock gating. + 16 + 1 + read-write + + + L1_DCACHE_DATA_MEM_FORCE_PD + The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power down + 17 + 1 + read-write + + + L1_DCACHE_DATA_MEM_FORCE_PU + The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up + 18 + 1 + read-write + + + + + L1_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x2C + 0x20 + + + L1_ICACHE0_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software. + 0 + 1 + read-write + + + L1_ICACHE0_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 1 + 1 + read-write + + + L1_ICACHE0_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. + 2 + 1 + read-only + + + L1_ICACHE1_FREEZE_EN + The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software. + 4 + 1 + read-write + + + L1_ICACHE1_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 5 + 1 + read-write + + + L1_ICACHE1_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + 6 + 1 + read-only + + + L1_ICACHE2_FREEZE_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_FREEZE_MODE + Reserved + 9 + 1 + read-only + + + L1_ICACHE2_FREEZE_DONE + Reserved + 10 + 1 + read-only + + + L1_ICACHE3_FREEZE_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_FREEZE_MODE + Reserved + 13 + 1 + read-only + + + L1_ICACHE3_FREEZE_DONE + Reserved + 14 + 1 + read-only + + + L1_DCACHE_FREEZE_EN + The bit is used to enable freeze operation on L1-DCache. It can be cleared by software. + 16 + 1 + read-write + + + L1_DCACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 17 + 1 + read-write + + + L1_DCACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L1-DCache is finished or not. 0: not finished. 1: finished. + 18 + 1 + read-only + + + + + L1_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x30 + 0x20 + 0x00033333 + + + L1_ICACHE0_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable. + 0 + 1 + read-write + + + L1_ICACHE0_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable. + 1 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable. + 4 + 1 + read-write + + + L1_ICACHE1_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable. + 5 + 1 + read-write + + + L1_ICACHE2_DATA_MEM_RD_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_DATA_MEM_WR_EN + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_RD_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_DATA_MEM_WR_EN + Reserved + 13 + 1 + read-only + + + L1_DCACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1: enable. + 16 + 1 + read-write + + + L1_DCACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1: enable. + 17 + 1 + read-write + + + + + L1_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x34 + 0x20 + 0x00033333 + + + L1_ICACHE0_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable. + 0 + 1 + read-write + + + L1_ICACHE0_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable. + 1 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable. + 4 + 1 + read-write + + + L1_ICACHE1_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable. + 5 + 1 + read-write + + + L1_ICACHE2_TAG_MEM_RD_EN + Reserved + 8 + 1 + read-only + + + L1_ICACHE2_TAG_MEM_WR_EN + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_RD_EN + Reserved + 12 + 1 + read-only + + + L1_ICACHE3_TAG_MEM_WR_EN + Reserved + 13 + 1 + read-only + + + L1_DCACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1: enable. + 16 + 1 + read-write + + + L1_DCACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1: enable. + 17 + 1 + read-write + + + + + L1_ICACHE0_PRELOCK_CONF + L1 instruction Cache 0 prelock configure register + 0x38 + 0x20 + + + L1_ICACHE0_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE0_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache0. + 1 + 1 + read-write + + + L1_ICACHE0_PRELOCK_RGID + The bit is used to set the gid of l1 icache0 prelock. + 2 + 4 + read-write + + + + + L1_ICACHE0_PRELOCK_SCT0_ADDR + L1 instruction Cache 0 prelock section0 address configure register + 0x3C + 0x20 + + + L1_ICACHE0_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE0_PRELOCK_SCT1_ADDR + L1 instruction Cache 0 prelock section1 address configure register + 0x40 + 0x20 + + + L1_ICACHE0_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE0_PRELOCK_SCT_SIZE + L1 instruction Cache 0 prelock section size configure register + 0x44 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE0_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-write + + + L1_ICACHE0_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write + + + + + L1_ICACHE1_PRELOCK_CONF + L1 instruction Cache 1 prelock configure register + 0x48 + 0x20 + + + L1_ICACHE1_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache1. + 0 + 1 + read-write + + + L1_ICACHE1_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE1_PRELOCK_RGID + The bit is used to set the gid of l1 icache1 prelock. + 2 + 4 + read-write + + + + + L1_ICACHE1_PRELOCK_SCT0_ADDR + L1 instruction Cache 1 prelock section0 address configure register + 0x4C + 0x20 + + + L1_ICACHE1_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE1_PRELOCK_SCT1_ADDR + L1 instruction Cache 1 prelock section1 address configure register + 0x50 + 0x20 + + + L1_ICACHE1_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE1_PRELOCK_SCT_SIZE + L1 instruction Cache 1 prelock section size configure register + 0x54 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE1_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-write + + + L1_ICACHE1_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write + + + + + L1_ICACHE2_PRELOCK_CONF + L1 instruction Cache 2 prelock configure register + 0x58 + 0x20 + + + L1_ICACHE2_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache2. + 0 + 1 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache2. + 1 + 1 + read-only + + + L1_ICACHE2_PRELOCK_RGID + The bit is used to set the gid of l1 icache2 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT0_ADDR + L1 instruction Cache 2 prelock section0 address configure register + 0x5C + 0x20 + + + L1_ICACHE2_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT1_ADDR + L1 instruction Cache 2 prelock section1 address configure register + 0x60 + 0x20 + + + L1_ICACHE2_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOCK_SCT_SIZE + L1 instruction Cache 2 prelock section size configure register + 0x64 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE2_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE2_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_ICACHE3_PRELOCK_CONF + L1 instruction Cache 3 prelock configure register + 0x68 + 0x20 + + + L1_ICACHE3_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-ICache3. + 0 + 1 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-ICache3. + 1 + 1 + read-only + + + L1_ICACHE3_PRELOCK_RGID + The bit is used to set the gid of l1 icache3 prelock. + 2 + 4 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT0_ADDR + L1 instruction Cache 3 prelock section0 address configure register + 0x6C + 0x20 + + + L1_ICACHE3_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT1_ADDR + L1 instruction Cache 3 prelock section1 address configure register + 0x70 + 0x20 + + + L1_ICACHE3_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOCK_SCT_SIZE + L1 instruction Cache 3 prelock section size configure register + 0x74 + 0x20 + 0x3FFF3FFF + + + L1_ICACHE3_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-only + + + L1_ICACHE3_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-only + + + + + L1_DCACHE_PRELOCK_CONF + L1 data Cache prelock configure register + 0x78 + 0x20 + + + L1_DCACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L1-DCache. + 0 + 1 + read-write + + + L1_DCACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L1-DCache. + 1 + 1 + read-write + + + L1_DCACHE_PRELOCK_RGID + The bit is used to set the gid of l1 dcache prelock. + 2 + 4 + read-write + + + + + L1_DCACHE_PRELOCK_SCT0_ADDR + L1 data Cache prelock section0 address configure register + 0x7C + 0x20 + + + L1_DCACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOCK_SCT1_ADDR + L1 data Cache prelock section1 address configure register + 0x80 + 0x20 + + + L1_DCACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOCK_SCT_SIZE + L1 data Cache prelock section size configure register + 0x84 + 0x20 + 0x3FFF3FFF + + + L1_DCACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG + 0 + 14 + read-write + + + L1_DCACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG + 16 + 14 + read-write + + + + + LOCK_CTRL + Lock-class (manual lock) operation control register + 0x88 + 0x20 + 0x00000004 + + + LOCK_ENA + The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) lock operation can be applied on LL1-ICache, L1-DCache and L2-Cache. + 0 + 1 + read-write + + + UNLOCK_ENA + The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. Note that (1) this bit and lock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock operation can be applied on L1-ICache, L1-DCache and L2-Cache. + 1 + 1 + read-write + + + LOCK_DONE + The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished. + 2 + 1 + read-only + + + LOCK_RGID + The bit is used to set the gid of cache lock/unlock. + 3 + 4 + read-write + + + + + LOCK_MAP + Lock (manual lock) map configure register + 0x8C + 0x20 + + + LOCK_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. + 0 + 6 + read-write + + + + + LOCK_ADDR + Lock (manual lock) address configure register + 0x90 + 0x20 + + + LOCK_ADDR + Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG + 0 + 32 + read-write + + + + + LOCK_SIZE + Lock (manual lock) size configure register + 0x94 + 0x20 + + + LOCK_SIZE + Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG + 0 + 16 + read-write + + + + + SYNC_CTRL + Sync-class operation control register + 0x98 + 0x20 + 0x00000001 + + + INVALIDATE_ENA + The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 0 + 1 + read-write + + + CLEAN_ENA + The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 1 + 1 + read-write + + + WRITEBACK_ENA + The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 2 + 1 + read-write + + + WRITEBACK_INVALIDATE_ENA + The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time. + 3 + 1 + read-write + + + SYNC_DONE + The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished. + 4 + 1 + read-only + + + SYNC_RGID + The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate) + 5 + 4 + read-write + + + + + SYNC_MAP + Sync map configure register + 0x9C + 0x20 + 0x0000001F + + + SYNC_MAP + Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache. + 0 + 6 + read-write + + + + + SYNC_ADDR + Sync address configure register + 0xA0 + 0x20 + + + SYNC_ADDR + Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG + 0 + 32 + read-write + + + + + SYNC_SIZE + Sync size configure register + 0xA4 + 0x20 + + + SYNC_SIZE + Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG + 0 + 28 + read-write + + + + + L1_ICACHE0_PRELOAD_CTRL + L1 instruction Cache 0 preload-operation control register + 0xA8 + 0x20 + 0x00000002 + + + L1_ICACHE0_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE0_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE0_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_ICACHE0_PRELOAD_RGID + The bit is used to set the gid of l1 icache0 preload. + 3 + 4 + read-write + + + + + L1_ICACHE0_PRELOAD_ADDR + L1 instruction Cache 0 preload address configure register + 0xAC + 0x20 + + + L1_ICACHE0_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE0_PRELOAD_SIZE + L1 instruction Cache 0 preload size configure register + 0xB0 + 0x20 + + + L1_ICACHE0_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG + 0 + 14 + read-write + + + + + L1_ICACHE1_PRELOAD_CTRL + L1 instruction Cache 1 preload-operation control register + 0xB4 + 0x20 + 0x00000002 + + + L1_ICACHE1_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_ICACHE1_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE1_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_ICACHE1_PRELOAD_RGID + The bit is used to set the gid of l1 icache1 preload. + 3 + 4 + read-write + + + + + L1_ICACHE1_PRELOAD_ADDR + L1 instruction Cache 1 preload address configure register + 0xB8 + 0x20 + + + L1_ICACHE1_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L1_ICACHE1_PRELOAD_SIZE + L1 instruction Cache 1 preload size configure register + 0xBC + 0x20 + + + L1_ICACHE1_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG + 0 + 14 + read-write + + + + + L1_ICACHE2_PRELOAD_CTRL + L1 instruction Cache 2 preload-operation control register + 0xC0 + 0x20 + 0x00000002 + + + L1_ICACHE2_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-only + + + L1_ICACHE2_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE2_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE2_PRELOAD_RGID + The bit is used to set the gid of l1 icache2 preload. + 3 + 4 + read-only + + + + + L1_ICACHE2_PRELOAD_ADDR + L1 instruction Cache 2 preload address configure register + 0xC4 + 0x20 + + + L1_ICACHE2_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE2_PRELOAD_SIZE + L1 instruction Cache 2 preload size configure register + 0xC8 + 0x20 + + + L1_ICACHE2_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_ICACHE3_PRELOAD_CTRL + L1 instruction Cache 3 preload-operation control register + 0xCC + 0x20 + 0x00000002 + + + L1_ICACHE3_PRELOAD_ENA + The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-only + + + L1_ICACHE3_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE3_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-only + + + L1_ICACHE3_PRELOAD_RGID + The bit is used to set the gid of l1 icache3 preload. + 3 + 4 + read-only + + + + + L1_ICACHE3_PRELOAD_ADDR + L1 instruction Cache 3 preload address configure register + 0xD0 + 0x20 + + + L1_ICACHE3_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG + 0 + 32 + read-only + + + + + L1_ICACHE3_PRELOAD_SIZE + L1 instruction Cache 3 preload size configure register + 0xD4 + 0x20 + + + L1_ICACHE3_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG + 0 + 14 + read-only + + + + + L1_DCACHE_PRELOAD_CTRL + L1 data Cache preload-operation control register + 0xD8 + 0x20 + 0x00000002 + + + L1_DCACHE_PRELOAD_ENA + The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L1_DCACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_DCACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L1_DCACHE_PRELOAD_RGID + The bit is used to set the gid of l1 dcache preload. + 3 + 4 + read-write + + + + + L1_DCACHE_PRELOAD_ADDR + L1 data Cache preload address configure register + 0xDC + 0x20 + + + L1_DCACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L1_DCACHE_PRELOAD_SIZE + L1 data Cache preload size configure register + 0xE0 + 0x20 + + + L1_DCACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG + 0 + 14 + read-write + + + + + L1_ICACHE0_AUTOLOAD_CTRL + L1 instruction Cache 0 autoload-operation control register + 0xE4 + 0x20 + 0x00000002 + + + L1_ICACHE0_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable. + 0 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE0_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L1_ICACHE0_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache0. + 8 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache0. + 9 + 1 + read-write + + + L1_ICACHE0_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache0 autoload. + 10 + 4 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 0 autoload section 0 address configure register + 0xE8 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 0 autoload section 0 size configure register + 0xEC + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 0 autoload section 1 address configure register + 0xF0 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 0 autoload section 1 size configure register + 0xF4 + 0x20 + + + L1_ICACHE0_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE1_AUTOLOAD_CTRL + L1 instruction Cache 1 autoload-operation control register + 0xF8 + 0x20 + 0x00000002 + + + L1_ICACHE1_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable. + 0 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE1_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L1_ICACHE1_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache1. + 8 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache1. + 9 + 1 + read-write + + + L1_ICACHE1_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache1 autoload. + 10 + 4 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 1 autoload section 0 address configure register + 0xFC + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 1 autoload section 0 size configure register + 0x100 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 1 autoload section 1 address configure register + 0x104 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 1 autoload section 1 size configure register + 0x108 + 0x20 + + + L1_ICACHE1_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_ICACHE2_AUTOLOAD_CTRL + L1 instruction Cache 2 autoload-operation control register + 0x10C + 0x20 + 0x00000002 + + + L1_ICACHE2_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE2_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache2. + 8 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache2. + 9 + 1 + read-only + + + L1_ICACHE2_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache2 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 2 autoload section 0 address configure register + 0x110 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 2 autoload section 0 size configure register + 0x114 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 2 autoload section 1 address configure register + 0x118 + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 2 autoload section 1 size configure register + 0x11C + 0x20 + + + L1_ICACHE2_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE3_AUTOLOAD_CTRL + L1 instruction Cache 3 autoload-operation control register + 0x120 + 0x20 + 0x00000002 + + + L1_ICACHE3_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, 0: disable. + 0 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending. + 2 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-only + + + L1_ICACHE3_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-ICache3. + 8 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-ICache3. + 9 + 1 + read-only + + + L1_ICACHE3_AUTOLOAD_RGID + The bit is used to set the gid of l1 icache3 autoload. + 10 + 4 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + L1 instruction Cache 3 autoload section 0 address configure register + 0x124 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + L1 instruction Cache 3 autoload section 0 size configure register + 0x128 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + L1 instruction Cache 3 autoload section 1 address configure register + 0x12C + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-only + + + + + L1_ICACHE3_AUTOLOAD_SCT1_SIZE + L1 instruction Cache 3 autoload section 1 size configure register + 0x130 + 0x20 + + + L1_ICACHE3_AUTOLOAD_SCT1_SIZE + Reserved + 0 + 28 + read-only + + + + + L1_DCACHE_AUTOLOAD_CTRL + L1 data Cache autoload-operation control register + 0x134 + 0x20 + 0x00000002 + + + L1_DCACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L1-DCache. 1: enable, 0: disable. + 0 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L1-DCache is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L1_DCACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L1-DCache. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L1-DCache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L1_DCACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L1-DCache. + 8 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L1-DCache. + 9 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L1-DCache. + 10 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L1-DCache. + 11 + 1 + read-write + + + L1_DCACHE_AUTOLOAD_RGID + The bit is used to set the gid of l1 dcache autoload. + 12 + 4 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT0_ADDR + L1 data Cache autoload section 0 address configure register + 0x138 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT0_SIZE + L1 data Cache autoload section 0 size configure register + 0x13C + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT1_ADDR + L1 data Cache autoload section 1 address configure register + 0x140 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT1_SIZE + L1 data Cache autoload section 1 size configure register + 0x144 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT2_ADDR + L1 data Cache autoload section 2 address configure register + 0x148 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT2_SIZE + L1 data Cache autoload section 2 size configure register + 0x14C + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA. + 0 + 28 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT3_ADDR + L1 data Cache autoload section 1 address configure register + 0x150 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA. + 0 + 32 + read-write + + + + + L1_DCACHE_AUTOLOAD_SCT3_SIZE + L1 data Cache autoload section 1 size configure register + 0x154 + 0x20 + + + L1_DCACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA. + 0 + 28 + read-write + + + + + L1_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x158 + 0x20 + + + L1_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-write + + + L1_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-write + + + L1_IBUS2_OVF_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_DBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-write + + + L1_DBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_OVF_INT_ENA + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_ENA + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x15C + 0x20 + + + L1_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + write-only + + + L1_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + write-only + + + L1_IBUS2_OVF_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_DBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + write-only + + + L1_DBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + write-only + + + L1_DBUS2_OVF_INT_CLR + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_CLR + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x160 + 0x20 + + + L1_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-write + + + L1_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-write + + + L1_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2. + 2 + 1 + read-write + + + L1_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3. + 3 + 1 + read-write + + + L1_DBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-write + + + L1_DBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache. + 6 + 1 + read-write + + + L1_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache. + 7 + 1 + read-write + + + + + L1_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x164 + 0x20 + + + L1_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + 0 + 1 + read-only + + + L1_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + 1 + 1 + read-only + + + L1_IBUS2_OVF_INT_ST + Reserved + 2 + 1 + read-only + + + L1_IBUS3_OVF_INT_ST + Reserved + 3 + 1 + read-only + + + L1_DBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + 4 + 1 + read-only + + + L1_DBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + 5 + 1 + read-only + + + L1_DBUS2_OVF_INT_ST + Reserved + 6 + 1 + read-only + + + L1_DBUS3_OVF_INT_ST + Reserved + 7 + 1 + read-only + + + + + L1_CACHE_ACS_FAIL_CTRL + Cache Access Fail Configuration register + 0x168 + 0x20 + + + L1_ICACHE0_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache0 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 0 + 1 + read-write + + + L1_ICACHE1_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache1 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 1 + 1 + read-write + + + L1_ICACHE2_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache2 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 2 + 1 + read-write + + + L1_ICACHE3_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 icache3 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 3 + 1 + read-write + + + L1_DCACHE_ACS_FAIL_CHECK_MODE + The bit is used to configure l1 dcache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x16C + 0x20 + + + L1_ICACHE0_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE1_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE2_FAIL_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_DCACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x170 + 0x20 + + + L1_ICACHE0_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + 0 + 1 + write-only + + + L1_ICACHE1_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + 1 + 1 + write-only + + + L1_ICACHE2_FAIL_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + write-only + + + + + L1_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x174 + 0x20 + + + L1_ICACHE0_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE1_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE2_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache2. + 2 + 1 + read-write + + + L1_ICACHE3_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-ICache3. + 3 + 1 + read-write + + + L1_DCACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L1-DCache. + 4 + 1 + read-write + + + + + L1_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x178 + 0x20 + + + L1_ICACHE0_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache. + 0 + 1 + read-only + + + L1_ICACHE1_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache. + 1 + 1 + read-only + + + L1_ICACHE2_FAIL_INT_ST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_FAIL_INT_ST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + 4 + 1 + read-only + + + + + L1_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x17C + 0x20 + + + L1_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L1-ICache0. + 0 + 1 + read-write + + + L1_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L1-ICache1. + 1 + 1 + read-write + + + L1_IBUS2_CNT_ENA + Reserved + 2 + 1 + read-only + + + L1_IBUS3_CNT_ENA + Reserved + 3 + 1 + read-only + + + L1_DBUS0_CNT_ENA + The bit is used to enable dbus0 counter in L1-DCache. + 4 + 1 + read-write + + + L1_DBUS1_CNT_ENA + The bit is used to enable dbus1 counter in L1-DCache. + 5 + 1 + read-write + + + L1_DBUS2_CNT_ENA + Reserved + 6 + 1 + read-only + + + L1_DBUS3_CNT_ENA + Reserved + 7 + 1 + read-only + + + L1_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L1-ICache0. + 16 + 1 + write-only + + + L1_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L1-ICache1. + 17 + 1 + write-only + + + L1_IBUS2_CNT_CLR + Reserved + 18 + 1 + read-only + + + L1_IBUS3_CNT_CLR + Reserved + 19 + 1 + read-only + + + L1_DBUS0_CNT_CLR + The bit is used to clear dbus0 counter in L1-DCache. + 20 + 1 + write-only + + + L1_DBUS1_CNT_CLR + The bit is used to clear dbus1 counter in L1-DCache. + 21 + 1 + write-only + + + L1_DBUS2_CNT_CLR + Reserved + 22 + 1 + read-only + + + L1_DBUS3_CNT_CLR + Reserved + 23 + 1 + read-only + + + + + L1_IBUS0_ACS_HIT_CNT + L1-ICache bus0 Hit-Access Counter register + 0x180 + 0x20 + + + L1_IBUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_MISS_CNT + L1-ICache bus0 Miss-Access Counter register + 0x184 + 0x20 + + + L1_IBUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_CONFLICT_CNT + L1-ICache bus0 Conflict-Access Counter register + 0x188 + 0x20 + + + L1_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS0_ACS_NXTLVL_RD_CNT + L1-ICache bus0 Next-Level-Access Counter register + 0x18C + 0x20 + + + L1_IBUS0_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_HIT_CNT + L1-ICache bus1 Hit-Access Counter register + 0x190 + 0x20 + + + L1_IBUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_MISS_CNT + L1-ICache bus1 Miss-Access Counter register + 0x194 + 0x20 + + + L1_IBUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_CONFLICT_CNT + L1-ICache bus1 Conflict-Access Counter register + 0x198 + 0x20 + + + L1_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS1_ACS_NXTLVL_RD_CNT + L1-ICache bus1 Next-Level-Access Counter register + 0x19C + 0x20 + + + L1_IBUS1_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_HIT_CNT + L1-ICache bus2 Hit-Access Counter register + 0x1A0 + 0x20 + + + L1_IBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_MISS_CNT + L1-ICache bus2 Miss-Access Counter register + 0x1A4 + 0x20 + + + L1_IBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_CONFLICT_CNT + L1-ICache bus2 Conflict-Access Counter register + 0x1A8 + 0x20 + + + L1_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS2_ACS_NXTLVL_RD_CNT + L1-ICache bus2 Next-Level-Access Counter register + 0x1AC + 0x20 + + + L1_IBUS2_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_HIT_CNT + L1-ICache bus3 Hit-Access Counter register + 0x1B0 + 0x20 + + + L1_IBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_MISS_CNT + L1-ICache bus3 Miss-Access Counter register + 0x1B4 + 0x20 + + + L1_IBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_CONFLICT_CNT + L1-ICache bus3 Conflict-Access Counter register + 0x1B8 + 0x20 + + + L1_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-ICache3. + 0 + 32 + read-only + + + + + L1_IBUS3_ACS_NXTLVL_RD_CNT + L1-ICache bus3 Next-Level-Access Counter register + 0x1BC + 0x20 + + + L1_IBUS3_NXTLVL_RD_CNT + The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_HIT_CNT + L1-DCache bus0 Hit-Access Counter register + 0x1C0 + 0x20 + + + L1_DBUS0_HIT_CNT + The register records the number of hits when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_MISS_CNT + L1-DCache bus0 Miss-Access Counter register + 0x1C4 + 0x20 + + + L1_DBUS0_MISS_CNT + The register records the number of missing when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_CONFLICT_CNT + L1-DCache bus0 Conflict-Access Counter register + 0x1C8 + 0x20 + + + L1_DBUS0_CONFLICT_CNT + The register records the number of access-conflicts when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_NXTLVL_RD_CNT + L1-DCache bus0 Next-Level-Access Counter register + 0x1CC + 0x20 + + + L1_DBUS0_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS0_ACS_NXTLVL_WR_CNT + L1-DCache bus0 WB-Access Counter register + 0x1D0 + 0x20 + + + L1_DBUS0_NXTLVL_WR_CNT + The register records the number of write back when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_HIT_CNT + L1-DCache bus1 Hit-Access Counter register + 0x1D4 + 0x20 + + + L1_DBUS1_HIT_CNT + The register records the number of hits when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_MISS_CNT + L1-DCache bus1 Miss-Access Counter register + 0x1D8 + 0x20 + + + L1_DBUS1_MISS_CNT + The register records the number of missing when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_CONFLICT_CNT + L1-DCache bus1 Conflict-Access Counter register + 0x1DC + 0x20 + + + L1_DBUS1_CONFLICT_CNT + The register records the number of access-conflicts when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_NXTLVL_RD_CNT + L1-DCache bus1 Next-Level-Access Counter register + 0x1E0 + 0x20 + + + L1_DBUS1_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS1_ACS_NXTLVL_WR_CNT + L1-DCache bus1 WB-Access Counter register + 0x1E4 + 0x20 + + + L1_DBUS1_NXTLVL_WR_CNT + The register records the number of write back when bus1 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_HIT_CNT + L1-DCache bus2 Hit-Access Counter register + 0x1E8 + 0x20 + + + L1_DBUS2_HIT_CNT + The register records the number of hits when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_MISS_CNT + L1-DCache bus2 Miss-Access Counter register + 0x1EC + 0x20 + + + L1_DBUS2_MISS_CNT + The register records the number of missing when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_CONFLICT_CNT + L1-DCache bus2 Conflict-Access Counter register + 0x1F0 + 0x20 + + + L1_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_NXTLVL_RD_CNT + L1-DCache bus2 Next-Level-Access Counter register + 0x1F4 + 0x20 + + + L1_DBUS2_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS2_ACS_NXTLVL_WR_CNT + L1-DCache bus2 WB-Access Counter register + 0x1F8 + 0x20 + + + L1_DBUS2_NXTLVL_WR_CNT + The register records the number of write back when bus2 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_HIT_CNT + L1-DCache bus3 Hit-Access Counter register + 0x1FC + 0x20 + + + L1_DBUS3_HIT_CNT + The register records the number of hits when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_MISS_CNT + L1-DCache bus3 Miss-Access Counter register + 0x200 + 0x20 + + + L1_DBUS3_MISS_CNT + The register records the number of missing when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_CONFLICT_CNT + L1-DCache bus3 Conflict-Access Counter register + 0x204 + 0x20 + + + L1_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when bus3 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_NXTLVL_RD_CNT + L1-DCache bus3 Next-Level-Access Counter register + 0x208 + 0x20 + + + L1_DBUS3_NXTLVL_RD_CNT + The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L1_DBUS3_ACS_NXTLVL_WR_CNT + L1-DCache bus3 WB-Access Counter register + 0x20C + 0x20 + + + L1_DBUS3_NXTLVL_WR_CNT + The register records the number of write back when bus0 accesses L1-DCache. + 0 + 32 + read-only + + + + + L1_ICACHE0_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x210 + 0x20 + + + L1_ICACHE0_FAIL_ID + The register records the ID of fail-access when cache0 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE0_FAIL_ATTR + The register records the attribution of fail-access when cache0 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE0_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x214 + 0x20 + + + L1_ICACHE0_FAIL_ADDR + The register records the address of fail-access when cache0 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE1_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x218 + 0x20 + + + L1_ICACHE1_FAIL_ID + The register records the ID of fail-access when cache1 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE1_FAIL_ATTR + The register records the attribution of fail-access when cache1 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE1_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x21C + 0x20 + + + L1_ICACHE1_FAIL_ADDR + The register records the address of fail-access when cache1 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE2_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x220 + 0x20 + + + L1_ICACHE2_FAIL_ID + The register records the ID of fail-access when cache2 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE2_FAIL_ATTR + The register records the attribution of fail-access when cache2 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE2_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x224 + 0x20 + + + L1_ICACHE2_FAIL_ADDR + The register records the address of fail-access when cache2 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_ICACHE3_ACS_FAIL_ID_ATTR + L1-ICache0 Access Fail ID/attribution information register + 0x228 + 0x20 + + + L1_ICACHE3_FAIL_ID + The register records the ID of fail-access when cache3 accesses L1-ICache. + 0 + 16 + read-only + + + L1_ICACHE3_FAIL_ATTR + The register records the attribution of fail-access when cache3 accesses L1-ICache. + 16 + 16 + read-only + + + + + L1_ICACHE3_ACS_FAIL_ADDR + L1-ICache0 Access Fail Address information register + 0x22C + 0x20 + + + L1_ICACHE3_FAIL_ADDR + The register records the address of fail-access when cache3 accesses L1-ICache. + 0 + 32 + read-only + + + + + L1_DCACHE_ACS_FAIL_ID_ATTR + L1-DCache Access Fail ID/attribution information register + 0x230 + 0x20 + + + L1_DCACHE_FAIL_ID + The register records the ID of fail-access when cache accesses L1-DCache. + 0 + 16 + read-only + + + L1_DCACHE_FAIL_ATTR + The register records the attribution of fail-access when cache accesses L1-DCache. + 16 + 16 + read-only + + + + + L1_DCACHE_ACS_FAIL_ADDR + L1-DCache Access Fail Address information register + 0x234 + 0x20 + + + L1_DCACHE_FAIL_ADDR + The register records the address of fail-access when cache accesses L1-DCache. + 0 + 32 + read-only + + + + + SYNC_L1_CACHE_PRELOAD_INT_ENA + L1-Cache Access Fail Interrupt enable register + 0x238 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs. + 0 + 1 + read-write + + + L1_ICACHE1_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs. + 1 + 1 + read-write + + + L1_ICACHE2_PLD_DONE_INT_ENA + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_ENA + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L1-DCache preload-operation. If preload operation is done, interrupt occurs. + 4 + 1 + read-write + + + SYNC_DONE_INT_ENA + The bit is used to enable interrupt of Cache sync-operation done. + 6 + 1 + read-write + + + L1_ICACHE0_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-write + + + L1_ICACHE1_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-write + + + L1_ICACHE2_PLD_ERR_INT_ENA + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_ENA + Reserved + 10 + 1 + read-only + + + L1_DCACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L1-DCache preload-operation error. + 11 + 1 + read-write + + + SYNC_ERR_INT_ENA + The bit is used to enable interrupt of Cache sync-operation error. + 13 + 1 + read-write + + + + + SYNC_L1_CACHE_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x23C + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + write-only + + + L1_ICACHE1_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + write-only + + + L1_ICACHE2_PLD_DONE_INT_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L1-DCache preload-operation is done. + 4 + 1 + write-only + + + SYNC_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + write-only + + + L1_ICACHE0_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache0 preload-operation error. + 7 + 1 + write-only + + + L1_ICACHE1_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-ICache1 preload-operation error. + 8 + 1 + write-only + + + L1_ICACHE2_PLD_ERR_INT_CLR + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_CLR + Reserved + 10 + 1 + read-only + + + L1_DCACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L1-DCache preload-operation error. + 11 + 1 + write-only + + + SYNC_ERR_INT_CLR + The bit is used to clear interrupt of Cache sync-operation error. + 13 + 1 + write-only + + + + + SYNC_L1_CACHE_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x240 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-write + + + L1_ICACHE1_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-write + + + L1_ICACHE2_PLD_DONE_INT_RAW + Reserved + 2 + 1 + read-write + + + L1_ICACHE3_PLD_DONE_INT_RAW + Reserved + 3 + 1 + read-write + + + L1_DCACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L1-DCache preload-operation is done. + 4 + 1 + read-write + + + SYNC_DONE_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + read-write + + + L1_ICACHE0_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs. + 7 + 1 + read-write + + + L1_ICACHE1_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs. + 8 + 1 + read-write + + + L1_ICACHE2_PLD_ERR_INT_RAW + Reserved + 9 + 1 + read-write + + + L1_ICACHE3_PLD_ERR_INT_RAW + Reserved + 10 + 1 + read-write + + + L1_DCACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L1-DCache preload-operation error occurs. + 11 + 1 + read-write + + + SYNC_ERR_INT_RAW + The raw bit of the interrupt that occurs only when Cache sync-operation error occurs. + 13 + 1 + read-write + + + + + SYNC_L1_CACHE_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x244 + 0x20 + + + L1_ICACHE0_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done. + 0 + 1 + read-only + + + L1_ICACHE1_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done. + 1 + 1 + read-only + + + L1_ICACHE2_PLD_DONE_INT_ST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_DONE_INT_ST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L1-DCache preload-operation is done. + 4 + 1 + read-only + + + SYNC_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done. + 6 + 1 + read-only + + + L1_ICACHE0_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + 7 + 1 + read-only + + + L1_ICACHE1_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + 8 + 1 + read-only + + + L1_ICACHE2_PLD_ERR_INT_ST + Reserved + 9 + 1 + read-only + + + L1_ICACHE3_PLD_ERR_INT_ST + Reserved + 10 + 1 + read-only + + + L1_DCACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L1-DCache preload-operation error. + 11 + 1 + read-only + + + SYNC_ERR_INT_ST + The bit indicates the status of the interrupt of Cache sync-operation error. + 13 + 1 + read-only + + + + + SYNC_L1_CACHE_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x248 + 0x20 + + + L1_ICACHE0_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache0. + 0 + 2 + read-only + + + L1_ICACHE1_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-ICache1. + 2 + 2 + read-only + + + L1_ICACHE2_PLD_ERR_CODE + Reserved + 4 + 2 + read-only + + + L1_ICACHE3_PLD_ERR_CODE + Reserved + 6 + 2 + read-only + + + L1_DCACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L1-DCache. + 8 + 2 + read-only + + + SYNC_ERR_CODE + The values 0-2 are available which means sync map, command conflict and size are error in Cache System. + 12 + 2 + read-only + + + + + L1_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x24C + 0x20 + + + L1_ICACHE0_SYNC_RST + set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 0 + 1 + read-write + + + L1_ICACHE1_SYNC_RST + set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 1 + 1 + read-write + + + L1_ICACHE2_SYNC_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_SYNC_RST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_SYNC_RST + set this bit to reset sync-logic inside L1-DCache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 4 + 1 + read-write + + + + + L1_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x250 + 0x20 + + + L1_ICACHE0_PLD_RST + set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 0 + 1 + read-write + + + L1_ICACHE1_PLD_RST + set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 1 + 1 + read-write + + + L1_ICACHE2_PLD_RST + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_PLD_RST + Reserved + 3 + 1 + read-only + + + L1_DCACHE_PLD_RST + set this bit to reset preload-logic inside L1-DCache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 4 + 1 + read-write + + + + + L1_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x254 + 0x20 + + + L1_ICACHE0_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0. + 0 + 1 + read-write + + + L1_ICACHE1_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1. + 1 + 1 + read-write + + + L1_ICACHE2_ALD_BUF_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_ALD_BUF_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L1-DCache. If this bit is active, autoload will not work in L1-DCache. This bit should not be active when autoload works in L1-DCache. + 4 + 1 + read-write + + + + + L1_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x258 + 0x20 + + + L1_ICACHE0_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed. + 0 + 1 + read-write + + + L1_ICACHE1_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed. + 1 + 1 + read-write + + + L1_ICACHE2_UNALLOC_CLR + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_UNALLOC_CLR + Reserved + 3 + 1 + read-only + + + L1_DCACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l1 dcache where the unallocate request is responsed but not completed. + 4 + 1 + read-write + + + + + L1_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x25C + 0x20 + + + L1_ICACHE0_TAG_OBJECT + Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register. + 0 + 1 + read-write + + + L1_ICACHE1_TAG_OBJECT + Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register. + 1 + 1 + read-write + + + L1_ICACHE2_TAG_OBJECT + Reserved + 2 + 1 + read-only + + + L1_ICACHE3_TAG_OBJECT + Reserved + 3 + 1 + read-only + + + L1_DCACHE_TAG_OBJECT + Set this bit to set L1-DCache tag memory as object. This bit should be onehot with the others fields inside this register. + 4 + 1 + read-write + + + L1_ICACHE0_MEM_OBJECT + Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register. + 6 + 1 + read-write + + + L1_ICACHE1_MEM_OBJECT + Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register. + 7 + 1 + read-write + + + L1_ICACHE2_MEM_OBJECT + Reserved + 8 + 1 + read-only + + + L1_ICACHE3_MEM_OBJECT + Reserved + 9 + 1 + read-only + + + L1_DCACHE_MEM_OBJECT + Set this bit to set L1-DCache data memory as object. This bit should be onehot with the others fields inside this register. + 10 + 1 + read-write + + + + + L1_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x260 + 0x20 + + + L1_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. + 0 + 3 + read-write + + + + + L1_CACHE_VADDR + Cache Vaddr register + 0x264 + 0x20 + 0x40000000 + + + L1_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-write + + + + + L1_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x268 + 0x20 + 0x00000268 + + + L1_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + 0 + 32 + read-write + + + + + LEVEL_SPLIT0 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x26C + 0x20 + 0x0000026C + + + LEVEL_SPLIT0 + Reserved + 0 + 32 + read-only + + + + + L2_CACHE_CTRL + L2 Cache(L2-Cache) control register + 0x270 + 0x20 + 0x00000010 + + + L2_CACHE_SHUT_DMA + The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable + 4 + 1 + read-write + + + L2_CACHE_UNDEF_OP + Reserved + 8 + 8 + read-write + + + + + L2_BYPASS_CACHE_CONF + Bypass Cache configure register + 0x274 + 0x20 + + + BYPASS_L2_CACHE_EN + The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass. + 5 + 1 + read-write + + + + + L2_CACHE_CACHESIZE_CONF + L2 Cache CacheSize mode configure register + 0x278 + 0x20 + 0x00000400 + + + L2_CACHE_CACHESIZE_256 + The field is used to configure cachesize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L2_CACHE_CACHESIZE_512 + The field is used to configure cachesize of L2-Cache as 512 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_CACHESIZE_1K + The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_CACHESIZE_2K + The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-only + + + L2_CACHE_CACHESIZE_4K + The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-only + + + L2_CACHE_CACHESIZE_8K + The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + L2_CACHE_CACHESIZE_16K + The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot. + 6 + 1 + read-only + + + L2_CACHE_CACHESIZE_32K + The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot. + 7 + 1 + read-only + + + L2_CACHE_CACHESIZE_64K + The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot. + 8 + 1 + read-only + + + L2_CACHE_CACHESIZE_128K + The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot. + 9 + 1 + read-write + + + L2_CACHE_CACHESIZE_256K + The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot. + 10 + 1 + read-write + + + L2_CACHE_CACHESIZE_512K + The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot. + 11 + 1 + read-write + + + L2_CACHE_CACHESIZE_1024K + The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot. + 12 + 1 + read-only + + + + + L2_CACHE_BLOCKSIZE_CONF + L2 Cache BlockSize mode configure register + 0x27C + 0x20 + 0x00000008 + + + L2_CACHE_BLOCKSIZE_8 + The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot. + 0 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_16 + The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot. + 1 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_32 + The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot. + 2 + 1 + read-only + + + L2_CACHE_BLOCKSIZE_64 + The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot. + 3 + 1 + read-write + + + L2_CACHE_BLOCKSIZE_128 + The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot. + 4 + 1 + read-write + + + L2_CACHE_BLOCKSIZE_256 + The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + 5 + 1 + read-only + + + + + L2_CACHE_WRAP_AROUND_CTRL + Cache wrap around control register + 0x280 + 0x20 + + + L2_CACHE_WRAP + Set this bit as 1 to enable L2-Cache wrap around mode. + 5 + 1 + read-write + + + + + L2_CACHE_TAG_MEM_POWER_CTRL + Cache tag memory power control register + 0x284 + 0x20 + 0x00500000 + + + L2_CACHE_TAG_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-write + + + L2_CACHE_TAG_MEM_FORCE_PD + The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-write + + + L2_CACHE_TAG_MEM_FORCE_PU + The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 + read-write + + + + + L2_CACHE_DATA_MEM_POWER_CTRL + Cache data memory power control register + 0x288 + 0x20 + 0x00500000 + + + L2_CACHE_DATA_MEM_FORCE_ON + The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating. + 20 + 1 + read-write + + + L2_CACHE_DATA_MEM_FORCE_PD + The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down + 21 + 1 + read-write + + + L2_CACHE_DATA_MEM_FORCE_PU + The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up + 22 + 1 + read-write + + + + + L2_CACHE_FREEZE_CTRL + Cache Freeze control register + 0x28C + 0x20 + + + L2_CACHE_FREEZE_EN + The bit is used to enable freeze operation on L2-Cache. It can be cleared by software. + 20 + 1 + read-write + + + L2_CACHE_FREEZE_MODE + The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck. + 21 + 1 + read-write + + + L2_CACHE_FREEZE_DONE + The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 22 + 1 + read-only + + + + + L2_CACHE_DATA_MEM_ACS_CONF + Cache data memory access configure register + 0x290 + 0x20 + 0x00300000 + + + L2_CACHE_DATA_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable. + 20 + 1 + read-write + + + L2_CACHE_DATA_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable. + 21 + 1 + read-write + + + + + L2_CACHE_TAG_MEM_ACS_CONF + Cache tag memory access configure register + 0x294 + 0x20 + 0x00300000 + + + L2_CACHE_TAG_MEM_RD_EN + The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable. + 20 + 1 + read-write + + + L2_CACHE_TAG_MEM_WR_EN + The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable. + 21 + 1 + read-write + + + + + L2_CACHE_PRELOCK_CONF + L2 Cache prelock configure register + 0x298 + 0x20 + + + L2_CACHE_PRELOCK_SCT0_EN + The bit is used to enable the first section of prelock function on L2-Cache. + 0 + 1 + read-write + + + L2_CACHE_PRELOCK_SCT1_EN + The bit is used to enable the second section of prelock function on L2-Cache. + 1 + 1 + read-write + + + L2_CACHE_PRELOCK_RGID + The bit is used to set the gid of l2 cache prelock. + 2 + 4 + read-write + + + + + L2_CACHE_PRELOCK_SCT0_ADDR + L2 Cache prelock section0 address configure register + 0x29C + 0x20 + + + L2_CACHE_PRELOCK_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG + 0 + 32 + read-write + + + + + L2_CACHE_PRELOCK_SCT1_ADDR + L2 Cache prelock section1 address configure register + 0x2A0 + 0x20 + + + L2_CACHE_PRELOCK_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG + 0 + 32 + read-write + + + + + L2_CACHE_PRELOCK_SCT_SIZE + L2 Cache prelock section size configure register + 0x2A4 + 0x20 + 0xFFFFFFFF + + + L2_CACHE_PRELOCK_SCT0_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG + 0 + 16 + read-write + + + L2_CACHE_PRELOCK_SCT1_SIZE + Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG + 16 + 16 + read-write + + + + + L2_CACHE_PRELOAD_CTRL + L2 Cache preload-operation control register + 0x2A8 + 0x20 + 0x00000002 + + + L2_CACHE_PRELOAD_ENA + The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done. + 0 + 1 + read-write + + + L2_CACHE_PRELOAD_DONE + The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_PRELOAD_ORDER + The bit is used to configure the direction of preload operation. 0: ascending, 1: descending. + 2 + 1 + read-write + + + L2_CACHE_PRELOAD_RGID + The bit is used to set the gid of l2 cache preload. + 3 + 4 + read-write + + + + + L2_CACHE_PRELOAD_ADDR + L2 Cache preload address configure register + 0x2AC + 0x20 + + + L2_CACHE_PRELOAD_ADDR + Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG + 0 + 32 + read-write + + + + + L2_CACHE_PRELOAD_SIZE + L2 Cache preload size configure register + 0x2B0 + 0x20 + + + L2_CACHE_PRELOAD_SIZE + Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG + 0 + 16 + read-write + + + + + L2_CACHE_AUTOLOAD_CTRL + L2 Cache autoload-operation control register + 0x2B4 + 0x20 + 0x00000002 + + + L2_CACHE_AUTOLOAD_ENA + The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable. + 0 + 1 + read-write + + + L2_CACHE_AUTOLOAD_DONE + The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished. + 1 + 1 + read-only + + + L2_CACHE_AUTOLOAD_ORDER + The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending. + 2 + 1 + read-write + + + L2_CACHE_AUTOLOAD_TRIGGER_MODE + The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger. + 3 + 2 + read-write + + + L2_CACHE_AUTOLOAD_SCT0_ENA + The bit is used to enable the first section for autoload operation on L2-Cache. + 8 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT1_ENA + The bit is used to enable the second section for autoload operation on L2-Cache. + 9 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT2_ENA + The bit is used to enable the third section for autoload operation on L2-Cache. + 10 + 1 + read-write + + + L2_CACHE_AUTOLOAD_SCT3_ENA + The bit is used to enable the fourth section for autoload operation on L2-Cache. + 11 + 1 + read-write + + + L2_CACHE_AUTOLOAD_RGID + The bit is used to set the gid of l2 cache autoload. + 12 + 4 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT0_ADDR + L2 Cache autoload section 0 address configure register + 0x2B8 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT0_ADDR + Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT0_SIZE + L2 Cache autoload section 0 size configure register + 0x2BC + 0x20 + + + L2_CACHE_AUTOLOAD_SCT0_SIZE + Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT1_ADDR + L2 Cache autoload section 1 address configure register + 0x2C0 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT1_ADDR + Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT1_SIZE + L2 Cache autoload section 1 size configure register + 0x2C4 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT1_SIZE + Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT2_ADDR + L2 Cache autoload section 2 address configure register + 0x2C8 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT2_ADDR + Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT2_SIZE + L2 Cache autoload section 2 size configure register + 0x2CC + 0x20 + + + L2_CACHE_AUTOLOAD_SCT2_SIZE + Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT3_ADDR + L2 Cache autoload section 3 address configure register + 0x2D0 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT3_ADDR + Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 32 + read-write + + + + + L2_CACHE_AUTOLOAD_SCT3_SIZE + L2 Cache autoload section 3 size configure register + 0x2D4 + 0x20 + + + L2_CACHE_AUTOLOAD_SCT3_SIZE + Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + 0 + 28 + read-write + + + + + L2_CACHE_ACS_CNT_INT_ENA + Cache Access Counter Interrupt enable register + 0x2D8 + 0x20 + + + L2_IBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-write + + + L2_IBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-write + + + L2_IBUS2_OVF_INT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-write + + + L2_DBUS1_OVF_INT_ENA + The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-write + + + L2_DBUS2_OVF_INT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ENA + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_INT_CLR + Cache Access Counter Interrupt clear register + 0x2DC + 0x20 + + + L2_IBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + write-only + + + L2_IBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + write-only + + + L2_IBUS2_OVF_INT_CLR + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_CLR + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + write-only + + + L2_DBUS1_OVF_INT_CLR + The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + write-only + + + L2_DBUS2_OVF_INT_CLR + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_CLR + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_INT_RAW + Cache Access Counter Interrupt raw register + 0x2E0 + 0x20 + + + L2_IBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0. + 8 + 1 + read-write + + + L2_IBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1. + 9 + 1 + read-write + + + L2_IBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2. + 10 + 1 + read-write + + + L2_IBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3. + 11 + 1 + read-write + + + L2_DBUS0_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache. + 12 + 1 + read-write + + + L2_DBUS1_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache. + 13 + 1 + read-write + + + L2_DBUS2_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache. + 14 + 1 + read-write + + + L2_DBUS3_OVF_INT_RAW + The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache. + 15 + 1 + read-write + + + + + L2_CACHE_ACS_CNT_INT_ST + Cache Access Counter Interrupt status register + 0x2E4 + 0x20 + + + L2_IBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 8 + 1 + read-only + + + L2_IBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 9 + 1 + read-only + + + L2_IBUS2_OVF_INT_ST + Reserved + 10 + 1 + read-only + + + L2_IBUS3_OVF_INT_ST + Reserved + 11 + 1 + read-only + + + L2_DBUS0_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + 12 + 1 + read-only + + + L2_DBUS1_OVF_INT_ST + The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + 13 + 1 + read-only + + + L2_DBUS2_OVF_INT_ST + Reserved + 14 + 1 + read-only + + + L2_DBUS3_OVF_INT_ST + Reserved + 15 + 1 + read-only + + + + + L2_CACHE_ACS_FAIL_CTRL + Cache Access Fail Configuration register + 0x2E8 + 0x20 + + + L2_CACHE_ACS_FAIL_CHECK_MODE + The bit is used to configure l2 cache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request + 0 + 1 + read-write + + + + + L2_CACHE_ACS_FAIL_INT_ENA + Cache Access Fail Interrupt enable register + 0x2EC + 0x20 + + + L2_CACHE_FAIL_INT_ENA + The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-write + + + + + L2_CACHE_ACS_FAIL_INT_CLR + L1-Cache Access Fail Interrupt clear register + 0x2F0 + 0x20 + + + L2_CACHE_FAIL_INT_CLR + The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + write-only + + + + + L2_CACHE_ACS_FAIL_INT_RAW + Cache Access Fail Interrupt raw register + 0x2F4 + 0x20 + + + L2_CACHE_FAIL_INT_RAW + The raw bit of the interrupt of access fail that occurs in L2-Cache. + 5 + 1 + read-write + + + + + L2_CACHE_ACS_FAIL_INT_ST + Cache Access Fail Interrupt status register + 0x2F8 + 0x20 + + + L2_CACHE_FAIL_INT_ST + The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + 5 + 1 + read-only + + + + + L2_CACHE_ACS_CNT_CTRL + Cache Access Counter enable and clear register + 0x2FC + 0x20 + + + L2_IBUS0_CNT_ENA + The bit is used to enable ibus0 counter in L2-Cache. + 8 + 1 + read-write + + + L2_IBUS1_CNT_ENA + The bit is used to enable ibus1 counter in L2-Cache. + 9 + 1 + read-write + + + L2_IBUS2_CNT_ENA + Reserved + 10 + 1 + read-only + + + L2_IBUS3_CNT_ENA + Reserved + 11 + 1 + read-only + + + L2_DBUS0_CNT_ENA + The bit is used to enable dbus0 counter in L2-Cache. + 12 + 1 + read-write + + + L2_DBUS1_CNT_ENA + The bit is used to enable dbus1 counter in L2-Cache. + 13 + 1 + read-write + + + L2_DBUS2_CNT_ENA + Reserved + 14 + 1 + read-only + + + L2_DBUS3_CNT_ENA + Reserved + 15 + 1 + read-only + + + L2_IBUS0_CNT_CLR + The bit is used to clear ibus0 counter in L2-Cache. + 24 + 1 + write-only + + + L2_IBUS1_CNT_CLR + The bit is used to clear ibus1 counter in L2-Cache. + 25 + 1 + write-only + + + L2_IBUS2_CNT_CLR + Reserved + 26 + 1 + read-only + + + L2_IBUS3_CNT_CLR + Reserved + 27 + 1 + read-only + + + L2_DBUS0_CNT_CLR + The bit is used to clear dbus0 counter in L2-Cache. + 28 + 1 + write-only + + + L2_DBUS1_CNT_CLR + The bit is used to clear dbus1 counter in L2-Cache. + 29 + 1 + write-only + + + L2_DBUS2_CNT_CLR + Reserved + 30 + 1 + read-only + + + L2_DBUS3_CNT_CLR + Reserved + 31 + 1 + read-only + + + + + L2_IBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x300 + 0x20 + + + L2_IBUS0_HIT_CNT + The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x304 + 0x20 + + + L2_IBUS0_MISS_CNT + The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x308 + 0x20 + + + L2_IBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS0_ACS_NXTLVL_RD_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x30C + 0x20 + + + L2_IBUS0_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x310 + 0x20 + + + L2_IBUS1_HIT_CNT + The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x314 + 0x20 + + + L2_IBUS1_MISS_CNT + The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x318 + 0x20 + + + L2_IBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS1_ACS_NXTLVL_RD_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x31C + 0x20 + + + L2_IBUS1_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x320 + 0x20 + + + L2_IBUS2_HIT_CNT + The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x324 + 0x20 + + + L2_IBUS2_MISS_CNT + The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x328 + 0x20 + + + L2_IBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS2_ACS_NXTLVL_RD_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x32C + 0x20 + + + L2_IBUS2_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x330 + 0x20 + + + L2_IBUS3_HIT_CNT + The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x334 + 0x20 + + + L2_IBUS3_MISS_CNT + The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x338 + 0x20 + + + L2_IBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_IBUS3_ACS_NXTLVL_RD_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x33C + 0x20 + + + L2_IBUS3_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_HIT_CNT + L2-Cache bus0 Hit-Access Counter register + 0x340 + 0x20 + + + L2_DBUS0_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_MISS_CNT + L2-Cache bus0 Miss-Access Counter register + 0x344 + 0x20 + + + L2_DBUS0_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_CONFLICT_CNT + L2-Cache bus0 Conflict-Access Counter register + 0x348 + 0x20 + + + L2_DBUS0_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_NXTLVL_RD_CNT + L2-Cache bus0 Next-Level-Access Counter register + 0x34C + 0x20 + + + L2_DBUS0_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS0_ACS_NXTLVL_WR_CNT + L2-Cache bus0 WB-Access Counter register + 0x350 + 0x20 + + + L2_DBUS0_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_HIT_CNT + L2-Cache bus1 Hit-Access Counter register + 0x354 + 0x20 + + + L2_DBUS1_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_MISS_CNT + L2-Cache bus1 Miss-Access Counter register + 0x358 + 0x20 + + + L2_DBUS1_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_CONFLICT_CNT + L2-Cache bus1 Conflict-Access Counter register + 0x35C + 0x20 + + + L2_DBUS1_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_NXTLVL_RD_CNT + L2-Cache bus1 Next-Level-Access Counter register + 0x360 + 0x20 + + + L2_DBUS1_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS1_ACS_NXTLVL_WR_CNT + L2-Cache bus1 WB-Access Counter register + 0x364 + 0x20 + + + L2_DBUS1_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_HIT_CNT + L2-Cache bus2 Hit-Access Counter register + 0x368 + 0x20 + + + L2_DBUS2_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_MISS_CNT + L2-Cache bus2 Miss-Access Counter register + 0x36C + 0x20 + + + L2_DBUS2_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_CONFLICT_CNT + L2-Cache bus2 Conflict-Access Counter register + 0x370 + 0x20 + + + L2_DBUS2_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_NXTLVL_RD_CNT + L2-Cache bus2 Next-Level-Access Counter register + 0x374 + 0x20 + + + L2_DBUS2_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS2_ACS_NXTLVL_WR_CNT + L2-Cache bus2 WB-Access Counter register + 0x378 + 0x20 + + + L2_DBUS2_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_HIT_CNT + L2-Cache bus3 Hit-Access Counter register + 0x37C + 0x20 + + + L2_DBUS3_HIT_CNT + The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_MISS_CNT + L2-Cache bus3 Miss-Access Counter register + 0x380 + 0x20 + + + L2_DBUS3_MISS_CNT + The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_CONFLICT_CNT + L2-Cache bus3 Conflict-Access Counter register + 0x384 + 0x20 + + + L2_DBUS3_CONFLICT_CNT + The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_NXTLVL_RD_CNT + L2-Cache bus3 Next-Level-Access Counter register + 0x388 + 0x20 + + + L2_DBUS3_NXTLVL_RD_CNT + The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_DBUS3_ACS_NXTLVL_WR_CNT + L2-Cache bus3 WB-Access Counter register + 0x38C + 0x20 + + + L2_DBUS3_NXTLVL_WR_CNT + The register records the number of write back when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + 0 + 32 + read-only + + + + + L2_CACHE_ACS_FAIL_ID_ATTR + L2-Cache Access Fail ID/attribution information register + 0x390 + 0x20 + + + L2_CACHE_FAIL_ID + The register records the ID of fail-access when L1-Cache accesses L2-Cache. + 0 + 16 + read-only + + + L2_CACHE_FAIL_ATTR + The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache. + 16 + 16 + read-only + + + + + L2_CACHE_ACS_FAIL_ADDR + L2-Cache Access Fail Address information register + 0x394 + 0x20 + + + L2_CACHE_FAIL_ADDR + The register records the address of fail-access when L1-Cache accesses L2-Cache. + 0 + 32 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_ENA + L1-Cache Access Fail Interrupt enable register + 0x398 + 0x20 + + + L2_CACHE_PLD_DONE_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation done. + 5 + 1 + read-write + + + L2_CACHE_PLD_ERR_INT_ENA + The bit is used to enable interrupt of L2-Cache preload-operation error. + 12 + 1 + read-write + + + + + L2_CACHE_SYNC_PRELOAD_INT_CLR + Sync Preload operation Interrupt clear register + 0x39C + 0x20 + + + L2_CACHE_PLD_DONE_INT_CLR + The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + write-only + + + L2_CACHE_PLD_ERR_INT_CLR + The bit is used to clear interrupt of L2-Cache preload-operation error. + 12 + 1 + write-only + + + + + L2_CACHE_SYNC_PRELOAD_INT_RAW + Sync Preload operation Interrupt raw register + 0x3A0 + 0x20 + + + L2_CACHE_PLD_DONE_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-write + + + L2_CACHE_PLD_ERR_INT_RAW + The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs. + 12 + 1 + read-write + + + + + L2_CACHE_SYNC_PRELOAD_INT_ST + L1-Cache Access Fail Interrupt status register + 0x3A4 + 0x20 + + + L2_CACHE_PLD_DONE_INT_ST + The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done. + 5 + 1 + read-only + + + L2_CACHE_PLD_ERR_INT_ST + The bit indicates the status of the interrupt of L2-Cache preload-operation error. + 12 + 1 + read-only + + + + + L2_CACHE_SYNC_PRELOAD_EXCEPTION + Cache Sync/Preload Operation exception register + 0x3A8 + 0x20 + + + L2_CACHE_PLD_ERR_CODE + The value 2 is Only available which means preload size is error in L2-Cache. + 10 + 2 + read-only + + + + + L2_CACHE_SYNC_RST_CTRL + Cache Sync Reset control register + 0x3AC + 0x20 + + + L2_CACHE_SYNC_RST + set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + 5 + 1 + read-write + + + + + L2_CACHE_PRELOAD_RST_CTRL + Cache Preload Reset control register + 0x3B0 + 0x20 + + + L2_CACHE_PLD_RST + set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + 5 + 1 + read-write + + + + + L2_CACHE_AUTOLOAD_BUF_CLR_CTRL + Cache Autoload buffer clear control register + 0x3B4 + 0x20 + + + L2_CACHE_ALD_BUF_CLR + set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache. + 5 + 1 + read-write + + + + + L2_UNALLOCATE_BUFFER_CLEAR + Unallocate request buffer clear registers + 0x3B8 + 0x20 + + + L2_CACHE_UNALLOC_CLR + The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed. + 5 + 1 + read-write + + + + + L2_CACHE_ACCESS_ATTR_CTRL + L2 cache access attribute control register + 0x3BC + 0x20 + 0x0000000F + + + L2_CACHE_ACCESS_FORCE_CC + Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable. + 0 + 1 + read-write + + + L2_CACHE_ACCESS_FORCE_WB + Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through. + 1 + 1 + read-write + + + L2_CACHE_ACCESS_FORCE_WMA + Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate. + 2 + 1 + read-write + + + L2_CACHE_ACCESS_FORCE_RMA + Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate. + 3 + 1 + read-write + + + + + L2_CACHE_OBJECT_CTRL + Cache Tag and Data memory Object control register + 0x3C0 + 0x20 + + + L2_CACHE_TAG_OBJECT + Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register. + 5 + 1 + read-write + + + L2_CACHE_MEM_OBJECT + Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register. + 11 + 1 + read-write + + + + + L2_CACHE_WAY_OBJECT + Cache Tag and Data memory way register + 0x3C4 + 0x20 + + + L2_CACHE_WAY_OBJECT + Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7. + 0 + 3 + read-write + + + + + L2_CACHE_VADDR + Cache Vaddr register + 0x3C8 + 0x20 + 0x40000000 + + + L2_CACHE_VADDR + Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + 0 + 32 + read-write + + + + + L2_CACHE_DEBUG_BUS + Cache Tag/data memory content register + 0x3CC + 0x20 + 0x000003CC + + + L2_CACHE_DEBUG_BUS + This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + 0 + 32 + read-write + + + + + LEVEL_SPLIT1 + USED TO SPLIT L1 CACHE AND L2 CACHE + 0x3D0 + 0x20 + 0x000003D0 + + + LEVEL_SPLIT1 + Reserved + 0 + 32 + read-only + + + + + CLOCK_GATE + Clock gate control register + 0x3D4 + 0x20 + 0x00000001 + + + CLK_EN + The bit is used to enable clock gate when access all registers in this module. + 0 + 1 + read-write + + + + + REDUNDANCY_SIG0 + Cache redundancy signal 0 register + 0x3D8 + 0x20 + + + REDCY_SIG0 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG1 + Cache redundancy signal 1 register + 0x3DC + 0x20 + + + REDCY_SIG1 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG2 + Cache redundancy signal 2 register + 0x3E0 + 0x20 + + + REDCY_SIG2 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG3 + Cache redundancy signal 3 register + 0x3E4 + 0x20 + + + REDCY_SIG3 + Those bits are prepared for ECO. + 0 + 32 + read-write + + + + + REDUNDANCY_SIG4 + Cache redundancy signal 0 register + 0x3E8 + 0x20 + + + REDCY_SIG4 + Those bits are prepared for ECO. + 0 + 4 + read-only + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02304130 + + + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE0 + Interrupt Controller (Core 0) + CORE0 + 0x500D6000 + + 0x0 + 0x218 + registers + + + + LP_RTC_INT_MAP + NA + 0x0 + 0x20 + + + CORE0_LP_RTC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_WDT_INT_MAP + NA + 0x4 + 0x20 + + + CORE0_LP_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_0_INT_MAP + NA + 0x8 + 0x20 + + + CORE0_LP_TIMER_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_1_INT_MAP + NA + 0xC + 0x20 + + + CORE0_LP_TIMER_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_HP_INT_MAP + NA + 0x10 + 0x20 + + + CORE0_MB_HP_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_LP_INT_MAP + NA + 0x14 + 0x20 + + + CORE0_MB_LP_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_0_INT_MAP + NA + 0x18 + 0x20 + + + CORE0_PMU_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_1_INT_MAP + NA + 0x1C + 0x20 + + + CORE0_PMU_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ANAPERI_INT_MAP + NA + 0x20 + 0x20 + + + CORE0_LP_ANAPERI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ADC_INT_MAP + NA + 0x24 + 0x20 + + + CORE0_LP_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_GPIO_INT_MAP + NA + 0x28 + 0x20 + + + CORE0_LP_GPIO_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2C_INT_MAP + NA + 0x2C + 0x20 + + + CORE0_LP_I2C_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2S_INT_MAP + NA + 0x30 + 0x20 + + + CORE0_LP_I2S_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SPI_INT_MAP + NA + 0x34 + 0x20 + + + CORE0_LP_SPI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TOUCH_INT_MAP + NA + 0x38 + 0x20 + + + CORE0_LP_TOUCH_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TSENS_INT_MAP + NA + 0x3C + 0x20 + + + CORE0_LP_TSENS_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_UART_INT_MAP + NA + 0x40 + 0x20 + + + CORE0_LP_UART_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_EFUSE_INT_MAP + NA + 0x44 + 0x20 + + + CORE0_LP_EFUSE_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SW_INT_MAP + NA + 0x48 + 0x20 + + + CORE0_LP_SW_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SYSREG_INT_MAP + NA + 0x4C + 0x20 + + + CORE0_LP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_HUK_INT_MAP + NA + 0x50 + 0x20 + + + CORE0_LP_HUK_INT_MAP + NA + 0 + 6 + read-write + + + + + SYS_ICM_INT_MAP + NA + 0x54 + 0x20 + + + CORE0_SYS_ICM_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_DEVICE_INT_MAP + NA + 0x58 + 0x20 + + + CORE0_USB_DEVICE_INT_MAP + NA + 0 + 6 + read-write + + + + + SDIO_HOST_INT_MAP + NA + 0x5C + 0x20 + + + CORE0_SDIO_HOST_INT_MAP + NA + 0 + 6 + read-write + + + + + GDMA_INT_MAP + NA + 0x60 + 0x20 + + + CORE0_GDMA_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI2_INT_MAP + NA + 0x64 + 0x20 + + + CORE0_SPI2_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI3_INT_MAP + NA + 0x68 + 0x20 + + + CORE0_SPI3_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S0_INT_MAP + NA + 0x6C + 0x20 + + + CORE0_I2S0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S1_INT_MAP + NA + 0x70 + 0x20 + + + CORE0_I2S1_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S2_INT_MAP + NA + 0x74 + 0x20 + + + CORE0_I2S2_INT_MAP + NA + 0 + 6 + read-write + + + + + UHCI0_INT_MAP + NA + 0x78 + 0x20 + + + CORE0_UHCI0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART0_INT_MAP + NA + 0x7C + 0x20 + + + CORE0_UART0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART1_INT_MAP + NA + 0x80 + 0x20 + + + CORE0_UART1_INT_MAP + NA + 0 + 6 + read-write + + + + + UART2_INT_MAP + NA + 0x84 + 0x20 + + + CORE0_UART2_INT_MAP + NA + 0 + 6 + read-write + + + + + UART3_INT_MAP + NA + 0x88 + 0x20 + + + CORE0_UART3_INT_MAP + NA + 0 + 6 + read-write + + + + + UART4_INT_MAP + NA + 0x8C + 0x20 + + + CORE0_UART4_INT_MAP + NA + 0 + 6 + read-write + + + + + LCD_CAM_INT_MAP + NA + 0x90 + 0x20 + + + CORE0_LCD_CAM_INT_MAP + NA + 0 + 6 + read-write + + + + + ADC_INT_MAP + NA + 0x94 + 0x20 + + + CORE0_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM0_INT_MAP + NA + 0x98 + 0x20 + + + CORE0_PWM0_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM1_INT_MAP + NA + 0x9C + 0x20 + + + CORE0_PWM1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN0_INT_MAP + NA + 0xA0 + 0x20 + + + CORE0_CAN0_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN1_INT_MAP + NA + 0xA4 + 0x20 + + + CORE0_CAN1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN2_INT_MAP + NA + 0xA8 + 0x20 + + + CORE0_CAN2_INT_MAP + NA + 0 + 6 + read-write + + + + + RMT_INT_MAP + NA + 0xAC + 0x20 + + + CORE0_RMT_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C0_INT_MAP + NA + 0xB0 + 0x20 + + + CORE0_I2C0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C1_INT_MAP + NA + 0xB4 + 0x20 + + + CORE0_I2C1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T0_INT_MAP + NA + 0xB8 + 0x20 + + + CORE0_TIMERGRP0_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T1_INT_MAP + NA + 0xBC + 0x20 + + + CORE0_TIMERGRP0_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_WDT_INT_MAP + NA + 0xC0 + 0x20 + + + CORE0_TIMERGRP0_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T0_INT_MAP + NA + 0xC4 + 0x20 + + + CORE0_TIMERGRP1_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T1_INT_MAP + NA + 0xC8 + 0x20 + + + CORE0_TIMERGRP1_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_WDT_INT_MAP + NA + 0xCC + 0x20 + + + CORE0_TIMERGRP1_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LEDC_INT_MAP + NA + 0xD0 + 0x20 + + + CORE0_LEDC_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + NA + 0xD4 + 0x20 + + + CORE0_SYSTIMER_TARGET0_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + NA + 0xD8 + 0x20 + + + CORE0_SYSTIMER_TARGET1_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + NA + 0xDC + 0x20 + + + CORE0_SYSTIMER_TARGET2_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH0_INT_MAP + NA + 0xE0 + 0x20 + + + CORE0_AHB_PDMA_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH1_INT_MAP + NA + 0xE4 + 0x20 + + + CORE0_AHB_PDMA_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH2_INT_MAP + NA + 0xE8 + 0x20 + + + CORE0_AHB_PDMA_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH0_INT_MAP + NA + 0xEC + 0x20 + + + CORE0_AHB_PDMA_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH1_INT_MAP + NA + 0xF0 + 0x20 + + + CORE0_AHB_PDMA_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH2_INT_MAP + NA + 0xF4 + 0x20 + + + CORE0_AHB_PDMA_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH0_INT_MAP + NA + 0xF8 + 0x20 + + + CORE0_AXI_PDMA_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH1_INT_MAP + NA + 0xFC + 0x20 + + + CORE0_AXI_PDMA_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH2_INT_MAP + NA + 0x100 + 0x20 + + + CORE0_AXI_PDMA_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH0_INT_MAP + NA + 0x104 + 0x20 + + + CORE0_AXI_PDMA_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH1_INT_MAP + NA + 0x108 + 0x20 + + + CORE0_AXI_PDMA_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH2_INT_MAP + NA + 0x10C + 0x20 + + + CORE0_AXI_PDMA_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + RSA_INT_MAP + NA + 0x110 + 0x20 + + + CORE0_RSA_INT_MAP + NA + 0 + 6 + read-write + + + + + AES_INT_MAP + NA + 0x114 + 0x20 + + + CORE0_AES_INT_MAP + NA + 0 + 6 + read-write + + + + + SHA_INT_MAP + NA + 0x118 + 0x20 + + + CORE0_SHA_INT_MAP + NA + 0 + 6 + read-write + + + + + ECC_INT_MAP + NA + 0x11C + 0x20 + + + CORE0_ECC_INT_MAP + NA + 0 + 6 + read-write + + + + + ECDSA_INT_MAP + NA + 0x120 + 0x20 + + + CORE0_ECDSA_INT_MAP + NA + 0 + 6 + read-write + + + + + KM_INT_MAP + NA + 0x124 + 0x20 + + + CORE0_KM_INT_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT0_MAP + NA + 0x128 + 0x20 + + + CORE0_GPIO_INT0_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT1_MAP + NA + 0x12C + 0x20 + + + CORE0_GPIO_INT1_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT2_MAP + NA + 0x130 + 0x20 + + + CORE0_GPIO_INT2_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT3_MAP + NA + 0x134 + 0x20 + + + CORE0_GPIO_INT3_MAP + NA + 0 + 6 + read-write + + + + + GPIO_PAD_COMP_INT_MAP + NA + 0x138 + 0x20 + + + CORE0_GPIO_PAD_COMP_INT_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_0_MAP + NA + 0x13C + 0x20 + + + CORE0_CPU_INT_FROM_CPU_0_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_1_MAP + NA + 0x140 + 0x20 + + + CORE0_CPU_INT_FROM_CPU_1_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_2_MAP + NA + 0x144 + 0x20 + + + CORE0_CPU_INT_FROM_CPU_2_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_3_MAP + NA + 0x148 + 0x20 + + + CORE0_CPU_INT_FROM_CPU_3_MAP + NA + 0 + 6 + read-write + + + + + CACHE_INT_MAP + NA + 0x14C + 0x20 + + + CORE0_CACHE_INT_MAP + NA + 0 + 6 + read-write + + + + + FLASH_MSPI_INT_MAP + NA + 0x150 + 0x20 + + + CORE0_FLASH_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + CSI_BRIDGE_INT_MAP + NA + 0x154 + 0x20 + + + CORE0_CSI_BRIDGE_INT_MAP + NA + 0 + 6 + read-write + + + + + DSI_BRIDGE_INT_MAP + NA + 0x158 + 0x20 + + + CORE0_DSI_BRIDGE_INT_MAP + NA + 0 + 6 + read-write + + + + + CSI_INT_MAP + NA + 0x15C + 0x20 + + + CORE0_CSI_INT_MAP + NA + 0 + 6 + read-write + + + + + DSI_INT_MAP + NA + 0x160 + 0x20 + + + CORE0_DSI_INT_MAP + NA + 0 + 6 + read-write + + + + + GMII_PHY_INT_MAP + NA + 0x164 + 0x20 + + + CORE0_GMII_PHY_INT_MAP + NA + 0 + 6 + read-write + + + + + LPI_INT_MAP + NA + 0x168 + 0x20 + + + CORE0_LPI_INT_MAP + NA + 0 + 6 + read-write + + + + + PMT_INT_MAP + NA + 0x16C + 0x20 + + + CORE0_PMT_INT_MAP + NA + 0 + 6 + read-write + + + + + SBD_INT_MAP + NA + 0x170 + 0x20 + + + CORE0_SBD_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG_INT_MAP + NA + 0x174 + 0x20 + + + CORE0_USB_OTG_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG_ENDP_MULTI_PROC_INT_MAP + NA + 0x178 + 0x20 + + + CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP + NA + 0 + 6 + read-write + + + + + JPEG_INT_MAP + NA + 0x17C + 0x20 + + + CORE0_JPEG_INT_MAP + NA + 0 + 6 + read-write + + + + + PPA_INT_MAP + NA + 0x180 + 0x20 + + + CORE0_PPA_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE0_TRACE_INT_MAP + NA + 0x184 + 0x20 + + + CORE0_CORE0_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE1_TRACE_INT_MAP + NA + 0x188 + 0x20 + + + CORE0_CORE1_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_CORE_CTRL_INT_MAP + NA + 0x18C + 0x20 + + + CORE0_HP_CORE_CTRL_INT_MAP + NA + 0 + 6 + read-write + + + + + ISP_INT_MAP + NA + 0x190 + 0x20 + + + CORE0_ISP_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_MST_INT_MAP + NA + 0x194 + 0x20 + + + CORE0_I3C_MST_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_SLV_INT_MAP + NA + 0x198 + 0x20 + + + CORE0_I3C_SLV_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG11_INT_MAP + NA + 0x19C + 0x20 + + + CORE0_USB_OTG11_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH0_INT_MAP + NA + 0x1A0 + 0x20 + + + CORE0_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH1_INT_MAP + NA + 0x1A4 + 0x20 + + + CORE0_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH0_INT_MAP + NA + 0x1A8 + 0x20 + + + CORE0_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH1_INT_MAP + NA + 0x1AC + 0x20 + + + CORE0_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH2_INT_MAP + NA + 0x1B0 + 0x20 + + + CORE0_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + PSRAM_MSPI_INT_MAP + NA + 0x1B4 + 0x20 + + + CORE0_PSRAM_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_SYSREG_INT_MAP + NA + 0x1B8 + 0x20 + + + CORE0_HP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + PCNT_INT_MAP + NA + 0x1BC + 0x20 + + + CORE0_PCNT_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PAU_INT_MAP + NA + 0x1C0 + 0x20 + + + CORE0_HP_PAU_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_RX_INT_MAP + NA + 0x1C4 + 0x20 + + + CORE0_HP_PARLIO_RX_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_TX_INT_MAP + NA + 0x1C8 + 0x20 + + + CORE0_HP_PARLIO_TX_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH0_INT_MAP + NA + 0x1CC + 0x20 + + + CORE0_H264_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH1_INT_MAP + NA + 0x1D0 + 0x20 + + + CORE0_H264_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH2_INT_MAP + NA + 0x1D4 + 0x20 + + + CORE0_H264_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH3_INT_MAP + NA + 0x1D8 + 0x20 + + + CORE0_H264_DMA2D_OUT_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH4_INT_MAP + NA + 0x1DC + 0x20 + + + CORE0_H264_DMA2D_OUT_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH0_INT_MAP + NA + 0x1E0 + 0x20 + + + CORE0_H264_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH1_INT_MAP + NA + 0x1E4 + 0x20 + + + CORE0_H264_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH2_INT_MAP + NA + 0x1E8 + 0x20 + + + CORE0_H264_DMA2D_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH3_INT_MAP + NA + 0x1EC + 0x20 + + + CORE0_H264_DMA2D_IN_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH4_INT_MAP + NA + 0x1F0 + 0x20 + + + CORE0_H264_DMA2D_IN_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH5_INT_MAP + NA + 0x1F4 + 0x20 + + + CORE0_H264_DMA2D_IN_CH5_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_REG_INT_MAP + NA + 0x1F8 + 0x20 + + + CORE0_H264_REG_INT_MAP + NA + 0 + 6 + read-write + + + + + ASSIST_DEBUG_INT_MAP + NA + 0x1FC + 0x20 + + + CORE0_ASSIST_DEBUG_INT_MAP + NA + 0 + 6 + read-write + + + + + INTR_STATUS_REG_0 + NA + 0x200 + 0x20 + + + CORE0_INTR_STATUS_0 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_1 + NA + 0x204 + 0x20 + + + CORE0_INTR_STATUS_1 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_2 + NA + 0x208 + 0x20 + + + CORE0_INTR_STATUS_2 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_3 + NA + 0x20C + 0x20 + + + CORE0_INTR_STATUS_3 + NA + 0 + 32 + read-only + + + + + CLOCK_GATE + NA + 0x210 + 0x20 + 0x00000001 + + + CORE0_REG_CLK_EN + NA + 0 + 1 + read-write + + + + + INTERRUPT_REG_DATE + NA + 0x3FC + 0x20 + 0x02003020 + + + CORE0_INTERRUPT_REG_DATE + NA + 0 + 28 + read-write + + + + + + + INTERRUPT_CORE1 + Interrupt Controller (Core 1) + CORE1 + 0x500D6800 + + 0x0 + 0x218 + registers + + + + LP_RTC_INT_MAP + NA + 0x0 + 0x20 + + + CORE1_LP_RTC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_WDT_INT_MAP + NA + 0x4 + 0x20 + + + CORE1_LP_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_0_INT_MAP + NA + 0x8 + 0x20 + + + CORE1_LP_TIMER_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TIMER_REG_1_INT_MAP + NA + 0xC + 0x20 + + + CORE1_LP_TIMER_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_HP_INT_MAP + NA + 0x10 + 0x20 + + + CORE1_MB_HP_INT_MAP + NA + 0 + 6 + read-write + + + + + MB_LP_INT_MAP + NA + 0x14 + 0x20 + + + CORE1_MB_LP_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_0_INT_MAP + NA + 0x18 + 0x20 + + + CORE1_PMU_REG_0_INT_MAP + NA + 0 + 6 + read-write + + + + + PMU_REG_1_INT_MAP + NA + 0x1C + 0x20 + + + CORE1_PMU_REG_1_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ANAPERI_INT_MAP + NA + 0x20 + 0x20 + + + CORE1_LP_ANAPERI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_ADC_INT_MAP + NA + 0x24 + 0x20 + + + CORE1_LP_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_GPIO_INT_MAP + NA + 0x28 + 0x20 + + + CORE1_LP_GPIO_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2C_INT_MAP + NA + 0x2C + 0x20 + + + CORE1_LP_I2C_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_I2S_INT_MAP + NA + 0x30 + 0x20 + + + CORE1_LP_I2S_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SPI_INT_MAP + NA + 0x34 + 0x20 + + + CORE1_LP_SPI_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TOUCH_INT_MAP + NA + 0x38 + 0x20 + + + CORE1_LP_TOUCH_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_TSENS_INT_MAP + NA + 0x3C + 0x20 + + + CORE1_LP_TSENS_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_UART_INT_MAP + NA + 0x40 + 0x20 + + + CORE1_LP_UART_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_EFUSE_INT_MAP + NA + 0x44 + 0x20 + + + CORE1_LP_EFUSE_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SW_INT_MAP + NA + 0x48 + 0x20 + + + CORE1_LP_SW_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_SYSREG_INT_MAP + NA + 0x4C + 0x20 + + + CORE1_LP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + LP_HUK_INT_MAP + NA + 0x50 + 0x20 + + + CORE1_LP_HUK_INT_MAP + NA + 0 + 6 + read-write + + + + + SYS_ICM_INT_MAP + NA + 0x54 + 0x20 + + + CORE1_SYS_ICM_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_DEVICE_INT_MAP + NA + 0x58 + 0x20 + + + CORE1_USB_DEVICE_INT_MAP + NA + 0 + 6 + read-write + + + + + SDIO_HOST_INT_MAP + NA + 0x5C + 0x20 + + + CORE1_SDIO_HOST_INT_MAP + NA + 0 + 6 + read-write + + + + + GDMA_INT_MAP + NA + 0x60 + 0x20 + + + CORE1_GDMA_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI2_INT_MAP + NA + 0x64 + 0x20 + + + CORE1_SPI2_INT_MAP + NA + 0 + 6 + read-write + + + + + SPI3_INT_MAP + NA + 0x68 + 0x20 + + + CORE1_SPI3_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S0_INT_MAP + NA + 0x6C + 0x20 + + + CORE1_I2S0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S1_INT_MAP + NA + 0x70 + 0x20 + + + CORE1_I2S1_INT_MAP + NA + 0 + 6 + read-write + + + + + I2S2_INT_MAP + NA + 0x74 + 0x20 + + + CORE1_I2S2_INT_MAP + NA + 0 + 6 + read-write + + + + + UHCI0_INT_MAP + NA + 0x78 + 0x20 + + + CORE1_UHCI0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART0_INT_MAP + NA + 0x7C + 0x20 + + + CORE1_UART0_INT_MAP + NA + 0 + 6 + read-write + + + + + UART1_INT_MAP + NA + 0x80 + 0x20 + + + CORE1_UART1_INT_MAP + NA + 0 + 6 + read-write + + + + + UART2_INT_MAP + NA + 0x84 + 0x20 + + + CORE1_UART2_INT_MAP + NA + 0 + 6 + read-write + + + + + UART3_INT_MAP + NA + 0x88 + 0x20 + + + CORE1_UART3_INT_MAP + NA + 0 + 6 + read-write + + + + + UART4_INT_MAP + NA + 0x8C + 0x20 + + + CORE1_UART4_INT_MAP + NA + 0 + 6 + read-write + + + + + LCD_CAM_INT_MAP + NA + 0x90 + 0x20 + + + CORE1_LCD_CAM_INT_MAP + NA + 0 + 6 + read-write + + + + + ADC_INT_MAP + NA + 0x94 + 0x20 + + + CORE1_ADC_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM0_INT_MAP + NA + 0x98 + 0x20 + + + CORE1_PWM0_INT_MAP + NA + 0 + 6 + read-write + + + + + PWM1_INT_MAP + NA + 0x9C + 0x20 + + + CORE1_PWM1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN0_INT_MAP + NA + 0xA0 + 0x20 + + + CORE1_CAN0_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN1_INT_MAP + NA + 0xA4 + 0x20 + + + CORE1_CAN1_INT_MAP + NA + 0 + 6 + read-write + + + + + CAN2_INT_MAP + NA + 0xA8 + 0x20 + + + CORE1_CAN2_INT_MAP + NA + 0 + 6 + read-write + + + + + RMT_INT_MAP + NA + 0xAC + 0x20 + + + CORE1_RMT_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C0_INT_MAP + NA + 0xB0 + 0x20 + + + CORE1_I2C0_INT_MAP + NA + 0 + 6 + read-write + + + + + I2C1_INT_MAP + NA + 0xB4 + 0x20 + + + CORE1_I2C1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T0_INT_MAP + NA + 0xB8 + 0x20 + + + CORE1_TIMERGRP0_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_T1_INT_MAP + NA + 0xBC + 0x20 + + + CORE1_TIMERGRP0_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP0_WDT_INT_MAP + NA + 0xC0 + 0x20 + + + CORE1_TIMERGRP0_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T0_INT_MAP + NA + 0xC4 + 0x20 + + + CORE1_TIMERGRP1_T0_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_T1_INT_MAP + NA + 0xC8 + 0x20 + + + CORE1_TIMERGRP1_T1_INT_MAP + NA + 0 + 6 + read-write + + + + + TIMERGRP1_WDT_INT_MAP + NA + 0xCC + 0x20 + + + CORE1_TIMERGRP1_WDT_INT_MAP + NA + 0 + 6 + read-write + + + + + LEDC_INT_MAP + NA + 0xD0 + 0x20 + + + CORE1_LEDC_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET0_INT_MAP + NA + 0xD4 + 0x20 + + + CORE1_SYSTIMER_TARGET0_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET1_INT_MAP + NA + 0xD8 + 0x20 + + + CORE1_SYSTIMER_TARGET1_INT_MAP + NA + 0 + 6 + read-write + + + + + SYSTIMER_TARGET2_INT_MAP + NA + 0xDC + 0x20 + + + CORE1_SYSTIMER_TARGET2_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH0_INT_MAP + NA + 0xE0 + 0x20 + + + CORE1_AHB_PDMA_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH1_INT_MAP + NA + 0xE4 + 0x20 + + + CORE1_AHB_PDMA_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_IN_CH2_INT_MAP + NA + 0xE8 + 0x20 + + + CORE1_AHB_PDMA_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH0_INT_MAP + NA + 0xEC + 0x20 + + + CORE1_AHB_PDMA_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH1_INT_MAP + NA + 0xF0 + 0x20 + + + CORE1_AHB_PDMA_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AHB_PDMA_OUT_CH2_INT_MAP + NA + 0xF4 + 0x20 + + + CORE1_AHB_PDMA_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH0_INT_MAP + NA + 0xF8 + 0x20 + + + CORE1_AXI_PDMA_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH1_INT_MAP + NA + 0xFC + 0x20 + + + CORE1_AXI_PDMA_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_IN_CH2_INT_MAP + NA + 0x100 + 0x20 + + + CORE1_AXI_PDMA_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH0_INT_MAP + NA + 0x104 + 0x20 + + + CORE1_AXI_PDMA_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH1_INT_MAP + NA + 0x108 + 0x20 + + + CORE1_AXI_PDMA_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + AXI_PDMA_OUT_CH2_INT_MAP + NA + 0x10C + 0x20 + + + CORE1_AXI_PDMA_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + RSA_INT_MAP + NA + 0x110 + 0x20 + + + CORE1_RSA_INT_MAP + NA + 0 + 6 + read-write + + + + + AES_INT_MAP + NA + 0x114 + 0x20 + + + CORE1_AES_INT_MAP + NA + 0 + 6 + read-write + + + + + SHA_INT_MAP + NA + 0x118 + 0x20 + + + CORE1_SHA_INT_MAP + NA + 0 + 6 + read-write + + + + + ECC_INT_MAP + NA + 0x11C + 0x20 + + + CORE1_ECC_INT_MAP + NA + 0 + 6 + read-write + + + + + ECDSA_INT_MAP + NA + 0x120 + 0x20 + + + CORE1_ECDSA_INT_MAP + NA + 0 + 6 + read-write + + + + + KM_INT_MAP + NA + 0x124 + 0x20 + + + CORE1_KM_INT_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT0_MAP + NA + 0x128 + 0x20 + + + CORE1_GPIO_INT0_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT1_MAP + NA + 0x12C + 0x20 + + + CORE1_GPIO_INT1_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT2_MAP + NA + 0x130 + 0x20 + + + CORE1_GPIO_INT2_MAP + NA + 0 + 6 + read-write + + + + + GPIO_INT3_MAP + NA + 0x134 + 0x20 + + + CORE1_GPIO_INT3_MAP + NA + 0 + 6 + read-write + + + + + GPIO_PAD_COMP_INT_MAP + NA + 0x138 + 0x20 + + + CORE1_GPIO_PAD_COMP_INT_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_0_MAP + NA + 0x13C + 0x20 + + + CORE1_CPU_INT_FROM_CPU_0_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_1_MAP + NA + 0x140 + 0x20 + + + CORE1_CPU_INT_FROM_CPU_1_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_2_MAP + NA + 0x144 + 0x20 + + + CORE1_CPU_INT_FROM_CPU_2_MAP + NA + 0 + 6 + read-write + + + + + CPU_INT_FROM_CPU_3_MAP + NA + 0x148 + 0x20 + + + CORE1_CPU_INT_FROM_CPU_3_MAP + NA + 0 + 6 + read-write + + + + + CACHE_INT_MAP + NA + 0x14C + 0x20 + + + CORE1_CACHE_INT_MAP + NA + 0 + 6 + read-write + + + + + FLASH_MSPI_INT_MAP + NA + 0x150 + 0x20 + + + CORE1_FLASH_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + CSI_BRIDGE_INT_MAP + NA + 0x154 + 0x20 + + + CORE1_CSI_BRIDGE_INT_MAP + NA + 0 + 6 + read-write + + + + + DSI_BRIDGE_INT_MAP + NA + 0x158 + 0x20 + + + CORE1_DSI_BRIDGE_INT_MAP + NA + 0 + 6 + read-write + + + + + CSI_INT_MAP + NA + 0x15C + 0x20 + + + CORE1_CSI_INT_MAP + NA + 0 + 6 + read-write + + + + + DSI_INT_MAP + NA + 0x160 + 0x20 + + + CORE1_DSI_INT_MAP + NA + 0 + 6 + read-write + + + + + GMII_PHY_INT_MAP + NA + 0x164 + 0x20 + + + CORE1_GMII_PHY_INT_MAP + NA + 0 + 6 + read-write + + + + + LPI_INT_MAP + NA + 0x168 + 0x20 + + + CORE1_LPI_INT_MAP + NA + 0 + 6 + read-write + + + + + PMT_INT_MAP + NA + 0x16C + 0x20 + + + CORE1_PMT_INT_MAP + NA + 0 + 6 + read-write + + + + + SBD_INT_MAP + NA + 0x170 + 0x20 + + + CORE1_SBD_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG_INT_MAP + NA + 0x174 + 0x20 + + + CORE1_USB_OTG_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG_ENDP_MULTI_PROC_INT_MAP + NA + 0x178 + 0x20 + + + CORE1_USB_OTG_ENDP_MULTI_PROC_INT_MAP + NA + 0 + 6 + read-write + + + + + JPEG_INT_MAP + NA + 0x17C + 0x20 + + + CORE1_JPEG_INT_MAP + NA + 0 + 6 + read-write + + + + + PPA_INT_MAP + NA + 0x180 + 0x20 + + + CORE1_PPA_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE0_TRACE_INT_MAP + NA + 0x184 + 0x20 + + + CORE1_CORE0_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + CORE1_TRACE_INT_MAP + NA + 0x188 + 0x20 + + + CORE1_CORE1_TRACE_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_CORE_CTRL_INT_MAP + NA + 0x18C + 0x20 + + + CORE1_HP_CORE_CTRL_INT_MAP + NA + 0 + 6 + read-write + + + + + ISP_INT_MAP + NA + 0x190 + 0x20 + + + CORE1_ISP_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_MST_INT_MAP + NA + 0x194 + 0x20 + + + CORE1_I3C_MST_INT_MAP + NA + 0 + 6 + read-write + + + + + I3C_SLV_INT_MAP + NA + 0x198 + 0x20 + + + CORE1_I3C_SLV_INT_MAP + NA + 0 + 6 + read-write + + + + + USB_OTG11_INT_MAP + NA + 0x19C + 0x20 + + + CORE1_USB_OTG11_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH0_INT_MAP + NA + 0x1A0 + 0x20 + + + CORE1_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_IN_CH1_INT_MAP + NA + 0x1A4 + 0x20 + + + CORE1_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH0_INT_MAP + NA + 0x1A8 + 0x20 + + + CORE1_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH1_INT_MAP + NA + 0x1AC + 0x20 + + + CORE1_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + DMA2D_OUT_CH2_INT_MAP + NA + 0x1B0 + 0x20 + + + CORE1_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + PSRAM_MSPI_INT_MAP + NA + 0x1B4 + 0x20 + + + CORE1_PSRAM_MSPI_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_SYSREG_INT_MAP + NA + 0x1B8 + 0x20 + + + CORE1_HP_SYSREG_INT_MAP + NA + 0 + 6 + read-write + + + + + PCNT_INT_MAP + NA + 0x1BC + 0x20 + + + CORE1_PCNT_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PAU_INT_MAP + NA + 0x1C0 + 0x20 + + + CORE1_HP_PAU_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_RX_INT_MAP + NA + 0x1C4 + 0x20 + + + CORE1_HP_PARLIO_RX_INT_MAP + NA + 0 + 6 + read-write + + + + + HP_PARLIO_TX_INT_MAP + NA + 0x1C8 + 0x20 + + + CORE1_HP_PARLIO_TX_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH0_INT_MAP + NA + 0x1CC + 0x20 + + + CORE1_H264_DMA2D_OUT_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH1_INT_MAP + NA + 0x1D0 + 0x20 + + + CORE1_H264_DMA2D_OUT_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH2_INT_MAP + NA + 0x1D4 + 0x20 + + + CORE1_H264_DMA2D_OUT_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH3_INT_MAP + NA + 0x1D8 + 0x20 + + + CORE1_H264_DMA2D_OUT_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_OUT_CH4_INT_MAP + NA + 0x1DC + 0x20 + + + CORE1_H264_DMA2D_OUT_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH0_INT_MAP + NA + 0x1E0 + 0x20 + + + CORE1_H264_DMA2D_IN_CH0_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH1_INT_MAP + NA + 0x1E4 + 0x20 + + + CORE1_H264_DMA2D_IN_CH1_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH2_INT_MAP + NA + 0x1E8 + 0x20 + + + CORE1_H264_DMA2D_IN_CH2_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH3_INT_MAP + NA + 0x1EC + 0x20 + + + CORE1_H264_DMA2D_IN_CH3_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH4_INT_MAP + NA + 0x1F0 + 0x20 + + + CORE1_H264_DMA2D_IN_CH4_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_DMA2D_IN_CH5_INT_MAP + NA + 0x1F4 + 0x20 + + + CORE1_H264_DMA2D_IN_CH5_INT_MAP + NA + 0 + 6 + read-write + + + + + H264_REG_INT_MAP + NA + 0x1F8 + 0x20 + + + CORE1_H264_REG_INT_MAP + NA + 0 + 6 + read-write + + + + + ASSIST_DEBUG_INT_MAP + NA + 0x1FC + 0x20 + + + CORE1_ASSIST_DEBUG_INT_MAP + NA + 0 + 6 + read-write + + + + + INTR_STATUS_REG_0 + NA + 0x200 + 0x20 + + + CORE1_INTR_STATUS_0 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_1 + NA + 0x204 + 0x20 + + + CORE1_INTR_STATUS_1 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_2 + NA + 0x208 + 0x20 + + + CORE1_INTR_STATUS_2 + NA + 0 + 32 + read-only + + + + + INTR_STATUS_REG_3 + NA + 0x20C + 0x20 + + + CORE1_INTR_STATUS_3 + NA + 0 + 32 + read-only + + + + + CLOCK_GATE + NA + 0x210 + 0x20 + 0x00000001 + + + CORE1_REG_CLK_EN + NA + 0 + 1 + read-write + + + + + INTERRUPT_REG_DATE + NA + 0x3FC + 0x20 + 0x02003020 + + + CORE1_INTERRUPT_REG_DATE + NA + 0 + 28 + read-write + + + + + + + MIPI_CSI_BRIDGE + MIPI Camera Interface Bridge + CSI_BRIG + 0x5009F800 + + 0x0 + 0x48 + registers + + + CSI_BRIDGE + 85 + + + + CLK_EN + csi bridge register mapping unit clock gating. + 0x0 + 0x20 + + + CLK_EN + 0: enable clock gating. 1: disable clock gating, clock always on. + 0 + 1 + read-write + + + + + CSI_EN + csi bridge enable. + 0x4 + 0x20 + + + CSI_BRIG_EN + 0: disable csi bridge. 1: enable csi bridge. + 0 + 1 + read-write + + + + + DMA_REQ_CFG + dma request configuration. + 0x8 + 0x20 + 0x00000080 + + + DMA_BURST_LEN + DMA burst length. + 0 + 12 + read-write + + + DMA_CFG_UPD_BY_BLK + 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: updated by frame. + 12 + 1 + read-write + + + DMA_FORCE_RD_STATUS + 1: mask dma request when reading frame info. 0: disable mask. + 16 + 1 + read-write + + + + + BUF_FLOW_CTL + csi bridge buffer control. + 0xC + 0x20 + 0x000007F8 + + + CSI_BUF_AFULL_THRD + buffer almost full threshold. + 0 + 14 + read-write + + + CSI_BUF_DEPTH + buffer data count. + 16 + 14 + read-only + + + + + DATA_TYPE_CFG + pixel data type configuration. + 0x10 + 0x20 + 0x00002F18 + + + DATA_TYPE_MIN + the min value of data type used for pixel filter. + 0 + 6 + read-write + + + DATA_TYPE_MAX + the max value of data type used for pixel filter. + 8 + 6 + read-write + + + + + FRAME_CFG + frame configuration. + 0x14 + 0x20 + 0x011E01E0 + + + VADR_NUM + vadr of frame data. + 0 + 12 + read-write + + + HADR_NUM + hadr of frame data. + 12 + 12 + read-write + + + HAS_HSYNC_E + 0: frame data doesn't contain hsync. 1: frame data contains hsync. + 24 + 1 + read-write + + + VADR_NUM_CHECK + 0: disable vadr check. 1: enable vadr check. + 25 + 1 + read-write + + + + + ENDIAN_MODE + data endianness order configuration. + 0x18 + 0x20 + + + BYTE_ENDIAN_ORDER + endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) when isp is bapassed. + 0 + 1 + read-write + + + BIT_ENDIAN_ORDER + N/A + 1 + 1 + read-write + + + + + INT_RAW + csi bridge interrupt raw. + 0x1C + 0x20 + + + VADR_NUM_GT_INT_RAW + reg_vadr_num is greater than real interrupt raw. + 0 + 1 + read-write + + + VADR_NUM_LT_INT_RAW + reg_vadr_num is less than real interrupt raw. + 1 + 1 + read-write + + + DISCARD_INT_RAW + an incomplete frame of data was sent interrupt raw. + 2 + 1 + read-write + + + CSI_BUF_OVERRUN_INT_RAW + buffer overrun interrupt raw. + 3 + 1 + read-write + + + CSI_ASYNC_FIFO_OVF_INT_RAW + buffer overflow interrupt raw. + 4 + 1 + read-write + + + DMA_CFG_HAS_UPDATED_INT_RAW + dma configuration update complete interrupt raw. + 5 + 1 + read-write + + + + + INT_CLR + csi bridge interrupt clr. + 0x20 + 0x20 + + + VADR_NUM_GT_REAL_INT_CLR + reg_vadr_num is greater than real interrupt clr. + 0 + 1 + write-only + + + VADR_NUM_LT_REAL_INT_CLR + reg_vadr_num is less than real interrupt clr. + 1 + 1 + write-only + + + DISCARD_INT_CLR + an incomplete frame of data was sent interrupt clr. + 2 + 1 + write-only + + + CSI_BUF_OVERRUN_INT_CLR + buffer overrun interrupt clr. + 3 + 1 + write-only + + + CSI_ASYNC_FIFO_OVF_INT_CLR + buffer overflow interrupt clr. + 4 + 1 + write-only + + + DMA_CFG_HAS_UPDATED_INT_CLR + dma configuration update complete interrupt clr. + 5 + 1 + write-only + + + + + INT_ST + csi bridge interrupt st. + 0x24 + 0x20 + + + VADR_NUM_GT_INT_ST + reg_vadr_num is greater than real interrupt st. + 0 + 1 + read-only + + + VADR_NUM_LT_INT_ST + reg_vadr_num is less than real interrupt st. + 1 + 1 + read-only + + + DISCARD_INT_ST + an incomplete frame of data was sent interrupt st. + 2 + 1 + read-only + + + CSI_BUF_OVERRUN_INT_ST + buffer overrun interrupt st. + 3 + 1 + read-only + + + CSI_ASYNC_FIFO_OVF_INT_ST + buffer overflow interrupt st. + 4 + 1 + read-only + + + DMA_CFG_HAS_UPDATED_INT_ST + dma configuration update complete interrupt st. + 5 + 1 + read-only + + + + + INT_ENA + csi bridge interrupt enable. + 0x28 + 0x20 + + + VADR_NUM_GT_INT_ENA + reg_vadr_num is greater than real interrupt enable. + 0 + 1 + read-write + + + VADR_NUM_LT_INT_ENA + reg_vadr_num is less than real interrupt enable. + 1 + 1 + read-write + + + DISCARD_INT_ENA + an incomplete frame of data was sent interrupt enable. + 2 + 1 + read-write + + + CSI_BUF_OVERRUN_INT_ENA + buffer overrun interrupt enable. + 3 + 1 + read-write + + + CSI_ASYNC_FIFO_OVF_INT_ENA + buffer overflow interrupt enable. + 4 + 1 + read-write + + + DMA_CFG_HAS_UPDATED_INT_ENA + dma configuration update complete interrupt enable. + 5 + 1 + read-write + + + + + DMA_REQ_INTERVAL + DMA interval configuration. + 0x2C + 0x20 + 0x00000001 + + + DMA_REQ_INTERVAL + 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle. + 0 + 16 + read-write + + + + + DMABLK_SIZE + DMA block size configuration. + 0x30 + 0x20 + 0x00001FFF + + + DMABLK_SIZE + the number of reg_dma_burst_len in a block + 0 + 13 + read-write + + + + + RDN_ECO_CS + N/A + 0x34 + 0x20 + + + RDN_ECO_EN + N/A + 0 + 1 + read-write + + + RDN_ECO_RESULT + N/A + 1 + 1 + read-only + + + + + RDN_ECO_LOW + N/A + 0x38 + 0x20 + + + RDN_ECO_LOW + N/A + 0 + 32 + read-write + + + + + RDN_ECO_HIGH + N/A + 0x3C + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + N/A + 0 + 32 + read-write + + + + + HOST_CTRL + csi host control by csi bridge. + 0x40 + 0x20 + 0x00000003 + + + CSI_ENABLECLK + enable clock lane module of csi phy. + 0 + 1 + read-write + + + CSI_CFG_CLK_EN + enable cfg_clk of csi host module. + 1 + 1 + read-write + + + LOOPBK_TEST_EN + for phy test by loopback dsi phy to csi phy. + 2 + 1 + read-write + + + + + MEM_CTRL + csi bridge buffer control. + 0x44 + 0x20 + 0x00002640 + + + CSI_BRIDGE_MEM_CLK_FORCE_ON + csi bridge memory clock gating force on. + 0 + 1 + read-write + + + CSI_MEM_AUX_CTRL + N/A + 1 + 14 + read-write + + + + + + + MIPI_CSI_HOST + MIPI Camera Interface Host + CSI_HOST + 0x5009F000 + + 0x0 + 0xA8 + registers + + + CSI + 87 + + + + VERSION + NA + 0x0 + 0x20 + 0x3135302A + + + VERSION + NA + 0 + 32 + read-only + + + + + N_LANES + NA + 0x4 + 0x20 + 0x00000001 + + + N_LANES + NA + 0 + 3 + read-write + + + + + CSI2_RESETN + NA + 0x8 + 0x20 + + + CSI2_RESETN + NA + 0 + 1 + read-write + + + + + INT_ST_MAIN + NA + 0xC + 0x20 + + + ST_STATUS_INT_PHY_FATAL + NA + 0 + 1 + read-only + + + ST_STATUS_INT_PKT_FATAL + NA + 1 + 1 + read-only + + + ST_STATUS_INT_BNDRY_FRAME_FATAL + NA + 2 + 1 + read-only + + + ST_STATUS_INT_SEQ_FRAME_FATAL + NA + 3 + 1 + read-only + + + ST_STATUS_INT_CRC_FRAME_FATAL + NA + 4 + 1 + read-only + + + ST_STATUS_INT_PLD_CRC_FATAL + NA + 5 + 1 + read-only + + + ST_STATUS_INT_DATA_ID + NA + 6 + 1 + read-only + + + ST_STATUS_INT_ECC_CORRECTED + NA + 7 + 1 + read-only + + + ST_STATUS_INT_PHY + NA + 16 + 1 + read-only + + + + + PHY_SHUTDOWNZ + NA + 0x40 + 0x20 + + + PHY_SHUTDOWNZ + NA + 0 + 1 + read-write + + + + + DPHY_RSTZ + NA + 0x44 + 0x20 + + + DPHY_RSTZ + NA + 0 + 1 + read-write + + + + + PHY_RX + NA + 0x48 + 0x20 + 0x00010000 + + + PHY_RXULPSESC_0 + NA + 0 + 1 + read-only + + + PHY_RXULPSESC_1 + NA + 1 + 1 + read-only + + + PHY_RXULPSCLKNOT + NA + 16 + 1 + read-only + + + PHY_RXCLKACTIVEHS + NA + 17 + 1 + read-only + + + + + PHY_STOPSTATE + NA + 0x4C + 0x20 + + + PHY_STOPSTATEDATA_0 + NA + 0 + 1 + read-only + + + PHY_STOPSTATEDATA_1 + NA + 1 + 1 + read-only + + + PHY_STOPSTATECLK + NA + 16 + 1 + read-only + + + + + PHY_TEST_CTRL0 + NA + 0x50 + 0x20 + 0x00000001 + + + PHY_TESTCLR + NA + 0 + 1 + read-write + + + PHY_TESTCLK + NA + 1 + 1 + read-write + + + + + PHY_TEST_CTRL1 + NA + 0x54 + 0x20 + + + PHY_TESTDIN + NA + 0 + 8 + read-write + + + PHY_TESTDOUT + NA + 8 + 8 + read-only + + + PHY_TESTEN + NA + 16 + 1 + read-write + + + + + VC_EXTENSION + NA + 0xC8 + 0x20 + + + VCX + NA + 0 + 1 + read-write + + + + + PHY_CAL + NA + 0xCC + 0x20 + + + RXSKEWCALHS + NA + 0 + 1 + read-only + + + + + INT_ST_PHY_FATAL + NA + 0xE0 + 0x20 + + + ST_PHY_ERRSOTSYNCHS_0 + NA + 0 + 1 + read-only + + + ST_PHY_ERRSOTSYNCHS_1 + NA + 1 + 1 + read-only + + + + + INT_MSK_PHY_FATAL + NA + 0xE4 + 0x20 + + + MASK_PHY_ERRSOTSYNCHS_0 + NA + 0 + 1 + read-write + + + MASK_PHY_ERRSOTSYNCHS_1 + NA + 1 + 1 + read-write + + + + + INT_FORCE_PHY_FATAL + NA + 0xE8 + 0x20 + + + FORCE_PHY_ERRSOTSYNCHS_0 + NA + 0 + 1 + read-write + + + FORCE_PHY_ERRSOTSYNCHS_1 + NA + 1 + 1 + read-write + + + + + INT_ST_PKT_FATAL + NA + 0xF0 + 0x20 + + + ST_ERR_ECC_DOUBLE + NA + 0 + 1 + read-only + + + ST_SHORTER_PAYLOAD + NA + 1 + 1 + read-only + + + + + INT_MSK_PKT_FATAL + NA + 0xF4 + 0x20 + + + MASK_ERR_ECC_DOUBLE + NA + 0 + 1 + read-write + + + MASK_SHORTER_PAYLOAD + NA + 1 + 1 + read-write + + + + + INT_FORCE_PKT_FATAL + NA + 0xF8 + 0x20 + + + FORCE_ERR_ECC_DOUBLE + NA + 0 + 1 + read-write + + + FORCE_SHORTER_PAYLOAD + NA + 1 + 1 + read-write + + + + + INT_ST_PHY + NA + 0x110 + 0x20 + + + ST_PHY_ERRSOTHS_0 + NA + 0 + 1 + read-only + + + ST_PHY_ERRSOTHS_1 + NA + 1 + 1 + read-only + + + ST_PHY_ERRESC_0 + NA + 16 + 1 + read-only + + + ST_PHY_ERRESC_1 + NA + 17 + 1 + read-only + + + + + INT_MSK_PHY + NA + 0x114 + 0x20 + + + MASK_PHY_ERRSOTHS_0 + NA + 0 + 1 + read-write + + + MASK_PHY_ERRSOTHS_1 + NA + 1 + 1 + read-write + + + MASK_PHY_ERRESC_0 + NA + 16 + 1 + read-write + + + MASK_PHY_ERRESC_1 + NA + 17 + 1 + read-write + + + + + INT_FORCE_PHY + NA + 0x118 + 0x20 + + + FORCE_PHY_ERRSOTHS_0 + NA + 0 + 1 + read-write + + + FORCE_PHY_ERRSOTHS_1 + NA + 1 + 1 + read-write + + + FORCE_PHY_ERRESC_0 + NA + 16 + 1 + read-write + + + FORCE_PHY_ERRESC_1 + NA + 17 + 1 + read-write + + + + + INT_ST_BNDRY_FRAME_FATAL + NA + 0x280 + 0x20 + + + ST_ERR_F_BNDRY_MATCH_VC0 + NA + 0 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC1 + NA + 1 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC2 + NA + 2 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC3 + NA + 3 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC4 + NA + 4 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC5 + NA + 5 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC6 + NA + 6 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC7 + NA + 7 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC8 + NA + 8 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC9 + NA + 9 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC10 + NA + 10 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC11 + NA + 11 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC12 + NA + 12 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC13 + NA + 13 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC14 + NA + 14 + 1 + read-only + + + ST_ERR_F_BNDRY_MATCH_VC15 + NA + 15 + 1 + read-only + + + + + INT_MSK_BNDRY_FRAME_FATAL + NA + 0x284 + 0x20 + + + MASK_ERR_F_BNDRY_MATCH_VC0 + NA + 0 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC1 + NA + 1 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC2 + NA + 2 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC3 + NA + 3 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC4 + NA + 4 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC5 + NA + 5 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC6 + NA + 6 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC7 + NA + 7 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC8 + NA + 8 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC9 + NA + 9 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC10 + NA + 10 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC11 + NA + 11 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC12 + NA + 12 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC13 + NA + 13 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC14 + NA + 14 + 1 + read-write + + + MASK_ERR_F_BNDRY_MATCH_VC15 + NA + 15 + 1 + read-write + + + + + INT_FORCE_BNDRY_FRAME_FATAL + NA + 0x288 + 0x20 + + + FORCE_ERR_F_BNDRY_MATCH_VC0 + NA + 0 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC1 + NA + 1 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC2 + NA + 2 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC3 + NA + 3 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC4 + NA + 4 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC5 + NA + 5 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC6 + NA + 6 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC7 + NA + 7 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC8 + NA + 8 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC9 + NA + 9 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC10 + NA + 10 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC11 + NA + 11 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC12 + NA + 12 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC13 + NA + 13 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC14 + NA + 14 + 1 + read-write + + + FORCE_ERR_F_BNDRY_MATCH_VC15 + NA + 15 + 1 + read-write + + + + + INT_ST_SEQ_FRAME_FATAL + NA + 0x290 + 0x20 + + + ST_ERR_F_SEQ_VC0 + NA + 0 + 1 + read-only + + + ST_ERR_F_SEQ_VC1 + NA + 1 + 1 + read-only + + + ST_ERR_F_SEQ_VC2 + NA + 2 + 1 + read-only + + + ST_ERR_F_SEQ_VC3 + NA + 3 + 1 + read-only + + + ST_ERR_F_SEQ_VC4 + NA + 4 + 1 + read-only + + + ST_ERR_F_SEQ_VC5 + NA + 5 + 1 + read-only + + + ST_ERR_F_SEQ_VC6 + NA + 6 + 1 + read-only + + + ST_ERR_F_SEQ_VC7 + NA + 7 + 1 + read-only + + + ST_ERR_F_SEQ_VC8 + NA + 8 + 1 + read-only + + + ST_ERR_F_SEQ_VC9 + NA + 9 + 1 + read-only + + + ST_ERR_F_SEQ_VC10 + NA + 10 + 1 + read-only + + + ST_ERR_F_SEQ_VC11 + NA + 11 + 1 + read-only + + + ST_ERR_F_SEQ_VC12 + NA + 12 + 1 + read-only + + + ST_ERR_F_SEQ_VC13 + NA + 13 + 1 + read-only + + + ST_ERR_F_SEQ_VC14 + NA + 14 + 1 + read-only + + + ST_ERR_F_SEQ_VC15 + NA + 15 + 1 + read-only + + + + + INT_MSK_SEQ_FRAME_FATAL + NA + 0x294 + 0x20 + + + MASK_ERR_F_SEQ_VC0 + NA + 0 + 1 + read-write + + + MASK_ERR_F_SEQ_VC1 + NA + 1 + 1 + read-write + + + MASK_ERR_F_SEQ_VC2 + NA + 2 + 1 + read-write + + + MASK_ERR_F_SEQ_VC3 + NA + 3 + 1 + read-write + + + MASK_ERR_F_SEQ_VC4 + NA + 4 + 1 + read-write + + + MASK_ERR_F_SEQ_VC5 + NA + 5 + 1 + read-write + + + MASK_ERR_F_SEQ_VC6 + NA + 6 + 1 + read-write + + + MASK_ERR_F_SEQ_VC7 + NA + 7 + 1 + read-write + + + MASK_ERR_F_SEQ_VC8 + NA + 8 + 1 + read-write + + + MASK_ERR_F_SEQ_VC9 + NA + 9 + 1 + read-write + + + MASK_ERR_F_SEQ_VC10 + NA + 10 + 1 + read-write + + + MASK_ERR_F_SEQ_VC11 + NA + 11 + 1 + read-write + + + MASK_ERR_F_SEQ_VC12 + NA + 12 + 1 + read-write + + + MASK_ERR_F_SEQ_VC13 + NA + 13 + 1 + read-write + + + MASK_ERR_F_SEQ_VC14 + NA + 14 + 1 + read-write + + + MASK_ERR_F_SEQ_VC15 + NA + 15 + 1 + read-write + + + + + INT_FORCE_SEQ_FRAME_FATAL + NA + 0x298 + 0x20 + + + FORCE_ERR_F_SEQ_VC0 + NA + 0 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC1 + NA + 1 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC2 + NA + 2 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC3 + NA + 3 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC4 + NA + 4 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC5 + NA + 5 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC6 + NA + 6 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC7 + NA + 7 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC8 + NA + 8 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC9 + NA + 9 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC10 + NA + 10 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC11 + NA + 11 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC12 + NA + 12 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC13 + NA + 13 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC14 + NA + 14 + 1 + read-write + + + FORCE_ERR_F_SEQ_VC15 + NA + 15 + 1 + read-write + + + + + INT_ST_CRC_FRAME_FATAL + NA + 0x2A0 + 0x20 + + + ST_ERR_FRAME_DATA_VC0 + NA + 0 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC1 + NA + 1 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC2 + NA + 2 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC3 + NA + 3 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC4 + NA + 4 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC5 + NA + 5 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC6 + NA + 6 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC7 + NA + 7 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC8 + NA + 8 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC9 + NA + 9 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC10 + NA + 10 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC11 + NA + 11 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC12 + NA + 12 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC13 + NA + 13 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC14 + NA + 14 + 1 + read-only + + + ST_ERR_FRAME_DATA_VC15 + NA + 15 + 1 + read-only + + + + + INT_MSK_CRC_FRAME_FATAL + NA + 0x2A4 + 0x20 + + + MASK_ERR_FRAME_DATA_VC0 + NA + 0 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC1 + NA + 1 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC2 + NA + 2 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC3 + NA + 3 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC4 + NA + 4 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC5 + NA + 5 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC6 + NA + 6 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC7 + NA + 7 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC8 + NA + 8 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC9 + NA + 9 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC10 + NA + 10 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC11 + NA + 11 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC12 + NA + 12 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC13 + NA + 13 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC14 + NA + 14 + 1 + read-write + + + MASK_ERR_FRAME_DATA_VC15 + NA + 15 + 1 + read-write + + + + + INT_FORCE_CRC_FRAME_FATAL + NA + 0x2A8 + 0x20 + + + FORCE_ERR_FRAME_DATA_VC0 + NA + 0 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC1 + NA + 1 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC2 + NA + 2 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC3 + NA + 3 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC4 + NA + 4 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC5 + NA + 5 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC6 + NA + 6 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC7 + NA + 7 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC8 + NA + 8 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC9 + NA + 9 + 1 + read-write + + + FORCE_ERR_FRAME_DATA_VC10 + NA + 10 + 1 + read-write + + + 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CH4_ENABLE_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + read-write + + + CH4_ENABLE_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + read-write + + + CH4_ENABLE_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + read-write + + + CH4_ENABLE_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + read-write + + + CH4_ENABLE_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + read-write + + + CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + read-write + + + CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + read-write + + + CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + read-write + + + CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + read-write + + + CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + read-write + + + CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + read-write + + + CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + read-write + + + CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + read-write + + + CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + read-write + + + CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + read-only + + + CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + read-write + + + CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + read-write + + + CH4_ENABLE_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + read-write + + + CH4_ENABLE_CH_DISABLED_INTSTAT + NA + 30 + 1 + read-write + + + CH4_ENABLE_CH_ABORTED_INTSTAT + NA + 31 + 1 + read-write + + + + + CH4_INTSTATUS_ENABLE1 + NA + 0x484 + 0x20 + 0x0000000F + + + CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + read-only + + + + + CH4_INTSTATUS0 + NA + 0x488 + 0x20 + + + CH4_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + read-only + + + CH4_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + read-only + + + CH4_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + read-only + + + CH4_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + read-only + + + CH4_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + read-only + + + CH4_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + read-only + + + CH4_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + read-only + + + CH4_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + read-only + + + CH4_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + read-only + + + CH4_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + read-only + + + CH4_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + read-only + + + CH4_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + read-only + + + CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + read-only + + + CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + read-only + + + CH4_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + read-only + + + CH4_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + read-only + + + CH4_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + read-only + + + CH4_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + read-only + + + CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + read-only + + + CH4_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + read-only + + + CH4_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + read-only + + + CH4_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + read-only + + + CH4_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + read-only + + + CH4_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + read-only + + + CH4_CH_DISABLED_INTSTAT + NA + 30 + 1 + read-only + + + CH4_CH_ABORTED_INTSTAT + NA + 31 + 1 + read-only + + + + + CH4_INTSTATUS1 + NA + 0x48C + 0x20 + + + CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + read-only + + + CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + read-only + + + CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + read-only + + + CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + read-only + + + + + CH4_INTSIGNAL_ENABLE0 + NA + 0x490 + 0x20 + 0xFA3F7FFB + + + CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL + NA + 0 + 1 + read-write + + + CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL + NA + 1 + 1 + read-write + + + CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL + NA + 3 + 1 + read-write + + + CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL + NA + 4 + 1 + read-write + + + CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL + NA + 5 + 1 + read-write + + + CH4_ENABLE_DST_DEC_ERR_INTSIGNAL + NA + 6 + 1 + read-write + + + CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL + NA + 7 + 1 + read-write + + + CH4_ENABLE_DST_SLV_ERR_INTSIGNAL + NA + 8 + 1 + read-write + + + CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL + NA + 9 + 1 + read-write + + + CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL + NA + 10 + 1 + read-write + + + CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL + NA + 11 + 1 + read-write + + + CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL + NA + 12 + 1 + read-write + + + CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL + NA + 13 + 1 + read-write + + + CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL + NA + 14 + 1 + read-write + + + CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL + NA + 16 + 1 + read-write + + + CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL + NA + 17 + 1 + read-write + + + CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL + NA + 18 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL + NA + 19 + 1 + read-write + + + CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL + NA + 20 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL + NA + 21 + 1 + read-write + + + CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL + NA + 25 + 1 + read-only + + + CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL + NA + 27 + 1 + read-write + + + CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL + NA + 28 + 1 + read-write + + + CH4_ENABLE_CH_SUSPENDED_INTSIGNAL + NA + 29 + 1 + read-write + + + CH4_ENABLE_CH_DISABLED_INTSIGNAL + NA + 30 + 1 + read-write + + + CH4_ENABLE_CH_ABORTED_INTSIGNAL + NA + 31 + 1 + read-write + + + + + CH4_INTSIGNAL_ENABLE1 + NA + 0x494 + 0x20 + 0x0000000F + + + CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL + NA + 0 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL + NA + 1 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL + NA + 2 + 1 + read-only + + + CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL + NA + 3 + 1 + read-only + + + + + CH4_INTCLEAR0 + NA + 0x498 + 0x20 + + + CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT + NA + 0 + 1 + write-only + + + CH4_CLEAR_DMA_TFR_DONE_INTSTAT + NA + 1 + 1 + write-only + + + CH4_CLEAR_SRC_TRANSCOMP_INTSTAT + NA + 3 + 1 + write-only + + + CH4_CLEAR_DST_TRANSCOMP_INTSTAT + NA + 4 + 1 + write-only + + + CH4_CLEAR_SRC_DEC_ERR_INTSTAT + NA + 5 + 1 + write-only + + + CH4_CLEAR_DST_DEC_ERR_INTSTAT + NA + 6 + 1 + write-only + + + CH4_CLEAR_SRC_SLV_ERR_INTSTAT + NA + 7 + 1 + write-only + + + CH4_CLEAR_DST_SLV_ERR_INTSTAT + NA + 8 + 1 + write-only + + + CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT + NA + 9 + 1 + write-only + + + CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT + NA + 10 + 1 + write-only + + + CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT + NA + 11 + 1 + write-only + + + CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT + NA + 12 + 1 + write-only + + + CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT + NA + 13 + 1 + write-only + + + CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT + NA + 14 + 1 + write-only + + + CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT + NA + 16 + 1 + write-only + + + CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT + NA + 17 + 1 + write-only + + + CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT + NA + 18 + 1 + write-only + + + CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT + NA + 19 + 1 + write-only + + + CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT + NA + 20 + 1 + write-only + + + CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT + NA + 21 + 1 + write-only + + + CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT + NA + 25 + 1 + write-only + + + CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT + NA + 27 + 1 + write-only + + + CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT + NA + 28 + 1 + write-only + + + CH4_CLEAR_CH_SUSPENDED_INTSTAT + NA + 29 + 1 + write-only + + + CH4_CLEAR_CH_DISABLED_INTSTAT + NA + 30 + 1 + write-only + + + CH4_CLEAR_CH_ABORTED_INTSTAT + NA + 31 + 1 + write-only + + + + + CH4_INTCLEAR1 + NA + 0x49C + 0x20 + + + CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT + NA + 0 + 1 + write-only + + + CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT + NA + 1 + 1 + write-only + + + CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT + NA + 2 + 1 + write-only + + + CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT + NA + 3 + 1 + write-only + + + + + + + DS + Digital Signature + DS + 0x50094000 + + 0x0 + 0xA5C + registers + + + + 512 + 0x1 + Y_MEM[%s] + memory that stores Y + 0x0 + 0x8 + + + 512 + 0x1 + M_MEM[%s] + memory that stores M + 0x200 + 0x8 + + + 512 + 0x1 + RB_MEM[%s] + memory that stores Rb + 0x400 + 0x8 + + + 48 + 0x1 + BOX_MEM[%s] + memory that stores BOX + 0x600 + 0x8 + + + 16 + 0x1 + IV_MEM[%s] + memory that stores IV + 0x630 + 0x8 + + + 512 + 0x1 + X_MEM[%s] + memory that stores X + 0x800 + 0x8 + + + 512 + 0x1 + Z_MEM[%s] + memory that stores Z + 0xA00 + 0x8 + + + SET_START + DS start control register + 0xE00 + 0x20 + + + SET_START + set this bit to start DS operation. + 0 + 1 + write-only + + + + + SET_CONTINUE + DS continue control register + 0xE04 + 0x20 + + + SET_CONTINUE + set this bit to continue DS operation. + 0 + 1 + write-only + + + + + SET_FINISH + DS finish control register + 0xE08 + 0x20 + + + SET_FINISH + Set this bit to finish DS process. + 0 + 1 + write-only + + + + + QUERY_BUSY + DS query busy register + 0xE0C + 0x20 + + + QUERY_BUSY + digital signature state. 1'b0: idle, 1'b1: busy + 0 + 1 + read-only + + + + + QUERY_KEY_WRONG + DS query key-wrong counter register + 0xE10 + 0x20 + + + QUERY_KEY_WRONG + digital signature key wrong counter + 0 + 4 + read-only + + + + + QUERY_CHECK + DS query check result register + 0xE14 + 0x20 + + + MD_ERROR + MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail + 0 + 1 + read-only + + + PADDING_BAD + padding checkout result. 1'b0: a good padding, 1'b1: a bad padding + 1 + 1 + read-only + + + + + DATE + DS version control register + 0xE20 + 0x20 + 0x20200618 + + + DATE + ds version information + 0 + 30 + read-write + + + + + + + MIPI_DSI_BRIDGE + MIPI Camera Interface Bridge + DSI_BRG + 0x500A0800 + + 0x0 + 0x94 + registers + + + DSI_BRIDGE + 86 + + + + CLK_EN + dsi bridge clk control register + 0x0 + 0x20 + + + CLK_EN + this bit configures force_on of dsi_bridge register clock gate + 0 + 1 + read-write + + + + + EN + dsi bridge en register + 0x4 + 0x20 + + + DSI_EN + this bit configures module enable of dsi_bridge. 0: disable, 1: enable + 0 + 1 + read-write + + + + + DMA_REQ_CFG + dsi bridge dma burst len register + 0x8 + 0x20 + 0x00000080 + + + DMA_BURST_LEN + this field configures the num of 64-bit in one dma burst transfer, valid only when dsi_bridge as flow controller + 0 + 12 + read-write + + + + + RAW_NUM_CFG + dsi bridge raw number control register + 0xC + 0x20 + 0x00038400 + + + RAW_NUM_TOTAL + this field configures number of total pix bits/64 + 0 + 22 + read-write + + + UNALIGN_64BIT_EN + this field configures whether the total pix bits is a multiple of 64bits. 0: align to 64-bit, 1: unalign to 64-bit + 22 + 1 + read-write + + + RAW_NUM_TOTAL_SET + this bit configures enable of reload reg_raw_num_total to internal cnt. 0: disable, 1: enable. valid only when dsi_bridge as flow controller + 31 + 1 + write-only + + + + + RAW_BUF_CREDIT_CTL + dsi bridge credit register + 0x10 + 0x20 + 0x03200400 + + + CREDIT_THRD + this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller + 0 + 15 + read-write + + + CREDIT_BURST_THRD + this field configures the threshold whether dsi_bridge fifo can receive one more dma burst, valid only when dsi_bridge as flow controller + 16 + 15 + read-write + + + CREDIT_RESET + this bit configures internal credit cnt clear, 0: non, 1: reset. valid only when dsi_bridge as flow controller + 31 + 1 + read-write + + + + + FIFO_FLOW_STATUS + dsi bridge raw buffer depth register + 0x14 + 0x20 + + + RAW_BUF_DEPTH + this field configures the depth of dsi_bridge fifo depth + 0 + 14 + read-only + + + + + PIXEL_TYPE + dsi bridge dpi type control register + 0x18 + 0x20 + + + RAW_TYPE + this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565 + 0 + 4 + read-write + + + DPI_CONFIG + this field configures the pixel arrange type of dpi interface + 4 + 2 + read-write + + + DATA_IN_TYPE + input data type, 0: rgb, 1: yuv + 6 + 1 + read-write + + + + + DMA_BLOCK_INTERVAL + dsi bridge dma block interval control register + 0x1C + 0x20 + 0x30002409 + + + DMA_BLOCK_SLOT + this field configures the max block_slot_cnt + 0 + 10 + read-write + + + DMA_BLOCK_INTERVAL + this field configures the max block_interval_cnt, block_interval_cnt increased by 1 when block_slot_cnt if full + 10 + 18 + read-write + + + RAW_NUM_TOTAL_AUTO_RELOAD + this bit configures enable of auto reload reg_raw_num_total, 0: disable, 1: enable + 28 + 1 + read-write + + + EN + this bit configures enable of interval between dma block transfer, 0: disable, 1: enable + 29 + 1 + read-write + + + + + DMA_REQ_INTERVAL + dsi bridge dma req interval control register + 0x20 + 0x20 + 0x00000001 + + + DMA_REQ_INTERVAL + this field configures the interval between dma req events + 0 + 16 + read-write + + + + + DPI_LCD_CTL + dsi bridge dpi signal control register + 0x24 + 0x20 + + + DPISHUTDN + this bit configures dpishutdn signal in dpi interface + 0 + 1 + read-write + + + DPICOLORM + this bit configures dpicolorm signal in dpi interface + 1 + 1 + read-write + + + DPIUPDATECFG + this bit configures dpiupdatecfg signal in dpi interface + 2 + 1 + read-write + + + + + DPI_RSV_DPI_DATA + dsi bridge dpi reserved data register + 0x28 + 0x20 + 0x00003FFF + + + DPI_RSV_DATA + this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow + 0 + 30 + read-write + + + + + DPI_V_CFG0 + dsi bridge dpi v config register 0 + 0x30 + 0x20 + 0x01E0020D + + + VTOTAL + this field configures the total length of one frame (by line) for dpi output, must meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank + 0 + 12 + read-write + + + VDISP + this field configures the length of valid line (by line) for dpi output + 16 + 12 + read-write + + + + + DPI_V_CFG1 + dsi bridge dpi v config register 1 + 0x34 + 0x20 + 0x00020021 + + + VBANK + this field configures the length between vsync and valid line (by line) for dpi output + 0 + 12 + read-write + + + VSYNC + this field configures the length of vsync (by line) for dpi output + 16 + 12 + read-write + + + + + DPI_H_CFG0 + dsi bridge dpi h config register 0 + 0x38 + 0x20 + 0x02800320 + + + HTOTAL + this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank + 0 + 12 + read-write + + + HDISP + this field configures the length of valid pixel data (by pixel num) for dpi output + 16 + 12 + read-write + + + + + DPI_H_CFG1 + dsi bridge dpi h config register 1 + 0x3C + 0x20 + 0x00600030 + + + HBANK + this field configures the length between hsync and pixel data valid (by pixel num) for dpi output + 0 + 12 + read-write + + + HSYNC + this field configures the length of hsync (by pixel num) for dpi output + 16 + 12 + read-write + + + + + DPI_MISC_CONFIG + dsi_bridge dpi misc config register + 0x40 + 0x20 + 0x000019D0 + + + DPI_EN + this bit configures enable of dpi output, 0: disable, 1: enable + 0 + 1 + read-write + + + FIFO_UNDERRUN_DISCARD_VCNT + this field configures the underrun interrupt musk, when underrun occurs and line cnt is less then this field + 4 + 12 + read-write + + + + + DPI_CONFIG_UPDATE + dsi_bridge dpi config update register + 0x44 + 0x20 + + + DPI_CONFIG_UPDATE + write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* + 0 + 1 + write-only + + + + + INT_ENA + dsi_bridge interrupt enable register + 0x50 + 0x20 + + + UNDERRUN_INT_ENA + write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal + 0 + 1 + read-write + + + + + INT_CLR + dsi_bridge interrupt clear register + 0x54 + 0x20 + + + UNDERRUN_INT_CLR + write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + 0 + 1 + write-only + + + + + INT_RAW + dsi_bridge raw interrupt register + 0x58 + 0x20 + + + UNDERRUN_INT_RAW + the raw interrupt status of dpi_underrun + 0 + 1 + read-write + + + + + INT_ST + dsi_bridge masked interrupt register + 0x5C + 0x20 + + + UNDERRUN_INT_ST + the masked interrupt status of dpi_underrun + 0 + 1 + read-only + + + + + HOST_BIST_CTL + dsi_bridge host bist control register + 0x60 + 0x20 + + + BISTOK + bistok + 0 + 1 + read-only + + + BISTON + biston + 1 + 1 + read-write + + + + + HOST_TRIGGER_REV + dsi_bridge host trigger reverse control register + 0x64 + 0x20 + + + TX_TRIGGER_REV_EN + tx_trigger reverse. 0: disable, 1: enable + 0 + 1 + read-write + + + RX_TRIGGER_REV_EN + rx_trigger reverse. 0: disable, 1: enable + 1 + 1 + read-write + + + + + BLK_RAW_NUM_CFG + dsi_bridge block raw number control register + 0x68 + 0x20 + 0x00038400 + + + BLK_RAW_NUM_TOTAL + this field configures number of total block pix bits/64 + 0 + 22 + read-write + + + BLK_RAW_NUM_TOTAL_SET + write 1 to reload reg_blk_raw_num_total to internal cnt + 31 + 1 + write-only + + + + + DMA_FRAME_INTERVAL + dsi_bridge dam frame interval control register + 0x6C + 0x20 + 0x20002409 + + + DMA_FRAME_SLOT + this field configures the max frame_slot_cnt + 0 + 10 + read-write + + + DMA_FRAME_INTERVAL + this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full + 10 + 18 + read-write + + + DMA_MULTIBLK_EN + this bit configures enable multi-blk transfer, 0: disable, 1: enable + 28 + 1 + read-write + + + EN + this bit configures enable interval between frame transfer, 0: disable, 1: enable + 29 + 1 + read-write + + + + + MEM_AUX_CTRL + dsi_bridge mem aux control register + 0x70 + 0x20 + 0x00001320 + + + DSI_MEM_AUX_CTRL + this field configures dsi_bridge fifo memory aux ctrl + 0 + 14 + read-write + + + + + RDN_ECO_CS + dsi_bridge rdn eco cs register + 0x74 + 0x20 + + + RDN_ECO_EN + rdn_eco_en + 0 + 1 + read-write + + + RDN_ECO_RESULT + rdn_eco_result + 1 + 1 + read-only + + + + + RDN_ECO_LOW + dsi_bridge rdn eco all low register + 0x78 + 0x20 + + + RDN_ECO_LOW + rdn_eco_low + 0 + 32 + read-write + + + + + RDN_ECO_HIGH + dsi_bridge rdn eco all high register + 0x7C + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + rdn_eco_high + 0 + 32 + read-write + + + + + HOST_CTRL + dsi_bridge host control register + 0x80 + 0x20 + 0x00000001 + + + DSI_CFG_REF_CLK_EN + this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable + 0 + 1 + read-write + + + + + MEM_CLK_CTRL + dsi_bridge mem force on control register + 0x84 + 0x20 + + + DSI_BRIDGE_MEM_CLK_FORCE_ON + this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on + 0 + 1 + read-write + + + DSI_MEM_CLK_FORCE_ON + this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on + 1 + 1 + read-write + + + + + DMA_FLOW_CTRL + dsi_bridge dma flow controller register + 0x88 + 0x20 + 0x00000011 + + + DSI_DMA_FLOW_CONTROLLER + this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller + 0 + 1 + read-write + + + DMA_FLOW_MULTIBLK_NUM + this field configures the num of blocks when multi-blk is enable and dmac as flow controller + 4 + 4 + read-write + + + + + RAW_BUF_ALMOST_EMPTY_THRD + dsi_bridge buffer empty threshold register + 0x8C + 0x20 + 0x00000200 + + + DSI_RAW_BUF_ALMOST_EMPTY_THRD + this field configures the fifo almost empty threshold, is valid only when dmac as flow controller + 0 + 11 + read-write + + + + + YUV_CFG + dsi_bridge yuv format config register + 0x90 + 0x20 + + + PROTOCAL + this bit configures yuv protoocl, 0: bt.601, 1: bt.709 + 0 + 1 + read-write + + + YUV_PIX_ENDIAN + this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0 + 1 + 1 + read-write + + + YUV422_FORMAT + this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy + 2 + 2 + read-write + + + + + PHY_LP_LOOPBACK_CTRL + dsi phy lp_loopback test ctrl + 0x94 + 0x20 + + + PHY_LP_TXDATAESC_1 + txdataesc_1 ctrl when enable dsi phy lp_loopback_test + 0 + 8 + read-write + + + PHY_LP_TXREQUESTESC_1 + txrequestesc_1 ctrl when enable dsi phy lp_loopback_test + 8 + 1 + read-write + + + PHY_LP_TXVALIDESC_1 + txvalidesc_1 ctrl when enable dsi phy lp_loopback_test + 9 + 1 + read-write + + + PHY_LP_TXLPDTESC_1 + txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test + 10 + 1 + read-write + + + PHY_LP_BASEDIR_1 + basedir_1 ctrl when enable dsi phy lp_loopback_test + 11 + 1 + read-write + + + PHY_LP_TXDATAESC_0 + txdataesc_0 ctrl when enable dsi phy lp_loopback_test + 16 + 8 + read-write + + + PHY_LP_TXREQUESTESC_0 + txrequestesc_0 ctrl when enable dsi phy lp_loopback_test + 24 + 1 + read-write + + + PHY_LP_TXVALIDESC_0 + txvalidesc_0 ctrl when enable dsi phy lp_loopback_test + 25 + 1 + read-write + + + PHY_LP_TXLPDTESC_0 + txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test + 26 + 1 + read-write + + + PHY_LP_BASEDIR_0 + basedir_0 ctrl when enable dsi phy lp_loopback_test + 27 + 1 + read-write + + + PHY_LP_LOOPBACK_CHECK + dsi phy lp_loopback test start check + 28 + 1 + write-only + + + PHY_LP_LOOPBACK_CHECK_DONE + dsi phy lp_loopback test check done + 29 + 1 + read-only + + + PHY_LP_LOOPBACK_EN + dsi phy lp_loopback ctrl en + 30 + 1 + read-write + + + PHY_LP_LOOPBACK_OK + result of dsi phy lp_loopback test + 31 + 1 + read-only + + + + + PHY_HS_LOOPBACK_CTRL + dsi phy hp_loopback test ctrl + 0x98 + 0x20 + 0x00000200 + + + PHY_HS_TXDATAHS_1 + txdatahs_1 ctrl when enable dsi phy hs_loopback_test + 0 + 8 + read-write + + + PHY_HS_TXREQUESTDATAHS_1 + txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test + 8 + 1 + read-write + + + PHY_HS_BASEDIR_1 + basedir_1 ctrl when enable dsi phy hs_loopback_test + 9 + 1 + read-write + + + PHY_HS_TXDATAHS_0 + txdatahs_0 ctrl when enable dsi phy hs_loopback_test + 16 + 8 + read-write + + + PHY_HS_TXREQUESTDATAHS_0 + txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test + 24 + 1 + read-write + + + PHY_HS_BASEDIR_0 + basedir_0 ctrl when enable dsi phy hs_loopback_test + 25 + 1 + read-write + + + PHY_HS_TXREQUESTHSCLK + txrequesthsclk when enable dsi phy hs_loopback_test + 27 + 1 + read-write + + + PHY_HS_LOOPBACK_CHECK + dsi phy hs_loopback test start check + 28 + 1 + write-only + + + PHY_HS_LOOPBACK_CHECK_DONE + dsi phy hs_loopback test check done + 29 + 1 + read-only + + + PHY_HS_LOOPBACK_EN + dsi phy hs_loopback ctrl en + 30 + 1 + read-write + + + PHY_HS_LOOPBACK_OK + result of dsi phy hs_loopback test + 31 + 1 + read-only + + + + + PHY_LOOPBACK_CNT + loopback test cnt + 0x9C + 0x20 + 0x00400040 + + + PHY_HS_CHECK_CNT_TH + hs_loopback test check cnt + 0 + 8 + read-write + + + PHY_LP_CHECK_CNT_TH + lp_loopback test check cnt + 16 + 8 + read-write + + + + + + + MIPI_DSI_HOST + MIPI Display Interface Host + DSI_HOST + 0x500A0000 + + 0x0 + 0x128 + registers + + + DSI + 88 + + + + VERSION + NA + 0x0 + 0x20 + 0x3134312A + + + VERSION + NA + 0 + 32 + read-only + + + + + PWR_UP + NA + 0x4 + 0x20 + + + SHUTDOWNZ + NA + 0 + 1 + read-write + + + + + CLKMGR_CFG + NA + 0x8 + 0x20 + + + TX_ESC_CLK_DIVISION + NA + 0 + 8 + read-write + + + TO_CLK_DIVISION + NA + 8 + 8 + read-write + + + + + DPI_VCID + NA + 0xC + 0x20 + + + DPI_VCID + NA + 0 + 2 + read-write + + + + + DPI_COLOR_CODING + NA + 0x10 + 0x20 + + + DPI_COLOR_CODING + NA + 0 + 4 + read-write + + + LOOSELY18_EN + NA + 8 + 1 + read-write + + + + + DPI_CFG_POL + NA + 0x14 + 0x20 + + + DATAEN_ACTIVE_LOW + NA + 0 + 1 + read-write + + + VSYNC_ACTIVE_LOW + NA + 1 + 1 + read-write + + + HSYNC_ACTIVE_LOW + NA + 2 + 1 + read-write + + + SHUTD_ACTIVE_LOW + NA + 3 + 1 + read-write + + + COLORM_ACTIVE_LOW + NA + 4 + 1 + read-write + + + + + DPI_LP_CMD_TIM + NA + 0x18 + 0x20 + + + INVACT_LPCMD_TIME + NA + 0 + 8 + read-write + + + OUTVACT_LPCMD_TIME + NA + 16 + 8 + read-write + + + + + DBI_VCID + NA + 0x1C + 0x20 + + + DBI_VCID + NA + 0 + 2 + read-write + + + + + DBI_CFG + NA + 0x20 + 0x20 + + + IN_DBI_CONF + NA + 0 + 4 + read-write + + + OUT_DBI_CONF + NA + 8 + 4 + read-write + + + LUT_SIZE_CONF + NA + 16 + 2 + read-write + + + + + DBI_PARTITIONING_EN + NA + 0x24 + 0x20 + + + PARTITIONING_EN + NA + 0 + 1 + read-write + + + + + DBI_CMDSIZE + NA + 0x28 + 0x20 + + + WR_CMD_SIZE + NA + 0 + 16 + read-write + + + ALLOWED_CMD_SIZE + NA + 16 + 16 + read-write + + + + + PCKHDL_CFG + NA + 0x2C + 0x20 + + + EOTP_TX_EN + NA + 0 + 1 + read-write + + + EOTP_RX_EN + NA + 1 + 1 + read-write + + + BTA_EN + NA + 2 + 1 + read-write + + + ECC_RX_EN + NA + 3 + 1 + read-write + + + CRC_RX_EN + NA + 4 + 1 + read-write + + + EOTP_TX_LP_EN + NA + 5 + 1 + read-write + + + + + GEN_VCID + NA + 0x30 + 0x20 + + + RX + NA + 0 + 2 + read-write + + + TEAR_AUTO + NA + 8 + 2 + read-write + + + TX_AUTO + NA + 16 + 2 + read-write + + + + + MODE_CFG + NA + 0x34 + 0x20 + 0x00000001 + + + CMD_VIDEO_MODE + NA + 0 + 1 + read-write + + + + + VID_MODE_CFG + NA + 0x38 + 0x20 + + + VID_MODE_TYPE + NA + 0 + 2 + read-write + + + LP_VSA_EN + NA + 8 + 1 + read-write + + + LP_VBP_EN + NA + 9 + 1 + read-write + + + LP_VFP_EN + NA + 10 + 1 + read-write + + + LP_VACT_EN + NA + 11 + 1 + read-write + + + LP_HBP_EN + NA + 12 + 1 + read-write + + + LP_HFP_EN + NA + 13 + 1 + read-write + + + FRAME_BTA_ACK_EN + NA + 14 + 1 + read-write + + + LP_CMD_EN + NA + 15 + 1 + read-write + + + VPG_EN + NA + 16 + 1 + read-write + + + VPG_MODE + NA + 20 + 1 + read-write + + + VPG_ORIENTATION + NA + 24 + 1 + read-write + + + + + VID_PKT_SIZE + NA + 0x3C + 0x20 + + + VID_PKT_SIZE + NA + 0 + 14 + read-write + + + + + VID_NUM_CHUNKS + NA + 0x40 + 0x20 + + + VID_NUM_CHUNKS + NA + 0 + 13 + read-write + + + + + VID_NULL_SIZE + NA + 0x44 + 0x20 + + + VID_NULL_SIZE + NA + 0 + 13 + read-write + + + + + VID_HSA_TIME + NA + 0x48 + 0x20 + + + VID_HSA_TIME + NA + 0 + 12 + read-write + + + + + VID_HBP_TIME + NA + 0x4C + 0x20 + + + VID_HBP_TIME + NA + 0 + 12 + read-write + + + + + VID_HLINE_TIME + NA + 0x50 + 0x20 + + + VID_HLINE_TIME + NA + 0 + 15 + read-write + + + + + VID_VSA_LINES + NA + 0x54 + 0x20 + + + VSA_LINES + NA + 0 + 10 + read-write + + + + + VID_VBP_LINES + NA + 0x58 + 0x20 + + + VBP_LINES + NA + 0 + 10 + read-write + + + + + VID_VFP_LINES + NA + 0x5C + 0x20 + + + VFP_LINES + NA + 0 + 10 + read-write + + + + + VID_VACTIVE_LINES + NA + 0x60 + 0x20 + + + V_ACTIVE_LINES + NA + 0 + 14 + read-write + + + + + EDPI_CMD_SIZE + NA + 0x64 + 0x20 + + + EDPI_ALLOWED_CMD_SIZE + NA + 0 + 16 + read-write + + + + + CMD_MODE_CFG + NA + 0x68 + 0x20 + + + TEAR_FX_EN + NA + 0 + 1 + read-write + + + ACK_RQST_EN + NA + 1 + 1 + read-write + + + GEN_SW_0P_TX + NA + 8 + 1 + read-write + + + GEN_SW_1P_TX + NA + 9 + 1 + read-write + + + GEN_SW_2P_TX + NA + 10 + 1 + read-write + + + GEN_SR_0P_TX + NA + 11 + 1 + read-write + + + GEN_SR_1P_TX + NA + 12 + 1 + read-write + + + GEN_SR_2P_TX + NA + 13 + 1 + read-write + + + GEN_LW_TX + NA + 14 + 1 + read-write + + + DCS_SW_0P_TX + NA + 16 + 1 + read-write + + + DCS_SW_1P_TX + NA + 17 + 1 + read-write + + + DCS_SR_0P_TX + NA + 18 + 1 + read-write + + + DCS_LW_TX + NA + 19 + 1 + read-write + + + MAX_RD_PKT_SIZE + NA + 24 + 1 + read-write + + + + + GEN_HDR + NA + 0x6C + 0x20 + + + GEN_DT + NA + 0 + 6 + read-write + + + GEN_VC + NA + 6 + 2 + read-write + + + GEN_WC_LSBYTE + NA + 8 + 8 + read-write + + + GEN_WC_MSBYTE + NA + 16 + 8 + read-write + + + + + GEN_PLD_DATA + NA + 0x70 + 0x20 + + + GEN_PLD_B1 + NA + 0 + 8 + read-write + + + GEN_PLD_B2 + NA + 8 + 8 + read-write + + + GEN_PLD_B3 + NA + 16 + 8 + read-write + + + GEN_PLD_B4 + NA + 24 + 8 + read-write + + + + + CMD_PKT_STATUS + NA + 0x74 + 0x20 + 0x00050015 + + + GEN_CMD_EMPTY + NA + 0 + 1 + read-only + + + GEN_CMD_FULL + NA + 1 + 1 + read-only + + + GEN_PLD_W_EMPTY + NA + 2 + 1 + read-only + + + GEN_PLD_W_FULL + NA + 3 + 1 + read-only + + + GEN_PLD_R_EMPTY + NA + 4 + 1 + read-only + + + GEN_PLD_R_FULL + NA + 5 + 1 + read-only + + + GEN_RD_CMD_BUSY + NA + 6 + 1 + read-only + + + GEN_BUFF_CMD_EMPTY + NA + 16 + 1 + read-only + + + GEN_BUFF_CMD_FULL + NA + 17 + 1 + read-only + + + GEN_BUFF_PLD_EMPTY + NA + 18 + 1 + read-only + + + GEN_BUFF_PLD_FULL + NA + 19 + 1 + read-only + + + + + TO_CNT_CFG + NA + 0x78 + 0x20 + + + LPRX_TO_CNT + NA + 0 + 16 + read-write + + + HSTX_TO_CNT + NA + 16 + 16 + read-write + + + + + HS_RD_TO_CNT + NA + 0x7C + 0x20 + + + HS_RD_TO_CNT + NA + 0 + 16 + read-write + + + + + LP_RD_TO_CNT + NA + 0x80 + 0x20 + + + LP_RD_TO_CNT + NA + 0 + 16 + read-write + + + + + HS_WR_TO_CNT + NA + 0x84 + 0x20 + + + HS_WR_TO_CNT + NA + 0 + 16 + read-write + + + + + LP_WR_TO_CNT + NA + 0x88 + 0x20 + + + LP_WR_TO_CNT + NA + 0 + 16 + read-write + + + + + BTA_TO_CNT + NA + 0x8C + 0x20 + + + BTA_TO_CNT + NA + 0 + 16 + read-write + + + + + SDF_3D + NA + 0x90 + 0x20 + + + MODE_3D + NA + 0 + 2 + read-write + + + FORMAT_3D + NA + 2 + 2 + read-write + + + SECOND_VSYNC + NA + 4 + 1 + read-write + + + RIGHT_FIRST + NA + 5 + 1 + read-write + + + SEND_3D_CFG + NA + 16 + 1 + read-write + + + + + LPCLK_CTRL + NA + 0x94 + 0x20 + + + PHY_TXREQUESTCLKHS + NA + 0 + 1 + read-write + + + AUTO_CLKLANE_CTRL + NA + 1 + 1 + read-write + + + + + PHY_TMR_LPCLK_CFG + NA + 0x98 + 0x20 + + + PHY_CLKLP2HS_TIME + NA + 0 + 10 + read-write + + + PHY_CLKHS2LP_TIME + NA + 16 + 10 + read-write + + + + + PHY_TMR_CFG + NA + 0x9C + 0x20 + + + PHY_LP2HS_TIME + NA + 0 + 10 + read-write + + + PHY_HS2LP_TIME + NA + 16 + 10 + read-write + + + + + PHY_RSTZ + NA + 0xA0 + 0x20 + + + PHY_SHUTDOWNZ + NA + 0 + 1 + read-write + + + PHY_RSTZ + NA + 1 + 1 + read-write + + + PHY_ENABLECLK + NA + 2 + 1 + read-write + + + PHY_FORCEPLL + NA + 3 + 1 + read-write + + + + + PHY_IF_CFG + NA + 0xA4 + 0x20 + 0x00000001 + + + N_LANES + NA + 0 + 2 + read-write + + + PHY_STOP_WAIT_TIME + NA + 8 + 8 + read-write + + + + + PHY_ULPS_CTRL + NA + 0xA8 + 0x20 + + + PHY_TXREQULPSCLK + NA + 0 + 1 + read-write + + + PHY_TXEXITULPSCLK + NA + 1 + 1 + read-write + + + PHY_TXREQULPSLAN + NA + 2 + 1 + read-write + + + PHY_TXEXITULPSLAN + NA + 3 + 1 + read-write + + + + + PHY_TX_TRIGGERS + NA + 0xAC + 0x20 + + + PHY_TX_TRIGGERS + NA + 0 + 4 + read-write + + + + + PHY_STATUS + NA + 0xB0 + 0x20 + 0x00000140 + + + PHY_LOCK + NA + 0 + 1 + read-only + + + PHY_DIRECTION + NA + 1 + 1 + read-only + + + PHY_STOPSTATECLKLANE + NA + 2 + 1 + read-only + + + PHY_ULPSACTIVENOTCLK + NA + 3 + 1 + read-only + + + PHY_STOPSTATE0LANE + NA + 4 + 1 + read-only + + + PHY_ULPSACTIVENOT0LANE + NA + 5 + 1 + read-only + + + PHY_RXULPSESC0LANE + NA + 6 + 1 + read-only + + + PHY_STOPSTATE1LANE + NA + 7 + 1 + read-only + + + PHY_ULPSACTIVENOT1LANE + NA + 8 + 1 + read-only + + + + + PHY_TST_CTRL0 + NA + 0xB4 + 0x20 + 0x00000001 + + + PHY_TESTCLR + NA + 0 + 1 + read-write + + + PHY_TESTCLK + NA + 1 + 1 + read-write + + + + + PHY_TST_CTRL1 + NA + 0xB8 + 0x20 + + + PHY_TESTDIN + NA + 0 + 8 + read-write + + + PHT_TESTDOUT + NA + 8 + 8 + read-only + + + PHY_TESTEN + NA + 16 + 1 + read-write + + + + + INT_ST0 + NA + 0xBC + 0x20 + + + ACK_WITH_ERR_0 + NA + 0 + 1 + read-only + + + ACK_WITH_ERR_1 + NA + 1 + 1 + read-only + + + ACK_WITH_ERR_2 + NA + 2 + 1 + read-only + + + ACK_WITH_ERR_3 + NA + 3 + 1 + read-only + + + ACK_WITH_ERR_4 + NA + 4 + 1 + read-only + + + ACK_WITH_ERR_5 + NA + 5 + 1 + read-only + + + ACK_WITH_ERR_6 + NA + 6 + 1 + read-only + + + ACK_WITH_ERR_7 + NA + 7 + 1 + read-only + + + ACK_WITH_ERR_8 + NA + 8 + 1 + read-only + + + ACK_WITH_ERR_9 + NA + 9 + 1 + read-only + + + ACK_WITH_ERR_10 + NA + 10 + 1 + read-only + + + ACK_WITH_ERR_11 + NA + 11 + 1 + read-only + + + ACK_WITH_ERR_12 + NA + 12 + 1 + read-only + + + ACK_WITH_ERR_13 + NA + 13 + 1 + read-only + + + ACK_WITH_ERR_14 + NA + 14 + 1 + read-only + + + ACK_WITH_ERR_15 + NA + 15 + 1 + read-only + + + DPHY_ERRORS_0 + NA + 16 + 1 + read-only + + + DPHY_ERRORS_1 + NA + 17 + 1 + read-only + + + DPHY_ERRORS_2 + NA + 18 + 1 + read-only + + + DPHY_ERRORS_3 + NA + 19 + 1 + read-only + + + DPHY_ERRORS_4 + NA + 20 + 1 + read-only + + + + + INT_ST1 + NA + 0xC0 + 0x20 + + + TO_HS_TX + NA + 0 + 1 + read-only + + + TO_LP_RX + NA + 1 + 1 + read-only + + + ECC_SINGLE_ERR + NA + 2 + 1 + read-only + + + ECC_MILTI_ERR + NA + 3 + 1 + read-only + + + CRC_ERR + NA + 4 + 1 + read-only + + + PKT_SIZE_ERR + NA + 5 + 1 + read-only + + + EOPT_ERR + NA + 6 + 1 + read-only + + + DPI_PLD_WR_ERR + NA + 7 + 1 + read-only + + + GEN_CMD_WR_ERR + NA + 8 + 1 + read-only + + + GEN_PLD_WR_ERR + NA + 9 + 1 + read-only + + + GEN_PLD_SEND_ERR + NA + 10 + 1 + read-only + + + GEN_PLD_RD_ERR + NA + 11 + 1 + read-only + + + GEN_PLD_RECEV_ERR + NA + 12 + 1 + read-only + + + DPI_BUFF_PLD_UNDER + NA + 19 + 1 + read-only + + + + + INT_MSK0 + NA + 0xC4 + 0x20 + + + MASK_ACK_WITH_ERR_0 + NA + 0 + 1 + read-write + + + MASK_ACK_WITH_ERR_1 + NA + 1 + 1 + read-write + + + MASK_ACK_WITH_ERR_2 + NA + 2 + 1 + read-write + + + MASK_ACK_WITH_ERR_3 + NA + 3 + 1 + read-write + + + MASK_ACK_WITH_ERR_4 + NA + 4 + 1 + read-write + + + MASK_ACK_WITH_ERR_5 + NA + 5 + 1 + read-write + + + MASK_ACK_WITH_ERR_6 + NA + 6 + 1 + read-write + + + MASK_ACK_WITH_ERR_7 + NA + 7 + 1 + read-write + + + MASK_ACK_WITH_ERR_8 + NA + 8 + 1 + read-write + + + MASK_ACK_WITH_ERR_9 + NA + 9 + 1 + read-write + + + MASK_ACK_WITH_ERR_10 + NA + 10 + 1 + read-write + + + MASK_ACK_WITH_ERR_11 + NA + 11 + 1 + read-write + + + MASK_ACK_WITH_ERR_12 + NA + 12 + 1 + read-write + + + MASK_ACK_WITH_ERR_13 + NA + 13 + 1 + read-write + + + MASK_ACK_WITH_ERR_14 + NA + 14 + 1 + read-write + + + MASK_ACK_WITH_ERR_15 + NA + 15 + 1 + read-write + + + MASK_DPHY_ERRORS_0 + NA + 16 + 1 + read-write + + + MASK_DPHY_ERRORS_1 + NA + 17 + 1 + read-write + + + MASK_DPHY_ERRORS_2 + NA + 18 + 1 + read-write + + + MASK_DPHY_ERRORS_3 + NA + 19 + 1 + read-write + + + MASK_DPHY_ERRORS_4 + NA + 20 + 1 + read-write + + + + + INT_MSK1 + NA + 0xC8 + 0x20 + + + MASK_TO_HS_TX + NA + 0 + 1 + read-write + + + MASK_TO_LP_RX + NA + 1 + 1 + read-write + + + MASK_ECC_SINGLE_ERR + NA + 2 + 1 + read-write + + + MASK_ECC_MILTI_ERR + NA + 3 + 1 + read-write + + + MASK_CRC_ERR + NA + 4 + 1 + read-write + + + MASK_PKT_SIZE_ERR + NA + 5 + 1 + read-write + + + MASK_EOPT_ERR + NA + 6 + 1 + read-write + + + MASK_DPI_PLD_WR_ERR + NA + 7 + 1 + read-write + + + MASK_GEN_CMD_WR_ERR + NA + 8 + 1 + read-write + + + MASK_GEN_PLD_WR_ERR + NA + 9 + 1 + read-write + + + MASK_GEN_PLD_SEND_ERR + NA + 10 + 1 + read-write + + + MASK_GEN_PLD_RD_ERR + NA + 11 + 1 + read-write + + + MASK_GEN_PLD_RECEV_ERR + NA + 12 + 1 + read-write + + + MASK_DPI_BUFF_PLD_UNDER + NA + 19 + 1 + read-write + + + + + PHY_CAL + NA + 0xCC + 0x20 + + + TXSKEWCALHS + NA + 0 + 1 + read-write + + + + + INT_FORCE0 + NA + 0xD8 + 0x20 + + + FORCE_ACK_WITH_ERR_0 + NA + 0 + 1 + read-write + + + FORCE_ACK_WITH_ERR_1 + NA + 1 + 1 + read-write + + + FORCE_ACK_WITH_ERR_2 + NA + 2 + 1 + read-write + + + FORCE_ACK_WITH_ERR_3 + NA + 3 + 1 + read-write + + + FORCE_ACK_WITH_ERR_4 + NA + 4 + 1 + read-write + + + FORCE_ACK_WITH_ERR_5 + NA + 5 + 1 + read-write + + + FORCE_ACK_WITH_ERR_6 + NA + 6 + 1 + read-write + + + FORCE_ACK_WITH_ERR_7 + NA + 7 + 1 + read-write + + + FORCE_ACK_WITH_ERR_8 + NA + 8 + 1 + read-write + + + FORCE_ACK_WITH_ERR_9 + NA + 9 + 1 + read-write + + + FORCE_ACK_WITH_ERR_10 + NA + 10 + 1 + read-write + + + FORCE_ACK_WITH_ERR_11 + NA + 11 + 1 + read-write + + + FORCE_ACK_WITH_ERR_12 + NA + 12 + 1 + read-write + + + FORCE_ACK_WITH_ERR_13 + NA + 13 + 1 + read-write + + + FORCE_ACK_WITH_ERR_14 + NA + 14 + 1 + read-write + + + FORCE_ACK_WITH_ERR_15 + NA + 15 + 1 + read-write + + + FORCE_DPHY_ERRORS_0 + NA + 16 + 1 + read-write + + + FORCE_DPHY_ERRORS_1 + NA + 17 + 1 + read-write + + + FORCE_DPHY_ERRORS_2 + NA + 18 + 1 + read-write + + + FORCE_DPHY_ERRORS_3 + NA + 19 + 1 + read-write + + + FORCE_DPHY_ERRORS_4 + NA + 20 + 1 + read-write + + + + + INT_FORCE1 + NA + 0xDC + 0x20 + + + FORCE_TO_HS_TX + NA + 0 + 1 + read-write + + + FORCE_TO_LP_RX + NA + 1 + 1 + read-write + + + FORCE_ECC_SINGLE_ERR + NA + 2 + 1 + read-write + + + FORCE_ECC_MILTI_ERR + NA + 3 + 1 + read-write + + + FORCE_CRC_ERR + NA + 4 + 1 + read-write + + + FORCE_PKT_SIZE_ERR + NA + 5 + 1 + read-write + + + FORCE_EOPT_ERR + NA + 6 + 1 + read-write + + + FORCE_DPI_PLD_WR_ERR + NA + 7 + 1 + read-write + + + FORCE_GEN_CMD_WR_ERR + NA + 8 + 1 + read-write + + + FORCE_GEN_PLD_WR_ERR + NA + 9 + 1 + read-write + + + FORCE_GEN_PLD_SEND_ERR + NA + 10 + 1 + read-write + + + FORCE_GEN_PLD_RD_ERR + NA + 11 + 1 + read-write + + + FORCE_GEN_PLD_RECEV_ERR + NA + 12 + 1 + read-write + + + FORCE_DPI_BUFF_PLD_UNDER + NA + 19 + 1 + read-write + + + + + DSC_PARAMETER + NA + 0xF0 + 0x20 + + + COMPRESSION_MODE + NA + 0 + 1 + read-write + + + COMPRESS_ALGO + NA + 8 + 2 + read-write + + + PPS_SEL + NA + 16 + 2 + read-write + + + + + PHY_TMR_RD_CFG + NA + 0xF4 + 0x20 + + + MAX_RD_TIME + NA + 0 + 15 + read-write + + + + + VID_SHADOW_CTRL + NA + 0x100 + 0x20 + + + VID_SHADOW_EN + NA + 0 + 1 + read-write + + + VID_SHADOW_REQ + NA + 8 + 1 + read-write + + + VID_SHADOW_PIN_REQ + NA + 16 + 1 + read-write + + + + + DPI_VCID_ACT + NA + 0x10C + 0x20 + + + DPI_VCID_ACT + NA + 0 + 2 + read-only + + + + + DPI_COLOR_CODING_ACT + NA + 0x110 + 0x20 + + + DPI_COLOR_CODING_ACT + NA + 0 + 4 + read-only + + + LOOSELY18_EN_ACT + NA + 8 + 1 + read-only + + + + + DPI_LP_CMD_TIM_ACT + NA + 0x118 + 0x20 + + + INVACT_LPCMD_TIME_ACT + NA + 0 + 8 + read-only + + + OUTVACT_LPCMD_TIME_ACT + NA + 16 + 8 + read-only + + + + + EDPI_TE_HW_CFG + NA + 0x11C + 0x20 + + + HW_TEAR_EFFECT_ON + NA + 0 + 1 + read-write + + + HW_TEAR_EFFECT_GEN + NA + 1 + 1 + read-write + + + HW_SET_SCAN_LINE + NA + 4 + 1 + read-write + + + SCAN_LINE_PARAMETER + NA + 16 + 16 + read-write + + + + + VID_MODE_CFG_ACT + NA + 0x138 + 0x20 + + + VID_MODE_TYPE_ACT + NA + 0 + 2 + read-only + + + LP_VSA_EN_ACT + NA + 2 + 1 + read-only + + + LP_VBP_EN_ACT + NA + 3 + 1 + read-only + + + LP_VFP_EN_ACT + NA + 4 + 1 + read-only + + + LP_VACT_EN_ACT + NA + 5 + 1 + read-only + + + LP_HBP_EN_ACT + NA + 6 + 1 + read-only + + + LP_HFP_EN_ACT + NA + 7 + 1 + read-only + + + FRAME_BTA_ACK_EN_ACT + NA + 8 + 1 + read-only + + + LP_CMD_EN_ACT + NA + 9 + 1 + read-only + + + + + VID_PKT_SIZE_ACT + NA + 0x13C + 0x20 + + + VID_PKT_SIZE_ACT + NA + 0 + 14 + read-only + + + + + VID_NUM_CHUNKS_ACT + NA + 0x140 + 0x20 + + + VID_NUM_CHUNKS_ACT + NA + 0 + 13 + read-only + + + + + VID_NULL_SIZE_ACT + NA + 0x144 + 0x20 + + + VID_NULL_SIZE_ACT + NA + 0 + 13 + read-only + + + + + VID_HSA_TIME_ACT + NA + 0x148 + 0x20 + + + VID_HSA_TIME_ACT + NA + 0 + 12 + read-only + + + + + VID_HBP_TIME_ACT + NA + 0x14C + 0x20 + + + VID_HBP_TIME_ACT + NA + 0 + 12 + read-only + + + + + VID_HLINE_TIME_ACT + NA + 0x150 + 0x20 + + + VID_HLINE_TIME_ACT + NA + 0 + 15 + read-only + + + + + VID_VSA_LINES_ACT + NA + 0x154 + 0x20 + + + VSA_LINES_ACT + NA + 0 + 10 + read-only + + + + + VID_VBP_LINES_ACT + NA + 0x158 + 0x20 + + + VBP_LINES_ACT + NA + 0 + 10 + read-only + + + + + VID_VFP_LINES_ACT + NA + 0x15C + 0x20 + + + VFP_LINES_ACT + NA + 0 + 10 + read-only + + + + + VID_VACTIVE_LINES_ACT + NA + 0x160 + 0x20 + + + V_ACTIVE_LINES_ACT + NA + 0 + 14 + read-only + + + + + VID_PKT_STATUS + NA + 0x168 + 0x20 + 0x00010005 + + + DPI_CMD_W_EMPTY + NA + 0 + 1 + read-only + + + DPI_CMD_W_FULL + NA + 1 + 1 + read-only + + + DPI_PLD_W_EMPTY + NA + 2 + 1 + read-only + + + DPI_PLD_W_FULL + NA + 3 + 1 + read-only + + + DPI_BUFF_PLD_EMPTY + NA + 16 + 1 + read-only + + + DPI_BUFF_PLD_FULL + NA + 17 + 1 + read-only + + + + + SDF_3D_ACT + NA + 0x190 + 0x20 + + + MODE_3D_ACT + NA + 0 + 2 + read-only + + + FORMAT_3D_ACT + NA + 2 + 2 + read-only + + + SECOND_VSYNC_ACT + NA + 4 + 1 + read-only + + + RIGHT_FIRST_ACT + NA + 5 + 1 + read-only + + + SEND_3D_CFG_ACT + NA + 16 + 1 + read-only + + + + + + + ECC + ECC (ECC Hardware Accelerator) + ECC + 0x50093000 + + 0x0 + 0x78 + registers + + + ECC + 71 + + + + MULT_INT_RAW + ECC interrupt raw register, valid in level. + 0xC + 0x20 + + + CALC_DONE_INT_RAW + The raw interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ST + ECC interrupt status register. + 0x10 + 0x20 + + + CALC_DONE_INT_ST + The masked interrupt status bit for the ecc_calc_done_int interrupt + 0 + 1 + read-only + + + + + MULT_INT_ENA + ECC interrupt enable register. + 0x14 + 0x20 + + + CALC_DONE_INT_ENA + The interrupt enable bit for the ecc_calc_done_int interrupt + 0 + 1 + read-write + + + + + MULT_INT_CLR + ECC interrupt clear register. + 0x18 + 0x20 + + + CALC_DONE_INT_CLR + Set this bit to clear the ecc_calc_done_int interrupt + 0 + 1 + write-only + + + + + MULT_CONF + ECC configure register + 0x1C + 0x20 + + + START + Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. + 0 + 1 + read-write + + + RESET + Write 1 to reset ECC Accelerator. + 1 + 1 + write-only + + + KEY_LENGTH + The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. + 2 + 1 + read-write + + + MOD_BASE + The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve) + 3 + 1 + read-write + + + WORK_MODE + The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. + 4 + 4 + read-write + + + SECURITY_MODE + Reserved + 8 + 1 + read-write + + + VERIFICATION_RESULT + The verification result bit of ECC Accelerator, only valid when calculation is done. + 29 + 1 + read-only + + + CLK_EN + Write 1 to force on register clock gate. + 30 + 1 + read-write + + + MEM_CLOCK_GATE_FORCE_ON + ECC memory clock gate force on register + 31 + 1 + read-write + + + + + MULT_DATE + Version control register + 0xFC + 0x20 + 0x02305040 + + + DATE + ECC mult version control register + 0 + 28 + read-write + + + + + 32 + 0x1 + K_MEM[%s] + The memory that stores k. + 0x100 + 0x8 + + + 32 + 0x1 + PX_MEM[%s] + The memory that stores Px. + 0x120 + 0x8 + + + 32 + 0x1 + PY_MEM[%s] + The memory that stores Py. + 0x140 + 0x8 + + + + + ECDSA + ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator + ECDSA + 0x50096000 + + 0x0 + 0xF8 + registers + + + + CONF + ECDSA configure register + 0x4 + 0x20 + + + WORK_MODE + The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid. + 0 + 2 + read-write + + + ECC_CURVE + The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + 2 + 1 + read-write + + + SOFTWARE_SET_K + The source of k select bit. 0: k is automatically generated by hardware. 1: k is written by software. + 3 + 1 + read-write + + + SOFTWARE_SET_Z + The source of z select bit. 0: z is generated from SHA result. 1: z is written by software. + 4 + 1 + read-write + + + DETERMINISTIC_K + The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by deterministic derivation algorithm. + 5 + 1 + read-write + + + DETERMINISTIC_LOOP + The (loop number - 1) value in the deterministic derivation algorithm to derive k. + 6 + 16 + read-write + + + + + CLK + ECDSA clock gate register + 0x8 + 0x20 + + + GATE_FORCE_ON + Write 1 to force on register clock gate. + 0 + 1 + read-write + + + + + INT_RAW + ECDSA interrupt raw register, valid in level. + 0xC + 0x20 + + + CALC_DONE_INT_RAW + The raw interrupt status bit for the ecdsa_calc_done_int interrupt + 0 + 1 + read-only + + + SHA_RELEASE_INT_RAW + The raw interrupt status bit for the ecdsa_sha_release_int interrupt + 1 + 1 + read-only + + + + + INT_ST + ECDSA interrupt status register. + 0x10 + 0x20 + + + CALC_DONE_INT_ST + The masked interrupt status bit for the ecdsa_calc_done_int interrupt + 0 + 1 + read-only + + + SHA_RELEASE_INT_ST + The masked interrupt status bit for the ecdsa_sha_release_int interrupt + 1 + 1 + read-only + + + + + INT_ENA + ECDSA interrupt enable register. + 0x14 + 0x20 + + + CALC_DONE_INT_ENA + The interrupt enable bit for the ecdsa_calc_done_int interrupt + 0 + 1 + read-write + + + SHA_RELEASE_INT_ENA + The interrupt enable bit for the ecdsa_sha_release_int interrupt + 1 + 1 + read-write + + + + + INT_CLR + ECDSA interrupt clear register. + 0x18 + 0x20 + + + CALC_DONE_INT_CLR + Set this bit to clear the ecdsa_calc_done_int interrupt + 0 + 1 + write-only + + + SHA_RELEASE_INT_CLR + Set this bit to clear the ecdsa_sha_release_int interrupt + 1 + 1 + write-only + + + + + START + ECDSA start register + 0x1C + 0x20 + + + START + Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared after configuration. + 0 + 1 + write-only + + + LOAD_DONE + Write 1 to input load done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + 1 + 1 + write-only + + + GET_DONE + Write 1 to input get done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + 2 + 1 + write-only + + + + + STATE + ECDSA status register + 0x20 + 0x20 + + + BUSY + The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY state. + 0 + 2 + read-only + + + + + RESULT + ECDSA result register + 0x24 + 0x20 + + + OPERATION_RESULT + The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is done. + 0 + 1 + read-only + + + K_VALUE_WARNING + The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the curve order, then actually taken k = k mod n. + 1 + 1 + read-only + + + + + DATE + Version control register + 0xFC + 0x20 + 0x02304070 + + + DATE + ECDSA version control register + 0 + 28 + read-write + + + + + SHA_MODE + ECDSA control SHA register + 0x200 + 0x20 + + + SHA_MODE + The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid. + 0 + 3 + read-write + + + + + SHA_START + ECDSA control SHA register + 0x210 + 0x20 + + + SHA_START + Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. + 0 + 1 + write-only + + + + + SHA_CONTINUE + ECDSA control SHA register + 0x214 + 0x20 + + + SHA_CONTINUE + Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. + 0 + 1 + write-only + + + + + SHA_BUSY + ECDSA status register + 0x218 + 0x20 + + + SHA_BUSY + The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in calculation. 0: SHA is idle. + 0 + 1 + read-only + + + + + 32 + 0x1 + MESSAGE_MEM[%s] + The memory that stores message. + 0x280 + 0x8 + + + 32 + 0x1 + R_MEM[%s] + The memory that stores r. + 0xA00 + 0x8 + + + 32 + 0x1 + S_MEM[%s] + The memory that stores s. + 0xA20 + 0x8 + + + 32 + 0x1 + Z_MEM[%s] + The memory that stores software written z. + 0xA40 + 0x8 + + + 32 + 0x1 + QAX_MEM[%s] + The memory that stores x coordinates of QA or software written k. + 0xA60 + 0x8 + + + 32 + 0x1 + QAY_MEM[%s] + The memory that stores y coordinates of QA. + 0xA80 + 0x8 + + + + + EFUSE + eFuse Controller + EFUSE + 0x5012D000 + + 0x0 + 0x3D8 + registers + + + + PGM_DATA0 + Register 0 that stores data to be programmed. + 0x0 + 0x20 + + + PGM_DATA_0 + Configures the 0th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA1 + Register 1 that stores data to be programmed. + 0x4 + 0x20 + + + PGM_DATA_1 + Configures the 1st 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA2 + Register 2 that stores data to be programmed. + 0x8 + 0x20 + + + PGM_DATA_2 + Configures the 2nd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA3 + Register 3 that stores data to be programmed. + 0xC + 0x20 + + + PGM_DATA_3 + Configures the 3rd 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA4 + Register 4 that stores data to be programmed. + 0x10 + 0x20 + + + PGM_DATA_4 + Configures the 4th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA5 + Register 5 that stores data to be programmed. + 0x14 + 0x20 + + + PGM_DATA_5 + Configures the 5th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA6 + Register 6 that stores data to be programmed. + 0x18 + 0x20 + + + PGM_DATA_6 + Configures the 6th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_DATA7 + Register 7 that stores data to be programmed. + 0x1C + 0x20 + + + PGM_DATA_7 + Configures the 7th 32-bit data to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE0 + Register 0 that stores the RS code to be programmed. + 0x20 + 0x20 + + + PGM_RS_DATA_0 + Configures the 0th 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE1 + Register 1 that stores the RS code to be programmed. + 0x24 + 0x20 + + + PGM_RS_DATA_1 + Configures the 1st 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + PGM_CHECK_VALUE2 + Register 2 that stores the RS code to be programmed. + 0x28 + 0x20 + + + PGM_RS_DATA_2 + Configures the 2nd 32-bit RS code to be programmed. + 0 + 32 + read-write + + + + + RD_WR_DIS + BLOCK0 data register 0. + 0x2C + 0x20 + + + WR_DIS + Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled. + 0 + 32 + read-only + + + + + RD_REPEAT_DATA0 + BLOCK0 data register 1. + 0x30 + 0x20 + + + RD_DIS + Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled. + 0 + 7 + read-only + + + USB_DEVICE_EXCHG_PINS + Enable usb device exchange pins of D+ and D-. + 7 + 1 + read-only + + + USB_OTG11_EXCHG_PINS + Enable usb otg11 exchange pins of D+ and D-. + 8 + 1 + read-only + + + DIS_USB_JTAG + Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled. + 9 + 1 + read-only + + + POWERGLITCH_EN + Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG + Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD + Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS + Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download. + 13 + 1 + read-only + + + DIS_TWAI + Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE + Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled. + 15 + 1 + read-only + + + SOFT_DIS_JTAG + Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled. + 16 + 3 + read-only + + + DIS_PAD_JTAG + Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT + Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled. + 20 + 1 + read-only + + + USB_DEVICE_DREFH + USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV + 21 + 2 + read-only + + + USB_OTG11_DREFH + USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV + 23 + 2 + read-only + + + USB_PHY_SEL + TBD + 25 + 1 + read-only + + + KM_HUK_GEN_STATE_LOW + Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. + 26 + 6 + read-only + + + + + RD_REPEAT_DATA1 + BLOCK0 data register 2. + 0x34 + 0x20 + + + KM_HUK_GEN_STATE_HIGH + Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid. + 0 + 3 + read-only + + + KM_RND_SWITCH_CYCLE + Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. + 3 + 2 + read-only + + + KM_DEPLOY_ONLY_ONCE + Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + 5 + 4 + read-only + + + FORCE_USE_KEY_MANAGER_KEY + Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + 9 + 4 + read-only + + + FORCE_DISABLE_SW_INIT_KEY + Set this bit to disable software written init key, and force use efuse_init_key. + 13 + 1 + read-only + + + XTS_KEY_LENGTH_256 + Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. + 14 + 1 + read-only + + + WDT_DELAY_SEL + Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT + Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0 + Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1 + Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2 + Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled. + 23 + 1 + read-only + + + KEY_PURPOSE_0 + Represents the purpose of Key0. + 24 + 4 + read-only + + + KEY_PURPOSE_1 + Represents the purpose of Key1. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA2 + BLOCK0 data register 3. + 0x38 + 0x20 + 0x00080000 + + + KEY_PURPOSE_2 + Represents the purpose of Key2. + 0 + 4 + read-only + + + KEY_PURPOSE_3 + Represents the purpose of Key3. + 4 + 4 + read-only + + + KEY_PURPOSE_4 + Represents the purpose of Key4. + 8 + 4 + read-only + + + KEY_PURPOSE_5 + Represents the purpose of Key5. + 12 + 4 + read-only + + + SEC_DPA_LEVEL + Represents the spa secure level by configuring the clock random divide mode. + 16 + 2 + read-only + + + ECDSA_ENABLE_SOFT_K + Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE + Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + 19 + 1 + read-only + + + SECURE_BOOT_EN + Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE + Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled. + 21 + 1 + read-only + + + FLASH_TYPE + The type of interfaced flash. 0: four data lines, 1: eight data lines. + 23 + 1 + read-only + + + FLASH_PAGE_SIZE + Set flash page size. + 24 + 2 + read-only + + + FLASH_ECC_EN + Set this bit to enable ecc for flash boot. + 26 + 1 + read-only + + + DIS_USB_OTG_DOWNLOAD_MODE + Set this bit to disable download via USB-OTG. + 27 + 1 + read-only + + + FLASH_TPUW + Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value. + 28 + 4 + read-only + + + + + RD_REPEAT_DATA3 + BLOCK0 data register 4. + 0x3C + 0x20 + + + DIS_DOWNLOAD_MODE + Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT + Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + 1 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ROM_PRINT + Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + 2 + 1 + read-only + + + LOCK_KM_KEY + TBD + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD + Represents whether security download is enabled or disabled. 1: enabled. 0: disabled. + 5 + 1 + read-only + + + UART_PRINT_CONTROL + Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. + 6 + 2 + read-only + + + FORCE_SEND_RESUME + Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced. + 8 + 1 + read-only + + + SECURE_VERSION + Represents the version used by ESP-IDF anti-rollback feature. + 9 + 16 + read-only + + + SECURE_BOOT_DISABLE_FAST_WAKE + Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled. + 25 + 1 + read-only + + + HYS_EN_PAD + Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled. + 26 + 1 + read-only + + + DCDC_VSET + Set the dcdc voltage default. + 27 + 5 + read-only + + + + + RD_REPEAT_DATA4 + BLOCK0 data register 5. + 0x40 + 0x20 + + + _0PXA_TIEH_SEL_0 + TBD + 0 + 2 + read-only + + + _0PXA_TIEH_SEL_1 + TBD. + 2 + 2 + read-only + + + _0PXA_TIEH_SEL_2 + TBD. + 4 + 2 + read-only + + + _0PXA_TIEH_SEL_3 + TBD. + 6 + 2 + read-only + + + KM_DISABLE_DEPLOY_MODE + TBD. + 8 + 4 + read-only + + + USB_DEVICE_DREFL + Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. + 12 + 2 + read-only + + + USB_OTG11_DREFL + Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV. + 14 + 2 + read-only + + + HP_PWR_SRC_SEL + HP system power source select. 0:LDO. 1: DCDC. + 18 + 1 + read-only + + + DCDC_VSET_EN + Select dcdc vset use efuse_dcdc_vset. + 19 + 1 + read-only + + + DIS_WDT + Set this bit to disable watch dog. + 20 + 1 + read-only + + + DIS_SWD + Set this bit to disable super-watchdog. + 21 + 1 + read-only + + + + + RD_MAC_SYS_0 + BLOCK1 data register $n. + 0x44 + 0x20 + + + MAC_0 + Stores the low 32 bits of MAC address. + 0 + 32 + read-only + + + + + RD_MAC_SYS_1 + BLOCK1 data register $n. + 0x48 + 0x20 + + + MAC_1 + Stores the high 16 bits of MAC address. + 0 + 16 + read-only + + + MAC_EXT + Stores the extended bits of MAC address. + 16 + 16 + read-only + + + + + RD_MAC_SYS_2 + BLOCK1 data register $n. + 0x4C + 0x20 + + + MAC_RESERVED_1 + Reserved. + 0 + 14 + read-only + + + MAC_RESERVED_0 + Reserved. + 14 + 18 + read-only + + + + + RD_MAC_SYS_3 + BLOCK1 data register $n. + 0x50 + 0x20 + + + MAC_RESERVED_2 + Reserved. + 0 + 18 + read-only + + + SYS_DATA_PART0_0 + Stores the first 14 bits of the zeroth part of system data. + 18 + 14 + read-only + + + + + RD_MAC_SYS_4 + BLOCK1 data register $n. + 0x54 + 0x20 + + + SYS_DATA_PART0_1 + Stores the first 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_MAC_SYS_5 + BLOCK1 data register $n. + 0x58 + 0x20 + + + SYS_DATA_PART0_2 + Stores the second 32 bits of the zeroth part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA0 + Register $n of BLOCK2 (system). + 0x5C + 0x20 + + + SYS_DATA_PART1_0 + Stores the zeroth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA1 + Register $n of BLOCK2 (system). + 0x60 + 0x20 + + + SYS_DATA_PART1_1 + Stores the first 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA2 + Register $n of BLOCK2 (system). + 0x64 + 0x20 + + + SYS_DATA_PART1_2 + Stores the second 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA3 + Register $n of BLOCK2 (system). + 0x68 + 0x20 + + + SYS_DATA_PART1_3 + Stores the third 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA4 + Register $n of BLOCK2 (system). + 0x6C + 0x20 + + + SYS_DATA_PART1_4 + Stores the fourth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA5 + Register $n of BLOCK2 (system). + 0x70 + 0x20 + + + SYS_DATA_PART1_5 + Stores the fifth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA6 + Register $n of BLOCK2 (system). + 0x74 + 0x20 + + + SYS_DATA_PART1_6 + Stores the sixth 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART1_DATA7 + Register $n of BLOCK2 (system). + 0x78 + 0x20 + + + SYS_DATA_PART1_7 + Stores the seventh 32 bits of the first part of system data. + 0 + 32 + read-only + + + + + RD_USR_DATA0 + Register $n of BLOCK3 (user). + 0x7C + 0x20 + + + USR_DATA0 + Stores the zeroth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA1 + Register $n of BLOCK3 (user). + 0x80 + 0x20 + + + USR_DATA1 + Stores the first 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA2 + Register $n of BLOCK3 (user). + 0x84 + 0x20 + + + USR_DATA2 + Stores the second 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA3 + Register $n of BLOCK3 (user). + 0x88 + 0x20 + + + USR_DATA3 + Stores the third 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA4 + Register $n of BLOCK3 (user). + 0x8C + 0x20 + + + USR_DATA4 + Stores the fourth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA5 + Register $n of BLOCK3 (user). + 0x90 + 0x20 + + + USR_DATA5 + Stores the fifth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA6 + Register $n of BLOCK3 (user). + 0x94 + 0x20 + + + USR_DATA6 + Stores the sixth 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_USR_DATA7 + Register $n of BLOCK3 (user). + 0x98 + 0x20 + + + USR_DATA7 + Stores the seventh 32 bits of BLOCK3 (user). + 0 + 32 + read-only + + + + + RD_KEY0_DATA0 + Register $n of BLOCK4 (KEY0). + 0x9C + 0x20 + + + KEY0_DATA0 + Stores the zeroth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA1 + Register $n of BLOCK4 (KEY0). + 0xA0 + 0x20 + + + KEY0_DATA1 + Stores the first 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA2 + Register $n of BLOCK4 (KEY0). + 0xA4 + 0x20 + + + KEY0_DATA2 + Stores the second 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA3 + Register $n of BLOCK4 (KEY0). + 0xA8 + 0x20 + + + KEY0_DATA3 + Stores the third 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA4 + Register $n of BLOCK4 (KEY0). + 0xAC + 0x20 + + + KEY0_DATA4 + Stores the fourth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA5 + Register $n of BLOCK4 (KEY0). + 0xB0 + 0x20 + + + KEY0_DATA5 + Stores the fifth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA6 + Register $n of BLOCK4 (KEY0). + 0xB4 + 0x20 + + + KEY0_DATA6 + Stores the sixth 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY0_DATA7 + Register $n of BLOCK4 (KEY0). + 0xB8 + 0x20 + + + KEY0_DATA7 + Stores the seventh 32 bits of KEY0. + 0 + 32 + read-only + + + + + RD_KEY1_DATA0 + Register $n of BLOCK5 (KEY1). + 0xBC + 0x20 + + + KEY1_DATA0 + Stores the zeroth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA1 + Register $n of BLOCK5 (KEY1). + 0xC0 + 0x20 + + + KEY1_DATA1 + Stores the first 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA2 + Register $n of BLOCK5 (KEY1). + 0xC4 + 0x20 + + + KEY1_DATA2 + Stores the second 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA3 + Register $n of BLOCK5 (KEY1). + 0xC8 + 0x20 + + + KEY1_DATA3 + Stores the third 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA4 + Register $n of BLOCK5 (KEY1). + 0xCC + 0x20 + + + KEY1_DATA4 + Stores the fourth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA5 + Register $n of BLOCK5 (KEY1). + 0xD0 + 0x20 + + + KEY1_DATA5 + Stores the fifth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA6 + Register $n of BLOCK5 (KEY1). + 0xD4 + 0x20 + + + KEY1_DATA6 + Stores the sixth 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY1_DATA7 + Register $n of BLOCK5 (KEY1). + 0xD8 + 0x20 + + + KEY1_DATA7 + Stores the seventh 32 bits of KEY1. + 0 + 32 + read-only + + + + + RD_KEY2_DATA0 + Register $n of BLOCK6 (KEY2). + 0xDC + 0x20 + + + KEY2_DATA0 + Stores the zeroth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA1 + Register $n of BLOCK6 (KEY2). + 0xE0 + 0x20 + + + KEY2_DATA1 + Stores the first 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA2 + Register $n of BLOCK6 (KEY2). + 0xE4 + 0x20 + + + KEY2_DATA2 + Stores the second 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA3 + Register $n of BLOCK6 (KEY2). + 0xE8 + 0x20 + + + KEY2_DATA3 + Stores the third 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA4 + Register $n of BLOCK6 (KEY2). + 0xEC + 0x20 + + + KEY2_DATA4 + Stores the fourth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA5 + Register $n of BLOCK6 (KEY2). + 0xF0 + 0x20 + + + KEY2_DATA5 + Stores the fifth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA6 + Register $n of BLOCK6 (KEY2). + 0xF4 + 0x20 + + + KEY2_DATA6 + Stores the sixth 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY2_DATA7 + Register $n of BLOCK6 (KEY2). + 0xF8 + 0x20 + + + KEY2_DATA7 + Stores the seventh 32 bits of KEY2. + 0 + 32 + read-only + + + + + RD_KEY3_DATA0 + Register $n of BLOCK7 (KEY3). + 0xFC + 0x20 + + + KEY3_DATA0 + Stores the zeroth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA1 + Register $n of BLOCK7 (KEY3). + 0x100 + 0x20 + + + KEY3_DATA1 + Stores the first 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA2 + Register $n of BLOCK7 (KEY3). + 0x104 + 0x20 + + + KEY3_DATA2 + Stores the second 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA3 + Register $n of BLOCK7 (KEY3). + 0x108 + 0x20 + + + KEY3_DATA3 + Stores the third 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA4 + Register $n of BLOCK7 (KEY3). + 0x10C + 0x20 + + + KEY3_DATA4 + Stores the fourth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA5 + Register $n of BLOCK7 (KEY3). + 0x110 + 0x20 + + + KEY3_DATA5 + Stores the fifth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA6 + Register $n of BLOCK7 (KEY3). + 0x114 + 0x20 + + + KEY3_DATA6 + Stores the sixth 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY3_DATA7 + Register $n of BLOCK7 (KEY3). + 0x118 + 0x20 + + + KEY3_DATA7 + Stores the seventh 32 bits of KEY3. + 0 + 32 + read-only + + + + + RD_KEY4_DATA0 + Register $n of BLOCK8 (KEY4). + 0x11C + 0x20 + + + KEY4_DATA0 + Stores the zeroth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA1 + Register $n of BLOCK8 (KEY4). + 0x120 + 0x20 + + + KEY4_DATA1 + Stores the first 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA2 + Register $n of BLOCK8 (KEY4). + 0x124 + 0x20 + + + KEY4_DATA2 + Stores the second 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA3 + Register $n of BLOCK8 (KEY4). + 0x128 + 0x20 + + + KEY4_DATA3 + Stores the third 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA4 + Register $n of BLOCK8 (KEY4). + 0x12C + 0x20 + + + KEY4_DATA4 + Stores the fourth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA5 + Register $n of BLOCK8 (KEY4). + 0x130 + 0x20 + + + KEY4_DATA5 + Stores the fifth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA6 + Register $n of BLOCK8 (KEY4). + 0x134 + 0x20 + + + KEY4_DATA6 + Stores the sixth 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY4_DATA7 + Register $n of BLOCK8 (KEY4). + 0x138 + 0x20 + + + KEY4_DATA7 + Stores the seventh 32 bits of KEY4. + 0 + 32 + read-only + + + + + RD_KEY5_DATA0 + Register $n of BLOCK9 (KEY5). + 0x13C + 0x20 + + + KEY5_DATA0 + Stores the zeroth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA1 + Register $n of BLOCK9 (KEY5). + 0x140 + 0x20 + + + KEY5_DATA1 + Stores the first 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA2 + Register $n of BLOCK9 (KEY5). + 0x144 + 0x20 + + + KEY5_DATA2 + Stores the second 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA3 + Register $n of BLOCK9 (KEY5). + 0x148 + 0x20 + + + KEY5_DATA3 + Stores the third 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA4 + Register $n of BLOCK9 (KEY5). + 0x14C + 0x20 + + + KEY5_DATA4 + Stores the fourth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA5 + Register $n of BLOCK9 (KEY5). + 0x150 + 0x20 + + + KEY5_DATA5 + Stores the fifth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA6 + Register $n of BLOCK9 (KEY5). + 0x154 + 0x20 + + + KEY5_DATA6 + Stores the sixth 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_KEY5_DATA7 + Register $n of BLOCK9 (KEY5). + 0x158 + 0x20 + + + KEY5_DATA7 + Stores the seventh 32 bits of KEY5. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA0 + Register $n of BLOCK10 (system). + 0x15C + 0x20 + + + SYS_DATA_PART2_0 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA1 + Register $n of BLOCK9 (KEY5). + 0x160 + 0x20 + + + SYS_DATA_PART2_1 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA2 + Register $n of BLOCK10 (system). + 0x164 + 0x20 + + + SYS_DATA_PART2_2 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA3 + Register $n of BLOCK10 (system). + 0x168 + 0x20 + + + SYS_DATA_PART2_3 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA4 + Register $n of BLOCK10 (system). + 0x16C + 0x20 + + + SYS_DATA_PART2_4 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA5 + Register $n of BLOCK10 (system). + 0x170 + 0x20 + + + SYS_DATA_PART2_5 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA6 + Register $n of BLOCK10 (system). + 0x174 + 0x20 + + + SYS_DATA_PART2_6 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_SYS_PART2_DATA7 + Register $n of BLOCK10 (system). + 0x178 + 0x20 + + + SYS_DATA_PART2_7 + Stores the 0th 32 bits of the 2nd part of system data. + 0 + 32 + read-only + + + + + RD_REPEAT_ERR0 + Programming error record register 0 of BLOCK0. + 0x17C + 0x20 + + + RD_DIS_ERR + Indicates a programming error of RD_DIS. + 0 + 7 + read-only + + + DIS_USB_DEVICE_EXCHG_PINS_ERR + Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. + 7 + 1 + read-only + + + DIS_USB_OTG11_EXCHG_PINS_ERR + Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. + 8 + 1 + read-only + + + DIS_USB_JTAG_ERR + Indicates a programming error of DIS_USB_JTAG. + 9 + 1 + read-only + + + POWERGLITCH_EN_ERR + Indicates a programming error of POWERGLITCH_EN. + 10 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG. + 11 + 1 + read-only + + + DIS_FORCE_DOWNLOAD_ERR + Indicates a programming error of DIS_FORCE_DOWNLOAD. + 12 + 1 + read-only + + + SPI_DOWNLOAD_MSPI_DIS_ERR + Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + 13 + 1 + read-only + + + DIS_TWAI_ERR + Indicates a programming error of DIS_TWAI. + 14 + 1 + read-only + + + JTAG_SEL_ENABLE_ERR + Indicates a programming error of JTAG_SEL_ENABLE. + 15 + 1 + read-only + + + SOFT_DIS_JTAG_ERR + Indicates a programming error of SOFT_DIS_JTAG. + 16 + 3 + read-only + + + DIS_PAD_JTAG_ERR + Indicates a programming error of DIS_PAD_JTAG. + 19 + 1 + read-only + + + DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + 20 + 1 + read-only + + + USB_DEVICE_DREFH_ERR + Indicates a programming error of USB_DEVICE_DREFH. + 21 + 2 + read-only + + + USB_OTG11_DREFH_ERR + Indicates a programming error of USB_OTG11_DREFH. + 23 + 2 + read-only + + + USB_PHY_SEL_ERR + Indicates a programming error of USB_PHY_SEL. + 25 + 1 + read-only + + + HUK_GEN_STATE_LOW_ERR + Indicates a programming error of HUK_GEN_STATE_LOW. + 26 + 6 + read-only + + + + + RD_REPEAT_ERR1 + Programming error record register 1 of BLOCK0. + 0x180 + 0x20 + + + KM_HUK_GEN_STATE_HIGH_ERR + Indicates a programming error of HUK_GEN_STATE_HIGH. + 0 + 3 + read-only + + + KM_RND_SWITCH_CYCLE_ERR + Indicates a programming error of KM_RND_SWITCH_CYCLE. + 3 + 2 + read-only + + + KM_DEPLOY_ONLY_ONCE_ERR + Indicates a programming error of KM_DEPLOY_ONLY_ONCE. + 5 + 4 + read-only + + + FORCE_USE_KEY_MANAGER_KEY_ERR + Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. + 9 + 4 + read-only + + + FORCE_DISABLE_SW_INIT_KEY_ERR + Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. + 13 + 1 + read-only + + + XTS_KEY_LENGTH_256_ERR + Indicates a programming error of XTS_KEY_LENGTH_256. + 14 + 1 + read-only + + + WDT_DELAY_SEL_ERR + Indicates a programming error of WDT_DELAY_SEL. + 16 + 2 + read-only + + + SPI_BOOT_CRYPT_CNT_ERR + Indicates a programming error of SPI_BOOT_CRYPT_CNT. + 18 + 3 + read-only + + + SECURE_BOOT_KEY_REVOKE0_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + 21 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE1_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + 22 + 1 + read-only + + + SECURE_BOOT_KEY_REVOKE2_ERR + Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + 23 + 1 + read-only + + + KEY_PURPOSE_0_ERR + Indicates a programming error of KEY_PURPOSE_0. + 24 + 4 + read-only + + + KEY_PURPOSE_1_ERR + Indicates a programming error of KEY_PURPOSE_1. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR2 + Programming error record register 2 of BLOCK0. + 0x184 + 0x20 + + + KEY_PURPOSE_2_ERR + Indicates a programming error of KEY_PURPOSE_2. + 0 + 4 + read-only + + + KEY_PURPOSE_3_ERR + Indicates a programming error of KEY_PURPOSE_3. + 4 + 4 + read-only + + + KEY_PURPOSE_4_ERR + Indicates a programming error of KEY_PURPOSE_4. + 8 + 4 + read-only + + + KEY_PURPOSE_5_ERR + Indicates a programming error of KEY_PURPOSE_5. + 12 + 4 + read-only + + + SEC_DPA_LEVEL_ERR + Indicates a programming error of SEC_DPA_LEVEL. + 16 + 2 + read-only + + + ECDSA_ENABLE_SOFT_K_ERR + Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. + 18 + 1 + read-only + + + CRYPT_DPA_ENABLE_ERR + Indicates a programming error of CRYPT_DPA_ENABLE. + 19 + 1 + read-only + + + SECURE_BOOT_EN_ERR + Indicates a programming error of SECURE_BOOT_EN. + 20 + 1 + read-only + + + SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + 21 + 1 + read-only + + + FLASH_TYPE_ERR + Indicates a programming error of FLASH_TYPE. + 23 + 1 + read-only + + + FLASH_PAGE_SIZE_ERR + Indicates a programming error of FLASH_PAGE_SIZE. + 24 + 2 + read-only + + + FLASH_ECC_EN_ERR + Indicates a programming error of FLASH_ECC_EN. + 26 + 1 + read-only + + + DIS_USB_OTG_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. + 27 + 1 + read-only + + + FLASH_TPUW_ERR + Indicates a programming error of FLASH_TPUW. + 28 + 4 + read-only + + + + + RD_REPEAT_ERR3 + Programming error record register 3 of BLOCK0. + 0x188 + 0x20 + + + DIS_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_DOWNLOAD_MODE. + 0 + 1 + read-only + + + DIS_DIRECT_BOOT_ERR + Indicates a programming error of DIS_DIRECT_BOOT. + 1 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. + 2 + 1 + read-only + + + LOCK_KM_KEY_ERR + TBD + 3 + 1 + read-only + + + DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR + Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + 4 + 1 + read-only + + + ENABLE_SECURITY_DOWNLOAD_ERR + Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + 5 + 1 + read-only + + + UART_PRINT_CONTROL_ERR + Indicates a programming error of UART_PRINT_CONTROL. + 6 + 2 + read-only + + + FORCE_SEND_RESUME_ERR + Indicates a programming error of FORCE_SEND_RESUME. + 8 + 1 + read-only + + + SECURE_VERSION_ERR + Indicates a programming error of SECURE VERSION. + 9 + 16 + read-only + + + SECURE_BOOT_DISABLE_FAST_WAKE_ERR + Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + 25 + 1 + read-only + + + HYS_EN_PAD_ERR + Indicates a programming error of HYS_EN_PAD. + 26 + 1 + read-only + + + DCDC_VSET_ERR + Indicates a programming error of DCDC_VSET. + 27 + 5 + read-only + + + + + RD_REPEAT_ERR4 + Programming error record register 4 of BLOCK0. + 0x18C + 0x20 + + + _0PXA_TIEH_SEL_0_ERR + Indicates a programming error of 0PXA_TIEH_SEL_0. + 0 + 2 + read-only + + + _0PXA_TIEH_SEL_1_ERR + Indicates a programming error of 0PXA_TIEH_SEL_1. + 2 + 2 + read-only + + + _0PXA_TIEH_SEL_2_ERR + Indicates a programming error of 0PXA_TIEH_SEL_2. + 4 + 2 + read-only + + + _0PXA_TIEH_SEL_3_ERR + Indicates a programming error of 0PXA_TIEH_SEL_3. + 6 + 2 + read-only + + + KM_DISABLE_DEPLOY_MODE_ERR + TBD. + 8 + 4 + read-only + + + USB_DEVICE_DREFL_ERR + Indicates a programming error of USB_DEVICE_DREFL. + 12 + 2 + read-only + + + USB_OTG11_DREFL_ERR + Indicates a programming error of USB_OTG11_DREFL. + 14 + 2 + read-only + + + HP_PWR_SRC_SEL_ERR + Indicates a programming error of HP_PWR_SRC_SEL. + 18 + 1 + read-only + + + DCDC_VSET_EN_ERR + Indicates a programming error of DCDC_VSET_EN. + 19 + 1 + read-only + + + DIS_WDT_ERR + Indicates a programming error of DIS_WDT. + 20 + 1 + read-only + + + DIS_SWD_ERR + Indicates a programming error of DIS_SWD. + 21 + 1 + read-only + + + + + RD_RS_ERR0 + Programming error record register 0 of BLOCK1-10. + 0x1C0 + 0x20 + + + MAC_SYS_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + MAC_SYS_FAIL + 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART1_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART1_FAIL + 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + USR_DATA_ERR_NUM + The value of this signal means the number of error bytes. + 8 + 3 + read-only + + + USR_DATA_FAIL + 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 11 + 1 + read-only + + + KEY0_ERR_NUM + The value of this signal means the number of error bytes. + 12 + 3 + read-only + + + KEY0_FAIL + 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. + 15 + 1 + read-only + + + KEY1_ERR_NUM + The value of this signal means the number of error bytes. + 16 + 3 + read-only + + + KEY1_FAIL + 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. + 19 + 1 + read-only + + + KEY2_ERR_NUM + The value of this signal means the number of error bytes. + 20 + 3 + read-only + + + KEY2_FAIL + 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. + 23 + 1 + read-only + + + KEY3_ERR_NUM + The value of this signal means the number of error bytes. + 24 + 3 + read-only + + + KEY3_FAIL + 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. + 27 + 1 + read-only + + + KEY4_ERR_NUM + The value of this signal means the number of error bytes. + 28 + 3 + read-only + + + KEY4_FAIL + 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. + 31 + 1 + read-only + + + + + RD_RS_ERR1 + Programming error record register 1 of BLOCK1-10. + 0x1C4 + 0x20 + + + KEY5_ERR_NUM + The value of this signal means the number of error bytes. + 0 + 3 + read-only + + + KEY5_FAIL + 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6. + 3 + 1 + read-only + + + SYS_PART2_ERR_NUM + The value of this signal means the number of error bytes. + 4 + 3 + read-only + + + SYS_PART2_FAIL + 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. + 7 + 1 + read-only + + + + + CLK + eFuse clcok configuration register. + 0x1C8 + 0x20 + + + MEM_FORCE_PD + Set this bit to force eFuse SRAM into power-saving mode. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit and force to activate clock signal of eFuse SRAM. + 1 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force eFuse SRAM into working mode. + 2 + 1 + read-write + + + EN + Set this bit to force enable eFuse register configuration clock signal. + 16 + 1 + read-write + + + + + CONF + eFuse operation mode configuraiton register + 0x1CC + 0x20 + + + OP_CODE + 0x5A5A: programming operation command 0x5AA5: read operation command. + 0 + 16 + read-write + + + CFG_ECDSA_BLK + Configures which block to use for ECDSA key output. + 16 + 4 + read-write + + + + + STATUS + eFuse status register. + 0x1D0 + 0x20 + + + STATE + Indicates the state of the eFuse state machine. + 0 + 4 + read-only + + + OTP_LOAD_SW + The value of OTP_LOAD_SW. + 4 + 1 + read-only + + + OTP_VDDQ_C_SYNC2 + The value of OTP_VDDQ_C_SYNC2. + 5 + 1 + read-only + + + OTP_STROBE_SW + The value of OTP_STROBE_SW. + 6 + 1 + read-only + + + OTP_CSB_SW + The value of OTP_CSB_SW. + 7 + 1 + read-only + + + OTP_PGENB_SW + The value of OTP_PGENB_SW. + 8 + 1 + read-only + + + OTP_VDDQ_IS_SW + The value of OTP_VDDQ_IS_SW. + 9 + 1 + read-only + + + BLK0_VALID_BIT_CNT + Indicates the number of block valid bit. + 10 + 10 + read-only + + + CUR_ECDSA_BLK + Indicates which block is used for ECDSA key output. + 20 + 4 + read-only + + + + + CMD + eFuse command register. + 0x1D4 + 0x20 + + + READ_CMD + Set this bit to send read command. + 0 + 1 + read-write + + + PGM_CMD + Set this bit to send programming command. + 1 + 1 + read-write + + + BLK_NUM + The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. + 2 + 4 + read-write + + + + + INT_RAW + eFuse raw interrupt register. + 0x1D8 + 0x20 + + + READ_DONE_INT_RAW + The raw bit signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_RAW + The raw bit signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ST + eFuse interrupt status register. + 0x1DC + 0x20 + + + READ_DONE_INT_ST + The status signal for read_done interrupt. + 0 + 1 + read-only + + + PGM_DONE_INT_ST + The status signal for pgm_done interrupt. + 1 + 1 + read-only + + + + + INT_ENA + eFuse interrupt enable register. + 0x1E0 + 0x20 + + + READ_DONE_INT_ENA + The enable signal for read_done interrupt. + 0 + 1 + read-write + + + PGM_DONE_INT_ENA + The enable signal for pgm_done interrupt. + 1 + 1 + read-write + + + + + INT_CLR + eFuse interrupt clear register. + 0x1E4 + 0x20 + + + READ_DONE_INT_CLR + The clear signal for read_done interrupt. + 0 + 1 + write-only + + + PGM_DONE_INT_CLR + The clear signal for pgm_done interrupt. + 1 + 1 + write-only + + + + + DAC_CONF + Controls the eFuse programming voltage. + 0x1E8 + 0x20 + 0x0001FE17 + + + DAC_CLK_DIV + Controls the division factor of the rising clock of the programming voltage. + 0 + 8 + read-write + + + DAC_CLK_PAD_SEL + Don't care. + 8 + 1 + read-write + + + DAC_NUM + Controls the rising period of the programming voltage. + 9 + 8 + read-write + + + OE_CLR + Reduces the power supply of the programming voltage. + 17 + 1 + read-write + + + + + RD_TIM_CONF + Configures read timing parameters. + 0x1EC + 0x20 + 0x0F010201 + + + THR_A + Configures the read hold time. + 0 + 8 + read-write + + + TRD + Configures the read time. + 8 + 8 + read-write + + + TSUR_A + Configures the read setup time. + 16 + 8 + read-write + + + READ_INIT_NUM + Configures the waiting time of reading eFuse memory. + 24 + 8 + read-write + + + + + WR_TIM_CONF1 + Configurarion register 1 of eFuse programming timing parameters. + 0x1F0 + 0x20 + 0x01266701 + + + TSUP_A + Configures the programming setup time. + 0 + 8 + read-write + + + PWR_ON_NUM + Configures the power up time for VDDQ. + 8 + 16 + read-write + + + THP_A + Configures the programming hold time. + 24 + 8 + read-write + + + + + WR_TIM_CONF2 + Configurarion register 2 of eFuse programming timing parameters. + 0x1F4 + 0x20 + 0x00A00140 + + + PWR_OFF_NUM + Configures the power outage time for VDDQ. + 0 + 16 + read-write + + + TPGM + Configures the active programming time. + 16 + 16 + read-write + + + + + WR_TIM_CONF0_RS_BYPASS + Configurarion register0 of eFuse programming time parameters and rs bypass operation. + 0x1F8 + 0x20 + 0x00002000 + + + BYPASS_RS_CORRECTION + Set this bit to bypass reed solomon correction step. + 0 + 1 + read-write + + + BYPASS_RS_BLK_NUM + Configures block number of programming twice operation. + 1 + 11 + read-write + + + UPDATE + Set this bit to update multi-bit register signals. + 12 + 1 + write-only + + + TPGM_INACTIVE + Configures the inactive programming time. + 13 + 8 + read-write + + + + + DATE + eFuse version register. + 0x1FC + 0x20 + 0x02305050 + + + DATE + Stores eFuse version. + 0 + 28 + read-write + + + + + APB2OTP_WR_DIS + eFuse apb2otp block0 data register1. + 0x800 + 0x20 + + + APB2OTP_BLOCK0_WR_DIS + Otp block0 write disable data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W1 + eFuse apb2otp block0 data register2. + 0x804 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W1 + Otp block0 backup1 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W2 + eFuse apb2otp block0 data register3. + 0x808 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W2 + Otp block0 backup1 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W3 + eFuse apb2otp block0 data register4. + 0x80C + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W3 + Otp block0 backup1 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W4 + eFuse apb2otp block0 data register5. + 0x810 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W4 + Otp block0 backup1 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP1_W5 + eFuse apb2otp block0 data register6. + 0x814 + 0x20 + + + APB2OTP_BLOCK0_BACKUP1_W5 + Otp block0 backup1 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W1 + eFuse apb2otp block0 data register7. + 0x818 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W1 + Otp block0 backup2 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W2 + eFuse apb2otp block0 data register8. + 0x81C + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W2 + Otp block0 backup2 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W3 + eFuse apb2otp block0 data register9. + 0x820 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W3 + Otp block0 backup2 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W4 + eFuse apb2otp block0 data register10. + 0x824 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W4 + Otp block0 backup2 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP2_W5 + eFuse apb2otp block0 data register11. + 0x828 + 0x20 + + + APB2OTP_BLOCK0_BACKUP2_W5 + Otp block0 backup2 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W1 + eFuse apb2otp block0 data register12. + 0x82C + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W1 + Otp block0 backup3 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W2 + eFuse apb2otp block0 data register13. + 0x830 + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W2 + Otp block0 backup3 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W3 + eFuse apb2otp block0 data register14. + 0x834 + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W3 + Otp block0 backup3 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W4 + eFuse apb2otp block0 data register15. + 0x838 + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W4 + Otp block0 backup3 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP3_W5 + eFuse apb2otp block0 data register16. + 0x83C + 0x20 + + + APB2OTP_BLOCK0_BACKUP3_W5 + Otp block0 backup3 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W1 + eFuse apb2otp block0 data register17. + 0x840 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W1 + Otp block0 backup4 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W2 + eFuse apb2otp block0 data register18. + 0x844 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W2 + Otp block0 backup4 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W3 + eFuse apb2otp block0 data register19. + 0x848 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W3 + Otp block0 backup4 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W4 + eFuse apb2otp block0 data register20. + 0x84C + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W4 + Otp block0 backup4 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK0_BACKUP4_W5 + eFuse apb2otp block0 data register21. + 0x850 + 0x20 + + + APB2OTP_BLOCK0_BACKUP4_W5 + Otp block0 backup4 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W1 + eFuse apb2otp block1 data register1. + 0x854 + 0x20 + + + APB2OTP_BLOCK1_W1 + Otp block1 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W2 + eFuse apb2otp block1 data register2. + 0x858 + 0x20 + + + APB2OTP_BLOCK1_W2 + Otp block1 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W3 + eFuse apb2otp block1 data register3. + 0x85C + 0x20 + + + APB2OTP_BLOCK1_W3 + Otp block1 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W4 + eFuse apb2otp block1 data register4. + 0x860 + 0x20 + + + APB2OTP_BLOCK1_W4 + Otp block1 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W5 + eFuse apb2otp block1 data register5. + 0x864 + 0x20 + + + APB2OTP_BLOCK1_W5 + Otp block1 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W6 + eFuse apb2otp block1 data register6. + 0x868 + 0x20 + + + APB2OTP_BLOCK1_W6 + Otp block1 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W7 + eFuse apb2otp block1 data register7. + 0x86C + 0x20 + + + APB2OTP_BLOCK1_W7 + Otp block1 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W8 + eFuse apb2otp block1 data register8. + 0x870 + 0x20 + + + APB2OTP_BLOCK1_W8 + Otp block1 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK1_W9 + eFuse apb2otp block1 data register9. + 0x874 + 0x20 + + + APB2OTP_BLOCK1_W9 + Otp block1 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W1 + eFuse apb2otp block2 data register1. + 0x878 + 0x20 + + + APB2OTP_BLOCK2_W1 + Otp block2 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W2 + eFuse apb2otp block2 data register2. + 0x87C + 0x20 + + + APB2OTP_BLOCK2_W2 + Otp block2 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W3 + eFuse apb2otp block2 data register3. + 0x880 + 0x20 + + + APB2OTP_BLOCK2_W3 + Otp block2 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W4 + eFuse apb2otp block2 data register4. + 0x884 + 0x20 + + + APB2OTP_BLOCK2_W4 + Otp block2 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W5 + eFuse apb2otp block2 data register5. + 0x888 + 0x20 + + + APB2OTP_BLOCK2_W5 + Otp block2 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W6 + eFuse apb2otp block2 data register6. + 0x88C + 0x20 + + + APB2OTP_BLOCK2_W6 + Otp block2 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W7 + eFuse apb2otp block2 data register7. + 0x890 + 0x20 + + + APB2OTP_BLOCK2_W7 + Otp block2 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W8 + eFuse apb2otp block2 data register8. + 0x894 + 0x20 + + + APB2OTP_BLOCK2_W8 + Otp block2 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W9 + eFuse apb2otp block2 data register9. + 0x898 + 0x20 + + + APB2OTP_BLOCK2_W9 + Otp block2 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W10 + eFuse apb2otp block2 data register10. + 0x89C + 0x20 + + + APB2OTP_BLOCK2_W10 + Otp block2 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK2_W11 + eFuse apb2otp block2 data register11. + 0x8A0 + 0x20 + + + APB2OTP_BLOCK2_W11 + Otp block2 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W1 + eFuse apb2otp block3 data register1. + 0x8A4 + 0x20 + + + APB2OTP_BLOCK3_W1 + Otp block3 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W2 + eFuse apb2otp block3 data register2. + 0x8A8 + 0x20 + + + APB2OTP_BLOCK3_W2 + Otp block3 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W3 + eFuse apb2otp block3 data register3. + 0x8AC + 0x20 + + + APB2OTP_BLOCK3_W3 + Otp block3 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W4 + eFuse apb2otp block3 data register4. + 0x8B0 + 0x20 + + + APB2OTP_BLOCK3_W4 + Otp block3 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W5 + eFuse apb2otp block3 data register5. + 0x8B4 + 0x20 + + + APB2OTP_BLOCK3_W5 + Otp block3 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W6 + eFuse apb2otp block3 data register6. + 0x8B8 + 0x20 + + + APB2OTP_BLOCK3_W6 + Otp block3 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W7 + eFuse apb2otp block3 data register7. + 0x8BC + 0x20 + + + APB2OTP_BLOCK3_W7 + Otp block3 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W8 + eFuse apb2otp block3 data register8. + 0x8C0 + 0x20 + + + APB2OTP_BLOCK3_W8 + Otp block3 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W9 + eFuse apb2otp block3 data register9. + 0x8C4 + 0x20 + + + APB2OTP_BLOCK3_W9 + Otp block3 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W10 + eFuse apb2otp block3 data register10. + 0x8C8 + 0x20 + + + APB2OTP_BLOCK3_W10 + Otp block3 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK3_W11 + eFuse apb2otp block3 data register11. + 0x8CC + 0x20 + + + APB2OTP_BLOCK3_W11 + Otp block3 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W1 + eFuse apb2otp block4 data register1. + 0x8D0 + 0x20 + + + APB2OTP_BLOCK4_W1 + Otp block4 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W2 + eFuse apb2otp block4 data register2. + 0x8D4 + 0x20 + + + APB2OTP_BLOCK4_W2 + Otp block4 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W3 + eFuse apb2otp block4 data register3. + 0x8D8 + 0x20 + + + APB2OTP_BLOCK4_W3 + Otp block4 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W4 + eFuse apb2otp block4 data register4. + 0x8DC + 0x20 + + + APB2OTP_BLOCK4_W4 + Otp block4 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W5 + eFuse apb2otp block4 data register5. + 0x8E0 + 0x20 + + + APB2OTP_BLOCK4_W5 + Otp block4 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W6 + eFuse apb2otp block4 data register6. + 0x8E4 + 0x20 + + + APB2OTP_BLOCK4_W6 + Otp block4 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W7 + eFuse apb2otp block4 data register7. + 0x8E8 + 0x20 + + + APB2OTP_BLOCK4_W7 + Otp block4 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W8 + eFuse apb2otp block4 data register8. + 0x8EC + 0x20 + + + APB2OTP_BLOCK4_W8 + Otp block4 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W9 + eFuse apb2otp block4 data register9. + 0x8F0 + 0x20 + + + APB2OTP_BLOCK4_W9 + Otp block4 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W10 + eFuse apb2otp block4 data registe10. + 0x8F4 + 0x20 + + + APB2OTP_BLOCK4_W10 + Otp block4 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK4_W11 + eFuse apb2otp block4 data register11. + 0x8F8 + 0x20 + + + APB2OTP_BLOCK4_W11 + Otp block4 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W1 + eFuse apb2otp block5 data register1. + 0x8FC + 0x20 + + + APB2OTP_BLOCK5_W1 + Otp block5 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W2 + eFuse apb2otp block5 data register2. + 0x900 + 0x20 + + + APB2OTP_BLOCK5_W2 + Otp block5 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W3 + eFuse apb2otp block5 data register3. + 0x904 + 0x20 + + + APB2OTP_BLOCK5_W3 + Otp block5 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W4 + eFuse apb2otp block5 data register4. + 0x908 + 0x20 + + + APB2OTP_BLOCK5_W4 + Otp block5 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W5 + eFuse apb2otp block5 data register5. + 0x90C + 0x20 + + + APB2OTP_BLOCK5_W5 + Otp block5 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W6 + eFuse apb2otp block5 data register6. + 0x910 + 0x20 + + + APB2OTP_BLOCK5_W6 + Otp block5 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W7 + eFuse apb2otp block5 data register7. + 0x914 + 0x20 + + + APB2OTP_BLOCK5_W7 + Otp block5 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W8 + eFuse apb2otp block5 data register8. + 0x918 + 0x20 + + + APB2OTP_BLOCK5_W8 + Otp block5 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W9 + eFuse apb2otp block5 data register9. + 0x91C + 0x20 + + + APB2OTP_BLOCK5_W9 + Otp block5 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W10 + eFuse apb2otp block5 data register10. + 0x920 + 0x20 + + + APB2OTP_BLOCK5_W10 + Otp block5 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK5_W11 + eFuse apb2otp block5 data register11. + 0x924 + 0x20 + + + APB2OTP_BLOCK5_W11 + Otp block5 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W1 + eFuse apb2otp block6 data register1. + 0x928 + 0x20 + + + APB2OTP_BLOCK6_W1 + Otp block6 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W2 + eFuse apb2otp block6 data register2. + 0x92C + 0x20 + + + APB2OTP_BLOCK6_W2 + Otp block6 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W3 + eFuse apb2otp block6 data register3. + 0x930 + 0x20 + + + APB2OTP_BLOCK6_W3 + Otp block6 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W4 + eFuse apb2otp block6 data register4. + 0x934 + 0x20 + + + APB2OTP_BLOCK6_W4 + Otp block6 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W5 + eFuse apb2otp block6 data register5. + 0x938 + 0x20 + + + APB2OTP_BLOCK6_W5 + Otp block6 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W6 + eFuse apb2otp block6 data register6. + 0x93C + 0x20 + + + APB2OTP_BLOCK6_W6 + Otp block6 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W7 + eFuse apb2otp block6 data register7. + 0x940 + 0x20 + + + APB2OTP_BLOCK6_W7 + Otp block6 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W8 + eFuse apb2otp block6 data register8. + 0x944 + 0x20 + + + APB2OTP_BLOCK6_W8 + Otp block6 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W9 + eFuse apb2otp block6 data register9. + 0x948 + 0x20 + + + APB2OTP_BLOCK6_W9 + Otp block6 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W10 + eFuse apb2otp block6 data register10. + 0x94C + 0x20 + + + APB2OTP_BLOCK6_W10 + Otp block6 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK6_W11 + eFuse apb2otp block6 data register11. + 0x950 + 0x20 + + + APB2OTP_BLOCK6_W11 + Otp block6 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W1 + eFuse apb2otp block7 data register1. + 0x954 + 0x20 + + + APB2OTP_BLOCK7_W1 + Otp block7 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W2 + eFuse apb2otp block7 data register2. + 0x958 + 0x20 + + + APB2OTP_BLOCK7_W2 + Otp block7 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W3 + eFuse apb2otp block7 data register3. + 0x95C + 0x20 + + + APB2OTP_BLOCK7_W3 + Otp block7 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W4 + eFuse apb2otp block7 data register4. + 0x960 + 0x20 + + + APB2OTP_BLOCK7_W4 + Otp block7 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W5 + eFuse apb2otp block7 data register5. + 0x964 + 0x20 + + + APB2OTP_BLOCK7_W5 + Otp block7 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W6 + eFuse apb2otp block7 data register6. + 0x968 + 0x20 + + + APB2OTP_BLOCK7_W6 + Otp block7 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W7 + eFuse apb2otp block7 data register7. + 0x96C + 0x20 + + + APB2OTP_BLOCK7_W7 + Otp block7 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W8 + eFuse apb2otp block7 data register8. + 0x970 + 0x20 + + + APB2OTP_BLOCK7_W8 + Otp block7 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W9 + eFuse apb2otp block7 data register9. + 0x974 + 0x20 + + + APB2OTP_BLOCK7_W9 + Otp block7 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W10 + eFuse apb2otp block7 data register10. + 0x978 + 0x20 + + + APB2OTP_BLOCK7_W10 + Otp block7 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK7_W11 + eFuse apb2otp block7 data register11. + 0x97C + 0x20 + + + APB2OTP_BLOCK7_W11 + Otp block7 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W1 + eFuse apb2otp block8 data register1. + 0x980 + 0x20 + + + APB2OTP_BLOCK8_W1 + Otp block8 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W2 + eFuse apb2otp block8 data register2. + 0x984 + 0x20 + + + APB2OTP_BLOCK8_W2 + Otp block8 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W3 + eFuse apb2otp block8 data register3. + 0x988 + 0x20 + + + APB2OTP_BLOCK8_W3 + Otp block8 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W4 + eFuse apb2otp block8 data register4. + 0x98C + 0x20 + + + APB2OTP_BLOCK8_W4 + Otp block8 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W5 + eFuse apb2otp block8 data register5. + 0x990 + 0x20 + + + APB2OTP_BLOCK8_W5 + Otp block8 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W6 + eFuse apb2otp block8 data register6. + 0x994 + 0x20 + + + APB2OTP_BLOCK8_W6 + Otp block8 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W7 + eFuse apb2otp block8 data register7. + 0x998 + 0x20 + + + APB2OTP_BLOCK8_W7 + Otp block8 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W8 + eFuse apb2otp block8 data register8. + 0x99C + 0x20 + + + APB2OTP_BLOCK8_W8 + Otp block8 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W9 + eFuse apb2otp block8 data register9. + 0x9A0 + 0x20 + + + APB2OTP_BLOCK8_W9 + Otp block8 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W10 + eFuse apb2otp block8 data register10. + 0x9A4 + 0x20 + + + APB2OTP_BLOCK8_W10 + Otp block8 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK8_W11 + eFuse apb2otp block8 data register11. + 0x9A8 + 0x20 + + + APB2OTP_BLOCK8_W11 + Otp block8 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W1 + eFuse apb2otp block9 data register1. + 0x9AC + 0x20 + + + APB2OTP_BLOCK9_W1 + Otp block9 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W2 + eFuse apb2otp block9 data register2. + 0x9B0 + 0x20 + + + APB2OTP_BLOCK9_W2 + Otp block9 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W3 + eFuse apb2otp block9 data register3. + 0x9B4 + 0x20 + + + APB2OTP_BLOCK9_W3 + Otp block9 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W4 + eFuse apb2otp block9 data register4. + 0x9B8 + 0x20 + + + APB2OTP_BLOCK9_W4 + Otp block9 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W5 + eFuse apb2otp block9 data register5. + 0x9BC + 0x20 + + + APB2OTP_BLOCK9_W5 + Otp block9 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W6 + eFuse apb2otp block9 data register6. + 0x9C0 + 0x20 + + + APB2OTP_BLOCK9_W6 + Otp block9 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W7 + eFuse apb2otp block9 data register7. + 0x9C4 + 0x20 + + + APB2OTP_BLOCK9_W7 + Otp block9 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W8 + eFuse apb2otp block9 data register8. + 0x9C8 + 0x20 + + + APB2OTP_BLOCK9_W8 + Otp block9 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W9 + eFuse apb2otp block9 data register9. + 0x9CC + 0x20 + + + APB2OTP_BLOCK9_W9 + Otp block9 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W10 + eFuse apb2otp block9 data register10. + 0x9D0 + 0x20 + + + APB2OTP_BLOCK9_W10 + Otp block9 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK9_W11 + eFuse apb2otp block9 data register11. + 0x9D4 + 0x20 + + + APB2OTP_BLOCK9_W11 + Otp block9 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W1 + eFuse apb2otp block10 data register1. + 0x9D8 + 0x20 + + + APB2OTP_BLOCK10_W1 + Otp block10 word1 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W2 + eFuse apb2otp block10 data register2. + 0x9DC + 0x20 + + + APB2OTP_BLOCK10_W2 + Otp block10 word2 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W3 + eFuse apb2otp block10 data register3. + 0x9E0 + 0x20 + + + APB2OTP_BLOCK10_W3 + Otp block10 word3 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W4 + eFuse apb2otp block10 data register4. + 0x9E4 + 0x20 + + + APB2OTP_BLOCK10_W4 + Otp block10 word4 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W5 + eFuse apb2otp block10 data register5. + 0x9E8 + 0x20 + + + APB2OTP_BLOCK10_W5 + Otp block10 word5 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W6 + eFuse apb2otp block10 data register6. + 0x9EC + 0x20 + + + APB2OTP_BLOCK10_W6 + Otp block10 word6 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W7 + eFuse apb2otp block10 data register7. + 0x9F0 + 0x20 + + + APB2OTP_BLOCK10_W7 + Otp block10 word7 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W8 + eFuse apb2otp block10 data register8. + 0x9F4 + 0x20 + + + APB2OTP_BLOCK10_W8 + Otp block10 word8 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W9 + eFuse apb2otp block10 data register9. + 0x9F8 + 0x20 + + + APB2OTP_BLOCK10_W9 + Otp block10 word9 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W10 + eFuse apb2otp block10 data register10. + 0x9FC + 0x20 + + + APB2OTP_BLOCK19_W10 + Otp block10 word10 data. + 0 + 32 + read-only + + + + + APB2OTP_BLK10_W11 + eFuse apb2otp block10 data register11. + 0xA00 + 0x20 + + + APB2OTP_BLOCK10_W11 + Otp block10 word11 data. + 0 + 32 + read-only + + + + + APB2OTP_EN + eFuse apb2otp enable configuration register. + 0xA08 + 0x20 + + + APB2OTP_APB2OTP_EN + Apb2otp mode enable signal. + 0 + 1 + read-write + + + + + + + GPIO + General Purpose Input/Output + GPIO + 0x500E0000 + + 0x0 + 0x5F8 + registers + + + GPIO_INT0 + 74 + + + GPIO_INT1 + 75 + + + GPIO_INT2 + 76 + + + GPIO_INT3 + 77 + + + GPIO_PAD_COMP + 78 + + + + BT_SELECT + GPIO bit select register + 0x0 + 0x20 + + + BT_SEL + GPIO bit select register + 0 + 32 + read-write + + + + + OUT + GPIO output register for GPIO0-31 + 0x4 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO0-31 + 0 + 32 + read-write + + + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0x8 + 0x20 + + + OUT_W1TS + GPIO output set register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0xC + 0x20 + + + OUT_W1TC + GPIO output clear register for GPIO0-31 + 0 + 32 + write-only + + + + + OUT1 + GPIO output register for GPIO32-56 + 0x10 + 0x20 + + + DATA_ORIG + GPIO output register for GPIO32-56 + 0 + 25 + read-write + + + + + OUT1_W1TS + GPIO output set register for GPIO32-56 + 0x14 + 0x20 + + + OUT1_W1TS + GPIO output set register for GPIO32-56 + 0 + 25 + write-only + + + + + OUT1_W1TC + GPIO output clear register for GPIO32-56 + 0x18 + 0x20 + + + OUT1_W1TC + GPIO output clear register for GPIO32-56 + 0 + 25 + write-only + + + + + ENABLE + GPIO output enable register for GPIO0-31 + 0x20 + 0x20 + + + DATA + GPIO output enable register for GPIO0-31 + 0 + 32 + read-write + + + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0x24 + 0x20 + + + ENABLE_W1TS + GPIO output enable set register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0x28 + 0x20 + + + ENABLE_W1TC + GPIO output enable clear register for GPIO0-31 + 0 + 32 + write-only + + + + + ENABLE1 + GPIO output enable register for GPIO32-56 + 0x2C + 0x20 + + + DATA + GPIO output enable register for GPIO32-56 + 0 + 25 + read-write + + + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-56 + 0x30 + 0x20 + + + ENABLE1_W1TS + GPIO output enable set register for GPIO32-56 + 0 + 25 + write-only + + + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-56 + 0x34 + 0x20 + + + ENABLE1_W1TC + GPIO output enable clear register for GPIO32-56 + 0 + 25 + write-only + + + + + STRAP + pad strapping register + 0x38 + 0x20 + + + STRAPPING + pad strapping register + 0 + 16 + read-only + + + + + IN + GPIO input register for GPIO0-31 + 0x3C + 0x20 + + + DATA_NEXT + GPIO input register for GPIO0-31 + 0 + 32 + read-only + + + + + IN1 + GPIO input register for GPIO32-56 + 0x40 + 0x20 + + + DATA_NEXT + GPIO input register for GPIO32-56 + 0 + 25 + read-only + + + + + STATUS + GPIO interrupt status register for GPIO0-31 + 0x44 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO0-31 + 0 + 32 + read-write + + + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0x48 + 0x20 + + + STATUS_W1TS + GPIO interrupt status set register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0x4C + 0x20 + + + STATUS_W1TC + GPIO interrupt status clear register for GPIO0-31 + 0 + 32 + write-only + + + + + STATUS1 + GPIO interrupt status register for GPIO32-56 + 0x50 + 0x20 + + + INTERRUPT + GPIO interrupt status register for GPIO32-56 + 0 + 25 + read-write + + + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-56 + 0x54 + 0x20 + + + STATUS1_W1TS + GPIO interrupt status set register for GPIO32-56 + 0 + 25 + write-only + + + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-56 + 0x58 + 0x20 + + + STATUS1_W1TC + GPIO interrupt status clear register for GPIO32-56 + 0 + 25 + write-only + + + + + INTR_0 + GPIO interrupt 0 status register for GPIO0-31 + 0x5C + 0x20 + + + INT_0 + GPIO interrupt 0 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_0 + GPIO interrupt 0 status register for GPIO32-56 + 0x60 + 0x20 + + + INT1_0 + GPIO interrupt 0 status register for GPIO32-56 + 0 + 25 + read-only + + + + + INTR_1 + GPIO interrupt 1 status register for GPIO0-31 + 0x64 + 0x20 + + + INT_1 + GPIO interrupt 1 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_1 + GPIO interrupt 1 status register for GPIO32-56 + 0x68 + 0x20 + + + INT1_1 + GPIO interrupt 1 status register for GPIO32-56 + 0 + 25 + read-only + + + + + STATUS_NEXT + GPIO interrupt source register for GPIO0-31 + 0x6C + 0x20 + + + STATUS_INTERRUPT_NEXT + GPIO interrupt source register for GPIO0-31 + 0 + 32 + read-only + + + + + STATUS_NEXT1 + GPIO interrupt source register for GPIO32-56 + 0x70 + 0x20 + + + STATUS_INTERRUPT_NEXT1 + GPIO interrupt source register for GPIO32-56 + 0 + 25 + read-only + + + + + 57 + 0x4 + PIN%s + GPIO pin configuration register + 0x74 + 0x20 + + + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 0 + 2 + read-write + + + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. + 2 + 1 + read-write + + + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. + 3 + 2 + read-write + + + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + 7 + 3 + read-write + + + WAKEUP_ENABLE + set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + 10 + 1 + read-write + + + CONFIG + reserved + 11 + 2 + read-write + + + INT_ENA + set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + 13 + 5 + read-write + + + + + FUNC1_IN_SEL_CFG + GPIO input function configuration register + 0x15C + 0x20 + 0x0000003F + + + FUNC1_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC1_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG1_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC2_IN_SEL_CFG + GPIO input function configuration register + 0x160 + 0x20 + 0x0000003F + + + FUNC2_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC2_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG2_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC3_IN_SEL_CFG + GPIO input function configuration register + 0x164 + 0x20 + 0x0000003F + + + FUNC3_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC3_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG3_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC4_IN_SEL_CFG + GPIO input function configuration register + 0x168 + 0x20 + 0x0000003F + + + FUNC4_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC4_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG4_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC5_IN_SEL_CFG + GPIO input function configuration register + 0x16C + 0x20 + 0x0000003F + + + FUNC5_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC5_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG5_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC6_IN_SEL_CFG + GPIO input function configuration register + 0x170 + 0x20 + 0x0000003F + + + FUNC6_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC6_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG6_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC7_IN_SEL_CFG + GPIO input function configuration register + 0x174 + 0x20 + 0x0000003F + + + FUNC7_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC7_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG7_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC8_IN_SEL_CFG + GPIO input function configuration register + 0x178 + 0x20 + 0x0000003F + + + FUNC8_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC8_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG8_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC9_IN_SEL_CFG + GPIO input function configuration register + 0x17C + 0x20 + 0x0000003F + + + FUNC9_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC9_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG9_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC10_IN_SEL_CFG + GPIO input function configuration register + 0x180 + 0x20 + 0x0000003E + + + FUNC10_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC10_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG10_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC11_IN_SEL_CFG + GPIO input function configuration register + 0x184 + 0x20 + 0x0000003E + + + FUNC11_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC11_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG11_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC12_IN_SEL_CFG + GPIO input function configuration register + 0x188 + 0x20 + 0x0000003E + + + FUNC12_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC12_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG12_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC13_IN_SEL_CFG + GPIO input function configuration register + 0x18C + 0x20 + 0x0000003E + + + FUNC13_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC13_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG13_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC14_IN_SEL_CFG + GPIO input function configuration register + 0x190 + 0x20 + 0x0000003E + + + FUNC14_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC14_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG14_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC15_IN_SEL_CFG + GPIO input function configuration register + 0x194 + 0x20 + 0x0000003E + + + FUNC15_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC15_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG15_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC16_IN_SEL_CFG + GPIO input function configuration register + 0x198 + 0x20 + 0x0000003E + + + FUNC16_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC16_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG16_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC17_IN_SEL_CFG + GPIO input function configuration register + 0x19C + 0x20 + 0x0000003E + + + FUNC17_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC17_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG17_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC18_IN_SEL_CFG + GPIO input function configuration register + 0x1A0 + 0x20 + 0x0000003E + + + FUNC18_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC18_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG18_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC19_IN_SEL_CFG + GPIO input function configuration register + 0x1A4 + 0x20 + 0x0000003E + + + FUNC19_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC19_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG19_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC20_IN_SEL_CFG + GPIO input function configuration register + 0x1A8 + 0x20 + 0x0000003E + + + FUNC20_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC20_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG20_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC21_IN_SEL_CFG + GPIO input function configuration register + 0x1AC + 0x20 + 0x0000003E + + + FUNC21_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC21_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG21_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC22_IN_SEL_CFG + GPIO input function configuration register + 0x1B0 + 0x20 + 0x0000003E + + + FUNC22_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC22_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG22_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC23_IN_SEL_CFG + GPIO input function configuration register + 0x1B4 + 0x20 + 0x0000003E + + + FUNC23_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC23_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG23_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC24_IN_SEL_CFG + GPIO input function configuration register + 0x1B8 + 0x20 + 0x0000003E + + + FUNC24_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC24_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG24_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC25_IN_SEL_CFG + GPIO input function configuration register + 0x1BC + 0x20 + 0x0000003E + + + FUNC25_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC25_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG25_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC26_IN_SEL_CFG + GPIO input function configuration register + 0x1C0 + 0x20 + 0x0000003E + + + FUNC26_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC26_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG26_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC27_IN_SEL_CFG + GPIO input function configuration register + 0x1C4 + 0x20 + 0x0000003E + + + FUNC27_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC27_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG27_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC28_IN_SEL_CFG + GPIO input function configuration register + 0x1C8 + 0x20 + 0x0000003E + + + FUNC28_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC28_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG28_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC29_IN_SEL_CFG + GPIO input function configuration register + 0x1CC + 0x20 + 0x0000003E + + + FUNC29_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC29_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG29_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC30_IN_SEL_CFG + GPIO input function configuration register + 0x1D0 + 0x20 + 0x0000003E + + + FUNC30_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC30_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG30_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC31_IN_SEL_CFG + GPIO input function configuration register + 0x1D4 + 0x20 + 0x0000003E + + + FUNC31_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC31_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG31_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC32_IN_SEL_CFG + GPIO input function configuration register + 0x1D8 + 0x20 + 0x0000003E + + + FUNC32_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC32_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG32_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC33_IN_SEL_CFG + GPIO input function configuration register + 0x1DC + 0x20 + 0x0000003E + + + FUNC33_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC33_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG33_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC34_IN_SEL_CFG + GPIO input function configuration register + 0x1E0 + 0x20 + 0x0000003E + + + FUNC34_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC34_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG34_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC35_IN_SEL_CFG + GPIO input function configuration register + 0x1E4 + 0x20 + 0x0000003E + + + FUNC35_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC35_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG35_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC36_IN_SEL_CFG + GPIO input function configuration register + 0x1E8 + 0x20 + 0x0000003E + + + FUNC36_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC36_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG36_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC37_IN_SEL_CFG + GPIO input function configuration register + 0x1EC + 0x20 + 0x0000003E + + + FUNC37_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC37_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG37_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC38_IN_SEL_CFG + GPIO input function configuration register + 0x1F0 + 0x20 + 0x0000003E + + + FUNC38_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC38_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG38_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC39_IN_SEL_CFG + GPIO input function configuration register + 0x1F4 + 0x20 + 0x0000003E + + + FUNC39_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC39_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG39_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC40_IN_SEL_CFG + GPIO input function configuration register + 0x1F8 + 0x20 + 0x0000003E + + + FUNC40_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC40_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG40_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC41_IN_SEL_CFG + GPIO input function configuration register + 0x1FC + 0x20 + 0x0000003E + + + FUNC41_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC41_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG41_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC42_IN_SEL_CFG + GPIO input function configuration register + 0x200 + 0x20 + 0x0000003E + + + FUNC42_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC42_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG42_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC43_IN_SEL_CFG + GPIO input function configuration register + 0x204 + 0x20 + 0x0000003E + + + FUNC43_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC43_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG43_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC44_IN_SEL_CFG + GPIO input function configuration register + 0x208 + 0x20 + 0x0000003E + + + FUNC44_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC44_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG44_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC45_IN_SEL_CFG + GPIO input function configuration register + 0x20C + 0x20 + 0x0000003E + + + FUNC45_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC45_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG45_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC47_IN_SEL_CFG + GPIO input function configuration register + 0x214 + 0x20 + 0x0000003E + + + FUNC47_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC47_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG47_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC48_IN_SEL_CFG + GPIO input function configuration register + 0x218 + 0x20 + 0x0000003E + + + FUNC48_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC48_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG48_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC49_IN_SEL_CFG + GPIO input function configuration register + 0x21C + 0x20 + 0x0000003E + + + FUNC49_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC49_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG49_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC50_IN_SEL_CFG + GPIO input function configuration register + 0x220 + 0x20 + 0x0000003E + + + FUNC50_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC50_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG50_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC51_IN_SEL_CFG + GPIO input function configuration register + 0x224 + 0x20 + 0x0000003E + + + FUNC51_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC51_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG51_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC52_IN_SEL_CFG + GPIO input function configuration register + 0x228 + 0x20 + 0x0000003E + + + FUNC52_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC52_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG52_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC53_IN_SEL_CFG + GPIO input function configuration register + 0x22C + 0x20 + 0x0000003E + + + FUNC53_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC53_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG53_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC54_IN_SEL_CFG + GPIO input function configuration register + 0x230 + 0x20 + 0x0000003E + + + FUNC54_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC54_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG54_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC55_IN_SEL_CFG + GPIO input function configuration register + 0x234 + 0x20 + 0x0000003E + + + FUNC55_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC55_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG55_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC56_IN_SEL_CFG + GPIO input function configuration register + 0x238 + 0x20 + 0x0000003E + + + FUNC56_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC56_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG56_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC57_IN_SEL_CFG + GPIO input function configuration register + 0x23C + 0x20 + 0x0000003E + + + FUNC57_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC57_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG57_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC58_IN_SEL_CFG + GPIO input function configuration register + 0x240 + 0x20 + 0x0000003E + + + FUNC58_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC58_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG58_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC59_IN_SEL_CFG + GPIO input function configuration register + 0x244 + 0x20 + 0x0000003E + + + FUNC59_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC59_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG59_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC60_IN_SEL_CFG + GPIO input function configuration register + 0x248 + 0x20 + 0x0000003E + + + FUNC60_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC60_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG60_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC61_IN_SEL_CFG + GPIO input function configuration register + 0x24C + 0x20 + 0x0000003E + + + FUNC61_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC61_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG61_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC62_IN_SEL_CFG + GPIO input function configuration register + 0x250 + 0x20 + 0x0000003E + + + FUNC62_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC62_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG62_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC63_IN_SEL_CFG + GPIO input function configuration register + 0x254 + 0x20 + 0x0000003E + + + FUNC63_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC63_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG63_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC64_IN_SEL_CFG + GPIO input function configuration register + 0x258 + 0x20 + 0x0000003E + + + FUNC64_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC64_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG64_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC65_IN_SEL_CFG + GPIO input function configuration register + 0x25C + 0x20 + 0x0000003E + + + FUNC65_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC65_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG65_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC66_IN_SEL_CFG + GPIO input function configuration register + 0x260 + 0x20 + 0x0000003E + + + FUNC66_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC66_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG66_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC68_IN_SEL_CFG + GPIO input function configuration register + 0x268 + 0x20 + 0x0000003F + + + FUNC68_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC68_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG68_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC69_IN_SEL_CFG + GPIO input function configuration register + 0x26C + 0x20 + 0x0000003F + + + FUNC69_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC69_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG69_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC70_IN_SEL_CFG + GPIO input function configuration register + 0x270 + 0x20 + 0x0000003F + + + FUNC70_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC70_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG70_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC71_IN_SEL_CFG + GPIO input function configuration register + 0x274 + 0x20 + 0x0000003F + + + FUNC71_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC71_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG71_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC74_IN_SEL_CFG + GPIO input function configuration register + 0x280 + 0x20 + 0x0000003E + + + FUNC74_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC74_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG74_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC75_IN_SEL_CFG + GPIO input function configuration register + 0x284 + 0x20 + 0x0000003E + + + FUNC75_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC75_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG75_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC76_IN_SEL_CFG + GPIO input function configuration register + 0x288 + 0x20 + 0x0000003E + + + FUNC76_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC76_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG76_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC77_IN_SEL_CFG + GPIO input function configuration register + 0x28C + 0x20 + 0x0000003E + + + FUNC77_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC77_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG77_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC78_IN_SEL_CFG + GPIO input function configuration register + 0x290 + 0x20 + 0x0000003E + + + FUNC78_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC78_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG78_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC80_IN_SEL_CFG + GPIO input function configuration register + 0x298 + 0x20 + 0x0000003F + + + FUNC80_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC80_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG80_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC83_IN_SEL_CFG + GPIO input function configuration register + 0x2A4 + 0x20 + 0x0000003F + + + FUNC83_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC83_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG83_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC86_IN_SEL_CFG + GPIO input function configuration register + 0x2B0 + 0x20 + 0x0000003F + + + FUNC86_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC86_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG86_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC89_IN_SEL_CFG + GPIO input function configuration register + 0x2BC + 0x20 + 0x0000003E + + + FUNC89_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC89_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG89_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC90_IN_SEL_CFG + GPIO input function configuration register + 0x2C0 + 0x20 + 0x0000003E + + + FUNC90_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC90_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG90_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC91_IN_SEL_CFG + GPIO input function configuration register + 0x2C4 + 0x20 + 0x0000003E + + + FUNC91_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC91_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG91_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC92_IN_SEL_CFG + GPIO input function configuration register + 0x2C8 + 0x20 + 0x0000003E + + + FUNC92_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC92_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG92_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC93_IN_SEL_CFG + GPIO input function configuration register + 0x2CC + 0x20 + 0x0000003E + + + FUNC93_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC93_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG93_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC94_IN_SEL_CFG + GPIO input function configuration register + 0x2D0 + 0x20 + 0x0000003E + + + FUNC94_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC94_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG94_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC95_IN_SEL_CFG + GPIO input function configuration register + 0x2D4 + 0x20 + 0x0000003E + + + FUNC95_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC95_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG95_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC96_IN_SEL_CFG + GPIO input function configuration register + 0x2D8 + 0x20 + 0x0000003E + + + FUNC96_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC96_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG96_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC97_IN_SEL_CFG + GPIO input function configuration register + 0x2DC + 0x20 + 0x0000003E + + + FUNC97_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC97_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG97_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC98_IN_SEL_CFG + GPIO input function configuration register + 0x2E0 + 0x20 + 0x0000003E + + + FUNC98_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC98_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG98_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC99_IN_SEL_CFG + GPIO input function configuration register + 0x2E4 + 0x20 + 0x0000003E + + + FUNC99_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC99_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG99_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC100_IN_SEL_CFG + GPIO input function configuration register + 0x2E8 + 0x20 + 0x0000003E + + + FUNC100_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC100_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG100_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC101_IN_SEL_CFG + GPIO input function configuration register + 0x2EC + 0x20 + 0x0000003E + + + FUNC101_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC101_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG101_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC102_IN_SEL_CFG + GPIO input function configuration register + 0x2F0 + 0x20 + 0x0000003E + + + FUNC102_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC102_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG102_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC103_IN_SEL_CFG + GPIO input function configuration register + 0x2F4 + 0x20 + 0x0000003E + + + FUNC103_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC103_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG103_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC104_IN_SEL_CFG + GPIO input function configuration register + 0x2F8 + 0x20 + 0x0000003E + + + FUNC104_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC104_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG104_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC105_IN_SEL_CFG + GPIO input function configuration register + 0x2FC + 0x20 + 0x0000003E + + + FUNC105_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC105_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG105_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC106_IN_SEL_CFG + GPIO input function configuration register + 0x300 + 0x20 + 0x0000003E + + + FUNC106_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC106_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG106_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC107_IN_SEL_CFG + GPIO input function configuration register + 0x304 + 0x20 + 0x0000003E + + + FUNC107_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC107_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG107_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC108_IN_SEL_CFG + GPIO input function configuration register + 0x308 + 0x20 + 0x0000003E + + + FUNC108_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC108_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG108_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC109_IN_SEL_CFG + GPIO input function configuration register + 0x30C + 0x20 + 0x0000003E + + + FUNC109_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC109_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG109_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC110_IN_SEL_CFG + GPIO input function configuration register + 0x310 + 0x20 + 0x0000003E + + + FUNC110_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC110_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG110_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC111_IN_SEL_CFG + GPIO input function configuration register + 0x314 + 0x20 + 0x0000003E + + + FUNC111_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC111_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG111_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC112_IN_SEL_CFG + GPIO input function configuration register + 0x318 + 0x20 + 0x0000003E + + + FUNC112_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC112_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG112_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC113_IN_SEL_CFG + GPIO input function configuration register + 0x31C + 0x20 + 0x0000003E + + + FUNC113_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC113_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG113_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC114_IN_SEL_CFG + GPIO input function configuration register + 0x320 + 0x20 + 0x0000003E + + + FUNC114_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC114_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG114_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC117_IN_SEL_CFG + GPIO input function configuration register + 0x32C + 0x20 + 0x0000003E + + + FUNC117_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC117_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG117_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC118_IN_SEL_CFG + GPIO input function configuration register + 0x330 + 0x20 + 0x0000003E + + + FUNC118_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC118_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG118_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC126_IN_SEL_CFG + GPIO input function configuration register + 0x350 + 0x20 + 0x0000003E + + + FUNC126_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC126_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG126_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC127_IN_SEL_CFG + GPIO input function configuration register + 0x354 + 0x20 + 0x0000003E + + + FUNC127_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC127_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG127_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC128_IN_SEL_CFG + GPIO input function configuration register + 0x358 + 0x20 + 0x0000003F + + + FUNC128_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC128_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG128_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC129_IN_SEL_CFG + GPIO input function configuration register + 0x35C + 0x20 + 0x0000003F + + + FUNC129_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC129_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG129_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC130_IN_SEL_CFG + GPIO input function configuration register + 0x360 + 0x20 + 0x0000003E + + + FUNC130_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC130_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG130_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC131_IN_SEL_CFG + GPIO input function configuration register + 0x364 + 0x20 + 0x0000003E + + + FUNC131_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC131_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG131_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC132_IN_SEL_CFG + GPIO input function configuration register + 0x368 + 0x20 + 0x0000003E + + + FUNC132_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC132_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG132_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC133_IN_SEL_CFG + GPIO input function configuration register + 0x36C + 0x20 + 0x0000003E + + + FUNC133_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC133_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG133_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC134_IN_SEL_CFG + GPIO input function configuration register + 0x370 + 0x20 + 0x0000003F + + + FUNC134_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC134_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG134_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC135_IN_SEL_CFG + GPIO input function configuration register + 0x374 + 0x20 + 0x0000003F + + + FUNC135_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC135_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG135_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC136_IN_SEL_CFG + GPIO input function configuration register + 0x378 + 0x20 + 0x0000003F + + + FUNC136_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC136_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG136_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC137_IN_SEL_CFG + GPIO input function configuration register + 0x37C + 0x20 + 0x0000003F + + + FUNC137_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC137_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG137_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC138_IN_SEL_CFG + GPIO input function configuration register + 0x380 + 0x20 + 0x0000003E + + + FUNC138_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC138_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG138_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC139_IN_SEL_CFG + GPIO input function configuration register + 0x384 + 0x20 + 0x0000003E + + + FUNC139_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC139_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG139_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC140_IN_SEL_CFG + GPIO input function configuration register + 0x388 + 0x20 + 0x0000003E + + + FUNC140_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC140_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG140_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC141_IN_SEL_CFG + GPIO input function configuration register + 0x38C + 0x20 + 0x0000003E + + + FUNC141_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC141_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG141_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC142_IN_SEL_CFG + GPIO input function configuration register + 0x390 + 0x20 + 0x0000003E + + + FUNC142_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC142_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG142_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC143_IN_SEL_CFG + GPIO input function configuration register + 0x394 + 0x20 + 0x0000003E + + + FUNC143_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC143_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG143_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC144_IN_SEL_CFG + GPIO input function configuration register + 0x398 + 0x20 + 0x0000003E + + + FUNC144_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC144_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG144_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC145_IN_SEL_CFG + GPIO input function configuration register + 0x39C + 0x20 + 0x0000003E + + + FUNC145_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC145_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG145_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC146_IN_SEL_CFG + GPIO input function configuration register + 0x3A0 + 0x20 + 0x0000003E + + + FUNC146_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC146_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG146_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC147_IN_SEL_CFG + GPIO input function configuration register + 0x3A4 + 0x20 + 0x0000003E + + + FUNC147_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC147_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG147_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC148_IN_SEL_CFG + GPIO input function configuration register + 0x3A8 + 0x20 + 0x0000003E + + + FUNC148_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC148_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG148_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC149_IN_SEL_CFG + GPIO input function configuration register + 0x3AC + 0x20 + 0x0000003E + + + FUNC149_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC149_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG149_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC150_IN_SEL_CFG + GPIO input function configuration register + 0x3B0 + 0x20 + 0x0000003E + + + FUNC150_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC150_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG150_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC151_IN_SEL_CFG + GPIO input function configuration register + 0x3B4 + 0x20 + 0x0000003E + + + FUNC151_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC151_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG151_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC152_IN_SEL_CFG + GPIO input function configuration register + 0x3B8 + 0x20 + 0x0000003E + + + FUNC152_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC152_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG152_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC153_IN_SEL_CFG + GPIO input function configuration register + 0x3BC + 0x20 + 0x0000003E + + + FUNC153_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC153_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG153_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC154_IN_SEL_CFG + GPIO input function configuration register + 0x3C0 + 0x20 + 0x0000003E + + + FUNC154_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC154_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG154_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC155_IN_SEL_CFG + GPIO input function configuration register + 0x3C4 + 0x20 + 0x0000003E + + + FUNC155_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC155_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG155_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC156_IN_SEL_CFG + GPIO input function configuration register + 0x3C8 + 0x20 + 0x0000003E + + + FUNC156_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC156_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG156_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC158_IN_SEL_CFG + GPIO input function configuration register + 0x3D0 + 0x20 + 0x0000003E + + + FUNC158_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC158_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG158_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC159_IN_SEL_CFG + GPIO input function configuration register + 0x3D4 + 0x20 + 0x0000003E + + + FUNC159_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC159_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG159_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC160_IN_SEL_CFG + GPIO input function configuration register + 0x3D8 + 0x20 + 0x0000003E + + + FUNC160_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC160_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG160_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC161_IN_SEL_CFG + GPIO input function configuration register + 0x3DC + 0x20 + 0x0000003E + + + FUNC161_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC161_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG161_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC162_IN_SEL_CFG + GPIO input function configuration register + 0x3E0 + 0x20 + 0x0000003E + + + FUNC162_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC162_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG162_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC163_IN_SEL_CFG + GPIO input function configuration register + 0x3E4 + 0x20 + 0x0000003E + + + FUNC163_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC163_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG163_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC164_IN_SEL_CFG + GPIO input function configuration register + 0x3E8 + 0x20 + 0x0000003E + + + FUNC164_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC164_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG164_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC165_IN_SEL_CFG + GPIO input function configuration register + 0x3EC + 0x20 + 0x0000003E + + + FUNC165_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC165_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG165_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC166_IN_SEL_CFG + GPIO input function configuration register + 0x3F0 + 0x20 + 0x0000003E + + + FUNC166_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC166_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG166_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC167_IN_SEL_CFG + GPIO input function configuration register + 0x3F4 + 0x20 + 0x0000003E + + + FUNC167_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC167_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG167_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC168_IN_SEL_CFG + GPIO input function configuration register + 0x3F8 + 0x20 + 0x0000003E + + + FUNC168_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC168_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG168_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC169_IN_SEL_CFG + GPIO input function configuration register + 0x3FC + 0x20 + 0x0000003E + + + FUNC169_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC169_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG169_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC170_IN_SEL_CFG + GPIO input function configuration register + 0x400 + 0x20 + 0x0000003E + + + FUNC170_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC170_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG170_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC171_IN_SEL_CFG + GPIO input function configuration register + 0x404 + 0x20 + 0x0000003E + + + FUNC171_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC171_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG171_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC172_IN_SEL_CFG + GPIO input function configuration register + 0x408 + 0x20 + 0x0000003E + + + FUNC172_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC172_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG172_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC173_IN_SEL_CFG + GPIO input function configuration register + 0x40C + 0x20 + 0x0000003E + + + FUNC173_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC173_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG173_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC174_IN_SEL_CFG + GPIO input function configuration register + 0x410 + 0x20 + 0x0000003E + + + FUNC174_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC174_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG174_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC175_IN_SEL_CFG + GPIO input function configuration register + 0x414 + 0x20 + 0x0000003E + + + FUNC175_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC175_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG175_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC176_IN_SEL_CFG + GPIO input function configuration register + 0x418 + 0x20 + 0x0000003E + + + FUNC176_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC176_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG176_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC177_IN_SEL_CFG + GPIO input function configuration register + 0x41C + 0x20 + 0x0000003E + + + FUNC177_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC177_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG177_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC178_IN_SEL_CFG + GPIO input function configuration register + 0x420 + 0x20 + 0x0000003E + + + FUNC178_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC178_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG178_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC179_IN_SEL_CFG + GPIO input function configuration register + 0x424 + 0x20 + 0x0000003E + + + FUNC179_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC179_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG179_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC180_IN_SEL_CFG + GPIO input function configuration register + 0x428 + 0x20 + 0x0000003E + + + FUNC180_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC180_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG180_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC181_IN_SEL_CFG + GPIO input function configuration register + 0x42C + 0x20 + 0x0000003E + + + FUNC181_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC181_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG181_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC182_IN_SEL_CFG + GPIO input function configuration register + 0x430 + 0x20 + 0x0000003E + + + FUNC182_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC182_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG182_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC183_IN_SEL_CFG + GPIO input function configuration register + 0x434 + 0x20 + 0x0000003E + + + FUNC183_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC183_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG183_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC184_IN_SEL_CFG + GPIO input function configuration register + 0x438 + 0x20 + 0x0000003E + + + FUNC184_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC184_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG184_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC185_IN_SEL_CFG + GPIO input function configuration register + 0x43C + 0x20 + 0x0000003E + + + FUNC185_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC185_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG185_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC186_IN_SEL_CFG + GPIO input function configuration register + 0x440 + 0x20 + 0x0000003E + + + FUNC186_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC186_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG186_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC187_IN_SEL_CFG + GPIO input function configuration register + 0x444 + 0x20 + 0x0000003E + + + FUNC187_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC187_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG187_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC188_IN_SEL_CFG + GPIO input function configuration register + 0x448 + 0x20 + 0x0000003E + + + FUNC188_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC188_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG188_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC189_IN_SEL_CFG + GPIO input function configuration register + 0x44C + 0x20 + 0x0000003E + + + FUNC189_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC189_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG189_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC190_IN_SEL_CFG + GPIO input function configuration register + 0x450 + 0x20 + 0x0000003E + + + FUNC190_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC190_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG190_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC191_IN_SEL_CFG + GPIO input function configuration register + 0x454 + 0x20 + 0x0000003E + + + FUNC191_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC191_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG191_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC192_IN_SEL_CFG + GPIO input function configuration register + 0x458 + 0x20 + 0x0000003E + + + FUNC192_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC192_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG192_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC193_IN_SEL_CFG + GPIO input function configuration register + 0x45C + 0x20 + 0x0000003E + + + FUNC193_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC193_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG193_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC194_IN_SEL_CFG + GPIO input function configuration register + 0x460 + 0x20 + 0x0000003E + + + FUNC194_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC194_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG194_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC195_IN_SEL_CFG + GPIO input function configuration register + 0x464 + 0x20 + 0x0000003E + + + FUNC195_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC195_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG195_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC196_IN_SEL_CFG + GPIO input function configuration register + 0x468 + 0x20 + 0x0000003E + + + FUNC196_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC196_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG196_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC197_IN_SEL_CFG + GPIO input function configuration register + 0x46C + 0x20 + 0x0000003E + + + FUNC197_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC197_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG197_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC198_IN_SEL_CFG + GPIO input function configuration register + 0x470 + 0x20 + 0x0000003E + + + FUNC198_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC198_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG198_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC199_IN_SEL_CFG + GPIO input function configuration register + 0x474 + 0x20 + 0x0000003E + + + FUNC199_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC199_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG199_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC200_IN_SEL_CFG + GPIO input function configuration register + 0x478 + 0x20 + 0x0000003E + + + FUNC200_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC200_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG200_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC201_IN_SEL_CFG + GPIO input function configuration register + 0x47C + 0x20 + 0x0000003E + + + FUNC201_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC201_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG201_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC202_IN_SEL_CFG + GPIO input function configuration register + 0x480 + 0x20 + 0x0000003E + + + FUNC202_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC202_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG202_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC203_IN_SEL_CFG + GPIO input function configuration register + 0x484 + 0x20 + 0x0000003E + + + FUNC203_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC203_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG203_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC214_IN_SEL_CFG + GPIO input function configuration register + 0x4B0 + 0x20 + 0x0000003E + + + FUNC214_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC214_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG214_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC215_IN_SEL_CFG + GPIO input function configuration register + 0x4B4 + 0x20 + 0x0000003E + + + FUNC215_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC215_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG215_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC216_IN_SEL_CFG + GPIO input function configuration register + 0x4B8 + 0x20 + 0x0000003E + + + FUNC216_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC216_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG216_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC217_IN_SEL_CFG + GPIO input function configuration register + 0x4BC + 0x20 + 0x0000003E + + + FUNC217_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC217_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG217_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC218_IN_SEL_CFG + GPIO input function configuration register + 0x4C0 + 0x20 + 0x0000003E + + + FUNC218_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC218_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG218_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC219_IN_SEL_CFG + GPIO input function configuration register + 0x4C4 + 0x20 + 0x0000003E + + + FUNC219_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC219_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG219_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC220_IN_SEL_CFG + GPIO input function configuration register + 0x4C8 + 0x20 + 0x0000003E + + + FUNC220_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC220_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG220_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC221_IN_SEL_CFG + GPIO input function configuration register + 0x4CC + 0x20 + 0x0000003E + + + FUNC221_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC221_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG221_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC222_IN_SEL_CFG + GPIO input function configuration register + 0x4D0 + 0x20 + 0x0000003E + + + FUNC222_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC222_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG222_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC223_IN_SEL_CFG + GPIO input function configuration register + 0x4D4 + 0x20 + 0x0000003E + + + FUNC223_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC223_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG223_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC224_IN_SEL_CFG + GPIO input function configuration register + 0x4D8 + 0x20 + 0x0000003E + + + FUNC224_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC224_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG224_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC225_IN_SEL_CFG + GPIO input function configuration register + 0x4DC + 0x20 + 0x0000003E + + + FUNC225_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC225_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG225_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC226_IN_SEL_CFG + GPIO input function configuration register + 0x4E0 + 0x20 + 0x0000003E + + + FUNC226_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC226_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG226_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC227_IN_SEL_CFG + GPIO input function configuration register + 0x4E4 + 0x20 + 0x0000003E + + + FUNC227_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC227_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG227_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC228_IN_SEL_CFG + GPIO input function configuration register + 0x4E8 + 0x20 + 0x0000003E + + + FUNC228_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC228_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG228_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC229_IN_SEL_CFG + GPIO input function configuration register + 0x4EC + 0x20 + 0x0000003E + + + FUNC229_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC229_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG229_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC230_IN_SEL_CFG + GPIO input function configuration register + 0x4F0 + 0x20 + 0x0000003E + + + FUNC230_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC230_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG230_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC231_IN_SEL_CFG + GPIO input function configuration register + 0x4F4 + 0x20 + 0x0000003E + + + FUNC231_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC231_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG231_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC232_IN_SEL_CFG + GPIO input function configuration register + 0x4F8 + 0x20 + 0x0000003E + + + FUNC232_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC232_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG232_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC233_IN_SEL_CFG + GPIO input function configuration register + 0x4FC + 0x20 + 0x0000003E + + + FUNC233_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC233_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG233_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC234_IN_SEL_CFG + GPIO input function configuration register + 0x500 + 0x20 + 0x0000003E + + + FUNC234_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC234_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG234_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC235_IN_SEL_CFG + GPIO input function configuration register + 0x504 + 0x20 + 0x0000003E + + + FUNC235_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC235_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG235_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC236_IN_SEL_CFG + GPIO input function configuration register + 0x508 + 0x20 + 0x0000003E + + + FUNC236_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC236_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG236_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC237_IN_SEL_CFG + GPIO input function configuration register + 0x50C + 0x20 + 0x0000003E + + + FUNC237_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC237_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG237_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC238_IN_SEL_CFG + GPIO input function configuration register + 0x510 + 0x20 + 0x0000003E + + + FUNC238_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC238_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG238_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC239_IN_SEL_CFG + GPIO input function configuration register + 0x514 + 0x20 + 0x0000003E + + + FUNC239_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC239_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG239_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC240_IN_SEL_CFG + GPIO input function configuration register + 0x518 + 0x20 + 0x0000003E + + + FUNC240_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC240_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG240_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC241_IN_SEL_CFG + GPIO input function configuration register + 0x51C + 0x20 + 0x0000003E + + + FUNC241_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC241_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG241_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC242_IN_SEL_CFG + GPIO input function configuration register + 0x520 + 0x20 + 0x0000003E + + + FUNC242_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC242_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG242_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC243_IN_SEL_CFG + GPIO input function configuration register + 0x524 + 0x20 + 0x0000003E + + + FUNC243_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC243_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG243_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC244_IN_SEL_CFG + GPIO input function configuration register + 0x528 + 0x20 + 0x0000003E + + + FUNC244_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC244_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG244_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC245_IN_SEL_CFG + GPIO input function configuration register + 0x52C + 0x20 + 0x0000003E + + + FUNC245_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC245_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG245_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC246_IN_SEL_CFG + GPIO input function configuration register + 0x530 + 0x20 + 0x0000003E + + + FUNC246_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC246_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG246_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC247_IN_SEL_CFG + GPIO input function configuration register + 0x534 + 0x20 + 0x0000003E + + + FUNC247_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC247_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG247_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC248_IN_SEL_CFG + GPIO input function configuration register + 0x538 + 0x20 + 0x0000003E + + + FUNC248_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC248_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG248_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC249_IN_SEL_CFG + GPIO input function configuration register + 0x53C + 0x20 + 0x0000003E + + + FUNC249_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC249_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG249_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC250_IN_SEL_CFG + GPIO input function configuration register + 0x540 + 0x20 + 0x0000003E + + + FUNC250_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC250_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG250_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC251_IN_SEL_CFG + GPIO input function configuration register + 0x544 + 0x20 + 0x0000003E + + + FUNC251_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC251_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG251_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC252_IN_SEL_CFG + GPIO input function configuration register + 0x548 + 0x20 + 0x0000003E + + + FUNC252_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC252_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG252_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC253_IN_SEL_CFG + GPIO input function configuration register + 0x54C + 0x20 + 0x0000003E + + + FUNC253_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC253_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG253_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC254_IN_SEL_CFG + GPIO input function configuration register + 0x550 + 0x20 + 0x0000003E + + + FUNC254_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC254_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG254_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + FUNC255_IN_SEL_CFG + GPIO input function configuration register + 0x554 + 0x20 + 0x0000003E + + + FUNC255_IN_SEL + set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level. + 0 + 6 + read-write + + + FUNC255_IN_INV_SEL + set this bit to invert input signal. 1:invert. 0:not invert. + 6 + 1 + read-write + + + SIG255_IN_SEL + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. + 7 + 1 + read-write + + + + + 57 + 0x4 + FUNC%s_OUT_SEL_CFG + GPIO output function select register + 0x558 + 0x20 + 0x00000100 + + + FUNC_OUT_SEL + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + 0 + 9 + read-write + + + FUNC_OUT_INV_SEL + set this bit to invert output signal.1:invert.0:not invert. + 9 + 1 + read-write + + + FUNC_OEN_SEL + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. + 10 + 1 + read-write + + + FUNC_OEN_INV_SEL + set this bit to invert output enable signal.1:invert.0:not invert. + 11 + 1 + read-write + + + + + INTR_2 + GPIO interrupt 2 status register for GPIO0-31 + 0x63C + 0x20 + + + INT_2 + GPIO interrupt 2 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_2 + GPIO interrupt 2 status register for GPIO32-56 + 0x640 + 0x20 + + + INT1_2 + GPIO interrupt 2 status register for GPIO32-56 + 0 + 25 + read-only + + + + + INTR_3 + GPIO interrupt 3 status register for GPIO0-31 + 0x644 + 0x20 + + + INT_3 + GPIO interrupt 3 status register for GPIO0-31 + 0 + 32 + read-only + + + + + INTR1_3 + GPIO interrupt 3 status register for GPIO32-56 + 0x648 + 0x20 + + + INT1_3 + GPIO interrupt 3 status register for GPIO32-56 + 0 + 25 + read-only + + + + + CLOCK_GATE + GPIO clock gate register + 0x64C + 0x20 + 0x00000001 + + + CLK_EN + set this bit to enable GPIO clock gate + 0 + 1 + read-write + + + + + INT_RAW + analog comparator interrupt raw + 0x700 + 0x20 + + + COMP0_NEG_INT_RAW + analog comparator pos edge interrupt raw + 0 + 1 + read-write + + + COMP0_POS_INT_RAW + analog comparator neg edge interrupt raw + 1 + 1 + read-write + + + COMP0_ALL_INT_RAW + analog comparator neg or pos edge interrupt raw + 2 + 1 + read-write + + + COMP1_NEG_INT_RAW + analog comparator pos edge interrupt raw + 3 + 1 + read-write + + + COMP1_POS_INT_RAW + analog comparator neg edge interrupt raw + 4 + 1 + read-write + + + COMP1_ALL_INT_RAW + analog comparator neg or pos edge interrupt raw + 5 + 1 + read-write + + + BISTOK_INT_RAW + pad bistok interrupt raw + 6 + 1 + read-write + + + BISTFAIL_INT_RAW + pad bistfail interrupt raw + 7 + 1 + read-write + + + + + INT_ST + analog comparator interrupt status + 0x704 + 0x20 + + + COMP0_NEG_INT_ST + analog comparator pos edge interrupt status + 0 + 1 + read-only + + + COMP0_POS_INT_ST + analog comparator neg edge interrupt status + 1 + 1 + read-only + + + COMP0_ALL_INT_ST + analog comparator neg or pos edge interrupt status + 2 + 1 + read-only + + + COMP1_NEG_INT_ST + analog comparator pos edge interrupt status + 3 + 1 + read-only + + + COMP1_POS_INT_ST + analog comparator neg edge interrupt status + 4 + 1 + read-only + + + COMP1_ALL_INT_ST + analog comparator neg or pos edge interrupt status + 5 + 1 + read-only + + + BISTOK_INT_ST + pad bistok interrupt status + 6 + 1 + read-only + + + BISTFAIL_INT_ST + pad bistfail interrupt status + 7 + 1 + read-only + + + + + INT_ENA + analog comparator interrupt enable + 0x708 + 0x20 + 0x000000FF + + + COMP0_NEG_INT_ENA + analog comparator pos edge interrupt enable + 0 + 1 + read-write + + + COMP0_POS_INT_ENA + analog comparator neg edge interrupt enable + 1 + 1 + read-write + + + COMP0_ALL_INT_ENA + analog comparator neg or pos edge interrupt enable + 2 + 1 + read-write + + + COMP1_NEG_INT_ENA + analog comparator pos edge interrupt enable + 3 + 1 + read-write + + + COMP1_POS_INT_ENA + analog comparator neg edge interrupt enable + 4 + 1 + read-write + + + COMP1_ALL_INT_ENA + analog comparator neg or pos edge interrupt enable + 5 + 1 + read-write + + + BISTOK_INT_ENA + pad bistok interrupt enable + 6 + 1 + read-write + + + BISTFAIL_INT_ENA + pad bistfail interrupt enable + 7 + 1 + read-write + + + + + INT_CLR + analog comparator interrupt clear + 0x70C + 0x20 + + + COMP0_NEG_INT_CLR + analog comparator pos edge interrupt clear + 0 + 1 + write-only + + + COMP0_POS_INT_CLR + analog comparator neg edge interrupt clear + 1 + 1 + write-only + + + COMP0_ALL_INT_CLR + analog comparator neg or pos edge interrupt clear + 2 + 1 + write-only + + + COMP1_NEG_INT_CLR + analog comparator pos edge interrupt clear + 3 + 1 + write-only + + + COMP1_POS_INT_CLR + analog comparator neg edge interrupt clear + 4 + 1 + write-only + + + COMP1_ALL_INT_CLR + analog comparator neg or pos edge interrupt clear + 5 + 1 + write-only + + + BISTOK_INT_CLR + pad bistok interrupt enable + 6 + 1 + write-only + + + BISTFAIL_INT_CLR + pad bistfail interrupt enable + 7 + 1 + write-only + + + + + ZERO_DET0_FILTER_CNT + GPIO analog comparator zero detect filter count + 0x710 + 0x20 + 0xFFFFFFFF + + + ZERO_DET0_FILTER_CNT + GPIO analog comparator zero detect filter count + 0 + 32 + read-write + + + + + ZERO_DET1_FILTER_CNT + GPIO analog comparator zero detect filter count + 0x714 + 0x20 + 0xFFFFFFFF + + + ZERO_DET1_FILTER_CNT + GPIO analog comparator zero detect filter count + 0 + 32 + read-write + + + + + SEND_SEQ + High speed sdio pad bist send sequence + 0x718 + 0x20 + 0x12345678 + + + SEND_SEQ + High speed sdio pad bist send sequence + 0 + 32 + read-write + + + + + RECIVE_SEQ + High speed sdio pad bist recive sequence + 0x71C + 0x20 + + + RECIVE_SEQ + High speed sdio pad bist recive sequence + 0 + 32 + read-only + + + + + BISTIN_SEL + High speed sdio pad bist in pad sel + 0x720 + 0x20 + 0x0000000F + + + BISTIN_SEL + High speed sdio pad bist in pad sel 0:pad39, 1: pad40... + 0 + 4 + read-write + + + + + BIST_CTRL + High speed sdio pad bist control + 0x724 + 0x20 + 0x00000001 + + + BIST_PAD_OE + High speed sdio pad bist out pad oe + 0 + 1 + read-write + + + BIST_START + High speed sdio pad bist start + 1 + 1 + write-only + + + + + DATE + GPIO version register + 0x7FC + 0x20 + 0x00230403 + + + DATE + version register + 0 + 28 + read-write + + + + + + + GPIO_SD + Sigma-Delta Modulation + GPIOSD + 0x500E0F00 + + 0x0 + 0xA4 + registers + + + + 8 + 0x4 + SIGMADELTA%s + Duty Cycle Configure Register of SDM%s + 0x0 + 0x20 + 0x0000FF00 + + + SD_IN + This field is used to configure the duty cycle of sigma delta modulation output. + 0 + 8 + read-write + + + SD_PRESCALE + This field is used to set a divider value to divide APB clock. + 8 + 8 + read-write + + + + + CLOCK_GATE + Clock Gating Configure Register + 0x20 + 0x20 + + + CLK_EN + Clock enable bit of configuration registers for sigma delta modulation. + 0 + 1 + read-write + + + + + SIGMADELTA_MISC + MISC Register + 0x24 + 0x20 + + + FUNCTION_CLK_EN + Clock enable bit of sigma delta modulation. + 30 + 1 + read-write + + + SPI_SWAP + Reserved. + 31 + 1 + read-write + + + + + 8 + 0x4 + GLITCH_FILTER_CH%s + Glitch Filter Configure Register of Channel%s + 0x30 + 0x20 + + + FILTER_CH0_EN + Glitch Filter channel enable bit. + 0 + 1 + read-write + + + FILTER_CH0_INPUT_IO_NUM + Glitch Filter input io number. + 1 + 6 + read-write + + + FILTER_CH0_WINDOW_THRES + Glitch Filter window threshold. + 7 + 6 + read-write + + + FILTER_CH0_WINDOW_WIDTH + Glitch Filter window width. + 13 + 6 + read-write + + + + + 8 + 0x4 + ETM_EVENT_CH%s_CFG + Etm Config register of Channel%s + 0x60 + 0x20 + + + ETM_CH0_EVENT_SEL + Etm event channel select gpio. + 0 + 6 + read-write + + + ETM_CH0_EVENT_EN + Etm event send enable bit. + 7 + 1 + read-write + + + + + ETM_TASK_P0_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA0 + 0x20 + + + ETM_TASK_GPIO0_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO0_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO1_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO1_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO2_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO2_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO3_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO3_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P1_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA4 + 0x20 + + + ETM_TASK_GPIO4_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO4_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO5_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO5_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO6_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO6_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO7_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO7_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P2_CFG + Etm Configure Register to decide which GPIO been chosen + 0xA8 + 0x20 + + + ETM_TASK_GPIO8_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO8_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO9_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO9_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO10_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO10_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO11_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO11_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P3_CFG + Etm Configure Register to decide which GPIO been chosen + 0xAC + 0x20 + + + ETM_TASK_GPIO12_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO12_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO13_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO13_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO14_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO14_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO15_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO15_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P4_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB0 + 0x20 + + + ETM_TASK_GPIO16_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO16_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO17_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO17_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO18_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO18_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO19_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO19_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P5_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB4 + 0x20 + + + ETM_TASK_GPIO20_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO20_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO21_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO21_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO22_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO22_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO23_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO23_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P6_CFG + Etm Configure Register to decide which GPIO been chosen + 0xB8 + 0x20 + + + ETM_TASK_GPIO24_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO24_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO25_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO25_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO26_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO26_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO27_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO27_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P7_CFG + Etm Configure Register to decide which GPIO been chosen + 0xBC + 0x20 + + + ETM_TASK_GPIO28_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO28_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO29_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO29_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO30_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO30_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO31_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO31_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P8_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC0 + 0x20 + + + ETM_TASK_GPIO32_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO32_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO33_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO33_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO34_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO34_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO35_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO35_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P9_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC4 + 0x20 + + + ETM_TASK_GPIO36_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO36_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO37_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO37_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO38_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO38_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO39_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO39_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P10_CFG + Etm Configure Register to decide which GPIO been chosen + 0xC8 + 0x20 + + + ETM_TASK_GPIO40_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO40_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO41_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO41_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO42_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO42_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO43_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO43_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P11_CFG + Etm Configure Register to decide which GPIO been chosen + 0xCC + 0x20 + + + ETM_TASK_GPIO44_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO44_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO45_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO45_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO46_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO46_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO47_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO47_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P12_CFG + Etm Configure Register to decide which GPIO been chosen + 0xD0 + 0x20 + + + ETM_TASK_GPIO48_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO48_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO49_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO49_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO50_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO50_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + ETM_TASK_GPIO51_EN + Enable bit of GPIO response etm task. + 24 + 1 + read-write + + + ETM_TASK_GPIO51_SEL + GPIO choose a etm task channel. + 25 + 3 + read-write + + + + + ETM_TASK_P13_CFG + Etm Configure Register to decide which GPIO been chosen + 0xD4 + 0x20 + + + ETM_TASK_GPIO52_EN + Enable bit of GPIO response etm task. + 0 + 1 + read-write + + + ETM_TASK_GPIO52_SEL + GPIO choose a etm task channel. + 1 + 3 + read-write + + + ETM_TASK_GPIO53_EN + Enable bit of GPIO response etm task. + 8 + 1 + read-write + + + ETM_TASK_GPIO53_SEL + GPIO choose a etm task channel. + 9 + 3 + read-write + + + ETM_TASK_GPIO54_EN + Enable bit of GPIO response etm task. + 16 + 1 + read-write + + + ETM_TASK_GPIO54_SEL + GPIO choose a etm task channel. + 17 + 3 + read-write + + + + + VERSION + Version Control Register + 0xFC + 0x20 + 0x02203050 + + + GPIO_SD_DATE + Version control register. + 0 + 28 + read-write + + + + + + + H264 + H264 Encoder (Core) + H264 + 0x50084000 + + 0x0 + 0xF4 + registers + + + H264_REG + 126 + + + + SYS_CTRL + H264 system level control register. + 0x0 + 0x20 + + + FRAME_START + Configures whether or not to start encoding one frame.\\0: Invalid. No effect\\1: Start encoding one frame + 0 + 1 + write-only + + + DMA_MOVE_START + Configures whether or not to start moving reference data from external mem.\\0: Invalid. No effect\\1: H264 start moving two MB lines of reference frame from external mem to internal mem + 1 + 1 + write-only + + + FRAME_MODE + Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this field must be set to 1 too.\\0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA\\1: Frame mode. Before every frame start, need reconfig reference frame DMA + 2 + 1 + read-write + + + SYS_RST_PULSE + Configures whether or not to reset H264 ip.\\0: Invalid. No effect\\1: Reset H264 ip + 3 + 1 + write-only + + + + + GOP_CONF + GOP related configuration register. + 0x4 + 0x20 + + + DUAL_STREAM_MODE + Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\0: Normal mode\\1: Dual stream mode + 0 + 1 + read-write + + + GOP_NUM + Configures the frame number of one GOP.\\0: The frame number of one GOP is infinite\\Others: Actual frame number of one GOP + 1 + 8 + read-write + + + + + A_SYS_MB_RES + Video A horizontal and vertical MB resolution register. + 0x8 + 0x20 + + + A_SYS_TOTAL_MB_Y + Configures video A vertical MB resolution. + 0 + 7 + read-write + + + A_SYS_TOTAL_MB_X + Configures video A horizontal MB resolution. + 7 + 7 + read-write + + + + + A_SYS_CONF + Video A system level configuration register. + 0xC + 0x20 + 0x00000203 + + + A_DB_TMP_READY_TRIGGER_MB_NUM + Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. + 0 + 7 + read-write + + + A_REC_READY_TRIGGER_MB_LINES + Configures when to trigger video A H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. + 7 + 7 + read-write + + + A_INTRA_COST_CMP_OFFSET + Configures video A intra cost offset when I MB compared with P MB. + 14 + 16 + read-write + + + + + A_DECI_SCORE + Video A luma and chroma MB decimate score Register. + 0x10 + 0x20 + + + A_C_DECI_SCORE + Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. + 0 + 10 + read-write + + + A_L_DECI_SCORE + Configures video A luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. + 10 + 10 + read-write + + + + + A_DECI_SCORE_OFFSET + Video A luma and chroma MB decimate score offset Register. + 0x14 + 0x20 + + + A_I16X16_DECI_SCORE_OFFSET + Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. + 0 + 6 + read-write + + + A_I_CHROMA_DECI_SCORE_OFFSET + Configures video A I chroma MB decimate score offset. This offset will be added to I chroma MB score. + 6 + 6 + read-write + + + A_P16X16_DECI_SCORE_OFFSET + Configures video A p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. + 12 + 6 + read-write + + + A_P_CHROMA_DECI_SCORE_OFFSET + Configures video A p chroma MB decimate score offset. This offset will be added to p chroma MB score. + 18 + 6 + read-write + + + + + A_RC_CONF0 + Video A rate control configuration register0. + 0x18 + 0x20 + + + A_QP + Configures video A frame level initial luma QP value. + 0 + 6 + read-write + + + A_RATE_CTRL_U + Configures video A parameter U value. U = int((float) u << 8). + 6 + 16 + read-write + + + A_MB_RATE_CTRL_EN + Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. + 22 + 1 + read-write + + + + + A_RC_CONF1 + Video A rate control configuration register1. + 0x1C + 0x20 + + + A_CHROMA_DC_QP_DELTA + Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. + 0 + 3 + read-write + + + A_CHROMA_QP_DELTA + Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. + 3 + 4 + read-write + + + A_QP_MIN + Configures video A allowed luma QP min value. + 7 + 6 + read-write + + + A_QP_MAX + Configures video A allowed luma QP max value. + 13 + 6 + read-write + + + A_MAD_FRAME_PRED + Configures vdieo A frame level predicted MB MAD value. + 19 + 12 + read-write + + + + + A_DB_BYPASS + Video A Deblocking bypass register + 0x20 + 0x20 + + + A_BYPASS_DB_FILTER + Configures whether or not to bypass video A deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter + 0 + 1 + read-write + + + + + A_ROI_REGION0 + Video A H264 ROI region0 range configure register. + 0x24 + 0x20 + + + X + Configures the horizontal start macroblocks of region 0 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 0 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 0 in Video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 0 in Video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 0 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION1 + Video A H264 ROI region1 range configure register. + 0x28 + 0x20 + + + X + Configures the horizontal start macroblocks of region 1 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 1 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 1 in Video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 1 in Video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 1 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION2 + Video A H264 ROI region2 range configure register. + 0x2C + 0x20 + + + X + Configures the horizontal start macroblocks of region 2 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 2 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 2 in Video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 2 in Video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 2 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION3 + Video A H264 ROI region3 range configure register. + 0x30 + 0x20 + + + X + Configures the horizontal start macroblocks of region 3 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 3 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 3 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 3 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 3 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION4 + Video A H264 ROI region4 range configure register. + 0x34 + 0x20 + + + X + Configures the horizontal start macroblocks of region 4 in Video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 4 in Video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 4 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 4 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 4 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION5 + Video A H264 ROI region5 range configure register. + 0x38 + 0x20 + + + X + Configures the horizontial start macroblocks of region 5 video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 5 video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 5 video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 5 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 5 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION6 + Video A H264 ROI region6 range configure register. + 0x3C + 0x20 + + + X + Configures the horizontial start macroblocks of region 6 video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 6 in video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 6 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 6 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 6 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION7 + Video A H264 ROI region7 range configure register. + 0x40 + 0x20 + + + X + Configures the horizontal start macroblocks of region 7 in video A. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 7 in video A. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 7 in video A. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 7 in video A. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video A ROI of region 7 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + A_ROI_REGION0_3_QP + Video A H264 ROI region0, region1,region2,region3 QP register. + 0x44 + 0x20 + + + A_ROI_REGION0_QP + Configure H264 ROI region0 qp in video A,fixed qp or delta qp. + 0 + 7 + read-write + + + A_ROI_REGION1_QP + Configure H264 ROI region1 qp in video A,fixed qp or delta qp. + 7 + 7 + read-write + + + A_ROI_REGION2_QP + Configure H264 ROI region2 qp in video A,fixed qp or delta qp. + 14 + 7 + read-write + + + A_ROI_REGION3_QP + Configure H264 ROI region3 qp in video A,fixed qp or delta qp. + 21 + 7 + read-write + + + + + A_ROI_REGION4_7_QP + Video A H264 ROI region4, region5,region6,region7 QP register. + 0x48 + 0x20 + + + A_ROI_REGION4_QP + Configure H264 ROI region4 qp in video A,fixed qp or delta qp. + 0 + 7 + read-write + + + A_ROI_REGION5_QP + Configure H264 ROI region5 qp in video A,fixed qp or delta qp. + 7 + 7 + read-write + + + A_ROI_REGION6_QP + Configure H264 ROI region6 qp in video A,fixed qp or delta qp. + 14 + 7 + read-write + + + A_ROI_REGION7_QP + Configure H264 ROI region7 qp in video A,fixed qp or delta qp. + 21 + 7 + read-write + + + + + A_NO_ROI_REGION_QP_OFFSET + Video A H264 no roi region QP register. + 0x4C + 0x20 + + + A_NO_ROI_REGION_QP + Configure H264 no region qp in video A, delta qp. + 0 + 7 + read-write + + + + + A_ROI_CONFIG + Video A H264 ROI configure register. + 0x50 + 0x20 + + + A_ROI_EN + Configure whether or not to enable ROI in video A.\\0:not enable ROI\\1:enable ROI. + 0 + 1 + read-write + + + A_ROI_MODE + Configure the mode of ROI in video A.\\0:fixed qp\\1:delta qp. + 1 + 1 + read-write + + + + + B_SYS_MB_RES + Video B horizontal and vertical MB resolution register. + 0x54 + 0x20 + + + B_SYS_TOTAL_MB_Y + Configures video B vertical MB resolution. + 0 + 7 + read-write + + + B_SYS_TOTAL_MB_X + Configures video B horizontal MB resolution. + 7 + 7 + read-write + + + + + B_SYS_CONF + Video B system level configuration register. + 0x58 + 0x20 + 0x00000203 + + + B_DB_TMP_READY_TRIGGER_MB_NUM + Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3. + 0 + 7 + read-write + + + B_REC_READY_TRIGGER_MB_LINES + Configures when to trigger video B H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4. + 7 + 7 + read-write + + + B_INTRA_COST_CMP_OFFSET + Configures video B intra cost offset when I MB compared with P MB. + 14 + 16 + read-write + + + + + B_DECI_SCORE + Video B luma and chroma MB decimate score Register. + 0x5C + 0x20 + + + B_C_DECI_SCORE + Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable. + 0 + 10 + read-write + + + B_L_DECI_SCORE + Configures video B luma MB decimate score. When luma score is smaller than it, luma decimate will be enable. + 10 + 10 + read-write + + + + + B_DECI_SCORE_OFFSET + Video B luma and chroma MB decimate score offset Register. + 0x60 + 0x20 + + + B_I16X16_DECI_SCORE_OFFSET + Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. + 0 + 6 + read-write + + + B_I_CHROMA_DECI_SCORE_OFFSET + Configures video B I chroma MB decimate score offset. This offset will be added to I chroma MB score. + 6 + 6 + read-write + + + B_P16X16_DECI_SCORE_OFFSET + Configures video B p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. + 12 + 6 + read-write + + + B_P_CHROMA_DECI_SCORE_OFFSET + Configures video B p chroma MB decimate score offset. This offset will be added to p chroma MB score. + 18 + 6 + read-write + + + + + B_RC_CONF0 + Video B rate control configuration register0. + 0x64 + 0x20 + + + B_QP + Configures video B frame level initial luma QP value. + 0 + 6 + read-write + + + B_RATE_CTRL_U + Configures video B parameter U value. U = int((float) u << 8). + 6 + 16 + read-write + + + B_MB_RATE_CTRL_EN + Configures video A whether or not to open macro block rate ctrl.\\1:Open the macro block rate ctrl\\1:Close the macro block rate ctrl. + 22 + 1 + read-write + + + + + B_RC_CONF1 + Video B rate control configuration register1. + 0x68 + 0x20 + + + B_CHROMA_DC_QP_DELTA + Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. + 0 + 3 + read-write + + + B_CHROMA_QP_DELTA + Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. + 3 + 4 + read-write + + + B_QP_MIN + Configures video B allowed luma QP min value. + 7 + 6 + read-write + + + B_QP_MAX + Configures video B allowed luma QP max value. + 13 + 6 + read-write + + + B_MAD_FRAME_PRED + Configures vdieo B frame level predicted MB MAD value. + 19 + 12 + read-write + + + + + B_DB_BYPASS + Video B Deblocking bypass register + 0x6C + 0x20 + + + B_BYPASS_DB_FILTER + Configures whether or not to bypass video B deblcoking filter. \\0: Open the deblock filter\\1: Close the deblock filter + 0 + 1 + read-write + + + + + B_ROI_REGION0 + Video B H264 ROI region0 range configure register. + 0x70 + 0x20 + + + X + Configures the horizontal start macroblocks of region 0 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 0 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 0 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 0 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 0 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION1 + Video B H264 ROI region1 range configure register. + 0x74 + 0x20 + + + X + Configures the horizontal start macroblocks of region 1 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 1 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 1 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 1 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 1 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION2 + Video B H264 ROI region2 range configure register. + 0x78 + 0x20 + + + X + Configures the horizontal start macroblocks of region 2 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 2 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 2 in Video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 2 in Video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 2 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION3 + Video B H264 ROI region3 range configure register. + 0x7C + 0x20 + + + X + Configures the horizontal start macroblocks of region 3 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 3 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 3 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 3 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 3 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION4 + Video B H264 ROI region4 range configure register. + 0x80 + 0x20 + + + X + Configures the horizontal start macroblocks of region 4 in Video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 4 in Video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 4 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 4 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 4 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION5 + Video B H264 ROI region5 range configure register. + 0x84 + 0x20 + + + X + Configures the horizontial start macroblocks of region 5 video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 5 video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 5 video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 5 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 5 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION6 + Video B H264 ROI region6 range configure register. + 0x88 + 0x20 + + + X + Configures the horizontial start macroblocks of region 6 video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 6 in video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 6 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 6 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 6 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION7 + Video B H264 ROI region7 range configure register. + 0x8C + 0x20 + + + X + Configures the horizontal start macroblocks of region 7 in video B. + 0 + 7 + read-write + + + Y + Configures the vertical start macroblocks of region 7 in video B. + 7 + 7 + read-write + + + X_LEN + Configures the number of macroblocks in horizontal direction of the region 7 in video B. + 14 + 7 + read-write + + + Y_LEN + Configures the number of macroblocks in vertical direction of the region 7 in video B. + 21 + 7 + read-write + + + EN + Configures whether or not to open Video B ROI of region 7 .\\0:Close ROI\\1:Open ROI. + 28 + 1 + read-write + + + + + B_ROI_REGION0_3_QP + Video B H264 ROI region0, region1,region2,region3 QP register. + 0x90 + 0x20 + + + B_ROI_REGION0_QP + Configure H264 ROI region0 qp in video B,fixed qp or delta qp. + 0 + 7 + read-write + + + B_ROI_REGION1_QP + Configure H264 ROI region1 qp in video B,fixed qp or delta qp. + 7 + 7 + read-write + + + B_ROI_REGION2_QP + Configure H264 ROI region2 qp in video B,fixed qp or delta qp. + 14 + 7 + read-write + + + B_ROI_REGION3_QP + Configure H264 ROI region3 qp in video B,fixed qp or delta qp. + 21 + 7 + read-write + + + + + B_ROI_REGION4_7_QP + Video B H264 ROI region4, region5,region6,region7 QP register. + 0x94 + 0x20 + + + B_ROI_REGION4_QP + Configure H264 ROI region4 qp in video B,fixed qp or delta qp. + 0 + 7 + read-write + + + B_ROI_REGION5_QP + Configure H264 ROI region5 qp in video B,fixed qp or delta qp. + 7 + 7 + read-write + + + B_ROI_REGION6_QP + Configure H264 ROI region6 qp in video B,fixed qp or delta qp. + 14 + 7 + read-write + + + B_ROI_REGION7_QP + Configure H264 ROI region7 qp in video B,fixed qp or delta qp. + 21 + 7 + read-write + + + + + B_NO_ROI_REGION_QP_OFFSET + Video B H264 no roi region QP register. + 0x98 + 0x20 + + + B_NO_ROI_REGION_QP + Configure H264 no region qp in video B, delta qp. + 0 + 7 + read-write + + + + + B_ROI_CONFIG + Video B H264 ROI configure register. + 0x9C + 0x20 + + + B_ROI_EN + Configure whether or not to enable ROI in video B.\\0:not enable ROI\\1:enable ROI. + 0 + 1 + read-write + + + B_ROI_MODE + Configure the mode of ROI in video B.\\0:fixed qp\\1:delta qp. + 1 + 1 + read-write + + + + + RC_STATUS0 + Rate control status register0. + 0xA0 + 0x20 + + + FRAME_MAD_SUM + Represents all MB actual MAD sum value of one frame. + 0 + 21 + read-only + + + + + RC_STATUS1 + Rate control status register1. + 0xA4 + 0x20 + + + FRAME_ENC_BITS + Represents all MB actual encoding bits sum value of one frame. + 0 + 27 + read-only + + + + + RC_STATUS2 + Rate control status register2. + 0xA8 + 0x20 + + + FRAME_QP_SUM + Represents all MB actual luma QP sum value of one frame. + 0 + 19 + read-only + + + + + SLICE_HEADER_REMAIN + Frame Slice Header remain bit register. + 0xAC + 0x20 + + + SLICE_REMAIN_BITLENGTH + Configures Slice Header remain bit number + 0 + 3 + read-write + + + SLICE_REMAIN_BIT + Configures Slice Header remain bit + 3 + 8 + read-write + + + + + SLICE_HEADER_BYTE_LENGTH + Frame Slice Header byte length register. + 0xB0 + 0x20 + + + SLICE_BYTE_LENGTH + Configures Slice Header byte number + 0 + 4 + read-write + + + + + BS_THRESHOLD + Bitstream buffer overflow threshold register + 0xB4 + 0x20 + 0x00000030 + + + BS_BUFFER_THRESHOLD + Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb. + 0 + 7 + read-write + + + + + SLICE_HEADER_BYTE0 + Frame Slice Header byte low 32 bit register. + 0xB8 + 0x20 + + + SLICE_BYTE_LSB + Configures Slice Header low 32 bit + 0 + 32 + read-write + + + + + SLICE_HEADER_BYTE1 + Frame Slice Header byte high 32 bit register. + 0xBC + 0x20 + + + SLICE_BYTE_MSB + Configures Slice Header high 32 bit + 0 + 32 + read-write + + + + + INT_RAW + Interrupt raw status register + 0xC0 + 0x20 + + + DB_TMP_READY_INT_RAW + Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel. + 0 + 1 + read-write + + + REC_READY_INT_RAW + Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when H264 encoding enough reconstruct pixel. + 1 + 1 + read-write + + + FRAME_DONE_INT_RAW + Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when H264 encoding one frame done. + 2 + 1 + read-write + + + DMA_MOVE_2MB_LINE_DONE_INT_RAW + Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Triggered when H264 move two MB lines of reference frame from external mem to internal mem done. + 3 + 1 + read-write + + + + + INT_ST + Interrupt masked status register + 0xC4 + 0x20 + + + DB_TMP_READY_INT_ST + The masked interrupt status of H264_DB_TMP_READY_INT. Valid only when the H264_DB_TMP_READY_INT_ENA is set to 1. + 0 + 1 + read-only + + + REC_READY_INT_ST + The masked interrupt status of H264_REC_READY_INT. Valid only when the H264_REC_READY_INT_ENA is set to 1. + 1 + 1 + read-only + + + FRAME_DONE_INT_ST + The masked interrupt status of H264_FRAME_DONE_INT. Valid only when the H264_FRAME_DONE_INT_ENA is set to 1. + 2 + 1 + read-only + + + DMA_MOVE_2MB_LINE_DONE_INT_ST + Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0xC8 + 0x20 + + + DB_TMP_READY_INT_ENA + Write 1 to enable H264_DB_TMP_READY_INT. + 0 + 1 + read-write + + + REC_READY_INT_ENA + Write 1 to enable H264_REC_READY_INT. + 1 + 1 + read-write + + + FRAME_DONE_INT_ENA + Write 1 to enable H264_FRAME_DONE_INT. + 2 + 1 + read-write + + + DMA_MOVE_2MB_LINE_DONE_INT_ENA + Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0xCC + 0x20 + + + DB_TMP_READY_INT_CLR + Write 1 to clear H264_DB_TMP_READY_INT. + 0 + 1 + write-only + + + REC_READY_INT_CLR + Write 1 to clear H264_REC_READY_INT. + 1 + 1 + write-only + + + FRAME_DONE_INT_CLR + Write 1 to clear H264_FRAME_DONE_INT. + 2 + 1 + write-only + + + DMA_MOVE_2MB_LINE_DONE_INT_CLR + Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT. + 3 + 1 + write-only + + + + + CONF + General configuration register. + 0xD0 + 0x20 + + + CLK_EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 0 + 1 + read-write + + + REC_RAM_CLK_EN2 + Configures whether or not to open the clock gate for rec ram2.\\0: Open the clock gate only when application writes or reads rec ram2\\1: Force open the clock gate for rec ram2 + 1 + 1 + read-write + + + REC_RAM_CLK_EN1 + Configures whether or not to open the clock gate for rec ram1.\\0: Open the clock gate only when application writes or reads rec ram1\\1: Force open the clock gate for rec ram1 + 2 + 1 + read-write + + + QUANT_RAM_CLK_EN2 + Configures whether or not to open the clock gate for quant ram2.\\0: Open the clock gate only when application writes or reads quant ram2\\1: Force open the clock gate for quant ram2 + 3 + 1 + read-write + + + QUANT_RAM_CLK_EN1 + Configures whether or not to open the clock gate for quant ram1.\\0: Open the clock gate only when application writes or reads quant ram1\\1: Force open the clock gate for quant ram1 + 4 + 1 + read-write + + + PRE_RAM_CLK_EN + Configures whether or not to open the clock gate for pre ram.\\0: Open the clock gate only when application writes or reads pre ram\\1: Force open the clock gate for pre ram + 5 + 1 + read-write + + + MVD_RAM_CLK_EN + Configures whether or not to open the clock gate for mvd ram.\\0: Open the clock gate only when application writes or reads mvd ram\\1: Force open the clock gate for mvd ram + 6 + 1 + read-write + + + MC_RAM_CLK_EN + Configures whether or not to open the clock gate for mc ram.\\0: Open the clock gate only when application writes or reads mc ram\\1: Force open the clock gate for mc ram + 7 + 1 + read-write + + + REF_RAM_CLK_EN + Configures whether or not to open the clock gate for ref ram.\\0: Open the clock gate only when application writes or reads ref ram\\1: Force open the clock gate for ref ram + 8 + 1 + read-write + + + I4X4_REF_RAM_CLK_EN + Configures whether or not to open the clock gate for i4x4_mode ram.\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\1: Force open the clock gate for i4x4_mode ram + 9 + 1 + read-write + + + IME_RAM_CLK_EN + Configures whether or not to open the clock gate for ime ram.\\0: Open the clock gate only when application writes or reads ime ram\\1: Force open the clock gate for ime ram + 10 + 1 + read-write + + + FME_RAM_CLK_EN + Configures whether or not to open the clock gate for fme ram.\\0: Open the clock gate only when application writes or readsfme ram\\1: Force open the clock gate for fme ram + 11 + 1 + read-write + + + FETCH_RAM_CLK_EN + Configures whether or not to open the clock gate for fetch ram.\\0: Open the clock gate only when application writes or reads fetch ram\\1: Force open the clock gate for fetch ram + 12 + 1 + read-write + + + DB_RAM_CLK_EN + Configures whether or not to open the clock gate for db ram.\\0: Open the clock gate only when application writes or reads db ram\\1: Force open the clock gate for db ram + 13 + 1 + read-write + + + CUR_MB_RAM_CLK_EN + Configures whether or not to open the clock gate for cur_mb ram.\\0: Open the clock gate only when application writes or reads cur_mb ram\\1: Force open the clock gate for cur_mb ram + 14 + 1 + read-write + + + CAVLC_RAM_CLK_EN + Configures whether or not to open the clock gate for cavlc ram.\\0: Open the clock gate only when application writes or reads cavlc ram\\1: Force open the clock gate for cavlc ram + 15 + 1 + read-write + + + IME_CLK_EN + Configures whether or not to open the clock gate for ime.\\0: Open the clock gate only when ime work\\1: Force open the clock gate for ime + 16 + 1 + read-write + + + FME_CLK_EN + Configures whether or not to open the clock gate for fme.\\0: Open the clock gate only when fme work\\1: Force open the clock gate for fme + 17 + 1 + read-write + + + MC_CLK_EN + Configures whether or not to open the clock gate for mc.\\0: Open the clock gate only when mc work\\1: Force open the clock gate for mc + 18 + 1 + read-write + + + INTERPOLATOR_CLK_EN + Configures whether or not to open the clock gate for interpolator.\\0: Open the clock gate only when interpolator work\\1: Force open the clock gate for interpolator + 19 + 1 + read-write + + + DB_CLK_EN + Configures whether or not to open the clock gate for deblocking filter.\\0: Open the clock gate only when deblocking filter work\\1: Force open the clock gate for deblocking filter + 20 + 1 + read-write + + + CLAVLC_CLK_EN + Configures whether or not to open the clock gate for cavlc.\\0: Open the clock gate only when cavlc work\\1: Force open the clock gate for cavlc + 21 + 1 + read-write + + + INTRA_CLK_EN + Configures whether or not to open the clock gate for intra.\\0: Open the clock gate only when intra work\\1: Force open the clock gate for intra + 22 + 1 + read-write + + + DECI_CLK_EN + Configures whether or not to open the clock gate for decimate.\\0: Open the clock gate only when decimate work\\1: Force open the clock gate for decimate + 23 + 1 + read-write + + + BS_CLK_EN + Configures whether or not to open the clock gate for bs buffer.\\0: Open the clock gate only when bs buffer work\\1: Force open the clock gate for bs buffer + 24 + 1 + read-write + + + MV_MERGE_CLK_EN + Configures whether or not to open the clock gate for mv merge.\\0: Open the clock gate only when mv merge work\\1: Force open the clock gate for mv merge + 25 + 1 + read-write + + + + + MV_MERGE_CONFIG + Mv merge configuration register. + 0xD4 + 0x20 + + + MV_MERGE_TYPE + Configure mv merge type.\\0: merge p16x16 mv\\1: merge min mv\\2: merge max mv\\3: not valid. + 0 + 2 + read-write + + + INT_MV_OUT_EN + Configure mv merge output integer part not zero mv or all part not zero mv.\\0: output all part not zero mv\\1: output integer part not zero mv. + 2 + 1 + read-write + + + A_MV_MERGE_EN + Configure whether or not to enable video A mv merge.\\0: disable\\1: enable. + 3 + 1 + read-write + + + B_MV_MERGE_EN + Configure whether or not to enable video B mv merge.\\0: disable\\1: enable. + 4 + 1 + read-write + + + MB_VALID_NUM + Represents the valid mb number of mv merge output. + 5 + 13 + read-only + + + + + DEBUG_DMA_SEL + Debug H264 DMA select register + 0xD8 + 0x20 + + + DBG_DMA_SEL + Every bit represents a dma in h264 + 0 + 8 + read-write + + + + + SYS_STATUS + System status register. + 0xDC + 0x20 + + + FRAME_NUM + Represents current frame number. + 0 + 9 + read-only + + + DUAL_STREAM_SEL + Represents which register group is used for cur frame.\\0: Register group A is used\\1: Register group B is used. + 9 + 1 + read-only + + + INTRA_FLAG + Represents the type of current encoding frame.\\0: P frame\\1: I frame. + 10 + 1 + read-only + + + + + FRAME_CODE_LENGTH + Frame code byte length register. + 0xE0 + 0x20 + + + FRAME_CODE_LENGTH + Represents current frame code byte length. + 0 + 24 + read-only + + + + + DEBUG_INFO0 + Debug information register0. + 0xE4 + 0x20 + + + TOP_CTRL_INTER_DEBUG_STATE + Represents top_ctrl_inter module FSM info. + 0 + 4 + read-only + + + TOP_CTRL_INTRA_DEBUG_STATE + Represents top_ctrl_intra module FSM info. + 4 + 3 + read-only + + + P_I_CMP_DEBUG_STATE + Represents p_i_cmp module FSM info. + 7 + 3 + read-only + + + MVD_DEBUG_STATE + Represents mvd module FSM info. + 10 + 3 + read-only + + + MC_CHROMA_IP_DEBUG_STATE + Represents mc_chroma_ip module FSM info. + 13 + 1 + read-only + + + INTRA_16X16_CHROMA_CTRL_DEBUG_STATE + Represents intra_16x16_chroma_ctrl module FSM info. + 14 + 4 + read-only + + + INTRA_4X4_CTRL_DEBUG_STATE + Represents intra_4x4_ctrl module FSM info. + 18 + 4 + read-only + + + INTRA_TOP_CTRL_DEBUG_STATE + Represents intra_top_ctrl module FSM info. + 22 + 3 + read-only + + + IME_CTRL_DEBUG_STATE + Represents ime_ctrl module FSM info. + 25 + 3 + read-only + + + + + DEBUG_INFO1 + Debug information register1. + 0xE8 + 0x20 + + + FME_CTRL_DEBUG_STATE + Represents fme_ctrl module FSM info. + 0 + 3 + read-only + + + DECI_CALC_DEBUG_STATE + Represents deci_calc module's FSM info. DEV use only. + 3 + 2 + read-only + + + DB_DEBUG_STATE + Represents db module FSM info. + 5 + 3 + read-only + + + CAVLC_ENC_DEBUG_STATE + Represents cavlc module enc FSM info. + 8 + 4 + read-only + + + CAVLC_SCAN_DEBUG_STATE + Represents cavlc module scan FSM info. + 12 + 4 + read-only + + + CAVLC_CTRL_DEBUG_STATE + Represents cavlc module ctrl FSM info. + 16 + 2 + read-only + + + BS_BUFFER_DEBUG_STATE + Represents bs buffer overflow info. + 18 + 1 + read-only + + + + + DEBUG_INFO2 + Debug information register2. + 0xEC + 0x20 + + + P_RC_DONE_DEBUG_FLAG + Represents p rate ctrl done status.\\0: not done\\1: done. + 0 + 1 + read-only + + + P_P_I_CMP_DONE_DEBUG_FLAG + Represents p p_i_cmp done status.\\0: not done\\1: done. + 1 + 1 + read-only + + + P_MV_MERGE_DONE_DEBUG_FLAG + Represents p mv merge done status.\\0: not done\\1: done. + 2 + 1 + read-only + + + P_MOVE_ORI_DONE_DEBUG_FLAG + Represents p move origin done status.\\0: not done\\1: done. + 3 + 1 + read-only + + + P_MC_DONE_DEBUG_FLAG + Represents p mc done status.\\0: not done\\1: done. + 4 + 1 + read-only + + + P_IME_DONE_DEBUG_FLAG + Represents p ime done status.\\0: not done\\1: done. + 5 + 1 + read-only + + + P_GET_ORI_DONE_DEBUG_FLAG + Represents p get origin done status.\\0: not done\\1: done. + 6 + 1 + read-only + + + P_FME_DONE_DEBUG_FLAG + Represents p fme done status.\\0: not done\\1: done. + 7 + 1 + read-only + + + P_FETCH_DONE_DEBUG_FLAG + Represents p fetch done status.\\0: not done\\1: done. + 8 + 1 + read-only + + + P_DB_DONE_DEBUG_FLAG + Represents p deblocking done status.\\0: not done\\1: done. + 9 + 1 + read-only + + + P_BS_BUF_DONE_DEBUG_FLAG + Represents p bitstream buffer done status.\\0: not done\\1: done. + 10 + 1 + read-only + + + REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG + Represents dma move 2 ref mb line done status.\\0: not done\\1: done. + 11 + 1 + read-only + + + I_P_I_CMP_DONE_DEBUG_FLAG + Represents I p_i_cmp done status.\\0: not done\\1: done. + 12 + 1 + read-only + + + I_MOVE_ORI_DONE_DEBUG_FLAG + Represents I move origin done status.\\0: not done\\1: done. + 13 + 1 + read-only + + + I_GET_ORI_DONE_DEBUG_FLAG + Represents I get origin done status.\\0: not done\\1: done. + 14 + 1 + read-only + + + I_EC_DONE_DEBUG_FLAG + Represents I encoder done status.\\0: not done\\1: done. + 15 + 1 + read-only + + + I_DB_DONE_DEBUG_FLAG + Represents I deblocking done status.\\0: not done\\1: done. + 16 + 1 + read-only + + + I_BS_BUF_DONE_DEBUG_FLAG + Represents I bitstream buffer done status.\\0: not done\\1: done. + 17 + 1 + read-only + + + + + DATE + Version control register + 0xF0 + 0x20 + 0x02304240 + + + LEDC_DATE + Configures the version. + 0 + 28 + read-write + + + + + + + H264_DMA + H264 Encoder (DMA) + H264_DMA + 0x500A7000 + + 0x0 + 0x3DC + registers + + + H264_DMA2D_OUT_CH0 + 115 + + + H264_DMA2D_OUT_CH1 + 116 + + + H264_DMA2D_OUT_CH2 + 117 + + + H264_DMA2D_OUT_CH3 + 118 + + + H264_DMA2D_OUT_CH4 + 119 + + + H264_DMA2D_IN_CH0 + 120 + + + H264_DMA2D_IN_CH1 + 121 + + + H264_DMA2D_IN_CH2 + 122 + + + H264_DMA2D_IN_CH3 + 123 + + + H264_DMA2D_IN_CH4 + 124 + + + H264_DMA2D_IN_CH5 + 125 + + + + OUT_CONF0_CH0 + TX CH0 config0 register + 0x0 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH0 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH0 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH0 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH0 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH0 + Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH0 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_REORDER_EN_CH0 + Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection + 16 + 1 + read-write + + + OUT_RST_CH0 + Write 1 then write 0 to this bit to reset TX channel + 24 + 1 + read-write + + + OUT_CMD_DISABLE_CH0 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH0 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH0 + TX CH0 interrupt raw register + 0x4 + 0x20 + + + OUT_DONE_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH0_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH0_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH0 + TX CH0 interrupt ena register + 0x8 + 0x20 + + + OUT_DONE_CH0_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH0_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH0_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH0_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH0_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH0_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH0 + TX CH0 interrupt st register + 0xC + 0x20 + + + OUT_DONE_CH0_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH0_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH0_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH0_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH0_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH0_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH0 + TX CH0 interrupt clr register + 0x10 + 0x20 + + + OUT_DONE_CH0_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH0_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH0_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH0_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH0_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH0_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH0_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH0_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH0_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH0 + TX CH0 outfifo status register + 0x14 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH0 + Tx FIFO full signal for Tx channel 0. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH0 + Tx FIFO empty signal for Tx channel 0. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH0 + Tx FIFO full signal for Tx channel 0. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH0 + Tx FIFO empty signal for Tx channel 0. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH0 + Tx FIFO full signal for Tx channel 0. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH0 + Tx FIFO empty signal for Tx channel 0. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH0 + The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + 18 + 2 + read-only + + + + + OUT_PUSH_CH0 + TX CH0 outfifo push register + 0x18 + 0x20 + + + OUTFIFO_WDATA_CH0 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH0 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH0 + TX CH0 out_link dscr ctrl register + 0x1C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH0 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH0 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH0 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH0 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH0 + TX CH0 out_link dscr addr register + 0x20 + 0x20 + + + OUTLINK_ADDR_CH0 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH0 + TX CH0 state register + 0x24 + 0x20 + 0x01000000 + + + OUTLINK_DSCR_ADDR_CH0 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH0 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH0 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH0 + This register indicate that if the channel reset is safety. + 24 + 1 + read-only + + + + + OUT_EOF_DES_ADDR_CH0 + TX CH0 eof des addr register + 0x28 + 0x20 + + + OUT_EOF_DES_ADDR_CH0 + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH0 + TX CH0 next dscr addr register + 0x2C + 0x20 + + + OUTLINK_DSCR_CH0 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH0 + TX CH0 last dscr addr register + 0x30 + 0x20 + + + OUTLINK_DSCR_BF0_CH0 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH0 + TX CH0 second-to-last dscr addr register + 0x34 + 0x20 + + + OUTLINK_DSCR_BF1_CH0 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH0 + TX CH0 arb register + 0x3C + 0x20 + 0x00000011 + + + OUT_ARB_TOKEN_NUM_CH0 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_OUT_ARB_PRIORITY_CH0 + Set the priority of channel + 4 + 2 + read-write + + + + + OUT_RO_STATUS_CH0 + TX CH0 reorder status register + 0x40 + 0x20 + 0x00000800 + + + OUTFIFO_RO_CNT_CH0 + The register stores the 8byte number of the data in reorder Tx FIFO for channel 0. + 0 + 2 + read-only + + + OUT_RO_WR_STATE_CH0 + The register stores the state of read ram of reorder + 6 + 2 + read-only + + + OUT_RO_RD_STATE_CH0 + The register stores the state of write ram of reorder + 8 + 2 + read-only + + + OUT_PIXEL_BYTE_CH0 + the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes + 10 + 4 + read-only + + + OUT_BURST_BLOCK_NUM_CH0 + the number of macro blocks contained in a burst of data at TX channel + 14 + 4 + read-only + + + + + OUT_RO_PD_CONF_CH0 + TX CH0 reorder power config register + 0x44 + 0x20 + 0x00000020 + + + OUT_RO_RAM_FORCE_PD_CH0 + dma reorder ram power down + 4 + 1 + read-write + + + OUT_RO_RAM_FORCE_PU_CH0 + dma reorder ram power up + 5 + 1 + read-write + + + OUT_RO_RAM_CLK_FO_CH0 + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. + 6 + 1 + read-write + + + + + OUT_MODE_ENABLE_CH0 + tx CH0 mode enable register + 0x50 + 0x20 + + + OUT_TEST_MODE_ENABLE_CH0 + tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode + 0 + 1 + read-write + + + + + OUT_MODE_YUV_CH0 + tx CH0 test mode yuv value register + 0x54 + 0x20 + + + OUT_TEST_Y_VALUE_CH0 + tx CH0 test mode y value + 0 + 8 + read-write + + + OUT_TEST_U_VALUE_CH0 + tx CH0 test mode u value + 8 + 8 + read-write + + + OUT_TEST_V_VALUE_CH0 + tx CH0 test mode v value + 16 + 8 + read-write + + + + + OUT_ETM_CONF_CH0 + TX CH0 ETM config register + 0x68 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH0 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH0 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH0 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH0 + tx CH0 buf len register + 0x70 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH0 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH0 + tx CH0 fifo byte cnt register + 0x74 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH0 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH0 + tx CH0 push byte cnt register + 0x78 + 0x20 + 0x000000FF + + + OUT_CMDFIFO_PUSH_BYTECNT_CH0 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH0 + tx CH0 xaddr register + 0x7C + 0x20 + + + OUT_CMDFIFO_XADDR_CH0 + only for debug + 0 + 32 + read-only + + + + + OUT_CONF0_CH1 + TX CH1 config0 register + 0x100 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH1 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH1 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH1 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH1 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH1 + Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 64 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH1 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_RST_CH1 + Write 1 then write 0 to this bit to reset TX channel + 24 + 1 + read-write + + + OUT_CMD_DISABLE_CH1 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH1 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH1 + TX CH1 interrupt raw register + 0x104 + 0x20 + + + OUT_DONE_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH1_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH1_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH1_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH1 + TX CH1 interrupt ena register + 0x108 + 0x20 + + + OUT_DONE_CH1_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH1_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH1_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH1_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH1_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH1_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH1 + TX CH1 interrupt st register + 0x10C + 0x20 + + + OUT_DONE_CH1_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH1_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH1_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH1_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH1_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH1_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH1 + TX CH1 interrupt clr register + 0x110 + 0x20 + + + OUT_DONE_CH1_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH1_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH1_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH1_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH1_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH1_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH1_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH1_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH1_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH1 + TX CH1 outfifo status register + 0x114 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH1 + Tx FIFO full signal for Tx channel 1. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH1 + Tx FIFO empty signal for Tx channel 1. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH1 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH1 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH1 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH1 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + OUT_PUSH_CH1 + TX CH1 outfifo push register + 0x118 + 0x20 + + + OUTFIFO_WDATA_CH1 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH1 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH1 + TX CH1 out_link dscr ctrl register + 0x11C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH1 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH1 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH1 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH1 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH1 + TX CH1 out_link dscr addr register + 0x120 + 0x20 + + + OUTLINK_ADDR_CH1 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH1 + TX CH1 state register + 0x124 + 0x20 + 0x01000000 + + + OUTLINK_DSCR_ADDR_CH1 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH1 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH1 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH1 + This register indicate that if the channel reset is safety. + 24 + 1 + read-only + + + + + OUT_EOF_DES_ADDR_CH1 + TX CH1 eof des addr register + 0x128 + 0x20 + + + OUT_EOF_DES_ADDR_CH1 + This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH1 + TX CH1 next dscr addr register + 0x12C + 0x20 + + + OUTLINK_DSCR_CH1 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH1 + TX CH1 last dscr addr register + 0x130 + 0x20 + + + OUTLINK_DSCR_BF0_CH1 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH1 + TX CH1 second-to-last dscr addr register + 0x134 + 0x20 + + + OUTLINK_DSCR_BF1_CH1 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH1 + TX CH1 arb register + 0x13C + 0x20 + 0x00000041 + + + OUT_ARB_TOKEN_NUM_CH1 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_OUT_ARB_PRIORITY_CH1 + Set the priority of channel + 6 + 1 + read-write + + + + + OUT_ETM_CONF_CH1 + TX CH1 ETM config register + 0x168 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH1 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH1 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH1 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH1 + tx CH1 buf len register + 0x170 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH1 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH1 + tx CH1 fifo byte cnt register + 0x174 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH1 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH1 + tx CH1 push byte cnt register + 0x178 + 0x20 + 0x000000FF + + + OUT_CMDFIFO_PUSH_BYTECNT_CH1 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH1 + tx CH1 xaddr register + 0x17C + 0x20 + + + OUT_CMDFIFO_XADDR_CH1 + only for debug + 0 + 32 + read-only + + + + + OUT_CONF0_CH2 + TX CH2 config0 register + 0x200 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH2 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH2 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH2 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH2 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH2 + Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH2 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_RST_CH2 + Write 1 then write 0 to this bit to reset TX channel + 24 + 1 + read-write + + + OUT_CMD_DISABLE_CH2 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH2 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH2 + TX CH2 interrupt raw register + 0x204 + 0x20 + + + OUT_DONE_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH2_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH2_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH2_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH2 + TX CH2 interrupt ena register + 0x208 + 0x20 + + + OUT_DONE_CH2_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH2_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH2_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH2_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH2_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH2_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH2 + TX CH2 interrupt st register + 0x20C + 0x20 + + + OUT_DONE_CH2_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH2_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH2_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH2_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH2_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH2_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH2 + TX CH2 interrupt clr register + 0x210 + 0x20 + + + OUT_DONE_CH2_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH2_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH2_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH2_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH2_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH2_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH2_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH2_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH2_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH2 + TX CH2 outfifo status register + 0x214 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH2 + Tx FIFO full signal for Tx channel 2. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH2 + Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH2 + Tx FIFO full signal for Tx channel 2. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH2 + Tx FIFO empty signal for Tx channel 2. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH2 + Tx FIFO full signal for Tx channel 2. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH2 + Tx FIFO empty signal for Tx channel 2. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 18 + 2 + read-only + + + + + OUT_PUSH_CH2 + TX CH2 outfifo push register + 0x218 + 0x20 + + + OUTFIFO_WDATA_CH2 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH2 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH2 + TX CH2 out_link dscr ctrl register + 0x21C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH2 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH2 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH2 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH2 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH2 + TX CH2 out_link dscr addr register + 0x220 + 0x20 + + + OUTLINK_ADDR_CH2 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH2 + TX CH2 state register + 0x224 + 0x20 + 0x01000000 + + + OUTLINK_DSCR_ADDR_CH2 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH2 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH2 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + OUT_RESET_AVAIL_CH2 + This register indicate that if the channel reset is safety. + 24 + 1 + read-only + + + + + OUT_EOF_DES_ADDR_CH2 + TX CH2 eof des addr register + 0x228 + 0x20 + + + OUT_EOF_DES_ADDR_CH2 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH2 + TX CH2 next dscr addr register + 0x22C + 0x20 + + + OUTLINK_DSCR_CH2 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH2 + TX CH2 last dscr addr register + 0x230 + 0x20 + + + OUTLINK_DSCR_BF0_CH2 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH2 + TX CH2 second-to-last dscr addr register + 0x234 + 0x20 + + + OUTLINK_DSCR_BF1_CH2 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH2 + TX CH2 arb register + 0x23C + 0x20 + 0x00000041 + + + OUT_ARB_TOKEN_NUM_CH2 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_OUT_ARB_PRIORITY_CH2 + Set the priority of channel + 6 + 1 + read-write + + + + + OUT_ETM_CONF_CH2 + TX CH2 ETM config register + 0x268 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH2 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH2 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH2 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH2 + tx CH2 buf len register + 0x270 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH2 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH2 + tx CH2 fifo byte cnt register + 0x274 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH2 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH2 + tx CH2 push byte cnt register + 0x278 + 0x20 + 0x000000FF + + + OUT_CMDFIFO_PUSH_BYTECNT_CH2 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH2 + tx CH2 xaddr register + 0x27C + 0x20 + + + OUT_CMDFIFO_XADDR_CH2 + only for debug + 0 + 32 + read-only + + + + + OUT_CONF0_CH3 + TX CH3 config0 register + 0x300 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH3 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH3 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH3 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH3 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH3 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH3 + Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH3 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH3 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH3 + TX CH3 interrupt raw register + 0x304 + 0x20 + + + OUT_DONE_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH3_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH3_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH3_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH3 + TX CH3 interrupt ena register + 0x308 + 0x20 + + + OUT_DONE_CH3_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH3_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH3_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH3_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH3_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH3_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH3 + TX CH3 interrupt st register + 0x30C + 0x20 + + + OUT_DONE_CH3_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH3_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH3_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH3_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH3_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH3_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH3 + TX CH3 interrupt clr register + 0x310 + 0x20 + + + OUT_DONE_CH3_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH3_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH3_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH3_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH3_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH3_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH3_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH3_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH3_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH3 + TX CH3 outfifo status register + 0x314 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH3 + Tx FIFO full signal for Tx channel 2. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH3 + Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH3 + Tx FIFO full signal for Tx channel 2. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH3 + Tx FIFO empty signal for Tx channel 2. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH3 + Tx FIFO full signal for Tx channel 2. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH3 + Tx FIFO empty signal for Tx channel 2. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 18 + 2 + read-only + + + + + OUT_PUSH_CH3 + TX CH3 outfifo push register + 0x318 + 0x20 + + + OUTFIFO_WDATA_CH3 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH3 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH3 + TX CH3 out_link dscr ctrl register + 0x31C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH3 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH3 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH3 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH3 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH3 + TX CH3 out_link dscr addr register + 0x320 + 0x20 + + + OUTLINK_ADDR_CH3 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH3 + TX CH3 state register + 0x324 + 0x20 + + + OUTLINK_DSCR_ADDR_CH3 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH3 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH3 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + + + OUT_EOF_DES_ADDR_CH3 + TX CH3 eof des addr register + 0x328 + 0x20 + + + OUT_EOF_DES_ADDR_CH3 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH3 + TX CH3 next dscr addr register + 0x32C + 0x20 + + + OUTLINK_DSCR_CH3 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH3 + TX CH3 last dscr addr register + 0x330 + 0x20 + + + OUTLINK_DSCR_BF0_CH3 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH3 + TX CH3 second-to-last dscr addr register + 0x334 + 0x20 + + + OUTLINK_DSCR_BF1_CH3 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH3 + TX CH3 arb register + 0x33C + 0x20 + 0x00000011 + + + OUT_ARB_TOKEN_NUM_CH3 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_OUT_ARB_PRIORITY_CH3 + Set the priority of channel + 4 + 2 + read-write + + + + + OUT_ETM_CONF_CH3 + TX CH3 ETM config register + 0x368 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH3 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH3 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH3 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH3 + tx CH3 buf len register + 0x370 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH3 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH3 + tx CH3 fifo byte cnt register + 0x374 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH3 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH3 + tx CH3 push byte cnt register + 0x378 + 0x20 + 0x0000003F + + + OUT_CMDFIFO_PUSH_BYTECNT_CH3 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH3 + tx CH3 xaddr register + 0x37C + 0x20 + + + OUT_CMDFIFO_XADDR_CH3 + only for debug + 0 + 32 + read-only + + + + + OUT_BLOCK_BUF_LEN_CH3 + tx CH3 block buf len register + 0x380 + 0x20 + + + OUT_BLOCK_BUF_LEN_CH3 + only for debug + 0 + 28 + read-only + + + + + OUT_CONF0_CH4 + TX CH4 config0 register + 0x400 + 0x20 + 0x00000002 + + + OUT_AUTO_WRBACK_CH4 + Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + 0 + 1 + read-write + + + OUT_EOF_MODE_CH4 + EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA + 1 + 1 + read-write + + + OUTDSCR_BURST_EN_CH4 + Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + 2 + 1 + read-write + + + OUT_ECC_AES_EN_CH4 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + OUT_CHECK_OWNER_CH4 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + OUT_MEM_BURST_LENGTH_CH4 + Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + OUT_PAGE_BOUND_EN_CH4 + Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + OUT_ARB_WEIGHT_OPT_DIS_CH4 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + OUT_INT_RAW_CH4 + TX CH4 interrupt raw register + 0x404 + 0x20 + + + OUT_DONE_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + 0 + 1 + read-write + + + OUT_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH4_INT_RAW + The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is overflow. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH4_INT_RAW + The raw interrupt bit turns to high level when fifo is underflow. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH4_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 8 + 1 + read-write + + + + + OUT_INT_ENA_CH4 + TX CH4 interrupt ena register + 0x408 + 0x20 + + + OUT_DONE_CH4_INT_ENA + The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + OUT_EOF_CH4_INT_ENA + The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + OUT_DSCR_ERR_CH4_INT_ENA + The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-write + + + OUT_TOTAL_EOF_CH4_INT_ENA + The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-write + + + OUTFIFO_OVF_L1_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + OUTFIFO_UDF_L1_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + OUTFIFO_OVF_L2_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + OUTFIFO_UDF_L2_CH4_INT_ENA + The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + OUT_DSCR_TASK_OVF_CH4_INT_ENA + The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-write + + + + + OUT_INT_ST_CH4 + TX CH4 interrupt st register + 0x40C + 0x20 + + + OUT_DONE_CH4_INT_ST + The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + OUT_EOF_CH4_INT_ST + The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + OUT_DSCR_ERR_CH4_INT_ST + The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + read-only + + + OUT_TOTAL_EOF_CH4_INT_ST + The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + read-only + + + OUTFIFO_OVF_L1_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + OUTFIFO_UDF_L1_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + OUTFIFO_OVF_L2_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + OUTFIFO_UDF_L2_CH4_INT_ST + The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + OUT_DSCR_TASK_OVF_CH4_INT_ST + The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + read-only + + + + + OUT_INT_CLR_CH4 + TX CH4 interrupt clr register + 0x410 + 0x20 + + + OUT_DONE_CH4_INT_CLR + Set this bit to clear the OUT_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + OUT_EOF_CH4_INT_CLR + Set this bit to clear the OUT_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + OUT_DSCR_ERR_CH4_INT_CLR + Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + 2 + 1 + write-only + + + OUT_TOTAL_EOF_CH4_INT_CLR + Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + 3 + 1 + write-only + + + OUTFIFO_OVF_L1_CH4_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + OUTFIFO_UDF_L1_CH4_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + OUTFIFO_OVF_L2_CH4_INT_CLR + Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + OUTFIFO_UDF_L2_CH4_INT_CLR + Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + OUT_DSCR_TASK_OVF_CH4_INT_CLR + Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + 8 + 1 + write-only + + + + + OUTFIFO_STATUS_CH4 + TX CH4 outfifo status register + 0x414 + 0x20 + 0x00020082 + + + OUTFIFO_FULL_L2_CH4 + Tx FIFO full signal for Tx channel 2. + 0 + 1 + read-only + + + OUTFIFO_EMPTY_L2_CH4 + Tx FIFO empty signal for Tx channel 2. + 1 + 1 + read-only + + + OUTFIFO_CNT_L2_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 2 + 4 + read-only + + + OUTFIFO_FULL_L1_CH4 + Tx FIFO full signal for Tx channel 2. + 6 + 1 + read-only + + + OUTFIFO_EMPTY_L1_CH4 + Tx FIFO empty signal for Tx channel 2. + 7 + 1 + read-only + + + OUTFIFO_CNT_L1_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 8 + 5 + read-only + + + OUTFIFO_FULL_L3_CH4 + Tx FIFO full signal for Tx channel 2. + 16 + 1 + read-only + + + OUTFIFO_EMPTY_L3_CH4 + Tx FIFO empty signal for Tx channel 2. + 17 + 1 + read-only + + + OUTFIFO_CNT_L3_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 2. + 18 + 2 + read-only + + + + + OUT_PUSH_CH4 + TX CH4 outfifo push register + 0x418 + 0x20 + + + OUTFIFO_WDATA_CH4 + This register stores the data that need to be pushed into DMA Tx FIFO. + 0 + 10 + read-write + + + OUTFIFO_PUSH_CH4 + Set this bit to push data into DMA Tx FIFO. + 10 + 1 + read-write + + + + + OUT_LINK_CONF_CH4 + TX CH4 out_link dscr ctrl register + 0x41C + 0x20 + 0x00800000 + + + OUTLINK_STOP_CH4 + Set this bit to stop dealing with the outlink descriptors. + 20 + 1 + read-write + + + OUTLINK_START_CH4 + Set this bit to start dealing with the outlink descriptors. + 21 + 1 + read-write + + + OUTLINK_RESTART_CH4 + Set this bit to restart a new outlink from the last address. + 22 + 1 + read-write + + + OUTLINK_PARK_CH4 + 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. + 23 + 1 + read-only + + + + + OUT_LINK_ADDR_CH4 + TX CH4 out_link dscr addr register + 0x420 + 0x20 + + + OUTLINK_ADDR_CH4 + This register stores the first outlink descriptor's address. + 0 + 32 + read-write + + + + + OUT_STATE_CH4 + TX CH4 state register + 0x424 + 0x20 + + + OUTLINK_DSCR_ADDR_CH4 + This register stores the current outlink descriptor's address. + 0 + 18 + read-only + + + OUT_DSCR_STATE_CH4 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + OUT_STATE_CH4 + This register stores the current control module state machine state. + 20 + 4 + read-only + + + + + OUT_EOF_DES_ADDR_CH4 + TX CH4 eof des addr register + 0x428 + 0x20 + + + OUT_EOF_DES_ADDR_CH4 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + OUT_DSCR_CH4 + TX CH4 next dscr addr register + 0x42C + 0x20 + + + OUTLINK_DSCR_CH4 + The address of the next outlink descriptor address y. + 0 + 32 + read-only + + + + + OUT_DSCR_BF0_CH4 + TX CH4 last dscr addr register + 0x430 + 0x20 + + + OUTLINK_DSCR_BF0_CH4 + The address of the last outlink descriptor's next address y-1. + 0 + 32 + read-only + + + + + OUT_DSCR_BF1_CH4 + TX CH4 second-to-last dscr addr register + 0x434 + 0x20 + + + OUTLINK_DSCR_BF1_CH4 + The address of the second-to-last outlink descriptor's next address y-2. + 0 + 32 + read-only + + + + + OUT_ARB_CH4 + TX CH4 arb register + 0x43C + 0x20 + 0x00000011 + + + OUT_ARB_TOKEN_NUM_CH4 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_OUT_ARB_PRIORITY_CH4 + Set the priority of channel + 4 + 2 + read-write + + + + + OUT_ETM_CONF_CH4 + TX CH4 ETM config register + 0x468 + 0x20 + 0x00000004 + + + OUT_ETM_EN_CH4 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + OUT_ETM_LOOP_EN_CH4 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + OUT_DSCR_TASK_MAK_CH4 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + OUT_BUF_LEN_CH4 + tx CH4 buf len register + 0x470 + 0x20 + + + OUT_CMDFIFO_BUF_LEN_HB_CH4 + only for debug + 0 + 13 + read-only + + + + + OUT_FIFO_BCNT_CH4 + tx CH4 fifo byte cnt register + 0x474 + 0x20 + + + OUT_CMDFIFO_OUTFIFO_BCNT_CH4 + only for debug + 0 + 10 + read-only + + + + + OUT_PUSH_BYTECNT_CH4 + tx CH4 push byte cnt register + 0x478 + 0x20 + 0x0000003F + + + OUT_CMDFIFO_PUSH_BYTECNT_CH4 + only for debug + 0 + 8 + read-only + + + + + OUT_XADDR_CH4 + tx CH4 xaddr register + 0x47C + 0x20 + + + OUT_CMDFIFO_XADDR_CH4 + only for debug + 0 + 32 + read-only + + + + + OUT_BLOCK_BUF_LEN_CH4 + tx CH4 block buf len register + 0x480 + 0x20 + + + OUT_BLOCK_BUF_LEN_CH4 + only for debug + 0 + 28 + read-only + + + + + IN_CONF0_CH0 + RX CH0 config0 register + 0x500 + 0x20 + + + INDSCR_BURST_EN_CH0 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH0 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH0 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH0 + Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH0 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH0 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH0 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH0 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH0 + RX CH0 interrupt raw register + 0x504 + 0x20 + + + IN_DONE_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0. + 0 + 1 + read-write + + + IN_SUC_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + 1 + 1 + read-write + + + IN_ERR_EOF_CH0_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH0_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH0_INT_RAW + The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH0_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH0_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH0 + RX CH0 interrupt ena register + 0x508 + 0x20 + + + IN_DONE_CH0_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH0_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH0_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH0_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH0_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH0_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH0_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH0_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH0 + RX CH0 interrupt st register + 0x50C + 0x20 + + + IN_DONE_CH0_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH0_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH0_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH0_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH0_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH0_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH0_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH0_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH0 + RX CH0 interrupt clr register + 0x510 + 0x20 + + + IN_DONE_CH0_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH0_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH0_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH0_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH0_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH0_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH0_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH0_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH0_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH0_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH0 + RX CH0 INFIFO status register + 0x514 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH0 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH0 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH0 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH0 + Tx FIFO full signal for Tx channel 0. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH0 + Tx FIFO empty signal for Tx channel 0. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH0 + The register stores the byte number of the data in Tx FIFO for Tx channel 0. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH0 + Tx FIFO full signal for Tx channel 0. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH0 + Tx FIFO empty signal for Tx channel 0. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH0 + The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + 18 + 2 + read-only + + + + + IN_POP_CH0 + RX CH0 INFIFO pop register + 0x518 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH0 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH0 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH0 + RX CH0 in_link dscr ctrl register + 0x51C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH0 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH0 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH0 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH0 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH0 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH0 + RX CH0 in_link dscr addr register + 0x520 + 0x20 + + + INLINK_ADDR_CH0 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH0 + RX CH0 state register + 0x524 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH0 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH0 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH0 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH0 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH0 + RX CH0 eof des addr register + 0x528 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH0 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH0 + RX CH0 err eof des addr register + 0x52C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH0 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH0 + RX CH0 next dscr addr register + 0x530 + 0x20 + + + INLINK_DSCR_CH0 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH0 + RX CH0 last dscr addr register + 0x534 + 0x20 + + + INLINK_DSCR_BF0_CH0 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH0 + RX CH0 second-to-last dscr addr register + 0x538 + 0x20 + + + INLINK_DSCR_BF1_CH0 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH0 + RX CH0 arb register + 0x540 + 0x20 + 0x00000051 + + + IN_ARB_TOKEN_NUM_CH0 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_IN_ARB_PRIORITY_CH0 + Set the priority of channel + 4 + 2 + read-write + + + INTER_IN_ARB_PRIORITY_CH0 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_RO_PD_CONF_CH0 + RX CH0 reorder power config register + 0x548 + 0x20 + + + IN_RO_RAM_CLK_FO_CH0 + 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA. + 6 + 1 + read-write + + + + + IN_ETM_CONF_CH0 + RX CH0 ETM config register + 0x56C + 0x20 + 0x00000004 + + + IN_ETM_EN_CH0 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH0 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH0 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH0 + rx CH0 fifo cnt register + 0x580 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH0 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH0 + rx CH0 pop data cnt register + 0x584 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH0 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH0 + rx CH0 xaddr register + 0x588 + 0x20 + + + IN_CMDFIFO_XADDR_CH0 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH0 + rx CH0 buf len hb rcv register + 0x58C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH0 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH1 + RX CH1 config0 register + 0x600 + 0x20 + + + INDSCR_BURST_EN_CH1 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH1 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH1 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH1 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH1 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH1 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH1 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH1 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH1 + RX CH1 interrupt raw register + 0x604 + 0x20 + + + IN_DONE_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH1_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH1_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH1_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH1_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH1_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH1 + RX CH1 interrupt ena register + 0x608 + 0x20 + + + IN_DONE_CH1_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH1_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH1_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH1_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH1_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH1_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH1_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH1_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH1 + RX CH1 interrupt st register + 0x60C + 0x20 + + + IN_DONE_CH1_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH1_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH1_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH1_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH1_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH1_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH1_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH1_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH1 + RX CH1 interrupt clr register + 0x610 + 0x20 + + + IN_DONE_CH1_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH1_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH1_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH1_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH1_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH1_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH1_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH1_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH1_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH1_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH1 + RX CH1 INFIFO status register + 0x614 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH1 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH1 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH1 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH1 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH1 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH1 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH1 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH1 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH1 + RX CH1 INFIFO pop register + 0x618 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH1 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH1 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH1 + RX CH1 in_link dscr ctrl register + 0x61C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH1 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH1 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH1 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH1 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH1 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH1 + RX CH1 in_link dscr addr register + 0x620 + 0x20 + + + INLINK_ADDR_CH1 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH1 + RX CH1 state register + 0x624 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH1 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH1 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH1 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH1 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH1 + RX CH1 eof des addr register + 0x628 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH1 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH1 + RX CH1 err eof des addr register + 0x62C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH1 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH1 + RX CH1 next dscr addr register + 0x630 + 0x20 + + + INLINK_DSCR_CH1 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH1 + RX CH1 last dscr addr register + 0x634 + 0x20 + + + INLINK_DSCR_BF0_CH1 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH1 + RX CH1 second-to-last dscr addr register + 0x638 + 0x20 + + + INLINK_DSCR_BF1_CH1 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH1 + RX CH1 arb register + 0x640 + 0x20 + 0x00000051 + + + IN_ARB_TOKEN_NUM_CH1 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_IN_ARB_PRIORITY_CH1 + Set the priority of channel + 4 + 2 + read-write + + + INTER_IN_ARB_PRIORITY_CH1 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH1 + RX CH1 ETM config register + 0x648 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH1 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH1 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH1 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH1 + rx CH1 fifo cnt register + 0x680 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH1 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH1 + rx CH1 pop data cnt register + 0x684 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH1 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH1 + rx CH1 xaddr register + 0x688 + 0x20 + + + IN_CMDFIFO_XADDR_CH1 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH1 + rx CH1 buf len hb rcv register + 0x68C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH1 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH2 + RX CH2 config0 register + 0x700 + 0x20 + + + INDSCR_BURST_EN_CH2 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH2 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH2 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH2 + Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH2 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH2 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH2 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH2 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH2 + RX CH2 interrupt raw register + 0x704 + 0x20 + + + IN_DONE_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH2_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH2_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH2_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH2_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH2_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH2 + RX CH2 interrupt ena register + 0x708 + 0x20 + + + IN_DONE_CH2_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH2_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH2_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH2_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH2_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH2_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH2_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH2_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH2 + RX CH2 interrupt st register + 0x70C + 0x20 + + + IN_DONE_CH2_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH2_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH2_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH2_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH2_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH2_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH2_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH2_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH2 + RX CH2 interrupt clr register + 0x710 + 0x20 + + + IN_DONE_CH2_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH2_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH2_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH2_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH2_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH2_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH2_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH2_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH2_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH2_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH2 + RX CH2 INFIFO status register + 0x714 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH2 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH2 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH2 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH2 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH2 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH2 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH2 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH2 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH2 + RX CH2 INFIFO pop register + 0x718 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH2 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH2 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH2 + RX CH2 in_link dscr ctrl register + 0x71C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH2 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH2 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH2 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH2 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH2 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH2 + RX CH2 in_link dscr addr register + 0x720 + 0x20 + + + INLINK_ADDR_CH2 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH2 + RX CH2 state register + 0x724 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH2 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH2 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH2 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH2 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH2 + RX CH2 eof des addr register + 0x728 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH2 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH2 + RX CH2 err eof des addr register + 0x72C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH2 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH2 + RX CH2 next dscr addr register + 0x730 + 0x20 + + + INLINK_DSCR_CH2 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH2 + RX CH2 last dscr addr register + 0x734 + 0x20 + + + INLINK_DSCR_BF0_CH2 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH2 + RX CH2 second-to-last dscr addr register + 0x738 + 0x20 + + + INLINK_DSCR_BF1_CH2 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH2 + RX CH2 arb register + 0x740 + 0x20 + 0x00000041 + + + IN_ARB_TOKEN_NUM_CH2 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_IN_ARB_PRIORITY_CH2 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH2 + RX CH2 ETM config register + 0x748 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH2 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH2 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH2 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH2 + rx CH2 fifo cnt register + 0x780 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH2 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH2 + rx CH2 pop data cnt register + 0x784 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH2 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH2 + rx CH2 xaddr register + 0x788 + 0x20 + + + IN_CMDFIFO_XADDR_CH2 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH2 + rx CH2 buf len hb rcv register + 0x78C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH2 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH3 + RX CH3 config0 register + 0x800 + 0x20 + + + INDSCR_BURST_EN_CH3 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH3 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH3 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH3 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH3 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH3 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH3 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH3 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH3 + RX CH3 interrupt raw register + 0x804 + 0x20 + + + IN_DONE_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH3_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH3_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH3_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH3_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH3_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH3 + RX CH3 interrupt ena register + 0x808 + 0x20 + + + IN_DONE_CH3_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH3_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH3_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH3_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH3_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH3_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH3_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH3_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH3 + RX CH3 interrupt st register + 0x80C + 0x20 + + + IN_DONE_CH3_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH3_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH3_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH3_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH3_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH3_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH3_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH3_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH3 + RX CH3 interrupt clr register + 0x810 + 0x20 + + + IN_DONE_CH3_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH3_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH3_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH3_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH3_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH3_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH3_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH3_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH3_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH3_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH3 + RX CH3 INFIFO status register + 0x814 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH3 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH3 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH3 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH3 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH3 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH3 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH3 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH3 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH3 + RX CH3 INFIFO pop register + 0x818 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH3 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH3 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH3 + RX CH3 in_link dscr ctrl register + 0x81C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH3 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH3 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH3 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH3 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH3 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH3 + RX CH3 in_link dscr addr register + 0x820 + 0x20 + + + INLINK_ADDR_CH3 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH3 + RX CH3 state register + 0x824 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH3 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH3 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH3 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH3 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH3 + RX CH3 eof des addr register + 0x828 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH3 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH3 + RX CH3 err eof des addr register + 0x82C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH3 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH3 + RX CH3 next dscr addr register + 0x830 + 0x20 + + + INLINK_DSCR_CH3 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH3 + RX CH3 last dscr addr register + 0x834 + 0x20 + + + INLINK_DSCR_BF0_CH3 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH3 + RX CH3 second-to-last dscr addr register + 0x838 + 0x20 + + + INLINK_DSCR_BF1_CH3 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH3 + RX CH3 arb register + 0x840 + 0x20 + 0x00000041 + + + IN_ARB_TOKEN_NUM_CH3 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_IN_ARB_PRIORITY_CH3 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH3 + RX CH3 ETM config register + 0x848 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH3 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH3 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH3 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH3 + rx CH3 fifo cnt register + 0x880 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH3 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH3 + rx CH3 pop data cnt register + 0x884 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH3 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH3 + rx CH3 xaddr register + 0x888 + 0x20 + + + IN_CMDFIFO_XADDR_CH3 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH3 + rx CH3 buf len hb rcv register + 0x88C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH3 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH4 + RX CH4 config0 register + 0x900 + 0x20 + + + INDSCR_BURST_EN_CH4 + Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + 2 + 1 + read-write + + + IN_ECC_AES_EN_CH4 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_CHECK_OWNER_CH4 + Set this bit to enable checking the owner attribute of the link descriptor. + 4 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH4 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH4 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH4 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH4 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + IN_ARB_WEIGHT_OPT_DIS_CH4 + Set this bit to 1 to disable arbiter optimum weight function. + 26 + 1 + read-write + + + + + IN_INT_RAW_CH4 + RX CH4 interrupt raw register + 0x904 + 0x20 + + + IN_DONE_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + IN_ERR_EOF_CH4_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + 2 + 1 + read-write + + + IN_DSCR_ERR_CH4_INT_RAW + The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH4_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH4_INT_RAW + The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH4_INT_RAW + The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + 9 + 1 + read-write + + + + + IN_INT_ENA_CH4 + RX CH4 interrupt ena register + 0x908 + 0x20 + + + IN_DONE_CH4_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH4_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + IN_ERR_EOF_CH4_INT_ENA + The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-write + + + IN_DSCR_ERR_CH4_INT_ENA + The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-write + + + INFIFO_OVF_L1_CH4_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + INFIFO_UDF_L1_CH4_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-write + + + INFIFO_OVF_L2_CH4_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-write + + + INFIFO_UDF_L2_CH4_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-write + + + IN_DSCR_EMPTY_CH4_INT_ENA + The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-write + + + IN_DSCR_TASK_OVF_CH4_INT_ENA + The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-write + + + + + IN_INT_ST_CH4 + RX CH4 interrupt st register + 0x90C + 0x20 + + + IN_DONE_CH4_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH4_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + IN_ERR_EOF_CH4_INT_ST + The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + read-only + + + IN_DSCR_ERR_CH4_INT_ST + The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + 3 + 1 + read-only + + + INFIFO_OVF_L1_CH4_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + INFIFO_UDF_L1_CH4_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + read-only + + + INFIFO_OVF_L2_CH4_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + read-only + + + INFIFO_UDF_L2_CH4_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + read-only + + + IN_DSCR_EMPTY_CH4_INT_ST + The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + read-only + + + IN_DSCR_TASK_OVF_CH4_INT_ST + The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + read-only + + + + + IN_INT_CLR_CH4 + RX CH4 interrupt clr register + 0x910 + 0x20 + + + IN_DONE_CH4_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH4_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + IN_ERR_EOF_CH4_INT_CLR + Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + 2 + 1 + write-only + + + IN_DSCR_ERR_CH4_INT_CLR + Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + 3 + 1 + write-only + + + INFIFO_OVF_L1_CH4_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + INFIFO_UDF_L1_CH4_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 5 + 1 + write-only + + + INFIFO_OVF_L2_CH4_INT_CLR + Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + 6 + 1 + write-only + + + INFIFO_UDF_L2_CH4_INT_CLR + Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + 7 + 1 + write-only + + + IN_DSCR_EMPTY_CH4_INT_CLR + Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + 8 + 1 + write-only + + + IN_DSCR_TASK_OVF_CH4_INT_CLR + Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + 9 + 1 + write-only + + + + + INFIFO_STATUS_CH4 + RX CH4 INFIFO status register + 0x914 + 0x20 + 0x00020082 + + + INFIFO_FULL_L2_CH4 + Rx FIFO full signal for Rx channel. + 0 + 1 + read-only + + + INFIFO_EMPTY_L2_CH4 + Rx FIFO empty signal for Rx channel. + 1 + 1 + read-only + + + INFIFO_CNT_L2_CH4 + The register stores the byte number of the data in Rx FIFO for Rx channel. + 2 + 4 + read-only + + + INFIFO_FULL_L1_CH4 + Tx FIFO full signal for Tx channel 1. + 6 + 1 + read-only + + + INFIFO_EMPTY_L1_CH4 + Tx FIFO empty signal for Tx channel 1. + 7 + 1 + read-only + + + INFIFO_CNT_L1_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 8 + 5 + read-only + + + INFIFO_FULL_L3_CH4 + Tx FIFO full signal for Tx channel 1. + 16 + 1 + read-only + + + INFIFO_EMPTY_L3_CH4 + Tx FIFO empty signal for Tx channel 1. + 17 + 1 + read-only + + + INFIFO_CNT_L3_CH4 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 18 + 2 + read-only + + + + + IN_POP_CH4 + RX CH4 INFIFO pop register + 0x918 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH4 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH4 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_LINK_CONF_CH4 + RX CH4 in_link dscr ctrl register + 0x91C + 0x20 + 0x01100000 + + + INLINK_AUTO_RET_CH4 + Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. + 20 + 1 + read-write + + + INLINK_STOP_CH4 + Set this bit to stop dealing with the inlink descriptors. + 21 + 1 + read-write + + + INLINK_START_CH4 + Set this bit to start dealing with the inlink descriptors. + 22 + 1 + read-write + + + INLINK_RESTART_CH4 + Set this bit to mount a new inlink descriptor. + 23 + 1 + read-write + + + INLINK_PARK_CH4 + 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. + 24 + 1 + read-only + + + + + IN_LINK_ADDR_CH4 + RX CH4 in_link dscr addr register + 0x920 + 0x20 + + + INLINK_ADDR_CH4 + This register stores the first inlink descriptor's address. + 0 + 32 + read-write + + + + + IN_STATE_CH4 + RX CH4 state register + 0x924 + 0x20 + 0x00800000 + + + INLINK_DSCR_ADDR_CH4 + This register stores the current inlink descriptor's address. + 0 + 18 + read-only + + + IN_DSCR_STATE_CH4 + This register stores the current descriptor state machine state. + 18 + 2 + read-only + + + IN_STATE_CH4 + This register stores the current control module state machine state. + 20 + 3 + read-only + + + IN_RESET_AVAIL_CH4 + This register indicate that if the channel reset is safety. + 23 + 1 + read-only + + + + + IN_SUC_EOF_DES_ADDR_CH4 + RX CH4 eof des addr register + 0x928 + 0x20 + + + IN_SUC_EOF_DES_ADDR_CH4 + This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + 0 + 32 + read-only + + + + + IN_ERR_EOF_DES_ADDR_CH4 + RX CH4 err eof des addr register + 0x92C + 0x20 + + + IN_ERR_EOF_DES_ADDR_CH4 + This register stores the address of the inlink descriptor when there are some errors in current receiving data. + 0 + 32 + read-only + + + + + IN_DSCR_CH4 + RX CH4 next dscr addr register + 0x930 + 0x20 + + + INLINK_DSCR_CH4 + The address of the next inlink descriptor address x. + 0 + 32 + read-only + + + + + IN_DSCR_BF0_CH4 + RX CH4 last dscr addr register + 0x934 + 0x20 + + + INLINK_DSCR_BF0_CH4 + The address of the last inlink descriptor's next address x-1. + 0 + 32 + read-only + + + + + IN_DSCR_BF1_CH4 + RX CH4 second-to-last dscr addr register + 0x938 + 0x20 + + + INLINK_DSCR_BF1_CH4 + The address of the second-to-last inlink descriptor's next address x-2. + 0 + 32 + read-only + + + + + IN_ARB_CH4 + RX CH4 arb register + 0x940 + 0x20 + 0x00000051 + + + IN_ARB_TOKEN_NUM_CH4 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + EXTER_IN_ARB_PRIORITY_CH4 + Set the priority of channel + 4 + 2 + read-write + + + INTER_IN_ARB_PRIORITY_CH4 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_ETM_CONF_CH4 + RX CH4 ETM config register + 0x948 + 0x20 + 0x00000004 + + + IN_ETM_EN_CH4 + Set this bit to 1 to enable ETM task function + 0 + 1 + read-write + + + IN_ETM_LOOP_EN_CH4 + when this bit is 1, dscr can be processed after receiving a task + 1 + 1 + read-write + + + IN_DSCR_TASK_MAK_CH4 + ETM dscr_ready maximum cache numbers + 2 + 2 + read-write + + + + + IN_FIFO_CNT_CH4 + rx CH4 fifo cnt register + 0x980 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH4 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH4 + rx CH4 pop data cnt register + 0x984 + 0x20 + 0x00000007 + + + IN_CMDFIFO_POP_DATA_CNT_CH4 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH4 + rx CH4 xaddr register + 0x988 + 0x20 + + + IN_CMDFIFO_XADDR_CH4 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH4 + rx CH4 buf len hb rcv register + 0x98C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH4 + only for debug + 0 + 29 + read-only + + + + + IN_CONF0_CH5 + RX CH5 config0 register + 0xA00 + 0x20 + + + IN_ECC_AES_EN_CH5 + When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned. + 3 + 1 + read-write + + + IN_MEM_BURST_LENGTH_CH5 + Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes + 6 + 3 + read-write + + + IN_PAGE_BOUND_EN_CH5 + Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length + 12 + 1 + read-write + + + IN_RST_CH5 + Write 1 then write 0 to this bit to reset Rx channel + 24 + 1 + read-write + + + IN_CMD_DISABLE_CH5 + Write 1 before reset and write 0 after reset + 25 + 1 + read-write + + + + + IN_CONF1_CH5 + RX CH5 config1 register + 0xA04 + 0x20 + + + BLOCK_START_ADDR_CH5 + RX Channel 5 destination start address + 0 + 32 + read-write + + + + + IN_CONF2_CH5 + RX CH5 config2 register + 0xA08 + 0x20 + 0x3C007800 + + + BLOCK_ROW_LENGTH_12LINE_CH5 + The number of bytes contained in a row block 12line in RX channel 5 + 0 + 16 + read-write + + + BLOCK_ROW_LENGTH_4LINE_CH5 + The number of bytes contained in a row block 4line in RX channel 5 + 16 + 16 + read-write + + + + + IN_CONF3_CH5 + RX CH5 config3 register + 0xA0C + 0x20 + 0x00200100 + + + BLOCK_LENGTH_12LINE_CH5 + The number of bytes contained in a block 12line + 0 + 14 + read-write + + + BLOCK_LENGTH_4LINE_CH5 + The number of bytes contained in a block 4line + 14 + 14 + read-write + + + + + IN_INT_RAW_CH5 + RX CH5 interrupt raw register + 0xA10 + 0x20 + + + IN_DONE_CH5_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + 0 + 1 + read-write + + + IN_SUC_EOF_CH5_INT_RAW + The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + 1 + 1 + read-write + + + INFIFO_OVF_L1_CH5_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + 2 + 1 + read-write + + + INFIFO_UDF_L1_CH5_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 3 + 1 + read-write + + + FETCH_MB_COL_CNT_OVF_CH5_INT_RAW + This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + 4 + 1 + read-write + + + + + IN_INT_ENA_CH5 + RX CH5 interrupt ena register + 0xA14 + 0x20 + + + IN_DONE_CH5_INT_ENA + The interrupt enable bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-write + + + IN_SUC_EOF_CH5_INT_ENA + The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-write + + + INFIFO_OVF_L1_CH5_INT_ENA + The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + 2 + 1 + read-write + + + INFIFO_UDF_L1_CH5_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 3 + 1 + read-write + + + FETCH_MB_COL_CNT_OVF_CH5_INT_ENA + The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + 4 + 1 + read-write + + + + + IN_INT_ST_CH5 + RX CH5 interrupt st register + 0xA18 + 0x20 + + + IN_DONE_CH5_INT_ST + The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + 0 + 1 + read-only + + + IN_SUC_EOF_CH5_INT_ST + The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + read-only + + + INFIFO_OVF_L1_CH5_INT_ST + The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + 2 + 1 + read-only + + + INFIFO_UDF_L1_CH5_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 3 + 1 + read-only + + + FETCH_MB_COL_CNT_OVF_CH5_INT_ST + The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + 4 + 1 + read-only + + + + + IN_INT_CLR_CH5 + RX CH5 interrupt clr register + 0xA1C + 0x20 + + + IN_DONE_CH5_INT_CLR + Set this bit to clear the IN_DONE_CH_INT interrupt. + 0 + 1 + write-only + + + IN_SUC_EOF_CH5_INT_CLR + Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + 1 + 1 + write-only + + + INFIFO_OVF_L1_CH5_INT_CLR + Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + 2 + 1 + write-only + + + INFIFO_UDF_L1_CH5_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 3 + 1 + write-only + + + FETCH_MB_COL_CNT_OVF_CH5_INT_CLR + Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + 4 + 1 + write-only + + + + + INFIFO_STATUS_CH5 + RX CH5 INFIFO status register + 0xA20 + 0x20 + 0x00000002 + + + INFIFO_FULL_L1_CH5 + Tx FIFO full signal for Tx channel 1. + 0 + 1 + read-only + + + INFIFO_EMPTY_L1_CH5 + Tx FIFO empty signal for Tx channel 1. + 1 + 1 + read-only + + + INFIFO_CNT_L1_CH5 + The register stores the byte number of the data in Tx FIFO for Tx channel 1. + 2 + 5 + read-only + + + + + IN_POP_CH5 + RX CH5 INFIFO pop register + 0xA24 + 0x20 + 0x00000400 + + + INFIFO_RDATA_CH5 + This register stores the data popping from DMA Rx FIFO. + 0 + 11 + read-only + + + INFIFO_POP_CH5 + Set this bit to pop data from DMA Rx FIFO. + 11 + 1 + read-write + + + + + IN_STATE_CH5 + RX CH5 state register + 0xA28 + 0x20 + 0x00000008 + + + IN_STATE_CH5 + This register stores the current control module state machine state. + 0 + 3 + read-only + + + IN_RESET_AVAIL_CH5 + This register indicate that if the channel reset is safety. + 3 + 1 + read-only + + + + + IN_ARB_CH5 + RX CH5 arb register + 0xA40 + 0x20 + 0x00000041 + + + IN_ARB_TOKEN_NUM_CH5 + Set the max number of token count of arbiter + 0 + 4 + read-write + + + INTER_IN_ARB_PRIORITY_CH5 + Set the priority of channel + 6 + 3 + read-write + + + + + IN_FIFO_CNT_CH5 + rx CH5 fifo cnt register + 0xA80 + 0x20 + + + IN_CMDFIFO_INFIFO_CNT_CH5 + only for debug + 0 + 10 + read-only + + + + + IN_POP_DATA_CNT_CH5 + rx CH5 pop data cnt register + 0xA84 + 0x20 + 0x000000FF + + + IN_CMDFIFO_POP_DATA_CNT_CH5 + only for debug + 0 + 8 + read-only + + + + + IN_XADDR_CH5 + rx CH5 xaddr register + 0xA88 + 0x20 + + + IN_CMDFIFO_XADDR_CH5 + only for debug + 0 + 32 + read-only + + + + + IN_BUF_HB_RCV_CH5 + rx CH5 buf len hb rcv register + 0xA8C + 0x20 + + + IN_CMDFIFO_BUF_HB_RCV_CH5 + only for debug + 0 + 29 + read-only + + + + + INTER_AXI_ERR + inter memory axi err register + 0xB00 + 0x20 + + + INTER_RID_ERR_CNT + AXI read id err cnt + 0 + 4 + read-only + + + INTER_RRESP_ERR_CNT + AXI read resp err cnt + 4 + 4 + read-only + + + INTER_WRESP_ERR_CNT + AXI write resp err cnt + 8 + 4 + read-only + + + INTER_RD_FIFO_CNT + AXI read cmd fifo remain cmd count + 12 + 3 + read-only + + + INTER_RD_BAK_FIFO_CNT + AXI read backup cmd fifo remain cmd count + 15 + 4 + read-only + + + INTER_WR_FIFO_CNT + AXI write cmd fifo remain cmd count + 19 + 3 + read-only + + + INTER_WR_BAK_FIFO_CNT + AXI write backup cmd fifo remain cmd count + 22 + 4 + read-only + + + + + EXTER_AXI_ERR + exter memory axi err register + 0xB04 + 0x20 + + + EXTER_RID_ERR_CNT + AXI read id err cnt + 0 + 4 + read-only + + + EXTER_RRESP_ERR_CNT + AXI read resp err cnt + 4 + 4 + read-only + + + EXTER_WRESP_ERR_CNT + AXI write resp err cnt + 8 + 4 + read-only + + + EXTER_RD_FIFO_CNT + AXI read cmd fifo remain cmd count + 12 + 3 + read-only + + + EXTER_RD_BAK_FIFO_CNT + AXI read backup cmd fifo remain cmd count + 15 + 4 + read-only + + + EXTER_WR_FIFO_CNT + AXI write cmd fifo remain cmd count + 19 + 3 + read-only + + + EXTER_WR_BAK_FIFO_CNT + AXI write backup cmd fifo remain cmd count + 22 + 4 + read-only + + + + + RST_CONF + axi reset config register + 0xB08 + 0x20 + + + INTER_AXIM_RD_RST + Write 1 then write 0 to this bit to reset axi master read data FIFO. + 0 + 1 + read-write + + + INTER_AXIM_WR_RST + Write 1 then write 0 to this bit to reset axi master write data FIFO. + 1 + 1 + read-write + + + EXTER_AXIM_RD_RST + Write 1 then write 0 to this bit to reset axi master read data FIFO. + 2 + 1 + read-write + + + EXTER_AXIM_WR_RST + Write 1 then write 0 to this bit to reset axi master write data FIFO. + 3 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 4 + 1 + read-write + + + + + INTER_MEM_START_ADDR0 + Start address of inter memory range0 register + 0xB0C + 0x20 + 0x30100000 + + + ACCESS_INTER_MEM_START_ADDR0 + The start address of accessible address space. + 0 + 32 + read-write + + + + + INTER_MEM_END_ADDR0 + end address of inter memory range0 register + 0xB10 + 0x20 + 0x8FFFFFFF + + + ACCESS_INTER_MEM_END_ADDR0 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + INTER_MEM_START_ADDR1 + Start address of inter memory range1 register + 0xB14 + 0x20 + 0x30100000 + + + ACCESS_INTER_MEM_START_ADDR1 + The start address of accessible address space. + 0 + 32 + read-write + + + + + INTER_MEM_END_ADDR1 + end address of inter memory range1 register + 0xB18 + 0x20 + 0x8FFFFFFF + + + ACCESS_INTER_MEM_END_ADDR1 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + EXTER_MEM_START_ADDR0 + Start address of exter memory range0 register + 0xB20 + 0x20 + 0x30100000 + + + ACCESS_EXTER_MEM_START_ADDR0 + The start address of accessible address space. + 0 + 32 + read-write + + + + + EXTER_MEM_END_ADDR0 + end address of exter memory range0 register + 0xB24 + 0x20 + 0x8FFFFFFF + + + ACCESS_EXTER_MEM_END_ADDR0 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + EXTER_MEM_START_ADDR1 + Start address of exter memory range1 register + 0xB28 + 0x20 + 0x30100000 + + + ACCESS_EXTER_MEM_START_ADDR1 + The start address of accessible address space. + 0 + 32 + read-write + + + + + EXTER_MEM_END_ADDR1 + end address of exter memory range1 register + 0xB2C + 0x20 + 0x8FFFFFFF + + + ACCESS_EXTER_MEM_END_ADDR1 + The end address of accessible address space. The access address beyond this range would lead to descriptor error. + 0 + 32 + read-write + + + + + OUT_ARB_CONFIG + reserved + 0xB30 + 0x20 + + + OUT_ARB_TIMEOUT_NUM + Set the max number of timeout count of arbiter + 0 + 16 + read-write + + + OUT_WEIGHT_EN + reserved + 16 + 1 + read-write + + + + + IN_ARB_CONFIG + reserved + 0xB34 + 0x20 + + + IN_ARB_TIMEOUT_NUM + Set the max number of timeout count of arbiter + 0 + 16 + read-write + + + IN_WEIGHT_EN + reserved + 16 + 1 + read-write + + + + + DATE + reserved + 0xB3C + 0x20 + 0x20230403 + + + DATE + register version. + 0 + 32 + read-write + + + + + COUNTER_RST + counter reset register + 0xB50 + 0x20 + + + RX_CH0_EXTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch0 counter. + 0 + 1 + read-write + + + RX_CH1_EXTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch1 counter. + 1 + 1 + read-write + + + RX_CH2_INTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch2 counter. + 2 + 1 + read-write + + + RX_CH5_INTER_COUNTER_RST + Write 1 then write 0 to this bit to reset rx ch5 counter. + 3 + 1 + read-write + + + + + RX_CH0_COUNTER + rx ch0 counter register + 0xB54 + 0x20 + + + RX_CH0_CNT + rx ch0 counter register + 0 + 23 + read-only + + + + + RX_CH1_COUNTER + rx ch1 counter register + 0xB58 + 0x20 + + + RX_CH1_CNT + rx ch1 counter register + 0 + 21 + read-only + + + + + RX_CH2_COUNTER + rx ch2 counter register + 0xB5C + 0x20 + + + RX_CH2_CNT + rx ch2 counter register + 0 + 11 + read-only + + + + + RX_CH5_COUNTER + rx ch5 counter register + 0xB60 + 0x20 + + + RX_CH5_CNT + rx ch5 counter register + 0 + 17 + read-only + + + + + + + HMAC + HMAC (Hash-based Message Authentication Code) Accelerator + HMAC + 0x50095000 + + 0x0 + 0xA4 + registers + + + + SET_START + Process control register 0. + 0x40 + 0x20 + + + SET_START + Start hmac operation. + 0 + 1 + write-only + + + + + SET_PARA_PURPOSE + Configure purpose. + 0x44 + 0x20 + + + PURPOSE_SET + Set hmac parameter purpose. + 0 + 4 + write-only + + + + + SET_PARA_KEY + Configure key. + 0x48 + 0x20 + + + KEY_SET + Set hmac parameter key. + 0 + 3 + write-only + + + + + SET_PARA_FINISH + Finish initial configuration. + 0x4C + 0x20 + + + SET_PARA_END + Finish hmac configuration. + 0 + 1 + write-only + + + + + SET_MESSAGE_ONE + Process control register 1. + 0x50 + 0x20 + + + SET_TEXT_ONE + Call SHA to calculate one message block. + 0 + 1 + write-only + + + + + SET_MESSAGE_ING + Process control register 2. + 0x54 + 0x20 + + + SET_TEXT_ING + Continue typical hmac. + 0 + 1 + write-only + + + + + SET_MESSAGE_END + Process control register 3. + 0x58 + 0x20 + + + SET_TEXT_END + Start hardware padding. + 0 + 1 + write-only + + + + + SET_RESULT_FINISH + Process control register 4. + 0x5C + 0x20 + + + SET_RESULT_END + After read result from upstream, then let hmac back to idle. + 0 + 1 + write-only + + + + + SET_INVALIDATE_JTAG + Invalidate register 0. + 0x60 + 0x20 + + + SET_INVALIDATE_JTAG + Clear result from hmac downstream JTAG. + 0 + 1 + write-only + + + + + SET_INVALIDATE_DS + Invalidate register 1. + 0x64 + 0x20 + + + SET_INVALIDATE_DS + Clear result from hmac downstream DS. + 0 + 1 + write-only + + + + + QUERY_ERROR + Error register. + 0x68 + 0x20 + + + QUERY_CHECK + Hmac configuration state. 0: key are agree with purpose. 1: error + 0 + 1 + read-only + + + + + QUERY_BUSY + Busy register. + 0x6C + 0x20 + + + BUSY_STATE + Hmac state. 1'b0: idle. 1'b1: busy + 0 + 1 + read-only + + + + + 64 + 0x1 + WR_MESSAGE_MEM[%s] + Message block memory. + 0x80 + 0x8 + + + 32 + 0x1 + RD_RESULT_MEM[%s] + Result from upstream. + 0xC0 + 0x8 + + + SET_MESSAGE_PAD + Process control register 5. + 0xF0 + 0x20 + + + SET_TEXT_PAD + Start software padding. + 0 + 1 + write-only + + + + + ONE_BLOCK + Process control register 6. + 0xF4 + 0x20 + + + SET_ONE_BLOCK + Don't have to do padding. + 0 + 1 + write-only + + + + + SOFT_JTAG_CTRL + Jtag register 0. + 0xF8 + 0x20 + + + SOFT_JTAG_CTRL + Turn on JTAG verification. + 0 + 1 + write-only + + + + + WR_JTAG + Jtag register 1. + 0xFC + 0x20 + + + WR_JTAG + 32-bit of key to be compared. + 0 + 32 + write-only + + + + + DATE + Date register. + 0x1FC + 0x20 + 0x20200618 + + + DATE + Hmac date information/ hmac version information. + 0 + 30 + read-write + + + + + + + HP_SYS + High-Power System + HP_SYS + 0x500E5000 + + 0x0 + 0x16C + registers + + + HP_SYS + 110 + + + + VER_DATE + NA + 0x0 + 0x20 + 0x20230519 + + + HP_REG_VER_DATE + NA + 0 + 32 + read-write + + + + + HP_CLK_EN + NA + 0x4 + 0x20 + + + HP_REG_CLK_EN + NA + 0 + 1 + read-write + + + + + HP_CPU_INT_FROM_CPU_0 + NA + 0x10 + 0x20 + + + HP_CPU_INT_FROM_CPU_0 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + HP_CPU_INT_FROM_CPU_1 + NA + 0x14 + 0x20 + + + HP_CPU_INT_FROM_CPU_1 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + HP_CPU_INT_FROM_CPU_2 + NA + 0x18 + 0x20 + + + HP_CPU_INT_FROM_CPU_2 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + HP_CPU_INT_FROM_CPU_3 + NA + 0x1C + 0x20 + + + HP_CPU_INT_FROM_CPU_3 + set 1 will triger a interrupt + 0 + 1 + read-write + + + + + HP_CACHE_CLK_CONFIG + NA + 0x20 + 0x20 + 0x00000033 + + + HP_REG_L2_CACHE_CLK_ON + l2 cahce clk enable + 0 + 1 + read-write + + + HP_REG_L1_D_CACHE_CLK_ON + l1 dcahce clk enable + 1 + 1 + read-write + + + HP_REG_L1_I1_CACHE_CLK_ON + l1 icahce1 clk enable + 4 + 1 + read-write + + + HP_REG_L1_I0_CACHE_CLK_ON + l1 icahce0 clk enable + 5 + 1 + read-write + + + + + HP_CACHE_RESET_CONFIG + NA + 0x24 + 0x20 + + + HP_REG_L1_D_CACHE_RESET + set 1 to reset l1 dcahce + 1 + 1 + read-write + + + HP_REG_L1_I1_CACHE_RESET + set 1 to reset l1 icahce1 + 4 + 1 + read-write + + + HP_REG_L1_I0_CACHE_RESET + set 1 to reset l1 icahce0 + 5 + 1 + read-write + + + + + DMA_ADDR_CTRL + NA + 0x2C + 0x20 + + + HP_REG_SYS_DMA_ADDR_SEL + 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx + 0 + 1 + read-write + + + + + HP_TCM_RAM_WRR_CONFIG + NA + 0x34 + 0x20 + 0x826ED93F + + + HP_REG_TCM_RAM_IBUS0_WT + weight value of ibus0 + 0 + 3 + read-write + + + HP_REG_TCM_RAM_IBUS1_WT + weight value of ibus1 + 3 + 3 + read-write + + + HP_REG_TCM_RAM_IBUS2_WT + weight value of ibus2 + 6 + 3 + read-write + + + HP_REG_TCM_RAM_IBUS3_WT + weight value of ibus3 + 9 + 3 + read-write + + + HP_REG_TCM_RAM_DBUS0_WT + weight value of dbus0 + 12 + 3 + read-write + + + HP_REG_TCM_RAM_DBUS1_WT + weight value of dbus1 + 15 + 3 + read-write + + + HP_REG_TCM_RAM_DBUS2_WT + weight value of dbus2 + 18 + 3 + read-write + + + HP_REG_TCM_RAM_DBUS3_WT + weight value of dbus3 + 21 + 3 + read-write + + + HP_REG_TCM_RAM_DMA_WT + weight value of dma + 24 + 3 + read-write + + + HP_REG_TCM_RAM_WRR_HIGH + enable weighted round robin arbitration + 31 + 1 + read-write + + + + + HP_TCM_SW_PARITY_BWE_MASK + NA + 0x38 + 0x20 + + + HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL + Set 1 to mask tcm bwe parity code bit + 0 + 1 + read-write + + + + + HP_TCM_RAM_PWR_CTRL0 + NA + 0x3C + 0x20 + + + HP_REG_HP_TCM_CLK_FORCE_ON + hp_tcm clk gatig force on + 0 + 1 + read-write + + + + + HP_L2_ROM_PWR_CTRL0 + NA + 0x40 + 0x20 + + + HP_REG_L2_ROM_CLK_FORCE_ON + l2_rom clk gating force on + 0 + 1 + read-write + + + + + HP_PROBEA_CTRL + NA + 0x50 + 0x20 + + + HP_REG_PROBE_A_MOD_SEL + Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in a mode + 0 + 16 + read-write + + + HP_REG_PROBE_A_TOP_SEL + Tihs field is used to selec module's probe_out[31:0] as probe out in a mode + 16 + 8 + read-write + + + HP_REG_PROBE_L_SEL + Tihs field is used to selec probe_out[31:16] + 24 + 2 + read-write + + + HP_REG_PROBE_H_SEL + Tihs field is used to selec probe_out[31:16] + 26 + 2 + read-write + + + HP_REG_PROBE_GLOBAL_EN + Set this bit to enable global debug probe in hp system. + 28 + 1 + read-write + + + + + HP_PROBEB_CTRL + NA + 0x54 + 0x20 + + + HP_REG_PROBE_B_MOD_SEL + Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in b mode. + 0 + 16 + read-write + + + HP_REG_PROBE_B_TOP_SEL + Tihs field is used to select module's probe_out[31:0] as probe_out in b mode + 16 + 8 + read-write + + + HP_REG_PROBE_B_EN + Set this bit to enable b mode for debug probe. 1: b mode, 0: a mode. + 24 + 1 + read-write + + + + + HP_PROBE_OUT + NA + 0x5C + 0x20 + + + HP_REG_PROBE_TOP_OUT + NA + 0 + 32 + read-only + + + + + HP_L2_MEM_RAM_PWR_CTRL0 + NA + 0x60 + 0x20 + + + HP_REG_L2_MEM_CLK_FORCE_ON + l2ram clk_gating force on + 0 + 1 + read-write + + + + + HP_CPU_CORESTALLED_ST + NA + 0x64 + 0x20 + + + HP_REG_CORE0_CORESTALLED_ST + hp core0 corestalled status + 0 + 1 + read-only + + + HP_REG_CORE1_CORESTALLED_ST + hp core1 corestalled status + 1 + 1 + read-only + + + + + HP_CRYPTO_CTRL + NA + 0x70 + 0x20 + + + HP_REG_ENABLE_SPI_MANUAL_ENCRYPT + NA + 0 + 1 + read-write + + + HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT + NA + 1 + 1 + read-write + + + HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT + NA + 2 + 1 + read-write + + + HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT + NA + 3 + 1 + read-write + + + + + HP_GPIO_O_HOLD_CTRL0 + NA + 0x74 + 0x20 + + + HP_REG_GPIO_0_HOLD_LOW + hold control for gpio47~16 + 0 + 32 + read-write + + + + + HP_GPIO_O_HOLD_CTRL1 + NA + 0x78 + 0x20 + + + HP_REG_GPIO_0_HOLD_HIGH + hold control for gpio56~48 + 0 + 9 + read-write + + + + + RDN_ECO_CS + NA + 0x7C + 0x20 + + + HP_REG_HP_SYS_RDN_ECO_EN + NA + 0 + 1 + read-write + + + HP_REG_HP_SYS_RDN_ECO_RESULT + NA + 1 + 1 + read-only + + + + + HP_CACHE_APB_POSTW_EN + NA + 0x80 + 0x20 + + + HP_REG_CACHE_APB_POSTW_EN + cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register + 0 + 1 + read-write + + + + + HP_L2_MEM_SUBSIZE + NA + 0x84 + 0x20 + + + HP_REG_L2_MEM_SUB_BLKSIZE + l2mem sub block size 00=>32 01=>64 10=>128 11=>256 + 0 + 2 + read-write + + + + + HP_L2_MEM_INT_RAW + NA + 0x9C + 0x20 + + + HP_REG_L2_MEM_ECC_ERR_INT_RAW + intr triggered when two bit error detected and corrected from ecc + 0 + 1 + read-write + + + HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW + intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode + 1 + 1 + read-write + + + HP_REG_L2_MEM_ERR_RESP_INT_RAW + intr triggered when err response occurs + 2 + 1 + read-write + + + + + HP_L2_MEM_INT_ST + NA + 0xA0 + 0x20 + + + HP_REG_L2_MEM_ECC_ERR_INT_ST + NA + 0 + 1 + read-only + + + HP_REG_L2_MEM_EXCEED_ADDR_INT_ST + NA + 1 + 1 + read-only + + + HP_REG_L2_MEM_ERR_RESP_INT_ST + NA + 2 + 1 + read-only + + + + + HP_L2_MEM_INT_ENA + NA + 0xA4 + 0x20 + + + HP_REG_L2_MEM_ECC_ERR_INT_ENA + NA + 0 + 1 + read-write + + + HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA + NA + 1 + 1 + read-write + + + HP_REG_L2_MEM_ERR_RESP_INT_ENA + NA + 2 + 1 + read-write + + + + + HP_L2_MEM_INT_CLR + NA + 0xA8 + 0x20 + + + HP_REG_L2_MEM_ECC_ERR_INT_CLR + NA + 0 + 1 + write-only + + + HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR + NA + 1 + 1 + write-only + + + HP_REG_L2_MEM_ERR_RESP_INT_CLR + NA + 2 + 1 + write-only + + + + + HP_L2_MEM_L2_RAM_ECC + NA + 0xAC + 0x20 + + + HP_REG_L2_RAM_UNIT0_ECC_EN + NA + 0 + 1 + read-write + + + HP_REG_L2_RAM_UNIT1_ECC_EN + NA + 1 + 1 + read-write + + + HP_REG_L2_RAM_UNIT2_ECC_EN + NA + 2 + 1 + read-write + + + HP_REG_L2_RAM_UNIT3_ECC_EN + NA + 3 + 1 + read-write + + + HP_REG_L2_RAM_UNIT4_ECC_EN + NA + 4 + 1 + read-write + + + HP_REG_L2_RAM_UNIT5_ECC_EN + NA + 5 + 1 + read-write + + + + + HP_L2_MEM_INT_RECORD0 + NA + 0xB0 + 0x20 + + + HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR + NA + 0 + 21 + read-only + + + HP_REG_L2_MEM_EXCEED_ADDR_INT_WE + NA + 21 + 1 + read-only + + + HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER + NA + 22 + 3 + read-only + + + + + HP_L2_MEM_INT_RECORD1 + NA + 0xB4 + 0x20 + + + HP_REG_L2_MEM_ECC_ERR_INT_ADDR + NA + 0 + 15 + read-only + + + HP_REG_L2_MEM_ECC_ONE_BIT_ERR + NA + 15 + 1 + read-only + + + HP_REG_L2_MEM_ECC_TWO_BIT_ERR + NA + 16 + 1 + read-only + + + HP_REG_L2_MEM_ECC_ERR_BIT + NA + 17 + 9 + read-only + + + HP_REG_L2_CACHE_ERR_BANK + NA + 26 + 1 + read-only + + + + + HP_L2_MEM_L2_CACHE_ECC + NA + 0xC4 + 0x20 + + + HP_REG_L2_CACHE_ECC_EN + NA + 0 + 1 + read-write + + + + + HP_L1CACHE_BUS0_ID + NA + 0xC8 + 0x20 + + + HP_REG_L1_CACHE_BUS0_ID + NA + 0 + 4 + read-write + + + + + HP_L1CACHE_BUS1_ID + NA + 0xCC + 0x20 + + + HP_REG_L1_CACHE_BUS1_ID + NA + 0 + 4 + read-write + + + + + HP_L2_MEM_RDN_ECO_CS + NA + 0xD8 + 0x20 + + + HP_REG_L2_MEM_RDN_ECO_EN + NA + 0 + 1 + read-write + + + HP_REG_L2_MEM_RDN_ECO_RESULT + NA + 1 + 1 + read-only + + + + + HP_L2_MEM_RDN_ECO_LOW + NA + 0xDC + 0x20 + + + HP_REG_L2_MEM_RDN_ECO_LOW + NA + 0 + 32 + read-write + + + + + HP_L2_MEM_RDN_ECO_HIGH + NA + 0xE0 + 0x20 + 0xFFFFFFFF + + + HP_REG_L2_MEM_RDN_ECO_HIGH + NA + 0 + 32 + read-write + + + + + HP_TCM_RDN_ECO_CS + NA + 0xE4 + 0x20 + + + HP_REG_HP_TCM_RDN_ECO_EN + NA + 0 + 1 + read-write + + + HP_REG_HP_TCM_RDN_ECO_RESULT + NA + 1 + 1 + read-only + + + + + HP_TCM_RDN_ECO_LOW + NA + 0xE8 + 0x20 + + + HP_REG_HP_TCM_RDN_ECO_LOW + NA + 0 + 32 + read-write + + + + + HP_TCM_RDN_ECO_HIGH + NA + 0xEC + 0x20 + 0xFFFFFFFF + + + HP_REG_HP_TCM_RDN_ECO_HIGH + NA + 0 + 32 + read-write + + + + + HP_GPIO_DED_HOLD_CTRL + NA + 0xF0 + 0x20 + + + HP_REG_GPIO_DED_HOLD + hold control for gpio63~56 + 0 + 26 + read-write + + + + + HP_L2_MEM_SW_ECC_BWE_MASK + NA + 0xF4 + 0x20 + + + HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL + Set 1 to mask bwe hamming code bit + 0 + 1 + read-write + + + + + HP_USB20OTG_MEM_CTRL + NA + 0xF8 + 0x20 + + + HP_REG_USB20_MEM_CLK_FORCE_ON + NA + 0 + 1 + read-write + + + + + HP_TCM_INT_RAW + need_des + 0xFC + 0x20 + + + HP_TCM_PARITY_ERR_INT_RAW + need_des + 31 + 1 + read-write + + + + + HP_TCM_INT_ST + need_des + 0x100 + 0x20 + + + HP_TCM_PARITY_ERR_INT_ST + need_des + 31 + 1 + read-only + + + + + HP_TCM_INT_ENA + need_des + 0x104 + 0x20 + + + HP_TCM_PARITY_ERR_INT_ENA + need_des + 31 + 1 + read-write + + + + + HP_TCM_INT_CLR + need_des + 0x108 + 0x20 + + + HP_TCM_PARITY_ERR_INT_CLR + need_des + 31 + 1 + write-only + + + + + HP_TCM_PARITY_INT_RECORD + need_des + 0x10C + 0x20 + + + HP_TCM_PARITY_ERR_INT_ADDR + hp tcm_parity_err_addr + 0 + 13 + read-only + + + + + HP_L1_CACHE_PWR_CTRL + NA + 0x110 + 0x20 + + + HP_REG_L1_CACHE_MEM_FO + need_des + 0 + 6 + read-write + + + + + HP_L2_CACHE_PWR_CTRL + NA + 0x114 + 0x20 + + + HP_REG_L2_CACHE_MEM_FO + need_des + 0 + 2 + read-write + + + + + HP_CPU_WAITI_CONF + CPU_WAITI configuration register + 0x118 + 0x20 + 0x00000001 + + + HP_CPU_WAIT_MODE_FORCE_ON + Set 1 to force cpu_waiti_clk enable. + 0 + 1 + read-write + + + HP_CPU_WAITI_DELAY_NUM + This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close + 1 + 4 + read-write + + + + + CORE_DEBUG_RUNSTALL_CONF + Core Debug runstall configure register + 0x11C + 0x20 + + + CORE_DEBUG_RUNSTALL_ENABLE + Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + 0 + 1 + read-write + + + + + HP_CORE_AHB_TIMEOUT + need_des + 0x120 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable hp core0&1 ahb timeout handle + 0 + 1 + read-write + + + THRES + This field used to set hp core0&1 ahb bus timeout threshold + 1 + 16 + read-write + + + + + HP_CORE_IBUS_TIMEOUT + need_des + 0x124 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable hp core0&1 ibus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set hp core0&1 ibus timeout threshold + 1 + 16 + read-write + + + + + HP_CORE_DBUS_TIMEOUT + need_des + 0x128 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable hp core0&1 dbus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set hp core0&1 dbus timeout threshold + 1 + 16 + read-write + + + + + HP_ICM_CPU_H2X_CFG + need_des + 0x138 + 0x20 + 0x00000003 + + + HP_CPU_ICM_H2X_POST_WR_EN + need_des + 0 + 1 + read-write + + + HP_CPU_ICM_H2X_CUT_THROUGH_EN + need_des + 1 + 1 + read-write + + + HP_CPU_ICM_H2X_BRIDGE_BUSY + need_des + 2 + 1 + read-only + + + + + HP_PERI1_APB_POSTW_EN + NA + 0x13C + 0x20 + + + HP_PERI1_APB_POSTW_EN + hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register + 0 + 1 + read-write + + + + + HP_BITSCRAMBLER_PERI_SEL + Bitscrambler Peri Sel + 0x140 + 0x20 + 0x000000FF + + + HP_BITSCRAMBLER_PERI_RX_SEL + Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none + 0 + 4 + read-write + + + HP_BITSCRAMBLER_PERI_TX_SEL + Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none + 4 + 4 + read-write + + + + + APB_SYNC_POSTW_EN + N/A + 0x144 + 0x20 + + + GMAC_APB_POSTW_EN + N/A + 0 + 1 + read-write + + + DSI_HOST_APB_POSTW_EN + N/A + 1 + 1 + read-write + + + CSI_HOST_APB_SYNC_POSTW_EN + N/A + 2 + 1 + read-write + + + CSI_HOST_APB_ASYNC_POSTW_EN + N/A + 3 + 1 + read-write + + + + + GDMA_CTRL + N/A + 0x148 + 0x20 + + + DEBUG_CH_NUM + N/A + 0 + 2 + read-write + + + + + GMAC_CTRL0 + N/A + 0x14C + 0x20 + + + PTP_PPS + N/A + 0 + 1 + read-only + + + SBD_FLOWCTRL + N/A + 1 + 1 + read-write + + + PHY_INTF_SEL + N/A + 2 + 3 + read-write + + + GMAC_MEM_CLK_FORCE_ON + N/A + 5 + 1 + read-write + + + GMAC_RST_CLK_TX_N + N/A + 6 + 1 + read-only + + + GMAC_RST_CLK_RX_N + N/A + 7 + 1 + read-only + + + + + GMAC_CTRL1 + N/A + 0x150 + 0x20 + + + PTP_TIMESTAMP_L + N/A + 0 + 32 + read-only + + + + + GMAC_CTRL2 + N/A + 0x154 + 0x20 + + + PTP_TIMESTAMP_H + N/A + 0 + 32 + read-only + + + + + VPU_CTRL + N/A + 0x158 + 0x20 + + + PPA_LSLP_MEM_PD + N/A + 0 + 1 + read-write + + + JPEG_SDSLP_MEM_PD + N/A + 1 + 1 + read-write + + + JPEG_LSLP_MEM_PD + N/A + 2 + 1 + read-write + + + JPEG_DSLP_MEM_PD + N/A + 3 + 1 + read-write + + + DMA2D_LSLP_MEM_PD + N/A + 4 + 1 + read-write + + + + + USBOTG20_CTRL + N/A + 0x15C + 0x20 + 0x00822640 + + + OTG_PHY_TEST_DONE + N/A + 0 + 1 + read-only + + + USB_MEM_AUX_CTRL + N/A + 1 + 14 + read-write + + + PHY_SUSPENDM + N/A + 15 + 1 + read-write + + + PHY_SUSPEND_FORCE_EN + N/A + 16 + 1 + read-write + + + PHY_RSTN + N/A + 17 + 1 + read-write + + + PHY_RESET_FORCE_EN + N/A + 18 + 1 + read-write + + + PHY_PLL_FORCE_EN + N/A + 19 + 1 + read-write + + + PHY_PLL_EN + N/A + 20 + 1 + read-write + + + OTG_SUSPENDM + N/A + 21 + 1 + read-write + + + OTG_PHY_TXBITSTUFF_EN + N/A + 22 + 1 + read-write + + + OTG_PHY_REFCLK_MODE + N/A + 23 + 1 + read-write + + + OTG_PHY_BISTEN + N/A + 24 + 1 + read-write + + + + + HP_TCM_ERR_RESP_CTRL + need_des + 0x160 + 0x20 + + + HP_TCM_ERR_RESP_EN + Set 1 to turn on tcm error response + 0 + 1 + read-write + + + + + HP_L2_MEM_REFRESH + NA + 0x164 + 0x20 + 0x00000040 + + + HP_REG_L2_MEM_UNIT0_REFERSH_EN + NA + 0 + 1 + read-write + + + HP_REG_L2_MEM_UNIT1_REFERSH_EN + NA + 1 + 1 + read-write + + + HP_REG_L2_MEM_UNIT2_REFERSH_EN + NA + 2 + 1 + read-write + + + HP_REG_L2_MEM_UNIT3_REFERSH_EN + NA + 3 + 1 + read-write + + + HP_REG_L2_MEM_UNIT4_REFERSH_EN + NA + 4 + 1 + read-write + + + HP_REG_L2_MEM_UNIT5_REFERSH_EN + NA + 5 + 1 + read-write + + + HP_REG_L2_MEM_REFERSH_CNT_RESET + Set 1 to reset l2mem_refresh_cnt + 6 + 1 + read-write + + + HP_REG_L2_MEM_UNIT0_REFRESH_DONE + NA + 7 + 1 + read-only + + + HP_REG_L2_MEM_UNIT1_REFRESH_DONE + NA + 8 + 1 + read-only + + + HP_REG_L2_MEM_UNIT2_REFRESH_DONE + NA + 9 + 1 + read-only + + + HP_REG_L2_MEM_UNIT3_REFRESH_DONE + NA + 10 + 1 + read-only + + + HP_REG_L2_MEM_UNIT4_REFRESH_DONE + NA + 11 + 1 + read-only + + + HP_REG_L2_MEM_UNIT5_REFRESH_DONE + NA + 12 + 1 + read-only + + + + + HP_TCM_INIT + NA + 0x168 + 0x20 + 0x00000002 + + + HP_REG_TCM_INIT_EN + NA + 0 + 1 + read-write + + + HP_REG_TCM_INIT_CNT_RESET + Set 1 to reset tcm init cnt + 1 + 1 + read-write + + + HP_REG_TCM_INIT_DONE + NA + 2 + 1 + read-only + + + + + HP_TCM_PARITY_CHECK_CTRL + need_des + 0x16C + 0x20 + + + HP_TCM_PARITY_CHECK_EN + Set 1 to turn on tcm parity check + 0 + 1 + read-write + + + + + HP_DESIGN_FOR_VERIFICATION0 + need_des + 0x170 + 0x20 + + + HP_DFV0 + register for DV + 0 + 32 + read-write + + + + + HP_DESIGN_FOR_VERIFICATION1 + need_des + 0x174 + 0x20 + + + HP_DFV1 + register for DV + 0 + 32 + read-write + + + + + HP_PSRAM_FLASH_ADDR_INTERCHANGE + need_des + 0x180 + 0x20 + + + CPU + Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache + 0 + 1 + read-write + + + DMA + Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb + 1 + 1 + read-write + + + + + HP_AHB2AXI_BRESP_ERR_INT_RAW + NA + 0x188 + 0x20 + + + HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW + the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi. + 0 + 1 + read-write + + + + + HP_AHB2AXI_BRESP_ERR_INT_ST + need_des + 0x18C + 0x20 + + + HP_CPU_ICM_H2X_BRESP_ERR_INT_ST + the masked interrupt status of cpu_icm_h2x_bresp_err + 31 + 1 + read-only + + + + + HP_AHB2AXI_BRESP_ERR_INT_ENA + need_des + 0x190 + 0x20 + + + HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA + Write 1 to enable cpu_icm_h2x_bresp_err int + 31 + 1 + read-write + + + + + HP_AHB2AXI_BRESP_ERR_INT_CLR + need_des + 0x194 + 0x20 + + + HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR + Write 1 to clear cpu_icm_h2x_bresp_err int + 31 + 1 + write-only + + + + + HP_L2_MEM_ERR_RESP_CTRL + need_des + 0x198 + 0x20 + + + HP_L2_MEM_ERR_RESP_EN + Set 1 to turn on l2mem error response + 0 + 1 + read-write + + + + + HP_L2_MEM_AHB_BUFFER_CTRL + need_des + 0x19C + 0x20 + + + HP_L2_MEM_AHB_WRBUFFER_EN + Set 1 to turn on l2mem ahb wr buffer + 0 + 1 + read-write + + + HP_L2_MEM_AHB_RDBUFFER_EN + Set 1 to turn on l2mem ahb rd buffer + 1 + 1 + read-write + + + + + HP_CORE_DMACTIVE_LPCORE + need_des + 0x1A0 + 0x20 + + + HP_CORE_DMACTIVE_LPCORE + hp core dmactive_lpcore value + 0 + 1 + read-only + + + + + HP_CORE_ERR_RESP_DIS + need_des + 0x1A4 + 0x20 + + + HP_CORE_ERR_RESP_DIS + Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp. + 0 + 3 + read-write + + + + + HP_CORE_TIMEOUT_INT_RAW + Hp core bus timeout interrupt raw register + 0x1A8 + 0x20 + + + HP_CORE0_AHB_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 ahb timeout + 0 + 1 + read-write + + + HP_CORE1_AHB_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 ahb timeout + 1 + 1 + read-write + + + HP_CORE0_IBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 ibus timeout + 2 + 1 + read-write + + + HP_CORE1_IBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 ibus timeout + 3 + 1 + read-write + + + HP_CORE0_DBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core0 dbus timeout + 4 + 1 + read-write + + + HP_CORE1_DBUS_TIMEOUT_INT_RAW + the raw interrupt status of hp core1 dbus timeout + 5 + 1 + read-write + + + + + HP_CORE_TIMEOUT_INT_ST + masked interrupt register + 0x1AC + 0x20 + + + HP_CORE0_AHB_TIMEOUT_INT_ST + the masked interrupt status of hp core0 ahb timeout + 0 + 1 + read-only + + + HP_CORE1_AHB_TIMEOUT_INT_ST + the masked interrupt status of hp core1 ahb timeout + 1 + 1 + read-only + + + HP_CORE0_IBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core0 ibus timeout + 2 + 1 + read-only + + + HP_CORE1_IBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core1 ibus timeout + 3 + 1 + read-only + + + HP_CORE0_DBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core0 dbus timeout + 4 + 1 + read-only + + + HP_CORE1_DBUS_TIMEOUT_INT_ST + the masked interrupt status of hp core1 dbus timeout + 5 + 1 + read-only + + + + + HP_CORE_TIMEOUT_INT_ENA + masked interrupt register + 0x1B0 + 0x20 + + + HP_CORE0_AHB_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_ahb_timeout int + 0 + 1 + read-write + + + HP_CORE1_AHB_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_ahb_timeout int + 1 + 1 + read-write + + + HP_CORE0_IBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_ibus_timeout int + 2 + 1 + read-write + + + HP_CORE1_IBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_ibus_timeout int + 3 + 1 + read-write + + + HP_CORE0_DBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core0_dbus_timeout int + 4 + 1 + read-write + + + HP_CORE1_DBUS_TIMEOUT_INT_ENA + Write 1 to enable hp_core1_dbus_timeout int + 5 + 1 + read-write + + + + + HP_CORE_TIMEOUT_INT_CLR + interrupt clear register + 0x1B4 + 0x20 + + + HP_CORE0_AHB_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_ahb_timeout int + 0 + 1 + write-only + + + HP_CORE1_AHB_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_ahb_timeout int + 1 + 1 + write-only + + + HP_CORE0_IBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_ibus_timeout int + 2 + 1 + write-only + + + HP_CORE1_IBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_ibus_timeout int + 3 + 1 + write-only + + + HP_CORE0_DBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core0_dbus_timeout int + 4 + 1 + write-only + + + HP_CORE1_DBUS_TIMEOUT_INT_CLR + Write 1 to clear hp_core1_dbus_timeout int + 5 + 1 + write-only + + + + + HP_GPIO_O_HYS_CTRL0 + NA + 0x1C0 + 0x20 + + + HP_REG_GPIO_0_HYS_LOW + hys control for gpio47~16 + 0 + 32 + read-write + + + + + HP_GPIO_O_HYS_CTRL1 + NA + 0x1C4 + 0x20 + + + HP_REG_GPIO_0_HYS_HIGH + hys control for gpio56~48 + 0 + 9 + read-write + + + + + HP_RSA_PD_CTRL + rsa pd ctrl register + 0x1D0 + 0x20 + 0x00000002 + + + HP_RSA_MEM_FORCE_PD + Set this bit to power down rsa internal memory. + 0 + 1 + read-write + + + HP_RSA_MEM_FORCE_PU + Set this bit to force power up rsa internal memory + 1 + 1 + read-write + + + HP_RSA_MEM_PD + Set this bit to force power down rsa internal memory. + 2 + 1 + read-write + + + + + HP_ECC_PD_CTRL + ecc pd ctrl register + 0x1D4 + 0x20 + 0x00000002 + + + HP_ECC_MEM_FORCE_PD + Set this bit to power down ecc internal memory. + 0 + 1 + read-write + + + HP_ECC_MEM_FORCE_PU + Set this bit to force power up ecc internal memory + 1 + 1 + read-write + + + HP_ECC_MEM_PD + Set this bit to force power down ecc internal memory. + 2 + 1 + read-write + + + + + HP_RNG_CFG + rng cfg register + 0x1D8 + 0x20 + + + HP_RNG_SAMPLE_ENABLE + enable rng sample chain + 0 + 1 + read-write + + + HP_RNG_CHAIN_CLK_DIV_NUM + chain clk div num to pad for debug + 16 + 8 + read-write + + + HP_RNG_SAMPLE_CNT + debug rng sample cnt + 24 + 8 + read-only + + + + + HP_UART_PD_CTRL + ecc pd ctrl register + 0x1DC + 0x20 + 0x00000002 + + + HP_UART_MEM_FORCE_PD + Set this bit to power down hp uart internal memory. + 0 + 1 + read-write + + + HP_UART_MEM_FORCE_PU + Set this bit to force power up hp uart internal memory + 1 + 1 + read-write + + + + + HP_PERI_MEM_CLK_FORCE_ON + hp peri mem clk force on regpster + 0x1E0 + 0x20 + + + HP_RMT_MEM_CLK_FORCE_ON + Set this bit to force on mem clk in rmt + 0 + 1 + read-write + + + HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON + Set this bit to force on tx mem clk in bitscrambler + 1 + 1 + read-write + + + HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON + Set this bit to force on rx mem clk in bitscrambler + 2 + 1 + read-write + + + HP_GDMA_MEM_CLK_FORCE_ON + Set this bit to force on mem clk in gdma + 3 + 1 + read-write + + + + + + + HP_SYS_CLKRST + HP_SYS_CLKRST Peripheral + HP_SYS_CLKRST + 0x500E6000 + + 0x0 + 0xF0 + registers + + + + CLK_EN0 + Reserved + 0x0 + 0x20 + 0x00000001 + + + REG_CLK_EN + Reserved + 0 + 1 + read-write + + + + + ROOT_CLK_CTRL0 + Reserved + 0x4 + 0x20 + + + REG_CPUICM_DELAY_NUM + Reserved + 0 + 4 + read-write + + + REG_SOC_CLK_DIV_UPDATE + Reserved + 4 + 1 + write-only + + + REG_CPU_CLK_DIV_NUM + Reserved + 5 + 8 + read-write + + + REG_CPU_CLK_DIV_NUMERATOR + Reserved + 13 + 8 + read-write + + + REG_CPU_CLK_DIV_DENOMINATOR + Reserved + 21 + 8 + read-write + + + + + ROOT_CLK_CTRL1 + Reserved + 0x8 + 0x20 + 0x00000001 + + + REG_MEM_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_MEM_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_MEM_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_SYS_CLK_DIV_NUM + Reserved + 24 + 8 + read-write + + + + + ROOT_CLK_CTRL2 + Reserved + 0xC + 0x20 + 0x00010000 + + + REG_SYS_CLK_DIV_NUMERATOR + Reserved + 0 + 8 + read-write + + + REG_SYS_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 + read-write + + + REG_APB_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_APB_CLK_DIV_NUMERATOR + Reserved + 24 + 8 + read-write + + + + + ROOT_CLK_CTRL3 + Reserved + 0x10 + 0x20 + + + REG_APB_CLK_DIV_DENOMINATOR + Reserved + 0 + 8 + read-write + + + + + SOC_CLK_CTRL0 + Reserved + 0x14 + 0x20 + 0xE6DF97AF + + + REG_CORE0_CLIC_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_CORE1_CLIC_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_MISC_CPU_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_CORE0_CPU_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_CORE1_CPU_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_TCM_CPU_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_BUSMON_CPU_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_L1CACHE_CPU_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_L1CACHE_D_CPU_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_L1CACHE_I0_CPU_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_L1CACHE_I1_CPU_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_TRACE_CPU_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_ICM_CPU_CLK_EN + Reserved + 12 + 1 + read-write + + + REG_GDMA_CPU_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_VPU_CPU_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_L1CACHE_MEM_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_L1CACHE_D_MEM_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_L1CACHE_I0_MEM_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_L1CACHE_I1_MEM_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_L2CACHE_MEM_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_L2MEM_MEM_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_L2MEMMON_MEM_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_ICM_MEM_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_MISC_SYS_CLK_EN + Reserved + 23 + 1 + read-write + + + REG_TRACE_SYS_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_L2CACHE_SYS_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_L2MEM_SYS_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_L2MEMMON_SYS_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_TCMMON_SYS_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_ICM_SYS_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_FLASH_SYS_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_PSRAM_SYS_CLK_EN + Reserved + 31 + 1 + read-write + + + + + SOC_CLK_CTRL1 + Reserved + 0x18 + 0x20 + 0x7C7F801F + + + REG_GPSPI2_SYS_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_GPSPI3_SYS_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_REGDMA_SYS_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_AHB_PDMA_SYS_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_AXI_PDMA_SYS_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_GDMA_SYS_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_DMA2D_SYS_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_VPU_SYS_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_JPEG_SYS_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_PPA_SYS_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_CSI_BRG_SYS_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_CSI_HOST_SYS_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_DSI_SYS_CLK_EN + Reserved + 12 + 1 + read-write + + + REG_EMAC_SYS_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_SDMMC_SYS_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_USB_OTG11_SYS_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_USB_OTG20_SYS_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_UHCI_SYS_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_UART0_SYS_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_UART1_SYS_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_UART2_SYS_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_UART3_SYS_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_UART4_SYS_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_PARLIO_SYS_CLK_EN + Reserved + 23 + 1 + read-write + + + REG_ETM_SYS_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_PVT_SYS_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_CRYPTO_SYS_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_KEY_MANAGER_SYS_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_BITSRAMBLER_SYS_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_BITSRAMBLER_RX_SYS_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_BITSRAMBLER_TX_SYS_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_H264_SYS_CLK_EN + Reserved + 31 + 1 + read-write + + + + + SOC_CLK_CTRL2 + Reserved + 0x1C + 0x20 + 0x20F80FDE + + + REG_RMT_SYS_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_HP_CLKRST_APB_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_SYSREG_APB_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_ICM_APB_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_INTRMTX_APB_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_ADC_APB_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_UHCI_APB_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_UART0_APB_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_UART1_APB_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_UART2_APB_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_UART3_APB_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_UART4_APB_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_I2C0_APB_CLK_EN + Reserved + 12 + 1 + read-write + + + REG_I2C1_APB_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_I2S0_APB_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_I2S1_APB_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_I2S2_APB_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_I3C_MST_APB_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_I3C_SLV_APB_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_GPSPI2_APB_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_GPSPI3_APB_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_TIMERGRP0_APB_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_TIMERGRP1_APB_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_SYSTIMER_APB_CLK_EN + Reserved + 23 + 1 + read-write + + + REG_TWAI0_APB_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_TWAI1_APB_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TWAI2_APB_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_MCPWM0_APB_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_MCPWM1_APB_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_USB_DEVICE_APB_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_PCNT_APB_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_PARLIO_APB_CLK_EN + Reserved + 31 + 1 + read-write + + + + + SOC_CLK_CTRL3 + Reserved + 0x20 + 0x20 + 0x00000008 + + + REG_LEDC_APB_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_LCDCAM_APB_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_ETM_APB_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_IOMUX_APB_CLK_EN + Reserved + 3 + 1 + read-write + + + + + REF_CLK_CTRL0 + Reserved + 0x24 + 0x20 + 0x02011309 + + + REG_REF_50M_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_REF_25M_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_REF_240M_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_REF_160M_CLK_DIV_NUM + Reserved + 24 + 8 + read-write + + + + + REF_CLK_CTRL1 + Reserved + 0x28 + 0x20 + 0x58170503 + + + REG_REF_120M_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_REF_80M_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_REF_20M_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_TM_400M_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_TM_200M_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TM_100M_CLK_EN + Reserved + 26 + 1 + read-write + + + REG_REF_50M_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_REF_25M_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_TM_480M_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_REF_240M_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_TM_240M_CLK_EN + Reserved + 31 + 1 + read-write + + + + + REF_CLK_CTRL2 + Reserved + 0x2C + 0x20 + 0x00000115 + + + REG_REF_160M_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_TM_160M_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_REF_120M_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_TM_120M_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_REF_80M_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_TM_80M_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_TM_60M_CLK_EN + Reserved + 6 + 1 + read-write + + + REG_TM_48M_CLK_EN + Reserved + 7 + 1 + read-write + + + REG_REF_20M_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_TM_20M_CLK_EN + Reserved + 9 + 1 + read-write + + + + + PERI_CLK_CTRL00 + Reserved + 0x30 + 0x20 + 0x0000C03C + + + REG_FLASH_CLK_SRC_SEL + Reserved + 0 + 2 + read-write + + + REG_FLASH_PLL_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_FLASH_CORE_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_FLASH_CORE_CLK_DIV_NUM + Reserved + 4 + 8 + read-write + + + REG_PSRAM_CLK_SRC_SEL + Reserved + 12 + 2 + read-write + + + REG_PSRAM_PLL_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_PSRAM_CORE_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_PSRAM_CORE_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_PAD_EMAC_REF_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_EMAC_RMII_CLK_SRC_SEL + Reserved + 25 + 2 + read-write + + + REG_EMAC_RMII_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_EMAC_RX_CLK_SRC_SEL + Reserved + 28 + 1 + read-write + + + REG_EMAC_RX_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL01 + Reserved + 0x34 + 0x20 + 0x00000401 + + + REG_EMAC_RX_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_EMAC_TX_CLK_SRC_SEL + Reserved + 8 + 1 + read-write + + + REG_EMAC_TX_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_EMAC_TX_CLK_DIV_NUM + Reserved + 10 + 8 + read-write + + + REG_EMAC_PTP_REF_CLK_SRC_SEL + Reserved + 18 + 1 + read-write + + + REG_EMAC_PTP_REF_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_EMAC_UNUSED0_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_EMAC_UNUSED1_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_SDIO_HS_MODE + Reserved + 22 + 1 + read-write + + + REG_SDIO_LS_CLK_SRC_SEL + Reserved + 23 + 1 + read-write + + + REG_SDIO_LS_CLK_EN + Reserved + 24 + 1 + read-write + + + + + PERI_CLK_CTRL02 + Reserved + 0x38 + 0x20 + + + REG_SDIO_LS_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_SDIO_LS_CLK_EDGE_CFG_UPDATE + Reserved + 8 + 1 + write-only + + + REG_SDIO_LS_CLK_EDGE_L + Reserved + 9 + 4 + read-write + + + REG_SDIO_LS_CLK_EDGE_H + Reserved + 13 + 4 + read-write + + + REG_SDIO_LS_CLK_EDGE_N + Reserved + 17 + 4 + read-write + + + REG_SDIO_LS_SLF_CLK_EDGE_SEL + Reserved + 21 + 2 + read-write + + + REG_SDIO_LS_DRV_CLK_EDGE_SEL + Reserved + 23 + 2 + read-write + + + REG_SDIO_LS_SAM_CLK_EDGE_SEL + Reserved + 25 + 2 + read-write + + + REG_SDIO_LS_SLF_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_SDIO_LS_DRV_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_SDIO_LS_SAM_CLK_EN + Reserved + 29 + 1 + read-write + + + REG_MIPI_DSI_DPHY_CLK_SRC_SEL + Reserved + 30 + 2 + read-write + + + + + PERI_CLK_CTRL03 + Reserved + 0x3C + 0x20 + + + REG_MIPI_DSI_DPHY_CFG_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_MIPI_DSI_DPHY_PLL_REFCLK_EN + Reserved + 1 + 1 + read-write + + + REG_MIPI_CSI_DPHY_CLK_SRC_SEL + Reserved + 2 + 2 + read-write + + + REG_MIPI_CSI_DPHY_CFG_CLK_EN + Reserved + 4 + 1 + read-write + + + REG_MIPI_DSI_DPICLK_SRC_SEL + Reserved + 5 + 2 + read-write + + + REG_MIPI_DSI_DPICLK_EN + Reserved + 7 + 1 + read-write + + + REG_MIPI_DSI_DPICLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + + + PERI_CLK_CTRL10 + Reserved + 0x40 + 0x20 + + + REG_I2C0_CLK_SRC_SEL + Reserved + 0 + 1 + read-write + + + REG_I2C0_CLK_EN + Reserved + 1 + 1 + read-write + + + REG_I2C0_CLK_DIV_NUM + Reserved + 2 + 8 + read-write + + + REG_I2C0_CLK_DIV_NUMERATOR + Reserved + 10 + 8 + read-write + + + REG_I2C0_CLK_DIV_DENOMINATOR + Reserved + 18 + 8 + read-write + + + REG_I2C1_CLK_SRC_SEL + Reserved + 26 + 1 + read-write + + + REG_I2C1_CLK_EN + Reserved + 27 + 1 + read-write + + + + + PERI_CLK_CTRL11 + Reserved + 0x44 + 0x20 + + + REG_I2C1_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_I2C1_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_I2C1_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_I2S0_RX_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_I2S0_RX_CLK_SRC_SEL + Reserved + 25 + 2 + read-write + + + + + PERI_CLK_CTRL12 + Reserved + 0x48 + 0x20 + + + REG_I2S0_RX_DIV_N + Reserved + 0 + 8 + read-write + + + REG_I2S0_RX_DIV_X + Reserved + 8 + 9 + read-write + + + REG_I2S0_RX_DIV_Y + Reserved + 17 + 9 + read-write + + + + + PERI_CLK_CTRL13 + Reserved + 0x4C + 0x20 + + + REG_I2S0_RX_DIV_Z + Reserved + 0 + 9 + read-write + + + REG_I2S0_RX_DIV_YN1 + Reserved + 9 + 1 + read-write + + + REG_I2S0_TX_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_I2S0_TX_CLK_SRC_SEL + Reserved + 11 + 2 + read-write + + + REG_I2S0_TX_DIV_N + Reserved + 13 + 8 + read-write + + + REG_I2S0_TX_DIV_X + Reserved + 21 + 9 + read-write + + + + + PERI_CLK_CTRL14 + Reserved + 0x50 + 0x20 + + + REG_I2S0_TX_DIV_Y + Reserved + 0 + 9 + read-write + + + REG_I2S0_TX_DIV_Z + Reserved + 9 + 9 + read-write + + + REG_I2S0_TX_DIV_YN1 + Reserved + 18 + 1 + read-write + + + REG_I2S0_MST_CLK_SEL + Reserved + 19 + 1 + read-write + + + REG_I2S1_RX_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_I2S1_RX_CLK_SRC_SEL + Reserved + 21 + 2 + read-write + + + REG_I2S1_RX_DIV_N + Reserved + 23 + 8 + read-write + + + + + PERI_CLK_CTRL15 + Reserved + 0x54 + 0x20 + + + REG_I2S1_RX_DIV_X + Reserved + 0 + 9 + read-write + + + REG_I2S1_RX_DIV_Y + Reserved + 9 + 9 + read-write + + + REG_I2S1_RX_DIV_Z + Reserved + 18 + 9 + read-write + + + REG_I2S1_RX_DIV_YN1 + Reserved + 27 + 1 + read-write + + + REG_I2S1_TX_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_I2S1_TX_CLK_SRC_SEL + Reserved + 29 + 2 + read-write + + + + + PERI_CLK_CTRL16 + Reserved + 0x58 + 0x20 + + + REG_I2S1_TX_DIV_N + Reserved + 0 + 8 + read-write + + + REG_I2S1_TX_DIV_X + Reserved + 8 + 9 + read-write + + + REG_I2S1_TX_DIV_Y + Reserved + 17 + 9 + read-write + + + + + PERI_CLK_CTRL17 + Reserved + 0x5C + 0x20 + + + REG_I2S1_TX_DIV_Z + Reserved + 0 + 9 + read-write + + + REG_I2S1_TX_DIV_YN1 + Reserved + 9 + 1 + read-write + + + REG_I2S1_MST_CLK_SEL + Reserved + 10 + 1 + read-write + + + REG_I2S2_RX_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_I2S2_RX_CLK_SRC_SEL + Reserved + 12 + 2 + read-write + + + REG_I2S2_RX_DIV_N + Reserved + 14 + 8 + read-write + + + REG_I2S2_RX_DIV_X + Reserved + 22 + 9 + read-write + + + + + PERI_CLK_CTRL18 + Reserved + 0x60 + 0x20 + + + REG_I2S2_RX_DIV_Y + Reserved + 0 + 9 + read-write + + + REG_I2S2_RX_DIV_Z + Reserved + 9 + 9 + read-write + + + REG_I2S2_RX_DIV_YN1 + Reserved + 18 + 1 + read-write + + + REG_I2S2_TX_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_I2S2_TX_CLK_SRC_SEL + Reserved + 20 + 2 + read-write + + + REG_I2S2_TX_DIV_N + Reserved + 22 + 8 + read-write + + + + + PERI_CLK_CTRL19 + Reserved + 0x64 + 0x20 + + + REG_I2S2_TX_DIV_X + Reserved + 0 + 9 + read-write + + + REG_I2S2_TX_DIV_Y + Reserved + 9 + 9 + read-write + + + REG_I2S2_TX_DIV_Z + Reserved + 18 + 9 + read-write + + + REG_I2S2_TX_DIV_YN1 + Reserved + 27 + 1 + read-write + + + REG_I2S2_MST_CLK_SEL + Reserved + 28 + 1 + read-write + + + REG_LCD_CLK_SRC_SEL + Reserved + 29 + 2 + read-write + + + REG_LCD_CLK_EN + Reserved + 31 + 1 + read-write + + + + + PERI_CLK_CTRL110 + Reserved + 0x68 + 0x20 + 0x04000000 + + + REG_LCD_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_LCD_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_LCD_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART0_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART0_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL111 + Reserved + 0x6C + 0x20 + 0x04000000 + + + REG_UART0_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART0_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART0_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART1_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART1_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL112 + Reserved + 0x70 + 0x20 + 0x04000000 + + + REG_UART1_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART1_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART1_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART2_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART2_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL113 + Reserved + 0x74 + 0x20 + 0x04000000 + + + REG_UART2_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART2_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART2_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART3_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART3_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL114 + Reserved + 0x78 + 0x20 + 0x04000000 + + + REG_UART3_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART3_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART3_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_UART4_CLK_SRC_SEL + Reserved + 24 + 2 + read-write + + + REG_UART4_CLK_EN + Reserved + 26 + 1 + read-write + + + + + PERI_CLK_CTRL115 + Reserved + 0x7C + 0x20 + + + REG_UART4_SCLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_UART4_SCLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_UART4_SCLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + REG_TWAI0_CLK_SRC_SEL + Reserved + 24 + 1 + read-write + + + REG_TWAI0_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TWAI1_CLK_SRC_SEL + Reserved + 26 + 1 + read-write + + + REG_TWAI1_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_TWAI2_CLK_SRC_SEL + Reserved + 28 + 1 + read-write + + + REG_TWAI2_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL116 + Reserved + 0x80 + 0x20 + 0x01100008 + + + REG_GPSPI2_CLK_SRC_SEL + Reserved + 0 + 3 + read-write + + + REG_GPSPI2_HS_CLK_EN + Reserved + 3 + 1 + read-write + + + REG_GPSPI2_HS_CLK_DIV_NUM + Reserved + 4 + 8 + read-write + + + REG_GPSPI2_MST_CLK_DIV_NUM + Reserved + 12 + 8 + read-write + + + REG_GPSPI2_MST_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_GPSPI3_CLK_SRC_SEL + Reserved + 21 + 3 + read-write + + + REG_GPSPI3_HS_CLK_EN + Reserved + 24 + 1 + read-write + + + + + PERI_CLK_CTRL117 + Reserved + 0x84 + 0x20 + 0x00010000 + + + REG_GPSPI3_HS_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_GPSPI3_MST_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_GPSPI3_MST_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_PARLIO_RX_CLK_SRC_SEL + Reserved + 17 + 2 + read-write + + + REG_PARLIO_RX_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_PARLIO_RX_CLK_DIV_NUM + Reserved + 20 + 8 + read-write + + + + + PERI_CLK_CTRL118 + Reserved + 0x88 + 0x20 + + + REG_PARLIO_RX_CLK_DIV_NUMERATOR + Reserved + 0 + 8 + read-write + + + REG_PARLIO_RX_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 + read-write + + + REG_PARLIO_TX_CLK_SRC_SEL + Reserved + 16 + 2 + read-write + + + REG_PARLIO_TX_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_PARLIO_TX_CLK_DIV_NUM + Reserved + 19 + 8 + read-write + + + + + PERI_CLK_CTRL119 + Reserved + 0x8C + 0x20 + + + REG_PARLIO_TX_CLK_DIV_NUMERATOR + Reserved + 0 + 8 + read-write + + + REG_PARLIO_TX_CLK_DIV_DENOMINATOR + Reserved + 8 + 8 + read-write + + + REG_I3C_MST_CLK_SRC_SEL + Reserved + 16 + 2 + read-write + + + REG_I3C_MST_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_I3C_MST_CLK_DIV_NUM + Reserved + 19 + 8 + read-write + + + REG_CAM_CLK_SRC_SEL + Reserved + 27 + 2 + read-write + + + REG_CAM_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL120 + Reserved + 0x90 + 0x20 + + + REG_CAM_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_CAM_CLK_DIV_NUMERATOR + Reserved + 8 + 8 + read-write + + + REG_CAM_CLK_DIV_DENOMINATOR + Reserved + 16 + 8 + read-write + + + + + PERI_CLK_CTRL20 + Reserved + 0x94 + 0x20 + 0xC9000000 + + + REG_MCPWM0_CLK_SRC_SEL + Reserved + 0 + 2 + read-write + + + REG_MCPWM0_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_MCPWM0_CLK_DIV_NUM + Reserved + 3 + 8 + read-write + + + REG_MCPWM1_CLK_SRC_SEL + Reserved + 11 + 2 + read-write + + + REG_MCPWM1_CLK_EN + Reserved + 13 + 1 + read-write + + + REG_MCPWM1_CLK_DIV_NUM + Reserved + 14 + 8 + read-write + + + REG_TIMERGRP0_T0_SRC_SEL + Reserved + 22 + 2 + read-write + + + REG_TIMERGRP0_T0_CLK_EN + Reserved + 24 + 1 + read-write + + + REG_TIMERGRP0_T1_SRC_SEL + Reserved + 25 + 2 + read-write + + + REG_TIMERGRP0_T1_CLK_EN + Reserved + 27 + 1 + read-write + + + REG_TIMERGRP0_WDT_SRC_SEL + Reserved + 28 + 2 + read-write + + + REG_TIMERGRP0_WDT_CLK_EN + Reserved + 30 + 1 + read-write + + + REG_TIMERGRP0_TGRT_CLK_EN + Reserved + 31 + 1 + read-write + + + + + PERI_CLK_CTRL21 + Reserved + 0x98 + 0x20 + 0x52400000 + + + REG_TIMERGRP0_TGRT_CLK_SRC_SEL + Reserved + 0 + 4 + read-write + + + REG_TIMERGRP0_TGRT_CLK_DIV_NUM + Reserved + 4 + 16 + read-write + + + REG_TIMERGRP1_T0_SRC_SEL + Reserved + 20 + 2 + read-write + + + REG_TIMERGRP1_T0_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_TIMERGRP1_T1_SRC_SEL + Reserved + 23 + 2 + read-write + + + REG_TIMERGRP1_T1_CLK_EN + Reserved + 25 + 1 + read-write + + + REG_TIMERGRP1_WDT_SRC_SEL + Reserved + 26 + 2 + read-write + + + REG_TIMERGRP1_WDT_CLK_EN + Reserved + 28 + 1 + read-write + + + REG_SYSTIMER_CLK_SRC_SEL + Reserved + 29 + 1 + read-write + + + REG_SYSTIMER_CLK_EN + Reserved + 30 + 1 + read-write + + + + + PERI_CLK_CTRL22 + Reserved + 0x9C + 0x20 + + + REG_LEDC_CLK_SRC_SEL + Reserved + 0 + 2 + read-write + + + REG_LEDC_CLK_EN + Reserved + 2 + 1 + read-write + + + REG_RMT_CLK_SRC_SEL + Reserved + 3 + 2 + read-write + + + REG_RMT_CLK_EN + Reserved + 5 + 1 + read-write + + + REG_RMT_CLK_DIV_NUM + Reserved + 6 + 8 + read-write + + + REG_RMT_CLK_DIV_NUMERATOR + Reserved + 14 + 8 + read-write + + + REG_RMT_CLK_DIV_DENOMINATOR + Reserved + 22 + 8 + read-write + + + REG_ADC_CLK_SRC_SEL + Reserved + 30 + 2 + read-write + + + + + PERI_CLK_CTRL23 + Reserved + 0xA0 + 0x20 + 0x00000008 + + + REG_ADC_CLK_EN + Reserved + 0 + 1 + read-write + + + REG_ADC_CLK_DIV_NUM + Reserved + 1 + 8 + read-write + + + REG_ADC_CLK_DIV_NUMERATOR + Reserved + 9 + 8 + read-write + + + REG_ADC_CLK_DIV_DENOMINATOR + Reserved + 17 + 8 + read-write + + + + + PERI_CLK_CTRL24 + Reserved + 0xA4 + 0x20 + 0x00000404 + + + REG_ADC_SAR1_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_ADC_SAR2_CLK_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_PVT_CLK_DIV_NUM + Reserved + 16 + 8 + read-write + + + REG_PVT_CLK_EN + Reserved + 24 + 1 + read-write + + + + + PERI_CLK_CTRL25 + Reserved + 0xA8 + 0x20 + 0x007FC000 + + + REG_PVT_PERI_GROUP_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_PVT_PERI_GROUP1_CLK_EN + Reserved + 8 + 1 + read-write + + + REG_PVT_PERI_GROUP2_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_PVT_PERI_GROUP3_CLK_EN + Reserved + 10 + 1 + read-write + + + REG_PVT_PERI_GROUP4_CLK_EN + Reserved + 11 + 1 + read-write + + + REG_CRYPTO_CLK_SRC_SEL + Reserved + 12 + 2 + read-write + + + REG_CRYPTO_AES_CLK_EN + Reserved + 14 + 1 + read-write + + + REG_CRYPTO_DS_CLK_EN + Reserved + 15 + 1 + read-write + + + REG_CRYPTO_ECC_CLK_EN + Reserved + 16 + 1 + read-write + + + REG_CRYPTO_HMAC_CLK_EN + Reserved + 17 + 1 + read-write + + + REG_CRYPTO_RSA_CLK_EN + Reserved + 18 + 1 + read-write + + + REG_CRYPTO_SEC_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_CRYPTO_SHA_CLK_EN + Reserved + 20 + 1 + read-write + + + REG_CRYPTO_ECDSA_CLK_EN + Reserved + 21 + 1 + read-write + + + REG_CRYPTO_KM_CLK_EN + Reserved + 22 + 1 + read-write + + + REG_ISP_CLK_SRC_SEL + Reserved + 23 + 2 + read-write + + + REG_ISP_CLK_EN + Reserved + 25 + 1 + read-write + + + + + PERI_CLK_CTRL26 + Reserved + 0xAC + 0x20 + 0x00000200 + + + REG_ISP_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_IOMUX_CLK_SRC_SEL + Reserved + 8 + 1 + read-write + + + REG_IOMUX_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_IOMUX_CLK_DIV_NUM + Reserved + 10 + 8 + read-write + + + REG_H264_CLK_SRC_SEL + Reserved + 18 + 1 + read-write + + + REG_H264_CLK_EN + Reserved + 19 + 1 + read-write + + + REG_H264_CLK_DIV_NUM + Reserved + 20 + 8 + read-write + + + REG_PADBIST_RX_CLK_SRC_SEL + Reserved + 28 + 1 + read-write + + + REG_PADBIST_RX_CLK_EN + Reserved + 29 + 1 + read-write + + + + + PERI_CLK_CTRL27 + Reserved + 0xB0 + 0x20 + + + REG_PADBIST_RX_CLK_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_PADBIST_TX_CLK_SRC_SEL + Reserved + 8 + 1 + read-write + + + REG_PADBIST_TX_CLK_EN + Reserved + 9 + 1 + read-write + + + REG_PADBIST_TX_CLK_DIV_NUM + Reserved + 10 + 8 + read-write + + + + + CLK_FORCE_ON_CTRL0 + Reserved + 0xB4 + 0x20 + 0x0003FFFF + + + REG_CPUICM_GATED_CLK_FORCE_ON + Reserved + 0 + 1 + read-write + + + REG_TCM_CPU_CLK_FORCE_ON + Reserved + 1 + 1 + read-write + + + REG_BUSMON_CPU_CLK_FORCE_ON + Reserved + 2 + 1 + read-write + + + REG_L1CACHE_CPU_CLK_FORCE_ON + Reserved + 3 + 1 + read-write + + + REG_L1CACHE_D_CPU_CLK_FORCE_ON + Reserved + 4 + 1 + read-write + + + REG_L1CACHE_I0_CPU_CLK_FORCE_ON + Reserved + 5 + 1 + read-write + + + REG_L1CACHE_I1_CPU_CLK_FORCE_ON + Reserved + 6 + 1 + read-write + + + REG_TRACE_CPU_CLK_FORCE_ON + Reserved + 7 + 1 + read-write + + + REG_TRACE_SYS_CLK_FORCE_ON + Reserved + 8 + 1 + read-write + + + REG_L1CACHE_MEM_CLK_FORCE_ON + Reserved + 9 + 1 + read-write + + + REG_L1CACHE_D_MEM_CLK_FORCE_ON + Reserved + 10 + 1 + read-write + + + REG_L1CACHE_I0_MEM_CLK_FORCE_ON + Reserved + 11 + 1 + read-write + + + REG_L1CACHE_I1_MEM_CLK_FORCE_ON + Reserved + 12 + 1 + read-write + + + REG_L2CACHE_MEM_CLK_FORCE_ON + Reserved + 13 + 1 + read-write + + + REG_L2MEM_MEM_CLK_FORCE_ON + Reserved + 14 + 1 + read-write + + + REG_SAR1_CLK_FORCE_ON + Reserved + 15 + 1 + read-write + + + REG_SAR2_CLK_FORCE_ON + Reserved + 16 + 1 + read-write + + + REG_GMAC_TX_CLK_FORCE_ON + Reserved + 17 + 1 + read-write + + + + + DPA_CTRL0 + Reserved + 0xB8 + 0x20 + + + REG_SEC_DPA_LEVEL + Reserved + 0 + 2 + read-write + + + REG_SEC_DPA_CFG_SEL + Reserved + 2 + 1 + read-write + + + + + ANA_PLL_CTRL0 + Reserved + 0xBC + 0x20 + + + REG_PLLA_CAL_END + Reserved + 0 + 1 + read-only + + + REG_PLLA_CAL_STOP + Reserved + 1 + 1 + read-write + + + REG_CPU_PLL_CAL_END + Reserved + 2 + 1 + read-only + + + REG_CPU_PLL_CAL_STOP + Reserved + 3 + 1 + read-write + + + REG_SDIO_PLL_CAL_END + Reserved + 4 + 1 + read-only + + + REG_SDIO_PLL_CAL_STOP + Reserved + 5 + 1 + read-write + + + REG_SYS_PLL_CAL_END + Reserved + 6 + 1 + read-only + + + REG_SYS_PLL_CAL_STOP + Reserved + 7 + 1 + read-write + + + REG_MSPI_CAL_END + Reserved + 8 + 1 + read-only + + + REG_MSPI_CAL_STOP + Reserved + 9 + 1 + read-write + + + + + HP_RST_EN0 + Reserved + 0xC0 + 0x20 + 0x00000100 + + + REG_RST_EN_CORECTRL + Reserved + 0 + 1 + read-write + + + REG_RST_EN_PVT_TOP + Reserved + 1 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP1 + Reserved + 2 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP2 + Reserved + 3 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP3 + Reserved + 4 + 1 + read-write + + + REG_RST_EN_PVT_PERI_GROUP4 + Reserved + 5 + 1 + read-write + + + REG_RST_EN_REGDMA + Reserved + 6 + 1 + read-write + + + REG_RST_EN_CORE0_GLOBAL + Reserved + 7 + 1 + read-write + + + REG_RST_EN_CORE1_GLOBAL + Reserved + 8 + 1 + read-write + + + REG_RST_EN_CORETRACE0 + Reserved + 9 + 1 + read-write + + + REG_RST_EN_CORETRACE1 + Reserved + 10 + 1 + read-write + + + REG_RST_EN_HP_TCM + Reserved + 11 + 1 + read-write + + + REG_RST_EN_HP_CACHE + Reserved + 12 + 1 + read-write + + + REG_RST_EN_L1_I0_CACHE + Reserved + 13 + 1 + read-write + + + REG_RST_EN_L1_I1_CACHE + Reserved + 14 + 1 + read-write + + + REG_RST_EN_L1_D_CACHE + Reserved + 15 + 1 + read-write + + + REG_RST_EN_L2_CACHE + Reserved + 16 + 1 + read-write + + + REG_RST_EN_L2_MEM + Reserved + 17 + 1 + read-write + + + REG_RST_EN_L2MEMMON + Reserved + 18 + 1 + read-write + + + REG_RST_EN_TCMMON + Reserved + 19 + 1 + read-write + + + REG_RST_EN_PVT_APB + Reserved + 20 + 1 + read-write + + + REG_RST_EN_GDMA + Reserved + 21 + 1 + read-write + + + REG_RST_EN_MSPI_AXI + Reserved + 22 + 1 + read-write + + + REG_RST_EN_DUAL_MSPI_AXI + Reserved + 23 + 1 + read-write + + + REG_RST_EN_MSPI_APB + Reserved + 24 + 1 + read-write + + + REG_RST_EN_DUAL_MSPI_APB + Reserved + 25 + 1 + read-write + + + REG_RST_EN_DSI_BRG + Reserved + 26 + 1 + read-write + + + REG_RST_EN_CSI_HOST + Reserved + 27 + 1 + read-write + + + REG_RST_EN_CSI_BRG + Reserved + 28 + 1 + read-write + + + REG_RST_EN_ISP + Reserved + 29 + 1 + read-write + + + REG_RST_EN_JPEG + Reserved + 30 + 1 + read-write + + + REG_RST_EN_DMA2D + Reserved + 31 + 1 + read-write + + + + + HP_RST_EN1 + Reserved + 0xC4 + 0x20 + + + REG_RST_EN_PPA + Reserved + 0 + 1 + read-write + + + REG_RST_EN_AHB_PDMA + Reserved + 1 + 1 + read-write + + + REG_RST_EN_AXI_PDMA + Reserved + 2 + 1 + read-write + + + REG_RST_EN_IOMUX + Reserved + 3 + 1 + read-write + + + REG_RST_EN_PADBIST + Reserved + 4 + 1 + read-write + + + REG_RST_EN_STIMER + Reserved + 5 + 1 + read-write + + + REG_RST_EN_TIMERGRP0 + Reserved + 6 + 1 + read-write + + + REG_RST_EN_TIMERGRP1 + Reserved + 7 + 1 + read-write + + + REG_RST_EN_UART0_CORE + Reserved + 8 + 1 + read-write + + + REG_RST_EN_UART1_CORE + Reserved + 9 + 1 + read-write + + + REG_RST_EN_UART2_CORE + Reserved + 10 + 1 + read-write + + + REG_RST_EN_UART3_CORE + Reserved + 11 + 1 + read-write + + + REG_RST_EN_UART4_CORE + Reserved + 12 + 1 + read-write + + + REG_RST_EN_UART0_APB + Reserved + 13 + 1 + read-write + + + REG_RST_EN_UART1_APB + Reserved + 14 + 1 + read-write + + + REG_RST_EN_UART2_APB + Reserved + 15 + 1 + read-write + + + REG_RST_EN_UART3_APB + Reserved + 16 + 1 + read-write + + + REG_RST_EN_UART4_APB + Reserved + 17 + 1 + read-write + + + REG_RST_EN_UHCI + Reserved + 18 + 1 + read-write + + + REG_RST_EN_I3CMST + Reserved + 19 + 1 + read-write + + + REG_RST_EN_I3CSLV + Reserved + 20 + 1 + read-write + + + REG_RST_EN_I2C1 + Reserved + 21 + 1 + read-write + + + REG_RST_EN_I2C0 + Reserved + 22 + 1 + read-write + + + REG_RST_EN_RMT + Reserved + 23 + 1 + read-write + + + REG_RST_EN_PWM0 + Reserved + 24 + 1 + read-write + + + REG_RST_EN_PWM1 + Reserved + 25 + 1 + read-write + + + REG_RST_EN_CAN0 + Reserved + 26 + 1 + read-write + + + REG_RST_EN_CAN1 + Reserved + 27 + 1 + read-write + + + REG_RST_EN_CAN2 + Reserved + 28 + 1 + read-write + + + REG_RST_EN_LEDC + Reserved + 29 + 1 + read-write + + + REG_RST_EN_PCNT + Reserved + 30 + 1 + read-write + + + REG_RST_EN_ETM + Reserved + 31 + 1 + read-write + + + + + HP_RST_EN2 + Reserved + 0xC8 + 0x20 + + + REG_RST_EN_INTRMTX + Reserved + 0 + 1 + read-write + + + REG_RST_EN_PARLIO + Reserved + 1 + 1 + read-write + + + REG_RST_EN_PARLIO_RX + Reserved + 2 + 1 + read-write + + + REG_RST_EN_PARLIO_TX + Reserved + 3 + 1 + read-write + + + REG_RST_EN_I2S0_APB + Reserved + 4 + 1 + read-write + + + REG_RST_EN_I2S1_APB + Reserved + 5 + 1 + read-write + + + REG_RST_EN_I2S2_APB + Reserved + 6 + 1 + read-write + + + REG_RST_EN_SPI2 + Reserved + 7 + 1 + read-write + + + REG_RST_EN_SPI3 + Reserved + 8 + 1 + read-write + + + REG_RST_EN_LCDCAM + Reserved + 9 + 1 + read-write + + + REG_RST_EN_ADC + Reserved + 10 + 1 + read-write + + + REG_RST_EN_BITSRAMBLER + Reserved + 11 + 1 + read-write + + + REG_RST_EN_BITSRAMBLER_RX + Reserved + 12 + 1 + read-write + + + REG_RST_EN_BITSRAMBLER_TX + Reserved + 13 + 1 + read-write + + + REG_RST_EN_CRYPTO + Reserved + 14 + 1 + read-write + + + REG_RST_EN_SEC + Reserved + 15 + 1 + read-write + + + REG_RST_EN_AES + Reserved + 16 + 1 + read-write + + + REG_RST_EN_DS + Reserved + 17 + 1 + read-write + + + REG_RST_EN_SHA + Reserved + 18 + 1 + read-write + + + REG_RST_EN_HMAC + Reserved + 19 + 1 + read-write + + + REG_RST_EN_ECDSA + Reserved + 20 + 1 + read-write + + + REG_RST_EN_RSA + Reserved + 21 + 1 + read-write + + + REG_RST_EN_ECC + Reserved + 22 + 1 + read-write + + + REG_RST_EN_KM + Reserved + 23 + 1 + read-write + + + REG_RST_EN_H264 + Reserved + 24 + 1 + read-write + + + + + HP_FORCE_NORST0 + Reserved + 0xCC + 0x20 + + + REG_FORCE_NORST_CORE0 + Reserved + 0 + 1 + read-write + + + REG_FORCE_NORST_CORE1 + Reserved + 1 + 1 + read-write + + + REG_FORCE_NORST_CORETRACE0 + Reserved + 2 + 1 + read-write + + + REG_FORCE_NORST_CORETRACE1 + Reserved + 3 + 1 + read-write + + + REG_FORCE_NORST_L2MEMMON + Reserved + 4 + 1 + read-write + + + REG_FORCE_NORST_TCMMON + Reserved + 5 + 1 + read-write + + + REG_FORCE_NORST_GDMA + Reserved + 6 + 1 + read-write + + + REG_FORCE_NORST_MSPI_AXI + Reserved + 7 + 1 + read-write + + + REG_FORCE_NORST_DUAL_MSPI_AXI + Reserved + 8 + 1 + read-write + + + REG_FORCE_NORST_MSPI_APB + Reserved + 9 + 1 + read-write + + + REG_FORCE_NORST_DUAL_MSPI_APB + Reserved + 10 + 1 + read-write + + + REG_FORCE_NORST_DSI_BRG + Reserved + 11 + 1 + read-write + + + REG_FORCE_NORST_CSI_HOST + Reserved + 12 + 1 + read-write + + + REG_FORCE_NORST_CSI_BRG + Reserved + 13 + 1 + read-write + + + REG_FORCE_NORST_ISP + Reserved + 14 + 1 + read-write + + + REG_FORCE_NORST_JPEG + Reserved + 15 + 1 + read-write + + + REG_FORCE_NORST_DMA2D + Reserved + 16 + 1 + read-write + + + REG_FORCE_NORST_PPA + Reserved + 17 + 1 + read-write + + + REG_FORCE_NORST_AHB_PDMA + Reserved + 18 + 1 + read-write + + + REG_FORCE_NORST_AXI_PDMA + Reserved + 19 + 1 + read-write + + + REG_FORCE_NORST_IOMUX + Reserved + 20 + 1 + read-write + + + REG_FORCE_NORST_PADBIST + Reserved + 21 + 1 + read-write + + + REG_FORCE_NORST_STIMER + Reserved + 22 + 1 + read-write + + + REG_FORCE_NORST_TIMERGRP0 + Reserved + 23 + 1 + read-write + + + REG_FORCE_NORST_TIMERGRP1 + Reserved + 24 + 1 + read-write + + + REG_FORCE_NORST_UART0 + Reserved + 25 + 1 + read-write + + + REG_FORCE_NORST_UART1 + Reserved + 26 + 1 + read-write + + + REG_FORCE_NORST_UART2 + Reserved + 27 + 1 + read-write + + + REG_FORCE_NORST_UART3 + Reserved + 28 + 1 + read-write + + + REG_FORCE_NORST_UART4 + Reserved + 29 + 1 + read-write + + + REG_FORCE_NORST_UHCI + Reserved + 30 + 1 + read-write + + + REG_FORCE_NORST_I3CMST + Reserved + 31 + 1 + read-write + + + + + HP_FORCE_NORST1 + Reserved + 0xD0 + 0x20 + + + REG_FORCE_NORST_I3CSLV + Reserved + 0 + 1 + read-write + + + REG_FORCE_NORST_I2C1 + Reserved + 1 + 1 + read-write + + + REG_FORCE_NORST_I2C0 + Reserved + 2 + 1 + read-write + + + REG_FORCE_NORST_RMT + Reserved + 3 + 1 + read-write + + + REG_FORCE_NORST_PWM0 + Reserved + 4 + 1 + read-write + + + REG_FORCE_NORST_PWM1 + Reserved + 5 + 1 + read-write + + + REG_FORCE_NORST_CAN0 + Reserved + 6 + 1 + read-write + + + REG_FORCE_NORST_CAN1 + Reserved + 7 + 1 + read-write + + + REG_FORCE_NORST_CAN2 + Reserved + 8 + 1 + read-write + + + REG_FORCE_NORST_LEDC + Reserved + 9 + 1 + read-write + + + REG_FORCE_NORST_PCNT + Reserved + 10 + 1 + read-write + + + REG_FORCE_NORST_ETM + Reserved + 11 + 1 + read-write + + + REG_FORCE_NORST_INTRMTX + Reserved + 12 + 1 + read-write + + + REG_FORCE_NORST_PARLIO + Reserved + 13 + 1 + read-write + + + REG_FORCE_NORST_PARLIO_RX + Reserved + 14 + 1 + read-write + + + REG_FORCE_NORST_PARLIO_TX + Reserved + 15 + 1 + read-write + + + REG_FORCE_NORST_I2S0 + Reserved + 16 + 1 + read-write + + + REG_FORCE_NORST_I2S1 + Reserved + 17 + 1 + read-write + + + REG_FORCE_NORST_I2S2 + Reserved + 18 + 1 + read-write + + + REG_FORCE_NORST_SPI2 + Reserved + 19 + 1 + read-write + + + REG_FORCE_NORST_SPI3 + Reserved + 20 + 1 + read-write + + + REG_FORCE_NORST_LCDCAM + Reserved + 21 + 1 + read-write + + + REG_FORCE_NORST_ADC + Reserved + 22 + 1 + read-write + + + REG_FORCE_NORST_BITSRAMBLER + Reserved + 23 + 1 + read-write + + + REG_FORCE_NORST_BITSRAMBLER_RX + Reserved + 24 + 1 + read-write + + + REG_FORCE_NORST_BITSRAMBLER_TX + Reserved + 25 + 1 + read-write + + + REG_FORCE_NORST_H264 + Reserved + 26 + 1 + read-write + + + + + HPWDT_CORE0_RST_CTRL0 + Reserved + 0xD4 + 0x20 + 0x00001011 + + + REG_HPCORE0_STALL_EN + Reserved + 0 + 1 + read-write + + + REG_HPCORE0_STALL_WAIT_NUM + Reserved + 1 + 8 + read-write + + + REG_WDT_HPCORE0_RST_LEN + Reserved + 9 + 8 + read-write + + + + + HPWDT_CORE1_RST_CTRL0 + Reserved + 0xD8 + 0x20 + 0x00001011 + + + REG_HPCORE1_STALL_EN + Reserved + 0 + 1 + read-write + + + REG_HPCORE1_STALL_WAIT_NUM + Reserved + 1 + 8 + read-write + + + REG_WDT_HPCORE1_RST_LEN + Reserved + 9 + 8 + read-write + + + + + CPU_SRC_FREQ0 + CPU Source Frequency + 0xDC + 0x20 + + + REG_CPU_SRC_FREQ + cpu source clock frequency, step by 0.25MHz + 0 + 32 + read-only + + + + + CPU_CLK_STATUS0 + CPU Clock Status + 0xE0 + 0x20 + + + REG_ASIC_OR_FPGA + 0: ASIC mode, 1: FPGA mode + 0 + 1 + read-only + + + REG_CPU_DIV_EFFECT + 0: Divider bypass, 1: Divider takes effect + 1 + 1 + read-only + + + REG_CPU_SRC_IS_CPLL + 0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m + 2 + 1 + read-only + + + REG_CPU_DIV_NUM_CUR + cpu current div number + 3 + 8 + read-only + + + REG_CPU_DIV_NUMERATOR_CUR + cpu current div numerator + 11 + 8 + read-only + + + REG_CPU_DIV_DENOMINATOR_CUR + cpu current div denominator + 19 + 8 + read-only + + + + + DBG_CLK_CTRL0 + Reserved + 0xE4 + 0x20 + 0x03FFFFFF + + + REG_DBG_CH0_SEL + Reserved + 0 + 8 + read-write + + + REG_DBG_CH1_SEL + Reserved + 8 + 8 + read-write + + + REG_DBG_CH2_SEL + Reserved + 16 + 8 + read-write + + + REG_DBG_CH0_DIV_NUM + Reserved + 24 + 8 + read-write + + + + + DBG_CLK_CTRL1 + Reserved + 0xE8 + 0x20 + 0x00000303 + + + REG_DBG_CH1_DIV_NUM + Reserved + 0 + 8 + read-write + + + REG_DBG_CH2_DIV_NUM + Reserved + 8 + 8 + read-write + + + REG_DBG_CH0_EN + Reserved + 16 + 1 + read-write + + + REG_DBG_CH1_EN + Reserved + 17 + 1 + read-write + + + REG_DBG_CH2_EN + Reserved + 18 + 1 + read-write + + + + + HPCORE_WDT_RESET_SOURCE0 + Reserved + 0xEC + 0x20 + 0x00000002 + + + REG_HPCORE0_WDT_RESET_SOURCE_SEL + 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0 + 0 + 1 + read-write + + + REG_HPCORE1_WDT_RESET_SOURCE_SEL + 1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1 + 1 + 1 + read-write + + + + + + + LP_HUK + LP_HUK Peripheral + HUK + 0x50114000 + + 0x0 + 0x1A8 + registers + + + LP_HUK + 20 + + + + CLK + HUK Generator clock gate control register + 0x4 + 0x20 + 0x00000001 + + + EN + Write 1 to force on register clock gate. + 0 + 1 + read-write + + + MEM_CG_FORCE_ON + Write 1 to force on memory clock gate. + 1 + 1 + read-write + + + + + INT_RAW + HUK Generator interrupt raw register, valid in level. + 0x8 + 0x20 + + + PREP_DONE_INT_RAW + The raw interrupt status bit for the huk_prep_done_int interrupt + 0 + 1 + read-only + + + PROC_DONE_INT_RAW + The raw interrupt status bit for the huk_proc_done_int interrupt + 1 + 1 + read-only + + + POST_DONE_INT_RAW + The raw interrupt status bit for the huk_post_done_int interrupt + 2 + 1 + read-only + + + + + INT_ST + HUK Generator interrupt status register. + 0xC + 0x20 + + + PREP_DONE_INT_ST + The masked interrupt status bit for the huk_prep_done_int interrupt + 0 + 1 + read-only + + + PROC_DONE_INT_ST + The masked interrupt status bit for the huk_proc_done_int interrupt + 1 + 1 + read-only + + + POST_DONE_INT_ST + The masked interrupt status bit for the huk_post_done_int interrupt + 2 + 1 + read-only + + + + + INT_ENA + HUK Generator interrupt enable register. + 0x10 + 0x20 + + + PREP_DONE_INT_ENA + The interrupt enable bit for the huk_prep_done_int interrupt + 0 + 1 + read-write + + + PROC_DONE_INT_ENA + The interrupt enable bit for the huk_proc_done_int interrupt + 1 + 1 + read-write + + + POST_DONE_INT_ENA + The interrupt enable bit for the huk_post_done_int interrupt + 2 + 1 + read-write + + + + + INT_CLR + HUK Generator interrupt clear register. + 0x14 + 0x20 + + + PREP_DONE_INT_CLR + Set this bit to clear the huk_prep_done_int interrupt + 0 + 1 + write-only + + + PROC_DONE_INT_CLR + Set this bit to clear the huk_proc_done_int interrupt + 1 + 1 + write-only + + + POST_DONE_INT_CLR + Set this bit to clear the huk_post_done_int interrupt + 2 + 1 + write-only + + + + + CONF + HUK Generator configuration register + 0x20 + 0x20 + + + MODE + Set this field to choose the huk process. 1: process huk generate mode. 0: process huk recovery mode. + 0 + 1 + read-write + + + + + START + HUK Generator control register + 0x24 + 0x20 + + + START + Write 1 to continue HUK Generator operation at LOAD/GAIN state. + 0 + 1 + write-only + + + CONTINUE + Write 1 to start HUK Generator at IDLE state. + 1 + 1 + write-only + + + + + STATE + HUK Generator state register + 0x28 + 0x20 + + + STATE + The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. + 0 + 2 + read-only + + + + + STATUS + HUK Generator HUK status register + 0x34 + 0x20 + + + STATUS + The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. 2: HUK is generated but invalid. 3: reserved. + 0 + 2 + read-only + + + RISK_LEVEL + The risk level of HUK. 0-6: the higher the risk level is, the more error bits there are in the PUF SRAM. 7: Error Level, HUK is invalid. + 2 + 3 + read-only + + + + + DATE + Version control register + 0xFC + 0x20 + 0x02305040 + + + DATE + HUK Generator version control register. + 0 + 28 + read-write + + + + + 384 + 0x1 + INFO_MEM[%s] + The memory that stores HUK info. + 0x100 + 0x8 + + + + + I2C0 + I2C (Inter-Integrated Circuit) Controller 0 + I2C + 0x500C4000 + + 0x0 + 0x90 + registers + + + I2C0 + 44 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL Clock. + 0x0 + 0x20 + + + SCL_LOW_PERIOD + Configures the low level width of the SCL Clock. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + SDA_FORCE_OUT + Configures the SDA output mode +1: Direct output, + +0: Open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + Configures the SCL output mode +1: Direct output, + +0: Open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + Configures the sample mode for SDA. +1: Sample SDA data on the SCL low level. + +0: Sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + MS_MODE + Configures the module as an I2C Master or Slave. +0: Slave + +1: Master + 4 + 1 + read-write + + + TRANS_START + Configures to start sending the data in txfifo for slave. +0: No effect + +1: Start + 5 + 1 + write-only + + + TX_LSB_FIRST + Configures to control the sending order for data needing to be sent. +1: send data from the least significant bit, + +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + Configures to control the storage order for received data. +1: receive data from the least significant bit + +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Configures whether to gate clock signal for registers. + +0: Force clock on for registers + +1: Support clock only when registers are read or written to by software. + 8 + 1 + read-write + + + ARBITRATION_EN + Configures to enable I2C bus arbitration detection. +0: No effect + +1: Enable + 9 + 1 + read-write + + + FSM_RST + Configures to reset the SCL_FSM. +0: No effect + +1: Reset + 10 + 1 + write-only + + + CONF_UPGATE + Configures this bit for synchronization +0: No effect + +1: Synchronize + 11 + 1 + write-only + + + SLV_TX_AUTO_START_EN + Configures to enable slave to send data automatically +0: Disable + +1: Enable + 12 + 1 + read-write + + + ADDR_10BIT_RW_CHECK_EN + Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. +0: Not check + +1: Check + 13 + 1 + read-write + + + ADDR_BROADCASTING_EN + Configures to support the 7bit general call function. +0: Not support + +1: Support + 14 + 1 + read-write + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + 0x0000C000 + + + RESP_REC + Represents the received ACK value in master mode or slave mode. +0: ACK, + +1: NACK. + 0 + 1 + read-only + + + SLAVE_RW + Represents the transfer direction in slave mode,. +1: Master reads from slave, + +0: Master writes to slave. + 1 + 1 + read-only + + + ARB_LOST + Represents whether the I2C controller loses control of SCL line. +0: No arbitration lost + +1: Arbitration lost + 3 + 1 + read-only + + + BUS_BUSY + Represents the I2C bus state. +1: The I2C bus is busy transferring data, + +0: The I2C bus is in idle state. + 4 + 1 + read-only + + + SLAVE_ADDRESSED + Represents whether the address sent by the master is equal to the address of the slave. +Valid only when the module is configured as an I2C Slave. +0: Not equal + +1: Equal + 5 + 1 + read-only + + + RXFIFO_CNT + Represents the number of data bytes to be sent. + 8 + 6 + read-only + + + STRETCH_CAUSE + Represents the cause of SCL clocking stretching in slave mode. +0: Stretching SCL low when the master starts to read data. + +1: Stretching SCL low when I2C TX FIFO is empty in slave mode. + +2: Stretching SCL low when I2C RX FIFO is full in slave mode. + 14 + 2 + read-only + + + TXFIFO_CNT + Represents the number of data bytes received in RAM. + 18 + 6 + read-only + + + SCL_MAIN_STATE_LAST + Represents the states of the I2C module state machine. +0: Idle, + +1: Address shift, + +2: ACK address, + +3: Rx data, + +4: Tx data, + +5: Send ACK, + +6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + Represents the states of the state machine used to produce SCL. +0: Idle, + +1: Start, + +2: Negative edge, + +3: Low, + +4: Positive edge, + +5: High, + +6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). +Measurement unit: i2c_sclk. + 0 + 5 + read-write + + + TIME_OUT_EN + Configures to enable time out control. +0: No effect + +1: Enable + 5 + 1 + read-write + + + + + SLAVE_ADDR + Local slave address setting + 0x10 + 0x20 + + + SLAVE_ADDR + Configure the slave address of I2C Slave. + 0 + 15 + read-write + + + ADDR_10BIT_EN + Configures to enable the slave 10-bit addressing mode in master mode. +0: No effect + +1: Enable + 31 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + Represents the offset address of the APB reading from RXFIFO + 0 + 5 + read-only + + + RXFIFO_WADDR + Represents the offset address of i2c module receiving data and writing to RXFIFO. + 5 + 5 + read-only + + + TXFIFO_RADDR + Represents the offset address of i2c module reading from TXFIFO. + 10 + 5 + read-only + + + TXFIFO_WADDR + Represents the offset address of APB bus writing to TXFIFO. + 15 + 5 + read-only + + + SLAVE_RW_POINT + Represents the offset address in the I2C Slave RAM addressed by I2C Master when in I2C slave mode. + 22 + 8 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x0000408B + + + RXFIFO_WM_THRHD + Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 5 + read-write + + + TXFIFO_WM_THRHD + Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 5 + read-write + + + NONFIFO_EN + Configures to enable APB nonfifo access. + 10 + 1 + read-write + + + FIFO_ADDR_CFG_EN + Configures to enable double addressing mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. +0: Disable + +1: Enable + 11 + 1 + read-write + + + RX_FIFO_RST + Configures to reset RXFIFO. +0: No effect + +1: Reset + 12 + 1 + read-write + + + TX_FIFO_RST + Configures to reset TXFIFO. +0: No effect + +1: Reset + 13 + 1 + read-write + + + FIFO_PRT_EN + Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. +0: No effect + +1: Enable + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + Represents the value of RXFIFO read data. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_RAW + The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_RAW + The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_RAW + The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Write 1 to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Write 1 to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Write 1 to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + SLAVE_STRETCH_INT_CLR + Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + write-only + + + GENERAL_CALL_INT_CLR + Write 1 to clear I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + write-only + + + SLAVE_ADDR_UNMATCH_INT_CLR + Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + 18 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + Write 1 to enable I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + Write 1 to enable I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + Write 1 to enable the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + Write 1 to enable the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + Write 1 to enable the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + Write 1 to enable the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + Write 1 to enable I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + Write 1 to enable I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + SLAVE_STRETCH_INT_ENA + Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-write + + + GENERAL_CALL_INT_ENA + Write 1 to enable I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-write + + + SLAVE_ADDR_UNMATCH_INT_ENA + Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + SLAVE_STRETCH_INT_ST + The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + 16 + 1 + read-only + + + GENERAL_CALL_INT_ST + The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. + 17 + 1 + read-only + + + SLAVE_ADDR_UNMATCH_INT_ST + The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + 18 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + Configures the time to hold the data after the falling edge of SCL. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + Configures the sample time after a positive SCL edge. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + Configures for how long SCL remains high in master mode. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + Configures the SCL_FSM's waiting period for SCL high level in master mode. +Measurement unit: i2c_sclk + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + Configures the delay after the STOP condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and SCL rising edge for a stop condition. +Measurement unit: i2c_sclk + 0x4C + 0x20 + 0x00000008 + + + TIME + Configures the time between the rising edge of SCL and the rising edge of SDA. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 0 + 4 + read-write + + + SDA_FILTER_THRES + Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 4 + 4 + read-write + + + SCL_FILTER_EN + Configures to enable the filter function for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + Configures to enable the filter function for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + COMD0 + I2C command register 0 + 0x58 + 0x20 + + + COMMAND0 + Configures command 0. It consists of three parts: +op_code is the command, +0: RSTART, +1: WRITE, +2: READ, +3: STOP, +4: END. + +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. + 0 + 14 + read-write + + + COMMAND0_DONE + Represents whether command 0 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD1 + I2C command register 1 + 0x5C + 0x20 + + + COMMAND1 + Configures command 1. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND1_DONE + Represents whether command 1 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD2 + I2C command register 2 + 0x60 + 0x20 + + + COMMAND2 + Configures command 2. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND2_DONE + Represents whether command 2 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD3 + I2C command register 3 + 0x64 + 0x20 + + + COMMAND3 + Configures command 3. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND3_DONE + Represents whether command 3 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD4 + I2C command register 4 + 0x68 + 0x20 + + + COMMAND4 + Configures command 4. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND4_DONE + Represents whether command 4 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD5 + I2C command register 5 + 0x6C + 0x20 + + + COMMAND5 + Configures command 5. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND5_DONE + Represents whether command 5 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD6 + I2C command register 6 + 0x70 + 0x20 + + + COMMAND6 + Configures command 6. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND6_DONE + Represents whether command 6 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD7 + I2C command register 7 + 0x74 + 0x20 + + + COMMAND7 + Configures command 7. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND7_DONE + Represents whether command 7 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configure the pulses of SCL generated in I2C master mode. +Valid when reg_scl_rst_slv_en is 1. +Measurement unit: i2c_sclk + 1 + 5 + read-write + + + SCL_PD_EN + Configures to power down the I2C output SCL line. +0: Not power down. + +1: Power down. +Valid only when reg_scl_force_out is 1. + 6 + 1 + read-write + + + SDA_PD_EN + Configures to power down the I2C output SDA line. +0: Not power down. + +1: Power down. +Valid only when reg_sda_force_out is 1. + 7 + 1 + read-write + + + + + SCL_STRETCH_CONF + Set SCL stretch of I2C slave + 0x84 + 0x20 + + + STRETCH_PROTECT_NUM + Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. +Measurement unit: i2c_sclk + 0 + 10 + read-write + + + SLAVE_SCL_STRETCH_EN + Configures to enable slave SCL stretch function. +0: Disable + +1: Enable +The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. + 10 + 1 + read-write + + + SLAVE_SCL_STRETCH_CLR + Configures to clear the I2C slave SCL stretch function. +0: No effect + +1: Clear + 11 + 1 + write-only + + + SLAVE_BYTE_ACK_CTL_EN + Configures to enable the function for slave to control ACK level. +0: Disable + +1: Enable + 12 + 1 + read-write + + + SLAVE_BYTE_ACK_LVL + Set the ACK level when slave controlling ACK level function enables. +0: Low level + +1: High level + 13 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201172 + + + DATE + Version control register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + Represents the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + Represents the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + I2C1 + I2C (Inter-Integrated Circuit) Controller 1 + 0x500C5000 + + I2C1 + 45 + + + + I2S0 + I2S (Inter-IC Sound) Controller 0 + I2S + 0x500C6000 + + 0x0 + 0x60 + registers + + + I2S0 + 27 + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_RAW + The raw interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + TX_DONE_INT_ST + The masked interrupt status bit for the i2s_tx_done_int interrupt + 1 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-only + + + TX_HUNG_INT_ST + The masked interrupt status bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + TX_DONE_INT_ENA + The interrupt enable bit for the i2s_tx_done_int interrupt + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + The interrupt enable bit for the i2s_tx_hung_int interrupt + 3 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the i2s_tx_done_int interrupt + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the i2s_tx_hung_int interrupt + 3 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00C0B600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 4 + 2 + read-write + + + RX_MONO + Set this bit to enable receiver in mono mode + 6 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 13 + 1 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 21 + 6 + read-write + + + + + TX_CONF + I2S TX configure register + 0x24 + 0x20 + 0x00C0F210 + + + TX_RESET + Set this bit to reset transmitter + 0 + 1 + write-only + + + TX_FIFO_RESET + Set this bit to reset Tx AFIFO + 1 + 1 + write-only + + + TX_START + Set this bit to start transmitting data + 2 + 1 + read-write + + + TX_SLAVE_MOD + Set this bit to enable slave transmitter mode + 3 + 1 + read-write + + + TX_STOP_EN + Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + 4 + 1 + read-write + + + TX_CHAN_EQUAL + 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. + 5 + 1 + read-write + + + TX_MONO + Set this bit to enable transmitter in mono mode + 6 + 1 + read-write + + + TX_BIG_ENDIAN + I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + TX_UPDATE + Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + TX_MONO_FST_VLD + 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. + 9 + 1 + read-write + + + TX_PCM_CONF + I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + TX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for transmitted data. + 12 + 1 + read-write + + + TX_MSB_SHIFT + Set this bit to enable transmitter in Phillips standard mode + 13 + 1 + read-write + + + TX_BCK_NO_DLY + 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. + 14 + 1 + read-write + + + TX_LEFT_ALIGN + 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. + 15 + 1 + read-write + + + TX_24_FILL_EN + 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode + 16 + 1 + read-write + + + TX_WS_IDLE_POL + 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + TX_BIT_ORDER + I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. + 18 + 1 + read-write + + + TX_TDM_EN + 1: Enable I2S TDM Tx mode . 0: Disable. + 19 + 1 + read-write + + + TX_PDM_EN + 1: Enable I2S PDM Tx mode . 0: Disable. + 20 + 1 + read-write + + + TX_BCK_DIV_NUM + Bit clock configuration bits in transmitter mode. + 21 + 6 + read-write + + + TX_CHAN_MOD + I2S transmitter channel mode configuration bits. + 27 + 3 + read-write + + + SIG_LOOPBACK + Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + 30 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x787BC000 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck + 0 + 9 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 19 + 8 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 27 + 5 + read-write + + + + + TX_CONF1 + I2S TX configure register 1 + 0x2C + 0x20 + 0x787BC000 + + + TX_TDM_WS_WIDTH + The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck + 0 + 9 + read-write + + + TX_BITS_MOD + Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 14 + 5 + read-write + + + TX_HALF_SAMPLE_BITS + I2S Tx half sample bits -1. + 19 + 8 + read-write + + + TX_TDM_CHAN_BITS + The Tx bit number for each channel minus 1in TDM mode. + 27 + 5 + read-write + + + + + TX_PCM2PDM_CONF + I2S TX PCM2PDM configuration register + 0x40 + 0x20 + 0x004AA004 + + + TX_PDM_HP_BYPASS + I2S TX PDM bypass hp filter or not. The option has been removed. + 0 + 1 + read-write + + + TX_PDM_SINC_OSR2 + I2S TX PDM OSR2 value + 1 + 4 + read-write + + + TX_PDM_PRESCALE + I2S TX PDM prescale for sigmadelta + 5 + 8 + read-write + + + TX_PDM_HP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 13 + 2 + read-write + + + TX_PDM_LP_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 15 + 2 + read-write + + + TX_PDM_SINC_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 17 + 2 + read-write + + + TX_PDM_SIGMADELTA_IN_SHIFT + I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 + 19 + 2 + read-write + + + TX_PDM_SIGMADELTA_DITHER2 + I2S TX PDM sigmadelta dither2 value + 21 + 1 + read-write + + + TX_PDM_SIGMADELTA_DITHER + I2S TX PDM sigmadelta dither value + 22 + 1 + read-write + + + TX_PDM_DAC_2OUT_EN + I2S TX PDM dac mode enable + 23 + 1 + read-write + + + TX_PDM_DAC_MODE_EN + I2S TX PDM dac 2channel enable + 24 + 1 + read-write + + + PCM2PDM_CONV_EN + I2S TX PDM Converter enable + 25 + 1 + read-write + + + + + TX_PCM2PDM_CONF1 + I2S TX PCM2PDM configuration register + 0x44 + 0x20 + 0x03F783C0 + + + TX_PDM_FP + I2S TX PDM Fp + 0 + 10 + read-write + + + TX_PDM_FS + I2S TX PDM Fs + 10 + 10 + read-write + + + TX_IIR_HP_MULT12_5 + The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) + 20 + 3 + read-write + + + TX_IIR_HP_MULT12_0 + The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) + 23 + 3 + read-write + + + + + RX_PDM2PCM_CONF + I2S RX configure register + 0x48 + 0x20 + 0xF8200000 + + + RX_PDM2PCM_EN + 1: Enable PDM2PCM RX mode. 0: DIsable. + 19 + 1 + read-write + + + RX_PDM_SINC_DSR_16_EN + Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. + 20 + 1 + read-write + + + RX_PDM2PCM_AMPLIFY_NUM + Configure PDM RX amplify number. + 21 + 4 + read-write + + + RX_PDM_HP_BYPASS + I2S PDM RX bypass hp filter or not. + 25 + 1 + read-write + + + RX_IIR_HP_MULT12_5 + The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + 26 + 3 + read-write + + + RX_IIR_HP_MULT12_0 + The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + 29 + 3 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x0000FFFF + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_PDM_CHAN2_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. + 2 + 1 + read-write + + + RX_TDM_PDM_CHAN3_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. + 3 + 1 + read-write + + + RX_TDM_PDM_CHAN4_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. + 4 + 1 + read-write + + + RX_TDM_PDM_CHAN5_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. + 5 + 1 + read-write + + + RX_TDM_PDM_CHAN6_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. + 6 + 1 + read-write + + + RX_TDM_PDM_CHAN7_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. + 7 + 1 + read-write + + + RX_TDM_CHAN8_EN + 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. + 8 + 1 + read-write + + + RX_TDM_CHAN9_EN + 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. + 9 + 1 + read-write + + + RX_TDM_CHAN10_EN + 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. + 10 + 1 + read-write + + + RX_TDM_CHAN11_EN + 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. + 11 + 1 + read-write + + + RX_TDM_CHAN12_EN + 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. + 12 + 1 + read-write + + + RX_TDM_CHAN13_EN + 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. + 13 + 1 + read-write + + + RX_TDM_CHAN14_EN + 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. + 14 + 1 + read-write + + + RX_TDM_CHAN15_EN + 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. + 15 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + TX_TDM_CTRL + I2S TX TDM mode control register + 0x54 + 0x20 + 0x0000FFFF + + + TX_TDM_CHAN0_EN + 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. + 0 + 1 + read-write + + + TX_TDM_CHAN1_EN + 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. + 1 + 1 + read-write + + + TX_TDM_CHAN2_EN + 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. + 2 + 1 + read-write + + + TX_TDM_CHAN3_EN + 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. + 3 + 1 + read-write + + + TX_TDM_CHAN4_EN + 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. + 4 + 1 + read-write + + + TX_TDM_CHAN5_EN + 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. + 5 + 1 + read-write + + + TX_TDM_CHAN6_EN + 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. + 6 + 1 + read-write + + + TX_TDM_CHAN7_EN + 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. + 7 + 1 + read-write + + + TX_TDM_CHAN8_EN + 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. + 8 + 1 + read-write + + + TX_TDM_CHAN9_EN + 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. + 9 + 1 + read-write + + + TX_TDM_CHAN10_EN + 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. + 10 + 1 + read-write + + + TX_TDM_CHAN11_EN + 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. + 11 + 1 + read-write + + + TX_TDM_CHAN12_EN + 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. + 12 + 1 + read-write + + + TX_TDM_CHAN13_EN + 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. + 13 + 1 + read-write + + + TX_TDM_CHAN14_EN + 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. + 14 + 1 + read-write + + + TX_TDM_CHAN15_EN + 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. + 15 + 1 + read-write + + + TX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + TX_TDM_SKIP_MSK_EN + When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. + 20 + 1 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_SD1_IN_DM + The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + RX_SD2_IN_DM + The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 8 + 2 + read-write + + + RX_SD3_IN_DM + The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 12 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + TX_TIMING + I2S TX timing control register + 0x5C + 0x20 + + + TX_SD_OUT_DM + The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + TX_SD1_OUT_DM + The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 4 + 2 + read-write + + + TX_WS_OUT_DM + The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + TX_BCK_OUT_DM + The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + TX_WS_IN_DM + The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + TX_BCK_IN_DM + The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + STATE + I2S TX status register + 0x6C + 0x20 + 0x00000001 + + + TX_IDLE + 1: i2s_tx is idle state. 0: i2s_tx is working. + 0 + 1 + read-only + + + + + ETM_CONF + I2S ETM configure register + 0x70 + 0x20 + 0x00010040 + + + ETM_TX_SEND_WORD_NUM + I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. + 0 + 10 + read-write + + + ETM_RX_RECEIVE_WORD_NUM + I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. + 10 + 10 + read-write + + + + + FIFO_CNT + I2S sync counter register + 0x74 + 0x20 + + + TX_FIFO_CNT + tx fifo counter value. + 0 + 31 + read-only + + + TX_FIFO_CNT_RST + Set this bit to reset tx fifo counter. + 31 + 1 + write-only + + + + + BCK_CNT + I2S sync counter register + 0x78 + 0x20 + + + TX_BCK_CNT + tx bck counter value. + 0 + 31 + read-only + + + TX_BCK_CNT_RST + Set this bit to reset tx bck counter. + 31 + 1 + write-only + + + + + CLK_GATE + Clock gate register + 0x7C + 0x20 + + + CLK_EN + set this bit to enable clock gate + 0 + 1 + read-write + + + + + DATE + Version control register + 0x80 + 0x20 + 0x02303240 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + I2S1 + I2S (Inter-IC Sound) Controller 1 + 0x500C7000 + + I2S1 + 28 + + + + I2S2 + I2S (Inter-IC Sound) Controller 2 + 0x500C8000 + + I2S2 + 29 + + + + I3C_MST + I3C Controller (Master) + I3C_MST + 0x500DA000 + + 0x0 + 0x90 + registers + + + I3C + 101 + + + + DEVICE_CTRL + DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities. + 0x0 + 0x20 + 0x00001020 + + + REG_BA_INCLUDE + This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed) + 1 + 1 + read-write + + + REG_TRANS_START + Transfer Start + 2 + 1 + read-write + + + REG_CLK_EN + NA + 3 + 1 + read-write + + + REG_IBI_RSTART_TRANS_EN + NA + 4 + 1 + read-write + + + REG_AUTO_DIS_IBI_EN + NA + 5 + 1 + read-write + + + REG_DMA_RX_EN + NA + 6 + 1 + read-write + + + REG_DMA_TX_EN + NA + 7 + 1 + read-write + + + REG_MULTI_SLV_SINGLE_CCC_EN + 0: rx high bit first, 1: rx low bit first + 8 + 1 + read-write + + + REG_RX_BIT_ORDER + 0: rx low byte fist, 1: rx high byte first + 9 + 1 + read-write + + + REG_RX_BYTE_ORDER + NA + 10 + 1 + read-write + + + REG_SCL_PULLUP_FORCE_EN + This bit is used to force scl_pullup_en + 11 + 1 + read-write + + + REG_SCL_OE_FORCE_EN + This bit is used to force scl_oe + 12 + 1 + read-write + + + REG_SDA_PP_RD_PULLUP_EN + NA + 13 + 1 + read-write + + + REG_SDA_RD_TBIT_HLVL_PULLUP_EN + NA + 14 + 1 + read-write + + + REG_SDA_PP_WR_PULLUP_EN + NA + 15 + 1 + read-write + + + REG_DATA_BYTE_CNT_UNLATCH + 1: read current real-time updated value 0: read latch data byte cnt value + 16 + 1 + read-write + + + REG_MEM_CLK_FORCE_ON + 1: dev characteristic and address table memory clk date force on . 0 : clock gating by rd/wr. + 17 + 1 + read-write + + + + + BUFFER_THLD_CTRL + In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt. + 0x1C + 0x20 + 0x00041041 + + + REG_CMD_BUF_EMPTY_THLD + Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt. + 0 + 4 + read-write + + + REG_RESP_BUF_THLD + Response Buffer Threshold Value is used to control the number of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR. + 6 + 3 + read-write + + + REG_IBI_DATA_BUF_THLD + In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI data entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt. + 12 + 3 + read-write + + + REG_IBI_STATUS_BUF_THLD + NA + 18 + 3 + read-write + + + + + DATA_BUFFER_THLD_CTRL + NA + 0x20 + 0x20 + 0x00000009 + + + REG_TX_DATA_BUF_THLD + Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31 + 0 + 3 + read-write + + + REG_RX_DATA_BUF_THLD + Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31 + 3 + 3 + read-write + + + + + IBI_NOTIFY_CTRL + NA + 0x24 + 0x20 + + + REG_NOTIFY_SIR_REJECTED + Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl. + 2 + 1 + read-write + + + + + IBI_SIR_REQ_PAYLOAD + NA + 0x28 + 0x20 + + + REG_SIR_REQ_PAYLOAD + NA + 0 + 32 + read-write + + + + + IBI_SIR_REQ_REJECT + NA + 0x2C + 0x20 + + + REG_SIR_REQ_REJECT + The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC + 0 + 32 + read-write + + + + + INT_CLR + NA + 0x30 + 0x20 + + + TX_DATA_BUF_THLD_INT_CLR + NA + 0 + 1 + write-only + + + RX_DATA_BUF_THLD_INT_CLR + NA + 1 + 1 + write-only + + + IBI_STATUS_THLD_INT_CLR + NA + 2 + 1 + write-only + + + CMD_BUF_EMPTY_THLD_INT_CLR + NA + 3 + 1 + write-only + + + RESP_READY_INT_CLR + NA + 4 + 1 + write-only + + + NXT_CMD_REQ_ERR_INT_CLR + NA + 5 + 1 + write-only + + + TRANSFER_ERR_INT_CLR + NA + 6 + 1 + write-only + + + TRANSFER_COMPLETE_INT_CLR + NA + 7 + 1 + write-only + + + COMMAND_DONE_INT_CLR + NA + 8 + 1 + write-only + + + DETECT_START_INT_CLR + NA + 9 + 1 + write-only + + + RESP_BUF_OVF_INT_CLR + NA + 10 + 1 + write-only + + + IBI_DATA_BUF_OVF_INT_CLR + NA + 11 + 1 + write-only + + + IBI_STATUS_BUF_OVF_INT_CLR + NA + 12 + 1 + write-only + + + IBI_HANDLE_DONE_INT_CLR + NA + 13 + 1 + write-only + + + IBI_DETECT_INT_CLR + NA + 14 + 1 + write-only + + + CMD_CCC_MISMATCH_INT_CLR + NA + 15 + 1 + write-only + + + + + INT_RAW + NA + 0x34 + 0x20 + 0x00000008 + + + TX_DATA_BUF_THLD_INT_RAW + NA + 0 + 1 + read-write + + + RX_DATA_BUF_THLD_INT_RAW + NA + 1 + 1 + read-write + + + IBI_STATUS_THLD_INT_RAW + NA + 2 + 1 + read-write + + + CMD_BUF_EMPTY_THLD_INT_RAW + NA + 3 + 1 + read-write + + + RESP_READY_INT_RAW + NA + 4 + 1 + read-write + + + NXT_CMD_REQ_ERR_INT_RAW + NA + 5 + 1 + read-write + + + TRANSFER_ERR_INT_RAW + NA + 6 + 1 + read-write + + + TRANSFER_COMPLETE_INT_RAW + NA + 7 + 1 + read-write + + + COMMAND_DONE_INT_RAW + NA + 8 + 1 + read-write + + + DETECT_START_INT_RAW + NA + 9 + 1 + read-write + + + RESP_BUF_OVF_INT_RAW + NA + 10 + 1 + read-write + + + IBI_DATA_BUF_OVF_INT_RAW + NA + 11 + 1 + read-write + + + IBI_STATUS_BUF_OVF_INT_RAW + NA + 12 + 1 + read-write + + + IBI_HANDLE_DONE_INT_RAW + NA + 13 + 1 + read-write + + + IBI_DETECT_INT_RAW + NA + 14 + 1 + read-write + + + CMD_CCC_MISMATCH_INT_RAW + NA + 15 + 1 + read-write + + + + + INT_ST + NA + 0x38 + 0x20 + + + TX_DATA_BUF_THLD_INT_ST + This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value. + 0 + 1 + read-only + + + RX_DATA_BUF_THLD_INT_ST + This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value. + 1 + 1 + read-only + + + IBI_STATUS_THLD_INT_ST + Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value. + 2 + 1 + read-only + + + CMD_BUF_EMPTY_THLD_INT_ST + This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value. + 3 + 1 + read-only + + + RESP_READY_INT_ST + This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value. + 4 + 1 + read-only + + + NXT_CMD_REQ_ERR_INT_ST + This interrupt is generated if toc is 0(master will restart next command), but command buf is empty. + 5 + 1 + read-only + + + TRANSFER_ERR_INT_ST + This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1. + 6 + 1 + read-only + + + TRANSFER_COMPLETE_INT_ST + NA + 7 + 1 + read-only + + + COMMAND_DONE_INT_ST + NA + 8 + 1 + read-only + + + DETECT_START_INT_ST + NA + 9 + 1 + read-only + + + RESP_BUF_OVF_INT_ST + NA + 10 + 1 + read-only + + + IBI_DATA_BUF_OVF_INT_ST + NA + 11 + 1 + read-only + + + IBI_STATUS_BUF_OVF_INT_ST + NA + 12 + 1 + read-only + + + IBI_HANDLE_DONE_INT_ST + NA + 13 + 1 + read-only + + + IBI_DETECT_INT_ST + NA + 14 + 1 + read-only + + + CMD_CCC_MISMATCH_INT_ST + NA + 15 + 1 + read-only + + + + + INT_ST_ENA + The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set. + 0x3C + 0x20 + + + TX_DATA_BUF_THLD_INT_ENA + Transmit Buffer threshold status enable. + 0 + 1 + read-write + + + RX_DATA_BUF_THLD_INT_ENA + Receive Buffer threshold status enable. + 1 + 1 + read-write + + + IBI_STATUS_THLD_INT_ENA + Only used in master mode. IBI Buffer threshold status enable. + 2 + 1 + read-write + + + CMD_BUF_EMPTY_THLD_INT_ENA + Command buffer ready status enable. + 3 + 1 + read-write + + + RESP_READY_INT_ENA + Response buffer ready status enable. + 4 + 1 + read-write + + + NXT_CMD_REQ_ERR_INT_ENA + next command request error status enable + 5 + 1 + read-write + + + TRANSFER_ERR_INT_ENA + Transfer error status enable + 6 + 1 + read-write + + + TRANSFER_COMPLETE_INT_ENA + NA + 7 + 1 + read-write + + + COMMAND_DONE_INT_ENA + NA + 8 + 1 + read-write + + + DETECT_START_INT_ENA + NA + 9 + 1 + read-write + + + RESP_BUF_OVF_INT_ENA + NA + 10 + 1 + read-write + + + IBI_DATA_BUF_OVF_INT_ENA + NA + 11 + 1 + read-write + + + IBI_STATUS_BUF_OVF_INT_ENA + NA + 12 + 1 + read-write + + + IBI_HANDLE_DONE_INT_ENA + NA + 13 + 1 + read-write + + + IBI_DETECT_INT_ENA + NA + 14 + 1 + read-write + + + CMD_CCC_MISMATCH_INT_ENA + NA + 15 + 1 + read-write + + + + + RESET_CTRL + NA + 0x44 + 0x20 + + + REG_CORE_SOFT_RST + NA + 0 + 1 + write-only + + + REG_CMD_BUF_RST + NA + 1 + 1 + read-write + + + REG_RESP_BUF_RST + NA + 2 + 1 + read-write + + + REG_TX_DATA_BUF_BUF_RST + NA + 3 + 1 + read-write + + + REG_RX_DATA_BUF_RST + NA + 4 + 1 + read-write + + + REG_IBI_DATA_BUF_RST + NA + 5 + 1 + read-write + + + REG_IBI_STATUS_BUF_RST + NA + 6 + 1 + read-write + + + + + BUFFER_STATUS_LEVEL + BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller. + 0x48 + 0x20 + 0x00000010 + + + CMD_BUF_EMPTY_CNT + Command Buffer Empty Locations contains the number of empty locations in the command buffer. + 0 + 5 + read-only + + + RESP_BUF_CNT + Response Buffer Level Value contains the number of valid data entries in the response buffer. + 8 + 4 + read-only + + + IBI_DATA_BUF_CNT + IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This is field is used in master mode. + 16 + 4 + read-only + + + IBI_STATUS_BUF_CNT + IBI Buffer Status Count contains the number of IBI status entries in the IBI Buffer. This field is used in master mode. + 24 + 4 + read-only + + + + + DATA_BUFFER_STATUS_LEVEL + DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller. + 0x4C + 0x20 + 0x00000020 + + + TX_DATA_BUF_EMPTY_CNT + Transmit Buffer Empty Level Value contains the number of empty locations in the transmit Buffer. + 0 + 6 + read-only + + + RX_DATA_BUF_CNT + Receive Buffer Level value contains the number of valid data entries in the receive buffer. + 16 + 6 + read-only + + + + + PRESENT_STATE0 + NA + 0x50 + 0x20 + 0x00000003 + + + SDA_LVL + This bit is used to check the SCL line level to recover from error and for debugging. This bit reflects the value of synchronized scl_in_a. + 0 + 1 + read-only + + + SCL_LVL + This bit is used to check the SDA line level to recover from error and for debugging. This bit reflects the value of synchronized sda_in_a. + 1 + 1 + read-only + + + BUS_BUSY + NA + 2 + 1 + read-only + + + BUS_FREE + NA + 3 + 1 + read-only + + + CMD_TID + NA + 9 + 4 + read-only + + + SCL_GEN_FSM_STATE + NA + 13 + 3 + read-only + + + IBI_EV_HANDLE_FSM_STATE + NA + 16 + 3 + read-only + + + I2C_MODE_FSM_STATE + NA + 19 + 3 + read-only + + + SDR_MODE_FSM_STATE + NA + 22 + 4 + read-only + + + DAA_MODE_FSM_STATE + Reflects whether the Master Controller is in IDLE or not. This bit will be set when all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the Master State machine is in idle state. 0X0: not in idle 0x1: in idle + 26 + 3 + read-only + + + MAIN_FSM_STATE + NA + 29 + 3 + read-only + + + + + PRESENT_STATE1 + NA + 0x54 + 0x20 + + + DATA_BYTE_CNT + Present transfer data byte cnt: tx data byte cnt if write rx data byte cnt if read ibi data byte cnt if IBI handle. + 0 + 16 + read-only + + + + + DEVICE_TABLE + Pointer for Device Address Table + 0x58 + 0x20 + + + REG_DCT_DAA_INIT_INDEX + Reserved + 0 + 4 + read-write + + + REG_DAT_DAA_INIT_INDEX + NA + 4 + 4 + read-write + + + PRESENT_DCT_INDEX + NA + 8 + 4 + read-only + + + PRESENT_DAT_INDEX + NA + 12 + 4 + read-only + + + + + TIME_OUT_VALUE + NA + 0x5C + 0x20 + 0x00410410 + + + REG_RESP_BUF_TO_VALUE + NA + 0 + 5 + read-write + + + REG_RESP_BUF_TO_EN + NA + 5 + 1 + read-write + + + REG_IBI_DATA_BUF_TO_VALUE + NA + 6 + 5 + read-write + + + REG_IBI_DATA_BUF_TO_EN + NA + 11 + 1 + read-write + + + REG_IBI_STATUS_BUF_TO_VALUE + NA + 12 + 5 + read-write + + + REG_IBI_STATUS_BUF_TO_EN + NA + 17 + 1 + read-write + + + REG_RX_DATA_BUF_TO_VALUE + NA + 18 + 5 + read-write + + + REG_RX_DATA_BUF_TO_EN + NA + 23 + 1 + read-write + + + + + SCL_I3C_MST_OD_TIME + NA + 0x60 + 0x20 + 0x00050019 + + + REG_I3C_MST_OD_LOW_PERIOD + SCL Open-Drain low count for I3C transfers targeted to I3C devices. + 0 + 16 + read-write + + + REG_I3C_MST_OD_HIGH_PERIOD + SCL Open-Drain High count for I3C transfers targeted to I3C devices. + 16 + 16 + read-write + + + + + SCL_I3C_MST_PP_TIME + NA + 0x64 + 0x20 + 0x00050005 + + + REG_I3C_MST_PP_LOW_PERIOD + NA + 0 + 8 + read-write + + + REG_I3C_MST_PP_HIGH_PERIOD + NA + 16 + 8 + read-write + + + + + SCL_I2C_FM_TIME + NA + 0x68 + 0x20 + 0x004B00A3 + + + REG_I2C_FM_LOW_PERIOD + NA + 0 + 16 + read-write + + + REG_I2C_FM_HIGH_PERIOD + The SCL open-drain low count timing for I2C Fast Mode transfers. + 16 + 16 + read-write + + + + + SCL_I2C_FMP_TIME + NA + 0x6C + 0x20 + 0x0021003F + + + REG_I2C_FMP_LOW_PERIOD + NA + 0 + 16 + read-write + + + REG_I2C_FMP_HIGH_PERIOD + NA + 16 + 8 + read-write + + + + + SCL_EXT_LOW_TIME + NA + 0x70 + 0x20 + + + REG_I3C_MST_EXT_LOW_PERIOD1 + NA + 0 + 8 + read-write + + + REG_I3C_MST_EXT_LOW_PERIOD2 + NA + 8 + 8 + read-write + + + REG_I3C_MST_EXT_LOW_PERIOD3 + NA + 16 + 8 + read-write + + + REG_I3C_MST_EXT_LOW_PERIOD4 + NA + 24 + 8 + read-write + + + + + SDA_SAMPLE_TIME + NA + 0x74 + 0x20 + + + REG_SDA_OD_SAMPLE_TIME + It is used to adjust sda sample point when scl high under open drain speed + 0 + 9 + read-write + + + REG_SDA_PP_SAMPLE_TIME + It is used to adjust sda sample point when scl high under push pull speed + 9 + 5 + read-write + + + + + SDA_HOLD_TIME + NA + 0x78 + 0x20 + 0x00000001 + + + REG_SDA_OD_TX_HOLD_TIME + It is used to adjust sda drive point after scl neg under open drain speed + 0 + 9 + read-write + + + REG_SDA_PP_TX_HOLD_TIME + It is used to adjust sda dirve point after scl neg under push pull speed + 9 + 5 + read-write + + + + + SCL_START_HOLD + NA + 0x7C + 0x20 + 0x00000008 + + + REG_SCL_START_HOLD_TIME + I2C_SCL_START_HOLD_TIME + 0 + 9 + read-write + + + REG_START_DET_HOLD_TIME + NA + 9 + 2 + read-write + + + + + SCL_RSTART_SETUP + NA + 0x80 + 0x20 + 0x00000008 + + + REG_SCL_RSTART_SETUP_TIME + I2C_SCL_RSTART_SETUP_TIME + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + NA + 0x84 + 0x20 + 0x00000008 + + + REG_SCL_STOP_HOLD_TIME + I2C_SCL_STOP_HOLD_TIME + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + NA + 0x88 + 0x20 + 0x00000008 + + + REG_SCL_STOP_SETUP_TIME + I2C_SCL_STOP_SETUP_TIME + 0 + 9 + read-write + + + + + BUS_FREE_TIME + NA + 0x90 + 0x20 + 0x00000005 + + + REG_BUS_FREE_TIME + I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing. + 0 + 16 + read-write + + + + + SCL_TERMN_T_EXT_LOW_TIME + NA + 0x94 + 0x20 + 0x00000002 + + + REG_I3C_MST_TERMN_T_EXT_LOW_TIME + NA + 0 + 8 + read-write + + + + + VER_ID + NA + 0xA0 + 0x20 + 0x20230504 + + + REG_I3C_MST_VER_ID + This field indicates the controller current release number that is read by an application. + 0 + 32 + read-write + + + + + VER_TYPE + NA + 0xA4 + 0x20 + + + REG_I3C_MST_VER_TYPE + This field indicates the controller current release type that is read by an application. + 0 + 32 + read-write + + + + + FPGA_DEBUG_PROBE + NA + 0xAC + 0x20 + 0x00000001 + + + REG_I3C_MST_FPGA_DEBUG_PROBE + For Debug Probe Test on FPGA + 0 + 32 + read-write + + + + + RND_ECO_CS + NA + 0xB0 + 0x20 + + + REG_RND_ECO_EN + NA + 0 + 1 + read-write + + + RND_ECO_RESULT + NA + 1 + 1 + read-only + + + + + RND_ECO_LOW + NA + 0xB4 + 0x20 + + + REG_RND_ECO_LOW + NA + 0 + 32 + read-write + + + + + RND_ECO_HIGH + NA + 0xB8 + 0x20 + 0x0000FFFF + + + REG_RND_ECO_HIGH + NA + 0 + 32 + read-write + + + + + + + I3C_MST_MEM + I3C_MST_MEM Peripheral + I3C_MST_MEM + 0x500DA000 + + 0x0 + 0x108 + registers + + + + COMMAND_BUF_PORT + NA + 0x8 + 0x20 + + + REG_COMMAND + Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus. + 0 + 32 + read-write + + + + + RESPONSE_BUF_PORT + NA + 0xC + 0x20 + + + RESPONSE + The Response Buffer can be read through this register. The response status for each Command is written into the Response Buffer by the controller if ROC (Response On Completion) bit is set or if transfer error has occurred. The response buffer can be read through this register. + 0 + 32 + read-only + + + + + RX_DATA_PORT + NA + 0x10 + 0x20 + + + RX_DATA_PORT + Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. + 0 + 32 + read-only + + + + + TX_DATA_PORT + NA + 0x14 + 0x20 + + + REG_TX_DATA_PORT + Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor. + 0 + 32 + read-write + + + + + IBI_STATUS_BUF + In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data) + 0x18 + 0x20 + + + DATA_LENGTH + This field represents the length of data received along with IBI, in bytes. + 0 + 8 + read-only + + + IBI_ID + IBI Identifier. The byte received after START which includes the address the R/W bit: Device address and R/W bit in case of Slave Interrupt or Master Request. + 8 + 8 + read-only + + + IBI_STS + IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI Data is always packed in4-byte aligned and put to the IBI Buffer. This register When read from, reads the data from the IBI buffer. IBI Status register when read from, returns the data from the IBI Buffer and indicates how the controller responded to incoming IBI(SIR, MR and HJ). + 28 + 1 + read-only + + + + + IBI_DATA_BUF + NA + 0x40 + 0x20 + + + IBI_DATA + NA + 0 + 32 + read-only + + + + + DEV_ADDR_TABLE1_LOC + NA + 0xC0 + 0x20 + + + REG_DAT_DEV1_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV1_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV1_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV1_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE2_LOC + NA + 0xC4 + 0x20 + + + REG_DAT_DEV2_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV2_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV2_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV2_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE3_LOC + NA + 0xC8 + 0x20 + + + REG_DAT_DEV3_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV3_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV3_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV3_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE4_LOC + NA + 0xCC + 0x20 + + + REG_DAT_DEV4_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV4_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV4_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV4_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE5_LOC + NA + 0xD0 + 0x20 + + + REG_DAT_DEV5_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV5_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV5_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV5_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE6_LOC + NA + 0xD4 + 0x20 + + + REG_DAT_DEV6_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV6_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV6_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV6_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE7_LOC + NA + 0xD8 + 0x20 + + + REG_DAT_DEV7_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV7_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV7_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV7_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE8_LOC + NA + 0xDC + 0x20 + + + REG_DAT_DEV8_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV8_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV8_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV8_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE9_LOC + NA + 0xE0 + 0x20 + + + REG_DAT_DEV9_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV9_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV9_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV9_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE10_LOC + NA + 0xE4 + 0x20 + + + REG_DAT_DEV10_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV10_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV10_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV10_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE11_LOC + NA + 0xE8 + 0x20 + + + REG_DAT_DEV11_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV11_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV11_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV11_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_ADDR_TABLE12_LOC + NA + 0xEC + 0x20 + + + REG_DAT_DEV12_STATIC_ADDR + NA + 0 + 7 + read-write + + + REG_DAT_DEV12_DYNAMIC_ADDR + Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address. + 16 + 8 + read-write + + + REG_DAT_DEV12_NACK_RETRY_CNT + This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state. + 29 + 2 + read-write + + + REG_DAT_DEV12_I2C + Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + 31 + 1 + read-write + + + + + DEV_CHAR_TABLE1_LOC1 + NA + 0x100 + 0x20 + + + DCT_DEV1_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE1_LOC2 + NA + 0x104 + 0x20 + + + DCT_DEV1_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE1_LOC3 + NA + 0x108 + 0x20 + + + DCT_DEV1_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE1_LOC4 + NA + 0x10C + 0x20 + + + DCT_DEV1_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC1 + NA + 0x110 + 0x20 + + + DCT_DEV2_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC2 + NA + 0x114 + 0x20 + + + DCT_DEV2_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC3 + NA + 0x118 + 0x20 + + + DCT_DEV2_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE2_LOC4 + NA + 0x11C + 0x20 + + + DCT_DEV2_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC1 + NA + 0x120 + 0x20 + + + DCT_DEV3_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC2 + NA + 0x124 + 0x20 + + + DCT_DEV3_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC3 + NA + 0x128 + 0x20 + + + DCT_DEV3_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE3_LOC4 + NA + 0x12C + 0x20 + + + DCT_DEV3_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC1 + NA + 0x130 + 0x20 + + + DCT_DEV4_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC2 + NA + 0x134 + 0x20 + + + DCT_DEV4_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC3 + NA + 0x138 + 0x20 + + + DCT_DEV4_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE4_LOC4 + NA + 0x13C + 0x20 + + + DCT_DEV4_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC1 + NA + 0x140 + 0x20 + + + DCT_DEV5_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC2 + NA + 0x144 + 0x20 + + + DCT_DEV5_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC3 + NA + 0x148 + 0x20 + + + DCT_DEV5_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE5_LOC4 + NA + 0x14C + 0x20 + + + DCT_DEV5_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC1 + NA + 0x150 + 0x20 + + + DCT_DEV6_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC2 + NA + 0x154 + 0x20 + + + DCT_DEV6_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC3 + NA + 0x158 + 0x20 + + + DCT_DEV6_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE6_LOC4 + NA + 0x15C + 0x20 + + + DCT_DEV6_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC1 + NA + 0x160 + 0x20 + + + DCT_DEV7_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC2 + NA + 0x164 + 0x20 + + + DCT_DEV7_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC3 + NA + 0x168 + 0x20 + + + DCT_DEV7_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE7_LOC4 + NA + 0x16C + 0x20 + + + DCT_DEV7_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC1 + NA + 0x170 + 0x20 + + + DCT_DEV8_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC2 + NA + 0x174 + 0x20 + + + DCT_DEV8_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC3 + NA + 0x178 + 0x20 + + + DCT_DEV8_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE8_LOC4 + NA + 0x17C + 0x20 + + + DCT_DEV8_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC1 + NA + 0x180 + 0x20 + + + DCT_DEV9_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC2 + NA + 0x184 + 0x20 + + + DCT_DEV9_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC3 + NA + 0x188 + 0x20 + + + DCT_DEV9_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE9_LOC4 + NA + 0x18C + 0x20 + + + DCT_DEV9_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC1 + NA + 0x190 + 0x20 + + + DCT_DEV10_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC2 + NA + 0x194 + 0x20 + + + DCT_DEV10_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC3 + NA + 0x198 + 0x20 + + + DCT_DEV10_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE10_LOC4 + NA + 0x19C + 0x20 + + + DCT_DEV10_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC1 + NA + 0x1A0 + 0x20 + + + DCT_DEV11_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC2 + NA + 0x1A4 + 0x20 + + + DCT_DEV11_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC3 + NA + 0x1A8 + 0x20 + + + DCT_DEV11_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE11_LOC4 + NA + 0x1AC + 0x20 + + + DCT_DEV11_LOC4 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC1 + NA + 0x1B0 + 0x20 + + + DCT_DEV12_LOC1 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC2 + NA + 0x1B4 + 0x20 + + + DCT_DEV12_LOC2 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC3 + NA + 0x1B8 + 0x20 + + + DCT_DEV12_LOC3 + NA + 0 + 32 + read-only + + + + + DEV_CHAR_TABLE12_LOC4 + NA + 0x1BC + 0x20 + + + DCT_DEV12_LOC4 + NA + 0 + 32 + read-only + + + + + + + I3C_SLV + I3C Controller (Slave) + I3C_SLV + 0x500DB000 + + 0x0 + 0x40 + registers + + + I3C_SLV + 102 + + + + CONFIG + NA + 0x4 + 0x20 + 0x002F0001 + + + SLVENA + 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master + 0 + 1 + read-write + + + NACK + 1:the slave will NACK all requests to it except CCC broadcast. This should be used with caution as the Master may determine the slave is missing if overused. + 1 + 1 + read-write + + + MATCHSS + 1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This allows START and STOP to be used to detect end of a message to /from this slave. + 2 + 1 + read-write + + + S0IGNORE + If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an Exit Pattern. This should only be used when the bus will not use HDR. + 3 + 1 + read-write + + + DDROK + NA + 4 + 1 + read-write + + + IDRAND + NA + 8 + 1 + read-write + + + OFFLINE + NA + 9 + 1 + read-write + + + BAMATCH + Bus Available condition match value for current ???Slow clock???. This provides the count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low when the Master is not doing so. The max width , and so max value, is controlled by the block. Only if enabled for events such IBI or MR or HJ, and if enabled to provide this as a register. With is limited to CLK_SLOW_BITS + 16 + 8 + read-write + + + SADDR + If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled to use one and to be provided by SW. Block may provide in HW as well. + 25 + 7 + read-write + + + + + STATUS + NA + 0x8 + 0x20 + + + STNOTSTOP + Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also set when busy. Note that this can also be true from an S0 or S1 error, which waits for an Exit Pattern. + 0 + 1 + read-only + + + STMSG + Is 1 if this bus Slave is listening to the bus traffic or repsonding, If STNOSTOP=1, then this will be 0 when a non-matching address seen until next respeated START it STOP. + 1 + 1 + read-only + + + STCCCH + Is 1 if a CCC message is being handled automatically. + 2 + 1 + read-only + + + STREQRD + 1 if the req in process is an sdr read from this slave or an IBI is being pushed out, + 3 + 1 + read-only + + + STREQWR + NA + 4 + 1 + read-only + + + STDAA + NA + 5 + 1 + read-only + + + STHDR + NA + 6 + 1 + read-only + + + START + NA + 8 + 1 + read-write + + + MATCHED + NA + 9 + 1 + read-write + + + STOP + NA + 10 + 1 + read-write + + + RXPEND + Receiving a message from master,which is not being handled by block(not a CCC internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will self-clear if data is read(FIFO and non-FIFO) + 11 + 1 + read-only + + + TXNOTFULL + Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is enabled for TX, it will also be signaled to provide more. + 12 + 1 + read-only + + + DACHG + The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in that state of being valid or none. Actual DA can be seen in the DYNADDR register. Note that this will also be used when MAP Auto feature is configured. This will be changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate if last change was due to Auto MAP. + 13 + 1 + read-write + + + CCC + A common -command-code(CCC), not handled by block, has been received. This acts differently between: *Broadcasted ones, which will then also correspond with RXPEND and the 1st byte will be the CCC(command) . *Direct ones, which may never be directed to this device. If it is, then the TXSEND or RXPEND will be triggered with this end the RXPEND will contain the command. + 14 + 1 + read-write + + + ERRWARN + NA + 15 + 1 + read-only + + + HDRMATCH + NA + 16 + 1 + read-write + + + + + CTRL + NA + 0xC + 0x20 + + + SLV_EVENT + If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1. + 0 + 2 + read-write + + + EXTDATA + reserved + 3 + 1 + read-write + + + MAPIDX + Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic Address, or can be any valid index. + 4 + 4 + read-write + + + IBIDATA + Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is required. + 8 + 8 + read-write + + + PENDINT + Should be set to the pending interrupt that GETSTATUS CCC will return. This should be maintained by the application if used and configured, as the Master will read this. If not configured, the GETSTATUS field will return 1 if an IBI is pending, and 0 otherwise. + 16 + 4 + read-write + + + ACTSTATE + NA + 20 + 2 + read-write + + + VENDINFO + NA + 24 + 8 + read-write + + + + + INTSET + INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor) + 0x10 + 0x20 + + + STOP_ENA + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 + 1 + read-write + + + RXPEND_ENA + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 + 1 + read-write + + + TXSEND_ENA + NA + 12 + 1 + read-write + + + + + INTCLR + NA + 0x14 + 0x20 + + + STOP_CLR + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 + 1 + write-only + + + RXPEND_CLR + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 + 1 + write-only + + + TXSEND_CLR + NA + 12 + 1 + write-only + + + + + INTMASKED + NA + 0x18 + 0x20 + + + STOP_MASK + Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped. + 10 + 1 + read-only + + + RXPEND_MASK + Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end. + 11 + 1 + read-only + + + TXSEND_MASK + NA + 12 + 1 + read-only + + + + + DATACTRL + NA + 0x2C + 0x20 + 0x000000B0 + + + FLUSHTB + Flushes the from-bus buffer/FIFO. Not normally used + 0 + 1 + write-only + + + FLUSHFB + Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message prematurely + 1 + 1 + write-only + + + UNLOCK + If this bit is not written 1, the register bits from 7 to 4 are not changed on write. + 3 + 1 + write-only + + + TXTRIG + Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 + 4 + 2 + read-write + + + RXTRIG + Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3 + 6 + 2 + read-write + + + TXCOUNT + NA + 16 + 5 + read-only + + + RXCOUNT + NA + 24 + 5 + read-only + + + TXFULL + NA + 30 + 1 + read-only + + + RXEMPTY + NA + 31 + 1 + read-only + + + + + WDATAB + NA + 0x30 + 0x20 + + + WDATAB + NA + 0 + 8 + write-only + + + WDATA_END + NA + 8 + 1 + write-only + + + + + WDATABE + NA + 0x34 + 0x20 + + + WDATABE + NA + 0 + 8 + write-only + + + + + RDARAB + Read Byte Data (from-bus) register + 0x40 + 0x20 + + + DATA0 + This register allows reading a byte from the bus unless external FIFO is used. A byte should not be read unless there is data waiting, as indicated by the RXPEND bit being set in the STATUS register + 0 + 8 + read-only + + + + + RDATAH + Read Half-word Data (from-bus) register + 0x48 + 0x20 + + + DATA_LSB + NA + 0 + 8 + read-only + + + DATA_MSB + This register allows reading a Half-word (byte pair) from the bus unless external FIFO is used. A Half-word should not be read unless there is at least 2 bytes of data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space in the DATACTRL register + 8 + 8 + read-only + + + + + CAPABILITIES2 + NA + 0x5C + 0x20 + 0x00000100 + + + CAPABLITIES2 + NA + 0 + 32 + read-only + + + + + CAPABILITIES + NA + 0x60 + 0x20 + 0x7C13FC1C + + + CAPABLITIES + NA + 0 + 32 + read-only + + + + + IDPARTNO + NA + 0x6C + 0x20 + + + PARTNO + NA + 0 + 32 + read-write + + + + + IDEXT + NA + 0x70 + 0x20 + + + IDEXT + NA + 0 + 32 + read-write + + + + + VENDORID + NA + 0x74 + 0x20 + 0x00005550 + + + VID + NA + 0 + 15 + read-write + + + + + + + AXI_ICM + AXI_ICM Peripheral + ICM_AXI + 0x500A4000 + + 0x0 + 0x10 + registers + + + + VERID_FILEDS + NA + 0x0 + 0x20 + 0x3430342A + + + ICM_REG_VERID + NA + 0 + 32 + read-only + + + + + HW_CFG + NA + 0x4 + 0x20 + 0x0070D151 + + + ICM_REG_AXI_HWCFG_QOS_SUPPORT + NA + 0 + 1 + read-only + + + ICM_REG_AXI_HWCFG_APB3_SUPPORT + NA + 1 + 1 + read-only + + + ICM_REG_AXI_HWCFG_AXI4_SUPPORT + NA + 2 + 1 + read-only + + + ICM_REG_AXI_HWCFG_LOCK_EN + NA + 3 + 1 + read-only + + + ICM_REG_AXI_HWCFG_TRUST_ZONE_EN + NA + 4 + 1 + read-only + + + ICM_REG_AXI_HWCFG_DECODER_TYPE + NA + 5 + 1 + read-only + + + ICM_REG_AXI_HWCFG_REMAP_EN + NA + 6 + 1 + read-only + + + ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN + NA + 7 + 1 + read-only + + + ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN + NA + 8 + 1 + read-only + + + ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS + NA + 12 + 5 + read-only + + + ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES + NA + 20 + 5 + read-only + + + + + CMD + NA + 0x8 + 0x20 + + + ICM_REG_AXI_CMD + NA + 0 + 3 + read-write + + + ICM_REG_RD_WR_CHAN + NA + 7 + 1 + read-write + + + ICM_REG_AXI_MASTER_PORT + NA + 8 + 4 + read-write + + + ICM_REG_AXI_ERR_BIT + NA + 28 + 1 + read-only + + + ICM_REG_AXI_SOFT_RESET_BIT + NA + 29 + 1 + read-write + + + ICM_REG_AXI_RD_WR_CMD + NA + 30 + 1 + read-write + + + ICM_REG_AXI_CMD_EN + NA + 31 + 1 + read-write + + + + + DATA + NA + 0xC + 0x20 + + + ICM_REG_DATA + NA + 0 + 32 + read-write + + + + + + + IO_MUX + Input/Output Multiplexer + IO_MUX + 0x500E1000 + + 0x0 + 0xE8 + registers + + + + gpio0 + iomux control register for gpio0 + 0x4 + 0x20 + 0x00000800 + + + GPIO0_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO0_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO0_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO0_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO0_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO0_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO0_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO0_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO0_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO0_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO0_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO0_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio1 + iomux control register for gpio1 + 0x8 + 0x20 + 0x00000800 + + + GPIO1_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO1_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO1_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO1_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO1_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO1_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO1_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO1_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO1_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO1_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO1_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO1_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio2 + iomux control register for gpio2 + 0xC + 0x20 + 0x00000800 + + + GPIO2_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO2_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO2_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO2_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO2_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO2_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO2_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO2_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO2_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO2_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO2_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO2_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio3 + iomux control register for gpio3 + 0x10 + 0x20 + 0x00000800 + + + GPIO3_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO3_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO3_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO3_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO3_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO3_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO3_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO3_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO3_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO3_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO3_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO3_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio4 + iomux control register for gpio4 + 0x14 + 0x20 + 0x00000800 + + + GPIO4_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO4_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO4_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO4_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO4_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO4_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO4_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO4_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO4_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO4_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO4_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO4_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio5 + iomux control register for gpio5 + 0x18 + 0x20 + 0x00000800 + + + GPIO5_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO5_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO5_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO5_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO5_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO5_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO5_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO5_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO5_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO5_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO5_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO5_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio6 + iomux control register for gpio6 + 0x1C + 0x20 + 0x00000800 + + + GPIO6_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO6_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO6_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO6_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO6_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO6_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO6_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO6_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO6_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO6_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO6_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO6_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio7 + iomux control register for gpio7 + 0x20 + 0x20 + 0x00000800 + + + GPIO7_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO7_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO7_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO7_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO7_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO7_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO7_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO7_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO7_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO7_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO7_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO7_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio8 + iomux control register for gpio8 + 0x24 + 0x20 + 0x00000800 + + + GPIO8_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO8_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO8_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO8_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO8_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO8_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO8_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO8_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO8_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO8_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO8_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO8_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio9 + iomux control register for gpio9 + 0x28 + 0x20 + 0x00000800 + + + GPIO9_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO9_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO9_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO9_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO9_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO9_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO9_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO9_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO9_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO9_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO9_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO9_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio10 + iomux control register for gpio10 + 0x2C + 0x20 + 0x00000800 + + + GPIO10_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO10_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO10_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO10_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO10_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO10_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO10_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO10_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO10_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO10_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO10_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO10_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio11 + iomux control register for gpio11 + 0x30 + 0x20 + 0x00000800 + + + GPIO11_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO11_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO11_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO11_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO11_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO11_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO11_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO11_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO11_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO11_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO11_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO11_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio12 + iomux control register for gpio12 + 0x34 + 0x20 + 0x00000800 + + + GPIO12_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO12_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO12_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO12_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO12_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO12_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO12_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO12_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO12_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO12_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO12_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO12_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio13 + iomux control register for gpio13 + 0x38 + 0x20 + 0x00000800 + + + GPIO13_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO13_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO13_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO13_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO13_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO13_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO13_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO13_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO13_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO13_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO13_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO13_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio14 + iomux control register for gpio14 + 0x3C + 0x20 + 0x00000800 + + + GPIO14_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO14_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO14_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO14_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO14_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO14_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO14_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO14_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO14_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO14_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO14_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO14_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio15 + iomux control register for gpio15 + 0x40 + 0x20 + 0x00000800 + + + GPIO15_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO15_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO15_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO15_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO15_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO15_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO15_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO15_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO15_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO15_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO15_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO15_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio16 + iomux control register for gpio16 + 0x44 + 0x20 + 0x00000800 + + + GPIO16_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO16_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO16_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO16_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO16_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO16_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO16_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO16_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO16_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO16_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO16_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO16_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio17 + iomux control register for gpio17 + 0x48 + 0x20 + 0x00000800 + + + GPIO17_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO17_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO17_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO17_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO17_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO17_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO17_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO17_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO17_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO17_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO17_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO17_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio18 + iomux control register for gpio18 + 0x4C + 0x20 + 0x00000800 + + + GPIO18_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO18_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO18_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO18_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO18_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO18_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO18_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO18_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO18_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO18_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO18_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO18_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio19 + iomux control register for gpio19 + 0x50 + 0x20 + 0x00000800 + + + GPIO19_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO19_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO19_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO19_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO19_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO19_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO19_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO19_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO19_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO19_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO19_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO19_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio20 + iomux control register for gpio20 + 0x54 + 0x20 + 0x00000800 + + + GPIO20_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO20_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO20_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO20_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO20_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO20_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO20_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO20_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO20_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO20_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO20_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO20_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio21 + iomux control register for gpio21 + 0x58 + 0x20 + 0x00000800 + + + GPIO21_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO21_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO21_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO21_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO21_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO21_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO21_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO21_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO21_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO21_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO21_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO21_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio22 + iomux control register for gpio22 + 0x5C + 0x20 + 0x00000800 + + + GPIO22_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO22_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO22_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO22_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO22_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO22_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO22_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO22_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO22_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO22_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO22_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO22_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio23 + iomux control register for gpio23 + 0x60 + 0x20 + 0x00000800 + + + GPIO23_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO23_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO23_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO23_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO23_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO23_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO23_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO23_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO23_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO23_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO23_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO23_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio24 + iomux control register for gpio24 + 0x64 + 0x20 + 0x00000800 + + + GPIO24_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO24_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO24_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO24_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO24_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO24_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO24_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO24_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO24_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO24_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO24_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO24_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio25 + iomux control register for gpio25 + 0x68 + 0x20 + 0x00000800 + + + GPIO25_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO25_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO25_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO25_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO25_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO25_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO25_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO25_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO25_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO25_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO25_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO25_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio26 + iomux control register for gpio26 + 0x6C + 0x20 + 0x00000800 + + + GPIO26_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO26_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO26_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO26_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO26_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO26_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO26_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO26_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO26_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO26_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO26_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO26_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio27 + iomux control register for gpio27 + 0x70 + 0x20 + 0x00000800 + + + GPIO27_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO27_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO27_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO27_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO27_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO27_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO27_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO27_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO27_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO27_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO27_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO27_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio28 + iomux control register for gpio28 + 0x74 + 0x20 + 0x00000800 + + + GPIO28_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO28_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO28_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO28_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO28_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO28_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO28_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO28_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO28_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO28_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO28_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO28_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio29 + iomux control register for gpio29 + 0x78 + 0x20 + 0x00000800 + + + GPIO29_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO29_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO29_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO29_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO29_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO29_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO29_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO29_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO29_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO29_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO29_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO29_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio30 + iomux control register for gpio30 + 0x7C + 0x20 + 0x00000800 + + + GPIO30_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO30_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO30_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO30_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO30_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO30_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO30_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO30_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO30_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO30_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO30_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO30_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio31 + iomux control register for gpio31 + 0x80 + 0x20 + 0x00000800 + + + GPIO31_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO31_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO31_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO31_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO31_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO31_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO31_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO31_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO31_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO31_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO31_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO31_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio32 + iomux control register for gpio32 + 0x84 + 0x20 + 0x00000800 + + + GPIO32_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO32_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO32_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO32_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO32_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO32_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO32_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO32_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO32_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO32_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO32_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO32_FILTER_EN + input filter enable + 15 + 1 + read-write + + + GPIO32_RUE_I3C + NA + 16 + 1 + read-write + + + GPIO32_RU_I3C + NA + 17 + 2 + read-write + + + GPIO32_RUE_SEL_I3C + NA + 19 + 1 + read-write + + + + + gpio33 + iomux control register for gpio33 + 0x88 + 0x20 + 0x00000800 + + + GPIO33_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO33_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO33_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO33_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO33_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO33_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO33_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO33_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO33_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO33_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO33_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO33_FILTER_EN + input filter enable + 15 + 1 + read-write + + + GPIO33_RUE_I3C + NA + 16 + 1 + read-write + + + GPIO33_RU_I3C + NA + 17 + 2 + read-write + + + GPIO33_RUE_SEL_I3C + NA + 19 + 1 + read-write + + + + + gpio34 + iomux control register for gpio34 + 0x8C + 0x20 + 0x00000800 + + + GPIO34_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO34_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO34_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO34_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO34_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO34_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO34_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO34_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO34_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO34_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO34_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO34_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio35 + iomux control register for gpio35 + 0x90 + 0x20 + 0x00000800 + + + GPIO35_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO35_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO35_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO35_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO35_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO35_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO35_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO35_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO35_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO35_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO35_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO35_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio36 + iomux control register for gpio36 + 0x94 + 0x20 + 0x00000800 + + + GPIO36_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO36_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO36_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO36_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO36_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO36_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO36_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO36_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO36_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO36_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO36_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO36_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio37 + iomux control register for gpio37 + 0x98 + 0x20 + 0x00000800 + + + GPIO37_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO37_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO37_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO37_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO37_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO37_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO37_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO37_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO37_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO37_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO37_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO37_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio38 + iomux control register for gpio38 + 0x9C + 0x20 + 0x00000800 + + + GPIO38_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO38_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO38_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO38_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO38_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO38_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO38_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO38_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO38_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO38_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO38_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO38_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio39 + iomux control register for gpio39 + 0xA0 + 0x20 + 0x00000800 + + + GPIO39_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO39_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO39_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO39_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO39_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO39_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO39_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO39_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO39_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO39_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO39_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO39_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio40 + iomux control register for gpio40 + 0xA4 + 0x20 + 0x00000800 + + + GPIO40_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO40_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO40_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO40_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO40_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO40_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO40_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO40_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO40_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO40_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO40_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO40_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio41 + iomux control register for gpio41 + 0xA8 + 0x20 + 0x00000800 + + + GPIO41_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO41_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO41_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO41_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO41_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO41_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO41_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO41_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO41_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO41_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO41_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO41_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio42 + iomux control register for gpio42 + 0xAC + 0x20 + 0x00000800 + + + GPIO42_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO42_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO42_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO42_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO42_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO42_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO42_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO42_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO42_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO42_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO42_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO42_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio43 + iomux control register for gpio43 + 0xB0 + 0x20 + 0x00000800 + + + GPIO43_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO43_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO43_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO43_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO43_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO43_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO43_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO43_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO43_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO43_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO43_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO43_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio44 + iomux control register for gpio44 + 0xB4 + 0x20 + 0x00000800 + + + GPIO44_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO44_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO44_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO44_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO44_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO44_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO44_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO44_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO44_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO44_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO44_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO44_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio45 + iomux control register for gpio45 + 0xB8 + 0x20 + 0x00000800 + + + GPIO45_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO45_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO45_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO45_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO45_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO45_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO45_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO45_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO45_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO45_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO45_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO45_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio46 + iomux control register for gpio46 + 0xBC + 0x20 + 0x00000800 + + + GPIO46_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO46_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO46_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO46_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO46_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO46_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO46_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO46_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO46_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO46_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO46_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO46_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio47 + iomux control register for gpio47 + 0xC0 + 0x20 + 0x00000800 + + + GPIO47_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO47_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO47_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO47_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO47_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO47_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO47_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO47_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO47_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO47_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO47_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO47_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio48 + iomux control register for gpio48 + 0xC4 + 0x20 + 0x00000800 + + + GPIO48_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO48_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO48_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO48_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO48_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO48_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO48_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO48_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO48_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO48_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO48_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO48_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio49 + iomux control register for gpio49 + 0xC8 + 0x20 + 0x00000800 + + + GPIO49_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO49_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO49_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO49_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO49_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO49_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO49_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO49_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO49_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO49_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO49_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO49_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio50 + iomux control register for gpio50 + 0xCC + 0x20 + 0x00000800 + + + GPIO50_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO50_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO50_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO50_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO50_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO50_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO50_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO50_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO50_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO50_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO50_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO50_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio51 + iomux control register for gpio51 + 0xD0 + 0x20 + 0x00000800 + + + GPIO51_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO51_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO51_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO51_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO51_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO51_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO51_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO51_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO51_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO51_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO51_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO51_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio52 + iomux control register for gpio52 + 0xD4 + 0x20 + 0x00000800 + + + GPIO52_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO52_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO52_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO52_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO52_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO52_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO52_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO52_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO52_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO52_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO52_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO52_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio53 + iomux control register for gpio53 + 0xD8 + 0x20 + 0x00000800 + + + GPIO53_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO53_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO53_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO53_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO53_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO53_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO53_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO53_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO53_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO53_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO53_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO53_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio54 + iomux control register for gpio54 + 0xDC + 0x20 + 0x00000800 + + + GPIO54_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO54_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO54_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO54_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO54_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO54_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO54_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO54_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO54_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO54_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO54_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO54_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio55 + iomux control register for gpio55 + 0xE0 + 0x20 + 0x00000800 + + + GPIO55_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO55_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO55_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO55_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO55_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO55_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO55_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO55_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO55_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO55_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO55_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO55_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + gpio56 + iomux control register for gpio56 + 0xE4 + 0x20 + 0x00000800 + + + GPIO56_MCU_OE + output enable on sleep mode + 0 + 1 + read-write + + + GPIO56_SLP_SEL + io sleep mode enable. set 1 to enable sleep mode. + 1 + 1 + read-write + + + GPIO56_MCU_WPD + pull-down enable on sleep mode + 2 + 1 + read-write + + + GPIO56_MCU_WPU + pull-up enable on sleep mode + 3 + 1 + read-write + + + GPIO56_MCU_IE + input enable on sleep mode + 4 + 1 + read-write + + + GPIO56_MCU_DRV + select drive strenth on sleep mode + 5 + 2 + read-write + + + GPIO56_FUN_WPD + pull-down enable + 7 + 1 + read-write + + + GPIO56_FUN_WPU + pull-up enable + 8 + 1 + read-write + + + GPIO56_FUN_IE + input enable + 9 + 1 + read-write + + + GPIO56_FUN_DRV + select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA + 10 + 2 + read-write + + + GPIO56_MCU_SEL + 0:select function0, 1:select function1 ... + 12 + 3 + read-write + + + GPIO56_FILTER_EN + input filter enable + 15 + 1 + read-write + + + + + DATE + iomux version + 0x104 + 0x20 + 0x00201222 + + + DATE + csv date + 0 + 28 + read-write + + + + + + + ISP + ISP Peripheral + ISP + 0x500A1000 + + 0x0 + 0x244 + registers + + + ISP + 100 + + + + VER_DATE + version control register + 0x0 + 0x20 + 0x20210608 + + + VER_DATA + csv version + 0 + 32 + read-write + + + + + CLK_EN + isp clk control register + 0x4 + 0x20 + + + CLK_EN + this bit configures the clk force on of isp reg. 0: disable, 1: enable + 0 + 1 + read-write + + + CLK_BLC_FORCE_ON + this bit configures the clk force on of blc. 0: disable, 1: enable + 1 + 1 + read-write + + + CLK_DPC_FORCE_ON + this bit configures the clk force on of dpc. 0: disable, 1: enable + 2 + 1 + read-write + + + CLK_BF_FORCE_ON + this bit configures the clk force on of bf. 0: disable, 1: enable + 3 + 1 + read-write + + + CLK_LSC_FORCE_ON + this bit configures the clk force on of lsc. 0: disable, 1: enable + 4 + 1 + read-write + + + CLK_DEMOSAIC_FORCE_ON + this bit configures the clk force on of demosaic. 0: disable, 1: enable + 5 + 1 + read-write + + + CLK_MEDIAN_FORCE_ON + this bit configures the clk force on of median. 0: disable, 1: enable + 6 + 1 + read-write + + + CLK_CCM_FORCE_ON + this bit configures the clk force on of ccm. 0: disable, 1: enable + 7 + 1 + read-write + + + CLK_GAMMA_FORCE_ON + this bit configures the clk force on of gamma. 0: disable, 1: enable + 8 + 1 + read-write + + + CLK_RGB2YUV_FORCE_ON + this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable + 9 + 1 + read-write + + + CLK_SHARP_FORCE_ON + this bit configures the clk force on of sharp. 0: disable, 1: enable + 10 + 1 + read-write + + + CLK_COLOR_FORCE_ON + this bit configures the clk force on of color. 0: disable, 1: enable + 11 + 1 + read-write + + + CLK_YUV2RGB_FORCE_ON + this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable + 12 + 1 + read-write + + + CLK_AE_FORCE_ON + this bit configures the clk force on of ae. 0: disable, 1: enable + 13 + 1 + read-write + + + CLK_AF_FORCE_ON + this bit configures the clk force on of af. 0: disable, 1: enable + 14 + 1 + read-write + + + CLK_AWB_FORCE_ON + this bit configures the clk force on of awb. 0: disable, 1: enable + 15 + 1 + read-write + + + CLK_HIST_FORCE_ON + this bit configures the clk force on of hist. 0: disable, 1: enable + 16 + 1 + read-write + + + CLK_MIPI_IDI_FORCE_ON + this bit configures the clk force on of mipi idi input. 0: disable, 1: enable + 17 + 1 + read-write + + + ISP_MEM_CLK_FORCE_ON + this bit configures the clk force on of all isp memory. 0: disable, 1: enable + 18 + 1 + read-write + + + + + CNTL + isp module enable control register + 0x8 + 0x20 + 0x40002442 + + + MIPI_DATA_EN + this bit configures mipi input data enable. 0: disable, 1: enable + 0 + 1 + read-write + + + ISP_EN + this bit configures isp global enable. 0: disable, 1: enable + 1 + 1 + read-write + + + BLC_EN + this bit configures blc enable. 0: disable, 1: enable + 2 + 1 + read-write + + + DPC_EN + this bit configures dpc enable. 0: disable, 1: enable + 3 + 1 + read-write + + + BF_EN + this bit configures bf enable. 0: disable, 1: enable + 4 + 1 + read-write + + + LSC_EN + this bit configures lsc enable. 0: disable, 1: enable + 5 + 1 + read-write + + + DEMOSAIC_EN + this bit configures demosaic enable. 0: disable, 1: enable + 6 + 1 + read-write + + + MEDIAN_EN + this bit configures median enable. 0: disable, 1: enable + 7 + 1 + read-write + + + CCM_EN + this bit configures ccm enable. 0: disable, 1: enable + 8 + 1 + read-write + + + GAMMA_EN + this bit configures gamma enable. 0: disable, 1: enable + 9 + 1 + read-write + + + RGB2YUV_EN + this bit configures rgb2yuv enable. 0: disable, 1: enable + 10 + 1 + read-write + + + SHARP_EN + this bit configures sharp enable. 0: disable, 1: enable + 11 + 1 + read-write + + + COLOR_EN + this bit configures color enable. 0: disable, 1: enable + 12 + 1 + read-write + + + YUV2RGB_EN + this bit configures yuv2rgb enable. 0: disable, 1: enable + 13 + 1 + read-write + + + AE_EN + this bit configures ae enable. 0: disable, 1: enable + 14 + 1 + read-write + + + AF_EN + this bit configures af enable. 0: disable, 1: enable + 15 + 1 + read-write + + + AWB_EN + this bit configures awb enable. 0: disable, 1: enable + 16 + 1 + read-write + + + HIST_EN + this bit configures hist enable. 0: disable, 1: enable + 17 + 1 + read-write + + + BYTE_ENDIAN_ORDER + select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: {[7:0], [15:8], [23:16], [31:24]} + 24 + 1 + read-write + + + ISP_DATA_TYPE + this field configures input data type, 0:RAW8 1:RAW10 2:RAW12 + 25 + 2 + read-write + + + ISP_IN_SRC + this field configures input data source, 0:CSI HOST 1:CAM 2:DMA + 27 + 2 + read-write + + + ISP_OUT_TYPE + this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: RGB565 + 29 + 3 + read-write + + + + + HSYNC_CNT + header hsync interval control register + 0xC + 0x20 + 0x00000007 + + + HSYNC_CNT + this field configures the number of clock before hsync and after vsync and line_end when decodes pix data from idi to isp + 0 + 8 + read-write + + + + + FRAME_CFG + frame control parameter register + 0x10 + 0x20 + 0x601E01E0 + + + VADR_NUM + this field configures input image size in y-direction, image row number - 1 + 0 + 12 + read-write + + + HADR_NUM + this field configures input image size in x-direction, image line number - 1 + 12 + 12 + read-write + + + BAYER_MODE + this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 : GR/BG 11 : RG/GB + 27 + 2 + read-write + + + HSYNC_START_EXIST + this bit configures the line end packet exist or not. 0: not exist, 1: exist + 29 + 1 + read-write + + + HSYNC_END_EXIST + this bit configures the line start packet exist or not. 0: not exist, 1: exist + 30 + 1 + read-write + + + + + CCM_COEF0 + ccm coef register 0 + 0x14 + 0x20 + 0x02500740 + + + CCM_RR + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_RG + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF1 + ccm coef register 1 + 0x18 + 0x20 + 0x022810C0 + + + CCM_RB + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_GR + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF3 + ccm coef register 3 + 0x1C + 0x20 + 0x02200680 + + + CCM_GG + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_GB + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF4 + ccm coef register 4 + 0x20 + 0x20 + 0x02581040 + + + CCM_BR + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + CCM_BG + this field configures the color correction matrix coefficient + 13 + 13 + read-write + + + + + CCM_COEF5 + ccm coef register 5 + 0x24 + 0x20 + 0x00000740 + + + CCM_BB + this field configures the color correction matrix coefficient + 0 + 13 + read-write + + + + + BF_MATRIX_CTRL + bf pix2matrix ctrl + 0x28 + 0x20 + + + BF_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + BF_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + BF_PADDING_DATA + this field configures bf matrix padding data + 16 + 8 + read-write + + + BF_PADDING_MODE + this bit configures the padding mode of bf matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 24 + 1 + read-write + + + + + BF_SIGMA + bf denoising level control register + 0x2C + 0x20 + 0x00000002 + + + SIGMA + this field configures the bayer denoising level, valid data from 2 to 20 + 0 + 6 + read-write + + + + + BF_GAU0 + bf gau template register 0 + 0x30 + 0x20 + 0xFFFFFFFF + + + GAU_TEMPLATE21 + this field configures index 21 of gausian template + 0 + 4 + read-write + + + GAU_TEMPLATE20 + this field configures index 20 of gausian template + 4 + 4 + read-write + + + GAU_TEMPLATE12 + this field configures index 12 of gausian template + 8 + 4 + read-write + + + GAU_TEMPLATE11 + this field configures index 11 of gausian template + 12 + 4 + read-write + + + GAU_TEMPLATE10 + this field configures index 10 of gausian template + 16 + 4 + read-write + + + GAU_TEMPLATE02 + this field configures index 02 of gausian template + 20 + 4 + read-write + + + GAU_TEMPLATE01 + this field configures index 01 of gausian template + 24 + 4 + read-write + + + GAU_TEMPLATE00 + this field configures index 00 of gausian template + 28 + 4 + read-write + + + + + BF_GAU1 + bf gau template register 1 + 0x34 + 0x20 + 0x0000000F + + + GAU_TEMPLATE22 + this field configures index 22 of gausian template + 0 + 4 + read-write + + + + + DPC_CTRL + DPC mode control register + 0x38 + 0x20 + 0x00000004 + + + DPC_CHECK_EN + this bit configures the check mode enable. 0: disable, 1: enable + 0 + 1 + read-write + + + STA_EN + this bit configures the sta dpc enable. 0: disable, 1: enable + 1 + 1 + read-write + + + DYN_EN + this bit configures the dyn dpc enable. 0: disable, 1: enable + 2 + 1 + read-write + + + DPC_BLACK_EN + this bit configures input image type select when in check mode, 0: white img, 1: black img + 3 + 1 + read-write + + + DPC_METHOD_SEL + this bit configures dyn dpc method select. 0: simple method, 1: hard method + 4 + 1 + read-write + + + DPC_CHECK_OD_EN + this bit configures output pixel data when in check mode or not. 0: no data output, 1: data output + 5 + 1 + read-write + + + + + DPC_CONF + DPC parameter config register + 0x3C + 0x20 + 0x04103030 + + + DPC_THRESHOLD_L + this bit configures the threshold to detect black img in check mode, or the low threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + 0 + 8 + read-write + + + DPC_THRESHOLD_H + this bit configures the threshold to detect white img in check mode, or the high threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1 + 8 + 8 + read-write + + + DPC_FACTOR_DARK + this field configures the dynamic correction method 1 dark factor + 16 + 6 + read-write + + + DPC_FACTOR_BRIG + this field configures the dynamic correction method 1 bright factor + 22 + 6 + read-write + + + + + DPC_MATRIX_CTRL + dpc pix2matrix ctrl + 0x40 + 0x20 + + + DPC_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + DPC_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + DPC_PADDING_DATA + this field configures dpc matrix padding data + 16 + 8 + read-write + + + DPC_PADDING_MODE + this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 24 + 1 + read-write + + + + + DPC_DEADPIX_CNT + DPC dead-pix number register + 0x44 + 0x20 + + + DPC_DEADPIX_CNT + this field represents the dead pixel count + 0 + 10 + read-only + + + + + LUT_CMD + LUT command register + 0x48 + 0x20 + + + LUT_ADDR + this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b lut, 01 sel r_gr lut + 0 + 12 + write-only + + + LUT_NUM + this field configures the lut selection. 0000:LSC LUT 0001:DPC LUT + 12 + 4 + write-only + + + LUT_CMD + this bit configures the access event of lut. 0:rd 1: wr + 16 + 1 + write-only + + + + + LUT_WDATA + LUT write data register + 0x4C + 0x20 + + + LUT_WDATA + this field configures the write data of lut. please initial ISP_LUT_WDATA before write ISP_LUT_CMD register + 0 + 32 + read-write + + + + + LUT_RDATA + LUT read data register + 0x50 + 0x20 + + + LUT_RDATA + this field represents the read data of lut. read ISP_LUT_RDATA after write ISP_LUT_CMD register + 0 + 32 + read-only + + + + + LSC_TABLESIZE + LSC point in x-direction + 0x54 + 0x20 + 0x0000001F + + + LSC_XTABLESIZE + this field configures lsc table size in x-direction + 0 + 5 + read-write + + + + + DEMOSAIC_MATRIX_CTRL + demosaic pix2matrix ctrl + 0x58 + 0x20 + + + DEMOSAIC_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + DEMOSAIC_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + DEMOSAIC_PADDING_DATA + this field configures demosaic matrix padding data + 16 + 8 + read-write + + + DEMOSAIC_PADDING_MODE + this bit configures the padding mode of demosaic matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 24 + 1 + read-write + + + + + DEMOSAIC_GRAD_RATIO + demosaic gradient select ratio + 0x5C + 0x20 + 0x00000010 + + + DEMOSAIC_GRAD_RATIO + this field configures demosaic gradient select ratio + 0 + 6 + read-write + + + + + MEDIAN_MATRIX_CTRL + median pix2matrix ctrl + 0x60 + 0x20 + + + MEDIAN_PADDING_DATA + this field configures median matrix padding data + 0 + 8 + read-write + + + MEDIAN_PADDING_MODE + this bit configures the padding mode of median matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding + 8 + 1 + read-write + + + + + INT_RAW + raw interrupt register + 0x64 + 0x20 + + + ISP_DATA_TYPE_ERR_INT_RAW + the raw interrupt status of input data type error. isp only support RGB bayer data type, other type will report type_err_int + 0 + 1 + read-only + + + ISP_ASYNC_FIFO_OVF_INT_RAW + the raw interrupt status of isp input fifo overflow + 1 + 1 + read-only + + + ISP_BUF_FULL_INT_RAW + the raw interrupt status of isp input buffer full + 2 + 1 + read-only + + + ISP_HVNUM_SETTING_ERR_INT_RAW + the raw interrupt status of hnum and vnum setting format error + 3 + 1 + read-only + + + ISP_DATA_TYPE_SETTING_ERR_INT_RAW + the raw interrupt status of setting invalid reg_data_type + 4 + 1 + read-only + + + ISP_MIPI_HNUM_UNMATCH_INT_RAW + the raw interrupt status of hnum setting unmatch with mipi input + 5 + 1 + read-only + + + DPC_CHECK_DONE_INT_RAW + the raw interrupt status of dpc check done + 6 + 1 + read-only + + + GAMMA_XCOORD_ERR_INT_RAW + the raw interrupt status of gamma setting error. it report the sum of the lengths represented by reg_gamma_x00~x0F isn't equal to 256 + 7 + 1 + read-only + + + AE_MONITOR_INT_RAW + the raw interrupt status of ae monitor + 8 + 1 + read-only + + + AE_FRAME_DONE_INT_RAW + the raw interrupt status of ae. + 9 + 1 + read-only + + + AF_FDONE_INT_RAW + the raw interrupt status of af statistic. when auto_update enable, each frame done will send one int pulse when manual_update, each time when write 1 to reg_manual_update will send a int pulse when next frame done + 10 + 1 + read-only + + + AF_ENV_INT_RAW + the raw interrupt status of af monitor. send a int pulse when env_det function enabled and environment changes detected + 11 + 1 + read-only + + + AWB_FDONE_INT_RAW + the raw interrupt status of awb. send a int pulse when statistic of one awb frame done + 12 + 1 + read-only + + + HIST_FDONE_INT_RAW + the raw interrupt status of histogram. send a int pulse when statistic of one frame histogram done + 13 + 1 + read-only + + + FRAME_INT_RAW + the raw interrupt status of isp frame end + 14 + 1 + read-only + + + BLC_FRAME_INT_RAW + the raw interrupt status of blc frame done + 15 + 1 + read-only + + + LSC_FRAME_INT_RAW + the raw interrupt status of lsc frame done + 16 + 1 + read-only + + + DPC_FRAME_INT_RAW + the raw interrupt status of dpc frame done + 17 + 1 + read-only + + + BF_FRAME_INT_RAW + the raw interrupt status of bf frame done + 18 + 1 + read-only + + + DEMOSAIC_FRAME_INT_RAW + the raw interrupt status of demosaic frame done + 19 + 1 + read-only + + + MEDIAN_FRAME_INT_RAW + the raw interrupt status of median frame done + 20 + 1 + read-only + + + CCM_FRAME_INT_RAW + the raw interrupt status of ccm frame done + 21 + 1 + read-only + + + GAMMA_FRAME_INT_RAW + the raw interrupt status of gamma frame done + 22 + 1 + read-only + + + RGB2YUV_FRAME_INT_RAW + the raw interrupt status of rgb2yuv frame done + 23 + 1 + read-only + + + SHARP_FRAME_INT_RAW + the raw interrupt status of sharp frame done + 24 + 1 + read-only + + + COLOR_FRAME_INT_RAW + the raw interrupt status of color frame done + 25 + 1 + read-only + + + YUV2RGB_FRAME_INT_RAW + the raw interrupt status of yuv2rgb frame done + 26 + 1 + read-only + + + TAIL_IDI_FRAME_INT_RAW + the raw interrupt status of isp_tail idi frame_end + 27 + 1 + read-only + + + HEADER_IDI_FRAME_INT_RAW + the raw interrupt status of real input frame end of isp_input + 28 + 1 + read-only + + + + + INT_ST + masked interrupt register + 0x68 + 0x20 + + + ISP_DATA_TYPE_ERR_INT_ST + the masked interrupt status of input data type error + 0 + 1 + read-only + + + ISP_ASYNC_FIFO_OVF_INT_ST + the masked interrupt status of isp input fifo overflow + 1 + 1 + read-only + + + ISP_BUF_FULL_INT_ST + the masked interrupt status of isp input buffer full + 2 + 1 + read-only + + + ISP_HVNUM_SETTING_ERR_INT_ST + the masked interrupt status of hnum and vnum setting format error + 3 + 1 + read-only + + + ISP_DATA_TYPE_SETTING_ERR_INT_ST + the masked interrupt status of setting invalid reg_data_type + 4 + 1 + read-only + + + ISP_MIPI_HNUM_UNMATCH_INT_ST + the masked interrupt status of hnum setting unmatch with mipi input + 5 + 1 + read-only + + + DPC_CHECK_DONE_INT_ST + the masked interrupt status of dpc check done + 6 + 1 + read-only + + + GAMMA_XCOORD_ERR_INT_ST + the masked interrupt status of gamma setting error + 7 + 1 + read-only + + + AE_MONITOR_INT_ST + the masked interrupt status of ae monitor + 8 + 1 + read-only + + + AE_FRAME_DONE_INT_ST + the masked interrupt status of ae + 9 + 1 + read-only + + + AF_FDONE_INT_ST + the masked interrupt status of af statistic + 10 + 1 + read-only + + + AF_ENV_INT_ST + the masked interrupt status of af monitor + 11 + 1 + read-only + + + AWB_FDONE_INT_ST + the masked interrupt status of awb + 12 + 1 + read-only + + + HIST_FDONE_INT_ST + the masked interrupt status of histogram + 13 + 1 + read-only + + + FRAME_INT_ST + the masked interrupt status of isp frame end + 14 + 1 + read-only + + + BLC_FRAME_INT_ST + the masked interrupt status of blc frame done + 15 + 1 + read-only + + + LSC_FRAME_INT_ST + the masked interrupt status of lsc frame done + 16 + 1 + read-only + + + DPC_FRAME_INT_ST + the masked interrupt status of dpc frame done + 17 + 1 + read-only + + + BF_FRAME_INT_ST + the masked interrupt status of bf frame done + 18 + 1 + read-only + + + DEMOSAIC_FRAME_INT_ST + the masked interrupt status of demosaic frame done + 19 + 1 + read-only + + + MEDIAN_FRAME_INT_ST + the masked interrupt status of median frame done + 20 + 1 + read-only + + + CCM_FRAME_INT_ST + the masked interrupt status of ccm frame done + 21 + 1 + read-only + + + GAMMA_FRAME_INT_ST + the masked interrupt status of gamma frame done + 22 + 1 + read-only + + + RGB2YUV_FRAME_INT_ST + the masked interrupt status of rgb2yuv frame done + 23 + 1 + read-only + + + SHARP_FRAME_INT_ST + the masked interrupt status of sharp frame done + 24 + 1 + read-only + + + COLOR_FRAME_INT_ST + the masked interrupt status of color frame done + 25 + 1 + read-only + + + YUV2RGB_FRAME_INT_ST + the masked interrupt status of yuv2rgb frame done + 26 + 1 + read-only + + + TAIL_IDI_FRAME_INT_ST + the masked interrupt status of isp_tail idi frame_end + 27 + 1 + read-only + + + HEADER_IDI_FRAME_INT_ST + the masked interrupt status of real input frame end of isp_input + 28 + 1 + read-only + + + + + INT_ENA + interrupt enable register + 0x6C + 0x20 + 0x000000C3 + + + ISP_DATA_TYPE_ERR_INT_ENA + write 1 to enable input data type error + 0 + 1 + read-write + + + ISP_ASYNC_FIFO_OVF_INT_ENA + write 1 to enable isp input fifo overflow + 1 + 1 + read-write + + + ISP_BUF_FULL_INT_ENA + write 1 to enable isp input buffer full + 2 + 1 + read-write + + + ISP_HVNUM_SETTING_ERR_INT_ENA + write 1 to enable hnum and vnum setting format error + 3 + 1 + read-write + + + ISP_DATA_TYPE_SETTING_ERR_INT_ENA + write 1 to enable setting invalid reg_data_type + 4 + 1 + read-write + + + ISP_MIPI_HNUM_UNMATCH_INT_ENA + write 1 to enable hnum setting unmatch with mipi input + 5 + 1 + read-write + + + DPC_CHECK_DONE_INT_ENA + write 1 to enable dpc check done + 6 + 1 + read-write + + + GAMMA_XCOORD_ERR_INT_ENA + write 1 to enable gamma setting error + 7 + 1 + read-write + + + AE_MONITOR_INT_ENA + write 1 to enable ae monitor + 8 + 1 + read-write + + + AE_FRAME_DONE_INT_ENA + write 1 to enable ae + 9 + 1 + read-write + + + AF_FDONE_INT_ENA + write 1 to enable af statistic + 10 + 1 + read-write + + + AF_ENV_INT_ENA + write 1 to enable af monitor + 11 + 1 + read-write + + + AWB_FDONE_INT_ENA + write 1 to enable awb + 12 + 1 + read-write + + + HIST_FDONE_INT_ENA + write 1 to enable histogram + 13 + 1 + read-write + + + FRAME_INT_ENA + write 1 to enable isp frame end + 14 + 1 + read-write + + + BLC_FRAME_INT_ENA + write 1 to enable blc frame done + 15 + 1 + read-write + + + LSC_FRAME_INT_ENA + write 1 to enable lsc frame done + 16 + 1 + read-write + + + DPC_FRAME_INT_ENA + write 1 to enable dpc frame done + 17 + 1 + read-write + + + BF_FRAME_INT_ENA + write 1 to enable bf frame done + 18 + 1 + read-write + + + DEMOSAIC_FRAME_INT_ENA + write 1 to enable demosaic frame done + 19 + 1 + read-write + + + MEDIAN_FRAME_INT_ENA + write 1 to enable median frame done + 20 + 1 + read-write + + + CCM_FRAME_INT_ENA + write 1 to enable ccm frame done + 21 + 1 + read-write + + + GAMMA_FRAME_INT_ENA + write 1 to enable gamma frame done + 22 + 1 + read-write + + + RGB2YUV_FRAME_INT_ENA + write 1 to enable rgb2yuv frame done + 23 + 1 + read-write + + + SHARP_FRAME_INT_ENA + write 1 to enable sharp frame done + 24 + 1 + read-write + + + COLOR_FRAME_INT_ENA + write 1 to enable color frame done + 25 + 1 + read-write + + + YUV2RGB_FRAME_INT_ENA + write 1 to enable yuv2rgb frame done + 26 + 1 + read-write + + + TAIL_IDI_FRAME_INT_ENA + write 1 to enable isp_tail idi frame_end + 27 + 1 + read-write + + + HEADER_IDI_FRAME_INT_ENA + write 1 to enable real input frame end of isp_input + 28 + 1 + read-write + + + + + INT_CLR + interrupt clear register + 0x70 + 0x20 + + + ISP_DATA_TYPE_ERR_INT_CLR + write 1 to clear input data type error + 0 + 1 + write-only + + + ISP_ASYNC_FIFO_OVF_INT_CLR + write 1 to clear isp input fifo overflow + 1 + 1 + write-only + + + ISP_BUF_FULL_INT_CLR + write 1 to clear isp input buffer full + 2 + 1 + write-only + + + ISP_HVNUM_SETTING_ERR_INT_CLR + write 1 to clear hnum and vnum setting format error + 3 + 1 + write-only + + + ISP_DATA_TYPE_SETTING_ERR_INT_CLR + write 1 to clear setting invalid reg_data_type + 4 + 1 + write-only + + + ISP_MIPI_HNUM_UNMATCH_INT_CLR + write 1 to clear hnum setting unmatch with mipi input + 5 + 1 + write-only + + + DPC_CHECK_DONE_INT_CLR + write 1 to clear dpc check done + 6 + 1 + write-only + + + GAMMA_XCOORD_ERR_INT_CLR + write 1 to clear gamma setting error + 7 + 1 + write-only + + + AE_MONITOR_INT_CLR + write 1 to clear ae monitor + 8 + 1 + write-only + + + AE_FRAME_DONE_INT_CLR + write 1 to clear ae + 9 + 1 + write-only + + + AF_FDONE_INT_CLR + write 1 to clear af statistic + 10 + 1 + write-only + + + AF_ENV_INT_CLR + write 1 to clear af monitor + 11 + 1 + write-only + + + AWB_FDONE_INT_CLR + write 1 to clear awb + 12 + 1 + write-only + + + HIST_FDONE_INT_CLR + write 1 to clear histogram + 13 + 1 + write-only + + + FRAME_INT_CLR + write 1 to clear isp frame end + 14 + 1 + write-only + + + BLC_FRAME_INT_CLR + write 1 to clear blc frame done + 15 + 1 + write-only + + + LSC_FRAME_INT_CLR + write 1 to clear lsc frame done + 16 + 1 + write-only + + + DPC_FRAME_INT_CLR + write 1 to clear dpc frame done + 17 + 1 + write-only + + + BF_FRAME_INT_CLR + write 1 to clear bf frame done + 18 + 1 + write-only + + + DEMOSAIC_FRAME_INT_CLR + write 1 to clear demosaic frame done + 19 + 1 + write-only + + + MEDIAN_FRAME_INT_CLR + write 1 to clear median frame done + 20 + 1 + write-only + + + CCM_FRAME_INT_CLR + write 1 to clear ccm frame done + 21 + 1 + write-only + + + GAMMA_FRAME_INT_CLR + write 1 to clear gamma frame done + 22 + 1 + write-only + + + RGB2YUV_FRAME_INT_CLR + write 1 to clear rgb2yuv frame done + 23 + 1 + write-only + + + SHARP_FRAME_INT_CLR + write 1 to clear sharp frame done + 24 + 1 + write-only + + + COLOR_FRAME_INT_CLR + write 1 to clear color frame done + 25 + 1 + write-only + + + YUV2RGB_FRAME_INT_CLR + write 1 to clear yuv2rgb frame done + 26 + 1 + write-only + + + TAIL_IDI_FRAME_INT_CLR + write 1 to clear isp_tail idi frame_end + 27 + 1 + write-only + + + HEADER_IDI_FRAME_INT_CLR + write 1 to clear real input frame end of isp_input + 28 + 1 + write-only + + + + + GAMMA_CTRL + gamma control register + 0x74 + 0x20 + 0x0000000E + + + GAMMA_UPDATE + Indicates that gamma register configuration is complete + 0 + 1 + read-write + + + GAMMA_B_LAST_CORRECT + this bit configures enable of last b segment correcction. 0: disable, 1: enable + 1 + 1 + read-write + + + GAMMA_G_LAST_CORRECT + this bit configures enable of last g segment correcction. 0: disable, 1: enable + 2 + 1 + read-write + + + GAMMA_R_LAST_CORRECT + this bit configures enable of last r segment correcction. 0: disable, 1: enable + 3 + 1 + read-write + + + + + GAMMA_RY1 + point of Y-axis of r channel gamma curve register 1 + 0x78 + 0x20 + 0x10203040 + + + GAMMA_R_Y03 + this field configures the point 3 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y02 + this field configures the point 2 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y01 + this field configures the point 1 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y00 + this field configures the point 0 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RY2 + point of Y-axis of r channel gamma curve register 2 + 0x7C + 0x20 + 0x50607080 + + + GAMMA_R_Y07 + this field configures the point 7 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y06 + this field configures the point 6 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y05 + this field configures the point 5 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y04 + this field configures the point 4 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RY3 + point of Y-axis of r channel gamma curve register 3 + 0x80 + 0x20 + 0x90A0B0C0 + + + GAMMA_R_Y0B + this field configures the point 11 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y0A + this field configures the point 10 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y09 + this field configures the point 9 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y08 + this field configures the point 8 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RY4 + point of Y-axis of r channel gamma curve register 4 + 0x84 + 0x20 + 0xD0E0F0FF + + + GAMMA_R_Y0F + this field configures the point 15 of Y-axis of r channel gamma curve + 0 + 8 + read-write + + + GAMMA_R_Y0E + this field configures the point 14 of Y-axis of r channel gamma curve + 8 + 8 + read-write + + + GAMMA_R_Y0D + this field configures the point 13 of Y-axis of r channel gamma curve + 16 + 8 + read-write + + + GAMMA_R_Y0C + this field configures the point 12 of Y-axis of r channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY1 + point of Y-axis of g channel gamma curve register 1 + 0x88 + 0x20 + 0x10203040 + + + GAMMA_G_Y03 + this field configures the point 3 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y02 + this field configures the point 2 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y01 + this field configures the point 1 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y00 + this field configures the point 0 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY2 + point of Y-axis of g channel gamma curve register 2 + 0x8C + 0x20 + 0x50607080 + + + GAMMA_G_Y07 + this field configures the point 7 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y06 + this field configures the point 6 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y05 + this field configures the point 5 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y04 + this field configures the point 4 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY3 + point of Y-axis of g channel gamma curve register 3 + 0x90 + 0x20 + 0x90A0B0C0 + + + GAMMA_G_Y0B + this field configures the point 11 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y0A + this field configures the point 10 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y09 + this field configures the point 9 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y08 + this field configures the point 8 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_GY4 + point of Y-axis of g channel gamma curve register 4 + 0x94 + 0x20 + 0xD0E0F0FF + + + GAMMA_G_Y0F + this field configures the point 15 of Y-axis of g channel gamma curve + 0 + 8 + read-write + + + GAMMA_G_Y0E + this field configures the point 14 of Y-axis of g channel gamma curve + 8 + 8 + read-write + + + GAMMA_G_Y0D + this field configures the point 13 of Y-axis of g channel gamma curve + 16 + 8 + read-write + + + GAMMA_G_Y0C + this field configures the point 12 of Y-axis of g channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY1 + point of Y-axis of b channel gamma curve register 1 + 0x98 + 0x20 + 0x10203040 + + + GAMMA_B_Y03 + this field configures the point 3 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y02 + this field configures the point 2 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y01 + this field configures the point 1 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y00 + this field configures the point 0 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY2 + point of Y-axis of b channel gamma curve register 2 + 0x9C + 0x20 + 0x50607080 + + + GAMMA_B_Y07 + this field configures the point 7 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y06 + this field configures the point 6 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y05 + this field configures the point 5 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y04 + this field configures the point 4 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY3 + point of Y-axis of b channel gamma curve register 3 + 0xA0 + 0x20 + 0x90A0B0C0 + + + GAMMA_B_Y0B + this field configures the point 11 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y0A + this field configures the point 10 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y09 + this field configures the point 9 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y08 + this field configures the point 8 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_BY4 + point of Y-axis of b channel gamma curve register 4 + 0xA4 + 0x20 + 0xD0E0F0FF + + + GAMMA_B_Y0F + this field configures the point 15 of Y-axis of b channel gamma curve + 0 + 8 + read-write + + + GAMMA_B_Y0E + this field configures the point 14 of Y-axis of b channel gamma curve + 8 + 8 + read-write + + + GAMMA_B_Y0D + this field configures the point 13 of Y-axis of b channel gamma curve + 16 + 8 + read-write + + + GAMMA_B_Y0C + this field configures the point 12 of Y-axis of b channel gamma curve + 24 + 8 + read-write + + + + + GAMMA_RX1 + point of X-axis of r channel gamma curve register 1 + 0xA8 + 0x20 + 0x00924924 + + + GAMMA_R_X07 + this field configures the point 7 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_R_X06 + this field configures the point 6 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_R_X05 + this field configures the point 5 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_R_X04 + this field configures the point 4 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_R_X03 + this field configures the point 3 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_R_X02 + this field configures the point 2 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_R_X01 + this field configures the point 1 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_R_X00 + this field configures the point 0 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_RX2 + point of X-axis of r channel gamma curve register 2 + 0xAC + 0x20 + 0x00924924 + + + GAMMA_R_X0F + this field configures the point 15 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_R_X0E + this field configures the point 14 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_R_X0D + this field configures the point 13 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_R_X0C + this field configures the point 12 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_R_X0B + this field configures the point 11 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_R_X0A + this field configures the point 10 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_R_X09 + this field configures the point 9 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_R_X08 + this field configures the point 8 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_GX1 + point of X-axis of g channel gamma curve register 1 + 0xB0 + 0x20 + 0x00924924 + + + GAMMA_G_X07 + this field configures the point 7 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_G_X06 + this field configures the point 6 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_G_X05 + this field configures the point 5 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_G_X04 + this field configures the point 4 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_G_X03 + this field configures the point 3 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_G_X02 + this field configures the point 2 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_G_X01 + this field configures the point 1 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_G_X00 + this field configures the point 0 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_GX2 + point of X-axis of g channel gamma curve register 2 + 0xB4 + 0x20 + 0x00924924 + + + GAMMA_G_X0F + this field configures the point 15 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_G_X0E + this field configures the point 14 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_G_X0D + this field configures the point 13 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_G_X0C + this field configures the point 12 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_G_X0B + this field configures the point 11 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_G_X0A + this field configures the point 10 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_G_X09 + this field configures the point 9 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_G_X08 + this field configures the point 8 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_BX1 + point of X-axis of b channel gamma curve register 1 + 0xB8 + 0x20 + 0x00924924 + + + GAMMA_B_X07 + this field configures the point 7 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_B_X06 + this field configures the point 6 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_B_X05 + this field configures the point 5 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_B_X04 + this field configures the point 4 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_B_X03 + this field configures the point 3 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_B_X02 + this field configures the point 2 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_B_X01 + this field configures the point 1 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_B_X00 + this field configures the point 0 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + GAMMA_BX2 + point of X-axis of b channel gamma curve register 2 + 0xBC + 0x20 + 0x00924924 + + + GAMMA_B_X0F + this field configures the point 15 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 0 + 3 + read-write + + + GAMMA_B_X0E + this field configures the point 14 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 3 + 3 + read-write + + + GAMMA_B_X0D + this field configures the point 13 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 6 + 3 + read-write + + + GAMMA_B_X0C + this field configures the point 12 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 9 + 3 + read-write + + + GAMMA_B_X0B + this field configures the point 11 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 12 + 3 + read-write + + + GAMMA_B_X0A + this field configures the point 10 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 15 + 3 + read-write + + + GAMMA_B_X09 + this field configures the point 9 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 18 + 3 + read-write + + + GAMMA_B_X08 + this field configures the point 8 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point + 21 + 3 + read-write + + + + + AE_CTRL + ae control register + 0xC0 + 0x20 + + + AE_UPDATE + write 1 to this bit triggers one statistic event + 0 + 1 + write-only + + + AE_SELECT + this field configures ae input data source, 0: data from median, 1: data from gama + 1 + 1 + read-write + + + + + AE_MONITOR + ae monitor control register + 0xC4 + 0x20 + + + TL + this field configures the lower lum threshold of ae monitor + 0 + 8 + read-write + + + TH + this field configures the higher lum threshold of ae monitor + 8 + 8 + read-write + + + PERIOD + this field cnfigures ae monitor frame period + 16 + 6 + read-write + + + + + AE_BX + ae window register in x-direction + 0xC8 + 0x20 + 0x00000180 + + + AE_X_BSIZE + this field configures every block x size + 0 + 11 + read-write + + + AE_X_START + this field configures first block start x address + 11 + 11 + read-write + + + + + AE_BY + ae window register in y-direction + 0xCC + 0x20 + 0x000000D8 + + + AE_Y_BSIZE + this field configures every block y size + 0 + 11 + read-write + + + AE_Y_START + this field configures first block start y address + 11 + 11 + read-write + + + + + AE_WINPIXNUM + ae sub-window pix num register + 0xD0 + 0x20 + 0x00014400 + + + AE_SUBWIN_PIXNUM + this field configures the pixel number of each sub win + 0 + 17 + read-write + + + + + AE_WIN_RECIPROCAL + reciprocal of ae sub-window pixel number + 0xD4 + 0x20 + + + AE_SUBWIN_RECIP + this field configures the reciprocal of each subwin_pixnum, 20bit fraction + 0 + 20 + read-write + + + + + AE_BLOCK_MEAN_0 + ae statistic result register 0 + 0xD8 + 0x20 + + + AE_B03_MEAN + this field configures block03 Y mean data + 0 + 8 + read-only + + + AE_B02_MEAN + this field configures block02 Y mean data + 8 + 8 + read-only + + + AE_B01_MEAN + this field configures block01 Y mean data + 16 + 8 + read-only + + + AE_B00_MEAN + this field configures block00 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_1 + ae statistic result register 1 + 0xDC + 0x20 + + + AE_B12_MEAN + this field configures block12 Y mean data + 0 + 8 + read-only + + + AE_B11_MEAN + this field configures block11 Y mean data + 8 + 8 + read-only + + + AE_B10_MEAN + this field configures block10 Y mean data + 16 + 8 + read-only + + + AE_B04_MEAN + this field configures block04 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_2 + ae statistic result register 2 + 0xE0 + 0x20 + + + AE_B21_MEAN + this field configures block21 Y mean data + 0 + 8 + read-only + + + AE_B20_MEAN + this field configures block20 Y mean data + 8 + 8 + read-only + + + AE_B14_MEAN + this field configures block14 Y mean data + 16 + 8 + read-only + + + AE_B13_MEAN + this field configures block13 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_3 + ae statistic result register 3 + 0xE4 + 0x20 + + + AE_B30_MEAN + this field configures block30 Y mean data + 0 + 8 + read-only + + + AE_B24_MEAN + this field configures block24 Y mean data + 8 + 8 + read-only + + + AE_B23_MEAN + this field configures block23 Y mean data + 16 + 8 + read-only + + + AE_B22_MEAN + this field configures block22 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_4 + ae statistic result register 4 + 0xE8 + 0x20 + + + AE_B34_MEAN + this field configures block34 Y mean data + 0 + 8 + read-only + + + AE_B33_MEAN + this field configures block33 Y mean data + 8 + 8 + read-only + + + AE_B32_MEAN + this field configures block32 Y mean data + 16 + 8 + read-only + + + AE_B31_MEAN + this field configures block31 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_5 + ae statistic result register 5 + 0xEC + 0x20 + + + AE_B43_MEAN + this field configures block43 Y mean data + 0 + 8 + read-only + + + AE_B42_MEAN + this field configures block42 Y mean data + 8 + 8 + read-only + + + AE_B41_MEAN + this field configures block41 Y mean data + 16 + 8 + read-only + + + AE_B40_MEAN + this field configures block40 Y mean data + 24 + 8 + read-only + + + + + AE_BLOCK_MEAN_6 + ae statistic result register 6 + 0xF0 + 0x20 + + + AE_B44_MEAN + this field configures block44 Y mean data + 24 + 8 + read-only + + + + + SHARP_CTRL0 + sharp control register 0 + 0xF4 + 0x20 + + + SHARP_THRESHOLD_LOW + this field configures sharpen threshold for detail + 0 + 8 + read-write + + + SHARP_THRESHOLD_HIGH + this field configures sharpen threshold for edge + 8 + 8 + read-write + + + SHARP_AMOUNT_LOW + this field configures sharpen amount for detail + 16 + 8 + read-write + + + SHARP_AMOUNT_HIGH + this field configures sharpen amount for edge + 24 + 8 + read-write + + + + + SHARP_FILTER0 + sharp usm config register 0 + 0xF8 + 0x20 + 0x00000441 + + + SHARP_FILTER_COE00 + this field configures unsharp masking(usm) filter coefficient + 0 + 5 + read-write + + + SHARP_FILTER_COE01 + this field configures usm filter coefficient + 5 + 5 + read-write + + + SHARP_FILTER_COE02 + this field configures usm filter coefficient + 10 + 5 + read-write + + + + + SHARP_FILTER1 + sharp usm config register 1 + 0xFC + 0x20 + 0x00000882 + + + SHARP_FILTER_COE10 + this field configures usm filter coefficient + 0 + 5 + read-write + + + SHARP_FILTER_COE11 + this field configures usm filter coefficient + 5 + 5 + read-write + + + SHARP_FILTER_COE12 + this field configures usm filter coefficient + 10 + 5 + read-write + + + + + SHARP_FILTER2 + sharp usm config register 2 + 0x100 + 0x20 + 0x00000441 + + + SHARP_FILTER_COE20 + this field configures usm filter coefficient + 0 + 5 + read-write + + + SHARP_FILTER_COE21 + this field configures usm filter coefficient + 5 + 5 + read-write + + + SHARP_FILTER_COE22 + this field configures usm filter coefficient + 10 + 5 + read-write + + + + + SHARP_MATRIX_CTRL + sharp pix2matrix ctrl + 0x104 + 0x20 + + + SHARP_TAIL_PIXEN_PULSE_TL + matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function + 0 + 8 + read-write + + + SHARP_TAIL_PIXEN_PULSE_TH + matrix tail pixen high level threshold, must < hnum-1, only reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail pulse function + 8 + 8 + read-write + + + SHARP_PADDING_DATA + this field configures sharp padding data + 16 + 8 + read-write + + + SHARP_PADDING_MODE + this field configures sharp padding mode + 24 + 1 + read-write + + + + + SHARP_CTRL1 + sharp control register 1 + 0x108 + 0x20 + + + SHARP_GRADIENT_MAX + this field configures sharp max gradient, refresh at the end of each frame end + 0 + 8 + read-only + + + + + DMA_CNTL + isp dma source trans control register + 0x10C + 0x20 + 0x001080A8 + + + DMA_EN + write 1 to triger dma to get 1 frame + 0 + 1 + write-only + + + DMA_UPDATE + write 1 to update reg_dma_burst_len & reg_dma_data_type + 1 + 1 + read-write + + + DMA_DATA_TYPE + this field configures the idi data type for image data + 2 + 6 + read-write + + + DMA_BURST_LEN + this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer + 8 + 12 + read-write + + + DMA_INTERVAL + this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ... + 20 + 12 + read-write + + + + + DMA_RAW_DATA + isp dma source total raw number set register + 0x110 + 0x20 + + + DMA_RAW_NUM_TOTAL + this field configures the the number of 64bits in a frame + 0 + 22 + read-write + + + DMA_RAW_NUM_TOTAL_SET + write 1 to update reg_dma_raw_num_total + 31 + 1 + write-only + + + + + CAM_CNTL + isp cam source control register + 0x114 + 0x20 + 0x00000004 + + + CAM_EN + write 1 to start recive camera data, write 0 to disable + 0 + 1 + read-write + + + CAM_UPDATE + write 1 to update ISP_CAM_CONF + 1 + 1 + read-write + + + CAM_RESET + this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset + 2 + 1 + read-write + + + CAM_CLK_INV + this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1: invert cam clk + 3 + 1 + read-write + + + + + CAM_CONF + isp cam source config register + 0x118 + 0x20 + 0x000000A8 + + + CAM_DATA_ORDER + this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0], cam_data_in[15:8]} + 0 + 1 + read-write + + + CAM_2BYTE_MODE + this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: disable, 1: enable + 1 + 1 + read-write + + + CAM_DATA_TYPE + this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: RAW12 + 2 + 6 + read-write + + + CAM_DE_INV + this bit configures cam data enable invert. 0: not invert, 1: invert + 8 + 1 + read-write + + + CAM_HSYNC_INV + this bit configures cam hsync invert. 0: not invert, 1: invert + 9 + 1 + read-write + + + CAM_VSYNC_INV + this bit configures cam vsync invert. 0: not invert, 1: invert + 10 + 1 + read-write + + + CAM_VSYNC_FILTER_THRES + this bit configures the number of clock of vsync filter length + 11 + 3 + read-write + + + CAM_VSYNC_FILTER_EN + this bit configures vsync filter en + 14 + 1 + read-write + + + + + AF_CTRL0 + af control register 0 + 0x11C + 0x20 + + + AF_AUTO_UPDATE + this bit configures auto_update enable. when set to 1, will update sum and lum each frame + 0 + 1 + read-write + + + AF_MANUAL_UPDATE + write 1 to this bit will update the sum and lum once + 4 + 1 + write-only + + + AF_ENV_THRESHOLD + this field configures env threshold. when both sum and lum changes larger than this value, consider environment changes and need to trigger a new autofocus. 4Bit fractional + 8 + 4 + read-write + + + AF_ENV_PERIOD + this field configures environment changes detection period (frame). When set to 0, disable this function + 16 + 8 + read-write + + + + + AF_CTRL1 + af control register 1 + 0x120 + 0x20 + + + AF_THPIXNUM + this field configures pixnum used when calculating the autofocus threshold. Set to 0 to disable threshold calculation + 0 + 22 + read-write + + + + + AF_GEN_TH_CTRL + af gen threshold control register + 0x124 + 0x20 + 0x04400080 + + + AF_GEN_THRESHOLD_MIN + this field configures min threshold when use auto_threshold + 0 + 16 + read-write + + + AF_GEN_THRESHOLD_MAX + this field configures max threshold when use auto_threshold + 16 + 16 + read-write + + + + + AF_ENV_USER_TH_SUM + af monitor user sum threshold register + 0x128 + 0x20 + + + AF_ENV_USER_THRESHOLD_SUM + this field configures user setup env detect sum threshold + 0 + 32 + read-write + + + + + AF_ENV_USER_TH_LUM + af monitor user lum threshold register + 0x12C + 0x20 + + + AF_ENV_USER_THRESHOLD_LUM + this field configures user setup env detect lum threshold + 0 + 30 + read-write + + + + + AF_THRESHOLD + af threshold register + 0x130 + 0x20 + 0x00000100 + + + AF_THRESHOLD + this field configures user threshold. When set to non-zero, autofocus will use this threshold + 0 + 16 + read-write + + + AF_GEN_THRESHOLD + this field represents the last calculated threshold + 16 + 16 + read-only + + + + + AF_HSCALE_A + h-scale of af window a register + 0x134 + 0x20 + 0x00010080 + + + AF_RPOINT_A + this field configures left coordinate of focus window a, must >= 2 + 0 + 12 + read-write + + + AF_LPOINT_A + this field configures top coordinate of focus window a, must >= 2 + 16 + 12 + read-write + + + + + AF_VSCALE_A + v-scale of af window a register + 0x138 + 0x20 + 0x00010080 + + + AF_BPOINT_A + this field configures right coordinate of focus window a, must <= hnum-2 + 0 + 12 + read-write + + + AF_TPOINT_A + this field configures bottom coordinate of focus window a, must <= hnum-2 + 16 + 12 + read-write + + + + + AF_HSCALE_B + h-scale of af window b register + 0x13C + 0x20 + 0x00010080 + + + AF_RPOINT_B + this field configures left coordinate of focus window b, must >= 2 + 0 + 12 + read-write + + + AF_LPOINT_B + this field configures top coordinate of focus window b, must >= 2 + 16 + 12 + read-write + + + + + AF_VSCALE_B + v-scale of af window b register + 0x140 + 0x20 + 0x00010080 + + + AF_BPOINT_B + this field configures right coordinate of focus window b, must <= hnum-2 + 0 + 12 + read-write + + + AF_TPOINT_B + this field configures bottom coordinate of focus window b, must <= hnum-2 + 16 + 12 + read-write + + + + + AF_HSCALE_C + v-scale of af window c register + 0x144 + 0x20 + 0x00010080 + + + AF_RPOINT_C + this field configures left coordinate of focus window c, must >= 2 + 0 + 12 + read-write + + + AF_LPOINT_C + this field configures top coordinate of focus window c, must >= 2 + 16 + 12 + read-write + + + + + AF_VSCALE_C + v-scale of af window c register + 0x148 + 0x20 + 0x00010080 + + + AF_BPOINT_C + this field configures right coordinate of focus window c, must <= hnum-2 + 0 + 12 + read-write + + + AF_TPOINT_C + this field configures bottom coordinate of focus window c, must <= hnum-2 + 16 + 12 + read-write + + + + + AF_SUM_A + result of sum of af window a + 0x14C + 0x20 + + + AF_SUMA + this field represents the result of accumulation of pix grad of focus window a + 0 + 30 + read-only + + + + + AF_SUM_B + result of sum of af window b + 0x150 + 0x20 + + + AF_SUMB + this field represents the result of accumulation of pix grad of focus window b + 0 + 30 + read-only + + + + + AF_SUM_C + result of sum of af window c + 0x154 + 0x20 + + + AF_SUMC + this field represents the result of accumulation of pix grad of focus window c + 0 + 30 + read-only + + + + + AF_LUM_A + result of lum of af window a + 0x158 + 0x20 + + + AF_LUMA + this field represents the result of accumulation of pix light of focus window a + 0 + 28 + read-only + + + + + AF_LUM_B + result of lum of af window b + 0x15C + 0x20 + + + AF_LUMB + this field represents the result of accumulation of pix light of focus window b + 0 + 28 + read-only + + + + + AF_LUM_C + result of lum of af window c + 0x160 + 0x20 + + + AF_LUMC + this field represents the result of accumulation of pix light of focus window c + 0 + 28 + read-only + + + + + AWB_MODE + awb mode control register + 0x164 + 0x20 + 0x00000003 + + + AWB_MODE + this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel algo1. 11: sel both algo0 and algo1 + 0 + 2 + read-write + + + AWB_SAMPLE + this bit configures awb sample location, 0:before ccm, 1:after ccm + 4 + 1 + read-write + + + + + AWB_HSCALE + h-scale of awb window + 0x168 + 0x20 + 0x0000077F + + + AWB_RPOINT + this field configures awb window right coordinate + 0 + 12 + read-write + + + AWB_LPOINT + this field configures awb window left coordinate + 16 + 12 + read-write + + + + + AWB_VSCALE + v-scale of awb window + 0x16C + 0x20 + 0x00000437 + + + AWB_BPOINT + this field configures awb window bottom coordinate + 0 + 12 + read-write + + + AWB_TPOINT + this field configures awb window top coordinate + 16 + 12 + read-write + + + + + AWB_TH_LUM + awb lum threshold register + 0x170 + 0x20 + 0x02FD0000 + + + AWB_MIN_LUM + this field configures lower threshold of r+g+b + 0 + 10 + read-write + + + AWB_MAX_LUM + this field configures upper threshold of r+g+b + 16 + 10 + read-write + + + + + AWB_TH_RG + awb r/g threshold register + 0x174 + 0x20 + 0x03FF0000 + + + AWB_MIN_RG + this field configures lower threshold of r/g, 2bit integer and 8bit fraction + 0 + 10 + read-write + + + AWB_MAX_RG + this field configures upper threshold of r/g, 2bit integer and 8bit fraction + 16 + 10 + read-write + + + + + AWB_TH_BG + awb b/g threshold register + 0x178 + 0x20 + 0x03FF0000 + + + AWB_MIN_BG + this field configures lower threshold of b/g, 2bit integer and 8bit fraction + 0 + 10 + read-write + + + AWB_MAX_BG + this field configures upper threshold of b/g, 2bit integer and 8bit fraction + 16 + 10 + read-write + + + + + AWB0_WHITE_CNT + result of awb white point number + 0x17C + 0x20 + + + AWB0_WHITE_CNT + this field configures number of white point detected of algo0 + 0 + 24 + read-only + + + + + AWB0_ACC_R + result of accumulate of r channel of all white points + 0x180 + 0x20 + + + AWB0_ACC_R + this field represents accumulate of channel r of all white point of algo0 + 0 + 32 + read-only + + + + + AWB0_ACC_G + result of accumulate of g channel of all white points + 0x184 + 0x20 + + + AWB0_ACC_G + this field represents accumulate of channel g of all white point of algo0 + 0 + 32 + read-only + + + + + AWB0_ACC_B + result of accumulate of b channel of all white points + 0x188 + 0x20 + + + AWB0_ACC_B + this field represents accumulate of channel b of all white point of algo0 + 0 + 32 + read-only + + + + + COLOR_CTRL + color control register + 0x18C + 0x20 + 0x00800080 + + + COLOR_SATURATION + this field configures the color saturation value + 0 + 8 + read-write + + + COLOR_HUE + this field configures the color hue angle + 8 + 8 + read-write + + + COLOR_CONTRAST + this field configures the color contrast value + 16 + 8 + read-write + + + COLOR_BRIGHTNESS + this field configures the color brightness value, signed 2's complement + 24 + 8 + read-write + + + + + BLC_VALUE + blc black level register + 0x190 + 0x20 + + + BLC_R3_VALUE + this field configures the black level of bottom right channel of bayer img + 0 + 8 + read-write + + + BLC_R2_VALUE + this field configures the black level of bottom left channel of bayer img + 8 + 8 + read-write + + + BLC_R1_VALUE + this field configures the black level of top right channel of bayer img + 16 + 8 + read-write + + + BLC_R0_VALUE + this field configures the black level of top left channel of bayer img + 24 + 8 + read-write + + + + + BLC_CTRL0 + blc stretch control register + 0x194 + 0x20 + + + BLC_R3_STRETCH + this bit configures the stretch feature of bottom right channel. 0: stretch disable, 1: stretch enable + 0 + 1 + read-write + + + BLC_R2_STRETCH + this bit configures the stretch feature of bottom left channel. 0: stretch disable, 1: stretch enable + 1 + 1 + read-write + + + BLC_R1_STRETCH + this bit configures the stretch feature of top right channel. 0: stretch disable, 1: stretch enable + 2 + 1 + read-write + + + BLC_R0_STRETCH + this bit configures the stretch feature of top left channel. 0: stretch disable, 1: stretch enable + 3 + 1 + read-write + + + + + BLC_CTRL1 + blc window control register + 0x198 + 0x20 + + + BLC_WINDOW_TOP + this field configures blc average calculation window top + 0 + 11 + read-write + + + BLC_WINDOW_LEFT + this field configures blc average calculation window left + 11 + 11 + read-write + + + BLC_WINDOW_VNUM + this field configures blc average calculation window vnum + 22 + 4 + read-write + + + BLC_WINDOW_HNUM + this field configures blc average calculation window hnum + 26 + 4 + read-write + + + BLC_FILTER_EN + this bit configures enable blc average input filter. 0: disable, 1: enable + 30 + 1 + read-write + + + + + BLC_CTRL2 + blc black threshold control register + 0x19C + 0x20 + + + BLC_R3_TH + this field configures black threshold when get blc average of bottom right channel + 0 + 8 + read-write + + + BLC_R2_TH + this field configures black threshold when get blc average of bottom left channel + 8 + 8 + read-write + + + BLC_R1_TH + this field configures black threshold when get blc average of top right channel + 16 + 8 + read-write + + + BLC_R0_TH + this field configures black threshold when get blc average of top left channel + 24 + 8 + read-write + + + + + BLC_MEAN + results of the average of black window + 0x1A0 + 0x20 + + + BLC_R3_MEAN + this field represents the average black value of bottom right channel + 0 + 8 + read-only + + + BLC_R2_MEAN + this field represents the average black value of bottom left channel + 8 + 8 + read-only + + + BLC_R1_MEAN + this field represents the average black value of top right channel + 16 + 8 + read-only + + + BLC_R0_MEAN + this field represents the average black value of top left channel + 24 + 8 + read-only + + + + + HIST_MODE + histogram mode control register + 0x1A4 + 0x20 + 0x00000004 + + + HIST_MODE + this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V + 0 + 3 + read-write + + + + + HIST_COEFF + histogram rgb to gray coefficients register + 0x1A8 + 0x20 + 0x00555555 + + + B + this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 + 0 + 8 + read-write + + + G + this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 + 8 + 8 + read-write + + + R + this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256 + 16 + 8 + read-write + + + + + HIST_OFFS + histogram window offsets register + 0x1AC + 0x20 + + + HIST_Y_OFFS + this field configures y coordinate of first window + 0 + 12 + read-write + + + HIST_X_OFFS + this field configures x coordinate of first window + 16 + 12 + read-write + + + + + HIST_SIZE + histogram sub-window size register + 0x1B0 + 0x20 + 0x00120020 + + + HIST_Y_SIZE + this field configures y direction size of subwindow + 0 + 9 + read-write + + + HIST_X_SIZE + this field configures x direction size of subwindow + 16 + 9 + read-write + + + + + HIST_SEG0 + histogram bin control register 0 + 0x1B4 + 0x20 + 0x10203040 + + + HIST_SEG_3_4 + this field configures threshold of histogram bin 3 and bin 4 + 0 + 8 + read-write + + + HIST_SEG_2_3 + this field configures threshold of histogram bin 2 and bin 3 + 8 + 8 + read-write + + + HIST_SEG_1_2 + this field configures threshold of histogram bin 1 and bin 2 + 16 + 8 + read-write + + + HIST_SEG_0_1 + this field configures threshold of histogram bin 0 and bin 1 + 24 + 8 + read-write + + + + + HIST_SEG1 + histogram bin control register 1 + 0x1B8 + 0x20 + 0x50607080 + + + HIST_SEG_7_8 + this field configures threshold of histogram bin 7 and bin 8 + 0 + 8 + read-write + + + HIST_SEG_6_7 + this field configures threshold of histogram bin 6 and bin 7 + 8 + 8 + read-write + + + HIST_SEG_5_6 + this field configures threshold of histogram bin 5 and bin 6 + 16 + 8 + read-write + + + HIST_SEG_4_5 + this field configures threshold of histogram bin 4 and bin 5 + 24 + 8 + read-write + + + + + HIST_SEG2 + histogram bin control register 2 + 0x1BC + 0x20 + 0x90A0B0C0 + + + HIST_SEG_11_12 + this field configures threshold of histogram bin 11 and bin 12 + 0 + 8 + read-write + + + HIST_SEG_10_11 + this field configures threshold of histogram bin 10 and bin 11 + 8 + 8 + read-write + + + HIST_SEG_9_10 + this field configures threshold of histogram bin 9 and bin 10 + 16 + 8 + read-write + + + HIST_SEG_8_9 + this field configures threshold of histogram bin 8 and bin 9 + 24 + 8 + read-write + + + + + HIST_SEG3 + histogram bin control register 3 + 0x1C0 + 0x20 + 0x00D0E0F0 + + + HIST_SEG_14_15 + this field configures threshold of histogram bin 14 and bin 15 + 0 + 8 + read-write + + + HIST_SEG_13_14 + this field configures threshold of histogram bin 13 and bin 14 + 8 + 8 + read-write + + + HIST_SEG_12_13 + this field configures threshold of histogram bin 12 and bin 13 + 16 + 8 + read-write + + + + + HIST_WEIGHT0 + histogram sub-window weight register 0 + 0x1C4 + 0x20 + 0x01010101 + + + HIST_WEIGHT_03 + this field configures weight of subwindow 03 + 0 + 8 + read-write + + + HIST_WEIGHT_02 + this field configures weight of subwindow 02 + 8 + 8 + read-write + + + HIST_WEIGHT_01 + this field configures weight of subwindow 01 + 16 + 8 + read-write + + + HIST_WEIGHT_00 + this field configures weight of subwindow 00 and sum of all weight should be 256 + 24 + 8 + read-write + + + + + HIST_WEIGHT1 + histogram sub-window weight register 1 + 0x1C8 + 0x20 + 0x01010101 + + + HIST_WEIGHT_12 + this field configures weight of subwindow 12 + 0 + 8 + read-write + + + HIST_WEIGHT_11 + this field configures weight of subwindow 11 + 8 + 8 + read-write + + + HIST_WEIGHT_10 + this field configures weight of subwindow 10 + 16 + 8 + read-write + + + HIST_WEIGHT_04 + this field configures weight of subwindow 04 + 24 + 8 + read-write + + + + + HIST_WEIGHT2 + histogram sub-window weight register 2 + 0x1CC + 0x20 + 0x01010101 + + + HIST_WEIGHT_21 + this field configures weight of subwindow 21 + 0 + 8 + read-write + + + HIST_WEIGHT_20 + this field configures weight of subwindow 20 + 8 + 8 + read-write + + + HIST_WEIGHT_14 + this field configures weight of subwindow 04 + 16 + 8 + read-write + + + HIST_WEIGHT_13 + this field configures weight of subwindow 13 + 24 + 8 + read-write + + + + + HIST_WEIGHT3 + histogram sub-window weight register 3 + 0x1D0 + 0x20 + 0xE8010101 + + + HIST_WEIGHT_30 + this field configures weight of subwindow 30 + 0 + 8 + read-write + + + HIST_WEIGHT_24 + this field configures weight of subwindow 24 + 8 + 8 + read-write + + + HIST_WEIGHT_23 + this field configures weight of subwindow 23 + 16 + 8 + read-write + + + HIST_WEIGHT_22 + this field configures weight of subwindow 22 + 24 + 8 + read-write + + + + + HIST_WEIGHT4 + histogram sub-window weight register 4 + 0x1D4 + 0x20 + 0x01010101 + + + HIST_WEIGHT_34 + this field configures weight of subwindow 34 + 0 + 8 + read-write + + + HIST_WEIGHT_33 + this field configures weight of subwindow 33 + 8 + 8 + read-write + + + HIST_WEIGHT_32 + this field configures weight of subwindow 32 + 16 + 8 + read-write + + + HIST_WEIGHT_31 + this field configures weight of subwindow 31 + 24 + 8 + read-write + + + + + HIST_WEIGHT5 + histogram sub-window weight register 5 + 0x1D8 + 0x20 + 0x01010101 + + + HIST_WEIGHT_43 + this field configures weight of subwindow 43 + 0 + 8 + read-write + + + HIST_WEIGHT_42 + this field configures weight of subwindow 42 + 8 + 8 + read-write + + + HIST_WEIGHT_41 + this field configures weight of subwindow 41 + 16 + 8 + read-write + + + HIST_WEIGHT_40 + this field configures weight of subwindow 40 + 24 + 8 + read-write + + + + + HIST_WEIGHT6 + histogram sub-window weight register 6 + 0x1DC + 0x20 + 0x00000001 + + + HIST_WEIGHT_44 + this field configures weight of subwindow 44 + 0 + 8 + read-write + + + + + HIST_BIN0 + result of histogram bin 0 + 0x1E0 + 0x20 + + + HIST_BIN_0 + this field represents result of histogram bin 0 + 0 + 17 + read-only + + + + + HIST_BIN1 + result of histogram bin 1 + 0x1E4 + 0x20 + + + HIST_BIN_1 + this field represents result of histogram bin 1 + 0 + 17 + read-only + + + + + HIST_BIN2 + result of histogram bin 2 + 0x1E8 + 0x20 + + + HIST_BIN_2 + this field represents result of histogram bin 2 + 0 + 17 + read-only + + + + + HIST_BIN3 + result of histogram bin 3 + 0x1EC + 0x20 + + + HIST_BIN_3 + this field represents result of histogram bin 3 + 0 + 17 + read-only + + + + + HIST_BIN4 + result of histogram bin 4 + 0x1F0 + 0x20 + + + HIST_BIN_4 + this field represents result of histogram bin 4 + 0 + 17 + read-only + + + + + HIST_BIN5 + result of histogram bin 5 + 0x1F4 + 0x20 + + + HIST_BIN_5 + this field represents result of histogram bin 5 + 0 + 17 + read-only + + + + + HIST_BIN6 + result of histogram bin 6 + 0x1F8 + 0x20 + + + HIST_BIN_6 + this field represents result of histogram bin 6 + 0 + 17 + read-only + + + + + HIST_BIN7 + result of histogram bin 7 + 0x1FC + 0x20 + + + HIST_BIN_7 + this field represents result of histogram bin 7 + 0 + 17 + read-only + + + + + HIST_BIN8 + result of histogram bin 8 + 0x200 + 0x20 + + + HIST_BIN_8 + this field represents result of histogram bin 8 + 0 + 17 + read-only + + + + + HIST_BIN9 + result of histogram bin 9 + 0x204 + 0x20 + + + HIST_BIN_9 + this field represents result of histogram bin 9 + 0 + 17 + read-only + + + + + HIST_BIN10 + result of histogram bin 10 + 0x208 + 0x20 + + + HIST_BIN_10 + this field represents result of histogram bin 10 + 0 + 17 + read-only + + + + + HIST_BIN11 + result of histogram bin 11 + 0x20C + 0x20 + + + HIST_BIN_11 + this field represents result of histogram bin 11 + 0 + 17 + read-only + + + + + HIST_BIN12 + result of histogram bin 12 + 0x210 + 0x20 + + + HIST_BIN_12 + this field represents result of histogram bin 12 + 0 + 17 + read-only + + + + + HIST_BIN13 + result of histogram bin 13 + 0x214 + 0x20 + + + HIST_BIN_13 + this field represents result of histogram bin 13 + 0 + 17 + read-only + + + + + HIST_BIN14 + result of histogram bin 14 + 0x218 + 0x20 + + + HIST_BIN_14 + this field represents result of histogram bin 14 + 0 + 17 + read-only + + + + + HIST_BIN15 + result of histogram bin 15 + 0x21C + 0x20 + + + HIST_BIN_15 + this field represents result of histogram bin 15 + 0 + 17 + read-only + + + + + MEM_AUX_CTRL_0 + mem aux control register 0 + 0x220 + 0x20 + 0x13201320 + + + HEADER_MEM_AUX_CTRL + this field configures the mem_aux of isp input buffer memory + 0 + 14 + read-write + + + DPC_LUT_MEM_AUX_CTRL + this field represents this field configures the mem_aux of dpc lut memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_1 + mem aux control register 1 + 0x224 + 0x20 + 0x13201320 + + + LSC_LUT_R_GR_MEM_AUX_CTRL + this field configures the mem_aux of lsc r gr lut memory + 0 + 14 + read-write + + + LSC_LUT_GB_B_MEM_AUX_CTRL + this field configures the mem_aux of lsc gb b lut memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_2 + mem aux control register 2 + 0x228 + 0x20 + 0x13201320 + + + BF_MATRIX_MEM_AUX_CTRL + this field configures the mem_aux of bf line buffer memory + 0 + 14 + read-write + + + DPC_MATRIX_MEM_AUX_CTRL + this field configures the mem_aux of dpc line buffer memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_3 + mem aux control register 3 + 0x22C + 0x20 + 0x13201320 + + + SHARP_MATRIX_Y_MEM_AUX_CTRL + this field configures the mem_aux of sharp y line buffer memory + 0 + 14 + read-write + + + DEMOSAIC_MATRIX_MEM_AUX_CTRL + this field configures the mem_aux of demosaic line buffer memory + 16 + 14 + read-write + + + + + MEM_AUX_CTRL_4 + mem aux control register 4 + 0x230 + 0x20 + 0x00001320 + + + SHARP_MATRIX_UV_MEM_AUX_CTRL + this field configures the mem_aux of sharp uv line buffer memory + 0 + 14 + read-write + + + + + YUV_FORMAT + yuv format control register + 0x234 + 0x20 + + + YUV_MODE + this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709 + 0 + 1 + read-write + + + YUV_RANGE + this bit configures the yuv range. 0: full range, 1: limit range + 1 + 1 + read-write + + + + + RDN_ECO_CS + rdn eco cs register + 0x238 + 0x20 + + + RDN_ECO_EN + rdn_eco_en + 0 + 1 + read-write + + + RDN_ECO_RESULT + rdn_eco_result + 1 + 1 + read-only + + + + + RDN_ECO_LOW + rdn eco all low register + 0x23C + 0x20 + + + RDN_ECO_LOW + rdn_eco_low + 0 + 32 + read-write + + + + + RDN_ECO_HIGH + rdn eco all high register + 0x240 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + rdn_eco_high + 0 + 32 + read-write + + + + + + + JPEG + JPEG Codec + JPEG + 0x50086000 + + 0x0 + 0xB0 + registers + + + JPEG + 95 + + + + CONFIG + Control and configuration registers + 0x0 + 0x20 + 0x00408958 + + + FSM_RST + fsm reset + 0 + 1 + write-only + + + JPEG_START + start to compress a new pic(in dma reg mode) + 1 + 1 + write-only + + + QNR_PRESITION + 0:8bit qnr,1:12bit qnr(TBD) + 2 + 1 + read-write + + + FF_CHECK_EN + enable whether to add "00" after "ff" + 3 + 1 + read-write + + + SAMPLE_SEL + 0:yuv444,1:yuv422, 2:yuv420 + 4 + 2 + read-write + + + DMA_LINKLIST_MODE + 1:use linklist to configure dma + 6 + 1 + read-only + + + DEBUG_DIRECT_OUT_EN + 0:normal mode,1:debug mode for direct output from input + 7 + 1 + read-write + + + GRAY_SEL + 0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram + 8 + 1 + read-write + + + LQNR_TBL_SEL + choose luminance quntization table id(TBD) + 9 + 2 + read-write + + + CQNR_TBL_SEL + choose chrominance quntization table id (TBD) + 11 + 2 + read-write + + + COLOR_SPACE + configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray + 13 + 2 + read-write + + + DHT_FIFO_EN + 0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to write dht len_total/codemin/value table. Reading dht len_total/codemin/value table only has nonfifo way + 15 + 1 + read-write + + + MEM_CLK_FORCE_ON + force memory's clock enabled + 16 + 1 + read-write + + + JFIF_VER + decode pause period to trigger decode_timeout int, the timeout periods =2 power (reg_decode_timeout_thres) -1 + 17 + 6 + read-write + + + DECODE_TIMEOUT_TASK_SEL + 0: software use reset to abort decode process ,1: decoder abort decode process by itself + 23 + 1 + read-write + + + SOFT_RST + when set to 1, soft reset JPEG module except jpeg_reg module + 24 + 1 + read-write + + + FIFO_RST + fifo reset + 25 + 1 + read-write + + + PIXEL_REV + reverse the source color pixel + 26 + 1 + read-write + + + TAILER_EN + set this bit to add EOI of "0xffd9" at the end of bitstream + 27 + 1 + read-write + + + PAUSE_EN + set this bit to pause jpeg encoding + 28 + 1 + read-write + + + MEM_FORCE_PD + 0: no operation,1:force jpeg memory to power down + 29 + 1 + read-write + + + MEM_FORCE_PU + 0: no operation,1:force jpeg memory to power up + 30 + 1 + read-write + + + MODE + 0:encoder mode, 1: decoder mode + 31 + 1 + read-write + + + + + DQT_INFO + Control and configuration registers + 0x4 + 0x20 + 0x03020100 + + + T0_DQT_INFO + Configure dqt table0's quantization coefficient precision in bit[7:4], configure dqt table0's table id in bit[3:0] + 0 + 8 + read-write + + + T1_DQT_INFO + Configure dqt table1's quantization coefficient precision in bit[7:4], configure dqt table1's table id in bit[3:0] + 8 + 8 + read-write + + + T2_DQT_INFO + Configure dqt table2's quantization coefficient precision in bit[7:4], configure dqt table2's table id in bit[3:0] + 16 + 8 + read-write + + + T3_DQT_INFO + Configure dqt table3's quantization coefficient precision in bit[7:4], configure dqt table3's table id in bit[3:0] + 24 + 8 + read-write + + + + + PIC_SIZE + Control and configuration registers + 0x8 + 0x20 + 0x028001E0 + + + VA + configure picture's height. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16 + 0 + 16 + read-write + + + HA + configure picture's width. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16 + 16 + 16 + read-write + + + + + T0QNR + Control and configuration registers + 0x10 + 0x20 + + + T0_QNR_VAL + write this reg to configure 64 quantization coefficient in t0 table + 0 + 32 + read-only + + + + + T1QNR + Control and configuration registers + 0x14 + 0x20 + + + CHROMINANCE_QNR_VAL + write this reg to configure 64 quantization coefficient in t1 table + 0 + 32 + read-only + + + + + T2QNR + Control and configuration registers + 0x18 + 0x20 + + + T2_QNR_VAL + write this reg to configure 64 quantization coefficient in t2 table + 0 + 32 + read-only + + + + + T3QNR + Control and configuration registers + 0x1C + 0x20 + + + T3_QNR_VAL + write this reg to configure 64 quantization coefficient in t3 table + 0 + 32 + read-only + + + + + DECODE_CONF + Control and configuration registers + 0x20 + 0x20 + 0x5F030000 + + + RESTART_INTERVAL + configure restart interval in DRI marker when decode + 0 + 16 + read-write + + + COMPONENT_NUM + configure number of components in frame when decode + 16 + 8 + read-write + + + SW_DHT_EN + software decode dht table enable + 24 + 1 + read-only + + + SOS_CHECK_BYTE_NUM + Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1 + 25 + 2 + read-write + + + RST_CHECK_BYTE_NUM + Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1 + 27 + 2 + read-write + + + MULTI_SCAN_ERR_CHECK + reserved for decoder + 29 + 1 + read-write + + + DEZIGZAG_READY_CTL + reserved for decoder + 30 + 1 + read-write + + + + + C0 + Control and configuration registers + 0x24 + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c0 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c0 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c0 + 12 + 4 + read-write + + + ID + the identifier of c0 + 16 + 8 + read-write + + + + + C1 + Control and configuration registers + 0x28 + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c1 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c1 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c1 + 12 + 4 + read-write + + + ID + the identifier of c1 + 16 + 8 + read-write + + + + + C2 + Control and configuration registers + 0x2C + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c2 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c2 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c2 + 12 + 4 + read-write + + + ID + the identifier of c2 + 16 + 8 + read-write + + + + + C3 + Control and configuration registers + 0x30 + 0x20 + 0x00001100 + + + DQT_TBL_SEL + choose c3 quntization table id (TBD) + 0 + 8 + read-write + + + Y_FACTOR + vertical sampling factor of c3 + 8 + 4 + read-write + + + X_FACTOR + horizontal sampling factor of c3 + 12 + 4 + read-write + + + ID + the identifier of c3 + 16 + 8 + read-write + + + + + DHT_INFO + Control and configuration registers + 0x34 + 0x20 + 0x00001010 + + + DC0_DHT_ID + configure dht dc table 0 id + 0 + 4 + read-write + + + DC1_DHT_ID + configure dht dc table 1 id + 4 + 4 + read-write + + + AC0_DHT_ID + configure dht ac table 0 id + 8 + 4 + read-write + + + AC1_DHT_ID + configure dht ac table 1 id + 12 + 4 + read-write + + + + + INT_RAW + Interrupt raw registers + 0x38 + 0x20 + + + DONE_INT_RAW + This raw interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + read-write + + + RLE_PARALLEL_ERR_INT_RAW + The raw interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + read-write + + + CID_ERR_INT_RAW + The raw interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + read-write + + + C_DHT_DC_ID_ERR_INT_RAW + The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + read-write + + + C_DHT_AC_ID_ERR_INT_RAW + The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + read-write + + + C_DQT_ID_ERR_INT_RAW + The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + read-write + + + RST_UXP_ERR_INT_RAW + The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + read-write + + + RST_CHECK_NONE_ERR_INT_RAW + The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + read-write + + + RST_CHECK_POS_ERR_INT_RAW + The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + read-write + + + OUT_EOF_INT_RAW + The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + read-write + + + SR_COLOR_MODE_ERR_INT_RAW + The raw interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + read-write + + + DCT_DONE_INT_RAW + The raw interrupt bit to sign that one dct calculation is finished. + 11 + 1 + read-write + + + BS_LAST_BLOCK_EOF_INT_RAW + The raw interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + read-write + + + SCAN_CHECK_NONE_ERR_INT_RAW + The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + read-write + + + SCAN_CHECK_POS_ERR_INT_RAW + The raw interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + read-write + + + UXP_DET_INT_RAW + The raw interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + read-write + + + EN_FRAME_EOF_ERR_INT_RAW + The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + read-write + + + EN_FRAME_EOF_LACK_INT_RAW + The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + read-write + + + DE_FRAME_EOF_ERR_INT_RAW + The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + read-write + + + DE_FRAME_EOF_LACK_INT_RAW + The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + read-write + + + SOS_UNMATCH_ERR_INT_RAW + The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + read-write + + + MARKER_ERR_FST_SCAN_INT_RAW + The raw interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + read-write + + + MARKER_ERR_OTHER_SCAN_INT_RAW + The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + read-write + + + UNDET_INT_RAW + The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + read-write + + + DECODE_TIMEOUT_INT_RAW + The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + read-write + + + + + INT_ENA + Interrupt enable registers + 0x3C + 0x20 + + + DONE_INT_ENA + This enable interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + read-write + + + RLE_PARALLEL_ERR_INT_ENA + The enable interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + read-write + + + CID_ERR_INT_ENA + The enable interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + read-write + + + C_DHT_DC_ID_ERR_INT_ENA + The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + read-write + + + C_DHT_AC_ID_ERR_INT_ENA + The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + read-write + + + C_DQT_ID_ERR_INT_ENA + The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + read-write + + + RST_UXP_ERR_INT_ENA + The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + read-write + + + RST_CHECK_NONE_ERR_INT_ENA + The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + read-write + + + RST_CHECK_POS_ERR_INT_ENA + The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + read-write + + + OUT_EOF_INT_ENA + The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + read-write + + + SR_COLOR_MODE_ERR_INT_ENA + The enable interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + read-write + + + DCT_DONE_INT_ENA + The enable interrupt bit to sign that one dct calculation is finished. + 11 + 1 + read-write + + + BS_LAST_BLOCK_EOF_INT_ENA + The enable interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + read-write + + + SCAN_CHECK_NONE_ERR_INT_ENA + The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + read-write + + + SCAN_CHECK_POS_ERR_INT_ENA + The enable interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + read-write + + + UXP_DET_INT_ENA + The enable interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + read-write + + + EN_FRAME_EOF_ERR_INT_ENA + The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + read-write + + + EN_FRAME_EOF_LACK_INT_ENA + The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + read-write + + + DE_FRAME_EOF_ERR_INT_ENA + The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + read-write + + + DE_FRAME_EOF_LACK_INT_ENA + The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + read-write + + + SOS_UNMATCH_ERR_INT_ENA + The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + read-write + + + MARKER_ERR_FST_SCAN_INT_ENA + The enable interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + read-write + + + MARKER_ERR_OTHER_SCAN_INT_ENA + The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + read-write + + + UNDET_INT_ENA + The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + read-write + + + DECODE_TIMEOUT_INT_ENA + The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + read-write + + + + + INT_ST + Interrupt status registers + 0x40 + 0x20 + + + DONE_INT_ST + This status interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + read-only + + + RLE_PARALLEL_ERR_INT_ST + The status interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + read-only + + + CID_ERR_INT_ST + The status interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + read-only + + + C_DHT_DC_ID_ERR_INT_ST + The status interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + read-only + + + C_DHT_AC_ID_ERR_INT_ST + The status interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + read-only + + + C_DQT_ID_ERR_INT_ST + The status interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + read-only + + + RST_UXP_ERR_INT_ST + The status interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + read-only + + + RST_CHECK_NONE_ERR_INT_ST + The status interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + read-only + + + RST_CHECK_POS_ERR_INT_ST + The status interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + read-only + + + OUT_EOF_INT_ST + The status interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + read-only + + + SR_COLOR_MODE_ERR_INT_ST + The status interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + read-only + + + DCT_DONE_INT_ST + The status interrupt bit to sign that one dct calculation is finished. + 11 + 1 + read-only + + + BS_LAST_BLOCK_EOF_INT_ST + The status interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + read-only + + + SCAN_CHECK_NONE_ERR_INT_ST + The status interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + read-only + + + SCAN_CHECK_POS_ERR_INT_ST + The status interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + read-only + + + UXP_DET_INT_ST + The status interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + read-only + + + EN_FRAME_EOF_ERR_INT_ST + The status interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + read-only + + + EN_FRAME_EOF_LACK_INT_ST + The status interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + read-only + + + DE_FRAME_EOF_ERR_INT_ST + The status interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + read-only + + + DE_FRAME_EOF_LACK_INT_ST + The status interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + read-only + + + SOS_UNMATCH_ERR_INT_ST + The status interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + read-only + + + MARKER_ERR_FST_SCAN_INT_ST + The status interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + read-only + + + MARKER_ERR_OTHER_SCAN_INT_ST + The status interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + read-only + + + UNDET_INT_ST + The status interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + read-only + + + DECODE_TIMEOUT_INT_ST + The status interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + read-only + + + + + INT_CLR + Interrupt clear registers + 0x44 + 0x20 + + + DONE_INT_CLR + This clear interrupt bit turns to high level when JPEG finishes encoding a picture.. + 0 + 1 + write-only + + + RLE_PARALLEL_ERR_INT_CLR + The clear interrupt bit to sign that rle parallel error when decoding. + 1 + 1 + write-only + + + CID_ERR_INT_CLR + The clear interrupt bit to sign that scan id check with component fails when decoding. + 2 + 1 + write-only + + + C_DHT_DC_ID_ERR_INT_CLR + The clear interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding. + 3 + 1 + write-only + + + C_DHT_AC_ID_ERR_INT_CLR + The clear interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding. + 4 + 1 + write-only + + + C_DQT_ID_ERR_INT_CLR + The clear interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding. + 5 + 1 + write-only + + + RST_UXP_ERR_INT_CLR + The clear interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + 6 + 1 + write-only + + + RST_CHECK_NONE_ERR_INT_CLR + The clear interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + 7 + 1 + write-only + + + RST_CHECK_POS_ERR_INT_CLR + The clear interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + 8 + 1 + write-only + + + OUT_EOF_INT_CLR + The clear interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + 9 + 1 + write-only + + + SR_COLOR_MODE_ERR_INT_CLR + The clear interrupt bit to sign that the selected source color mode is not supported. + 10 + 1 + write-only + + + DCT_DONE_INT_CLR + The clear interrupt bit to sign that one dct calculation is finished. + 11 + 1 + write-only + + + BS_LAST_BLOCK_EOF_INT_CLR + The clear interrupt bit to sign that the coding process for last block is finished. + 12 + 1 + write-only + + + SCAN_CHECK_NONE_ERR_INT_CLR + The clear interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + 13 + 1 + write-only + + + SCAN_CHECK_POS_ERR_INT_CLR + The clear interrupt bit to sign that SOS header marker position wrong when decoding. + 14 + 1 + write-only + + + UXP_DET_INT_CLR + The clear interrupt bit to sign that unsupported header marker is detected when decoding. + 15 + 1 + write-only + + + EN_FRAME_EOF_ERR_INT_CLR + The clear interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + 16 + 1 + write-only + + + EN_FRAME_EOF_LACK_INT_CLR + The clear interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + 17 + 1 + write-only + + + DE_FRAME_EOF_ERR_INT_CLR + The clear interrupt bit to sign that decoded blocks are smaller than expected when decoding. + 18 + 1 + write-only + + + DE_FRAME_EOF_LACK_INT_CLR + The clear interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + 19 + 1 + write-only + + + SOS_UNMATCH_ERR_INT_CLR + The clear interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding. + 20 + 1 + write-only + + + MARKER_ERR_FST_SCAN_INT_CLR + The clear interrupt bit to sign that the first scan has header marker error when decoding. + 21 + 1 + write-only + + + MARKER_ERR_OTHER_SCAN_INT_CLR + The clear interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + 22 + 1 + write-only + + + UNDET_INT_CLR + The clear interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + 23 + 1 + write-only + + + DECODE_TIMEOUT_INT_CLR + The clear interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + 24 + 1 + write-only + + + + + STATUS0 + Trace and Debug registers + 0x48 + 0x20 + + + BITSTREAM_EOF_VLD_CNT + the valid bit count for last bitstream + 11 + 6 + read-only + + + DCTOUT_ZZSCAN_ADDR + the zig-zag read addr from dctout_ram + 17 + 6 + read-only + + + QNRVAL_ZZSCAN_ADDR + the zig-zag read addr from qnrval_ram + 23 + 6 + read-only + + + REG_STATE_YUV + the state of jpeg fsm + 29 + 3 + read-only + + + + + STATUS2 + Trace and Debug registers + 0x4C + 0x20 + 0x08000000 + + + SOURCE_PIXEL + source pixels fetched from dma + 0 + 24 + read-only + + + LAST_BLOCK + indicate the encoding process for the last mcu of the picture + 24 + 1 + read-only + + + LAST_MCU + indicate the encoding process for the last block of the picture + 25 + 1 + read-only + + + LAST_DC + indicate the encoding process is at the header of the last block of the picture + 26 + 1 + read-only + + + PACKFIFO_READY + the jpeg pack_fifo ready signal, high active + 27 + 1 + read-only + + + + + STATUS3 + Trace and Debug registers + 0x50 + 0x20 + + + YO + component y transferred from rgb input + 0 + 9 + read-only + + + Y_READY + component y valid signal, high active + 9 + 1 + read-only + + + CBO + component cb transferred from rgb input + 10 + 9 + read-only + + + CB_READY + component cb valid signal, high active + 19 + 1 + read-only + + + CRO + component cr transferred from rgb input + 20 + 9 + read-only + + + CR_READY + component cr valid signal, high active + 29 + 1 + read-only + + + + + STATUS4 + Trace and Debug registers + 0x54 + 0x20 + + + HFM_BITSTREAM + the hufman bitstream during encoding process + 0 + 32 + read-only + + + + + DHT_TOTLEN_DC0 + Trace and Debug registers + 0x58 + 0x20 + + + DHT_TOTLEN_DC0 + write the numbers of 1~n codeword length sum from 1~16 of dc0 table + 0 + 32 + read-only + + + + + DHT_VAl_DC0 + Trace and Debug registers + 0x5C + 0x20 + + + DHT_VAL_DC0 + write codeword corresponding huffman values of dc0 table + 0 + 32 + read-only + + + + + DHT_TOTLEN_AC0 + Trace and Debug registers + 0x60 + 0x20 + + + DHT_TOTLEN_AC0 + write the numbers of 1~n codeword length sum from 1~16 of ac0 table + 0 + 32 + read-only + + + + + DHT_VAl_AC0 + Trace and Debug registers + 0x64 + 0x20 + + + DHT_VAL_AC0 + write codeword corresponding huffman values of ac0 table + 0 + 32 + read-only + + + + + DHT_TOTLEN_DC1 + Trace and Debug registers + 0x68 + 0x20 + + + DHT_TOTLEN_DC1 + write the numbers of 1~n codeword length sum from 1~16 of dc1 table + 0 + 32 + read-only + + + + + DHT_VAl_DC1 + Trace and Debug registers + 0x6C + 0x20 + + + DHT_VAL_DC1 + write codeword corresponding huffman values of dc1 table + 0 + 32 + read-only + + + + + DHT_TOTLEN_AC1 + Trace and Debug registers + 0x70 + 0x20 + + + DHT_TOTLEN_AC1 + write the numbers of 1~n codeword length sum from 1~16 of ac1 table + 0 + 32 + read-only + + + + + DHT_VAl_AC1 + Trace and Debug registers + 0x74 + 0x20 + + + DHT_VAL_AC1 + write codeword corresponding huffman values of ac1 table + 0 + 32 + read-only + + + + + DHT_CODEMIN_DC0 + Trace and Debug registers + 0x78 + 0x20 + + + DHT_CODEMIN_DC0 + write the minimum codeword of code length from 1~16 of dc0 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DHT_CODEMIN_AC0 + Trace and Debug registers + 0x7C + 0x20 + + + DHT_CODEMIN_AC0 + write the minimum codeword of code length from 1~16 of ac0 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DHT_CODEMIN_DC1 + Trace and Debug registers + 0x80 + 0x20 + + + DHT_CODEMIN_DC1 + write the minimum codeword of code length from 1~16 of dc1 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DHT_CODEMIN_AC1 + Trace and Debug registers + 0x84 + 0x20 + + + DHT_CODEMIN_AC1 + write the minimum codeword of code length from 1~16 of ac1 table. The codeword is left shifted to the MSB position of a 16bit word + 0 + 32 + read-only + + + + + DECODER_STATUS0 + Trace and Debug registers + 0x88 + 0x20 + + + DECODE_BYTE_CNT + Reserved + 0 + 26 + read-only + + + HEADER_DEC_ST + Reserved + 26 + 4 + read-only + + + DECODE_SAMPLE_SEL + Reserved + 30 + 2 + read-only + + + + + DECODER_STATUS1 + Trace and Debug registers + 0x8C + 0x20 + + + ENCODE_DATA + Reserved + 0 + 16 + read-only + + + COUNT_Q + Reserved + 16 + 7 + read-only + + + MCU_FSM_READY + Reserved + 23 + 1 + read-only + + + DECODE_DATA + Reserved + 24 + 8 + read-only + + + + + DECODER_STATUS2 + Trace and Debug registers + 0x90 + 0x20 + + + COMP_BLOCK_NUM + Reserved + 0 + 26 + read-only + + + SCAN_NUM + Reserved + 26 + 3 + read-only + + + RST_CHECK_WAIT + Reserved + 29 + 1 + read-only + + + SCAN_CHECK_WAIT + Reserved + 30 + 1 + read-only + + + MCU_IN_PROC + Reserved + 31 + 1 + read-only + + + + + DECODER_STATUS3 + Trace and Debug registers + 0x94 + 0x20 + + + LOOKUP_DATA + Reserved + 0 + 32 + read-only + + + + + DECODER_STATUS4 + Trace and Debug registers + 0x98 + 0x20 + + + BLOCK_EOF_CNT + Reserved + 0 + 26 + read-only + + + DEZIGZAG_READY + Reserved + 26 + 1 + read-only + + + DE_FRAME_EOF_CHECK + Reserved + 27 + 1 + read-only + + + DE_DMA2D_IN_PUSH + Reserved + 28 + 1 + read-only + + + + + DECODER_STATUS5 + Trace and Debug registers + 0x9C + 0x20 + + + IDCT_HFM_DATA + Reserved + 0 + 16 + read-only + + + NS0 + Reserved + 16 + 3 + read-only + + + NS1 + Reserved + 19 + 3 + read-only + + + NS2 + Reserved + 22 + 3 + read-only + + + NS3 + Reserved + 25 + 3 + read-only + + + DATA_LAST_O + Reserved + 28 + 1 + read-only + + + RDN_RESULT + redundant registers for jpeg + 29 + 1 + read-only + + + RDN_ENA + redundant control registers for jpeg + 30 + 1 + read-write + + + + + STATUS5 + Trace and Debug registers + 0xA0 + 0x20 + + + PIC_BLOCK_NUM + Reserved + 0 + 24 + read-only + + + + + ECO_LOW + Trace and Debug registers + 0xA4 + 0x20 + + + RDN_ECO_LOW + redundant registers for jpeg + 0 + 32 + read-write + + + + + ECO_HIGH + Trace and Debug registers + 0xA8 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + redundant registers for jpeg + 0 + 32 + read-write + + + + + SYS + Trace and Debug registers + 0xF8 + 0x20 + + + CLK_EN + Reserved + 31 + 1 + read-write + + + + + VERSION + Trace and Debug registers + 0xFC + 0x20 + 0x02111190 + + + JPEG_VER + Reserved + 0 + 28 + read-write + + + + + + + LCD_CAM + Camera/LCD Controller + LCDCAM + 0x500DC000 + + 0x0 + 0x4C + registers + + + + LCD_CLOCK + LCD clock config register. + 0x0 + 0x20 + 0x00000843 + + + LCD_CLKCNT_N + f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + 0 + 6 + read-write + + + LCD_CLK_EQU_SYSCLK + 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1). + 6 + 1 + read-write + + + LCD_CK_IDLE_EDGE + 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle. + 7 + 1 + read-write + + + LCD_CK_OUT_EDGE + 1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low in the second half data cycle. + 8 + 1 + read-write + + + LCD_CLKM_DIV_NUM + Integral LCD clock divider value + 9 + 8 + read-write + + + LCD_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + LCD_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + LCD_CLK_SEL + Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + CLK_EN + Set this bit to enable clk gate + 31 + 1 + read-write + + + + + CAM_CTRL + CAM config register. + 0x4 + 0x20 + 0x00000800 + + + CAM_STOP_EN + Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop. + 0 + 1 + read-write + + + CAM_VSYNC_FILTER_THRES + Filter threshold value for CAM_VSYNC signal. + 1 + 3 + read-write + + + CAM_UPDATE + 1: Update Camera registers, will be cleared by hardware. 0 : Not care. + 4 + 1 + read-write + + + CAM_BYTE_ORDER + 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 5 + 1 + read-write + + + CAM_BIT_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 6 + 1 + read-write + + + CAM_LINE_INT_EN + 1: Enable to generate CAM_HS_INT. 0: Disable. + 7 + 1 + read-write + + + CAM_VS_EOF_EN + 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen. + 8 + 1 + read-write + + + CAM_CLKM_DIV_NUM + Integral Camera clock divider value + 9 + 8 + read-write + + + CAM_CLKM_DIV_B + Fractional clock divider numerator value + 17 + 6 + read-write + + + CAM_CLKM_DIV_A + Fractional clock divider denominator value + 23 + 6 + read-write + + + CAM_CLK_SEL + Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock. + 29 + 2 + read-write + + + + + CAM_CTRL1 + CAM config register. + 0x8 + 0x20 + + + CAM_REC_DATA_BYTELEN + Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + 0 + 16 + read-write + + + CAM_LINE_INT_NUM + The line number minus 1 to generate cam_hs_int. + 16 + 6 + read-write + + + CAM_CLK_INV + 1: Invert the input signal CAM_PCLK. 0: Not invert. + 22 + 1 + read-write + + + CAM_VSYNC_FILTER_EN + 1: Enable CAM_VSYNC filter function. 0: bypass. + 23 + 1 + read-write + + + CAM_2BYTE_EN + 1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8. + 24 + 1 + read-write + + + CAM_DE_INV + CAM_DE invert enable signal, valid in high level. + 25 + 1 + read-write + + + CAM_HSYNC_INV + CAM_HSYNC invert enable signal, valid in high level. + 26 + 1 + read-write + + + CAM_VSYNC_INV + CAM_VSYNC invert enable signal, valid in high level. + 27 + 1 + read-write + + + CAM_VH_DE_MODE_EN + 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC. + 28 + 1 + read-write + + + CAM_START + Camera module start signal. + 29 + 1 + read-write + + + CAM_RESET + Camera module reset signal. + 30 + 1 + write-only + + + CAM_AFIFO_RESET + Camera AFIFO reset signal. + 31 + 1 + write-only + + + + + CAM_RGB_YUV + CAM YUV/RGB converter configuration register. + 0xC + 0x20 + 0x00C00000 + + + CAM_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 21 + 1 + read-write + + + CAM_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + CAM_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + CAM_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + CAM_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + CAM_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + CAM_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + CAM_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + CAM_CONV_ENABLE + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_RGB_YUV + LCD YUV/RGB converter configuration register. + 0x10 + 0x20 + 0x00C00000 + + + LCD_CONV_8BITS_DATA_INV + 1:invert every two 8bits input data. 2. disabled. + 20 + 1 + read-write + + + LCD_CONV_TXTORX + 0: txtorx mode off. 1: txtorx mode on. + 21 + 1 + read-write + + + LCD_CONV_YUV2YUV_MODE + 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1. + 22 + 2 + read-write + + + LCD_CONV_YUV_MODE + 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in + 24 + 2 + read-write + + + LCD_CONV_PROTOCOL_MODE + 0:BT601. 1:BT709. + 26 + 1 + read-write + + + LCD_CONV_DATA_OUT_MODE + LIMIT or FULL mode of Data out. 0: limit. 1: full + 27 + 1 + read-write + + + LCD_CONV_DATA_IN_MODE + LIMIT or FULL mode of Data in. 0: limit. 1: full + 28 + 1 + read-write + + + LCD_CONV_MODE_8BITS_ON + 0: 16bits mode. 1: 8bits mode. + 29 + 1 + read-write + + + LCD_CONV_TRANS_MODE + 0: YUV to RGB. 1: RGB to YUV. + 30 + 1 + read-write + + + LCD_CONV_ENABLE + 0: Bypass converter. 1: Enable converter. + 31 + 1 + read-write + + + + + LCD_USER + LCD config register. + 0x14 + 0x20 + 0x00000001 + + + LCD_DOUT_CYCLELEN + The output data cycles minus 1 of LCD module. + 0 + 13 + read-write + + + LCD_ALWAYS_OUT_EN + LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set. + 13 + 1 + read-write + + + LCD_DOUT_BYTE_SWIZZLE_MODE + 0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA + 14 + 3 + read-write + + + LCD_DOUT_BYTE_SWIZZLE_ENABLE + 1: enable byte swizzle 0: disable + 17 + 1 + read-write + + + LCD_DOUT_BIT_ORDER + 1: change bit order in every byte. 0: Not change. + 18 + 1 + read-write + + + LCD_BYTE_MODE + 2: 24bit mode. 1: 16bit mode. 0: 8bit mode + 19 + 2 + read-write + + + LCD_UPDATE + 1: Update LCD registers, will be cleared by hardware. 0 : Not care. + 21 + 1 + read-write + + + LCD_BIT_ORDER + 1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change. + 22 + 1 + read-write + + + LCD_BYTE_ORDER + 1: invert data byte order, only valid in 2 byte mode. 0: Not change. + 23 + 1 + read-write + + + LCD_DOUT + 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable. + 24 + 1 + read-write + + + LCD_DUMMY + 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable. + 25 + 1 + read-write + + + LCD_CMD + 1: Be able to send command in LCD sequence when LCD starts. 0: Disable. + 26 + 1 + read-write + + + LCD_START + LCD start sending data enable signal, valid in high level. + 27 + 1 + read-write + + + LCD_RESET + The value of command. + 28 + 1 + write-only + + + LCD_DUMMY_CYCLELEN + The dummy cycle length minus 1. + 29 + 2 + read-write + + + LCD_CMD_2_CYCLE_EN + The cycle length of command phase. 1: 2 cycles. 0: 1 cycle. + 31 + 1 + read-write + + + + + LCD_MISC + LCD config register. + 0x18 + 0x20 + 0x000000C0 + + + LCD_WIRE_MODE + The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit + 4 + 2 + read-write + + + LCD_VFK_CYCLELEN + The setup cycle length minus 1 in LCD non-RGB mode. + 6 + 6 + read-write + + + LCD_VBK_CYCLELEN + The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode. + 12 + 13 + read-write + + + LCD_NEXT_FRAME_EN + 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out. + 25 + 1 + read-write + + + LCD_BK_EN + 1: Enable blank region when LCD sends data out. 0: No blank region. + 26 + 1 + read-write + + + LCD_AFIFO_RESET + LCD AFIFO reset signal. + 27 + 1 + write-only + + + LCD_CD_DATA_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge. + 28 + 1 + read-write + + + LCD_CD_DUMMY_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge. + 29 + 1 + read-write + + + LCD_CD_CMD_SET + 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge. + 30 + 1 + read-write + + + LCD_CD_IDLE_EDGE + The default value of LCD_CD. + 31 + 1 + read-write + + + + + LCD_CTRL + LCD config register. + 0x1C + 0x20 + + + LCD_HB_FRONT + It is the horizontal blank front porch of a frame. + 0 + 11 + read-write + + + LCD_VA_HEIGHT + It is the vertical active height of a frame. + 11 + 10 + read-write + + + LCD_VT_HEIGHT + It is the vertical total height of a frame. + 21 + 10 + read-write + + + LCD_RGB_MODE_EN + 1: Enable LCD RGB mode. 0: Disable LCD RGB mode. + 31 + 1 + read-write + + + + + LCD_CTRL1 + LCD config register. + 0x20 + 0x20 + + + LCD_VB_FRONT + It is the vertical blank front porch of a frame. + 0 + 8 + read-write + + + LCD_HA_WIDTH + It is the horizontal active width of a frame. + 8 + 12 + read-write + + + LCD_HT_WIDTH + It is the horizontal total width of a frame. + 20 + 12 + read-write + + + + + LCD_CTRL2 + LCD config register. + 0x24 + 0x20 + 0x00010001 + + + LCD_VSYNC_WIDTH + It is the position of LCD_VSYNC active pulse in a line. + 0 + 7 + read-write + + + LCD_VSYNC_IDLE_POL + It is the idle value of LCD_VSYNC. + 7 + 1 + read-write + + + LCD_DE_IDLE_POL + It is the idle value of LCD_DE. + 8 + 1 + read-write + + + LCD_HS_BLANK_EN + 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode. + 9 + 1 + read-write + + + LCD_HSYNC_WIDTH + It is the position of LCD_HSYNC active pulse in a line. + 16 + 7 + read-write + + + LCD_HSYNC_IDLE_POL + It is the idle value of LCD_HSYNC. + 23 + 1 + read-write + + + LCD_HSYNC_POSITION + It is the position of LCD_HSYNC active pulse in a line. + 24 + 8 + read-write + + + + + LCD_FIRST_CMD_VAL + LCD config register. + 0x28 + 0x20 + + + LCD_FIRST_CMD_VALUE + The LCD write command value of first cmd cycle. + 0 + 32 + read-write + + + + + LCD_LATTER_CMD_VAL + LCD config register. + 0x2C + 0x20 + + + LCD_LATTER_CMD_VALUE + The LCD write command value of latter cmd cycle. + 0 + 32 + read-write + + + + + LCD_DLY_MODE_CFG1 + LCD config register. + 0x30 + 0x20 + + + DOUT16_MODE + The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + DOUT17_MODE + The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + DOUT18_MODE + The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + DOUT19_MODE + The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + DOUT20_MODE + The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 8 + 2 + read-write + + + DOUT21_MODE + The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 10 + 2 + read-write + + + DOUT22_MODE + The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 12 + 2 + read-write + + + DOUT23_MODE + The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 14 + 2 + read-write + + + LCD_CD_MODE + The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 16 + 2 + read-write + + + LCD_DE_MODE + The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 18 + 2 + read-write + + + LCD_HSYNC_MODE + The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 20 + 2 + read-write + + + LCD_VSYNC_MODE + The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 22 + 2 + read-write + + + + + LCD_DLY_MODE_CFG2 + LCD config register. + 0x38 + 0x20 + + + DOUT0_MODE + The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 0 + 2 + read-write + + + DOUT1_MODE + The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 2 + 2 + read-write + + + DOUT2_MODE + The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 4 + 2 + read-write + + + DOUT3_MODE + The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 6 + 2 + read-write + + + DOUT4_MODE + The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 8 + 2 + read-write + + + DOUT5_MODE + The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 10 + 2 + read-write + + + DOUT6_MODE + The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 12 + 2 + read-write + + + DOUT7_MODE + The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 14 + 2 + read-write + + + DOUT8_MODE + The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 16 + 2 + read-write + + + DOUT9_MODE + The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 18 + 2 + read-write + + + DOUT10_MODE + The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 20 + 2 + read-write + + + DOUT11_MODE + The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 22 + 2 + read-write + + + DOUT12_MODE + The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 24 + 2 + read-write + + + DOUT13_MODE + The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 26 + 2 + read-write + + + DOUT14_MODE + The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 28 + 2 + read-write + + + DOUT15_MODE + The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK. + 30 + 2 + read-write + + + + + LC_DMA_INT_ENA + LCDCAM interrupt enable register. + 0x64 + 0x20 + + + LCD_VSYNC_INT_ENA + The enable bit for LCD frame end interrupt. + 0 + 1 + read-write + + + LCD_TRANS_DONE_INT_ENA + The enable bit for lcd transfer end interrupt. + 1 + 1 + read-write + + + CAM_VSYNC_INT_ENA + The enable bit for Camera frame end interrupt. + 2 + 1 + read-write + + + CAM_HS_INT_ENA + The enable bit for Camera line interrupt. + 3 + 1 + read-write + + + + + LC_DMA_INT_RAW + LCDCAM interrupt raw register, valid in level. + 0x68 + 0x20 + + + LCD_VSYNC_INT_RAW + The raw bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_RAW + The raw bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_RAW + The raw bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_RAW + The raw bit for Camera line interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_ST + LCDCAM interrupt status register. + 0x6C + 0x20 + + + LCD_VSYNC_INT_ST + The status bit for LCD frame end interrupt. + 0 + 1 + read-only + + + LCD_TRANS_DONE_INT_ST + The status bit for lcd transfer end interrupt. + 1 + 1 + read-only + + + CAM_VSYNC_INT_ST + The status bit for Camera frame end interrupt. + 2 + 1 + read-only + + + CAM_HS_INT_ST + The status bit for Camera transfer end interrupt. + 3 + 1 + read-only + + + + + LC_DMA_INT_CLR + LCDCAM interrupt clear register. + 0x70 + 0x20 + + + LCD_VSYNC_INT_CLR + The clear bit for LCD frame end interrupt. + 0 + 1 + write-only + + + LCD_TRANS_DONE_INT_CLR + The clear bit for lcd transfer end interrupt. + 1 + 1 + write-only + + + CAM_VSYNC_INT_CLR + The clear bit for Camera frame end interrupt. + 2 + 1 + write-only + + + CAM_HS_INT_CLR + The clear bit for Camera line interrupt. + 3 + 1 + write-only + + + + + LC_REG_DATE + Version register + 0xFC + 0x20 + 0x02303090 + + + LC_DATE + LCD_CAM version control register + 0 + 28 + read-write + + + + + + + LEDC + LED Control PWM (Pulse Width Modulation) + LEDC + 0x500D3000 + + 0x0 + 0x124 + registers + + + LEDC + 52 + + + + 8 + 0x14 + CH%s_CONF0 + Configuration register 0 for channel %s + 0x0 + 0x20 + + + TIMER_SEL_CH + Configures which timer is channel %s selected.\\0: Select timer0\\1: Select timer1\\2: Select timer2\\3: Select timer3 + 0 + 2 + read-write + + + SIG_OUT_EN_CH + Configures whether or not to enable signal output on channel %s.\\0: Signal output disable\\1: Signal output enable + 2 + 1 + read-write + + + IDLE_LV_CH + Configures the output value when channel %s is inactive. Valid only when LEDC_SIG_OUT_EN_CH%s is 0.\\0: Output level is low\\1: Output level is high + 3 + 1 + read-write + + + PARA_UP_CH + Configures whether or not to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update + 4 + 1 + write-only + + + OVF_NUM_CH + Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + 5 + 10 + read-write + + + OVF_CNT_EN_CH + Configures whether or not to enable the ovf_cnt of channel %s.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + OVF_CNT_RESET_CH + Configures whether or not to reset the ovf_cnt of channel %s.\\0: Invalid. No effect\\1: Reset the ovf_cnt + 16 + 1 + write-only + + + + + 8 + 0x14 + CH%s_HPOINT + High point register for channel %s + 0x4 + 0x20 + + + HPOINT_CH + Configures high point of signal output on channel %s. The output value changes to high when the selected timers has reached the value specified by this register. + 0 + 20 + read-write + + + + + 8 + 0x14 + CH%s_DUTY + Initial duty cycle register for channel %s + 0x8 + 0x20 + + + DUTY_CH + Configures the duty of signal output on channel %s. + 0 + 25 + read-write + + + + + 8 + 0x14 + CH%s_CONF1 + Configuration register 1 for channel %s + 0xC + 0x20 + + + DUTY_START_CH + Configures whether the duty cycle fading configurations take effect.\\0: Not take effect\\1: Take effect + 31 + 1 + read-write + + + + + 8 + 0x14 + CH%s_DUTY_R + Current duty cycle register for channel %s + 0x10 + 0x20 + + + DUTY_CH_R + Represents the current duty of output signal on channel %s. + 0 + 25 + read-only + + + + + 4 + 0x8 + TIMER%s_CONF + Timer %s configuration register + 0xA0 + 0x20 + 0x01000000 + + + TIMER_DUTY_RES + Configures the range of the counter in timer %s. + 0 + 5 + read-write + + + CLK_DIV_TIMER + Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part. + 5 + 18 + read-write + + + TIMER_PAUSE + Configures whether or not to pause the counter in timer %s.\\0: Normal\\1: Pause + 23 + 1 + read-write + + + TIMER_RST + Configures whether or not to reset timer %s. The counter will show 0 after reset.\\0: Not reset\\1: Reset + 24 + 1 + read-write + + + TICK_SEL_TIMER + Configures which clock is timer %s selected. Unused. + 25 + 1 + read-write + + + TIMER_PARA_UP + Configures whether or not to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.\\0: Invalid. No effect\\1: Update + 26 + 1 + write-only + + + + + 4 + 0x8 + TIMER%s_VALUE + Timer %s current counter value register + 0xA4 + 0x20 + + + TIMER_CNT + Represents the current counter value of timer %s. + 0 + 20 + read-only + + + + + INT_RAW + Interrupt raw status register + 0xC0 + 0x20 + + + TIMER0_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the timer0 has reached its maximum counter value. + 0 + 1 + read-write + + + TIMER1_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the timer1 has reached its maximum counter value. + 1 + 1 + read-write + + + TIMER2_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the timer2 has reached its maximum counter value. + 2 + 1 + read-write + + + TIMER3_OVF_INT_RAW + Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the timer3 has reached its maximum counter value. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered when the fading of duty has finished. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered when the fading of duty has finished. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered when the fading of duty has finished. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered when the fading of duty has finished. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered when the fading of duty has finished. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered when the fading of duty has finished. + 9 + 1 + read-write + + + DUTY_CHNG_END_CH6_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered when the fading of duty has finished. + 10 + 1 + read-write + + + DUTY_CHNG_END_CH7_INT_RAW + Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered when the fading of duty has finished. + 11 + 1 + read-write + + + OVF_CNT_CH0_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + 17 + 1 + read-write + + + OVF_CNT_CH6_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + 18 + 1 + read-write + + + OVF_CNT_CH7_INT_RAW + Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + 19 + 1 + read-write + + + + + INT_ST + Interrupt masked status register + 0xC4 + 0x20 + + + TIMER0_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only when LEDC_TIMER0_OVF_INT_ENA is set to 1. + 0 + 1 + read-only + + + TIMER1_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only when LEDC_TIMER1_OVF_INT_ENA is set to 1. + 1 + 1 + read-only + + + TIMER2_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only when LEDC_TIMER2_OVF_INT_ENA is set to 1. + 2 + 1 + read-only + + + TIMER3_OVF_INT_ST + Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only when LEDC_TIMER3_OVF_INT_ENA is set to 1. + 3 + 1 + read-only + + + DUTY_CHNG_END_CH0_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + 4 + 1 + read-only + + + DUTY_CHNG_END_CH1_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + 5 + 1 + read-only + + + DUTY_CHNG_END_CH2_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + 6 + 1 + read-only + + + DUTY_CHNG_END_CH3_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + 7 + 1 + read-only + + + DUTY_CHNG_END_CH4_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + 8 + 1 + read-only + + + DUTY_CHNG_END_CH5_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + 9 + 1 + read-only + + + DUTY_CHNG_END_CH6_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1. + 10 + 1 + read-only + + + DUTY_CHNG_END_CH7_INT_ST + Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1. + 11 + 1 + read-only + + + OVF_CNT_CH0_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + 12 + 1 + read-only + + + OVF_CNT_CH1_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + 13 + 1 + read-only + + + OVF_CNT_CH2_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + 14 + 1 + read-only + + + OVF_CNT_CH3_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + 15 + 1 + read-only + + + OVF_CNT_CH4_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + 16 + 1 + read-only + + + OVF_CNT_CH5_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + 17 + 1 + read-only + + + OVF_CNT_CH6_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + 18 + 1 + read-only + + + OVF_CNT_CH7_INT_ST + Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0xC8 + 0x20 + + + TIMER0_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT. + 0 + 1 + read-write + + + TIMER1_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT. + 1 + 1 + read-write + + + TIMER2_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT. + 2 + 1 + read-write + + + TIMER3_OVF_INT_ENA + Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT. + 3 + 1 + read-write + + + DUTY_CHNG_END_CH0_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT. + 4 + 1 + read-write + + + DUTY_CHNG_END_CH1_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT. + 5 + 1 + read-write + + + DUTY_CHNG_END_CH2_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT. + 6 + 1 + read-write + + + DUTY_CHNG_END_CH3_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT. + 7 + 1 + read-write + + + DUTY_CHNG_END_CH4_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT. + 8 + 1 + read-write + + + DUTY_CHNG_END_CH5_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT. + 9 + 1 + read-write + + + DUTY_CHNG_END_CH6_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT. + 10 + 1 + read-write + + + DUTY_CHNG_END_CH7_INT_ENA + Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT. + 11 + 1 + read-write + + + OVF_CNT_CH0_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT. + 12 + 1 + read-write + + + OVF_CNT_CH1_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT. + 13 + 1 + read-write + + + OVF_CNT_CH2_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT. + 14 + 1 + read-write + + + OVF_CNT_CH3_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT. + 15 + 1 + read-write + + + OVF_CNT_CH4_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT. + 16 + 1 + read-write + + + OVF_CNT_CH5_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT. + 17 + 1 + read-write + + + OVF_CNT_CH6_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT. + 18 + 1 + read-write + + + OVF_CNT_CH7_INT_ENA + Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0xCC + 0x20 + + + TIMER0_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT. + 0 + 1 + write-only + + + TIMER1_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT. + 1 + 1 + write-only + + + TIMER2_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT. + 2 + 1 + write-only + + + TIMER3_OVF_INT_CLR + Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT. + 3 + 1 + write-only + + + DUTY_CHNG_END_CH0_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT. + 4 + 1 + write-only + + + DUTY_CHNG_END_CH1_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT. + 5 + 1 + write-only + + + DUTY_CHNG_END_CH2_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT. + 6 + 1 + write-only + + + DUTY_CHNG_END_CH3_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT. + 7 + 1 + write-only + + + DUTY_CHNG_END_CH4_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT. + 8 + 1 + write-only + + + DUTY_CHNG_END_CH5_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT. + 9 + 1 + write-only + + + DUTY_CHNG_END_CH6_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT. + 10 + 1 + write-only + + + DUTY_CHNG_END_CH7_INT_CLR + Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT. + 11 + 1 + write-only + + + OVF_CNT_CH0_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT. + 12 + 1 + write-only + + + OVF_CNT_CH1_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT. + 13 + 1 + write-only + + + OVF_CNT_CH2_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT. + 14 + 1 + write-only + + + OVF_CNT_CH3_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT. + 15 + 1 + write-only + + + OVF_CNT_CH4_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT. + 16 + 1 + write-only + + + OVF_CNT_CH5_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT. + 17 + 1 + write-only + + + OVF_CNT_CH6_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT. + 18 + 1 + write-only + + + OVF_CNT_CH7_INT_CLR + Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT. + 19 + 1 + write-only + + + + + 8 + 0x4 + CH%s_GAMMA_CONF + Ledc ch%s gamma config register. + 0x100 + 0x20 + + + CH_GAMMA_ENTRY_NUM + Configures the number of duty cycle fading rages for LEDC ch%s. + 0 + 5 + read-write + + + CH_GAMMA_PAUSE + Configures whether or not to pause duty cycle fading of LEDC ch%s.\\0: Invalid. No effect\\1: Pause + 5 + 1 + write-only + + + CH_GAMMA_RESUME + Configures whether or nor to resume duty cycle fading of LEDC ch%s.\\0: Invalid. No effect\\1: Resume + 6 + 1 + write-only + + + + + EVT_TASK_EN0 + Ledc event task enable bit register0. + 0x120 + 0x20 + + + EVT_DUTY_CHNG_END_CH0_EN + Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH1_EN + Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH2_EN + Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH3_EN + Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH4_EN + Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH5_EN + Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH6_EN + Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + EVT_DUTY_CHNG_END_CH7_EN + Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH0_EN + Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH1_EN + Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH2_EN + Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH3_EN + Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH4_EN + Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH5_EN + Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH6_EN + Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + EVT_OVF_CNT_PLS_CH7_EN + Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + EVT_TIME_OVF_TIMER0_EN + Configures whether or not to enable the ledc_timer0_ovf event.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + EVT_TIME_OVF_TIMER1_EN + Configures whether or not to enable the ledc_timer1_ovf event.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + EVT_TIME_OVF_TIMER2_EN + Configures whether or not to enable the ledc_timer2_ovf event.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + EVT_TIME_OVF_TIMER3_EN + Configures whether or not to enable the ledc_timer3_ovf event.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + EVT_TIME0_CMP_EN + Configures whether or not to enable the ledc_timer0_cmp event.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + EVT_TIME1_CMP_EN + Configures whether or not to enable the ledc_timer1_cmp event.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + EVT_TIME2_CMP_EN + Configures whether or not to enable the ledc_timer2_cmp event.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + EVT_TIME3_CMP_EN + Configures whether or not to enable the ledc_timer3_cmp event.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH0_EN + Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH1_EN + Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH2_EN + Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH3_EN + Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH4_EN + Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH5_EN + Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH6_EN + Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\0: Disable\\1: Enable + 30 + 1 + read-write + + + TASK_DUTY_SCALE_UPDATE_CH7_EN + Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\0: Disable\\1: Enable + 31 + 1 + read-write + + + + + EVT_TASK_EN1 + Ledc event task enable bit register1. + 0x124 + 0x20 + + + TASK_TIMER0_RES_UPDATE_EN + Configures whether or not to enable ledc_timer0_res_update task.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TASK_TIMER1_RES_UPDATE_EN + Configures whether or not to enable ledc_timer1_res_update task.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TASK_TIMER2_RES_UPDATE_EN + Configures whether or not to enable ledc_timer2_res_update task.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TASK_TIMER3_RES_UPDATE_EN + Configures whether or not to enable ledc_timer3_res_update task.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TASK_TIMER0_CAP_EN + Configures whether or not to enable ledc_timer0_cap task.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TASK_TIMER1_CAP_EN + Configures whether or not to enable ledc_timer1_cap task.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TASK_TIMER2_CAP_EN + Configures whether or not to enable ledc_timer2_cap task.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TASK_TIMER3_CAP_EN + Configures whether or not to enable ledc_timer3_cap task.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH0_EN + Configures whether or not to enable ledc_ch0_sig_out_dis task.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH1_EN + Configures whether or not to enable ledc_ch1_sig_out_dis task.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH2_EN + Configures whether or not to enable ledc_ch2_sig_out_dis task.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH3_EN + Configures whether or not to enable ledc_ch3_sig_out_dis task.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH4_EN + Configures whether or not to enable ledc_ch4_sig_out_dis task.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH5_EN + Configures whether or not to enable ledc_ch5_sig_out_dis task.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH6_EN + Configures whether or not to enable ledc_ch6_sig_out_dis task.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + TASK_SIG_OUT_DIS_CH7_EN + Configures whether or not to enable ledc_ch7_sig_out_dis task.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + TASK_OVF_CNT_RST_CH0_EN + Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + TASK_OVF_CNT_RST_CH1_EN + Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + TASK_OVF_CNT_RST_CH2_EN + Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + TASK_OVF_CNT_RST_CH3_EN + Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + TASK_OVF_CNT_RST_CH4_EN + Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + TASK_OVF_CNT_RST_CH5_EN + Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + TASK_OVF_CNT_RST_CH6_EN + Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + TASK_OVF_CNT_RST_CH7_EN + Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + TASK_TIMER0_RST_EN + Configures whether or not to enable ledc_timer0_rst task.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + TASK_TIMER1_RST_EN + Configures whether or not to enable ledc_timer1_rst task.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + TASK_TIMER2_RST_EN + Configures whether or not to enable ledc_timer2_rst task.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + TASK_TIMER3_RST_EN + Configures whether or not to enable ledc_timer3_rst task.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + TASK_TIMER0_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer0_pause_resume task.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + TASK_TIMER1_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer1_pause_resume task.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + TASK_TIMER2_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer2_pause_resume task.\\0: Disable\\1: Enable + 30 + 1 + read-write + + + TASK_TIMER3_PAUSE_RESUME_EN + Configures whether or not to enable ledc_timer3_pause_resume task.\\0: Disable\\1: Enable + 31 + 1 + read-write + + + + + EVT_TASK_EN2 + Ledc event task enable bit register2. + 0x128 + 0x20 + + + TASK_GAMMA_RESTART_CH0_EN + Configures whether or not to enable ledc_ch0_gamma_restart task.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TASK_GAMMA_RESTART_CH1_EN + Configures whether or not to enable ledc_ch1_gamma_restart task.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TASK_GAMMA_RESTART_CH2_EN + Configures whether or not to enable ledc_ch2_gamma_restart task.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TASK_GAMMA_RESTART_CH3_EN + Configures whether or not to enable ledc_ch3_gamma_restart task.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TASK_GAMMA_RESTART_CH4_EN + Configures whether or not to enable ledc_ch4_gamma_restart task.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TASK_GAMMA_RESTART_CH5_EN + Configures whether or not to enable ledc_ch5_gamma_restart task.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TASK_GAMMA_RESTART_CH6_EN + Configures whether or not to enable ledc_ch6_gamma_restart task.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TASK_GAMMA_RESTART_CH7_EN + Configures whether or not to enable ledc_ch7_gamma_restart task.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH0_EN + Configures whether or not to enable ledc_ch0_gamma_pause task.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH1_EN + Configures whether or not to enable ledc_ch1_gamma_pause task.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH2_EN + Configures whether or not to enable ledc_ch2_gamma_pause task.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH3_EN + Configures whether or not to enable ledc_ch3_gamma_pause task.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH4_EN + Configures whether or not to enable ledc_ch4_gamma_pause task.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH5_EN + Configures whether or not to enable ledc_ch5_gamma_pause task.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH6_EN + Configures whether or not to enable ledc_ch6_gamma_pause task.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + TASK_GAMMA_PAUSE_CH7_EN + Configures whether or not to enable ledc_ch7_gamma_pause task.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + TASK_GAMMA_RESUME_CH0_EN + Configures whether or not to enable ledc_ch0_gamma_resume task.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + TASK_GAMMA_RESUME_CH1_EN + Configures whether or not to enable ledc_ch1_gamma_resume task.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + TASK_GAMMA_RESUME_CH2_EN + Configures whether or not to enable ledc_ch2_gamma_resume task.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + TASK_GAMMA_RESUME_CH3_EN + Configures whether or not to enable ledc_ch3_gamma_resume task.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + TASK_GAMMA_RESUME_CH4_EN + Configures whether or not to enable ledc_ch4_gamma_resume task.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + TASK_GAMMA_RESUME_CH5_EN + Configures whether or not to enable ledc_ch5_gamma_resume task.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + TASK_GAMMA_RESUME_CH6_EN + Configures whether or not to enable ledc_ch6_gamma_resume task.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + TASK_GAMMA_RESUME_CH7_EN + Configures whether or not to enable ledc_ch7_gamma_resume task.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + + + 4 + 0x4 + TIMER%s_CMP + Ledc timer%s compare value register. + 0x140 + 0x20 + + + TIMER_CMP + Configures the comparison value for LEDC timer%s. + 0 + 20 + read-write + + + + + 4 + 0x4 + TIMER%s_CNT_CAP + Ledc timer%s captured count value register. + 0x150 + 0x20 + + + TIMER_CNT_CAP + Represents the captured LEDC timer%s count value. + 0 + 20 + read-only + + + + + CONF + LEDC global configuration register + 0x170 + 0x20 + + + APB_CLK_SEL + Configures the clock source for the four timers.\\0: APB_CLK\\1: RC_FAST_CLK\\2: XTAL_CLK\\3: Invalid. No clock + 0 + 2 + read-write + + + GAMMA_RAM_CLK_EN_CH0 + Configures whether or not to open LEDC ch0 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram\\1: Force open the clock gate for LEDC ch0 gamma ram + 2 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH1 + Configures whether or not to open LEDC ch1 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram\\1: Force open the clock gate for LEDC ch1 gamma ram + 3 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH2 + Configures whether or not to open LEDC ch2 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram\\1: Force open the clock gate for LEDC ch2 gamma ram + 4 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH3 + Configures whether or not to open LEDC ch3 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram\\1: Force open the clock gate for LEDC ch3 gamma ram + 5 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH4 + Configures whether or not to open LEDC ch4 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram\\1: Force open the clock gate for LEDC ch4 gamma ram + 6 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH5 + Configures whether or not to open LEDC ch5 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram\\1: Force open the clock gate for LEDC ch5 gamma ram + 7 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH6 + Configures whether or not to open LEDC ch6 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram\\1: Force open the clock gate for LEDC ch6 gamma ram + 8 + 1 + read-write + + + GAMMA_RAM_CLK_EN_CH7 + Configures whether or not to open LEDC ch7 gamma ram clock gate.\\0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram\\1: Force open the clock gate for LEDC ch7 gamma ram + 9 + 1 + read-write + + + CLK_EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 31 + 1 + read-write + + + + + DATE + Version control register + 0x174 + 0x20 + 0x02303070 + + + LEDC_DATE + Configures the version. + 0 + 28 + read-write + + + + + + + LP_INTR + Low-power Interrupt Controller + LPINTR + 0x5012C000 + + 0x0 + 0x18 + registers + + + + SW_INT_RAW + need_des + 0x0 + 0x20 + + + LP_SW_INT_RAW + need_des + 31 + 1 + read-write + + + + + SW_INT_ST + need_des + 0x4 + 0x20 + + + LP_SW_INT_ST + need_des + 31 + 1 + read-only + + + + + SW_INT_ENA + need_des + 0x8 + 0x20 + + + LP_SW_INT_ENA + need_des + 31 + 1 + read-write + + + + + SW_INT_CLR + need_des + 0xC + 0x20 + + + LP_SW_INT_CLR + need_des + 31 + 1 + write-only + + + + + STATUS + need_des + 0x10 + 0x20 + + + LP_HUK_INTR_ST + need_des + 10 + 1 + read-only + + + SYSREG_INTR_ST + need_des + 11 + 1 + read-only + + + LP_SW_INTR_ST + need_des + 12 + 1 + read-only + + + LP_EFUSE_INTR_ST + need_des + 13 + 1 + read-only + + + LP_UART_INTR_ST + need_des + 14 + 1 + read-only + + + LP_TSENS_INTR_ST + need_des + 15 + 1 + read-only + + + LP_TOUCH_INTR_ST + need_des + 16 + 1 + read-only + + + LP_SPI_INTR_ST + need_des + 17 + 1 + read-only + + + LP_I2S_INTR_ST + need_des + 18 + 1 + read-only + + + LP_I2C_INTR_ST + need_des + 19 + 1 + read-only + + + LP_GPIO_INTR_ST + need_des + 20 + 1 + read-only + + + LP_ADC_INTR_ST + need_des + 21 + 1 + read-only + + + ANAPERI_INTR_ST + need_des + 22 + 1 + read-only + + + PMU_REG_1_INTR_ST + need_des + 23 + 1 + read-only + + + PMU_REG_0_INTR_ST + need_des + 24 + 1 + read-only + + + MB_LP_INTR_ST + need_des + 25 + 1 + read-only + + + MB_HP_INTR_ST + need_des + 26 + 1 + read-only + + + LP_TIMER_REG_1_INTR_ST + need_des + 27 + 1 + read-only + + + LP_TIMER_REG_0_INTR_ST + need_des + 28 + 1 + read-only + + + LP_WDT_INTR_ST + need_des + 29 + 1 + read-only + + + LP_RTC_INTR_ST + need_des + 30 + 1 + read-only + + + HP_INTR_ST + need_des + 31 + 1 + read-only + + + + + DATE + need_des + 0x3FC + 0x20 + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_PERI + LP_PERI Peripheral + LPPERI + 0x50120000 + + 0x0 + 0x2C + registers + + + + CLK_EN + need_des + 0x0 + 0x20 + 0x7FFF0000 + + + CK_EN_RNG + need_des + 16 + 1 + read-write + + + CK_EN_LP_TSENS + need_des + 17 + 1 + read-write + + + CK_EN_LP_PMS + need_des + 18 + 1 + read-write + + + CK_EN_LP_EFUSE + need_des + 19 + 1 + read-write + + + CK_EN_LP_IOMUX + need_des + 20 + 1 + read-write + + + CK_EN_LP_TOUCH + need_des + 21 + 1 + read-write + + + CK_EN_LP_SPI + need_des + 22 + 1 + read-write + + + CK_EN_LP_ADC + need_des + 23 + 1 + read-write + + + CK_EN_LP_I2S_TX + need_des + 24 + 1 + read-write + + + CK_EN_LP_I2S_RX + need_des + 25 + 1 + read-write + + + CK_EN_LP_I2S + need_des + 26 + 1 + read-write + + + CK_EN_LP_I2CMST + need_des + 27 + 1 + read-write + + + CK_EN_LP_I2C + need_des + 28 + 1 + read-write + + + CK_EN_LP_UART + need_des + 29 + 1 + read-write + + + CK_EN_LP_INTR + need_des + 30 + 1 + read-write + + + CK_EN_LP_CORE + write 1 to force on lp_core clk + 31 + 1 + read-write + + + + + CORE_CLK_SEL + need_des + 0x4 + 0x20 + + + LP_I2S_TX_CLK_SEL + need_des + 24 + 2 + read-write + + + LP_I2S_RX_CLK_SEL + need_des + 26 + 2 + read-write + + + LP_I2C_CLK_SEL + need_des + 28 + 2 + read-write + + + LP_UART_CLK_SEL + need_des + 30 + 2 + read-write + + + + + RESET_EN + need_des + 0x8 + 0x20 + + + RST_EN_LP_TSENS + need_des + 18 + 1 + read-write + + + RST_EN_LP_PMS + need_des + 19 + 1 + read-write + + + RST_EN_LP_EFUSE + need_des + 20 + 1 + read-write + + + RST_EN_LP_IOMUX + need_des + 21 + 1 + read-write + + + RST_EN_LP_TOUCH + need_des + 22 + 1 + read-write + + + RST_EN_LP_SPI + need_des + 23 + 1 + read-write + + + RST_EN_LP_ADC + need_des + 24 + 1 + read-write + + + RST_EN_LP_I2S + need_des + 25 + 1 + read-write + + + RST_EN_LP_I2CMST + need_des + 26 + 1 + read-write + + + RST_EN_LP_I2C + need_des + 27 + 1 + read-write + + + RST_EN_LP_UART + need_des + 28 + 1 + read-write + + + RST_EN_LP_INTR + need_des + 29 + 1 + read-write + + + RST_EN_LP_ROM + need_des + 30 + 1 + read-write + + + RST_EN_LP_CORE + need_des + 31 + 1 + write-only + + + + + CPU + need_des + 0xC + 0x20 + 0x80000000 + + + LPCORE_DBGM_UNAVAILABLE + need_des + 31 + 1 + read-write + + + + + MEM_CTRL + need_des + 0x28 + 0x20 + 0x80000000 + + + LP_UART_WAKEUP_FLAG_CLR + need_des + 0 + 1 + write-only + + + LP_UART_WAKEUP_FLAG + need_des + 1 + 1 + read-write + + + LP_UART_WAKEUP_EN + need_des + 29 + 1 + read-write + + + LP_UART_MEM_FORCE_PD + need_des + 30 + 1 + read-write + + + LP_UART_MEM_FORCE_PU + need_des + 31 + 1 + read-write + + + + + ADC_CTRL + need_des + 0x2C + 0x20 + 0x04040400 + + + SAR2_CLK_FORCE_ON + need_des + 6 + 1 + read-write + + + SAR1_CLK_FORCE_ON + need_des + 7 + 1 + read-write + + + LPADC_FUNC_DIV_NUM + need_des + 8 + 8 + read-write + + + LPADC_SAR2_DIV_NUM + need_des + 16 + 8 + read-write + + + LPADC_SAR1_DIV_NUM + need_des + 24 + 8 + read-write + + + + + LP_I2S_RXCLK_DIV_NUM + need_des + 0x30 + 0x20 + 0x02000000 + + + LP_I2S_RX_CLKM_DIV_NUM + need_des + 24 + 8 + read-write + + + + + LP_I2S_RXCLK_DIV_XYZ + need_des + 0x34 + 0x20 + 0x00004000 + + + LP_I2S_RX_CLKM_DIV_YN1 + need_des + 4 + 1 + read-write + + + LP_I2S_RX_CLKM_DIV_Z + need_des + 5 + 9 + read-write + + + LP_I2S_RX_CLKM_DIV_Y + need_des + 14 + 9 + read-write + + + LP_I2S_RX_CLKM_DIV_X + need_des + 23 + 9 + read-write + + + + + LP_I2S_TXCLK_DIV_NUM + need_des + 0x38 + 0x20 + 0x02000000 + + + LP_I2S_TX_CLKM_DIV_NUM + need_des + 24 + 8 + read-write + + + + + LP_I2S_TXCLK_DIV_XYZ + need_des + 0x3C + 0x20 + 0x00004000 + + + LP_I2S_TX_CLKM_DIV_YN1 + need_des + 4 + 1 + read-write + + + LP_I2S_TX_CLKM_DIV_Z + need_des + 5 + 9 + read-write + + + LP_I2S_TX_CLKM_DIV_Y + need_des + 14 + 9 + read-write + + + LP_I2S_TX_CLKM_DIV_X + need_des + 23 + 9 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_SYS + LP_SYS Peripheral + LPSYSREG + 0x50110000 + + 0x0 + 0x110 + registers + + + LP_SYS + 19 + + + + LP_SYS_VER_DATE + need_des + 0x0 + 0x20 + 0x20230509 + + + VER_DATE + need_des + 0 + 32 + read-write + + + + + CLK_SEL_CTRL + need_des + 0x4 + 0x20 + + + ENA_SW_SEL_SYS_CLK + reserved + 16 + 1 + read-write + + + SW_SYS_CLK_SRC_SEL + reserved + 17 + 1 + read-write + + + + + SYS_CTRL + need_des + 0x8 + 0x20 + 0x1FFFC7F8 + + + LP_CORE_DISABLE + lp cpu disable + 0 + 1 + read-write + + + SYS_SW_RST + digital system software reset bit + 1 + 1 + write-only + + + FORCE_DOWNLOAD_BOOT + need_des + 2 + 1 + read-write + + + DIG_FIB + need_des + 3 + 8 + read-write + + + IO_MUX_RESET_DISABLE + reset disable bit for LP IOMUX + 11 + 1 + read-write + + + ANA_FIB + need_des + 14 + 7 + read-only + + + LP_FIB_SEL + need_des + 21 + 8 + read-write + + + LP_CORE_ETM_WAKEUP_FLAG_CLR + need_des + 29 + 1 + write-only + + + LP_CORE_ETM_WAKEUP_FLAG + need_des + 30 + 1 + read-write + + + SYSTIMER_STALL_SEL + 0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from hp_core1 + 31 + 1 + read-write + + + + + LP_CLK_CTRL + need_des + 0xC + 0x20 + 0x00004001 + + + CLK_EN + need_des + 0 + 1 + read-write + + + LP_FOSC_HP_CKEN + reserved + 14 + 1 + read-write + + + + + LP_RST_CTRL + need_des + 0x10 + 0x20 + 0x00000003 + + + ANA_RST_BYPASS + analog source reset bypass : wdt,brown out,super wdt,glitch + 0 + 1 + read-write + + + SYS_RST_BYPASS + system source reset bypass : software reset,hp wdt,lp wdt,efuse + 1 + 1 + read-write + + + EFUSE_FORCE_NORST + efuse force no reset control + 2 + 1 + read-write + + + + + LP_CORE_BOOT_ADDR + need_des + 0x18 + 0x20 + 0x50100000 + + + LP_CPU_BOOT_ADDR + need_des + 0 + 32 + read-write + + + + + EXT_WAKEUP1 + need_des + 0x1C + 0x20 + + + SEL + Bitmap to select RTC pads for ext wakeup1 + 0 + 16 + read-write + + + STATUS_CLR + clear ext wakeup1 status + 16 + 1 + write-only + + + + + EXT_WAKEUP1_STATUS + need_des + 0x20 + 0x20 + + + EXT_WAKEUP1_STATUS + ext wakeup1 status + 0 + 16 + read-only + + + + + LP_TCM_PWR_CTRL + need_des + 0x24 + 0x20 + + + LP_TCM_ROM_CLK_FORCE_ON + need_des + 5 + 1 + read-write + + + LP_TCM_RAM_CLK_FORCE_ON + need_des + 7 + 1 + read-write + + + + + BOOT_ADDR_HP_LP + need_des + 0x28 + 0x20 + + + BOOT_ADDR_HP_LP + need_des + 0 + 32 + read-write + + + + + LP_STORE0 + need_des + 0x2C + 0x20 + + + LP_SCRATCH0 + need_des + 0 + 32 + read-write + + + + + LP_STORE1 + need_des + 0x30 + 0x20 + + + LP_SCRATCH1 + need_des + 0 + 32 + read-write + + + + + LP_STORE2 + need_des + 0x34 + 0x20 + + + LP_SCRATCH2 + need_des + 0 + 32 + read-write + + + + + LP_STORE3 + need_des + 0x38 + 0x20 + + + LP_SCRATCH3 + need_des + 0 + 32 + read-write + + + + + LP_STORE4 + need_des + 0x3C + 0x20 + + + LP_SCRATCH4 + need_des + 0 + 32 + read-write + + + + + LP_STORE5 + need_des + 0x40 + 0x20 + + + LP_SCRATCH5 + need_des + 0 + 32 + read-write + + + + + LP_STORE6 + need_des + 0x44 + 0x20 + + + LP_SCRATCH6 + need_des + 0 + 32 + read-write + + + + + LP_STORE7 + need_des + 0x48 + 0x20 + + + LP_SCRATCH7 + need_des + 0 + 32 + read-write + + + + + LP_STORE8 + need_des + 0x4C + 0x20 + + + LP_SCRATCH8 + need_des + 0 + 32 + read-write + + + + + LP_STORE9 + need_des + 0x50 + 0x20 + + + LP_SCRATCH9 + need_des + 0 + 32 + read-write + + + + + LP_STORE10 + need_des + 0x54 + 0x20 + + + LP_SCRATCH10 + need_des + 0 + 32 + read-write + + + + + LP_STORE11 + need_des + 0x58 + 0x20 + + + LP_SCRATCH11 + need_des + 0 + 32 + read-write + + + + + LP_STORE12 + need_des + 0x5C + 0x20 + + + LP_SCRATCH12 + need_des + 0 + 32 + read-write + + + + + LP_STORE13 + need_des + 0x60 + 0x20 + + + LP_SCRATCH13 + need_des + 0 + 32 + read-write + + + + + LP_STORE14 + need_des + 0x64 + 0x20 + + + LP_SCRATCH14 + need_des + 0 + 32 + read-write + + + + + LP_STORE15 + need_des + 0x68 + 0x20 + + + LP_SCRATCH15 + need_des + 0 + 32 + read-write + + + + + LP_PROBEA_CTRL + need_des + 0x6C + 0x20 + + + PROBE_A_MOD_SEL + need_des + 0 + 16 + read-write + + + PROBE_A_TOP_SEL + need_des + 16 + 8 + read-write + + + PROBE_L_SEL + need_des + 24 + 2 + read-write + + + PROBE_H_SEL + need_des + 26 + 2 + read-write + + + PROBE_GLOBAL_EN + need_des + 28 + 1 + read-write + + + + + LP_PROBEB_CTRL + need_des + 0x70 + 0x20 + + + PROBE_B_MOD_SEL + need_des + 0 + 16 + read-write + + + PROBE_B_TOP_SEL + need_des + 16 + 8 + read-write + + + PROBE_B_EN + need_des + 24 + 1 + read-write + + + + + LP_PROBE_OUT + need_des + 0x74 + 0x20 + + + PROBE_TOP_OUT + need_des + 0 + 32 + read-only + + + + + F2S_APB_BRG_CNTL + need_des + 0x9C + 0x20 + + + F2S_APB_POSTW_EN + reserved + 0 + 1 + read-write + + + + + USB_CTRL + need_des + 0x100 + 0x20 + + + SW_HW_USB_PHY_SEL + need_des + 0 + 1 + read-write + + + SW_USB_PHY_SEL + need_des + 1 + 1 + read-write + + + USBOTG20_WAKEUP_CLR + clear usb wakeup to PMU. + 2 + 1 + write-only + + + USBOTG20_IN_SUSPEND + indicate usb otg2.0 is in suspend state. + 3 + 1 + read-write + + + + + ANA_XPD_PAD_GROUP + need_des + 0x10C + 0x20 + 0x000000FF + + + ANA_REG_XPD_PAD_GROUP + Set 1 to power up pad group + 0 + 8 + read-write + + + + + LP_TCM_RAM_RDN_ECO_CS + need_des + 0x110 + 0x20 + + + LP_TCM_RAM_RDN_ECO_EN + need_des + 0 + 1 + read-write + + + LP_TCM_RAM_RDN_ECO_RESULT + need_des + 1 + 1 + read-only + + + + + LP_TCM_RAM_RDN_ECO_LOW + need_des + 0x114 + 0x20 + + + LP_TCM_RAM_RDN_ECO_LOW + need_des + 0 + 32 + read-write + + + + + LP_TCM_RAM_RDN_ECO_HIGH + need_des + 0x118 + 0x20 + 0xFFFFFFFF + + + LP_TCM_RAM_RDN_ECO_HIGH + need_des + 0 + 32 + read-write + + + + + LP_TCM_ROM_RDN_ECO_CS + need_des + 0x11C + 0x20 + + + LP_TCM_ROM_RDN_ECO_EN + need_des + 0 + 1 + read-write + + + LP_TCM_ROM_RDN_ECO_RESULT + need_des + 1 + 1 + read-only + + + + + LP_TCM_ROM_RDN_ECO_LOW + need_des + 0x120 + 0x20 + + + LP_TCM_ROM_RDN_ECO_LOW + need_des + 0 + 32 + read-write + + + + + LP_TCM_ROM_RDN_ECO_HIGH + need_des + 0x124 + 0x20 + 0xFFFFFFFF + + + LP_TCM_ROM_RDN_ECO_HIGH + need_des + 0 + 32 + read-write + + + + + HP_ROOT_CLK_CTRL + need_des + 0x130 + 0x20 + 0x00000003 + + + CPU_CLK_EN + clock gate enable for hp cpu root 400M clk + 0 + 1 + read-write + + + SYS_CLK_EN + clock gate enable for hp sys root 480M clk + 1 + 1 + read-write + + + + + LP_PMU_RDN_ECO_LOW + need_des + 0x138 + 0x20 + + + PMU_RDN_ECO_LOW + need_des + 0 + 32 + read-write + + + + + LP_PMU_RDN_ECO_HIGH + need_des + 0x13C + 0x20 + 0xFFFFFFFF + + + PMU_RDN_ECO_HIGH + need_des + 0 + 32 + read-write + + + + + PAD_COMP0 + need_des + 0x148 + 0x20 + + + DREF_COMP0 + pad comp dref + 0 + 3 + read-write + + + MODE_COMP0 + pad comp mode + 3 + 1 + read-write + + + XPD_COMP0 + pad comp xpd + 4 + 1 + read-write + + + + + PAD_COMP1 + need_des + 0x14C + 0x20 + + + DREF_COMP1 + pad comp dref + 0 + 3 + read-write + + + MODE_COMP1 + pad comp mode + 3 + 1 + read-write + + + XPD_COMP1 + pad comp xpd + 4 + 1 + read-write + + + + + BACKUP_DMA_CFG0 + need_des + 0x154 + 0x20 + 0x1906414A + + + BURST_LIMIT_AON + need_des + 0 + 5 + read-write + + + READ_INTERVAL_AON + need_des + 5 + 7 + read-write + + + LINK_BACKUP_TOUT_THRES_AON + need_des + 12 + 10 + read-write + + + LINK_TOUT_THRES_AON + need_des + 22 + 10 + read-write + + + + + BACKUP_DMA_CFG1 + need_des + 0x158 + 0x20 + + + AON_BYPASS + need_des + 31 + 1 + read-write + + + + + BACKUP_DMA_CFG2 + need_des + 0x15C + 0x20 + + + LINK_ADDR_AON + need_des + 0 + 32 + read-write + + + + + BOOT_ADDR_HP_CORE1 + need_des + 0x164 + 0x20 + + + BOOT_ADDR_HP_CORE1 + need_des + 0 + 32 + read-write + + + + + LP_ADDRHOLE_ADDR + need_des + 0x168 + 0x20 + + + LP_ADDRHOLE_ADDR + need_des + 0 + 32 + read-only + + + + + LP_ADDRHOLE_INFO + need_des + 0x16C + 0x20 + + + LP_ADDRHOLE_ID + master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma. + 0 + 5 + read-only + + + LP_ADDRHOLE_WR + 1:write trans, 0: read trans. + 5 + 1 + read-only + + + LP_ADDRHOLE_SECURE + 1: illegal address access, 0: access without permission + 6 + 1 + read-only + + + + + INT_RAW + raw interrupt register + 0x170 + 0x20 + + + LP_ADDRHOLE_INT_RAW + the raw interrupt status of lp addrhole(for lp peri and lp ram tee apm, and lp matrix default slave) + 0 + 1 + read-only + + + IDBUS_ADDRHOLE_INT_RAW + the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + 1 + 1 + read-only + + + LP_CORE_AHB_TIMEOUT_INT_RAW + the raw interrupt status of lp core ahb bus timeout + 2 + 1 + read-only + + + LP_CORE_IBUS_TIMEOUT_INT_RAW + the raw interrupt status of lp core ibus timeout + 3 + 1 + read-only + + + LP_CORE_DBUS_TIMEOUT_INT_RAW + the raw interrupt status of lp core dbus timeout + 4 + 1 + read-only + + + ETM_TASK_ULP_INT_RAW + the raw interrupt status of etm task ulp + 5 + 1 + read-only + + + SLOW_CLK_TICK_INT_RAW + the raw interrupt status of slow_clk_tick + 6 + 1 + read-only + + + + + INT_ST + masked interrupt register + 0x174 + 0x20 + + + LP_ADDRHOLE_INT_ST + the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp matrix default slave) + 0 + 1 + read-only + + + IDBUS_ADDRHOLE_INT_ST + the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + 1 + 1 + read-only + + + LP_CORE_AHB_TIMEOUT_INT_ST + the masked interrupt status of lp core ahb bus timeout + 2 + 1 + read-only + + + LP_CORE_IBUS_TIMEOUT_INT_ST + the masked interrupt status of lp core ibus timeout + 3 + 1 + read-only + + + LP_CORE_DBUS_TIMEOUT_INT_ST + the masked interrupt status of lp core dbus timeout + 4 + 1 + read-only + + + ETM_TASK_ULP_INT_ST + the masked interrupt status of etm task ulp + 5 + 1 + read-only + + + SLOW_CLK_TICK_INT_ST + the masked interrupt status of slow_clk_tick + 6 + 1 + read-only + + + + + INT_ENA + masked interrupt register + 0x178 + 0x20 + + + LP_ADDRHOLE_INT_ENA + Write 1 to enable lp addrhole int + 0 + 1 + read-write + + + IDBUS_ADDRHOLE_INT_ENA + Write 1 to enable idbus addrhole int + 1 + 1 + read-write + + + LP_CORE_AHB_TIMEOUT_INT_ENA + Write 1 to enable lp_core_ahb_timeout int + 2 + 1 + read-write + + + LP_CORE_IBUS_TIMEOUT_INT_ENA + Write 1 to enable lp_core_ibus_timeout int + 3 + 1 + read-write + + + LP_CORE_DBUS_TIMEOUT_INT_ENA + Write 1 to enable lp_core_dbus_timeout int + 4 + 1 + read-write + + + ETM_TASK_ULP_INT_ENA + Write 1 to enable etm task ulp int + 5 + 1 + read-write + + + SLOW_CLK_TICK_INT_ENA + Write 1 to enable slow_clk_tick int + 6 + 1 + read-write + + + + + INT_CLR + interrupt clear register + 0x17C + 0x20 + + + LP_ADDRHOLE_INT_CLR + write 1 to clear lp addrhole int + 0 + 1 + write-only + + + IDBUS_ADDRHOLE_INT_CLR + write 1 to clear idbus addrhole int + 1 + 1 + write-only + + + LP_CORE_AHB_TIMEOUT_INT_CLR + Write 1 to clear lp_core_ahb_timeout int + 2 + 1 + write-only + + + LP_CORE_IBUS_TIMEOUT_INT_CLR + Write 1 to clear lp_core_ibus_timeout int + 3 + 1 + write-only + + + LP_CORE_DBUS_TIMEOUT_INT_CLR + Write 1 to clear lp_core_dbus_timeout int + 4 + 1 + write-only + + + ETM_TASK_ULP_INT_CLR + Write 1 to clear etm tasl ulp int + 5 + 1 + write-only + + + SLOW_CLK_TICK_INT_CLR + Write 1 to clear slow_clk_tick int + 6 + 1 + write-only + + + + + HP_MEM_AUX_CTRL + need_des + 0x180 + 0x20 + 0x00002070 + + + HP_MEM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + LP_MEM_AUX_CTRL + need_des + 0x184 + 0x20 + 0x00002070 + + + LP_MEM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + HP_ROM_AUX_CTRL + need_des + 0x188 + 0x20 + 0x00000070 + + + HP_ROM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + LP_ROM_AUX_CTRL + need_des + 0x18C + 0x20 + 0x00000070 + + + LP_ROM_AUX_CTRL + need_des + 0 + 32 + read-write + + + + + LP_CPU_DBG_PC + need_des + 0x190 + 0x20 + + + LP_CPU_DBG_PC + need_des + 0 + 32 + read-only + + + + + LP_CPU_EXC_PC + need_des + 0x194 + 0x20 + + + LP_CPU_EXC_PC + need_des + 0 + 32 + read-only + + + + + IDBUS_ADDRHOLE_ADDR + need_des + 0x198 + 0x20 + + + IDBUS_ADDRHOLE_ADDR + need_des + 0 + 32 + read-only + + + + + IDBUS_ADDRHOLE_INFO + need_des + 0x19C + 0x20 + + + IDBUS_ADDRHOLE_ID + need_des + 0 + 5 + read-only + + + IDBUS_ADDRHOLE_WR + need_des + 5 + 1 + read-only + + + IDBUS_ADDRHOLE_SECURE + need_des + 6 + 1 + read-only + + + + + HP_POR_RST_BYPASS_CTRL + need_des + 0x1A0 + 0x20 + 0xFF00FF00 + + + HP_PO_CNNT_RSTN_BYPASS_CTRL + [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn +[14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn +[13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn +[12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn +[11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst +[10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst +[9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn +[8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn + 8 + 8 + read-write + + + HP_PO_RSTN_BYPASS_CTRL + [31] 1'b1: po_rstn bypass sys_sw_rstn +[30] 1'b1: po_rstn bypass hp_wdt_sys_rstn +[29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn +[28] 1'b1: po_rstn bypass hp_sdio_sys_rstn +[27] 1'b1: po_rstn bypass usb_jtag_chip_rst +[26] 1'b1: po_rstn bypass usb_uart_chip_rst +[25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn +[24] 1'b1: po_rstn bypass efuse_err_rstn + 24 + 8 + read-write + + + + + RNG_DATA + rng data register + 0x1A4 + 0x20 + + + RND_DATA + result of rng output + 0 + 32 + read-only + + + + + LP_CORE_AHB_TIMEOUT + need_des + 0x1B0 + 0x20 + 0x007FFFFF + + + EN + set this field to 1 to enable lp core ahb timeout handle + 0 + 1 + read-write + + + THRES + This field used to set lp core ahb bus timeout threshold + 1 + 16 + read-write + + + LP2HP_AHB_TIMEOUT_EN + set this field to 1 to enable lp2hp ahb timeout handle + 17 + 1 + read-write + + + LP2HP_AHB_TIMEOUT_THRES + This field used to set lp2hp ahb bus timeout threshold + 18 + 5 + read-write + + + + + LP_CORE_IBUS_TIMEOUT + need_des + 0x1B4 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable lp core ibus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set lp core ibus timeout threshold + 1 + 16 + read-write + + + + + LP_CORE_DBUS_TIMEOUT + need_des + 0x1B8 + 0x20 + 0x0001FFFF + + + EN + set this field to 1 to enable lp core dbus timeout handle + 0 + 1 + read-write + + + THRES + This field used to set lp core dbus timeout threshold + 1 + 16 + read-write + + + + + LP_CORE_ERR_RESP_DIS + need_des + 0x1BC + 0x20 + + + LP_CORE_ERR_RESP_DIS + Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to disable ahb err resp. + 0 + 3 + read-write + + + + + RNG_CFG + rng cfg register + 0x1C0 + 0x20 + 0x00000003 + + + RNG_TIMER_EN + enable rng timer + 0 + 1 + read-write + + + RNG_TIMER_PSCALE + configure ng timer pscale + 1 + 8 + read-write + + + RNG_SAR_ENABLE + enable rng_saradc + 9 + 1 + read-write + + + RNG_SAR_DATA + debug rng sar sample cnt + 16 + 13 + read-only + + + + + + + LP_ANA_PERI + LP_ANA_PERI Peripheral + LP_ANA_PERI + 0x50113000 + + 0x0 + 0x140 + registers + + + LP_ANA + 8 + + + + LP_ANA_BOD_MODE0_CNTL + need_des + 0x0 + 0x20 + 0x0FFC0100 + + + LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA + need_des + 6 + 1 + read-write + + + LP_ANA_BOD_MODE0_PD_RF_ENA + need_des + 7 + 1 + read-write + + + LP_ANA_BOD_MODE0_INTR_WAIT + need_des + 8 + 10 + read-write + + + LP_ANA_BOD_MODE0_RESET_WAIT + need_des + 18 + 10 + read-write + + + LP_ANA_BOD_MODE0_CNT_CLR + need_des + 28 + 1 + read-write + + + LP_ANA_BOD_MODE0_INTR_ENA + need_des + 29 + 1 + read-write + + + LP_ANA_BOD_MODE0_RESET_SEL + need_des + 30 + 1 + read-write + + + LP_ANA_BOD_MODE0_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_BOD_MODE1_CNTL + need_des + 0x4 + 0x20 + + + LP_ANA_BOD_MODE1_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_VDD_SOURCE_CNTL + need_des + 0x8 + 0x20 + 0x040000FF + + + LP_ANA_DETMODE_SEL + need_des + 0 + 8 + read-write + + + LP_ANA_VGOOD_EVENT_RECORD + need_des + 8 + 8 + read-only + + + LP_ANA_VBAT_EVENT_RECORD_CLR + need_des + 16 + 8 + write-only + + + LP_ANA_BOD_SOURCE_ENA + need_des + 24 + 8 + read-write + + + + + LP_ANA_VDDBAT_BOD_CNTL + need_des + 0xC + 0x20 + 0xFFC00000 + + + LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG + need_des + 0 + 1 + read-only + + + LP_ANA_VDDBAT_CHARGER + need_des + 10 + 1 + read-write + + + LP_ANA_VDDBAT_CNT_CLR + need_des + 11 + 1 + read-write + + + LP_ANA_VDDBAT_UPVOLTAGE_TARGET + need_des + 12 + 10 + read-write + + + LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET + need_des + 22 + 10 + read-write + + + + + LP_ANA_VDDBAT_CHARGE_CNTL + need_des + 0x10 + 0x20 + 0xFFC00000 + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG + need_des + 0 + 1 + read-only + + + LP_ANA_VDDBAT_CHARGE_CHARGER + need_des + 10 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_CNT_CLR + need_des + 11 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET + need_des + 12 + 10 + read-write + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET + need_des + 22 + 10 + read-write + + + + + LP_ANA_CK_GLITCH_CNTL + need_des + 0x14 + 0x20 + + + LP_ANA_CK_GLITCH_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_PG_GLITCH_CNTL + need_des + 0x18 + 0x20 + + + LP_ANA_POWER_GLITCH_RESET_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_FIB_ENABLE + need_des + 0x1C + 0x20 + 0xFFFFFFFF + + + LP_ANA_ANA_FIB_ENA + need_des + 0 + 32 + read-write + + + + + LP_ANA_INT_RAW + need_des + 0x20 + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW + need_des + 27 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW + need_des + 28 + 1 + read-write + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW + need_des + 29 + 1 + read-write + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW + need_des + 30 + 1 + read-write + + + LP_ANA_BOD_MODE0_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_ANA_INT_ST + need_des + 0x24 + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST + need_des + 27 + 1 + read-only + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST + need_des + 28 + 1 + read-only + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_ST + need_des + 29 + 1 + read-only + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST + need_des + 30 + 1 + read-only + + + LP_ANA_BOD_MODE0_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_ANA_INT_ENA + need_des + 0x28 + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA + need_des + 27 + 1 + read-write + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA + need_des + 28 + 1 + read-write + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA + need_des + 29 + 1 + read-write + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA + need_des + 30 + 1 + read-write + + + LP_ANA_BOD_MODE0_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_INT_CLR + need_des + 0x2C + 0x20 + + + LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR + need_des + 27 + 1 + write-only + + + LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR + need_des + 28 + 1 + write-only + + + LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR + need_des + 29 + 1 + write-only + + + LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR + need_des + 30 + 1 + write-only + + + LP_ANA_BOD_MODE0_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_ANA_LP_INT_RAW + need_des + 0x30 + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_ANA_LP_INT_ST + need_des + 0x34 + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_ANA_LP_INT_ENA + need_des + 0x38 + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_ANA_LP_INT_CLR + need_des + 0x3C + 0x20 + + + LP_ANA_BOD_MODE0_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM + need_des + 0xFC + 0x20 + 0x06419064 + + + LP_ANA_TOUCH_APPROACH_MEAS_NUM2 + need_des + 0 + 10 + read-write + + + LP_ANA_TOUCH_APPROACH_MEAS_NUM1 + need_des + 10 + 10 + read-write + + + LP_ANA_TOUCH_APPROACH_MEAS_NUM0 + need_des + 20 + 10 + read-write + + + + + LP_ANA_TOUCH_SCAN_CTRL1 + need_des + 0x100 + 0x20 + 0x00080000 + + + LP_ANA_TOUCH_SHIELD_PAD_EN + need_des + 0 + 1 + read-write + + + LP_ANA_TOUCH_INACTIVE_CONNECTION + need_des + 1 + 1 + read-write + + + LP_ANA_TOUCH_SCAN_PAD_MAP + need_des + 2 + 15 + read-write + + + LP_ANA_TOUCH_XPD_WAIT + need_des + 17 + 15 + read-write + + + + + LP_ANA_TOUCH_SCAN_CTRL2 + need_des + 0x104 + 0x20 + 0x37BFFFC0 + + + LP_ANA_TOUCH_TIMEOUT_NUM + need_des + 6 + 16 + read-write + + + LP_ANA_TOUCH_TIMEOUT_EN + need_des + 22 + 1 + read-write + + + LP_ANA_TOUCH_OUT_RING + need_des + 23 + 4 + read-write + + + LP_ANA_FREQ_SCAN_EN + need_des + 27 + 1 + read-write + + + LP_ANA_FREQ_SCAN_CNT_LIMIT + need_des + 28 + 2 + read-write + + + + + LP_ANA_TOUCH_WORK + need_des + 0x108 + 0x20 + + + LP_ANA_DIV_NUM2 + need_des + 16 + 3 + read-write + + + LP_ANA_DIV_NUM1 + need_des + 19 + 3 + read-write + + + LP_ANA_DIV_NUM0 + need_des + 22 + 3 + read-write + + + LP_ANA_TOUCH_OUT_SEL + need_des + 25 + 1 + read-write + + + LP_ANA_TOUCH_OUT_RESET + need_des + 26 + 1 + write-only + + + LP_ANA_TOUCH_OUT_GATE + need_des + 27 + 1 + read-write + + + + + LP_ANA_TOUCH_WORK_MEAS_NUM + need_des + 0x10C + 0x20 + 0x06419064 + + + LP_ANA_TOUCH_MEAS_NUM2 + need_des + 0 + 10 + read-write + + + LP_ANA_TOUCH_MEAS_NUM1 + need_des + 10 + 10 + read-write + + + LP_ANA_TOUCH_MEAS_NUM0 + need_des + 20 + 10 + read-write + + + + + LP_ANA_TOUCH_FILTER1 + need_des + 0x110 + 0x20 + 0x6A0A0200 + + + LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN + Reserved + 0 + 1 + read-write + + + LP_ANA_TOUCH_HYSTERESIS + need_des + 1 + 2 + read-write + + + LP_ANA_TOUCH_NEG_NOISE_THRES + need_des + 3 + 2 + read-write + + + LP_ANA_TOUCH_NOISE_THRES + need_des + 5 + 2 + read-write + + + LP_ANA_TOUCH_SMOOTH_LVL + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_JITTER_STEP + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FILTER_MODE + need_des + 13 + 3 + read-write + + + LP_ANA_TOUCH_FILTER_EN + need_des + 16 + 1 + read-write + + + LP_ANA_TOUCH_NEG_NOISE_LIMIT + need_des + 17 + 4 + read-write + + + LP_ANA_TOUCH_APPROACH_LIMIT + need_des + 21 + 8 + read-write + + + LP_ANA_TOUCH_DEBOUNCE_LIMIT + need_des + 29 + 3 + read-write + + + + + LP_ANA_TOUCH_FILTER2 + need_des + 0x114 + 0x20 + 0x1FFF8000 + + + LP_ANA_TOUCH_OUTEN + need_des + 15 + 15 + read-write + + + LP_ANA_TOUCH_BYPASS_NOISE_THRES + need_des + 30 + 1 + read-write + + + LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES + need_des + 31 + 1 + read-write + + + + + LP_ANA_TOUCH_FILTER3 + need_des + 0x118 + 0x20 + + + LP_ANA_TOUCH_BASELINE_SW + need_des + 0 + 16 + read-write + + + LP_ANA_TOUCH_UPDATE_BASELINE_SW + need_des + 16 + 1 + write-only + + + + + LP_ANA_TOUCH_SLP0 + need_des + 0x11C + 0x20 + 0x001E0000 + + + LP_ANA_TOUCH_SLP_TH0 + need_des + 0 + 16 + read-write + + + LP_ANA_TOUCH_SLP_CHANNEL_CLR + need_des + 16 + 1 + write-only + + + LP_ANA_TOUCH_SLP_PAD + need_des + 17 + 4 + read-write + + + + + LP_ANA_TOUCH_SLP1 + need_des + 0x120 + 0x20 + + + LP_ANA_TOUCH_SLP_TH2 + need_des + 0 + 16 + read-write + + + LP_ANA_TOUCH_SLP_TH1 + need_des + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_CLR + need_des + 0x124 + 0x20 + + + LP_ANA_TOUCH_CHANNEL_CLR + need_des + 0 + 15 + write-only + + + LP_ANA_TOUCH_STATUS_CLR + need_des + 15 + 1 + write-only + + + + + LP_ANA_TOUCH_APPROACH + need_des + 0x128 + 0x20 + 0x00000FFF + + + PAD0 + need_des + 0 + 4 + read-write + + + PAD1 + need_des + 4 + 4 + read-write + + + PAD2 + need_des + 8 + 4 + read-write + + + LP_ANA_TOUCH_SLP_APPROACH_EN + need_des + 12 + 1 + read-write + + + + + LP_ANA_TOUCH_FREQ0_SCAN_PARA + need_des + 0x12C + 0x20 + + + LP_ANA_TOUCH_FREQ0_DCAP_LPF + need_des + 0 + 7 + read-write + + + LP_ANA_TOUCH_FREQ0_DRES_LPF + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_FREQ0_DRV_LS + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FREQ0_DRV_HS + need_des + 13 + 5 + read-write + + + LP_ANA_TOUCH_FREQ0_DBIAS + need_des + 18 + 5 + read-write + + + + + LP_ANA_TOUCH_FREQ1_SCAN_PARA + need_des + 0x130 + 0x20 + + + LP_ANA_TOUCH_FREQ1_DCAP_LPF + need_des + 0 + 7 + read-write + + + LP_ANA_TOUCH_FREQ1_DRES_LPF + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_FREQ1_DRV_LS + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FREQ1_DRV_HS + need_des + 13 + 5 + read-write + + + LP_ANA_TOUCH_FREQ1_DBIAS + need_des + 18 + 5 + read-write + + + + + LP_ANA_TOUCH_FREQ2_SCAN_PARA + need_des + 0x134 + 0x20 + + + LP_ANA_TOUCH_FREQ2_DCAP_LPF + need_des + 0 + 7 + read-write + + + LP_ANA_TOUCH_FREQ2_DRES_LPF + need_des + 7 + 2 + read-write + + + LP_ANA_TOUCH_FREQ2_DRV_LS + need_des + 9 + 4 + read-write + + + LP_ANA_TOUCH_FREQ2_DRV_HS + need_des + 13 + 5 + read-write + + + LP_ANA_TOUCH_FREQ2_DBIAS + need_des + 18 + 5 + read-write + + + + + LP_ANA_TOUCH_ANA_PARA + need_des + 0x138 + 0x20 + + + LP_ANA_TOUCH_TOUCH_BUF_DRV + need_des + 0 + 3 + read-write + + + LP_ANA_TOUCH_TOUCH_EN_CAL + need_des + 3 + 1 + read-write + + + LP_ANA_TOUCH_TOUCH_DCAP_CAL + need_des + 4 + 7 + read-write + + + + + LP_ANA_TOUCH_MUX0 + need_des + 0x13C + 0x20 + 0x20000000 + + + LP_ANA_TOUCH_DATA_SEL + need_des + 8 + 2 + read-write + + + LP_ANA_TOUCH_FREQ_SEL + need_des + 10 + 2 + read-write + + + LP_ANA_TOUCH_BUFSEL + need_des + 12 + 15 + read-write + + + LP_ANA_TOUCH_DONE_EN + need_des + 27 + 1 + read-write + + + LP_ANA_TOUCH_DONE_FORCE + need_des + 28 + 1 + read-write + + + LP_ANA_TOUCH_FSM_EN + need_des + 29 + 1 + read-write + + + LP_ANA_TOUCH_START_EN + need_des + 30 + 1 + read-write + + + LP_ANA_TOUCH_START_FORCE + need_des + 31 + 1 + read-write + + + + + LP_ANA_TOUCH_MUX1 + need_des + 0x140 + 0x20 + + + LP_ANA_TOUCH_START + need_des + 0 + 15 + read-write + + + LP_ANA_TOUCH_XPD + need_des + 15 + 15 + read-write + + + + + LP_ANA_TOUCH_PAD0_TH0 + need_des + 0x144 + 0x20 + + + LP_ANA_TOUCH_PAD0_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD0_TH1 + need_des + 0x148 + 0x20 + + + LP_ANA_TOUCH_PAD0_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD0_TH2 + need_des + 0x14C + 0x20 + + + LP_ANA_TOUCH_PAD0_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD1_TH0 + need_des + 0x150 + 0x20 + + + LP_ANA_TOUCH_PAD1_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD1_TH1 + need_des + 0x154 + 0x20 + + + LP_ANA_TOUCH_PAD1_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD1_TH2 + need_des + 0x158 + 0x20 + + + LP_ANA_TOUCH_PAD1_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD2_TH0 + need_des + 0x15C + 0x20 + + + LP_ANA_TOUCH_PAD2_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD2_TH1 + need_des + 0x160 + 0x20 + + + LP_ANA_TOUCH_PAD2_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD2_TH2 + need_des + 0x164 + 0x20 + + + LP_ANA_TOUCH_PAD2_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD3_TH0 + need_des + 0x168 + 0x20 + + + LP_ANA_TOUCH_PAD3_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD3_TH1 + need_des + 0x16C + 0x20 + + + LP_ANA_TOUCH_PAD3_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD3_TH2 + need_des + 0x170 + 0x20 + + + LP_ANA_TOUCH_PAD3_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD4_TH0 + need_des + 0x174 + 0x20 + + + LP_ANA_TOUCH_PAD4_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD4_TH1 + need_des + 0x178 + 0x20 + + + LP_ANA_TOUCH_PAD4_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD4_TH2 + need_des + 0x17C + 0x20 + + + LP_ANA_TOUCH_PAD4_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD5_TH0 + need_des + 0x180 + 0x20 + + + LP_ANA_TOUCH_PAD5_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD5_TH1 + need_des + 0x184 + 0x20 + + + LP_ANA_TOUCH_PAD5_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD5_TH2 + need_des + 0x188 + 0x20 + + + LP_ANA_TOUCH_PAD5_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD6_TH0 + need_des + 0x18C + 0x20 + + + LP_ANA_TOUCH_PAD6_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD6_TH1 + need_des + 0x190 + 0x20 + + + LP_ANA_TOUCH_PAD6_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD6_TH2 + need_des + 0x194 + 0x20 + + + LP_ANA_TOUCH_PAD6_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD7_TH0 + need_des + 0x198 + 0x20 + + + LP_ANA_TOUCH_PAD7_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD7_TH1 + need_des + 0x19C + 0x20 + + + LP_ANA_TOUCH_PAD7_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD7_TH2 + need_des + 0x1A0 + 0x20 + + + LP_ANA_TOUCH_PAD7_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD8_TH0 + need_des + 0x1A4 + 0x20 + + + LP_ANA_TOUCH_PAD8_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD8_TH1 + need_des + 0x1A8 + 0x20 + + + LP_ANA_TOUCH_PAD8_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD8_TH2 + need_des + 0x1AC + 0x20 + + + LP_ANA_TOUCH_PAD8_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD9_TH0 + need_des + 0x1B0 + 0x20 + + + LP_ANA_TOUCH_PAD9_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD9_TH1 + need_des + 0x1B4 + 0x20 + + + LP_ANA_TOUCH_PAD9_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD9_TH2 + need_des + 0x1B8 + 0x20 + + + LP_ANA_TOUCH_PAD9_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD10_TH0 + need_des + 0x1BC + 0x20 + + + LP_ANA_TOUCH_PAD10_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD10_TH1 + need_des + 0x1C0 + 0x20 + + + LP_ANA_TOUCH_PAD10_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD10_TH2 + need_des + 0x1C4 + 0x20 + + + LP_ANA_TOUCH_PAD10_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD11_TH0 + need_des + 0x1C8 + 0x20 + + + LP_ANA_TOUCH_PAD11_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD11_TH1 + need_des + 0x1CC + 0x20 + + + LP_ANA_TOUCH_PAD11_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD11_TH2 + need_des + 0x1D0 + 0x20 + + + LP_ANA_TOUCH_PAD11_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD12_TH0 + need_des + 0x1D4 + 0x20 + + + LP_ANA_TOUCH_PAD12_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD12_TH1 + need_des + 0x1D8 + 0x20 + + + LP_ANA_TOUCH_PAD12_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD12_TH2 + need_des + 0x1DC + 0x20 + + + LP_ANA_TOUCH_PAD12_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD13_TH0 + need_des + 0x1E0 + 0x20 + + + LP_ANA_TOUCH_PAD13_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD13_TH1 + need_des + 0x1E4 + 0x20 + + + LP_ANA_TOUCH_PAD13_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD13_TH2 + need_des + 0x1E8 + 0x20 + + + LP_ANA_TOUCH_PAD13_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD14_TH0 + need_des + 0x1EC + 0x20 + + + LP_ANA_TOUCH_PAD14_TH0 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD14_TH1 + need_des + 0x1F0 + 0x20 + + + LP_ANA_TOUCH_PAD14_TH1 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_TOUCH_PAD14_TH2 + need_des + 0x1F4 + 0x20 + + + LP_ANA_TOUCH_PAD14_TH2 + Reserved + 16 + 16 + read-write + + + + + LP_ANA_DATE + need_des + 0x3FC + 0x20 + 0x00230420 + + + LP_ANA_LP_ANA_DATE + need_des + 0 + 31 + read-write + + + LP_ANA_CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_AON_CLKRST + LP_AON_CLKRST Peripheral + LP_AON_CLKRST + 0x50111000 + + 0x0 + 0x54 + registers + + + + LP_AONCLKRST_LP_CLK_CONF + need_des + 0x0 + 0x20 + 0x00000004 + + + LP_AONCLKRST_SLOW_CLK_SEL + need_des + 0 + 2 + read-write + + + LP_AONCLKRST_FAST_CLK_SEL + need_des + 2 + 2 + read-write + + + LP_AONCLKRST_LP_PERI_DIV_NUM + need_des + 4 + 6 + read-write + + + LP_AONCLKRST_ANA_SEL_REF_PLL8M + need_des + 10 + 1 + read-write + + + + + LP_AONCLKRST_LP_CLK_PO_EN + need_des + 0x4 + 0x20 + + + LP_AONCLKRST_CLK_CORE_EFUSE_OEN + need_des + 0 + 1 + read-write + + + LP_AONCLKRST_CLK_LP_BUS_OEN + need_des + 1 + 1 + read-write + + + LP_AONCLKRST_CLK_AON_SLOW_OEN + need_des + 2 + 1 + read-write + + + LP_AONCLKRST_CLK_AON_FAST_OEN + need_des + 3 + 1 + read-write + + + LP_AONCLKRST_CLK_SLOW_OEN + need_des + 4 + 1 + read-write + + + LP_AONCLKRST_CLK_FAST_OEN + need_des + 5 + 1 + read-write + + + LP_AONCLKRST_CLK_FOSC_OEN + need_des + 6 + 1 + read-write + + + LP_AONCLKRST_CLK_RC32K_OEN + need_des + 7 + 1 + read-write + + + LP_AONCLKRST_CLK_SXTAL_OEN + need_des + 8 + 1 + read-write + + + LP_AONCLKRST_CLK_SOSC_OEN + 1'b1: probe sosc clk on +1'b0: probe sosc clk off + 9 + 1 + read-write + + + + + LP_AONCLKRST_LP_CLK_EN + need_des + 0x8 + 0x20 + 0x08000000 + + + LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON + need_des + 26 + 1 + read-write + + + LP_AONCLKRST_CK_EN_LP_RAM + need_des + 27 + 1 + read-write + + + LP_AONCLKRST_ETM_EVENT_TICK_EN + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_PLL8M_CLK_FORCE_ON + need_des + 29 + 1 + read-write + + + LP_AONCLKRST_XTAL_CLK_FORCE_ON + need_des + 30 + 1 + read-write + + + LP_AONCLKRST_FOSC_CLK_FORCE_ON + need_des + 31 + 1 + read-write + + + + + LP_AONCLKRST_LP_RST_EN + need_des + 0xC + 0x20 + + + LP_AONCLKRST_RST_EN_LP_HUK + need_des + 24 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_ANAPERI + need_des + 25 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_WDT + need_des + 26 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_TIMER + need_des + 27 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_RTC + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_MAILBOX + need_des + 29 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_AONEFUSEREG + need_des + 30 + 1 + read-write + + + LP_AONCLKRST_RST_EN_LP_RAM + need_des + 31 + 1 + read-write + + + + + LP_AONCLKRST_RESET_CAUSE + need_des + 0x10 + 0x20 + 0x02000000 + + + LP_AONCLKRST_LPCORE_RESET_CAUSE + 6'h1: POR reset +6'h9: PMU LP PERI power down reset +6'ha: PMU LP CPU reset +6'hf: brown out reset +6'h10: LP watchdog chip reset +6'h12: super watch dog reset +6'h13: glitch reset +6'h14: software reset + 0 + 6 + read-only + + + LP_AONCLKRST_LPCORE_RESET_FLAG + need_des + 6 + 1 + read-only + + + LP_AONCLKRST_HPCORE0_RESET_CAUSE + 6'h1: POR reset +6'h3: digital system software reset +6'h5: PMU HP system power down reset +6'h7: HP system reset from HP watchdog +6'h9: HP system reset from LP watchdog +6'hb: HP core reset from HP watchdog +6'hc: HP core software reset +6'hd: HP core reset from LP watchdog +6'hf: brown out reset +6'h10: LP watchdog chip reset +6'h12: super watch dog reset +6'h13: glitch reset +6'h14: efuse crc error reset +6'h16: HP usb jtag chip reset +6'h17: HP usb uart chip reset +6'h18: HP jtag reset +6'h1a: HP core lockup + 7 + 6 + read-only + + + LP_AONCLKRST_HPCORE0_RESET_FLAG + need_des + 13 + 1 + read-only + + + LP_AONCLKRST_HPCORE1_RESET_CAUSE + 6'h1: POR reset +6'h3: digital system software reset +6'h5: PMU HP system power down reset +6'h7: HP system reset from HP watchdog +6'h9: HP system reset from LP watchdog +6'hb: HP core reset from HP watchdog +6'hc: HP core software reset +6'hd: HP core reset from LP watchdog +6'hf: brown out reset +6'h10: LP watchdog chip reset +6'h12: super watch dog reset +6'h13: glitch reset +6'h14: efuse crc error reset +6'h16: HP usb jtag chip reset +6'h17: HP usb uart chip reset +6'h18: HP jtag reset +6'h1a: HP core lockup + 14 + 6 + read-only + + + LP_AONCLKRST_HPCORE1_RESET_FLAG + need_des + 20 + 1 + read-only + + + LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK + 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore pmu_lp_cpu_reset reset_cause + 25 + 1 + read-write + + + LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR + need_des + 26 + 1 + write-only + + + LP_AONCLKRST_LPCORE_RESET_FLAG_CLR + need_des + 27 + 1 + write-only + + + LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR + need_des + 28 + 1 + write-only + + + LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR + need_des + 29 + 1 + write-only + + + LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR + need_des + 30 + 1 + write-only + + + LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR + need_des + 31 + 1 + write-only + + + + + LP_AONCLKRST_HPCPU_RESET_CTRL0 + need_des + 0x14 + 0x20 + 0x80028002 + + + LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN + write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature + 0 + 1 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH + need_des + 1 + 3 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN + write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature + 4 + 1 + read-write + + + LP_AONCLKRST_HPCORE0_STALL_WAIT + need_des + 5 + 7 + read-write + + + LP_AONCLKRST_HPCORE0_STALL_EN + need_des + 12 + 1 + read-write + + + LP_AONCLKRST_HPCORE0_SW_RESET + need_des + 13 + 1 + write-only + + + LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET + need_des + 14 + 1 + read-write + + + LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL + 1'b1: boot from HP TCM ROM: 0x4FC00000 +1'b0: boot from LP TCM RAM: 0x50108000 + 15 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN + write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature + 16 + 1 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH + need_des + 17 + 3 + read-write + + + LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN + write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature + 20 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_STALL_WAIT + need_des + 21 + 7 + read-write + + + LP_AONCLKRST_HPCORE1_STALL_EN + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_SW_RESET + need_des + 29 + 1 + write-only + + + LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET + need_des + 30 + 1 + read-write + + + LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL + 1'b1: boot from HP TCM ROM: 0x4FC00000 +1'b0: boot from LP TCM RAM: 0x50108000 + 31 + 1 + read-write + + + + + LP_AONCLKRST_HPCPU_RESET_CTRL1 + need_des + 0x18 + 0x20 + + + LP_AONCLKRST_HPCORE0_SW_STALL_CODE + HP core0 software stall when set to 8'h86 + 16 + 8 + read-write + + + LP_AONCLKRST_HPCORE1_SW_STALL_CODE + HP core1 software stall when set to 8'h86 + 24 + 8 + read-write + + + + + LP_AONCLKRST_FOSC_CNTL + need_des + 0x1C + 0x20 + 0x64000000 + + + LP_AONCLKRST_FOSC_DFREQ + need_des + 22 + 10 + read-write + + + + + LP_AONCLKRST_RC32K_CNTL + need_des + 0x20 + 0x20 + 0x0000028A + + + LP_AONCLKRST_RC32K_DFREQ + need_des + 0 + 32 + read-write + + + + + LP_AONCLKRST_SOSC_CNTL + need_des + 0x24 + 0x20 + 0x2B000000 + + + LP_AONCLKRST_SOSC_DFREQ + need_des + 22 + 10 + read-write + + + + + LP_AONCLKRST_CLK_TO_HP + need_des + 0x28 + 0x20 + 0xF0000000 + + + LP_AONCLKRST_ICG_HP_XTAL32K + reserved + 28 + 1 + read-write + + + LP_AONCLKRST_ICG_HP_SOSC + reserved + 29 + 1 + read-write + + + LP_AONCLKRST_ICG_HP_OSC32K + reserved + 30 + 1 + read-write + + + LP_AONCLKRST_ICG_HP_FOSC + reserved + 31 + 1 + read-write + + + + + LP_AONCLKRST_LPMEM_FORCE + need_des + 0x2C + 0x20 + + + LP_AONCLKRST_LPMEM_CLK_FORCE_ON + reserved + 31 + 1 + read-write + + + + + LP_AONCLKRST_XTAL32K + need_des + 0x30 + 0x20 + 0x66C00000 + + + LP_AONCLKRST_DRES_XTAL32K + need_des + 22 + 3 + read-write + + + LP_AONCLKRST_DGM_XTAL32K + need_des + 25 + 3 + read-write + + + LP_AONCLKRST_DBUF_XTAL32K + need_des + 28 + 1 + read-write + + + LP_AONCLKRST_DAC_XTAL32K + need_des + 29 + 3 + read-write + + + + + LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS + need_des + 0x34 + 0x20 + 0xFFFFFFFF + + + LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS + reserved + 0 + 32 + read-write + + + + + LP_AONCLKRST_HPSYS_0_RESET_BYPASS + need_des + 0x38 + 0x20 + 0xFFFFFFFF + + + LP_AONCLKRST_HPSYS_0_RESET_BYPASS + reserved + 0 + 32 + read-write + + + + + LP_AONCLKRST_HPSYS_APM_RESET_BYPASS + need_des + 0x3C + 0x20 + 0xFFFFFFFF + + + LP_AONCLKRST_HPSYS_APM_RESET_BYPASS + reserved + 0 + 32 + read-write + + + + + LP_AONCLKRST_HP_CLK_CTRL + HP Clock Control Register. + 0x40 + 0x20 + 0x1FFFFFFC + + + LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL + HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m. + 0 + 2 + read-write + + + LP_AONCLKRST_HP_ROOT_CLK_EN + HP SoC Root Clock Enable. + 2 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN + PARLIO TX Clock From Pad Enable. + 3 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN + PARLIO RX Clock From Pad Enable. + 4 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN + UART4 SLP Clock From Pad Enable. + 5 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN + UART3 SLP Clock From Pad Enable. + 6 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN + UART2 SLP Clock From Pad Enable. + 7 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN + UART1 SLP Clock From Pad Enable. + 8 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN + UART0 SLP Clock From Pad Enable. + 9 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN + I2S2 MCLK Clock From Pad Enable. + 10 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN + I2S1 MCLK Clock From Pad Enable. + 11 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN + I2S0 MCLK Clock From Pad Enable. + 12 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN + EMAC RX Clock From Pad Enable. + 13 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN + EMAC TX Clock From Pad Enable. + 14 + 1 + read-write + + + LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN + EMAC TXRX Clock From Pad Enable. + 15 + 1 + read-write + + + LP_AONCLKRST_HP_XTAL_32K_CLK_EN + XTAL 32K Clock Enable. + 16 + 1 + read-write + + + LP_AONCLKRST_HP_RC_32K_CLK_EN + RC 32K Clock Enable. + 17 + 1 + read-write + + + LP_AONCLKRST_HP_SOSC_150K_CLK_EN + SOSC 150K Clock Enable. + 18 + 1 + read-write + + + LP_AONCLKRST_HP_PLL_8M_CLK_EN + PLL 8M Clock Enable. + 19 + 1 + read-write + + + LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN + AUDIO PLL Clock Enable. + 20 + 1 + read-write + + + LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN + SDIO PLL2 Clock Enable. + 21 + 1 + read-write + + + LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN + SDIO PLL1 Clock Enable. + 22 + 1 + read-write + + + LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN + SDIO PLL0 Clock Enable. + 23 + 1 + read-write + + + LP_AONCLKRST_HP_FOSC_20M_CLK_EN + FOSC 20M Clock Enable. + 24 + 1 + read-write + + + LP_AONCLKRST_HP_XTAL_40M_CLK_EN + XTAL 40M Clock Enalbe. + 25 + 1 + read-write + + + LP_AONCLKRST_HP_CPLL_400M_CLK_EN + CPLL 400M Clock Enable. + 26 + 1 + read-write + + + LP_AONCLKRST_HP_SPLL_480M_CLK_EN + SPLL 480M Clock Enable. + 27 + 1 + read-write + + + LP_AONCLKRST_HP_MPLL_500M_CLK_EN + MPLL 500M Clock Enable. + 28 + 1 + read-write + + + + + LP_AONCLKRST_HP_USB_CLKRST_CTRL0 + HP USB Clock Reset Control Register. + 0x44 + 0x20 + 0x09C4C27A + + + LP_AONCLKRST_USB_OTG20_SLEEP_MODE + unused. + 0 + 1 + read-write + + + LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN + unused. + 1 + 1 + read-write + + + LP_AONCLKRST_USB_OTG11_SLEEP_MODE + unused. + 2 + 1 + read-write + + + LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN + unused. + 3 + 1 + read-write + + + LP_AONCLKRST_USB_OTG11_48M_CLK_EN + usb otg11 fs phy clock enable. + 4 + 1 + read-write + + + LP_AONCLKRST_USB_DEVICE_48M_CLK_EN + usb device fs phy clock enable. + 5 + 1 + read-write + + + LP_AONCLKRST_USB_48M_DIV_NUM + usb 480m to 25m divide number. + 6 + 8 + read-write + + + LP_AONCLKRST_USB_25M_DIV_NUM + usb 500m to 25m divide number. + 14 + 8 + read-write + + + LP_AONCLKRST_USB_12M_DIV_NUM + usb 480m to 12m divide number. + 22 + 8 + read-write + + + + + LP_AONCLKRST_HP_USB_CLKRST_CTRL1 + HP USB Clock Reset Control Register. + 0x48 + 0x20 + 0xC0000000 + + + LP_AONCLKRST_RST_EN_USB_OTG20_ADP + usb otg20 adp reset en + 0 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_OTG20_PHY + usb otg20 phy reset en + 1 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_OTG20 + usb otg20 reset en + 2 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_OTG11 + usb org11 reset en + 3 + 1 + read-write + + + LP_AONCLKRST_RST_EN_USB_DEVICE + usb device reset en + 4 + 1 + read-write + + + LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL + usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk. + 28 + 2 + read-write + + + LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN + usb otg20 hs phy refclk enable. + 30 + 1 + read-write + + + LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN + usb otg20 ulpi clock enable. + 31 + 1 + read-write + + + + + LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL + need_des + 0x4C + 0x20 + + + LP_AONCLKRST_RST_EN_SDMMC + hp sdmmc reset en + 28 + 1 + read-write + + + LP_AONCLKRST_FORCE_NORST_SDMMC + hp sdmmc force norst + 29 + 1 + read-write + + + LP_AONCLKRST_RST_EN_EMAC + hp emac reset en + 30 + 1 + read-write + + + LP_AONCLKRST_FORCE_NORST_EMAC + hp emac force norst + 31 + 1 + read-write + + + + + LP_AONCLKRST_DATE + need_des + 0x3FC + 0x20 + + + LP_AONCLKRST_CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_GPIO + Low-power General Purpose Input/Output + LP_GPIO + 0x5012A000 + + 0x0 + 0xEC + registers + + + LP_GPIO + 10 + + + + CLK_EN + Reserved + 0x0 + 0x20 + 0x00000001 + + + REG_CLK_EN + Reserved + 0 + 1 + read-write + + + + + VER_DATE + Reserved + 0x4 + 0x20 + 0x00230323 + + + REG_VER_DATE + Reserved + 0 + 28 + read-write + + + + + OUT + Reserved + 0x8 + 0x20 + + + REG_GPIO_OUT_DATA + Reserved + 0 + 16 + read-write + + + + + OUT_W1TS + Reserved + 0xC + 0x20 + + + REG_GPIO_OUT_DATA_W1TS + Reserved + 0 + 16 + write-only + + + + + OUT_W1TC + Reserved + 0x10 + 0x20 + + + REG_GPIO_OUT_DATA_W1TC + Reserved + 0 + 16 + write-only + + + + + ENABLE + Reserved + 0x14 + 0x20 + + + REG_GPIO_ENABLE_DATA + Reserved + 0 + 16 + read-write + + + + + ENABLE_W1TS + Reserved + 0x18 + 0x20 + + + REG_GPIO_ENABLE_DATA_W1TS + Reserved + 0 + 16 + write-only + + + + + ENABLE_W1TC + Reserved + 0x1C + 0x20 + + + REG_GPIO_ENABLE_DATA_W1TC + Reserved + 0 + 16 + write-only + + + + + STATUS + Reserved + 0x20 + 0x20 + + + REG_GPIO_STATUS_DATA + Reserved + 0 + 16 + read-write + + + + + STATUS_W1TS + Reserved + 0x24 + 0x20 + + + REG_GPIO_STATUS_DATA_W1TS + Reserved + 0 + 16 + write-only + + + + + STATUS_W1TC + Reserved + 0x28 + 0x20 + + + REG_GPIO_STATUS_DATA_W1TC + Reserved + 0 + 16 + write-only + + + + + STATUS_NEXT + Reserved + 0x2C + 0x20 + + + REG_GPIO_STATUS_INTERRUPT_NEXT + Reserved + 0 + 16 + read-only + + + + + IN + Reserved + 0x30 + 0x20 + + + REG_GPIO_IN_DATA_NEXT + Reserved + 0 + 16 + read-only + + + + + PIN0 + Reserved + 0x34 + 0x20 + + + REG_GPIO_PIN0_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN0_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN0_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPIO_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN1 + Reserved + 0x38 + 0x20 + + + REG_GPIO_PIN1_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN1_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN1_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI1_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN2 + Reserved + 0x3C + 0x20 + + + REG_GPIO_PIN2_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN2_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN2_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI2_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN3 + Reserved + 0x40 + 0x20 + + + REG_GPIO_PIN3_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN3_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN3_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI3_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN4 + Reserved + 0x44 + 0x20 + + + REG_GPIO_PIN4_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN4_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN4_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI4_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN5 + Reserved + 0x48 + 0x20 + + + REG_GPIO_PIN5_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN5_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN5_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI5_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN6 + Reserved + 0x4C + 0x20 + + + REG_GPIO_PIN6_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN6_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN6_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI6_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN7 + Reserved + 0x50 + 0x20 + + + REG_GPIO_PIN7_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN7_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN7_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI7_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN8 + Reserved + 0x54 + 0x20 + + + REG_GPIO_PIN8_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN8_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN8_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI8_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN9 + Reserved + 0x58 + 0x20 + + + REG_GPIO_PIN9_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN9_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN9_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI9_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN10 + Reserved + 0x5C + 0x20 + + + REG_GPIO_PIN10_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN10_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN10_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI10_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN11 + Reserved + 0x60 + 0x20 + + + REG_GPIO_PIN11_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN11_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN11_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI11_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN12 + Reserved + 0x64 + 0x20 + + + REG_GPIO_PIN12_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN12_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN12_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI12_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN13 + Reserved + 0x68 + 0x20 + + + REG_GPIO_PIN13_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN13_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN13_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI13_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN14 + Reserved + 0x6C + 0x20 + + + REG_GPIO_PIN14_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN14_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN14_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI14_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + PIN15 + Reserved + 0x70 + 0x20 + + + REG_GPIO_PIN15_WAKEUP_ENABLE + Reserved + 0 + 1 + read-write + + + REG_GPIO_PIN15_INT_TYPE + Reserved + 1 + 3 + read-write + + + REG_GPIO_PIN15_PAD_DRIVER + Reserved + 4 + 1 + read-write + + + REG_GPI15_PIN0_EDGE_WAKEUP_CLR + need des + 5 + 1 + write-only + + + + + FUNC0_IN_SEL_CFG + Reserved + 0x74 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC0_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG0_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC0_IN_SEL + reg_gpio_func0_in_sel[5:4]==2'b11->constant 1,reg_gpio_func0_in_sel[5:4]==2'b10->constant 0 + 2 + 6 + read-write + + + + + FUNC1_IN_SEL_CFG + Reserved + 0x78 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC1_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG1_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC1_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC2_IN_SEL_CFG + Reserved + 0x7C + 0x20 + 0x00000080 + + + REG_GPIO_FUNC2_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG2_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC2_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC3_IN_SEL_CFG + Reserved + 0x80 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC3_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG3_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC3_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC4_IN_SEL_CFG + Reserved + 0x84 + 0x20 + 0x000000C0 + + + REG_GPIO_FUNC4_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG4_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC4_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC5_IN_SEL_CFG + Reserved + 0x88 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC5_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG5_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC5_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC6_IN_SEL_CFG + Reserved + 0x8C + 0x20 + 0x00000080 + + + REG_GPIO_FUNC6_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG6_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC6_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC7_IN_SEL_CFG + Reserved + 0x90 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC7_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG7_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC7_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC8_IN_SEL_CFG + Reserved + 0x94 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC8_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG8_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC8_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC9_IN_SEL_CFG + Reserved + 0x98 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC9_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG9_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC9_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC10_IN_SEL_CFG + Reserved + 0x9C + 0x20 + 0x00000080 + + + REG_GPIO_FUNC10_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG10_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC10_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC11_IN_SEL_CFG + Reserved + 0xA0 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC11_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG11_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC11_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC12_IN_SEL_CFG + Reserved + 0xA4 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC12_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG12_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC12_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC13_IN_SEL_CFG + Reserved + 0xA8 + 0x20 + 0x00000080 + + + REG_GPIO_FUNC13_IN_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_SIG13_IN_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC13_IN_SEL + Reserved + 2 + 6 + read-write + + + + + FUNC0_OUT_SEL_CFG + Reserved + 0xF4 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC0_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC0_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC0_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC0_OUT_SEL + reg_gpio_func0_out_sel[5:1]==16 -> output gpio register value to pad + 3 + 6 + read-write + + + + + FUNC1_OUT_SEL_CFG + Reserved + 0xF8 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC1_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC1_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC1_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC1_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC2_OUT_SEL_CFG + Reserved + 0xFC + 0x20 + 0x00000100 + + + REG_GPIO_FUNC2_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC2_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC2_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC2_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC3_OUT_SEL_CFG + Reserved + 0x100 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC3_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC3_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC3_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC3_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC4_OUT_SEL_CFG + Reserved + 0x104 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC4_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC4_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC4_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC4_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC5_OUT_SEL_CFG + Reserved + 0x108 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC5_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC5_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC5_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC5_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC6_OUT_SEL_CFG + Reserved + 0x10C + 0x20 + 0x00000100 + + + REG_GPIO_FUNC6_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC6_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC6_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC6_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC7_OUT_SEL_CFG + Reserved + 0x110 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC7_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC7_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC7_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC7_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC8_OUT_SEL_CFG + Reserved + 0x114 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC8_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC8_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC8_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC8_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC9_OUT_SEL_CFG + Reserved + 0x118 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC9_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC9_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC9_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC9_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC10_OUT_SEL_CFG + Reserved + 0x11C + 0x20 + 0x00000100 + + + REG_GPIO_FUNC10_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC10_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC10_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC10_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC11_OUT_SEL_CFG + Reserved + 0x120 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC11_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC11_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC11_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC11_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC12_OUT_SEL_CFG + Reserved + 0x124 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC12_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC12_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC12_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC12_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC13_OUT_SEL_CFG + Reserved + 0x128 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC13_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC13_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC13_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC13_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC14_OUT_SEL_CFG + Reserved + 0x12C + 0x20 + 0x00000100 + + + REG_GPIO_FUNC14_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC14_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC14_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC14_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + FUNC15_OUT_SEL_CFG + Reserved + 0x130 + 0x20 + 0x00000100 + + + REG_GPIO_FUNC15_OE_INV_SEL + Reserved + 0 + 1 + read-write + + + REG_GPIO_FUNC15_OE_SEL + Reserved + 1 + 1 + read-write + + + REG_GPIO_FUNC15_OUT_INV_SEL + Reserved + 2 + 1 + read-write + + + REG_GPIO_FUNC15_OUT_SEL + Reserved + 3 + 6 + read-write + + + + + + + LP_I2C0 + Low-power I2C (Inter-Integrated Circuit) Controller 0 + LP_I2C + 0x50122000 + + 0x0 + 0x88 + registers + + + LP_I2C0 + 11 + + + + SCL_LOW_PERIOD + Configures the low level width of the SCL +Clock + 0x0 + 0x20 + + + SCL_LOW_PERIOD + Configures the low level width of the SCL Clock. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + CTR + Transmission setting + 0x4 + 0x20 + 0x00000208 + + + SDA_FORCE_OUT + Configures the SDA output mode +1: Direct output, + +0: Open drain output. + 0 + 1 + read-write + + + SCL_FORCE_OUT + Configures the SCL output mode +1: Direct output, + +0: Open drain output. + 1 + 1 + read-write + + + SAMPLE_SCL_LEVEL + Configures the sample mode for SDA. +1: Sample SDA data on the SCL low level. + +0: Sample SDA data on the SCL high level. + 2 + 1 + read-write + + + RX_FULL_ACK_LEVEL + Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. + 3 + 1 + read-write + + + TRANS_START + Configures to start sending the data in txfifo for slave. +0: No effect + +1: Start + 5 + 1 + write-only + + + TX_LSB_FIRST + Configures to control the sending order for data needing to be sent. +1: send data from the least significant bit, + +0: send data from the most significant bit. + 6 + 1 + read-write + + + RX_LSB_FIRST + Configures to control the storage order for received data. +1: receive data from the least significant bit + +0: receive data from the most significant bit. + 7 + 1 + read-write + + + CLK_EN + Configures whether to gate clock signal for registers. + +0: Force clock on for registers + +1: Support clock only when registers are read or written to by software. + 8 + 1 + read-write + + + ARBITRATION_EN + Configures to enable I2C bus arbitration detection. +0: No effect + +1: Enable + 9 + 1 + read-write + + + FSM_RST + Configures to reset the SCL_FSM. +0: No effect + +1: Reset + 10 + 1 + write-only + + + CONF_UPGATE + Configures this bit for synchronization +0: No effect + +1: Synchronize + 11 + 1 + write-only + + + + + SR + Describe I2C work status. + 0x8 + 0x20 + + + RESP_REC + Represents the received ACK value in master mode or slave mode. +0: ACK, + +1: NACK. + 0 + 1 + read-only + + + ARB_LOST + Represents whether the I2C controller loses control of SCL line. +0: No arbitration lost + +1: Arbitration lost + 3 + 1 + read-only + + + BUS_BUSY + Represents the I2C bus state. +1: The I2C bus is busy transferring data, + +0: The I2C bus is in idle state. + 4 + 1 + read-only + + + RXFIFO_CNT + Represents the number of data bytes to be sent. + 8 + 5 + read-only + + + TXFIFO_CNT + Represents the number of data bytes received in RAM. + 18 + 5 + read-only + + + SCL_MAIN_STATE_LAST + Represents the states of the I2C module state machine. +0: Idle, + +1: Address shift, + +2: ACK address, + +3: Rx data, + +4: Tx data, + +5: Send ACK, + +6: Wait ACK + 24 + 3 + read-only + + + SCL_STATE_LAST + Represents the states of the state machine used to produce SCL. +0: Idle, + +1: Start, + +2: Negative edge, + +3: Low, + +4: Positive edge, + +5: High, + +6: Stop + 28 + 3 + read-only + + + + + TO + Setting time out control for receiving data. + 0xC + 0x20 + 0x00000010 + + + TIME_OUT_VALUE + Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). +Measurement unit: i2c_sclk. + 0 + 5 + read-write + + + TIME_OUT_EN + Configures to enable time out control. +0: No effect + +1: Enable + 5 + 1 + read-write + + + + + FIFO_ST + FIFO status register. + 0x14 + 0x20 + + + RXFIFO_RADDR + Represents the offset address of the APB reading from RXFIFO + 0 + 4 + read-only + + + RXFIFO_WADDR + Represents the offset address of i2c module receiving data and writing to RXFIFO. + 5 + 4 + read-only + + + TXFIFO_RADDR + Represents the offset address of i2c module reading from TXFIFO. + 10 + 4 + read-only + + + TXFIFO_WADDR + Represents the offset address of APB bus writing to TXFIFO. + 15 + 4 + read-only + + + + + FIFO_CONF + FIFO configuration register. + 0x18 + 0x20 + 0x00004046 + + + RXFIFO_WM_THRHD + Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. + 0 + 4 + read-write + + + TXFIFO_WM_THRHD + Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. + 5 + 4 + read-write + + + NONFIFO_EN + Configures to enable APB nonfifo access. + 10 + 1 + read-write + + + RX_FIFO_RST + Configures to reset RXFIFO. +0: No effect + +1: Reset + 12 + 1 + read-write + + + TX_FIFO_RST + Configures to reset TXFIFO. +0: No effect + +1: Reset + 13 + 1 + read-write + + + FIFO_PRT_EN + Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. +0: No effect + +1: Enable + 14 + 1 + read-write + + + + + DATA + Rx FIFO read data. + 0x1C + 0x20 + + + FIFO_RDATA + Represents the value of RXFIFO read data. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x20 + 0x20 + 0x00000002 + + + RXFIFO_WM_INT_RAW + The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_RAW + The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_RAW + The raw interrupt status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_RAW + The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_RAW + The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_RAW + The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_RAW + The raw interrupt status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_RAW + The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_RAW + The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_RAW + The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_RAW + The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_RAW + The raw interrupt status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + INT_CLR + Interrupt clear bits + 0x24 + 0x20 + + + RXFIFO_WM_INT_CLR + Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + write-only + + + TXFIFO_WM_INT_CLR + Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + write-only + + + END_DETECT_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 3 + 1 + write-only + + + BYTE_TRANS_DONE_INT_CLR + Write 1 to clear the I2C_END_DETECT_INT interrupt. + 4 + 1 + write-only + + + ARBITRATION_LOST_INT_CLR + Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + write-only + + + MST_TXFIFO_UDF_INT_CLR + Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + write-only + + + TRANS_COMPLETE_INT_CLR + Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + write-only + + + TIME_OUT_INT_CLR + Write 1 to clear the I2C_TIME_OUT_INT interrupt. + 8 + 1 + write-only + + + TRANS_START_INT_CLR + Write 1 to clear the I2C_TRANS_START_INT interrupt. + 9 + 1 + write-only + + + NACK_INT_CLR + Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + write-only + + + TXFIFO_OVF_INT_CLR + Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + write-only + + + RXFIFO_UDF_INT_CLR + Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + write-only + + + SCL_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + write-only + + + SCL_MAIN_ST_TO_INT_CLR + Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + write-only + + + DET_START_INT_CLR + Write 1 to clear I2C_DET_START_INT interrupt. + 15 + 1 + write-only + + + + + INT_ENA + Interrupt enable bits + 0x28 + 0x20 + + + RXFIFO_WM_INT_ENA + Write 1 to anable I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-write + + + TXFIFO_WM_INT_ENA + Write 1 to anable I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + Write 1 to anable I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-write + + + END_DETECT_INT_ENA + Write 1 to anable the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-write + + + BYTE_TRANS_DONE_INT_ENA + Write 1 to anable the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-write + + + MST_TXFIFO_UDF_INT_ENA + Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-write + + + TRANS_COMPLETE_INT_ENA + Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-write + + + TIME_OUT_INT_ENA + Write 1 to anable the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-write + + + TRANS_START_INT_ENA + Write 1 to anable the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-write + + + NACK_INT_ENA + Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-write + + + TXFIFO_OVF_INT_ENA + Write 1 to anable I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-write + + + RXFIFO_UDF_INT_ENA + Write 1 to anable I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-write + + + SCL_ST_TO_INT_ENA + Write 1 to anable I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-write + + + SCL_MAIN_ST_TO_INT_ENA + Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-write + + + DET_START_INT_ENA + Write 1 to anable I2C_DET_START_INT interrupt. + 15 + 1 + read-write + + + + + INT_STATUS + Status of captured I2C communication events + 0x2C + 0x20 + + + RXFIFO_WM_INT_ST + The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + 0 + 1 + read-only + + + TXFIFO_WM_INT_ST + The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + 1 + 1 + read-only + + + RXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + 2 + 1 + read-only + + + END_DETECT_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 3 + 1 + read-only + + + BYTE_TRANS_DONE_INT_ST + The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + 4 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + 5 + 1 + read-only + + + MST_TXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + 6 + 1 + read-only + + + TRANS_COMPLETE_INT_ST + The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + 7 + 1 + read-only + + + TIME_OUT_INT_ST + The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + 8 + 1 + read-only + + + TRANS_START_INT_ST + The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + 9 + 1 + read-only + + + NACK_INT_ST + The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + 10 + 1 + read-only + + + TXFIFO_OVF_INT_ST + The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + 11 + 1 + read-only + + + RXFIFO_UDF_INT_ST + The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + 12 + 1 + read-only + + + SCL_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + 13 + 1 + read-only + + + SCL_MAIN_ST_TO_INT_ST + The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + 14 + 1 + read-only + + + DET_START_INT_ST + The masked interrupt status status of I2C_DET_START_INT interrupt. + 15 + 1 + read-only + + + + + SDA_HOLD + Configures the hold time after a negative SCL edge. + 0x30 + 0x20 + + + TIME + Configures the time to hold the data after the falling edge of SCL. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SDA_SAMPLE + Configures the sample time after a positive SCL edge. + 0x34 + 0x20 + + + TIME + Configures the sample time after a positive SCL edge. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_HIGH_PERIOD + Configures the high level width of SCL + 0x38 + 0x20 + + + SCL_HIGH_PERIOD + Configures for how long SCL remains high in master mode. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + SCL_WAIT_HIGH_PERIOD + Configures the SCL_FSM's waiting period for SCL high level in master mode. +Measurement unit: i2c_sclk + 9 + 7 + read-write + + + + + SCL_START_HOLD + Configures the delay between the SDA and SCL negative edge for a start condition + 0x40 + 0x20 + 0x00000008 + + + TIME + Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. +Measurement unit: i2c_sclk. + 0 + 9 + read-write + + + + + SCL_RSTART_SETUP + Configures the delay between the positive +edge of SCL and the negative edge of SDA + 0x44 + 0x20 + 0x00000008 + + + TIME + Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_HOLD + Configures the delay after the SCL clock +edge for a stop condition + 0x48 + 0x20 + 0x00000008 + + + TIME + Configures the delay after the STOP condition. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + SCL_STOP_SETUP + Configures the delay between the SDA and +SCL positive edge for a stop condition + 0x4C + 0x20 + 0x00000008 + + + TIME + Configures the time between the rising edge of SCL and the rising edge of SDA. +Measurement unit: i2c_sclk + 0 + 9 + read-write + + + + + FILTER_CFG + SCL and SDA filter configuration register + 0x50 + 0x20 + 0x00000300 + + + SCL_FILTER_THRES + Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 0 + 4 + read-write + + + SDA_FILTER_THRES + Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. +Measurement unit: i2c_sclk + 4 + 4 + read-write + + + SCL_FILTER_EN + Configures to enable the filter function for SCL. + 8 + 1 + read-write + + + SDA_FILTER_EN + Configures to enable the filter function for SDA. + 9 + 1 + read-write + + + + + CLK_CONF + I2C CLK configuration register + 0x54 + 0x20 + 0x00200000 + + + SCLK_DIV_NUM + the integral part of the fractional divisor for i2c module + 0 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor for i2c module + 8 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor for i2c module + 14 + 6 + read-write + + + SCLK_SEL + The clock selection for i2c module:0-XTAL,1-CLK_8MHz. + 20 + 1 + read-write + + + SCLK_ACTIVE + The clock switch for i2c module + 21 + 1 + read-write + + + + + COMD0 + I2C command register 0 + 0x58 + 0x20 + + + COMMAND0 + Configures command 0. It consists of three parts: +op_code is the command, +0: RSTART, +1: WRITE, +2: READ, +3: STOP, +4: END. + +Byte_num represents the number of bytes that need to be sent or received. +ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information. + 0 + 14 + read-write + + + COMMAND0_DONE + Represents whether command 0 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD1 + I2C command register 1 + 0x5C + 0x20 + + + COMMAND1 + Configures command 1. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND1_DONE + Represents whether command 1 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD2 + I2C command register 2 + 0x60 + 0x20 + + + COMMAND2 + Configures command 2. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND2_DONE + Represents whether command 2 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD3 + I2C command register 3 + 0x64 + 0x20 + + + COMMAND3 + Configures command 3. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND3_DONE + Represents whether command 3 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD4 + I2C command register 4 + 0x68 + 0x20 + + + COMMAND4 + Configures command 4. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND4_DONE + Represents whether command 4 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD5 + I2C command register 5 + 0x6C + 0x20 + + + COMMAND5 + Configures command 5. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND5_DONE + Represents whether command 5 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD6 + I2C command register 6 + 0x70 + 0x20 + + + COMMAND6 + Configures command 6. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND6_DONE + Represents whether command 6 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + COMD7 + I2C command register 7 + 0x74 + 0x20 + + + COMMAND7 + Configures command 7. See details in I2C_CMD0_REG[13:0]. + 0 + 14 + read-write + + + COMMAND7_DONE + Represents whether command 7 is done in I2C Master mode. +0: Not done + +1: Done + 31 + 1 + read-write + + + + + SCL_ST_TIME_OUT + SCL status time out register + 0x78 + 0x20 + 0x00000010 + + + SCL_ST_TO_I2C + Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_MAIN_ST_TIME_OUT + SCL main status time out register + 0x7C + 0x20 + 0x00000010 + + + SCL_MAIN_ST_TO_I2C + Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. +Measurement unit: i2c_sclk + 0 + 5 + read-write + + + + + SCL_SP_CONF + Power configuration register + 0x80 + 0x20 + + + SCL_RST_SLV_EN + When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 0 + 1 + read-write + + + SCL_RST_SLV_NUM + Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]. + 1 + 5 + read-write + + + SCL_PD_EN + Configure the pulses of SCL generated in I2C master mode. +Valid when reg_scl_rst_slv_en is 1. +Measurement unit: i2c_sclk + 6 + 1 + read-write + + + SDA_PD_EN + Configures to power down the I2C output SCL line. +0: Not power down. + +1: Power down. +Valid only when reg_scl_force_out is 1. + 7 + 1 + read-write + + + + + DATE + Version register + 0xF8 + 0x20 + 0x02201143 + + + DATE + Version control register. + 0 + 32 + read-write + + + + + TXFIFO_START_ADDR + I2C TXFIFO base address register + 0x100 + 0x20 + + + TXFIFO_START_ADDR + Represents the I2C txfifo first address. + 0 + 32 + read-only + + + + + RXFIFO_START_ADDR + I2C RXFIFO base address register + 0x180 + 0x20 + + + RXFIFO_START_ADDR + Represents the I2C rxfifo first address. + 0 + 32 + read-only + + + + + + + LP_I2S0 + Low-power I2S (Inter-IC Sound) Controller 0 + LP_I2S + 0x50125000 + + 0x0 + 0x98 + registers + + + LP_I2S0 + 12 + + + + VAD_CONF + I2S VAD Configure register + 0x0 + 0x20 + + + VAD_EN + VAD enable register + 0 + 1 + read-write + + + VAD_RESET + VAD reset register + 1 + 1 + write-only + + + VAD_FORCE_START + VAD force start register. + 2 + 1 + write-only + + + + + VAD_RESULT + I2S VAD Result register + 0x4 + 0x20 + + + VAD_FLAG + Reg vad flag observe signal + 0 + 1 + read-only + + + ENERGY_ENOUGH + Reg energy enough observe signal + 1 + 1 + read-only + + + + + RX_MEM_CONF + I2S VAD Observe register + 0x8 + 0x20 + 0x00007E00 + + + RX_MEM_FIFO_CNT + The number of data in the rx mem + 0 + 9 + read-only + + + RX_MEM_THRESHOLD + I2S rx mem will trigger an interrupt when the data in the mem is over(not including equal) reg_rx_mem_threshold + 9 + 8 + read-write + + + + + INT_RAW + I2S interrupt raw register, valid in level. + 0xC + 0x20 + + + RX_DONE_INT_RAW + The raw interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + RX_HUNG_INT_RAW + The raw interrupt status bit for the i2s_rx_hung_int interrupt + 1 + 1 + read-only + + + RX_FIFOMEM_UDF_INT_RAW + The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + read-only + + + VAD_DONE_INT_RAW + The raw interrupt status bit for the vad_done_int interrupt + 3 + 1 + read-only + + + VAD_RESET_DONE_INT_RAW + The raw interrupt status bit for the vad_reset_done_int interrupt + 4 + 1 + read-only + + + RX_MEM_THRESHOLD_INT_RAW + The raw interrupt status bit for the rx_mem_threshold_int interrupt + 5 + 1 + read-only + + + + + INT_ST + I2S interrupt status register. + 0x10 + 0x20 + + + RX_DONE_INT_ST + The masked interrupt status bit for the i2s_rx_done_int interrupt + 0 + 1 + read-only + + + RX_HUNG_INT_ST + The masked interrupt status bit for the i2s_rx_hung_int interrupt + 1 + 1 + read-only + + + RX_FIFOMEM_UDF_INT_ST + The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + read-only + + + LP_VAD_DONE_INT_ST + The masked interrupt status bit for the vad_done_int interrupt + 3 + 1 + read-only + + + LP_VAD_RESET_DONE_INT_ST + The masked interrupt status bit for the vad_reset_done_int interrupt + 4 + 1 + read-only + + + RX_MEM_THRESHOLD_INT_ST + The masked interrupt status bit for the rx_mem_threshold_int interrupt + 5 + 1 + read-only + + + + + INT_ENA + I2S interrupt enable register. + 0x14 + 0x20 + + + RX_DONE_INT_ENA + The interrupt enable bit for the i2s_rx_done_int interrupt + 0 + 1 + read-write + + + RX_HUNG_INT_ENA + The interrupt enable bit for the i2s_rx_hung_int interrupt + 1 + 1 + read-write + + + RX_FIFOMEM_UDF_INT_ENA + The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + read-write + + + LP_VAD_DONE_INT_ENA + The interrupt enable bit for the vad_done_int interrupt + 3 + 1 + read-write + + + LP_VAD_RESET_DONE_INT_ENA + The interrupt enable bit for the vad_reset_done_int interrupt + 4 + 1 + read-write + + + RX_MEM_THRESHOLD_INT_ENA + The interrupt enable bit for the rx_mem_threshold_int interrupt + 5 + 1 + read-write + + + + + INT_CLR + I2S interrupt clear register. + 0x18 + 0x20 + + + RX_DONE_INT_CLR + Set this bit to clear the i2s_rx_done_int interrupt + 0 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the i2s_rx_hung_int interrupt + 1 + 1 + write-only + + + RX_FIFOMEM_UDF_INT_CLR + Set this bit to clear the i2s_rx_fifomem_udf_int interrupt + 2 + 1 + write-only + + + LP_VAD_DONE_INT_CLR + Set this bit to clear the vad_done_int interrupt + 3 + 1 + write-only + + + LP_VAD_RESET_DONE_INT_CLR + Set this bit to clear the vad_reset_done_int interrupt + 4 + 1 + write-only + + + RX_MEM_THRESHOLD_INT_CLR + Set this bit to clear the rx_mem_threshold_int interrupt + 5 + 1 + write-only + + + + + RX_CONF + I2S RX configure register + 0x20 + 0x20 + 0x00009600 + + + RX_RESET + Set this bit to reset receiver + 0 + 1 + write-only + + + RX_FIFO_RESET + Set this bit to reset Rx AFIFO + 1 + 1 + write-only + + + RX_START + Set this bit to start receiving data + 2 + 1 + read-write + + + RX_SLAVE_MOD + Set this bit to enable slave receiver mode + 3 + 1 + read-write + + + RX_FIFOMEM_RESET + Set this bit to reset Rx Syncfifomem + 4 + 1 + write-only + + + RX_MONO + Set this bit to enable receiver in mono mode + 5 + 1 + read-write + + + RX_BIG_ENDIAN + I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. + 7 + 1 + read-write + + + RX_UPDATE + Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + 8 + 1 + read-write + + + RX_MONO_FST_VLD + 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. + 9 + 1 + read-write + + + RX_PCM_CONF + I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & + 10 + 2 + read-write + + + RX_PCM_BYPASS + Set this bit to bypass Compress/Decompress module for received data. + 12 + 1 + read-write + + + RX_STOP_MODE + 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. + 13 + 2 + read-write + + + RX_LEFT_ALIGN + 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. + 15 + 1 + read-write + + + RX_24_FILL_EN + 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. + 16 + 1 + read-write + + + RX_WS_IDLE_POL + 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. + 17 + 1 + read-write + + + RX_BIT_ORDER + I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. + 18 + 1 + read-write + + + RX_TDM_EN + 1: Enable I2S TDM Rx mode . 0: Disable. + 19 + 1 + read-write + + + RX_PDM_EN + 1: Enable I2S PDM Rx mode . 0: Disable. + 20 + 1 + read-write + + + + + RX_CONF1 + I2S RX configure register 1 + 0x28 + 0x20 + 0x2F3DE300 + + + RX_TDM_WS_WIDTH + The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck + 0 + 7 + read-write + + + RX_BCK_DIV_NUM + Bit clock configuration bits in receiver mode. + 7 + 6 + read-write + + + RX_BITS_MOD + Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. + 13 + 5 + read-write + + + RX_HALF_SAMPLE_BITS + I2S Rx half sample bits -1. + 18 + 6 + read-write + + + RX_TDM_CHAN_BITS + The Rx bit number for each channel minus 1in TDM mode. + 24 + 5 + read-write + + + RX_MSB_SHIFT + Set this bit to enable receiver in Phillips standard mode + 29 + 1 + read-write + + + + + RX_TDM_CTRL + I2S TX TDM mode control register + 0x50 + 0x20 + 0x00000003 + + + RX_TDM_PDM_CHAN0_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. + 0 + 1 + read-write + + + RX_TDM_PDM_CHAN1_EN + 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. + 1 + 1 + read-write + + + RX_TDM_TOT_CHAN_NUM + The total channel number of I2S TX TDM mode. + 16 + 4 + read-write + + + + + RX_TIMING + I2S RX timing control register + 0x58 + 0x20 + + + RX_SD_IN_DM + The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 0 + 2 + read-write + + + RX_WS_OUT_DM + The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 16 + 2 + read-write + + + RX_BCK_OUT_DM + The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 20 + 2 + read-write + + + RX_WS_IN_DM + The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 24 + 2 + read-write + + + RX_BCK_IN_DM + The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. + 28 + 2 + read-write + + + + + LC_HUNG_CONF + I2S HUNG configure register. + 0x60 + 0x20 + 0x00000810 + + + LC_FIFO_TIMEOUT + the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + 0 + 8 + read-write + + + LC_FIFO_TIMEOUT_SHIFT + The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + 8 + 3 + read-write + + + LC_FIFO_TIMEOUT_ENA + The enable bit for FIFO timeout + 11 + 1 + read-write + + + + + RXEOF_NUM + I2S RX data number control register. + 0x64 + 0x20 + 0x00000040 + + + RX_EOF_NUM + The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. + 0 + 12 + read-write + + + + + CONF_SIGLE_DATA + I2S signal data register + 0x68 + 0x20 + + + SINGLE_DATA + The configured constant channel data to be sent out. + 0 + 32 + read-write + + + + + RX_PDM_CONF + I2S RX configure register + 0x70 + 0x20 + 0xF8200000 + + + RX_PDM2PCM_EN + 1: Enable PDM2PCM RX mode. 0: DIsable. + 19 + 1 + read-write + + + RX_PDM_SINC_DSR_16_EN + Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64. + 20 + 1 + read-write + + + RX_PDM2PCM_AMPLIFY_NUM + Configure PDM RX amplify number. + 21 + 4 + read-write + + + RX_PDM_HP_BYPASS + I2S PDM RX bypass hp filter or not. + 25 + 1 + read-write + + + RX_IIR_HP_MULT12_5 + The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0]) + 26 + 3 + read-write + + + RX_IIR_HP_MULT12_0 + The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0]) + 29 + 3 + read-write + + + + + ECO_LOW + I2S ECO register + 0x74 + 0x20 + + + RDN_ECO_LOW + logic low eco registers + 0 + 32 + read-write + + + + + ECO_HIGH + I2S ECO register + 0x78 + 0x20 + 0xFFFFFFFF + + + RDN_ECO_HIGH + logic high eco registers + 0 + 32 + read-write + + + + + ECO_CONF + I2S ECO register + 0x7C + 0x20 + + + RDN_ENA + enable rdn counter bit + 0 + 1 + read-write + + + RDN_RESULT + rdn result + 1 + 1 + read-only + + + + + VAD_PARAM0 + I2S VAD Parameter register + 0x80 + 0x20 + 0x00C81388 + + + PARAM_MIN_ENERGY + VAD parameter + 0 + 16 + read-write + + + PARAM_INIT_FRAME_NUM + VAD parameter + 16 + 9 + read-write + + + + + VAD_PARAM1 + I2S VAD Parameter register + 0x84 + 0x20 + 0x281E1E43 + + + PARAM_MIN_SPEECH_COUNT + VAD parameter + 0 + 4 + read-write + + + PARAM_MAX_SPEECH_COUNT + VAD parameter + 4 + 7 + read-write + + + PARAM_HANGOVER_SPEECH + VAD parameter + 11 + 5 + read-write + + + PARAM_HANGOVER_SILENT + VAD parameter + 16 + 8 + read-write + + + PARAM_MAX_OFFSET + VAD parameter + 24 + 7 + read-write + + + PARAM_SKIP_BAND_ENERGY + Set 1 to skip band energy check. + 31 + 1 + read-write + + + + + VAD_PARAM2 + I2S VAD Parameter register + 0x88 + 0x20 + 0x7EB86666 + + + PARAM_NOISE_AMP_DOWN + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_AMP_UP + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM3 + I2S VAD Parameter register + 0x8C + 0x20 + 0x7D717FDF + + + PARAM_NOISE_SPE_UP0 + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_SPE_UP1 + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM4 + I2S VAD Parameter register + 0x90 + 0x20 + 0x799A6666 + + + PARAM_NOISE_SPE_DOWN + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_MEAN_DOWN + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM5 + I2S VAD Parameter register + 0x94 + 0x20 + 0x7C287D71 + + + PARAM_NOISE_MEAN_UP0 + VAD parameter + 0 + 16 + read-write + + + PARAM_NOISE_MEAN_UP1 + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM6 + I2S VAD Parameter register + 0x98 + 0x20 + 0xB4007D00 + + + PARAM_NOISE_STD_FS_THSL + Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to ((noise_std_max)>>11)^2*5 + 0 + 16 + read-write + + + PARAM_NOISE_STD_FS_THSH + Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to ((noise_std_max)>>11)^2*5 + 16 + 16 + read-write + + + + + VAD_PARAM7 + I2S VAD Parameter register + 0x9C + 0x20 + 0x01487EB8 + + + PARAM_THRES_UPD_BASE + VAD parameter + 0 + 16 + read-write + + + PARAM_THRES_UPD_VARY + VAD parameter + 16 + 16 + read-write + + + + + VAD_PARAM8 + I2S VAD Parameter register + 0xA0 + 0x20 + 0x20005040 + + + PARAM_THRES_UPD_BDL + Noise_std boundary low when updating threshold. + 0 + 8 + read-write + + + PARAM_THRES_UPD_BDH + Noise_std boundary high when updating threshold. + 8 + 8 + read-write + + + PARAM_FEATURE_BURST + VAD parameter + 16 + 16 + read-write + + + + + VAD_OB0 + I2S VAD Observe register + 0xB0 + 0x20 + + + SPEECH_COUNT_OB + Reg silent count observe + 0 + 8 + read-only + + + SILENT_COUNT_OB + Reg speech count observe + 8 + 8 + read-only + + + MAX_SIGNAL0_OB + Reg max signal0 observe + 16 + 16 + read-only + + + + + VAD_OB1 + I2S VAD Observe register + 0xB4 + 0x20 + + + MAX_SIGNAL1_OB + Reg max signal1 observe + 0 + 16 + read-only + + + MAX_SIGNAL2_OB + Reg max signal2 observe + 16 + 16 + read-only + + + + + VAD_OB2 + I2S VAD Observe register + 0xB8 + 0x20 + + + NOISE_AMP_OB + Reg noise_amp observe signal + 0 + 32 + read-only + + + + + VAD_OB3 + I2S VAD Observe register + 0xBC + 0x20 + + + NOISE_MEAN_OB + Reg noise_mean observe signal + 0 + 32 + read-only + + + + + VAD_OB4 + I2S VAD Observe register + 0xC0 + 0x20 + + + NOISE_STD_OB + Reg noise_std observe signal + 0 + 32 + read-only + + + + + VAD_OB5 + I2S VAD Observe register + 0xC4 + 0x20 + + + OFFSET_OB + Reg offset observe signal + 0 + 32 + read-only + + + + + VAD_OB6 + I2S VAD Observe register + 0xC8 + 0x20 + + + THRESHOLD_OB + Reg threshold observe signal + 0 + 32 + read-only + + + + + VAD_OB7 + I2S VAD Observe register + 0xCC + 0x20 + + + ENERGY_LOW_OB + Reg energy bit 31~0 observe signal + 0 + 32 + read-only + + + + + VAD_OB8 + I2S VAD Observe register + 0xD0 + 0x20 + + + ENERGY_HIGH_OB + Reg energy bit 63~32 observe signal + 0 + 32 + read-only + + + + + CLK_GATE + Clock gate register + 0xF8 + 0x20 + 0x0000000A + + + CLK_EN + set this bit to enable clock gate + 0 + 1 + read-write + + + VAD_CG_FORCE_ON + VAD clock gate force on register + 1 + 1 + read-write + + + RX_MEM_CG_FORCE_ON + I2S rx mem clock gate force on register + 2 + 1 + read-write + + + RX_REG_CG_FORCE_ON + I2S rx reg clock gate force on register + 3 + 1 + read-write + + + + + DATE + Version control register + 0xFC + 0x20 + 0x02305040 + + + DATE + I2S version control register + 0 + 28 + read-write + + + + + + + LP_IO_MUX + Low-power Input/Output Multiplexer + LP_IOMUX + 0x5012B000 + + 0x0 + 0x54 + registers + + + + CLK_EN + Reserved + 0x0 + 0x20 + 0x00000001 + + + REG_CLK_EN + Reserved + 0 + 1 + read-write + + + + + VER_DATE + Reserved + 0x4 + 0x20 + 0x00230313 + + + REG_VER_DATE + Reserved + 0 + 28 + read-write + + + + + PAD0 + Reserved + 0x8 + 0x20 + 0x00000002 + + + REG_PAD0_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD0_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD0_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD0_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD0_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD0_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD0_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD0_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD0_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD0_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD1 + Reserved + 0xC + 0x20 + 0x00000002 + + + REG_PAD1_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD1_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD1_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD1_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD1_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD1_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD1_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD1_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD1_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD1_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD2 + Reserved + 0x10 + 0x20 + 0x00000002 + + + REG_PAD2_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD2_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD2_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD2_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD2_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD2_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD2_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD2_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD2_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD2_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD3 + Reserved + 0x14 + 0x20 + 0x00000002 + + + REG_PAD3_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD3_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD3_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD3_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD3_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD3_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD3_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD3_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD3_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD3_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD4 + Reserved + 0x18 + 0x20 + 0x00000002 + + + REG_PAD4_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD4_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD4_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD4_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD4_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD4_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD4_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD4_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD4_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD4_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD5 + Reserved + 0x1C + 0x20 + 0x00000002 + + + REG_PAD5_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD5_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD5_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD5_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD5_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD5_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD5_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD5_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD5_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD5_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD6 + Reserved + 0x20 + 0x20 + 0x00000002 + + + REG_PAD6_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD6_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD6_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD6_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD6_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD6_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD6_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD6_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD6_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD6_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD7 + Reserved + 0x24 + 0x20 + 0x00000002 + + + REG_PAD7_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD7_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD7_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD7_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD7_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD7_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD7_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD7_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD7_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD7_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD8 + Reserved + 0x28 + 0x20 + 0x00000002 + + + REG_PAD8_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD8_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD8_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD8_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD8_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD8_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD8_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD8_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD8_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD8_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD9 + Reserved + 0x2C + 0x20 + 0x00000002 + + + REG_PAD9_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD9_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD9_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD9_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD9_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD9_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD9_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD9_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD9_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD9_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD10 + Reserved + 0x30 + 0x20 + 0x00000002 + + + REG_PAD10_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD10_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD10_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD10_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD10_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD10_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD10_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD10_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD10_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD10_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD11 + Reserved + 0x34 + 0x20 + 0x00000002 + + + REG_PAD11_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD11_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD11_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD11_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD11_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD11_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD11_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD11_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD11_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD11_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD120 + Reserved + 0x38 + 0x20 + 0x00000002 + + + REG_PAD12_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD12_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD12_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD12_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD12_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD12_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD12_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD12_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD12_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD12_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD13 + Reserved + 0x3C + 0x20 + 0x00000002 + + + REG_PAD13_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD13_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD13_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD13_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD13_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD13_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD13_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD13_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD13_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD13_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD14 + Reserved + 0x40 + 0x20 + 0x00000002 + + + REG_PAD14_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD14_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD14_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD14_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD14_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD14_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD14_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD14_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD14_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD14_FILTER_EN + need des + 11 + 1 + read-write + + + + + PAD15 + Reserved + 0x44 + 0x20 + 0x00000002 + + + REG_PAD15_DRV + Reserved + 0 + 2 + read-write + + + REG_PAD15_RDE + Reserved + 2 + 1 + read-write + + + REG_PAD15_RUE + Reserved + 3 + 1 + read-write + + + REG_PAD15_MUX_SEL + 1:use LP GPIO,0: use digital GPIO + 4 + 1 + read-write + + + REG_PAD15_FUN_SEL + function sel + 5 + 2 + read-write + + + REG_PAD15_SLP_SEL + 1: enable sleep mode during sleep,0: no sleep mode + 7 + 1 + read-write + + + REG_PAD15_SLP_IE + input enable in sleep mode + 8 + 1 + read-write + + + REG_PAD15_SLP_OE + output enable in sleep mode + 9 + 1 + read-write + + + REG_PAD15_FUN_IE + input enable in work mode + 10 + 1 + read-write + + + REG_PAD15_FILTER_EN + need des + 11 + 1 + read-write + + + + + EXT_WAKEUP0_SEL + Reserved + 0x48 + 0x20 + + + REG_XTL_EXT_CTR_SEL + select LP GPIO 0 ~ 15 to control XTAL + 0 + 5 + read-write + + + REG_EXT_WAKEUP0_SEL + Reserved + 5 + 5 + read-write + + + + + LP_PAD_HOLD + Reserved + 0x4C + 0x20 + + + REG_LP_GPIO_HOLD + Reserved + 0 + 16 + read-write + + + + + LP_PAD_HYS + Reserved + 0x50 + 0x20 + + + REG_LP_GPIO_HYS + Reserved + 0 + 16 + read-write + + + + + + + LP_UART + Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + LP_UART + 0x50121000 + + 0x0 + 0x84 + registers + + + LP_UART + 16 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-write + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-write + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-write + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-write + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-write + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-write + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-write + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-write + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-write + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-write + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-write + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV_SYNC + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + CLKDIV_FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 3 + 5 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 19 + 5 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0_SYNC + Configuration register 0 + 0x20 + 0x20 + 0x0000001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 3 + 5 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 11 + 5 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF_SYNC + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 3 + 5 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001420F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 13 + 5 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0_SYNC + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x00006000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 3 + 5 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 11 + 5 + read-write + + + + + TXBRK_CONF_SYNC + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF_SYNC + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF_SYNC + RS485 mode configuration + 0x4C + 0x20 + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + + + AT_CMD_PRECNT_SYNC + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT_SYNC + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT_SYNC + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR_SYNC + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF_SYNC + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 3 + 5 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 12 + 5 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 3 + 5 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 12 + 5 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03000000 + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02305050 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + MCPWM0 + Motor Control Pulse-Width Modulation 0 + MCPWM + 0x500C0000 + + 0x0 + 0x14C + registers + + + PWM0 + 38 + + + + CLK_CFG + PWM clock prescaler register. + 0x0 + 0x20 + + + CLK_PRESCALE + Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1). + 0 + 8 + read-write + + + + + 3 + 0x10 + TIMER%s_CFG0 + PWM timer%s period and update method configuration register. + 0x4 + 0x20 + 0x0000FF00 + + + TIMER_PRESCALE + Configures the prescaler value of timer%s, so that the period of PT0_clk = Period of PWM_clk * (PWM_TIMER%s_PRESCALE + 1) + 0 + 8 + read-write + + + TIMER_PERIOD + Configures the period shadow of PWM timer%s + 8 + 16 + read-write + + + TIMER_PERIOD_UPMETHOD + Configures the update method for active register of PWM timer%s period.\\0: Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal zero event + 24 + 2 + read-write + + + + + 3 + 0x10 + TIMER%s_CFG1 + PWM timer%s working mode and start/stop control register. + 0x8 + 0x20 + + + TIMER_START + Configures whether or not to start/stop PWM timer%s.\\0: If PWM timer%s starts, then stops at TEZ\\1: If timer%s starts, then stops at TEP\\2: PWM timer%s starts and runs on\\3: Timer%s starts and stops at the next TEZ\\4: Timer0 starts and stops at the next TEP.\\TEP here and below means the event that happens when the timer equals to period + 0 + 3 + read-write + + + TIMER_MOD + Configures the working mode of PWM timer%s.\\0: Freeze\\1: Increase mode\\2: Decrease mode\\3: Up-down mode + 3 + 2 + read-write + + + + + 3 + 0x10 + TIMER%s_SYNC + PWM timer%s sync function configuration register. + 0xC + 0x20 + + + TIMER_SYNCI_EN + Configures whether or not to enable timer%s reloading with phase on sync input event is enabled.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + SW + Configures the generation of software sync. Toggling this bit will trigger a software sync. + 1 + 1 + read-write + + + TIMER_SYNCO_SEL + Configures the selection of PWM timer%s sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3: Invalid, sync_out selects noting + 2 + 2 + read-write + + + TIMER_PHASE + Configures the phase for timer%s reload on sync event. + 4 + 16 + read-write + + + TIMER_PHASE_DIRECTION + Configures the PWM timer%s's direction when timer%s mode is up-down mode.\\0: Increase\\1: Decrease + 20 + 1 + read-write + + + + + 3 + 0x10 + TIMER%s_STATUS + PWM timer%s status register. + 0x10 + 0x20 + + + TIMER_VALUE + Represents current PWM timer%s counter value. + 0 + 16 + read-only + + + TIMER_DIRECTION + Represents current PWM timer%s counter direction.\\0: Increment\\1: Decrement + 16 + 1 + read-only + + + + + TIMER_SYNCI_CFG + Synchronization input selection register for PWM timers. + 0x34 + 0x20 + + + TIMER0_SYNCISEL + Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + 0 + 3 + read-write + + + TIMER1_SYNCISEL + Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + 3 + 3 + read-write + + + TIMER2_SYNCISEL + Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2: PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected + 6 + 3 + read-write + + + EXTERNAL_SYNCI0_INVERT + Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1: Invert + 9 + 1 + read-write + + + EXTERNAL_SYNCI1_INVERT + Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1: Invert + 10 + 1 + read-write + + + EXTERNAL_SYNCI2_INVERT + Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1: Invert + 11 + 1 + read-write + + + + + OPERATOR_TIMERSEL + PWM operator's timer select register + 0x38 + 0x20 + + + OPERATOR0_TIMERSEL + Configures which PWM timer will be the timing reference for PWM operator0.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + 0 + 2 + read-write + + + OPERATOR1_TIMERSEL + Configures which PWM timer will be the timing reference for PWM operator1.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + 2 + 2 + read-write + + + OPERATOR2_TIMERSEL + Configures which PWM timer will be the timing reference for PWM operator2.\\0: Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2 + 4 + 2 + read-write + + + + + 3 + 0x38 + GEN%s_STMP_CFG + Generator%s time stamp registers A and B transfer status and update method register + 0x3C + 0x20 + + + CMPR_A_UPMETHOD + Configures the update method for PWM generator %s time stamp A's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 0 + 4 + read-write + + + CMPR_B_UPMETHOD + Configures the update method for PWM generator %s time stamp B's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 4 + 4 + read-write + + + CMPR_A_SHDW_FULL + Represents whether or not generator%s time stamp A's shadow reg is transferred.\\0: A's active reg has been updated with shadow register latest value.\\1: A's shadow reg is filled and waiting to be transferred to A's active reg + 8 + 1 + read-write + + + CMPR_B_SHDW_FULL + Represents whether or not generator%s time stamp B's shadow reg is transferred.\\0: B's active reg has been updated with shadow register latest value.\\1: B's shadow reg is filled and waiting to be transferred to B's active reg + 9 + 1 + read-write + + + + + 3 + 0x38 + GEN%s_TSTMP_A + Generator%s time stamp A's shadow register + 0x40 + 0x20 + + + CMPR_A + Configures the value of PWM generator %s time stamp A's shadow register. + 0 + 16 + read-write + + + + + 3 + 0x38 + GEN%s_TSTMP_B + Generator%s time stamp B's shadow register + 0x44 + 0x20 + + + CMPR_B + Configures the value of PWM generator %s time stamp B's shadow register. + 0 + 16 + read-write + + + + + 3 + 0x38 + GEN%s_CFG0 + Generator%s fault event T0 and T1 configuration register + 0x48 + 0x20 + + + GEN_CFG_UPMETHOD + Configures update method for PWM generator %s's active register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 0 + 4 + read-write + + + GEN_T0_SEL + Configures source selection for PWM generator %s event_t0, take effect immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: Invalid, Select nothing + 4 + 3 + read-write + + + GEN_T1_SEL + Configures source selection for PWM generator %s event_t1, take effect immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4: Invalid, Select nothing + 7 + 3 + read-write + + + + + 3 + 0x38 + GEN%s_FORCE + Generator%s output signal force mode register. + 0x4C + 0x20 + 0x00000020 + + + GEN_CNTUFORCE_UPMETHOD + Configures update method for continuous software force of PWM generator%s.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable update. TEA/B here and below means an event generated when the timer's value equals to that of register A/B. + 0 + 6 + read-write + + + GEN_A_CNTUFORCE_MODE + Configures continuous software force mode for PWM%s A.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 6 + 2 + read-write + + + GEN_B_CNTUFORCE_MODE + Configures continuous software force mode for PWM%s B.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 8 + 2 + read-write + + + GEN_A_NCIFORCE + Configures the generation of non-continuous immediate software-force event for PWM%s A, a toggle will trigger a force event. + 10 + 1 + read-write + + + GEN_A_NCIFORCE_MODE + Configures non-continuous immediate software force mode for PWM%s A.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 11 + 2 + read-write + + + GEN_B_NCIFORCE + Configures the generation of non-continuous immediate software-force event for PWM%s B, a toggle will trigger a force event. + 13 + 1 + read-write + + + GEN_B_NCIFORCE_MODE + Configures non-continuous immediate software force mode for PWM%s B.\\0: Disabled\\1: Low\\2: High\\3: Disabled + 14 + 2 + read-write + + + + + 3 + 0x38 + GEN%s_A + PWM%s output signal A actions configuration register + 0x50 + 0x20 + + + UTEZ + Configures action on PWM%s A triggered by event TEZ when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 0 + 2 + read-write + + + UTEP + Configures action on PWM%s A triggered by event TEP when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 2 + 2 + read-write + + + UTEA + Configures action on PWM%s A triggered by event TEA when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 4 + 2 + read-write + + + UTEB + Configures action on PWM%s A triggered by event TEB when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 6 + 2 + read-write + + + UT0 + Configures action on PWM%s A triggered by event_t0 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 8 + 2 + read-write + + + UT1 + Configures action on PWM%s A triggered by event_t1 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 10 + 2 + read-write + + + DTEZ + Configures action on PWM%s A triggered by event TEZ when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 12 + 2 + read-write + + + DTEP + Configures action on PWM%s A triggered by event TEP when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 14 + 2 + read-write + + + DTEA + Configures action on PWM%s A triggered by event TEA when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 16 + 2 + read-write + + + DTEB + Configures action on PWM%s A triggered by event TEB when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 18 + 2 + read-write + + + DT0 + Configures action on PWM%s A triggered by event_t0 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 20 + 2 + read-write + + + DT1 + Configures action on PWM%s A triggered by event_t1 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 22 + 2 + read-write + + + + + 3 + 0x38 + GEN%s_B + PWM%s output signal B actions configuration register + 0x54 + 0x20 + + + UTEZ + Configures action on PWM%s B triggered by event TEZ when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 0 + 2 + read-write + + + UTEP + Configures action on PWM%s B triggered by event TEP when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 2 + 2 + read-write + + + UTEA + Configures action on PWM%s B triggered by event TEA when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 4 + 2 + read-write + + + UTEB + Configures action on PWM%s B triggered by event TEB when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 6 + 2 + read-write + + + UT0 + Configures action on PWM%s B triggered by event_t0 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 8 + 2 + read-write + + + UT1 + Configures action on PWM%s B triggered by event_t1 when timer increasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 10 + 2 + read-write + + + DTEZ + Configures action on PWM%s B triggered by event TEZ when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 12 + 2 + read-write + + + DTEP + Configures action on PWM%s B triggered by event TEP when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 14 + 2 + read-write + + + DTEA + Configures action on PWM%s B triggered by event TEA when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 16 + 2 + read-write + + + DTEB + Configures action on PWM%s B triggered by event TEB when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 18 + 2 + read-write + + + DT0 + Configures action on PWM%s B triggered by event_t0 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 20 + 2 + read-write + + + DT1 + Configures action on PWM%s B triggered by event_t1 when timer decreasing.\\0: No change\\1: Low\\2: High\\3: Toggle + 22 + 2 + read-write + + + + + 3 + 0x38 + DT%s_CFG + Dead time configuration register + 0x58 + 0x20 + 0x00018000 + + + DB_FED_UPMETHOD + Configures update method for FED (Falling edge delay) active register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 0 + 4 + read-write + + + DB_RED_UPMETHOD + Configures update method for RED (rising edge delay) active register.\\0: Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1: Sync\\Bit3 is set to 1: Disable the update + 4 + 4 + read-write + + + DB_DEB_MODE + Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode + 8 + 1 + read-write + + + DB_A_OUTSWAP + Configures S6 in table. + 9 + 1 + read-write + + + DB_B_OUTSWAP + Configures S7 in table. + 10 + 1 + read-write + + + DB_RED_INSEL + Configures S4 in table. + 11 + 1 + read-write + + + DB_FED_INSEL + Configures S5 in table. + 12 + 1 + read-write + + + DB_RED_OUTINVERT + Configures S2 in table. + 13 + 1 + read-write + + + DB_FED_OUTINVERT + Configures S3 in table. + 14 + 1 + read-write + + + DB_A_OUTBYPASS + Configures S1 in table. + 15 + 1 + read-write + + + DB_B_OUTBYPASS + Configures S0 in table. + 16 + 1 + read-write + + + DB_CLK_SEL + Configures dead time generator %s clock selection.\\0: PWM_clk\\1: PT_clk + 17 + 1 + read-write + + + + + 3 + 0x38 + DT%s_FED_CFG + Falling edge delay (FED) shadow register + 0x5C + 0x20 + + + DB_FED + Configures shadow register for FED. + 0 + 16 + read-write + + + + + 3 + 0x38 + DT%s_RED_CFG + Rising edge delay (RED) shadow register + 0x60 + 0x20 + + + DB_RED + Configures shadow register for RED. + 0 + 16 + read-write + + + + + 3 + 0x38 + CARRIER%s_CFG + Carrier%s configuration register + 0x64 + 0x20 + + + CHOPPER_EN + Configures whether or not to enable carrier%s.\\0: Bypassed\\1: Enabled + 0 + 1 + read-write + + + CHOPPER_PRESCALE + Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1) + 1 + 4 + read-write + + + CHOPPER_DUTY + Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8 + 5 + 3 + read-write + + + CHOPPER_OSHTWTH + Configures width of the first pulse. Measurement unit: Periods of the carrier. + 8 + 4 + read-write + + + CHOPPER_OUT_INVERT + Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\0: Normal\\1: Invert + 12 + 1 + read-write + + + CHOPPER_IN_INVERT + Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\0: Normal\\1: Invert + 13 + 1 + read-write + + + + + 3 + 0x38 + FH%s_CFG0 + PWM%s A and PWM%s B trip events actions configuration register + 0x68 + 0x20 + + + TZ_SW_CBC + Configures whether or not to enable software force cycle-by-cycle mode action.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TZ_F2_CBC + Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TZ_F1_CBC + Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TZ_F0_CBC + Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TZ_SW_OST + Configures whether or not to enable software force one-shot mode action.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TZ_F2_OST + Configures whether or not event_f2 will trigger one-shot mode action.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TZ_F1_OST + Configures whether or not event_f1 will trigger one-shot mode action.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TZ_F0_OST + Configures whether or not event_f0 will trigger one-shot mode action.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TZ_A_CBC_D + Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 8 + 2 + read-write + + + TZ_A_CBC_U + Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 10 + 2 + read-write + + + TZ_A_OST_D + Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 12 + 2 + read-write + + + TZ_A_OST_U + Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 14 + 2 + read-write + + + TZ_B_CBC_D + Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 16 + 2 + read-write + + + TZ_B_CBC_U + Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 18 + 2 + read-write + + + TZ_B_OST_D + Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 20 + 2 + read-write + + + TZ_B_OST_U + Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle + 22 + 2 + read-write + + + + + 3 + 0x38 + FH%s_CFG1 + Software triggers for fault handler actions configuration register + 0x6C + 0x20 + + + TZ_CLR_OST + Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action. + 0 + 1 + read-write + + + TZ_CBCPULSE + Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP + 1 + 2 + read-write + + + TZ_FORCE_CBC + Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action. + 3 + 1 + read-write + + + TZ_FORCE_OST + Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action. + 4 + 1 + read-write + + + + + 3 + 0x38 + FH%s_STATUS + Fault events status register + 0x70 + 0x20 + + + TZ_CBC_ON + Represents whether or not an cycle-by-cycle mode action is on going.\\0:No action\\1: On going + 0 + 1 + read-only + + + TZ_OST_ON + Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On going + 1 + 1 + read-only + + + + + FAULT_DETECT + Fault detection configuration and status register + 0xE4 + 0x20 + + + F0_EN + Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + F1_EN + Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + F2_EN + Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + F0_POLE + Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level low\\1: Level high + 3 + 1 + read-write + + + F1_POLE + Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level low\\1: Level high + 4 + 1 + read-write + + + F2_POLE + Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level low\\1: Level high + 5 + 1 + read-write + + + EVENT_F0 + Represents whether or not an event_f0 is on going.\\0: No action\\1: On going + 6 + 1 + read-only + + + EVENT_F1 + Represents whether or not an event_f1 is on going.\\0: No action\\1: On going + 7 + 1 + read-only + + + EVENT_F2 + Represents whether or not an event_f2 is on going.\\0: No action\\1: On going + 8 + 1 + read-only + + + + + CAP_TIMER_CFG + Capture timer configuration register + 0xE8 + 0x20 + + + CAP_TIMER_EN + Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CAP_SYNCI_EN + Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + CAP_SYNCI_SEL + Configures the selection of capture module sync input.\\0: None\\1: Timer0 sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None + 2 + 3 + read-write + + + CAP_SYNC_SW + Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0: Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with value in phase register + 5 + 1 + write-only + + + + + CAP_TIMER_PHASE + Capture timer sync phase register + 0xEC + 0x20 + + + CAP_PHASE + Configures phase value for capture timer sync operation. + 0 + 32 + read-write + + + + + 3 + 0x4 + CAP_CH%s_CFG + Capture channel %s configuration register + 0xF0 + 0x20 + + + CAP_EN + Configures whether or not to enable capture on channel %s.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CAP_MODE + Configures which edge of capture on channel %s after prescaling is used.\\0: None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1: Enable capture on the positive edge + 1 + 2 + read-write + + + CAP_PRESCALE + Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1 + 3 + 8 + read-write + + + CAP_IN_INVERT + Configures whether or not to invert CAP%s from GPIO matrix before prescale.\\0: Normal\\1: Invert + 11 + 1 + read-write + + + CAP_SW + Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a software forced capture on channel %s + 12 + 1 + write-only + + + + + 3 + 0x4 + CAP_CH%s + CAP%s capture value register + 0xFC + 0x20 + + + CAP_VALUE + Represents value of last capture on CAP%s + 0 + 32 + read-only + + + + + CAP_STATUS + Last capture trigger edge information register + 0x108 + 0x20 + + + CAP0_EDGE + Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge + 0 + 1 + read-only + + + CAP1_EDGE + Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge + 1 + 1 + read-only + + + CAP2_EDGE + Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge + 2 + 1 + read-only + + + + + UPDATE_CFG + Generator Update configuration register + 0x10C + 0x20 + 0x00000005 + + + GLOBAL_UP_EN + Configures whether or not to enable global update for all active registers in MCPWM module.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + GLOBAL_FORCE_UP + Configures the generation of global forced update for all active registers in MCPWM module. A toggle (software invert its value) will trigger a global forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. + 1 + 1 + read-write + + + OP0_UP_EN + Configures whether or not to enable update of active registers in PWM operator0. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + OP0_FORCE_UP + Configures the generation of forced update for active registers in PWM operator0. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. + 3 + 1 + read-write + + + OP1_UP_EN + Configures whether or not to enable update of active registers in PWM operator1. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + OP1_FORCE_UP + Configures the generation of forced update for active registers in PWM operator1. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. + 5 + 1 + read-write + + + OP2_UP_EN + Configures whether or not to enable update of active registers in PWM operator2. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + OP2_FORCE_UP + Configures the generation of forced update for active registers in PWM operator2. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. + 7 + 1 + read-write + + + + + INT_ENA + Interrupt enable register + 0x110 + 0x20 + + + TIMER0_STOP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears. + 12 + 1 + read-write + + + FAULT1_CLR_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears. + 13 + 1 + read-write + + + FAULT2_CLR_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears. + 14 + 1 + read-write + + + CMPR0_TEA_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event. + 15 + 1 + read-write + + + CMPR1_TEA_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event. + 16 + 1 + read-write + + + CMPR2_TEA_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event. + 17 + 1 + read-write + + + CMPR0_TEB_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event. + 18 + 1 + read-write + + + CMPR1_TEB_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event. + 19 + 1 + read-write + + + CMPR2_TEB_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event. + 20 + 1 + read-write + + + TZ0_CBC_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0. + 27 + 1 + read-write + + + CAP1_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1. + 28 + 1 + read-write + + + CAP2_INT_ENA + Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2. + 29 + 1 + read-write + + + + + INT_RAW + Interrupt raw status register + 0x114 + 0x20 + + + TIMER0_STOP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops. + 0 + 1 + read-write + + + TIMER1_STOP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops. + 1 + 1 + read-write + + + TIMER2_STOP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops. + 2 + 1 + read-write + + + TIMER0_TEZ_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-write + + + TIMER1_TEZ_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-write + + + TIMER2_TEZ_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-write + + + TIMER0_TEP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-write + + + TIMER1_TEP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-write + + + TIMER2_TEP_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-write + + + FAULT0_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts. + 9 + 1 + read-write + + + FAULT1_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts. + 10 + 1 + read-write + + + FAULT2_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts. + 11 + 1 + read-write + + + FAULT0_CLR_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears. + 12 + 1 + read-write + + + FAULT1_CLR_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears. + 13 + 1 + read-write + + + FAULT2_CLR_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears. + 14 + 1 + read-write + + + CMPR0_TEA_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-write + + + CMPR1_TEA_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-write + + + CMPR2_TEA_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-write + + + CMPR0_TEB_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-write + + + CMPR1_TEB_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-write + + + CMPR2_TEB_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-write + + + TZ0_CBC_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-write + + + TZ1_CBC_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-write + + + TZ2_CBC_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-write + + + TZ0_OST_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-write + + + TZ1_OST_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-write + + + TZ2_OST_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-write + + + CAP0_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0. + 27 + 1 + read-write + + + CAP1_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1. + 28 + 1 + read-write + + + CAP2_INT_RAW + Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2. + 29 + 1 + read-write + + + + + INT_ST + Interrupt masked status register + 0x118 + 0x20 + + + TIMER0_STOP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when the timer 0 stops. + 0 + 1 + read-only + + + TIMER1_STOP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when the timer 1 stops. + 1 + 1 + read-only + + + TIMER2_STOP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when the timer 2 stops. + 2 + 1 + read-only + + + TIMER0_TEZ_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + read-only + + + TIMER1_TEZ_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + read-only + + + TIMER2_TEZ_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + read-only + + + TIMER0_TEP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + read-only + + + TIMER1_TEP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + read-only + + + TIMER2_TEP_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + read-only + + + FAULT0_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 starts. + 9 + 1 + read-only + + + FAULT1_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 starts. + 10 + 1 + read-only + + + FAULT2_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 starts. + 11 + 1 + read-only + + + FAULT0_CLR_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 clears. + 12 + 1 + read-only + + + FAULT1_CLR_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 clears. + 13 + 1 + read-only + + + FAULT2_CLR_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 clears. + 14 + 1 + read-only + + + CMPR0_TEA_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + read-only + + + CMPR1_TEA_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + read-only + + + CMPR2_TEA_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + read-only + + + CMPR0_TEB_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + read-only + + + CMPR1_TEB_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + read-only + + + CMPR2_TEB_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + read-only + + + TZ0_CBC_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + read-only + + + TZ1_CBC_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + read-only + + + TZ2_CBC_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + read-only + + + TZ0_OST_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + read-only + + + TZ1_OST_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + read-only + + + TZ2_OST_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + read-only + + + CAP0_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP0. + 27 + 1 + read-only + + + CAP1_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP1. + 28 + 1 + read-only + + + CAP2_INT_ST + Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP2. + 29 + 1 + read-only + + + + + INT_CLR + Interrupt clear register + 0x11C + 0x20 + + + TIMER0_STOP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops. + 0 + 1 + write-only + + + TIMER1_STOP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops. + 1 + 1 + write-only + + + TIMER2_STOP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops. + 2 + 1 + write-only + + + TIMER0_TEZ_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event. + 3 + 1 + write-only + + + TIMER1_TEZ_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event. + 4 + 1 + write-only + + + TIMER2_TEZ_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event. + 5 + 1 + write-only + + + TIMER0_TEP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event. + 6 + 1 + write-only + + + TIMER1_TEP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event. + 7 + 1 + write-only + + + TIMER2_TEP_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event. + 8 + 1 + write-only + + + FAULT0_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts. + 9 + 1 + write-only + + + FAULT1_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts. + 10 + 1 + write-only + + + FAULT2_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts. + 11 + 1 + write-only + + + FAULT0_CLR_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears. + 12 + 1 + write-only + + + FAULT1_CLR_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears. + 13 + 1 + write-only + + + FAULT2_CLR_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears. + 14 + 1 + write-only + + + CMPR0_TEA_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event + 15 + 1 + write-only + + + CMPR1_TEA_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event + 16 + 1 + write-only + + + CMPR2_TEA_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event + 17 + 1 + write-only + + + CMPR0_TEB_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event + 18 + 1 + write-only + + + CMPR1_TEB_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event + 19 + 1 + write-only + + + CMPR2_TEB_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event + 20 + 1 + write-only + + + TZ0_CBC_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + 21 + 1 + write-only + + + TZ1_CBC_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + 22 + 1 + write-only + + + TZ2_CBC_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + 23 + 1 + write-only + + + TZ0_OST_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM0. + 24 + 1 + write-only + + + TZ1_OST_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM1. + 25 + 1 + write-only + + + TZ2_OST_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM2. + 26 + 1 + write-only + + + CAP0_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0. + 27 + 1 + write-only + + + CAP1_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1. + 28 + 1 + write-only + + + CAP2_INT_CLR + Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2. + 29 + 1 + write-only + + + + + EVT_EN + Event enable register + 0x120 + 0x20 + + + EVT_TIMER0_STOP_EN + Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + EVT_TIMER1_STOP_EN + Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + EVT_TIMER2_STOP_EN + Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + EVT_TIMER0_TEZ_EN + Configures whether or not to enable timer0 equal zero event generate.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + EVT_TIMER1_TEZ_EN + Configures whether or not to enable timer1 equal zero event generate.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + EVT_TIMER2_TEZ_EN + Configures whether or not to enable timer2 equal zero event generate.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + EVT_TIMER0_TEP_EN + Configures whether or not to enable timer0 equal period event generate.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + EVT_TIMER1_TEP_EN + Configures whether or not to enable timer1 equal period event generate.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + EVT_TIMER2_TEP_EN + Configures whether or not to enable timer2 equal period event generate.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + EVT_OP0_TEA_EN + Configures whether or not to enable PWM generator0 timer equal a event generate.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + EVT_OP1_TEA_EN + Configures whether or not to enable PWM generator1 timer equal a event generate.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + EVT_OP2_TEA_EN + Configures whether or not to enable PWM generator2 timer equal a event generate.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + EVT_OP0_TEB_EN + Configures whether or not to enable PWM generator0 timer equal b event generate.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + EVT_OP1_TEB_EN + Configures whether or not to enable PWM generator1 timer equal b event generate.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + EVT_OP2_TEB_EN + Configures whether or not to enable PWM generator2 timer equal b event generate.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + EVT_F0_EN + Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + EVT_F1_EN + Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + EVT_F2_EN + Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + EVT_F0_CLR_EN + Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + EVT_F1_CLR_EN + Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + EVT_F2_CLR_EN + Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + EVT_TZ0_CBC_EN + Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + EVT_TZ1_CBC_EN + Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + EVT_TZ2_CBC_EN + Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + EVT_TZ0_OST_EN + Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + EVT_TZ1_OST_EN + Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + EVT_TZ2_OST_EN + Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + EVT_CAP0_EN + Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + EVT_CAP1_EN + Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + EVT_CAP2_EN + Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + + + TASK_EN + Task enable register + 0x124 + 0x20 + + + TASK_CMPR0_A_UP_EN + Configures whether or not to enable PWM generator0 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + TASK_CMPR1_A_UP_EN + Configures whether or not to enable PWM generator1 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + TASK_CMPR2_A_UP_EN + Configures whether or not to enable PWM generator2 timer stamp A's shadow register update task receive.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + TASK_CMPR0_B_UP_EN + Configures whether or not to enable PWM generator0 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + TASK_CMPR1_B_UP_EN + Configures whether or not to enable PWM generator1 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + TASK_CMPR2_B_UP_EN + Configures whether or not to enable PWM generator2 timer stamp B's shadow register update task receive.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + TASK_GEN_STOP_EN + Configures whether or not to enable all PWM generate stop task receive.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + TASK_TIMER0_SYNC_EN + Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + TASK_TIMER1_SYNC_EN + Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + TASK_TIMER2_SYNC_EN + Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + TASK_TIMER0_PERIOD_UP_EN + Configures whether or not to enable timer0 period update task receive.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + TASK_TIMER1_PERIOD_UP_EN + Configures whether or not to enable timer1 period update task receive.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + TASK_TIMER2_PERIOD_UP_EN + Configures whether or not to enable timer2 period update task receive.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + TASK_TZ0_OST_EN + Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + TASK_TZ1_OST_EN + Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + TASK_TZ2_OST_EN + Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + TASK_CLR0_OST_EN + Configures whether or not to enable one shot trip0 clear task receive.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + TASK_CLR1_OST_EN + Configures whether or not to enable one shot trip1 clear task receive.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + TASK_CLR2_OST_EN + Configures whether or not to enable one shot trip2 clear task receive.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + TASK_CAP0_EN + Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + TASK_CAP1_EN + Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + TASK_CAP2_EN + Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + + + EVT_EN2 + Event enable register2 + 0x128 + 0x20 + + + EVT_OP0_TEE1_EN + Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + EVT_OP1_TEE1_EN + Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + EVT_OP2_TEE1_EN + Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG event generate.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + EVT_OP0_TEE2_EN + Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + EVT_OP1_TEE2_EN + Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + EVT_OP2_TEE2_EN + Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG event generate.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + + + 3 + 0x8 + OP%s_TSTMP_E1 + Generator%s timer stamp E1 value register + 0x12C + 0x20 + + + OP_TSTMP_E1 + Configures generator%s timer stamp E1 value register + 0 + 16 + read-write + + + + + 3 + 0x8 + OP%s_TSTMP_E2 + Generator%s timer stamp E2 value register + 0x130 + 0x20 + + + OP_TSTMP_E2 + Configures generator%s timer stamp E2 value register + 0 + 16 + read-write + + + + + CLK + Global configuration register + 0x144 + 0x20 + + + EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 0 + 1 + read-write + + + + + VERSION + Version register. + 0x148 + 0x20 + 0x02212290 + + + DATE + Configures the version. + 0 + 28 + read-write + + + + + + + MCPWM1 + Motor Control Pulse-Width Modulation 1 + 0x500C1000 + + PWM1 + 39 + + + + PARL_IO + Parallel IO Controller + PARL_IO + 0x500CF000 + + 0x0 + 0x54 + registers + + + PARLIO_RX + 113 + + + PARLIO_TX + 114 + + + + RX_MODE_CFG + Parallel RX Sampling mode configuration register. + 0x0 + 0x20 + 0x00E00000 + + + RX_EXT_EN_SEL + Configures rx external enable signal selection from IO PAD. + 21 + 4 + read-write + + + RX_SW_EN + Set this bit to enable data sampling by software. + 25 + 1 + read-write + + + RX_EXT_EN_INV + Set this bit to invert the external enable signal. + 26 + 1 + read-write + + + RX_PULSE_SUBMODE_SEL + Configures the rxd pulse sampling submode. +4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) +4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) +4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) +4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) +4'd4: positive pulse start(data bit included) && length end +4'd5: positive pulse start(data bit excluded) && length end + 27 + 3 + read-write + + + RX_SMP_MODE_SEL + Configures the rxd sampling mode. +2'b00: external level enable mode +2'b01: external pulse enable mode +2'b10: internal software enable mode + 30 + 2 + read-write + + + + + RX_DATA_CFG + Parallel RX data configuration register. + 0x4 + 0x20 + 0x60000000 + + + RX_BITLEN + Configures expected byte number of received data. + 9 + 19 + read-write + + + RX_DATA_ORDER_INV + Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + 28 + 1 + read-write + + + RX_BUS_WID_SEL + Configures the rxd bus width. +3'd0: bus width is 1. +3'd1: bus width is 2. +3'd2: bus width is 4. +3'd3: bus width is 8. + 29 + 3 + read-write + + + + + RX_GENRL_CFG + Parallel RX general configuration register. + 0x8 + 0x20 + 0x21FFE000 + + + RX_GATING_EN + Set this bit to enable the clock gating of output rx clock. + 12 + 1 + read-write + + + RX_TIMEOUT_THRES + Configures threshold of timeout counter. + 13 + 16 + read-write + + + RX_TIMEOUT_EN + Set this bit to enable timeout function to generate error eof. + 29 + 1 + read-write + + + RX_EOF_GEN_SEL + Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by external enable signal. + 30 + 1 + read-write + + + + + RX_START_CFG + Parallel RX Start configuration register. + 0xC + 0x20 + + + RX_START + Set this bit to start rx data sampling. + 31 + 1 + read-write + + + + + TX_DATA_CFG + Parallel TX data configuration register. + 0x10 + 0x20 + 0x60000000 + + + TX_BITLEN + Configures expected byte number of sent data. + 9 + 19 + read-write + + + TX_DATA_ORDER_INV + Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + 28 + 1 + read-write + + + TX_BUS_WID_SEL + Configures the txd bus width. +3'd0: bus width is 1. +3'd1: bus width is 2. +3'd2: bus width is 4. +3'd3: bus width is 8. + 29 + 3 + read-write + + + + + TX_START_CFG + Parallel TX Start configuration register. + 0x14 + 0x20 + + + TX_START + Set this bit to start tx data transmit. + 31 + 1 + read-write + + + + + TX_GENRL_CFG + Parallel TX general configuration register. + 0x18 + 0x20 + + + TX_EOF_GEN_SEL + Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by DMA eof. + 13 + 1 + read-write + + + TX_IDLE_VALUE + Configures bus value of transmitter in IDLE state. + 14 + 16 + read-write + + + TX_GATING_EN + Set this bit to enable the clock gating of output tx clock. + 30 + 1 + read-write + + + TX_VALID_OUTPUT_EN + Set this bit to enable the output of tx data valid signal. + 31 + 1 + read-write + + + + + FIFO_CFG + Parallel IO FIFO configuration register. + 0x1C + 0x20 + + + TX_FIFO_SRST + Set this bit to reset async fifo in tx module. + 30 + 1 + read-write + + + RX_FIFO_SRST + Set this bit to reset async fifo in rx module. + 31 + 1 + read-write + + + + + REG_UPDATE + Parallel IO FIFO configuration register. + 0x20 + 0x20 + + + RX_REG_UPDATE + Set this bit to update rx register configuration. + 31 + 1 + write-only + + + + + ST + Parallel IO module status register0. + 0x24 + 0x20 + + + TX_READY + Represents the status that tx is ready to transmit. + 31 + 1 + read-only + + + + + INT_ENA + Parallel IO interrupt enable singal configuration register. + 0x28 + 0x20 + + + TX_FIFO_REMPTY_INT_ENA + Set this bit to enable TX_FIFO_REMPTY_INT. + 0 + 1 + read-write + + + RX_FIFO_WOVF_INT_ENA + Set this bit to enable RX_FIFO_WOVF_INT. + 1 + 1 + read-write + + + TX_EOF_INT_ENA + Set this bit to enable TX_EOF_INT. + 2 + 1 + read-write + + + + + INT_RAW + Parallel IO interrupt raw singal status register. + 0x2C + 0x20 + + + TX_FIFO_REMPTY_INT_RAW + The raw interrupt status of TX_FIFO_REMPTY_INT. + 0 + 1 + read-write + + + RX_FIFO_WOVF_INT_RAW + The raw interrupt status of RX_FIFO_WOVF_INT. + 1 + 1 + read-write + + + TX_EOF_INT_RAW + The raw interrupt status of TX_EOF_INT. + 2 + 1 + read-write + + + + + INT_ST + Parallel IO interrupt singal status register. + 0x30 + 0x20 + + + TX_FIFO_REMPTY_INT_ST + The masked interrupt status of TX_FIFO_REMPTY_INT. + 0 + 1 + read-only + + + RX_FIFO_WOVF_INT_ST + The masked interrupt status of RX_FIFO_WOVF_INT. + 1 + 1 + read-only + + + TX_EOF_INT_ST + The masked interrupt status of TX_EOF_INT. + 2 + 1 + read-only + + + + + INT_CLR + Parallel IO interrupt clear singal configuration register. + 0x34 + 0x20 + + + TX_FIFO_REMPTY_INT_CLR + Set this bit to clear TX_FIFO_REMPTY_INT. + 0 + 1 + write-only + + + RX_FIFO_WOVF_INT_CLR + Set this bit to clear RX_FIFO_WOVF_INT. + 1 + 1 + write-only + + + TX_EOF_INT_CLR + Set this bit to clear TX_EOF_INT. + 2 + 1 + write-only + + + + + RX_ST0 + Parallel IO RX status register0 + 0x38 + 0x20 + + + RX_CNT + Indicates the cycle number of reading Rx FIFO. + 8 + 5 + read-only + + + RX_FIFO_WR_BIT_CNT + Indicates the current written bit number into Rx FIFO. + 13 + 19 + read-only + + + + + RX_ST1 + Parallel IO RX status register1 + 0x3C + 0x20 + + + RX_FIFO_RD_BIT_CNT + Indicates the current read bit number from Rx FIFO. + 13 + 19 + read-only + + + + + TX_ST0 + Parallel IO TX status register0 + 0x40 + 0x20 + + + TX_CNT + Indicates the cycle number of reading Tx FIFO. + 6 + 7 + read-only + + + TX_FIFO_RD_BIT_CNT + Indicates the current read bit number from Tx FIFO. + 13 + 19 + read-only + + + + + RX_CLK_CFG + Parallel IO RX clk configuration register + 0x44 + 0x20 + + + RX_CLK_I_INV + Set this bit to invert the input Rx core clock. + 30 + 1 + read-write + + + RX_CLK_O_INV + Set this bit to invert the output Rx core clock. + 31 + 1 + read-write + + + + + TX_CLK_CFG + Parallel IO TX clk configuration register + 0x48 + 0x20 + + + TX_CLK_I_INV + Set this bit to invert the input Tx core clock. + 30 + 1 + read-write + + + TX_CLK_O_INV + Set this bit to invert the output Tx core clock. + 31 + 1 + read-write + + + + + CLK + Parallel IO clk configuration register + 0x120 + 0x20 + + + EN + Force clock on for this register file + 31 + 1 + read-write + + + + + VERSION + Version register. + 0x3FC + 0x20 + 0x02212260 + + + DATE + Version of this register file + 0 + 28 + read-write + + + + + + + PAU + PAU Peripheral + PAU + 0x60093000 + + 0x0 + 0x44 + registers + + + PAU + 112 + + + + REGDMA_CONF + Peri backup control register + 0x0 + 0x20 + + + FLOW_ERR + backup error type + 0 + 3 + read-only + + + START + backup start signal + 3 + 1 + write-only + + + TO_MEM + backup direction(reg to mem / mem to reg) + 4 + 1 + read-write + + + LINK_SEL + Link select + 5 + 2 + read-write + + + START_MAC + mac sw backup start signal + 7 + 1 + write-only + + + TO_MEM_MAC + mac sw backup direction(reg to mem / mem to reg) + 8 + 1 + read-write + + + SEL_MAC + mac hw/sw select + 9 + 1 + read-write + + + + + REGDMA_CLK_CONF + Clock control register + 0x4 + 0x20 + + + CLK_EN + clock enable + 0 + 1 + read-write + + + + + REGDMA_ETM_CTRL + ETM start ctrl reg + 0x8 + 0x20 + + + ETM_START_0 + etm_start_0 reg + 0 + 1 + write-only + + + ETM_START_1 + etm_start_1 reg + 1 + 1 + write-only + + + ETM_START_2 + etm_start_2 reg + 2 + 1 + write-only + + + ETM_START_3 + etm_start_3 reg + 3 + 1 + write-only + + + + + REGDMA_LINK_0_ADDR + link_0_addr + 0xC + 0x20 + + + LINK_ADDR_0 + link_0_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_1_ADDR + Link_1_addr + 0x10 + 0x20 + + + LINK_ADDR_1 + Link_1_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_2_ADDR + Link_2_addr + 0x14 + 0x20 + + + LINK_ADDR_2 + Link_2_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_3_ADDR + Link_3_addr + 0x18 + 0x20 + + + LINK_ADDR_3 + Link_3_addr reg + 0 + 32 + read-write + + + + + REGDMA_LINK_MAC_ADDR + Link_mac_addr + 0x1C + 0x20 + + + LINK_ADDR_MAC + Link_mac_addr reg + 0 + 32 + read-write + + + + + REGDMA_CURRENT_LINK_ADDR + current link addr + 0x20 + 0x20 + + + CURRENT_LINK_ADDR + current link addr reg + 0 + 32 + read-only + + + + + REGDMA_BACKUP_ADDR + Backup addr + 0x24 + 0x20 + + + BACKUP_ADDR + backup addr reg + 0 + 32 + read-only + + + + + REGDMA_MEM_ADDR + mem addr + 0x28 + 0x20 + + + MEM_ADDR + mem addr reg + 0 + 32 + read-only + + + + + REGDMA_BKP_CONF + backup config + 0x2C + 0x20 + 0x7D101920 + + + READ_INTERVAL + Link read_interval + 0 + 7 + read-write + + + LINK_TOUT_THRES + link wait timeout threshold + 7 + 10 + read-write + + + BURST_LIMIT + burst limit + 17 + 5 + read-write + + + BACKUP_TOUT_THRES + Backup timeout threshold + 22 + 10 + read-write + + + + + INT_ENA + Read only register for error and done + 0x30 + 0x20 + + + DONE_INT_ENA + backup done flag + 0 + 1 + read-write + + + ERROR_INT_ENA + error flag + 1 + 1 + read-write + + + + + INT_RAW + Read only register for error and done + 0x34 + 0x20 + + + DONE_INT_RAW + backup done flag + 0 + 1 + read-write + + + ERROR_INT_RAW + error flag + 1 + 1 + read-write + + + + + INT_CLR + Read only register for error and done + 0x38 + 0x20 + + + DONE_INT_CLR + backup done flag + 0 + 1 + write-only + + + ERROR_INT_CLR + error flag + 1 + 1 + write-only + + + + + INT_ST + Read only register for error and done + 0x3C + 0x20 + + + DONE_INT_ST + backup done flag + 0 + 1 + read-only + + + ERROR_INT_ST + error flag + 1 + 1 + read-only + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x02203070 + + + DATE + REGDMA date information/ REGDMA version information. + 0 + 28 + read-write + + + + + + + PCNT + Pulse Count Controller + PCNT + 0x500C9000 + + 0x0 + 0x78 + registers + + + PCNT + 111 + + + + 4 + 0xC + U%s_CONF0 + Configuration register 0 for unit %s + 0x0 + 0x20 + 0x00003C10 + + + FILTER_THRES_U + This sets the maximum threshold, in APB_CLK cycles, for the filter. + +Any pulses with width less than this will be ignored when the filter is enabled. + 0 + 10 + read-write + + + FILTER_EN_U + This is the enable bit for unit %s's input filter. + 10 + 1 + read-write + + + THR_ZERO_EN_U + This is the enable bit for unit %s's zero comparator. + 11 + 1 + read-write + + + THR_H_LIM_EN_U + This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt. + 12 + 1 + read-write + + + THR_L_LIM_EN_U + This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt. + 13 + 1 + read-write + + + THR_THRES0_EN_U + This is the enable bit for unit %s's thres0 comparator. + 14 + 1 + read-write + + + THR_THRES1_EN_U + This is the enable bit for unit %s's thres1 comparator. + 15 + 1 + read-write + + + CH0_NEG_MODE_U + This register sets the behavior when the signal input of channel 0 detects a negative edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 16 + 2 + read-write + + + CH0_POS_MODE_U + This register sets the behavior when the signal input of channel 0 detects a positive edge. + +1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter + 18 + 2 + read-write + + + CH0_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 20 + 2 + read-write + + + CH0_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 22 + 2 + read-write + + + CH1_NEG_MODE_U + This register sets the behavior when the signal input of channel 1 detects a negative edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 24 + 2 + read-write + + + CH1_POS_MODE_U + This register sets the behavior when the signal input of channel 1 detects a positive edge. + +1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter + 26 + 2 + read-write + + + CH1_HCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 28 + 2 + read-write + + + CH1_LCTRL_MODE_U + This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. + +0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification + 30 + 2 + read-write + + + + + 4 + 0xC + U%s_CONF1 + Configuration register 1 for unit %s + 0x4 + 0x20 + + + CNT_THRES0_U + This register is used to configure the thres0 value for unit %s. + 0 + 16 + read-write + + + CNT_THRES1_U + This register is used to configure the thres1 value for unit %s. + 16 + 16 + read-write + + + + + 4 + 0xC + U%s_CONF2 + Configuration register 2 for unit %s + 0x8 + 0x20 + + + CNT_H_LIM_U + This register is used to configure the thr_h_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0. + 0 + 16 + read-write + + + CNT_L_LIM_U + This register is used to configure the thr_l_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0. + 16 + 16 + read-write + + + + + 4 + 0x4 + U%s_CNT + Counter value for unit %s + 0x30 + 0x20 + + + PULSE_CNT_U + This register stores the current pulse count value for unit %s. + 0 + 16 + read-only + + + + + INT_RAW + Interrupt raw status register + 0x40 + 0x20 + + + CNT_THR_EVENT_U0_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_RAW + The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_ST + Interrupt status register + 0x44 + 0x20 + + + CNT_THR_EVENT_U0_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-only + + + CNT_THR_EVENT_U1_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-only + + + CNT_THR_EVENT_U2_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-only + + + CNT_THR_EVENT_U3_INT_ST + The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-only + + + + + INT_ENA + Interrupt enable register + 0x48 + 0x20 + + + CNT_THR_EVENT_U0_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + read-write + + + CNT_THR_EVENT_U1_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + read-write + + + CNT_THR_EVENT_U2_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + read-write + + + CNT_THR_EVENT_U3_INT_ENA + The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + read-write + + + + + INT_CLR + Interrupt clear register + 0x4C + 0x20 + + + CNT_THR_EVENT_U0_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + 0 + 1 + write-only + + + CNT_THR_EVENT_U1_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + 1 + 1 + write-only + + + CNT_THR_EVENT_U2_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + 2 + 1 + write-only + + + CNT_THR_EVENT_U3_INT_CLR + Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + 3 + 1 + write-only + + + + + 4 + 0x4 + U%s_STATUS + PNCT UNIT%s status register + 0x50 + 0x20 + + + CNT_THR_ZERO_MODE_U + The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. + 0 + 2 + read-only + + + CNT_THR_THRES1_LAT_U + The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others + 2 + 1 + read-only + + + CNT_THR_THRES0_LAT_U + The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others + 3 + 1 + read-only + + + CNT_THR_L_LIM_LAT_U + The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others + 4 + 1 + read-only + + + CNT_THR_H_LIM_LAT_U + The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others + 5 + 1 + read-only + + + CNT_THR_ZERO_LAT_U + The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others + 6 + 1 + read-only + + + + + CTRL + Control register for all counters + 0x60 + 0x20 + 0x00000001 + + + PULSE_CNT_RST_U0 + Set this bit to clear unit 0's counter. + 0 + 1 + read-write + + + CNT_PAUSE_U0 + Set this bit to freeze unit 0's counter. + 1 + 1 + read-write + + + PULSE_CNT_RST_U1 + Set this bit to clear unit 1's counter. + 2 + 1 + read-write + + + CNT_PAUSE_U1 + Set this bit to freeze unit 1's counter. + 3 + 1 + read-write + + + PULSE_CNT_RST_U2 + Set this bit to clear unit 2's counter. + 4 + 1 + read-write + + + CNT_PAUSE_U2 + Set this bit to freeze unit 2's counter. + 5 + 1 + read-write + + + PULSE_CNT_RST_U3 + Set this bit to clear unit 3's counter. + 6 + 1 + read-write + + + CNT_PAUSE_U3 + Set this bit to freeze unit 3's counter. + 7 + 1 + read-write + + + DALTA_CHANGE_EN_U0 + Configures this bit to enable unit 0's step comparator. + 8 + 1 + read-write + + + DALTA_CHANGE_EN_U1 + Configures this bit to enable unit 1's step comparator. + 9 + 1 + read-write + + + DALTA_CHANGE_EN_U2 + Configures this bit to enable unit 2's step comparator. + 10 + 1 + read-write + + + DALTA_CHANGE_EN_U3 + Configures this bit to enable unit 3's step comparator. + 11 + 1 + read-write + + + CLK_EN + The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application + 16 + 1 + read-write + + + + + U3_CHANGE_CONF + Configuration register for unit $n's step value. + 0x64 + 0x20 + + + CNT_STEP_U3 + Configures the step value for unit 3. + 0 + 16 + read-write + + + CNT_STEP_LIM_U3 + Configures the step limit value for unit 3. + 16 + 16 + read-write + + + + + U2_CHANGE_CONF + Configuration register for unit $n's step value. + 0x68 + 0x20 + + + CNT_STEP_U2 + Configures the step value for unit 2. + 0 + 16 + read-write + + + CNT_STEP_LIM_U2 + Configures the step limit value for unit 2. + 16 + 16 + read-write + + + + + U1_CHANGE_CONF + Configuration register for unit $n's step value. + 0x6C + 0x20 + + + CNT_STEP_U1 + Configures the step value for unit 1. + 0 + 16 + read-write + + + CNT_STEP_LIM_U1 + Configures the step limit value for unit 1. + 16 + 16 + read-write + + + + + U0_CHANGE_CONF + Configuration register for unit $n's step value. + 0x70 + 0x20 + + + CNT_STEP_U0 + Configures the step value for unit 0. + 0 + 16 + read-write + + + CNT_STEP_LIM_U0 + Configures the step limit value for unit 0. + 16 + 16 + read-write + + + + + DATE + PCNT version control register + 0xFC + 0x20 + 0x22091900 + + + DATE + This is the PCNT version control register. + 0 + 32 + read-write + + + + + + + PMU + PMU Peripheral + PMU + 0x50115000 + + 0x0 + 0x21C + registers + + + PMU0 + 6 + + + PMU1 + 7 + + + + HP_ACTIVE_DIG_POWER + need_des + 0x0 + 0x20 + + + HP_ACTIVE_DCDC_SWITCH_PD_EN + need_des + 21 + 1 + read-write + + + HP_ACTIVE_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_ACTIVE_PD_HP_MEM_PD_EN + need_des + 23 + 1 + read-write + + + HP_ACTIVE_PD_CNNT_PD_EN + need_des + 30 + 1 + read-write + + + HP_ACTIVE_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_ICG_HP_FUNC + need_des + 0x4 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_HP_APB + need_des + 0x8 + 0x20 + 0xFFFFFFFF + + + HP_ACTIVE_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_ICG_MODEM + need_des + 0xC + 0x20 + + + HP_ACTIVE_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_ACTIVE_HP_SYS_CNTL + need_des + 0x10 + 0x20 + + + HP_ACTIVE_HP_POWER_DET_BYPASS + need_des + 23 + 1 + read-write + + + HP_ACTIVE_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_ACTIVE_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_ACTIVE_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_ACTIVE_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_ACTIVE_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_ACTIVE_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_ACTIVE_HP_CK_POWER + need_des + 0x14 + 0x20 + + + HP_ACTIVE_I2C_ISO_EN + need_des + 21 + 1 + read-write + + + HP_ACTIVE_I2C_RETENTION + need_des + 22 + 1 + read-write + + + HP_ACTIVE_XPD_PLL_I2C + need_des + 23 + 4 + read-write + + + HP_ACTIVE_XPD_PLL + need_des + 27 + 4 + read-write + + + + + HP_ACTIVE_BIAS + need_des + 0x18 + 0x20 + 0x00500000 + + + HP_ACTIVE_DCM_VSET + need_des + 18 + 5 + read-write + + + HP_ACTIVE_DCM_MODE + need_des + 23 + 2 + read-write + + + HP_ACTIVE_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_ACTIVE_DBG_ATTEN + need_des + 26 + 4 + read-write + + + HP_ACTIVE_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_ACTIVE_BACKUP + need_des + 0x1C + 0x20 + + + HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 4 + 2 + read-write + + + HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE + need_des + 6 + 2 + read-write + + + HP_ACTIVE_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_SLEEP2ACTIVE_RETENTION_EN + need_des + 11 + 1 + read-write + + + HP_MODEM2ACTIVE_RETENTION_EN + need_des + 12 + 1 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_CLK_SEL + need_des + 14 + 2 + read-write + + + HP_MODEM2ACTIVE_BACKUP_CLK_SEL + need_des + 16 + 2 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_MODE + need_des + 20 + 3 + read-write + + + HP_MODEM2ACTIVE_BACKUP_MODE + need_des + 23 + 3 + read-write + + + HP_SLEEP2ACTIVE_BACKUP_EN + need_des + 29 + 1 + read-write + + + HP_MODEM2ACTIVE_BACKUP_EN + need_des + 30 + 1 + read-write + + + + + HP_ACTIVE_BACKUP_CLK + need_des + 0x20 + 0x20 + + + HP_ACTIVE_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_ACTIVE_SYSCLK + need_des + 0x24 + 0x20 + + + HP_ACTIVE_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + read-write + + + HP_ACTIVE_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + read-write + + + HP_ACTIVE_SYS_CLK_SLP_SEL + need_des + 28 + 1 + read-write + + + HP_ACTIVE_ICG_SLP_SEL + need_des + 29 + 1 + read-write + + + HP_ACTIVE_DIG_SYS_CLK_SEL + need_des + 30 + 2 + read-write + + + + + HP_ACTIVE_HP_REGULATOR0 + need_des + 0x28 + 0x20 + 0xC6677180 + + + LP_DBIAS_VOL + need_des + 4 + 5 + read-only + + + HP_DBIAS_VOL + need_des + 9 + 5 + read-only + + + DIG_REGULATOR0_DBIAS_SEL + need_des + 14 + 1 + read-write + + + DIG_DBIAS_INIT + need_des + 15 + 1 + write-only + + + HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_XPD + need_des + 18 + 1 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + read-write + + + HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + read-write + + + HP_ACTIVE_HP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_ACTIVE_HP_REGULATOR1 + need_des + 0x2C + 0x20 + + + HP_ACTIVE_HP_REGULATOR_DRV_B + need_des + 26 + 6 + read-write + + + + + HP_ACTIVE_XTAL + need_des + 0x30 + 0x20 + 0x80000000 + + + HP_ACTIVE_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + HP_MODEM_DIG_POWER + need_des + 0x34 + 0x20 + + + HP_MODEM_DCDC_SWITCH_PD_EN + need_des + 21 + 1 + read-write + + + HP_MODEM_HP_MEM_DSLP + need_des + 22 + 1 + write-only + + + HP_MODEM_PD_HP_MEM_PD_EN + need_des + 23 + 4 + write-only + + + HP_MODEM_PD_HP_WIFI_PD_EN + need_des + 27 + 1 + write-only + + + HP_MODEM_PD_HP_CPU_PD_EN + need_des + 29 + 1 + write-only + + + HP_MODEM_PD_CNNT_PD_EN + need_des + 30 + 1 + write-only + + + HP_MODEM_PD_TOP_PD_EN + need_des + 31 + 1 + write-only + + + + + HP_MODEM_ICG_HP_FUNC + need_des + 0x38 + 0x20 + 0xFFFFFFFF + + + HP_MODEM_DIG_ICG_FUNC_EN + need_des + 0 + 32 + write-only + + + + + HP_MODEM_ICG_HP_APB + need_des + 0x3C + 0x20 + 0xFFFFFFFF + + + HP_MODEM_DIG_ICG_APB_EN + need_des + 0 + 32 + write-only + + + + + HP_MODEM_ICG_MODEM + need_des + 0x40 + 0x20 + + + HP_MODEM_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + write-only + + + + + HP_MODEM_HP_SYS_CNTL + need_des + 0x44 + 0x20 + + + HP_MODEM_HP_POWER_DET_BYPASS + need_des + 23 + 1 + write-only + + + HP_MODEM_UART_WAKEUP_EN + need_des + 24 + 1 + write-only + + + HP_MODEM_LP_PAD_HOLD_ALL + need_des + 25 + 1 + write-only + + + HP_MODEM_HP_PAD_HOLD_ALL + need_des + 26 + 1 + write-only + + + HP_MODEM_DIG_PAD_SLP_SEL + need_des + 27 + 1 + write-only + + + HP_MODEM_DIG_PAUSE_WDT + need_des + 28 + 1 + write-only + + + HP_MODEM_DIG_CPU_STALL + need_des + 29 + 1 + write-only + + + + + HP_MODEM_HP_CK_POWER + need_des + 0x48 + 0x20 + + + HP_MODEM_I2C_ISO_EN + need_des + 21 + 1 + write-only + + + HP_MODEM_I2C_RETENTION + need_des + 22 + 1 + write-only + + + HP_MODEM_XPD_PLL_I2C + need_des + 23 + 4 + write-only + + + HP_MODEM_XPD_PLL + need_des + 27 + 4 + write-only + + + + + HP_MODEM_BIAS + need_des + 0x4C + 0x20 + 0x00500000 + + + HP_MODEM_DCM_VSET + need_des + 18 + 5 + write-only + + + HP_MODEM_DCM_MODE + need_des + 23 + 2 + write-only + + + HP_MODEM_XPD_BIAS + need_des + 25 + 1 + write-only + + + HP_MODEM_DBG_ATTEN + need_des + 26 + 4 + write-only + + + HP_MODEM_PD_CUR + need_des + 30 + 1 + write-only + + + SLEEP + need_des + 31 + 1 + write-only + + + + + HP_MODEM_BACKUP + need_des + 0x50 + 0x20 + + + HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE + need_des + 4 + 2 + write-only + + + HP_MODEM_RETENTION_MODE + need_des + 10 + 1 + write-only + + + HP_SLEEP2MODEM_RETENTION_EN + need_des + 11 + 1 + write-only + + + HP_SLEEP2MODEM_BACKUP_CLK_SEL + need_des + 14 + 2 + write-only + + + HP_SLEEP2MODEM_BACKUP_MODE + need_des + 20 + 3 + write-only + + + HP_SLEEP2MODEM_BACKUP_EN + need_des + 29 + 1 + write-only + + + + + HP_MODEM_BACKUP_CLK + need_des + 0x54 + 0x20 + + + HP_MODEM_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + write-only + + + + + HP_MODEM_SYSCLK + need_des + 0x58 + 0x20 + + + HP_MODEM_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + write-only + + + HP_MODEM_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + write-only + + + HP_MODEM_SYS_CLK_SLP_SEL + need_des + 28 + 1 + write-only + + + HP_MODEM_ICG_SLP_SEL + need_des + 29 + 1 + write-only + + + HP_MODEM_DIG_SYS_CLK_SEL + need_des + 30 + 2 + write-only + + + + + HP_MODEM_HP_REGULATOR0 + need_des + 0x5C + 0x20 + 0xC6670000 + + + HP_MODEM_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + write-only + + + HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + write-only + + + HP_MODEM_HP_REGULATOR_XPD + need_des + 18 + 1 + write-only + + + HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + write-only + + + HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + write-only + + + HP_MODEM_HP_REGULATOR_DBIAS + need_des + 27 + 5 + write-only + + + + + HP_MODEM_HP_REGULATOR1 + need_des + 0x60 + 0x20 + + + HP_MODEM_HP_REGULATOR_DRV_B + need_des + 8 + 24 + write-only + + + + + HP_MODEM_XTAL + need_des + 0x64 + 0x20 + 0x80000000 + + + HP_MODEM_XPD_XTAL + need_des + 31 + 1 + write-only + + + + + HP_SLEEP_DIG_POWER + need_des + 0x68 + 0x20 + + + HP_SLEEP_DCDC_SWITCH_PD_EN + need_des + 21 + 1 + read-write + + + HP_SLEEP_HP_MEM_DSLP + need_des + 22 + 1 + read-write + + + HP_SLEEP_PD_HP_MEM_PD_EN + need_des + 23 + 1 + read-write + + + HP_SLEEP_PD_CNNT_PD_EN + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_TOP_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_ICG_HP_FUNC + need_des + 0x6C + 0x20 + 0xFFFFFFFF + + + HP_SLEEP_DIG_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_ICG_HP_APB + need_des + 0x70 + 0x20 + 0xFFFFFFFF + + + HP_SLEEP_DIG_ICG_APB_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_ICG_MODEM + need_des + 0x74 + 0x20 + + + HP_SLEEP_DIG_ICG_MODEM_CODE + need_des + 30 + 2 + read-write + + + + + HP_SLEEP_HP_SYS_CNTL + need_des + 0x78 + 0x20 + + + HP_SLEEP_HP_POWER_DET_BYPASS + need_des + 23 + 1 + read-write + + + HP_SLEEP_UART_WAKEUP_EN + need_des + 24 + 1 + read-write + + + HP_SLEEP_LP_PAD_HOLD_ALL + need_des + 25 + 1 + read-write + + + HP_SLEEP_HP_PAD_HOLD_ALL + need_des + 26 + 1 + read-write + + + HP_SLEEP_DIG_PAD_SLP_SEL + need_des + 27 + 1 + read-write + + + HP_SLEEP_DIG_PAUSE_WDT + need_des + 28 + 1 + read-write + + + HP_SLEEP_DIG_CPU_STALL + need_des + 29 + 1 + read-write + + + + + HP_SLEEP_HP_CK_POWER + need_des + 0x7C + 0x20 + + + HP_SLEEP_I2C_ISO_EN + need_des + 21 + 1 + read-write + + + HP_SLEEP_I2C_RETENTION + need_des + 22 + 1 + read-write + + + HP_SLEEP_XPD_PLL_I2C + need_des + 23 + 4 + read-write + + + HP_SLEEP_XPD_PLL + need_des + 27 + 4 + read-write + + + + + HP_SLEEP_BIAS + need_des + 0x80 + 0x20 + 0x00500000 + + + HP_SLEEP_DCM_VSET + need_des + 18 + 5 + read-write + + + HP_SLEEP_DCM_MODE + need_des + 23 + 2 + read-write + + + HP_SLEEP_XPD_BIAS + need_des + 25 + 1 + read-write + + + HP_SLEEP_DBG_ATTEN + need_des + 26 + 4 + read-write + + + HP_SLEEP_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_BACKUP + need_des + 0x84 + 0x20 + + + HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE + need_des + 6 + 2 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE + need_des + 8 + 2 + read-write + + + HP_SLEEP_RETENTION_MODE + need_des + 10 + 1 + read-write + + + HP_MODEM2SLEEP_RETENTION_EN + need_des + 12 + 1 + read-write + + + HP_ACTIVE2SLEEP_RETENTION_EN + need_des + 13 + 1 + read-write + + + HP_MODEM2SLEEP_BACKUP_CLK_SEL + need_des + 16 + 2 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_CLK_SEL + need_des + 18 + 2 + read-write + + + HP_MODEM2SLEEP_BACKUP_MODE + need_des + 23 + 3 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_MODE + need_des + 26 + 3 + read-write + + + HP_MODEM2SLEEP_BACKUP_EN + need_des + 30 + 1 + read-write + + + HP_ACTIVE2SLEEP_BACKUP_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_BACKUP_CLK + need_des + 0x88 + 0x20 + + + HP_SLEEP_BACKUP_ICG_FUNC_EN + need_des + 0 + 32 + read-write + + + + + HP_SLEEP_SYSCLK + need_des + 0x8C + 0x20 + + + HP_SLEEP_DIG_SYS_CLK_NO_DIV + need_des + 26 + 1 + read-write + + + HP_SLEEP_ICG_SYS_CLOCK_EN + need_des + 27 + 1 + read-write + + + HP_SLEEP_SYS_CLK_SLP_SEL + need_des + 28 + 1 + read-write + + + HP_SLEEP_ICG_SLP_SEL + need_des + 29 + 1 + read-write + + + HP_SLEEP_DIG_SYS_CLK_SEL + need_des + 30 + 2 + read-write + + + + + HP_SLEEP_HP_REGULATOR0 + need_des + 0x90 + 0x20 + 0xC6670000 + + + HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD + need_des + 16 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD + need_des + 17 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_XPD + need_des + 18 + 1 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS + need_des + 19 + 4 + read-write + + + HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS + need_des + 23 + 4 + read-write + + + HP_SLEEP_HP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_SLEEP_HP_REGULATOR1 + need_des + 0x94 + 0x20 + + + HP_SLEEP_HP_REGULATOR_DRV_B + need_des + 26 + 6 + read-write + + + + + HP_SLEEP_XTAL + need_des + 0x98 + 0x20 + 0x80000000 + + + HP_SLEEP_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_LP_REGULATOR0 + need_des + 0x9C + 0x20 + 0xC6600000 + + + HP_SLEEP_LP_REGULATOR_SLP_XPD + need_des + 21 + 1 + read-write + + + HP_SLEEP_LP_REGULATOR_XPD + need_des + 22 + 1 + read-write + + + HP_SLEEP_LP_REGULATOR_SLP_DBIAS + need_des + 23 + 4 + read-write + + + HP_SLEEP_LP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + HP_SLEEP_LP_REGULATOR1 + need_des + 0xA0 + 0x20 + + + HP_SLEEP_LP_REGULATOR_DRV_B + need_des + 26 + 6 + read-write + + + + + HP_SLEEP_LP_DCDC_RESERVE + need_des + 0xA4 + 0x20 + + + PMU_HP_SLEEP_LP_DCDC_RESERVE + need_des + 0 + 32 + write-only + + + + + HP_SLEEP_LP_DIG_POWER + need_des + 0xA8 + 0x20 + + + HP_SLEEP_LP_PAD_SLP_SEL + need_des + 26 + 1 + read-write + + + HP_SLEEP_BOD_SOURCE_SEL + need_des + 27 + 1 + read-write + + + HP_SLEEP_VDDBAT_MODE + need_des + 28 + 2 + read-write + + + HP_SLEEP_LP_MEM_DSLP + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_LP_PERI_PD_EN + need_des + 31 + 1 + read-write + + + + + HP_SLEEP_LP_CK_POWER + need_des + 0xAC + 0x20 + 0x40000000 + + + HP_SLEEP_XPD_LPPLL + need_des + 27 + 1 + read-write + + + HP_SLEEP_XPD_XTAL32K + need_des + 28 + 1 + read-write + + + HP_SLEEP_XPD_RC32K + need_des + 29 + 1 + read-write + + + HP_SLEEP_XPD_FOSC_CLK + need_des + 30 + 1 + read-write + + + HP_SLEEP_PD_OSC_CLK + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_BIAS_RESERVE + need_des + 0xB0 + 0x20 + + + PMU_LP_SLEEP_LP_BIAS_RESERVE + need_des + 0 + 32 + write-only + + + + + LP_SLEEP_LP_REGULATOR0 + need_des + 0xB4 + 0x20 + 0xC6600000 + + + LP_SLEEP_LP_REGULATOR_SLP_XPD + need_des + 21 + 1 + read-write + + + LP_SLEEP_LP_REGULATOR_XPD + need_des + 22 + 1 + read-write + + + LP_SLEEP_LP_REGULATOR_SLP_DBIAS + need_des + 23 + 4 + read-write + + + LP_SLEEP_LP_REGULATOR_DBIAS + need_des + 27 + 5 + read-write + + + + + LP_SLEEP_LP_REGULATOR1 + need_des + 0xB8 + 0x20 + + + LP_SLEEP_LP_REGULATOR_DRV_B + need_des + 26 + 6 + read-write + + + + + LP_SLEEP_XTAL + need_des + 0xBC + 0x20 + 0x80000000 + + + LP_SLEEP_XPD_XTAL + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_DIG_POWER + need_des + 0xC0 + 0x20 + + + LP_SLEEP_LP_PAD_SLP_SEL + need_des + 26 + 1 + read-write + + + LP_SLEEP_BOD_SOURCE_SEL + need_des + 27 + 1 + read-write + + + LP_SLEEP_VDDBAT_MODE + need_des + 28 + 2 + read-write + + + LP_SLEEP_LP_MEM_DSLP + need_des + 30 + 1 + read-write + + + LP_SLEEP_PD_LP_PERI_PD_EN + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_LP_CK_POWER + need_des + 0xC4 + 0x20 + 0x40000000 + + + LP_SLEEP_XPD_LPPLL + need_des + 27 + 1 + read-write + + + LP_SLEEP_XPD_XTAL32K + need_des + 28 + 1 + read-write + + + LP_SLEEP_XPD_RC32K + need_des + 29 + 1 + read-write + + + LP_SLEEP_XPD_FOSC_CLK + need_des + 30 + 1 + read-write + + + LP_SLEEP_PD_OSC_CLK + need_des + 31 + 1 + read-write + + + + + LP_SLEEP_BIAS + need_des + 0xC8 + 0x20 + + + LP_SLEEP_XPD_BIAS + need_des + 25 + 1 + read-write + + + LP_SLEEP_DBG_ATTEN + need_des + 26 + 4 + read-write + + + LP_SLEEP_PD_CUR + need_des + 30 + 1 + read-write + + + SLEEP + need_des + 31 + 1 + read-write + + + + + IMM_HP_CK_POWER + need_des + 0xCC + 0x20 + + + TIE_LOW_CALI_XTAL_ICG + need_des + 0 + 1 + read-write + + + TIE_LOW_GLOBAL_PLL_ICG + need_des + 1 + 4 + write-only + + + TIE_LOW_GLOBAL_XTAL_ICG + need_des + 5 + 1 + write-only + + + TIE_LOW_I2C_RETENTION + need_des + 6 + 1 + write-only + + + TIE_LOW_XPD_PLL_I2C + need_des + 7 + 4 + write-only + + + TIE_LOW_XPD_PLL + need_des + 11 + 4 + write-only + + + TIE_LOW_XPD_XTAL + need_des + 15 + 1 + write-only + + + TIE_HIGH_CALI_XTAL_ICG + need_des + 16 + 1 + read-write + + + TIE_HIGH_GLOBAL_PLL_ICG + need_des + 17 + 4 + write-only + + + TIE_HIGH_GLOBAL_XTAL_ICG + need_des + 21 + 1 + write-only + + + TIE_HIGH_I2C_RETENTION + need_des + 22 + 1 + write-only + + + TIE_HIGH_XPD_PLL_I2C + need_des + 23 + 4 + write-only + + + TIE_HIGH_XPD_PLL + need_des + 27 + 4 + write-only + + + TIE_HIGH_XPD_XTAL + need_des + 31 + 1 + write-only + + + + + IMM_SLEEP_SYSCLK + need_des + 0xD0 + 0x20 + + + UPDATE_DIG_ICG_SWITCH + need_des + 28 + 1 + write-only + + + TIE_LOW_ICG_SLP_SEL + need_des + 29 + 1 + write-only + + + TIE_HIGH_ICG_SLP_SEL + need_des + 30 + 1 + write-only + + + UPDATE_DIG_SYS_CLK_SEL + need_des + 31 + 1 + write-only + + + + + IMM_HP_FUNC_ICG + need_des + 0xD4 + 0x20 + + + UPDATE_DIG_ICG_FUNC_EN + need_des + 31 + 1 + write-only + + + + + IMM_HP_APB_ICG + need_des + 0xD8 + 0x20 + + + UPDATE_DIG_ICG_APB_EN + need_des + 31 + 1 + write-only + + + + + IMM_MODEM_ICG + need_des + 0xDC + 0x20 + + + UPDATE_DIG_ICG_MODEM_EN + need_des + 31 + 1 + write-only + + + + + IMM_LP_ICG + need_des + 0xE0 + 0x20 + + + TIE_LOW_LP_ROOTCLK_SEL + need_des + 30 + 1 + write-only + + + TIE_HIGH_LP_ROOTCLK_SEL + need_des + 31 + 1 + write-only + + + + + IMM_PAD_HOLD_ALL + need_des + 0xE4 + 0x20 + + + PAD_SLP_SEL + need_des + 0 + 1 + read-only + + + LP_PAD_HOLD_ALL + need_des + 1 + 1 + read-only + + + HP_PAD_HOLD_ALL + need_des + 2 + 1 + read-only + + + TIE_HIGH_PAD_SLP_SEL + need_des + 26 + 1 + write-only + + + TIE_LOW_PAD_SLP_SEL + need_des + 27 + 1 + write-only + + + TIE_HIGH_LP_PAD_HOLD_ALL + need_des + 28 + 1 + write-only + + + TIE_LOW_LP_PAD_HOLD_ALL + need_des + 29 + 1 + write-only + + + TIE_HIGH_HP_PAD_HOLD_ALL + need_des + 30 + 1 + write-only + + + TIE_LOW_HP_PAD_HOLD_ALL + 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0x20 + + + EXT_WAKEUP_STATUS_CLR + need_des + 30 + 1 + read-write + + + EXT_WAKEUP_FILTER + need_des + 31 + 1 + read-write + + + + + SDIO_WAKEUP_CNTL + need_des + 0x1F8 + 0x20 + 0x000003FF + + + SDIO_ACT_DNUM + need_des + 0 + 10 + read-write + + + + + XTAL_SLP + need_des + 0x1FC + 0x20 + 0x000F0000 + + + CNT_TARGET + need_des + 16 + 16 + read-write + + + + + CPU_SW_STALL + need_des + 0x200 + 0x20 + + + HPCORE1_SW_STALL_CODE + need_des + 16 + 8 + read-write + + + HPCORE0_SW_STALL_CODE + need_des + 24 + 8 + read-write + + + + + DCM_CTRL + need_des + 0x204 + 0x20 + 0x00010000 + + + DCDC_ON_REQ + SW trigger dcdc on + 0 + 1 + write-only + + + DCDC_OFF_REQ + SW trigger dcdc off + 1 + 1 + write-only + + + DCDC_LIGHTSLP_REQ + SW trigger dcdc enter lightsleep + 2 + 1 + write-only + + + DCDC_DEEPSLP_REQ + SW trigger dcdc enter deepsleep + 3 + 1 + write-only + + + DCDC_DONE_FORCE + need_des + 7 + 1 + read-write + + + DCDC_ON_FORCE_PU + need_des + 8 + 1 + read-write + + + DCDC_ON_FORCE_PD + need_des + 9 + 1 + read-write + + + DCDC_FB_RES_FORCE_PU + need_des + 10 + 1 + read-write + + + DCDC_FB_RES_FORCE_PD + need_des + 11 + 1 + read-write + + + DCDC_LS_FORCE_PU + need_des + 12 + 1 + read-write + + + DCDC_LS_FORCE_PD + need_des + 13 + 1 + read-write + + + DCDC_DS_FORCE_PU + need_des + 14 + 1 + read-write + + + DCDC_DS_FORCE_PD + need_des + 15 + 1 + read-write + + + DCM_CUR_ST + need_des + 16 + 8 + read-only + + + DCDC_EN_AMUX_TEST + Enable analog mux to pull PAD TEST_DCDC voltage signal + 29 + 1 + read-write + + + + + DCM_WAIT_DELAY + need_des + 0x208 + 0x20 + 0x004B0205 + + + DCDC_PRE_DELAY + DCDC pre-on/post off delay + 0 + 8 + read-write + + + DCDC_RES_OFF_DELAY + DCDC fb res off delay + 8 + 8 + read-write + + + DCDC_STABLE_DELAY + DCDC stable delay + 16 + 10 + read-write + + + + + VDDBAT_CFG + need_des + 0x20C + 0x20 + + + ANA_VDDBAT_MODE + need_des + 0 + 2 + read-only + + + VDDBAT_SW_UPDATE + need_des + 31 + 1 + write-only + + + + + TOUCH_PWR_CNTL + need_des + 0x210 + 0x20 + 0x00190140 + + + TOUCH_WAIT_CYCLES + need_des + 5 + 9 + read-write + + + TOUCH_SLEEP_CYCLES + need_des + 14 + 16 + read-write + + + TOUCH_FORCE_DONE + need_des + 30 + 1 + read-write + + + TOUCH_SLEEP_TIMER_EN + need_des + 31 + 1 + read-write + + + + + RDN_ECO + need_des + 0x214 + 0x20 + + + PMU_RDN_ECO_RESULT + need_des + 0 + 1 + read-only + + + PMU_RDN_ECO_EN + need_des + 31 + 1 + read-write + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02303140 + + + PMU_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + PPA + PPA Peripheral + PPA + 0x50087000 + + 0x0 + 0x88 + registers + + + PPA + 96 + + + + BLEND0_CLUT_DATA + CLUT sram data read/write register in background plane of blender + 0x0 + 0x20 + + + RDWR_WORD_BLEND0_CLUT + Write and read data to/from CLUT RAM in background plane of blender engine through this field in fifo mode. + 0 + 32 + read-write + + + + + BLEND1_CLUT_DATA + CLUT sram data read/write register in foreground plane of blender + 0x4 + 0x20 + + + RDWR_WORD_BLEND1_CLUT + Write and read data to/from CLUT RAM in foreground plane of blender engine through this field in fifo mode. + 0 + 32 + read-write + + + + + CLUT_CONF + CLUT configure register + 0xC + 0x20 + + + APB_FIFO_MASK + 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode. + 0 + 1 + read-write + + + BLEND0_CLUT_MEM_RST + Write 1 then write 0 to this bit to reset BLEND0 CLUT. + 1 + 1 + read-write + + + BLEND1_CLUT_MEM_RST + Write 1 then write 0 to this bit to reset BLEND1 CLUT. + 2 + 1 + read-write + + + BLEND0_CLUT_MEM_RDADDR_RST + Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. + 3 + 1 + read-write + + + BLEND1_CLUT_MEM_RDADDR_RST + Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. + 4 + 1 + read-write + + + BLEND0_CLUT_MEM_FORCE_PD + 1: force power down BLEND CLUT memory. + 5 + 1 + read-write + + + BLEND0_CLUT_MEM_FORCE_PU + 1: force power up BLEND CLUT memory. + 6 + 1 + read-write + + + BLEND0_CLUT_MEM_CLK_ENA + 1: Force clock on for BLEND CLUT memory. + 7 + 1 + read-write + + + + + INT_RAW + Raw status interrupt + 0x10 + 0x20 + + + SR_EOF_INT_RAW + The raw interrupt bit turns to high level when scaling and rotating engine calculate one frame image. + 0 + 1 + read-write + + + BLEND_EOF_INT_RAW + The raw interrupt bit turns to high level when blending engine calculate one frame image. + 1 + 1 + read-write + + + SR_PARAM_CFG_ERR_INT_RAW + The raw interrupt bit turns to high level when the configured scaling and rotating coefficient is wrong. User can check the reasons through register PPA_SR_PARAM_ERR_ST_REG. + 2 + 1 + read-write + + + + + INT_ST + Masked interrupt + 0x14 + 0x20 + + + SR_EOF_INT_ST + The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. + 0 + 1 + read-only + + + BLEND_EOF_INT_ST + The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. + 1 + 1 + read-only + + + SR_PARAM_CFG_ERR_INT_ST + The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + 2 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x18 + 0x20 + + + SR_EOF_INT_ENA + The interrupt enable bit for the PPA_SR_EOF_INT interrupt. + 0 + 1 + read-write + + + BLEND_EOF_INT_ENA + The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. + 1 + 1 + read-write + + + SR_PARAM_CFG_ERR_INT_ENA + The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + 2 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x1C + 0x20 + + + SR_EOF_INT_CLR + Set this bit to clear the PPA_SR_EOF_INT interrupt. + 0 + 1 + write-only + + + BLEND_EOF_INT_CLR + Set this bit to clear the PPA_BLEND_EOF_INT interrupt. + 1 + 1 + write-only + + + SR_PARAM_CFG_ERR_INT_CLR + Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + 2 + 1 + write-only + + + + + SR_COLOR_MODE + Scaling and rotating engine color mode register + 0x20 + 0x20 + + + SR_RX_CM + The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. + 0 + 4 + read-write + + + SR_TX_CM + The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved. + 4 + 4 + read-write + + + YUV_RX_RANGE + YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range + 8 + 1 + read-write + + + YUV_TX_RANGE + YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range + 9 + 1 + read-write + + + YUV2RGB_PROTOCAL + YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709 + 10 + 1 + read-write + + + RGB2YUV_PROTOCAL + RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709 + 11 + 1 + read-write + + + + + BLEND_COLOR_MODE + blending engine color mode register + 0x24 + 0x20 + + + BLEND0_RX_CM + The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. + 0 + 4 + read-write + + + BLEND1_RX_CM + The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4. + 4 + 4 + read-write + + + BLEND_TX_CM + The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved.. + 8 + 4 + read-write + + + + + SR_BYTE_ORDER + Scaling and rotating engine byte order register + 0x28 + 0x20 + + + SR_RX_BYTE_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + 0 + 1 + read-write + + + SR_RX_RGB_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + 1 + 1 + read-write + + + SR_MACRO_BK_RO_BYPASS + Set this bit to 1 to bypass the macro block order function. This function is used to improve efficient accessing external memory. + 2 + 1 + read-write + + + + + BLEND_BYTE_ORDER + Blending engine byte order register + 0x2C + 0x20 + + + BLEND0_RX_BYTE_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + 0 + 1 + read-write + + + BLEND1_RX_BYTE_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + 1 + 1 + read-write + + + BLEND0_RX_RGB_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + 2 + 1 + read-write + + + BLEND1_RX_RGB_SWAP_EN + Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + 3 + 1 + read-write + + + + + BLEND_TRANS_MODE + Blending engine mode configure register + 0x34 + 0x20 + + + BLEND_EN + Set this bit to enable alpha blending. + 0 + 1 + read-write + + + BLEND_BYPASS + Set this bit to bypass blender. Then background date would be output. + 1 + 1 + read-write + + + BLEND_FIX_PIXEL_FILL_EN + This bit is used to enable fix pixel filling. When this mode is enable only Tx channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL. + 2 + 1 + read-write + + + UPDATE + Set this bit to update the transfer mode. Only the bit is set the transfer mode is valid. + 3 + 1 + write-only + + + BLEND_RST + write 1 then write 0 to reset blending engine. + 4 + 1 + read-write + + + + + SR_FIX_ALPHA + Scaling and rotating engine alpha override register + 0x38 + 0x20 + 0x00000080 + + + SR_RX_FIX_ALPHA + The value would replace the alpha value in received pixel for Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN is enabled. + 0 + 8 + read-write + + + SR_RX_ALPHA_MOD + Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. + 8 + 2 + read-write + + + SR_RX_ALPHA_INV + Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + 10 + 1 + read-write + + + + + BLEND_TX_SIZE + Fix pixel filling mode image size register + 0x3C + 0x20 + + + BLEND_HB + The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel + 0 + 14 + read-write + + + BLEND_VB + The vertical width of image block that would be filled in fix pixel filling mode. The unit is pixel + 14 + 14 + read-write + + + + + BLEND_FIX_ALPHA + Blending engine alpha override register + 0x40 + 0x20 + 0x00008080 + + + BLEND0_RX_FIX_ALPHA + The value would replace the alpha value in received pixel for background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled. + 0 + 8 + read-write + + + BLEND1_RX_FIX_ALPHA + The value would replace the alpha value in received pixel for foreground plane of blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled. + 8 + 8 + read-write + + + BLEND0_RX_ALPHA_MOD + Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. + 16 + 2 + read-write + + + BLEND1_RX_ALPHA_MOD + Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256. + 18 + 2 + read-write + + + BLEND0_RX_ALPHA_INV + Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + 20 + 1 + read-write + + + BLEND1_RX_ALPHA_INV + Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + 21 + 1 + read-write + + + + + BLEND_RGB + RGB color register + 0x48 + 0x20 + 0x00808080 + + + BLEND1_RX_B + blue color for A4/A8 mode. + 0 + 8 + read-write + + + BLEND1_RX_G + green color for A4/A8 mode. + 8 + 8 + read-write + + + BLEND1_RX_R + red color for A4/A8 mode. + 16 + 8 + read-write + + + + + BLEND_FIX_PIXEL + Blending engine fix pixel register + 0x4C + 0x20 + + + BLEND_TX_FIX_PIXEL + The configure fix pixel in fix pixel filling mode for blender engine. + 0 + 32 + read-write + + + + + CK_FG_LOW + foreground color key lower threshold + 0x50 + 0x20 + 0x00FFFFFF + + + COLORKEY_FG_B_LOW + color key lower threshold of foreground b channel + 0 + 8 + read-write + + + COLORKEY_FG_G_LOW + color key lower threshold of foreground g channel + 8 + 8 + read-write + + + COLORKEY_FG_R_LOW + color key lower threshold of foreground r channel + 16 + 8 + read-write + + + + + CK_FG_HIGH + foreground color key higher threshold + 0x54 + 0x20 + + + COLORKEY_FG_B_HIGH + color key higher threshold of foreground b channel + 0 + 8 + read-write + + + COLORKEY_FG_G_HIGH + color key higher threshold of foreground g channel + 8 + 8 + read-write + + + COLORKEY_FG_R_HIGH + color key higher threshold of foreground r channel + 16 + 8 + read-write + + + + + CK_BG_LOW + background color key lower threshold + 0x58 + 0x20 + 0x00FFFFFF + + + COLORKEY_BG_B_LOW + color key lower threshold of background b channel + 0 + 8 + read-write + + + COLORKEY_BG_G_LOW + color key lower threshold of background g channel + 8 + 8 + read-write + + + COLORKEY_BG_R_LOW + color key lower threshold of background r channel + 16 + 8 + read-write + + + + + CK_BG_HIGH + background color key higher threshold + 0x5C + 0x20 + + + COLORKEY_BG_B_HIGH + color key higher threshold of background b channel + 0 + 8 + read-write + + + COLORKEY_BG_G_HIGH + color key higher threshold of background g channel + 8 + 8 + read-write + + + COLORKEY_BG_R_HIGH + color key higher threshold of background r channel + 16 + 8 + read-write + + + + + CK_DEFAULT + default value when foreground and background both in color key range + 0x60 + 0x20 + + + COLORKEY_DEFAULT_B + default B channle value of color key + 0 + 8 + read-write + + + COLORKEY_DEFAULT_G + default G channle value of color key + 8 + 8 + read-write + + + COLORKEY_DEFAULT_R + default R channle value of color key + 16 + 8 + read-write + + + COLORKEY_FG_BG_REVERSE + when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the result is fg + 24 + 1 + read-write + + + + + SR_SCAL_ROTATE + Scaling and rotating coefficient register + 0x64 + 0x20 + 0x00001001 + + + SR_SCAL_X_INT + The integrated part of scaling coefficient in X direction. + 0 + 8 + read-write + + + SR_SCAL_X_FRAG + The fragment part of scaling coefficient in X direction. + 8 + 4 + read-write + + + SR_SCAL_Y_INT + The integrated part of scaling coefficient in Y direction. + 12 + 8 + read-write + + + SR_SCAL_Y_FRAG + The fragment part of scaling coefficient in Y direction. + 20 + 4 + read-write + + + SR_ROTATE_ANGLE + The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree. + 24 + 2 + read-write + + + SCAL_ROTATE_RST + Write 1 then write 0 to this bit to reset scaling and rotating engine. + 26 + 1 + read-write + + + SCAL_ROTATE_START + Write 1 to enable scaling and rotating engine after parameter is configured. + 27 + 1 + write-only + + + SR_MIRROR_X + Image mirror in X direction. 0: disable, 1: enable + 28 + 1 + read-write + + + SR_MIRROR_Y + Image mirror in Y direction. 0: disable, 1: enable + 29 + 1 + read-write + + + + + SR_MEM_PD + SR memory power done register + 0x68 + 0x20 + + + SR_MEM_CLK_ENA + Set this bit to force clock enable of scaling and rotating engine's data memory. + 0 + 1 + read-write + + + SR_MEM_FORCE_PD + Set this bit to force power down scaling and rotating engine's data memory. + 1 + 1 + read-write + + + SR_MEM_FORCE_PU + Set this bit to force power up scaling and rotating engine's data memory. + 2 + 1 + read-write + + + + + REG_CONF + Register clock enable register + 0x6C + 0x20 + + + CLK_EN + PPA register clock gate enable signal. + 0 + 1 + read-write + + + + + CLUT_CNT + BLEND CLUT write counter register + 0x70 + 0x20 + + + BLEND0_CLUT_CNT + The write data counter of BLEND0 CLUT in fifo mode. + 0 + 9 + read-only + + + BLEND1_CLUT_CNT + The write data counter of BLEND1 CLUT in fifo mode. + 9 + 9 + read-only + + + + + BLEND_ST + Blending engine status register + 0x74 + 0x20 + + + BLEND_SIZE_DIFF_ST + 1: indicate the size of two image is different. + 0 + 1 + read-only + + + + + SR_PARAM_ERR_ST + Scaling and rotating coefficient error register + 0x78 + 0x20 + + + TX_DSCR_VB_ERR_ST + The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive descriptor is larger than VA in 2DDMA receive descriptor. + 0 + 1 + read-only + + + TX_DSCR_HB_ERR_ST + The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive descriptor is larger than HA in 2DDMA receive descriptor. + 1 + 1 + read-only + + + Y_RX_SCAL_EQUAL_0_ERR_ST + The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0. + 2 + 1 + read-only + + + RX_DSCR_VB_ERR_ST + The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor + 3 + 1 + read-only + + + YDST_LEN_TOO_SAMLL_ERR_ST + The error is that the scaled image width is 0. For example. when source width is 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as the result would be floored. + 4 + 1 + read-only + + + YDST_LEN_TOO_LARGE_ERR_ST + The error is that the scaled width is larger than (2^13 - 1). + 5 + 1 + read-only + + + X_RX_SCAL_EQUAL_0_ERR_ST + The error is that the scaled image height is 0. + 6 + 1 + read-only + + + RX_DSCR_HB_ERR_ST + The error is that the HB in 2DDMA transmit descriptor plus the offset of X coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit descriptor. + 7 + 1 + read-only + + + XDST_LEN_TOO_SAMLL_ERR_ST + The error is that the scaled image height is 0. For example. when source height is 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as the result would be floored. + 8 + 1 + read-only + + + XDST_LEN_TOO_LARGE_ERR_ST + The error is that the scaled image height is larger than (2^13 - 1). + 9 + 1 + read-only + + + X_YUV420_RX_SCALE_ERR_ST + The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 rx + 10 + 1 + read-only + + + Y_YUV420_RX_SCALE_ERR_ST + The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 rx + 11 + 1 + read-only + + + X_YUV420_TX_SCALE_ERR_ST + The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 tx + 12 + 1 + read-only + + + Y_YUV420_TX_SCALE_ERR_ST + The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 tx + 13 + 1 + read-only + + + + + SR_STATUS + SR FSM register + 0x7C + 0x20 + + + SR_RX_DSCR_SAMPLE_STATE + Reserved. + 0 + 2 + read-only + + + SR_RX_SCAN_STATE + Reserved. + 2 + 2 + read-only + + + SR_TX_DSCR_SAMPLE_STATE + Reserved. + 4 + 2 + read-only + + + SR_TX_SCAN_STATE + Reserved. + 6 + 3 + read-only + + + + + ECO_LOW + Reserved. + 0x80 + 0x20 + + + RND_ECO_LOW + Reserved. + 0 + 32 + read-write + + + + + ECO_HIGH + Reserved. + 0x84 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + Reserved. + 0 + 32 + read-write + + + + + ECO_CELL_CTRL + Reserved. + 0x88 + 0x20 + + + RDN_RESULT + Reserved. + 0 + 1 + read-only + + + RDN_ENA + Reserved. + 1 + 1 + read-write + + + + + SRAM_CTRL + PPA SRAM Control Register + 0x8C + 0x20 + 0x00001320 + + + MEM_AUX_CTRL + Control signals + 0 + 14 + read-write + + + + + DATE + PPA Version register + 0x100 + 0x20 + 0x02304041 + + + DATE + register version. + 0 + 32 + read-write + + + + + + + PVT + PVT Peripheral + PVT + 0x5009E000 + + 0x0 + 0x1F0 + registers + + + + PMUP_BITMAP_HIGH0 + select valid pvt channel + 0x0 + 0x20 + + + PUMP_BITMAP_HIGH0 + select valid high channel0 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH1 + select valid pvt channel + 0x4 + 0x20 + + + PUMP_BITMAP_HIGH1 + select valid high channel1 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH2 + select valid pvt channel + 0x8 + 0x20 + + + PUMP_BITMAP_HIGH2 + select valid high channel2 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH3 + select valid pvt channel + 0xC + 0x20 + + + PUMP_BITMAP_HIGH3 + select valid high channel3 + 0 + 32 + read-write + + + + + PMUP_BITMAP_HIGH4 + select valid pvt channel + 0x10 + 0x20 + + + PUMP_BITMAP_HIGH4 + select valid high channel4 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW0 + select valid pvt channel + 0x14 + 0x20 + + + PUMP_BITMAP_LOW0 + select valid low channel0 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW1 + select valid pvt channel + 0x18 + 0x20 + + + PUMP_BITMAP_LOW1 + select valid low channel1 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW2 + select valid pvt channel + 0x1C + 0x20 + + + PUMP_BITMAP_LOW2 + select valid low channel2 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW3 + select valid pvt channel + 0x20 + 0x20 + + + PUMP_BITMAP_LOW3 + select valid low channel3 + 0 + 32 + read-write + + + + + PMUP_BITMAP_LOW4 + select valid pvt channel + 0x24 + 0x20 + + + PUMP_BITMAP_LOW4 + select valid low channel4 + 0 + 32 + read-write + + + + + PMUP_DRV_CFG + configure pump drv + 0x28 + 0x20 + + + PUMP_EN + configure pvt charge xpd + 9 + 1 + read-write + + + CLK_EN + force register clken + 10 + 1 + read-write + + + PUMP_DRV4 + configure cmd4 drv + 11 + 4 + read-write + + + PUMP_DRV3 + configure cmd3 drv + 15 + 4 + read-write + + + PUMP_DRV2 + configure cmd2 drv + 19 + 4 + read-write + + + PUMP_DRV1 + configure cmd1 drv + 23 + 4 + read-write + + + PUMP_DRV0 + configure cmd0 drv + 27 + 4 + read-write + + + + + PMUP_CHANNEL_CFG + configure the code of valid pump channel code + 0x2C + 0x20 + + + PUMP_CHANNEL_CODE4 + configure cmd4 code + 7 + 5 + read-write + + + PUMP_CHANNEL_CODE3 + configure cmd3 code + 12 + 5 + read-write + + + PUMP_CHANNEL_CODE2 + configure cmd2 code + 17 + 5 + read-write + + + PUMP_CHANNEL_CODE1 + configure cmd1 code + 22 + 5 + read-write + + + PUMP_CHANNEL_CODE0 + configure cmd0 code + 27 + 5 + read-write + + + + + CLK_CFG + configure pvt clk + 0x30 + 0x20 + + + PUMP_CLK_DIV_NUM + needs field desc + 0 + 8 + read-write + + + MONITOR_CLK_PVT_EN + needs field desc + 8 + 1 + read-write + + + CLK_SEL + select pvt clk + 31 + 1 + read-write + + + + + DBIAS_CHANNEL_SEL0 + needs desc + 0x34 + 0x20 + 0x81020400 + + + DBIAS_CHANNEL3_SEL + needs field desc + 4 + 7 + read-write + + + DBIAS_CHANNEL2_SEL + needs field desc + 11 + 7 + read-write + + + DBIAS_CHANNEL1_SEL + needs field desc + 18 + 7 + read-write + + + DBIAS_CHANNEL0_SEL + needs field desc + 25 + 7 + read-write + + + + + DBIAS_CHANNEL_SEL1 + needs desc + 0x38 + 0x20 + 0x80000000 + + + DBIAS_CHANNEL4_SEL + needs field desc + 25 + 7 + read-write + + + + + DBIAS_CHANNEL0_SEL + needs desc + 0x3C + 0x20 + + + DBIAS_CHANNEL0_CFG + needs field desc + 0 + 17 + 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read-write + + + DELAY_OVF_VT1_PD_SITE2_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT2_VT1_CONF2 + needs desc + 0x1A0 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE2_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT3_VT1_CONF2 + needs desc + 0x1A4 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE2_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT0_VT2_CONF2 + needs desc + 0x1A8 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE2_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT1_VT2_CONF2 + needs desc + 0x1AC + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE2_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT2_VT2_CONF2 + needs desc + 0x1B0 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE2_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE2_UNIT3_VT2_CONF2 + needs desc + 0x1B4 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE2_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT0_VT0_CONF2 + needs desc + 0x1B8 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE3_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT1_VT0_CONF2 + needs desc + 0x1BC + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE3_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT2_VT0_CONF2 + needs desc + 0x1C0 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE3_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT3_VT0_CONF2 + needs desc + 0x1C4 + 0x20 + + + MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT0_PD_SITE3_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT0_VT1_CONF2 + needs desc + 0x1C8 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE3_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT1_VT1_CONF2 + needs desc + 0x1CC + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE3_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT2_VT1_CONF2 + needs desc + 0x1D0 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE3_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT3_VT1_CONF2 + needs desc + 0x1D4 + 0x20 + + + MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT1_PD_SITE3_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT0_VT2_CONF2 + needs desc + 0x1D8 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE3_UNIT0 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT1_VT2_CONF2 + needs desc + 0x1DC + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE3_UNIT1 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT2_VT2_CONF2 + needs desc + 0x1E0 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE3_UNIT2 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 + needs field desc + 16 + 16 + read-only + + + + + COMB_PD_SITE3_UNIT3_VT2_CONF2 + needs desc + 0x1E4 + 0x20 + + + MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 + needs field desc + 0 + 2 + read-write + + + DELAY_OVF_VT2_PD_SITE3_UNIT3 + needs field desc + 15 + 1 + read-only + + + TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 + needs field desc + 16 + 16 + read-only + + + + + VALUE_UPDATE + needs field desc + 0x1E8 + 0x20 + + + VALUE_UPDATE + needs field desc + 0 + 1 + write-only + + + BYPASS + needs field desc + 1 + 1 + read-write + + + + + DATE + version register + 0xFFC + 0x20 + 0x02112130 + + + DATE + version register + 0 + 32 + read-write + + + + + + + RMT + Remote Control + RMT + 0x500D4000 + + 0x0 + 0xD0 + registers + + + RMT + 43 + + + + 4 + 0x4 + TX_CH%sDATA + The read and write data register for CHANNEL%s by apb fifo access. + 0x0 + 0x20 + + + CHDATA + Read and write data for channel %s via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + RX_CH%sDATA + The read and write data register for CHANNEL$n by apb fifo access. + 0x10 + 0x20 + + + CHDATA + Read and write data for channel 0 via APB FIFO. + 0 + 32 + read-only + + + + + 4 + 0x4 + TX_CH%sCONF0 + Channel %s configure register 0 + 0x20 + 0x20 + 0x00710200 + + + TX_START_CH0 + Set this bit to start sending data on CHANNEL%s. + 0 + 1 + write-only + + + MEM_RD_RST_CH0 + Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + 1 + 1 + write-only + + + APB_MEM_RST_CH0 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + TX_CONTI_MODE_CH0 + Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + 3 + 1 + read-write + + + MEM_TX_WRAP_EN_CH0 + This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. + 4 + 1 + read-write + + + IDLE_OUT_LV_CH0 + This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + 5 + 1 + read-write + + + IDLE_OUT_EN_CH0 + This is the output enable-control bit for CHANNEL%s in IDLE state. + 6 + 1 + read-write + + + TX_STOP_CH0 + Set this bit to stop the transmitter of CHANNEL%s sending data out. + 7 + 1 + read-write + + + DIV_CNT_CH0 + This register is used to configure the divider for clock of CHANNEL%s. + 8 + 8 + read-write + + + MEM_SIZE_CH0 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 16 + 4 + read-write + + + CARRIER_EFF_EN_CH0 + 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. + 20 + 1 + read-write + + + CARRIER_EN_CH0 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 21 + 1 + read-write + + + CARRIER_OUT_LV_CH0 + This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level. + 22 + 1 + read-write + + + AFIFO_RST_CH0 + Reserved + 23 + 1 + write-only + + + CONF_UPDATE_CH0 + synchronization bit for CHANNEL%s + 24 + 1 + write-only + + + + + 4 + 0x8 + RX_CH%sCONF0 + Channel %s configure register 0 + 0x30 + 0x20 + 0x317FFF02 + + + DIV_CNT_CH4 + This register is used to configure the divider for clock of CHANNEL%s. + 0 + 8 + read-write + + + IDLE_THRES_CH4 + When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. + 8 + 15 + read-write + + + MEM_SIZE_CH4 + This register is used to configure the maximum size of memory allocated to CHANNEL%s. + 24 + 4 + read-write + + + CARRIER_EN_CH4 + This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. + 28 + 1 + read-write + + + CARRIER_OUT_LV_CH4 + This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level. + 29 + 1 + read-write + + + + + 4 + 0x8 + RX_CH%sCONF1 + Channel %s configure register 1 + 0x34 + 0x20 + 0x000001E8 + + + RX_EN_CH4 + Set this bit to enable receiver to receive data on CHANNEL%s. + 0 + 1 + read-write + + + MEM_WR_RST_CH4 + Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + 1 + 1 + write-only + + + APB_MEM_RST_CH4 + Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + 2 + 1 + write-only + + + MEM_OWNER_CH4 + This register marks the ownership of CHANNEL%s's ram block.1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram. + 3 + 1 + read-write + + + RX_FILTER_EN_CH4 + This is the receive filter's enable bit for CHANNEL%s. + 4 + 1 + read-write + + + RX_FILTER_THRES_CH4 + Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + 5 + 8 + read-write + + + MEM_RX_WRAP_EN_CH4 + This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. + 13 + 1 + read-write + + + AFIFO_RST_CH4 + Reserved + 14 + 1 + write-only + + + CONF_UPDATE_CH4 + synchronization bit for CHANNEL%s + 15 + 1 + write-only + + + + + 4 + 0x4 + TX_CH%sSTATUS + Channel %s status register + 0x50 + 0x20 + + + MEM_RADDR_EX_CH0 + This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_WADDR_CH0 + This register records the memory address offset when writes RAM over APB bus. + 11 + 10 + read-only + + + STATE_CH0 + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_EMPTY_CH0 + This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + 25 + 1 + read-only + + + APB_MEM_WR_ERR_CH0 + This status bit will be set if the offset address out of memory size when writes via APB bus. + 26 + 1 + read-only + + + + + 4 + 0x4 + RX_CH%sSTATUS + Channel %s status register + 0x60 + 0x20 + 0x000600C0 + + + MEM_WADDR_EX_CH4 + This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + 0 + 10 + read-only + + + APB_MEM_RADDR_CH4 + This register records the memory address offset when reads RAM over APB bus. + 11 + 10 + read-only + + + STATE_CH4 + This register records the FSM status of CHANNEL%s. + 22 + 3 + read-only + + + MEM_OWNER_ERR_CH4 + This status bit will be set when the ownership of memory block is wrong. + 25 + 1 + read-only + + + MEM_FULL_CH4 + This status bit will be set if the receiver receives more data than the memory size. + 26 + 1 + read-only + + + APB_MEM_RD_ERR_CH4 + This status bit will be set if the offset address out of memory size when reads via APB bus. + 27 + 1 + read-only + + + + + INT_RAW + Raw interrupt status + 0x70 + 0x20 + + + CH0_TX_END_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmission done. + 0 + 1 + read-write + + + CH1_TX_END_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmission done. + 1 + 1 + read-write + + + CH2_TX_END_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when transmission done. + 2 + 1 + read-write + + + CH3_TX_END_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when transmission done. + 3 + 1 + read-write + + + TX_CH0_ERR_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when error occurs. + 4 + 1 + read-write + + + TX_CH1_ERR_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when error occurs. + 5 + 1 + read-write + + + TX_CH2_ERR_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when error occurs. + 6 + 1 + read-write + + + TX_CH3_ERR_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when error occurs. + 7 + 1 + read-write + + + CH0_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value. + 8 + 1 + read-write + + + CH1_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value. + 9 + 1 + read-write + + + CH2_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value. + 10 + 1 + read-write + + + CH3_TX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value. + 11 + 1 + read-write + + + CH0_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value. + 12 + 1 + read-write + + + CH1_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value. + 13 + 1 + read-write + + + CH2_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value. + 14 + 1 + read-write + + + CH3_TX_LOOP_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value. + 15 + 1 + read-write + + + CH4_RX_END_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when reception done. + 16 + 1 + read-write + + + CH5_RX_END_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when reception done. + 17 + 1 + read-write + + + CH6_RX_END_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when reception done. + 18 + 1 + read-write + + + CH7_RX_END_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when reception done. + 19 + 1 + read-write + + + RX_CH4_ERR_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when error occurs. + 20 + 1 + read-write + + + RX_CH5_ERR_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when error occurs. + 21 + 1 + read-write + + + RX_CH6_ERR_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when error occurs. + 22 + 1 + read-write + + + RX_CH7_ERR_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when error occurs. + 23 + 1 + read-write + + + CH4_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value. + 24 + 1 + read-write + + + CH5_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value. + 25 + 1 + read-write + + + CH6_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value. + 26 + 1 + read-write + + + CH7_RX_THR_EVENT_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value. + 27 + 1 + read-write + + + TX_CH3_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + 28 + 1 + read-write + + + RX_CH7_DMA_ACCESS_FAIL_INT_RAW + The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + 29 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x74 + 0x20 + + + CH0_TX_END_INT_ST + The masked interrupt status bit for CH0_TX_END_INT. + 0 + 1 + read-only + + + CH1_TX_END_INT_ST + The masked interrupt status bit for CH1_TX_END_INT. + 1 + 1 + read-only + + + CH2_TX_END_INT_ST + The masked interrupt status bit for CH2_TX_END_INT. + 2 + 1 + read-only + + + CH3_TX_END_INT_ST + The masked interrupt status bit for CH3_TX_END_INT. + 3 + 1 + read-only + + + TX_CH0_ERR_INT_ST + The masked interrupt status bit for CH0_ERR_INT. + 4 + 1 + read-only + + + TX_CH1_ERR_INT_ST + The masked interrupt status bit for CH1_ERR_INT. + 5 + 1 + read-only + + + TX_CH2_ERR_INT_ST + The masked interrupt status bit for CH2_ERR_INT. + 6 + 1 + read-only + + + TX_CH3_ERR_INT_ST + The masked interrupt status bit for CH3_ERR_INT. + 7 + 1 + read-only + + + CH0_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-only + + + CH1_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-only + + + CH2_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH2_TX_THR_EVENT_INT. + 10 + 1 + read-only + + + CH3_TX_THR_EVENT_INT_ST + The masked interrupt status bit for CH3_TX_THR_EVENT_INT. + 11 + 1 + read-only + + + CH0_TX_LOOP_INT_ST + The masked interrupt status bit for CH0_TX_LOOP_INT. + 12 + 1 + read-only + + + CH1_TX_LOOP_INT_ST + The masked interrupt status bit for CH1_TX_LOOP_INT. + 13 + 1 + read-only + + + CH2_TX_LOOP_INT_ST + The masked interrupt status bit for CH2_TX_LOOP_INT. + 14 + 1 + read-only + + + CH3_TX_LOOP_INT_ST + The masked interrupt status bit for CH3_TX_LOOP_INT. + 15 + 1 + read-only + + + CH4_RX_END_INT_ST + The masked interrupt status bit for CH4_RX_END_INT. + 16 + 1 + read-only + + + CH5_RX_END_INT_ST + The masked interrupt status bit for CH5_RX_END_INT. + 17 + 1 + read-only + + + CH6_RX_END_INT_ST + The masked interrupt status bit for CH6_RX_END_INT. + 18 + 1 + read-only + + + CH7_RX_END_INT_ST + The masked interrupt status bit for CH7_RX_END_INT. + 19 + 1 + read-only + + + RX_CH4_ERR_INT_ST + The masked interrupt status bit for CH4_ERR_INT. + 20 + 1 + read-only + + + RX_CH5_ERR_INT_ST + The masked interrupt status bit for CH5_ERR_INT. + 21 + 1 + read-only + + + RX_CH6_ERR_INT_ST + The masked interrupt status bit for CH6_ERR_INT. + 22 + 1 + read-only + + + RX_CH7_ERR_INT_ST + The masked interrupt status bit for CH7_ERR_INT. + 23 + 1 + read-only + + + CH4_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-only + + + CH5_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-only + + + CH6_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-only + + + CH7_RX_THR_EVENT_INT_ST + The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_ST + The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0x78 + 0x20 + + + CH0_TX_END_INT_ENA + The interrupt enable bit for CH0_TX_END_INT. + 0 + 1 + read-write + + + CH1_TX_END_INT_ENA + The interrupt enable bit for CH1_TX_END_INT. + 1 + 1 + read-write + + + CH2_TX_END_INT_ENA + The interrupt enable bit for CH2_TX_END_INT. + 2 + 1 + read-write + + + CH3_TX_END_INT_ENA + The interrupt enable bit for CH3_TX_END_INT. + 3 + 1 + read-write + + + TX_CH0_ERR_INT_ENA + The interrupt enable bit for CH0_ERR_INT. + 4 + 1 + read-write + + + TX_CH1_ERR_INT_ENA + The interrupt enable bit for CH1_ERR_INT. + 5 + 1 + read-write + + + TX_CH2_ERR_INT_ENA + The interrupt enable bit for CH2_ERR_INT. + 6 + 1 + read-write + + + TX_CH3_ERR_INT_ENA + The interrupt enable bit for CH3_ERR_INT. + 7 + 1 + read-write + + + CH0_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH0_TX_THR_EVENT_INT. + 8 + 1 + read-write + + + CH1_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH1_TX_THR_EVENT_INT. + 9 + 1 + read-write + + + CH2_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH2_TX_THR_EVENT_INT. + 10 + 1 + read-write + + + CH3_TX_THR_EVENT_INT_ENA + The interrupt enable bit for CH3_TX_THR_EVENT_INT. + 11 + 1 + read-write + + + CH0_TX_LOOP_INT_ENA + The interrupt enable bit for CH0_TX_LOOP_INT. + 12 + 1 + read-write + + + CH1_TX_LOOP_INT_ENA + The interrupt enable bit for CH1_TX_LOOP_INT. + 13 + 1 + read-write + + + CH2_TX_LOOP_INT_ENA + The interrupt enable bit for CH2_TX_LOOP_INT. + 14 + 1 + read-write + + + CH3_TX_LOOP_INT_ENA + The interrupt enable bit for CH3_TX_LOOP_INT. + 15 + 1 + read-write + + + CH4_RX_END_INT_ENA + The interrupt enable bit for CH4_RX_END_INT. + 16 + 1 + read-write + + + CH5_RX_END_INT_ENA + The interrupt enable bit for CH5_RX_END_INT. + 17 + 1 + read-write + + + CH6_RX_END_INT_ENA + The interrupt enable bit for CH6_RX_END_INT. + 18 + 1 + read-write + + + CH7_RX_END_INT_ENA + The interrupt enable bit for CH7_RX_END_INT. + 19 + 1 + read-write + + + CH4_ERR_INT_ENA + The interrupt enable bit for CH4_ERR_INT. + 20 + 1 + read-write + + + CH5_ERR_INT_ENA + The interrupt enable bit for CH5_ERR_INT. + 21 + 1 + read-write + + + CH6_ERR_INT_ENA + The interrupt enable bit for CH6_ERR_INT. + 22 + 1 + read-write + + + CH7_ERR_INT_ENA + The interrupt enable bit for CH7_ERR_INT. + 23 + 1 + read-write + + + CH4_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH4_RX_THR_EVENT_INT. + 24 + 1 + read-write + + + CH5_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH5_RX_THR_EVENT_INT. + 25 + 1 + read-write + + + CH6_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH6_RX_THR_EVENT_INT. + 26 + 1 + read-write + + + CH7_RX_THR_EVENT_INT_ENA + The interrupt enable bit for CH7_RX_THR_EVENT_INT. + 27 + 1 + read-write + + + TX_CH3_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + 28 + 1 + read-write + + + RX_CH7_DMA_ACCESS_FAIL_INT_ENA + The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + 29 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x7C + 0x20 + + + CH0_TX_END_INT_CLR + Set this bit to clear theCH0_TX_END_INT interrupt. + 0 + 1 + write-only + + + CH1_TX_END_INT_CLR + Set this bit to clear theCH1_TX_END_INT interrupt. + 1 + 1 + write-only + + + CH2_TX_END_INT_CLR + Set this bit to clear theCH2_TX_END_INT interrupt. + 2 + 1 + write-only + + + CH3_TX_END_INT_CLR + Set this bit to clear theCH3_TX_END_INT interrupt. + 3 + 1 + write-only + + + TX_CH0_ERR_INT_CLR + Set this bit to clear theCH0_ERR_INT interrupt. + 4 + 1 + write-only + + + TX_CH1_ERR_INT_CLR + Set this bit to clear theCH1_ERR_INT interrupt. + 5 + 1 + write-only + + + TX_CH2_ERR_INT_CLR + Set this bit to clear theCH2_ERR_INT interrupt. + 6 + 1 + write-only + + + TX_CH3_ERR_INT_CLR + Set this bit to clear theCH3_ERR_INT interrupt. + 7 + 1 + write-only + + + CH0_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + 8 + 1 + write-only + + + CH1_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + 9 + 1 + write-only + + + CH2_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. + 10 + 1 + write-only + + + CH3_TX_THR_EVENT_INT_CLR + Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. + 11 + 1 + write-only + + + CH0_TX_LOOP_INT_CLR + Set this bit to clear theCH0_TX_LOOP_INT interrupt. + 12 + 1 + write-only + + + CH1_TX_LOOP_INT_CLR + Set this bit to clear theCH1_TX_LOOP_INT interrupt. + 13 + 1 + write-only + + + CH2_TX_LOOP_INT_CLR + Set this bit to clear theCH2_TX_LOOP_INT interrupt. + 14 + 1 + write-only + + + CH3_TX_LOOP_INT_CLR + Set this bit to clear theCH3_TX_LOOP_INT interrupt. + 15 + 1 + write-only + + + CH4_RX_END_INT_CLR + Set this bit to clear theCH4_RX_END_INT interrupt. + 16 + 1 + write-only + + + CH5_RX_END_INT_CLR + Set this bit to clear theCH5_RX_END_INT interrupt. + 17 + 1 + write-only + + + CH6_RX_END_INT_CLR + Set this bit to clear theCH6_RX_END_INT interrupt. + 18 + 1 + write-only + + + CH7_RX_END_INT_CLR + Set this bit to clear theCH7_RX_END_INT interrupt. + 19 + 1 + write-only + + + RX_CH4_ERR_INT_CLR + Set this bit to clear theCH4_ERR_INT interrupt. + 20 + 1 + write-only + + + RX_CH5_ERR_INT_CLR + Set this bit to clear theCH5_ERR_INT interrupt. + 21 + 1 + write-only + + + RX_CH6_ERR_INT_CLR + Set this bit to clear theCH6_ERR_INT interrupt. + 22 + 1 + write-only + + + RX_CH7_ERR_INT_CLR + Set this bit to clear theCH7_ERR_INT interrupt. + 23 + 1 + write-only + + + CH4_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + 24 + 1 + write-only + + + CH5_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + 25 + 1 + write-only + + + CH6_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + 26 + 1 + write-only + + + CH7_RX_THR_EVENT_INT_CLR + Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + 27 + 1 + write-only + + + TX_CH3_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + 28 + 1 + write-only + + + RX_CH7_DMA_ACCESS_FAIL_INT_CLR + Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + 29 + 1 + write-only + + + + + 4 + 0x4 + CH%sCARRIER_DUTY + Channel %s duty cycle configuration register + 0x80 + 0x20 + 0x00400040 + + + CARRIER_LOW_CH + This register is used to configure carrier wave 's low level clock period for CHANNEL%s. + 0 + 16 + read-write + + + CARRIER_HIGH_CH + This register is used to configure carrier wave 's high level clock period for CHANNEL%s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_RX_CARRIER_RM + Channel %s carrier remove register + 0x90 + 0x20 + + + CARRIER_LOW_THRES_CH + The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + 0 + 16 + read-write + + + CARRIER_HIGH_THRES_CH + The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + 16 + 16 + read-write + + + + + 4 + 0x4 + CH%s_TX_LIM + Channel %s Tx event configuration register + 0xA0 + 0x20 + 0x00000080 + + + TX_LIM_CH + This register is used to configure the maximum entries that CHANNEL%s can send out. + 0 + 9 + read-write + + + TX_LOOP_NUM_CH + This register is used to configure the maximum loop count when tx_conti_mode is valid. + 9 + 10 + read-write + + + TX_LOOP_CNT_EN_CH + This register is the enabled bit for loop count. + 19 + 1 + read-write + + + LOOP_COUNT_RESET_CH + This register is used to reset the loop count when tx_conti_mode is valid. + 20 + 1 + write-only + + + LOOP_STOP_EN_CH + This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + 21 + 1 + read-write + + + + + 4 + 0x4 + CH%s_RX_LIM + Channel %s Rx event configuration register + 0xB0 + 0x20 + 0x00000080 + + + RX_LIM_CH4 + This register is used to configure the maximum entries that CHANNEL%s can receive. + 0 + 9 + read-write + + + + + SYS_CONF + RMT apb configuration register + 0xC0 + 0x20 + 0x05000010 + + + APB_FIFO_MASK + 1'h1: access memory directly. 1'h0: access memory by FIFO. + 0 + 1 + read-write + + + MEM_CLK_FORCE_ON + Set this bit to enable the clock for RMT memory. + 1 + 1 + read-write + + + MEM_FORCE_PD + Set this bit to power down RMT memory. + 2 + 1 + read-write + + + MEM_FORCE_PU + 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. + 3 + 1 + read-write + + + SCLK_DIV_NUM + the integral part of the fractional divisor + 4 + 8 + read-write + + + SCLK_DIV_A + the numerator of the fractional part of the fractional divisor + 12 + 6 + read-write + + + SCLK_DIV_B + the denominator of the fractional part of the fractional divisor + 18 + 6 + read-write + + + SCLK_SEL + choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL + 24 + 2 + read-write + + + SCLK_ACTIVE + rmt_sclk switch + 26 + 1 + read-write + + + CLK_EN + RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers + 31 + 1 + read-write + + + + + TX_SIM + RMT TX synchronous register + 0xC4 + 0x20 + + + CH0 + Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + 0 + 1 + read-write + + + CH1 + Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + 1 + 1 + read-write + + + CH2 + Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. + 2 + 1 + read-write + + + CH3 + Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. + 3 + 1 + read-write + + + EN + This register is used to enable multiple of channels to start sending data synchronously. + 4 + 1 + read-write + + + + + REF_CNT_RST + RMT clock divider reset register + 0xC8 + 0x20 + + + TX_REF_CNT_RST_CH0 + This register is used to reset the clock divider of CHANNEL0. + 0 + 1 + write-only + + + TX_REF_CNT_RST_CH1 + This register is used to reset the clock divider of CHANNEL1. + 1 + 1 + write-only + + + TX_REF_CNT_RST_CH2 + This register is used to reset the clock divider of CHANNEL2. + 2 + 1 + write-only + + + TX_REF_CNT_RST_CH3 + This register is used to reset the clock divider of CHANNEL3. + 3 + 1 + write-only + + + RX_REF_CNT_RST_CH4 + This register is used to reset the clock divider of CHANNEL4. + 4 + 1 + write-only + + + RX_REF_CNT_RST_CH5 + This register is used to reset the clock divider of CHANNEL5. + 5 + 1 + write-only + + + RX_REF_CNT_RST_CH6 + This register is used to reset the clock divider of CHANNEL6. + 6 + 1 + write-only + + + RX_REF_CNT_RST_CH7 + This register is used to reset the clock divider of CHANNEL7. + 7 + 1 + write-only + + + + + DATE + RMT version register + 0xCC + 0x20 + 0x02201111 + + + DATE + This is the version register. + 0 + 28 + read-write + + + + + + + RSA + RSA (Rivest Shamir Adleman) Accelerator + RSA + 0x50092000 + + 0x0 + 0x74 + registers + + + RSA + 68 + + + + 16 + 0x1 + M_MEM[%s] + Represents M + 0x0 + 0x8 + + + 16 + 0x1 + Z_MEM[%s] + Represents Z + 0x200 + 0x8 + + + 16 + 0x1 + Y_MEM[%s] + Represents Y + 0x400 + 0x8 + + + 16 + 0x1 + X_MEM[%s] + Represents X + 0x600 + 0x8 + + + M_PRIME + Represents M’ + 0x800 + 0x20 + + + M_PRIME + Represents M’ + 0 + 32 + read-write + + + + + MODE + Configures RSA length + 0x804 + 0x20 + + + MODE + Configures the RSA length. + 0 + 7 + read-write + + + + + QUERY_CLEAN + RSA clean register + 0x808 + 0x20 + + + QUERY_CLEAN + Represents whether or not the RSA memory completes initialization. + +0: Not complete + +1: Completed + 0 + 1 + read-only + + + + + SET_START_MODEXP + Starts modular exponentiation + 0x80C + 0x20 + + + SET_START_MODEXP + Configure whether or not to start the modular exponentiation. + +0: No effect + +1: Start + 0 + 1 + write-only + + + + + SET_START_MODMULT + Starts modular multiplication + 0x810 + 0x20 + + + SET_START_MODMULT + Configure whether or not to start the modular multiplication. + +0: No effect + +1: Start + 0 + 1 + write-only + + + + + SET_START_MULT + Starts multiplication + 0x814 + 0x20 + + + SET_START_MULT + Configure whether or not to start the multiplication. + +0: No effect + +1: Start + 0 + 1 + write-only + + + + + QUERY_IDLE + Represents the RSA status + 0x818 + 0x20 + + + QUERY_IDLE + Represents the RSA status. + +0: Busy + +1: Idle + 0 + 1 + read-only + + + + + INT_CLR + Clears RSA interrupt + 0x81C + 0x20 + + + CLEAR_INTERRUPT + Write 1 to clear the RSA interrupt. + 0 + 1 + write-only + + + + + CONSTANT_TIME + Configures the constant_time option + 0x820 + 0x20 + 0x00000001 + + + CONSTANT_TIME + Configures the constant_time option. + +0: Acceleration + +1: No acceleration (default) + 0 + 1 + read-write + + + + + SEARCH_ENABLE + Configures the search option + 0x824 + 0x20 + + + SEARCH_ENABLE + Configure the search option. + +0: No acceleration (default) + +1: Acceleration + +This option should be used together with RSA_SEARCH_POS. + 0 + 1 + read-write + + + + + SEARCH_POS + Configures the search position + 0x828 + 0x20 + + + SEARCH_POS + Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + 0 + 12 + read-write + + + + + INT_ENA + Enables the RSA interrupt + 0x82C + 0x20 + + + INT_ENA + Write 1 to enable the RSA interrupt. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x830 + 0x20 + 0x20200618 + + + DATE + Version control register. + 0 + 30 + read-write + + + + + + + LP_ADC + Low-power Analog to Digital Converter + RTCADC + 0x50127000 + + 0x0 + 0x80 + registers + + + LP_ADC + 9 + + + + READER1_CTRL + Control the read operation of ADC1. + 0x0 + 0x20 + 0x20040002 + + + SAR1_CLK_DIV + Clock divider. + 0 + 8 + read-write + + + SAR1_CLK_GATED + N/A + 18 + 1 + read-write + + + SAR1_SAMPLE_NUM + N/A + 19 + 8 + read-write + + + SAR1_DATA_INV + Invert SAR ADC1 data. + 28 + 1 + read-write + + + SAR1_INT_EN + Enable saradc1 to send out interrupt. + 29 + 1 + read-write + + + SAR1_EN_PAD_FORCE_ENABLE + Force enable adc en_pad to analog circuit 2'b11: force enable . + 30 + 2 + read-write + + + + + READER1_STATUS + N/A + 0x4 + 0x20 + 0x20000000 + + + SAR1_READER_STATUS + N/A + 0 + 32 + read-only + + + + + MEAS1_CTRL1 + N/A + 0x8 + 0x20 + + + FORCE_XPD_AMP + N/A + 24 + 2 + read-write + + + AMP_RST_FB_FORCE + N/A + 26 + 2 + read-write + + + AMP_SHORT_REF_FORCE + N/A + 28 + 2 + read-write + + + AMP_SHORT_REF_GND_FORCE + N/A + 30 + 2 + read-write + + + + + MEAS1_CTRL2 + ADC1 configuration registers. + 0xC + 0x20 + + + MEAS1_DATA_SAR + SAR ADC1 data. + 0 + 16 + read-only + + + MEAS1_DONE_SAR + SAR ADC1 conversion done indication. + 16 + 1 + read-only + + + MEAS1_START_SAR + SAR ADC1 controller (in RTC) starts conversion. + 17 + 1 + read-write + + + MEAS1_START_FORCE + 1: SAR ADC1 controller (in RTC) is started by SW. + 18 + 1 + read-write + + + SAR1_EN_PAD + SAR ADC1 pad enable bitmap. + 19 + 12 + read-write + + + SAR1_EN_PAD_FORCE + 1: SAR ADC1 pad enable bitmap is controlled by SW. + 31 + 1 + read-write + + + + + MEAS1_MUX + SAR ADC1 MUX register. + 0x10 + 0x20 + + + SAR1_DIG_FORCE + 1: SAR ADC1 controlled by DIG ADC1 CTRL. + 31 + 1 + read-write + + + + + ATTEN1 + ADC1 attenuation registers. + 0x14 + 0x20 + 0xFFFFFFFF + + + SAR1_ATTEN + 2-bit attenuation for each pad. + 0 + 32 + read-write + + + + + AMP_CTRL1 + N/A + 0x18 + 0x20 + 0x000A000A + + + SAR_AMP_WAIT1 + N/A + 0 + 16 + read-write + + + SAR_AMP_WAIT2 + N/A + 16 + 16 + read-write + + + + + AMP_CTRL2 + N/A + 0x1C + 0x20 + 0x000A0000 + + + SAR1_DAC_XPD_FSM_IDLE + N/A + 0 + 1 + read-write + + + XPD_SAR_AMP_FSM_IDLE + N/A + 1 + 1 + read-write + + + AMP_RST_FB_FSM_IDLE + N/A + 2 + 1 + read-write + + + AMP_SHORT_REF_FSM_IDLE + N/A + 3 + 1 + read-write + + + AMP_SHORT_REF_GND_FSM_IDLE + N/A + 4 + 1 + read-write + + + XPD_SAR_FSM_IDLE + N/A + 5 + 1 + read-write + + + SAR_RSTB_FSM_IDLE + N/A + 6 + 1 + read-write + + + SAR_AMP_WAIT3 + N/A + 16 + 16 + read-write + + + + + AMP_CTRL3 + N/A + 0x20 + 0x20 + 0x007338F3 + + + SAR1_DAC_XPD_FSM + N/A + 0 + 4 + read-write + + + XPD_SAR_AMP_FSM + N/A + 4 + 4 + read-write + + + AMP_RST_FB_FSM + N/A + 8 + 4 + read-write + + + AMP_SHORT_REF_FSM + N/A + 12 + 4 + read-write + + + AMP_SHORT_REF_GND_FSM + N/A + 16 + 4 + read-write + + + XPD_SAR_FSM + N/A + 20 + 4 + read-write + + + SAR_RSTB_FSM + N/A + 24 + 4 + read-write + + + + + READER2_CTRL + Control the read operation of ADC2. + 0x24 + 0x20 + 0x40050002 + + + SAR2_CLK_DIV + Clock divider. + 0 + 8 + read-write + + + SAR2_WAIT_ARB_CYCLE + Wait arbit stable after sar_done. + 16 + 2 + read-write + + + SAR2_CLK_GATED + N/A + 18 + 1 + read-write + + + SAR2_SAMPLE_NUM + N/A + 19 + 8 + read-write + + + SAR2_EN_PAD_FORCE_ENABLE + Force enable adc en_pad to analog circuit 2'b11: force enable . + 27 + 2 + read-write + + + SAR2_DATA_INV + Invert SAR ADC2 data. + 29 + 1 + read-write + + + SAR2_INT_EN + Enable saradc2 to send out interrupt. + 30 + 1 + read-write + + + + + READER2_STATUS + N/A + 0x28 + 0x20 + + + SAR2_READER_STATUS + N/A + 0 + 32 + read-only + + + + + MEAS2_CTRL1 + ADC2 configuration registers. + 0x2C + 0x20 + 0x07020200 + + + SAR2_CNTL_STATE + saradc2_cntl_fsm. + 0 + 3 + read-only + + + SAR2_PWDET_CAL_EN + RTC control pwdet enable. + 3 + 1 + read-write + + + SAR2_PKDET_CAL_EN + RTC control pkdet enable. + 4 + 1 + read-write + + + SAR2_EN_TEST + SAR2_EN_TEST. + 5 + 1 + read-write + + + SAR2_RSTB_FORCE + N/A + 6 + 2 + read-write + + + SAR2_STANDBY_WAIT + N/A + 8 + 8 + read-write + + + SAR2_RSTB_WAIT + N/A + 16 + 8 + read-write + + + SAR2_XPD_WAIT + N/A + 24 + 8 + read-write + + + + + MEAS2_CTRL2 + ADC2 configuration registers. + 0x30 + 0x20 + + + MEAS2_DATA_SAR + SAR ADC2 data. + 0 + 16 + read-only + + + MEAS2_DONE_SAR + SAR ADC2 conversion done indication. + 16 + 1 + read-only + + + MEAS2_START_SAR + SAR ADC2 controller (in RTC) starts conversion. + 17 + 1 + read-write + + + MEAS2_START_FORCE + 1: SAR ADC2 controller (in RTC) is started by SW. + 18 + 1 + read-write + + + SAR2_EN_PAD + SAR ADC2 pad enable bitmap. + 19 + 12 + read-write + + + SAR2_EN_PAD_FORCE + 1: SAR ADC2 pad enable bitmap is controlled by SW. + 31 + 1 + read-write + + + + + MEAS2_MUX + SAR ADC2 MUX register. + 0x34 + 0x20 + + + SAR2_PWDET_CCT + SAR2_PWDET_CCT. + 28 + 3 + read-write + + + SAR2_RTC_FORCE + In sleep, force to use rtc to control ADC. + 31 + 1 + read-write + + + + + ATTEN2 + ADC1 attenuation registers. + 0x38 + 0x20 + 0xFFFFFFFF + + + SAR2_ATTEN + 2-bit attenuation for each pad. + 0 + 32 + read-write + + + + + FORCE_WPD_SAR + In sleep, force to use rtc to control ADC + 0x3C + 0x20 + + + FORCE_XPD_SAR1 + 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control. + 0 + 2 + read-write + + + FORCE_XPD_SAR2 + 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control. + 2 + 2 + read-write + + + + + MEAS_STATUS + N/A + 0x40 + 0x20 + + + SARADC_MEAS_STATUS + N/A + 0 + 8 + read-only + + + + + REG_CLKEN + N/A + 0x44 + 0x20 + + + CLK_EN + N/A + 0 + 1 + read-write + + + + + COCPU_INT_RAW + Interrupt raw registers. + 0x48 + 0x20 + + + COCPU_SARADC1_INT_RAW + ADC1 Conversion is done, int raw. + 0 + 1 + read-write + + + COCPU_SARADC2_INT_RAW + ADC2 Conversion is done, int raw. + 1 + 1 + read-write + + + COCPU_SARADC1_ERROR_INT_RAW + An errro occurs from ADC1, int raw. + 2 + 1 + read-write + + + COCPU_SARADC2_ERROR_INT_RAW + An errro occurs from ADC2, int raw. + 3 + 1 + read-write + + + COCPU_SARADC1_WAKE_INT_RAW + A wakeup event is triggered from ADC1, int raw. + 4 + 1 + read-write + + + COCPU_SARADC2_WAKE_INT_RAW + A wakeup event is triggered from ADC2, int raw. + 5 + 1 + read-write + + + + + INT_ENA + Interrupt enable registers. + 0x4C + 0x20 + + + COCPU_SARADC1_INT_ENA + ADC1 Conversion is done, int enable. + 0 + 1 + read-write + + + COCPU_SARADC2_INT_ENA + ADC2 Conversion is done, int enable. + 1 + 1 + read-write + + + COCPU_SARADC1_ERROR_INT_ENA + An errro occurs from ADC1, int enable. + 2 + 1 + read-write + + + COCPU_SARADC2_ERROR_INT_ENA + An errro occurs from ADC2, int enable. + 3 + 1 + read-write + + + COCPU_SARADC1_WAKE_INT_ENA + A wakeup event is triggered from ADC1, int enable. + 4 + 1 + read-write + + + COCPU_SARADC2_WAKE_INT_ENA + A wakeup event is triggered from ADC2, int enable. + 5 + 1 + read-write + + + + + INT_ST + Interrupt status registers. + 0x50 + 0x20 + + + COCPU_SARADC1_INT_ST + ADC1 Conversion is done, int status. + 0 + 1 + read-only + + + COCPU_SARADC2_INT_ST + ADC2 Conversion is done, int status. + 1 + 1 + read-only + + + COCPU_SARADC1_ERROR_INT_ST + An errro occurs from ADC1, int status. + 2 + 1 + read-only + + + COCPU_SARADC2_ERROR_INT_ST + An errro occurs from ADC2, int status. + 3 + 1 + read-only + + + COCPU_SARADC1_WAKE_INT_ST + A wakeup event is triggered from ADC1, int status. + 4 + 1 + read-only + + + COCPU_SARADC2_WAKE_INT_ST + A wakeup event is triggered from ADC2, int status. + 5 + 1 + read-only + + + + + INT_CLR + Interrupt clear registers. + 0x54 + 0x20 + + + COCPU_SARADC1_INT_CLR + ADC1 Conversion is done, int clear. + 0 + 1 + write-only + + + COCPU_SARADC2_INT_CLR + ADC2 Conversion is done, int clear. + 1 + 1 + write-only + + + COCPU_SARADC1_ERROR_INT_CLR + An errro occurs from ADC1, int clear. + 2 + 1 + write-only + + + COCPU_SARADC2_ERROR_INT_CLR + An errro occurs from ADC2, int clear. + 3 + 1 + write-only + + + COCPU_SARADC1_WAKE_INT_CLR + A wakeup event is triggered from ADC1, int clear. + 4 + 1 + write-only + + + COCPU_SARADC2_WAKE_INT_CLR + A wakeup event is triggered from ADC2, int clear. + 5 + 1 + write-only + + + + + INT_ENA_W1TS + Interrupt enable assert registers. + 0x58 + 0x20 + + + COCPU_SARADC1_INT_ENA_W1TS + ADC1 Conversion is done, write 1 to assert int enable. + 0 + 1 + write-only + + + COCPU_SARADC2_INT_ENA_W1TS + ADC2 Conversion is done, write 1 to assert int enable. + 1 + 1 + write-only + + + COCPU_SARADC1_ERROR_INT_ENA_W1TS + An errro occurs from ADC1, write 1 to assert int enable. + 2 + 1 + write-only + + + COCPU_SARADC2_ERROR_INT_ENA_W1TS + An errro occurs from ADC2, write 1 to assert int enable. + 3 + 1 + write-only + + + COCPU_SARADC1_WAKE_INT_ENA_W1TS + A wakeup event is triggered from ADC1, write 1 to assert int enable. + 4 + 1 + write-only + + + COCPU_SARADC2_WAKE_INT_ENA_W1TS + A wakeup event is triggered from ADC2, write 1 to assert int enable. + 5 + 1 + write-only + + + + + INT_ENA_W1TC + Interrupt enable deassert registers. + 0x5C + 0x20 + + + COCPU_SARADC1_INT_ENA_W1TC + ADC1 Conversion is done, write 1 to deassert int enable. + 0 + 1 + write-only + + + COCPU_SARADC2_INT_ENA_W1TC + ADC2 Conversion is done, write 1 to deassert int enable. + 1 + 1 + write-only + + + COCPU_SARADC1_ERROR_INT_ENA_W1TC + An errro occurs from ADC1, write 1 to deassert int enable. + 2 + 1 + write-only + + + COCPU_SARADC2_ERROR_INT_ENA_W1TC + An errro occurs from ADC2, write 1 to deassert int enable. + 3 + 1 + write-only + + + COCPU_SARADC1_WAKE_INT_ENA_W1TC + A wakeup event is triggered from ADC1, write 1 to deassert int enable. + 4 + 1 + write-only + + + COCPU_SARADC2_WAKE_INT_ENA_W1TC + A wakeup event is triggered from ADC2, write 1 to deassert int enable. + 5 + 1 + write-only + + + + + WAKEUP1 + ADC1 wakeup configuration registers. + 0x60 + 0x20 + 0x03FFC000 + + + SAR1_WAKEUP_TH_LOW + Lower threshold. + 0 + 12 + read-write + + + SAR1_WAKEUP_TH_HIGH + Upper threshold. + 14 + 12 + read-write + + + SAR1_WAKEUP_OVER_UPPER_TH + Indicates that this wakeup event arose from exceeding upper threshold. + 29 + 1 + read-only + + + SAR1_WAKEUP_EN + Wakeup function enable. + 30 + 1 + read-write + + + SAR1_WAKEUP_MODE + 0:absolute value comparison mode. 1: relative value comparison mode. + 31 + 1 + read-write + + + + + WAKEUP2 + ADC2 wakeup configuration registers. + 0x64 + 0x20 + 0x03FFC000 + + + SAR2_WAKEUP_TH_LOW + Lower threshold. + 0 + 12 + read-write + + + SAR2_WAKEUP_TH_HIGH + Upper threshold. + 14 + 12 + read-write + + + SAR2_WAKEUP_OVER_UPPER_TH + Indicates that this wakeup event arose from exceeding upper threshold. + 29 + 1 + read-only + + + SAR2_WAKEUP_EN + Wakeup function enable. + 30 + 1 + read-write + + + SAR2_WAKEUP_MODE + 0:absolute value comparison mode. 1: relative value comparison mode. + 31 + 1 + read-write + + + + + WAKEUP_SEL + Wakeup source select register. + 0x68 + 0x20 + + + SAR_WAKEUP_SEL + 0: ADC1. 1: ADC2. + 0 + 1 + read-write + + + + + SAR1_HW_WAKEUP + Hardware automatic sampling registers for wakeup function. + 0x6C + 0x20 + 0x000000C8 + + + ADC1_HW_READ_EN_I + Enable hardware automatic sampling. + 0 + 1 + read-write + + + ADC1_HW_READ_RATE_I + Hardware automatic sampling rate. + 1 + 16 + read-write + + + + + SAR2_HW_WAKEUP + Hardware automatic sampling registers for wakeup function. + 0x70 + 0x20 + 0x000000C8 + + + ADC2_HW_READ_EN_I + Enable hardware automatic sampling. + 0 + 1 + read-write + + + ADC2_HW_READ_RATE_I + Hardware automatic sampling rate. + 1 + 16 + read-write + + + + + RND_ECO_LOW + N/A + 0x74 + 0x20 + + + RND_ECO_LOW + N/A + 0 + 32 + read-write + + + + + RND_ECO_HIGH + N/A + 0x78 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + N/A + 0 + 32 + read-write + + + + + RND_ECO_CS + N/A + 0x7C + 0x20 + + + RND_ECO_EN + N/A + 0 + 1 + read-write + + + RND_ECO_RESULT + N/A + 1 + 1 + read-only + + + + + + + LP_TIMER + Low-power Timer + RTC_TIMER + 0x50112000 + + 0x0 + 0x4C + registers + + + LP_TIMER0 + 2 + + + LP_TIMER1 + 3 + + + + TAR0_LOW + need_des + 0x0 + 0x20 + + + MAIN_TIMER_TAR_LOW0 + need_des + 0 + 32 + read-write + + + + + TAR0_HIGH + need_des + 0x4 + 0x20 + + + MAIN_TIMER_TAR_HIGH0 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN0 + need_des + 31 + 1 + write-only + + + + + TAR1_LOW + need_des + 0x8 + 0x20 + + + MAIN_TIMER_TAR_LOW1 + need_des + 0 + 32 + read-write + + + + + TAR1_HIGH + need_des + 0xC + 0x20 + + + MAIN_TIMER_TAR_HIGH1 + need_des + 0 + 16 + read-write + + + MAIN_TIMER_TAR_EN1 + need_des + 31 + 1 + write-only + + + + + UPDATE + need_des + 0x10 + 0x20 + + + MAIN_TIMER_UPDATE + need_des + 28 + 1 + write-only + + + MAIN_TIMER_XTAL_OFF + need_des + 29 + 1 + read-write + + + MAIN_TIMER_SYS_STALL + need_des + 30 + 1 + read-write + + + MAIN_TIMER_SYS_RST + need_des + 31 + 1 + read-write + + + + + MAIN_BUF0_LOW + need_des + 0x14 + 0x20 + + + MAIN_TIMER_BUF0_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF0_HIGH + need_des + 0x18 + 0x20 + + + MAIN_TIMER_BUF0_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_BUF1_LOW + need_des + 0x1C + 0x20 + + + MAIN_TIMER_BUF1_LOW + need_des + 0 + 32 + read-only + + + + + MAIN_BUF1_HIGH + need_des + 0x20 + 0x20 + + + MAIN_TIMER_BUF1_HIGH + need_des + 0 + 16 + read-only + + + + + MAIN_OVERFLOW + need_des + 0x24 + 0x20 + + + MAIN_TIMER_ALARM_LOAD + need_des + 31 + 1 + write-only + + + + + INT_RAW + need_des + 0x28 + 0x20 + + + OVERFLOW_RAW + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + need_des + 0x2C + 0x20 + + + OVERFLOW_ST + need_des + 30 + 1 + read-only + + + SOC_WAKEUP_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x30 + 0x20 + + + OVERFLOW_ENA + need_des + 30 + 1 + read-write + + + SOC_WAKEUP_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x34 + 0x20 + + + OVERFLOW_CLR + need_des + 30 + 1 + write-only + + + SOC_WAKEUP_INT_CLR + need_des + 31 + 1 + write-only + + + + + LP_INT_RAW + need_des + 0x38 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_RAW + need_des + 30 + 1 + read-write + + + MAIN_TIMER_LP_INT_RAW + need_des + 31 + 1 + read-write + + + + + LP_INT_ST + need_des + 0x3C + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ST + need_des + 30 + 1 + read-only + + + MAIN_TIMER_LP_INT_ST + need_des + 31 + 1 + read-only + + + + + LP_INT_ENA + need_des + 0x40 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_ENA + need_des + 30 + 1 + read-write + + + MAIN_TIMER_LP_INT_ENA + need_des + 31 + 1 + read-write + + + + + LP_INT_CLR + need_des + 0x44 + 0x20 + + + MAIN_TIMER_OVERFLOW_LP_INT_CLR + need_des + 30 + 1 + write-only + + + MAIN_TIMER_LP_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02111150 + + + DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_TOUCH + LP_TOUCH Peripheral + RTC_TOUCH + 0x50128000 + + 0x0 + 0x64 + registers + + + LP_TOUCH + 14 + + + + INT_RAW + need_des + 0x0 + 0x20 + + + SCAN_DONE_INT_RAW + need_des + 0 + 1 + read-write + + + DONE_INT_RAW + need_des + 1 + 1 + read-write + + + ACTIVE_INT_RAW + need_des + 2 + 1 + read-write + + + INACTIVE_INT_RAW + need_des + 3 + 1 + read-write + + + TIMEOUT_INT_RAW + need_des + 4 + 1 + read-write + + + APPROACH_LOOP_DONE_INT_RAW + need_des + 5 + 1 + read-write + + + + + INT_ST + need_des + 0x4 + 0x20 + + + SCAN_DONE_INT_ST + need_des + 0 + 1 + read-only + + + DONE_INT_ST + need_des + 1 + 1 + read-only + + + ACTIVE_INT_ST + need_des + 2 + 1 + read-only + + + INACTIVE_INT_ST + need_des + 3 + 1 + read-only + + + TIMEOUT_INT_ST + need_des + 4 + 1 + read-only + + + APPROACH_LOOP_DONE_INT_ST + need_des + 5 + 1 + read-only + + + + + INT_ENA + need_des + 0x8 + 0x20 + + + SCAN_DONE_INT_ENA + need_des + 0 + 1 + read-write + + + DONE_INT_ENA + need_des + 1 + 1 + read-write + + + ACTIVE_INT_ENA + need_des + 2 + 1 + read-write + + + INACTIVE_INT_ENA + need_des + 3 + 1 + read-write + + + TIMEOUT_INT_ENA + need_des + 4 + 1 + read-write + + + APPROACH_LOOP_DONE_INT_ENA + need_des + 5 + 1 + read-write + + + + + INT_CLR + need_des + 0xC + 0x20 + + + SCAN_DONE_INT_CLR + need_des + 0 + 1 + write-only + + + DONE_INT_CLR + need_des + 1 + 1 + write-only + + + ACTIVE_INT_CLR + need_des + 2 + 1 + write-only + + + INACTIVE_INT_CLR + need_des + 3 + 1 + write-only + + + TIMEOUT_INT_CLR + need_des + 4 + 1 + write-only + + + APPROACH_LOOP_DONE_INT_CLR + need_des + 5 + 1 + write-only + + + + + CHN_STATUS + need_des + 0x10 + 0x20 + + + PAD_ACTIVE + need_des + 0 + 15 + read-only + + + MEAS_DONE + need_des + 15 + 1 + read-only + + + SCAN_CURR + need_des + 16 + 4 + read-only + + + + + STATUS_0 + need_des + 0x14 + 0x20 + + + PAD0_DATA + need_des + 0 + 16 + read-only + + + PAD0_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD0_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_1 + need_des + 0x18 + 0x20 + + + PAD1_DATA + need_des + 0 + 16 + read-only + + + PAD1_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD1_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_2 + need_des + 0x1C + 0x20 + + + PAD2_DATA + need_des + 0 + 16 + read-only + + + PAD2_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD2_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_3 + need_des + 0x20 + 0x20 + + + PAD3_DATA + need_des + 0 + 16 + read-only + + + PAD3_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD3_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_4 + need_des + 0x24 + 0x20 + + + PAD4_DATA + need_des + 0 + 16 + read-only + + + PAD4_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD4_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_5 + need_des + 0x28 + 0x20 + + + PAD5_DATA + need_des + 0 + 16 + read-only + + + PAD5_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD5_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_6 + need_des + 0x2C + 0x20 + + + PAD6_DATA + need_des + 0 + 16 + read-only + + + PAD6_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD6_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_7 + need_des + 0x30 + 0x20 + + + PAD7_DATA + need_des + 0 + 16 + read-only + + + PAD7_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD7_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_8 + need_des + 0x34 + 0x20 + + + PAD8_DATA + need_des + 0 + 16 + read-only + + + PAD8_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD8_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_9 + need_des + 0x38 + 0x20 + + + PAD9_DATA + need_des + 0 + 16 + read-only + + + PAD9_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD9_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_10 + need_des + 0x3C + 0x20 + + + PAD10_DATA + need_des + 0 + 16 + read-only + + + PAD10_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD10_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_11 + need_des + 0x40 + 0x20 + + + PAD11_DATA + need_des + 0 + 16 + read-only + + + PAD11_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD11_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_12 + need_des + 0x44 + 0x20 + + + PAD12_DATA + need_des + 0 + 16 + read-only + + + PAD12_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD12_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_13 + need_des + 0x48 + 0x20 + + + PAD13_DATA + need_des + 0 + 16 + read-only + + + PAD13_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD13_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_14 + need_des + 0x4C + 0x20 + + + PAD14_DATA + need_des + 0 + 16 + read-only + + + PAD14_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + PAD14_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_15 + need_des + 0x50 + 0x20 + + + SLP_DATA + need_des + 0 + 16 + read-only + + + SLP_DEBOUNCE_CNT + need_des + 16 + 3 + read-only + + + SLP_NEG_NOISE_CNT + need_des + 19 + 4 + read-only + + + + + STATUS_16 + need_des + 0x54 + 0x20 + + + APPROACH_PAD2_CNT + need_des + 0 + 8 + read-only + + + APPROACH_PAD1_CNT + need_des + 8 + 8 + read-only + + + APPROACH_PAD0_CNT + need_des + 16 + 8 + read-only + + + SLP_APPROACH_CNT + need_des + 24 + 8 + read-only + + + + + STATUS_17 + need_des + 0x58 + 0x20 + + + DCAP_LPF + Reserved + 0 + 7 + read-only + + + DRES_LPF + need_des + 7 + 2 + read-only + + + DRV_LS + need_des + 9 + 4 + read-only + + + DRV_HS + need_des + 13 + 5 + read-only + + + DBIAS + need_des + 18 + 5 + read-only + + + RTC_FREQ_SCAN_CNT + need_des + 23 + 2 + read-only + + + + + CHN_TMP_STATUS + need_des + 0x5C + 0x20 + + + PAD_INACTIVE_STATUS + need_des + 0 + 15 + read-only + + + PAD_ACTIVE_STATUS + need_des + 15 + 15 + read-only + + + + + DATE + need_des + 0x100 + 0x20 + 0x00230314 + + + RTC_DATE + need_des + 0 + 28 + read-write + + + RTC_CLK_EN + need_des + 31 + 1 + read-write + + + + + + + LP_WDT + Low-power Watchdog Timer + RTC_WDT + 0x50116000 + + 0x0 + 0x38 + registers + + + LP_WDT + 1 + + + + CONFIG0 + need_des + 0x0 + 0x20 + 0x00013214 + + + WDT_CHIP_RESET_WIDTH + need_des + 0 + 8 + read-write + + + WDT_CHIP_RESET_EN + need_des + 8 + 1 + read-write + + + WDT_PAUSE_IN_SLP + need_des + 9 + 1 + read-write + + + WDT_APPCPU_RESET_EN + need_des + 10 + 1 + read-write + + + WDT_PROCPU_RESET_EN + need_des + 11 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + need_des + 12 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + need_des + 13 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + need_des + 16 + 3 + read-write + + + WDT_STG3 + need_des + 19 + 3 + read-write + + + WDT_STG2 + need_des + 22 + 3 + read-write + + + WDT_STG1 + need_des + 25 + 3 + read-write + + + WDT_STG0 + need_des + 28 + 3 + read-write + + + WDT_EN + need_des + 31 + 1 + read-write + + + + + CONFIG1 + need_des + 0x4 + 0x20 + 0x00030D40 + + + WDT_STG0_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG2 + need_des + 0x8 + 0x20 + 0x00013880 + + + WDT_STG1_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG3 + need_des + 0xC + 0x20 + 0x00000FFF + + + WDT_STG2_HOLD + need_des + 0 + 32 + read-write + + + + + CONFIG4 + need_des + 0x10 + 0x20 + 0x00000FFF + + + WDT_STG3_HOLD + need_des + 0 + 32 + read-write + + + + + FEED + need_des + 0x14 + 0x20 + + + FEED + need_des + 31 + 1 + write-only + + + + + WPROTECT + need_des + 0x18 + 0x20 + + + WDT_WKEY + need_des + 0 + 32 + read-write + + + + + SWD_CONFIG + need_des + 0x1C + 0x20 + 0x12C00000 + + + SWD_RESET_FLAG + need_des + 0 + 1 + read-only + + + SWD_AUTO_FEED_EN + need_des + 18 + 1 + read-write + + + SWD_RST_FLAG_CLR + need_des + 19 + 1 + write-only + + + SWD_SIGNAL_WIDTH + need_des + 20 + 10 + read-write + + + SWD_DISABLE + need_des + 30 + 1 + read-write + + + SWD_FEED + need_des + 31 + 1 + write-only + + + + + SWD_WPROTECT + need_des + 0x20 + 0x20 + + + SWD_WKEY + need_des + 0 + 32 + read-write + + + + + INT_RAW + need_des + 0x24 + 0x20 + + + SUPER_WDT_INT_RAW + need_des + 30 + 1 + read-write + + + LP_WDT_INT_RAW + need_des + 31 + 1 + read-write + + + + + INT_ST + need_des + 0x28 + 0x20 + + + SUPER_WDT_INT_ST + need_des + 30 + 1 + read-only + + + LP_WDT_INT_ST + need_des + 31 + 1 + read-only + + + + + INT_ENA + need_des + 0x2C + 0x20 + + + SUPER_WDT_INT_ENA + need_des + 30 + 1 + read-write + + + LP_WDT_INT_ENA + need_des + 31 + 1 + read-write + + + + + INT_CLR + need_des + 0x30 + 0x20 + + + SUPER_WDT_INT_CLR + need_des + 30 + 1 + write-only + + + LP_WDT_INT_CLR + need_des + 31 + 1 + write-only + + + + + DATE + need_des + 0x3FC + 0x20 + 0x02112080 + + + LP_WDT_DATE + need_des + 0 + 31 + read-write + + + CLK_EN + need_des + 31 + 1 + read-write + + + + + + + SDHOST + SD/MMC Host Controller + SDHOST + 0x50083000 + + 0x0 + 0xB0 + registers + + + + CTRL + Control register + 0x0 + 0x20 + + + CONTROLLER_RESET + To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles. + 0 + 1 + read-write + + + FIFO_RESET + To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. +Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. + 1 + 1 + read-write + + + DMA_RESET + To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. + 2 + 1 + read-write + + + INT_ENABLE + Global interrupt enable/disable bit. 0: Disable; 1: Enable. + 4 + 1 + read-write + + + READ_WAIT + For sending read-wait to SDIO cards. + 6 + 1 + read-write + + + SEND_IRQ_RESPONSE + Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state. + 7 + 1 + read-write + + + ABORT_READ_DATA + After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle. + 8 + 1 + read-write + + + SEND_CCSD + When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. +NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS. + 9 + 1 + read-write + + + SEND_AUTO_STOP_CCSD + Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit. + 10 + 1 + read-write + + + CEATA_DEVICE_INTERRUPT_STATUS + Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit. + 11 + 1 + read-write + + + + + CLKDIV + Clock divider configuration register + 0x8 + 0x20 + + + CLK_DIVIDER0 + Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 0 + 8 + read-write + + + CLK_DIVIDER1 + Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 8 + 8 + read-write + + + CLK_DIVIDER2 + Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 16 + 8 + read-write + + + CLK_DIVIDER3 + Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on. + 24 + 8 + read-write + + + + + CLKSRC + Clock source selection register + 0xC + 0x20 + + + CLKSRC + Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value. +00 : Clock divider 0; +01 : Clock divider 1; +10 : Clock divider 2; +11 : Clock divider 3. + 0 + 4 + read-write + + + + + CLKENA + Clock enable register + 0x10 + 0x20 + + + CCLK_ENABLE + Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. +0: Clock disabled; +1: Clock enabled. + 0 + 2 + read-write + + + LP_ENABLE + Disable clock when the card is in IDLE state. One bit per card. +0: clock disabled; +1: clock enabled. + 16 + 2 + read-write + + + + + TMOUT + Data and response timeout configuration register + 0x14 + 0x20 + 0xFFFFFF40 + + + RESPONSE_TIMEOUT + Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out. + 0 + 8 + read-write + + + DATA_TIMEOUT + Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. +NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled. + 8 + 24 + read-write + + + + + CTYPE + Card bus width configuration register + 0x18 + 0x20 + + + CARD_WIDTH4 + One bit per card indicates if card is 1-bit or 4-bit mode. +0: 1-bit mode; +1: 4-bit mode. +Bit[1:0] correspond to card[1:0] respectively. + 0 + 2 + read-write + + + CARD_WIDTH8 + One bit per card indicates if card is in 8-bit mode. +0: Non 8-bit mode; +1: 8-bit mode. +Bit[17:16] correspond to card[1:0] respectively. + 16 + 2 + read-write + + + + + BLKSIZ + Card data block size configuration register + 0x1C + 0x20 + 0x00000200 + + + BLOCK_SIZE + Block size. + 0 + 16 + read-write + + + + + BYTCNT + Data transfer length configuration register + 0x20 + 0x20 + 0x00000200 + + + BYTE_COUNT + Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer. + 0 + 32 + read-write + + + + + INTMASK + SDIO interrupt mask register + 0x24 + 0x20 + + + INT_MASK + These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): Rx Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation-by-host timeout; +Bit 9 (DRTO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-write + + + SDIO_INT_MASK + SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt. + 16 + 2 + read-write + + + + + CMDARG + Command argument data register + 0x28 + 0x20 + + + CMDARG + Value indicates command argument to be passed to the card. + 0 + 32 + read-write + + + + + CMD + Command and boot configuration register + 0x2C + 0x20 + 0x20000000 + + + INDEX + Command index. + 0 + 6 + read-write + + + RESPONSE_EXPECT + 0: No response expected from card; 1: Response expected from card. + 6 + 1 + read-write + + + RESPONSE_LENGTH + 0: Short response expected from card; 1: Long response expected from card. + 7 + 1 + read-write + + + CHECK_RESPONSE_CRC + 0: Do not check; 1: Check response CRC. +Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. + 8 + 1 + read-write + + + DATA_EXPECTED + 0: No data transfer expected; 1: Data transfer expected. + 9 + 1 + read-write + + + READ_WRITE + 0: Read from card; 1: Write to card. +Don't care if no data is expected from card. + 10 + 1 + read-write + + + TRANSFER_MODE + 0: Block data transfer command; 1: Stream data transfer command. +Don't care if no data expected. + 11 + 1 + read-write + + + SEND_AUTO_STOP + 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer. + 12 + 1 + read-write + + + WAIT_PRVDATA_COMPLETE + 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. +The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command. + 13 + 1 + read-write + + + STOP_ABORT_CMD + 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. +When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. + 14 + 1 + read-write + + + SEND_INITIALIZATION + 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. +After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. + 15 + 1 + read-write + + + CARD_NUMBER + Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported. + 16 + 5 + read-write + + + UPDATE_CLOCK_REGISTERS_ONLY + 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. +Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. +Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. + 21 + 1 + read-write + + + READ_CEATA_DEVICE + Read access flag. +0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; +1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. +Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device. + 22 + 1 + read-write + + + CCS_EXPECTED + Expected Command Completion Signal (CCS) configuration. +0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; +1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. +If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked. + 23 + 1 + read-write + + + USE_HOLE + Use Hold Register. +0: CMD and DATA sent to card bypassing HOLD Register; +1: CMD and DATA sent to card through the HOLD Register. + 29 + 1 + read-write + + + START_CMD + Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register. + 31 + 1 + read-write + + + + + RESP0 + Response data register + 0x30 + 0x20 + + + RESPONSE0 + Bit[31:0] of response. + 0 + 32 + read-only + + + + + RESP1 + Long response data register + 0x34 + 0x20 + + + RESPONSE1 + Bit[63:32] of long response. + 0 + 32 + read-only + + + + + RESP2 + Long response data register + 0x38 + 0x20 + + + RESPONSE2 + Bit[95:64] of long response. + 0 + 32 + read-only + + + + + RESP3 + Long response data register + 0x3C + 0x20 + + + RESPONSE3 + Bit[127:96] of long response. + 0 + 32 + read-only + + + + + MINTSTS + Masked interrupt status register + 0x40 + 0x20 + + + INT_STATUS_MSK + Interrupt enabled only if corresponding bit in interrupt mask register is set. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-only + + + SDIO_INTERRUPT_MSK + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). + 16 + 2 + read-only + + + + + RINTSTS + Raw interrupt status register + 0x44 + 0x20 + + + INT_STATUS_RAW + Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. +Bit 15 (EBE): End-bit error/no CRC error; +Bit 14 (ACD): Auto command done; +Bit 13 (SBE/BCI): RX Start Bit Error; +Bit 12 (HLE): Hardware locked write error; +Bit 11 (FRUN): FIFO underrun/overrun error; +Bit 10 (HTO): Data starvation by host timeout (HTO); +Bit 9 (DTRO): Data read timeout; +Bit 8 (RTO): Response timeout; +Bit 7 (DCRC): Data CRC error; +Bit 6 (RCRC): Response CRC error; +Bit 5 (RXDR): Receive FIFO data request; +Bit 4 (TXDR): Transmit FIFO data request; +Bit 3 (DTO): Data transfer over; +Bit 2 (CD): Command done; +Bit 1 (RE): Response error; +Bit 0 (CD): Card detect. + 0 + 16 + read-write + + + SDIO_INTERRUPT_RAW + Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. +0: No SDIO interrupt from card; +1: SDIO interrupt from card. + 16 + 2 + read-write + + + + + STATUS + SD/MMC status register + 0x48 + 0x20 + 0x00000716 + + + FIFO_RX_WATERMARK + FIFO reached Receive watermark level, not qualified with data transfer. + 0 + 1 + read-only + + + FIFO_TX_WATERMARK + FIFO reached Transmit watermark level, not qualified with data transfer. + 1 + 1 + read-only + + + FIFO_EMPTY + FIFO is empty status. + 2 + 1 + read-only + + + FIFO_FULL + FIFO is full status. + 3 + 1 + read-only + + + COMMAND_FSM_STATES + Command FSM states. +0: Idle; +1: Send init sequence; +2: Send cmd start bit; +3: Send cmd tx bit; +4: Send cmd index + arg; +5: Send cmd crc7; +6: Send cmd end bit; +7: Receive resp start bit; +8: Receive resp IRQ response; +9: Receive resp tx bit; +10: Receive resp cmd idx; +11: Receive resp data; +12: Receive resp crc7; +13: Receive resp end bit; +14: Cmd path wait NCC; +15: Wait, cmd-to-response turnaround. + 4 + 4 + read-only + + + DATA_3_STATUS + Raw selected sdhost_card_data[3], checks whether card is present. +0: card not present; +1: card present. + 8 + 1 + read-only + + + DATA_BUSY + Inverted version of raw selected sdhost_card_data[0]. +0: Card data not busy; +1: Card data busy. + 9 + 1 + read-only + + + DATA_STATE_MC_BUSY + Data transmit or receive state-machine is busy. + 10 + 1 + read-only + + + RESPONSE_INDEX + Index of previous response, including any auto-stop sent by core. + 11 + 6 + read-only + + + FIFO_COUNT + FIFO count, number of filled locations in FIFO. + 17 + 13 + read-only + + + + + FIFOTH + FIFO configuration register + 0x4C + 0x20 + + + TX_WMARK + FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. + 0 + 12 + read-write + + + RX_WMARK + FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. + 16 + 11 + read-write + + + DMA_MULTIPLE_TRANSACTION_SIZE + Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. + 28 + 3 + read-write + + + + + CDETECT + Card detect register + 0x50 + 0x20 + + + CARD_DETECT_N + Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented. + 0 + 2 + read-only + + + + + WRTPRT + Card write protection (WP) status register + 0x54 + 0x20 + + + WRITE_PROTECT + Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. + 0 + 2 + read-only + + + + + TCBCNT + Transferred byte count register + 0x5C + 0x20 + + + TCBCNT + Number of bytes transferred by CIU unit to card. + 0 + 32 + read-only + + + + + TBBCNT + Transferred byte count register + 0x60 + 0x20 + + + TBBCNT + Number of bytes transferred between Host/DMA memory and BIU FIFO. + 0 + 32 + read-only + + + + + DEBNCE + Debounce filter time configuration register + 0x64 + 0x20 + + + DEBOUNCE_COUNT + Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted or removed. + 0 + 24 + read-write + + + + + USRID + User ID (scratchpad) register + 0x68 + 0x20 + + + USRID + User identification register, value set by user. Can also be used as a scratchpad register by user. + 0 + 32 + read-write + + + + + VERID + Version ID (scratchpad) register + 0x6C + 0x20 + 0x5432270A + + + VERSIONID + Hardware version register. Can also be read by fireware. + 0 + 32 + read-only + + + + + HCON + Hardware feature register + 0x70 + 0x20 + 0x03444CC3 + + + CARD_TYPE + Hardware support SDIO and MMC. + 0 + 1 + read-only + + + CARD_NUM + Support card number is 2. + 1 + 5 + read-only + + + BUS_TYPE + Register config is APB bus. + 6 + 1 + read-only + + + DATA_WIDTH + Regisger data widht is 32. + 7 + 3 + read-only + + + ADDR_WIDTH + Register address width is 32. + 10 + 6 + read-only + + + DMA_WIDTH + DMA data witdth is 32. + 18 + 3 + read-only + + + RAM_INDISE + Inside RAM in SDMMC module. + 21 + 1 + read-only + + + HOLD + Have a hold regiser in data path . + 22 + 1 + read-only + + + NUM_CLK_DIV + Have 4 clk divider in design . + 24 + 2 + read-only + + + + + UHS + UHS-1 register + 0x74 + 0x20 + + + DDR + DDR mode selecton,1 bit for each card. +0-Non-DDR mdoe. +1-DDR mdoe. + 16 + 2 + read-write + + + + + RST_N + Card reset register + 0x78 + 0x20 + 0x00000001 + + + CARD_RESET + Hardware reset. +1: Active mode; +0: Reset. +These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1. + 0 + 2 + read-write + + + + + BMOD + Burst mode transfer configuration register + 0x80 + 0x20 + + + SWR + Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle. + 0 + 1 + read-write + + + FB + Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. + 1 + 1 + read-write + + + DE + IDMAC Enable. When set, the IDMAC is enabled. + 7 + 1 + read-write + + + PBL + Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: +000: 1-byte transfer; +001: 4-byte transfer; +010: 8-byte transfer; +011: 16-byte transfer; +100: 32-byte transfer; +101: 64-byte transfer; +110: 128-byte transfer; +111: 256-byte transfer. +PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access. + 8 + 3 + read-write + + + + + PLDMND + Poll demand configuration register + 0x84 + 0x20 + + + PD + Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only . + 0 + 32 + write-only + + + + + DBADDR + Descriptor base address register + 0x88 + 0x20 + + + DBADDR + Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only. + 0 + 32 + read-write + + + + + IDSTS + IDMAC status register + 0x8C + 0x20 + + + TI + Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. + 0 + 1 + read-write + + + RI + Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit. + 4 + 1 + read-write + + + CES + Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: +EBE : End Bit Error; +RTO : Response Timeout/Boot Ack Timeout; +RCRC : Response CRC; +SBE : Start Bit Error; +DRTO : Data Read Timeout/BDS timeout; +DCRC : Data CRC for Receive; +RE : Response Error. +Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error. + 5 + 1 + read-write + + + NIS + Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit. + 8 + 1 + read-write + + + AIS + Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit. + 9 + 1 + read-write + + + FBE_CODE + Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. +001: Host Abort received during transmission; +010: Host Abort received during reception; +Others: Reserved. + 10 + 3 + read-write + + + FSM + DMAC FSM present state. +0: DMA_IDLE (idle state); +1: DMA_SUSPEND (suspend state); +2: DESC_RD (descriptor reading state); +3: DESC_CHK (descriptor checking state); +4: DMA_RD_REQ_WAIT (read-data request waiting state); +5: DMA_WR_REQ_WAIT (write-data request waiting state); +6: DMA_RD (data-read state); +7: DMA_WR (data-write state); +8: DESC_CLOSE (descriptor close state). + 13 + 4 + read-write + + + + + IDINTEN + IDMAC interrupt enable register + 0x90 + 0x20 + + + TI + Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. + 0 + 1 + read-write + + + RI + Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. + 1 + 1 + read-write + + + FBE + Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. + 2 + 1 + read-write + + + DU + Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. + 4 + 1 + read-write + + + CES + Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. + 5 + 1 + read-write + + + NI + Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: +IDINTEN[0]: Transmit Interrupt; +IDINTEN[1]: Receive Interrupt. + 8 + 1 + read-write + + + AI + Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: +IDINTEN[2]: Fatal Bus Error Interrupt; +IDINTEN[4]: DU Interrupt. + 9 + 1 + read-write + + + + + DSCADDR + Host descriptor address pointer + 0x94 + 0x20 + + + DSCADDR + Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC. + 0 + 32 + read-only + + + + + BUFADDR + Host buffer address pointer register + 0x98 + 0x20 + + + BUFADDR + Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC. + 0 + 32 + read-only + + + + + CARDTHRCTL + Card Threshold Control register + 0x100 + 0x20 + + + CARDRDTHREN + Card read threshold enable. +1'b0-Card read threshold disabled. +1'b1-Card read threshold enabled. + 0 + 1 + read-write + + + CARDCLRINTEN + Busy clear interrupt generation: +1'b0-Busy clear interrypt disabled. +1'b1-Busy clear interrypt enabled. + 1 + 1 + read-write + + + CARDWRTHREN + Applicable when HS400 mode is enabled. +1'b0-Card write Threshold disabled. +1'b1-Card write Threshold enabled. + 2 + 1 + read-write + + + CARDTHRESHOLD + The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1. + 16 + 16 + read-write + + + + + EMMCDDR + eMMC DDR register + 0x10C + 0x20 + + + HALFSTARTBIT + Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: +1'b0-Full cycle. +1'b1-less than one full cycle. + 0 + 2 + read-write + + + HS400_MODE + Set 1 to enable HS400 mode. + 31 + 1 + read-write + + + + + ENSHIFT + Enable Phase Shift register + 0x110 + 0x20 + + + ENABLE_SHIFT + Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. +2'b00-Default phase shift. +2'b01-Enables shifted to next immediate positive edge. +2'b10-Enables shifted to next immediate negative edge. +2'b11-Reserved. + 0 + 4 + read-write + + + + + BUFFIFO + CPU write and read transmit data by FIFO + 0x200 + 0x20 + + + BUFFIFO + CPU write and read transmit data by FIFO. This register points to the current Data FIFO . + 0 + 32 + read-write + + + + + CLK_EDGE_SEL + SDIO control register. + 0x800 + 0x20 + 0x00820200 + + + CCLKIN_EDGE_DRV_SEL + It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270. + 0 + 3 + read-write + + + CCLKIN_EDGE_SAM_SEL + It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270. + 3 + 3 + read-write + + + CCLKIN_EDGE_SLF_SEL + It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270. + 6 + 3 + read-write + + + CCLLKIN_EDGE_H + The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + 9 + 4 + read-write + + + CCLLKIN_EDGE_L + The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + 13 + 4 + read-write + + + CCLLKIN_EDGE_N + The clock division of cclk_in. + 17 + 4 + read-write + + + ESDIO_MODE + Enable esdio mode. + 21 + 1 + read-write + + + ESD_MODE + Enable esd mode. + 22 + 1 + read-write + + + CCLK_EN + Sdio clock enable. + 23 + 1 + read-write + + + ULTRA_HIGH_SPEED_MODE + Enable ultra high speed mode, use dll to generate clk. + 24 + 1 + read-write + + + + + RAW_INTS + SDIO raw ints register. + 0x804 + 0x20 + + + RAW_INTS + It indicates raw ints. + 0 + 32 + read-only + + + + + DLL_CLK_CONF + SDIO DLL clock control register. + 0x808 + 0x20 + + + DLL_CCLK_IN_SLF_EN + Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + 0 + 1 + read-write + + + DLL_CCLK_IN_DRV_EN + Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + 1 + 1 + read-write + + + DLL_CCLK_IN_SAM_EN + Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + 2 + 1 + read-write + + + DLL_CCLK_IN_SLF_PHASE + It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + 3 + 6 + read-write + + + DLL_CCLK_IN_DRV_PHASE + It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + 9 + 6 + read-write + + + DLL_CCLK_IN_SAM_PHASE + It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + 15 + 6 + read-write + + + + + DLL_CONF + SDIO DLL configuration register. + 0x80C + 0x20 + + + DLL_CAL_STOP + Set 1 to stop calibration. + 0 + 1 + read-write + + + DLL_CAL_END + 1 means calibration finished. + 1 + 1 + read-only + + + + + + + SHA + SHA (Secure Hash Algorithm) Accelerator + SHA + 0x50091000 + + 0x0 + 0xB0 + registers + + + SHA + 70 + + + + MODE + Initial configuration register. + 0x0 + 0x20 + + + MODE + Sha mode. + 0 + 3 + read-write + + + + + T_STRING + SHA 512/t configuration register 0. + 0x4 + 0x20 + + + T_STRING + Sha t_string (used if and only if mode == SHA_512/t). + 0 + 32 + read-write + + + + + T_LENGTH + SHA 512/t configuration register 1. + 0x8 + 0x20 + + + T_LENGTH + Sha t_length (used if and only if mode == SHA_512/t). + 0 + 6 + read-write + + + + + DMA_BLOCK_NUM + DMA configuration register 0. + 0xC + 0x20 + + + DMA_BLOCK_NUM + Dma-sha block number. + 0 + 6 + read-write + + + + + START + Typical SHA configuration register 0. + 0x10 + 0x20 + + + START + Reserved. + 1 + 31 + read-only + + + + + CONTINUE + Typical SHA configuration register 1. + 0x14 + 0x20 + + + CONTINUE + Reserved. + 1 + 31 + read-only + + + + + BUSY + Busy register. + 0x18 + 0x20 + + + STATE + Sha busy state. 1'b0: idle. 1'b1: busy. + 0 + 1 + read-only + + + + + DMA_START + DMA configuration register 1. + 0x1C + 0x20 + + + DMA_START + Start dma-sha. + 0 + 1 + write-only + + + + + DMA_CONTINUE + DMA configuration register 2. + 0x20 + 0x20 + + + DMA_CONTINUE + Continue dma-sha. + 0 + 1 + write-only + + + + + CLEAR_IRQ + Interrupt clear register. + 0x24 + 0x20 + + + CLEAR_INTERRUPT + Clear sha interrupt. + 0 + 1 + write-only + + + + + IRQ_ENA + Interrupt enable register. + 0x28 + 0x20 + + + INTERRUPT_ENA + Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. + 0 + 1 + read-write + + + + + DATE + Date register. + 0x2C + 0x20 + 0x20201229 + + + DATE + Sha date information/ sha version information. + 0 + 30 + read-write + + + + + 64 + 0x1 + H_MEM[%s] + Sha H memory which contains intermediate hash or finial hash. + 0x40 + 0x8 + + + 64 + 0x1 + M_MEM[%s] + Sha M memory which contains message. + 0x80 + 0x8 + + + + + SOC_ETM + Event Task Matrix + SOC_ETM + 0x500D5000 + + 0x0 + 0x228 + registers + + + + CH_ENA_AD0 + Channel enable status register + 0x0 + 0x20 + + + CH_ENA0 + Represents ch0 enable status.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CH_ENA1 + Represents ch1 enable status.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + CH_ENA2 + Represents ch2 enable status.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + CH_ENA3 + Represents ch3 enable status.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + CH_ENA4 + Represents ch4 enable status.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + CH_ENA5 + Represents ch5 enable status.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + CH_ENA6 + Represents ch6 enable status.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + CH_ENA7 + Represents ch7 enable status.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + CH_ENA8 + Represents ch8 enable status.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + CH_ENA9 + Represents ch9 enable status.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + CH_ENA10 + Represents ch10 enable status.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + CH_ENA11 + Represents ch11 enable status.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + CH_ENA12 + Represents ch12 enable status.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + CH_ENA13 + Represents ch13 enable status.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + CH_ENA14 + Represents ch14 enable status.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + CH_ENA15 + Represents ch15 enable status.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + CH_ENA16 + Represents ch16 enable status.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + CH_ENA17 + Represents ch17 enable status.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + CH_ENA18 + Represents ch18 enable status.\\0: Disable\\1: Enable + 18 + 1 + read-write + + + CH_ENA19 + Represents ch19 enable status.\\0: Disable\\1: Enable + 19 + 1 + read-write + + + CH_ENA20 + Represents ch20 enable status.\\0: Disable\\1: Enable + 20 + 1 + read-write + + + CH_ENA21 + Represents ch21 enable status.\\0: Disable\\1: Enable + 21 + 1 + read-write + + + CH_ENA22 + Represents ch22 enable status.\\0: Disable\\1: Enable + 22 + 1 + read-write + + + CH_ENA23 + Represents ch23 enable status.\\0: Disable\\1: Enable + 23 + 1 + read-write + + + CH_ENA24 + Represents ch24 enable status.\\0: Disable\\1: Enable + 24 + 1 + read-write + + + CH_ENA25 + Represents ch25 enable status.\\0: Disable\\1: Enable + 25 + 1 + read-write + + + CH_ENA26 + Represents ch26 enable status.\\0: Disable\\1: Enable + 26 + 1 + read-write + + + CH_ENA27 + Represents ch27 enable status.\\0: Disable\\1: Enable + 27 + 1 + read-write + + + CH_ENA28 + Represents ch28 enable status.\\0: Disable\\1: Enable + 28 + 1 + read-write + + + CH_ENA29 + Represents ch29 enable status.\\0: Disable\\1: Enable + 29 + 1 + read-write + + + CH_ENA30 + Represents ch30 enable status.\\0: Disable\\1: Enable + 30 + 1 + read-write + + + CH_ENA31 + Represents ch31 enable status.\\0: Disable\\1: Enable + 31 + 1 + read-write + + + + + CH_ENA_AD0_SET + Channel enable set register + 0x4 + 0x20 + + + CH_SET0 + Configures whether or not to enable ch0.\\0: Invalid, No effect\\1: Enable + 0 + 1 + write-only + + + CH_SET1 + Configures whether or not to enable ch1.\\0: Invalid, No effect\\1: Enable + 1 + 1 + write-only + + + CH_SET2 + Configures whether or not to enable ch2.\\0: Invalid, No effect\\1: Enable + 2 + 1 + write-only + + + CH_SET3 + Configures whether or not to enable ch3.\\0: Invalid, No effect\\1: Enable + 3 + 1 + write-only + + + CH_SET4 + Configures whether or not to enable ch4.\\0: Invalid, No effect\\1: Enable + 4 + 1 + write-only + + + CH_SET5 + Configures whether or not to enable ch5.\\0: Invalid, No effect\\1: Enable + 5 + 1 + write-only + + + CH_SET6 + Configures whether or not to enable ch6.\\0: Invalid, No effect\\1: Enable + 6 + 1 + write-only + + + CH_SET7 + Configures whether or not to enable ch7.\\0: Invalid, No effect\\1: Enable + 7 + 1 + write-only + + + CH_SET8 + Configures whether or not to enable ch8.\\0: Invalid, No effect\\1: Enable + 8 + 1 + write-only + + + CH_SET9 + Configures whether or not to enable ch9.\\0: Invalid, No effect\\1: Enable + 9 + 1 + write-only + + + CH_SET10 + Configures whether or not to enable ch10.\\0: Invalid, No effect\\1: Enable + 10 + 1 + write-only + + + CH_SET11 + Configures whether or not to enable ch11.\\0: Invalid, No effect\\1: Enable + 11 + 1 + write-only + + + CH_SET12 + Configures whether or not to enable ch12.\\0: Invalid, No effect\\1: Enable + 12 + 1 + write-only + + + CH_SET13 + Configures whether or not to enable ch13.\\0: Invalid, No effect\\1: Enable + 13 + 1 + write-only + + + CH_SET14 + Configures whether or not to enable ch14.\\0: Invalid, No effect\\1: Enable + 14 + 1 + write-only + + + CH_SET15 + Configures whether or not to enable ch15.\\0: Invalid, No effect\\1: Enable + 15 + 1 + write-only + + + CH_SET16 + Configures whether or not to enable ch16.\\0: Invalid, No effect\\1: Enable + 16 + 1 + write-only + + + CH_SET17 + Configures whether or not to enable ch17.\\0: Invalid, No effect\\1: Enable + 17 + 1 + write-only + + + CH_SET18 + Configures whether or not to enable ch18.\\0: Invalid, No effect\\1: Enable + 18 + 1 + write-only + + + CH_SET19 + Configures whether or not to enable ch19.\\0: Invalid, No effect\\1: Enable + 19 + 1 + write-only + + + CH_SET20 + Configures whether or not to enable ch20.\\0: Invalid, No effect\\1: Enable + 20 + 1 + write-only + + + CH_SET21 + Configures whether or not to enable ch21.\\0: Invalid, No effect\\1: Enable + 21 + 1 + write-only + + + CH_SET22 + Configures whether or not to enable ch22.\\0: Invalid, No effect\\1: Enable + 22 + 1 + write-only + + + CH_SET23 + Configures whether or not to enable ch23.\\0: Invalid, No effect\\1: Enable + 23 + 1 + write-only + + + CH_SET24 + Configures whether or not to enable ch24.\\0: Invalid, No effect\\1: Enable + 24 + 1 + write-only + + + CH_SET25 + Configures whether or not to enable ch25.\\0: Invalid, No effect\\1: Enable + 25 + 1 + write-only + + + CH_SET26 + Configures whether or not to enable ch26.\\0: Invalid, No effect\\1: Enable + 26 + 1 + write-only + + + CH_SET27 + Configures whether or not to enable ch27.\\0: Invalid, No effect\\1: Enable + 27 + 1 + write-only + + + CH_SET28 + Configures whether or not to enable ch28.\\0: Invalid, No effect\\1: Enable + 28 + 1 + write-only + + + CH_SET29 + Configures whether or not to enable ch29.\\0: Invalid, No effect\\1: Enable + 29 + 1 + write-only + + + CH_SET30 + Configures whether or not to enable ch30.\\0: Invalid, No effect\\1: Enable + 30 + 1 + write-only + + + CH_SET31 + Configures whether or not to enable ch31.\\0: Invalid, No effect\\1: Enable + 31 + 1 + write-only + + + + + CH_ENA_AD0_CLR + Channel enable clear register + 0x8 + 0x20 + + + CH_CLR0 + Configures whether or not to clear ch0 enable.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + CH_CLR1 + Configures whether or not to clear ch1 enable.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + CH_CLR2 + Configures whether or not to clear ch2 enable.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + CH_CLR3 + Configures whether or not to clear ch3 enable.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + CH_CLR4 + Configures whether or not to clear ch4 enable.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + CH_CLR5 + Configures whether or not to clear ch5 enable.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + CH_CLR6 + Configures whether or not to clear ch6 enable.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + CH_CLR7 + Configures whether or not to clear ch7 enable.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + CH_CLR8 + Configures whether or not to clear ch8 enable.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + CH_CLR9 + Configures whether or not to clear ch9 enable.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + CH_CLR10 + Configures whether or not to clear ch10 enable.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + CH_CLR11 + Configures whether or not to clear ch11 enable.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + CH_CLR12 + Configures whether or not to clear ch12 enable.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + CH_CLR13 + Configures whether or not to clear ch13 enable.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + CH_CLR14 + Configures whether or not to clear ch14 enable.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + CH_CLR15 + Configures whether or not to clear ch15 enable.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + CH_CLR16 + Configures whether or not to clear ch16 enable.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + CH_CLR17 + Configures whether or not to clear ch17 enable.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + CH_CLR18 + Configures whether or not to clear ch18 enable.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + CH_CLR19 + Configures whether or not to clear ch19 enable.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + CH_CLR20 + Configures whether or not to clear ch20 enable.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + CH_CLR21 + Configures whether or not to clear ch21 enable.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + CH_CLR22 + Configures whether or not to clear ch22 enable.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + CH_CLR23 + Configures whether or not to clear ch23 enable.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + CH_CLR24 + Configures whether or not to clear ch24 enable.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + CH_CLR25 + Configures whether or not to clear ch25 enable.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + CH_CLR26 + Configures whether or not to clear ch26 enable.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + CH_CLR27 + Configures whether or not to clear ch27 enable.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + CH_CLR28 + Configures whether or not to clear ch28 enable.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + CH_CLR29 + Configures whether or not to clear ch29 enable.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + CH_CLR30 + Configures whether or not to clear ch30 enable.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + CH_CLR31 + Configures whether or not to clear ch31 enable.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + CH_ENA_AD1 + Channel enable status register + 0xC + 0x20 + + + CH_ENA32 + Represents ch32 enable status.\\0: Disable\\1: Enable + 0 + 1 + read-write + + + CH_ENA33 + Represents ch33 enable status.\\0: Disable\\1: Enable + 1 + 1 + read-write + + + CH_ENA34 + Represents ch34 enable status.\\0: Disable\\1: Enable + 2 + 1 + read-write + + + CH_ENA35 + Represents ch35 enable status.\\0: Disable\\1: Enable + 3 + 1 + read-write + + + CH_ENA36 + Represents ch36 enable status.\\0: Disable\\1: Enable + 4 + 1 + read-write + + + CH_ENA37 + Represents ch37 enable status.\\0: Disable\\1: Enable + 5 + 1 + read-write + + + CH_ENA38 + Represents ch38 enable status.\\0: Disable\\1: Enable + 6 + 1 + read-write + + + CH_ENA39 + Represents ch39 enable status.\\0: Disable\\1: Enable + 7 + 1 + read-write + + + CH_ENA40 + Represents ch40 enable status.\\0: Disable\\1: Enable + 8 + 1 + read-write + + + CH_ENA41 + Represents ch41 enable status.\\0: Disable\\1: Enable + 9 + 1 + read-write + + + CH_ENA42 + Represents ch42 enable status.\\0: Disable\\1: Enable + 10 + 1 + read-write + + + CH_ENA43 + Represents ch43 enable status.\\0: Disable\\1: Enable + 11 + 1 + read-write + + + CH_ENA44 + Represents ch44 enable status.\\0: Disable\\1: Enable + 12 + 1 + read-write + + + CH_ENA45 + Represents ch45 enable status.\\0: Disable\\1: Enable + 13 + 1 + read-write + + + CH_ENA46 + Represents ch46 enable status.\\0: Disable\\1: Enable + 14 + 1 + read-write + + + CH_ENA47 + Represents ch47 enable status.\\0: Disable\\1: Enable + 15 + 1 + read-write + + + CH_ENA48 + Represents ch48 enable status.\\0: Disable\\1: Enable + 16 + 1 + read-write + + + CH_ENA49 + Represents ch49 enable status.\\0: Disable\\1: Enable + 17 + 1 + read-write + + + + + CH_ENA_AD1_SET + Channel enable set register + 0x10 + 0x20 + + + CH_SET32 + Configures whether or not to enable ch32.\\0: Invalid, No effect\\1: Enable + 0 + 1 + write-only + + + CH_SET33 + Configures whether or not to enable ch33.\\0: Invalid, No effect\\1: Enable + 1 + 1 + write-only + + + CH_SET34 + Configures whether or not to enable ch34.\\0: Invalid, No effect\\1: Enable + 2 + 1 + write-only + + + CH_SET35 + Configures whether or not to enable ch35.\\0: Invalid, No effect\\1: Enable + 3 + 1 + write-only + + + CH_SET36 + Configures whether or not to enable ch36.\\0: Invalid, No effect\\1: Enable + 4 + 1 + write-only + + + CH_SET37 + Configures whether or not to enable ch37.\\0: Invalid, No effect\\1: Enable + 5 + 1 + write-only + + + CH_SET38 + Configures whether or not to enable ch38.\\0: Invalid, No effect\\1: Enable + 6 + 1 + write-only + + + CH_SET39 + Configures whether or not to enable ch39.\\0: Invalid, No effect\\1: Enable + 7 + 1 + write-only + + + CH_SET40 + Configures whether or not to enable ch40.\\0: Invalid, No effect\\1: Enable + 8 + 1 + write-only + + + CH_SET41 + Configures whether or not to enable ch41.\\0: Invalid, No effect\\1: Enable + 9 + 1 + write-only + + + CH_SET42 + Configures whether or not to enable ch42.\\0: Invalid, No effect\\1: Enable + 10 + 1 + write-only + + + CH_SET43 + Configures whether or not to enable ch43.\\0: Invalid, No effect\\1: Enable + 11 + 1 + write-only + + + CH_SET44 + Configures whether or not to enable ch44.\\0: Invalid, No effect\\1: Enable + 12 + 1 + write-only + + + CH_SET45 + Configures whether or not to enable ch45.\\0: Invalid, No effect\\1: Enable + 13 + 1 + write-only + + + CH_SET46 + Configures whether or not to enable ch46.\\0: Invalid, No effect\\1: Enable + 14 + 1 + write-only + + + CH_SET47 + Configures whether or not to enable ch47.\\0: Invalid, No effect\\1: Enable + 15 + 1 + write-only + + + CH_SET48 + Configures whether or not to enable ch48.\\0: Invalid, No effect\\1: Enable + 16 + 1 + write-only + + + CH_SET49 + Configures whether or not to enable ch49.\\0: Invalid, No effect\\1: Enable + 17 + 1 + write-only + + + + + CH_ENA_AD1_CLR + Channel enable clear register + 0x14 + 0x20 + + + CH_CLR32 + Configures whether or not to clear ch32 enable.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + CH_CLR33 + Configures whether or not to clear ch33 enable.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + CH_CLR34 + Configures whether or not to clear ch34 enable.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + CH_CLR35 + Configures whether or not to clear ch35 enable.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + CH_CLR36 + Configures whether or not to clear ch36 enable.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + CH_CLR37 + Configures whether or not to clear ch37 enable.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + CH_CLR38 + Configures whether or not to clear ch38 enable.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + CH_CLR39 + Configures whether or not to clear ch39 enable.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + CH_CLR40 + Configures whether or not to clear ch40 enable.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + CH_CLR41 + Configures whether or not to clear ch41 enable.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + CH_CLR42 + Configures whether or not to clear ch42 enable.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + CH_CLR43 + Configures whether or not to clear ch43 enable.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + CH_CLR44 + Configures whether or not to clear ch44 enable.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + CH_CLR45 + Configures whether or not to clear ch45 enable.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + CH_CLR46 + Configures whether or not to clear ch46 enable.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + CH_CLR47 + Configures whether or not to clear ch47 enable.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + CH_CLR48 + Configures whether or not to clear ch48 enable.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + CH_CLR49 + Configures whether or not to clear ch49 enable.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + + + CH0_EVT_ID + Channel0 event id register + 0x18 + 0x20 + + + CH0_EVT_ID + Configures ch0_evt_id + 0 + 8 + read-write + + + + + CH0_TASK_ID + Channel0 task id register + 0x1C + 0x20 + + + CH0_TASK_ID + Configures ch0_task_id + 0 + 8 + read-write + + + + + CH1_EVT_ID + Channel1 event id register + 0x20 + 0x20 + + + CH1_EVT_ID + Configures ch1_evt_id + 0 + 8 + read-write + + + + + CH1_TASK_ID + Channel1 task id register + 0x24 + 0x20 + + + CH1_TASK_ID + Configures ch1_task_id + 0 + 8 + read-write + + + + + CH2_EVT_ID + Channel2 event id register + 0x28 + 0x20 + + + CH2_EVT_ID + Configures ch2_evt_id + 0 + 8 + read-write + + + + + CH2_TASK_ID + Channel2 task id register + 0x2C + 0x20 + + + CH2_TASK_ID + Configures ch2_task_id + 0 + 8 + read-write + + + + + CH3_EVT_ID + Channel3 event id register + 0x30 + 0x20 + + + CH3_EVT_ID + Configures ch3_evt_id + 0 + 8 + read-write + + + + + CH3_TASK_ID + Channel3 task id register + 0x34 + 0x20 + + + CH3_TASK_ID + Configures ch3_task_id + 0 + 8 + read-write + + + + + CH4_EVT_ID + Channel4 event id register + 0x38 + 0x20 + + + CH4_EVT_ID + Configures ch4_evt_id + 0 + 8 + read-write + + + + + CH4_TASK_ID + Channel4 task id register + 0x3C + 0x20 + + + CH4_TASK_ID + Configures ch4_task_id + 0 + 8 + read-write + + + + + CH5_EVT_ID + Channel5 event id register + 0x40 + 0x20 + + + CH5_EVT_ID + Configures ch5_evt_id + 0 + 8 + read-write + + + + + CH5_TASK_ID + Channel5 task id register + 0x44 + 0x20 + + + CH5_TASK_ID + Configures ch5_task_id + 0 + 8 + read-write + + + + + CH6_EVT_ID + Channel6 event id register + 0x48 + 0x20 + + + CH6_EVT_ID + Configures ch6_evt_id + 0 + 8 + read-write + + + + + CH6_TASK_ID + Channel6 task id register + 0x4C + 0x20 + + + CH6_TASK_ID + Configures ch6_task_id + 0 + 8 + read-write + + + + + CH7_EVT_ID + Channel7 event id register + 0x50 + 0x20 + + + CH7_EVT_ID + Configures ch7_evt_id + 0 + 8 + read-write + + + + + CH7_TASK_ID + Channel7 task id register + 0x54 + 0x20 + + + CH7_TASK_ID + Configures ch7_task_id + 0 + 8 + read-write + + + + + CH8_EVT_ID + Channel8 event id register + 0x58 + 0x20 + + + CH8_EVT_ID + Configures ch8_evt_id + 0 + 8 + read-write + + + + + CH8_TASK_ID + Channel8 task id register + 0x5C + 0x20 + + + CH8_TASK_ID + Configures ch8_task_id + 0 + 8 + read-write + + + + + CH9_EVT_ID + Channel9 event id register + 0x60 + 0x20 + + + CH9_EVT_ID + Configures ch9_evt_id + 0 + 8 + read-write + + + + + CH9_TASK_ID + Channel9 task id register + 0x64 + 0x20 + + + CH9_TASK_ID + Configures ch9_task_id + 0 + 8 + read-write + + + + + CH10_EVT_ID + Channel10 event id register + 0x68 + 0x20 + + + CH10_EVT_ID + Configures ch10_evt_id + 0 + 8 + read-write + + + + + CH10_TASK_ID + Channel10 task id register + 0x6C + 0x20 + + + CH10_TASK_ID + Configures ch10_task_id + 0 + 8 + read-write + + + + + CH11_EVT_ID + Channel11 event id register + 0x70 + 0x20 + + + CH11_EVT_ID + Configures ch11_evt_id + 0 + 8 + read-write + + + + + CH11_TASK_ID + Channel11 task id register + 0x74 + 0x20 + + + CH11_TASK_ID + Configures ch11_task_id + 0 + 8 + read-write + + + + + CH12_EVT_ID + Channel12 event id register + 0x78 + 0x20 + + + CH12_EVT_ID + Configures ch12_evt_id + 0 + 8 + read-write + + + + + CH12_TASK_ID + Channel12 task id register + 0x7C + 0x20 + + + CH12_TASK_ID + Configures ch12_task_id + 0 + 8 + read-write + + + + + CH13_EVT_ID + Channel13 event id register + 0x80 + 0x20 + + + CH13_EVT_ID + Configures ch13_evt_id + 0 + 8 + read-write + + + + + CH13_TASK_ID + Channel13 task id register + 0x84 + 0x20 + + + CH13_TASK_ID + Configures ch13_task_id + 0 + 8 + read-write + + + + + CH14_EVT_ID + Channel14 event id register + 0x88 + 0x20 + + + CH14_EVT_ID + Configures ch14_evt_id + 0 + 8 + read-write + + + + + CH14_TASK_ID + Channel14 task id register + 0x8C + 0x20 + + + CH14_TASK_ID + Configures ch14_task_id + 0 + 8 + read-write + + + + + CH15_EVT_ID + Channel15 event id register + 0x90 + 0x20 + + + CH15_EVT_ID + Configures ch15_evt_id + 0 + 8 + read-write + + + + + CH15_TASK_ID + Channel15 task id register + 0x94 + 0x20 + + + CH15_TASK_ID + Configures ch15_task_id + 0 + 8 + read-write + + + + + CH16_EVT_ID + Channel16 event id register + 0x98 + 0x20 + + + CH16_EVT_ID + Configures ch16_evt_id + 0 + 8 + read-write + + + + + CH16_TASK_ID + Channel16 task id register + 0x9C + 0x20 + + + CH16_TASK_ID + Configures ch16_task_id + 0 + 8 + read-write + + + + + CH17_EVT_ID + Channel17 event id register + 0xA0 + 0x20 + + + CH17_EVT_ID + Configures ch17_evt_id + 0 + 8 + read-write + + + + + CH17_TASK_ID + Channel17 task id register + 0xA4 + 0x20 + + + CH17_TASK_ID + Configures ch17_task_id + 0 + 8 + read-write + + + + + CH18_EVT_ID + Channel18 event id register + 0xA8 + 0x20 + + + CH18_EVT_ID + Configures ch18_evt_id + 0 + 8 + read-write + + + + + CH18_TASK_ID + Channel18 task id register + 0xAC + 0x20 + + + CH18_TASK_ID + Configures ch18_task_id + 0 + 8 + read-write + + + + + CH19_EVT_ID + Channel19 event id register + 0xB0 + 0x20 + + + CH19_EVT_ID + Configures ch19_evt_id + 0 + 8 + read-write + + + + + CH19_TASK_ID + Channel19 task id register + 0xB4 + 0x20 + + + CH19_TASK_ID + Configures ch19_task_id + 0 + 8 + read-write + + + + + CH20_EVT_ID + Channel20 event id register + 0xB8 + 0x20 + + + CH20_EVT_ID + Configures ch20_evt_id + 0 + 8 + read-write + + + + + CH20_TASK_ID + Channel20 task id register + 0xBC + 0x20 + + + CH20_TASK_ID + Configures ch20_task_id + 0 + 8 + read-write + + + + + CH21_EVT_ID + Channel21 event id register + 0xC0 + 0x20 + + + CH21_EVT_ID + Configures ch21_evt_id + 0 + 8 + read-write + + + + + CH21_TASK_ID + Channel21 task id register + 0xC4 + 0x20 + + + CH21_TASK_ID + Configures ch21_task_id + 0 + 8 + read-write + + + + + CH22_EVT_ID + Channel22 event id register + 0xC8 + 0x20 + + + CH22_EVT_ID + Configures ch22_evt_id + 0 + 8 + read-write + + + + + CH22_TASK_ID + Channel22 task id register + 0xCC + 0x20 + + + CH22_TASK_ID + Configures ch22_task_id + 0 + 8 + read-write + + + + + CH23_EVT_ID + Channel23 event id register + 0xD0 + 0x20 + + + CH23_EVT_ID + Configures ch23_evt_id + 0 + 8 + read-write + + + + + CH23_TASK_ID + Channel23 task id register + 0xD4 + 0x20 + + + CH23_TASK_ID + Configures ch23_task_id + 0 + 8 + read-write + + + + + CH24_EVT_ID + Channel24 event id register + 0xD8 + 0x20 + + + CH24_EVT_ID + Configures ch24_evt_id + 0 + 8 + read-write + + + + + CH24_TASK_ID + Channel24 task id register + 0xDC + 0x20 + + + CH24_TASK_ID + Configures ch24_task_id + 0 + 8 + read-write + + + + + CH25_EVT_ID + Channel25 event id register + 0xE0 + 0x20 + + + CH25_EVT_ID + Configures ch25_evt_id + 0 + 8 + read-write + + + + + CH25_TASK_ID + Channel25 task id register + 0xE4 + 0x20 + + + CH25_TASK_ID + Configures ch25_task_id + 0 + 8 + read-write + + + + + CH26_EVT_ID + Channel26 event id register + 0xE8 + 0x20 + + + CH26_EVT_ID + Configures ch26_evt_id + 0 + 8 + read-write + + + + + CH26_TASK_ID + Channel26 task id register + 0xEC + 0x20 + + + CH26_TASK_ID + Configures ch26_task_id + 0 + 8 + read-write + + + + + CH27_EVT_ID + Channel27 event id register + 0xF0 + 0x20 + + + CH27_EVT_ID + Configures ch27_evt_id + 0 + 8 + read-write + + + + + CH27_TASK_ID + Channel27 task id register + 0xF4 + 0x20 + + + CH27_TASK_ID + Configures ch27_task_id + 0 + 8 + read-write + + + + + CH28_EVT_ID + Channel28 event id register + 0xF8 + 0x20 + + + CH28_EVT_ID + Configures ch28_evt_id + 0 + 8 + read-write + + + + + CH28_TASK_ID + Channel28 task id register + 0xFC + 0x20 + + + CH28_TASK_ID + Configures ch28_task_id + 0 + 8 + read-write + + + + + CH29_EVT_ID + Channel29 event id register + 0x100 + 0x20 + + + CH29_EVT_ID + Configures ch29_evt_id + 0 + 8 + read-write + + + + + CH29_TASK_ID + Channel29 task id register + 0x104 + 0x20 + + + CH29_TASK_ID + Configures ch29_task_id + 0 + 8 + read-write + + + + + CH30_EVT_ID + Channel30 event id register + 0x108 + 0x20 + + + CH30_EVT_ID + Configures ch30_evt_id + 0 + 8 + read-write + + + + + CH30_TASK_ID + Channel30 task id register + 0x10C + 0x20 + + + CH30_TASK_ID + Configures ch30_task_id + 0 + 8 + read-write + + + + + CH31_EVT_ID + Channel31 event id register + 0x110 + 0x20 + + + CH31_EVT_ID + Configures ch31_evt_id + 0 + 8 + read-write + + + + + CH31_TASK_ID + Channel31 task id register + 0x114 + 0x20 + + + CH31_TASK_ID + Configures ch31_task_id + 0 + 8 + read-write + + + + + CH32_EVT_ID + Channel32 event id register + 0x118 + 0x20 + + + CH32_EVT_ID + Configures ch32_evt_id + 0 + 8 + read-write + + + + + CH32_TASK_ID + Channel32 task id register + 0x11C + 0x20 + + + CH32_TASK_ID + Configures ch32_task_id + 0 + 8 + read-write + + + + + CH33_EVT_ID + Channel33 event id register + 0x120 + 0x20 + + + CH33_EVT_ID + Configures ch33_evt_id + 0 + 8 + read-write + + + + + CH33_TASK_ID + Channel33 task id register + 0x124 + 0x20 + + + CH33_TASK_ID + Configures ch33_task_id + 0 + 8 + read-write + + + + + CH34_EVT_ID + Channel34 event id register + 0x128 + 0x20 + + + CH34_EVT_ID + Configures ch34_evt_id + 0 + 8 + read-write + + + + + CH34_TASK_ID + Channel34 task id register + 0x12C + 0x20 + + + CH34_TASK_ID + Configures ch34_task_id + 0 + 8 + read-write + + + + + CH35_EVT_ID + Channel35 event id register + 0x130 + 0x20 + + + CH35_EVT_ID + Configures ch35_evt_id + 0 + 8 + read-write + + + + + CH35_TASK_ID + Channel35 task id register + 0x134 + 0x20 + + + CH35_TASK_ID + Configures ch35_task_id + 0 + 8 + read-write + + + + + CH36_EVT_ID + Channel36 event id register + 0x138 + 0x20 + + + CH36_EVT_ID + Configures ch36_evt_id + 0 + 8 + read-write + + + + + CH36_TASK_ID + Channel36 task id register + 0x13C + 0x20 + + + CH36_TASK_ID + Configures ch36_task_id + 0 + 8 + read-write + + + + + CH37_EVT_ID + Channel37 event id register + 0x140 + 0x20 + + + CH37_EVT_ID + Configures ch37_evt_id + 0 + 8 + read-write + + + + + CH37_TASK_ID + Channel37 task id register + 0x144 + 0x20 + + + CH37_TASK_ID + Configures ch37_task_id + 0 + 8 + read-write + + + + + CH38_EVT_ID + Channel38 event id register + 0x148 + 0x20 + + + CH38_EVT_ID + Configures ch38_evt_id + 0 + 8 + read-write + + + + + CH38_TASK_ID + Channel38 task id register + 0x14C + 0x20 + + + CH38_TASK_ID + Configures ch38_task_id + 0 + 8 + read-write + + + + + CH39_EVT_ID + Channel39 event id register + 0x150 + 0x20 + + + CH39_EVT_ID + Configures ch39_evt_id + 0 + 8 + read-write + + + + + CH39_TASK_ID + Channel39 task id register + 0x154 + 0x20 + + + CH39_TASK_ID + Configures ch39_task_id + 0 + 8 + read-write + + + + + CH40_EVT_ID + Channel40 event id register + 0x158 + 0x20 + + + CH40_EVT_ID + Configures ch40_evt_id + 0 + 8 + read-write + + + + + CH40_TASK_ID + Channel40 task id register + 0x15C + 0x20 + + + CH40_TASK_ID + Configures ch40_task_id + 0 + 8 + read-write + + + + + CH41_EVT_ID + Channel41 event id register + 0x160 + 0x20 + + + CH41_EVT_ID + Configures ch41_evt_id + 0 + 8 + read-write + + + + + CH41_TASK_ID + Channel41 task id register + 0x164 + 0x20 + + + CH41_TASK_ID + Configures ch41_task_id + 0 + 8 + read-write + + + + + CH42_EVT_ID + Channel42 event id register + 0x168 + 0x20 + + + CH42_EVT_ID + Configures ch42_evt_id + 0 + 8 + read-write + + + + + CH42_TASK_ID + Channel42 task id register + 0x16C + 0x20 + + + CH42_TASK_ID + Configures ch42_task_id + 0 + 8 + read-write + + + + + CH43_EVT_ID + Channel43 event id register + 0x170 + 0x20 + + + CH43_EVT_ID + Configures ch43_evt_id + 0 + 8 + read-write + + + + + CH43_TASK_ID + Channel43 task id register + 0x174 + 0x20 + + + CH43_TASK_ID + Configures ch43_task_id + 0 + 8 + read-write + + + + + CH44_EVT_ID + Channel44 event id register + 0x178 + 0x20 + + + CH44_EVT_ID + Configures ch44_evt_id + 0 + 8 + read-write + + + + + CH44_TASK_ID + Channel44 task id register + 0x17C + 0x20 + + + CH44_TASK_ID + Configures ch44_task_id + 0 + 8 + read-write + + + + + CH45_EVT_ID + Channel45 event id register + 0x180 + 0x20 + + + CH45_EVT_ID + Configures ch45_evt_id + 0 + 8 + read-write + + + + + CH45_TASK_ID + Channel45 task id register + 0x184 + 0x20 + + + CH45_TASK_ID + Configures ch45_task_id + 0 + 8 + read-write + + + + + CH46_EVT_ID + Channel46 event id register + 0x188 + 0x20 + + + CH46_EVT_ID + Configures ch46_evt_id + 0 + 8 + read-write + + + + + CH46_TASK_ID + Channel46 task id register + 0x18C + 0x20 + + + CH46_TASK_ID + Configures ch46_task_id + 0 + 8 + read-write + + + + + CH47_EVT_ID + Channel47 event id register + 0x190 + 0x20 + + + CH47_EVT_ID + Configures ch47_evt_id + 0 + 8 + read-write + + + + + CH47_TASK_ID + Channel47 task id register + 0x194 + 0x20 + + + CH47_TASK_ID + Configures ch47_task_id + 0 + 8 + read-write + + + + + CH48_EVT_ID + Channel48 event id register + 0x198 + 0x20 + + + CH48_EVT_ID + Configures ch48_evt_id + 0 + 8 + read-write + + + + + CH48_TASK_ID + Channel48 task id register + 0x19C + 0x20 + + + CH48_TASK_ID + Configures ch48_task_id + 0 + 8 + read-write + + + + + CH49_EVT_ID + Channel49 event id register + 0x1A0 + 0x20 + + + CH49_EVT_ID + Configures ch49_evt_id + 0 + 8 + read-write + + + + + CH49_TASK_ID + Channel49 task id register + 0x1A4 + 0x20 + + + CH49_TASK_ID + Configures ch49_task_id + 0 + 8 + read-write + + + + + EVT_ST0 + Events trigger status register + 0x1A8 + 0x20 + + + GPIO_EVT_CH0_RISE_EDGE_ST + Represents GPIO_evt_ch0_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + GPIO_EVT_CH1_RISE_EDGE_ST + Represents GPIO_evt_ch1_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + GPIO_EVT_CH2_RISE_EDGE_ST + Represents GPIO_evt_ch2_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + GPIO_EVT_CH3_RISE_EDGE_ST + Represents GPIO_evt_ch3_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + GPIO_EVT_CH4_RISE_EDGE_ST + Represents GPIO_evt_ch4_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + GPIO_EVT_CH5_RISE_EDGE_ST + Represents GPIO_evt_ch5_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + GPIO_EVT_CH6_RISE_EDGE_ST + Represents GPIO_evt_ch6_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + GPIO_EVT_CH7_RISE_EDGE_ST + Represents GPIO_evt_ch7_rise_edge trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + GPIO_EVT_CH0_FALL_EDGE_ST + Represents GPIO_evt_ch0_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + GPIO_EVT_CH1_FALL_EDGE_ST + Represents GPIO_evt_ch1_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + GPIO_EVT_CH2_FALL_EDGE_ST + Represents GPIO_evt_ch2_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + GPIO_EVT_CH3_FALL_EDGE_ST + Represents GPIO_evt_ch3_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + GPIO_EVT_CH4_FALL_EDGE_ST + Represents GPIO_evt_ch4_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + GPIO_EVT_CH5_FALL_EDGE_ST + Represents GPIO_evt_ch5_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + GPIO_EVT_CH6_FALL_EDGE_ST + Represents GPIO_evt_ch6_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + GPIO_EVT_CH7_FALL_EDGE_ST + Represents GPIO_evt_ch7_fall_edge trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + GPIO_EVT_CH0_ANY_EDGE_ST + Represents GPIO_evt_ch0_any_edge trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + GPIO_EVT_CH1_ANY_EDGE_ST + Represents GPIO_evt_ch1_any_edge trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + GPIO_EVT_CH2_ANY_EDGE_ST + Represents GPIO_evt_ch2_any_edge trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + GPIO_EVT_CH3_ANY_EDGE_ST + Represents GPIO_evt_ch3_any_edge trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + GPIO_EVT_CH4_ANY_EDGE_ST + Represents GPIO_evt_ch4_any_edge trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + GPIO_EVT_CH5_ANY_EDGE_ST + Represents GPIO_evt_ch5_any_edge trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + GPIO_EVT_CH6_ANY_EDGE_ST + Represents GPIO_evt_ch6_any_edge trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + GPIO_EVT_CH7_ANY_EDGE_ST + Represents GPIO_evt_ch7_any_edge trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + GPIO_EVT_ZERO_DET_POS0_ST + Represents GPIO_evt_zero_det_pos0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + GPIO_EVT_ZERO_DET_NEG0_ST + Represents GPIO_evt_zero_det_neg0 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + GPIO_EVT_ZERO_DET_POS1_ST + Represents GPIO_evt_zero_det_pos1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + GPIO_EVT_ZERO_DET_NEG1_ST + Represents GPIO_evt_zero_det_neg1 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH0_ST + Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH1_ST + Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH2_ST + Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH3_ST + Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST0_CLR + Events trigger status clear register + 0x1AC + 0x20 + + + GPIO_EVT_CH0_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + GPIO_EVT_CH1_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + GPIO_EVT_CH2_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + GPIO_EVT_CH3_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + GPIO_EVT_CH4_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + GPIO_EVT_CH5_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + GPIO_EVT_CH6_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + GPIO_EVT_CH7_RISE_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + GPIO_EVT_CH0_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + GPIO_EVT_CH1_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + GPIO_EVT_CH2_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + GPIO_EVT_CH3_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + GPIO_EVT_CH4_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + GPIO_EVT_CH5_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + GPIO_EVT_CH6_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + GPIO_EVT_CH7_FALL_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + GPIO_EVT_CH0_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + GPIO_EVT_CH1_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + GPIO_EVT_CH2_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + GPIO_EVT_CH3_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + GPIO_EVT_CH4_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + GPIO_EVT_CH5_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + GPIO_EVT_CH6_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + GPIO_EVT_CH7_ANY_EDGE_ST_CLR + Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + GPIO_EVT_ZERO_DET_POS0_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + GPIO_EVT_ZERO_DET_NEG0_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + GPIO_EVT_ZERO_DET_POS1_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + GPIO_EVT_ZERO_DET_NEG1_ST_CLR + Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST1 + Events trigger status register + 0x1B0 + 0x20 + + + LEDC_EVT_DUTY_CHNG_END_CH4_ST + Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH5_ST + Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH6_ST + Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + LEDC_EVT_DUTY_CHNG_END_CH7_ST + Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH0_ST + Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH1_ST + Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH2_ST + Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH3_ST + Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH4_ST + Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH5_ST + Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH6_ST + Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + LEDC_EVT_OVF_CNT_PLS_CH7_ST + Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER0_ST + Represents LEDC_evt_time_ovf_timer0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER1_ST + Represents LEDC_evt_time_ovf_timer1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER2_ST + Represents LEDC_evt_time_ovf_timer2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + LEDC_EVT_TIME_OVF_TIMER3_ST + Represents LEDC_evt_time_ovf_timer3 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + LEDC_EVT_TIMER0_CMP_ST + Represents LEDC_evt_timer0_cmp trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + LEDC_EVT_TIMER1_CMP_ST + Represents LEDC_evt_timer1_cmp trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + LEDC_EVT_TIMER2_CMP_ST + Represents LEDC_evt_timer2_cmp trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + LEDC_EVT_TIMER3_CMP_ST + Represents LEDC_evt_timer3_cmp trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + TG0_EVT_CNT_CMP_TIMER0_ST + Represents TG0_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + TG0_EVT_CNT_CMP_TIMER1_ST + Represents TG0_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + TG1_EVT_CNT_CMP_TIMER0_ST + Represents TG1_evt_cnt_cmp_timer0 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + TG1_EVT_CNT_CMP_TIMER1_ST + Represents TG1_evt_cnt_cmp_timer1 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + SYSTIMER_EVT_CNT_CMP0_ST + Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + SYSTIMER_EVT_CNT_CMP1_ST + Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + SYSTIMER_EVT_CNT_CMP2_ST + Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM0_EVT_TIMER0_STOP_ST + Represents MCPWM0_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM0_EVT_TIMER1_STOP_ST + Represents MCPWM0_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM0_EVT_TIMER2_STOP_ST + Represents MCPWM0_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM0_EVT_TIMER0_TEZ_ST + Represents MCPWM0_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM0_EVT_TIMER1_TEZ_ST + Represents MCPWM0_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST1_CLR + Events trigger status clear register + 0x1B4 + 0x20 + + + LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR + Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR + Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER0_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER1_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER2_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + LEDC_EVT_TIME_OVF_TIMER3_ST_CLR + Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + LEDC_EVT_TIMER0_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + LEDC_EVT_TIMER1_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + LEDC_EVT_TIMER2_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + LEDC_EVT_TIMER3_CMP_ST_CLR + Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + TG0_EVT_CNT_CMP_TIMER0_ST_CLR + Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + TG0_EVT_CNT_CMP_TIMER1_ST_CLR + Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + TG1_EVT_CNT_CMP_TIMER0_ST_CLR + Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + TG1_EVT_CNT_CMP_TIMER1_ST_CLR + Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + SYSTIMER_EVT_CNT_CMP0_ST_CLR + Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + SYSTIMER_EVT_CNT_CMP1_ST_CLR + Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + SYSTIMER_EVT_CNT_CMP2_ST_CLR + Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM0_EVT_TIMER0_STOP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM0_EVT_TIMER1_STOP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM0_EVT_TIMER2_STOP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM0_EVT_TIMER0_TEZ_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM0_EVT_TIMER1_TEZ_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST2 + Events trigger status register + 0x1B8 + 0x20 + + + MCPWM0_EVT_TIMER2_TEZ_ST + Represents MCPWM0_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM0_EVT_TIMER0_TEP_ST + Represents MCPWM0_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM0_EVT_TIMER1_TEP_ST + Represents MCPWM0_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + MCPWM0_EVT_TIMER2_TEP_ST + Represents MCPWM0_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + MCPWM0_EVT_OP0_TEA_ST + Represents MCPWM0_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + MCPWM0_EVT_OP1_TEA_ST + Represents MCPWM0_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + MCPWM0_EVT_OP2_TEA_ST + Represents MCPWM0_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + MCPWM0_EVT_OP0_TEB_ST + Represents MCPWM0_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + MCPWM0_EVT_OP1_TEB_ST + Represents MCPWM0_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + MCPWM0_EVT_OP2_TEB_ST + Represents MCPWM0_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + MCPWM0_EVT_F0_ST + Represents MCPWM0_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + MCPWM0_EVT_F1_ST + Represents MCPWM0_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + MCPWM0_EVT_F2_ST + Represents MCPWM0_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + MCPWM0_EVT_F0_CLR_ST + Represents MCPWM0_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + MCPWM0_EVT_F1_CLR_ST + Represents MCPWM0_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + MCPWM0_EVT_F2_CLR_ST + Represents MCPWM0_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM0_EVT_TZ0_CBC_ST + Represents MCPWM0_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM0_EVT_TZ1_CBC_ST + Represents MCPWM0_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM0_EVT_TZ2_CBC_ST + Represents MCPWM0_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM0_EVT_TZ0_OST_ST + Represents MCPWM0_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM0_EVT_TZ1_OST_ST + Represents MCPWM0_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM0_EVT_TZ2_OST_ST + Represents MCPWM0_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM0_EVT_CAP0_ST + Represents MCPWM0_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM0_EVT_CAP1_ST + Represents MCPWM0_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM0_EVT_CAP2_ST + Represents MCPWM0_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM0_EVT_OP0_TEE1_ST + Represents MCPWM0_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM0_EVT_OP1_TEE1_ST + Represents MCPWM0_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM0_EVT_OP2_TEE1_ST + Represents MCPWM0_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM0_EVT_OP0_TEE2_ST + Represents MCPWM0_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM0_EVT_OP1_TEE2_ST + Represents MCPWM0_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM0_EVT_OP2_TEE2_ST + Represents MCPWM0_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM1_EVT_TIMER0_STOP_ST + Represents MCPWM1_evt_timer0_stop trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST2_CLR + Events trigger status clear register + 0x1BC + 0x20 + + + MCPWM0_EVT_TIMER2_TEZ_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM0_EVT_TIMER0_TEP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM0_EVT_TIMER1_TEP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + MCPWM0_EVT_TIMER2_TEP_ST_CLR + Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + MCPWM0_EVT_OP0_TEA_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + MCPWM0_EVT_OP1_TEA_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + MCPWM0_EVT_OP2_TEA_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + MCPWM0_EVT_OP0_TEB_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + MCPWM0_EVT_OP1_TEB_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + MCPWM0_EVT_OP2_TEB_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + MCPWM0_EVT_F0_ST_CLR + Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + MCPWM0_EVT_F1_ST_CLR + Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + MCPWM0_EVT_F2_ST_CLR + Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + MCPWM0_EVT_F0_CLR_ST_CLR + Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + MCPWM0_EVT_F1_CLR_ST_CLR + Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + MCPWM0_EVT_F2_CLR_ST_CLR + Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM0_EVT_TZ0_CBC_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM0_EVT_TZ1_CBC_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM0_EVT_TZ2_CBC_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM0_EVT_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM0_EVT_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM0_EVT_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM0_EVT_CAP0_ST_CLR + Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM0_EVT_CAP1_ST_CLR + Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM0_EVT_CAP2_ST_CLR + Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM0_EVT_OP0_TEE1_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM0_EVT_OP1_TEE1_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM0_EVT_OP2_TEE1_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM0_EVT_OP0_TEE2_ST_CLR + Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM0_EVT_OP1_TEE2_ST_CLR + Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM0_EVT_OP2_TEE2_ST_CLR + Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM1_EVT_TIMER0_STOP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST3 + Events trigger status register + 0x1C0 + 0x20 + + + MCPWM1_EVT_TIMER1_STOP_ST + Represents MCPWM1_evt_timer1_stop trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM1_EVT_TIMER2_STOP_ST + Represents MCPWM1_evt_timer2_stop trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM1_EVT_TIMER0_TEZ_ST + Represents MCPWM1_evt_timer0_tez trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + MCPWM1_EVT_TIMER1_TEZ_ST + Represents MCPWM1_evt_timer1_tez trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + MCPWM1_EVT_TIMER2_TEZ_ST + Represents MCPWM1_evt_timer2_tez trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + MCPWM1_EVT_TIMER0_TEP_ST + Represents MCPWM1_evt_timer0_tep trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + MCPWM1_EVT_TIMER1_TEP_ST + Represents MCPWM1_evt_timer1_tep trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + MCPWM1_EVT_TIMER2_TEP_ST + Represents MCPWM1_evt_timer2_tep trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + MCPWM1_EVT_OP0_TEA_ST + Represents MCPWM1_evt_op0_tea trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + MCPWM1_EVT_OP1_TEA_ST + Represents MCPWM1_evt_op1_tea trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + MCPWM1_EVT_OP2_TEA_ST + Represents MCPWM1_evt_op2_tea trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + MCPWM1_EVT_OP0_TEB_ST + Represents MCPWM1_evt_op0_teb trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + MCPWM1_EVT_OP1_TEB_ST + Represents MCPWM1_evt_op1_teb trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + MCPWM1_EVT_OP2_TEB_ST + Represents MCPWM1_evt_op2_teb trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + MCPWM1_EVT_F0_ST + Represents MCPWM1_evt_f0 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + MCPWM1_EVT_F1_ST + Represents MCPWM1_evt_f1 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM1_EVT_F2_ST + Represents MCPWM1_evt_f2 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM1_EVT_F0_CLR_ST + Represents MCPWM1_evt_f0_clr trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM1_EVT_F1_CLR_ST + Represents MCPWM1_evt_f1_clr trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM1_EVT_F2_CLR_ST + Represents MCPWM1_evt_f2_clr trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM1_EVT_TZ0_CBC_ST + Represents MCPWM1_evt_tz0_cbc trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM1_EVT_TZ1_CBC_ST + Represents MCPWM1_evt_tz1_cbc trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM1_EVT_TZ2_CBC_ST + Represents MCPWM1_evt_tz2_cbc trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM1_EVT_TZ0_OST_ST + Represents MCPWM1_evt_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM1_EVT_TZ1_OST_ST + Represents MCPWM1_evt_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM1_EVT_TZ2_OST_ST + Represents MCPWM1_evt_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM1_EVT_CAP0_ST + Represents MCPWM1_evt_cap0 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM1_EVT_CAP1_ST + Represents MCPWM1_evt_cap1 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM1_EVT_CAP2_ST + Represents MCPWM1_evt_cap2 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM1_EVT_OP0_TEE1_ST + Represents MCPWM1_evt_op0_tee1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM1_EVT_OP1_TEE1_ST + Represents MCPWM1_evt_op1_tee1 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM1_EVT_OP2_TEE1_ST + Represents MCPWM1_evt_op2_tee1 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST3_CLR + Events trigger status clear register + 0x1C4 + 0x20 + + + MCPWM1_EVT_TIMER1_STOP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM1_EVT_TIMER2_STOP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM1_EVT_TIMER0_TEZ_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + MCPWM1_EVT_TIMER1_TEZ_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + MCPWM1_EVT_TIMER2_TEZ_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + MCPWM1_EVT_TIMER0_TEP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + MCPWM1_EVT_TIMER1_TEP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + MCPWM1_EVT_TIMER2_TEP_ST_CLR + Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + MCPWM1_EVT_OP0_TEA_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_tea trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + MCPWM1_EVT_OP1_TEA_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_tea trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + MCPWM1_EVT_OP2_TEA_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_tea trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + MCPWM1_EVT_OP0_TEB_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_teb trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + MCPWM1_EVT_OP1_TEB_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_teb trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + MCPWM1_EVT_OP2_TEB_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_teb trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + MCPWM1_EVT_F0_ST_CLR + Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + MCPWM1_EVT_F1_ST_CLR + Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM1_EVT_F2_ST_CLR + Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM1_EVT_F0_CLR_ST_CLR + Configures whether or not to clear MCPWM1_evt_f0_clr trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM1_EVT_F1_CLR_ST_CLR + Configures whether or not to clear MCPWM1_evt_f1_clr trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM1_EVT_F2_CLR_ST_CLR + Configures whether or not to clear MCPWM1_evt_f2_clr trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM1_EVT_TZ0_CBC_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM1_EVT_TZ1_CBC_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM1_EVT_TZ2_CBC_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM1_EVT_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM1_EVT_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM1_EVT_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM1_EVT_CAP0_ST_CLR + Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM1_EVT_CAP1_ST_CLR + Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM1_EVT_CAP2_ST_CLR + Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM1_EVT_OP0_TEE1_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM1_EVT_OP1_TEE1_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM1_EVT_OP2_TEE1_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST4 + Events trigger status register + 0x1C8 + 0x20 + + + MCPWM1_EVT_OP0_TEE2_ST + Represents MCPWM1_evt_op0_tee2 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM1_EVT_OP1_TEE2_ST + Represents MCPWM1_evt_op1_tee2 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM1_EVT_OP2_TEE2_ST + Represents MCPWM1_evt_op2_tee2 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + ADC_EVT_CONV_CMPLT0_ST + Represents ADC_evt_conv_cmplt0 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + ADC_EVT_EQ_ABOVE_THRESH0_ST + Represents ADC_evt_eq_above_thresh0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + ADC_EVT_EQ_ABOVE_THRESH1_ST + Represents ADC_evt_eq_above_thresh1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + ADC_EVT_EQ_BELOW_THRESH0_ST + Represents ADC_evt_eq_below_thresh0 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + ADC_EVT_EQ_BELOW_THRESH1_ST + Represents ADC_evt_eq_below_thresh1 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + ADC_EVT_RESULT_DONE0_ST + Represents ADC_evt_result_done0 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + ADC_EVT_STOPPED0_ST + Represents ADC_evt_stopped0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + ADC_EVT_STARTED0_ST + Represents ADC_evt_started0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + REGDMA_EVT_DONE0_ST + Represents REGDMA_evt_done0 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + REGDMA_EVT_DONE1_ST + Represents REGDMA_evt_done1 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + REGDMA_EVT_DONE2_ST + Represents REGDMA_evt_done2 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + REGDMA_EVT_DONE3_ST + Represents REGDMA_evt_done3 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + REGDMA_EVT_ERR0_ST + Represents REGDMA_evt_err0 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + REGDMA_EVT_ERR1_ST + Represents REGDMA_evt_err1 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + REGDMA_EVT_ERR2_ST + Represents REGDMA_evt_err2 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + REGDMA_EVT_ERR3_ST + Represents REGDMA_evt_err3 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + TMPSNSR_EVT_OVER_LIMIT_ST + Represents TMPSNSR_evt_over_limit trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + I2S0_EVT_RX_DONE_ST + Represents I2S0_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + I2S0_EVT_TX_DONE_ST + Represents I2S0_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + I2S0_EVT_X_WORDS_RECEIVED_ST + Represents I2S0_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + I2S0_EVT_X_WORDS_SENT_ST + Represents I2S0_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + I2S1_EVT_RX_DONE_ST + Represents I2S1_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + I2S1_EVT_TX_DONE_ST + Represents I2S1_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + I2S1_EVT_X_WORDS_RECEIVED_ST + Represents I2S1_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + I2S1_EVT_X_WORDS_SENT_ST + Represents I2S1_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + I2S2_EVT_RX_DONE_ST + Represents I2S2_evt_rx_done trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + I2S2_EVT_TX_DONE_ST + Represents I2S2_evt_tx_done trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + I2S2_EVT_X_WORDS_RECEIVED_ST + Represents I2S2_evt_x_words_received trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + I2S2_EVT_X_WORDS_SENT_ST + Represents I2S2_evt_x_words_sent trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST4_CLR + Events trigger status clear register + 0x1CC + 0x20 + + + MCPWM1_EVT_OP0_TEE2_ST_CLR + Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM1_EVT_OP1_TEE2_ST_CLR + Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM1_EVT_OP2_TEE2_ST_CLR + Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + ADC_EVT_CONV_CMPLT0_ST_CLR + Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR + Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR + Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + ADC_EVT_EQ_BELOW_THRESH0_ST_CLR + Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + ADC_EVT_EQ_BELOW_THRESH1_ST_CLR + Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + ADC_EVT_RESULT_DONE0_ST_CLR + Configures whether or not to clear ADC_evt_result_done0 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + ADC_EVT_STOPPED0_ST_CLR + Configures whether or not to clear ADC_evt_stopped0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + ADC_EVT_STARTED0_ST_CLR + Configures whether or not to clear ADC_evt_started0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + REGDMA_EVT_DONE0_ST_CLR + Configures whether or not to clear REGDMA_evt_done0 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + REGDMA_EVT_DONE1_ST_CLR + Configures whether or not to clear REGDMA_evt_done1 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + REGDMA_EVT_DONE2_ST_CLR + Configures whether or not to clear REGDMA_evt_done2 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + REGDMA_EVT_DONE3_ST_CLR + Configures whether or not to clear REGDMA_evt_done3 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + REGDMA_EVT_ERR0_ST_CLR + Configures whether or not to clear REGDMA_evt_err0 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + REGDMA_EVT_ERR1_ST_CLR + Configures whether or not to clear REGDMA_evt_err1 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + REGDMA_EVT_ERR2_ST_CLR + Configures whether or not to clear REGDMA_evt_err2 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + REGDMA_EVT_ERR3_ST_CLR + Configures whether or not to clear REGDMA_evt_err3 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + TMPSNSR_EVT_OVER_LIMIT_ST_CLR + Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + I2S0_EVT_RX_DONE_ST_CLR + Configures whether or not to clear I2S0_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + I2S0_EVT_TX_DONE_ST_CLR + Configures whether or not to clear I2S0_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + I2S0_EVT_X_WORDS_RECEIVED_ST_CLR + Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + I2S0_EVT_X_WORDS_SENT_ST_CLR + Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + I2S1_EVT_RX_DONE_ST_CLR + Configures whether or not to clear I2S1_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + I2S1_EVT_TX_DONE_ST_CLR + Configures whether or not to clear I2S1_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + I2S1_EVT_X_WORDS_RECEIVED_ST_CLR + Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + I2S1_EVT_X_WORDS_SENT_ST_CLR + Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + I2S2_EVT_RX_DONE_ST_CLR + Configures whether or not to clear I2S2_evt_rx_done trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + I2S2_EVT_TX_DONE_ST_CLR + Configures whether or not to clear I2S2_evt_tx_done trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + I2S2_EVT_X_WORDS_RECEIVED_ST_CLR + Configures whether or not to clear I2S2_evt_x_words_received trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + I2S2_EVT_X_WORDS_SENT_ST_CLR + Configures whether or not to clear I2S2_evt_x_words_sent trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST5 + Events trigger status register + 0x1D0 + 0x20 + + + ULP_EVT_ERR_INTR_ST + Represents ULP_evt_err_intr trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + ULP_EVT_HALT_ST + Represents ULP_evt_halt trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + ULP_EVT_START_INTR_ST + Represents ULP_evt_start_intr trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + RTC_EVT_TICK_ST + Represents RTC_evt_tick trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + RTC_EVT_OVF_ST + Represents RTC_evt_ovf trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + RTC_EVT_CMP_ST + Represents RTC_evt_cmp trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + PDMA_AHB_EVT_IN_DONE_CH0_ST + Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + PDMA_AHB_EVT_IN_DONE_CH1_ST + Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + PDMA_AHB_EVT_IN_DONE_CH2_ST + Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST + Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST + Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST + Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST + Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST + Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST + Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST + Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST + Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST + Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + PDMA_AHB_EVT_OUT_DONE_CH0_ST + Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + PDMA_AHB_EVT_OUT_DONE_CH1_ST + Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + PDMA_AHB_EVT_OUT_DONE_CH2_ST + Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + PDMA_AHB_EVT_OUT_EOF_CH0_ST + Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + PDMA_AHB_EVT_OUT_EOF_CH1_ST + Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + PDMA_AHB_EVT_OUT_EOF_CH2_ST + Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST + Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST + Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST + Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST + Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST + Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST + Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST + Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST + Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST5_CLR + Events trigger status clear register + 0x1D4 + 0x20 + + + ULP_EVT_ERR_INTR_ST_CLR + Configures whether or not to clear ULP_evt_err_intr trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + ULP_EVT_HALT_ST_CLR + Configures whether or not to clear ULP_evt_halt trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + ULP_EVT_START_INTR_ST_CLR + Configures whether or not to clear ULP_evt_start_intr trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + RTC_EVT_TICK_ST_CLR + Configures whether or not to clear RTC_evt_tick trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + RTC_EVT_OVF_ST_CLR + Configures whether or not to clear RTC_evt_ovf trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + RTC_EVT_CMP_ST_CLR + Configures whether or not to clear RTC_evt_cmp trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST6 + Events trigger status register + 0x1D8 + 0x20 + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST + Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + PDMA_AXI_EVT_IN_DONE_CH0_ST + Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + PDMA_AXI_EVT_IN_DONE_CH1_ST + Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + PDMA_AXI_EVT_IN_DONE_CH2_ST + Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST + Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST + Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST + Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST + Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST + Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST + Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST + Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST + Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST + Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + PDMA_AXI_EVT_OUT_DONE_CH0_ST + Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + PDMA_AXI_EVT_OUT_DONE_CH1_ST + Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + PDMA_AXI_EVT_OUT_DONE_CH2_ST + Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + PDMA_AXI_EVT_OUT_EOF_CH0_ST + Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + PDMA_AXI_EVT_OUT_EOF_CH1_ST + Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + PDMA_AXI_EVT_OUT_EOF_CH2_ST + Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST + Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST + Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST + Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST + Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST + Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST + Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST + Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST + Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST + Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + PMU_EVT_SLEEP_WEEKUP_ST + Represents PMU_evt_sleep_weekup trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + DMA2D_EVT_IN_DONE_CH0_ST + Represents DMA2D_evt_in_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + DMA2D_EVT_IN_DONE_CH1_ST + Represents DMA2D_evt_in_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + DMA2D_EVT_IN_SUC_EOF_CH0_ST + Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + EVT_ST6_CLR + Events trigger status clear register + 0x1DC + 0x20 + + + PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + PMU_EVT_SLEEP_WEEKUP_ST_CLR + Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + DMA2D_EVT_IN_DONE_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + DMA2D_EVT_IN_DONE_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + EVT_ST7 + Events trigger status register + 0x1E0 + 0x20 + + + DMA2D_EVT_IN_SUC_EOF_CH1_ST + Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + DMA2D_EVT_OUT_DONE_CH0_ST + Represents DMA2D_evt_out_done_ch0 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + DMA2D_EVT_OUT_DONE_CH1_ST + Represents DMA2D_evt_out_done_ch1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + DMA2D_EVT_OUT_DONE_CH2_ST + Represents DMA2D_evt_out_done_ch2 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + DMA2D_EVT_OUT_EOF_CH0_ST + Represents DMA2D_evt_out_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + DMA2D_EVT_OUT_EOF_CH1_ST + Represents DMA2D_evt_out_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + DMA2D_EVT_OUT_EOF_CH2_ST + Represents DMA2D_evt_out_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST + Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST + Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST + Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + + + EVT_ST7_CLR + Events trigger status clear register + 0x1E4 + 0x20 + + + DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + DMA2D_EVT_OUT_DONE_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + DMA2D_EVT_OUT_DONE_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + DMA2D_EVT_OUT_DONE_CH2_ST_CLR + Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + DMA2D_EVT_OUT_EOF_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + DMA2D_EVT_OUT_EOF_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + DMA2D_EVT_OUT_EOF_CH2_ST_CLR + Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + + + TASK_ST0 + Tasks trigger status register + 0x1E8 + 0x20 + + + GPIO_TASK_CH0_SET_ST + Represents GPIO_task_ch0_set trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + GPIO_TASK_CH1_SET_ST + Represents GPIO_task_ch1_set trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + GPIO_TASK_CH2_SET_ST + Represents GPIO_task_ch2_set trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + GPIO_TASK_CH3_SET_ST + Represents GPIO_task_ch3_set trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + GPIO_TASK_CH4_SET_ST + Represents GPIO_task_ch4_set trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + GPIO_TASK_CH5_SET_ST + Represents GPIO_task_ch5_set trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + GPIO_TASK_CH6_SET_ST + Represents GPIO_task_ch6_set trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + GPIO_TASK_CH7_SET_ST + Represents GPIO_task_ch7_set trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + GPIO_TASK_CH0_CLEAR_ST + Represents GPIO_task_ch0_clear trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + GPIO_TASK_CH1_CLEAR_ST + Represents GPIO_task_ch1_clear trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + GPIO_TASK_CH2_CLEAR_ST + Represents GPIO_task_ch2_clear trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + GPIO_TASK_CH3_CLEAR_ST + Represents GPIO_task_ch3_clear trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + GPIO_TASK_CH4_CLEAR_ST + Represents GPIO_task_ch4_clear trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + GPIO_TASK_CH5_CLEAR_ST + Represents GPIO_task_ch5_clear trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + GPIO_TASK_CH6_CLEAR_ST + Represents GPIO_task_ch6_clear trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + GPIO_TASK_CH7_CLEAR_ST + Represents GPIO_task_ch7_clear trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + GPIO_TASK_CH0_TOGGLE_ST + Represents GPIO_task_ch0_toggle trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + GPIO_TASK_CH1_TOGGLE_ST + Represents GPIO_task_ch1_toggle trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + GPIO_TASK_CH2_TOGGLE_ST + Represents GPIO_task_ch2_toggle trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + GPIO_TASK_CH3_TOGGLE_ST + Represents GPIO_task_ch3_toggle trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + GPIO_TASK_CH4_TOGGLE_ST + Represents GPIO_task_ch4_toggle trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + GPIO_TASK_CH5_TOGGLE_ST + Represents GPIO_task_ch5_toggle trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + GPIO_TASK_CH6_TOGGLE_ST + Represents GPIO_task_ch6_toggle trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + GPIO_TASK_CH7_TOGGLE_ST + Represents GPIO_task_ch7_toggle trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + LEDC_TASK_TIMER0_RES_UPDATE_ST + Represents LEDC_task_timer0_res_update trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + LEDC_TASK_TIMER1_RES_UPDATE_ST + Represents LEDC_task_timer1_res_update trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + LEDC_TASK_TIMER2_RES_UPDATE_ST + Represents LEDC_task_timer2_res_update trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + LEDC_TASK_TIMER3_RES_UPDATE_ST + Represents LEDC_task_timer3_res_update trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST + Represents LEDC_task_duty_scale_update_ch0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST + Represents LEDC_task_duty_scale_update_ch1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST + Represents LEDC_task_duty_scale_update_ch2 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST + Represents LEDC_task_duty_scale_update_ch3 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST0_CLR + Tasks trigger status clear register + 0x1EC + 0x20 + + + GPIO_TASK_CH0_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch0_set trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + GPIO_TASK_CH1_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch1_set trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + GPIO_TASK_CH2_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch2_set trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + GPIO_TASK_CH3_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch3_set trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + GPIO_TASK_CH4_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch4_set trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + GPIO_TASK_CH5_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch5_set trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + GPIO_TASK_CH6_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch6_set trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + GPIO_TASK_CH7_SET_ST_CLR + Configures whether or not to clear GPIO_task_ch7_set trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + GPIO_TASK_CH0_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + GPIO_TASK_CH1_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + GPIO_TASK_CH2_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + GPIO_TASK_CH3_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + GPIO_TASK_CH4_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + GPIO_TASK_CH5_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + GPIO_TASK_CH6_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + GPIO_TASK_CH7_CLEAR_ST_CLR + Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + GPIO_TASK_CH0_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + GPIO_TASK_CH1_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + GPIO_TASK_CH2_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + GPIO_TASK_CH3_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + GPIO_TASK_CH4_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + GPIO_TASK_CH5_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + GPIO_TASK_CH6_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + GPIO_TASK_CH7_TOGGLE_ST_CLR + Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR + Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST1 + Tasks trigger status register + 0x1F0 + 0x20 + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST + Represents LEDC_task_duty_scale_update_ch4 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST + Represents LEDC_task_duty_scale_update_ch5 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST + Represents LEDC_task_duty_scale_update_ch6 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST + Represents LEDC_task_duty_scale_update_ch7 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + LEDC_TASK_TIMER0_CAP_ST + Represents LEDC_task_timer0_cap trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + LEDC_TASK_TIMER1_CAP_ST + Represents LEDC_task_timer1_cap trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + LEDC_TASK_TIMER2_CAP_ST + Represents LEDC_task_timer2_cap trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + LEDC_TASK_TIMER3_CAP_ST + Represents LEDC_task_timer3_cap trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH0_ST + Represents LEDC_task_sig_out_dis_ch0 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH1_ST + Represents LEDC_task_sig_out_dis_ch1 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH2_ST + Represents LEDC_task_sig_out_dis_ch2 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH3_ST + Represents LEDC_task_sig_out_dis_ch3 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH4_ST + Represents LEDC_task_sig_out_dis_ch4 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH5_ST + Represents LEDC_task_sig_out_dis_ch5 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH6_ST + Represents LEDC_task_sig_out_dis_ch6 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + LEDC_TASK_SIG_OUT_DIS_CH7_ST + Represents LEDC_task_sig_out_dis_ch7 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH0_ST + Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH1_ST + Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH2_ST + Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH3_ST + Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH4_ST + Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH5_ST + Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH6_ST + Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + LEDC_TASK_OVF_CNT_RST_CH7_ST + Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + LEDC_TASK_TIMER0_RST_ST + Represents LEDC_task_timer0_rst trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + LEDC_TASK_TIMER1_RST_ST + Represents LEDC_task_timer1_rst trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + LEDC_TASK_TIMER2_RST_ST + Represents LEDC_task_timer2_rst trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + LEDC_TASK_TIMER3_RST_ST + Represents LEDC_task_timer3_rst trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + LEDC_TASK_TIMER0_RESUME_ST + Represents LEDC_task_timer0_resume trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + LEDC_TASK_TIMER1_RESUME_ST + Represents LEDC_task_timer1_resume trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + LEDC_TASK_TIMER2_RESUME_ST + Represents LEDC_task_timer2_resume trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + LEDC_TASK_TIMER3_RESUME_ST + Represents LEDC_task_timer3_resume trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST1_CLR + Tasks trigger status clear register + 0x1F4 + 0x20 + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR + Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + LEDC_TASK_TIMER0_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + LEDC_TASK_TIMER1_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + LEDC_TASK_TIMER2_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + LEDC_TASK_TIMER3_CAP_ST_CLR + Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR + Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR + Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + LEDC_TASK_TIMER0_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + LEDC_TASK_TIMER1_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + LEDC_TASK_TIMER2_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + LEDC_TASK_TIMER3_RST_ST_CLR + Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + LEDC_TASK_TIMER0_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + LEDC_TASK_TIMER1_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + LEDC_TASK_TIMER2_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + LEDC_TASK_TIMER3_RESUME_ST_CLR + Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST2 + Tasks trigger status register + 0x1F8 + 0x20 + + + LEDC_TASK_TIMER0_PAUSE_ST + Represents LEDC_task_timer0_pause trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + LEDC_TASK_TIMER1_PAUSE_ST + Represents LEDC_task_timer1_pause trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + LEDC_TASK_TIMER2_PAUSE_ST + Represents LEDC_task_timer2_pause trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + LEDC_TASK_TIMER3_PAUSE_ST + Represents LEDC_task_timer3_pause trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH0_ST + Represents LEDC_task_gamma_restart_ch0 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH1_ST + Represents LEDC_task_gamma_restart_ch1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH2_ST + Represents LEDC_task_gamma_restart_ch2 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH3_ST + Represents LEDC_task_gamma_restart_ch3 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH4_ST + Represents LEDC_task_gamma_restart_ch4 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH5_ST + Represents LEDC_task_gamma_restart_ch5 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH6_ST + Represents LEDC_task_gamma_restart_ch6 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + LEDC_TASK_GAMMA_RESTART_CH7_ST + Represents LEDC_task_gamma_restart_ch7 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH0_ST + Represents LEDC_task_gamma_pause_ch0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH1_ST + Represents LEDC_task_gamma_pause_ch1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH2_ST + Represents LEDC_task_gamma_pause_ch2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH3_ST + Represents LEDC_task_gamma_pause_ch3 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH4_ST + Represents LEDC_task_gamma_pause_ch4 trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH5_ST + Represents LEDC_task_gamma_pause_ch5 trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH6_ST + Represents LEDC_task_gamma_pause_ch6 trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + LEDC_TASK_GAMMA_PAUSE_CH7_ST + Represents LEDC_task_gamma_pause_ch7 trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH0_ST + Represents LEDC_task_gamma_resume_ch0 trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH1_ST + Represents LEDC_task_gamma_resume_ch1 trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH2_ST + Represents LEDC_task_gamma_resume_ch2 trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH3_ST + Represents LEDC_task_gamma_resume_ch3 trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH4_ST + Represents LEDC_task_gamma_resume_ch4 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH5_ST + Represents LEDC_task_gamma_resume_ch5 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH6_ST + Represents LEDC_task_gamma_resume_ch6 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + LEDC_TASK_GAMMA_RESUME_CH7_ST + Represents LEDC_task_gamma_resume_ch7 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + TG0_TASK_CNT_START_TIMER0_ST + Represents TG0_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + TG0_TASK_ALARM_START_TIMER0_ST + Represents TG0_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + TG0_TASK_CNT_STOP_TIMER0_ST + Represents TG0_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + TG0_TASK_CNT_RELOAD_TIMER0_ST + Represents TG0_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST2_CLR + Tasks trigger status clear register + 0x1FC + 0x20 + + + LEDC_TASK_TIMER0_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + LEDC_TASK_TIMER1_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + LEDC_TASK_TIMER2_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + LEDC_TASK_TIMER3_PAUSE_ST_CLR + Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR + Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR + Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR + Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + TG0_TASK_CNT_START_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + TG0_TASK_ALARM_START_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + TG0_TASK_CNT_STOP_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST3 + Tasks trigger status register + 0x200 + 0x20 + + + TG0_TASK_CNT_CAP_TIMER0_ST + Represents TG0_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + TG0_TASK_CNT_START_TIMER1_ST + Represents TG0_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + TG0_TASK_ALARM_START_TIMER1_ST + Represents TG0_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + TG0_TASK_CNT_STOP_TIMER1_ST + Represents TG0_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + TG0_TASK_CNT_RELOAD_TIMER1_ST + Represents TG0_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + TG0_TASK_CNT_CAP_TIMER1_ST + Represents TG0_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + TG1_TASK_CNT_START_TIMER0_ST + Represents TG1_task_cnt_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + TG1_TASK_ALARM_START_TIMER0_ST + Represents TG1_task_alarm_start_timer0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + TG1_TASK_CNT_STOP_TIMER0_ST + Represents TG1_task_cnt_stop_timer0 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + TG1_TASK_CNT_RELOAD_TIMER0_ST + Represents TG1_task_cnt_reload_timer0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + TG1_TASK_CNT_CAP_TIMER0_ST + Represents TG1_task_cnt_cap_timer0 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + TG1_TASK_CNT_START_TIMER1_ST + Represents TG1_task_cnt_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + TG1_TASK_ALARM_START_TIMER1_ST + Represents TG1_task_alarm_start_timer1 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + TG1_TASK_CNT_STOP_TIMER1_ST + Represents TG1_task_cnt_stop_timer1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + TG1_TASK_CNT_RELOAD_TIMER1_ST + Represents TG1_task_cnt_reload_timer1 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + TG1_TASK_CNT_CAP_TIMER1_ST + Represents TG1_task_cnt_cap_timer1 trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM0_TASK_CMPR0_A_UP_ST + Represents MCPWM0_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM0_TASK_CMPR1_A_UP_ST + Represents MCPWM0_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM0_TASK_CMPR2_A_UP_ST + Represents MCPWM0_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM0_TASK_CMPR0_B_UP_ST + Represents MCPWM0_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM0_TASK_CMPR1_B_UP_ST + Represents MCPWM0_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM0_TASK_CMPR2_B_UP_ST + Represents MCPWM0_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM0_TASK_GEN_STOP_ST + Represents MCPWM0_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM0_TASK_TIMER0_SYN_ST + Represents MCPWM0_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM0_TASK_TIMER1_SYN_ST + Represents MCPWM0_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM0_TASK_TIMER2_SYN_ST + Represents MCPWM0_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM0_TASK_TIMER0_PERIOD_UP_ST + Represents MCPWM0_task_timer0_period_up trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM0_TASK_TIMER1_PERIOD_UP_ST + Represents MCPWM0_task_timer1_period_up trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + MCPWM0_TASK_TIMER2_PERIOD_UP_ST + Represents MCPWM0_task_timer2_period_up trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + MCPWM0_TASK_TZ0_OST_ST + Represents MCPWM0_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + MCPWM0_TASK_TZ1_OST_ST + Represents MCPWM0_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + MCPWM0_TASK_TZ2_OST_ST + Represents MCPWM0_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST3_CLR + Tasks trigger status clear register + 0x204 + 0x20 + + + TG0_TASK_CNT_CAP_TIMER0_ST_CLR + Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + TG0_TASK_CNT_START_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + TG0_TASK_ALARM_START_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + TG0_TASK_CNT_STOP_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + TG0_TASK_CNT_CAP_TIMER1_ST_CLR + Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + TG1_TASK_CNT_START_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + TG1_TASK_ALARM_START_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + TG1_TASK_CNT_STOP_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + TG1_TASK_CNT_CAP_TIMER0_ST_CLR + Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + TG1_TASK_CNT_START_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + TG1_TASK_ALARM_START_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + TG1_TASK_CNT_STOP_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + TG1_TASK_CNT_CAP_TIMER1_ST_CLR + Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM0_TASK_CMPR0_A_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM0_TASK_CMPR1_A_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM0_TASK_CMPR2_A_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM0_TASK_CMPR0_B_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM0_TASK_CMPR1_B_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM0_TASK_CMPR2_B_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM0_TASK_GEN_STOP_ST_CLR + Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM0_TASK_TIMER0_SYN_ST_CLR + Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM0_TASK_TIMER1_SYN_ST_CLR + Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM0_TASK_TIMER2_SYN_ST_CLR + Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + MCPWM0_TASK_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + MCPWM0_TASK_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + MCPWM0_TASK_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST4 + Tasks trigger status register + 0x208 + 0x20 + + + MCPWM0_TASK_CLR0_OST_ST + Represents MCPWM0_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + MCPWM0_TASK_CLR1_OST_ST + Represents MCPWM0_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + MCPWM0_TASK_CLR2_OST_ST + Represents MCPWM0_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + MCPWM0_TASK_CAP0_ST + Represents MCPWM0_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + MCPWM0_TASK_CAP1_ST + Represents MCPWM0_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + MCPWM0_TASK_CAP2_ST + Represents MCPWM0_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + MCPWM1_TASK_CMPR0_A_UP_ST + Represents MCPWM1_task_cmpr0_a_up trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + MCPWM1_TASK_CMPR1_A_UP_ST + Represents MCPWM1_task_cmpr1_a_up trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + MCPWM1_TASK_CMPR2_A_UP_ST + Represents MCPWM1_task_cmpr2_a_up trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + MCPWM1_TASK_CMPR0_B_UP_ST + Represents MCPWM1_task_cmpr0_b_up trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + MCPWM1_TASK_CMPR1_B_UP_ST + Represents MCPWM1_task_cmpr1_b_up trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + MCPWM1_TASK_CMPR2_B_UP_ST + Represents MCPWM1_task_cmpr2_b_up trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + MCPWM1_TASK_GEN_STOP_ST + Represents MCPWM1_task_gen_stop trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + MCPWM1_TASK_TIMER0_SYN_ST + Represents MCPWM1_task_timer0_syn trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + MCPWM1_TASK_TIMER1_SYN_ST + Represents MCPWM1_task_timer1_syn trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + MCPWM1_TASK_TIMER2_SYN_ST + Represents MCPWM1_task_timer2_syn trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + MCPWM1_TASK_TIMER0_PERIOD_UP_ST + Represents MCPWM1_task_timer0_period_up trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + MCPWM1_TASK_TIMER1_PERIOD_UP_ST + Represents MCPWM1_task_timer1_period_up trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + MCPWM1_TASK_TIMER2_PERIOD_UP_ST + Represents MCPWM1_task_timer2_period_up trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + MCPWM1_TASK_TZ0_OST_ST + Represents MCPWM1_task_tz0_ost trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + MCPWM1_TASK_TZ1_OST_ST + Represents MCPWM1_task_tz1_ost trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + MCPWM1_TASK_TZ2_OST_ST + Represents MCPWM1_task_tz2_ost trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + MCPWM1_TASK_CLR0_OST_ST + Represents MCPWM1_task_clr0_ost trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + MCPWM1_TASK_CLR1_OST_ST + Represents MCPWM1_task_clr1_ost trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + MCPWM1_TASK_CLR2_OST_ST + Represents MCPWM1_task_clr2_ost trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + MCPWM1_TASK_CAP0_ST + Represents MCPWM1_task_cap0 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + MCPWM1_TASK_CAP1_ST + Represents MCPWM1_task_cap1 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + MCPWM1_TASK_CAP2_ST + Represents MCPWM1_task_cap2 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + ADC_TASK_SAMPLE0_ST + Represents ADC_task_sample0 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + ADC_TASK_SAMPLE1_ST + Represents ADC_task_sample1 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + ADC_TASK_START0_ST + Represents ADC_task_start0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + ADC_TASK_STOP0_ST + Represents ADC_task_stop0 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST4_CLR + Tasks trigger status clear register + 0x20C + 0x20 + + + MCPWM0_TASK_CLR0_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + MCPWM0_TASK_CLR1_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + MCPWM0_TASK_CLR2_OST_ST_CLR + Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + MCPWM0_TASK_CAP0_ST_CLR + Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + MCPWM0_TASK_CAP1_ST_CLR + Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + MCPWM0_TASK_CAP2_ST_CLR + Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + MCPWM1_TASK_CMPR0_A_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + MCPWM1_TASK_CMPR1_A_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + MCPWM1_TASK_CMPR2_A_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + MCPWM1_TASK_CMPR0_B_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + MCPWM1_TASK_CMPR1_B_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + MCPWM1_TASK_CMPR2_B_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + MCPWM1_TASK_GEN_STOP_ST_CLR + Configures whether or not to clear MCPWM1_task_gen_stop trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + MCPWM1_TASK_TIMER0_SYN_ST_CLR + Configures whether or not to clear MCPWM1_task_timer0_syn trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + MCPWM1_TASK_TIMER1_SYN_ST_CLR + Configures whether or not to clear MCPWM1_task_timer1_syn trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + MCPWM1_TASK_TIMER2_SYN_ST_CLR + Configures whether or not to clear MCPWM1_task_timer2_syn trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR + Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + MCPWM1_TASK_TZ0_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_tz0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + MCPWM1_TASK_TZ1_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_tz1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + MCPWM1_TASK_TZ2_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_tz2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + MCPWM1_TASK_CLR0_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_clr0_ost trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + MCPWM1_TASK_CLR1_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_clr1_ost trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + MCPWM1_TASK_CLR2_OST_ST_CLR + Configures whether or not to clear MCPWM1_task_clr2_ost trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + MCPWM1_TASK_CAP0_ST_CLR + Configures whether or not to clear MCPWM1_task_cap0 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + MCPWM1_TASK_CAP1_ST_CLR + Configures whether or not to clear MCPWM1_task_cap1 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + MCPWM1_TASK_CAP2_ST_CLR + Configures whether or not to clear MCPWM1_task_cap2 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + ADC_TASK_SAMPLE0_ST_CLR + Configures whether or not to clear ADC_task_sample0 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + ADC_TASK_SAMPLE1_ST_CLR + Configures whether or not to clear ADC_task_sample1 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + ADC_TASK_START0_ST_CLR + Configures whether or not to clear ADC_task_start0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + ADC_TASK_STOP0_ST_CLR + Configures whether or not to clear ADC_task_stop0 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST5 + Tasks trigger status register + 0x210 + 0x20 + + + REGDMA_TASK_START0_ST + Represents REGDMA_task_start0 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + REGDMA_TASK_START1_ST + Represents REGDMA_task_start1 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + REGDMA_TASK_START2_ST + Represents REGDMA_task_start2 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + REGDMA_TASK_START3_ST + Represents REGDMA_task_start3 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + TMPSNSR_TASK_START_SAMPLE_ST + Represents TMPSNSR_task_start_sample trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + TMPSNSR_TASK_STOP_SAMPLE_ST + Represents TMPSNSR_task_stop_sample trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + I2S0_TASK_START_RX_ST + Represents I2S0_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + I2S0_TASK_START_TX_ST + Represents I2S0_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + I2S0_TASK_STOP_RX_ST + Represents I2S0_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + I2S0_TASK_STOP_TX_ST + Represents I2S0_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + I2S1_TASK_START_RX_ST + Represents I2S1_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + I2S1_TASK_START_TX_ST + Represents I2S1_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + I2S1_TASK_STOP_RX_ST + Represents I2S1_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + I2S1_TASK_STOP_TX_ST + Represents I2S1_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + I2S2_TASK_START_RX_ST + Represents I2S2_task_start_rx trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + I2S2_TASK_START_TX_ST + Represents I2S2_task_start_tx trigger status.\\0: Not triggered\\1: Triggered + 15 + 1 + read-write + + + I2S2_TASK_STOP_RX_ST + Represents I2S2_task_stop_rx trigger status.\\0: Not triggered\\1: Triggered + 16 + 1 + read-write + + + I2S2_TASK_STOP_TX_ST + Represents I2S2_task_stop_tx trigger status.\\0: Not triggered\\1: Triggered + 17 + 1 + read-write + + + ULP_TASK_WAKEUP_CPU_ST + Represents ULP_task_wakeup_cpu trigger status.\\0: Not triggered\\1: Triggered + 18 + 1 + read-write + + + ULP_TASK_INT_CPU_ST + Represents ULP_task_int_cpu trigger status.\\0: Not triggered\\1: Triggered + 19 + 1 + read-write + + + RTC_TASK_START_ST + Represents RTC_task_start trigger status.\\0: Not triggered\\1: Triggered + 20 + 1 + read-write + + + RTC_TASK_STOP_ST + Represents RTC_task_stop trigger status.\\0: Not triggered\\1: Triggered + 21 + 1 + read-write + + + RTC_TASK_CLR_ST + Represents RTC_task_clr trigger status.\\0: Not triggered\\1: Triggered + 22 + 1 + read-write + + + RTC_TASK_TRIGGERFLW_ST + Represents RTC_task_triggerflw trigger status.\\0: Not triggered\\1: Triggered + 23 + 1 + read-write + + + PDMA_AHB_TASK_IN_START_CH0_ST + Represents PDMA_AHB_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 24 + 1 + read-write + + + PDMA_AHB_TASK_IN_START_CH1_ST + Represents PDMA_AHB_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 25 + 1 + read-write + + + PDMA_AHB_TASK_IN_START_CH2_ST + Represents PDMA_AHB_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 26 + 1 + read-write + + + PDMA_AHB_TASK_OUT_START_CH0_ST + Represents PDMA_AHB_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 27 + 1 + read-write + + + PDMA_AHB_TASK_OUT_START_CH1_ST + Represents PDMA_AHB_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 28 + 1 + read-write + + + PDMA_AHB_TASK_OUT_START_CH2_ST + Represents PDMA_AHB_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 29 + 1 + read-write + + + PDMA_AXI_TASK_IN_START_CH0_ST + Represents PDMA_AXI_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 30 + 1 + read-write + + + PDMA_AXI_TASK_IN_START_CH1_ST + Represents PDMA_AXI_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 31 + 1 + read-write + + + + + TASK_ST5_CLR + Tasks trigger status clear register + 0x214 + 0x20 + + + REGDMA_TASK_START0_ST_CLR + Configures whether or not to clear REGDMA_task_start0 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + REGDMA_TASK_START1_ST_CLR + Configures whether or not to clear REGDMA_task_start1 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + REGDMA_TASK_START2_ST_CLR + Configures whether or not to clear REGDMA_task_start2 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + REGDMA_TASK_START3_ST_CLR + Configures whether or not to clear REGDMA_task_start3 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + TMPSNSR_TASK_START_SAMPLE_ST_CLR + Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + TMPSNSR_TASK_STOP_SAMPLE_ST_CLR + Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + I2S0_TASK_START_RX_ST_CLR + Configures whether or not to clear I2S0_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + I2S0_TASK_START_TX_ST_CLR + Configures whether or not to clear I2S0_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + I2S0_TASK_STOP_RX_ST_CLR + Configures whether or not to clear I2S0_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + I2S0_TASK_STOP_TX_ST_CLR + Configures whether or not to clear I2S0_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + I2S1_TASK_START_RX_ST_CLR + Configures whether or not to clear I2S1_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + I2S1_TASK_START_TX_ST_CLR + Configures whether or not to clear I2S1_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + I2S1_TASK_STOP_RX_ST_CLR + Configures whether or not to clear I2S1_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + I2S1_TASK_STOP_TX_ST_CLR + Configures whether or not to clear I2S1_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + I2S2_TASK_START_RX_ST_CLR + Configures whether or not to clear I2S2_task_start_rx trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + I2S2_TASK_START_TX_ST_CLR + Configures whether or not to clear I2S2_task_start_tx trigger status.\\0: Invalid, No effect\\1: Clear + 15 + 1 + write-only + + + I2S2_TASK_STOP_RX_ST_CLR + Configures whether or not to clear I2S2_task_stop_rx trigger status.\\0: Invalid, No effect\\1: Clear + 16 + 1 + write-only + + + I2S2_TASK_STOP_TX_ST_CLR + Configures whether or not to clear I2S2_task_stop_tx trigger status.\\0: Invalid, No effect\\1: Clear + 17 + 1 + write-only + + + ULP_TASK_WAKEUP_CPU_ST_CLR + Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\0: Invalid, No effect\\1: Clear + 18 + 1 + write-only + + + ULP_TASK_INT_CPU_ST_CLR + Configures whether or not to clear ULP_task_int_cpu trigger status.\\0: Invalid, No effect\\1: Clear + 19 + 1 + write-only + + + RTC_TASK_START_ST_CLR + Configures whether or not to clear RTC_task_start trigger status.\\0: Invalid, No effect\\1: Clear + 20 + 1 + write-only + + + RTC_TASK_STOP_ST_CLR + Configures whether or not to clear RTC_task_stop trigger status.\\0: Invalid, No effect\\1: Clear + 21 + 1 + write-only + + + RTC_TASK_CLR_ST_CLR + Configures whether or not to clear RTC_task_clr trigger status.\\0: Invalid, No effect\\1: Clear + 22 + 1 + write-only + + + RTC_TASK_TRIGGERFLW_ST_CLR + Configures whether or not to clear RTC_task_triggerflw trigger status.\\0: Invalid, No effect\\1: Clear + 23 + 1 + write-only + + + PDMA_AHB_TASK_IN_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 24 + 1 + write-only + + + PDMA_AHB_TASK_IN_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 25 + 1 + write-only + + + PDMA_AHB_TASK_IN_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 26 + 1 + write-only + + + PDMA_AHB_TASK_OUT_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 27 + 1 + write-only + + + PDMA_AHB_TASK_OUT_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 28 + 1 + write-only + + + PDMA_AHB_TASK_OUT_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 29 + 1 + write-only + + + PDMA_AXI_TASK_IN_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 30 + 1 + write-only + + + PDMA_AXI_TASK_IN_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 31 + 1 + write-only + + + + + TASK_ST6 + Tasks trigger status register + 0x218 + 0x20 + + + PDMA_AXI_TASK_IN_START_CH2_ST + Represents PDMA_AXI_task_in_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 0 + 1 + read-write + + + PDMA_AXI_TASK_OUT_START_CH0_ST + Represents PDMA_AXI_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 1 + 1 + read-write + + + PDMA_AXI_TASK_OUT_START_CH1_ST + Represents PDMA_AXI_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 2 + 1 + read-write + + + PDMA_AXI_TASK_OUT_START_CH2_ST + Represents PDMA_AXI_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 3 + 1 + read-write + + + PMU_TASK_SLEEP_REQ_ST + Represents PMU_task_sleep_req trigger status.\\0: Not triggered\\1: Triggered + 4 + 1 + read-write + + + DMA2D_TASK_IN_START_CH0_ST + Represents DMA2D_task_in_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 5 + 1 + read-write + + + DMA2D_TASK_IN_START_CH1_ST + Represents DMA2D_task_in_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 6 + 1 + read-write + + + DMA2D_TASK_IN_DSCR_READY_CH0_ST + Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: Triggered + 7 + 1 + read-write + + + DMA2D_TASK_IN_DSCR_READY_CH1_ST + Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: Triggered + 8 + 1 + read-write + + + DMA2D_TASK_OUT_START_CH0_ST + Represents DMA2D_task_out_start_ch0 trigger status.\\0: Not triggered\\1: Triggered + 9 + 1 + read-write + + + DMA2D_TASK_OUT_START_CH1_ST + Represents DMA2D_task_out_start_ch1 trigger status.\\0: Not triggered\\1: Triggered + 10 + 1 + read-write + + + DMA2D_TASK_OUT_START_CH2_ST + Represents DMA2D_task_out_start_ch2 trigger status.\\0: Not triggered\\1: Triggered + 11 + 1 + read-write + + + DMA2D_TASK_OUT_DSCR_READY_CH0_ST + Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: Not triggered\\1: Triggered + 12 + 1 + read-write + + + DMA2D_TASK_OUT_DSCR_READY_CH1_ST + Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: Not triggered\\1: Triggered + 13 + 1 + read-write + + + DMA2D_TASK_OUT_DSCR_READY_CH2_ST + Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: Not triggered\\1: Triggered + 14 + 1 + read-write + + + + + TASK_ST6_CLR + Tasks trigger status clear register + 0x21C + 0x20 + + + PDMA_AXI_TASK_IN_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 0 + 1 + write-only + + + PDMA_AXI_TASK_OUT_START_CH0_ST_CLR + Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 1 + 1 + write-only + + + PDMA_AXI_TASK_OUT_START_CH1_ST_CLR + Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 2 + 1 + write-only + + + PDMA_AXI_TASK_OUT_START_CH2_ST_CLR + Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 3 + 1 + write-only + + + PMU_TASK_SLEEP_REQ_ST_CLR + Configures whether or not to clear PMU_task_sleep_req trigger status.\\0: Invalid, No effect\\1: Clear + 4 + 1 + write-only + + + DMA2D_TASK_IN_START_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 5 + 1 + write-only + + + DMA2D_TASK_IN_START_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 6 + 1 + write-only + + + DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 7 + 1 + write-only + + + DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 8 + 1 + write-only + + + DMA2D_TASK_OUT_START_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 9 + 1 + write-only + + + DMA2D_TASK_OUT_START_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 10 + 1 + write-only + + + DMA2D_TASK_OUT_START_CH2_ST_CLR + Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 11 + 1 + write-only + + + DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR + Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger status.\\0: Invalid, No effect\\1: Clear + 12 + 1 + write-only + + + DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR + Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger status.\\0: Invalid, No effect\\1: Clear + 13 + 1 + write-only + + + DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR + Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger status.\\0: Invalid, No effect\\1: Clear + 14 + 1 + write-only + + + + + CLK_EN + ETM clock enable register + 0x220 + 0x20 + + + CLK_EN + Configures whether or not to open register clock gate.\\0: Open the clock gate only when application writes registers\\1: Force open the clock gate for register + 0 + 1 + read-write + + + + + DATE + ETM date register + 0x224 + 0x20 + 0x02303031 + + + DATE + Configures the version. + 0 + 28 + read-write + + + + + + + SPI0 + SPI (Serial Peripheral Interface) Controller 0 + SPI0 + 0x5008C000 + + 0x0 + 0x14C + registers + + + + SPI_MEM_CMD + SPI0 FSM status register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_USR + SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-only + + + + + SPI_MEM_CTRL + SPI0 control register. + 0x8 + 0x20 + 0x802C200C + + + SPI_MEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller. + 0 + 1 + read-write + + + SPI_MEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller. + 1 + 1 + read-write + + + SPI_MEM_FDUMMY_RIN + In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-write + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-write + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-write + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-write + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_DQS_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-write + + + SPI_MEM_DATA_IE_ALWAYS_ON + When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI0 control1 register. + 0xC + 0x20 + 0x28E00000 + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_AR_SIZE0_1_SUPPORT_EN + 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. + 21 + 1 + read-write + + + SPI_AW_SIZE0_1_SUPPORT_EN + 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. + 22 + 1 + read-write + + + SPI_AXI_RDATA_BACK_FAST + 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available. + 23 + 1 + read-write + + + SPI_MEM_RRESP_ECC_ERR_EN + 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG. + 24 + 1 + read-write + + + SPI_MEM_AR_SPLICE_EN + Set this bit to enable AXI Read Splice-transfer. + 25 + 1 + read-write + + + SPI_MEM_AW_SPLICE_EN + Set this bit to enable AXI Write Splice-transfer. + 26 + 1 + read-write + + + SPI_MEM_RAM0_EN + When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 27 + 1 + read-only + + + SPI_MEM_DUAL_RAM_EN + Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. + 28 + 1 + read-only + + + SPI_MEM_FAST_WRITE_EN + Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2. + 29 + 1 + read-write + + + SPI_MEM_RXFIFO_RST + The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. + 30 + 1 + write-only + + + SPI_MEM_TXFIFO_RST + The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. + 31 + 1 + write-only + + + + + SPI_MEM_CTRL2 + SPI0 control2 register. + 0x10 + 0x20 + 0x01002C21 + + + SPI_MEM_CS_SETUP_TIME + (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit. + 0 + 5 + read-write + + + SPI_MEM_CS_HOLD_TIME + SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit. + 5 + 5 + read-write + + + SPI_MEM_ECC_CS_HOLD_TIME + SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. + 10 + 3 + read-write + + + SPI_MEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash. + 13 + 1 + read-write + + + SPI_MEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + 14 + 1 + read-write + + + SPI_MEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 24 + 1 + read-write + + + SPI_MEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SPI_MEM_SYNC_RESET + The spi0_mst_st and spi0_slv_st will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock. + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI0 user register. + 0x18 + 0x20 + + + SPI_MEM_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. + 6 + 1 + read-write + + + SPI_MEM_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 7 + 1 + read-write + + + SPI_MEM_CK_OUT_EDGE + The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + 9 + 1 + read-write + + + SPI_MEM_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI0 user1 register. + 0x1C + 0x20 + 0x5C000047 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_DBYTELEN + SPI0 USR_CMD read or write data byte length -1 + 6 + 3 + read-only + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI0 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_RD_STATUS + SPI0 read control register. + 0x2C + 0x20 + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI0 misc register + 0x34 + 0x20 + + + SPI_MEM_FSUB_PIN + For SPI0, flash is connected to SUBPINs. + 7 + 1 + read-write + + + SPI_MEM_SSUB_PIN + For SPI0, sram is connected to SUBPINs. + 8 + 1 + read-write + + + SPI_MEM_CK_IDLE_EDGE + 1: SPI_CLK line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + SPI_CS line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_CACHE_FCTRL + SPI0 bit mode control register. + 0x3C + 0x20 + 0xC0000000 + + + SPI_MEM_AXI_REQ_EN + For SPI0, AXI master access enable, 1: enable, 0:disable. + 0 + 1 + read-write + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_CACHE_FLASH_USR_CMD + For SPI0, cache read flash for user define command, 1: enable, 0:disable. + 2 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + SPI_SAME_AW_AR_ADDR_CHK_EN + Set this bit to check AXI read/write the same address region. + 30 + 1 + read-write + + + SPI_CLOSE_AXI_INF_EN + Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP. + 31 + 1 + read-write + + + + + SPI_MEM_CACHE_SCTRL + SPI0 external RAM control register + 0x40 + 0x20 + 0x0055C070 + + + SPI_MEM_CACHE_USR_SADDR_4BYTE + For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable. + 0 + 1 + read-write + + + SPI_MEM_USR_SRAM_DIO + For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable + 1 + 1 + read-write + + + SPI_MEM_USR_SRAM_QIO + For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable + 2 + 1 + read-write + + + SPI_MEM_USR_WR_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations. + 3 + 1 + read-write + + + SPI_MEM_USR_RD_SRAM_DUMMY + For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations. + 4 + 1 + read-write + + + SPI_MEM_CACHE_SRAM_USR_RCMD + For SPI0, In the external RAM mode cache read external RAM for user define command. + 5 + 1 + read-write + + + SPI_MEM_SRAM_RDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1). + 6 + 6 + read-write + + + SPI_MEM_SRAM_ADDR_BITLEN + For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1). + 14 + 6 + read-write + + + SPI_MEM_CACHE_SRAM_USR_WCMD + For SPI0, In the external RAM mode cache write sram for user define command + 20 + 1 + read-write + + + SPI_MEM_SRAM_OCT + reserved + 21 + 1 + read-write + + + SPI_MEM_SRAM_WDUMMY_CYCLELEN + For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1). + 22 + 6 + read-write + + + + + SPI_MEM_SRAM_CMD + SPI0 external RAM mode control register + 0x44 + 0x20 + 0x80C00000 + + + SPI_MEM_SCLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. + 0 + 2 + read-write + + + SPI_MEM_SWB_MODE + Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. + 2 + 8 + read-write + + + SPI_MEM_SDIN_DUAL + For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 10 + 1 + read-write + + + SPI_MEM_SDOUT_DUAL + For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 11 + 1 + read-write + + + SPI_MEM_SADDR_DUAL + For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. + 12 + 1 + read-write + + + SPI_MEM_SDIN_QUAD + For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 14 + 1 + read-write + + + SPI_MEM_SDOUT_QUAD + For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 15 + 1 + read-write + + + SPI_MEM_SADDR_QUAD + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 16 + 1 + read-write + + + SPI_MEM_SCMD_QUAD + For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. + 17 + 1 + read-write + + + SPI_MEM_SDIN_OCT + For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. + 18 + 1 + read-write + + + SPI_MEM_SDOUT_OCT + For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. + 19 + 1 + read-write + + + SPI_MEM_SADDR_OCT + For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_SCMD_OCT + For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. + 21 + 1 + read-write + + + SPI_MEM_SDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 22 + 1 + read-write + + + SPI_MEM_SDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. + 23 + 1 + read-write + + + SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller. + 24 + 1 + read-write + + + SPI_SMEM_WDUMMY_ALWAYS_OUT + In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller. + 25 + 1 + read-write + + + SPI_MEM_SDIN_HEX + For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + 26 + 1 + read-write + + + SPI_MEM_SDOUT_HEX + For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + 27 + 1 + read-write + + + SPI_SMEM_DQS_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. + 30 + 1 + read-write + + + SPI_SMEM_DATA_IE_ALWAYS_ON + When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. + 31 + 1 + read-write + + + + + SPI_MEM_SRAM_DRD_CMD + SPI0 external RAM DDR read command control register + 0x48 + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE + For SPI0,When cache mode is enable it is the read command value of command phase for sram. + 0 + 16 + read-write + + + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN + For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SPI_MEM_SRAM_DWR_CMD + SPI0 external RAM DDR write command control register + 0x4C + 0x20 + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE + For SPI0,When cache mode is enable it is the write command value of command phase for sram. + 0 + 16 + read-write + + + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN + For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1). + 28 + 4 + read-write + + + + + SPI_MEM_SRAM_CLK + SPI0 external RAM clock control register + 0x50 + 0x20 + 0x00030103 + + + SPI_MEM_SCLKCNT_L + For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_SCLKCNT_H + For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_SCLKCNT_N + For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_SCLK_EQU_SYSCLK + For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock. + 31 + 1 + read-write + + + + + SPI_MEM_FSM + SPI0 FSM status register + 0x54 + 0x20 + 0x00000200 + + + SPI_MEM_LOCK_DELAY_TIME + The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. + 7 + 5 + read-write + + + + + SPI_MEM_INT_ENA + SPI0 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_ECC_ERR_INT_ENA + The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-write + + + SPI_MEM_PMS_REJECT_INT_ENA + The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-write + + + SPI_MEM_AXI_RADDR_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-write + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-write + + + SPI_MEM_AXI_WADDR_ERR_INT__ENA + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-write + + + SPI_MEM_DQS0_AFIFO_OVF_INT_ENA + The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + 28 + 1 + read-write + + + SPI_MEM_DQS1_AFIFO_OVF_INT_ENA + The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + 29 + 1 + read-write + + + SPI_MEM_BUS_FIFO1_UDF_INT_ENA + The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + 30 + 1 + read-write + + + SPI_MEM_BUS_FIFO0_UDF_INT_ENA + The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + 31 + 1 + read-write + + + + + SPI_MEM_INT_CLR + SPI0 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_ECC_ERR_INT_CLR + The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + write-only + + + SPI_MEM_PMS_REJECT_INT_CLR + The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + write-only + + + SPI_MEM_AXI_RADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + write-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + write-only + + + SPI_MEM_AXI_WADDR_ERR_INT_CLR + The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + write-only + + + SPI_MEM_DQS0_AFIFO_OVF_INT_CLR + The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + 28 + 1 + write-only + + + SPI_MEM_DQS1_AFIFO_OVF_INT_CLR + The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + 29 + 1 + write-only + + + SPI_MEM_BUS_FIFO1_UDF_INT_CLR + The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + 30 + 1 + write-only + + + SPI_MEM_BUS_FIFO0_UDF_INT_CLR + The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + 31 + 1 + write-only + + + + + SPI_MEM_INT_RAW + SPI0 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-write + + + SPI_MEM_ECC_ERR_INT_RAW + The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. + 5 + 1 + read-write + + + SPI_MEM_PMS_REJECT_INT_RAW + The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others. + 6 + 1 + read-write + + + SPI_MEM_AXI_RADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others. + 7 + 1 + read-write + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others. + 8 + 1 + read-write + + + SPI_MEM_AXI_WADDR_ERR_INT_RAW + The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others. + 9 + 1 + read-write + + + SPI_MEM_DQS0_AFIFO_OVF_INT_RAW + The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow. + 28 + 1 + read-write + + + SPI_MEM_DQS1_AFIFO_OVF_INT_RAW + The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow. + 29 + 1 + read-write + + + SPI_MEM_BUS_FIFO1_UDF_INT_RAW + The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow. + 30 + 1 + read-write + + + SPI_MEM_BUS_FIFO0_UDF_INT_RAW + The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow. + 31 + 1 + read-write + + + + + SPI_MEM_INT_ST + SPI0 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_ECC_ERR_INT_ST + The status bit for SPI_MEM_ECC_ERR_INT interrupt. + 5 + 1 + read-only + + + SPI_MEM_PMS_REJECT_INT_ST + The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + 6 + 1 + read-only + + + SPI_MEM_AXI_RADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + 7 + 1 + read-only + + + SPI_MEM_AXI_WR_FLASH_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + 8 + 1 + read-only + + + SPI_MEM_AXI_WADDR_ERR_INT_ST + The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + 9 + 1 + read-only + + + SPI_MEM_DQS0_AFIFO_OVF_INT_ST + The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + 28 + 1 + read-only + + + SPI_MEM_DQS1_AFIFO_OVF_INT_ST + The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + 29 + 1 + read-only + + + SPI_MEM_BUS_FIFO1_UDF_INT_ST + The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + 30 + 1 + read-only + + + SPI_MEM_BUS_FIFO0_UDF_INT_ST + The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + 31 + 1 + read-only + + + + + SPI_MEM_DDR + SPI0 flash DDR mode control register + 0xD4 + 0x20 + 0x00003020 + + + SPI_FMEM_DDR_EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash. + 12 + 1 + read-write + + + SPI_FMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash. + 13 + 1 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + SPI_SMEM_DDR + SPI0 external RAM DDR mode control register + 0xD8 + 0x20 + 0x00003020 + + + EN + 1: in DDR mode, 0 in SDR mode + 0 + 1 + read-write + + + SPI_SMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi DDR mode. + 1 + 1 + read-write + + + RDAT_SWP + Set the bit to reorder rx data of the word in spi DDR mode. + 2 + 1 + read-write + + + WDAT_SWP + Set the bit to reorder tx data of the word in spi DDR mode. + 3 + 1 + read-write + + + CMD_DIS + the bit is used to disable dual edge in command phase when DDR mode. + 4 + 1 + read-write + + + SPI_SMEM_OUTMINBYTELEN + It is the minimum output data length in the DDR psram. + 5 + 7 + read-write + + + SPI_SMEM_TX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM. + 12 + 1 + read-write + + + SPI_SMEM_RX_DDR_MSK_EN + Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM. + 13 + 1 + read-write + + + SPI_SMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-write + + + DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_SMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_SMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_SMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to external RAM. . + 28 + 1 + read-write + + + SPI_SMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_SMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ATTR + MSPI flash PMS section %s attribute register + 0x100 + 0x20 + 0x00000003 + + + SPI_FMEM_PMS_RD_ATTR + 1: SPI1 flash PMS section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_FMEM_PMS_WR_ATTR + 1: SPI1 flash PMS section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_FMEM_PMS_ECC + SPI1 flash PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_ADDR + SPI1 flash PMS section %s start address register + 0x110 + 0x20 + + + S + SPI1 flash PMS section %s start address value + 0 + 27 + read-write + + + + + 4 + 0x4 + SPI_FMEM_PMS%s_SIZE + SPI1 flash PMS section %s start address register + 0x120 + 0x20 + 0x00001000 + + + SPI_FMEM_PMS_SIZE + SPI1 flash PMS section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE) + 0 + 15 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ATTR + SPI1 flash PMS section %s start address register + 0x130 + 0x20 + 0x00000003 + + + SPI_SMEM_PMS_RD_ATTR + 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed. + 0 + 1 + read-write + + + SPI_SMEM_PMS_WR_ATTR + 1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed. + 1 + 1 + read-write + + + SPI_SMEM_PMS_ECC + SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG. + 2 + 1 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_ADDR + SPI1 external RAM PMS section %s start address register + 0x140 + 0x20 + + + S + SPI1 external RAM PMS section %s start address value + 0 + 27 + read-write + + + + + 4 + 0x4 + SPI_SMEM_PMS%s_SIZE + SPI1 external RAM PMS section %s start address register + 0x150 + 0x20 + 0x00001000 + + + SPI_SMEM_PMS_SIZE + SPI1 external RAM PMS section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE) + 0 + 15 + read-write + + + + + SPI_MEM_PMS_REJECT + SPI1 access reject register + 0x164 + 0x20 + + + SPI_MEM_REJECT_ADDR + This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 0 + 27 + read-only + + + SPI_MEM_PM_EN + Set this bit to enable SPI0/1 transfer permission control function. + 27 + 1 + read-write + + + SPI_MEM_PMS_LD + 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 28 + 1 + read-only + + + SPI_MEM_PMS_ST + 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 29 + 1 + read-only + + + SPI_MEM_PMS_MULTI_HIT + 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 30 + 1 + read-only + + + SPI_MEM_PMS_IVD + 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + 31 + 1 + read-only + + + + + SPI_MEM_ECC_CTRL + MSPI ECC control register + 0x168 + 0x20 + 0x01005000 + + + SPI_MEM_ECC_ERR_CNT + This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 5 + 6 + read-only + + + SPI_FMEM_ECC_ERR_INT_NUM + Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + 11 + 6 + read-write + + + SPI_FMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + 17 + 1 + read-write + + + SPI_FMEM_PAGE_SIZE + Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SPI_FMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-write + + + SPI_MEM_USR_ECC_ADDR_EN + Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + 21 + 1 + read-write + + + SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN + 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information. + 24 + 1 + read-write + + + SPI_MEM_ECC_ERR_BITS + Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7) + 25 + 7 + read-only + + + + + SPI_MEM_ECC_ERR_ADDR + MSPI ECC error address register + 0x16C + 0x20 + + + SPI_MEM_ECC_ERR_ADDR + This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + 0 + 27 + read-only + + + + + SPI_MEM_AXI_ERR_ADDR + SPI0 AXI request error address. + 0x170 + 0x20 + + + SPI_MEM_AXI_ERR_ADDR + This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. + 0 + 27 + read-only + + + + + SPI_SMEM_ECC_CTRL + MSPI ECC control register + 0x174 + 0x20 + 0x00080000 + + + SPI_SMEM_ECC_ERR_INT_EN + Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + 17 + 1 + read-write + + + SPI_SMEM_PAGE_SIZE + Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. + 18 + 2 + read-write + + + SPI_SMEM_ECC_ADDR_EN + Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1. + 20 + 1 + read-write + + + + + SPI_SMEM_AXI_ADDR_CTRL + SPI0 AXI address control register + 0x178 + 0x20 + 0xFC000000 + + + SPI_MEM_ALL_FIFO_EMPTY + The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others. + 26 + 1 + read-only + + + SPI_RDATA_AFIFO_REMPTY + 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. + 27 + 1 + read-only + + + SPI_RADDR_AFIFO_REMPTY + 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. + 28 + 1 + read-only + + + SPI_WDATA_AFIFO_REMPTY + 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. + 29 + 1 + read-only + + + SPI_WBLEN_AFIFO_REMPTY + 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. + 30 + 1 + read-only + + + SPI_ALL_AXI_TRANS_AFIFO_EMPTY + This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE. + 31 + 1 + read-only + + + + + SPI_MEM_AXI_ERR_RESP_EN + SPI0 AXI error response enable register + 0x17C + 0x20 + + + SPI_MEM_AW_RESP_EN_MMU_VLD + Set this bit to enable AXI response function for mmu valid err in axi write trans. + 0 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_MMU_GID + Set this bit to enable AXI response function for mmu gid err in axi write trans. + 1 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_AXI_SIZE + Set this bit to enable AXI response function for axi size err in axi write trans. + 2 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_AXI_FLASH + Set this bit to enable AXI response function for axi flash err in axi write trans. + 3 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_MMU_ECC + Set this bit to enable AXI response function for mmu ecc err in axi write trans. + 4 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_MMU_SENS + Set this bit to enable AXI response function for mmu sens in err axi write trans. + 5 + 1 + read-write + + + SPI_MEM_AW_RESP_EN_AXI_WSTRB + Set this bit to enable AXI response function for axi wstrb err in axi write trans. + 6 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_VLD + Set this bit to enable AXI response function for mmu valid err in axi read trans. + 7 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_GID + Set this bit to enable AXI response function for mmu gid err in axi read trans. + 8 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_ECC + Set this bit to enable AXI response function for mmu ecc err in axi read trans. + 9 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_MMU_SENS + Set this bit to enable AXI response function for mmu sensitive err in axi read trans. + 10 + 1 + read-write + + + SPI_MEM_AR_RESP_EN_AXI_SIZE + Set this bit to enable AXI response function for axi size err in axi read trans. + 11 + 1 + read-write + + + + + SPI_MEM_TIMING_CALI + SPI0 flash timing calibration register + 0x180 + 0x20 + 0x00000001 + + + SPI_MEM_TIMING_CLK_ENA + The bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-write + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + SPI_MEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash. + 5 + 1 + read-write + + + UPDATE + Set this bit to update delay mode, delay num and extra dummy in MSPI. + 6 + 1 + write-only + + + + + SPI_MEM_DIN_MODE + MSPI flash input timing delay mode control register + 0x184 + 0x20 + + + SPI_MEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_MEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_MEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_MEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_MEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 12 + 3 + read-write + + + SPI_MEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 15 + 3 + read-write + + + SPI_MEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 18 + 3 + read-write + + + SPI_MEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 21 + 3 + read-write + + + SPI_MEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk + 24 + 3 + read-write + + + + + SPI_MEM_DIN_NUM + MSPI flash input timing delay number control register + 0x188 + 0x20 + + + SPI_MEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_MEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_MEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_MEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_MEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_MEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_MEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_MEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_MEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_MEM_DOUT_MODE + MSPI flash output timing adjustment control register + 0x18C + 0x20 + + + SPI_MEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_MEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_MEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_MEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_MEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 4 + 1 + read-write + + + SPI_MEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 5 + 1 + read-write + + + SPI_MEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 6 + 1 + read-write + + + SPI_MEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 7 + 1 + read-write + + + SPI_MEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk + 8 + 1 + read-write + + + + + SPI_SMEM_TIMING_CALI + MSPI external RAM timing calibration register + 0x190 + 0x20 + 0x00000001 + + + SPI_SMEM_TIMING_CLK_ENA + For sram, the bit is used to enable timing adjust clock for all reading operations. + 0 + 1 + read-write + + + SPI_SMEM_TIMING_CALI + For sram, the bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_SMEM_EXTRA_DUMMY_CYCLELEN + For sram, add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + SPI_SMEM_DLL_TIMING_CALI + Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM. + 5 + 1 + read-write + + + + + SPI_SMEM_DIN_MODE + MSPI external RAM input timing delay mode control register + 0x194 + 0x20 + + + SPI_SMEM_DIN0_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_SMEM_DIN1_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_SMEM_DIN2_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_SMEM_DIN3_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_SMEM_DIN4_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 12 + 3 + read-write + + + SPI_SMEM_DIN5_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 15 + 3 + read-write + + + SPI_SMEM_DIN6_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 18 + 3 + read-write + + + SPI_SMEM_DIN7_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 21 + 3 + read-write + + + SPI_SMEM_DINS_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 24 + 3 + read-write + + + + + SPI_SMEM_DIN_NUM + MSPI external RAM input timing delay number control register + 0x198 + 0x20 + + + SPI_SMEM_DIN0_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_SMEM_DIN1_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_SMEM_DIN2_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_SMEM_DIN3_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_SMEM_DIN4_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_SMEM_DIN5_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_SMEM_DIN6_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_SMEM_DIN7_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_SMEM_DINS_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_SMEM_DOUT_MODE + MSPI external RAM output timing adjustment control register + 0x19C + 0x20 + + + SPI_SMEM_DOUT0_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_SMEM_DOUT1_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_SMEM_DOUT2_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_SMEM_DOUT3_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_SMEM_DOUT4_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 4 + 1 + read-write + + + SPI_SMEM_DOUT5_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 5 + 1 + read-write + + + SPI_SMEM_DOUT6_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 6 + 1 + read-write + + + SPI_SMEM_DOUT7_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 7 + 1 + read-write + + + SPI_SMEM_DOUTS_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 8 + 1 + read-write + + + + + SPI_SMEM_AC + MSPI external RAM ECC and SPI CS timing control register + 0x1A0 + 0x20 + 0x8000B084 + + + SPI_SMEM_CS_SETUP + For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + 0 + 1 + read-write + + + SPI_SMEM_CS_HOLD + For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. + 1 + 1 + read-write + + + SPI_SMEM_CS_SETUP_TIME + For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. + 2 + 5 + read-write + + + SPI_SMEM_CS_HOLD_TIME + For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. + 7 + 5 + read-write + + + SPI_SMEM_ECC_CS_HOLD_TIME + SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. + 12 + 3 + read-write + + + SPI_SMEM_ECC_SKIP_PAGE_CORNER + 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM. + 15 + 1 + read-write + + + SPI_SMEM_ECC_16TO18_BYTE_EN + Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. + 16 + 1 + read-write + + + SPI_SMEM_CS_HOLD_DELAY + These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + 25 + 6 + read-write + + + SPI_SMEM_SPLIT_TRANS_EN + Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not. + 31 + 1 + read-write + + + + + SPI_SMEM_DIN_HEX_MODE + MSPI 16x external RAM input timing delay mode control register + 0x1A4 + 0x20 + + + SPI_SMEM_DIN08_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 0 + 3 + read-write + + + SPI_SMEM_DIN09_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 3 + 3 + read-write + + + SPI_SMEM_DIN10_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 6 + 3 + read-write + + + SPI_SMEM_DIN11_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 9 + 3 + read-write + + + SPI_SMEM_DIN12_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 12 + 3 + read-write + + + SPI_SMEM_DIN13_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 15 + 3 + read-write + + + SPI_SMEM_DIN14_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 18 + 3 + read-write + + + SPI_SMEM_DIN15_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 21 + 3 + read-write + + + SPI_SMEM_DINS_HEX_MODE + the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge + 24 + 3 + read-write + + + + + SPI_SMEM_DIN_HEX_NUM + MSPI 16x external RAM input timing delay number control register + 0x1A8 + 0x20 + + + SPI_SMEM_DIN08_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 0 + 2 + read-write + + + SPI_SMEM_DIN09_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 2 + 2 + read-write + + + SPI_SMEM_DIN10_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 4 + 2 + read-write + + + SPI_SMEM_DIN11_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 6 + 2 + read-write + + + SPI_SMEM_DIN12_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 8 + 2 + read-write + + + SPI_SMEM_DIN13_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 10 + 2 + read-write + + + SPI_SMEM_DIN14_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 12 + 2 + read-write + + + SPI_SMEM_DIN15_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 14 + 2 + read-write + + + SPI_SMEM_DINS_HEX_NUM + the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... + 16 + 2 + read-write + + + + + SPI_SMEM_DOUT_HEX_MODE + MSPI 16x external RAM output timing adjustment control register + 0x1AC + 0x20 + + + SPI_SMEM_DOUT08_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 0 + 1 + read-write + + + SPI_SMEM_DOUT09_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 1 + 1 + read-write + + + SPI_SMEM_DOUT10_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 2 + 1 + read-write + + + SPI_SMEM_DOUT11_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 3 + 1 + read-write + + + SPI_SMEM_DOUT12_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 4 + 1 + read-write + + + SPI_SMEM_DOUT13_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 5 + 1 + read-write + + + SPI_SMEM_DOUT14_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 6 + 1 + read-write + + + SPI_SMEM_DOUT15_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 7 + 1 + read-write + + + SPI_SMEM_DOUTS_HEX_MODE + the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge + 8 + 1 + read-write + + + + + SPI_MEM_CLOCK_GATE + SPI0 clock gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PLAIN_BASE + The base address of the memory that stores plaintext in Manual Encryption + 0x300 + 0x20 + + + SPI_XTS_PLAIN + This field is only used to generate include file in c case. This field is useless. Please do not use this field. + 0 + 32 + read-write + + + + + SPI_MEM_XTS_LINESIZE + Manual Encryption Line-Size register + 0x340 + 0x20 + + + SPI_XTS_LINESIZE + This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved. + 0 + 2 + read-write + + + + + SPI_MEM_XTS_DESTINATION + Manual Encryption destination register + 0x344 + 0x20 + + + SPI_XTS_DESTINATION + This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. + 0 + 1 + read-write + + + + + SPI_MEM_XTS_PHYSICAL_ADDRESS + Manual Encryption physical address register + 0x348 + 0x20 + + + SPI_XTS_PHYSICAL_ADDRESS + This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter. + 0 + 26 + read-write + + + + + SPI_MEM_XTS_TRIGGER + Manual Encryption physical address register + 0x34C + 0x20 + + + SPI_XTS_TRIGGER + Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_RELEASE + Manual Encryption physical address register + 0x350 + 0x20 + + + SPI_XTS_RELEASE + Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_DESTROY + Manual Encryption physical address register + 0x354 + 0x20 + + + SPI_XTS_DESTROY + Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0. + 0 + 1 + write-only + + + + + SPI_MEM_XTS_STATE + Manual Encryption physical address register + 0x358 + 0x20 + + + SPI_XTS_STATE + This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi. + 0 + 2 + read-only + + + + + SPI_MEM_XTS_DATE + Manual Encryption version register + 0x35C + 0x20 + 0x20201010 + + + SPI_XTS_DATE + This bits stores the last modified-time of manual encryption feature. + 0 + 30 + read-write + + + + + SPI_MEM_MMU_ITEM_CONTENT + MSPI-MMU item content register + 0x37C + 0x20 + 0x0000037C + + + SPI_MMU_ITEM_CONTENT + MSPI-MMU item content + 0 + 32 + read-write + + + + + SPI_MEM_MMU_ITEM_INDEX + MSPI-MMU item index register + 0x380 + 0x20 + + + SPI_MMU_ITEM_INDEX + MSPI-MMU item index + 0 + 32 + read-write + + + + + SPI_MEM_MMU_POWER_CTRL + MSPI MMU power control register + 0x384 + 0x20 + 0x13200004 + + + SPI_MMU_MEM_FORCE_ON + Set this bit to enable mmu-memory clock force on + 0 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PD + Set this bit to force mmu-memory powerdown + 1 + 1 + read-write + + + SPI_MMU_MEM_FORCE_PU + Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc. + 2 + 1 + read-write + + + SPI_MEM_AUX_CTRL + MMU PSRAM aux control register + 16 + 14 + read-write + + + SPI_MEM_RDN_ENA + ECO register enable bit + 30 + 1 + read-write + + + SPI_MEM_RDN_RESULT + MSPI module clock domain and AXI clock domain ECO register result register + 31 + 1 + read-only + + + + + SPI_MEM_DPA_CTRL + SPI memory cryption DPA register + 0x388 + 0x20 + 0x0000000F + + + SPI_CRYPT_SECURITY_LEVEL + Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing) + 0 + 3 + read-write + + + SPI_CRYPT_CALC_D_DPA_EN + Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1. + 3 + 1 + read-write + + + SPI_CRYPT_DPA_SELECT_REGISTER + 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. + 4 + 1 + read-write + + + + + SPI_MEM_REGISTERRND_ECO_HIGH + MSPI ECO high register + 0x3F0 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_HIGH + ECO high register + 0 + 32 + read-write + + + + + SPI_MEM_REGISTERRND_ECO_LOW + MSPI ECO low register + 0x3F4 + 0x20 + 0x0000037C + + + SPI_MEM_REGISTERRND_ECO_LOW + ECO low register + 0 + 32 + read-write + + + + + SPI_MEM_DATE + SPI0 version control register + 0x3FC + 0x20 + 0x02303100 + + + SPI_MEM_DATE + SPI0 register version. + 0 + 28 + read-write + + + + + + + SPI1 + SPI (Serial Peripheral Interface) Controller 1 + SPI1 + 0x5008D000 + + 0x0 + 0xAC + registers + + + + SPI_MEM_CMD + SPI1 memory command register + 0x0 + 0x20 + + + SPI_MEM_MST_ST + The current status of SPI1 master FSM. + 0 + 4 + read-only + + + SPI_MEM_SLV_ST + The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. + 4 + 4 + read-only + + + SPI_MEM_FLASH_PE + In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. + 17 + 1 + read-write + + + SPI_MEM_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 18 + 1 + read-write + + + SPI_MEM_FLASH_HPM + Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. + 19 + 1 + read-write + + + SPI_MEM_FLASH_RES + This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_FLASH_DP + Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 21 + 1 + read-write + + + SPI_MEM_FLASH_CE + Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FLASH_BE + Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FLASH_SE + Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_FLASH_PP + Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. + 25 + 1 + read-write + + + SPI_MEM_FLASH_WRSR + Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 26 + 1 + read-write + + + SPI_MEM_FLASH_RDSR + Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 27 + 1 + read-write + + + SPI_MEM_FLASH_RDID + Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 28 + 1 + read-write + + + SPI_MEM_FLASH_WRDI + Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 29 + 1 + read-write + + + SPI_MEM_FLASH_WREN + Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 30 + 1 + read-write + + + SPI_MEM_FLASH_READ + Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. + 31 + 1 + read-write + + + + + SPI_MEM_ADDR + SPI1 address register + 0x4 + 0x20 + + + SPI_MEM_USR_ADDR_VALUE + In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. + 0 + 32 + read-write + + + + + SPI_MEM_CTRL + SPI1 control register. + 0x8 + 0x20 + 0x002CA00C + + + SPI_MEM_FDUMMY_RIN + In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 2 + 1 + read-write + + + SPI_MEM_FDUMMY_WOUT + In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_OCT + Apply 8 signals during write-data phase 1:enable 0: disable + 4 + 1 + read-write + + + SPI_MEM_FDIN_OCT + Apply 8 signals during read-data phase 1:enable 0: disable + 5 + 1 + read-write + + + SPI_MEM_FADDR_OCT + Apply 8 signals during address phase 1:enable 0: disable + 6 + 1 + read-write + + + SPI_MEM_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable + 8 + 1 + read-write + + + SPI_MEM_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable + 9 + 1 + read-write + + + SPI_MEM_FCS_CRC_EN + For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. + 10 + 1 + read-write + + + SPI_MEM_TX_CRC_EN + For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + 11 + 1 + read-write + + + SPI_MEM_FASTRD_MODE + This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. + 13 + 1 + read-write + + + SPI_MEM_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. + 14 + 1 + read-write + + + SPI_MEM_RESANDRES + The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. + 15 + 1 + read-write + + + SPI_MEM_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low + 18 + 1 + read-write + + + SPI_MEM_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low + 19 + 1 + read-write + + + SPI_MEM_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. + 20 + 1 + read-write + + + SPI_MEM_WP + Write protect signal output when SPI is idle. 1: output high, 0: output low. + 21 + 1 + read-write + + + SPI_MEM_WRSR_2B + two bytes data will be written to status register when it is set. 1: enable 0: disable. + 22 + 1 + read-write + + + SPI_MEM_FREAD_DIO + In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. + 23 + 1 + read-write + + + SPI_MEM_FREAD_QIO + In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. + 24 + 1 + read-write + + + + + SPI_MEM_CTRL1 + SPI1 control1 register. + 0xC + 0x20 + 0x00000FFC + + + SPI_MEM_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. + 0 + 2 + read-write + + + SPI_MEM_CS_HOLD_DLY_RES + After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. + 2 + 10 + read-write + + + + + SPI_MEM_CTRL2 + SPI1 control2 register. + 0x10 + 0x20 + + + SPI_MEM_SYNC_RESET + The FSM will be reset. + 31 + 1 + write-only + + + + + SPI_MEM_CLOCK + SPI1 clock division control register. + 0x14 + 0x20 + 0x00030103 + + + SPI_MEM_CLKCNT_L + In the master mode it must be equal to spi_mem_clkcnt_N. + 0 + 8 + read-write + + + SPI_MEM_CLKCNT_H + In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + 8 + 8 + read-write + + + SPI_MEM_CLKCNT_N + In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + 16 + 8 + read-write + + + SPI_MEM_CLK_EQU_SYSCLK + reserved + 31 + 1 + read-write + + + + + SPI_MEM_USER + SPI1 user register. + 0x18 + 0x20 + 0x80000000 + + + SPI_MEM_CK_OUT_EDGE + the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + 9 + 1 + read-write + + + SPI_MEM_FWRITE_DUAL + In the write operations read-data phase apply 2 signals + 12 + 1 + read-write + + + SPI_MEM_FWRITE_QUAD + In the write operations read-data phase apply 4 signals + 13 + 1 + read-write + + + SPI_MEM_FWRITE_DIO + In the write operations address phase and read-data phase apply 2 signals. + 14 + 1 + read-write + + + SPI_MEM_FWRITE_QIO + In the write operations address phase and read-data phase apply 4 signals. + 15 + 1 + read-write + + + SPI_MEM_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 24 + 1 + read-write + + + SPI_MEM_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. + 25 + 1 + read-write + + + SPI_MEM_USR_DUMMY_IDLE + SPI clock is disable in dummy phase when the bit is enable. + 26 + 1 + read-write + + + SPI_MEM_USR_MOSI + This bit enable the write-data phase of an operation. + 27 + 1 + read-write + + + SPI_MEM_USR_MISO + This bit enable the read-data phase of an operation. + 28 + 1 + read-write + + + SPI_MEM_USR_DUMMY + This bit enable the dummy phase of an operation. + 29 + 1 + read-write + + + SPI_MEM_USR_ADDR + This bit enable the address phase of an operation. + 30 + 1 + read-write + + + SPI_MEM_USR_COMMAND + This bit enable the command phase of an operation. + 31 + 1 + read-write + + + + + SPI_MEM_USER1 + SPI1 user1 register. + 0x1C + 0x20 + 0x5C000007 + + + SPI_MEM_USR_DUMMY_CYCLELEN + The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + 0 + 6 + read-write + + + SPI_MEM_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). + 26 + 6 + read-write + + + + + SPI_MEM_USER2 + SPI1 user2 register. + 0x20 + 0x20 + 0x70000000 + + + SPI_MEM_USR_COMMAND_VALUE + The value of command. + 0 + 16 + read-write + + + SPI_MEM_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1) + 28 + 4 + read-write + + + + + SPI_MEM_MOSI_DLEN + SPI1 send data bit length control register. + 0x24 + 0x20 + + + SPI_MEM_USR_MOSI_DBITLEN + The length in bits of write-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_MISO_DLEN + SPI1 receive data bit length control register. + 0x28 + 0x20 + + + SPI_MEM_USR_MISO_DBITLEN + The length in bits of read-data. The register value shall be (bit_num-1). + 0 + 10 + read-write + + + + + SPI_MEM_RD_STATUS + SPI1 status register. + 0x2C + 0x20 + + + SPI_MEM_STATUS + The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + 0 + 16 + read-write + + + SPI_MEM_WB_MODE + Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + 16 + 8 + read-write + + + + + SPI_MEM_MISC + SPI1 misc register + 0x34 + 0x20 + 0x00000002 + + + SPI_MEM_CS0_DIS + SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. + 0 + 1 + read-write + + + SPI_MEM_CS1_DIS + SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. + 1 + 1 + read-write + + + SPI_MEM_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle + 9 + 1 + read-write + + + SPI_MEM_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. + 10 + 1 + read-write + + + + + SPI_MEM_TX_CRC + SPI1 TX CRC data register. + 0x38 + 0x20 + 0xFFFFFFFF + + + DATA + For SPI1, the value of crc32. + 0 + 32 + read-only + + + + + SPI_MEM_CACHE_FCTRL + SPI1 bit mode control register. + 0x3C + 0x20 + + + SPI_MEM_CACHE_USR_ADDR_4BYTE + For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + 1 + 1 + read-write + + + SPI_MEM_FDIN_DUAL + For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 3 + 1 + read-write + + + SPI_MEM_FDOUT_DUAL + For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 4 + 1 + read-write + + + SPI_MEM_FADDR_DUAL + For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. + 5 + 1 + read-write + + + SPI_MEM_FDIN_QUAD + For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 6 + 1 + read-write + + + SPI_MEM_FDOUT_QUAD + For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 7 + 1 + read-write + + + SPI_MEM_FADDR_QUAD + For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. + 8 + 1 + read-write + + + + + SPI_MEM_W0 + SPI1 memory data buffer0 + 0x58 + 0x20 + + + SPI_MEM_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W1 + SPI1 memory data buffer1 + 0x5C + 0x20 + + + SPI_MEM_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W2 + SPI1 memory data buffer2 + 0x60 + 0x20 + + + SPI_MEM_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W3 + SPI1 memory data buffer3 + 0x64 + 0x20 + + + SPI_MEM_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W4 + SPI1 memory data buffer4 + 0x68 + 0x20 + + + SPI_MEM_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W5 + SPI1 memory data buffer5 + 0x6C + 0x20 + + + SPI_MEM_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W6 + SPI1 memory data buffer6 + 0x70 + 0x20 + + + SPI_MEM_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W7 + SPI1 memory data buffer7 + 0x74 + 0x20 + + + SPI_MEM_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W8 + SPI1 memory data buffer8 + 0x78 + 0x20 + + + SPI_MEM_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W9 + SPI1 memory data buffer9 + 0x7C + 0x20 + + + SPI_MEM_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W10 + SPI1 memory data buffer10 + 0x80 + 0x20 + + + SPI_MEM_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W11 + SPI1 memory data buffer11 + 0x84 + 0x20 + + + SPI_MEM_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W12 + SPI1 memory data buffer12 + 0x88 + 0x20 + + + SPI_MEM_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W13 + SPI1 memory data buffer13 + 0x8C + 0x20 + + + SPI_MEM_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W14 + SPI1 memory data buffer14 + 0x90 + 0x20 + + + SPI_MEM_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_W15 + SPI1 memory data buffer15 + 0x94 + 0x20 + + + SPI_MEM_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_MEM_FLASH_WAITI_CTRL + SPI1 wait idle control register + 0x98 + 0x20 + 0x00050001 + + + SPI_MEM_WAITI_EN + 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported. + 0 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY + The dummy phase enable when wait flash idle (RDSR) + 1 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_EN + 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer. + 2 + 1 + read-write + + + SPI_MEM_WAITI_ADDR_CYCLELEN + When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared. + 3 + 2 + read-write + + + SPI_MEM_WAITI_CMD_2B + 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. + 9 + 1 + read-write + + + SPI_MEM_WAITI_DUMMY_CYCLELEN + The dummy cycle length when wait flash idle(RDSR). + 10 + 6 + read-write + + + SPI_MEM_WAITI_CMD + The command value to wait flash idle(RDSR). + 16 + 16 + read-write + + + + + SPI_MEM_FLASH_SUS_CTRL + SPI1 flash suspend control register + 0x9C + 0x20 + 0x08002000 + + + SPI_MEM_FLASH_PER + program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 0 + 1 + read-write + + + SPI_MEM_FLASH_PES + program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + 1 + 1 + read-write + + + SPI_MEM_FLASH_PER_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_PES_WAIT_EN + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. + 3 + 1 + read-write + + + SPI_MEM_PES_PER_EN + Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PES_EN + Set this bit to enable Auto-suspending function. + 5 + 1 + read-write + + + SPI_MEM_PESR_END_MSK + The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. + 6 + 16 + read-write + + + SPI_FMEM_RD_SUS_2B + 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit + 22 + 1 + read-write + + + SPI_MEM_PER_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. + 23 + 1 + read-write + + + SPI_MEM_PES_END_EN + 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. + 24 + 1 + read-write + + + SPI_MEM_SUS_TIMEOUT_CNT + When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. + 25 + 7 + read-write + + + + + SPI_MEM_FLASH_SUS_CMD + SPI1 flash suspend command register + 0xA0 + 0x20 + 0x00057575 + + + SPI_MEM_FLASH_PES_COMMAND + Program/Erase suspend command. + 0 + 16 + read-write + + + SPI_MEM_WAIT_PESR_COMMAND + Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + 16 + 16 + read-write + + + + + SPI_MEM_SUS_STATUS + SPI1 flash suspend status register + 0xA4 + 0x20 + 0x7A7A0000 + + + SPI_MEM_FLASH_SUS + The status of flash suspend, only used in SPI1. + 0 + 1 + read-write + + + SPI_MEM_WAIT_PESR_CMD_2B + 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. + 1 + 1 + read-write + + + SPI_MEM_FLASH_HPM_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. + 2 + 1 + read-write + + + SPI_MEM_FLASH_RES_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. + 3 + 1 + read-write + + + SPI_MEM_FLASH_DP_DLY_128 + 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. + 4 + 1 + read-write + + + SPI_MEM_FLASH_PER_DLY_128 + Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. + 5 + 1 + read-write + + + SPI_MEM_FLASH_PES_DLY_128 + Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. + 6 + 1 + read-write + + + SPI_MEM_SPI0_LOCK_EN + 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. + 7 + 1 + read-write + + + SPI_MEM_FLASH_PESR_CMD_2B + 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8. + 15 + 1 + read-write + + + SPI_MEM_FLASH_PER_COMMAND + Program/Erase resume command. + 16 + 16 + read-write + + + + + SPI_MEM_INT_ENA + SPI1 interrupt enable register + 0xC0 + 0x20 + + + SPI_MEM_PER_END_INT_ENA + The enable bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-write + + + SPI_MEM_PES_END_INT_ENA + The enable bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-write + + + SPI_MEM_WPE_END_INT_ENA + The enable bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-write + + + SPI_MEM_SLV_ST_END_INT_ENA + The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_ENA + The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-write + + + SPI_MEM_BROWN_OUT_INT_ENA + The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-write + + + + + SPI_MEM_INT_CLR + SPI1 interrupt clear register + 0xC4 + 0x20 + + + SPI_MEM_PER_END_INT_CLR + The clear bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + write-only + + + SPI_MEM_PES_END_INT_CLR + The clear bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + write-only + + + SPI_MEM_WPE_END_INT_CLR + The clear bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + write-only + + + SPI_MEM_SLV_ST_END_INT_CLR + The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + write-only + + + SPI_MEM_MST_ST_END_INT_CLR + The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + write-only + + + SPI_MEM_BROWN_OUT_INT_CLR + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + write-only + + + + + SPI_MEM_INT_RAW + SPI1 interrupt raw register + 0xC8 + 0x20 + + + SPI_MEM_PER_END_INT_RAW + The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. + 0 + 1 + read-write + + + SPI_MEM_PES_END_INT_RAW + The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. + 1 + 1 + read-write + + + SPI_MEM_WPE_END_INT_RAW + The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. + 2 + 1 + read-write + + + SPI_MEM_SLV_ST_END_INT_RAW + The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others + 3 + 1 + read-write + + + SPI_MEM_MST_ST_END_INT_RAW + The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. + 4 + 1 + read-write + + + SPI_MEM_BROWN_OUT_INT_RAW + The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. + 10 + 1 + read-write + + + + + SPI_MEM_INT_ST + SPI1 interrupt status register + 0xCC + 0x20 + + + SPI_MEM_PER_END_INT_ST + The status bit for SPI_MEM_PER_END_INT interrupt. + 0 + 1 + read-only + + + SPI_MEM_PES_END_INT_ST + The status bit for SPI_MEM_PES_END_INT interrupt. + 1 + 1 + read-only + + + SPI_MEM_WPE_END_INT_ST + The status bit for SPI_MEM_WPE_END_INT interrupt. + 2 + 1 + read-only + + + SPI_MEM_SLV_ST_END_INT_ST + The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + 3 + 1 + read-only + + + SPI_MEM_MST_ST_END_INT_ST + The status bit for SPI_MEM_MST_ST_END_INT interrupt. + 4 + 1 + read-only + + + SPI_MEM_BROWN_OUT_INT_ST + The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + 10 + 1 + read-only + + + + + SPI_MEM_DDR + SPI1 DDR control register + 0xD4 + 0x20 + 0x00000020 + + + SPI_FMEM_DDR_EN + 1: in ddr mode, 0 in sdr mode + 0 + 1 + read-write + + + SPI_FMEM_VAR_DUMMY + Set the bit to enable variable dummy cycle in spi ddr mode. + 1 + 1 + read-write + + + SPI_FMEM_DDR_RDAT_SWP + Set the bit to reorder rx data of the word in spi ddr mode. + 2 + 1 + read-write + + + SPI_FMEM_DDR_WDAT_SWP + Set the bit to reorder tx data of the word in spi ddr mode. + 3 + 1 + read-write + + + SPI_FMEM_DDR_CMD_DIS + the bit is used to disable dual edge in command phase when ddr mode. + 4 + 1 + read-write + + + SPI_FMEM_OUTMINBYTELEN + It is the minimum output data length in the panda device. + 5 + 7 + read-write + + + SPI_FMEM_USR_DDR_DQS_THD + The delay number of data strobe which from memory based on SPI clock. + 14 + 7 + read-write + + + SPI_FMEM_DDR_DQS_LOOP + 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. + 21 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_EN + Set this bit to enable the differential SPI_CLK#. + 24 + 1 + read-write + + + SPI_FMEM_DQS_CA_IN + Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + 26 + 1 + read-write + + + SPI_FMEM_HYPERBUS_DUMMY_2X + Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + 27 + 1 + read-write + + + SPI_FMEM_CLK_DIFF_INV + Set this bit to invert SPI_DIFF when accesses to flash. . + 28 + 1 + read-write + + + SPI_FMEM_OCTA_RAM_ADDR + Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. + 29 + 1 + read-write + + + SPI_FMEM_HYPERBUS_CA + Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. + 30 + 1 + read-write + + + + + SPI_MEM_TIMING_CALI + SPI1 timing control register + 0x180 + 0x20 + + + SPI_MEM_TIMING_CALI + The bit is used to enable timing auto-calibration for all reading operations. + 1 + 1 + read-write + + + SPI_MEM_EXTRA_DUMMY_CYCLELEN + add extra dummy spi clock cycle length for spi clock calibration. + 2 + 3 + read-write + + + + + SPI_MEM_CLOCK_GATE + SPI1 clk_gate register + 0x200 + 0x20 + 0x00000001 + + + SPI_MEM_CLK_EN + Register clock gate enable signal. 1: Enable. 0: Disable. + 0 + 1 + read-write + + + + + SPI_MEM_DATE + Version control register + 0x3FC + 0x20 + 0x02111240 + + + SPI_MEM_DATE + Version control register + 0 + 28 + read-write + + + + + + + SPI2 + SPI (Serial Peripheral Interface) Controller 2 + SPI2 + 0x500D0000 + + 0x0 + 0x98 + registers + + + SPI2 + 25 + + + + SPI_CMD + Command control register + 0x0 + 0x20 + + + SPI_CONF_BITLEN + Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + 0 + 18 + read-write + + + SPI_UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + write-only + + + SPI_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + SPI_ADDR + Address value register + 0x4 + 0x20 + + + SPI_USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + SPI_CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + SPI_DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_FADDR_OCT + Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + SPI_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FCMD_OCT + Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 10 + 1 + read-write + + + SPI_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + SPI_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_FREAD_OCT + In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. + 16 + 1 + read-write + + + SPI_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + SPI_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + SPI_HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + SPI_WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + SPI_RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + SPI_WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + SPI_CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + SPI_CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + SPI_CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + SPI_CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + SPI_CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + SPI_CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + SPI_DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_OPI_MODE + Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. + 4 + 1 + read-write + + + SPI_TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + SPI_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + SPI_CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + SPI_FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + SPI_FWRITE_OCT + In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + 14 + 1 + read-write + + + SPI_USR_CONF_NXT + 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + SPI_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + SPI_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + SPI_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + SPI_USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + SPI_USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + SPI_USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + SPI_USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + SPI_MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + SPI_CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + SPI_CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + SPI_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + SPI_USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + SPI_USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + SPI_MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + SPI_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + SPI_MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + SPI_MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + SPI_MISC + SPI misc register + 0x20 + 0x20 + 0x0000003E + + + SPI_CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_CS3_DIS + SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_CS4_DIS + SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. + 4 + 1 + read-write + + + SPI_CS5_DIS + SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 6 + read-write + + + SPI_CLK_DATA_DTR_EN + 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + 16 + 1 + read-write + + + SPI_DATA_DTR_EN + 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. + 17 + 1 + read-write + + + SPI_ADDR_DTR_EN + 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. + 18 + 1 + read-write + + + SPI_CMD_DTR_EN + 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. + 19 + 1 + read-write + + + SPI_SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + SPI_DQS_IDLE_EDGE + The default value of spi_dqs. Can be configured in CONF state. + 24 + 1 + read-write + + + SPI_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_QUAD_DIN_PIN_SWAP + 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + SPI_DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_DIN4_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 8 + 2 + read-write + + + SPI_DIN5_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 10 + 2 + read-write + + + SPI_DIN6_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 12 + 2 + read-write + + + SPI_DIN7_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 14 + 2 + read-write + + + SPI_TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + SPI_DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + SPI_DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_DIN4_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 8 + 2 + read-write + + + SPI_DIN5_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 10 + 2 + read-write + + + SPI_DIN6_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 12 + 2 + read-write + + + SPI_DIN7_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 14 + 2 + read-write + + + + + SPI_DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + SPI_DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_DOUT4_MODE + The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 4 + 1 + read-write + + + SPI_DOUT5_MODE + The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_DOUT6_MODE + The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_DOUT7_MODE + The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_D_DQS_MODE + The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 8 + 1 + read-write + + + + + SPI_DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + SPI_DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + SPI_DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + SPI_DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SPI_SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SPI_SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + SPI_RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + SPI_DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + SPI_DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + SPI_RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + SPI_BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + SPI_DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + SPI_DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SPI_SEG_MAGIC_ERR_INT_ENA + The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + SPI_APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + SPI_APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + SPI_DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SEG_MAGIC_ERR_INT_CLR + The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-write + + + SPI_SEG_MAGIC_ERR_INT_RAW + The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. + 14 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-write + + + SPI_APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-write + + + SPI_APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-write + + + + + SPI_DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SPI_SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SPI_SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SPI_SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SPI_SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SPI_SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SPI_SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SPI_SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SPI_SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SPI_SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SPI_SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + SPI_TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + SPI_DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SPI_SEG_MAGIC_ERR_INT_ST + The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + read-only + + + SPI_SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SPI_SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + SPI_APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + SPI_APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + SPI_DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SEG_MAGIC_ERR_INT_SET + The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + 14 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + SPI_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + SPI_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + SPI_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + SPI_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + SPI_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + SPI_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + SPI_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + SPI_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + SPI_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + SPI_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + SPI_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + SPI_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + SPI_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + SPI_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + SPI_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + SPI_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_SLAVE + SPI slave control register + 0xE0 + 0x20 + 0x02800000 + + + SPI_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + SPI_RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SPI_SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SPI_SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SPI_SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SPI_SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + SPI_SLV_LAST_BYTE_STRB + Represents the effective bit of the last received data byte in SPI slave FD and HD mode. + 12 + 8 + read-only + + + SPI_DMA_SEG_MAGIC_VALUE + The magic value of BM table in master DMA seg-trans. + 22 + 4 + read-write + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SPI_SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + SPI_USR_CONF + 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. + 28 + 1 + read-write + + + SPI_MST_FD_WAIT_DMA_TX_DATA + In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. + 29 + 1 + read-write + + + + + SPI_SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SPI_SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SPI_SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SPI_SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + SPI_CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + SPI_CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + SPI_MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + SPI_MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + SPI_DATE + Version control + 0xF0 + 0x20 + 0x02207202 + + + SPI_DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SPI3 + SPI (Serial Peripheral Interface) Controller 3 + SPI3 + 0x500D1000 + + 0x0 + 0x98 + registers + + + SPI3 + 26 + + + + SPI_CMD + Command control register + 0x0 + 0x20 + + + SPI_UPDATE + Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. + 23 + 1 + write-only + + + SPI_USR + User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. + 24 + 1 + read-write + + + + + SPI_ADDR + Address value register + 0x4 + 0x20 + + + SPI_USR_ADDR_VALUE + Address to slave. Can be configured in CONF state. + 0 + 32 + read-write + + + + + SPI_CTRL + SPI control register + 0x8 + 0x20 + 0x003C0000 + + + SPI_DUMMY_OUT + 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_FADDR_DUAL + Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 5 + 1 + read-write + + + SPI_FADDR_QUAD + Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_FCMD_DUAL + Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 8 + 1 + read-write + + + SPI_FCMD_QUAD + Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FREAD_DUAL + In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. + 14 + 1 + read-write + + + SPI_FREAD_QUAD + In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. + 15 + 1 + read-write + + + SPI_Q_POL + The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. + 18 + 1 + read-write + + + SPI_D_POL + The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. + 19 + 1 + read-write + + + SPI_HOLD_POL + SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 20 + 1 + read-write + + + SPI_WP_POL + Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. + 21 + 1 + read-write + + + SPI_RD_BIT_ORDER + In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. + 23 + 2 + read-write + + + SPI_WR_BIT_ORDER + In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. + 25 + 2 + read-write + + + + + SPI_CLOCK + SPI clock control register + 0xC + 0x20 + 0x80003043 + + + SPI_CLKCNT_L + In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + 0 + 6 + read-write + + + SPI_CLKCNT_H + In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + 6 + 6 + read-write + + + SPI_CLKCNT_N + In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + 12 + 6 + read-write + + + SPI_CLKDIV_PRE + In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + 18 + 4 + read-write + + + SPI_CLK_EQU_SYSCLK + In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER + SPI USER control register + 0x10 + 0x20 + 0x800000C0 + + + SPI_DOUTDIN + Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_QPI_MODE + Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. + 3 + 1 + read-write + + + SPI_TSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + 5 + 1 + read-write + + + SPI_CS_HOLD + spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_CS_SETUP + spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. + 7 + 1 + read-write + + + SPI_RSCK_I_EDGE + In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + 8 + 1 + read-write + + + SPI_CK_OUT_EDGE + the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + 9 + 1 + read-write + + + SPI_FWRITE_DUAL + In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + 12 + 1 + read-write + + + SPI_FWRITE_QUAD + In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + 13 + 1 + read-write + + + SPI_SIO + Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. + 17 + 1 + read-write + + + SPI_USR_MISO_HIGHPART + read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 24 + 1 + read-write + + + SPI_USR_MOSI_HIGHPART + write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. + 25 + 1 + read-write + + + SPI_USR_DUMMY_IDLE + spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + 26 + 1 + read-write + + + SPI_USR_MOSI + This bit enable the write-data phase of an operation. Can be configured in CONF state. + 27 + 1 + read-write + + + SPI_USR_MISO + This bit enable the read-data phase of an operation. Can be configured in CONF state. + 28 + 1 + read-write + + + SPI_USR_DUMMY + This bit enable the dummy phase of an operation. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_USR_ADDR + This bit enable the address phase of an operation. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_USR_COMMAND + This bit enable the command phase of an operation. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_USER1 + SPI USER control register 1 + 0x14 + 0x20 + 0xB8410007 + + + SPI_USR_DUMMY_CYCLELEN + The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + 0 + 8 + read-write + + + SPI_MST_WFULL_ERR_END_EN + 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. + 16 + 1 + read-write + + + SPI_CS_SETUP_TIME + (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + 17 + 5 + read-write + + + SPI_CS_HOLD_TIME + delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + 22 + 5 + read-write + + + SPI_USR_ADDR_BITLEN + The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 27 + 5 + read-write + + + + + SPI_USER2 + SPI USER control register 2 + 0x18 + 0x20 + 0x78000000 + + + SPI_USR_COMMAND_VALUE + The value of command. Can be configured in CONF state. + 0 + 16 + read-write + + + SPI_MST_REMPTY_ERR_END_EN + 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. + 27 + 1 + read-write + + + SPI_USR_COMMAND_BITLEN + The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + 28 + 4 + read-write + + + + + SPI_MS_DLEN + SPI data bit length control register + 0x1C + 0x20 + + + SPI_MS_DATA_BITLEN + The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + 0 + 18 + read-write + + + + + SPI_MISC + SPI misc register + 0x20 + 0x20 + 0x00000006 + + + SPI_CS0_DIS + SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_CS1_DIS + SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_CS2_DIS + SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_CK_DIS + 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + 6 + 1 + read-write + + + SPI_MASTER_CS_POL + In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + 7 + 3 + read-write + + + SPI_SLAVE_CS_POL + spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. + 23 + 1 + read-write + + + SPI_CK_IDLE_EDGE + 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. + 29 + 1 + read-write + + + SPI_CS_KEEP_ACTIVE + spi cs line keep low when the bit is set. Can be configured in CONF state. + 30 + 1 + read-write + + + SPI_QUAD_DIN_PIN_SWAP + 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state. + 31 + 1 + read-write + + + + + SPI_DIN_MODE + SPI input delay mode configuration + 0x24 + 0x20 + + + SPI_DIN0_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_MODE + the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. + 6 + 2 + read-write + + + SPI_TIMING_HCLK_ACTIVE + 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. + 16 + 1 + read-write + + + + + SPI_DIN_NUM + SPI input delay number configuration + 0x28 + 0x20 + + + SPI_DIN0_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_DIN1_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 2 + 2 + read-write + + + SPI_DIN2_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 4 + 2 + read-write + + + SPI_DIN3_NUM + the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + 6 + 2 + read-write + + + + + SPI_DOUT_MODE + SPI output delay mode configuration + 0x2C + 0x20 + + + SPI_DOUT0_MODE + The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 0 + 1 + read-write + + + SPI_DOUT1_MODE + The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 1 + 1 + read-write + + + SPI_DOUT2_MODE + The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 2 + 1 + read-write + + + SPI_DOUT3_MODE + The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. + 3 + 1 + read-write + + + + + SPI_DMA_CONF + SPI DMA control register + 0x30 + 0x20 + 0x00000003 + + + SPI_DMA_OUTFIFO_EMPTY + Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. + 0 + 1 + read-only + + + SPI_DMA_INFIFO_FULL + Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. + 1 + 1 + read-only + + + SPI_DMA_SLV_SEG_TRANS_EN + Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + 18 + 1 + read-write + + + SPI_SLV_RX_SEG_TRANS_CLR_EN + 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. + 19 + 1 + read-write + + + SPI_SLV_TX_SEG_TRANS_CLR_EN + 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + 20 + 1 + read-write + + + SPI_RX_EOF_EN + 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + 21 + 1 + read-write + + + SPI_DMA_RX_ENA + Set this bit to enable SPI DMA controlled receive data mode. + 27 + 1 + read-write + + + SPI_DMA_TX_ENA + Set this bit to enable SPI DMA controlled send data mode. + 28 + 1 + read-write + + + SPI_RX_AFIFO_RST + Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. + 29 + 1 + write-only + + + SPI_BUF_AFIFO_RST + Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. + 30 + 1 + write-only + + + SPI_DMA_AFIFO_RST + Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. + 31 + 1 + write-only + + + + + SPI_DMA_INT_ENA + SPI interrupt enable register + 0x34 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ENA + The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA + The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_ENA + The enable bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_ENA + The enable bit for SPI slave En_QPI interrupt. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_ENA + The enable bit for SPI slave CMD7 interrupt. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_ENA + The enable bit for SPI slave CMD8 interrupt. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_ENA + The enable bit for SPI slave CMD9 interrupt. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_ENA + The enable bit for SPI slave CMDA interrupt. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_ENA + The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_ENA + The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_ENA + The enable bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_ENA + The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_ENA + The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_ENA + The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA + The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA + The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-write + + + SPI_APP2_INT_ENA + The enable bit for SPI_APP2_INT interrupt. + 19 + 1 + read-write + + + SPI_APP1_INT_ENA + The enable bit for SPI_APP1_INT interrupt. + 20 + 1 + read-write + + + + + SPI_DMA_INT_CLR + SPI interrupt clear register + 0x38 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_CLR + The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR + The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_CLR + The clear bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_CLR + The clear bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_CLR + The clear bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_CLR + The clear bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_CLR + The clear bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_CLR + The clear bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_CLR + The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_CLR + The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_CLR + The clear bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_CLR + The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_CLR + The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_CLR + The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR + The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR + The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_CLR + The clear bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_CLR + The clear bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_DMA_INT_RAW + SPI interrupt raw register + 0x3C + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_RAW + 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. + 0 + 1 + read-write + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW + 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. + 1 + 1 + read-write + + + SPI_SLV_EX_QPI_INT_RAW + The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. + 2 + 1 + read-write + + + SPI_SLV_EN_QPI_INT_RAW + The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. + 3 + 1 + read-write + + + SPI_SLV_CMD7_INT_RAW + The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. + 4 + 1 + read-write + + + SPI_SLV_CMD8_INT_RAW + The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. + 5 + 1 + read-write + + + SPI_SLV_CMD9_INT_RAW + The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. + 6 + 1 + read-write + + + SPI_SLV_CMDA_INT_RAW + The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. + 7 + 1 + read-write + + + SPI_SLV_RD_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. + 8 + 1 + read-write + + + SPI_SLV_WR_DMA_DONE_INT_RAW + The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. + 9 + 1 + read-write + + + SPI_SLV_RD_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. + 10 + 1 + read-write + + + SPI_SLV_WR_BUF_DONE_INT_RAW + The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. + 11 + 1 + read-write + + + SPI_TRANS_DONE_INT_RAW + The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. + 12 + 1 + read-write + + + SPI_DMA_SEG_TRANS_DONE_INT_RAW + The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. + 13 + 1 + read-write + + + SPI_SLV_BUF_ADDR_ERR_INT_RAW + The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. + 15 + 1 + read-write + + + SPI_SLV_CMD_ERR_INT_RAW + The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. + 16 + 1 + read-write + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW + The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + 17 + 1 + read-write + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW + The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + 18 + 1 + read-write + + + SPI_APP2_INT_RAW + The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + 19 + 1 + read-write + + + SPI_APP1_INT_RAW + The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + 20 + 1 + read-write + + + + + SPI_DMA_INT_ST + SPI interrupt status register + 0x40 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_ST + The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + read-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST + The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + read-only + + + SPI_SLV_EX_QPI_INT_ST + The status bit for SPI slave Ex_QPI interrupt. + 2 + 1 + read-only + + + SPI_SLV_EN_QPI_INT_ST + The status bit for SPI slave En_QPI interrupt. + 3 + 1 + read-only + + + SPI_SLV_CMD7_INT_ST + The status bit for SPI slave CMD7 interrupt. + 4 + 1 + read-only + + + SPI_SLV_CMD8_INT_ST + The status bit for SPI slave CMD8 interrupt. + 5 + 1 + read-only + + + SPI_SLV_CMD9_INT_ST + The status bit for SPI slave CMD9 interrupt. + 6 + 1 + read-only + + + SPI_SLV_CMDA_INT_ST + The status bit for SPI slave CMDA interrupt. + 7 + 1 + read-only + + + SPI_SLV_RD_DMA_DONE_INT_ST + The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + read-only + + + SPI_SLV_WR_DMA_DONE_INT_ST + The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + read-only + + + SPI_SLV_RD_BUF_DONE_INT_ST + The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + read-only + + + SPI_SLV_WR_BUF_DONE_INT_ST + The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + read-only + + + SPI_TRANS_DONE_INT_ST + The status bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + read-only + + + SPI_DMA_SEG_TRANS_DONE_INT_ST + The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + read-only + + + SPI_SLV_BUF_ADDR_ERR_INT_ST + The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + read-only + + + SPI_SLV_CMD_ERR_INT_ST + The status bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + read-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST + The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + read-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST + The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + read-only + + + SPI_APP2_INT_ST + The status bit for SPI_APP2_INT interrupt. + 19 + 1 + read-only + + + SPI_APP1_INT_ST + The status bit for SPI_APP1_INT interrupt. + 20 + 1 + read-only + + + + + SPI_DMA_INT_SET + SPI interrupt software set register + 0x44 + 0x20 + + + SPI_DMA_INFIFO_FULL_ERR_INT_SET + The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + 0 + 1 + write-only + + + SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET + The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + 1 + 1 + write-only + + + SPI_SLV_EX_QPI_INT_SET + The software set bit for SPI slave Ex_QPI interrupt. + 2 + 1 + write-only + + + SPI_SLV_EN_QPI_INT_SET + The software set bit for SPI slave En_QPI interrupt. + 3 + 1 + write-only + + + SPI_SLV_CMD7_INT_SET + The software set bit for SPI slave CMD7 interrupt. + 4 + 1 + write-only + + + SPI_SLV_CMD8_INT_SET + The software set bit for SPI slave CMD8 interrupt. + 5 + 1 + write-only + + + SPI_SLV_CMD9_INT_SET + The software set bit for SPI slave CMD9 interrupt. + 6 + 1 + write-only + + + SPI_SLV_CMDA_INT_SET + The software set bit for SPI slave CMDA interrupt. + 7 + 1 + write-only + + + SPI_SLV_RD_DMA_DONE_INT_SET + The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + 8 + 1 + write-only + + + SPI_SLV_WR_DMA_DONE_INT_SET + The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + 9 + 1 + write-only + + + SPI_SLV_RD_BUF_DONE_INT_SET + The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + 10 + 1 + write-only + + + SPI_SLV_WR_BUF_DONE_INT_SET + The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + 11 + 1 + write-only + + + SPI_TRANS_DONE_INT_SET + The software set bit for SPI_TRANS_DONE_INT interrupt. + 12 + 1 + write-only + + + SPI_DMA_SEG_TRANS_DONE_INT_SET + The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + 13 + 1 + write-only + + + SPI_SLV_BUF_ADDR_ERR_INT_SET + The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + 15 + 1 + write-only + + + SPI_SLV_CMD_ERR_INT_SET + The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + 16 + 1 + write-only + + + SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET + The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + 17 + 1 + write-only + + + SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET + The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + 18 + 1 + write-only + + + SPI_APP2_INT_SET + The software set bit for SPI_APP2_INT interrupt. + 19 + 1 + write-only + + + SPI_APP1_INT_SET + The software set bit for SPI_APP1_INT interrupt. + 20 + 1 + write-only + + + + + SPI_W0 + SPI CPU-controlled buffer0 + 0x98 + 0x20 + + + SPI_BUF0 + data buffer + 0 + 32 + read-write + + + + + SPI_W1 + SPI CPU-controlled buffer1 + 0x9C + 0x20 + + + SPI_BUF1 + data buffer + 0 + 32 + read-write + + + + + SPI_W2 + SPI CPU-controlled buffer2 + 0xA0 + 0x20 + + + SPI_BUF2 + data buffer + 0 + 32 + read-write + + + + + SPI_W3 + SPI CPU-controlled buffer3 + 0xA4 + 0x20 + + + SPI_BUF3 + data buffer + 0 + 32 + read-write + + + + + SPI_W4 + SPI CPU-controlled buffer4 + 0xA8 + 0x20 + + + SPI_BUF4 + data buffer + 0 + 32 + read-write + + + + + SPI_W5 + SPI CPU-controlled buffer5 + 0xAC + 0x20 + + + SPI_BUF5 + data buffer + 0 + 32 + read-write + + + + + SPI_W6 + SPI CPU-controlled buffer6 + 0xB0 + 0x20 + + + SPI_BUF6 + data buffer + 0 + 32 + read-write + + + + + SPI_W7 + SPI CPU-controlled buffer7 + 0xB4 + 0x20 + + + SPI_BUF7 + data buffer + 0 + 32 + read-write + + + + + SPI_W8 + SPI CPU-controlled buffer8 + 0xB8 + 0x20 + + + SPI_BUF8 + data buffer + 0 + 32 + read-write + + + + + SPI_W9 + SPI CPU-controlled buffer9 + 0xBC + 0x20 + + + SPI_BUF9 + data buffer + 0 + 32 + read-write + + + + + SPI_W10 + SPI CPU-controlled buffer10 + 0xC0 + 0x20 + + + SPI_BUF10 + data buffer + 0 + 32 + read-write + + + + + SPI_W11 + SPI CPU-controlled buffer11 + 0xC4 + 0x20 + + + SPI_BUF11 + data buffer + 0 + 32 + read-write + + + + + SPI_W12 + SPI CPU-controlled buffer12 + 0xC8 + 0x20 + + + SPI_BUF12 + data buffer + 0 + 32 + read-write + + + + + SPI_W13 + SPI CPU-controlled buffer13 + 0xCC + 0x20 + + + SPI_BUF13 + data buffer + 0 + 32 + read-write + + + + + SPI_W14 + SPI CPU-controlled buffer14 + 0xD0 + 0x20 + + + SPI_BUF14 + data buffer + 0 + 32 + read-write + + + + + SPI_W15 + SPI CPU-controlled buffer15 + 0xD4 + 0x20 + + + SPI_BUF15 + data buffer + 0 + 32 + read-write + + + + + SPI_SLAVE + SPI slave control register + 0xE0 + 0x20 + + + SPI_CLK_MODE + SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. + 0 + 2 + read-write + + + SPI_CLK_MODE_13 + {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + 2 + 1 + read-write + + + SPI_RSCK_DATA_OUT + It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge + 3 + 1 + read-write + + + SPI_SLV_RDDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others + 8 + 1 + read-write + + + SPI_SLV_WRDMA_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others + 9 + 1 + read-write + + + SPI_SLV_RDBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others + 10 + 1 + read-write + + + SPI_SLV_WRBUF_BITLEN_EN + 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others + 11 + 1 + read-write + + + SPI_SLV_LAST_BYTE_STRB + Represents the effective bit of the last received data byte in SPI slave FD and HD mode. + 12 + 8 + read-only + + + MODE + Set SPI work mode. 1: slave mode 0: master mode. + 26 + 1 + read-write + + + SPI_SOFT_RESET + Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. + 27 + 1 + write-only + + + SPI_MST_FD_WAIT_DMA_TX_DATA + In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. + 29 + 1 + read-write + + + + + SPI_SLAVE1 + SPI slave control register 1 + 0xE4 + 0x20 + + + SPI_SLV_DATA_BITLEN + The transferred data bit length in SPI slave FD and HD mode. + 0 + 18 + read-write + + + SPI_SLV_LAST_COMMAND + In the slave mode it is the value of command. + 18 + 8 + read-write + + + SPI_SLV_LAST_ADDR + In the slave mode it is the value of address. + 26 + 6 + read-write + + + + + SPI_CLK_GATE + SPI module clock and register clock control + 0xE8 + 0x20 + + + SPI_CLK_EN + Set this bit to enable clk gate + 0 + 1 + read-write + + + SPI_MST_CLK_ACTIVE + Set this bit to power on the SPI module clock. + 1 + 1 + read-write + + + SPI_MST_CLK_SEL + This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. + 2 + 1 + read-write + + + + + SPI_DATE + Version control + 0xF0 + 0x20 + 0x02207202 + + + SPI_DATE + SPI register version. + 0 + 28 + read-write + + + + + + + SYSTIMER + System Timer + SYSTIMER + 0x500E2000 + + 0x0 + 0x90 + registers + + + SYSTIMER_TARGET0 + 53 + + + SYSTIMER_TARGET1 + 54 + + + SYSTIMER_TARGET2 + 55 + + + + CONF + Configure system timer clock + 0x0 + 0x20 + 0x46000000 + + + SYSTIMER_CLK_FO + systimer clock force on + 0 + 1 + read-write + + + ETM_EN + enable systimer's etm task and event + 1 + 1 + read-write + + + TARGET2_WORK_EN + target2 work enable + 22 + 1 + read-write + + + TARGET1_WORK_EN + target1 work enable + 23 + 1 + read-write + + + TARGET0_WORK_EN + target0 work enable + 24 + 1 + read-write + + + TIMER_UNIT1_CORE1_STALL_EN + If timer unit1 is stalled when core1 stalled + 25 + 1 + read-write + + + TIMER_UNIT1_CORE0_STALL_EN + If timer unit1 is stalled when core0 stalled + 26 + 1 + read-write + + + TIMER_UNIT0_CORE1_STALL_EN + If timer unit0 is stalled when core1 stalled + 27 + 1 + read-write + + + TIMER_UNIT0_CORE0_STALL_EN + If timer unit0 is stalled when core0 stalled + 28 + 1 + read-write + + + TIMER_UNIT1_WORK_EN + timer unit1 work enable + 29 + 1 + read-write + + + TIMER_UNIT0_WORK_EN + timer unit0 work enable + 30 + 1 + read-write + + + CLK_EN + register file clk gating + 31 + 1 + read-write + + + + + UNIT0_OP + system timer unit0 value update register + 0x4 + 0x20 + + + TIMER_UNIT0_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT0_UPDATE + update timer_unit0 + 30 + 1 + write-only + + + + + UNIT1_OP + system timer unit1 value update register + 0x8 + 0x20 + + + TIMER_UNIT1_VALUE_VALID + timer value is sync and valid + 29 + 1 + read-only + + + TIMER_UNIT1_UPDATE + update timer unit1 + 30 + 1 + write-only + + + + + UNIT0_LOAD_HI + system timer unit0 value high load register + 0xC + 0x20 + + + TIMER_UNIT0_LOAD_HI + timer unit0 load high 20 bits + 0 + 20 + read-write + + + + + UNIT0_LOAD_LO + system timer unit0 value low load register + 0x10 + 0x20 + + + TIMER_UNIT0_LOAD_LO + timer unit0 load low 32 bits + 0 + 32 + read-write + + + + + UNIT1_LOAD_HI + system timer unit1 value high load register + 0x14 + 0x20 + + + TIMER_UNIT1_LOAD_HI + timer unit1 load high 20 bits + 0 + 20 + read-write + + + + + UNIT1_LOAD_LO + system timer unit1 value low load register + 0x18 + 0x20 + + + TIMER_UNIT1_LOAD_LO + timer unit1 load low 32 bits + 0 + 32 + read-write + + + + + TARGET0_HI + system timer comp0 value high register + 0x1C + 0x20 + + + TIMER_TARGET0_HI + timer taget0 high 20 bits + 0 + 20 + read-write + + + + + TARGET0_LO + system timer comp0 value low register + 0x20 + 0x20 + + + TIMER_TARGET0_LO + timer taget0 low 32 bits + 0 + 32 + read-write + + + + + TARGET1_HI + system timer comp1 value high register + 0x24 + 0x20 + + + TIMER_TARGET1_HI + timer taget1 high 20 bits + 0 + 20 + read-write + + + + + TARGET1_LO + system timer comp1 value low register + 0x28 + 0x20 + + + TIMER_TARGET1_LO + timer taget1 low 32 bits + 0 + 32 + read-write + + + + + TARGET2_HI + system timer comp2 value high register + 0x2C + 0x20 + + + TIMER_TARGET2_HI + timer taget2 high 20 bits + 0 + 20 + read-write + + + + + TARGET2_LO + system timer comp2 value low register + 0x30 + 0x20 + + + TIMER_TARGET2_LO + timer taget2 low 32 bits + 0 + 32 + read-write + + + + + TARGET0_CONF + system timer comp0 target mode register + 0x34 + 0x20 + + + TARGET0_PERIOD + target0 period + 0 + 26 + read-write + + + TARGET0_PERIOD_MODE + Set target0 to period mode + 30 + 1 + read-write + + + TARGET0_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET1_CONF + system timer comp1 target mode register + 0x38 + 0x20 + + + TARGET1_PERIOD + target1 period + 0 + 26 + read-write + + + TARGET1_PERIOD_MODE + Set target1 to period mode + 30 + 1 + read-write + + + TARGET1_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + TARGET2_CONF + system timer comp2 target mode register + 0x3C + 0x20 + + + TARGET2_PERIOD + target2 period + 0 + 26 + read-write + + + TARGET2_PERIOD_MODE + Set target2 to period mode + 30 + 1 + read-write + + + TARGET2_TIMER_UNIT_SEL + select which unit to compare + 31 + 1 + read-write + + + + + UNIT0_VALUE_HI + system timer unit0 value high register + 0x40 + 0x20 + + + TIMER_UNIT0_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT0_VALUE_LO + system timer unit0 value low register + 0x44 + 0x20 + + + TIMER_UNIT0_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + UNIT1_VALUE_HI + system timer unit1 value high register + 0x48 + 0x20 + + + TIMER_UNIT1_VALUE_HI + timer read value high 20bits + 0 + 20 + read-only + + + + + UNIT1_VALUE_LO + system timer unit1 value low register + 0x4C + 0x20 + + + TIMER_UNIT1_VALUE_LO + timer read value low 32bits + 0 + 32 + read-only + + + + + COMP0_LOAD + system timer comp0 conf sync register + 0x50 + 0x20 + + + TIMER_COMP0_LOAD + timer comp0 sync enable signal + 0 + 1 + write-only + + + + + COMP1_LOAD + system timer comp1 conf sync register + 0x54 + 0x20 + + + TIMER_COMP1_LOAD + timer comp1 sync enable signal + 0 + 1 + write-only + + + + + COMP2_LOAD + system timer comp2 conf sync register + 0x58 + 0x20 + + + TIMER_COMP2_LOAD + timer comp2 sync enable signal + 0 + 1 + write-only + + + + + UNIT0_LOAD + system timer unit0 conf sync register + 0x5C + 0x20 + + + TIMER_UNIT0_LOAD + timer unit0 sync enable signal + 0 + 1 + write-only + + + + + UNIT1_LOAD + system timer unit1 conf sync register + 0x60 + 0x20 + + + TIMER_UNIT1_LOAD + timer unit1 sync enable signal + 0 + 1 + write-only + + + + + INT_ENA + systimer interrupt enable register + 0x64 + 0x20 + + + TARGET0_INT_ENA + interupt0 enable + 0 + 1 + read-write + + + TARGET1_INT_ENA + interupt1 enable + 1 + 1 + read-write + + + TARGET2_INT_ENA + interupt2 enable + 2 + 1 + read-write + + + + + INT_RAW + systimer interrupt raw register + 0x68 + 0x20 + + + TARGET0_INT_RAW + interupt0 raw + 0 + 1 + read-write + + + TARGET1_INT_RAW + interupt1 raw + 1 + 1 + read-write + + + TARGET2_INT_RAW + interupt2 raw + 2 + 1 + read-write + + + + + INT_CLR + systimer interrupt clear register + 0x6C + 0x20 + + + TARGET0_INT_CLR + interupt0 clear + 0 + 1 + write-only + + + TARGET1_INT_CLR + interupt1 clear + 1 + 1 + write-only + + + TARGET2_INT_CLR + interupt2 clear + 2 + 1 + write-only + + + + + INT_ST + systimer interrupt status register + 0x70 + 0x20 + + + TARGET0_INT_ST + interupt0 status + 0 + 1 + read-only + + + TARGET1_INT_ST + interupt1 status + 1 + 1 + read-only + + + TARGET2_INT_ST + interupt2 status + 2 + 1 + read-only + + + + + REAL_TARGET0_LO + system timer comp0 actual target value low register + 0x74 + 0x20 + + + TARGET0_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET0_HI + system timer comp0 actual target value high register + 0x78 + 0x20 + + + TARGET0_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET1_LO + system timer comp1 actual target value low register + 0x7C + 0x20 + + + TARGET1_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET1_HI + system timer comp1 actual target value high register + 0x80 + 0x20 + + + TARGET1_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + REAL_TARGET2_LO + system timer comp2 actual target value low register + 0x84 + 0x20 + + + TARGET2_LO_RO + actual target value value low 32bits + 0 + 32 + read-only + + + + + REAL_TARGET2_HI + system timer comp2 actual target value high register + 0x88 + 0x20 + + + TARGET2_HI_RO + actual target value value high 20bits + 0 + 20 + read-only + + + + + DATE + system timer version control register + 0xFC + 0x20 + 0x02201073 + + + DATE + systimer register version + 0 + 32 + read-write + + + + + + + TIMG0 + Timer Group 0 + TIMG + 0x500C2000 + + 0x0 + 0x68 + registers + + + TG0_T0 + 46 + + + TG0_T1 + 47 + + + TG0_WDT + 48 + + + + T0CONFIG + Timer %s configuration register + 0x0 + 0x20 + 0x60002000 + + + USE_XTAL + 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. + 9 + 1 + read-write + + + ALARM_EN + When set, the alarm is enabled. This bit is automatically cleared once an +alarm occurs. + 10 + 1 + read-write + + + DIVCNT_RST + When set, Timer %s 's clock divider counter will be reset. + 12 + 1 + write-only + + + DIVIDER + Timer %s clock (T%s_clk) prescaler value. + 13 + 16 + read-write + + + AUTORELOAD + When set, timer %s auto-reload at alarm is enabled. + 29 + 1 + read-write + + + INCREASE + When set, the timer %s time-base counter will increment every clock tick. When +cleared, the timer %s time-base counter will decrement. + 30 + 1 + read-write + + + EN + When set, the timer %s time-base counter is enabled. + 31 + 1 + read-write + + + + + T0LO + Timer %s current value, low 32 bits + 0x4 + 0x20 + + + LO + After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter +of timer %s can be read here. + 0 + 32 + read-only + + + + + T0HI + Timer %s current value, high 22 bits + 0x8 + 0x20 + + + HI + After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter +of timer %s can be read here. + 0 + 22 + read-only + + + + + T0UPDATE + Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + 0xC + 0x20 + + + UPDATE + After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. + 31 + 1 + read-write + + + + + T0ALARMLO + Timer %s alarm value, low 32 bits + 0x10 + 0x20 + + + ALARM_LO + Timer %s alarm trigger time-base counter value, low 32 bits. + 0 + 32 + read-write + + + + + T0ALARMHI + Timer %s alarm value, high bits + 0x14 + 0x20 + + + ALARM_HI + Timer %s alarm trigger time-base counter value, high 22 bits. + 0 + 22 + read-write + + + + + T0LOADLO + Timer %s reload value, low 32 bits + 0x18 + 0x20 + + + LOAD_LO + Low 32 bits of the value that a reload will load onto timer %s time-base +Counter. + 0 + 32 + read-write + + + + + T0LOADHI + Timer %s reload value, high 22 bits + 0x1C + 0x20 + + + LOAD_HI + High 22 bits of the value that a reload will load onto timer %s time-base +counter. + 0 + 22 + read-write + + + + + T0LOAD + Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + 0x20 + 0x20 + + + LOAD + Write any value to trigger a timer %s time-base counter reload. + 0 + 32 + write-only + + + + + WDTCONFIG0 + Watchdog timer configuration register + 0x48 + 0x20 + 0x0004C000 + + + WDT_APPCPU_RESET_EN + WDT reset CPU enable. + 12 + 1 + read-write + + + WDT_PROCPU_RESET_EN + WDT reset CPU enable. + 13 + 1 + read-write + + + WDT_FLASHBOOT_MOD_EN + When set, Flash boot protection is enabled. + 14 + 1 + read-write + + + WDT_SYS_RESET_LENGTH + System reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 15 + 3 + read-write + + + WDT_CPU_RESET_LENGTH + CPU reset signal length selection. 0: 100 ns, 1: 200 ns, +2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + 18 + 3 + read-write + + + WDT_USE_XTAL + choose WDT clock:0-apb_clk, 1-xtal_clk. + 21 + 1 + read-write + + + WDT_CONF_UPDATE_EN + update the WDT configuration registers + 22 + 1 + write-only + + + WDT_STG3 + Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 23 + 2 + read-write + + + WDT_STG2 + Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 25 + 2 + read-write + + + WDT_STG1 + Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 27 + 2 + read-write + + + WDT_STG0 + Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. + 29 + 2 + read-write + + + WDT_EN + When set, MWDT is enabled. + 31 + 1 + read-write + + + + + WDTCONFIG1 + Watchdog timer prescaler register + 0x4C + 0x20 + 0x00010000 + + + WDT_DIVCNT_RST + When set, WDT 's clock divider counter will be reset. + 0 + 1 + write-only + + + WDT_CLK_PRESCALE + MWDT clock prescaler value. MWDT clock period = 12.5 ns * +TIMG_WDT_CLK_PRESCALE. + 16 + 16 + read-write + + + + + WDTCONFIG2 + Watchdog timer stage 0 timeout value + 0x50 + 0x20 + 0x018CBA80 + + + WDT_STG0_HOLD + Stage 0 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG3 + Watchdog timer stage 1 timeout value + 0x54 + 0x20 + 0x07FFFFFF + + + WDT_STG1_HOLD + Stage 1 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG4 + Watchdog timer stage 2 timeout value + 0x58 + 0x20 + 0x000FFFFF + + + WDT_STG2_HOLD + Stage 2 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTCONFIG5 + Watchdog timer stage 3 timeout value + 0x5C + 0x20 + 0x000FFFFF + + + WDT_STG3_HOLD + Stage 3 timeout value, in MWDT clock cycles. + 0 + 32 + read-write + + + + + WDTFEED + Write to feed the watchdog timer + 0x60 + 0x20 + + + WDT_FEED + Write any value to feed the MWDT. (WO) + 0 + 32 + write-only + + + + + WDTWPROTECT + Watchdog write protect register + 0x64 + 0x20 + 0x50D83AA1 + + + WDT_WKEY + If the register contains a different value than its reset value, write +protection is enabled. + 0 + 32 + read-write + + + + + RTCCALICFG + RTC calibration configure register + 0x68 + 0x20 + 0x00011000 + + + RTC_CALI_START_CYCLING + 0: one-shot frequency calculation,1: periodic frequency calculation, + 12 + 1 + read-write + + + RTC_CALI_CLK_SEL + 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. + 13 + 2 + read-write + + + RTC_CALI_RDY + indicate one-shot frequency calculation is done. + 15 + 1 + read-only + + + RTC_CALI_MAX + Configure the time to calculate RTC slow clock's frequency. + 16 + 15 + read-write + + + RTC_CALI_START + Set this bit to start one-shot frequency calculation. + 31 + 1 + read-write + + + + + RTCCALICFG1 + RTC calibration configure1 register + 0x6C + 0x20 + + + RTC_CALI_CYCLING_DATA_VLD + indicate periodic frequency calculation is done. + 0 + 1 + read-only + + + RTC_CALI_VALUE + When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency. + 7 + 25 + read-only + + + + + INT_ENA_TIMERS + Interrupt enable bits + 0x70 + 0x20 + + + T0_INT_ENA + The interrupt enable bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-write + + + T1_INT_ENA + The interrupt enable bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-write + + + WDT_INT_ENA + The interrupt enable bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-write + + + + + INT_RAW_TIMERS + Raw interrupt status + 0x74 + 0x20 + + + T0_INT_RAW + The raw interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_RAW + The raw interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_RAW + The raw interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + + + INT_ST_TIMERS + Masked interrupt status + 0x78 + 0x20 + + + T0_INT_ST + The masked interrupt status bit for the TIMG_T0_INT interrupt. + 0 + 1 + read-only + + + T1_INT_ST + The masked interrupt status bit for the TIMG_T1_INT interrupt. + 1 + 1 + read-only + + + WDT_INT_ST + The masked interrupt status bit for the TIMG_WDT_INT interrupt. + 2 + 1 + read-only + + + + + INT_CLR_TIMERS + Interrupt clear bits + 0x7C + 0x20 + + + T0_INT_CLR + Set this bit to clear the TIMG_T0_INT interrupt. + 0 + 1 + write-only + + + T1_INT_CLR + Set this bit to clear the TIMG_T1_INT interrupt. + 1 + 1 + write-only + + + WDT_INT_CLR + Set this bit to clear the TIMG_WDT_INT interrupt. + 2 + 1 + write-only + + + + + RTCCALICFG2 + Timer group calibration register + 0x80 + 0x20 + 0xFFFFFF98 + + + RTC_CALI_TIMEOUT + RTC calibration timeout indicator + 0 + 1 + read-only + + + RTC_CALI_TIMEOUT_RST_CNT + Cycles that release calibration timeout reset + 3 + 4 + read-write + + + RTC_CALI_TIMEOUT_THRES + Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. + 7 + 25 + read-write + + + + + NTIMERS_DATE + Timer version control register + 0xF8 + 0x20 + 0x02209142 + + + NTIMGS_DATE + Timer version control register + 0 + 28 + read-write + + + + + REGCLK + Timer group clock gate register + 0xFC + 0x20 + 0x70000000 + + + ETM_EN + enable timer's etm task and event + 28 + 1 + read-write + + + WDT_CLK_IS_ACTIVE + enable WDT's clock + 29 + 1 + read-write + + + TIMER_CLK_IS_ACTIVE + enable Timer 30's clock + 30 + 1 + read-write + + + CLK_EN + Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. + 31 + 1 + read-write + + + + + + + TIMG1 + Timer Group 1 + 0x500C3000 + + TG1_T0 + 49 + + + TG1_T1 + 50 + + + TG1_WDT + 51 + + + + TRACE0 + TRACE0 Peripheral + TRACE + 0x3FF04000 + + 0x0 + 0x4C + registers + + + + MEM_START_ADDR + mem start addr + 0x0 + 0x20 + + + MEM_START_ADDR + The start address of trace memory + 0 + 32 + read-write + + + + + MEM_END_ADDR + mem end addr + 0x4 + 0x20 + 0xFFFFFFFF + + + MEM_END_ADDR + The end address of trace memory + 0 + 32 + read-write + + + + + MEM_CURRENT_ADDR + mem current addr + 0x8 + 0x20 + + + MEM_CURRENT_ADDR + current_mem_addr,indicate that next writing addr + 0 + 32 + read-only + + + + + MEM_ADDR_UPDATE + mem addr update + 0xC + 0x20 + + + MEM_CURRENT_ADDR_UPDATE + when set, the will \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}. + 0 + 1 + write-only + + + + + FIFO_STATUS + fifo status register + 0x10 + 0x20 + 0x00000001 + + + FIFO_EMPTY + Represent whether the fifo is empty. \\1: empty \\0: not empty + 0 + 1 + read-only + + + WORK_STATUS + Represent trace work status: \\0: idle state \\1: working state\\ 2: wait state due to hart halted or havereset \\3: lost state + 1 + 2 + read-only + + + + + INTR_ENA + interrupt enable register + 0x14 + 0x20 + + + FIFO_OVERFLOW_INTR_ENA + Set 1 enable fifo_overflow interrupt + 0 + 1 + read-write + + + MEM_FULL_INTR_ENA + Set 1 enable mem_full interrupt + 1 + 1 + read-write + + + + + INTR_RAW + interrupt status register + 0x18 + 0x20 + + + FIFO_OVERFLOW_INTR_RAW + fifo_overflow interrupt status + 0 + 1 + read-only + + + MEM_FULL_INTR_RAW + mem_full interrupt status + 1 + 1 + read-only + + + + + INTR_CLR + interrupt clear register + 0x1C + 0x20 + + + FIFO_OVERFLOW_INTR_CLR + Set 1 clear fifo overflow interrupt + 0 + 1 + write-only + + + MEM_FULL_INTR_CLR + Set 1 clear mem full interrupt + 1 + 1 + write-only + + + + + TRIGGER + trigger register + 0x20 + 0x20 + 0x0000000C + + + ON + Configure whether or not start trace.\\1: start trace \\0: invalid\\ + 0 + 1 + write-only + + + OFF + Configure whether or not stop trace.\\1: stop trace \\0: invalid\\ + 1 + 1 + write-only + + + MEM_LOOP + Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ + 2 + 1 + read-write + + + RESTART_ENA + Configure whether or not enable auto-restart.\\1: enable\\0: disable\\ + 3 + 1 + read-write + + + + + CONFIG + trace configuration register + 0x24 + 0x20 + + + DM_TRIGGER_ENA + Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ + 0 + 1 + read-write + + + RESET_ENA + Configure whether or not enable trace cpu haverest, when enabeld, if cpu have reset, the encoder will output a packet to report the address of the last instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: disabled\\ + 1 + 1 + read-write + + + HALT_ENA + Configure whether or not enable trace cpu is halted, when enabeld, if the cpu halted, the encoder will output a packet to report the address of the last instruction, and upon halted deassertion, the encoder start again.When disabled, encoder will not report the last address before halted and first address after halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ + 2 + 1 + read-write + + + STALL_ENA + Configure whether or not enable stall cpu. When enabled, when the fifo almost full, the cpu will be stalled until the packets is able to write to fifo.\\1: enabled.\\0: disabled\\ + 3 + 1 + read-write + + + FULL_ADDRESS + Configure whether or not enable full-address mode.\\1: full address mode.\\0: delta address mode\\ + 4 + 1 + read-write + + + IMPLICIT_EXCEPT + Configure whether or not enabel implicit exception mode. When enabled,, do not sent exception address, only exception cause in exception packets.\\1: enabled\\0: disabled\\ + 5 + 1 + read-write + + + + + FILTER_CONTROL + filter control register + 0x28 + 0x20 + + + FILTER_EN + Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match + 0 + 1 + read-write + + + MATCH_COMP + when set, the comparator must be high in order for the filter to match + 1 + 1 + read-write + + + MATCH_PRIVILEGE + when set, match privilege levels specified by \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + 2 + 1 + read-write + + + MATCH_ECAUSE + when set, start matching from exception cause codes specified by \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop matching upon return from the 1st matching exception. + 3 + 1 + read-write + + + MATCH_INTERRUPT + when set, start matching from a trap with the interrupt level codes specified by \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and stop matching upon return from the 1st matching trap. + 4 + 1 + read-write + + + + + FILTER_MATCH_CONTROL + filter match control register + 0x2C + 0x20 + + + MATCH_CHOICE_PRIVILEGE + Select match which privilege level when \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1: machine mode. \\0: user mode + 0 + 1 + read-write + + + MATCH_VALUE_INTERRUPT + Select which match which itype when \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\1: match itype of 2. \\0: match itype or 1. + 1 + 1 + read-write + + + MATCH_CHOICE_ECAUSE + specified which ecause matched. + 2 + 6 + read-write + + + + + FILTER_COMPARATOR_CONTROL + filter comparator match control register + 0x30 + 0x20 + + + P_INPUT + Determines which input to compare against the primary comparator, \\0: iaddr, \\1: tval. + 0 + 1 + read-write + + + P_FUNCTION + Select the primary comparator function. \\0: equal, \\1: not equal, \\2: less than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: always match + 2 + 3 + read-write + + + P_NOTIFY + Generate a trace packet explicitly reporting the address that cause the primary match + 5 + 1 + read-write + + + S_INPUT + Determines which input to compare against the secondary comparator, \\0: iaddr, \\1: tval. + 8 + 1 + read-write + + + S_FUNCTION + Select the secondary comparator function. \\0: equal, \\1: not equal, \\2: less than, \\3: less than or equal, \\4: greater than, \\5: greater than or equal, \\other: always match + 10 + 3 + read-write + + + S_NOTIFY + Generate a trace packet explicitly reporting the address that cause the secondary match + 13 + 1 + read-write + + + MATCH_MODE + 0: only primary matches, \\1: primary and secondary comparator both matches(P\&\&S),\\ 2:either primary or secondary comparator matches !(P\&\&S), \\3: set when primary matches and continue to match until after secondary comparator matches + 16 + 2 + read-write + + + + + FILTER_P_COMPARATOR_MATCH + primary comparator match value + 0x34 + 0x20 + + + P_MATCH + primary comparator match value + 0 + 32 + read-write + + + + + FILTER_S_COMPARATOR_MATCH + secondary comparator match value + 0x38 + 0x20 + + + S_MATCH + secondary comparator match value + 0 + 32 + read-write + + + + + RESYNC_PROLONGED + resync configuration register + 0x3C + 0x20 + 0x00000080 + + + RESYNC_PROLONGED + count number, when count to this value, send a sync package + 0 + 24 + read-write + + + RESYNC_MODE + resyc mode sel: \\0: off, \\2: cycle count \\3: package num count + 24 + 2 + read-write + + + + + AHB_CONFIG + AHB config register + 0x40 + 0x20 + + + HBURST + set hburst + 0 + 3 + read-write + + + MAX_INCR + set max continuous access for incr mode + 3 + 3 + read-write + + + + + CLOCK_GATE + Clock gate control register + 0x44 + 0x20 + 0x00000001 + + + CLK_EN + The bit is used to enable clock gate when access all registers in this module. + 0 + 1 + read-write + + + + + DATE + Version control register + 0x3FC + 0x20 + 0x02211300 + + + DATE + version control register. Note that this default value stored is the latest date when the hardware logic was updated. + 0 + 28 + read-write + + + + + + + TRACE1 + TRACE1 Peripheral + 0x3FF05000 + + + LP_TSENS + Low-power Temperature Sensor + TSENS + 0x5012F000 + + 0x0 + 0x38 + registers + + + LP_TSENS + 15 + + + + CTRL + Tsens configuration. + 0x0 + 0x20 + 0x00019400 + + + OUT + Temperature sensor data out. + 0 + 8 + read-only + + + READY + Indicate temperature sensor out ready. + 8 + 1 + read-only + + + SAMPLE_EN + Enable sample signal for wakeup module. + 9 + 1 + read-write + + + WAKEUP_MASK + Wake up signal mask. + 10 + 1 + read-write + + + INT_EN + Enable temperature sensor to send out interrupt. + 12 + 1 + read-write + + + IN_INV + Invert temperature sensor data. + 13 + 1 + read-write + + + CLK_DIV + Temperature sensor clock divider. + 14 + 8 + read-write + + + POWER_UP + Temperature sensor power up. + 22 + 1 + read-write + + + POWER_UP_FORCE + 1: dump out & power up controlled by SW, 0: by FSM. + 23 + 1 + read-write + + + + + CTRL2 + Tsens configuration. + 0x4 + 0x20 + 0x00004002 + + + XPD_WAIT + N/A + 0 + 12 + read-write + + + XPD_FORCE + N/A + 12 + 2 + read-write + + + CLK_INV + N/A + 14 + 1 + read-write + + + + + INT_RAW + Tsens interrupt raw registers. + 0x8 + 0x20 + + + COCPU_TSENS_WAKE_INT_RAW + Tsens wakeup interrupt raw. + 0 + 1 + read-write + + + + + INT_ST + Tsens interrupt status registers. + 0xC + 0x20 + + + COCPU_TSENS_WAKE_INT_ST + Tsens wakeup interrupt status. + 0 + 1 + read-only + + + + + INT_ENA + Tsens interrupt enable registers. + 0x10 + 0x20 + + + COCPU_TSENS_WAKE_INT_ENA + Tsens wakeup interrupt enable. + 0 + 1 + read-write + + + + + INT_CLR + Tsens interrupt clear registers. + 0x14 + 0x20 + + + COCPU_TSENS_WAKE_INT_CLR + Tsens wakeup interrupt clear. + 0 + 1 + write-only + + + + + CLK_CONF + Tsens regbank configuration registers. + 0x18 + 0x20 + + + CLK_EN + Tsens regbank clock gating enable. + 0 + 1 + read-write + + + + + INT_ENA_W1TS + Tsens wakeup interrupt enable assert. + 0x1C + 0x20 + + + COCPU_TSENS_WAKE_INT_ENA_W1TS + Write 1 to this field to assert interrupt enable. + 0 + 1 + write-only + + + + + INT_ENA_W1TC + Tsens wakeup interrupt enable deassert. + 0x20 + 0x20 + + + COCPU_TSENS_WAKE_INT_ENA_W1TC + Write 1 to this field to deassert interrupt enable. + 0 + 1 + write-only + + + + + WAKEUP_CTRL + Tsens wakeup control registers. + 0x24 + 0x20 + 0x003FC000 + + + WAKEUP_TH_LOW + Lower threshold. + 0 + 8 + read-write + + + WAKEUP_TH_HIGH + Upper threshold. + 14 + 8 + read-write + + + WAKEUP_OVER_UPPER_TH + Indicates that this wakeup event arose from exceeding upper threshold. + 29 + 1 + read-only + + + WAKEUP_EN + Tsens wakeup enable. + 30 + 1 + read-write + + + WAKEUP_MODE + 0:absolute value comparison mode. 1: relative value comparison mode. + 31 + 1 + read-write + + + + + SAMPLE_RATE + Hardware automatic sampling control registers. + 0x28 + 0x20 + 0x00000014 + + + SAMPLE_RATE + Hardware automatic sampling rate. + 0 + 16 + read-write + + + + + RND_ECO_LOW + N/A + 0x2C + 0x20 + + + RND_ECO_LOW + N/A + 0 + 32 + read-write + + + + + RND_ECO_HIGH + N/A + 0x30 + 0x20 + 0xFFFFFFFF + + + RND_ECO_HIGH + N/A + 0 + 32 + read-write + + + + + RND_ECO_CS + N/A + 0x34 + 0x20 + + + RND_ECO_EN + N/A + 0 + 1 + read-write + + + RND_ECO_RESULT + N/A + 1 + 1 + read-only + + + + + + + TWAI0 + Two-Wire Automotive Interface + TWAI + 0x500D7000 + + 0x0 + 0x8C + registers + + + TWAI0 + 40 + + + + MODE + TWAI mode register. + 0x0 + 0x20 + 0x00000001 + + + RESET_MODE + 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode. + 0 + 1 + read-write + + + LISTEN_ONLY_MODE + 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal. + 1 + 1 + read-write + + + SELF_TEST_MODE + 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission. + 2 + 1 + read-write + + + ACCEPTANCE_FILTER_MODE + 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active). + 3 + 1 + read-write + + + + + CMD + TWAI command register. + 0x4 + 0x20 + + + TX_REQUEST + 1: present, a message shall be transmitted. 0: absent + 0 + 1 + write-only + + + ABORT_TX + 1: present, if not already in progress, a pending transmission request is cancelled. 0: absent + 1 + 1 + write-only + + + RELEASE_BUFFER + 1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action + 2 + 1 + write-only + + + CLEAR_DATA_OVERRUN + 1: clear, the data overrun status bit is cleared. 0: no action. + 3 + 1 + write-only + + + SELF_RX_REQUEST + 1: present, a message shall be transmitted and received simultaneously. 0: absent. + 4 + 1 + write-only + + + + + STATUS + TWAI status register. + 0x8 + 0x20 + + + RECEIVE_BUFFER + 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available + 0 + 1 + read-only + + + OVERRUN + 1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given + 1 + 1 + read-only + + + TRANSMIT_BUFFER + 1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted + 2 + 1 + read-only + + + TRANSMISSION_COMPLETE + 1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed + 3 + 1 + read-only + + + RECEIVE + 1: receive, the TWAI controller is receiving a message. 0: idle + 4 + 1 + read-only + + + TRANSMIT + 1: transmit, the TWAI controller is transmitting a message. 0: idle + 5 + 1 + read-only + + + ERR + 1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit + 6 + 1 + read-only + + + NODE_BUS_OFF + 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities + 7 + 1 + read-only + + + MISS + 1: current message is destroyed because of FIFO overflow. + 8 + 1 + read-only + + + + + INTERRUPT + Interrupt signals' register. + 0xC + 0x20 + + + RECEIVE_INT_ST + 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset + 0 + 1 + read-only + + + TRANSMIT_INT_ST + 1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset + 1 + 1 + read-only + + + ERR_WARNING_INT_ST + 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset + 2 + 1 + read-only + + + DATA_OVERRUN_INT_ST + 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset + 3 + 1 + read-only + + + TS_COUNTER_OVFL_INT_ST + 1: this bit is set then the timestamp counter reaches the maximum value and overflow. + 4 + 1 + read-only + + + ERR_PASSIVE_INT_ST + 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset + 5 + 1 + read-only + + + ARBITRATION_LOST_INT_ST + 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset + 6 + 1 + read-only + + + BUS_ERR_INT_ST + 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset + 7 + 1 + read-only + + + IDLE_INT_ST + 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset + 8 + 1 + read-only + + + + + INTERRUPT_ENABLE + Interrupt enable register. + 0x10 + 0x20 + + + EXT_RECEIVE_INT_ENA + 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable + 0 + 1 + read-write + + + EXT_TRANSMIT_INT_ENA + 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable + 1 + 1 + read-write + + + EXT_ERR_WARNING_INT_ENA + 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 2 + 1 + read-write + + + EXT_DATA_OVERRUN_INT_ENA + 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable + 3 + 1 + read-write + + + TS_COUNTER_OVFL_INT_ENA + enable the timestamp counter overflow interrupt request. + 4 + 1 + read-write + + + ERR_PASSIVE_INT_ENA + 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable + 5 + 1 + read-write + + + ARBITRATION_LOST_INT_ENA + 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable + 6 + 1 + read-write + + + BUS_ERR_INT_ENA + 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable + 7 + 1 + read-write + + + IDLE_INT_ENA + 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable + 8 + 1 + read-only + + + + + BUS_TIMING_0 + Bit timing configuration register 0. + 0x18 + 0x20 + + + BAUD_PRESC + The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode. + 0 + 14 + read-write + + + SYNC_JUMP_WIDTH + The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode. + 14 + 2 + read-write + + + + + BUS_TIMING_1 + Bit timing configuration register 1. + 0x1C + 0x20 + + + TIME_SEGMENT1 + The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 0 + 4 + read-write + + + TIME_SEGMENT2 + The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + 4 + 3 + read-write + + + TIME_SAMPLING + 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode. + 7 + 1 + read-write + + + + + ARB_LOST_CAP + TWAI arbiter lost capture register. + 0x2C + 0x20 + + + ARBITRATION_LOST_CAPTURE + This register contains information about the bit position of losing arbitration. + 0 + 5 + read-only + + + + + ERR_CODE_CAP + TWAI error info capture register. + 0x30 + 0x20 + + + ERR_CAPTURE_CODE_SEGMENT + This register contains information about the location of errors on the bus. + 0 + 5 + read-only + + + ERR_CAPTURE_CODE_DIRECTION + 1: RX, error occurred during reception. 0: TX, error occurred during transmission. + 5 + 1 + read-only + + + ERR_CAPTURE_CODE_TYPE + 00: bit error. 01: form error. 10:stuff error. 11:other type of error. + 6 + 2 + read-only + + + + + ERR_WARNING_LIMIT + TWAI error threshold configuration register. + 0x34 + 0x20 + 0x00000060 + + + ERR_WARNING_LIMIT + The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + RX_ERR_CNT + Rx error counter register. + 0x38 + 0x20 + + + RX_ERR_CNT + The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + TX_ERR_CNT + Tx error counter register. + 0x3C + 0x20 + + + TX_ERR_CNT + The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + 0 + 8 + read-write + + + + + DATA_0 + Data register 0. + 0x40 + 0x20 + + + DATA_0 + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0. + 0 + 8 + read-write + + + + + DATA_1 + Data register 1. + 0x44 + 0x20 + + + DATA_1 + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1. + 0 + 8 + read-write + + + + + DATA_2 + Data register 2. + 0x48 + 0x20 + + + DATA_2 + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2. + 0 + 8 + read-write + + + + + DATA_3 + Data register 3. + 0x4C + 0x20 + + + DATA_3 + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3. + 0 + 8 + read-write + + + + + DATA_4 + Data register 4. + 0x50 + 0x20 + + + DATA_4 + In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4. + 0 + 8 + read-write + + + + + DATA_5 + Data register 5. + 0x54 + 0x20 + + + DATA_5 + In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5. + 0 + 8 + read-write + + + + + DATA_6 + Data register 6. + 0x58 + 0x20 + + + DATA_6 + In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6. + 0 + 8 + read-write + + + + + DATA_7 + Data register 7. + 0x5C + 0x20 + + + DATA_7 + In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7. + 0 + 8 + read-write + + + + + DATA_8 + Data register 8. + 0x60 + 0x20 + + + DATA_8 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8. + 0 + 8 + read-write + + + + + DATA_9 + Data register 9. + 0x64 + 0x20 + + + DATA_9 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9. + 0 + 8 + read-write + + + + + DATA_10 + Data register 10. + 0x68 + 0x20 + + + DATA_10 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10. + 0 + 8 + read-write + + + + + DATA_11 + Data register 11. + 0x6C + 0x20 + + + DATA_11 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11. + 0 + 8 + read-write + + + + + DATA_12 + Data register 12. + 0x70 + 0x20 + + + DATA_12 + In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12. + 0 + 8 + read-write + + + + + RX_MESSAGE_COUNTER + Received message counter register. + 0x74 + 0x20 + + + RX_MESSAGE_COUNTER + Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. + 0 + 7 + read-only + + + + + CLOCK_DIVIDER + Clock divider register. + 0x7C + 0x20 + + + CD + These bits are used to define the frequency at the external CLKOUT pin. + 0 + 8 + read-write + + + CLOCK_OFF + 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode. + 8 + 1 + read-write + + + + + SW_STANDBY_CFG + Software configure standby pin directly. + 0x80 + 0x20 + 0x00000002 + + + SW_STANDBY_EN + Enable standby pin. + 0 + 1 + read-write + + + SW_STANDBY_CLR + Clear standby pin. + 1 + 1 + read-write + + + + + HW_CFG + Hardware configure standby pin. + 0x84 + 0x20 + + + HW_STANDBY_EN + Enable function that hardware control standby pin. + 0 + 1 + read-write + + + + + HW_STANDBY_CNT + Configure standby counter. + 0x88 + 0x20 + 0x00000001 + + + STANDBY_WAIT_CNT + Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled. + 0 + 32 + read-write + + + + + IDLE_INTR_CNT + Configure idle interrupt counter. + 0x8C + 0x20 + 0x00000001 + + + IDLE_INTR_CNT + Configure the number of cycles before triggering idle interrupt. + 0 + 32 + read-write + + + + + ECO_CFG + ECO configuration register. + 0x90 + 0x20 + 0x00000002 + + + RDN_ENA + Enable eco module. + 0 + 1 + read-write + + + RDN_RESULT + Output of eco module. + 1 + 1 + read-only + + + + + TIMESTAMP_DATA + Timestamp data register + 0x94 + 0x20 + + + TIMESTAMP_DATA + Data of timestamp of a CAN frame. + 0 + 32 + read-only + + + + + TIMESTAMP_PRESCALER + Timestamp configuration register + 0x98 + 0x20 + 0x0000001F + + + TS_DIV_NUM + Configures the clock division number of timestamp counter. + 0 + 16 + read-write + + + + + TIMESTAMP_CFG + Timestamp configuration register + 0x9C + 0x20 + + + TS_ENABLE + enable the timestamp collection function. + 0 + 1 + read-write + + + + + + + TWAI1 + Two-Wire Automotive Interface + 0x500D8000 + + TWAI1 + 41 + + + + TWAI2 + Two-Wire Automotive Interface + 0x500D9000 + + TWAI2 + 42 + + + + UART0 + UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + UART + 0x500CA000 + + 0x0 + 0x98 + registers + + + UART0 + 31 + + + + FIFO + FIFO data register + 0x0 + 0x20 + + + RXFIFO_RD_BYTE + UART 0 accesses FIFO via this register. + 0 + 8 + read-only + + + + + INT_RAW + Raw interrupt status + 0x4 + 0x20 + 0x00000002 + + + RXFIFO_FULL_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_RAW + This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + 1 + 1 + read-write + + + PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error in the data. + 2 + 1 + read-write + + + FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error . + 3 + 1 + read-write + + + RXFIFO_OVF_INT_RAW + This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + 4 + 1 + read-write + + + DSR_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + 5 + 1 + read-write + + + CTS_CHG_INT_RAW + This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + 6 + 1 + read-write + + + BRK_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_RAW + This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + 8 + 1 + read-write + + + SW_XON_INT_RAW + This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + 9 + 1 + read-write + + + SW_XOFF_INT_RAW + This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + 10 + 1 + read-write + + + GLITCH_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + 13 + 1 + read-write + + + TX_DONE_INT_RAW + This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_RAW + This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + 16 + 1 + read-write + + + RS485_CLASH_INT_RAW + This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_RAW + This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + 18 + 1 + read-write + + + WAKEUP_INT_RAW + This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + 19 + 1 + read-write + + + + + INT_ST + Masked interrupt status + 0x8 + 0x20 + + + RXFIFO_FULL_INT_ST + This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + 0 + 1 + read-only + + + TXFIFO_EMPTY_INT_ST + This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + 1 + 1 + read-only + + + PARITY_ERR_INT_ST + This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + 2 + 1 + read-only + + + FRM_ERR_INT_ST + This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + 3 + 1 + read-only + + + RXFIFO_OVF_INT_ST + This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + 4 + 1 + read-only + + + DSR_CHG_INT_ST + This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + 5 + 1 + read-only + + + CTS_CHG_INT_ST + This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + 6 + 1 + read-only + + + BRK_DET_INT_ST + This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + 7 + 1 + read-only + + + RXFIFO_TOUT_INT_ST + This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + 8 + 1 + read-only + + + SW_XON_INT_ST + This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + 9 + 1 + read-only + + + SW_XOFF_INT_ST + This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + 10 + 1 + read-only + + + GLITCH_DET_INT_ST + This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + 11 + 1 + read-only + + + TX_BRK_DONE_INT_ST + This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + 12 + 1 + read-only + + + TX_BRK_IDLE_DONE_INT_ST + This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + 13 + 1 + read-only + + + TX_DONE_INT_ST + This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + 14 + 1 + read-only + + + RS485_PARITY_ERR_INT_ST + This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + 15 + 1 + read-only + + + RS485_FRM_ERR_INT_ST + This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + 16 + 1 + read-only + + + RS485_CLASH_INT_ST + This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + 17 + 1 + read-only + + + AT_CMD_CHAR_DET_INT_ST + This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + 18 + 1 + read-only + + + WAKEUP_INT_ST + This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + 19 + 1 + read-only + + + + + INT_ENA + Interrupt enable bits + 0xC + 0x20 + + + RXFIFO_FULL_INT_ENA + This is the enable bit for rxfifo_full_int_st register. + 0 + 1 + read-write + + + TXFIFO_EMPTY_INT_ENA + This is the enable bit for txfifo_empty_int_st register. + 1 + 1 + read-write + + + PARITY_ERR_INT_ENA + This is the enable bit for parity_err_int_st register. + 2 + 1 + read-write + + + FRM_ERR_INT_ENA + This is the enable bit for frm_err_int_st register. + 3 + 1 + read-write + + + RXFIFO_OVF_INT_ENA + This is the enable bit for rxfifo_ovf_int_st register. + 4 + 1 + read-write + + + DSR_CHG_INT_ENA + This is the enable bit for dsr_chg_int_st register. + 5 + 1 + read-write + + + CTS_CHG_INT_ENA + This is the enable bit for cts_chg_int_st register. + 6 + 1 + read-write + + + BRK_DET_INT_ENA + This is the enable bit for brk_det_int_st register. + 7 + 1 + read-write + + + RXFIFO_TOUT_INT_ENA + This is the enable bit for rxfifo_tout_int_st register. + 8 + 1 + read-write + + + SW_XON_INT_ENA + This is the enable bit for sw_xon_int_st register. + 9 + 1 + read-write + + + SW_XOFF_INT_ENA + This is the enable bit for sw_xoff_int_st register. + 10 + 1 + read-write + + + GLITCH_DET_INT_ENA + This is the enable bit for glitch_det_int_st register. + 11 + 1 + read-write + + + TX_BRK_DONE_INT_ENA + This is the enable bit for tx_brk_done_int_st register. + 12 + 1 + read-write + + + TX_BRK_IDLE_DONE_INT_ENA + This is the enable bit for tx_brk_idle_done_int_st register. + 13 + 1 + read-write + + + TX_DONE_INT_ENA + This is the enable bit for tx_done_int_st register. + 14 + 1 + read-write + + + RS485_PARITY_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 15 + 1 + read-write + + + RS485_FRM_ERR_INT_ENA + This is the enable bit for rs485_parity_err_int_st register. + 16 + 1 + read-write + + + RS485_CLASH_INT_ENA + This is the enable bit for rs485_clash_int_st register. + 17 + 1 + read-write + + + AT_CMD_CHAR_DET_INT_ENA + This is the enable bit for at_cmd_char_det_int_st register. + 18 + 1 + read-write + + + WAKEUP_INT_ENA + This is the enable bit for uart_wakeup_int_st register. + 19 + 1 + read-write + + + + + INT_CLR + Interrupt clear bits + 0x10 + 0x20 + + + RXFIFO_FULL_INT_CLR + Set this bit to clear the rxfifo_full_int_raw interrupt. + 0 + 1 + write-only + + + TXFIFO_EMPTY_INT_CLR + Set this bit to clear txfifo_empty_int_raw interrupt. + 1 + 1 + write-only + + + PARITY_ERR_INT_CLR + Set this bit to clear parity_err_int_raw interrupt. + 2 + 1 + write-only + + + FRM_ERR_INT_CLR + Set this bit to clear frm_err_int_raw interrupt. + 3 + 1 + write-only + + + RXFIFO_OVF_INT_CLR + Set this bit to clear rxfifo_ovf_int_raw interrupt. + 4 + 1 + write-only + + + DSR_CHG_INT_CLR + Set this bit to clear the dsr_chg_int_raw interrupt. + 5 + 1 + write-only + + + CTS_CHG_INT_CLR + Set this bit to clear the cts_chg_int_raw interrupt. + 6 + 1 + write-only + + + BRK_DET_INT_CLR + Set this bit to clear the brk_det_int_raw interrupt. + 7 + 1 + write-only + + + RXFIFO_TOUT_INT_CLR + Set this bit to clear the rxfifo_tout_int_raw interrupt. + 8 + 1 + write-only + + + SW_XON_INT_CLR + Set this bit to clear the sw_xon_int_raw interrupt. + 9 + 1 + write-only + + + SW_XOFF_INT_CLR + Set this bit to clear the sw_xoff_int_raw interrupt. + 10 + 1 + write-only + + + GLITCH_DET_INT_CLR + Set this bit to clear the glitch_det_int_raw interrupt. + 11 + 1 + write-only + + + TX_BRK_DONE_INT_CLR + Set this bit to clear the tx_brk_done_int_raw interrupt.. + 12 + 1 + write-only + + + TX_BRK_IDLE_DONE_INT_CLR + Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + 13 + 1 + write-only + + + TX_DONE_INT_CLR + Set this bit to clear the tx_done_int_raw interrupt. + 14 + 1 + write-only + + + RS485_PARITY_ERR_INT_CLR + Set this bit to clear the rs485_parity_err_int_raw interrupt. + 15 + 1 + write-only + + + RS485_FRM_ERR_INT_CLR + Set this bit to clear the rs485_frm_err_int_raw interrupt. + 16 + 1 + write-only + + + RS485_CLASH_INT_CLR + Set this bit to clear the rs485_clash_int_raw interrupt. + 17 + 1 + write-only + + + AT_CMD_CHAR_DET_INT_CLR + Set this bit to clear the at_cmd_char_det_int_raw interrupt. + 18 + 1 + write-only + + + WAKEUP_INT_CLR + Set this bit to clear the uart_wakeup_int_raw interrupt. + 19 + 1 + write-only + + + + + CLKDIV_SYNC + Clock divider configuration + 0x14 + 0x20 + 0x000002B6 + + + CLKDIV + The integral part of the frequency divider factor. + 0 + 12 + read-write + + + CLKDIV_FRAG + The decimal part of the frequency divider factor. + 20 + 4 + read-write + + + + + RX_FILT + Rx Filter configuration + 0x18 + 0x20 + 0x00000008 + + + GLITCH_FILT + when input pulse width is lower than this value the pulse is ignored. + 0 + 8 + read-write + + + GLITCH_FILT_EN + Set this bit to enable Rx signal filter. + 8 + 1 + read-write + + + + + STATUS + UART status register + 0x1C + 0x20 + 0xE000C000 + + + RXFIFO_CNT + Stores the byte number of valid data in Rx-FIFO. + 0 + 8 + read-only + + + DSRN + The register represent the level value of the internal uart dsr signal. + 13 + 1 + read-only + + + CTSN + This register represent the level value of the internal uart cts signal. + 14 + 1 + read-only + + + RXD + This register represent the level value of the internal uart rxd signal. + 15 + 1 + read-only + + + TXFIFO_CNT + Stores the byte number of data in Tx-FIFO. + 16 + 8 + read-only + + + DTRN + This bit represents the level of the internal uart dtr signal. + 29 + 1 + read-only + + + RTSN + This bit represents the level of the internal uart rts signal. + 30 + 1 + read-only + + + TXD + This bit represents the level of the internal uart txd signal. + 31 + 1 + read-only + + + + + CONF0_SYNC + a + 0x20 + 0x20 + 0x0000001C + + + PARITY + This register is used to configure the parity check mode. + 0 + 1 + read-write + + + PARITY_EN + Set this bit to enable uart parity check. + 1 + 1 + read-write + + + BIT_NUM + This register is used to set the length of data. + 2 + 2 + read-write + + + STOP_BIT_NUM + This register is used to set the length of stop bit. + 4 + 2 + read-write + + + TXD_BRK + Set this bit to enbale transmitter to send NULL when the process of sending data is done. + 6 + 1 + read-write + + + IRDA_DPLX + Set this bit to enable IrDA loopback mode. + 7 + 1 + read-write + + + IRDA_TX_EN + This is the start enable bit for IrDA transmitter. + 8 + 1 + read-write + + + IRDA_WCTL + 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. + 9 + 1 + read-write + + + IRDA_TX_INV + Set this bit to invert the level of IrDA transmitter. + 10 + 1 + read-write + + + IRDA_RX_INV + Set this bit to invert the level of IrDA receiver. + 11 + 1 + read-write + + + LOOPBACK + Set this bit to enable uart loopback test mode. + 12 + 1 + read-write + + + TX_FLOW_EN + Set this bit to enable flow control function for transmitter. + 13 + 1 + read-write + + + IRDA_EN + Set this bit to enable IrDA protocol. + 14 + 1 + read-write + + + RXD_INV + Set this bit to inverse the level value of uart rxd signal. + 15 + 1 + read-write + + + TXD_INV + Set this bit to inverse the level value of uart txd signal. + 16 + 1 + read-write + + + DIS_RX_DAT_OVF + Disable UART Rx data overflow detect. + 17 + 1 + read-write + + + ERR_WR_MASK + 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. + 18 + 1 + read-write + + + AUTOBAUD_EN + This is the enable bit for detecting baudrate. + 19 + 1 + read-write + + + MEM_CLK_EN + UART memory clock gate enable signal. + 20 + 1 + read-write + + + SW_RTS + This register is used to configure the software rts signal which is used in software flow control. + 21 + 1 + read-write + + + RXFIFO_RST + Set this bit to reset the uart receive-FIFO. + 22 + 1 + read-write + + + TXFIFO_RST + Set this bit to reset the uart transmit-FIFO. + 23 + 1 + read-write + + + + + CONF1 + Configuration register 1 + 0x24 + 0x20 + 0x00006060 + + + RXFIFO_FULL_THRHD + It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + 0 + 8 + read-write + + + TXFIFO_EMPTY_THRHD + It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + 8 + 8 + read-write + + + CTS_INV + Set this bit to inverse the level value of uart cts signal. + 16 + 1 + read-write + + + DSR_INV + Set this bit to inverse the level value of uart dsr signal. + 17 + 1 + read-write + + + RTS_INV + Set this bit to inverse the level value of uart rts signal. + 18 + 1 + read-write + + + DTR_INV + Set this bit to inverse the level value of uart dtr signal. + 19 + 1 + read-write + + + SW_DTR + This register is used to configure the software dtr signal which is used in software flow control. + 20 + 1 + read-write + + + CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 21 + 1 + read-write + + + + + HWFC_CONF_SYNC + Hardware flow-control configuration + 0x2C + 0x20 + + + RX_FLOW_THRHD + This register is used to configure the maximum amount of data that can be received when hardware flow control works. + 0 + 8 + read-write + + + RX_FLOW_EN + This is the flow enable bit for UART receiver. + 8 + 1 + read-write + + + + + SLEEP_CONF0 + UART sleep configure register 0 + 0x30 + 0x20 + + + WK_CHAR1 + This register restores the specified wake up char1 to wake up + 0 + 8 + read-write + + + WK_CHAR2 + This register restores the specified wake up char2 to wake up + 8 + 8 + read-write + + + WK_CHAR3 + This register restores the specified wake up char3 to wake up + 16 + 8 + read-write + + + WK_CHAR4 + This register restores the specified wake up char4 to wake up + 24 + 8 + read-write + + + + + SLEEP_CONF1 + UART sleep configure register 1 + 0x34 + 0x20 + + + WK_CHAR0 + This register restores the specified char0 to wake up + 0 + 8 + read-write + + + + + SLEEP_CONF2 + UART sleep configure register 2 + 0x38 + 0x20 + 0x001404F0 + + + ACTIVE_THRESHOLD + The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + 0 + 10 + read-write + + + RX_WAKE_UP_THRHD + In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + 10 + 8 + read-write + + + WK_CHAR_NUM + This register is used to select number of wake up char. + 18 + 3 + read-write + + + WK_CHAR_MASK + This register is used to mask wake up char. + 21 + 5 + read-write + + + WK_MODE_SEL + This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than + 26 + 2 + read-write + + + + + SWFC_CONF0_SYNC + Software flow-control character configuration + 0x3C + 0x20 + 0x00001311 + + + XON_CHAR + This register stores the Xon flow control char. + 0 + 8 + read-write + + + XOFF_CHAR + This register stores the Xoff flow control char. + 8 + 8 + read-write + + + XON_XOFF_STILL_SEND + In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. + 16 + 1 + read-write + + + SW_FLOW_CON_EN + Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + 17 + 1 + read-write + + + XONOFF_DEL + Set this bit to remove flow control char from the received data. + 18 + 1 + read-write + + + FORCE_XON + Set this bit to enable the transmitter to go on sending data. + 19 + 1 + read-write + + + FORCE_XOFF + Set this bit to stop the transmitter from sending data. + 20 + 1 + read-write + + + SEND_XON + Set this bit to send Xon char. It is cleared by hardware automatically. + 21 + 1 + read-write + + + SEND_XOFF + Set this bit to send Xoff char. It is cleared by hardware automatically. + 22 + 1 + read-write + + + + + SWFC_CONF1 + Software flow-control character configuration + 0x40 + 0x20 + 0x0000E000 + + + XON_THRESHOLD + When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + 0 + 8 + read-write + + + XOFF_THRESHOLD + When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + 8 + 8 + read-write + + + + + TXBRK_CONF_SYNC + Tx Break character configuration + 0x44 + 0x20 + 0x0000000A + + + TX_BRK_NUM + This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + 0 + 8 + read-write + + + + + IDLE_CONF_SYNC + Frame-end idle configuration + 0x48 + 0x20 + 0x00040100 + + + RX_IDLE_THRHD + It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + 0 + 10 + read-write + + + TX_IDLE_NUM + This register is used to configure the duration time between transfers. + 10 + 10 + read-write + + + + + RS485_CONF_SYNC + RS485 mode configuration + 0x4C + 0x20 + + + RS485_EN + Set this bit to choose the rs485 mode. + 0 + 1 + read-write + + + DL0_EN + Set this bit to delay the stop bit by 1 bit. + 1 + 1 + read-write + + + DL1_EN + Set this bit to delay the stop bit by 1 bit. + 2 + 1 + read-write + + + RS485TX_RX_EN + Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + 3 + 1 + read-write + + + RS485RXBY_TX_EN + 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. + 4 + 1 + read-write + + + RS485_RX_DLY_NUM + This register is used to delay the receiver's internal data signal. + 5 + 1 + read-write + + + RS485_TX_DLY_NUM + This register is used to delay the transmitter's internal data signal. + 6 + 4 + read-write + + + + + AT_CMD_PRECNT_SYNC + Pre-sequence timing configuration + 0x50 + 0x20 + 0x00000901 + + + PRE_IDLE_NUM + This register is used to configure the idle duration time before the first at_cmd is received by receiver. + 0 + 16 + read-write + + + + + AT_CMD_POSTCNT_SYNC + Post-sequence timing configuration + 0x54 + 0x20 + 0x00000901 + + + POST_IDLE_NUM + This register is used to configure the duration time between the last at_cmd and the next data. + 0 + 16 + read-write + + + + + AT_CMD_GAPTOUT_SYNC + Timeout configuration + 0x58 + 0x20 + 0x0000000B + + + RX_GAP_TOUT + This register is used to configure the duration time between the at_cmd chars. + 0 + 16 + read-write + + + + + AT_CMD_CHAR_SYNC + AT escape sequence detection configuration + 0x5C + 0x20 + 0x0000032B + + + AT_CMD_CHAR + This register is used to configure the content of at_cmd char. + 0 + 8 + read-write + + + CHAR_NUM + This register is used to configure the num of continuous at_cmd chars received by receiver. + 8 + 8 + read-write + + + + + MEM_CONF + UART memory power configuration + 0x60 + 0x20 + + + MEM_FORCE_PD + Set this bit to force power down UART memory. + 25 + 1 + read-write + + + MEM_FORCE_PU + Set this bit to force power up UART memory. + 26 + 1 + read-write + + + + + TOUT_CONF_SYNC + UART threshold and allocation configuration + 0x64 + 0x20 + 0x00000028 + + + RX_TOUT_EN + This is the enble bit for uart receiver's timeout function. + 0 + 1 + read-write + + + RX_TOUT_FLOW_DIS + Set this bit to stop accumulating idle_cnt when hardware flow control works. + 1 + 1 + read-write + + + RX_TOUT_THRHD + This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + 2 + 10 + read-write + + + + + MEM_TX_STATUS + Tx-SRAM write and read offset address. + 0x68 + 0x20 + + + TX_SRAM_WADDR + This register stores the offset write address in Tx-SRAM. + 0 + 8 + read-only + + + TX_SRAM_RADDR + This register stores the offset read address in Tx-SRAM. + 9 + 8 + read-only + + + + + MEM_RX_STATUS + Rx-SRAM write and read offset address. + 0x6C + 0x20 + 0x00010080 + + + RX_SRAM_RADDR + This register stores the offset read address in RX-SRAM. + 0 + 8 + read-only + + + RX_SRAM_WADDR + This register stores the offset write address in Rx-SRAM. + 9 + 8 + read-only + + + + + FSM_STATUS + UART transmit and receive status. + 0x70 + 0x20 + + + ST_URX_OUT + This is the status register of receiver. + 0 + 4 + read-only + + + ST_UTX_OUT + This is the status register of transmitter. + 4 + 4 + read-only + + + + + POSPULSE + Autobaud high pulse register + 0x74 + 0x20 + 0x00000FFF + + + POSEDGE_MIN_CNT + This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + NEGPULSE + Autobaud low pulse register + 0x78 + 0x20 + 0x00000FFF + + + NEGEDGE_MIN_CNT + This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + 0 + 12 + read-only + + + + + LOWPULSE + Autobaud minimum low pulse duration register + 0x7C + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + HIGHPULSE + Autobaud minimum high pulse duration register + 0x80 + 0x20 + 0x00000FFF + + + MIN_CNT + This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + 0 + 12 + read-only + + + + + RXD_CNT + Autobaud edge change count register + 0x84 + 0x20 + + + RXD_EDGE_CNT + This register stores the count of rxd edge change. It is used in baud rate-detect process. + 0 + 10 + read-only + + + + + CLK_CONF + UART core clock configuration + 0x88 + 0x20 + 0x03000000 + + + TX_SCLK_EN + Set this bit to enable UART Tx clock. + 24 + 1 + read-write + + + RX_SCLK_EN + Set this bit to enable UART Rx clock. + 25 + 1 + read-write + + + TX_RST_CORE + Write 1 then write 0 to this bit to reset UART Tx. + 26 + 1 + read-write + + + RX_RST_CORE + Write 1 then write 0 to this bit to reset UART Rx. + 27 + 1 + read-write + + + + + DATE + UART Version register + 0x8C + 0x20 + 0x02305050 + + + DATE + This is the version register. + 0 + 32 + read-write + + + + + AFIFO_STATUS + UART AFIFO Status + 0x90 + 0x20 + 0x0000000A + + + TX_AFIFO_FULL + Full signal of APB TX AFIFO. + 0 + 1 + read-only + + + TX_AFIFO_EMPTY + Empty signal of APB TX AFIFO. + 1 + 1 + read-only + + + RX_AFIFO_FULL + Full signal of APB RX AFIFO. + 2 + 1 + read-only + + + RX_AFIFO_EMPTY + Empty signal of APB RX AFIFO. + 3 + 1 + read-only + + + + + REG_UPDATE + UART Registers Configuration Update register + 0x98 + 0x20 + + + REG_UPDATE + Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + 0 + 1 + read-write + + + + + ID + UART ID register + 0x9C + 0x20 + 0x00000500 + + + ID + This register is used to configure the uart_id. + 0 + 32 + read-write + + + + + + + UHCI0 + Universal Host Controller Interface 0 + UHCI + 0x500DF000 + + 0x0 + 0x84 + registers + + + UHCI0 + 30 + + + + CONF0 + UHCI Configuration Register0 + 0x0 + 0x20 + 0x000006E0 + + + TX_RST + Write 1 then write 0 to this bit to reset decode state machine. + 0 + 1 + read-write + + + RX_RST + Write 1 then write 0 to this bit to reset encode state machine. + 1 + 1 + read-write + + + UART_SEL + Select which uart to connect with GDMA. + 2 + 3 + read-write + + + SEPER_EN + Set this bit to separate the data frame using a special char. + 5 + 1 + read-write + + + HEAD_EN + Set this bit to encode the data packet with a formatting header. + 6 + 1 + read-write + + + CRC_REC_EN + Set this bit to enable UHCI to receive the 16 bit CRC. + 7 + 1 + read-write + + + UART_IDLE_EOF_EN + If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state. + 8 + 1 + read-write + + + LEN_EOF_EN + If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received. + 9 + 1 + read-write + + + ENCODE_CRC_EN + Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + 10 + 1 + read-write + + + CLK_EN + 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. + 11 + 1 + read-write + + + UART_RX_BRK_EOF_EN + If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART. + 12 + 1 + read-write + + + + + INT_RAW + UHCI Interrupt Raw Register + 0x4 + 0x20 + + + RX_START_INT_RAW + Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully. + 0 + 1 + read-write + + + TX_START_INT_RAW + Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter. + 1 + 1 + read-write + + + RX_HUNG_INT_RAW + Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value. + 2 + 1 + read-write + + + TX_HUNG_INT_RAW + Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_RAW + Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_RAW + Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode. + 5 + 1 + read-write + + + OUT_EOF_INT_RAW + Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF. + 6 + 1 + read-write + + + APP_CTRL0_INT_RAW + Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1. + 7 + 1 + read-write + + + APP_CTRL1_INT_RAW + Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1. + 8 + 1 + read-write + + + + + INT_ST + UHCI Interrupt Status Register + 0x8 + 0x20 + + + RX_START_INT_ST + Indicates the interrupt status of UHCI_RX_START_INT. + 0 + 1 + read-only + + + TX_START_INT_ST + Indicates the interrupt status of UHCI_TX_START_INT. + 1 + 1 + read-only + + + RX_HUNG_INT_ST + Indicates the interrupt status of UHCI_RX_HUNG_INT. + 2 + 1 + read-only + + + TX_HUNG_INT_ST + Indicates the interrupt status of UHCI_TX_HUNG_INT. + 3 + 1 + read-only + + + SEND_S_REG_Q_INT_ST + Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + read-only + + + SEND_A_REG_Q_INT_ST + Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + read-only + + + OUTLINK_EOF_ERR_INT_ST + Indicates the interrupt status of UHCI_OUT_EOF_INT. + 6 + 1 + read-only + + + APP_CTRL0_INT_ST + Indicates the interrupt status of UHCI_APP_CTRL0_INT. + 7 + 1 + read-only + + + APP_CTRL1_INT_ST + Indicates the interrupt status of UHCI_APP_CTRL1_INT. + 8 + 1 + read-only + + + + + INT_ENA + UHCI Interrupt Enable Register + 0xC + 0x20 + + + RX_START_INT_ENA + Set this bit to enable the interrupt of UHCI_RX_START_INT. + 0 + 1 + read-write + + + TX_START_INT_ENA + Set this bit to enable the interrupt of UHCI_TX_START_INT. + 1 + 1 + read-write + + + RX_HUNG_INT_ENA + Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + 2 + 1 + read-write + + + TX_HUNG_INT_ENA + Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + 3 + 1 + read-write + + + SEND_S_REG_Q_INT_ENA + Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + read-write + + + SEND_A_REG_Q_INT_ENA + Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + read-write + + + OUTLINK_EOF_ERR_INT_ENA + Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + 6 + 1 + read-write + + + APP_CTRL0_INT_ENA + Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + 7 + 1 + read-write + + + APP_CTRL1_INT_ENA + Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + 8 + 1 + read-write + + + + + INT_CLR + UHCI Interrupt Clear Register + 0x10 + 0x20 + + + RX_START_INT_CLR + Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + 0 + 1 + write-only + + + TX_START_INT_CLR + Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + 1 + 1 + write-only + + + RX_HUNG_INT_CLR + Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + 2 + 1 + write-only + + + TX_HUNG_INT_CLR + Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + 3 + 1 + write-only + + + SEND_S_REG_Q_INT_CLR + Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + 4 + 1 + write-only + + + SEND_A_REG_Q_INT_CLR + Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + 5 + 1 + write-only + + + OUTLINK_EOF_ERR_INT_CLR + Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + 6 + 1 + write-only + + + APP_CTRL0_INT_CLR + Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + 7 + 1 + write-only + + + APP_CTRL1_INT_CLR + Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + 8 + 1 + write-only + + + + + CONF1 + UHCI Configuration Register1 + 0x14 + 0x20 + 0x00000033 + + + CHECK_SUM_EN + Set this bit to enable head checksum check when receiving. + 0 + 1 + read-write + + + CHECK_SEQ_EN + Set this bit to enable sequence number check when receiving. + 1 + 1 + read-write + + + CRC_DISABLE + Set this bit to support CRC calculation, and data integrity check bit should 1. + 2 + 1 + read-write + + + SAVE_HEAD + Set this bit to save data packet head when UHCI receive data. + 3 + 1 + read-write + + + TX_CHECK_SUM_RE + Set this bit to encode data packet with checksum. + 4 + 1 + read-write + + + TX_ACK_NUM_RE + Set this bit to encode data packet with ACK when reliable data packet is ready. + 5 + 1 + read-write + + + WAIT_SW_START + Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + 7 + 1 + read-write + + + SW_START + Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + 8 + 1 + write-only + + + + + STATE0 + UHCI Receive Status Register + 0x18 + 0x20 + + + RX_ERR_CAUSE + Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is not found, but received packet is completed. 3'b110: CRC check error. + 0 + 3 + read-only + + + DECODE_STATE + Indicates UHCI decoder status. + 3 + 3 + read-only + + + + + STATE1 + UHCI Transmit Status Register + 0x1C + 0x20 + + + ENCODE_STATE + Indicates UHCI encoder status. + 0 + 3 + read-only + + + + + ESCAPE_CONF + UHCI Escapes Configuration Register0 + 0x20 + 0x20 + 0x00000033 + + + TX_C0_ESC_EN + Set this bit to enable resolve char 0xC0 when DMA receiving data. + 0 + 1 + read-write + + + TX_DB_ESC_EN + Set this bit to enable resolve char 0xDB when DMA receiving data. + 1 + 1 + read-write + + + TX_11_ESC_EN + Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + 2 + 1 + read-write + + + TX_13_ESC_EN + Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + 3 + 1 + read-write + + + RX_C0_ESC_EN + Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + 4 + 1 + read-write + + + RX_DB_ESC_EN + Set this bit to enable replacing 0xDB with special char when DMA receiving data. + 5 + 1 + read-write + + + RX_11_ESC_EN + Set this bit to enable replacing 0x11 with special char when DMA receiving data. + 6 + 1 + read-write + + + RX_13_ESC_EN + Set this bit to enable replacing 0x13 with special char when DMA receiving data. + 7 + 1 + read-write + + + + + HUNG_CONF + UHCI Hung Configuration Register0 + 0x24 + 0x20 + 0x00810810 + + + TXFIFO_TIMEOUT + Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data. + 0 + 8 + read-write + + + TXFIFO_TIMEOUT_SHIFT + Configures the maximum counter value. + 8 + 3 + read-write + + + TXFIFO_TIMEOUT_ENA + Set this bit to enable TX FIFO timeout when receiving. + 11 + 1 + read-write + + + RXFIFO_TIMEOUT + Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data. + 12 + 8 + read-write + + + RXFIFO_TIMEOUT_SHIFT + Configures the maximum counter value. + 20 + 3 + read-write + + + RXFIFO_TIMEOUT_ENA + Set this bit to enable TX FIFO timeout when DMA sending data. + 23 + 1 + read-write + + + + + ACK_NUM + UHCI Ack Value Configuration Register0 + 0x28 + 0x20 + + + ACK_NUM + Indicates the ACK number during software flow control. + 0 + 3 + read-write + + + LOAD + Set this bit to load the ACK value of UHCI_ACK_NUM. + 3 + 1 + write-only + + + + + RX_HEAD + UHCI Head Register + 0x2C + 0x20 + + + RX_HEAD + Stores the head of received packet. + 0 + 32 + read-only + + + + + QUICK_SENT + UCHI Quick send Register + 0x30 + 0x20 + + + SINGLE_SEND_NUM + Configures single_send mode. + 0 + 3 + read-write + + + SINGLE_SEND_EN + Set this bit to enable sending short packet with single_send mode. + 3 + 1 + write-only + + + ALWAYS_SEND_NUM + Configures always_send mode. + 4 + 3 + read-write + + + ALWAYS_SEND_EN + Set this bit to enable sending short packet with always_send mode. + 7 + 1 + read-write + + + + + REG_Q0_WORD0 + UHCI Q0_WORD0 Quick Send Register + 0x34 + 0x20 + + + SEND_Q0_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q0_WORD1 + UHCI Q0_WORD1 Quick Send Register + 0x38 + 0x20 + + + SEND_Q0_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD0 + UHCI Q1_WORD0 Quick Send Register + 0x3C + 0x20 + + + SEND_Q1_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q1_WORD1 + UHCI Q1_WORD1 Quick Send Register + 0x40 + 0x20 + + + SEND_Q1_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD0 + UHCI Q2_WORD0 Quick Send Register + 0x44 + 0x20 + + + SEND_Q2_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q2_WORD1 + UHCI Q2_WORD1 Quick Send Register + 0x48 + 0x20 + + + SEND_Q2_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD0 + UHCI Q3_WORD0 Quick Send Register + 0x4C + 0x20 + + + SEND_Q3_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q3_WORD1 + UHCI Q3_WORD1 Quick Send Register + 0x50 + 0x20 + + + SEND_Q3_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD0 + UHCI Q4_WORD0 Quick Send Register + 0x54 + 0x20 + + + SEND_Q4_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q4_WORD1 + UHCI Q4_WORD1 Quick Send Register + 0x58 + 0x20 + + + SEND_Q4_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD0 + UHCI Q5_WORD0 Quick Send Register + 0x5C + 0x20 + + + SEND_Q5_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q5_WORD1 + UHCI Q5_WORD1 Quick Send Register + 0x60 + 0x20 + + + SEND_Q5_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD0 + UHCI Q6_WORD0 Quick Send Register + 0x64 + 0x20 + + + SEND_Q6_WORD0 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + REG_Q6_WORD1 + UHCI Q6_WORD1 Quick Send Register + 0x68 + 0x20 + + + SEND_Q6_WORD1 + Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + 0 + 32 + read-write + + + + + ESC_CONF0 + UHCI Escapes Sequence Configuration Register0 + 0x6C + 0x20 + 0x00DCDBC0 + + + SEPER_CHAR + Configures the delimiter for encoding, default value is 0xC0. + 0 + 8 + read-write + + + SEPER_ESC_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + SEPER_ESC_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDC. + 16 + 8 + read-write + + + + + ESC_CONF1 + UHCI Escapes Sequence Configuration Register1 + 0x70 + 0x20 + 0x00DDDBDB + + + ESC_SEQ0 + Configures the char needing encoding, which is 0xDB as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ0_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ0_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDD. + 16 + 8 + read-write + + + + + ESC_CONF2 + UHCI Escapes Sequence Configuration Register2 + 0x74 + 0x20 + 0x00DEDB11 + + + ESC_SEQ1 + Configures the char needing encoding, which is 0x11 as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ1_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ1_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDE. + 16 + 8 + read-write + + + + + ESC_CONF3 + UHCI Escapes Sequence Configuration Register3 + 0x78 + 0x20 + 0x00DFDB13 + + + ESC_SEQ2 + Configures the char needing encoding, which is 0x13 as flow control char by default. + 0 + 8 + read-write + + + ESC_SEQ2_CHAR0 + Configures the first char of SLIP escape character, default value is 0xDB. + 8 + 8 + read-write + + + ESC_SEQ2_CHAR1 + Configures the second char of SLIP escape character, default value is 0xDF. + 16 + 8 + read-write + + + + + PKT_THRES + UCHI Packet Length Configuration Register + 0x7C + 0x20 + 0x00000080 + + + PKT_THRS + Configures the data packet's maximum length when UHCI_HEAD_EN is 0. + 0 + 13 + read-write + + + + + DATE + UHCI Version Register + 0x80 + 0x20 + 0x02201100 + + + DATE + Configures version. + 0 + 32 + read-write + + + + + + + USB_DEVICE + Full-speed USB Serial/JTAG Controller + USB_DEVICE + 0x500D2000 + + 0x0 + 0x8C + registers + + + USB_DEVICE + 22 + + + + EP1 + FIFO access for the CDC-ACM data IN and OUT endpoints. + 0x0 + 0x20 + + + USB_SERIAL_JTAG_RDWR_BYTE + Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. + 0 + 8 + read-only + + + + + EP1_CONF + Configuration and control registers for the CDC-ACM FIFOs. + 0x4 + 0x20 + 0x00000002 + + + USB_SERIAL_JTAG_WR_DONE + Set this bit to indicate writing byte data to UART Tx FIFO is done. + 0 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE + 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL + 1'b1: Indicate there is data in UART Rx FIFO. + 2 + 1 + read-only + + + + + INT_RAW + Interrupt raw status register. + 0x8 + 0x20 + 0x00000008 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW + The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SOF_INT_RAW + The raw interrupt bit turns to high level when SOF frame is received. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW + The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW + The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_PID_ERR_INT_RAW + The raw interrupt bit turns to high level when pid error is detected. + 4 + 1 + read-write + + + USB_SERIAL_JTAG_CRC5_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC5 error is detected. + 5 + 1 + read-write + + + USB_SERIAL_JTAG_CRC16_ERR_INT_RAW + The raw interrupt bit turns to high level when CRC16 error is detected. + 6 + 1 + read-write + + + USB_SERIAL_JTAG_STUFF_ERR_INT_RAW + The raw interrupt bit turns to high level when stuff error is detected. + 7 + 1 + read-write + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW + The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW + The raw interrupt bit turns to high level when usb bus reset is detected. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW + The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_RTS_CHG_INT_RAW + The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_DTR_CHG_INT_RAW + The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of GET LINE CODING request is received. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW + The raw interrupt bit turns to high level when level of SET LINE CODING request is received. + 15 + 1 + read-write + + + + + INT_ST + Interrupt status register. + 0xC + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST + The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_SOF_INT_ST + The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST + The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_PID_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_ST + The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST + The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST + The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST + The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_ST + The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST + The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-only + + + + + INT_ENA + Interrupt enable status register. + 0x10 + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA + The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SOF_INT_ENA + The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA + The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_PID_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + read-write + + + USB_SERIAL_JTAG_CRC5_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + read-write + + + USB_SERIAL_JTAG_CRC16_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + read-write + + + USB_SERIAL_JTAG_STUFF_ERR_INT_ENA + The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + read-write + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA + The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA + The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA + The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_RTS_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_DTR_CHG_INT_ENA + The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA + The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + read-write + + + + + INT_CLR + Interrupt clear status register. + 0x14 + 0x20 + + + USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + 0 + 1 + write-only + + + USB_SERIAL_JTAG_SOF_INT_CLR + Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + 1 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + 2 + 1 + write-only + + + USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR + Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + 3 + 1 + write-only + + + USB_SERIAL_JTAG_PID_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + 4 + 1 + write-only + + + USB_SERIAL_JTAG_CRC5_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + 5 + 1 + write-only + + + USB_SERIAL_JTAG_CRC16_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + 6 + 1 + write-only + + + USB_SERIAL_JTAG_STUFF_ERR_INT_CLR + Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + 7 + 1 + write-only + + + USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR + Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + 8 + 1 + write-only + + + USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR + Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + 9 + 1 + write-only + + + USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + 10 + 1 + write-only + + + USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR + Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + 11 + 1 + write-only + + + USB_SERIAL_JTAG_RTS_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + 12 + 1 + write-only + + + USB_SERIAL_JTAG_DTR_CHG_INT_CLR + Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + 13 + 1 + write-only + + + USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + 14 + 1 + write-only + + + USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR + Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + 15 + 1 + write-only + + + + + CONF0 + PHY hardware configuration. + 0x18 + 0x20 + 0x00004200 + + + USB_SERIAL_JTAG_PHY_SEL + Select internal/external PHY + 0 + 1 + read-write + + + USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE + Enable software control USB D+ D- exchange + 1 + 1 + read-write + + + USB_SERIAL_JTAG_EXCHG_PINS + USB D+ D- exchange + 2 + 1 + read-write + + + USB_SERIAL_JTAG_VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV + 3 + 2 + read-write + + + USB_SERIAL_JTAG_VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV + 5 + 2 + read-write + + + USB_SERIAL_JTAG_VREF_OVERRIDE + Enable software control input threshold + 7 + 1 + read-write + + + USB_SERIAL_JTAG_PAD_PULL_OVERRIDE + Enable software control USB D+ D- pullup pulldown + 8 + 1 + read-write + + + USB_SERIAL_JTAG_DP_PULLUP + Control USB D+ pull up. + 9 + 1 + read-write + + + USB_SERIAL_JTAG_DP_PULLDOWN + Control USB D+ pull down. + 10 + 1 + read-write + + + USB_SERIAL_JTAG_DM_PULLUP + Control USB D- pull up. + 11 + 1 + read-write + + + USB_SERIAL_JTAG_DM_PULLDOWN + Control USB D- pull down. + 12 + 1 + read-write + + + USB_SERIAL_JTAG_PULLUP_VALUE + Control pull up value. + 13 + 1 + read-write + + + USB_SERIAL_JTAG_USB_PAD_ENABLE + Enable USB pad function. + 14 + 1 + read-write + + + USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN + Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. + 15 + 1 + read-write + + + + + TEST + Registers used for debugging the PHY. + 0x1C + 0x20 + 0x00000030 + + + USB_SERIAL_JTAG_TEST_ENABLE + Enable test of the USB pad + 0 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_USB_OE + USB pad oen in test + 1 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_TX_DP + USB D+ tx value in test + 2 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_TX_DM + USB D- tx value in test + 3 + 1 + read-write + + + USB_SERIAL_JTAG_TEST_RX_RCV + USB RCV value in test + 4 + 1 + read-only + + + USB_SERIAL_JTAG_TEST_RX_DP + USB D+ rx value in test + 5 + 1 + read-only + + + USB_SERIAL_JTAG_TEST_RX_DM + USB D- rx value in test + 6 + 1 + read-only + + + + + JFIFO_ST + JTAG FIFO status and control registers. + 0x20 + 0x20 + 0x00000044 + + + USB_SERIAL_JTAG_IN_FIFO_CNT + JTAT in fifo counter. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_EMPTY + 1: JTAG in fifo is empty. + 2 + 1 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_FULL + 1: JTAG in fifo is full. + 3 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_CNT + JTAT out fifo counter. + 4 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_EMPTY + 1: JTAG out fifo is empty. + 6 + 1 + read-only + + + USB_SERIAL_JTAG_OUT_FIFO_FULL + 1: JTAG out fifo is full. + 7 + 1 + read-only + + + USB_SERIAL_JTAG_IN_FIFO_RESET + Write 1 to reset JTAG in fifo. + 8 + 1 + read-write + + + USB_SERIAL_JTAG_OUT_FIFO_RESET + Write 1 to reset JTAG out fifo. + 9 + 1 + read-write + + + + + FRAM_NUM + Last received SOF frame index register. + 0x24 + 0x20 + + + USB_SERIAL_JTAG_SOF_FRAME_INDEX + Frame index of received SOF frame. + 0 + 11 + read-only + + + + + IN_EP0_ST + Control IN endpoint status information. + 0x28 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP0_STATE + State of IN Endpoint 0. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP0_WR_ADDR + Write data address of IN endpoint 0. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP0_RD_ADDR + Read data address of IN endpoint 0. + 9 + 7 + read-only + + + + + IN_EP1_ST + CDC-ACM IN endpoint status information. + 0x2C + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP1_STATE + State of IN Endpoint 1. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP1_WR_ADDR + Write data address of IN endpoint 1. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP1_RD_ADDR + Read data address of IN endpoint 1. + 9 + 7 + read-only + + + + + IN_EP2_ST + CDC-ACM interrupt IN endpoint status information. + 0x30 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP2_STATE + State of IN Endpoint 2. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP2_WR_ADDR + Write data address of IN endpoint 2. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP2_RD_ADDR + Read data address of IN endpoint 2. + 9 + 7 + read-only + + + + + IN_EP3_ST + JTAG IN endpoint status information. + 0x34 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_IN_EP3_STATE + State of IN Endpoint 3. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_IN_EP3_WR_ADDR + Write data address of IN endpoint 3. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_IN_EP3_RD_ADDR + Read data address of IN endpoint 3. + 9 + 7 + read-only + + + + + OUT_EP0_ST + Control OUT endpoint status information. + 0x38 + 0x20 + + + USB_SERIAL_JTAG_OUT_EP0_STATE + State of OUT Endpoint 0. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP0_WR_ADDR + Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP0_RD_ADDR + Read data address of OUT endpoint 0. + 9 + 7 + read-only + + + + + OUT_EP1_ST + CDC-ACM OUT endpoint status information. + 0x3C + 0x20 + + + USB_SERIAL_JTAG_OUT_EP1_STATE + State of OUT Endpoint 1. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_WR_ADDR + Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_RD_ADDR + Read data address of OUT endpoint 1. + 9 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT + Data count in OUT endpoint 1 when one packet is received. + 16 + 7 + read-only + + + + + OUT_EP2_ST + JTAG OUT endpoint status information. + 0x40 + 0x20 + + + USB_SERIAL_JTAG_OUT_EP2_STATE + State of OUT Endpoint 2. + 0 + 2 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_WR_ADDR + Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. + 2 + 7 + read-only + + + USB_SERIAL_JTAG_OUT_EP2_RD_ADDR + Read data address of OUT endpoint 2. + 9 + 7 + read-only + + + + + MISC_CONF + Clock enable control + 0x44 + 0x20 + + + USB_SERIAL_JTAG_CLK_EN + 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. + 0 + 1 + read-write + + + + + MEM_CONF + Memory power control + 0x48 + 0x20 + 0x00000002 + + + USB_SERIAL_JTAG_USB_MEM_PD + 1: power down usb memory. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_USB_MEM_CLK_EN + 1: Force clock on for usb memory. + 1 + 1 + read-write + + + + + CHIP_RST + CDC-ACM chip reset control. + 0x4C + 0x20 + + + USB_SERIAL_JTAG_RTS + 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_DTR + 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. + 1 + 1 + read-only + + + USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS + Set this bit to disable chip reset from usb serial channel to reset chip. + 2 + 1 + read-write + + + + + SET_LINE_CODE_W0 + W0 of SET_LINE_CODING command. + 0x50 + 0x20 + + + USB_SERIAL_JTAG_DW_DTE_RATE + The value of dwDTERate set by host through SET_LINE_CODING command. + 0 + 32 + read-only + + + + + SET_LINE_CODE_W1 + W1 of SET_LINE_CODING command. + 0x54 + 0x20 + + + USB_SERIAL_JTAG_BCHAR_FORMAT + The value of bCharFormat set by host through SET_LINE_CODING command. + 0 + 8 + read-only + + + USB_SERIAL_JTAG_BPARITY_TYPE + The value of bParityTpye set by host through SET_LINE_CODING command. + 8 + 8 + read-only + + + USB_SERIAL_JTAG_BDATA_BITS + The value of bDataBits set by host through SET_LINE_CODING command. + 16 + 8 + read-only + + + + + GET_LINE_CODE_W0 + W0 of GET_LINE_CODING command. + 0x58 + 0x20 + + + USB_SERIAL_JTAG_GET_DW_DTE_RATE + The value of dwDTERate set by software which is requested by GET_LINE_CODING command. + 0 + 32 + read-write + + + + + GET_LINE_CODE_W1 + W1 of GET_LINE_CODING command. + 0x5C + 0x20 + + + USB_SERIAL_JTAG_GET_BDATA_BITS + The value of bCharFormat set by software which is requested by GET_LINE_CODING command. + 0 + 8 + read-write + + + USB_SERIAL_JTAG_GET_BPARITY_TYPE + The value of bParityTpye set by software which is requested by GET_LINE_CODING command. + 8 + 8 + read-write + + + USB_SERIAL_JTAG_GET_BCHAR_FORMAT + The value of bDataBits set by software which is requested by GET_LINE_CODING command. + 16 + 8 + read-write + + + + + CONFIG_UPDATE + Configuration registers' value update + 0x60 + 0x20 + + + USB_SERIAL_JTAG_CONFIG_UPDATE + Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. + 0 + 1 + write-only + + + + + SER_AFIFO_CONFIG + Serial AFIFO configure register + 0x64 + 0x20 + 0x00000010 + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR + Write 1 to reset CDC_ACM IN async FIFO write clock domain. + 0 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD + Write 1 to reset CDC_ACM IN async FIFO read clock domain. + 1 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR + Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + 2 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD + Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + 3 + 1 + read-write + + + USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY + CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + 4 + 1 + read-only + + + USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL + CDC_ACM OUT IN async FIFO empty signal in write clock domain. + 5 + 1 + read-only + + + + + BUS_RESET_ST + USB Bus reset status register + 0x68 + 0x20 + 0x00000001 + + + USB_SERIAL_JTAG_USB_BUS_RESET_ST + USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released. + 0 + 1 + read-only + + + + + ECO_LOW_48 + Reserved. + 0x6C + 0x20 + + + USB_SERIAL_JTAG_RND_ECO_LOW_48 + Reserved. + 0 + 32 + read-write + + + + + ECO_HIGH_48 + Reserved. + 0x70 + 0x20 + 0xFFFFFFFF + + + USB_SERIAL_JTAG_RND_ECO_HIGH_48 + Reserved. + 0 + 32 + read-write + + + + + ECO_CELL_CTRL_48 + Reserved. + 0x74 + 0x20 + + + USB_SERIAL_JTAG_RDN_RESULT_48 + Reserved. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_RDN_ENA_48 + Reserved. + 1 + 1 + read-write + + + + + ECO_LOW_APB + Reserved. + 0x78 + 0x20 + + + USB_SERIAL_JTAG_RND_ECO_LOW_APB + Reserved. + 0 + 32 + read-write + + + + + ECO_HIGH_APB + Reserved. + 0x7C + 0x20 + 0xFFFFFFFF + + + USB_SERIAL_JTAG_RND_ECO_HIGH_APB + Reserved. + 0 + 32 + read-write + + + + + ECO_CELL_CTRL_APB + Reserved. + 0x80 + 0x20 + + + USB_SERIAL_JTAG_RDN_RESULT_APB + Reserved. + 0 + 1 + read-only + + + USB_SERIAL_JTAG_RDN_ENA_APB + Reserved. + 1 + 1 + read-write + + + + + SRAM_CTRL + PPA SRAM Control Register + 0x84 + 0x20 + 0x00001320 + + + USB_SERIAL_JTAG_MEM_AUX_CTRL + Control signals + 0 + 14 + read-write + + + + + DATE + Date register + 0x88 + 0x20 + 0x02112010 + + + USB_SERIAL_JTAG_DATE + register version. + 0 + 32 + read-write + + + + + + + USB_WRAP + USB_WRAP Peripheral + USB_WRAP + 0x50080000 + + 0x0 + 0xC + registers + + + + OTG_CONF + USB wrapper configuration registers. + 0x0 + 0x20 + 0x00100000 + + + SRP_SESSEND_OVERRIDE + This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input, 1'b1: the signal is controlled by the software. + 0 + 1 + read-write + + + SRP_SESSEND_VALUE + Software over-ride value of srp session end signal. + 1 + 1 + read-write + + + PHY_SEL + Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY. + 2 + 1 + read-write + + + DFIFO_FORCE_PD + Force the dfifo to go into low power mode. The data in dfifo will not lost. + 3 + 1 + read-write + + + DBNCE_FLTR_BYPASS + Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals + 4 + 1 + read-write + + + EXCHG_PINS_OVERRIDE + Enable software controlle USB D+ D- exchange + 5 + 1 + read-write + + + EXCHG_PINS + USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-. + 6 + 1 + read-write + + + VREFH + Control single-end input high threshold,1.76V to 2V, step 80mV. + 7 + 2 + read-write + + + VREFL + Control single-end input low threshold,0.8V to 1.04V, step 80mV. + 9 + 2 + read-write + + + VREF_OVERRIDE + Enable software controlle input threshold. + 11 + 1 + read-write + + + PAD_PULL_OVERRIDE + Enable software controlle USB D+ D- pullup pulldown. + 12 + 1 + read-write + + + DP_PULLUP + Controlle USB D+ pullup. + 13 + 1 + read-write + + + DP_PULLDOWN + Controlle USB D+ pulldown. + 14 + 1 + read-write + + + DM_PULLUP + Controlle USB D+ pullup. + 15 + 1 + read-write + + + DM_PULLDOWN + Controlle USB D+ pulldown. + 16 + 1 + read-write + + + PULLUP_VALUE + Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K. + 17 + 1 + read-write + + + USB_PAD_ENABLE + Enable USB pad function. + 18 + 1 + read-write + + + AHB_CLK_FORCE_ON + Force ahb clock always on. + 19 + 1 + read-write + + + PHY_CLK_FORCE_ON + Force phy clock always on. + 20 + 1 + read-write + + + PHY_TX_EDGE_SEL + Select phy tx signal output clock edge. 1'b0: negedge, 1'b1: posedge. + 21 + 1 + read-write + + + DFIFO_FORCE_PU + Disable the dfifo to go into low power mode. The data in dfifo will not lost. + 22 + 1 + read-write + + + CLK_EN + Disable auto clock gating of CSR registers. + 31 + 1 + read-write + + + + + TEST_CONF + USB wrapper test configuration registers. + 0x4 + 0x20 + + + TEST_ENABLE + Enable test of the USB pad. + 0 + 1 + read-write + + + TEST_USB_OE + USB pad oen in test. + 1 + 1 + read-write + + + TEST_TX_DP + USB D+ tx value in test. + 2 + 1 + read-write + + + TEST_TX_DM + USB D- tx value in test. + 3 + 1 + read-write + + + TEST_RX_RCV + USB differential rx value in test. + 4 + 1 + read-only + + + TEST_RX_DP + USB D+ rx value in test. + 5 + 1 + read-only + + + TEST_RX_DM + USB D- rx value in test. + 6 + 1 + read-only + + + + + DATE + Date register. + 0x3FC + 0x20 + 0x23030504 + + + USB_WRAP_DATE + Date register. + 0 + 32 + read-only + + + + + + + \ No newline at end of file